diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 2ce3afa911471..62d156b1f97f0 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -123,7 +123,7 @@ jobs: strategy: matrix: - boards: [arm-01, arm-02, arm-03, arm-04, arm-05, arm-06, arm-07, arm-08, arm-09, arm-10, arm-11, arm-12, arm-13, other, risc-v, sim-01, sim-02, xtensa, codechecker] + boards: [arm-01, arm-02, arm-03, arm-04, arm-05, arm-06, arm-07, arm-08, arm-09, arm-10, arm-11, arm-12, arm-13, other, risc-v, sim-01, sim-02, xtensa] steps: - name: Download Source Artifact @@ -192,12 +192,12 @@ jobs: - name: Restore Tools Cache id: cache-tools - uses: actions/cache@v3 + uses: actions/cache@v4 env: cache-name: ${{ runner.os }}-cache-tools with: path: ./sources/tools - key: ${{ runner.os }}-tools-${{ hashFiles('./sources/nuttx/tools/ci/cibuild.sh') }} + key: ${{ runner.os }}-tools-${{ hashFiles('./sources/nuttx/tools/ci/platforms/darwin.sh') }} - name: Export NuttX Repo SHA run: echo "nuttx_sha=`git -C sources/nuttx rev-parse HEAD`" >> $GITHUB_ENV @@ -219,3 +219,71 @@ jobs: name: macos-builds path: buildartifacts/ continue-on-error: true + + msys2: + needs: Fetch-Source + runs-on: windows-latest + strategy: + fail-fast: false + matrix: + boards: [msys2] + + defaults: + run: + shell: msys2 {0} + steps: + - uses: actions/checkout@v4 + - uses: msys2/setup-msys2@v2 + with: + msystem: MSYS + update: false + install: >- + base-devel + gcc + gperf + automake + autoconf + git + python3 + ncurses-devel + unzip + zip + tio + zlib-devel + cmake + ninja + python-pip + vim + + - name: pip3 install + run: | + pip3 install --root-user-action=ignore --no-cache-dir pyelftools cxxfilt kconfiglib + + - run: git config --global core.autocrlf false + + - name: Download Source Artifact + uses: actions/download-artifact@v3 + with: + name: source-bundle + path: . + + - name: Extract sources + run: tar zxf sources.tar.gz + + - name: Export NuttX Repo SHA + run: echo "nuttx_sha=`git -C sources/nuttx rev-parse HEAD`" >> $GITHUB_ENV + + - name: Run Builds + run: | + echo "::add-matcher::sources/nuttx/.github/gcc.json" + export ARTIFACTDIR=`pwd`/buildartifacts + git config --global --add safe.directory /github/workspace/sources/nuttx + git config --global --add safe.directory /github/workspace/sources/apps + cd sources/nuttx/tools/ci + ./cibuild.sh -g -i -A -C -R testlist/${{matrix.boards}}.dat + + - uses: actions/upload-artifact@v3 + with: + name: msys2-builds + path: buildartifacts/ + continue-on-error: true diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml index b7c1070be4bb5..8da61e8cf4982 100644 --- a/.github/workflows/lint.yml +++ b/.github/workflows/lint.yml @@ -22,7 +22,7 @@ jobs: fetch-depth: 0 - run: mkdir super-linter.report - name: Lint - uses: github/super-linter@v5 + uses: github/super-linter@v6 env: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} VALIDATE_ALL_CODEBASE: false diff --git a/.gitignore b/.gitignore index 34e29b22642f1..5f21c69b3072c 100644 --- a/.gitignore +++ b/.gitignore @@ -58,7 +58,10 @@ uImage .context\ * # $(TOPDIR)/Makefile.[unix|win]::$(DIRLINKS_EXTERNAL_DIRS) .dirlinks +.fakelnk .vscode .DS_Store tools/gdb/__pycache__ /build +.ccls-cache +compile_commands.json diff --git a/CMakeLists.txt b/CMakeLists.txt index 80f03424ad588..dba8ace983af0 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -48,7 +48,6 @@ endif() # Basic CMake configuration ################################################## -set(CMAKE_CXX_STANDARD 14) set(CMAKE_CXX_EXTENSIONS OFF) list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/cmake) set(CMAKE_EXPORT_COMPILE_COMMANDS ON) @@ -84,7 +83,12 @@ if(NOT KCONFIGLIB) $ pip install kconfiglib") endif() -if(EXISTS ${BOARD_CONFIG} AND EXISTS ${BOARD_CONFIG}/defconfig) +# BOARD CONFIG can be set to directory path, or [/:] +# configuration pair + +if((EXISTS ${BOARD_CONFIG} AND EXISTS ${BOARD_CONFIG}/defconfig) + OR (EXISTS ${NUTTX_DIR}/${BOARD_CONFIG} + AND EXISTS ${NUTTX_DIR}/${BOARD_CONFIG}/defconfig)) get_filename_component(NUTTX_BOARD_ABS_DIR ${BOARD_CONFIG} ABSOLUTE BASE_DIR ${NUTTX_DIR}) @@ -103,7 +107,7 @@ if(EXISTS ${BOARD_CONFIG} AND EXISTS ${BOARD_CONFIG}/defconfig) string(REGEX REPLACE "(.*)/(.*)/${NUTTX_CONFIG}" "\\1" NUTTX_BOARD_DIR ${NUTTX_BOARD_ABS_DIR}) - set(NUTTX_DEFCONFIG ${BOARD_CONFIG}/defconfig) + set(NUTTX_DEFCONFIG ${NUTTX_BOARD_ABS_DIR}/defconfig) else() if(BOARD_CONFIG MATCHES "/") set(MATCH_REGEX "/") @@ -241,7 +245,7 @@ else() endif() if(NOT EXISTS ${CMAKE_BINARY_DIR}/boards/dummy/Kconfig) - if(CONFIG_ARCH_BOARD_CUSTOM) + if(CONFIG_ARCH_BOARD_CUSTOM AND EXISTS ${NUTTX_BOARD_ABS_DIR}/Kconfig) nuttx_create_symlink(${NUTTX_BOARD_ABS_DIR}/Kconfig ${CMAKE_BINARY_DIR}/boards/dummy/Kconfig) else() @@ -278,7 +282,7 @@ if(NOT EXISTS ${CMAKE_BINARY_DIR}/arch/dummy) endif() if(NOT EXISTS ${CMAKE_BINARY_DIR}/arch/dummy/Kconfig) - if(CONFIG_ARCH_CHIP_CUSTOM) + if(CONFIG_ARCH_CHIP_CUSTOM AND EXISTS ${NUTTX_CHIP_ABS_DIR}/Kconfig) nuttx_create_symlink(${NUTTX_CHIP_ABS_DIR}/Kconfig ${CMAKE_BINARY_DIR}/arch/dummy/Kconfig) else() @@ -372,6 +376,7 @@ include(nuttx_add_symtab) include(nuttx_add_module) include(nuttx_add_dependencies) include(nuttx_export_header) +include(nuttx_source_file_properties) include(menuconfig) include(ExternalProject) @@ -412,6 +417,14 @@ include(platform) # Setup main nuttx target #################################################### add_executable(nuttx) +if(CONFIG_BUILD_PROTECTED) + add_executable(nuttx_user) +endif() + +if(CONFIG_ALLSYMS) + include(nuttx_allsyms) +endif() + add_dependencies(nuttx nuttx_context) if(WIN32) @@ -436,6 +449,7 @@ if(CONFIG_ARCH_SIM) TARGET nuttx PROPERTY NUTTX_KERNEL_COMPILE_OPTIONS) target_compile_options(sim_head PRIVATE ${options}) + target_compile_options(sim_head PRIVATE -fvisibility=default) # We need the relocatable object to be first in the list of libraries to be # linked against final nuttx binary @@ -475,15 +489,17 @@ if(WIN32) else() add_compile_options( # system wide warnings - -Wall - $<$:-Wstrict-prototypes> - -Wshadow - -Wundef + -Wall $<$:-Wstrict-prototypes> -Wshadow -Wundef # system wide options - $<$:-nostdinc++> $<$:-D__ASSEMBLY__>) endif() +if(NOT CONFIG_LIBCXXTOOLCHAIN) + add_compile_options($<$:-nostdinc++>) +else() + add_compile_options($<$:-D_STDLIB_H_>) +endif() + if(NOT CONFIG_CXX_EXCEPTION) add_compile_options($<$:-fno-exceptions> $<$:-fcheck-new>) @@ -542,11 +558,15 @@ endif() # Add apps/ to the build (if present) -if(EXISTS ${NUTTX_APPS_DIR}/CMakeLists.txt) - add_subdirectory(${NUTTX_APPS_DIR} apps) -else() - message( - STATUS "Application directory not found at ${NUTTX_APPS_DIR}, skipping") +if(NOT CONFIG_BUILD_KERNEL) + + if(EXISTS ${NUTTX_APPS_DIR}/CMakeLists.txt) + add_subdirectory(${NUTTX_APPS_DIR} apps) + else() + message( + STATUS "Application directory not found at ${NUTTX_APPS_DIR}, skipping") + endif() + endif() # Link step ################################################################## @@ -589,11 +609,12 @@ endif() file(TOUCH ${CMAKE_BINARY_DIR}/nuttx.manifest) get_property(nuttx_kernel_libs GLOBAL PROPERTY NUTTX_KERNEL_LIBRARIES) +get_property(nuttx_extra_libs GLOBAL PROPERTY NUTTX_EXTRA_LIBRARIES) + if(CONFIG_BUILD_FLAT) get_property(nuttx_system_libs GLOBAL PROPERTY NUTTX_SYSTEM_LIBRARIES) + get_property(nuttx_apps_libs GLOBAL PROPERTY NUTTX_APPS_LIBRARIES) endif() -get_property(nuttx_apps_libs GLOBAL PROPERTY NUTTX_APPS_LIBRARIES) -get_property(nuttx_extra_libs GLOBAL PROPERTY NUTTX_EXTRA_LIBRARIES) set(nuttx_libs ${nuttx_kernel_libs} ${nuttx_system_libs} ${nuttx_apps_libs}) @@ -688,16 +709,28 @@ else() list(APPEND nuttx_libs_paths $) endforeach() - add_custom_command( - OUTPUT nuttx.rel - COMMAND - ${CMAKE_C_COMPILER} ARGS -r $<$:-m32> - $ $<$>:-Wl,--start-group> - ${nuttx_libs_paths} ${nuttx_extra_libs} - $<$>:-Wl,--end-group> -o nuttx.rel - COMMAND ${CMAKE_OBJCOPY} --redefine-syms=nuttx-names.dat nuttx.rel - DEPENDS ${nuttx_libs} ${nuttx_extra_libs} sim_head - COMMAND_EXPAND_LISTS) + if(APPLE) + add_custom_command( + OUTPUT nuttx.rel + COMMAND + ${CMAKE_LINKER} ARGS -r $<$:-m32> + $ $<$>:-Wl,--start-group> + ${nuttx_libs_paths} ${nuttx_extra_libs} + $<$>:-Wl,--end-group> -o nuttx.rel + DEPENDS ${nuttx_libs} ${nuttx_extra_libs} sim_head + COMMAND_EXPAND_LISTS) + else() + add_custom_command( + OUTPUT nuttx.rel + COMMAND + ${CMAKE_C_COMPILER} ARGS -r $<$:-m32> + $ $<$>:-Wl,--start-group> + ${nuttx_libs_paths} ${nuttx_extra_libs} + $<$>:-Wl,--end-group> -o nuttx.rel + COMMAND ${CMAKE_OBJCOPY} --redefine-syms=nuttx-names.dat nuttx.rel + DEPENDS ${nuttx_libs} ${nuttx_extra_libs} sim_head + COMMAND_EXPAND_LISTS) + endif() add_custom_target(nuttx-rel DEPENDS nuttx.rel $<$>:nuttx.ld>) @@ -714,26 +747,37 @@ endif() # Userspace portion ########################################################## -if(NOT CONFIG_BUILD_FLAT) - add_executable(nuttx_user) +if(CONFIG_BUILD_PROTECTED) get_property(nuttx_system_libs GLOBAL PROPERTY NUTTX_SYSTEM_LIBRARIES) + get_property(nuttx_apps_libs GLOBAL PROPERTY NUTTX_APPS_LIBRARIES) + get_property(user_ldscript GLOBAL PROPERTY LD_SCRIPT_USER) list(TRANSFORM user_ldscript PREPEND "-Wl,--script=") + execute_process( + COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} ${NUTTX_EXTRA_FLAGS} + --print-libgcc-file-name + OUTPUT_STRIP_TRAILING_WHITESPACE + OUTPUT_VARIABLE nuttx_user_libgcc) + + # reset link options for userspace to prevent sections from being accidentally + # deleted + set_target_properties(nuttx_user PROPERTIES LINK_OPTIONS "") + target_link_options( nuttx_user PRIVATE -nostartfiles -nodefaultlibs - -Wl,--entry=${CONFIG_USER_ENTRYPOINT} - -Wl,--undefined=${CONFIG_USER_ENTRYPOINT}) + -Wl,--entry=${CONFIG_INIT_ENTRYPOINT} + -Wl,--undefined=${CONFIG_INIT_ENTRYPOINT}) target_link_libraries( nuttx_user PRIVATE ${user_ldscript} - userspace $<$>:-Wl,--start-group> ${nuttx_system_libs} - gcc + ${nuttx_apps_libs} + ${nuttx_user_libgcc} $<$:supc++> $<$>:-Wl,--end-group>) @@ -759,3 +803,8 @@ if(NOT CONFIG_BUILD_FLAT) # TODO: could also merge elf binaries endif() + +if(CONFIG_BUILD_KERNEL) + # TODO: generate nuttx-export-xxx.tar.gz for userland development + +endif() diff --git a/Documentation/Makefile b/Documentation/Makefile index 3a691eb74191d..b82d6729e18c3 100644 --- a/Documentation/Makefile +++ b/Documentation/Makefile @@ -23,10 +23,12 @@ # You can set these variables from the command line, and also # from the environment for the first two. -SPHINXOPTS ?= -j 1 -W -A nuttx_versions="latest,${NUTTX_VERSIONS}" -SPHINXBUILD ?= sphinx-build -SOURCEDIR = . -BUILDDIR = _build +SPHINXOPTS ?= -j 1 -W -A nuttx_versions="latest,${NUTTX_VERSIONS}" +SPHINXAUTOOPTS ?= -j 8 -W +SPHINXBUILD ?= sphinx-build +SPHINXAUTOBUILD ?= sphinx-autobuild +SOURCEDIR = . +BUILDDIR = _build # Put it first so that "make" without argument is like "make help". help: @@ -37,7 +39,7 @@ help: html: clean autobuild: clean - sphinx-autobuild . _build -j=8 + @$(SPHINXAUTOBUILD) "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXAUTOOPTS) $(O) # Catch-all target: route all unknown targets to Sphinx using the new # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). diff --git a/Documentation/Pipfile.lock b/Documentation/Pipfile.lock index dc00931692b4d..8cc12d04ae6c7 100644 --- a/Documentation/Pipfile.lock +++ b/Documentation/Pipfile.lock @@ -32,92 +32,107 @@ }, "certifi": { "hashes": [ - "sha256:539cc1d13202e33ca466e88b2807e29f4c13049d6d87031a3c110744495cb082", - "sha256:92d6037539857d8206b8f6ae472e8b77db8058fec5937a1ef3f54304089edbb9" + "sha256:0569859f95fc761b18b45ef421b1290a0f65f147e92a1e5eb3e635f9a5e4e66f", + "sha256:dc383c07b76109f368f6106eee2b593b04a011ea4d55f652c6ca24a754d1cdd1" ], - "index": "pypi", - "version": "==2023.7.22" + "markers": "python_version >= '3.6'", + "version": "==2024.2.2" }, "charset-normalizer": { "hashes": [ - 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Core OS +sched +* [#10919](https://github.com/apache/nuttx/pull/10919) sched: assert: move the backtrace dump after the stack dump +* [#11195](https://github.com/apache/nuttx/pull/11195) sched: assert: restore assertion registers to array of last registers +* [#10858](https://github.com/apache/nuttx/pull/10858) sched: assert.c: Print process name in assert dump +* [#11131](https://github.com/apache/nuttx/pull/11131) sched: Check for zero sleep time and yield CPU +* [#11226](https://github.com/apache/nuttx/pull/11226) sched: delete check when pick nexttcb in readytorun list +* [#11038](https://github.com/apache/nuttx/pull/11038) sched: env_dup: fix issue about USE_AFTER_FREE +* [#11102](https://github.com/apache/nuttx/pull/11102) sched: explicitly select the cpuload clock source configuration +* [#10816](https://github.com/apache/nuttx/pull/10816) sched: Fix dependencies of CONFIG_SCHED_CPULOAD_ settings +* [#11036](https://github.com/apache/nuttx/pull/11036) sched: Follow o_cloexe semantics when calling the exec function +* [#10867](https://github.com/apache/nuttx/pull/10867) sched: format: modify spin_lock_irqsave format +* [#11018](https://github.com/apache/nuttx/pull/11018) sched: group/killchildren: replace syscall(2) to kernel api +* [#10605](https://github.com/apache/nuttx/pull/10605) sched: Implement ticket spinlock +* [#10827](https://github.com/apache/nuttx/pull/10827) sched: Improve adjtime() functionality +* [#11231](https://github.com/apache/nuttx/pull/11231) sched: lock refine: remove sched_[un]lock in xxx_waitsample +* [#11302](https://github.com/apache/nuttx/pull/11302) sched: misc/rwlock:Implementing read/write locks. +* [#11347](https://github.com/apache/nuttx/pull/11347) sched: Print more information in assert +* [#11017](https://github.com/apache/nuttx/pull/11017) sched: pthread/barrierwait: replace syscall(2) to kernel api +* [#10929](https://github.com/apache/nuttx/pull/10929) sched: Remove the unused tcb argument from group_setupidlefiles +* [#10776](https://github.com/apache/nuttx/pull/10776) sched: rw spinlock +* [#11124](https://github.com/apache/nuttx/pull/11124) sched: rw spinlocks: cosmetic changes +* [#11191](https://github.com/apache/nuttx/pull/11191) sched: sem_holder.c: When accessing SEM_WAITLIST, use holder's addrenv +* [#11257](https://github.com/apache/nuttx/pull/11257) sched: semaphore: Move POSIX regulated parts of semaphores into libc +* [#11252](https://github.com/apache/nuttx/pull/11252) sched: sigaction: Expand si_user for non-kernel signals +* [#10970](https://github.com/apache/nuttx/pull/10970) sched: smp call exit immediately when cpuset change to 0. +* [#10861](https://github.com/apache/nuttx/pull/10861) sched: spinlock: Add spin_lock_init and spin_is_locked macro +* [#11348](https://github.com/apache/nuttx/pull/11348) sched: Stack recored:Add maximum stack statistics when the task is running +* [#9163](https://github.com/apache/nuttx/pull/9163) sched: Stop the sched timer when possible to save the power in tickless mode +* [#10934](https://github.com/apache/nuttx/pull/10934) sched: support smp function call +* [#11032](https://github.com/apache/nuttx/pull/11032) sched: task: [posix]spawn: Simplify how spawn attributes are handled +* [#11241](https://github.com/apache/nuttx/pull/11241) sched: task: pthread_cancelpt: Fix nxtask_delete from another task group +* [#11165](https://github.com/apache/nuttx/pull/11165) sched: task: pthread_cancelpt: Move cancel point handling to libc, data to TLS +* [#11097](https://github.com/apache/nuttx/pull/11097) sched: task: Remove spawn_proxyattrs as obsolete implementation +* [#11177](https://github.com/apache/nuttx/pull/11177) sched: taskfiles: skip unnecessary file open/close operations to improve performance +* [#11250](https://github.com/apache/nuttx/pull/11250) sched: taskspawn: fix spawn fail if enable FDCHECK +* [#10834](https://github.com/apache/nuttx/pull/10834) sched: timer: handle perf count overflow + +mm +* [#11068](https://github.com/apache/nuttx/pull/11068) mm: both use spin_lock_irqxx() when operated delaylist +* [#11183](https://github.com/apache/nuttx/pull/11183) mm: free delay list when exceeding specified count +* [#11258](https://github.com/apache/nuttx/pull/11258) mm: kmap: Finalize kmap implementation for RISC-V +* [#10837](https://github.com/apache/nuttx/pull/10837) mm: kmap: Fix bug in kmm_unmap +* [#10876](https://github.com/apache/nuttx/pull/10876) mm: kmap: Fix several issues with the kmm_map interface +* [#11114](https://github.com/apache/nuttx/pull/11114) mm: kmap: Fix bad dependency to ARCH_VMA_MAPPING +* [#11092](https://github.com/apache/nuttx/pull/11092) mm: improve SMP performance +* [#11152](https://github.com/apache/nuttx/pull/11152) mm: record the maximum system memory usage +* [#11168](https://github.com/apache/nuttx/pull/11168) mm: Remove mm_spinlock +* [#10984](https://github.com/apache/nuttx/pull/10984) mm: Replace enter_critical_section with spin_irqsave + +libs +* [#11408](https://github.com/apache/nuttx/pull/11408) libc: add fgetwc, getwc, ungetwc wchar api implementation +* [#10602](https://github.com/apache/nuttx/pull/10602) libc: add support for custom streams with fopencookie() +* [#11011](https://github.com/apache/nuttx/pull/11011) libc: add support for memory buffer stream with fmemopen() +* [#11274](https://github.com/apache/nuttx/pull/11274) libc: add support for open_memstream +* [#11288](https://github.com/apache/nuttx/pull/11288) libc: arm: add support of PACBTI +* [#10969](https://github.com/apache/nuttx/pull/10969) libc: Change errno to set_errno and get_errno +* [#11294](https://github.com/apache/nuttx/pull/11294) libc: Fix -nan issue with f32 +* [#11198](https://github.com/apache/nuttx/pull/11198) libc: Fix improper handling of 64 bit types for libvsprintf +* [#11322](https://github.com/apache/nuttx/pull/11322) libc: Handle PCREL_HI20/LO12_I/S relocations correctly +* [#10994](https://github.com/apache/nuttx/pull/10994) libc: Improve stdio unlock version function +* [#11364](https://github.com/apache/nuttx/pull/11364) libc: lib_slcd: fix encode/decode of binary nibble to/from ascii hex +* [#11035](https://github.com/apache/nuttx/pull/11035) libc: localtime: fix the timezone error caused by minor error +* [#11281](https://github.com/apache/nuttx/pull/11281) libc: machine/arm: align related implementations of armv7 architecture +* [#10927](https://github.com/apache/nuttx/pull/10927) libc: machine: Remove FAR from sparc +* [#11133](https://github.com/apache/nuttx/pull/11133) libc: realpath: allocate link buffer of pseudofs to save stack +* [#10913](https://github.com/apache/nuttx/pull/10913) libc: Refine the implementation of fopen/fdopen +* [#10993](https://github.com/apache/nuttx/pull/10993) libc: Remove the unused lib_libdtoa.c +* [#11137](https://github.com/apache/nuttx/pull/11137) libc: Solve some problems encountered during cmake compilation +* [#10992](https://github.com/apache/nuttx/pull/10992) libc: stdio: Change FILE buffer field from "unsigned char *" to "char *" +* [#11063](https://github.com/apache/nuttx/pull/11063) libc: stdlib/lib_exit.c: fix multiple definition of __dso_handle and sethost.sh: add MSYS environmen for msys2 +* [#11447](https://github.com/apache/nuttx/pull/11447) libc: stream: add stream interface +* [#11350](https://github.com/apache/nuttx/pull/11350) libc: Support gdbstub kernal debugging +* [#11346](https://github.com/apache/nuttx/pull/11346) libc: Supports storing coredump into block devices +* [#10862](https://github.com/apache/nuttx/pull/10862) libc: memfd: shm_unlink or unlink anonymous file +* [#10891](https://github.com/apache/nuttx/pull/10891) libc: memfd: turn a runtime error into a linker error +* [#10972](https://github.com/apache/nuttx/pull/10972) libds: add missing observer_b16.c to cmake build +* [#10915](https://github.com/apache/nuttx/pull/10915) libdsp: lib_observer.c: use float numbers for some calculations +* [#10979](https://github.com/apache/nuttx/pull/10979) libdsp: update LP_FILTER comment +* [#11256](https://github.com/apache/nuttx/pull/11256) libm: Fix an issue that public header files are not exported +* [#11162](https://github.com/apache/nuttx/pull/11162) libm: newlib: Change the download site to https +* [#11386](https://github.com/apache/nuttx/pull/11386) libs: log2ceil: Move implementation of log2ceil to a common place +* [#11043](https://github.com/apache/nuttx/pull/11043) libs: modlib: optimize code and add arch api for allocating data section +* [#11394](https://github.com/apache/nuttx/pull/11394) libxx: cmake: remove useless code +* [#11050](https://github.com/apache/nuttx/pull/11050) libxx: Silence warnings when building libcxx. +* [#11301](https://github.com/apache/nuttx/pull/11301) libxx: upgrade llvm version to 17.0.6 +* [#10860](https://github.com/apache/nuttx/pull/10860) libxx: Use gnu++20 option only if using libcxx +misc +* [#11242](https://github.com/apache/nuttx/pull/11242) Revert "libc/lib_bzero:Add bzero prototype." +* [#10881](https://github.com/apache/nuttx/pull/10881) arm, arm64, xtensa, libxx: Change sed -r to sed -E to support macOS +* [#11027](https://github.com/apache/nuttx/pull/11027) assert: rename __ASSERT to __ASSERT__ to avoid conflict +* [#11025](https://github.com/apache/nuttx/pull/11025) audio: add amr format support +* [#11055](https://github.com/apache/nuttx/pull/11055) binfmt/elf: Select ARCH_USE_TEXT_HEAP if ARCH_HAVE_TEXT_HEAP +* [#11238](https://github.com/apache/nuttx/pull/11238) clock.h: use CONFIG_DEBUG_SCHED to test init ticks +* [#10924](https://github.com/apache/nuttx/pull/10924) crypto/rsa_verify: export rsa verify via /dev/crypto +* [#10978](https://github.com/apache/nuttx/pull/10978) debug/assert: decouple configuration of show file name feature +* [#10809](https://github.com/apache/nuttx/pull/10809) dma: support source/destination address auto step +* [#10870](https://github.com/apache/nuttx/pull/10870) fixedmath: add abs and sign operations +* [#11111](https://github.com/apache/nuttx/pull/11111) ioctl: add definitions related to ethtool +* [#11121](https://github.com/apache/nuttx/pull/11121) ioctl: add SIOCGIWNAME support +* [#11026](https://github.com/apache/nuttx/pull/11026) kernel: replace all sem_* to nxsem_*: in kernel space +* [#10849](https://github.com/apache/nuttx/pull/10849) langinfo: The character U+ff0c "，" could be confused with the ASCII character U… +* [#11243](https://github.com/apache/nuttx/pull/11243) list: search prev item in reverse order +* [#11221](https://github.com/apache/nuttx/pull/11221) poll: pollsetup should notify only one fd passed by caller +* [#10892](https://github.com/apache/nuttx/pull/10892) refine: move BIT Macro to nuttx/bits.h +* [#11218](https://github.com/apache/nuttx/pull/11218) spinlock: Move the inclusion of stdatomic.h to source file +* [#10869](https://github.com/apache/nuttx/pull/10869) sys/types: supporting 32-bit IDs for gid_t/uid_t +* [#11207](https://github.com/apache/nuttx/pull/11207) tcbinfo:remove total_num form tcbinfo. +* [#11298](https://github.com/apache/nuttx/pull/11298) video: Update v4l2m2m interface & create videoio.h +* [#11362](https://github.com/apache/nuttx/pull/11362) virtio.h: add virtio_has_feature api for virtio driver +Build System +Improvements +* [#11007](https://github.com/apache/nuttx/pull/11007) Revert "make/archive: Use the full path name when matching or storing… +* [#11047](https://github.com/apache/nuttx/pull/11047) applications: Move the test tools in the system to the testing +* [#11395](https://github.com/apache/nuttx/pull/11395) cmake: build file support with libcxx 17.0.6 +* [#10982](https://github.com/apache/nuttx/pull/10982) cmake: correct cmake rule file name +* [#11375](https://github.com/apache/nuttx/pull/11375) cmake: fix NUTTX_COMMON_DIR +* [#11031](https://github.com/apache/nuttx/pull/11031) cmake: init RISC-V cmake qemu-rv build +* [#10843](https://github.com/apache/nuttx/pull/10843) cmake: raise error if previous make build was not cleaned +* [#10879](https://github.com/apache/nuttx/pull/10879) fix: TreeNode has same attribute with NodeMixin +* [#10968](https://github.com/apache/nuttx/pull/10968) nuttx: generate nuttx.map file when enable debug link map. +* [#11303](https://github.com/apache/nuttx/pull/11303) sh: Enhanced compilation system +* [#11432](https://github.com/apache/nuttx/pull/11432) tools: config.mk: whether verbosity is enabled or not, should use bash +* [#11098](https://github.com/apache/nuttx/pull/11098) tools: configure.c and tools/sethost.sh Add CONFIG_EXPERIMENTAL for configure windows native +Architectural Support +New Architecture Support +* [#11319](https://github.com/apache/nuttx/pull/11319) arm:imxrt: Add support for imxrt1170 Soc and imxrt1170-evk board +* [#11371](https://github.com/apache/nuttx/pull/11371) riscv: Add support for Bouffalo Lab BL808 SoC (T-Head C906) + +Architecture Improvements +* [#10836](https://github.com/apache/nuttx/pull/10836) arch: add a flag indicating that the chip doesn't support DMA transfer from/to FLASH +* [#10759](https://github.com/apache/nuttx/pull/10759) arch: add use_data to g_tcbinfo +* [#11190](https://github.com/apache/nuttx/pull/11190) arch: dumponexit: unify dump on exit to common code +* [#10828](https://github.com/apache/nuttx/pull/10828) arch: simplify ARCH_PERF_EVENTS related code +* [#11160](https://github.com/apache/nuttx/pull/11160) arch: textheap: add _heapmember declare for text and data heap +arm + * [#11282](https://github.com/apache/nuttx/pull/11282) clang: replace deprecated parameter +* [#11170](https://github.com/apache/nuttx/pull/11170) Let's old arm's arm_doirq return register context like armv7-a +* [#11413](https://github.com/apache/nuttx/pull/11413) debug:fix gdbstub clear fpb & dwt when already use jtag/swo bug +* [#11166](https://github.com/apache/nuttx/pull/11166) armv8-m: Fix typo error for NVIC_SYSHCON_HARDFAULTPENDED + +* [#11118](https://github.com/apache/nuttx/pull/11118) cxd56xx: Support to get gnss firmware version + +* [#11398](https://github.com/apache/nuttx/pull/11398) imxrt: Extend FlexIO support to 117x +* [#11436](https://github.com/apache/nuttx/pull/11436) imxrt: flexio move ifdef guard lower +* [#11012](https://github.com/apache/nuttx/pull/11012) imxrt: NXP I2C non-DMA end only on stop with end of packet +* [#11000](https://github.com/apache/nuttx/pull/11000) imxrt: nxp lpi2c calculated timeout can not be 0 +* [#11033](https://github.com/apache/nuttx/pull/11033) imxrt: NXP lpi2c DMA transaction only need the status conditioned +* [#11164](https://github.com/apache/nuttx/pull/11164) imxrt: NXP Serial Do not wait on TXDMA semaphore +* [#11070](https://github.com/apache/nuttx/pull/11070) imxrt: NXP Serial overcome race where DMA has not fetched TCD again +* [#11020](https://github.com/apache/nuttx/pull/11020) imxrt: serial Ensure the cache is updated if the DMA has updated again + +* [#11199](https://github.com/apache/nuttx/pull/11199) imx6: Replace cpu_start_t with start_t + +* [#10877](https://github.com/apache/nuttx/pull/10877) mx8mp: Add support for SPI + +* [#11203](https://github.com/apache/nuttx/pull/11203) nRF91: initial support for GNSS +* [#11308](https://github.com/apache/nuttx/pull/11308) nrf{52|53|91}: add missing support for 1 Mbps UART baud +* [#10826](https://github.com/apache/nuttx/pull/10826) nrf{52|53|91}: add support for up_perf +* [#10830](https://github.com/apache/nuttx/pull/10830) nrf{52|53|91}: fixes for timer + +* [#11172](https://github.com/apache/nuttx/pull/11172) rp2040: pwm: Fix errors at CONFIG_PWM_NCHANNELS=1 + +* [#10817](https://github.com/apache/nuttx/pull/10817) sama5: Sort SAMA5D2 adc/tsd dma +* [#10806](https://github.com/apache/nuttx/pull/10806) sama5: TSD trigger and pressure scaling issues +* [#11307](https://github.com/apache/nuttx/pull/11307) samd212: invert tx and rx in spi_dma_setup +* [#11212](https://github.com/apache/nuttx/pull/11212) samd212: sam_dmac: Fix compilation and fix SAM_DMAC_CHINTENCLR settings +* [#10855](https://github.com/apache/nuttx/pull/10855) samv7: channel gain switching in aefc +* [#11312](https://github.com/apache/nuttx/pull/11312) samv7: sam_emac: Implement errata workaround for KSZ8061 PHY + +* [#10847](https://github.com/apache/nuttx/pull/10847) {stm32|stm32f7|at32|samv7|imxrt}: fix for adc_setup +* [#11211](https://github.com/apache/nuttx/pull/11211) stm32: Add support for Ethernet packet timestamping and PTP timer +* [#11175](https://github.com/apache/nuttx/pull/11175) stm32: foc: add support for board-specific ioctl +* [#10833](https://github.com/apache/nuttx/pull/10833) stm32: Initialize LED driver during late initialization for nucleo-f446re +* [#11181](https://github.com/apache/nuttx/pull/11181) stm32: stm32/stm32_adc.c: protect irq_attach with refcounter +* [#11194](https://github.com/apache/nuttx/pull/11194) stm32: stm32_foc.c: rename some macros +* [#11194](https://github.com/apache/nuttx/pull/11194) stm32: stm32_eth: Fix excessively long critical section in ifdown handlerm +* [#10865](https://github.com/apache/nuttx/pull/10865) stm32: UART needs to be disabled before changing setup + +* [#10824](https://github.com/apache/nuttx/pull/10824) stm32l4: ADC: Adds low level operations to start and stop DMA. +* [#11154](https://github.com/apache/nuttx/pull/11154) stm32h7: serial: Do not wait on TXDMA semaphore +* [#11323](https://github.com/apache/nuttx/pull/11323) stm32h7: serial refactor out tx dma semaphore +* [#11332](https://github.com/apache/nuttx/pull/11332) stm32h7: serial Remove .txdmasem = SEM_INITIALIZER(1) bad cherry-pick +* [#10841](https://github.com/apache/nuttx/pull/10841) stm32h7: stm32_oneshot.c: Fix format warnings. +* [#11334](https://github.com/apache/nuttx/pull/11334) stm32h7: stm32h7_adc: Dynamically set clock prescaler and BOOST +* [#11367](https://github.com/apache/nuttx/pull/11367) stm32u5: fix EXTICR2,3,4 register offsets + +* [#10846](https://github.com/apache/nuttx/pull/10846) s32k1xx: Fix LPUART inversion warnings & config. +* [#10844](https://github.com/apache/nuttx/pull/10844) s32k1xx: Fix warnings in PWM code. +* [#11099](https://github.com/apache/nuttx/pull/11099) s32kxxx: flexcan doesn't set srr bit for extended frames +* [#11325](https://github.com/apache/nuttx/pull/11325) s32k3xx: NXP S32K3xx Fixes stuttering output +* [#11106](https://github.com/apache/nuttx/pull/11106) s32k3xx: serial ensure the cache is updated if the DMA has updated again +arm64 +* [#10888](https://github.com/apache/nuttx/pull/10888) Add support for FIQ interrupts +* [#11352](https://github.com/apache/nuttx/pull/11352) coredump: support arm64 coredump +* [#11200](https://github.com/apache/nuttx/pull/11200) Disable ARCH_HAVE_FORK for arm64 as a precaution +* [#11429](https://github.com/apache/nuttx/pull/11429) Fix GICv2 detection +* [#10966](https://github.com/apache/nuttx/pull/10966) Remove unnecessary code in arm64_cpu_idle.S +* [#11037](https://github.com/apache/nuttx/pull/11037) support relocate for aarch64 +* [#10917](https://github.com/apache/nuttx/pull/10917) support up_coherent_dcache function +* [#10918](https://github.com/apache/nuttx/pull/10918) target cpuid calculation error in arm64_gic_raise_sgi function +* [#11182](https://github.com/apache/nuttx/pull/11182) the bug of sscanf exception output in arm64 platform +* [#11245](https://github.com/apache/nuttx/pull/11245) vector: no need to save x0 to sp +* [#10904](https://github.com/apache/nuttx/pull/10904) XN should only be set when the attribute MT_EXECUTE_NEVER is set +risc-v +* [#10856](https://github.com/apache/nuttx/pull/10856) addrenv: utils: Determine page table flags by type of vaddr +* [#11113](https://github.com/apache/nuttx/pull/11113) addrenv: Fix static page table mapping (paddr instead of vaddr) +* [#10838](https://github.com/apache/nuttx/pull/10838) addrenv: Fix the user VMA end address +* [#10829](https://github.com/apache/nuttx/pull/10829) addrenv: Fix two SHM related issues +* [#11389](https://github.com/apache/nuttx/pull/11389) arch_elf: Check for _HI20 relocation validity +* [#11437](https://github.com/apache/nuttx/pull/11437) espressif: mcuboot: Fix dependency of the Espressif's port MCUboot. +* [#11034](https://github.com/apache/nuttx/pull/11034) espressif: Update esp-hal-3rdparty version +* [#11024](https://github.com/apache/nuttx/pull/11024) litex/litex_emac: Add support for KSZ8061 ethernet PHY. +* [#11029](https://github.com/apache/nuttx/pull/11029) litex/litex-emac: Add support for phy interrupts. +* [#11028](https://github.com/apache/nuttx/pull/11028) litex/litex_gpio: Fix ISR dispatch when using higher GPIO indexes. +* [#11365](https://github.com/apache/nuttx/pull/11365) mmu: Extend MMU Flags to 64-bit for T-Head C906 and Svpbmt +* [#11283](https://github.com/apache/nuttx/pull/11283) mpfs: corespi: Round up divider to prevent overlock of SPI +* [#10822](https://github.com/apache/nuttx/pull/10822) mpfs: corespi: Several speed optimizations to the FPGA driver +* [#10921](https://github.com/apache/nuttx/pull/10921) mpfs: ethernet: Fix RX/TX buffer and descriptor handling +* [#11405](https://github.com/apache/nuttx/pull/11405) mpfs: ethernet: Remove DMA_ENABLE hack +* [#10922](https://github.com/apache/nuttx/pull/10922) mpfs: entrypoints: Fix potential R_RISCV_JAL linker error +* [#11247](https://github.com/apache/nuttx/pull/11247) mpfs: ihc: cleanup DEBUGASSERTs and irq enabling +* [#11355](https://github.com/apache/nuttx/pull/11355) mpfs: mpfs_head.S: Change j/jal to tail call +* [#10923](https://github.com/apache/nuttx/pull/10923) mpfs: mpfs_head.S: Simplify clearing PMP +* [#11233](https://github.com/apache/nuttx/pull/11233) mpfs: opensbi: update opensbi to version 1.3.1 +* [#11404](https://github.com/apache/nuttx/pull/11404) mpfs: usb: Use kernel memory instead of user memory for DMA +* [#11403](https://github.com/apache/nuttx/pull/11403) mpfs: pmpcfg: Move PMPCFG registers to common location +* [#10875](https://github.com/apache/nuttx/pull/10875) pgalloc.h: Return kernel vaddr for kernel RAM paddr +* [#11374](https://github.com/apache/nuttx/pull/11374) riscv_pmp.c: Revert LOG2_CEIL back to run-time log2ceil function +* [#11001](https://github.com/apache/nuttx/pull/11001) Simplify PMP configuration and code +* [#11441](https://github.com/apache/nuttx/pull/11441) Update mode.h to add CSR_TVEC +sim +* [#10930](https://github.com/apache/nuttx/pull/10930) crypto: Use mbedtls default configuration without special check +* [#11381](https://github.com/apache/nuttx/pull/11381) sim_lcd: add open & close +* [#11122](https://github.com/apache/nuttx/pull/11122) sim_netdriver: some sim defconfig have problems when using the network +* [#11246](https://github.com/apache/nuttx/pull/11246) sim support 16bbp +* [#11237](https://github.com/apache/nuttx/pull/11237) simwifi: Connect the wifi whose ssid contains the special charaters. +* [#11235](https://github.com/apache/nuttx/pull/11235) simwifi: Escapes the special characters of ssid in the scan results. +* [#11069](https://github.com/apache/nuttx/pull/11069) simwifi: Fix the error of the need length for scan bssinfo. +* [#11112](https://github.com/apache/nuttx/pull/11112) simwifi: For scan results, parse and translate the Chinese ssid encoded by the wpa_cli. +* [#11066](https://github.com/apache/nuttx/pull/11066) simwifi: host wlan0 obtains ip and set dns for wlan0 in the defwan wlan0 +* [#11108](https://github.com/apache/nuttx/pull/11108) simwifi: Transfer the special characters in ssid. +* [#11104](https://github.com/apache/nuttx/pull/11104) simwifi: Support that get the connected Chinese essid. +* [#11051](https://github.com/apache/nuttx/pull/11051) simwifi: Support that simwifi connects to the hidden ssid. +* [#11171](https://github.com/apache/nuttx/pull/11171) Replace [enter|leave]_critical_section with up_irq_[save|restore] +* [#11219](https://github.com/apache/nuttx/pull/11219) Remove the wrong comment from up_allocate_heap +* [#11205](https://github.com/apache/nuttx/pull/11205) usb_rawgadget: remove halt operation +* [#10910](https://github.com/apache/nuttx/pull/10910) Update Fix more generic for platforms that do not have execinfo.h +* [#11030](https://github.com/apache/nuttx/pull/11030) wifidriver: Fix the scan error. +* [#10886](https://github.com/apache/nuttx/pull/10886) wifidriver: Support the sim wifi. +x86_64 +* [#10899](https://github.com/apache/nuttx/pull/10899) Fix idle stack assignment +xtensa +* [#11141](https://github.com/apache/nuttx/pull/11141) esp32: ble: Enable the BLE interrupt during an SPI flash operation +* [#10859](https://github.com/apache/nuttx/pull/10859) esp32: ble: Fix task_create_wrapper CPU core ID passed as argument +* [#10851](https://github.com/apache/nuttx/pull/10851) esp32: irq: Fix erroneous interrupt allocation for each CPU core +* [#11139](https://github.com/apache/nuttx/pull/11139) esp32s2: Add rtc heap support +* [#11300](https://github.com/apache/nuttx/pull/11300) esp32s2: Add RTC support +* [#11138](https://github.com/apache/nuttx/pull/11138) esp32s2: Add SPI slave support +* [#10850](https://github.com/apache/nuttx/pull/10850) esp32s2: add UART RS485 support +* [#10823](https://github.com/apache/nuttx/pull/10823) esp32s2: Add support to TWAI/CANBus controller +* [#11431](https://github.com/apache/nuttx/pull/11431) esp32s2: Add xtwdt and rwdt support +* [#10873](https://github.com/apache/nuttx/pull/10873) esp32s2: ESP32-S3 I2C improvements +* [#11259](https://github.com/apache/nuttx/pull/11259) esp32s3: Add rtc heap support +* [#11180](https://github.com/apache/nuttx/pull/11180) esp32s3: Add RWDT support +* [#11287](https://github.com/apache/nuttx/pull/11287) esp32s3: Add SPIRAM high memory support +* [#11179](https://github.com/apache/nuttx/pull/11179) esp32s3: Add XTWDT support +* [#10854](https://github.com/apache/nuttx/pull/10854) esp32s3: ble: enable the BLE interrupt during a SPI flash operation +* [#11331](https://github.com/apache/nuttx/pull/11331) esp32s3: enable LIBC_ARCH_ATOMIC +* [#11299](https://github.com/apache/nuttx/pull/11299) esp32s3: Fix esp32s3 mcuboot ota crash +* [#11136](https://github.com/apache/nuttx/pull/11136) esp32s3: Fix issue regarding IRAM-enabled ISRs by fixing the linker +* [#11285](https://github.com/apache/nuttx/pull/11285) esp32s3: Fix some ESP32S3 module reboot and QVL issues +* [#10882](https://github.com/apache/nuttx/pull/10882) esp32s3: Fix the os halt issue when esp32s3 wlan has high-speed or long time d… +* [#11427](https://github.com/apache/nuttx/pull/11427) esp32s3: Fixed bbpll not calibrated from bootloader issue +* [#11328](https://github.com/apache/nuttx/pull/11328) esp32s3: GPIO clear pending interrupt status before enable IRQ +* [#11329](https://github.com/apache/nuttx/pull/11329) esp32s3: QSPI disable DMA when sending command to slave +* [#11286](https://github.com/apache/nuttx/pull/11286) esp32s3: Invalidate cache if the flash address used has a cache mapping. +* [#11144](https://github.com/apache/nuttx/pull/11144) esp32s3: Support malloc from external RAM and internal RAM +* [#11157](https://github.com/apache/nuttx/pull/11157) esp32s3: Support multiple PHY init data bin +* [#11434](https://github.com/apache/nuttx/pull/11434) esp32s3: Support reading encrypted partitions +* [#11052](https://github.com/apache/nuttx/pull/11052) esp32s3: Support to read data from flash to PSRAM +* [#11340](https://github.com/apache/nuttx/pull/11340) esp32s3: Tasks use SPIRAM as stack can do SPI flash read/write/erase/map/unmap +* [#11428](https://github.com/apache/nuttx/pull/11428) espressif/rmt: Implement a common RMT (Remote Control) driver for xtensa-based devices. +Driver Support +New Driver Support +* [#10770](https://github.com/apache/nuttx/pull/10770) drivers: add regmap subsystems support. +* [#10902](https://github.com/apache/nuttx/pull/10902) motor: Add stepper interface +* [#11253](https://github.com/apache/nuttx/pull/11253) mtd: Adds support to W25Q20CL memory. +* [#11149](https://github.com/apache/nuttx/pull/11149) mtd: mx25rxx: add support for MX25L25673G chip +* [#11422](https://github.com/apache/nuttx/pull/11422) net: ksz9477: Add simple port-based static VLAN configuration +* [#11339](https://github.com/apache/nuttx/pull/11339) net: lan9250: Add LAN9250 driver(SPI and QSPI mode) +* [#11280](https://github.com/apache/nuttx/pull/11280) sensors: Add support for MS5607 +* [#10864](https://github.com/apache/nuttx/pull/10864) sensors: max31865:RTD-to-Digital Converter +* [#10914](https://github.com/apache/nuttx/pull/10914) stepper: add DRV8825 +* [#11228](https://github.com/apache/nuttx/pull/11228) tee: add optee client driver module +Drivers Improvements +* [#11071](https://github.com/apache/nuttx/pull/11071) Kconfigs: rename {Rpmsg|rpmsg} to RPMGS +* [#11061](https://github.com/apache/nuttx/pull/11061) can: Add new ioctls +* [#10845](https://github.com/apache/nuttx/pull/10845) foc: foc_dummy.c: update dummy device state only if dev opened +* [#11176](https://github.com/apache/nuttx/pull/11176) foc: return scaling factor for phase currents and BEMF via ioctl +* [#10808](https://github.com/apache/nuttx/pull/10808) ioexpander: Minor fix for ioexpander driver +* [#11147](https://github.com/apache/nuttx/pull/11147) lcd: add stride support for LCD driver +* [#11185](https://github.com/apache/nuttx/pull/11185) lcd: change lcd stride from pixel to bytes +* [#10926](https://github.com/apache/nuttx/pull/10926) math: mpi: add mpi driver in math +* [#11240](https://github.com/apache/nuttx/pull/11240) misc: Rpmsgblk function optimization +* [#11220](https://github.com/apache/nuttx/pull/11220) mmcsd: mmcsd_sdinitialize should save csd register into priv->csd +* [#10909](https://github.com/apache/nuttx/pull/10909) mtd: filemtd:Fix teardown return error number EINVAL +* [#11041](https://github.com/apache/nuttx/pull/11041) mtd: get mtd_geometry_s.model for mtd partition and optimize code +* [#11187](https://github.com/apache/nuttx/pull/11187) mtd: s25fl1: fix compile warnings caused by incorrect variable print format +* [#11370](https://github.com/apache/nuttx/pull/11370) mtd: w25q: add nxsig_usleep to busy waiting in w25qxxxjv_erase_sector() +* [#11391](https://github.com/apache/nuttx/pull/11391) net: qemu/wifi: Add the virtual wifi function on the emulator. +* [#11216](https://github.com/apache/nuttx/pull/11216) net: skeleton.c doesn't compile without this patch if ioctls are enabled +* [#10907](https://github.com/apache/nuttx/pull/10907) note: Change 0/1 to false/true +* [#11153](https://github.com/apache/nuttx/pull/11153) note: delete sched_note_flatten +* [#10840](https://github.com/apache/nuttx/pull/10840) note: optimize note performance +* [#10920](https://github.com/apache/nuttx/pull/10920) note: remove remaining event code +* [#11074](https://github.com/apache/nuttx/pull/11074) power: pm: use pm_staytimeout() in greedy_governor_activity() +* [#11132](https://github.com/apache/nuttx/pull/11132) rptun: check the status before stop remote proc +* [#11222](https://github.com/apache/nuttx/pull/11222) rtc: RTC driver improvement +* [#10831](https://github.com/apache/nuttx/pull/10831) rtt: make RTT console optional +* [#11296](https://github.com/apache/nuttx/pull/11296) segger: rtt: correct macro name to avoid unable to change default mode +* [#11419](https://github.com/apache/nuttx/pull/11419) sensors: mx56xx: Add support for second order compensation +* [#11426](https://github.com/apache/nuttx/pull/11426) sensors: mx56xx: Fix threshold and calculation +* [#11178](https://github.com/apache/nuttx/pull/11178) serial: uart_tcsendbreak: Remove cancel point, as tcsendbreak is not one +* [#11402](https://github.com/apache/nuttx/pull/11402) syslog: ramlog: improve ramlog performance +* [#11392](https://github.com/apache/nuttx/pull/11392) syslog: ramlog: multi readers +* [#10890](https://github.com/apache/nuttx/pull/10890) syslog: ramlog: remove sched_[un]lock and rl_nwaiters +* [#11186](https://github.com/apache/nuttx/pull/11186) timers: Rewrite adjtime() implementation to work for RTC and tickless kernel +* [#11356](https://github.com/apache/nuttx/pull/11356) usbdev: Add callback for CONFIG_USBDEV_SOFINTERRUPT +* [#11042](https://github.com/apache/nuttx/pull/11042) usbdev: config USBDEV_TRACE_INITIALIDSET when disbale USBDEV_TRACE +* [#11161](https://github.com/apache/nuttx/pull/11161) usbdev: Solve some problems of USB hotplug +* [#10985](https://github.com/apache/nuttx/pull/10985) usrsock: Make the field of usrsock_request native alignment +* [#11103](https://github.com/apache/nuttx/pull/11103) usrsock: rpmsg_server: Keep msg order in recursive call +* [#11107](https://github.com/apache/nuttx/pull/11107) usrsock: socket fallback with ENETDOWN +* [#10874](https://github.com/apache/nuttx/pull/10874) video: fb: Add fb_register_device +* [#10812](https://github.com/apache/nuttx/pull/10812) video: goldfish: Remove the vsync residual code +* [#11380](https://github.com/apache/nuttx/pull/11380) video: goldfish: optimize goldfish fb register +* [#11249](https://github.com/apache/nuttx/pull/11249) video: video.c: modify set_buf call seqence in start_capture function. +* [#11224](https://github.com/apache/nuttx/pull/11224) video: wait when the vsync queue is full in FBIO_WAITFORVSYNC +* [#11382](https://github.com/apache/nuttx/pull/11382) virtio: Support for setting MAC addresses of the virtio-net interfaces +* [#11385](https://github.com/apache/nuttx/pull/11385) virtio: virtio-gpu: convert virito-gpu fb_register to virtio_gpu_fb_register +* [#11201](https://github.com/apache/nuttx/pull/11201) virtio: Virtio Qemu 8.1.2 issues fix +* [#11013](https://github.com/apache/nuttx/pull/11013) wireless: bluetooth: Add option to set the HCI TX thread affinity while running with SMP enabled +* [#11072](https://github.com/apache/nuttx/pull/11072) wireless: bluetooth: rpmsg depends on RPTUN + +Board Support +New Board Support +arm +* [#10987](https://github.com/apache/nuttx/pull/10987) gd32f4: add gd32f470i board support +* [#11094](https://github.com/apache/nuttx/pull/11094) stm32: add support to LINUM-STM32H753BI board +* [#10990](https://github.com/apache/nuttx/pull/10990) stm32: add support to STM32F401RC-RS485 board +* [#11358](https://github.com/apache/nuttx/pull/11358) stm32h7: linum-stm32h753bi: Add modbus example using usart6 +* [#11276](https://github.com/apache/nuttx/pull/11276) seeed-xiao-rp2040: Add initial board support + +xtensa +* [#10976](https://github.com/apache/nuttx/pull/10976) Add ESP32-2432S028 board +* [#10928](https://github.com/apache/nuttx/pull/10928) esp32s3-box: Support hardware version 3 + +risc-v +* [#11379](https://github.com/apache/nuttx/pull/11379) Initial support for CanMV-k230 board +* [#11377](https://github.com/apache/nuttx/pull/11377) Add support for PINE64 Ox64 BL808 SBC + +Board Improvements +* [#11056](https://github.com/apache/nuttx/pull/11056) Modify test "ramtest" path +* [#11192](https://github.com/apache/nuttx/pull/11192) remove obsolete CONFIG_EXAMPLES_FOC_IPHASE_ADC option + +arm +* [#11101](https://github.com/apache/nuttx/pull/11101) cxd56xx: Add cxd5610 gnss driver + +* [#11373](https://github.com/apache/nuttx/pull/11373) gd32f4xx: change gd32f470z board code + +* [#11193](https://github.com/apache/nuttx/pull/11193) imx6: Fix sabre-6quad:libcxx + +* [#11310](https://github.com/apache/nuttx/pull/11310) nrf52: nrf52832-dk: add timer example +* [#10835](https://github.com/apache/nuttx/pull/10835) nrf52: remove CONFIG_ARMV7M_SYSTICK form tickless configs + +* [#11150](https://github.com/apache/nuttx/pull/11150) sama5: Add QSPI support SAMA5 +* [#11151](https://github.com/apache/nuttx/pull/11151) sama5: sama5d2-xult: add support for QSPI flash and nxffs + +* [#11117](https://github.com/apache/nuttx/pull/11117) stm32: b-g431b-esc1: don't use CONFIG_STM32_USE_LEGACY_PINMAP=y +* [#11306](https://github.com/apache/nuttx/pull/11306) stm32h7: fix config conflict +* [#11214](https://github.com/apache/nuttx/pull/11214) stm32h7: linum-stm32h753bi: Add support to RTC and alarm +* [#11167](https://github.com/apache/nuttx/pull/11167) stm32h7: linum-stm32h753bi: Added suport to userlerds library. +* [#11265](https://github.com/apache/nuttx/pull/11265) stm32f4: stm32f401rc-rs485: Add sdcard support +* [#11217](https://github.com/apache/nuttx/pull/11217) stm32f4: stm32f401rc-rs485: Add buttons support +* [#11169](https://github.com/apache/nuttx/pull/11169) stm32f4: stm32f401rc-rs485: add support to userleds +* [#11255](https://github.com/apache/nuttx/pull/11255) stm32f4: stm32f401rc-rs485: Fix f401rc flash size +risc-v +* [#10736](https://github.com/apache/nuttx/pull/10736) esp32c3: pm: Let PM_PROCFS depend on FS_PROCFS_REGISTER +* [#11418](https://github.com/apache/nuttx/pull/11418) esp32c6: Add ostest defconfig +* [#11096](https://github.com/apache/nuttx/pull/11096) mpfs: Add option for board specific PMP configuration +* [#11262](https://github.com/apache/nuttx/pull/11262) qemu-rv: rv-virt/knsh: Set correct RAM_START and RAM_SIZE +* [#11397](https://github.com/apache/nuttx/pull/11397) qemu-rv: Virtio sound +sim +* [#10960](https://github.com/apache/nuttx/pull/10960) fix Cygwin/MSYS2 ld: unrecognized option '-z' +* [#11290](https://github.com/apache/nuttx/pull/11290) nxscope: remove CONFIG_ALLSYMS=y +xtensa +* [#11142](https://github.com/apache/nuttx/pull/11142) esp32: Add LVGL defconfig +* [#11229](https://github.com/apache/nuttx/pull/11229) esp32: Add support enconder to ESP32-2432S028 +* [#10961](https://github.com/apache/nuttx/pull/10961) esp32: Add wifishare board config and documentation +* [#10996](https://github.com/apache/nuttx/pull/10996) esp32: Rename Shift game to Brickmatch and add an board example to esp32-devkitc +* [#11417](https://github.com/apache/nuttx/pull/11417) esp32<|s2|s3>_board_spiflash: Fix error message about SmartFS init +* [#11425](https://github.com/apache/nuttx/pull/11425) esp32s2: Increase init task stack size to 3072 +* [#11156](https://github.com/apache/nuttx/pull/11156) esp32s3: Link stack checking function and data to SRAM when enable flash or PSRAM driver +* [#11342](https://github.com/apache/nuttx/pull/11342) esp32s3: add esp32s3-devkit:toywasm kconfig +* [#11295](https://github.com/apache/nuttx/pull/11295) esp32s3: Add rtc defconfig +* [#10885](https://github.com/apache/nuttx/pull/10885) ESP32S3-EYE: GPIO and button support +* [#10884](https://github.com/apache/nuttx/pull/10884) ESP32-S3-EYE: I2C, SPI and LCD support +* [#10883](https://github.com/apache/nuttx/pull/10883) ESP32-S3-EYE: Wifi +File System +Improvements +* [#10995](https://github.com/apache/nuttx/pull/10995) Change inode_checkflags to static function +* [#11445](https://github.com/apache/nuttx/pull/11445) Fix hostfs after uid/gid changes +* [#11433](https://github.com/apache/nuttx/pull/11433) fat: Fix number of data clusters usable for fat driver +* [#11196](https://github.com/apache/nuttx/pull/11196) fat: fix ubsan warning of shift-out-of-bounds +* [#10706](https://github.com/apache/nuttx/pull/10706) fs_epoll: several epoll problems fix +* [#11125](https://github.com/apache/nuttx/pull/11125) fs_files.c: make sure that fs_getfilep is not interrupted when holding mutex +* [#11349](https://github.com/apache/nuttx/pull/11349) fs_gettype:add zipfs magic +* [#11446](https://github.com/apache/nuttx/pull/11446) hostfs:fix structure layout inconsistency in hostfs +* [#11090](https://github.com/apache/nuttx/pull/11090) inode: Change inode_unlink to static function +* [#11188](https://github.com/apache/nuttx/pull/11188) inode: check file list before memcpy +* [#11140](https://github.com/apache/nuttx/pull/11140) inode: improve the performance of get file pointer +* [#11318](https://github.com/apache/nuttx/pull/11318) proc: Fix groupfd to get fd by group instead of current tcb +* [#11449](https://github.com/apache/nuttx/pull/11449) procfs add poll support +* [#11360](https://github.com/apache/nuttx/pull/11360) procfs/cpuinfo: Zero copylen in cpuinfo_read +* [#11039](https://github.com/apache/nuttx/pull/11039) rename: fix use after free issue about rename +* [#11451](https://github.com/apache/nuttx/pull/11451) smartfs: Add necessary aligned access in smartfs_rename() +* [#11248](https://github.com/apache/nuttx/pull/11248) spiffs: correct mutex lock cycle of spiffs +* [#10804](https://github.com/apache/nuttx/pull/10804) support zipfs,can mount zipfile +* [#11232](https://github.com/apache/nuttx/pull/11232) tmpfs: fix an integer overflow +* [#10880](https://github.com/apache/nuttx/pull/10880) vfs: add munmap logic to pseudofs + +Networking +Improvements +* [#10813](https://github.com/apache/nuttx/pull/10813) Add CONFIG_NET_ICMPv6_ROUTER_LIFETIME +* [#10893](https://github.com/apache/nuttx/pull/10893) allow icmpv6 and udp to find the dev by the ifindex with s_boundto. +* [#10916](https://github.com/apache/nuttx/pull/10916) Fix RNDIS compilation error +* [#10819](https://github.com/apache/nuttx/pull/10819) local: Fix the problem that local udp socketpair cannot release fifo files. +* [#11443](https://github.com/apache/nuttx/pull/11443) local: make the call return of each process consistent with linux +* [#11015](https://github.com/apache/nuttx/pull/11015) local: Support SO_SNDBUF option in getsockopt +* [#11289](https://github.com/apache/nuttx/pull/11289) loopback: Fix flags of lo device +* [#11324](https://github.com/apache/nuttx/pull/11324) icmpv6:Optimize the process of obtaining the IPv6 address through RA. +* [#11010](https://github.com/apache/nuttx/pull/11010) icmpv6: Fix net mask logic in icmpv6_setaddresses +* [#11197](https://github.com/apache/nuttx/pull/11197) igmp: call IFF_SET_IPv4 when igmp_send +* [#11384](https://github.com/apache/nuttx/pull/11384) ipv6: Fix source address with many addresses in same network +* [#11378](https://github.com/apache/nuttx/pull/11378) ipv6: Move xxx_ipv6multicast from arch to common code +* [#10894](https://github.com/apache/nuttx/pull/10894) netdb: When set a dns nameserver which already exists, retrun OK +* [#11076](https://github.com/apache/nuttx/pull/11076) netconfig: Enable SOCK_CLOEXEC for ioctl sockets +* [#11396](https://github.com/apache/nuttx/pull/11396) netdev: Modify the logic for setting the IFF_RUNNING status of interfaces. +* [#11110](https://github.com/apache/nuttx/pull/11110) Simplify getting value for different domain +* [#11054](https://github.com/apache/nuttx/pull/11054) Support multiple IPv6 address per netdev +* [#11406](https://github.com/apache/nuttx/pull/11406) tcp: Recover from iob shortage with TCP_WRITE_BUFFERS +* [#11126](https://github.com/apache/nuttx/pull/11126) tcp: Support initial sequence number described in RFC 6528 +* [#11009](https://github.com/apache/nuttx/pull/11009) tun: Fix the error of calling tun_close when tun_txavail or tun_txavail_work is executed +* [#10986](https://github.com/apache/nuttx/pull/10986) tun: Fix the error of calling tun_close when tun_txavail or tun_txavail_work is executed +* [#11372](https://github.com/apache/nuttx/pull/11372) udp: Add check when sending too big packet without IP frag +* [#11210](https://github.com/apache/nuttx/pull/11210) udp: Add support for SO_TIMESTAMP +* [#11120](https://github.com/apache/nuttx/pull/11120) udp: modify ipv4 multicast to allow different conn to join simultaneously +* [#10878](https://github.com/apache/nuttx/pull/10878) usersock: Return -ENOSUPP directly if domain isn't equal to PF_INET/PF_INET6 +Security Issues Fixed In This Release +Compatibility Concerns +* [#10605](https://github.com/apache/nuttx/pull/10605)  Implement ticket spinlock + +A proposal to slove #1488 + +Implement ticket spinlock. + + +* [#10861](https://github.com/apache/nuttx/pull/10861) spinlock: Add spin_lock_init and spin_is_locked macro + +align with Linux api naming. + + +* [#11102](https://github.com/apache/nuttx/pull/11102) sched: explicitly select the cpuload clock source configuration + +Different configurations require different dependencies. +Explicitly select dependencies to avoid automatically selecting +inappropriate configurations. + +* [#11334](https://github.com/apache/nuttx/pull/11334) stm32h7_adc: Dynamically set clock prescaler and BOOST + +First commit is aligning naming and is a breaking change. + +* [#10827](https://github.com/apache/nuttx/pull/10827) Improve adjtime() functionality + +Prior pull request #9084 and issue #8858 added basic adjtime() +support for the SAMv7 platform. + +This pull request adds support for STM32 platform. + +In addition I have made a few changes to the adjtime() configuration +options: + +1) Previously adjustments less than 1 microsecond per tick would be +   completely ignored. Now they are applied over a shorter period at +   a rate of 1 us per tick. + +2) Previously CLOCK_ADJTIME_PERIOD was in units of 1/100th of second. +   Change to milliseconds to be more generally useful unit. +   Change setting name to CLOCK_ADJTIME_PERIOD_MS to make the unit change +   easier to notice. + +3) Previously CLOCK_ADJTIME_SLEWLIMIT was in percentage. +   Most clock crystals have better accuracy than 1%, so the minimum slew +   rate was excessive. Change to CLOCK_ADJTIME_SLEWLIMIT_PPM with setting +   value in parts per million. + +4) No need to use floating point math in clock_adjtime.c. + +Impact + +Users who have used CLOCK_ADJTIME_PERIOD and CLOCK_ADJTIME_SLEWLIMIT  +settings should update their configuration. New CLOCK_ADJTIME_PERIOD_MS is +10x the old period value, and new CLOCK_ADJTIME_SLEWLIMIT_PPM is 10000 times +the old slewlimit. \ No newline at end of file diff --git a/Documentation/ReleaseNotes/NuttX-12.5.0 b/Documentation/ReleaseNotes/NuttX-12.5.0 new file mode 100644 index 0000000000000..c23951d9a3674 --- /dev/null +++ b/Documentation/ReleaseNotes/NuttX-12.5.0 @@ -0,0 +1,462 @@ +NuttX-12.5.0 +------------ + +What's New In This Release +Improvements to Core OS +sched +* [#11944](https://github.com/apache/nuttx/pull/11944) sched: Fix user task exception handling +* [#11498](https://github.com/apache/nuttx/pull/11498) sched: move etc romfs mount from nsh to sched/init +* [#11846](https://github.com/apache/nuttx/pull/11846) sched: remove unused group link node +* [#11950](https://github.com/apache/nuttx/pull/11950) sched: replace some global variables to macro +* [#11769](https://github.com/apache/nuttx/pull/11769) sched: rw_sem: replace mutex with spinlock +* [#11818](https://github.com/apache/nuttx/pull/11818) sched.h: fix CPU_EQUAL(s1, s2) write error +* [#11949](https://github.com/apache/nuttx/pull/11949) sched/cpu: replace up_cpu_index() to this_cpu() +* [#11816](https://github.com/apache/nuttx/pull/11816) sched/cpuload: remove ciritical_section() to fix recursive +* [#11839](https://github.com/apache/nuttx/pull/11839) sched/environ: check envcp validity before hold sched_lock() +* [#11848](https://github.com/apache/nuttx/pull/11848) sched/group: change type of task group member to single queue +* [#11832](https://github.com/apache/nuttx/pull/11832) sched/group: move task group into task_tcb_s to improve performance +* [#11838](https://github.com/apache/nuttx/pull/11838) sched/group: replace group_findbypid to task_getgroup +* [#11885](https://github.com/apache/nuttx/pull/11885) sched/group: set clear flag if the group is not really needed +* [#11971](https://github.com/apache/nuttx/pull/11971) sched/init: move task list table from data to bss +* [#11542](https://github.com/apache/nuttx/pull/11542) sched/logging: add task activation/exit logs +* [#11854](https://github.com/apache/nuttx/pull/11854) sched/pthread: fix memory leak of pthread_tcb_s +* [#11898](https://github.com/apache/nuttx/pull/11898) sched/pthread/join: refactor pthread join to support join task +* [#11890](https://github.com/apache/nuttx/pull/11890) sched/pthread/join: remove unused joininfo +* [#11891](https://github.com/apache/nuttx/pull/11891) sched/pthread: replace pthread_sem_give() to nxsem_post() to unify the post method +* [#11972](https://github.com/apache/nuttx/pull/11972) sched/signal: merge allocate of signal pool +* [#11916](https://github.com/apache/nuttx/pull/11916) sched/signal: move unblock signal info to stack +* [#11925](https://github.com/apache/nuttx/pull/11925) sched/stdio/file: unify group file list to common single queue +* [#11840](https://github.com/apache/nuttx/pull/11840) sched/task: save argument counter to avoid limit check +* [#11948](https://github.com/apache/nuttx/pull/11948) sched/tasklist: replace task status list with macro definition +* [#11774](https://github.com/apache/nuttx/pull/11774) sched/tcb: add preserved tcb flag to support static tcb +* [#11777](https://github.com/apache/nuttx/pull/11777) sched/tls: inline group info in flat mode to improve performance +* [#11953](https://github.com/apache/nuttx/pull/11953) sched/wqueue: replace some global variables to macro +mm +* [#11921](https://github.com/apache/nuttx/pull/11921) mm: Using Macros Instead of Memory to Fill Labels +* [#11884](https://github.com/apache/nuttx/pull/11884) mm/kconfig: fix typo in MM_DEFAULT_ALIGNMENT +libs +* [#11526](https://github.com/apache/nuttx/pull/11526) libc.csv: Fix qsort signature with unexpected quotation mark +* [#11977](https://github.com/apache/nuttx/pull/11977) libc/uname: Add option to disable uname timestamp +* [#11772](https://github.com/apache/nuttx/pull/11772) libm/newlib: fix support for x86_64 +* [#11889](https://github.com/apache/nuttx/pull/11889) libs/libc/string: fix memmem() boundary case when needle is at end of haystack +* [#11474](https://github.com/apache/nuttx/pull/11474) libcxx.defs: appease "expr: syntax error" messages with clang +* [#11556](https://github.com/apache/nuttx/pull/11556) libcxx: Fix CMake compile with correct CMAKE_CXX_STANDARD +* [#11918](https://github.com/apache/nuttx/pull/11918) libxx: ibcxxabi: Path not found +misc +* [#11486](https://github.com/apache/nuttx/pull/11486) assert: fix flags type, should be irqstate_t +* [#11796](https://github.com/apache/nuttx/pull/11796) assert/panic: disable panic message to save the code size +* [#11989](https://github.com/apache/nuttx/pull/11989) audio: libsrc +* [#11464](https://github.com/apache/nuttx/pull/11464) binfmt/libelf: adjust log levels of a few binfmt logs +* [#11904](https://github.com/apache/nuttx/pull/11904) binfmt/loadmodule: replace kmm_free() to lib_free() +* [#11862](https://github.com/apache/nuttx/pull/11862) binfmt/task/member: remove invaild membership reverse +* [#11733](https://github.com/apache/nuttx/pull/11733) include/rpmsg/rpmsg.h: remove temporary define +* [#11640](https://github.com/apache/nuttx/pull/11640) include/threads.h: Fix typo in mtx_timedlock +* [#11466](https://github.com/apache/nuttx/pull/11466) include/types.h: make 64-bit time_t back to unsigned +* [#11805](https://github.com/apache/nuttx/pull/11805) list: rename container_of to list_container_of from public header +* [#11903](https://github.com/apache/nuttx/pull/11903) Revert "assert/panic: disable panic message to save the code size" +* [#11858](https://github.com/apache/nuttx/pull/11858) Replace PRIxPTR with %p and remove the cast of (uintptr_t) +* [#11686](https://github.com/apache/nuttx/pull/11686) openamp: Fix void pointer arithmetic in openamp to remove compilation… +* [#11786](https://github.com/apache/nuttx/pull/11786) tls: report warning if pthread enabled only + +Changes to the Build System +Bug Fixes +* [#11914](https://github.com/apache/nuttx/pull/11914) cmake: add initial KERNEL mode support +* [#11579](https://github.com/apache/nuttx/pull/11579) cmake: add support for Ubuntu stock toolchain for risc-v +* [#11736](https://github.com/apache/nuttx/pull/11736) cmake: add target that define in external moduleCMakeLists.txt +* [#11545](https://github.com/apache/nuttx/pull/11545) cmake: arm/armv8-r: init armv8-r cmake build +* [#11788](https://github.com/apache/nuttx/pull/11788) cmake: fix empty BASE_DEFCONFIG +* [#11749](https://github.com/apache/nuttx/pull/11749) cmake: fix external library mode +* [#11893](https://github.com/apache/nuttx/pull/11893) cmake: fix libxx header file search path issue and enable libxx for CMake build +* [#11745](https://github.com/apache/nuttx/pull/11745) cmake: fix the problems of using cmake to compile custom board +* [#11667](https://github.com/apache/nuttx/pull/11667) cmake: Fixed nucleo-u5a5zj-q +* [#11457](https://github.com/apache/nuttx/pull/11457) cmake: init arch arm64 CMake and qemu-armv8a build +* [#11415](https://github.com/apache/nuttx/pull/11415) cmake: set NUTTX variable +* [#11488](https://github.com/apache/nuttx/pull/11488) cmake: some fixes for sim/macOS + cmake + libcxx +* [#11475](https://github.com/apache/nuttx/pull/11475) cmake: some fixes for cmake build of libcxx +* [#11735](https://github.com/apache/nuttx/pull/11735) cmake/toolchain: fix compiler warning on ARM32 +* [#11624](https://github.com/apache/nuttx/pull/11624) compiler/tasking: fix unreachable code on tasking toolchain +* [#11202](https://github.com/apache/nuttx/pull/11202) tools: Allow apps to customize NuttX build time variables +* [#11808](https://github.com/apache/nuttx/pull/11808) tools: Fix broken exported CMake toolchain file link dependencies +* [#11900](https://github.com/apache/nuttx/pull/11900) tools: Fix cmake-format wrong execution order +* [#11942](https://github.com/apache/nuttx/pull/11942) tools: Fix Export.mk +* [#11908](https://github.com/apache/nuttx/pull/11908) tools: Improve export by adding NuttX current target (arch, chip, board) +* [#11548](https://github.com/apache/nuttx/pull/11548) tools/export: add Zig support for kernel build on linux host +* [#11920](https://github.com/apache/nuttx/pull/11920) tools/gdb: memdump: Enhance memdump +* [#11506](https://github.com/apache/nuttx/pull/11506) tools/link.sh: fix an incorrect variable +* [#11888](https://github.com/apache/nuttx/pull/11888) tools/minidumpserver.py: support quit with gdb +* [#11448](https://github.com/apache/nuttx/pull/11448) tools/mkallsyms: support sorting symbol tables by name +* [#11606](https://github.com/apache/nuttx/pull/11606) tools/nxstyle: can use ',' in the string when declaring it +* [#11710](https://github.com/apache/nuttx/pull/11710) toolchain/lto: enable lto flags only on GNU toolchain +* [#11711](https://github.com/apache/nuttx/pull/11711) toolchain/tasking: add dependencies rules for tasking compiler +Architectural Support +New Architecture Support +* [#11707](https://github.com/apache/nuttx/pull/11707) arch/tricore: add Infineon AURIX TriCore support + +Architecture Improvements +arm +* [#11409](https://github.com/apache/nuttx/pull/11409) arch: Remove the identity mapping of up_addrenv_va_to_pa and up_addrenv_pa_to_va +* [#11812](https://github.com/apache/nuttx/pull/11812) arch: use c++ standard lib that comes with gcc +* [#11558](https://github.com/apache/nuttx/pull/11558) arch/commons: remove duplicated task exit logging +* [#11468](https://github.com/apache/nuttx/pull/11468) arch/Kconfig: add dependency to MM_KMAP for ARCH_KMAP_VBASE +* [#11632](https://github.com/apache/nuttx/pull/11632) arch/Kconfig: replace RPTUN_PING with RPMSG_PING +* [#11453](https://github.com/apache/nuttx/pull/11453) arch/Refine exception handling in ARM +* [#11833](https://github.com/apache/nuttx/pull/11833) arch/arm/arm: fix compile error +* [#11855](https://github.com/apache/nuttx/pull/11855) arch/arm/armv7-a/gicv2: move IRQ to group1 and group0 as the FIQ +* [#11484](https://github.com/apache/nuttx/pull/11484) arch/arm/armv7-a/qemu: add QEMU_TRUSTZONE config and default n +* [#11817](https://github.com/apache/nuttx/pull/11817) arch/arm/armv7-a/r: timer update +* [#11814](https://github.com/apache/nuttx/pull/11814) arch/arm/armv7-a/r: use _ebss as idle stack both in SMP mode or not +* [#11835](https://github.com/apache/nuttx/pull/11835) arch/arm/armv7-a/r: use _ebss as idle stack both in SMP mode or not +* [#11477](https://github.com/apache/nuttx/pull/11477) arch/arm/armv7-m: Expose section name to allow relocation +* [#11795](https://github.com/apache/nuttx/pull/11795) arch/arm/armv8-r: fix build break if disable CONFIG_UART_PL011 +* [#11523](https://github.com/apache/nuttx/pull/11523) arch/arm/armv8-r: fix compile warning +* [#11521](https://github.com/apache/nuttx/pull/11521) arch/arm/armv8-r: wfi secondary cores if SMP is disabled +* [#11522](https://github.com/apache/nuttx/pull/11522) arch/arm/fvp-v8r: fix arm_earlyserialinit() is not called correctly + +* [#11657](https://github.com/apache/nuttx/pull/11657) arch/arm/cxd56xx: Add new feature to use GNSS RAM +* [#11834](https://github.com/apache/nuttx/pull/11834) arch/arm/cxd56xx: Follow interface change of set_buf() operation + +* [#11815](https://github.com/apache/nuttx/pull/11815) arc/arm/goldfish & qemu: handle MMU table and CONFIG_RAM_END +* [#11837](https://github.com/apache/nuttx/pull/11837) arc/arm/goldfish & qemu: handle MMU table and CONFIG_RAM_END + +* [#11494](https://github.com/apache/nuttx/pull/11494) arch/arm/sama5: add LCD backlight PWM clock source selection +* [#11569](https://github.com/apache/nuttx/pull/11569) arch/arm/sama5: sam_ehci: fix transfer cancellation process. +* [#11602](https://github.com/apache/nuttx/pull/11602) arch/arm/sama5: sam_serial: fix to compile with "UART Flow control enable… + +* [#11665](https://github.com/apache/nuttx/pull/11665) arch/arm/samv7: add support for BOARDIOC_RESET_CAUSE command +* [#11836](https://github.com/apache/nuttx/pull/11836) arch/arm/samv7: add support for USART TX DMA transfers +* [#11584](https://github.com/apache/nuttx/pull/11584) arch/arm/samv7: add support for SPI mode in USART peripheral +* [#11601](https://github.com/apache/nuttx/pull/11601) arch/arm/samv7: fix QSPI DMA option not showing in menuconfig +* [#11880](https://github.com/apache/nuttx/pull/11880) arch/arm/samv7: fix typos in Kconfig PWM0 fault input selections - inv. polarity +* [#11595](https://github.com/apache/nuttx/pull/11595) arch/arm/samv7: refactor DAC driver + +* [#11697](https://github.com/apache/nuttx/pull/11697) arch/arm/stm32: Fix STM32xx PWM STOP in multichannel mode +* [#11752](https://github.com/apache/nuttx/pull/11752) arch/arm/stm32/stm32f30xxx_rcc.c: fix broken flash setup +* [#11901](https://github.com/apache/nuttx/pull/11901) arch/arm/stm32/stm32_serial.c: fix compilation of onewire driver mode +* [#11981](https://github.com/apache/nuttx/pull/11981) arch/arm/stm32h7: Fix race condition in ADC interrupt handling +* [#11982](https://github.com/apache/nuttx/pull/11982) arch/arm/stm32h7: Modify the enable logic of FDCAN +* [#11582](https://github.com/apache/nuttx/pull/11582) arch/arm/stm32h7: serial make TX DMA busy when there are an outstanding transaction +* [#11963](https://github.com/apache/nuttx/pull/11963) arch/arm/stm32f7/stm32_foc.c: Set .info_get to foc_lower_ops +* [#11934](https://github.com/apache/nuttx/pull/11934) arch/arm/stm32h7/linum-stm32h753bi: Add buzzer support +* [#11849](https://github.com/apache/nuttx/pull/11849) arch/arm/stm32h7/linum-stm32h753bi: Add support to eeprom using the i2c3 +* [#11830](https://github.com/apache/nuttx/pull/11830) arch/arm/stm32h7/linum-stm32h753bi: Add support to sdcard +* [#11902](https://github.com/apache/nuttx/pull/11902) arch/arm/stm32f40/stm32f40xxx_pinmap: add 3rd alternate mapping for USART6 + +* [#11962](https://github.com/apache/nuttx/pull/11962) arch/arm/imxrt/imxrt_start.c: Clear CONTROL register at start to … + +* [#11511](https://github.com/apache/nuttx/pull/11511) arch/arm/mx8mp: Fix mx8mp ecspi interruption management. + +* [#11878](https://github.com/apache/nuttx/pull/11878) arch/arm/nrf: fixes for SPI +* [#11843](https://github.com/apache/nuttx/pull/11843) arch/arm/nrf{52|53|91}/spi: fix error message +* [#11706](https://github.com/apache/nuttx/pull/11706) arch/arm/nrf{52|53|91}/xxx_rtc.h: include nuttx/irq.h +* [#11702](https://github.com/apache/nuttx/pull/11702) arch/nrf{52|53|91}: let the events from comparator correspond to CC id +* [#11703](https://github.com/apache/nuttx/pull/11703) arch/nrf{52|53}/gpiote.c: fix event reconfiguration for a given pin + +* [#11648](https://github.com/apache/nuttx/pull/11648) arch/arm/rp2040: Support Clock Outputs + +* [#11845](https://github.com/apache/nuttx/pull/11845) arch/arm/s32k1xx: Disable interrupt during FTFC operation + +* [#11564](https://github.com/apache/nuttx/pull/11564) arch/arm/xmc4: add GPIO_U1C0_SCLKOUT_3 P4.0 for spi2 on xm4 +* [#11737](https://github.com/apache/nuttx/pull/11737) arch/arm/xmc4: Add tickless support +* [#11728](https://github.com/apache/nuttx/pull/11728) arch/arm/xmc4: Add XMC4 flash command sequence API +* [#11678](https://github.com/apache/nuttx/pull/11678) arch/arm/xmc4: Fix CCU registers +* [#11581](https://github.com/apache/nuttx/pull/11581) arch/arm/xmc4: fix typo: it is P4.0 and not P0.4 +* [#11600](https://github.com/apache/nuttx/pull/11600) arch/arm/xmc4: xmc4 ccu4 global registers +arm64 +* [#11986](https://github.com/apache/nuttx/pull/11986) arch/arm64: Add the head obj to libarch.a as well +* [#11969](https://github.com/apache/nuttx/pull/11969) arch/arm64/src/common: Remove void * arithmetic +* [#11975](https://github.com/apache/nuttx/pull/11975) arch/arm64/arm64_head.S: Add explicit input section for __start +* [#11946](https://github.com/apache/nuttx/pull/11946) arch/arm64/arm64_mmu: Add data synchronization barrier after page tables are written +* [#11974](https://github.com/apache/nuttx/pull/11974) arch/arm64/imx9: Add CCM (Clock Controller Module) driver + + +risc-v +* [#11612](https://github.com/apache/nuttx/pull/11612) arch/risc-v: add status fields for VS and XS +* [#11985](https://github.com/apache/nuttx/pull/11985) arch/risc-v: minor revision of risc-v/arch.h and fs_mmap.c +* [#11824](https://github.com/apache/nuttx/pull/11824) arch/risc-v: Rename existing CONFIG_PAGING to CONFIG_LEGACY_PAGING and implement page-fault exception and on-demand paging for RISC-V +* [#11620](https://github.com/apache/nuttx/pull/11620) arch/risc-v: reorganization +* [#11876](https://github.com/apache/nuttx/pull/11876) arch/risc-v: simpleboot support +* [#11585](https://github.com/apache/nuttx/pull/11585) arch/risc-v/bl808: Flush MMU Cache after updating SATP +* [#11472](https://github.com/apache/nuttx/pull/11472) arch/risc-v/bl808: Implement Timer with OpenSBI +* [#11609](https://github.com/apache/nuttx/pull/11609) arch/risc-v/canmv230: add CMake support +* [#11561](https://github.com/apache/nuttx/pull/11561) arch/risc-v/cmake: set llvm cputype only for LLVM based toolchain +* [#11650](https://github.com/apache/nuttx/pull/11650) arch/risc-v/common: add param to mmu_flush_cache interface +* [#11961](https://github.com/apache/nuttx/pull/11961) arch/risc-v/common/supervisor/riscv_perform_syscall.c: Record the… +* [#11549](https://github.com/apache/nuttx/pull/11549) arch/risc-v/toolchain: configurable vendor ISA extensions +* [#11721](https://github.com/apache/nuttx/pull/11721) arch/risc-v/esp_: Implement the RMT peripheral for all the supported Risc-V ESP32 devices +* [#11906](https://github.com/apache/nuttx/pull/11906) arch/risc-v/k230: add ARCH_HAVE_RESET and revise logging +* [#11619](https://github.com/apache/nuttx/pull/11619) arch/risc-v/k230: add big core support +* [#11726](https://github.com/apache/nuttx/pull/11726) arch/risc-v/k230: add IPI support to improve RPMsg efficiency +* [#11559](https://github.com/apache/nuttx/pull/11559) arch/risc-v/k230: add NUTTSBI based kernel build support +* [#11504](https://github.com/apache/nuttx/pull/11504) arch/risc-v/k230: add PROTECTED build support +* [#11911](https://github.com/apache/nuttx/pull/11911) arch/risc-v/k230: fix k230_hart_is_big issue +* [#11831](https://github.com/apache/nuttx/pull/11831) arch/risc-v/k230: improvements to support K230 vendor u-boot +* [#11673](https://github.com/apache/nuttx/pull/11673) arch/risc-v/k230: initial Asymmetric Multi-Processing support +* [#11762](https://github.com/apache/nuttx/pull/11762) arch/risc-v/k230: minor revision on configs +* [#11869](https://github.com/apache/nuttx/pull/11869) arch/risc-v/k230: minor revision on PMP settings +* [#11691](https://github.com/apache/nuttx/pull/11691) arch/risc-v/k230: revise k230 hart operations and kernel linker script. +* [#11513](https://github.com/apache/nuttx/pull/11513) arch/risc-v/k230: use fully linked apps in kernel build +* [#11939](https://github.com/apache/nuttx/pull/11939) arch/risc-v/litex: Allow FDT to be passed from previous boot change. +* [#11497](https://github.com/apache/nuttx/pull/11497) arch/risc-v/litex: fix typo in litex/irq.h +* [#11664](https://github.com/apache/nuttx/pull/11664) arch/risc-v/mpfs: i2c fixes +* [#11630](https://github.com/apache/nuttx/pull/11630) arch/risc-v/mpfs: wrapper for sdio device drivers +* [#11598](https://github.com/apache/nuttx/pull/11598) arch/risc-v/mpfs/mpfs_corespi: Fix firing of stale interrupt after warm reset +* [#11663](https://github.com/apache/nuttx/pull/11663) arch/risc-v/mpfs/mpfs_irq.c: Fix up_irqinitialize for warm reboot +* [#11493](https://github.com/apache/nuttx/pull/11493) arch/risc-v/mpfs/mpfs_mpu: Add driver to set MPUCFG registers +* [#11528](https://github.com/apache/nuttx/pull/11528) arch/risc-v/mpfs/mpfs_mpucfg.c: Add mpfs_mpu_lock() +* [#11662](https://github.com/apache/nuttx/pull/11662) arch/risc-v/mpfs/mpfs_serial.c: Allow switching uart output to co… +* [#11527](https://github.com/apache/nuttx/pull/11527) arch/risc-v/mpfs/mpfs_usb.c: Remove PMPCFG configuration from the driver +* [#11794](https://github.com/apache/nuttx/pull/11794) arch/risc-v/rv-virt: Add .init_section to linker script +* [#11496](https://github.com/apache/nuttx/pull/11496) arch/risc-v/rv-virt: revise mstatus operations +* [#11524](https://github.com/apache/nuttx/pull/11524) arch/risc-v/rv-virt: use fully linked apps for kernel build +* [#11541](https://github.com/apache/nuttx/pull/11541) arch/risc-v/nuttsbi: add device specific initialization hook +* [#11533](https://github.com/apache/nuttx/pull/11533) arch/risc-v/nuttsbi: use ARCH_RV_MMIO_BITS for mtimer access selection +* [#11864](https://github.com/apache/nuttx/pull/11864) arch/risc-v/nuttsbi: revise PMP manipulation in NuttX SBI +* [#11638](https://github.com/apache/nuttx/pull/11638) arch/risc-v/nuttsbi: fix weak sbi_late_initialize issues +* [#11731](https://github.com/apache/nuttx/pull/11731) arch/risc-v/espressif: Add SPI Flash support +* [#11993](https://github.com/apache/nuttx/pull/11993) arch/risc-v/espressif: Fix esp32c6 strange characters on boot +* [#11599](https://github.com/apache/nuttx/pull/11599) arch/risc-v/espressif: Legacy bootloader clean-up +* [#11565](https://github.com/apache/nuttx/pull/11565) arch/risc-v/esp32c3-generic: add simple boot support +sim +* [#11458](https://github.com/apache/nuttx/pull/11458) arch/sim: add assertions on hostfs copy of structures +* [#11610](https://github.com/apache/nuttx/pull/11610) arch/sim: fix X11 compile failed +* [#11461](https://github.com/apache/nuttx/pull/11461) arch/sim: make the cmake version of hostfs build similar to the Makefile one +* [#11983](https://github.com/apache/nuttx/pull/11983) arch/sim/matter: solve compilation problems for the matter community +* [#11905](https://github.com/apache/nuttx/pull/11905) arch/sim/nxcamera: add CONFIG_SIM_FBBPP=32 +* [#11459](https://github.com/apache/nuttx/pull/11459) arch/sim/src/sim/CMakeLists.txt: update a few file names +tricore +* [#11959](https://github.com/apache/nuttx/pull/11959) arch/tricore: add spinlock support +x86_64 +* [#11865](https://github.com/apache/nuttx/pull/11865) arch/x86_64: add addrenv support +* [#11747](https://github.com/apache/nuttx/pull/11747) arch/x86_64: add cmake support +* [#11866](https://github.com/apache/nuttx/pull/11866) arch/x86_64: add SSE instruction support +* [#11791](https://github.com/apache/nuttx/pull/11791) arch/x86_64: add spinlock support +* [#11782](https://github.com/apache/nuttx/pull/11782) arch/x86_64: change optimization to -Os for FULLOPT +* [#11899](https://github.com/apache/nuttx/pull/11899) arch/x86_64: move common Make.defs to common +* [#11715](https://github.com/apache/nuttx/pull/11715) arch/x86_64: move common toolchain options to Toolchain.defs +* [#11790](https://github.com/apache/nuttx/pull/11790) arch/x86_64: move PCI bus initialization from qemu-intel64 to common x86_64 +* [#11809](https://github.com/apache/nuttx/pull/11809) arch/x86_64/intel64: add HPET timer support as oneshot timer +* [#11770](https://github.com/apache/nuttx/pull/11770) arch/x86_64/intel64: add software reset support +* [#11783](https://github.com/apache/nuttx/pull/11783) arch/x86_64/intel64: enable FPU and implement up_fpucmp to pass ostest +* [#11748](https://github.com/apache/nuttx/pull/11748) arch/x86_64/intel64: fix various issues with stack misalignment +* [#11873](https://github.com/apache/nuttx/pull/11873) arch/x86_64/intel64: improvements for interrupts +* [#11872](https://github.com/apache/nuttx/pull/11872) arch/x86_64/intel64: improvements for system clock +* [#11764](https://github.com/apache/nuttx/pull/11764) arch/x86_64/intel64: prase multiboot2 header before revoking the lower memory +xtensa +* [#11563](https://github.com/apache/nuttx/pull/11563) arch/xtensa/esp32: Explicitly fail on boot-up for unsupported ESP32 versions +* [#11802](https://github.com/apache/nuttx/pull/11802) arch/xtensa/esp32: Fix issue of system blocking when SPIRAM is used as stack +* [#11897](https://github.com/apache/nuttx/pull/11897) arch/xtensa/esp32: Fix wrong interrupt number +* [#11588](https://github.com/apache/nuttx/pull/11588) arch/xtensa/esp32s3: Add APIs to release DMA channel resources +* [#11593](https://github.com/apache/nuttx/pull/11593) arch/xtensa/esp32s3: Add DMA peripheral to spi driver configuration +* [#11801](https://github.com/apache/nuttx/pull/11801) arch/xtensa/esp32s3: Add the return value of SPI driver +* [#11853](https://github.com/apache/nuttx/pull/11853) arch/xtensa/esp32s3: Configure DMA maximum buffer size based on access to different RAM +* [#11743](https://github.com/apache/nuttx/pull/11743) arch/xtensa/esp32s3: Deinitialize ESP32-S3 SPI slave GDMA engine +* [#11822](https://github.com/apache/nuttx/pull/11822) arch/xtensa/esp32s3: feat(esp32s3-bootloader): allow 32MB flash +* [#11604](https://github.com/apache/nuttx/pull/11604) arch/xtensa/esp32s3: Fix crash issue that occurs when deleting a semaphore in WPA3 +* [#11685](https://github.com/apache/nuttx/pull/11685) arch/xtensa/esp32s2: Fix esp32s2 wdt interrupt bug +* [#11779](https://github.com/apache/nuttx/pull/11779) arch/xtensa/esp32s3: Fix issue of system blocking when SPIRAM is used as stack +* [#11807](https://github.com/apache/nuttx/pull/11807) arch/xtensa/esp32s3: Fix symbol collision between mbedTLS and the Wi-Fi driver +* [#11562](https://github.com/apache/nuttx/pull/11562) arch/xtensa/esp32s3: Fix USB pull-up and pull-down issue +* [#11852](https://github.com/apache/nuttx/pull/11852) arch/xtensa/esp32s3: Fix the issue of erasing a wide range of flash sectors +* [#11820](https://github.com/apache/nuttx/pull/11820) arch/xtensa/esp32s3: fix(esp32s3_spiflash_mtd): use correct type specifiers +* [#11534](https://github.com/apache/nuttx/pull/11534) arch/xtensa/esp32s3: Support WPA3 on softap mode +* [#11516](https://github.com/apache/nuttx/pull/11516) arch/xtensa/esp32[s2|s3] Following up update interrupt type constants. +* [#11557](https://github.com/apache/nuttx/pull/11557) arch/xtensa/esp32s3/pwm: Fix pwm output +* [#11519](https://github.com/apache/nuttx/pull/11519) arch/xtensa/esp32s3/rt_timer: Fix deadlock on RT-Timer thread and Fix Wi-Fi usage with SMP enabled. +* [#11554](https://github.com/apache/nuttx/pull/11554) arch/xtensa/esp32s3/spi: Add SPI bus init in bringup and fix SPI bus 2 and 3 conflict +* [#11575](https://github.com/apache/nuttx/pull/11575) arch/xtensa/esp32s3/spi-dma: Fix spi dma transfer. +* [#11538](https://github.com/apache/nuttx/pull/11538) arch/xtensa/esp32s3/wifi: Fix Wi-Fi connection to WPA3-SAE APs. +Driver Support +New Driver Support +* [#11767](https://github.com/apache/nuttx/pull/11767) drivers/analog/hx711: Add driver for hx711 weight scale ADC +* [#11868](https://github.com/apache/nuttx/pull/11868) drivers/can/sja1000: Add SJA1000 CAN driver support +* [#11806](https://github.com/apache/nuttx/pull/11806) drivers/mtd/mtd_nandram: Adds virtual NAND Flash simulator +* [#11552](https://github.com/apache/nuttx/pull/11552) drivers/usbhost: Add a USB bluetooth driver + +Drivers With Improvements +* [#11589](https://github.com/apache/nuttx/pull/11589) drivers/alt1250: Notice instance information +* [#11829](https://github.com/apache/nuttx/pull/11829) drivers/analog/hx711: Fix few issues in hx711 driver +* [#11941](https://github.com/apache/nuttx/pull/11941) drivers/devicetree: add common FDT utilities APIs +* [#11947](https://github.com/apache/nuttx/pull/11947) drivers/ioexpander: icjx: add support for multiple pin read/write +* [#11590](https://github.com/apache/nuttx/pull/11590) drivers/ioexpander: add support for iC-JX expander +* [#11423](https://github.com/apache/nuttx/pull/11423) drivers/mtd: Add MTD for AT25 eeprom +* [#11886](https://github.com/apache/nuttx/pull/11886) drivers/mtd: mt_config_fs : update nvs to support align size +* [#11671](https://github.com/apache/nuttx/pull/11671) drivers/modem/alt1250: Add LTE_CMDID_RESTARTAPI command +* [#11580](https://github.com/apache/nuttx/pull/11580) drivers/note: fix build with CONFIG_SCHED_INSTRUMENTATION_FUNCTION +* [#11857](https://github.com/apache/nuttx/pull/11857) drivers/pipe: Change to the block mode by file_ioctl(FIONBIO) +* [#11618](https://github.com/apache/nuttx/pull/11618) drivers/rpmsg: It should be possible to use ping without rptun being enabled, so striped rptun_ping out of rptun and rename to rpmsg_ping. +* [#11714](https://github.com/apache/nuttx/pull/11714) drivers/rpmsg: make all rpmsg services depend on RPMSG +* [#11699](https://github.com/apache/nuttx/pull/11699) drivers/rpmsg/ping: Replace UINT_MAX with CLOCK_MAX +* [#11483](https://github.com/apache/nuttx/pull/11483) drivers/rpmsg/rpmsgdev_server: do not notify the client when the fds has teardown +* [#11481](https://github.com/apache/nuttx/pull/11481) drivers/rpmsg/rpmsg_sockif: recv/recvmsg return 0 when peer close +* [#11591](https://github.com/apache/nuttx/pull/11591) drivers/rpmsgfs: decoupling rpmsgfs server and rpmsg virtio. +* [#11510](https://github.com/apache/nuttx/pull/11510) drivers/rpmsgfs: synchronous message transfer format +* [#11515](https://github.com/apache/nuttx/pull/11515) drivers/rpmsgmtd: use fixed length struct to transfer between two cpus +* [#11687](https://github.com/apache/nuttx/pull/11687) drivers/rptun: add explicit initialization for variable +* [#11537](https://github.com/apache/nuttx/pull/11537) drivers/rptun: decoupling rptun ping and rptun_virtio_device, rptun ping and rptun. +* [#11712](https://github.com/apache/nuttx/pull/11712) drivers/rptun: dump: move rptun_dump.c to rptun.c, remove redundant code. +* [#11603](https://github.com/apache/nuttx/pull/11603) drivers/rptun: extract rptun char to rpmsg/rpmsg.c +* [#11741](https://github.com/apache/nuttx/pull/11741) drivers/rptun: ioctl: remove rptun_panic and rptun_dump_all +* [#11713](https://github.com/apache/nuttx/pull/11713) drivers/rptun: ioctl: Strip rpmsg ioctl and rptun ioctl. +* [#11487](https://github.com/apache/nuttx/pull/11487) drivers/rptun: ping: support data checksum and data transfer rate calculation +* [#11520](https://github.com/apache/nuttx/pull/11520) drivers/rptun: remove rptun work queue related unused code +* [#11627](https://github.com/apache/nuttx/pull/11627) drivers/rptun: remove temporarily retained RPTUNIOC_xxx definitions. +* [#11454](https://github.com/apache/nuttx/pull/11454) drivers/rptun: Select OPENMAP under RPTUN +* [#11536](https://github.com/apache/nuttx/pull/11536) drivers/rptun: Strip rpmsg and rptun. +* [#11719](https://github.com/apache/nuttx/pull/11719) drivers/rptun: should initialize the vring da when da == 0 || da == -1 +* [#11874](https://github.com/apache/nuttx/pull/11874) drivers/sensors: add uorb support for lsm9ds1 +* [#11628](https://github.com/apache/nuttx/pull/11628) drivers/sensors: delete warning about argument type in bmi160 +* [#11792](https://github.com/apache/nuttx/pull/11792) drivers/sensors: Remove duplicated defnitions from bmi160.h +* [#11789](https://github.com/apache/nuttx/pull/11789) drivers/sensors/bmi160: fix compilation errors +* [#11923](https://github.com/apache/nuttx/pull/11923) drivers/sensors/bmi270: fix accel and gyro data position +* [#11525](https://github.com/apache/nuttx/pull/11525) drivers/serial/pl011: add support of uart0/2/3 port +* [#11813](https://github.com/apache/nuttx/pull/11813) drivers/syslog: syslog_rpmsg: handle syslog_rpmsg_transfer() return value +* [#11965](https://github.com/apache/nuttx/pull/11965) drivers/usbdev/cdcecm: remove duplicate assignment statements +* [#11560](https://github.com/apache/nuttx/pull/11560) drivers/usbhost: Update USB bluetooth driver +* [#11859](https://github.com/apache/nuttx/pull/11859) drivers/video: Update for improvement and bug fix +* [#11936](https://github.com/apache/nuttx/pull/11936) drivers/video/V4l2: header update +* [#11887](https://github.com/apache/nuttx/pull/11887) drivers/video/v4l2: refactor +* [#11716](https://github.com/apache/nuttx/pull/11716) drivers/virtio: move metal_init to the virtio_register_drivers() +* [#11478](https://github.com/apache/nuttx/pull/11478) drivers/virtio-mmio: ack the interrupt as soon as possible +* [#11482](https://github.com/apache/nuttx/pull/11482) drivers/virtio-mmio: avoid output error log when not found mmio device +* [#11485](https://github.com/apache/nuttx/pull/11485) drivers/virtio-mmio: use byte to byte in read/write config when length != 1,2,4,8 +* [#11592](https://github.com/apache/nuttx/pull/11592) drivers/wireless: bcmf_driver:wlan interface status reset by unsolicited wpa packet +* [#11617](https://github.com/apache/nuttx/pull/11617) drivers/wireless: IEEE802.15.4 support for nrf52 +* [#11701](https://github.com/apache/nuttx/pull/11701) drivers/wireless: ieee802154_mac: add TRACEDUMP request +* [#11705](https://github.com/apache/nuttx/pull/11705) drivers/wireless: mrf24j40: add support for IEEE802154_ATTR_PHY_REGDUMP +* [#11616](https://github.com/apache/nuttx/pull/11616) drivers/wireless: mrf24j40: minor fixes +* [#11535](https://github.com/apache/nuttx/pull/11535) drivers/wireless/bluetooth: Prevent btsak from repeatedly showing the same error. + +Board Support +New Board Support +* [#11960](https://github.com/apache/nuttx/pull/11960) boards: add two new gd32f4 boards +* [#11583](https://github.com/apache/nuttx/pull/11583) boards: Bring up changes from nuttx/pci branch (2nd attempt) +* [#11991](https://github.com/apache/nuttx/pull/11991) boards: esp32c6 devkitm support +* [#11945](https://github.com/apache/nuttx/pull/11945) boards: Initial port for i.MX93 and i.MX93EVK board +* [#11879](https://github.com/apache/nuttx/pull/11879) boards/stm32h7: add Waveshare OpenH743I board +* [#11607](https://github.com/apache/nuttx/pull/11607) boards/arm/xmc4: add xmc4800-relax to nuttx +* [#9761](https://github.com/apache/nuttx/pull/9761) boards/risc-v: Add support for hpm6360evk +Boards With Improvements +arm +* [#11765](https://github.com/apache/nuttx/pull/11765) boards: Enhance board/board.mk compilation capabilities +* [#11499](https://github.com/apache/nuttx/pull/11499) boards: Add CONFIG_LIBC_EXECFUNCS and CONFIG_PSEUDOTERM to adb config + +* [#11626](https://github.com/apache/nuttx/pull/11626) boards/arm/cxd56xx: Add geoid to cxd5610 gnss driver +* [#11652](https://github.com/apache/nuttx/pull/11652) boards/arm/cxd56xx: Fix the modem reset sequence +* [#11793](https://github.com/apache/nuttx/pull/11793) boards/arm/spresense: Add reset control on BLE1507 Add-on board + +* [#11531](https://github.com/apache/nuttx/pull/11531) boards/arm/sama5d3-xplained: Add USB mouse initialization. + +* [#11614](https://github.com/apache/nuttx/pull/11614) boards/arm/{nrf52840-dk| nrf52840-dk}: use TIMER1 as hardware timer +* [#11704](https://github.com/apache/nuttx/pull/11704) boards/arm/nrf{52|53|91}/common: add reset logic + +* [#11658](https://github.com/apache/nuttx/pull/11658) boards/arm/qemu-armv8a: Add nxrecorder to defconfigs + +* [#11927](https://github.com/apache/nuttx/pull/11927) boards/arm/rp2040: Implement board_uniqueid() +* [#11717](https://github.com/apache/nuttx/pull/11717) boards/arm/rp2040/raspberrypi-pico: Add autoleds and userleds support +* [#11978](https://github.com/apache/nuttx/pull/11978) boards/arm/rp2040/raspberrypi-pico: Add buttons support example + +* [#11623](https://github.com/apache/nuttx/pull/11623) boards/arm/g32f4: modified the execution logic of the board_late_initialize()，bringup(). +* [#11642](https://github.com/apache/nuttx/pull/11642) boards/arm/stm32_bbsram.c: fix some build error when enable BBSRAM +* [#11926](https://github.com/apache/nuttx/pull/11926) boards/arm/stm32/stm32f429i-disco add CAN driver support +* [#11500](https://github.com/apache/nuttx/pull/11500) boards/arm/stm32f40/stm32f401rc-rs485: Add rs-485 support +* [#11828](https://github.com/apache/nuttx/pull/11828) boards/arm/stm32f40/stm32f401rc-rs485: Add support to ADC +* [#11882](https://github.com/apache/nuttx/pull/11882) boards/arm/stm32f40/stm32f401rc-rs485: Add support to PWM/DAC +* [#11929](https://github.com/apache/nuttx/pull/11929) boards/arm/stm32f40/stm32f401rc-rs485: Add support to Quadrature Encoder +* [#11708](https://github.com/apache/nuttx/pull/11708) boards/arm/stm32f40/stm32f401rc-rs485: Add USB console support +* [#11766](https://github.com/apache/nuttx/pull/11766) boards/arm/stm32f40/stm32f401rc-rs485: Add support to LM75 sensor +* [#11682](https://github.com/apache/nuttx/pull/11682) boards/arm/stm32f40/stm32f401rc-rs485: Add rs-485 master mode configuration +* [#11784](https://github.com/apache/nuttx/pull/11784) boards/arm/stm32f40/stm32f411-minimum: remove non existing include in Kconfig +* [#11698](https://github.com/apache/nuttx/pull/11698) boards/arm/stm32h7/linum-stm32h753bi: add modbus master using uart6 +* [#11768](https://github.com/apache/nuttx/pull/11768) boards/arm/stm32h7/linum-stm32h753bi: Add USB console support +* [#11505](https://github.com/apache/nuttx/pull/11505) boards/arm/stm32h7/nucleo-h745zi/stm32_bringup.c: the cpuname should be the remote cpu name +* [#11669](https://github.com/apache/nuttx/pull/11669) boards/arm/stm32h7/nucleo-h743zi2: pysim Modified CONFIG_INIT_STACKSIZE to 2048 +* [#11501](https://github.com/apache/nuttx/pull/11501) boards/arm/stm32h7/nucleo-l432kc: Fix board configuration for USART2 +* [#11681](https://github.com/apache/nuttx/pull/11681) boards/arm/stm32h7/STM32-H745 files for pysimCoder + +* [#11679](https://github.com/apache/nuttx/pull/11679) boards/arm/xmc4/xmc4800-relax: build xmc4800-relax using CMake +* [#11659](https://github.com/apache/nuttx/pull/11659) boards/arm/xmc4/xmc4800-relax: Add EtherCAT support on xmc4800-relax + +arm64 +* [#11797](https://github.com/apache/nuttx/pull/11797) boards/arm64: SMP: fix crash when switch to new task which is still running +* [#11479](https://github.com/apache/nuttx/pull/11479) boards/arm64/qemu/qemu_bringup: add tmp fs mount for qemu-armv8a +avr +* [#11668](https://github.com/apache/nuttx/pull/11668) boards/avr/avr32dev1: Fix compilation and nsh boot-up +x86_64 +* [#11867](https://github.com/apache/nuttx/pull/11867) boards/intel64: move PCI initialization back to board logic +* [#11781](https://github.com/apache/nuttx/pull/11781) boards/intel64: qemu-intel64: add .note.gnu.* to linker script +risc-v +* [#11465](https://github.com/apache/nuttx/pull/11465) boards/risc-v/k230: adding kernel build for CanMV-K230 device +* [#11851](https://github.com/apache/nuttx/pull/11851) boards/risc-v/k230: remove unnecessary ARCH_LAZYFPU from defconfigs +* [#11489](https://github.com/apache/nuttx/pull/11489) boards/risc-v/k230: revise CanMV230 kernel build support +* [#11631](https://github.com/apache/nuttx/pull/11631) boarsd/risc-v/qemu: Use ROMFS image to load user applications in kernel mode and update rv-virt board documentation +* [#11660](https://github.com/apache/nuttx/pull/11660) boards/risc-v/rv-virt: Add nxrecorder to defconfigs +* [#11587](https://github.com/apache/nuttx/pull/11587) boards/risc-v/rv-virt: Fix the hello app crash with nsh64 +* [#11633](https://github.com/apache/nuttx/pull/11633) boarsd/risc-v/rv-virt: Guard mount point for procfs/tmpfs +* [#11576](https://github.com/apache/nuttx/pull/11576) boards/risc-v/rv-virt/configs: avoid build errors with cmake or stock gcc 10.2 +xtrensa +* [#11842](https://github.com/apache/nuttx/pull/11842) boards/xtensa/esp32: Increase init task stack size to 3072 +* [#11895](https://github.com/apache/nuttx/pull/11895) boards/xtensa/esp32: ESP32 opencores network driver for QEMU +* [#11725](https://github.com/apache/nuttx/pull/11725) boards/xtensa/esp32-sparrow-kit: Add I2S support for the board's microphone +* [#11636](https://github.com/apache/nuttx/pull/11636) boards/xtensa/esp32/dac-one-shot: lower-half driver for ESP32 internal DAC +* [#11844](https://github.com/apache/nuttx/pull/11844) boards/xtensa/esp32c6: Remove sotest config for esp32c6 +File System +improvements +* [#11841](https://github.com/apache/nuttx/pull/11841) fs: enhance file_allocate_from_tcb() mulit-threads saftey & remove memcpy when close the fd +* [#11896](https://github.com/apache/nuttx/pull/11896) fs: revise comments and harden nx_mount logic +* [#11892](https://github.com/apache/nuttx/pull/11892) fs/driver: using nx_unlink to call unlink ops to release some resource +* [#11723](https://github.com/apache/nuttx/pull/11723) fs/fat: fs_fat32: fix default return value of fat_ioctl(). +* [#11850](https://github.com/apache/nuttx/pull/11850) fs/inode: add pre-allocated task files to avoid allocator access +* [#11958](https://github.com/apache/nuttx/pull/11958) fs/inode: replace some global variables to macro +* [#11729](https://github.com/apache/nuttx/pull/11729) fs/littlefs: Add to get the full path +* [#11680](https://github.com/apache/nuttx/pull/11680) fs/mount: add FS_RPMSGFS as cause of NODFS_SUPPORT +* [#11540](https://github.com/apache/nuttx/pull/11540) fs/partition: fs_mbr: fix for MBR block count calculation. +* [#11776](https://github.com/apache/nuttx/pull/11776) fs/procfs: add build config to /proc/version +* [#11550](https://github.com/apache/nuttx/pull/11550) fs/romfs: Move rn_child/rn_count before rn_namesize +* [#11629](https://github.com/apache/nuttx/pull/11629) fs/shmfs: Fix CONFIG_FS_SHM -> CONFIG_FS_SHMFS +* [#11634](https://github.com/apache/nuttx/pull/11634) fs/shmfs: Fix stat() system call for shmfs object +* [#11635](https://github.com/apache/nuttx/pull/11635) fs/shmfs: Fix shmfs_truncate +* [#11647](https://github.com/apache/nuttx/pull/11647) fs/vfat: Fix typo in the macro DIRSEC_BYTENDX +* [#11724](https://github.com/apache/nuttx/pull/11724) fs/vfs: Implement Filelock +Networking +Improvements +* [#11495](https://github.com/apache/nuttx/pull/11495) net: add support for multi PHY and optionally use it on imxrt +* [#11759](https://github.com/apache/nuttx/pull/11759) net: Fix minor coding problems +* [#11492](https://github.com/apache/nuttx/pull/11492) net: Only call arp_send for PF_INET and icmpv6_neighbor for PF_INET6 +* [#11491](https://github.com/apache/nuttx/pull/11491) net/can: Release IOB when failed to queue in datahandler +* [#11856](https://github.com/apache/nuttx/pull/11856) net/local: Fix the minor issue found +* [#11480](https://github.com/apache/nuttx/pull/11480) net/local: local_sendmsg: fix peer->lc_cfps[] array out-of-range write +* [#11804](https://github.com/apache/nuttx/pull/11804) net/local: Minor local socket improvement +* [#11653](https://github.com/apache/nuttx/pull/11653) net/nat: Fix ICMP Error MSG Processing +* [#11744](https://github.com/apache/nuttx/pull/11744) net/pkt: Support binding to devices other than ETH +* [#11509](https://github.com/apache/nuttx/pull/11509) net/route: Support longest prefix match for routing +* [#11649](https://github.com/apache/nuttx/pull/11649) net/rpmsgsock: Rename rpmsg_socket_getconnname to rpmsg_socket_getpeername +* [#11578](https://github.com/apache/nuttx/pull/11578) net/support to ARP Address Conflict Detection +* [#11909](https://github.com/apache/nuttx/pull/11909) net/tcp: return true only when send window updates +* [#11910](https://github.com/apache/nuttx/pull/11910) net/tun: in tun_write, try to release iob before iob_prepare +* [#11639](https://github.com/apache/nuttx/pull/11639) net/udp: Fix source address selection under IPv6 + +Security Issues Fixed In This Release + +Compatibility Concerns +* [#11498](https://github.com/apache/nuttx/pull/11498) sched: move etc romfs mount from nsh to sched/init + + +Usually the startup script is placed under /etc. The contents of the etc directory are compiled and linked with Nuttx binary in the form of romfs. After startup, it will be mounted by Nsh. + +etc is generated by the different boards, that use genromfs and xxd tools to generate and compile it into the Nuttx, for example: boards/arm/at32/at32f437-mini/tool/mkromfs.sh +The more common method is etc image generated from the content in the corresponding board/arch/board/board/src/etc directory, and added by Makefile for example: boards/sim/sim/sim/src/etc. + +But in kernel/protected mode, Nuttx kernel and apps are run in different privileged/non-privileged mode or the isolated binarys, so as that nsh should use syscall to access Nuttx kernel by exported API. In this scenario, nsh can not mount the etc image content, because that is generated in board and as a part of Nuttx kernel. + +changes: + +move etc romfs mount from nsh to Nuttx, but keep the script to parse and execute. +move and rename the related CONFIG, move customized nsh_romfsimg.h to etc_romfs.c in boards, and no need declaration for romfs_img/romfs_img_len. + +This commit changes and updates all configurations in Nuttx arch/board as much as possible, +but if any missing, please refer to the following simple guide: + +rename CONFIG_NSH_ROMFSETC to CONFIG_ETC_ROMFS, and delete CONFIG_NSH_ARCHROMFS in defconfig +rename the etc romfs mount configs, for example CONFIG_NSH_FATDEVNO to CONFIG_ETC_FATDEVNO +move customized nsh_romfsimg.h to etc_romfs.c in board/arch/board/board/src and no need declaration for romfs_img/romfs_img_len. +delete default nsh_romfsimg.h, if ROMFSETC is enabled, should generate and compile etc_romfs.c in board/arch/board/board/src. diff --git a/Documentation/ReleaseNotes/NuttX-12.5.1 b/Documentation/ReleaseNotes/NuttX-12.5.1 new file mode 100644 index 0000000000000..1b1360b38d068 --- /dev/null +++ b/Documentation/ReleaseNotes/NuttX-12.5.1 @@ -0,0 +1,45 @@ +NuttX-12.5.1 +------------ + +What's New In This Release + +Major Changes to Core OS +Bug Fixes +sched +* [#12062](https://github.com/apache/nuttx/pull/12062) sched/SMP: Fix returning uninitialized variable in nxsched_add_readytorun() + +mm +* [#12068](https://github.com/apache/nuttx/pull/12068) mm/kmap.h: fix typo in comments + +Architectural Support +Bug Fixes +* [#12073](https://github.com/apache/nuttx/pull/12073) all: Fix accessing uninitialized local variables + +arm +* [#12071](https://github.com/apache/nuttx/pull/12071) arch/arm/am335x: Fix incorrect signedness of variable +* [#12072](https://github.com/apache/nuttx/pull/12072) arch/arm/s32k3xx: Fix incorrect check for invalid port or pin number +* [#12098](https://github.com/apache/nuttx/pull/12098) arch/arm/stm32h7/fdcan: fixed kconfig and debug register +* [#12099](https://github.com/apache/nuttx/pull/12099) arch/arm/stm32h7/stm32_i2c: fix sending large data over i2c +* [#12070](https://github.com/apache/nuttx/pull/12070) arch/arm/stm32h7: Serial Fix Logic error in up_dma_txavailable +risc-v +* [#12069](https://github.com/apache/nuttx/pull/12069) arch/risc-v/esp32[c3|c6|h2]: Fix filesystem test support +* [#12061](https://github.com/apache/nuttx/pull/12061) arch/risc-v/espressif: Fix empty cpuint number +Xtensa +* [#12065](https://github.com/apache/nuttx/pull/12065) arch/xtensa/esp32s3: Fix one page program span over 2 pages + +Driver Support +Bug Fixes +* [#12074](https://github.com/apache/nuttx/pull/12074) drivers/net/lan9250: Fix crash issue of sending packets by lan9250 driver +* [#12066](https://github.com/apache/nuttx/pull/12066) drivers/video/isx019: Fix the default_value of some parameters + +Board Support +Bug Fixes +* [#12060](https://github.com/apache/nuttx/pull/12060) boards: Fix board configs after disabling NSH_DISABLE_HELP + +arm +* [#12063](https://github.com/apache/nuttx/pull/12063) boards/arm/rp2040: Fix build errors for nshsram configurations +* [#12064](https://github.com/apache/nuttx/pull/12064) boards/arm/raspberrypi-pico: Fix nshsram build error + +Networking +Bug Fixes +* [#12097](https://github.com/apache/nuttx/pull/12097) net: Fix max conn always one less than configured value diff --git a/Documentation/applications/testing/cachespeed/index.rst b/Documentation/applications/benchmarks/cachespeed/index.rst similarity index 100% rename from Documentation/applications/testing/cachespeed/index.rst rename to Documentation/applications/benchmarks/cachespeed/index.rst diff --git a/Documentation/applications/benchmarks/coremark-pro/index.rst b/Documentation/applications/benchmarks/coremark-pro/index.rst new file mode 100644 index 0000000000000..236931b247da3 --- /dev/null +++ b/Documentation/applications/benchmarks/coremark-pro/index.rst @@ -0,0 +1,3 @@ +=============================== +``coremark-pro`` CoreMark-PRO +=============================== diff --git a/Documentation/applications/benchmarks/dhrystone/index.rst b/Documentation/applications/benchmarks/dhrystone/index.rst new file mode 100644 index 0000000000000..e2c089cb18590 --- /dev/null +++ b/Documentation/applications/benchmarks/dhrystone/index.rst @@ -0,0 +1,3 @@ +=============================== +``Dhrystone`` Dhrystone +=============================== diff --git a/Documentation/applications/benchmarks/fio/index.rst b/Documentation/applications/benchmarks/fio/index.rst new file mode 100644 index 0000000000000..fb06b365047c6 --- /dev/null +++ b/Documentation/applications/benchmarks/fio/index.rst @@ -0,0 +1,3 @@ +=============================== +``FIO`` FIO Benchmark +=============================== diff --git a/Documentation/applications/testing/iozone/index.rst b/Documentation/applications/benchmarks/iozone/index.rst similarity index 100% rename from Documentation/applications/testing/iozone/index.rst rename to Documentation/applications/benchmarks/iozone/index.rst diff --git a/Documentation/applications/testing/osperf/index.rst b/Documentation/applications/benchmarks/osperf/index.rst similarity index 100% rename from Documentation/applications/testing/osperf/index.rst rename to Documentation/applications/benchmarks/osperf/index.rst diff --git a/Documentation/applications/testing/ramspeed/index.rst b/Documentation/applications/benchmarks/ramspeed/index.rst similarity index 100% rename from Documentation/applications/testing/ramspeed/index.rst rename to Documentation/applications/benchmarks/ramspeed/index.rst diff --git a/Documentation/applications/testing/superpi/index.rst b/Documentation/applications/benchmarks/superpi/index.rst similarity index 100% rename from Documentation/applications/testing/superpi/index.rst rename to Documentation/applications/benchmarks/superpi/index.rst diff --git a/Documentation/applications/nsh/commands.rst b/Documentation/applications/nsh/commands.rst index 674ab2286896c..aee407611c90a 100644 --- a/Documentation/applications/nsh/commands.rst +++ b/Documentation/applications/nsh/commands.rst @@ -231,9 +231,10 @@ indication only if the files differ. **Command Syntax**:: - date [-s "MMM DD HH:MM:SS YYYY"] + date [-s "MMM DD HH:MM:SS YYYY"] [-u] [+%format] -**Synopsis**. Show or set the current date and time. +**Synopsis**. Show or set the current date and time or UTC with ``-u`` option, +and support format output with ``+%format``. To show the current system time and date, type in the ``date`` command. The output displays the day of the week, day of the month, month, year, @@ -503,6 +504,34 @@ examples: The ``export`` command is not supported by NSH unless both ``CONFIG_NSH_VARS=y`` and ``CONFIG_DISABLE_ENVIRON``\ is not set. +.. _cmdexpr: + +``expr`` Evaluate expressions +============================= + +**Command Syntax**:: + + expr + +**Synopsis**. It is a mini version for the expr command, which implements the +features of addition, subtraction, multiplication, division and mod. + +**Examples**: + + nsh> expr 5 - 2 + 3 + nsh> set hello 10 + nsh> expr $hello - 2 + 8 + nsh> expr 8 a 9 + Unknown operator + nsh> expr 20 / 5 + 4 + nsh> expr 10 % 4 + 2 + nsh> expr 100 + 0 + 100 + .. _cmdfree: ``free`` Show Memory Manager Status @@ -876,7 +905,7 @@ implementation is simplified for use with NuttX in these ways: **Command Syntax**:: - ls [-lRs] + ls [-lRsh] **Synopsis**. Show the contents of the directory at ````. NOTE: ```` must refer to a directory and @@ -888,6 +917,7 @@ no other file system object. ``-R`` Show the contents of specified directory and all of its sub-directories. ``-s`` Show the size of the files along with the filenames in the listing ``-l`` Show size and mode information along with the filenames in the listing. +``-h`` Show size and mode information along with the filenames in the listing with humanable. ====== ================================ .. _cmdlsmod: @@ -1756,6 +1786,27 @@ and the group-wide environment variables. For example:: nsh> +.. _cmduptime: + +``uptime`` Show how long the system has been running +==================================================== + +**Command Syntax**: + + uptime [-sph] + +**Synopsis**. Display of the following information: the current time, +how long the system has been running, and the load averages for the past 1, 5, +and 15 minutes. + +**Options** + +====== ================================ +``-p`` show uptime in pretty format +``-s`` system up since +``-h`` display this help and exit +====== ================================ + .. _cmdurldecode: ``urldecode`` URL Decode @@ -1898,4 +1949,3 @@ Example:: nsh> ``ping6`` differs from ``ping`` in that it uses IPv6 addressing. - diff --git a/Documentation/applications/nsh/config.rst b/Documentation/applications/nsh/config.rst index b4dfa9cda90ba..93a0b19571e0a 100644 --- a/Documentation/applications/nsh/config.rst +++ b/Documentation/applications/nsh/config.rst @@ -299,12 +299,6 @@ Configuration Description registered as ``/dev/mmcsd``\ *N* where *N* is the minor number. Default is zero. - ``CONFIG_NSH_ROMFSETC`` Mount a ROMFS file system at ``/etc`` and provide a system init - script at ``/etc/init.d.rc.sysinit`` and a startup script at - ``/etc/init.d/rcS``. - The default system init script will mount a FAT FS RAMDISK at - ``/tmp`` but the logic is `easily extensible <#startupscript>`__. - ``CONFIG_NSH_CONSOLE`` If ``CONFIG_NSH_CONSOLE`` is set to *y*, then a serial console front-end is selected. @@ -451,44 +445,20 @@ Configuration Description is indicated. ============================================== ============================================================ -If ``CONFIG_NSH_ROMFSETC`` is selected, then the following additional +If ``CONFIG_ETC_ROMFS`` is selected, then the following additional configuration setting apply: ============================== ============================================================== Configuration Description ============================== ============================================================== -``CONFIG_NSH_ARCHROMFS`` May be defined to specify an alternative ROMFS image - that can be found at ``boards////include/nsh_romfsimg.h``. -``CONFIG_NSH_ROMFSMOUNTPT`` The default mountpoint for the ROMFS volume is ``"/etc"``, - but that can be changed with this setting. This must be a - absolute path beginning with '``/``' and enclosed in quotes. ``CONFIG_NSH_SYSINITSCRIPT`` This is the relative path to the system init script within the mountpoint. The default is ``"init.d/rc.sysinit"``. This is a relative path and must not start with '``/``' but must be enclosed in quotes. ``CONFIG_NSH_INITSCRIPT`` This is the relative path to the startup script within the mountpoint. The default is ``"init.d/rcS"``. This is a relative path and must not start with '``/``' but must be enclosed in quotes. -``CONFIG_NSH_ROMFSDEVNO`` This is the minor number of the ROMFS block device. - The default is '``0``' corresponding to ``/dev/ram0``. -``CONFIG_NSH_ROMFSSECTSIZE`` This is the sector size to use with the ROMFS volume. Since the - default volume is very small, this defaults to 64 but should - be increased if the ROMFS volume were to be become large. - Any value selected must be a power of 2. ============================== ============================================================== -When the default ``rc.sysinit`` file used when ``CONFIG_NSH_ROMFSETC`` is -selected, it will mount a FAT FS under ``/tmp``. The following -selections describe that FAT FS. - -============================== ======================================================= -Configuration Description -============================== ======================================================= -``CONFIG_NSH_FATDEVNO`` This is the minor number of the FAT FS block device. - The default is '``1``' corresponding to ``/dev/ram1``. -``CONFIG_NSH_FATSECTSIZE`` This is the sector size use with the FAT FS. Default is 512. -============================== ======================================================= - - Common Problems =============== diff --git a/Documentation/applications/nsh/installation.rst b/Documentation/applications/nsh/installation.rst index 4633460fb86eb..a88a7275258bb 100644 --- a/Documentation/applications/nsh/installation.rst +++ b/Documentation/applications/nsh/installation.rst @@ -27,177 +27,3 @@ increasing difficulty: create the start-up script. It is sufficiently complex that is deserves its own paragraph -NuttShell Start up Scripts --------------------------- - -First of all you should look at `NSH Start-Up Script <#startupscript>`__ -paragraph. Most everything you need to know can be found there. That -information will be repeated and extended here for completeness. - -**NSH Start-Up Script**. NSH supports options to provide a start up -script for NSH. The start-up script contains any command support by NSH -(i.e., that you see when you enter 'nsh> help'). In general this -capability is enabled with ``CONFIG_NSH_ROMFSETC=y``, but has several -other related configuration options as described with the `NSH-specific -configuration settings <#nshconfiguration>`__ paragraph. This capability -also depends on: - - - ``CONFIG_DISABLE_MOUNTPOINT=n``. If mount point support is disabled, - then you cannot mount *any* file systems. - - - ``CONFIG_FS_ROMFS`` enabled. This option enables ROMFS file system - support. - -**Default Start-Up Behavior**. The implementation that is provided is -intended to provide great flexibility for the use of Start-Up files. -This paragraph will discuss the general behavior when all of the -configuration options are set to the default values. - -In this default case, enabling ``CONFIG_NSH_ROMFSETC`` will cause NSH to -behave as follows at NSH start-up time: - - - NSH will create a read-only RAM disk (a ROM disk), containing a tiny - ROMFS file system containing the following:: - - `--init.d/ - `-- rcS - `-- rc.sysinit - - Where ``rcS`` is the NSH start-up script. - Where ``rc.sysinit`` is the NSH system-init script. - - - NSH will then mount the ROMFS file system at ``/etc``, resulting in:: - - |--dev/ - | `-- ram0 - `--etc/ - `--init.d/ - `-- rcS - `-- rc.sysinit - - - By default, the contents of ``rc.sysinit`` script are:: - - # Create a RAMDISK and mount it at /tmp - - mkrd -m 1 -s 512 1024 - mkfatfs /dev/ram1 - mount -t vfat /dev/ram1 /tmp - - - NSH will execute the script at ``/etc/init.d/rc.sysinit`` at system - init (before the first NSH prompt). After execution of the script, - the root FS will look like:: - - |--dev/ - | |-- ram0 - | `-- ram1 - |--etc/ - | `--init.d/ - | `-- rcS - | `-- rc.sysinit - `--tmp/ - -**Example Configurations**. Here are some configurations that have -``CONFIG_NSH_ROMFSETC=y`` in the NuttX configuration file. They might -provide useful examples: - - - ``boards/arm/stm32/hymini-stm32v/nsh2`` - - ``boards/arm/dm320/ntosd-dm320/nsh`` - - ``boards/sim/sim/sim/nsh`` - - ``boards/sim/sim/sim/nsh2`` - - ``boards/sim/sim/sim/nx`` - - ``boards/sim/sim/sim/nx11`` - - ``boards/sim/sim/sim/touchscreen`` - -In most of these cases, the configuration sets up the *default* -``/etc/init.d/rc.sysinit`` and ``/etc/init.d/rcS`` script. The default -script is here: ``apps/nshlib/rc.sysinit.template`` and -``apps/nshlib/rcS.template``. (The funny values in the rc.sysinit.template -like ``XXXMKRDMINORXXX`` get replaced via ``sed`` at build time). This -default configuration creates a ramdisk and mounts it at ``/tmp`` as -discussed above. - -If that default behavior is not what you want, then you can provide your -own custom ``rc.sysinit`` and ``rcS`` script by defining -``CONFIG_NSH_ARCHROMFS=y`` in the configuration file. - -**Modifying the ROMFS Image**. The contents of the ``/etc`` directory -are retained in the file ``apps/nshlib/nsh_romfsimg.h`` OR, if -``CONFIG_NSH_ARCHROMFS`` is defined, -``include/arch/board/nsh_romfsimg.h``. In order to modify the start-up -behavior, there are three things to study: - - #. **Configuration Options.** The additional ``CONFIG_NSH_ROMFSETC`` - configuration options discussed with the other `NSH-specific - configuration settings <#nshconfiguration>`__. - - #. ``tools/mkromfsimg.sh`` **Script**. The script - ``tools/mkromfsimg.sh`` creates ``nsh_romfsimg.h``. It is not - automatically executed. If you want to change the configuration - settings associated with creating and mounting the ``/tmp`` - directory, then it will be necessary to re-generate this header file - using the ``tools/mkromfsimg.sh`` script. - - The behavior of this script depends upon several things: - - #. The configuration settings then installed configuration. - - #. The ``genromfs`` tool(available from - `http://romfs.sourceforge.net `__) - or included within the NuttX buildroot toolchain. There is also a - snapshot available in the NuttX tools repository - `here `__. - - #. The ``xxd`` tool that is used to generate the C header files (xxd - is a normal part of a complete Linux or Cygwin installation, - usually as part of the ``vi`` package). - - #. The file ``apps/nshlib/rc.sysinit.template`` (OR, if - ``CONFIG_NSH_ARCHROMFS`` is defined - ``include/arch/board/rc.sysinit.template``. - - The file ``apps/nshlib/rcS.template`` (OR, if - ``CONFIG_NSH_ARCHROMFS`` is defined - ``include/arch/board/rcs.template``. - - #. ``rc.sysinit.template``. The file ``apps/nshlib/rc.sysinit.template`` - contains the general form of the ``rc.sysinit`` file; configured values - are plugged into this template file to produce the final ``rc.sysinit`` file. - - ``rcS.template``. The file ``apps/nshlib/rcS.template`` contains the - general form of the ``rcS`` file; configured values are plugged into - this template file to produce the final ``rcS`` file. - - To generate a custom ``rc.sysinit`` and ``rcS`` file a copy of - ``rc.sysinit.template`` and ``rcS.template`` needs to - be placed at ``tools/`` and changed according to the desired start-up - behaviour. Running ``tools/mkromfsimg.h`` creates ``nsh_romfsimg.h`` - which needs to be copied to ``apps/nshlib`` OR if - ``CONFIG_NSH_ARCHROMFS`` is defined to - ``boards////include``. - -``rc.sysinit.template``. The default ``rc.sysinit.template``, -``apps/nshlib/rc.sysinit.template``, generates the standard, default -``apps/nshlib/nsh_romfsimg.h`` file. - -``rcS.template``. The default ``rcS.template``, -``apps/nshlib/rcS.template``, generates the standard, default -``apps/nshlib/nsh_romfsimg.h`` file. - -If ``CONFIG_NSH_ARCHROMFS`` is defined in the NuttX configuration file, -then a custom, board-specific ``nsh_romfsimg.h`` file residing in -``boards////include``\ will be used. NOTE when the OS -is configured, ``include/arch/board`` will be linked to -``boards////include``. - -All of the startup-behavior is contained in ``rc.sysinit.template`` and -``rcS.template``. The role of ``mkromfsimg.sh`` script is to (1) apply -the specific configuration settings to ``rc.sysinit.template`` to create -the final ``rc.sysinit``, and ``rcS.template`` to create the final ``rcS``, -and (2) to generate the header file ``nsh_romfsimg.h`` containing the ROMFS file -system image. To do this, ``mkromfsimg.sh`` uses two tools that must be -installed in your system: - - #. The ``genromfs`` tool that is used to generate the ROMFS file system - image. - - #. The ``xxd`` tool that is used to create the C header file. diff --git a/Documentation/applications/nsh/nsh.rst b/Documentation/applications/nsh/nsh.rst index d69aefb47a2ad..3398e40f7e830 100644 --- a/Documentation/applications/nsh/nsh.rst +++ b/Documentation/applications/nsh/nsh.rst @@ -261,123 +261,3 @@ Environment Variables ========== ================================================ -NSH Start-Up Script -=================== - -**NSH Start-Up Script**. NSH supports options to provide a start -up script for NSH. In general this capability is enabled with -``CONFIG_NSH_ROMFSETC``, but has several other related -configuration options as described with the -:doc:`NSH specific configuration settings `. -This capability also depends on: - - - ``CONFIG_DISABLE_MOUNTPOINT`` not set - - ``CONFIG_FS_ROMFS`` enabled - -**Default Start-Up Behavior**. The implementation that is provided -is intended to provide great flexibility for the use of Start-Up -files. This paragraph will discuss the general behavior when all -of the configuration options are set to the default values. - -In this default case, enabling ``CONFIG_NSH_ROMFSETC`` will cause -NSH to behave as follows at NSH startup time: - - - NSH will create a read-only RAM disk (a ROM disk), containing a - tiny ROMFS file system containing the following:: - - `--init.d/ - `-- rcS - `-- rc.sysinit - - Where rcS is the NSH start-up script. - Where rc.sysinit is the NSH system init script. - - - NSH will then mount the ROMFS file system at ``/etc``, - resulting in:: - - |--dev/ - | `-- ram0 - `--etc/ - `--init.d/ - `-- rcS - `-- rc.sysinit - - - By default, the contents of rc.sysinit script are:: - - # Create a RAMDISK and mount it at XXXRDMOUNTPOINTXXX - - mkrd -m 1 -s 512 1024 - mkfatfs /dev/ram1 - mount -t vfat /dev/ram1 /tmp - - - NSH will execute the script at ``/etc/init.d/rc.sysinit`` at - system init script(before the first NSH prompt). After - execution of the script, the root FS will look like:: - - |--dev/ - | |-- ram0 - | `-- ram1 - |--etc/ - | `--init.d/ - | `-- rcS - | `-- rc.sysinit - `--tmp/ - -**Modifying the ROMFS Image**. The contents of the ``/etc`` -directory are retained in the file ``apps/nshlib/nsh_romfsimg.h`` -OR, if ``CONFIG_NSH_ARCHROMFS`` is defined, -``include/arch/board/rcs.template``). In order to modify the -start-up behavior, there are three things to study: - - #. **Configuration Options.** The additional - ``CONFIG_NSH_ROMFSETC`` configuration options discussed with - the other :doc:`NSH specific configuration settings `. - #. `tools/mkromfsimg.sh`` **Script**. The script - ``tools/mkromfsimg.sh`` creates ``nsh_romfsimg.h``. It is not - automatically executed. If you want to change the configuration - settings associated with creating and mounting the ``/tmp`` - directory, then it will be necessary to re-generate this header - file using the ``tools/mkromfsimg.sh`` script. - - The behavior of this script depends upon three things: - - - The configuration settings then installed configuration. - - The ``genromfs`` tool (available from - http://romfs.sourceforge.net). - - The file ``apps/nshlib/rc.sysinit.template`` (OR, if - ``CONFIG_NSH_ARCHROMFS`` is defined - ``include/arch/board/rc.sysinit.template``. - The file ``apps/nshlib/rcS.template`` (OR, if - ``CONFIG_NSH_ARCHROMFS`` is defined - ``include/arch/board/rcs.template``. - - #. ``rc.sysinit.template``: The file ``apps/nshlib/rc.sysinit.template`` - contains the general form of the ``rc.sysinit`` file; configured - values are plugged into this template file to produce the final - ``rc.sysinit`` file. - - ``rcS.template``: The file ``apps/nshlib/rcS.template`` - contains the general form of the ``rcS`` file; configured - values are plugged into this template file to produce the final - ``rcS`` file. - -.. note:: - ``apps/nshlib/rcS.template`` and ``apps/nshlib/rc.sysinit.template`` - generates the standard, default ``nsh_romfsimg.h`` file. - If ``CONFIG_NSH_ARCHROMFS`` is defined in the NuttX configuration - file, then a custom, board-specific ``nsh_romfsimg.h`` file residing - in the ``boards////include`` directory will be - used. NOTE when the OS is configured, ``include/arch/board`` will be - linked to ``boards////include``. - -All of the startup-behavior is contained in ``rc.sysinit.template`` -and ``rcS.template``. The role of ``mkromfsimg.sh`` is to (1) apply -the specific configuration settings to ``rc.sysinit.template`` to create -the final ``rc.sysinit``, and ``rc.sysinit.template`` to create the final -``rcS`` and (2) to generate the header file ``nsh_romfsimg.h`` -containing the ROMFS file system image. - -**Further Information**. See the section on -:doc:`Customizing the NuttShell ` for additional, more detailed -information about the NSH start-up script and how to modify it. - diff --git a/Documentation/applications/testing/nand_sim/index.rst b/Documentation/applications/testing/nand_sim/index.rst new file mode 100644 index 0000000000000..cf5fb2cee84b8 --- /dev/null +++ b/Documentation/applications/testing/nand_sim/index.rst @@ -0,0 +1,171 @@ +====================================== +``nand`` - NAND Flash Device Simulator +====================================== + +In order to test the filesystems that work with NAND flash devices in a +simulator, this exists to provide a virtual NAND flash device, along with its +driver, to allow manual (or scripted) testing, as well as to provide an +option to log the various actions performed under-the-hood along with the +state of the device, which includes the read, write and erase counts of each +page in the device. + +Structure of NAND Flash +======================= + +Most NAND flashes share a common interface, specified by the +`Open NAND Flash Interface (ONFI) `_. + +The important part from it, required in this context, is that a NAND Flash is +divided into a lot of blocks. And each blocks are divided into a lot of +pages. + +Here's the peculiar bit. If you want to erase a page, you need to erase +the *entire* block that it is part of, ie. blocks are the smallest erasable +units in a NAND flash. However, a page is the smallest unit to which you can +write data, or read data from. + +Why would you need erase operation? The Program/ Erase (P/E) cycle states +that a page (and thus its block) need to be erased first before data can be +written to it (Erase-Before-Write). + +Each page has a data area, and a spare area. Depending on the data area's +size, the spare area may have different structures (schemes). All the +required schemes are defined in ``/drivers/mtd/mtd_nandscheme.c`` (in +the ``g_nand_sparescheme*`` structures). + +Due to the nature of NAND flash, upon testing, a manufaturer may decide that +a certain block fails some test(s), and mark it as a **bad block** by +writing a certain value in a certain position in the spare area (depends on +data area's size, and thus, the spare area's scheme) of every page in it. + +.. NOTE:: + * While certain blocks may *still work* even if they are marked as bad, + it's inadvisable to store any data in it. + + * The spare data is the **only** record of a block being bad or not. + Please do not erase it. + + * Certain blocks may become bad after continuous usage, and would need + to be marked as such by either the filesystem or the driver. + +Currently, this simulator supports only 512 B sized pages, which means it +will follow the ``g_nand_sparescheme512`` scheme for its spare area, and +thus have a bad block marker at index ``5``. + +If a block is *not* bad, it contains a value of ``0xff`` in the place of a +bad block marker. Any other value denote it's a bad block. + +RAM to Device (Lower Half) +========================== + +Since this is an emulation, RAM of the host running the simulator is used +to create the device. While the speed of operations won't be even close to +the original, this being in the RAM, which works multitudes faster than +actual device, the functionality on the other hand has been kept consistent +to the utmost. + +First, ``/include/nuttx/mtd/nand.h`` has a structure ``struct nand_dev_s`` +defining a raw NAND MTD device (lowest level). Its field ``nand_dev_s->raw`` +is of type ``struct nand_raw_s *`` (defined in +``include/nuttx/mtd/nand_raw.h``), and this is what will hold the methods +for the raw device. There are primarily 3 methods that need to be looked +into: + +* eraseblock +* rawread +* rawwrite + +Conforming to the functionality of NAND flashes, these three were implemented +as ``nand_ram_*`` in ``/drivers/mtd/nand_ram.c`` to emulate RAM into a +virtual NAND flash. + +While in real devices, the spare area follows the data area (in most schemes) +, since this is virtual, we can get away with keeping the two into two +separate arrays, namely ``nand_ram_flash_data`` and ``nand_ram_flash_spare`` +for data and spare respectively. Each array has as many elements as number +of pages in the device. + +As the spare areas has some spare bytes we can use, some space is used as +counters for the reads/writes/erases each page faces, thus giving a clear +picture of wear of the virtual device to the tester. + +.. NOTE:: + ECC extension has not been implemented yet, so ECC bits in spare are + yet to be used or initialized properly. + +The method ``nand_ram_initialize()`` takes in a preallocated space for a +raw device (of type ``struct nand_raw_s`` as defined in +``include/nuttx/mtd/nand_raw.h``) and attaches these 3 custom methods as well +as device information like page size, block size, etc. to it. These form +the lower half of the driver. + +Upper Half +========== + +The method ``nand_ram_initialize()`` also initializes a +``struct mtd_dev_s *`` (defined in ``include/nuttx/mtd/mtd.h``), which it +returns. This structure contains a reference to our custom lower half in +``mtd_dev_s->raw``, as well as an upper half containing methods ``nand_*`` +(defined in ``drivers/mtd/mtd_nand.c``). + +Wrapper Over Upper Half +======================= + +The upper half, along with the lower half attached to it, received from +``nand_ram_initialize()`` contains these 5 methods for the upper half: + +* erase +* bread +* bwrite +* ioctl +* isbad +* markbad + +Each driver's upper half needs to be registered with NuttX before it can +appear in the list of devices (in ``/dev``). Instead of the previously +acquired upper-half, we'll be registering a wrapper over it, to improve +logging. The wrapper methods are defined as ``nand_wrapper_*`` in +``drivers/mtd/mtd_nandwrapper.c``. + +Here's a complicated bit. The actual upper half is an MTD device, but +more specifically, it is a NAND MTD device, which is represented by +``struct nand_dev_s``. Due to how it is defined, ``struct mtd_dev_s`` forms +the very start of ``struct nand_dev_s``, and hence they can be type-casted +to each other (provided required memory is accessible). Our wrapper, being a +wrapper over an MTD device, is an MTD device itself as well. MTD device +methods take in a ``struct mtd_dev_s *dev`` which describe the device +itself (which is the actual device that is registered using +``register_mtddriver``), which includes its methods. Our wrapper methods +receive such a device as well, which contains the wrapper device including +the wrapper functions. But, this way, there is no way of accessing the +methods of the actual upper half itself. Thus, instead of ``dev`` being +of type ``struct nand_dev_s``, it is actually of type +``struct nand_wrapper_dev_s`` which is a superset of ``struct nand_dev_s``, +who itself is a superset of ``struct mtd_dev_s``. Similar to previous case, +``struct mtd_dev_s`` forms the very start of ``struct nand_wrapper_dev_s``, +and thus the types are inter-changeable. + +The methods ``nand_wrapper_*`` in ``drivers/mtd/mtd_nandwrapper.c`` all +pass the parameters to corresponding method of the actual upper half +after logging it. *But, the device passed on to the actual upper half +is still the wrapper, not the actual upper half, as the upper half methods +may call the other methods as well internally and we might want to log +them as well*. + +Registering Device & Daemon +=========================== + +This wrapper is then registered using ``register_mtddriver``, and this +whole thing is converted to be a daemon, so that the device can keep running +in the background. + +Making it a daemon is achieved by using ``fork()``, killing the parent, and +using ``daemon()`` in child. + +Known Issues +============ + +* ECC is not implemented yet. +* MLC NAND Flash is not implemented yet. +* Due to the fixed name of the device, there can't be more than one instance + of this virtual device. \ No newline at end of file diff --git a/Documentation/applications/wireless/i8sak/index.rst b/Documentation/applications/wireless/i8sak/index.rst index 22342e72ec635..d7bf623212fec 100644 --- a/Documentation/applications/wireless/i8sak/index.rst +++ b/Documentation/applications/wireless/i8sak/index.rst @@ -3,7 +3,7 @@ ================================================== Description ------------ +=========== The i8sak app is a useful CLI for testing various IEEE 802.15.4 functionality. It also serves as a starting place for learning how to interface with the NuttX @@ -30,7 +30,8 @@ _sticky_, meaning, if you set the endpoint short address once, any future operation using the endpoint short address can default to the previously used address. This is particularly useful to keep the command lengths down. -## How To Use +How To Use +========== The i8sak app has a series of CLI functions that can be invoked. The default i8sak command is ``i8`` to make things quick and easy to type. @@ -47,6 +48,11 @@ This will tell the MAC layer that it should now act as a PAN coordinator using PAN ID CD:AB. For now, this function assumes that we are operating a non-beacon enabled PAN, since, as of this writing, beacon-enabled networks are unfinished. +Configure PAN coordinator short address and EP short addres:: + + i8 set saddr 0A:00 + i8 set ep_saddr 0B:00 + Next, on the same device, run:: i8 acceptassoc @@ -117,7 +123,7 @@ similar to the following:: Dest. Address - 0xDEADBEEF00FADE0C Src. Address - 0xDEADBEEF00FADE0A Command Type - Association Response - Assigned SADDR - 0x000C + Assigned SADDR - 0x000B Assoc Status - Successful 3a) ACK diff --git a/Documentation/components/drivers/character/analog.rst b/Documentation/components/drivers/character/analog.rst deleted file mode 100644 index c8f8c754600b8..0000000000000 --- a/Documentation/components/drivers/character/analog.rst +++ /dev/null @@ -1,55 +0,0 @@ -======================== -Analog (ADC/DAC) Drivers -======================== - -The NuttX analog drivers are split into two parts: - -#. An "upper half", generic driver that provides the common analog - interface to application level code, and -#. A "lower half", platform-specific driver that implements the - low-level controls to implement the analog functionality. - -- General header files for the NuttX analog drivers reside in - ``include/nuttx/analog/``. These header files includes both the - application level interface to the analog driver as well as the - interface between the "upper half" and "lower half" drivers. -- Common analog logic and share-able analog drivers reside in the - ``drivers/analog/``. -- Platform-specific drivers reside in - ``arch//src/`` directory - for the specific processor ```` and for the - specific ```` analog peripheral devices. - -ADC Drivers ------------ - -- ``include/nuttx/analog/adc.h``. All structures and APIs needed - to work with ADC drivers are provided in this header file. This - header file includes: - - #. Structures and interface descriptions needed to develop a - low-level, architecture-specific, ADC driver. - #. To register the ADC driver with a common ADC character - driver. - #. Interfaces needed for interfacing user programs with the - common ADC character driver. - -- ``drivers/analog/adc.c``. The implementation of the common ADC - character driver. - -DAC Drivers ------------ - -- ``include/nuttx/analog/dac.h``. All structures and APIs needed - to work with DAC drivers are provided in this header file. This - header file includes: - - #. Structures and interface descriptions needed to develop a - low-level, architecture-specific, DAC driver. - #. To register the DAC driver with a common DAC character - driver. - #. Interfaces needed for interfacing user programs with the - common DAC character driver. - -- ``drivers/analog/dac.c``. The implementation of the common DAC - character driver. diff --git a/Documentation/components/drivers/character/analog/adc/adc1242/index.rst b/Documentation/components/drivers/character/analog/adc/adc1242/index.rst new file mode 100644 index 0000000000000..1eecf13d52e97 --- /dev/null +++ b/Documentation/components/drivers/character/analog/adc/adc1242/index.rst @@ -0,0 +1,11 @@ +========== +TI ADS1242 +========== + +ADS1242 24-Bit SPI powered ADC. This driver supports reading the ADC +conversionresult as well as configuring the ADC, setting the input channel, +etc. is implemented via ioctl calls. However, it does not yet implement +the standard ADC interface. + +- ``include/nuttx/analog/ads1242.h``. All structures and APIs needed + to work with DAtC drivers are provided in this header file. diff --git a/Documentation/components/drivers/character/analog/adc/ads7828/index.rst b/Documentation/components/drivers/character/analog/adc/ads7828/index.rst new file mode 100644 index 0000000000000..812c5e89d9e8e --- /dev/null +++ b/Documentation/components/drivers/character/analog/adc/ads7828/index.rst @@ -0,0 +1,9 @@ +========== +TI ADS7828 +========== + +ADS7828 12-Bit I2C powered ADC. This driver supports reading single or +multiple ADC conversion result as well as onfiguring the ADC, via ioctl calls. + +- ``include/nuttx/analog/ads7828.h``. All structures and APIs needed + to work with DAtC drivers are provided in this header file. diff --git a/Documentation/components/drivers/character/analog/adc/hx711/index.rst b/Documentation/components/drivers/character/analog/adc/hx711/index.rst new file mode 100644 index 0000000000000..648c4adf161fe --- /dev/null +++ b/Documentation/components/drivers/character/analog/adc/hx711/index.rst @@ -0,0 +1,221 @@ +======================== +Avia Semiconductor HX711 +======================== + +Driver contributed by Michał Łyszczek. + +HX711 is a 24bit ADC (Analog Digital Converter) designed for weight scales. +This chip can be very slow. With internal oscillator and RATE pin pulled +down, it outputs only 10 samples per second. To not hog down CPU, driver +uses interrupt to detect when chip is ready. This will make read(2) blocking, +but system can do whatever it needs before chip is ready. Because of that +driver does not fully follow ADC API, but rather standard character device +(read only). + +Values from tensometer can be easily read from shell with ``cat`` command + +.. code-block:: + + cat /dev/hxx711_0 + +Altough it may be better to dump values with example ``hx711`` program, +since ``cat`` will just read until the end of time, and if ctrl+c is +not working, it will steal shell forever. + +------- +reading +------- + +Reading is done by calling standard, posix, read(2) function. Only one value +can be returned with single call to read(2). But an averaging function can +be enabled, so that driver will read N samples, average them, and then will +return single averaged value. + +This function accepts two types of buffer. + +If buffer is of size ``sizeof(int32_t)`` a int32 value will be stored in +a buffer. If buffer size of bigger than ``sizeof(int32_t)`` function will +store string representation of values in passed buffer. + +Simple code to read and print value may look like this + +.. code-block:: C + + int fd; + fd = open("/dev/hx711_0", O_RDONLY); + + for (; ; ) + { + int32_t value; + value = read(fd, &value, sizeof(value)); + printf("Read: %"PRIi32"\n", value); + } + +----- +ioctl +----- + +Since this chip (and driver) is designed for weight scale, kernel driver +can provide some processing to make life easier for userspace code. These +functions are implemented via ioctl(2) commands. In practice, non of these +can be used, but if you just open driver and read it, you will get raw +values from hx711 chip, which you will have to process yourself. If your +needs are more standard, it's better to use kernel processing. + +HX711_SET_AVERAGE +----------------- + +.. code-block:: C + + unsigned average = 5; + ioctl(fd, HX711_SET_AVERAGE, average); + +Driver will read this number of samples from hx711 and will return average +value of them all. To avoid corrupted data due to integer overflow, max +average value that can be set is 225. If you need to average more values +you will need to write your own code for that. + +HX711_SET_CHANNEL +----------------- + +.. code-block:: C + + char channel = 'a'; + ioctl(fd, HX711_SET_CHANNEL, channel); + +HX711 has 2 channels, A and B, which can be swapped as necessary. Driver +automatically performs dummy read, so that next call to read(2) will return +value from new channel. When you switch to channel 'B', driver automatically +changes gain to 32 (the only possible value). Going back to 'A' will set +gain to 128. + +HX711_SET_GAIN +-------------- + +.. code-block:: C + + unsigned char gain = 128; + ioctl(fd, HX711_SET_GAIN, gain); + +Set gain. Channel 'A' supports gain "128" and "64". Channel 'B' has only +one gain option - 32. + +HX711_SET_VAL_PER_UNIT +---------------------- + +.. code-block:: C + + int val_per_unit = 813; + ioctl(fd, HX711_SET_VAL_PER_UNIT, val_per_unit); + +Driver can perform calculations so that you can read physical values like +grams, ounce or pounds, or your own artificial unit. You just need to specify +what value from tensometer coresponds to one unit. + +Say you have tensometer that has max value of 1'000'000. Value 100'000 means +1kg and sensor is fully linear. If you want to get readings in kg, you would +set ``val_per_unit`` to 100'000. If you wanted output in grams, it would be +value of 100. To have tenths of grams precision, you would set it to 10. +Driver does not care about unit, you just pick one and stick to it. + +Note that driver can only return integers, so if you set it to return unit +of kg, you will only get 1, 2, 3kg... and you won't be able to sense 0.5kg +or 1.5kg. For that you would have to set value to 10'000, and driver would +return you values of 15 (for 1.5kg) or 0.5 (for 0.5kg). + +HX711_TARE +---------- + +.. code-block:: C + + float precision = 0.1; + ioctl(fd, HX711_TARE, &precision); + +Every scale needs a tare function. Driver polls hx711 for some time, and if +it detects that scale is stable state, ioctl(2) will return with success, +and next read(2) call will take new tare value into consideration when +returning readings. Scale is assumed to be stable when several consecutive +readings are (min-max values) are within specified precition. + +If ``HX711_SET_VAL_PER_UNIT`` was set prior to this, you can pass value +in your unit. If you configured driver to work with grams, you can set +this value to 0.1 (gram) or 5 (gram). + +If driver cannot get stable reading within some time, it will return with +ETIME errno set. + +Important note, make sure you have set correct sign before taring, or +else you will double your tare value instead of zeroing it! + +HX711_SIGN +---------- + +.. code-block:: C + + int sign = -1; + ioctl(fd, HX711_SIGN, &sign); + +If values from drivers go lower when mass on scale goes higher you can swap +the sign. This may be necessary when tensometer was installed upside down. + +--------------------- +hx711 example program +--------------------- + +There is also companion program in Application Configuration ---> Examples +called ``HX711 driver example``. Main purpose of this is to show how to +use the driver, but it also is a very good tool for quickly debuging chip +from the shell, as it can dump readings and set all options. + +.. code-block:: + + -h print this help message + -d path to hx711 device, default: /dev/hx711_0 + -t tares the scale with specified precision, might take few seconds to complete. + If you set value per unit, precision is in units, otherwise it's raw values. + If units are used, float can be passed like 0.1 + -v value read that coresponds to one unit. This value has to be + calibrated first before it's known + -s reverse sign, if values decreses when mass increases, pass this + -D dumps current device settings (like, average, channel, gain etc.) + -a set how many samples should be averaged before returning value, + values [1..225] are valid + -c set channel to read (either 'a' or 'b' is valid) + -g set adc gain, for channel 'a' 64 and 128 are valid, + for channel 'b', only 64 is valid + -r read this number of samples before exiting, samples will be printed + on stdout as string, one sample per line + + Set values are persistant, as in once set they are stored in driver and + will be applied during execution of this program. + + If you specify only <-a|-c|-g|-v|-t> without -r, program will set new parameters + and exit. You can later call program again only with -r option to read + samples with previously set values. You can also pass all of them in one call + + To test if you require CONFIG_ADC_HX711_ADD_DELAY option set, run as: + hx711 -a225 -r128 + This will load hx711 chip long enough to show any possible errors due to + lack of added delay. + + Program executes in order: set options, tare, dump, run, so if you specify all + options, new settings will be applied, then new settings will be printed + and at the end program will tare the scale and print samples + + Examples: + + Set hx711 settings for first chip and exit: + hx711 -a32 -ca -g64 + + Dump chip settings from different chip + hx711 -d/dev/hx711_2 -D + + Read 10 samples with previously set hx711 settings + hx711 -r10 + + Change channel and read 32 samples (average setting won't change): + hx711 -cb -r32 + + Set value per unit, to get output in grams, and then tare with 10g precision + hx711 -v 813 -t 10 + diff --git a/Documentation/components/drivers/character/analog/adc/index.rst b/Documentation/components/drivers/character/analog/adc/index.rst new file mode 100644 index 0000000000000..c705cb1295fb5 --- /dev/null +++ b/Documentation/components/drivers/character/analog/adc/index.rst @@ -0,0 +1,142 @@ +=========== +ADC Drivers +=========== + +- ``include/nuttx/analog/adc.h``. All structures and APIs needed + to work with ADC drivers are provided in this header file. This + header file includes: + + #. Structures and interface descriptions needed to develop a + low-level, architecture-specific, ADC driver. + #. To register the ADC driver with a common ADC character + driver. + #. Interfaces needed for interfacing user programs with the + common ADC character driver. + +- ``drivers/analog/adc.c``. The implementation of the common ADC + character driver. + +Application Programming Interface +================================= + +The first necessary thing to be done in order to use the ADC driver from an +application is to include the correct header filer. It contains the +Application Programming Interface to the ADC driver. To do so, include: + + +.. code-block:: c + + #include + +ADC driver is registered as a POSIX character device file into ``/dev`` +namespace. It is necessary to open the device to get a file descriptor for +further operations. This can be done with standard POSIX ``open()`` call. + +Standard POSIX ``read()`` operation may be used to read the measured data from +the controller. The driver utilizes FIFO queue for received measurements +and ``read()`` operation gets data from this queue. Structure ``adc_msg_s`` +(or array of these structures) should be passed to buffer parameter of +``read()`` call. This structure represents one ADC measurement. + +.. c:struct:: adc_msg_s +.. code-block:: c + + begin_packed_struct struct adc_msg_s + { + /* The 8-bit ADC Channel */ + uint8_t am_channel; + /* ADC convert result (4 bytes) */ + int32_t am_data; + } end_packed_struct; + +User may perform polling operation on the driver with ``poll()`` call. +The controller also may be configured/controlled at run time with numerous +``ioctl()`` calls. Following commands are supported: + + * :c:macro:`ANIOC_TRIGGER` + * :c:macro:`ANIOC_WDOG_UPPER` + * :c:macro:`ANIOC_WDOG_LOWER` + * :c:macro:`ANIOC_GET_NCHANNELS` + * :c:macro:`ANIOC_RESET_FIFO` + * :c:macro:`ANIOC_SAMPLES_ON_READ` + +.. c:macro:: ANIOC_TRIGGER + +The ``ANIOC_TRIGGER`` command triggers one conversion. This call is used +when software trigger conversion is configured. The opposite to software +trigger is a hardware trigger. This may be some timer driver for example. + +.. c:macro:: ANIOC_WDOG_UPPER + +This command is used to set the upper threshold for the watchdog. + +.. c:macro:: ANIOC_WDOG_LOWER + +This command is used to set the lower threshold for the watchdog. + +.. c:macro:: ANIOC_GET_NCHANNELS + +The ``ANIOC_GET_NCHANNELS`` gets the number of used/configured channels +for given opened instance. This is the only portable way how to get +the number of channels from the driver. + +.. c:macro:: ANIOC_RESET_FIFO + +This ``ioctl`` command clears the FIFO queue in which measured data are stored. + +.. c:macro:: ANIOC_SAMPLES_ON_READ + +The ``ANIOC_SAMPLES_ON_READ`` returns number of samples/measured data waiting +in the FIFO queue to be read. + +It is possible for a controller to support its specific ioctl commands. These +should be described in controller specific documentation. + +Application Example +~~~~~~~~~~~~~~~~~~~ + +An example application can be found in ``nuttx-apps`` repository under +path ``examples/adc``. It is an example application that reads the data +from the defined number of channels. + +.. code-block :: bash + + nsh> adc + Sample: + 1: channel: 0 value 951 + 2: channel: 1 value 1879 + Sample: + 1: channel: 0 value 952 + 2: channel: 1 value 1880 + Sample: + 1: channel: 0 value 942 + 2: channel: 1 value 1800 + +Configuration +============= + +This section describes ADC driver configuration in ``Kconfig``. The reader +should refer to target documentation for target specific configuration. + +ADC peripheral is enabled by ``CONFIG_ANALOG`` and ``CONFIG_ADC`` options, +respectively. The user can configure FIFO queue size with configuration +option ``CONFIG_ADC_FIFOSIZE``. This variable defines the size of the +ADC ring buffer that is used to queue received ADC data until they can be +retrieved by the application by reading from the ADC character device. Since +this is a ring buffer, the actual number of bytes that can be +retained in buffer is (``CONFIG_ADC_FIFOSIZE - 1``). + +Configuration option ``CONFIG_ADC_NPOLLWAITERS`` defines number of +threads that can be waiting on poll. + +External Devices +================ + +NuttX also provides support for various external ADC devices. These usually +communicates with MCU with I2C or SPI peripherals. + +.. toctree:: + :maxdepth: 1 + :glob: + + */* diff --git a/Documentation/components/drivers/character/analog/adc/ltc1867l/index.rst b/Documentation/components/drivers/character/analog/adc/ltc1867l/index.rst new file mode 100644 index 0000000000000..8419d162418b4 --- /dev/null +++ b/Documentation/components/drivers/character/analog/adc/ltc1867l/index.rst @@ -0,0 +1,8 @@ +=============== +LTC 1863L/1867L +=============== + +LTC 1863L (12 bit) and LTC 1867L (16 bit) SPI powered ADC. + +- ``include/nuttx/analog/ltc1867l.h``. All structures and APIs needed + to work with DAtC drivers are provided in this header file. diff --git a/Documentation/components/drivers/character/analog/adc/max1161x/index.rst b/Documentation/components/drivers/character/analog/adc/max1161x/index.rst new file mode 100644 index 0000000000000..c8688247e825f --- /dev/null +++ b/Documentation/components/drivers/character/analog/adc/max1161x/index.rst @@ -0,0 +1,9 @@ +==================== +Maxim MAX11612-11617 +==================== + +MAX1161X 12-Bit I2C powered ADC Family. This driver supports reading single or +multiple ADC conversion result as well as configuring the ADC, via ioctl calls. + +- ``include/nuttx/analog/max1161x.h``. All structures and APIs needed + to work with DAtC drivers are provided in this header file. diff --git a/Documentation/components/drivers/character/analog/adc/pga11x/index.rst b/Documentation/components/drivers/character/analog/adc/pga11x/index.rst new file mode 100644 index 0000000000000..3557ac26f3fcd --- /dev/null +++ b/Documentation/components/drivers/character/analog/adc/pga11x/index.rst @@ -0,0 +1,8 @@ +=============== +TI PGA112/3/6/7 +=============== + +PGA112, PGA113, PGA116, PGA117 Zero-Drift PROGRAMMABLE GAIN AMPLIFIER with MUX. + +- ``include/nuttx/analog/pga11x.h``. All structures and APIs needed + to work with DAtC drivers are provided in this header file. diff --git a/Documentation/components/drivers/character/analog/dac/dac7554/index.rst b/Documentation/components/drivers/character/analog/dac/dac7554/index.rst new file mode 100644 index 0000000000000..30f327a7361a7 --- /dev/null +++ b/Documentation/components/drivers/character/analog/dac/dac7554/index.rst @@ -0,0 +1,5 @@ +========================= +Texas Instruments DAC7554 +========================= + +Texas Instruments DAC7554 DAC. This controller does not have API. diff --git a/Documentation/components/drivers/character/analog/dac/dac7571/index.rst b/Documentation/components/drivers/character/analog/dac/dac7571/index.rst new file mode 100644 index 0000000000000..a277f48b53899 --- /dev/null +++ b/Documentation/components/drivers/character/analog/dac/dac7571/index.rst @@ -0,0 +1,5 @@ +========================= +Texas Instruments DAC7571 +========================= + +Texas Instruments DAC7571 DAC. This controller does not have API. diff --git a/Documentation/components/drivers/character/analog/dac/index.rst b/Documentation/components/drivers/character/analog/dac/index.rst new file mode 100644 index 0000000000000..fc4c39c1f285a --- /dev/null +++ b/Documentation/components/drivers/character/analog/dac/index.rst @@ -0,0 +1,75 @@ +=========== +DAC Drivers +=========== + +- ``include/nuttx/analog/dac.h``. All structures and APIs needed + to work with DAtC drivers are provided in this header file. This + header file includes: + + #. Structures and inerface descriptions needed to develop a + low-level, architecture-specific, DAC driver. + #. To register the DAC driver with a common DAC character + driver. + #. Interfaces needed for interfacing user programs with the + common DAC character driver. + +- ``drivers/analog/dac.c``. The implementation of the common DAC + character driver. + +Application Programming Interface +================================= + +The first necessary thing to be done in order to use the DAC driver from an +application is to include the correct header filer. It contains the +Application Programming Interface to the PWM driver. To do so, include + +.. code-block:: c + + #include + +DAC driver is registered as a POSIX character device driver into ``/dev`` +namespace. It is necessary to open the device to get a file descriptor for +further operations. This can be done with standard POSIX ``open()`` call. + +Standard POSIX ``write()`` call is used to send data from an application to +a controller. Structure ``dac_msg_s`` is used to pass the data/samples. + +.. c:struct:: dac_msg_s +.. code-block:: c + + begin_packed_struct struct dac_msg_s + { + /* The 8-bit DAC Channel */ + uint8_t am_channel; + /* DAC convert result (4 bytes) */ + int32_t am_data; + } end_packed_struct; + +Application Example +~~~~~~~~~~~~~~~~~~~ + +An example application can be found in ``nuttx-apps`` repository under +path ``examples/dac``. It provides command line interface to write data +to DAC channels.s + +Configuration +============= + +This section describes DAC driver configuration in ``Kconfig``. The reader +should refer to target documentation for target specific configuration. + +The peripheral is enabled by ``CONFIG_ANALOG`` and ``CONFIG_DAC`` options, +respectively. The FIFO queue size is configurable with ``CONFIG_DAC_FIFOSIZE``. +This size is limited to ``255`` to fit into ``uint8_t``. + +External Devices +================ + +NuttX also provides support for various external DAC devices. These usually +communicates with MCU with I2C or SPI peripherals. + +.. toctree:: + :maxdepth: 1 + :glob: + + */* diff --git a/Documentation/components/drivers/character/analog/dac/mcp48xx/index.rst b/Documentation/components/drivers/character/analog/dac/mcp48xx/index.rst new file mode 100644 index 0000000000000..91b32d595c29f --- /dev/null +++ b/Documentation/components/drivers/character/analog/dac/mcp48xx/index.rst @@ -0,0 +1,8 @@ +=========================== +Microchip MCP4802/4812/4822 +=========================== + +Microchip MCP4802/4812/4822 DAC. + +- ``include/nuttx/analog/mcp48xx.h``. All structures and APIs needed + to work with DAtC drivers are provided in this header file. diff --git a/Documentation/components/drivers/character/analog/index.rst b/Documentation/components/drivers/character/analog/index.rst new file mode 100644 index 0000000000000..7d65b773725cb --- /dev/null +++ b/Documentation/components/drivers/character/analog/index.rst @@ -0,0 +1,29 @@ +======================== +Analog (ADC/DAC) Drivers +======================== + +The NuttX analog drivers are split into two parts: + +#. An "upper half", generic driver that provides the common analog + interface to application level code, and +#. A "lower half", platform-specific driver that implements the + low-level controls to implement the analog functionality. + +- General header files for the NuttX analog drivers reside in + ``include/nuttx/analog/``. These header files includes both the + application level interface to the analog driver as well as the + interface between the "upper half" and "lower half" drivers. +- Common analog logic and share-able analog drivers reside in the + ``drivers/analog/``. +- Platform-specific drivers reside in + ``arch//src/`` directory + for the specific processor ```` and for the + specific ```` analog peripheral devices. + +.. toctree:: + :caption: Supported Drivers + :maxdepth: 1 + + adc/index.rst + dac/index.rst + diff --git a/Documentation/components/drivers/character/index.rst b/Documentation/components/drivers/character/index.rst index 555b92bd0dc18..81639bcb90478 100644 --- a/Documentation/components/drivers/character/index.rst +++ b/Documentation/components/drivers/character/index.rst @@ -55,7 +55,7 @@ Character device drivers have these properties: :maxdepth: 2 1wire.rst - analog.rst + analog/index.rst bch.rst can.rst contactless.rst diff --git a/Documentation/components/drivers/character/quadrature.rst b/Documentation/components/drivers/character/quadrature.rst index cd8013217b731..739e7fada8ae7 100644 --- a/Documentation/components/drivers/character/quadrature.rst +++ b/Documentation/components/drivers/character/quadrature.rst @@ -28,3 +28,99 @@ following locations: for the specific processor ```` and for the specific ```` Quadrature Encoder peripheral devices. +Application Programming Interface +================================= + +The first thing to be done in order to use the quadrature encoder driver +from an application is to include the correct header filer. It contains the +Application Programming Interface to the driver. To do so, include + +.. code-block:: c + + #include + +Quadrature encoder driver is registered as a POSIX character device file +into ``/dev`` namespace. It is necessary to open the device to get a file +descriptor for further operations. This can be done with standard POSIX +``open()`` call. + +The driver is accessed only through ``ioctl`` interface, functions ``read`` +and ``write`` does not have any affect. Following ``ioctl`` commands are +available: + + * :c:macro:`QEIOC_POSITION` + * :c:macro:`QEIOC_RESET` + * :c:macro:`QEIOC_SETPOSMAX` + * :c:macro:`QEIOC_SETINDEX` + * :c:macro:`QEIOC_GETINDEX` + +.. c:macro:: QEIOC_POSITION + +This call gets the current position from the encoder driver. Argument +of the call is a pointer to ``int32_t`` variable. + +.. c:macro:: QEIOC_RESET + +This command resets the current encoder positition to zero. + +.. c:macro:: QEIOC_SETPOSMAX + +The ``QEIOC_SETPOSMAX`` call sets the maximum position for the encoder. +An argument is an ``uint32_t`` variable with the maximum position value. + +.. c:macro:: QEIOC_SETINDEX + +This ioctl sets the index position of the encoder. An argument is an +``uint32_t`` variable with the maximum position value. + +.. c:macro:: QEIOC_GETINDEX + +This ioctl gets the index position of the encoder. An argument is a +pointer to ``qe_index_s`` structure. + +.. c:struct:: qe_index_s +.. code-block:: c + + struct qe_index_s + { + /* Qencoder actual position */ + int32_t qenc_pos; + /* Index last position */ + int32_t indx_pos; + /* Number of index occurances */ + int16_t indx_cnt; + }; + +The pointer to this structure is used as an argument to ``QEIOC_GETINDEX`` +ioctl command. It gets the current encoder position, the last position of +index and the number of index occurances. + +Application Example +~~~~~~~~~~~~~~~~~~~ + +An example application can be found in ``nuttx-apps`` repository under +path ``examples/qencoder``. It demonstrates the basic data read +from an encoder device. + +.. code-block:: console + + nsh> qe + 1. 0 + 2. 0 + 3. 0 + 4. 1 + 5. 1 + 6. 1 + 7. 2 + 8. 2 + 9. 3 + +Configuration +============= + +This section describes qencoder driver configuration in ``Kconfig``. The +reader should refer to target documentation for target specific configuration. + +The ``CONFIG_SENSORS`` option has to be enabled in order to use the qencoder +peripheral. The peripheral itself is enabled by ``CONFIG_SENSORS_QENCODER`` +option. diff --git a/Documentation/components/drivers/character/timers/pwm.rst b/Documentation/components/drivers/character/timers/pwm.rst index 5d584afdea4e6..50483801ffa05 100644 --- a/Documentation/components/drivers/character/timers/pwm.rst +++ b/Documentation/components/drivers/character/timers/pwm.rst @@ -32,3 +32,181 @@ Files supporting PWM can be found in the following locations: in ``arch//src/`` directory for the specific processor ```` and for the specific ```` PWM peripheral devices. + +Application Level Interface +=========================== + +The first necessary thing to be done in order to use the PWM driver in an +application is to include the header file for the NuttX timer driver. It contains +the Application Level Interface to the PWM driver. To do so, include: + +.. code-block:: c + + #include + +PWM driver is registered as a POSIX character device file into ``/dev`` +namespace. It is necessary to open the device to get a file descriptor for +further operations. + +The PWM is accessed only through ``ioctl`` interface, functions ``read`` +and ``write`` does not have any affect. Following ``ioctl`` commands are +available: + + * :c:macro:`PWMIOC_SETCHARACTERISTICS` + * :c:macro:`PWMIOC_GETCHARACTERISTICS` + * :c:macro:`PWMIOC_START` + * :c:macro:`PWMIOC_STOP` + +.. c:macro:: PWMIOC_SETCHARACTERISTICS + +The ``PWMIOC_SETCHARACTERISTICS`` command sets PWM characteristics such as +frequency, duty cycle, dead times and so on. These characteristics are +set through ``pwm_info_s`` structure. + +.. c:struct:: pwm_info_s +.. code-block:: c + + struct pwm_info_s + { + /* Frequency of the pulse train */ + uint32_t frequency; + #ifdef CONFIG_PWM_MULTICHAN + /* Per-channel output state */ + struct pwm_chan_s channels[CONFIG_PWM_NCHANNELS]; + #else + /* Duty of the pulse train, "1"-to-"0" duration. + * Maximum: 65535/65536 (0x0000ffff) + * Minimum: 1/65536 (0x00000001) + */ + ub16_t duty; + #ifdef CONFIG_PWM_DEADTIME + /* Dead time value for main output */ + ub16_t dead_time_a; + /* Dead time value for complementary output */ + ub16_t dead_time_b; + #endif + #ifdef CONFIG_PWM_PULSECOUNT + /* The number of pulse to generate. 0 means to + * generate an indefinite number of pulses + */ + uint32_t count; + #endif + /* Channel polarity */ + uint8_t cpol; + /* Disabled channel polarity */ + uint8_t dcpol; + #endif /* CONFIG_PWM_MULTICHAN */ + /* User provided argument to be used in the lower half */ + FAR void *arg; + }; + +Structure ``pwm_chan_s`` holds the representation of one PWM channel +if multiple channels are used ( ``CONFIG_PWM_MULTICHAN`` is set). + +.. c:struct:: pwm_chan_s +.. code-block:: c + + struct pwm_chan_s + { + /* Duty of the pulse train, "1"-to-"0" duration. + * Maximum: 65535/65536 (0x0000ffff) + * Minimum: 1/65536 (0x00000001) + */ + ub16_t duty; + #ifdef CONFIG_PWM_OVERWRITE + /* Channel overwrite */ + bool ch_outp_ovrwr; + /* Channel overwrite value */ + bool ch_outp_ovrwr_val; + #endif + #ifdef CONFIG_PWM_DEADTIME + /* Dead time value for main output */ + ub16_t dead_time_a; + /* Dead time value for complementary output */ + ub16_t dead_time_b; + #endif + /* Channel polarity */ + uint8_t cpol; + /* Disabled channel polarity */ + uint8_t dcpol; + /* Channel number */ + int8_t channel; + }; + +Apart from duty cycle and frequency, the ``ioctl`` command allows to +set many other PWM characteristics. These functionalities might not be +supported by all PWM controllers and user should always refer to target +documentation in this case. + +If ``CONFIG_PWM_OVERWRITE`` is set and ``ch_outp_ovrwr`` is true, it is +possible to overwrite channel output with value set in ``ch_outp_ovrwr_val``. +Configuration option ``CONFIG_PWM_DEADTIME`` and fields ``dead_time_a`` +and ``dead_time_b`` provides an option to set dead time between complementary +outputs. This instructs the driver to automatically insert output activation +delay for complementary PWM outputs and is useful for H-bridge motor control +for example. + +User may also set default channel polarity ``cpol`` and disabled channel +polarity ``dcpol``. If set to zero, default controller values (or values +determined in the configuration) are used. Following defines can be used +to set the polarities: + +.. code-block:: c + + /* Not defined, the default output state is arch dependant */ + #define PWM_CPOL_NDEF 0 + /* Logical zero */ + #define PWM_CPOL_LOW 1 + /* Logical one */ + #define PWM_CPOL_HIGH 2 + + /* Not defined, the default output state is arch dependant */ + #define PWM_DCPOL_NDEF 0 + /* Logical zero */ + #define PWM_DCPOL_LOW 1 + /* Logical one */ + #define PWM_DCPOL_HIGH 2 + +.. c:macro:: PWMIOC_GETCHARACTERISTICS + +Command ``PWMIOC_GETCHARACTERISTICS`` operates the same way as +``PWMIOC_SETCHARACTERISTICS`` but it obtains currently set values +instead of setting them. + +.. c:macro:: PWMIOC_START + +The ``PWMIOC_START`` command starts the pulsed output. Characteristics +of PWM channels should be set before this operation. + +.. c:macro:: PWMIOC_STOPS + +The ``PWMIOC_STOPS`` command stops the pulsed output. + +Application Example +~~~~~~~~~~~~~~~~~~~ + +An example application can be found in ``nuttx-apps`` repository under the +path ``examples/pwm``. + +.. code-block :: bash + + nsh> pwm + +Configuration +============= + +This section describes common PWM configuration in ``Kconfig``. The reader +should refer to target documentation for target specific configuration. + +PWM is enabled by ``CONFIG_PWM`` configuration option. Option +``CONFIG_PWM_MULTICHAN`` selects support for multiple channels for one PWM +instance. If multiple channels are used, configuration option +``CONFIG_PWM_NCHANNELS`` defines the maximum number of channels per instance. +Each timer/controller may support fewer output channels than this value. + +Generation of pin overwrite is enabled by ``CONFIG_PWM_OVERWRITE`` option. +This supports generation of a pin overwrite with 0 or 1 without the need to +wait for an end of cycle. + +The ``CONFIG_PWM_DEADTIME`` option brings the possibility to introduce +dead time values between complementary PWM outputs. diff --git a/Documentation/components/drivers/index.rst b/Documentation/components/drivers/index.rst index 03bb7cc902f5b..401f7336ca04c 100644 --- a/Documentation/components/drivers/index.rst +++ b/Documentation/components/drivers/index.rst @@ -37,7 +37,7 @@ Subdirectories of ``nuttx/drivers`` 1wire device drivers. -* ``analog/`` :doc:`character/analog` +* ``analog/`` :doc:`character/analog/index` This directory holds implementations of analog device drivers. This includes drivers for Analog to Digital Conversion (ADC) as diff --git a/Documentation/components/drivers/special/usbhost.rst b/Documentation/components/drivers/special/usbhost.rst index 7c91c1ddc0dbd..4c32829c4a5e4 100644 --- a/Documentation/components/drivers/special/usbhost.rst +++ b/Documentation/components/drivers/special/usbhost.rst @@ -2,36 +2,36 @@ USB Host-Side Drivers ===================== -- ``include/nuttx/usb/usbhost.h``. All structures and APIs - needed to work with USB host-side drivers are provided in this - header file. - -- ``struct usbhost_driver_s`` and - ``struct usbhost_connection_s``. Each USB host controller - driver must implement an instance of - ``struct usbhost_driver_s`` and - ``struct usbhost_connection_s``: ``struct usbhost_driver_s`` - provides the interface between the USB host driver and the USB - class driver; ``struct usbhost_connection_s`` provides the - interface between the USB host driver and platform-specific - connection management and device enumeration logic. These - structures are defined in ``include/nuttx/usb/usbhost.h``. +- **USB host controller driver** abstracts the host controller + device in the target chip. Each USB host controller driver + must implement an instance of ``struct usbhost_driver_s`` and + ``struct usbhost_connection_s`` defined in + ``include/nuttx/usb/usbhost.h``. + + - ``struct usbhost_driver_s`` provides the interface between + the USB host driver and the USB host class driver. + + - ``struct usbhost_connection_s`` provides the interface between + the USB host driver and platform-specific connection management + and device enumeration logic. + **Examples**: ``arch/arm/src/lpc17xx_40xx/lpc17_40_usbhost.c``, ``arch/arm/src/stm32/stm32_otgfshost.c``, ``arch/arm/src/sama5/sam_ohci.c``, and ``arch/arm/src/sama5/sam_ehci.c``. -- ``struct usbhost_class_s``. Each USB host class driver must - implement an instance of ``struct usbhost_class_s``. This - structure is also defined in ``include/nuttx/usb/usbhost.h``. +- **USB host class driver** abstracts USB peripherals conected to + the USB host controller. Each USB host class driver must implement + an instance of ``struct usbhost_class_s`` defined also in + ``include/nuttx/usb/usbhost.h``. **Examples**: ``drivers/usbhost/usbhost_storage.c`` - **USB Host Class Driver Registry**. The NuttX USB host infrastructure includes a *registry*. During its initialization, each USB host class driver must call the - interface, ``usbhost_registerclass()`` in order add its + interface, ``usbhost_registerclass()`` in order to add its interface to the registry. Later, when a USB device is connected, the USB host controller will look up the USB host class driver that is needed to support the connected device in @@ -84,7 +84,7 @@ USB Host-Side Drivers **Examples**: The function ``usbhost_msc_initialize()`` in the file ``drivers/usbhost/usbhost_storage.c`` - #. Each application must include a *waiter* thread thread that + #. Each application must include a *waiter* thread that (1) calls the USB host controller driver's ``wait()`` to detect the connection of a device, and then (2) call the USB host controller driver's ``enumerate`` method to bind the diff --git a/Documentation/components/filesystem/fat.rst b/Documentation/components/filesystem/fat.rst index 326f45803114d..b5bd021c34571 100644 --- a/Documentation/components/filesystem/fat.rst +++ b/Documentation/components/filesystem/fat.rst @@ -2,4 +2,186 @@ FAT === -Support for FAT filesystem. +File Allocation Table (FAT) is a very simple file system designed by Microsoft +and, as the name suggests, it uses a table to track clusters on a storage +volume. There have been multiple versions of FAT, like ``FAT12``, ``FAT16``, +and lastly ``FAT32`` to consider for growing data volumes. Even though FAT +has been superseded by more recent file systems in most Windows computers, +current Windows editions, macOS, Linux, Unix as well as Apache NuttX support +FAT. It is still used for floppy disks, USB flash drives as well as for +storage media in smaller, portable devices like digital cameras. + +FAT uses a magic number ``0x4D44``, and has been named as ``vfat`` in the +codebase, due to the implementation being actually VFAT, which is an extension +that allows for long file names. This page contains information about the FAT +file system from the perspective of the implementation of FAT that exists in +NuttX. + +FAT Structure +============= + +The number beside ``FAT`` (eg. ``16`` in ``FAT16``) represents the number of +bits used for each entry in the allocation table. A FAT volume has multiple +sections: + +* **Master Boot Record**: Master Boot Record (MBR) or Boot Sector contains + information needed by the file system to access the volume, including the + volume's layout and file system structure, akin to a superblock in Linux + file systems. +* **Allocation Table Region**: Stores the file allocation table, as well as + its copy which acts as a backup. The file allocation table keeps a track of + all the clusters in the volume, and thus has one entry for each cluster. +* **Root Directory**: It stores a directory table containing entries + describing the files and directories stored on the volume. Each entry + contains metadata about file system objects. + +.. NOTE:: + Root Directory exists as a separate section if the volume is for ``FAT12`` + or ``FAT16``, right after the Allocation Table Region and has a fixed upper + limit to the number of entries. ``FAT32`` does not have a dedicated region + for the Root Directory, but has it incorporated into the following Data + Region, and thus ``FAT32`` does not have any hard coded upper limit to the + number of entries. + +* **Data Region**: This region stores the actual data of the files as well as + directory data. Data Region is divided into multiple clusters, which are + numbered sequentially and have corresponding entries in the allocation + table. Cluster sizes can vary depending on the volume size as well as on + the type of the FAT file system. + +The first entry in the Allocation Table is for the volume's FAT ID while the +second entry indicates that the cluster is reserved. Given that ``FAT32`` does +not have a dedicated Root Directory section, in ``FAT32`` volume, the third +entry points to the root directory. + +File names can be either `short `_ +(also known as 8.3 filename or SFN), or long (LFN), till a maximum length +limit. + +Master Boot Record (MBR) +======================== + +The Boot Record may be one of two types. One is a much older type which does +not contain partitions, and one more recent with them. One distinguishing +feature of FAT is that all MBRs contain ``0x55AA`` at an offset of 510 from +the start, which can be used to determine the type of FAT being used in the +block device. + +For the older type, the MBR exists at the start of the drive. It does not +contain any partitions. + +The newer type has a partition table at an offset of 446 from the start of +the drive. It allows for 4 primary partitions. It has FAT Boot Records (FBRs) +at the start of every partition, which, for most parts, are identical in +structure to the older MBRs. + +Partition Table Entries +======================= + +The partition table contains information for 4 primary partitions, each +partition having entries in the table of 16 bytes each. These have various +information about the partition including, but not limited to, type of the +partition, starting sector, and partition size. + +Allocation Table +================ + +The allocation table follows the boot record, and has an entry for each +cluster available in the data region. Each entry has a size defined by the +file system type. ``FAT12`` has 12 byte long entries, ``FAT16`` has 16 byte +entries and ``FAT32`` has 32 byte entries. + +File data is made up of a linked list (or chain) of clusters. Entries in the +allocation table, which correspond to actual clusters, contain the cluster +number of the next cluster that appears in the file. The last cluster of a +file has a value in their allocation table entry such that all of its bits +are set (``0xFFF`` for FAT12, ``0xFFFF`` for FAT16, ``0xFFFFFFFF`` for FAT32). + +The starting cluster (head of the file chain) is pointed to by the directory +entry of that file. + +Directory Entires +================= + +A directory is basically a file which has a table that contains directory +entries that contain the metadata about the files and subdirectories in it. +Each directory entry describes a file or a subdirectory inside the directory. + +Root directory in FAT12/16 have a dedicated region, separate from the data +area. In FAT32, root directory is just like a regular directory in the data +region (ie. without any dedicated region) except for: + +* Its starting cluster is denoted in the boot record. +* It is not pointed to by any other directory. +* It has no entries corresponding to ``.`` and ``..`` (all non-root + directories have both of these entries). + +Directory entries are 32 bytes long, and start with an 11 bytes long SFN. The +rest of the directory entry contain information like the file attributes, +timestamps of creation as well as access and write, cluster number and +file size, to name a few. + +8.3 filename +------------ + +The first byte of a directory's 8.3 filename (and hence first byte of the +entire directory entry) has a special meaning. It has 3 possible values: + +* ``0xe5`` : Denotes that the current directory entry is empty. +* ``0x00`` : Denotes that this entry, as well as all following entries, are + empty. +* ``0x05`` : Actual value is ``0xe5``. + +The rest of the 7 + 3 byte of the directory entry are for the name (with +extension). + +Files +===== + +The starting cluster of data in a file is pointed by the directory entry of +the file. + +File allocation is very primitive in FAT, and the first available location in +the volume is given to a file. + +File attributes +-------------------- + +File attributes are denoted by a bit flag of the size of a single byte. +The file flags in FAT, with their bit representation, are as follows: + +.. list-table:: File Attributes + :header-rows: 1 + + * - Attribute Macro + - Bit representation + - Hex value + * - ``FATATTR_READONLY`` + - ``00000001`` + - 0x1 + * - ``FATATTR_HIDDEN`` + - ``00000010`` + - 0x2 + * - ``FATATTR_SYSTEM`` + - ``00000100`` + - 0x4 + * - ``FATATTR_VOLUMEID`` + - ``00001000`` + - 0x8 + * - ``FATATTR_DIRECTORY`` + - ``00010000`` + - 0x10 + * - ``FATATTR_ARCHIVE`` + - ``00100000`` + - 0x20 + +Out of these, FAT exposes a user to ``FATATTR_READONLY``, ``FATATTR_HIDDEN``, +``FATATTR_SYSTEM`` and ``FATATTR_ARCHIVE`` to the user. + +Implementation +============== + +The Apache NuttX implementation of VFAT can be found in: + +* ``fs/fat`` directory. +* ``include/nuttx/fs/fat.h`` header file. \ No newline at end of file diff --git a/Documentation/components/filesystem/index.rst b/Documentation/components/filesystem/index.rst index b9e120f2251d9..943e3f54e9ff6 100644 --- a/Documentation/components/filesystem/index.rst +++ b/Documentation/components/filesystem/index.rst @@ -2,9 +2,10 @@ NuttX File System ================= -**Overview**. NuttX includes an optional, scalable file system. -This file-system may be omitted altogether; NuttX does not depend -on the presence of any file system. +NuttX includes an optional, scalable file system. This file-system may be +omitted altogether; NuttX does not depend on the presence of any file system. + +.. _root_fs: **Pseudo Root File System**. A simple *in-memory*, *pseudo* file system can be enabled by default. This is an *in-memory* file @@ -18,8 +19,7 @@ system). Any user supplied data or logic can be accessed via the pseudo-file system. Built in support is provided for character and -block `drivers <#DeviceDrivers>`__ in the ``/dev`` pseudo file -system directory. +block drivers in the ``/dev`` pseudo file system directory. **Mounted File Systems** The simple in-memory file system can be extended my mounting block devices that provide access to true @@ -41,6 +41,492 @@ pseudo file systems may be mounted in the true, root file system. The approach selected by NuttX is intended to support greater scalability from the very tiny platform to the moderate platform. +Virtual File System (VFS) +========================= + +Virtual File System provides a unified interface for various file systems to +be able to co-exist together by exposing a blueprint that each file system +needs to implement. This also allows the file system to be free from worry +about the device driver implementations for storage devices, as they also +expose a unified way of accessing the underlying devices. + +How VFS works +------------- + +Threads are controllable sequences of instruction execution with their own +stacks. Each task in NuttX is represented by a Task Control Block (TCB) (TCB +is defined in ``include/nuttx/sched.h``) and tasks are organized in task +lists. + +All threads that are created by ``pthread_create()`` are part of the same task +group. A task group (defined in ``include/nuttx/sched.h``) is a shared +structure pointed to by the TCBs of all the threads that belong to the same +task group, and this task group contains all the resources shared across the +task group which includes *file descriptors* in the form of a **file list**. + +A file list (defined in ``include/nuttx/fs/fs.h``) contains file structures +that denote open files (along with a spinlock to manage access to the file +list). With the devices listed in the :ref:`root file system ` (on +points like ``/dev/led``, ``/dev/mmcsd0``, etc. which are henceforth called +blockdriver mount points) in an unmounted state, storage devices can be +mounted using the ``mount()`` command (to any point like ``/dir/abcd``) with +any specific supported file system, which internally calls its implemented +``mountpt_operations->bind()`` method and passes the blockdriver's mount +point inode to it, thus creating a **mount point**. The blockdriver mount +point inode will have a ``mountpt->i_private`` which contains any (file system +dependent) information about the mount and is to be filled by the file system +during the execution of ``mountpt_operations->bind()`` (and usually this data +includes a pointer to the blockdriver mount point as well). After that, +according to system calls, the other exposed functions of the filesystem +are called as per need. + +VFS Interface +------------- + +VFS allows file systems to expose their own implementations of methods +belonging to a unified interface: + +* **File operations** + +.. c:function:: int open(FAR struct file *filep, FAR const char *relpath, int oflags, mode_t mode) + + Opens a file. Files are required to be opened before any other file + operations are performed on it. + + :param FAR struct file * filep: Open file's file structure pointer. The + ``filep->f_priv`` member needs to be set here with the file system + specific data that represents an open file. + :param FAR const char * relpath: Relative path of the file from the root of + the mounted file system. + :param int oflags: Flags in a bit field that specify the mode for openning + the file (eg. ``O_RDONLY``, ``O_RDWR``, etc. defined in + ``include/fcntl.h``). + :param mode_t mode: Specifies the mode (permissions). If ``oflags`` include + ``O_CREAT``, then this contains the mode for the file to be created. + :returns: Status of openning a file. + :retval OK (0): Success. + :retval < 0: Error. + +.. c:function:: int close(FAR struct file *filep) + + This closes the opened file, and ideally syncs all the changes to the file + to be written to the disk, as well as free the memory allocated to store the + open file's data. + + :param FAR struct file * filep: Open file's file structure pointer. + :returns: Status of closing a file. + :retval OK (0): Success. + :retval < 0: Error. + +.. c:function:: ssize_t read(FAR struct file *filep, FAR char *buffer, size_t buflen) + + Reads maximum ``buflen`` bytes from an opened file (from the current offset + the opened file descriptor is pointing at if the file system supports + seeking). + + :param FAR struct file * filep: Open file's file structure pointer. + :param FAR char * buffer: Buffer to store the read data. + :param size_t buflen: Length of the maximum number of bytes to be read. + :returns: Number of bytes read. + :retval > 0: Size of bytes read. + :retval < 0: Error. + +.. c:function:: ssize_t write(FAR struct file *filep, FAR const char *buffer, size_t buflen) + + Writes maximum ``buflen`` bytes to an opened file (from the current offset + the opened file is at if the file system supports seeking). + + :param FAR struct file * filep: Open file's file structure pointer. + :param FAR char * buffer: Buffer which contains the data to be written. + :param size_t buflen: Length of the maximum number of bytes to be written. + :returns: Number of bytes written. + :retval > 0: Size of bytes written. + :retval < ``buflen``: Insufficient storage or file size limit reached + :retval < 0: Error. + +.. NOTE:: + POSIX requires that a ``read()`` after a ``write()`` should get the newly + written data, but not all file systems conform to POSIX, especially as + POSIX requires atomic writes, which is not usually implemented + as it can impact performance. + + To be POSIX compliant in concurrent situations, either the writes have to + be atomic, or read is blocked with a lock until an on-going write is + finished, which, as stated, would impact performance. + +.. c:function:: off_t seek(FAR struct file *filep, off_t offset, int whence) + + Underlying implementation of ``lseek()``, it allows the open file's file + structure to point to any particular location in the file. + + :param FAR struct file * filep: Open file's file structure pointer. + :param off_t offset: The offset required. + :param int whence: This controls how the offset it applied. It can have + values (defined in ``/include/sys/types.h``): + + * SEEK_SET: Offset from start of file. + * SEEK_CUR: Offset from current location in file. + * SEEK_END: Offset *after* end of file. + +.. NOTE:: + + According to POSIX, ``lseek()`` to any point after the end of the file + *does not* by itself increase the size of the file. Later writes to this + part will, however, increase it to at least the end of the written data, and + the "gap" before this written data should be filled with ``\0`` in case of + any reads after such a write operation. + +.. c:function:: int ioctl(FAR struct file *filep, int cmd, unsigned long arg) + + It is the underlying implementation of ``ioctl()`` (I/O Control). + ``ioctl()`` manipulates the underlying device parameters of files. + + :param FAR struct file * filep: Open file's file structure pointer. + :param int cmd: It can take a variety of values (which are defined in + ``include/nuttx/fs/ioctl.h``). It represents the command that will be + carried out on the file. Both the filesystem, as well as the device driver + needs to support the command in order for the function to run. + :param unsigned long arg: Additional argument that may be required for + ioctl. Details for what is required is written in the comments beside + the desired ioctl command in ``include/nuttx/fs/ioctl.h``. + :returns: Status of ioctl operation. + :retval OK (0): Success. + :retval < 0: Error. + +.. c:function:: int mmap(FAR struct file *filep, FAR struct mm_map_entry_s *map) + + Underlying implementation of ``mmap()``. ``mmap()`` creates a new mapping + in the virtual address space of the calling process. + + :param FAR struct file * filep: Open file's file structure pointer. + :param FAR struct mm_map_entry_s * map: mmap entry strucutre pointer, which + includes the virtual address. + :returns: Status of mmap operation. + :retval OK (0): Success. + :retval < 0: Error. + +.. NOTE:: + NuttX operates in a flat open address space. Therefore, it generally does + not require ``mmap()`` functionality. There are two notable exceptions where + ``mmap()`` functionality is required: + + 1. ``mmap()`` is the API that is used to support direct access to random + access media under the following very restrictive conditions: + + a. The filesystem implements the mmap file operation. Any file + system that maps files contiguously on the media should support + this ioctl. (vs. file system that scatter files over the media + in non-contiguous sectors). As of this writing, ROMFS is the + only file system that meets this requirement. + + b. The underlying block driver supports the BIOC_XIPBASE ioctl + command that maps the underlying media to a randomly accessible + address. At present, only the RAM/ROM disk driver does this. + + 2. If CONFIG_FS_RAMMAP is defined in the configuration, then mmap() will + support simulation of memory mapped files by copying files whole + into RAM. + +.. c:function:: int truncate(FAR struct file *filep, off_t length) + + Shrinks or expands the file to be of the desired size. + + :param FAR struct file * filep: Open file's file structure pointer. + :param off_t length: Final size of the file. + :returns: Status of truncate operation. + :retval OK (0): Success. + :retval < 0: Error. + + +.. c:function:: int poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup) + + Underlying implementation of ``poll()``. The ``poll()`` function provides + applications with a mechanism for multiplexing input/output over a set of + file descriptors. + + :param FAR struct file * filep: Open file's pointer. + :param FAR struct pollfd * fds: The structure describing the events to be + monitored, OR NULL if this is a request to stop monitoring events. + :param bool setup: true: Setup up the poll; false: Teardown the poll + :returns: Status of poll operation. + :retval OK (0): Success. + :retval < 0: Error. + +* **Additional open file specific operations** + +.. c:function:: int sync(FAR struct file *filep) + + This synchronizes the on-disk file system state of the file with the + in-memory file system state, ie. commits the file system caches to the disk. + + :param FAR struct file * filep: Open file's ``struct file`` (defined in + ``include/nuttx/fs/fs.h``) pointer. + :returns: Status of syncing a file. + :retval OK (0): Success. + :retval < 0: Error. + +.. c:function:: int dup(FAR const struct file *oldp, FAR struct file *newp) + + Duplicate an open file structure. + + :param FAR const struct file * oldp: Pointer to structure that is to be + duplicated. + :param FAR struct file * newp: Pointer to structure in which the duplicate + data will be stored. + :returns: Status of duplicating open file's structure. + :retval OK (0): Success. + :retval < 0: Error. + +.. c:function:: int fstat(FAR const struct file *filep, FAR struct stat *buf) + + Obtain information about an open file. + + :param FAR const struct file * filep: Open file's pointer. + :param FAR struct stat * buf: Pointer to the ``struct stat`` (defined in + ``include/sys/stat.h``). + :returns: Status of obtaining open file's information. + :retval OK (0): Success. + :retval < 0: Error. + +.. c:function:: int fchstat(FAR const struct file *filep, FAR const struct stat *buf, int flags) + + Change file stats. It can change the mode, timestamps and ownership. + + :param FAR struct file * filep: Open file's pointer. + :param FAR const struct stat * buf: Pointer to stat structure describing + the values that need to be updated. + :param int flags: Bit field that can include (defined in + ``include/nuttx/fs/fs.h``): + + * ``CH_STAT_MODE`` + * ``CH_STAT_UID`` + * ``CH_STAT_GID`` + * ``CH_STAT_ATIME`` + * ``CH_STAT_MTIME`` + + This describes what needs to be updated. + :returns: Status of changin open file's stats. + :retval OK (0): Success. + :retval < 0: Error. + +* **Directory operations** + +.. c:function:: int opendir(FAR struct inode *mountpt, FAR const char *relpath, FAR struct fs_dirent_s **dir) + + Opens a directory stream for the provided directory. Other directory + operations can be used after this to do various directory related operations + . We say the directory stream points to the first entry, but you need + ``readdir()`` to read the first entry. + + :param FAR struct inode * mountpt: Mount point inode of the file system. + :param FAR const char * relpath: Relative path from the root of the point + point of the directory. + :param FAR struct fs_dirent_s ** dir: A directory stream structure pointer + which needs to be populated with the required fields (defined in + ``include/nuttx/fs/fs.h``). + :returns: Status of openning the directory. + :retval OK (0): Success. + :retval < 0: Error. + +.. c:function:: int closedir(FAR struct inode *mountpt, FAR struct fs_dirent_s *dir) + + Closes a directory stream, as well as deallocates any memory used while + while openning a directory stream. + + :param FAR struct inode * mountpt: Mount point inode of the file system. + :param FAR struct fs_dirent_s ** dir: A directory stream structure pointer + which was previously allocated (and needs to be freed). + :returns: Status of closing the directory. + :retval OK (0): Success. + +.. c:function:: int readdir(FAR struct inode *mountpt, FAR struct fs_dirent_s *dir, FAR struct dirent *entry) + + This reads the next directory entry in a directory stream. If the stream + points to the base of the directory, then the first directory entry in the + directory is given. + + :param FAR struct inode * mountpt: Mount point inode of the file system. + :param FAR struct fs_dirent_s ** dir: A directory stream structure pointer. + :param FAR struct dirent * entry: Pointer to the directory entry. This will + be modified to point to the directory entry after it in the directory. + :returns: Status of reading the directory. + :retval OK (0): Success. + :retval < 0: Error. + +.. c:function:: int rewinddir(FAR struct inode *mountpt, FAR struct fs_dirent_s *dir) + + Resets the directory stream back to the first entry, like it was after + openning. + + :param FAR struct inode * mountpt: Mount point inode of the file system. + :param FAR struct fs_dirent_s ** dir: A directory stream structure pointer. + :returns: Status of rewinding the directory. + :retval OK (0): Success. + :retval < 0: Error. + +* **Volume-relations operations** + +.. c:function:: int bind(FAR struct inode *blkdriver, FAR const void *data, FAR void **handle) + + This is where the file system related data is initialized, and + is part of the mount process. + + :param FAR struct inode * blkdriver: Pointer to the block driver's device + inode. This needs to be opened in this function. + :param FAR const void * data: The options provided during mount. + :param FAR void ** handle: Whatever data ``handle`` points to is attached + to the ``mountpt`` inode after this function is called during the mount + process. This way, this file system's other methods can receive + this information if they have access to ``mountpt`` inode, by accessing + ``mountpt->i_private``. + :returns: Status of binding operation. + :retval OK (0): Success. + :retval < 0: Error. + +.. c:function:: int unbind(FAR void *handle, FAR struct inode **blkdriver, unsigned int flags) + + This is part of the unmounting process. The file system first + needs to assess the flags passed to it and appropriately do the tasks + required by these flags, and then it needs to free the private data + (``handle`` and any allocated members), as well as close the + previously-opened (during mount) block driver's inode. + + :param FAR void * handle: Private data of the file-system. + :param FAR struct inode ** blkdriver: The device inode of the block driver's + device inode. + :param unsigned int flags: Flags dictate the actions needed to be carried + out before the file system data is removed and the block driver inode is + closed. The values can be (as defined in ``include/sys/mount.h``): + + * ``MNT_FORCE`` + * ``MNT_DETACH`` + * ``MNT_EXPIRE`` + * ``UMOUNT_NOFOLLOW`` + + :returns: Status of unbinding operation. + :retval OK (0): Success. + :retval < 0: Error. + +.. c:function:: int statfs(FAR struct inode *mountpt, FAR struct statfs *buf) + + Provides stats for that instance of the file system. The exact + stats that are provided can be viewed in the members of + ``struct statfs`` (in file ``include/sys/statfs.h``). + + :param FAR struct inode * mountpt: Mount point inode of the file system. + :param FAR struct statfs * buf: Buffer that needs to be filled with the + relevant file system information. + :returns: Status of finding the filesystem stats operation. + :retval OK (0): Success. + :retval < 0: Error. + + +* **Path operations** + +.. c:function:: int unlink(FAR struct inode *mountpt, FAR const char *relpath) + + Removes a file, specifically, removes a name from the file system. + + :param FAR struct inode * mountpt: Mount point inode of the file system. + :param FAR const char * relpath: The relative path of the file from the root + of the file system. + :returns: Status of unlinking operation. + :retval OK (0): Success. + :retval < 0: Error. + +.. c:function:: int mkdir(FAR struct inode *mountpt, FAR const char *relpath, mode_t mode) + + Creates a directory. + + :param FAR struct inode * mountpt: Mount point inode of the file system. + :param FAR const char * relpath: Relative path of the new directory from the + root of the file system. + :param mode_t mode: The mode (permissions) for the directory. + :returns: Status of creating a directory operation. + :retval OK (0): Success. + :retval < 0: Error. + +.. c:function:: int rmdir(FAR struct inode *mountpt, FAR const char *relpath) + + Removes a directory. + + :param FAR struct inode * mountpt: Mount point inode of the file system. + :param FAR const char * relpath: Relative path of the directory from the + root of the file system. + :returns: Status of removing a directory operation. + :retval OK (0): Success. + :retval < 0: Error. + +.. c:function:: int rename(FAR struct inode *mountpt, FAR const char *oldrelpath, FAR const char *newrelpath) + + Renames a file or a directory + + :param FAR struct inode * mountpt: Mount point inode of the file system. + :param FAR const char * oldrelpath: Existing path of the file or directory. + :param FAR const char * newrelpath: New path of the file or directory. + :returns: Status of renaming a file or a directory operation. + :retval OK (0): Success. + :retval < 0: Error. + +.. c:function:: int stat(FAR struct inode *mountpt, FAR const char *relpath, FAR struct stat *buf) + + Information about a file or a directory. The exact information that is + provided can be viewed in the members of ``struct stat`` + (in file ``include/sys/stat.h``). + + :param FAR struct inode * mountpt: Mount point inode of the file system. + :param FAR const char * relpath: Relative path of the file or directory from + the root of the file system. + :param FAR struct stat * buf: Buffer that needs to be filled with the + relevant file or directory information. + :returns: Status of finding information about a file or directory.1 operation. + :retval OK (0): Success. + :retval < 0: Error. + +.. c:function:: int chstat(FAR struct inode *mountpt, FAR const char *relpath, FAR const struct stat *buf, int flags) + + Change the stats of a file or directory. + + :param FAR struct inode * mountpt: Mount point inode of the file system. + :param FAR const char * relpath: Relative path of the file or directory from + the root of the file system. + :param FAR const struct stat * buf: Contains the new stat information. Access + only the ones that are required according to the flags. + :param int flags: A bit field that can have values including ``CH_STAT_MODE`` + , ``CH_STAT_UID``, ``CH_STAT_GID``, ``CH_STAT_ATIME`` or ``CH_STAT_MTIME`` + which are or-ed together. + +.. c:function:: int syncfs(FAR struct inode *mountpt) + + This works like ``sync()`` but instead of the file, it syncs the entire + filesystem's metadata. + + :param FAR struct inode * mountpt: Mount point inode of the file system. + :returns: Status of syncing file system metadata operation. + :retval OK (0): Success. + :retval < 0: Error. + + +The file systems can have their own implementations for these functions +under-the-hood, but the user does not have to worry about the underlying file +system during file I/O, as the file system has to expose its implementations +in a unified interface. + +.. NOTE:: + Each file system has to globally expose their implementations of the unified + interface as defined by ``struct mountpt_operations`` (in + ``include/fs/fs.h``) to one of the lists defined in ``fs/mount/fs_mount.c`` + depending on the type of the file system. + + They also need their own `magic number `_ + to be listed in ``include/sys`` and in ``fs_gettype`` function (in + ``fs/mount/fs_gettype.c``) for identification of the filesystem. + + +File systems +============ + +NuttX provides support for a variety of file systems out of the box. .. toctree:: :maxdepth: 1 @@ -65,3 +551,18 @@ scalability from the very tiny platform to the moderate platform. unionfs.rst userfs.rst zipfs.rst + +FS Categories +------------- + +File systems can be divided into these categories on the basis of the drivers +they require: + +1. They require a block device driver. They include vfat, romfs, smartfs, and + littlefs. +2. They require MTD drivers. They include romfs, spiffs, littlefs. +3. They require neither block nor MTD drivers. They include nxffs, tmpfs, nfs + binfs, procfs, userfs, hostfs, cromfs, unionfs, rpmsgfs, and zipfs. + +The requirements are specified by declaring the filesystem in the proper +array in ``fs/mount/fs_mount.c``. \ No newline at end of file diff --git a/Documentation/components/filesystem/rpmsgfs.rst b/Documentation/components/filesystem/rpmsgfs.rst index 3d4b5ac58ff1f..6571bbe7bf121 100644 --- a/Documentation/components/filesystem/rpmsgfs.rst +++ b/Documentation/components/filesystem/rpmsgfs.rst @@ -2,4 +2,31 @@ RPMSG File System ================= -Use rpmsg file system to mount remote directories to local. +Once RPMsg link is available, we can use rpmsg file system to mount remote directories with the help of RPMsg file system drivers. + +Here we show an example of mounting and using a master file system path from remote side, it is as easy as using a local file system. + +Building +======== + +At file system server side (the master), we need enable the ``CONFIG_FS_RPMSGFS_SERVER`` configuration. + +At file system client side (the remote), we need enable the ``CONFIG_FS_RPMSGFS`` configuration. + +Then we build the two sides accordingly. + +Running +======= + +Using the following command to mount the master's ``/proc`` file system to ``/proc.master`` from the ``nsh`` sessino of the remote node. + +.. code:: console + + remote> mount -t rpmsgfs -o cpu=master,fs=/proc /proc.master + remote> cat /proc/uptime /proc.master/uptime + 39.06 + 39.06 + remote> + +Note the ``-o cpu=master,fs=/proc`` specifies the ``master`` node's ``/proc`` path as the source, the ``/proc.master`` is the mount point at remote side. All files under that mount point is actually hosted at the master side. The ``-t rpmsgfs`` selects the RPMsg file system driver to serve the operation. + diff --git a/Documentation/components/filesystem/shmfs.rst b/Documentation/components/filesystem/shmfs.rst index f5ed0b8315812..f23d79c7e1de4 100644 --- a/Documentation/components/filesystem/shmfs.rst +++ b/Documentation/components/filesystem/shmfs.rst @@ -2,4 +2,16 @@ Shared Memory File System ========================= -Include support for shm_open() and shm_close. +This supports the POSIX shm_open() APIs for shared memory among unrelated +apps. + +It can be enabled with ``CONFIG_FS_SHMFS=y``. To check how it works, please +also enable the example app via ``CONFIG_EXMAPLE_SHM=y`` and run ``shm_test`` +from NSH command line. + +This file system doesn't support mount operations though. + +If comment the line using ``shm_unlink()`` in the example app, we can see +a file under ``/var/shm/`` from NSH command line after running the example. +We can also remove that file from command line. + diff --git a/Documentation/components/filesystem/tmpfs.rst b/Documentation/components/filesystem/tmpfs.rst index 97a88bf3c583d..95fda02cfcb63 100644 --- a/Documentation/components/filesystem/tmpfs.rst +++ b/Documentation/components/filesystem/tmpfs.rst @@ -2,4 +2,12 @@ TMPFS ===== -TMPFS filesystem. +NuttX TMPFS file system is a tiny dyamic RAM based file system. + +It can be enabled by adding ``CONFIG_FS_TMPFS=y`` to the configuration at build time. + +At runtime, simply use ``mount -t tmpfs /tmp`` to have a ``/tmp`` folder backed by TMPFS, then files and folders can be created under that folder. + +Be aware that TMPFS is backed by kernel memory thus don't expect to store big files on it and its size is limited by free kernel memory. + +We can watch the size of TMPFS with ``df -h`` command, especially you can see the ``Size`` column of TMPFS changes when files are added or removed in the TMPFS folder. Changes in TMPFS size is always reflected by reverse changes of free kernel memory size. diff --git a/Documentation/components/libs/libc/index.rst b/Documentation/components/libs/libc/index.rst index 8307dc19e6096..0d8966e5be994 100644 --- a/Documentation/components/libs/libc/index.rst +++ b/Documentation/components/libs/libc/index.rst @@ -7,16 +7,16 @@ what you would expect to find in a standard C library. The sub-directories in this directory contain standard interface that can be executed by user- mode programs. -Normally, NuttX is built with no protection and all threads running in kerne- -mode. In that model, there is no real architectural distinction between +Normally, NuttX is built with no protection and all threads running in kernel- +mode. In that mode, there is no real architectural distinction between what is a kernel-mode program and what is a user-mode program; the system is -more like on multi-threaded program that all runs in kernel-mode. +more like an multi-threaded program that all runs in kernel-mode. But if the ``CONFIG_BUILD_PROTECTED`` option is selected, NuttX will be built into distinct user-mode and kernel-mode sections. In that case, most of the code in the ``nuttx/`` directory will run in kernel-mode with exceptions of (1) the user-mode "proxies" found in syscall/proxies, and (2) the -standard C library functions found in this directory. In this build model, +standard C library functions found in this directory. In this build mode, it is critical to separate the user-mode OS interfaces in this way. If ``CONFIG_BUILD_KERNEL`` is selected, then only a NuttX kernel will be built @@ -25,9 +25,9 @@ with no applications. Sub-Directories =============== -The files in the ``libs/libc/`` directory are organized (mostly) according which file -in the include/ directory provides the prototype for library functions. So -we have:: +The files in the ``libs/libc/`` directory are organized (mostly) according +which file in the ``include/`` directory provides the prototype for library +functions. So we have:: audio - This part of the audio system: nuttx/audio/audio.h builtin - Support for builtin applications. Used by nuttx/binfmt and NSH. @@ -128,7 +128,8 @@ Symbol tables have differing usefulness in different NuttX build modes: interact with the OS). #. But in the kernel build mode (``CONFIG_BUILD_LOADABLE``), only fully linked - executables loadable via ``execl()``, ``execv()``, or ``posix_spawan()`` can used. + executables loadable via ``execl()``, ``execv()``, or ``posix_spawan()`` + can be used. There is no use for a symbol table with the kernel build since all memory resources are separate; nothing is share-able with the newly started process. diff --git a/Documentation/components/net/index.rst b/Documentation/components/net/index.rst index 7573e02b09946..24218071dfc08 100644 --- a/Documentation/components/net/index.rst +++ b/Documentation/components/net/index.rst @@ -7,7 +7,12 @@ Network Support sixlowpan.rst socketcan.rst + pkt.rst + nat.rst + netdev.rst + netdriver.rst netguardsize.rst + netlink.rst slip.rst wqueuedeadlocks.rst @@ -33,7 +38,7 @@ Network Support +- nat - Network Address Translation (NAT) +- neighbor - Neighbor Discovery Protocol (IPv6) +- netdev - Socket network device interface - +- netfiletr - Iptables Interface + +- netfilter - Iptables Interface +- netlink - Netlink IPC socket interface +- pkt - "Raw" packet socket support +- procfs - net devices PROCFS support diff --git a/Documentation/components/net/nat.rst b/Documentation/components/net/nat.rst new file mode 100644 index 0000000000000..abd1b380f1cdc --- /dev/null +++ b/Documentation/components/net/nat.rst @@ -0,0 +1,228 @@ +================================= +Network Address Translation (NAT) +================================= + +NuttX supports full cone or symmetric NAT logic, which currently supports + +- TCP + +- UDP + +- ICMP + + - ECHO (REQUEST & REPLY) + + - Error Messages (DEST_UNREACHABLE & TIME_EXCEEDED & PARAMETER_PROBLEM) + +Workflow +======== + +:: + + Local Network (LAN) External Network (WAN) + |----------------| + | | external port> peer port> + |----------------| + +- Outbound + + - **LAN** -> **Forward** -> **NAT** (only if targeting at WAN) -> **WAN** + + - All packets from **LAN** and targeting at **WAN** will be masqueraded + with ``local ip:port`` changed to ``external ip:port``. + +- Inbound + + - **WAN** -> **NAT** (only from WAN, change destination) -> **Forward** -> **LAN** + + - Packets from **WAN** will try to be changed back from + ``external ip:port`` to ``local ip:port`` and send to **LAN**. + +Configuration Options +===================== + +``CONFIG_NET_NAT`` + Enable or disable Network Address Translation (NAT) function. + Depends on ``CONFIG_NET_IPFORWARD``. +``CONFIG_NET_NAT44`` & ``CONFIG_NET_NAT66`` + Enable or disable NAT on IPv4 / IPv6. + Depends on ``CONFIG_NET_NAT``. +``CONFIG_NET_NAT44_FULL_CONE`` & ``CONFIG_NET_NAT66_FULL_CONE`` + Enable Full Cone NAT logic. Full Cone NAT is easier to traverse than + Symmetric NAT, and uses less resources than Symmetric NAT. +``CONFIG_NET_NAT44_SYMMETRIC`` & ``CONFIG_NET_NAT66_SYMMETRIC`` + Enable Symmetric NAT logic. Symmetric NAT will be safer than Full Cone NAT, + be more difficult to traverse, and has more entries which may lead to heavier load. +``CONFIG_NET_NAT_HASH_BITS`` + The bits of the hashtable of NAT entries, hashtable has (1 << bits) buckets. +``CONFIG_NET_NAT_TCP_EXPIRE_SEC`` + The expiration time for idle TCP entry in NAT. + The default value 86400 is suggested by RFC2663, Section 2.6, + Page 5. But we may set it to shorter time like 240s for better + performance. +``CONFIG_NET_NAT_UDP_EXPIRE_SEC`` + The expiration time for idle UDP entry in NAT. +``CONFIG_NET_NAT_ICMP_EXPIRE_SEC`` + The expiration time for idle ICMP entry in NAT. +``CONFIG_NET_NAT_ICMPv6_EXPIRE_SEC`` + The expiration time for idle ICMPv6 entry in NAT. +``CONFIG_NET_NAT_ENTRY_RECLAIM_SEC`` + The time to auto reclaim all expired NAT entries. A value of zero will + disable auto reclaiming. + Expired entries will be automatically reclaimed when matching + inbound/outbound entries, so this config does not have significant + impact when NAT is normally used, but very useful when the hashtable + is big and there are only a few connections using NAT (which will + only trigger reclaiming on a few chains in hashtable). + +Usage +===== + + - :c:func:`nat_enable()` + - :c:func:`nat_disable()` + +.. c:function:: int nat_enable(FAR struct net_driver_s *dev); + + Enable NAT function on a network device, on which the outbound packets + will be masqueraded. + + :return: Zero is returned if NAT function is successfully enabled on + the device; A negated errno value is returned if failed. + +.. c:function:: int nat_disable(FAR struct net_driver_s *dev); + + Disable NAT function on a network device. + + :return: Zero is returned if NAT function is successfully disabled on + the device; A negated errno value is returned if failed. + +Validation +========== + +Validated on Ubuntu 22.04 x86_64 with NuttX SIM by following steps: + +1. Configure NuttX with >=2 TAP devices (host route mode) and NAT enabled: + + .. code-block:: Kconfig + + CONFIG_NET_IPFORWARD=y + CONFIG_NET_NAT=y + # CONFIG_SIM_NET_BRIDGE is not set + CONFIG_SIM_NETDEV_NUMBER=2 + +2. Call ``nat_enable`` on one dev on startup, or manually enable NAT + with ``iptables`` command (either may work). + + .. code-block:: c + + /* arch/sim/src/sim/up_netdriver.c */ + int netdriver_init(void) + { + ... + nat_enable(&g_sim_dev[0]); + ... + } + + .. code-block:: shell + + iptables -t nat -A POSTROUTING -o eth0 -j MASQUERADE + +3. Set IP Address for NuttX on startup + + .. code-block:: shell + + ifconfig eth0 10.0.1.2 + ifup eth0 + ifconfig eth1 10.0.10.2 + ifup eth1 + + # IPv6 if you need + ifconfig eth0 inet6 add fc00:1::2/64 gw fc00:1::1 + ifconfig eth1 inet6 add fc00:10::2/64 + +4. Configure IP & namespace & route on host side (maybe need to be root, then try ``sudo -i``) + + .. code-block:: bash + + IF_HOST="enp1s0" + IF_0="tap0" + IP_HOST_0="10.0.1.1" + IF_1="tap1" + IP_HOST_1="10.0.10.1" + IP_NUTTX_1="10.0.10.2" + + # add net namespace LAN for $IF_1 + ip netns add LAN + ip netns exec LAN sysctl -w net.ipv4.ip_forward=1 + ip link set $IF_1 netns LAN + ip netns exec LAN ip link set $IF_1 up + ip netns exec LAN ip link set lo up + + # add address and set default route + ip addr add $IP_HOST_0/24 dev $IF_0 + ip netns exec LAN ip addr add $IP_HOST_1/24 dev $IF_1 + ip netns exec LAN ip route add default dev $IF_1 via $IP_NUTTX_1 + + # nat to allow NuttX to access the internet + iptables -t nat -A POSTROUTING -o $IF_HOST -j MASQUERADE + iptables -A FORWARD -i $IF_HOST -o $IF_0 -j ACCEPT + iptables -A FORWARD -i $IF_0 -o $IF_HOST -j ACCEPT + sysctl -w net.ipv4.ip_forward=1 + + # IPv6 if you need + IP6_HOST_0="fc00:1::1" + IP6_HOST_1="fc00:10::1" + IP6_NUTTX_1="fc00:10::2" + + # add address and set default route + ip -6 addr add $IP6_HOST_0/64 dev $IF_0 + ip netns exec LAN ip -6 addr add $IP6_HOST_1/64 dev $IF_1 + ip netns exec LAN ip -6 route add default dev $IF_1 via $IP6_NUTTX_1 + + # nat to allow NuttX to access the internet + ip6tables -t nat -A POSTROUTING -o $IF_HOST -j MASQUERADE + ip6tables -A FORWARD -i $IF_HOST -o $IF_0 -j ACCEPT + ip6tables -A FORWARD -i $IF_0 -o $IF_HOST -j ACCEPT + sysctl -w net.ipv6.conf.all.forwarding=1 + +5. Do anything in the LAN namespace will go through NAT + + .. code-block:: shell + + # Host side + iperf -B 10.0.1.1 -s -i 1 + # LAN side + sudo ip netns exec LAN iperf -B 10.0.10.1 -c 10.0.1.1 -i 1 + + .. code-block:: shell + + # Host side + python3 -m http.server -b :: + # LAN side + for i in {1..20000}; do sudo ip netns exec LAN curl 'http://10.0.1.1:8000/' > /dev/null 2>1; done + for i in {1..20000}; do sudo ip netns exec LAN curl 'http://[fc00:1::1]:8000/' > /dev/null 2>1; done + + .. code-block:: shell + + # LAN side + sudo ip netns exec LAN ping 8.8.8.8 + sudo ip netns exec LAN ping 2001:4860:4860::8888 + + .. code-block:: shell + + # LAN side + sudo ip netns exec LAN traceroute -n 8.8.8.8 # ICMP error msg of UDP + sudo ip netns exec LAN traceroute -n -T 8.8.8.8 # ICMP error msg of TCP + sudo ip netns exec LAN traceroute -n -I 8.8.8.8 # ICMP error msg of ICMP + sudo ip netns exec LAN traceroute -n 2001:4860:4860::8888 + sudo ip netns exec LAN traceroute -n -T 2001:4860:4860::8888 + sudo ip netns exec LAN traceroute -n -I 2001:4860:4860::8888 + + .. code-block:: shell + + # Host side + tcpdump -nn -i tap0 + # LAN side + sudo ip netns exec LAN tcpdump -nn -i tap1 diff --git a/Documentation/reference/os/netdev.rst b/Documentation/components/net/netdev.rst similarity index 95% rename from Documentation/reference/os/netdev.rst rename to Documentation/components/net/netdev.rst index 2bc0fe73912d6..1075ff9b30e3c 100644 --- a/Documentation/reference/os/netdev.rst +++ b/Documentation/components/net/netdev.rst @@ -8,6 +8,13 @@ Network Devices interface and is passed to the network via ``netdev_register()``. +- ``include/nuttx/net/netdev_lowerhalf.h``. (Recommended for new + drivers, see :ref:`Network Drivers `) + This header file defines the interface between the network device + and the network stack. The network device is a lower-half driver + that provides the network stack with the ability to send and receive + packets. + IP Addresses ============ diff --git a/Documentation/components/net/netdriver.rst b/Documentation/components/net/netdriver.rst new file mode 100644 index 0000000000000..763e15b824690 --- /dev/null +++ b/Documentation/components/net/netdriver.rst @@ -0,0 +1,237 @@ +.. _netdriver: + +=============== +Network Drivers +=============== + +The NuttX network driver is split into two parts: + +#. An "upper half", generic driver that provides the common network + interface to application level code, and +#. A "lower half", platform-specific driver that implements the + low-level timer controls to implement the network functionality. + +Files supporting network driver can be found in the following locations: + +- **Interface Definition**. The header file for the NuttX network + driver resides at ``include/nuttx/net/netdev_lowerhalf.h``. This + header file includes the interface between the "upper half" and + "lower half" drivers. +- **"Upper Half" Driver**. The generic, "upper half" network driver + resides at ``drivers/net/netdev_upperhalf.c``. +- **"Lower Half" Drivers**. Platform-specific network drivers reside + in ``arch//src/`` or ``drivers/net`` + directory for the specific processor ```` and for + the specific ```` network peripheral devices. + +**Special Note**: Not all network drivers are implemented with this +architecture. Known lower-half drivers: +``arch/sim/src/sim/sim_netdriver.c``, ``drivers/virtio/virtio-net.c`` + +How to change full network driver into lower-half one +===================================================== + +We have many network drivers that are implemented as full network drivers +with ``include/nuttx/net/netdev.h``, we can change them into lower-half +drivers to remove the common code (which is already in upper-half driver). +Here is a guide to do so: + +1. Change ``struct net_driver_s`` to ``struct netdev_lowerhalf_s`` in + the network driver structure. If you really need to touch some fields + inside ``struct net_driver_s`` like MAC address, you can access them + through ``struct netdev_lowerhalf_s::netdev``. +2. Change the function names called in the network driver file to the names + with prefix ``netdev_lower_``, e.g. ``netdev_lower_register`` and + ``netdev_lower_carrier_on``. +3. Change the core functions called by work queue like ``txpoll`` as + ``transmit`` and ``receive`` in the ``netdev_ops_s`` structure. You may + need to change ``memcpy`` for ``d_buf`` into ``netpkt_copyin`` and + ``netpkt_copyout``. + + - Note that the ``receive`` function just need to return the received + packet instead of calling functions like ``ipv4_input`` or doing reply. + The upper-half will call ``receive`` to get all packets until it + returns ``NULL`` and send these packets into the network stack. + - Also remember to call ``netpkt_free`` for the transmitted packets. + +4. Remove work queues related to send and receive, and replace them + with calling ``netdev_lower_txdone`` and ``netdev_lower_rxready``. + Then the upper-half driver will call ``transmit`` and ``receive`` to + send/get packets. +5. Remove any buffer related to ``d_buf``, and make sure ``d_buf`` is not + used in the lower-half driver. +6. Remove ``txavail`` function, the upper-half driver will call ``transmit`` + when it has packets to send. +7. Remove the statistics macros like ``NETDEV_TXPACKETS``, ``NETDEV_TXDONE``, + ``NETDEV_RXPACKETS`` or ``NETDEV_RXDROPPED``, these macros are well + handled in upper-half. But you may still keep macros like + ``NETDEV_TXTIMEOUTS`` and ``NETDEV_RXERRORS`` because the upper-half + cannot know whether these error happens. +8. Find a suitable ``quota`` for the driver, and set it in the driver + initialization function. The quota is the maximum number of buffers + that the driver can hold at the same time. For example, if the TX quota + is set to 5, it means that if the driver has 5 unreleased packets + (``netpkt_free``), the upper-half will not call ``transmit`` until they + are released. + + - Note: An exception is that if the net stack is replying for RX packet, + this replied packet will always be put into ``transmit``, which may + exceed the TX quota temporarily. + +"Lower Half" Example +==================== + +.. code-block:: c + + struct _priv_s + { + /* This holds the information visible to the NuttX network */ + + struct netdev_lowerhalf_s dev; + + ... + }; + + static const struct netdev_ops_s g_ops = + { + .ifup = _ifup, + .ifdown = _ifdown, + .transmit = _transmit, + .receive = _receive, + .addmac = _addmac, + .rmmac = _rmmac, + .ioctl = _ioctl + }; + + /* The Wi-Fi driver registration function can be implemented as follows, + * where refers to the chip name. netdev_lower_register() is the + * network device interface provided by upper-half drivers to register + * network device drivers. + */ + + int _netdev_init(FAR struct _priv_s *priv) + { + FAR struct netdev_lowerhalf_s *dev = &priv->dev; + + dev->ops = &g_ops; + + /* The maximum number of buffers that the driver can hold + * at the same time. For example, if the TX quota is set to 5, it + * means that if the driver has 5 unreleased packets (netpkt_free), + * the upper layer will not call transmit until they are released. + * After the rx quota is used up and no new buffer can be allocated + * (netpkt_alloc), it needs to notify the upper layer + * (netdev_lower_rxready) and restore the quota by submitting buffer + * back through receive function. + * If the driver processes each packet individually (without + * accumulating multiple packets before sending/receiving), it can be + * set to 1. + */ + + dev->quota[NETPKT_TX] = 1; + dev->quota[NETPKT_RX] = 1; + + return netdev_lower_register(dev, NET_LL_ETHERNET); + } + + /* The transmit function can be implemented as follows, where + * refers to the chip name. + */ + + static int _transmit(FAR struct netdev_lowerhalf_s *dev, + FAR netpkt_t *pkt) + { + FAR struct _priv_s *priv = (FAR struct _priv_s *)dev; + unsigned int len = netpkt_getdatalen(dev, pkt); + + #if you want to do offloading + if (!netpkt_is_fragmented(pkt)) + { + /* Contiguous memory, just use data pointer */ + + FAR uint8_t *databuf = netpkt_getdata(dev, pkt); + FAR uint8_t *devbuf = databuf - sizeof(struct _txhead_s); + + /* Do Transmit. Note: `databuf` points to the L2 data, and there is + * a reserved memory with size of `CONFIG_NET_LL_GUARDSIZE` before + * databuf to be used for driver header, drivers can just fill data + * there (`devbuf`) and start the transmission. + */ + + ... + } + else + #endif + { + /* Copyout the L2 data and transmit. */ + + uint8_t devbuf[1600]; + netpkt_copyout(dev, devbuf, pkt, len, 0); + + /* Do Transmit */ + + ... + } + + return OK; + } + + static void _txdone_interrupt(FAR struct _priv_s *priv) + { + FAR struct netdev_lowerhalf_s *dev = &priv->dev; + + /* Perform some processing in the driver (if necessary) */ + + ... + + /* Free the buffer and notify the upper layer */ + + netpkt_free(dev, pkt, NETPKT_TX); + netdev_lower_txdone(dev); + } + + /* The receive function can be implemented as follows, where + * refers to the chip name. + */ + + static void _rxready_interrupt(FAR struct _priv_s *priv) + { + FAR struct netdev_lowerhalf_s *dev = &priv->dev; + netdev_lower_rxready(dev); + } + + static FAR netpkt_t *_receive(FAR struct netdev_lowerhalf_s *dev) + { + /* It is also possible to allocate the pkt and receive the data in + * advance, and then call rxready and return pkt through receive + */ + + FAR netpkt_t *pkt = netpkt_alloc(dev, NETPKT_RX); + + if (pkt) + { + #if NETPKT_BUFLEN > 15xx && you want to do offloading + /* Write directly to the buffer inside pkt, len corresponds to the + * length of L2 data (need the NETPKT_BUFLEN to be large enough to + * hold the data). The `_rxhead_s` is the driver header before + * the actual data (maybe you don't have). + */ + + len = receive_data_into(netpkt_getbase(pkt)); + netpkt_resetreserved(&priv->dev, pkt, sizeof(struct _rxhead_s)); + netpkt_setdatalen(&priv->dev, pkt, len); + #else + uint8_t devbuf[1600]; + + /* Copy from src, len corresponds to the length of L2 data, you can + * always use this method to receive data. The `_rxhead_s` is + * the driver header before the actual data (maybe you don't have). + */ + + len = receive_data_into(devbuf); + netpkt_copyin(dev, pkt, devbuf + sizeof(struct _rxhead_s), len, 0); + #endif + } + + return pkt; + } diff --git a/Documentation/components/net/netlink.rst b/Documentation/components/net/netlink.rst new file mode 100644 index 0000000000000..cb19c1b61e510 --- /dev/null +++ b/Documentation/components/net/netlink.rst @@ -0,0 +1,137 @@ +===================== +Netlink Route support +===================== + +Netlink Route (:c:macro:`NETLINK_ROUTE`) allow notifying msg when the network +changes. And then apps can obtain these changes by monitoring to netlink socket +messages. + +NuttX supports Netlink Route groups + +- RTMGRP_IPV4_ROUTE | RTMGRP_IPV6_ROUTE + - Notify when IPV4|IPV6 routing table changes. + +- RTMGRP_NEIGH + - Notify when ARP (IPV4) or neighbors (IPV6) table changes. + +- RTNLGRP_IPV6_PREFIX + - Notify when IPV6 prefix changes. + +Messages content +================ + +1. RTMGRP_IPV4_ROUTE | RTMGRP_IPV6_ROUTE + + ``RTM_NEWROUTE``, ``RTM_DELROUTE``, ``RTM_GETROUTE``: + Create, remove or receive information about a network route. These + messages contain an rtmsg structure with 3 optional sequence of + rtattr structures following. + + .. code-block:: c + + struct getroute_recvfrom_ipv4addr_s + { + struct rtattr attr; + in_addr_t addr; + }; + + struct getroute_recvfrom_ipv4response_s + { + struct nlmsghdr hdr; + struct rtmsg rte; + struct getroute_recvfrom_ipv4addr_s dst; + struct getroute_recvfrom_ipv4addr_s genmask; + struct getroute_recvfrom_ipv4addr_s gateway; + }; + + struct getroute_recvfrom_ipv6addr_s + { + struct rtattr attr; + net_ipv6addr_t addr; + }; + + struct getroute_recvfrom_ipv6response_s + { + struct nlmsghdr hdr; + struct rtmsg rte; + struct getroute_recvfrom_ipv6addr_s dst; + struct getroute_recvfrom_ipv6addr_s genmask; + struct getroute_recvfrom_ipv6addr_s gateway; + }; + +2. RTMGRP_NEIGH + + ``RTM_NEWNEIGH``, ``RTM_DELNEIGH``, ``RTM_GETNEIGH``: + Add, remove or receive information about a neighbor table entry (e.g., + an ARP entry). The message contains an ndmsg structure and optional + sequence of rtattr structures following. And the date will be ``struct arpreq`` + in ``include/netinet/arp.h``or ``struct neighbor_entry_s`` in ``include/net/neighbor.h`` + + .. code-block:: c + + struct getneigh_recvfrom_response_s + { + struct nlmsghdr hdr; + struct ndmsg msg; + struct rtattr attr; + uint8_t data[1]; + }; + +3. RTNLGRP_IPV6_PREFIX + + ``RTM_NEWPREFIX``: + Receive information about IPV6 prefix. The message contains an prefixmsg structure + and two optional sequence of rtattr structures following. And the ``addr`` and + ``prefix_cacheinfo`` are parsed from the RA message. + + .. code-block:: c + + struct getprefix_recvfrom_addr_s + { + struct rtattr attr; + net_ipv6addr_t addr; + }; + + struct getprefix_recvfrom_cache_s + { + struct rtattr attr; + struct prefix_cacheinfo pci; + }; + + struct getprefix_recvfrom_response_s + { + struct nlmsghdr hdr; + struct prefixmsg pmsg; + struct getprefix_recvfrom_addr_s prefix; + struct getprefix_recvfrom_cache_s pci; + }; + +Usage +===== + +.. code-block:: c + + struct sockaddr_nl addr; + struct nlmsghdr *hdr; + uint8_t buffer[BUFSIZE]; + int sd = socket(AF_NETLINK, SOCK_RAW, NETLINK_ROUTE); + + addr.nl_family = AF_NETLINK; + addr.nl_groups = RTMGRP_IPV4_ROUTE | RTMGRP_IPV6_ROUTE | + RTMGRP_NEIGH | RTMGRP_IPV6_PREFIX; + + bind(sd, (FAR struct sockaddr *)&addr, sizeof(addr)); /* Bind to device */ + while (1) + { + recv(sd, buf, BUFSIZE, 0); + for (hdr = buf; NLMSG_OK(hdr, ret); hdr = NLMSG_NEXT(hdr, ret)) + { + if (hdr->nlmsg_type == RTM_...) + { + /* Func parsed netlink msg*/ + ... + } + } + } + + close(sd); /* Close the socket */ \ No newline at end of file diff --git a/Documentation/components/net/pkt.rst b/Documentation/components/net/pkt.rst new file mode 100644 index 0000000000000..28eb044293fcb --- /dev/null +++ b/Documentation/components/net/pkt.rst @@ -0,0 +1,37 @@ +=========================== +"Raw" packet socket support +=========================== + +Packet sockets (:c:macro:`AF_PACKET`) allow receiving and transmitting frames +without a transport protocol in between. Frames received are copied into a +packet socket tap before they enter the network. Data written into a packet +socket will bypass the network altogether and be placed in the transmission +buffer of the network interface driver. + +Configuration Options +===================== + +``CONFIG_NET_PKT_PREALLOC_CONNS`` + Number of preallocated packet connections (all tasks). +``CONFIG_NET_PKT_ALLOC_CONNS`` + Dynamic memory allocations for packet connections. +``CONFIG_NET_PKT_MAX_CONNS`` + Maximum number of packet connections. + +Usage +===== + +.. code-block:: c + + struct sockaddr_ll addr; + uint8_t buffer[BUFSIZE]; + int sd = socket(AF_PACKET, SOCK_RAW, 0); /* Create a packet socket */ + + addr.sll_family = AF_PACKET; + addr.sll_ifindex = if_nametoindex("eth0"); + bind(sd, (FAR struct sockaddr *)&addr, sizeof(addr)); /* Bind to device */ + + recv(sd, buffer, sizeof(buffer), 0); /* read(sd, buffer, sizeof(buffer)); */ + send(sd, buffer, sizeof(buffer), 0); /* write(sd, buffer, sizeof(buffer)); */ + + close(sd); /* Close the socket */ diff --git a/Documentation/components/paging.rst b/Documentation/components/paging.rst index 455ac76da7fc5..7adf8b2235cad 100644 --- a/Documentation/components/paging.rst +++ b/Documentation/components/paging.rst @@ -4,17 +4,78 @@ On-Demand Paging ================ -Introduction -============ - -Overview --------- - -This document summarizes the design of NuttX on-demand paging. This -feature permits embedded MCUs with some limited RAM space to execute -large programs from some non-random access media. - -What kind of platforms can support NuttX on-demang paging? +Kernel Build Implementation +=========================== + +On-demand paging and lazy loading are techniques used to manage physical +memory. The basic idea is to allow a program to execute even though the +entire program is not resident in memory. The program is loaded into +memory on demand. This is a technique that is used in many operating +systems to allow large programs to execute on small memory systems. +Commonly, a Memory Management Unit (MMU) is used to map virtual memory +into physical memory. Applications are then loaded into virtual memory +address spaces and access to physical memory is managed by the MMU. If +the virtual memory is not resident in physical memory, then a page fault +occurs. The operating system then loads the missing page into memory and +resumes execution. + +Requirements and Assumptions +---------------------------- + +On-demand paging requires *Kernel Build* (``CONFIG_BUILD_KERNEL=y``) mode. +In this mode, no applications are built within the NuttX kernel. Instead, +the applications are built as separate programs that are loaded into memory +(``CONFIG_ELF=y`` and ``CONFIG_BINFMT_LOADABLE=y``). In this mode, each +process has its own address environment (``CONFIG_ARCH_ADDRENV=y``). + +Logic Design Description +------------------------ + +When an application is being loaded ``up_addrenv_create`` is called to create +the process's address environment. This includes mapping the commonly used +``text``, ``data`` and ``heap`` sections withing the virtual memory space. +Without on-demand paging, the physical memory is then allocated and mapped +accordingly, before the process is started. When on-demand paging is enabled, +usually only one single page for each section is allocated and mapped. + +The process starts executing within its address environment, accessing the +virtual memory. Whenever it tries to access a virtual memory address that is +not mapped in the MMU, a page fault occurs. The MMU then triggers an +exception that is handled by the kernel. The kernel then checks if there are +enough free physical pages available and maps the virtual memory address to +it. Finally, execution is resumed from the same point where the page fault +first occurred. + +Example: RISC-V +^^^^^^^^^^^^^^^ + +RISC-V's ``up_addrenv_create`` calls ``create_region`` (both defined in +``arch/risc-v/src/common/riscv_addrenv.c``). ``create_region`` maps a single +region to MMU by allocating physical memory for the page tables. When +``CONFIG_PAGING=y`` is not selected, all the physical page tables are +allocated from the physical memory space and then mapped to the virtual +memory space. When ``CONFIG_PAGING=y`` is selected, only the first page of +each section is mapped to the virtual memory space. The rest of the pages are +mapped to the virtual memory space only when a page fault occurs. + +The page fault is handled by the ``riscv_fillpage`` function in the exception +handler (defined in ``arch/risc-v/src/common/riscv_exception.c``). Whenever +a page fault occurs, the ``riscv_fillpage`` function is called. This function +allocates a physical page and maps it to the virtual memory space that +triggered the page fault exception and then resumes execution from the same +point where the page fault first occurred. + +:ref:`knsh32_paging` simulates a device with 4MiB physical memory with 8MiB +of virtual heap memory allocated for each process. This is possible by +enabling on-demand paging. + +Legacy Implementation +===================== + +This legacy implementation runs on *Flat Build* (*Kernel Build* did not +even exist at that time). + +What kind of platforms can support NuttX legacy on-demand paging? #. The MCU should have some large, probably low-cost non-volatile storage such as serial FLASH or an SD card. This storage probably @@ -29,7 +90,7 @@ What kind of platforms can support NuttX on-demang paging? LPC3131) would be sufficient for many applications. #. The MCU has an MMU (again like the NXP LPC3131). -If the platform meets these requirement, then NuttX can provide +If the platform meets these requirements, then NuttX can provide on-demand paging: It can copy .text from the large program in non-volatile media into RAM as needed to execute a huge program from the small RAM. @@ -55,10 +116,10 @@ Terminology Task Control Block NuttX Common Logic Design Description -===================================== +------------------------------------- Initialization --------------- +^^^^^^^^^^^^^^ The following declarations will be added. @@ -89,7 +150,7 @@ logic, those architecture specific functions are instead declared in ``include/nuttx/page.h``. Page Faults ------------ +^^^^^^^^^^^ **Page fault exception handling**. Page fault handling is performed by the function ``pg_miss()``. This function is called from @@ -146,7 +207,7 @@ inputs are required. page fill. Fill Initiation ---------------- +^^^^^^^^^^^^^^^ The page fill worker thread will be awakened on one of three conditions: @@ -217,7 +278,7 @@ The architecture-specific functions, ``up_checkmapping()``, will be prototyped in ``include/nuttx/arch.h`` Fill Complete -------------- +^^^^^^^^^^^^^ For the blocking ``up_fillpage()``, the result of the fill will be returned directly from the call to ``up_fillpage``. @@ -246,7 +307,7 @@ completed: - Signal the page fill worker thread. Task Resumption ---------------- +^^^^^^^^^^^^^^^ For the non-blocking ``up_fillpage()``, the page fill worker thread will detect that the page fill is complete when it is awakened with @@ -279,10 +340,10 @@ In this either, the page fill worker thread will: - Wait for the next fill related event (a new page fault). Architecture-Specific Support Requirements -========================================== +------------------------------------------ Memory Organization -------------------- +^^^^^^^^^^^^^^^^^^^ **Memory Regions**. Chip specific logic will map the virtual and physical address spaces into three general regions: @@ -367,7 +428,7 @@ would be a two phase link: "non-swappable" region. Architecture-Specific Functions -------------------------------- +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Most standard, architecture-specific functions are declared in ``include/nuttx/arch.h``. However, for the case of this paging logic, @@ -406,4 +467,3 @@ implemented just for on-demand paging support are: will be called when the page fill is finished (or an error occurs). This callback is assumed to occur from an interrupt level when the device driver completes the fill operation. - diff --git a/Documentation/components/syscall.rst b/Documentation/components/syscall.rst index 07a1310afa56e..9a175f1c78de2 100644 --- a/Documentation/components/syscall.rst +++ b/Documentation/components/syscall.rst @@ -202,8 +202,8 @@ mksyscall --------- mksyscall is C program that is used used during the initial NuttX build -by the logic in the top-level ``syscall/``! directory. Information about the +by the logic in the top-level ``syscall/`` directory. Information about the stubs and proxies is maintained in a comma separated value (CSV) file -in the ``syscall/`` directory. The mksyscall program will accept this CVS +in the ``syscall/`` directory. The mksyscall program will accept this CSV file as input and generate all of the required proxy or stub files as output. See ``Documentation/components/tools/`` for additional information. diff --git a/Documentation/guides/customapps.rst b/Documentation/guides/customapps.rst index 44eeb6e953bcb..dd839fe89dc55 100644 --- a/Documentation/guides/customapps.rst +++ b/Documentation/guides/customapps.rst @@ -31,9 +31,9 @@ The CustomApps directory need only to contain the minimum three files: 1.1 Makefile ------------ -The custom application directory must include a Makefile to make all of the targets -expected by the NuttX build and must generate an archive called libapps.a in the -top-level of the custom directory structure. +The custom application directory must include a Makefile to make all of the +targets expected by the NuttX build and must generate an archive called +libapps.a in the top-level of the custom directory structure. The Makefile has just those minimum required targets: @@ -104,9 +104,10 @@ The Makefile has just those minimum required targets: 1.2 Kconfig ----------- -A Kconfig file must be included but need not be populated with any meaningful options. -This is a place where you can add settings to generate customized builds of your custom -application and/or choose which of your apps to include. +A Kconfig file must be included but need not be populated with any meaningful +options. +This is a place where you can add settings to generate customized builds of +your custom application and/or choose which of your apps to include. In the minimum case, Kconfig is only: @@ -116,7 +117,8 @@ In the minimum case, Kconfig is only: # see the file kconfig-language.txt in the NuttX tools repository. # -or +but it is more usual to include at least the basic information any NuttX app +requires, as well as anything else your app may need: .. code-block:: console @@ -124,7 +126,30 @@ or # see the file kconfig-language.txt in the NuttX tools repository. # - + config CUSTOM_APPS_MY_APP + tristate "My App" + default n + ---help--- + Enable My App + + if CUSTOM_APPS_MY_APP + + config CUSTOM_APPS_MY_APP_PROGNAME + string "Program name" + default "myapp" + ---help--- + This is the name of the program that will be used when the NSH ELF + program is installed. + + config CUSTOM_APPS_MY_APP_PRIORITY + int "My App task priority" + default 100 + + config CUSTOM_APPS_MY_APP_STACKSIZE + int "My App stack size" + default DEFAULT_TASK_STACKSIZE + + endif 1.3 CustomHello.c ----------------- @@ -232,7 +257,19 @@ Create a sub-directory under the ``CustomApps`` directory called ``CustomHello`` The same ``CustomHello.c`` file as described above should be created here. -2.5 CustomHello Makefile +2.5 CustomHello Make.defs +------------------------- + +Create a Make.defs in the ``CustomApps/CustomHello`` directory with the following lines: + + .. code-block:: console + + ifneq ($(CONFIG_CUSTOM_APPS_CUSTOM_HELLO),) + CONFIGURED_APPS += $(APPDIR)/CustomApps/CustomHello + endif + + +2.6 CustomHello Makefile ------------------------ Create a Makefile in the ``CustomApps/CustomHello`` directory with the following lines: @@ -255,7 +292,7 @@ Create a Makefile in the ``CustomApps/CustomHello`` directory with the following include $(APPDIR)/Application.mk -2.6 CustomHello Kconfig +2.7 CustomHello Kconfig ----------------------- Create a Kconfig file in the ``CustomApps/CustomHello`` directory, with the following lines. For @@ -293,7 +330,7 @@ the purposes of this example, the Kconfig will only cover our single application endif -2.7 Build and Run +2.8 Build and Run ----------------- Once these files have been created, run a ``make clean`` (you may need to run ``make distclean`` diff --git a/Documentation/guides/customboards.rst b/Documentation/guides/customboards.rst index 95c21b0d5b868..fea4f6d4785ee 100644 --- a/Documentation/guides/customboards.rst +++ b/Documentation/guides/customboards.rst @@ -46,7 +46,7 @@ To build the custom board, the syntax is slightly different to in-tree boards an .. code-block:: console - $ .tools/configure -l ../CustomBoards/MyCustomBoardName/MyCustomConfig + $ .tools/configure -l ../CustomBoards/MyCustomBoardName/configs/MyCustomConfig Copy files Select CONFIG_HOST_LINUX=y Refreshing... diff --git a/Documentation/guides/etcromfs.rst b/Documentation/guides/etcromfs.rst new file mode 100644 index 0000000000000..aee60257a3928 --- /dev/null +++ b/Documentation/guides/etcromfs.rst @@ -0,0 +1,177 @@ +========================= +etc romfs +========================= +The ROMFS image is the contents of the ``/etc`` directory, including the start-up script +contains any command support by Nuttx, and other customized contents needed. + +Configuration +============= + +.. code-block:: console + + CONFIG_NSH_ROMFS /* Mount a ROMFS file system at "/etc" and provide a system init script at + "/etc/init.d.rc.sysinit" and a startup script at "etc/init.d/rcS". */ + CONFIG_ETC_ROMFSMOUNTPT /* The default mountpoint for the ROMFS volume is "/etc", but that can be + changed with this setting. This must be a absolute path beginning with '/' + and enclosed in quotes. */ + CONFIG_ETC_ROMFSDEVNO /* This is the minor number of the ROMFS block device. The default is '0' + corresponding to "/dev/ram0". */ + CONFIG_ETC_ROMFSSECTSIZE /* This is the sector size to use with the ROMFS volume. Since the default volume + is very small, this defaults to 64 but should be increased if the ROMFS volume + were to be become large. Any value selected must be a power of 2. */ + +This capability also depends on: + +.. code-block:: console + + CONFIG_DISABLE_MOUNTPOINT /* If mount point support is disabled, then you cannot mount any file systems. */ + CONFIG_FS_ROMFS /* This option enables ROMFS file system support. */ + +Start up Scripts +================ + +**Start-Up Script**. The start-up script contains any command support by Nuttx +(i.e., that you see when you enter 'nsh> help'). The implementation that is provided is +intended to provide great flexibility for the use of Start-Up files. +This paragraph will discuss the general behavior when all of the +configuration options are set to the default values. + +In this default case, enabling ``CONFIG_ETC_ROMFS`` will cause Nuttx to +behave as follows at Nuttx start-up time: + + - Nuttx will create a read-only RAM disk (a ROM disk), containing a tiny + ROMFS file system containing the following:: + + `--init.d/ + `-- rcS + `-- rc.sysinit + + Where ``rcS`` is the start-up script. + Where ``rc.sysinit`` is the system-init script. + + - Nuttx will then mount the ROMFS file system at ``/etc``, resulting in:: + + |--dev/ + | `-- ram0 + `--etc/ + `--init.d/ + `-- rcS + `-- rc.sysinit + + - By default, the contents of ``rc.sysinit`` script are:: + + # Create a RAMDISK and mount it at /tmp + + mkrd -m 1 -s 512 1024 + mkfatfs /dev/ram1 + mount -t vfat /dev/ram1 /tmp + + - NSH will execute the script at ``/etc/init.d/rc.sysinit`` at system + init (before the first NSH prompt). After execution of the script, + the root FS will look like:: + + |--dev/ + | |-- ram0 + | `-- ram1 + |--etc/ + | `--init.d/ + | `-- rcS + | `-- rc.sysinit + `--tmp/ + +**Example Configurations**. Here are some configurations that have +``CONFIG_ETC_ROMFS=y`` in the NuttX configuration file. They might +provide useful examples: + + - ``boards/arm/stm32/hymini-stm32v/nsh2`` + - ``boards/arm/dm320/ntosd-dm320/nsh`` + - ``boards/sim/sim/sim/nsh`` + - ``boards/sim/sim/sim/nsh2`` + - ``boards/sim/sim/sim/nx`` + - ``boards/sim/sim/sim/nx11`` + - ``boards/sim/sim/sim/touchscreen`` + +In most of these cases, the configuration sets up the *default* +``/etc/init.d/rc.sysinit`` and ``/etc/init.d/rcS`` script. The default +script is here: ``apps/nshlib/rc.sysinit.template`` and +``apps/nshlib/rcS.template``. (The funny values in the rc.sysinit.template +like ``XXXMKRDMINORXXX`` get replaced via ``sed`` at build time). This +default configuration creates a ramdisk and mounts it at ``/tmp`` as +discussed above. + +Customizing Start up Scripts +============================ + +In order to modify the start-up behavior, there are three things to study: + + #. **Configuration Options.** The additional ``CONFIG_ETC_ROMFS`` + configuration options discussed with `Configuration` + + #. ``tools/mkromfsimg.sh`` **Script**. The script + ``tools/mkromfsimg.sh`` creates ``etc_romfs.c``. It is not + automatically executed. If you want to change the configuration + settings associated with creating and mounting the ``/tmp`` + directory, then it will be necessary to re-generate this header file + using the ``tools/mkromfsimg.sh`` script. + + The behavior of this script depends upon several things: + + #. The configuration settings then installed configuration. + + #. The ``genromfs`` tool(available from + `http://romfs.sourceforge.net `__) + or included within the NuttX buildroot toolchain. There is also a + snapshot available in the NuttX tools repository + `here `__. + + #. The ``xxd`` tool that is used to generate the C header files (xxd + is a normal part of a complete Linux or Cygwin installation, + usually as part of the ``vi`` package). + + #. The file ``include/arch/board/rc.sysinit.template`` and + the file ``include/arch/board/rcs.template`` + + #. ``rc.sysinit.template``. The file ``apps/nshlib/rc.sysinit.template`` + contains the general form of the ``rc.sysinit`` file; configured values + are plugged into this template file to produce the final ``rc.sysinit`` file. + + ``rcS.template``. The file ``apps/nshlib/rcS.template`` contains the + general form of the ``rcS`` file; configured values are plugged into + this template file to produce the final ``rcS`` file. + + To generate a custom ``rc.sysinit`` and ``rcS`` file a copy of + ``rc.sysinit.template`` and ``rcS.template`` needs to + be placed at ``tools/`` and changed according to the desired start-up + behaviour. Running ``tools/mkromfsimg.h`` creates ``etc_romfs.c`` + which needs to be copied to ``arch/board/src`` and compiled in Makefile + +All of the startup-behavior is contained in ``rc.sysinit.template`` and +``rcS.template``. The role of ``mkromfsimg.sh`` script is to (1) apply +the specific configuration settings to ``rc.sysinit.template`` to create +the final ``rc.sysinit``, and ``rcS.template`` to create the final ``rcS``, +and (2) to generate the source file ``etc_romfs.c`` containing the ROMFS file +system image. To do this, ``mkromfsimg.sh`` uses two tools that must be +installed in your system: + + #. The ``genromfs`` tool that is used to generate the ROMFS file system + image. + + #. The ``xxd`` tool that is used to create the C header file. + +Customizing ROMFS Image +======================= + +The ROMFS image can be generated from the content in the corresponding +``board/arch/board/board/src/etc`` directory, and added by Makefile. + +**Example Configurations**. Here are some configurations that have +``CONFIG_ETC_ROMFS=y`` in the NuttX configuration file. They might +provide useful examples: + + - ``boards/risc-v/bl808/ox64/src/etc`` + - ``boards/risc-v/qemu-rv/rv-virt/src/etc`` + - ``boards/risc-v/esp32c3/esp32c3-devkit/src/etc`` + - ``boards/risc-v/k230/canmv230/src/etc`` + - ``boards/risc-v/jh7110/star64/src/etc`` + - ``boards/arm64/rk3399/nanopi_m4/src/etc`` + - ``boards/sim/sim/sim/src/etc`` diff --git a/Documentation/guides/index.rst b/Documentation/guides/index.rst index 9f092e140a8b7..01e1175553b25 100644 --- a/Documentation/guides/index.rst +++ b/Documentation/guides/index.rst @@ -30,3 +30,4 @@ Guides stm32nullpointer.rst stm32ccm.rst stackrecord.rst + etcromfs.rst diff --git a/Documentation/guides/pysimcoder.rst b/Documentation/guides/pysimcoder.rst index 991c802363c99..f202b1a162ae8 100644 --- a/Documentation/guides/pysimcoder.rst +++ b/Documentation/guides/pysimcoder.rst @@ -49,7 +49,7 @@ with NuttX. The list is the following: ``CONFIG_ARCH_RAMVECTORS=y`` ``CONFIG_NSH_FILE_APPS=y`` ``CONFIG_BOARDCTL_APP_SYMTAB=y`` ``CONFIG_NSH_LINELEN=64`` ``CONFIG_BOARDCTL_OS_SYMTAB=y`` ``CONFIG_NSH_READLINE=y`` -``CONFIG_BUILTIN=y`` ``CONFIG_NSH_ROMFSETC=y`` +``CONFIG_BUILTIN=y`` ``CONFIG_ETC_ROMFS=y`` ``CONFIG_ELF=y`` ``CONFIG_PSEUDOTERM=y`` ``CONFIG_FS_BINFS=y`` ``CONFIG_PTHREAD_CLEANUP_STACKSIZE=1`` ``CONFIG_FS_PROCFS=y`` ``CONFIG_PTHREAD_MUTEX_TYPES=y`` diff --git a/Documentation/guides/qemugdb.rst b/Documentation/guides/qemugdb.rst index 488953960f69b..e071e06ea5d4b 100644 --- a/Documentation/guides/qemugdb.rst +++ b/Documentation/guides/qemugdb.rst @@ -53,42 +53,33 @@ Start GDB to connect to QEMU .. code-block:: console - $ gdb-multiarch -ix tools/nuttx-gdbinit nuttx - (gdb) target extended-remote localhost:1234 - Remote debugging using localhost:1234 - 0x000012ee in up_mdelay (milliseconds=milliseconds@entry=250) - at common/arm_mdelay.c:51 - 51 for (j = 0; j < CONFIG_BOARD_LOOPSPERMSEC; j++) + $ gdb-multiarch nuttx -ex "source tools/gdb/__init__.py" -ex "target remote 127.0.0.1:1234" + Type "apropos word" to search for commands related to "word"... + Reading symbols from nuttx... + set pagination off + source tools/gdb/lists.py + source tools/gdb/utils.py + source tools/gdb/memdump.py + + if use thread command, please don't use 'continue', use 'c' instead !!! + source tools/gdb/thread.py + "handle SIGUSR1 "nostop" "pass" "noprint" + Remote debugging using 127.0.0.1:1234 + 0x0000a45a in up_idle () at chip/common/tiva_idle.c:62 + 62 } (gdb) #. From (gdb) prompt you can run commands to inpect NuttX: .. code-block:: console - (gdb) info_nxthreads - target examined - _target_arch.name=armv7 - $_target_has_fpu : 1 - $_target_has_smp : 0 - saved current_tcb (pid=0) - * - 0 Thread 0x20001538 (Name: Idle Task, State: Running, Priority: 0, Stack: 464/1000) PC: 0x12fc in up_mdelay() - saved current_tcb (pid=0) - - 1 Thread 0x20005060 (Name: hpwork, State: Waiting,Semaphore, Priority: 224, Stack: 320/1992) PC: 0x47dd in work_thread() - saved current_tcb (pid=0) - - 2 Thread 0x20005c30 (Name: nsh_main, State: Waiting,Semaphore, Priority: 100, Stack: 1016/2000) PC: 0x1 in _vectors() - saved current_tcb (pid=0) - - 3 Thread 0x20006b40 (Name: NTP daemon, State: Waiting,Signal, Priority: 100, Stack: 864/1952) PC: 0x0 in _vectors() - saved current_tcb (pid=0) - - 4 Thread 0x20008540 (Name: telnetd, State: Waiting,Semaphore, Priority: 100, Stack: 616/2008) PC: 0x20008fd4 in No() - saved current_tcb (pid=0) - saved current_tcb (pid=0) - saved current_tcb (pid=0) - saved current_tcb (pid=0) + (gdb) info threads + Id Thread Info Frame + *0 Thread 0x2000168c (Name: Idle_Task, State: Running, Priority: 0, Stack: 1008) 0xa45a up_idle() at chip/common/tiva_idle.c:62 + 1 Thread 0x20005270 (Name: hpwork, State: Waiting,Semaphore, Priority: 224, Stack: 1984) 0xa68c up_switch_context() at common/arm_switchcontext.c:95 + 2 Thread 0x20005e30 (Name: nsh_main, State: Waiting,Semaphore, Priority: 100, Stack: 2008) 0xa68c up_switch_context() at common/arm_switchcontext.c:95 + 3 Thread 0x20006d48 (Name: NTP_daemon, State: Waiting,Signal, Priority: 100, Stack: 1960) 0xa68c up_switch_context() at common/arm_switchcontext.c:95 + 4 Thread 0x20008b60 (Name: telnetd, State: Waiting,Semaphore, Priority: 100, Stack: 2016) 0xa68c up_switch_context() at common/arm_switchcontext.c:95 (gdb) As you can see QEMU and GDB are powerful tools to debug NuttX without using external board or expensive debugging hardware. diff --git a/Documentation/implementation/bottomhalf_interrupt.rst b/Documentation/implementation/bottomhalf_interrupt.rst index 18862dadfed33..dbbaa025ae4cc 100644 --- a/Documentation/implementation/bottomhalf_interrupt.rst +++ b/Documentation/implementation/bottomhalf_interrupt.rst @@ -6,7 +6,7 @@ RTOS Interrupts =============== A well-design RTOS depends on the most minimal of interrupt level processing. -This is a very different concept that for bare metal programming: +This is a very different concept from that for bare metal programming: * With bare metal programming most of the real-time work is usually performed in interrupt handlers. Interrupt handler execution may then extend in time diff --git a/Documentation/implementation/critical_sections.rst b/Documentation/implementation/critical_sections.rst index c5fcd31ffcd09..227935b0129b9 100644 --- a/Documentation/implementation/critical_sections.rst +++ b/Documentation/implementation/critical_sections.rst @@ -408,7 +408,7 @@ You have these options: or code when they could be re-designed to use critical sections over shorter code sequences. -#. In some cases, use of critical sections or disabling of pre-emption could replaced +#. In some cases, use of critical sections or disabling of pre-emption could be replaced with a locking semaphore. The scope of the locking effect for the use of such locks is not global but is limited only to tasks that share the same resource. Critical sections should correctly be used only to protect resources that are shared between diff --git a/Documentation/index.rst b/Documentation/index.rst index 8d756ffde79ee..c8b6fd9c215c8 100644 --- a/Documentation/index.rst +++ b/Documentation/index.rst @@ -38,5 +38,6 @@ Last Updated: |today| faq/index.rst guides/index.rst glossary.rst + logos/index.rst .. include:: substitutions.rst diff --git a/Documentation/known-warnings.txt b/Documentation/known-warnings.txt index 4688c74d49618..6b882f3751722 100644 --- a/Documentation/known-warnings.txt +++ b/Documentation/known-warnings.txt @@ -3,4 +3,15 @@ # Function and (enum or struct) name .*Duplicate C declaration.*\n.*'\.\. c:.*:: net_driver_s'.* -.*Duplicate C declaration.*\n.*'\.\. c:.*:: sigaction'.* +.*Duplicate C declaration.*\n.*'\.\. c:.*::.*sigaction.* +.*Duplicate C declaration.*\n.*'\.\. c:.*::.*open.* +.*Duplicate C declaration.*\n.*'\.\. c:.*::.*close.* +.*Duplicate C declaration.*\n.*'\.\. c:.*::.*read.* +.*Duplicate C declaration.*\n.*'\.\. c:.*::.*write.* +.*Duplicate C declaration.*\n.*'\.\. c:.*::.*ioctl.* +.*Duplicate C declaration.*\n.*'\.\. c:.*::.*mmap.* +.*Duplicate C declaration.*\n.*'\.\. c:.*::.*poll.* +.*Duplicate C declaration.*\n.*'\.\. c:.*::.*dup.* +.*Duplicate C declaration.*\n.*'\.\. c:.*::.*rewinddir.* +.*Duplicate C declaration.*\n.*'\.\. c:.*::.*bind.* +.*Duplicate C declaration.*\n.*'\.\. c:.*::.*unlink.* diff --git a/Documentation/logos/NuttX_Logo.png b/Documentation/logos/NuttX_Logo.png new file mode 100644 index 0000000000000..0ad4c912b4782 Binary files /dev/null and b/Documentation/logos/NuttX_Logo.png differ diff --git a/Documentation/logos/NuttX_Logo.svg b/Documentation/logos/NuttX_Logo.svg new file mode 100644 index 0000000000000..8df0ecc7223df --- /dev/null +++ b/Documentation/logos/NuttX_Logo.svg @@ -0,0 +1,291 @@ + + + + diff --git a/Documentation/logos/NuttX_Orig.png b/Documentation/logos/NuttX_Orig.png new file mode 100644 index 0000000000000..360e657dd20f3 Binary files /dev/null and b/Documentation/logos/NuttX_Orig.png differ diff --git a/Documentation/logos/NuttX_Simple.png b/Documentation/logos/NuttX_Simple.png new file mode 100644 index 0000000000000..e20a65f8905e9 Binary files /dev/null and b/Documentation/logos/NuttX_Simple.png differ diff --git a/Documentation/logos/NuttX_Simple.svg b/Documentation/logos/NuttX_Simple.svg new file mode 100644 index 0000000000000..7455df72625e8 --- /dev/null +++ b/Documentation/logos/NuttX_Simple.svg @@ -0,0 +1,237 @@ + + + + + NuttX Logo + + + + + + image/svg+xml + + NuttX Logo + 5 Nov 2021 + + + Alan Carvalho de Assis + + + + + Alan Carvalho de Assis + + + + + Alan Carvalho de Assis + + + + + NuttX + Logo + + + This is the NuttX Logo created on Inkscape by Alan Carvalho de Assis + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Documentation/logos/index.rst b/Documentation/logos/index.rst new file mode 100644 index 0000000000000..75019fa8dfad1 --- /dev/null +++ b/Documentation/logos/index.rst @@ -0,0 +1,47 @@ +.. todo:: + Add NuttX Logo to use on eletronic boards PCBs. + +=========== +NuttX Logos +=========== + +The original NuttX logo was created by Greg Nutt (the creator of NuttX) himself. + +According with Greg his idea was to create a simple logo with some retro style. + +That original vector file was lost and all we have is a PNG file depicting it: + +.. figure:: NuttX_Orig.png + :align: center + +Modern NuttX Logo +----------------- + +Some years ago Dave Marples created a representation of the original Logo, +it is very similar to the original Logo and seems more modern: + +.. figure:: NuttX_Logo.png + :align: center + +Download SVG version :download:`svg ` + +This logo can be used in websites, promotion materials, etc. + +Simplified NuttX Logo +--------------------- + +There is also a simplified Logo created by Alan C. Assis. This version can be +used on Documentation, T-Shirts and other places where we don't have a huge hue +of colors. + +.. figure:: NuttX_Simple.png + :align: center + +Download SVG version :download:`svg ` + +These logos are not registered by Apache Foundation, but please use it with +respect to the NuttX Project, always to help to promote the project. + +If you need to use it with some commercial product, please send an email +communicating your intention to: private@nuttx.apache.org + diff --git a/Documentation/platforms/arm/a1x/index.rst b/Documentation/platforms/arm/a1x/index.rst index e1a3cd2f8789f..20a72b915172f 100644 --- a/Documentation/platforms/arm/a1x/index.rst +++ b/Documentation/platforms/arm/a1x/index.rst @@ -12,7 +12,7 @@ have are supported by NuttX: board, but the others may be compatible: Refer to the NuttX board - `README `__ + `README `__ file for further information. **STATUS**. This port was an experiment was was not completely diff --git a/Documentation/platforms/arm/am335x/index.rst b/Documentation/platforms/arm/am335x/index.rst index b69e7342cca7c..901baf600f1a3 100644 --- a/Documentation/platforms/arm/am335x/index.rst +++ b/Documentation/platforms/arm/am335x/index.rst @@ -20,7 +20,7 @@ AM335x are supported by NuttX: - **NuttX-7.31**. An LCD driver was added in NuttX-7.31. Refer to the Beaglebone Black board - `README `__ + `README `__ file for further, up-to-date information. Supported Boards diff --git a/Documentation/platforms/arm/efm32/index.rst b/Documentation/platforms/arm/efm32/index.rst index 6a42fd7f0b379..120bc9b869e6b 100644 --- a/Documentation/platforms/arm/efm32/index.rst +++ b/Documentation/platforms/arm/efm32/index.rst @@ -29,7 +29,7 @@ This is a port for the Silicon Laboratories' EFM32 supported are included, but not fully tested. Refer to the EFM32 Gecko Starter Kit - `README.txt `__ + `README.txt `__ file for further information. #. **Olimex EFM32G880F120-STK**. This board features: @@ -50,7 +50,7 @@ This is a port for the Silicon Laboratories' EFM32 required to make further progress in testing. Refer to the Olimex EFM32G880F120-STK - `README.txt `__ + `README.txt `__ for further information. SiLabs EFM32 Giant Gecko diff --git a/Documentation/platforms/arm/gd32f4/boards/gd32f450zk-aiotbox/gd32f450z_aiotbox.png b/Documentation/platforms/arm/gd32f4/boards/gd32f450zk-aiotbox/gd32f450z_aiotbox.png new file mode 100644 index 0000000000000..9c9ad992d427e Binary files /dev/null and b/Documentation/platforms/arm/gd32f4/boards/gd32f450zk-aiotbox/gd32f450z_aiotbox.png differ diff --git a/Documentation/platforms/arm/gd32f4/boards/gd32f450zk-aiotbox/index.rst b/Documentation/platforms/arm/gd32f4/boards/gd32f450zk-aiotbox/index.rst new file mode 100644 index 0000000000000..6a67c8d2cee01 --- /dev/null +++ b/Documentation/platforms/arm/gd32f4/boards/gd32f450zk-aiotbox/index.rst @@ -0,0 +1,11 @@ +================== +gd32f450zk-aiotbox +================== + +The GD32F450Z-AIOTBOX board is a Xiaomi AIoT development platform U1 +control board that uses the GD32F450ZK chip as the core. + +.. figure:: gd32f450z_aiotbox.png + :align: center + :alt: gd32f450z_aiotbox + diff --git a/Documentation/platforms/arm/gd32f4/boards/gd32f470zk-aiotbox/gd32f470z_aiotbox.png b/Documentation/platforms/arm/gd32f4/boards/gd32f470zk-aiotbox/gd32f470z_aiotbox.png new file mode 100644 index 0000000000000..6ae043fab2072 Binary files /dev/null and b/Documentation/platforms/arm/gd32f4/boards/gd32f470zk-aiotbox/gd32f470z_aiotbox.png differ diff --git a/Documentation/platforms/arm/gd32f4/boards/gd32f470zk-aiotbox/index.rst b/Documentation/platforms/arm/gd32f4/boards/gd32f470zk-aiotbox/index.rst new file mode 100644 index 0000000000000..334d193ff9ce4 --- /dev/null +++ b/Documentation/platforms/arm/gd32f4/boards/gd32f470zk-aiotbox/index.rst @@ -0,0 +1,15 @@ +================== +gd32f470zk-aiotbox +================== + +The GD32F470Z-AIOTBOX board is a Xiaomi AIoT development platform U1 +control board that uses the GD32F470ZK chip as the core. + +The GD32F470ZK features a single-core ARM Cortex-M4F MCU which can run up +to 240 MHz with flash accesses zero wait states, 3072kiB of Flash, 256kiB +of SRAM and 114 GPIOs. + +.. figure:: gd32f470z_aiotbox.png + :align: center + :alt: gd32f470z_aiotbox + diff --git a/Documentation/platforms/arm/gd32f4/boards/gd32f470zk-eval/gd32f470z_eval.png b/Documentation/platforms/arm/gd32f4/boards/gd32f470zk-eval/gd32f470z_eval.png old mode 100755 new mode 100644 diff --git a/Documentation/platforms/arm/imx6/index.rst b/Documentation/platforms/arm/imx6/index.rst index 2b006dd118099..88fd92f720155 100644 --- a/Documentation/platforms/arm/imx6/index.rst +++ b/Documentation/platforms/arm/imx6/index.rst @@ -6,7 +6,7 @@ The basic port has been completed for the following i.MX6 board: - **Sabre-6Quad**. This is a port to the NXP/Freescale Sabre-6Quad board. Refer to the NuttX board - `README `__ + `README `__ file for further information. **STATUS:** The basic, minimal port is code complete and introduced @@ -18,7 +18,7 @@ The basic port has been completed for the following i.MX6 board: Basic support of NuttX running in SMP mode on the i.MX6Q was also accomplished in NuttX-7.16. However, there are still known issues with SMP support on this platform as described in the - `README `__ + `README `__ file for the board. Supported Boards diff --git a/Documentation/platforms/arm/kinetis/index.rst b/Documentation/platforms/arm/kinetis/index.rst index 311247b345cf2..9217400014f09 100644 --- a/Documentation/platforms/arm/kinetis/index.rst +++ b/Documentation/platforms/arm/kinetis/index.rst @@ -52,7 +52,7 @@ NuttX 7.17. Initial release includes two NSH configurations with support for on-board LEDs, buttons, and Ethernet with the on-board KSZ8081 PHY. SDHC supported has been integrated, but not verified. Refer to the NuttX board -`README `__ +`README `__ file for further information. **MK64FN1M0VMD12**. Architecture support for the \_MK64FN1M0VMD12 was @@ -67,7 +67,7 @@ by `TWR-SER `__ which includes (among other things), an RS232 and Ethernet connections. Refer to the NuttX board -`README `__ +`README `__ file for further information. **Driver Status**. @@ -90,7 +90,7 @@ NXP/FreeScale Kinetis K66 Support for the Kinetis K64 family and specifically for the **NXP/Freescale Freedom K66F** board was contributed by David Sidrane in NuttX 7.20. Refer to the NuttX board -`README `__ +`README `__ file for further information. **Driver Status**. diff --git a/Documentation/platforms/arm/lc823450/index.rst b/Documentation/platforms/arm/lc823450/index.rst index ccce0540048cf..be91d292e906b 100644 --- a/Documentation/platforms/arm/lc823450/index.rst +++ b/Documentation/platforms/arm/lc823450/index.rst @@ -29,7 +29,7 @@ Semiconductor `__. Refer to the NuttX board -`README `__ +`README `__ file for details of the NuttX port. This port is intended to test LC823450 features including SMP. Supported diff --git a/Documentation/platforms/arm/lpc17xx/index.rst b/Documentation/platforms/arm/lpc17xx/index.rst index 1f05d19e64774..c500f1047c214 100644 --- a/Documentation/platforms/arm/lpc17xx/index.rst +++ b/Documentation/platforms/arm/lpc17xx/index.rst @@ -75,7 +75,7 @@ boards. - Support for the mbed board was contributed by Dave Marples and released in NuttX-5.11. Refer to the NuttX board - `README `__ + `README `__ file for further information. #. **Olimex LPC1766-STK** @@ -90,7 +90,7 @@ boards. - The NuttX-5.17 released added support for low-speed USB devices, interrupt endpoints, and a *USB host HID keyboard class driver*. - Refer to the NuttX board - `README `__ + `README `__ file for further information. Verified configurations are now available for the NuttShell with @@ -111,7 +111,7 @@ boards. Verified configurations include DHCPD, the NuttShell (NSH), NuttX graphis (NX), THTTPD, and USB mass storage device. Refer to the NuttX board - `README `__ + `README `__ file for further information. #. **Zilogic's ZKIT-ARM-1769 board** @@ -121,7 +121,7 @@ boards. NuttX-6.26. The NuttX Buildroot toolchain is used by default. Verifed configurations include the "Hello, World!" example application and a THTTPD demonstration. Refer to the NuttX board - `README `__ + `README `__ file for further information. #. **Micromint Lincoln60 board with an NXP LPC1769** @@ -130,7 +130,7 @@ boards. NuttX-6.20. As contributed board support, I am unsure of what all has been verfied and what has not. See the Microment website and the NuttX board - `README `__ + `README `__ file for further information about the Lincoln board. #. **U-Blox Modem Evaluation (LPCXpresso LPC1768)** @@ -139,7 +139,7 @@ boards. and made available in NuttX-7.15. This is a variant of the LPCXpresso LPC1768 board support with special provisions for the U-Blox Model Evaluation board. See the NuttX board - `README `__ + `README `__ file for further information about this port. #. **Keil MCB1700 (LPC1768)** diff --git a/Documentation/platforms/arm/lpc40xx/boards/lx_cpu/README.txt b/Documentation/platforms/arm/lpc40xx/boards/lx_cpu/README.txt index be2b44bef93ac..0b9743e87e7e5 100644 --- a/Documentation/platforms/arm/lpc40xx/boards/lx_cpu/README.txt +++ b/Documentation/platforms/arm/lpc40xx/boards/lx_cpu/README.txt @@ -99,7 +99,7 @@ Using OpenOCD with the Olimex ARM-USB-OCD Building OpenOCD under Cygwin: - Refer to boards/arm/lpc17xx_40xx/olimex-lpc1766stk/README.txt + Refer to Documentation/platforms/arm/lpc17xx/boards/olimex-lpc1766stk/README.txt Installing OpenOCD in Ubuntu Linux: diff --git a/Documentation/platforms/arm/lpc43xx/index.rst b/Documentation/platforms/arm/lpc43xx/index.rst index f442b5ed8dc71..b8772f1cf40ba 100644 --- a/Documentation/platforms/arm/lpc43xx/index.rst +++ b/Documentation/platforms/arm/lpc43xx/index.rst @@ -12,7 +12,7 @@ website `__ + `README `__ file for more detailed information about this port. - **NuttX-6.20** The basic LPC4330-Xplorer port is complete. The basic @@ -28,7 +28,7 @@ website `__ + `README `__ file for more detailed information about this port. - **NuttX-7.6**. The basic port is was contributed by Toby Duckworth. @@ -42,7 +42,7 @@ for more detailed information about the LPC4357 and the LPC4357-EVB. development board featuring the NXP LPC4370FET100 MCU. - **STATUS:** Refer to the NuttX board - `README `__ + `README `__ file for more detailed information about this port. - **NuttX-7.12** The NXP LPC4370-Link2 port is was contributed by Lok @@ -52,7 +52,7 @@ development board featuring the NXP LPC4370FET100 MCU. LPC4337-WS development board featuring the NXP LPC4337JBD144 MCU. - **STATUS:** Refer to the NuttX board - `README `__ + `README `__ file for more detailed information about this port. - **NuttX-7.14** The NXP WaveShare LPC4337-WS port is was contributed diff --git a/Documentation/platforms/arm/lpc54xx/index.rst b/Documentation/platforms/arm/lpc54xx/index.rst index d6db70d9dd71c..adb4ff3190d5a 100644 --- a/Documentation/platforms/arm/lpc54xx/index.rst +++ b/Documentation/platforms/arm/lpc54xx/index.rst @@ -23,7 +23,7 @@ relevant changes incorporated in NuttX-7.26. Framebuffer" feature also added in NuttX-7.29. Refer to the LPCXpresso-LPC54628 board -`README `__ +`README `__ file for more detailed information about this port. Supported Boards diff --git a/Documentation/platforms/arm/nrf52/boards/nrf52840-dk/index.rst b/Documentation/platforms/arm/nrf52/boards/nrf52840-dk/index.rst index 04c565c507fd5..f48585f774a08 100644 --- a/Documentation/platforms/arm/nrf52/boards/nrf52840-dk/index.rst +++ b/Documentation/platforms/arm/nrf52/boards/nrf52840-dk/index.rst @@ -138,3 +138,20 @@ usbnsh ------ Basic NuttShell configuration (CDCACM console enabled in USB Port, at 115200 bps). + +ieee802154_6lowpan +------------------ + +Cheat Sheet. Here is a concise summary of all all the steps needed to +run the UDP test (C=Coordinator; E=Endpoint):: + + C: nsh> i8 wpan0 startpan cd:ab + C: nsh> i8 set saddr 0A:00 + C: nsh> i8 set ep_saddr 0B:00 + C: nsh> i8 acceptassoc + E: nsh> i8 wpan0 assoc + C: nsh> ifup wpan0 + C: nsh> ifconfig <-- To get the + E: nsh> ifup wpan0 + C: nsh> udpserver & + E: nsh> udpclient & diff --git a/Documentation/platforms/arm/nrf52/ieee802154.rst b/Documentation/platforms/arm/nrf52/ieee802154.rst new file mode 100644 index 0000000000000..7d2c348ec51a3 --- /dev/null +++ b/Documentation/platforms/arm/nrf52/ieee802154.rst @@ -0,0 +1,44 @@ +========================== +Nordic nRF52 IEEE 802.15.4 +========================== + +.. note:: + + This driver is highly experimental. + Help with development and testing will be appreciated ;) + +Supported features: + +* frame transmission +* frame reception and filtering +* immediate ACK (incoming and outgoing) +* promiscuous mode +* delayed transmision +* radio events trace +* setting pending bit for all incoming Data Request frames +* un-slotted CSMA-CA + +Work in progres features (some logic is present, but they require more work): + +* beacon transmision (periodic transmition works, but requires verification) +* slotted CSMA-CA +* GTS + +Fetures not implemented: + +* enhanced ACK (Enh-ACK) +* enhanced beacon +* low power mode +* advanced features from IEEE 802.15.4e (DSME, TSCH) + +Reserved peripherals +==================== + +This implementation reserves the following peripherals: + +* ``RADIO`` - used for radio operations + +* ``TIMER0`` - used as high resolution timer for ACK, IFS and other radio delays + +* ``RTC0`` - if superframe support is enabled, used as low power timer to hande + superframe events diff --git a/Documentation/platforms/arm/nrf52/index.rst b/Documentation/platforms/arm/nrf52/index.rst index 2bb73de03cf4e..912422ee17ec8 100644 --- a/Documentation/platforms/arm/nrf52/index.rst +++ b/Documentation/platforms/arm/nrf52/index.rst @@ -51,9 +51,9 @@ Peripheral Support The following list indicates peripherals supported in NuttX: -========== ======= ===== +========== ======= =============== Peripheral Support Notes -========== ======= ===== +========== ======= =============== GPIO Yes GPIOTE Yes I2S No @@ -64,7 +64,7 @@ PPI Yes PWM Yes QDEC No QSPI Yes -RADIO Yes Basic +RADIO Yes BLE, IEEE 802.15.4 RNG Yes RTC Yes SAADC Yes @@ -78,7 +78,7 @@ UART Yes UARTE No USBD Yes WDT Yes -========== ======= ===== +========== ======= =============== Peripherals such as AAR, ACL, CCM, ECB are not directly used by NuttX since they are part of BLE controller implementation (link). @@ -206,6 +206,11 @@ is provided with settings already set. Note that in this case, some peripherals (mostly those related to BLE) will be unavailable. Some PPI channels will also be ocuppied (``NRF52_PPI_NUM_CONFIGURABLE_CHANNELS`` will be set accordingly in this case). +IEEE 802.15.4 Support +===================== + +Details about IEEE 802.15.4 support for nRF52 can be found in :doc:`ieee802154`. + Supported Boards ================ @@ -214,3 +219,4 @@ Supported Boards :maxdepth: 1 boards/*/* + ieee802154.rst diff --git a/Documentation/platforms/arm/nuc1xx/index.rst b/Documentation/platforms/arm/nuc1xx/index.rst index cde4ca3d92673..14f35042181ed 100644 --- a/Documentation/platforms/arm/nuc1xx/index.rst +++ b/Documentation/platforms/arm/nuc1xx/index.rst @@ -10,7 +10,7 @@ This initial support is very minimal: There is a NuttShell (:ref:`NSH `) configuration that might be the basis for an application development. As of this writing, more device drivers are needed to make this a more complete port. Refer to the NuttX board -`README `__ +`README `__ file for further information. **Memory Usage**. For a full-featured RTOS such as NuttX, providing diff --git a/Documentation/platforms/arm/rp2040/boards/adafruit-feather-rp2040/index.rst b/Documentation/platforms/arm/rp2040/boards/adafruit-feather-rp2040/index.rst index 6c7b850fca054..fb7656d541bc9 100644 --- a/Documentation/platforms/arm/rp2040/boards/adafruit-feather-rp2040/index.rst +++ b/Documentation/platforms/arm/rp2040/boards/adafruit-feather-rp2040/index.rst @@ -125,7 +125,7 @@ audiopack --------- NuttShell configuration (console enabled in UART0, at 115200 bps) with -support for NSPlayer audio player. +support for NXPlayer audio player. composite --------- diff --git a/Documentation/platforms/arm/rp2040/boards/adafruit-kb2040/index.rst b/Documentation/platforms/arm/rp2040/boards/adafruit-kb2040/index.rst index 105bc89e63904..199abe088faf0 100644 --- a/Documentation/platforms/arm/rp2040/boards/adafruit-kb2040/index.rst +++ b/Documentation/platforms/arm/rp2040/boards/adafruit-kb2040/index.rst @@ -101,7 +101,7 @@ audiopack --------- NuttShell configuration (console enabled in UART0, at 115200 bps) with -support for NSPlayer audio player. +support for NXPlayer audio player. composite --------- diff --git a/Documentation/platforms/arm/rp2040/boards/raspberrypi-pico-w/index.rst b/Documentation/platforms/arm/rp2040/boards/raspberrypi-pico-w/index.rst index b88ec8fb43ae8..10df77037ccd4 100644 --- a/Documentation/platforms/arm/rp2040/boards/raspberrypi-pico-w/index.rst +++ b/Documentation/platforms/arm/rp2040/boards/raspberrypi-pico-w/index.rst @@ -149,7 +149,7 @@ audiopack --------- NuttShell configuration (console enabled in UART0, at 115200 bps) with -support for NSPlayer audio player. +support for NXPlayer audio player. composite --------- diff --git a/Documentation/platforms/arm/rp2040/boards/raspberrypi-pico/index.rst b/Documentation/platforms/arm/rp2040/boards/raspberrypi-pico/index.rst index fd1e52b1fa466..e25db55f909ce 100644 --- a/Documentation/platforms/arm/rp2040/boards/raspberrypi-pico/index.rst +++ b/Documentation/platforms/arm/rp2040/boards/raspberrypi-pico/index.rst @@ -127,7 +127,19 @@ audiopack --------- NuttShell configuration (console enabled in UART0, at 115200 bps) with -support for NSPlayer audio player. +support for NXPlayer audio player. + +bmp280 +------ + +NuttShell configuration (console enabled in USB Port, at 115200 bps) with support for Bosch BMP280 sensor: + +.. code-block:: console + + nsh> bmp280 + Absolute pressure [hPa] = 1008.460022 + Temperature [C] = 21.809999 + nsh> composite --------- diff --git a/Documentation/platforms/arm/rp2040/boards/w5500-evb-pico/W5500-EVB-Pico.png b/Documentation/platforms/arm/rp2040/boards/w5500-evb-pico/W5500-EVB-Pico.png new file mode 100644 index 0000000000000..a228fa84fe697 Binary files /dev/null and b/Documentation/platforms/arm/rp2040/boards/w5500-evb-pico/W5500-EVB-Pico.png differ diff --git a/Documentation/platforms/arm/rp2040/boards/w5500-evb-pico/index.rst b/Documentation/platforms/arm/rp2040/boards/w5500-evb-pico/index.rst new file mode 100644 index 0000000000000..7e3b4f1a7cb0a --- /dev/null +++ b/Documentation/platforms/arm/rp2040/boards/w5500-evb-pico/index.rst @@ -0,0 +1,228 @@ +=============================== +W5500-EVB-Pico +=============================== + +The `W5500-EVB-Pico `_ +is a microcontroller evaluation board based on the Raspberry Pi RP2040 and fully +hardwired TCP/IP controller W5500 – and basically works the same as Raspberry Pi +Pico board but with additional Ethernet via W5500. + +.. figure:: W5500-EVB-Pico.png + :align: center + +Features +======== + +* RP2040 microcontroller chip +* Dual-core ARM Cortex M0+ processor, flexible clock running up to 133 MHz +* 264kB of SRAM, and 2MB of on-board Flash memory +* Castellated module allows soldering direct to carrier boards +* USB 1.1 Host and Device support +* Low-power sleep and dormant modes +* Drag & drop programming using mass storage over USB +* 26 multi-function GPIO pins +* 2× SPI, 2× I2C, 2× UART, 3× 12-bit ADC, 16× controllable PWM channels +* Accurate clock and timer on-chip +* Temperature sensor +* Accelerated floating point libraries on-chip +* 8 × Programmable IO (PIO) state machines for custom peripheral support +* Ethernet port via WIZnet W5500, hardwired to SPI0 and two GPIO pins. + +Supported RP2040 capabilities +============================= + +* UART (console port) + + * GPIO 0 (UART0 TX) and GPIO 1 (UART0 RX) are used for the console. + +* I2C +* SPI (master only) +* DMAC +* PWM +* ADC +* Watchdog +* USB device + + * MSC, CDC/ACM serial and these composite device are supported. + * CDC/ACM serial device can be used for the console. + +* PIO (RP2040 Programmable I/O) +* Flash ROM Boot +* SRAM Boot + + * If Pico SDK is available, nuttx.uf2 file which can be used in + BOOTSEL mode will be created. + * Persistent flash filesystem in unused flash ROM + +Currently unsupported RP2040 capabilities +========================================= + +* SPI Slave Mode +* SSI +* RTC +* Timers + +Serial Console +============== + +The board is configured to use the USB connection as the serial console. + +Buttons and LEDs +================ + +User LED controlled by GPIO25. + +A BOOTSEL button, which if held down when power is first +applied to the board, will cause the RP2040 to boot into programming +mode and appear as a storage device to a computer connected via USB. +Saving a .UF2 file to this device will replace the Flash ROM contents +on the RP2040. + +Pin Mapping +=========== +Pads numbered anticlockwise from USB connector. + +===== ========== ========== +Pad Signal Notes +===== ========== ========== +1 GPIO0 Default TX for UART0 serial console +2 GPIO1 Default RX for UART1 serial console +3 Ground +4 GPIO2 +5 GPIO3 +6 GPIO4 +7 GPIO5 +8 Ground +9 GPIO6 +10 GPIO7 +11 GPIO8 +12 GPIO9 +13 Ground +14 GPIO10 +15 GPIO11 +16 GPIO12 +17 GPIO13 +18 Ground +19 GPIO14 +20 GPIO15 +21 GPIO16 W5500 MISO +22 GPIO17 W5500 CSn +23 Ground +24 GPIO18 W5500 SCLK +25 GPIO19 W5500 MOSI +26 GPIO20 W5500 RSTn +27 GPIO21 W5500 INTn +28 Ground +29 GPIO22 +30 Run +31 GPIO26 ADC0 +32 GPIO27 ADC1 +33 AGND Analog Ground +34 GPIO28 ADC2 +35 ADC_VREF +36 3V3 Power output to peripherals +37 3V3_EN Pull to ground to turn off. +38 Ground +39 VSYS +5V Supply to board +40 VBUS Connected to USB +5V +===== ========== ========== + +Other RP2040 Pins +================= + +====== ========== +Signal Notes +====== ========== +GPIO23 Output - Power supply control. +GPIO24 Input - High if USB port or Pad 40 supplying power. +GPIO25 Output - On board LED. +ADC3 Input - Analog voltage equal to one third of VSys voltage. +====== ========== + +Separate pins for the Serial Debug Port (SDB) are available + +Power Supply +============ + +The W5500-EVB-Pico can be powered via the USB connector, +or by supplying +5V to pin 39. The board had a diode that prevents +power from pin 39 from flowing back to the USB socket, although +the socket can be power via pin 30. + +The W5500-EVB-Pico chip run on 3.3 volts. This is supplied +by an onboard voltage regulator. This regulator can be disabled +by pulling pin 37 to ground. + +The regulator can run in two modes. By default the regulator runs +in PFM mode which provides the best efficiency, but may be +switched to PWM mode for improved ripple by outputting a one +on GPIO23. + +Installation +============ + +1. Download Raspberry Pi Pico SDK + +:: + + $ git clone -b 1.1.2 https://github.com/raspberrypi/pico-sdk.git + +2. Set PICO_SDK_PATH environment variable + +:: + + $ export PICO_SDK_PATH= + +3. Configure and build NuttX + +:: + + $ git clone https://github.com/apache/nuttx.git nuttx + $ git clone https://github.com/apache/nuttx-apps.git apps + $ cd nuttx + $ make distclean + $ ./tools/configure.sh w5500-evb-pico:usbnsh + $ make V=1 + +4. Connect W5500-EVB-Pico board to USB port while pressing BOOTSEL. + The board will be detected as USB Mass Storage Device. + Then copy "nuttx.uf2" into the device. + (Same manner as the standard Pico SDK applications installation.) + +5. `usbnsh` configuration provides the console access by USB CDC/ACM serial + devcice. The console is available by using a terminal software on the USB + host. + +Configurations +============== + +usbnsh +------ + +USB CDC/ACM serial console with NuttShell. TCP/IPv4 & IPv6 networking is +supported via the Ethernet port. + +License exceptions +================== + +The following files are originated from the files in Pico SDK. +So, the files are licensed under 3-Clause BSD same as Pico SDK. + +Created by referring to the Pico SDK clock initialization +--------------------------------------------------------- + +* arch/arm/src/rp2040/rp2040_clock.c +* arch/arm/src/rp2040/rp2040_pll.c +* arch/arm/src/rp2040/rp2040_xosc.c + +Providing an API similar to the Pico SDK's hardware_pio API +----------------------------------------------------------- + +* arch/arm/src/rp2040/rp2040_pio.c +* arch/arm/src/rp2040/rp2040_pio.h +* arch/arm/src/rp2040/rp2040_pio_instructions.h + +Generated from rp2040.svd originally provided in Pico SDK +--------------------------------------------------------- + +* arch/arm/src/rp2040/hardware/\*.h diff --git a/Documentation/platforms/arm/rp2040/index.rst b/Documentation/platforms/arm/rp2040/index.rst index f24d245c589c3..4ff293b480f9f 100644 --- a/Documentation/platforms/arm/rp2040/index.rst +++ b/Documentation/platforms/arm/rp2040/index.rst @@ -23,6 +23,7 @@ USB PIO RP2040 Programmable I/O IRQs DMA +Clock Output ws2812 Smart pixels (e.g. Neopixel) Flash ROM Boot SRAM Boot If Pico SDK is available a nuttx.uf2 file will be created diff --git a/Documentation/platforms/arm/sam34/index.rst b/Documentation/platforms/arm/sam34/index.rst index 8a8b039ba85af..25782bf678816 100644 --- a/Documentation/platforms/arm/sam34/index.rst +++ b/Documentation/platforms/arm/sam34/index.rst @@ -53,7 +53,7 @@ Support for the SAM4L Xplained modules was added in NuttX-6.29: module Refer to the NuttX board -`README `__ +`README `__ file for further information. **Memory Usage**. The ATSAM4LC4C comes in a 100-pin package and has @@ -91,7 +91,7 @@ to NuttX by Masayuki Ishikawa in NuttX-7.19. The SAM4CM is a dual-CPU part and SMP was included for the ARMv7-M and SAM3/4 families. The SAM4CMP-DB board support includes an NSH configuration that operates in an SMP configuration. Refer to the NuttX board -`README `__ +`README `__ file for further information. Microchip SAM4E diff --git a/Documentation/platforms/arm/sama5/boards/sama5d3x-ek/README.txt b/Documentation/platforms/arm/sama5/boards/sama5d3x-ek/README.txt index fb7743aea3b8f..ef21c3e24bcda 100644 --- a/Documentation/platforms/arm/sama5/boards/sama5d3x-ek/README.txt +++ b/Documentation/platforms/arm/sama5/boards/sama5d3x-ek/README.txt @@ -502,13 +502,13 @@ Boot sequence DRAMBOOT -------- - See also boards/arm/sama5/sama5d4-ek/README.txt for a description of the DRAMBOOT + See also Documentation/platforms/arm/sama5/boards/sama5d4-ek/README.txt for a description of the DRAMBOOT program. This is a tiny version of NuttX that can run out of internal SRAM. If you put this program on the HSMCI1 microSD card as boot.bin, then it will boot on power up and you can download NuttX directly into DRAM by sending the nuttx.hex file over the serial connection. - The boards/arm/sama5/sama5d4-ek/README.txt also describes variants AT25BOOT and + The Documentation/platforms/arm/sama5/boards/sama5d4-ek/README.txt also describes variants AT25BOOT and SRAMBOOT. This have not been ported to the SAMA5D3x-EK, but are available if they are useful too you. diff --git a/Documentation/platforms/arm/sama5/boards/sama5d4-ek/README.txt b/Documentation/platforms/arm/sama5/boards/sama5d4-ek/README.txt index d840889c17e55..9b7311f09627d 100644 --- a/Documentation/platforms/arm/sama5/boards/sama5d4-ek/README.txt +++ b/Documentation/platforms/arm/sama5/boards/sama5d4-ek/README.txt @@ -4386,11 +4386,11 @@ Configurations Relevant configuration options include: - CONFIG_NSH_ROMFSETC=y : Enable mounting at of startup file system - CONFIG_NSH_ROMFSMOUNTPT="/etc" : Mount at /etc - CONFIG_NSH_ROMFSDEVNO=0 : Device is /dev/ram0 - CONFIG_NSH_ARCHROMFS=y : ROMFS image is at - boards/arm/sama5/sama5d4-ek/include/nsh_romfsimg.h + CONFIG_ETC_ROMFS=y : Enable mounting at of startup file system + ROMFS image is at + boards/arm/sama5/sama5d4-ek/src/etc_romfs.c + CONFIG_ETC_ROMFSMOUNTPT="/etc" : Mount at /etc + CONFIG_ETC_ROMFSDEVNO=0 : Device is /dev/ram0 The content of /etc/init.d/rcS can be see in the file rcS.template that can be found at: boards/arm/sama5/sama5d4-ek/include/rcS.template: diff --git a/Documentation/platforms/arm/sama5/index.rst b/Documentation/platforms/arm/sama5/index.rst index b50627800ab65..17f3f1ed8918f 100644 --- a/Documentation/platforms/arm/sama5/index.rst +++ b/Documentation/platforms/arm/sama5/index.rst @@ -102,7 +102,7 @@ There are ports to two Microchip SAMA5D3 boards: *Tickless* operation. Refer to the NuttX board - `README `__ + `README `__ file for further information. **Microchip SAMA5D3 Xplained development board** This is the port of NuttX @@ -124,7 +124,7 @@ does not have NOR FLASH and, as a consequence NuttX must boot into SDRAM with the help of U-Boot. Refer to the NuttX board -`README `__ +`README `__ file for further information. @@ -150,7 +150,7 @@ There is a port in progress on one Microchip SAMA5D4 board: that larger display. Support for a graphics media player is included (although there were issues with the WM8904 audio CODEC on my board). An SRAM bootloader was also included. Refer to the NuttX board - `README `__ + `README `__ file for current status. **Development Environments:** 1) Linux with native Linux GNU toolchain, diff --git a/Documentation/platforms/arm/samd2l2/boards/samd21-xplained/README.txt b/Documentation/platforms/arm/samd2l2/boards/samd21-xplained/README.txt index 483d494f513e8..1174150fd8067 100644 --- a/Documentation/platforms/arm/samd2l2/boards/samd21-xplained/README.txt +++ b/Documentation/platforms/arm/samd2l2/boards/samd21-xplained/README.txt @@ -27,7 +27,7 @@ Contents STATUS/ISSUES ============= - 1. See boards/arm/samd2l2/samd20-xplained/README.txt. + 1. See Documentation/platforms/arm/samd2l2/boards/samd20-xplained/README.txt. This port derives from the SAMD20 Xplained board board and all issues there should apply. diff --git a/Documentation/platforms/arm/samv7/boards/same70-xplained/README.txt b/Documentation/platforms/arm/samv7/boards/same70-xplained/README.txt index b69778f1edb16..916b1d3456ac2 100644 --- a/Documentation/platforms/arm/samv7/boards/same70-xplained/README.txt +++ b/Documentation/platforms/arm/samv7/boards/same70-xplained/README.txt @@ -32,7 +32,7 @@ Status/Open Issues via the EDBG VCOM and LED and buttons support. SDRAM and the HSMCI SD card slot also appear to be fully functional. -See also boards/arm/samv7/samv71-xult/README.txt +See also Documentation/platforms/arm/samv7/boards/samv71-xult/README.txt Serial Console ============== diff --git a/Documentation/platforms/arm/samv7/index.rst b/Documentation/platforms/arm/samv7/index.rst index 79acccde8cc19..644a26106f7d2 100644 --- a/Documentation/platforms/arm/samv7/index.rst +++ b/Documentation/platforms/arm/samv7/index.rst @@ -284,14 +284,28 @@ The peripheral implements four timer counter modules, each supporting three inde Universal Synchronous Asynchronous Receiver Transceiver (USART) --------------------------------------------------------------- -The MCU supports both UART and USART controllers. USART can be also used in RS-485 mode (enabled -by ``CONFIG_SAMV7_USARTx_RS485MODE`` option) or can be used with RX DMA support. For this purpose it -is required to configure idle bus timeout value in ``CONFIG_SAMV7_SERIAL_DMA_TIMEOUT``. This option -ensures data are read from the DMA buffer even if it is not full yet. TX DMA support is not implemented -as well as entire DMA support for UART peripheral. +The MCU supports both UART and USART controllers. USART peripheral can be used with TX and RX DMA support. +For RX DMA it is required to configure idle bus timeout value in ``CONFIG_SAMV7_SERIAL_DMA_TIMEOUT``. +This option ensures data are read from the DMA buffer even if it is not full yet. DMA support is +implemented only for USART peripheral and not for UART. + +There are several modes in which USART peripheral can operate (ISO7816, IrDA, RS485, SPI, LIN and LON). +Currently RS485 and SPI master are supported by NuttX. + +RS-485 mode is enabled by ``CONFIG_SAMV7_USARTx_RS485MODE`` option (``CONFIG_SAMV7_USART2_SERIALDRIVER`` +has to be true). In this case RTS pin is set to logical 1 before the serial driver is opened and board +specific logic is required to set it to logical zero. This has to be done in board initialization. Once +the driver is opened for the first time, architecture layer takes care of correct settings of RTS pin. +There is no additional requirement for driver initialization, the process is the same as with serial mode. + +SPI master (host) mode is enabled by ``CONFIG_SAMV7_USARTx_SPI_MASTER`` option. In this mode USART emulates +SPI peripheral with one slave (client) device (more slaves are not supported by the peripheral). The interface +with the driver is the same as with other SPI drivers but BSP layer does not have to support chip selection. +Command/data transfers are also not supported by the peripheral. Driver for SPI master mode is initialized +by :c:func:`sam_serial_spi_initialize` with port number as an argument. USART/UART can be also used to emulate 1 wire interface. SAMv7 MCUs do not have build in support for -1 wire therefore external hardware as TX/RX connection or optical isolation might be required. Selecting +1 wire, therefore external hardware as TX/RX connection or optical isolation might be required. Selecting ``CONFIG_SAMV7_UARTx_1WIREDRIVER`` enables 1 wire driver and sets USART/UART peripheral to this mode. Output pins are configured as if serial mode was selected plus TX is open drain. SAMv7 part of the driver is initialized by :c:func:`sam_1wireinitialize` with port number as an argument. diff --git a/Documentation/platforms/arm/stm32f4/boards/nucleo-f411re/index.rst b/Documentation/platforms/arm/stm32f4/boards/nucleo-f411re/index.rst index dd73b4b1270bf..0d6bb7228b6ec 100644 --- a/Documentation/platforms/arm/stm32f4/boards/nucleo-f411re/index.rst +++ b/Documentation/platforms/arm/stm32f4/boards/nucleo-f411re/index.rst @@ -1,5 +1,5 @@ ================ -ST Nucleo F401RE +ST Nucleo F411RE ================ This page discusses issues unique to NuttX configurations for the ST diff --git a/Documentation/platforms/arm/stm32f4/boards/nucleo-f412zg/index.rst b/Documentation/platforms/arm/stm32f4/boards/nucleo-f412zg/index.rst index cbad2e3d64eda..8414ec310e9ce 100644 --- a/Documentation/platforms/arm/stm32f4/boards/nucleo-f412zg/index.rst +++ b/Documentation/platforms/arm/stm32f4/boards/nucleo-f412zg/index.rst @@ -1,9 +1,9 @@ ================ -ST Nucleo F410RB +ST Nucleo F412ZG ================ This page discusses issues unique to NuttX configurations for the ST -Nucleo F410RB board from ST Micro. See +Nucleo F412ZG board from ST Micro. See http://www.st.com/en/evaluation-tools/nucleo-f412zg.html @@ -92,7 +92,7 @@ Pins and Connectors:: TTL to RS-232 converter connection:: - Nucleo CN10 STM32F410RB + Nucleo CN10 STM32F412ZG ----------- ------------ Pin 21 PA9 USART1_RX *Warning you make need to reverse RX/TX on Pin 33 PA10 USART1_TX some RS-232 converters @@ -125,7 +125,7 @@ Pins and Connectors:: TTL to RS-232 converter connection:: - Nucleo CN9 STM32F410RB + Nucleo CN9 STM32F412ZG ----------- ------------ Pin 1 PA3 USART2_RX *Warning you make need to reverse RX/TX on Pin 2 PA2 USART2_TX some RS-232 converters diff --git a/Documentation/platforms/arm/stm32f4/boards/stm32f401rc-rs485/index.rst b/Documentation/platforms/arm/stm32f4/boards/stm32f401rc-rs485/index.rst index 1371b309211e1..8bc84c461d42b 100644 --- a/Documentation/platforms/arm/stm32f4/boards/stm32f401rc-rs485/index.rst +++ b/Documentation/platforms/arm/stm32f4/boards/stm32f401rc-rs485/index.rst @@ -69,31 +69,32 @@ User Buttons The STM32F4-RS485 has 4 user switches. -======= ===== -SWITCH PINS -======= ===== -SWIO_1 PB13 -SWIO_2 PB14 -SWIO_3 PB15 -SWIO_4 PC6 -======= ===== +======= ===== ====== +SWITCH PINS LABEL +======= ===== ====== +SWIO_1 PB13 SW3 +SWIO_2 PB14 SW4 +SWIO_3 PB15 SW5 +SWIO_4 PC6 SW6[1] +======= ===== ====== + +[1] The switch SWIO_4 (SW6) is disabled due a conflict with PIN +PC6 when using USART6. UARTs ===== The STM32F4-RS485 has 1 USART available for user. -USART2 +USART6 ------ ========== ======= UART/USART PINS ========== ======= -CTS PA0 -RTS PA1 -TX PA2 [1] -RX PA3 -CK PA4 +TX PC6 [1] +RX PC7 +CK PA8 ========== ======= [1] Warning you make need to reverse RX/TX on some RS-232 converters @@ -154,7 +155,7 @@ Users can enable EERPOM support on STM32F4-RS485 by following below configuratio Temperature Sensor ================== -The STM32F4-RS485 development board has a temperature sensor TMP75 (TMP75AIDR) connected through I2C as below: +The STM32F4-RS485 development board has a temperature sensor TMP75 (compatible with LM75) connected through I2C as below: ====== ===== I2C PINS @@ -174,7 +175,7 @@ USART2 PINS ========== ===== USART2_RX RO USART2_RTS DE, /RE -SART2_RX DI +USART2_RX DI ========== ===== A/D Converter @@ -221,7 +222,28 @@ nsh --- Configures the NuttShell (nsh) located at apps/examples/nsh. This -configuration enables a serial console on UART2. +configuration enables a serial console on USART6. + + +usbnsh +------ + +Configures the NuttShell (nsh) located at apps/examples/nsh. This +configuration enables a serial console over USB. + +After flasing and reboot your board you should see in your dmesg logs:: + + [ 2638.948089] usb 1-1.4: new full-speed USB device number 16 using xhci_hcd + [ 2639.054432] usb 1-1.4: New USB device found, idVendor=0525, idProduct=a4a7, bcdDevice= 1.01 + [ 2639.054437] usb 1-1.4: New USB device strings: Mfr=1, Product=2, SerialNumber=3 + [ 2639.054438] usb 1-1.4: Product: CDC/ACM Serial + [ 2639.054440] usb 1-1.4: Manufacturer: NuttX + [ 2639.054441] usb 1-1.4: SerialNumber: 0 + [ 2639.074861] cdc_acm 1-1.4:1.0: ttyACM0: USB ACM device + [ 2639.074886] usbcore: registered new interface driver cdc_acm + [ 2639.074887] cdc_acm: USB Abstract Control Model driver for USB modems and ISDN adapters + +You may need to press **ENTER** 3 times before the NSH show up. sdcard ------ @@ -235,3 +257,344 @@ NSH commands:: nsh> mount -t procfs /proc nsh> mount -t vfat /dev/mmcsd0 /mnt +modbus_slave +------------ + +Configures the NuttShell (nsh) and enables modbus in slave mode. This +configuration enables a serial console on USART6. The RS-485 is connected +to USART2. Follow below precedure to use modbus test aplication, you will +need a USB to RS-485 converter to connect the board to a PC via RS-485. + +NuttShell configuration: + +Run modbus application at NSH:: + + nsh> modbus -help + USAGE: modbus [-d|e|s|q|h] + + Where: + -d : Disable protocol stack + -e : Enable the protocol stack + -s : Show current status + -q : Quit application + -h : Show this information + + nsh> modbus -e + +PC Configuration: + +Download and install mbpoll aplication:: + + sudo apt install mbpoll + +Check which TTY USB port is being used by you USB to RS-485 converter:: + + sudo dmesg + [99846.668209] usb 1-1.3: Product: USB Serial + [99846.676313] ch341 1-1.3:1.0: ch341-uart converter detected + [99846.677454] usb 1-1.3: ch341-uart converter now attached to ttyUSB1 + +Run the mbpoll as below:: + + mbpoll -a 10 -b 38400 -t 3 -r 1000 -c 4 /dev/ttyUSB1 -R + + +At PC terminal you will see the mbpoll application receiving the random values +generated by STM32F401RC-RS485 and transmitted over RS-485:: + + mbpoll 1.0-0 - FieldTalk(tm) Modbus(R) Master Simulator + Copyright © 2015-2019 Pascal JEAN, https://github.com/epsilonrt/mbpoll + This program comes with ABSOLUTELY NO WARRANTY. + This is free software, and you are welcome to redistribute it + under certain conditions; type 'mbpoll -w' for details. + + Protocol configuration: Modbus RTU + Slave configuration...: address = [10] + start reference = 1000, count = 4 + Communication.........: /dev/ttyUSB1, 38400-8E1 + t/o 1.00 s, poll rate 1000 ms + Data type.............: 16-bit register, input register table + -- Polling slave 10... Ctrl-C to stop) + [1000]: 58080 (-7456) + [1001]: 0 + [1002]: 0 + [1003]: 0 + -- Polling slave 10... Ctrl-C to stop) + [1000]: 6100 + [1001]: 0 + [1002]: 0 + [1003]: 0 + -- Polling slave 10... Ctrl-C to stop) + [1000]: 51010 (-14526) + [1001]: 0 + [1002]: 0 + [1003]: 0 + -- Polling slave 10... Ctrl-C to stop) + [1000]: 12528 + [1001]: 0 + [1002]: 0 + [1003]: 0 + +modbus_master +------------- + +Configures the NuttShell (nsh) and enables modbus in master mode. This +configuration enables a serial console on USART6. The RS-485 is connected +to USART2. Follow below precedure to use modbusmaster test aplication, you will +need a USB to RS-485 converter to connect the board to a PC via RS-485. + +PC Configuration: + +Download and install diagslave aplication from https://www.modbusdriver.com/diagslave.html. + +Check which TTY USB port is being used by you USB to RS-485 converter:: + + sudo dmesg + [99846.668209] usb 1-1.3: Product: USB Serial + [99846.676313] ch341 1-1.3:1.0: ch341-uart converter detected + [99846.677454] usb 1-1.3: ch341-uart converter now attached to ttyUSB1 + +Run the diagslave as below:: + + sudo diagslave -a 10 -b 38400 /dev/ttyUSB1 + +At PC terminal you will see the diagslave application listening to address 10, +notice that this address is configurable via MODBUSMASTER_SLAVEADDR:: + + diagslave 3.4 - FieldTalk(tm) Modbus(R) Diagnostic Slave Simulator + Copyright (c) 2002-2021 proconX Pty Ltd + Visit https://www.modbusdriver.com for Modbus libraries and tools. + + Protocol configuration: Modbus RTU, frame tolerance = 0ms + Slave configuration: address = 10, master activity t/o = 3.00s + Serial port configuration: /dev/ttyUSB1, 38400, 8, 1, even + + Server started up successfully. + Listening to network (Ctrl-C to stop) + Slave 10: readHoldingRegisters from 2, 1 references + ....... + +NuttShell configuration: + +Run modbusmaster application at NSH:: + + NuttShell (NSH) NuttX-12.4.0 + nsh> modbusmaster + Initializing modbus master... + Creating poll thread. + Sending 100 requests to slave 10 + mbmaster_main: Exiting poll thread. + Modbus master statistics: + Requests count: 100 + Responses count: 100 + Errors count: 0 + Deinitializing modbus master... + +The application modbusmaster will send 100 requests, you can check on diagslave:: + + Server started up successfully. + Listening to network (Ctrl-C to stop) + Slave 10: readHoldingRegisters from 2, 1 references + Slave 10: readHoldingRegisters from 2, 1 references + Slave 10: readHoldingRegisters from 2, 1 references + Slave 10: readHoldingRegisters from 2, 1 references + Slave 10: readHoldingRegisters from 2, 1 references + Slave 10: readHoldingRegisters from 2, 1 references + Slave 10: readHoldingRegisters from 2, 1 references + +lm75 +---- + +Configures the NuttShell (nsh) over USB Serial (check usbserial configuration) and enables temperature sensor LM75. +NSH commands:: + + nsh> lm75 -help + Usage: temp [OPTIONS] + [-n count] selects the samples to collect. Default: 1 Current: 100 + [-h] shows this message and exits + nsh> lm75 -n 3 + 30.13 degrees Celsius + 30.13 degrees Celsius + 30.13 degrees Celsius + +adc +--- + +Configures the NuttShell (nsh) over USB Serial (check usbserial configuration) and enables ADC 1 on channels 0 and 4. +NSH commands:: + + nsh> adc -h + Usage: adc [OPTIONS] + + Arguments are "sticky". For example, once the ADC device is + specified, that device will be re-used until it is changed. + + "sticky" OPTIONS include: + [-p devpath] selects the ADC device. Default: /dev/adc0 Current: /dev/adc0 + [-n count] selects the samples to collect. Default: 1 Current: 0 + [-h] shows this message and exits + nsh> adc -n 2 + adc_main: g_adcstate.count: 2 + adc_main: Hardware initialized. Opening the ADC device: /dev/adc0 + Sample: + 1: channel: 0 value: 2684 + Sample: + 1: channel: 4 value: 2682 + +Currently there is a bug that causes the application to always read the same value for channel 0 and 4. If you want to read the value from channel 2, you will need to enable the config "ADC1 Scan Mode". + +dac +--- + +Configures the NuttShell (nsh) over USB Serial (check usbserial configuration) and enables PWM 3 on channel 1. +Use pwm command on NSH to change dutty cycle, frequency and duration, use dac_out_2 to measure the output voltage. +NSH commands:: + + nsh> pwm -h + Usage: pwm [OPTIONS] + + Arguments are "sticky". For example, once the PWM frequency is + specified, that frequency will be re-used until it is changed. + + "sticky" OPTIONS include: + [-p devpath] selects the PWM device. Default: /dev/pwm0 Current: NONE + [-f frequency] selects the pulse frequency. Default: 100 Hz Current: 100 Hz + [-d duty] selects the pulse duty as a percentage. Default: 50 % Current: 50 % + [-t duration] is the duration of the pulse train in seconds. Default: 5 Current: 5 + [-h] shows this message and exits + nsh> pwm -d 50 -t 3 + pwm_main: starting output with frequency: 50 duty: 00007fff + pwm_main: stopping output + +qencoder +-------- + +Configures the NuttShell (nsh) over USB Serial (check usbserial configuration) and enables Timer 3 on channels 1 and +2 to handle Quadrature Encoder. +NSH commands:: + + nsh> qe -help + + Usage: qe [OPTIONS] + + OPTIONS include: + [-p devpath] QE device path + [-n samples] Number of samples + [-t msec] Delay between samples (msec) + [-r] Reset the position to zero + [-h] Shows this message and exits + nsh> qe -p /dev/qe0 -n 5 -t 100 -r + nsh: qe: too many arguments + qe_main: Hardware initialized. Opening the encoder device: /dev/qe0 + qe_main: Resetting the count... + qe_main: Number of samples: 5 + qe_main: 1. 0 + qe_main: 2. 0 + qe_main: 3. 4 + qe_main: 4. 2 + qe_main: 5. 2 + Terminating! + +rndis +----- + +Configures the NuttShell (nsh), enables a serial console on USART6 and enables RNDIS over USB. +NSH commands:: + + nsh> ping -h + + Usage: ping [-c ] [-i ] [-W ] [-s ] + ping -h + + Where: + is either an IPv4 address or the name of the remote host + that is requested the ICMPv4 ECHO reply. + -c determines the number of pings. Default 10. + -i is the default delay between pings (milliseconds). + Default 1000. + -W is the timeout for wait response (milliseconds). + Default 1000. + -s specifies the number of data bytes to be sent. Default 56. + -h shows this text and exits. + + nsh> ping 10.42.0.1 + PING 10.42.0.1 56 bytes of data + 56 bytes from 10.42.0.1: icmp_seq=0 time=0.0 ms + 56 bytes from 10.42.0.1: icmp_seq=1 time=0.0 ms + ... + 10 packets transmitted, 10 received, 0% packet loss, time 10100 ms + rtt min/avg/max/mdev = 0.000/0.000/0.000/0.000 ms + +usbmsc +------ + +Configures the NuttShell (nsh), enables a serial console on USART6 and enables USB Mass Storage. +NSH commands:: + + nsh> msconn + mcsonn_main: Creating block drivers + mcsonn_main: Configuring with NLUNS=1 + mcsonn_main: handle=0x20004c10 + mcsonn_main: Bind LUN=0 to /dev/mmcsd0 + mcsonn_main: Connected + + nsh> msdis + +hcs04 +----- + +Configures the NuttShell (nsh) over USB Serial (check usbserial configuration) and enables ultrasonic sensor HC-SR04:: + + nsh> cat /dev/dist0 + 6241 --> value + 6227 + 6241 + 6255 + +You can convert the value using following:: + + Convert to cm: value/58 + Convert to inches: value/148 + +ssd1309 +------- + +This config is used to enable support to the transparent OLED display powered by SSD1309. +The resolution of this display is 128x64 (although the effective view is 128x56). + +You can wire the display to your board this way: + +======= ===== +OLED PINS +======= ===== +CS PB7 +DC PB8 +RESET PB6 +SDA PA7 +SCK PA5 +======= ===== + +The board profile configures the NSH over USB and you can use the fb command to test:: + + NuttShell (NSH) NuttX-12.5.1 + nsh> fb + VideoInfo: + fmt: 0 + xres: 128 + yres: 64 + nplanes: 1 + PlaneInfo (plane 0): + fbmem: 0x200034f8 + fblen: 1024 + stride: 16 + display: 0 + bpp: 1 + Mapped FB: 0x200034f8 + 0: ( 0, 0) (128, 64) + 1: ( 11, 5) (106, 54) + 2: ( 22, 10) ( 84, 44) + 3: ( 33, 15) ( 62, 34) + 4: ( 44, 20) ( 40, 24) + 5: ( 55, 25) ( 18, 14) + Test finished + nsh> diff --git a/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst b/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst index c9ad293b7efc1..7a2c3d5ac7c18 100644 --- a/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst +++ b/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst @@ -49,8 +49,10 @@ Expansion connector 2 features. - 6 PWM Channels - 10 ADCs -LEDs -==== +Board documentation: https://wittetech.com/ + +BOARD-LEDs +========== The LINUM-STM32H753BI has 3 software controllable LEDs. @@ -115,25 +117,26 @@ The LINUM-STM32H753BI board has two on-board RS-485 transceiver connected to USA DE PG12 ====== ===== -SDCARD +SDMMC ====== The LINUM-STM32H753BI has one SDCard slot connected as below: ========== ===== - SDMMC1 PINS + SDMMC1 PINS ========== ===== - SDMMC_D0 PC8 - SDMMC_D1 PC9 - SDMMC_D2 PC10 - SDMMC_D3 PC11 - SDMMC_DK PC12 + SDMMC_D0 PC8 + SDMMC_D1 PC9 + SDMMC_D2 PC10 + SDMMC_D3 PC11 + SDMMC_DK PC12 ========== ===== =============== ===== GPIO PINS =============== ===== SDCARD_DETECTED PG7 + SDCARD_PWR_EN PD7 =============== ===== ETHERNET @@ -183,14 +186,15 @@ USB The LINUM-STM32H753BI has one usb port. - ======= ===== - USB PINS - ======= ===== - USB_N PA11 - USB_P PA12 - USB_EN PI12 - USB_FLT PI13 - ======= ===== + ========= ===== + USB PINS + ========= ===== + USB_VBUS PA9 + USB_N PA11 + USB_P PA12 + USB_EN PI12 + USB_FLT PI13 + ========= ===== QUADSPI ============== @@ -223,7 +227,7 @@ The LINUM-STM32H753BI connects the EEPROM memory and the touchscreen sensor to I EEPROM MEMORY -------------- -EEPROM memory used is the 24LC256 with 256Kb. +EEPROM memory used is the 24LC256 with 256Kb with the control bytes value 0x54. TOUCHSCREEN SENSOR ------------------ @@ -299,42 +303,37 @@ LCD ======= The LINUM-STM32H753BI use the LTDC to support one LCD with RGB connection. - =========== ===== - LTDC PINS - =========== ===== - LTDC_B0 PF0 - LTDC_B1 PJ13 - LTDC_B2 PJ14 - LTDC_B3 PJ15 - LTDC_B4 PK3 - LTDC_B5 PK4 - LTDC_B6 PK5 - LTDC_B7 PK6 - LTDC_CLK PI14 - LTDC_DE PK7 - LTDC_G0 PJ7 - LTDC_G1 PJ8 - LTDC_G2 PJ9 - LTDC_G3 PJ10 - LTDC_G4 PJ11 - LTDC_G5 PK0 - LTDC_G6 PK1 - LTDC_G7 PK2 - LTDC_HSYNC PI10 - LTDC_R0 PI15 - LTDC_R1 PJ0 - LTDC_R2 PJ1 - LTDC_R3 PJ2 - LTDC_R4 PJ3 - LTDC_R5 PJ4 - LTDC_R6 PJ5 - LTDC_R7 PJ6 - LTDC_VSYNC PI9 - =========== ===== - ============= ===== - PWM PINS + LTDC PINS ============= ===== + LTDC_B0 PF0 + LTDC_B1 PJ13 + LTDC_B2 PJ14 + LTDC_B3 PJ15 + LTDC_B4 PK3 + LTDC_B5 PK4 + LTDC_B6 PK5 + LTDC_B7 PK6 + LTDC_CLK PI14 + LTDC_DE PK7 + LTDC_G0 PJ7 + LTDC_G1 PJ8 + LTDC_G2 PJ9 + LTDC_G3 PJ10 + LTDC_G4 PJ11 + LTDC_G5 PK0 + LTDC_G6 PK1 + LTDC_G7 PK2 + LTDC_HSYNC PI10 + LTDC_R0 PI15 + LTDC_R1 PJ0 + LTDC_R2 PJ1 + LTDC_R3 PJ2 + LTDC_R4 PJ3 + LTDC_R5 PJ4 + LTDC_R6 PJ5 + LTDC_R7 PJ6 + LTDC_VSYNC PI9 PWM_BACKLIGHT PH6 ============= ===== @@ -350,15 +349,15 @@ The LINUM-STM32H753BI has one I2S output. I2S2_SDO PI3 ======== ===== -BUZZER +PWM ======= -The LINUM-STM32H753BI has a buzzer without internal oscillator +The LINUM-STM32H753BI has a buzzer without internal oscillator connected to PB7 - ======= ===== - GPIO PINS - ======= ===== - BUZZER PC13 - ======= ===== + ========= ===== + GPIO PINS + ========= ===== + BUZZER PB7 + ========= ===== ============== @@ -379,6 +378,27 @@ nsh Configures the NuttShell (nsh) located at apps/examples/nsh. This configuration enables a serial console on UART1. +usbnsh +------ + +Configures the NuttShell (nsh) located at apps/examples/nsh. This configuration enables a serial console over USB. + +After flasing and reboot your board you should see in your dmesg logs:: + + $ sudo dmesg | tail + [ 9180.937813] usb 3-1.1.2: SerialNumber: 0 + [ 9180.946974] cdc_acm 3-1.1.2:1.0: ttyACM0: USB ACM device + [ 9715.123387] usb 3-1.1.2: USB disconnect, device number 20 + [ 9717.393142] usb 3-1.1.2: new full-speed USB device number 21 using xhci_hcd + [ 9717.494824] usb 3-1.1.2: New USB device found, idVendor=0525, idProduct=a4a7, bcdDevice= 1.01 + [ 9717.494834] usb 3-1.1.2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 + [ 9717.494837] usb 3-1.1.2: Product: CDC/ACM Serial + [ 9717.494840] usb 3-1.1.2: Manufacturer: NuttX + [ 9717.494842] usb 3-1.1.2: SerialNumber: 0 + [ 9717.504192] cdc_acm 3-1.1.2:1.0: ttyACM0: USB ACM device + +You may need to press ENTER 3 times before the NSH show up. + modbus_slave ------------ @@ -393,3 +413,345 @@ can enable the ModBus to respond to queries:: In your pc you will be able to read the ModBus registers using an application like ``mbpoll``:: $ mbpoll -a 10 -b 38400 -t 3 -r 1000 -c 4 /dev/ttyUSB1 -R + +modbus_master +------------- + +Configures the ModBus RTU Master located at apps/examples/modbusmaster. This +configuration enables a RS485 on USART6. + +After configuring the desired pins on menuconfig and wiring the RS485 converter, you +can enable the ModBus Master to create queries for device with address 10:: + + nsh> mbmaster + +In your pc you will be able to create a ModBus Slave with address 10 using an application like ``diagslave``:: + + $ sudo diagslave -a 10 -b 38400 /dev/ttyUSB0 + +sdcard +------ + +Configures the NuttShell (nsh) and enables SD card support. The board has an onboard microSD slot that should be +automatically registered as the block device /dev/mmcsd0 when an SD card is present. + +The SD card can then be mounted by the NSH commands:: + + nsh> mount -t vfat /dev/mmcsd0 /mnt + nsh> mount + nsh> echo "Hello World!!" > /mnt/test_file.txt + nhs> ls /mnt/ + test_file.txt + nsh> cat /mnt/test_file.txt + Hello World!! + +eeprom +------ + +Use **dd** command to write and read data from EEPROM as below::: + + nsh> dd if=/dev/console of=/dev/eeprom bs=1 count=35 + Witte-Tech Linum-STM32H753BI board + nsh> dd if=/dev/eeprom of=/dev/console bs=4 count=35 + Witte-Tech Linum-STM32H753BI board + nsh> + +buzzer +------ + +This example use the timer 4 with channel 2 to generate a PWM output signal on buzzer pin:: + + nsh> ls /dev + /dev: + console + null + pwm0 + rtc0 + ttyS0 + nsh> pwm -d 75 -t 3 + pwm_main: starting output with frequency: 100 duty: 0000bfff + pwm_main: stopping output + nsh> pwm -f 300 -t 3 + pwm_main: starting output with frequency: 300 duty: 0000bfff + pwm_main: stopping output + +leds +------ + +Example to blink the RBG led of board, using this example the board led status support stop to work:: + + # turn on led red + printf \x00000001 > /dev/userleds + + # turn on led green + printf \x00000002 > /dev/userleds + + # turn on led blue + printf \x00000004 > /dev/userleds + + # Run blink leds sample + nsh> leds + leds_main: Starting the led_daemon + leds_main: led_daemon started + + led_daemon (pid# 3): Running + led_daemon: Opening /dev/userleds + led_daemon: Supported LEDs 0x07 + led_daemon: LED set 0x01 + nsh> led_daemon: LED set 0x02 + led_daemon: LED set 0x03 + led_daemon: LED set 0x04 + led_daemon: LED set 0x05 + led_daemon: LED set 0x06 + led_daemon: LED set 0x07 + led_daemon: LED set 0x06 + led_daemon: LED set 0x05 + led_daemon: LED set 0x04 + led_daemon: LED set 0x03 + led_daemon: LED set 0x02 + led_daemon: LED set 0x01 + +zmodem +------ + +This example use the nsh via usb and the SDCard to storage the files exchanged. +By default the zmodem lib use the path /tmp to storage the files. + +Sending files to target:: + + # Mount the SDCard at /tmp + nsh> mount -t vfat /dev/mmcsd0 /tmp + + # Waiting for a new file. + nsh> rz + + # Transmitting a file to target. + my_pc$ sz --zmodem nuttx_logo.txt > /dev/ttyACM0 < /dev/ttyACM0 + + # Check if the file was received + nsh> ls -l /tmp + /tmp: + -rw-rw-rw- 1942 nuttx_logo.txt + +Transmiting a file to PC:: + + # Sending the file nuttx_logo.txt to PC + nsh> sz -x 1 /tmp/nuttx_logo.txt + **B00000000000000 + + # Using zmodem to receive a file from target + my_pc/temp$ rz > /dev/ttyACM0 < /dev/ttyACM0 + Receiving: nuttx_logo.txt + Bytes received: 1942/ 1942 BPS:124544 + + Transfer complete + my_pc/temp$ ls -l + -rw------- 1 nuttx nuttx 1942 abr 6 16:07 nuttx_logo.txt + +If you don't have a SDCard on your board, you can mount the TMPFS at /tmp and transfer files to it, +but you cannot transfer big files because TMPFS could use the free RAM of your board:: + + nsh> mount -t tmpfs /tmp + +nxffs +----- +This example use the flash memory W25Q128JV via qspi with the nxffs file system:: + + NuttShell (NSH) NuttX-12.5.1-RC0 + nsh> ls + /: + dev/ + w25/ + nsh> cd /w25 + nsh> echo "hello world!" > message.txt + nsh> ls + /w25: + message.txt + nsh> cat message.txt + hello world! + +littlefs +-------- +This example use the flash memory W25Q128JV via qspi with the littlefs file system:: + + NuttShell (NSH) NuttX-12.5.1-RC0 + nsh> ls + /: + dev/ + w25/ + nsh> cd /w25 + nsh> mkdir folder1 + nsh> cd folder1 + nsh> echo "hello world!!!!" > message.txt + nsh> cat message.txt + hello world!!!! + nsh> ls + /w25/folder1: + . + .. + message.txt + +rndis +----- +This example use ethernet over usb and show how configure ip and download file with wget command from server. + +After flash the board check if the linux found and recognized the new network driver:: + + $ sudo dmesg | tail + [30260.873245] rndis_host 3-1.3:1.0 enxa0e0deadbeef: unregister 'rndis_host' usb-0000:00:14.0-1.3, RNDIS device + [30265.461419] usb 3-1.3: new full-speed USB device number 34 using xhci_hcd + [30265.563354] usb 3-1.3: New USB device found, idVendor=584e, idProduct=5342, bcdDevice= 0.01 + [30265.563359] usb 3-1.3: New USB device strings: Mfr=1, Product=2, SerialNumber=3 + [30265.563361] usb 3-1.3: Product: RNDIS gadget + [30265.563362] usb 3-1.3: Manufacturer: NuttX + [30265.563363] usb 3-1.3: SerialNumber: 1234 + [30265.572179] rndis_host 3-1.3:1.0: dev can't take 1558 byte packets (max 660), adjusting MTU to 602 + [30265.573517] rndis_host 3-1.3:1.0 eth0: register 'rndis_host' at usb-0000:00:14.0-1.3, RNDIS device, a0:e0:de:ad:be:ef + [30265.584924] rndis_host 3-1.3:1.0 enxa0e0deadbeef: renamed from eth0 + + $ ifconfig + enxa0e0deadbeef: flags=4163 mtu 602 + inet 10.42.0.1 netmask 255.255.255.0 broadcast 10.42.0.255 + ether a0:e0:de:ad:be:ef txqueuelen 1000 (Ethernet) + RX packets 87 bytes 10569 (10.5 KB) + RX errors 0 dropped 0 overruns 0 frame 0 + TX packets 99 bytes 22896 (22.8 KB) + TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 + +**OBS:** In network settings of PC enable "Shared to other computers" + +Configure the IP of target:: + + nsh> ifconfig eth0 10.42.0.2 + nsh> ifconfig + lo Link encap:Local Loopback at RUNNING mtu 1518 + inet addr:127.0.0.1 DRaddr:127.0.0.1 Mask:255.0.0.0 + + eth0 Link encap:Ethernet HWaddr 00:e0:de:ad:be:ef at UP mtu 576 + inet addr:10.42.0.2 DRaddr:10.42.0.1 Mask:255.255.255.0 + + IPv4 TCP UDP ICMP + Received 012a 0000 0126 0000 + Dropped 0004 0000 0000 0000 + IPv4 VHL: 0000 Frg: 0001 + Checksum 0000 0000 0000 ---- + TCP ACK: 0000 SYN: 0000 + RST: 0000 0000 + Type 0000 ---- ---- 0000 + Sent 0000 0000 0000 0000 + Rexmit ---- 0000 ---- ---- + nsh> + +Testing communication with PC using ping command:: + + nsh> ping 10.42.0.1 + PING 10.42.0.1 56 bytes of data + 56 bytes from 10.42.0.1: icmp_seq=0 time=0.0 ms + 56 bytes from 10.42.0.1: icmp_seq=1 time=0.0 ms + 56 bytes from 10.42.0.1: icmp_seq=2 time=0.0 ms + 56 bytes from 10.42.0.1: icmp_seq=3 time=0.0 ms + 56 bytes from 10.42.0.1: icmp_seq=4 time=0.0 ms + 56 bytes from 10.42.0.1: icmp_seq=5 time=0.0 ms + 56 bytes from 10.42.0.1: icmp_seq=6 time=0.0 ms + 56 bytes from 10.42.0.1: icmp_seq=7 time=0.0 ms + 56 bytes from 10.42.0.1: icmp_seq=8 time=0.0 ms + 56 bytes from 10.42.0.1: icmp_seq=9 time=0.0 ms + 10 packets transmitted, 10 received, 0% packet loss, time 10100 ms + rtt min/avg/max/mdev = 0.000/0.000/0.000/0.000 ms + +In your pc you will be able connect to target using telnet and access their shell nsh:: + + $ telnet 10.42.0.2 + Trying 10.42.0.2... + Connected to 10.42.0.2. + Escape character is '^]'. + + NuttShell (NSH) NuttX-12.5.1 + nsh> uname -a + NuttX 12.5.1 c148e8f2af-dirty Apr 28 2024 10:27:50 arm linum-stm32h753bi + nsh> exit + Connection closed by foreign host. + $ + +Testing wget to download file from server:: + + # PC: Creating a http server and sharing local folder. + $ sudo python3 -m http.server 80 -d ./ + + # log of server + Serving HTTP on 0.0.0.0 port 80 (http://0.0.0.0:80/) ... + 10.42.0.2 - - [28/Apr/2024 16:14:39] "GET /nuttx_logo.txt HTTP/1.0" 200 - + + # Using wget on target + nsh> mount -t tmpfs /tmp + nsh> cd /tmp + nsh> pwd + /tmp + nsh> wget http://10.42.0.1/nuttx_logo.txt + nsh> ls + /tmp: + nuttx_logo.txt + +usbmsc-sdcard +------------- +This example uses the USB Mass Storage with SD Card. + +Enable the USB Mass Storage with the command **msconn**:: + + nsh> msconn + mcsonn_main: Creating block drivers + mcsonn_main: handle=0x38003020 + mcsonn_main: Bind LUN=0 to /dev/mmcsd0 + mcsonn_main: Connected + +After that check if your PC recognized the usb driver:: + + $ sudo dmesg | tail + [sudo] password for jaga: + [27219.361934] usbcore: registered new interface driver uas + [27220.378231] scsi 0:0:0:0: Direct-Access NuttX Mass Storage 0101 PQ: 0 ANSI: 2 + [27220.378646] sd 0:0:0:0: Attached scsi generic sg0 type 0 + [27220.379203] sd 0:0:0:0: [sda] 1930240 512-byte logical blocks: (988 MB/943 MiB) + [27220.597414] sd 0:0:0:0: [sda] Write Protect is off + [27220.597419] sd 0:0:0:0: [sda] Mode Sense: 0f 00 00 00 + [27220.817620] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA + [27221.265245] sda: sda1 + [27221.266103] sd 0:0:0:0: [sda] Attached SCSI removable disk + [27228.147377] FAT-fs (sda1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck. + +**OBS:** This example disable the macro CONFIG_STM32H7_SDMMC_IDMA, for more information read the file: arch/arm/stm32h7/stm32_sdmmc.c + +netnsh +------ + +This configuration is focused on network testing using the ethernet periferal:: + + $ nsh> ifconfig + eth0 Link encap:Ethernet HWaddr 00:e0:de:ad:be:ef at UP mtu 1486 + inet addr:192.168.1.6 DRaddr:192.168.1.1 Mask:255.255.255.0 + + IPv4 TCP UDP ICMP + Received 01b9 0025 0194 0000 + Dropped 0000 0000 0000 0000 + IPv4 VHL: 0000 Frg: 0000 + Checksum 0000 0000 0000 ---- + TCP ACK: 0000 SYN: 0000 + RST: 0000 0000 + Type 0000 ---- ---- 0000 + Sent 0028 0025 0003 0000 + Rexmit ---- 0000 ---- ---- + + nsh> ping google.com + PING 142.251.129.110 56 bytes of data + 56 bytes from 142.251.129.110: icmp_seq=0 time=10.0 ms + 56 bytes from 142.251.129.110: icmp_seq=1 time=0.0 ms + 56 bytes from 142.251.129.110: icmp_seq=2 time=0.0 ms + 56 bytes from 142.251.129.110: icmp_seq=3 time=0.0 ms + 56 bytes from 142.251.129.110: icmp_seq=4 time=0.0 ms + 56 bytes from 142.251.129.110: icmp_seq=5 time=0.0 ms + 56 bytes from 142.251.129.110: icmp_seq=6 time=0.0 ms + 56 bytes from 142.251.129.110: icmp_seq=7 time=0.0 ms + 56 bytes from 142.251.129.110: icmp_seq=8 time=0.0 ms + 56 bytes from 142.251.129.110: icmp_seq=9 time=0.0 ms + 10 packets transmitted, 10 received, 0% packet loss, time 10100 ms + rtt min/avg/max/mdev = 0.000/1.000/10.000/3.000 ms \ No newline at end of file diff --git a/Documentation/platforms/arm/stm32h7/boards/openh743i/index.rst b/Documentation/platforms/arm/stm32h7/boards/openh743i/index.rst new file mode 100644 index 0000000000000..7edfe2426896a --- /dev/null +++ b/Documentation/platforms/arm/stm32h7/boards/openh743i/index.rst @@ -0,0 +1,24 @@ +=================== +Waveshare OpenH743I +=================== + +The OpenH743I-C is an STM32 development board with STM32H743IIT6. +It comes with a rich expansion interface to support access to various +peripheral modules. + +.. note:: This board has very poor signal integrity. + +Peripherals +=========== + +SDMMC +----- + +The SDMMC1 interface seems not to work correctly with clock frequencies higher +than 20 MHz. + +USBHS +----- + +The reset pin on the ULPI port must be connected to the PE2 pin of the MCU. +If it's not connected, ULPI interface may not work correctly without power reset. diff --git a/Documentation/platforms/arm/stm32h7/boards/weact-stm32h743/index.rst b/Documentation/platforms/arm/stm32h7/boards/weact-stm32h743/index.rst new file mode 100644 index 0000000000000..363e93d849a84 --- /dev/null +++ b/Documentation/platforms/arm/stm32h7/boards/weact-stm32h743/index.rst @@ -0,0 +1,75 @@ +=============== +weact-stm32h743 +=============== + +This page discusses issues unique to NuttX configurations for the +WeAct STM32H743 board. + +.. figure:: weact-stm32h743.png + :align: center + +Board information +================= + +This board was release by WeAct Studio in 2020 and developed based on +STM32H743VI microcontroller. + +The board features: + - USB-C power supply + - SWD connector + - Crystal for HS 25MHz + - Crystal for RTC 32.768KHz + - 1 user LED + - 1 MicroSD connector supporting 1 or 4-bit bus + - 1 USB 2.0 Host/Device + - 2 SPI Flash + - 1 OLED display + - 1 Camera + +Board documentation: https://github.com/WeActStudio/MiniSTM32H7xx + +BOARD-LED +========= + +The WeAct STM32H743 has 1 software controllable LED. + + ==== ===== + LED PINS + ==== ===== + E3 PE3 + ==== ===== + +UART/USART +========== + +The WeAct STM32H743 used the USART1 for serial debug messages. + +USART1 +------ + + ====== ===== + USART1 PINS + ====== ===== + TX PB14 + RX PB15 + ====== ===== + +============== + +Each weact-stm32h743 configuration is maintained in a sub-directory and +can be selected as follow:: + + tools/configure.sh weact-stm32h743: + + Where is one of the following: + + +Configuration Directories +------------------------- + +nsh +--- + +Configures the NuttShell (nsh) located at apps/examples/nsh. This +configuration enables a serial console on UART1. + diff --git a/Documentation/platforms/arm/stm32h7/boards/weact-stm32h743/weact-stm32h743.png b/Documentation/platforms/arm/stm32h7/boards/weact-stm32h743/weact-stm32h743.png new file mode 100644 index 0000000000000..b112ab45358f5 Binary files /dev/null and b/Documentation/platforms/arm/stm32h7/boards/weact-stm32h743/weact-stm32h743.png differ diff --git a/Documentation/platforms/arm/stm32l4/boards/b-l475e-iot01a/index.rst b/Documentation/platforms/arm/stm32l4/boards/b-l475e-iot01a/index.rst index 57af8097cecff..46246435a6f5e 100644 --- a/Documentation/platforms/arm/stm32l4/boards/b-l475e-iot01a/index.rst +++ b/Documentation/platforms/arm/stm32l4/boards/b-l475e-iot01a/index.rst @@ -13,7 +13,7 @@ Board Features B-L475E-IOT01A Discovery kit key features and specifications: -- MCU: STM32L475 Series MCU based on ARM Cortex-M4 core with 1 MB Flash memory, 128 KB SRAM +- MCU: STM32L475 Series MCU based on ARM Cortex-M4 core with 1 MB Flash memory, 128 KB SRAM - Storage: 64 Mbit (8MB)  Quad-SPI Flash memory (Macronix) - Connectivity: - Bluetooth 4.1 LE module (SPBTLE-RF) @@ -84,7 +84,7 @@ corresponding GPIO.:: These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is selected. In that case, the usage by the board port is defined in include/board.h and src/lpc31_leds.c. The LEDs are used to encode -OS-related events as follows: +OS-related events as follows:: SYMBOL Meaning LED2 LED1 ------------------- ----------------------- -------- -------- @@ -114,7 +114,7 @@ Serial Console Arduino Serial Shield --------------------- -An TLL-to-RS232 Converter shield may be used with UART4: +An TLL-to-RS232 Converter shield may be used with UART4:: UART4: @@ -129,7 +129,7 @@ Virtual COM Port ---------------- The serial interface USART1 is directly available as a virtual COM port -of the PC connected to the ST-LINK/V2-1 USB connector CN7. +of the PC connected to the ST-LINK/V2-1 USB connector CN7. :: USART1: @@ -146,7 +146,7 @@ no parity, 1 stop bit, no flow control. Other Options ------------- -USART2 - Available on CN10 if solder bridges closed. +USART2 - Available on CN10 if solder bridges closed:: -------------- ---------------- --------------------------- STM32L475VGTx Board Signal PMOD / Solder Bridges @@ -155,7 +155,7 @@ USART2 - Available on CN10 if solder bridges closed. USART2_TX PD5 PMOD-UART2_TX CN10 pin2 TX/D1 (SB20) -------------- ---------------- --------------------------- -USART3 - Dedicated to ISM43362-M3G-L44 Serial-to-Wifi Module. +USART3 - Dedicated to ISM43362-M3G-L44 Serial-to-Wifi Module:: -------------- ---------------- ------------------ STM32L475VGTx Board Signal Arduino Connector @@ -389,14 +389,14 @@ NOTES: Test Matrix: The following configurations have been tested successfully (with - CRC disabled): + CRC disabled):: =========== ===== ===== ====== COMPRESSION UDP TCP Telnet =========== ===== ===== ====== - hc06 08/04 08/04 08/05 - hc1 - ipv6 + hc06 08/04 08/04 08/05 + hc1 + ipv6 =========== ===== ===== ====== Other configuration options have not been specifically addressed @@ -470,7 +470,7 @@ configuration and most of the notes there apply here as well. Where is the IP address of the E1 endpoint. - Similarly for the UDP test: + Similarly for the UDP test:: E1: nsh> udpserver & E2: nsh> udpclient & @@ -498,7 +498,7 @@ configuration and most of the notes there apply here as well. will map the all-nodes IPv6 to the Spirit destination address 0xff and the packet will be broadcast to all Spirit nodes. - Here are the procedures for using the test + Here are the procedures for using the test:: C: nsh> ifup wpan0 <-- Brings up the network on the hub diff --git a/Documentation/platforms/arm/tiva/boards/tm4c123g-launchpad/README.txt b/Documentation/platforms/arm/tiva/boards/tm4c123g-launchpad/README.txt index 624342a61eb85..080e398793445 100644 --- a/Documentation/platforms/arm/tiva/boards/tm4c123g-launchpad/README.txt +++ b/Documentation/platforms/arm/tiva/boards/tm4c123g-launchpad/README.txt @@ -231,7 +231,7 @@ Using OpenOCD and GDB with an FT2232 JTAG emulator Building OpenOCD under Cygwin: - Refer to boards/arm/lpc17xx_40xx/olimex-lpc1766stk/README.txt + Refer to Documentation/platforms/arm/lpc17xx/boards/olimex-lpc1766stk/README.txt Installing OpenOCD in Linux: diff --git a/Documentation/platforms/arm/tiva/boards/tm4c129e-launchpad/README.txt b/Documentation/platforms/arm/tiva/boards/tm4c129e-launchpad/README.txt index 892d1b8685e49..3a5b7bd5a7660 100644 --- a/Documentation/platforms/arm/tiva/boards/tm4c129e-launchpad/README.txt +++ b/Documentation/platforms/arm/tiva/boards/tm4c129e-launchpad/README.txt @@ -33,8 +33,8 @@ EK-TM4C1294XL and DK-TM4C129X from the DK-T4C129X. Refer to the following README files for additional information that may be relevant to this board as well: - boards/arm/tiva/tm4c1294-launchpad/README.txt - boards/arm/tiva/dk-tm4c129x/README.txt + Documentation/platforms/arm/tiva/boards/tm4c1294-launchpad/README.txt + Documentation/platforms/arm/tiva/boards/dk-tm4c129x/README.txt Status ====== diff --git a/Documentation/platforms/arm/tiva/index.rst b/Documentation/platforms/arm/tiva/index.rst index 7617ec3decdcd..9bc46a63dd4e7 100644 --- a/Documentation/platforms/arm/tiva/index.rst +++ b/Documentation/platforms/arm/tiva/index.rst @@ -63,7 +63,7 @@ Header file support was contributed by Tiago Maluta for this part. Jose Pablo Rojas V. is used those header file changes to port NuttX to the TI/Stellaris EKK-LM3S9B96. That port was available in the NuttX-6.20 release. Refer to the NuttX board -`README `__ +`README `__ file for further information. TI/SimpleLink CC13x0 @@ -115,7 +115,7 @@ LaunchPad `(EK-TM4C1294XL) `__. NuttX-7.25. Refer to the EK-TM4C1294XL board -`README `__ +`README `__ file for more detailed information about this port. TI/Tiva TM4C129E @@ -133,7 +133,7 @@ LaunchPad `(EK-TM4C129EXL) `__. example in the NuttX apps repository. Refer to the EK-TM4C129EXL board -`README `__ +`README `__ file for more detailed information about this port. TI/Tiva TM4C129X @@ -154,13 +154,13 @@ Development Kit `(DK-TM4C129X) `__. (:ref:`NSH `). Both are networked enabled: One configured to support IPv4 and one configured to supported IPv6. Instructions are included in the board - `README `__ + `README `__ file for configuring both IPv4 and IPv6 simultaneously. - Tiva PWM and Quadrature Encoder drivers were contributed to NuttX in 7.18 by Young. Refer to the DK-TM4C129X board -`README `__ +`README `__ file for more detailed information about this port. TI/SimpleLink CC13x2 diff --git a/Documentation/platforms/arm64/imx9/boards/imx93-evk/README.txt b/Documentation/platforms/arm64/imx9/boards/imx93-evk/README.txt new file mode 100644 index 0000000000000..03e23579e4451 --- /dev/null +++ b/Documentation/platforms/arm64/imx9/boards/imx93-evk/README.txt @@ -0,0 +1,146 @@ +README.txt +========== + +The kit i.MX93 Evaluation Kit has a pre-installed Linux image which contains +u-boot and the i.MX93 reference Linux installation. + +u-boot is required to boot NuttX (for now) as it initializes the hardware for +us, i.e. DDR, clocks, I/O muxes etc. + +========================================== + +How to run nuttx on i.MX93 Evaluation Kit. + +========================================== + +Below is a set of instructions on how to run NuttX on the i.MX93 EVK + +========================================== + +Pre-requisites + +========================================== + +- imx93_ca55.JLinkScript which is a custom file, put it wherever you want + +========================================== + +U-Boot configuration + +========================================== + +Two things need to be configured on u-boot before NuttX can be loaded: + +- u-boot data cache must be turned off +- u-boot must stop to the u-boot console, i.e. the Linux payload must not be loaded + +Manual option: + +1. Disable u-boot autostart (needs to be done only once): + + Hit any key to stop autoboot: 0 + u-boot=> setenv bootdelay -1 + u-boot=> saveenv + Saving Environment to MMC... Writing to MMC(0)... OK + u-boot=> reset + +2. On every boot, the data cache must be disabled for options 2 and 3 to work + + u-boot=> dcache off + +Automated option: + +1. Replace the default bootcmd to disable dcache automatically: + + u-boot=> setenv bootdelay 0 + u-boot=> setenv bootcmd dcache off + u-boot=> saveenv + Saving Environment to MMC... Writing to MMC(0)... OK + u-boot=> reset + +To restore the default bootcmd which starts Linux automatically: + + u-boot=> setenv bootcmd run distro_bootcmd;run bsp_bootcmd + u-boot=> saveenv + Saving Environment to MMC... Writing to MMC(0)... OK + u-boot=> reset + +The default bootcmd is: + +u-boot=> env print bootcmd +bootcmd=run distro_bootcmd;run bsp_bootcmd + +========================================== + +Loading and running the NuttX image + +========================================== + +You have three options: + +1 - Load via u-boot from SD-card +2 - Load via gdb +3 - Load via JLink + +========================================== + +Option 1: load via u-boot from SD-card: + +========================================== + +1. Build nuttx, and move nuttx.bin to SD-card + +2. Load from SD-card and start nuttx payload + + u-boot=> dcache off; fatload mmc 1 0x80000000 nuttx.bin; go 0x80000000 + +========================================== + +Option 2: start via gdb: + +========================================== + +1. Start JLinkGDBServer + + JLinkGDBServer -device CORTEX-A55 -JLinkScriptFile /imx93_ca55.JLinkScript + +2. Start gdb + + $ aarch64-none-elf-gdb + + 2.1 Attach and load nuttx + + (gdb) target remote localhost:2331 + (gdb) set mem inaccessible-by-default off + (gdb) load /nuttx + (gdb) monitor go + +========================================== + +Option 3: load with JLink: + +========================================== + +1. Start JLink + + $ JLinkExe -device CORTEX-A55 -if JTAG -jtagconf -1,-1 -speed 4000 -JLinkScriptFile /imx93_ca55.JLinkScript + + 1.1 Add -AutoConnect 1 to connect automatically + + $ JLinkExe -device CORTEX-A55 -if JTAG -jtagconf -1,-1 -speed 4000 -JLinkScriptFile /imx93_ca55.JLinkScript -AutoConnect 1 + +2. Connect JLink + + 2.1 Connect to the debugger + + Type "connect" to establish a target connection, '?' for help + J-Link>connect + + You should now have a JLink prompt. + + Cortex-A55 identified. + J-Link> + +3. Load nuttx. Note that JLink expects the .elf extension, the default build output of nuttx is just "nuttx" without the extension, so it must be added to the file... + + J-Link>LoadFile /nuttx.elf diff --git a/Documentation/platforms/arm64/imx9/boards/imx93-evk/index.rst b/Documentation/platforms/arm64/imx9/boards/imx93-evk/index.rst new file mode 100644 index 0000000000000..97ed448898f19 --- /dev/null +++ b/Documentation/platforms/arm64/imx9/boards/imx93-evk/index.rst @@ -0,0 +1,6 @@ +========== +imx93-evk +========== + +.. include:: README.txt + :literal: diff --git a/Documentation/platforms/arm64/imx9/index.rst b/Documentation/platforms/arm64/imx9/index.rst new file mode 100644 index 0000000000000..4b1e5b7412014 --- /dev/null +++ b/Documentation/platforms/arm64/imx9/index.rst @@ -0,0 +1,12 @@ +========= +NXP i.MX9 +========= + +Supported Boards +================ + +.. toctree:: + :glob: + :maxdepth: 1 + + boards/*/* diff --git a/Documentation/platforms/avr/at32uc3/boards/avr32dev1/index.rst b/Documentation/platforms/avr/at32uc3/boards/avr32dev1/index.rst index c6856400f76e1..eb01af1b2a65c 100644 --- a/Documentation/platforms/avr/at32uc3/boards/avr32dev1/index.rst +++ b/Documentation/platforms/avr/at32uc3/boards/avr32dev1/index.rst @@ -2,9 +2,40 @@ avr32dev1 ========= -This is a port of NuttX to the Atmel AVR32DEV1 board. That board is -based on the Atmel AT32UC3B0256 MCU and uses a specially patched -version of the GNU toolchain: The patches provide support for the +This is a port of NuttX to the Atmel AVR32DEV1 board and compatible +with MCUZone UC3B-CPU board depicted here: + +.. figure:: mcuzone_uc3b-cpu.png + :align: center + +This board is based on the Atmel AT32UC3B0256 MCU and uses a specially +patched version of the GNU toolchain: The patches provide support for the AVR32 family. That patched GNU toolchain is available only from the -Atmel website. STATUS: This port is functional but very basic. There +Atmel website. + +STATUS: This port is functional but very basic. There are configurations for NSH and the OS test. + +Features +======== + + - AVR32 AT32UC3B0256 microcontroller + - mini-USB Connector + - Power LED (LED1) + - MCU controllable LEDs: LED2 and LED3 + - S1/RESET and S2 buttons (S2 accessible to user) + - 12MHz (main clock) and 32KHz for RTC + +Serial Console +============== + +The board uses by default the USART1 as serial console. +The pins PB2 (TXD) and PA24 (RXD) are used for USART1. + +This way you need to connect a USB/Serial adapter to +get access to the NuttShell. Connect the TXD from your +USB/Serial to the RXD of the board, and the RXD from +USB/Serial to the TXD of the board. + +There is another detail about the baudrate, you need to +use 57600 8n1. diff --git a/Documentation/platforms/avr/at32uc3/boards/avr32dev1/mcuzone_uc3b-cpu.png b/Documentation/platforms/avr/at32uc3/boards/avr32dev1/mcuzone_uc3b-cpu.png new file mode 100644 index 0000000000000..c259b30361015 Binary files /dev/null and b/Documentation/platforms/avr/at32uc3/boards/avr32dev1/mcuzone_uc3b-cpu.png differ diff --git a/Documentation/platforms/avr/at32uc3/index.rst b/Documentation/platforms/avr/at32uc3/index.rst index d5fd061275e96..f633f9ef50347 100644 --- a/Documentation/platforms/avr/at32uc3/index.rst +++ b/Documentation/platforms/avr/at32uc3/index.rst @@ -28,7 +28,7 @@ The basic, port was be released in NuttX-5.13. A complete port will include drivers for additional AVR32 UC3 devices -- like SPI and USB --- and will be available in a later release, time permitting. Refer to the NuttX board -`README `__ +`README `__ file for further information. Supported Boards diff --git a/Documentation/platforms/mips/pic32mz/index.rst b/Documentation/platforms/mips/pic32mz/index.rst index 959434c40e366..d6fcd8a05d20d 100644 --- a/Documentation/platforms/mips/pic32mz/index.rst +++ b/Documentation/platforms/mips/pic32mz/index.rst @@ -36,7 +36,7 @@ timers. **NuttX-9.0**. Cache operations were implemented. Refer to the NuttX board -`README `__ +`README `__ file for further information. **Development Environment:** Same as for the PIC32MZ. diff --git a/Documentation/platforms/renesas/m16c/boards/skp16c26/README.txt b/Documentation/platforms/renesas/m16c/boards/skp16c26/README.txt index 99cbb7fd149c1..b8eaf5df22a31 100644 --- a/Documentation/platforms/renesas/m16c/boards/skp16c26/README.txt +++ b/Documentation/platforms/renesas/m16c/boards/skp16c26/README.txt @@ -1,4 +1,4 @@ -boards/renesas/m16c/skp16c26/README.txt +Documentation/platforms/renesas/m16c/boards/skp16c26/README.txt ^^^^^^^^^^^^^^^^^^^^^^^^^^^ 1. The buildroot package can be used to build an M16C toolchain. The toolchain diff --git a/Documentation/platforms/renesas/m16c/index.rst b/Documentation/platforms/renesas/m16c/index.rst index 3ca099c79a9f1..b01bee71bec9b 100644 --- a/Documentation/platforms/renesas/m16c/index.rst +++ b/Documentation/platforms/renesas/m16c/index.rst @@ -14,7 +14,7 @@ Where the reference line is: No workaround is known at this time. This is a show stopper for M16C. Refer to the NuttX board -`README `__ +`README `__ file for further information. Supported Boards diff --git a/Documentation/platforms/renesas/rx65n/boards/rx65n-grrose/ROMFS.txt b/Documentation/platforms/renesas/rx65n/boards/rx65n-grrose/ROMFS.txt index 955b191ba4aed..69d21ea9442bd 100644 --- a/Documentation/platforms/renesas/rx65n/boards/rx65n-grrose/ROMFS.txt +++ b/Documentation/platforms/renesas/rx65n/boards/rx65n-grrose/ROMFS.txt @@ -5,7 +5,7 @@ README -------- This directory contains logic to support a custom ROMFS system-init script and start-up script. These scripts are used by by the NSH when it starts - provided that CONFIG_NSH_ARCHROMFS=y. These scripts provide a ROMFS volume + provided that CONFIG_ETC_ROMFS=y. These scripts provide a ROMFS volume that will be mounted at /etc and will look like this at run-time: NuttShell (NSH) NuttX-8.2 diff --git a/Documentation/platforms/renesas/rx65n/boards/rx65n-rsk2mb/ROMFS.txt b/Documentation/platforms/renesas/rx65n/boards/rx65n-rsk2mb/ROMFS.txt index f4efccb0b206f..5a95e8f404b19 100644 --- a/Documentation/platforms/renesas/rx65n/boards/rx65n-rsk2mb/ROMFS.txt +++ b/Documentation/platforms/renesas/rx65n/boards/rx65n-rsk2mb/ROMFS.txt @@ -5,7 +5,7 @@ README -------- This directory contains logic to support a custom ROMFS system-init script and start-up script. These scripts are used by by the NSH when it starts - provided that CONFIG_NSH_ARCHROMFS=y. These scripts provide a ROMFS volume + provided that CONFIG_ETC_ROMFS=y. These scripts provide a ROMFS volume that will be mounted at /etc and will look like this at run-time: NuttShell (NSH) NuttX-8.2 diff --git a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit-rust-1/README.txt b/Documentation/platforms/risc-v/esp32c3-legacy/boards/esp32c3-devkit-rust-1/README.txt similarity index 100% rename from Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit-rust-1/README.txt rename to Documentation/platforms/risc-v/esp32c3-legacy/boards/esp32c3-devkit-rust-1/README.txt diff --git a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit-rust-1/index.rst b/Documentation/platforms/risc-v/esp32c3-legacy/boards/esp32c3-devkit-rust-1/index.rst similarity index 100% rename from Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit-rust-1/index.rst rename to Documentation/platforms/risc-v/esp32c3-legacy/boards/esp32c3-devkit-rust-1/index.rst diff --git a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/ESP32-C3-DevKitC-02-v1.1.png b/Documentation/platforms/risc-v/esp32c3-legacy/boards/esp32c3-devkit/ESP32-C3-DevKitC-02-v1.1.png similarity index 100% rename from Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/ESP32-C3-DevKitC-02-v1.1.png rename to Documentation/platforms/risc-v/esp32c3-legacy/boards/esp32c3-devkit/ESP32-C3-DevKitC-02-v1.1.png diff --git a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/ESP32-C3-DevKitM-1-v1.0.png b/Documentation/platforms/risc-v/esp32c3-legacy/boards/esp32c3-devkit/ESP32-C3-DevKitM-1-v1.0.png similarity index 100% rename from Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/ESP32-C3-DevKitM-1-v1.0.png rename to Documentation/platforms/risc-v/esp32c3-legacy/boards/esp32c3-devkit/ESP32-C3-DevKitM-1-v1.0.png diff --git a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/ROMFS.txt b/Documentation/platforms/risc-v/esp32c3-legacy/boards/esp32c3-devkit/ROMFS.txt similarity index 98% rename from Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/ROMFS.txt rename to Documentation/platforms/risc-v/esp32c3-legacy/boards/esp32c3-devkit/ROMFS.txt index c1db6083685d4..3c5c42de901d9 100644 --- a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/ROMFS.txt +++ b/Documentation/platforms/risc-v/esp32c3-legacy/boards/esp32c3-devkit/ROMFS.txt @@ -5,7 +5,7 @@ README -------- This directory contains logic to support a custom ROMFS system-init script and start-up script. These scripts are used by by the NSH when it starts - provided that CONFIG_NSH_ARCHROMFS=y. These scripts provide a ROMFS volume + provided that CONFIG_ETC_ROMFS=y. These scripts provide a ROMFS volume that will be mounted at /etc and will look like this at run-time: NuttShell (NSH) NuttX-10.1.0-RC1 diff --git a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/index.rst b/Documentation/platforms/risc-v/esp32c3-legacy/boards/esp32c3-devkit/index.rst similarity index 100% rename from Documentation/platforms/risc-v/esp32c3/boards/esp32c3-devkit/index.rst rename to Documentation/platforms/risc-v/esp32c3-legacy/boards/esp32c3-devkit/index.rst diff --git a/Documentation/platforms/risc-v/esp32c3-legacy/index.rst b/Documentation/platforms/risc-v/esp32c3-legacy/index.rst new file mode 100644 index 0000000000000..4fdee90272e43 --- /dev/null +++ b/Documentation/platforms/risc-v/esp32c3-legacy/index.rst @@ -0,0 +1,287 @@ +.. note:: + A new approach is being adopted for this chip and this implementation will be deprecated when the same support level is achieved. + For the new approach please check :ref:`here`. + +=========================== +Espressif ESP32-C3 (Legacy) +=========================== + +The ESP32-C3 is an ultra-low-power and highly integrated SoC with a RISC-V +core and supports 2.4 GHz Wi-Fi and Bluetooth Low Energy. + +* Address Space + - 800 KB of internal memory address space accessed from the instruction bus + - 560 KB of internal memory address space accessed from the data bus + - 1016 KB of peripheral address space + - 8 MB of external memory virtual address space accessed from the instruction bus + - 8 MB of external memory virtual address space accessed from the data bus + - 480 KB of internal DMA address space +* Internal Memory + - 384 KB ROM + - 400 KB SRAM (16 KB can be configured as Cache) + - 8 KB of SRAM in RTC +* External Memory + - Up to 16 MB of external flash +* Peripherals + - 35 peripherals +* GDMA + - 7 modules are capable of DMA operations. + +ESP32-C3 Toolchain +================== + +A generic RISC-V toolchain can be used to build ESP32-C3 projects. It's recommended to use the same +toolchain used by NuttX CI. Please refer to the Docker +`container `_ and +check for the current compiler version being used. For instance: + +.. code-block:: + + ############################################################################### + # Build image for tool required by RISCV builds + ############################################################################### + FROM nuttx-toolchain-base AS nuttx-toolchain-riscv + # Download the latest RISCV GCC toolchain prebuilt by xPack + RUN mkdir riscv-none-elf-gcc && \ + curl -s -L "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v12.3.0-2/xpack-riscv-none-elf-gcc-12.3.0-2-linux-x64.tar.gz" \ + | tar -C riscv-none-elf-gcc --strip-components 1 -xz + +It uses the xPack's prebuilt toolchain based on GCC 12.3.0. + +Installing +---------- + +First, create a directory to hold the toolchain: + +.. code-block:: console + + $ mkdir -p /path/to/your/toolchain/riscv-none-elf-gcc + +Download and extract toolchain: + +.. code-block:: console + + $ curl -s -L "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v12.3.0-2/xpack-riscv-none-elf-gcc-12.3.0-2-linux-x64.tar.gz" \ + | tar -C /path/to/your/toolchain/riscv-none-elf-gcc --strip-components 1 -xz + +Add the toolchain to your `PATH`: + +.. code-block:: console + + $ echo "export PATH=/path/to/your/toolchain/riscv-none-elf-gcc/bin:$PATH" >> ~/.bashrc + +You can edit your shell's rc files if you don't use bash. + +Second stage bootloader and partition table +=========================================== + +The NuttX port for now relies on IDF's second stage bootloader to carry on some hardware +initializations. The binaries for the bootloader and the partition table can be found in +this repository: https://github.com/espressif/esp-nuttx-bootloader +That repository contains a dummy IDF project that's used to build the bootloader and +partition table, these are then presented as Github assets and can be downloaded +from: https://github.com/espressif/esp-nuttx-bootloader/releases +Download ``bootloader-esp32c3.bin`` and ``partition-table-esp32c3.bin`` and place them +in a folder, the path to this folder will be used later to program them. This +can be: ``../esp-bins`` + +Building and flashing +===================== + +First make sure that ``esptool.py`` is installed. This tool is used to convert +the ELF to a compatible ESP32 image and to flash the image into the board. +It can be installed with: ``pip install esptool``. + +Configure the NuttX project: ``./tools/configure.sh esp32c3-devkit:nsh`` +Run ``make`` to build the project. Note that the conversion mentioned above is +included in the build process. +The ``esptool.py`` command to flash all the binaries is:: + + esptool.py --chip esp32c3 --port /dev/ttyUSBXX --baud 921600 write_flash 0x0 bootloader.bin 0x8000 partition-table.bin 0x10000 nuttx.bin + +However, this is also included in the build process and we can build and flash with:: + + make flash ESPTOOL_PORT= ESPTOOL_BINDIR=../esp-bins + +Where ```` is typically ``/dev/ttyUSB0`` or similar and ``../esp-bins`` is +the path to the folder containing the bootloader and the partition table +for the ESP32-C3 as explained above. +Note that this step is required only one time. Once the bootloader and partition +table are flashed, we don't need to flash them again. So subsequent builds +would just require: ``make flash ESPTOOL_PORT=/dev/ttyUSBXX`` + +Debugging with OpenOCD +====================== + +Download and build OpenOCD from Espressif, that can be found in +https://github.com/espressif/openocd-esp32 + +If you have an ESP32-C3 ECO3, no external JTAG is required to debug, the ESP32-C3 +integrates a USB-to-JTAG adapter. + +OpenOCD can then be used:: + + openocd -c 'set ESP_RTOS none' -f board/esp32c3-builtin.cfg + +For versions prior to ESP32-C3 ECO3, an external JTAG adapter is needed. +It can be connected as follows:: + + TMS -> GPIO4 + TDI -> GPIO5 + TCK -> GPIO6 + TDO -> GPIO7 + +Furthermore, an efuse needs to be burnt to be able to debug:: + + espefuse.py -p burn_efuse DIS_USB_JTAG + +OpenOCD can then be used:: + + openocd -c 'set ESP_RTOS none' -f board/esp32c3-ftdi.cfg + +Peripheral Support +================== + +The following list indicates the state of peripherals' support in NuttX: + +=========== ======= ===== +Peripheral Support NOTES +=========== ======= ===== +ADC Yes +AES Yes +Bluetooth Yes +CDC Console Yes Rev.3 +DMA Yes +eFuse Yes +GPIO Yes +I2C Yes +LED_PWM Yes +RNG Yes +RSA Yes +RTC Yes +SHA Yes +SPI Yes +SPIFLASH Yes +Timers Yes +Touch Yes +UART Yes +Watchdog Yes +Wifi Yes +=========== ======= ===== + +Secure Boot and Flash Encryption +================================ + +Secure Boot +----------- + +Secure Boot protects a device from running any unauthorized (i.e., unsigned) code by checking that +each piece of software that is being booted is signed. On an ESP32-C3, these pieces of software include +the second stage bootloader and each application binary. Note that the first stage bootloader does not +require signing as it is ROM code thus cannot be changed. This is achieved using specific hardware in +conjunction with MCUboot (read more about MCUboot `here `__). + +The Secure Boot process on the ESP32-C3 involves the following steps performed: + +1. The first stage bootloader verifies the second stage bootloader's RSA-PSS signature. If the verification is successful, + the first stage bootloader loads and executes the second stage bootloader. + +2. When the second stage bootloader loads a particular application image, the application's signature (RSA, ECDSA or ED25519) is verified + by MCUboot. + If the verification is successful, the application image is executed. + +.. warning:: Once enabled, Secure Boot will not boot a modified bootloader. The bootloader will only boot an + application firmware image if it has a verified digital signature. There are implications for reflashing + updated images once Secure Boot is enabled. You can find more information about the ESP32-C3's Secure boot + `here `__. + +.. note:: As the bootloader image is built on top of the Hardware Abstraction Layer component + of `ESP-IDF `_, the + `API port by Espressif `_ will be used + by MCUboot rather than the original NuttX port. + +Flash Encryption +---------------- + +Flash encryption is intended for encrypting the contents of the ESP32-C3's off-chip flash memory. Once this feature is enabled, +firmware is flashed as plaintext, and then the data is encrypted in place on the first boot. As a result, physical readout +of flash will not be sufficient to recover most flash contents. + +.. warning:: After enabling Flash Encryption, an encryption key is generated internally by the device and + cannot be accessed by the user for re-encrypting data and re-flashing the system, hence it will be permanently encrypted. + Re-flashing an encrypted system is complicated and not always possible. You can find more information about the ESP32-C3's Flash Encryption + `here `__. + +Prerequisites +------------- + +First of all, we need to install ``imgtool`` (a MCUboot utility application to manipulate binary +images) and ``esptool`` (the ESP32-C3 toolkit):: + + $ pip install imgtool esptool + +We also need to make sure that the python modules are added to ``PATH``:: + + $ echo "PATH=$PATH:/home/$USER/.local/bin" >> ~/.bashrc + +Now, we will create a folder to store the generated keys (such as ``~/signing_keys``):: + + $ mkdir ~/signing_keys && cd ~/signing_keys + +With all set up, we can now generate keys to sign the bootloader and application binary images, +respectively, of the compiled project:: + + $ espsecure.py generate_signing_key --version 2 bootloader_signing_key.pem + $ imgtool keygen --key app_signing_key.pem --type rsa-3072 + +.. important:: The contents of the key files must be stored securely and kept secret. + +Enabling Secure Boot and Flash Encryption +----------------------------------------- + +To enable Secure Boot for the current project, go to the project's NuttX directory, execute ``make menuconfig`` and the following steps: + + 1. Enable experimental features in :menuselection:`Build Setup --> Show experimental options`; + + 2. Enable MCUboot in :menuselection:`Application Configuration --> Bootloader Utilities --> MCUboot`; + + 3. Change image type to ``MCUboot-bootable format`` in :menuselection:`System Type --> Application Image Configuration --> Application Image Format`; + + 4. Enable building MCUboot from the source code by selecting ``Build binaries from source``; + in :menuselection:`System Type --> Application Image Configuration --> Source for bootloader binaries`; + + 5. Enable Secure Boot in :menuselection:`System Type --> Application Image Configuration --> Enable hardware Secure Boot in bootloader`; + + 6. If you want to protect the SPI Bus against data sniffing, you can enable Flash Encryption in + :menuselection:`System Type --> Application Image Configuration --> Enable Flash Encryption on boot`. + +Now you can design an update and confirm agent to your application. Check the `MCUboot design guide `_ and the +`MCUboot Espressif port documentation `_ for +more information on how to apply MCUboot. Also check some `notes about the NuttX MCUboot port `_, +the `MCUboot porting guide `_ and some +`examples of MCUboot applied in Nuttx applications `_. + +After you developed an application which implements all desired functions, you need to flash it into the primary image slot +of the device (it will automatically be in the confirmed state, you can learn more about image +confirmation `here `_). +To flash to the primary image slot, select ``Application image primary slot`` in +:menuselection:`System Type --> Application Image Configuration --> Target slot for image flashing` +and compile it using ``make -j ESPSEC_KEYDIR=~/signing_keys``. + +When creating update images, make sure to change :menuselection:`System Type --> Application Image Configuration --> Target slot for image flashing` +to ``Application image secondary slot``. + +.. important:: When deploying your application, make sure to disable UART Download Mode by selecting ``Permanently disabled`` in + :menuselection:`System Type --> Application Image Configuration --> UART ROM download mode` + and change usage mode to ``Release`` in `System Type --> Application Image Configuration --> Enable usage mode`. + **After disabling UART Download Mode you will not be able to flash other images through UART.** + + +Supported Boards +================ + +.. toctree:: + :glob: + :maxdepth: 1 + + boards/*/* diff --git a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/ESP32-C3-DevKitC-02-v1.1.png b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/ESP32-C3-DevKitC-02-v1.1.png new file mode 100644 index 0000000000000..88a89947554ac Binary files /dev/null and b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/ESP32-C3-DevKitC-02-v1.1.png differ diff --git a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/ESP32-C3-DevKitM-1-v1.0.png b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/ESP32-C3-DevKitM-1-v1.0.png new file mode 100644 index 0000000000000..ad0c387cc7341 Binary files /dev/null and b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/ESP32-C3-DevKitM-1-v1.0.png differ diff --git a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/index.rst b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/index.rst new file mode 100644 index 0000000000000..eaf89cac04a7b --- /dev/null +++ b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/index.rst @@ -0,0 +1,263 @@ +================ +ESP32-C3 DevKit +================ + +The ESP32-C3 DevKit is an entry-level development board equipped with either +an ESP32-C3-WROOM-02 or an ESP32-C3-MINI-1. +ESP32-C3-WROOM-02 and ESP32-C3-MINI-1 are SoMs based on the RISC-V ESP32-C3 CPU. + +Most of the I/O pins are broken out to the pin headers on both sides for easy +interfacing. Developers can either connect peripherals with jumper wires or +mount ESP32-C3 DevKit on a breadboard. + +.. list-table:: + :align: center + + * - .. figure:: ESP32-C3-DevKitC-02-v1.1.png + :align: center + + ESP32-C3-DevKitC-02 + + - .. figure:: ESP32-C3-DevKitM-1-v1.0.png + :align: center + + ESP32-C3-DevKitM-1 + +Buttons and LEDs +================ + +Board Buttons +------------- +There are two buttons labeled Boot and RST. The RST button is not available +to software. It pulls the chip enable line that doubles as a reset line. + +The BOOT button is connected to IO9. On reset it is used as a strapping +pin to determine whether the chip boots normally or into the serial +bootloader. After reset, however, the BOOT button can be used for software +input. + +Board LEDs +---------- + +There is one on-board LED that indicates the presence of power. +Another WS2812 LED is connected to GPIO8 and is available for software. + +Configurations +============== + +All of the configurations presented below can be tested by running the following commands:: + + $ ./tools/configure.sh esp32c3-generic: + $ make flash ESPTOOL_PORT=/dev/ttyUSB0 -j + +Where is the name of board configuration you want to use, i.e.: nsh, buttons, wifi... +Then use a serial console terminal like ``picocom`` configured to 115200 8N1. + +coremark +-------- + +This configuration sets the CoreMark benchmark up for running on the maximum +number of cores for this system. It also enables some optimization flags and +disables the NuttShell to get the best possible score. + +.. note:: As the NSH is disabled, the application will start as soon as the + system is turned on. + +gpio +---- + +This is a test for the GPIO driver. It uses GPIO1 and GPIO2 as outputs and +GPIO9 as an interrupt pin. + +At the nsh, we can turn the outputs on and off with the following:: + + nsh> gpio -o 1 /dev/gpio0 + nsh> gpio -o 1 /dev/gpio1 + + nsh> gpio -o 0 /dev/gpio0 + nsh> gpio -o 0 /dev/gpio1 + +We can use the interrupt pin to send a signal when the interrupt fires:: + + nsh> gpio -w 14 /dev/gpio2 + +The pin is configured as a rising edge interrupt, so after issuing the +above command, connect it to 3.3V. + +nsh +--- + +Basic configuration to run the NuttShell (nsh). + +ostest +------ + +This is the NuttX test at ``apps/testing/ostest`` that is run against all new +architecture ports to assure a correct implementation of the OS. + +pwm +--- + +This configuration demonstrates the use of PWM through a LED connected to GPIO2. +To test it, just execute the ``pwm`` application:: + + nsh> pwm + pwm_main: starting output with frequency: 10000 duty: 00008000 + pwm_main: stopping output + +rmt +--- + +This configuration configures the transmitter and the receiver of the +Remote Control Transceiver (RMT) peripheral on the ESP32-C3 using GPIOs 8 +and 2, respectively. The RMT peripheral is better explained +`here `__, +in the ESP-IDF documentation. The minimal data unit in the frame is called the +RMT symbol, which is represented by ``rmt_item32_t`` in the driver: + +.. figure:: rmt_symbol.png + :align: center + +The example ``rmtchar`` can be used to test the RMT peripheral. Connecting +these pins externally to each other will make the transmitter send RMT items +and demonstrates the usage of the RMT peripheral:: + + nsh> rmtchar + +**WS2812 addressable RGB LEDs** + +This same configuration enables the usage of the RMT peripheral and the example +``ws2812`` to drive addressable RGB LEDs:: + + nsh> ws2812 + +Please note that this board contains an on-board WS2812 LED connected to GPIO8 +and, by default, this config configures the RMT transmitter in the same pin. + +rtc +--- + +This configuration demonstrates the use of the RTC driver through alarms. +You can set an alarm, check its progress and receive a notification after it expires:: + + nsh> alarm 10 + alarm_daemon started + alarm_daemon: Running + Opening /dev/rtc0 + Alarm 0 set in 10 seconds + nsh> alarm -r + Opening /dev/rtc0 + Alarm 0 is active with 10 seconds to expiration + nsh> alarm_daemon: alarm 0 received + +spiflash +-------- + +This config tests the external SPI that comes with the ESP32-C3 module connected +through SPI1. + +By default a SmartFS file system is selected. +Once booted you can use the following commands to mount the file system:: + + nsh> mksmartfs /dev/smart0 + nsh> mount -t smartfs /dev/smart0 /mnt + +sta_softap +---------- + +With this configuration you can run these commands to be able +to connect your smartphone or laptop to your board:: + + nsh> ifup wlan1 + nsh> dhcpd_start wlan1 + nsh> wapi psk wlan1 mypasswd 3 + nsh> wapi essid wlan1 nuttxap 1 + +In this case, you are creating the access point ``nuttxapp`` in your board and to +connect to it on your smartphone you will be required to type the password ``mypasswd`` +using WPA2. + +.. tip:: Please refer to :ref:`ESP32 Wi-Fi SoftAP Mode ` + for more information. + +The ``dhcpd_start`` is necessary to let your board to associate an IP to your smartphone. + +timer +----- + +This config test the general use purpose timers. It includes the 4 timers, +adds driver support, registers the timers as devices and includes the timer +example. + +To test it, just run the following:: + + nsh> timer -d /dev/timerx + +Where x in the timer instance. + +twai +---- + +This configuration enables the support for the TWAI (Two-Wire Automotive Interface) driver. +You can test it by connecting TWAI RX and TWAI TX pins which are GPIO0 and GPIO2 by default +to an external transceiver or connecting TWAI RX to TWAI TX pin by enabling +the `CONFIG_CAN_LOOPBACK` option (``Device Drivers -> CAN Driver Support -> CAN loopback mode``) +and running the ``can`` example:: + + nsh> can + nmsgs: 0 + min ID: 1 max ID: 2047 + Bit timing: + Baud: 1000000 + TSEG1: 15 + TSEG2: 4 + SJW: 3 + ID: 1 DLC: 1 + +usbconsole +---------- + +This configuration tests the built-in USB-to-serial converter found in ESP32-C3 (revision 3). +``esptool`` can be used to check the version of the chip and if this feature is +supported. Running ``esptool.py -p chip_id`` should have ``Chip is +ESP32-C3 (revision 3)`` in its output. +When connecting the board a new device should appear, a ``/dev/ttyACMX`` on Linux +or a ``/dev/cu.usbmodemXXX`` om macOS. +This can be used to flash and monitor the device with the usual commands:: + + make download ESPTOOL_PORT=/dev/ttyACM0 + minicom -D /dev/ttyACM0 + +watchdog +-------- + +This configuration tests the watchdog timers. It includes the 2 MWDTS, +adds driver support, registers the WDTs as devices and includes the watchdog +example application. + +To test it, just run the following command:: + + nsh> wdog -i /dev/watchdogX + +Where X is the watchdog instance. + +wifi +---- + +Enables Wi-Fi support. You can define your credentials this way:: + + $ make menuconfig + -> Application Configuration + -> Network Utilities + -> Network initialization (NETUTILS_NETINIT [=y]) + -> WAPI Configuration + +Or if you don't want to keep it saved in the firmware you can do it +at runtime:: + + nsh> wapi psk wlan0 mypasswd 3 + nsh> wapi essid wlan0 myssid 1 + nsh> renew wlan0 + +.. tip:: Please refer to :ref:`ESP32 Wi-Fi Station Mode ` + for more information. diff --git a/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/rmt_symbol.png b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/rmt_symbol.png new file mode 100644 index 0000000000000..7f859d7c98be7 Binary files /dev/null and b/Documentation/platforms/risc-v/esp32c3/boards/esp32c3-generic/rmt_symbol.png differ diff --git a/Documentation/platforms/risc-v/esp32c3/index.rst b/Documentation/platforms/risc-v/esp32c3/index.rst index 18c97ed5cc1f0..c6c870d12d7e8 100644 --- a/Documentation/platforms/risc-v/esp32c3/index.rst +++ b/Documentation/platforms/risc-v/esp32c3/index.rst @@ -1,3 +1,5 @@ +.. _esp32c3: + ================== Espressif ESP32-C3 ================== @@ -33,16 +35,16 @@ check for the current compiler version being used. For instance: .. code-block:: - ############################################################################### - # Build image for tool required by RISCV builds - ############################################################################### - FROM nuttx-toolchain-base AS nuttx-toolchain-riscv - # Download the latest RISCV GCC toolchain prebuilt by xPack - RUN mkdir riscv-none-elf-gcc && \ - curl -s -L "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v12.3.0-2/xpack-riscv-none-elf-gcc-12.3.0-2-linux-x64.tar.gz" \ - | tar -C riscv-none-elf-gcc --strip-components 1 -xz + ############################################################################### + # Build image for tool required by RISCV builds + ############################################################################### + FROM nuttx-toolchain-base AS nuttx-toolchain-riscv + # Download the latest RISCV GCC toolchain prebuilt by xPack + RUN mkdir riscv-none-elf-gcc && \ + curl -s -L "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz" \ + | tar -C riscv-none-elf-gcc --strip-components 1 -xz -It uses the xPack's prebuilt toolchain based on GCC 12.3.0. +It uses the xPack's prebuilt toolchain based on GCC 13.2.0-2. Installing ---------- @@ -51,60 +53,60 @@ First, create a directory to hold the toolchain: .. code-block:: console - $ mkdir -p /path/to/your/toolchain/riscv-none-elf-gcc + $ mkdir -p /path/to/your/toolchain/riscv-none-elf-gcc Download and extract toolchain: .. code-block:: console - $ curl -s -L "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v12.3.0-2/xpack-riscv-none-elf-gcc-12.3.0-2-linux-x64.tar.gz" \ - | tar -C /path/to/your/toolchain/riscv-none-elf-gcc --strip-components 1 -xz + $ curl -s -L "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz" \ + | tar -C /path/to/your/toolchain/riscv-none-elf-gcc --strip-components 1 -xz Add the toolchain to your `PATH`: .. code-block:: console - $ echo "export PATH=/path/to/your/toolchain/riscv-none-elf-gcc/bin:$PATH" >> ~/.bashrc + $ echo "export PATH=/path/to/your/toolchain/riscv-none-elf-gcc/bin:$PATH" >> ~/.bashrc You can edit your shell's rc files if you don't use bash. -Second stage bootloader and partition table -=========================================== - -The NuttX port for now relies on IDF's second stage bootloader to carry on some hardware -initializations. The binaries for the bootloader and the partition table can be found in -this repository: https://github.com/espressif/esp-nuttx-bootloader -That repository contains a dummy IDF project that's used to build the bootloader and -partition table, these are then presented as Github assets and can be downloaded -from: https://github.com/espressif/esp-nuttx-bootloader/releases -Download ``bootloader-esp32c3.bin`` and ``partition-table-esp32c3.bin`` and place them -in a folder, the path to this folder will be used later to program them. This -can be: ``../esp-bins`` +Second stage bootloader +======================= + +Nuttx can boot the ESP32-C3 directly using the so-called "Simple Boot". +An externally-built 2nd stage bootloader is not required in this case as all +functions required to boot the device are built within Nuttx. Simple boot does not +require any specific configuration (it is selectable by default if no other +2nd stage bootloader is used). + +If other features, like `Secure Boot and Flash Encryption`_, are required, an +externally-built 2nd stage bootloader is needed. The bootloader is built using +the ``make bootloader`` command. This command generates the firmware in the +``nuttx`` folder. The ``ESPTOOL_BINDIR`` is used in the ``make flash`` command +to specify the path to the bootloader. For compatibility among other SoCs and +future options of 2nd stage bootloaders, the commands ``make bootloader`` and +the ``ESPTOOL_BINDIR`` option (for the ``make flash``) can be used even if no +externally-built 2nd stage bootloader is being built (they will be ignored if +Simple Boot is used, for instance). Building and flashing ===================== -First make sure that ``esptool.py`` is installed. This tool is used to convert -the ELF to a compatible ESP32 image and to flash the image into the board. +First, make sure that ``esptool.py`` is installed. This tool is used to convert +the ELF to a compatible ESP32-C3 image and to flash the image into the board. It can be installed with: ``pip install esptool``. -Configure the NuttX project: ``./tools/configure.sh esp32c3-devkit:nsh`` +Configure the NuttX project: ``./tools/configure.sh esp32c3-generic:nsh`` Run ``make`` to build the project. Note that the conversion mentioned above is included in the build process. -The ``esptool.py`` command to flash all the binaries is:: - - esptool.py --chip esp32c3 --port /dev/ttyUSBXX --baud 921600 write_flash 0x0 bootloader.bin 0x8000 partition-table.bin 0x10000 nuttx.bin +The ``esptool.py`` is used to flash all the binaries. However, this is also +included in the build process and we can build and flash with:: -However, this is also included in the build process and we can build and flash with:: + make flash ESPTOOL_PORT= ESPTOOL_BINDIR=./ - make flash ESPTOOL_PORT= ESPTOOL_BINDIR=../esp-bins - -Where ```` is typically ``/dev/ttyUSB0`` or similar and ``../esp-bins`` is -the path to the folder containing the bootloader and the partition table -for the ESP32-C3 as explained above. -Note that this step is required only one time. Once the bootloader and partition -table are flashed, we don't need to flash them again. So subsequent builds -would just require: ``make flash ESPTOOL_PORT=/dev/ttyUSBXX`` +Where ```` is typically ``/dev/ttyUSB0`` or similar and ``./`` is +the path to the folder containing the externally-built 2nd stage bootloader for +the ESP32-C3 as explained above. Debugging with OpenOCD ====================== @@ -117,7 +119,7 @@ integrates a USB-to-JTAG adapter. OpenOCD can then be used:: - openocd -c 'set ESP_RTOS none' -f board/esp32c3-builtin.cfg + openocd -c 'set ESP_RTOS none' -f board/esp32c3-builtin.cfg For versions prior to ESP32-C3 ECO3, an external JTAG adapter is needed. It can be connected as follows:: @@ -140,30 +142,31 @@ Peripheral Support The following list indicates the state of peripherals' support in NuttX: -=========== ======= ===== +=========== ======= ==================== Peripheral Support NOTES -=========== ======= ===== -ADC Yes -AES Yes -Bluetooth Yes +=========== ======= ==================== +ADC No +AES No +Bluetooth No +CAN/TWAI Yes CDC Console Yes Rev.3 -DMA Yes -eFuse Yes +DMA No +eFuse No GPIO Yes -I2C Yes +I2C No LED_PWM Yes -RNG Yes -RSA Yes +RNG No +RSA No RTC Yes -SHA Yes -SPI Yes +SHA No +SPI No SPIFLASH Yes Timers Yes -Touch Yes +Touch No UART Yes Watchdog Yes -Wifi Yes -=========== ======= ===== +Wifi Yes WPA3-SAE supported +=========== ======= ==================== Secure Boot and Flash Encryption ================================ @@ -211,24 +214,24 @@ of flash will not be sufficient to recover most flash contents. Prerequisites ------------- -First of all, we need to install ``imgtool`` (a MCUboot utility application to manipulate binary -images) and ``esptool`` (the ESP32-C3 toolkit):: +First of all, we need to install ``imgtool`` (the MCUboot utility application to manipulate binary +images):: - $ pip install imgtool esptool + $ pip install imgtool We also need to make sure that the python modules are added to ``PATH``:: - $ echo "PATH=$PATH:/home/$USER/.local/bin" >> ~/.bashrc + $ echo "PATH=$PATH:/home/$USER/.local/bin" >> ~/.bashrc Now, we will create a folder to store the generated keys (such as ``~/signing_keys``):: - $ mkdir ~/signing_keys && cd ~/signing_keys + $ mkdir ~/signing_keys && cd ~/signing_keys With all set up, we can now generate keys to sign the bootloader and application binary images, respectively, of the compiled project:: - $ espsecure.py generate_signing_key --version 2 bootloader_signing_key.pem - $ imgtool keygen --key app_signing_key.pem --type rsa-3072 + $ espsecure.py generate_signing_key --version 2 bootloader_signing_key.pem + $ imgtool keygen --key app_signing_key.pem --type rsa-3072 .. important:: The contents of the key files must be stored securely and kept secret. @@ -237,19 +240,14 @@ Enabling Secure Boot and Flash Encryption To enable Secure Boot for the current project, go to the project's NuttX directory, execute ``make menuconfig`` and the following steps: - 1. Enable experimental features in :menuselection:`Build Setup --> Show experimental options`; - - 2. Enable MCUboot in :menuselection:`Application Configuration --> Bootloader Utilities --> MCUboot`; - - 3. Change image type to ``MCUboot-bootable format`` in :menuselection:`System Type --> Application Image Configuration --> Application Image Format`; - - 4. Enable building MCUboot from the source code by selecting ``Build binaries from source``; - in :menuselection:`System Type --> Application Image Configuration --> Source for bootloader binaries`; - - 5. Enable Secure Boot in :menuselection:`System Type --> Application Image Configuration --> Enable hardware Secure Boot in bootloader`; - - 6. If you want to protect the SPI Bus against data sniffing, you can enable Flash Encryption in - :menuselection:`System Type --> Application Image Configuration --> Enable Flash Encryption on boot`. + 1. Enable experimental features in :menuselection:`Build Setup --> Show experimental options`; + 2. Enable MCUboot in :menuselection:`Application Configuration --> Bootloader Utilities --> MCUboot`; + 3. Change image type to ``MCUboot-bootable format`` in :menuselection:`System Type --> Application Image Configuration --> Application Image Format`; + 4. Enable building MCUboot from the source code by selecting ``Build binaries from source``; + in :menuselection:`System Type --> Application Image Configuration --> Source for bootloader binaries`; + 5. Enable Secure Boot in :menuselection:`System Type --> Application Image Configuration --> Enable hardware Secure Boot in bootloader`; + 6. If you want to protect the SPI Bus against data sniffing, you can enable Flash Encryption in + :menuselection:`System Type --> Application Image Configuration --> Enable Flash Encryption on boot`. Now you can design an update and confirm agent to your application. Check the `MCUboot design guide `_ and the `MCUboot Espressif port documentation `_ for @@ -277,7 +275,7 @@ Supported Boards ================ .. toctree:: - :glob: - :maxdepth: 1 + :glob: + :maxdepth: 1 - boards/*/* + boards/*/* diff --git a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkit/index.rst b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkit/index.rst deleted file mode 100644 index 6d038bbb932c3..0000000000000 --- a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkit/index.rst +++ /dev/null @@ -1,104 +0,0 @@ -================== -ESP32-C6-DevKitC-1 -================== - -ESP32-C6-DevKitC-1 is an entry-level development board based on ESP32-C6-WROOM-1(U), -a general-purpose module with a 8 MB SPI flash. This board integrates complete Wi-Fi, -Bluetooth LE, Zigbee, and Thread functions. You can find the board schematic -`here `_. - -Most of the I/O pins are broken out to the pin headers on both sides for easy interfacing. -Developers can either connect peripherals with jumper wires or mount ESP32-C6-DevKitC-1 on -a breadboard. - -.. figure:: esp32-c6-devkitc-1-isometric_v1.2.png - :alt: ESP32-C6-DevKitC-1 Board Layout - :figclass: align-center - - ESP32-C6-DevKitC-1 Board Layout - -The block diagram below presents main components of the ESP32-C6-DevKitC-1. - -.. figure:: esp32-c6-devkitc-1-v1.2-block-diagram.png - :alt: ESP32-C6-DevKitC-1 Electrical Block Diagram - :figclass: align-center - - ESP32-C6-DevKitC-1 Electrical Block Diagram - -Hardware Components -------------------- - -.. figure:: esp32-c6-devkitc-1-v1.2-annotated-photo.png - :alt: ESP32-C6-DevKitC-1 Hardware Components - :figclass: align-center - - ESP32-C6-DevKitC-1 Hardware Components - -Buttons and LEDs -================ - -Board Buttons --------------- -There are two buttons labeled Boot and RST. The RST button is not available -to software. It pulls the chip enable line that doubles as a reset line. - -The BOOT button is connected to IO9. On reset it is used as a strapping -pin to determine whether the chip boots normally or into the serial -bootloader. After reset, however, the BOOT button can be used for software -input. - -Board LEDs ----------- - -There is one on-board LED that indicates the presence of power. -Another WS2812 LED is connected to GPIO8 and is available for software. - -Current Measurement -=================== - -The J5 headers on the ESP32-C6-DevKitC-1 can be used for measuring the current -drawn by the ESP32-C6-WROOM-1(U) module: - - - Remove the jumper: Power supply between the module and peripherals on the - board is cut off. To measure the module's current, connect the board with an - ammeter via J5 headers; - - Apply the jumper (factory default): Restore the board's normal functionality. - -.. note:: - When using 3V3 and GND pin headers to power the board, please remove the J5 jumper, - and connect an ammeter in series to the external circuit to measure the module's current. - -Pin Mapping -=========== - -.. figure:: esp32-c6-devkitc-1-pin-layout.png - :alt: ESP32-C6-DevKitC pin layout - :figclass: align-center - - ESP32-C6-DevKitC-1 Pin Layout - -Configurations -============== - -All of the configurations presented below can be tested by running the following commands:: - - $ ./tools/configure.sh esp32c6-devkit: - $ make flash ESPTOOL_PORT=/dev/ttyUSB0 -j - -Where is the name of board configuration you want to use, i.e.: nsh, buttons, wifi... -Then use a serial console terminal like ``picocom`` configured to 115200 8N1. - -coremark --------- - -This configuration sets the CoreMark benchmark up for running on the maximum -number of cores for this system. It also enables some optimization flags and -disables the NuttShell to get the best possible score. - -.. note:: As the NSH is disabled, the application will start as soon as the - system is turned on. - -nsh ---- - -Basic configuration to run the NuttShell (nsh). \ No newline at end of file diff --git a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkit/esp32-c6-devkitc-1-isometric_v1.2.png b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/esp32-c6-devkitc-1-isometric_v1.2.png similarity index 100% rename from Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkit/esp32-c6-devkitc-1-isometric_v1.2.png rename to Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/esp32-c6-devkitc-1-isometric_v1.2.png diff --git a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkit/esp32-c6-devkitc-1-pin-layout.png b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/esp32-c6-devkitc-1-pin-layout.png similarity index 100% rename from Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkit/esp32-c6-devkitc-1-pin-layout.png rename to Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/esp32-c6-devkitc-1-pin-layout.png diff --git a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkit/esp32-c6-devkitc-1-v1.2-annotated-photo.png b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/esp32-c6-devkitc-1-v1.2-annotated-photo.png similarity index 100% rename from Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkit/esp32-c6-devkitc-1-v1.2-annotated-photo.png rename to Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/esp32-c6-devkitc-1-v1.2-annotated-photo.png diff --git a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkit/esp32-c6-devkitc-1-v1.2-block-diagram.png b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/esp32-c6-devkitc-1-v1.2-block-diagram.png similarity index 100% rename from Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkit/esp32-c6-devkitc-1-v1.2-block-diagram.png rename to Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/esp32-c6-devkitc-1-v1.2-block-diagram.png diff --git a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/index.rst b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/index.rst new file mode 100644 index 0000000000000..af7f93a0f6928 --- /dev/null +++ b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/index.rst @@ -0,0 +1,298 @@ +================== +ESP32-C6-DevKitC-1 +================== + +ESP32-C6-DevKitC-1 is an entry-level development board based on ESP32-C6-WROOM-1(U), +a general-purpose module with a 8 MB SPI flash. This board integrates complete Wi-Fi, +Bluetooth LE, Zigbee, and Thread functions. You can find the board schematic +`here `_. + +Most of the I/O pins are broken out to the pin headers on both sides for easy interfacing. +Developers can either connect peripherals with jumper wires or mount ESP32-C6-DevKitC-1 on +a breadboard. + +.. figure:: esp32-c6-devkitc-1-isometric_v1.2.png + :alt: ESP32-C6-DevKitC-1 Board Layout + :figclass: align-center + + ESP32-C6-DevKitC-1 Board Layout + +The block diagram below presents main components of the ESP32-C6-DevKitC-1. + +.. figure:: esp32-c6-devkitc-1-v1.2-block-diagram.png + :alt: ESP32-C6-DevKitC-1 Electrical Block Diagram + :figclass: align-center + + ESP32-C6-DevKitC-1 Electrical Block Diagram + +Hardware Components +------------------- + +.. figure:: esp32-c6-devkitc-1-v1.2-annotated-photo.png + :alt: ESP32-C6-DevKitC-1 Hardware Components + :figclass: align-center + + ESP32-C6-DevKitC-1 Hardware Components + +Buttons and LEDs +================ + +Board Buttons +-------------- +There are two buttons labeled Boot and RST. The RST button is not available +to software. It pulls the chip enable line that doubles as a reset line. + +The BOOT button is connected to IO9. On reset it is used as a strapping +pin to determine whether the chip boots normally or into the serial +bootloader. After reset, however, the BOOT button can be used for software +input. + +Board LEDs +---------- + +There is one on-board LED that indicates the presence of power. +Another WS2812 LED is connected to GPIO8 and is available for software. + +Current Measurement +=================== + +The J5 headers on the ESP32-C6-DevKitC-1 can be used for measuring the current +drawn by the ESP32-C6-WROOM-1(U) module: + + - Remove the jumper: Power supply between the module and peripherals on the + board is cut off. To measure the module's current, connect the board with an + ammeter via J5 headers; + - Apply the jumper (factory default): Restore the board's normal functionality. + +.. note:: + When using 3V3 and GND pin headers to power the board, please remove the J5 jumper, + and connect an ammeter in series to the external circuit to measure the module's current. + +Pin Mapping +=========== + +.. figure:: esp32-c6-devkitc-1-pin-layout.png + :alt: ESP32-C6-DevKitC pin layout + :figclass: align-center + + ESP32-C6-DevKitC-1 Pin Layout + +Configurations +============== + +All of the configurations presented below can be tested by running the following commands:: + + $ ./tools/configure.sh esp32c6-devkitc: + $ make flash ESPTOOL_PORT=/dev/ttyUSB0 -j + +Where is the name of board configuration you want to use, i.e.: nsh, buttons, wifi... +Then use a serial console terminal like ``picocom`` configured to 115200 8N1. + +coremark +-------- + +This configuration sets the CoreMark benchmark up for running on the maximum +number of cores for this system. It also enables some optimization flags and +disables the NuttShell to get the best possible score. + +.. note:: As the NSH is disabled, the application will start as soon as the + system is turned on. + +gpio +---- + +This is a test for the GPIO driver. It uses GPIO1 and GPIO2 as outputs and +GPIO9 as an interrupt pin. + +At the nsh, we can turn the outputs on and off with the following:: + + nsh> gpio -o 1 /dev/gpio0 + nsh> gpio -o 1 /dev/gpio1 + + nsh> gpio -o 0 /dev/gpio0 + nsh> gpio -o 0 /dev/gpio1 + +We can use the interrupt pin to send a signal when the interrupt fires:: + + nsh> gpio -w 14 /dev/gpio2 + +The pin is configured as a rising edge interrupt, so after issuing the +above command, connect it to 3.3V. + +nsh +--- + +Basic configuration to run the NuttShell (nsh). + +ostest +------ + +This is the NuttX test at ``apps/testing/ostest`` that is run against all new +architecture ports to assure a correct implementation of the OS. + +pwm +--- + +This configuration demonstrates the use of PWM through a LED connected to GPIO8. +To test it, just execute the ``pwm`` application:: + + nsh> pwm + pwm_main: starting output with frequency: 10000 duty: 00008000 + pwm_main: stopping output + +rmt +--- + +This configuration configures the transmitter and the receiver of the +Remote Control Transceiver (RMT) peripheral on the ESP32-C6 using GPIOs 8 +and 2, respectively. The RMT peripheral is better explained +`here `__, +in the ESP-IDF documentation. The minimal data unit in the frame is called the +RMT symbol, which is represented by ``rmt_item32_t`` in the driver: + +.. figure:: rmt_symbol.png + :align: center + +The example ``rmtchar`` can be used to test the RMT peripheral. Connecting +these pins externally to each other will make the transmitter send RMT items +and demonstrates the usage of the RMT peripheral:: + + nsh> rmtchar + +**WS2812 addressable RGB LEDs** + +This same configuration enables the usage of the RMT peripheral and the example +``ws2812`` to drive addressable RGB LEDs:: + + nsh> ws2812 + +Please note that this board contains an on-board WS2812 LED connected to GPIO8 +and, by default, this config configures the RMT transmitter in the same pin. + +rtc +--- + +This configuration demonstrates the use of the RTC driver through alarms. +You can set an alarm, check its progress and receive a notification after it expires:: + + nsh> alarm 10 + alarm_daemon started + alarm_daemon: Running + Opening /dev/rtc0 + Alarm 0 set in 10 seconds + nsh> alarm -r + Opening /dev/rtc0 + Alarm 0 is active with 10 seconds to expiration + nsh> alarm_daemon: alarm 0 received + +spiflash +-------- + +This config tests the external SPI that comes with the ESP32-C6 module connected +through SPI1. + +By default a SmartFS file system is selected. +Once booted you can use the following commands to mount the file system:: + + nsh> mksmartfs /dev/smart0 + nsh> mount -t smartfs /dev/smart0 /mnt + +sta_softap +---------- + +With this configuration you can run these commands to be able +to connect your smartphone or laptop to your board:: + + nsh> ifup wlan1 + nsh> dhcpd_start wlan1 + nsh> wapi psk wlan1 mypasswd 3 + nsh> wapi essid wlan1 nuttxap 1 + +In this case, you are creating the access point ``nuttxapp`` in your board and to +connect to it on your smartphone you will be required to type the password ``mypasswd`` +using WPA2. + +.. tip:: Please refer to :ref:`ESP32 Wi-Fi SoftAP Mode ` + for more information. + +The ``dhcpd_start`` is necessary to let your board to associate an IP to your smartphone. + +timer +----- + +This config test the general use purpose timers. It includes the 4 timers, +adds driver support, registers the timers as devices and includes the timer +example. + +To test it, just run the following:: + + nsh> timer -d /dev/timerx + +Where x in the timer instance. + +twai +---- + +This configuration enables the support for the TWAI (Two-Wire Automotive Interface) driver. +You can test it by connecting TWAI RX and TWAI TX pins which are GPIO0 and GPIO2 by default +to an external transceiver or connecting TWAI RX to TWAI TX pin by enabling +the `CONFIG_CAN_LOOPBACK` option (``Device Drivers -> CAN Driver Support -> CAN loopback mode``) +and running the ``can`` example:: + + nsh> can + nmsgs: 0 + min ID: 1 max ID: 2047 + Bit timing: + Baud: 1000000 + TSEG1: 15 + TSEG2: 4 + SJW: 3 + ID: 1 DLC: 1 + +usbconsole +---------- + +This configuration tests the built-in USB-to-serial converter found in ESP32-C6. +``esptool`` can be used to check the version of the chip and if this feature is +supported. Running ``esptool.py -p chip_id`` should have ``Chip is +ESP32-C6`` in its output. +When connecting the board a new device should appear, a ``/dev/ttyACMX`` on Linux +or a ``/dev/cu.usbmodemXXX`` om macOS. +This can be used to flash and monitor the device with the usual commands:: + + make download ESPTOOL_PORT=/dev/ttyACM0 + minicom -D /dev/ttyACM0 + +watchdog +-------- + +This configuration tests the watchdog timers. It includes the 1 MWDTS, +adds driver support, registers the WDTs as devices and includes the watchdog +example application. + +To test it, just run the following command:: + + nsh> wdog -i /dev/watchdogX + +Where X is the watchdog instance. + +wifi +---- + +Enables Wi-Fi support. You can define your credentials this way:: + + $ make menuconfig + -> Application Configuration + -> Network Utilities + -> Network initialization (NETUTILS_NETINIT [=y]) + -> WAPI Configuration + +Or if you don't want to keep it saved in the firmware you can do it +at runtime:: + + nsh> wapi psk wlan0 mypasswd 3 + nsh> wapi essid wlan0 myssid 1 + nsh> renew wlan0 + +.. tip:: Please refer to :ref:`ESP32 Wi-Fi Station Mode ` + for more information. diff --git a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/rmt_symbol.png b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/rmt_symbol.png new file mode 100644 index 0000000000000..7f859d7c98be7 Binary files /dev/null and b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitc/rmt_symbol.png differ diff --git a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/esp32-c6-devkitm-1-isometric.png b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/esp32-c6-devkitm-1-isometric.png new file mode 100644 index 0000000000000..11cf41908f4d5 Binary files /dev/null and b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/esp32-c6-devkitm-1-isometric.png differ diff --git a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/esp32-c6-devkitm-1-pin-layout.png b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/esp32-c6-devkitm-1-pin-layout.png new file mode 100644 index 0000000000000..b6e0255f315d3 Binary files /dev/null and b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/esp32-c6-devkitm-1-pin-layout.png differ diff --git a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/esp32-c6-devkitm-1-v1-annotated-photo.png b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/esp32-c6-devkitm-1-v1-annotated-photo.png new file mode 100644 index 0000000000000..b9aab3de7d81c Binary files /dev/null and b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/esp32-c6-devkitm-1-v1-annotated-photo.png differ diff --git a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/esp32-c6-devkitm-1-v1-block-diagram.png b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/esp32-c6-devkitm-1-v1-block-diagram.png new file mode 100644 index 0000000000000..57d5a29f1585f Binary files /dev/null and b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/esp32-c6-devkitm-1-v1-block-diagram.png differ diff --git a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/index.rst b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/index.rst new file mode 100644 index 0000000000000..6887ad704540c --- /dev/null +++ b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/index.rst @@ -0,0 +1,298 @@ +================== +ESP32-C6-DevKitM-1 +================== + +ESP32-C6-DevKitM-1 is an entry-level development board based on ESP32-C6-MINI-1(U), +a general-purpose module with a 4 MB SPI flash. This board integrates complete Wi-Fi, +Bluetooth LE, Zigbee, and Thread functions. You can find the board schematic +`here `_. + +Most of the I/O pins are broken out to the pin headers on both sides for easy interfacing. +Developers can either connect peripherals with jumper wires or mount ESP32-C6-DevKitM-1 on +a breadboard. + +.. figure:: esp32-c6-devkitm-1-isometric.png + :alt: ESP32-C6-DevKitM-1 Board Layout + :figclass: align-center + + ESP32-C6-DevKitM-1 Board Layout + +The block diagram below presents main components of the ESP32-C6-DevKitM-1. + +.. figure:: esp32-c6-devkitm-1-v1-block-diagram.png + :alt: ESP32-C6-DevKitM-1 Electrical Block Diagram + :figclass: align-center + + ESP32-C6-DevKitM-1 Electrical Block Diagram + +Hardware Components +------------------- + +.. figure:: esp32-c6-devkitm-1-v1-annotated-photo.png + :alt: ESP32-C6-DevKitM-1 Hardware Components + :figclass: align-center + + ESP32-C6-DevKitM-1 Hardware Components + +Buttons and LEDs +================ + +Board Buttons +-------------- +There are two buttons labeled Boot and RST. The RST button is not available +to software. It pulls the chip enable line that doubles as a reset line. + +The BOOT button is connected to IO9. On reset it is used as a strapping +pin to determine whether the chip boots normally or into the serial +bootloader. After reset, however, the BOOT button can be used for software +input. + +Board LEDs +---------- + +There is one on-board LED that indicates the presence of power. +Another WS2812 LED is connected to GPIO8 and is available for software. + +Current Measurement +=================== + +The J5 headers on the ESP32-C6-DevKitM-1 can be used for measuring the current +drawn by the ESP32-C6-MINI-1(U) module: + + - Remove the jumper: Power supply between the module and peripherals on the + board is cut off. To measure the module's current, connect the board with an + ammeter via J5 headers; + - Apply the jumper (factory default): Restore the board's normal functionality. + +.. note:: + When using 3V3 and GND pin headers to power the board, please remove the J5 jumper, + and connect an ammeter in series to the external circuit to measure the module's current. + +Pin Mapping +=========== + +.. figure:: esp32-c6-devkitm-1-pin-layout.png + :alt: ESP32-C6-DevKitM pin layout + :figclass: align-center + + ESP32-C6-DevKitM-1 Pin Layout + +Configurations +============== + +All of the configurations presented below can be tested by running the following commands:: + + $ ./tools/configure.sh esp32c6-devkitm: + $ make flash ESPTOOL_PORT=/dev/ttyUSB0 -j + +Where is the name of board configuration you want to use, i.e.: nsh, buttons, wifi... +Then use a serial console terminal like ``picocom`` configured to 115200 8N1. + +coremark +-------- + +This configuration sets the CoreMark benchmark up for running on the maximum +number of cores for this system. It also enables some optimization flags and +disables the NuttShell to get the best possible score. + +.. note:: As the NSH is disabled, the application will start as soon as the + system is turned on. + +gpio +---- + +This is a test for the GPIO driver. It uses GPIO1 and GPIO2 as outputs and +GPIO9 as an interrupt pin. + +At the nsh, we can turn the outputs on and off with the following:: + + nsh> gpio -o 1 /dev/gpio0 + nsh> gpio -o 1 /dev/gpio1 + + nsh> gpio -o 0 /dev/gpio0 + nsh> gpio -o 0 /dev/gpio1 + +We can use the interrupt pin to send a signal when the interrupt fires:: + + nsh> gpio -w 14 /dev/gpio2 + +The pin is configured as a rising edge interrupt, so after issuing the +above command, connect it to 3.3V. + +nsh +--- + +Basic configuration to run the NuttShell (nsh). + +ostest +------ + +This is the NuttX test at ``apps/testing/ostest`` that is run against all new +architecture ports to assure a correct implementation of the OS. + +pwm +--- + +This configuration demonstrates the use of PWM through a LED connected to GPIO8. +To test it, just execute the ``pwm`` application:: + + nsh> pwm + pwm_main: starting output with frequency: 10000 duty: 00008000 + pwm_main: stopping output + +rmt +--- + +This configuration configures the transmitter and the receiver of the +Remote Control Transceiver (RMT) peripheral on the ESP32-C6 using GPIOs 8 +and 2, respectively. The RMT peripheral is better explained +`here `__, +in the ESP-IDF documentation. The minimal data unit in the frame is called the +RMT symbol, which is represented by ``rmt_item32_t`` in the driver: + +.. figure:: rmt_symbol.png + :align: center + +The example ``rmtchar`` can be used to test the RMT peripheral. Connecting +these pins externally to each other will make the transmitter send RMT items +and demonstrates the usage of the RMT peripheral:: + + nsh> rmtchar + +**WS2812 addressable RGB LEDs** + +This same configuration enables the usage of the RMT peripheral and the example +``ws2812`` to drive addressable RGB LEDs:: + + nsh> ws2812 + +Please note that this board contains an on-board WS2812 LED connected to GPIO8 +and, by default, this config configures the RMT transmitter in the same pin. + +rtc +--- + +This configuration demonstrates the use of the RTC driver through alarms. +You can set an alarm, check its progress and receive a notification after it expires:: + + nsh> alarm 10 + alarm_daemon started + alarm_daemon: Running + Opening /dev/rtc0 + Alarm 0 set in 10 seconds + nsh> alarm -r + Opening /dev/rtc0 + Alarm 0 is active with 10 seconds to expiration + nsh> alarm_daemon: alarm 0 received + +spiflash +-------- + +This config tests the external SPI that comes with the ESP32-C6 module connected +through SPI1. + +By default a SmartFS file system is selected. +Once booted you can use the following commands to mount the file system:: + + nsh> mksmartfs /dev/smart0 + nsh> mount -t smartfs /dev/smart0 /mnt + +sta_softap +---------- + +With this configuration you can run these commands to be able +to connect your smartphone or laptop to your board:: + + nsh> ifup wlan1 + nsh> dhcpd_start wlan1 + nsh> wapi psk wlan1 mypasswd 3 + nsh> wapi essid wlan1 nuttxap 1 + +In this case, you are creating the access point ``nuttxapp`` in your board and to +connect to it on your smartphone you will be required to type the password ``mypasswd`` +using WPA2. + +.. tip:: Please refer to :ref:`ESP32 Wi-Fi SoftAP Mode ` + for more information. + +The ``dhcpd_start`` is necessary to let your board to associate an IP to your smartphone. + +timer +----- + +This config test the general use purpose timers. It includes the 4 timers, +adds driver support, registers the timers as devices and includes the timer +example. + +To test it, just run the following:: + + nsh> timer -d /dev/timerx + +Where x in the timer instance. + +twai +---- + +This configuration enables the support for the TWAI (Two-Wire Automotive Interface) driver. +You can test it by connecting TWAI RX and TWAI TX pins which are GPIO0 and GPIO2 by default +to an external transceiver or connecting TWAI RX to TWAI TX pin by enabling +the `CONFIG_CAN_LOOPBACK` option (``Device Drivers -> CAN Driver Support -> CAN loopback mode``) +and running the ``can`` example:: + + nsh> can + nmsgs: 0 + min ID: 1 max ID: 2047 + Bit timing: + Baud: 1000000 + TSEG1: 15 + TSEG2: 4 + SJW: 3 + ID: 1 DLC: 1 + +usbconsole +---------- + +This configuration tests the built-in USB-to-serial converter found in ESP32-C6. +``esptool`` can be used to check the version of the chip and if this feature is +supported. Running ``esptool.py -p chip_id`` should have ``Chip is +ESP32-C6`` in its output. +When connecting the board a new device should appear, a ``/dev/ttyACMX`` on Linux +or a ``/dev/cu.usbmodemXXX`` om macOS. +This can be used to flash and monitor the device with the usual commands:: + + make download ESPTOOL_PORT=/dev/ttyACM0 + minicom -D /dev/ttyACM0 + +watchdog +-------- + +This configuration tests the watchdog timers. It includes the 1 MWDTS, +adds driver support, registers the WDTs as devices and includes the watchdog +example application. + +To test it, just run the following command:: + + nsh> wdog -i /dev/watchdogX + +Where X is the watchdog instance. + +wifi +---- + +Enables Wi-Fi support. You can define your credentials this way:: + + $ make menuconfig + -> Application Configuration + -> Network Utilities + -> Network initialization (NETUTILS_NETINIT [=y]) + -> WAPI Configuration + +Or if you don't want to keep it saved in the firmware you can do it +at runtime:: + + nsh> wapi psk wlan0 mypasswd 3 + nsh> wapi essid wlan0 myssid 1 + nsh> renew wlan0 + +.. tip:: Please refer to :ref:`ESP32 Wi-Fi Station Mode ` + for more information. diff --git a/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/rmt_symbol.png b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/rmt_symbol.png new file mode 100644 index 0000000000000..7f859d7c98be7 Binary files /dev/null and b/Documentation/platforms/risc-v/esp32c6/boards/esp32c6-devkitm/rmt_symbol.png differ diff --git a/Documentation/platforms/risc-v/esp32c6/index.rst b/Documentation/platforms/risc-v/esp32c6/index.rst index f2c4aeeaf70fb..f09f1797df92e 100644 --- a/Documentation/platforms/risc-v/esp32c6/index.rst +++ b/Documentation/platforms/risc-v/esp32c6/index.rst @@ -33,16 +33,16 @@ check for the current compiler version being used. For instance: .. code-block:: - ############################################################################### - # Build image for tool required by RISCV builds - ############################################################################### - FROM nuttx-toolchain-base AS nuttx-toolchain-riscv - # Download the latest RISCV GCC toolchain prebuilt by xPack - RUN mkdir riscv-none-elf-gcc && \ - curl -s -L "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v12.3.0-2/xpack-riscv-none-elf-gcc-12.3.0-2-linux-x64.tar.gz" \ - | tar -C riscv-none-elf-gcc --strip-components 1 -xz + ############################################################################### + # Build image for tool required by RISCV builds + ############################################################################### + FROM nuttx-toolchain-base AS nuttx-toolchain-riscv + # Download the latest RISCV GCC toolchain prebuilt by xPack + RUN mkdir riscv-none-elf-gcc && \ + curl -s -L "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz" \ + | tar -C riscv-none-elf-gcc --strip-components 1 -xz -It uses the xPack's prebuilt toolchain based on GCC 12.3.0. +It uses the xPack's prebuilt toolchain based on GCC 13.2.0-2. Installing ---------- @@ -51,60 +51,81 @@ First, create a directory to hold the toolchain: .. code-block:: console - $ mkdir -p /path/to/your/toolchain/riscv-none-elf-gcc + $ mkdir -p /path/to/your/toolchain/riscv-none-elf-gcc Download and extract toolchain: .. code-block:: console - $ curl -s -L "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v12.3.0-2/xpack-riscv-none-elf-gcc-12.3.0-2-linux-x64.tar.gz" \ - | tar -C /path/to/your/toolchain/riscv-none-elf-gcc --strip-components 1 -xz + $ curl -s -L "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz" \ + | tar -C /path/to/your/toolchain/riscv-none-elf-gcc --strip-components 1 -xz Add the toolchain to your `PATH`: .. code-block:: console - $ echo "export PATH=/path/to/your/toolchain/riscv-none-elf-gcc/bin:$PATH" >> ~/.bashrc + $ echo "export PATH=/path/to/your/toolchain/riscv-none-elf-gcc/bin:$PATH" >> ~/.bashrc You can edit your shell's rc files if you don't use bash. -Second stage bootloader and partition table -=========================================== +Second stage bootloader +======================= -The NuttX port for now relies on IDF's second stage bootloader to carry on some hardware -initializations. The binaries for the bootloader and the partition table can be found in -this repository: https://github.com/espressif/esp-nuttx-bootloader -That repository contains a dummy IDF project that's used to build the bootloader and -partition table, these are then presented as Github assets and can be downloaded -from: https://github.com/espressif/esp-nuttx-bootloader/releases -Download ``bootloader-esp32c6.bin`` and ``partition-table-esp32c6.bin`` and place them -in a folder, the path to this folder will be used later to program them. This -can be: ``../esp-bins`` +Nuttx can boot the ESP32-C6 directly using the so-called "Simple Boot". +An externally-built 2nd stage bootloader is not required in this case as all +functions required to boot the device are built within Nuttx. Simple boot does not +require any specific configuration (it is selectable by default if no other +2nd stage bootloader is used). For compatibility among other SoCs and future options +of 2nd stage bootloaders, the commands ``make bootloader`` and the ``ESPTOOL_BINDIR`` +option (for the ``make flash``) are kept (and ignored if Simple Boot is used). Building and flashing ===================== -First make sure that ``esptool.py`` is installed. This tool is used to convert +First, make sure that ``esptool.py`` is installed. This tool is used to convert the ELF to a compatible ESP32-C6 image and to flash the image into the board. It can be installed with: ``pip install esptool``. -Configure the NuttX project: ``./tools/configure.sh esp32c6-devkit:nsh`` +Configure the NuttX project: ``./tools/configure.sh esp32c6-devkitc:nsh`` Run ``make`` to build the project. Note that the conversion mentioned above is included in the build process. -The ``esptool.py`` command to flash all the binaries is:: +The ``esptool.py`` is used to flash all the binaries. However, this is also +included in the build process and we can build and flash with:: - esptool.py --chip esp32c6 --port /dev/ttyUSBXX --baud 921600 write_flash 0x0 bootloader.bin 0x8000 partition-table.bin 0x10000 nuttx.bin + make flash ESPTOOL_PORT= ESPTOOL_BINDIR=./ -However, this is also included in the build process and we can build and flash with:: +Where ```` is typically ``/dev/ttyUSB0`` or similar and ``./`` is +the path to the folder containing the externally-built 2nd stage bootloader for +the ESP32-C6 as explained above. - make flash ESPTOOL_PORT= ESPTOOL_BINDIR=../esp-bins +Debugging with OpenOCD +====================== -Where ```` is typically ``/dev/ttyUSB0`` or similar and ``../esp-bins`` is -the path to the folder containing the bootloader and the partition table -for the ESP32-C6 as explained above. -Note that this step is required only one time. Once the bootloader and partition -table are flashed, we don't need to flash them again. So subsequent builds -would just require: ``make flash ESPTOOL_PORT=/dev/ttyUSBXX`` +Download and build OpenOCD from Espressif, that can be found in +https://github.com/espressif/openocd-esp32 + +You do not need an external JTAG to debug, the ESP32-C6 integrates a +USB-to-JTAG adapter. + +OpenOCD can then be used:: + + openocd -c 'set ESP_RTOS none' -f board/esp32c6-builtin.cfg + +If you want to debug with an external JTAG adapter it can +be connected as follows:: + + TMS -> GPIO4 + TDI -> GPIO5 + TCK -> GPIO6 + TDO -> GPIO7 + +Furthermore, an efuse needs to be burnt to be able to debug:: + + espefuse.py -p burn_efuse DIS_USB_JTAG + +OpenOCD can then be used:: + + openocd -c 'set ESP_RTOS none' -f board/esp32c6-ftdi.cfg Peripheral Support ================== @@ -117,32 +138,32 @@ Peripheral Support ADC No AES No Bluetooth No -CAN/TWAI No +CAN/TWAI Yes DMA No ECC No eFuse No -GPIO No +GPIO Yes HMAC No I2C No I2S No Int. Temp. No LED No -LED_PWM No +LED_PWM Yes MCPWM No Pulse Counter No RMT No RNG No RSA No -RTC No +RTC Yes SD/MMC No SDIO No SHA No SPI No -SPIFLASH No -Timers No +SPIFLASH Yes +Timers Yes UART Yes Watchdog Yes -Wifi No +Wifi Yes XTS No ============== ======= @@ -150,7 +171,7 @@ Supported Boards ================ .. toctree:: - :glob: - :maxdepth: 1 + :glob: + :maxdepth: 1 - boards/*/* + boards/*/* diff --git a/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/ESP32-H2-DevKitM-1-v1.0-block-diagram.png b/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/ESP32-H2-DevKitM-1-v1.0-block-diagram.png new file mode 100644 index 0000000000000..6b87d1162e4d1 Binary files /dev/null and b/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/ESP32-H2-DevKitM-1-v1.0-block-diagram.png differ diff --git a/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/esp32-h2-devkitm-1-isometric.png b/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/esp32-h2-devkitm-1-isometric.png new file mode 100644 index 0000000000000..974c61b144d47 Binary files /dev/null and b/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/esp32-h2-devkitm-1-isometric.png differ diff --git a/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/esp32-h2-devkitm-1-pin-layout.png b/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/esp32-h2-devkitm-1-pin-layout.png new file mode 100644 index 0000000000000..1e326e6d01133 Binary files /dev/null and b/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/esp32-h2-devkitm-1-pin-layout.png differ diff --git a/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/esp32-h2-devkitm-1-v1.2-annotated-photo.png b/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/esp32-h2-devkitm-1-v1.2-annotated-photo.png new file mode 100644 index 0000000000000..208ff02f2ccbd Binary files /dev/null and b/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/esp32-h2-devkitm-1-v1.2-annotated-photo.png differ diff --git a/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/index.rst b/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/index.rst new file mode 100644 index 0000000000000..8d53ec0b58d52 --- /dev/null +++ b/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/index.rst @@ -0,0 +1,256 @@ +================== +ESP32-H2-DevKitM-1 +================== + +ESP32-H2-DevKitM-1 is an entry-level development board based on Bluetooth® Low Energy and +IEEE 802.15.4 combo module ESP32-H2-MINI-1 or ESP32-H2-MINI-1U. You can find the board schematic +`here `_. + +Most of the I/O pins on the ESP32-H2-MINI-1/1U module are broken out to the pin headers on +both sides of this board for easy interfacing. Developers can either connect peripherals with +jumper wires or mount ESP32-H2-DevKitM-1 on a breadboard. + +.. figure:: esp32-h2-devkitm-1-isometric.png + :alt: ESP32-H2-DevKitM-1 Board Layout + :figclass: align-center + + ESP32-H2-DevKitM-1 Board Layout + +The block diagram below presents main components of the ESP32-H2-DevKitM-1. + +.. figure:: ESP32-H2-DevKitM-1-v1.0-block-diagram.png + :alt: ESP32-H2-DevKitM-1 Electrical Block Diagram + :figclass: align-center + + ESP32-H2-DevKitM-1 Electrical Block Diagram + +Hardware Components +------------------- + +.. figure:: esp32-h2-devkitm-1-v1.2-annotated-photo.png + :alt: ESP32-H2-DevKitM-1 Hardware Components + :figclass: align-center + + ESP32-H2-DevKitM-1 Hardware Components + +Buttons and LEDs +================ + +Board Buttons +-------------- +There are two buttons labeled Boot and RST. The RST button is not available +to software. It pulls the chip enable line that doubles as a reset line. + +The BOOT button is connected to IO9. On reset it is used as a strapping +pin to determine whether the chip boots normally or into the serial +bootloader. After reset, however, the BOOT button can be used for software +input. + +Board LEDs +---------- + +There is one on-board LED that indicates the presence of power. +Another WS2812 LED is connected to GPIO8 and is available for software. + +Current Measurement +=================== + +The J5 headers on ESP32-H2-DevKitM-1 can be used for measuring the current +drawn by the ESP32-H2-MINI-1/1U module: + + - Remove the jumper: Power supply between the module and peripherals on the + board is cut off. To measure the module's current, connect the board with an + ammeter via J5 headers; + - Apply the jumper (factory default): Restore the board's normal functionality. + +.. note:: + When using 3V3 and GND pin headers to power the board, please remove the J5 jumper, + and connect an ammeter in series to the external circuit to measure the module's current. + +Pin Mapping +=========== + +.. figure:: esp32-h2-devkitm-1-pin-layout.png + :alt: ESP32-H2-DevKitM-1 pin layout + :figclass: align-center + + ESP32-H2-DevKitM-1 Pin Layout + +Configurations +============== + +All of the configurations presented below can be tested by running the following commands:: + + $ ./tools/configure.sh esp32h2-devkit: + $ make flash ESPTOOL_PORT=/dev/ttyUSB0 -j + +Where is the name of board configuration you want to use, i.e.: nsh, buttons, wifi... +Then use a serial console terminal like ``picocom`` configured to 115200 8N1. + +coremark +-------- + +This configuration sets the CoreMark benchmark up for running on the maximum +number of cores for this system. It also enables some optimization flags and +disables the NuttShell to get the best possible score. + +.. note:: As the NSH is disabled, the application will start as soon as the + system is turned on. + +gpio +---- + +This is a test for the GPIO driver. It uses GPIO1 and GPIO2 as outputs and +GPIO9 as an interrupt pin. + +At the nsh, we can turn the outputs on and off with the following:: + + nsh> gpio -o 1 /dev/gpio0 + nsh> gpio -o 1 /dev/gpio1 + + nsh> gpio -o 0 /dev/gpio0 + nsh> gpio -o 0 /dev/gpio1 + +We can use the interrupt pin to send a signal when the interrupt fires:: + + nsh> gpio -w 14 /dev/gpio2 + +The pin is configured as a rising edge interrupt, so after issuing the +above command, connect it to 3.3V. + +nsh +--- + +Basic configuration to run the NuttShell (nsh). + +ostest +------ + +This is the NuttX test at ``apps/testing/ostest`` that is run against all new +architecture ports to assure a correct implementation of the OS. + +pwm +--- + +This configuration demonstrates the use of PWM through a LED connected to GPIO8. +To test it, just execute the ``pwm`` application:: + + nsh> pwm + pwm_main: starting output with frequency: 10000 duty: 00008000 + pwm_main: stopping output + +rmt +--- + +This configuration configures the transmitter and the receiver of the +Remote Control Transceiver (RMT) peripheral on the ESP32-H2 using GPIOs 8 +and 2, respectively. The RMT peripheral is better explained +`here `__, +in the ESP-IDF documentation. The minimal data unit in the frame is called the +RMT symbol, which is represented by ``rmt_item32_t`` in the driver: + +.. figure:: rmt_symbol.png + :align: center + +The example ``rmtchar`` can be used to test the RMT peripheral. Connecting +these pins externally to each other will make the transmitter send RMT items +and demonstrates the usage of the RMT peripheral:: + + nsh> rmtchar + +**WS2812 addressable RGB LEDs** + +This same configuration enables the usage of the RMT peripheral and the example +``ws2812`` to drive addressable RGB LEDs:: + + nsh> ws2812 + +Please note that this board contains an on-board WS2812 LED connected to GPIO8 +and, by default, this config configures the RMT transmitter in the same pin. + +rtc +--- + +This configuration demonstrates the use of the RTC driver through alarms. +You can set an alarm, check its progress and receive a notification after it expires:: + + nsh> alarm 10 + alarm_daemon started + alarm_daemon: Running + Opening /dev/rtc0 + Alarm 0 set in 10 seconds + nsh> alarm -r + Opening /dev/rtc0 + Alarm 0 is active with 10 seconds to expiration + nsh> alarm_daemon: alarm 0 received + +spiflash +-------- + +This config tests the external SPI that comes with the ESP32-H2 module connected +through SPI1. + +By default a SmartFS file system is selected. +Once booted you can use the following commands to mount the file system:: + + nsh> mksmartfs /dev/smart0 + nsh> mount -t smartfs /dev/smart0 /mnt + +timer +----- + +This config test the general use purpose timers. It includes the 4 timers, +adds driver support, registers the timers as devices and includes the timer +example. + +To test it, just run the following:: + + nsh> timer -d /dev/timerx + +Where x in the timer instance. + +twai +---- + +This configuration enables the support for the TWAI (Two-Wire Automotive Interface) driver. +You can test it by connecting TWAI RX and TWAI TX pins which are GPIO0 and GPIO2 by default +to an external transceiver or connecting TWAI RX to TWAI TX pin by enabling +the `CONFIG_CAN_LOOPBACK` option (``Device Drivers -> CAN Driver Support -> CAN loopback mode``) +and running the ``can`` example:: + + nsh> can + nmsgs: 0 + min ID: 1 max ID: 2047 + Bit timing: + Baud: 1000000 + TSEG1: 15 + TSEG2: 4 + SJW: 3 + ID: 1 DLC: 1 + +usbconsole +---------- + +This configuration tests the built-in USB-to-serial converter found in ESP32-H2. +``esptool`` can be used to check the version of the chip and if this feature is +supported. Running ``esptool.py -p chip_id`` should have ``Chip is +ESP32-H2`` in its output. +When connecting the board a new device should appear, a ``/dev/ttyACMX`` on Linux +or a ``/dev/cu.usbmodemXXX`` om macOS. +This can be used to flash and monitor the device with the usual commands:: + + make download ESPTOOL_PORT=/dev/ttyACM0 + minicom -D /dev/ttyACM0 + +watchdog +-------- + +This configuration tests the watchdog timers. It includes the 1 MWDTS, +adds driver support, registers the WDTs as devices and includes the watchdog +example application. + +To test it, just run the following command:: + + nsh> wdog -i /dev/watchdogX + +Where X is the watchdog instance. diff --git a/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/rmt_symbol.png b/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/rmt_symbol.png new file mode 100644 index 0000000000000..7f859d7c98be7 Binary files /dev/null and b/Documentation/platforms/risc-v/esp32h2/boards/esp32h2-devkit/rmt_symbol.png differ diff --git a/Documentation/platforms/risc-v/esp32h2/index.rst b/Documentation/platforms/risc-v/esp32h2/index.rst new file mode 100644 index 0000000000000..0e9102c7969d6 --- /dev/null +++ b/Documentation/platforms/risc-v/esp32h2/index.rst @@ -0,0 +1,177 @@ +================== +Espressif ESP32-H2 +================== + +The ESP32-H2 is an ultra-low-power and highly integrated SoC with a RISC-V +core and supports 2.4 GHz transceiver, Bluetooth 5 (LE) and the 802.15.4 protocol. + +* Address Space + - 452 KB of internal memory address space accessed from the instruction bus + - 452 KB of internal memory address space accessed from the data bus + - 832 KB of peripheral address space + - 16 MB of external memory virtual address space accessed from the instruction bus + - 16 MB of external memory virtual address space accessed from the data bus + - 260 KB of internal DMA address space +* Internal Memory + - 128 KB ROM + - 320 KB SRAM (16 KB can be configured as Cache) + - 4 KB of SRAM in RTC +* External Memory + - Up to 16 MB of external flash +* Peripherals + - Multiple peripherals +* GDMA + - 7 modules are capable of DMA operations. + +ESP32-H2 Toolchain +================== + +A generic RISC-V toolchain can be used to build ESP32-H2 projects. It's recommended to use the same +toolchain used by NuttX CI. Please refer to the Docker +`container `_ and +check for the current compiler version being used. For instance: + +.. code-block:: + + ############################################################################### + # Build image for tool required by RISCV builds + ############################################################################### + FROM nuttx-toolchain-base AS nuttx-toolchain-riscv + # Download the latest RISCV GCC toolchain prebuilt by xPack + RUN mkdir riscv-none-elf-gcc && \ + curl -s -L "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz" \ + | tar -C riscv-none-elf-gcc --strip-components 1 -xz + +It uses the xPack's prebuilt toolchain based on GCC 13.2.0-2. + +Installing +---------- + +First, create a directory to hold the toolchain: + +.. code-block:: console + + $ mkdir -p /path/to/your/toolchain/riscv-none-elf-gcc + +Download and extract toolchain: + +.. code-block:: console + + $ curl -s -L "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz" \ + | tar -C /path/to/your/toolchain/riscv-none-elf-gcc --strip-components 1 -xz + +Add the toolchain to your `PATH`: + +.. code-block:: console + + $ echo "export PATH=/path/to/your/toolchain/riscv-none-elf-gcc/bin:$PATH" >> ~/.bashrc + +You can edit your shell's rc files if you don't use bash. + +Second stage bootloader +======================= + +Nuttx can boot the ESP32-H2 directly using the so-called "Simple Boot". +An externally-built 2nd stage bootloader is not required in this case as all +functions required to boot the device are built within Nuttx. Simple boot does not +require any specific configuration (it is selectable by default if no other +2nd stage bootloader is used). For compatibility among other SoCs and future options +of 2nd stage bootloaders, the commands ``make bootloader`` and the ``ESPTOOL_BINDIR`` +option (for the ``make flash``) are kept (and ignored if Simple Boot is used). + +Building and flashing +===================== + +First, make sure that ``esptool.py`` is installed. This tool is used to convert +the ELF to a compatible ESP32-H2 image and to flash the image into the board. +It can be installed with: ``pip install esptool``. + +Configure the NuttX project: ``./tools/configure.sh esp32h2-devkit:nsh`` +Run ``make`` to build the project. Note that the conversion mentioned above is +included in the build process. +The ``esptool.py`` is used to flash all the binaries. However, this is also +included in the build process and we can build and flash with:: + + make flash ESPTOOL_PORT= ESPTOOL_BINDIR=./ + +Where ```` is typically ``/dev/ttyUSB0`` or similar and ``./`` is +the path to the folder containing the externally-built 2nd stage bootloader for +the ESP32-H2 as explained above. + +Debugging with OpenOCD +====================== + +Download and build OpenOCD from Espressif, that can be found in +https://github.com/espressif/openocd-esp32 + +You don not need an external JTAG is to debug, the ESP32-H2 integrates a +USB-to-JTAG adapter. + +OpenOCD can then be used:: + + openocd -c 'set ESP_RTOS none' -f board/esp32h2-builtin.cfg + +If you want to debug with an external JTAG adapter it can +be connected as follows:: + + TMS -> GPIO2 + TDI -> GPIO5 + TCK -> GPIO5 + TDO -> GPIO3 + +Furthermore, an efuse needs to be burnt to be able to debug:: + + espefuse.py -p burn_efuse DIS_USB_JTAG + +OpenOCD can then be used:: + + openocd -c 'set ESP_RTOS none' -f board/esp32h2-ftdi.cfg + +Peripheral Support +================== + +The following list indicates the state of peripherals' support in NuttX: + +============== ======= +Peripheral Support +============== ======= +ADC No +AES No +Bluetooth No +CAN/TWAI Yes +DMA No +ECC No +eFuse No +GPIO Yes +HMAC No +I2C No +I2S No +Int. Temp. No +LED No +LED_PWM Yes +MCPWM No +Pulse Counter No +RMT No +RNG No +RSA No +RTC Yes +SD/MMC No +SDIO No +SHA No +SPI No +SPIFLASH Yes +Timers Yes +UART Yes +Watchdog Yes +Wifi No +XTS No +============== ======= + +Supported Boards +================ + +.. toctree:: + :glob: + :maxdepth: 1 + + boards/*/* diff --git a/Documentation/platforms/risc-v/k230/boards/canmv230/index.rst b/Documentation/platforms/risc-v/k230/boards/canmv230/index.rst index 7f5cdd67d5197..acbaae474ca73 100644 --- a/Documentation/platforms/risc-v/k230/boards/canmv230/index.rst +++ b/Documentation/platforms/risc-v/k230/boards/canmv230/index.rst @@ -2,62 +2,180 @@ CanMV K230 ============= -The `Kendryte K230 `_ SoC contains two indepedent T-Head C908 based RV64GC CPU cores. The CPU1 even has RVV1.0 vector extension and operates at higher speed. The SoC contains accelerators for depth image processing, audio processing and neural network inferencing etc. - The `CanMV K230 `_ is a raspberry-pi sized single board computer with 512MB DRAM and a microSD card slot for booting. It comes with serial console, Ethernet, HDMI and USB/OTG ports. Unfortuunately it doesn't support JTAG alike debugging interfaces. The `K230 SDK `_ contains source code, libraries and user guides for booting up an AMP enviroment with Linux on CPU0 and RT-Thread on CPU1. -K230 boots from CPU0 and loads U-Boot into DRAM first, then U-Boot kicks off OpenSBI wrapped Linux/RTT OS images on respective CPU cores accordingly. - -The K230 U-Boot operates in machine mode, thus provides an ideal environment for NuttX. allowing one to run flat or kernel builds in theory. +K230 boots from CPU0 and loads U-Boot SPL into DRAM first, then U-Boot kicks off OpenSBI wrapped Linux/RTT OS images on respective CPU cores accordingly. +The K230 U-Boot kicks off firmwares in machine mode, thus it allows flat, protected or kernel +NuttX `build modes `_. The kernel build mode further works with OpenSBI or a builtin minimal SBI layer. Preparations ============ -Please follow the K230 SDK to prepare a booting SD card for the board, or use prebuilt boot image from `here `_. +Take the prebuilt CanMV-k230 boot image from `here `_ as the default K230 SDK doesn't support RiscV standard PTE format at least till v1.2. The package also contains an extract of the OpenSBI from K230 SDK v1.2 release, which is needed to wrap the `canmv230/knsh` kernel build. The K230 SBI extract is +also available at `this Github repository `_, it will updated +over the time to match updates at NuttX repository. Make sure that before trying NuttX: -- The board can boot default SDK image normally. -- U-Boot console can be accessed from host(e.g. `minicom -D /dev/ttyACM0`). -- U-Boot has access to a TFTP service is available. -- You can drop files to the TFTP service folder. +- The board can boot with prebuilt CanMV-k230 image. +- Device console access available (e.g. ``minicom -D /dev/ttyACM0``). +- U-Boot connectivity to TFTP service available. -Note for below NuttX tests, the SD image is only used to enter U-Boot console. +For below NuttX tests, the microSD card is only used to enter the U-Boot console environment, as NuttX isn't using any storage yet. -RISC-V Toolchain -================ +Toolchains +========== -Before building NuttX for Star64, download the **RISC-V Toolchain riscv64-unknown-elf** from `XPack `_ or use "gcc-riscv64-unknown-elf" on Ubuntu. +To build NuttX, we can use the stock **gcc-riscv64-unknown-elf** toolchain on Ubuntu, or download the RISC-V Toolchain riscv64-unknown-elf from `XPack `_. Building ======== -To build NuttX for CanMV, :doc:`install the prerequisites ` and :doc:`clone the git repositories ` for ``nuttx`` and ``apps``. -Configure the NuttX project and build the project: +To build NuttX for CanMV-k230, :doc:`install the prerequisites ` and :doc:`clone the git repositories ` for ``nuttx`` and ``apps``. + +FLAT Build +---------- + +FLAT build is straightforward: + +.. code:: console + + $ cd nuttx + $ make distclean && tools/configure.sh canmv230:nsh + $ make -j4 + +The generated `nuttx.bin` can then be tried on the target. + +PROTECTED Build +--------------- + +PROTECTED build can be done like below: .. code:: console $ cd nuttx - $ tools/configure.sh canmv230:nsh + $ make distclean && tools/configure.sh canmv230:pnsh $ make -j4 -There should have `nuttx.bin` generated. +There will be `nuttx.bin` and `nuttx_user.bin` generated. We need pad `nuttx.bin` to so that to fill memory gap till user space flash start then combine it with `nuttx_user.bin` to form the final binary for run on the target. Say the gap between uflash and kflash is 256KB in `scripts/ld-protected.script`, we can pad-combine them like below: + +.. code:: console + + $ dd if=/dev/zero of=/tmp/padded bs=1024 count=256 + $ dd if=nuttx.bin of=/tmp/padded conv=notrunc + $ cat /tmp/padded nuttx_user.bin > /tftp-folder/nuttx.bin + +The combined `nuttx.bin` in TFTP service folder can then be tried on target. + +KERNEL Build +------------ + +KERNEL build requires two build passes: + +- First pass to build kernel and export package so that to build apps as ROMFS. +- Second pass to build the kernel with real ROMFS image containing the apps. + +There are two configurations for KERNEL build mode: + +- The ``canmv230/knsh`` is for use within standard SBI environment. +- The ``canmv230/nsbi`` uses a built-in minimal SBI environment. + +The ``canmv230/nsbi`` has smaller footprint and is simpler to use, the ``canmv230/knsh`` is more tedious to build and is for situatinos with standard SBI environment. + +Take the following steps to build the kernel export package: + +.. code:: console + + $ # first pass to build kernel exports + $ cd nuttx + $ make distclean && tools/configure.sh canmv230:knsh + $ make -j4 + $ make export # build nuttx-export-*.gz package + +With export package, we can then build the apps and ROMFS: + +.. code:: console + + $ cd apps + $ # import the nuttx-export-*.gz package from kernel + $ tools/mkimport.sh -z -x ../nuttx/nuttx-export-*.gz + $ make import) # build the apps + $ # generate ROMFS image for contents in apps/bin folder + $ tools/mkromfsimg.sh ../nuttx/arch/risc-v/src/board/romfs_boot.c + +Once ROMFS for apps is ready, build the kernel again: + +.. code:: console + + $ cd nuttx + $ make -j4 # build kernel again with real ROMFS + +The ``nuttx.bin`` is the artifact of kernel build. For ``canmv230/nsbi`` case, simply copy it to the TFTP folder then run on the target. + +For ``canmv230/knsh`` case, take additional steps to wrap the artifact with the OpenSBI extract from the K230 SDK downloaded above: -Booting +.. code:: console + + $ cd $HOME + $ # unpack the K230 OpenSBI extract + $ tar xvf canmv230-opensbi-dtb.tar.xz + $ export OSBI=$HOME/opensbi + $ cd /tmp/aaa # use a temporary folder + $ make -C $OSBI O=$(pwd) PLATFORM=generic \ + CROSS_COMPILE=riscv64-unknown-elf- FW_PIC=n K230_LIITLE_CORE=1 \ + FW_FDT_PATH=$OSBI/k230.dtb FW_PAYLOAD_PATH=nuttx.bin -j4 + $ cp platform/generic/firmware/fw_payload.bin tftp-server-path/nuttx.bin + +Please use actual paths on your host for ``nuttx.bin`` and TFTP folder when running above commands. + +This Github `repository `_ contains latest version of the K230 OpenSBI extract. + + +Running ======= -Copy the `nuttx.bin` to the TFTP service folder and work with the U-Boot console: +Within U-boot console, load ``nuttx.bin`` from TFTP and run it as shown below: .. code:: console k230# usb start k230# ping $serverip k230# tftp 8000000 nuttx.bin - k230# boot_barememtal 0 8000000 $filesize + k230# go 8000000 + +Then the ``nsh`` console should appear, type ``help`` to see available commands. + + +Asymmetric Multi Processing +=========================== + +We can do Asymmetric Multi Processing on K230 using the little core as master and the big core as remote. + +Take the ``canmv230/master`` and ``canmv230/remote`` configurations to build the master and remote NuttX images respectively. They are both kernel builds derived from ``canmv230/nsbi`` mentioned above, so we can follow above kernel mode build steps to build them. + +Let's put the NuttX image files as ``master.bin`` and ``remote.bin`` respectively on the TFTP folder. To run them on K230 device, do the following from U-Boot console: + + +.. code:: console + + k230# usb start + k230# ping $serverip + k230# tftp 7000000 remote.bin + k230# tftp 8000000 master.bin + k230# go 8000000 + +Then we should see the "master> " prompt, this is the master console. where we can further run the ``cu`` command and press Return key to see the remote console, within remote console type ``~.`` to get back to the master console. + +There is a `session log `_ showing how to enter remote node and check file system status then get back and check master file system status. + + +Issues +====== + +- The ``ostest`` app has non-zero exit code in Kernel mode. -Then the `nsh> `console should appear, type `help` to see available commands. diff --git a/Documentation/platforms/risc-v/k230/index.rst b/Documentation/platforms/risc-v/k230/index.rst index 6f6c8ed2b3fbd..a93e8d55cd3ca 100644 --- a/Documentation/platforms/risc-v/k230/index.rst +++ b/Documentation/platforms/risc-v/k230/index.rst @@ -2,6 +2,23 @@ Kendryte K230 ============= +The `Kendryte K230 `_ SoC contains two 64 bit RV64GC CPUs based on T-Head C908 IP core for embedded IoT applications. + +- **CPU1:** RISC-V Core, 1.6GHz, 32KB I-cache, 32KB D-cache, 256KB L2 Cache, 128bit RVV 1.0 support +- **CPU0:** RISC-V Core, 0.8GHz, 32KB I-cache, 32KB D-cache, 256KB L2 Cache +- **KPU:** INT8 and INT16 Inference performance: Restnet-50>85fps@INT8, Mobilenet_v2 >670fps@INT8, YoloV5S>38fps@INT8 +- **DPU:** for 3D structured light, resolution is up to 1920*1080 +- **RAM:** 32-bit LPDDR4 / DDR4 / LPDDR3 / DDR3 +- **Video Codec:** H.264, H.265 and JPEG support; +- **Video Input:** 3 x MIPI-CSI +- **Video Output:** 1 x MIPI DSI +- **USB:** USB-OTG 2.0 x 2 +- **Security:** TRNG, OTP +- **Peripherals:** 5xUART, 5xI2C, 6xPWM, 64xGPIO+8xPMU, 2xSDxC:SD3.0, 3xSPI, WDT/RTC/Timer + +See more details from above vendor's website. + + Supported Boards ================ diff --git a/Documentation/platforms/risc-v/litex/cores/vexriscv/index.rst b/Documentation/platforms/risc-v/litex/cores/vexriscv/index.rst index ec6306c2c20d5..6b39c841c8b5b 100644 --- a/Documentation/platforms/risc-v/litex/cores/vexriscv/index.rst +++ b/Documentation/platforms/risc-v/litex/cores/vexriscv/index.rst @@ -22,7 +22,8 @@ Booting Create a file, 'boot.json' in the Nuttx root directory, with the following content:: { - "nuttx.bin": "0x40000000" + "nuttx.bin": "0x40000000", + "board.dtb": "0x41ec0000" } Load the application over serial with:: diff --git a/Documentation/platforms/risc-v/litex/cores/vexriscv_smp/index.rst b/Documentation/platforms/risc-v/litex/cores/vexriscv_smp/index.rst index aa515c9781e21..1ceb8cb578ea1 100644 --- a/Documentation/platforms/risc-v/litex/cores/vexriscv_smp/index.rst +++ b/Documentation/platforms/risc-v/litex/cores/vexriscv_smp/index.rst @@ -45,6 +45,7 @@ Create a file, 'boot.json' in the Nuttx root directory, with the following conte { "romfs.img": "0x40C00000", "nuttx.bin": "0x40000000", + "board.dtb": "0x41ec0000", "opensbi.bin": "0x40f00000" } diff --git a/Documentation/platforms/risc-v/litex/index.rst b/Documentation/platforms/risc-v/litex/index.rst index 939d8257c4d68..2fd6c74d89f9a 100644 --- a/Documentation/platforms/risc-v/litex/index.rst +++ b/Documentation/platforms/risc-v/litex/index.rst @@ -59,6 +59,26 @@ the source can be obtained from https://github.com/riscv-collab/riscv-gnu-toolch Check the linked github repository for other options, including building with multilib enabled. +Device tree support +========================= + +Currently, the litex port requires that the memory mapped peripheral addresses and IRQ numbers +match those generated by LiteX. Although, this approach is being phased-out in favour of +using a flattened device tree (FDT) to dynamically instantiate drivers. + +Generating and compiling the device tree:: + + $ ./litex/tools/litex_json2dts_linux.py path/to/built/gateware/csr.json > board.dts + $ dtc -@ -I dts -O dtb board.dts -o board.dtb + +Ensure the board.dtb is placed in the NuttX root directory. + +If a peripheral isn't working with the LiteX generated gateware, consider checking +the addresses and IRQ numbers in + + - arch/risc-v/src/litex/hardware/litex_memorymap.h + - arch/risc-v/include/litex/irq.h + Core specific information ========================= diff --git a/Documentation/platforms/risc-v/qemu-rv/boards/rv-virt/README.txt b/Documentation/platforms/risc-v/qemu-rv/boards/rv-virt/README.txt deleted file mode 100644 index bf8a428250bd5..0000000000000 --- a/Documentation/platforms/risc-v/qemu-rv/boards/rv-virt/README.txt +++ /dev/null @@ -1,120 +0,0 @@ -1. Download and install toolchain - - $ curl https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-ubuntu14.tar.gz - -2. Build and install qemu - - $ git clone https://github.com/qemu/qemu - $ cd qemu - $ ./configure --target-list=riscv32-softmmu,riscv64-softmmu - $ make - $ sudo make install - -3.1. Configure and build NuttX for BUILD_FLAT - - $ mkdir ./nuttx; cd ./nuttx - $ git clone https://github.com/apache/nuttx.git nuttx - $ git clone https://github.com/apache/nuttx-apps.git apps - $ cd nuttx - $ make distclean - $ ./tools/configure.sh rv-virt:nsh - $ make V=1 -j7 - -3.2 Configure and build NuttX for BUILD_KERNEL, 64-bit or 32-bit - - $ mkdir ./nuttx; cd ./nuttx - $ git clone https://github.com/apache/nuttx.git nuttx - $ git clone https://github.com/apache/nuttx-apps.git apps - $ cd nuttx - $ make distclean - $ # For 64-bit build. - $ ./tools/configure.sh rv-virt:knsh64 - $ # For 32-bit build. - $ ./tools/configure.sh rv-virt:knsh32 - $ make V=1 -j7 - $ make export V=1 - $ cd ../apps - $ ./tools/mkimport.sh -z -x ../nuttx/nuttx-export-*.tar.gz - $ make import V=1 - $ cd ../nuttx - -4. Run the nuttx with qemu - - $ qemu-system-riscv32 -semihosting -M virt,aclint=on -cpu rv32 -smp 8 -bios none -kernel nuttx -nographic - - or - - $ qemu-system-riscv64 -semihosting -M virt,aclint=on -cpu rv64 -smp 8 -bios none -kernel nuttx -nographic - - NuttShell (NSH) NuttX-10.3.0-RC1 - nsh> mount -t hostfs -o fs=. /host - nsh> cat /host/AUTHORS - This is a list of all the contributors that have submitted ICLA, SGA - If you are not on this list and believe you should be, please inform us. - - ICLA - ==== - ... - nsh> - -4. Run the virtio network, block, serial and rng driver with qemu - - $ dd if=/dev/zero of=./mydisk-1gb.img bs=1M count=1024 - - $ qemu-system-riscv32 -semihosting -M virt,aclint=on -cpu rv32 -smp 8 \ - -global virtio-mmio.force-legacy=false \ - -device virtio-serial-device,bus=virtio-mmio-bus.0 \ - -chardev socket,telnet=on,host=127.0.0.1,port=3450,server=on,wait=off,id=foo \ - -device virtconsole,chardev=foo \ - -device virtio-rng-device,bus=virtio-mmio-bus.1 \ - -netdev user,id=u1,hostfwd=tcp:127.0.0.1:10023-10.0.2.15:23,hostfwd=tcp:127.0.0.1:15001-10.0.2.15:5001 \ - -device virtio-net-device,netdev=u1,bus=virtio-mmio-bus.2 \ - -drive file=./mydisk-1gb.img,if=none,format=raw,id=hd \ - -device virtio-blk-device,bus=virtio-mmio-bus.3,drive=hd \ - -bios none -kernel ./nuttx/nuttx -nographic - - or - - $ qemu-system-riscv64 -semihosting -M virt,aclint=on -cpu rv64 -smp 8 \ - -global virtio-mmio.force-legacy=false \ - -device virtio-serial-device,bus=virtio-mmio-bus.0 \ - -chardev socket,telnet=on,host=127.0.0.1,port=3450,server=on,wait=off,id=foo \ - -device virtconsole,chardev=foo \ - -device virtio-rng-device,bus=virtio-mmio-bus.1 \ - -netdev user,id=u1,hostfwd=tcp:127.0.0.1:10023-10.0.2.15:23,hostfwd=tcp:127.0.0.1:15001-10.0.2.15:5001 \ - -device virtio-net-device,netdev=u1,bus=virtio-mmio-bus.2 \ - -drive file=./mydisk-1gb.img,if=none,format=raw,id=hd \ - -device virtio-blk-device,bus=virtio-mmio-bus.3,drive=hd \ - -bios none -kernel ./nuttx/nuttx -nographic - -5. Run the virtio gpu driver with qemu and test fb demo - $ # For 32-bit build. - $ ./tools/configure.sh rv-virt:fb - $ make -j - $ qemu-system-riscv32 -semihosting -M virt -cpu rv32 -smp 8 \ - -chardev stdio,id=con,mux=on \ - -serial chardev:con \ - -device virtio-gpu-device,xres=640,yres=480,bus=virtio-mmio-bus.0 \ - -mon chardev=con,mode=readline \ - -bios none -kernel nuttx - - NuttShell (NSH) NuttX-10.4.0 - nsh> fb - - $ # For 64-bit build. - $ ./tools/configure.sh rv-virt:fb64 - $ make -j - $ qemu-system-riscv64 -semihosting -M virt -cpu rv64 -smp 8 \ - -chardev stdio,id=con,mux=on \ - -serial chardev:con \ - -device virtio-gpu-device,xres=640,yres=480,bus=virtio-mmio-bus.0 \ - -mon chardev=con,mode=readline \ - -bios none -kernel nuttx - - NuttShell (NSH) NuttX-10.4.0 - nsh> fb - -6. TODO - - Support FPU - Support RISC-V User mode diff --git a/Documentation/platforms/risc-v/qemu-rv/boards/rv-virt/index.rst b/Documentation/platforms/risc-v/qemu-rv/boards/rv-virt/index.rst index 32ced5adb67ea..413294dd48f02 100644 --- a/Documentation/platforms/risc-v/qemu-rv/boards/rv-virt/index.rst +++ b/Documentation/platforms/risc-v/qemu-rv/boards/rv-virt/index.rst @@ -2,5 +2,384 @@ rv-virt ======= -.. include:: README.txt - :literal: +RISC-V Toolchain +================ + +Any generic RISC-V toolchain can be used. It's recommended to use the same toolchain used by NuttX CI. + +Please refer to the `Docker container `_ and +check for the current compiler version being used. For instance: + +.. code-block:: + + ############################################################################### + # Build image for tool required by RISCV builds + ############################################################################### + FROM nuttx-toolchain-base AS nuttx-toolchain-riscv + # Download the latest RISCV GCC toolchain prebuilt by xPack + RUN mkdir riscv-none-elf-gcc && \ + curl -s -L "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz" \ + | tar -C riscv-none-elf-gcc --strip-components 1 -xz + +It uses the xPack's prebuilt toolchain based on GCC 13.2.0-2. + +RISC-V QEMU +=========== + +Build and install ``qemu``:: + + $ git clone https://github.com/qemu/qemu + $ cd qemu + $ ./configure --target-list=riscv32-softmmu,riscv64-softmmu + $ make + $ sudo make install + +QEMU 7.2.9 or later and OpenSBI v1.1 or later (usually shipped with QEMU) is required, to support RISC-V "Sstc" Extension. It is also recommended to use the latest QEMU and OpenSBI. + +For users who wish to use their own OpenSBI, please refer to `OpenSBI repository `_. + +Configurations +============== + +All of the configurations presented below can be tested by running the following commands:: + + $ ./tools/configure.sh rv-virt: + +Where is the name of the configuration you want to use, i.e.: nsh, knsh32, knsh64... + +To build it, run the following command:: + + $ make -j$(nproc) + +or, with more verbosity:: + + $ make V=1 -j$(nproc) + +.. warning:: + Some configurations require additional steps to be built. Please refer to the specific + configurations to check it out + +Finally, to run it, use the following command: + +For 32-bit configurations:: + + $ qemu-system-riscv32 -semihosting -M virt,aclint=on -cpu rv32 -smp 8 -bios none -kernel nuttx -nographic + +And, for 64-bit configurations:: + + $ qemu-system-riscv64 -semihosting -M virt,aclint=on -cpu rv64 -smp 8 -bios none -kernel nuttx -nographic + +If testing with kernel build, remove the ``-bios none`` option. Kernel build +requires SBI to function properly. + +citest +------ + +This configuration is the default configuration intended to be used by the automated +testing on CI of 32-bit RISC-V using QEMU. + +To run it with QEMU, use the following command:: + + $ qemu-system-riscv32 -semihosting -M virt -cpu rv32 \ + -drive index=0,id=userdata,if=none,format=raw,file=./fatfs.img \ + -device virtio-blk-device,bus=virtio-mmio-bus.0,drive=userdata \ + -bios none -kernel nuttx -nographic + +To run the CI scripts, use the following command:: + + $ ./nuttx/boards/risc-v/qemu-rv/rv-virt/configs/citest/run + +citest64 +-------- + +Identical to the `citest`_ configuration, but for 64-bit RISC-V. + +fb +-- + +Uses the VirtIO GPU driver to run the `fb` demo application on 32-bit RISC-V. + +To run it with QEMU, use the following command:: + + $ qemu-system-riscv32 -semihosting -M virt -cpu rv32 -smp 8 \ + -chardev stdio,id=con,mux=on \ + -serial chardev:con \ + -device virtio-gpu-device,xres=640,yres=480,bus=virtio-mmio-bus.0 \ + -mon chardev=con,mode=readline \ + -bios none -kernel nuttx + +fb64 +---- + +Identical to the `fb`_ configuration, but for 64-bit RISC-V. + +To run it with QEMU, use the following command:: + + $ qemu-system-riscv64 -semihosting -M virt -cpu rv64 -smp 8 \ + -chardev stdio,id=con,mux=on \ + -serial chardev:con \ + -device virtio-gpu-device,xres=640,yres=480,bus=virtio-mmio-bus.0 \ + -mon chardev=con,mode=readline \ + -bios none -kernel nuttx + +knetnsh64 +--------- + +Similar to the `knsh32`_ configuration, but with networking support and 64-bit RISC-V. + +To run it with QEMU, use the following command:: + + $ dd if=/dev/zero of=./mydisk-1gb.img bs=1M count=1024 + + $ qemu-system-riscv64 -semihosting -M virt,aclint=on -cpu rv64 -smp 8 \ + -global virtio-mmio.force-legacy=false \ + -device virtio-serial-device,bus=virtio-mmio-bus.0 \ + -chardev socket,telnet=on,host=127.0.0.1,port=3450,server=on,wait=off,id=foo \ + -device virtconsole,chardev=foo \ + -device virtio-rng-device,bus=virtio-mmio-bus.1 \ + -netdev user,id=u1,hostfwd=tcp:127.0.0.1:10023-10.0.2.15:23,hostfwd=tcp:127.0.0.1:15001-10.0.2.15:5001 \ + -device virtio-net-device,netdev=u1,bus=virtio-mmio-bus.2 \ + -drive file=./mydisk-1gb.img,if=none,format=raw,id=hd \ + -device virtio-blk-device,bus=virtio-mmio-bus.3,drive=hd \ + -kernel ./nuttx/nuttx -nographic + +knetnsh64_smp +------------- + +Similar to the `knetnsh64`_ configuration, but with SMP support for 64-bit RISC-V. + +knsh32 +------ + +This is similar to the `nsh`_ configuration except that NuttX +is built as a kernel-mode, monolithic module, and the user applications +are built separately. It uses `hostfs` and QEMU in semi-hosting mode to +load the user-space applications. This is intended to 32-bit RISC-V. + +To build it, use the following command:: + + $ make V=1 -j$(nproc) + $ make export V=1 -j$(nproc) + $ pushd ../apps + $ ./tools/mkimport.sh -z -x ../nuttx/nuttx-export-*.tar.gz + $ make import V=1 -j$(nproc) + $ popd + +Run it with QEMU using the default command for 32-bit RISC-V. + +In `nsh`, applications can be run from the `/system/bin` directory:: + + nsh> /system/bin/hello + +.. _knsh32_paging: + +knsh32_paging +------------- + +Similar to ``knsh32_romfs``, but enabling on-demand paging: this +configuration simulates a 4MiB device (using QEMU), but sets the number of +heap pages equal to ``CONFIG_ARCH_HEAP_NPAGES=2048``. This means that each +process's heap is 8MiB, whereas ``CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE`` is +``1048576`` (1MiB) represents the stack size of the processes (which is +allocated from the process's heap). This configuration is used for 32-bit +RISC-V which implements the Sv32 MMU specification and enables processes +to have their own address space larger than the available physical memory. +This is particularly useful for implementing a set of programming language +interpreters. + +knsh32_romfs +------------ + +Similar to the `knsh32`_ configuration, but uses ROMFS instead of `hostfs`. +A ROMFS image is generated and linked to the kernel. This requires re-running ``make``:: + + $ make V=1 -j$(nproc) + $ make export V=1 -j$(nproc) + $ pushd ../apps + $ ./tools/mkimport.sh -z -x ../nuttx/nuttx-export-*.tar.gz + $ make import V=1 -j$(nproc) + $ ./tools/mkromfsimg.sh ../nuttx/arch/risc-v/src/board/romfs_boot.c + $ popd + $ make V=1 -j$(nproc) + +To run it, use the following command:: + + $ qemu-system-riscv32 -M virt,aclint=on -cpu rv32 -smp 8 -kernel nuttx -nographic + +In `nsh`, applications can be run from the `/system/bin` directory:: + + nsh> /system/bin/hello + +knsh64 +------ + +Similar to the `knsh32`_ configuration, but for 64-bit RISC-V. + +Run it with QEMU using the default command for 64-bit RISC-V. + +In `nsh`, applications can be run from the `/system/bin` directory:: + + nsh> /system/bin/hello + +ksmp64 +------ + +Identical to the `knsh64`_ configuration but with SMP support. + +netnsh +------ + +Similar to the `nsh`_ configuration, but with networking support for 32-bit RISC-V. + +To run it with QEMU, use the following command:: + + $ dd if=/dev/zero of=./mydisk-1gb.img bs=1M count=1024 + + $ qemu-system-riscv32 -semihosting -M virt,aclint=on -cpu rv32 -smp 8 \ + -global virtio-mmio.force-legacy=false \ + -device virtio-serial-device,bus=virtio-mmio-bus.0 \ + -chardev socket,telnet=on,host=127.0.0.1,port=3450,server=on,wait=off,id=foo \ + -device virtconsole,chardev=foo \ + -device virtio-rng-device,bus=virtio-mmio-bus.1 \ + -netdev user,id=u1,hostfwd=tcp:127.0.0.1:10023-10.0.2.15:23,hostfwd=tcp:127.0.0.1:15001-10.0.2.15:5001 \ + -device virtio-net-device,netdev=u1,bus=virtio-mmio-bus.2 \ + -drive file=./mydisk-1gb.img,if=none,format=raw,id=hd \ + -device virtio-blk-device,bus=virtio-mmio-bus.3,drive=hd \ + -bios none -kernel ./nuttx/nuttx -nographic + +netnsh64 +-------- + +Similar to the `netnsh`_ configuration, but for 64-bit RISC-V. + +To run it with QEMU, use the following command:: + + $ dd if=/dev/zero of=./mydisk-1gb.img bs=1M count=1024 + + $ qemu-system-riscv64 -semihosting -M virt,aclint=on -cpu rv64 -smp 8 \ + -global virtio-mmio.force-legacy=false \ + -device virtio-serial-device,bus=virtio-mmio-bus.0 \ + -chardev socket,telnet=on,host=127.0.0.1,port=3450,server=on,wait=off,id=foo \ + -device virtconsole,chardev=foo \ + -device virtio-rng-device,bus=virtio-mmio-bus.1 \ + -netdev user,id=u1,hostfwd=tcp:127.0.0.1:10023-10.0.2.15:23,hostfwd=tcp:127.0.0.1:15001-10.0.2.15:5001 \ + -device virtio-net-device,netdev=u1,bus=virtio-mmio-bus.2 \ + -drive file=./mydisk-1gb.img,if=none,format=raw,id=hd \ + -device virtio-blk-device,bus=virtio-mmio-bus.3,drive=hd \ + -bios none -kernel ./nuttx/nuttx -nographic + +netnsh64_smp +------------ + +Similar to the `netnsh64`_ configuration, but with SMP support for 64-bit RISC-V. + +To run it with QEMU, use the following command:: + + $ dd if=/dev/zero of=./mydisk-1gb.img bs=1M count=1024 + + $ qemu-system-riscv64 -semihosting -M virt,aclint=on -cpu rv64 -smp 8 \ + -global virtio-mmio.force-legacy=false \ + -device virtio-serial-device,bus=virtio-mmio-bus.0 \ + -chardev socket,telnet=on,host=127.0.0.1,port=3450,server=on,wait=off,id=foo \ + -device virtconsole,chardev=foo \ + -device virtio-rng-device,bus=virtio-mmio-bus.1 \ + -netdev user,id=u1,hostfwd=tcp:127.0.0.1:10023-10.0.2.15:23,hostfwd=tcp:127.0.0.1:15001-10.0.2.15:5001 \ + -device virtio-net-device,netdev=u1,bus=virtio-mmio-bus.2 \ + -drive file=./mydisk-1gb.img,if=none,format=raw,id=hd \ + -device virtio-blk-device,bus=virtio-mmio-bus.3,drive=hd \ + -bios none -kernel ./nuttx/nuttx -nographic + +netnsh_smp +---------- + +Similar to the `netnsh`_ configuration, but with SMP support for 32-bit RISC-V. + +To run it with QEMU, use the following command:: + + $ dd if=/dev/zero of=./mydisk-1gb.img bs=1M count=1024 + + $ qemu-system-riscv32 -semihosting -M virt,aclint=on -cpu rv32 -smp 8 \ + -global virtio-mmio.force-legacy=false \ + -device virtio-serial-device,bus=virtio-mmio-bus.0 \ + -chardev socket,telnet=on,host=127.0.0.1,port=3450,server=on,wait=off,id=foo \ + -device virtconsole,chardev=foo \ + -device virtio-rng-device,bus=virtio-mmio-bus.1 \ + -netdev user,id=u1,hostfwd=tcp:127.0.0.1:10023-10.0.2.15:23,hostfwd=tcp:127.0.0.1:15001-10.0.2.15:5001 \ + -device virtio-net-device,netdev=u1,bus=virtio-mmio-bus.2 \ + -drive file=./mydisk-1gb.img,if=none,format=raw,id=hd \ + -device virtio-blk-device,bus=virtio-mmio-bus.3,drive=hd \ + -bios none -kernel ./nuttx/nuttx -nographic + +nsh +--- + +Configures the NuttShell (nsh) located at examples/nsh. This NSH +configuration is focused on low-level, command-line driver testing. +This configuration is used for 32-bit RISC-V + +nsh64 +----- + +Identical to the `nsh`_ configuration, but for 64-bit RISC-V. + +smp +--- + +Similar to the `nsh`_ configuration, but with SMP support. +This configuration is used for 32-bit RISC-V + +smp64 +----- + +Similar to the `nsh`_ configuration, but with SMP support +This configuration is used for 64-bit RISC-V + +RISC-V GDB Debugging +==================== + +First of all, make sure to select ``CONFIG_DEBUG_SYMBOLS=y`` in `menuconfig`. + +After building the kernel (and the applications, in kernel mode), use the toolchain's GDB +to debug RISC-V applications. For instance, if you are using the xPack's prebuilt toolchain, +you can use the following command to start GDB:: + + $ riscv-none-elf-gdb-py3 -ix tools/gdb/__init__.py --tui nuttx + +To use QEMU for debugging, one should add the parameters ``-s -S`` to the QEMU command line. + +For instance:: + + $ qemu-system-riscv32 -semihosting -M virt,aclint=on -cpu rv32 -smp 8 -bios none -kernel nuttx -nographic -s -S + +Then, in GDB, use the following command to connect to QEMU:: + + $ target extended-remote localhost:1234 + +Debugging Applications in Kernel Mode +------------------------------------- + +In kernel mode, only the kernel symbols are loaded by default. + +If needed, one should also load the application symbols using the following command:: + + $ add-symbol-file
+ +``address`` refers to the ``.text`` section of the application and can be retrieved from the ELF file using the following command:: + + $ riscv-none-elf-readelf -WS | grep .text + +For instance, to check the ``.text`` section address of the ``hello`` application, use the following command:: + + $ riscv-none-elf-readelf -WS ../apps/bin/hello | grep .text + [ 1] .text PROGBITS c0000000 001000 0009e0 00 AX 0 0 2 + +.. note:: Pay attention that ``riscv-none-elf-readelf`` refers to your toolchain's readelf utility. Adjust accordingly if you are + using a different toolchain. + +Then, look for the ``.text`` section address and use the ``c0000000`` as the address to load the symbols. + +For instance, if you want to load the ``hello`` application, you can use the following command in GDB:: + + $ add-symbol-file ../apps/bin/hello 0xc0000000 + +Then, you can set breakpoints, step through the code, and inspect the memory and registers of the applications too. diff --git a/Documentation/platforms/sim/sim/boards/sim/README.txt b/Documentation/platforms/sim/sim/boards/sim/README.txt index 55ffc088e842a..cc1100011b0f0 100644 --- a/Documentation/platforms/sim/sim/boards/sim/README.txt +++ b/Documentation/platforms/sim/sim/boards/sim/README.txt @@ -5,7 +5,7 @@ README -------- This directory contains logic to support a custom ROMFS system-init script and start-up script. These scripts are used by by the NSH when it starts - provided that CONFIG_NSH_ARCHROMFS=y. These scripts provide a ROMFS volume + provided that CONFIG_ETC_ROMFS=y. These scripts provide a ROMFS volume that will be mounted at /etc and will look like this at run-time: NuttShell (NSH) NuttX-7.31 diff --git a/Documentation/platforms/sim/sim/boards/sim/index.rst b/Documentation/platforms/sim/sim/boards/sim/index.rst index d5c5efa6868da..472bfdabfd186 100644 --- a/Documentation/platforms/sim/sim/boards/sim/index.rst +++ b/Documentation/platforms/sim/sim/boards/sim/index.rst @@ -692,6 +692,7 @@ NOTES running C++ static initializers until NuttX has been initialized. fb +-- A simple configuration used for some basic (non-graphic) debug of the framebuffer character drivers using apps/examples/fb. @@ -1043,7 +1044,7 @@ NOTES @@ -117,7 +117,8 @@ /* Execute the startup script */ - #ifdef CONFIG_NSH_ROMFSETC + #ifdef CONFIG_ETC_ROMFS - nsh_script(&pstate->cn_vtbl, "init", NSH_INITPATH); +// REMOVE ME +// nsh_script(&pstate->cn_vtbl, "init", NSH_INITPATH); @@ -1115,14 +1116,14 @@ rpproxy and rpserver rpserver: Remote master(host) server process. rpserver contains all the real hardware configuration, such as: - 1.Universal Asynchronous Receiver/Transmitter (UART). - 2.Specific File System. - 3.Network protocol stack and real network card device. - 4.... + 1. Universal Asynchronous Receiver/Transmitter (UART). + 2. Specific File System. + 3. Network protocol stack and real network card device. + 4. ... Rpmsg driver used in this example include: -1.Rpmsg Syslog +1. Rpmsg Syslog Source:: @@ -1250,6 +1251,8 @@ To use this example: 1 1 224 FIFO Kthread --- Waiting Signal 00000000 002032 hpwork 3 3 100 FIFO Task --- Running 00000000 004080 init + To switch back the console, type ``"~."`` in the cu session. + 3. RpmsgFS: Mount the remote file system via RPMSGFS, cu to proxy first:: @@ -1371,6 +1374,33 @@ and 32-bit modules. This has apps/examples/sotest enabled. This configuration is intended for 64-bit host OS. +sqlite +------- + +This configuration is used to test sqlite. Since hostfs does not support +FIOC_FILEPATH, it cannot currently be used in hostfs. + +Basic usage example:: + + nsh> cd tmp + nsh> sqlite3 test.db + SQLite version 3.45.1 2024-01-30 16:01:20 + Enter ".help" for usage hints. + sqlite> + CREATE TABLE COMPANY( + ID INT PRIMARY KEY sqlite> (x1...> NOT NULL, + NAME TEXT NOT NULL, + AGE (x1...> (x1...> INT NOT NULL, + ADDRESS CHAR(50), + SALARY (x1...> (x1...> REAL + );(x1...> + sqlite> .quit + sqlite> + nsh> + nsh> ls -l + /tmp: + -rwxrwxrwx 12288 test.db + tcploop ------- @@ -1679,7 +1709,7 @@ This is a configuration with sim usbdev support. Then you can use commands such as adb shell, adb push, adb pull as normal. 2> Run RNDIS: - + NuttX enter command:: $ conn 0 diff --git a/Documentation/platforms/tricore/index.rst b/Documentation/platforms/tricore/index.rst new file mode 100644 index 0000000000000..d0cf6d644df7c --- /dev/null +++ b/Documentation/platforms/tricore/index.rst @@ -0,0 +1,41 @@ +======= +TriCore +======= + +All TriCore source reside in lower-level common, chip-specific, and architecture-specific +directories. + +arch/tricore/src/common/ Directory +================================== + +This directory holds source files common to all TriCore architectures. + +Architecture-Specific Directories +================================= + +Architecture-specific directories hold common source files shared for by +implementations of specific TriCore architectures. + +``TriCore`` + This directory holds logic appropriate for any instantiation of the 32-bit + TriCore architecture. + +Chip-Specific directories +========================= + +For SoC chips, in particular, on-chip devices and differing interrupt +structures may require special, chip-specific definitions in these chip- +specific directories. + +The core Chip implementation is based on Infineon Low Level Drivers (iLLDs). +The unified API is more friendly to developers familiar with Infineon SDK/HAL. +We can get more code examples on Infineon's official Github: `AURIX_code_examples `__ + +``TC3xx`` + This is the implementation of NuttX on the Infineon’s AURIX™- TC3xx microcontroller family. + +.. toctree:: + :maxdepth: 1 + :glob: + + */* diff --git a/Documentation/platforms/tricore/tc397/boards/kit_a2g_tc397_tft/index.rst b/Documentation/platforms/tricore/tc397/boards/kit_a2g_tc397_tft/index.rst new file mode 100644 index 0000000000000..a7abe66b38e0e --- /dev/null +++ b/Documentation/platforms/tricore/tc397/boards/kit_a2g_tc397_tft/index.rst @@ -0,0 +1,61 @@ +================= +KIT_A2G_TC397_TFT +================= + +This page file describes the contents of the build configurations available +for the NuttX TriCore port. + +Infineon’s AURIX™- TC3xx `KIT_A2G_TC397_TFT `__ Board +===================================================================================================================================== + +This port should work on KIT_A2G_TC397_TFT with a proper CPU. +The mandatory CPU features are: + +* System Timer (STM) +* Asynchronous Serial Interface(ASCLIN) UART +* IRQs are managed by Interrupt Router(INT), IR Service Request Control Registers(SRC). + +Toolchains +========== + +Currently, only the Infineon’s AURIX™ Tasking toolchain is tested. + +Configurations +============== + +Common Configuration Notes +-------------------------- + +1. Each Tricore TC397 configuration is maintained in a sub-directory + and can be selected as follow:: + + tools/configure.sh tc397: + + Where ```` is one of the configuration sub-directories described in + the following paragraph. + + NuttX Shell:: + + tools/configure.sh tc397:nsh + +2. These configurations use the mconf-based configuration tool. To + change a configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. + + b. Execute ``make menuconfig`` in nuttx/ in order to start the + reconfiguration process. + +3. By default, all configurations assume the Linux. This is easily + reconfigured:: + + CONFIG_HOST_LINUX=y + +Configuration Sub-Directories +----------------------------- + +ostest +------ + +The "standard" NuttX examples/ostest configuration. diff --git a/Documentation/platforms/tricore/tc397/index.rst b/Documentation/platforms/tricore/tc397/index.rst new file mode 100644 index 0000000000000..fa406585edbf7 --- /dev/null +++ b/Documentation/platforms/tricore/tc397/index.rst @@ -0,0 +1,23 @@ +============= +TriCore/TC397 +============= + +**TriCore/TC397** An TriCore flat address port was ported in NuttX-12.0. It +consists of the following feautres: + +- Runs in Supervisor Mode. +- IRQs are managed by Interrupt Router (INT), IR Service Request Control Registers (SRC). +- Used System timer (STM) for systick. + +This kernel with ostest have been tested with + +- Infineon's AURIX™ TC397 Evaluation Board: KIT_A2G_TC397_5V_TFT + +Supported Boards +================ + +.. toctree:: + :glob: + :maxdepth: 1 + + boards/*/* diff --git a/Documentation/platforms/x86/qemu/index.rst b/Documentation/platforms/x86/qemu/index.rst index 7ed64378df769..7088e4d90660c 100644 --- a/Documentation/platforms/x86/qemu/index.rst +++ b/Documentation/platforms/x86/qemu/index.rst @@ -13,7 +13,7 @@ examples under QEMU. The port is reported to be functional on the Lizhuoyi contributed additional keyboard and VGA drivers. This is a great, stable starting point for anyone interested in fleshing out the x86 port! Refer to the NuttX -`README `__ +`README `__ file for further information. Supported Boards diff --git a/Documentation/platforms/x86_64/qemu/boards/qemu-intel64/README.txt b/Documentation/platforms/x86_64/qemu/boards/qemu-intel64/README.txt deleted file mode 100644 index b76337c675f45..0000000000000 --- a/Documentation/platforms/x86_64/qemu/boards/qemu-intel64/README.txt +++ /dev/null @@ -1,184 +0,0 @@ -README -====== - -This README file describes the contents of the build configurations available -for the NuttX QEMU x86_64 port. - -Contents -======== - - * Creating a bootable disk - * QEMU/KVM - - Running QEMU/KVM - * Bochs - - Building Bochs - - Running Bochs - * Real machine - * Toolchain - * FAQ - * Configurations - - ostest - -Creating a bootable disk -======================== - -This build supports multiboot2, which means that usual multiboot2 bootlaoders, e.g. grub can be used. -To create a bootable disk with grub2, create a directory named `iso` with grub configuration file and the compiled nuttx.elf. - -##### Directory and file hierarchy -``` - - iso/ - - boot/ - - grub/ - - grub.cfg - - nuttx.elf -``` - -##### grub.cfg - -The grub.cfg should contain the boot entry of NuttX. -``` -set timeout=0 -set default=0 -menuentry "kernel" { - multiboot2 /boot/nuttx.elf -} -``` - -##### Making the disk - -Use the following command to create the disk. -P.S. In some distros, `grub-mkrescue` is called `grub2-mkrescue` -``` -grub-mkrescue -o boot.iso iso -``` - -QEMU/KVM -==== - -QEMU is a generic and open source machine emulator and virtual machine. Here are -some links (which will probably be mostly outdated by the time your read this): - - Home Page: http://wiki.qemu.org/Main_Page - Downloads: http://wiki.qemu.org/Download - Documentation: http://wiki.qemu.org/Manual - -KVM is the Linux kernel hypervisor. -It supports creations of virtual machines in Linux systems. -It is usually coupled with Qemu as its I/O supporting layer. - -The qemu can be build from source or downloaded from distro repositories. -However, a modern CPU and KVM support are mandatory because the X2APIC is not available -in pure emulator mode. -This mean using this build with qemu in windows or old x86 machine can be frustrating. -In such case, looks the next section and use bochs emulator instead. - -Running QEMU ------------- - - In the top-level NuttX directory: - - qemu-system-x86_64 -cpu host -enable-kvm -m 2G -cdrom boot.iso -nographic -serial mon:stdio - - This multiplex the qemu console and COM1 to your console. - Use control-a 1 and 2 to switch between. - Use control-a x to terminate the emulation. - - P.S. Make sure that you CPU supports the mandatory features. Look at Real machine - section for more information. - -Bochs -===== - -Bochs is also a generic and open source machine emulator and virtualizer. -It does very comprehensive emulation of x86 platform, even the state-of-art processors. -Here are some links (which will probably be mostly outdated by the time your read this): - - Home Page: http://bochs.sourceforge.net - -The bochs can be build from source. -Unlike qemu, it does not rely on KVM to support modern hardware features, therefore it can -also be used under Windows. -When building bochs, remember to enable x86-64 support with "--enable-x86-64". -If you also want support for SIMD instructions, enable them with "--enable-avx --enable-evex". - -Running Bochs ------------- - - First edit/check the .bochsrc - You can create one in the top-level NuttX directory or bochs will use the one in your $HOME. - Remember to change the CPU model to one with mandatory features and enable the COM port. - - * Find and edit (You might adjust the IPS as you machine perform): - ``` - cpu: model=broadwell_ult, count=1, ips=50000000, reset_on_triple_fault=0, ignore_bad_msrs=0, msrs="msrs.def" a - ata0-master: type=cdrom, path="", status=inserted - - ``` - - * Add: - ``` - com1: enabled=1, mode=file, dev=com1.out - ``` - - In the top-level NuttX directory: - - ``` - bochs - ``` - - The emulator will drop into debugger mode. - Enter 'c' to start the emulation. - COM port output will be in the com1.out file. - -Real machine -============ - -This port should work on real x86-64 machine with a proper CPU. -The mandatory CPU features are: - * TSC DEADLINE or APIC timer - * PCID - * X2APIC - -WARNING: IF you use TSC DEADLINE, make sure that your CPU's TSC DEADLINE timer is not buggy! - -Toolchains -========== - - Currently, only the Linux GCC toolchain is tested. - While building on a modern x86_64 PC, the default system GCC can be used. - -Configurations -============== - -Common Configuration Notes --------------------------- - - 1. Each Qemu-intel64 configuration is maintained in a sub-directory - and can be selected as follow: - - tools/configure.sh qemu-intel64: - - Where is one of the configuration sub-directories described in - the following paragraph. - - 2. These configurations use the mconf-based configuration tool. To - change a configurations using that tool, you should: - - a. Build and install the kconfig-mconf tool. See nuttx/README.txt - see additional README.txt files in the NuttX tools repository. - - b. Execute 'make menuconfig' in nuttx/ in order to start the - reconfiguration process. - - 3. By default, all configurations assume the Linux. This is easily - reconfigured: - - CONFIG_HOST_LINUX=y - -Configuration Sub-Directories ------------------------------ - - ostest - - The "standard" NuttX examples/ostest configuration. diff --git a/Documentation/platforms/x86_64/qemu/boards/qemu-intel64/index.rst b/Documentation/platforms/x86_64/qemu/boards/qemu-intel64/index.rst index 04bcc426cebda..c927ad922a7eb 100644 --- a/Documentation/platforms/x86_64/qemu/boards/qemu-intel64/index.rst +++ b/Documentation/platforms/x86_64/qemu/boards/qemu-intel64/index.rst @@ -2,6 +2,192 @@ qemu-intel64 ============ -.. include:: README.txt - :literal: +This page file describes the contents of the build configurations available +for the NuttX QEMU x86_64 port. +Creating a bootable disk +======================== + +This build supports multiboot2, which means that usual multiboot2 bootlaoders, +e.g. grub can be used. To create a bootable disk with grub2, create a directory +named ``iso`` with grub configuration file and the compiled ``nuttx.elf``. + +Directory and file hierarchy:: + + - iso/ + - boot/ + - grub/ + - grub.cfg + - nuttx.elf + +The grub.cfg should contain the boot entry of NuttX:: + + set timeout=0 + set default=0 + menuentry "kernel" { + multiboot2 /boot/nuttx.elf + } + +Making the disk +--------------- + +Use the following command to create the disk. +P.S. In some distros, ``grub-mkrescue`` is called ``grub2-mkrescue``:: + + grub-mkrescue -o boot.iso iso + +Grub with UEFI +-------------- + +This flow is very similar except you need to have the BOOTX64.EFI file. +You can find this in most Linux distributions:: + + iso/ + └── boot + ├── efi + │ └── EFI + │ └── BOOT + │ └── BOOTX64.EFI + ├── grub + │ └── grub.cfg + └── nuttx.elf + +QEMU/KVM +======== + +QEMU is a generic and open source machine emulator and virtual machine. Here are +some links (which will probably be mostly outdated by the time your read this): + +* Home Page: http://wiki.qemu.org/Main_Page +* Downloads: http://wiki.qemu.org/Download +* Documentation: http://wiki.qemu.org/Manual + +KVM is the Linux kernel hypervisor. +It supports creations of virtual machines in Linux systems. +It is usually coupled with Qemu as its I/O supporting layer. + +The qemu can be build from source or downloaded from distro repositories. +However, a modern CPU and KVM support are mandatory because the X2APIC is not +available in pure emulator mode. +This mean using this build with qemu in windows or old x86 machine can be +frustrating. In such case, looks the next section and use bochs emulator instead. + +Running QEMU +------------ + +In the top-level NuttX directory:: + + qemu-system-x86_64 -cpu host -enable-kvm -m 2G -cdrom boot.iso -nographic -serial mon:stdio + +This multiplex the qemu console and COM1 to your console. + +Use control-a 1 and 2 to switch between. +Use control-a x to terminate the emulation. + +P.S. Make sure that you CPU supports the mandatory features. Look at Real machine +section for more information. + +For testing the PCI bus and driver layers. This QEMU configuration can be used +with the pcitest NuttX configuration:: + + qemu-system-x86_64 -cpu host,+pcid,+x2apic,+tsc-deadline,+xsave,+rdrand --enable-kvm -smp 1 -m 2G -cdrom boot.iso --nographic -s -no-reboot -device edu -device pci-testdev + +This will enable the QEMU pci-test and edu PCI test devices which test PIO, MMIO, IRQ, and DMA +functions. Additionally it will show detailed information about the enumeration of the PCI bus. + +If you want to boot using UEFI and TianoCore you will need to add a flag like this to +point at OVMF ``--bios /usr/share/edk2/ovmf/OVMF_CODE.fd`` + +Bochs +===== + +Bochs is also a generic and open source machine emulator and virtualizer. +It does very comprehensive emulation of x86 platform, even the state-of-art processors. +Here are some links (which will probably be mostly outdated by the time your read this): + +* Home Page: http://bochs.sourceforge.net + +The bochs can be build from source. +Unlike qemu, it does not rely on KVM to support modern hardware features, +therefore it can also be used under Windows. +When building bochs, remember to enable x86-64 support with ``--enable-x86-64``. +If you also want support for SIMD instructions, enable them with ``--enable-avx --enable-evex``. + +Running Bochs +------------- + +First edit/check the ``.bochsrc`` +You can create one in the top-level NuttX directory or bochs will use the one in your $HOME. +Remember to change the CPU model to one with mandatory features and enable the COM port. + +* Find and edit (You might adjust the IPS as you machine perform):: + + cpu: model=broadwell_ult, count=1, ips=50000000, reset_on_triple_fault=0, ignore_bad_msrs=0, msrs="msrs.def" + ata0-master: type=cdrom, path="", status=inserted + +* Add:: + + com1: enabled=1, mode=file, dev=com1.out + +* In the top-level NuttX directory:: + + bochs + +The emulator will drop into debugger mode. +Enter ``c`` to start the emulation. +COM port output will be in the com1.out file. + +Real machine +============ + +This port should work on real x86-64 machine with a proper CPU. +The mandatory CPU features are: + +* TSC DEADLINE or APIC timer +* PCID +* X2APIC + +WARNING: IF you use TSC DEADLINE, make sure that your CPU's TSC DEADLINE timer +is not buggy! + +Toolchains +========== + +Currently, only the Linux GCC toolchain is tested. +While building on a modern x86_64 PC, the default system GCC can be used. + +Configurations +============== + +Common Configuration Notes +-------------------------- + +1. Each Qemu-intel64 configuration is maintained in a sub-directory + and can be selected as follow:: + + tools/configure.sh qemu-intel64: + + Where ```` is one of the configuration sub-directories described in + the following paragraph. + +2. These configurations use the mconf-based configuration tool. To + change a configurations using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. + + b. Execute ``make menuconfig`` in nuttx/ in order to start the + reconfiguration process. + +3. By default, all configurations assume the Linux. This is easily + reconfigured:: + + CONFIG_HOST_LINUX=y + +Configuration Sub-Directories +----------------------------- + +ostest +------ + +The "standard" NuttX examples/ostest configuration. diff --git a/Documentation/platforms/xtensa/esp32/boards/esp32-devkitc/index.rst b/Documentation/platforms/xtensa/esp32/boards/esp32-devkitc/index.rst index d346d8ce84ae2..60fa4f7a4f10a 100644 --- a/Documentation/platforms/xtensa/esp32/boards/esp32-devkitc/index.rst +++ b/Documentation/platforms/xtensa/esp32/boards/esp32-devkitc/index.rst @@ -329,6 +329,33 @@ was successful by running ``cxxtest``:: Invalid file! /invalid File /proc/version exists! +dac +--- +This configuration enables DAC and registers a `DAC example application `_. + +.. note:: The DAC module is hard-wired to pins 25 (channel 0) and 26 + (channel 1). The default device name is ``/dev/dac0`` and can be changed in + the config menu. + +.. note:: The DAC channels in `IDF `_ are numbered ``channel 1`` (pin 25) and ``channel 2`` (pin 26). + +.. note:: Max value 255 should be close to VRef (3.3V) but it probably will not. + You can more realistically expect to get voltage around 3.09V. + +With this example you can use (not only) the following commands: + +For a multimeter, you can use the command: + +``dac -d 5000 -s 32 test`` + +For oscilloscope or anything else with tracing: + +``dac -d 0 -s 4 test`` + +For more info about the example capabilities invoke help message by typing + +``dac -h`` + efuse ----- @@ -854,7 +881,7 @@ This example uses littlefs on ESP32's SPI flash to store wasm modules. % python3 mkfsimg.py \ --img-filename ..../littlefs.bin \ - --img-size 3080192 \ + --img-size 2621440 \ --block-size 4096 \ --prog-size 256 \ --read-size 256 \ diff --git a/Documentation/platforms/xtensa/esp32/index.rst b/Documentation/platforms/xtensa/esp32/index.rst index 7a6bd10098326..dce0af96c7f29 100644 --- a/Documentation/platforms/xtensa/esp32/index.rst +++ b/Documentation/platforms/xtensa/esp32/index.rst @@ -16,16 +16,61 @@ On dual-core SoCs, the two CPUs are typically named "PRO_CPU" and "APP_CPU" (for "protocol" and "application"), however for most purposes the two CPUs are interchangeable. -Toolchain -========= +ESP32 Toolchain +================== + +The toolchain used to build ESP32 firmware can be either downloaded or built from the sources. +It is **highly** recommended to use (download or build) the same toolchain version that is being +used by the NuttX CI. + +Please refer to the Docker +`container `_ and +check for the current compiler version being used. For instance: + +.. code-block:: + + ############################################################################### + # Build image for tool required by ESP32 builds + ############################################################################### + FROM nuttx-toolchain-base AS nuttx-toolchain-esp32 + # Download the latest ESP32 GCC toolchain prebuilt by Espressif + RUN mkdir -p xtensa-esp32-elf-gcc && \ + curl -s -L "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz" \ + | tar -C xtensa-esp32-elf-gcc --strip-components 1 -xJ + + RUN mkdir -p xtensa-esp32s2-elf-gcc && \ + curl -s -L "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s2-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz" \ + | tar -C xtensa-esp32s2-elf-gcc --strip-components 1 -xJ + + RUN mkdir -p xtensa-esp32s3-elf-gcc && \ + curl -s -L "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz" \ + | tar -C xtensa-esp32s3-elf-gcc --strip-components 1 -xJ + +For ESP32, the toolchain version is based on GGC 12.2.0 (``xtensa-esp32-elf-12.2.0_20230208``) + +The prebuilt Toolchain (Recommended) +------------------------------------ + +First, create a directory to hold the toolchain: + +.. code-block:: console + + $ mkdir -p /path/to/your/toolchain/xtensa-esp32-elf-gcc + +Download and extract toolchain: + +.. code-block:: console + + $ curl -s -L "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz" \ + | tar -C xtensa-esp32-elf-gcc --strip-components 1 -xJ -You can use the prebuilt `toolchain `__ -for Xtensa architecture and `OpenOCD `__ -for ESP32 by Espressif. +Add the toolchain to your `PATH`: -For flashing firmware, you will need to install ``esptool.py`` by running:: +.. code-block:: console + + $ echo "export PATH=/path/to/your/toolchain/xtensa-esp32-elf-gcc/bin:$PATH" >> ~/.bashrc - $ pip install esptool +You can edit your shell's rc files if you don't use bash. Building from source -------------------- @@ -37,7 +82,6 @@ build the toolchain with crosstool-NG on Linux are as follows $ git clone https://github.com/espressif/crosstool-NG.git $ cd crosstool-NG - $ git checkout esp-2021r1 $ git submodule update --init $ ./bootstrap && ./configure --enable-local && make @@ -95,6 +139,7 @@ AES Yes Bluetooth Yes CAN/TWAI Yes DMA Yes +DAC Yes One-shot eFuse Yes Ethernet Yes GPIO Yes @@ -404,6 +449,13 @@ A QEMU-compatible ``nuttx.merged.bin`` binary image will be created. It can be r $ qemu-system-xtensa -nographic -machine esp32 -drive file=nuttx.merged.bin,if=mtd,format=raw +QEMU Networking +--------------- + +Networking is possible using the openeth MAC driver. Enable ``ESP32_OPENETH`` option and set the nic in QEMU: + + $ qemu-system-xtensa -nographic -machine esp32 -drive file=nuttx.merged.bin,if=mtd,format=raw -nic user,model=open_eth + Secure Boot and Flash Encryption ================================ diff --git a/Documentation/platforms/xtensa/esp32s2/boards/esp32s2-saola-1/index.rst b/Documentation/platforms/xtensa/esp32s2/boards/esp32s2-saola-1/index.rst index 36d622b138ccf..cf34262a675a5 100644 --- a/Documentation/platforms/xtensa/esp32s2/boards/esp32s2-saola-1/index.rst +++ b/Documentation/platforms/xtensa/esp32s2/boards/esp32s2-saola-1/index.rst @@ -335,6 +335,35 @@ To test it, just run ``rand`` to get 32 randomly generated bytes:: 0000 98 b9 66 a2 a2 c0 a2 ae 09 70 93 d1 b5 91 86 c8 ..f......p...... 0010 8f 0e 0b 04 29 64 21 72 01 92 7c a2 27 60 6f 90 ....)d!r..|.'`o. +rmt +--- + +This configuration configures the transmitter and the receiver of the +Remote Control Transceiver (RMT) peripheral on the ESP32-S2 using GPIOs 18 +and 2, respectively. The RMT peripheral is better explained +`here `__, +in the ESP-IDF documentation. The minimal data unit in the frame is called the +RMT symbol, which is represented by ``rmt_item32_t`` in the driver: + +.. figure:: rmt_symbol.png + :align: center + +The example ``rmtchar`` can be used to test the RMT peripheral. Connecting +these pins externally to each other will make the transmitter send RMT items +and demonstrates the usage of the RMT peripheral:: + + nsh> rmtchar + +**WS2812 addressable RGB LEDs** + +This same configuration enables the usage of the RMT peripheral and the example +``ws2812`` to drive addressable RGB LEDs:: + + nsh> ws2812 + +Please note that this board contains an on-board WS2812 LED connected to GPIO18 +and, by default, this config configures the RMT transmitter in the same pin. + rtc --- diff --git a/Documentation/platforms/xtensa/esp32s2/boards/esp32s2-saola-1/rmt_symbol.png b/Documentation/platforms/xtensa/esp32s2/boards/esp32s2-saola-1/rmt_symbol.png new file mode 100644 index 0000000000000..7f859d7c98be7 Binary files /dev/null and b/Documentation/platforms/xtensa/esp32s2/boards/esp32s2-saola-1/rmt_symbol.png differ diff --git a/Documentation/platforms/xtensa/esp32s2/index.rst b/Documentation/platforms/xtensa/esp32s2/index.rst index d61a41d088e0e..9ef5adad1934a 100644 --- a/Documentation/platforms/xtensa/esp32s2/index.rst +++ b/Documentation/platforms/xtensa/esp32s2/index.rst @@ -9,16 +9,61 @@ All embedded memory, external memory and peripherals are located on the data bus and/or the instruction bus of the CPU. Multiple peripherals in the system can access embedded memory via DMA. -Toolchain -========= +ESP32-S2 Toolchain +================== + +The toolchain used to build ESP32-S2 firmware can be either downloaded or built from the sources. +It is **highly** recommended to use (download or build) the same toolchain version that is being +used by the NuttX CI. + +Please refer to the Docker +`container `_ and +check for the current compiler version being used. For instance: + +.. code-block:: + + ############################################################################### + # Build image for tool required by ESP32 builds + ############################################################################### + FROM nuttx-toolchain-base AS nuttx-toolchain-esp32 + # Download the latest ESP32 GCC toolchain prebuilt by Espressif + RUN mkdir -p xtensa-esp32-elf-gcc && \ + curl -s -L "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz" \ + | tar -C xtensa-esp32-elf-gcc --strip-components 1 -xJ + + RUN mkdir -p xtensa-esp32s2-elf-gcc && \ + curl -s -L "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s2-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz" \ + | tar -C xtensa-esp32s2-elf-gcc --strip-components 1 -xJ + + RUN mkdir -p xtensa-esp32s3-elf-gcc && \ + curl -s -L "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz" \ + | tar -C xtensa-esp32s3-elf-gcc --strip-components 1 -xJ + +For ESP32-S2, the toolchain version is based on GGC 12.2.0 (``xtensa-esp32s2-elf-12.2.0_20230208``) + +The prebuilt Toolchain (Recommended) +------------------------------------ + +First, create a directory to hold the toolchain: -You can use the prebuilt `toolchain `__ -for Xtensa architecture and `OpenOCD `__ -for ESP32-S2 by Espressif. +.. code-block:: console + + $ mkdir -p /path/to/your/toolchain/xtensa-esp32s2-elf-gcc + +Download and extract toolchain: + +.. code-block:: console + + $ curl -s -L "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s2-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz" \ + | tar -C xtensa-esp32s2-elf-gcc --strip-components 1 -xJ + +Add the toolchain to your `PATH`: + +.. code-block:: console -For flashing firmware, you will need to install ``esptool.py`` by running:: + $ echo "export PATH=/path/to/your/toolchain/xtensa-esp32s2-elf-gcc/bin:$PATH" >> ~/.bashrc - $ pip install esptool +You can edit your shell's rc files if you don't use bash. Building from source -------------------- @@ -30,20 +75,19 @@ build the toolchain with crosstool-NG on Linux are as follows $ git clone https://github.com/espressif/crosstool-NG.git $ cd crosstool-NG - $ git checkout esp-2021r1 $ git submodule update --init $ ./bootstrap && ./configure --enable-local && make - $ ./ct-ng xtensa-esp32-elf + $ ./ct-ng xtensa-esp32s2-elf $ ./ct-ng build - $ chmod -R u+w builds/xtensa-esp32-elf + $ chmod -R u+w builds/xtensa-esp32s2-elf $ export PATH="crosstool-NG/builds/xtensa-esp32-elf/bin:$PATH" -Alternatively, you may follow the steps in -`ESP-IDF documentation `_. +These steps are given in the setup guide in +`ESP-IDF documentation `_. Flashing ======== diff --git a/Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/index.rst b/Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/index.rst index 99f76d576aca1..ad5d4dd1de091 100644 --- a/Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/index.rst +++ b/Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/index.rst @@ -46,6 +46,14 @@ Board LEDs There are several on-board LEDs for that indicate the presence of power and USB activity. None of these are available for use by software. +Another WS2812 LED is connected to GPIO48 or GPIO38 depending on the boards +version. + +.. note:: Both the initial and v1.1 versions of ESP32-S3-DevKitC-1 are + available on the market. The main difference lies in the GPIO assignment + for the RGB LED: the initial version (1.0) uses GPIO48, whereas v1.1 uses + GPIO38. The initial version is selected by default, but one can select + ``CONFIG_ESP32S3_DEVKITC_1_V11`` through ``make menuconfig``. I2S === @@ -317,6 +325,59 @@ To test it, just run the ``oneshot`` example:: Waiting... Finished +pm +------- + +This config demonstrate the use of power management present on the ESP32-S3. +You can use the ``pmconfig`` command to test the power management. +Enables PM support. You can define standby mode and sleep mode delay time:: + + $ make menuconfig + -> Board Selection + -> (15) PM_STANDBY delay (seconds) + (0) PM_STANDBY delay (nanoseconds) + (20) PM_SLEEP delay (seconds) + (0) PM_SLEEP delay (nanoseconds) + +Before switching PM status, you need to query the current PM status:: + + nsh> pmconfig + Last state 0, Next state 0 + + /proc/pm/state0: + DOMAIN0 WAKE SLEEP TOTAL + normal 0s 00% 0s 00% 0s 00% + idle 0s 00% 0s 00% 0s 00% + standby 0s 00% 0s 00% 0s 00% + sleep 0s 00% 0s 00% 0s 00% + + /proc/pm/wakelock0: + DOMAIN0 STATE COUNT TIME + system normal 2 1s + system idle 1 1s + system standby 1 1s + system sleep 1 1s + +System switch to the PM idle mode, you need to enter:: + + nsh> pmconfig relax normal + nsh> pmconfig relax normal + +System switch to the PM standby mode, you need to enter:: + + nsh> pmconfig relax idle + nsh> pmconfig relax normal + nsh> pmconfig relax normal + +System switch to the PM sleep mode, you need to enter:: + + nsh> pmconfig relax standby + nsh> pmconfig relax idle + nsh> pmconfig relax normal + nsh> pmconfig relax normal + +Note: When normal mode COUNT is 0, it will switch to the next PM state where COUNT is not 0. + psram_quad ---------- @@ -372,6 +433,37 @@ To test it, just run ``rand`` to get 32 randomly generated bytes:: 0000 98 b9 66 a2 a2 c0 a2 ae 09 70 93 d1 b5 91 86 c8 ..f......p...... 0010 8f 0e 0b 04 29 64 21 72 01 92 7c a2 27 60 6f 90 ....)d!r..|.'`o. +rmt +--- + +This configuration configures the transmitter and the receiver of the +Remote Control Transceiver (RMT) peripheral on the ESP32-S3 using GPIOs 48 +(or 38, depending on the board version) and 2, respectively. +The RMT peripheral is better explained +`here `__, +in the ESP-IDF documentation. The minimal data unit in the frame is called the +RMT symbol, which is represented by ``rmt_item32_t`` in the driver: + +.. figure:: rmt_symbol.png + :align: center + +The example ``rmtchar`` can be used to test the RMT peripheral. Connecting +these pins externally to each other will make the transmitter send RMT items +and demonstrates the usage of the RMT peripheral:: + + nsh> rmtchar + +**WS2812 addressable RGB LEDs** + +This same configuration enables the usage of the RMT peripheral and the example +``ws2812`` to drive addressable RGB LEDs:: + + nsh> ws2812 + +Please note that this board contains an on-board WS2812 LED connected to GPIO48 +(or GPIO38, depending on the board version) and, by default, this config +configures the RMT transmitter in the same pin. + rtc --- diff --git a/Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/rmt_symbol.png b/Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/rmt_symbol.png new file mode 100644 index 0000000000000..7f859d7c98be7 Binary files /dev/null and b/Documentation/platforms/xtensa/esp32s3/boards/esp32s3-devkit/rmt_symbol.png differ diff --git a/Documentation/platforms/xtensa/esp32s3/index.rst b/Documentation/platforms/xtensa/esp32s3/index.rst index 2229f65fa1be5..5501cb1f59a01 100644 --- a/Documentation/platforms/xtensa/esp32s3/index.rst +++ b/Documentation/platforms/xtensa/esp32s3/index.rst @@ -16,16 +16,61 @@ On dual-core SoCs, the two CPUs are typically named "PRO_CPU" and "APP_CPU" (for "protocol" and "application"), however for most purposes the two CPUs are interchangeable. -Toolchain -========= +ESP32-S3 Toolchain +================== + +The toolchain used to build ESP32-S3 firmware can be either downloaded or built from the sources. +It is **highly** recommended to use (download or build) the same toolchain version that is being +used by the NuttX CI. + +Please refer to the Docker +`container `_ and +check for the current compiler version being used. For instance: + +.. code-block:: + + ############################################################################### + # Build image for tool required by ESP32 builds + ############################################################################### + FROM nuttx-toolchain-base AS nuttx-toolchain-esp32 + # Download the latest ESP32 GCC toolchain prebuilt by Espressif + RUN mkdir -p xtensa-esp32-elf-gcc && \ + curl -s -L "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz" \ + | tar -C xtensa-esp32-elf-gcc --strip-components 1 -xJ + + RUN mkdir -p xtensa-esp32s2-elf-gcc && \ + curl -s -L "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s2-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz" \ + | tar -C xtensa-esp32s2-elf-gcc --strip-components 1 -xJ -You can use the prebuilt `toolchain `__ -for Xtensa architecture and `OpenOCD `__ -for ESP32-S3 by Espressif. + RUN mkdir -p xtensa-esp32s3-elf-gcc && \ + curl -s -L "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz" \ + | tar -C xtensa-esp32s3-elf-gcc --strip-components 1 -xJ + +For ESP32-S3, the toolchain version is based on GGC 12.2.0 (``xtensa-esp32s3-elf-12.2.0_20230208``) + +The prebuilt Toolchain (Recommended) +------------------------------------ + +First, create a directory to hold the toolchain: + +.. code-block:: console -For flashing firmware, you will need to install ``esptool.py`` by running:: + $ mkdir -p /path/to/your/toolchain/xtensa-esp32s3-elf-gcc - $ pip install esptool +Download and extract toolchain: + +.. code-block:: console + + $ curl -s -L "https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32s3-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz" \ + | tar -C xtensa-esp32s3-elf-gcc --strip-components 1 -xJ + +Add the toolchain to your `PATH`: + +.. code-block:: console + + $ echo "export PATH=/path/to/your/toolchain/xtensa-esp32s3-elf-gcc/bin:$PATH" >> ~/.bashrc + +You can edit your shell's rc files if you don't use bash. Building from source -------------------- @@ -51,36 +96,52 @@ build the toolchain with crosstool-NG on Linux are as follows These steps are given in the setup guide in `ESP-IDF documentation `_. -Flashing -======== - -Firmware for ESP32-S3 is flashed via the USB/UART or internal USB DEVICE JTAG interface using the -``esptool.py`` tool. -It's a two step process where the first converts the ELF file into a ESP32-S3 compatible binary -and the second flashes it to the board. These steps are included into the build system and you can -flash your NuttX firmware simply by running:: - - $ make flash ESPTOOL_PORT= - -where ```` is typically ``/dev/ttyUSB0`` or similar. You can change the baudrate by passing ``ESPTOOL_BAUD``. +Building and flashing NuttX +=========================== Bootloader and partitions ------------------------- -ESP32-S3 requires a bootloader to be flashed as well as a set of FLASH partitions. This is only needed the first time -(or any time you which to modify either of these). An easy way is to use prebuilt binaries for NuttX `from here `_. In there you will find instructions to rebuild these if necessary. -Once you downloaded both binaries, you can flash them by adding an ``ESPTOOL_BINDIR`` parameter, pointing to the directory where these binaries were downloaded: +Nuttx can boot the ESP32-S3 directly using the so-called "Simple Boot". An externally-built +2nd stage bootloader is not required in this case as all functions required to boot the device +are built within Nuttx. Simple boot does not require any specific configuration (it is selectable +by default if no other 2nd stage bootloader is used). -.. code-block:: console +If other features are required, an externally-built 2nd stage bootloader is needed. The bootloader +is built using the ``make bootloader`` command. This command generates the firmware in the +``nuttx`` folder. The ``ESPTOOL_BINDIR`` is used in the ``make flash`` command to specify the path +to the bootloader. For compatibility among other SoCs and future options of 2nd stage bootloaders, +the commands ``make bootloader`` and the ``ESPTOOL_BINDIR`` option (for the ``make flash``) can be +used even if no externally-built 2nd stage bootloader is being built (they will be ignored if +Simple Boot is used, for instance):: - $ make flash ESPTOOL_PORT= ESPTOOL_BINDIR= + $ make bootloader -.. note:: It is recommended that if this is the first time you are using the board with NuttX that you perform a complete SPI FLASH erase. +.. note:: It is recommended that if this is the first time you are using the board with NuttX to + perform a complete SPI FLASH erase. - .. code-block:: console + .. code-block:: console $ esptool.py erase_flash +Building and Flashing +--------------------- + +First, make sure that ``esptool.py`` is installed. This tool is used to convert the ELF to a +compatible ESP32-S3 image and to flash the image into the board. +It can be installed with: ``pip install esptool``. + +It's a two-step process where the first converts the ELF file into an ESP32-S3 compatible binary +and the second flashes it to the board. These steps are included in the build system and it is +possible to build and flash the NuttX firmware simply by running:: + + $ make flash ESPTOOL_PORT= ESPTOOL_BINDIR=./ + +where ```` is typically ``/dev/ttyUSB0`` or similar. ``ESPTOOL_BINDIR=./`` is the path of the +externally-built 2nd stage bootloader and the partition table (if applicable): when built using the +``make bootloader``, these files are placed into ``nuttx`` folder. ``ESPTOOL_BAUD`` is able to +change the flash baudrate if desired. + Peripheral Support ================== @@ -89,8 +150,8 @@ The following list indicates the state of peripherals' support in NuttX: ========== ======= ===== Peripheral Support NOTES ========== ======= ===== -ADC No -AES No +ADC YES +AES YES Bluetooth No CAMERA No CAN/TWAI Yes @@ -169,64 +230,11 @@ using WPA2. The ``dhcpd_start`` is necessary to let your board to associate an IP to your smartphone. -Memory Map -========== - -Address Mapping ---------------- - -================== ========== ========== =============== =============== -BUS TYPE START LAST DESCRIPTION NOTES -================== ========== ========== =============== =============== -To be added -================== ========== ========== =============== =============== - -Embedded Memory ---------------- - -=========== ========== ========== =============== =============== -BUS TYPE START LAST DESCRIPTION NOTES -=========== ========== ========== =============== =============== -To be added -=========== ========== ========== =============== =============== - -Boundary Address (Embedded) ---------------------------- - -====================== ========== ========== =============== =============== -BUS TYPE START LAST DESCRIPTION NOTES -====================== ========== ========== =============== =============== -To be added -====================== ========== ========== =============== =============== - -External Memory ---------------- - -=========== ========== ========== =============== =============== -BUS TYPE START LAST DESCRIPTION NOTES -=========== ========== ========== =============== =============== -To be added -=========== ========== ========== =============== =============== - -Boundary Address (External) ---------------------------- - -To be added - -Linker Segments ---------------- - -+---------------------+------------+------------+------+------------------------------+ -| DESCRIPTION | START | END | ATTR | LINKER SEGMENT NAME | -+=====================+============+============+======+==============================+ -| To be added | | | | | -+---------------------+------------+------------+------+------------------------------+ - Supported Boards ================ .. toctree:: - :glob: - :maxdepth: 1 + :glob: + :maxdepth: 1 - boards/*/* + boards/*/* diff --git a/Documentation/platforms/z16/z16f/index.rst b/Documentation/platforms/z16/z16f/index.rst index 765b827471877..5eb782a1e5484 100644 --- a/Documentation/platforms/z16/z16f/index.rst +++ b/Documentation/platforms/z16/z16f/index.rst @@ -12,7 +12,7 @@ available in NuttX version 0.3.7. A working NuttShell (NSH) configuration as added in NuttX-6.33 (although a patch is required to work around an issue with a ZDS-II 5.0.1 tool problem). An ESPI driver was added in NuttX-7.2. Refer to the NuttX board -`README `__ +`README `__ file for further information. Supported Boards diff --git a/Documentation/platforms/z80/z180/index.rst b/Documentation/platforms/z80/z180/index.rst index 9559011fc1b2a..2412327f0e033 100644 --- a/Documentation/platforms/z80/z180/index.rst +++ b/Documentation/platforms/z80/z180/index.rst @@ -16,7 +16,7 @@ makes additional P112 derivative hobbyist home brew computers. P112 board. Boards from Kickstarter project will not be available, however, until the third quarter of 2013. So it will be some time before this port is verified on hardware. Refer to the NuttX board -`README `__ +`README `__ file for further information. The arch/z80 directories contain files to support a variety of 8-bit architectures diff --git a/Documentation/platforms/z80/z8/index.rst b/Documentation/platforms/z80/z8/index.rst index 42b2c3f8c16c7..af64399d08d1e 100644 --- a/Documentation/platforms/z80/z8/index.rst +++ b/Documentation/platforms/z80/z8/index.rst @@ -13,9 +13,9 @@ environment is either Windows native or Cygwin under Windows. **STATUS:** This release has been verified only on the ZiLOG ZDS-II Z8Encore! chip simulation as of nuttx-0.3.9. Refer to the NuttX board README files for the -`z8encore000zco `__ +`z8encore000zco `__ and for -the\ `z8f64200100kit `__ +the\ `z8f64200100kit `__ for further information. Supported Boards diff --git a/Documentation/platforms/z80/z80/index.rst b/Documentation/platforms/z80/z80/index.rst index f16705024ad70..1cce01ba0f775 100644 --- a/Documentation/platforms/z80/z80/index.rst +++ b/Documentation/platforms/z80/z80/index.rst @@ -9,7 +9,7 @@ Z80 instruction simulator called z80sim. **STATUS:** This port is complete and stable to the extent that it can be tested using an instruction set simulator. Refer to the NuttX board -`README `__ +`README `__ file for further information. **XTRS: TRS-80 Model I/III/4/4P Emulator for Unix**. A very similar Z80 diff --git a/Documentation/quickstart/compiling_cmake.rst b/Documentation/quickstart/compiling_cmake.rst index 6a4df5aadf8aa..86259aa6b1d5d 100644 --- a/Documentation/quickstart/compiling_cmake.rst +++ b/Documentation/quickstart/compiling_cmake.rst @@ -45,10 +45,10 @@ We can now build NuttX. To do so, you can simply run: .. code-block:: console $ cd nuttx - $ cmake --build build -t menuconfig + $ cmake --build build The build will complete by generating the binary outputs -inside ``build/nuttx`` directory. Typically this includes the ``nuttx`` +inside ``build/`` directory. Typically this includes the ``nuttx`` ELF file (suitable for debugging using ``gdb``) and a ``nuttx.bin`` file that can be flashed to the board. diff --git a/Documentation/quickstart/debugging.rst b/Documentation/quickstart/debugging.rst index 546f72560abcf..d9bc13d3a815b 100644 --- a/Documentation/quickstart/debugging.rst +++ b/Documentation/quickstart/debugging.rst @@ -129,7 +129,7 @@ as there are some options hardcoded into opencd. By default, it assumes: * ``CONFIG_DISABLE_MQUEUE=y`` - * ``CONFIG_PAGING=n`` + * ``CONFIG_LEGACY_PAGING=n`` If you need these options to be set differently, you will have to edit ``./src/rtos/nuttx_header.h`` from ``openocd``, change the corresponding settings and then rebuild it. diff --git a/Documentation/quickstart/organization.rst b/Documentation/quickstart/organization.rst index 401dcd207b59b..006444feb8e43 100644 --- a/Documentation/quickstart/organization.rst +++ b/Documentation/quickstart/organization.rst @@ -237,10 +237,10 @@ support. For details see :doc:`/components/wireless`. -``nuttx/CMakeList.txt`` -======================= +``nuttx/CMakeLists.txt`` +======================== -The top-level ``CMakeList.txt`` file. +The top-level ``CMakeLists.txt`` file. ``nuttx/Makefile`` ================== diff --git a/Documentation/reference/os/conventions.rst b/Documentation/reference/os/conventions.rst index 74ecad093576e..c2f8587f75967 100644 --- a/Documentation/reference/os/conventions.rst +++ b/Documentation/reference/os/conventions.rst @@ -9,7 +9,7 @@ Naming and Header File Conventions the architecture-specific implementation in ``arch/``. ``up_`` is supposed to stand for microprocessor; the ``u`` - is like the Greek letter micron: ľ. So it would be ``ľP`` + is like the Greek letter micron: μ. So it would be ``μP`` which is a common shortening of the word microprocessor. I don't like that name very much. I wish I would have used a more obvious prefix like ``arch_`` instead -- then I would @@ -51,8 +51,8 @@ Naming and Header File Conventions case I am referring to the OS as layered into application interface, common internal OS logic, and lower level platform-specific layers. The platform-specific layers all - reside in the either ``arch/`` sub-directories on the - ``config/`` subdirectories: The former sub-directories are + reside in the either ``arch/`` sub-directories or the + ``boards/`` subdirectories: The former sub-directories are reserved for microcontroller-specific logic and the latter for board-specific logic. @@ -66,7 +66,7 @@ Naming and Header File Conventions This strict layering is enforced in the NuttX build system by controlling the compiler include paths: Higher level code can - never include header files from either; of the + never include header files from either of the platform-specific source directories; microcontroller-specific code can never include header files from the board-specific source directories. The board-specific directories are, then, diff --git a/Documentation/reference/os/index.rst b/Documentation/reference/os/index.rst index dc9ff91063d61..6e6d9ac7ea9cf 100644 --- a/Documentation/reference/os/index.rst +++ b/Documentation/reference/os/index.rst @@ -17,7 +17,6 @@ in other header files. iob.rst led.rst mutex.rst - nat.rst newreno.rst notifier.rst nuttx.rst @@ -26,4 +25,3 @@ in other header files. smp.rst time_clock.rst wqueue.rst - netdev.rst diff --git a/Documentation/reference/os/nat.rst b/Documentation/reference/os/nat.rst deleted file mode 100644 index 01215356b0fd7..0000000000000 --- a/Documentation/reference/os/nat.rst +++ /dev/null @@ -1,186 +0,0 @@ -================================= -Network Address Translation (NAT) -================================= - -NuttX supports full cone NAT logic, which currently supports - -- TCP - -- UDP - -- ICMP - - - ECHO (REQUEST & REPLY) - - - Error Messages (DEST_UNREACHABLE & TIME_EXCEEDED & PARAMETER_PROBLEM) - -Workflow -======== - -:: - - Local Network (LAN) External Network (WAN) - |----------------| - | | external port> peer port> - |----------------| - -- Outbound - - - **LAN** -> **Forward** -> **NAT** (only if targeting at WAN) -> **WAN** - - - All packets from **LAN** and targeting at **WAN** will be masqueraded - with ``local ip:port`` changed to ``external ip:port``. - -- Inbound - - - **WAN** -> **NAT** (only from WAN, change destination) -> **Forward** -> **LAN** - - - Packets from **WAN** will try to be changed back from - ``external ip:port`` to ``local ip:port`` and send to **LAN**. - -Configuration Options -===================== - -``CONFIG_NET_NAT`` - Enable or disable Network Address Translation (NAT) function. - Depends on ``CONFIG_NET_IPFORWARD``. -``CONFIG_NET_NAT_HASH_BITS`` - The bits of the hashtable of NAT entries, hashtable has (1 << bits) buckets. -``CONFIG_NET_NAT_TCP_EXPIRE_SEC`` - The expiration time for idle TCP entry in NAT. - The default value 86400 is suggested by RFC2663, Section 2.6, - Page 5. But we may set it to shorter time like 240s for better - performance. -``CONFIG_NET_NAT_UDP_EXPIRE_SEC`` - The expiration time for idle UDP entry in NAT. -``CONFIG_NET_NAT_ICMP_EXPIRE_SEC`` - The expiration time for idle ICMP entry in NAT. -``CONFIG_NET_NAT_ENTRY_RECLAIM_SEC`` - The time to auto reclaim all expired NAT entries. A value of zero will - disable auto reclaiming. - Expired entries will be automatically reclaimed when matching - inbound/outbound entries, so this config does not have significant - impact when NAT is normally used, but very useful when the hashtable - is big and there are only a few connections using NAT (which will - only trigger reclaiming on a few chains in hashtable). - -Usage -===== - - - :c:func:`ipv4_nat_enable()` - - :c:func:`ipv4_nat_disable()` - -.. c:function:: int ipv4_nat_enable(FAR struct net_driver_s *dev); - - Enable NAT function on a network device, on which the outbound packets - will be masqueraded. - - :return: Zero is returned if NAT function is successfully enabled on - the device; A negated errno value is returned if failed. - -.. c:function:: int ipv4_nat_disable(FAR struct net_driver_s *dev); - - Disable NAT function on a network device. - - :return: Zero is returned if NAT function is successfully disabled on - the device; A negated errno value is returned if failed. - -Validation -========== - -Validated on Ubuntu 22.04 x86_64 with NuttX SIM by following steps: - -1. Configure NuttX with >=2 TAP devices (host route mode) and NAT enabled: - - .. code-block:: Kconfig - - CONFIG_NET_IPFORWARD=y - CONFIG_NET_NAT=y - # CONFIG_SIM_NET_BRIDGE is not set - CONFIG_SIM_NETDEV_NUMBER=2 - -2. Call ``ipv4_nat_enable`` on one dev on startup - - .. code-block:: c - - /* arch/sim/src/sim/up_netdriver.c */ - int netdriver_init(void) - { - ... - ipv4_nat_enable(&g_sim_dev[0]); - ... - } - -3. Set IP Address for NuttX on startup - - .. code-block:: shell - - ifconfig eth0 10.0.1.2 - ifup eth0 - ifconfig eth1 10.0.10.2 - ifup eth1 - -4. Configure IP & namespace & route on host side (maybe need to be root, then try ``sudo -i``) - - .. code-block:: bash - - IF_HOST="enp1s0" - IF_0="tap0" - IP_HOST_0="10.0.1.1" - IF_1="tap1" - IP_HOST_1="10.0.10.1" - IP_NUTTX_1="10.0.10.2" - - # add net namespace LAN for $IF_1 - ip netns add LAN - ip netns exec LAN sysctl -w net.ipv4.ip_forward=1 - ip link set $IF_1 netns LAN - ip netns exec LAN ip link set $IF_1 up - ip netns exec LAN ip link set lo up - - # add address and set default route - ip addr add $IP_HOST_0/24 dev $IF_0 - ip netns exec LAN ip addr add $IP_HOST_1/24 dev $IF_1 - ip netns exec LAN ip route add default dev $IF_1 via $IP_NUTTX_1 - - # nat to allow NuttX to access the internet - iptables -t nat -A POSTROUTING -o $IF_HOST -j MASQUERADE - iptables -A FORWARD -i $IF_HOST -o $IF_0 -j ACCEPT - iptables -A FORWARD -i $IF_0 -o $IF_HOST -j ACCEPT - sysctl -w net.ipv4.ip_forward=1 - -5. Do anything in the LAN namespace will go through NAT - - .. code-block:: shell - - # Host side - iperf -B 10.0.1.1 -s -i 1 - # LAN side - sudo ip netns exec LAN iperf -B 10.0.10.1 -c 10.0.1.1 -i 1 - - .. code-block:: shell - - # Host side - python3 -m http.server - # LAN side - for i in {1..20000}; do sudo ip netns exec LAN curl 'http://10.0.1.1:8000/' > /dev/null 2>1; done - - .. code-block:: shell - - # LAN side - sudo ip netns exec LAN ping 8.8.8.8 - - .. code-block:: shell - - # LAN side - sudo ip netns exec LAN traceroute -n 8.8.8.8 # ICMP error msg of UDP - sudo ip netns exec LAN traceroute -n -T 8.8.8.8 # ICMP error msg of TCP - - .. code-block:: shell - - # Host side - tcpdump -nn -i tap0 - # LAN side - sudo ip netns exec LAN tcpdump -nn -i tap1 diff --git a/Documentation/reference/os/notifier.rst b/Documentation/reference/os/notifier.rst index b5cb14a0b0008..908d6ebbdf340 100644 --- a/Documentation/reference/os/notifier.rst +++ b/Documentation/reference/os/notifier.rst @@ -1,3 +1,5 @@ +.. _notifier_chain: + ============== Notifier Chain ============== diff --git a/Kconfig b/Kconfig index 603c6f924d608..4775813184f45 100644 --- a/Kconfig +++ b/Kconfig @@ -2196,6 +2196,72 @@ config DEBUG_IPC_INFO endif # DEBUG_IPC +config DEBUG_PCI + bool "PCI Debug Features" + default n + depends on PCI + ---help--- + Enable PCI driver debug features. + + Support for this debug option is architecture-specific and may not + be available for some MCUs. + +if DEBUG_PCI + +config DEBUG_PCI_ERROR + bool "PCI Error Output" + default n + depends on DEBUG_ERROR + ---help--- + Enable PCI driver error output to SYSLOG. + +config DEBUG_PCI_WARN + bool "PCI Warnings Output" + default n + depends on DEBUG_WARN + ---help--- + Enable PCI driver warning output to SYSLOG. + +config DEBUG_PCI_INFO + bool "PCI Informational Output" + default n + depends on DEBUG_INFO + ---help--- + Enable PCI driver informational output to SYSLOG. + +endif # DEBUG_PCI + +config DEBUG_RPMSG + bool "RPMSG Debug Features" + default n + depends on RPMSG + ---help--- + Enable RPMSG driver debug features. + +if DEBUG_RPMSG + +config DEBUG_RPMSG_ERROR + bool "RPMSG Error Output" + default n + depends on DEBUG_ERROR + ---help--- + Enable RPMSG driver error output to SYSLOG. + +config DEBUG_RPMSG_WARN + bool "RPMSG Warnings Output" + default n + depends on DEBUG_WARN + ---help--- + Enable RPMSG driver warning output to SYSLOG. + +config DEBUG_RPMSG_INFO + bool "RPMSG Informational Output" + default n + depends on DEBUG_INFO + ---help--- + Enable RPMSG driver informational output to SYSLOG. + +endif # DEBUG_RPMSG endif # DEBUG_FEATURES config ARCH_HAVE_STACKCHECK diff --git a/LICENSE b/LICENSE index 7ba4c9701231b..8913ecfb81ccc 100644 --- a/LICENSE +++ b/LICENSE @@ -3842,6 +3842,7 @@ arch/arm/src/rp2040/rp2040_pio.h arch/arm/src/rp2040/rp2040_pio_instructions.h arch/arm/src/rp2040/rp2040_pll.c arch/arm/src/rp2040/rp2040_xosc.c +boards/arm/rp2040/common/src/rp2040_uniqueid.c ========================================================== Based upon the software originally developed by Raspberry Pi (Trading) Ltd. @@ -8564,3 +8565,72 @@ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +include/search.h +====================== +$NetBSD: search.h,v 1.12 1999/02/22 10:34:28 christos Exp $ +$FreeBSD: src/include/search.h,v 1.4 2002/03/23 17:24:53 imp Exp $ + +Written by J.T. Conklin +Public domain. + +libs/libc/search/hcreate.c +libs/libc/search/hcreate_r.c +====================== +$NetBSD: hcreate.c,v 1.2 2001/02/19 21:26:04 ross Exp $ + +Copyright (c) 2001 Christopher G. Demetriou +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +libs/libc/search/hash_func.c +====================== +Copyright (c) 1990, 1993 +The Regents of the University of California. All rights reserved. + +This code is derived from software contributed to Berkeley by +Margo Seltzer. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. diff --git a/arch/CMakeLists.txt b/arch/CMakeLists.txt index ac8f147493553..41b790a83b46b 100644 --- a/arch/CMakeLists.txt +++ b/arch/CMakeLists.txt @@ -25,7 +25,7 @@ nuttx_add_kernel_library(arch) target_include_directories(arch PRIVATE ${CMAKE_SOURCE_DIR}/sched) -if(NOT CONFIG_BUILD_FLAT) +if(CONFIG_BUILD_PROTECTED) nuttx_add_system_library(arch_interface) target_include_directories(arch_interface PRIVATE ${CMAKE_SOURCE_DIR}/sched) endif() diff --git a/arch/Kconfig b/arch/Kconfig index da974c6071e95..df1726f022113 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -92,6 +92,7 @@ config ARCH_RISCV select ARCH_HAVE_RDWR_MEM_CPU_RUN select ARCH_HAVE_TCBINFO select ARCH_HAVE_THREAD_LOCAL + select ARCH_HAVE_POWEROFF select ARCH_HAVE_LAZYFPU if ARCH_HAVE_FPU ---help--- RISC-V 32 and 64-bit RV32 / RV64 architectures. @@ -130,6 +131,10 @@ config ARCH_X86 config ARCH_X86_64 bool "x86_64" select ARCH_HAVE_TCBINFO + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU + select ARCH_HAVE_TESTSET + select ARCH_HAVE_CUSTOMOPT select LIBC_ARCH_ELF_64BIT if LIBC_ARCH_ELF ---help--- x86-64 architectures. @@ -174,6 +179,15 @@ config ARCH_SPARC ---help--- SPARC architectures (SPARC V8) +config ARCH_TRICORE + bool "Infineon TriCore" + select ARCH_HAVE_INTERRUPTSTACK + select ARCH_HAVE_STACKCHECK + select ARCH_HAVE_CUSTOMOPT + select ARCH_HAVE_TCBINFO + ---help--- + Infineon 32-bit AURIX TriCore architectures + endchoice config ARCH @@ -194,6 +208,7 @@ config ARCH default "z80" if ARCH_Z80 default "or1k" if ARCH_OR1K default "sparc" if ARCH_SPARC + default "tricore" if ARCH_TRICORE source "arch/arm/Kconfig" source "arch/arm64/Kconfig" @@ -211,6 +226,7 @@ source "arch/z16/Kconfig" source "arch/z80/Kconfig" source "arch/or1k/Kconfig" source "arch/sparc/Kconfig" +source "arch/tricore/Kconfig" config ARCH_CHIP_CUSTOM bool "Custom Chip Support" @@ -263,6 +279,10 @@ config ARCH_TOOLCHAIN_CLANG select ARCH_TOOLCHAIN_GNU default n +config ARCH_TOOLCHAIN_TASKING + bool + default n + choice prompt "Link Time Optimization (LTO)" default LTO_NONE @@ -411,6 +431,18 @@ config ARCH_HAVE_TEXT_HEAP ---help--- Special memory region for dynamic code loading +config ARCH_HAVE_TEXT_HEAP_SEPARATE_DATA_ADDRESS + bool + default n + ---help--- + Textheap might have separate instruction/data mappings + +config ARCH_HAVE_TEXT_HEAP_WORD_ALIGNED_READ + bool + default n + ---help--- + Loads from the instruction mapping of textheap need to be word-aligned + config ARCH_HAVE_DATA_HEAP bool default n @@ -440,6 +472,11 @@ config ARCH_HAVE_DPFPU default n select ARCH_HAVE_FPU +config ARCH_HAVE_QPFPU + bool + default n + select ARCH_HAVE_DPFPU + config ARCH_HAVE_LAZYFPU bool default n @@ -518,7 +555,7 @@ config ARCH_HAVE_PERF_EVENTS config ARCH_PERF_EVENTS bool "Configure hardware performance counting" - default y if SCHED_CRITMONITOR || SCHED_IRQMONITOR || RPTUN_PING || SEGGER_SYSVIEW + default y if SCHED_CRITMONITOR || SCHED_IRQMONITOR || RPMSG_PING || SEGGER_SYSVIEW default n depends on ARCH_HAVE_PERF_EVENTS ---help--- @@ -550,14 +587,17 @@ config ARCH_HAVE_TRUSTZONE choice prompt "TrustZone Configuration" - default ARCH_TRUSTZONE_NONSECURE + default ARCH_TRUSTZONE_DISABLED depends on ARCH_HAVE_TRUSTZONE +config ARCH_TRUSTZONE_DISABLED + bool "TrustZone disabled, all CPUs operate in secure state" + config ARCH_TRUSTZONE_SECURE - bool "All CPUs operate secure state" + bool "TrustZone enabled, all CPUs operate secure state" config ARCH_TRUSTZONE_NONSECURE - bool "All CPUs operate non-secure state" + bool "TrustZone enabled, all CPUs operate non-secure state" endchoice # TrustZone Configuration @@ -577,6 +617,14 @@ config ARCH_DPFPU Enable toolchain support for double precision (64-bit) floating point if both the toolchain and the hardware support it. +config ARCH_QPFPU + bool "Quad-Precision FPU support" + default y + depends on ARCH_FPU && ARCH_HAVE_DPFPU && ARCH_HAVE_QPFPU + ---help--- + Enable toolchain support for quadruple precision (128 bits or 16 bytes) floating + point if both the toolchain and the hardware support it. + config ARCH_LAZYFPU bool "Enable lazy FPU state save / restore" default n @@ -688,6 +736,10 @@ config ARCH_VMA_MAPPING bool "Support runtime memory mapping into SHM area" default n +config ARCH_KVMA_MAPPING + bool + default n + config ARCH_SHM_VBASE hex "Shared memory base" depends on ARCH_VMA_MAPPING @@ -696,6 +748,7 @@ config ARCH_SHM_VBASE config ARCH_KMAP_VBASE hex "Kernel dynamic virtual mappings base" + depends on ARCH_KVMA_MAPPING ---help--- The virtual address of the beginning of the kernel dynamic mapping region. @@ -730,42 +783,28 @@ config ARCH_SHM_MAXREGIONS int "Max shared memory regions" default 1 ---help--- - The maximum number of regions that can allocated for the shared - memory space. This hard-coded value permits static allocation of + The maximum number of regions that can be used with SysV shared + memory interface. This hard-coded value permits static allocation of the shared memory data structures and serves no other purpose. Default is 1. - The size of the virtual shared memory address space is then - determined by the product of the maximum number of regions, the - maximum number of pages per region, and the configured size of - each page. - config ARCH_SHM_NPAGES - int "Max shared memory pages" + int "Max size of userspace VM mapping in pages" default 1 ---help--- - The maximum number of pages that can allocated per region for the shared memory - region. Default is 1. - - The size of the virtual shared memory address space is then - determined by the product of the maximum number of regions, the - maximum number of pages per region, and the configured size of - each page. + The max size of the virtual memory region for shared memory, + userspace device mappings etc. endif # ARCH_VMA_MAPPING config ARCH_KMAP_NPAGES int "Max kernel dynamic mapping pages" default 1 + depends on ARCH_KVMA_MAPPING ---help--- The maximum amount of pages that a kernel can use for dynamically mapping physical pages to itself. - The size of the virtual shared memory address space is then - determined by the product of the maximum number of regions, the - maximum number of pages per region, and the configured size of - each page. - config ARCH_STACK_DYNAMIC bool "Dynamic user stack" default n @@ -871,16 +910,26 @@ config ARCH_PGPOOL_SIZE endif # ARCH_PGPOOL_MAPPING endif # ARCH_ADDRENV && ARCH_NEED_ADDRENV_MAPPING -menuconfig PAGING +config PAGING bool "On-demand paging" default n - depends on ARCH_USE_MMU && !ARCH_ROMPGTABLE + depends on BUILD_KERNEL && ARCH_USE_MMU && !ARCH_ROMPGTABLE && !LEGACY_PAGING + ---help--- + If set =y in your configation file, this setting will enable on-demand + paging, which relies on a MMU to enable larger virtual memory spaces + and map it to physical memory on-demand (usually during a page-fault + exception). + +menuconfig LEGACY_PAGING + bool "Legacy On-demand paging" + default n + depends on EXPERIMENTAL && ARCH_USE_MMU && !ARCH_ROMPGTABLE ---help--- - If set =y in your configation file, this setting will enable the on-demand - paging feature as described in + If set =y in your configation file, this setting will enable lazy loading + backed up by the experimental on-demand paging feature as described in https://nuttx.apache.org/docs/latest/components/paging.html. -if PAGING +if LEGACY_PAGING config PAGING_PAGESIZE int "Page size (bytes)" @@ -998,7 +1047,7 @@ config PAGING_TIMEOUT_TICKS number if microseconds, then a fatal error will be declared. Default: No timeouts monitored -endif # PAGING +endif # LEGACY_PAGING config ARCH_IRQPRIO bool "Prioritized interrupt support" diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index dea4e3904d7ed..71cbcfc25c9fd 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -83,7 +83,7 @@ config ARCH_CHIP_AM335X config ARCH_CHIP_FVP_ARMV8R_AARCH32 bool "ARM FVP virt platform (ARMv8r AARCH32)" - select ARCH_ARMV8R + select ARCH_CORTEXR52 select ARCH_HAVE_LOWVECTORS select ARCH_HAVE_FETCHADD select ARMV8R_HAVE_DECODEFIQ @@ -305,6 +305,7 @@ config ARCH_CHIP_NRF91 select ARCH_HAVE_TRUSTZONE select ARCH_HAVE_TICKLESS select ARCH_DMA_NO_FLASH_TRANSFER + select ARCH_HAVE_FPU depends on EXPERIMENTAL ---help--- Nordic nRF91 architectures (ARM Cortex-M33 with integrated @@ -600,6 +601,7 @@ config ARCH_CHIP_XMC4 select ARCH_HAVE_I2CRESET select ARM_HAVE_MPU_UNIFIED select ARMV7M_HAVE_STACKCHECK + select ARCH_HAVE_TICKLESS ---help--- Infineon XMC4xxx(ARM Cortex-M4) architectures @@ -648,6 +650,11 @@ config ARCH_CHIP_TLSR82 ---help--- Telink tlsr82xx architectures (Customed armv6m) +config ARCH_CHIP_MPS + bool "MPS ARM Series" + ---help--- + MPS platform (MPS2 MPS3) + config ARCH_CHIP_QEMU_ARM bool "QEMU virt platform (ARMv7a)" select ARCH_HAVE_PSCI @@ -926,6 +933,13 @@ config ARCH_CORTEXR7 select ARCH_HAVE_MPU select ARCH_HAVE_TESTSET +config ARCH_CORTEXR52 + bool + default n + select ARCH_ARMV8R + select ARCH_HAVE_MPU + select ARCH_HAVE_TESTSET + config ARCH_ARMV8M bool default n @@ -1087,6 +1101,7 @@ config ARCH_CHIP default "phy62xx" if ARCH_CHIP_PHY62XX default "tlsr82" if ARCH_CHIP_TLSR82 default "qemu" if ARCH_CHIP_QEMU_ARM + default "mps" if ARCH_CHIP_MPS default "goldfish" if ARCH_CHIP_GOLDFISH_ARM default "at32" if ARCH_CHIP_AT32 @@ -1564,6 +1579,9 @@ endif if ARCH_CHIP_QEMU_ARM source "arch/arm/src/qemu/Kconfig" endif +if ARCH_CHIP_MPS +source "arch/arm/src/mps/Kconfig" +endif if ARCH_CHIP_GOLDFISH_ARM source "arch/arm/src/goldfish/Kconfig" endif diff --git a/arch/arm/include/arm/irq.h b/arch/arm/include/arm/irq.h index 2d65c735f0d57..dd7ab7cb0a673 100644 --- a/arch/arm/include/arm/irq.h +++ b/arch/arm/include/arm/irq.h @@ -153,7 +153,7 @@ struct xcptcontext * address register (FAR) at the time of data abort exception. */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING uintptr_t far; #endif }; diff --git a/arch/arm/include/armv7-a/irq.h b/arch/arm/include/armv7-a/irq.h index d95e0b9545d02..1bc4ce0ce5c1a 100644 --- a/arch/arm/include/armv7-a/irq.h +++ b/arch/arm/include/armv7-a/irq.h @@ -273,7 +273,7 @@ struct xcptcontext * address register (FAR) at the time of data abort exception. */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING uintptr_t far; #endif @@ -357,9 +357,10 @@ noinstrument_function static inline irqstate_t up_irq_save(void) __asm__ __volatile__ ( "\tmrs %0, cpsr\n" - "\tcpsid i\n" -#if defined(CONFIG_ARMV7A_DECODEFIQ) +#ifdef CONFIG_ARCH_TRUSTZONE_SECURE "\tcpsid f\n" +#else + "\tcpsid i\n" #endif : "=r" (cpsr) : @@ -378,9 +379,11 @@ static inline irqstate_t up_irq_enable(void) __asm__ __volatile__ ( "\tmrs %0, cpsr\n" - "\tcpsie i\n" -#if defined(CONFIG_ARMV7A_DECODEFIQ) +#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT) "\tcpsie f\n" +#endif +#ifndef CONFIG_ARCH_TRUSTZONE_SECURE + "\tcpsie i\n" #endif : "=r" (cpsr) : diff --git a/arch/arm/include/armv7-r/irq.h b/arch/arm/include/armv7-r/irq.h index 80911537042fa..09a107a3171da 100644 --- a/arch/arm/include/armv7-r/irq.h +++ b/arch/arm/include/armv7-r/irq.h @@ -272,7 +272,7 @@ struct xcptcontext * address register (FAR) at the time of data abort exception. */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING uintptr_t far; #endif diff --git a/arch/arm/include/armv8-r/irq.h b/arch/arm/include/armv8-r/irq.h index f0ca5e0fbd439..b59bc54896449 100644 --- a/arch/arm/include/armv8-r/irq.h +++ b/arch/arm/include/armv8-r/irq.h @@ -272,7 +272,7 @@ struct xcptcontext * address register (FAR) at the time of data abort exception. */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING uintptr_t far; #endif diff --git a/arch/arm/include/cxd56xx/gnssram.h b/arch/arm/include/cxd56xx/gnssram.h new file mode 100644 index 0000000000000..c7a1e33f1f11a --- /dev/null +++ b/arch/arm/include/cxd56xx/gnssram.h @@ -0,0 +1,186 @@ +/**************************************************************************** + * arch/arm/include/cxd56xx/gnssram.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_CXD56XX_GNSSRAM_H +#define __ARCH_ARM_INCLUDE_CXD56XX_GNSSRAM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SECTION_GNSSRAM_TEXT ".gnssram.text" +#define SECTION_GNSSRAM_DATA ".gnssram.data" +#define SECTION_GNSSRAM_BSS ".gnssram.bss" + +/* Locate code and data into GNSS RAM */ + +#ifdef CONFIG_CXD56_GNSS_RAM +# define GNSSRAM_CODE locate_code(SECTION_GNSSRAM_TEXT) +# define GNSSRAM_DATA locate_data(SECTION_GNSSRAM_DATA) +# define GNSSRAM_BSS locate_data(SECTION_GNSSRAM_BSS) +#else +# define GNSSRAM_CODE +# define GNSSRAM_DATA +# define GNSSRAM_BSS +#endif + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: up_gnssram_initialize + * + * Description: + * Initialize the GNSS heap. + * + ****************************************************************************/ + +void up_gnssram_initialize(void); + +/**************************************************************************** + * Name: up_gnssram_uninitialize + * + * Description: + * Uninitialize the GNSS heap. + * + ****************************************************************************/ + +void up_gnssram_uninitialize(void); + +/**************************************************************************** + * Name: up_gnssram_malloc + * + * Description: + * Allocate memory from the GNSS heap. + * + ****************************************************************************/ + +void *up_gnssram_malloc(size_t size); + +/**************************************************************************** + * Name: up_gnssram_calloc + * + * Description: + * Calculates the size of the allocation and allocate memory from + * the GNSS heap. + * + ****************************************************************************/ + +void *up_gnssram_calloc(size_t n, size_t elem_size); + +/**************************************************************************** + * Name: up_gnssram_realloc + * + * Description: + * Reallocate memory from the GNSS heap. + * + ****************************************************************************/ + +void *up_gnssram_realloc(void *ptr, size_t size); + +/**************************************************************************** + * Name: up_gnssram_zalloc + * + * Description: + * Allocate and zero memory from the GNSS heap. + * + ****************************************************************************/ + +void *up_gnssram_zalloc(size_t size); + +/**************************************************************************** + * Name: up_gnssram_free + * + * Description: + * Free memory from the GNSS heap. + * + ****************************************************************************/ + +void up_gnssram_free(void *mem); + +/**************************************************************************** + * Name: up_gnssram_memalign + * + * Description: + * memalign requests more than enough space from malloc, finds a region + * within that chunk that meets the alignment request and then frees any + * leading or trailing space. + * + * The alignment argument must be a power of two (not checked). 8-byte + * alignment is guaranteed by normal malloc calls. + * + ****************************************************************************/ + +void *up_gnssram_memalign(size_t alignment, size_t size); + +/**************************************************************************** + * Name: up_gnssram_heapmember + * + * Description: + * Check if an address lies in the GNSS heap. + * + * Parameters: + * mem - The address to check + * + * Return Value: + * true if the address is a member of the GNSS heap. false if not + * + ****************************************************************************/ + +bool up_gnssram_heapmember(void *mem); + +/**************************************************************************** + * Name: up_gnssram_mallinfo + * + * Description: + * mallinfo returns a copy of updated current heap information for the + * GNSS heap. + * + ****************************************************************************/ + +struct mallinfo up_gnssram_mallinfo(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM_INCLUDE_CXD56XX_GNSSRAM_H */ diff --git a/arch/arm/include/irq.h b/arch/arm/include/irq.h index 69b47a3da135f..21e221816bd55 100644 --- a/arch/arm/include/irq.h +++ b/arch/arm/include/irq.h @@ -83,7 +83,7 @@ extern "C" ****************************************************************************/ /* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt + * register storage structure. It is non-NULL only during interrupt * processing. Access to g_current_regs[] must be through the macro * CURRENT_REGS for portability. */ diff --git a/arch/arm/include/mps/chip.h b/arch/arm/include/mps/chip.h new file mode 100644 index 0000000000000..84d89e5a712d0 --- /dev/null +++ b/arch/arm/include/mps/chip.h @@ -0,0 +1,48 @@ +/**************************************************************************** + * arch/arm/include/mps/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_INCLUDE_MPS_CHIP_H +#define __ARCH_ARM_INCLUDE_MPS_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* Bits [7:5] set in minimum priority */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_INCLUDE_MPS_CHIP_H */ diff --git a/arch/arm/include/mps/irq.h b/arch/arm/include/mps/irq.h new file mode 100644 index 0000000000000..6d9cdffc61c3b --- /dev/null +++ b/arch/arm/include/mps/irq.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * arch/arm/include/mps/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM_INCLUDE_MPS_IRQ_H +#define __ARCH_ARM_INCLUDE_MPS_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +#define NR_IRQS 130 /* Total number of interrupts */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* __ARCH_ARM_INCLUDE_MPS_IRQ_H */ diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h index f155df64d2311..00855956cb121 100644 --- a/arch/arm/include/stm32/chip.h +++ b/arch/arm/include/stm32/chip.h @@ -1587,7 +1587,7 @@ # define STM32_NDMA 2 /* DMA1-2 with 8 streams each*/ # define STM32_NSPI 3 /* SPI1-3 */ # define STM32_NI2S 2 /* I2S2-3 (multiplexed with SPI2-3) */ -# define STM32_NUSART 3 /* USART1, 2 and 6 */ +# define STM32_NUSART 6 /* Actually only 3: USART1, 2 and 6 */ # define STM32_NI2C 3 /* I2C1-3 */ # define STM32_NCAN 0 /* No CAN */ # if defined(CONFIG_ARCH_CHIP_STM32F401CB) || defined(CONFIG_ARCH_CHIP_STM32F401CC) diff --git a/arch/arm/include/stm32h7/chip.h b/arch/arm/include/stm32h7/chip.h index f0b38971ef6b6..d59b908ab5e6f 100644 --- a/arch/arm/include/stm32h7/chip.h +++ b/arch/arm/include/stm32h7/chip.h @@ -73,7 +73,8 @@ defined (CONFIG_ARCH_CHIP_STM32H753ZI) || \ defined (CONFIG_ARCH_CHIP_STM32H7B3LI) || \ defined (CONFIG_ARCH_CHIP_STM32H745XI) || \ - defined (CONFIG_ARCH_CHIP_STM32H745ZI) + defined (CONFIG_ARCH_CHIP_STM32H745ZI) || \ + defined (CONFIG_ARCH_CHIP_STM32H755II) #elif defined(CONFIG_ARCH_CHIP_STM32H747XI) #else # error STM32 H7 chip not identified diff --git a/arch/arm/src/Makefile b/arch/arm/src/Makefile index 4850080312920..d00fbfea5916b 100644 --- a/arch/arm/src/Makefile +++ b/arch/arm/src/Makefile @@ -18,7 +18,7 @@ # ############################################################################ -include $(TOPDIR)/Make.defs +include $(TOPDIR)/tools/apps-or-nuttx-Make.defs include chip/Make.defs ifeq ($(CONFIG_ARCH_ARMV7A),y) # ARMv7-A @@ -180,13 +180,27 @@ $(KBIN): $(OBJS) board$(DELIM)libboard$(LIBEXT): $(Q) $(MAKE) -C board libboard$(LIBEXT) EXTRAFLAGS="$(EXTRAFLAGS)" -define LINK_ALLSYMS - $(Q) $(TOPDIR)/tools/mkallsyms.py $(NUTTX) allsyms.tmp +# When multiple linking, these two additional linking objects will be included + +ifeq ($(CONFIG_MM_KASAN_GLOBAL),y) +EXTRA_LIBS += kasan_globals$(OBJEXT) +endif +ifeq ($(CONFIG_ALLSYMS),y) +EXTRA_LIBS += allsyms$(OBJEXT) +endif + +define LINK_ALLSYMS_KASAN + $(if $(CONFIG_ALLSYMS), + $(Q) $(TOPDIR)/tools/mkallsyms.py $(NUTTX) allsyms.tmp --orderbyname $(CONFIG_SYMTAB_ORDEREDBYNAME) $(Q) $(call COMPILE, allsyms.tmp, allsyms$(OBJEXT), -x c) + $(Q) $(call DELFILE, allsyms.tmp)) + $(if $(CONFIG_MM_KASAN_GLOBAL), + $(Q) $(TOPDIR)/tools/kasan_global.py -e $(NUTTX) -o kasan_globals.tmp + $(Q) $(call COMPILE, kasan_globals.tmp, kasan_globals$(OBJEXT) -fno-sanitize=kernel-address, -x c) + $(Q) $(call DELFILE, kasan_globals.tmp)) $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ - -o $(NUTTX) $(HEAD_OBJ) allsyms$(OBJEXT) $(EXTRA_OBJS) \ + -o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \ $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) - $(Q) $(call DELFILE, allsyms.tmp allsyms$(OBJEXT)) endef $(addsuffix .tmp,$(ARCHSCRIPT)): $(ARCHSCRIPT) @@ -194,17 +208,19 @@ $(addsuffix .tmp,$(ARCHSCRIPT)): $(ARCHSCRIPT) nuttx$(EXEEXT): $(HEAD_OBJ) board$(DELIM)libboard$(LIBEXT) $(addsuffix .tmp,$(ARCHSCRIPT)) $(Q) echo "LD: nuttx" -ifneq ($(CONFIG_ALLSYMS),y) +ifeq ($(CONFIG_ALLSYMS)$(CONFIG_MM_KASAN_GLOBAL),) $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ -o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \ $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) else - $(Q) # Link and generate default table - $(Q) $(if $(wildcard $(shell echo $(NUTTX))),,$(call LINK_ALLSYMS,$^)) - $(Q) # Extract all symbols - $(Q) $(call LINK_ALLSYMS, $^) - $(Q) # Extract again since the table offset may changed - $(Q) $(call LINK_ALLSYMS, $^) + $(Q) $(call LINK_ALLSYMS_KASAN) + $(Q) $(call LINK_ALLSYMS_KASAN) + $(Q) $(call LINK_ALLSYMS_KASAN) + $(Q) $(call LINK_ALLSYMS_KASAN) +endif +ifeq ($(CONFIG_MM_KASAN_GLOBAL),y) + $(Q) $(OBJCOPY) -R .kasan.global $(NUTTX) + $(Q) $(OBJCOPY) -R .kasan.unused $(NUTTX) endif ifneq ($(CONFIG_WINDOWS_NATIVE),y) $(Q) $(NM) $(NUTTX) | \ diff --git a/arch/arm/src/a1x/a1x_boot.c b/arch/arm/src/a1x/a1x_boot.c index 59d675661abee..f4be425153cbc 100644 --- a/arch/arm/src/a1x/a1x_boot.c +++ b/arch/arm/src/a1x/a1x_boot.c @@ -27,7 +27,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif @@ -128,7 +128,7 @@ static inline void a1x_setupmappings(void) ****************************************************************************/ #if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && \ - defined(CONFIG_PAGING) + defined(CONFIG_LEGACY_PAGING) static void a1x_vectorpermissions(uint32_t mmuflags) { /* The PTE for the beginning of ISRAM is at the base of the L2 page table */ @@ -226,7 +226,7 @@ static void a1x_copyvectorblock(void) * read only, then temporarily mark the mapping write-able (non-buffered). */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING a1x_vectorpermissions(MMU_L2_VECTRWFLAGS); #endif @@ -250,7 +250,7 @@ static void a1x_copyvectorblock(void) /* Make the vectors read-only, cacheable again */ -#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING) +#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_LEGACY_PAGING) a1x_vectorpermissions(MMU_L2_VECTORFLAGS); #endif } diff --git a/arch/arm/src/a1x/hardware/a10_memorymap.h b/arch/arm/src/a1x/hardware/a10_memorymap.h index 40465dc56bbcc..55f849faf7ebc 100644 --- a/arch/arm/src/a1x/hardware/a10_memorymap.h +++ b/arch/arm/src/a1x/hardware/a10_memorymap.h @@ -28,6 +28,15 @@ #include #include +/* A1X Virtual (mapped) Memory Map + * + * board_memorymap.h contains special mappings that are needed when a ROM + * memory map is used. It is included in this odd location because it + * depends on some the virtual address definitions provided above. + */ + +#include + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -279,15 +288,6 @@ #define A1X_DDR_MMUFLAGS MMU_MEMFLAGS #define A1X_BROM_MMUFLAGS MMU_ROMFLAGS -/* A1X Virtual (mapped) Memory Map - * - * board_memorymap.h contains special mappings that are needed when a ROM - * memory map is used. It is included in this odd location because it - * depends on some the virtual address definitions provided above. - */ - -#include - /* A1X Virtual (mapped) Memory Map. These are the mappings that will * be created if the page table lies in RAM. If the platform has another, * read-only, pre-initialized page table (perhaps in ROM), then the board.h @@ -441,11 +441,11 @@ #else /* PGTABLE_BASE_PADDR || PGTABLE_BASE_VADDR */ - /* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory - * map probably do not apply because paging logic will probably partition - * the SRAM section differently. In particular, if the page table is - * located at the end of SRAM, then the virtual page table address defined - * below will probably be in error. + /* If CONFIG_LEGACY_PAGING is selected, then parts of the 1-to-1 virtual + * memory map probably do not apply because paging logic will probably + * partition the SRAM section differently. In particular, if the page + * table is located at the end of SRAM, then the virtual page table address + * defined below will probably be in error. * In that case PGTABLE_BASE_VADDR is defined in the file mmu.h * * We must declare the page table at the bottom or at the top of internal @@ -514,8 +514,8 @@ * * 1) One mapping the vector table (only when CONFIG_ARCH_LOWVECTORS is not * defined). - * 2) If on-demand paging is supported (CONFIG_PAGING=y), than an additional - * L2 page table is needed. + * 2) If on-demand paging is supported (CONFIG_LEGACY_PAGING=y), than an + * additional L2 page table is needed. */ #ifndef CONFIG_ARCH_LOWVECTORS @@ -546,7 +546,7 @@ /* Paging L2 page table base addresses * - * NOTE: If CONFIG_PAGING is defined, mmu.h will re-assign the virtual + * NOTE: If CONFIG_LEGACY_PAGING is defined, mmu.h will re-assign the virtual * address of the page table. */ diff --git a/arch/arm/src/am335x/am335x_boot.c b/arch/arm/src/am335x/am335x_boot.c index ee68fad9adba0..2bd19b54851a5 100644 --- a/arch/arm/src/am335x/am335x_boot.c +++ b/arch/arm/src/am335x/am335x_boot.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif @@ -198,7 +198,7 @@ static inline void am335x_remap(void) ****************************************************************************/ #if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && \ - defined(CONFIG_PAGING) + defined(CONFIG_LEGACY_PAGING) static void am335x_vectorpermissions(uint32_t mmuflags) { /* The PTE for the beginning of OCMC0 RAM is at the base of the L2 page @@ -307,7 +307,7 @@ static void am335x_copyvectorblock(void) uint32_t *end; uint32_t *dest; -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /* If we are using re-mapped vectors in an area that has been marked * read only, then temporarily mark the mapping write-able (non-buffered). */ @@ -334,7 +334,7 @@ static void am335x_copyvectorblock(void) *dest++ = *src++; } -#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING) +#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_LEGACY_PAGING) /* Make the vectors read-only, cache-able again */ am335x_vectorpermissions(MMU_L2_VECTORFLAGS); diff --git a/arch/arm/src/am335x/am335x_lcdc.c b/arch/arm/src/am335x/am335x_lcdc.c index 5e9608450eb7c..a650032bb171f 100644 --- a/arch/arm/src/am335x/am335x_lcdc.c +++ b/arch/arm/src/am335x/am335x_lcdc.c @@ -338,7 +338,7 @@ static int am335x_lcd_interrupt(int irq, void *context, void *arg) static uint32_t am335x_lcd_divisor(uint32_t reference, uint32_t frequency) { uint32_t div; - uint32_t delta; + int32_t delta; uint32_t mindelta; int i; @@ -374,7 +374,7 @@ static int am335x_set_refclk(uint32_t frequency) uint32_t sysclk; uint32_t mul; uint32_t div; - uint32_t delta; + int32_t delta; uint32_t mindelta; int timeout; int i; diff --git a/arch/arm/src/am335x/hardware/am3358_memorymap.h b/arch/arm/src/am335x/hardware/am3358_memorymap.h index e745691b928f0..4004f204fc032 100644 --- a/arch/arm/src/am335x/hardware/am3358_memorymap.h +++ b/arch/arm/src/am335x/hardware/am3358_memorymap.h @@ -28,6 +28,15 @@ #include #include +/* AM335X Virtual (mapped) Memory Map + * + * board_memorymap.h contains special mappings that are needed when a ROM + * memory map is used. It is included in this odd location because it + * depends on some the virtual address definitions provided above. + */ + +#include + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -250,15 +259,6 @@ #define AM335X_PERIPH_MMUFLAGS MMU_IOFLAGS #define AM335X_DDR_MMUFLAGS MMU_MEMFLAGS -/* AM335X Virtual (mapped) Memory Map - * - * board_memorymap.h contains special mappings that are needed when a ROM - * memory map is used. It is included in this odd location because it - * depends on some the virtual address definitions provided above. - */ - -#include - /* AM335X Virtual (mapped) Memory Map. These are the mappings that will * be created if the page table lies in RAM. If the platform has another, * read-only, pre-initialized page table (perhaps in ROM), then the board.h @@ -461,12 +461,12 @@ #else /* PGTABLE_BASE_PADDR || PGTABLE_BASE_VADDR */ - /* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory - * map probably do not apply because paging logic will probably partition - * the SRAM section differently. In particular, if the page table is - * located at the end of SRAM, then the virtual page table address defined - * below will probably be in error. In that case PGTABLE_BASE_VADDR is - * defined in the file mmu.h + /* If CONFIG_LEGACY_PAGING is selected, then parts of the 1-to-1 virtual + * memory map probably do not apply because paging logic will probably + * partition the SRAM section differently. In particular, if the page + * table is located at the end of SRAM, then the virtual page table address + * defined below will probably be in error. + * In that case PGTABLE_BASE_VADDR is defined in the file mmu.h * * We must declare the page table at the bottom or at the top of internal * SRAM. We pick the bottom of internal SRAM *unless* there are vectors @@ -547,7 +547,7 @@ /* Paging L2 page table base addresses * - * NOTE: If CONFIG_PAGING is defined, mmu.h will re-assign the virtual + * NOTE: If CONFIG_LEGACY_PAGING is defined, mmu.h will re-assign the virtual * address of the page table. */ diff --git a/arch/arm/src/arm/Make.defs b/arch/arm/src/arm/Make.defs index cbe3fa4a8b5ea..ceed32eb30e6f 100644 --- a/arch/arm/src/arm/Make.defs +++ b/arch/arm/src/arm/Make.defs @@ -29,10 +29,9 @@ CMN_CSRCS += arm_prefetchabort.c arm_schedulesigaction.c CMN_CSRCS += arm_sigdeliver.c arm_syscall.c arm_tcbinfo.c CMN_CSRCS += arm_undefinedinsn.c -CMN_ASRCS += arm_cache.S arm_vectoraddrexcptn.S -CMN_ASRCS += arm_vectors.S arm_vectortab.S +CMN_ASRCS += arm_cache.S arm_vectors.S arm_vectortab.S CMN_ASRCS += arm_saveusercontext.S -ifeq ($(CONFIG_PAGING),y) +ifeq ($(CONFIG_LEGACY_PAGING),y) CMN_CSRCS += arm_pginitialize.c arm_checkmapping.c arm_allocpage.c arm_va2pte.c endif diff --git a/arch/arm/src/arm/arm_allocpage.c b/arch/arm/src/arm/arm_allocpage.c index 480a034674ca9..003ffa7267a4a 100644 --- a/arch/arm/src/arm/arm_allocpage.c +++ b/arch/arm/src/arm/arm_allocpage.c @@ -32,7 +32,7 @@ #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING #include @@ -171,7 +171,7 @@ int up_allocpage(struct tcb_s *tcb, void **vpage) */ pgndx = g_pgndx++; - if (g_pgndx >= CONFIG_PAGING) + if (g_pgndx >= CONFIG_LEGACY_PAGING) { g_pgndx = 0; g_pgwrap = true; @@ -225,4 +225,4 @@ int up_allocpage(struct tcb_s *tcb, void **vpage) return OK; } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/arm/arm_checkmapping.c b/arch/arm/src/arm/arm_checkmapping.c index fd935ec72a7de..5657cf3ae4f3c 100644 --- a/arch/arm/src/arm/arm_checkmapping.c +++ b/arch/arm/src/arm/arm_checkmapping.c @@ -35,7 +35,7 @@ #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /**************************************************************************** * Pre-processor Definitions @@ -106,4 +106,4 @@ bool up_checkmapping(struct tcb_s *tcb) return (*pte != 0); } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/arm/arm_dataabort.c b/arch/arm/src/arm/arm_dataabort.c index ae59292ec9e02..642569625f8dd 100644 --- a/arch/arm/src/arm/arm_dataabort.c +++ b/arch/arm/src/arm/arm_dataabort.c @@ -34,7 +34,7 @@ #include "sched/sched.h" #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include # include "arm.h" #endif @@ -49,8 +49,8 @@ * Input Parameters: * regs - The standard, ARM register save array. * - * If CONFIG_PAGING is selected in the NuttX configuration file, then these - * additional input values are expected: + * If CONFIG_LEGACY_PAGING is selected in the NuttX configuration file, then + * these additional input values are expected: * * far - Fault address register. On a data abort, the ARM MMU places the * miss virtual address (MVA) into the FAR register. This is the address @@ -65,11 +65,11 @@ * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING void arm_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr) { struct tcb_s *tcb = this_task(); -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING uint32_t *savestate; /* Save the saved processor context in CURRENT_REGS where it can be @@ -80,7 +80,7 @@ void arm_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr) #endif CURRENT_REGS = regs; -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /* In the NuttX on-demand paging implementation, only the read-only, .text * section is paged. However, the ARM compiler generated PC-relative data * fetches from within the .text sections. Also, it is customary to locate @@ -149,7 +149,7 @@ void arm_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr) PANIC_WITH_REGS("panic", regs); } -#else /* CONFIG_PAGING */ +#else /* CONFIG_LEGACY_PAGING */ void arm_dataabort(uint32_t *regs) { @@ -165,4 +165,4 @@ void arm_dataabort(uint32_t *regs) PANIC_WITH_REGS("panic", regs); } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/arm/arm_head.S b/arch/arm/src/arm/arm_head.S index e087c61fb7314..c46bae2ec255d 100644 --- a/arch/arm/src/arm/arm_head.S +++ b/arch/arm/src/arm/arm_head.S @@ -28,7 +28,7 @@ #include "chip.h" #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include # include "pg_macros.h" #endif @@ -128,7 +128,7 @@ * NPAGE1=(1024 -((a) & 0x00000fff) >> 2) NPAGE1=1-1024 */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # define PG_L2_TEXT_PBASE (PG_L2_TEXT_PADDR & PG_L1_PADDRMASK) # define PG_L2_TEXT_NPAGE1 (PTE_NPAGES - ((PG_L2_TEXT_PADDR & ~PG_L1_PADDRMASK) >> 2)) # define PG_L2_PGTABLE_PBASE (PG_L2_PGTABLE_PADDR & PG_L1_PADDRMASK) @@ -253,7 +253,7 @@ __start: str r3, [r4, r0, lsr #18] /* identity mapping */ #endif -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /* Map the read-only .text region in place. This must be done * before the MMU is enabled and the virtual addressing takes @@ -292,7 +292,7 @@ __start: ldmia r0, {r0, r1, r2, r3} pg_l2map r0, r1, r2, r3, r5 -#else /* CONFIG_PAGING */ +#else /* CONFIG_LEGACY_PAGING */ #ifdef CONFIG_IDENTITY_TEXTMAP mksection r0, r4 /* r0=phys. base section */ @@ -317,7 +317,7 @@ __start: * can only be assumed to cover the initial .text region. */ -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ #endif /* CONFIG_ARCH_ROMPGTABLE */ /* The following logic will set up the ARM920/ARM926 for normal operation. @@ -443,7 +443,7 @@ __start: .long PGTABLE_BASE_VADDR /* Virtual start of page table */ #endif -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING .Ltxtspan: .long PG_L1_TEXT_PADDR /* Physical address in the L1 table */ @@ -471,7 +471,7 @@ __start: .long PG_PGTABLE_NPAGES /* Total mapped page table pages */ .long MMU_L2_PGTABFLAGS /* L2 MMU flags to use */ -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ .size __start, .-__start /**************************************************************************** @@ -501,7 +501,7 @@ __start: str r0, [r4, r3, lsr #18] /* Undo identity mapping */ #endif -#if defined(CONFIG_PAGING) +#if defined(CONFIG_LEGACY_PAGING) /* Populate the L1 table for the data region */ adr r0, .Ldataspan @@ -557,7 +557,7 @@ __start: * will still probably be located in a separate (virtual) address region. */ -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ #endif /* CONFIG_ARCH_ROMPGTABLE */ /* Zero BSS and set up the stack pointer */ @@ -583,7 +583,7 @@ __start: * address region. */ -#if defined(CONFIG_BOOT_RUNFROMFLASH) || defined(CONFIG_PAGING) +#if defined(CONFIG_BOOT_RUNFROMFLASH) || defined(CONFIG_LEGACY_PAGING) adr r3, .Ldatainit ldmia r3, {r0, r1, r2} @@ -622,14 +622,14 @@ __start: .long _ebss .long _ebss+CONFIG_IDLETHREAD_STACKSIZE -#if !defined(CONFIG_PAGING) && !defined(CONFIG_BOOT_RUNFROMFLASH) +#if !defined(CONFIG_LEGACY_PAGING) && !defined(CONFIG_BOOT_RUNFROMFLASH) .LCnuttxpaddr: .long NUTTX_START_PADDR & 0xfff00000 #endif -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING .Ldataspan: .long PG_L1_DATA_VADDR /* Virtual address in the L1 table */ @@ -644,9 +644,9 @@ __start: .long PG_DATA_NPAGES /* Number of pages in the data region */ .long MMU_L2_DATAFLAGS /* L2 MMU flags to use */ -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ -#if defined(CONFIG_BOOT_RUNFROMFLASH) || defined(CONFIG_PAGING) +#if defined(CONFIG_BOOT_RUNFROMFLASH) || defined(CONFIG_LEGACY_PAGING) .Ldatainit: .long _eronly /* Where .data defaults are stored in FLASH */ .long _sdata /* Where .data needs to reside in SDRAM */ diff --git a/arch/arm/src/arm/arm_pginitialize.c b/arch/arm/src/arm/arm_pginitialize.c index 22a1aed7db21f..fb5fb5340ddfb 100644 --- a/arch/arm/src/arm/arm_pginitialize.c +++ b/arch/arm/src/arm/arm_pginitialize.c @@ -31,7 +31,7 @@ #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /**************************************************************************** * Pre-processor Definitions @@ -77,4 +77,4 @@ void arm_pginitialize(void) */ } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/arm/arm_prefetchabort.c b/arch/arm/src/arm/arm_prefetchabort.c index fbfa62dc59b73..c96143066e3a6 100644 --- a/arch/arm/src/arm/arm_prefetchabort.c +++ b/arch/arm/src/arm/arm_prefetchabort.c @@ -30,7 +30,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif @@ -65,7 +65,7 @@ void arm_prefetchabort(uint32_t *regs) { -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING uint32_t *savestate; /* Save the saved processor context in CURRENT_REGS where it can be @@ -76,7 +76,7 @@ void arm_prefetchabort(uint32_t *regs) #endif CURRENT_REGS = regs; -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /* Get the (virtual) address of instruction that caused the prefetch * abort. When the exception occurred, this address was provided in the * lr register and this value was saved in the context save area as the PC diff --git a/arch/arm/src/arm/arm_va2pte.c b/arch/arm/src/arm/arm_va2pte.c index 4e8ae09745d58..7f1715cb216a1 100644 --- a/arch/arm/src/arm/arm_va2pte.c +++ b/arch/arm/src/arm/arm_va2pte.c @@ -35,7 +35,7 @@ #include "pg_macros.h" #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /**************************************************************************** * Pre-processor Definitions @@ -103,4 +103,4 @@ uint32_t *arm_va2pte(uintptr_t vaddr) return &L2[ndx]; } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/arm/arm_vectoraddrexcptn.S b/arch/arm/src/arm/arm_vectoraddrexcptn.S deleted file mode 100644 index 5d32fd0341986..0000000000000 --- a/arch/arm/src/arm/arm_vectoraddrexcptn.S +++ /dev/null @@ -1,67 +0,0 @@ -/**************************************************************************** - * arch/arm/src/arm/arm_vectoraddrexceptn.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - - .file "arm_vectoraddrexcptn.S" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Symbols - ****************************************************************************/ - - .globl arm_vectoraddrexcptn - -/**************************************************************************** - * Assembly Macros - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - - .text - .syntax unified - .arm - -/**************************************************************************** - * Name: arm_vectoraddrexcptn - * - * Description: - * Shouldn't happen. This exception handler is in a separate file from - * other vector handlers because some processors do not support the - * Address Exception vector. - * - ****************************************************************************/ - - .globl arm_vectoraddrexcptn - .type arm_vectoraddrexcptn, %function -arm_vectoraddrexcptn: - b arm_vectoraddrexcptn - .size arm_vectoraddrexcptn, . - arm_vectoraddrexcptn - .end diff --git a/arch/arm/src/arm/arm_vectors.S b/arch/arm/src/arm/arm_vectors.S index c1d234ceef5ae..bad5c411420aa 100644 --- a/arch/arm/src/arm/arm_vectors.S +++ b/arch/arm/src/arm/arm_vectors.S @@ -397,7 +397,7 @@ arm_vectordata: mov fp, #0 /* Init frame pointer */ mov r0, sp /* Get r0=xcp */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING mrc p15, 0, r1, c6, c0, 0 /* Get R1=FAR */ mrc p15, 0, r2, c5, c0, 0 /* Get r2=FSR */ #endif @@ -636,6 +636,22 @@ arm_vectorfiq: subs pc, lr, #4 .size arm_vectorfiq, . - arm_vectorfiq +/**************************************************************************** + * Name: arm_vectoraddrexcptn + * + * Description: + * Shouldn't happen. This exception handler is in a separate file from + * other vector handlers because some processors do not support the + * Address Exception vector. + * + ****************************************************************************/ + + .globl arm_vectoraddrexcptn + .type arm_vectoraddrexcptn, %function +arm_vectoraddrexcptn: + b arm_vectoraddrexcptn + .size arm_vectoraddrexcptn, . - arm_vectoraddrexcptn + /**************************************************************************** * Name: g_intstackalloc/g_intstacktop ****************************************************************************/ diff --git a/arch/arm/src/arm/pg_macros.h b/arch/arm/src/arm/pg_macros.h index d1c59b57a7473..f890113e3edbf 100644 --- a/arch/arm/src/arm/pg_macros.h +++ b/arch/arm/src/arm/pg_macros.h @@ -41,14 +41,14 @@ /* Configuration ************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /* Sanity check -- we cannot be using a ROM page table and supporting on- * demand paging. */ #ifdef CONFIG_ARCH_ROMPGTABLE -# error "Cannot support both CONFIG_PAGING and CONFIG_ARCH_ROMPGTABLE" +# error "Cannot support both CONFIG_LEGACY_PAGING and CONFIG_ARCH_ROMPGTABLE" #endif /* Virtual Page Table Location **********************************************/ @@ -342,7 +342,7 @@ #define PG_POOL_PGPADDR(ndx) (PG_PAGED_PBASE + ((ndx) << PAGESHIFT)) #define PG_POOL_PGVADDR(ndx) (PG_PAGED_VBASE + ((ndx) << PAGESHIFT)) -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ /**************************************************************************** * Assembly Macros @@ -355,8 +355,8 @@ * * Description: * Write several, contiguous L2 page table entries. npages entries will be - * written. This macro is used when CONFIG_PAGING is enable. This case, - * it is used as follows: + * written. This macro is used when CONFIG_LEGACY_PAGING is enable. + * This case, it is used as follows: * * ldr r0, =PGTABLE_L2_BASE_PADDR <-- Address in L2 table * ldr r1, =PG_LOCKED_PBASE <-- Physical page memory address @@ -385,7 +385,7 @@ * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING .macro pg_l2map, l2, ppage, npages, mmuflags, tmp b 2f 1: @@ -418,7 +418,7 @@ cmp \npages, #0 bgt 1b .endm -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ /**************************************************************************** * Name: pg_l1span @@ -426,8 +426,8 @@ * Description: * Write several, contiguous unmapped coarse L1 page table entries. As * many entries will be written as many as needed to span npages. This - * macro is used when CONFIG_PAGING is enable. This case, it is used as - * follows: + * macro is used when CONFIG_LEGACY_PAGING is enable. + * This case, it is used as follows: * * ldr r0, =PG_L1_PGTABLE_PADDR <-- Address in the L1 table * ldr r1, =PG_L2_PGTABLE_PADDR <-- Physical address of L2 page table @@ -461,7 +461,7 @@ * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING .macro pg_l1span, l1, l2, npages, ppage, mmuflags, tmp b 2f 1: @@ -499,7 +499,7 @@ bgt 1b .endm -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ #endif /* __ASSEMBLY__ */ /**************************************************************************** diff --git a/arch/arm/src/armv6-m/arm_exception.S b/arch/arm/src/armv6-m/arm_exception.S index 6408d4d1f1ae7..22dea51a5a2f0 100644 --- a/arch/arm/src/armv6-m/arm_exception.S +++ b/arch/arm/src/armv6-m/arm_exception.S @@ -100,6 +100,7 @@ exception_common: mrs r1, msp /* R1=The main stack pointer */ subs r1, #SW_XCPT_SIZE /* R1=Beginning of context array on the stack */ msr msp, r1 /* Reserved stack space */ + isb sy b 2f 1: @@ -160,6 +161,7 @@ exception_common: mov r2, r1 /* Reserve signal context */ subs r2, r2, #XCPTCONTEXT_SIZE msr msp, r2 /* We are using the main stack pointer */ + isb sy 3: #endif @@ -197,10 +199,12 @@ exception_common: lsls r0, #(31 - EXC_RETURN_PROCESS_BITNO) /* Move to bit 31 */ bmi 4f /* Test bit 31 */ msr msp, r1 /* R1=The main stack pointer */ + isb sy b 5f 4: msr psp, r1 /* R1=The process stack pointer */ + isb sy 5: diff --git a/arch/arm/src/armv6-m/arm_initialstate.c b/arch/arm/src/armv6-m/arm_initialstate.c index b52c8f3f9b572..979e77e3bf055 100644 --- a/arch/arm/src/armv6-m/arm_initialstate.c +++ b/arch/arm/src/armv6-m/arm_initialstate.c @@ -157,11 +157,7 @@ void up_initial_state(struct tcb_s *tcb) noinline_function void arm_initialize_stack(void) { -#ifdef CONFIG_SMP - uint32_t stack = (uint32_t)arm_intstack_top(); -#else - uint32_t stack = (uint32_t)g_intstacktop; -#endif + uint32_t stack = up_get_intstackbase(up_cpu_index()) + INTSTACK_SIZE; uint32_t tempa = 0; uint32_t tempb = 2; @@ -172,6 +168,7 @@ noinline_function void arm_initialize_stack(void) "mov %1, sp\n" "msr psp, %1\n" + "isb sy\n" /* Select PSP */ @@ -183,6 +180,7 @@ noinline_function void arm_initialize_stack(void) /* Initialize MSP */ "msr msp, %0\n" + "isb sy\n" : : "r" (stack), "r" (tempa), "r" (tempb) : "memory"); diff --git a/arch/arm/src/armv7-a/CMakeLists.txt b/arch/arm/src/armv7-a/CMakeLists.txt index 543cc6e235616..33660f6d3611a 100644 --- a/arch/arm/src/armv7-a/CMakeLists.txt +++ b/arch/arm/src/armv7-a/CMakeLists.txt @@ -25,8 +25,7 @@ set(SRCS arm_vectortab.S) # Common assembly language files -list(APPEND SRCS arm_cpuhead.S arm_vectoraddrexcptn.S arm_vectors.S - arm_saveusercontext.S) +list(APPEND SRCS arm_cpuhead.S arm_vectors.S arm_saveusercontext.S) # Common C source files @@ -61,7 +60,7 @@ if(CONFIG_ARMV7A_L2CC_PL310) list(APPEND SRCS arm_l2cc_pl310.c) endif() -if(CONFIG_PAGING) +if(CONFIG_LEGACY_PAGING) list( APPEND SRCS @@ -75,8 +74,14 @@ else() endif() if(CONFIG_ARCH_ADDRENV) - list(APPEND SRCS arm_addrenv.c arm_addrenv_utils.c arm_addrenv_perms.c - arm_pgalloc.c) + list( + APPEND + SRCS + arm_addrenv.c + arm_addrenv_utils.c + arm_addrenv_perms.c + arm_pgalloc.c + arm_addrenv_pgmap.c) if(CONFIG_ARCH_STACK_DYNAMIC) list(APPEND SRCS arm_addrenv_ustack.c) endif() @@ -114,4 +119,8 @@ if(CONFIG_ARCH_HAVE_PSCI) list(APPEND SRCS arm_cpu_psci.c arm_smccc.S) endif() +if(CONFIG_ARCH_HIPRI_INTERRUPT) + list(APPEND SRCS arm_dofiq.c) +endif() + target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/armv7-a/Kconfig b/arch/arm/src/armv7-a/Kconfig index 8fb14d602510b..232b96e23a3ba 100644 --- a/arch/arm/src/armv7-a/Kconfig +++ b/arch/arm/src/armv7-a/Kconfig @@ -8,6 +8,8 @@ comment "ARMv7-A Configuration Options" config ARMV7A_HAVE_GICv2 bool select ARCH_HAVE_IRQTRIGGER + select ARCH_HAVE_IRQPRIO + select ARCH_HAVE_HIPRI_INTERRUPT default n ---help--- Selected by the configuration tool if the architecture supports the @@ -173,14 +175,6 @@ endif # ARCH_L2CACHE endmenu # L2 Cache Configuration endif # ARMV7A_HAVE_L2CC -config ARMV7A_DECODEFIQ - bool "FIQ Handler" - default n - ---help--- - Select this option if your platform supports the function - arm_decodefiq(). This is used primarily to support secure TrustZone - interrupts received on the FIQ vector. - config ARMV7A_ALIGNMENT_TRAP bool "Enable Alignment Check at __start" default n diff --git a/arch/arm/src/armv7-a/Make.defs b/arch/arm/src/armv7-a/Make.defs index 6ea56bba38849..7227039291e7c 100644 --- a/arch/arm/src/armv7-a/Make.defs +++ b/arch/arm/src/armv7-a/Make.defs @@ -36,8 +36,7 @@ endif # Common assembly language files -CMN_ASRCS += arm_cpuhead.S arm_vectoraddrexcptn.S arm_vectors.S -CMN_ASRCS += arm_saveusercontext.S +CMN_ASRCS += arm_cpuhead.S arm_vectors.S arm_saveusercontext.S # Common C source files @@ -56,7 +55,7 @@ ifeq ($(CONFIG_ARMV7A_L2CC_PL310),y) CMN_CSRCS += arm_l2cc_pl310.c endif -ifeq ($(CONFIG_PAGING),y) +ifeq ($(CONFIG_LEGACY_PAGING),y) CMN_CSRCS += arm_allocpage.c arm_checkmapping.c arm_pginitialize.c CMN_CSRCS += arm_va2pte.c CMN_ASRCS += arm_pghead.S @@ -66,6 +65,7 @@ endif ifeq ($(CONFIG_ARCH_ADDRENV),y) CMN_CSRCS += arm_addrenv.c arm_addrenv_utils.c arm_addrenv_perms.c arm_pgalloc.c + CMN_CSRCS += arm_addrenv_pgmap.c ifeq ($(CONFIG_ARCH_STACK_DYNAMIC),y) CMN_CSRCS += arm_addrenv_ustack.c endif @@ -98,3 +98,7 @@ ifeq ($(CONFIG_ARCH_HAVE_PSCI),y) CMN_ASRCS += arm_smccc.S CMN_CSRCS += arm_cpu_psci.c endif + +ifeq ($(CONFIG_ARCH_HIPRI_INTERRUPT),y) + CMN_CSRCS += arm_dofiq.c +endif diff --git a/arch/arm/src/armv7-a/arm_addrenv_pgmap.c b/arch/arm/src/armv7-a/arm_addrenv_pgmap.c new file mode 100644 index 0000000000000..3ced8813fecbd --- /dev/null +++ b/arch/arm/src/armv7-a/arm_addrenv_pgmap.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * arch/arm/src/armv7-a/arm_addrenv_pgmap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "pgalloc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_addrenv_page_vaddr + * + * Description: + * Find the kernel virtual address associated with physical page. + * + * Input Parameters: + * page - The page physical address. + * + * Returned Value: + * Page kernel virtual address on success; NULL on failure. + * + ****************************************************************************/ + +uintptr_t up_addrenv_page_vaddr(uintptr_t page) +{ + return arm_pgvaddr(page); +} + +/**************************************************************************** + * Name: up_addrenv_page_wipe + * + * Description: + * Wipe a page of physical memory, first mapping it into kernel virtual + * memory. + * + * Input Parameters: + * page - The page physical address. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void up_addrenv_page_wipe(uintptr_t page) +{ + uintptr_t vaddr = arm_pgvaddr(page); + memset((void *)vaddr, 0, MM_PGSIZE); +} diff --git a/arch/arm/src/armv7-a/arm_allocpage.c b/arch/arm/src/armv7-a/arm_allocpage.c index aed3a4d6a7391..4c897d91ec174 100644 --- a/arch/arm/src/armv7-a/arm_allocpage.c +++ b/arch/arm/src/armv7-a/arm_allocpage.c @@ -32,7 +32,7 @@ #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING #include @@ -163,7 +163,7 @@ int arm_allocpage(struct tcb_s *tcb, void **vpage) */ pgndx = g_pgndx++; - if (g_pgndx >= CONFIG_PAGING) + if (g_pgndx >= CONFIG_LEGACY_PAGING) { g_pgndx = 0; g_pgwrap = true; @@ -219,4 +219,4 @@ int arm_allocpage(struct tcb_s *tcb, void **vpage) return OK; } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/armv7-a/arm_checkmapping.c b/arch/arm/src/armv7-a/arm_checkmapping.c index 3a5c16d4fbb87..41ce634168b69 100644 --- a/arch/arm/src/armv7-a/arm_checkmapping.c +++ b/arch/arm/src/armv7-a/arm_checkmapping.c @@ -33,7 +33,7 @@ #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /**************************************************************************** * Public Functions @@ -92,4 +92,4 @@ bool arm_checkmapping(struct tcb_s *tcb) return (*pte != 0); } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/armv7-a/arm_cpupause.c b/arch/arm/src/armv7-a/arm_cpupause.c index ed098c4ba77e7..4c7b6a71ddb56 100644 --- a/arch/arm/src/armv7-a/arm_cpupause.c +++ b/arch/arm/src/armv7-a/arm_cpupause.c @@ -85,7 +85,7 @@ bool up_cpu_pausereq(int cpu) } /**************************************************************************** - * Name: up_cpu_paused + * Name: up_cpu_paused_save * * Description: * Handle a pause request from another CPU. Normally, this logic is @@ -94,16 +94,8 @@ bool up_cpu_pausereq(int cpu) * pause operation in other contexts where the interrupt cannot be taken * in order to avoid deadlocks. * - * This function performs the following operations: - * - * 1. It saves the current task state at the head of the current assigned - * task list. - * 2. It waits on a spinlock, then - * 3. Returns from interrupt, restoring the state of the new task at the - * head of the ready to run list. - * * Input Parameters: - * cpu - The index of the CPU to be paused + * None * * Returned Value: * On success, OK is returned. Otherwise, a negated errno value indicating @@ -111,7 +103,7 @@ bool up_cpu_pausereq(int cpu) * ****************************************************************************/ -int up_cpu_paused(int cpu) +int up_cpu_paused_save(void) { struct tcb_s *tcb = this_task(); @@ -131,6 +123,38 @@ int up_cpu_paused(int cpu) arm_savestate(tcb->xcp.regs); + return OK; +} + +/**************************************************************************** + * Name: up_cpu_paused + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. + * + * This function performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. + * + * Input Parameters: + * cpu - The index of the CPU to be paused + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused(int cpu) +{ /* Release the g_cpu_paused spinlock to synchronize with the * requesting CPU. */ @@ -147,11 +171,31 @@ int up_cpu_paused(int cpu) spin_lock(&g_cpu_wait[cpu]); - /* This CPU has been resumed. Restore the exception context of the TCB at - * the (new) head of the assigned task list. - */ + spin_unlock(&g_cpu_wait[cpu]); + spin_unlock(&g_cpu_resumed[cpu]); + + return OK; +} - tcb = this_task(); +/**************************************************************************** + * Name: up_cpu_paused_restore + * + * Description: + * Restore the state of the CPU after it was paused via up_cpu_pause(), + * and resume normal tasking. + * + * Input Parameters: + * None + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused_restore(void) +{ + struct tcb_s *tcb = this_task(); #ifdef CONFIG_SCHED_INSTRUMENTATION /* Notify that we have resumed */ @@ -168,8 +212,6 @@ int up_cpu_paused(int cpu) */ arm_restorestate(tcb->xcp.regs); - spin_unlock(&g_cpu_wait[cpu]); - spin_unlock(&g_cpu_resumed[cpu]); return OK; } diff --git a/arch/arm/src/armv7-a/arm_dataabort.c b/arch/arm/src/armv7-a/arm_dataabort.c index 2c2952b1299d6..13f562baa8bf9 100644 --- a/arch/arm/src/armv7-a/arm_dataabort.c +++ b/arch/arm/src/armv7-a/arm_dataabort.c @@ -33,7 +33,7 @@ #include "sched/sched.h" #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include # include "arm.h" #endif @@ -48,8 +48,8 @@ * Input Parameters: * regs - The standard, ARM register save array. * - * If CONFIG_PAGING is selected in the NuttX configuration file, then these - * additional input values are expected: + * If CONFIG_LEGACY_PAGING is selected in the NuttX configuration file, then + * these additional input values are expected: * * dfar - Fault address register. On a data abort, the ARM MMU places the * miss virtual address (MVA) into the DFAR register. This is the @@ -64,7 +64,7 @@ * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr) { struct tcb_s *tcb = this_task(); @@ -144,7 +144,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr) return regs; /* To keep the compiler happy */ } -#else /* CONFIG_PAGING */ +#else /* CONFIG_LEGACY_PAGING */ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr) { @@ -162,4 +162,4 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr) return regs; /* To keep the compiler happy */ } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/armv7-a/arm_dofiq.c b/arch/arm/src/armv7-a/arm_dofiq.c new file mode 100644 index 0000000000000..ffa2ee851f23a --- /dev/null +++ b/arch/arm/src/armv7-a/arm_dofiq.c @@ -0,0 +1,63 @@ +/**************************************************************************** + * arch/arm/src/armv7-a/arm_dofiq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "gic.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_dofiq + * + * Description: + * Receives the decoded GIC interrupt information and dispatches control + * to the attached fiq handler. It is not allowed to call OS functions + * within a FIQ handler. + * + ****************************************************************************/ + +uint32_t *arm_dofiq(int fiq, uint32_t *regs) +{ + board_autoled_on(LED_INIRQ); + +#ifdef CONFIG_SUPPRESS_INTERRUPTS + PANIC(); +#else + irq_dispatch(fiq, regs); +#endif + + board_autoled_off(LED_INIRQ); + return regs; +} diff --git a/arch/arm/src/armv7-a/arm_gicv2.c b/arch/arm/src/armv7-a/arm_gicv2.c index 0917ae700a880..0dbe6be1708b7 100644 --- a/arch/arm/src/armv7-a/arm_gicv2.c +++ b/arch/arm/src/armv7-a/arm_gicv2.c @@ -35,13 +35,19 @@ #include "arm_internal.h" #include "gic.h" +#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_TRUSTZONE_NONSECURE) +# if defined(CONFIG_ARCH_HIPRI_INTERRUPT) +# error "ARCH_HIPRI_INTERRUPT must configure with ARCH_TRUSTZONE_DISABLED or no trustzone" +# endif +#endif + #ifdef CONFIG_ARMV7A_HAVE_GICv2 /**************************************************************************** * Public Functions ****************************************************************************/ -#ifdef CONFIG_ARCH_HAVE_TRUSTZONE +#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT) /**************************************************************************** * Name: up_set_secure_irq * @@ -120,8 +126,8 @@ void arm_gic0_initialize(void) /* A processor in Secure State sets: * - * 1. Which interrupts are non-secure (ICDISR). All set to zero (group - * 0). + * 1. Which interrupts are non-secure (ICDISR). All set to one (group + * 1). * 2. Trigger mode of the SPI (ICDICFR). All fields set to 0b01->Level * sensitive, 1-N model. * 3. Interrupt Clear-Enable (ICDICER) @@ -137,7 +143,7 @@ void arm_gic0_initialize(void) for (irq = GIC_IRQ_SPI; irq < nlines; irq += 32) { - putreg32(0x00000000, GIC_ICDISR(irq)); /* SPIs group 0 */ + putreg32(0xffffffff, GIC_ICDISR(irq)); /* SPIs group 1 */ putreg32(0xffffffff, GIC_ICDICER(irq)); /* SPIs disabled */ } @@ -205,7 +211,7 @@ void arm_gic_initialize(void) putreg32(0x000000ff, GIC_ICDISR(0)); #else - putreg32(0x00000000, GIC_ICDISR(0)); /* SGIs and PPIs secure */ + putreg32(0xffffffff, GIC_ICDISR(0)); /* SGIs and PPIs no-secure */ #endif putreg32(0xfe000000, GIC_ICDICER(0)); /* PPIs disabled */ @@ -224,12 +230,17 @@ void arm_gic_initialize(void) * field; the value n (n=0-6) specifies that bits (n+1) through bit 7 are * used in the comparison for interrupt pre-emption. A GIC supports a * minimum of 16 and a maximum of 256 priority levels so not all binary - * point settings may be meaningul. The special value n=7 - * (GIC_ICCBPR_NOPREMPT) disables pre-emption. We disable all pre-emption - * here to prevent nesting of interrupt handling. + * point settings may be meaningul. When CONFIG_ARCH_HIPRI_INTERRUPT is not + * enabled, we set n=7 (GIC_ICCBPR_NOPREMPT) to disable interrupt nesting. + * When CONFIG_ARCH_HIPRI_INTERRUPT is enabled, we set n=6 (GIC_ICCBPR_7_7) + * (g.sssssss) to support group priority. */ +#ifdef CONFIG_ARCH_HIPRI_INTERRUPT + putreg32(GIC_ICCBPR_7_7, GIC_ICCBPR); +#else putreg32(GIC_ICCBPR_NOPREMPT, GIC_ICCBPR); +#endif /* Program the idle priority in the PMR */ @@ -239,7 +250,12 @@ void arm_gic_initialize(void) iccicr = getreg32(GIC_ICCICR); -#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) +#ifdef CONFIG_ARCH_TRUSTZONE_NONSECURE + /* Clear non-secure state ICCICR bits to be configured below */ + + iccicr &= ~(GIC_ICCICRU_EOIMODENS | GIC_ICCICRU_ENABLEGRP1 | + GIC_ICCICRU_FIQBYPDISGRP1 | GIC_ICCICRU_IRQBYPDISGRP1); +#else /* Clear secure state ICCICR bits to be configured below */ iccicr &= ~(GIC_ICCICRS_FIQEN | GIC_ICCICRS_ACKTCTL | GIC_ICCICRS_CBPR | @@ -247,16 +263,9 @@ void arm_gic_initialize(void) GIC_ICCICRS_ENABLEGRP0 | GIC_ICCICRS_ENABLEGRP1 | GIC_ICCICRS_FIQBYPDISGRP0 | GIC_ICCICRS_IRQBYPDISGRP0 | GIC_ICCICRS_FIQBYPDISGRP1 | GIC_ICCICRS_IRQBYPDISGRP1); - -#else - /* Clear non-secure state ICCICR bits to be configured below */ - - iccicr &= ~(GIC_ICCICRU_EOIMODENS | GIC_ICCICRU_ENABLEGRP1 | - GIC_ICCICRU_FIQBYPDISGRP1 | GIC_ICCICRU_IRQBYPDISGRP1); - #endif -#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) +#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT) /* Set FIQn=1 if secure interrupts are to signal using nfiq_c. * * NOTE: Only for processors that operate in secure state. @@ -284,7 +293,17 @@ void arm_gic_initialize(void) # endif #endif -#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) +#ifndef CONFIG_ARCH_TRUSTZONE_SECURE + iccicr |= GIC_ICCICRS_ACKTCTL; +#endif + +#ifdef CONFIG_ARCH_TRUSTZONE_NONSECURE + /* Enable the Group 1 interrupts and disable Group 1 bypass. */ + + iccicr |= (GIC_ICCICRU_ENABLEGRP1 | GIC_ICCICRU_FIQBYPDISGRP1 | + GIC_ICCICRU_IRQBYPDISGRP1); + icddcr = GIC_ICDDCR_ENABLE; +#else /* Enable the Group 0 interrupts, FIQEn and disable Group 0/1 * bypass. */ @@ -293,14 +312,6 @@ void arm_gic_initialize(void) GIC_ICCICRS_FIQBYPDISGRP0 | GIC_ICCICRS_IRQBYPDISGRP0 | GIC_ICCICRS_FIQBYPDISGRP1 | GIC_ICCICRS_IRQBYPDISGRP1); icddcr = (GIC_ICDDCR_ENABLEGRP0 | GIC_ICDDCR_ENABLEGRP1); - -#else - /* Enable the Group 1 interrupts and disable Group 1 bypass. */ - - iccicr |= (GIC_ICCICRU_ENABLEGRP1 | GIC_ICCICRU_FIQBYPDISGRP1 | - GIC_ICCICRU_IRQBYPDISGRP1); - icddcr = GIC_ICDDCR_ENABLE; - #endif /* Write the final ICCICR value to enable the GIC. */ @@ -381,6 +392,7 @@ uint32_t *arm_decodeirq(uint32_t *regs) * ****************************************************************************/ +#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT) uint32_t *arm_decodefiq(uint32_t *regs) { uint32_t regval; @@ -391,9 +403,9 @@ uint32_t *arm_decodefiq(uint32_t *regs) regval = getreg32(GIC_ICCIAR); irq = (regval & GIC_ICCIAR_INTID_MASK) >> GIC_ICCIAR_INTID_SHIFT; -#ifdef CONFIG_ARMV7A_GIC_EOIMODE +# ifdef CONFIG_ARMV7A_GIC_EOIMODE putreg32(regval, GIC_ICCEOIR); -#endif +# endif /* Ignore spurions IRQs. ICCIAR will report 1023 if there is no pending * interrupt. @@ -405,18 +417,23 @@ uint32_t *arm_decodefiq(uint32_t *regs) { /* Dispatch the interrupt */ +# ifdef CONFIG_ARCH_HIPRI_INTERRUPT + regs = arm_dofiq(irq, regs); +# else regs = arm_doirq(irq, regs); +# endif } /* Write to the end-of-interrupt register */ -#ifdef CONFIG_ARMV7A_GIC_EOIMODE +# ifdef CONFIG_ARMV7A_GIC_EOIMODE putreg32(regval, GIC_ICCDIR); -#else +# else putreg32(regval, GIC_ICCEOIR); -#endif +# endif return regs; } +#endif /**************************************************************************** * Name: up_enable_irq @@ -500,6 +517,8 @@ void up_disable_irq(int irq) * * Description: * Set the priority of an IRQ. + * For group0, priority bit[7] must be 0; + * For group1, priority bit[7] must be 1; * * Since this API is not supported on all architectures, it should be * avoided in common implementations where possible. diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S index 9c9ce98de03aa..9e0b0330ff8f0 100644 --- a/arch/arm/src/armv7-a/arm_head.S +++ b/arch/arm/src/armv7-a/arm_head.S @@ -34,8 +34,6 @@ #ifndef IDLE_STACK_BASE #ifdef CONFIG_BOOT_SDRAM_DATA #define IDLE_STACK_BASE IDLE_STACK_VBASE - #elif defined(CONFIG_SMP) - #define IDLE_STACK_BASE _enoinit #else #define IDLE_STACK_BASE _ebss #endif @@ -43,7 +41,7 @@ #define IDLE_STACK_TOP (IDLE_STACK_BASE + CONFIG_IDLETHREAD_STACKSIZE) -#ifndef CONFIG_PAGING +#ifndef CONFIG_LEGACY_PAGING .file "arm_head.S" diff --git a/arch/arm/src/armv7-a/arm_initialstate.c b/arch/arm/src/armv7-a/arm_initialstate.c index c9ea5ec8cad73..81d99fcebb714 100644 --- a/arch/arm/src/armv7-a/arm_initialstate.c +++ b/arch/arm/src/armv7-a/arm_initialstate.c @@ -137,15 +137,19 @@ void up_initial_state(struct tcb_s *tcb) cpsr |= (PSR_I_BIT | PSR_F_BIT); -#else /* CONFIG_SUPPRESS_INTERRUPTS */ - /* Leave IRQs enabled (Also FIQs if CONFIG_ARMV7A_DECODEFIQ is selected) */ +#elif defined(CONFIG_ARCH_TRUSTZONE_SECURE) + /* In tee, we need to disable the IRQ interrupt to make the A core + * policy consistent with the M core. + */ -#ifndef CONFIG_ARMV7A_DECODEFIQ + cpsr |= PSR_I_BIT; +#elif !defined(CONFIG_ARCH_HIPRI_INTERRUPT) + /* Leave IRQs enabled (Also FIQs if CONFIG_ARCH_TRUSTZONE_SECURE or + * CONFIG_ARCH_HIPRI_INTERRUPT is selected) + */ cpsr |= PSR_F_BIT; - -#endif /* !CONFIG_ARMV7A_DECODEFIQ */ -#endif /* CONFIG_SUPPRESS_INTERRUPTS */ +#endif #ifdef CONFIG_ARM_THUMB cpsr |= PSR_T_BIT; diff --git a/arch/arm/src/armv7-a/arm_perf.c b/arch/arm/src/armv7-a/arm_perf.c index 9768bf7d89806..2f50fb87c38e7 100644 --- a/arch/arm/src/armv7-a/arm_perf.c +++ b/arch/arm/src/armv7-a/arm_perf.c @@ -26,6 +26,7 @@ #include #include "arm_internal.h" +#include "arm_timer.h" #include "sctlr.h" #ifdef CONFIG_ARCH_PERF_EVENTS @@ -64,6 +65,13 @@ void up_perf_init(void *arg) { g_cpu_freq = (unsigned long)(uintptr_t)arg; +#ifdef CONFIG_ARMV7A_HAVE_PTM + if (g_cpu_freq == ULONG_MAX || g_cpu_freq == 0) + { + g_cpu_freq = arm_timer_get_freq(); + } +#endif + cp15_pmu_uer(PMUER_UME); cp15_pmu_pmcr(PMCR_E); cp15_pmu_cesr(PMCESR_CCES); diff --git a/arch/arm/src/armv7-a/arm_pghead.S b/arch/arm/src/armv7-a/arm_pghead.S index b0c6533f2f84f..b2d45c59e588e 100644 --- a/arch/arm/src/armv7-a/arm_pghead.S +++ b/arch/arm/src/armv7-a/arm_pghead.S @@ -32,7 +32,7 @@ #include "chip.h" #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING .file "arm_pghead.S" @@ -50,7 +50,7 @@ /* The page table cannot be in ROM if we are going to do pagin! */ #ifndef CONFIG_ARCH_ROMPGTABLE -# error CONFIG_PAGING and CONFIG_ARCH_ROMPGTABLE are incompatible options +# error CONFIG_LEGACY_PAGING and CONFIG_ARCH_ROMPGTABLE are incompatible options #endif /* There are three operational memory configurations: diff --git a/arch/arm/src/armv7-a/arm_pginitialize.c b/arch/arm/src/armv7-a/arm_pginitialize.c index 787804f48307f..3df18ae9fd217 100644 --- a/arch/arm/src/armv7-a/arm_pginitialize.c +++ b/arch/arm/src/armv7-a/arm_pginitialize.c @@ -31,7 +31,7 @@ #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /**************************************************************************** * Public Functions @@ -65,4 +65,4 @@ void arm_pginitialize(void) */ } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/armv7-a/arm_prefetchabort.c b/arch/arm/src/armv7-a/arm_prefetchabort.c index b071b7c14e86b..0728a69a404bb 100644 --- a/arch/arm/src/armv7-a/arm_prefetchabort.c +++ b/arch/arm/src/armv7-a/arm_prefetchabort.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif @@ -50,7 +50,7 @@ * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr) { @@ -117,7 +117,7 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr) return regs; } -#else /* CONFIG_PAGING */ +#else /* CONFIG_LEGACY_PAGING */ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr) { @@ -135,4 +135,4 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr) return regs; /* To keep the compiler happy */ } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/armv7-a/arm_smccc.S b/arch/arm/src/armv7-a/arm_smccc.S index 51befee045825..3365feb29806c 100644 --- a/arch/arm/src/armv7-a/arm_smccc.S +++ b/arch/arm/src/armv7-a/arm_smccc.S @@ -44,33 +44,40 @@ * handled by Secure Monitor code running in EL3. */ - .text - .syntax unified + .text + .syntax unified + + .global arm_smccc_smc + .type arm_smccc_smc, function - .global arm_smccc_smc - .type arm_smccc_smc, function arm_smccc_smc: - mov r12, sp - push {r4-r7} - ldm r12, {r4-r7} - smc #0 - pop {r4-r7} - ldr r12, [sp, #(4 * 4)] - stm r12, {r0-r3} - bx lr + mov r12, sp + push {r4-r7} + ldm r12, {r4-r7} + smc #0 + pop {r4-r7} + ldr r12, [sp, #(4 * 4)] + stm r12, {r0-r3} + bx lr -/* The HVC instruction is used to generate a synchronous exception that is - * handled by a hypervisor running in EL2. - */ + .size arm_smccc_smc, . - arm_smccc_smc + + /* The HVC instruction is used to generate a synchronous exception that is + * handled by a hypervisor running in EL2. + */ + + .global arm_smccc_hvc + .type arm_smccc_hvc, function - .global arm_smccc_hvc - .type arm_smccc_hvc, function arm_smccc_hvc: - mov r12, sp - push {r4-r7} - ldm r12, {r4-r7} - hvc #0 - pop {r4-r7} - ldr r12, [sp, #(4 * 4)] - stm r12, {r0-r3} - bx lr + mov r12, sp + push {r4-r7} + ldm r12, {r4-r7} + hvc #0 + pop {r4-r7} + ldr r12, [sp, #(4 * 4)] + stm r12, {r0-r3} + bx lr + + .size arm_smccc_hvc, . - arm_smccc_hvc + .end diff --git a/arch/arm/src/armv7-a/arm_timer.c b/arch/arm/src/armv7-a/arm_timer.c index 54d53a300f46b..2efc10549172e 100644 --- a/arch/arm/src/armv7-a/arm_timer.c +++ b/arch/arm/src/armv7-a/arm_timer.c @@ -87,12 +87,6 @@ static const struct oneshot_operations_s g_arm_timer_ops = * Private Functions ****************************************************************************/ -static inline uint32_t arm_timer_get_freq(void) -{ - ARM_ISB(); - return CP15_GET(CNTFRQ); -} - static inline void arm_timer_set_freq(uint32_t freq) { CP15_SET(CNTFRQ, freq); @@ -129,6 +123,18 @@ static inline void arm_timer_set_tval(uint32_t tval) ARM_ISB(); } +static inline uint64_t arm_timer_get_cval(void) +{ + ARM_ISB(); + return CP15_GET64(CNTP_CVAL); +} + +static inline void arm_timer_set_cval(uint64_t cval) +{ + CP15_SET64(CNTP_CVAL, cval); + ARM_ISB(); +} + static inline uint64_t nsec_from_count(uint64_t count, uint32_t freq) { return (uint64_t)count * NSEC_PER_SEC / freq; @@ -150,7 +156,7 @@ static int arm_timer_maxdelay(struct oneshot_lowerhalf_s *lower_, struct arm_timer_lowerhalf_s *lower = (struct arm_timer_lowerhalf_s *)lower_; - uint64_t maxnsec = nsec_from_count(UINT32_MAX, lower->freq); + uint64_t maxnsec = nsec_from_count(UINT64_MAX, lower->freq); ts->tv_sec = maxnsec / NSEC_PER_SEC; ts->tv_nsec = maxnsec % NSEC_PER_SEC; @@ -165,7 +171,7 @@ static int arm_timer_start(struct oneshot_lowerhalf_s *lower_, struct arm_timer_lowerhalf_s *lower = (struct arm_timer_lowerhalf_s *)lower_; irqstate_t flags; - uint32_t count; + uint64_t count; uint32_t ctrl; flags = up_irq_save(); @@ -175,7 +181,7 @@ static int arm_timer_start(struct oneshot_lowerhalf_s *lower_, count = sec_to_count(ts->tv_sec, lower->freq) + nsec_to_count(ts->tv_nsec, lower->freq); - arm_timer_set_tval(count); + arm_timer_set_cval(arm_timer_get_count() + count); ctrl = arm_timer_get_ctrl(); ctrl &= ~ARM_TIMER_CTRL_INT_MASK; @@ -230,6 +236,8 @@ static int arm_timer_interrupt(int irq, void *context, void *arg) DEBUGASSERT(lower != NULL); + arm_timer_set_ctrl(arm_timer_get_ctrl() | ARM_TIMER_CTRL_INT_MASK); + if (lower->callback != NULL) { callback = lower->callback; @@ -249,6 +257,12 @@ static int arm_timer_interrupt(int irq, void *context, void *arg) * Public Functions ****************************************************************************/ +uint32_t arm_timer_get_freq(void) +{ + ARM_ISB(); + return CP15_GET(CNTFRQ); +} + struct oneshot_lowerhalf_s *arm_timer_initialize(unsigned int freq) { struct arm_timer_lowerhalf_s *lower; diff --git a/arch/arm/src/armv7-a/arm_timer.h b/arch/arm/src/armv7-a/arm_timer.h index c1b8336bd01b1..52ee69fac649e 100644 --- a/arch/arm/src/armv7-a/arm_timer.h +++ b/arch/arm/src/armv7-a/arm_timer.h @@ -59,8 +59,10 @@ extern "C" #ifdef CONFIG_ARMV7A_HAVE_PTM struct oneshot_lowerhalf_s *arm_timer_initialize(unsigned int freq); +uint32_t arm_timer_get_freq(void); #else # define arm_timer_initialize(freq) NULL +# define arm_timer_get_freq() 0 #endif #undef EXTERN diff --git a/arch/arm/src/armv7-a/arm_va2pte.c b/arch/arm/src/armv7-a/arm_va2pte.c index df692ff9716bd..f9dd94a4f2756 100644 --- a/arch/arm/src/armv7-a/arm_va2pte.c +++ b/arch/arm/src/armv7-a/arm_va2pte.c @@ -34,7 +34,7 @@ #include "chip.h" #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /**************************************************************************** * Public Functions @@ -90,4 +90,4 @@ uint32_t *arm_va2pte(uintptr_t vaddr) return &L2[ndx]; } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/arch/arm/src/armv7-a/arm_vectoraddrexcptn.S b/arch/arm/src/armv7-a/arm_vectoraddrexcptn.S deleted file mode 100644 index af407a4f58223..0000000000000 --- a/arch/arm/src/armv7-a/arm_vectoraddrexcptn.S +++ /dev/null @@ -1,67 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-a/arm_vectoraddrexceptn.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - - .file "arm_vectoraddrexcptn.S" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Symbols - ****************************************************************************/ - - .globl arm_vectoraddrexcptn - -/**************************************************************************** - * Assembly Macros - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - - .text - .syntax unified - .arm - -/**************************************************************************** - * Name: arm_vectoraddrexcptn - * - * Description: - * Shouldn't happen. This exception handler is in a separate file from - * other vector handlers because some processors do not support the - * Address Exception vector. - * - ****************************************************************************/ - - .globl arm_vectoraddrexcptn - .type arm_vectoraddrexcptn, %function -arm_vectoraddrexcptn: - b arm_vectoraddrexcptn - .size arm_vectoraddrexcptn, . - arm_vectoraddrexcptn - .end diff --git a/arch/arm/src/armv7-a/arm_vectors.S b/arch/arm/src/armv7-a/arm_vectors.S index 12952621b43fa..509c44dfa1c3b 100644 --- a/arch/arm/src/armv7-a/arm_vectors.S +++ b/arch/arm/src/armv7-a/arm_vectors.S @@ -180,10 +180,10 @@ arm_vectorirq: /* Switch to SYS mode */ -#ifdef CONFIG_ARMV7A_DECODEFIQ - cpsid if, #PSR_MODE_SYS -#else +#ifdef CONFIG_ARCH_HIPRI_INTERRUPT cpsid i, #PSR_MODE_SYS +#else + cpsid if, #PSR_MODE_SYS #endif /* Create a context structure. First set aside a stack frame @@ -290,10 +290,10 @@ arm_vectorsvc: /* Switch to SYS mode */ -#ifdef CONFIG_ARMV7A_DECODEFIQ - cpsid if, #PSR_MODE_SYS -#else +#ifdef CONFIG_ARCH_HIPRI_INTERRUPT cpsid i, #PSR_MODE_SYS +#else + cpsid if, #PSR_MODE_SYS #endif /* Create a context structure. First set aside a stack frame @@ -401,10 +401,10 @@ arm_vectordata: /* Switch to SYS mode */ -#ifdef CONFIG_ARMV7A_DECODEFIQ - cpsid if, #PSR_MODE_SYS -#else +#ifdef CONFIG_ARCH_HIPRI_INTERRUPT cpsid i, #PSR_MODE_SYS +#else + cpsid if, #PSR_MODE_SYS #endif /* Create a context structure. First set aside a stack frame @@ -642,14 +642,14 @@ arm_vectorundefinsn: * ****************************************************************************/ -#ifdef CONFIG_ARMV7A_DECODEFIQ +#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT) .globl arm_decodefiq #endif .globl arm_vectorfiq .type arm_vectorfiq, %function arm_vectorfiq: -#ifdef CONFIG_ARMV7A_DECODEFIQ +#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT) /* Save the LR and SPSR onto the SYS mode stack before switch. */ @@ -732,6 +732,22 @@ arm_vectorfiq: #endif .size arm_vectorfiq, . - arm_vectorfiq +/**************************************************************************** + * Name: arm_vectoraddrexcptn + * + * Description: + * Shouldn't happen. This exception handler is in a separate file from + * other vector handlers because some processors do not support the + * Address Exception vector. + * + ****************************************************************************/ + + .globl arm_vectoraddrexcptn + .type arm_vectoraddrexcptn, %function +arm_vectoraddrexcptn: + b arm_vectoraddrexcptn + .size arm_vectoraddrexcptn, . - arm_vectoraddrexcptn + /**************************************************************************** * Name: g_intstackalloc/g_intstacktop ****************************************************************************/ @@ -755,7 +771,7 @@ g_intstacktop: * Name: g_fiqstackalloc/g_fiqstacktop ****************************************************************************/ -#ifdef CONFIG_ARMV7A_DECODEFIQ +#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT) .globl g_fiqstackalloc .type g_fiqstackalloc, object .globl g_fiqstacktop diff --git a/arch/arm/src/armv7-a/crt0.c b/arch/arm/src/armv7-a/crt0.c index eeaf4508e2790..6ce0b1d052f1d 100644 --- a/arch/arm/src/armv7-a/crt0.c +++ b/arch/arm/src/armv7-a/crt0.c @@ -91,7 +91,7 @@ static void sig_trampoline(void) ****************************************************************************/ /**************************************************************************** - * Name: _start + * Name: __start * * Description: * This function is the low level entry point into the main thread of @@ -110,7 +110,7 @@ static void sig_trampoline(void) * ****************************************************************************/ -void _start(int argc, char *argv[]) +void __start(int argc, char *argv[]) { int ret; diff --git a/arch/arm/src/armv7-a/gic.h b/arch/arm/src/armv7-a/gic.h index 00e2c21aca279..2cbeaa8f7ff7e 100644 --- a/arch/arm/src/armv7-a/gic.h +++ b/arch/arm/src/armv7-a/gic.h @@ -93,6 +93,11 @@ #define GIC_SHIFT32(n) ((n) & 31) /* Shift 1-bit per field */ #define GIC_MASK32(n) (1 << GIC_SHIFT32(n)) /* 1-bit mask */ +/* GIC group */ + +#define GIC_GROUP0 0 +#define GIC_GROUP1 1 + /* GIC Register Offsets *****************************************************/ /* CPU Interface registers */ @@ -537,7 +542,11 @@ #define GIC_ICDSGIR_INTID_MASK (0x3ff << GIC_ICDSGIR_INTID_SHIFT) # define GIC_ICDSGIR_INTID(n) ((uint32_t)(n) << GIC_ICDSGIR_INTID_SHIFT) /* Bits 10-14: Reserved */ -#define GIC_ICDSGIR_NSATT (1 << 15) +#define GIC_ICDSGIR_NSATT_SHIFT (15) +#define GIC_ICDSGIR_NSATT_MASK (1 << GIC_ICDSGIR_NSATT_SHIFT) +# define GIC_ICDSGIR_NSATT_GRP0 (0 << GIC_ICDSGIR_NSATT_SHIFT) +# define GIC_ICDSGIR_NSATT_GRP1 (1 << GIC_ICDSGIR_NSATT_SHIFT) + #define GIC_ICDSGIR_CPUTARGET_SHIFT (16) /* Bits 16-23: CPU target */ #define GIC_ICDSGIR_CPUTARGET_MASK (0xff << GIC_ICDSGIR_CPUTARGET_SHIFT) # define GIC_ICDSGIR_CPUTARGET(n) ((uint32_t)(n) << GIC_ICDSGIR_CPUTARGET_SHIFT) @@ -671,6 +680,15 @@ static inline void arm_cpu_sgi(int sgi, unsigned int cpuset) GIC_ICDSGIR_TGTFILTER_THIS; #endif +#ifndef CONFIG_ARCH_TRUSTZONE_SECURE + /* Set NSATT be 1: forward the SGI specified in the SGIINTID field to a + * specified CPU interfaces only if the SGI is configured as Group 1 on + * that interface. + */ + + regval |= GIC_ICDSGIR_NSATT_GRP1; +#endif + putreg32(regval, GIC_ICDSGIR); } @@ -757,6 +775,38 @@ int arm_gic_irq_trigger(int irq, bool edge); uint32_t *arm_decodeirq(uint32_t *regs); +/**************************************************************************** + * Name: arm_dofiq + * + * Description: + * Receives the decoded GIC interrupt information and dispatches control + * to the attached fiq handler. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_HIPRI_INTERRUPT +uint32_t *arm_dofiq(int irq, uint32_t *regs); +#endif + +/**************************************************************************** + * Name: arm_decodefiq + * + * Description: + * This function is called from the FIQ vector handler in arm_vectors.S. + * At this point, the interrupt has been taken and the registers have + * been saved on the stack. This function simply needs to determine the + * the fiq number of the interrupt and then to call arm_doirq to dispatch + * the interrupt. + * + * Input Parameters: + * regs - A pointer to the register save area on the stack. + * + ****************************************************************************/ + +#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT) +uint32_t *arm_decodefiq(uint32_t *regs); +#endif + /**************************************************************************** * Name: arm_start_handler * @@ -820,7 +870,7 @@ int arm_pause_handler(int irq, void *context, void *arg); #ifdef CONFIG_DEBUG_IRQ_INFO void arm_gic_dump(const char *msg, bool all, int irq); #else -# define arm_gic_dump(m,a,i) +# define arm_gic_dump(msg, all, irq) #endif #undef EXTERN diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h index 83be9370f6ad8..c381e62b19665 100644 --- a/arch/arm/src/armv7-a/mmu.h +++ b/arch/arm/src/armv7-a/mmu.h @@ -49,16 +49,16 @@ /* Configuration ************************************************************/ -#if defined(CONFIG_PAGING) || defined(CONFIG_ARCH_ADDRENV) +#if defined(CONFIG_LEGACY_PAGING) || defined(CONFIG_ARCH_ADDRENV) /* Sanity check -- we cannot be using a ROM page table and supporting on- * demand paging. */ #ifdef CONFIG_ARCH_ROMPGTABLE -# error "Cannot support both CONFIG_PAGING/CONFIG_ARCH_ADDRENV and CONFIG_ARCH_ROMPGTABLE" +# error "Cannot support both CONFIG_LEGACY_PAGING/CONFIG_ARCH_ADDRENV and CONFIG_ARCH_ROMPGTABLE" #endif -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ /* MMU CP15 Register Bit Definitions ****************************************/ @@ -645,7 +645,10 @@ * require up to 16Kb of memory. */ -#define PGTABLE_SIZE 0x00004000 +#ifndef PGTABLE_SIZE +# define PGTABLE_SIZE 0x00004000 +#endif + #ifdef CONFIG_ARCH_ADDRENV # define ALL_PGTABLE_SIZE (PGTABLE_SIZE * CONFIG_SMP_NCPUS) #else @@ -654,7 +657,7 @@ /* Virtual Page Table Location **********************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /* Check if the virtual address of the page table has been defined. It * should not be defined: architecture specific logic should suppress * defining PGTABLE_BASE_VADDR unless: (1) it is defined in the NuttX @@ -894,7 +897,7 @@ #define PG_POOL_PGPADDR(ndx) (PG_PAGED_PBASE + ((ndx) << PAGESHIFT)) #define PG_POOL_PGVADDR(ndx) (PG_PAGED_VBASE + ((ndx) << PAGESHIFT)) -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ /**************************************************************************** * Public Types @@ -1053,8 +1056,8 @@ struct page_mapping_s * * Description: * Write several, contiguous L2 page table entries. npages entries will be - * written. This macro is used when CONFIG_PAGING is enable. This case, - * it is used as follows: + * written. This macro is used when CONFIG_LEGACY_PAGING is enable. + * This case, it is used as follows: * * ldr r0, =PGTABLE_L2_BASE_PADDR <-- Address in L2 table * ldr r1, =PG_LOCKED_PBASE <-- Physical page memory address @@ -1083,7 +1086,7 @@ struct page_mapping_s * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING .macro pg_l2map, l2, ppage, npages, mmuflags, tmp b 2f 1: @@ -1116,7 +1119,7 @@ struct page_mapping_s cmp \npages, #0 bgt 1b .endm -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ /**************************************************************************** * Name: pg_l1span @@ -1124,7 +1127,7 @@ struct page_mapping_s * Description: * Write several, contiguous, unmapped, small L1 page table entries. * As many entries will be written as many as needed to span npages. - * This macro is used when CONFIG_PAGING is enable. In this case, + * This macro is used when CONFIG_LEGACY_PAGING is enable. In this case, * it is used as follows: * * ldr r0, =PG_L1_PGTABLE_PADDR <-- Address in the L1 table @@ -1159,7 +1162,7 @@ struct page_mapping_s * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING .macro pg_l1span, l1, l2, npages, ppage, mmuflags, tmp b 2f 1: @@ -1197,7 +1200,7 @@ struct page_mapping_s bgt 1b .endm -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ #endif /* __ASSEMBLY__ */ /**************************************************************************** diff --git a/arch/arm/src/armv7-m/arm_exception.S b/arch/arm/src/armv7-m/arm_exception.S index de5e8a3852900..d2478aadd2b15 100644 --- a/arch/arm/src/armv7-m/arm_exception.S +++ b/arch/arm/src/armv7-m/arm_exception.S @@ -118,6 +118,7 @@ */ .text + .section .text.exception_common .thumb_func .type exception_common, function exception_common: @@ -137,6 +138,7 @@ exception_common: mrs r1, msp /* R1=The main stack pointer (MSP) */ sub r2, r1, #SW_XCPT_SIZE /* Reserved stack space */ msr msp, r2 + isb sy 2: mov r2, r1 /* R2=Copy of the main/process stack pointer */ diff --git a/arch/arm/src/armv7-m/arm_initialstate.c b/arch/arm/src/armv7-m/arm_initialstate.c index fe42f23344e1d..1d4250edc87c5 100644 --- a/arch/arm/src/armv7-m/arm_initialstate.c +++ b/arch/arm/src/armv7-m/arm_initialstate.c @@ -180,11 +180,7 @@ void up_initial_state(struct tcb_s *tcb) noinline_function void arm_initialize_stack(void) { -#ifdef CONFIG_SMP - uint32_t stack = (uint32_t)arm_intstack_top(); -#else - uint32_t stack = (uint32_t)g_intstacktop; -#endif + uint32_t stack = up_get_intstackbase(up_cpu_index()) + INTSTACK_SIZE; uint32_t temp = 0; __asm__ __volatile__ @@ -194,6 +190,7 @@ noinline_function void arm_initialize_stack(void) "mov %1, sp\n" "msr psp, %1\n" + "isb sy\n" /* Select PSP */ @@ -205,6 +202,7 @@ noinline_function void arm_initialize_stack(void) /* Initialize MSP */ "msr msp, %0\n" + "isb sy\n" : : "r" (stack), "r" (temp) : "memory"); diff --git a/arch/arm/src/armv7-m/arm_mpu.c b/arch/arm/src/armv7-m/arm_mpu.c index 7a35108495a3f..3e04442cf8ffd 100644 --- a/arch/arm/src/armv7-m/arm_mpu.c +++ b/arch/arm/src/armv7-m/arm_mpu.c @@ -185,7 +185,7 @@ static inline uint32_t mpu_subregion_ls(size_t offset, uint8_t l2size) * ****************************************************************************/ -#if defined(CONFIG_MPU_RESET) || defined(CONFIG_ARM_MPU_EARLY_RESET) +#if defined(CONFIG_ARM_MPU_RESET) || defined(CONFIG_ARM_MPU_EARLY_RESET) static void mpu_reset_internal() { int region; @@ -423,7 +423,7 @@ void mpu_configure_region(uintptr_t base, size_t size, * MPU initialization. * ****************************************************************************/ -#if defined(CONFIG_MPU_RESET) +#if defined(CONFIG_ARM_MPU_RESET) void mpu_reset() { mpu_reset_internal(); diff --git a/arch/arm/src/armv7-m/mpu.h b/arch/arm/src/armv7-m/mpu.h index 18c24ff0fe8b8..b75f03c2040dd 100644 --- a/arch/arm/src/armv7-m/mpu.h +++ b/arch/arm/src/armv7-m/mpu.h @@ -139,7 +139,7 @@ * ****************************************************************************/ -#if defined(CONFIG_MPU_RESET) +#if defined(CONFIG_ARM_MPU_RESET) void mpu_reset(void); #else # define mpu_reset() diff --git a/arch/arm/src/armv7-r/CMakeLists.txt b/arch/arm/src/armv7-r/CMakeLists.txt index ebc7d2ad1971e..e2b2cce85a7f8 100644 --- a/arch/arm/src/armv7-r/CMakeLists.txt +++ b/arch/arm/src/armv7-r/CMakeLists.txt @@ -24,8 +24,7 @@ set(SRCS arm_vectortab.S) # Common assembly language files -list(APPEND SRCS arm_head.S arm_vectoraddrexcptn.S arm_vectors.S - arm_saveusercontext.S) +list(APPEND SRCS arm_head.S arm_vectors.S arm_saveusercontext.S) # Common C source files diff --git a/arch/arm/src/armv7-r/Make.defs b/arch/arm/src/armv7-r/Make.defs index 22261e2f798eb..be004c67fe30f 100644 --- a/arch/arm/src/armv7-r/Make.defs +++ b/arch/arm/src/armv7-r/Make.defs @@ -38,8 +38,7 @@ CMN_CSRCS += arm_perf.c cp15_cacheops.c # Common C source files -CMN_ASRCS += arm_head.S arm_vectoraddrexcptn.S arm_vectors.S -CMN_ASRCS += arm_saveusercontext.S +CMN_ASRCS += arm_head.S arm_vectors.S arm_saveusercontext.S ifeq ($(CONFIG_ARMV7R_HAVE_PTM), y) CMN_CSRCS += arm_timer.c diff --git a/arch/arm/src/armv7-r/arm_cpupause.c b/arch/arm/src/armv7-r/arm_cpupause.c index 921b1f0f3996e..3e8102d6f5132 100644 --- a/arch/arm/src/armv7-r/arm_cpupause.c +++ b/arch/arm/src/armv7-r/arm_cpupause.c @@ -85,7 +85,7 @@ bool up_cpu_pausereq(int cpu) } /**************************************************************************** - * Name: up_cpu_paused + * Name: up_cpu_paused_save * * Description: * Handle a pause request from another CPU. Normally, this logic is @@ -94,16 +94,8 @@ bool up_cpu_pausereq(int cpu) * pause operation in other contexts where the interrupt cannot be taken * in order to avoid deadlocks. * - * This function performs the following operations: - * - * 1. It saves the current task state at the head of the current assigned - * task list. - * 2. It waits on a spinlock, then - * 3. Returns from interrupt, restoring the state of the new task at the - * head of the ready to run list. - * * Input Parameters: - * cpu - The index of the CPU to be paused + * None * * Returned Value: * On success, OK is returned. Otherwise, a negated errno value indicating @@ -111,7 +103,7 @@ bool up_cpu_pausereq(int cpu) * ****************************************************************************/ -int up_cpu_paused(int cpu) +int up_cpu_paused_save(void) { struct tcb_s *tcb = this_task(); @@ -131,6 +123,38 @@ int up_cpu_paused(int cpu) arm_savestate(tcb->xcp.regs); + return OK; +} + +/**************************************************************************** + * Name: up_cpu_paused + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. + * + * This function performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. + * + * Input Parameters: + * cpu - The index of the CPU to be paused + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused(int cpu) +{ /* Release the g_cpu_paused spinlock to synchronize with the * requesting CPU. */ @@ -147,11 +171,31 @@ int up_cpu_paused(int cpu) spin_lock(&g_cpu_wait[cpu]); - /* This CPU has been resumed. Restore the exception context of the TCB at - * the (new) head of the assigned task list. - */ + spin_unlock(&g_cpu_wait[cpu]); + spin_unlock(&g_cpu_resumed[cpu]); + + return OK; +} - tcb = this_task(); +/**************************************************************************** + * Name: up_cpu_paused_restore + * + * Description: + * Restore the state of the CPU after it was paused via up_cpu_pause(), + * and resume normal tasking. + * + * Input Parameters: + * None + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused_restore(void) +{ + struct tcb_s *tcb = this_task(); #ifdef CONFIG_SCHED_INSTRUMENTATION /* Notify that we have resumed */ @@ -168,8 +212,6 @@ int up_cpu_paused(int cpu) */ arm_restorestate(tcb->xcp.regs); - spin_unlock(&g_cpu_wait[cpu]); - spin_unlock(&g_cpu_resumed[cpu]); return OK; } diff --git a/arch/arm/src/armv7-r/arm_gicv2.c b/arch/arm/src/armv7-r/arm_gicv2.c index b5d5426697351..46407b67604cf 100644 --- a/arch/arm/src/armv7-r/arm_gicv2.c +++ b/arch/arm/src/armv7-r/arm_gicv2.c @@ -41,7 +41,7 @@ * Public Functions ****************************************************************************/ -#ifdef CONFIG_ARCH_HAVE_TRUSTZONE +#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT) /**************************************************************************** * Name: up_set_secure_irq * diff --git a/arch/arm/src/armv7-r/arm_head.S b/arch/arm/src/armv7-r/arm_head.S index 149fbcf921390..cd298688dc91d 100644 --- a/arch/arm/src/armv7-r/arm_head.S +++ b/arch/arm/src/armv7-r/arm_head.S @@ -76,11 +76,7 @@ */ #ifndef IDLE_STACK_BASE -# ifdef CONFIG_SMP -# define IDLE_STACK_BASE _enoinit -# else -# define IDLE_STACK_BASE _ebss -# endif +# define IDLE_STACK_BASE _ebss #endif #define IDLE_STACK_TOP IDLE_STACK_BASE+CONFIG_IDLETHREAD_STACKSIZE diff --git a/arch/arm/src/armv7-r/arm_mpu.c b/arch/arm/src/armv7-r/arm_mpu.c index 20239092432c3..40abae76ab5ab 100644 --- a/arch/arm/src/armv7-r/arm_mpu.c +++ b/arch/arm/src/armv7-r/arm_mpu.c @@ -185,7 +185,7 @@ static inline uint32_t mpu_subregion_ls(size_t offset, uint8_t l2size) * ****************************************************************************/ -#if defined(CONFIG_MPU_RESET) || defined(CONFIG_ARM_MPU_EARLY_RESET) +#if defined(CONFIG_ARM_MPU_RESET) || defined(CONFIG_ARM_MPU_EARLY_RESET) static void mpu_reset_internal() { int region; @@ -336,7 +336,7 @@ uint32_t mpu_subregion(uintptr_t base, size_t size, uint8_t l2size) * MPU initialization. * ****************************************************************************/ -#if defined(CONFIG_MPU_RESET) +#if defined(CONFIG_ARM_MPU_RESET) void mpu_reset() { mpu_reset_internal(); diff --git a/arch/arm/src/armv7-r/arm_perf.c b/arch/arm/src/armv7-r/arm_perf.c index c3d1310862fd4..de25750f64eb5 100644 --- a/arch/arm/src/armv7-r/arm_perf.c +++ b/arch/arm/src/armv7-r/arm_perf.c @@ -26,6 +26,7 @@ #include #include "arm_internal.h" +#include "arm_timer.h" #include "sctlr.h" #ifdef CONFIG_ARCH_PERF_EVENTS @@ -64,6 +65,13 @@ void up_perf_init(void *arg) { g_cpu_freq = (unsigned long)(uintptr_t)arg; +#ifdef CONFIG_ARMV7R_HAVE_PTM + if (g_cpu_freq == ULONG_MAX || g_cpu_freq == 0) + { + g_cpu_freq = arm_timer_get_freq(); + } +#endif + cp15_pmu_uer(PMUER_UME); cp15_pmu_pmcr(PMCR_E); cp15_pmu_cesr(PMCESR_CCES); diff --git a/arch/arm/src/armv7-r/arm_timer.c b/arch/arm/src/armv7-r/arm_timer.c index fafcbf98c074d..af7a5a7496cfa 100644 --- a/arch/arm/src/armv7-r/arm_timer.c +++ b/arch/arm/src/armv7-r/arm_timer.c @@ -87,12 +87,6 @@ static const struct oneshot_operations_s g_arm_timer_ops = * Private Functions ****************************************************************************/ -static inline uint32_t arm_timer_get_freq(void) -{ - ARM_ISB(); - return CP15_GET(CNTFRQ); -} - static inline void arm_timer_set_freq(uint32_t freq) { CP15_SET(CNTFRQ, freq); @@ -129,9 +123,23 @@ static inline void arm_timer_set_tval(uint32_t tval) ARM_ISB(); } +static inline uint64_t arm_timer_get_cval(void) +{ + ARM_ISB(); + return CP15_GET64(CNTP_CVAL); +} + +static inline void arm_timer_set_cval(uint64_t cval) +{ + CP15_SET64(CNTP_CVAL, cval); + ARM_ISB(); +} + static inline uint64_t nsec_from_count(uint64_t count, uint32_t freq) { - return (uint64_t)count * NSEC_PER_SEC / freq; + uint64_t sec = count / freq; + uint64_t nsec = (count % freq) * NSEC_PER_SEC / freq; + return sec * NSEC_PER_SEC + nsec; } static inline uint64_t nsec_to_count(uint32_t nsec, uint32_t freq) @@ -150,7 +158,7 @@ static int arm_timer_maxdelay(struct oneshot_lowerhalf_s *lower_, struct arm_timer_lowerhalf_s *lower = (struct arm_timer_lowerhalf_s *)lower_; - uint64_t maxnsec = nsec_from_count(UINT32_MAX, lower->freq); + uint64_t maxnsec = nsec_from_count(UINT64_MAX, lower->freq); ts->tv_sec = maxnsec / NSEC_PER_SEC; ts->tv_nsec = maxnsec % NSEC_PER_SEC; @@ -165,7 +173,7 @@ static int arm_timer_start(struct oneshot_lowerhalf_s *lower_, struct arm_timer_lowerhalf_s *lower = (struct arm_timer_lowerhalf_s *)lower_; irqstate_t flags; - uint32_t count; + uint64_t count; uint32_t ctrl; flags = up_irq_save(); @@ -175,7 +183,7 @@ static int arm_timer_start(struct oneshot_lowerhalf_s *lower_, count = sec_to_count(ts->tv_sec, lower->freq) + nsec_to_count(ts->tv_nsec, lower->freq); - arm_timer_set_tval(count); + arm_timer_set_cval(arm_timer_get_count() + count); ctrl = arm_timer_get_ctrl(); ctrl &= ~ARM_TIMER_CTRL_INT_MASK; @@ -230,6 +238,8 @@ static int arm_timer_interrupt(int irq, void *context, void *arg) DEBUGASSERT(lower != NULL); + arm_timer_set_ctrl(arm_timer_get_ctrl() | ARM_TIMER_CTRL_INT_MASK); + if (lower->callback != NULL) { callback = lower->callback; @@ -249,6 +259,12 @@ static int arm_timer_interrupt(int irq, void *context, void *arg) * Public Functions ****************************************************************************/ +uint32_t arm_timer_get_freq(void) +{ + ARM_ISB(); + return CP15_GET(CNTFRQ); +} + struct oneshot_lowerhalf_s *arm_timer_initialize(unsigned int freq) { struct arm_timer_lowerhalf_s *lower; diff --git a/arch/arm/src/armv7-r/arm_timer.h b/arch/arm/src/armv7-r/arm_timer.h index cd9549ecf79e5..681e5060daa7b 100644 --- a/arch/arm/src/armv7-r/arm_timer.h +++ b/arch/arm/src/armv7-r/arm_timer.h @@ -59,8 +59,10 @@ extern "C" #ifdef CONFIG_ARMV7R_HAVE_PTM struct oneshot_lowerhalf_s *arm_timer_initialize(unsigned int freq); +uint32_t arm_timer_get_freq(void); #else # define arm_timer_initialize(freq) NULL +# define arm_timer_get_freq() 0 #endif #undef EXTERN diff --git a/arch/arm/src/armv7-r/arm_vectoraddrexcptn.S b/arch/arm/src/armv7-r/arm_vectoraddrexcptn.S deleted file mode 100644 index cefe180ac080b..0000000000000 --- a/arch/arm/src/armv7-r/arm_vectoraddrexcptn.S +++ /dev/null @@ -1,67 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv7-r/arm_vectoraddrexceptn.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - - .file "arm_vectoraddrexcptn.S" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Symbols - ****************************************************************************/ - - .globl arm_vectoraddrexcptn - -/**************************************************************************** - * Assembly Macros - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - - .text - .syntax unified - .arm - -/**************************************************************************** - * Name: arm_vectoraddrexcptn - * - * Description: - * Shouldn't happen. This exception handler is in a separate file from - * other vector handlers because some processors do not support the - * Address Exception vector. - * - ****************************************************************************/ - - .globl arm_vectoraddrexcptn - .type arm_vectoraddrexcptn, %function -arm_vectoraddrexcptn: - b arm_vectoraddrexcptn - .size arm_vectoraddrexcptn, . - arm_vectoraddrexcptn - .end diff --git a/arch/arm/src/armv7-r/arm_vectors.S b/arch/arm/src/armv7-r/arm_vectors.S index 0f8e2224b92d0..b783430d0f594 100644 --- a/arch/arm/src/armv7-r/arm_vectors.S +++ b/arch/arm/src/armv7-r/arm_vectors.S @@ -716,6 +716,22 @@ arm_vectorfiq: #endif .size arm_vectorfiq, . - arm_vectorfiq +/**************************************************************************** + * Name: arm_vectoraddrexcptn + * + * Description: + * Shouldn't happen. This exception handler is in a separate file from + * other vector handlers because some processors do not support the + * Address Exception vector. + * + ****************************************************************************/ + + .globl arm_vectoraddrexcptn + .type arm_vectoraddrexcptn, %function +arm_vectoraddrexcptn: + b arm_vectoraddrexcptn + .size arm_vectoraddrexcptn, . - arm_vectoraddrexcptn + /**************************************************************************** * Name: g_intstackalloc/g_intstacktop ****************************************************************************/ diff --git a/arch/arm/src/armv7-r/mpu.h b/arch/arm/src/armv7-r/mpu.h index e7e05d7a5933e..7b4a05511fae8 100644 --- a/arch/arm/src/armv7-r/mpu.h +++ b/arch/arm/src/armv7-r/mpu.h @@ -128,7 +128,7 @@ extern "C" * ****************************************************************************/ -#if defined(CONFIG_MPU_RESET) +#if defined(CONFIG_ARM_MPU_RESET) void mpu_reset(void); #else # define mpu_reset() do { } while (0) diff --git a/arch/arm/src/armv8-m/arm_doirq.c b/arch/arm/src/armv8-m/arm_doirq.c index 0a4a9131b2fde..5e942d7aa5e54 100644 --- a/arch/arm/src/armv8-m/arm_doirq.c +++ b/arch/arm/src/armv8-m/arm_doirq.c @@ -68,7 +68,7 @@ static inline bool arm_from_thread(uint32_t excret) return true; } -#ifdef CONFIG_ARCH_HAVE_TRUSTZONE +#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) if (!(excret & EXC_RETURN_SECURE_STACK) && (excret & EXC_RETURN_EXC_SECURE)) { diff --git a/arch/arm/src/armv8-m/arm_exception.S b/arch/arm/src/armv8-m/arm_exception.S index 01ac94eb65c52..cd9cc92bc73da 100644 --- a/arch/arm/src/armv8-m/arm_exception.S +++ b/arch/arm/src/armv8-m/arm_exception.S @@ -137,6 +137,7 @@ exception_common: mrs r1, msp /* R1=The main stack pointer (MSP) */ sub r2, r1, #SW_XCPT_SIZE /* Reserve the stack space */ msr msp, r2 + isb sy 2: mov r2, r1 /* R2=Copy of the main/process stack pointer */ add r2, #HW_XCPT_SIZE /* R2=MSP/PSP before the interrupt was taken */ diff --git a/arch/arm/src/armv8-m/arm_initialstate.c b/arch/arm/src/armv8-m/arm_initialstate.c index 536f464b28bb4..ccbf494fa0adb 100644 --- a/arch/arm/src/armv8-m/arm_initialstate.c +++ b/arch/arm/src/armv8-m/arm_initialstate.c @@ -186,17 +186,8 @@ void up_initial_state(struct tcb_s *tcb) noinline_function void arm_initialize_stack(void) { -#ifdef CONFIG_SMP - uint32_t stack = (uint32_t)arm_intstack_top(); -#ifdef CONFIG_ARMV8M_STACKCHECK_HARDWARE - uint32_t stacklim = (uint32_t)arm_intstack_alloc(); -#endif -#else - uint32_t stack = (uint32_t)g_intstacktop; -#ifdef CONFIG_ARMV8M_STACKCHECK_HARDWARE - uint32_t stacklim = (uint32_t)g_intstackalloc; -#endif -#endif + uint32_t stacklim = up_get_intstackbase(up_cpu_index()); + uint32_t stack = stacklim + INTSTACK_SIZE; uint32_t temp = 0; __asm__ __volatile__ @@ -213,6 +204,7 @@ noinline_function void arm_initialize_stack(void) "mrs %1, msplim\n" "msr psplim, %1\n" #endif + "isb sy\n" /* Select PSP */ @@ -228,6 +220,7 @@ noinline_function void arm_initialize_stack(void) #ifdef CONFIG_ARMV8M_STACKCHECK_HARDWARE "msr msplim, %2\n" #endif + "isb sy\n" : #ifdef CONFIG_ARMV8M_STACKCHECK_HARDWARE : "r" (stack), "r" (temp), "r" (stacklim) diff --git a/arch/arm/src/armv8-m/arm_mpu.c b/arch/arm/src/armv8-m/arm_mpu.c index 327b3a030c99b..effd078a90304 100644 --- a/arch/arm/src/armv8-m/arm_mpu.c +++ b/arch/arm/src/armv8-m/arm_mpu.c @@ -79,7 +79,7 @@ unsigned int mpu_allocregion(void) * ****************************************************************************/ -#if defined(CONFIG_MPU_RESET) || defined(CONFIG_ARM_MPU_EARLY_RESET) +#if defined(CONFIG_ARM_MPU_RESET) || defined(CONFIG_ARM_MPU_EARLY_RESET) static void mpu_reset_internal() { int region; @@ -184,7 +184,7 @@ void mpu_configure_region(uintptr_t base, size_t size, * MPU initialization. * ****************************************************************************/ -#if defined(CONFIG_MPU_RESET) +#if defined(CONFIG_ARM_MPU_RESET) void mpu_reset() { mpu_reset_internal(); diff --git a/arch/arm/src/armv8-m/arm_secure_irq.c b/arch/arm/src/armv8-m/arm_secure_irq.c index 376ec71f34094..ce36478ed47b0 100644 --- a/arch/arm/src/armv8-m/arm_secure_irq.c +++ b/arch/arm/src/armv8-m/arm_secure_irq.c @@ -33,7 +33,7 @@ #include "arm_internal.h" #include "nvic.h" -#ifdef CONFIG_ARCH_HAVE_TRUSTZONE +#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) /**************************************************************************** * Public Functions diff --git a/arch/arm/src/armv8-m/mpu.h b/arch/arm/src/armv8-m/mpu.h index 077eb52a07c27..8db68a77e9922 100644 --- a/arch/arm/src/armv8-m/mpu.h +++ b/arch/arm/src/armv8-m/mpu.h @@ -178,7 +178,7 @@ * ****************************************************************************/ -#if defined(CONFIG_MPU_RESET) +#if defined(CONFIG_ARM_MPU_RESET) void mpu_reset(void); #else # define mpu_reset() do { } while (0) diff --git a/arch/arm/src/armv8-r/CMakeLists.txt b/arch/arm/src/armv8-r/CMakeLists.txt new file mode 100644 index 0000000000000..79a08e37f86ac --- /dev/null +++ b/arch/arm/src/armv8-r/CMakeLists.txt @@ -0,0 +1,54 @@ +# ############################################################################## +# arch/arm/src/armv8-r/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +# The vector table + +set(SRCS arm_vectortab.S) + +# Common assembly language files + +list(APPEND SRCS arm_head.S arm_vectors.S arm_saveusercontext.S) + +# Common C source files + +list( + APPEND + SRCS + arm_arch_timer.c + arm_cache.c + arm_cpuinfo.c + arm_dataabort.c + arm_doirq.c + arm_gicv3.c + arm_initialstate.c + arm_prefetchabort.c + arm_schedulesigaction.c + arm_sigdeliver.c + arm_syscall.c + arm_tcbinfo.c + arm_undefinedinsn.c + arm_perf.c + cp15_cacheops.c) + +if(CONFIG_ARCH_FPU) + list(APPEND SRCS arm_fpucmp.c arm_fpuconfig.S) +endif() + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/armv8-r/Make.defs b/arch/arm/src/armv8-r/Make.defs index 7937478593e68..e906ef0333661 100644 --- a/arch/arm/src/armv8-r/Make.defs +++ b/arch/arm/src/armv8-r/Make.defs @@ -38,8 +38,7 @@ CMN_CSRCS += arm_perf.c cp15_cacheops.c # Common C source files -CMN_ASRCS += arm_head.S arm_vectoraddrexcptn.S arm_vectors.S -CMN_ASRCS += arm_saveusercontext.S +CMN_ASRCS += arm_head.S arm_vectors.S arm_saveusercontext.S # ifeq ($(CONFIG_BUILD_PROTECTED),y) # CMN_CSRCS += arm_mpu.c diff --git a/arch/arm/src/armv8-r/arm_gicv3.c b/arch/arm/src/armv8-r/arm_gicv3.c index a351ae68d1b48..1d22ca0b18baf 100644 --- a/arch/arm/src/armv8-r/arm_gicv3.c +++ b/arch/arm/src/armv8-r/arm_gicv3.c @@ -313,7 +313,7 @@ static int arm_gic_send_sgi(unsigned int sgi_id, uint64_t target_aff, uint32_t aff1; uint64_t sgi_val; - assert(GIC_IS_SGI(sgi_id)); + ASSERT(GIC_IS_SGI(sgi_id)); /* Extract affinity fields from target */ @@ -448,7 +448,7 @@ static void gicv3_cpuif_init(void) CP15_SET(ICC_SRE, icc_sre); icc_sre = CP15_GET(ICC_SRE); - assert(icc_sre & ICC_SRE_ELX_SRE_BIT); + ASSERT(icc_sre & ICC_SRE_ELX_SRE_BIT); } CP15_SET(ICC_PMR, GIC_IDLE_PRIO); @@ -727,7 +727,7 @@ static int gic_validate_dist_version(void) spis = MIN(GICD_TYPER_SPIS(typer), 1020U) - 32; espis = GICD_TYPER_ESPIS(typer); - sinfo("GICD_TYPER = 0x%x\n", typer); + sinfo("GICD_TYPER = 0x%" PRIu32 "\n", typer); sinfo("%d SPIs implemented\n", spis); sinfo("%d Extended SPIs implemented\n", espis); diff --git a/arch/arm/src/armv8-r/arm_head.S b/arch/arm/src/armv8-r/arm_head.S index ed1f05931239a..1ff6b05aeebd7 100644 --- a/arch/arm/src/armv8-r/arm_head.S +++ b/arch/arm/src/armv8-r/arm_head.S @@ -132,12 +132,12 @@ .type __start, #function __start: -#if defined(CONFIG_SMP) && CONFIG_SMP_NCPUS > 1 /* Get cpuindex, cpu0 continue boot, others wait event from cpu0 */ mrc CP15_MPIDR(r0) and r0, r0, #0x3 cmp r0, #0 +#if defined(CONFIG_SMP) && CONFIG_SMP_NCPUS > 1 beq __cpu0_start wfe cmp r0, #1 @@ -155,9 +155,21 @@ __start: beq __cpu4_start # endif -__cpu0_start: +#else + beq __cpu0_start + +__cpux_wfi: + + /* Clear all pending data access */ + + dsb sy + wfi + b __cpux_wfi + #endif +__cpu0_start: + /* Make sure that IRQs and FIQs are disabled */ cpsid if diff --git a/arch/arm/src/armv8-r/arm_perf.c b/arch/arm/src/armv8-r/arm_perf.c index b0564f60f8355..63bc1eb30239c 100644 --- a/arch/arm/src/armv8-r/arm_perf.c +++ b/arch/arm/src/armv8-r/arm_perf.c @@ -28,6 +28,8 @@ #include "arm_internal.h" #include "sctlr.h" +#ifdef CONFIG_ARCH_PERF_EVENTS + /**************************************************************************** * Private Data ****************************************************************************/ @@ -85,3 +87,4 @@ void up_perf_convert(unsigned long elapsed, struct timespec *ts) left = elapsed - ts->tv_sec * g_cpu_freq; ts->tv_nsec = NSEC_PER_SEC * (uint64_t)left / g_cpu_freq; } +#endif /* CONFIG_ARCH_PERF_EVENTS */ diff --git a/arch/arm/src/armv8-r/arm_vectoraddrexcptn.S b/arch/arm/src/armv8-r/arm_vectoraddrexcptn.S deleted file mode 100644 index 88a5ce9cf8aeb..0000000000000 --- a/arch/arm/src/armv8-r/arm_vectoraddrexcptn.S +++ /dev/null @@ -1,67 +0,0 @@ -/**************************************************************************** - * arch/arm/src/armv8-r/arm_vectoraddrexceptn.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - - .file "arm_vectoraddrexcptn.S" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Symbols - ****************************************************************************/ - - .globl arm_vectoraddrexcptn - -/**************************************************************************** - * Assembly Macros - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - - .text - .syntax unified - .arm - -/**************************************************************************** - * Name: arm_vectoraddrexcptn - * - * Description: - * Shouldn't happen. This exception handler is in a separate file from - * other vector handlers because some processors do not support the - * Address Exception vector. - * - ****************************************************************************/ - - .globl arm_vectoraddrexcptn - .type arm_vectoraddrexcptn, %function -arm_vectoraddrexcptn: - b arm_vectoraddrexcptn - .size arm_vectoraddrexcptn, . - arm_vectoraddrexcptn - .end diff --git a/arch/arm/src/armv8-r/arm_vectors.S b/arch/arm/src/armv8-r/arm_vectors.S index cd62baf4f6b7d..78b32446a7cea 100644 --- a/arch/arm/src/armv8-r/arm_vectors.S +++ b/arch/arm/src/armv8-r/arm_vectors.S @@ -716,6 +716,22 @@ arm_vectorfiq: #endif .size arm_vectorfiq, . - arm_vectorfiq +/**************************************************************************** + * Name: arm_vectoraddrexcptn + * + * Description: + * Shouldn't happen. This exception handler is in a separate file from + * other vector handlers because some processors do not support the + * Address Exception vector. + * + ****************************************************************************/ + + .globl arm_vectoraddrexcptn + .type arm_vectoraddrexcptn, %function +arm_vectoraddrexcptn: + b arm_vectoraddrexcptn + .size arm_vectoraddrexcptn, . - arm_vectoraddrexcptn + /**************************************************************************** * Name: g_intstackalloc/g_intstacktop ****************************************************************************/ diff --git a/arch/arm/src/at32/at32_serial.c b/arch/arm/src/at32/at32_serial.c index b776cd9f7f27d..05c70cd96775e 100644 --- a/arch/arm/src/at32/at32_serial.c +++ b/arch/arm/src/at32/at32_serial.c @@ -1118,11 +1118,11 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); up_setusartint(priv, ie); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -1133,7 +1133,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (ie) { @@ -1174,7 +1174,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) up_setusartint(priv, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/arm/src/cmake/Toolchain.cmake b/arch/arm/src/cmake/Toolchain.cmake index 3d3de2368138c..4c55953543014 100644 --- a/arch/arm/src/cmake/Toolchain.cmake +++ b/arch/arm/src/cmake/Toolchain.cmake @@ -29,6 +29,8 @@ if(CONFIG_ARCH_ARMV7A) # ARMv7-A set(ARCH_SUBDIR armv7-a) elseif(CONFIG_ARCH_ARMV7R) # ARMv7-R set(ARCH_SUBDIR armv7-r) +elseif(CONFIG_ARCH_ARMV8R) # ARMv8-R + set(ARCH_SUBDIR armv8-r) elseif(CONFIG_ARCH_ARMV7M) # ARMv7-M set(ARCH_SUBDIR armv7-m) elseif(CONFIG_ARCH_ARMV8M) # ARMv8-M @@ -65,8 +67,8 @@ else() set(CMAKE_C_COMPILER_TARGET ${TOOLCHAIN_PREFIX}) set(CMAKE_CXX_COMPILER_TARGET ${TOOLCHAIN_PREFIX}) - set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) - set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}-gcc) + set(CMAKE_ASM_COMPILER ${TOOLCHAIN_PREFIX}-gcc) + set(CMAKE_C_COMPILER ${CMAKE_ASM_COMPILER}) set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}-g++) set(CMAKE_STRIP ${TOOLCHAIN_PREFIX}-strip --strip-unneeded) set(CMAKE_OBJCOPY ${TOOLCHAIN_PREFIX}-objcopy) @@ -182,13 +184,16 @@ if(CONFIG_DEBUG_SYMBOLS) endif() set(ARCHCFLAGS "-Wstrict-prototypes") -set(ARCHCXXFLAGS "-nostdinc++") -if(CONFIG_CXX_EXCEPTION) +if(NOT CONFIG_LIBCXXTOOLCHAIN) + set(ARCHCXXFLAGS "${ARCHCXXFLAGS} -nostdinc++") +endif() + +if(NOT CONFIG_CXX_EXCEPTION) string(APPEND ARCHCXXFLAGS " -fno-exceptions -fcheck-new") endif() -if(CONFIG_CXX_RTTI) +if(NOT CONFIG_CXX_RTTI) string(APPEND ARCHCXXFLAGS " -fno-rtti") endif() diff --git a/arch/arm/src/cmake/armv8-r.cmake b/arch/arm/src/cmake/armv8-r.cmake new file mode 100644 index 0000000000000..9b026c72be43c --- /dev/null +++ b/arch/arm/src/cmake/armv8-r.cmake @@ -0,0 +1,38 @@ +# ############################################################################## +# arch/arm/src/cmake/armv8-r.cmake +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(PLATFORM_FLAGS) + +if(CONFIG_ARCH_CORTEXR52) + list(APPEND PLATFORM_FLAGS -mcpu=cortex-r52) +endif() + +if(CONFIG_ARCH_FPU) + list(APPEND PLATFORM_FLAGS -mfpu=vfpv3-d16) + if(CONFIG_ARM_FPU_ABI_SOFT) + list(APPEND PLATFORM_FLAGS -mfloat-abi=softfp) + else() + list(APPEND PLATFORM_FLAGS -mfloat-abi=hard) + endif() +else() + list(APPEND PLATFORM_FLAGS -mfloat-abi=soft) +endif() + +add_compile_options(${PLATFORM_FLAGS}) diff --git a/arch/arm/src/cmake/platform.cmake b/arch/arm/src/cmake/platform.cmake index 5337cf994d056..3806f6f17fcc9 100644 --- a/arch/arm/src/cmake/platform.cmake +++ b/arch/arm/src/cmake/platform.cmake @@ -1,5 +1,5 @@ # ############################################################################## -# ./arch/arm/src/cmake/platform.cmake +# arch/arm/src/cmake/platform.cmake # # Licensed to the Apache Software Foundation (ASF) under one or more contributor # license agreements. See the NOTICE file distributed with this work for @@ -50,6 +50,8 @@ elseif(CONFIG_ARCH_CORTEXR5) set(CMAKE_SYSTEM_PROCESSOR cortex-r5) elseif(CONFIG_ARCH_CORTEXR7) set(CMAKE_SYSTEM_PROCESSOR cortex-r7) +elseif(CONFIG_ARCH_CORTEXR52) + set(CMAKE_SYSTEM_PROCESSOR cortex-r8) else() message(FATAL_ERROR "CMAKE_SYSTEM_PROCESSOR not set") endif() @@ -57,15 +59,17 @@ endif() get_directory_property(NUTTX_EXTRA_FLAGS DIRECTORY ${CMAKE_SOURCE_DIR} COMPILE_OPTIONS) +separate_arguments(CMAKE_C_FLAG_ARGS NATIVE_COMMAND ${CMAKE_C_FLAGS}) + execute_process( - COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} ${NUTTX_EXTRA_FLAGS} + COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} ${NUTTX_EXTRA_FLAGS} --print-libgcc-file-name OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE extra_library) if(NOT EXISTS ${extra_library} AND CONFIG_ARCH_TOOLCHAIN_CLANG) get_filename_component(COMPILER_RT_LIB ${extra_library} NAME) execute_process( - COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} ${NUTTX_EXTRA_FLAGS} + COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} ${NUTTX_EXTRA_FLAGS} --print-file-name ${COMPILER_RT_LIB} OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE extra_library) @@ -75,7 +79,7 @@ list(APPEND EXTRA_LIB ${extra_library}) if(NOT CONFIG_LIBM) execute_process( - COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} ${NUTTX_EXTRA_FLAGS} + COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} ${NUTTX_EXTRA_FLAGS} --print-file-name=libm.a OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE extra_library) @@ -84,7 +88,7 @@ endif() if(CONFIG_LIBSUPCXX) execute_process( - COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} ${NUTTX_EXTRA_FLAGS} + COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} ${NUTTX_EXTRA_FLAGS} --print-file-name=libsupc++.a OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE extra_library) @@ -93,7 +97,7 @@ endif() if(CONFIG_ARCH_COVERAGE) execute_process( - COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} ${NUTTX_EXTRA_FLAGS} + COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} ${NUTTX_EXTRA_FLAGS} --print-file-name=libgcov.a OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE extra_library) @@ -102,5 +106,4 @@ endif() nuttx_add_extra_library(${EXTRA_LIB}) -separate_arguments(CMAKE_C_FLAG_ARGS NATIVE_COMMAND ${CMAKE_C_FLAGS}) set(PREPROCES ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} -E -P -x c) diff --git a/arch/arm/src/common/CMakeLists.txt b/arch/arm/src/common/CMakeLists.txt index ac630ec46b911..5776283ea2363 100644 --- a/arch/arm/src/common/CMakeLists.txt +++ b/arch/arm/src/common/CMakeLists.txt @@ -59,7 +59,8 @@ if(CONFIG_BUILD_PROTECTED OR CONFIG_BUILD_KERNEL) list(APPEND SRCS arm_task_start.c arm_pthread_start.c arm_signal_dispatch.c) if(CONFIG_BUILD_PROTECTED) - list(APPEND SRCS ${ARCH_TOOLCHAIN_PATH}/arm_signal_handler.S) + target_sources(arch_interface + PRIVATE ${ARCH_TOOLCHAIN_PATH}/arm_signal_handler.S) endif() endif() diff --git a/arch/arm/src/common/Toolchain.defs b/arch/arm/src/common/Toolchain.defs index 1e0184abc5cfd..e96aa55f02188 100644 --- a/arch/arm/src/common/Toolchain.defs +++ b/arch/arm/src/common/Toolchain.defs @@ -78,6 +78,10 @@ ifeq ($(CONFIG_MM_KASAN_ALL),y) ARCHOPTIMIZATION += -fsanitize=kernel-address endif +ifeq ($(CONFIG_MM_KASAN_GLOBAL),y) + ARCHOPTIMIZATION += --param asan-globals=1 +endif + ifeq ($(CONFIG_MM_KASAN_DISABLE_READS_CHECK),y) ARCHOPTIMIZATION += --param asan-instrument-reads=0 endif @@ -289,12 +293,16 @@ endif # Architecture flags ARCHCFLAGS += -Wstrict-prototypes -Wno-attributes -Wno-unknown-pragmas -ARCHCXXFLAGS += -nostdinc++ -Wno-attributes -Wno-unknown-pragmas +ARCHCXXFLAGS += -Wno-attributes -Wno-unknown-pragmas # When all C++ code is built using GCC 7.1 or a higher version, # we can safely disregard warnings of the type "parameter passing for X changed in GCC 7.1." # Refer to : https://stackoverflow.com/questions/48149323/what-does-the-gcc-warning-project-parameter-passing-for-x-changed-in-gcc-7-1-m +ifneq ($(CONFIG_LIBCXXTOOLCHAIN),y) + ARCHCXXFLAGS += -nostdinc++ +endif + ifneq ($(CONFIG_ARCH_TOOLCHAIN_CLANG),y) ARCHCFLAGS += -Wno-psabi ARCHCXXFLAGS += -Wno-psabi @@ -386,6 +394,10 @@ ifeq ($(CONFIG_ARCH_COVERAGE),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libgcov.a)) endif +ifeq ($(CONFIG_LIBCXXTOOLCHAIN),y) + EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libstdc++.a)) +endif + # Zig toolchain include $(TOPDIR)/tools/Zig.defs diff --git a/arch/arm/src/common/arm_allocateheap.c b/arch/arm/src/common/arm_allocateheap.c index ef28edc82899b..f3678176af629 100644 --- a/arch/arm/src/common/arm_allocateheap.c +++ b/arch/arm/src/common/arm_allocateheap.c @@ -36,6 +36,7 @@ #include #include "arm_internal.h" +#include "chip.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/common/arm_backtrace_fp.c b/arch/arm/src/common/arm_backtrace_fp.c index 85c62f23ce5b4..cfb624a4157ff 100644 --- a/arch/arm/src/common/arm_backtrace_fp.c +++ b/arch/arm/src/common/arm_backtrace_fp.c @@ -105,9 +105,6 @@ int up_backtrace(struct tcb_s *tcb, void **buffer, int size, int skip) { struct tcb_s *rtcb = running_task(); -#if CONFIG_ARCH_INTERRUPTSTACK > 7 - void *istacklimit; -#endif irqstate_t flags; int ret; @@ -121,13 +118,10 @@ int up_backtrace(struct tcb_s *tcb, if (up_interrupt_context()) { #if CONFIG_ARCH_INTERRUPTSTACK > 7 -# ifdef CONFIG_SMP - istacklimit = (void *)arm_intstack_top(); -# else - istacklimit = g_intstacktop; -# endif /* CONFIG_SMP */ - ret = backtrace(istacklimit - (CONFIG_ARCH_INTERRUPTSTACK & ~7), - istacklimit, + void *istackbase = (void *)up_get_intstackbase(up_cpu_index()); + + ret = backtrace(istackbase, + istackbase + INTSTACK_SIZE, (void *)__builtin_frame_address(0), NULL, buffer, size, &skip); #else diff --git a/arch/arm/src/common/arm_backtrace_sp.c b/arch/arm/src/common/arm_backtrace_sp.c index 47ec8f324eba5..afca4ec3bf03b 100644 --- a/arch/arm/src/common/arm_backtrace_sp.c +++ b/arch/arm/src/common/arm_backtrace_sp.c @@ -257,16 +257,12 @@ int up_backtrace(struct tcb_s *tcb, if (up_interrupt_context()) { - unsigned long top; + unsigned long top = #if CONFIG_ARCH_INTERRUPTSTACK > 7 -# ifdef CONFIG_SMP - top = arm_intstack_top(); -# else - top = (unsigned long)g_intstacktop; -# endif /* CONFIG_SMP */ + up_get_intstackbase(up_cpu_index()) + INTSTACK_SIZE; #else - top = (unsigned long)rtcb->stack_base_ptr + - rtcb->adj_stack_size; + (unsigned long)rtcb->stack_base_ptr + + rtcb->adj_stack_size; #endif ret = backtrace_branch(top, sp, buffer, size, &skip); if (ret < size) diff --git a/arch/arm/src/common/arm_backtrace_unwind.c b/arch/arm/src/common/arm_backtrace_unwind.c index 9369f916158f5..8b670244a4c3d 100644 --- a/arch/arm/src/common/arm_backtrace_unwind.c +++ b/arch/arm/src/common/arm_backtrace_unwind.c @@ -724,11 +724,8 @@ int up_backtrace(struct tcb_s *tcb, if (up_interrupt_context()) { #if CONFIG_ARCH_INTERRUPTSTACK > 7 -# ifdef CONFIG_SMP - frame.stack_top = arm_intstack_top(); -# else - frame.stack_top = (unsigned long)&g_intstacktop; -# endif /* CONFIG_SMP */ + frame.stack_top = up_get_intstackbase(up_cpu_index()) + + INTSTACK_SIZE; #endif /* CONFIG_ARCH_INTERRUPTSTACK > 7 */ ret = backtrace_unwind(&frame, buffer, size, &skip); diff --git a/arch/arm/src/common/arm_checkstack.c b/arch/arm/src/common/arm_checkstack.c index dd4b53d5cb915..7f3c6415ddbed 100644 --- a/arch/arm/src/common/arm_checkstack.c +++ b/arch/arm/src/common/arm_checkstack.c @@ -224,9 +224,9 @@ size_t up_check_tcbstack(struct tcb_s *tcb) } #if CONFIG_ARCH_INTERRUPTSTACK > 3 -size_t up_check_intstack(void) +size_t up_check_intstack(int cpu) { - return arm_stack_check((void *)up_get_intstackbase(), + return arm_stack_check((void *)up_get_intstackbase(cpu), STACK_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK)); } #endif diff --git a/arch/arm/src/common/arm_exit.c b/arch/arm/src/common/arm_exit.c index 2a68b93ddb24b..0f12c17600860 100644 --- a/arch/arm/src/common/arm_exit.c +++ b/arch/arm/src/common/arm_exit.c @@ -62,8 +62,6 @@ void up_exit(int status) enter_critical_section(); - sinfo("TCB=%p exiting\n", tcb); - nxsched_dumponexit(); /* Destroy the task at the head of the ready to run list. */ diff --git a/arch/arm/src/common/arm_getintstack.c b/arch/arm/src/common/arm_getintstack.c index b2617d79fe6bd..d2a5b1a5fac00 100644 --- a/arch/arm/src/common/arm_getintstack.c +++ b/arch/arm/src/common/arm_getintstack.c @@ -24,8 +24,6 @@ #include -#include - #include "arm_internal.h" /**************************************************************************** @@ -36,14 +34,9 @@ * Name: up_get_intstackbase ****************************************************************************/ -#if CONFIG_ARCH_INTERRUPTSTACK > 3 -uintptr_t up_get_intstackbase(void) +#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 3 +uintptr_t up_get_intstackbase(int cpu) { -#ifdef CONFIG_SMP - return arm_intstack_alloc(); -#else return (uintptr_t)g_intstackalloc; -#endif } #endif - diff --git a/arch/arm/src/common/arm_initialize.c b/arch/arm/src/common/arm_initialize.c index 65a09495e5d8e..5d18bf66eb50c 100644 --- a/arch/arm/src/common/arm_initialize.c +++ b/arch/arm/src/common/arm_initialize.c @@ -33,7 +33,7 @@ ****************************************************************************/ /* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt + * register storage structure. It is non-NULL only during interrupt * processing. Access to g_current_regs[] must be through the macro * CURRENT_REGS for portability. */ @@ -57,18 +57,15 @@ volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; static inline void arm_color_intstack(void) { #ifdef CONFIG_SMP - uint32_t *ptr = (uint32_t *)arm_intstack_alloc(); -#else - uint32_t *ptr = (uint32_t *)g_intstackalloc; -#endif - ssize_t size; + int cpu; - for (size = ((CONFIG_ARCH_INTERRUPTSTACK & ~3) * CONFIG_SMP_NCPUS); - size > 0; - size -= sizeof(uint32_t)) + for (cpu = 0; cpu < CONFIG_SMP_NCPUS; cpu++) { - *ptr++ = INTSTACK_COLOR; + arm_stack_color((void *)up_get_intstackbase(cpu), INTSTACK_SIZE); } +#else + arm_stack_color((void *)g_intstackalloc, INTSTACK_SIZE); +#endif } #else # define arm_color_intstack() diff --git a/arch/arm/src/common/arm_internal.h b/arch/arm/src/common/arm_internal.h index f8971cf41c213..eb33e5ec2f068 100644 --- a/arch/arm/src/common/arm_internal.h +++ b/arch/arm/src/common/arm_internal.h @@ -349,11 +349,6 @@ void arm_pminitialize(void); /* Interrupt handling *******************************************************/ -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -uintptr_t arm_intstack_alloc(void); -uintptr_t arm_intstack_top(void); -#endif - #if CONFIG_ARCH_INTERRUPTSTACK > 7 void weak_function arm_initialize_stack(void); #endif @@ -402,14 +397,20 @@ int arm_securefault(int irq, void *context, void *arg); #elif defined(CONFIG_ARCH_ARMV7A) || defined(CONFIG_ARCH_ARMV7R) || defined(CONFIG_ARCH_ARMV8R) +/* Interrupt acknowledge and dispatch */ + +#ifdef CONFIG_ARCH_HIPRI_INTERRUPT +uint32_t *arm_dofiq(int fiq, uint32_t *regs); +#endif + /* Paging support */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING void arm_pginitialize(void); uint32_t *arm_va2pte(uintptr_t vaddr); -#else /* CONFIG_PAGING */ +#else /* CONFIG_LEGACY_PAGING */ # define arm_pginitialize() -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ /* Exception Handlers */ @@ -424,14 +425,14 @@ uint32_t *arm_undefinedinsn(uint32_t *regs); /* Paging support (and exception handlers) */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING void arm_pginitialize(void); uint32_t *arm_va2pte(uintptr_t vaddr); void arm_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr); -#else /* CONFIG_PAGING */ +#else /* CONFIG_LEGACY_PAGING */ # define arm_pginitialize() void arm_dataabort(uint32_t *regs); -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ /* Exception handlers */ diff --git a/arch/arm/src/cxd56xx/Kconfig b/arch/arm/src/cxd56xx/Kconfig index 8d3b7c27b39aa..f28d0692e10a2 100644 --- a/arch/arm/src/cxd56xx/Kconfig +++ b/arch/arm/src/cxd56xx/Kconfig @@ -1436,4 +1436,22 @@ config CXD56_USE_SYSBUS ---help--- To make ldrex/strex work correctly, this option must be enabled +config CXD56_GNSS_RAM + bool "Use GNSS RAM as general memory" + default !CXD56_SUBCORE + ---help--- + Enable to use GNSS RAM as general memory. As long as the GNSS feature + is not used, GNSS RAM can be used as general memory. This memory is + 640KByte total, which is lower performance than the application RAM. + +if CXD56_GNSS_RAM + +config CXD56_GNSS_HEAP + bool "Use GNSS RAM as heap memory" + default y + ---help--- + Enable to use GNSS RAM as heap memory. + +endif # CXD56_GNSS_RAM + endmenu diff --git a/arch/arm/src/cxd56xx/Make.defs b/arch/arm/src/cxd56xx/Make.defs index c7fef91031ed1..54c653c050d1b 100644 --- a/arch/arm/src/cxd56xx/Make.defs +++ b/arch/arm/src/cxd56xx/Make.defs @@ -169,3 +169,7 @@ endif ifeq ($(CONFIG_CXD56_HOSTIF),y) CHIP_CSRCS += cxd56_hostif.c endif + +ifeq ($(CONFIG_CXD56_GNSS_HEAP),y) +CHIP_CSRCS += cxd56_gnssheap.c +endif diff --git a/arch/arm/src/cxd56xx/cxd56_cisif.c b/arch/arm/src/cxd56xx/cxd56_cisif.c index 651e625bf069b..dcb30fa2b386d 100644 --- a/arch/arm/src/cxd56xx/cxd56_cisif.c +++ b/arch/arm/src/cxd56xx/cxd56_cisif.c @@ -978,14 +978,36 @@ static int cxd56_cisif_validate_buf(struct imgdata_s *data, return OK; } +static int32_t cisif_get_mode(uint8_t nr_datafmts, + imgdata_format_t *datafmts) +{ + switch (datafmts[IMGDATA_FMT_MAIN].pixelformat) + { + case IMGDATA_PIX_FMT_UYVY: /* YUV 4:2:2 */ + case IMGDATA_PIX_FMT_RGB565: /* RGB565 */ + + /* CISIF does not distinguish between YUV and RGB */ + + return MODE_YUV_TRS_EN; + + case IMGDATA_PIX_FMT_JPEG: /* JPEG */ + return MODE_JPG_TRS_EN; + + case IMGDATA_PIX_FMT_JPEG_WITH_SUBIMG: /* JPEG + YUV 4:2:2 */ + return MODE_INTLEV_TRS_EN; + + default: + return -EINVAL; + } +} + static int cxd56_cisif_set_buf(struct imgdata_s *data, uint8_t nr_datafmts, - FAR imgdata_format_t *datafmts, + imgdata_format_t *datafmts, uint8_t *addr, uint32_t size) { int ret; - uint32_t mode; - uint32_t regval; + int32_t mode; uint16_t w; uint16_t h; @@ -995,7 +1017,7 @@ static int cxd56_cisif_set_buf(struct imgdata_s *data, return ret; } - mode = cisif_reg_read(CISIF_MODE); + mode = cisif_get_mode(nr_datafmts, datafmts); switch (mode) { @@ -1007,18 +1029,19 @@ static int cxd56_cisif_set_buf(struct imgdata_s *data, ret = cisif_set_jpg_sarea(addr, size); break; - default: /* MODE_INTLEV_TRS_EN */ - - /* Get YUV frame size information */ + case MODE_INTLEV_TRS_EN: - regval = cisif_reg_read(CISIF_ACT_SIZE); - h = (regval >> 16) & 0x1ff; - w = regval & 0x01ff; + w = datafmts[IMGDATA_FMT_SUB].width; + h = datafmts[IMGDATA_FMT_SUB].height; ret = cisif_set_intlev_sarea(addr, size, YUV_SIZE(w, h)); break; + + default: + ret = -EINVAL; + break; } if (ret != OK) diff --git a/arch/arm/src/cxd56xx/cxd56_clock.c b/arch/arm/src/cxd56xx/cxd56_clock.c index 4b7e3d578b491..ef62efdd7efb9 100644 --- a/arch/arm/src/cxd56xx/cxd56_clock.c +++ b/arch/arm/src/cxd56xx/cxd56_clock.c @@ -69,6 +69,8 @@ #define PDID_SCU 0 #define PDID_APP_DSP 9 #define PDID_APP_SUB 10 +#define PDID_GNSS_ITP 12 +#define PDID_GNSS 13 #define PDID_APP_AUD 14 /* For enable_apwd, disable_apwd (analog domain) */ @@ -2602,6 +2604,41 @@ int cxd56_hostseq_clock_disable(void) return ret; } +int cxd56_gnssram_clock_enable(void) +{ + uint32_t stat; + + stat = getreg32(CXD56_TOPREG_PWD_STAT); + if ((stat & (1u << PDID_GNSS)) && (stat & (1u << PDID_GNSS_ITP))) + { + /* Already power on */ + + return OK; + } + + /* Enable all of GNSS RAM memory power. */ + + putreg32(0xff00ffff, CXD56_TOPREG_GNSS_RAMMODE_SEL); + enable_pwd(PDID_GNSS_ITP); + enable_pwd(PDID_GNSS); + putreg32(0x143, CXD56_TOPREG_GNSDSP_CKEN); + busy_wait(10); + putreg32(0x103, CXD56_TOPREG_GNSDSP_CKEN); + putreg32(0x10000, CXD56_TOPREG_SWRESET_GNSDSP); + putreg32(0x153, CXD56_TOPREG_GNSDSP_CKEN); + return OK; +} + +int cxd56_gnssram_clock_disable(void) +{ + putreg32(0x0, CXD56_TOPREG_GNSDSP_CKEN); + putreg32(0x0, CXD56_TOPREG_SWRESET_GNSDSP); + putreg32(0xff000000, CXD56_TOPREG_GNSS_RAMMODE_SEL); + disable_pwd(PDID_GNSS); + disable_pwd(PDID_GNSS_ITP); + return OK; +} + int up_pmramctrl(int cmd, uintptr_t addr, size_t size) { int startidx; diff --git a/arch/arm/src/cxd56xx/cxd56_clock.h b/arch/arm/src/cxd56xx/cxd56_clock.h index 81014ca1fb8b5..0968a4a4d77ac 100644 --- a/arch/arm/src/cxd56xx/cxd56_clock.h +++ b/arch/arm/src/cxd56xx/cxd56_clock.h @@ -724,6 +724,26 @@ int cxd56_hostseq_clock_enable(void); int cxd56_hostseq_clock_disable(void); +/**************************************************************************** + * Name: cxd56_gnssram_clock_enable + * + * Description: + * Enable clock of the GNSS RAM + * + ****************************************************************************/ + +int cxd56_gnssram_clock_enable(void); + +/**************************************************************************** + * Name: cxd56_gnssram_clock_disable + * + * Description: + * Disable clock of the GNSS RAM + * + ****************************************************************************/ + +int cxd56_gnssram_clock_disable(void); + #undef EXTERN #if defined(__cplusplus) } diff --git a/arch/arm/src/cxd56xx/cxd56_cpupause.c b/arch/arm/src/cxd56xx/cxd56_cpupause.c index 476c684331add..2e1a6a9542862 100644 --- a/arch/arm/src/cxd56xx/cxd56_cpupause.c +++ b/arch/arm/src/cxd56xx/cxd56_cpupause.c @@ -167,7 +167,7 @@ bool up_cpu_pausereq(int cpu) } /**************************************************************************** - * Name: up_cpu_paused + * Name: up_cpu_paused_save * * Description: * Handle a pause request from another CPU. Normally, this logic is @@ -176,16 +176,8 @@ bool up_cpu_pausereq(int cpu) * pause operation in other contexts where the interrupt cannot be taken * in order to avoid deadlocks. * - * This function performs the following operations: - * - * 1. It saves the current task state at the head of the current assigned - * task list. - * 2. It waits on a spinlock, then - * 3. Returns from interrupt, restoring the state of the new task at the - * head of the ready to run list. - * * Input Parameters: - * cpu - The index of the CPU to be paused + * None * * Returned Value: * On success, OK is returned. Otherwise, a negated errno value indicating @@ -193,15 +185,8 @@ bool up_cpu_pausereq(int cpu) * ****************************************************************************/ -int up_cpu_paused(int cpu) +int up_cpu_paused_save(void) { - /* Fistly, check if this IPI is to enable/disable IRQ */ - - if (handle_irqreq(cpu)) - { - return OK; - } - struct tcb_s *tcb = this_task(); /* Update scheduler parameters */ @@ -220,6 +205,45 @@ int up_cpu_paused(int cpu) arm_savestate(tcb->xcp.regs); + return OK; +} + +/**************************************************************************** + * Name: up_cpu_paused + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. + * + * This function performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. + * + * Input Parameters: + * cpu - The index of the CPU to be paused + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused(int cpu) +{ + /* Fistly, check if this IPI is to enable/disable IRQ */ + + if (handle_irqreq(cpu)) + { + return OK; + } + /* Wait for the spinlock to be released */ spin_unlock(&g_cpu_paused[cpu]); @@ -230,11 +254,31 @@ int up_cpu_paused(int cpu) spin_lock(&g_cpu_wait[cpu]); - /* Restore the exception context of the tcb at the (new) head of the - * assigned task list. - */ + spin_unlock(&g_cpu_wait[cpu]); + spin_unlock(&g_cpu_resumed[cpu]); - tcb = this_task(); + return OK; +} + +/**************************************************************************** + * Name: up_cpu_paused_restore + * + * Description: + * Restore the state of the CPU after it was paused via up_cpu_pause(), + * and resume normal tasking. + * + * Input Parameters: + * None + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused_restore(void) +{ + struct tcb_s *tcb = this_task(); #ifdef CONFIG_SCHED_INSTRUMENTATION /* Notify that we have resumed */ @@ -251,8 +295,6 @@ int up_cpu_paused(int cpu) */ arm_restorestate(tcb->xcp.regs); - spin_unlock(&g_cpu_wait[cpu]); - spin_unlock(&g_cpu_resumed[cpu]); return OK; } diff --git a/arch/arm/src/cxd56xx/cxd56_farapistub.h b/arch/arm/src/cxd56xx/cxd56_farapistub.h index a58e2eca953a7..0cafa916c6849 100644 --- a/arch/arm/src/cxd56xx/cxd56_farapistub.h +++ b/arch/arm/src/cxd56xx/cxd56_farapistub.h @@ -21,6 +21,6 @@ #ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_FARAPISTUB_H #define __ARCH_ARM_SRC_CXD56XX_CXD56_FARAPISTUB_H -#define FARAPISTUB_VERSION 20585 +#define FARAPISTUB_VERSION 20591 #endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_FARAPISTUB_H */ diff --git a/arch/arm/src/cxd56xx/cxd56_gnssheap.c b/arch/arm/src/cxd56xx/cxd56_gnssheap.c new file mode 100644 index 0000000000000..cd7c93b456776 --- /dev/null +++ b/arch/arm/src/cxd56xx/cxd56_gnssheap.c @@ -0,0 +1,196 @@ +/**************************************************************************** + * arch/arm/src/cxd56xx/cxd56_gnssheap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "cxd56_clock.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct mm_heap_s *g_gnssheap; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_gnssram_initialize + * + * Description: + * Initialize the GNSS heap. + * + ****************************************************************************/ + +void up_gnssram_initialize(void) +{ + void *start; + size_t size; + + /* These values come from the linker scripts. */ + + extern uint8_t _sgnssheap[]; + extern uint8_t _egnssheap[]; + + cxd56_gnssram_clock_enable(); + + start = (void *)_sgnssheap; + size = (size_t)(_egnssheap - _sgnssheap); + g_gnssheap = mm_initialize("gnssheap", start, size); +} + +/**************************************************************************** + * Name: up_gnssram_uninitialize + * + * Description: + * Uninitialize the GNSS heap. + * + ****************************************************************************/ + +void up_gnssram_uninitialize(void) +{ + mm_uninitialize(g_gnssheap); +} + +/**************************************************************************** + * Name: up_gnssram_malloc + * + * Description: + * Allocate memory from the GNSS heap. + * + ****************************************************************************/ + +void *up_gnssram_malloc(size_t size) +{ + return mm_malloc(g_gnssheap, size); +} + +/**************************************************************************** + * Name: up_gnssram_calloc + * + * Description: + * Calculates the size of the allocation and allocate memory from + * the GNSS heap. + * + ****************************************************************************/ + +void *up_gnssram_calloc(size_t n, size_t elem_size) +{ + return mm_calloc(g_gnssheap, n, elem_size); +} + +/**************************************************************************** + * Name: up_gnssram_realloc + * + * Description: + * Reallocate memory from the GNSS heap. + * + ****************************************************************************/ + +void *up_gnssram_realloc(void *ptr, size_t size) +{ + return mm_realloc(g_gnssheap, ptr, size); +} + +/**************************************************************************** + * Name: up_gnssram_zalloc + * + * Description: + * Allocate and zero memory from the GNSS heap. + * + ****************************************************************************/ + +void *up_gnssram_zalloc(size_t size) +{ + return mm_zalloc(g_gnssheap, size); +} + +/**************************************************************************** + * Name: up_gnssram_free + * + * Description: + * Free memory from the GNSS heap. + * + ****************************************************************************/ + +void up_gnssram_free(void *mem) +{ + mm_free(g_gnssheap, mem); +} + +/**************************************************************************** + * Name: up_gnssram_memalign + * + * Description: + * memalign requests more than enough space from malloc, finds a region + * within that chunk that meets the alignment request and then frees any + * leading or trailing space. + * + * The alignment argument must be a power of two (not checked). 8-byte + * alignment is guaranteed by normal malloc calls. + * + ****************************************************************************/ + +void *up_gnssram_memalign(size_t alignment, size_t size) +{ + return mm_memalign(g_gnssheap, alignment, size); +} + +/**************************************************************************** + * Name: up_gnssram_heapmember + * + * Description: + * Check if an address lies in the GNSS heap. + * + * Parameters: + * mem - The address to check + * + * Return Value: + * true if the address is a member of the GNSS heap. false if not + * + ****************************************************************************/ + +bool up_gnssram_heapmember(void *mem) +{ + return mm_heapmember(g_gnssheap, mem); +} + +/**************************************************************************** + * Name: up_gnssram_mallinfo + * + * Description: + * mallinfo returns a copy of updated current heap information for the + * user heap. + * + ****************************************************************************/ + +struct mallinfo up_gnssram_mallinfo(void) +{ + return mm_mallinfo(g_gnssheap); +} diff --git a/arch/arm/src/cxd56xx/cxd56_irq.c b/arch/arm/src/cxd56xx/cxd56_irq.c index 5885ed53fe807..4f5b7bbc7a9ff 100644 --- a/arch/arm/src/cxd56xx/cxd56_irq.c +++ b/arch/arm/src/cxd56xx/cxd56_irq.c @@ -573,23 +573,7 @@ int up_prioritize_irq(int irq, int priority) #endif /**************************************************************************** - * Name: arm_intstack_top - * - * Description: - * Return a pointer to the top the correct interrupt stack allocation - * for the current CPU. - * - ****************************************************************************/ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -uintptr_t arm_intstack_top(void) -{ - return g_cpu_intstack_top[up_cpu_index()]; -} -#endif - -/**************************************************************************** - * Name: arm_intstack_alloc + * Name: up_get_intstackbase * * Description: * Return a pointer to the "alloc" the correct interrupt stack allocation @@ -598,8 +582,8 @@ uintptr_t arm_intstack_top(void) ****************************************************************************/ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -uintptr_t arm_intstack_alloc(void) +uintptr_t up_get_intstackbase(int cpu) { - return g_cpu_intstack_top[up_cpu_index()] - INTSTACK_SIZE; + return g_cpu_intstack_top[cpu] - INTSTACK_SIZE; } #endif diff --git a/arch/arm/src/cxd56xx/cxd56_nxaudio.c b/arch/arm/src/cxd56xx/cxd56_nxaudio.c index 6551111157b98..2831b6e0cf2e1 100644 --- a/arch/arm/src/cxd56xx/cxd56_nxaudio.c +++ b/arch/arm/src/cxd56xx/cxd56_nxaudio.c @@ -2020,8 +2020,8 @@ static int cxd56_set_mic_gains(uint8_t gain, enum cxd56_mic_type_e mic_dev, static void cxd56_get_mic_config(uint8_t *count, uint8_t *dev, uint8_t *mode) { uint8_t i; - uint8_t is_dmic; - uint8_t is_amic; + bool is_dmic = false; + bool is_amic = false; uint8_t mic_sel = 0; uint8_t mic_count = 0; diff --git a/arch/arm/src/cxd56xx/cxd56_start.c b/arch/arm/src/cxd56xx/cxd56_start.c index efca5ffc45c64..078f05d3a0568 100644 --- a/arch/arm/src/cxd56xx/cxd56_start.c +++ b/arch/arm/src/cxd56xx/cxd56_start.c @@ -164,6 +164,18 @@ void __start(void) *dest++ = 0; } +#ifdef CONFIG_CXD56_GNSS_RAM + /* Clear .gnssram.bss section. */ + + extern uint8_t _gnssramsbss[]; + extern uint8_t _gnssramebss[]; + + for (dest = (uint32_t *)_gnssramsbss; dest < (uint32_t *)_gnssramebss; ) + { + *dest++ = 0; + } +#endif + /* Initialize the FPU (if configured) */ arm_fpuconfig(); diff --git a/arch/arm/src/cxd56xx/hardware/cxd5602_topreg.h b/arch/arm/src/cxd56xx/hardware/cxd5602_topreg.h index 73504f5ab4d7e..a14a2b7e62b8f 100644 --- a/arch/arm/src/cxd56xx/hardware/cxd5602_topreg.h +++ b/arch/arm/src/cxd56xx/hardware/cxd5602_topreg.h @@ -241,6 +241,7 @@ #define CXD56_TOPREG_FUSEWRAD (CXD56_TOPREG_BASE + 0x0a04) #define CXD56_TOPREG_FUSEWRDT (CXD56_TOPREG_BASE + 0x0a08) #define CXD56_TOPREG_FUSEWRPG (CXD56_TOPREG_BASE + 0x0a0c) +#define CXD56_TOPREG_GNSS_RAMMODE_SEL (CXD56_TOPREG_BASE + 0x0c00) #define CXD56_TOPREG_ADSP1_BOOT_ENTRY_POINT (CXD56_TOPREG_BASE + 0x1010) #define CXD56_TOPREG_ADSP2_BOOT_ENTRY_POINT (CXD56_TOPREG_BASE + 0x1014) #define CXD56_TOPREG_ADSP3_BOOT_ENTRY_POINT (CXD56_TOPREG_BASE + 0x1018) diff --git a/arch/arm/src/efm32/efm32_leserial.c b/arch/arm/src/efm32/efm32_leserial.c index 4c66ea3525080..c8d396cd26f53 100644 --- a/arch/arm/src/efm32/efm32_leserial.c +++ b/arch/arm/src/efm32/efm32_leserial.c @@ -308,10 +308,10 @@ static void efm32_restoreuartint(struct efm32_leuart_s *priv, uint32_t ien) * bits in ien. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); priv->ien = ien; efm32_setuartint(priv); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -322,14 +322,14 @@ static void efm32_disableuartint(struct efm32_leuart_s *priv, uint32_t *ien) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (ien) { *ien = priv->ien; } efm32_restoreuartint(priv, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/arm/src/efm32/efm32_serial.c b/arch/arm/src/efm32/efm32_serial.c index 7e32cc1448c1b..e25831420706f 100644 --- a/arch/arm/src/efm32/efm32_serial.c +++ b/arch/arm/src/efm32/efm32_serial.c @@ -522,10 +522,10 @@ static void efm32_restoreuartint(struct efm32_usart_s *priv, uint32_t ien) * ien */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); priv->ien = ien; efm32_setuartint(priv); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -537,14 +537,14 @@ static void efm32_disableuartint(struct efm32_usart_s *priv, uint32_t *ien) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (ien) { *ien = priv->ien; } efm32_restoreuartint(priv, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } #endif diff --git a/arch/arm/src/fvp-v8r-aarch32/CMakeLists.txt b/arch/arm/src/fvp-v8r-aarch32/CMakeLists.txt new file mode 100644 index 0000000000000..51834e91095a3 --- /dev/null +++ b/arch/arm/src/fvp-v8r-aarch32/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# arch/arm/src/fvp-v8r-aarch32/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS fvp_boot.c fvp_serial.c) + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/fvp-v8r-aarch32/Make.defs b/arch/arm/src/fvp-v8r-aarch32/Make.defs index f27c3aa36d2c2..00030a2a88690 100644 --- a/arch/arm/src/fvp-v8r-aarch32/Make.defs +++ b/arch/arm/src/fvp-v8r-aarch32/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# arch/arm/src/fvp-v8r/Make.defs +# arch/arm/src/fvp-v8r-aarch32/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with @@ -21,4 +21,4 @@ include armv8-r/Make.defs # fvp-specific C source files -CHIP_CSRCS = fvp_boot.c fvp_serial.c +CHIP_CSRCS = fvp_boot.c fvp_serial.c diff --git a/arch/arm/src/fvp-v8r-aarch32/fvp_boot.c b/arch/arm/src/fvp-v8r-aarch32/fvp_boot.c index cd90415731bc2..f48f8d94400f2 100644 --- a/arch/arm/src/fvp-v8r-aarch32/fvp_boot.c +++ b/arch/arm/src/fvp-v8r-aarch32/fvp_boot.c @@ -30,12 +30,15 @@ #include +#include "arm_internal.h" + #include "barriers.h" #include "cp15.h" #include "arm_gic.h" #include "chip.h" #include "fvp_boot.h" -#include "serial_pl011.h" + +#include /**************************************************************************** * Private Data diff --git a/arch/arm/src/fvp-v8r-aarch32/fvp_serial.c b/arch/arm/src/fvp-v8r-aarch32/fvp_serial.c index 2b1355850b3bf..677f9ae2bcf01 100644 --- a/arch/arm/src/fvp-v8r-aarch32/fvp_serial.c +++ b/arch/arm/src/fvp-v8r-aarch32/fvp_serial.c @@ -56,7 +56,9 @@ void arm_earlyserialinit(void) * when they are first opened. */ +#ifdef CONFIG_UART_PL011 pl011_earlyserialinit(); +#endif } /*************************************************************************** @@ -69,7 +71,16 @@ void arm_earlyserialinit(void) void arm_serialinit(void) { +#ifdef CONFIG_UART_PL011 pl011_serialinit(); +#endif +} + +#else /* USE_SERIALDRIVER */ + +int up_putc(int ch) +{ + return 0; } #endif /* USE_SERIALDRIVER */ diff --git a/arch/arm/src/fvp-v8r-aarch32/serial_pl011.h b/arch/arm/src/fvp-v8r-aarch32/serial_pl011.h deleted file mode 100644 index 1c91902a28cf3..0000000000000 --- a/arch/arm/src/fvp-v8r-aarch32/serial_pl011.h +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** - * arch/arm/src/fvp-v8r-aarch32/serial_pl011.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_FVP_V8R_SERIAL_PL011_H -#define __ARCH_ARM_SRC_FVP_V8R_SERIAL_PL011_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_FVP_V8R_SERIAL_PL011_H */ diff --git a/arch/arm/src/gd32f4/Kconfig b/arch/arm/src/gd32f4/Kconfig index c47c8d8021215..9852b46a94771 100644 --- a/arch/arm/src/gd32f4/Kconfig +++ b/arch/arm/src/gd32f4/Kconfig @@ -774,9 +774,9 @@ config GD32F4_ONESHOT_MAXTIMERS timers that you can use. # config GD32F4_TIMER0 -# bool "TIMER0" -# default n -# depend on GD32F4_HAVE_TIMER0 +# bool "TIMER0" +# default n +# depend on GD32F4_HAVE_TIMER0 config GD32F4_TIMER0_PWM bool "TIMER0 PWM" diff --git a/arch/arm/src/gd32f4/gd32f4xx_serial.c b/arch/arm/src/gd32f4/gd32f4xx_serial.c index b401ffc7295df..348840af5542d 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_serial.c +++ b/arch/arm/src/gd32f4/gd32f4xx_serial.c @@ -1124,7 +1124,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint32_t *ie) irqstate_t flags; uint32_t ctl_ie; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (ie) { @@ -1158,7 +1158,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint32_t *ie) ctl_ie = (USART_CFG_CTL_MASK << USART_CFG_SHIFT); up_setusartint(priv, ctl_ie); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -1169,11 +1169,11 @@ static void up_restoreusartint(struct up_dev_s *priv, uint32_t ie) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); up_setusartint(priv, ie); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/arm/src/goldfish/Kconfig b/arch/arm/src/goldfish/Kconfig index 9526d26a59091..4c92b8f90168d 100644 --- a/arch/arm/src/goldfish/Kconfig +++ b/arch/arm/src/goldfish/Kconfig @@ -17,7 +17,6 @@ config ARCH_CHIP_GOLDFISH_CORTEXA7 select ARCH_HAVE_ADDRENV select ARCH_HAVE_LOWVECTORS select ARCH_HAVE_MULTICPU - select ARCH_HAVE_TRUSTZONE select ARCH_NEED_ADDRENV_MAPPING select ARMV7A_HAVE_GICv2 select ARMV7A_HAVE_GTM @@ -27,4 +26,15 @@ endchoice # Goldfish Chip Selection endmenu # "Goldfish Virt Chip Selection" +config ARCH_CHIP_GOLDFISH_TRUSTZONE + bool "Enable Arm Security Extensions (TrustZone)" + select ARCH_HAVE_TRUSTZONE + default n + ---help--- + Doc: https://qemu-project.gitlab.io/qemu/system/arm/virt.html + shows that set secure=on/of can emulating a guest CPU which + implements the Arm Security Extensions (TrustZone). + The default is off. And this config can enable/disable + TrustZone in qemu chip. + endif # ARCH_CHIP_GOLDFISH_ARM diff --git a/arch/arm/src/goldfish/chip.h b/arch/arm/src/goldfish/chip.h index 355e3b37d6110..5dee28a9bf919 100644 --- a/arch/arm/src/goldfish/chip.h +++ b/arch/arm/src/goldfish/chip.h @@ -31,12 +31,17 @@ * Pre-processor Definitions ****************************************************************************/ +#define QEMU_SPI_IRQ_BASE 32 #define CHIP_MPCORE_VBASE 0x8000000 #define MPCORE_ICD_OFFSET 0x0000 #define MPCORE_ICC_OFFSET 0x10000 -#define PGTABLE_BASE_PADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - ALL_PGTABLE_SIZE) -#define PGTABLE_BASE_VADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - ALL_PGTABLE_SIZE) +#define PGTABLE_SIZE 0x00004000 +#define PGTABLE_BASE_PADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - PGTABLE_SIZE * CONFIG_SMP_NCPUS) +#define PGTABLE_BASE_VADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - PGTABLE_SIZE * CONFIG_SMP_NCPUS) + +#undef CONFIG_RAM_END +#define CONFIG_RAM_END PGTABLE_BASE_PADDR #define NUTTX_TEXT_VADDR (CONFIG_FLASH_VSTART & 0xfff00000) #define NUTTX_TEXT_PADDR (CONFIG_FLASH_VSTART & 0xfff00000) diff --git a/arch/arm/src/goldfish/goldfish_boot.c b/arch/arm/src/goldfish/goldfish_boot.c index c0b6bac29c839..b9bf51f473b8d 100644 --- a/arch/arm/src/goldfish/goldfish_boot.c +++ b/arch/arm/src/goldfish/goldfish_boot.c @@ -47,6 +47,10 @@ void arm_boot(void) { + /* Perf init */ + + up_perf_init(0); + /* Set the page table for section */ goldfish_setupmappings(); diff --git a/arch/arm/src/goldfish/goldfish_irq.c b/arch/arm/src/goldfish/goldfish_irq.c index b06b09b97eff2..43b71830c7b16 100644 --- a/arch/arm/src/goldfish/goldfish_irq.c +++ b/arch/arm/src/goldfish/goldfish_irq.c @@ -127,23 +127,7 @@ void up_irqinitialize(void) } /**************************************************************************** - * Name: arm_intstack_top - * - * Description: - * Return a pointer to the top the correct interrupt stack allocation - * for the current CPU. - * - ****************************************************************************/ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -uintptr_t arm_intstack_top(void) -{ - return g_irqstack_top[up_cpu_index()]; -} -#endif - -/**************************************************************************** - * Name: arm_intstack_alloc + * Name: up_get_intstackbase * * Description: * Return a pointer to the "alloc" the correct interrupt stack allocation @@ -152,8 +136,8 @@ uintptr_t arm_intstack_top(void) ****************************************************************************/ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -uintptr_t arm_intstack_alloc(void) +uintptr_t up_get_intstackbase(int cpu) { - return g_irqstack_top[up_cpu_index()] - INTSTACK_SIZE; + return g_irqstack_top[cpu] - INTSTACK_SIZE; } #endif diff --git a/arch/arm/src/imx6/hardware/imx_memorymap.h b/arch/arm/src/imx6/hardware/imx_memorymap.h index 2067a92ca9752..e4bba00fbf3da 100644 --- a/arch/arm/src/imx6/hardware/imx_memorymap.h +++ b/arch/arm/src/imx6/hardware/imx_memorymap.h @@ -923,9 +923,9 @@ * memory to address 0x0000:0000 using both the MMU and the AXI matrix * REMAP register. So no L2 page table is required. * - * 2) If on-demand paging is supported (CONFIG_PAGING=y), than an additional - * L2 page table is needed. This page table will use the remainder of - * the address space. + * 2) If on-demand paging is supported (CONFIG_LEGACY_PAGING=y), than an + * additional L2 page table is needed. This page table will use the + * remainder of the address space. */ #ifndef CONFIG_ARCH_LOWVECTORS @@ -974,7 +974,7 @@ /* Paging L2 page table base addresses * - * NOTE: If CONFIG_PAGING is defined, mmu.h will re-assign the virtual + * NOTE: If CONFIG_LEGACY_PAGING is defined, mmu.h will re-assign the virtual * address of the page table. */ diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c index 764943cbd7a95..cb27a2ac494a8 100644 --- a/arch/arm/src/imx6/imx_boot.c +++ b/arch/arm/src/imx6/imx_boot.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif @@ -111,7 +111,7 @@ static inline void imx_remap(void) ****************************************************************************/ #if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && \ - defined(CONFIG_PAGING) + defined(CONFIG_LEGACY_PAGING) static void imx_vectorpermissions(uint32_t mmuflags) { /* The PTE for the beginning of OCRAM is at the base of the L2 page table */ @@ -215,7 +215,7 @@ static void imx_copyvectorblock(void) uint32_t *end; uint32_t *dest; -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /* If we are using re-mapped vectors in an area that has been marked * read only, then temporarily mark the mapping write-able (non-buffered). */ @@ -241,7 +241,7 @@ static void imx_copyvectorblock(void) *dest++ = *src++; } -#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING) +#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_LEGACY_PAGING) /* Make the vectors read-only, cacheable again */ imx_vectorpermissions(MMU_L2_VECTORFLAGS); diff --git a/arch/arm/src/imx6/imx_gpio.c b/arch/arm/src/imx6/imx_gpio.c index 133d13a4c7995..6a77d6b0afe6a 100644 --- a/arch/arm/src/imx6/imx_gpio.c +++ b/arch/arm/src/imx6/imx_gpio.c @@ -29,6 +29,7 @@ #include #include +#include #include "chip.h" #include "arm_internal.h" @@ -512,7 +513,7 @@ int imx_config_gpio(gpio_pinset_t pinset) /* Configure the pin as an input initially to avoid any spurious outputs */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); /* Configure based upon the pin mode */ @@ -555,7 +556,7 @@ int imx_config_gpio(gpio_pinset_t pinset) break; } - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); return ret; } diff --git a/arch/arm/src/imx6/imx_irq.c b/arch/arm/src/imx6/imx_irq.c index 7fad4ff632276..97e65671e07ca 100644 --- a/arch/arm/src/imx6/imx_irq.c +++ b/arch/arm/src/imx6/imx_irq.c @@ -152,23 +152,7 @@ void up_irqinitialize(void) } /**************************************************************************** - * Name: arm_intstack_top - * - * Description: - * Return a pointer to the top the correct interrupt stack allocation - * for the current CPU. - * - ****************************************************************************/ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -uintptr_t arm_intstack_top(void) -{ - return g_irqstack_top[up_cpu_index()]; -} -#endif - -/**************************************************************************** - * Name: arm_intstack_alloc + * Name: up_get_intstackbase * * Description: * Return a pointer to the "alloc" the correct interrupt stack allocation @@ -177,8 +161,8 @@ uintptr_t arm_intstack_top(void) ****************************************************************************/ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -uintptr_t arm_intstack_alloc(void) +uintptr_t up_get_intstackbase(int cpu) { - return g_irqstack_top[up_cpu_index()] - INTSTACK_SIZE; + return g_irqstack_top[cpu] - INTSTACK_SIZE; } #endif diff --git a/arch/arm/src/imxrt/Kconfig b/arch/arm/src/imxrt/Kconfig index 5de5cb6a44334..872493bd4d68f 100644 --- a/arch/arm/src/imxrt/Kconfig +++ b/arch/arm/src/imxrt/Kconfig @@ -226,6 +226,7 @@ endmenu # Application Image Configuration config IMXRT_USDHC bool default n + select ARCH_HAVE_SDIO_PREFLIGHT config IMXRT_FLEXIO bool @@ -2613,7 +2614,7 @@ config IMXRT_SRAM_HEAPOFFSET Used to reserve memory at the beginning of SRAM for, as an example, a framebuffer. -endmenu # i.MX RT Heap Configuration +endmenu # i.MX RT Heap Configuration config IMXRT_FLEXRAM_PARTITION bool "Set FlexRAM Paritioning" diff --git a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ccm.h b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ccm.h index 763c257ccb88c..f60b0095f541f 100644 --- a/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ccm.h +++ b/arch/arm/src/imxrt/hardware/rt117x/imxrt117x_ccm.h @@ -754,7 +754,7 @@ #define CCM_CCGR_MU_A 20 #define CCM_CCGR_MU_B 21 #define CCM_CCGR_EDMA 22 -#define CCM_CCGR_DMA 22 //Note Added CTRL for compatiblity +#define CCM_CCGR_DMA 22 /* Note Added CTRL for compatiblity */ #define CCM_CCGR_EDMA_LPSR 23 #define CCM_CCGR_ROMCP 24 #define CCM_CCGR_OCRAM 25 @@ -770,10 +770,10 @@ #define CCM_CCGR_IEE 35 #define CCM_CCGR_KEY_MANAGER 36 #define CCM_CCGR_PUF 36 -#define CCM_CCGR_OCOTP_CTRL 37 //Note Added CTRL for compatiblity +#define CCM_CCGR_OCOTP_CTRL 37 /* Note Added CTRL for compatiblity */ #define CCM_CCGR_SNVS_HP 38 #define CCM_CCGR_SNVS 39 -#define CCM_CCGR_SNVS_LP 39 //Note Added CTRL for compatiblity +#define CCM_CCGR_SNVS_LP 39 /* Note Added CTRL for compatiblity */ #define CCM_CCGR_CAAM 40 #define CCM_CCGR_JTAG_MUX 41 #define CCM_CCGR_CSTRACE 42 @@ -796,7 +796,7 @@ #define CCM_CCGR_ACMP2 59 #define CCM_CCGR_ACMP3 60 #define CCM_CCGR_ACMP4 61 -#define CCM_CCGR_PIT 62 // Renamed from PIT1 to PIT for compatibility +#define CCM_CCGR_PIT 62 /* Renamed from PIT1 to PIT for compatibility */ #define CCM_CCGR_PIT2 63 #define CCM_CCGR_GPT1 64 #define CCM_CCGR_GPT2 65 diff --git a/arch/arm/src/imxrt/imxrt117x_mpuinit.c b/arch/arm/src/imxrt/imxrt117x_mpuinit.c index 2f5a9117ebacd..529705798fe85 100644 --- a/arch/arm/src/imxrt/imxrt117x_mpuinit.c +++ b/arch/arm/src/imxrt/imxrt117x_mpuinit.c @@ -51,6 +51,7 @@ MPU_RASR_XN; /* Execute-never to prevent instruction fetch */ putreg32(regval, MPU_RASR); +#ifdef CONFIG_IMXRT_SEMC mpu_configure_region(IMXRT_SEMC0_BASE, 512 * 1024 * 1024, /* Instruction access Enabled */ @@ -62,6 +63,7 @@ /* Not Shareable */ /* No Subregion disable */ ); +#endif mpu_configure_region(IMXRT_FLEXSPI2_CIPHER_BASE, 512 * 1024 * 1024, @@ -91,7 +93,7 @@ /* Instruction access Enabled */ - MPU_RASR_AP_RWRW | /* P:RW U:RW */ + MPU_RASR_AP_RORO | /* P:R0 U:R0 */ MPU_RASR_TEX_NOR /* Normal */ /* Not Cacheable */ /* Not Bufferable */ diff --git a/arch/arm/src/imxrt/imxrt_enet.c b/arch/arm/src/imxrt/imxrt_enet.c index df8a72489c835..bd70a5ac28bcd 100644 --- a/arch/arm/src/imxrt/imxrt_enet.c +++ b/arch/arm/src/imxrt/imxrt_enet.c @@ -250,8 +250,25 @@ * ...and further PHY descriptions here. */ -#if defined(CONFIG_ETH0_PHY_KSZ8081) -# define BOARD_PHY_NAME "KSZ8081" +#if defined(CONFIG_ETH0_PHY_MULTI) +# if !defined(BOARD_ETH0_PHY_LIST) +# error "CONFIG_ETH0_PHY_MULTI requires board.h to define BOARD_ETH0_PHY_LIST!" +# endif +# define BOARD_PHY_NAME g_board_phys[priv->current_phy].name +# define BOARD_PHYID1 g_board_phys[priv->current_phy].id1 +# define BOARD_PHYID2 g_board_phys[priv->current_phy].id2 +# define BOARD_PHY_STATUS g_board_phys[priv->current_phy].status +# define BOARD_PHY_ADDR priv->current_phy_address +# define BOARD_PHY_10BASET(s) (imxrt_phy_status(priv, (s), g_board_phys[priv->current_phy].mbps10) != 0) +# define BOARD_PHY_100BASET(s) (imxrt_phy_status(priv, (s), g_board_phys[priv->current_phy].mbps100) != 0) +# define BOARD_PHY_ISDUPLEX(s) (imxrt_phy_status(priv, (s), g_board_phys[priv->current_phy].duplex) != 0) +# define BOARD_PHY_ISCLAUSE45() (g_board_phys[priv->current_phy].clause == 45) +# define CLAUSE45 +# define MMD1 1 +# define MMD1_PMA_STATUS1 1 +# define MMD1_PS1_RECEIVE_LINK_STATUS (1 << 2) +#elif defined(CONFIG_ETH0_PHY_KSZ8081) +# define BOARD_PHY_NAME MII_KSZ8081_NAME # define BOARD_PHYID1 MII_PHYID1_KSZ8081 # define BOARD_PHYID2 MII_PHYID2_KSZ8081 # define BOARD_PHY_STATUS MII_KSZ8081_PHYCTRL1 @@ -260,7 +277,7 @@ # define BOARD_PHY_100BASET(s) (((s) & MII_PHYCTRL1_MODE_100HDX) != 0) # define BOARD_PHY_ISDUPLEX(s) (((s) & MII_PHYCTRL1_MODE_DUPLEX) != 0) #elif defined(CONFIG_ETH0_PHY_LAN8720) -# define BOARD_PHY_NAME "LAN8720" +# define BOARD_PHY_NAME MII_LAN8720_NAME # define BOARD_PHYID1 MII_PHYID1_LAN8720 # define BOARD_PHYID2 MII_PHYID2_LAN8720 # define BOARD_PHY_STATUS MII_LAN8720_SCSR @@ -269,7 +286,7 @@ # define BOARD_PHY_100BASET(s) (((s)&MII_LAN8720_SPSCR_100MBPS) != 0) # define BOARD_PHY_ISDUPLEX(s) (((s)&MII_LAN8720_SPSCR_DUPLEX) != 0) #elif defined(CONFIG_ETH0_PHY_LAN8742A) -# define BOARD_PHY_NAME "LAN8742A" +# define BOARD_PHY_NAME MII_LAN8742A_NAME # define BOARD_PHYID1 MII_PHYID1_LAN8742A # define BOARD_PHYID2 MII_PHYID2_LAN8742A # define BOARD_PHY_STATUS MII_LAN8740_SCSR @@ -278,7 +295,7 @@ # define BOARD_PHY_100BASET(s) (((s)&MII_LAN8720_SPSCR_100MBPS) != 0) # define BOARD_PHY_ISDUPLEX(s) (((s)&MII_LAN8720_SPSCR_DUPLEX) != 0) #elif defined(CONFIG_ETH0_PHY_DP83825I) -# define BOARD_PHY_NAME "DP83825I" +# define BOARD_PHY_NAME MII_DP83825I_NAME # define BOARD_PHYID1 MII_PHYID1_DP83825I # define BOARD_PHYID2 MII_PHYID2_DP83825I # define BOARD_PHY_STATUS MII_DP83825I_PHYSTS @@ -287,7 +304,7 @@ # define BOARD_PHY_100BASET(s) (((s) & MII_DP83825I_PHYSTS_SPEED) == 0) # define BOARD_PHY_ISDUPLEX(s) (((s) & MII_DP83825I_PHYSTS_DUPLEX) != 0) #elif defined(CONFIG_ETH0_PHY_TJA1103) -# define BOARD_PHY_NAME "TJA1103" +# define BOARD_PHY_NAME MII_TJA1103_NAME # define BOARD_PHYID1 MII_PHYID1_TJA1103 # define BOARD_PHYID2 MII_PHYID2_TJA1103 # define BOARD_PHY_STATUS MII_TJA110X_BSR @@ -300,7 +317,7 @@ # define MMD1_PMA_STATUS1 1 # define MMD1_PS1_RECEIVE_LINK_STATUS (1 << 2) #elif defined(CONFIG_ETH0_PHY_YT8512) -# define BOARD_PHY_NAME "YT8512" +# define BOARD_PHY_NAME MII_YT8512_NAME # define BOARD_PHYID1 MII_PHYID1_YT8512 # define BOARD_PHYID2 MII_PHYID2_YT8512 # define BOARD_PHY_STATUS MII_YT8512_PHYSTS @@ -375,6 +392,10 @@ struct imxrt_driver_s struct enet_desc_s *txdesc; /* A pointer to the list of TX descriptor */ struct enet_desc_s *rxdesc; /* A pointer to the list of RX descriptors */ +#if defined(CONFIG_ETH0_PHY_MULTI) + uint8_t current_phy; /* The index of the PHY being used */ + uint8_t current_phy_address; /* The address of the PHY being used */ +#endif /* This holds the information visible to the NuttX network */ struct net_driver_s dev; /* Interface understood by the network */ @@ -384,6 +405,15 @@ struct imxrt_driver_s * Private Data ****************************************************************************/ +/* BOARD_ETH0_PHY_LIST provided by the board.h for CONFIG_ETH0_PHY_MULTI */ + +#if defined(CONFIG_ETH0_PHY_MULTI) +const struct phy_desc_s g_board_phys[] = + { + BOARD_ETH0_PHY_LIST + }; +#endif + static struct imxrt_driver_s g_enet[CONFIG_IMXRT_ENET_NETHIFS]; /* The DMA descriptors */ @@ -470,6 +500,13 @@ static int imxrt_ioctl(struct net_driver_s *dev, int cmd, /* PHY/MII support */ +#if defined(CONFIG_ETH0_PHY_MULTI) +static int imxrt_phy_is(struct imxrt_driver_s *priv, const char *name); +static int imxrt_phy_status(struct imxrt_driver_s *priv, int phydata, + uint16_t mask); +static int imxrt_determine_phy(struct imxrt_driver_s *priv); +#endif + #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) static int imxrt_phyintenable(struct imxrt_driver_s *priv); #endif @@ -1377,6 +1414,15 @@ static int imxrt_ifup_action(struct net_driver_s *dev, bool resetphy) /* Configure the PHY */ +#if defined(CONFIG_ETH0_PHY_MULTI) + ret = imxrt_determine_phy(priv); + if (ret < 0) + { + nerr("ERROR: Failed to determine the PHY: %d\n", ret); + return ret; + } +#endif + ret = imxrt_initphy(priv, resetphy); if (ret < 0) { @@ -1872,7 +1918,11 @@ static int imxrt_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) struct mii_ioctl_data_s *req = (struct mii_ioctl_data_s *)((uintptr_t)arg); #if defined(CLAUSE45) - if (MII_MSR == req->reg_num) + if ( +# if defined(CONFIG_ETH0_PHY_MULTI) + BOARD_PHY_ISCLAUSE45() && +# endif + MII_MSR == req->reg_num) { ret = imxrt_readmmd(priv, req->phy_id, MMD1, MMD1_PMA_STATUS1, &req->val_out); @@ -1926,46 +1976,60 @@ static int imxrt_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) #if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) static int imxrt_phyintenable(struct imxrt_driver_s *priv) { +#if defined(CONFIG_ETH0_PHY_KSZ8051) || defined(CONFIG_ETH0_PHY_KSZ8061) || \ + defined(CONFIG_ETH0_PHY_KSZ8081) || defined(CONFIG_ETH0_PHY_DP83825I) || \ + defined(CONFIG_ETH0_YT8512) || defined(CONFIG_ETH0_PHY_MULTI) + uint16_t phyval; int ret; -#if defined(CONFIG_ETH0_PHY_KSZ8051) || defined(CONFIG_ETH0_PHY_KSZ8061) || \ - defined(CONFIG_ETH0_PHY_KSZ8081) || defined(CONFIG_ETH0_PHY_DP83825I) + /* Compile time Kzxxxx defaults */ - /* Read the interrupt status register in order to clear any pending - * interrupts - */ + uint16_t mask = MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN; + uint8_t rreg = MII_KSZ8081_INT; + uint8_t wreg = rreg; - ret = imxrt_readmii(priv, priv->phyaddr, MII_KSZ8081_INT, &phyval); - if (ret == OK) - { - /* Enable link up/down interrupts */ + /* Compile time YT8512 defaults */ +# if defined(CONFIG_ETH0_YT8512) + mask = MII_YT8512_IMR_LD_EN | MII_YT8512_IMR_LU_EN; + rreg = MII_YT8512_ISR; + wreg = MII_YT8512_IMR; +# endif - ret = imxrt_writemii(priv, priv->phyaddr, MII_KSZ8081_INT, - (MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN)); + /* Run time YT8512 defaults */ +# if defined(CONFIG_ETH0_PHY_MULTI) + if (imxrt_phy_is(priv, MII_YT8512_NAME)) + { + mask = MII_YT8512_IMR_LD_EN | MII_YT8512_IMR_LU_EN; + rreg = MII_YT8512_ISR; + wreg = MII_YT8512_IMR; } - - return ret; -#elif defined(CONFIG_ETH0_YT8512) + else if (!(imxrt_phy_is(priv, MII_KSZ8051_NAME) || + imxrt_phy_is(priv, MII_KSZ8061_NAME) || + imxrt_phy_is(priv, MII_KSZ8081_NAME) || + imxrt_phy_is(priv, MII_DP83825I_NAME))) + { + return -ENOSYS; + } +# endif /* Read the interrupt status register in order to clear any pending * interrupts */ - ret = imxrt_readmii(priv, priv->phyaddr, MII_YT8512_ISR, &phyval); + ret = imxrt_readmii(priv, priv->phyaddr, rreg, &phyval); if (ret == OK) { /* Enable link up/down interrupts */ - ret = imxrt_writemii(priv, priv->phyaddr, MII_YT8512_IMR, - (MII_YT8512_IMR_LD_EN | MII_YT8512_IMR_LU_EN)); + ret = imxrt_writemii(priv, priv->phyaddr, wreg, mask); } return ret; #else # error Unrecognized PHY return -ENOSYS; -#endif +# endif } #endif @@ -2121,6 +2185,126 @@ static int imxrt_readmii(struct imxrt_driver_s *priv, uint8_t phyaddr, return OK; } +#if defined(CONFIG_ETH0_PHY_MULTI) +/**************************************************************************** + * Function: imxrt_determine_phy + * + * Description: + * Uses the board.h supplied PHY list to determine which PHY + * is populated on this board. + * + * Input Parameters: + * priv - Reference to the private ENET driver state structure + * + * Returned Value: + * Zero on success, a -ENOENT errno value on failure. + * + ****************************************************************************/ + +static int imxrt_determine_phy(struct imxrt_driver_s *priv) +{ + uint16_t phydata = 0xffff; + uint8_t phyaddr = 0; + uint8_t last_phyaddr = 0; + int retries; + int ret; + + for (priv->current_phy = 0; priv->current_phy < nitems(g_board_phys); + priv->current_phy++) + { + priv->current_phy_address = + (uint8_t) g_board_phys[priv->current_phy].address_lo; + last_phyaddr = g_board_phys[priv->current_phy].address_high == 0xffff ? + priv->current_phy_address : + (uint8_t) g_board_phys[priv->current_phy].address_high; + + for (phyaddr = priv->current_phy_address; phyaddr <= last_phyaddr; + phyaddr++) + { + retries = 0; + do + { + nxsig_usleep(100); + phydata = 0xffff; + ret = imxrt_readmii(priv, phyaddr, MII_PHYID1, &phydata); + } + while ((ret < 0 || phydata == 0xffff) && ++retries < 3); + + if (retries <= 3 && ret == 0 && + phydata == g_board_phys[priv->current_phy].id1) + { + do + { + nxsig_usleep(100); + phydata = 0xffff; + ret = imxrt_readmii(priv, phyaddr, MII_PHYID2, &phydata); + } + while ((ret < 0 || phydata == 0xffff) && ++retries < 3); + if (retries <= 3 && ret == 0 && + (phydata & 0xfff0) == + (g_board_phys[priv->current_phy].id2 & 0xfff0)) + { + return OK; + } + } + } + } + + return -ENOENT; +} + +/**************************************************************************** + * Function: imxrt_phy_is + * + * Description: + * Compares the name with the current selected PHY's name + * + * Input Parameters: + * priv - Reference to the private ENET driver state structure + * name - a pointer to comapre to. + * + * Returned Value: + * 1 on match, a 0 on no match. + * + ****************************************************************************/ + +static int imxrt_phy_is(struct imxrt_driver_s *priv, const char *name) +{ + return strcmp(g_board_phys[priv->current_phy].name, name) == 0; +} + +/**************************************************************************** + * Function: imxrt_phy_status + * + * Description: + * Compares the name with the current selected PHY's name. + * + * Input Parameters: + * priv - Reference to the private ENET driver state structure + * phydata - last read phy data - may be ignored if there is no + * status register defined by the current PHY. + * mask - A value to and with phydata if a status register is + * defined. Or the value retunred if no status register is + * defined. + * + * Returned Value: + * mask or (phydat & mask) + * + ****************************************************************************/ + +static int imxrt_phy_status(struct imxrt_driver_s *priv, int phydata, + uint16_t mask) +{ + int rv = mask; + if (g_board_phys[priv->current_phy].status != 0xffff) + { + rv &= phydata; + } + + return rv; +} +#endif + #if 0 #if defined(CLAUSE45) /**************************************************************************** @@ -2416,213 +2600,265 @@ static inline int imxrt_initphy(struct imxrt_driver_s *priv, bool renogphy) return -ENXIO; } -#ifdef CONFIG_ETH0_PHY_KSZ8081 - /* Reset PHY */ +#if defined(CONFIG_ETH0_PHY_KSZ8081) || defined(CONFIG_ETH0_PHY_MULTI) +# if defined(CONFIG_ETH0_PHY_MULTI) + if (imxrt_phy_is(priv, MII_KSZ8081_NAME)) + { +# endif + /* Reset PHY */ - imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET); + imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET); - /* Set RMII mode */ + /* Set RMII mode */ - ret = imxrt_readmii(priv, phyaddr, MII_KSZ8081_PHYCTRL2, &phydata); - if (ret < 0) - { - nerr("ERROR: Failed to read MII_KSZ8081_PHYCTRL2\n"); - return ret; - } + ret = imxrt_readmii(priv, phyaddr, MII_KSZ8081_PHYCTRL2, &phydata); + if (ret < 0) + { + nerr("ERROR: Failed to read MII_KSZ8081_PHYCTRL2\n"); + return ret; + } - /* Indicate 50MHz clock */ + /* Indicate 50MHz clock */ - imxrt_writemii(priv, phyaddr, MII_KSZ8081_PHYCTRL2, - (phydata | (1 << 7))); + imxrt_writemii(priv, phyaddr, MII_KSZ8081_PHYCTRL2, + (phydata | (1 << 7))); - /* Switch off NAND Tree mode (in case it was set via pinning) */ + /* Switch off NAND Tree mode (in case it was set via pinning) */ - ret = imxrt_readmii(priv, phyaddr, MII_KSZ8081_OMSO, &phydata); - if (ret < 0) - { - nerr("ERROR: Failed to read MII_KSZ8081_OMSO: %d\n", ret); - return ret; - } + ret = imxrt_readmii(priv, phyaddr, MII_KSZ8081_OMSO, &phydata); + if (ret < 0) + { + nerr("ERROR: Failed to read MII_KSZ8081_OMSO: %d\n", ret); + return ret; + } - imxrt_writemii(priv, phyaddr, MII_KSZ8081_OMSO, - (phydata & ~(1 << 5))); + imxrt_writemii(priv, phyaddr, MII_KSZ8081_OMSO, + (phydata & ~(1 << 5))); - /* Set Ethernet led to green = activity and yellow = link and */ + /* Set Ethernet led to green = activity and yellow = link and */ - ret = imxrt_readmii(priv, phyaddr, MII_KSZ8081_PHYCTRL2, &phydata); - if (ret < 0) - { - nerr("ERROR: Failed to read MII_KSZ8081_PHYCTRL2\n"); - return ret; + ret = imxrt_readmii(priv, phyaddr, MII_KSZ8081_PHYCTRL2, &phydata); + if (ret < 0) + { + nerr("ERROR: Failed to read MII_KSZ8081_PHYCTRL2\n"); + return ret; + } + + imxrt_writemii(priv, phyaddr, MII_KSZ8081_PHYCTRL2, + (phydata | (1 << 4))); + + imxrt_writemii(priv, phyaddr, MII_ADVERTISE, + MII_ADVERTISE_100BASETXFULL | + MII_ADVERTISE_100BASETXHALF | + MII_ADVERTISE_10BASETXFULL | + MII_ADVERTISE_10BASETXHALF | + MII_ADVERTISE_CSMA); +# if defined(CONFIG_ETH0_PHY_MULTI) } - imxrt_writemii(priv, phyaddr, MII_KSZ8081_PHYCTRL2, - (phydata | (1 << 4))); +# endif +#endif +#if defined (CONFIG_ETH0_PHY_LAN8720) || \ + defined (CONFIG_ETH0_PHY_LAN8742A) || \ + defined (CONFIG_ETH0_PHY_MULTI) - imxrt_writemii(priv, phyaddr, MII_ADVERTISE, - MII_ADVERTISE_100BASETXFULL | - MII_ADVERTISE_100BASETXHALF | - MII_ADVERTISE_10BASETXFULL | - MII_ADVERTISE_10BASETXHALF | - MII_ADVERTISE_CSMA); +# if defined(CONFIG_ETH0_PHY_MULTI) + if (imxrt_phy_is(priv, MII_LAN8720_NAME) || + imxrt_phy_is(priv, MII_LAN8742A_NAME)) + { +# endif -#elif defined (CONFIG_ETH0_PHY_LAN8720) || defined (CONFIG_ETH0_PHY_LAN8742A) - /* Make sure that PHY comes up in correct mode when it's reset */ + /* Make sure that PHY comes up in correct mode when it's reset */ - imxrt_writemii(priv, phyaddr, MII_LAN8720_MODES, - MII_LAN8720_MODES_RESV | MII_LAN8720_MODES_ALL | - MII_LAN8720_MODES_PHYAD(BOARD_PHY_ADDR)); + imxrt_writemii(priv, phyaddr, MII_LAN8720_MODES, + MII_LAN8720_MODES_RESV | MII_LAN8720_MODES_ALL | + MII_LAN8720_MODES_PHYAD(BOARD_PHY_ADDR)); - /* ...and reset PHY */ + /* ...and reset PHY */ - imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET); + imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET); -#elif defined (CONFIG_ETH0_PHY_DP83825I) +# if defined(CONFIG_ETH0_PHY_MULTI) + } +# endif +#endif +#if defined (CONFIG_ETH0_PHY_DP83825I) || defined (CONFIG_ETH0_PHY_MULTI) - /* Reset PHY */ +#if defined(CONFIG_ETH0_PHY_MULTI) + if (imxrt_phy_is(priv, MII_DP83825I_NAME)) + { +#endif - imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET); + /* Reset PHY */ - /* Set RMII mode and Indicate 50MHz clock */ + imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET); - imxrt_writemii(priv, phyaddr, MII_DP83825I_RCSR, - MII_DP83825I_RCSC_ELAST_2 | MII_DP83825I_RCSC_RMIICS); + /* Set RMII mode and Indicate 50MHz clock */ - imxrt_writemii(priv, phyaddr, MII_ADVERTISE, - MII_ADVERTISE_100BASETXFULL | - MII_ADVERTISE_100BASETXHALF | - MII_ADVERTISE_10BASETXFULL | - MII_ADVERTISE_10BASETXHALF | - MII_ADVERTISE_CSMA); + imxrt_writemii(priv, phyaddr, MII_DP83825I_RCSR, + MII_DP83825I_RCSC_ELAST_2 | + MII_DP83825I_RCSC_RMIICS); -#elif defined (CONFIG_ETH0_PHY_YT8512) + imxrt_writemii(priv, phyaddr, MII_ADVERTISE, + MII_ADVERTISE_100BASETXFULL | + MII_ADVERTISE_100BASETXHALF | + MII_ADVERTISE_10BASETXFULL | + MII_ADVERTISE_10BASETXHALF | + MII_ADVERTISE_CSMA); - /* Reset PHY */ +# if defined(CONFIG_ETH0_PHY_MULTI) + } +# endif +#endif - imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET); +#if defined(CONFIG_ETH0_PHY_YT8512) || defined(CONFIG_ETH0_PHY_MULTI) +# if defined(CONFIG_ETH0_PHY_MULTI) + if (!imxrt_phy_is(priv, MII_YT8512_NAME)) + { +# endif + /* Reset PHY */ - /* Config LEDs */ + imxrt_writemii(priv, phyaddr, MII_MCR, MII_MCR_RESET); - imxrt_writemii(priv, phyaddr, MII_YT8512_DEBUG_ADDR_OFFSET, - MII_YT8512_LED0); + /* Config LEDs */ - imxrt_readmii(priv, phyaddr, MII_YT8512_DEBUG_DATA, &phydata); + imxrt_writemii(priv, phyaddr, MII_YT8512_DEBUG_ADDR_OFFSET, + MII_YT8512_LED0); - imxrt_writemii(priv, phyaddr, MII_YT8512_DEBUG_ADDR_OFFSET, - MII_YT8512_LED0); + imxrt_readmii(priv, phyaddr, MII_YT8512_DEBUG_DATA, &phydata); - imxrt_writemii(priv, phyaddr, MII_YT8512_DEBUG_DATA, 0x331); + imxrt_writemii(priv, phyaddr, MII_YT8512_DEBUG_ADDR_OFFSET, + MII_YT8512_LED0); - imxrt_writemii(priv, phyaddr, MII_YT8512_DEBUG_ADDR_OFFSET, - MII_YT8512_LED1); + imxrt_writemii(priv, phyaddr, MII_YT8512_DEBUG_DATA, 0x331); - imxrt_readmii(priv, phyaddr, MII_YT8512_DEBUG_DATA, &phydata); + imxrt_writemii(priv, phyaddr, MII_YT8512_DEBUG_ADDR_OFFSET, + MII_YT8512_LED1); - imxrt_writemii(priv, phyaddr, MII_YT8512_DEBUG_ADDR_OFFSET, - MII_YT8512_LED1); + imxrt_readmii(priv, phyaddr, MII_YT8512_DEBUG_DATA, &phydata); - imxrt_writemii(priv, phyaddr, MII_YT8512_DEBUG_DATA, 0x30); + imxrt_writemii(priv, phyaddr, MII_YT8512_DEBUG_ADDR_OFFSET, + MII_YT8512_LED1); - /* Set negotiation */ + imxrt_writemii(priv, phyaddr, MII_YT8512_DEBUG_DATA, 0x30); - imxrt_writemii(priv, phyaddr, MII_ADVERTISE, - MII_ADVERTISE_100BASETXFULL | - MII_ADVERTISE_100BASETXHALF | - MII_ADVERTISE_10BASETXFULL | - MII_ADVERTISE_10BASETXHALF | - MII_ADVERTISE_CSMA); + /* Set negotiation */ + imxrt_writemii(priv, phyaddr, MII_ADVERTISE, + MII_ADVERTISE_100BASETXFULL | + MII_ADVERTISE_100BASETXHALF | + MII_ADVERTISE_10BASETXFULL | + MII_ADVERTISE_10BASETXHALF | + MII_ADVERTISE_CSMA); + +# if defined(CONFIG_ETH0_PHY_MULTI) + } +# endif #endif -#if !defined(CONFIG_ETH0_PHY_TJA1103) - /* Start auto negotiation */ +#if !defined(CONFIG_ETH0_PHY_TJA1103) +#if defined(CONFIG_ETH0_PHY_MULTI) + if (!imxrt_phy_is(priv, MII_TJA1103_NAME)) + { +#endif + /* Start auto negotiation */ - ninfo("%s: Start Autonegotiation...\n", BOARD_PHY_NAME); - imxrt_writemii(priv, phyaddr, MII_MCR, - (MII_MCR_ANRESTART | MII_MCR_ANENABLE)); + ninfo("%s: Start Autonegotiation...\n", BOARD_PHY_NAME); + imxrt_writemii(priv, phyaddr, MII_MCR, + (MII_MCR_ANRESTART | MII_MCR_ANENABLE)); - /* Wait for auto negotiation to complete */ + /* Wait for auto negotiation to complete */ - for (retries = 0; retries < LINK_NLOOPS; retries++) - { - ret = imxrt_readmii(priv, phyaddr, MII_MSR, &phydata); - if (ret < 0) + for (retries = 0; retries < LINK_NLOOPS; retries++) { - nerr("ERROR: Failed to read %s MII_MSR: %d\n", - BOARD_PHY_NAME, ret); - return ret; + ret = imxrt_readmii(priv, phyaddr, MII_MSR, &phydata); + if (ret < 0) + { + nerr("ERROR: Failed to read %s MII_MSR: %d\n", + BOARD_PHY_NAME, ret); + return ret; + } + + if (phydata & MII_MSR_ANEGCOMPLETE) + { + break; + } + + nxsig_usleep(LINK_WAITUS); } if (phydata & MII_MSR_ANEGCOMPLETE) { - break; + ninfo("%s: Autonegotiation complete\n", BOARD_PHY_NAME); + ninfo("%s: MII_MSR: %04x\n", BOARD_PHY_NAME, phydata); } + else + { + /* TODO: Autonegotiation has right now failed. Maybe the Eth + * cable is not connected. PHY chip have mechanisms to + * configure link OK. We should leave autconf on, and find a + * way to re-configure MCU whenever the link is ready. + */ - nxsig_usleep(LINK_WAITUS); - } - - if (phydata & MII_MSR_ANEGCOMPLETE) - { - ninfo("%s: Autonegotiation complete\n", BOARD_PHY_NAME); - ninfo("%s: MII_MSR: %04x\n", BOARD_PHY_NAME, phydata); - } - else - { - /* TODO: Autonegotiation has right now failed. Maybe the Eth cable - * is not connected. PHY chip have mechanisms to configure link - * OK. We should leave autconf on, and find a way to re-configure - * MCU whenever the link is ready. - */ - - ninfo("%s: Autonegotiation failed [%d] (is cable plugged-in ?), " - "default to 10Mbs mode\n", \ - BOARD_PHY_NAME, retries); + ninfo("%s: Autonegotiation failed [%d] (is cable plugged-in ?)" + ", default to 10Mbs mode\n", + BOARD_PHY_NAME, retries); - /* Stop auto negotiation */ + /* Stop auto negotiation */ - imxrt_writemii(priv, phyaddr, MII_MCR, 0); + imxrt_writemii(priv, phyaddr, MII_MCR, 0); + } +# if defined(CONFIG_ETH0_PHY_MULTI) } +# endif #endif } #if !defined(CONFIG_ETH0_PHY_TJA1103) - /* When we get here we have a (negotiated) speed and duplex. This is also - * the point we enter if renegotiation is turned off, so have multiple - * attempts at reading the status register in case the PHY isn't awake - * properly. - */ - - retries = 0; - do +# if defined(CONFIG_ETH0_PHY_MULTI) + if (!imxrt_phy_is(priv, MII_TJA1103_NAME)) { - phydata = 0xffff; - ret = imxrt_readmii(priv, phyaddr, BOARD_PHY_STATUS, &phydata); - } - while ((ret < 0 || phydata == 0xffff) && ++retries < 3); - - /* If we didn't successfully read anything and we haven't tried a physical - * renegotiation then lets do that - */ +# endif + /* When we get here we have a (negotiated) speed and duplex. This + * is also the point we enter if renegotiation is turned off, so have + * multiple attempts at reading the status register in case the PHY + * isn't awake properly. + */ - if (retries >= 3) - { - if (renogphy == false) + retries = 0; + do { - /* Give things one more chance with renegotiation turned on */ - - return imxrt_initphy(priv, true); + phydata = 0xffff; + ret = imxrt_readmii(priv, phyaddr, BOARD_PHY_STATUS, &phydata); } - else + while ((ret < 0 || phydata == 0xffff) && ++retries < 3); + + /* If we didn't successfully read anything and we haven't tried + * a physical renegotiation then lets do that + */ + + if (retries >= 3) { - /* That didn't end well, just give up */ + if (renogphy == false) + { + /* Give things one more chance with renegotiation turned on */ - nerr("ERROR: Failed to read %s BOARD_PHY_STATUS[%02x]: %d\n", - BOARD_PHY_NAME, BOARD_PHY_STATUS, ret); - return ret; + return imxrt_initphy(priv, true); + } + else + { + /* That didn't end well, just give up */ + + nerr("ERROR: Failed to read %s BOARD_PHY_STATUS[%02x]: %d\n", + BOARD_PHY_NAME, BOARD_PHY_STATUS, ret); + return ret; + } } - } - ninfo("%s: BOARD_PHY_STATUS: %04x\n", BOARD_PHY_NAME, phydata); + ninfo("%s: BOARD_PHY_STATUS: %04x\n", BOARD_PHY_NAME, phydata); +# if defined(CONFIG_ETH0_PHY_MULTI) + } +# endif #endif /* Set up the transmit and receive control registers based on the diff --git a/arch/arm/src/imxrt/imxrt_flexspi.c b/arch/arm/src/imxrt/imxrt_flexspi.c index adc108bde2e79..e55daa9051b9a 100644 --- a/arch/arm/src/imxrt/imxrt_flexspi.c +++ b/arch/arm/src/imxrt/imxrt_flexspi.c @@ -370,7 +370,7 @@ static uint32_t imxrt_flexspi_configure_dll(struct flexspi_type_s *base, } break; default: - assert(false); + ASSERT(false); break; } @@ -431,7 +431,7 @@ static int imxrt_flexspi_check_and_clear_error(struct flexspi_type_s *base, } else { - assert(false); + ASSERT(false); } /* Clear the flags */ @@ -808,7 +808,7 @@ void imxrt_flexspi_update_lut_private(struct flexspi_type_s *base, const uint32_t *cmd, uint32_t count) { - assert(index < 64u); + ASSERT(index < 64u); uint32_t i = 0; volatile uint32_t *lut_base; diff --git a/arch/arm/src/imxrt/imxrt_serial.c b/arch/arm/src/imxrt/imxrt_serial.c index f91be50d254bc..1605096b2b1ce 100644 --- a/arch/arm/src/imxrt/imxrt_serial.c +++ b/arch/arm/src/imxrt/imxrt_serial.c @@ -743,6 +743,7 @@ struct imxrt_uart_s #endif #ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE const uint32_t tx_gpio; /* TX GPIO pin configuration */ + const struct uart_ops_s *prev_ops; #endif uint8_t stopbits2:1; /* 1: Configure with 2 stop bits vs 1 */ @@ -806,11 +807,17 @@ static bool imxrt_rxavailable(struct uart_dev_s *dev); #if !defined(SERIAL_HAVE_ONLY_TXDMA) static void imxrt_txint(struct uart_dev_s *dev, bool enable); #endif +#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE +static void imxrt_singlewire_txint(struct uart_dev_s *dev, bool enable); +#endif #ifdef CONFIG_SERIAL_IFLOWCONTROL static bool imxrt_rxflowcontrol(struct uart_dev_s *dev, unsigned int nbuffered, bool upper); #endif +#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE +static void imxrt_singlewire_send(struct uart_dev_s *dev, int ch); +#endif static void imxrt_send(struct uart_dev_s *dev, int ch); static bool imxrt_txready(struct uart_dev_s *dev); @@ -855,6 +862,27 @@ static int up_pm_prepare(struct pm_callback_s *cb, int domain, /* Serial driver UART operations */ +#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE +static const struct uart_ops_s g_lpuart_singlewire_ops = +{ + .setup = imxrt_setup, + .shutdown = imxrt_shutdown, + .attach = imxrt_attach, + .detach = imxrt_detach, + .ioctl = imxrt_ioctl, + .receive = imxrt_receive, + .rxint = imxrt_rxint, + .rxavailable = imxrt_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = imxrt_rxflowcontrol, +#endif + .send = imxrt_singlewire_send, + .txint = imxrt_singlewire_txint, + .txready = imxrt_txready, + .txempty = imxrt_txempty, +}; +#endif + #if !defined(SERIAL_HAVE_ONLY_TXDMA) && !defined(SERIAL_HAVE_ONLY_RXDMA) static const struct uart_ops_s g_lpuart_ops = { @@ -2629,7 +2657,9 @@ static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg) if ((arg & SER_SINGLEWIRE_ENABLED) != 0) { - uint32_t gpio_val = IOMUX_OPENDRAIN; + uint32_t gpio_val = (arg & SER_SINGLEWIRE_PUSHPULL) == + SER_SINGLEWIRE_PUSHPULL ? + IOMUX_CMOS_OUTPUT : IOMUX_OPENDRAIN; gpio_val |= (arg & SER_SINGLEWIRE_PULL_MASK) == SER_SINGLEWIRE_PULLUP ? IOMUX_PULL_UP : IOMUX_PULL_NONE; @@ -2639,6 +2669,8 @@ static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg) imxrt_config_gpio((priv->tx_gpio & ~(IOMUX_PULL_MASK | IOMUX_OPENDRAIN)) | gpio_val); regval |= LPUART_CTRL_LOOPS | LPUART_CTRL_RSRC; + priv->prev_ops = priv->dev.ops; + priv->dev.ops = &g_lpuart_singlewire_ops; } else { @@ -2646,6 +2678,10 @@ static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg) IOMUX_OPENDRAIN)) | IOMUX_PULL_NONE); regval &= ~(LPUART_CTRL_LOOPS | LPUART_CTRL_RSRC); + if (priv->dev.ops == &g_lpuart_singlewire_ops) + { + priv->dev.ops = priv->prev_ops; + } } imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, regval); @@ -3206,6 +3242,34 @@ static void imxrt_dma_send(struct uart_dev_s *dev) } #endif +#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE +/**************************************************************************** + * Name: imxrt_singlewire_send + * + * Description: + * This method will will switch TXDIR to an output + * and send one byte on the UART + * + ****************************************************************************/ + +static void imxrt_singlewire_send(struct uart_dev_s *dev, int ch) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev; + uint32_t regval; + irqstate_t flags; + + flags = spin_lock_irqsave(NULL); + regval = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET); + regval &= ~(LPUART_CTRL_RSRC); + regval |= (LPUART_CTRL_TXDIR); + imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, regval); + spin_unlock_irqrestore(NULL, flags); + + imxrt_serialout(priv, IMXRT_LPUART_DATA_OFFSET, (uint32_t)ch); +} + +#endif + /**************************************************************************** * Name: imxrt_send * @@ -3279,6 +3343,51 @@ static void imxrt_txint(struct uart_dev_s *dev, bool enable) } #endif +/**************************************************************************** + * Name: imxrt_singlewire_txint + * + * Description: + * Call to enable or disable TX interrupts in single wire mode + * + ****************************************************************************/ + +#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE +static void imxrt_singlewire_txint(struct uart_dev_s *dev, bool enable) +{ + struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev; + irqstate_t flags; + uint32_t regval; + + /* Enable interrupt for TX complete */ + + flags = spin_lock_irqsave(NULL); + regval = imxrt_serialin(priv, IMXRT_LPUART_CTRL_OFFSET); + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ie |= LPUART_CTRL_TIE; +#endif + } + else + { + /* Don't disable TX interrupt yet if transmission isn't complete */ + + if (imxrt_txempty(dev)) + { + regval |= LPUART_CTRL_RSRC; + regval &= ~(LPUART_CTRL_TXDIR); + priv->ie &= ~LPUART_CTRL_TIE; + } + } + + regval &= ~LPUART_ALL_INTS; + regval |= priv->ie; + + imxrt_serialout(priv, IMXRT_LPUART_CTRL_OFFSET, regval); + spin_unlock_irqrestore(NULL, flags); +} +#endif + /**************************************************************************** * Name: imxrt_txready * diff --git a/arch/arm/src/imxrt/imxrt_start.c b/arch/arm/src/imxrt/imxrt_start.c index cc51d70e4ebac..107e03dae1879 100644 --- a/arch/arm/src/imxrt/imxrt_start.c +++ b/arch/arm/src/imxrt/imxrt_start.c @@ -149,11 +149,16 @@ void __start(void) const register uint32_t *src; register uint32_t *dest; - /* Make sure that interrupts are disabled and set SP */ + /* Make sure that interrupts are disabled and set MSP */ __asm__ __volatile__ ("\tcpsid i\n"); __asm__ __volatile__ ("MSR MSP, %0\n" : : "r" (IDLE_STACK) :); + /* Make sure that we use MSP from now on */ + + __asm__ __volatile__ ("MSR CONTROL, %0\n" : : "r" (0) :); + __asm__ __volatile__ ("ISB SY\n"); + /* Make sure VECTAB is set to NuttX vector table * and not the one from the boot ROM and have consistency * with debugger that automatically set the VECTAB diff --git a/arch/arm/src/imxrt/imxrt_usdhc.c b/arch/arm/src/imxrt/imxrt_usdhc.c index b831dc3fd154b..81a0851fc3276 100644 --- a/arch/arm/src/imxrt/imxrt_usdhc.c +++ b/arch/arm/src/imxrt/imxrt_usdhc.c @@ -352,6 +352,10 @@ static int imxrt_registercallback(struct sdio_dev_s *dev, /* DMA */ #ifdef CONFIG_IMXRT_USDHC_DMA +# if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) +static int imxrt_dmapreflight(struct sdio_dev_s *dev, + const uint8_t *buffer, size_t buflen); +# endif static int imxrt_dmarecvsetup(struct sdio_dev_s *dev, uint8_t *buffer, size_t buflen); static int imxrt_dmasendsetup(struct sdio_dev_s *dev, @@ -415,6 +419,9 @@ struct imxrt_dev_s g_sdhcdev[IMXRT_MAX_SDHC_DEV_SLOTS] = .registercallback = imxrt_registercallback, #ifdef CONFIG_SDIO_DMA #ifdef CONFIG_IMXRT_USDHC_DMA +# if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) + .dmapreflight = imxrt_dmapreflight, +# endif .dmarecvsetup = imxrt_dmarecvsetup, .dmasendsetup = imxrt_dmasendsetup, #else @@ -473,6 +480,9 @@ struct imxrt_dev_s g_sdhcdev[IMXRT_MAX_SDHC_DEV_SLOTS] = .callbackenable = imxrt_callbackenable, .registercallback = imxrt_registercallback, #ifdef CONFIG_SDIO_DMA +# if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) + .dmapreflight = imxrt_dmapreflight, +# endif #ifdef CONFIG_IMXRT_USDHC_DMA .dmarecvsetup = imxrt_dmarecvsetup, .dmasendsetup = imxrt_dmasendsetup, @@ -2911,6 +2921,60 @@ static int imxrt_registercallback(struct sdio_dev_s *dev, return OK; } +/**************************************************************************** + * Name: imxrt_dmapreflight + * + * Description: + * Preflight an SDIO DMA operation. If the buffer is not well-formed for + * SDIO DMA transfer (alignment, size, etc.) returns an error. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * buffer - The memory to DMA to/from + * buflen - The size of the DMA transfer in bytes + * + * Returned Value: + * OK on success; a negated errno on failure + ****************************************************************************/ + +#if defined(CONFIG_IMXRT_USDHC_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) +static int imxrt_dmapreflight(struct sdio_dev_s *dev, + const uint8_t *buffer, size_t buflen) +{ + struct imxrt_dev_s *priv = (struct imxrt_dev_s *)dev; + DEBUGASSERT(priv != NULL && buflen > 0); + + /* DMA must be possible to the buffer and it must be word (4 bytes) aligned + */ + + if (buffer != priv->rxbuffer && ((uintptr_t)buffer & 3) != 0) + { + mcerr("non word aligned buffer:%p\n", buffer); + return -EFAULT; + } + +#if defined(CONFIG_ARMV7M_DCACHE) + /* buffer alignment is required for DMA transfers with dcache in buffered + * mode (not write-through) because a) arch_invalidate_dcache could lose + * buffered writes and b) arch_flush_dcache could corrupt adjacent memory + * if the maddr and the mend+1, the next next address are not on + * ARMV7M_DCACHE_LINESIZE boundaries. + */ + + if (buffer != priv->rxbuffer && + (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE - 1)) != 0 || + ((uintptr_t)(buffer + buflen) & (ARMV7M_DCACHE_LINESIZE - 1)) != 0)) + { + mcerr("dcache unaligned buffer:%p end:%p\n", + buffer, buffer + buflen - 1); + return -EFAULT; + } +#endif + + return 0; +} +#endif + /**************************************************************************** * Name: imxrt_dmarecvsetup * @@ -2936,7 +3000,19 @@ static int imxrt_dmarecvsetup(struct sdio_dev_s *dev, { struct imxrt_dev_s *priv = (struct imxrt_dev_s *)dev; DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); - DEBUGASSERT(((uint32_t) buffer & 3) == 0); +#if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) + /* Normaly imxrt_dmapreflight is called prior to imxrt_dmarecvsetup + * except for the case where the CSR read is done at initalization + * + * With a total read size of less then priv->rxbuffer we can + * handel the unaligned case herein, using the rxbuffer. + * + * Any other case is a falult. + */ + + DEBUGASSERT(buflen <= sizeof(priv->rxbuffer) || + imxrt_dmapreflight(dev, buffer, buflen) == 0); +#endif /* Begin sampling register values */ @@ -2947,8 +3023,8 @@ static int imxrt_dmarecvsetup(struct sdio_dev_s *dev, if (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE - 1)) != 0 || (buflen & (ARMV7M_DCACHE_LINESIZE - 1)) != 0) { - /* The read buffer is not cache-line aligned. Read to an internal - * buffer instead. + /* The read buffer is not cache-line aligned, but will fit in + * the rxbuffer. So Read to an internalbuffer instead. */ up_invalidate_dcache((uintptr_t)priv->rxbuffer, diff --git a/arch/arm/src/kinetis/kinetis_lpserial.c b/arch/arm/src/kinetis/kinetis_lpserial.c index ad82d1054e2a3..d7ca5db9eba0a 100644 --- a/arch/arm/src/kinetis/kinetis_lpserial.c +++ b/arch/arm/src/kinetis/kinetis_lpserial.c @@ -705,10 +705,10 @@ static void kinetis_restoreuartint(struct kinetis_dev_s *priv, uint32_t ie) * ie */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); priv->ie = ie & LPUART_CTRL_ALL_INTS; kinetis_setuartint(priv); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -720,14 +720,14 @@ static void kinetis_disableuartint(struct kinetis_dev_s *priv, uint32_t *ie) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (ie) { *ie = priv->ie; } kinetis_restoreuartint(priv, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } #endif diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c index 38a39ab71f4dd..5b6f8f59a8f87 100644 --- a/arch/arm/src/kinetis/kinetis_serial.c +++ b/arch/arm/src/kinetis/kinetis_serial.c @@ -792,12 +792,12 @@ static void up_setuartint(struct up_dev_s *priv) * ie */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); regval = up_serialin(priv, KINETIS_UART_C2_OFFSET); regval &= ~UART_C2_ALLINTS; regval |= priv->ie; up_serialout(priv, KINETIS_UART_C2_OFFSET, regval); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -812,10 +812,10 @@ static void up_restoreuartint(struct up_dev_s *priv, uint8_t ie) * ie */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); priv->ie = ie & UART_C2_ALLINTS; up_setuartint(priv); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -827,14 +827,14 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *ie) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (ie) { *ie = priv->ie; } up_restoreuartint(priv, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } #endif diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c index f60a074651ce7..ccf5f1ba42746 100644 --- a/arch/arm/src/kinetis/kinetis_usbdev.c +++ b/arch/arm/src/kinetis/kinetis_usbdev.c @@ -3370,7 +3370,7 @@ static int khci_epconfigure(struct usbdev_ep_s *ep, uint32_t regval; uint8_t epno; bool epin; - bool bidi; + bool bidi = false; int index; #ifdef CONFIG_DEBUG_FEATURES diff --git a/arch/arm/src/kl/kl_serial.c b/arch/arm/src/kl/kl_serial.c index 94fd2d9f7aa72..4becc1e2c2ae5 100644 --- a/arch/arm/src/kl/kl_serial.c +++ b/arch/arm/src/kl/kl_serial.c @@ -328,12 +328,12 @@ static void up_setuartint(struct up_dev_s *priv) * in ie. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); regval = up_serialin(priv, KL_UART_C2_OFFSET); regval &= ~UART_C2_ALLINTS; regval |= priv->ie; up_serialout(priv, KL_UART_C2_OFFSET, regval); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -348,10 +348,10 @@ static void up_restoreuartint(struct up_dev_s *priv, uint8_t ie) * in ie. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); priv->ie = ie & UART_C2_ALLINTS; up_setuartint(priv); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -362,14 +362,14 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *ie) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (ie) { *ie = priv->ie; } up_restoreuartint(priv, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/arm/src/lc823450/lc823450_cpupause.c b/arch/arm/src/lc823450/lc823450_cpupause.c index d00c939ef2c91..fc5a246157b24 100644 --- a/arch/arm/src/lc823450/lc823450_cpupause.c +++ b/arch/arm/src/lc823450/lc823450_cpupause.c @@ -95,7 +95,7 @@ bool up_cpu_pausereq(int cpu) } /**************************************************************************** - * Name: up_cpu_paused + * Name: up_cpu_paused_save * * Description: * Handle a pause request from another CPU. Normally, this logic is @@ -104,16 +104,8 @@ bool up_cpu_pausereq(int cpu) * pause operation in other contexts where the interrupt cannot be taken * in order to avoid deadlocks. * - * This function performs the following operations: - * - * 1. It saves the current task state at the head of the current assigned - * task list. - * 2. It waits on a spinlock, then - * 3. Returns from interrupt, restoring the state of the new task at the - * head of the ready to run list. - * * Input Parameters: - * cpu - The index of the CPU to be paused + * None * * Returned Value: * On success, OK is returned. Otherwise, a negated errno value indicating @@ -121,7 +113,7 @@ bool up_cpu_pausereq(int cpu) * ****************************************************************************/ -int up_cpu_paused(int cpu) +int up_cpu_paused_save(void) { struct tcb_s *tcb = this_task(); @@ -141,6 +133,38 @@ int up_cpu_paused(int cpu) arm_savestate(tcb->xcp.regs); + return OK; +} + +/**************************************************************************** + * Name: up_cpu_paused + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. + * + * This function performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. + * + * Input Parameters: + * cpu - The index of the CPU to be paused + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused(int cpu) +{ /* Wait for the spinlock to be released */ spin_unlock(&g_cpu_paused[cpu]); @@ -151,11 +175,31 @@ int up_cpu_paused(int cpu) spin_lock(&g_cpu_wait[cpu]); - /* Restore the exception context of the tcb at the (new) head of the - * assigned task list. - */ + spin_unlock(&g_cpu_wait[cpu]); + spin_unlock(&g_cpu_resumed[cpu]); + + return OK; +} + +/**************************************************************************** + * Name: up_cpu_paused_restore + * + * Description: + * Restore the state of the CPU after it was paused via up_cpu_pause(), + * and resume normal tasking. + * + * Input Parameters: + * None + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ - tcb = this_task(); +int up_cpu_paused_restore(void) +{ + struct tcb_s *tcb = this_task(); #ifdef CONFIG_SCHED_INSTRUMENTATION /* Notify that we have resumed */ @@ -173,10 +217,6 @@ int up_cpu_paused(int cpu) arm_restorestate(tcb->xcp.regs); - spin_unlock(&g_cpu_wait[cpu]); - - spin_unlock(&g_cpu_resumed[cpu]); - return OK; } @@ -307,7 +347,7 @@ int up_cpu_pause(int cpu) * called. g_cpu_paused will be unlocked in any case. */ - return 0; + return OK; } /**************************************************************************** @@ -357,5 +397,5 @@ int up_cpu_resume(int cpu) spin_unlock(&g_cpu_resumed[cpu]); - return 0; + return OK; } diff --git a/arch/arm/src/lc823450/lc823450_gpio.c b/arch/arm/src/lc823450/lc823450_gpio.c index 3d95278d0576c..258815eca862b 100644 --- a/arch/arm/src/lc823450/lc823450_gpio.c +++ b/arch/arm/src/lc823450/lc823450_gpio.c @@ -372,7 +372,7 @@ void lc823450_gpio_write(uint16_t gpiocfg, bool value) #ifdef CONFIG_LC823450_VGPIO if (port == (GPIO_PORTV >> GPIO_PORT_SHIFT)) { - assert(pin < GPIO_VIRTUAL_NUM); + ASSERT(pin < GPIO_VIRTUAL_NUM); if (vgpio_ops[pin] && vgpio_ops[pin]->write) { vgpio_ops[pin]->write(pin, value); @@ -437,7 +437,7 @@ bool lc823450_gpio_read(uint16_t gpiocfg) #ifdef CONFIG_LC823450_VGPIO if (port == (GPIO_PORTV >> GPIO_PORT_SHIFT)) { - assert(pin < GPIO_VIRTUAL_NUM); + ASSERT(pin < GPIO_VIRTUAL_NUM); if (vgpio_ops[pin] && vgpio_ops[pin]->read) { return vgpio_ops[pin]->read(pin); @@ -506,7 +506,7 @@ int lc823450_gpio_initialize(void) #ifdef CONFIG_LC823450_VGPIO int lc823450_vgpio_register(unsigned int pin, struct vgpio_ops_s *ops) { - assert(pin < GPIO_VIRTUAL_NUM); + ASSERT(pin < GPIO_VIRTUAL_NUM); vgpio_ops[pin] = ops; return OK; } diff --git a/arch/arm/src/lc823450/lc823450_irq.c b/arch/arm/src/lc823450/lc823450_irq.c index c64e1a3a31974..817940308cc6f 100644 --- a/arch/arm/src/lc823450/lc823450_irq.c +++ b/arch/arm/src/lc823450/lc823450_irq.c @@ -820,23 +820,7 @@ int lc823450_irq_register(int irq, struct lc823450_irq_ops *ops) #endif /* CONFIG_LC823450_VIRQ */ /**************************************************************************** - * Name: arm_intstack_top - * - * Description: - * Return a pointer to the top the correct interrupt stack allocation - * for the current CPU. - * - ****************************************************************************/ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -uintptr_t arm_intstack_top(void) -{ - return g_cpu_intstack_top[up_cpu_index()]; -} -#endif - -/**************************************************************************** - * Name: arm_intstack_alloc + * Name: up_get_intstackbase * * Description: * Return a pointer to the "alloc" the correct interrupt stack allocation @@ -845,8 +829,8 @@ uintptr_t arm_intstack_top(void) ****************************************************************************/ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -uintptr_t arm_intstack_alloc(void) +uintptr_t up_get_intstackbase(int cpu) { - return g_cpu_intstack_top[up_cpu_index()] - INTSTACK_SIZE; + return g_cpu_intstack_top[cpu] - INTSTACK_SIZE; } #endif diff --git a/arch/arm/src/lc823450/lc823450_timer.c b/arch/arm/src/lc823450/lc823450_timer.c index 00b10c9f87269..bf98eee42ceae 100644 --- a/arch/arm/src/lc823450/lc823450_timer.c +++ b/arch/arm/src/lc823450/lc823450_timer.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/src/lc823450/lc823450_usbdev.c b/arch/arm/src/lc823450/lc823450_usbdev.c index f9b35ca7768e2..facacbc43cbc3 100644 --- a/arch/arm/src/lc823450/lc823450_usbdev.c +++ b/arch/arm/src/lc823450/lc823450_usbdev.c @@ -38,6 +38,7 @@ # include #endif +#include #include #include #include diff --git a/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c b/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c index 252c9c984844c..23eef26f95ab7 100644 --- a/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c +++ b/arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c @@ -227,6 +227,8 @@ static int lpc17_40_i2c_start(struct lpc17_40_i2cdev_s *priv) uint32_t timeout; int i; + nxsem_reset(&priv->wait, 0); + putreg32(I2C_CONCLR_STAC | I2C_CONCLR_SIC, priv->base + LPC17_40_I2C_CONCLR_OFFSET); putreg32(I2C_CONSET_STA, priv->base + LPC17_40_I2C_CONSET_OFFSET); diff --git a/arch/arm/src/lpc31xx/lpc31_allocateheap.c b/arch/arm/src/lpc31xx/lpc31_allocateheap.c index 11f7d9153096b..513eb92bfb1a8 100644 --- a/arch/arm/src/lpc31xx/lpc31_allocateheap.c +++ b/arch/arm/src/lpc31xx/lpc31_allocateheap.c @@ -37,7 +37,7 @@ #include "arm_internal.h" #include "lpc31_memorymap.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include # include "pg_macros.h" #endif @@ -134,7 +134,7 @@ * will let the heap run all the way to the end of SRAM. */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # ifdef PGTABLE_IN_HIGHSRAM # define LPC31_HEAP_VEND (PG_LOCKED_VBASE + PG_TOTAL_VSIZE - PGTABLE_SIZE) # else diff --git a/arch/arm/src/lpc31xx/lpc31_boot.c b/arch/arm/src/lpc31xx/lpc31_boot.c index 9618c2b381876..e7a4f3b0363be 100644 --- a/arch/arm/src/lpc31xx/lpc31_boot.c +++ b/arch/arm/src/lpc31xx/lpc31_boot.c @@ -29,7 +29,7 @@ #include "arm.h" #include "arm_internal.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include # include "pg_macros.h" #endif @@ -71,7 +71,7 @@ static const struct section_mapping_s g_section_mapping[] = { { LPC31_SHADOWSPACE_PSECTION, LPC31_SHADOWSPACE_VSECTION, LPC31_SHADOWSPACE_MMUFLAGS, LPC31_SHADOWSPACE_NSECTIONS}, -#ifndef CONFIG_PAGING /* SRAM is already fully mapped */ +#ifndef CONFIG_LEGACY_PAGING /* SRAM is already fully mapped */ { LPC31_INTSRAM_PSECTION, LPC31_INTSRAM_VSECTION, LPC31_INTSRAM_MMUFLAGS, LPC31_INTSRAM_NSECTIONS}, #endif @@ -188,7 +188,7 @@ static void up_setupmappings(void) * ****************************************************************************/ -#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING) +#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_LEGACY_PAGING) static void up_vectorpermissions(uint32_t mmuflags) { /* The PTE for the beginning of ISRAM is at the base of the L2 page table */ @@ -281,7 +281,7 @@ static void up_copyvectorblock(void) */ #if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && \ - defined(CONFIG_PAGING) + defined(CONFIG_LEGACY_PAGING) up_vectorpermissions(MMU_L2_VECTRWFLAGS); #endif @@ -306,7 +306,7 @@ static void up_copyvectorblock(void) /* Make the vectors read-only, cacheable again */ -#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING) +#if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_LEGACY_PAGING) up_vectorpermissions(MMU_L2_VECTROFLAGS); #endif diff --git a/arch/arm/src/lpc31xx/lpc31_memorymap.h b/arch/arm/src/lpc31xx/lpc31_memorymap.h index 53c95c5f02a94..c6a53e5bf85b8 100644 --- a/arch/arm/src/lpc31xx/lpc31_memorymap.h +++ b/arch/arm/src/lpc31xx/lpc31_memorymap.h @@ -28,6 +28,13 @@ #include #include "chip.h" +/* board_memorymap.h contains special mappings that are needed when a ROM + * memory map is used. It is included in this odd location because it + * depends on some the virtual address definitions provided above. + */ + +#include + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -185,13 +192,6 @@ #define LPC31_INTC_MMUFLAGS MMU_IOFLAGS #define LPC31_NAND_MMUFLAGS MMU_IOFLAGS -/* board_memorymap.h contains special mappings that are needed when a ROM - * memory map is used. It is included in this odd location because it - * depends on some the virtual address definitions provided above. - */ - -#include - /* LPC31XX Virtual (mapped) Memory Map. These are the mappings that will * be created if the page table lies in RAM. If the platform has another, * read-only, pre-initialized page table (perhaps in ROM), then the board.h @@ -243,7 +243,7 @@ #elif defined(CONFIG_BOOT_RUNFROMEXTSRAM) # define NUTTX_START_VADDR LPC31_EXTSRAM0_VADDR # define NUTTX_START_PADDR LPC31_EXTSRAM0_PADDR -#else /* CONFIG_BOOT_RUNFROMISRAM, CONFIG_PAGING */ +#else /* CONFIG_BOOT_RUNFROMISRAM, CONFIG_LEGACY_PAGING */ # define NUTTX_START_VADDR LPC31_INTSRAM0_VADDR # define NUTTX_START_PADDR LPC31_INTSRAM0_PADDR #endif @@ -277,18 +277,18 @@ # error "CONFIG_ARCH_ROMPGTABLE defined; PGTABLE_BASE_P/VADDR not defined" # else -/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory - * map probably do not apply because paging logic will probably partition - * the SRAM section differently. In particular, if the page table is located - * at the end of SRAM, then the virtual page table address defined below - * will probably be in error. +/* If CONFIG_LEGACY_PAGING is selected, then parts of the 1-to-1 virtual + * memory map probably do not apply because paging logic will probably + * partition the SRAM section differently. In particular, if the page + * table is located at the end of SRAM, then the virtual page table address + * defined below will probably be in error. * * We work around this header file interdependency by (1) insisting that * pg_macros.h be included AFTER this header file, then (2) allowing the * pg_macros.h header file to redefine PGTABLE_BASE_VADDR. */ -# if defined(CONFIG_PAGING) && defined(__ARCH_ARM_SRC_ARM_PG_MACROS_H) +# if defined(CONFIG_LEGACY_PAGING) && defined(__ARCH_ARM_SRC_ARM_PG_MACROS_H) # error "pg_macros.h must be included AFTER this header file" # endif @@ -312,11 +312,11 @@ # endif # define PGTABLE_IN_HIGHSRAM 1 -/* If CONFIG_PAGING is defined, insist that pg_macros.h assign the virtual +/* If CONFIG_LEGACY_PAGING is defined, insist that pg_macros.h assign the * address of the page table. */ -# ifdef CONFIG_PAGING +# ifdef CONFIG_LEGACY_PAGING # undef PGTABLE_BASE_VADDR # endif # else @@ -341,8 +341,8 @@ * (for normal operation). We will reuse this memory for coarse page tables * as follows: * - * NOTE: If CONFIG_PAGING is defined, pg_macros.h will re-assign the virtual - * address of the page table. + * NOTE: If CONFIG_LEGACY_PAGING is defined, pg_macros.h will re-assign the + * virtual address of the page table. */ #define PGTABLE_L2_COARSE_OFFSET ((((LPC31_LAST_PSECTION >> 20) + 255) & ~255) << 2) diff --git a/arch/arm/src/lpc54xx/lpc54_lowputc.c b/arch/arm/src/lpc54xx/lpc54_lowputc.c index c859665d7e7d8..4360c91b031fb 100644 --- a/arch/arm/src/lpc54xx/lpc54_lowputc.c +++ b/arch/arm/src/lpc54xx/lpc54_lowputc.c @@ -63,6 +63,8 @@ #include +#include + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -797,18 +799,18 @@ void arm_lowputc(char ch) * atomic. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if ((getreg32(CONSOLE_BASE + LPC54_USART_FIFOSTAT_OFFSET) & USART_FIFOSTAT_TXNOTFULL) != 0) { /* Send the character */ putreg32((uint32_t)ch, CONSOLE_BASE + LPC54_USART_FIFOWR_OFFSET); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); return; } - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } #endif } diff --git a/arch/arm/src/lpc54xx/lpc54_serial.c b/arch/arm/src/lpc54xx/lpc54_serial.c index cfaa94e40fb64..4d62be6222440 100644 --- a/arch/arm/src/lpc54xx/lpc54_serial.c +++ b/arch/arm/src/lpc54xx/lpc54_serial.c @@ -922,14 +922,14 @@ static void lpc54_fifoint_disableall(struct lpc54_dev_s *priv, { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (intset) { *intset = lpc54_serialin(priv, LPC54_USART_FIFOINTENCLR_OFFSET); } lpc54_serialout(priv, LPC54_USART_FIFOINTENCLR_OFFSET, USART_FIFOINT_ALL); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/arm/src/mps/Kconfig b/arch/arm/src/mps/Kconfig new file mode 100644 index 0000000000000..65ebd3ff892ae --- /dev/null +++ b/arch/arm/src/mps/Kconfig @@ -0,0 +1,26 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_MPS + +menu "MPS Chip Selection" + +choice + prompt "ARM MPS Configuration" + default ARCH_CHIP_MPS3_AN547 + +config ARCH_CHIP_MPS3_AN547 + bool "MPS3 AN547 Processor Cortexm55" + select ARCH_CORTEXM55 + +config ARCH_CHIP_MPS3_AN524 + bool "MPS3 AN524 Processor Cortexm33" + select ARCH_CORTEXM33 + +endchoice + +endmenu + +endif diff --git a/arch/arm/src/mps/Make.defs b/arch/arm/src/mps/Make.defs new file mode 100644 index 0000000000000..8d3eabdc7914a --- /dev/null +++ b/arch/arm/src/mps/Make.defs @@ -0,0 +1,23 @@ +############################################################################ +# arch/arm/src/mps/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include armv8-m/Make.defs + +CHIP_CSRCS = mps_start.c mps_serial.c mps_irq.c mps_timer.c mps_allocateheap.c diff --git a/arch/arm/src/mps/chip.h b/arch/arm/src/mps/chip.h new file mode 100644 index 0000000000000..c879ffcff8338 --- /dev/null +++ b/arch/arm/src/mps/chip.h @@ -0,0 +1,37 @@ +/**************************************************************************** + * arch/arm/src/mps/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MPS_CHIP_H +#define __ARCH_ARM_SRC_MPS_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ARMV8M_PERIPHERAL_INTERRUPTS NR_IRQS + +#endif /* __ARCH_ARM_SRC_MPS_CHIP_H */ diff --git a/arch/arm/src/mps/mps_allocateheap.c b/arch/arm/src/mps/mps_allocateheap.c new file mode 100644 index 0000000000000..3fd7bc97feeef --- /dev/null +++ b/arch/arm/src/mps/mps_allocateheap.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * arch/arm/src/mps/mps_allocateheap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_BUILD_KERNEL) +# define MM_ADDREGION kmm_addregion +#else +# define MM_ADDREGION umm_addregion +#endif + +#define MPS3_DDR_BASE (void *)0x60000000 +#define MPS3_DDR_SIZE (2 * 1024 * 1024 * 1024UL) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_addregion + ****************************************************************************/ + +#if CONFIG_MM_REGIONS > 1 +void arm_addregion(void) +{ + MM_ADDREGION(MPS3_DDR_BASE, MPS3_DDR_SIZE); +} +#endif diff --git a/arch/arm/src/mps/mps_irq.c b/arch/arm/src/mps/mps_irq.c new file mode 100644 index 0000000000000..6e9af56347d73 --- /dev/null +++ b/arch/arm/src/mps/mps_irq.c @@ -0,0 +1,340 @@ +/**************************************************************************** + * arch/arm/src/mps/mps_irq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "arm_internal.h" +#include "mps_irq.h" +#include "nvic.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NVIC_ENA_OFFSET (0) +#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE) + +#define DEFPRIORITY32 (NVIC_SYSH_PRIORITY_DEFAULT << 24 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 16 | \ + NVIC_SYSH_PRIORITY_DEFAULT << 8 | \ + NVIC_SYSH_PRIORITY_DEFAULT) + +/* Size of the interrupt stack allocation */ + +#define INTSTACK_ALLOC (CONFIG_SMP_NCPUS * INTSTACK_SIZE) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +static int mps_nmi(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! NMI received\n"); + PANIC(); + return 0; +} + +static int mps_pendsv(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! PendSV received\n"); + PANIC(); + return 0; +} + +static int mps_reserved(int irq, void *context, void *arg) +{ + up_irq_save(); + _err("PANIC!!! Reserved interrupt\n"); + PANIC(); + return 0; +} +#endif + +/**************************************************************************** + * Name: mps_prioritize_syscall + * + * Description: + * Set the priority of an exception. This function may be needed + * internally even if support for prioritized interrupts is not enabled. + * + ****************************************************************************/ + +#ifdef CONFIG_ARMV8M_USEBASEPRI +static inline void mps_prioritize_syscall(int priority) +{ + uint32_t regval; + + /* SVCALL is system handler 11 */ + + regval = getreg32(NVIC_SYSH8_11_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK; + regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT); + putreg32(regval, NVIC_SYSH8_11_PRIORITY); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + * + * Description: + * This function is called by up_initialize() during the bring-up of the + * system. It is the responsibility of this function to but the interrupt + * subsystem into the working and ready state. + * + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uint32_t regaddr; + int num_priority_registers; + int i; + + /* Disable all interrupts */ + + for (i = 0; i < NR_IRQS - MPS_IRQ_FIRST; i += 32) + { + putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); + } + + putreg32((uint32_t)_vectors, NVIC_VECTAB); + +#ifdef CONFIG_ARCH_RAMVECTORS + /* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based + * vector table that requires special initialization. + */ + + up_ramvec_initialize(); +#endif + + /* Set all interrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); + + /* The NVIC ICTR register (bits 0-4) holds the number of of interrupt + * lines that the NVIC supports: + * + * 0 -> 32 interrupt lines, 8 priority registers + * 1 -> 64 " " " ", 16 priority registers + * 2 -> 96 " " " ", 32 priority registers + * ... + */ + + num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8; + + /* Now set all of the interrupt lines to the default priority */ + + regaddr = NVIC_IRQ0_3_PRIORITY; + while (num_priority_registers--) + { + putreg32(DEFPRIORITY32, regaddr); + regaddr += 4; + } + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(MPS_IRQ_SVCALL, arm_svcall, NULL); + irq_attach(MPS_IRQ_HARDFAULT, arm_hardfault, NULL); + + /* Set the priority of the SVCall interrupt */ + +#ifdef CONFIG_ARCH_IRQPRIO + + /* up_prioritize_irq(MPS_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ + +#endif +#ifdef CONFIG_ARMV8M_USEBASEPRI + mps_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY); +#endif + + /* If the MPU is enabled, then attach and enable the Memory Management + * Fault handler. + */ + +#ifdef CONFIG_ARM_MPU + irq_attach(MPS_IRQ_MEMFAULT, arm_memfault, NULL); + up_enable_irq(MPS_IRQ_MEMFAULT); +#endif + + /* Attach all other processor exceptions (except reset and sys tick) */ + +#ifdef CONFIG_DEBUG_FEATURES + irq_attach(MPS_IRQ_NMI, mps_nmi, NULL); +#ifndef CONFIG_ARM_MPU + irq_attach(MPS_IRQ_MEMFAULT, arm_memfault, NULL); +#endif + irq_attach(MPS_IRQ_BUSFAULT, arm_busfault, NULL); + irq_attach(MPS_IRQ_USAGEFAULT, arm_usagefault, NULL); + irq_attach(MPS_IRQ_PENDSV, mps_pendsv, NULL); + arm_enable_dbgmonitor(); + irq_attach(MPS_IRQ_DBGMONITOR, arm_dbgmonitor, NULL); + irq_attach(MPS_IRQ_RESERVED, mps_reserved, NULL); +#endif + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + + /* And finally, enable interrupts */ + + up_irq_enable(); +#endif +} + +static int mps_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, + uintptr_t offset) +{ + int n; + + DEBUGASSERT(irq >= MPS_IRQ_NMI && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= MPS_IRQ_FIRST) + { + n = irq - MPS_IRQ_FIRST; + *regaddr = NVIC_IRQ_ENABLE(n) + offset; + *bit = (uint32_t)0x1 << (n & 0x1f); + } + + /* Handle processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == MPS_IRQ_MEMFAULT) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + else if (irq == MPS_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + else if (irq == MPS_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + else if (irq == MPS_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_ENABLE; + } + else + { + return -EINVAL; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (mps_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to disable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Clear Enable register. For other exceptions, we need to + * clear the bit in the System Handler Control and State Register. + */ + + if (irq >= MPS_IRQ_FIRST) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval &= ~bit; + putreg32(regval, regaddr); + } + } +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + uint32_t bit; + + if (mps_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0) + { + /* Modify the appropriate bit in the register to enable the interrupt. + * For normal interrupts, we need to set the bit in the associated + * Interrupt Set Enable register. For other exceptions, we need to + * set the bit in the System Handler Control and State Register. + */ + + if (irq >= MPS_IRQ_FIRST) + { + putreg32(bit, regaddr); + } + else + { + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } + } +} + +/**************************************************************************** + * Name: arm_ack_irq + ****************************************************************************/ + +void arm_ack_irq(int irq) +{ +} diff --git a/arch/arm/src/mps/mps_irq.h b/arch/arm/src/mps/mps_irq.h new file mode 100644 index 0000000000000..26d5e9c8f76af --- /dev/null +++ b/arch/arm/src/mps/mps_irq.h @@ -0,0 +1,72 @@ +/**************************************************************************** + * arch/arm/src/mps/mps_irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MPS_MPS_IRQ_H +#define __ARCH_ARM_SRC_MPS_MPS_IRQ_H + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/* IRQ numbers. + * The IRQ number corresponds vector number and hence map directly to bits + * in the NVIC. This does, however, waste several words of memory in the + * IRQ to handle mapping tables. + */ + +/* Processor Exceptions (vectors 0-15) */ + +#define MPS_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */ + /* Vector 0: Reset stack pointer value */ + /* Vector 1: Reset (not handler as an IRQ) */ +#define MPS_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */ +#define MPS_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */ +#define MPS_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */ +#define MPS_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */ +#define MPS_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */ + /* Vectors 7-10: Reserved */ +#define MPS_IRQ_SVCALL (11) /* Vector 11: SVC call */ +#define MPS_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */ + /* Vector 13: Reserved */ +#define MPS_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */ +#define MPS_IRQ_SYSTICK (15) /* Vector 15: System tick */ + +#define MPS_IRQ_FIRST (16) /* Vector number of the first external interrupt */ + +#define NVIC_SYSH_PRIORITY_DEFAULT (0x80) /* Midpoint is the default */ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_MPS_MPS_IRQ_H */ diff --git a/arch/arm/src/mps/mps_serial.c b/arch/arm/src/mps/mps_serial.c new file mode 100644 index 0000000000000..3df89e3f2cca3 --- /dev/null +++ b/arch/arm/src/mps/mps_serial.c @@ -0,0 +1,63 @@ +/*************************************************************************** + * arch/arm/src/mps/mps_serial.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ***************************************************************************/ + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#include + +#include "arm_internal.h" + +/*************************************************************************** + * Public Functions + ***************************************************************************/ + +/*************************************************************************** + * Name: arm_serialinit + * + * Description: + * Register serial console and serial ports. This assumes that + * arm_earlyserialinit was called previously. + * + ***************************************************************************/ + +void arm_serialinit(void) +{ + cmsdk_serialinit(); +} + +#if USE_EARLYSERIALINIT + +/*************************************************************************** + * Name: arm_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before arm_serialinit. + * + ***************************************************************************/ + +void arm_earlyserialinit(void) +{ + cmsdk_earlyserialinit(); +} +#endif diff --git a/arch/arm/src/mps/mps_start.c b/arch/arm/src/mps/mps_start.c new file mode 100644 index 0000000000000..d015f72cdb80b --- /dev/null +++ b/arch/arm/src/mps/mps_start.c @@ -0,0 +1,97 @@ +/**************************************************************************** + * arch/arm/src/mps/mps_start.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "arm_internal.h" +#include "mps_irq.h" +#include "mpu.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_idle_topstack: _sbss is the start of the BSS region as defined by the + * linker script. _ebss lies at the end of the BSS region. The idle task + * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. + * The IDLE thread is the thread that the system boots on and, eventually, + * becomes the IDLE, do nothing task that runs only when there is nothing + * else to run. The heap continues from there until the end of memory. + * g_idle_topstack is a read-only variable the provides this computed + * address. + */ + +const uintptr_t g_idle_topstack = HEAP_BASE; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __start + * + * Description: + * This is the reset entry point. + * + ****************************************************************************/ + +void __start(void) +{ + const uint32_t *src; + uint32_t *dest; + + /* If enabled reset the MPU */ + + mpu_early_reset(); + arm_fpuconfig(); + + /* Set bss to zero */ + + for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; ) + { + *dest++ = 0; + } + + /* Copy the program from FLASH to RAM. */ + + for (src = (const uint32_t *)_eronly, + dest = (uint32_t *)_sdata; dest < (uint32_t *)_edata; + ) + { + *dest++ = *src++; + } + +#ifdef USE_EARLYSERIALINIT + arm_earlyserialinit(); +#endif + + nx_start(); +} diff --git a/arch/arm/src/mps/mps_timer.c b/arch/arm/src/mps/mps_timer.c new file mode 100644 index 0000000000000..7a01be36ee58e --- /dev/null +++ b/arch/arm/src/mps/mps_timer.c @@ -0,0 +1,56 @@ +/**************************************************************************** + * arch/arm/src/mps/mps_timer.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "arm_internal.h" +#include "systick.h" +#include "mps_irq.h" +#include "nvic.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#define SYSTICK_RELOAD ((MPS_SYSTICK_CLOCK / CLK_TCK) - 1) + +/**************************************************************************** + * Function: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer hardware. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + /* Set reload register, qemu maybe have a bug, + * if RELOAD is zero, set CTRL is not useful + */ + + putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); + up_timer_set_lowerhalf(systick_initialize(true, MPS_SYSTICK_CLOCK, -1)); +} diff --git a/arch/arm/src/mx8mp/Kconfig b/arch/arm/src/mx8mp/Kconfig index 91213bb7cf387..bf0524a1edd5f 100644 --- a/arch/arm/src/mx8mp/Kconfig +++ b/arch/arm/src/mx8mp/Kconfig @@ -123,6 +123,14 @@ config MX8MP_SPI_DRIVER endif # MX8MP_SPI +config MX8MP_RPMSG + bool "RPMSG support" + default y + depends on DEV_RPMSG + ---help--- + Enable RPMSG shared memory and behave as a client device that can be + accessed by the IMX8MP A53 core running Linux IMX. + endmenu # i.MX8MP Peripheral Selection # These "hidden" settings determine whether a peripheral option is available diff --git a/arch/arm/src/mx8mp/Make.defs b/arch/arm/src/mx8mp/Make.defs index dea1edf49d82b..6d7ee57411066 100644 --- a/arch/arm/src/mx8mp/Make.defs +++ b/arch/arm/src/mx8mp/Make.defs @@ -43,3 +43,7 @@ endif ifeq ($(CONFIG_SPI),y) CHIP_CSRCS += mx8mp_ecspi.c endif + +ifeq ($(CONFIG_MX8MP_RPMSG),y) +CHIP_CSRCS += mx8mp_rptun.c mx8mp_ipc.c mx8mp_rsctable.c +endif diff --git a/arch/arm/src/mx8mp/hardware/mx8mp_memorymap.h b/arch/arm/src/mx8mp/hardware/mx8mp_memorymap.h index 8a8ce40475acc..8f14dfc6216a4 100644 --- a/arch/arm/src/mx8mp/hardware/mx8mp_memorymap.h +++ b/arch/arm/src/mx8mp/hardware/mx8mp_memorymap.h @@ -105,6 +105,8 @@ #define MX8M_ECSPI2 0x30830000u #define MX8M_ECSPI3 0x30840000u +#define MX8M_MUB 0x30AB0000u + #define MX8M_GPIO 0x30200000u #define MX8M_GPIO1 (MX8M_GPIO + 0x10000 * 0) #define MX8M_GPIO2 (MX8M_GPIO + 0x10000 * 1) diff --git a/arch/arm/src/mx8mp/hardware/mx8mp_mu.h b/arch/arm/src/mx8mp/hardware/mx8mp_mu.h new file mode 100644 index 0000000000000..f1344080cd266 --- /dev/null +++ b/arch/arm/src/mx8mp/hardware/mx8mp_mu.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/hardware/mx8mp_mu.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_MU_H +#define __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_MU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Messaging Unit Register Offsets ******************************************/ + +#define MU_TR_OFFSET 0x0000 +#define MU_RR_OFFSET 0x0010 +#define MU_SR_OFFSET 0x0020 +#define MU_CR_OFFSET 0x0024 + +/* Messaging Unit Register Bit Definitions **********************************/ + +#define MU_SR_RF0_SHIFT 27 +#define MU_SR_RF1_SHIFT 26 +#define MU_SR_RF2_SHIFT 25 +#define MU_SR_RF3_SHIFT 24 +#define MU_SR_TE0_SHIFT 23 +#define MU_SR_TE1_SHIFT 22 +#define MU_SR_TE2_SHIFT 21 +#define MU_SR_TE3_SHIFT 20 + +#define MU_CR_GIE_MASK 0xf0000000U +#define MU_CR_RIE_MASK 0x0f000000U +#define MU_CR_TIE_MASK 0x00f00000U +#define MU_CR_GIR_MASK 0x000f0000U +#define MU_CR_RIE0_SHIFT 27 +#define MU_CR_RIE1_SHIFT 26 +#define MU_CR_RIE2_SHIFT 25 +#define MU_CR_RIE3_SHIFT 24 + +#endif /* __ARCH_ARM_SRC_MX8MP_HARDWARE_MX8MP_I2C_H */ diff --git a/arch/arm/src/mx8mp/mx8mp_clockconfig.c b/arch/arm/src/mx8mp/mx8mp_clockconfig.c index 1198bd00c1106..e7a397d39c0cd 100644 --- a/arch/arm/src/mx8mp/mx8mp_clockconfig.c +++ b/arch/arm/src/mx8mp/mx8mp_clockconfig.c @@ -92,6 +92,8 @@ void mx8mp_clockconfig(void) mx8mp_ccm_gate_clock(CCM_SIM_WAKEUP_CLK_GATE, CLK_ALWAYS_NEEDED); mx8mp_ccm_gate_clock(CCM_DEBUG_CLK_GATE, CLK_ALWAYS_NEEDED); mx8mp_ccm_gate_clock(CCM_SEC_DEBUG_CLK_GATE, CLK_ALWAYS_NEEDED); + mx8mp_ccm_gate_clock(CCM_UART4_CLK_GATE, CLK_ALWAYS_NEEDED); + mx8mp_ccm_gate_clock(CCM_MU_CLK_GATE, CLK_ALWAYS_NEEDED); /* Make sure that main buses are enabled (TODO to be tuned or adjust * by configuration) diff --git a/arch/arm/src/mx8mp/mx8mp_ecspi.c b/arch/arm/src/mx8mp/mx8mp_ecspi.c index 83dd60e341424..d1d812f39a9ad 100644 --- a/arch/arm/src/mx8mp/mx8mp_ecspi.c +++ b/arch/arm/src/mx8mp/mx8mp_ecspi.c @@ -229,9 +229,9 @@ static void mx8mp_spi_enable(struct mx8mp_spi_s *priv) * ******************************************************************************/ -static inline int mx8mp_spi_wait_irq(struct mx8mp_spi_s *priv, int usec) +static inline int mx8mp_spi_wait_irq(struct mx8mp_spi_s *priv, int nsec) { - return nxsem_tickwait(&priv->wait, USEC2TICK(usec)); + return nxsem_tickwait(&priv->wait, NSEC2TICK(nsec)); } /****************************************************************************** @@ -245,6 +245,7 @@ static inline int mx8mp_spi_wait_irq(struct mx8mp_spi_s *priv, int usec) static int mx8mp_spi_interrupt(int irq, void *context, void *arg) { struct mx8mp_spi_s *priv = (struct mx8mp_spi_s *)arg; + putreg32(0, priv->base + INTREG_OFFSET); nxsem_post(&priv->wait); return 0; @@ -271,9 +272,13 @@ static int mx8mp_spi_transfer(struct mx8mp_spi_s *priv, /* WARNING: SPI FIFO works on 32 bits data only */ - /* 1. clear IRQs */ + /* 1. clear and enable IRQs */ - modreg32(0, STATREG_TC | STATREG_RO, priv->base + STATREG_OFFSET); + putreg32(INTREG_RDREN, priv->base + INTREG_OFFSET); + + modreg32(STATREG_TC | STATREG_RO, + STATREG_TC | STATREG_RO, + priv->base + STATREG_OFFSET); /* 2. compute words to process */ @@ -444,7 +449,7 @@ static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) /* Store byte duration to adapt irq waiting time */ - priv->byte_duration = (USEC_PER_SEC / priv->actual) * 8; + priv->byte_duration = (NSEC_PER_SEC / priv->actual) * 8; return priv->actual; } diff --git a/arch/arm/src/mx8mp/mx8mp_ipc.c b/arch/arm/src/mx8mp/mx8mp_ipc.c new file mode 100644 index 0000000000000..f66c2b0c22058 --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_ipc.c @@ -0,0 +1,216 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_ipc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "mx8mp_ipc.h" + +#include +#include +#include +#include +#include + +#include "arm_internal.h" +#include "hardware/mx8mp_mu.h" +#include "hardware/mx8mp_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MX8MP_IPC_CHANS 8 +#define RPMSG_MU_CHANNEL 1 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* IPC receive channel configuration */ + +struct mx8mp_ipc_recv_s +{ + ipc_callback_t callback; + void *args; +}; + +/* IPC device */ + +struct mx8mp_ipc_s +{ + struct mx8mp_ipc_recv_s recv[MX8MP_IPC_CHANS]; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct mx8mp_ipc_s g_mx8mp_ipc; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_ipc_disable_all_interrupts + ****************************************************************************/ + +static void mx8mp_ipc_disable_all_interrupts(void) +{ + uint32_t reg = getreg32(MX8M_MUB + MU_CR_OFFSET); + putreg32(reg & ~(MU_CR_GIE_MASK | MU_CR_RIE_MASK | MU_CR_TIE_MASK), + MX8M_MUB + MU_CR_OFFSET); +} + +/**************************************************************************** + * Name: mx8mp_ipc_mu_enable_interrupt + ****************************************************************************/ + +static void mx8mp_ipc_mu_enable_interrupt(uint32_t index) +{ + uint32_t reg = getreg32(MX8M_MUB + MU_CR_OFFSET); + + /* GIR bits must be masked! */ + + putreg32((reg & ~MU_CR_GIR_MASK) | (1UL << MU_CR_RIE0_SHIFT) >> index, + MX8M_MUB + MU_CR_OFFSET); +} + +/**************************************************************************** + * Name: mx8mp_ipc_mu_data_ready + ****************************************************************************/ + +static bool mx8mp_ipc_mu_data_ready(int id) +{ + return (((1UL << MU_SR_RF0_SHIFT) >> id) + & getreg32(MX8M_MUB + MU_SR_OFFSET)) != 0UL; +} + +/**************************************************************************** + * Name: mx8mp_ipc_mu_tx_empty + ****************************************************************************/ + +static bool mx8mp_ipc_mu_tx_empty(int index) +{ + return (getreg32(MX8M_MUB + MU_SR_OFFSET) + & ((1UL << MU_SR_TE0_SHIFT) >> index)) != 0UL; +} + +/**************************************************************************** + * Name: mx8mp_ipc_mu_send_msg + ****************************************************************************/ + +static void mx8mp_ipc_mu_send_msg(uint32_t index, uint32_t msg) +{ + putreg32(msg, MX8M_MUB + MU_TR_OFFSET + (index * sizeof(uint32_t))); +} + +/**************************************************************************** + * Name: mx8mp_ipc_interrupt + ****************************************************************************/ + +static int mx8mp_ipc_interrupt(int irq, void *context, void *args) +{ + struct mx8mp_ipc_s *dev = args; + if (!mx8mp_ipc_mu_data_ready(RPMSG_MU_CHANNEL)) + { + return 0; + } + + uint32_t channel = getreg32(MX8M_MUB + MU_RR_OFFSET + + (RPMSG_MU_CHANNEL * sizeof(uint32_t))) + >> 16; + if (channel >= MX8MP_IPC_CHANS) + { + return 0; + } + + if (dev->recv[channel].callback) + { + dev->recv[channel].callback(channel, dev->recv[channel].args); + } + + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_ipc_subscribe + ****************************************************************************/ + +void mx8mp_ipc_subscribe(int id, ipc_callback_t callback, void *args) +{ + struct mx8mp_ipc_s *dev = &g_mx8mp_ipc; + + DEBUGASSERT(id < MX8MP_IPC_CHANS); + + ipcinfo("IPC subscribe %d\n", id); + + /* Register callback */ + + dev->recv[id].callback = callback; + dev->recv[id].args = args; +} + +/**************************************************************************** + * Name: mx8mp_ipc_signal + ****************************************************************************/ + +void mx8mp_ipc_signal(int id) +{ + DEBUGASSERT(id < MX8MP_IPC_CHANS); + + ipcinfo("IPC signal %d\n", id); + + /* Wait TX register to be empty. */ + + while (!mx8mp_ipc_mu_tx_empty(id)) + { + } + + mx8mp_ipc_mu_send_msg(1, id); +} + +/**************************************************************************** + * Name: mx8mp_ipc_init + ****************************************************************************/ + +void mx8mp_ipc_init(void) +{ + struct mx8mp_ipc_s *dev = &g_mx8mp_ipc; + + /* Reset device */ + + memset(dev, 0, sizeof(struct mx8mp_ipc_s)); + + mx8mp_ipc_disable_all_interrupts(); + + /* Attach and enable the IRQ */ + + irq_attach(MX8MP_IRQ_MU1_M7, mx8mp_ipc_interrupt, dev); + up_enable_irq(MX8MP_IRQ_MU1_M7); + + mx8mp_ipc_mu_enable_interrupt(RPMSG_MU_CHANNEL); +} diff --git a/arch/arm/src/mx8mp/mx8mp_ipc.h b/arch/arm/src/mx8mp/mx8mp_ipc.h new file mode 100644 index 0000000000000..f033beb245dfe --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_ipc.h @@ -0,0 +1,45 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_ipc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MX8MP_MX8MP_IPC_H +#define __ARCH_ARM_SRC_MX8MP_MX8MP_IPC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef void (*ipc_callback_t)(int id, void *arg); + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +void mx8mp_ipc_subscribe(int id, ipc_callback_t callback, void *args); +void mx8mp_ipc_signal(int id); +void mx8mp_ipc_init(void); +void mx8mp_ipc_enable(void); + +#endif /* __ARCH_ARM_SRC_MX8MP_MX8MP_IPC_H */ diff --git a/arch/arm/src/mx8mp/mx8mp_rptun.c b/arch/arm/src/mx8mp/mx8mp_rptun.c new file mode 100644 index 0000000000000..2fdcd2c1ed047 --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_rptun.c @@ -0,0 +1,297 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_rptun.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "mx8mp_rptun.h" +#include "mx8mp_ipc.h" +#include "mx8mp_rsctable.h" +#include + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Vring configuration parameters */ + +#define VRING_SHMEM (0x550FF000) /* Vring shared memory start */ + +/* IPC configuration */ + +#define RPTUN_IPC_CHAN_MASTER_RX (0) /* RX for master is ready */ +#define RPTUN_IPC_CHAN_SLAVE_RX (1) /* RX for slave is ready */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* MX8MP rptun sharred memory */ + +struct mx8mp_rptun_shmem_s +{ + struct rptun_rsc_s rsc; +}; + +/* MX8MP rptun device */ + +struct mx8mp_rptun_dev_s +{ + struct rptun_dev_s rptun; + rptun_callback_t callback; + void *arg; + struct mx8mp_rptun_shmem_s *shmem; + char cpuname[RPMSG_NAME_SIZE + 1]; + char shmemname[RPMSG_NAME_SIZE + 1]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static const char *mx8mp_rptun_get_cpuname(struct rptun_dev_s *dev); +static const char *mx8mp_rptun_get_firmware(struct rptun_dev_s *dev); +static const struct rptun_addrenv_s * +mx8mp_rptun_get_addrenv(struct rptun_dev_s *dev); +static struct rptun_rsc_s * +mx8mp_rptun_get_resource(struct rptun_dev_s *dev); +static bool mx8mp_rptun_is_autostart(struct rptun_dev_s *dev); +static bool mx8mp_rptun_is_master(struct rptun_dev_s *dev); +static int mx8mp_rptun_start(struct rptun_dev_s *dev); +static int mx8mp_rptun_stop(struct rptun_dev_s *dev); +static int mx8mp_rptun_notify(struct rptun_dev_s *dev, uint32_t vqid); +static int mx8mp_rptun_register_callback(struct rptun_dev_s *dev, + rptun_callback_t callback, + void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct rptun_ops_s g_mx8mp_rptun_ops = +{ + .get_cpuname = mx8mp_rptun_get_cpuname, + .get_firmware = mx8mp_rptun_get_firmware, + .get_addrenv = mx8mp_rptun_get_addrenv, + .get_resource = mx8mp_rptun_get_resource, + .is_autostart = mx8mp_rptun_is_autostart, + .is_master = mx8mp_rptun_is_master, + .start = mx8mp_rptun_start, + .stop = mx8mp_rptun_stop, + .notify = mx8mp_rptun_notify, + .register_callback = mx8mp_rptun_register_callback, +}; + +struct mx8mp_rptun_dev_s g_rptun_dev; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_rptun_get_cpuname + ****************************************************************************/ + +static const char *mx8mp_rptun_get_cpuname(struct rptun_dev_s *dev) +{ + struct mx8mp_rptun_dev_s *priv = container_of(dev, + struct mx8mp_rptun_dev_s, rptun); + + return priv->cpuname; +} + +/**************************************************************************** + * Name: mx8mp_rptun_get_firmware + ****************************************************************************/ + +static const char *mx8mp_rptun_get_firmware(struct rptun_dev_s *dev) +{ + return NULL; +} + +/**************************************************************************** + * Name: mx8mp_rptun_get_addrenv + ****************************************************************************/ + +static const struct rptun_addrenv_s * +mx8mp_rptun_get_addrenv(struct rptun_dev_s *dev) +{ + return NULL; +} + +/**************************************************************************** + * Name: mx8mp_rptun_get_resource + ****************************************************************************/ + +static struct rptun_rsc_s *mx8mp_rptun_get_resource(struct rptun_dev_s *dev) +{ + struct mx8mp_rptun_dev_s *priv + = container_of(dev, struct mx8mp_rptun_dev_s, rptun); + + if (priv->shmem != NULL) + { + return &priv->shmem->rsc; + } + + priv->shmem = (struct mx8mp_rptun_shmem_s *)VRING_SHMEM; + if (priv->shmem->rsc.rsc_tbl_hdr.offset + != g_mx8mp_rsc_table.rsc_tbl_hdr.offset) + { + mx8mp_copy_rsc_table(); + } + + return &priv->shmem->rsc; +} + +/**************************************************************************** + * Name: mx8mp_rptun_is_autostart + ****************************************************************************/ + +static bool mx8mp_rptun_is_autostart(struct rptun_dev_s *dev) +{ + return true; +} + +/**************************************************************************** + * Name: mx8mp_rptun_is_master + ****************************************************************************/ + +static bool mx8mp_rptun_is_master(struct rptun_dev_s *dev) +{ + return false; +} + +/**************************************************************************** + * Name: mx8mp_rptun_start + ****************************************************************************/ + +static int mx8mp_rptun_start(struct rptun_dev_s *dev) +{ + return 0; +} + +/**************************************************************************** + * Name: mx8mp_rptun_stop + ****************************************************************************/ + +static int mx8mp_rptun_stop(struct rptun_dev_s *dev) +{ + return 0; +} + +/**************************************************************************** + * Name: mx8mp_rptun_notify + ****************************************************************************/ + +static int mx8mp_rptun_notify(struct rptun_dev_s *dev, uint32_t vqid) +{ + mx8mp_ipc_signal(RPTUN_IPC_CHAN_MASTER_RX); + + return 0; +} + +/**************************************************************************** + * Name: mx8mp_rptun_register_callback + ****************************************************************************/ + +static int mx8mp_rptun_register_callback(struct rptun_dev_s *dev, + rptun_callback_t callback, + void *arg) +{ + struct mx8mp_rptun_dev_s *priv = container_of(dev, + struct mx8mp_rptun_dev_s, rptun); + + priv->callback = callback; + priv->arg = arg; + + return 0; +} + +/**************************************************************************** + * Name: mx8mp_ipc_slave_callback + ****************************************************************************/ + +static void mx8mp_ipc_callback(int id, void *arg) +{ + ipcinfo("Rptun IPC interrupt %d\n", id); + if (id == RPTUN_IPC_CHAN_SLAVE_RX) + { + struct mx8mp_rptun_dev_s *dev = &g_rptun_dev; + + up_invalidate_dcache(0x55000000, 0x55010000); + up_invalidate_dcache(0x55400000, 0x55500000); + if (dev->callback != NULL) + { + dev->callback(dev->arg, RPTUN_NOTIFY_ALL); + } + } + else + { + DEBUGASSERT(0); + } + + __asm volatile("dsb 0xF" ::: "memory"); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int mx8mp_rptun_init(const char *shmemname, const char *cpuname) +{ + struct mx8mp_rptun_dev_s *dev = &g_rptun_dev; + int ret = OK; + + /* Initialize IPC */ + + mx8mp_ipc_init(); + + /* Subscribe to IPC */ + + mx8mp_ipc_subscribe(RPTUN_IPC_CHAN_SLAVE_RX, + mx8mp_ipc_callback, + dev); + + /* Configure device */ + + dev->rptun.ops = &g_mx8mp_rptun_ops; + strncpy(dev->cpuname, cpuname, RPMSG_NAME_SIZE); + strncpy(dev->shmemname, shmemname, RPMSG_NAME_SIZE); + + ret = rptun_initialize(&dev->rptun); + if (ret < 0) + { + ipcerr("ERROR: rptun_initialize failed %d!\n", ret); + } + + return ret; +} diff --git a/arch/arm/src/mx8mp/mx8mp_rptun.h b/arch/arm/src/mx8mp/mx8mp_rptun.h new file mode 100644 index 0000000000000..50631f4ba432b --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_rptun.h @@ -0,0 +1,44 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_rptun.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MX8MP_MX8MP_RPTUN_H +#define __ARCH_ARM_SRC_MX8MP_MX8MP_RPTUN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: mx8mp_rptun_init + ****************************************************************************/ + +int mx8mp_rptun_init(const char *shmemname, const char *cpuname); + +#endif /* __ARCH_ARM_SRC_MX8MP_MX8MP_RPTUN_H */ diff --git a/arch/arm/src/mx8mp/mx8mp_rsctable.c b/arch/arm/src/mx8mp/mx8mp_rsctable.c new file mode 100644 index 0000000000000..60839575e52bb --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_rsctable.c @@ -0,0 +1,123 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_rsctable.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "mx8mp_rsctable.h" +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NUM_VRINGS 0x02 +#define RL_BUFFER_COUNT 0x100 +#define VRING_ALIGN 0x1000 +#define VDEV0_VRING_BASE 0x55000000 +#define RESOURCE_TABLE_BASE 0x550FF000 +#define VRING_SIZE 0x8000 + +#define NO_RESOURCE_ENTRIES (1) +#define RSC_VDEV_FEATURE_NS (1) /* Support name service announcement */ +#define MX8MP_RSC_TABLE_VERSION (1) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Place resource table in special ELF section */ +#if defined(__ARMCC_VERSION) || defined(__GNUC__) +__attribute__ ((section(".resource_table"))) +#elif defined(__ICCARM__) +#pragma location = ".resource_table" +#else +#error Compiler not supported! +#endif +const struct rptun_rsc_s g_mx8mp_rsc_table = +{ + .rsc_tbl_hdr = + { + MX8MP_RSC_TABLE_VERSION, + NO_RESOURCE_ENTRIES, + { + 0, 0 + } + }, + + .offset = + { + offsetof(struct rptun_rsc_s, rpmsg_vdev) + }, + + .log_trace = + { + RSC_TRACE, 0, 0 + }, + + .rpmsg_vdev = /* SRTM virtio device entry */ + { + RSC_VDEV, + 7, + 2, + RSC_VDEV_FEATURE_NS, + 0, + 0, + 0, + NUM_VRINGS, + { + 0, 0 + } + }, + + .rpmsg_vring0 = + { + VDEV0_VRING_BASE, + VRING_ALIGN, + RL_BUFFER_COUNT, + 0, + 0 + }, + + .rpmsg_vring1 = + { + VDEV0_VRING_BASE + VRING_SIZE, + VRING_ALIGN, + RL_BUFFER_COUNT, + 1, + 0 + }, + + .config = + { + 0 + } +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void mx8mp_copy_rsc_table(void) +{ + memcpy((void *)RESOURCE_TABLE_BASE, (void *)&g_mx8mp_rsc_table, + sizeof(g_mx8mp_rsc_table)); +} diff --git a/arch/arm/src/mx8mp/mx8mp_rsctable.h b/arch/arm/src/mx8mp/mx8mp_rsctable.h new file mode 100644 index 0000000000000..721accb517d7a --- /dev/null +++ b/arch/arm/src/mx8mp/mx8mp_rsctable.h @@ -0,0 +1,42 @@ +/**************************************************************************** + * arch/arm/src/mx8mp/mx8mp_rsctable.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_MX8MP_MX8MP_RSCTABLE_H +#define __ARCH_ARM_SRC_MX8MP_MX8MP_RSCTABLE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +extern const struct rptun_rsc_s g_mx8mp_rsc_table; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +void mx8mp_copy_rsc_table(void); + +#endif /* __ARCH_ARM_SRC_MX8MP_MX8MP_RSCTABLE_H */ diff --git a/arch/arm/src/nrf52/CMakeLists.txt b/arch/arm/src/nrf52/CMakeLists.txt index 409db39c17766..d20b6339d7f91 100644 --- a/arch/arm/src/nrf52/CMakeLists.txt +++ b/arch/arm/src/nrf52/CMakeLists.txt @@ -1,22 +1,22 @@ -############################################################################ +# ############################################################################## # arch/arm/src/nrf52/CMakeLists.txt # -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at # -# http://www.apache.org/licenses/LICENSE-2.0 +# http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, WITHOUT # WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. +# License for the specific language governing permissions and limitations under +# the License. # -############################################################################ +# ############################################################################## set(SRCS nrf52_start.c @@ -94,6 +94,20 @@ endif() if(CONFIG_NRF52_RADIO) list(APPEND SRCS nrf52_radio.c) + + if(CONFIG_NRF52_RADIO_IEEE802154) + list(APPEND SRCS nrf52_ieee802154_radio.c) + list(APPEND SRCS nrf52_ieee802154_tim.c) + list(APPEND SRCS nrf52_ieee802154.c) + + if(CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME) + list(APPEND SRCS nrf52_ieee802154_rtc.c) + endif() + + if(CONFIG_NRF52_RADIO_IEEE802154_TRACE) + list(APPEND SRCS nrf52_ieee802154_trace.c) + endif() + endif() endif() if(CONFIG_NRF52_TIMER) @@ -130,65 +144,68 @@ endif() if(CONFIG_NRF52_SOFTDEVICE_CONTROLLER) -set(NRFXLIB_VER "2.3.0") -set(NRFXLIB_URL "https://github.com/nrfconnect/sdk-nrfxlib/archive") - -if(NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/sdk-nrfxlib) - FetchContent_Declare( - sdk-nrfxlib - DOWNLOAD_NAME "sdk-nrfxlib-v${NRFXLIB_VER}.tar.gz" - DOWNLOAD_DIR ${CMAKE_CURRENT_LIST_DIR} - URL "${NRFXLIB_URL}/v${NRFXLIB_VER}.tar.gz" - SOURCE_DIR - ${CMAKE_CURRENT_LIST_DIR}/sdk-nrfxlib - BINARY_DIR - ${CMAKE_BINARY_DIR}/arch/sdk-nrfxlib - CONFIGURE_COMMAND - "" - BUILD_COMMAND - "" - INSTALL_COMMAND - "" - TEST_COMMAND - "" - DOWNLOAD_NO_PROGRESS true - TIMEOUT 30) - - FetchContent_GetProperties(sdk-nrfxlib) - - if(NOT sdk-nrfxlib_POPULATED) - FetchContent_Populate(sdk-nrfxlib) + set(NRFXLIB_VER "2.3.0") + set(NRFXLIB_URL "https://github.com/nrfconnect/sdk-nrfxlib/archive") + + if(NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/sdk-nrfxlib) + FetchContent_Declare( + sdk-nrfxlib + DOWNLOAD_NAME "sdk-nrfxlib-v${NRFXLIB_VER}.tar.gz" + DOWNLOAD_DIR ${CMAKE_CURRENT_LIST_DIR} + URL "${NRFXLIB_URL}/v${NRFXLIB_VER}.tar.gz" + SOURCE_DIR + ${CMAKE_CURRENT_LIST_DIR}/sdk-nrfxlib + BINARY_DIR + ${CMAKE_BINARY_DIR}/arch/sdk-nrfxlib + CONFIGURE_COMMAND + "" + BUILD_COMMAND + "" + INSTALL_COMMAND + "" + TEST_COMMAND + "" + DOWNLOAD_NO_PROGRESS true + TIMEOUT 30) + + FetchContent_GetProperties(sdk-nrfxlib) + + if(NOT sdk-nrfxlib_POPULATED) + FetchContent_Populate(sdk-nrfxlib) + endif() endif() -endif() -set(NRFXLIB_DIR "${NUTTX_CHIP_ABS_DIR}/sdk-nrfxlib") + set(NRFXLIB_DIR "${NUTTX_CHIP_ABS_DIR}/sdk-nrfxlib") -target_include_directories(arch PRIVATE ${NUTTX_CHIP_ABS_DIR}/sdc) -target_include_directories(arch PRIVATE ${NRFXLIB_DIR}/mpsl/include) -target_include_directories(arch PRIVATE ${NRFXLIB_DIR}/softdevice_controller/include) + target_include_directories(arch PRIVATE ${NUTTX_CHIP_ABS_DIR}/sdc) + target_include_directories(arch PRIVATE ${NRFXLIB_DIR}/mpsl/include) + target_include_directories( + arch PRIVATE ${NRFXLIB_DIR}/softdevice_controller/include) -list(APPEND SRCS nrf52_sdc.c) + list(APPEND SRCS nrf52_sdc.c) -add_compile_options(-DNRF52_SERIES) + add_compile_options(-DNRF52_SERIES) -if(CONFIG_ARCH_FPU) - set(NRFXLIB_LIB_VARIANT hard-float) -else () - set(NRFXLIB_LIB_VARIANT soft-float) -endif() + if(CONFIG_ARCH_FPU) + set(NRFXLIB_LIB_VARIANT hard-float) + else() + set(NRFXLIB_LIB_VARIANT soft-float) + endif() -if(CONFIG_NRF52_SDC_PERIPHERAL) - set(SOFTDEVICE_LIB_VARIANT libsoftdevice_controller_peripheral.a) -elseif(CONFIG_NRF52_SDC_CENTRAL) - set(SOFTDEVICE_LIB_VARIANT libsoftdevice_controller_central.a) -elseif(CONFIG_NRF52_SDC_MULTIROLE) - set(SOFTDEVICE_LIB_VARIANT libsoftdevice_controller_multirole.a) -endif() + if(CONFIG_NRF52_SDC_PERIPHERAL) + set(SOFTDEVICE_LIB_VARIANT libsoftdevice_controller_peripheral.a) + elseif(CONFIG_NRF52_SDC_CENTRAL) + set(SOFTDEVICE_LIB_VARIANT libsoftdevice_controller_central.a) + elseif(CONFIG_NRF52_SDC_MULTIROLE) + set(SOFTDEVICE_LIB_VARIANT libsoftdevice_controller_multirole.a) + endif() -target_link_libraries(arch - ${NRFXLIB_DIR}/mpsl/lib/cortex-m4/${NRFXLIB_LIB_VARIANT}/libmpsl.a) -target_link_libraries(arch - ${NRFXLIB_DIR}/softdevice_controller/lib/cortex-m4/${NRFXLIB_LIB_VARIANT}/${SOFTDEVICE_LIB_VARIANT}) + target_link_libraries( + arch ${NRFXLIB_DIR}/mpsl/lib/cortex-m4/${NRFXLIB_LIB_VARIANT}/libmpsl.a) + target_link_libraries( + arch + ${NRFXLIB_DIR}/softdevice_controller/lib/cortex-m4/${NRFXLIB_LIB_VARIANT}/${SOFTDEVICE_LIB_VARIANT} + ) endif() diff --git a/arch/arm/src/nrf52/Kconfig b/arch/arm/src/nrf52/Kconfig index 2bde7f31047d3..5bd0a293bb182 100644 --- a/arch/arm/src/nrf52/Kconfig +++ b/arch/arm/src/nrf52/Kconfig @@ -42,6 +42,8 @@ config ARCH_CHIP_NRF52840 select NRF52_HAVE_USBDEV select NRF52_HAVE_PWM3 select NRF52_HAVE_CRYPTOCELL + select NRF52_HAVE_IEEE802154 + select NRF52_HAVE_BLELR endchoice # NRF52 Chip Selection @@ -134,6 +136,14 @@ config NRF52_HAVE_CRYPTOCELL bool default n +config NRF52_HAVE_BLELE + bool + default n + +config NRF52_HAVE_IEEE802154 + bool + default n + # Peripheral Selection config NRF52_I2C_MASTER @@ -611,6 +621,52 @@ endif # NRF52_PWM endmenu # PWM configuration +menu "RADIO Configuration" + +if NRF52_RADIO + +config NRF52_RADIO_CUSTOM + bool "RADIO uses custom IRQ handlers" + default n + +config NRF52_RADIO_IEEE802154 + bool "RADIO IEEE802.15.4 protocol" + default n + depends on NRF52_HAVE_IEEE802154 + select ARMV7M_USEBASEPRI + select ARCH_RAMVECTORS + select ARCH_IRQPRIO + select NRF52_RADIO_CUSTOM + select NRF52_TIMER0 + +if NRF52_RADIO_IEEE802154 + +config NRF52_RADIO_IEEE802154_SUPERFRAME + bool "RADIO IEEE802.15.4 superframe support" + default n + select NRF52_RTC0 + select NRF52_USE_LFCLK + +config NRF52_RADIO_IEEE802154_GTS_SLOTS + int "RADIO IEEE802.15.4 GTS slots" + default 2 + depends on NRF52_RADIO_IEEE802154_SUPERFRAME + +config NRF52_RADIO_IEEE802154_TRACE + bool "RADIO IEEE802.15.4 trace support" + default n + +config NRF52_RADIO_IEEE802154_TRACE_BUFSIZE + int "RADIO IEEE802.15.4 trace buffer size" + depends on NRF52_RADIO_IEEE802154_TRACE + default 1024 + +endif + +endif #NRF52_RADIO + +endmenu # "RADIO Configuration" + menu "SAADC Configuration" if NRF52_SAADC diff --git a/arch/arm/src/nrf52/Make.defs b/arch/arm/src/nrf52/Make.defs index c570f66ff4bcb..12650bc976b25 100644 --- a/arch/arm/src/nrf52/Make.defs +++ b/arch/arm/src/nrf52/Make.defs @@ -89,6 +89,17 @@ endif ifeq ($(CONFIG_NRF52_RADIO),y) CHIP_CSRCS += nrf52_radio.c +ifeq ($(CONFIG_NRF52_RADIO_IEEE802154),y) +CHIP_CSRCS += nrf52_ieee802154_radio.c +CHIP_CSRCS += nrf52_ieee802154_tim.c +CHIP_CSRCS += nrf52_ieee802154.c +ifeq ($(CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME),y) +CHIP_CSRCS += nrf52_ieee802154_rtc.c +endif +ifeq ($(CONFIG_NRF52_RADIO_IEEE802154_TRACE),y) +CHIP_CSRCS += nrf52_ieee802154_trace.c +endif +endif endif ifeq ($(CONFIG_NRF52_TIMER),y) diff --git a/arch/arm/src/nrf52/hardware/nrf52_radio.h b/arch/arm/src/nrf52/hardware/nrf52_radio.h index 14f16753c8575..d58793976ce1b 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_radio.h +++ b/arch/arm/src/nrf52/hardware/nrf52_radio.h @@ -206,146 +206,6 @@ /* Register Bitfield Definitions ********************************************/ -/* TASKS_TXEN Register */ - -#define RADIO_TASKS_TXEN (1 << 0) /* Bit 0: Enable RADIO in TX mode */ - -/* TASKS_RXEN Register */ - -#define RADIO_TASKS_RXEN (1 << 0) /* Bit 0: Enable RADIO in RX mode */ - -/* TASKS_START Register */ - -#define RADIO_TASKS_START (1 << 0) /* Bit 0: Start RADIO */ - -/* TASKS_STOP Register */ - -#define RADIO_TASKS_STOP (1 << 0) /* Bit 0: Stop RADIO */ - -/* TASKS_DISABLE Register */ - -#define RADIO_TASKS_DISABLE (1 << 0) /* Bit 0: Disable RADIO */ - -/* TASKS_RSSISTART Register */ - -#define RADIO_TASKS_RSSISTART (1 << 0) /* Bit 0: Start the RSSI */ - -/* TASKS_RSSISTOP Register */ - -#define RADIO_TASKS_RSSISTOP (1 << 0) /* Bit 0: Stop the RSSI */ - -/* TASKS_BCSTART Register */ - -#define RADIO_TASKS_BCSTART (1 << 0) /* Bit 0: Start the bit counter */ - -/* TASKS_BCSTOP Register */ - -#define RADIO_TASKS_BCSTOP (1 << 0) /* Bit 0: Stop the bit counter */ - -/* TASKS_EDSTART Register */ - -#define RADIO_TASKS_EDSTART (1 << 0) /* Bit 0: Start the energy detect measurement (IEEE 802.15.4) */ - -/* TASKS_EDSTOP Register */ - -#define RADIO_TASKS_EDSTOP (1 << 0) /* Bit 0: Stop the energy detect measurement (IEEE 802.15.4) */ - -/* TASKS_CCASTART Register */ - -#define RADIO_TASKS_CCASTART (1 << 0) /* Bit 0: Start the channel assessment (IEEE 802.15.4) */ - -/* TASKS_CCASTOP Register */ - -#define RADIO_TASKS_CCASTOP (1 << 0) /* Bit 0: Stop the channel assessment (IEEE 802.15.4) */ - -/* EVENTS_READY Register */ - -#define RADIO_EVENTS_READY (1 << 0) /* Bit 0: RADIO has ramped up and is ready to be started */ - -/* EVENTS_ADDRESS Register */ - -#define RADIO_EVENTS_ADDRESS (1 << 0) /* Bit 0: Address sent or received */ - -/* EVENTS_PAYLOAD Register */ - -#define RADIO_EVENTS_PAYLOAD (1 << 0) /* Bit 0: Packet payload sent or received */ - -/* EVENTS_END Register */ - -#define RADIO_EVENTS_END (1 << 0) /* Bit 0: Packet sent or received */ - -/* EVENTS_DISABLED Register */ - -#define RADIO_EVENTS_DISABLED (1 << 0) /* Bit 0: RADIO has been disabled */ - -/* EVENTS_DEVMATCH Register */ - -#define RADIO_EVENTS_DEVMATCH (1 << 0) /* Bit 0: A device address match */ - -/* EVENTS_DEVMISS Register */ - -#define RADIO_EVENTS_DEVMISS (1 << 0) /* Bit 0: No device address match */ - -/* EVENTS_RSSIEND Register */ - -#define RADIO_EVENTS_RSSIEND (1 << 0) /* Bit 0: Sampling of receive signal strength complete */ - -/* EVENTS_BCMATCH Register */ - -#define RADIO_EVENTS_BCMATCH (1 << 0) /* Bit 0: Bit counter reached bit count value */ - -/* EVENTS_CRCOK Register */ - -#define RADIO_EVENTS_CRCOK (1 << 0) /* Bit 0: Packet received with CRC ok */ - -/* EVENTS_CRCERROR Register */ - -#define RADIO_EVENTS_CRCERROR (1 << 0) /* Bit 0: Packet received with CRC error */ - -/* EVENTS_FRAMESTART Register */ - -#define RADIO_EVENTS_FRAMESTART (1 << 0) /* Bit 0: IEEE 802.15.4 length field received*/ - -/* EVENTS_EDEND Register */ - -#define RADIO_EVENTS_EDEND (1 << 0) /* Bit 0: ampling of energy detection complete */ - -/* EVENTS_EDSTOPPED Register */ - -#define RADIO_EVENTS_EDSTOPPED (1 << 0) /* Bit 0: The sampling of energy detection has stopped */ - -/* EVENTS_CCAIDLE Register */ - -#define RADIO_EVENTS_CCAIDLE (1 << 0) /* Bit 0: Wireless medium in idle */ - -/* EVENTS_CCABUSY Register */ - -#define RADIO_EVENTS_CCABUSY (1 << 0) /* Bit 0: Wireless medium busy */ - -/* EVENTS_CCASTOPPED Register */ - -#define RADIO_EVENTS_CCASTOPPED (1 << 0) /* Bit 0: The CCA has stopped */ - -/* EVENTS_RATEBOOST Register */ - -#define RADIO_EVENTS_RATEBOOST (1 << 0) /* Bit 0: Ble_LR CI field received */ - -/* EVENTS_TXREADY Register */ - -#define RADIO_EVENTS_TXREADY (1 << 0) /* Bit 0: RADIO has ramped up and is ready to be started TX path */ - -/* EVENTS_RXREADY Register */ - -#define RADIO_EVENTS_RXREADY (1 << 0) /* Bit 0: RADIO has ramped up and is ready to be started RX path */ - -/* EVENTS_MHRMATCH Register */ - -#define RADIO_EVENTS_MHRMATCH (1 << 0) /* Bit 0: MAC header match found */ - -/* EVENTS_PHYEND Register */ - -#define RADIO_EVENTS_PHYEND (1 << 0) /* Bit 0: Last bit is sent on air */ - /* SHORTS Register */ #define RADIO_SHORTS_READY_START (1 << 0) /* Bit 0: Shortcut between event READY and task START */ @@ -622,6 +482,12 @@ # define RADIO_CCACTRL_CCAMODE_CANDED (2 << RADIO_CCACTRL_CCAMODE_SHIFT) # define RADIO_CCACTRL_CCAMODE_CORED (3 << RADIO_CCACTRL_CCAMODE_SHIFT) # define RADIO_CCACTRL_CCAMODE_EDTST1 (4 << RADIO_CCACTRL_CCAMODE_SHIFT) +#define RADIO_CCACTRL_CCAEDTHRES_SHIFT (8) +#define RADIO_CCACTRL_CCAEDTHRES_MASK (0xff << RADIO_CCACTRL_CCAEDTHRES_SHIFT) +#define RADIO_CCACTRL_CCACORRTHRES_SHIFT (16) +#define RADIO_CCACTRL_CCACORRTHRES_MASK (0xff << RADIO_CCACTRL_CCACORRTHRES_SHIFT) +#define RADIO_CCACTRL_CCACORRCNT_SHIFT (24) +#define RADIO_CCACTRL_CCACORRCNT_MASK (0xff << RADIO_CCACTRL_CCACORRCNT_SHIFT) /* POWER Register */ diff --git a/arch/arm/src/nrf52/hardware/nrf52_temp.h b/arch/arm/src/nrf52/hardware/nrf52_temp.h index 850d70bdc9ef1..439739ef67e64 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_temp.h +++ b/arch/arm/src/nrf52/hardware/nrf52_temp.h @@ -95,4 +95,4 @@ #define NRF52_TEMP_INTENCLR_DATARDY (1 << 0) /* Read: Enabled */ -#endif // __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_TEMP_H +#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_TEMP_H */ diff --git a/arch/arm/src/nrf52/hardware/nrf52_utils.h b/arch/arm/src/nrf52/hardware/nrf52_utils.h index 4ecbc1ce7dfb0..069234bc1f7eb 100644 --- a/arch/arm/src/nrf52/hardware/nrf52_utils.h +++ b/arch/arm/src/nrf52/hardware/nrf52_utils.h @@ -27,6 +27,8 @@ #include +#include "arm_internal.h" + /**************************************************************************** * Public Function Prototypes / Inline Functions ****************************************************************************/ diff --git a/arch/arm/src/nrf52/nrf52_gpiote.c b/arch/arm/src/nrf52/nrf52_gpiote.c index f2bf33855ab3b..5aead39e92997 100644 --- a/arch/arm/src/nrf52/nrf52_gpiote.c +++ b/arch/arm/src/nrf52/nrf52_gpiote.c @@ -53,8 +53,9 @@ struct nrf52_gpiote_callback_s { - xcpt_t callback; - void *arg; + xcpt_t callback; + void *arg; + uint32_t pinset; }; /**************************************************************************** @@ -462,12 +463,15 @@ int nrf52_gpiote_set_event(uint32_t pinset, flags = enter_critical_section(); - /* Get free channel */ + /* Get free channel or channel already used by pinset */ for (i = 0; i < GPIOTE_CHANNELS; i++) { - if (g_gpiote_ch_callbacks[i].callback == NULL) + if (g_gpiote_ch_callbacks[i].callback == NULL || + g_gpiote_ch_callbacks[i].pinset == pinset) { + g_gpiote_ch_callbacks[i].pinset = pinset; + /* Configure channel */ nrf52_gpiote_set_ch_event(pinset, i, diff --git a/arch/arm/src/nrf52/nrf52_ieee802154.c b/arch/arm/src/nrf52/nrf52_ieee802154.c new file mode 100644 index 0000000000000..28956ce75e28a --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_ieee802154.c @@ -0,0 +1,999 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_ieee802154.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include + +#include "nrf52_ieee802154_trace.h" + +#include "nrf52_ieee802154_priv.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_NRF52_RADIO_CUSTOM +# error RADIO custom interrupts must be enabled +#endif + +#ifndef CONFIG_SCHED_HPWORK +# error High priority work queue required in this driver +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* IEEE 802.15.4 radio data */ + +static struct nrf52_radioi8_dev_s g_nrf52_radioi8; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Set/get radio attributes */ + +static int nrf52_radioi8_setrxmode(struct nrf52_radioi8_dev_s *dev, + int mode); +static int nrf52_radioi8_setpanid(struct nrf52_radioi8_dev_s *dev, + const uint8_t *panid); +static int nrf52_radioi8_setsaddr(struct nrf52_radioi8_dev_s *dev, + const uint8_t *saddr); +static int nrf52_radioi8_seteaddr(struct nrf52_radioi8_dev_s *dev, + const uint8_t *eaddr); +static int nrf52_radioi8_setcoordsaddr(struct nrf52_radioi8_dev_s *dev, + const uint8_t *saddr); +static int nrf52_radioi8_setdevmode(struct nrf52_radioi8_dev_s *dev, + uint8_t mode); + +/* Radio ops */ + +static int nrf52_radioi8_bind(struct ieee802154_radio_s *radio, + struct ieee802154_radiocb_s *radiocb); +static int nrf52_radioi8_reset(struct ieee802154_radio_s *radio); +static int nrf52_radioi8_getattr(struct ieee802154_radio_s *radio, + enum ieee802154_attr_e attr, + union ieee802154_attr_u *attrval); +static int nrf52_radioi8_setattr(struct ieee802154_radio_s *radio, + enum ieee802154_attr_e attr, + const union ieee802154_attr_u *attrval); +static int nrf52_radioi8_txnotify(struct ieee802154_radio_s *radio, + bool gts); +static int nrf52_radioi8_txdelayed(struct ieee802154_radio_s *radio, + struct ieee802154_txdesc_s *txdesc, + uint32_t symboldelay); +static int nrf52_radioi8_rxenable(struct ieee802154_radio_s *radio, + bool enable); +static int nrf52_radioi8_setchannel(struct nrf52_radioi8_dev_s *dev, + uint8_t chan); +static int nrf52_radioi8_setcca(struct nrf52_radioi8_dev_s *dev, + struct ieee802154_cca_s *cca); +static int nrf52_radioi8_energydetect(struct ieee802154_radio_s *radio, + uint32_t nsymbols); + +static int +nrf52_radioi8_beaconstart(struct ieee802154_radio_s *radio, + const struct ieee802154_superframespec_s *sfspec, + struct ieee802154_beaconframe_s *beacon); +static int +nrf52_radioi8_beaconupdate(struct ieee802154_radio_s *radio, + struct ieee802154_beaconframe_s *beacon); +static int nrf52_radioi8_beaconstop(struct ieee802154_radio_s *radio); +static int +nrf52_radioi8_sfupdate(struct ieee802154_radio_s *radio, + const struct ieee802154_superframespec_s *sfspec); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_radioi8_setrxmode + * + * Description: + * Set the RX mode (normal, promiscuous, no CRC). + * + ****************************************************************************/ + +static int nrf52_radioi8_setrxmode(struct nrf52_radioi8_dev_s *dev, + int mode) +{ + wlinfo("setrxmode %d\n", mode); + + if (mode < NRF52_RXMODE_NORMAL || mode > NRF52_RXMODE_NOCRC) + { + return -EINVAL; + } + + dev->state.rxmode = mode; + + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_setpanid + * + * Description: + * Define the PAN ID the device is operating on. + * + ****************************************************************************/ + +static int nrf52_radioi8_setpanid(struct nrf52_radioi8_dev_s *dev, + const uint8_t *panid) +{ + wlinfo("setpanid: %02X:%02X\n", panid[0], panid[1]); + IEEE802154_PANIDCOPY(dev->state.addr.panid, panid); + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_setsaddr + * + * Description: + * Define the device short address. The following addresses are special: + * + * FFFEh : Broadcast + * FFFFh : Unspecified + * + ****************************************************************************/ + +static int nrf52_radioi8_setsaddr(struct nrf52_radioi8_dev_s *dev, + const uint8_t *saddr) +{ + wlinfo("setsaddr: %02X:%02X\n", saddr[0], saddr[1]); + IEEE802154_SADDRCOPY(dev->state.addr.saddr, saddr); + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_seteaddr + * + * Description: + * Define the device extended address. The following addresses are special: + * + * ffffffffffffffffh : Unspecified + * + ****************************************************************************/ + +static int nrf52_radioi8_seteaddr(struct nrf52_radioi8_dev_s *dev, + const uint8_t *eaddr) +{ + int i = 0; + + wlinfo("seteaddr: %02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n", + eaddr[0], eaddr[1], eaddr[2], eaddr[3], eaddr[4], eaddr[5], + eaddr[6], eaddr[7]); + + for (i = 0; i < 8; i++) + { + dev->state.addr.eaddr[i] = eaddr[i]; + } + + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_setcoordsaddr + * + * Description: + * Define the coordinator short address. The following addresses are + * special: + * + * FFFEh : Broadcast + * FFFFh : Unspecified + * + ****************************************************************************/ + +static int nrf52_radioi8_setcoordsaddr(struct nrf52_radioi8_dev_s *dev, + const uint8_t *saddr) +{ + IEEE802154_SADDRCOPY(dev->state.addr.saddr, saddr); + + wlinfo("setcoordsaddr: %02X:%02X\n", saddr[0], saddr[1]); + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_setcoordeaddr + * + * Description: + * Define the coordinator extended address. The following addresses are + * special: + * + * FFFFFFFFFFFFFFFFh : Unspecified + * + ****************************************************************************/ + +static int nrf52_radioi8_setcoordeaddr(struct nrf52_radioi8_dev_s *dev, + const uint8_t *eaddr) +{ + int i = 0; + + wlinfo("setcoordeaddr: %02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X\n", + eaddr[0], eaddr[1], eaddr[2], eaddr[3], eaddr[4], eaddr[5], + eaddr[6], eaddr[7]); + + for (i = 0; i < 8; i++) + { + dev->state.addr.eaddr[i] = eaddr[i]; + } + + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_setdevmode + * + * Description: + * Define the device behaviour: endpoint, coord or PAN coord. + * + ****************************************************************************/ + +static int nrf52_radioi8_setdevmode(struct nrf52_radioi8_dev_s *dev, + uint8_t mode) +{ + wlinfo("setdevmode %d\n", mode); + + if (mode < IEEE802154_DEVMODE_ENDPOINT || + mode > IEEE802154_DEVMODE_PANCOORD) + { + return -EINVAL; + } + + dev->state.devmode = mode; + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_bind + * + * Description: + * Bind radio callbacks. + * + ****************************************************************************/ + +static int nrf52_radioi8_bind(struct ieee802154_radio_s *radio, + struct ieee802154_radiocb_s *radiocb) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)radio; + + DEBUGASSERT(dev != NULL); + dev->radiocb = radiocb; + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_reset + * + * Description: + * Reset radio. + * + ****************************************************************************/ + +static int nrf52_radioi8_reset(struct ieee802154_radio_s *radio) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)radio; + struct ieee802154_cca_s cca; + int ret = OK; + +#ifdef CONFIG_NRF52_RADIO_IEEE802154_TRACE + /* Reset trace */ + + nrf52_radioi8_trace_init(); +#endif + + /* Reset radio state */ + + memset(&dev->state, 0, sizeof(struct nrf52_radioi8_state_s)); + + /* Initialize radio in IEEE 802.15.4 mode */ + + ret = dev->radio->ops->reset(dev->radio); + if (ret < 0) + { + goto errout; + } + + /* Reset TIMER */ + + dev->tim->ops->reset(dev); + +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + /* Reset RTC */ + + dev->rtc->ops->reset(dev); +#endif + + /* Set channel */ + + nrf52_radioi8_setchannel(dev, 11); + + /* Configure default CCA: + * - CCA mode ED + * - no carrier sense + * - recommenced ED threshold -69 dBm + */ + + cca.use_ed = 1; + cca.use_cs = 0; + cca.edth = 0x60; + cca.csth = 0x00; + nrf52_radioi8_setcca(dev, &cca); + + /* Configure initial RX mode */ + + nrf52_radioi8_setrxmode(dev, NRF52_RXMODE_NORMAL); + +errout: + return ret; +} + +/**************************************************************************** + * Name: nrf52_radioi8_getattr + * + * Description: + * Get radio attribute. + * + ****************************************************************************/ + +static int nrf52_radioi8_getattr(struct ieee802154_radio_s *radio, + enum ieee802154_attr_e attr, + union ieee802154_attr_u *attrval) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)radio; + int ret = OK; + + switch (attr) + { + case IEEE802154_ATTR_MAC_EADDR: + { + memcpy(&attrval->mac.eaddr[0], &dev->state.addr.eaddr[0], 8); + ret = IEEE802154_STATUS_SUCCESS; + break; + } + + case IEEE802154_ATTR_MAC_MAX_FRAME_WAITTIME: + { + attrval->mac.max_frame_waittime = + dev->radio->state.max_frame_waittime; + ret = IEEE802154_STATUS_SUCCESS; + break; + } + + case IEEE802154_ATTR_PHY_SYMBOL_DURATION: + { + attrval->phy.symdur_picosec = (IEEE802154_SYMBOL_US * 1000000); + ret = IEEE802154_STATUS_SUCCESS; + break; + } + + case IEEE802154_ATTR_PHY_CHAN: + { + attrval->phy.chan = dev->state.chan; + ret = IEEE802154_STATUS_SUCCESS; + break; + } + + case IEEE802154_ATTR_PHY_FCS_LEN: + { + attrval->phy.fcslen = 2; + ret = IEEE802154_STATUS_SUCCESS; + break; + } + + case IEEE802154_ATTR_PHY_REGDUMP: + { + NRF52_RADIO_DUMPREGS(dev->radio->lower); + break; + } + +#ifdef CONFIG_NRF52_RADIO_IEEE802154_TRACE + case IEEE802154_ATTR_PHY_TRACEDUMP: + { + nrf52_radioi8_trace_dump(); + break; + } +#endif + + default: + { + ret = IEEE802154_STATUS_UNSUPPORTED_ATTRIBUTE; + break; + } + } + + return ret; +} + +/**************************************************************************** + * Name: nrf52_radioi8_setattr + * + * Description: + * Set radio attribute. + * + ****************************************************************************/ + +static int nrf52_radioi8_setattr(struct ieee802154_radio_s *radio, + enum ieee802154_attr_e attr, + const union ieee802154_attr_u *attrval) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)radio; + int ret = IEEE802154_STATUS_SUCCESS; + + switch (attr) + { + case IEEE802154_ATTR_MAC_PANID: + { + nrf52_radioi8_setpanid(dev, attrval->mac.panid); + break; + } + + case IEEE802154_ATTR_MAC_SADDR: + { + nrf52_radioi8_setsaddr(dev, attrval->mac.saddr); + break; + } + + case IEEE802154_ATTR_MAC_EADDR: + { + nrf52_radioi8_seteaddr(dev, attrval->mac.eaddr); + break; + } + + case IEEE802154_ATTR_MAC_COORD_SADDR: + { + nrf52_radioi8_setcoordsaddr(dev, attrval->mac.coordsaddr); + break; + } + + case IEEE802154_ATTR_MAC_COORD_EADDR: + { + nrf52_radioi8_setcoordeaddr(dev, attrval->mac.coordeaddr); + break; + } + + case IEEE802154_ATTR_MAC_PROMISCUOUS_MODE: + { + if (attrval->mac.promisc_mode) + { + nrf52_radioi8_setrxmode(dev, NRF52_RXMODE_PROMISC); + } + else + { + nrf52_radioi8_setrxmode(dev, NRF52_RXMODE_NORMAL); + } + break; + } + + case IEEE802154_ATTR_PHY_CHAN: + { + nrf52_radioi8_setchannel(dev, attrval->phy.chan); + break; + } + + case IEEE802154_ATTR_MAC_DEVMODE: + { + nrf52_radioi8_setdevmode(dev, attrval->mac.devmode); + break; + } + + default: + { + ret = IEEE802154_STATUS_UNSUPPORTED_ATTRIBUTE; + break; + } + } + + return ret; +} + +/**************************************************************************** + * Name: nrf52_radioi8_txnotify + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + ****************************************************************************/ + +static int nrf52_radioi8_txnotify(struct ieee802154_radio_s *radio, + bool gts) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)radio; + int ret = OK; + + if (gts) + { + ret = dev->radio->ops->gts_poll(dev); + } + else + { + ret = dev->radio->ops->csma_poll(dev); + } + + return ret; +} + +/**************************************************************************** + * Name: nrf52_radioi8_txdelayed + * + * Description: + * Transmit a packet without regard to supeframe structure after a certain + * number of symbols. This function is used to send Data Request + * responses. It can also be used to send data immediately if the delay + * is set to 0. + * + ****************************************************************************/ + +static int nrf52_radioi8_txdelayed(struct ieee802154_radio_s *radio, + struct ieee802154_txdesc_s *txdesc, + uint32_t symboldelay) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)radio; + int ret = OK; + + /* Get exclusive access to the radio device */ + + ret = nxmutex_lock(&dev->lock); + if (ret < 0) + { + return ret; + } + + /* There should never be more than one of these transactions at once. */ + + DEBUGASSERT(!dev->state.txdelayed_busy); + + dev->state.txdelayed_desc = txdesc; + dev->state.txdelayed_busy = true; + + /* TODO: should we add txdelayed to queue ? */ + + if (dev->radio->state.csma_busy) + { + return -EBUSY; + } + + /* Wait for ACKTX done - we start transmition in + * nrf52_radioi8_state_acktx() + */ + + if (dev->radio->state.state == NRF52_RADIO_STATE_ACKTX) + { + goto out; + } + + /* Setup TX */ + + dev->radio->ops->norm_setup(dev, txdesc->frame, false); + + if (symboldelay == 0) + { + /* Send now */ + + dev->radio->ops->norm_trigger(dev); + } + else + { + /* Run TIMER - TX is handled in timer isr */ + + dev->tim->ops->setup(dev, NRF52_TIMER_CHAN_TXDELAY, symboldelay); + } + +out: + nxmutex_unlock(&dev->lock); + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_rxenable + * + * Description: + * Enable/Disable receiver. + * + ****************************************************************************/ + +static int nrf52_radioi8_rxenable(struct ieee802154_radio_s *radio, + bool enable) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)radio; + + wlinfo("rxenable %d\n", enable); + return dev->radio->ops->rxenable(dev, enable); +} + +/**************************************************************************** + * Name: nrf52_radioi8_energydetect + * + * Description: + * Start the energy detect measurement. + * + ****************************************************************************/ + +static int nrf52_radioi8_energydetect(struct ieee802154_radio_s *radio, + uint32_t nsymbols) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)radio; + + return dev->radio->ops->energydetect(dev, nsymbols); +} + +/**************************************************************************** + * Name: nrf52_radioi8_setchannel + * + * Description: + * Define the current radio channel the device is operating on. + * In the 2.4 GHz, there are 16 channels, each 2 MHz wide, 5 MHz spacing: + * + * Chan MHz Chan MHz Chan MHz Chan MHz + * 11 2405 15 2425 19 2445 23 2465 + * 12 2410 16 2430 20 2450 24 2470 + * 13 2415 17 2435 21 2455 25 2475 + * 14 2420 18 2440 22 2460 26 2480 + * + ****************************************************************************/ + +static int nrf52_radioi8_setchannel(struct nrf52_radioi8_dev_s *dev, + uint8_t chan) +{ + int ret = OK; + + wlinfo("setchannel: %u\n", (unsigned)chan); + + if (dev->state.chan == chan) + { + return OK; + } + + if (chan < 11 || chan > 26) + { + wlerr("Invalid chan: %d\n", chan); + return -EINVAL; + } + + ret = dev->radio->ops->setchannel(dev, chan); + if (ret < 0) + { + wlerr("dev->radio->ops->setchannel failed %d\n", ret); + return -EINVAL; + } + + dev->state.chan = chan; + + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_setcca + * + * Description: + * Define the Clear Channel Assessement method. + * + ****************************************************************************/ + +static int nrf52_radioi8_setcca(struct nrf52_radioi8_dev_s *dev, + struct ieee802154_cca_s *cca) +{ + int ret = OK; + + if (!cca->use_ed && !cca->use_cs) + { + return -EINVAL; + } + + if (cca->use_cs && cca->csth > 0x0f) + { + return -EINVAL; + } + + /* Configure CCA */ + + ret = dev->radio->ops->setcca(dev, cca); + if (ret < 0) + { + wlerr("dev->radio->ops->setcca failed %d\n", ret); + return -EINVAL; + } + + memcpy(&dev->state.cca, cca, sizeof(struct ieee802154_cca_s)); + + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_beaconstart + * + * Description: + * Start beacon. + * + ****************************************************************************/ + +static int +nrf52_radioi8_beaconstart(struct ieee802154_radio_s *radio, + const struct ieee802154_superframespec_s *sfspec, + struct ieee802154_beaconframe_s *beacon) +{ +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)radio; + irqstate_t flags; + + if (sfspec->pancoord) + { + flags = enter_critical_section(); + + /* Local copy */ + + memcpy(&dev->state.sf, (void *)sfspec, + sizeof(struct ieee802154_superframespec_s)); + + /* Setup beacon transmition */ + + dev->radio->ops->beacon_setup(dev, beacon->bf_data, beacon->bf_len); + + /* Configure RTC events */ + + dev->rtc->ops->setup(dev, &dev->state.sf); + + /* Start RTC */ + + dev->rtc->ops->start(dev); + + leave_critical_section(flags); + } + else + { + /* TODO: missing logic for non-PAN coord */ + + return -ENOTTY; + } + + return OK; +#else + return -ENOTSUP; +#endif +} + +/**************************************************************************** + * Name: nrf52_radioi8_beaconupdate + * + * Description: + * Update beacon. + * + ****************************************************************************/ + +static int +nrf52_radioi8_beaconupdate(struct ieee802154_radio_s *radio, + struct ieee802154_beaconframe_s *beacon) +{ +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)radio; + irqstate_t flags; + + flags = enter_critical_section(); + + /* Arm the beacon TX buffer */ + + memcpy(&dev->radio->beaconbuf[1], beacon->bf_data, beacon->bf_len); + + /* Length = Frame data + CRC */ + + dev->radio->beaconbuf[0] = beacon->bf_len + 2; + + leave_critical_section(flags); + + return OK; +#else + return -ENOTSUP; +#endif +} + +/**************************************************************************** + * Name: nrf52_radioi8_beaconstop + * + * Description: + * Stop beacon. + * + ****************************************************************************/ + +static int nrf52_radioi8_beaconstop(struct ieee802154_radio_s *radio) +{ +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)radio; + irqstate_t flags; + + flags = enter_critical_section(); + + /* Stop RTC */ + + dev->rtc->ops->stop(dev); + + leave_critical_section(flags); + + return OK; +#else + return -ENOTSUP; +#endif +} + +/**************************************************************************** + * Name: nrf52_radioi8_sfupdate + * + * Description: + * Update super frame. + * + ****************************************************************************/ + +static int +nrf52_radioi8_sfupdate(struct ieee802154_radio_s *radio, + const struct ieee802154_superframespec_s *sfspec) +{ +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)radio; + irqstate_t flags; + + flags = enter_critical_section(); + + /* Local copy */ + + memcpy(&dev->state.sf, (void *)sfspec, + sizeof(struct ieee802154_superframespec_s)); + + /* If we are operating on a beacon-enabled network, use slotted CSMA */ + + if (sfspec->beaconorder < 15) + { + /* Need slotted CSMA-CA */ + + dev->radio->state.slotted = true; + + /* Configure RTC */ + + dev->rtc->ops->setup(dev, &dev->state.sf); + + /* Wait for beacon to sync */ + + dev->radio->state.wait_for_beacon = true; + } + else + { + /* Need un-slotted CSMA-CA */ + + dev->radio->state.slotted = false; + } + + leave_critical_section(flags); + + return OK; +#else + return -ENOTSUP; +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_radioi8_register + * + * Description: + * Register NRF52 radio in IEE802154 mode. + * + ****************************************************************************/ + +struct ieee802154_radio_s * +nrf52_radioi8_register(struct nrf52_radio_board_s *board) +{ + struct nrf52_radioi8_dev_s *dev = &g_nrf52_radioi8; + + /* Reset data */ + + memset(&g_nrf52_radioi8, 0, sizeof(struct nrf52_radioi8_dev_s)); + + /* Allow exclusive access to the privmac struct */ + + nxmutex_init(&dev->lock); + + /* Initialize lower-half radio */ + + dev->radio = nrf52_radioi8_radio_init(dev, board); + if (dev->radio == NULL) + { + wlerr("nrf52_radioi8_radio_init failed %d\n", -errno); + return NULL; + } + + DEBUGASSERT(dev->radio->ops->txstart); + DEBUGASSERT(dev->radio->ops->notify_noack); + DEBUGASSERT(dev->radio->ops->ccastart); + DEBUGASSERT(dev->radio->ops->rxenable); + DEBUGASSERT(dev->radio->ops->energydetect); + DEBUGASSERT(dev->radio->ops->setchannel); + DEBUGASSERT(dev->radio->ops->setcca); + DEBUGASSERT(dev->radio->ops->norm_setup); + DEBUGASSERT(dev->radio->ops->norm_trigger); +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + DEBUGASSERT(dev->radio->ops->beacon_setup); + DEBUGASSERT(dev->radio->ops->beacon_tx); +#endif + DEBUGASSERT(dev->radio->ops->reset); + DEBUGASSERT(dev->radio->ops->csma_poll); + DEBUGASSERT(dev->radio->ops->gts_poll); + + /* Initialize TIMER */ + + dev->tim = nrf52_radioi8_tim_init(dev); + if (dev->tim == NULL) + { + wlerr("nrf52_radioi8_tim_init failed %d\n", -errno); + return NULL; + } + + DEBUGASSERT(dev->tim->ops->setup); + DEBUGASSERT(dev->tim->ops->stop); + DEBUGASSERT(dev->tim->ops->reset); + +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + /* Initialize RTC */ + + dev->rtc = nrf52_radioi8_rtc_init(dev); + if (dev->rtc == NULL) + { + wlerr("nrf52_radioi8_rtc_init failed %d\n", -errno); + return NULL; + } + + DEBUGASSERT(dev->rtc->ops->setup); + DEBUGASSERT(dev->rtc->ops->start); + DEBUGASSERT(dev->rtc->ops->stop); + DEBUGASSERT(dev->rtc->ops->reset); +#endif + + /* Connect MAC ops */ + + dev->macops.bind = nrf52_radioi8_bind; + dev->macops.reset = nrf52_radioi8_reset; + dev->macops.getattr = nrf52_radioi8_getattr; + dev->macops.setattr = nrf52_radioi8_setattr; + dev->macops.txnotify = nrf52_radioi8_txnotify; + dev->macops.txdelayed = nrf52_radioi8_txdelayed; + dev->macops.rxenable = nrf52_radioi8_rxenable; + dev->macops.energydetect = nrf52_radioi8_energydetect; + dev->macops.beaconstart = nrf52_radioi8_beaconstart; + dev->macops.beaconupdate = nrf52_radioi8_beaconupdate; + dev->macops.beaconstop = nrf52_radioi8_beaconstop; + dev->macops.sfupdate = nrf52_radioi8_sfupdate; + + return &dev->macops; +} diff --git a/arch/arm/src/nrf52/nrf52_ieee802154_priv.h b/arch/arm/src/nrf52/nrf52_ieee802154_priv.h new file mode 100644 index 0000000000000..04e542ee3aa6d --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_ieee802154_priv.h @@ -0,0 +1,144 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_ieee802154_priv.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_NRF52_IEEE802154_PRIV_H +#define __ARCH_ARM_SRC_NRF52_NRF52_IEEE802154_PRIV_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "nrf52_ieee802154_radio.h" +#include "nrf52_ieee802154_rtc.h" +#include "nrf52_ieee802154_tim.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* GTS slots */ + +#ifndef CONFIG_NRF52_RADIO_IEEE802154_GTS_SLOTS +# define NRF52_GTS_SLOTS 0 +#else +# define NRF52_GTS_SLOTS CONFIG_NRF52_RADIO_IEEE802154_GTS_SLOTS +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* RX modes */ + +enum nrf52_ieee802154_rxmode_e +{ + NRF52_RXMODE_NORMAL, + NRF52_RXMODE_PROMISC, + NRF52_RXMODE_NOCRC +}; + +/* Device modes */ + +enum nrf52_ieee802154_devmode_e +{ + NRF52_DEVMODE_ENDPOINT, + NRF52_DEVMODE_COORD, + NRF52_DEVMODE_PANCOORD +}; + +/* IEEE 802.15.4 device state */ + +struct nrf52_radioi8_state_s +{ + /* MAC Attributes */ + + struct ieee802154_addr_s addr; /* Address */ + struct ieee802154_cca_s cca; /* Clear channel assessement method */ + + /* TX CSMA */ + + struct ieee802154_txdesc_s *txdelayed_desc; + struct ieee802154_txdesc_s *csma_desc; + + /* Radio state */ + + uint8_t chan; /* 11 to 26 for the 2.4 GHz band */ + uint8_t devmode; /* device mode: endpoint, coord, PAN coord */ + uint8_t rxmode; /* Reception mode: Normal, no CRC, promiscuous */ + + /* TX state */ + + bool txdelayed_busy; /* No CSMA transfer */ + +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + /* Superframe data */ + + struct ieee802154_superframespec_s sf; + + /* TX GTS */ + + struct ieee802154_txdesc_s *gts_desc[NRF52_GTS_SLOTS]; + bool gts_busy[NRF52_GTS_SLOTS]; +#endif +}; + +/* IEEE 802.15.4 radio device */ + +struct nrf52_radioi8_dev_s +{ + /* The public device instance - must be first */ + + struct ieee802154_radio_s macops; + + /* Registered callbacks */ + + struct ieee802154_radiocb_s *radiocb; + + /* Radio interface */ + + struct nrf52_radioi8_radio_s *radio; + + /* High resolution timer */ + + struct nrf52_radioi8_tim_s *tim; + + /* Low resolution, low power timer */ + +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + struct nrf52_radioi8_rtc_s *rtc; +#endif + + /* Radio state */ + + struct nrf52_radioi8_state_s state; + + /* Exclusive access to this struct */ + + mutex_t lock; +}; + +#endif /* __ARCH_ARM_SRC_NRF52_NRF52_IEEE802154_PRIV_H */ diff --git a/arch/arm/src/nrf52/nrf52_ieee802154_radio.c b/arch/arm/src/nrf52/nrf52_ieee802154_radio.c new file mode 100644 index 0000000000000..e4c671504d87e --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_ieee802154_radio.c @@ -0,0 +1,2116 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_ieee802154_radio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "nrf52_ieee802154_radio.h" +#include "nrf52_ieee802154_trace.h" + +#include "nrf52_ieee802154_priv.h" + +#include "hardware/nrf52_utils.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Constant from NRF52 manual */ + +#define NRF52_ED_RSSISCALE (4) + +/* ED configuration: + * - IRQ on EDEND event (sampling of energy detection complete) + * - shortcut between READY and EDSTART + * - shortcut between EDEND and DISABLE + * + * Set in nrf52_radioi8_energydetect() reset in nrf52_radioi8_isr_radio(). + * + * EDSTART task set in nrf52_radioi8_energydetect(). + */ + +#define IEEE802154_ED_INT (RADIO_INT_EDEND) +#define IEEE802154_ED_SHORTS (RADIO_SHORTS_READY_EDSTART | \ + RADIO_SHORTS_EDEND_DISABLE) + +/* RX configuration: + * - IRQ on END event (packet recveived) + * - shortcut between RXREADY and START + * - shortcut between END and DISABLE + * + * Set in nrf52_radioi8_rxenable() reset in nrf52_radioi8_rxenable(). + * + * RXEN task set in nrf52_radioi8_rxenable() and + * nrf52_radioi8_isr_radio() after RX handled and no pending ACKTX. + */ + +#define IEEE802154_RX_INT (RADIO_INT_END) +#define IEEE802154_RX_SHORTS (RADIO_SHORTS_RXREADY_START | \ + RADIO_SHORTS_END_DISABLE) + +/* NOTE: for TX we trigger interrupts on PHYEND event, not END! */ + +/* TX CCA un-slotted configuration: + * - IRQ on PHYEND event + * - IRQ on CCABUSY event + * - shortcut between TXREADY and START + * - shortcut between PHYEND and DISABLE + * - shortcut between RXREADY and CCASTART + * - shortcut between CCAIDLE and STOP + * - shortcut between CCAIDLE and TXEN + * + * Set in nrf52_radioi8_radio_norm_setup() reset in + * nrf52_radioi8_isr_radio(). + * + * CCASTART task set in nrf52_radioi8_isr_tim() when CCA transfer. + */ + +#define IEEE802154_TXCCAUNSLT_INT (RADIO_INT_PHYEND | \ + RADIO_INT_CCABUSY) +#define IEEE802154_TXCCAUNSLT_SHORTS (RADIO_SHORTS_TXREADY_START | \ + RADIO_SHORTS_PHYEND_DISABLE | \ + RADIO_SHORTS_RXREADY_CCASTART | \ + RADIO_SHORTS_CCAIDLE_STOP | \ + RADIO_SHORTS_CCAIDLE_TXEN) + +/* TX CCA slotted configuration: + * - IRQ on PHYEND event + * - IRQ on CCABUSY event + * - IRQ on CCAIDLE event + * - shortcut between TXREADY and START + * - shortcut between PHYEND and DISABLE + * + * Set in nrf52_radioi8_radio_norm_setup() reset in + * nrf52_radioi8_isr_radio(). + * + * CCASTART task set in nrf52_radioi8_isr_tim() when CCA transfer. + */ + +#define IEEE802154_TXCCASLT_INT (RADIO_INT_PHYEND | \ + RADIO_INT_CCAIDLE | \ + RADIO_INT_CCABUSY) +#define IEEE802154_TXCCASLT_SHORTS (RADIO_SHORTS_TXREADY_START | \ + RADIO_SHORTS_PHYEND_DISABLE | \ + RADIO_SHORTS_RXREADY_CCASTART) + +/* TX no-CCA configuration: + * - IRQ on PHYEND event + * - shortcut between TXREADY and START + * - shortcut between PHYEND and DISABLE + * + * Set in nrf52_radioi8_radio_norm_setup() reset in + * nrf52_radioi8_isr_radio(). + * + * TXEN task set in nrf52_radioi8_radio_norm_trigger() when non-CCA + * transfer or in nrf52_radioi8_isr_tim() for TXDELAY. + */ + +#define IEEE802154_TX_INT (RADIO_INT_PHYEND) +#define IEEE802154_TX_SHORTS (RADIO_SHORTS_TXREADY_START | \ + RADIO_SHORTS_PHYEND_DISABLE) + +/* ACK configuration: + * - IRQ on PHYEND event + * - shortcut between PHYEND and DISABLE + * + * Set in nrf52_radioi8_ack_transmit reset in nrf52_radioi8_isr_radio(). + * + * TXEN task set in nrf52_radioi8_ack_transmit(). + * START task set in nrf52_radioi8_isr_tim(). + */ + +#define IEEE802154_ACKTX_INT (RADIO_INT_PHYEND) +#define IEEE802154_ACKTX_SHORTS (RADIO_SHORTS_PHYEND_DISABLE) + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void nrf52_radioi8_rx_parse(struct nrf52_radioi8_dev_s *dev, + uint8_t *ftype, uint8_t *cmdtype); +static void nrf52_radioi8_ack_transmit(struct nrf52_radioi8_dev_s *dev); +static bool nrf52_radioi8_filter(struct nrf52_radioi8_dev_s *dev); +#if NRF52_GTS_SLOTS > 0 +static void nrf52_radioi8_gts_setup(struct nrf52_radioi8_dev_s *dev, + uint8_t fifo, struct iob_s *frame); +#endif + +/* Ops */ + +static void nrf52_radioi8_txstart(struct nrf52_radioi8_dev_s *dev); +static void nrf52_radioi8_ccastart(struct nrf52_radioi8_dev_s *dev); +static void nrf52_radioi8_notify_noack(struct nrf52_radioi8_dev_s *dev); +static int nrf52_radioi8_rxenable(struct nrf52_radioi8_dev_s *dev, + bool enable); +static int nrf52_radioi8_energydetect(struct nrf52_radioi8_dev_s *dev, + uint32_t nsymbols); +static int nrf52_radioi8_setchannel(struct nrf52_radioi8_dev_s *dev, + uint8_t chan); +static int nrf52_radioi8_setcca(struct nrf52_radioi8_dev_s *dev, + struct ieee802154_cca_s *cca); +static void nrf52_radioi8_norm_setup_buf(struct nrf52_radioi8_dev_s *dev, + uint8_t *buf, bool csma); +static void nrf52_radioi8_norm_setup(struct nrf52_radioi8_dev_s *dev, + struct iob_s *frame, bool csma); +static void nrf52_radioi8_norm_trigger(struct nrf52_radioi8_dev_s *dev); +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME +static void nrf52_radioi8_beacon_setup(struct nrf52_radioi8_dev_s *dev, + uint8_t *data, uint8_t len); +static void nrf52_radioi8_beacon_tx(struct nrf52_radioi8_dev_s *dev); +#endif +static int nrf52_radioi8_reset(struct nrf52_radioi8_radio_s *dev); +static int nrf52_radioi8_csmapoll(struct nrf52_radioi8_dev_s *dev); +static int nrf52_radioi8_gtspoll(struct nrf52_radioi8_dev_s *dev); + +/* Interrupts logic */ + +static void nrf52_radioi8_work_noack(void *arg); +static void nrf52_radioi8_work_rx(void *arg); +static void nrf52_radioi8_work_tx(void *arg); +static void nrf52_radioi8_work_busy(void *arg); +static void nrf52_radioi8_work_ed(void *arg); +static void nrf52_radioi8_state_rx(struct nrf52_radioi8_dev_s *dev); +static void nrf52_radioi8_state_tx(struct nrf52_radioi8_dev_s *dev); +static void nrf52_radioi8_state_acktx(struct nrf52_radioi8_dev_s *dev); +static void nrf52_radioi8_state_ed(struct nrf52_radioi8_dev_s *dev); +static int nrf52_radioi8_isr_radio(int irq, void *context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Packet buffers - must be byte aligned in RAM. + * + * NOTE: The first byte is PHR, the last byte is LQI. + */ + +static uint8_t aligned_data(8) + g_nrf52_radioi8_rxbuf[IEEE802154_MAX_PHY_PACKET_SIZE + 2]; + +static uint8_t aligned_data(8) + g_nrf52_radioi8_txbuf[IEEE802154_MAX_PHY_PACKET_SIZE + 2]; + +static uint8_t aligned_data(8) + g_nrf52_radioi8_ackbuf[IEEE802154_ACK_FRAME_SIZE + 1]; + +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME +static uint8_t aligned_data(8) + g_nrf52_radioi8_beaconbuf[IEEE802154_MAX_PHY_PACKET_SIZE + 2]; +#endif + +/* Radio ops */ + +static struct nrf52_radioi8_radio_ops_s g_radioi8_radio_ops = +{ + .txstart = nrf52_radioi8_txstart, + .ccastart = nrf52_radioi8_ccastart, + .notify_noack = nrf52_radioi8_notify_noack, + .rxenable = nrf52_radioi8_rxenable, + .energydetect = nrf52_radioi8_energydetect, + .setchannel = nrf52_radioi8_setchannel, + .setcca = nrf52_radioi8_setcca, + .norm_setup = nrf52_radioi8_norm_setup, + .norm_trigger = nrf52_radioi8_norm_trigger, +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + .beacon_setup = nrf52_radioi8_beacon_setup, + .beacon_tx = nrf52_radioi8_beacon_tx, +#endif + .reset = nrf52_radioi8_reset, + .csma_poll = nrf52_radioi8_csmapoll, + .gts_poll = nrf52_radioi8_gtspoll +}; + +/* Radio interface */ + +static struct nrf52_radioi8_radio_s g_radioi8_radio; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_radioi8_rx_parse + * + * Description: + * Get the RX frame type and command type if present. + * + ****************************************************************************/ + +static void nrf52_radioi8_rx_parse(struct nrf52_radioi8_dev_s *dev, + uint8_t *ftype, uint8_t *cmdtype) +{ + uint16_t *frame_ctrl = NULL; + uint8_t smode = 0; + uint8_t dmode = 0; + uint8_t panid_comp = 0; + int i = 0; + + /* Frame starts from offset 1 */ + + i = 1; + + /* Frame ctrl */ + + frame_ctrl = (uint16_t *)&dev->radio->rxbuf[i]; + i += sizeof(uint16_t); + + /* Frame seq */ + + i += 1; + + /* Return now if a given frame is not a command frame */ + + *ftype = ((*frame_ctrl & IEEE802154_FRAMECTRL_FTYPE) >> + IEEE802154_FRAMECTRL_SHIFT_FTYPE); + if (*ftype != IEEE802154_FRAME_COMMAND) + { + return; + } + + /* Now we have to find the offset for the frame command type */ + + smode = ((*frame_ctrl & IEEE802154_FRAMECTRL_SADDR) >> + IEEE802154_FRAMECTRL_SHIFT_SADDR); + + dmode = ((*frame_ctrl & IEEE802154_FRAMECTRL_DADDR) >> + IEEE802154_FRAMECTRL_SHIFT_DADDR); + + panid_comp = ((*frame_ctrl & IEEE802154_FRAMECTRL_PANIDCOMP) >> + IEEE802154_FRAMECTRL_SHIFT_PANIDCOMP); + + if (dmode != IEEE802154_ADDRMODE_NONE) + { + i += IEEE802154_PANIDSIZE; + + if (dmode == IEEE802154_ADDRMODE_SHORT) + { + i += IEEE802154_SADDRSIZE; + } + else if (dmode == IEEE802154_ADDRMODE_EXTENDED) + { + i += IEEE802154_EADDRSIZE; + } + } + + if (smode != IEEE802154_ADDRMODE_NONE) + { + if (!panid_comp) + { + i += IEEE802154_PANIDSIZE; + } + + if (smode == IEEE802154_ADDRMODE_SHORT) + { + i += IEEE802154_SADDRSIZE; + } + else if (smode == IEEE802154_ADDRMODE_EXTENDED) + { + i += IEEE802154_EADDRSIZE; + } + } + + *cmdtype = dev->radio->rxbuf[i]; +} + +/**************************************************************************** + * Name: nrf52_radioi8_ack_transmit + * + * Description: + * Transmit ACK. + * + ****************************************************************************/ + +static void nrf52_radioi8_ack_transmit(struct nrf52_radioi8_dev_s *dev) +{ + struct nrf52_radio_dev_s *lower = NULL; + uint8_t *ackbuf = dev->radio->ackbuf; + uint32_t regval = 0; + uint8_t ftype = 0; + uint8_t cmdtype = 0; + bool pending = false; + + DEBUGASSERT(dev); + lower = dev->radio->lower; + + /* Restore RX after ACK - we already are in DISABLE state so no need to + * disable RX + */ + + if (dev->radio->state.rxenabled) + { + dev->radio->state.rxrestore = true; + } + + /* Clear events */ + + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_READY_OFFSET, 0); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_TXREADY_OFFSET, 0); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_RXREADY_OFFSET, 0); + + /* Fill ACK buffer */ + + ackbuf[0] = IEEE802154_ACK_FRAME_SIZE; + ackbuf[1] = 0x02; + ackbuf[2] = 0; + ackbuf[3] = dev->radio->rxbuf[3]; + + /* Get RX frame type */ + + nrf52_radioi8_rx_parse(dev, &ftype, &cmdtype); + + /* If this is ACK for Data Request command - set frame pending flag */ + + if (dev->state.devmode != NRF52_DEVMODE_ENDPOINT && + ftype == IEEE802154_FRAME_COMMAND && + cmdtype == IEEE802154_CMD_DATA_REQ) + { + pending = true; + } + + /* Set frame pedning flag for this ACK */ + + if (pending) + { + ackbuf[1] |= 0x10; + } + + /* Configure shorts and interrupts */ + + NRF52_RADIO_SHRTSET(lower, IEEE802154_ACKTX_SHORTS); + NRF52_RADIO_INTEN(lower, IEEE802154_ACKTX_INT); + + /* Set packet pointer - buffer must be aligned */ + + regval = (uint32_t)ackbuf; + DEBUGASSERT(nrf52_easydma_valid(regval)); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_PACKETPTR_OFFSET, regval); + + /* Set state to ACK */ + + dev->radio->state.state = NRF52_RADIO_STATE_ACKTX; + + /* Enable TX - start TX is called from timer interrupt */ + + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_TASKS_TXEN_OFFSET, 1); + + /* Run TIMER - TX is handled in timer isr */ + + nrf52_radioi8_trace_put(RADIO_TRACE_ACKTX, pending); + dev->tim->ops->setup(dev, NRF52_TIMER_CHAN_ACK, IEEE802154_ACKIFS_SYMBOLS); +} + +/**************************************************************************** + * Name: nrf52_radioi8_filter + * + * Description: + * Filter received frames. + * + ****************************************************************************/ + +static bool nrf52_radioi8_filter(struct nrf52_radioi8_dev_s *dev) +{ + struct ieee802154_addr_s addr; + uint8_t *rx = &dev->radio->rxbuf[1]; + uint16_t *fc = (uint16_t *)&rx[0]; + + /* Promiscuous mode */ + + if (dev->state.rxmode == NRF52_RXMODE_PROMISC) + { + return true; + } + + /* Beacon frame */ + + if (((*fc & IEEE802154_FRAMECTRL_FTYPE) == IEEE802154_FRAME_BEACON) && + IEEE802154_PANIDCMP(IEEE802154_PANID_UNSPEC, &dev->state.addr.panid)) + { + return true; + } + + /* Get destination address */ + + IEEE802154_PANIDCOPY(addr.panid, &rx[3]); + addr.mode = ((*fc & IEEE802154_FRAMECTRL_DADDR) >> + IEEE802154_FRAMECTRL_SHIFT_DADDR); + if (addr.mode == IEEE802154_ADDRMODE_SHORT) + { + IEEE802154_SADDRCOPY(addr.saddr, &rx[5]); + } + else if (addr.mode == IEEE802154_ADDRMODE_EXTENDED) + { + IEEE802154_EADDRCOPY(addr.eaddr, &rx[5]); + } + + /* PAN ID match */ + + if (!IEEE802154_PANIDCMP(IEEE802154_PANID_UNSPEC, dev->state.addr.panid) && + !IEEE802154_PANIDCMP(addr.panid, &dev->state.addr.panid)) + { + return false; + } + + /* Destination address match */ + + if (addr.mode == IEEE802154_ADDRMODE_SHORT) + { + if (IEEE802154_SADDRCMP(addr.saddr, + &dev->state.addr.saddr)) + { + return true; + } + + else if (IEEE802154_SADDRCMP(addr.saddr, + IEEE802154_SADDR_UNSPEC)) + { + return true; + } + } + else if (addr.mode == IEEE802154_ADDRMODE_EXTENDED) + { + if (IEEE802154_EADDRCMP(addr.eaddr, + &dev->state.addr.eaddr)) + { + return true; + } + + else if (IEEE802154_EADDRCMP(addr.eaddr, + IEEE802154_EADDR_UNSPEC)) + { + return true; + } + } + + /* Otherwise drop this frame */ + + return false; +} + +#if NRF52_GTS_SLOTS > 0 +/**************************************************************************** + * Name: nrf52_radioi8_gts_setup + * + * Description: + * Setup a GTS transaction. + * + ****************************************************************************/ + +static void nrf52_radioi8_gts_setup(struct nrf52_radioi8_dev_s *dev, + uint8_t fifo, struct iob_s *frame) +{ + /* Missing logic */ + + ASSERT(0); +} + +/**************************************************************************** + * Name: nrf52_radioi8_dopoll_gts + * + * Description: + * This function is called in order to perform an out-of-sequence TX poll. + * + ****************************************************************************/ + +static void nrf52_radioi8_dopoll_gts(void *arg) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)arg; + int gts = 0; + int len = 0; + + /* Get exclusive access to the driver */ + + while (nxmutex_lock(&dev->lock) < 0) + { + } + + for (gts = 0; gts < NRF52_GTS_SLOTS; gts++) + { + if (!dev->state.gts_busy[gts]) + { + len = dev->radiocb->poll(dev->radiocb, true, + &dev->state.gts_desc[gts]); + + if (len > 0) + { + /* Now the txdesc is in use */ + + dev->state.gts_busy[gts] = 1; + + /* Setup the GTS transaction */ + + nrf52_radioi8_gts_setup(dev, gts, + dev->state.gts_desc[gts]->frame); + } + } + } + + nxmutex_unlock(&dev->lock); +} +#endif /* NRF52_GTS_SLOTS > 0 */ + +/**************************************************************************** + * Name: nrf52_radioi8_txstart + * + * Description: + * Start transmition, TX must be armed (TXEN must be set). + * + ****************************************************************************/ + +static void nrf52_radioi8_txstart(struct nrf52_radioi8_dev_s *dev) +{ + struct nrf52_radio_dev_s *lower = NULL; + + DEBUGASSERT(dev); + lower = dev->radio->lower; + + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_TASKS_START_OFFSET, 1); +} + +/**************************************************************************** + * Name: nrf52_radioi8_ccastart + * + * Description: + * Start CCA, RX must be armed (RXEN must be set). + * + ****************************************************************************/ + +static void nrf52_radioi8_ccastart(struct nrf52_radioi8_dev_s *dev) +{ + struct nrf52_radio_dev_s *lower = NULL; + + DEBUGASSERT(dev); + lower = dev->radio->lower; + + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_TASKS_CCASTART_OFFSET, 1); +} + +/**************************************************************************** + * Name: nrf52_radioi8_notify_noack + * + * Description: + * Notify Radio layer about noack event. + * + ****************************************************************************/ + +static void nrf52_radioi8_notify_noack(struct nrf52_radioi8_dev_s *dev) +{ + /* If flag is set - no ACK was received */ + + if (dev->radio->state.waitack == true) + { + /* Notify MAC layer */ + + DEBUGASSERT(work_available(&dev->radio->noackwork)); + work_queue(HPWORK, &dev->radio->noackwork, + nrf52_radioi8_work_noack, (void *)dev, 0); + + /* Clear flag */ + + dev->radio->state.waitack = false; + } +} + +/**************************************************************************** + * Name: nrf52_radioi8_rxenable + * + * Description: + * Enable/Disable receiver. + * + ****************************************************************************/ + +static int nrf52_radioi8_rxenable(struct nrf52_radioi8_dev_s *dev, + bool enable) +{ + struct nrf52_radio_dev_s *lower = NULL; + uint32_t regval = 0; + + DEBUGASSERT(dev); + lower = dev->radio->lower; + + if (enable) + { + nrf52_radioi8_trace_put(RADIO_TRACE_RXENABLE, 0); + + /* Clear events */ + + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_END_OFFSET, 0); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_READY_OFFSET, 0); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_PHYEND_OFFSET, 0); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_TXREADY_OFFSET, 0); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_RXREADY_OFFSET, 0); + + /* Configure shorts and interrupts */ + + NRF52_RADIO_SHRTSET(lower, IEEE802154_RX_SHORTS); + NRF52_RADIO_INTEN(lower, IEEE802154_RX_INT); + + /* Set packet pointer - buffer must be aligned */ + + regval = (uint32_t)dev->radio->rxbuf; + DEBUGASSERT(nrf52_easydma_valid(regval)); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_PACKETPTR_OFFSET, regval); + + /* Set state to RX */ + + dev->radio->state.state = NRF52_RADIO_STATE_RX; + + /* Start RX */ + + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_TASKS_RXEN_OFFSET, 1); + } + else + { + nrf52_radioi8_trace_put(RADIO_TRACE_RXDISABLE, 0); + + /* Disalbe interrups and shorts */ + + NRF52_RADIO_INTCLR(lower, IEEE802154_RX_INT); + NRF52_RADIO_SHRTSET(lower, 0); + + /* Disable RX */ + + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_TASKS_DISABLE_OFFSET, 1); + } + + /* Store state */ + + dev->radio->state.rxenabled = enable; + + /* Data returned by callback in ISR */ + + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_energydetect + * + * Description: + * Start the energy detect measurement. + * + ****************************************************************************/ + +static int nrf52_radioi8_energydetect(struct nrf52_radioi8_dev_s *dev, + uint32_t nsymbols) +{ + struct nrf52_radio_dev_s *lower = NULL; + + DEBUGASSERT(dev); + lower = dev->radio->lower; + + /* Clear events */ + + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_EDEND_OFFSET, 0); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_READY_OFFSET, 0); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_RXREADY_OFFSET, 0); + + /* Configure shortucts and interrupts */ + + NRF52_RADIO_SHRTSET(lower, IEEE802154_ED_SHORTS); + NRF52_RADIO_INTEN(lower, IEEE802154_ED_INT); + + /* Configure ED symbols */ + + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EDCNT_OFFSET, nsymbols); + + /* Set state to ENERGY_DETECT (ED) */ + + dev->radio->state.state = NRF52_RADIO_STATE_ED; + + /* Start RX */ + + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_TASKS_RXEN_OFFSET, 1); + + /* Data returned by callback in ISR */ + + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_setchannel + * + * Description: + * Define the current radio channel the device is operating on. + * + ****************************************************************************/ + +static int nrf52_radioi8_setchannel(struct nrf52_radioi8_dev_s *dev, + uint8_t chan) +{ + struct nrf52_radio_dev_s *lower = NULL; + uint32_t freq = 2405 + 5 * (chan - 11); + + DEBUGASSERT(dev); + lower = dev->radio->lower; + + return NRF52_RADIO_FREQSET(lower, freq); +} + +/**************************************************************************** + * Name: nrf52_radioi8_setcca + * + * Description: + * Configure the Clear Channel Assessement. + * + ****************************************************************************/ + +static int nrf52_radioi8_setcca(struct nrf52_radioi8_dev_s *dev, + struct ieee802154_cca_s *cca) +{ + struct nrf52_radio_dev_s *lower = NULL; + struct nrf52_radio_cca_s c; + + DEBUGASSERT(dev); + lower = dev->radio->lower; + + /* Fill radio sturcture */ + + memset(&c, 0, sizeof(struct nrf52_radio_cca_s)); + + if (cca->use_ed && !cca->use_cs) + { + c.mode = NRF52_RADIO_CCA_ED; + } + else if (~cca->use_ed && cca->use_cs) + { + c.mode = NRF52_RADIO_CCA_CARRIER; + } + else if (cca->use_ed && cca->use_cs) + { + c.mode = NRF52_RADIO_CCA_CARRIER_AND_ED; + } + + c.edthres = cca->edth; + c.corrthres = cca->csth; + c.corrcnt = 5; + + /* Configure radio */ + + NRF52_RADIO_CCACFG(lower, &c); + + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_norm_setup_buf + * + * Description: + * Setup a normal transaction (non GTS) from buffer. + * + ****************************************************************************/ + +static void nrf52_radioi8_norm_setup_buf(struct nrf52_radioi8_dev_s *dev, + uint8_t *buf, bool csma) +{ + struct nrf52_radio_dev_s *lower = NULL; + uint32_t regval = 0; + + DEBUGASSERT(dev); + lower = dev->radio->lower; + + nrf52_radioi8_trace_put(RADIO_TRACE_CSMASETUP, csma); + + /* If RX is enabled - we have to temporarly disable it */ + + if (dev->radio->state.rxenabled) + { + dev->macops.rxenable((struct ieee802154_radio_s *)dev, false); + + /* Restore RX after TX completed */ + + dev->radio->state.rxrestore = true; + } + + /* Set packet pointer - buffer must be aligned */ + + regval = (uint32_t)buf; + DEBUGASSERT(nrf52_easydma_valid(regval)); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_PACKETPTR_OFFSET, regval); + + if (csma) + { + /* Clear events */ + + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_END_OFFSET, 0); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_READY_OFFSET, 0); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_PHYEND_OFFSET, 0); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_TXREADY_OFFSET, 0); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_CCABUSY_OFFSET, 0); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_CCAIDLE_OFFSET, 0); + + /* Configure shorts and interrupts */ + + if (dev->radio->state.slotted) + { +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + NRF52_RADIO_SHRTSET(lower, IEEE802154_TXCCASLT_SHORTS); + NRF52_RADIO_INTEN(lower, IEEE802154_TXCCASLT_INT); +#else + ASSERT(0); +#endif + } + else + { + NRF52_RADIO_SHRTSET(lower, IEEE802154_TXCCAUNSLT_SHORTS); + NRF52_RADIO_INTEN(lower, IEEE802154_TXCCAUNSLT_INT); + } + + dev->radio->state.state = NRF52_RADIO_STATE_TX_CSMA; + } + else + { + /* Clear events */ + + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_END_OFFSET, 0); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_READY_OFFSET, 0); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_PHYEND_OFFSET, 0); + + /* Configure shorts and interrupts */ + + NRF52_RADIO_SHRTSET(lower, IEEE802154_TX_SHORTS); + NRF52_RADIO_INTEN(lower, IEEE802154_TX_INT); + dev->radio->state.state = NRF52_RADIO_STATE_TX_NOCSMA; + } +} + +/**************************************************************************** + * Name: nrf52_radioi8_norm_setup + * + * Description: + * Setup a normal transaction (non GTS). + * + ****************************************************************************/ + +static void nrf52_radioi8_norm_setup(struct nrf52_radioi8_dev_s *dev, + struct iob_s *frame, bool csma) +{ + /* The first byte in TX buffer is PHR */ + + dev->radio->txbuf[0] = frame->io_len; + + /* Allocate space for CRC */ + + dev->radio->txbuf[0] += 2; + + /* Copy frame to RX buffer - we must send from aligned buffer */ + + memcpy(&dev->radio->txbuf[1], &frame->io_data[0], frame->io_len); + + /* Setup buffer */ + + nrf52_radioi8_norm_setup_buf(dev, dev->radio->txbuf, csma); +} + +/**************************************************************************** + * Name: nrf52_radioi8_trg_csma + * + * Description: + * Trigger transaction with CSMA-CA. + * + ****************************************************************************/ + +static void nrf52_radioi8_trg_csma(struct nrf52_radioi8_dev_s *dev) +{ + uint32_t delay = 0; + + /* Set state to TX */ + + dev->radio->state.state = NRF52_RADIO_STATE_TX; + + /* Need slotted CSMA-CA */ + + if (dev->radio->state.slotted) + { +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + if (!dev->radio->state.csma_busy) + { + /* Initial backoff state */ + + dev->radio->state.NB = 0; + dev->radio->state.CW = IEEE802154_CW0; + } + + /* Battery life extension */ + + if (dev->radio->state.ble) + { + dev->radio->state.BE = MIN(2, dev->radio->state.min_be); + } + else + { + dev->radio->state.BE = dev->radio->state.min_be; + } + + /* Get random unit backoff period delay */ + + delay = rand() % ((1 << dev->radio->state.BE) - 1); + + /* TODO: + * - locate backoff period boundary + * - perform CCA on backoff period boundary + */ + + ASSERT(0); +#else + ASSERT(0); +#endif + } + + /* Need un-slotted CSMA-CA */ + + else + { + if (!dev->radio->state.csma_busy) + { + /* Initial backoff state */ + + dev->radio->state.NB = 0; + dev->radio->state.BE = dev->radio->state.min_be; + } + + /* Get random unit backoff period delay */ + + delay = rand() % ((1 << dev->radio->state.BE) - 1); + } + + /* CSMA is in use */ + + dev->radio->state.csma_busy = true; + nrf52_radioi8_trace_put(RADIO_TRACE_CSMATRIGGER, delay); + + dev->tim->ops->setup(dev, NRF52_TIMER_CHAN_CSMADELAY, + delay * IEEE802154_UNIT_BACKOFF_PERIOD); +} + +/**************************************************************************** + * Name: nrf52_radioi8_trg_nocsma + * + * Description: + * Trigger transaction without CSMA-CA; + * + ****************************************************************************/ + +static void nrf52_radioi8_trg_nocsma(struct nrf52_radioi8_dev_s *dev) +{ + struct nrf52_radio_dev_s *lower = NULL; + + DEBUGASSERT(dev); + lower = dev->radio->lower; + + /* Set state to TX */ + + dev->radio->state.state = NRF52_RADIO_STATE_TX; + + /* Start TX - we transmit immediately */ + + nrf52_radioi8_trace_put(RADIO_TRACE_NOCSMATRIGGER, + dev->radio->state.state); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_TASKS_TXEN_OFFSET, 1); +} + +/**************************************************************************** + * Name: nrf52_radioi8_norm_trigger + * + * Description: + * Trigger normal transaction (non GTS). + * + ****************************************************************************/ + +static void nrf52_radioi8_norm_trigger(struct nrf52_radioi8_dev_s *dev) +{ + /* Wait for ACK */ + + if (dev->radio->txbuf[1] & IEEE802154_FRAMECTRL_ACKREQ) + { + dev->radio->state.waitack = true; + } + + /* CSMA transmition */ + + if (dev->radio->state.state == NRF52_RADIO_STATE_TX_CSMA) + { + nrf52_radioi8_trg_csma(dev); + } + + /* No-CSMA transmition */ + + else if (dev->radio->state.state == NRF52_RADIO_STATE_TX_NOCSMA) + { + nrf52_radioi8_trg_nocsma(dev); + } + + /* Invalid state */ + + else + { + /* We should not be there */ + + DEBUGASSERT(0); + } +} + +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME +/**************************************************************************** + * Name: nrf52_radioi8_beacon_setup + * + * Description: + * Setup a beacon frame transfer + * + ****************************************************************************/ + +static void nrf52_radioi8_beacon_setup(struct nrf52_radioi8_dev_s *dev, + uint8_t *data, uint8_t len) +{ + /* Set beacon TX buffer */ + + memcpy(&dev->radio->beaconbuf[1], data, len); + + /* Length = Frame data + CRC */ + + dev->radio->beaconbuf[0] = len + 2; +} + +/**************************************************************************** + * Name: nrf52_radioi8_beacon_tx + * + * Description: + * Transmit a beacon frame (non CSMA-CA transfer). + * + ****************************************************************************/ + +static void nrf52_radioi8_beacon_tx(struct nrf52_radioi8_dev_s *dev) +{ + /* Beacon buffer is ready to send - transmit as non CSMA-CA */ + + nrf52_radioi8_norm_setup_buf(dev, dev->radio->beaconbuf, false); + + /* Send now */ + + nrf52_radioi8_norm_trigger(dev); +} +#endif + +/**************************************************************************** + * Name: nrf52_radioi8_reset + * + * Description: + * Reset radio state to work with IEEE 802.15.4. + * + ****************************************************************************/ + +static int nrf52_radioi8_reset(struct nrf52_radioi8_radio_s *dev) +{ + struct nrf52_radio_dev_s *radio = NULL; + struct nrf52_radio_crc_s crc; + struct nrf52_radio_pktcfg_s pcfg; + int ret = OK; + + DEBUGASSERT(dev); + radio = dev->lower; + + /* Reset radio state */ + + memset(&dev->state, 0, sizeof(struct nrf52_radioi8_radio_data_s)); + + /* Reset radio */ + + NRF52_RADIO_RESET(radio); + + /* MAC prameters */ + + dev->state.max_frame_waittime = IEEE802154_MAX_FRAME_WAITTIME; + dev->state.max_csma_backoffs = IEEE802154_MAX_CSMA_BACKOFFS; + dev->state.min_be = IEEE802154_MIN_BE; + dev->state.max_be = IEEE802154_MAX_BE; + + /* Set radio IEEE 802.15.4 mode */ + + ret = NRF52_RADIO_MODESET(radio, NRF52_RADIO_MODE_IEEE802154); + if (ret < 0) + { + goto errout; + } + + /* Configure CRC */ + + crc.len = 2; + crc.skip = NRF52_RADIO_CRC_SKIPADDR_IEEE802154; + crc.poly = 0x011021; + crc.init = 0; + + ret = NRF52_RADIO_CRCCFG(radio, &crc); + if (ret < 0) + { + goto errout; + } + + /* Configure packet for IEEE 802.15.4 mode */ + + pcfg.max_len = IEEE802154_MAX_PHY_PACKET_SIZE; + pcfg.stat_len = 0; + pcfg.bal_len = 0; + pcfg.lf_len = 8; + pcfg.s0_len = 0; + pcfg.s1_len = 0; + pcfg.ci_len = 0; + pcfg.pl_len = NRF52_RADIO_PREAMBLE_32BITZERO; + pcfg.term_len = 0; + pcfg.crcinc = true; + pcfg.endian = false; + pcfg.whiteen = false; + + ret = NRF52_RADIO_PKTCFG(radio, &pcfg); + if (ret < 0) + { + goto errout; + } + + /* Disable hardware TIFS */ + + NRF52_RADIO_PUTREG(radio, NRF52_RADIO_MODECNF0_OFFSET, + RADIO_MODECNF0_RU); + + /* Set TX power */ + + NRF52_RADIO_TXPWRSET(radio, 0); + + /* TODO: Configure LNA/PA */ + +errout: + return ret; +} + +/**************************************************************************** + * Name: nrf52_radioi8_dopoll_csma + * + * Description: + * Out-of-sequence TX poll. + * + ****************************************************************************/ + +void nrf52_radioi8_dopoll_csma(void *arg) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)arg; + int len = 0; + + /* Get exclusive access to the driver */ + + while (nxmutex_lock(&dev->lock) < 0) + { + } + + /* If this a CSMA transaction and we have room in the CSMA */ + + if (!dev->radio->state.csma_busy) + { + wlinfo("Polling for frame\n"); + len = dev->radiocb->poll(dev->radiocb, false, &dev->state.csma_desc); + + if (len > 0) + { + wlinfo("Frame received. Frame length: %d\n", len); + + /* Setup the CSMA transaction */ + + dev->radio->ops->norm_setup(dev, dev->state.csma_desc->frame, + true); + dev->radio->ops->norm_trigger(dev); + } + } + + nxmutex_unlock(&dev->lock); +} + +/**************************************************************************** + * Name: nrf52_radioi8_csmapoll + * + * Description: + * Handle CSMA poll. + * + ****************************************************************************/ + +static int nrf52_radioi8_csmapoll(struct nrf52_radioi8_dev_s *dev) +{ + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&dev->radio->csma_pollwork)) + { + /* Schedule to serialize the poll on the worker thread. */ + + work_queue(HPWORK, &dev->radio->csma_pollwork, + nrf52_radioi8_dopoll_csma, dev, 0); + } + + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_gtspoll + * + * Description: + * Handle GTS poll. + * + ****************************************************************************/ + +static int nrf52_radioi8_gtspoll(struct nrf52_radioi8_dev_s *dev) +{ +#if NRF52_GTS_SLOTS > 0 + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&dev->radio->gts_pollwork)) + { + /* Schedule to serialize the poll on the worker thread. */ + + work_queue(HPWORK, &dev->radio->gts_pollwork, + nrf52_radioi8_dopoll_gts, dev, 0); + } + + return OK; +#else + /* GTS not supported */ + + return -ENOTSUP; +#endif +} + +/**************************************************************************** + * Name: nrf52_radioi8_work_noack + * + * Description: + * Handle no ACK work. + * + ****************************************************************************/ + +static void nrf52_radioi8_work_noack(void *arg) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)arg; + struct nrf52_radio_dev_s *lower = NULL; + struct ieee802154_txdesc_s *tx = NULL; + bool *busy = NULL; + bool csma = false; + + DEBUGASSERT(dev); + lower = dev->radio->lower; + + nrf52_radioi8_trace_put(RADIO_TRACE_WORK_NOACK, 0); + + /* Get exclusive access to the driver */ + + while (nxmutex_lock(&dev->lock) < 0) + { + } + + if (dev->state.txdelayed_busy) + { + tx = dev->state.txdelayed_desc; + busy = &dev->state.txdelayed_busy; + csma = false; + } + else + { + tx = dev->state.csma_desc; + busy = &dev->radio->state.csma_busy; + csma = true; + } + + if (tx->retrycount > 0) + { + /* Disable RX */ + + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_TASKS_DISABLE_OFFSET, 1); + + /* Try again */ + + tx->retrycount -= 1; + nrf52_radioi8_trace_put(RADIO_TRACE_TXRETRY, tx->retrycount); + nrf52_radioi8_norm_setup(dev, tx->frame, csma); + nrf52_radioi8_norm_trigger(dev); + } + else + { + nrf52_radioi8_trace_put(RADIO_TRACE_NOACK, 0); + + tx->conf->status = IEEE802154_STATUS_NO_ACK; + tx->framepending = false; + dev->radiocb->txdone(dev->radiocb, tx); + *busy = false; + } + + /* Unlock the radio device */ + + nxmutex_unlock(&dev->lock); +} + +/**************************************************************************** + * Name: nrf52_radioi8_work_irq + * + * Description: + * Handle RX work. + * + ****************************************************************************/ + +static void nrf52_radioi8_work_rx(void *arg) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)arg; + struct nrf52_radio_dev_s *lower = NULL; + struct ieee802154_primitive_s *prim = NULL; + struct ieee802154_data_ind_s *ind = NULL; + uint8_t index = 0; + bool crcok = false; + + DEBUGASSERT(dev); + lower = dev->radio->lower; + + nrf52_radioi8_trace_put(RADIO_TRACE_WORK_RX, 0); + + /* Get exclusive access to the driver */ + + while (nxmutex_lock(&dev->lock) < 0) + { + } + + /* Check CRC */ + + crcok = NRF52_RADIO_GETREG(lower, NRF52_RADIO_CRCSTATUS_OFFSET); + if (dev->state.rxmode != NRF52_RXMODE_NOCRC && crcok == false) + { + goto out; + } + + /* Allocate a data_ind to put the frame in */ + + prim = ieee802154_primitive_allocate(); + ind = (struct ieee802154_data_ind_s *)prim; + if (ind == NULL) + { + wlerr("ERROR: Unable to allocate data_ind. Discarding frame\n"); + goto out; + } + + prim->type = IEEE802154_PRIMITIVE_IND_DATA; + + /* Allocate an IOB to put the frame into */ + + ind->frame = iob_alloc(false); + DEBUGASSERT(ind->frame != NULL); + + /* First byte is the PHR */ + + ind->frame->io_len = dev->radio->rxbuf[0]; + + /* Reduce len by 2, we only receive frames with correct crc, no check + * required. + */ + + ind->frame->io_len -= 2; + + for (index = 0; index < ind->frame->io_len; index++) + { + ind->frame->io_data[index] = dev->radio->rxbuf[index + 1]; + } + + /* Set CRC fields to 0 */ + + ind->frame->io_data[index + 1] = 0; + ind->frame->io_data[index + 2] = 0; + + /* LQI is the last byte in RAM */ + + ind->lqi = dev->radio->rxbuf[index + 1]; + + /* RSSI is non-standard field and is not supported here. + * TODO: get RSSI from LQI ? + */ + + ind->rssi = 0; + + /* Callback the receiver in the next highest layer */ + + dev->radiocb->rxframe(dev->radiocb, ind); + +out: + + /* Re-Enable RX if not handling ACK TX now */ + + if (dev->radio->state.state != NRF52_RADIO_STATE_ACKTX) + { + /* Enable packet reception */ + + dev->macops.rxenable((struct ieee802154_radio_s *)dev, true); + } + + /* Unlock the radio device */ + + nxmutex_unlock(&dev->lock); +} + +/**************************************************************************** + * Name: nrf52_radioi8_work_tx + * + * Description: + * Handle TX work. + * + ****************************************************************************/ + +static void nrf52_radioi8_work_tx(void *arg) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)arg; + enum ieee802154_status_e status; + bool fpending = false; + + nrf52_radioi8_trace_put(RADIO_TRACE_WORK_TX, 0); + + /* Get exclusive access to the driver */ + + while (nxmutex_lock(&dev->lock) < 0) + { + } + + /* Get frame pending flag from the last TX ACK */ + + fpending = dev->radio->state.framepending; + dev->radio->state.framepending = false; + + status = IEEE802154_STATUS_SUCCESS; + + if (dev->state.txdelayed_busy) + { + /* Inform the next layer of the transmission success/failure */ + + dev->state.txdelayed_desc->conf->status = status; + dev->state.txdelayed_desc->framepending = fpending; + dev->radiocb->txdone(dev->radiocb, dev->state.txdelayed_desc); + dev->state.txdelayed_desc = NULL; + dev->state.txdelayed_busy = false; + } + else + { + /* Inform the next layer of the transmission success/failure */ + + dev->state.csma_desc->conf->status = status; + dev->state.csma_desc->framepending = fpending; + dev->radiocb->txdone(dev->radiocb, dev->state.csma_desc); + dev->state.csma_desc = NULL; + + /* We are now done with the transaction */ + + dev->radio->state.csma_busy = false; + + /* Must unlock the radio before calling poll */ + + nxmutex_unlock(&dev->lock); + nrf52_radioi8_dopoll_csma(dev); + while (nxmutex_lock(&dev->lock) < 0) + { + } + } + + /* Re-Enable RX if not handling ACK TX now */ + + if (dev->radio->state.state != NRF52_RADIO_STATE_ACKTX) + { + /* Enable packet reception */ + + dev->macops.rxenable((struct ieee802154_radio_s *)dev, true); + } + + /* Unlock the radio device */ + + nxmutex_unlock(&dev->lock); +} + +/**************************************************************************** + * Name: nrf52_radioi8_work_busy + * + * Description: + * Handle CCABUSY work. + * + ****************************************************************************/ + +static void nrf52_radioi8_work_busy(void *arg) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)arg; + + nrf52_radioi8_trace_put(RADIO_TRACE_WORK_BUSY, 0); + + /* Get exclusive access to the driver */ + + while (nxmutex_lock(&dev->lock) < 0) + { + } + + dev->state.txdelayed_desc->conf->status = + IEEE802154_STATUS_CHANNEL_ACCESS_FAILURE; + + dev->radiocb->txdone(dev->radiocb, dev->state.txdelayed_desc); + + /* Unlock the radio device */ + + nxmutex_unlock(&dev->lock); +} + +/**************************************************************************** + * Name: nrf52_radioi8_work_ed + * + * Description: + * Handle ED work. + * + ****************************************************************************/ + +static void nrf52_radioi8_work_ed(void *arg) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)arg; + struct nrf52_radio_dev_s *lower = NULL; + int ed = 0; + + DEBUGASSERT(dev); + lower = dev->radio->lower; + + nrf52_radioi8_trace_put(RADIO_TRACE_WORK_ED, 0); + + /* Get result */ + + ed = NRF52_RADIO_GETREG(lower, NRF52_RADIO_EDSAMPLE_OFFSET); + + /* Convert to IEEE 802.15.4 scale */ + + ed = ((ed > 63) ? 255: (ed * NRF52_ED_RSSISCALE)); + + /* Callback the receiver in the next highest layer */ + + dev->radiocb->edresult(dev->radiocb, ed); +} + +/**************************************************************************** + * Name: nrf52_radioi8_state_rx + * + * Description: + * Handle radio interrupt for RX state. + * + ****************************************************************************/ + +static void nrf52_radioi8_state_rx(struct nrf52_radioi8_dev_s *dev) +{ + uint8_t *rxbuf = dev->radio->rxbuf; + + /* Frame filter */ + + if (dev->radio->state.waitack == false) + { + if (!nrf52_radioi8_filter(dev)) + { + nrf52_radioi8_trace_put(RADIO_TRACE_DROPFRAME, 0); + + /* Enable RX and ignore this frame */ + + dev->macops.rxenable((struct ieee802154_radio_s *)dev, + true); + return; + } + } + +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + /* TODO: resync with beacon ? */ + + if (dev->radio->state.wait_for_beacon == true) + { + uint16_t *fc = (uint16_t *)&rxbuf[0]; + + /* TODO: NOT TESTES, should we check panid here ? */ + + if (((*fc & IEEE802154_FRAMECTRL_FTYPE) == IEEE802154_FRAME_BEACON) && + IEEE802154_PANIDCMP(IEEE802154_PANID_UNSPEC, + &dev->state.addr.panid)) + { + /* Start RTC */ + + dev->rtc->ops->start(dev); + + dev->radio->state.wait_for_beacon = false; + } + } +#endif + + /* Start ACK handling now - this must be done in isr */ + + if (dev->state.rxmode == NRF52_RXMODE_NORMAL && + rxbuf[1] & IEEE802154_FRAMECTRL_ACKREQ && + rxbuf[0] != IEEE802154_ACK_FRAME_SIZE) + { + nrf52_radioi8_ack_transmit(dev); + } + + /* Store RX frame long flag */ + + dev->radio->state.rxlong = rxbuf[0] > 18 ? true : false; + + /* We don't wait for TX ACK - forward this frame to MAC */ + + if (dev->radio->state.waitack == false) + { + nrf52_radioi8_trace_put(RADIO_TRACE_IRQ_RXDONE, 0); + + /* Receive DONE */ + + if (work_available(&dev->radio->irqwork)) + { + work_queue(HPWORK, &dev->radio->irqwork, + nrf52_radioi8_work_rx, (void *)dev, 0); + } + } + + /* We wait for TX ACK and this frame is ACK - confirm TX to MAC */ + + else if (rxbuf[0] == IEEE802154_ACK_FRAME_SIZE && + dev->radio->state.waitack == true) + { + nrf52_radioi8_trace_put(RADIO_TRACE_IRQ_RXACKDONE, 0); + + /* ACK frame received */ + + dev->radio->state.waitack = false; + + /* Get frame pedning flag */ + + dev->radio->state.framepending = rxbuf[1] & 0x10; + + /* Clear timer */ + + dev->tim->ops->stop(dev); + + /* This is ACK - notify MAC that TX complete */ + + if (work_available(&dev->radio->irqwork)) + { + work_queue(HPWORK, &dev->radio->irqwork, + nrf52_radioi8_work_tx, (void *)dev, 0); + } + } + + /* We wait for TX ACK and this is not ACK - notify TX failure */ + + else + { + /* Clear flag */ + + dev->radio->state.waitack = false; + + /* And notify MAC */ + + DEBUGASSERT(work_available(&dev->radio->noackwork)); + work_queue(HPWORK, &dev->radio->noackwork, + nrf52_radioi8_work_noack, (void *)dev, 0); + } +} + +/**************************************************************************** + * Name: nrf52_radioi8_state_tx + * + * Description: + * Handle radio interrupt for TX state. + * + ****************************************************************************/ + +static void nrf52_radioi8_state_tx(struct nrf52_radioi8_dev_s *dev) +{ + struct nrf52_radio_dev_s *lower = NULL; + + DEBUGASSERT(dev); + lower = dev->radio->lower; + + if (dev->radio->state.waitack == true) + { + nrf52_radioi8_trace_put(RADIO_TRACE_IRQ_WAITACK, 0); + + /* Start timer and wait for ACK */ + + dev->tim->ops->setup(dev, NRF52_TIMER_CHAN_WAITACK, + IEEE802154_ACK_WAIT); + } + else + { + nrf52_radioi8_trace_put(RADIO_TRACE_IRQ_TXDONE, 0); + + /* Transmit DONE */ + + if (work_available(&dev->radio->irqwork)) + { + work_queue(HPWORK, &dev->radio->irqwork, + nrf52_radioi8_work_tx, (void *)dev, 0); + } + } + + /* CCABUSY event for TX */ + + if (NRF52_RADIO_GETREG(lower, NRF52_RADIO_EVENTS_CCABUSY_OFFSET)) + { + nrf52_radioi8_trace_put(RADIO_TRACE_IRQ_TXCCABUSY, 0); + + /* Clear event */ + + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_CCABUSY_OFFSET, 0); + + /* Slotted CSMA-CA */ + + if (dev->radio->state.slotted == true) + { +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + dev->radio->state.NB += 1; + dev->radio->state.CW = IEEE802154_CW0; + dev->radio->state.BE = MIN(2, dev->radio->state.min_be); + + if (dev->radio->state.NB > dev->radio->state.max_csma_backoffs) + { + /* Return fauilure to MAC */ + + if (work_available(&dev->radio->irqwork)) + { + work_queue(HPWORK, &dev->radio->irqwork, + nrf52_radioi8_work_busy, (void *)dev, 0); + } + } + else + { + /* Try again */ + + dev->radio->state.state = NRF52_RADIO_STATE_TX_CSMA; + nrf52_radioi8_norm_trigger(dev); + + /* Do not restore RX */ + + return; + } +#else + ASSERT(0); +#endif + } + + /* Un-slotted CSMA-CA */ + + else + { + /* Update backoff */ + + dev->radio->state.NB -= 1; + dev->radio->state.BE = MIN(dev->radio->state.BE + 1, + dev->radio->state.max_be); + + if (dev->radio->state.NB > dev->radio->state.max_csma_backoffs) + { + /* Return fauilure to MAC */ + + if (work_available(&dev->radio->irqwork)) + { + work_queue(HPWORK, &dev->radio->irqwork, + nrf52_radioi8_work_busy, (void *)dev, 0); + } + } + else + { + /* Try again */ + + dev->radio->state.state = NRF52_RADIO_STATE_TX_CSMA; + nrf52_radioi8_norm_trigger(dev); + + /* Do not restore RX */ + + return; + } + } + } + + /* CCAIDLE event for TX */ + + if (NRF52_RADIO_GETREG(lower, NRF52_RADIO_EVENTS_CCAIDLE_OFFSET)) + { + /* Clear event */ + + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_CCAIDLE_OFFSET, 0); + + /* Slotted CSMA-CA */ + + if (dev->radio->state.slotted == true) + { +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + dev->radio->state.CW -= 1; + + if (dev->radio->state.CW == 0) + { + /* Enable TX - short TXREADY-START is enabled */ + + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_TASKS_TXEN_OFFSET, 1); + } + else + { + /* Do not restore RX */ + + return; + } +#else + ASSERT(0); +#endif + } + + /* Un-slotted CSMA-CA */ + + else + { + /* Nothing here */ + } + } + + /* Restore RX */ + + if (dev->radio->state.rxrestore | dev->radio->state.waitack) + { + dev->macops.rxenable((struct ieee802154_radio_s *)dev, true); + dev->radio->state.rxrestore = false; + } +} + +/**************************************************************************** + * Name: nrf52_radioi8_state_acktx + * + * Description: + * Handle radio interrupt for ACKTX state. + * + ****************************************************************************/ + +static void nrf52_radioi8_state_acktx(struct nrf52_radioi8_dev_s *dev) +{ + nrf52_radioi8_trace_put(RADIO_TRACE_IRQ_ACKTX, 0); + + /* Handle pending TX */ + + if (dev->state.txdelayed_busy) + { + nrf52_radioi8_norm_setup(dev, + dev->state.txdelayed_desc->frame, + false); + + /* Send with timer to keep IFS */ + + if (dev->radio->state.rxlong) + { + dev->tim->ops->setup(dev, NRF52_TIMER_CHAN_TXDELAY, + IEEE802154_LIFS_SYMBOLS); + } + else + { + dev->tim->ops->setup(dev, NRF52_TIMER_CHAN_TXDELAY, + IEEE802154_SIFS_SYMBOLS); + } + } + + /* Restore RX */ + + else if (dev->radio->state.rxrestore) + { + dev->macops.rxenable((struct ieee802154_radio_s *)dev, true); + dev->radio->state.rxrestore = false; + } +} + +/**************************************************************************** + * Name: nrf52_radioi8_state_ed + * + * Description: + * Handle radio interrupt for ED state. + * + ****************************************************************************/ + +static void nrf52_radioi8_state_ed(struct nrf52_radioi8_dev_s *dev) +{ + /* Energy detect DONE */ + + DEBUGASSERT(work_available(&dev->radio->irqwork)); + work_queue(HPWORK, &dev->radio->irqwork, + nrf52_radioi8_work_ed, (void *)dev, 0); +} + +/**************************************************************************** + * Name: nrf52_radioi8_isr_radio + * + * Description: + * Radio IEEE 802.15.4 interrupt handler. + * + ****************************************************************************/ + +static int nrf52_radioi8_isr_radio(int irq, void *context, void *arg) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)arg; + struct nrf52_radio_dev_s *lower = NULL; + irqstate_t flags; + uint8_t state; + + DEBUGASSERT(dev != NULL); + lower = dev->radio->lower; + + flags = enter_critical_section(); + + nrf52_radioi8_trace_put(RADIO_TRACE_IRQ_RADIO, 0); + + /* Get state */ + + state = dev->radio->state.state; + dev->radio->state.state = NRF52_RADIO_STATE_DISABLED; + + /* Always clear END and PHYEND events */ + + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_END_OFFSET, 0); + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_PHYEND_OFFSET, 0); + + /* Clear interrupts and shorts */ + + NRF52_RADIO_INTCLR(lower, 0xffffffff); + NRF52_RADIO_SHRTSET(lower, 0); + + /* If by chance radio is not disabled - disable it now. This should be + * handled by SHORTS, but this not always work... + */ + + if (NRF52_RADIO_GETREG(lower, NRF52_RADIO_STATE_OFFSET) + != RADIO_STATE_DISABLED) + { + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_TASKS_DISABLE_OFFSET, 1); + + /* Don't wait for the DISABLED event, hopefully the radio will be + * disabled by the time we use it again. Max delay is TX->DSIABLED + * and takes 21us. + */ + } + + /* Handle IRQ depending on the current state */ + + switch (state) + { + case NRF52_RADIO_STATE_RX: + { + nrf52_radioi8_state_rx(dev); + + break; + } + + case NRF52_RADIO_STATE_TX: + { + nrf52_radioi8_state_tx(dev); + + break; + } + + case NRF52_RADIO_STATE_ACKTX: + { + nrf52_radioi8_state_acktx(dev); + + break; + } + + case NRF52_RADIO_STATE_ED: + { + /* Clear event */ + + NRF52_RADIO_PUTREG(lower, NRF52_RADIO_EVENTS_EDEND_OFFSET, 0); + + nrf52_radioi8_state_ed(dev); + + break; + } + + default: + { + ASSERT(0); + break; + } + } + + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_radioi8_radio_init + * + * Description: + * Initialize RADIO for IEEE802154 operations. + * + ****************************************************************************/ + +struct nrf52_radioi8_radio_s * +nrf52_radioi8_radio_init(struct nrf52_radioi8_dev_s *dev, + struct nrf52_radio_board_s *board) +{ + struct nrf52_radio_dev_s *radio = NULL; + + /* Initialize lower-half radio */ + + radio = nrf52_radio_initialize(0, board); + if (radio == NULL) + { + wlerr("nrf52_radio_initialize failed %d\n", -errno); + return NULL; + } + + /* Attach custom RADIO interrupt */ + + irq_attach(radio->irq, nrf52_radioi8_isr_radio, dev); + up_enable_irq(radio->irq); + + /* Set interrupts priority */ + + up_prioritize_irq(radio->irq, 0); + + /* Connect radioer */ + + memset(&g_radioi8_radio, 0, sizeof(struct nrf52_radioi8_radio_s)); + g_radioi8_radio.ops = &g_radioi8_radio_ops; + g_radioi8_radio.lower = radio; + + /* Connect buffers */ + + g_radioi8_radio.rxbuf = g_nrf52_radioi8_rxbuf; + g_radioi8_radio.txbuf = g_nrf52_radioi8_txbuf; + g_radioi8_radio.ackbuf = g_nrf52_radioi8_ackbuf; +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + g_radioi8_radio.beaconbuf = g_nrf52_radioi8_beaconbuf; +#endif + + return &g_radioi8_radio; +} diff --git a/arch/arm/src/nrf52/nrf52_ieee802154_radio.h b/arch/arm/src/nrf52/nrf52_ieee802154_radio.h new file mode 100644 index 0000000000000..8dd9146bd07d2 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_ieee802154_radio.h @@ -0,0 +1,246 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_ieee802154_radio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_NRF52_IEEE802154_RADIO_H +#define __ARCH_ARM_SRC_NRF52_NRF52_IEEE802154_RADIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "hardware/nrf52_radio.h" + +#include "nrf52_radio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IEEE 802.15.4 constants */ + +#define IEEE802154_MAX_FRAME_WAITTIME (16 + 32 + 4064) +#define IEEE802154_MAX_CSMA_BACKOFFS (1) +#define IEEE802154_MIN_BE (3) +#define IEEE802154_MAX_BE (5) +#define IEEE802154_CW0 (2) + +/* ACK_SYM + turnaround symbols + backoff */ + +#define IEEE802154_ACK_WAIT (12+ \ + IEEE802154_TURN_AROUND_TIME+ \ + IEEE802154_UNIT_BACKOFF_PERIOD) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Radio state */ + +enum nrf52_radioi8_state_e +{ + NRF52_RADIO_STATE_DISABLED = 0, /* Radio disabled */ + NRF52_RADIO_STATE_TX_CSMA, /* CSMA TX armed */ + NRF52_RADIO_STATE_TX_NOCSMA, /* Non CSMA TX armed */ + NRF52_RADIO_STATE_TX, /* TX on the air */ + NRF52_RADIO_STATE_RX, /* RX active */ + NRF52_RADIO_STATE_ACKTX, /* Transmiting ACK now */ + NRF52_RADIO_STATE_ED, /* Energy detection now */ +}; + +/* Radio data */ + +struct nrf52_radioi8_radio_data_s +{ + /* Radio state */ + + uint8_t state; + + /* CSMA-CA */ + + uint8_t NB; /* Number of required back offs */ + uint8_t CW; /* Contention window length */ + uint8_t BE; /* Backoff exponent */ + + /* RX state */ + + bool rxenabled; /* RX enabled now */ + bool rxrestore; /* RX needs to be restored */ + bool rxlong; /* Last RX frame was long */ + + /* TX state */ + + bool waitack; /* TX needs ACK */ + bool framepending; /* Frame pending from the last TX ACK */ + bool csma_busy; /* Un-slotted CSMA busy */ + bool slotted; /* Slotted CSMA-CA */ + + /* Radio configuration */ + + uint32_t max_frame_waittime; /* Max Frame wait time */ + uint8_t max_csma_backoffs; /* Max CSMA backoffs */ + uint8_t min_be; /* Min backoff exponent (BE) */ + uint8_t max_be; /* Max backoff exponent (BE) */ + +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + /* Superframe data */ + + bool wait_for_beacon; /* Device wait for beacon */ + bool ble; /* Batter life extension */ +#endif +}; + +/* Forward reference */ + +struct nrf52_radioi8_radio_s; +struct ieee802154_radio_s; +struct nrf52_radioi8_dev_s; +struct ieee802154_cca_s; + +/* Radio ops */ + +struct nrf52_radioi8_radio_ops_s +{ + /* Start transmition - TX must be armed (TXEN set) */ + + void (*txstart)(struct nrf52_radioi8_dev_s *dev); + + /* Start CCA - RX must be armed (RXEN set) */ + + void (*ccastart)(struct nrf52_radioi8_dev_s *dev); + + /* Notify MAC about no ACK */ + + void (*notify_noack)(struct nrf52_radioi8_dev_s *dev); + + /* Enable/Disable receiver */ + + int (*rxenable)(struct nrf52_radioi8_dev_s *dev, bool enable); + + /* Start the energy detect measurement */ + + int (*energydetect)(struct nrf52_radioi8_dev_s *dev, uint32_t nsymbols); + + /* Define the current radio channel the device is operating on */ + + int (*setchannel)(struct nrf52_radioi8_dev_s *dev, uint8_t chan); + + /* Configure the Clear Channel Assessement */ + + int (*setcca)(struct nrf52_radioi8_dev_s *dev, + struct ieee802154_cca_s *cca); + + /* Setup a normal transaction (non GTS) */ + + void (*norm_setup)(struct nrf52_radioi8_dev_s *dev, + struct iob_s *frame, bool csma); + + /* Trigger normal transaction (non GTS) */ + + void (*norm_trigger)(struct nrf52_radioi8_dev_s *dev); + +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + /* Setup a beacon frame transfe */ + + void (*beacon_setup)(struct nrf52_radioi8_dev_s *dev, + uint8_t *data, uint8_t len); + + /* Transmit a beacon frame (non CSMA-CA transfer) */ + + void (*beacon_tx)(struct nrf52_radioi8_dev_s *dev); +#endif + + /* Reset radio state to work with IEEE 802.15.4 */ + + int (*reset)(struct nrf52_radioi8_radio_s *dev); + + /* Handle TX poll (no GTS) */ + + int (*csma_poll)(struct nrf52_radioi8_dev_s *dev); + + /* Handle GTS poll */ + + int (*gts_poll)(struct nrf52_radioi8_dev_s *dev); +}; + +/* Radio interface */ + +struct nrf52_radioi8_radio_s +{ + /* Radio lower-half */ + + struct nrf52_radio_dev_s *lower; + + /* IEEE 802.15.4 radio operations */ + + struct nrf52_radioi8_radio_ops_s *ops; + + /* Packet buffers */ + + uint8_t *rxbuf; + uint8_t *txbuf; + uint8_t *ackbuf; +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + uint8_t *beaconbuf; +#endif + + /* For deferring interrupts work */ + + struct work_s irqwork; + + /* For deferring no ACK work */ + + struct work_s noackwork; + + /* For deferring poll work to the work queue */ + + struct work_s csma_pollwork; + +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + /* For deferring poll work to the work queue */ + + struct work_s gts_pollwork; +#endif + + /* Radio data */ + + struct nrf52_radioi8_radio_data_s state; +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_radioi8_radio_init + * + * Description: + * Initialize RADIO for IEEE802154 operations. + * + ****************************************************************************/ + +struct nrf52_radioi8_radio_s * +nrf52_radioi8_radio_init(struct nrf52_radioi8_dev_s *dev, + struct nrf52_radio_board_s *board); + +#endif /* __ARCH_ARM_SRC_NRF52_NRF52_IEEE802154_RADIO_H */ diff --git a/arch/arm/src/nrf52/nrf52_ieee802154_rtc.c b/arch/arm/src/nrf52/nrf52_ieee802154_rtc.c new file mode 100644 index 0000000000000..7d32b3df78cee --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_ieee802154_rtc.c @@ -0,0 +1,392 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_ieee802154_rtc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include + +#include "nrf52_ieee802154_rtc.h" +#include "nrf52_ieee802154_trace.h" + +#include "nrf52_ieee802154_priv.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME +# warning Beacon and superframe support work in progress +#endif + +#ifndef CONFIG_NRF52_RTC0 +# error CONFIG_NRF52_RTC0 is needed to handle radio timings +#endif + +/* RTC instance - 0 */ + +#define NRF52_IEEE802154_RTC0 (0) + +/* RTC prescaler set to 0, freq = 32.768kHz, resolution = 30.517 us */ + +#define NRF52_RTC_PRESCALER (0) +#define NRF52_RTC_FREQUENCY (32768) + +#define NRF52_RTC_RESOLUTION_NS (30517) + +/* 31 * 30.517us = 946.027us */ + +#define NRF52_RTC_TIMESLOT_CC (31) + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* RTC ops */ + +static int nrf52_radioi8_rtc(struct nrf52_radioi8_dev_s *dev, + struct ieee802154_superframespec_s *sfspec); +static int nrf52_radioi8_rtc_start(struct nrf52_radioi8_dev_s *dev); +static int nrf52_radioi8_rtc_stop(struct nrf52_radioi8_dev_s *dev); +static void nrf52_radioi8_rtc_reset(struct nrf52_radioi8_dev_s *dev); + +/* Interrupts logic */ + +static void nrf52_radioi8_work_inactive(void *arg); +static int nrf52_radioi8_isr_rtc(int irq, void *context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* RTC ops */ + +static struct nrf52_radioi8_rtc_ops_s g_radioi8_rtc_ops = +{ + .setup = nrf52_radioi8_rtc, + .start = nrf52_radioi8_rtc_start, + .stop = nrf52_radioi8_rtc_stop, + .reset = nrf52_radioi8_rtc_reset +}; + +/* RTC instance */ + +static struct nrf52_radioi8_rtc_s g_radioi8_rtc; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_radioi8_rtc + * + * Description: + * Configure RTC events according to superframe spec. + * + ****************************************************************************/ + +static int nrf52_radioi8_rtc(struct nrf52_radioi8_dev_s *dev, + struct ieee802154_superframespec_s *sfspec) +{ + uint32_t bi = 0; + uint32_t sd = 0; + uint32_t cap = 0; + irqstate_t flags; + + flags = enter_critical_section(); + + /* Stop RTC and clear the counter */ + + NRF52_RTC_STOP(dev->rtc->rtc); + NRF52_RTC_CLEAR(dev->rtc->rtc); + + /* Initialize BI counter */ + + bi = ((IEEE802154_BASE_SUPERFRAME_DURATION * + (2 << sfspec->beaconorder) * + IEEE802154_SYMBOL_US * 1000) / + NRF52_RTC_RESOLUTION_NS); + NRF52_RTC_SETCC(dev->rtc->rtc, NRF52_RTC_BI, bi); + + /* Initialize SD counter */ + + sd = ((IEEE802154_BASE_SUPERFRAME_DURATION * + (2 << sfspec->sforder) * + IEEE802154_SYMBOL_US * 1000) / + NRF52_RTC_RESOLUTION_NS); + NRF52_RTC_SETCC(dev->rtc->rtc, NRF52_RTC_SD, sd); + + /* Initialize CAP counter */ + + cap = ((sfspec->final_capslot * + IEEE802154_TIMESLOT_US * 1000) / + NRF52_RTC_RESOLUTION_NS); + NRF52_RTC_SETCC(dev->rtc->rtc, NRF52_RTC_CAP, cap); + + /* Initialize timeslot counter */ + + dev->rtc->rtc_timeslot = NRF52_RTC_TIMESLOT_CC; + NRF52_RTC_SETCC(dev->rtc->rtc, NRF52_RTC_TIMESLOT, dev->rtc->rtc_timeslot); + + /* Configure interupts */ + + NRF52_RTC_ENABLEINT(dev->rtc->rtc, NRF52_RTC_BI); + NRF52_RTC_ENABLEINT(dev->rtc->rtc, NRF52_RTC_SD); + NRF52_RTC_ENABLEINT(dev->rtc->rtc, NRF52_RTC_CAP); + NRF52_RTC_ENABLEINT(dev->rtc->rtc, NRF52_RTC_TIMESLOT); + + /* Configure events */ + + NRF52_RTC_ENABLEEVT(dev->rtc->rtc, NRF52_RTC_BI); + NRF52_RTC_ENABLEEVT(dev->rtc->rtc, NRF52_RTC_SD); + NRF52_RTC_ENABLEEVT(dev->rtc->rtc, NRF52_RTC_CAP); + NRF52_RTC_ENABLEEVT(dev->rtc->rtc, NRF52_RTC_TIMESLOT); + + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_rtc_start + * + * Description: + * Start RTC. + * + ****************************************************************************/ + +static int nrf52_radioi8_rtc_start(struct nrf52_radioi8_dev_s *dev) +{ + NRF52_RTC_START(dev->rtc->rtc); + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_rtc_stop + * + * Description: + * Stop RTC. + * + ****************************************************************************/ + +static int nrf52_radioi8_rtc_stop(struct nrf52_radioi8_dev_s *dev) +{ + NRF52_RTC_STOP(dev->rtc->rtc); + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_rtc_reset + * + * Description: + * Reset RTC. + * + ****************************************************************************/ + +static void nrf52_radioi8_rtc_reset(struct nrf52_radioi8_dev_s *dev) +{ + /* Configure RTC - freq = 32.768 kHz */ + + NRF52_RTC_STOP(dev->rtc->rtc); + NRF52_RTC_SETPRE(dev->rtc->rtc, NRF52_RTC_PRESCALER); + + /* Reset data */ + + dev->rtc->rtc_timeslot = 0; +} + +/**************************************************************************** + * Name: nrf52_radioi8_work_inactive + * + * Description: + * Work when we enter inactive state. + * + ****************************************************************************/ + +static void nrf52_radioi8_work_inactive(void *arg) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)arg; + enum ieee802154_sfevent_e sfevent; + + /* Notify MAC */ + + sfevent = IEEE802154_SFEVENT_ENDOFACTIVE; + dev->radiocb->sfevent(dev->radiocb, sfevent); +} + +/**************************************************************************** + * Name: nrf52_radioi8_isr_rtc + * + * Description: + * Helper RTC0 interrupt handler. + * + ****************************************************************************/ + +static int nrf52_radioi8_isr_rtc(int irq, void *context, void *arg) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)arg; + struct nrf52_radioi8_rtc_s *rtc = NULL; + irqstate_t flags; + + DEBUGASSERT(dev != NULL); + rtc = dev->rtc; + + flags = enter_critical_section(); + + /* End of CAP */ + + if (NRF52_RTC_CHECKINT(rtc->rtc, NRF52_RTC_CAP)) + { + nrf52_radioi8_trace_put(RADIO_TRACE_IRQ_RTCCAP, 0); + + /* TODO */ + + /* Clear event */ + + NRF52_RTC_ACKINT(rtc->rtc, NRF52_RTC_CAP); + } + + /* End of active portion */ + + else if (NRF52_RTC_CHECKINT(rtc->rtc, NRF52_RTC_SD)) + { + nrf52_radioi8_trace_put(RADIO_TRACE_IRQ_RTCSD, 0); + + /* Schedule work */ + + DEBUGASSERT(work_available(&dev->rtc->inactive_work)); + work_queue(HPWORK, &dev->rtc->inactive_work, + nrf52_radioi8_work_inactive, dev, 0); + + /* Reset timeslot */ + + rtc->rtc_timeslot = NRF52_RTC_TIMESLOT_CC; + + /* Clear event */ + + NRF52_RTC_ACKINT(rtc->rtc, NRF52_RTC_SD); + } + + /* Beacon interval */ + + else if (NRF52_RTC_CHECKINT(rtc->rtc, NRF52_RTC_BI)) + { + nrf52_radioi8_trace_put(RADIO_TRACE_IRQ_RTCBI, 0); + + /* Transmit beacon if we are not endpoint */ + + if (dev->state.devmode != NRF52_DEVMODE_ENDPOINT) + { + /* Transmit data from beaconbuf */ + + dev->radio->ops->beacon_tx(dev); + } + + /* Clear event */ + + NRF52_RTC_ACKINT(rtc->rtc, NRF52_RTC_BI); + + /* Next cycle */ + + NRF52_RTC_TRGOVRFLW(rtc->rtc); + + /* TODO: resync with beacon ? */ + } + + /* Timeslot in active portion */ + + if (NRF52_RTC_CHECKINT(rtc->rtc, NRF52_RTC_TIMESLOT)) + { + nrf52_radioi8_trace_put(RADIO_TRACE_IRQ_RTCTIMESLOT, 0); + + /* TODO: how to sync transmition with timeslot ? + * do we need count every timeslot here ? + * or wait for the timeslot we are interested in ? + * or just use txdelay ? + */ + + /* Update timeslot */ + + rtc->rtc_timeslot += NRF52_RTC_TIMESLOT_CC; + NRF52_RTC_SETCC(rtc->rtc, NRF52_RTC_TIMESLOT, rtc->rtc_timeslot); + + /* Clear event */ + + NRF52_RTC_ACKINT(rtc->rtc, NRF52_RTC_TIMESLOT); + } + + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_radioi8_rtc_init + * + * Description: + * Initialize low resoluton, low power timer for IEEE802154 operations. + * Used to handle superframe timings. + * + ****************************************************************************/ + +struct nrf52_radioi8_rtc_s * +nrf52_radioi8_rtc_init(struct nrf52_radioi8_dev_s *dev) +{ + struct nrf52_rtc_dev_s *rtc = NULL; + + /* Reserve RTC0 */ + + rtc = nrf52_rtc_init(NRF52_IEEE802154_RTC0); + if (rtc == NULL) + { + wlerr("nrf52_rtc_init(0) failed %d\n", -errno); + return NULL; + } + + /* Atach RTC interrupt */ + + NRF52_RTC_SETISR(rtc, nrf52_radioi8_isr_rtc, dev); + + /* Set interrupts priority */ + + up_prioritize_irq(NRF52_IRQ_RTC0, 0); + + /* Connect RTC */ + + memset(&g_radioi8_rtc, 0, sizeof(struct nrf52_radioi8_rtc_s)); + g_radioi8_rtc.ops = &g_radioi8_rtc_ops; + g_radioi8_rtc.rtc = rtc; + + return &g_radioi8_rtc; +} diff --git a/arch/arm/src/nrf52/nrf52_ieee802154_rtc.h b/arch/arm/src/nrf52/nrf52_ieee802154_rtc.h new file mode 100644 index 0000000000000..de6f475ff2dc9 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_ieee802154_rtc.h @@ -0,0 +1,116 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_ieee802154_rtc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_NRF52_IEEE802154_RTC_H +#define __ARCH_ARM_SRC_NRF52_NRF52_IEEE802154_RTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "nrf52_rtc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* RTC events */ + +enum nrf52_ieee802154_rtc_e +{ + NRF52_RTC_BI = 0, /* Beacon Interval interval (BI) */ + NRF52_RTC_TIMESLOT = 1, /* Time slot */ + NRF52_RTC_CAP = 2, /* Contention Access Period (CAP) */ + NRF52_RTC_SD = 3 /* Super Frame Duration (SD) */ +}; + +/* Forward reference */ + +struct nrf52_radioi8_rtc_s; +struct nrf52_radioi8_dev_s; + +/* RTC ops */ + +struct nrf52_radioi8_rtc_ops_s +{ + /* Configure RTC events according to superframe spec */ + + int (*setup)(struct nrf52_radioi8_dev_s *dev, + struct ieee802154_superframespec_s *sfspec); + + /* Start RTC */ + + int (*start)(struct nrf52_radioi8_dev_s *dev); + + /* Stop RTC */ + + int (*stop)(struct nrf52_radioi8_dev_s *dev); + + /* Reset RTC */ + + void (*reset)(struct nrf52_radioi8_dev_s *dev); +}; + +/* RTC interface */ + +struct nrf52_radioi8_rtc_s +{ + /* RTC lower-half */ + + struct nrf52_rtc_dev_s *rtc; + + /* IEEE 802.15.4 RTC operations */ + + struct nrf52_radioi8_rtc_ops_s *ops; + +#ifdef CONFIG_NRF52_RADIO_IEEE802154_SUPERFRAME + /* For deferring inactive state work to the work queue */ + + struct work_s inactive_work; + + /* RTC state */ + + uint32_t rtc_timeslot; +#endif +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_radioi8_rtc_init + * + * Description: + * Initialize low resoluton, low power timer for IEEE802154 operations. + * Used to handle superframe timings. + * + ****************************************************************************/ + +struct nrf52_radioi8_rtc_s * +nrf52_radioi8_rtc_init(struct nrf52_radioi8_dev_s *dev); + +#endif /* __ARCH_ARM_SRC_NRF52_NRF52_IEEE802154_RTC_H */ diff --git a/arch/arm/src/nrf52/nrf52_ieee802154_tim.c b/arch/arm/src/nrf52/nrf52_ieee802154_tim.c new file mode 100644 index 0000000000000..7e8dd5749cbad --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_ieee802154_tim.c @@ -0,0 +1,347 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_ieee802154_tim.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "nrf52_ieee802154_tim.h" +#include "nrf52_ieee802154_trace.h" + +#include "nrf52_ieee802154_priv.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_NRF52_TIMER0 +# error CONFIG_NRF52_TIMER0 is needed to handle radio timings +#endif + +/* Timer instance - 0 */ + +#define NRF52_IEEE802154_TIMER0 (0) + +/* Timer period set to 16us (symbol duration) */ + +#define NRF52_TIMER_FREQUENCY (1000000 / 16) + +/* 16MHz / (2 ** 8) = 62500 */ + +#define NRF52_TIMER_PRESCALER (8) + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* RTC ops */ + +static int nrf52_radioi8_tim(struct nrf52_radioi8_dev_s *dev, uint8_t chan, + uint32_t val); +static void nrf52_radioi8_tim_stop(struct nrf52_radioi8_dev_s *dev); +static void nrf52_radioi8_tim_reset(struct nrf52_radioi8_dev_s *dev); + +/* Interrupts logic */ + +static int nrf52_radioi8_isr_tim(int irq, void *context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Timer ops */ + +static struct nrf52_radioi8_tim_ops_s g_radioi8_tim_ops = +{ + .setup = nrf52_radioi8_tim, + .stop = nrf52_radioi8_tim_stop, + .reset = nrf52_radioi8_tim_reset +}; + +/* Timer instance */ + +static struct nrf52_radioi8_tim_s g_radioi8_tim; + +/**************************************************************************** + * Private Function + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_radioi8_tim + * + * Description: + * Configure TIMER event. + * + ****************************************************************************/ + +static int nrf52_radioi8_tim(struct nrf52_radioi8_dev_s *dev, uint8_t chan, + uint32_t val) +{ + struct nrf52_radioi8_tim_s *tim = NULL; + irqstate_t flags; + + DEBUGASSERT(dev != NULL); + tim = dev->tim; + + flags = enter_critical_section(); + + if (tim->tim_pending == true) + { + wlerr("TIMER busy! drop %" PRId8 " %" PRId32 " request\n", chan, val); + ASSERT(0); + return -EBUSY; + } + + /* Stop timer and clear the counter */ + + NRF52_TIM_STOP(tim->tim); + NRF52_TIM_CLEAR(tim->tim); + + /* Clear the previous event */ + + NRF52_TIM_ACKINT(tim->tim, chan); + + /* Set compare register */ + + NRF52_TIM_SETCC(tim->tim, chan, val); + + /* Configure interupt */ + + NRF52_TIM_ENABLEINT(tim->tim, chan); + + /* Set TIMER pending flag and used channel */ + + tim->tim_pending = true; + tim->tim_now = chan; + + /* Start timer */ + + nrf52_radioi8_trace_put(RADIO_TRACE_TIMSTART, chan); + + if (val > 0) + { + NRF52_TIM_START(tim->tim); + } + else + { + /* Call handler now */ + + nrf52_radioi8_isr_tim(0, NULL, dev); + } + + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Name: nrf52_radioi8_tim_stop + * + * Description: + * Stop timer. + * + ****************************************************************************/ + +static void nrf52_radioi8_tim_stop(struct nrf52_radioi8_dev_s *dev) +{ + NRF52_TIM_STOP(dev->tim->tim); + NRF52_TIM_DISABLEINT(dev->tim->tim, dev->tim->tim_now); + + /* Reset state */ + + dev->tim->tim_pending = false; + dev->tim->tim_now = -1; +} + +/**************************************************************************** + * Name: nrf52_radioi8_tim_reset + * + * Description: + * Reset TIMER. + * + ****************************************************************************/ + +static void nrf52_radioi8_tim_reset(struct nrf52_radioi8_dev_s *dev) +{ + /* Configure TIMER - freq = 62500 */ + + NRF52_TIM_STOP(dev->tim->tim); + NRF52_TIM_CONFIGURE(dev->tim->tim, NRF52_TIM_MODE_TIMER, + NRF52_TIM_WIDTH_32B); + NRF52_TIM_SETPRE(dev->tim->tim, NRF52_TIMER_PRESCALER); + + /* Reset state */ + + dev->tim->tim_pending = false; + dev->tim->tim_now = -1; +} + +/**************************************************************************** + * Name: nrf52_radioi8_isr_tim + * + * Description: + * Helper tim interrupt handler. + * + ****************************************************************************/ + +static int nrf52_radioi8_isr_tim(int irq, void *context, void *arg) +{ + struct nrf52_radioi8_dev_s *dev = (struct nrf52_radioi8_dev_s *)arg; + struct nrf52_radioi8_tim_s *tim = NULL; + irqstate_t flags; + + DEBUGASSERT(dev != NULL); + tim = dev->tim; + + flags = enter_critical_section(); + + switch (tim->tim_now) + { + /* RX ACK handler */ + + case NRF52_TIMER_CHAN_ACK: + { + nrf52_radioi8_trace_put(RADIO_TRACE_IRQ_TIMACKTX, 0); + + /* Start TX */ + + dev->radio->ops->txstart(dev); + + break; + } + + /* Delayed TX handler */ + + case NRF52_TIMER_CHAN_TXDELAY: + { + nrf52_radioi8_trace_put(RADIO_TRACE_IRQ_TIMTXDELAY, 0); + + /* Trigger TX */ + + dev->radio->ops->norm_trigger(dev); + + break; + } + + /* ACK wait handler */ + + case NRF52_TIMER_CHAN_WAITACK: + { + nrf52_radioi8_trace_put(RADIO_TRACE_IRQ_TIMWAITACK, 0); + + /* Notify radio layer */ + + dev->radio->ops->notify_noack(dev); + + break; + } + + case NRF52_TIMER_CHAN_CSMADELAY: + { + nrf52_radioi8_trace_put(RADIO_TRACE_IRQ_TIMCSMADELAY, 0); + + /* Start CCA - we transmit immediately after the CCA procedure ends + * (CCAIDLE_TXEN short), or CCABUSY interrupt happen. + */ + + dev->radio->ops->ccastart(dev); + + break; + } + + default: + { + ASSERT(0); + break; + } + } + + /* Stop timer */ + + NRF52_TIM_STOP(tim->tim); + + /* Disable and clear interrupts */ + + NRF52_TIM_DISABLEINT(tim->tim, tim->tim_now); + NRF52_TIM_ACKINT(tim->tim, tim->tim_now); + + /* Clear TIMER pending flag and used channel */ + + tim->tim_pending = false; + tim->tim_now = -1; + + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_radioi8_tim_init + * + * Description: + * Initialize high resoluton timer for IEEE802154 operations. + * Used to handle short radio timeouts like ACK, IFS or delayed + * transmitions. + * + ****************************************************************************/ + +struct nrf52_radioi8_tim_s * +nrf52_radioi8_tim_init(struct nrf52_radioi8_dev_s *dev) +{ + struct nrf52_tim_dev_s *tim = NULL; + + /* Reserve TIMER0 */ + + tim = nrf52_tim_init(NRF52_IEEE802154_TIMER0); + if (tim == NULL) + { + wlerr("nrf52_tim_init(0) failed %d\n", -errno); + return NULL; + } + + /* Atach TIMER interrupt */ + + NRF52_TIM_SETISR(tim, nrf52_radioi8_isr_tim, dev); + + /* Set interrupts priority */ + + up_prioritize_irq(NRF52_IRQ_TIMER0, 0); + + /* Connect timer */ + + memset(&g_radioi8_tim, 0, sizeof(struct nrf52_radioi8_tim_s)); + g_radioi8_tim.ops = &g_radioi8_tim_ops; + g_radioi8_tim.tim = tim; + + return &g_radioi8_tim; +} diff --git a/arch/arm/src/nrf52/nrf52_ieee802154_tim.h b/arch/arm/src/nrf52/nrf52_ieee802154_tim.h new file mode 100644 index 0000000000000..0821353475b39 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_ieee802154_tim.h @@ -0,0 +1,105 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_ieee802154_tim.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_NRF52_IEEE802154_TIM_H +#define __ARCH_ARM_SRC_NRF52_NRF52_IEEE802154_TIM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "nrf52_tim.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum nrf52_ieee802154_timer_e +{ + NRF52_TIMER_CHAN_ACK = 0, /* Handle ACK time */ + NRF52_TIMER_CHAN_TXDELAY = 1, /* Handle TX delay */ + NRF52_TIMER_CHAN_WAITACK = 2, /* Handle ACK wait */ + NRF52_TIMER_CHAN_CSMADELAY = 3, /* Handle CSMA wait */ +}; + +/* Forward reference */ + +struct nrf52_radioi8_tim_s; +struct nrf52_radioi8_dev_s; + +/* Timer ops */ + +struct nrf52_radioi8_tim_ops_s +{ + /* Configure TIMER event */ + + int (*setup)(struct nrf52_radioi8_dev_s *dev, uint8_t chan, uint32_t val); + + /* Stop timer */ + + void (*stop)(struct nrf52_radioi8_dev_s *dev); + + /* Reset timer */ + + void (*reset)(struct nrf52_radioi8_dev_s *dev); +}; + +/* Timer interface */ + +struct nrf52_radioi8_tim_s +{ + /* Timer lower-half */ + + struct nrf52_tim_dev_s *tim; + + /* IEEE 802.15.4 timer operations */ + + struct nrf52_radioi8_tim_ops_s *ops; + + /* Timer state */ + + int8_t tim_now; + bool tim_pending; +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_radioi8_tim_init + * + * Description: + * Initialize high resoluton timer for IEEE802154 operations. + * Used to handle short radio timeouts like ACK, IFS or delayed + * transmitions. + * + ****************************************************************************/ + +struct nrf52_radioi8_tim_s * +nrf52_radioi8_tim_init(struct nrf52_radioi8_dev_s *dev); + +#endif /* __ARCH_ARM_SRC_NRF52_NRF52_IEEE802154_TIM_H */ diff --git a/arch/arm/src/nrf52/nrf52_ieee802154_trace.c b/arch/arm/src/nrf52/nrf52_ieee802154_trace.c new file mode 100644 index 0000000000000..69d6f7f668912 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_ieee802154_trace.c @@ -0,0 +1,154 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_ieee802154_trace.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "nrf52_ieee802154_trace.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This must match enum radio_trace_type_e */ + +static const char *g_radio_trace_str[] = +{ + "RADIO IRQ", + "RADIO IRQ: RX DONE", + "RADIO IRQ: TX DONE", + "RADIO IRQ: ACK TX", + "RADIO IRQ: WAIT ACK", + "RADIO IRQ: RX ACK DONE", + "RADIO IRQ: TX CCA BUSY", + + "TIM IRQ: TIM ACK TX", + "TIM IRQ; TIM TX DELAY", + "TIM IRQ: TIM WAIT ACK", + "TIM IRQ: TIM CSMA DELAY", + "RTC IRQ: RTC SD", + "RTC IRQ: RTC CAP", + "RTC IRQ: RTC TIMESLOT", + "RTC IRQ: RTC BI", + + "WORK: RX", + "WORK: TX", + "WORK: BUSY", + "WORK: ED", + "WORK: NO ACK", + + "ACKTX", + "TIMSTART", + "RXENABLE", + "RXDISABLE", + "CSMASETUP", + "CSMATRIGGER", + "NOCSMATRIGGER", + "NOACK", + "DROPFRAME", + "TXTRYAGAIN", +}; + +/* Trace data */ + +static volatile size_t g_radio_trace_cntr = 0; +static volatile struct radio_trace_s +g_radio_trace[CONFIG_NRF52_RADIO_IEEE802154_TRACE_BUFSIZE]; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_radioi8_trace_init + * + * Description: + * Initialize trace interface. + * + ****************************************************************************/ + +void nrf52_radioi8_trace_init(void) +{ + g_radio_trace_cntr = 0; + memset((void *)g_radio_trace, 0, sizeof(g_radio_trace)); +} + +/**************************************************************************** + * Name: nrf52_radioi8_trace_put + * + * Description: + * Put trace event. + * + ****************************************************************************/ + +void nrf52_radioi8_trace_put(uint8_t type, uint32_t arg) +{ + if (g_radio_trace_cntr >= CONFIG_NRF52_RADIO_IEEE802154_TRACE_BUFSIZE) + { + g_radio_trace_cntr = 0; + } + + g_radio_trace[g_radio_trace_cntr].time = perf_gettime(); + g_radio_trace[g_radio_trace_cntr].str = g_radio_trace_str[type]; + g_radio_trace[g_radio_trace_cntr].arg = arg; + g_radio_trace_cntr += 1; +} + +/**************************************************************************** + * Name: nrf52_radioi8_trace_dump + * + * Description: + * Dump radio trace. + * + ****************************************************************************/ + +void nrf52_radioi8_trace_dump(void) +{ + int i = 0; + + printf("NRF52 Radio IEEE 802.15.4 Trace dump:\n"); + printf("CPU freq: %d\n\n", BOARD_SYSTICK_CLOCK); + + for (i = 0; i < g_radio_trace_cntr; i += 1) + { + printf("[%lu]: %s %lu\n\n", + g_radio_trace[i].time, + g_radio_trace[i].str, + g_radio_trace[i].arg); + } + + /* Reset trace buffer */ + + g_radio_trace_cntr = 0; + memset((void *)g_radio_trace, 0, sizeof(g_radio_trace)); +} diff --git a/arch/arm/src/nrf52/nrf52_ieee802154_trace.h b/arch/arm/src/nrf52/nrf52_ieee802154_trace.h new file mode 100644 index 0000000000000..a43daa8c10b98 --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_ieee802154_trace.h @@ -0,0 +1,106 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_ieee802154_trace.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_NRF52_IEEE802154_TRACE_H +#define __ARCH_ARM_SRC_NRF52_NRF52_IEEE802154_TRACE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Trace item */ + +struct radio_trace_s +{ + clock_t time; /* Event timestamp */ + const char *str; /* Event string */ + uint32_t arg; /* Optional data */ +}; + +/* This must match char *g_radio_trace_str[] */ + +enum radio_trace_type_e +{ + /* Radio interupts */ + + RADIO_TRACE_IRQ_RADIO, + RADIO_TRACE_IRQ_RXDONE, + RADIO_TRACE_IRQ_TXDONE, + RADIO_TRACE_IRQ_ACKTX, + RADIO_TRACE_IRQ_WAITACK, + RADIO_TRACE_IRQ_RXACKDONE, + RADIO_TRACE_IRQ_TXCCABUSY, + + /* Timer interrupts */ + + RADIO_TRACE_IRQ_TIMACKTX, + RADIO_TRACE_IRQ_TIMTXDELAY, + RADIO_TRACE_IRQ_TIMWAITACK, + RADIO_TRACE_IRQ_TIMCSMADELAY, + RADIO_TRACE_IRQ_RTCSD, + RADIO_TRACE_IRQ_RTCCAP, + RADIO_TRACE_IRQ_RTCTIMESLOT, + RADIO_TRACE_IRQ_RTCBI, + + /* Works */ + + RADIO_TRACE_WORK_RX, + RADIO_TRACE_WORK_TX, + RADIO_TRACE_WORK_BUSY, + RADIO_TRACE_WORK_ED, + RADIO_TRACE_WORK_NOACK, + + /* Various events */ + + RADIO_TRACE_ACKTX, + RADIO_TRACE_TIMSTART, + RADIO_TRACE_RXENABLE, + RADIO_TRACE_RXDISABLE, + RADIO_TRACE_CSMASETUP, + RADIO_TRACE_CSMATRIGGER, + RADIO_TRACE_NOCSMATRIGGER, + RADIO_TRACE_NOACK, + RADIO_TRACE_DROPFRAME, + RADIO_TRACE_TXRETRY, +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_NRF52_RADIO_IEEE802154_TRACE +void nrf52_radioi8_trace_init(void); +void nrf52_radioi8_trace_put(uint8_t type, uint32_t arg); +void nrf52_radioi8_trace_dump(void); +#else +# define nrf52_radioi8_trace_put(...) +#endif + +#endif /* __ARCH_ARM_SRC_NRF52_NRF52_IEEE802154_TRACE_H */ diff --git a/arch/arm/src/nrf52/nrf52_ppi.h b/arch/arm/src/nrf52/nrf52_ppi.h index f7b82b839b22d..f51d6e066d80f 100644 --- a/arch/arm/src/nrf52/nrf52_ppi.h +++ b/arch/arm/src/nrf52/nrf52_ppi.h @@ -171,4 +171,4 @@ void nrf52_ppi_grp_enable(uint8_t group, bool enable); } #endif -#endif // __ARCH_ARM_SRC_NRF52_NRF52_PPI_H +#endif /* __ARCH_ARM_SRC_NRF52_NRF52_PPI_H */ diff --git a/arch/arm/src/nrf52/nrf52_radio.c b/arch/arm/src/nrf52/nrf52_radio.c index 60ba3f1a071cc..7184873548195 100644 --- a/arch/arm/src/nrf52/nrf52_radio.c +++ b/arch/arm/src/nrf52/nrf52_radio.c @@ -41,15 +41,6 @@ #include "hardware/nrf52_radio.h" #include "hardware/nrf52_utils.h" -#warning NRF52 RADIO support is EXPERIMENTAL! - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define NRF52_RADIO_RXBUFFER (255) -#define NRF52_RADIO_TXBUFFER (255) - /**************************************************************************** * Private Function Prototypes ****************************************************************************/ @@ -64,17 +55,20 @@ static uint32_t nrf52_radio_getreg(struct nrf52_radio_dev_s *dev, /* Radio operations *********************************************************/ +static void nrf52_radio_reset(struct nrf52_radio_dev_s *dev); +static void nrf52_radio_inten(struct nrf52_radio_dev_s *dev, uint32_t irq); +static void nrf52_radio_intclr(struct nrf52_radio_dev_s *dev, uint32_t irq); +static void nrf52_radio_shorts(struct nrf52_radio_dev_s *dev, uint32_t sh); static int nrf52_radio_power(struct nrf52_radio_dev_s *dev, bool state); static int nrf52_radio_mode_set(struct nrf52_radio_dev_s *dev, uint8_t mode); static int nrf52_radio_freq_set(struct nrf52_radio_dev_s *dev, uint32_t freq); static int nrf52_radio_rssi_get(struct nrf52_radio_dev_s *dev, - int *rssi); + int8_t *rssi); static int nrf52_radio_txpower_set(struct nrf52_radio_dev_s *dev, uint8_t txpower); -static int nrf52_radio_tifs_set(struct nrf52_radio_dev_s *dev, - uint16_t us); +static int nrf52_radio_tifs_set(struct nrf52_radio_dev_s *dev, uint16_t us); static int nrf52_radio_pkt_cfg(struct nrf52_radio_dev_s *dev, struct nrf52_radio_pktcfg_s *cfg); static int nrf52_radio_crc_cfg(struct nrf52_radio_dev_s *dev, @@ -83,22 +77,15 @@ static int nrf52_radio_white_set(struct nrf52_radio_dev_s *dev, uint8_t init); static int nrf52_radio_addr_set(struct nrf52_radio_dev_s *dev, uint8_t i, struct nrf52_radio_addr_s *addr); -static int nrf52_radio_write(struct nrf52_radio_dev_s *dev, - uint8_t *buf, int len); -static int nrf52_radio_read(struct nrf52_radio_dev_s *dev, - uint8_t *buf, int len); static void nrf52_radio_dumpregs(struct nrf52_radio_dev_s *dev); -/* Radio interrupts *********************************************************/ - -static int nrf52_radio_isr(int irq, void *context, void *arg); -static int nrf52_radio_isr_rx(struct nrf52_radio_dev_s *dev); -static int nrf52_radio_isr_tx(struct nrf52_radio_dev_s *dev); - -/* Radio configuration ******************************************************/ - -static int nrf52_radio_setup(struct nrf52_radio_dev_s *dev); -static int nrf52_radio_reset(struct nrf52_radio_dev_s *dev); +#ifdef CONFIG_NRF52_HAVE_IEEE802154 +static void nrf52_radio_sfd_set(struct nrf52_radio_dev_s *dev, uint8_t sfd); +static void nrf52_radio_edcnt_set(struct nrf52_radio_dev_s *dev, + uint32_t edcnt); +static void nrf52_radio_cca_cfg(struct nrf52_radio_dev_s *dev, + struct nrf52_radio_cca_s *cca); +#endif /**************************************************************************** * Private Data @@ -107,8 +94,14 @@ static int nrf52_radio_reset(struct nrf52_radio_dev_s *dev); /* NRF52 radio operations */ struct nrf52_radio_dev_s; -struct nrf52_radio_ops_s g_nrf52_radio_ops = +static struct nrf52_radio_ops_s g_nrf52_radio_ops = { + .reset = nrf52_radio_reset, + .putreg = nrf52_radio_putreg, + .getreg = nrf52_radio_getreg, + .inten = nrf52_radio_inten, + .intclr = nrf52_radio_intclr, + .shorts = nrf52_radio_shorts, .power = nrf52_radio_power, .mode_set = nrf52_radio_mode_set, .freq_set = nrf52_radio_freq_set, @@ -119,33 +112,23 @@ struct nrf52_radio_ops_s g_nrf52_radio_ops = .white_set = nrf52_radio_white_set, .crc_cfg = nrf52_radio_crc_cfg, .addr_set = nrf52_radio_addr_set, - .read = nrf52_radio_read, - .write = nrf52_radio_write, - .dumpregs = nrf52_radio_dumpregs + .dumpregs = nrf52_radio_dumpregs, +#ifdef CONFIG_NRF52_HAVE_IEEE802154 + .sfd_set = nrf52_radio_sfd_set, + .edcnt_set = nrf52_radio_edcnt_set, + .cca_cfg = nrf52_radio_cca_cfg, +#endif }; -/* RX buffer 1 */ - -uint8_t g_nrf52_radio_dev_rx1[NRF52_RADIO_RXBUFFER]; - -/* TX buffer 1 */ - -uint8_t g_nrf52_radio_dev_tx1[NRF52_RADIO_TXBUFFER]; - /* Radio device 1 */ -struct nrf52_radio_dev_s g_nrf52_radio_dev_1 = +static struct nrf52_radio_dev_s g_nrf52_radio_dev_1 = { .ops = &g_nrf52_radio_ops, .irq = NRF52_IRQ_RADIO, .base = NRF52_RADIO_BASE, .mode = 0, - .rxbuf_len = NRF52_RADIO_RXBUFFER, - .txbuf_len = NRF52_RADIO_TXBUFFER, - .rxbuf = g_nrf52_radio_dev_rx1, - .txbuf = g_nrf52_radio_dev_tx1, .lock = NXMUTEX_INITIALIZER, - .sem_isr = SEM_INITIALIZER(0), }; /**************************************************************************** @@ -181,6 +164,45 @@ static uint32_t nrf52_radio_getreg(struct nrf52_radio_dev_s *dev, return getreg32(dev->base + offset); } +/**************************************************************************** + * Name: nrf52_radio_inten + * + * Description: + * Enable interrupts. + * + ****************************************************************************/ + +static void nrf52_radio_inten(struct nrf52_radio_dev_s *dev, uint32_t irq) +{ + nrf52_radio_putreg(dev, NRF52_RADIO_INTENSET_OFFSET, irq); +} + +/**************************************************************************** + * Name: nrf52_radio_intclr + * + * Description: + * Disable interrupts. + * + ****************************************************************************/ + +static void nrf52_radio_intclr(struct nrf52_radio_dev_s *dev, uint32_t irq) +{ + nrf52_radio_putreg(dev, NRF52_RADIO_INTENCLR_OFFSET, irq); +} + +/**************************************************************************** + * Name: nrf52_radio_shorts + * + * Description: + * Configure RADIO shorts + * + ****************************************************************************/ + +static void nrf52_radio_shorts(struct nrf52_radio_dev_s *dev, uint32_t sh) +{ + nrf52_radio_putreg(dev, NRF52_RADIO_SHORTS_OFFSET, sh); +} + /**************************************************************************** * Name: nrf52_radio_power * @@ -234,7 +256,12 @@ static int nrf52_radio_mode_set(struct nrf52_radio_dev_s *dev, /* Check if mode is valid */ - if (mode > NRF52_RADIO_MODE_IEEE802154) +#ifndef CONFIG_NRF52_HAVE_IEEE802154 + if (mode >= NRF52_RADIO_MODE_LAST) +#else + if (mode >= NRF52_RADIO_MODE_LAST && + mode != NRF52_RADIO_MODE_IEEE802154) +#endif { wlerr("ERROR: unsupported RADIO mode %d\n", mode); ret = -EINVAL; @@ -272,7 +299,7 @@ static int nrf52_radio_freq_set(struct nrf52_radio_dev_s *dev, if (freq < 2360 || freq > 2500) { - wlerr("ERROR: unsupported radio frequency %d MHz\n", freq); + wlerr("ERROR: unsupported radio frequency %" PRId32" MHz\n", freq); ret = -EINVAL; goto errout; } @@ -282,6 +309,11 @@ static int nrf52_radio_freq_set(struct nrf52_radio_dev_s *dev, if (freq < 2400) { regval |= RADIO_FREQUENCY_MAP_2360MHZ; + freq -= 2360; + } + else + { + freq -= 2400; } regval |= freq; @@ -300,14 +332,13 @@ static int nrf52_radio_freq_set(struct nrf52_radio_dev_s *dev, ****************************************************************************/ static int nrf52_radio_rssi_get(struct nrf52_radio_dev_s *dev, - int *rssi) + int8_t *rssi) { uint32_t regval = 0; /* Start the RSSI meassurement */ - nrf52_radio_putreg(dev, NRF52_RADIO_TASKS_RSSISTART_OFFSET, - RADIO_TASKS_RSSISTART); + nrf52_radio_putreg(dev, NRF52_RADIO_TASKS_RSSISTART_OFFSET, 1); /* Wait for the RSSI sample */ @@ -316,7 +347,7 @@ static int nrf52_radio_rssi_get(struct nrf52_radio_dev_s *dev, /* Get the RSSI sample */ regval = nrf52_radio_getreg(dev, NRF52_RADIO_RSSISAMPLE_OFFSET); - *rssi = -(int)regval; + *rssi = -(int8_t)regval; return OK; } @@ -382,13 +413,13 @@ static int nrf52_radio_addr_set(struct nrf52_radio_dev_s *dev, uint8_t i, /* Get current BASE and PREFIX registers */ base_now = nrf52_radio_getreg(dev, basereg); + UNUSED(base_now); prefix_now = nrf52_radio_getreg(dev, prefixreg); /* TODO: check if new address match to old BASE1 */ if (basereg == NRF52_RADIO_BASE1_OFFSET) { -#warning missing logic! } /* Get new BASE */ @@ -457,8 +488,7 @@ static int nrf52_radio_txpower_set(struct nrf52_radio_dev_s *dev, * ****************************************************************************/ -static int nrf52_radio_tifs_set(struct nrf52_radio_dev_s *dev, - uint16_t us) +static int nrf52_radio_tifs_set(struct nrf52_radio_dev_s *dev, uint16_t us) { int ret = OK; @@ -496,7 +526,7 @@ static int nrf52_radio_pkt_cfg(struct nrf52_radio_dev_s *dev, { uint32_t pcnf0 = 0; uint32_t pcnf1 = 0; - int ret = OK; + int ret = OK; /* LENGTH field length */ @@ -532,6 +562,7 @@ static int nrf52_radio_pkt_cfg(struct nrf52_radio_dev_s *dev, pcnf0 &= (~RADIO_PCNF0_S1INCL); +#ifdef HAVE_RADIO_BLELR /* Configure code indicator length */ if (cfg->ci_len > RADIO_PCNF0_CILEN_MAX) @@ -565,6 +596,7 @@ static int nrf52_radio_pkt_cfg(struct nrf52_radio_dev_s *dev, /* Include CRC in LENGTH or not */ pcnf0 |= (cfg->crcinc << RADIO_PCNF0_CRCINC_SHIFT); +#endif /* Configure maximum payload length */ @@ -588,14 +620,17 @@ static int nrf52_radio_pkt_cfg(struct nrf52_radio_dev_s *dev, /* Configure base address length */ - if (cfg->bal_len < RADIO_PCNF1_BALEN_MIN || - cfg->bal_len > RADIO_PCNF1_BALEN_MAX) + if (cfg->bal_len) { - ret = -EINVAL; - goto errout; - } + if (cfg->bal_len < RADIO_PCNF1_BALEN_MIN || + cfg->bal_len > RADIO_PCNF1_BALEN_MAX) + { + ret = -EINVAL; + goto errout; + } - pcnf1 |= (cfg->bal_len << RADIO_PCNF1_BALEN_SHIFT); + pcnf1 |= (cfg->bal_len << RADIO_PCNF1_BALEN_SHIFT); + } /* Configure on-air endianness of packet */ @@ -714,126 +749,6 @@ static int nrf52_radio_crc_cfg(struct nrf52_radio_dev_s *dev, return ret; } -/**************************************************************************** - * Name: nrf52_radio_write - * - * Description: - * Write radio packet - * - ****************************************************************************/ - -static int nrf52_radio_write(struct nrf52_radio_dev_s *dev, - uint8_t *buf, int len) -{ - int ret = OK; - - /* Lock device */ - - ret = nxmutex_lock(&dev->lock); - if (ret < 0) - { - return ret; - } - - /* */ - - if (len > dev->txbuf_len) - { - ret = -ENOMEM; - goto errout; - } - - /* Copy packet */ - - memcpy(dev->txbuf, buf, len); - - /* Set packet pointer */ - - DEBUGASSERT(nrf52_easydma_valid(&dev->txbuf)); - nrf52_radio_putreg(dev, NRF52_RADIO_PACKETPTR_OFFSET, &dev->txbuf); - - /* Set state to TX */ - - dev->state = NRF52_RADIO_STATE_TX; - - /* Start TX. - * NOTE: shortcut between READ and START is enabled. - */ - - nrf52_radio_putreg(dev, NRF52_RADIO_TASKS_TXEN_OFFSET, RADIO_TASKS_TXEN); - - /* Wait for IRQ */ - - ret = nxsem_wait(&dev->sem_isr); - -errout: - - /* Unlock device */ - - nxmutex_unlock(&dev->lock); - return ret; -} - -/**************************************************************************** - * Name: nrf52_radio_read - * - * Description: - * Read radio packet - * - ****************************************************************************/ - -static int nrf52_radio_read(struct nrf52_radio_dev_s *dev, - uint8_t *buf, int len) -{ - int ret = OK; - - /* Lock radio */ - - ret = nxmutex_lock(&dev->lock); - if (ret < 0) - { - return ret; - } - - /* */ - - if (len > dev->rxbuf_len) - { - ret = -ENOMEM; - goto errout; - } - - /* Set packet pointer */ - - DEBUGASSERT(nrf52_easydma_valid(&dev->rxbuf)); - nrf52_radio_putreg(dev, NRF52_RADIO_PACKETPTR_OFFSET, &dev->rxbuf); - - /* Set state to RX */ - - dev->state = NRF52_RADIO_STATE_RX; - - /* Start RX. - * NOTE: shortcut between READ and START is enabled. - */ - - nrf52_radio_putreg(dev, NRF52_RADIO_TASKS_RXEN_OFFSET, RADIO_TASKS_RXEN); - - /* Wait for IRQ */ - - ret = nxsem_wait(&dev->sem_isr); - - /* Copy packet */ - - memcpy(buf, dev->rxbuf, len); - -errout: - - /* Unlock radio */ - - nxmutex_unlock(&dev->lock); - return ret; -} - /**************************************************************************** * Name: nrf52_radio_dumpregs * @@ -846,250 +761,176 @@ static void nrf52_radio_dumpregs(struct nrf52_radio_dev_s *dev) { printf("\nnrf52_radio_dumpregs:\n"); - printf("SHORTS 0x%08x\n", + printf("SHORTS 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_SHORTS_OFFSET)); - printf("INTENSET 0x%08x\n", + printf("INTENSET 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_INTENSET_OFFSET)); - printf("CRCSTATUS 0x%08x\n", + printf("CRCSTATUS 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_CRCSTATUS_OFFSET)); - printf("RXMATCH 0x%08x\n", + printf("RXMATCH 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_RXMATCH_OFFSET)); - printf("RXCRC 0x%08x\n", + printf("RXCRC 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_RXCRC_OFFSET)); - printf("DAI 0x%08x\n", + printf("DAI 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DAI_OFFSET)); - printf("PDUSTAT 0x%08x\n", + printf("PDUSTAT 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_PDUSTAT_OFFSET)); - printf("PACKETPTR 0x%08x\n", + printf("PACKETPTR 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_PACKETPTR_OFFSET)); - printf("FREQUENCY 0x%08x\n", + printf("FREQUENCY 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_FREQUENCY_OFFSET)); - printf("TXPOWER 0x%08x\n", + printf("TXPOWER 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_TXPOWER_OFFSET)); - printf("MODE 0x%08x\n", + printf("MODE 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_MODE_OFFSET)); - printf("PCNF0 0x%08x\n", + printf("PCNF0 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_PCNF0_OFFSET)); - printf("PCNF1 0x%08x\n", + printf("PCNF1 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_PCNF1_OFFSET)); - printf("BASE0 0x%08x\n", + printf("BASE0 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_BASE0_OFFSET)); - printf("BASE1 0x%08x\n", + printf("BASE1 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_BASE1_OFFSET)); - printf("PREFIX0 0x%08x\n", + printf("PREFIX0 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_PREFIX0_OFFSET)); - printf("PREFIX1 0x%08x\n", + printf("PREFIX1 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_PREFIX1_OFFSET)); - printf("TXADDRESS 0x%08x\n", + printf("TXADDRESS 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_TXADDRESS_OFFSET)); - printf("RXADDRESS 0x%08x\n", - nrf52_radio_getreg(dev, NRF52_RADIO_RXADDRESS_OFFSET)); - printf("CRCCNF 0x%08x\n", + printf("RXADDRESSES 0x%08" PRIx32 "\n", + nrf52_radio_getreg(dev, NRF52_RADIO_RXADDRESSES_OFFSET)); + printf("CRCCNF 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_CRCCNF_OFFSET)); - printf("CRCPOLY 0x%08x\n", + printf("CRCPOLY 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_CRCPOLY_OFFSET)); - printf("CRCINIT 0x%08x\n", + printf("CRCINIT 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_CRCINIT_OFFSET)); - printf("TIFS 0x%08x\n", + printf("TIFS 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_TIFS_OFFSET)); - printf("RSSISAMPLE 0x%08x\n", + printf("RSSISAMPLE 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_RSSISAMPLE_OFFSET)); - printf("STATE 0x%08x\n", + printf("STATE 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_STATE_OFFSET)); - printf("DATAWHITEIV 0x%08x\n", + printf("DATAWHITEIV 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DATAWHITEIV_OFFSET)); - printf("BCC 0x%08x\n", + printf("BCC 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_BCC_OFFSET)); - printf("DAB0 0x%08x\n", + printf("DAB0 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DAB_OFFSET(0))); - printf("DAB1 0x%08x\n", + printf("DAB1 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DAB_OFFSET(1))); - printf("DAB2 0x%08x\n", + printf("DAB2 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DAB_OFFSET(2))); - printf("DAB3 0x%08x\n", + printf("DAB3 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DAB_OFFSET(3))); - printf("DAB4 0x%08x\n", + printf("DAB4 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DAB_OFFSET(4))); - printf("DAB5 0x%08x\n", + printf("DAB5 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DAB_OFFSET(5))); - printf("DAB6 0x%08x\n", + printf("DAB6 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DAB_OFFSET(6))); - printf("DAB7 0x%08x\n", + printf("DAB7 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DAB_OFFSET(6))); - printf("DAP0 0x%08x\n", + printf("DAP0 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DAP_OFFSET(0))); - printf("DAP1 0x%08x\n", + printf("DAP1 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DAP_OFFSET(1))); - printf("DAP2 0x%08x\n", + printf("DAP2 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DAP_OFFSET(2))); - printf("DAP3 0x%08x\n", + printf("DAP3 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DAP_OFFSET(3))); - printf("DAP4 0x%08x\n", + printf("DAP4 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DAP_OFFSET(4))); - printf("DAP5 0x%08x\n", + printf("DAP5 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DAP_OFFSET(5))); - printf("DAP6 0x%08x\n", + printf("DAP6 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DAP_OFFSET(6))); - printf("DAP7 0x%08x\n", + printf("DAP7 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DAP_OFFSET(6))); - printf("DACNF 0x%08x\n", + printf("DACNF 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_DACNF_OFFSET)); - printf("MHRMATCHCONF 0x%08x\n", + printf("MHRMATCHCONF 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_MHRMATCHCONF_OFFSET)); - printf("MHRMATCHMAS 0x%08x\n", + printf("MHRMATCHMAS 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_MHRMATCHMAS_OFFSET)); - printf("MODECNF0 0x%08x\n", + printf("MODECNF0 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_MODECNF0_OFFSET)); - printf("SFD 0x%08x\n", + printf("SFD 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_SFD_OFFSET)); - printf("EDCNT 0x%08x\n", + printf("EDCNT 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_EDCNT_OFFSET)); - printf("EDSAMPLE 0x%08x\n", + printf("EDSAMPLE 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_EDSAMPLE_OFFSET)); - printf("CCACTRL 0x%08x\n", + printf("CCACTRL 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_CCACTRL_OFFSET)); - printf("POWER 0x%08x\n", + printf("POWER 0x%08" PRIx32 "\n", nrf52_radio_getreg(dev, NRF52_RADIO_POWER_OFFSET)); } -/**************************************************************************** - * Name: nrf52_radio_isr_rx - * - * Description: - * RX radio interrupt handler - * - ****************************************************************************/ - -static int nrf52_radio_isr_rx(struct nrf52_radio_dev_s *dev) -{ - /* RX done */ - - nxsem_post(&dev->sem_isr); - - return OK; -} +#ifdef CONFIG_NRF52_HAVE_IEEE802154 /**************************************************************************** - * Name: nrf52_radio_isr_tx + * Name: nrf52_radio_sfd_set * * Description: - * TX radio interrupt handler + * Set SFD. * ****************************************************************************/ -static int nrf52_radio_isr_tx(struct nrf52_radio_dev_s *dev) +static void nrf52_radio_sfd_set(struct nrf52_radio_dev_s *dev, uint8_t sfd) { - /* TX done */ - - nxsem_post(&dev->sem_isr); - - return OK; + nrf52_radio_putreg(dev, NRF52_RADIO_SFD_OFFSET, sfd); } /**************************************************************************** - * Name: nrf52_radio_isr + * Name: nrf52_radio_edcnt_set * * Description: - * Radio interrupt handler + * Set EDCNT. * ****************************************************************************/ -static int nrf52_radio_isr(int irq, void *context, void *arg) +static void nrf52_radio_edcnt_set(struct nrf52_radio_dev_s *dev, + uint32_t edcnt) { - struct nrf52_radio_dev_s *dev = (struct nrf52_radio_dev_s *)arg; - int ret = OK; - uint32_t state = 0; - - DEBUGASSERT(dev); - - /* Get radio state */ - - wlinfo("RADIO ISR STATE=%d\n", dev->state); - - /* Handle radio state */ - - switch (dev->state) - { - case NRF52_RADIO_STATE_RX: - { - /* Transmit DONE */ - - ret = nrf52_radio_isr_rx(dev); - - break; - } - - case NRF52_RADIO_STATE_TX: - { - /* Receive DONE */ - - ret = nrf52_radio_isr_tx(dev); - - break; - } - - case NRF52_RADIO_STATE_DISABLED: - { - break; - } - - default: - { - PANIC(); - break; - } - } - - /* Clear END event */ - - nrf52_radio_putreg(dev, NRF52_RADIO_EVENTS_END_OFFSET, 0); - - /* Update radio state - * NOTE: shortcut between END and DISABLE is enabled. - */ - - dev->state = NRF52_RADIO_STATE_DISABLED; - - return ret; + nrf52_radio_putreg(dev, NRF52_RADIO_EDCNT_OFFSET, edcnt); } /**************************************************************************** - * Name: nrf52_radio_setup + * Name: nrf52_radio_cca_cfg * * Description: - * Initial RADIO setup + * Set CCA configuration * ****************************************************************************/ -static int nrf52_radio_setup(struct nrf52_radio_dev_s *dev) +static void nrf52_radio_cca_cfg(struct nrf52_radio_dev_s *dev, + struct nrf52_radio_cca_s *cca) { uint32_t regval = 0; - int ret = OK; - DEBUGASSERT(dev); + /* CCA mode of operation */ - /* Configure interrupts: - * 1. END - packet sent or received - */ + regval |= (cca->mode << 0); - regval = (RADIO_INT_END); - nrf52_radio_putreg(dev, NRF52_RADIO_INTENSET_OFFSET, regval); + /* CCA energy busy threshold */ - /* Configure shortucts: - * 1. shortcut between READY and START - * 2. shortcut between END and DISABLE - */ + regval |= ((cca->edthres << RADIO_CCACTRL_CCAEDTHRES_SHIFT) + & RADIO_CCACTRL_CCAEDTHRES_MASK); - regval = RADIO_SHORTS_READY_START; - regval |= RADIO_SHORTS_END_DISABLE; - nrf52_radio_putreg(dev, NRF52_RADIO_SHORTS_OFFSET, regval); + /* CCA correlator busy threshold */ - /* Power on radio */ + regval |= ((cca->corrthres << RADIO_CCACTRL_CCACORRTHRES_SHIFT) + & RADIO_CCACTRL_CCACORRTHRES_MASK); - nrf52_radio_power(dev, true); + /* Limit for occurances above CCACORRTHRES */ - return ret; + regval |= ((cca->corrcnt << RADIO_CCACTRL_CCACORRCNT_SHIFT) + & RADIO_CCACTRL_CCACORRCNT_MASK); + + nrf52_radio_putreg(dev, NRF52_RADIO_CCACTRL_OFFSET, regval); } +#endif /**************************************************************************** * Name: nrf52_radio_reset @@ -1099,21 +940,22 @@ static int nrf52_radio_setup(struct nrf52_radio_dev_s *dev) * ****************************************************************************/ -static int nrf52_radio_reset(struct nrf52_radio_dev_s *dev) +static void nrf52_radio_reset(struct nrf52_radio_dev_s *dev) { /* Turn off radio power */ nrf52_radio_power(dev, false); - - /* Wait some time */ - - nxsig_usleep(100000); - - /* Turn on radio power */ - + up_udelay(100); nrf52_radio_power(dev, true); + up_udelay(100); - return OK; + /* Reset radio state */ + + dev->mode = 0; + dev->tifs = 0; + dev->txpower = 0; + memset(&dev->pktcfg, 0, sizeof(dev->pktcfg)); + memset(&dev->addr, 0, sizeof(dev->addr)); } /**************************************************************************** @@ -1132,7 +974,6 @@ struct nrf52_radio_dev_s * nrf52_radio_initialize(int intf, struct nrf52_radio_board_s *board) { struct nrf52_radio_dev_s *dev = NULL; - int ret = OK; /* Get radio interface */ @@ -1157,13 +998,6 @@ nrf52_radio_initialize(int intf, struct nrf52_radio_board_s *board) /* Reset some data */ memset(&dev->pktcfg, 0, sizeof(struct nrf52_radio_pktcfg_s)); - memset(dev->rxbuf, 0, NRF52_RADIO_RXBUFFER); - memset(dev->txbuf, 0, NRF52_RADIO_TXBUFFER); - - /* Attach radio interrupt */ - - irq_attach(dev->irq, nrf52_radio_isr, dev); - up_enable_irq(dev->irq); /* Connect board-specific data */ @@ -1171,21 +1005,7 @@ nrf52_radio_initialize(int intf, struct nrf52_radio_board_s *board) /* Reset radio */ - ret = nrf52_radio_reset(dev); - if (ret < 0) - { - wlerr("ERROR: failed to reset radio interface %d\n", ret); - goto errout; - } - - /* Initial radio setup */ - - ret = nrf52_radio_setup(dev); - if (ret < 0) - { - wlerr("ERROR: failed to setup radio interface %d\n", ret); - goto errout; - } + nrf52_radio_reset(dev); return dev; diff --git a/arch/arm/src/nrf52/nrf52_radio.h b/arch/arm/src/nrf52/nrf52_radio.h index a0e01804d629f..aadca4cbd95cf 100644 --- a/arch/arm/src/nrf52/nrf52_radio.h +++ b/arch/arm/src/nrf52/nrf52_radio.h @@ -40,6 +40,29 @@ #define NRF52_RADIO_LOGICAL_ADDRESS_MAX (8) +/* Ops */ + +#define NRF52_RADIO_RESET(lower) lower->ops->reset(lower) +#define NRF52_RADIO_PUTREG(lower, o, v) lower->ops->putreg(lower, o, v) +#define NRF52_RADIO_GETREG(lower, o) lower->ops->getreg(lower, o) +#define NRF52_RADIO_INTEN(lower, i) lower->ops->inten(lower, i) +#define NRF52_RADIO_INTCLR(lower, i) lower->ops->intclr(lower, i) +#define NRF52_RADIO_SHRTSET(lower, s) lower->ops->shorts(lower, s) +#define NRF52_RADIO_PWRSET(lower, pwr) lower->ops->power(lower, pwr) +#define NRF52_RADIO_MODESET(lower, m) lower->ops->mode_set(lower, m) +#define NRF52_RADIO_FREQSET(lower, f) lower->ops->freq_set(lower, f) +#define NRF52_RADIO_RSSIGET(lower, r) lower->ops->rssi_get(lower, r) +#define NRF52_RADIO_TXPWRSET(lower, p) lower->ops->txpower_set(lower, p) +#define NRF52_RADIO_TIFSSET(lower, p) lower->ops->tifs_set(lower, t) +#define NRF52_RADIO_PKTCFG(lower, cfg) lower->ops->pkt_cfg(lower, cfg) +#define NRF52_RADIO_CRCCFG(lower, cfg) lower->ops->crc_cfg(lower, cfg) +#define NRF52_RADIO_WHITESET(lower, cfg) lower->ops->white_set(lower, c) +#define NRF52_RADIO_ADDRSET(lower, i, a) lower->ops->addr_set(lower, i, a) +#define NRF52_RADIO_DUMPREGS(lower) lower->ops->dumpregs(lower) +#define NRF52_RADIO_SFDSET(lower, sfd) lower->ops->sfd_set(lower, sfd) +#define NRF52_RADIO_EDCNTSET(lower, ec) lower->ops->edcnt_set(lower, ec) +#define NRF52_RADIO_CCACFG(lower, cca) lower->ops->cca_cfg(lower, cca) + /**************************************************************************** * Public Types ****************************************************************************/ @@ -50,20 +73,18 @@ enum nrf52_radio_mode_e { NRF52_RADIO_MODE_NRF1MBIT = 0, NRF52_RADIO_MODE_NRF2MBIT = 1, - NRF52_RADIO_MODE_BLE1MBIT = 2, - NRF52_RADIO_MODE_BLE2MBIT = 3, - NRF52_RADIO_MODE_BLELR125KBIT = 4, - NRF52_RADIO_MODE_BLELR500KBIT = 5, - NRF52_RADIO_MODE_IEEE802154 = 6 -}; - -/* Radio state */ - -enum nrf52_radio_state_e -{ - NRF52_RADIO_STATE_DISABLED = 0, - NRF52_RADIO_STATE_TX = 1, - NRF52_RADIO_STATE_RX = 2, + NRF52_RADIO_MODE_NRF250KBIT = 2, + NRF52_RADIO_MODE_BLE1MBIT = 3, + NRF52_RADIO_MODE_BLE2MBIT = 4, +#ifdef CONFIG_NRF52_HAVE_BLELR + NRF52_RADIO_MODE_BLELR125KBIT = 5, + NRF52_RADIO_MODE_BLELR500KBIT = 6, +#endif + NRF52_RADIO_MODE_LAST, + +#ifdef CONFIG_NRF52_HAVE_IEEE802154 + NRF52_RADIO_MODE_IEEE802154 = 15 +#endif }; /* Preamble configuration */ @@ -95,7 +116,18 @@ enum nrf52_radio_crc_skipaddr_e NRF52_RADIO_CRC_SKIPADDR_IEEE802154 = 2, }; -/* On air packet layout: +/* CCA mode of operation */ + +enum nrf52_radio_cca_mode_e +{ + NRF52_RADIO_CCA_ED = 0, + NRF52_RADIO_CCA_CARRIER = 1, + NRF52_RADIO_CCA_CARRIER_AND_ED = 2, + NRF52_RADIO_CCA_CARRIER_OR_ED = 2, + NRF52_RADIO_CCA_EDTEST1 = 4, +}; + +/* On air packet layout (no IEEE802154 mode): * * +---------------------------------------+ * | FIRST | @@ -105,7 +137,6 @@ enum nrf52_radio_crc_skipaddr_e * | | ADDRESS | | | * +----------+---------------+----+-------+ * - * * +----------------------------+ * | Stored on RAM | * |----+--------+----+---------| @@ -122,6 +153,20 @@ enum nrf52_radio_crc_skipaddr_e * | | | * +-------+-------+ * + * For IEEE802154 mode packet layout is different: + * + * +--------------------------------------------------------------------+ + * | PHY protocol data unit (PPDU) | + * +--------------------+-----+---------+-------------------------------+ + * | Preamble sequence | SFD | Lenght | PHY payload | + * |--------------------+-----+---------+-------------------------------+ + * | 5 octets synchronization | 1 octet | Maximum 127 octets (PSDU) | + * | header (SHR) | (PHR) +-------------------------------+ + * | | | MAC protocol data unit (MPDU) | + * +--------------------------+---------+-------------------------------+ + * | Stored on RAM | + * +-----------------------------------------+ + * */ /* Radio packet configuration */ @@ -166,11 +211,49 @@ struct nrf52_radio_addr_s uint8_t a4; /* BASE[3] */ }; +#ifdef CONFIG_NRF52_HAVE_IEEE802154 + +/* IEEE 802.15.4 clear channel assessment control */ + +struct nrf52_radio_cca_s +{ + uint8_t mode; /* CCA mode of operation */ + uint8_t edthres; /* CCA energy busy threshold */ + uint8_t corrthres; /* CCA correlator busy threshold */ + uint8_t corrcnt; /* Limit for occurances above CCACORRTHRES */ +}; +#endif + /* NRF52 radio operations */ struct nrf52_radio_dev_s; struct nrf52_radio_ops_s { + /* Reset radio */ + + void (*reset)(struct nrf52_radio_dev_s *dev); + + /* Put register value */ + + void (*putreg)(struct nrf52_radio_dev_s *dev, uint32_t offset, + uint32_t value); + + /* Get register value */ + + uint32_t (*getreg)(struct nrf52_radio_dev_s *dev, uint32_t offset); + + /* Enable interrupts */ + + void (*inten)(struct nrf52_radio_dev_s *dev, uint32_t irq); + + /* Disable interrupts */ + + void (*intclr)(struct nrf52_radio_dev_s *dev, uint32_t irq); + + /* Configure shorts */ + + void (*shorts)(struct nrf52_radio_dev_s *dev, uint32_t irq); + /* Turn-on/turn-off radio power */ int (*power)(struct nrf52_radio_dev_s *dev, bool state); @@ -185,7 +268,7 @@ struct nrf52_radio_ops_s /* Get RSSI sample */ - int (*rssi_get)(struct nrf52_radio_dev_s *dev, int *rssi); + int (*rssi_get)(struct nrf52_radio_dev_s *dev, int8_t *rssi); /* Set TX power */ @@ -214,19 +297,24 @@ struct nrf52_radio_ops_s int (*addr_set)(struct nrf52_radio_dev_s *dev, uint8_t i, struct nrf52_radio_addr_s *addr); - /* Read packet */ + /* Dump radio registers */ + + void (*dumpregs)(struct nrf52_radio_dev_s *dev); - int (*read)(struct nrf52_radio_dev_s *dev, - uint8_t *buf, int len); +#ifdef CONFIG_NRF52_HAVE_IEEE802154 + /* IEEE 802.15.4 start of frame delimiter */ - /* Write packet */ + void (*sfd_set)(struct nrf52_radio_dev_s *dev, uint8_t sfd); - int (*write)(struct nrf52_radio_dev_s *dev, - uint8_t *buf, int len); + /* IEEE 802.15.4 energy detect level */ - /* Dump radio registers */ + void (*edcnt_set)(struct nrf52_radio_dev_s *dev, uint32_t edcnt); - void (*dumpregs)(struct nrf52_radio_dev_s *dev); + /* IEEE 802.15.4 clear channel assessment control */ + + void (*cca_cfg)(struct nrf52_radio_dev_s *dev, + struct nrf52_radio_cca_s *cca); +#endif }; /* NRF52 radio board specific data */ @@ -247,18 +335,10 @@ struct nrf52_radio_dev_s uint32_t base; /* Radio base */ uint32_t irq; /* Radio IRQ number */ uint8_t mode; /* Radio mode */ - uint8_t state; /* Radio state */ struct nrf52_radio_pktcfg_s pktcfg; /* Current packet */ - uint16_t rxbuf_len; /* RX buffer length */ - uint16_t txbuf_len; /* TX buffer length */ - uint8_t *rxbuf; /* RX buffer */ - uint8_t *txbuf; /* TX buffer */ mutex_t lock; /* Mutual exclusion mutex */ - sem_t sem_isr; /* Interrupt wait semaphore */ uint16_t tifs; /* Interframe spacing time */ uint8_t txpower; /* TX power */ - uint8_t txaddr; /* TX address */ - uint8_t rxaddr; /* RX addresses */ struct nrf52_radio_addr_s addr[NRF52_RADIO_LOGICAL_ADDRESS_MAX]; }; diff --git a/arch/arm/src/nrf52/nrf52_radio_ieee802154.h b/arch/arm/src/nrf52/nrf52_radio_ieee802154.h new file mode 100644 index 0000000000000..7160378a50efd --- /dev/null +++ b/arch/arm/src/nrf52/nrf52_radio_ieee802154.h @@ -0,0 +1,53 @@ +/**************************************************************************** + * arch/arm/src/nrf52/nrf52_radio_ieee802154.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_NRF52_NRF52_RADIO_IEEE802154_H +#define __ARCH_ARM_SRC_NRF52_NRF52_RADIO_IEEE802154_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "nrf52_radio.h" + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_radioi8_register + * + * Description: + * Register NRF52 radio in IEEE802154 mode + * + ****************************************************************************/ + +struct ieee802154_radio_s * +nrf52_radioi8_register(struct nrf52_radio_board_s *board); + +#endif /* __ARCH_ARM_SRC_NRF52_NRF52_RADIO_IEEE802154_H */ diff --git a/arch/arm/src/nrf52/nrf52_rtc.h b/arch/arm/src/nrf52/nrf52_rtc.h index 8814b9e2040c8..38ed737c38824 100644 --- a/arch/arm/src/nrf52/nrf52_rtc.h +++ b/arch/arm/src/nrf52/nrf52_rtc.h @@ -27,6 +27,8 @@ #include +#include + #include /**************************************************************************** @@ -78,12 +80,12 @@ enum nrf52_rtc_cc_e enum nrf52_rtc_evt_e { - NRF52_RTC_EVT_TICK = 0, - NRF52_RTC_EVT_OVRFLW = 1, - NRF52_RTC_EVT_COMPARE0 = 2, - NRF52_RTC_EVT_COMPARE1 = 3, - NRF52_RTC_EVT_COMPARE2 = 4, - NRF52_RTC_EVT_COMPARE3 = 5, + NRF52_RTC_EVT_COMPARE0 = 0, + NRF52_RTC_EVT_COMPARE1 = 1, + NRF52_RTC_EVT_COMPARE2 = 2, + NRF52_RTC_EVT_COMPARE3 = 3, + NRF52_RTC_EVT_TICK = 4, + NRF52_RTC_EVT_OVRFLW = 5, }; /* NRF52 RTC device */ diff --git a/arch/arm/src/nrf52/nrf52_spi.c b/arch/arm/src/nrf52/nrf52_spi.c index f55e683928678..f98945feb5d92 100644 --- a/arch/arm/src/nrf52/nrf52_spi.c +++ b/arch/arm/src/nrf52/nrf52_spi.c @@ -235,7 +235,7 @@ static const struct spi_ops_s g_spi1ops = # ifdef CONFIG_SPI_EXCHANGE .exchange = nrf52_spi_exchange, # else - .sndlock = nrf52_spi_sndblock, + .sndblock = nrf52_spi_sndblock, .recvblock = nrf52_spi_recvblock, # endif #ifdef CONFIG_SPI_TRIGGER @@ -1164,11 +1164,11 @@ static void nrf52_spi_exchange(struct spi_dev_s *dev, nxsem_wait_uninterruptible(&priv->sem_isr); #endif - if (nrf52_spi_getreg(priv, NRF52_SPIM_TXDAMOUNT_OFFSET) != - transfer_size) + regval = nrf52_spi_getreg(priv, NRF52_SPIM_TXDAMOUNT_OFFSET); + if (regval != transfer_size) { spierr("Incomplete transfer wrote %" PRId32 " expected %zu\n", - regval, nwords); + regval, transfer_size); } /* SPI stop */ diff --git a/arch/arm/src/nrf52/nrf52_tim.c b/arch/arm/src/nrf52/nrf52_tim.c index dfaff60692d7f..25c029440973a 100644 --- a/arch/arm/src/nrf52/nrf52_tim.c +++ b/arch/arm/src/nrf52/nrf52_tim.c @@ -657,7 +657,7 @@ static int nrf52_tim_checkint(struct nrf52_tim_dev_s *dev, uint8_t s) case NRF52_TIM_INT_COMPARE1: { - ret = nrf52_tim_getreg(dev, NRF52_TIM_EVENTS_COMPARE_OFFSET(0)); + ret = nrf52_tim_getreg(dev, NRF52_TIM_EVENTS_COMPARE_OFFSET(1)); break; } diff --git a/arch/arm/src/nrf53/hardware/nrf53_temp.h b/arch/arm/src/nrf53/hardware/nrf53_temp.h index 24f6e12ca1a42..2b0a1910cd302 100644 --- a/arch/arm/src/nrf53/hardware/nrf53_temp.h +++ b/arch/arm/src/nrf53/hardware/nrf53_temp.h @@ -94,4 +94,4 @@ #define NRF53_TEMP_INTENCLR_DATARDY (1 << 0) /* Read: Enabled */ -#endif // __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_TEMP_H +#endif /* __ARCH_ARM_SRC_NRF53_HARDWARE_NRF53_TEMP_H */ diff --git a/arch/arm/src/nrf53/nrf53_gpiote.c b/arch/arm/src/nrf53/nrf53_gpiote.c index 4b79c7f3f5ac4..9db5c6cea0469 100644 --- a/arch/arm/src/nrf53/nrf53_gpiote.c +++ b/arch/arm/src/nrf53/nrf53_gpiote.c @@ -59,8 +59,9 @@ struct nrf53_gpiote_callback_s { - xcpt_t callback; - void *arg; + xcpt_t callback; + void *arg; + uint32_t pinset; }; /**************************************************************************** @@ -501,13 +502,14 @@ int nrf53_gpiote_set_event(uint32_t pinset, flags = enter_critical_section(); - /* Get free channel */ + /* Get free channel or channel already used by pinset */ for (i = 0; i < GPIOTE_CHANNELS; i++) { - if (g_gpiote_ch_callbacks[i].callback == NULL) + if (g_gpiote_ch_callbacks[i].callback == NULL || + g_gpiote_ch_callbacks[i].pinset == pinset) { - /* Configure channel */ + g_gpiote_ch_callbacks[i].pinset = pinset; nrf53_gpiote_set_ch_event(pinset, i, risingedge, fallingedge, diff --git a/arch/arm/src/nrf53/nrf53_rptun.c b/arch/arm/src/nrf53/nrf53_rptun.c index b97c66d7918b8..9e7ba8c20db3a 100644 --- a/arch/arm/src/nrf53/nrf53_rptun.c +++ b/arch/arm/src/nrf53/nrf53_rptun.c @@ -93,7 +93,6 @@ struct nrf53_rptun_dev_s bool master; struct nrf53_rptun_shmem_s *shmem; char cpuname[RPMSG_NAME_SIZE + 1]; - char shmemname[RPMSG_NAME_SIZE + 1]; }; /**************************************************************************** @@ -101,9 +100,6 @@ struct nrf53_rptun_dev_s ****************************************************************************/ static const char *nrf53_rptun_get_cpuname(struct rptun_dev_s *dev); -static const char *nrf53_rptun_get_firmware(struct rptun_dev_s *dev); -static const struct rptun_addrenv_s * -nrf53_rptun_get_addrenv(struct rptun_dev_s *dev); static struct rptun_rsc_s * nrf53_rptun_get_resource(struct rptun_dev_s *dev); static bool nrf53_rptun_is_autostart(struct rptun_dev_s *dev); @@ -127,8 +123,6 @@ static void nrf53_rptun_panic(struct rptun_dev_s *dev); static const struct rptun_ops_s g_nrf53_rptun_ops = { .get_cpuname = nrf53_rptun_get_cpuname, - .get_firmware = nrf53_rptun_get_firmware, - .get_addrenv = nrf53_rptun_get_addrenv, .get_resource = nrf53_rptun_get_resource, .is_autostart = nrf53_rptun_is_autostart, .is_master = nrf53_rptun_is_master, @@ -167,25 +161,6 @@ static const char *nrf53_rptun_get_cpuname(struct rptun_dev_s *dev) return priv->cpuname; } -/**************************************************************************** - * Name: nrf53_rptun_get_firmware - ****************************************************************************/ - -static const char *nrf53_rptun_get_firmware(struct rptun_dev_s *dev) -{ - return NULL; -} - -/**************************************************************************** - * Name: nrf53_rptun_get_addrenv - ****************************************************************************/ - -static const struct rptun_addrenv_s * -nrf53_rptun_get_addrenv(struct rptun_dev_s *dev) -{ - return NULL; -} - /**************************************************************************** * Name: nrf53_rptun_get_resource ****************************************************************************/ @@ -480,7 +455,7 @@ static int nrf53_rptun_thread(int argc, char *argv[]) * Public Functions ****************************************************************************/ -int nrf53_rptun_init(const char *shmemname, const char *cpuname) +int nrf53_rptun_init(const char *cpuname) { struct nrf53_rptun_dev_s *dev = &g_rptun_dev; int ret = OK; @@ -512,7 +487,6 @@ int nrf53_rptun_init(const char *shmemname, const char *cpuname) dev->rptun.ops = &g_nrf53_rptun_ops; strncpy(dev->cpuname, cpuname, RPMSG_NAME_SIZE); - strncpy(dev->shmemname, shmemname, RPMSG_NAME_SIZE); ret = rptun_initialize(&dev->rptun); if (ret < 0) @@ -533,43 +507,3 @@ int nrf53_rptun_init(const char *shmemname, const char *cpuname) errout: return ret; } - -/**************************************************************************** - * Name: up_addrenv_va_to_pa - * - * Description: - * This is needed by openamp/libmetal/lib/system/nuttx/io.c:78. The - * physical memory is mapped as virtual. - * - * Input Parameters: - * va_ - * - * Returned Value: - * va - * - ****************************************************************************/ - -uintptr_t up_addrenv_va_to_pa(void *va) -{ - return (uintptr_t)va; -} - -/**************************************************************************** - * Name: up_addrenv_pa_to_va - * - * Description: - * This is needed by openamp/libmetal/lib/system/nuttx/io.c. The - * physical memory is mapped as virtual. - * - * Input Parameters: - * pa - * - * Returned Value: - * pa - * - ****************************************************************************/ - -void *up_addrenv_pa_to_va(uintptr_t pa) -{ - return (void *)pa; -} diff --git a/arch/arm/src/nrf53/nrf53_rptun.h b/arch/arm/src/nrf53/nrf53_rptun.h index db5eecdb3a20a..038dfaf2c616c 100644 --- a/arch/arm/src/nrf53/nrf53_rptun.h +++ b/arch/arm/src/nrf53/nrf53_rptun.h @@ -50,7 +50,7 @@ extern "C" * Name: nrf53_rptun_init ****************************************************************************/ -int nrf53_rptun_init(const char *shmemname, const char *cpuname); +int nrf53_rptun_init(const char *cpuname); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/nrf53/nrf53_rtc.h b/arch/arm/src/nrf53/nrf53_rtc.h index b086e2972d93d..10e7a00f2cebc 100644 --- a/arch/arm/src/nrf53/nrf53_rtc.h +++ b/arch/arm/src/nrf53/nrf53_rtc.h @@ -27,6 +27,8 @@ #include +#include + #include /**************************************************************************** @@ -78,12 +80,12 @@ enum nrf53_rtc_cc_e enum nrf53_rtc_evt_e { - NRF53_RTC_EVT_TICK = 0, - NRF53_RTC_EVT_OVRFLW = 1, - NRF53_RTC_EVT_COMPARE0 = 2, - NRF53_RTC_EVT_COMPARE1 = 3, - NRF53_RTC_EVT_COMPARE2 = 4, - NRF53_RTC_EVT_COMPARE3 = 5, + NRF53_RTC_EVT_COMPARE0 = 0, + NRF53_RTC_EVT_COMPARE1 = 1, + NRF53_RTC_EVT_COMPARE2 = 2, + NRF53_RTC_EVT_COMPARE3 = 3, + NRF53_RTC_EVT_TICK = 4, + NRF53_RTC_EVT_OVRFLW = 5, }; /* NRF53 RTC device */ diff --git a/arch/arm/src/nrf53/nrf53_spi.c b/arch/arm/src/nrf53/nrf53_spi.c index b15bf6306a23c..89bcf25a86ea4 100644 --- a/arch/arm/src/nrf53/nrf53_spi.c +++ b/arch/arm/src/nrf53/nrf53_spi.c @@ -210,7 +210,7 @@ static const struct spi_ops_s g_spi1ops = # ifdef CONFIG_SPI_EXCHANGE .exchange = nrf53_spi_exchange, # else - .sndlock = nrf53_spi_sndblock, + .sndblock = nrf53_spi_sndblock, .recvblock = nrf53_spi_recvblock, # endif #ifdef CONFIG_SPI_TRIGGER @@ -1158,11 +1158,11 @@ static void nrf53_spi_exchange(struct spi_dev_s *dev, nxsem_wait_uninterruptible(&priv->sem_isr); #endif - if (nrf53_spi_getreg(priv, NRF53_SPIM_TXDAMOUNT_OFFSET) != - transfer_size) + regval = nrf53_spi_getreg(priv, NRF53_SPIM_TXDAMOUNT_OFFSET); + if (regval != transfer_size) { spierr("Incomplete transfer wrote %" PRId32 " expected %zu\n", - regval, nwords); + regval, transfer_size); } /* SPI stop */ diff --git a/arch/arm/src/nrf53/nrf53_tim.c b/arch/arm/src/nrf53/nrf53_tim.c index c822f2e86f203..a49dad5474f46 100644 --- a/arch/arm/src/nrf53/nrf53_tim.c +++ b/arch/arm/src/nrf53/nrf53_tim.c @@ -657,7 +657,7 @@ static int nrf53_tim_checkint(struct nrf53_tim_dev_s *dev, uint8_t s) case NRF53_TIM_INT_COMPARE1: { - ret = nrf53_tim_getreg(dev, NRF53_TIM_EVENTS_COMPARE_OFFSET(0)); + ret = nrf53_tim_getreg(dev, NRF53_TIM_EVENTS_COMPARE_OFFSET(1)); break; } diff --git a/arch/arm/src/nrf91/nrf91_modem.h b/arch/arm/src/nrf91/nrf91_modem.h index 16e0b2d43ca16..3e6a855b0bb6f 100644 --- a/arch/arm/src/nrf91/nrf91_modem.h +++ b/arch/arm/src/nrf91/nrf91_modem.h @@ -68,10 +68,6 @@ # error SHMEM base addres must be word-aligned (4 bytes) #endif -#ifdef CONFIG_ARCH_FPU -# error missing FPU configuration - FPU must be activated in SPE and NSPE -#endif - /**************************************************************************** * Public Functions Prototypes ****************************************************************************/ diff --git a/arch/arm/src/nrf91/nrf91_rtc.h b/arch/arm/src/nrf91/nrf91_rtc.h index acbbe02b523e3..c0732e0396eb5 100644 --- a/arch/arm/src/nrf91/nrf91_rtc.h +++ b/arch/arm/src/nrf91/nrf91_rtc.h @@ -27,6 +27,8 @@ #include +#include + #include /**************************************************************************** @@ -78,12 +80,12 @@ enum nrf91_rtc_cc_e enum nrf91_rtc_evt_e { - NRF91_RTC_EVT_TICK = 0, - NRF91_RTC_EVT_OVRFLW = 1, - NRF91_RTC_EVT_COMPARE0 = 2, - NRF91_RTC_EVT_COMPARE1 = 3, - NRF91_RTC_EVT_COMPARE2 = 4, - NRF91_RTC_EVT_COMPARE3 = 5, + NRF91_RTC_EVT_COMPARE0 = 0, + NRF91_RTC_EVT_COMPARE1 = 1, + NRF91_RTC_EVT_COMPARE2 = 2, + NRF91_RTC_EVT_COMPARE3 = 3, + NRF91_RTC_EVT_TICK = 4, + NRF91_RTC_EVT_OVRFLW = 5, }; /* NRF91 RTC device */ diff --git a/arch/arm/src/nrf91/nrf91_spi.c b/arch/arm/src/nrf91/nrf91_spi.c index c0361375fb194..4df333937d860 100644 --- a/arch/arm/src/nrf91/nrf91_spi.c +++ b/arch/arm/src/nrf91/nrf91_spi.c @@ -210,7 +210,7 @@ static const struct spi_ops_s g_spi1ops = # ifdef CONFIG_SPI_EXCHANGE .exchange = nrf91_spi_exchange, # else - .sndlock = nrf91_spi_sndblock, + .sndblock = nrf91_spi_sndblock, .recvblock = nrf91_spi_recvblock, # endif #ifdef CONFIG_SPI_TRIGGER @@ -348,59 +348,6 @@ static struct nrf91_spidev_s g_spi3dev = }; #endif -/* SPI4 */ - -#ifdef CONFIG_NRF91_SPI4_MASTER -static const struct spi_ops_s g_spi4ops = -{ - .lock = nrf91_spi_lock, - .select = nrf91_spi4select, - .setfrequency = nrf91_spi_setfrequency, - .setmode = nrf91_spi_setmode, - .setbits = nrf91_spi_setbits, -# ifdef CONFIG_SPI_HWFEATURES - .hwfeatures = nrf91_spi_hwfeatures, -# endif - .status = nrf91_spi4status, -# ifdef CONFIG_SPI_CMDDATA - .cmddata = nrf91_spi4cmddata, -# endif - .send = nrf91_spi_send, -# ifdef CONFIG_SPI_EXCHANGE - .exchange = nrf91_spi_exchange, -# else - .sndlock = nrf91_spi_sndblock, - .recvblock = nrf91_spi_recvblock, -# endif -#ifdef CONFIG_SPI_TRIGGER - .trigger = nrf91_spi_trigger, -#endif -#ifdef CONFIG_SPI_CALLBACK - .registercallback = nrf91_spi4register, /* Provided externally */ -#else - .registercallback = NULL, /* Not implemented */ -#endif -}; - -static struct nrf91_spidev_s g_spi4dev = -{ - .spidev = - { - .ops = &g_spi4ops, - }, - - .base = NRF91_SPIM4_BASE, - .lock = NXMUTEX_INITIALIZER, -#ifdef CONFIG_NRF91_SPI_MASTER_INTERRUPTS - .sem_isr = SEM_INITIALIZER(0), - .irq = NRF91_IRQ_SPI4, -#endif - .sck_pin = BOARD_SPI4_SCK_PIN, - .frequency = 0, - .mode = 0 -}; -#endif - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -620,23 +567,6 @@ static void nrf91_spi_gpioinit(struct nrf91_spidev_s *priv) #endif } #endif - -#ifdef CONFIG_NRF91_SPI4_MASTER - if (priv == &g_spi4dev) - { -#ifdef BOARD_SPI4_MISO_PIN - nrf91_gpio_config(BOARD_SPI4_MISO_PIN); - nrf91_spi_pselinit(priv, NRF91_SPIM_PSELMISO_OFFSET, - BOARD_SPI4_MISO_PIN); -#endif -#ifdef BOARD_SPI4_MOSI_PIN - nrf91_gpio_config(BOARD_SPI4_MOSI_PIN); - nrf91_spi_pselinit(priv, NRF91_SPIM_PSELMOSI_OFFSET, - BOARD_SPI4_MOSI_PIN); - nrf91_gpio_write(BOARD_SPI4_MOSI_PIN, false); -#endif - } -#endif } #ifdef CONFIG_PM @@ -699,18 +629,6 @@ static void nrf91_spi_gpiodeinit(struct nrf91_spidev_s *priv) #endif } #endif - -#ifdef CONFIG_NRF91_SPI4_MASTER - if (priv == &g_spi4dev) - { -#ifdef BOARD_SPI4_MISO_PIN - nrf91_gpio_unconfig(BOARD_SPI4_MISO_PIN); -#endif -#ifdef BOARD_SPI4_MOSI_PIN - nrf91_gpio_unconfig(BOARD_SPI4_MOSI_PIN); -#endif - } -#endif } #endif @@ -782,7 +700,7 @@ static uint32_t nrf91_spi_setfrequency(struct spi_dev_s *dev, /* Frequency > 8MHz available only for SPIM4 */ - if (frequency > 8000000 && priv->base != NRF91_SPIM4_BASE) + if (frequency > 8000000) { frequency = 8000000; spiwarn("Reduce freq to %" PRId32 "\n", frequency); @@ -834,18 +752,6 @@ static uint32_t nrf91_spi_setfrequency(struct spi_dev_s *dev, break; } - case 16000000: - { - regval = SPIM_FREQUENCY_16MBPS; - break; - } - - case 32000000: - { - regval = SPIM_FREQUENCY_32MBPS; - break; - } - default: { spierr("Frequency unsupported %" PRId32 "\n", frequency); @@ -1158,11 +1064,11 @@ static void nrf91_spi_exchange(struct spi_dev_s *dev, nxsem_wait_uninterruptible(&priv->sem_isr); #endif - if (nrf91_spi_getreg(priv, NRF91_SPIM_TXDAMOUNT_OFFSET) != - transfer_size) + regval = nrf91_spi_getreg(priv, NRF91_SPIM_TXDAMOUNT_OFFSET); + if (regval != transfer_size) { spierr("Incomplete transfer wrote %" PRId32 " expected %zu\n", - regval, nwords); + regval, transfer_size); } /* SPI stop */ @@ -1298,9 +1204,6 @@ static int nrf91_spi_pm_prepare(struct pm_callback_s *cb, int domain, #ifdef CONFIG_NRF91_SPI3_MASTER active |= nrf91_spi_getreg(&g_spi3dev, SPIM_EVENTS_STARTED); #endif -#ifdef CONFIG_NRF91_SPI4_MASTER - active |= nrf91_spi_getreg(&g_spi4dev, SPIM_EVENTS_STARTED); -#endif if (active) { @@ -1361,13 +1264,6 @@ static void nrf91_spi_pm_notify(struct pm_callback_s *cb, int domain, nrf91_spi_deinit(&g_spi3dev); } #endif - -#ifdef CONFIG_NRF91_SPI4_MASTER - if (g_spi4dev.initialized) - { - nrf91_spi_deinit(&g_spi4dev); - } -#endif } else { @@ -1400,13 +1296,6 @@ static void nrf91_spi_pm_notify(struct pm_callback_s *cb, int domain, nrf91_spi_init(&g_spi3dev); } #endif - -#ifdef CONFIG_NRF91_SPI4_MASTER - if (g_spi4dev.initialized) - { - nrf91_spi_init(&g_spi4dev); - } -#endif } } #endif @@ -1469,14 +1358,6 @@ struct spi_dev_s *nrf91_spibus_initialize(int port) } #endif -#ifdef CONFIG_NRF91_SPI4_MASTER - case 4: - { - priv = &g_spi4dev; - break; - } -#endif - default: { goto errout; diff --git a/arch/arm/src/nrf91/nrf91_tim.c b/arch/arm/src/nrf91/nrf91_tim.c index c6e468492564d..6890e23f3f013 100644 --- a/arch/arm/src/nrf91/nrf91_tim.c +++ b/arch/arm/src/nrf91/nrf91_tim.c @@ -657,7 +657,7 @@ static int nrf91_tim_checkint(struct nrf91_tim_dev_s *dev, uint8_t s) case NRF91_TIM_INT_COMPARE1: { - ret = nrf91_tim_getreg(dev, NRF91_TIM_EVENTS_COMPARE_OFFSET(0)); + ret = nrf91_tim_getreg(dev, NRF91_TIM_EVENTS_COMPARE_OFFSET(1)); break; } diff --git a/arch/arm/src/phy62xx/phyplus_timer_lowerhalf.c b/arch/arm/src/phy62xx/phyplus_timer_lowerhalf.c index 0cf45d3dd7fdd..b98769cff7756 100644 --- a/arch/arm/src/phy62xx/phyplus_timer_lowerhalf.c +++ b/arch/arm/src/phy62xx/phyplus_timer_lowerhalf.c @@ -397,7 +397,7 @@ static void phyplus_setcallback(struct timer_lowerhalf_s *lower, } leave_critical_section(flags); - assert(ret == OK); + ASSERT(ret == OK); /* #if 0 * irqstate_t flags = enter_critical_section(); diff --git a/arch/arm/src/qemu/Kconfig b/arch/arm/src/qemu/Kconfig index 017bfadd4972c..4eadae871b099 100644 --- a/arch/arm/src/qemu/Kconfig +++ b/arch/arm/src/qemu/Kconfig @@ -17,7 +17,6 @@ config ARCH_CHIP_QEMU_CORTEXA7 select ARCH_HAVE_ADDRENV select ARCH_HAVE_LOWVECTORS select ARCH_HAVE_MULTICPU - select ARCH_HAVE_TRUSTZONE select ARCH_NEED_ADDRENV_MAPPING select ARMV7A_HAVE_GICv2 select ARMV7A_HAVE_GTM @@ -27,4 +26,16 @@ endchoice # Qemu Chip Selection endmenu # "Qemu Virt Chip Selection" +config ARCH_CHIP_QEMU_TRUSTZONE + bool "Enable Arm Security Extensions (TrustZone)" + select ARCH_HAVE_TRUSTZONE + default n + ---help--- + Doc: https://qemu-project.gitlab.io/qemu/system/arm/virt.html + shows that set secure=on/of can emulating a guest CPU which + implements the Arm Security Extensions (TrustZone). + The default is off. And this config can enable/disable + TrustZone in qemu chip. + + endif # ARCH_CHIP_QEMU_ARM diff --git a/arch/arm/src/qemu/Make.defs b/arch/arm/src/qemu/Make.defs index 7ba6e1a0dc6ae..f51924e3b07bf 100644 --- a/arch/arm/src/qemu/Make.defs +++ b/arch/arm/src/qemu/Make.defs @@ -22,3 +22,7 @@ include armv7-a/Make.defs # qemu-specific C source files CHIP_CSRCS = qemu_boot.c qemu_serial.c qemu_irq.c qemu_timer.c qemu_memorymap.c + +ifeq ($(CONFIG_SMP),y) + CHIP_CSRCS += qemu_cpuboot.c +endif diff --git a/arch/arm/src/qemu/chip.h b/arch/arm/src/qemu/chip.h index fe581e329d6fa..ab2ccc38fa9c1 100644 --- a/arch/arm/src/qemu/chip.h +++ b/arch/arm/src/qemu/chip.h @@ -31,12 +31,17 @@ * Pre-processor Definitions ****************************************************************************/ +#define QEMU_SPI_IRQ_BASE 32 #define CHIP_MPCORE_VBASE 0x8000000 #define MPCORE_ICD_OFFSET 0x0000 #define MPCORE_ICC_OFFSET 0x10000 -#define PGTABLE_BASE_PADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - ALL_PGTABLE_SIZE) -#define PGTABLE_BASE_VADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - ALL_PGTABLE_SIZE) +#define PGTABLE_SIZE 0x00004000 +#define PGTABLE_BASE_PADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - PGTABLE_SIZE * CONFIG_SMP_NCPUS) +#define PGTABLE_BASE_VADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - PGTABLE_SIZE * CONFIG_SMP_NCPUS) + +#undef CONFIG_RAM_END +#define CONFIG_RAM_END PGTABLE_BASE_PADDR #define NUTTX_TEXT_VADDR (CONFIG_FLASH_VSTART & 0xfff00000) #define NUTTX_TEXT_PADDR (CONFIG_FLASH_VSTART & 0xfff00000) diff --git a/arch/arm/src/qemu/qemu_boot.c b/arch/arm/src/qemu/qemu_boot.c index 479bbc5883dbe..b61c243d03d53 100644 --- a/arch/arm/src/qemu/qemu_boot.c +++ b/arch/arm/src/qemu/qemu_boot.c @@ -26,6 +26,7 @@ #include "arm_internal.h" +#include "qemu_boot.h" #include "qemu_irq.h" #include "qemu_memorymap.h" @@ -47,6 +48,10 @@ void arm_boot(void) { + /* Perf init */ + + up_perf_init(0); + /* Set the page table for section */ qemu_setupmappings(); @@ -68,4 +73,12 @@ void arm_boot(void) arm_earlyserialinit(); #endif + + /* Now we can enable all other CPUs. The enabled CPUs will start execution + * at __cpuN_start and, after very low-level CPU initialization has been + * performed, will branch to arm_cpu_boot() + * (see arch/arm/src/armv7-a/smp.h) + */ + + qemu_cpu_enable(); } diff --git a/arch/arm/src/qemu/qemu_boot.h b/arch/arm/src/qemu/qemu_boot.h new file mode 100644 index 0000000000000..3e3a1dbf1a5df --- /dev/null +++ b/arch/arm/src/qemu/qemu_boot.h @@ -0,0 +1,83 @@ +/**************************************************************************** + * arch/arm/src/qemu/qemu_boot.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_QEMU_QEMU_BOOT_H +#define __ARCH_ARM_SRC_QEMU_QEMU_BOOT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: qemu_cpu_enable + * + * Description: + * Called from CPU0 to enable all other CPUs. The enabled CPUs will start + * execution at __cpuN_start and, after very low-level CPU initialization + * has been performed, will branch to arm_cpu_boot() + * (see arch/arm/src/armv7-a/smp.h) + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +void qemu_cpu_enable(void); +#else +# define qemu_cpu_enable() +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_QEMU_QEMU_BOOT_H */ diff --git a/arch/arm/src/qemu/qemu_cpuboot.c b/arch/arm/src/qemu/qemu_cpuboot.c new file mode 100644 index 0000000000000..f619d4670b1ab --- /dev/null +++ b/arch/arm/src/qemu/qemu_cpuboot.c @@ -0,0 +1,172 @@ +/**************************************************************************** + * arch/arm/src/qemu/qemu_cpuboot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "sctlr.h" +#include "smp.h" +#include "scu.h" +#include "gic.h" +#include "mmu.h" +#include "barriers.h" +#include "arm_cpu_psci.h" + +#ifdef CONFIG_SMP + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const start_t g_cpu_boot[CONFIG_SMP_NCPUS] = +{ + 0, +#if CONFIG_SMP_NCPUS > 1 + __cpu1_start, +#endif +#if CONFIG_SMP_NCPUS > 2 + __cpu2_start, +#endif +#if CONFIG_SMP_NCPUS > 3 + __cpu3_start +#endif +}; + +/* Symbols defined via the linker script */ + +extern uint8_t _vector_start[]; /* Beginning of vector block */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: qemu_cpu_enable + * + * Description: + * Called from CPU0 to enable all other CPUs. The enabled CPUs will start + * execution at __cpuN_start and, after very low-level CPU initialization + * has been performed, will branch to arm_cpu_boot() + * (see arch/arm/src/armv7-a/smp.h) + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void qemu_cpu_enable(void) +{ + int cpu; + + for (cpu = 1; cpu < CONFIG_SMP_NCPUS; cpu++) + { + /* Then enable the CPU */ + + psci_cpu_on(CORE_TO_MPID(cpu, 0), (uintptr_t)g_cpu_boot[cpu]); + } +} + +/**************************************************************************** + * Name: arm_cpu_boot + * + * Description: + * Continues the C-level initialization started by the assembly language + * __cpu[n]_start function. At a minimum, this function needs to + * initialize interrupt handling and, perhaps, wait on WFI for + * arm_cpu_start() to issue an SGI. + * + * This function must be provided by the each ARMv7-A MCU and implement + * MCU-specific initialization logic. + * + * Input Parameters: + * cpu - The CPU index. This is the same value that would be obtained by + * calling up_cpu_index(); + * + * Returned Value: + * Does not return. + * + ****************************************************************************/ + +void arm_cpu_boot(int cpu) +{ + /* Enable SMP cache coherency for the CPU */ + + arm_enable_smp(cpu); + + /* Initialize the FPU */ + + arm_fpuconfig(); + + /* Initialize the Generic Interrupt Controller (GIC) for CPUn (n != 0) */ + + arm_gic_initialize(); + +#ifdef CONFIG_ARCH_LOWVECTORS + /* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the + * beginning of the .text region must appear at address at the address + * specified in the VBAR. There are two ways to accomplish this: + * + * 1. By explicitly mapping the beginning of .text region with a page + * table entry so that the virtual address zero maps to the beginning + * of the .text region. VBAR == 0x0000:0000. + * + * 2. Set the Cortex-A5 VBAR register so that the vector table address + * is moved to a location other than 0x0000:0000. + * + * The second method is used by this logic. + */ + + /* Set the VBAR register to the address of the vector table */ + + DEBUGASSERT((((uintptr_t)_vector_start) & ~VBAR_MASK) == 0); + cp15_wrvbar((uint32_t)_vector_start); +#endif /* CONFIG_ARCH_LOWVECTORS */ + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + /* And finally, enable interrupts */ + + up_irq_enable(); +#endif + + /* The next thing that we expect to happen is for logic running on CPU0 + * to call up_cpu_start() which generate an SGI and a context switch to + * the configured NuttX IDLE task. + */ + + for (; ; ) + { + asm("WFI"); + } +} +#endif /* CONFIG_SMP */ diff --git a/arch/arm/src/qemu/qemu_irq.c b/arch/arm/src/qemu/qemu_irq.c index e69918e99e63f..d86c377e3f4e4 100644 --- a/arch/arm/src/qemu/qemu_irq.c +++ b/arch/arm/src/qemu/qemu_irq.c @@ -127,23 +127,7 @@ void up_irqinitialize(void) } /**************************************************************************** - * Name: arm_intstack_top - * - * Description: - * Return a pointer to the top the correct interrupt stack allocation - * for the current CPU. - * - ****************************************************************************/ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -uintptr_t arm_intstack_top(void) -{ - return g_irqstack_top[up_cpu_index()]; -} -#endif - -/**************************************************************************** - * Name: arm_intstack_alloc + * Name: up_get_intstackbase * * Description: * Return a pointer to the "alloc" the correct interrupt stack allocation @@ -152,8 +136,8 @@ uintptr_t arm_intstack_top(void) ****************************************************************************/ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -uintptr_t arm_intstack_alloc(void) +uintptr_t up_get_intstackbase(int cpu) { - return g_irqstack_top[up_cpu_index()] - INTSTACK_SIZE; + return g_irqstack_top[cpu] - INTSTACK_SIZE; } #endif diff --git a/arch/arm/src/qemu/qemu_memorymap.c b/arch/arm/src/qemu/qemu_memorymap.c index 603f90d293a50..2eceb2ecda304 100644 --- a/arch/arm/src/qemu/qemu_memorymap.c +++ b/arch/arm/src/qemu/qemu_memorymap.c @@ -47,6 +47,10 @@ static const struct section_mapping_s g_section_mapping[] = VIRT_IO_PSECTION, VIRT_IO_VSECTION, MMU_IOFLAGS, _NSECTIONS(VIRT_IO_SECSIZE) }, + { + VIRT_SEC_MEM_PSECTION, VIRT_SEC_MEM_VSECTION, + MMU_MEMFLAGS, _NSECTIONS(VIRT_SEC_MEM_SECSIZE) + }, { VIRT_PCIE_PSECTION, VIRT_PCIE_VSECTION, MMU_IOFLAGS, _NSECTIONS(VIRT_PCIE_SECSIZE) diff --git a/arch/arm/src/qemu/qemu_memorymap.h b/arch/arm/src/qemu/qemu_memorymap.h index 4c8660ac6707d..01fea1d37ebf8 100644 --- a/arch/arm/src/qemu/qemu_memorymap.h +++ b/arch/arm/src/qemu/qemu_memorymap.h @@ -39,19 +39,22 @@ /* Qemu virt Physical Memory Map ********************************************/ #define VIRT_FLASH_PSECTION 0x00000000 /* 0x00000000-0x08000000 */ -#define VIRT_IO_PSECTION 0x08000000 /* 0x08000000-0x0f000000 */ +#define VIRT_IO_PSECTION 0x08000000 /* 0x08000000-0x0e000000 */ +#define VIRT_SEC_MEM_PSECTION 0x0e000000 /* 0x0e000000-0x0f000000 */ #define VIRT_PCIE_PSECTION 0x10000000 /* 0x10000000-0x40000000 */ /* Qemu virt Virtual Memory Map *********************************************/ #define VIRT_FLASH_VSECTION VIRT_FLASH_PSECTION #define VIRT_IO_VSECTION VIRT_IO_PSECTION +#define VIRT_SEC_MEM_VSECTION VIRT_SEC_MEM_PSECTION #define VIRT_PCIE_VSECTION VIRT_PCIE_PSECTION /* Sizes of memory regions in bytes. */ #define VIRT_FLASH_SECSIZE (128*1024*1024) -#define VIRT_IO_SECSIZE (112*1024*1024) +#define VIRT_IO_SECSIZE (96*1024*1024) +#define VIRT_SEC_MEM_SECSIZE (16*1024*1024) #define VIRT_PCIE_SECSIZE (3*256*1024*1024) /**************************************************************************** diff --git a/arch/arm/src/rp2040/Kconfig b/arch/arm/src/rp2040/Kconfig index 751f0c806caf7..7a977a16bfa1f 100644 --- a/arch/arm/src/rp2040/Kconfig +++ b/arch/arm/src/rp2040/Kconfig @@ -3,7 +3,7 @@ # see the file kconfig-language.txt in the NuttX tools repository. # - comment "RP2040 Configuration Options" +comment "RP2040 Configuration Options" config RP2040_DMAC bool "DMAC support" @@ -377,7 +377,6 @@ config RP2040_PWM2_PHASE_CORRECT endif # RP2040_PWM2 - config RP2040_PWM3 bool "PWM3" ---help--- @@ -663,6 +662,222 @@ endif # ADC endif # RP2040_ADC +##################################################################### +# CLK_GPOUT Configuration +##################################################################### + +menuconfig RP2040_CLK_GPOUT_ENABLE + bool "Enable Clock Outputs" + default n + +if RP2040_CLK_GPOUT_ENABLE + +config RP2040_CLK_GPOUT0 + bool "CLK_GPOUT0 Clock Output (pin 21)" + default n + ---help--- + Enable CLK_GPOUT0 + +if RP2040_CLK_GPOUT0 + +choice + prompt "Source Clock" + +config RP2040_CLK_GPOUT0_SRC_REF + bool "REF (6 - 12 MHz)" + ---help--- + Reference clock that is always running unless in DORMANT mode. Runs from + Ring Oscillator (ROSC) at power-up but can be switched to Crystal + Oscillator (XOSC) for more accuracy. + +config RP2040_CLK_GPOUT0_SRC_SYS + bool "SYS (125 MHz)" + ---help--- + System clock that is always running unless in DORMANT mode. Runs from + clk_ref at power-up but is typically switched to a PLL. + +config RP2040_CLK_GPOUT0_SRC_USB + bool "USB (48 MHz)" + ---help--- + USB reference clock. Must be 48MHz. + +config RP2040_CLK_GPOUT0_SRC_ADC + bool "ADC (48 MHz)" + ---help--- + ADC reference clock. Must be 48MHz. + +config RP2040_CLK_GPOUT0_SRC_RTC + bool "RTC (46875 Hz)" + ---help--- + RTC reference clock. The RTC divides this clock to generate a 1 second reference. + +endchoice # Source Clock + +config RP2040_CLK_GPOUT0_DIVINT + int "Divisor (Integer)" + default 1 + +config RP2040_CLK_GPOUT0_DIVFRAC + int "Divisor (Fractional)" + default 0 + +endif # RP2040_CLK_GPOUT0 + +config RP2040_CLK_GPOUT1 + bool "CLK_GPOUT1 Clock Output (pin 23)" + default n + ---help--- + Enable CLK_GPOUT1 + +if RP2040_CLK_GPOUT1 + +choice + prompt "Source Clock" + +config RP2040_CLK_GPOUT1_SRC_REF + bool "REF (6 - 12 MHz)" + ---help--- + Reference clock that is always running unless in DORMANT mode. Runs from + Ring Oscillator (ROSC) at power-up but can be switched to Crystal + Oscillator (XOSC) for more accuracy. + +config RP2040_CLK_GPOUT1_SRC_SYS + bool "SYS (125 MHz)" + ---help--- + System clock that is always running unless in DORMANT mode. Runs from + clk_ref at power-up but is typically switched to a PLL. + +config RP2040_CLK_GPOUT1_SRC_USB + bool "USB (48 MHz)" + ---help--- + USB reference clock. Must be 48MHz. + +config RP2040_CLK_GPOUT1_SRC_ADC + bool "ADC (48 MHz)" + ---help--- + ADC reference clock. Must be 48MHz. + +config RP2040_CLK_GPOUT1_SRC_RTC + bool "RTC (46875 Hz)" + ---help--- + RTC reference clock. The RTC divides this clock to generate a 1 second reference. + +endchoice # Source Clock + +config RP2040_CLK_GPOUT1_DIVINT + int "Divisor (Integer)" + default 1 + +config RP2040_CLK_GPOUT1_DIVFRAC + int "Divisor (Fractional)" + default 0 + +endif # RP2040_CLK_GPOUT1 + +config RP2040_CLK_GPOUT2 + bool "CLK_GPOUT2 Clock Output (pin 24)" + default n + ---help--- + Enable CLK_GPOUT2 + +if RP2040_CLK_GPOUT2 + +choice + prompt "Source Clock" + +config RP2040_CLK_GPOUT2_SRC_REF + bool "REF (6 - 12 MHz)" + ---help--- + Reference clock that is always running unless in DORMANT mode. Runs from + Ring Oscillator (ROSC) at power-up but can be switched to Crystal + Oscillator (XOSC) for more accuracy. + +config RP2040_CLK_GPOUT2_SRC_SYS + bool "SYS (125 MHz)" + ---help--- + System clock that is always running unless in DORMANT mode. Runs from + clk_ref at power-up but is typically switched to a PLL. + +config RP2040_CLK_GPOUT2_SRC_USB + bool "USB (48 MHz)" + ---help--- + USB reference clock. Must be 48MHz. + +config RP2040_CLK_GPOUT2_SRC_ADC + bool "ADC (48 MHz)" + ---help--- + ADC reference clock. Must be 48MHz. + +config RP2040_CLK_GPOUT2_SRC_RTC + bool "RTC (46875 Hz)" + ---help--- + RTC reference clock. The RTC divides this clock to generate a 1 second reference. + +endchoice # Source Clock + +config RP2040_CLK_GPOUT2_DIVINT + int "Divisor (Integer)" + default 1 + +config RP2040_CLK_GPOUT2_DIVFRAC + int "Divisor (Fractional)" + default 0 + +endif # RP2040_CLK_GPOUT2 + +config RP2040_CLK_GPOUT3 + bool "CLK_GPOUT3 Clock Output (pin 25)" + default n + ---help--- + Enable CLK_GPOUT3 + +if RP2040_CLK_GPOUT3 + +choice + prompt "Source Clock" + +config RP2040_CLK_GPOUT3_SRC_REF + bool "REF (6 - 12 MHz)" + ---help--- + Reference clock that is always running unless in DORMANT mode. Runs from + Ring Oscillator (ROSC) at power-up but can be switched to Crystal + Oscillator (XOSC) for more accuracy. + +config RP2040_CLK_GPOUT3_SRC_SYS + bool "SYS (125 MHz)" + ---help--- + System clock that is always running unless in DORMANT mode. Runs from + clk_ref at power-up but is typically switched to a PLL. + +config RP2040_CLK_GPOUT3_SRC_USB + bool "USB (48 MHz)" + ---help--- + USB reference clock. Must be 48MHz. + +config RP2040_CLK_GPOUT3_SRC_ADC + bool "ADC (48 MHz)" + ---help--- + ADC reference clock. Must be 48MHz. + +config RP2040_CLK_GPOUT3_SRC_RTC + bool "RTC (46875 Hz)" + ---help--- + RTC reference clock. The RTC divides this clock to generate a 1 second reference. + +endchoice # Source Clock + +config RP2040_CLK_GPOUT3_DIVINT + int "Divisor (Integer)" + default 1 + +config RP2040_CLK_GPOUT3_DIVFRAC + int "Divisor (Fractional)" + default 0 + +endif # RP2040_CLK_GPOUT3 + +endif # RP2040_CLK_GPOUT_ENABLE + ##################################################################### # WS2812 Configuration ##################################################################### diff --git a/arch/arm/src/rp2040/rp2040_clock.c b/arch/arm/src/rp2040/rp2040_clock.c index e874ac543e4eb..6f759a829f9c8 100644 --- a/arch/arm/src/rp2040/rp2040_clock.c +++ b/arch/arm/src/rp2040/rp2040_clock.c @@ -81,13 +81,37 @@ static inline bool has_glitchless_mux(int clk_index) clk_index == RP2040_CLOCKS_NDX_REF; } +#if defined(CONFIG_RP2040_CLK_GPOUT_ENABLE) +static bool rp2040_clock_configure_gpout(int clk_index, + uint32_t src, + uint32_t div_int, + uint32_t div_frac) +{ + if (clk_index > RP2040_CLOCKS_NDX_GPOUT3 || + clk_index < RP2040_CLOCKS_NDX_GPOUT0 || + (src >> RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT) > 0xa) + { + return false; + } + + putreg32((div_int << RP2040_CLOCKS_CLK_GPOUT0_DIV_INT_SHIFT) | + (div_frac & RP2040_CLOCKS_CLK_GPOUT0_DIV_FRAC_MASK), + (RP2040_CLOCKS_CLK_NDX_DIV(clk_index))); + putreg32((src << RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_SHIFT) | + RP2040_CLOCKS_CLK_GPOUT0_CTRL_ENABLE, + (RP2040_CLOCKS_CLK_NDX_CTRL(clk_index))); + + return true; +} +#endif + bool rp2040_clock_configure(int clk_index, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t freq) { uint32_t div; - assert(src_freq >= freq); + ASSERT(src_freq >= freq); if (freq > src_freq) { @@ -274,6 +298,91 @@ void clocks_init(void) RP2040_CLOCKS_CLK_PERI_CTRL_AUXSRC_CLK_SYS, BOARD_SYS_FREQ, BOARD_PERI_FREQ); + +#if defined(CONFIG_RP2040_CLK_GPOUT_ENABLE) + uint32_t src; + + #if defined(CONFIG_RP2040_CLK_GPOUT0) + #if defined(CONFIG_RP2040_CLK_GPOUT0_SRC_REF) + src = RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_REF; + #elif defined(CONFIG_RP2040_CLK_GPOUT0_SRC_SYS) + src = RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_SYS; + #elif defined(CONFIG_RP2040_CLK_GPOUT0_SRC_USB) + src = RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_USB; + #elif defined(CONFIG_RP2040_CLK_GPOUT0_SRC_ADC) + src = RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_ADC; + #elif defined(CONFIG_RP2040_CLK_GPOUT0_SRC_RTC) + src = RP2040_CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_CLK_RTC; + #else + src = 0; + #endif + rp2040_clock_configure_gpout(RP2040_CLOCKS_NDX_GPOUT0, + src, + CONFIG_RP2040_CLK_GPOUT0_DIVINT, + CONFIG_RP2040_CLK_GPOUT0_DIVFRAC); + #endif + + #if defined(CONFIG_RP2040_CLK_GPOUT1) + #if defined(CONFIG_RP2040_CLK_GPOUT1_SRC_REF) + src = RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_REF; + #elif defined(CONFIG_RP2040_CLK_GPOUT1_SRC_SYS) + src = RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_SYS; + #elif defined(CONFIG_RP2040_CLK_GPOUT1_SRC_USB) + src = RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_USB; + #elif defined(CONFIG_RP2040_CLK_GPOUT1_SRC_ADC) + src = RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_ADC; + #elif defined(CONFIG_RP2040_CLK_GPOUT1_SRC_RTC) + src = RP2040_CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_CLK_RTC; + #else + src = 0; + #endif + rp2040_clock_configure_gpout(RP2040_CLOCKS_NDX_GPOUT1, + src, + CONFIG_RP2040_CLK_GPOUT1_DIVINT, + CONFIG_RP2040_CLK_GPOUT1_DIVFRAC); + #endif + + #if defined(CONFIG_RP2040_CLK_GPOUT2) + #if defined(CONFIG_RP2040_CLK_GPOUT2_SRC_REF) + src = RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_REF; + #elif defined(CONFIG_RP2040_CLK_GPOUT2_SRC_SYS) + src = RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_SYS; + #elif defined(CONFIG_RP2040_CLK_GPOUT2_SRC_USB) + src = RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_USB; + #elif defined(CONFIG_RP2040_CLK_GPOUT2_SRC_ADC) + src = RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_ADC; + #elif defined(CONFIG_RP2040_CLK_GPOUT2_SRC_RTC) + src = RP2040_CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_CLK_RTC; + #else + src = 0; + #endif + rp2040_clock_configure_gpout(RP2040_CLOCKS_NDX_GPOUT2, + src, + CONFIG_RP2040_CLK_GPOUT2_DIVINT, + CONFIG_RP2040_CLK_GPOUT2_DIVFRAC); + #endif + + #if defined(CONFIG_RP2040_CLK_GPOUT3) + #if defined(CONFIG_RP2040_CLK_GPOUT3_SRC_REF) + src = RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_REF; + #elif defined(CONFIG_RP2040_CLK_GPOUT3_SRC_SYS) + src = RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_SYS; + #elif defined(CONFIG_RP2040_CLK_GPOUT3_SRC_USB) + src = RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_USB; + #elif defined(CONFIG_RP2040_CLK_GPOUT3_SRC_ADC) + src = RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_ADC; + #elif defined(CONFIG_RP2040_CLK_GPOUT3_SRC_RTC) + src = RP2040_CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_CLK_RTC; + #else + src = 0; + #endif + rp2040_clock_configure_gpout(RP2040_CLOCKS_NDX_GPOUT3, + src, + CONFIG_RP2040_CLK_GPOUT3_DIVINT, + CONFIG_RP2040_CLK_GPOUT3_DIVFRAC); + #endif + +#endif } /**************************************************************************** diff --git a/arch/arm/src/rp2040/rp2040_cpupause.c b/arch/arm/src/rp2040/rp2040_cpupause.c index 2d74d7751190c..44e100ef41976 100644 --- a/arch/arm/src/rp2040/rp2040_cpupause.c +++ b/arch/arm/src/rp2040/rp2040_cpupause.c @@ -135,7 +135,7 @@ bool up_cpu_pausereq(int cpu) } /**************************************************************************** - * Name: up_cpu_paused + * Name: up_cpu_paused_save * * Description: * Handle a pause request from another CPU. Normally, this logic is @@ -144,16 +144,8 @@ bool up_cpu_pausereq(int cpu) * pause operation in other contexts where the interrupt cannot be taken * in order to avoid deadlocks. * - * This function performs the following operations: - * - * 1. It saves the current task state at the head of the current assigned - * task list. - * 2. It waits on a spinlock, then - * 3. Returns from interrupt, restoring the state of the new task at the - * head of the ready to run list. - * * Input Parameters: - * cpu - The index of the CPU to be paused + * None * * Returned Value: * On success, OK is returned. Otherwise, a negated errno value indicating @@ -161,7 +153,7 @@ bool up_cpu_pausereq(int cpu) * ****************************************************************************/ -int up_cpu_paused(int cpu) +int up_cpu_paused_save(void) { struct tcb_s *tcb = this_task(); @@ -181,6 +173,38 @@ int up_cpu_paused(int cpu) arm_savestate(tcb->xcp.regs); + return OK; +} + +/**************************************************************************** + * Name: up_cpu_paused + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. + * + * This function performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. + * + * Input Parameters: + * cpu - The index of the CPU to be paused + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused(int cpu) +{ /* Wait for the spinlock to be released */ spin_unlock(&g_cpu_paused[cpu]); @@ -191,11 +215,31 @@ int up_cpu_paused(int cpu) spin_lock(&g_cpu_wait[cpu]); - /* Restore the exception context of the tcb at the (new) head of the - * assigned task list. - */ + spin_unlock(&g_cpu_wait[cpu]); + spin_unlock(&g_cpu_resumed[cpu]); - tcb = this_task(); + return OK; +} + +/**************************************************************************** + * Name: up_cpu_paused_restore + * + * Description: + * Restore the state of the CPU after it was paused via up_cpu_pause(), + * and resume normal tasking. + * + * Input Parameters: + * None + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused_restore(void) +{ + struct tcb_s *tcb = this_task(); #ifdef CONFIG_SCHED_INSTRUMENTATION /* Notify that we have resumed */ @@ -212,8 +256,6 @@ int up_cpu_paused(int cpu) */ arm_restorestate(tcb->xcp.regs); - spin_unlock(&g_cpu_wait[cpu]); - spin_unlock(&g_cpu_resumed[cpu]); return OK; } @@ -357,7 +399,7 @@ int up_cpu_pause(int cpu) * called. g_cpu_paused will be unlocked in any case. */ - return 0; + return OK; } /**************************************************************************** @@ -406,7 +448,7 @@ int up_cpu_resume(int cpu) spin_lock(&g_cpu_resumed[cpu]); spin_unlock(&g_cpu_resumed[cpu]); - return 0; + return OK; } /**************************************************************************** diff --git a/arch/arm/src/rp2040/rp2040_gpio.h b/arch/arm/src/rp2040/rp2040_gpio.h index 7d6aa14898cf0..f68eea025276e 100644 --- a/arch/arm/src/rp2040/rp2040_gpio.h +++ b/arch/arm/src/rp2040/rp2040_gpio.h @@ -55,12 +55,19 @@ #define RP2040_GPIO_FUNC_USB RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_USB #define RP2040_GPIO_FUNC_NULL RP2040_IO_BANK0_GPIO_CTRL_FUNCSEL_NULL +/* GPIO function pins *******************************************************/ + +#define RP2040_GPIO_PIN_CLK_GPOUT0 (21) +#define RP2040_GPIO_PIN_CLK_GPOUT1 (23) +#define RP2040_GPIO_PIN_CLK_GPOUT2 (24) +#define RP2040_GPIO_PIN_CLK_GPOUT3 (25) + /* GPIO interrupt modes *****************************************************/ -#define RP2040_GPIO_INTR_LEVEL_LOW 0 -#define RP2040_GPIO_INTR_LEVEL_HIGH 1 -#define RP2040_GPIO_INTR_EDGE_LOW 2 -#define RP2040_GPIO_INTR_EDGE_HIGH 3 +#define RP2040_GPIO_INTR_LEVEL_LOW 0 +#define RP2040_GPIO_INTR_LEVEL_HIGH 1 +#define RP2040_GPIO_INTR_EDGE_LOW 2 +#define RP2040_GPIO_INTR_EDGE_HIGH 3 /**************************************************************************** * Public Types diff --git a/arch/arm/src/rp2040/rp2040_irq.c b/arch/arm/src/rp2040/rp2040_irq.c index b6d8c40f0e464..cb76498c3d5d1 100644 --- a/arch/arm/src/rp2040/rp2040_irq.c +++ b/arch/arm/src/rp2040/rp2040_irq.c @@ -438,23 +438,7 @@ int up_prioritize_irq(int irq, int priority) #endif /**************************************************************************** - * Name: arm_intstack_top - * - * Description: - * Return a pointer to the top the correct interrupt stack allocation - * for the current CPU. - * - ****************************************************************************/ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -uintptr_t arm_intstack_top(void) -{ - return g_cpu_intstack_top[up_cpu_index()]; -} -#endif - -/**************************************************************************** - * Name: arm_intstack_alloc + * Name: up_get_intstackbase * * Description: * Return a pointer to the "alloc" the correct interrupt stack allocation @@ -463,8 +447,8 @@ uintptr_t arm_intstack_top(void) ****************************************************************************/ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 -uintptr_t arm_intstack_alloc(void) +uintptr_t up_get_intstackbase(int cpu) { - return g_cpu_intstack_top[up_cpu_index()] - INTSTACK_SIZE; + return g_cpu_intstack_top[cpu] - INTSTACK_SIZE; } #endif diff --git a/arch/arm/src/rp2040/rp2040_pio.c b/arch/arm/src/rp2040/rp2040_pio.c index fc1f01f5b9910..83e5c33e957a4 100644 --- a/arch/arm/src/rp2040/rp2040_pio.c +++ b/arch/arm/src/rp2040/rp2040_pio.c @@ -127,7 +127,7 @@ static int hw_claim_unused_from_range(uint8_t *bits, bool required, static void hw_claim_clear(uint8_t *bits, uint32_t bit_index) { uint32_t save = hw_claim_lock(); - assert(bits[bit_index >> 3u] & (1u << (bit_index & 7u))); + ASSERT(bits[bit_index >> 3u] & (1u << (bit_index & 7u))); bits[bit_index >> 3u] &= (uint8_t) ~(1u << (bit_index & 7u)); hw_claim_unlock(save); } @@ -135,7 +135,7 @@ static void hw_claim_clear(uint8_t *bits, uint32_t bit_index) static int _pio_find_offset_for_program(uint32_t pio, const rp2040_pio_program_t *program) { - assert(program->length < PIO_INSTRUCTION_COUNT); + ASSERT(program->length < PIO_INSTRUCTION_COUNT); uint32_t used_mask = _used_instruction_space[rp2040_pio_get_index(pio)]; uint32_t program_mask = (1u << program->length) - 1; @@ -306,7 +306,7 @@ void rp2040_pio_remove_program(uint32_t pio, uint32_t program_mask = (1u << program->length) - 1; program_mask <<= loaded_offset; uint32_t save = hw_claim_lock(); - assert(program_mask == + ASSERT(program_mask == (_used_instruction_space[rp2040_pio_get_index(pio)] & program_mask)); _used_instruction_space[rp2040_pio_get_index(pio)] &= ~program_mask; diff --git a/arch/arm/src/rp2040/rp2040_pio_instructions.h b/arch/arm/src/rp2040/rp2040_pio_instructions.h index 35cf1640699fd..cfe6bbd33ca3e 100644 --- a/arch/arm/src/rp2040/rp2040_pio_instructions.h +++ b/arch/arm/src/rp2040/rp2040_pio_instructions.h @@ -143,11 +143,11 @@ inline static uint32_t _pio_encode_instr_and_args( uint32_t major = _pio_major_instr_bits(instr_bits); if (major == pio_instr_bits_in || major == pio_instr_bits_out) { - assert(arg2 && arg2 <= 32); + ASSERT(arg2 && arg2 <= 32); } else { - assert(arg2 <= 31); + ASSERT(arg2 <= 31); } #endif return instr_bits | (arg1 << 5u) | (arg2 & 0x1fu); diff --git a/arch/arm/src/rp2040/rp2040_pll.c b/arch/arm/src/rp2040/rp2040_pll.c index fc5e4f78d9c50..01b1d0fe2129f 100644 --- a/arch/arm/src/rp2040/rp2040_pll.c +++ b/arch/arm/src/rp2040/rp2040_pll.c @@ -91,11 +91,11 @@ void rp2040_pll_init(uint32_t base, uint32_t refdiv, uint32_t vco_freq, /* Check parameter ranges */ - assert(fbdiv >= 16 && fbdiv <= 320); - assert((post_div1 >= 1 && post_div1 <= 7) && + ASSERT(fbdiv >= 16 && fbdiv <= 320); + ASSERT((post_div1 >= 1 && post_div1 <= 7) && (post_div2 >= 1 && post_div2 <= 7)); - assert(post_div2 <= post_div1); - assert(ref_mhz <= (vco_freq / 16)); + ASSERT(post_div2 <= post_div1); + ASSERT(ref_mhz <= (vco_freq / 16)); /* Put calculated value into feedback divider */ diff --git a/arch/arm/src/rp2040/rp2040_xosc.c b/arch/arm/src/rp2040/rp2040_xosc.c index 978a3b5ab4ac5..a2492a2dfea5d 100644 --- a/arch/arm/src/rp2040/rp2040_xosc.c +++ b/arch/arm/src/rp2040/rp2040_xosc.c @@ -75,7 +75,7 @@ void rp2040_xosc_init(void) { /* Assumes 1-15 MHz input */ - assert(BOARD_XOSC_FREQ <= (15 * MHZ)); + ASSERT(BOARD_XOSC_FREQ <= (15 * MHZ)); putreg32(RP2040_XOSC_CTRL_FREQ_RANGE_1_15MHZ, RP2040_XOSC_CTRL); /* Set xosc startup delay */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_progmem.c b/arch/arm/src/s32k1xx/s32k1xx_progmem.c index c1ac94f090802..70d8c007cd341 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_progmem.c +++ b/arch/arm/src/s32k1xx/s32k1xx_progmem.c @@ -77,6 +77,13 @@ static uint32_t execute_ftfc_command(void) uint8_t regval; uint32_t retval; + /* AN12003: only one FlexNVM operation can be executed at a time. + * Disable ISR during this time so an ISR doesn't cause a hardfault + * from a simultaneous read. + */ + + irqstate_t flags = enter_critical_section(); + /* Clear CCIF to launch command */ regval = getreg8(S32K1XX_FTFC_FSTAT); @@ -87,6 +94,8 @@ static uint32_t execute_ftfc_command(void) retval = getreg8(S32K1XX_FTFC_FSTAT); + leave_critical_section(flags); + if (retval & (FTTC_FSTAT_MGSTAT0 | FTTC_FSTAT_FPVIOL | FTTC_FSTAT_ACCERR | FTTC_FSTAT_RDCOLERR)) { diff --git a/arch/arm/src/s32k3xx/s32k3xx_pin.c b/arch/arm/src/s32k3xx/s32k3xx_pin.c index db38c17c3d0e6..e231c165cda98 100644 --- a/arch/arm/src/s32k3xx/s32k3xx_pin.c +++ b/arch/arm/src/s32k3xx/s32k3xx_pin.c @@ -70,7 +70,7 @@ int s32k3xx_pinconfig(uint32_t cfgset) DEBUGASSERT(port < S32K3XX_NPORTS); DEBUGASSERT(pin < S32K3XX_NPINS); - if ((port >= S32K3XX_NPORTS) && (pin >= S32K3XX_NPINS)) + if ((port >= S32K3XX_NPORTS) || (pin >= S32K3XX_NPINS)) { return -EINVAL; /* Invalid port or pin number */ } diff --git a/arch/arm/src/sam34/sam4cm_cpupause.c b/arch/arm/src/sam34/sam4cm_cpupause.c index f81902bd9b803..dc80b3cc9d11b 100644 --- a/arch/arm/src/sam34/sam4cm_cpupause.c +++ b/arch/arm/src/sam34/sam4cm_cpupause.c @@ -97,7 +97,7 @@ bool up_cpu_pausereq(int cpu) } /**************************************************************************** - * Name: up_cpu_paused + * Name: up_cpu_paused_save * * Description: * Handle a pause request from another CPU. Normally, this logic is @@ -106,16 +106,8 @@ bool up_cpu_pausereq(int cpu) * pause operation in other contexts where the interrupt cannot be taken * in order to avoid deadlocks. * - * This function performs the following operations: - * - * 1. It saves the current task state at the head of the current assigned - * task list. - * 2. It waits on a spinlock, then - * 3. Returns from interrupt, restoring the state of the new task at the - * head of the ready to run list. - * * Input Parameters: - * cpu - The index of the CPU to be paused + * None * * Returned Value: * On success, OK is returned. Otherwise, a negated errno value indicating @@ -123,7 +115,7 @@ bool up_cpu_pausereq(int cpu) * ****************************************************************************/ -int up_cpu_paused(int cpu) +int up_cpu_paused_save(void) { struct tcb_s *tcb = this_task(); @@ -143,6 +135,38 @@ int up_cpu_paused(int cpu) arm_savestate(tcb->xcp.regs); + return OK; +} + +/**************************************************************************** + * Name: up_cpu_paused + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. + * + * This function performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. + * + * Input Parameters: + * cpu - The index of the CPU to be paused + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused(int cpu) +{ /* Wait for the spinlock to be released */ spin_unlock(&g_cpu_paused[cpu]); @@ -153,11 +177,31 @@ int up_cpu_paused(int cpu) spin_lock(&g_cpu_wait[cpu]); - /* Restore the exception context of the tcb at the (new) head of the - * assigned task list. - */ + spin_unlock(&g_cpu_wait[cpu]); + spin_unlock(&g_cpu_resumed[cpu]); + + return OK; +} - tcb = this_task(); +/**************************************************************************** + * Name: up_cpu_paused_restore + * + * Description: + * Restore the state of the CPU after it was paused via up_cpu_pause(), + * and resume normal tasking. + * + * Input Parameters: + * None + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused_restore(void) +{ + struct tcb_s *tcb = this_task(); #ifdef CONFIG_SCHED_INSTRUMENTATION /* Notify that we have resumed */ @@ -174,8 +218,6 @@ int up_cpu_paused(int cpu) */ arm_restorestate(tcb->xcp.regs); - spin_unlock(&g_cpu_wait[cpu]); - spin_unlock(&g_cpu_resumed[cpu]); return OK; } diff --git a/arch/arm/src/sam34/sam_lowputc.c b/arch/arm/src/sam34/sam_lowputc.c index 3ec9fc51e2f0a..0c2f1078ccd72 100644 --- a/arch/arm/src/sam34/sam_lowputc.c +++ b/arch/arm/src/sam34/sam_lowputc.c @@ -27,6 +27,7 @@ #include #include +#include #include "arm_internal.h" #include "sam_gpio.h" @@ -277,18 +278,18 @@ void arm_lowputc(char ch) * atomic. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) & UART_INT_TXEMPTY) != 0) { /* Send the character */ putreg32((uint32_t)ch, SAM_CONSOLE_BASE + SAM_UART_THR_OFFSET); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); return; } - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } #endif } diff --git a/arch/arm/src/sama5/Kconfig b/arch/arm/src/sama5/Kconfig index 078d031ef6f04..5e03b6e6c44f5 100644 --- a/arch/arm/src/sama5/Kconfig +++ b/arch/arm/src/sama5/Kconfig @@ -491,7 +491,6 @@ config SAMA5_SAIC bool "Secure Advanced Interrupt Controller (SAIC)" default n depends on SAMA5_HAVE_SAIC - select ARMV7A_DECODEFIQ config SAMA5_RXLP bool "Low power asynchronous receiver" @@ -1109,16 +1108,16 @@ choice default SAMA5D2_CLASSD_PWM_TRAILING ---help--- TRAILING EDGE: The signal is single-ended. - If bit NON_OVERLAP is cleared, the signal is sent to + If bit NON_OVERLAP is cleared, the signal is sent to CLASSD_L0 and CLASSD_R0. If bit NON_OVERLAP is set, the signal is sent to CLASSD_L0/L1 and CLASSD_R0/R1. UNIFORM: The signal is differential. - If bit NON_OVERLAP is cleared, the signal is sent to + If bit NON_OVERLAP is cleared, the signal is sent to CLASSD_L0/L2 and CLASSD_R0/R2. - If bit NON_OVERLAP is set, the signal is sent to + If bit NON_OVERLAP is set, the signal is sent to CLASSD_L0/L1/L2/L3 and CLASSD_R0/R1/R2/R3. config SAMA5D2_CLASSD_PWM_TRAILING @@ -1246,8 +1245,8 @@ config SAMA5D2_CLASSD_MONO default 0 ---help--- Disabled. The signal is sent stereo to the left and right channels. - Enabled. The same signal is sent on both left and right channels. - The sent signal is defined by the MONOMODE field value. + Enabled. The same signal is sent on both left and right channels. + The sent signal is defined by the MONOMODE field value. choice prompt "Mono Mode Selection (MONOMODE)" @@ -5535,9 +5534,9 @@ endchoice # CS0 Memory Type # depends on SAMA5_EBICS0_NAND # # config SAMA5_EBICS0_ECCNONE -# bool "No ECC" -# ---help--- -# Only raw transfers to/from NAND are supported +# bool "No ECC" +# ---help--- +# Only raw transfers to/from NAND are supported # # config SAMA5_EBICS0_SWECC # bool "Software ECC" diff --git a/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h b/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h index e5b870e5a6659..ee1470b0c1273 100644 --- a/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h +++ b/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h @@ -28,6 +28,15 @@ #include #include +/* SAMA5 Virtual (mapped) Memory Map + * + * board_memorymap.h contains special mappings that are needed when a ROM + * memory map is used. It is included in this odd location because it + * depends on some the virtual address definitions provided above. + */ + +#include + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -373,15 +382,6 @@ #define SAM_PERIPHB_MMUFLAGS MMU_IOFLAGS #define SAM_PERIPHC_MMUFLAGS MMU_IOFLAGS -/* SAMA5 Virtual (mapped) Memory Map - * - * board_memorymap.h contains special mappings that are needed when a ROM - * memory map is used. It is included in this odd location because it - * depends on some the virtual address definitions provided above. - */ - -#include - /* SAMA5 Virtual (mapped) Memory Map. These are the mappings that will * be created if the page table lies in RAM. If the platform has another, * read-only, pre-initialized page table (perhaps in ROM), then the @@ -664,12 +664,12 @@ # error "CONFIG_ARCH_ROMPGTABLE defined; PGTABLE_BASE_P/VADDR not defined" # endif -/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory - * map probably do not apply because paging logic will probably partition - * the SRAM section differently. In particular, if the page table is located - * at the end of SRAM, then the virtual page table address defined below - * will probably be in error. In that case PGTABLE_BASE_VADDR is defined - * in the file mmu.h +/* If CONFIG_LEGACY_PAGING is selected, then parts of the 1-to-1 virtual + * memory map probably do not apply because paging logic will probably + * partition the SRAM section differently. In particular, if the page + * table is located at the end of SRAM, then the virtual page table address + * defined below will probably be in error. In that case PGTABLE_BASE_VADDR + * is defined in the file mmu.h * * We must declare the page table at the bottom or at the top of internal * SRAM. We pick the bottom of internal SRAM *unless* there are vectors @@ -681,18 +681,18 @@ /* In this case, page table must lie at the top 16Kb of ISRAM1 (or ISRAM0 * if ISRAM1 is not available in this architecture) * - * If CONFIG_PAGING is defined, then mmu.h assign the virtual address - * of the page table. + * If CONFIG_LEGACY_PAGING is defined, then mmu.h assign the virtual + * address of the page table. */ # if SAM_ISRAM1_SIZE > 0 # define PGTABLE_BASE_PADDR (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE) -# ifndef CONFIG_PAGING +# ifndef CONFIG_LEGACY_PAGING # define PGTABLE_BASE_VADDR (SAM_ISRAM1_VADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE) # endif # else # define PGTABLE_BASE_PADDR (SAM_ISRAM0_PADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE) -# ifndef CONFIG_PAGING +# ifndef CONFIG_LEGACY_PAGING # define PGTABLE_BASE_VADDR (SAM_ISRAM0_VADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE) # endif # endif @@ -721,7 +721,7 @@ */ # define PGTABLE_BASE_PADDR SAM_ISRAM0_PADDR -# ifndef CONFIG_PAGING +# ifndef CONFIG_LEGACY_PAGING # define PGTABLE_BASE_VADDR SAM_ISRAM0_VADDR # endif # define PGTABLE_IN_LOWSRAM 1 @@ -803,9 +803,9 @@ * memory to address 0x0000:0000 using both the MMU and the AXI matrix * REMAP register. So no L2 page table is required. * - * 2) If on-demand paging is supported (CONFIG_PAGING=y), than an additional - * L2 page table is needed. This page table will use the remainder of - * the address space. + * 2) If on-demand paging is supported (CONFIG_LEGACY_PAGING=y), than an + * additional L2 page table is needed. This page table will use the + * remainder of the address space. */ #ifndef CONFIG_ARCH_LOWVECTORS @@ -838,7 +838,7 @@ /* Paging L2 page table base addresses * - * NOTE: If CONFIG_PAGING is defined, mmu.h will re-assign the virtual + * NOTE: If CONFIG_LEGACY_PAGING is defined, mmu.h will re-assign the virtual * address of the page table. */ diff --git a/arch/arm/src/sama5/hardware/_sama5d3x_memorymap.h b/arch/arm/src/sama5/hardware/_sama5d3x_memorymap.h index 796e21d564c3a..d11ae4edfe790 100644 --- a/arch/arm/src/sama5/hardware/_sama5d3x_memorymap.h +++ b/arch/arm/src/sama5/hardware/_sama5d3x_memorymap.h @@ -28,6 +28,15 @@ #include #include +/* SAMA5 Virtual (mapped) Memory Map + * + * board_memorymap.h contains special mappings that are needed when a ROM + * memory map is used. It is included in this odd location because it + * depends on some the virtual address definitions provided above. + */ + +#include + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -311,15 +320,6 @@ #define SAM_PERIPHB_MMUFLAGS MMU_IOFLAGS #define SAM_SYSC_MMUFLAGS MMU_IOFLAGS -/* SAMA5 Virtual (mapped) Memory Map - * - * board_memorymap.h contains special mappings that are needed when a ROM - * memory map is used. It is included in this odd location because it - * depends on some the virtual address definitions provided above. - */ - -#include - /* SAMA5 Virtual (mapped) Memory Map. These are the mappings that will * be created if the page table lies in RAM. If the platform has another, * read-only, pre-initialized page table (perhaps in ROM), then the board.h @@ -572,12 +572,12 @@ # error "CONFIG_ARCH_ROMPGTABLE defined; PGTABLE_BASE_P/VADDR not defined" # endif -/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory - * map probably do not apply because paging logic will probably partition - * the SRAM section differently. In particular, if the page table is located - * at the end of SRAM, then the virtual page table address defined below - * will probably be in error. In that case PGTABLE_BASE_VADDR is defined - * in the file mmu.h +/* If CONFIG_LEGACY_PAGING is selected, then parts of the 1-to-1 virtual + * memory map probably do not apply because paging logic will probably + * partition the SRAM section differently. In particular, if the page + * table is located at the end of SRAM, then the virtual page table address + * defined below will probably be in error. In that case PGTABLE_BASE_VADDR + * is defined in the file mmu.h * * We must declare the page table at the bottom or at the top of internal * SRAM. We pick the bottom of internal SRAM *unless* there are vectors @@ -589,18 +589,18 @@ /* In this case, page table must lie at the top 16Kb of ISRAM1 (or ISRAM0 * if ISRAM1 is not available in this architecture) * - * If CONFIG_PAGING is defined, then mmu.h assign the virtual address + * If CONFIG_LEGACY_PAGING is defined, then mmu.h assign the virtual address * of the page table. */ # if SAM_ISRAM1_SIZE > 0 # define PGTABLE_BASE_PADDR (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE) -# ifndef CONFIG_PAGING +# ifndef CONFIG_LEGACY_PAGING # define PGTABLE_BASE_VADDR (SAM_ISRAM1_VADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE) # endif # else # define PGTABLE_BASE_PADDR (SAM_ISRAM0_PADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE) -# ifndef CONFIG_PAGING +# ifndef CONFIG_LEGACY_PAGING # define PGTABLE_BASE_VADDR (SAM_ISRAM0_VADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE) # endif # endif @@ -629,7 +629,7 @@ */ # define PGTABLE_BASE_PADDR SAM_ISRAM0_PADDR -# ifndef CONFIG_PAGING +# ifndef CONFIG_LEGACY_PAGING # define PGTABLE_BASE_VADDR SAM_ISRAM0_VADDR # endif # define PGTABLE_IN_LOWSRAM 1 @@ -711,7 +711,7 @@ * boot memory to address 0x0000:0000 using both the MMU and the AXI * matrix REMAP register. So no L2 page table is required. * - * 2) If on-demand paging is supported (CONFIG_PAGING=y), than an + * 2) If on-demand paging is supported (CONFIG_LEGACY_PAGING=y), than an * additional L2 page table is needed. * This page table will use the remainder of the address space. */ @@ -746,7 +746,7 @@ /* Paging L2 page table base addresses * - * NOTE: If CONFIG_PAGING is defined, mmu.h will re-assign the virtual + * NOTE: If CONFIG_LEGACY_PAGING is defined, mmu.h will re-assign the virtual * address of the page table. */ diff --git a/arch/arm/src/sama5/hardware/_sama5d4x_memorymap.h b/arch/arm/src/sama5/hardware/_sama5d4x_memorymap.h index 7945a42ed7d16..80682c7a647d2 100644 --- a/arch/arm/src/sama5/hardware/_sama5d4x_memorymap.h +++ b/arch/arm/src/sama5/hardware/_sama5d4x_memorymap.h @@ -28,6 +28,15 @@ #include #include +/* SAMA5 Virtual (mapped) Memory Map + * + * board_memorymap.h contains special mappings that are needed when a ROM + * memory map is used. It is included in this odd location because it + * depends on some the virtual address definitions provided above. + */ + +#include + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -311,15 +320,6 @@ #define SAM_PERIPHB_MMUFLAGS MMU_IOFLAGS #define SAM_PERIPHC_MMUFLAGS MMU_IOFLAGS -/* SAMA5 Virtual (mapped) Memory Map - * - * board_memorymap.h contains special mappings that are needed when a ROM - * memory map is used. It is included in this odd location because it - * depends on some the virtual address definitions provided above. - */ - -#include - /* SAMA5 Virtual (mapped) Memory Map. These are the mappings that will * be created if the page table lies in RAM. If the platform has another, * read-only, pre-initialized page table (perhaps in ROM), then the board.h @@ -562,12 +562,12 @@ # error "CONFIG_ARCH_ROMPGTABLE defined; PGTABLE_BASE_P/VADDR not defined" # endif -/* If CONFIG_PAGING is selected, then parts of the 1-to-1 virtual memory - * map probably do not apply because paging logic will probably partition - * the SRAM section differently. In particular, if the page table is located - * at the end of SRAM, then the virtual page table address defined below - * will probably be in error. In that case PGTABLE_BASE_VADDR is defined - * in the file mmu.h +/* If CONFIG_LEGACY_PAGING is selected, then parts of the 1-to-1 virtual + * memory map probably do not apply because paging logic will probably + * partition the SRAM section differently. In particular, if the page + * table is located at the end of SRAM, then the virtual page table address + * defined below will probably be in error. In that case PGTABLE_BASE_VADDR + * is defined in the file mmu.h * * We must declare the page table at the bottom or at the top of internal * SRAM. We pick the bottom of internal SRAM *unless* there are vectors @@ -579,18 +579,18 @@ /* In this case, page table must lie at the top 16Kb of ISRAM1 (or ISRAM0 * if ISRAM1 is not available in this architecture) * - * If CONFIG_PAGING is defined, then mmu.h assign the virtual address + * If CONFIG_LEGACY_PAGING is defined, then mmu.h assign the virtual address * of the page table. */ # if SAM_ISRAM1_SIZE > 0 # define PGTABLE_BASE_PADDR (SAM_ISRAM1_PADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE) -# ifndef CONFIG_PAGING +# ifndef CONFIG_LEGACY_PAGING # define PGTABLE_BASE_VADDR (SAM_ISRAM1_VADDR+SAM_ISRAM1_SIZE-PGTABLE_SIZE) # endif # else # define PGTABLE_BASE_PADDR (SAM_ISRAM0_PADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE) -# ifndef CONFIG_PAGING +# ifndef CONFIG_LEGACY_PAGING # define PGTABLE_BASE_VADDR (SAM_ISRAM0_VADDR+SAM_ISRAM0_SIZE-PGTABLE_SIZE) # endif # endif @@ -619,7 +619,7 @@ */ # define PGTABLE_BASE_PADDR SAM_ISRAM0_PADDR -# ifndef CONFIG_PAGING +# ifndef CONFIG_LEGACY_PAGING # define PGTABLE_BASE_VADDR SAM_ISRAM0_VADDR # endif # define PGTABLE_IN_LOWSRAM 1 @@ -703,9 +703,9 @@ * memory to address 0x0000:0000 using both the MMU and the AXI matrix * REMAP register. So no L2 page table is required. * - * 2) If on-demand paging is supported (CONFIG_PAGING=y), than an additional - * L2 page table is needed. This page table will use the remainder of - * the address space. + * 2) If on-demand paging is supported (CONFIG_LEGACY_PAGING=y), than an + * additional L2 page table is needed. This page table will use the + * remainder of the address space. */ #ifndef CONFIG_ARCH_LOWVECTORS @@ -738,7 +738,7 @@ /* Paging L2 page table base addresses * - * NOTE: If CONFIG_PAGING is defined, mmu.h will re-assign the virtual + * NOTE: If CONFIG_LEGACY_PAGING is defined, mmu.h will re-assign the virtual * address of the page table. */ diff --git a/arch/arm/src/sama5/sam_adc.c b/arch/arm/src/sama5/sam_adc.c index fe0be104d1b32..0ceb248f49207 100644 --- a/arch/arm/src/sama5/sam_adc.c +++ b/arch/arm/src/sama5/sam_adc.c @@ -481,8 +481,10 @@ static void sam_adc_gain(struct sam_adc_s *priv); static void sam_adc_analogchange(struct sam_adc_s *priv); static void sam_adc_sequencer(struct sam_adc_s *priv); static void sam_adc_channels(struct sam_adc_s *priv); +#if defined(CONFIG_SAMA5_ADC_PERIODIC_TRIG) static void sam_adc_trigperiod(struct sam_adc_s *priv, uint32_t period); #endif +#endif /**************************************************************************** * Private Data @@ -858,7 +860,7 @@ static int sam_adc_dmasetup(struct sam_adc_s *priv, uint8_t *buffer, * None * ****************************************************************************/ - +#if defined(CONFIG_SAMA5_ADC_PERIODIC_TRIG) static void sam_adc_trigperiod(struct sam_adc_s *priv, uint32_t period) { uint32_t trigper; @@ -909,6 +911,7 @@ static void sam_adc_trigperiod(struct sam_adc_s *priv, uint32_t period) regval |= ADC_TRGR_TRGPER(trigper); sam_adc_putreg(priv, SAM_ADC_TRGR, regval); } +#endif /**************************************************************************** * ADC interrupt handling @@ -1103,7 +1106,11 @@ static int sam_adc_bind(struct adc_dev_s *dev, static void sam_adc_reset(struct adc_dev_s *dev) { +#if defined(CONFIG_SAMA5_ADC_REGDEBUG) || \ + defined(CONFIG_SAMA5_ADC_DMA) || \ + defined(CONFIG_SAMA5_ADC_TIOATRIG) struct sam_adc_s *priv = (struct sam_adc_s *)dev->ad_priv; +#endif uint32_t regval; ainfo("Resetting..\n"); diff --git a/arch/arm/src/sama5/sam_boot.c b/arch/arm/src/sama5/sam_boot.c index 7efbb28f8ec01..b3c25246562f2 100644 --- a/arch/arm/src/sama5/sam_boot.c +++ b/arch/arm/src/sama5/sam_boot.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif @@ -102,7 +102,7 @@ static inline void sam_remap(void) ****************************************************************************/ #if !defined(CONFIG_ARCH_ROMPGTABLE) && defined(CONFIG_ARCH_LOWVECTORS) && \ - defined(CONFIG_PAGING) + defined(CONFIG_LEGACY_PAGING) static void sam_vectorpermissions(uint32_t mmuflags) { /* The PTE for the beginning of ISRAM is at the base of the L2 page table */ @@ -217,7 +217,7 @@ static void sam_copyvectorblock(void) uint32_t *end; uint32_t *dest; -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /* If we are using re-mapped vectors in an area that has been marked * read only, then temporarily mark the mapping write-able (non-buffered). */ @@ -243,7 +243,7 @@ static void sam_copyvectorblock(void) *dest++ = *src++; } -#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_PAGING) +#if !defined(CONFIG_ARCH_LOWVECTORS) && defined(CONFIG_LEGACY_PAGING) /* Make the vectors read-only, cacheable again */ sam_vectorpermissions(MMU_L2_VECTORFLAGS); diff --git a/arch/arm/src/sama5/sam_ehci.c b/arch/arm/src/sama5/sam_ehci.c index cc689589f3df4..7331a0678f676 100644 --- a/arch/arm/src/sama5/sam_ehci.c +++ b/arch/arm/src/sama5/sam_ehci.c @@ -2719,7 +2719,7 @@ static int sam_qh_cancel(struct sam_qh_s *qh, uint32_t **bp, void *arg) /* Check if this is the QH that we are looking for */ - if (qh->epinfo == epinfo) + if (qh->epinfo != epinfo) { /* No... keep looking */ @@ -4441,7 +4441,7 @@ static int sam_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep) * head. */ - if (qh && qh != &g_asynchead) + if (qh && qh == &g_asynchead) { /* Claim that we successfully cancelled the transfer */ diff --git a/arch/arm/src/sama5/sam_irq.c b/arch/arm/src/sama5/sam_irq.c index 430f13df2289c..b3f07dc0a1b7f 100644 --- a/arch/arm/src/sama5/sam_irq.c +++ b/arch/arm/src/sama5/sam_irq.c @@ -617,11 +617,11 @@ uint32_t *arm_decodeirq(uint32_t *regs) return sam_decodeirq(SAM_AIC_VBASE, regs); } -#if defined(CONFIG_SAMA5_SAIC) /* This is the entry point from the ARM FIQ vector handler */ uint32_t *arm_decodefiq(uint32_t *regs) { +#if defined(CONFIG_SAMA5_SAIC) uint32_t *ret; /* In order to distinguish a FIQ from a true secure interrupt we need to @@ -646,8 +646,11 @@ uint32_t *arm_decodefiq(uint32_t *regs) } return ret; -} +#else + DEBUGASSERT(false); + return NULL; #endif +} /**************************************************************************** * Name: up_disable_irq (and sam_disable_irq helper) diff --git a/arch/arm/src/sama5/sam_lcd.c b/arch/arm/src/sama5/sam_lcd.c index 5a11653801ea5..8f6ca524fdd55 100644 --- a/arch/arm/src/sama5/sam_lcd.c +++ b/arch/arm/src/sama5/sam_lcd.c @@ -2282,6 +2282,9 @@ static void sam_lcd_enable(void) #ifdef BOARD_LCDC_PIXCLK_INV regval |= LCDC_LCDCFG0_CLKPOL; #endif +#ifdef BOARD_LCDC_PWMCLK + regval |= LCDC_LCDCFG0_CLKPWMSEL; +#endif #ifdef BOARD_LCDC_MCK_MUL2 regval |= LCDC_LCDCFG0_CLKSEL; #endif diff --git a/arch/arm/src/sama5/sam_lowputc.c b/arch/arm/src/sama5/sam_lowputc.c index 9caf822362855..51130a3ad6305 100644 --- a/arch/arm/src/sama5/sam_lowputc.c +++ b/arch/arm/src/sama5/sam_lowputc.c @@ -27,6 +27,7 @@ #include #include +#include #include "arm_internal.h" #include "sam_pio.h" @@ -235,18 +236,18 @@ void arm_lowputc(char ch) * atomic. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if ((getreg32(SAM_CONSOLE_VBASE + SAM_UART_SR_OFFSET) & UART_INT_TXEMPTY) != 0) { /* Send the character */ putreg32((uint32_t)ch, SAM_CONSOLE_VBASE + SAM_UART_THR_OFFSET); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); return; } - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } #elif defined(SAMA5_HAVE_FLEXCOM_CONSOLE) diff --git a/arch/arm/src/sama5/sam_serial.c b/arch/arm/src/sama5/sam_serial.c index 6d56c6dd311bd..45d74c6ee646d 100644 --- a/arch/arm/src/sama5/sam_serial.c +++ b/arch/arm/src/sama5/sam_serial.c @@ -1019,6 +1019,7 @@ static int up_setup(struct uart_dev_s *dev) up_shutdown(dev); #if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL) +#if defined(ATSAMA5D3) || defined(ATSAMA5D4) /* Setting the USART to operate with hardware handshaking is performed by * writing the USART_MODE field in the Mode Register (US_MR) to the value * 0x2. ... Using this mode requires using the PDC or DMAC channel for @@ -1032,6 +1033,7 @@ static int up_setup(struct uart_dev_s *dev) regval = (UART_MR_MODE_HWHS | SAM_MR_USCLKS | UART_MR_CHMODE_NORMAL); } else +#endif #endif { #if defined(ATSAMA5D2) diff --git a/arch/arm/src/sama5/sam_spi.c b/arch/arm/src/sama5/sam_spi.c index d3579a1c575d7..b9a2ed104c379 100644 --- a/arch/arm/src/sama5/sam_spi.c +++ b/arch/arm/src/sama5/sam_spi.c @@ -507,7 +507,7 @@ static void spi_dumpregs(struct sam_spidev_s *spi, const char *msg) getreg32(spi->base + SAM_SPI_MR_OFFSET), getreg32(spi->base + SAM_SPI_SR_OFFSET), getreg32(spi->base + SAM_SPI_IMR_OFFSET)); - spiinfo(" CSR0:%" PRIx32 " CSR1:%" PRIx32 " CSR2:%" PRIx32 " CSR3:%" \ + spiinfo(" CSR0:%" PRIx32 " CSR1:%" PRIx32 " CSR2:%" PRIx32 " CSR3:%" PRIx32 "\n", getreg32(spi->base + SAM_SPI_CSR0_OFFSET), getreg32(spi->base + SAM_SPI_CSR1_OFFSET), diff --git a/arch/arm/src/sama5/sam_tsd.c b/arch/arm/src/sama5/sam_tsd.c index a9fa4655159ff..e6f31cbc6490e 100644 --- a/arch/arm/src/sama5/sam_tsd.c +++ b/arch/arm/src/sama5/sam_tsd.c @@ -65,7 +65,10 @@ #include #include -#include +#if !defined(CONFIG_SAMA5_ADC_PERIODIC_TRIG) && \ + !defined(CONFIG_SAMA5_ADC_CONTINUOUS_TRIG) +# include +#endif #include #include #include @@ -91,13 +94,13 @@ */ #define DEV_FORMAT "/dev/input%d" -#define DEV_NAMELEN 16 +#define DEV_NAMELEN 24 /* Poll the pen position while the pen is down at this rate (50MS): */ #define TSD_WDOG_DELAY MSEC2TICK(50) -/* This is a value for the threshold that guantees a big difference on the +/* This is a value for the threshold that guarantees a big difference on the * first pendown (but can't overflow). */ @@ -114,7 +117,7 @@ /* Pen sample state bit sets */ #ifdef CONFIG_SAMA5_TSD_4WIRE -# define TSD_PENUP_VALID (TOUCH_UP | TOUCH_ID_VALID | TOUCH_POS_VALID | \ +# define TSD_PENUP_VALID (TOUCH_UP | TOUCH_ID_VALID | TOUCH_POS_VALID | \ TOUCH_PRESSURE_VALID) # define TSD_PENUP_INVALID (TOUCH_UP | TOUCH_ID_VALID) # define TSD_PENDOWN (TOUCH_DOWN | TOUCH_ID_VALID | TOUCH_POS_VALID | \ @@ -122,8 +125,8 @@ # define TSD_PENMOVE (TOUCH_MOVE | TOUCH_ID_VALID | TOUCH_POS_VALID | \ TOUCH_PRESSURE_VALID) #else -# define TSD_PENUP_VALID (TOUCH_UP | TOUCH_ID_VALID | TOUCH_POS_VALID) -# define TSD_PENUP_INVALID (TOUCH_UP | TOUCH_ID_VALID) +# define TSD_PENUP_VALID (TOUCH_UP | TOUCH_ID_VALID | TOUCH_POS_VALID) +# define TSD_PENUP_INVALID (TOUCH_UP | TOUCH_ID_VALID) # define TSD_PENDOWN (TOUCH_DOWN | TOUCH_ID_VALID | TOUCH_POS_VALID) # define TSD_PENMOVE (TOUCH_MOVE | TOUCH_ID_VALID | TOUCH_POS_VALID) #endif @@ -136,59 +139,78 @@ # define BOARD_TSD_PENDETSENS 0 #endif +/* The driver has always used 8 sample averages for the default filtering, + * once a pen down has been detected. + * With typical periodic sample rates of 20ms+, this means some loss of + * precision of touchscreen movement detection, or even missed touches. + * A board-level #define can override this default + */ + +#ifndef BOARD_TSD_PENDOWN_TSAV +# define BOARD_TSD_PENDOWN_TSAV ADC_TSMR_TSAV_8CONV +#endif + #if !defined BOARD_TSD_IBCTL && defined ATSAMA5D2 # define BOARD_TSD_IBCTL 0 #endif +#ifndef BOARD_TOUCHSCREEN_SAMPLE_CACHES +# define BOARD_TOUCHSCREEN_SAMPLE_CACHES 64 +#endif + /**************************************************************************** * Private Types ****************************************************************************/ -/* This describes the state of one contact */ +/* This describes the state of one contact */ enum sam_contact_e { - CONTACT_NONE = 0, /* No contact */ - CONTACT_DOWN, /* First contact */ - CONTACT_MOVE, /* Same contact, possibly different position */ - CONTACT_UP, /* Contact lost */ + CONTACT_NONE = 0, /* No contact */ + CONTACT_DOWN, /* First contact */ + CONTACT_MOVE, /* Same contact, possibly diff. position */ + CONTACT_UP, /* Contact lost */ }; -/* This structure describes the results of one touchscreen sample */ +/* This structure describes the results of one touchscreen sample */ struct sam_sample_s { - uint8_t id; /* Sampled touch point ID */ - uint8_t contact; /* Contact state (see enum sam_contact_e) */ - bool valid; /* True: x,y,p contain valid, sampled data */ - uint16_t x; /* Measured X position */ - uint16_t y; /* Measured Y position */ + uint8_t id; /* Sampled touch point ID */ + uint8_t contact; /* Contact state (see enum sam_contact_e) */ + bool valid; /* True: x,y,p contain valid, sampled data */ + uint16_t x; /* Measured X position */ + uint16_t y; /* Measured Y position */ #ifdef CONFIG_SAMA5_TSD_4WIRE - uint16_t p; /* Measured pressure */ + uint16_t p; /* Measured pressure */ #endif }; -/* This structure describes the state of one touchscreen driver instance */ +/* This structure describes the state of one touchscreen driver instance */ struct sam_tsd_s { - uint8_t nwaiters; /* Num threads waiting for TSD data */ - uint8_t id; /* Current touch point ID */ - uint8_t valid; /* Data ready bit set */ - uint8_t crefs; /* Number of times device opened */ - volatile bool penchange; /* An unreported event is buffered */ - uint32_t threshx; /* Thresholding X value */ - uint32_t threshy; /* Thresholding Y value */ - sem_t waitsem; /* Used to wait for data available */ - - struct sam_adc_s *adc; /* ADC device handle */ - struct work_s work; /* Supports int. handling "bottom half" */ - struct sam_sample_s sample; /* Last sampled touch point data */ - struct wdog_s wdog; /* Poll position while the pen is down */ - struct g_tscaldata_s caldata; /* Touchscreen Calibration Data */ + uint8_t nwaiters; /* Num threads waiting for TSD data */ + uint8_t id; /* Current touch point ID */ + uint8_t valid; /* Data ready bit set */ + uint8_t crefs; /* Number of times device opened */ + volatile bool penchange; /* An unreported event is buffered */ + uint32_t threshx; /* Thresholding X value */ + uint32_t threshy; /* Thresholding Y value */ + sem_t waitsem; /* Used to wait for data available */ + + struct sam_adc_s *adc; /* ADC device handle */ + struct work_s work; /* Supports int. handling "bottom half" */ + struct sam_sample_s sample; /* Last sampled touch point data */ +#if !defined(CONFIG_SAMA5_ADC_PERIODIC_TRIG) && \ + !defined(CONFIG_SAMA5_ADC_CONTINUOUS_TRIG) + struct wdog_s wdog; /* Poll position while the pen is down */ +#endif + struct g_tscaldata_s caldata; /* Touchscreen Calibration Data */ bool scaled; /* Character dreiver read should return * scaled values (true) or not (false). */ + uint32_t pending; /* saved ISR status from the ADC driver */ /* The following is a list if poll structures of threads waiting for * driver events. The 'struct pollfd' reference for each open is also @@ -211,8 +233,10 @@ static int sam_tsd_waitsample(struct sam_tsd_s *priv, struct sam_sample_s *sample); static void sam_tsd_bottomhalf(void *arg); static int sam_tsd_schedule(struct sam_tsd_s *priv); +#if !defined(CONFIG_SAMA5_ADC_PERIODIC_TRIG) && \ + !defined(CONFIG_SAMA5_ADC_CONTINUOUS_TRIG) static void sam_tsd_expiry(wdparm_t arg); - +#endif /* Character driver methods */ static int sam_tsd_open(struct file *filep); @@ -501,25 +525,31 @@ static void sam_tsd_bottomhalf(void *arg) uint32_t yscale; uint32_t y; uint32_t ydiff; +#ifdef CONFIG_SAMA5_TSD_4WIRE uint32_t z1; uint32_t z2; uint32_t pressr; uint32_t p; +#endif bool pendown; DEBUGASSERT(priv != NULL); - - /* Get the set of pending ADC interrupts and pen status */ - - pending = sam_adc_getreg(priv->adc, SAM_ADC_ISR); + regval = sam_adc_getreg(priv->adc, SAM_ADC_TRGR); /* Get exclusive access to the driver data structure */ sam_adc_lock(priv->adc); + pending = priv->pending; /* ISR status passed to us from the ADC driver */ - /* Check the pen state */ + /* Check the pen state. Down if: + * - Pen status is down OR + * - Pen down interrupt seen, but NOT if + * - Pen up interrrupt occurred as we need to deal with that + */ - pendown = ((pending & ADC_SR_PENS) != 0); + pendown = ((((pending & ADC_SR_PENS) != 0) || + ((pending & ADC_INT_PEN) != 0)) && + (pending & ADC_INT_NOPEN) == 0); /* Handle the change from pen down to pen up */ @@ -536,8 +566,11 @@ static void sam_tsd_bottomhalf(void *arg) /* We will enable only the ADC_INT_PEN interrupt on exit. We don't * want to hear anything from the touchscreen until the next touch. */ - +#ifdef SAMA5_TSD_TRIG_CHANGE_ALLOWED ier = ADC_INT_PEN; +#else + ier = ADC_TSD_PRESSINTS; +#endif /* Ignore the interrupt if the pen was already up (CONTACT_NONE == pen * up and already reported; CONTACT_UP == pen up, but not reported) @@ -547,6 +580,7 @@ static void sam_tsd_bottomhalf(void *arg) priv->sample.contact == CONTACT_UP) { + iinfo("\t\t\t\t\tIgnored interrupt\n"); goto ignored; } @@ -562,7 +596,7 @@ static void sam_tsd_bottomhalf(void *arg) sam_tsd_setaverage(priv, ADC_TSMR_TSAV_NOFILTER); sam_tsd_debounce(priv, BOARD_TSD_DEBOUNCE); -#ifdef SAMA5_TSD_PENDET_TRIG_ALLOWED +#ifdef SAMA5_TSD_TRIG_CHANGE_ALLOWED regval = sam_adc_getreg(priv->adc, SAM_ADC_TRGR); regval &= ~ADC_TRGR_TRGMOD_MASK; regval |= ADC_TRGR_TRGMOD_PEN; @@ -583,10 +617,13 @@ static void sam_tsd_bottomhalf(void *arg) * a little later. NOTE that pen interrupts are not re-enabled in * this case; we rely on the timer expiry to get us going again. */ - +#if !defined(CONFIG_SAMA5_ADC_PERIODIC_TRIG) && \ + !defined(CONFIG_SAMA5_ADC_CONTINUOUS_TRIG) wd_start(&priv->wdog, TSD_WDOG_DELAY, sam_tsd_expiry, (wdparm_t)priv); ier = 0; +#endif + iinfo("\t\t\t\t\tlast event not processed\n"); goto ignored; } else @@ -599,7 +636,7 @@ static void sam_tsd_bottomhalf(void *arg) ier = ADC_TSD_RELEASEINTS; - /* Check if all of the date that we need is available. If not, just + /* Check if all of the data that we need is available. If not, just * re-enable interrupts and wait until it is. */ @@ -607,15 +644,14 @@ static void sam_tsd_bottomhalf(void *arg) { /* But don't enable interrupts for the data that we already have */ - ier &= ~(pending & TSD_ALLREADY); + ier &= ~pending & TSD_ALLREADY; /* datasheet says that if TSAV != 0 there may not be interrupts - * for TSD channels so periodic or continuous triggers are needed - * unless we're already using periodic triggers (for std adc ops). + * for TSD channels so periodic or continuous triggers are needed. + * We may be already using periodic triggers (for std adc ops). */ -#ifdef SAMA5_TSD_PENDET_TRIG_ALLOWED +#ifdef SAMA5_TSD_TRIG_CHANGE_ALLOWED regval = sam_adc_getreg(priv->adc, SAM_ADC_TSMR); - regval &= ADC_TSMR_TSAV_MASK; if ((regval & ADC_TSMR_TSAV_MASK) != 0) { regval = sam_adc_getreg(priv->adc, SAM_ADC_TRGR); @@ -628,11 +664,13 @@ static void sam_tsd_bottomhalf(void *arg) } #endif + iinfo("\t\t\t\t\tNot all data ready to read\n"); goto ignored; } /* Sample positional values. Get raw X and Y position data */ + iinfo("\t\t\t\t\tsampling data\n"); regval = sam_adc_getreg(priv->adc, SAM_ADC_XPOSR); xraw = (regval & ADC_XPOSR_XPOS_MASK) >> ADC_XPOSR_XPOS_SHIFT; xscale = (regval & ADC_XPOSR_XSCALE_MASK) >> ADC_XPOSR_XSCALE_SHIFT; @@ -650,12 +688,13 @@ static void sam_tsd_bottomhalf(void *arg) #endif /* Discard any bad readings. This check may not be necessary. */ - if (xraw == 0 || xraw >= xscale || yraw == 0 || yraw > yscale) + if (xraw == 0 || xraw > xscale || yraw == 0 || yraw > yscale) { iwarn("WARNING: Discarding: x %" PRId32 ":%" PRId32 " y %" PRId32 ":%" PRId32 "\n", xraw, xscale, yraw, yscale); + iinfo("\t\t\t\t\tBad reading\n"); goto ignored; } @@ -668,11 +707,11 @@ static void sam_tsd_bottomhalf(void *arg) */ #ifdef CONFIG_SAMA5_TSD_SWAPXY - x = ((yraw << 12)) / yscale; - y = ((xraw << 12)) / xscale; + x = ((yraw << 12) - yraw) / yscale; + y = ((xraw << 12) - xraw) / xscale; #else - x = ((xraw << 12)) / xscale; - y = ((yraw << 12)) / yscale; + x = ((xraw << 12) - xraw) / xscale; + y = ((yraw << 12) - yraw) / yscale; #endif /* Perform a thresholding operation so that the results will be @@ -685,10 +724,11 @@ static void sam_tsd_bottomhalf(void *arg) ydiff = y > priv->threshy ? (y - priv->threshy) : (priv->threshy - y); /* Continue to sample the position while the pen is down */ - +#if !defined(CONFIG_SAMA5_ADC_PERIODIC_TRIG) && \ + !defined(CONFIG_SAMA5_ADC_CONTINUOUS_TRIG) wd_start(&priv->wdog, TSD_WDOG_DELAY, sam_tsd_expiry, (wdparm_t)priv); - +#endif /* Check the thresholds. Bail if (1) this is not the first * measurement and (2) there is no significant difference from * the last measurement. @@ -702,6 +742,7 @@ static void sam_tsd_bottomhalf(void *arg) * anything. */ + iinfo("\t\t\t\t\tNo change\n"); goto ignored; } @@ -753,13 +794,12 @@ static void sam_tsd_bottomhalf(void *arg) /* First contact. Handle transitions from pen UP to pen DOWN */ priv->sample.contact = CONTACT_DOWN; + sam_tsd_setaverage(priv, BOARD_TSD_PENDOWN_TSAV); + sam_tsd_debounce(priv, 300); /* 300ns */ -#ifdef SAMA5_TSD_PENDET_TRIG_ALLOWED /* Configure for periodic trigger */ - sam_tsd_setaverage(priv, ADC_TSMR_TSAV_8CONV); - sam_tsd_debounce(priv, 300); /* 300ns */ - +#ifdef SAMA5_TSD_TRIG_CHANGE_ALLOWED regval = sam_adc_getreg(priv->adc, SAM_ADC_TRGR); regval &= ~ADC_TRGR_TRGMOD_MASK; regval |= ADC_TRGR_TRGMOD_PERIOD; @@ -801,9 +841,10 @@ static int sam_tsd_schedule(struct sam_tsd_s *priv) /* Disable the watchdog timer. It will be re-enabled in the worker thread * while the pen remains down. */ - +#if !defined(CONFIG_SAMA5_ADC_PERIODIC_TRIG) && \ + !defined(CONFIG_SAMA5_ADC_CONTINUOUS_TRIG) wd_cancel(&priv->wdog); - +#endif /* Disable further touchscreen interrupts. Touchscreen interrupts will be * re-enabled after the worker thread executes. */ @@ -833,7 +874,8 @@ static int sam_tsd_schedule(struct sam_tsd_s *priv) * watchdog timer. This function handles that timer expiration. * ****************************************************************************/ - +#if !defined(CONFIG_SAMA5_ADC_PERIODIC_TRIG) && \ + !defined(CONFIG_SAMA5_ADC_CONTINUOUS_TRIG) static void sam_tsd_expiry(wdparm_t arg) { struct sam_tsd_s *priv = (struct sam_tsd_s *)arg; @@ -842,6 +884,7 @@ static void sam_tsd_expiry(wdparm_t arg) sam_tsd_schedule(priv); } +#endif /**************************************************************************** * Name: sam_tsd_open @@ -936,6 +979,7 @@ static ssize_t sam_tsd_read(struct file *filep, char *buffer, size_t len) struct sam_tsd_s *priv; struct touch_sample_s *report; struct sam_sample_s sample; + int regval; int ret; iinfo("buffer:%p len:%d\n", buffer, len); @@ -967,7 +1011,7 @@ static ssize_t sam_tsd_read(struct file *filep, char *buffer, size_t len) ret = sam_tsd_sample(priv, &sample); if (ret < 0) { - /* Sample data is not available now. We would ave to wait to get + /* Sample data is not available now. We would have to wait to get * receive sample data. If the user has specified the O_NONBLOCK * option, then just return an error. */ @@ -978,6 +1022,18 @@ static ssize_t sam_tsd_read(struct file *filep, char *buffer, size_t len) ret = -EAGAIN; goto errout; } + else + { + /* If we have opened in blocking mode, there is a big risk that + * we cause the system to hang because tsd_wait_sample will enter + * a critical section until an adc sample is available - which may + * be a very long time if the pen detect ADC trigger is in use. + */ + + regval = sam_adc_getreg(priv->adc, SAM_ADC_TRGR); + regval &= ADC_TRGR_TRGMOD_MASK; + DEBUGASSERT(regval != ADC_TRGR_TRGMOD_PEN); + } /* Wait for sample data */ @@ -1554,7 +1610,7 @@ static void sam_tsd_initialize(struct sam_tsd_s *priv) { uint32_t regval; -#ifdef SAMA5_TSD_PENDET_TRIG_ALLOWED +#ifdef SAMA5_TSD_TRIG_CHANGE_ALLOWED /* Disable touch trigger */ regval = sam_adc_getreg(priv->adc, SAM_ADC_TRGR); @@ -1569,17 +1625,20 @@ static void sam_tsd_initialize(struct sam_tsd_s *priv) sam_tsd_tracking(priv, BOARD_TSD_TRACKTIM); /* set trigger mode to be periodic in case ADC not already - * been initialised. It's the only option allowed and that works. + * been initialised. It's the only option allowed and that works, unless + * continuous mode is set of course. */ -#ifndef SAMA5_TSD_PENDET_TRIG_ALLOWED - /* if we're allowed to use pendet trigger no need to do this */ - +#ifdef CONFIG_SAMA5_ADC_TRIGGER_PERIOD regval = sam_adc_getreg(priv, SAM_ADC_TRGR); regval &= ~ADC_TRGR_TRGMOD_MASK; regval |= ADC_TRGR_TRGMOD_PERIOD; sam_adc_putreg(priv, SAM_ADC_TRGR, regval); sam_tsd_trigperiod(priv, CONFIG_SAMA5_ADC_TRIGGER_PERIOD); + + /* Make sure the configured trigger period is used */ + + sam_tsd_trigperiod(priv, CONFIG_SAMA5_ADC_TRIGGER_PERIOD); #else sam_tsd_trigperiod(priv, 20000); /* 20ms */ #endif @@ -1643,7 +1702,7 @@ static void sam_tsd_initialize(struct sam_tsd_s *priv) #endif sam_adc_putreg(priv->adc, SAM_ADC_ACR, regval); -#ifdef SAMA5_TSD_PENDET_TRIG_ALLOWED +#ifdef SAMA5_TSD_TRIG_CHANGE_ALLOWED /* we assume periodic otherwise */ /* Configure pen interrupt generation */ regval = sam_adc_getreg(priv->adc, SAM_ADC_TRGR); @@ -1661,6 +1720,7 @@ static void sam_tsd_initialize(struct sam_tsd_s *priv) sam_adc_putreg(priv->adc, SAM_ADC_CR, regval); #endif + regval = sam_adc_getreg(priv->adc, SAM_ADC_ISR); up_enable_irq(SAM_IRQ_ADC); } @@ -1687,15 +1747,16 @@ static void sam_tsd_uninitialize(struct sam_tsd_s *priv) /* Disable the watchdog timer. It will be re-enabled in the worker thread * while the pen remains down. */ - +#if !defined(CONFIG_SAMA5_ADC_PERIODIC_TRIG) && \ + !defined(CONFIG_SAMA5_ADC_CONTINUOUS_TRIG) wd_cancel(&priv->wdog); - +#endif /* Disable further touchscreen interrupts. Touchscreen interrupts will be * re-enabled after the worker thread executes. */ sam_adc_putreg(priv->adc, SAM_ADC_IDR, ADC_TSD_ALLINTS); -#ifdef SAMA5_TSD_PENDET_TRIG_ALLOWED +#ifdef SAMA5_TSD_TRIG_CHANGE_ALLOWED /* Disable touch trigger */ regval = sam_adc_getreg(priv->adc, SAM_ADC_TRGR); @@ -1800,6 +1861,7 @@ void sam_tsd_interrupt(uint32_t pending) * worker thread. */ + priv->pending = pending; ret = sam_tsd_schedule(priv); if (ret < 0) { diff --git a/arch/arm/src/sama5/sam_tsd.h b/arch/arm/src/sama5/sam_tsd.h index 00e684a6715de..8dcb0c1af3ea8 100644 --- a/arch/arm/src/sama5/sam_tsd.h +++ b/arch/arm/src/sama5/sam_tsd.h @@ -40,14 +40,27 @@ # define CONFIG_SAMA5_TSD_RXP 6 #endif +#if !defined(CONFIG_SAMA5_ADC_SWTRIG) && \ + !defined(CONFIG_SAMA5_ADC_PERIODIC_TRIG) && \ + !defined(CONFIG_SAMA5_ADC_CONTINUOUS_TRIG) +# warning ADC trigger mode incompatible with TSD operation +#endif + #ifndef CONFIG_SAMA5_ADC_TRIGGER_PERIOD # define CONFIG_SAMA5_ADC_TRIGGER_PERIOD 20000 #endif -/* Only allow Pendet triggering in limited circumstances */ +/* Only allow TSD trigger mode changes in limited circumstances. + * The TSD driver changes between pen detection and periodic triggers + * but this can upset normal non-tsd ADC operation, so we only allow the + * driver to change the mode if SW trigger mode is set. + * NB - this still might conflict of course so BEWARE! + */ -#if defined(CONFIG_SAMA5_ADC_SWTRIG) -# define SAMA5_TSD_PENDET_TRIG_ALLOWED +#ifdef CONFIG_SAMA5_ADC_SWTRIG +# define SAMA5_TSD_TRIG_CHANGE_ALLOWED +#else +# warning TSD will not be using Pen Detection interrupts #endif /* Touchscreen interrupt event sets @@ -60,6 +73,7 @@ * ADC_SR_PENS Pen detect Status (Not an interrupt) */ +#define ADC_TSD_PRESSINTS (ADC_INT_XRDY | ADC_INT_YRDY | ADC_INT_PRDY | ADC_INT_PEN) #define ADC_TSD_CMNINTS (ADC_INT_XRDY | ADC_INT_YRDY | ADC_INT_PRDY | ADC_INT_NOPEN) #define ADC_TSD_ALLINTS (ADC_TSD_CMNINTS | ADC_INT_PEN) #define ADC_TSD_ALLSTATUS (ADC_TSD_ALLINTS | ADC_SR_PENS) diff --git a/arch/arm/src/sama5/sama5d2x_memorymap.c b/arch/arm/src/sama5/sama5d2x_memorymap.c index 3e5ce8feb79b8..76b8dea2312eb 100644 --- a/arch/arm/src/sama5/sama5d2x_memorymap.c +++ b/arch/arm/src/sama5/sama5d2x_memorymap.c @@ -97,7 +97,7 @@ const struct section_mapping_s g_section_mapping[] = SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS }, -#ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */ +#ifndef CONFIG_LEGACY_PAGING /* Internal SRAM is already fully mapped */ { SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION, SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS }, diff --git a/arch/arm/src/sama5/sama5d3x_memorymap.c b/arch/arm/src/sama5/sama5d3x_memorymap.c index 5916f0447bdd4..59a13169ded9b 100644 --- a/arch/arm/src/sama5/sama5d3x_memorymap.c +++ b/arch/arm/src/sama5/sama5d3x_memorymap.c @@ -110,7 +110,7 @@ const struct section_mapping_s g_section_mapping[] = SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS }, -#ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */ +#ifndef CONFIG_LEGACY_PAGING /* Internal SRAM is already fully mapped */ { SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION, SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS }, diff --git a/arch/arm/src/sama5/sama5d4x_memorymap.c b/arch/arm/src/sama5/sama5d4x_memorymap.c index 914d311682729..5c32bb608b0c6 100644 --- a/arch/arm/src/sama5/sama5d4x_memorymap.c +++ b/arch/arm/src/sama5/sama5d4x_memorymap.c @@ -110,7 +110,7 @@ const struct section_mapping_s g_section_mapping[] = SAM_NFCSRAM_MMUFLAGS, SAM_NFCSRAM_NSECTIONS }, -#ifndef CONFIG_PAGING /* Internal SRAM is already fully mapped */ +#ifndef CONFIG_LEGACY_PAGING /* Internal SRAM is already fully mapped */ { SAM_ISRAM_PSECTION, SAM_ISRAM_VSECTION, SAM_ISRAM_MMUFLAGS, SAM_ISRAM_NSECTIONS }, diff --git a/arch/arm/src/samd2l2/sam_serial.c b/arch/arm/src/samd2l2/sam_serial.c index 3fd443b1915df..342548fc6a7b2 100644 --- a/arch/arm/src/samd2l2/sam_serial.c +++ b/arch/arm/src/samd2l2/sam_serial.c @@ -1045,7 +1045,7 @@ int up_putc(int ch) * interrupts from firing in the serial driver code. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); /* Check for LF */ @@ -1057,7 +1057,7 @@ int up_putc(int ch) } sam_lowputc(ch); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); #endif return ch; } diff --git a/arch/arm/src/samd5e5/sam_serial.c b/arch/arm/src/samd5e5/sam_serial.c index bfd460d92c1a4..c5b3687419677 100644 --- a/arch/arm/src/samd5e5/sam_serial.c +++ b/arch/arm/src/samd5e5/sam_serial.c @@ -1104,7 +1104,7 @@ int up_putc(int ch) * interrupts from firing in the serial driver code. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); /* Check for LF */ @@ -1116,7 +1116,7 @@ int up_putc(int ch) } sam_lowputc(ch); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); #endif return ch; } diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig index 84bfec41ecacf..0c90741383dc3 100644 --- a/arch/arm/src/samv7/Kconfig +++ b/arch/arm/src/samv7/Kconfig @@ -275,6 +275,10 @@ config SAMV7_DAC bool default n +config SAMV7_QENCODER + bool + default n + config SAMV7_HAVE_DAC1 bool default n @@ -283,6 +287,10 @@ config SAMV7_HAVE_EBI bool default n +config SAMV7_EEFC + bool + default n + config SAMV7_EMAC bool default n @@ -360,6 +368,10 @@ config SAMV7_1WIREDRIVER bool default n +config SAMV7_USART_IS_SPI_MASTER + bool + default n + config SAMV7_HAVE_USART0 bool default n @@ -661,14 +673,31 @@ menuconfig SAMV7_PWM0 if SAMV7_PWM0 +config SAMV7_PWM0_SYNC + bool "PWM0 synchronous channels" + depends on PWM_MULTICHAN + default n + ---help--- + This option makes the synchronization between channels possible. + This means every synchronized channel has the same clock, the + same period and the same alignment. If any channel is defined + as synchronous, channel 0 is defined as synchronous too because + channel 0's counter is used by other synchronous channels. + This option automatically defines channel 0 as synchronous. + config SAMV7_PWM0_CH0 bool "PWM0 Channel 0" default n if SAMV7_PWM0_CH0 +config SAMV7_PWM0_CH0_LONLY + bool "Use only L output" + default n + config SAMV7_PWM0_CH0_COMP bool "Use complementary output" + depends on !SAMV7_PWM0_CH0_LONLY default n endif @@ -679,8 +708,18 @@ config SAMV7_PWM0_CH1 if SAMV7_PWM0_CH1 +config SAMV7_PWM0_CH1_LONLY + bool "Use only L output" + default n + config SAMV7_PWM0_CH1_COMP bool "Use complementary output" + depends on !SAMV7_PWM0_CH1_LONLY + default n + +config SAMV7_PWM0_CH1_SYNC + bool "Synchronous channel" + depends on SAMV7_PWM0_SYNC default n endif @@ -691,8 +730,18 @@ config SAMV7_PWM0_CH2 if SAMV7_PWM0_CH2 +config SAMV7_PWM0_CH2_LONLY + bool "Use only L output" + default n + config SAMV7_PWM0_CH2_COMP bool "Use complementary output" + depends on !SAMV7_PWM0_CH2_LONLY + default n + +config SAMV7_PWM0_CH2_SYNC + bool "Synchronous channel" + depends on SAMV7_PWM0_SYNC default n endif @@ -703,8 +752,18 @@ config SAMV7_PWM0_CH3 if SAMV7_PWM0_CH3 +config SAMV7_PWM0_CH3_LONLY + bool "Use only L output" + default n + config SAMV7_PWM0_CH3_COMP bool "Use complementary output" + depends on !SAMV7_PWM0_CH3_LONLY + default n + +config SAMV7_PWM0_CH3_SYNC + bool "Synchronous channel" + depends on SAMV7_PWM0_SYNC default n endif @@ -785,9 +844,9 @@ config SAMV7_PWM0_PA9 bool "External fault input from PA9" default n -if SAMV7_PWM1_PA9 +if SAMV7_PWM0_PA9 -config SAMV7_PWM1_PA9_POL +config SAMV7_PWM0_PA9_POL bool "Inverted polarity" default n ---help--- @@ -800,9 +859,9 @@ config SAMV7_PWM0_PD8 bool "External fault input from PD8" default n -if SAMV7_PWM1_PD8 +if SAMV7_PWM0_PD8 -config SAMV7_PWM1_PD8_POL +config SAMV7_PWM0_PD8_POL bool "Inverted polarity" default n ---help--- @@ -815,9 +874,9 @@ config SAMV7_PWM0_PD9 bool "External fault input from PD9" default n -if SAMV7_PWM1_PD9 +if SAMV7_PWM0_PD9 -config SAMV7_PWM1_PD9_POL +config SAMV7_PWM0_PD9_POL bool "Inverted polarity" default n ---help--- @@ -877,14 +936,31 @@ menuconfig SAMV7_PWM1 if SAMV7_PWM1 +config SAMV7_PWM1_SYNC + bool "PWM1 synchronous channels" + depends on PWM_MULTICHAN + default n + ---help--- + This option makes the synchronization between channels possible. + This means every synchronized channel has the same clock, the + same period and the same alignment. If any channel is defined + as synchronous, channel 0 is defined as synchronous too because + channel 0's counter is used by other synchronous channels. + This option automatically defines channel 0 as synchronous. + config SAMV7_PWM1_CH0 bool "PWM1 Channel 0" default n if SAMV7_PWM1_CH0 +config SAMV7_PWM1_CH0_LONLY + bool "Use only L output" + default n + config SAMV7_PWM1_CH0_COMP bool "Use complementary output" + depends on !SAMV7_PWM1_CH0_LONLY default n endif @@ -895,8 +971,18 @@ config SAMV7_PWM1_CH1 if SAMV7_PWM1_CH1 +config SAMV7_PWM1_CH1_LONLY + bool "Use only L output" + default n + config SAMV7_PWM1_CH1_COMP bool "Use complementary output" + depends on !SAMV7_PWM1_CH1_LONLY + default n + +config SAMV7_PWM1_CH1_SYNC + bool "Synchronous channel" + depends on SAMV7_PWM1_SYNC default n endif @@ -907,8 +993,18 @@ config SAMV7_PWM1_CH2 if SAMV7_PWM1_CH2 +config SAMV7_PWM1_CH2_LONLY + bool "Use only L output" + default n + config SAMV7_PWM1_CH2_COMP bool "Use complementary output" + depends on !SAMV7_PWM1_CH2_LONLY + default n + +config SAMV7_PWM1_CH2_SYNC + bool "Synchronous channel" + depends on SAMV7_PWM1_SYNC default n endif @@ -919,8 +1015,18 @@ config SAMV7_PWM1_CH3 if SAMV7_PWM1_CH3 +config SAMV7_PWM1_CH3_LONLY + bool "Use only L output" + default n + config SAMV7_PWM1_CH3_COMP bool "Use complementary output" + depends on !SAMV7_PWM1_CH3_LONLY + default n + +config SAMV7_PWM1_CH3_SYNC + bool "Synchronous channel" + depends on SAMV7_PWM1_SYNC default n endif @@ -1339,6 +1445,21 @@ config SAMV7_USART0_1WIREDRIVER bool "1-Wire driver" select SAMV7_1WIREDRIVER +config SAMV7_USART0_SPI_MASTER + bool "USART0 as SPI Master driver" + select SAMV7_USART_IS_SPI_MASTER + ---help--- + Switch USART0 to SPI master (host) mode. In this mode USART is used + to emulate SPI peripheral. Pin configuration is following: + + TXD - MOSI + RXD - MISO + SCK - SCK + RTS - NSS (chip select) + + There is only one chip select therefore SPI master can be used to + communicate only with one slave device. + endchoice # "USART0 Driver Configuration" if SAMV7_USART0_SERIALDRIVER @@ -1376,6 +1497,21 @@ config SAMV7_USART1_1WIREDRIVER bool "1-Wire driver" select SAMV7_1WIREDRIVER +config SAMV7_USART1_SPI_MASTER + bool "USART1 as SPI Master driver" + select SAMV7_USART_IS_SPI_MASTER + ---help--- + Switch USART1 to SPI master (host) mode. In this mode USART is used + to emulate SPI peripheral. Pin configuration is following: + + TXD - MOSI + RXD - MISO + SCK - SCK + RTS - NSS (chip select) + + There is only one chip select therefore SPI master can be used to + communicate only with one slave device. + endchoice # "USART1 Driver Configuration" if SAMV7_USART1_SERIALDRIVER @@ -1413,6 +1549,21 @@ config SAMV7_USART2_1WIREDRIVER bool "1-Wire driver" select SAMV7_1WIREDRIVER +config SAMV7_USART2_SPI_MASTER + bool "USART2 as SPI Master driver" + select SAMV7_USART_IS_SPI_MASTER + ---help--- + Switch USART2 to SPI master (host) mode. In this mode USART is used + to emulate SPI peripheral. Pin configuration is following: + + TXD - MOSI + RXD - MISO + SCK - SCK + RTS - NSS (chip select) + + There is only one chip select therefore SPI master can be used to + communicate only with one slave device. + endchoice # "USART2 Driver Configuration" if SAMV7_USART2_SERIALDRIVER @@ -1639,6 +1790,7 @@ menuconfig SAMV7_PROGMEM bool "FLASH program memory" default n select ARCH_HAVE_PROGMEM + select SAMV7_EEFC ---help--- Enable support FLASH interfaces as defined in include/nuttx/progmem.h @@ -1657,6 +1809,16 @@ config SAMV7_PROGMEM_NSECTORS endif # SAMV7_PROGMEM +config SAMV7_USER_SIGNATURE + bool "FLASH user signature" + default n + select SAMV7_EEFC + ---help--- + Each SAMv7 product contains a user signature area of 512 bytes in + embedded flash. It is possible to read, write and erase this area. + Data stored in this area are not erased by asserting ERASE pin or by + software ERASE command. + menu "SDRAM Configuration" depends on SAMV7_SDRAMC @@ -1824,7 +1986,7 @@ config SAMV7_SPI_REGDEBUG endmenu # SPI device driver options menu "QSPI Device Driver Configuration" - depends on SAMV7_QSPI && !SAMV7_QSPI_IS_SPI + depends on SAMV7_QSPI && !SAMV7_QSPI_SPI_MODE config SAMV7_QSPI_DLYBS int "Delay Before QSCK (nsec)" @@ -3705,6 +3867,7 @@ config SAMV7_TC0_QE bool "TC0" default n depends on SAMV7_TC0 + select SAMV7_QENCODER select SAMV7_TC0_TIOA0 select SAMV7_TC0_TIOB0 ---help--- @@ -3714,6 +3877,7 @@ config SAMV7_TC1_QE bool "TC1" default n depends on SAMV7_TC1 + select SAMV7_QENCODER select SAMV7_TC1_TIOA3 select SAMV7_TC1_TIOB3 ---help--- @@ -3723,6 +3887,7 @@ config SAMV7_TC2_QE bool "TC2" default n depends on SAMV7_TC2 + select SAMV7_QENCODER select SAMV7_TC2_TIOA6 select SAMV7_TC2_TIOB6 ---help--- @@ -3732,11 +3897,25 @@ config SAMV7_TC3_QE bool "TC3" default n depends on SAMV7_TC3 + select SAMV7_QENCODER select SAMV7_TC3_TIOA9 select SAMV7_TC3_TIOB9 ---help--- Reserve TC3 for use by QEncoder. +config SAMV7_QENCODER_ENABLE_GETINDEX + bool "Support ioctl GETINDEX call" + default n + ---help--- + Index signal does not reset the internal counter. + However, each time index is hit, capture A and B registers + are used to save the counter's value instead of + resetting it. + + This provides support for the GETINDEX ioctl call + with the qe_index_s struct. The 16 to 32 bit extension + of the driver's counter is also done. + config SAMV7_QENCODER_FILTER bool "Enable filtering on SAMV7 QEncoder input" default y diff --git a/arch/arm/src/samv7/Make.defs b/arch/arm/src/samv7/Make.defs index e0dfec248420d..8e3bf36514a3a 100644 --- a/arch/arm/src/samv7/Make.defs +++ b/arch/arm/src/samv7/Make.defs @@ -29,6 +29,7 @@ include armv7-m/Make.defs CHIP_CSRCS = sam_start.c sam_clockconfig.c sam_irq.c sam_allocateheap.c CHIP_CSRCS += sam_lowputc.c sam_serial.c sam_gpio.c sam_pck.c sam_uid.c +CHIP_CSRCS += sam_systemreset.c # Configuration-dependent SAMV7 files @@ -59,14 +60,14 @@ ifeq ($(CONFIG_SAMV7_RSWDT),y) CHIP_CSRCS += sam_rswdt.c endif -ifeq ($(CONFIG_SAMV7_SYSTEMRESET),y) -CHIP_CSRCS += sam_systemreset.c -endif - ifeq ($(CONFIG_SAMV7_1WIREDRIVER),y) CHIP_CSRCS += sam_1wire.c endif +ifeq ($(CONFIG_SAMV7_USART_IS_SPI_MASTER),y) +CHIP_CSRCS += sam_serial_spi.c +endif + ifeq ($(CONFIG_SAMV7_SPI_MASTER),y) CHIP_CSRCS += sam_spi.c endif @@ -107,7 +108,7 @@ endif ifeq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += sam_tickless.c endif -ifeq ($(CONFIG_SENSORS_QENCODER),y) +ifeq ($(CONFIG_SAMV7_QENCODER),y) CHIP_CSRCS += sam_qencoder.c endif endif @@ -136,8 +137,16 @@ ifeq ($(CONFIG_SAMV7_TRNG),y) CHIP_CSRCS += sam_trng.c endif +ifeq ($(CONFIG_SAMV7_EEFC),y) +CHIP_CSRCS += sam_eefc.c +endif + ifeq ($(CONFIG_SAMV7_PROGMEM),y) -CHIP_CSRCS += sam_progmem.c sam_eefc.c +CHIP_CSRCS += sam_progmem.c +endif + +ifeq ($(CONFIG_SAMV7_USER_SIGNATURE),y) +CHIP_CSRCS += sam_us.c endif ifeq ($(CONFIG_SAMV7_PWM),y) diff --git a/arch/arm/src/samv7/sam_1wire.c b/arch/arm/src/samv7/sam_1wire.c index 28a2c17ef2af7..19c8300033117 100644 --- a/arch/arm/src/samv7/sam_1wire.c +++ b/arch/arm/src/samv7/sam_1wire.c @@ -471,7 +471,7 @@ static int sam_init(struct sam_1wire_s *priv) up_enable_irq(priv->irq); } - return OK; + return ret; } /**************************************************************************** @@ -885,41 +885,49 @@ struct onewire_dev_s *sam_1wireinitialize(int port) { #ifdef CONFIG_SAMV7_UART0_1WIREDRIVER case 0: + sam_uart0_enableclk(); priv = &sam_1wire0_priv; break; #endif #ifdef CONFIG_SAMV7_UART1_1WIREDRIVER case 1: + sam_uart1_enableclk(); priv = &sam_1wire1_priv; break; #endif #ifdef CONFIG_SAMV7_UART2_1WIREDRIVER case 2: + sam_uart2_enableclk(); priv = &sam_1wire2_priv; break; #endif #ifdef CONFIG_SAMV7_UART3_1WIREDRIVER case 3: + sam_uart3_enableclk(); priv = &sam_1wire3_priv; break; #endif #ifdef CONFIG_SAMV7_UART4_1WIREDRIVER case 4: + sam_uart4_enableclk(); priv = &sam_1wire4_priv; break; #endif #ifdef CONFIG_SAMV7_USART0_1WIREDRIVER case 5: + sam_usart0_enableclk(); priv = &sam_1wire5_priv; break; #endif #ifdef CONFIG_SAMV7_USART1_1WIREDRIVER case 6: + sam_usart1_enableclk(); priv = &sam_1wire6_priv; break; #endif #ifdef CONFIG_SAMV7_USART2_1WIREDRIVER case 7: + sam_usart2_enableclk(); priv = &sam_1wire7_priv; break; #endif diff --git a/arch/arm/src/samv7/sam_config.h b/arch/arm/src/samv7/sam_config.h index eed358f026372..94bf3fa4ff368 100644 --- a/arch/arm/src/samv7/sam_config.h +++ b/arch/arm/src/samv7/sam_config.h @@ -97,28 +97,6 @@ /* USARTs *******************************************************************/ -/* If the USART is not being used as a UART or for SPI, then it really isn't - * enabled for our purposes. - */ - -#if !defined(CONFIG_USART0_SERIALDRIVER) && !defined(CONFIG_USART0_ISSPI) -# undef CONFIG_SAMV7_USART0 -# undef CONFIG_USART0_SERIAL_CONSOLE -# undef CONFIG_USART0_IFLOWCONTROL -#endif - -#if !defined(CONFIG_USART1_SERIALDRIVER) && !defined(CONFIG_USART1_ISSPI) -# undef CONFIG_SAMV7_USART1 -# undef CONFIG_USART1_SERIAL_CONSOLE -# undef CONFIG_USART1_IFLOWCONTROL -#endif - -#if !defined(CONFIG_USART2_SERIALDRIVER) && !defined(CONFIG_USART2_ISSPI) -# undef CONFIG_SAMV7_USART2 -# undef CONFIG_USART2_SERIAL_CONSOLE -# undef CONFIG_USART2_IFLOWCONTROL -#endif - /* Don't enable USARTs not supported by the chip. */ #if SAMV7_NUSART < 1 diff --git a/arch/arm/src/samv7/sam_dac.c b/arch/arm/src/samv7/sam_dac.c index 1601e27c226c2..1fb2d3330ad4a 100644 --- a/arch/arm/src/samv7/sam_dac.c +++ b/arch/arm/src/samv7/sam_dac.c @@ -68,7 +68,7 @@ struct sam_dac_s { - uint8_t initialized : 1; /* True, the DAC block has been initialized */ + uint8_t users; /* Number of channels using peripheral */ #ifdef CONFIG_SAMV7_DAC_TRIGGER TC_HANDLE tc; /* Timer handle */ #endif @@ -78,7 +78,7 @@ struct sam_dac_s struct sam_chan_s { - uint8_t inuse : 1; /* True, the driver is in use and not available */ + bool inuse; /* True, the driver is in use and not available */ uint8_t intf; /* DAC zero-based interface number (0 or 1) */ uint32_t dro; /* Conversion Data Register */ #ifdef CONFIG_SAMV7_DAC_TRIGGER @@ -134,7 +134,7 @@ static struct sam_chan_s g_dac1priv = .intf = 0, .dro = SAM_DACC_CDR0, #ifdef CONFIG_SAMV7_DAC_TRIGGER - .reg_dacc_trigr_clear = DACC_TRIGR_TRGSEL0_MASK, + .reg_dacc_trigr_clear = DACC_TRIGR_TRGSEL0_MASK | DACC_TRIGR_TRGEN0_EN, .reg_dacc_trigr_set = DACC_TRIGR_TRGSEL0( CONFIG_SAMV7_DAC_TRIGGER_SELECT) | DACC_TRIGR_TRGEN0, @@ -154,7 +154,7 @@ static struct sam_chan_s g_dac2priv = .intf = 1, .dro = SAM_DACC_CDR1, #ifdef CONFIG_SAMV7_DAC_TRIGGER - .reg_dacc_trigr_clear = DACC_TRIGR_TRGSEL1_MASK, + .reg_dacc_trigr_clear = DACC_TRIGR_TRGSEL1_MASK | DACC_TRIGR_TRGEN1_EN, .reg_dacc_trigr_set = DACC_TRIGR_TRGSEL1( CONFIG_SAMV7_DAC_TRIGGER_SELECT) | DACC_TRIGR_TRGEN1, @@ -226,15 +226,46 @@ static int dac_interrupt(int irq, void *context, void *arg) static void dac_reset(struct dac_dev_s *dev) { + struct sam_chan_s *chan = dev->ad_priv; +#ifdef CONFIG_SAMV7_DAC_TRIGGER + uint32_t regval; +#endif irqstate_t flags; /* Reset only the selected DAC channel; the other DAC channel must remain - * functional. + * functional. The controller however does not have an option to reset + * single channel, therefore we have to do this manually by writing zeroes + * to all important registers. + */ + + /* This should be called only before dac_setup(), therefore the channel + * should not be in use. Skip reset if it is. */ - flags = enter_critical_section(); + if (chan->inuse) + { + /* Yes.. then return EBUSY */ + + return; + } + + flags = enter_critical_section(); + + /* Disable channel */ + + putreg32(1u << chan->intf, SAM_DACC_CHDR); + + /* Disable interrupts */ -#warning "Missing logic" + dac_txint(dev, false); + +#ifdef CONFIG_SAMV7_DAC_TRIGGER + /* Reset trigger mode */ + + regval = getreg32(SAM_DACC_TRIGR); + regval &= ~chan->reg_dacc_trigr_clear; + putreg32(regval, SAM_DACC_TRIGR); +#endif leave_critical_section(flags); } @@ -257,7 +288,40 @@ static void dac_reset(struct dac_dev_s *dev) static int dac_setup(struct dac_dev_s *dev) { -#warning "Missing logic" + struct sam_chan_s *chan = dev->ad_priv; + int ret; + + /* Initialize the DAC peripheral module */ + + ret = dac_module_init(); + if (ret < 0) + { + aerr("ERROR: Failed to initialize the DAC peripheral module: %d\n", + ret); + return ret; + } + + /* Add channel user. We can do this because the upper layer checks + * whether the device is opened for the first time and calls dac_setup + * only if this is true. Therefore there can not be a situation where + * the application would open DAC1 two times and dac_setup would be called + * two times. We however have to check number of users (DAC0 and DAC1) + * to know whether we want to disable the entire peripheral during + * shutdown. + */ + + g_dacmodule.users++; + + /* Configure the selected DAC channel */ + + ret = dac_channel_init(chan); + if (ret < 0) + { + aerr("ERROR: Failed to initialize DAC channel %d: %d\n", + chan->intf, ret); + return ret; + } + return OK; } @@ -277,7 +341,43 @@ static int dac_setup(struct dac_dev_s *dev) static void dac_shutdown(struct dac_dev_s *dev) { -#warning "Missing logic" + struct sam_chan_s *chan = dev->ad_priv; + + /* We can use dac_reset() to disable the channel. */ + + chan->inuse = false; + dac_reset(dev); + + /* Decrement number of peripheral users. */ + + g_dacmodule.users--; + + if (g_dacmodule.users == 0) + { + /* This means there are no more channels using the peripheral. We + * can disable entire peripheral and free timer. + */ + + /* Reset peripheral. This will simulate HW reset and clean all + * registers. + */ + + putreg32(DACC_CR_SWRST, SAM_DACC_CR); + + /* Disable interrupt */ + + up_disable_irq(SAM_IRQ_DACC); + + /* Detach interrupt */ + + irq_detach(SAM_IRQ_DACC); + +#ifdef CONFIG_SAMV7_DAC_TRIGGER + /* Free timer */ + + dac_timer_free(&g_dacmodule); +#endif + } } /**************************************************************************** @@ -327,7 +427,7 @@ static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg) /* Interrupt based transfer */ - putreg16(msg->am_data >> 16, chan->dro); + putreg32(msg->am_data & DACC_CDR_DATA0_MASK, chan->dro); return OK; } @@ -483,11 +583,11 @@ static int dac_channel_init(struct sam_chan_s *chan) /* Enable DAC Channel */ - putreg32(1 << chan->intf, SAM_DACC_CHER); + putreg32(1u << chan->intf, SAM_DACC_CHER); /* Mark the DAC channel "in-use" */ - chan->inuse = 1; + chan->inuse = true; return OK; } @@ -509,9 +609,9 @@ static int dac_module_init(void) uint32_t regval; int ret; - /* Has the DAC block already been initialized? */ + /* Has the DAC block already been users? */ - if (g_dacmodule.initialized) + if (g_dacmodule.users > 0) { /* Yes.. then return success We only have to do this once */ @@ -571,9 +671,6 @@ static int dac_module_init(void) ainfo("Enable the DAC interrupt: irq=%d\n", SAM_IRQ_DACC); up_enable_irq(SAM_IRQ_DACC); - /* Mark the DAC module as initialized */ - - g_dacmodule.initialized = 1; return OK; } @@ -598,8 +695,6 @@ static int dac_module_init(void) struct dac_dev_s *sam_dac_initialize(int intf) { struct dac_dev_s *dev; - struct sam_chan_s *chan; - int ret; #ifdef CONFIG_SAMV7_DAC0 if (intf == 0) @@ -622,26 +717,6 @@ struct dac_dev_s *sam_dac_initialize(int intf) return NULL; } - /* Initialize the DAC peripheral module */ - - ret = dac_module_init(); - if (ret < 0) - { - aerr("ERROR: Failed to initialize the DAC peripheral module: %d\n", - ret); - return NULL; - } - - /* Configure the selected DAC channel */ - - chan = dev->ad_priv; - ret = dac_channel_init(chan); - if (ret < 0) - { - aerr("ERROR: Failed to initialize DAC channel %d: %d\n", intf, ret); - return NULL; - } - return dev; } diff --git a/arch/arm/src/samv7/sam_gpio.c b/arch/arm/src/samv7/sam_gpio.c index b88b72eee2e6f..b7fd6940ba688 100644 --- a/arch/arm/src/samv7/sam_gpio.c +++ b/arch/arm/src/samv7/sam_gpio.c @@ -42,6 +42,11 @@ * Pre-processor Definitions ****************************************************************************/ +#if defined(CONFIG_SAMV7_JTAG_FULL_ENABLE) && defined(CONFIG_SAMV7_USART1) +# error CONFIG_SAMV7_JTAG_FULL_ENABLE is incompatible with CONFIG_SAMV7_USART1. +# error The SYSIO Pin4 must be bound to PB4 to use USART1 +#endif + #if !defined(CONFIG_SAMV7_ERASE_ENABLE) || \ !defined(CONFIG_SAMV7_JTAG_FULL_ENABLE) # if defined(CONFIG_SAMV7_ERASE_DISABLE) @@ -51,7 +56,7 @@ # endif # if defined(CONFIG_SAMV7_JTAG_DISABLE) # define SYSIO_BITS (MATRIX_CCFG_SYSIO_SYSIO4 | MATRIX_CCFG_SYSIO_SYSIO5 | \ - MATRIX_CCFG_SYSIO_SYSIO6 | MATRIX_CCFG_SYSIO_SYSIO7) + MATRIX_CCFG_SYSIO_SYSIO6 | MATRIX_CCFG_SYSIO_SYSIO7) # endif # if defined(CONFIG_SAMV7_JTAG_FULL_SW_ENABLE) # define SYSIO_BITS MATRIX_CCFG_SYSIO_SYSIO4 diff --git a/arch/arm/src/samv7/sam_lowputc.c b/arch/arm/src/samv7/sam_lowputc.c index 2fbfdf79f2b39..afbd732037036 100644 --- a/arch/arm/src/samv7/sam_lowputc.c +++ b/arch/arm/src/samv7/sam_lowputc.c @@ -27,13 +27,14 @@ #include #include +#include #include #include "arm_internal.h" #include "sam_config.h" #include "sam_gpio.h" #include "sam_periphclks.h" -#include "sam_lowputc.h" +#include "sam_start.h" #include "hardware/sam_uart.h" #include "hardware/sam_pinmap.h" @@ -183,18 +184,18 @@ void arm_lowputc(char ch) * atomic. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if ((getreg32(SAM_CONSOLE_BASE + SAM_UART_SR_OFFSET) & UART_INT_TXEMPTY) != 0) { /* Send the character */ putreg32((uint32_t)ch, SAM_CONSOLE_BASE + SAM_UART_THR_OFFSET); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); return; } - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } #endif } @@ -240,67 +241,64 @@ void sam_lowsetup(void) uint64_t divb3; uint32_t intpart; uint32_t fracpart; -#endif -#if (defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)) || \ - defined(CONFIG_SAMV7_USART1) uint32_t regval; #endif /* Enable clocking for all selected UART/USARTs */ -#ifdef CONFIG_SAMV7_UART0 +#ifdef CONFIG_UART0_SERIALDRIVER sam_uart0_enableclk(); #endif -#ifdef CONFIG_SAMV7_UART1 +#ifdef CONFIG_UART1_SERIALDRIVER sam_uart1_enableclk(); #endif -#ifdef CONFIG_SAMV7_UART2 +#ifdef CONFIG_UART2_SERIALDRIVER sam_uart2_enableclk(); #endif -#ifdef CONFIG_SAMV7_UART3 +#ifdef CONFIG_UART3_SERIALDRIVER sam_uart3_enableclk(); #endif -#ifdef CONFIG_SAMV7_UART4 +#ifdef CONFIG_UART4_SERIALDRIVER sam_uart4_enableclk(); #endif -#ifdef CONFIG_SAMV7_USART0 +#ifdef CONFIG_USART0_SERIALDRIVER sam_usart0_enableclk(); #endif -#ifdef CONFIG_SAMV7_USART1 +#ifdef CONFIG_USART1_SERIALDRIVER sam_usart1_enableclk(); #endif -#ifdef CONFIG_SAMV7_USART2 +#ifdef CONFIG_USART2_SERIALDRIVER sam_usart2_enableclk(); #endif /* Configure UART pins for all selected UART/USARTs */ -#ifdef CONFIG_SAMV7_UART0 +#ifdef CONFIG_UART0_SERIALDRIVER sam_configgpio(GPIO_UART0_RXD); sam_configgpio(GPIO_UART0_TXD); #endif -#ifdef CONFIG_SAMV7_UART1 +#ifdef CONFIG_UART1_SERIALDRIVER sam_configgpio(GPIO_UART1_RXD); sam_configgpio(GPIO_UART1_TXD); #endif -#ifdef CONFIG_SAMV7_UART2 +#ifdef CONFIG_UART2_SERIALDRIVER sam_configgpio(GPIO_UART2_RXD); sam_configgpio(GPIO_UART2_TXD); #endif -#ifdef CONFIG_SAMV7_UART3 +#ifdef CONFIG_UART3_SERIALDRIVER sam_configgpio(GPIO_UART3_RXD); sam_configgpio(GPIO_UART3_TXD); #endif -#ifdef CONFIG_SAMV7_UART4 +#ifdef CONFIG_UART4_SERIALDRIVER sam_configgpio(GPIO_UART4_RXD); sam_configgpio(GPIO_UART4_TXD); #endif -#ifdef CONFIG_SAMV7_USART0 +#ifdef CONFIG_USART0_SERIALDRIVER sam_configgpio(GPIO_USART0_RXD); sam_configgpio(GPIO_USART0_TXD); #ifdef CONFIG_USART0_OFLOWCONTROL @@ -311,7 +309,7 @@ void sam_lowsetup(void) #endif #endif -#ifdef CONFIG_SAMV7_USART1 +#ifdef CONFIG_USART1_SERIALDRIVER sam_configgpio(GPIO_USART1_RXD); sam_configgpio(GPIO_USART1_TXD); # ifdef CONFIG_USART1_OFLOWCONTROL @@ -321,22 +319,9 @@ void sam_lowsetup(void) sam_configgpio(GPIO_USART1_RTS); # endif - /* To use the USART1 as an USART, the SYSIO Pin4 must be bound to PB4 - * instead of TDI - */ - -# if defined(CONFIG_SAMV7_JTAG_FULL_ENABLE) -# warning CONFIG_SAMV7_JTAG_FULL_ENABLE is incompatible with CONFIG_SAMV7_USART1. -# warning The SYSIO Pin4 must be bound to PB4 to use USART1 -# endif - - regval = getreg32(SAM_MATRIX_CCFG_SYSIO); - regval |= MATRIX_CCFG_SYSIO_SYSIO4; - putreg32(regval, SAM_MATRIX_CCFG_SYSIO); - #endif -#ifdef CONFIG_SAMV7_USART2 +#ifdef CONFIG_USART2_SERIALDRIVER sam_configgpio(GPIO_USART2_RXD); sam_configgpio(GPIO_USART2_TXD); #ifdef CONFIG_USART2_OFLOWCONTROL diff --git a/arch/arm/src/samv7/sam_lowputc.h b/arch/arm/src/samv7/sam_lowputc.h deleted file mode 100644 index 0849fbe67f13b..0000000000000 --- a/arch/arm/src/samv7/sam_lowputc.h +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * arch/arm/src/samv7/sam_lowputc.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM_SRC_SAMV7_SAM_LOWPUTC_H -#define __ARCH_ARM_SRC_SAMV7_SAM_LOWPUTC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include -#include - -#include "arm_internal.h" -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: sam_lowsetup - * - * Description: - * Called at the very beginning of _start. - * Performs low level initialization including setup of the console UART. - * This UART done early so that the serial console is available for - * debugging very early in the boot sequence. - * - ****************************************************************************/ - -void sam_lowsetup(void); - -/**************************************************************************** - * Name: sam_boardinitialize - * - * Description: - * All SAMV7 architectures must provide the following entry point. This - * entry point is called early in the initialization -- after all memory - * has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void sam_boardinitialize(void); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM_SRC_SAMV7_SAM_LOWPUTC_H */ diff --git a/arch/arm/src/samv7/sam_pwm.c b/arch/arm/src/samv7/sam_pwm.c index f61492c21a6b8..e743a83e2a9a8 100644 --- a/arch/arm/src/samv7/sam_pwm.c +++ b/arch/arm/src/samv7/sam_pwm.c @@ -65,6 +65,13 @@ #define PWM_RES 65535 #define COMP_UNITS_NUM 8 +/* Sync offset flags defines */ + +#define CH0_SYNC_FLAG (1 << 0) +#define CH1_SYNC_FLAG (1 << 1) +#define CH2_SYNC_FLAG (1 << 2) +#define CH3_SYNC_FLAG (1 << 3) + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -104,6 +111,7 @@ struct sam_pwm_s const struct sam_pwm_fault_s *fault; uint8_t channels_num; /* Number of channels */ uintptr_t base; /* Base address of peripheral register */ + uint8_t sync; /* Flags of synchronized channels */ }; /* PWM driver methods */ @@ -136,44 +144,64 @@ static struct sam_pwm_channel_s g_pwm0_channels[] = #ifdef CONFIG_SAMV7_PWM0_CH0 { .channel = 0, +#ifdef CONFIG_SAMV7_PWM0_CH0_LONLY + .pin_h = 0, + .pin_l = GPIO_PWMC0_L0, +#else .pin_h = GPIO_PWMC0_H0, #ifdef CONFIG_SAMV7_PWM0_CH0_COMP .pin_l = GPIO_PWMC0_L0, #else .pin_l = 0, +#endif #endif }, #endif #ifdef CONFIG_SAMV7_PWM0_CH1 { .channel = 1, +#ifdef CONFIG_SAMV7_PWM0_CH1_LONLY + .pin_h = 0, + .pin_l = GPIO_PWMC0_L1, +#else .pin_h = GPIO_PWMC0_H1, #ifdef CONFIG_SAMV7_PWM0_CH1_COMP .pin_l = GPIO_PWMC0_L1, #else .pin_l = 0, +#endif #endif }, #endif #ifdef CONFIG_SAMV7_PWM0_CH2 { .channel = 2, +#ifdef CONFIG_SAMV7_PWM0_CH2_LONLY + .pin_h = 0, + .pin_l = GPIO_PWMC0_L2, +#else .pin_h = GPIO_PWMC0_H2, #ifdef CONFIG_SAMV7_PWM0_CH2_COMP .pin_l = GPIO_PWMC0_L2, #else .pin_l = 0, +#endif #endif }, #endif #ifdef CONFIG_SAMV7_PWM0_CH3 { .channel = 3, +#ifdef CONFIG_SAMV7_PWM0_CH3_LONLY + .pin_h = 0, + .pin_l = GPIO_PWMC0_L3, +#else .pin_h = GPIO_PWMC0_H3, #ifdef CONFIG_SAMV7_PWM0_CH3_COMP .pin_l = GPIO_PWMC0_L3, #else .pin_l = 0, +#endif #endif }, #endif @@ -209,6 +237,38 @@ static struct sam_pwm_fault_s g_pwm0_fault = .gpio_2 = GPIO_PWMC0_FI2, }; +/* Define sync flags */ + +#ifdef CONFIG_SAMV7_PWM0_SYNC + #define PWM0_CH0_SYNC_FLAG CH0_SYNC_FLAG + + #ifdef CONFIG_SAMV7_PWM0_CH1_SYNC + #define PWM0_CH1_SYNC_FLAG CH1_SYNC_FLAG + #else + #define PWM0_CH1_SYNC_FLAG 0 + #endif + + #ifdef CONFIG_SAMV7_PWM0_CH2_SYNC + #define PWM0_CH2_SYNC_FLAG CH2_SYNC_FLAG + #else + #define PWM0_CH2_SYNC_FLAG 0 + #endif + + #ifdef CONFIG_SAMV7_PWM0_CH3_SYNC + #define PWM0_CH3_SYNC_FLAG CH3_SYNC_FLAG + #else + #define PWM0_CH3_SYNC_FLAG 0 + #endif +#else + #define PWM0_CH0_SYNC_FLAG 0 + #define PWM0_CH1_SYNC_FLAG 0 + #define PWM0_CH2_SYNC_FLAG 0 + #define PWM0_CH3_SYNC_FLAG 0 +#endif + +#define PWM0_SYNC_FLAGS (PWM0_CH0_SYNC_FLAG | PWM0_CH1_SYNC_FLAG | \ + PWM0_CH2_SYNC_FLAG | PWM0_CH3_SYNC_FLAG) + static struct sam_pwm_s g_pwm0 = { .ops = &g_pwmops, @@ -217,6 +277,7 @@ static struct sam_pwm_s g_pwm0 = .fault = &g_pwm0_fault, .channels_num = PWM0_NCHANNELS, .base = SAM_PWM0_BASE, + .sync = PWM0_SYNC_FLAGS, }; #endif /* CONFIG_SAMV7_PWM0 */ @@ -227,44 +288,64 @@ static struct sam_pwm_channel_s g_pwm1_channels[] = #ifdef CONFIG_SAMV7_PWM1_CH0 { .channel = 0, +#ifdef CONFIG_SAMV7_PWM1_CH0_LONLY + .pin_h = 0, + .pin_l = GPIO_PWMC1_L0, +#else .pin_h = GPIO_PWMC1_H0, #ifdef CONFIG_SAMV7_PWM1_CH0_COMP .pin_l = GPIO_PWMC1_L0, #else .pin_l = 0, +#endif #endif }, #endif #ifdef CONFIG_SAMV7_PWM1_CH1 { .channel = 1, +#ifdef CONFIG_SAMV7_PWM1_CH1_LONLY + .pin_h = 0, + .pin_l = GPIO_PWMC1_L1, +#else .pin_h = GPIO_PWMC1_H1, #ifdef CONFIG_SAMV7_PWM1_CH1_COMP .pin_l = GPIO_PWMC1_L1, #else .pin_l = 0, +#endif #endif }, #endif #ifdef CONFIG_SAMV7_PWM1_CH2 { .channel = 2, +#ifdef CONFIG_SAMV7_PWM1_CH2_LONLY + .pin_h = 0, + .pin_l = GPIO_PWMC1_L2, +#else .pin_h = GPIO_PWMC1_H2, #ifdef CONFIG_SAMV7_PWM1_CH2_COMP .pin_l = GPIO_PWMC1_L2, #else .pin_l = 0, +#endif #endif }, #endif #ifdef CONFIG_SAMV7_PWM1_CH3 { .channel = 3, +#ifdef CONFIG_SAMV7_PWM1_CH3_LONLY + .pin_h = 0, + .pin_l = GPIO_PWMC1_L3, +#else .pin_h = GPIO_PWMC1_H3, #ifdef CONFIG_SAMV7_PWM1_CH3_COMP .pin_l = GPIO_PWMC1_L3, #else .pin_l = 0, +#endif #endif }, #endif @@ -300,6 +381,38 @@ static struct sam_pwm_fault_s g_pwm1_fault = .gpio_2 = GPIO_PWMC1_FI2, }; +/* Define sync flags */ + +#ifdef CONFIG_SAMV7_PWM1_SYNC + #define PWM1_CH0_SYNC_FLAG CH0_SYNC_FLAG + + #ifdef CONFIG_SAMV7_PWM1_CH1_SYNC + #define PWM1_CH1_SYNC_FLAG CH1_SYNC_FLAG + #else + #define PWM1_CH1_SYNC_FLAG 0 + #endif + + #ifdef CONFIG_SAMV7_PWM1_CH2_SYNC + #define PWM1_CH2_SYNC_FLAG CH2_SYNC_FLAG + #else + #define PWM1_CH2_SYNC_FLAG 0 + #endif + + #ifdef CONFIG_SAMV7_PWM1_CH3_SYNC + #define PWM1_CH3_SYNC_FLAG CH3_SYNC_FLAG + #else + #define PWM1_CH3_SYNC_FLAG 0 + #endif +#else + #define PWM1_CH0_SYNC_FLAG 0 + #define PWM1_CH1_SYNC_FLAG 0 + #define PWM1_CH2_SYNC_FLAG 0 + #define PWM1_CH3_SYNC_FLAG 0 +#endif + +#define PWM1_SYNC_FLAGS (PWM1_CH0_SYNC_FLAG | PWM1_CH1_SYNC_FLAG | \ + PWM1_CH2_SYNC_FLAG | PWM1_CH3_SYNC_FLAG) + static struct sam_pwm_s g_pwm1 = { .ops = &g_pwmops, @@ -308,6 +421,7 @@ static struct sam_pwm_s g_pwm1 = .fault = &g_pwm1_fault, .channels_num = PWM1_NCHANNELS, .base = SAM_PWM1_BASE, + .sync = PWM1_SYNC_FLAGS, }; #endif @@ -332,7 +446,7 @@ static void pwm_set_deadtime(struct pwm_lowerhalf_s *dev, uint8_t channel, ub16_t duty); #endif static void pwm_set_polarity(struct pwm_lowerhalf_s *dev, uint8_t channel, - uint8_t cpol); + uint8_t cpol, uint8_t dcpol); /**************************************************************************** * Private Functions @@ -456,10 +570,14 @@ static void pwm_set_output(struct pwm_lowerhalf_s *dev, uint8_t channel, width); } - /* Enable the channel */ - regval = CHID_SEL(1 << channel); - pwm_putreg(priv, SAMV7_PWM_ENA, regval); + + /* The enabling of a channel should be only done on unsynced channels */ + + if (!(priv->sync & regval)) + { + pwm_putreg(priv, SAMV7_PWM_ENA, regval); + } } /**************************************************************************** @@ -594,14 +712,14 @@ static void pwm_set_deadtime(struct pwm_lowerhalf_s *dev, uint8_t channel, if (width_1 > (period - regval)) { - pwmerr("ERROR: Dead Time value DTH has to be < period - duty! " \ + pwmerr("ERROR: Dead Time value DTH has to be < period - duty! " "Setting DTH to 0\n"); width_1 = 0; } if (width_2 > regval) { - pwmerr("ERROR: Dead Time value DTL has to be < duty! " \ + pwmerr("ERROR: Dead Time value DTL has to be < duty! " "Setting DTL to 0\n"); width_2 = 0; } @@ -631,6 +749,7 @@ static void pwm_set_deadtime(struct pwm_lowerhalf_s *dev, uint8_t channel, * dev - A reference to the lower half PWM driver state structure * channel - Channel to by updated * cpol - Desired polarity + * dcpol - Desired default polarity of a disabled channel * * Returned Value: * None @@ -638,18 +757,33 @@ static void pwm_set_deadtime(struct pwm_lowerhalf_s *dev, uint8_t channel, ****************************************************************************/ static void pwm_set_polarity(struct pwm_lowerhalf_s *dev, uint8_t channel, - uint8_t cpol) + uint8_t cpol, uint8_t dcpol) { struct sam_pwm_s *priv = (struct sam_pwm_s *)dev; uint16_t regval; + /* Can't change polarity, if the channel is enabled! */ + + if (pwm_getreg(priv, SAMV7_PWM_SR) & CHID_SEL(1 << channel)) + { + return; + } + regval = pwm_getreg(priv, SAMV7_PWM_CMRX + (channel * CHANNEL_OFFSET)); regval &= ~CMR_CPOL; + regval &= ~CMR_DPOLI; + if (cpol == PWM_CPOL_HIGH) { regval |= CMR_CPOL; } + if ((dcpol == PWM_DCPOL_LOW && cpol == PWM_CPOL_HIGH) || + (dcpol == PWM_DCPOL_HIGH && cpol == PWM_CPOL_LOW)) + { + regval |= CMR_DPOLI; + } + pwm_putreg(priv, SAMV7_PWM_CMRX + (channel * CHANNEL_OFFSET), regval); } @@ -761,6 +895,14 @@ static int pwm_setup(struct pwm_lowerhalf_s *dev) pwm_putreg(priv, SAMV7_PWM_FPV1, 0); pwm_putreg(priv, SAMV7_PWM_FPV2, 0); + /* Enable synchronous channels. The flags in priv->sync + * correspond to the lowest bits in PWM_SCM. + * UPDM[1:0] is set to zero (manual update of deadtime, duty). + */ + + regval = (uint32_t)priv->sync; + pwm_putreg(priv, SAMV7_PWM_SCM, regval); + return OK; } @@ -815,9 +957,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, const struct pwm_info_s *info) { struct sam_pwm_s *priv = (struct sam_pwm_s *)dev; -#ifdef CONFIG_PWM_OVERWRITE uint32_t regval; -#endif #ifdef CONFIG_PWM_MULTICHAN for (int i = 0; i < PWM_NCHANNELS; i++) @@ -846,7 +986,8 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, info->channels[i].duty); #endif pwm_set_polarity(dev, priv->channels[index - 1].channel, - info->channels[i].cpol); + info->channels[i].cpol, + info->channels[i].dcpol); pwm_set_output(dev, priv->channels[index - 1].channel, info->channels[i].duty); #ifdef CONFIG_PWM_OVERWRITE @@ -870,6 +1011,25 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, #endif } } + + /* Perform the update of synchronized PWM channels */ + + if (priv->sync) + { + regval = SCUC_UPDULOCK; + + /* Enable the Channel 0 if synchronous channels are used. + * Channel 0's counter is used by all synchronous channels and + * enabling CH0 results in enabling all synchronous channels. + * + * Enable the CH0 here after all setting all channel parameters, + * because setting polarity configurations requires disabled + * channels. + */ + + pwm_putreg(priv, SAMV7_PWM_ENA, CHID_SEL(1)); + pwm_putreg(priv, SAMV7_PWM_SCUC, regval); + } #else /* Set the frequency and enable PWM output just for first channel */ @@ -879,7 +1039,7 @@ static int pwm_start(struct pwm_lowerhalf_s *dev, info->dead_time_a, info->dead_time_b); #endif pwm_set_polarity(dev, priv->channels[0].channel, - info->cpol); + info->cpol, info->dcpol); pwm_set_output(dev, priv->channels[0].channel, info->duty); #endif @@ -919,6 +1079,12 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) pwm_putreg(priv, SAMV7_PWM_DIS, regval); } + /* Just to be sure, disable all sync channels too */ + + regval = pwm_getreg(priv, SAMV7_PWM_SCM); + regval &= ~(CHID_SEL(1 << 0) | CHID_SEL(1 << 1) | + CHID_SEL(1 << 2) | CHID_SEL(1 << 3)); + pwm_putreg(priv, SAMV7_PWM_SCM, regval); #else regval = CHID_SEL(1 << priv->channels[0].channel); pwm_putreg(priv, SAMV7_PWM_DIS, regval); diff --git a/arch/arm/src/samv7/sam_qencoder.c b/arch/arm/src/samv7/sam_qencoder.c index ba28a7306606e..351a52f595321 100644 --- a/arch/arm/src/samv7/sam_qencoder.c +++ b/arch/arm/src/samv7/sam_qencoder.c @@ -41,7 +41,7 @@ #include "sam_tc.h" #include "sam_qencoder.h" -#ifdef CONFIG_SENSORS_QENCODER +#if defined(CONFIG_SENSORS_QENCODER) && defined(CONFIG_SAMV7_QENCODER) /**************************************************************************** * Pre-processor Definitions @@ -67,6 +67,19 @@ struct sam_lowerhalf_s TC_HANDLE tch; /* Handle returned by sam_tc_initialize() */ bool inuse; /* True: The lower-half driver is in-use */ + +#ifdef CONFIG_SAMV7_QENCODER_ENABLE_GETINDEX + /* qe_index_s IOCTL support: + * All variables are of an unsigned type, while the variables in the + * struct qe_index_s are of a signed type. The reason for using unsigned + * types is that the operations on unsigned types when extending is + * defined (overflow arithmetics). + */ + + uint32_t last_pos; /* The actual position */ + uint32_t last_index; /* The actual position of the last index */ + uint32_t index_cnt; /* The number of index hits */ +#endif }; /**************************************************************************** @@ -85,6 +98,14 @@ static int sam_position(struct qe_lowerhalf_s *lower, int32_t *pos); static int sam_reset(struct qe_lowerhalf_s *lower); static int sam_ioctl(struct qe_lowerhalf_s *lower, int cmd, unsigned long arg); +#ifdef CONFIG_SAMV7_QENCODER_ENABLE_GETINDEX +static int sam_qeindex(struct qe_lowerhalf_s *lower, + struct qe_index_s *dest); +static inline int32_t sam_qe_pos_16to32b(struct qe_lowerhalf_s *lower, + uint32_t current_pos); +static inline int32_t sam_qe_indx_pos_16to32b(struct qe_lowerhalf_s *lower, + uint32_t current_indx_pos); +#endif /**************************************************************************** * Private Data @@ -229,10 +250,15 @@ static int sam_shutdown(struct qe_lowerhalf_s *lower) static int sam_position(struct qe_lowerhalf_s *lower, int32_t *pos) { struct sam_lowerhalf_s *priv = (struct sam_lowerhalf_s *)lower; + uint32_t new_pos; + new_pos = sam_tc_getcounter(priv->tch); /* Return the counter value */ - - *pos = (int32_t)sam_tc_getcounter(priv->tch); +#ifdef CONFIG_SAMV7_QENCODER_ENABLE_GETINDEX + *pos = sam_qe_pos_16to32b(lower, new_pos); +#else + *pos = (int32_t)new_pos; +#endif return OK; } @@ -270,10 +296,139 @@ static int sam_reset(struct qe_lowerhalf_s *lower) static int sam_ioctl(struct qe_lowerhalf_s *lower, int cmd, unsigned long arg) { - /* No ioctl commands supported */ - +#ifdef CONFIG_SAMV7_QENCODER_ENABLE_GETINDEX + switch (cmd) + { + case QEIOC_GETINDEX: + { + /* Call the qeindex function */ + + sam_qeindex(lower, (struct qe_index_s *)arg); + return OK; + } + + default: + { + return -ENOTTY; + } + } +#else return -ENOTTY; +#endif +} + +#ifdef CONFIG_SAMV7_QENCODER_ENABLE_GETINDEX +/**************************************************************************** + * Name: sam_qe_pos_16to32b + * + * Description: + * An inline function performing the extension of current position. + * Last reading is saved to priv->last_pos. + * + ****************************************************************************/ + +static inline int32_t sam_qe_pos_16to32b(struct qe_lowerhalf_s *lower, + uint32_t current_pos) +{ + struct sam_lowerhalf_s *priv = (struct sam_lowerhalf_s *)lower; + + uint32_t new_pos = *(volatile uint32_t *)&priv->last_pos; + new_pos += (int16_t)(current_pos - new_pos); + *(volatile uint32_t *)&priv->last_pos = new_pos; + + return (int32_t)new_pos; +} +#endif + +#ifdef CONFIG_SAMV7_QENCODER_ENABLE_GETINDEX +/**************************************************************************** + * Name: sam_qe_indx_pos_16to32b + * + * Description: + * An inline function performing the extension of the last index position. + * Last reading is saved to priv->last_index. + * + ****************************************************************************/ + +static inline int32_t sam_qe_indx_pos_16to32b(struct qe_lowerhalf_s *lower, + uint32_t current_indx_pos) +{ + struct sam_lowerhalf_s *priv = (struct sam_lowerhalf_s *)lower; + + uint32_t new_index = *(volatile uint32_t *)&priv->last_pos; + new_index += (int16_t)(current_indx_pos - new_index); + *(volatile uint32_t *)&priv->last_index = new_index; + + return (int32_t)new_index; } +#endif + +#ifdef CONFIG_SAMV7_QENCODER_ENABLE_GETINDEX +/**************************************************************************** + * Name: sam_qeindex + * + * Description: + * A function used for a GETINDEX ioctl call. Works with the internal + * variables needed for the 32 bit extension. + * + ****************************************************************************/ + +static int sam_qeindex(struct qe_lowerhalf_s *lower, struct qe_index_s *dest) +{ + int32_t current_pos; + uint32_t status; + uint32_t current_indx_pos; + bool captured = false; + struct sam_lowerhalf_s *priv = (struct sam_lowerhalf_s *)lower; + + /* Perform the current position retrieval everytime */ + + sam_position(lower, ¤t_pos); + dest->qenc_pos = current_pos; + + /* Perform the capture logic */ + + TC_HANDLE handle = priv->tch; + + /* Get the interrupt */ + + status = sam_tc_getpending(handle); + + /* Check if something has been captured. + * The reason for using two capture registers is due to their exclusive + * access. So it requires reading switching. + */ + + if (status & TC_INT_LDRAS) + { + /* The new index pos is in the Capture A register */ + + current_indx_pos = sam_tc_getregister(handle, TC_REGA); + captured = true; + } + else if (status & TC_INT_LDRBS) + { + /* The new index pos is in the Capture B register */ + + current_indx_pos = sam_tc_getregister(handle, TC_REGB); + captured = true; + } + + /* We've caught something. Increase the index hit count + * and extend the reading. + */ + + if (captured) + { + priv->index_cnt++; + sam_qe_indx_pos_16to32b(lower, current_indx_pos); + } + + dest->indx_pos = priv->last_index; + dest->indx_cnt = priv->index_cnt; + return OK; +} +#endif /**************************************************************************** * Public Functions @@ -323,10 +478,30 @@ int sam_qeinitialize(const char *devpath, int tc) /* Allocate the timer/counter and select its mode of operation */ + /* When configuring the timer with no index reset, do not obey + * the datasheet's QDEC instructions. Do not set the TC_CMR_ABETRG and + * TC_CMR_ETRGEDG_RISING bits responsible for the counter reset, + * because triggers reset the internal counter. + * Instead, to get the position of the last index, use the ability + * to capture internal counter's value with an upcoming index. + * + * Due to the internal structure of the Timer/Counter, both Capture + * registers (A and B) must be used, because of the exclusive access + * to both Capture registers (refer to section 49-6 in the latest 2023 + * ATSAMV7's datasheet). + */ +#ifdef CONFIG_SAMV7_QENCODER_ENABLE_GETINDEX + mode = TC_CMR_TCCLKS_XC0 | /* Use XC0 as an external TCCLKS value */ + TC_CMR_CAPTURE | /* Select 'Capture mode' */ + TC_CMR_LDRA_RISING | /* Select 'Rising edge' for the RA loading */ + TC_CMR_LDRB_RISING | /* Select 'Rising edge' for the RB loading */ + TC_CMR_SBSMPLR_ONE; /* Capture every upcoming edge */ +#else mode = TC_CMR_TCCLKS_XC0 | /* Use XC0 as an external TCCLKS value */ TC_CMR_ETRGEDG_RISING | /* Select 'Rising edge' as the External Trigger Edge */ TC_CMR_ABETRG | /* Select 'TIOAx' as the External Trigger */ TC_CMR_CAPTURE; /* Select 'Capture mode' */ +#endif priv->tch = sam_tc_allocate(tc * SAM_TC_NCHANNELS, mode); if (priv->tch == NULL) @@ -366,4 +541,4 @@ int sam_qeinitialize(const char *devpath, int tc) return OK; } -#endif /* CONFIG_SENSORS_QENCODER */ +#endif /* CONFIG_SENSORS_QENCODER && CONFIG_SAMV7_QENCODER */ diff --git a/arch/arm/src/samv7/sam_qencoder.h b/arch/arm/src/samv7/sam_qencoder.h index 222465246007f..b084e1834af20 100644 --- a/arch/arm/src/samv7/sam_qencoder.h +++ b/arch/arm/src/samv7/sam_qencoder.h @@ -29,7 +29,7 @@ #include "chip.h" -#ifdef CONFIG_SENSORS_QENCODER +#if defined(CONFIG_SENSORS_QENCODER) && defined(CONFIG_SAMV7_QENCODER) /**************************************************************************** * Included Files @@ -77,5 +77,5 @@ int sam_qeinitialize(const char *devpath, int tc); -#endif /* CONFIG_SENSORS_QENCODER */ +#endif /* CONFIG_SENSORS_QENCODER && CONFIG_SAMV7_QENCODER */ #endif /* __ARCH_ARM_SRC_SAMV7_SAM_QENCODER_H */ diff --git a/arch/arm/src/samv7/sam_serial.c b/arch/arm/src/samv7/sam_serial.c index 24987e18c871e..48f6859b914ea 100644 --- a/arch/arm/src/samv7/sam_serial.c +++ b/arch/arm/src/samv7/sam_serial.c @@ -67,28 +67,44 @@ defined(CONFIG_USART2_RXDMA) # define SERIAL_HAVE_RXDMA #else -# undef SERIAL_HAVE_RXDMA +# undef SERIAL_HAVE_RXDMA #endif #if defined(CONFIG_UART0_RXDMA) || defined(CONFIG_UART1_RXDMA) || \ defined(CONFIG_UART2_RXDMA) || defined(CONFIG_UART3_RXDMA) || \ defined(CONFIG_UART4_RXDMA) -# warning RX DMA is currently supported only for USART driver. +# warning RX DMA is currently supported only for USART driver. #endif #if defined(SERIAL_HAVE_RXDMA) && !defined(CONFIG_SAMV7_XDMAC) -# error SERIAL DMA requires CONFIG_SAMV7_XDMAC to be selected +# error SERIAL DMA requires CONFIG_SAMV7_XDMAC to be selected #endif -#ifdef SERIAL_HAVE_CONSOLE_RXDMA -# error RX DMA for serial console is currently not supported. +#if defined(CONFIG_USART0_TXDMA) || defined(CONFIG_USART1_TXDMA) || \ + defined(CONFIG_USART2_TXDMA) +# define SERIAL_HAVE_TXDMA +#else +# undef SERIAL_HAVE_TXDMA #endif #if defined(CONFIG_UART0_TXDMA) || defined(CONFIG_UART1_TXDMA) || \ defined(CONFIG_UART2_TXDMA) || defined(CONFIG_UART3_TXDMA) || \ - defined(CONFIG_UART4_TXDMA) || defined(CONFIG_USART0_TXDMA) || \ - defined(CONFIG_USART1_TXDMA) || defined(CONFIG_USART2_TXDMA) -# warning TX DMA is currently not supported. + defined(CONFIG_UART4_TXDMA) +# warning TX DMA is currently supported only for USART driver. +#endif + +#if defined(SERIAL_HAVE_TXDMA) && !defined(CONFIG_SAMV7_XDMAC) +# error SERIAL DMA requires CONFIG_SAMV7_XDMAC to be selected +#endif + +#if defined(SERIAL_HAVE_TXDMA) && !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required (CONFIG_SCHED_WORKQUEUE) +#elif defined(SERIAL_HAVE_TXDMA) && !defined(CONFIG_SCHED_HPWORK) +# error Hi-priority work queue support is required (CONFIG_SCHED_HPWORK) +#endif + +#ifdef SERIAL_HAVE_CONSOLE_DMA +# error DMA for serial console is currently not supported. #endif #ifndef CONFIG_SAMV7_SERIAL_DMA_TIMEOUT @@ -124,6 +140,18 @@ #endif /* SERIAL_HAVE_RXDMA */ +#ifdef SERIAL_HAVE_TXDMA + +# define DMA_TXFLAGS (DMACH_FLAG_FIFOCFG_LARGEST | \ + DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH | \ + DMACH_FLAG_PERIPHWIDTH_8BITS | DMACH_FLAG_PERIPHCHUNKSIZE_1 | \ + DMACH_FLAG_MEMPID_MAX | DMACH_FLAG_MEMAHB_AHB_IF0 | \ + DMACH_FLAG_PERIPHAHB_AHB_IF1 | DMACH_FLAG_MEMWIDTH_8BITS | \ + DMACH_FLAG_MEMINCREMENT | DMACH_FLAG_MEMCHUNKSIZE_1 | \ + DMACH_FLAG_MEMBURST_1) + +#endif /* SERIAL_HAVE_TXDMA */ + /* Which UART/USART with be tty0/console and which tty1-7? */ /* First pick the console and ttys0. This could be any of UART0-4, @@ -417,6 +445,7 @@ struct sam_dev_s #endif bool has_rxdma; /* True if RX DMA is enabled */ + bool has_txdma; bool has_rs485; /* True if RS-485 mode is enabled */ #ifdef SERIAL_HAVE_RS485 @@ -434,6 +463,14 @@ struct sam_dev_s uint32_t rxdmanext; /* Next byte in the DMA buffer to be read */ uint32_t * const rxbuf[2]; /* Receive DMA buffer */ struct chnext_view1_s *desc[2]; +#endif + /* TX DMA state */ + +#ifdef SERIAL_HAVE_TXDMA + const unsigned int txdma_channel; /* DMA channel assigned */ + DMA_HANDLE txdma; /* currently-open receive DMA stream */ + struct work_s work; /* Supports txavailable worker */ + sem_t txdma_sem; #endif }; @@ -447,25 +484,37 @@ static int sam_attach(struct uart_dev_s *dev); static void sam_detach(struct uart_dev_s *dev); static int sam_interrupt(int irq, void *context, void *arg); static int sam_ioctl(struct file *filep, int cmd, unsigned long arg); -#ifdef SERIAL_HAVE_NODMA_OPS +#ifdef SERIAL_HAVE_NORXDMA_OPS static int sam_receive(struct uart_dev_s *dev, unsigned int *status); static void sam_rxint(struct uart_dev_s *dev, bool enable); static bool sam_rxavailable(struct uart_dev_s *dev); #endif static void sam_send(struct uart_dev_s *dev, int ch); +#ifdef SERIAL_HAVE_NOTXDMA_OPS static void sam_txint(struct uart_dev_s *dev, bool enable); static bool sam_txready(struct uart_dev_s *dev); static bool sam_txempty(struct uart_dev_s *dev); +#endif -#ifdef SERIAL_HAVE_RXDMA +#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA) static int sam_dma_setup(struct uart_dev_s *dev); static void sam_dma_shutdown(struct uart_dev_s *dev); +#endif + +#ifdef SERIAL_HAVE_RXDMA static int sam_dma_receive(struct uart_dev_s *dev, unsigned int *status); static void sam_dma_rxint(struct uart_dev_s *dev, bool enable); static bool sam_dma_rxavailable(struct uart_dev_s *dev); static void sam_dma_rxcallback(DMA_HANDLE handle, void *arg, int status); #endif +#ifdef SERIAL_HAVE_TXDMA +static void sam_dma_send(struct uart_dev_s *dev); +static void sam_dma_txint(struct uart_dev_s *dev, bool enable); +static void sam_dma_txavailable(struct uart_dev_s *dev); +static void sam_dma_txcallback(DMA_HANDLE handle, void *arg, int status); +#endif + /**************************************************************************** * Private Data ****************************************************************************/ @@ -516,6 +565,54 @@ static const struct uart_ops_s g_uart_rxdma_ops = }; #endif +/* TX DMA is defined */ + +#ifdef SERIAL_HAVE_TXDMA_OPS +static const struct uart_ops_s g_uart_txdma_ops = +{ + .setup = sam_dma_setup, + .shutdown = sam_dma_shutdown, + .attach = sam_attach, + .detach = sam_detach, + .ioctl = sam_ioctl, + .receive = sam_receive, + .rxint = sam_rxint, + .rxavailable = sam_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = sam_send, + .txint = sam_dma_txint, + .txready = sam_txready, + .txempty = sam_txready, + .dmatxavail = sam_dma_txavailable, + .dmasend = sam_dma_send, +}; +#endif + +#ifdef SERIAL_HAVE_RXTXDMA_OPS +static const struct uart_ops_s g_uart_rxtxdma_ops = +{ + .setup = sam_dma_setup, + .shutdown = sam_dma_shutdown, + .attach = sam_attach, + .detach = sam_detach, + .ioctl = sam_ioctl, + .receive = sam_dma_receive, + .rxint = sam_dma_rxint, + .rxavailable = sam_dma_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = sam_send, + .txint = sam_dma_txint, + .txready = sam_txready, + .txempty = sam_txready, + .dmatxavail = sam_dma_txavailable, + .dmasend = sam_dma_send, +}; +#endif + /* I/O buffers */ #if defined(CONFIG_SAMV7_UART0) && defined(CONFIG_UART0_SERIALDRIVER) @@ -749,6 +846,9 @@ static struct sam_dev_s g_usart0priv = }, .has_rxdma = true, # endif +# ifdef CONFIG_USART0_TXDMA + .has_txdma = true, +# endif # ifdef CONFIG_SAMV7_USART0_RS485MODE .has_rs485 = true, .rs485_dir_gpio = GPIO_USART0_RTS, @@ -767,8 +867,12 @@ static uart_dev_t g_usart0port = .size = CONFIG_USART0_TXBUFSIZE, .buffer = g_usart0txbuffer, }, -# ifdef CONFIG_USART0_RXDMA +# if defined(CONFIG_USART0_RXDMA) && defined(CONFIG_USART0_TXDMA) + .ops = &g_uart_rxtxdma_ops, +# elif defined(CONFIG_USART0_RXDMA) && !defined(CONFIG_USART0_TXDMA) .ops = &g_uart_rxdma_ops, +# elif !defined(CONFIG_USART0_RXDMA) && defined(CONFIG_USART0_TXDMA) + .ops = &g_uart_txdma_ops, # else .ops = &g_uart_ops, # endif @@ -804,6 +908,9 @@ static struct sam_dev_s g_usart1priv = }, .has_rxdma = true, # endif +# ifdef CONFIG_USART1_TXDMA + .has_txdma = true, +# endif # ifdef CONFIG_SAMV7_USART1_RS485MODE .has_rs485 = true, .rs485_dir_gpio = GPIO_USART1_RTS, @@ -822,8 +929,12 @@ static uart_dev_t g_usart1port = .size = CONFIG_USART1_TXBUFSIZE, .buffer = g_usart1txbuffer, }, -# ifdef CONFIG_USART1_RXDMA +# if defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA) + .ops = &g_uart_rxtxdma_ops, +# elif defined(CONFIG_USART1_RXDMA) && !defined(CONFIG_USART1_TXDMA) .ops = &g_uart_rxdma_ops, +# elif !defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_TXDMA) + .ops = &g_uart_txdma_ops, # else .ops = &g_uart_ops, # endif @@ -859,6 +970,9 @@ static struct sam_dev_s g_usart2priv = }, .has_rxdma = true, # endif +# ifdef CONFIG_USART2_TXDMA + .has_txdma = true, +# endif # ifdef CONFIG_SAMV7_USART2_RS485MODE .has_rs485 = true, .rs485_dir_gpio = GPIO_USART2_RTS, @@ -877,8 +991,12 @@ static uart_dev_t g_usart2port = .size = CONFIG_USART2_TXBUFSIZE, .buffer = g_usart2txbuffer, }, -# ifdef CONFIG_USART2_RXDMA +# if defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA) + .ops = &g_uart_rxtxdma_ops, +# elif defined(CONFIG_USART2_RXDMA) && !defined(CONFIG_USART2_TXDMA) .ops = &g_uart_rxdma_ops, +# elif !defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_TXDMA) + .ops = &g_uart_txdma_ops, # else .ops = &g_uart_ops, # endif @@ -1187,7 +1305,7 @@ static int sam_setup(struct uart_dev_s *dev) * ****************************************************************************/ -#ifdef SERIAL_HAVE_RXDMA +#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA) static int sam_dma_setup(struct uart_dev_s *dev) { struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; @@ -1209,12 +1327,7 @@ static int sam_dma_setup(struct uart_dev_s *dev) if (priv->has_rxdma) { - /* Do this only if this peripheral has RX DMA. This might not be - * neccessary at current state of the driver as sam_dma_setup() - * cannot be called if USARTn does not have RX DMA but it will be - * needed when TX DMA is implemented. The sam_dma_setup() can be - * called even when TX DMA is defined and RX DMA is not. - */ + /* Do this only if this peripheral has RX DMA enabled. */ priv->rxdma = sam_dmachannel(0, DMA_RXFLAGS | DMACH_FLAG_PERIPHPID(priv->pid)); @@ -1263,6 +1376,18 @@ static int sam_dma_setup(struct uart_dev_s *dev) sam_serialout(priv, SAM_UART_IER_OFFSET, UART_INT_TIMEOUT); } +#endif + +#ifdef SERIAL_HAVE_TXDMA + if (priv->has_txdma) + { + /* Do this only if this peripheral has TX DMA enabled. */ + + priv->txdma = sam_dmachannel(0, DMA_TXFLAGS | \ + DMACH_FLAG_PERIPHPID(priv->pid)); + sem_init(&priv->txdma_sem, 0, 1); + } + #endif return OK; @@ -1318,7 +1443,7 @@ static void sam_shutdown(struct uart_dev_s *dev) * ****************************************************************************/ -#ifdef SERIAL_HAVE_RXDMA +#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA) static void sam_dma_shutdown(struct uart_dev_s *dev) { struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; @@ -1328,14 +1453,31 @@ static void sam_dma_shutdown(struct uart_dev_s *dev) sam_shutdown(dev); #ifdef SERIAL_HAVE_RXDMA - /* Stop the RX DMA channel */ + if (priv->has_rxdma) + { + /* Stop the RX DMA channel */ - sam_dmastop(priv->rxdma); + sam_dmastop(priv->rxdma); - /* Release the RX DMA channel */ + /* Release the RX DMA channel */ - sam_dmafree(priv->rxdma); - priv->rxdma = NULL; + sam_dmafree(priv->rxdma); + priv->rxdma = NULL; + } +#endif + +#ifdef SERIAL_HAVE_TXDMA + if (priv->has_txdma) + { + /* Stop the TX DMA channel */ + + sam_dmastop(priv->txdma); + + /* Release the TX DMA channel */ + + sam_dmafree(priv->txdma); + priv->txdma = NULL; + } #endif } #endif @@ -1746,7 +1888,7 @@ static int sam_ioctl(struct file *filep, int cmd, unsigned long arg) * ****************************************************************************/ -#ifdef SERIAL_HAVE_NODMA_OPS +#ifdef SERIAL_HAVE_NORXDMA_OPS static int sam_receive(struct uart_dev_s *dev, unsigned int *status) { struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; @@ -1770,7 +1912,7 @@ static int sam_receive(struct uart_dev_s *dev, unsigned int *status) * ****************************************************************************/ -#ifdef SERIAL_HAVE_NODMA_OPS +#ifdef SERIAL_HAVE_NORXDMA_OPS static void sam_rxint(struct uart_dev_s *dev, bool enable) { struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; @@ -1800,7 +1942,7 @@ static void sam_rxint(struct uart_dev_s *dev, bool enable) * ****************************************************************************/ -#ifdef SERIAL_HAVE_NODMA_OPS +#ifdef SERIAL_HAVE_NORXDMA_OPS static bool sam_rxavailable(struct uart_dev_s *dev) { struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; @@ -1957,7 +2099,7 @@ static void sam_send(struct uart_dev_s *dev, int ch) * ****************************************************************************/ -#if defined(SERIAL_HAVE_RXDMA_OPS) || defined(SERIAL_HAVE_NODMA_OPS) +#ifdef SERIAL_HAVE_NOTXDMA_OPS static void sam_txint(struct uart_dev_s *dev, bool enable) { struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; @@ -2001,11 +2143,13 @@ static void sam_txint(struct uart_dev_s *dev, bool enable) * ****************************************************************************/ +#ifdef SERIAL_HAVE_NOTXDMA_OPS static bool sam_txready(struct uart_dev_s *dev) { struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; return ((sam_serialin(priv, SAM_UART_SR_OFFSET) & UART_INT_TXRDY) != 0); } +#endif /**************************************************************************** * Name: sam_dma_rxcallback @@ -2037,11 +2181,196 @@ static void sam_dma_rxcallback(DMA_HANDLE handle, void *arg, int status) * ****************************************************************************/ +#ifdef SERIAL_HAVE_NODMA_OPS static bool sam_txempty(struct uart_dev_s *dev) { struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; return ((sam_serialin(priv, SAM_UART_SR_OFFSET) & UART_INT_TXEMPTY) != 0); } +#endif + +/**************************************************************************** + * Name: sam_dma_send + * + * Description: + * This method will initiates DMA transfer for sending bytes over UART. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_TXDMA +static void sam_dma_send(struct uart_dev_s *dev) +{ + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; + uint32_t maddr; + uint32_t paddr; + size_t buflen; + + /* We need to stop DMA before reconfiguration */ + + sam_dmastop(priv->txdma); + + /* Flush the contents of the TX buffer into physical memory */ + + up_flush_dcache((uintptr_t)dev->dmatx.buffer, + (uintptr_t)dev->dmatx.buffer + dev->dmatx.length); + + /* Setup first half */ + + paddr = priv->usartbase + SAM_UART_THR_OFFSET; + + maddr = (uint32_t) dev->dmatx.buffer; + buflen = (size_t) dev->dmatx.length; + + /* Is this a split transfer? */ + + sam_dmatxsetup(priv->txdma, paddr, maddr, buflen); + + /* Start transmission with the callback on DMA completion */ + + sam_dmastart(priv->txdma, sam_dma_txcallback, (void *)dev); +} + +/**************************************************************************** + * Name: sam_dma_txint + * + * Description: + * This method handles TX interrupt if DMA is enabled. + * + ****************************************************************************/ + +static void sam_dma_txint(struct uart_dev_s *dev, bool enable) +{ + /* Nothing to do. */ + + /* In case of DMA transfer we do not want to make use of UART interrupts. + * Instead, we use DMA interrupts that are activated once during boot + * sequence. Furthermore we can use sam_dma_txcallback() to handle staff at + * half DMA transfer or after transfer completion (depending configuration, + * see stm32_dmastart(...) ). + */ +} + +/**************************************************************************** + * Name: sam_dma_txavailable + * + * Description: + * This method waits on semaphore until DMA is available. + * + ****************************************************************************/ + +static void sam_dma_txavailable(struct uart_dev_s *dev) +{ + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; + int rv; + + /* Only send when the DMA is idle */ + + if (sam_dmaresidual(priv->txdma) == 0) + { + uart_xmitchars_dma(dev); + } +} + +/**************************************************************************** + * Name: sam_dma_txavailable_worker + * + * Description: + * This method waits on semaphore until DMA is available. + * + ****************************************************************************/ + +static void sam_dma_txavailable_worker(void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + + /* Just call sam_dma_txavailable. We cannot have sam_dma_txavailable + * directly as a worker because the function is defined with + * struct uart_dev_s *dev parameter. + */ + + sam_dma_txavailable(dev); +} + +/**************************************************************************** + * Name: sam_dma_txcallback + * + * Description: + * This method implements callback after DMA is done. + * + ****************************************************************************/ + +static void sam_dma_txcallback(DMA_HANDLE handle, void *arg, int status) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct sam_dev_s *priv = (struct sam_dev_s *)dev->priv; + uint32_t maddr; + uint32_t paddr; + size_t buflen; + + if (status != OK) + { + /* This means some error occured during DMA transfer. This is most + * likely just rare error so schedule work again. Note that this is not + * ideal and we could end in an infinite loop. Better approach would be + * to use some error counter and report error to serial driver if + * counter exceeds some limit. However there currently is no way how to + * report DMA error to upper layer driver. + */ + + DEBUGASSERT(work_available(&priv->work)); + DEBUGVERIFY(work_queue(HPWORK, &priv->work, sam_dma_txavailable_worker, + (void *)dev, 0)); + return; + } + + /* Update 'nbytes' indicating number of bytes actually transferred by DMA. + * This is important to free TX buffer space by 'uart_xmitchars_done'. + */ + + dev->dmatx.nbytes = dev->dmatx.length; + if (priv->dev.dmatx.nlength) + { + /* Set up DMA on next buffer */ + + up_flush_dcache((uintptr_t)dev->dmatx.nbuffer, + (uintptr_t)dev->dmatx.nbuffer + dev->dmatx.nlength); + + paddr = priv->usartbase + SAM_UART_THR_OFFSET; + maddr = (uint32_t)dev->dmatx.nbuffer; + buflen = (size_t)dev->dmatx.nlength; + + /* Start transmission with the callback on DMA completion */ + + sam_dmatxsetup(priv->txdma, paddr, maddr, buflen); + + /* Set length for next completion */ + + priv->dev.dmatx.length = priv->dev.dmatx.nlength; + priv->dev.dmatx.nlength = 0; + + /* Start transmission with the callback on DMA completion */ + + sam_dmastart(priv->txdma, sam_dma_txcallback, (void *)dev); + + return; + } + + /* Finish DMA transfer and let waiting task (if any) know it is free + * to use. + */ + + uart_xmitchars_done(dev); + + /* Check for available transfer. This is handled by HP worker as we + * are currently in DMA interrupt. So just schedule next work and return + * from the interrupt. + */ + + DEBUGASSERT(work_available(&priv->work)); + DEBUGVERIFY(work_queue(HPWORK, &priv->work, sam_dma_txavailable_worker, + (void *)dev, 0)); +} +#endif /* SERIAL_HAVE_TXDMA */ /**************************************************************************** * Public Functions @@ -2164,7 +2493,7 @@ void arm_serialinit(void) uart_register("/dev/console", &CONSOLE_DEV); #endif -#ifdef SERIAL_HAVE_CONSOLE_RXDMA +#ifdef SERIAL_HAVE_CONSOLE_DMA /* If we need to re-initialise the console to enable DMA do that here. */ sam_dma_setup(&CONSOLE_DEV); diff --git a/arch/arm/src/samv7/sam_serial.h b/arch/arm/src/samv7/sam_serial.h index 142b631051a32..ff65430c06d3f 100644 --- a/arch/arm/src/samv7/sam_serial.h +++ b/arch/arm/src/samv7/sam_serial.h @@ -44,45 +44,99 @@ # define SERIAL_HAVE_RS485 1 #endif -/* Is RX DMA used on the console UART? */ - -#undef SERIAL_HAVE_CONSOLE_RXDMA -#if defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_USART0_RXDMA) -# define SERIAL_HAVE_CONSOLE_RXDMA -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_USART1_RXDMA) -# define SERIAL_HAVE_CONSOLE_RXDMA -#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_USART2_RXDMA) -# define SERIAL_HAVE_CONSOLE_RXDMA +/* Is RX/TX DMA used on the console UART? */ + +#undef SERIAL_HAVE_CONSOLE_DMA +#if defined(CONFIG_USART0_SERIAL_CONSOLE) && \ + (defined(CONFIG_USART0_RXDMA) || defined(CONFIG_USART0_TXDMA)) +# define SERIAL_HAVE_CONSOLE_DMA +#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && \ + (defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART1_TXDMA)) +# define SERIAL_HAVE_CONSOLE_DMA +#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && \ + (defined(CONFIG_USART2_RXDMA) || defined(CONFIG_USART2_TXDMA)) +# define SERIAL_HAVE_CONSOLE_DMA #endif -/* RX DMA ops */ +/* RX/TX DMA ops */ -#undef SERIAL_HAVE_NODMA_OPS +#undef SERIAL_HAVE_NORXDMA_OPS #if !defined(CONFIG_USART0_RXDMA) && defined(CONFIG_SAMV7_USART0) -# define SERIAL_HAVE_NODMA_OPS +# define SERIAL_HAVE_NORXDMA_OPS #elif !defined(CONFIG_USART1_RXDMA) && defined(CONFIG_SAMV7_USART1) -# define SERIAL_HAVE_NODMA_OPS +# define SERIAL_HAVE_NORXDMA_OPS #elif !defined(CONFIG_USART2_RXDMA) && defined(CONFIG_SAMV7_USART2) +# define SERIAL_HAVE_NORXDMA_OPS +#endif + +#undef SERIAL_HAVE_NOTXDMA_OPS +#if !defined(CONFIG_USART0_TXDMA) && defined(CONFIG_SAMV7_USART0) +# define SERIAL_HAVE_NOTXDMA_OPS +#elif !defined(CONFIG_USART1_TXDMA) && defined(CONFIG_SAMV7_USART1) +# define SERIAL_HAVE_NOTXDMA_OPS +#elif !defined(CONFIG_USART2_TXDMA) && defined(CONFIG_SAMV7_USART2) +# define SERIAL_HAVE_NOTXDMA_OPS +#endif + +#undef SERIAL_HAVE_RXTXDMA_OPS +#if defined(CONFIG_USART0_TXDMA) && defined(CONFIG_USART0_RXDMA) +# define SERIAL_HAVE_RXTXDMA_OPS +#elif defined(CONFIG_USART0_TXDMA) && !defined(CONFIG_USART0_RXDMA) +# define SERIAL_HAVE_TXDMA_OPS +#elif !defined(CONFIG_USART0_TXDMA) && defined(CONFIG_USART0_RXDMA) +# define SERIAL_HAVE_RXDMA_OPS +#endif +#if defined(CONFIG_USART1_TXDMA) && defined(CONFIG_USART1_RXDMA) +# define SERIAL_HAVE_RXTXDMA_OPS +#elif defined(CONFIG_USART1_TXDMA) && !defined(CONFIG_USART1_RXDMA) +# define SERIAL_HAVE_TXDMA_OPS +#elif !defined(CONFIG_USART1_TXDMA) && defined(CONFIG_USART1_RXDMA) +# define SERIAL_HAVE_RXDMA_OPS +#endif +#if defined(CONFIG_USART2_TXDMA) && defined(CONFIG_USART2_RXDMA) +# define SERIAL_HAVE_RXTXDMA_OPS +#elif defined(CONFIG_USART2_TXDMA) && !defined(CONFIG_USART2_RXDMA) +# define SERIAL_HAVE_TXDMA_OPS +#elif !defined(CONFIG_USART2_TXDMA) && defined(CONFIG_USART2_RXDMA) +# define SERIAL_HAVE_RXDMA_OPS +#endif + +/* No DMA ops */ + +#undef SERIAL_HAVE_NODMA_OPS +#if !defined(CONFIG_USART0_TXDMA) && !defined(CONFIG_USART0_RXDMA) && \ + defined(CONFIG_SAMV7_USART0) # define SERIAL_HAVE_NODMA_OPS -#elif defined(CONFIG_SAMV7_UART0) +#endif +#if !defined(CONFIG_USART1_TXDMA) && !defined(CONFIG_USART1_RXDMA) && \ + defined(CONFIG_SAMV7_USART1) # define SERIAL_HAVE_NODMA_OPS +#endif +#if !defined(CONFIG_USART2_TXDMA) && !defined(CONFIG_USART2_RXDMA) && \ + defined(CONFIG_SAMV7_USART2) +# define SERIAL_HAVE_NODMA_OPS +#endif + +#if defined(CONFIG_SAMV7_UART0) +# define SERIAL_HAVE_NODMA_OPS +# define SERIAL_HAVE_NORXDMA_OPS +# define SERIAL_HAVE_NOTXDMA_OPS #elif defined(CONFIG_SAMV7_UART1) # define SERIAL_HAVE_NODMA_OPS +# define SERIAL_HAVE_NORXDMA_OPS +# define SERIAL_HAVE_NOTXDMA_OPS #elif defined(CONFIG_SAMV7_UART2) # define SERIAL_HAVE_NODMA_OPS +# define SERIAL_HAVE_NORXDMA_OPS +# define SERIAL_HAVE_NOTXDMA_OPS #elif defined(CONFIG_SAMV7_UART3) # define SERIAL_HAVE_NODMA_OPS +# define SERIAL_HAVE_NORXDMA_OPS +# define SERIAL_HAVE_NOTXDMA_OPS #elif defined(CONFIG_SAMV7_UART4) # define SERIAL_HAVE_NODMA_OPS -#endif - -#undef SERIAL_HAVE_RXDMA_OPS -#if defined(CONFIG_USART0_RXDMA) -# define SERIAL_HAVE_RXDMA_OPS -#elif defined(CONFIG_USART1_RXDMA) -# define SERIAL_HAVE_RXDMA_OPS -#elif defined(CONFIG_USART2_RXDMA) -# define SERIAL_HAVE_RXDMA_OPS +# define SERIAL_HAVE_NORXDMA_OPS +# define SERIAL_HAVE_NOTXDMA_OPS #endif /**************************************************************************** @@ -101,7 +155,7 @@ ****************************************************************************/ #ifdef SERIAL_HAVE_RXDMA -void sam_serial_dma_poll(void) +void sam_serial_dma_poll(void); #endif #endif /* __ARCH_ARM_SRC_SAMV7_SAM_SERIAL_H */ diff --git a/arch/arm/src/samv7/sam_serial_spi.c b/arch/arm/src/samv7/sam_serial_spi.c new file mode 100644 index 0000000000000..a8bbd1efa4e47 --- /dev/null +++ b/arch/arm/src/samv7/sam_serial_spi.c @@ -0,0 +1,839 @@ +/**************************************************************************** + * arch/arm/src/samv7/sam_serial_spi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "sam_config.h" + +#include "hardware/sam_pinmap.h" +#include "hardware/sam_uart.h" +#include "sam_gpio.h" +#include "sam_periphclks.h" +#include "sam_serial_spi.h" + +#ifdef CONFIG_SAMV7_USART_IS_SPI_MASTER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define FAST_USART_CLOCK BOARD_MCK_FREQUENCY +#define SLOW_USART_CLOCK (BOARD_MCK_FREQUENCY >> 3) + +#define SERIAL_SPI_MAX_DIVIDER 65534 +#define SERIAL_SPI_MIN_DIVIDER 6 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct sam_serial_spi_pins_s +{ + uint32_t mosi; + uint32_t miso; + uint32_t sck; + uint32_t nss; +}; + +struct sam_serial_spi_s +{ + struct sam_serial_spi_pins_s pins; + uint32_t base; /* SPI controller register base address */ + uint32_t frequency; /* Requested clock frequency */ + uint32_t actual; /* Actual clock frequency */ + uint8_t mode; /* Mode 0,1,2,3 */ + uint8_t nbits; /* Width of word in bits (8 or 9) */ + mutex_t spilock; /* Assures mutually exclusive access to SPI */ + bool initialized; /* TRUE: Controller has been initialized */ +}; + +/* The overall state of one SPI controller */ + +struct sam_spidev_s +{ + const struct spi_ops_s *ops; + struct sam_serial_spi_s *priv; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint32_t serial_getreg(struct sam_serial_spi_s *priv, + int offset); +static inline void serial_putreg(struct sam_serial_spi_s *priv, int offset, + uint32_t value); +static inline void serial_flush(struct sam_serial_spi_s *priv); + +/* SPI master methods */ + +static int serial_spi_lock(struct spi_dev_s *dev, bool lock); +static void serial_spi_select(struct spi_dev_s *dev, uint32_t devid, + bool selected); +static uint32_t serial_spi_setfrequency(struct spi_dev_s *dev, + uint32_t frequency); +static void serial_spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode); +static void serial_spi_setbits(struct spi_dev_s *dev, int nbits); +static uint8_t serial_spi_status(struct spi_dev_s *dev, uint32_t devid); +static uint32_t serial_spi_send(struct spi_dev_s *dev, uint32_t wd); +static void serial_spi_exchange(struct spi_dev_s *dev, const void *txbuffer, + void *rxbuffer, size_t nwords); +#ifndef CONFIG_SPI_EXCHANGE +static void serial_spi_sndblock(struct spi_dev_s *dev, const void *buffer, + size_t nwords); +static void serial_spi_recvblock(struct spi_dev_s *dev, void *buffer, + size_t nwords); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* SERIAL_SPI driver operations */ + +static const struct spi_ops_s g_spiops = +{ + .lock = serial_spi_lock, + .select = serial_spi_select, + .setfrequency = serial_spi_setfrequency, + .setmode = serial_spi_setmode, + .setbits = serial_spi_setbits, + .status = serial_spi_status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = NULL, +#endif + .send = serial_spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = serial_spi_exchange, +#else + .sndblock = serial_spi_sndblock, + .recvblock = serial_spi_recvblock, +#endif + .registercallback = NULL, +}; + +/* This is the overall state of the SPI0 controller */ + +#ifdef CONFIG_SAMV7_USART0_SPI_MASTER +static struct sam_serial_spi_s sam_serial0spi_priv = +{ + .pins = + { + .mosi = GPIO_USART0_TXD, + .miso = GPIO_USART0_RXD, + .sck = GPIO_USART0_SCK, + .nss = GPIO_USART0_RTS, + }, + .base = SAM_USART0_BASE, + .actual = 0, + .mode = 0, + .nbits = 0, + .spilock = NXMUTEX_INITIALIZER, + .initialized = false, +}; +#endif + +#ifdef CONFIG_SAMV7_USART1_SPI_MASTER +static struct sam_serial_spi_s sam_serial1spi_priv = +{ + .pins = + { + .mosi = GPIO_USART1_TXD, + .miso = GPIO_USART1_RXD, + .sck = GPIO_USART1_SCK, + .nss = GPIO_USART1_RTS, + }, + .base = SAM_USART1_BASE, + .actual = 0, + .mode = 0, + .nbits = 0, + .spilock = NXMUTEX_INITIALIZER, + .initialized = false, +}; +#endif + +#ifdef CONFIG_SAMV7_USART2_SPI_MASTER +static struct sam_serial_spi_s sam_serial2spi_priv = +{ + .pins = + { + .mosi = GPIO_USART2_TXD, + .miso = GPIO_USART2_RXD, + .sck = GPIO_USART2_SCK, + .nss = GPIO_USART2_RTS, + }, + .base = SAM_USART2_BASE, + .actual = 0, + .mode = 0, + .nbits = 0, + .spilock = NXMUTEX_INITIALIZER, + .initialized = false, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline uint32_t serial_getreg(struct sam_serial_spi_s *priv, + int offset) +{ + return getreg32(priv->base + offset); +} + +/**************************************************************************** + * Name: sam_serialout + ****************************************************************************/ + +static inline void serial_putreg(struct sam_serial_spi_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->base + offset); +} + +/**************************************************************************** + * Name: serial_flush + ****************************************************************************/ + +static inline void serial_flush(struct sam_serial_spi_s *priv) +{ + uint32_t status; + + /* Make sure the no TX activity is in progress... waiting if necessary */ + + status = serial_getreg(priv, SAM_UART_SR_OFFSET); + while ((status & UART_INT_TXRDY) == 0) + { + nxsig_usleep(100); + status = serial_getreg(priv, SAM_UART_SR_OFFSET); + } + + /* Then make sure that there is no pending RX data .. reading as + * discarding as necessary. + */ + + while ((serial_getreg(priv, SAM_UART_SR_OFFSET) & UART_INT_RXRDY) != 0) + { + serial_getreg(priv, SAM_UART_RHR_OFFSET); + } +} + +/**************************************************************************** + * Name: serial_spi_lock + * + * Description: + * On SPI buses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the buses for a sequence of + * transfers. The bus should be locked before the chip is selected. After + * locking the SPI bus, the caller should then also call the setfrequency, + * setbits, and setmode methods to make sure that the SPI is properly + * configured for the device. If the SPI bus is being shared, then it + * may have been left in an incompatible state. + * + * Input Parameters: + * dev - Device-specific state data + * lock - true: Lock spi bus, false: unlock SPI bus + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int serial_spi_lock(struct spi_dev_s *dev, bool lock) +{ + struct sam_spidev_s *spi = (struct sam_spidev_s *)dev; + struct sam_serial_spi_s *priv = (struct sam_serial_spi_s *)spi->priv; + int ret; + + spiinfo("lock=%d\n", lock); + if (lock) + { + ret = nxmutex_lock(&priv->spilock); + } + else + { + ret = nxmutex_unlock(&priv->spilock); + } + + return ret; +} + +/**************************************************************************** + * Name: serial_spi_select + * + * Description: + * This function does not actually set the chip select line. Rather, it + * simply maps the device ID into a chip select number and retains that + * chip select number for later use. + * + * Input Parameters: + * dev - Device-specific state data + * devid - Device ID + * selected - true if CS is selected + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void serial_spi_select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + struct sam_spidev_s *spi = (struct sam_spidev_s *)dev; + struct sam_serial_spi_s *priv = (struct sam_serial_spi_s *)spi->priv; + + /* There is only one CS. */ + + spiinfo("Chip select %d\n", selected); + + if (selected) + { + serial_putreg(priv, SAM_UART_CR_OFFSET, UART_CR_FCS); + } + else + { + serial_putreg(priv, SAM_UART_CR_OFFSET, UART_CR_RCS); + } +} + +/**************************************************************************** + * Name: serial_spi_setfrequency + * + * Description: + * Set the SPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static uint32_t serial_spi_setfrequency(struct spi_dev_s *dev, + uint32_t frequency) +{ + struct sam_spidev_s *spi = (struct sam_spidev_s *)dev; + struct sam_serial_spi_s *priv = (struct sam_serial_spi_s *)spi->priv; + uint32_t intpart; + uint32_t regval; + uint32_t selected_clk; + uint32_t actual; + + spiinfo("frequency=%ld\n", frequency); + + if (priv->frequency == frequency) + { + return priv->actual; + } + + /* Disable receiver and transmitter */ + + serial_putreg(priv, SAM_UART_CR_OFFSET, UART_CR_RXDIS | UART_CR_TXDIS); + + /* Configure the SPI frequency/baud rate: + * + * divisor = selected clock / baud rate + */ + + selected_clk = FAST_USART_CLOCK; + intpart = (selected_clk + (frequency >> 1)) / frequency; + + if ((intpart & ~UART_BRGR_CD_MASK) != 0) + { + /* Use the divided USART clock */ + + selected_clk = SLOW_USART_CLOCK; + intpart = (selected_clk + (frequency >> 1)) / + frequency; + + /* Re-select the clock source */ + + regval = serial_getreg(priv, SAM_UART_MR_OFFSET); + regval &= ~UART_MR_USCLKS_MASK; + regval |= UART_MR_USCLKS_MCKDIV; + serial_putreg(priv, SAM_UART_MR_OFFSET, regval); + + /* Value written in UART_BRGR_CD must be even to ensure a + * 50:50 mark of the SCK pin. This applies only if + * UART_MR_USCLKS_MCKDIV is selected + */ + + if (intpart % 2 != 0) + { + intpart += 1; + } + } + + /* Value written in UART_BRGR_CD greater or equal to 6. */ + + if (intpart < SERIAL_SPI_MIN_DIVIDER) + { + intpart = SERIAL_SPI_MIN_DIVIDER; + } + else if (intpart > SERIAL_SPI_MAX_DIVIDER) + { + intpart = SERIAL_SPI_MAX_DIVIDER; + } + + regval = UART_BRGR_CD(intpart); + + serial_putreg(priv, SAM_UART_BRGR_OFFSET, regval); + + /* Enable receiver & transmitter */ + + serial_putreg(priv, SAM_UART_CR_OFFSET, UART_CR_RXEN | UART_CR_TXEN); + + actual = selected_clk / intpart; + + spiinfo("Frequency %ld->%ld\n", priv->frequency, actual); + + priv->frequency = frequency; + priv->actual = actual; + + return actual; +} + +/**************************************************************************** + * Name: serial_spi_setmode + * + * Description: + * Set the SPI mode. Optional. See enum spi_mode_e for mode definitions + * + * Input Parameters: + * dev - Device-specific state data + * mode - The SPI mode requested + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void serial_spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) +{ + struct sam_spidev_s *spi = (struct sam_spidev_s *)dev; + struct sam_serial_spi_s *priv = (struct sam_serial_spi_s *)spi->priv; + uint32_t regval; + + spiinfo("mode=%d\n", mode); + + /* Perform operation only if mode has changed. */ + + if (mode != priv->mode) + { + /* Yes. Set the mode: + * + * MODE + * SPI CPOL NCPHA + * 0 0 1 + * 1 0 0 + * 2 1 1 + * 3 1 0 + */ + + regval = serial_getreg(priv, SAM_UART_MR_OFFSET); + regval &= ~(UART_MR_CPOL | UART_MR_CPHA); + + switch (mode) + { + case SPIDEV_MODE0: /* CPOL=0; CPHA=1 */ + regval |= UART_MR_CPHA; + break; + + case SPIDEV_MODE1: /* CPOL=0; CPHA=0 */ + break; + + case SPIDEV_MODE2: /* CPOL=1; CPHA=1 */ + regval |= UART_MR_CPOL | UART_MR_CPHA; + break; + + case SPIDEV_MODE3: /* CPOL=1; CPHA=0 */ + regval |= UART_MR_CPOL; + break; + + default: + DEBUGASSERT(FALSE); + return; + } + + serial_putreg(priv, SAM_UART_MR_OFFSET, regval); + + /* Save the mode so that subsequent re-configurations will be faster */ + + priv->mode = mode; + } +} + +/**************************************************************************** + * Name: serial_spi_setbits + * + * Description: + * Set the number if bits per word. + * + * Input Parameters: + * dev - Device-specific state data + * nbits - The number of bits requested + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void serial_spi_setbits(struct spi_dev_s *dev, int nbits) +{ + /* Only 8 bit transfer is supported. */ + + spiinfo("Only 8 bit transfer is supported on USART SPI.\n"); +} + +/**************************************************************************** + * Name: serial_spi_status + * + * Description: + * Return status information associated with the SPI device. + * + * Input Parameters: + * devid - Identifies the (logical) device + * + * Returned Value: + * Bit-encoded SPI status (see include/nuttx/spi/spi.h. + * + ****************************************************************************/ + +static uint8_t serial_spi_status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} + +/**************************************************************************** + * Name: serial_spi_send + * + * Description: + * Exchange one word on SPI + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * response + * + ****************************************************************************/ + +static uint32_t serial_spi_send(struct spi_dev_s *dev, uint32_t wd) +{ + uint8_t txbyte; + uint8_t rxbyte; + + txbyte = (uint8_t)wd; + rxbyte = (uint8_t)0; + serial_spi_exchange(dev, &txbyte, &rxbyte, 1); + + spierr("Sent %02x received %02x\n", txbyte, rxbyte); + return (uint32_t)rxbyte; +} + +/**************************************************************************** + * Name: serial_spi_exchange + * + * Description: + * Exchange a block of data from SPI. + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to the buffer in which to receive data + * nwords - the length of data that to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void serial_spi_exchange(struct spi_dev_s *dev, const void *txbuffer, + void *rxbuffer, size_t nwords) +{ + struct sam_spidev_s *spi = (struct sam_spidev_s *)dev; + struct sam_serial_spi_s *priv = (struct sam_serial_spi_s *)spi->priv; + uint32_t data; + uint32_t status; + uint8_t *rxptr; + uint8_t *txptr; + + spiinfo("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); + + /* Set up working pointers */ + + rxptr = (uint8_t *)rxbuffer; + txptr = (uint8_t *)txbuffer; + + /* Make sure that any previous transfer is flushed from the hardware */ + + serial_flush(priv); + + for (; nwords > 0; nwords--) + { + /* Get the data to send (0xff if there is no data source). */ + + if (txptr) + { + data = (uint32_t)*txptr++; + } + else + { + data = 0xffff; + } + + /* Wait for any previous data written to the TDR to be transferred + * to the serializer. + */ + + status = serial_getreg(priv, SAM_UART_SR_OFFSET); + while ((status & UART_INT_TXRDY) == 0) + { + nxsig_usleep(100); + status = serial_getreg(priv, SAM_UART_SR_OFFSET); + } + + /* Write the data to transmitted to the Transmit Data Register (TDR) */ + + serial_putreg(priv, SAM_UART_THR_OFFSET, data); + + /* Wait for the read data to be available in the RDR. */ + + status = serial_getreg(priv, SAM_UART_SR_OFFSET); + while ((status & UART_INT_RXRDY) == 0) + { + nxsig_usleep(100); + status = serial_getreg(priv, SAM_UART_SR_OFFSET); + } + + /* Read the received data from the SPI Data Register. */ + + data = serial_getreg(priv, SAM_UART_RHR_OFFSET); + if (rxptr) + { + *rxptr++ = (uint8_t)data; + } + } +} + +/**************************************************************************** + * Name: serial_spi_sndblock + * + * Description: + * Send a block of data on SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void serial_spi_sndblock(struct spi_dev_s *dev, const void *buffer, + size_t nwords) +{ + /* spi_exchange can do this. */ + + serial_spi_exchange(dev, buffer, NULL, nwords); +} + +/**************************************************************************** + * Name: serial_spi_recvblock + * + * Description: + * Revice a block of data from SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer in which to receive data + * nwords - the length of data that can be received in the buffer in number + * of words. The wordsize is determined by the number of + * bits-per-word selected for the SPI interface. If nbits <= 8, + * the data is packed into uint8_t's; if nbits >8, the data is + * packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void serial_spi_recvblock(struct spi_dev_s *dev, void *buffer, + size_t nwords) +{ + /* spi_exchange can do this. */ + + serial_spi_exchange(dev, NULL, buffer, nwords); +} +#endif /* CONFIG_SPI_EXCHANGE */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_serial_spi_initialize + * + * Description: + * Initialize the selected SPI port in master mode + * + * Input Parameters: + * port - USART interface to be used (0-2) + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct spi_dev_s *sam_serial_spi_initialize(int port) +{ + struct sam_serial_spi_s *priv; + struct sam_spidev_s *spi; + irqstate_t flags; + uint32_t regval; + + spiinfo("Initializing USART%d as SPI\n", port); + DEBUGASSERT(port >= 0 && port < SAMV7_NUSART); + + switch (port) + { +#ifdef CONFIG_SAMV7_USART0_SPI_MASTER + case 0: + sam_usart0_enableclk(); + priv = &sam_serial0spi_priv; + break; +#endif +#ifdef CONFIG_SAMV7_USART1_SPI_MASTER + case 1: + sam_usart1_enableclk(); + priv = &sam_serial1spi_priv; + break; +#endif +#ifdef CONFIG_SAMV7_USART2_SPI_MASTER + case 2: + sam_usart2_enableclk(); + priv = &sam_serial2spi_priv; + break; +#endif + default: + spierr("ERROR: Incorrect port number %d\n", port); + return NULL; + } + + spi = kmm_zalloc(sizeof(struct sam_spidev_s)); + if (!spi) + { + spierr("ERROR: Could not allocate sam_spics_s structure!\n"); + return NULL; + } + + /* Select the SPI operations */ + + spi->ops = &g_spiops; + spi->priv = priv; + + if (!priv->initialized) + { + flags = enter_critical_section(); + + sam_configgpio(priv->pins.mosi); + sam_configgpio(priv->pins.miso); + sam_configgpio(priv->pins.sck); + sam_configgpio(priv->pins.nss); + + /* Disable write protection */ + + serial_putreg(priv, SAM_UART_WPMR_OFFSET, USART_WPMR_WPKEY); + + serial_putreg(priv, SAM_UART_MR_OFFSET, 0); + serial_putreg(priv, SAM_UART_RTOR_OFFSET, 0); + serial_putreg(priv, SAM_UART_TTGR_OFFSET, 0); + + /* Reset and disable receiver and transmitter */ + + serial_putreg(priv, SAM_UART_CR_OFFSET, + (UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RXDIS | + UART_CR_TXDIS)); + + /* Reset status bits */ + + serial_putreg(priv, SAM_UART_CR_OFFSET, UART_CR_RSTSTA); + + leave_critical_section(flags); + + /* Configure mode register. */ + + regval = UART_MR_MODE_SPIMSTR | UART_MR_CLKO | UART_MR_CHRL_8BITS; + serial_putreg(priv, SAM_UART_MR_OFFSET, regval); + + /* Enable receiver & transmitter */ + + serial_putreg(priv, SAM_UART_CR_OFFSET, (UART_CR_RXEN | UART_CR_TXEN)); + + spi->priv->mode = 0; + spi->priv->nbits = 8; + spi->priv->frequency = 0; + spi->priv->actual = 0; + + priv->initialized = true; + } + + return (struct spi_dev_s *)spi; +} + +#endif /* CONFIG_SAMV7_USART_IS_SPI_MASTER */ diff --git a/arch/arm/src/samv7/sam_serial_spi.h b/arch/arm/src/samv7/sam_serial_spi.h new file mode 100644 index 0000000000000..15ec169ef4bea --- /dev/null +++ b/arch/arm/src/samv7/sam_serial_spi.h @@ -0,0 +1,109 @@ +/**************************************************************************** + * arch/arm/src/samv7/sam_serial_spi.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMV7_SAM_SERIAL_SPI_H +#define __ARCH_ARM_SRC_SAMV7_SAM_SERIAL_SPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "sam_config.h" + +#ifdef CONFIG_SAMV7_USART_IS_SPI_MASTER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_serial_spi_initialize + * + * Description: + * Initialize the selected SPI port in master mode + * + * Input Parameters: + * port - USART interface to be used (0-2) + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct spi_dev_s; +struct spi_dev_s *sam_serial_spi_initialize(int port); + +/**************************************************************************** + * Name: sam_serial_status + * + * Description: + * Return status information associated with the SPI device. + * + * Input Parameters: + * devid - Identifies the (logical) device + * + * Returned Value: + * Bit-encoded SPI status (see include/nuttx/spi/spi.h). + * + ****************************************************************************/ + +uint8_t sam_serial_status(struct spi_dev_s *dev, uint32_t devid); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_SAMV7_USART_IS_SPI_MASTER */ +#endif /* __ARCH_ARM_SRC_SAMV7_SAM_SERIAL_SPI_H */ diff --git a/arch/arm/src/samv7/sam_systemreset.c b/arch/arm/src/samv7/sam_systemreset.c index 02d969ff09240..0ae11e233559b 100644 --- a/arch/arm/src/samv7/sam_systemreset.c +++ b/arch/arm/src/samv7/sam_systemreset.c @@ -33,13 +33,59 @@ #include "arm_internal.h" #include "hardware/sam_rstc.h" - -#ifdef CONFIG_SAMV7_SYSTEMRESET +#include "sam_systemreset.h" /**************************************************************************** * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: sam_get_reset_cause + * + * Description: + * Get cause of the last CPU reset. This is done by reading reset status + * registger. + * + * Returned Value: + * CPU reset cause in form of macros defined in sam_systemreset.h. This is + * to avoid passing boardctl dependent structure to architecture layer. + * Board level specific code should include sam_systemreset.h and set + * boardctl result according to that. -1 is returned in case of invalid + * value in status register. + * + ****************************************************************************/ + +int sam_get_reset_cause(void) +{ + int ret; + uint32_t rstsr; + + rstsr = getreg32(SAM_RSTC_SR); + switch (rstsr & RSTC_SR_RSTTYP_MASK) + { + case RSTC_SR_RSTTYP_PWRUP: + ret = SAMV7_RESET_PWRUP; + break; + case RSTC_SR_RSTTYP_BACKUP: + ret = SAMV7_RESET_BACKUP; + break; + case RSTC_SR_RSTTYP_WDOG: + ret = SAMV7_RESET_WDOG; + break; + case RSTC_SR_RSTTYP_SWRST: + ret = SAMV7_RESET_SWRST; + break; + case RSTC_SR_RSTTYP_NRST: + ret = SAMV7_RESET_NRST; + break; + default: + ret = -1; + break; + } + + return ret; +} + /**************************************************************************** * Name: up_systemreset * @@ -48,6 +94,7 @@ * ****************************************************************************/ +#ifdef CONFIG_SAMV7_SYSTEMRESET void up_systemreset(void) { uint32_t rstcr; diff --git a/arch/arm/src/samv7/sam_systemreset.h b/arch/arm/src/samv7/sam_systemreset.h new file mode 100644 index 0000000000000..d64c193e5d811 --- /dev/null +++ b/arch/arm/src/samv7/sam_systemreset.h @@ -0,0 +1,62 @@ +/**************************************************************************** + * arch/arm/src/samv7/sam_systemreset.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMV7_SAM_SYSTEMRESET_H +#define __ARCH_ARM_SRC_SAMV7_SAM_SYSTEMRESET_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SAMV7_RESET_PWRUP 1 +#define SAMV7_RESET_BACKUP 2 +#define SAMV7_RESET_WDOG 3 +#define SAMV7_RESET_SWRST 4 +#define SAMV7_RESET_NRST 5 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_get_reset_cause + * + * Description: + * Get cause of the last CPU reset. This is done by reading reset status + * registger. + * + * Returned Value: + * CPU reset cause in form of macros defined in sam_systemreset.h. This is + * to avoid passing boardctl dependent structure to architecture layer. + * Board level specific code should include sam_systemreset.h and set + * boardctl result according to that. -1 is returned in case of invalid + * value in status register. + * + ****************************************************************************/ + +int sam_get_reset_cause(void); + +#endif /* __ARCH_ARM_SRC_SAMV7_SAM_SYSTEMRESET_H */ diff --git a/arch/arm/src/samv7/sam_us.c b/arch/arm/src/samv7/sam_us.c new file mode 100644 index 0000000000000..aca0376617fd0 --- /dev/null +++ b/arch/arm/src/samv7/sam_us.c @@ -0,0 +1,191 @@ +/**************************************************************************** + * arch/arm/src/samv7/sam_us.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "barriers.h" + +#include "hardware/sam_memorymap.h" + +#include "sam_eefc.h" +#include "sam_us.h" + +#ifdef CONFIG_SAMV7_USER_SIGNATURE + +#define SAMV7_US_START (SAM_INTFLASH_BASE) +#define SAMV7_US_SIZE (512) +#define SAMV7_US_PAGE_WORDS (SAMV7_US_SIZE / sizeof(uint32_t)) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint32_t g_page_buffer[SAMV7_US_PAGE_WORDS]; +static mutex_t g_page_lock = NXMUTEX_INITIALIZER; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_erase_user_signature + * + * Description: + * Erases user signature page. + * + * Returned Value: + * Zero on success, negated errno value on error. + * + ****************************************************************************/ + +int sam_erase_user_signature(void) +{ + int ret; + + ret = sam_eefc_command(EEFC_FCR_FCMD_EUS, 0); + if (ret < 0) + { + return ret; + } + + return 0; +} + +/**************************************************************************** + * Name: sam_write_user_signature + * + * Description: + * Writes data to user signature page. + * + * Input Parameters: + * buffer - The buffer to be written to user signature. + * buflen - Number of bytes to be written. + * + * Returned Value: + * Number of written bytes on success, negated errno on error. + * + ****************************************************************************/ + +int sam_write_user_signature(void *buffer, size_t buflen) +{ + uint32_t *dest; + int ret; + + if (buflen > SAMV7_US_SIZE) + { + return -ENOMEM; + } + + /* Ensure single access to gloval g_page_buffer */ + + ret = nxmutex_lock(&g_page_lock); + if (ret < 0) + { + return ret; + } + + memcpy((uint8_t *)g_page_buffer, buffer, buflen); + + /* Reference manual 22.4.3.9: Write the full page, at any page address, + * within the internal memory area address space. + */ + + dest = (uint32_t *)SAMV7_US_START; + for (int i = 0; i < SAMV7_US_PAGE_WORDS; i++) + { + *dest++ = g_page_buffer[i]; + +#ifdef CONFIG_ARMV7M_DCACHE_WRITETHROUGH + ARM_DMB(); +#endif + } + + /* Flush the data cache to memory */ + + up_clean_dcache(SAMV7_US_START, SAMV7_US_START + SAMV7_US_SIZE); + + /* EEFC_FCR_FARG does not have any affect for user signature, + * therefore second argument can be zero. + */ + + ret = sam_eefc_command(EEFC_FCR_FCMD_WUS, 0); + if (ret < 0) + { + nxmutex_unlock(&g_page_lock); + return ret; + } + + nxmutex_unlock(&g_page_lock); + return buflen; +} + +/**************************************************************************** + * Name: sam_get_user_signature + * + * Description: + * Get bytes from user signature area. + * + * Input Parameters: + * buffer - The buffer to store user signature. + * buflen - Number of bytes to be read. + * + * Returned Value: + * NONE. + * + ****************************************************************************/ + +int sam_read_user_signature(void *buffer, size_t buflen) +{ + size_t nwords; + int ret; + + /* Ensure single access to gloval g_page_buffer */ + + ret = nxmutex_lock(&g_page_lock); + if (ret < 0) + { + return ret; + } + + /* sam_eefc_readsequence requires read length in bit words. */ + + nwords = (buflen + sizeof(uint32_t) / sizeof(uint32_t)); + sam_eefc_readsequence(FCMD_STUS, FCMD_SPUS, g_page_buffer, nwords); + + /* Copy local buffer to void *buffer provided by the user. */ + + memcpy(buffer, (uint8_t *)g_page_buffer, buflen); + + nxmutex_unlock(&g_page_lock); + return buflen; +} + +#endif /* CONFIG_SAMV7_USER_SIGNATURE */ diff --git a/arch/arm/src/samv7/sam_us.h b/arch/arm/src/samv7/sam_us.h new file mode 100644 index 0000000000000..548febec8ef96 --- /dev/null +++ b/arch/arm/src/samv7/sam_us.h @@ -0,0 +1,81 @@ +/**************************************************************************** + * arch/arm/src/samv7/sam_us.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMV7_SAM_US_H +#define __ARCH_ARM_SRC_SAMV7_SAM_US_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_erase_user_signature + * + * Description: + * Erases user signature page. + * + * Returned Value: + * Zero on success, negated errno value on error. + * + ****************************************************************************/ + +int sam_erase_user_signature(void); + +/**************************************************************************** + * Name: sam_write_user_signature + * + * Description: + * Writes data to user signature page. + * + * Input Parameters: + * buffer - The buffer to be written to user signature. + * buflen - Number of bytes to be written. + * + * Returned Value: + * Number of written bytes on success, negated errno on error. + * + ****************************************************************************/ + +int sam_write_user_signature(void *buffer, size_t buflen); + +/**************************************************************************** + * Name: sam_get_user_signature + * + * Description: + * Get bytes from user signature area. + * + * Input Parameters: + * buffer - The buffer to store user signature. + * buflen - Number of bytes to be read. + * + * Returned Value: + * NONE. + * + ****************************************************************************/ + +int sam_read_user_signature(void *buffer, size_t buflen); + +#endif /* __ARCH_ARM_SRC_SAMV7_SAM_US_H */ diff --git a/arch/arm/src/samv7/sam_xdmac.c b/arch/arm/src/samv7/sam_xdmac.c index 1daa39cc6ac05..dcca1bf6ae7e6 100644 --- a/arch/arm/src/samv7/sam_xdmac.c +++ b/arch/arm/src/samv7/sam_xdmac.c @@ -2118,6 +2118,25 @@ size_t sam_destaddr(DMA_HANDLE handle) return sam_getdmach(xdmach, SAM_XDMACH_CDA_OFFSET); } +/**************************************************************************** + * Name: sam_dmaresidual + * + * Description: + * Returns the number of bytes remaining to be transferred + * + * Assumptions: + * - DMA handle allocated by sam_dmachannel() + * + ****************************************************************************/ + +size_t sam_dmaresidual(DMA_HANDLE handle) +{ + struct sam_xdmach_s *xdmach = (struct sam_xdmach_s *)handle; + uint32_t cubc = sam_getdmach(xdmach, SAM_XDMACH_CUBC_OFFSET); + + return cubc & XDMACH_CUBC_UBLEN_MASK; +} + /**************************************************************************** * Name: sam_dmasample * diff --git a/arch/arm/src/samv7/sam_xdmac.h b/arch/arm/src/samv7/sam_xdmac.h index 533fa488d9e35..869ddc3e1671b 100644 --- a/arch/arm/src/samv7/sam_xdmac.h +++ b/arch/arm/src/samv7/sam_xdmac.h @@ -238,6 +238,19 @@ extern "C" size_t sam_destaddr(DMA_HANDLE handle); +/**************************************************************************** + * Name: sam_dmaresidual + * + * Description: + * Returns the number of bytes remaining to be transferred + * + * Assumptions: + * - DMA handle allocated by sam_dmachannel() + * + ****************************************************************************/ + +size_t sam_dmaresidual(DMA_HANDLE handle); + /**************************************************************************** * Name: sam_dmachannel * diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h b/arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h index 37cb8c0b11a67..142bb058a39ff 100644 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h +++ b/arch/arm/src/stm32/hardware/stm32f40xxx_pinmap.h @@ -1029,8 +1029,10 @@ #define GPIO_USART6_RTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN8) #define GPIO_USART6_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) #define GPIO_USART6_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9) +#define GPIO_USART6_RX_3 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12) #define GPIO_USART6_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) #define GPIO_USART6_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14) +#define GPIO_USART6_TX_3 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ defined(CONFIG_STM32_STM32F469) diff --git a/arch/arm/src/stm32/hardware/stm32f40xxx_pinmap_legacy.h b/arch/arm/src/stm32/hardware/stm32f40xxx_pinmap_legacy.h index eabd7a1d6e32b..e7ebec04404a7 100644 --- a/arch/arm/src/stm32/hardware/stm32f40xxx_pinmap_legacy.h +++ b/arch/arm/src/stm32/hardware/stm32f40xxx_pinmap_legacy.h @@ -1029,8 +1029,10 @@ #define GPIO_USART6_RTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN8) #define GPIO_USART6_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7) #define GPIO_USART6_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9) +#define GPIO_USART6_RX_3 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12) #define GPIO_USART6_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6) #define GPIO_USART6_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14) +#define GPIO_USART6_TX_3 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11) #if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \ defined(CONFIG_STM32_STM32F469) diff --git a/arch/arm/src/stm32/stm32_pwm.c b/arch/arm/src/stm32/stm32_pwm.c index df937654cdec2..cc8436fe76f75 100644 --- a/arch/arm/src/stm32/stm32_pwm.c +++ b/arch/arm/src/stm32/stm32_pwm.c @@ -247,7 +247,7 @@ # define TIMRST_TIM16 RCC_APB1RSTR_TIM16RST # define TIMCLK_TIM17 STM32_APB1_TIM17_CLKIN # define TIMRCCEN_TIM17 STM32_RCC_APB1ENR -# define TIMEN_TIM17 RCC_APB1ENR_TIM71EN +# define TIMEN_TIM17 RCC_APB1ENR_TIM17EN # define TIMRCCRST_TIM17 STM32_RCC_APB1RSTR # define TIMRST_TIM17 RCC_APB1RSTR_TIM17RST #endif @@ -4463,6 +4463,13 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) outputs = pwm_outputs_from_channels(priv); ret = pwm_outputs_enable(dev, outputs, false); + /* Clear all channels */ + + pwm_putreg(priv, STM32_GTIM_CCR1_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_CCR2_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_CCR3_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_CCR4_OFFSET, 0); + leave_critical_section(flags); pwm_dumpregs(dev, "After stop"); diff --git a/arch/arm/src/stm32/stm32_serial.c b/arch/arm/src/stm32/stm32_serial.c index 98888ff1353a5..ca5010446cb77 100644 --- a/arch/arm/src/stm32/stm32_serial.c +++ b/arch/arm/src/stm32/stm32_serial.c @@ -1339,11 +1339,11 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); up_setusartint(priv, ie); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -1354,7 +1354,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (ie) { @@ -1395,7 +1395,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) up_setusartint(priv, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -2227,11 +2227,14 @@ static int up_interrupt(int irq, void *context, void *arg) static int up_ioctl(struct file *filep, int cmd, unsigned long arg) { #if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) \ - || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) \ + || defined(CONFIG_STM32_USART_SINGLEWIRE) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; #endif -#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) +#if defined(CONFIG_SERIAL_TERMIOS) \ + || defined(CONFIG_STM32_SERIALBRK_BSDCOMPAT) \ + || defined(CONFIG_STM32_USART_SINGLEWIRE) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; #endif int ret = OK; diff --git a/arch/arm/src/stm32/stm32f30xxx_rcc.c b/arch/arm/src/stm32/stm32f30xxx_rcc.c index 7b4f6ca258a07..a6daf9dece914 100644 --- a/arch/arm/src/stm32/stm32f30xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f30xxx_rcc.c @@ -476,6 +476,13 @@ static void stm32_stdclockconfig(void) #endif + /* Enable FLASH prefetch buffer and set FLASH wait states */ + + regval = getreg32(STM32_FLASH_ACR); + regval &= ~FLASH_ACR_LATENCY_MASK; + regval |= (FLASH_ACR_LATENCY_SETTING | FLASH_ACR_PRTFBE); + putreg32(regval, STM32_FLASH_ACR); + /* Set the HCLK source/divider */ regval = getreg32(STM32_RCC_CFGR); diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c index 4b572fffea36d..770aacb4dc321 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial_v1.c @@ -803,7 +803,7 @@ static void stm32serial_disableusartint(struct stm32_serial_s *priv, { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (ie) { @@ -847,7 +847,7 @@ static void stm32serial_disableusartint(struct stm32_serial_s *priv, stm32serial_setusartint(priv, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c b/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c index 19d88d613e810..2c2a701ee8db3 100644 --- a/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c +++ b/arch/arm/src/stm32f0l0g0/stm32_serial_v2.c @@ -531,11 +531,11 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); up_setusartint(priv, ie); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -546,7 +546,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (ie) { @@ -590,7 +590,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) up_setusartint(priv, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/arm/src/stm32f7/CMakeLists.txt b/arch/arm/src/stm32f7/CMakeLists.txt index a0b7e4262fe8b..5b677a6d12759 100644 --- a/arch/arm/src/stm32f7/CMakeLists.txt +++ b/arch/arm/src/stm32f7/CMakeLists.txt @@ -33,8 +33,7 @@ list( stm32_start.c stm32_capture.c stm32_uid.c - stm32_waste.c -) + stm32_waste.c) if(CONFIG_STM32F7_TICKLESS_TIMER) list(APPEND SRCS stm32_tickless.c) @@ -94,6 +93,10 @@ if(CONFIG_STM32F7_I2C) list(APPEND SRCS stm32_i2c.c) endif() +if(CONFIG_STM32F7_I2S) + list(APPEND SRCS stm32_i2s.c) +endif() + if(CONFIG_STM32F7_SPI) list(APPEND SRCS stm32_spi.c) endif() @@ -110,9 +113,9 @@ if(CONFIG_USBHOST) list(APPEND SRCS stm32_otghost.c) if(CONFIG_USBHOST_TRACE) list(APPEND SRCS stm32_usbhost.c) - elseif(CONFIG_DEBUG_USB) - list(APPEND SRCS stm32_usbhost.c) - endif() + elseif(CONFIG_DEBUG_USB) + list(APPEND SRCS stm32_usbhost.c) + endif() endif() if(CONFIG_STM32F7_TIM) diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index f25b9e706b6e3..d80662fbf005a 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -1214,6 +1214,11 @@ config STM32F7_HAVE_EXTERNAL_ULPI bool default n +config STM32F7_I2S + bool + default n + select STM32F7_SPI_DMA + config STM32F7_HAVE_SAI1 bool default n @@ -1499,6 +1504,24 @@ config STM32F7_RNG depends on STM32F7_HAVE_RNG select ARCH_HAVE_RNG +config STM32F7_I2S1 + bool "I2S1" + default n + depends on !STM32F7_SPI1 + select STM32F7_I2S + +config STM32F7_I2S2 + bool "I2S2" + default n + depends on !STM32F7_SPI2 + select STM32F7_I2S + +config STM32F7_I2S3 + bool "I2S3" + default n + depends on !STM32F7_SPI3 + select STM32F7_I2S + config STM32F7_SAI1 bool "SAI1" default n @@ -2429,6 +2452,131 @@ config STM32F7_SPI6_DMA_BUFFER endmenu # "SPI Configuration" +menu "I2S Configuration" + depends on STM32F7_I2S + +config STM32F7_I2S_MAXINFLIGHT + int "I2S queue size" + default 16 + ---help--- + This is the total number of transfers, both RX and TX, that can be + enqueue before the caller is required to wait. This setting + determines the number certain queue data structures that will be + pre-allocated. + +if STM32F7_I2S1 + +comment "I2S1 Configuration" + +config STM32F7_I2S1_MCK + bool "I2S1_MCK" + default n + ---help--- + TBD. + +config STM32F7_I2S1_RX + bool "Enable I2S1 receiver" + default n + ---help--- + Enable I2S receipt logic + +config STM32F7_I2S1_TX + bool "Enable I2S1 transmitter" + default n + ---help--- + Enable I2S transmission logic + +config STM32F7_I2S1_DATALEN + int "I2S1 Data width (bits)" + default 16 + ---help--- + Data width in bits. This is a default value and may be change + via the I2S interface + +endif #STM32F7_I2S1 + +if STM32F7_I2S2 + +comment "I2S2 Configuration" + +config STM32F7_I2S2_MCK + bool "I2S2_MCK" + default n + ---help--- + TBD. + +config STM32F7_I2S2_RX + bool "Enable I2S2 receiver" + default n + ---help--- + Enable I2S receipt logic + +config STM32F7_I2S2_TX + bool "Enable I2S2 transmitter" + default n + ---help--- + Enable I2S transmission logic + +config STM32F7_I2S2_DATALEN + int "I2S2 Data width (bits)" + default 16 + ---help--- + Data width in bits. This is a default value and may be change + via the I2S interface + +endif #STM32F7_I2S2 + +if STM32F7_I2S3 + +comment "I2S3 Configuration" + +config STM32F7_I2S3_MCK + bool "I2S3_MCK" + default n + ---help--- + TBD. + +config STM32F7_I2S3_RX + bool "Enable I2S3 receiver" + default n + ---help--- + Enable I2S receipt logic + +config STM32F7_I2S3_TX + bool "Enable I2S3 transmitter" + default n + ---help--- + Enable I2S transmission logic + +config STM32_I2S3_DATALEN + int "I2S3 Data width (bits)" + default 16 + ---help--- + Data width in bits. This is a default value and may be change + via the I2S interface + +endif #STM32F7_I2S3 + +config STM32F7_I2S_DMADEBUG + bool "I2S DMA transfer debug" + depends on DEBUG_DMA + default n + ---help--- + Enable special debug instrumentation analyze I2S DMA data transfers. + This logic is as non-invasive as possible: It samples DMA + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. + +config STM32_I2S_REGDEBUG + bool "SSC Register level debug" + depends on DEBUG + default n + ---help--- + Output detailed register-level SSC device debug information. + Very invasive! Requires also DEBUG. + +endmenu # I2S Configuration + menu "I2C Configuration" depends on STM32F7_I2C diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index 531a04e9b6f0a..c027b65b914dc 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -93,6 +93,10 @@ ifeq ($(CONFIG_STM32F7_I2C),y) CHIP_CSRCS += stm32_i2c.c endif +ifeq ($(CONFIG_STM32F7_I2S),y) +CHIP_CSRCS += stm32_i2s.c +endif + ifeq ($(CONFIG_STM32F7_SPI),y) CHIP_CSRCS += stm32_spi.c endif diff --git a/arch/arm/src/stm32f7/stm32_foc.c b/arch/arm/src/stm32f7/stm32_foc.c index f644bd370ead1..0e6cdfa0ae93a 100644 --- a/arch/arm/src/stm32f7/stm32_foc.c +++ b/arch/arm/src/stm32f7/stm32_foc.c @@ -718,6 +718,7 @@ static struct foc_lower_ops_s g_stm32_foc_ops = .start = stm32_foc_start, .pwm_duty_set = stm32_foc_pwm_duty_set, .pwm_off = stm32_foc_pwm_off, + .info_get = stm32_foc_info_get, .ioctl = stm32_foc_ioctl, .bind = stm32_foc_bind, .fault_clear = stm32_foc_fault_clear, diff --git a/arch/arm/src/stm32f7/stm32_i2s.c b/arch/arm/src/stm32f7/stm32_i2s.c new file mode 100644 index 0000000000000..ae589abc3033f --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_i2s.c @@ -0,0 +1,2737 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32_i2s.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * up_spiinitialize()) are provided by common STM32 logic. To use this + * common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure I2S chip + * select pins. + * 2. Provide stm32_i2s2/3select() and stm32_i2s2/3status() functions in + * your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board + * is configured. + * 3. Add a calls to up_spiinitialize() in your low level application + * initialization logic + * 4. The handle returned by stm32_i2sbus_initialize() may then be used to + * bind the I2S driver to higher level logic + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "stm32_dma.h" +#include "stm32_gpio.h" +#include "stm32_spi.h" +#include "stm32_rcc.h" + +#if defined(CONFIG_STM32F7_I2S1) || defined(CONFIG_STM32F7_I2S2) || defined(CONFIG_STM32F7_I2S3) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SCHED_WORKQUEUE +# error Work queue support is required (CONFIG_SCHED_WORKQUEUE) +#endif + +#ifndef CONFIG_AUDIO +# error CONFIG_AUDIO required by this driver +#endif + +#ifndef CONFIG_STM32F7_I2S_MAXINFLIGHT +# define CONFIG_STM32F7_I2S_MAXINFLIGHT 16 +#endif + +/* Assume no RX/TX support until we learn better */ + +#undef I2S_HAVE_RX +#undef I2S_HAVE_TX + +/* Check for I2S RX support */ + +# if defined(CONFIG_STM32F7_I2S1_RX) +# define I2S_HAVE_RX 1 + +# ifdef CONFIG_STM32F7_I2S1_MCK +# define I2S_HAVE_MCK 1 +# endif + +# endif + +# if defined(CONFIG_STM32F7_I2S2_RX) +# define I2S_HAVE_RX 1 + +# ifdef CONFIG_STM32F7_I2S2_MCK +# define I2S_HAVE_MCK 1 +# endif + +# endif + +# if defined(CONFIG_STM32F7_I2S3_RX) +# define I2S_HAVE_RX 1 + +# ifdef CONFIG_STM32F7_I2S3_MCK +# define I2S_HAVE_MCK 1 +# endif + +# endif + +/* Check for I2S3 TX support */ + +# if defined(CONFIG_STM32F7_I2S1_TX) +# define I2S_HAVE_TX 1 + +# ifdef CONFIG_STM32F7_I2S1_MCK +# define I2S_HAVE_MCK 1 +# endif + +# endif + +# if defined(CONFIG_STM32F7_I2S2_TX) +# define I2S_HAVE_TX 1 + +# ifdef CONFIG_STM32F7_I2S2_MCK +# define I2S_HAVE_MCK 1 +# endif + +# endif + +# if defined(CONFIG_STM32F7_I2S3_TX) +# define I2S_HAVE_TX 1 + +# ifdef CONFIG_STM32F7_I2S3_MCK +# define I2S_HAVE_MCK 1 +# endif + +# endif + +/* Configuration ************************************************************/ + +/* I2S interrupts */ + +#ifdef CONFIG_STM32F7_SPI_INTERRUPTS +# error "Interrupt driven I2S not yet supported" +#endif + +/* Can't have both interrupt driven SPI and SPI DMA */ + +#if defined(CONFIG_STM32F7_SPI_INTERRUPTS) && defined(CONFIG_STM32F7_SPI_DMA) +# error "Cannot enable both interrupt mode and DMA mode for SPI" +#endif + +/* SPI DMA priority */ + +#ifdef CONFIG_STM32F7_SPI_DMA + +# if defined(CONFIG_SPI_DMAPRIO) +# define SPI_DMA_PRIO CONFIG_SPI_DMAPRIO +# elif defined(DMA_SCR_PRIMED) +# define SPI_DMA_PRIO DMA_SCR_PRILO +# else +# error "Unknown STM32 DMA" +# endif + +# if (SPI_DMA_PRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_SPI_DMAPRIO" +# endif + +/* DMA channel configuration */ + +# define SPI_RXDMA16_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_P2M) +# define SPI_RXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_P2M) +# define SPI_RXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_P2M) +# define SPI_RXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_DIR_P2M) +# define SPI_TXDMA16_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_16BITS|DMA_SCR_PSIZE_16BITS|DMA_SCR_MINC|DMA_SCR_DIR_M2P) +# define SPI_TXDMA8_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_MINC|DMA_SCR_DIR_M2P) +# define SPI_TXDMA16NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_16BITS |DMA_SCR_DIR_M2P) +# define SPI_TXDMA8NULL_CONFIG (SPI_DMA_PRIO|DMA_SCR_MSIZE_8BITS |DMA_SCR_PSIZE_8BITS |DMA_SCR_DIR_M2P) + +#endif /* CONFIG_STM32F7_SPI_DMA */ + +/* Debug ********************************************************************/ + +/* Check if SSC debug is enabled (non-standard.. no support in + * include/debug.h + */ + +#ifndef CONFIG_DEBUG_I2S_INFO +# undef CONFIG_STM32F7_I2S_DMADEBUG +# undef CONFIG_STM32F7_I2S_REGDEBUG +# undef CONFIG_STM32F7_I2S_QDEBUG +# undef CONFIG_STM32F7_I2S_DUMPBUFFERS +#endif + +/* The I2S can handle most any bit width from 8 to 32. However, the DMA + * logic here is constrained to byte, half-word, and word sizes. + */ + +#ifndef CONFIG_STM32F7_I2S1_DATALEN +# define CONFIG_STM32F7_I2S1_DATALEN 16 +#endif + +#ifndef CONFIG_STM32F7_I2S2_DATALEN +# define CONFIG_STM32F7_I2S2_DATALEN 16 +#endif + +#ifndef CONFIG_STM32F7_I2S3_DATALEN +# define CONFIG_STM32F7_I2S3_DATALEN 16 +#endif + +#if CONFIG_STM32F7_I2S1_DATALEN == 8 +# define STM32F7_I2S1_DATAMASK 0 +#elif CONFIG_STM32F7_I2S1_DATALEN == 16 +# define STM32F7_I2S1_DATAMASK 1 +#elif CONFIG_STM32F7_I2S1_DATALEN < 8 || CONFIG_STM32F7_I2S1_DATALEN > 16 +# error Invalid value for CONFIG_STM32F7_I2S1_DATALEN +#else +# error Valid but supported value for CONFIG_STM32F7_I2S1_DATALEN +#endif + +#if CONFIG_STM32F7_I2S2_DATALEN == 8 +# define STM32F7_I2S2_DATAMASK 0 +#elif CONFIG_STM32F7_I2S2_DATALEN == 16 +# define STM32F7_I2S2_DATAMASK 1 +#elif CONFIG_STM32F7_I2S2_DATALEN < 8 || CONFIG_STM32F7_I2S2_DATALEN > 16 +# error Invalid value for CONFIG_STM32F7_I2S2_DATALEN +#else +# error Valid but supported value for CONFIG_STM32F7_I2S1_DATALEN +#endif + +#if CONFIG_STM32F7_I2S3_DATALEN == 8 +# define STM32F7_I2S3_DATAMASK 0 +#elif CONFIG_STM32F7_I2S3_DATALEN == 16 +# define STM32F7_I2S3_DATAMASK 1 +#elif CONFIG_STM32F7_I2S3_DATALEN < 8 || CONFIG_STM32F7_I2S3_DATALEN > 16 +# error Invalid value for CONFIG_STM32F7_I2S3_DATALEN +#else +# error Valid but supported value for CONFIG_STM32F7_I2S3_DATALEN +#endif + +/* Check if we need to build RX and/or TX support */ + +#if defined(I2S_HAVE_RX) || defined(I2S_HAVE_TX) + +#ifndef CONFIG_DEBUG_DMA +# undef CONFIG_STM32F7_I2S_DMADEBUG +#endif + +#define DMA_INITIAL 0 +#define DMA_AFTER_SETUP 1 +#define DMA_AFTER_START 2 +#define DMA_CALLBACK 3 +#define DMA_TIMEOUT 3 +#define DMA_END_TRANSFER 4 +#define DMA_NSAMPLES 5 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* I2S buffer container */ + +struct stm32_buffer_s +{ + struct stm32_buffer_s *flink; /* Supports a singly linked list */ + i2s_callback_t callback; /* Function to call when the transfer + * completes */ + uint32_t timeout; /* The timeout value to use with DMA + * transfers */ + void *arg; /* The argument to be returned with the + * callback */ + struct ap_buffer_s *apb; /* The audio buffer */ + int result; /* The result of the transfer */ +}; + +/* This structure describes the state of one receiver or transmitter + * transport. + */ + +struct stm32_transport_s +{ + DMA_HANDLE dma; /* I2S DMA handle */ + struct wdog_s dog; /* Watchdog that handles DMA timeouts */ + sq_queue_t pend; /* A queue of pending transfers */ + sq_queue_t act; /* A queue of active transfers */ + sq_queue_t done; /* A queue of completed transfers */ + struct work_s work; /* Supports worker thread operations */ + +#ifdef CONFIG_STM32F7_I2S_DMADEBUG + struct stm32_dmaregs_s dmaregs[DMA_NSAMPLES]; +#endif +}; + +/* The state of the one I2S peripheral */ + +struct stm32_i2s_s +{ + struct i2s_dev_s dev; /* Externally visible I2S interface */ + uintptr_t base; /* I2S controller register base address */ + mutex_t lock; /* Assures mutually exclusive access to I2S */ + bool initialized; /* Has I2S interface been initialized */ + uint8_t datalen; /* Data width (8 or 16) */ + uint8_t align; /* Log2 of data width (0 or 1) */ + uint8_t rxenab:1; /* True: RX transfers enabled */ + uint8_t txenab:1; /* True: TX transfers enabled */ + uint8_t i2sno:6; /* I2S controller number (0 or 1) */ +#ifdef I2S_HAVE_MCK + uint32_t samplerate; /* Data sample rate (determines only MCK + * divider) */ +#endif + uint32_t rxccr; /* DMA control register for RX transfers */ + uint32_t txccr; /* DMA control register for TX transfers */ +#ifdef I2S_HAVE_RX + struct stm32_transport_s rx; /* RX transport state */ +#endif +#ifdef I2S_HAVE_TX + struct stm32_transport_s tx; /* TX transport state */ +#endif + + /* Pre-allocated pool of buffer containers */ + + sem_t bufsem; /* Buffer wait semaphore */ + struct stm32_buffer_s *freelist; /* A list a free buffer containers */ + struct stm32_buffer_s containers[CONFIG_STM32F7_I2S_MAXINFLIGHT]; + + /* Debug stuff */ + +#ifdef CONFIG_STM32F7_I2S_REGDEBUG + bool wr; /* Last was a write */ + uint32_t regaddr; /* Last address */ + uint16_t regval; /* Last value */ + int count; /* Number of times */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register helpers */ + +#ifdef CONFIG_STM32F7_I2S_REGDEBUG +static bool i2s_checkreg(struct stm32_i2s_s *priv, bool wr, + uint16_t regval, uint32_t regaddr); +#else +# define i2s_checkreg(priv,wr,regval,regaddr) (false) +#endif + +static inline uint16_t i2s_getreg(struct stm32_i2s_s *priv, uint8_t offset); +static inline void i2s_putreg(struct stm32_i2s_s *priv, uint8_t offset, + uint16_t regval); + +#if defined(CONFIG_DEBUG_I2S_INFO) +static void i2s_dump_regs(struct stm32_i2s_s *priv, const char *msg); +#else +# define i2s_dump_regs(s,m) +#endif + +#ifdef CONFIG_STM32F7_I2S_DUMPBUFFERS +# define i2s_init_buffer(b,s) memset(b, 0x55, s); +# define i2s_dump_buffer(m,b,s) lib_dumpbuffer(m,b,s) +#else +# define i2s_init_buffer(b,s) +# define i2s_dump_buffer(m,b,s) +#endif + +/* Buffer container helpers */ + +static struct stm32_buffer_s * + i2s_buf_allocate(struct stm32_i2s_s *priv); +static void i2s_buf_free(struct stm32_i2s_s *priv, + struct stm32_buffer_s *bfcontainer); +static void i2s_buf_initialize(struct stm32_i2s_s *priv); + +/* DMA support */ + +#ifdef CONFIG_STM32F7_I2S_DMADEBUG +static void i2s_dma_sampleinit(struct stm32_i2s_s *priv, + struct stm32_transport_s *xpt); +#endif + +#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_RX) +# define i2s_rxdma_sample(s,i) stm32_dmasample((s)->rx.dma, &(s)->rx.dmaregs[i]) +# define i2s_rxdma_sampleinit(s) i2s_dma_sampleinit(s, &(s)->rx) +static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result); + +#else +# define i2s_rxdma_sample(s,i) +# define i2s_rxdma_sampleinit(s) +# define i2s_rxdma_sampledone(s,r) + +#endif + +#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_TX) +# define i2s_txdma_sample(s,i) stm32_dmasample((s)->tx.dma, &(s)->tx.dmaregs[i]) +# define i2s_txdma_sampleinit(s) i2s_dma_sampleinit(s, &(s)->tx) +static void i2s_txdma_sampledone(struct stm32_i2s_s *priv, int result); + +#else +# define i2s_txdma_sample(s,i) +# define i2s_txdma_sampleinit(s) +# define i2s_txdma_sampledone(s,r) + +#endif + +#ifdef I2S_HAVE_RX +static void i2s_rxdma_timeout(wdparm_t arg); +static int i2s_rxdma_setup(struct stm32_i2s_s *priv); +static void i2s_rx_worker(void *arg); +static void i2s_rx_schedule(struct stm32_i2s_s *priv, int result); +static void i2s_rxdma_callback(DMA_HANDLE handle, uint8_t result, + void *arg); +#endif +#ifdef I2S_HAVE_TX +static void i2s_txdma_timeout(wdparm_t arg); +static int i2s_txdma_setup(struct stm32_i2s_s *priv); +static void i2s_tx_worker(void *arg); +static void i2s_tx_schedule(struct stm32_i2s_s *priv, int result); +static void i2s_txdma_callback(DMA_HANDLE handle, uint8_t result, + void *arg); +#endif + +/* I2S methods (and close friends) */ + +static int i2s_checkwidth(struct stm32_i2s_s *priv, int bits); + +static uint32_t stm32_i2s_rxsamplerate(struct i2s_dev_s *dev, uint32_t rate); +static uint32_t stm32_i2s_rxdatawidth(struct i2s_dev_s *dev, int bits); +static int stm32_i2s_receive(struct i2s_dev_s *dev, + struct ap_buffer_s *apb, + i2s_callback_t callback, + void *arg, uint32_t timeout); +static uint32_t stm32_i2s_txsamplerate(struct i2s_dev_s *dev, uint32_t rate); +static uint32_t stm32_i2s_txdatawidth(struct i2s_dev_s *dev, int bits); +static int stm32_i2s_send(struct i2s_dev_s *dev, + struct ap_buffer_s *apb, + i2s_callback_t callback, void *arg, + uint32_t timeout); + +/* Initialization */ + +static uint32_t i2s_mckdivider(struct stm32_i2s_s *priv); +static int i2s_dma_flags(struct stm32_i2s_s *priv); +static int i2s_dma_allocate(struct stm32_i2s_s *priv); +static void i2s_dma_free(struct stm32_i2s_s *priv); + +#ifdef CONFIG_STM32F7_I2S1 +static void i2s1_configure(struct stm32_i2s_s *priv); +#endif + +#ifdef CONFIG_STM32F7_I2S2 +static void i2s2_configure(struct stm32_i2s_s *priv); +#endif + +#ifdef CONFIG_STM32F7_I2S3 +static void i2s3_configure(struct stm32_i2s_s *priv); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* I2S device operations */ + +static const struct i2s_ops_s g_i2sops = +{ + /* Receiver methods */ + + .i2s_rxsamplerate = stm32_i2s_rxsamplerate, + .i2s_rxdatawidth = stm32_i2s_rxdatawidth, + .i2s_receive = stm32_i2s_receive, + + /* Transmitter methods */ + + .i2s_txsamplerate = stm32_i2s_txsamplerate, + .i2s_txdatawidth = stm32_i2s_txdatawidth, + .i2s_send = stm32_i2s_send, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: i2s_checkreg + * + * Description: + * Check if the current register access is a duplicate of the preceding. + * + * Input Parameters: + * regval - The value to be written + * regaddr - The address of the register to write to + * + * Returned Value: + * true: This is the first register access of this type. + * flase: This is the same as the preceding register access. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32F7_I2S_REGDEBUG +static bool i2s_checkreg(struct stm32_i2s_s *priv, bool wr, uint16_t regval, + uint32_t regaddr) +{ + if (wr == priv->wr && /* Same kind of access? */ + regval == priv->regval && /* Same value? */ + regaddr == priv->regaddr) /* Same address? */ + { + /* Yes, then just keep a count of the number of times we did this. */ + + priv->count++; + return false; + } + else + { + /* Did we do the previous operation more than once? */ + + if (priv->count > 0) + { + /* Yes... show how many times we did it */ + + i2sinfo("...[Repeats %d times]...\n", priv->count); + } + + /* Save information about the new access */ + + priv->wr = wr; + priv->regval = regval; + priv->regaddr = regaddr; + priv->count = 0; + } + + /* Return true if this is the first time that we have done this operation */ + + return true; +} +#endif + +/**************************************************************************** + * Name: i2s_getreg + * + * Description: + * Get the contents of the I2S register at offset + * + * Input Parameters: + * priv - private I2S device structure + * offset - offset to the register of interest + * + * Returned Value: + * The contents of the 16-bit register + * + ****************************************************************************/ + +static inline uint16_t i2s_getreg(struct stm32_i2s_s *priv, + uint8_t offset) +{ + uint32_t regaddr = priv->base + offset; + uint16_t regval = getreg16(regaddr); + +#ifdef CONFIG_STM32F7_I2S_REGDEBUG + if (i2s_checkreg(priv, false, regval, regaddr)) + { + i2sinfo("%08x->%04x\n", regaddr, regval); + } +#endif + + return regval; +} + +/**************************************************************************** + * Name: spi_putreg + * + * Description: + * Write a 16-bit value to the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * value - the 16-bit value to be written + * + * Returned Value: + * The contents of the 16-bit register + * + ****************************************************************************/ + +static inline void i2s_putreg(struct stm32_i2s_s *priv, uint8_t offset, + uint16_t regval) +{ + uint32_t regaddr = priv->base + offset; + +#ifdef CONFIG_STM32F7_I2S_REGDEBUG + if (i2s_checkreg(priv, true, regval, regaddr)) + { + i2sinfo("%08x<-%04x\n", regaddr, regval); + } +#endif + + putreg16(regval, regaddr); +} + +/**************************************************************************** + * Name: i2s_dump_regs + * + * Description: + * Dump the contents of all I2S registers + * + * Input Parameters: + * priv - The I2S controller to dump + * msg - Message to print before the register data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_I2S) +static void i2s_dump_regs(struct stm32_i2s_s *priv, const char *msg) +{ + i2sinfo("I2S%d: %s\n", priv->i2sno, msg); + i2sinfo(" CR1:%04x CR2:%04x SR:%04x DR:%04x\n", + i2s_getreg(priv, STM32_SPI_CR1_OFFSET), + i2s_getreg(priv, STM32_SPI_CR2_OFFSET), + i2s_getreg(priv, STM32_SPI_SR_OFFSET), + i2s_getreg(priv, STM32_SPI_DR_OFFSET)); + i2sinfo(" I2SCFGR:%04x I2SPR:%04x\n", + i2s_getreg(priv, STM32_SPI_I2SCFGR_OFFSET), + i2s_getreg(priv, STM32_SPI_I2SPR_OFFSET)); + i2sinfo(" PLLI2SCFGR:%08x\n", getreg32(STM32_RCC_PLLI2SCFGR)); +} +#endif + +/**************************************************************************** + * Name: i2s_buf_allocate + * + * Description: + * Allocate a buffer container by removing the one at the head of the + * free list + * + * Input Parameters: + * priv - I2S state instance + * + * Returned Value: + * A non-NULL pointer to the allocate buffer container on success; NULL if + * there are no available buffer containers. + * + * Assumptions: + * The caller does NOT have exclusive access to the I2S state structure. + * That would result in a deadlock! + * + ****************************************************************************/ + +static struct stm32_buffer_s *i2s_buf_allocate(struct stm32_i2s_s *priv) +{ + struct stm32_buffer_s *bfcontainer; + irqstate_t flags; + int ret; + + /* Set aside a buffer container. By doing this, we guarantee that we will + * have at least one free buffer container. + */ + + ret = nxsem_wait_uninterruptible(&priv->bufsem); + if (ret < 0) + { + return NULL; + } + + /* Get the buffer from the head of the free list */ + + flags = enter_critical_section(); + bfcontainer = priv->freelist; + DEBUGASSERT(bfcontainer); + + /* Unlink the buffer from the freelist */ + + priv->freelist = bfcontainer->flink; + leave_critical_section(flags); + return bfcontainer; +} + +/**************************************************************************** + * Name: i2s_buf_free + * + * Description: + * Free buffer container by adding it to the head of the free list + * + * Input Parameters: + * priv - I2S state instance + * bfcontainer - The buffer container to be freed + * + * Returned Value: + * None + * + * Assumptions: + * The caller has exclusive access to the I2S state structure + * + ****************************************************************************/ + +static void i2s_buf_free(struct stm32_i2s_s *priv, + struct stm32_buffer_s *bfcontainer) +{ + irqstate_t flags; + + /* Put the buffer container back on the free list */ + + flags = enter_critical_section(); + bfcontainer->flink = priv->freelist; + priv->freelist = bfcontainer; + leave_critical_section(flags); + + /* Wake up any threads waiting for a buffer container */ + + nxsem_post(&priv->bufsem); +} + +/**************************************************************************** + * Name: i2s_buf_initialize + * + * Description: + * Initialize the buffer container allocator by adding all of the + * pre-allocated buffer containers to the free list + * + * Input Parameters: + * priv - I2S state instance + * + * Returned Value: + * None + * + * Assumptions: + * Called early in I2S initialization so that there are no issues with + * concurrency. + * + ****************************************************************************/ + +static void i2s_buf_initialize(struct stm32_i2s_s *priv) +{ + int i; + + priv->freelist = NULL; + nxsem_init(&priv->bufsem, 0, CONFIG_STM32F7_I2S_MAXINFLIGHT); + + for (i = 0; i < CONFIG_STM32F7_I2S_MAXINFLIGHT; i++) + { + i2s_buf_free(priv, &priv->containers[i]); + } +} + +/**************************************************************************** + * Name: i2s_dma_sampleinit + * + * Description: + * Initialize sampling of DMA registers (if CONFIG_STM32F7_I2S_DMADEBUG) + * + * Input Parameters: + * priv - I2S state instance + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32F7_I2S_DMADEBUG) +static void i2s_dma_sampleinit(struct stm32_i2s_s *priv, + struct stm32_transport_s *xpt) +{ + /* Put contents of register samples into a known state */ + + memset(xpt->dmaregs, 0xff, DMA_NSAMPLES * sizeof(struct stm32_dmaregs_s)); + + /* Then get the initial samples */ + + stm32_dmasample(xpt->dma, &xpt->dmaregs[DMA_INITIAL]); +} +#endif + +/**************************************************************************** + * Name: i2s_rxdma_sampledone + * + * Description: + * Dump sampled RX DMA registers + * + * Input Parameters: + * priv - I2S state instance + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_RX) +static void i2s_rxdma_sampledone(struct stm32_i2s_s *priv, int result) +{ + i2sinfo("result: %d\n", result); + + /* Sample the final registers */ + + stm32_dmasample(priv->rx.dma, &priv->rx.dmaregs[DMA_END_TRANSFER]); + + /* Then dump the sampled DMA registers */ + + /* Initial register values */ + + stm32_dmadump(priv->rx.dma, &priv->rx.dmaregs[DMA_INITIAL], + "RX: Initial Registers"); + + /* Register values after DMA setup */ + + stm32_dmadump(priv->rx.dma, &priv->rx.dmaregs[DMA_AFTER_SETUP], + "RX: After DMA Setup"); + + /* Register values after DMA start */ + + stm32_dmadump(priv->rx.dma, &priv->rx.dmaregs[DMA_AFTER_START], + "RX: After DMA Start"); + + /* Register values at the time of the TX and RX DMA callbacks + * -OR- DMA timeout. + * + * If the DMA timedout, then there will not be any RX DMA + * callback samples. There is probably no TX DMA callback + * samples either, but we don't know for sure. + */ + + if (result == -ETIMEDOUT || result == -EINTR) + { + stm32_dmadump(priv->rx.dma, &priv->rx.dmaregs[DMA_TIMEOUT], + "RX: At DMA timeout"); + } + else + { + stm32_dmadump(priv->rx.dma, &priv->rx.dmaregs[DMA_CALLBACK], + "RX: At DMA callback"); + } + + stm32_dmadump(priv->rx.dma, &priv->rx.dmaregs[DMA_END_TRANSFER], + "RX: At End-of-Transfer"); + + i2s_dump_regs(priv, "RX: At End-of-Transfer"); +} +#endif + +/**************************************************************************** + * Name: i2s_txdma_sampledone + * + * Description: + * Dump sampled DMA registers + * + * Input Parameters: + * priv - I2S state instance + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_STM32F7_I2S_DMADEBUG) && defined(I2S_HAVE_TX) +static void i2s_txdma_sampledone(struct stm32_i2s_s *priv, int result) +{ + i2sinfo("result: %d\n", result); + + /* Sample the final registers */ + + stm32_dmasample(priv->tx.dma, &priv->tx.dmaregs[DMA_END_TRANSFER]); + + /* Then dump the sampled DMA registers */ + + /* Initial register values */ + + stm32_dmadump(priv->tx.dma, &priv->tx.dmaregs[DMA_INITIAL], + "TX: Initial Registers"); + + /* Register values after DMA setup */ + + stm32_dmadump(priv->tx.dma, &priv->tx.dmaregs[DMA_AFTER_SETUP], + "TX: After DMA Setup"); + + /* Register values after DMA start */ + + stm32_dmadump(priv->tx.dma, &priv->tx.dmaregs[DMA_AFTER_START], + "TX: After DMA Start"); + + /* Register values at the time of the TX and RX DMA callbacks + * -OR- DMA timeout. + */ + + if (result == -ETIMEDOUT || result == -EINTR) + { + stm32_dmadump(priv->tx.dma, &priv->tx.dmaregs[DMA_TIMEOUT], + "TX: At DMA timeout"); + } + else + { + stm32_dmadump(priv->tx.dma, &priv->tx.dmaregs[DMA_CALLBACK], + "TX: At DMA callback"); + } + + stm32_dmadump(priv->tx.dma, &priv->tx.dmaregs[DMA_END_TRANSFER], + "TX: At End-of-Transfer"); + + i2s_dump_regs(priv, "TX: At End-of-Transfer"); +} +#endif + +/**************************************************************************** + * Name: i2s_rxdma_timeout + * + * Description: + * The RX watchdog timeout without completion of the RX DMA. + * + * Input Parameters: + * arg - The argument + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +#ifdef I2S_HAVE_RX +static void i2s_rxdma_timeout(wdparm_t arg) +{ + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg; + DEBUGASSERT(priv != NULL); + + /* Sample DMA registers at the time of the timeout */ + + i2s_rxdma_sample(priv, DMA_TIMEOUT); + + /* Cancel the DMA */ + + stm32_dmastop(priv->rx.dma); + + /* Then schedule completion of the transfer to occur on the worker thread. + * NOTE: stm32_dmastop() will call the DMA complete callback with an error + * of -EINTR. So the following is just insurance and should have no + * effect if the worker is already schedule. + */ + + i2s_rx_schedule(priv, -ETIMEDOUT); +} +#endif + +/**************************************************************************** + * Name: i2s_rxdma_setup + * + * Description: + * Setup and initiate the next RX DMA transfer + * + * Input Parameters: + * priv - I2S state instance + * + * Returned Value: + * OK on success; a negated errno value on failure + * + * Assumptions: + * Interrupts are disabled + * + ****************************************************************************/ + +#ifdef I2S_HAVE_RX +static int i2s_rxdma_setup(struct stm32_i2s_s *priv) +{ + struct stm32_buffer_s *bfcontainer; + struct ap_buffer_s *apb; + uintptr_t samp; + uint32_t timeout; + bool notimeout; + int ret; + + /* If there is already an active transmission in progress, then bail + * returning success. + */ + + if (!sq_empty(&priv->rx.act)) + { + return OK; + } + + /* If there are no pending transfer, then bail returning success */ + + if (sq_empty(&priv->rx.pend)) + { + return OK; + } + + /* Initialize DMA register sampling */ + + i2s_rxdma_sampleinit(priv); + + /* Loop, adding each pending DMA */ + + timeout = 0; + notimeout = false; + + do + { + /* Remove the pending RX transfer at the head of the RX pending + * queue. + */ + + bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->rx.pend); + DEBUGASSERT(bfcontainer && bfcontainer->apb); + + apb = bfcontainer->apb; + DEBUGASSERT(((uintptr_t)apb->samp % priv->align) == 0); + + /* No data received yet */ + + apb->nbytes = 0; + apb->curbyte = 0; + samp = (uintptr_t)&apb->samp[apb->curbyte]; + + /* Configure the RX DMA */ + + stm32_dmasetup(priv->rx.dma, priv->base + STM32_SPI_DR_OFFSET, + (uint32_t)samp, apb->nmaxbytes, priv->rxccr); + + /* Increment the DMA timeout */ + + if (bfcontainer->timeout > 0) + { + timeout += bfcontainer->timeout; + } + else + { + notimeout = true; + } + + /* Add the container to the list of active DMAs */ + + sq_addlast((sq_entry_t *)bfcontainer, &priv->rx.act); + } +#if 1 /* REVISIT: Chained RX transfers */ + while (0); +#else + while (!sq_empty(&priv->rx.pend)); +#endif + + /* Sample DMA registers */ + + i2s_rxdma_sample(priv, DMA_AFTER_SETUP); + + /* Start the DMA, saving the container as the current active transfer */ + + stm32_dmastart(priv->rx.dma, i2s_rxdma_callback, priv, false); + + i2s_rxdma_sample(priv, DMA_AFTER_START); + + /* Enable the receiver */ + + i2s_putreg(priv, STM32_SPI_CR2_OFFSET, + i2s_getreg(priv, STM32_SPI_CR2_OFFSET) | SPI_CR2_RXDMAEN); + + /* Start a watchdog to catch DMA timeouts */ + + if (!notimeout) + { + ret = wd_start(&priv->rx.dog, timeout, + i2s_rxdma_timeout, (wdparm_t)priv); + + /* Check if we have successfully started the watchdog timer. Note + * that we do nothing in the case of failure to start the timer. We + * are already committed to the DMA anyway. Let's just hope that the + * DMA does not hang. + */ + + if (ret < 0) + { + i2serr("ERROR: wd_start failed: %d\n", ret); + } + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: i2s_rx_worker + * + * Description: + * RX transfer done worker + * + * Input Parameters: + * arg - the I2S device instance cast to void* + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef I2S_HAVE_RX +static void i2s_rx_worker(void *arg) +{ + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg; + struct stm32_buffer_s *bfcontainer; + struct ap_buffer_s *apb; + irqstate_t flags; + + DEBUGASSERT(priv); + + /* When the transfer was started, the active buffer containers were removed + * from the rx.pend queue and saved in the rx.act queue. We get here when + * the DMA is finished... either successfully, with a DMA error, or with a + * DMA timeout. + * + * In any case, the buffer containers in rx.act will be moved to the end + * of the rx.done queue and rx.act queue will be emptied before this worker + * is started. + * + * REVISIT: Normal DMA callback processing should restart the DMA + * immediately to avoid audio artifacts at the boundaries between DMA + * transfers. Unfortunately, the DMA callback occurs at the interrupt + * level and we cannot call dma_rxsetup() from the interrupt level. + * So we have to start the next DMA here. + */ + + i2sinfo("rx.act.head=%p rx.done.head=%p\n", + priv->rx.act.head, priv->rx.done.head); + + /* Check if the DMA is IDLE */ + + if (sq_empty(&priv->rx.act)) + { +#ifdef CONFIG_STM32F7_I2S_DMADEBUG + bfcontainer = (struct stm32_buffer_s *)sq_peek(&priv->rx.done); + if (bfcontainer) + { + /* Dump the DMA registers */ + + i2s_rxdma_sampledone(priv, bfcontainer->result); + } +#endif + + /* Then start the next DMA. This must be done with interrupts + * disabled. + */ + + flags = enter_critical_section(); + i2s_rxdma_setup(priv); + leave_critical_section(flags); + } + + /* Process each buffer in the rx.done queue */ + + while (sq_peek(&priv->rx.done) != NULL) + { + /* Remove the buffer container from the rx.done queue. NOTE that + * interrupts must be enabled to do this because the rx.done queue is + * also modified from the interrupt level. + */ + + flags = enter_critical_section(); + bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->rx.done); + leave_critical_section(flags); + + DEBUGASSERT(bfcontainer && bfcontainer->apb && bfcontainer->callback); + apb = bfcontainer->apb; + + /* If the DMA was successful, then update the number of valid bytes in + * the audio buffer. + */ + + if (bfcontainer->result == OK) + { + apb->nbytes = apb->nmaxbytes; + } + + i2s_dump_buffer("Received", apb->samp, apb->nbytes); + + /* Perform the RX transfer done callback */ + + bfcontainer->callback(&priv->dev, apb, bfcontainer->arg, + bfcontainer->result); + + /* Release our reference on the audio buffer. This may very likely + * cause the audio buffer to be freed. + */ + + apb_free(apb); + + /* And release the buffer container */ + + i2s_buf_free(priv, bfcontainer); + } +} +#endif + +/**************************************************************************** + * Name: i2s_rx_schedule + * + * Description: + * An RX DMA completion or timeout has occurred. Schedule processing on + * the working thread. + * + * Input Parameters: + * handle - The DMA handler + * arg - A pointer to the chip select struction + * result - The result of the DMA transfer + * + * Returned Value: + * None + * + * Assumptions: + * Interrupts are disabled + * + ****************************************************************************/ + +#ifdef I2S_HAVE_RX +static void i2s_rx_schedule(struct stm32_i2s_s *priv, int result) +{ + struct stm32_buffer_s *bfcontainer; + int ret; + + /* Upon entry, the transfer(s) that just completed are the ones in the + * priv->rx.act queue. NOTE: In certain conditions, this function may + * be called an additional time, hence, we can't assert this to be true. + * For example, in the case of a timeout, this function will be called by + * both indirectly via the stm32_dmastop() logic and directly via the + * i2s_rxdma_timeout() logic. + */ + + /* Move all entries from the rx.act queue to the rx.done queue */ + + while (!sq_empty(&priv->rx.act)) + { + /* Remove the next buffer container from the rx.act list */ + + bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->rx.act); + + /* Report the result of the transfer */ + + bfcontainer->result = result; + + /* Add the completed buffer container to the tail of the rx.done + * queue + */ + + sq_addlast((sq_entry_t *)bfcontainer, &priv->rx.done); + } + + /* If the worker has completed running, then reschedule the working thread. + * REVISIT: There may be a race condition here. So we do nothing is the + * worker is not available. + */ + + if (work_available(&priv->rx.work)) + { + /* Schedule the TX DMA done processing to occur on the worker thread. */ + + ret = work_queue(HPWORK, &priv->rx.work, i2s_rx_worker, priv, 0); + if (ret != 0) + { + i2serr("ERROR: Failed to queue RX work: %d\n", ret); + } + } +} +#endif + +/**************************************************************************** + * Name: i2s_rxdma_callback + * + * Description: + * This callback function is invoked at the completion of the I2S RX DMA. + * + * Input Parameters: + * handle - The DMA handler + * arg - A pointer to the chip select struction + * result - The result of the DMA transfer + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef I2S_HAVE_RX +static void i2s_rxdma_callback(DMA_HANDLE handle, uint8_t result, void *arg) +{ + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg; + DEBUGASSERT(priv != NULL); + + /* Cancel the watchdog timeout */ + + wd_cancel(&priv->rx.dog); + + /* Sample DMA registers at the time of the DMA completion */ + + i2s_rxdma_sample(priv, DMA_CALLBACK); + + /* REVISIT: We would like to the next DMA started here so that we do not + * get audio glitches at the boundaries between DMA transfers. + * Unfortunately, we cannot call stm32_dmasetup() from an interrupt + * handler! + */ + + /* Then schedule completion of the transfer to occur on the worker thread */ + + i2s_rx_schedule(priv, result); +} +#endif + +/**************************************************************************** + * Name: i2s_txdma_timeout + * + * Description: + * The RX watchdog timeout without completion of the RX DMA. + * + * Input Parameters: + * arg - The argument + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +#ifdef I2S_HAVE_TX +static void i2s_txdma_timeout(wdparm_t arg) +{ + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg; + DEBUGASSERT(priv != NULL); + + /* Sample DMA registers at the time of the timeout */ + + i2s_txdma_sample(priv, DMA_TIMEOUT); + + /* Cancel the DMA */ + + stm32_dmastop(priv->tx.dma); + + /* Then schedule completion of the transfer to occur on the worker thread. + * NOTE: stm32_dmastop() will call the DMA complete callback with an error + * of -EINTR. So the following is just insurance and should have no + * effect if the worker is already schedule. + */ + + i2s_tx_schedule(priv, -ETIMEDOUT); +} +#endif + +/**************************************************************************** + * Name: i2s_txdma_setup + * + * Description: + * Setup and initiate the next TX DMA transfer + * + * Input Parameters: + * priv - I2S state instance + * + * Returned Value: + * OK on success; a negated errno value on failure + * + * Assumptions: + * Interrupts are disabled + * + ****************************************************************************/ + +#ifdef I2S_HAVE_TX +static int i2s_txdma_setup(struct stm32_i2s_s *priv) +{ + struct stm32_buffer_s *bfcontainer; + struct ap_buffer_s *apb; + uintptr_t samp; + uint32_t timeout; + apb_samp_t nbytes; + bool notimeout; + int ret; + + /* If there is already an active transmission in progress, then bail + * returning success. + */ + + if (!sq_empty(&priv->tx.act)) + { + return OK; + } + + /* If there are no pending transfer, then bail returning success */ + + if (sq_empty(&priv->tx.pend)) + { + return OK; + } + + /* Initialize DMA register sampling */ + + i2s_txdma_sampleinit(priv); + + /* Loop, adding each pending DMA */ + + timeout = 0; + notimeout = false; + + do + { + /* Remove the pending TX transfer at the head of the TX pending + * queue. + */ + + bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->tx.pend); + DEBUGASSERT(bfcontainer && bfcontainer->apb); + + apb = bfcontainer->apb; + + /* Get the transfer information, accounting for any data offset */ + + samp = (uintptr_t)&apb->samp[apb->curbyte]; + nbytes = apb->nbytes - apb->curbyte; + DEBUGASSERT((samp & priv->align) == 0 && (nbytes & priv->align) == 0); + + /* Configure DMA stream */ + + stm32_dmasetup(priv->tx.dma, priv->base + STM32_SPI_DR_OFFSET, + (uint32_t)samp, nbytes / 2, priv->txccr); + + /* Increment the DMA timeout */ + + if (bfcontainer->timeout > 0) + { + timeout += bfcontainer->timeout; + } + else + { + notimeout = true; + } + + /* Add the container to the list of active DMAs */ + + sq_addlast((sq_entry_t *)bfcontainer, &priv->tx.act); + } +#if 1 /* REVISIT: Chained TX transfers */ + while (0); +#else + while (!sq_empty(&priv->tx.pend)); +#endif + + /* Sample DMA registers */ + + i2s_txdma_sample(priv, DMA_AFTER_SETUP); + + /* Start the DMA, saving the container as the current active transfer */ + + stm32_dmastart(priv->tx.dma, i2s_txdma_callback, priv, true); + + i2s_txdma_sample(priv, DMA_AFTER_START); + + /* Enable the transmitter */ + + i2s_putreg(priv, STM32_SPI_CR2_OFFSET, + i2s_getreg(priv, STM32_SPI_CR2_OFFSET) | SPI_CR2_TXDMAEN); + + /* Start a watchdog to catch DMA timeouts */ + + if (!notimeout) + { + ret = wd_start(&priv->tx.dog, timeout, + i2s_txdma_timeout, (wdparm_t)priv); + + /* Check if we have successfully started the watchdog timer. Note + * that we do nothing in the case of failure to start the timer. We + * are already committed to the DMA anyway. Let's just hope that the + * DMA does not hang. + */ + + if (ret < 0) + { + i2serr("ERROR: wd_start failed: %d\n", ret); + } + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: i2s_tx_worker + * + * Description: + * TX transfer done worker + * + * Input Parameters: + * arg - the I2S device instance cast to void* + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef I2S_HAVE_TX +static void i2s_tx_worker(void *arg) +{ + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg; + struct stm32_buffer_s *bfcontainer; + irqstate_t flags; + + DEBUGASSERT(priv); + + /* When the transfer was started, the active buffer containers were removed + * from the tx.pend queue and saved in the tx.act queue. We get here when + * the DMA is finished... either successfully, with a DMA error, or with a + * DMA timeout. + * + * In any case, the buffer containers in tx.act will be moved to the end + * of the tx.done queue and tx.act will be emptied before this worker is + * started. + * + * REVISIT: Normal DMA callback processing should restart the DMA + * immediately to avoid audio artifacts at the boundaries between DMA + * transfers. Unfortunately, the DMA callback occurs at the interrupt + * level and we cannot call dma_txsetup() from the interrupt level. + * So we have to start the next DMA here. + */ + + i2sinfo("tx.act.head=%p tx.done.head=%p\n", + priv->tx.act.head, priv->tx.done.head); + + /* Check if the DMA is IDLE */ + + if (sq_empty(&priv->tx.act)) + { +#ifdef CONFIG_STM32F7_I2S_DMADEBUG + bfcontainer = (struct stm32_buffer_s *)sq_peek(&priv->tx.done); + if (bfcontainer) + { + /* Dump the DMA registers */ + + i2s_txdma_sampledone(priv, bfcontainer->result); + } +#endif + + /* Then start the next DMA. This must be done with interrupts + * disabled. + */ + + flags = enter_critical_section(); + i2s_txdma_setup(priv); + leave_critical_section(flags); + } + + /* Process each buffer in the tx.done queue */ + + while (sq_peek(&priv->tx.done) != NULL) + { + /* Remove the buffer container from the tx.done queue. NOTE that + * interrupts must be enabled to do this because the tx.done queue is + * also modified from the interrupt level. + */ + + flags = enter_critical_section(); + bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->tx.done); + leave_critical_section(flags); + + /* Perform the TX transfer done callback */ + + DEBUGASSERT(bfcontainer && bfcontainer->callback); + bfcontainer->callback(&priv->dev, bfcontainer->apb, + bfcontainer->arg, bfcontainer->result); + + /* Release our reference on the audio buffer. This may very likely + * cause the audio buffer to be freed. + */ + + apb_free(bfcontainer->apb); + + /* And release the buffer container */ + + i2s_buf_free(priv, bfcontainer); + } +} +#endif + +/**************************************************************************** + * Name: i2s_tx_schedule + * + * Description: + * An TX DMA completion or timeout has occurred. Schedule processing on + * the working thread. + * + * Input Parameters: + * handle - The DMA handler + * arg - A pointer to the chip select struction + * result - The result of the DMA transfer + * + * Returned Value: + * None + * + * Assumptions: + * - Interrupts are disabled + * - The TX timeout has been canceled. + * + ****************************************************************************/ + +#ifdef I2S_HAVE_TX +static void i2s_tx_schedule(struct stm32_i2s_s *priv, int result) +{ + struct stm32_buffer_s *bfcontainer; + int ret; + + /* Upon entry, the transfer(s) that just completed are the ones in the + * priv->tx.act queue. NOTE: In certain conditions, this function may + * be called an additional time, hence, we can't assert this to be true. + * For example, in the case of a timeout, this function will be called by + * both indirectly via the stm32_dmastop() logic and directly via the + * i2s_txdma_timeout() logic. + */ + + /* Move all entries from the tx.act queue to the tx.done queue */ + + while (!sq_empty(&priv->tx.act)) + { + /* Remove the next buffer container from the tx.act list */ + + bfcontainer = (struct stm32_buffer_s *)sq_remfirst(&priv->tx.act); + + /* Report the result of the transfer */ + + bfcontainer->result = result; + + /* Add the completed buffer container to the tail of the tx.done + * queue + */ + + sq_addlast((sq_entry_t *)bfcontainer, &priv->tx.done); + } + + /* If the worker has completed running, then reschedule the working thread. + * REVISIT: There may be a race condition here. So we do nothing is the + * worker is not available. + */ + + if (work_available(&priv->tx.work)) + { + /* Schedule the TX DMA done processing to occur on the worker thread. */ + + ret = work_queue(HPWORK, &priv->tx.work, i2s_tx_worker, priv, 0); + if (ret != 0) + { + i2serr("ERROR: Failed to queue TX work: %d\n", ret); + } + } +} +#endif + +/**************************************************************************** + * Name: i2s_txdma_callback + * + * Description: + * This callback function is invoked at the completion of the I2S TX DMA. + * + * Input Parameters: + * handle - The DMA handler + * arg - A pointer to the chip select struction + * result - The result of the DMA transfer + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef I2S_HAVE_TX +static void i2s_txdma_callback(DMA_HANDLE handle, uint8_t result, void *arg) +{ + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)arg; + DEBUGASSERT(priv != NULL); + + /* Cancel the watchdog timeout */ + + wd_cancel(&priv->tx.dog); + + /* Sample DMA registers at the time of the DMA completion */ + + i2s_txdma_sample(priv, DMA_CALLBACK); + + /* REVISIT: We would like to the next DMA started here so that we do not + * get audio glitches at the boundaries between DMA transfers. + * Unfortunately, we cannot call stm32_dmasetup() from an interrupt + * handler! + */ + + /* Then schedule completion of the transfer to occur on the worker thread */ + + i2s_tx_schedule(priv, result); +} +#endif + +/**************************************************************************** + * Name: i2s_checkwidth + * + * Description: + * Check for a valid bit width. The I2S is capable of handling most any + * bit width from 8 to 16, but the DMA logic in this driver is constrained + * to 8- and 16-bit data widths + * + * Input Parameters: + * dev - Device-specific state data + * rate - The I2S sample rate in samples (not bits) per second + * + * Returned Value: + * Returns the resulting bitrate + * + ****************************************************************************/ + +static int i2s_checkwidth(struct stm32_i2s_s *priv, int bits) +{ + /* The I2S can handle most any bit width from 8 to 32. However, the DMA + * logic here is constrained to byte, half-word, and word sizes. + */ + + switch (bits) + { + case 8: + priv->align = 0; + break; + + case 16: + priv->align = 1; + break; + + default: + i2serr("ERROR: Unsupported or invalid data width: %d\n", bits); + return (bits < 8 || bits > 16) ? -EINVAL : -ENOSYS; + } + + /* Save the new data width */ + + priv->datalen = bits; + return OK; +} + +/**************************************************************************** + * Name: stm32_i2s_rxsamplerate + * + * Description: + * Set the I2S RX sample rate. NOTE: This will have no effect if (1) the + * driver does not support an I2C receiver or if (2) the sample rate is + * driven by the I2S frame clock. This may also have unexpected side- + * effects of the RX sample is coupled with the TX sample rate. + * + * Input Parameters: + * dev - Device-specific state data + * rate - The I2S sample rate in samples (not bits) per second + * + * Returned Value: + * Returns the resulting bitrate + * + ****************************************************************************/ + +static uint32_t stm32_i2s_rxsamplerate(struct i2s_dev_s *dev, uint32_t rate) +{ +#if defined(I2S_HAVE_RX) && defined(I2S_HAVE_MCK) + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev; + DEBUGASSERT(priv && priv->samplerate >= 0 && rate > 0); + + /* Check if the receiver is driven by the MCK */ + + if (priv->samplerate != rate) + { + /* Save the new sample rate and update the MCK divider */ + + priv->samplerate = rate; + return i2s_mckdivider(priv); + } +#endif + + return 0; +} + +/**************************************************************************** + * Name: stm32_i2s_rxdatawidth + * + * Description: + * Set the I2S RX data width. The RX bitrate is determined by + * sample_rate * data_width. + * + * Input Parameters: + * dev - Device-specific state data + * width - The I2S data with in bits. + * + * Returned Value: + * Returns the resulting bitrate + * + ****************************************************************************/ + +static uint32_t stm32_i2s_rxdatawidth(struct i2s_dev_s *dev, int bits) +{ +#ifdef I2S_HAVE_RX + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev; + int ret; + + DEBUGASSERT(priv && bits > 1); + + /* Check if this is a bit width that we are configured to handle */ + + ret = i2s_checkwidth(priv, bits); + if (ret < 0) + { + i2serr("ERROR: i2s_checkwidth failed: %d\n", ret); + return 0; + } + + /* Update the DMA flags */ + + ret = i2s_dma_flags(priv); + if (ret < 0) + { + i2serr("ERROR: i2s_dma_flags failed: %d\n", ret); + return 0; + } + +#endif + + return 0; +} + +/**************************************************************************** + * Name: stm32_i2s_receive + * + * Description: + * Receive a block of data from I2S. + * + * Input Parameters: + * dev - Device-specific state data + * apb - A pointer to the audio buffer in which to receive data + * callback - A user provided callback function that will be called at + * the completion of the transfer. The callback will be + * performed in the context of the worker thread. + * arg - An opaque argument that will be provided to the callback + * when the transfer complete + * timeout - The timeout value to use. The transfer will be canceled + * and an ETIMEDOUT error will be reported if this timeout + * elapsed without completion of the DMA transfer. Units + * are system clock ticks. Zero means no timeout. + * + * Returned Value: + * OK on success; a negated errno value on failure. NOTE: This function + * only enqueues the transfer and returns immediately. Success here only + * means that the transfer was enqueued correctly. + * + * When the transfer is complete, a 'result' value will be provided as + * an argument to the callback function that will indicate if the transfer + * failed. + * + ****************************************************************************/ + +static int stm32_i2s_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, + i2s_callback_t callback, void *arg, uint32_t timeout) +{ + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev; +#ifdef I2S_HAVE_RX + struct stm32_buffer_s *bfcontainer; + irqstate_t flags; + int ret; +#endif + + DEBUGASSERT(priv && apb && ((uintptr_t)apb->samp & priv->align) == 0); + i2sinfo("apb=%p nmaxbytes=%d arg=%p timeout=%" PRId32 "\n", + apb, apb->nmaxbytes, arg, timeout); + + i2s_init_buffer(apb->samp, apb->nmaxbytes); + +#ifdef I2S_HAVE_RX + /* Allocate a buffer container in advance */ + + bfcontainer = i2s_buf_allocate(priv); + DEBUGASSERT(bfcontainer); + + /* Get exclusive access to the I2S driver data */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + goto errout_with_buf; + } + + /* Has the RX channel been enabled? */ + + if (!priv->rxenab) + { + i2serr("ERROR: I2S%d has no receiver\n", priv->i2sno); + ret = -EAGAIN; + goto errout_with_lock; + } + + /* Add a reference to the audio buffer */ + + apb_reference(apb); + + /* Initialize the buffer container structure */ + + bfcontainer->callback = (void *)callback; + bfcontainer->timeout = timeout; + bfcontainer->arg = arg; + bfcontainer->apb = apb; + bfcontainer->result = -EBUSY; + + /* Add the buffer container to the end of the RX pending queue */ + + flags = enter_critical_section(); + sq_addlast((sq_entry_t *)bfcontainer, &priv->rx.pend); + + /* Then start the next transfer. If there is already a transfer in + * progress, then this will do nothing. + */ + + ret = i2s_rxdma_setup(priv); + DEBUGASSERT(ret == OK); + leave_critical_section(flags); + nxmutex_unlock(&priv->lock); + return OK; + +errout_with_lock: + nxmutex_unlock(&priv->lock); + +errout_with_buf: + i2s_buf_free(priv, bfcontainer); + return ret; + +#else + i2serr("ERROR: I2S%d has no receiver\n", priv->i2sno); + UNUSED(priv); + return -ENOSYS; +#endif +} + +static int stm32_i2s_roundf(float num) +{ + if (((int)(num + 0.5f)) > num) + { + return num + 1; + } + + return num; +} + +/**************************************************************************** + * Name: stm32_i2s_txsamplerate + * + * Description: + * Set the I2S TX sample rate. NOTE: This will have no effect if (1) the + * driver does not support an I2S transmitter or if (2) the sample rate is + * driven by the I2S frame clock. This may also have unexpected side- + * effects of the TX sample is coupled with the RX sample rate. + * + * Input Parameters: + * dev - Device-specific state data + * rate - The I2S sample rate in samples (not bits) per second + * + * Returned Value: + * Returns the resulting bitrate + * + ****************************************************************************/ + +static uint32_t stm32_i2s_txsamplerate(struct i2s_dev_s *dev, uint32_t rate) +{ +#if defined(I2S_HAVE_TX) && defined(I2S_HAVE_MCK) + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev; + + DEBUGASSERT(priv && priv->samplerate >= 0 && rate > 0); + + /* Check if the receiver is driven by the MCK/2 */ + + if (priv->samplerate != rate) + { + /* Save the new sample rate and update the MCK/2 divider */ + + priv->samplerate = rate; + return i2s_mckdivider(priv); + } +#endif + + return 0; +} + +/**************************************************************************** + * Name: stm32_i2s_txdatawidth + * + * Description: + * Set the I2S TX data width. The TX bitrate is determined by + * sample_rate * data_width. + * + * Input Parameters: + * dev - Device-specific state data + * width - The I2S data with in bits. + * + * Returned Value: + * Returns the resulting bitrate + * + ****************************************************************************/ + +static uint32_t stm32_i2s_txdatawidth(struct i2s_dev_s *dev, int bits) +{ +#ifdef I2S_HAVE_TX + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev; + int ret; + + i2sinfo("Data width bits of tx = %d\n", bits); + DEBUGASSERT(priv && bits > 1); + + /* Check if this is a bit width that we are configured to handle */ + + ret = i2s_checkwidth(priv, bits); + if (ret < 0) + { + i2serr("ERROR: i2s_checkwidth failed: %d\n", ret); + return 0; + } + + /* Update the DMA flags */ + + ret = i2s_dma_flags(priv); + if (ret < 0) + { + i2serr("ERROR: i2s_dma_flags failed: %d\n", ret); + return 0; + } +#endif + + return 0; +} + +/**************************************************************************** + * Name: stm32_i2s_send + * + * Description: + * Send a block of data on I2S. + * + * Input Parameters: + * dev - Device-specific state data + * apb - A pointer to the audio buffer from which to send data + * callback - A user provided callback function that will be called at + * the completion of the transfer. The callback will be + * performed in the context of the worker thread. + * arg - An opaque argument that will be provided to the callback + * when the transfer complete + * timeout - The timeout value to use. The transfer will be canceled + * and an ETIMEDOUT error will be reported if this timeout + * elapsed without completion of the DMA transfer. Units + * are system clock ticks. Zero means no timeout. + * + * Returned Value: + * OK on success; a negated errno value on failure. NOTE: This function + * only enqueues the transfer and returns immediately. Success here only + * means that the transfer was enqueued correctly. + * + * When the transfer is complete, a 'result' value will be provided as + * an argument to the callback function that will indicate if the transfer + * failed. + * + ****************************************************************************/ + +static int stm32_i2s_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, + i2s_callback_t callback, void *arg, uint32_t timeout) +{ + struct stm32_i2s_s *priv = (struct stm32_i2s_s *)dev; +#ifdef I2S_HAVE_TX + struct stm32_buffer_s *bfcontainer; + irqstate_t flags; + int ret; +#endif + + /* Make sure that we have valid pointers that that the data has uint32_t + * alignment. + */ + + DEBUGASSERT(priv && apb); + i2sinfo("apb=%p nbytes=%d arg=%p timeout=%" PRId32 "\n", + apb, apb->nbytes - apb->curbyte, arg, timeout); + + i2s_dump_buffer("Sending", &apb->samp[apb->curbyte], + apb->nbytes - apb->curbyte); + DEBUGASSERT(((uintptr_t)&apb->samp[apb->curbyte] & priv->align) == 0); + +#ifdef I2S_HAVE_TX + /* Allocate a buffer container in advance */ + + bfcontainer = i2s_buf_allocate(priv); + DEBUGASSERT(bfcontainer); + + /* Get exclusive access to the I2S driver data */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + goto errout_with_buf; + } + + /* Has the TX channel been enabled? */ + + if (!priv->txenab) + { + i2serr("ERROR: I2S%d has no transmitter\n", priv->i2sno); + ret = -EAGAIN; + goto errout_with_lock; + } + + /* Add a reference to the audio buffer */ + + apb_reference(apb); + + /* Initialize the buffer container structure */ + + bfcontainer->callback = (void *)callback; + bfcontainer->timeout = timeout; + bfcontainer->arg = arg; + bfcontainer->apb = apb; + bfcontainer->result = -EBUSY; + + /* Add the buffer container to the end of the TX pending queue */ + + flags = enter_critical_section(); + sq_addlast((sq_entry_t *)bfcontainer, &priv->tx.pend); + + /* Then start the next transfer. If there is already a transfer in + * progress, then this will do nothing. + */ + + ret = i2s_txdma_setup(priv); + DEBUGASSERT(ret == OK); + leave_critical_section(flags); + nxmutex_unlock(&priv->lock); + return OK; + +errout_with_lock: + nxmutex_unlock(&priv->lock); + +errout_with_buf: + i2s_buf_free(priv, bfcontainer); + return ret; + +#else + i2serr("ERROR: I2S%d has no transmitter\n", priv->i2sno); + UNUSED(priv); + return -ENOSYS; +#endif +} + +/**************************************************************************** + * Name: i2s_mckdivider + * + * Description: + * Setup the MCK divider based on the currently selected data width and + * the sample rate + * + * Input Parameters: + * priv - I2C device structure (only the sample rate and data length is + * needed at this point). + * + * Returned Value: + * The current bitrate + * + ****************************************************************************/ + +static uint32_t i2s_mckdivider(struct stm32_i2s_s *priv) +{ + _info("Entry\n"); +#ifdef I2S_HAVE_MCK + uint32_t bitrate; + uint32_t regval; + + uint16_t pllr = 5; + uint16_t plln = 256; + uint16_t div = 12; + uint16_t odd = 1; + + DEBUGASSERT(priv && priv->samplerate >= 0 && priv->datalen > 0); + + /* A zero sample rate means to disable the MCK/2 clock */ + + if (priv->samplerate == 0) + { + bitrate = 0; + regval = 0; + } + else + { + int R; + int n; + int od; + int napprox; + int diff; + int diff_min = 500000000; + + for (od = 0; od <= 1; ++od) + { + for (R = 2; R <= 7; ++R) + { + for (n = 2; n <= 256; ++n) + { + napprox = stm32_i2s_roundf(priv->samplerate / 1000000.0f * + (8 * 32 * R * (2 * n + od))); + if ((napprox > 432) || (napprox < 50)) + { + continue; + } + + diff = abs(priv->samplerate - 1000000 * napprox / + (8 * 32 * R * (2 * n + od))); + if (diff_min > diff) + { + diff_min = diff; + plln = napprox; + pllr = R; + div = n; + odd = od; + } + } + } + } + + /* Calculate the new bitrate in Hz */ + + bitrate = priv->samplerate * priv->datalen; + } + + /* Configure MCK divider */ + + /* Disable I2S */ + + i2s_putreg(priv, STM32_SPI_I2SCFGR_OFFSET, 0); + + /* I2S clock configuration */ + + putreg32((getreg32(STM32_RCC_CR) & (~RCC_CR_PLLI2SON)), STM32_RCC_CR); + + /* PLLI2S clock used as I2S clock source */ + + putreg32(((getreg32(STM32_RCC_CFGR)) & (~RCC_CFGR_I2SSRC)), + STM32_RCC_CFGR); + regval = (pllr << 28) | (plln << 6); + putreg32(regval, STM32_RCC_PLLI2SCFGR); + + /* Enable PLLI2S and wait until it is ready */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLON; + regval |= RCC_CR_PLLI2SON; + putreg32(regval, STM32_RCC_CR); + while (!(getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY)); + + i2s_putreg(priv, STM32_SPI_I2SPR_OFFSET, + div | (odd << 8) | SPI_I2SPR_MCKOE); + i2s_putreg(priv, STM32_SPI_I2SCFGR_OFFSET, + SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SCFG_MTX | SPI_I2SCFGR_I2SE); + +#if 0 + putreg32((getreg32(STM32_DMA1_HIFCR) | DMA_HIFCR_CTCIF7), + STM32_DMA1_HIFCR); +#endif + + putreg32((getreg32(STM32_DMA1_HIFCR) | 0x80000000), STM32_DMA1_HIFCR); + + i2s_dump_regs(priv, "After i2s_mckdivider"); + + return bitrate; +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: i2s_dma_flags + * + * Description: + * Determine DMA FLAGS based on PID and data width + * + * Input Parameters: + * priv - Partially initialized I2C device structure. + * + * Returned Value: + * OK on success; a negated errno value on failure + * + ****************************************************************************/ + +static int i2s_dma_flags(struct stm32_i2s_s *priv) +{ + switch (priv->datalen) + { + case 8: + + /* Reconfigure the RX DMA (and TX DMA if applicable) */ + + priv->rxccr = SPI_RXDMA8_CONFIG; + priv->txccr = SPI_TXDMA8_CONFIG; + break; + + case 16: + priv->rxccr = SPI_RXDMA16_CONFIG; + priv->txccr = SPI_TXDMA16_CONFIG; + break; + + default: + i2serr("ERROR: Unsupported data width: %d\n", priv->datalen); + return -ENOSYS; + } + + return OK; +} + +/**************************************************************************** + * Name: i2s_dma_allocate + * + * Description: + * Allocate I2S DMA channels + * + * Input Parameters: + * priv - Partially initialized I2S device structure. This function + * will complete the DMA specific portions of the initialization + * + * Returned Value: + * OK on success; A negated errno value on failure. + * + ****************************************************************************/ + +static int i2s_dma_allocate(struct stm32_i2s_s *priv) +{ + int ret; + + /* Get the DMA flags for this channel */ + + ret = i2s_dma_flags(priv); + if (ret < 0) + { + i2serr("ERROR: i2s_dma_flags failed: %d\n", ret); + return ret; + } + + /* Allocate DMA channels. These allocations exploit that fact that + * I2S2 is managed by DMA1 and I2S3 is managed by DMA2. Hence, + * the I2S number (i2sno) is the same as the DMA number. + */ + +#ifdef I2S_HAVE_RX + if (priv->rxenab) + { + /* Allocate an RX DMA channel */ + + priv->rx.dma = stm32_dmachannel(DMACHAN_I2S2_RX); + if (!priv->rx.dma) + { + i2serr("ERROR: Failed to allocate the RX DMA channel\n"); + goto errout; + } + } +#endif + +#ifdef I2S_HAVE_TX + if (priv->txenab) + { + /* Allocate a TX DMA channel */ + + priv->tx.dma = stm32_dmachannel(DMACHAN_I2S2_TX); + if (!priv->tx.dma) + { + i2serr("ERROR: Failed to allocate the TX DMA channel\n"); + goto errout; + } + } +#endif + + /* Success exit */ + + return OK; + + /* Error exit */ + +errout: + i2s_dma_free(priv); + return -ENOMEM; +} + +/**************************************************************************** + * Name: i2s_dma_free + * + * Description: + * Release DMA-related resources allocated by i2s_dma_allocate() + * + * Input Parameters: + * priv - Partially initialized I2C device structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void i2s_dma_free(struct stm32_i2s_s *priv) +{ +#ifdef I2S_HAVE_TX + wd_cancel(&priv->tx.dog); + if (priv->tx.dma) + { + stm32_dmafree(priv->tx.dma); + } +#endif + +#ifdef I2S_HAVE_RX + wd_cancel(&priv->rx.dog); + if (priv->rx.dma) + { + stm32_dmafree(priv->rx.dma); + } +#endif +} + +/**************************************************************************** + * Name: i2s1_configure + * + * Description: + * Configure I2S1 + * + * Input Parameters: + * priv - Partially initialized I2C device structure. These functions + * will complete the I2S specific portions of the initialization + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32F7_I2S1 +static void i2s1_configure(struct stm32_i2s_s *priv) +{ + /* Configure multiplexed pins as connected on the board. Chip + * select pins must be selected by board-specific logic. + */ + + priv->base = STM32_I2S1_BASE; + +#ifdef CONFIG_STM32F7_I2S1_RX + priv->rxenab = true; + + if (!priv->initialized) + { + /* Configure I2S2 pins: MCK, SD, CK, WS */ + + stm32_configgpio(GPIO_I2S1_MCK); + stm32_configgpio(GPIO_I2S1_SD); + stm32_configgpio(GPIO_I2S1_CK); + stm32_configgpio(GPIO_I2S1_WS); + priv->initialized = true; + } +#endif /* CONFIG_STM32F7_I2S1_RX */ + +#ifdef CONFIG_STM32F7_I2S1_TX + priv->txenab = true; + + /* Only configure if the port is not already configured */ + + if (!priv->initialized) + { + /* Configure I2S2 pins: MCK, SD, CK, WS */ + + stm32_configgpio(GPIO_I2S1_MCK); + stm32_configgpio(GPIO_I2S1_SD); + stm32_configgpio(GPIO_I2S1_CK); + stm32_configgpio(GPIO_I2S1_WS); + priv->initialized = true; + } +#endif /* CONFIG_STM32F7_I2S1_TX */ + + /* Configure driver state specific to this I2S peripheral */ + + priv->datalen = CONFIG_STM32F7_I2S1_DATALEN; +#ifdef CONFIG_DEBUG + priv->align = STM32F7_I2S2_DATAMASK; +#endif +} +#endif /* CONFIG_STM32F7_I2S1 */ + +/**************************************************************************** + * Name: i2s2_configure + * + * Description: + * Configure I2S2 + * + * Input Parameters: + * priv - Partially initialized I2C device structure. These functions + * will complete the I2S specific portions of the initialization + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32F7_I2S2 +static void i2s2_configure(struct stm32_i2s_s *priv) +{ + /* Configure multiplexed pins as connected on the board. Chip + * select pins must be selected by board-specific logic. + */ + + priv->base = STM32_I2S2_BASE; + +#ifdef CONFIG_STM32F7_I2S2_RX + priv->rxenab = true; + + if (!priv->initialized) + { + /* Configure I2S2 pins: MCK, SD, CK, WS */ + + stm32_configgpio(GPIO_I2S2_MCK); + stm32_configgpio(GPIO_I2S2_SD); + stm32_configgpio(GPIO_I2S2_CK); + stm32_configgpio(GPIO_I2S2_WS); + priv->initialized = true; + } +#endif /* CONFIG_STM32F7_I2S2_RX */ + +#ifdef CONFIG_STM32F7_I2S2_TX + priv->txenab = true; + + /* Only configure if the port is not already configured */ + + if (!priv->initialized) + { + /* Configure I2S2 pins: MCK, SD, CK, WS */ + + stm32_configgpio(GPIO_I2S2_MCK); + stm32_configgpio(GPIO_I2S2_SD); + stm32_configgpio(GPIO_I2S2_CK); + stm32_configgpio(GPIO_I2S2_WS); + priv->initialized = true; + } +#endif /* CONFIG_STM32F7_I2S2_TX */ + + /* Configure driver state specific to this I2S peripheral */ + + priv->datalen = CONFIG_STM32F7_I2S2_DATALEN; +#ifdef CONFIG_DEBUG + priv->align = STM32F7_I2S2_DATAMASK; +#endif +} +#endif /* CONFIG_STM32F7_I2S2 */ + +/**************************************************************************** + * Name: i2s3_configure + * + * Description: + * Configure I2S3 + * + * Input Parameters: + * priv - Partially initialized I2C device structure. These functions + * will complete the I2S specific portions of the initialization + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32F7_I2S3 +static void i2s3_configure(struct stm32_i2s_s *priv) +{ + /* Configure multiplexed pins as connected on the board. Chip + * select pins must be selected by board-specific logic. + */ + + priv->base = STM32_I2S3_BASE; + +#ifdef CONFIG_STM32F7_I2S3_RX + priv->rxenab = true; + + if (!priv->initialized) + { + /* Configure I2S3 pins: MCK, SD, CK, WS */ + + stm32_configgpio(GPIO_I2S3_MCK); + stm32_configgpio(GPIO_I2S3_SD); + stm32_configgpio(GPIO_I2S3_CK); + stm32_configgpio(GPIO_I2S3_WS); + priv->initialized = true; + } +#endif /* CONFIG_STM32F7_I2S3_RX */ + +#ifdef CONFIG_STM32F7_I2S3_TX + priv->txenab = true; + + /* Only configure if the port is not already configured */ + + if (!priv->initialized) + { + /* Configure I2S3 pins: MCK, SD, CK, WS */ + + stm32_configgpio(GPIO_I2S3_MCK); + stm32_configgpio(GPIO_I2S3_SD); + stm32_configgpio(GPIO_I2S3_CK); + stm32_configgpio(GPIO_I2S3_WS); + priv->initialized = true; + } +#endif /* CONFIG_STM32F7_I2S3_TX */ + + /* Configure driver state specific to this I2S peripheral */ + + priv->datalen = CONFIG_STM32F7_I2S3_DATALEN; +#ifdef CONFIG_DEBUG + priv->align = STM32F7_I2S3_DATAMASK; +#endif +} +#endif /* CONFIG_STM32F7_I2S3 */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2sbus_initialize + * + * Description: + * Initialize the selected i2S port + * + * Input Parameters: + * Port number (for hardware that has multiple I2S interfaces) + * + * Returned Value: + * Valid I2S device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct i2s_dev_s *stm32_i2sbus_initialize(int port) +{ + struct stm32_i2s_s *priv = NULL; + irqstate_t flags; + int ret; + + /* The support STM32 parts have only a single I2S port */ + + i2sinfo("port: %d\n", port); + + /* Allocate a new state structure for this chip select. NOTE that there + * is no protection if the same chip select is used in two different + * chip select structures. + */ + + priv = kmm_zalloc(sizeof(struct stm32_i2s_s)); + if (!priv) + { + i2serr("ERROR: Failed to allocate a chip select structure\n"); + return NULL; + } + + /* Set up the initial state for this chip select structure. Other fields + * were zeroed by kmm_zalloc(). + */ + + /* Initialize the common parts for the I2S device structure */ + + nxmutex_init(&priv->lock); + priv->dev.ops = &g_i2sops; + priv->i2sno = port; + + /* Initialize buffering */ + + i2s_buf_initialize(priv); + + flags = enter_critical_section(); + +#ifdef CONFIG_STM32F7_I2S1 + if (port == 1) + { + /* Select I2S1 */ + + i2s1_configure(priv); + } + else +#endif +#ifdef CONFIG_STM32F7_I2S2 + if (port == 2) + { + /* Select I2S2 */ + + i2s2_configure(priv); + } + else +#endif +#ifdef CONFIG_STM32F7_I2S3 + if (port == 3) + { + /* Select I2S3 */ + + i2s3_configure(priv); + } + else +#endif + { + i2serr("ERROR: Unsupported I2S port: %d\n", port); + leave_critical_section(flags); + return NULL; + } + + /* Allocate DMA channels */ + + ret = i2s_dma_allocate(priv); + if (ret < 0) + { + goto errout_with_alloc; + } + + leave_critical_section(flags); + i2s_dump_regs(priv, "After initialization"); + + /* Success exit */ + + return &priv->dev; + + /* Failure exits */ + +errout_with_alloc: + leave_critical_section(flags); + nxmutex_destroy(&priv->lock); + nxsem_destroy(&priv->bufsem); + kmm_free(priv); + return NULL; +} +#endif /* I2S_HAVE_RX || I2S_HAVE_TX */ + +#endif /* CONFIG_STM32F7_I2S1 || CONFIG_STM32F7_I2S2 || CONFIG_STM32F7_I2S3 */ diff --git a/arch/arm/src/stm32f7/stm32_i2s.h b/arch/arm/src/stm32f7/stm32_i2s.h new file mode 100644 index 0000000000000..66d124ca7631c --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_i2s.h @@ -0,0 +1,74 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32_i2s.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_STM32_I2S_H +#define __ARCH_ARM_SRC_STM32F7_STM32_I2S_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip.h" + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2sbus_initialize + * + * Description: + * Initialize the selected I2S port + * + * Input Parameters: + * Port number (for hardware that has multiple I2S interfaces) + * + * Returned Value: + * Valid I2S device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct i2s_dev_s *stm32_i2sbus_initialize(int port); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_STM32F7_STM32_I2S_H */ diff --git a/arch/arm/src/stm32f7/stm32_pwm.c b/arch/arm/src/stm32f7/stm32_pwm.c index fb88fcc9aed09..d1d3d76bc2708 100644 --- a/arch/arm/src/stm32f7/stm32_pwm.c +++ b/arch/arm/src/stm32f7/stm32_pwm.c @@ -4007,6 +4007,13 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) outputs = pwm_outputs_from_channels(priv); ret = pwm_outputs_enable(dev, outputs, false); + /* Clear all channels */ + + pwm_putreg(priv, STM32_GTIM_CCR1_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_CCR2_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_CCR3_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_CCR4_OFFSET, 0); + leave_critical_section(flags); pwm_dumpregs(dev, "After stop"); diff --git a/arch/arm/src/stm32f7/stm32_rtc.c b/arch/arm/src/stm32f7/stm32_rtc.c index 708429990bc51..207fa19588687 100644 --- a/arch/arm/src/stm32f7/stm32_rtc.c +++ b/arch/arm/src/stm32f7/stm32_rtc.c @@ -758,7 +758,7 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) putreg32(alarmreg, STM32_RTC_ALRMAR); putreg32(0, STM32_RTC_ALRMASSR); - rtcinfo(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR)); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); /* Enable RTC alarm A */ diff --git a/arch/arm/src/stm32f7/stm32_serial.c b/arch/arm/src/stm32f7/stm32_serial.c index 14b7c3cb142b1..691823f8b47ef 100644 --- a/arch/arm/src/stm32f7/stm32_serial.c +++ b/arch/arm/src/stm32f7/stm32_serial.c @@ -1405,11 +1405,11 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); up_setusartint(priv, ie); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -1420,7 +1420,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (ie) { @@ -1464,7 +1464,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) up_setusartint(priv, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index 32f2a62eb6a88..35167d38389d4 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -405,13 +405,13 @@ static inline void rcc_enableapb1(void) regval |= RCC_APB1ENR_WWDGEN; #endif -#ifdef CONFIG_STM32F7_SPI2 +#if defined(CONFIG_STM32F7_SPI2) || defined(CONFIG_STM32F7_I2S2) /* SPI2 clock enable */ regval |= RCC_APB1ENR_SPI2EN; #endif -#ifdef CONFIG_STM32F7_SPI3 +#if defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_I2S3) /* SPI3 clock enable */ regval |= RCC_APB1ENR_SPI3EN; @@ -913,7 +913,10 @@ static void stm32_stdclockconfig(void) { } #endif -#if defined(CONFIG_STM32F7_PLLI2S) || (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1)) + +#if defined(CONFIG_STM32F7_PLLI2S) || \ + (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || \ + (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1)) /* Configure PLLI2S */ @@ -922,10 +925,10 @@ static void stm32_stdclockconfig(void) | RCC_PLLI2SCFGR_PLLI2SP_MASK | RCC_PLLI2SCFGR_PLLI2SQ_MASK | RCC_PLLI2SCFGR_PLLI2SR_MASK); - regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN - | STM32_RCC_PLLSAICFGR_PLLSAIP - | STM32_RCC_PLLSAICFGR_PLLSAIQ - | STM32_RCC_PLLSAICFGR_PLLSAIR); + regval |= (STM32_RCC_PLLI2SCFGR_PLLI2SN + | STM32_RCC_PLLI2SCFGR_PLLI2SP + | STM32_RCC_PLLI2SCFGR_PLLI2SQ + | STM32_RCC_PLLI2SCFGR_PLLI2SR); putreg32(regval, STM32_RCC_PLLI2SCFGR); /* Enable PLLI2S */ diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig index 382e6429f23bd..930980a014b6e 100644 --- a/arch/arm/src/stm32h7/Kconfig +++ b/arch/arm/src/stm32h7/Kconfig @@ -17,8 +17,6 @@ config ARCH_CHIP_STM32H743AG select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_G select STM32H7_IO_CONFIG_A - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, UFBGA169 @@ -37,8 +35,6 @@ config ARCH_CHIP_STM32H743BG select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_G select STM32H7_IO_CONFIG_B - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, LQFP208 @@ -48,8 +44,6 @@ config ARCH_CHIP_STM32H743BI select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_B - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, LQFP208 @@ -59,8 +53,6 @@ config ARCH_CHIP_STM32H743IG select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_G select STM32H7_IO_CONFIG_I - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, LQFP176 or UFBGA176 @@ -70,8 +62,6 @@ config ARCH_CHIP_STM32H743II select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, LQFP176 or UFBGA176 @@ -81,8 +71,6 @@ config ARCH_CHIP_STM32H743VG select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_G select STM32H7_IO_CONFIG_V - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, LQFP100 or TFBGA100 @@ -92,8 +80,6 @@ config ARCH_CHIP_STM32H743VI select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_V - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, LQFP100 or TFBGA100 @@ -103,8 +89,6 @@ config ARCH_CHIP_STM32H743XG select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_G select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, TFBGA240 @@ -114,8 +98,6 @@ config ARCH_CHIP_STM32H743XI select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, TFBGA240 @@ -125,8 +107,6 @@ config ARCH_CHIP_STM32H743ZG select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_G select STM32H7_IO_CONFIG_Z - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 1024 Kb FLASH, 1024K Kb SRAM, LQFP144 @@ -136,8 +116,6 @@ config ARCH_CHIP_STM32H743ZI select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_Z - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, LQFP144 @@ -219,8 +197,6 @@ config ARCH_CHIP_STM32H747XI select STM32H7_STM32H7X7XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_X - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 select STM32H7_HAVE_SMPS ---help--- Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM @@ -231,8 +207,6 @@ config ARCH_CHIP_STM32H753AI select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_A - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, UFBGA169 @@ -251,8 +225,6 @@ config ARCH_CHIP_STM32H753II select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_I - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP176/UFBGA176 @@ -262,8 +234,6 @@ config ARCH_CHIP_STM32H753VI select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_V - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP100/TFBGA100 @@ -282,8 +252,6 @@ config ARCH_CHIP_STM32H753ZI select STM32H7_STM32H7X3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_Z - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, with cryptographic accelerator, LQFP144 @@ -293,13 +261,23 @@ config ARCH_CHIP_STM32H7B3LI select STM32H7_STM32H7B3XX select STM32H7_FLASH_CONFIG_I select STM32H7_IO_CONFIG_L - select STM32H7_HAVE_FDCAN1 - select STM32H7_HAVE_FDCAN2 select STM32H7_HAVE_SMPS ---help--- STM32 H7 Cortex M7, 2048 Kb FLASH, 1376 Kb SRAM, with cryptographic accelerator, TFBGA225 +config ARCH_CHIP_STM32H755II + bool "STM32H755II" + select STM32H7_STM32H7X5XX + select STM32H7_FLASH_CONFIG_I + select STM32H7_IO_CONFIG_I + select STM32H7_HAVE_FDCAN1 + select STM32H7_HAVE_FDCAN2 + select STM32H7_HAVE_SMPS + ---help--- + STM32 H7 Cortex M7, 2048 Kb FLASH, 1024K Kb SRAM, + with cryptographic accelerator, LQFP176/UFBGA176 + endchoice # STM32 H7 Chip Selection config STM32H7_HAVE_SMPS @@ -846,17 +824,20 @@ config STM32H7_WWDG default n select WATCHDOG + +menu "STM32H7 FDCAN Selection" + config STM32H7_FDCAN1 bool "FDCAN1" - select STM32H7_FDCAN default n - depends on STM32H7_HAVE_FDCAN1 + select STM32H7_FDCAN config STM32H7_FDCAN2 bool "FDCAN2" - select STM32H7_FDCAN default n - depends on STM32H7_HAVE_FDCAN2 + select STM32H7_FDCAN + +endmenu # STM32H7 FDCAN Selection menu "STM32H7 I2C Selection" @@ -5945,7 +5926,6 @@ endmenu # STM32H7_FDCAN2 config STM32H7_FDCAN_REGDEBUG bool "Enable register dump debugging" - depends on DEBUG_CAN_INFO depends on DEBUG_NET_INFO default n ---help--- diff --git a/arch/arm/src/stm32h7/stm32_adc.c b/arch/arm/src/stm32h7/stm32_adc.c index 10ad1b9c1d245..e4d608bb68931 100644 --- a/arch/arm/src/stm32h7/stm32_adc.c +++ b/arch/arm/src/stm32h7/stm32_adc.c @@ -55,6 +55,7 @@ #include #include +#include #include #include #include @@ -1252,6 +1253,8 @@ static void adc_enable(struct stm32_dev_s *priv) /* Wait for hardware to be ready for conversions */ while (!(adc_getreg(priv, STM32_ADC_ISR_OFFSET) & ADC_INT_ADRDY)); + + adc_modifyreg(priv, STM32_ADC_ISR_OFFSET, 0, ADC_INT_ADRDY); } /**************************************************************************** @@ -1584,7 +1587,7 @@ static void adc_setupclock(struct stm32_dev_s *priv) uint32_t max_clock = 36000000; uint32_t src_clock; uint32_t adc_clock; - uint32_t setbits; + uint32_t setbits = 0; /* The maximum clock is different for rev Y devices and rev V devices. * rev V can support an ADC clock of up to 50MHz. rev Y only supports @@ -2007,6 +2010,13 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) /* Stop ADC conversions to avoid continuous interrupts */ adc_startconv(priv, false); + + /* Clear the interrupt. This register only accepts write 1's so its + * safe to only set the 1 bit without regard for the rest of the + * register + */ + + adc_putreg(priv, STM32_ADC_ISR_OFFSET, ADC_INT_AWD1); } /* OVR: Overrun */ @@ -2036,6 +2046,11 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) priv->cb->au_reset(dev); } + /* Clear the interrupt. This register only accepts write 1's so its + * safe to only set the 1 bit without regard for the rest of the + * register + */ + adc_putreg(priv, STM32_ADC_ISR_OFFSET, ADC_INT_OVR); } @@ -2090,6 +2105,10 @@ static int adc_interrupt(struct adc_dev_s *dev, uint32_t adcisr) } } while ((adc_getreg(priv, STM32_ADC_ISR_OFFSET) & ADC_INT_EOC) != 0); + + /* We dont't add EOC to the bits to clear. It will cause a race + * condition. EOC should only be cleared by reading the ADC_DR + */ } return OK; @@ -2119,10 +2138,6 @@ static int adc12_interrupt(int irq, void *context, void *arg) if (pending != 0) { adc_interrupt(&g_adcdev1, regval); - - /* Clear interrupts */ - - putreg32(regval, STM32_ADC1_ISR); } #endif @@ -2132,10 +2147,6 @@ static int adc12_interrupt(int irq, void *context, void *arg) if (pending != 0) { adc_interrupt(&g_adcdev2, regval); - - /* Clear interrupts */ - - putreg32(regval, STM32_ADC2_ISR); } #endif @@ -2166,10 +2177,6 @@ static int adc3_interrupt(int irq, void *context, void *arg) if (pending != 0) { adc_interrupt(&g_adcdev3, regval); - - /* Clear interrupts */ - - putreg32(regval, STM32_ADC3_ISR); } return OK; diff --git a/arch/arm/src/stm32h7/stm32_fdcan_sock.c b/arch/arm/src/stm32h7/stm32_fdcan_sock.c index f13e5ad5d0064..31e415cb17493 100644 --- a/arch/arm/src/stm32h7/stm32_fdcan_sock.c +++ b/arch/arm/src/stm32h7/stm32_fdcan_sock.c @@ -549,7 +549,7 @@ static void fdcan_dumpregs(struct fdcan_driver_s *priv) /* Protocol error -- check protocol status register for details */ regval = getreg32(priv->base + STM32_FDCAN_PSR_OFFSET); - printf("--PSR.LEC = %d\n", regval & FDCAN_PSR_LEC); + printf("--PSR.LEC = %" PRId32 "\n", regval & FDCAN_PSR_LEC_MASK); } } #endif @@ -2080,7 +2080,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv) } #ifdef CONFIG_STM32H7_FDCAN_REGDEBUG - const fdcan_bitseg *tim = &priv->arbi_timing; + const struct fdcan_bitseg *tim = &priv->arbi_timing; ninfo("[fdcan][arbi] Timings: presc=%u sjw=%u bs1=%u bs2=%u\r\n", tim->prescaler, tim->sjw, tim->bs1, tim->bs2); #endif @@ -2104,7 +2104,7 @@ int fdcan_initialize(struct fdcan_driver_s *priv) } #ifdef CONFIG_STM32H7_FDCAN_REGDEBUG - const fdcan_bitseg *tim = &priv->data_timing; + tim = &priv->data_timing; ninfo("[fdcan][data] Timings: presc=%u sjw=%u bs1=%u bs2=%u\r\n", tim->prescaler, tim->sjw, tim->bs1, tim->bs2); #endif diff --git a/arch/arm/src/stm32h7/stm32_i2c.c b/arch/arm/src/stm32h7/stm32_i2c.c index 87736a2a4ac72..c484db8742639 100644 --- a/arch/arm/src/stm32h7/stm32_i2c.c +++ b/arch/arm/src/stm32h7/stm32_i2c.c @@ -1990,9 +1990,9 @@ static int stm32_i2c_isr_process(struct stm32_i2c_priv_s *priv) i2cinfo("TCR: DISABLE RELOAD: NBYTES = dcnt = %i msgc = %i\n", priv->dcnt, priv->msgc); - stm32_i2c_disable_reload(priv); - stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt); + + stm32_i2c_disable_reload(priv); } i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08" PRIx32 "\n", diff --git a/arch/arm/src/stm32h7/stm32_pwm.c b/arch/arm/src/stm32h7/stm32_pwm.c index e6da7c99f2de4..a208f0cd53136 100644 --- a/arch/arm/src/stm32h7/stm32_pwm.c +++ b/arch/arm/src/stm32h7/stm32_pwm.c @@ -145,7 +145,7 @@ #define TIMRST_TIM16 RCC_APB2RSTR_TIM16RST #define TIMCLK_TIM17 STM32_APB2_TIM17_CLKIN #define TIMRCCEN_TIM17 STM32_RCC_APB2ENR -#define TIMEN_TIM17 RCC_APB2ENR_TIM71EN +#define TIMEN_TIM17 RCC_APB2ENR_TIM17EN #define TIMRCCRST_TIM17 STM32_RCC_APB2RSTR #define TIMRST_TIM17 RCC_APB2RSTR_TIM17RST @@ -4227,6 +4227,14 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev) regval &= ~resetbit; putreg32(regval, regaddr); + + /* Clear all channels */ + + pwm_putreg(priv, STM32_GTIM_CCR1_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_CCR2_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_CCR3_OFFSET, 0); + pwm_putreg(priv, STM32_GTIM_CCR4_OFFSET, 0); + leave_critical_section(flags); pwminfo("regaddr: %08" PRIx32 " resetbit: %08" PRIx32 "\n", diff --git a/arch/arm/src/stm32h7/stm32_qspi.c b/arch/arm/src/stm32h7/stm32_qspi.c index 288766536dc75..113e9cc242762 100644 --- a/arch/arm/src/stm32h7/stm32_qspi.c +++ b/arch/arm/src/stm32h7/stm32_qspi.c @@ -1851,7 +1851,7 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) return 0; } - spiinfo("frequency=%d\n", frequency); + spiinfo("frequency=%" PRId32 "\n", frequency); DEBUGASSERT(priv); /* Wait till BUSY flag reset */ @@ -1905,14 +1905,14 @@ static uint32_t qspi_setfrequency(struct qspi_dev_s *dev, uint32_t frequency) /* Calculate the new actual frequency */ actual = QSPI_CLK_FREQUENCY / prescaler; - spiinfo("prescaler=%d actual=%d\n", prescaler, actual); + spiinfo("prescaler=%" PRId32 " actual=%" PRId32 "\n", prescaler, actual); /* Save the frequency setting */ priv->frequency = frequency; priv->actual = actual; - spiinfo("Frequency %d->%d\n", frequency, actual); + spiinfo("Frequency %" PRId32 "->%" PRId32 "\n", frequency, actual); return actual; } @@ -1983,7 +1983,7 @@ static void qspi_setmode(struct qspi_dev_s *dev, enum qspi_mode_e mode) } qspi_putreg(priv, regval, STM32_QUADSPI_DCR_OFFSET); - spiinfo("DCR=%08x\n", regval); + spiinfo("DCR=%08" PRIx32 "\n", regval); /* Save the mode so that subsequent re-configurations will be faster */ diff --git a/arch/arm/src/stm32h7/stm32_rcc.c b/arch/arm/src/stm32h7/stm32_rcc.c index 55e6b9cbf81c8..2b67b1904238c 100644 --- a/arch/arm/src/stm32h7/stm32_rcc.c +++ b/arch/arm/src/stm32h7/stm32_rcc.c @@ -59,7 +59,11 @@ #elif defined(CONFIG_STM32H7_STM32H7B3XX) # include "stm32h7x3xx_rcc.c" #elif defined(CONFIG_STM32H7_STM32H7X5XX) -# include "stm32h7x3xx_rcc.c" +# if defined(CONFIG_ARCH_CHIP_STM32H755II) +# include "stm32h7x5xx_rcc.c" +# else +# include "stm32h7x3xx_rcc.c" +# endif #elif defined(CONFIG_STM32H7_STM32H7X7XX) # include "stm32h7x7xx_rcc.c" #else diff --git a/arch/arm/src/stm32h7/stm32_rptun.c b/arch/arm/src/stm32h7/stm32_rptun.c index 818451f12ef59..46a66789efc11 100644 --- a/arch/arm/src/stm32h7/stm32_rptun.c +++ b/arch/arm/src/stm32h7/stm32_rptun.c @@ -99,7 +99,6 @@ struct stm32_rptun_dev_s bool master; struct stm32_rptun_shmem_s *shmem; char cpuname[RPMSG_NAME_SIZE + 1]; - char shmemname[RPMSG_NAME_SIZE + 1]; }; /**************************************************************************** @@ -107,9 +106,6 @@ struct stm32_rptun_dev_s ****************************************************************************/ static const char *stm32_rptun_get_cpuname(struct rptun_dev_s *dev); -static const char *stm32_rptun_get_firmware(struct rptun_dev_s *dev); -static const struct rptun_addrenv_s * -stm32_rptun_get_addrenv(struct rptun_dev_s *dev); static struct rptun_rsc_s * stm32_rptun_get_resource(struct rptun_dev_s *dev); static bool stm32_rptun_is_autostart(struct rptun_dev_s *dev); @@ -133,8 +129,6 @@ static void stm32_rptun_panic(struct rptun_dev_s *dev); static const struct rptun_ops_s g_stm32_rptun_ops = { .get_cpuname = stm32_rptun_get_cpuname, - .get_firmware = stm32_rptun_get_firmware, - .get_addrenv = stm32_rptun_get_addrenv, .get_resource = stm32_rptun_get_resource, .is_autostart = stm32_rptun_is_autostart, .is_master = stm32_rptun_is_master, @@ -173,25 +167,6 @@ static const char *stm32_rptun_get_cpuname(struct rptun_dev_s *dev) return priv->cpuname; } -/**************************************************************************** - * Name: stm32_rptun_get_firmware - ****************************************************************************/ - -static const char *stm32_rptun_get_firmware(struct rptun_dev_s *dev) -{ - return NULL; -} - -/**************************************************************************** - * Name: stm32_rptun_get_addrenv - ****************************************************************************/ - -static const struct rptun_addrenv_s * -stm32_rptun_get_addrenv(struct rptun_dev_s *dev) -{ - return NULL; -} - /**************************************************************************** * Name: stm32_rptun_get_resource ****************************************************************************/ @@ -476,7 +451,7 @@ static int stm32_rptun_thread(int argc, char *argv[]) * Public Functions ****************************************************************************/ -int stm32_rptun_init(const char *shmemname, const char *cpuname) +int stm32_rptun_init(const char *cpuname) { struct stm32_rptun_dev_s *dev = &g_rptun_dev; int ret = OK; @@ -506,7 +481,6 @@ int stm32_rptun_init(const char *shmemname, const char *cpuname) dev->rptun.ops = &g_stm32_rptun_ops; strncpy(dev->cpuname, cpuname, RPMSG_NAME_SIZE); - strncpy(dev->shmemname, shmemname, RPMSG_NAME_SIZE); ret = rptun_initialize(&dev->rptun); if (ret < 0) @@ -527,43 +501,3 @@ int stm32_rptun_init(const char *shmemname, const char *cpuname) errout: return ret; } - -/**************************************************************************** - * Name: up_addrenv_va_to_pa - * - * Description: - * This is needed by openamp/libmetal/lib/system/nuttx/io.c:78. The - * physical memory is mapped as virtual. - * - * Input Parameters: - * va_ - * - * Returned Value: - * va - * - ****************************************************************************/ - -uintptr_t up_addrenv_va_to_pa(void *va) -{ - return (uintptr_t)va; -} - -/**************************************************************************** - * Name: up_addrenv_pa_to_va - * - * Description: - * This is needed by openamp/libmetal/lib/system/nuttx/io.c. The - * physical memory is mapped as virtual. - * - * Input Parameters: - * pa - * - * Returned Value: - * pa - * - ****************************************************************************/ - -void *up_addrenv_pa_to_va(uintptr_t pa) -{ - return (void *)pa; -} diff --git a/arch/arm/src/stm32h7/stm32_rptun.h b/arch/arm/src/stm32h7/stm32_rptun.h index 40e5e5f68788e..9f9e12f2d7894 100644 --- a/arch/arm/src/stm32h7/stm32_rptun.h +++ b/arch/arm/src/stm32h7/stm32_rptun.h @@ -50,7 +50,7 @@ extern "C" * Name: stm32_rptun_init ****************************************************************************/ -int stm32_rptun_init(const char *shmemname, const char *cpuname); +int stm32_rptun_init(const char *cpuname); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/arm/src/stm32h7/stm32_rtc.c b/arch/arm/src/stm32h7/stm32_rtc.c index 7a86de4864625..ea865a16657a5 100644 --- a/arch/arm/src/stm32h7/stm32_rtc.c +++ b/arch/arm/src/stm32h7/stm32_rtc.c @@ -758,7 +758,7 @@ static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) putreg32(alarmreg, STM32_RTC_ALRMAR); putreg32(0, STM32_RTC_ALRMASSR); - rtcinfo(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR)); + rtcinfo(" ALRMAR: %08" PRIx32 "\n", getreg32(STM32_RTC_ALRMAR)); /* Enable RTC alarm A */ diff --git a/arch/arm/src/stm32h7/stm32_sdmmc.c b/arch/arm/src/stm32h7/stm32_sdmmc.c index faf70a42afbb1..fe780234ca30b 100644 --- a/arch/arm/src/stm32h7/stm32_sdmmc.c +++ b/arch/arm/src/stm32h7/stm32_sdmmc.c @@ -1900,8 +1900,8 @@ static void stm32_reset(struct sdio_dev_s *dev) struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; irqstate_t flags; uint32_t regval; - uint32_t regaddress; - uint32_t restval; + uint32_t regaddress = 0; + uint32_t restval = 0; /* Disable clocking */ diff --git a/arch/arm/src/stm32h7/stm32_serial.c b/arch/arm/src/stm32h7/stm32_serial.c index 22efa0d14763b..ee33b6a5bc896 100644 --- a/arch/arm/src/stm32h7/stm32_serial.c +++ b/arch/arm/src/stm32h7/stm32_serial.c @@ -1566,11 +1566,11 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); up_setusartint(priv, ie); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } #endif @@ -1582,7 +1582,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (ie) { @@ -1626,7 +1626,7 @@ static void up_disableusartint(struct up_dev_s *priv, uint16_t *ie) up_setusartint(priv, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -3356,13 +3356,18 @@ static void up_dma_txcallback(DMA_HANDLE handle, uint8_t status, void *arg) static void up_dma_txavailable(struct uart_dev_s *dev) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; + irqstate_t flags = enter_critical_section(); /* Only send when the DMA is idle */ - if (stm32_dmaresidual(priv->txdma) == 0) + if (priv->dev.dmatx.length == 0 && + priv->dev.dmatx.nlength == 0 && + stm32_dmaresidual(priv->txdma) == 0) { uart_xmitchars_dma(dev); } + + leave_critical_section(flags); } #endif diff --git a/arch/arm/src/stm32h7/stm32h7x5xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x5xx_rcc.c new file mode 100644 index 0000000000000..8b0c386c8b235 --- /dev/null +++ b/arch/arm/src/stm32h7/stm32h7x5xx_rcc.c @@ -0,0 +1,1050 @@ +/**************************************************************************** + * arch/arm/src/stm32h7/stm32h7x5xx_rcc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "stm32_pwr.h" +#include "hardware/stm32_axi.h" +#include "hardware/stm32_syscfg.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Allow up to 100 milliseconds for the high speed clock to become ready. + * that is a very long delay, but if the clock does not become ready we are + * hosed anyway. Normally this is very fast, but I have seen at least one + * board that required this long, long timeout for the HSE to be ready. + */ + +#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC) + +/* Same for HSI */ + +#define HSIRDY_TIMEOUT HSERDY_TIMEOUT + +/* HSE divisor to yield ~1MHz RTC clock */ + +#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000 + +/* FLASH wait states */ + +#if !defined(BOARD_FLASH_WAITSTATES) +# error BOARD_FLASH_WAITSTATES not defined +#elif BOARD_FLASH_WAITSTATES < 0 || BOARD_FLASH_WAITSTATES > 15 +# error BOARD_FLASH_WAITSTATES is out of range +#endif + +/* Voltage output scale (default to Scale 1 mode) */ + +#ifndef STM32_PWR_VOS_SCALE +# define STM32_PWR_VOS_SCALE PWR_D3CR_VOS_SCALE_1 +#endif + +#if !defined(BOARD_FLASH_PROGDELAY) +# if (STM32_PWR_VOS_SCALE == PWR_D3CR_VOS_SCALE_1) || \ + (STM32_PWR_VOS_SCALE == PWR_D3CR_VOS_SCALE_0) +# if STM32_SYSCLK_FREQUENCY <= 70000000 && BOARD_FLASH_WAITSTATES == 0 +# define BOARD_FLASH_PROGDELAY 0 +# elif STM32_SYSCLK_FREQUENCY <= 140000000 && BOARD_FLASH_WAITSTATES == 1 +# define BOARD_FLASH_PROGDELAY 10 +# elif STM32_SYSCLK_FREQUENCY <= 185000000 && BOARD_FLASH_WAITSTATES == 2 +# define BOARD_FLASH_PROGDELAY 1 +# elif STM32_SYSCLK_FREQUENCY <= 210000000 && BOARD_FLASH_WAITSTATES == 2 +# define BOARD_FLASH_PROGDELAY 2 +# elif STM32_SYSCLK_FREQUENCY <= 225000000 && BOARD_FLASH_WAITSTATES == 3 +# define BOARD_FLASH_PROGDELAY 2 +# else +# define BOARD_FLASH_PROGDELAY 2 +# endif +# else +# define BOARD_FLASH_PROGDELAY 2 +# endif +#endif + +/* PLL are only enabled if the P,Q or R outputs are enabled. */ + +#undef USE_PLL1 +#if STM32_PLLCFG_PLL1CFG & (RCC_PLLCFGR_DIVP1EN | RCC_PLLCFGR_DIVQ1EN | \ + RCC_PLLCFGR_DIVR1EN) +# define USE_PLL1 +#endif + +#undef USE_PLL2 +#if STM32_PLLCFG_PLL2CFG & (RCC_PLLCFGR_DIVP2EN | RCC_PLLCFGR_DIVQ2EN | \ + RCC_PLLCFGR_DIVR2EN) +# define USE_PLL2 +#endif + +#undef USE_PLL3 +#if STM32_PLLCFG_PLL3CFG & (RCC_PLLCFGR_DIVP3EN | RCC_PLLCFGR_DIVQ3EN | \ + RCC_PLLCFGR_DIVR3EN) +# define USE_PLL3 +#endif + +#if defined(STM32_BOARD_USEHSI) && !defined(STM32_BOARD_HSIDIV) +#error When HSI is used, you have to define STM32_BOARD_HSIDIV in board/include/board.h +#endif + +/* Over-drive is supported only for Voltage output scale 1 mode. + * It is required when SYSCLK frequency is over 400 MHz or it can be forced + * to a given state by adding define to the board.h configuration file: + * + * #define STM32_VOS_OVERDRIVE 1 - force over-drive enabled, + * #define STM32_VOS_OVERDRIVE 0 - force over-drive disabled, + * #undef STM32_VOS_OVERDRIVE - autoselect over-drive by logic below + * + * Boosting the core voltage can be a workaround solution to problems with + * poor board signal integration for high-speed digital interfaces like ULPI. + * Higher voltage means faster clock signal edges which may be sufficient to + * synchronise the high-speed clock and data. + */ + +#ifndef STM32_VOS_OVERDRIVE +# if (STM32_PWR_VOS_SCALE == PWR_D3CR_VOS_SCALE_1) && \ + (STM32_SYSCLK_FREQUENCY > 400000000) +# define STM32_VOS_OVERDRIVE 1 +# else +# define STM32_VOS_OVERDRIVE 0 +# endif +#else +# if (STM32_VOS_OVERDRIVE == 1) && \ + (STM32_PWR_VOS_SCALE != PWR_D3CR_VOS_SCALE_1) +# error Over-drive can be selected only when VOS1 is configured +# endif +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rcc_reset + * + * Description: + * Reset the RCC clock configuration to the default reset state + * + ****************************************************************************/ + +static inline void rcc_reset(void) +{ + uint32_t regval; + + /* Enable the Internal High Speed clock (HSI) */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_HSION; + putreg32(regval, STM32_RCC_CR); + +#if defined(CONFIG_STM32H7_AXI_SRAM_CORRUPTION_WAR) + /* Errata 2.2.9 Enable workaround for Reading from AXI SRAM may lead to + * data read corruption. See ES0392 Rev 6. + */ + + putreg32(AXI_TARG_READ_ISS_OVERRIDE, STM32_AXI_TARG7_FN_MOD); +#endif + + /* Reset CFGR register */ + + putreg32(0x00000000, STM32_RCC_CFGR); + + /* Reset HSION, HSEON, CSSON and PLLON bits */ + + regval = getreg32(STM32_RCC_CR); + regval &= ~(RCC_CR_HSEON | RCC_CR_HSI48ON | + RCC_CR_CSION | RCC_CR_PLL1ON | + RCC_CR_PLL2ON | RCC_CR_PLL3ON | + RCC_CR_HSIDIV_MASK); + + /* Set HSI predivider to default (4, 16MHz) */ + + regval |= RCC_CR_HSIDIV_4; + + putreg32(regval, STM32_RCC_CR); + + /* Reset PLLCFGR register to reset default */ + + putreg32(RCC_PLLCFGR_RESET, STM32_RCC_PLLCFGR); + + /* Reset HSEBYP bit */ + + regval = getreg32(STM32_RCC_CR); + regval &= ~RCC_CR_HSEBYP; + putreg32(regval, STM32_RCC_CR); + + /* Disable all interrupts */ + + putreg32(0x00000000, STM32_RCC_CIER); +} + +/**************************************************************************** + * Name: rcc_enableahb1 + * + * Description: + * Enable selected AHB1 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb1(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB1ENR register to enabled the + * selected AHB1 peripherals. + */ + + regval = getreg32(STM32_RCC_AHB1ENR); +#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) + /* ADC1 & 2 clock enable */ + + regval |= RCC_AHB1ENR_ADC12EN; +#endif + +#ifdef CONFIG_STM32H7_DMA1 + /* DMA 1 clock enable */ + + regval |= RCC_AHB1ENR_DMA1EN; +#endif + +#ifdef CONFIG_STM32H7_DMA2 + /* DMA 2 clock enable */ + + regval |= RCC_AHB1ENR_DMA2EN; +#endif + +#ifdef CONFIG_STM32H7_OTGFS + /* USB OTG FS clock enable */ + + regval |= RCC_AHB1ENR_OTGFSEN; +#endif + +#ifdef CONFIG_STM32H7_OTGHS +# ifndef CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI + /* Enable only clocking for USB OTG HS */ + + regval |= RCC_AHB1ENR_OTGHSEN; +# else + /* Enable clocking for USB OTG HS and external PHY */ + + regval |= RCC_AHB1ENR_OTGHSEN | RCC_AHB1ENR_OTGHSULPIEN; +# endif +#endif + +#ifdef CONFIG_STM32H7_ETHMAC + /* Enable ethernet clocks */ + + regval |= (RCC_AHB1ENR_ETH1MACEN | RCC_AHB1ENR_ETH1TXEN | + RCC_AHB1ENR_ETH1RXEN); +#endif + + putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableahb2 + * + * Description: + * Enable selected AHB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb2(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB2ENR register to enabled the + * selected AHB2 peripherals. + */ + + regval = getreg32(STM32_RCC_AHB2ENR); + +#ifdef CONFIG_STM32H7_SDMMC2 + /* SDMMC2 clock enable */ + + regval |= RCC_AHB2ENR_SDMMC2EN; +#endif + +#ifdef CONFIG_STM32H7_RNG + /* Random number generator clock enable */ + + regval |= RCC_AHB2ENR_RNGEN; +#endif + + putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableahb3 + * + * Description: + * Enable selected AHB3 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb3(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB3ENR register to enabled the + * selected AHB3 peripherals. + */ + + regval = getreg32(STM32_RCC_AHB3ENR); + +#ifdef CONFIG_STM32H7_MDMA + /* MDMA clock enable */ + + regval |= RCC_AHB3ENR_MDMAEN; +#endif + +#ifdef CONFIG_STM32H7_SDMMC1 + /* SDMMC clock enable */ + + regval |= RCC_AHB3ENR_SDMMC1EN; +#endif + +#ifdef CONFIG_STM32H7_FMC + /* Flexible static memory controller module clock enable */ + + regval |= RCC_AHB3ENR_FMCEN; +#endif + +#if defined(CONFIG_STM32H7_LTDC) && defined(CONFIG_STM32H7_DMA2D) + /* Enable DMA2D */ + + regval |= RCC_AHB3ENR_DMA2DEN; +#endif + + /* TODO: ... */ + + putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableahb4 + * + * Description: + * Enable selected AHB4 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableahb4(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the AHB4ENR register to enabled the + * selected AHB4 peripherals. + */ + + regval = getreg32(STM32_RCC_AHB4ENR); + +#ifdef CONFIG_STM32H7_ADC3 + /* ADC3 clock enable */ + + regval |= RCC_AHB4ENR_ADC3EN; +#endif + + /* Enable GPIO, GPIOB, ... GPIOK */ + +#if STM32H7_NGPIO > 0 + regval |= (RCC_AHB4ENR_GPIOAEN +#if STM32H7_NGPIO > 1 + | RCC_AHB4ENR_GPIOBEN +#endif +#if STM32H7_NGPIO > 2 + | RCC_AHB4ENR_GPIOCEN +#endif +#if STM32H7_NGPIO > 3 + | RCC_AHB4ENR_GPIODEN +#endif +#if STM32H7_NGPIO > 4 + | RCC_AHB4ENR_GPIOEEN +#endif +#if (STM32H7_NGPIO > 5) && (defined(CONFIG_STM32H7_HAVE_GPIOF)) + | RCC_AHB4ENR_GPIOFEN +#endif +#if (STM32H7_NGPIO > 6) && (defined(CONFIG_STM32H7_HAVE_GPIOG)) + | RCC_AHB4ENR_GPIOGEN +#endif +#if STM32H7_NGPIO > 7 + | RCC_AHB4ENR_GPIOHEN +#endif +#if STM32H7_NGPIO > 8 + | RCC_AHB4ENR_GPIOIEN +#endif +#if STM32H7_NGPIO > 9 + | RCC_AHB4ENR_GPIOJEN +#endif +#if STM32H7_NGPIO > 10 + | RCC_AHB4ENR_GPIOKEN +#endif + ); +#endif + +#ifdef CONFIG_STM32H7_BDMA + /* BDMA clock enable */ + + regval |= RCC_AHB4ENR_BDMAEN; +#endif + +#ifdef CONFIG_STM32H7_CRC + /* CRC clock enable */ + + regval |= RCC_AHB4ENR_CRCEN; +#endif + +#ifdef CONFIG_STM32H7_BKPSRAM + /* Backup SRAM clock enable */ + + regval |= RCC_AHB4ENR_BKPSRAMEN; +#endif + +#ifdef CONFIG_STM32H7_HSEM + /* HSEM clock enable */ + + regval |= RCC_AHB4ENR_HSEMEN; +#endif + + putreg32(regval, STM32_RCC_AHB4ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb1 + * + * Description: + * Enable selected APB1 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb1(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB1L/HENR register to enabled the + * selected APB1 peripherals. + */ + + regval = getreg32(STM32_RCC_APB1LENR); + +#ifdef CONFIG_STM32H7_SPI2 + /* SPI2 clock enable */ + + regval |= RCC_APB1LENR_SPI2EN; +#endif + +#ifdef CONFIG_STM32H7_SPI3 + /* SPI3 clock enable */ + + regval |= RCC_APB1LENR_SPI3EN; +#endif + +#ifdef CONFIG_STM32H7_I2C1 + /* I2C1 clock enable */ + + regval |= RCC_APB1LENR_I2C1EN; +#endif + +#ifdef CONFIG_STM32H7_I2C2 + /* I2C2 clock enable */ + + regval |= RCC_APB1LENR_I2C2EN; +#endif + +#ifdef CONFIG_STM32H7_I2C3 + /* I2C3 clock enable */ + + regval |= RCC_APB1LENR_I2C3EN; +#endif + + putreg32(regval, STM32_RCC_APB1LENR); /* Enable APB1L peripherals */ + + regval = getreg32(STM32_RCC_APB1HENR); + +#ifdef CONFIG_STM32H7_FDCAN + /* FDCAN clock enable */ + + regval |= RCC_APB1HENR_FDCANEN; +#endif + + putreg32(regval, STM32_RCC_APB1HENR); /* Enable APB1H peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb2 + * + * Description: + * Enable selected APB2 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb2(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB2ENR register to enabled the + * selected APB2 peripherals. + */ + + regval = getreg32(STM32_RCC_APB2ENR); + +#ifdef CONFIG_STM32H7_SPI1 + /* SPI1 clock enable */ + + regval |= RCC_APB2ENR_SPI1EN; +#endif + +#ifdef CONFIG_STM32H7_SPI4 + /* SPI4 clock enable */ + + regval |= RCC_APB2ENR_SPI4EN; +#endif + +#ifdef CONFIG_STM32H7_SPI5 + /* SPI5 clock enable */ + + regval |= RCC_APB2ENR_SPI5EN; +#endif + +#ifdef CONFIG_STM32H7_USART1 + /* USART1 clock enable */ + + regval |= RCC_APB2ENR_USART1EN; +#endif + +#ifdef CONFIG_STM32H7_USART6 + /* USART6 clock enable */ + + regval |= RCC_APB2ENR_USART6EN; +#endif + + putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb3 + * + * Description: + * Enable selected APB3 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb3(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB3ENR register to enabled the + * selected APB3 peripherals. + */ + + regval = getreg32(STM32_RCC_APB3ENR); + +#ifdef CONFIG_STM32H7_LTDC + /* LTDC clock enable */ + + regval |= RCC_APB3ENR_LTDCEN; +#endif + + putreg32(regval, STM32_RCC_APB3ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableapb4 + * + * Description: + * Enable selected APB4 peripherals + * + ****************************************************************************/ + +static inline void rcc_enableapb4(void) +{ + uint32_t regval; + + /* Set the appropriate bits in the APB4ENR register to enabled the + * selected APB4 peripherals. + */ + + regval = getreg32(STM32_RCC_APB4ENR); + +#ifdef CONFIG_STM32H7_SYSCFG + /* System configuration controller clock enable */ + + regval |= RCC_APB4ENR_SYSCFGEN; +#endif + +#ifdef CONFIG_STM32H7_I2C4 + /* I2C4 clock enable */ + + regval |= RCC_APB4ENR_I2C4EN; +#endif + +#ifdef CONFIG_STM32H7_SPI6 + /* SPI6 clock enable */ + + regval |= RCC_APB4ENR_SPI6EN; +#endif + + /* TODO: ... */ + + putreg32(regval, STM32_RCC_APB4ENR); /* Enable peripherals */ +} + +/**************************************************************************** + * Name: rcc_enableperiphals + ****************************************************************************/ + +static inline void rcc_enableperipherals(void) +{ + rcc_enableahb1(); + rcc_enableahb2(); + rcc_enableahb3(); + rcc_enableahb4(); + rcc_enableapb1(); + rcc_enableapb2(); + rcc_enableapb3(); + rcc_enableapb4(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_stdclockconfig + * + * Description: + * Called to change to new clock based on settings in board.h + * + * NOTE: This logic would need to be extended if you need to select low- + * power clocking modes! + ****************************************************************************/ + +void stm32_stdclockconfig(void) +{ + uint32_t regval; + volatile int32_t timeout; + +#ifdef STM32_BOARD_USEHSI + /* Enable Internal High-Speed Clock (HSI) */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_HSION; /* Enable HSI */ + + /* Set HSI predivider to board specific value */ + + regval |= STM32_BOARD_HSIDIV; + + putreg32(regval, STM32_RCC_CR); + + /* Wait until the HSI is ready (or until a timeout elapsed) */ + + for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the HSIRDY flag is the set in the CR */ + + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } + +#else /* if STM32_BOARD_USEHSE */ + /* Enable External High-Speed Clock (HSE) */ + + regval = getreg32(STM32_RCC_CR); +#ifdef STM32_HSEBYP_ENABLE /* May be defined in board.h header file */ + regval |= RCC_CR_HSEBYP; /* Enable HSE clock bypass */ +#else + regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */ +#endif + regval |= RCC_CR_HSEON; /* Enable HSE */ + putreg32(regval, STM32_RCC_CR); + + /* Wait until the HSE is ready (or until a timeout elapsed) */ + + for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--) + { + /* Check if the HSERDY flag is the set in the CR */ + + if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) + { + /* If so, then break-out with timeout > 0 */ + + break; + } + } +#endif + +#ifdef CONFIG_STM32H7_HSI48 + /* Enable HSI48 */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_HSI48ON; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the HSI48 is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_HSI48RDY) == 0) + { + } +#endif + +#ifdef CONFIG_STM32H7_CSI + /* Enable CSI */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_CSION; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the CSI is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_CSIRDY) == 0) + { + } +#endif + + /* Check for a timeout. If this timeout occurs, then we are hosed. We + * have no real back-up plan, although the following logic makes it look + * as though we do. + */ + + if (timeout > 0) + { + /* Set the D1 domain Core prescaler and the HCLK source/divider */ + + regval = getreg32(STM32_RCC_D1CFGR); + regval &= ~(RCC_D1CFGR_HPRE_MASK | RCC_D1CFGR_D1CPRE_MASK); + regval |= (STM32_RCC_D1CFGR_HPRE | STM32_RCC_D1CFGR_D1CPRE); + putreg32(regval, STM32_RCC_D1CFGR); + + /* Set PCLK1 */ + + regval = getreg32(STM32_RCC_D2CFGR); + regval &= ~RCC_D2CFGR_D2PPRE2_MASK; + regval |= STM32_RCC_D2CFGR_D2PPRE1; + putreg32(regval, STM32_RCC_D2CFGR); + + /* Set PCLK2 */ + + regval = getreg32(STM32_RCC_D2CFGR); + regval &= ~RCC_D2CFGR_D2PPRE2_MASK; + regval |= STM32_RCC_D2CFGR_D2PPRE2; + putreg32(regval, STM32_RCC_D2CFGR); + + /* Set PCLK3 */ + + regval = getreg32(STM32_RCC_D1CFGR); + regval &= ~RCC_D1CFGR_D1PPRE_MASK; + regval |= STM32_RCC_D1CFGR_D1PPRE; + putreg32(regval, STM32_RCC_D1CFGR); + + /* Set PCLK4 */ + + regval = getreg32(STM32_RCC_D3CFGR); + regval &= ~RCC_D3CFGR_D3PPRE_MASK; + regval |= STM32_RCC_D3CFGR_D3PPRE; + putreg32(regval, STM32_RCC_D3CFGR); + +#ifdef CONFIG_STM32H7_RTC_HSECLOCK + /* Set the RTC clock divisor */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_RTCPRE_MASK; + regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR); + putreg32(regval, STM32_RCC_CFGR); +#endif + + /* Configure PLL123 clock source and multipiers */ + +#ifdef STM32_BOARD_USEHSI + regval = (RCC_PLLCKSELR_PLLSRC_HSI | + STM32_PLLCFG_PLL1M | + STM32_PLLCFG_PLL2M | + STM32_PLLCFG_PLL3M); +#else /* if STM32_BOARD_USEHSE */ + regval = (RCC_PLLCKSELR_PLLSRC_HSE | + STM32_PLLCFG_PLL1M | + STM32_PLLCFG_PLL2M | + STM32_PLLCFG_PLL3M); +#endif + putreg32(regval, STM32_RCC_PLLCKSELR); + + /* Each PLL offers 3 outputs with post-dividers (PLLxP/PLLxQ/PLLxR) */ + + /* Configure PLL1 dividers */ + + regval = (STM32_PLLCFG_PLL1N | + STM32_PLLCFG_PLL1P | + STM32_PLLCFG_PLL1Q | + STM32_PLLCFG_PLL1R); + putreg32(regval, STM32_RCC_PLL1DIVR); + + /* Configure PLL2 dividers */ + + regval = (STM32_PLLCFG_PLL2N | + STM32_PLLCFG_PLL2P | + STM32_PLLCFG_PLL2Q | + STM32_PLLCFG_PLL2R); + putreg32(regval, STM32_RCC_PLL2DIVR); + + /* Configure PLL3 dividers */ + + regval = (STM32_PLLCFG_PLL3N | + STM32_PLLCFG_PLL3P | + STM32_PLLCFG_PLL3Q | + STM32_PLLCFG_PLL3R); + putreg32(regval, STM32_RCC_PLL3DIVR); + + /* Configure PLLs */ + + regval = (STM32_PLLCFG_PLL1CFG | + STM32_PLLCFG_PLL2CFG | + STM32_PLLCFG_PLL3CFG); + putreg32(regval, STM32_RCC_PLLCFGR); + + regval = getreg32(STM32_RCC_CR); +#if defined(USE_PLL1) + /* Enable the PLL1 */ + + regval |= RCC_CR_PLL1ON; +#endif + +#if defined(USE_PLL2) + /* Enable the PLL2 */ + + regval |= RCC_CR_PLL2ON; +#endif + +#if defined(USE_PLL3) + /* Enable the PLL3 */ + + regval |= RCC_CR_PLL3ON; +#endif + putreg32(regval, STM32_RCC_CR); + +#if defined(USE_PLL1) + /* Wait until the PLL1 is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL1RDY) == 0) + { + } +#endif + +#if defined(USE_PLL2) + /* Wait until the PLL2 is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0) + { + } +#endif + +#if defined(USE_PLL3) + /* Wait until the PLL3 is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL3RDY) == 0) + { + } +#endif + + /* We must write the lower byte of the PWR_CR3 register is written once + * after POR and it shall be written before changing VOS level or + * ck_sys clock frequency. No limitation applies to the upper bytes. + * + * Programming data corresponding to an invalid combination of + * LDOEN and BYPASS bits will be ignored: data will not be written, + * the written-once mechanism will lock the register and any further + * write access will be ignored. The default supply configuration will + * be kept and the ACTVOSRDY bit in PWR control status register 1 + * (PWR_CSR1) will go on indicating invalid voltage levels. + * + * N.B. The system shall be power cycled before writing a new value. + */ + +#if defined(CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY) + regval = getreg32(STM32_PWR_CR3); + regval &= ~(STM32_PWR_CR3_BYPASS | STM32_PWR_CR3_LDOEN | + STM32_PWR_CR3_SMPSEXTHP | STM32_PWR_CR3_SMPSLEVEL_MASK); + regval |= STM32_PWR_CR3_SCUEN; + putreg32(regval, STM32_PWR_CR3); +#elif defined(CONFIG_STM32H7_PWR_LDO_SUPPLY) + regval = getreg32(STM32_PWR_CR3); + regval &= ~(STM32_PWR_CR3_BYPASS | STM32_PWR_CR3_SCUEN | + STM32_PWR_CR3_SMPSEXTHP | STM32_PWR_CR3_SMPSLEVEL_MASK); + regval |= STM32_PWR_CR3_LDOEN; + putreg32(regval, STM32_PWR_CR3); +#else + regval = getreg32(STM32_PWR_CR3); + regval |= STM32_PWR_CR3_LDOEN | STM32_PWR_CR3_SCUEN; + putreg32(regval, STM32_PWR_CR3); +#endif + + /* Set the voltage output scale */ + + regval = getreg32(STM32_PWR_D3CR); + regval &= ~STM32_PWR_D3CR_VOS_MASK; + regval |= STM32_PWR_VOS_SCALE; + putreg32(regval, STM32_PWR_D3CR); + + while ((getreg32(STM32_PWR_D3CR) & STM32_PWR_D3CR_VOSRDY) == 0) + { + } + + /* See Reference manual Section 5.4.1, System supply startup */ + + while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ACTVOSRDY) == 0) + { + } + +#if STM32_VOS_OVERDRIVE && (STM32_PWR_VOS_SCALE == PWR_D3CR_VOS_SCALE_1) + /* Over-drive support for VOS1 */ + + /* Enable System configuration controller clock to Enable ODEN */ + + regval = getreg32(STM32_RCC_APB4ENR); + regval |= RCC_APB4ENR_SYSCFGEN; + putreg32(regval, STM32_RCC_APB4ENR); + + /* Enable Overdrive */ + + regval = getreg32(STM32_SYSCFG_PWRCR); + regval |= SYSCFG_PWRCR_ODEN; + putreg32(regval, STM32_SYSCFG_PWRCR); + + while ((getreg32(STM32_PWR_D3CR) & STM32_PWR_D3CR_VOSRDY) == 0) + { + } +#endif + + /* Configure FLASH wait states */ + + regval = FLASH_ACR_WRHIGHFREQ(BOARD_FLASH_PROGDELAY) | + FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES); + + putreg32(regval, STM32_FLASH_ACR); + + /* Select the PLL1P as system clock source */ + + regval = getreg32(STM32_RCC_CFGR); + regval &= ~RCC_CFGR_SW_MASK; + regval |= RCC_CFGR_SW_PLL1; + putreg32(regval, STM32_RCC_CFGR); + + /* Wait until the PLL source is used as the system clock source */ + + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + RCC_CFGR_SWS_PLL1) + { + } + + /* Configure SDMMC source clock */ + +#if defined(STM32_RCC_D1CCIPR_SDMMCSEL) + regval = getreg32(STM32_RCC_D1CCIPR); + regval &= ~RCC_D1CCIPR_SDMMC_MASK; + regval |= STM32_RCC_D1CCIPR_SDMMCSEL; + putreg32(regval, STM32_RCC_D1CCIPR); +#endif + + /* Configure I2C source clock */ + +#if defined(STM32_RCC_D2CCIP2R_I2C123SRC) + regval = getreg32(STM32_RCC_D2CCIP2R); + regval &= ~RCC_D2CCIP2R_I2C123SEL_MASK; + regval |= STM32_RCC_D2CCIP2R_I2C123SRC; + putreg32(regval, STM32_RCC_D2CCIP2R); +#endif + +#if defined(STM32_RCC_D3CCIPR_I2C4SRC) + regval = getreg32(STM32_RCC_D3CCIPR); + regval &= ~RCC_D3CCIPR_I2C4SEL_MASK; + regval |= STM32_RCC_D3CCIPR_I2C4SRC; + putreg32(regval, STM32_RCC_D3CCIPR); +#endif + + /* Configure SPI source clock */ + +#if defined(STM32_RCC_D2CCIP1R_SPI123SRC) + regval = getreg32(STM32_RCC_D2CCIP1R); + regval &= ~RCC_D2CCIP1R_SPI123SEL_MASK; + regval |= STM32_RCC_D2CCIP1R_SPI123SRC; + putreg32(regval, STM32_RCC_D2CCIP1R); +#endif + +#if defined(STM32_RCC_D2CCIP1R_SPI45SRC) + regval = getreg32(STM32_RCC_D2CCIP1R); + regval &= ~RCC_D2CCIP1R_SPI45SEL_MASK; + regval |= STM32_RCC_D2CCIP1R_SPI45SRC; + putreg32(regval, STM32_RCC_D2CCIP1R); +#endif + +#if defined(STM32_RCC_D3CCIPR_SPI6SRC) + regval = getreg32(STM32_RCC_D3CCIPR); + regval &= ~RCC_D3CCIPR_SPI6SEL_MASK; + regval |= STM32_RCC_D3CCIPR_SPI6SRC; + putreg32(regval, STM32_RCC_D3CCIPR); +#endif + + /* Configure USB source clock */ + +#if defined(STM32_RCC_D2CCIP2R_USBSRC) + regval = getreg32(STM32_RCC_D2CCIP2R); + regval &= ~RCC_D2CCIP2R_USBSEL_MASK; + regval |= STM32_RCC_D2CCIP2R_USBSRC; + putreg32(regval, STM32_RCC_D2CCIP2R); +#endif + + /* Configure ADC source clock */ + +#if defined(STM32_RCC_D3CCIPR_ADCSRC) + regval = getreg32(STM32_RCC_D3CCIPR); + regval &= ~RCC_D3CCIPR_ADCSEL_MASK; + regval |= STM32_RCC_D3CCIPR_ADCSRC; + putreg32(regval, STM32_RCC_D3CCIPR); +#endif + + /* Configure FDCAN source clock */ + +#if defined(STM32_RCC_D2CCIP1R_FDCANSEL) + regval = getreg32(STM32_RCC_D2CCIP1R); + regval &= ~RCC_D2CCIP1R_FDCANSEL_MASK; + regval |= STM32_RCC_D2CCIP1R_FDCANSEL; + putreg32(regval, STM32_RCC_D2CCIP1R); +#endif + +#if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK) + /* Low speed internal clock source LSI */ + + stm32_rcc_enablelsi(); +#endif + +#if defined(CONFIG_STM32H7_RTC_LSECLOCK) + /* Low speed external clock source LSE + * + * TODO: There is another case where the LSE needs to + * be enabled: if the MCO1 pin selects LSE as source. + */ + + stm32_rcc_enablelse(); +#endif + } +} diff --git a/arch/arm/src/stm32l4/stm32l4_adc.c b/arch/arm/src/stm32l4/stm32l4_adc.c index 096d2c1f96864..a49559d8ebde3 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.c +++ b/arch/arm/src/stm32l4/stm32l4_adc.c @@ -34,6 +34,7 @@ #include #include +#include #include #include #include diff --git a/arch/arm/src/stm32l4/stm32l4_serial.c b/arch/arm/src/stm32l4/stm32l4_serial.c index c6b4c903450b5..648fc995ba906 100644 --- a/arch/arm/src/stm32l4/stm32l4_serial.c +++ b/arch/arm/src/stm32l4/stm32l4_serial.c @@ -901,11 +901,11 @@ static void stm32l4serial_restoreusartint(struct stm32l4_serial_s *priv, { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); stm32l4serial_setusartint(priv, ie); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -917,7 +917,7 @@ static void stm32l4serial_disableusartint(struct stm32l4_serial_s *priv, { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (ie) { @@ -965,7 +965,7 @@ static void stm32l4serial_disableusartint(struct stm32l4_serial_s *priv, stm32l4serial_setusartint(priv, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/arm/src/stm32l5/stm32l5_serial.c b/arch/arm/src/stm32l5/stm32l5_serial.c index ee3e466183934..b483d1835fb3d 100644 --- a/arch/arm/src/stm32l5/stm32l5_serial.c +++ b/arch/arm/src/stm32l5/stm32l5_serial.c @@ -906,11 +906,11 @@ static void stm32l5serial_restoreusartint(struct stm32l5_serial_s *priv, { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); stm32l5serial_setusartint(priv, ie); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -922,7 +922,7 @@ static void stm32l5serial_disableusartint(struct stm32l5_serial_s *priv, { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (ie) { @@ -965,7 +965,7 @@ static void stm32l5serial_disableusartint(struct stm32l5_serial_s *priv, stm32l5serial_setusartint(priv, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/arm/src/stm32u5/CMakeLists.txt b/arch/arm/src/stm32u5/CMakeLists.txt index d034144d8990c..a84f3aca8b544 100644 --- a/arch/arm/src/stm32u5/CMakeLists.txt +++ b/arch/arm/src/stm32u5/CMakeLists.txt @@ -25,6 +25,7 @@ set(SRCS stm32_irq.c stm32_lowputc.c stm32_rcc.c + stm32_i2c.c stm32_serial.c stm32_start.c stm32_waste.c @@ -32,6 +33,7 @@ set(SRCS stm32_spi.c stm32_lse.c stm32_lsi.c + stm32u5xx_rcc.c stm32_pwr.c stm32_tim.c stm32_flash.c @@ -53,8 +55,8 @@ if(CONFIG_DEBUG_FEATURES) list(APPEND SRCS stm32_dumpgpio.c) endif() -if(CONFIG_STM32U5_STM32U585XX) - list(APPEND SRCS stm32u585xx_rcc.c) +if(CONFIG_USBDEV) + list(APPEND SRCS stm32_otgdev.c) endif() target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/stm32u5/stm32_serial.c b/arch/arm/src/stm32u5/stm32_serial.c index 5ce2fecfd7cfa..97f90300e2668 100644 --- a/arch/arm/src/stm32u5/stm32_serial.c +++ b/arch/arm/src/stm32u5/stm32_serial.c @@ -922,7 +922,7 @@ static void stm32serial_disableusartint(struct stm32_serial_s *priv, { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (ie) { @@ -965,7 +965,7 @@ static void stm32serial_disableusartint(struct stm32_serial_s *priv, stm32serial_setusartint(priv, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/arm/src/stm32wb/stm32wb_serial.c b/arch/arm/src/stm32wb/stm32wb_serial.c index 889061620cbc8..b83a23ff693d6 100644 --- a/arch/arm/src/stm32wb/stm32wb_serial.c +++ b/arch/arm/src/stm32wb/stm32wb_serial.c @@ -556,11 +556,11 @@ static void stm32wb_serial_restoreusartint(struct stm32wb_serial_s *priv, { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); stm32wb_serial_setusartint(priv, ie); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -572,7 +572,7 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (ie) { @@ -620,7 +620,7 @@ static void stm32wb_serial_disableusartint(struct stm32wb_serial_s *priv, stm32wb_serial_setusartint(priv, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/arm/src/stm32wl5/stm32wl5_serial.c b/arch/arm/src/stm32wl5/stm32wl5_serial.c index 660ca12424d62..037bbbcfa5bd5 100644 --- a/arch/arm/src/stm32wl5/stm32wl5_serial.c +++ b/arch/arm/src/stm32wl5/stm32wl5_serial.c @@ -661,11 +661,11 @@ static void stm32wl5serial_restoreusartint(struct stm32wl5_serial_s *priv, { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); stm32wl5serial_setusartint(priv, ie); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -677,7 +677,7 @@ static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv, { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (ie) { @@ -720,7 +720,7 @@ static void stm32wl5serial_disableusartint(struct stm32wl5_serial_s *priv, stm32wl5serial_setusartint(priv, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/arm/src/str71x/str71x_map.h b/arch/arm/src/str71x/str71x_map.h index ad40e6f30a9e8..597520a7b81dd 100644 --- a/arch/arm/src/str71x/str71x_map.h +++ b/arch/arm/src/str71x/str71x_map.h @@ -81,4 +81,4 @@ * Public Functions Prototypes ****************************************************************************/ -#endif // __ARCH_ARM_SRC_STR71X_STR71X_MAP_H +#endif /* __ARCH_ARM_SRC_STR71X_STR71X_MAP_H */ diff --git a/arch/arm/src/tiva/common/tiva_pwm.c b/arch/arm/src/tiva/common/tiva_pwm.c index be67fc681e9bb..1bb0e85a74d56 100644 --- a/arch/arm/src/tiva/common/tiva_pwm.c +++ b/arch/arm/src/tiva/common/tiva_pwm.c @@ -757,7 +757,7 @@ static int tiva_pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd, struct pwm_lowerhalf_s *tiva_pwm_initialize(int channel) { - assert(channel >= 0 && channel <= 7); + ASSERT(channel >= 0 && channel <= 7); struct tiva_pwm_chan_s *chan; switch (channel) @@ -824,7 +824,7 @@ struct pwm_lowerhalf_s *tiva_pwm_initialize(int channel) /* Enable PWM controller (refer to TM4C1294NCPDT 23.4.1) */ - assert(chan->controller_id == 0); + ASSERT(chan->controller_id == 0); tiva_pwm_enablepwr(chan->controller_id); tiva_pwm_enableclk(chan->controller_id); diff --git a/arch/arm/src/tiva/hardware/tiva_adc.h b/arch/arm/src/tiva/hardware/tiva_adc.h index 78836b77a90b7..c1dc100534861 100644 --- a/arch/arm/src/tiva/hardware/tiva_adc.h +++ b/arch/arm/src/tiva/hardware/tiva_adc.h @@ -943,4 +943,4 @@ #define ADC_CC_CS_PIOSC (0x001) /* PIOSC */ #define ADC_CC_CS_MOSC (0x002) /* MOSC */ -#endif // __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADC_H +#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TIVA_ADC_H */ diff --git a/arch/arm/src/tiva/hardware/tm4c/tm4c_flash.h b/arch/arm/src/tiva/hardware/tm4c/tm4c_flash.h index ead5615d2083e..5cc4d1d909924 100644 --- a/arch/arm/src/tiva/hardware/tm4c/tm4c_flash.h +++ b/arch/arm/src/tiva/hardware/tm4c/tm4c_flash.h @@ -415,4 +415,4 @@ /* Flash Memory Protection Program Enable 0-15 (32-bit, bit-encoded) */ -#endif // __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C_FLASH_H +#endif /* __ARCH_ARM_SRC_TIVA_HARDWARE_TM4C_TM4C_FLASH_H */ diff --git a/arch/arm/src/tlsr82/tc32/tc32_backtrace.c b/arch/arm/src/tlsr82/tc32/tc32_backtrace.c index 7a8dbf68fb177..d94ad56903c74 100644 --- a/arch/arm/src/tlsr82/tc32/tc32_backtrace.c +++ b/arch/arm/src/tlsr82/tc32/tc32_backtrace.c @@ -456,7 +456,7 @@ int up_backtrace(struct tcb_s *tcb, void **buffer, int size, int skip) struct tcb_s *rtcb = running_task(); irqstate_t flags; void *sp; - int ret; + int ret = 0; if (size <= 0 || !buffer) { @@ -475,12 +475,8 @@ int up_backtrace(struct tcb_s *tcb, void **buffer, int size, int skip) if (up_interrupt_context()) { #if CONFIG_ARCH_INTERRUPTSTACK > 7 - ret = backtrace_push( -# ifdef CONFIG_SMP - arm_intstack_top(), -# else - g_intstacktop, -# endif /* CONFIG_SMP */ + ret = backtrace_push((void *)(INTSTACK_SIZE + + up_get_intstackbase(up_cpu_index())), &sp, (void *)up_backtrace + 16, buffer, size, &skip); #else @@ -515,8 +511,6 @@ int up_backtrace(struct tcb_s *tcb, void **buffer, int size, int skip) } else { - ret = 0; - flags = enter_critical_section(); if (skip-- <= 0) diff --git a/arch/arm/src/tms570/tms570_lowputc.c b/arch/arm/src/tms570/tms570_lowputc.c index 599c2f7475007..9f7232460b3d4 100644 --- a/arch/arm/src/tms570/tms570_lowputc.c +++ b/arch/arm/src/tms570/tms570_lowputc.c @@ -50,6 +50,7 @@ #include #include +#include #include #include "arm_internal.h" @@ -200,18 +201,18 @@ void arm_lowputc(char ch) * atomic. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if ((getreg32(TMS570_CONSOLE_BASE + TMS570_SCI_FLR_OFFSET) & SCI_FLR_TXRDY) != 0) { /* Send the character */ putreg32((uint32_t)ch, TMS570_CONSOLE_BASE + TMS570_SCI_TD_OFFSET); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); return; } - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } #endif } diff --git a/arch/arm/src/xmc4/CMakeLists.txt b/arch/arm/src/xmc4/CMakeLists.txt new file mode 100644 index 0000000000000..2903dbd6ee29b --- /dev/null +++ b/arch/arm/src/xmc4/CMakeLists.txt @@ -0,0 +1,54 @@ +# ############################################################################## +# arch/arm/src/xmc4/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +list( + APPEND + SRCS + xmc4_allocateheap.c + xmc4_clockconfig.c + xmc4_clockutils.c + xmc4_clrpend.c + xmc4_gpio.c + xmc4_irq.c + xmc4_lowputc.c + xmc4_serial.c + xmc4_start.c + xmc4_usic.c + xmc4_timerisr.c) + +if(CONFIG_BUILD_PROTECTED) + list(APPEND SRCS xmc4_userspace.c xmc4_mpuinit.c) +endif() + +if(CONFIG_XMC4_ECAT) + list(APPEND SRCS xmc4_ecat.c) +endif() + +if(NOT CONFIG_ARCH_IDLE_CUSTOM) + list(APPEND SRCS xmc4_idle.c) +endif() + +if(CONFIG_XMC4_USCI_SPI) + list(APPEND SRCS xmc4_spi.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/xmc4/Kconfig b/arch/arm/src/xmc4/Kconfig index 46fcae7d0013e..a6191796ea40c 100644 --- a/arch/arm/src/xmc4/Kconfig +++ b/arch/arm/src/xmc4/Kconfig @@ -177,6 +177,23 @@ config XMC4_USIC2 ---help--- Support USIC2 +config XMC4_ECAT + bool "Enable EtherCAT interface" + default y + depends on ARCH_CHIP_XMC4800 + ---help--- + Enable start up of the EtherCAT interface and configure ports. + +config XMC4_ECAT_P0 + bool "Enable EtherCAT port 0" + default y + depends on XMC4_ECAT + +config XMC4_ECAT_P1 + bool "Enable EtherCAT port 1" + default n + depends on XMC4_ECAT + endmenu menu "XMC4xxx USIC Configuration" diff --git a/arch/arm/src/xmc4/Make.defs b/arch/arm/src/xmc4/Make.defs index 20604841612b9..f5eb2b3b2eab0 100644 --- a/arch/arm/src/xmc4/Make.defs +++ b/arch/arm/src/xmc4/Make.defs @@ -23,8 +23,9 @@ include armv7-m/Make.defs # Required XMC4xxx files CHIP_CSRCS = xmc4_allocateheap.c xmc4_clockconfig.c xmc4_clockutils.c -CHIP_CSRCS += xmc4_clrpend.c xmc4_irq.c xmc4_lowputc.c xmc4_gpio.c -CHIP_CSRCS += xmc4_serial.c xmc4_start.c xmc4_usic.c +CHIP_CSRCS += xmc4_clrpend.c xmc4_flash.c xmc4_gpio.c xmc4_irq.c +CHIP_CSRCS += xmc4_lowputc.c xmc4_serial.c xmc4_start.c xmc4_usic.c +CHIP_CSRCS += xmc4_ccu4.c # Configuration-dependent Kinetis files @@ -34,6 +35,8 @@ endif ifneq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += xmc4_timerisr.c +else +CHIP_CSRCS += xmc4_tickless.c endif ifeq ($(CONFIG_BUILD_PROTECTED),y) @@ -47,3 +50,7 @@ endif ifeq ($(CONFIG_XMC4_USCI_SPI),y) CHIP_CSRCS += xmc4_spi.c endif + +ifeq ($(CONFIG_XMC4_ECAT),y) +CHIP_CSRCS += xmc4_ecat.c +endif diff --git a/arch/arm/src/xmc4/hardware/xmc4_ccu4.h b/arch/arm/src/xmc4/hardware/xmc4_ccu4.h new file mode 100644 index 0000000000000..57ae6f0a1ef15 --- /dev/null +++ b/arch/arm/src/xmc4/hardware/xmc4_ccu4.h @@ -0,0 +1,1334 @@ +/**************************************************************************** + * arch/arm/src/xmc4/hardware/xmc4_ccu4.h + * + * Copyright (C) 2017 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * May include some logic from sample code provided by Infineon: + * + * Copyright (C) 2011-2015 Infineon Technologies AG. All rights reserved. + * + * Infineon Technologies AG (Infineon) is supplying this software for use + * with Infineon's microcontrollers. This file can be freely distributed + * within development tools that are supporting such microcontrollers. + * + * THIS SOFTWARE IS PROVIDED AS IS. NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS + * SOFTWARE. INFINEON SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, + * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ****************************************************************************/ + +/* Reference: XMC4500 Reference Manual V1.5 2014-07 Microcontrollers. */ + +#ifndef __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_CCU4_H +#define __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_CCU4_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/xmc4_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +/* CCU4 Global Registers */ + +#define XMC4_CCU4_GCTRL_OFFSET 0x0000 /* Module General Control Register */ +#define XMC4_CCU4_GSTAT_OFFSET 0x0004 /* General Slice Status Register */ +#define XMC4_CCU4_GIDLS_OFFSET 0x0008 /* General Idle Enable Register */ +#define XMC4_CCU4_GIDLC_OFFSET 0x000C /* General Idle Disable Register */ +#define XMC4_CCU4_GCSS_OFFSET 0x0010 /* General Channel Set Register */ +#define XMC4_CCU4_GCSC_OFFSET 0x0014 /* General Channel Clear Register */ +#define XMC4_CCU4_GCST_OFFSET 0x0018 /* General Channel Status Register */ +#define XMC4_CCU4_MIDR_OFFSET 0x0080 /* Module Identification Register */ + +/* CC40 Registers */ + +#define XMC4_CCU4_CC40INS_OFFSET 0x0100 /* Input Selector Unit Configuration */ +#define XMC4_CCU4_CC40CMC_OFFSET 0x0104 /* Connection Matrix Configuration */ +#define XMC4_CCU4_CC40TST_OFFSET 0x0108 /* Timer Run Status */ +#define XMC4_CCU4_CC40TCSET_OFFSET 0x010C /* Timer Run Set */ +#define XMC4_CCU4_CC40TCCLR_OFFSET 0x0110 /* Timer Run Clear */ +#define XMC4_CCU4_CC40TC_OFFSET 0x0114 /* General Timer Configuration */ +#define XMC4_CCU4_CC40PSL_OFFSET 0x0118 /* Output Passive Level Configuration */ +#define XMC4_CCU4_CC40DIT_OFFSET 0x011C /* Dither Configuration */ +#define XMC4_CCU4_CC40DITS_OFFSET 0x0120 /* Dither Shadow Register */ +#define XMC4_CCU4_CC40PSC_OFFSET 0x0124 /* Prescaler Configuration */ +#define XMC4_CCU4_CC40FPC_OFFSET 0x0128 /* Prescaler Compare Value */ +#define XMC4_CCU4_CC40FPCS_OFFSET 0x012C /* Prescaler Shadow Compare Value */ +#define XMC4_CCU4_CC40PR_OFFSET 0x0130 /* Timer Period Value */ +#define XMC4_CCU4_CC40PRS_OFFSET 0x0134 /* Timer Period Shadow Value */ +#define XMC4_CCU4_CC40CR_OFFSET 0x0138 /* Timer Compare Value */ +#define XMC4_CCU4_CC40CRS_OFFSET 0x013C /* Timer Compare Shadow Value */ +#define XMC4_CCU4_CC40TIMER_OFFSET 0x0170 /* Timer Current Value */ +#define XMC4_CCU4_CC40C0V_OFFSET 0x0174 /* Capture Register 0 Value */ +#define XMC4_CCU4_CC40C1V_OFFSET 0x0178 /* Capture Register 1 Value */ +#define XMC4_CCU4_CC40C2V_OFFSET 0x017C /* Capture Register 2 Value */ +#define XMC4_CCU4_CC40C3V_OFFSET 0x0180 /* Capture Register 3 Value */ +#define XMC4_CCU4_CC40INTS_OFFSET 0x01A0 /* Interrupt Status */ +#define XMC4_CCU4_CC40INTE_OFFSET 0x01A4 /* Interrupt Enable */ +#define XMC4_CCU4_CC40SRS_OFFSET 0x01A8 /* Interrupt Configuration */ +#define XMC4_CCU4_CC40SWS_OFFSET 0x01AC /* Interrupt Status Set */ +#define XMC4_CCU4_CC40SWR_OFFSET 0x01B0 /* Interrupt Status Clear */ +#define XMC4_CCU4_CC40ECRD0_OFFSET 0x01B8 /* Extended Read Back 0 */ +#define XMC4_CCU4_CC40ECRD1_OFFSET 0x01BC /* Extended Read Back 1 */ + +/* CC41 Registers */ + +#define XMC4_CCU4_CC41INS_OFFSET 0x0200 /* Input Selector Unit Configuration */ +#define XMC4_CCU4_CC41CMC_OFFSET 0x0204 /* Connection Matrix Configuration */ +#define XMC4_CCU4_CC41TST_OFFSET 0x0208 /* Timer Run Status */ +#define XMC4_CCU4_CC41TCSET_OFFSET 0x020C /* Timer Run Set */ +#define XMC4_CCU4_CC41TCCLR_OFFSET 0x0210 /* Timer Run Clear */ +#define XMC4_CCU4_CC41TC_OFFSET 0x0214 /* General Timer Configuration */ +#define XMC4_CCU4_CC41PSL_OFFSET 0x0218 /* Output Passive Level Configuration */ +#define XMC4_CCU4_CC41DIT_OFFSET 0x021C /* Dither Configuration */ +#define XMC4_CCU4_CC41DITS_OFFSET 0x0220 /* Dither Shadow Register */ +#define XMC4_CCU4_CC41PSC_OFFSET 0x0224 /* Prescaler Configuration */ +#define XMC4_CCU4_CC41FPC_OFFSET 0x0228 /* Prescaler Compare Value */ +#define XMC4_CCU4_CC41FPCS_OFFSET 0x022C /* Prescaler Shadow Compare Value */ +#define XMC4_CCU4_CC41PR_OFFSET 0x0230 /* Timer Period Value */ +#define XMC4_CCU4_CC41PRS_OFFSET 0x0234 /* Timer Period Shadow Value */ +#define XMC4_CCU4_CC41CR_OFFSET 0x0238 /* Timer Compare Value */ +#define XMC4_CCU4_CC41CRS_OFFSET 0x023C /* Timer Compare Shadow Value */ +#define XMC4_CCU4_CC41TIMER_OFFSET 0x0270 /* Timer Current Value */ +#define XMC4_CCU4_CC41C0V_OFFSET 0x0274 /* Capture Register 0 Value */ +#define XMC4_CCU4_CC41C1V_OFFSET 0x0278 /* Capture Register 1 Value */ +#define XMC4_CCU4_CC41C2V_OFFSET 0x027C /* Capture Register 2 Value */ +#define XMC4_CCU4_CC41C3V_OFFSET 0x0280 /* Capture Register 3 Value */ +#define XMC4_CCU4_CC41INTS_OFFSET 0x02A0 /* Interrupt Status */ +#define XMC4_CCU4_CC41INTE_OFFSET 0x02A4 /* Interrupt Enable */ +#define XMC4_CCU4_CC41SRS_OFFSET 0x02A8 /* Interrupt Configuration */ +#define XMC4_CCU4_CC41SWS_OFFSET 0x02AC /* Interrupt Status Set */ +#define XMC4_CCU4_CC41SWR_OFFSET 0x02B0 /* Interrupt Status Clear */ +#define XMC4_CCU4_CC41ECRD0_OFFSET 0x02B8 /* Extended Read Back 0 */ +#define XMC4_CCU4_CC41ECRD1_OFFSET 0x02BC /* Extended Read Back 1 */ + +/* CC42 Registers */ + +#define XMC4_CCU4_CC42INS_OFFSET 0x0300 /* Input Selector Unit Configuration */ +#define XMC4_CCU4_CC42CMC_OFFSET 0x0304 /* Connection Matrix Configuration */ +#define XMC4_CCU4_CC42TST_OFFSET 0x0308 /* Timer Run Status */ +#define XMC4_CCU4_CC42TCSET_OFFSET 0x030C /* Timer Run Set */ +#define XMC4_CCU4_CC42TCCLR_OFFSET 0x0310 /* Timer Run Clear */ +#define XMC4_CCU4_CC42TC_OFFSET 0x0314 /* General Timer Configuration */ +#define XMC4_CCU4_CC42PSL_OFFSET 0x0318 /* Output Passive Level Configuration */ +#define XMC4_CCU4_CC42DIT_OFFSET 0x031C /* Dither Configuration */ +#define XMC4_CCU4_CC42DITS_OFFSET 0x0320 /* Dither Shadow Register */ +#define XMC4_CCU4_CC42PSC_OFFSET 0x0324 /* Prescaler Configuration */ +#define XMC4_CCU4_CC42FPC_OFFSET 0x0328 /* Prescaler Compare Value */ +#define XMC4_CCU4_CC42FPCS_OFFSET 0x032C /* Prescaler Shadow Compare Value */ +#define XMC4_CCU4_CC42PR_OFFSET 0x0330 /* Timer Period Value */ +#define XMC4_CCU4_CC42PRS_OFFSET 0x0334 /* Timer Period Shadow Value */ +#define XMC4_CCU4_CC42CR_OFFSET 0x0338 /* Timer Compare Value */ +#define XMC4_CCU4_CC42CRS_OFFSET 0x033C /* Timer Compare Shadow Value */ +#define XMC4_CCU4_CC42TIMER_OFFSET 0x0370 /* Timer Current Value */ +#define XMC4_CCU4_CC42C0V_OFFSET 0x0374 /* Capture Register 0 Value */ +#define XMC4_CCU4_CC42C1V_OFFSET 0x0378 /* Capture Register 1 Value */ +#define XMC4_CCU4_CC42C2V_OFFSET 0x037C /* Capture Register 2 Value */ +#define XMC4_CCU4_CC42C3V_OFFSET 0x0380 /* Capture Register 3 Value */ +#define XMC4_CCU4_CC42INTS_OFFSET 0x03A0 /* Interrupt Status */ +#define XMC4_CCU4_CC42INTE_OFFSET 0x03A4 /* Interrupt Enable */ +#define XMC4_CCU4_CC42SRS_OFFSET 0x03A8 /* Interrupt Configuration */ +#define XMC4_CCU4_CC42SWS_OFFSET 0x03AC /* Interrupt Status Set */ +#define XMC4_CCU4_CC42SWR_OFFSET 0x03B0 /* Interrupt Status Clear */ +#define XMC4_CCU4_CC42ECRD0_OFFSET 0x03B8 /* Extended Read Back 0 */ +#define XMC4_CCU4_CC42ECRD1_OFFSET 0x03BC /* Extended Read Back 1 */ + +/* CC43 Registers */ + +#define XMC4_CCU4_CC43INS_OFFSET 0x0400 /* Input Selector Unit Configuration */ +#define XMC4_CCU4_CC43CMC_OFFSET 0x0404 /* Connection Matrix Configuration */ +#define XMC4_CCU4_CC43TST_OFFSET 0x0408 /* Timer Run Status */ +#define XMC4_CCU4_CC43TCSET_OFFSET 0x040C /* Timer Run Set */ +#define XMC4_CCU4_CC43TCCLR_OFFSET 0x0410 /* Timer Run Clear */ +#define XMC4_CCU4_CC43TC_OFFSET 0x0414 /* General Timer Configuration */ +#define XMC4_CCU4_CC43PSL_OFFSET 0x0418 /* Output Passive Level Configuration */ +#define XMC4_CCU4_CC43DIT_OFFSET 0x041C /* Dither Configuration */ +#define XMC4_CCU4_CC43DITS_OFFSET 0x0420 /* Dither Shadow Register */ +#define XMC4_CCU4_CC43PSC_OFFSET 0x0424 /* Prescaler Configuration */ +#define XMC4_CCU4_CC43FPC_OFFSET 0x0428 /* Prescaler Compare Value */ +#define XMC4_CCU4_CC43FPCS_OFFSET 0x042C /* Prescaler Shadow Compare Value */ +#define XMC4_CCU4_CC43PR_OFFSET 0x0430 /* Timer Period Value */ +#define XMC4_CCU4_CC43PRS_OFFSET 0x0434 /* Timer Period Shadow Value */ +#define XMC4_CCU4_CC43CR_OFFSET 0x0438 /* Timer Compare Value */ +#define XMC4_CCU4_CC43CRS_OFFSET 0x043C /* Timer Compare Shadow Value */ +#define XMC4_CCU4_CC43TIMER_OFFSET 0x0470 /* Timer Current Value */ +#define XMC4_CCU4_CC43C0V_OFFSET 0x0474 /* Capture Register 0 Value */ +#define XMC4_CCU4_CC43C1V_OFFSET 0x0478 /* Capture Register 1 Value */ +#define XMC4_CCU4_CC43C2V_OFFSET 0x047C /* Capture Register 2 Value */ +#define XMC4_CCU4_CC43C3V_OFFSET 0x0480 /* Capture Register 3 Value */ +#define XMC4_CCU4_CC43INTS_OFFSET 0x04A0 /* Interrupt Status */ +#define XMC4_CCU4_CC43INTE_OFFSET 0x04A4 /* Interrupt Enable */ +#define XMC4_CCU4_CC43SRS_OFFSET 0x04A8 /* Interrupt Configuration */ +#define XMC4_CCU4_CC43SWS_OFFSET 0x04AC /* Interrupt Status Set */ +#define XMC4_CCU4_CC43SWR_OFFSET 0x04B0 /* Interrupt Status Clear */ +#define XMC4_CCU4_CC43ECRD0_OFFSET 0x04B8 /* Extended Read Back 0 */ +#define XMC4_CCU4_CC43ECRD1_OFFSET 0x04BC /* Extended Read Back 1 */ + +/* Register Addresses *******************************************************/ + +/* CCU40 Global Registers */ + +#define XMC4_CCU40_GCTRL (XMC4_CCU40_BASE+XMC4_CCU4_GCTRL_OFFSET) +#define XMC4_CCU40_GSTAT (XMC4_CCU40_BASE+XMC4_CCU4_GSTAT_OFFSET) +#define XMC4_CCU40_GIDLS (XMC4_CCU40_BASE+XMC4_CCU4_GIDLS_OFFSET) +#define XMC4_CCU40_GIDLC (XMC4_CCU40_BASE+XMC4_CCU4_GIDLC_OFFSET) +#define XMC4_CCU40_GCSS (XMC4_CCU40_BASE+XMC4_CCU4_GCSS_OFFSET) +#define XMC4_CCU40_GCSC (XMC4_CCU40_BASE+XMC4_CCU4_GCSC_OFFSET) +#define XMC4_CCU40_GCST (XMC4_CCU40_BASE+XMC4_CCU4_GCST_OFFSET) +#define XMC4_CCU40_MIDR (XMC4_CCU40_BASE+XMC4_CCU4_MIDR_OFFSET) + +/* CCU40 CC40 Slice Registers */ + +#define XMC4_CCU40_CC40INS (XMC4_CCU40_BASE+XMC4_CCU4_CC40INS_OFFSET) +#define XMC4_CCU40_CC40CMC (XMC4_CCU40_BASE+XMC4_CCU4_CC40CMC_OFFSET) +#define XMC4_CCU40_CC40TST (XMC4_CCU40_BASE+XMC4_CCU4_CC40TST_OFFSET) +#define XMC4_CCU40_CC40TCSET (XMC4_CCU40_BASE+XMC4_CCU4_CC40TCSET_OFFSET) +#define XMC4_CCU40_CC40TCCLR (XMC4_CCU40_BASE+XMC4_CCU4_CC40TCCLR_OFFSET) +#define XMC4_CCU40_CC40TC (XMC4_CCU40_BASE+XMC4_CCU4_CC40TC_OFFSET) +#define XMC4_CCU40_CC40PSL (XMC4_CCU40_BASE+XMC4_CCU4_CC40PSL_OFFSET) +#define XMC4_CCU40_CC40DIT (XMC4_CCU40_BASE+XMC4_CCU4_CC40DIT_OFFSET) +#define XMC4_CCU40_CC40DITS (XMC4_CCU40_BASE+XMC4_CCU4_CC40DITS_OFFSET) +#define XMC4_CCU40_CC40PSC (XMC4_CCU40_BASE+XMC4_CCU4_CC40PSC_OFFSET) +#define XMC4_CCU40_CC40FPC (XMC4_CCU40_BASE+XMC4_CCU4_CC40FPC_OFFSET) +#define XMC4_CCU40_CC40FPCS (XMC4_CCU40_BASE+XMC4_CCU4_CC40FPCS_OFFSET) +#define XMC4_CCU40_CC40PR (XMC4_CCU40_BASE+XMC4_CCU4_CC40PR_OFFSET) +#define XMC4_CCU40_CC40PRS (XMC4_CCU40_BASE+XMC4_CCU4_CC40PRS_OFFSET) +#define XMC4_CCU40_CC40CR (XMC4_CCU40_BASE+XMC4_CCU4_CC40CR_OFFSET) +#define XMC4_CCU40_CC40CRS (XMC4_CCU40_BASE+XMC4_CCU4_CC40CRS_OFFSET) +#define XMC4_CCU40_CC40TIMER (XMC4_CCU40_BASE+XMC4_CCU4_CC40TIMER_OFFSET) +#define XMC4_CCU40_CC40C0V (XMC4_CCU40_BASE+XMC4_CCU4_CC40C0V_OFFSET) +#define XMC4_CCU40_CC40C1V (XMC4_CCU40_BASE+XMC4_CCU4_CC40C1V_OFFSET) +#define XMC4_CCU40_CC40C2V (XMC4_CCU40_BASE+XMC4_CCU4_CC40C2V_OFFSET) +#define XMC4_CCU40_CC40C3V (XMC4_CCU40_BASE+XMC4_CCU4_CC40C3V_OFFSET) +#define XMC4_CCU40_CC40INTS (XMC4_CCU40_BASE+XMC4_CCU4_CC40INTS_OFFSET) +#define XMC4_CCU40_CC40INTE (XMC4_CCU40_BASE+XMC4_CCU4_CC40INTE_OFFSET) +#define XMC4_CCU40_CC40SRS (XMC4_CCU40_BASE+XMC4_CCU4_CC40SRS_OFFSET) +#define XMC4_CCU40_CC40SWS (XMC4_CCU40_BASE+XMC4_CCU4_CC40SWS_OFFSET) +#define XMC4_CCU40_CC40SWR (XMC4_CCU40_BASE+XMC4_CCU4_CC40SWR_OFFSET) +#define XMC4_CCU40_CC40ECRD0 (XMC4_CCU40_BASE+XMC4_CCU4_CC40ECRD0_OFFSET) +#define XMC4_CCU40_CC40ECRD1 (XMC4_CCU40_BASE+XMC4_CCU4_CC40ECRD1_OFFSET) + +/* CCU40 CC41 Slice Registers */ + +#define XMC4_CCU40_CC41INS (XMC4_CCU40_BASE+XMC4_CCU4_CC41INS_OFFSET) +#define XMC4_CCU40_CC41CMC (XMC4_CCU40_BASE+XMC4_CCU4_CC41CMC_OFFSET) +#define XMC4_CCU40_CC41TST (XMC4_CCU40_BASE+XMC4_CCU4_CC41TST_OFFSET) +#define XMC4_CCU40_CC41TCSET (XMC4_CCU40_BASE+XMC4_CCU4_CC41TCSET_OFFSET) +#define XMC4_CCU40_CC41TCCLR (XMC4_CCU40_BASE+XMC4_CCU4_CC41TCCLR_OFFSET) +#define XMC4_CCU40_CC41TC (XMC4_CCU40_BASE+XMC4_CCU4_CC41TC_OFFSET) +#define XMC4_CCU40_CC41PSL (XMC4_CCU40_BASE+XMC4_CCU4_CC41PSL_OFFSET) +#define XMC4_CCU40_CC41DIT (XMC4_CCU40_BASE+XMC4_CCU4_CC41DIT_OFFSET) +#define XMC4_CCU40_CC41DITS (XMC4_CCU40_BASE+XMC4_CCU4_CC41DITS_OFFSET) +#define XMC4_CCU40_CC41PSC (XMC4_CCU40_BASE+XMC4_CCU4_CC41PSC_OFFSET) +#define XMC4_CCU40_CC41FPC (XMC4_CCU40_BASE+XMC4_CCU4_CC41FPC_OFFSET) +#define XMC4_CCU40_CC41FPCS (XMC4_CCU40_BASE+XMC4_CCU4_CC41FPCS_OFFSET) +#define XMC4_CCU40_CC41PR (XMC4_CCU40_BASE+XMC4_CCU4_CC41PR_OFFSET) +#define XMC4_CCU40_CC41PRS (XMC4_CCU40_BASE+XMC4_CCU4_CC41PRS_OFFSET) +#define XMC4_CCU40_CC41CR (XMC4_CCU40_BASE+XMC4_CCU4_CC41CR_OFFSET) +#define XMC4_CCU40_CC41CRS (XMC4_CCU40_BASE+XMC4_CCU4_CC41CRS_OFFSET) +#define XMC4_CCU40_CC41TIMER (XMC4_CCU40_BASE+XMC4_CCU4_CC41TIMER_OFFSET) +#define XMC4_CCU40_CC41C0V (XMC4_CCU40_BASE+XMC4_CCU4_CC41C0V_OFFSET) +#define XMC4_CCU40_CC41C1V (XMC4_CCU40_BASE+XMC4_CCU4_CC41C1V_OFFSET) +#define XMC4_CCU40_CC41C2V (XMC4_CCU40_BASE+XMC4_CCU4_CC41C2V_OFFSET) +#define XMC4_CCU40_CC41C3V (XMC4_CCU40_BASE+XMC4_CCU4_CC41C3V_OFFSET) +#define XMC4_CCU40_CC41INTS (XMC4_CCU40_BASE+XMC4_CCU4_CC41INTS_OFFSET) +#define XMC4_CCU40_CC41INTE (XMC4_CCU40_BASE+XMC4_CCU4_CC41INTE_OFFSET) +#define XMC4_CCU40_CC41SRS (XMC4_CCU40_BASE+XMC4_CCU4_CC41SRS_OFFSET) +#define XMC4_CCU40_CC41SWS (XMC4_CCU40_BASE+XMC4_CCU4_CC41SWS_OFFSET) +#define XMC4_CCU40_CC41SWR (XMC4_CCU40_BASE+XMC4_CCU4_CC41SWR_OFFSET) +#define XMC4_CCU40_CC41ECRD0 (XMC4_CCU40_BASE+XMC4_CCU4_CC41ECRD0_OFFSET) +#define XMC4_CCU40_CC41ECRD1 (XMC4_CCU40_BASE+XMC4_CCU4_CC41ECRD1_OFFSET) + +/* CCU40 CC42 Slice Registers */ + +#define XMC4_CCU40_CC42INS (XMC4_CCU40_BASE+XMC4_CCU4_CC42INS_OFFSET) +#define XMC4_CCU40_CC42CMC (XMC4_CCU40_BASE+XMC4_CCU4_CC42CMC_OFFSET) +#define XMC4_CCU40_CC42TST (XMC4_CCU40_BASE+XMC4_CCU4_CC42TST_OFFSET) +#define XMC4_CCU40_CC42TCSET (XMC4_CCU40_BASE+XMC4_CCU4_CC42TCSET_OFFSET) +#define XMC4_CCU40_CC42TCCLR (XMC4_CCU40_BASE+XMC4_CCU4_CC42TCCLR_OFFSET) +#define XMC4_CCU40_CC42TC (XMC4_CCU40_BASE+XMC4_CCU4_CC42TC_OFFSET) +#define XMC4_CCU40_CC42PSL (XMC4_CCU40_BASE+XMC4_CCU4_CC42PSL_OFFSET) +#define XMC4_CCU40_CC42DIT (XMC4_CCU40_BASE+XMC4_CCU4_CC42DIT_OFFSET) +#define XMC4_CCU40_CC42DITS (XMC4_CCU40_BASE+XMC4_CCU4_CC42DITS_OFFSET) +#define XMC4_CCU40_CC42PSC (XMC4_CCU40_BASE+XMC4_CCU4_CC42PSC_OFFSET) +#define XMC4_CCU40_CC42FPC (XMC4_CCU40_BASE+XMC4_CCU4_CC42FPC_OFFSET) +#define XMC4_CCU40_CC42FPCS (XMC4_CCU40_BASE+XMC4_CCU4_CC42FPCS_OFFSET) +#define XMC4_CCU40_CC42PR (XMC4_CCU40_BASE+XMC4_CCU4_CC42PR_OFFSET) +#define XMC4_CCU40_CC42PRS (XMC4_CCU40_BASE+XMC4_CCU4_CC42PRS_OFFSET) +#define XMC4_CCU40_CC42CR (XMC4_CCU40_BASE+XMC4_CCU4_CC42CR_OFFSET) +#define XMC4_CCU40_CC42CRS (XMC4_CCU40_BASE+XMC4_CCU4_CC42CRS_OFFSET) +#define XMC4_CCU40_CC42TIMER (XMC4_CCU40_BASE+XMC4_CCU4_CC42TIMER_OFFSET) +#define XMC4_CCU40_CC42C0V (XMC4_CCU40_BASE+XMC4_CCU4_CC42C0V_OFFSET) +#define XMC4_CCU40_CC42C1V (XMC4_CCU40_BASE+XMC4_CCU4_CC42C1V_OFFSET) +#define XMC4_CCU40_CC42C2V (XMC4_CCU40_BASE+XMC4_CCU4_CC42C2V_OFFSET) +#define XMC4_CCU40_CC42C3V (XMC4_CCU40_BASE+XMC4_CCU4_CC42C3V_OFFSET) +#define XMC4_CCU40_CC42INTS (XMC4_CCU40_BASE+XMC4_CCU4_CC42INTS_OFFSET) +#define XMC4_CCU40_CC42INTE (XMC4_CCU40_BASE+XMC4_CCU4_CC42INTE_OFFSET) +#define XMC4_CCU40_CC42SRS (XMC4_CCU40_BASE+XMC4_CCU4_CC42SRS_OFFSET) +#define XMC4_CCU40_CC42SWS (XMC4_CCU40_BASE+XMC4_CCU4_CC42SWS_OFFSET) +#define XMC4_CCU40_CC42SWR (XMC4_CCU40_BASE+XMC4_CCU4_CC42SWR_OFFSET) +#define XMC4_CCU40_CC42ECRD0 (XMC4_CCU40_BASE+XMC4_CCU4_CC42ECRD0_OFFSET) +#define XMC4_CCU40_CC42ECRD1 (XMC4_CCU40_BASE+XMC4_CCU4_CC42ECRD1_OFFSET) + +/* CCU40 CC43 Slice Registers */ + +#define XMC4_CCU40_CC43INS (XMC4_CCU40_BASE+XMC4_CCU4_CC43INS_OFFSET) +#define XMC4_CCU40_CC43CMC (XMC4_CCU40_BASE+XMC4_CCU4_CC43CMC_OFFSET) +#define XMC4_CCU40_CC43TST (XMC4_CCU40_BASE+XMC4_CCU4_CC43TST_OFFSET) +#define XMC4_CCU40_CC43TCSET (XMC4_CCU40_BASE+XMC4_CCU4_CC43TCSET_OFFSET) +#define XMC4_CCU40_CC43TCCLR (XMC4_CCU40_BASE+XMC4_CCU4_CC43TCCLR_OFFSET) +#define XMC4_CCU40_CC43TC (XMC4_CCU40_BASE+XMC4_CCU4_CC43TC_OFFSET) +#define XMC4_CCU40_CC43PSL (XMC4_CCU40_BASE+XMC4_CCU4_CC43PSL_OFFSET) +#define XMC4_CCU40_CC43DIT (XMC4_CCU40_BASE+XMC4_CCU4_CC43DIT_OFFSET) +#define XMC4_CCU40_CC43DITS (XMC4_CCU40_BASE+XMC4_CCU4_CC43DITS_OFFSET) +#define XMC4_CCU40_CC43PSC (XMC4_CCU40_BASE+XMC4_CCU4_CC43PSC_OFFSET) +#define XMC4_CCU40_CC43FPC (XMC4_CCU40_BASE+XMC4_CCU4_CC43FPC_OFFSET) +#define XMC4_CCU40_CC43FPCS (XMC4_CCU40_BASE+XMC4_CCU4_CC43FPCS_OFFSET) +#define XMC4_CCU40_CC43PR (XMC4_CCU40_BASE+XMC4_CCU4_CC43PR_OFFSET) +#define XMC4_CCU40_CC43PRS (XMC4_CCU40_BASE+XMC4_CCU4_CC43PRS_OFFSET) +#define XMC4_CCU40_CC43CR (XMC4_CCU40_BASE+XMC4_CCU4_CC43CR_OFFSET) +#define XMC4_CCU40_CC43CRS (XMC4_CCU40_BASE+XMC4_CCU4_CC43CRS_OFFSET) +#define XMC4_CCU40_CC43TIMER (XMC4_CCU40_BASE+XMC4_CCU4_CC43TIMER_OFFSET) +#define XMC4_CCU40_CC43C0V (XMC4_CCU40_BASE+XMC4_CCU4_CC43C0V_OFFSET) +#define XMC4_CCU40_CC43C1V (XMC4_CCU40_BASE+XMC4_CCU4_CC43C1V_OFFSET) +#define XMC4_CCU40_CC43C2V (XMC4_CCU40_BASE+XMC4_CCU4_CC43C2V_OFFSET) +#define XMC4_CCU40_CC43C3V (XMC4_CCU40_BASE+XMC4_CCU4_CC43C3V_OFFSET) +#define XMC4_CCU40_CC43INTS (XMC4_CCU40_BASE+XMC4_CCU4_CC43INTS_OFFSET) +#define XMC4_CCU40_CC43INTE (XMC4_CCU40_BASE+XMC4_CCU4_CC43INTE_OFFSET) +#define XMC4_CCU40_CC43SRS (XMC4_CCU40_BASE+XMC4_CCU4_CC43SRS_OFFSET) +#define XMC4_CCU40_CC43SWS (XMC4_CCU40_BASE+XMC4_CCU4_CC43SWS_OFFSET) +#define XMC4_CCU40_CC43SWR (XMC4_CCU40_BASE+XMC4_CCU4_CC43SWR_OFFSET) +#define XMC4_CCU40_CC43ECRD0 (XMC4_CCU40_BASE+XMC4_CCU4_CC43ECRD0_OFFSET) +#define XMC4_CCU40_CC43ECRD1 (XMC4_CCU40_BASE+XMC4_CCU4_CC43ECRD1_OFFSET) + +/* CCU41 Global Registers */ + +#define XMC4_CCU41_GCTRL (XMC4_CCU41_BASE+XMC4_CCU4_GCTRL_OFFSET) +#define XMC4_CCU41_GSTAT (XMC4_CCU41_BASE+XMC4_CCU4_GSTAT_OFFSET) +#define XMC4_CCU41_GIDLS (XMC4_CCU41_BASE+XMC4_CCU4_GIDLS_OFFSET) +#define XMC4_CCU41_GIDLC (XMC4_CCU41_BASE+XMC4_CCU4_GIDLC_OFFSET) +#define XMC4_CCU41_GCSS (XMC4_CCU41_BASE+XMC4_CCU4_GCSS_OFFSET) +#define XMC4_CCU41_GCSC (XMC4_CCU41_BASE+XMC4_CCU4_GCSC_OFFSET) +#define XMC4_CCU41_GCST (XMC4_CCU41_BASE+XMC4_CCU4_GCST_OFFSET) +#define XMC4_CCU41_MIDR (XMC4_CCU41_BASE+XMC4_CCU4_MIDR_OFFSET) + +/* CCU41 CC40 Slice Registers */ + +#define XMC4_CCU41_CC40INS (XMC4_CCU41_BASE+XMC4_CCU4_CC40INS_OFFSET) +#define XMC4_CCU41_CC40CMC (XMC4_CCU41_BASE+XMC4_CCU4_CC40CMC_OFFSET) +#define XMC4_CCU41_CC40TST (XMC4_CCU41_BASE+XMC4_CCU4_CC40TST_OFFSET) +#define XMC4_CCU41_CC40TCSET (XMC4_CCU41_BASE+XMC4_CCU4_CC40TCSET_OFFSET) +#define XMC4_CCU41_CC40TCCLR (XMC4_CCU41_BASE+XMC4_CCU4_CC40TCCLR_OFFSET) +#define XMC4_CCU41_CC40TC (XMC4_CCU41_BASE+XMC4_CCU4_CC40TC_OFFSET) +#define XMC4_CCU41_CC40PSL (XMC4_CCU41_BASE+XMC4_CCU4_CC40PSL_OFFSET) +#define XMC4_CCU41_CC40DIT (XMC4_CCU41_BASE+XMC4_CCU4_CC40DIT_OFFSET) +#define XMC4_CCU41_CC40DITS (XMC4_CCU41_BASE+XMC4_CCU4_CC40DITS_OFFSET) +#define XMC4_CCU41_CC40PSC (XMC4_CCU41_BASE+XMC4_CCU4_CC40PSC_OFFSET) +#define XMC4_CCU41_CC40FPC (XMC4_CCU41_BASE+XMC4_CCU4_CC40FPC_OFFSET) +#define XMC4_CCU41_CC40FPCS (XMC4_CCU41_BASE+XMC4_CCU4_CC40FPCS_OFFSET) +#define XMC4_CCU41_CC40PR (XMC4_CCU41_BASE+XMC4_CCU4_CC40PR_OFFSET) +#define XMC4_CCU41_CC40PRS (XMC4_CCU41_BASE+XMC4_CCU4_CC40PRS_OFFSET) +#define XMC4_CCU41_CC40CR (XMC4_CCU41_BASE+XMC4_CCU4_CC40CR_OFFSET) +#define XMC4_CCU41_CC40CRS (XMC4_CCU41_BASE+XMC4_CCU4_CC40CRS_OFFSET) +#define XMC4_CCU41_CC40TIMER (XMC4_CCU41_BASE+XMC4_CCU4_CC40TIMER_OFFSET) +#define XMC4_CCU41_CC40C0V (XMC4_CCU41_BASE+XMC4_CCU4_CC40C0V_OFFSET) +#define XMC4_CCU41_CC40C1V (XMC4_CCU41_BASE+XMC4_CCU4_CC40C1V_OFFSET) +#define XMC4_CCU41_CC40C2V (XMC4_CCU41_BASE+XMC4_CCU4_CC40C2V_OFFSET) +#define XMC4_CCU41_CC40C3V (XMC4_CCU41_BASE+XMC4_CCU4_CC40C3V_OFFSET) +#define XMC4_CCU41_CC40INTS (XMC4_CCU41_BASE+XMC4_CCU4_CC40INTS_OFFSET) +#define XMC4_CCU41_CC40INTE (XMC4_CCU41_BASE+XMC4_CCU4_CC40INTE_OFFSET) +#define XMC4_CCU41_CC40SRS (XMC4_CCU41_BASE+XMC4_CCU4_CC40SRS_OFFSET) +#define XMC4_CCU41_CC40SWS (XMC4_CCU41_BASE+XMC4_CCU4_CC40SWS_OFFSET) +#define XMC4_CCU41_CC40SWR (XMC4_CCU41_BASE+XMC4_CCU4_CC40SWR_OFFSET) +#define XMC4_CCU41_CC40ECRD0 (XMC4_CCU41_BASE+XMC4_CCU4_CC40ECRD0_OFFSET) +#define XMC4_CCU41_CC40ECRD1 (XMC4_CCU41_BASE+XMC4_CCU4_CC40ECRD1_OFFSET) + +/* CCU41 CC41 Slice Registers */ + +#define XMC4_CCU41_CC41INS (XMC4_CCU41_BASE+XMC4_CCU4_CC41INS_OFFSET) +#define XMC4_CCU41_CC41CMC (XMC4_CCU41_BASE+XMC4_CCU4_CC41CMC_OFFSET) +#define XMC4_CCU41_CC41TST (XMC4_CCU41_BASE+XMC4_CCU4_CC41TST_OFFSET) +#define XMC4_CCU41_CC41TCSET (XMC4_CCU41_BASE+XMC4_CCU4_CC41TCSET_OFFSET) +#define XMC4_CCU41_CC41TCCLR (XMC4_CCU41_BASE+XMC4_CCU4_CC41TCCLR_OFFSET) +#define XMC4_CCU41_CC41TC (XMC4_CCU41_BASE+XMC4_CCU4_CC41TC_OFFSET) +#define XMC4_CCU41_CC41PSL (XMC4_CCU41_BASE+XMC4_CCU4_CC41PSL_OFFSET) +#define XMC4_CCU41_CC41DIT (XMC4_CCU41_BASE+XMC4_CCU4_CC41DIT_OFFSET) +#define XMC4_CCU41_CC41DITS (XMC4_CCU41_BASE+XMC4_CCU4_CC41DITS_OFFSET) +#define XMC4_CCU41_CC41PSC (XMC4_CCU41_BASE+XMC4_CCU4_CC41PSC_OFFSET) +#define XMC4_CCU41_CC41FPC (XMC4_CCU41_BASE+XMC4_CCU4_CC41FPC_OFFSET) +#define XMC4_CCU41_CC41FPCS (XMC4_CCU41_BASE+XMC4_CCU4_CC41FPCS_OFFSET) +#define XMC4_CCU41_CC41PR (XMC4_CCU41_BASE+XMC4_CCU4_CC41PR_OFFSET) +#define XMC4_CCU41_CC41PRS (XMC4_CCU41_BASE+XMC4_CCU4_CC41PRS_OFFSET) +#define XMC4_CCU41_CC41CR (XMC4_CCU41_BASE+XMC4_CCU4_CC41CR_OFFSET) +#define XMC4_CCU41_CC41CRS (XMC4_CCU41_BASE+XMC4_CCU4_CC41CRS_OFFSET) +#define XMC4_CCU41_CC41TIMER (XMC4_CCU41_BASE+XMC4_CCU4_CC41TIMER_OFFSET) +#define XMC4_CCU41_CC41C0V (XMC4_CCU41_BASE+XMC4_CCU4_CC41C0V_OFFSET) +#define XMC4_CCU41_CC41C1V (XMC4_CCU41_BASE+XMC4_CCU4_CC41C1V_OFFSET) +#define XMC4_CCU41_CC41C2V (XMC4_CCU41_BASE+XMC4_CCU4_CC41C2V_OFFSET) +#define XMC4_CCU41_CC41C3V (XMC4_CCU41_BASE+XMC4_CCU4_CC41C3V_OFFSET) +#define XMC4_CCU41_CC41INTS (XMC4_CCU41_BASE+XMC4_CCU4_CC41INTS_OFFSET) +#define XMC4_CCU41_CC41INTE (XMC4_CCU41_BASE+XMC4_CCU4_CC41INTE_OFFSET) +#define XMC4_CCU41_CC41SRS (XMC4_CCU41_BASE+XMC4_CCU4_CC41SRS_OFFSET) +#define XMC4_CCU41_CC41SWS (XMC4_CCU41_BASE+XMC4_CCU4_CC41SWS_OFFSET) +#define XMC4_CCU41_CC41SWR (XMC4_CCU41_BASE+XMC4_CCU4_CC41SWR_OFFSET) +#define XMC4_CCU41_CC41ECRD0 (XMC4_CCU41_BASE+XMC4_CCU4_CC41ECRD0_OFFSET) +#define XMC4_CCU41_CC41ECRD1 (XMC4_CCU41_BASE+XMC4_CCU4_CC41ECRD1_OFFSET) + +/* CCU41 CC42 Slice Registers */ + +#define XMC4_CCU41_CC42INS (XMC4_CCU41_BASE+XMC4_CCU4_CC42INS_OFFSET) +#define XMC4_CCU41_CC42CMC (XMC4_CCU41_BASE+XMC4_CCU4_CC42CMC_OFFSET) +#define XMC4_CCU41_CC42TST (XMC4_CCU41_BASE+XMC4_CCU4_CC42TST_OFFSET) +#define XMC4_CCU41_CC42TCSET (XMC4_CCU41_BASE+XMC4_CCU4_CC42TCSET_OFFSET) +#define XMC4_CCU41_CC42TCCLR (XMC4_CCU41_BASE+XMC4_CCU4_CC42TCCLR_OFFSET) +#define XMC4_CCU41_CC42TC (XMC4_CCU41_BASE+XMC4_CCU4_CC42TC_OFFSET) +#define XMC4_CCU41_CC42PSL (XMC4_CCU41_BASE+XMC4_CCU4_CC42PSL_OFFSET) +#define XMC4_CCU41_CC42DIT (XMC4_CCU41_BASE+XMC4_CCU4_CC42DIT_OFFSET) +#define XMC4_CCU41_CC42DITS (XMC4_CCU41_BASE+XMC4_CCU4_CC42DITS_OFFSET) +#define XMC4_CCU41_CC42PSC (XMC4_CCU41_BASE+XMC4_CCU4_CC42PSC_OFFSET) +#define XMC4_CCU41_CC42FPC (XMC4_CCU41_BASE+XMC4_CCU4_CC42FPC_OFFSET) +#define XMC4_CCU41_CC42FPCS (XMC4_CCU41_BASE+XMC4_CCU4_CC42FPCS_OFFSET) +#define XMC4_CCU41_CC42PR (XMC4_CCU41_BASE+XMC4_CCU4_CC42PR_OFFSET) +#define XMC4_CCU41_CC42PRS (XMC4_CCU41_BASE+XMC4_CCU4_CC42PRS_OFFSET) +#define XMC4_CCU41_CC42CR (XMC4_CCU41_BASE+XMC4_CCU4_CC42CR_OFFSET) +#define XMC4_CCU41_CC42CRS (XMC4_CCU41_BASE+XMC4_CCU4_CC42CRS_OFFSET) +#define XMC4_CCU41_CC42TIMER (XMC4_CCU41_BASE+XMC4_CCU4_CC42TIMER_OFFSET) +#define XMC4_CCU41_CC42C0V (XMC4_CCU41_BASE+XMC4_CCU4_CC42C0V_OFFSET) +#define XMC4_CCU41_CC42C1V (XMC4_CCU41_BASE+XMC4_CCU4_CC42C1V_OFFSET) +#define XMC4_CCU41_CC42C2V (XMC4_CCU41_BASE+XMC4_CCU4_CC42C2V_OFFSET) +#define XMC4_CCU41_CC42C3V (XMC4_CCU41_BASE+XMC4_CCU4_CC42C3V_OFFSET) +#define XMC4_CCU41_CC42INTS (XMC4_CCU41_BASE+XMC4_CCU4_CC42INTS_OFFSET) +#define XMC4_CCU41_CC42INTE (XMC4_CCU41_BASE+XMC4_CCU4_CC42INTE_OFFSET) +#define XMC4_CCU41_CC42SRS (XMC4_CCU41_BASE+XMC4_CCU4_CC42SRS_OFFSET) +#define XMC4_CCU41_CC42SWS (XMC4_CCU41_BASE+XMC4_CCU4_CC42SWS_OFFSET) +#define XMC4_CCU41_CC42SWR (XMC4_CCU41_BASE+XMC4_CCU4_CC42SWR_OFFSET) +#define XMC4_CCU41_CC42ECRD0 (XMC4_CCU41_BASE+XMC4_CCU4_CC42ECRD0_OFFSET) +#define XMC4_CCU41_CC42ECRD1 (XMC4_CCU41_BASE+XMC4_CCU4_CC42ECRD1_OFFSET) + +/* CCU41 CC43 Slice Registers */ + +#define XMC4_CCU41_CC43INS (XMC4_CCU41_BASE+XMC4_CCU4_CC43INS_OFFSET) +#define XMC4_CCU41_CC43CMC (XMC4_CCU41_BASE+XMC4_CCU4_CC43CMC_OFFSET) +#define XMC4_CCU41_CC43TST (XMC4_CCU41_BASE+XMC4_CCU4_CC43TST_OFFSET) +#define XMC4_CCU41_CC43TCSET (XMC4_CCU41_BASE+XMC4_CCU4_CC43TCSET_OFFSET) +#define XMC4_CCU41_CC43TCCLR (XMC4_CCU41_BASE+XMC4_CCU4_CC43TCCLR_OFFSET) +#define XMC4_CCU41_CC43TC (XMC4_CCU41_BASE+XMC4_CCU4_CC43TC_OFFSET) +#define XMC4_CCU41_CC43PSL (XMC4_CCU41_BASE+XMC4_CCU4_CC43PSL_OFFSET) +#define XMC4_CCU41_CC43DIT (XMC4_CCU41_BASE+XMC4_CCU4_CC43DIT_OFFSET) +#define XMC4_CCU41_CC43DITS (XMC4_CCU41_BASE+XMC4_CCU4_CC43DITS_OFFSET) +#define XMC4_CCU41_CC43PSC (XMC4_CCU41_BASE+XMC4_CCU4_CC43PSC_OFFSET) +#define XMC4_CCU41_CC43FPC (XMC4_CCU41_BASE+XMC4_CCU4_CC43FPC_OFFSET) +#define XMC4_CCU41_CC43FPCS (XMC4_CCU41_BASE+XMC4_CCU4_CC43FPCS_OFFSET) +#define XMC4_CCU41_CC43PR (XMC4_CCU41_BASE+XMC4_CCU4_CC43PR_OFFSET) +#define XMC4_CCU41_CC43PRS (XMC4_CCU41_BASE+XMC4_CCU4_CC43PRS_OFFSET) +#define XMC4_CCU41_CC43CR (XMC4_CCU41_BASE+XMC4_CCU4_CC43CR_OFFSET) +#define XMC4_CCU41_CC43CRS (XMC4_CCU41_BASE+XMC4_CCU4_CC43CRS_OFFSET) +#define XMC4_CCU41_CC43TIMER (XMC4_CCU41_BASE+XMC4_CCU4_CC43TIMER_OFFSET) +#define XMC4_CCU41_CC43C0V (XMC4_CCU41_BASE+XMC4_CCU4_CC43C0V_OFFSET) +#define XMC4_CCU41_CC43C1V (XMC4_CCU41_BASE+XMC4_CCU4_CC43C1V_OFFSET) +#define XMC4_CCU41_CC43C2V (XMC4_CCU41_BASE+XMC4_CCU4_CC43C2V_OFFSET) +#define XMC4_CCU41_CC43C3V (XMC4_CCU41_BASE+XMC4_CCU4_CC43C3V_OFFSET) +#define XMC4_CCU41_CC43INTS (XMC4_CCU41_BASE+XMC4_CCU4_CC43INTS_OFFSET) +#define XMC4_CCU41_CC43INTE (XMC4_CCU41_BASE+XMC4_CCU4_CC43INTE_OFFSET) +#define XMC4_CCU41_CC43SRS (XMC4_CCU41_BASE+XMC4_CCU4_CC43SRS_OFFSET) +#define XMC4_CCU41_CC43SWS (XMC4_CCU41_BASE+XMC4_CCU4_CC43SWS_OFFSET) +#define XMC4_CCU41_CC43SWR (XMC4_CCU41_BASE+XMC4_CCU4_CC43SWR_OFFSET) +#define XMC4_CCU41_CC43ECRD0 (XMC4_CCU41_BASE+XMC4_CCU4_CC43ECRD0_OFFSET) +#define XMC4_CCU41_CC43ECRD1 (XMC4_CCU41_BASE+XMC4_CCU4_CC43ECRD1_OFFSET) + +/* CCU42 Global Registers */ + +#define XMC4_CCU42_GCTRL (XMC4_CCU42_BASE+XMC4_CCU4_GCTRL_OFFSET) +#define XMC4_CCU42_GSTAT (XMC4_CCU42_BASE+XMC4_CCU4_GSTAT_OFFSET) +#define XMC4_CCU42_GIDLS (XMC4_CCU42_BASE+XMC4_CCU4_GIDLS_OFFSET) +#define XMC4_CCU42_GIDLC (XMC4_CCU42_BASE+XMC4_CCU4_GIDLC_OFFSET) +#define XMC4_CCU42_GCSS (XMC4_CCU42_BASE+XMC4_CCU4_GCSS_OFFSET) +#define XMC4_CCU42_GCSC (XMC4_CCU42_BASE+XMC4_CCU4_GCSC_OFFSET) +#define XMC4_CCU42_GCST (XMC4_CCU42_BASE+XMC4_CCU4_GCST_OFFSET) +#define XMC4_CCU42_MIDR (XMC4_CCU42_BASE+XMC4_CCU4_MIDR_OFFSET) + +/* CCU42 CC40 Slice Registers */ + +#define XMC4_CCU42_CC40INS (XMC4_CCU42_BASE+XMC4_CCU4_CC40INS_OFFSET) +#define XMC4_CCU42_CC40CMC (XMC4_CCU42_BASE+XMC4_CCU4_CC40CMC_OFFSET) +#define XMC4_CCU42_CC40TST (XMC4_CCU42_BASE+XMC4_CCU4_CC40TST_OFFSET) +#define XMC4_CCU42_CC40TCSET (XMC4_CCU42_BASE+XMC4_CCU4_CC40TCSET_OFFSET) +#define XMC4_CCU42_CC40TCCLR (XMC4_CCU42_BASE+XMC4_CCU4_CC40TCCLR_OFFSET) +#define XMC4_CCU42_CC40TC (XMC4_CCU42_BASE+XMC4_CCU4_CC40TC_OFFSET) +#define XMC4_CCU42_CC40PSL (XMC4_CCU42_BASE+XMC4_CCU4_CC40PSL_OFFSET) +#define XMC4_CCU42_CC40DIT (XMC4_CCU42_BASE+XMC4_CCU4_CC40DIT_OFFSET) +#define XMC4_CCU42_CC40DITS (XMC4_CCU42_BASE+XMC4_CCU4_CC40DITS_OFFSET) +#define XMC4_CCU42_CC40PSC (XMC4_CCU42_BASE+XMC4_CCU4_CC40PSC_OFFSET) +#define XMC4_CCU42_CC40FPC (XMC4_CCU42_BASE+XMC4_CCU4_CC40FPC_OFFSET) +#define XMC4_CCU42_CC40FPCS (XMC4_CCU42_BASE+XMC4_CCU4_CC40FPCS_OFFSET) +#define XMC4_CCU42_CC40PR (XMC4_CCU42_BASE+XMC4_CCU4_CC40PR_OFFSET) +#define XMC4_CCU42_CC40PRS (XMC4_CCU42_BASE+XMC4_CCU4_CC40PRS_OFFSET) +#define XMC4_CCU42_CC40CR (XMC4_CCU42_BASE+XMC4_CCU4_CC40CR_OFFSET) +#define XMC4_CCU42_CC40CRS (XMC4_CCU42_BASE+XMC4_CCU4_CC40CRS_OFFSET) +#define XMC4_CCU42_CC40TIMER (XMC4_CCU42_BASE+XMC4_CCU4_CC40TIMER_OFFSET) +#define XMC4_CCU42_CC40C0V (XMC4_CCU42_BASE+XMC4_CCU4_CC40C0V_OFFSET) +#define XMC4_CCU42_CC40C1V (XMC4_CCU42_BASE+XMC4_CCU4_CC40C1V_OFFSET) +#define XMC4_CCU42_CC40C2V (XMC4_CCU42_BASE+XMC4_CCU4_CC40C2V_OFFSET) +#define XMC4_CCU42_CC40C3V (XMC4_CCU42_BASE+XMC4_CCU4_CC40C3V_OFFSET) +#define XMC4_CCU42_CC40INTS (XMC4_CCU42_BASE+XMC4_CCU4_CC40INTS_OFFSET) +#define XMC4_CCU42_CC40INTE (XMC4_CCU42_BASE+XMC4_CCU4_CC40INTE_OFFSET) +#define XMC4_CCU42_CC40SRS (XMC4_CCU42_BASE+XMC4_CCU4_CC40SRS_OFFSET) +#define XMC4_CCU42_CC40SWS (XMC4_CCU42_BASE+XMC4_CCU4_CC40SWS_OFFSET) +#define XMC4_CCU42_CC40SWR (XMC4_CCU42_BASE+XMC4_CCU4_CC40SWR_OFFSET) +#define XMC4_CCU42_CC40ECRD0 (XMC4_CCU42_BASE+XMC4_CCU4_CC40ECRD0_OFFSET) +#define XMC4_CCU42_CC40ECRD1 (XMC4_CCU42_BASE+XMC4_CCU4_CC40ECRD1_OFFSET) + +/* CCU42 CC41 Slice Registers */ + +#define XMC4_CCU42_CC41INS (XMC4_CCU42_BASE+XMC4_CCU4_CC41INS_OFFSET) +#define XMC4_CCU42_CC41CMC (XMC4_CCU42_BASE+XMC4_CCU4_CC41CMC_OFFSET) +#define XMC4_CCU42_CC41TST (XMC4_CCU42_BASE+XMC4_CCU4_CC41TST_OFFSET) +#define XMC4_CCU42_CC41TCSET (XMC4_CCU42_BASE+XMC4_CCU4_CC41TCSET_OFFSET) +#define XMC4_CCU42_CC41TCCLR (XMC4_CCU42_BASE+XMC4_CCU4_CC41TCCLR_OFFSET) +#define XMC4_CCU42_CC41TC (XMC4_CCU42_BASE+XMC4_CCU4_CC41TC_OFFSET) +#define XMC4_CCU42_CC41PSL (XMC4_CCU42_BASE+XMC4_CCU4_CC41PSL_OFFSET) +#define XMC4_CCU42_CC41DIT (XMC4_CCU42_BASE+XMC4_CCU4_CC41DIT_OFFSET) +#define XMC4_CCU42_CC41DITS (XMC4_CCU42_BASE+XMC4_CCU4_CC41DITS_OFFSET) +#define XMC4_CCU42_CC41PSC (XMC4_CCU42_BASE+XMC4_CCU4_CC41PSC_OFFSET) +#define XMC4_CCU42_CC41FPC (XMC4_CCU42_BASE+XMC4_CCU4_CC41FPC_OFFSET) +#define XMC4_CCU42_CC41FPCS (XMC4_CCU42_BASE+XMC4_CCU4_CC41FPCS_OFFSET) +#define XMC4_CCU42_CC41PR (XMC4_CCU42_BASE+XMC4_CCU4_CC41PR_OFFSET) +#define XMC4_CCU42_CC41PRS (XMC4_CCU42_BASE+XMC4_CCU4_CC41PRS_OFFSET) +#define XMC4_CCU42_CC41CR (XMC4_CCU42_BASE+XMC4_CCU4_CC41CR_OFFSET) +#define XMC4_CCU42_CC41CRS (XMC4_CCU42_BASE+XMC4_CCU4_CC41CRS_OFFSET) +#define XMC4_CCU42_CC41TIMER (XMC4_CCU42_BASE+XMC4_CCU4_CC41TIMER_OFFSET) +#define XMC4_CCU42_CC41C0V (XMC4_CCU42_BASE+XMC4_CCU4_CC41C0V_OFFSET) +#define XMC4_CCU42_CC41C1V (XMC4_CCU42_BASE+XMC4_CCU4_CC41C1V_OFFSET) +#define XMC4_CCU42_CC41C2V (XMC4_CCU42_BASE+XMC4_CCU4_CC41C2V_OFFSET) +#define XMC4_CCU42_CC41C3V (XMC4_CCU42_BASE+XMC4_CCU4_CC41C3V_OFFSET) +#define XMC4_CCU42_CC41INTS (XMC4_CCU42_BASE+XMC4_CCU4_CC41INTS_OFFSET) +#define XMC4_CCU42_CC41INTE (XMC4_CCU42_BASE+XMC4_CCU4_CC41INTE_OFFSET) +#define XMC4_CCU42_CC41SRS (XMC4_CCU42_BASE+XMC4_CCU4_CC41SRS_OFFSET) +#define XMC4_CCU42_CC41SWS (XMC4_CCU42_BASE+XMC4_CCU4_CC41SWS_OFFSET) +#define XMC4_CCU42_CC41SWR (XMC4_CCU42_BASE+XMC4_CCU4_CC41SWR_OFFSET) +#define XMC4_CCU42_CC41ECRD0 (XMC4_CCU42_BASE+XMC4_CCU4_CC41ECRD0_OFFSET) +#define XMC4_CCU42_CC41ECRD1 (XMC4_CCU42_BASE+XMC4_CCU4_CC41ECRD1_OFFSET) + +/* CCU42 CC42 Slice Registers */ + +#define XMC4_CCU42_CC42INS (XMC4_CCU42_BASE+XMC4_CCU4_CC42INS_OFFSET) +#define XMC4_CCU42_CC42CMC (XMC4_CCU42_BASE+XMC4_CCU4_CC42CMC_OFFSET) +#define XMC4_CCU42_CC42TST (XMC4_CCU42_BASE+XMC4_CCU4_CC42TST_OFFSET) +#define XMC4_CCU42_CC42TCSET (XMC4_CCU42_BASE+XMC4_CCU4_CC42TCSET_OFFSET) +#define XMC4_CCU42_CC42TCCLR (XMC4_CCU42_BASE+XMC4_CCU4_CC42TCCLR_OFFSET) +#define XMC4_CCU42_CC42TC (XMC4_CCU42_BASE+XMC4_CCU4_CC42TC_OFFSET) +#define XMC4_CCU42_CC42PSL (XMC4_CCU42_BASE+XMC4_CCU4_CC42PSL_OFFSET) +#define XMC4_CCU42_CC42DIT (XMC4_CCU42_BASE+XMC4_CCU4_CC42DIT_OFFSET) +#define XMC4_CCU42_CC42DITS (XMC4_CCU42_BASE+XMC4_CCU4_CC42DITS_OFFSET) +#define XMC4_CCU42_CC42PSC (XMC4_CCU42_BASE+XMC4_CCU4_CC42PSC_OFFSET) +#define XMC4_CCU42_CC42FPC (XMC4_CCU42_BASE+XMC4_CCU4_CC42FPC_OFFSET) +#define XMC4_CCU42_CC42FPCS (XMC4_CCU42_BASE+XMC4_CCU4_CC42FPCS_OFFSET) +#define XMC4_CCU42_CC42PR (XMC4_CCU42_BASE+XMC4_CCU4_CC42PR_OFFSET) +#define XMC4_CCU42_CC42PRS (XMC4_CCU42_BASE+XMC4_CCU4_CC42PRS_OFFSET) +#define XMC4_CCU42_CC42CR (XMC4_CCU42_BASE+XMC4_CCU4_CC42CR_OFFSET) +#define XMC4_CCU42_CC42CRS (XMC4_CCU42_BASE+XMC4_CCU4_CC42CRS_OFFSET) +#define XMC4_CCU42_CC42TIMER (XMC4_CCU42_BASE+XMC4_CCU4_CC42TIMER_OFFSET) +#define XMC4_CCU42_CC42C0V (XMC4_CCU42_BASE+XMC4_CCU4_CC42C0V_OFFSET) +#define XMC4_CCU42_CC42C1V (XMC4_CCU42_BASE+XMC4_CCU4_CC42C1V_OFFSET) +#define XMC4_CCU42_CC42C2V (XMC4_CCU42_BASE+XMC4_CCU4_CC42C2V_OFFSET) +#define XMC4_CCU42_CC42C3V (XMC4_CCU42_BASE+XMC4_CCU4_CC42C3V_OFFSET) +#define XMC4_CCU42_CC42INTS (XMC4_CCU42_BASE+XMC4_CCU4_CC42INTS_OFFSET) +#define XMC4_CCU42_CC42INTE (XMC4_CCU42_BASE+XMC4_CCU4_CC42INTE_OFFSET) +#define XMC4_CCU42_CC42SRS (XMC4_CCU42_BASE+XMC4_CCU4_CC42SRS_OFFSET) +#define XMC4_CCU42_CC42SWS (XMC4_CCU42_BASE+XMC4_CCU4_CC42SWS_OFFSET) +#define XMC4_CCU42_CC42SWR (XMC4_CCU42_BASE+XMC4_CCU4_CC42SWR_OFFSET) +#define XMC4_CCU42_CC42ECRD0 (XMC4_CCU42_BASE+XMC4_CCU4_CC42ECRD0_OFFSET) +#define XMC4_CCU42_CC42ECRD1 (XMC4_CCU42_BASE+XMC4_CCU4_CC42ECRD1_OFFSET) + +/* CCU42 CC43 Slice Registers */ + +#define XMC4_CCU42_CC43INS (XMC4_CCU42_BASE+XMC4_CCU4_CC43INS_OFFSET) +#define XMC4_CCU42_CC43CMC (XMC4_CCU42_BASE+XMC4_CCU4_CC43CMC_OFFSET) +#define XMC4_CCU42_CC43TST (XMC4_CCU42_BASE+XMC4_CCU4_CC43TST_OFFSET) +#define XMC4_CCU42_CC43TCSET (XMC4_CCU42_BASE+XMC4_CCU4_CC43TCSET_OFFSET) +#define XMC4_CCU42_CC43TCCLR (XMC4_CCU42_BASE+XMC4_CCU4_CC43TCCLR_OFFSET) +#define XMC4_CCU42_CC43TC (XMC4_CCU42_BASE+XMC4_CCU4_CC43TC_OFFSET) +#define XMC4_CCU42_CC43PSL (XMC4_CCU42_BASE+XMC4_CCU4_CC43PSL_OFFSET) +#define XMC4_CCU42_CC43DIT (XMC4_CCU42_BASE+XMC4_CCU4_CC43DIT_OFFSET) +#define XMC4_CCU42_CC43DITS (XMC4_CCU42_BASE+XMC4_CCU4_CC43DITS_OFFSET) +#define XMC4_CCU42_CC43PSC (XMC4_CCU42_BASE+XMC4_CCU4_CC43PSC_OFFSET) +#define XMC4_CCU42_CC43FPC (XMC4_CCU42_BASE+XMC4_CCU4_CC43FPC_OFFSET) +#define XMC4_CCU42_CC43FPCS (XMC4_CCU42_BASE+XMC4_CCU4_CC43FPCS_OFFSET) +#define XMC4_CCU42_CC43PR (XMC4_CCU42_BASE+XMC4_CCU4_CC43PR_OFFSET) +#define XMC4_CCU42_CC43PRS (XMC4_CCU42_BASE+XMC4_CCU4_CC43PRS_OFFSET) +#define XMC4_CCU42_CC43CR (XMC4_CCU42_BASE+XMC4_CCU4_CC43CR_OFFSET) +#define XMC4_CCU42_CC43CRS (XMC4_CCU42_BASE+XMC4_CCU4_CC43CRS_OFFSET) +#define XMC4_CCU42_CC43TIMER (XMC4_CCU42_BASE+XMC4_CCU4_CC43TIMER_OFFSET) +#define XMC4_CCU42_CC43C0V (XMC4_CCU42_BASE+XMC4_CCU4_CC43C0V_OFFSET) +#define XMC4_CCU42_CC43C1V (XMC4_CCU42_BASE+XMC4_CCU4_CC43C1V_OFFSET) +#define XMC4_CCU42_CC43C2V (XMC4_CCU42_BASE+XMC4_CCU4_CC43C2V_OFFSET) +#define XMC4_CCU42_CC43C3V (XMC4_CCU42_BASE+XMC4_CCU4_CC43C3V_OFFSET) +#define XMC4_CCU42_CC43INTS (XMC4_CCU42_BASE+XMC4_CCU4_CC43INTS_OFFSET) +#define XMC4_CCU42_CC43INTE (XMC4_CCU42_BASE+XMC4_CCU4_CC43INTE_OFFSET) +#define XMC4_CCU42_CC43SRS (XMC4_CCU42_BASE+XMC4_CCU4_CC43SRS_OFFSET) +#define XMC4_CCU42_CC43SWS (XMC4_CCU42_BASE+XMC4_CCU4_CC43SWS_OFFSET) +#define XMC4_CCU42_CC43SWR (XMC4_CCU42_BASE+XMC4_CCU4_CC43SWR_OFFSET) +#define XMC4_CCU42_CC43ECRD0 (XMC4_CCU42_BASE+XMC4_CCU4_CC43ECRD0_OFFSET) +#define XMC4_CCU42_CC43ECRD1 (XMC4_CCU42_BASE+XMC4_CCU4_CC43ECRD1_OFFSET) + +/* CCU43 Global Registers */ + +#define XMC4_CCU43_GCTRL (XMC4_CCU43_BASE+XMC4_CCU4_GCTRL_OFFSET) +#define XMC4_CCU43_GSTAT (XMC4_CCU43_BASE+XMC4_CCU4_GSTAT_OFFSET) +#define XMC4_CCU43_GIDLS (XMC4_CCU43_BASE+XMC4_CCU4_GIDLS_OFFSET) +#define XMC4_CCU43_GIDLC (XMC4_CCU43_BASE+XMC4_CCU4_GIDLC_OFFSET) +#define XMC4_CCU43_GCSS (XMC4_CCU43_BASE+XMC4_CCU4_GCSS_OFFSET) +#define XMC4_CCU43_GCSC (XMC4_CCU43_BASE+XMC4_CCU4_GCSC_OFFSET) +#define XMC4_CCU43_GCST (XMC4_CCU43_BASE+XMC4_CCU4_GCST_OFFSET) +#define XMC4_CCU43_MIDR (XMC4_CCU43_BASE+XMC4_CCU4_MIDR_OFFSET) + +/* CCU43 CC40 Slice Registers */ + +#define XMC4_CCU43_CC40INS (XMC4_CCU43_BASE+XMC4_CCU4_CC40INS_OFFSET) +#define XMC4_CCU43_CC40CMC (XMC4_CCU43_BASE+XMC4_CCU4_CC40CMC_OFFSET) +#define XMC4_CCU43_CC40TST (XMC4_CCU43_BASE+XMC4_CCU4_CC40TST_OFFSET) +#define XMC4_CCU43_CC40TCSET (XMC4_CCU43_BASE+XMC4_CCU4_CC40TCSET_OFFSET) +#define XMC4_CCU43_CC40TCCLR (XMC4_CCU43_BASE+XMC4_CCU4_CC40TCCLR_OFFSET) +#define XMC4_CCU43_CC40TC (XMC4_CCU43_BASE+XMC4_CCU4_CC40TC_OFFSET) +#define XMC4_CCU43_CC40PSL (XMC4_CCU43_BASE+XMC4_CCU4_CC40PSL_OFFSET) +#define XMC4_CCU43_CC40DIT (XMC4_CCU43_BASE+XMC4_CCU4_CC40DIT_OFFSET) +#define XMC4_CCU43_CC40DITS (XMC4_CCU43_BASE+XMC4_CCU4_CC40DITS_OFFSET) +#define XMC4_CCU43_CC40PSC (XMC4_CCU43_BASE+XMC4_CCU4_CC40PSC_OFFSET) +#define XMC4_CCU43_CC40FPC (XMC4_CCU43_BASE+XMC4_CCU4_CC40FPC_OFFSET) +#define XMC4_CCU43_CC40FPCS (XMC4_CCU43_BASE+XMC4_CCU4_CC40FPCS_OFFSET) +#define XMC4_CCU43_CC40PR (XMC4_CCU43_BASE+XMC4_CCU4_CC40PR_OFFSET) +#define XMC4_CCU43_CC40PRS (XMC4_CCU43_BASE+XMC4_CCU4_CC40PRS_OFFSET) +#define XMC4_CCU43_CC40CR (XMC4_CCU43_BASE+XMC4_CCU4_CC40CR_OFFSET) +#define XMC4_CCU43_CC40CRS (XMC4_CCU43_BASE+XMC4_CCU4_CC40CRS_OFFSET) +#define XMC4_CCU43_CC40TIMER (XMC4_CCU43_BASE+XMC4_CCU4_CC40TIMER_OFFSET) +#define XMC4_CCU43_CC40C0V (XMC4_CCU43_BASE+XMC4_CCU4_CC40C0V_OFFSET) +#define XMC4_CCU43_CC40C1V (XMC4_CCU43_BASE+XMC4_CCU4_CC40C1V_OFFSET) +#define XMC4_CCU43_CC40C2V (XMC4_CCU43_BASE+XMC4_CCU4_CC40C2V_OFFSET) +#define XMC4_CCU43_CC40C3V (XMC4_CCU43_BASE+XMC4_CCU4_CC40C3V_OFFSET) +#define XMC4_CCU43_CC40INTS (XMC4_CCU43_BASE+XMC4_CCU4_CC40INTS_OFFSET) +#define XMC4_CCU43_CC40INTE (XMC4_CCU43_BASE+XMC4_CCU4_CC40INTE_OFFSET) +#define XMC4_CCU43_CC40SRS (XMC4_CCU43_BASE+XMC4_CCU4_CC40SRS_OFFSET) +#define XMC4_CCU43_CC40SWS (XMC4_CCU43_BASE+XMC4_CCU4_CC40SWS_OFFSET) +#define XMC4_CCU43_CC40SWR (XMC4_CCU43_BASE+XMC4_CCU4_CC40SWR_OFFSET) +#define XMC4_CCU43_CC40ECRD0 (XMC4_CCU43_BASE+XMC4_CCU4_CC40ECRD0_OFFSET) +#define XMC4_CCU43_CC40ECRD1 (XMC4_CCU43_BASE+XMC4_CCU4_CC40ECRD1_OFFSET) + +/* CCU43 CC41 Slice Registers */ + +#define XMC4_CCU43_CC41INS (XMC4_CCU43_BASE+XMC4_CCU4_CC41INS_OFFSET) +#define XMC4_CCU43_CC41CMC (XMC4_CCU43_BASE+XMC4_CCU4_CC41CMC_OFFSET) +#define XMC4_CCU43_CC41TST (XMC4_CCU43_BASE+XMC4_CCU4_CC41TST_OFFSET) +#define XMC4_CCU43_CC41TCSET (XMC4_CCU43_BASE+XMC4_CCU4_CC41TCSET_OFFSET) +#define XMC4_CCU43_CC41TCCLR (XMC4_CCU43_BASE+XMC4_CCU4_CC41TCCLR_OFFSET) +#define XMC4_CCU43_CC41TC (XMC4_CCU43_BASE+XMC4_CCU4_CC41TC_OFFSET) +#define XMC4_CCU43_CC41PSL (XMC4_CCU43_BASE+XMC4_CCU4_CC41PSL_OFFSET) +#define XMC4_CCU43_CC41DIT (XMC4_CCU43_BASE+XMC4_CCU4_CC41DIT_OFFSET) +#define XMC4_CCU43_CC41DITS (XMC4_CCU43_BASE+XMC4_CCU4_CC41DITS_OFFSET) +#define XMC4_CCU43_CC41PSC (XMC4_CCU43_BASE+XMC4_CCU4_CC41PSC_OFFSET) +#define XMC4_CCU43_CC41FPC (XMC4_CCU43_BASE+XMC4_CCU4_CC41FPC_OFFSET) +#define XMC4_CCU43_CC41FPCS (XMC4_CCU43_BASE+XMC4_CCU4_CC41FPCS_OFFSET) +#define XMC4_CCU43_CC41PR (XMC4_CCU43_BASE+XMC4_CCU4_CC41PR_OFFSET) +#define XMC4_CCU43_CC41PRS (XMC4_CCU43_BASE+XMC4_CCU4_CC41PRS_OFFSET) +#define XMC4_CCU43_CC41CR (XMC4_CCU43_BASE+XMC4_CCU4_CC41CR_OFFSET) +#define XMC4_CCU43_CC41CRS (XMC4_CCU43_BASE+XMC4_CCU4_CC41CRS_OFFSET) +#define XMC4_CCU43_CC41TIMER (XMC4_CCU43_BASE+XMC4_CCU4_CC41TIMER_OFFSET) +#define XMC4_CCU43_CC41C0V (XMC4_CCU43_BASE+XMC4_CCU4_CC41C0V_OFFSET) +#define XMC4_CCU43_CC41C1V (XMC4_CCU43_BASE+XMC4_CCU4_CC41C1V_OFFSET) +#define XMC4_CCU43_CC41C2V (XMC4_CCU43_BASE+XMC4_CCU4_CC41C2V_OFFSET) +#define XMC4_CCU43_CC41C3V (XMC4_CCU43_BASE+XMC4_CCU4_CC41C3V_OFFSET) +#define XMC4_CCU43_CC41INTS (XMC4_CCU43_BASE+XMC4_CCU4_CC41INTS_OFFSET) +#define XMC4_CCU43_CC41INTE (XMC4_CCU43_BASE+XMC4_CCU4_CC41INTE_OFFSET) +#define XMC4_CCU43_CC41SRS (XMC4_CCU43_BASE+XMC4_CCU4_CC41SRS_OFFSET) +#define XMC4_CCU43_CC41SWS (XMC4_CCU43_BASE+XMC4_CCU4_CC41SWS_OFFSET) +#define XMC4_CCU43_CC41SWR (XMC4_CCU43_BASE+XMC4_CCU4_CC41SWR_OFFSET) +#define XMC4_CCU43_CC41ECRD0 (XMC4_CCU43_BASE+XMC4_CCU4_CC41ECRD0_OFFSET) +#define XMC4_CCU43_CC41ECRD1 (XMC4_CCU43_BASE+XMC4_CCU4_CC41ECRD1_OFFSET) + +/* CCU43 CC42 Slice Registers */ + +#define XMC4_CCU43_CC42INS (XMC4_CCU43_BASE+XMC4_CCU4_CC42INS_OFFSET) +#define XMC4_CCU43_CC42CMC (XMC4_CCU43_BASE+XMC4_CCU4_CC42CMC_OFFSET) +#define XMC4_CCU43_CC42TST (XMC4_CCU43_BASE+XMC4_CCU4_CC42TST_OFFSET) +#define XMC4_CCU43_CC42TCSET (XMC4_CCU43_BASE+XMC4_CCU4_CC42TCSET_OFFSET) +#define XMC4_CCU43_CC42TCCLR (XMC4_CCU43_BASE+XMC4_CCU4_CC42TCCLR_OFFSET) +#define XMC4_CCU43_CC42TC (XMC4_CCU43_BASE+XMC4_CCU4_CC42TC_OFFSET) +#define XMC4_CCU43_CC42PSL (XMC4_CCU43_BASE+XMC4_CCU4_CC42PSL_OFFSET) +#define XMC4_CCU43_CC42DIT (XMC4_CCU43_BASE+XMC4_CCU4_CC42DIT_OFFSET) +#define XMC4_CCU43_CC42DITS (XMC4_CCU43_BASE+XMC4_CCU4_CC42DITS_OFFSET) +#define XMC4_CCU43_CC42PSC (XMC4_CCU43_BASE+XMC4_CCU4_CC42PSC_OFFSET) +#define XMC4_CCU43_CC42FPC (XMC4_CCU43_BASE+XMC4_CCU4_CC42FPC_OFFSET) +#define XMC4_CCU43_CC42FPCS (XMC4_CCU43_BASE+XMC4_CCU4_CC42FPCS_OFFSET) +#define XMC4_CCU43_CC42PR (XMC4_CCU43_BASE+XMC4_CCU4_CC42PR_OFFSET) +#define XMC4_CCU43_CC42PRS (XMC4_CCU43_BASE+XMC4_CCU4_CC42PRS_OFFSET) +#define XMC4_CCU43_CC42CR (XMC4_CCU43_BASE+XMC4_CCU4_CC42CR_OFFSET) +#define XMC4_CCU43_CC42CRS (XMC4_CCU43_BASE+XMC4_CCU4_CC42CRS_OFFSET) +#define XMC4_CCU43_CC42TIMER (XMC4_CCU43_BASE+XMC4_CCU4_CC42TIMER_OFFSET) +#define XMC4_CCU43_CC42C0V (XMC4_CCU43_BASE+XMC4_CCU4_CC42C0V_OFFSET) +#define XMC4_CCU43_CC42C1V (XMC4_CCU43_BASE+XMC4_CCU4_CC42C1V_OFFSET) +#define XMC4_CCU43_CC42C2V (XMC4_CCU43_BASE+XMC4_CCU4_CC42C2V_OFFSET) +#define XMC4_CCU43_CC42C3V (XMC4_CCU43_BASE+XMC4_CCU4_CC42C3V_OFFSET) +#define XMC4_CCU43_CC42INTS (XMC4_CCU43_BASE+XMC4_CCU4_CC42INTS_OFFSET) +#define XMC4_CCU43_CC42INTE (XMC4_CCU43_BASE+XMC4_CCU4_CC42INTE_OFFSET) +#define XMC4_CCU43_CC42SRS (XMC4_CCU43_BASE+XMC4_CCU4_CC42SRS_OFFSET) +#define XMC4_CCU43_CC42SWS (XMC4_CCU43_BASE+XMC4_CCU4_CC42SWS_OFFSET) +#define XMC4_CCU43_CC42SWR (XMC4_CCU43_BASE+XMC4_CCU4_CC42SWR_OFFSET) +#define XMC4_CCU43_CC42ECRD0 (XMC4_CCU43_BASE+XMC4_CCU4_CC42ECRD0_OFFSET) +#define XMC4_CCU43_CC42ECRD1 (XMC4_CCU43_BASE+XMC4_CCU4_CC42ECRD1_OFFSET) + +/* CCU43 CC43 Slice Registers */ + +#define XMC4_CCU43_CC43INS (XMC4_CCU43_BASE+XMC4_CCU4_CC43INS_OFFSET) +#define XMC4_CCU43_CC43CMC (XMC4_CCU43_BASE+XMC4_CCU4_CC43CMC_OFFSET) +#define XMC4_CCU43_CC43TST (XMC4_CCU43_BASE+XMC4_CCU4_CC43TST_OFFSET) +#define XMC4_CCU43_CC43TCSET (XMC4_CCU43_BASE+XMC4_CCU4_CC43TCSET_OFFSET) +#define XMC4_CCU43_CC43TCCLR (XMC4_CCU43_BASE+XMC4_CCU4_CC43TCCLR_OFFSET) +#define XMC4_CCU43_CC43TC (XMC4_CCU43_BASE+XMC4_CCU4_CC43TC_OFFSET) +#define XMC4_CCU43_CC43PSL (XMC4_CCU43_BASE+XMC4_CCU4_CC43PSL_OFFSET) +#define XMC4_CCU43_CC43DIT (XMC4_CCU43_BASE+XMC4_CCU4_CC43DIT_OFFSET) +#define XMC4_CCU43_CC43DITS (XMC4_CCU43_BASE+XMC4_CCU4_CC43DITS_OFFSET) +#define XMC4_CCU43_CC43PSC (XMC4_CCU43_BASE+XMC4_CCU4_CC43PSC_OFFSET) +#define XMC4_CCU43_CC43FPC (XMC4_CCU43_BASE+XMC4_CCU4_CC43FPC_OFFSET) +#define XMC4_CCU43_CC43FPCS (XMC4_CCU43_BASE+XMC4_CCU4_CC43FPCS_OFFSET) +#define XMC4_CCU43_CC43PR (XMC4_CCU43_BASE+XMC4_CCU4_CC43PR_OFFSET) +#define XMC4_CCU43_CC43PRS (XMC4_CCU43_BASE+XMC4_CCU4_CC43PRS_OFFSET) +#define XMC4_CCU43_CC43CR (XMC4_CCU43_BASE+XMC4_CCU4_CC43CR_OFFSET) +#define XMC4_CCU43_CC43CRS (XMC4_CCU43_BASE+XMC4_CCU4_CC43CRS_OFFSET) +#define XMC4_CCU43_CC43TIMER (XMC4_CCU43_BASE+XMC4_CCU4_CC43TIMER_OFFSET) +#define XMC4_CCU43_CC43C0V (XMC4_CCU43_BASE+XMC4_CCU4_CC43C0V_OFFSET) +#define XMC4_CCU43_CC43C1V (XMC4_CCU43_BASE+XMC4_CCU4_CC43C1V_OFFSET) +#define XMC4_CCU43_CC43C2V (XMC4_CCU43_BASE+XMC4_CCU4_CC43C2V_OFFSET) +#define XMC4_CCU43_CC43C3V (XMC4_CCU43_BASE+XMC4_CCU4_CC43C3V_OFFSET) +#define XMC4_CCU43_CC43INTS (XMC4_CCU43_BASE+XMC4_CCU4_CC43INTS_OFFSET) +#define XMC4_CCU43_CC43INTE (XMC4_CCU43_BASE+XMC4_CCU4_CC43INTE_OFFSET) +#define XMC4_CCU43_CC43SRS (XMC4_CCU43_BASE+XMC4_CCU4_CC43SRS_OFFSET) +#define XMC4_CCU43_CC43SWS (XMC4_CCU43_BASE+XMC4_CCU4_CC43SWS_OFFSET) +#define XMC4_CCU43_CC43SWR (XMC4_CCU43_BASE+XMC4_CCU4_CC43SWR_OFFSET) +#define XMC4_CCU43_CC43ECRD0 (XMC4_CCU43_BASE+XMC4_CCU4_CC43ECRD0_OFFSET) +#define XMC4_CCU43_CC43ECRD1 (XMC4_CCU43_BASE+XMC4_CCU4_CC43ECRD1_OFFSET) + +/* Register Bit-Field Definitions *******************************************/ + +/* CCU4 Global Registers */ + +/* Global Control Register (GCTRL) */ + +#define CCU4_GCTRL_PRBC_SHIFT (0) /* Bits 0-2: Prescaler Clear Configuration */ +#define CCU4_GCTRL_PRBC_MASK (7 << CCU4_GCTRL_PRBC_SHIFT) +# define CCU4_GCTRL_PRBC_SW (0 << CCU4_GCTRL_PRBC_SHIFT) /* SW only */ +# define CCU4_GCTRL_PRBC_CC40 (1 << CCU4_GCTRL_PRBC_SHIFT) /* When the Run Bit of CC40 is cleared */ +# define CCU4_GCTRL_PRBC_CC41 (2 << CCU4_GCTRL_PRBC_SHIFT) /* When the Run Bit of CC41 is cleared */ +# define CCU4_GCTRL_PRBC_CC42 (3 << CCU4_GCTRL_PRBC_SHIFT) /* When the Run Bit of CC42 is cleared */ +# define CCU4_GCTRL_PRBC_CC43 (4 << CCU4_GCTRL_PRBC_SHIFT) /* When the Run Bit of CC43 is cleared */ +#define CCU4_GCTRL_PCIS_SHIFT (4) /* Bits 4-5: Prescaler Input Clock Selection */ +#define CCU4_GCTRL_PCIS_MASK (3 << CCU4_GCTRL_PCIS_SHIFT) +# define CCU4_GCTRL_PCIS_MODULE_CLK (0 << CCU4_GCTRL_PCIS_SHIFT) /* Module clock */ +# define CCU4_GCTRL_PCIS_ECLKA (1 << CCU4_GCTRL_PCIS_SHIFT) /* CCU4x.ECLKA */ +# define CCU4_GCTRL_PCIS_ECLKB (2 << CCU4_GCTRL_PCIS_SHIFT) /* CCU4x.ECLKB */ +# define CCU4_GCTRL_PCIS_ECLKC (3 << CCU4_GCTRL_PCIS_SHIFT) /* CCU4x.ECLKC */ +#define CCU4_GCTRL_SUSCFG_SHIFT (8) /* Bits 8-9: Suspend Mode Configuration */ +#define CCU4_GCTRL_SUSCFG_MASK (3 << CCU4_GCTRL_SUSCFG_SHIFT) +#define CCU4_GCTRL_MSE0_SHIFT (10) /* Bits 10: Slice 0 Multi Channel shadow transfer enable */ +#define CCU4_GCTRL_MSE0_MASK (1 << CCU4_GCTRL_MSE0_SHIFT) +#define CCU4_GCTRL_MSE1_SHIFT (11) /* Bits 11: Slice 1 Multi Channel shadow transfer enable */ +#define CCU4_GCTRL_MSE1_MASK (1 << CCU4_GCTRL_MSE1_SHIFT) +#define CCU4_GCTRL_MSE2_SHIFT (12) /* Bits 12: Slice 2 Multi Channel shadow transfer enable */ +#define CCU4_GCTRL_MSE2_MASK (1 << CCU4_GCTRL_MSE2_SHIFT) +#define CCU4_GCTRL_MSE3_SHIFT (13) /* Bits 13: Slice 3 Multi Channel shadow transfer enable */ +#define CCU4_GCTRL_MSE3_MASK (1 << CCU4_GCTRL_MSE3_SHIFT) +#define CCU4_GCTRL_MSDE_SHIFT (15) /* Bits 14-15: Multi Channel shadow transfer request configuration */ +#define CCU4_GCTRL_MSDE_MASK (3 << CCU4_GCTRL_MSDE_SHIFT) + +/* Global Status Register (GSTAT) */ + +#define CCU4_GSTAT_S0I_SHIFT (0) /* Bits 0: CC40 IDLE status */ +#define CCU4_GSTAT_S0I_MASK (1 << CCU4_GSTAT_S0I_SHIFT) +#define CCU4_GSTAT_S1I_SHIFT (1) /* Bits 1: CC41 IDLE status */ +#define CCU4_GSTAT_S1I_MASK (1 << CCU4_GSTAT_S1I_SHIFT) +#define CCU4_GSTAT_S2I_SHIFT (2) /* Bits 2: CC42 IDLE status */ +#define CCU4_GSTAT_S2I_MASK (1 << CCU4_GSTAT_S2I_SHIFT) +#define CCU4_GSTAT_S3I_SHIFT (3) /* Bits 3: CC43 IDLE status */ +#define CCU4_GSTAT_S3I_MASK (1 << CCU4_GSTAT_SI_SHIFT) +#define CCU4_GSTAT_PRB_SHIFT (8) /* Bits 8: Prescaler Run Bit */ +#define CCU4_GSTAT_PRB_MASK (1 << CCU4_GSTAT_SI_SHIFT) + +/* Global Idle Set (GIDLS) */ + +#define CCU4_GIDLS_SS0I_SHIFT (0) /* Bits 0: CC40 IDLE mode set */ +#define CCU4_GIDLS_SS0I_MASK (1 << CCU4_GIDLS_SS0I_SHIFT) +#define CCU4_GIDLS_SS1I_SHIFT (1) /* Bits 1: CC41 IDLE mode set */ +#define CCU4_GIDLS_SS1I_MASK (1 << CCU4_GIDLS_SS1I_SHIFT) +#define CCU4_GIDLS_SS2I_SHIFT (2) /* Bits 2: CC42 IDLE mode set */ +#define CCU4_GIDLS_SS2I_MASK (1 << CCU4_GIDLS_SS2I_SHIFT) +#define CCU4_GIDLS_SS3I_SHIFT (3) /* Bits 3: CC43 IDLE mode set */ +#define CCU4_GIDLS_SS3I_MASK (1 << CCU4_GIDLS_SS3I_SHIFT) +#define CCU4_GIDLS_CPRB_SHIFT (8) /* Bits 8: Prescaler Run Bit Clear */ +#define CCU4_GIDLS_CPRB_MASK (1 << CCU4_GIDLS_CPRB_SHIFT) +#define CCU4_GIDLS_PSIC_SHIFT (9) /* Bits 9: Prescaler clear */ +#define CCU4_GIDLS_PSIC_MASK (1 << CCU4_GIDLS_PSIC_SHIFT) + +/* Global Idle Clear (GIDLC) */ + +#define CCU4_GIDLC_CS0I_SHIFT (0) /* Bits 0: CC40 IDLE mode clear */ +#define CCU4_GIDLC_CS0I_MASK (1 << CCU4_GIDLC_CS0I_SHIFT) +#define CCU4_GIDLC_CS1I_SHIFT (1) /* Bits 1: CC41 IDLE mode clear */ +#define CCU4_GIDLC_CS1I_MASK (1 << CCU4_GIDLC_CS1I_SHIFT) +#define CCU4_GIDLC_CS2I_SHIFT (2) /* Bits 2: CC42 IDLE mode clear */ +#define CCU4_GIDLC_CS2I_MASK (1 << CCU4_GIDLC_CS2I_SHIFT) +#define CCU4_GIDLC_CS3I_SHIFT (3) /* Bits 3: CC43 IDLE mode clear */ +#define CCU4_GIDLC_CS3I_MASK (1 << CCU4_GIDLC_CS3I_SHIFT) +#define CCU4_GIDLC_SPRB_SHIFT (8) /* Bits 8: Prescaler Run Bit Set */ +#define CCU4_GIDLC_SPRB_MASK (1 << CCU4_GIDLC_SPRB_SHIFT) + +/* Global Channel Set (GCSS) */ + +#define CCU4_GCSS_S0SE_SHIFT (0) /* Bits 0: Slice 0 shadow transfer set enable */ +#define CCU4_GCSS_S0SE_MASK (1 << CCU4_GCSS_S0SE_SHIFT) +#define CCU4_GCSS_S0DSE_SHIFT (1) /* Bits 1: Slice 0 Dither shadow transfer set enable */ +#define CCU4_GCSS_S0DSE_MASK (1 << CCU4_GCSS_S0DSE_SHIFT) +#define CCU4_GCSS_S0PSE_SHIFT (2) /* Bits 2: Slice 0 Prescaler shadow transfer set enable */ +#define CCU4_GCSS_S0PSE_MASK (1 << CCU4_GCSS_S0PSE_SHIFT) +#define CCU4_GCSS_S1SE_SHIFT (4) /* Bits 4: Slice 1 shadow transfer set enable */ +#define CCU4_GCSS_S1SE_MASK (1 << CCU4_GCSS_S1SE_SHIFT) +#define CCU4_GCSS_S1DSE_SHIFT (5) /* Bits 5: Slice 1 Dither shadow transfer set enable */ +#define CCU4_GCSS_S1DSE_MASK (1 << CCU4_GCSS_S1DSE_SHIFT) +#define CCU4_GCSS_S1PSE_SHIFT (6) /* Bits 6: Slice 1 Prescaler shadow transfer set enable */ +#define CCU4_GCSS_S1PSE_MASK (1 << CCU4_GCSS_S1PSE_SHIFT) +#define CCU4_GCSS_S2SE_SHIFT (8) /* Bits 8: Slice 2 shadow transfer set enable */ +#define CCU4_GCSS_S2SE_MASK (1 << CCU4_GCSS_S2SE_SHIFT) +#define CCU4_GCSS_S2DSE_SHIFT (9) /* Bits 9: Slice 2 Dither shadow transfer set enable */ +#define CCU4_GCSS_S2DSE_MASK (1 << CCU4_GCSS_S2DSE_SHIFT) +#define CCU4_GCSS_S2PSE_SHIFT (10) /* Bits 10: Slice 2 Prescaler shadow transfer set enable */ +#define CCU4_GCSS_S2PSE_MASK (1 << CCU4_GCSS_S2PSE_SHIFT) +#define CCU4_GCSS_S3SE_SHIFT (12) /* Bits 12: Slice 3 shadow transfer set enable */ +#define CCU4_GCSS_S3SE_MASK (1 << CCU4_GCSS_S3SE_SHIFT) +#define CCU4_GCSS_S3DSE_SHIFT (13) /* Bits 13: Slice 3 Dither shadow transfer set enable */ +#define CCU4_GCSS_S3DSE_MASK (1 << CCU4_GCSS_S3DSE_SHIFT) +#define CCU4_GCSS_S3PSE_SHIFT (14) /* Bits 14: Slice 3 Prescaler shadow transfer set enable */ +#define CCU4_GCSS_S3PSE_MASK (1 << CCU4_GCSS_S3PSE_SHIFT) +#define CCU4_GCSS_S0STS_SHIFT (16) /* Bits 16: Slice 0 status bit set */ +#define CCU4_GCSS_S0STS_MASK (1 << CCU4_GCSS_S0STS_SHIFT) +#define CCU4_GCSS_S1STS_SHIFT (17) /* Bits 17: Slice 1 status bit set */ +#define CCU4_GCSS_S1STS_MASK (1 << CCU4_GCSS_S1STS_SHIFT) +#define CCU4_GCSS_S2STS_SHIFT (18) /* Bits 18: Slice 2 status bit set */ +#define CCU4_GCSS_S2STS_MASK (1 << CCU4_GCSS_S2STS_SHIFT) +#define CCU4_GCSS_S3STS_SHIFT (19) /* Bits 19: Slice 3 status bit set */ +#define CCU4_GCSS_S3STS_MASK (1 << CCU4_GCSS_S3STS_SHIFT) + +/* Global Channel Clear (GCSC) */ + +#define CCU4_GCSC_S0SC_SHIFT (0) /* Bits 0: Slice 0 shadow transfer clear */ +#define CCU4_GCSC_S0SC_MASK (1 << CCU4_GCSC_S0SC_SHIFT) +#define CCU4_GCSC_S0DSC_SHIFT (1) /* Bits 1: Slice 0 Dither shadow transfer clear */ +#define CCU4_GCSC_S0DSC_MASK (1 << CCU4_GCSC_S0DSC_SHIFT) +#define CCU4_GCSC_S0PSC_SHIFT (2) /* Bits 2: Slice 0 Prescaler shadow transfer clear */ +#define CCU4_GCSC_S0PSC_MASK (1 << CCU4_GCSC_S0PSC_SHIFT) +#define CCU4_GCSC_S1SC_SHIFT (4) /* Bits 4: Slice 1 shadow transfer clear */ +#define CCU4_GCSC_S1SC_MASK (1 << CCU4_GCSC_S1SC_SHIFT) +#define CCU4_GCSC_S1DSC_SHIFT (5) /* Bits 5: Slice 1 Dither shadow transfer clear */ +#define CCU4_GCSC_S1DSC_MASK (1 << CCU4_GCSC_S1DSC_SHIFT) +#define CCU4_GCSC_S1PSC_SHIFT (6) /* Bits 6: Slice 1 Prescaler shadow transfer clear */ +#define CCU4_GCSC_S1PSC_MASK (1 << CCU4_GCSC_S1PSC_SHIFT) +#define CCU4_GCSC_S2SC_SHIFT (8) /* Bits 8: Slice 2 shadow transfer clear */ +#define CCU4_GCSC_S2SC_MASK (1 << CCU4_GCSC_S2SC_SHIFT) +#define CCU4_GCSC_S2DSC_SHIFT (9) /* Bits 9: Slice 2 Dither shadow transfer clear */ +#define CCU4_GCSC_S2DSC_MASK (1 << CCU4_GCSC_S2DSC_SHIFT) +#define CCU4_GCSC_S2PSC_SHIFT (10) /* Bits 10: Slice 2 Prescaler shadow transfer clear */ +#define CCU4_GCSC_S2PSC_MASK (1 << CCU4_GCSC_S2PSC_SHIFT) +#define CCU4_GCSC_S3SC_SHIFT (12) /* Bits 12: Slice 3 shadow transfer clear */ +#define CCU4_GCSC_S3SC_MASK (1 << CCU4_GCSC_S3SC_SHIFT) +#define CCU4_GCSC_S3DSC_SHIFT (13) /* Bits 13: Slice 3 Dither shadow transfer clear */ +#define CCU4_GCSC_S3DSC_MASK (1 << CCU4_GCSC_S3DSC_SHIFT) +#define CCU4_GCSC_S3PSC_SHIFT (14) /* Bits 14: Slice 3 Prescaler shadow transfer clear */ +#define CCU4_GCSC_S3PSC_MASK (1 << CCU4_GCSC_S3PSC_SHIFT) +#define CCU4_GCSC_S0STC_SHIFT (16) /* Bits 16: Slice 0 status bit clear */ +#define CCU4_GCSC_S0STC_MASK (1 << CCU4_GCSC_S0STC_SHIFT) +#define CCU4_GCSC_S1STC_SHIFT (17) /* Bits 17: Slice 1 status bit clear */ +#define CCU4_GCSC_S1STC_MASK (1 << CCU4_GCSC_S1STC_SHIFT) +#define CCU4_GCSC_S2STC_SHIFT (18) /* Bits 18: Slice 2 status bit clear */ +#define CCU4_GCSC_S2STC_MASK (1 << CCU4_GCSC_S2STC_SHIFT) +#define CCU4_GCSC_S3STC_SHIFT (19) /* Bits 19: Slice 3 status bit clear */ +#define CCU4_GCSC_S3STC_MASK (1 << CCU4_GCSC_S3STC_SHIFT) + +/* Global Channel Clear (GCST) */ + +#define CCU4_GCST_S0SS_SHIFT (0) /* Bits 0: Slice 0 shadow transfer status */ +#define CCU4_GCST_S0SS_MASK (1 << CCU4_GCST_S0SS_SHIFT) +#define CCU4_GCST_S0DSS_SHIFT (1) /* Bits 1: Slice 0 Dither shadow transfer status */ +#define CCU4_GCST_S0DSS_MASK (1 << CCU4_GCST_S0DSS_SHIFT) +#define CCU4_GCST_S0PSS_SHIFT (2) /* Bits 2: Slice 0 Prescaler shadow transfer status */ +#define CCU4_GCST_S0PSS_MASK (1 << CCU4_GCST_S0PSS_SHIFT) +#define CCU4_GCST_S1SS_SHIFT (4) /* Bits 4: Slice 1 shadow transfer status */ +#define CCU4_GCST_S1SS_MASK (1 << CCU4_GCST_S1SS_SHIFT) +#define CCU4_GCST_S1DSS_SHIFT (5) /* Bits 5: Slice 1 Dither shadow transfer status */ +#define CCU4_GCST_S1DSS_MASK (1 << CCU4_GCST_S1DSS_SHIFT) +#define CCU4_GCST_S1PSS_SHIFT (6) /* Bits 6: Slice 1 Prescaler shadow transfer status */ +#define CCU4_GCST_S1PSS_MASK (1 << CCU4_GCST_S1PSS_SHIFT) +#define CCU4_GCST_S2SS_SHIFT (8) /* Bits 8: Slice 2 shadow transfer status */ +#define CCU4_GCST_S2SS_MASK (1 << CCU4_GCST_S2SS_SHIFT) +#define CCU4_GCST_S2DSS_SHIFT (9) /* Bits 9: Slice 2 Dither shadow transfer status */ +#define CCU4_GCST_S2DSS_MASK (1 << CCU4_GCST_S2DSS_SHIFT) +#define CCU4_GCST_S2PSS_SHIFT (10) /* Bits 10: Slice 2 Prescaler shadow transfer status */ +#define CCU4_GCST_S2PSS_MASK (1 << CCU4_GCST_S2PSS_SHIFT) +#define CCU4_GCST_S3SS_SHIFT (12) /* Bits 12: Slice 3 shadow transfer status */ +#define CCU4_GCST_S3SS_MASK (1 << CCU4_GCST_S3SS_SHIFT) +#define CCU4_GCST_S3DSS_SHIFT (13) /* Bits 13: Slice 3 Dither shadow transfer status */ +#define CCU4_GCST_S3DSS_MASK (1 << CCU4_GCST_S3DSS_SHIFT) +#define CCU4_GCST_S3PSS_SHIFT (14) /* Bits 14: Slice 3 Prescaler shadow transfer status */ +#define CCU4_GCST_S3PSS_MASK (1 << CCU4_GCST_S3PSS_SHIFT) +#define CCU4_GCST_CC40ST_SHIFT (16) /* Bits 16: Slice 0 status bit */ +#define CCU4_GCST_CC40ST_MASK (1 << CCU4_GCST_CC40ST_SHIFT) +#define CCU4_GCST_CC41ST_SHIFT (17) /* Bits 17: Slice 1 status bit */ +#define CCU4_GCST_CC41ST_MASK (1 << CCU4_GCST_CC41ST_SHIFT) +#define CCU4_GCST_CC42ST_SHIFT (18) /* Bits 18: Slice 2 status bit */ +#define CCU4_GCST_CC42ST_MASK (1 << CCU4_GCST_CC42ST_SHIFT) +#define CCU4_GCST_CC43ST_SHIFT (19) /* Bits 19: Slice 3 status bit */ +#define CCU4_GCST_CC43ST_MASK (1 << CCU4_GCST_CC43ST_SHIFT) + +/* Module Identification (MIDR) */ + +#define CCU4_MIDR_MODR_SHIFT (0) /* Bits 0: Module Revision */ +#define CCU4_MIDR_MODR_MASK (0xFF << CCU4_MIDR_MODR_SHIFT) +#define CCU4_MIDR_MODT_SHIFT (8) /* Bits 8: Module Type */ +#define CCU4_MIDR_MODT_MASK (0xFF << CCU4_MIDR_MODT_SHIFT) +#define CCU4_MIDR_MODN_SHIFT (16) /* Bits 16: Module Number */ +#define CCU4_MIDR_MODN_MASK (0xFFFF << CCU4_MIDR_MODN_SHIFT) + +/* Slice (CC4y) Registers [y = 0-3] */ + +/* Input Selector Configuration (CC4yINS) */ + +#define CCU4_CC4_INS_EV0IS_SHIFT (0) /* Bits 0-3: Event 0 signal selection */ +#define CCU4_CC4_INS_EV0IS_MASK (15 << CCU4_CC4_INS_EV0IS_SHIFT) +# define CCU4_CC4_INS_EV0IS_INA (0 << CCU4_CC4_INS_EV0IS_SHIFT) /* CCU4x.INyA */ +# define CCU4_CC4_INS_EV0IS_INB (1 << CCU4_CC4_INS_EV0IS_SHIFT) /* CCU4x.INyB */ +# define CCU4_CC4_INS_EV0IS_INC (2 << CCU4_CC4_INS_EV0IS_SHIFT) /* CCU4x.INyC */ +# define CCU4_CC4_INS_EV0IS_IND (3 << CCU4_CC4_INS_EV0IS_SHIFT) /* CCU4x.INyD */ +# define CCU4_CC4_INS_EV0IS_INE (4 << CCU4_CC4_INS_EV0IS_SHIFT) /* CCU4x.INyE */ +# define CCU4_CC4_INS_EV0IS_INF (5 << CCU4_CC4_INS_EV0IS_SHIFT) /* CCU4x.INyF */ +# define CCU4_CC4_INS_EV0IS_ING (6 << CCU4_CC4_INS_EV0IS_SHIFT) /* CCU4x.INyG */ +# define CCU4_CC4_INS_EV0IS_INH (7 << CCU4_CC4_INS_EV0IS_SHIFT) /* CCU4x.INyH */ +# define CCU4_CC4_INS_EV0IS_INI (8 << CCU4_CC4_INS_EV0IS_SHIFT) /* CCU4x.INyI */ +# define CCU4_CC4_INS_EV0IS_INJ (9 << CCU4_CC4_INS_EV0IS_SHIFT) /* CCU4x.INyJ */ +# define CCU4_CC4_INS_EV0IS_INK (10 << CCU4_CC4_INS_EV0IS_SHIFT) /* CCU4x.INyK */ +# define CCU4_CC4_INS_EV0IS_INL (11 << CCU4_CC4_INS_EV0IS_SHIFT) /* CCU4x.INyL */ +# define CCU4_CC4_INS_EV0IS_INM (12 << CCU4_CC4_INS_EV0IS_SHIFT) /* CCU4x.INyM */ +# define CCU4_CC4_INS_EV0IS_INN (13 << CCU4_CC4_INS_EV0IS_SHIFT) /* CCU4x.INyN */ +# define CCU4_CC4_INS_EV0IS_INO (14 << CCU4_CC4_INS_EV0IS_SHIFT) /* CCU4x.INyO */ +# define CCU4_CC4_INS_EV0IS_INP (15 << CCU4_CC4_INS_EV0IS_SHIFT) /* CCU4x.INyP */ +#define CCU4_CC4_INS_EV1IS_SHIFT (4) /* Bits 4-7: Event 1 signal selection */ +#define CCU4_CC4_INS_EV1IS_MASK (15 << CCU4_CC4_INS_EV1IS_SHIFT) +# define CCU4_CC4_INS_EV1IS_INA (0 << CCU4_CC4_INS_EV1IS_SHIFT) /* CCU4x.INyA */ +# define CCU4_CC4_INS_EV1IS_INB (1 << CCU4_CC4_INS_EV1IS_SHIFT) /* CCU4x.INyB */ +# define CCU4_CC4_INS_EV1IS_INC (2 << CCU4_CC4_INS_EV1IS_SHIFT) /* CCU4x.INyC */ +# define CCU4_CC4_INS_EV1IS_IND (3 << CCU4_CC4_INS_EV1IS_SHIFT) /* CCU4x.INyD */ +# define CCU4_CC4_INS_EV1IS_INE (4 << CCU4_CC4_INS_EV1IS_SHIFT) /* CCU4x.INyE */ +# define CCU4_CC4_INS_EV1IS_INF (5 << CCU4_CC4_INS_EV1IS_SHIFT) /* CCU4x.INyF */ +# define CCU4_CC4_INS_EV1IS_ING (6 << CCU4_CC4_INS_EV1IS_SHIFT) /* CCU4x.INyG */ +# define CCU4_CC4_INS_EV1IS_INH (7 << CCU4_CC4_INS_EV1IS_SHIFT) /* CCU4x.INyH */ +# define CCU4_CC4_INS_EV1IS_INI (8 << CCU4_CC4_INS_EV1IS_SHIFT) /* CCU4x.INyI */ +# define CCU4_CC4_INS_EV1IS_INJ (9 << CCU4_CC4_INS_EV1IS_SHIFT) /* CCU4x.INyJ */ +# define CCU4_CC4_INS_EV1IS_INK (10 << CCU4_CC4_INS_EV1IS_SHIFT) /* CCU4x.INyK */ +# define CCU4_CC4_INS_EV1IS_INL (11 << CCU4_CC4_INS_EV1IS_SHIFT) /* CCU4x.INyL */ +# define CCU4_CC4_INS_EV1IS_INM (12 << CCU4_CC4_INS_EV1IS_SHIFT) /* CCU4x.INyM */ +# define CCU4_CC4_INS_EV1IS_INN (13 << CCU4_CC4_INS_EV1IS_SHIFT) /* CCU4x.INyN */ +# define CCU4_CC4_INS_EV1IS_INO (14 << CCU4_CC4_INS_EV1IS_SHIFT) /* CCU4x.INyO */ +# define CCU4_CC4_INS_EV1IS_INP (15 << CCU4_CC4_INS_EV1IS_SHIFT) /* CCU4x.INyP */ +#define CCU4_CC4_INS_EV2IS_SHIFT (8) /* Bits 8-11: Event 2 signal selection */ +#define CCU4_CC4_INS_EV2IS_MASK (15 << CCU4_CC4_INS_EV2IS_SHIFT) +# define CCU4_CC4_INS_EV2IS_INA (0 << CCU4_CC4_INS_EV2IS_SHIFT) /* CCU4x.INyA */ +# define CCU4_CC4_INS_EV2IS_INB (1 << CCU4_CC4_INS_EV2IS_SHIFT) /* CCU4x.INyB */ +# define CCU4_CC4_INS_EV2IS_INC (2 << CCU4_CC4_INS_EV2IS_SHIFT) /* CCU4x.INyC */ +# define CCU4_CC4_INS_EV2IS_IND (3 << CCU4_CC4_INS_EV2IS_SHIFT) /* CCU4x.INyD */ +# define CCU4_CC4_INS_EV2IS_INE (4 << CCU4_CC4_INS_EV2IS_SHIFT) /* CCU4x.INyE */ +# define CCU4_CC4_INS_EV2IS_INF (5 << CCU4_CC4_INS_EV2IS_SHIFT) /* CCU4x.INyF */ +# define CCU4_CC4_INS_EV2IS_ING (6 << CCU4_CC4_INS_EV2IS_SHIFT) /* CCU4x.INyG */ +# define CCU4_CC4_INS_EV2IS_INH (7 << CCU4_CC4_INS_EV2IS_SHIFT) /* CCU4x.INyH */ +# define CCU4_CC4_INS_EV2IS_INI (8 << CCU4_CC4_INS_EV2IS_SHIFT) /* CCU4x.INyI */ +# define CCU4_CC4_INS_EV2IS_INJ (9 << CCU4_CC4_INS_EV2IS_SHIFT) /* CCU4x.INyJ */ +# define CCU4_CC4_INS_EV2IS_INK (10 << CCU4_CC4_INS_EV2IS_SHIFT) /* CCU4x.INyK */ +# define CCU4_CC4_INS_EV2IS_INL (11 << CCU4_CC4_INS_EV2IS_SHIFT) /* CCU4x.INyL */ +# define CCU4_CC4_INS_EV2IS_INM (12 << CCU4_CC4_INS_EV2IS_SHIFT) /* CCU4x.INyM */ +# define CCU4_CC4_INS_EV2IS_INN (13 << CCU4_CC4_INS_EV2IS_SHIFT) /* CCU4x.INyN */ +# define CCU4_CC4_INS_EV2IS_INO (14 << CCU4_CC4_INS_EV2IS_SHIFT) /* CCU4x.INyO */ +# define CCU4_CC4_INS_EV2IS_INP (15 << CCU4_CC4_INS_EV2IS_SHIFT) /* CCU4x.INyP */ +#define CCU4_CC4_INS_EV0EM_SHIFT (16) /* Bits 16-17: Event 0 Edge Selection */ +#define CCU4_CC4_INS_EV0EM_MASK (3 << CCU4_CC4_INS_EV0EM_SHIFT) +# define CCU4_CC4_INS_EV0EM_NA (0 << CCU4_CC4_INS_EV0EM_SHIFT) /* No action */ +# define CCU4_CC4_INS_EV0EM_RE (1 << CCU4_CC4_INS_EV0EM_SHIFT) /* Signal active on rising edge */ +# define CCU4_CC4_INS_EV0EM_FE (2 << CCU4_CC4_INS_EV0EM_SHIFT) /* Signal active on falling edge */ +# define CCU4_CC4_INS_EV0EM_BE (3 << CCU4_CC4_INS_EV0EM_SHIFT) /* Signal active on both edges */ +#define CCU4_CC4_INS_EV1EM_SHIFT (18) /* Bits 18-19: Event 1 Edge Selection */ +#define CCU4_CC4_INS_EV1EM_MASK (3 << CCU4_CC4_INS_EV1EM_SHIFT) +# define CCU4_CC4_INS_EV1EM_NA (0 << CCU4_CC4_INS_EV1EM_SHIFT) /* No action */ +# define CCU4_CC4_INS_EV1EM_RE (1 << CCU4_CC4_INS_EV1EM_SHIFT) /* Signal active on rising edge */ +# define CCU4_CC4_INS_EV1EM_FE (2 << CCU4_CC4_INS_EV1EM_SHIFT) /* Signal active on falling edge */ +# define CCU4_CC4_INS_EV1EM_BE (3 << CCU4_CC4_INS_EV1EM_SHIFT) /* Signal active on both edges */ +#define CCU4_CC4_INS_EV2EM_SHIFT (20) /* Bits 20-21: Event 2 Edge Selection */ +#define CCU4_CC4_INS_EV2EM_MASK (0x300000 << CCU4_CC4_INS_EV2EM_SHIFT) +# define CCU4_CC4_INS_EV2EM_NA (0 << CCU4_CC4_INS_EV2EM_SHIFT) /* No action */ +# define CCU4_CC4_INS_EV2EM_RE (1 << CCU4_CC4_INS_EV2EM_SHIFT) /* Signal active on rising edge */ +# define CCU4_CC4_INS_EV2EM_FE (2 << CCU4_CC4_INS_EV2EM_SHIFT) /* Signal active on falling edge */ +# define CCU4_CC4_INS_EV2EM_BE (3 << CCU4_CC4_INS_EV2EM_SHIFT) /* Signal active on both edges */ +#define CCU4_CC4_INS_EV0LM_SHIFT (22) /* Bit 22: Event 0 Level Selection */ +#define CCU4_CC4_INS_EV0LM_MASK (1 << CCU4_CC4_INS_EV0LM_SHIFT) +#define CCU4_CC4_INS_EV1LM_SHIFT (23) /* Bit 23: Event 1 Level Selection */ +#define CCU4_CC4_INS_EV1LM_MASK (1 << CCU4_CC4_INS_EV1LM_SHIFT) +#define CCU4_CC4_INS_EV2LM_SHIFT (24) /* Bit 24: Event 2 Level Selection */ +#define CCU4_CC4_INS_EV2LM_MASK (1 << CCU4_CC4_INS_EV2LM_SHIFT) +#define CCU4_CC4_INS_LPF0M_SHIFT (25) /* Bits 25-26: Event 0 Low Pass Filter Configuration */ +#define CCU4_CC4_INS_LPF0M_MASK (3 << CCU4_CC4_INS_LPF0M_SHIFT) +# define CCU4_CC4_INS_LPF0M_DISABLED (0 << CCU4_CC4_INS_LPF0M_SHIFT) /* LPF is disabled */ +# define CCU4_CC4_INS_LPF0M_3CC (1 << CCU4_CC4_INS_LPF0M_SHIFT) /* 3 clock cycles of fCCU4 */ +# define CCU4_CC4_INS_LPF0M_5CC (2 << CCU4_CC4_INS_LPF0M_SHIFT) /* 5 clock cycles of fCCU4 */ +# define CCU4_CC4_INS_LPF0M_7CC (3 << CCU4_CC4_INS_LPF0M_SHIFT) /* 7 clock cycles of fCCU4 */ +#define CCU4_CC4_INS_LPF1M_SHIFT (27) /* Bits 27-28: Event 1 Low Pass Filter Configuration */ +#define CCU4_CC4_INS_LPF1M_MASK (3 << CCU4_CC4_INS_LPF1M_SHIFT) +# define CCU4_CC4_INS_LPF1M_DISABLED (0 << CCU4_CC4_INS_LPF1M_SHIFT) /* LPF is disabled */ +# define CCU4_CC4_INS_LPF1M_3CC (1 << CCU4_CC4_INS_LPF1M_SHIFT) /* 3 clock cycles of fCCU4 */ +# define CCU4_CC4_INS_LPF1M_5CC (2 << CCU4_CC4_INS_LPF1M_SHIFT) /* 5 clock cycles of fCCU4 */ +# define CCU4_CC4_INS_LPF1M_7CC (3 << CCU4_CC4_INS_LPF1M_SHIFT) /* 7 clock cycles of fCCU4 */ +#define CCU4_CC4_INS_LPF2M_SHIFT (29) /* Bits 29-30: Event 2 Low Pass Filter Configuration */ +#define CCU4_CC4_INS_LPF2M_MASK (3 << CCU4_CC4_INS_LPF2M_SHIFT) +# define CCU4_CC4_INS_LPF2M_DISABLED (0 << CCU4_CC4_INS_LPF2M_SHIFT) /* LPF is disabled */ +# define CCU4_CC4_INS_LPF2M_3CC (1 << CCU4_CC4_INS_LPF2M_SHIFT) /* 3 clock cycles of fCCU4 */ +# define CCU4_CC4_INS_LPF2M_5CC (2 << CCU4_CC4_INS_LPF2M_SHIFT) /* 5 clock cycles of fCCU4 */ +# define CCU4_CC4_INS_LPF2M_7CC (3 << CCU4_CC4_INS_LPF2M_SHIFT) /* 7 clock cycles of fCCU4 */ + +/* Connection Matrix Control (CC4yCMC) */ + +#define CCU4_CC4_CMC_STRTS_SHIFT (0) /* Bits 0-1: External Start Functionality Selector */ +#define CCU4_CC4_CMC_STRTS_MASK (3 << CCU4_CC4_CMC_STRTS_SHIFT) +#define CCU4_CC4_CMC_ENDS_SHIFT (2) /* Bits 2-3: External Stop Functionality Selector */ +#define CCU4_CC4_CMC_ENDS_MASK (3 << CCU4_CC4_CMC_ENDS_SHIFT) +#define CCU4_CC4_CMC_CAP0S_SHIFT (4) /* Bits 4-5: External Capture 0 Functionality Selector */ +#define CCU4_CC4_CMC_CAP0S_MASK (3 << CCU4_CC4_CMC_CAP0S_SHIFT) +#define CCU4_CC4_CMC_CAP1S_SHIFT (6) /* Bits 6-7: External Capture 1 Functionality Selector */ +#define CCU4_CC4_CMC_CAP1S_MASK (3 << CCU4_CC4_CMC_CAP1S_SHIFT) +#define CCU4_CC4_CMC_GATES_SHIFT (8) /* Bits 8-9: External Gate Functionality Selector */ +#define CCU4_CC4_CMC_GATES_MASK (3 << CCU4_CC4_CMC_GATES_SHIFT) +#define CCU4_CC4_CMC_UDS_SHIFT (10) /* Bits 10-11: External Up/Down Functionality Selector */ +#define CCU4_CC4_CMC_UDS_MASK (3 << CCU4_CC4_CMC_UDS_SHIFT) +#define CCU4_CC4_CMC_LDS_SHIFT (12) /* Bits 12-13: External Timer Load Functionality Selector */ +#define CCU4_CC4_CMC_LDS_MASK (3 << CCU4_CC4_CMC_LDS_SHIFT) +#define CCU4_CC4_CMC_CNTS_SHIFT (14) /* Bits 14-15: External Count Selector */ +#define CCU4_CC4_CMC_CNTS_MASK (3 << CCU4_CC4_CMC_CNTS_SHIFT) +#define CCU4_CC4_CMC_OFS_SHIFT (16) /* Bit 16: Override Function Selector */ +#define CCU4_CC4_CMC_OFS_MASK (1 << CCU4_CC4_CMC_OFS_SHIFT) +#define CCU4_CC4_CMC_TS_SHIFT (17) /* Bit 17: Trap Function Selector */ +#define CCU4_CC4_CMC_TS_MASK (1 << CCU4_CC4_CMC_TS_SHIFT) +#define CCU4_CC4_CMC_MOS_SHIFT (18) /* Bits 18-19: External Modulation Functionality Selector */ +#define CCU4_CC4_CMC_MOS_MASK (3 << CCU4_CC4_CMC_MOS_SHIFT) +#define CCU4_CC4_CMC_TCE_SHIFT (20) /* Bit 20: Timer Concatenation Enable */ +#define CCU4_CC4_CMC_TCE_MASK (1 << CCU4_CC4_CMC_TCE_SHIFT) + +/* Slice Timer Status (CC4yTCST) */ + +#define CCU4_CC4_TCST_TRB_SHIFT (0) /* Bit 0: Timer Run Bit */ +#define CCU4_CC4_TCST_TRB_MASK (1 << CCU4_CC4_TCST_TRB_SHIFT) +#define CCU4_CC4_TCST_CDIR_SHIFT (1) /* Bit 1: Timer Counting Direction */ +#define CCU4_CC4_TCST_CDIR_MASK (1 << CCU4_CC4_TCST_CDIR_SHIFT) + +/* Slice Timer Run Set (CC4yTCSET) */ + +#define CCU4_CC4_TCSET_TRBS_SHIFT (0) /* Bit 0: Timer Run Bit set */ +#define CCU4_CC4_TCSET_TRBS_MASK (1 << CCU4_CC4_TCSET_TRBS_SHIFT) + +/* Slice Timer Clear (CC4yTCCLR) */ + +#define CCU4_CC4_TCCLR_TRBC_SHIFT (0) /* Bit 0: Timer Run Bit Clear */ +#define CCU4_CC4_TCCLR_TRBC_MASK (1 << CCU4_CC4_TCCLR_TRBC_SHIFT) +#define CCU4_CC4_TCCLR_TCC_SHIFT (1) /* Bit 1: Timer Clear */ +#define CCU4_CC4_TCCLR_TCC_MASK (1 << CCU4_CC4_TCCLR_TCC_SHIFT) +#define CCU4_CC4_TCCLR_DITC_SHIFT (2) /* Bit 2: Dither Counter Clear */ +#define CCU4_CC4_TCCLR_DITC_MASK (1 << CCU4_CC4_TCCLR_DITC_SHIFT) + +/* Slice Timer Control (CC4yTC) */ + +#define CCU4_CC4_TC_TCM_SHIFT (0) /* Bit 0: Timer Counting Mode */ +#define CCU4_CC4_TC_TCM_MASK (1 << CCU4_CC4_TC_TCM_SHIFT) +#define CCU4_CC4_TC_TSSM_SHIFT (1) /* Bit 1: Timer Single Shot Mode */ +#define CCU4_CC4_TC_TSSM_MASK (1 << CCU4_CC4_TC_TSSM_SHIFT) +#define CCU4_CC4_TC_CLST_SHIFT (2) /* Bit 2: Shadow Transfer on Clear */ +#define CCU4_CC4_TC_CLST_MASK (1 << CCU4_CC4_TC_CLST_SHIFT) +#define CCU4_CC4_TC_CMOD_SHIFT (3) /* Bit 3: Capture Compare Mode */ +#define CCU4_CC4_TC_CMOD_MASK (1 << CCU4_CC4_TC_CMOD_SHIFT) +#define CCU4_CC4_TC_ECM_SHIFT (4) /* Bit 4: Extended Capture Mode */ +#define CCU4_CC4_TC_ECM_MASK (1 << CCU4_CC4_TC_ECM_SHIFT) +#define CCU4_CC4_TC_CAPC_SHIFT (5) /* Bits 5-6: Clear on Capture Control */ +#define CCU4_CC4_TC_CAPC_MASK (3 << CCU4_CC4_TC_CAPC_SHIFT) +#define CCU4_CC4_TC_ENDM_SHIFT (8) /* Bits 8-9: Extended Stop Function Control */ +#define CCU4_CC4_TC_ENDM_MASK (3 << CCU4_CC4_TC_ENDM_SHIFT) +#define CCU4_CC4_TC_STRM_SHIFT (10) /* Bit 10: Extended Start Function Control */ +#define CCU4_CC4_TC_STRM_MASK (1 << CCU4_CC4_TC_STRM_SHIFT) +#define CCU4_CC4_TC_SCE_SHIFT (11) /* Bit 11: Equal Capture Event enable */ +#define CCU4_CC4_TC_SCE_MASK (1 << CCU4_CC4_TC_SCE_SHIFT) +#define CCU4_CC4_TC_CCS_SHIFT (12) /* Bit 12: Continuous Capture Enable */ +#define CCU4_CC4_TC_CCS_MASK (1 << CCU4_CC4_TC_CCS_SHIFT) +#define CCU4_CC4_TC_DITHE_SHIFT (13) /* Bits 13-14: Dither Enable */ +#define CCU4_CC4_TC_DITHE_MASK (3 << CCU4_CC4_TC_DITHE_SHIFT) +#define CCU4_CC4_TC_DIM_SHIFT (15) /* Bit 15: Dither input selector */ +#define CCU4_CC4_TC_DIM_MASK (1 << CCU4_CC4_TC_DIM_SHIFT) +#define CCU4_CC4_TC_FPE_SHIFT (16) /* Bit 16: Floating Prescaler enable */ +#define CCU4_CC4_TC_FPE_MASK (1 << CCU4_CC4_TC_FPE_SHIFT) +#define CCU4_CC4_TC_TRAPE_SHIFT (17) /* Bit 17: TRAP enable */ +#define CCU4_CC4_TC_TRAPE_MASK (1 << CCU4_CC4_TC_TRAPE_SHIFT) +#define CCU4_CC4_TC_TRPSE_SHIFT (21) /* Bit 21: TRAP Synchronization Enable */ +#define CCU4_CC4_TC_TRPSE_MASK (1 << CCU4_CC4_TC_TRPSE_SHIFT) +#define CCU4_CC4_TC_TRPSW_SHIFT (22) /* Bit 22: TRAP State Clear Control */ +#define CCU4_CC4_TC_TRPSW_MASK (1 << CCU4_CC4_TC_TRPSW_SHIFT) +#define CCU4_CC4_TC_EMS_SHIFT (23) /* Bit 23: External Modulation Synchronization */ +#define CCU4_CC4_TC_EMS_MASK (1 << CCU4_CC4_TC_EMS_SHIFT) +#define CCU4_CC4_TC_EMT_SHIFT (24) /* Bit 24: External Modulation Type */ +#define CCU4_CC4_TC_EMT_MASK (1 << CCU4_CC4_TC_EMT_SHIFT) +#define CCU4_CC4_TC_MCME_SHIFT (25) /* Bit 25: Multi Channel Mode Enable */ +#define CCU4_CC4_TC_MCME_MASK (1 << CCU4_CC4_TC_MCME_SHIFT) + +/* Passive Level Config (CC4yPSL) */ + +#define CCU4_CC4_PSL_PSL_SHIFT (0) /* Bit 0: Output Passive Level */ +#define CCU4_CC4_PSL_PSL_MASK (1 << CCU4_CC4_PSL_PSL_SHIFT) + +/* Dither Config (CC4yDIT) */ + +#define CCU4_CC4_DIT_DCV_SHIFT (0) /* Bits 0-3: Dither compare Value */ +#define CCU4_CC4_DIT_DCV_MASK (15 << CCU4_CC4_DIT_DCV_SHIFT) +#define CCU4_CC4_DIT_DCNT_SHIFT (8) /* Bits 8-11: Dither counter actual value */ +#define CCU4_CC4_DIT_DCNT_MASK (15 << CCU4_CC4_DIT_DCNT_SHIFT) + +/* Dither Shadow Register (CC4yDITS) */ + +#define CCU4_CC4_DITS_DCVS_SHIFT (0) /* Bits 0-3: Dither Shadow Compare Value */ +#define CCU4_CC4_DITS_DCVS_MASK (15 << CCU4_CC4_DITS_DCVS_SHIFT) + +/* Prescaler Control (CC4yPSC) */ + +#define CCU4_CC4_PSC_PSIV_SHIFT (0) /* Bits 0-3: Passive State Configuration */ +#define CCU4_CC4_PSC_PSIV_MASK (15 << CCU4_CC4_PSC_PSIV_SHIFT) + +/* Floating Prescaler Control (CC4yFPC) */ + +#define CCU4_CC4_FPC_PCMP_SHIFT (0) /* Bits 0-3: Floating Prescaler Compare Value */ +#define CCU4_CC4_FPC_PCMP_MASK (15 << CCU4_CC4_FPC_PCMP_SHIFT) +#define CCU4_CC4_FPC_PVAL_SHIFT (8) /* Bits 8-11: Actual Prescaler Value */ +#define CCU4_CC4_FPC_PVAL_MASK (15 << CCU4_CC4_FPC_PVAL_SHIFT) + +/* Floating Prescaler Shadow (CC4yFPCS) */ + +#define CCU4_CC4_FPCS_PCMP_SHIFT (0) /* Bits 0-3: Passive Comparator Pattern */ +#define CCU4_CC4_FPCS_PCMP_MASK (15 << CCU4_CC4_FPCS_PCMP_SHIFT) + +/* Timer Period Value (CC4yPR) */ + +#define CCU4_CC4_PR_PR_SHIFT (0) /* Bits 0-15: Period Register */ +#define CCU4_CC4_PR_PR_MASK (0xFFFF << CCU4_CC4_PR_PR_SHIFT) + +/* Timer Shadow Period Value (CC4yPRS) */ + +#define CCU4_CC4_PRS_PRS_SHIFT (0) /* Bits 0-15: Period Register */ +#define CCU4_CC4_PRS_PRS_MASK (0xFFFF << CCU4_CC4_PRS_PRS_SHIFT) + +/* Timer Compare Value (CC4yCR) */ + +#define CCU4_CC4_CR_CR_SHIFT (0) /* Bits 0-15: Compare Register Value */ +#define CCU4_CC4_CR_CR_MASK (0xFFFF << CCU4_CC4_CR_CR_SHIFT) + +/* Timer Shadow Compare Value (CC4yCRS) */ + +#define CCU4_CC4_CRS_CRS_SHIFT (0) /* Bits 0-15: Compare Register */ +#define CCU4_CC4_CRS_CRS_MASK (0xFFFF << CCU4_CC4_CRS_CRS_SHIFT) + +/* Timer Value (CC4yTIMER) */ + +#define CCU4_CC4_TIMER_TVAL_SHIFT (0) /* Bits 0-15: Timer Value */ +#define CCU4_CC4_TIMER_TVAL_MASK (0xFFFF << CCU4_CC4_TIMER_TVAL_SHIFT) + +/* Capture Register 0 (CC4yC0V) */ + +#define CCU4_CC4_C0V_CAPTV_SHIFT (0) /* Bits 0-15: Capture Value */ +#define CCU4_CC4_C0V_CAPTV_MASK (0xFFFF << CCU4_CC4_C0V_CAPTV_SHIFT) +#define CCU4_CC4_C0V_FPCV_SHIFT (16) /* Bits 16-19: Prescaler Value */ +#define CCU4_CC4_C0V_FPCV_MASK (15 << CCU4_CC4_C0V_FPCV_SHIFT) +#define CCU4_CC4_C0V_FFL_SHIFT (20) /* Bit 20: Full Flag */ +#define CCU4_CC4_C0V_FFL_MASK (1 << CCU4_CC4_C0V_FFL_SHIFT) + +/* Capture Register 1 (CC4yC1V) */ + +#define CCU4_CC4_C1V_CAPTV_SHIFT (0) /* Bits 0-15: Capture Value */ +#define CCU4_CC4_C1V_CAPTV_MASK (0xFFFF << CCU4_CC4_C1V_CAPTV_SHIFT) +#define CCU4_CC4_C1V_FPCV_SHIFT (16) /* Bits 16-19: Prescaler Value */ +#define CCU4_CC4_C1V_FPCV_MASK (15 << CCU4_CC4_C1V_FPCV_SHIFT) +#define CCU4_CC4_C1V_FFL_SHIFT (20) /* Bit 20: Full Flag */ +#define CCU4_CC4_C1V_FFL_MASK (1 << CCU4_CC4_C1V_FFL_SHIFT) + +/* Capture Register 2 (CC4yC2V) */ + +#define CCU4_CC4_C2V_CAPTV_SHIFT (0) /* Bits 0-15: Capture Value */ +#define CCU4_CC4_C2V_CAPTV_MASK (0xFFFF << CCU4_CC4_C2V_CAPTV_SHIFT) +#define CCU4_CC4_C2V_FPCV_SHIFT (16) /* Bits 16-19: Prescaler Value */ +#define CCU4_CC4_C2V_FPCV_MASK (15 << CCU4_CC4_C2V_FPCV_SHIFT) +#define CCU4_CC4_C2V_FFL_SHIFT (20) /* Bit 20: Full Flag */ +#define CCU4_CC4_C2V_FFL_MASK (1 << CCU4_CC4_C2V_FFL_SHIFT) + +/* Capture Register 3 (CC4yC3V) */ + +#define CCU4_CC4_C3V_CAPTV_SHIFT (0) /* Bits 0-15: Capture Value */ +#define CCU4_CC4_C3V_CAPTV_MASK (0xFFFF << CCU4_CC4_C3V_CAPTV_SHIFT) +#define CCU4_CC4_C3V_FPCV_SHIFT (16) /* Bits 16-19: Prescaler Value */ +#define CCU4_CC4_C3V_FPCV_MASK (15 << CCU4_CC4_C3V_FPCV_SHIFT) +#define CCU4_CC4_C3V_FFL_SHIFT (20) /* Bit 20: Full Flag */ +#define CCU4_CC4_C3V_FFL_MASK (1 << CCU4_CC4_C3V_FFL_SHIFT) + +/* Interrupt Status (CC4yINTS) */ + +#define CCU4_CC4_INTS_PMUS_SHIFT (0) /* Bit 0: Period Match while Counting Up */ +#define CCU4_CC4_INTS_PMUS_MASK (1 << CCU4_CC4_INTS_PMUS_SHIFT) +#define CCU4_CC4_INTS_OMDS_SHIFT (1) /* Bit 1: One Match while Counting Down */ +#define CCU4_CC4_INTS_OMDS_MASK (1 << CCU4_CC4_INTS_OMDS_SHIFT) +#define CCU4_CC4_INTS_CMUS_SHIFT (2) /* Bit 2: Compare Match while Counting Up */ +#define CCU4_CC4_INTS_CMUS_MASK (1 << CCU4_CC4_INTS_CMUS_SHIFT) +#define CCU4_CC4_INTS_CMDS_SHIFT (3) /* Bit 3: Compare Match while Counting Down */ +#define CCU4_CC4_INTS_CMDS_MASK (1 << CCU4_CC4_INTS_CMDS_SHIFT) +#define CCU4_CC4_INTS_E0AS_SHIFT (8) /* Bit 8: Event 0 Detection Status */ +#define CCU4_CC4_INTS_E0AS_MASK (1 << CCU4_CC4_INTS_E0AS_SHIFT) +#define CCU4_CC4_INTS_E1AS_SHIFT (9) /* Bit 9: Event 1 Detection Status */ +#define CCU4_CC4_INTS_E1AS_MASK (1 << CCU4_CC4_INTS_E1AS_SHIFT) +#define CCU4_CC4_INTS_E2AS_SHIFT (10) /* Bit 10: Event 2 Detection Status */ +#define CCU4_CC4_INTS_E2AS_MASK (1 << CCU4_CC4_INTS_E2AS_SHIFT) +#define CCU4_CC4_INTS_TRPF_SHIFT (11) /* Bit 11: Trap Flag Status */ +#define CCU4_CC4_INTS_TRPF_MASK (1 << CCU4_CC4_INTS_TRPF_SHIFT) + +/* Interrupt Enable Control (CC4yINTE) */ + +#define CCU4_CC4_INTE_PME_SHIFT (0) /* Bit 0: Period match while counting up enable */ +#define CCU4_CC4_INTE_PME_MASK (1 << CCU4_CC4_INTE_PME_SHIFT) +#define CCU4_CC4_INTE_OME_SHIFT (1) /* Bit 1: One match while counting down enable */ +#define CCU4_CC4_INTE_OME_MASK (1 << CCU4_CC4_INTE_OME_SHIFT) +#define CCU4_CC4_INTE_CMUE_SHIFT (2) /* Bit 2: Compare match while counting up enable */ +#define CCU4_CC4_INTE_CMUE_MASK (1 << CCU4_CC4_INTE_CMUE_SHIFT) +#define CCU4_CC4_INTE_CMDE_SHIFT (3) /* Bit 3: Compare match while counting down enable */ +#define CCU4_CC4_INTE_CMDE_MASK (1 << CCU4_CC4_INTE_CMDE_SHIFT) +#define CCU4_CC4_INTE_E0AE_SHIFT (8) /* Bit 8: Event 0 interrupt enable */ +#define CCU4_CC4_INTE_E0AE_MASK (1 << CCU4_CC4_INTE_E0AE_SHIFT) +#define CCU4_CC4_INTE_E1AE_SHIFT (9) /* Bit 9: Event 1 interrupt enable */ +#define CCU4_CC4_INTE_E1AE_MASK (1 << CCU4_CC4_INTE_E1AE_SHIFT) +#define CCU4_CC4_INTE_E2AE_SHIFT (10) /* Bit 10: Event 2 interrupt enable */ +#define CCU4_CC4_INTE_E2AE_MASK (1 << CCU4_CC4_INTE_E2AE_SHIFT) + +/* Service Request Selector (CC4ySRS) */ + +#define CCU4_CC4_SRS_POSR_SHIFT (0) /* Bits 0-1: Period/One match Service request selector */ +#define CCU4_CC4_SRS_POSR_MASK (3 << CCU4_CC4_SRS_POSR_SHIFT) +#define CCU4_CC4_SRS_CMSR_SHIFT (2) /* Bits 2-3: Compare match Service request selector */ +#define CCU4_CC4_SRS_CMSR_MASK (3 << CCU4_CC4_SRS_CMSR_SHIFT) +#define CCU4_CC4_SRS_E0SR_SHIFT (8) /* Bits 8-9: Event 0 Service request selector */ +#define CCU4_CC4_SRS_E0SR_MASK (3 << CCU4_CC4_SRS_E0SR_SHIFT) +#define CCU4_CC4_SRS_E1SR_SHIFT (10) /* Bits 10-11: Event 1 Service request selector */ +#define CCU4_CC4_SRS_E1SR_MASK (3 << CCU4_CC4_SRS_E1SR_SHIFT) +#define CCU4_CC4_SRS_E2SR_SHIFT (12) /* Bits 12-13: Event 2 Service request selector */ +#define CCU4_CC4_SRS_E2SR_MASK (3 << CCU4_CC4_SRS_E2SR_SHIFT) + +/* Interrupt Status Set (CC4ySWS) */ + +#define CCU4_CC4_SWS_SPM_SHIFT (0) /* Bit 0: Period match while counting up set */ +#define CCU4_CC4_SWS_SPM_MASK (1 << CCU4_CC4_SWS_SPM_SHIFT) +#define CCU4_CC4_SWS_SOM_SHIFT (1) /* Bit 1: One match while counting down set */ +#define CCU4_CC4_SWS_SOM_MASK (1 << CCU4_CC4_SWS_SOM_SHIFT) +#define CCU4_CC4_SWS_SCMU_SHIFT (2) /* Bit 2: Compare match while counting up set */ +#define CCU4_CC4_SWS_SCMU_MASK (1 << CCU4_CC4_SWS_SCMU_SHIFT) +#define CCU4_CC4_SWS_SCMD_SHIFT (3) /* Bit 3: Compare match while counting down set */ +#define CCU4_CC4_SWS_SCMD_MASK (1 << CCU4_CC4_SWS_SCMD_SHIFT) +#define CCU4_CC4_SWS_SE0A_SHIFT (8) /* Bit 8: Event 0 detection set */ +#define CCU4_CC4_SWS_SE0A_MASK (1 << CCU4_CC4_SWS_SE0A_SHIFT) +#define CCU4_CC4_SWS_SE1A_SHIFT (9) /* Bit 9: Event 1 detection set */ +#define CCU4_CC4_SWS_SE1A_MASK (1 << CCU4_CC4_SWS_SE1A_SHIFT) +#define CCU4_CC4_SWS_SE2A_SHIFT (10) /* Bit 10: Event 2 detection set */ +#define CCU4_CC4_SWS_SE2A_MASK (1 << CCU4_CC4_SWS_SE2A_SHIFT) +#define CCU4_CC4_SWS_STRPF_SHIFT (11) /* Bit 11: Trap Flag status set */ +#define CCU4_CC4_SWS_STRPF_MASK (1 << CCU4_CC4_SWS_STRPF_SHIFT) + +/* Interrupt Status Clear (CC4ySWR) */ + +#define CCU4_CC4_SWR_RPM_SHIFT (0) /* Bit 0: Period match while counting up clear */ +#define CCU4_CC4_SWR_RPM_MASK (1 << CCU4_CC4_SWR_RPM_SHIFT) +#define CCU4_CC4_SWR_ROM_SHIFT (1) /* Bit 1: One match while counting down clear */ +#define CCU4_CC4_SWR_ROM_MASK (1 << CCU4_CC4_SWR_ROM_SHIFT) +#define CCU4_CC4_SWR_RCMU_SHIFT (2) /* Bit 2: Compare match while counting up clear */ +#define CCU4_CC4_SWR_RCMU_MASK (1 << CCU4_CC4_SWR_RCMU_SHIFT) +#define CCU4_CC4_SWR_RCMD_SHIFT (3) /* Bit 3: Compare match while counting down clear */ +#define CCU4_CC4_SWR_RCMD_MASK (1 << CCU4_CC4_SWR_RCMD_SHIFT) +#define CCU4_CC4_SWR_RE0A_SHIFT (8) /* Bit 8: Event 0 detection clear */ +#define CCU4_CC4_SWR_RE0A_MASK (1 << CCU4_CC4_SWR_RE0A_SHIFT) +#define CCU4_CC4_SWR_RE1A_SHIFT (9) /* Bit 9: Event 1 detection clear */ +#define CCU4_CC4_SWR_RE1A_MASK (1 << CCU4_CC4_SWR_RE1A_SHIFT) +#define CCU4_CC4_SWR_RE2A_SHIFT (10) /* Bit 10: Event 2 detection clear */ +#define CCU4_CC4_SWR_RE2A_MASK (1 << CCU4_CC4_SWR_RE2A_SHIFT) +#define CCU4_CC4_SWR_RTRPF_SHIFT (11) /* Bit 11: Trap Flag status clear */ +#define CCU4_CC4_SWR_RTRPF_MASK (1 << CCU4_CC4_SWR_RTRPF_SHIFT) + +/* Extended Read Back 0 (CC4yECRD0) */ + +#define CCU4_CC4_ECRD0_CAPV_SHIFT (0) /* Bits 0-15: Timer Capture Value */ +#define CCU4_CC4_ECRD0_CAPV_MASK (0xFFFF << CCU4_CC4_ECRD0_CAPV_SHIFT) +#define CCU4_CC4_ECRD0_FPCV_SHIFT (16) /* Bits 16-19: Prescaler Capture value */ +#define CCU4_CC4_ECRD0_FPCV_MASK (15 << CCU4_CC4_ECRD0_FPCV_SHIFT) +#define CCU4_CC4_ECRD0_SPTR_SHIFT (20) /* Bits 20-21: Slice pointer */ +#define CCU4_CC4_ECRD0_SPTR_MASK (3 << CCU4_CC4_ECRD0_SPTR_SHIFT) +#define CCU4_CC4_ECRD0_VPTR_SHIFT (22) /* Bits 22-23: Capture register pointer */ +#define CCU4_CC4_ECRD0_VPTR_MASK (3 << CCU4_CC4_ECRD0_VPTR_SHIFT) +#define CCU4_CC4_ECRD0_FFL_SHIFT (24) /* Bit 24: Full Flag */ +#define CCU4_CC4_ECRD0_FFL_MASK (1 << CCU4_CC4_ECRD0_FFL_SHIFT) +#define CCU4_CC4_ECRD0_LCV_SHIFT (25) /* Bit 25: Lost Capture Value */ +#define CCU4_CC4_ECRD0_LCV_MASK (1 << CCU4_CC4_ECRD0_LCV_SHIFT) + +/* Extended Read Back 1 (CC4yECRD1) */ + +#define CCU4_CC4_ECRD1_CAPV_SHIFT (0) /* Bits 0-15: Timer Capture Value */ +#define CCU4_CC4_ECRD1_CAPV_MASK (0xFFFF << CCU4_CC4_ECRD1_CAPV_SHIFT) +#define CCU4_CC4_ECRD1_FPCV_SHIFT (16) /* Bits 16-19: Prescaler Capture value */ +#define CCU4_CC4_ECRD1_FPCV_MASK (15 << CCU4_CC4_ECRD1_FPCV_SHIFT) +#define CCU4_CC4_ECRD1_SPTR_SHIFT (20) /* Bits 20-21: Slice pointer */ +#define CCU4_CC4_ECRD1_SPTR_MASK (3 << CCU4_CC4_ECRD1_SPTR_SHIFT) +#define CCU4_CC4_ECRD1_VPTR_SHIFT (22) /* Bits 22-23: Capture register pointer */ +#define CCU4_CC4_ECRD1_VPTR_MASK (3 << CCU4_CC4_ECRD1_VPTR_SHIFT) +#define CCU4_CC4_ECRD1_FFL_SHIFT (24) /* Bit 24: Full Flag */ +#define CCU4_CC4_ECRD1_FFL_MASK (1 << CCU4_CC4_ECRD1_FFL_SHIFT) +#define CCU4_CC4_ECRD1_LCV_SHIFT (25) /* Bit 25: Lost Capture Value */ +#define CCU4_CC4_ECRD1_LCV_MASK (1 << CCU4_CC4_ECRD1_LCV_SHIFT) + +#endif /* __ARCH_ARM_SRC_XMC4_HARDWARE_XMC4_CCU4_H */ diff --git a/arch/arm/src/xmc4/hardware/xmc4_flash.h b/arch/arm/src/xmc4/hardware/xmc4_flash.h index 19a022785697e..07db5c477ecdd 100644 --- a/arch/arm/src/xmc4/hardware/xmc4_flash.h +++ b/arch/arm/src/xmc4/hardware/xmc4_flash.h @@ -64,6 +64,42 @@ * Pre-processor Definitions ****************************************************************************/ +/* Flash memory address */ + +#define XMC4_FLASH_S0_OFFSET 0X000000 +#define XMC4_FLASH_S1_OFFSET 0X004000 +#define XMC4_FLASH_S2_OFFSET 0X008000 +#define XMC4_FLASH_S3_OFFSET 0X00c000 +#define XMC4_FLASH_S4_OFFSET 0X010000 +#define XMC4_FLASH_S5_OFFSET 0X014000 +#define XMC4_FLASH_S6_OFFSET 0X018000 +#define XMC4_FLASH_S7_OFFSET 0X01c000 +#define XMC4_FLASH_S8_OFFSET 0X020000 +#define XMC4_FLASH_S9_OFFSET 0X040000 +#define XMC4_FLASH_S10_OFFSET 0X080000 +#define XMC4_FLASH_S11_OFFSET 0X0c0000 +#define XMC4_FLASH_S12_OFFSET 0X100000 +#define XMC4_FLASH_S13_OFFSET 0X140000 +#define XMC4_FLASH_S14_OFFSET 0X180000 +#define XMC4_FLASH_S15_OFFSET 0X1c0000 + +#define XMC4_FLASH_S0 (XMC4_UNCACHED_PFLASH_BASE + XMC4_FLASH_S0_OFFSET) +#define XMC4_FLASH_S1 (XMC4_UNCACHED_PFLASH_BASE + XMC4_FLASH_S1_OFFSET) +#define XMC4_FLASH_S2 (XMC4_UNCACHED_PFLASH_BASE + XMC4_FLASH_S2_OFFSET) +#define XMC4_FLASH_S3 (XMC4_UNCACHED_PFLASH_BASE + XMC4_FLASH_S3_OFFSET) +#define XMC4_FLASH_S4 (XMC4_UNCACHED_PFLASH_BASE + XMC4_FLASH_S4_OFFSET) +#define XMC4_FLASH_S5 (XMC4_UNCACHED_PFLASH_BASE + XMC4_FLASH_S5_OFFSET) +#define XMC4_FLASH_S6 (XMC4_UNCACHED_PFLASH_BASE + XMC4_FLASH_S6_OFFSET) +#define XMC4_FLASH_S7 (XMC4_UNCACHED_PFLASH_BASE + XMC4_FLASH_S7_OFFSET) +#define XMC4_FLASH_S8 (XMC4_UNCACHED_PFLASH_BASE + XMC4_FLASH_S8_OFFSET) +#define XMC4_FLASH_S9 (XMC4_UNCACHED_PFLASH_BASE + XMC4_FLASH_S9_OFFSET) +#define XMC4_FLASH_S10 (XMC4_UNCACHED_PFLASH_BASE + XMC4_FLASH_S10_OFFSET) +#define XMC4_FLASH_S11 (XMC4_UNCACHED_PFLASH_BASE + XMC4_FLASH_S11_OFFSET) +#define XMC4_FLASH_S12 (XMC4_UNCACHED_PFLASH_BASE + XMC4_FLASH_S12_OFFSET) +#define XMC4_FLASH_S13 (XMC4_UNCACHED_PFLASH_BASE + XMC4_FLASH_S13_OFFSET) +#define XMC4_FLASH_S14 (XMC4_UNCACHED_PFLASH_BASE + XMC4_FLASH_S14_OFFSET) +#define XMC4_FLASH_S15 (XMC4_UNCACHED_PFLASH_BASE + XMC4_FLASH_S15_OFFSET) + /* Register Offsets *********************************************************/ /* PMU Registers -- See ID register */ diff --git a/arch/arm/src/xmc4/hardware/xmc4_memorymap.h b/arch/arm/src/xmc4/hardware/xmc4_memorymap.h index 8dace60e4b24f..d20c41d22f299 100644 --- a/arch/arm/src/xmc4/hardware/xmc4_memorymap.h +++ b/arch/arm/src/xmc4/hardware/xmc4_memorymap.h @@ -80,6 +80,7 @@ * USCI - Universal Serial Interface */ +#define XMC4_UNCACHED_PFLASH_BASE 0X0c000000 /* Uncached PMU/flash start address */ #define XMC4_PBA0_BASE 0x40000000 /* PBA0 */ #define XMC4_VADC_BASE 0x40004000 /* VADC */ #define XMC4_VADC_G0_BASE 0x40004400 diff --git a/arch/arm/src/xmc4/hardware/xmc4_pinmux.h b/arch/arm/src/xmc4/hardware/xmc4_pinmux.h index 5ccc6dd5e5432..56f9a322ecc7c 100644 --- a/arch/arm/src/xmc4/hardware/xmc4_pinmux.h +++ b/arch/arm/src/xmc4/hardware/xmc4_pinmux.h @@ -373,6 +373,68 @@ #define GPIO_EBU_SDCLKO_1 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT5 | GPIO_PIN8) #define GPIO_EBU_SDCLKO_2 (GPIO_OUTPUT | GPIO_PINCTRL_HW0 | GPIO_PORT6 | GPIO_PIN4) #define GPIO_EBU_WAIT (GPIO_INPUT | GPIO_PINCTRL_HW1 | GPIO_PORT3 | GPIO_PIN3) + +#define GPIO_ECAT_CONF_OUTPUT GPIO_OUTPUT | GPIO_OUTPUT_PUSHPULL | GPIO_PINCTRL_SOFTWARE | GPIO_OUTPUT_CLEAR +#define GPIO_ECAT_CLK_25_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN0 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_CLK_25_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN13 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_LED_RUN (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT0 | GPIO_PIN8 | GPIO_OUTPUT_ALT3) +#define GPIO_ECAT_LED_ERR (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT0 | GPIO_PIN7 | GPIO_OUTPUT_ALT3) +#define GPIO_ECAT_MCLK (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT3 | GPIO_PIN3 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_MDO (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN12) +#define GPIO_ECAT_P0_LED_LINK_ACT_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT6 | GPIO_PIN3 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_P0_LED_LINK_ACT_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT1 | GPIO_PIN12 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_P0_LINK_STATUS (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN15) +#define GPIO_ECAT_P0_RXD0_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN0) +#define GPIO_ECAT_P0_RXD0_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN4) +#define GPIO_ECAT_P0_RXD1_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN1) +#define GPIO_ECAT_P0_RXD1_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN5) +#define GPIO_ECAT_P0_RXD2_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN2) +#define GPIO_ECAT_P0_RXD2_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN10) +#define GPIO_ECAT_P0_RXD3_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN7) +#define GPIO_ECAT_P0_RXD3_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN11) +#define GPIO_ECAT_P0_RX_CLK_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN4) +#define GPIO_ECAT_P0_RX_CLK_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN1) +#define GPIO_ECAT_P0_RX_DV_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN6) +#define GPIO_ECAT_P0_RX_DV_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN9) +#define GPIO_ECAT_P0_RX_ERR (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN6) +#define GPIO_ECAT_P0_TX_CLK_1 (GPIO_INPUT | GPIO_PORT5 | GPIO_PIN5) +#define GPIO_ECAT_P0_TX_CLK_2 (GPIO_INPUT | GPIO_PORT1 | GPIO_PIN0) +#define GPIO_ECAT_P0_TXD0_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN2 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_P0_TXD0_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN6 | GPIO_OUTPUT_ALT1) +#define GPIO_ECAT_P0_TXD1_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN4 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_P0_TXD1_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN7 | GPIO_OUTPUT_ALT1) +#define GPIO_ECAT_P0_TXD2_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN5 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_P0_TXD2_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN8 | GPIO_OUTPUT_ALT1) +#define GPIO_ECAT_P0_TXD3_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN6 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_P0_TXD3_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN2 | GPIO_OUTPUT_ALT1) +#define GPIO_ECAT_P0_TX_EN_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT6 | GPIO_PIN1 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_P0_TX_EN_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT1 | GPIO_PIN3 | GPIO_OUTPUT_ALT1) +#define GPIO_ECAT_P1_LED_LINK_ACT_1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT3 | GPIO_PIN12 | GPIO_OUTPUT_ALT1) +#define GPIO_ECAT_P1_LED_LINK_ACT_2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT0 | GPIO_PIN11 | GPIO_OUTPUT_ALT1) +#define GPIO_ECAT_P1_LINK_STATUS_1 (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN4) +#define GPIO_ECAT_P1_LINK_STATUS_2 (GPIO_INPUT_PULLUP | GPIO_PORT15 | GPIO_PIN3) +#define GPIO_ECAT_P1_RXD0_1 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN11) +#define GPIO_ECAT_P1_RXD0_2 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN7) +#define GPIO_ECAT_P1_RXD1_1 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN6) +#define GPIO_ECAT_P1_RXD1_2 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN12) +#define GPIO_ECAT_P1_RXD2_1 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN5) +#define GPIO_ECAT_P1_RXD2_2 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN13) +#define GPIO_ECAT_P1_RXD3_1 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN4) +#define GPIO_ECAT_P1_RXD3_2 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN14) +#define GPIO_ECAT_P1_RX_CLK_1 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN1) +#define GPIO_ECAT_P1_RX_CLK_2 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN6) +#define GPIO_ECAT_P1_RX_DV_1 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN9) +#define GPIO_ECAT_P1_RX_DV_2 (GPIO_INPUT | GPIO_PORT14 | GPIO_PIN15) +#define GPIO_ECAT_P1_RX_ERR_1 (GPIO_INPUT | GPIO_PORT15 | GPIO_PIN2) +#define GPIO_ECAT_P1_RX_ERR_2 (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN5) +#define GPIO_ECAT_P1_TX_CLK (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN10) +#define GPIO_ECAT_P1_TXD0 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT3 | GPIO_PIN1 | GPIO_OUTPUT_ALT3) +#define GPIO_ECAT_P1_TXD1 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT3 | GPIO_PIN2 | GPIO_OUTPUT_ALT3) +#define GPIO_ECAT_P1_TXD2 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT0 | GPIO_PIN2 | GPIO_OUTPUT_ALT1) +#define GPIO_ECAT_P1_TXD3 (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT0 | GPIO_PIN3 | GPIO_OUTPUT_ALT1) +#define GPIO_ECAT_P1_TX_EN (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSHARP | GPIO_PORT3 | GPIO_PIN0 | GPIO_OUTPUT_ALT4) +#define GPIO_ECAT_PHY_RESET (GPIO_ECAT_CONF_OUTPUT | GPIO_PADA2_STRONGSOFT | GPIO_PORT0 | GPIO_PIN0 | GPIO_OUTPUT_ALT1) + #define GPIO_ERU0_0A0 (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN1) #define GPIO_ERU0_0A1 (GPIO_INPUT | GPIO_PORT3 | GPIO_PIN2) #define GPIO_ERU0_0A2 (GPIO_INPUT | GPIO_PORT2 | GPIO_PIN5) @@ -658,6 +720,7 @@ #define GPIO_U1C0_MCLKOUT (GPIO_OUTPUT_ALT2 | GPIO_PORT5 | GPIO_PIN10) #define GPIO_U1C0_SCLKOUT_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT0 | GPIO_PIN11) #define GPIO_U1C0_SCLKOUT_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT5 | GPIO_PIN8) +#define GPIO_U1C0_SCLKOUT_3 (GPIO_OUTPUT_ALT4 | GPIO_PORT4 | GPIO_PIN0) #define GPIO_U1C0_SELO0_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT0 | GPIO_PIN6) #define GPIO_U1C0_SELO0_2 (GPIO_OUTPUT_ALT2 | GPIO_PORT5 | GPIO_PIN9) #define GPIO_U1C0_SELO1_1 (GPIO_OUTPUT_ALT2 | GPIO_PORT0 | GPIO_PIN14) diff --git a/arch/arm/src/xmc4/hardware/xmc4_scu.h b/arch/arm/src/xmc4/hardware/xmc4_scu.h index 5860225139bad..0f9d6c6a47884 100644 --- a/arch/arm/src/xmc4/hardware/xmc4_scu.h +++ b/arch/arm/src/xmc4/hardware/xmc4_scu.h @@ -74,6 +74,9 @@ #define XMC4_SCU_GPR0_OFFSET 0x002c /* General Purpose Register 0 */ #define XMC4_SCU_GPR1_OFFSET 0x0030 /* General Purpose Register 1 */ #define XMC4_SCU_ETH0CON_OFFSET 0x0040 /* Ethernet 0 Port Control */ +#define XMC4_SCU_ECAT0CON_OFFSET 0x01b0 /* EtherCAT 0 Common Port Control */ +#define XMC4_SCU_ECAT0CONP0_OFFSET 0x01b4 /* EtherCAT 0 Port 0 Control */ +#define XMC4_SCU_ECAT0CONP1_OFFSET 0x01b8 /* EtherCAT 0 Port 1 Control */ #define XMC4_SCU_CCUCON_OFFSET 0x004c /* CCUx Global Start Control Register */ #define XMC4_SCU_DTSCON_OFFSET 0x008c /* DTS Control */ #define XMC4_SCU_DTSSTAT_OFFSET 0x0090 /* DTS Status */ @@ -164,6 +167,7 @@ #define XMC4_SCU_EXTCLKCR_OFFSET 0x0028 /* External clock Control Register */ #define XMC4_SCU_SLEEPCR_OFFSET 0x0030 /* Sleep Control Register */ #define XMC4_SCU_DSLEEPCR_OFFSET 0x0034 /* Deep Sleep Control Register */ +#define XMC4_SCU_ECATCLKCR_OFFSET 0x0038 /* EtherCat Control Register */ #ifdef XMC4_SCU_GATING # define XMC4_SCU_CGATSTAT0_OFFSET 0x0040 /* Peripheral 0 Clock Gating Status */ # define XMC4_SCU_CGATSET0_OFFSET 0x0044 /* Peripheral 0 Clock Gating Set */ @@ -206,6 +210,9 @@ #define XMC4_SCU_GPR0 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_GPR0_OFFSET) #define XMC4_SCU_GPR1 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_GPR1_OFFSET) #define XMC4_SCU_ETH0CON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ETH0CON_OFFSET) +#define XMC4_SCU_ECAT0CON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ECAT0CON_OFFSET) +#define XMC4_SCU_ECAT0CONP0 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ECAT0CONP0_OFFSET) +#define XMC4_SCU_ECAT0CONP1 (XMC4_SCU_GENERAL_BASE+XMC4_SCU_ECAT0CONP1_OFFSET) #define XMC4_SCU_CCUCON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_CCUCON_OFFSET) #define XMC4_SCU_DTSCON (XMC4_SCU_GENERAL_BASE+XMC4_SCU_DTSCON_OFFSET) #define XMC4_SCU_DTSSTAT (XMC4_SCU_GENERAL_BASE+XMC4_SCU_DTSSTAT_OFFSET) @@ -296,6 +303,7 @@ #define XMC4_SCU_EXTCLKCR (XMC4_SCU_CLK_BASE+XMC4_SCU_EXTCLKCR_OFFSET) #define XMC4_SCU_SLEEPCR (XMC4_SCU_CLK_BASE+XMC4_SCU_SLEEPCR_OFFSET) #define XMC4_SCU_DSLEEPCR (XMC4_SCU_CLK_BASE+XMC4_SCU_DSLEEPCR_OFFSET) +#define XMC4_SCU_ECATCLKCR (XMC4_SCU_CLK_BASE+ XMC4_SCU_ECATCLKCR_OFFSET) #ifdef XMC4_SCU_GATING # define XMC4_SCU_CGATSTAT0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSTAT0_OFFSET) # define XMC4_SCU_CGATSET0 (XMC4_SCU_CLK_BASE+XMC4_SCU_CGATSET0_OFFSET) @@ -336,7 +344,7 @@ #define SCU_ID_MOD_REV_SHIFT (0) /* Bits 0-7: Module Revision Number */ #define SCU_ID_MOD_REV_MASK (0xff << SCU_ID_MOD_REV_SHIFT) #define SCU_ID_MOD_TYPE_SHIFT (8) /* Bits 8-15: Module Type */ -#define SCU_ID_MOD_TYPE_MASK (0xff << SCU_ID_MOD_REV_SHIFT) +#define SCU_ID_MOD_TYPE_MASK (0xff << SCU_ID_MOD_TYPE_SHIFT) #define SCU_ID_MOD_NUMBER_SHIFT (16) /* Bits 16-31: Module Number Value */ #define SCU_ID_MOD_NUMBER_MASK (0xffff << SCU_ID_MOD_NUMBER_SHIFT) @@ -345,9 +353,9 @@ /* Manufactory ID */ #define SCU_IDMANUF_DEPT_SHIFT (0) /* Bits 0-4: Department Identification Number */ -#define SCU_IDMANUF_DEPT_MASK (31 << SCU_IDMANUF_MOD_DEPT_SHIFT) +#define SCU_IDMANUF_DEPT_MASK (31 << SCU_IDMANUF_DEPT_SHIFT) #define SCU_IDMANUF_MANUF_SHIFT (5) /* Bits 5-15: Manufacturer Identification Number */ -#define SCU_IDMANUF_MANUF_MASK (0x7ff << SCU_IDMANUF_MOD_MANUF_SHIFT) +#define SCU_IDMANUF_MANUF_MASK (0x7ff << SCU_IDMANUF_MANUF_SHIFT) /* Start-up Control */ @@ -360,7 +368,7 @@ #define SCU_STCON_SWCON_SHIFT (8) /* Bits 8-11: SW Configuration */ #define SCU_STCON_SWCON_MASK (15 << SCU_STCON_SWCON_SHIFT) -# define SCU_STCON_SWCON_ ROM (0 << SCU_STCON_SWCON_SHIFT) /* Normal boot from Boot ROM */ +# define SCU_STCON_SWCON_ROM (0 << SCU_STCON_SWCON_SHIFT) /* Normal boot from Boot ROM */ # define SCU_STCON_SWCON_ASCBSL (1 << SCU_STCON_SWCON_SHIFT) /* ASC BSL enabled */ # define SCU_STCON_SWCON_BMI (2 << SCU_STCON_SWCON_SHIFT) /* BMI customized boot enabled */ # define SCU_STCON_SWCON_CANBSL (3 << SCU_STCON_SWCON_SHIFT) /* CAN BSL enabled */ @@ -454,6 +462,122 @@ # define SCU_ETH0CON_INFSEL_MII (0) /* 0=MII */ # define SCU_ETH0CON_INFSEL_RMII (1 << 26) /* 1=RMII */ +/* EtherCAT 0 Port Control */ + +/* Common */ +#define SCU_ECAT0CON_MDIO_SHIFT (22) +#define SCU_ECAT0CON_MDIOA (0 << SCU_ECAT0CON_MDIO_SHIFT) +#define SCU_ECAT0CON_MDIOB (1 << SCU_ECAT0CON_MDIO_SHIFT) +#define SCU_ECAT0CON_MDIOC (2 << SCU_ECAT0CON_MDIO_SHIFT) +#define SCU_ECAT0CON_MDIOD (3 << SCU_ECAT0CON_MDIO_SHIFT) + +#define SCU_ECAT0CON_PHY_OFFSET_SHIFT (16) +#define SCU_ECAT0CON_PHY_OFFSET (1 << SCU_ECAT0CON_PHY_OFFSET_SHIFT) + +#define SCU_ECAT0CON_ECATRSTEN_SHIFT (0) +#define SCU_ECAT0CON_ECATRSTEN (0 << SCU_ECAT0CON_ECATRSTEN_SHIFT) + +/* Port 0 */ +#define SCU_ECAT0CON_RXD0_SHIFT (0) +#define SCU_ECAT0CON_PORT0_RXD0A (0 << SCU_ECAT0CON_RXD0_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD0B (1 << SCU_ECAT0CON_RXD0_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD0C (2 << SCU_ECAT0CON_RXD0_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD0D (3 << SCU_ECAT0CON_RXD0_SHIFT) + +#define SCU_ECAT0CON_RXD1_SHIFT (2) +#define SCU_ECAT0CON_PORT0_RXD1A (0 << SCU_ECAT0CON_RXD1_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD1B (1 << SCU_ECAT0CON_RXD1_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD1C (2 << SCU_ECAT0CON_RXD1_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD1D (3 << SCU_ECAT0CON_RXD1_SHIFT) + +#define SCU_ECAT0CON_RXD2_SHIFT (4) +#define SCU_ECAT0CON_PORT0_RXD2A (0 << SCU_ECAT0CON_RXD2_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD2B (1 << SCU_ECAT0CON_RXD2_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD2C (2 << SCU_ECAT0CON_RXD2_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD2D (3 << SCU_ECAT0CON_RXD2_SHIFT) + +#define SCU_ECAT0CON_RXD3_SHIFT (6) +#define SCU_ECAT0CON_PORT0_RXD3A (0 << SCU_ECAT0CON_RXD3_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD3B (1 << SCU_ECAT0CON_RXD3_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD3C (2 << SCU_ECAT0CON_RXD3_SHIFT) +#define SCU_ECAT0CON_PORT0_RXD3D (3 << SCU_ECAT0CON_RXD3_SHIFT) + +#define SCU_ECAT0CON_RX_ERR_SHIFT (8) +#define SCU_ECAT0CON_PORT0_RX_ERRA (0 << SCU_ECAT0CON_RX_ERR_SHIFT) +#define SCU_ECAT0CON_PORT0_RX_ERRB (1 << SCU_ECAT0CON_RX_ERR_SHIFT) +#define SCU_ECAT0CON_PORT0_RX_ERRC (2 << SCU_ECAT0CON_RX_ERR_SHIFT) +#define SCU_ECAT0CON_PORT0_RX_ERRD (3 << SCU_ECAT0CON_RX_ERR_SHIFT) + +#define SCU_ECAT0CON_RX_DV_SHIFT (10) +#define SCU_ECAT0CON_PORT0_RX_DVA (0 << SCU_ECAT0CON_RX_DV_SHIFT) +#define SCU_ECAT0CON_PORT0_RX_DVB (1 << SCU_ECAT0CON_RX_DV_SHIFT) +#define SCU_ECAT0CON_PORT0_RX_DVC (2 << SCU_ECAT0CON_RX_DV_SHIFT) +#define SCU_ECAT0CON_PORT0_RX_DVD (3 << SCU_ECAT0CON_RX_DV_SHIFT) + +#define SCU_ECAT0CON_RX_CLK_SHIFT (12) +#define SCU_ECAT0CON_PORT0_RX_CLKA (0 << SCU_ECAT0CON_RX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT0_RX_CLKB (1 << SCU_ECAT0CON_RX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT0_RX_CLKC (2 << SCU_ECAT0CON_RX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT0_RX_CLKD (3 << SCU_ECAT0CON_RX_CLK_SHIFT) + +#define SCU_ECAT0CON_LINK_SHIFT (16) +#define SCU_ECAT0CON_PORT0_LINKA (0 << SCU_ECAT0CON_LINK_SHIFT) +#define SCU_ECAT0CON_PORT0_LINKB (1 << SCU_ECAT0CON_LINK_SHIFT) +#define SCU_ECAT0CON_PORT0_LINKC (2 << SCU_ECAT0CON_LINK_SHIFT) +#define SCU_ECAT0CON_PORT0_LINKD (3 << SCU_ECAT0CON_LINK_SHIFT) + +#define SCU_ECAT0CON_TX_CLK_SHIFT (28) +#define SCU_ECAT0CON_PORT0_TX_CLKA (0 << SCU_ECAT0CON_TX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT0_TX_CLKB (1 << SCU_ECAT0CON_TX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT0_TX_CLKC (2 << SCU_ECAT0CON_TX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT0_TX_CLKD (3 << SCU_ECAT0CON_TX_CLK_SHIFT) + +/* Port 1 */ +#define SCU_ECAT0CON_PORT1_RXD0A (0 << SCU_ECAT0CON_RXD0_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD0B (1 << SCU_ECAT0CON_RXD0_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD0C (2 << SCU_ECAT0CON_RXD0_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD0D (3 << SCU_ECAT0CON_RXD0_SHIFT) + +#define SCU_ECAT0CON_PORT1_RXD1A (0 << SCU_ECAT0CON_RXD1_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD1B (1 << SCU_ECAT0CON_RXD1_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD1C (2 << SCU_ECAT0CON_RXD1_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD1D (3 << SCU_ECAT0CON_RXD1_SHIFT) + +#define SCU_ECAT0CON_PORT1_RXD2A (0 << SCU_ECAT0CON_RXD2_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD2B (1 << SCU_ECAT0CON_RXD2_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD2C (2 << SCU_ECAT0CON_RXD2_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD2D (3 << SCU_ECAT0CON_RXD2_SHIFT) + +#define SCU_ECAT0CON_PORT1_RXD3A (0 << SCU_ECAT0CON_RXD3_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD3B (1 << SCU_ECAT0CON_RXD3_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD3C (2 << SCU_ECAT0CON_RXD3_SHIFT) +#define SCU_ECAT0CON_PORT1_RXD3D (3 << SCU_ECAT0CON_RXD3_SHIFT) + +#define SCU_ECAT0CON_PORT1_RX_ERRA (0 << SCU_ECAT0CON_RX_ERR_SHIFT) +#define SCU_ECAT0CON_PORT1_RX_ERRB (1 << SCU_ECAT0CON_RX_ERR_SHIFT) +#define SCU_ECAT0CON_PORT1_RX_ERRC (2 << SCU_ECAT0CON_RX_ERR_SHIFT) +#define SCU_ECAT0CON_PORT1_RX_ERRD (3 << SCU_ECAT0CON_RX_ERR_SHIFT) + +#define SCU_ECAT0CON_PORT1_RX_DVA (0 << SCU_ECAT0CON_RX_DV_SHIFT) +#define SCU_ECAT0CON_PORT1_RX_DVB (1 << SCU_ECAT0CON_RX_DV_SHIFT) +#define SCU_ECAT0CON_PORT1_RX_DVC (2 << SCU_ECAT0CON_RX_DV_SHIFT) +#define SCU_ECAT0CON_PORT1_RX_DVD (3 << SCU_ECAT0CON_RX_DV_SHIFT) + +#define SCU_ECAT0CON_PORT1_RX_CLKA (0 << SCU_ECAT0CON_RX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT1_RX_CLKB (1 << SCU_ECAT0CON_RX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT1_RX_CLKC (2 << SCU_ECAT0CON_RX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT1_RX_CLKD (3 << SCU_ECAT0CON_RX_CLK_SHIFT) + +#define SCU_ECAT0CON_PORT1_LINKA (0 << SCU_ECAT0CON_LINK_SHIFT) +#define SCU_ECAT0CON_PORT1_LINKB (1 << SCU_ECAT0CON_LINK_SHIFT) +#define SCU_ECAT0CON_PORT1_LINKC (2 << SCU_ECAT0CON_LINK_SHIFT) +#define SCU_ECAT0CON_PORT1_LINKD (3 << SCU_ECAT0CON_LINK_SHIFT) + +#define SCU_ECAT0CON_PORT1_TX_CLKA (0 << SCU_ECAT0CON_TX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT1_TX_CLKB (1 << SCU_ECAT0CON_TX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT1_TX_CLKC (2 << SCU_ECAT0CON_TX_CLK_SHIFT) +#define SCU_ECAT0CON_PORT1_TX_CLKD (3 << SCU_ECAT0CON_TX_CLK_SHIFT) + /* CCUx Global Start Control Register */ #define SCU_CCUCON_GSC40 (1 << 0) /* Bit 0: Global Start Control CCU40 */ @@ -871,6 +995,7 @@ #define SCU_PR2_DMA1RS (1 << 5) /* Bit 5: DMA1 Reset */ #define SCU_PR2_FCERS (1 << 6) /* Bit 6: FCE Reset */ #define SCU_PR2_USBRS (1 << 7) /* Bit 7: USB Reset */ +#define SCU_PR2_ECAT0RS (1 << 10) /* Bit 10: ECAT0 Reset */ /* Peripheral Reset Status Register 3, Peripheral Reset Set Register 3, * Peripheral Reset Clear Register 3 diff --git a/arch/arm/src/xmc4/xmc4_ccu4.c b/arch/arm/src/xmc4/xmc4_ccu4.c new file mode 100644 index 0000000000000..8d8519d099443 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_ccu4.c @@ -0,0 +1,195 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_ccu4.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * XMC CCU Driver + * + * For now, this file contains only helper methods mandatory for xmc tickless + * feature. Contibutions are welcomed. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "hardware/xmc4_ccu4.h" +#include "xmc4_ccu4.h" + +#define CCU4_NDIVIDERS 15 + +static const uint8_t g_log2divider[CCU4_NDIVIDERS] = +{ + 1, /* TIMER_CLOCK1 -> div2 */ + 2, /* TIMER_CLOCK1 -> div4 */ + 3, /* TIMER_CLOCK2 -> div8 */ + 4, /* TIMER_CLOCK2 -> div16 */ + 5, /* TIMER_CLOCK3 -> div32 */ + 6, /* TIMER_CLOCK3 -> div64 */ + 7, /* TIMER_CLOCK4 -> div128 */ + 8, /* TIMER_CLOCK4 -> div256 */ + 9, /* TIMER_CLOCK4 -> div512 */ + 10, /* TIMER_CLOCK4 -> div1024 */ + 11, /* TIMER_CLOCK4 -> div2048 */ + 12, /* TIMER_CLOCK4 -> div4096 */ + 13, /* TIMER_CLOCK4 -> div8192 */ + 14, /* TIMER_CLOCK4 -> div16384 */ + 15 /* TIMER_CLOCK4 -> div32769 */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_ccu4_divfreq_lookup + * + * Description: + * Given the TC input frequency (Ftcin) and a divider index, return the + * value of the divided frequency + * + * Input Parameters: + * ftcin - TC input frequency + * ndx - Divider index + * + * Returned Value: + * The divided frequency value + * + ****************************************************************************/ + +static uint32_t xmc4_ccu4_divfreq_lookup(uint32_t ftcin, int ndx) +{ + return ftcin >> g_log2divider[ndx]; +} + +/**************************************************************************** + * Name: xmc4_ccu4_freqdiv_lookup + * + * Description: + * Given the TC input frequency (Ftcin) and a divider index, return the + * value of the Ftcin divider. + * + * Input Parameters: + * ftcin - TC input frequency + * ndx - Divider index + * + * Returned Value: + * The Ftcin input divider value + * + ****************************************************************************/ + +static int xmc4_ccu4_freqdiv_lookup(uint32_t ftcin, int ndx) +{ + return 1 << g_log2divider[ndx]; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_ccu4_divisor + * + * Description: + * Finds the best MCK divisor given the timer frequency and MCK. The + * result is guaranteed to satisfy the following equation: + * + * (Ftcin / (div * 65536)) <= freq <= (Ftcin / dev) + * + * where: + * freq - the desired frequency + * Ftcin - The timer/counter input frequency + * div - With DIV being the highest possible value. + * + * Input Parameters: + * frequency Desired timer frequency. + * div Divisor value. + * pssiv PSSIV field value for divisor. + * + * Returned Value: + * Zero (OK) if a proper divisor has been found, otherwise a negated errno + * value indicating the nature of the failure. + * + ****************************************************************************/ + +int xmc4_ccu4_divisor(uint32_t frequency, uint32_t *div, uint32_t *pssiv) +{ + uint32_t ftcin = BOARD_CCU_FREQUENCY; + int ndx = 0; + + tmrinfo("frequency=%" PRIu32 "\n", frequency); + + /* Satisfy lower bound. That is, the value of the divider such that: + * + * frequency >= (tc_input_frequency * 65536) / divider. + */ + + while (frequency < (xmc4_ccu4_divfreq_lookup(ftcin, ndx) >> 16)) + { + if (++ndx > CCU4_NDIVIDERS) + { + /* If no divisor can be found, return -ERANGE */ + + tmrerr("ERROR: Lower bound search failed\n"); + return -ERANGE; + } + } + + /* Try to maximize DIV while still satisfying upper bound. That the + * value of the divider such that: + * + * frequency < tc_input_frequency / divider. + */ + + for (; ndx < (CCU4_NDIVIDERS - 1); ndx++) + { + if (frequency > xmc4_ccu4_divfreq_lookup(ftcin, ndx + 1)) + { + break; + } + } + + /* Return the divider value */ + + if (div) + { + uint32_t value = xmc4_ccu4_freqdiv_lookup(ftcin, ndx); + tmrinfo("return div=%lu\n", (unsigned long)value); + *div = value; + } + + /* Return the PSSIV selection */ + + if (pssiv) + { + tmrinfo("return pssiv=%d\n", ndx + 1); + *pssiv = ndx + 1; + } + + return OK; +} diff --git a/arch/arm/src/xmc4/xmc4_ccu4.h b/arch/arm/src/xmc4/xmc4_ccu4.h new file mode 100644 index 0000000000000..c334d020b348c --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_ccu4.h @@ -0,0 +1,64 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_ccu4.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_CCU4_H +#define __ARCH_ARM_SRC_XMC4_XMC4_CCU4_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_ccu4_divisor + * + * Description: + * Finds the best MCK divisor given the timer frequency and MCK. The + * result is guaranteed to satisfy the following equation: + * + * (Ftcin / (div * 65536)) <= freq <= (Ftcin / dev) + * + * where: + * freq - the desired frequency + * Ftcin - The timer/counter input frequency + * div - With DIV being the highest possible value. + * + * Input Parameters: + * frequency Desired timer frequency. + * div Divisor value. + * pssiv PSSIV field value for divisor. + * + * Returned Value: + * Zero (OK) if a proper divisor has been found, otherwise a negated errno + * value indicating the nature of the failure. + * + ****************************************************************************/ + +int xmc4_ccu4_divisor(uint32_t frequency, uint32_t *div, uint32_t *pssiv); + +#endif diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c index 1f95fa44e5e0f..78924a619af08 100644 --- a/arch/arm/src/xmc4/xmc4_clockconfig.c +++ b/arch/arm/src/xmc4/xmc4_clockconfig.c @@ -483,7 +483,7 @@ void xmc4_clock_configure(void) regval = getreg32(XMC4_SCU_USBPLLCON); regval &= ~(SCU_USBPLLCON_VCOPWD | SCU_USBPLLCON_PLLPWD); - getreg32(regval, XMC4_SCU_USBPLLCON); + putreg32(regval, XMC4_SCU_USBPLLCON); /* USB PLL uses as clock input the OSC_HP */ diff --git a/arch/arm/src/xmc4/xmc4_ecat.c b/arch/arm/src/xmc4/xmc4_ecat.c new file mode 100644 index 0000000000000..821852d550c0f --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_ecat.c @@ -0,0 +1,707 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_ecat.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "xmc4_ecat.h" + +#include +#include + +#include "arm_internal.h" +#include "hardware/xmc4_pinmux.h" +#include "hardware/xmc4_scu.h" +#include "debug.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void xmc4_ecat_initialize() +{ +#ifdef CONFIG_XMC4_ECAT_P0 + /* Init inputs */ + + xmc4_gpio_config(ECAT_P0_LINK_STATUS); + xmc4_gpio_config(ECAT_P0_RXD3); + xmc4_gpio_config(ECAT_P0_RXD2); + xmc4_gpio_config(ECAT_P0_RXD1); + xmc4_gpio_config(ECAT_P0_RXD0); + xmc4_gpio_config(ECAT_P0_RX_DV); + xmc4_gpio_config(ECAT_P0_RX_CLK); + xmc4_gpio_config(ECAT_P0_RX_ERR); + xmc4_gpio_config(ECAT_P0_TX_CLK); + + /* Init outputs */ + + xmc4_gpio_config(ECAT_P0_LED_LINK_ACT); + xmc4_gpio_config(ECAT_P0_TXD3); + xmc4_gpio_config(ECAT_P0_TXD2); + xmc4_gpio_config(ECAT_P0_TXD1); + xmc4_gpio_config(ECAT_P0_TXD0); + xmc4_gpio_config(ECAT_P0_TX_EN); +#endif + +#ifdef CONFIG_XMC4_ECAT_P1 + /* Init inputs */ + + xmc4_gpio_config(ECAT_P1_LINK_STATUS); + xmc4_gpio_config(ECAT_P1_RXD3); + xmc4_gpio_config(ECAT_P1_RXD2); + xmc4_gpio_config(ECAT_P1_RXD1); + xmc4_gpio_config(ECAT_P1_RXD0); + xmc4_gpio_config(ECAT_P1_RX_DV); + xmc4_gpio_config(ECAT_P1_RX_CLK); + xmc4_gpio_config(ECAT_P1_RX_ERR); + xmc4_gpio_config(ECAT_P1_TX_CLK); + + /* Init outputs */ + + xmc4_gpio_config(ECAT_P1_LED_LINK_ACT); + xmc4_gpio_config(ECAT_P1_TXD3); + xmc4_gpio_config(ECAT_P1_TXD2); + xmc4_gpio_config(ECAT_P1_TXD1); + xmc4_gpio_config(ECAT_P1_TXD0); + xmc4_gpio_config(ECAT_P1_TX_EN); +#endif + + xmc4_gpio_config(ECAT_MDO); + xmc4_gpio_config(ECAT_CLK_25); + xmc4_gpio_config(ECAT_LED_ERR); + xmc4_gpio_config(ECAT_LED_RUN); + xmc4_gpio_config(ECAT_MCLK); + xmc4_gpio_config(ECAT_PHY_RESET); + + /* configure PLL */ + + #define SCU_ECATCLKCR_PLL ((0 << 16) | (1 << 0)) + putreg32(SCU_ECATCLKCR_PLL, XMC4_SCU_ECATCLKCR); + + /* ECAT reset */ + + putreg32(SCU_PR2_ECAT0RS, XMC4_SCU_PRSET2); + while (!(getreg32(XMC4_SCU_PRSTAT2) & SCU_PR2_ECAT0RS)) /* is ecat reset */ + { + }; + + /* Gate peripheral clock */ + + putreg32(SCU_CGAT2_ECAT, XMC4_SCU_CGATSET2); + + /* init port control MII */ + + xmc4_ecat_initialize_port_control(); + + /* ECAT init, Ungate peripheral */ + + putreg32(SCU_CGAT2_ECAT, XMC4_SCU_CGATCLR2); + + /* Deassert reset */ + + putreg32(SCU_PR2_ECAT0RS, XMC4_SCU_PRCLR2); + while ((getreg32(XMC4_SCU_PRSTAT2) & SCU_PR2_ECAT0RS)) /* is ecat reset */ + { + }; +} + +void xmc4_ecat_initialize_port_control() +{ + /* common */ + + uint32_t mdio_conf = 0; + switch (ECAT_MDO & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT0 | GPIO_PIN12: + { + mdio_conf = SCU_ECAT0CON_MDIOA; + break; + } + + case GPIO_PORT4 | GPIO_PIN2: + { + mdio_conf = SCU_ECAT0CON_MDIOB; + break; + } + + case GPIO_PORT9 | GPIO_PIN7: + { + mdio_conf = SCU_ECAT0CON_MDIOC; + break; + } + + default: + { + nerr("Unknown mdio config \n"); + } + } + + uint32_t ecat0_con_conf = 0; + ecat0_con_conf |= SCU_ECAT0CON_PHY_OFFSET; + ecat0_con_conf |= SCU_ECAT0CON_ECATRSTEN; + ecat0_con_conf |= mdio_conf; + + /* port0 */ + + uint32_t port0_rxd0_conf = 0; + switch (ECAT_P0_RXD0 & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT1 | GPIO_PIN4: + { + port0_rxd0_conf = SCU_ECAT0CON_PORT0_RXD0A; + break; + } + + case GPIO_PORT5 | GPIO_PIN0: + { + port0_rxd0_conf = SCU_ECAT0CON_PORT0_RXD0B; + break; + } + + case GPIO_PORT7 | GPIO_PIN4: + { + port0_rxd0_conf = SCU_ECAT0CON_PORT0_RXD0C; + break; + } + + default: + { + nerr("Unknown port0_rxd0 config \n"); + } + } + + uint32_t port0_rxd1_conf = 0; + switch (ECAT_P0_RXD1 & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT1 | GPIO_PIN5: + { + port0_rxd1_conf = SCU_ECAT0CON_PORT0_RXD1A; + break; + } + + case GPIO_PORT5 | GPIO_PIN1: + { + port0_rxd1_conf = SCU_ECAT0CON_PORT0_RXD1B; + break; + } + + case GPIO_PORT7 | GPIO_PIN5: + { + port0_rxd1_conf = SCU_ECAT0CON_PORT0_RXD1C; + break; + } + + default: + { + nerr("Unknown port0_rxd1 config \n"); + } + } + + uint32_t port0_rxd2_conf = 0; + switch (ECAT_P0_RXD2 & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT1 | GPIO_PIN10: + { + port0_rxd2_conf = SCU_ECAT0CON_PORT0_RXD2A; + break; + } + + case GPIO_PORT5 | GPIO_PIN2: + { + port0_rxd2_conf = SCU_ECAT0CON_PORT0_RXD2B; + break; + } + + case GPIO_PORT7 | GPIO_PIN6: + { + port0_rxd2_conf = SCU_ECAT0CON_PORT0_RXD2C; + break; + } + + default: + { + nerr("Unknown port0_rxd2 config \n"); + } + } + + uint32_t port0_rxd3_conf = 0; + switch (ECAT_P0_RXD3 & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT1 | GPIO_PIN11: + { + port0_rxd3_conf = SCU_ECAT0CON_PORT0_RXD3A; + break; + } + + case GPIO_PORT5 | GPIO_PIN7: + { + port0_rxd3_conf = SCU_ECAT0CON_PORT0_RXD3B; + break; + } + + case GPIO_PORT7 | GPIO_PIN7: + { + port0_rxd3_conf = SCU_ECAT0CON_PORT0_RXD3C; + break; + } + + default: + { + nerr("Unknown port0_rxd2 config \n"); + } + } + + uint32_t port0_rx_clk_conf = 0; + switch (ECAT_P0_RX_CLK & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT1 | GPIO_PIN1: + { + port0_rx_clk_conf = SCU_ECAT0CON_PORT0_RX_CLKA; + break; + } + + case GPIO_PORT5 | GPIO_PIN4: + { + port0_rx_clk_conf = SCU_ECAT0CON_PORT0_RX_CLKB; + break; + } + + case GPIO_PORT7 | GPIO_PIN10: + { + port0_rx_clk_conf = SCU_ECAT0CON_PORT0_RX_CLKC; + break; + } + + default: + { + nerr("Unknown port0_rx_clk config \n"); + } + } + + uint32_t port0_rx_dv_conf = 0; + switch (ECAT_P0_RX_DV & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT1 | GPIO_PIN9: + { + port0_rx_dv_conf = SCU_ECAT0CON_PORT0_RX_DVA; + break; + } + + case GPIO_PORT5 | GPIO_PIN6: + { + port0_rx_dv_conf = SCU_ECAT0CON_PORT0_RX_DVB; + break; + } + + case GPIO_PORT7 | GPIO_PIN11: + { + port0_rx_dv_conf = SCU_ECAT0CON_PORT0_RX_DVC; + break; + } + + default: + { + nerr("Unknown port0_rx_dv config \n"); + } + } + + uint32_t port0_rx_err_conf = 0; + switch (ECAT_P0_RX_ERR & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT4 | GPIO_PIN0: + { + port0_rx_err_conf = SCU_ECAT0CON_PORT0_RX_ERRA; + break; + } + + case GPIO_PORT2 | GPIO_PIN6: + { + port0_rx_err_conf = SCU_ECAT0CON_PORT0_RX_ERRB; + break; + } + + case GPIO_PORT7 | GPIO_PIN9: + { + port0_rx_err_conf = SCU_ECAT0CON_PORT0_RX_ERRC; + break; + } + + default: + { + nerr("Unknown port0_rx_err config \n"); + } + } + + uint32_t port0_link_conf = 0; + switch (ECAT_P0_LINK_STATUS & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT4 | GPIO_PIN1: + { + port0_link_conf = SCU_ECAT0CON_PORT0_LINKA; + break; + } + + case GPIO_PORT1 | GPIO_PIN15: + { + port0_link_conf = SCU_ECAT0CON_PORT0_LINKB; + break; + } + + case GPIO_PORT9 | GPIO_PIN10: + { + port0_link_conf = SCU_ECAT0CON_PORT0_LINKC; + break; + } + + default: + { + nerr("Unknown port0_link config \n"); + } + } + + uint32_t port0_tx_clk_conf = 0; + switch (ECAT_P0_TX_CLK & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT1 | GPIO_PIN0: + { + port0_tx_clk_conf = SCU_ECAT0CON_PORT0_TX_CLKA; + break; + } + + case GPIO_PORT5 | GPIO_PIN5: + { + port0_tx_clk_conf = SCU_ECAT0CON_PORT0_TX_CLKB; + break; + } + + case GPIO_PORT9 | GPIO_PIN1: + { + port0_tx_clk_conf = SCU_ECAT0CON_PORT0_TX_CLKC; + break; + } + + default: + { + nerr("Unknown port0_tx_clk config \n"); + } + } + + uint32_t ecat0_port0_conf = 0; +#ifndef CONFIG_XMC4_ECAT_P0 + /* When port 0 is not available, the unused MII need to be tied + * to not connected pins. + */ + + port0_rxd0_conf = SCU_ECAT0CON_PORT0_RXD0D; + port0_rxd1_conf = SCU_ECAT0CON_PORT0_RXD1D; + port0_rxd2_conf = SCU_ECAT0CON_PORT0_RXD2D; + port0_rxd3_conf = SCU_ECAT0CON_PORT0_RXD3D; + port0_rx_clk_conf = SCU_ECAT0CON_PORT0_RX_CLKD; + port0_rx_dv_conf = SCU_ECAT0CON_PORT0_RX_DVD; + port0_rx_err_conf = SCU_ECAT0CON_PORT0_RX_ERRD; + port0_link_conf = SCU_ECAT0CON_PORT0_LINKB; + port0_tx_clk_conf = SCU_ECAT0CON_PORT0_TX_CLKD; +#endif + ecat0_port0_conf |= port0_rxd0_conf; + ecat0_port0_conf |= port0_rxd1_conf; + ecat0_port0_conf |= port0_rxd2_conf; + ecat0_port0_conf |= port0_rxd3_conf; + ecat0_port0_conf |= port0_rx_clk_conf; + ecat0_port0_conf |= port0_rx_dv_conf; + ecat0_port0_conf |= port0_rx_err_conf; + ecat0_port0_conf |= port0_link_conf; + ecat0_port0_conf |= port0_tx_clk_conf; + + putreg32(ecat0_port0_conf, XMC4_SCU_ECAT0CONP0); + + /* port 1 */ + + uint32_t port1_rxd0_conf = 0; + switch (ECAT_P1_RXD0 & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT0 | GPIO_PIN11: + { + port1_rxd0_conf = SCU_ECAT0CON_PORT1_RXD0A; + break; + } + + case GPIO_PORT14 | GPIO_PIN7: + { + port1_rxd0_conf = SCU_ECAT0CON_PORT1_RXD0B; + break; + } + + case GPIO_PORT8 | GPIO_PIN4: + { + port1_rxd0_conf = SCU_ECAT0CON_PORT1_RXD0C; + break; + } + + default: + { + nerr("Unknown port1_rxd0 config \n"); + } + } + + uint32_t port1_rxd1_conf = 0; + switch (ECAT_P1_RXD1 & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT0 | GPIO_PIN6: + { + port1_rxd1_conf = SCU_ECAT0CON_PORT1_RXD1A; + break; + } + + case GPIO_PORT14 | GPIO_PIN12: + { + port1_rxd1_conf = SCU_ECAT0CON_PORT1_RXD1B; + break; + } + + case GPIO_PORT8 | GPIO_PIN5: + { + port1_rxd1_conf = SCU_ECAT0CON_PORT1_RXD1C; + break; + } + + default: + { + nerr("Unknown port1_rxd1 config \n"); + } + } + + uint32_t port1_rxd2_conf = 0; + switch (ECAT_P1_RXD2 & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT0 | GPIO_PIN5: + { + port1_rxd2_conf = SCU_ECAT0CON_PORT1_RXD2A; + break; + } + + case GPIO_PORT14 | GPIO_PIN13: + { + port1_rxd2_conf = SCU_ECAT0CON_PORT1_RXD2B; + break; + } + + case GPIO_PORT8 | GPIO_PIN6: + { + port1_rxd2_conf = SCU_ECAT0CON_PORT1_RXD2C; + break; + } + + default: + { + nerr("Unknown port1_rxd2 config \n"); + } + } + + uint32_t port1_rxd3_conf = 0; + switch (ECAT_P1_RXD3 & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT0 | GPIO_PIN4: + { + port1_rxd3_conf = SCU_ECAT0CON_PORT1_RXD3A; + break; + } + + case GPIO_PORT14 | GPIO_PIN14: + { + port1_rxd3_conf = SCU_ECAT0CON_PORT1_RXD3B; + break; + } + + case GPIO_PORT8 | GPIO_PIN7: + { + port1_rxd3_conf = SCU_ECAT0CON_PORT1_RXD3C; + break; + } + + default: + { + nerr("Unknown port1_rxd3 config \n"); + } + } + + uint32_t port1_rx_clk_conf = 0; + switch (ECAT_P1_RX_CLK & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT0 | GPIO_PIN1: + { + port1_rx_clk_conf = SCU_ECAT0CON_PORT1_RX_CLKA; + break; + } + + case GPIO_PORT14 | GPIO_PIN6: + { + port1_rx_clk_conf = SCU_ECAT0CON_PORT1_RX_CLKB; + break; + } + + case GPIO_PORT8 | GPIO_PIN10: + { + port1_rx_clk_conf = SCU_ECAT0CON_PORT1_RX_CLKC; + break; + } + + default: + { + nerr("Unknown port1_rx_clk config \n"); + } + } + + uint32_t port1_rx_dv_conf = 0; + switch (ECAT_P1_RX_DV & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT0 | GPIO_PIN9: + { + port1_rx_dv_conf = SCU_ECAT0CON_PORT1_RX_DVA; + break; + } + + case GPIO_PORT14 | GPIO_PIN15: + { + port1_rx_dv_conf = SCU_ECAT0CON_PORT1_RX_DVB; + break; + } + + case GPIO_PORT8 | GPIO_PIN11: + { + port1_rx_dv_conf = SCU_ECAT0CON_PORT1_RX_DVC; + break; + } + + default: + { + nerr("Unknown port1_rx_dv config \n"); + } + } + + uint32_t port1_link_conf = 0; + switch (ECAT_P1_LINK_STATUS & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT3 | GPIO_PIN4: + { + port1_link_conf = SCU_ECAT0CON_PORT1_LINKA; + break; + } + + case GPIO_PORT15 | GPIO_PIN3: + { + port1_link_conf = SCU_ECAT0CON_PORT1_LINKB; + break; + } + + case GPIO_PORT9 | GPIO_PIN11: + { + port1_link_conf = SCU_ECAT0CON_PORT1_LINKC; + break; + } + + default: + { + nerr("Unknown port1_link config \n"); + } + } + + uint32_t port1_tx_clk_conf = 0; + switch (ECAT_P1_TX_CLK & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT0 | GPIO_PIN10: + { + port1_tx_clk_conf = SCU_ECAT0CON_PORT1_TX_CLKA; + break; + } + + case GPIO_PORT5 | GPIO_PIN9: + { + port1_tx_clk_conf = SCU_ECAT0CON_PORT1_TX_CLKB; + break; + } + + case GPIO_PORT9 | GPIO_PIN0: + { + port1_tx_clk_conf = SCU_ECAT0CON_PORT1_TX_CLKC; + break; + } + + default: + { + nerr("Unknown port1_tx_clk config \n"); + } + } + + uint32_t port1_rx_err_conf = 0; + switch (ECAT_P1_RX_ERR & (GPIO_PORT_MASK | GPIO_PIN_MASK)) + { + case GPIO_PORT3 | GPIO_PIN5: + { + port1_rx_err_conf = SCU_ECAT0CON_PORT1_RX_ERRA; + break; + } + + case GPIO_PORT15 | GPIO_PIN2: + { + port1_rx_err_conf = SCU_ECAT0CON_PORT1_RX_ERRB; + break; + } + + case GPIO_PORT8 | GPIO_PIN9: + { + port1_rx_err_conf = SCU_ECAT0CON_PORT1_RX_ERRC; + break; + } + + default: + { + nerr("Unknown port1_rx_err config \n"); + } + } + + uint32_t ecat0_port1_conf = 0; +#ifndef CONFIG_XMC4_ECAT_P1 + /* When port 1 is not available, the unused MII need to be tied + * to not connected pins. + */ + + port1_rxd0_conf = SCU_ECAT0CON_PORT1_RXD0D; + port1_rxd1_conf = SCU_ECAT0CON_PORT1_RXD1D; + port1_rxd2_conf = SCU_ECAT0CON_PORT1_RXD2D; + port1_rxd3_conf = SCU_ECAT0CON_PORT1_RXD3D; + port1_rx_clk_conf = SCU_ECAT0CON_PORT1_RX_CLKD; + port1_rx_dv_conf = SCU_ECAT0CON_PORT1_RX_DVD; + port1_rx_err_conf = SCU_ECAT0CON_PORT1_RX_ERRD; + port1_link_conf = SCU_ECAT0CON_PORT1_LINKB; + port1_tx_clk_conf = SCU_ECAT0CON_PORT1_TX_CLKD; +#endif + ecat0_port1_conf |= port1_rxd0_conf; + ecat0_port1_conf |= port1_rxd1_conf; + ecat0_port1_conf |= port1_rxd2_conf; + ecat0_port1_conf |= port1_rxd3_conf; + ecat0_port1_conf |= port1_rx_clk_conf; + ecat0_port1_conf |= port1_rx_dv_conf; + ecat0_port1_conf |= port1_rx_err_conf; + ecat0_port1_conf |= port1_link_conf; + ecat0_port1_conf |= port1_tx_clk_conf; + + putreg32(ecat0_port1_conf, XMC4_SCU_ECAT0CONP1); +} diff --git a/arch/arm/src/xmc4/xmc4_ecat.h b/arch/arm/src/xmc4/xmc4_ecat.h new file mode 100644 index 0000000000000..27e0600e4fc7c --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_ecat.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_ecat.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_ecat_initialize + * + * Description: + * Initialize the EtherCAT module. Configure the pins, the PLL, the + * physical ports and run the start up sequence. + * See chapter "16.14 Initialization and System Dependencies" from + * Infineon-ReferenceManual_XMC4700_XMC4800-UM-v01_03-EN.pdf for + * references. + * + ****************************************************************************/ + +void xmc4_ecat_initialize(void); + +/**************************************************************************** + * Name: xmc4_ecat_initialize_port_control + * + * Description: + * Apply the proper physical port configuration based on the pin properties + * defined in board.h according to "26.10.1 Port I/O Function Table" from + * Infineon-ReferenceManual_XMC4700_XMC4800-UM-v01_03-EN.pdf. + * + ****************************************************************************/ + +void xmc4_ecat_initialize_port_control(void); diff --git a/arch/arm/src/xmc4/xmc4_flash.c b/arch/arm/src/xmc4/xmc4_flash.c new file mode 100644 index 0000000000000..1ad04789dbfba --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_flash.c @@ -0,0 +1,136 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_flash.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "xmc4_flash.h" + +#include "arm_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void xmc4_flash_reset_to_read(void) +{ + putreg32(0xf0, XMC4_UNCACHED_PFLASH_BASE + 0x5554); +} + +void xmc4_flash_enter_page_mode(void) +{ + putreg32(0x50, XMC4_UNCACHED_PFLASH_BASE + 0x5554); +} + +void xmc4_flash_load_page(uint32_t low_word, uint32_t high_word) +{ + putreg32(low_word, XMC4_UNCACHED_PFLASH_BASE + 0x55f0); + putreg32(high_word, XMC4_UNCACHED_PFLASH_BASE + 0x55f4); +} + +void xmc4_flash_write_page(uint32_t page_start_address) +{ + putreg32(0xaa, XMC4_UNCACHED_PFLASH_BASE + 0x5554); + putreg32(0x55, XMC4_UNCACHED_PFLASH_BASE + 0xaaa8); + putreg32(0xa0, XMC4_UNCACHED_PFLASH_BASE + 0x5554); + putreg32(0xaa, page_start_address); +} + +void xmc4_flash_write_user_config_page(uint32_t page_start_address) +{ + putreg32(0xaa, XMC4_UNCACHED_PFLASH_BASE + 0x5554); + putreg32(0x55, XMC4_UNCACHED_PFLASH_BASE + 0xaaa8); + putreg32(0xc0, XMC4_UNCACHED_PFLASH_BASE + 0x5554); + putreg32(0xaa, page_start_address); +} + +void xmc4_flash_erase_sector(uint32_t sector_start_address) +{ + putreg32(0xaa, XMC4_UNCACHED_PFLASH_BASE + 0x5554); + putreg32(0x55, XMC4_UNCACHED_PFLASH_BASE + 0xaaa8); + putreg32(0x80, XMC4_UNCACHED_PFLASH_BASE + 0x5554); + putreg32(0xaa, XMC4_UNCACHED_PFLASH_BASE + 0x5554); + putreg32(0x55, XMC4_UNCACHED_PFLASH_BASE + 0xaaa8); + putreg32(0x30, sector_start_address); +} + +void xmc4_flash_erase_physical_sector(uint32_t sector_start_address) +{ + putreg32(0xaa, XMC4_UNCACHED_PFLASH_BASE + 0x5554); + putreg32(0x55, XMC4_UNCACHED_PFLASH_BASE + 0xaaa8); + putreg32(0x80, XMC4_UNCACHED_PFLASH_BASE + 0x5554); + putreg32(0xaa, XMC4_UNCACHED_PFLASH_BASE + 0x5554); + putreg32(0x55, XMC4_UNCACHED_PFLASH_BASE + 0xaaa8); + putreg32(0x40, sector_start_address); +} + +void xmc4_flash_repair_physical_sector(uint32_t sector_start_address) +{ + putreg32(0xaa, XMC4_UNCACHED_PFLASH_BASE + 0x5554); + putreg32(0x55, XMC4_UNCACHED_PFLASH_BASE + 0xaaa8); + putreg32(0x80, XMC4_UNCACHED_PFLASH_BASE + 0x5554); + putreg32(0xaa, XMC4_UNCACHED_PFLASH_BASE + 0x5554); + putreg32(0x55, XMC4_UNCACHED_PFLASH_BASE + 0xaaa8); + putreg32(0x40, sector_start_address); +} + +void xmc4_flash_erase_user_config_block(uint32_t block_start_address) +{ + putreg32(0xaa, XMC4_UNCACHED_PFLASH_BASE + 0x5554); + putreg32(0x55, XMC4_UNCACHED_PFLASH_BASE + 0xaaa8); + putreg32(0x80, XMC4_UNCACHED_PFLASH_BASE + 0x5554); + putreg32(0xaa, XMC4_UNCACHED_PFLASH_BASE + 0x5554); + putreg32(0x55, XMC4_UNCACHED_PFLASH_BASE + 0xaaa8); + putreg32(0xc0, block_start_address); +} + +void xmc4_flash_disable_sector_write_protection(uint32_t user_level, + uint32_t password_0, + uint32_t password_1) +{ + putreg32(0xaa, XMC4_UNCACHED_PFLASH_BASE + 0x5554); + putreg32(0x55, XMC4_UNCACHED_PFLASH_BASE + 0xaaa8); + putreg32(user_level, XMC4_UNCACHED_PFLASH_BASE + 0x553c); + putreg32(password_0, XMC4_UNCACHED_PFLASH_BASE + 0xaaa8); + putreg32(password_1, XMC4_UNCACHED_PFLASH_BASE + 0xaaa8); + putreg32(0x05, XMC4_UNCACHED_PFLASH_BASE + 0x5558); +} + +void xmc4_flash_disable_sector_read_protection(uint32_t password_0, + uint32_t password_1) +{ + putreg32(0xaa, XMC4_UNCACHED_PFLASH_BASE + 0x5554); + putreg32(0x55, XMC4_UNCACHED_PFLASH_BASE + 0xaaa8); + putreg32(0x00, XMC4_UNCACHED_PFLASH_BASE + 0x553c); + putreg32(password_0, XMC4_UNCACHED_PFLASH_BASE + 0xaaa8); + putreg32(password_1, XMC4_UNCACHED_PFLASH_BASE + 0xaaa8); + putreg32(0x08, XMC4_UNCACHED_PFLASH_BASE + 0x5558); +} + +void xmc4_flash_resume_protection(void) +{ + putreg32(0x5e, XMC4_UNCACHED_PFLASH_BASE + 0x5554); +} + +void xmc4_flash_clear_status(void) +{ + putreg32(0xf5, XMC4_UNCACHED_PFLASH_BASE + 0x5554); +} diff --git a/arch/arm/src/xmc4/xmc4_flash.h b/arch/arm/src/xmc4/xmc4_flash.h new file mode 100644 index 0000000000000..19f4d27a11aaf --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_flash.h @@ -0,0 +1,166 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_flash.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_XMC4_XMC4_FLASH_H +#define __ARCH_ARM_SRC_XMC4_XMC4_FLASH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/xmc4_flash.h" + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/* Flash Command Sequences API */ + +/**************************************************************************** + * Name: xmc4_flash_reset_to_read + * + * Description: Reset command interpreter, abort page mode. + * Clear error flags of FSR. + ****************************************************************************/ + +void xmc4_flash_reset_to_read(void); + +/**************************************************************************** + * Name: xmc4_flash_enter_page_mode + * + * Description: PFLASH enters page mode. + ****************************************************************************/ + +void xmc4_flash_enter_page_mode(void); + +/**************************************************************************** + * Name: xmc4_flash_load_page + * + * Description: Fill the page assembly buffer. Addressed bank must be in + * page mode. In case of overflow, overflow data is discarded. + * 32 Load Page operations are required to fill the assembly + * buffer for one 256 byte page. + ****************************************************************************/ + +void xmc4_flash_load_page(uint32_t low_word, uint32_t high_word); + +/**************************************************************************** + * Name: xmc4_flash_write_page + * + * Description: Starts the programming process for one page with the data + * transferred previously by Load Page commands. + ****************************************************************************/ + +void xmc4_flash_write_page(uint32_t page_start_address); + +/**************************************************************************** + * Name: xmc4_flash_write_user_config_page + * + * Description: Starts the programming process for one page with the data + * transferred previously by Load Page commands. + ****************************************************************************/ + +void xmc4_flash_write_user_config_page(uint32_t page_start_address); + +/**************************************************************************** + * Name: xmc4_flash_erase_sector + * + * Description: Given sector is erased. + * + ****************************************************************************/ + +void xmc4_flash_erase_sector(uint32_t sector_start_address); + +/**************************************************************************** + * Name: xmc4_flash_erase_physical_sector + * + * Description: Given physical sector is erased. Depending on config of + * PROCON1.PSR it repairs the sector. + * + ****************************************************************************/ + +void xmc4_flash_erase_physical_sector(uint32_t sector_start_address); + +/**************************************************************************** + * Name: xmc4_flash_repair_physical_sector + * + * Description: Given physical sector is repaired. Depending on config of + * PROCON1.PSR it erases the sector. + * + ****************************************************************************/ + +void xmc4_flash_repair_physical_sector(uint32_t sector_start_address); + +/**************************************************************************** + * Name: xmc4_flash_erase_user_config_block + * + * Description: Given user configurable block is erased. + * + ****************************************************************************/ + +void xmc4_flash_erase_user_config_block(uint32_t block_start_address); + +/**************************************************************************** + * Name: xmc4_flash_disable_sector_write_protection + * + * Description: The sector write protection belonging to user level UL is + * temporarily disabled by setting FSR.WPRODIS when the passwords + * PW0 and PW1 match their configured values in the corresponding + * UCB + ****************************************************************************/ + +void xmc4_flash_disable_sector_write_protection(uint32_t user_level, + uint32_t password_0, + uint32_t password_1); + +/**************************************************************************** + * Name: xmc4_flash_disable_sector_read_protection + * + * Description: The Flash module read protection including the derived module + * wide write protection are temporarily disabled by setting + * FSR.RPRODIS when the passwords PW0 and PW1 match their + * configured values in the UCB0. + ****************************************************************************/ + +void xmc4_flash_disable_sector_read_protection(uint32_t password_0, + uint32_t password_1); + +/**************************************************************************** + * Name: xmc4_flash_resume_protection + * + * Description: This command clears all FSR.WPRODISx and the FSR.RPRODIS + * effectively enabling again the Flash protection as it was + * configured. + ****************************************************************************/ + +void xmc4_flash_resume_protection(void); + +/**************************************************************************** + * Name: xmc4_flash_clear_status + * + * Description: The flags FSR.PROG and FSR.ERASE and the error flags of FSR + * (PFOPER, SQER, PROER, PFDBER, ORIER, VER) are cleared. + ****************************************************************************/ + +void xmc4_flash_clear_status(void); + +#endif /* __ARCH_ARM_SRC_XMC4_XMC4_FLASH_H */ diff --git a/arch/arm/src/xmc4/xmc4_serial.c b/arch/arm/src/xmc4/xmc4_serial.c index d8a840bcfd33c..d5bef7c3ab6ae 100644 --- a/arch/arm/src/xmc4/xmc4_serial.c +++ b/arch/arm/src/xmc4/xmc4_serial.c @@ -551,14 +551,14 @@ static inline void xmc4_modifyreg(struct xmc4_dev_s *priv, unsigned uintptr_t regaddr = priv->uartbase + offset; uint32_t regval; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); regval = getreg32(regaddr); regval &= ~clrbits; regval |= setbits; putreg32(regval, regaddr); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -573,9 +573,9 @@ static void xmc4_setuartint(struct xmc4_dev_s *priv) * bits in priv->ccr. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); xmc4_modifyreg(priv, XMC4_USIC_CCR_OFFSET, CCR_ALL_EVENTS, priv->ccr); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -590,10 +590,10 @@ static void xmc4_restoreuartint(struct xmc4_dev_s *priv, uint32_t ccr) * in the ccr argument. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); priv->ccr = ccr; xmc4_setuartint(priv); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -604,14 +604,14 @@ static void xmc4_disableuartint(struct xmc4_dev_s *priv, uint32_t *ccr) { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (ccr) { *ccr = priv->ccr; } xmc4_restoreuartint(priv, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/arm/src/xmc4/xmc4_tickless.c b/arch/arm/src/xmc4/xmc4_tickless.c new file mode 100644 index 0000000000000..953c9a56c3ba5 --- /dev/null +++ b/arch/arm/src/xmc4/xmc4_tickless.c @@ -0,0 +1,574 @@ +/**************************************************************************** + * arch/arm/src/xmc4/xmc4_tickless.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Tickless OS Support. + * + * When CONFIG_SCHED_TICKLESS is enabled, all support for timer interrupts + * is suppressed and the platform specific code is expected to provide the + * following custom functions. + * + * void up_timer_initialize(void): Initializes the timer facilities. + * Called early in the initialization sequence (by up_initialize()). + * int up_timer_gettime(struct timespec *ts): Returns the current + * time from the platform specific time source. + * int up_timer_cancel(void): Cancels the interval timer. + * int up_timer_start(const struct timespec *ts): Start (or re-starts) + * the interval timer. + * + * The RTOS will provide the following interfaces for use by the platform- + * specific interval timer implementation: + * + * void nxsched_timer_expiration(void): Called by the platform-specific + * logic when the interval timer expires. + * + * NOTE + * Alarm option is NOT supported by XMC and never will. + * Hardware restrictions. + * + ****************************************************************************/ + +/**************************************************************************** + * XMC Timer Usage + * + * This implementation uses two timers: + * - One freerun timer to get the time since startup + * - One oneshoe timer to wait the desired delay + * + * For now, user cannot choose the CCU used. This implementation uses the + * CCU40 for timing, and CCU41 for interval. Contributions are welcome + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include +#include "hardware/xmc4_scu.h" +#include "hardware/xmc4_ccu4.h" +#include "xmc4_ccu4.h" + +#ifdef CONFIG_SCHED_TICKLESS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Only alarm option can be supporter by xmc. + * Indeed, xmc CCU compare value cannot be updated + * on the flight. It's updated via shadow registers and + * these are loaded to compare value register only on overflow + */ + +#ifdef CONFIG_SCHED_TICKLESS_ALARM +# error Alarm support is not supported by xmc +#endif + +/* The XMC only have 16 bits timers, so whatever the resolution this max is + * reached very quickly. Therefore we force the user to enable this max. + */ + +#ifndef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP +# error XMC tickless feature need to have a max delay for sleep +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct xmc4_tickless_s +{ + uint32_t overflow; /* Timer counter overflow */ + uint32_t frequency; /* Frequency Timers */ + volatile bool pending; /* True: pending task */ + uint32_t period; /* Interval period */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct xmc4_tickless_s g_tickless; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_interval_handler + * + * Description: + * Called when the oneshot timer reaches its period + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void xmc4_interval_handler(void *arg) +{ + tmrinfo("Expired...\n"); + + /* Stop the timer */ + + putreg32(CCU4_CC4_TCCLR_TRBC_MASK, XMC4_CCU41_CC40TCCLR); + + g_tickless.pending = false; + nxsched_timer_expiration(); +} + +/**************************************************************************** + * Name: xmc_timing_handler + * + * Description: + * Timer interrupt callback. When the freerun timer counter overflows, + * this interrupt will occur. We will just increment an overflow count. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void xmc4_timing_handler(void) +{ + tmrinfo("Overflow"); + g_tickless.overflow++; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_timer_initialize + * + * Description: + * Initializes all platform-specific timer facilities. This function is + * called early in the initialization sequence by up_initialize(). + * On return, the current up-time should be available from + * up_timer_gettime() and the interval timer is ready for use (but not + * actively timing. + * + * Provided by platform-specific code and called from the architecture- + * specific logic. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Assumptions: + * Called early in the initialization sequence before any special + * concurrency protections are required. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ +#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP + uint64_t max_delay; +#endif + int ret; + + g_tickless.pending = false; + g_tickless.overflow = 0; + g_tickless.frequency = USEC_PER_SEC / (uint32_t)CONFIG_USEC_PER_TICK; + + /* Enable CCU clock */ + + putreg32(SCU_CLK_CCUC, XMC4_SCU_CLKSET); + + /* Enable CCU clock during sleep */ + + putreg32(SCU_SLEEPCR_CCUCR | SCU_SLEEPCR_SYSSEL, XMC4_SCU_SLEEPCR); + + uint32_t divisor; + uint32_t pssiv; + ret = xmc4_ccu4_divisor(USEC_PER_SEC / (uint32_t)CONFIG_USEC_PER_TICK, + &divisor, + &pssiv); + g_tickless.frequency = BOARD_CCU_FREQUENCY / divisor; + if (ret < 0) + { + tmrerr("ERROR: xmc4_ccu4_divisor failed: %d\n", ret); + return ret; + } + + tmrinfo("frequency=%lu, divisor=%lu, cmr=%08lx\n", + (unsigned long)g_tickless.frequency, (unsigned long)divisor, + (unsigned long)pssiv); + + /* Initialize Interval Timer + * + * Ths timer is configured to be a oneshot timer, that has + * a resolution that matches the USEC_PER_TICK, and + * will be started in up_timer_start and uses its period + * (not compare value) to trigger an interrupt. + */ + + /* Apply reset */ + + putreg32(SCU_PR0_CCU41RS, XMC4_SCU_PRSET0); + putreg32(SCU_PR0_CCU41RS, XMC4_SCU_PRCLR0); + + /* Enable CC40 Slice */ + + putreg32(CCU4_GIDLC_CS0I_MASK, XMC4_CCU41_GIDLC); + + /* Enable the prescaler and set value */ + + putreg32(CCU4_GIDLC_SPRB_MASK, XMC4_CCU41_GIDLC); + putreg32(pssiv, XMC4_CCU41_CC40PSC); + +#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP + max_delay = (float)UINT16_MAX * USEC_PER_SEC / g_tickless.frequency; + g_oneshot_maxticks = max_delay / CONFIG_USEC_PER_TICK; +#endif + + /* Enable Single shot mode */ + + putreg32(CCU4_CC4_TC_TSSM_MASK, XMC4_CCU41_CC40TC); + + /* Attach the interrupt handler */ + + irq_attach(XMC4_IRQ_CCU41_SR0, (xcpt_t)xmc4_interval_handler, NULL); + + /* Enable Interrupt */ + + up_enable_irq(XMC4_IRQ_CCU41_SR0); + + /* Initialize Timing Timer + * + * This timer is configure to be a freerun timer that + * has a resolution that matches the USEC_PER_TICK. + */ + + /* Apply reset */ + + putreg32(SCU_PR0_CCU40RS, XMC4_SCU_PRSET0); + putreg32(SCU_PR0_CCU40RS, XMC4_SCU_PRCLR0); + + /* Enable CC40 */ + + putreg32(CCU4_GIDLC_CS0I_MASK, XMC4_CCU40_GIDLC); + + /* Enable the prescaler and set value */ + + putreg32(CCU4_GIDLC_SPRB_MASK, XMC4_CCU40_GIDLC); + putreg32(pssiv, XMC4_CCU40_CC40PSC); + + /* Set Period of the timer to max */ + + putreg32(UINT16_MAX, XMC4_CCU40_CC40PRS); + + /* Enable Period Match Interrupt */ + + putreg32(CCU4_CC4_INTE_PME_MASK, XMC4_CCU40_CC40INTE); + up_enable_irq(XMC4_IRQ_CCU40_SR0); + + /* Attach the interrupt handler */ + + irq_attach(XMC4_IRQ_CCU40_SR0, (xcpt_t)xmc4_timing_handler, NULL); + + /* Enable shadow transfer */ + + putreg32(CCU4_GCSS_S0SE_MASK, XMC4_CCU40_GCSS); + + /* Start the timing timer */ + + putreg32(CCU4_CC4_TCSET_TRBS_MASK, XMC4_CCU40_CC40TCSET); +} + +/**************************************************************************** + * Name: up_timer_gettime + * + * Description: + * Return the elapsed time since power-up (or, more correctly, since + * up_timer_initialize() was called). This function is functionally + * equivalent to: + * + * int clock_gettime(clockid_t clockid, struct timespec *ts); + * + * when clockid is CLOCK_MONOTONIC. + * + * This function provides the basis for reporting the current time and + * also is used to eliminate error build-up from small errors in interval + * time calculations. + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Provides the location in which to return the up-time. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * Called from the normal tasking context. The implementation must + * provide whatever mutual exclusion is necessary for correct operation. + * This can include disabling interrupts in order to assure atomic register + * operations. + * + ****************************************************************************/ + +int up_timer_gettime(struct timespec *ts) +{ + uint64_t usec; + uint32_t counter; + uint32_t overflow; + uint32_t sec; + irqstate_t flags; + + /* Temporarily disable the overflow counter */ + + flags = enter_critical_section(); + + counter = getreg32(XMC4_CCU40_CC40TIMER); + overflow = g_tickless.overflow; + + leave_critical_section(flags); + + usec = (uint64_t)(overflow * UINT16_MAX + counter) + * USEC_PER_SEC / g_tickless.frequency; + sec = usec / USEC_PER_SEC; + ts->tv_sec = sec; + ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; + + tmrinfo("usec=%llu ts=(%lu, %lu)\n", + usec, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + + return OK; +} + +/**************************************************************************** + * Name: up_alarm_start + * + * Description: + * Start the alarm. nxsched_alarm_expiration() will be called when the + * alarm occurs (unless up_alaram_cancel is called to stop it). + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - The time in the future at the alarm is expected to occur. When + * the alarm occurs the timer logic will call + * nxsched_alarm_expiration(). + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * May be called from interrupt level handling or from the normal tasking + * level. Interrupts may need to be disabled internally to assure + * non-reentrancy. + * + ****************************************************************************/ + +int up_timer_start(const struct timespec *ts) +{ + uint64_t usec; + uint64_t period; + irqstate_t flags; + + tmrinfo("ts=(%lu, %lu)\n", + (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + DEBUGASSERT(ts); + + /* Was an interval already running? */ + + flags = enter_critical_section(); + if (g_tickless.pending) + { + /* Yes.. then cancel it */ + + tmrinfo("Already running... cancelling\n"); + up_timer_cancel(NULL); + } + + /* Express the delay in microseconds */ + + usec = (uint64_t)ts->tv_sec * USEC_PER_SEC + + (uint64_t)(ts->tv_nsec / NSEC_PER_USEC); + + /* Compute periods of the timers to match delay to wait */ + + period = usec * (uint64_t)g_tickless.frequency / USEC_PER_SEC; + putreg32(period, XMC4_CCU41_CC40PRS); + + tmrinfo("usec=%llu period=%08llx\n", usec, period); + + DEBUGASSERT(period <= UINT16_MAX); + g_tickless.period = period; + + /* Enable interrupt */ + + putreg32(CCU4_CC4_INTE_PME_MASK, XMC4_CCU41_CC40INTE); + + /* Enable shadow transfer */ + + putreg32(CCU4_GCSS_S0SE_MASK, XMC4_CCU41_GCSS); + + /* Start timer */ + + putreg32(CCU4_CC4_TCSET_TRBS_MASK, XMC4_CCU41_CC40TCSET); + + g_tickless.pending = true; + leave_critical_section(flags); + + return OK; +} + +/**************************************************************************** + * Name: up_alarm_cancel + * + * Description: + * Cancel the alarm and return the time of cancellation of the alarm. + * These two steps need to be as nearly atomic as possible. + * nxsched_alarm_expiration() will not be called unless the alarm is + * restarted with up_alarm_start(). + * + * If, as a race condition, the alarm has already expired when this + * function is called, then time returned is the current time. + * + * NOTE: This function may execute at a high rate with no timer running (as + * when pre-emption is enabled and disabled). + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Location to return the expiration time. The current time should + * returned if the alarm is not active. ts may be NULL in which + * case the time is not returned. + * + * Returned Value: + * Zero (OK) is returned on success. A call to up_alarm_cancel() when + * the timer is not active should also return success; a negated errno + * value is returned on any failure. + * + * Assumptions: + * May be called from interrupt level handling or from the normal tasking + * level. Interrupts may need to be disabled internally to assure + * non-reentrancy. + * + ****************************************************************************/ + +int up_timer_cancel(struct timespec *ts) +{ + uint32_t regval; + uint64_t usec; + uint64_t sec; + uint64_t nsec; + irqstate_t flags; + uint32_t period; + uint32_t count; + + /* Was the timer running? */ + + flags = enter_critical_section(); + if (!g_tickless.pending) + { + /* No.. Just return zero timer remaining and successful cancellation. + * This function may execute at a high rate with no timer running + * (as when pre-emption is enabled and disabled). + */ + + if (ts != NULL) + { + ts->tv_sec = 0; + ts->tv_nsec = 0; + } + + leave_critical_section(flags); + return OK; + } + + /* Yes.. Get the timer counter and period registers and disable the compare + * interrupt. + */ + + regval = getreg32(XMC4_CCU41_CC40INTE); + regval &= ~CCU4_CC4_INTE_PME_MASK; + putreg32(regval, XMC4_CCU41_CC40INTE); + putreg32(CCU4_CC4_TCCLR_TCC_MASK | CCU4_CC4_TCCLR_TRBC_MASK, + XMC4_CCU41_CC40TCCLR); + + count = getreg32(XMC4_CCU41_CC40TIMER); + period = g_tickless.period; + g_tickless.pending = false; + leave_critical_section(flags); + + tmrinfo("Cancelling...\n"); + + if (ts != NULL) + { + /* Yes.. then calculate and return the time remaining on the + * oneshot timer. + */ + + tmrinfo("period=%lu count=%lu\n", + (unsigned long)period, (unsigned long)count); + + /* The total time remaining is the difference. Convert that + * to units of microseconds. + * + * frequency = ticks / second + * seconds = ticks * frequency + * usecs = (ticks * USEC_PER_SEC) / frequency; + */ + + usec = (((uint64_t)(period - count)) * USEC_PER_SEC) / + g_tickless.frequency; + + sec = usec / USEC_PER_SEC; + nsec = ((usec) - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; + ts->tv_sec = (time_t)sec; + ts->tv_nsec = (unsigned long)nsec; + + tmrinfo("remaining count : %lu (%lu, %lu)\n", count, + (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + } + + return OK; +} + +#endif /* CONFIG_SCHED_TICKLESS */ diff --git a/arch/arm64/CMakeLists.txt b/arch/arm64/CMakeLists.txt new file mode 100644 index 0000000000000..1ac26592f8dfe --- /dev/null +++ b/arch/arm64/CMakeLists.txt @@ -0,0 +1,21 @@ +# ############################################################################## +# arch/arm64/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +nuttx_add_subdirectory() diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index a37e03aa694ba..30ccf1bde1760 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -91,6 +91,15 @@ config ARCH_CHIP_IMX8 ---help--- NXP i.MX8 (ARMv8a) applications processors +config ARCH_CHIP_IMX9 + bool "NXP i.MX9 Platform (ARMv8.2a)" + select ARCH_HAVE_ADDRENV + select ARCH_HAVE_I2CRESET + select ARCH_HAVE_IRQTRIGGER + select ARCH_NEED_ADDRENV_MAPPING + ---help--- + NXP i.MX9 (ARMv8.2a) applications processors + config ARCH_CHIP_ARM64_CUSTOM bool "Custom ARM64 chip" select ARCH_CHIP_CUSTOM @@ -137,6 +146,15 @@ config ARCH_HAVE_EL3 runing at EL3 is not necessary and system register for EL3 is not accessible +config ARCH_ARM64_EXCEPTION_LEVEL + int "Exception level to operate" + default 1 + range 1 3 + ---help--- + Default exception level is EL1 for the NuttX OS. However, + if NuttX works as the primary bootloader, this may be set + to EL3. Other levels are not supported at the moment. + config ARCH_SET_VMPIDR_EL2 bool "Set VMPIDR_EL2 at EL2 stage" ---help--- @@ -181,6 +199,18 @@ config ARCH_CORTEX_A53 select ARCH_HAVE_TESTSET select ARM_HAVE_NEON +config ARCH_CORTEX_A55 + bool + default n + select ARCH_ARMV8A + select ARCH_HAVE_TRUSTZONE + select ARCH_DCACHE + select ARCH_ICACHE + select ARCH_HAVE_MMU + select ARCH_HAVE_FPU + select ARCH_HAVE_TESTSET + select ARM_HAVE_NEON + config ARCH_CORTEX_A57 bool default n @@ -229,6 +259,7 @@ config ARCH_CHIP default "goldfish" if ARCH_CHIP_GOLDFISH default "fvp-v8r" if ARCH_CHIP_FVP_ARMV8R default "imx8" if ARCH_CHIP_IMX8 + default "imx9" if ARCH_CHIP_IMX9 config ARM_HAVE_NEON bool @@ -311,6 +342,10 @@ if ARCH_CHIP_IMX8 source "arch/arm64/src/imx8/Kconfig" endif +if ARCH_CHIP_IMX9 +source "arch/arm64/src/imx9/Kconfig" +endif + if ARCH_CHIP_GOLDFISH source "arch/arm64/src/goldfish/Kconfig" endif diff --git a/arch/arm64/include/imx9/chip.h b/arch/arm64/include/imx9/chip.h new file mode 100644 index 0000000000000..5147ab4cc9855 --- /dev/null +++ b/arch/arm64/include/imx9/chip.h @@ -0,0 +1,90 @@ +/**************************************************************************** + * arch/arm64/include/imx9/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_INCLUDE_IMX9_CHIP_H +#define __ARCH_ARM64_INCLUDE_IMX9_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Cache line sizes (in bytes)for the i.MX9 (Cortex-A55) */ + +#define ARMV8A_DCACHE_LINESIZE 64 /* 64 bytes (16 words) */ +#define ARMV8A_ICACHE_LINESIZE 64 /* 64 bytes (16 words) */ + +/* Number of bytes in x kibibytes/mebibytes/gibibytes */ + +#define KB(x) ((x) << 10) +#define MB(x) (KB(x) << 10) +#define GB(x) (MB(UINT64_C(x)) << 10) + +#if defined(CONFIG_ARCH_CHIP_IMX93) + +#if CONFIG_ARM_GIC_VERSION == 3 || CONFIG_ARM_GIC_VERSION == 4 + +#define CONFIG_GICD_BASE 0x48000000 +#define CONFIG_GICR_BASE 0x48040000 +#define CONFIG_GICR_OFFSET 0x20000 + +#else + +#error CONFIG_ARM_GIC_VERSION should be 2, 3 or 4 + +#endif /* CONFIG_ARM_GIC_VERSION */ + +#define CONFIG_RAMBANK1_ADDR 0x80000000 +#define CONFIG_RAMBANK1_SIZE MB(128) + +#define CONFIG_DEVICEIO_BASEADDR 0x40000000 +#define CONFIG_DEVICEIO_SIZE MB(512) + +#define CONFIG_OCRAM_BASE_ADDR 0x20480000 +#define CONFIG_OCRAM_SIZE KB(640) + +#define CONFIG_FSPI_PER_BASEADDR 0x28000000 +#define CONFIG_FSPI_PER_SIZE MB(128) + +#define MPID_TO_CLUSTER_ID(mpid) ((mpid) & ~0xff) + +#define IMX9_GPIO_NPORTS 4 + +#endif + +/**************************************************************************** + * Assembly Macros + ****************************************************************************/ + +#ifdef __ASSEMBLY__ + +.macro get_cpu_id xreg0 + mrs \xreg0, mpidr_el1 + ubfx \xreg0, \xreg0, #0, #8 +.endm + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_ARM64_INCLUDE_IMX9_CHIP_H */ diff --git a/arch/arm64/include/imx9/imx93_irq.h b/arch/arm64/include/imx9/imx93_irq.h new file mode 100644 index 0000000000000..010a1b3e25e20 --- /dev/null +++ b/arch/arm64/include/imx9/imx93_irq.h @@ -0,0 +1,298 @@ +/**************************************************************************** + * arch/arm64/include/imx9/imx93_irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_INCLUDE_IMX9_IMX93_IRQ_H +#define __ARCH_ARM64_INCLUDE_IMX9_IMX93_IRQ_H + +#define IMX9_IRQ_RESERVED32 (IMX9_IRQ_EXT + 0) /* Exception condition notification while boot */ +#define IMX9_IRQ_RESERVED33 (IMX9_IRQ_EXT + 1) /* DAP interrupt */ +#define IMX9_IRQ_RESERVED34 (IMX9_IRQ_EXT + 2) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED35 (IMX9_IRQ_EXT + 3) /* CTI trigger outputs from CM33 platform */ +#define IMX9_IRQ_RESERVED36 (IMX9_IRQ_EXT + 4) /* CTI trigger outputs from CA55 platform */ +#define IMX9_IRQ_RESERVED37 (IMX9_IRQ_EXT + 5) /* Performance Unit Interrupts from CA55 platform */ +#define IMX9_IRQ_RESERVED38 (IMX9_IRQ_EXT + 6) /* ECC error from CA55 platform cache */ +#define IMX9_IRQ_RESERVED39 (IMX9_IRQ_EXT + 7) /* 1-bit or 2-bit ECC or Parity error from CA55 platform cache */ +#define IMX9_IRQ_CAN1 (IMX9_IRQ_EXT + 8) /* CAN1 interrupt */ +#define IMX9_IRQ_CAN1_ERROR (IMX9_IRQ_EXT + 9) /* CAN1 error interrupt */ +#define IMX9_IRQ_GPIO1_0 (IMX9_IRQ_EXT + 10) /* General Purpose Input/Output 1 interrupt 0 */ +#define IMX9_IRQ_GPIO1_1 (IMX9_IRQ_EXT + 11) /* General Purpose Input/Output 1 interrupt 1 */ +#define IMX9_IRQ_I3C1 (IMX9_IRQ_EXT + 12) /* Improved Inter-Integrated Circuit 1 interrupt */ +#define IMX9_IRQ_LPI2C1 (IMX9_IRQ_EXT + 13) /* Low Power Inter-Integrated Circuit module 1 */ +#define IMX9_IRQ_LPI2C2 (IMX9_IRQ_EXT + 14) /* Low Power Inter-Integrated Circuit module 2 */ +#define IMX9_IRQ_LPIT1 (IMX9_IRQ_EXT + 15) /* Low Power Periodic Interrupt Timer 1 */ +#define IMX9_IRQ_LPSPI1 (IMX9_IRQ_EXT + 16) /* Low Power Serial Peripheral Interface 1 */ +#define IMX9_IRQ_LPSPI2 (IMX9_IRQ_EXT + 17) /* Low Power Serial Peripheral Interface 2 */ +#define IMX9_IRQ_LPTMR1 (IMX9_IRQ_EXT + 18) /* Low Power Timer 1 */ +#define IMX9_IRQ_LPUART1 (IMX9_IRQ_EXT + 19) /* Low Power UART 1 */ +#define IMX9_IRQ_LPUART2 (IMX9_IRQ_EXT + 20) /* Low Power UART 2 */ +#define IMX9_IRQ_MU1_A (IMX9_IRQ_EXT + 21) /* Messaging Unit 1 - Side A (to communicate with M7 core) */ +#define IMX9_IRQ_MU1_B (IMX9_IRQ_EXT + 22) /* Messaging Unit 1 - Side B (to communicate with M33 core) */ +#define IMX9_IRQ_MU2_A (IMX9_IRQ_EXT + 23) /* Messaging Unit 2 - Side A (to communicate with M7 core) */ +#define IMX9_IRQ_MU2_B (IMX9_IRQ_EXT + 24) /* Messaging Unit 2 - Side B (to communicate with A55 core) */ +#define IMX9_IRQ_RESERVED57 (IMX9_IRQ_EXT + 25) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED58 (IMX9_IRQ_EXT + 26) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED59 (IMX9_IRQ_EXT + 27) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED60 (IMX9_IRQ_EXT + 28) /* Edgelock Trust MUA RX full interrupt */ +#define IMX9_IRQ_RESERVED61 (IMX9_IRQ_EXT + 29) /* Edgelock Trust MUA TX empty interrupt */ +#define IMX9_IRQ_RESERVED62 (IMX9_IRQ_EXT + 30) /* Edgelock Apps Core MUA RX full interrupt */ +#define IMX9_IRQ_RESERVED63 (IMX9_IRQ_EXT + 31) /* Edgelock Apps Core MUA TX empty interrupt */ +#define IMX9_IRQ_RESERVED64 (IMX9_IRQ_EXT + 32) /* Edgelock Realtime Core MUA RX full interrupt */ +#define IMX9_IRQ_RESERVED65 (IMX9_IRQ_EXT + 33) /* Edgelock Realtime Core MUA TX empty interrupt */ +#define IMX9_IRQ_RESERVED66 (IMX9_IRQ_EXT + 34) /* Edgelock secure interrupt */ +#define IMX9_IRQ_RESERVED67 (IMX9_IRQ_EXT + 35) /* Edgelock non-secure interrupt */ +#define IMX9_IRQ_TPM1 (IMX9_IRQ_EXT + 36) /* Timer PWM module 1 */ +#define IMX9_IRQ_TPM2 (IMX9_IRQ_EXT + 37) /* Timer PWM module 2 */ +#define IMX9_IRQ_WDOG1 (IMX9_IRQ_EXT + 38) /* Watchdog 1 Interrupt */ +#define IMX9_IRQ_WDOG2 (IMX9_IRQ_EXT + 39) /* Watchdog 2 Interrupt */ +#define IMX9_IRQ_TRDC (IMX9_IRQ_EXT + 40) /* AONMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED73 (IMX9_IRQ_EXT + 41) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED74 (IMX9_IRQ_EXT + 42) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED75 (IMX9_IRQ_EXT + 43) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED76 (IMX9_IRQ_EXT + 44) /* Reserved interrupt */ +#define IMX9_IRQ_SAI1 (IMX9_IRQ_EXT + 45) /* Serial Audio Interface 1 */ +#define IMX9_IRQ_RESERVED78 (IMX9_IRQ_EXT + 46) /* M33 PS Tag/Data Parity Error */ +#define IMX9_IRQ_RESERVED79 (IMX9_IRQ_EXT + 47) /* M33 TCM ECC interrupt */ +#define IMX9_IRQ_RESERVED80 (IMX9_IRQ_EXT + 48) /* M33 TCM Error interrupt */ +#define IMX9_IRQ_RESERVED81 (IMX9_IRQ_EXT + 49) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED82 (IMX9_IRQ_EXT + 50) /* Reserved interrupt */ +#define IMX9_IRQ_CAN2 (IMX9_IRQ_EXT + 51) /* CAN2 interrupt */ +#define IMX9_IRQ_CAN2_ERROR (IMX9_IRQ_EXT + 52) /* CAN2 error interrupt */ +#define IMX9_IRQ_FLEXIO1 (IMX9_IRQ_EXT + 53) /* Flexible IO 1 interrupt */ +#define IMX9_IRQ_FLEXIO2 (IMX9_IRQ_EXT + 54) /* Flexible IO 2 interrupt */ +#define IMX9_IRQ_FLEXSPI1 (IMX9_IRQ_EXT + 55) /* FlexSPI controller interface interrupt 1 */ +#define IMX9_IRQ_RESERVED88 (IMX9_IRQ_EXT + 56) /* Reserved interrupt */ +#define IMX9_IRQ_GPIO2_0 (IMX9_IRQ_EXT + 57) /* General Purpose Input/Output 2 interrupt 0 */ +#define IMX9_IRQ_GPIO2_1 (IMX9_IRQ_EXT + 58) /* General Purpose Input/Output 2 interrupt 1 */ +#define IMX9_IRQ_GPIO3_0 (IMX9_IRQ_EXT + 59) /* General Purpose Input/Output 3 interrupt 0 */ +#define IMX9_IRQ_GPIO3_1 (IMX9_IRQ_EXT + 60) /* General Purpose Input/Output 3 interrupt 1 */ +#define IMX9_IRQ_I3C2 (IMX9_IRQ_EXT + 61) /* Improved Inter-Integrated Circuit 2 interrupt */ +#define IMX9_IRQ_LPI2C3 (IMX9_IRQ_EXT + 62) /* Low Power Inter-Integrated Circuit module 3 */ +#define IMX9_IRQ_LPI2C4 (IMX9_IRQ_EXT + 63) /* Low Power Inter-Integrated Circuit module 4 */ +#define IMX9_IRQ_LPIT2 (IMX9_IRQ_EXT + 64) /* Low Power Periodic Interrupt Timer 2 */ +#define IMX9_IRQ_LPSPI3 (IMX9_IRQ_EXT + 65) /* Low Power Serial Peripheral Interface 3 */ +#define IMX9_IRQ_LPSPI4 (IMX9_IRQ_EXT + 66) /* Low Power Serial Peripheral Interface 4 */ +#define IMX9_IRQ_LPTMR2 (IMX9_IRQ_EXT + 67) /* Low Power Timer 2 */ +#define IMX9_IRQ_LPUART3 (IMX9_IRQ_EXT + 68) /* Low Power UART 3 */ +#define IMX9_IRQ_LPUART4 (IMX9_IRQ_EXT + 69) /* Low Power UART 4 */ +#define IMX9_IRQ_LPUART5 (IMX9_IRQ_EXT + 70) /* Low Power UART 5 */ +#define IMX9_IRQ_LPUART6 (IMX9_IRQ_EXT + 71) /* Low Power UART 6 */ +#define IMX9_IRQ_RESERVED104 (IMX9_IRQ_EXT + 72) /* MTR Master error interrupt */ +#define IMX9_IRQ_RESERVED105 (IMX9_IRQ_EXT + 73) /* BBNSM Non-Secure interrupt */ +#define IMX9_IRQ_RESERVED106 (IMX9_IRQ_EXT + 74) /* System Counter compare interrupt */ +#define IMX9_IRQ_TPM3 (IMX9_IRQ_EXT + 75) /* Timer PWM module 3 */ +#define IMX9_IRQ_TPM4 (IMX9_IRQ_EXT + 76) /* Timer PWM module 4 */ +#define IMX9_IRQ_TPM5 (IMX9_IRQ_EXT + 77) /* Timer PWM module 5 */ +#define IMX9_IRQ_TPM6 (IMX9_IRQ_EXT + 78) /* Timer PWM module 6 */ +#define IMX9_IRQ_WDOG3 (IMX9_IRQ_EXT + 79) /* Watchdog 3 Interrupt */ +#define IMX9_IRQ_WDOG4 (IMX9_IRQ_EXT + 80) /* Watchdog 4 Interrupt */ +#define IMX9_IRQ_WDOG5 (IMX9_IRQ_EXT + 81) /* Watchdog 5 Interrupt */ +#define IMX9_IRQ_RESERVED114 (IMX9_IRQ_EXT + 82) /* WAKEUPMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_TEMPMON (IMX9_IRQ_EXT + 83) /* TempSensor interrupt */ +#define IMX9_IRQ_RESERVED116 (IMX9_IRQ_EXT + 84) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED117 (IMX9_IRQ_EXT + 85) /* Reserved interrupt */ +#define IMX9_IRQ_USDHC1 (IMX9_IRQ_EXT + 86) /* ultra Secure Digital Host Controller interrupt 1 */ +#define IMX9_IRQ_USDHC2 (IMX9_IRQ_EXT + 87) /* ultra Secure Digital Host Controller interrupt 2 */ +#define IMX9_IRQ_RESERVED120 (IMX9_IRQ_EXT + 88) /* MEGAMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED121 (IMX9_IRQ_EXT + 89) /* NIC_WRAPPER TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED122 (IMX9_IRQ_EXT + 90) /* DRAM controller Performance Monitor Interrupt */ +#define IMX9_IRQ_RESERVED123 (IMX9_IRQ_EXT + 91) /* DRAM controller Critical Interrupt */ +#define IMX9_IRQ_RESERVED124 (IMX9_IRQ_EXT + 92) /* DRAM Phy Critical Interrupt */ +#define IMX9_IRQ_RESERVED125 (IMX9_IRQ_EXT + 93) /* Reserved interrupt */ +#define IMX9_IRQ_DMA3_ERROR (IMX9_IRQ_EXT + 94) /* eDMA1 error interrupt */ +#define IMX9_IRQ_DMA3_0 (IMX9_IRQ_EXT + 95) /* eDMA1 channel 0 interrupt */ +#define IMX9_IRQ_DMA3_1 (IMX9_IRQ_EXT + 96) /* eDMA1 channel 1 interrupt */ +#define IMX9_IRQ_DMA3_2 (IMX9_IRQ_EXT + 97) /* eDMA1 channel 2 interrupt */ +#define IMX9_IRQ_DMA3_3 (IMX9_IRQ_EXT + 98) /* eDMA1 channel 3 interrupt */ +#define IMX9_IRQ_DMA3_4 (IMX9_IRQ_EXT + 99) /* eDMA1 channel 4 interrupt */ +#define IMX9_IRQ_DMA3_5 (IMX9_IRQ_EXT + 100) /* eDMA1 channel 5 interrupt */ +#define IMX9_IRQ_DMA3_6 (IMX9_IRQ_EXT + 101) /* eDMA1 channel 6 interrupt */ +#define IMX9_IRQ_DMA3_7 (IMX9_IRQ_EXT + 102) /* eDMA1 channel 7 interrupt */ +#define IMX9_IRQ_DMA3_8 (IMX9_IRQ_EXT + 103) /* eDMA1 channel 8 interrupt */ +#define IMX9_IRQ_DMA3_9 (IMX9_IRQ_EXT + 104) /* eDMA1 channel 9 interrupt */ +#define IMX9_IRQ_DMA3_10 (IMX9_IRQ_EXT + 105) /* eDMA1 channel 10 interrupt */ +#define IMX9_IRQ_DMA3_11 (IMX9_IRQ_EXT + 106) /* eDMA1 channel 11 interrupt */ +#define IMX9_IRQ_DMA3_12 (IMX9_IRQ_EXT + 107) /* eDMA1 channel 12 interrupt */ +#define IMX9_IRQ_DMA3_13 (IMX9_IRQ_EXT + 108) /* eDMA1 channel 13 interrupt */ +#define IMX9_IRQ_DMA3_14 (IMX9_IRQ_EXT + 109) /* eDMA1 channel 14 interrupt */ +#define IMX9_IRQ_DMA3_15 (IMX9_IRQ_EXT + 110) /* eDMA1 channel 15 interrupt */ +#define IMX9_IRQ_DMA3_16 (IMX9_IRQ_EXT + 111) /* eDMA1 channel 16 interrupt */ +#define IMX9_IRQ_DMA3_17 (IMX9_IRQ_EXT + 112) /* eDMA1 channel 17 interrupt */ +#define IMX9_IRQ_DMA3_18 (IMX9_IRQ_EXT + 113) /* eDMA1 channel 18 interrupt */ +#define IMX9_IRQ_DMA3_19 (IMX9_IRQ_EXT + 114) /* eDMA1 channel 19 interrupt */ +#define IMX9_IRQ_DMA3_20 (IMX9_IRQ_EXT + 115) /* eDMA1 channel 20 interrupt */ +#define IMX9_IRQ_DMA3_21 (IMX9_IRQ_EXT + 116) /* eDMA1 channel 21 interrupt */ +#define IMX9_IRQ_DMA3_22 (IMX9_IRQ_EXT + 117) /* eDMA1 channel 22 interrupt */ +#define IMX9_IRQ_DMA3_23 (IMX9_IRQ_EXT + 118) /* eDMA1 channel 23 interrupt */ +#define IMX9_IRQ_DMA3_24 (IMX9_IRQ_EXT + 119) /* eDMA1 channel 24 interrupt */ +#define IMX9_IRQ_DMA3_25 (IMX9_IRQ_EXT + 120) /* eDMA1 channel 25 interrupt */ +#define IMX9_IRQ_DMA3_26 (IMX9_IRQ_EXT + 121) /* eDMA1 channel 26 interrupt */ +#define IMX9_IRQ_DMA3_27 (IMX9_IRQ_EXT + 122) /* eDMA1 channel 27 interrupt */ +#define IMX9_IRQ_DMA3_28 (IMX9_IRQ_EXT + 123) /* eDMA1 channel 28 interrupt */ +#define IMX9_IRQ_DMA3_29 (IMX9_IRQ_EXT + 124) /* eDMA1 channel 29 interrupt */ +#define IMX9_IRQ_DMA3_30 (IMX9_IRQ_EXT + 125) /* eDMA1 channel 30 interrupt */ +#define IMX9_IRQ_RESERVED158 (IMX9_IRQ_EXT + 126) /* Reserved interrupt */ +#define IMX9_IRQ_DMA4_ERROR (IMX9_IRQ_EXT + 127) /* eDMA2 error interrupt */ +#define IMX9_IRQ_DMA4_0_1 (IMX9_IRQ_EXT + 128) /* eDMA2 channel 0/1 interrupt */ +#define IMX9_IRQ_DMA4_2_3 (IMX9_IRQ_EXT + 129) /* eDMA2 channel 2/3 interrupt */ +#define IMX9_IRQ_DMA4_4_5 (IMX9_IRQ_EXT + 130) /* eDMA2 channel 4/5 interrupt */ +#define IMX9_IRQ_DMA4_6_7 (IMX9_IRQ_EXT + 131) /* eDMA2 channel 6/7 interrupt */ +#define IMX9_IRQ_DMA4_8_9 (IMX9_IRQ_EXT + 132) /* eDMA2 channel 8/9 interrupt */ +#define IMX9_IRQ_DMA4_10_11 (IMX9_IRQ_EXT + 133) /* eDMA2 channel 10/11 interrupt */ +#define IMX9_IRQ_DMA4_12_13 (IMX9_IRQ_EXT + 134) /* eDMA2 channel 12/13 interrupt */ +#define IMX9_IRQ_DMA4_14_15 (IMX9_IRQ_EXT + 135) /* eDMA2 channel 14/15 interrupt */ +#define IMX9_IRQ_DMA4_16_17 (IMX9_IRQ_EXT + 136) /* eDMA2 channel 16/17 interrupt */ +#define IMX9_IRQ_DMA4_18_19 (IMX9_IRQ_EXT + 137) /* eDMA2 channel 18/19 interrupt */ +#define IMX9_IRQ_DMA4_20_21 (IMX9_IRQ_EXT + 138) /* eDMA2 channel 20/21 interrupt */ +#define IMX9_IRQ_DMA4_22_23 (IMX9_IRQ_EXT + 139) /* eDMA2 channel 22/23 interrupt */ +#define IMX9_IRQ_DMA4_24_25 (IMX9_IRQ_EXT + 140) /* eDMA2 channel 24/25 interrupt */ +#define IMX9_IRQ_DMA4_26_27 (IMX9_IRQ_EXT + 141) /* eDMA2 channel 26/27 interrupt */ +#define IMX9_IRQ_DMA4_28_29 (IMX9_IRQ_EXT + 142) /* eDMA2 channel 28/29 interrupt */ +#define IMX9_IRQ_DMA4_30_31 (IMX9_IRQ_EXT + 143) /* eDMA2 channel 30/31 interrupt */ +#define IMX9_IRQ_DMA4_32_33 (IMX9_IRQ_EXT + 144) /* eDMA2 channel 32/33 interrupt */ +#define IMX9_IRQ_DMA4_34_35 (IMX9_IRQ_EXT + 145) /* eDMA2 channel 34/35 interrupt */ +#define IMX9_IRQ_DMA4_36_37 (IMX9_IRQ_EXT + 146) /* eDMA2 channel 36/37 interrupt */ +#define IMX9_IRQ_DMA4_38_39 (IMX9_IRQ_EXT + 147) /* eDMA2 channel 38/39 interrupt */ +#define IMX9_IRQ_DMA4_40_41 (IMX9_IRQ_EXT + 148) /* eDMA2 channel 40/41 interrupt */ +#define IMX9_IRQ_DMA4_42_43 (IMX9_IRQ_EXT + 149) /* eDMA2 channel 42/43 interrupt */ +#define IMX9_IRQ_DMA4_44_45 (IMX9_IRQ_EXT + 150) /* eDMA2 channel 44/45 interrupt */ +#define IMX9_IRQ_DMA4_46_47 (IMX9_IRQ_EXT + 151) /* eDMA2 channel 46/47 interrupt */ +#define IMX9_IRQ_DMA4_48_49 (IMX9_IRQ_EXT + 152) /* eDMA2 channel 48/49 interrupt */ +#define IMX9_IRQ_DMA4_50_51 (IMX9_IRQ_EXT + 153) /* eDMA2 channel 50/51 interrupt */ +#define IMX9_IRQ_DMA4_52_53 (IMX9_IRQ_EXT + 154) /* eDMA2 channel 52/53 interrupt */ +#define IMX9_IRQ_DMA4_54_55 (IMX9_IRQ_EXT + 155) /* eDMA2 channel 54/55 interrupt */ +#define IMX9_IRQ_DMA4_56_57 (IMX9_IRQ_EXT + 156) /* eDMA2 channel 56/57 interrupt */ +#define IMX9_IRQ_DMA4_58_59 (IMX9_IRQ_EXT + 157) /* eDMA2 channel 58/59 interrupt */ +#define IMX9_IRQ_DMA4_60_61 (IMX9_IRQ_EXT + 158) /* eDMA2 channel 60/61 interrupt */ +#define IMX9_IRQ_DMA4_62_63 (IMX9_IRQ_EXT + 159) /* eDMA2 channel 62/63 interrupt */ +#define IMX9_IRQ_RESERVED192 (IMX9_IRQ_EXT + 160) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED193 (IMX9_IRQ_EXT + 161) /* Edgelock Group 1 reset source */ +#define IMX9_IRQ_RESERVED194 (IMX9_IRQ_EXT + 162) /* Edgelock Group 2 reset source */ +#define IMX9_IRQ_RESERVED195 (IMX9_IRQ_EXT + 163) /* Edgelock Group 2 reset source */ +#define IMX9_IRQ_RESERVED196 (IMX9_IRQ_EXT + 164) /* JTAGSW DAP MDM-AP SRC reset source */ +#define IMX9_IRQ_RESERVED197 (IMX9_IRQ_EXT + 165) /* JTAGC SRC reset source */ +#define IMX9_IRQ_RESERVED198 (IMX9_IRQ_EXT + 166) /* CM33 SYSREQRST SRC reset source */ +#define IMX9_IRQ_RESERVED199 (IMX9_IRQ_EXT + 167) /* CM33 LOCKUP SRC reset source */ +#define IMX9_IRQ_RESERVED200 (IMX9_IRQ_EXT + 168) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED201 (IMX9_IRQ_EXT + 169) /* Reserved interrupt */ +#define IMX9_IRQ_SAI2 (IMX9_IRQ_EXT + 170) /* Serial Audio Interface 2 */ +#define IMX9_IRQ_SAI3 (IMX9_IRQ_EXT + 171) /* Serial Audio Interface 3 */ +#define IMX9_IRQ_ISI (IMX9_IRQ_EXT + 172) /* ISI interrupt */ +#define IMX9_IRQ_RESERVED205 (IMX9_IRQ_EXT + 173) /* PXP interrupt 0 */ +#define IMX9_IRQ_RESERVED206 (IMX9_IRQ_EXT + 174) /* PXP interrupt 1 */ +#define IMX9_IRQ_CSI (IMX9_IRQ_EXT + 175) /* CSI interrupt */ +#define IMX9_IRQ_RESERVED208 (IMX9_IRQ_EXT + 176) /* LCDIF Sync Interrupt */ +#define IMX9_IRQ_DSI (IMX9_IRQ_EXT + 177) /* MIPI DSI Interrupt Request */ +#define IMX9_IRQ_RESERVED210 (IMX9_IRQ_EXT + 178) /* Machine learning processor interrupt */ +#define IMX9_IRQ_ENET_MAC0_RX_TX_D ONE1 (IMX9_IRQ_EXT + 179) /* MAC 0 Receive/ Trasmit Frame/ Buffer Done */ +#define IMX9_IRQ_ENET_MAC0_RX_TX_D ONE2 (IMX9_IRQ_EXT + 180) /* MAC 0 Receive/ Trasmit Frame/ Buffer Done */ +#define IMX9_IRQ_ENET (IMX9_IRQ_EXT + 181) /* MAC 0 IRQ */ +#define IMX9_IRQ_ENET_1588 (IMX9_IRQ_EXT + 182) /* MAC 0 1588 Timer Interrupt - synchronous */ +#define IMX9_IRQ_ENET_QOS_PMT (IMX9_IRQ_EXT + 183) /* ENET QOS PMT interrupt */ +#define IMX9_IRQ_ENET_QOS (IMX9_IRQ_EXT + 184) /* ENET QOS interrupt */ +#define IMX9_IRQ_RESERVED217 (IMX9_IRQ_EXT + 185) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED218 (IMX9_IRQ_EXT + 186) /* Reserved interrupt */ +#define IMX9_IRQ_USB1 (IMX9_IRQ_EXT + 187) /* USB-1 Wake-up Interrupt */ +#define IMX9_IRQ_USB2 (IMX9_IRQ_EXT + 188) /* USB-2 Wake-up Interrupt */ +#define IMX9_IRQ_GPIO4_0 (IMX9_IRQ_EXT + 189) /* General Purpose Input/Output 4 interrupt 0 */ +#define IMX9_IRQ_GPIO4_1 (IMX9_IRQ_EXT + 190) /* General Purpose Input/Output 4 interrupt 1 */ +#define IMX9_IRQ_LPSPI5 (IMX9_IRQ_EXT + 191) /* Low Power Serial Peripheral Interface 5 */ +#define IMX9_IRQ_LPSPI6 (IMX9_IRQ_EXT + 192) /* Low Power Serial Peripheral Interface 6 */ +#define IMX9_IRQ_LPSPI7 (IMX9_IRQ_EXT + 193) /* Low Power Serial Peripheral Interface 7 */ +#define IMX9_IRQ_LPSPI8 (IMX9_IRQ_EXT + 194) /* Low Power Serial Peripheral Interface 8 */ +#define IMX9_IRQ_LPI2C5 (IMX9_IRQ_EXT + 195) /* Low Power Inter-Integrated Circuit module 5 */ +#define IMX9_IRQ_LPI2C6 (IMX9_IRQ_EXT + 196) /* Low Power Inter-Integrated Circuit module 6 */ +#define IMX9_IRQ_LPI2C7 (IMX9_IRQ_EXT + 197) /* Low Power Inter-Integrated Circuit module 7 */ +#define IMX9_IRQ_LPI2C8 (IMX9_IRQ_EXT + 198) /* Low Power Inter-Integrated Circuit module 8 */ +#define IMX9_IRQ_PDM_HWVAD_ERROR (IMX9_IRQ_EXT + 199) /* PDM interrupt */ +#define IMX9_IRQ_PDM_HWVAD_EVENT (IMX9_IRQ_EXT + 200) /* PDM interrupt */ +#define IMX9_IRQ_PDM_ERROR (IMX9_IRQ_EXT + 201) /* PDM interrupt */ +#define IMX9_IRQ_PDM_EVENT (IMX9_IRQ_EXT + 202) /* PDM interrupt */ +#define IMX9_IRQ_RESERVED235 (IMX9_IRQ_EXT + 203) /* AUDIO XCVR interrupt */ +#define IMX9_IRQ_RESERVED236 (IMX9_IRQ_EXT + 204) /* AUDIO XCVR interrupt */ +#define IMX9_IRQ_USDHC3 (IMX9_IRQ_EXT + 205) /* ultra Secure Digital Host Controller interrupt 3 */ +#define IMX9_IRQ_RESERVED238 (IMX9_IRQ_EXT + 206) /* OCRAM MECC interrupt */ +#define IMX9_IRQ_RESERVED239 (IMX9_IRQ_EXT + 207) /* OCRAM MECC interrupt */ +#define IMX9_IRQ_RESERVED240 (IMX9_IRQ_EXT + 208) /* HSIOMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_RESERVED241 (IMX9_IRQ_EXT + 209) /* MEDIAMIX TRDC transfer error interrupt */ +#define IMX9_IRQ_LPUART7 (IMX9_IRQ_EXT + 210) /* Low Power UART 7 */ +#define IMX9_IRQ_LPUART8 (IMX9_IRQ_EXT + 211) /* Low Power UART 8 */ +#define IMX9_IRQ_RESERVED244 (IMX9_IRQ_EXT + 212) /* CM33 MCM interrupt */ +#define IMX9_IRQ_RESERVED245 (IMX9_IRQ_EXT + 213) /* SFA interrupt */ +#define IMX9_IRQ_RESERVED246 (IMX9_IRQ_EXT + 214) /* GIC600 INTERRUPT */ +#define IMX9_IRQ_RESERVED247 (IMX9_IRQ_EXT + 215) /* GIC600 INTERRUPT */ +#define IMX9_IRQ_RESERVED248 (IMX9_IRQ_EXT + 216) /* GIC600 INTERRUPT */ +#define IMX9_IRQ_RESERVED249 (IMX9_IRQ_EXT + 217) /* ADC interrupt */ +#define IMX9_IRQ_RESERVED250 (IMX9_IRQ_EXT + 218) /* ADC interrupt */ +#define IMX9_IRQ_RESERVED251 (IMX9_IRQ_EXT + 219) /* ADC interrupt */ +#define IMX9_IRQ_RESERVED252 (IMX9_IRQ_EXT + 220) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED253 (IMX9_IRQ_EXT + 221) /* I3C1 wakeup irq after double sync */ +#define IMX9_IRQ_RESERVED254 (IMX9_IRQ_EXT + 222) /* I3C2 wakeup irq after double sync */ +#define IMX9_IRQ_RESERVED255 (IMX9_IRQ_EXT + 223) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED256 (IMX9_IRQ_EXT + 224) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED257 (IMX9_IRQ_EXT + 225) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED258 (IMX9_IRQ_EXT + 226) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED259 (IMX9_IRQ_EXT + 227) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED260 (IMX9_IRQ_EXT + 228) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED261 (IMX9_IRQ_EXT + 229) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED262 (IMX9_IRQ_EXT + 230) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED263 (IMX9_IRQ_EXT + 231) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED264 (IMX9_IRQ_EXT + 232) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED265 (IMX9_IRQ_EXT + 233) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED266 (IMX9_IRQ_EXT + 234) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED267 (IMX9_IRQ_EXT + 235) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED268 (IMX9_IRQ_EXT + 236) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED269 (IMX9_IRQ_EXT + 237) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED270 (IMX9_IRQ_EXT + 238) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED271 (IMX9_IRQ_EXT + 239) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED272 (IMX9_IRQ_EXT + 240) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED273 (IMX9_IRQ_EXT + 241) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED274 (IMX9_IRQ_EXT + 242) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED275 (IMX9_IRQ_EXT + 243) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED276 (IMX9_IRQ_EXT + 244) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED277 (IMX9_IRQ_EXT + 245) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED278 (IMX9_IRQ_EXT + 246) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED279 (IMX9_IRQ_EXT + 247) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED280 (IMX9_IRQ_EXT + 248) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED281 (IMX9_IRQ_EXT + 249) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED282 (IMX9_IRQ_EXT + 250) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED283 (IMX9_IRQ_EXT + 251) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED284 (IMX9_IRQ_EXT + 252) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED285 (IMX9_IRQ_EXT + 253) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED286 (IMX9_IRQ_EXT + 254) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED287 (IMX9_IRQ_EXT + 255) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED288 (IMX9_IRQ_EXT + 256) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED289 (IMX9_IRQ_EXT + 257) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED290 (IMX9_IRQ_EXT + 258) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED291 (IMX9_IRQ_EXT + 259) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED292 (IMX9_IRQ_EXT + 260) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED293 (IMX9_IRQ_EXT + 261) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED294 (IMX9_IRQ_EXT + 262) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED295 (IMX9_IRQ_EXT + 263) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED296 (IMX9_IRQ_EXT + 264) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED297 (IMX9_IRQ_EXT + 265) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED298 (IMX9_IRQ_EXT + 266) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED299 (IMX9_IRQ_EXT + 267) /* Reserved interrupt */ +#define IMX9_IRQ_RESERVED300 (IMX9_IRQ_EXT + 268) /* ADC Asynchronous Interrupt */ + +/* Total amount of entries in system vector table */ + +#define NR_IRQS (301) + +#endif /* __ARCH_ARM64_INCLUDE_IMX9_IMX93_IRQ_H */ diff --git a/arch/arm64/include/imx9/irq.h b/arch/arm64/include/imx9/irq.h new file mode 100644 index 0000000000000..5e96f56a7957a --- /dev/null +++ b/arch/arm64/include/imx9/irq.h @@ -0,0 +1,70 @@ +/**************************************************************************** + * arch/arm64/include/imx9/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_ARM64_INCLUDE_IMX9_IRQ_H +#define __ARCH_ARM64_INCLUDE_IMX9_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX93) +# include +#else +# error "Unrecognized i.MX9 architecture" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IMX9_IRQ_SOFTWARE0 (0) /* Cortex-A55 Software Generated Interrupt 0 */ +#define IMX9_IRQ_SOFTWARE1 (1) /* Cortex-A55 Software Generated Interrupt 1 */ +#define IMX9_IRQ_SOFTWARE2 (2) /* Cortex-A55 Software Generated Interrupt 2 */ +#define IMX9_IRQ_SOFTWARE3 (3) /* Cortex-A55 Software Generated Interrupt 3 */ +#define IMX9_IRQ_SOFTWARE4 (4) /* Cortex-A55 Software Generated Interrupt 4 */ +#define IMX9_IRQ_SOFTWARE5 (5) /* Cortex-A55 Software Generated Interrupt 5 */ +#define IMX9_IRQ_SOFTWARE6 (6) /* Cortex-A55 Software Generated Interrupt 6 */ +#define IMX9_IRQ_SOFTWARE7 (7) /* Cortex-A55 Software Generated Interrupt 7 */ +#define IMX9_IRQ_SOFTWARE8 (8) /* Cortex-A55 Software Generated Interrupt 8 */ +#define IMX9_IRQ_SOFTWARE9 (9) /* Cortex-A55 Software Generated Interrupt 9 */ +#define IMX9_IRQ_SOFTWARE10 (10) /* Cortex-A55 Software Generated Interrupt 10 */ +#define IMX9_IRQ_SOFTWARE11 (11) /* Cortex-A55 Software Generated Interrupt 11 */ +#define IMX9_IRQ_SOFTWARE12 (12) /* Cortex-A55 Software Generated Interrupt 12 */ +#define IMX9_IRQ_SOFTWARE13 (13) /* Cortex-A55 Software Generated Interrupt 13 */ +#define IMX9_IRQ_SOFTWARE14 (14) /* Cortex-A55 Software Generated Interrupt 14 */ +#define IMX9_IRQ_SOFTWARE15 (15) /* Cortex-A55 Software Generated Interrupt 15 */ +#define IMX9_IRQ_VIRTUALMAINTENANCE (25) /* Cortex-A55 Virtual Maintenance Interrupt */ +#define IMX9_IRQ_HYPERVISORTIMER (26) /* Cortex-A55 Hypervisor Timer Interrupt */ +#define IMX9_IRQ_VIRTUALTIMER (27) /* Cortex-A55 Virtual Timer Interrupt */ +#define IMX9_IRQ_LEGACYFASTINT (28) /* Cortex-A55 Legacy nFIQ signal Interrupt */ +#define IMX9_IRQ_SECUREPHYTIMER (29) /* Cortex-A55 Secure Physical Timer Interrupt */ +#define IMX9_IRQ_NONSECUREPHYTIMER (30) /* Cortex-A55 Non-secure Physical Timer Interrupt */ +#define IMX9_IRQ_LEGACYIRQ (31) /* Cortex-A55 Legacy nIRQ Interrupt */ + +#define IMX9_IRQ_EXT (32) /* Vector number of the first ext int */ + +#endif /* __ARCH_ARM64_INCLUDE_IMX9_IRQ_H */ diff --git a/arch/arm64/include/irq.h b/arch/arm64/include/irq.h index ccaf44e1b5cf3..56ac7278a8338 100644 --- a/arch/arm64/include/irq.h +++ b/arch/arm64/include/irq.h @@ -207,7 +207,7 @@ extern "C" ****************************************************************************/ /* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt + * register storage structure. It is non-NULL only during interrupt * processing. Access to g_current_regs[] must be through the macro * CURRENT_REGS for portability. */ @@ -254,7 +254,7 @@ struct xcptcontext * address register (FAR) at the time of data abort exception. */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING uintptr_t far; #endif diff --git a/arch/arm64/src/CMakeLists.txt b/arch/arm64/src/CMakeLists.txt new file mode 100644 index 0000000000000..baf56e8c9211f --- /dev/null +++ b/arch/arm64/src/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm64/src/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## +add_subdirectory(common) +add_subdirectory(${NUTTX_CHIP_ABS_DIR} EXCLUDE_FROM_ALL exclude_chip) +# Include directories (before system ones) as PUBLIC so that it can be exposed +# to libboard +target_include_directories(arch BEFORE PUBLIC ${NUTTX_CHIP_ABS_DIR} common) +if(NOT CONFIG_BUILD_FLAT) + target_include_directories(arch_interface BEFORE PUBLIC ${NUTTX_CHIP_ABS_DIR} + common) +endif() diff --git a/arch/arm64/src/Makefile b/arch/arm64/src/Makefile index fc1b4c9ffa053..15f5b7b02df0c 100644 --- a/arch/arm64/src/Makefile +++ b/arch/arm64/src/Makefile @@ -18,7 +18,7 @@ # ############################################################################ -include $(TOPDIR)/Make.defs +include $(TOPDIR)/tools/apps-or-nuttx-Make.defs include chip/Make.defs ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src @@ -54,7 +54,7 @@ CSRCS = $(CHIP_CSRCS) $(CMN_CSRCS) COBJS = $(CSRCS:.c=$(OBJEXT)) SRCS = $(ASRCS) $(CSRCS) -OBJS = $(AOBJS) $(COBJS) +OBJS = $(AOBJS) $(COBJS) $(HEAD_OBJ) # User-mode objects @@ -156,13 +156,27 @@ $(KBIN): $(OBJS) board$(DELIM)libboard$(LIBEXT): $(Q) $(MAKE) -C board libboard$(LIBEXT) EXTRAFLAGS="$(EXTRAFLAGS)" -define LINK_ALLSYMS - $(Q) $(TOPDIR)/tools/mkallsyms.py $(NUTTX) allsyms.tmp +# When multiple linking, these two additional linking objects will be included + +ifeq ($(CONFIG_MM_KASAN_GLOBAL),y) +EXTRA_LIBS += kasan_globals$(OBJEXT) +endif +ifeq ($(CONFIG_ALLSYMS),y) +EXTRA_LIBS += allsyms$(OBJEXT) +endif + +define LINK_ALLSYMS_KASAN + $(if $(CONFIG_ALLSYMS), + $(Q) $(TOPDIR)/tools/mkallsyms.py $(NUTTX) allsyms.tmp --orderbyname $(CONFIG_SYMTAB_ORDEREDBYNAME) $(Q) $(call COMPILE, allsyms.tmp, allsyms$(OBJEXT), -x c) + $(Q) $(call DELFILE, allsyms.tmp)) + $(if $(CONFIG_MM_KASAN_GLOBAL), + $(Q) $(TOPDIR)/tools/kasan_global.py -e $(NUTTX) -o kasan_globals.tmp + $(Q) $(call COMPILE, kasan_globals.tmp, kasan_globals$(OBJEXT) -fno-sanitize=kernel-address, -x c) + $(Q) $(call DELFILE, kasan_globals.tmp)) $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ - -o $(NUTTX) $(HEAD_OBJ) allsyms$(OBJEXT) $(EXTRA_OBJS) \ + -o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \ $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) - $(Q) $(call DELFILE, allsyms.tmp allsyms$(OBJEXT)) endef $(addsuffix .tmp,$(ARCHSCRIPT)): $(ARCHSCRIPT) @@ -170,17 +184,19 @@ $(addsuffix .tmp,$(ARCHSCRIPT)): $(ARCHSCRIPT) nuttx$(EXEEXT): $(HEAD_OBJ) board$(DELIM)libboard$(LIBEXT) $(addsuffix .tmp,$(ARCHSCRIPT)) $(Q) echo "LD: nuttx" -ifneq ($(CONFIG_ALLSYMS),y) +ifeq ($(CONFIG_ALLSYMS)$(CONFIG_MM_KASAN_GLOBAL),) $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ -o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \ $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) else - $(Q) # Link and generate default table - $(Q) $(if $(wildcard $(shell echo $(NUTTX))),,$(call LINK_ALLSYMS,$^)) - $(Q) # Extract all symbols - $(Q) $(call LINK_ALLSYMS, $^) - $(Q) # Extract again since the table offset may changed - $(Q) $(call LINK_ALLSYMS, $^) + $(Q) $(call LINK_ALLSYMS_KASAN) + $(Q) $(call LINK_ALLSYMS_KASAN) + $(Q) $(call LINK_ALLSYMS_KASAN) + $(Q) $(call LINK_ALLSYMS_KASAN) +endif +ifeq ($(CONFIG_MM_KASAN_GLOBAL),y) + $(Q) $(OBJCOPY) -R .kasan.global $(NUTTX) + $(Q) $(OBJCOPY) -R .kasan.unused $(NUTTX) endif ifneq ($(CONFIG_WINDOWS_NATIVE),y) $(Q) $(NM) $(NUTTX) | \ diff --git a/arch/arm64/src/Toolchain.defs b/arch/arm64/src/Toolchain.defs index 214b481d5e1f6..015622af49655 100644 --- a/arch/arm64/src/Toolchain.defs +++ b/arch/arm64/src/Toolchain.defs @@ -30,22 +30,20 @@ # reliable code generation. # -ifeq ($(CONFIG_ARCH_ARMV8A),y) - ARCHCPUFLAGS += -march=armv8-a -endif - -ifeq ($(CONFIG_ARCH_ARMV8R),y) - ARCHCPUFLAGS += -march=armv8-r -endif - ifeq ($(CONFIG_ARCH_CORTEX_A53),y) ARCHCPUFLAGS += -mcpu=cortex-a53 +else ifeq ($(CONFIG_ARCH_CORTEX_A55),y) + ARCHCPUFLAGS += -mcpu=cortex-a55 else ifeq ($(CONFIG_ARCH_CORTEX_A57),y) ARCHCPUFLAGS += -mcpu=cortex-a57 else ifeq ($(CONFIG_ARCH_CORTEX_A72),y) ARCHCPUFLAGS += -mcpu=cortex-a72 else ifeq ($(CONFIG_ARCH_CORTEX_R82),y) ARCHCPUFLAGS += -mcpu=cortex-r82 +else ifeq ($(CONFIG_ARCH_ARMV8A),y) + ARCHCPUFLAGS += -march=armv8-a +else ifeq ($(CONFIG_ARCH_ARMV8R),y) + ARCHCPUFLAGS += -march=armv8-r endif ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) @@ -84,6 +82,10 @@ ifeq ($(CONFIG_MM_KASAN_ALL),y) ARCHOPTIMIZATION += -fsanitize=kernel-address endif +ifeq ($(CONFIG_MM_KASAN_GLOBAL),y) + ARCHOPTIMIZATION += --param asan-globals=1 +endif + # Instrumentation options ifeq ($(CONFIG_ARCH_INSTRUMENT_ALL),y) @@ -96,7 +98,7 @@ ifeq ($(CONFIG_ARCH_FPU),y) endif ARCHCFLAGS += -fno-common -ARCHCXXFLAGS += -fno-common -nostdinc++ +ARCHCXXFLAGS += -fno-common ARCHCFLAGS += -Wall -Wstrict-prototypes -Wshadow -Wundef -Werror -Wno-attributes -Wno-unknown-pragmas ARCHCXXFLAGS += -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas @@ -105,6 +107,10 @@ ARCHCXXFLAGS += -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas # we can safely disregard warnings of the type "parameter passing for X changed in GCC 7.1." # Refer to : https://stackoverflow.com/questions/48149323/what-does-the-gcc-warning-project-parameter-passing-for-x-changed-in-gcc-7-1-m +ifneq ($(CONFIG_LIBCXXTOOLCHAIN),y) + ARCHCXXFLAGS += -nostdinc++ +endif + ifneq ($(CONFIG_ARCH_TOOLCHAIN_CLANG),y) ARCHCFLAGS += -Wno-psabi ARCHCXXFLAGS += -Wno-psabi diff --git a/arch/arm64/src/a64/a64_boot.c b/arch/arm64/src/a64/a64_boot.c index fc7c2eb15b2ec..fc9f21224324d 100644 --- a/arch/arm64/src/a64/a64_boot.c +++ b/arch/arm64/src/a64/a64_boot.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif diff --git a/arch/arm64/src/a64/a64_serial.c b/arch/arm64/src/a64/a64_serial.c index 03ee3b104f3f6..90ab577c1902b 100644 --- a/arch/arm64/src/a64/a64_serial.c +++ b/arch/arm64/src/a64/a64_serial.c @@ -965,7 +965,7 @@ static int a64_uart_init(uint32_t gating, uint32_t rst, pio_pinset_t tx, irqstate_t flags; int ret = OK; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); /* Enable clocking to UART */ @@ -991,7 +991,7 @@ static int a64_uart_init(uint32_t gating, uint32_t rst, pio_pinset_t tx, } } - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); return ret; }; diff --git a/arch/arm64/src/cmake/Toolchain.cmake b/arch/arm64/src/cmake/Toolchain.cmake new file mode 100644 index 0000000000000..233172e68bff9 --- /dev/null +++ b/arch/arm64/src/cmake/Toolchain.cmake @@ -0,0 +1,193 @@ +# ############################################################################## +# arch/arm64/src/cmake/Toolchain.cmake +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_VERSION 1) +set(CMAKE_C_COMPILER_FORCED TRUE) +set(CMAKE_CXX_COMPILER_FORCED TRUE) + +# Default toolchain +set(TOOLCHAIN_PREFIX aarch64-none-elf) + +set(CMAKE_LIBRARY_ARCHITECTURE ${TOOLCHAIN_PREFIX}) +set(CMAKE_C_COMPILER_TARGET ${TOOLCHAIN_PREFIX}) +set(CMAKE_CXX_COMPILER_TARGET ${TOOLCHAIN_PREFIX}) +set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) +set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}-gcc) +set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}-g++) +set(CMAKE_STRIP ${TOOLCHAIN_PREFIX}-strip --strl dunneeded) +set(CMAKE_OBJCOPY ${TOOLCHAIN_PREFIX}-objcopy) +set(CMAKE_OBJDUMP ${TOOLCHAIN_PREFIX}-objdump) +set(CMAKE_LINKER ${TOOLCHAIN_PREFIX}-ld) +set(CMAKE_LD ${TOOLCHAIN_PREFIX}-ld) +set(CMAKE_AR ${TOOLCHAIN_PREFIX}-ar) +set(CMAKE_NM ${TOOLCHAIN_PREFIX}-nm) +set(CMAKE_RANLIB ${TOOLCHAIN_PREFIX}-gcc-ranlib) +if(CONFIG_LTO_FULL) + add_compile_options(-flto) + if(CONFIG_ARM64_TOOLCHAIN_GNU_EABI) + set(CMAKE_LD ${TOOLCHAIN_PREFIX}-gcc) + set(CMAKE_AR ${TOOLCHAIN_PREFIX}-gcc-ar) + set(CMAKE_NM ${TOOLCHAIN_PREFIX}-gcc-nm) + add_compile_options(-fuse-linker-plugin) + add_compile_options(-fno-builtin) + endif() +endif() + +add_link_options(--entry=__start) +# override the ARCHIVE command +set(CMAKE_C_ARCHIVE_CREATE " rcs ") +set(CMAKE_CXX_ARCHIVE_CREATE " rcs ") +set(CMAKE_ASM_ARCHIVE_CREATE " rcs ") + +if(CONFIG_ARCH_ARMV8A) + add_compile_options(-march=armv8-a) +endif() + +if(CONFIG_ARCH_ARMV8R) + add_compile_options(-march=armv8-r) +endif() + +if(CONFIG_ARCH_CORTEX_A53) + add_compile_options(-mcpu=cortex-a53) +elseif(CONFIG_ARCH_CORTEX_A57) + add_compile_options(-mcpu=cortex-a57) +elseif(CONFIG_ARCH_CORTEX_A72) + add_compile_options(-mcpu=cortex-a72) +elseif(CONFIG_ARCH_CORTEX_R82) + add_compile_options(-mcpu=cortex-r82) +endif() + +if(CONFIG_DEBUG_CUSTOMOPT) + add_compile_options(${CONFIG_DEBUG_OPTLEVEL}) +elseif(CONFIG_DEBUG_FULLOPT) + add_compile_options(-Os) +endif() + +if(NOT CONFIG_DEBUG_NOOPT) + add_compile_options(-fno-strict-aliasing) +endif() + +if(CONFIG_FRAME_POINTER) + add_compile_options(-fno-omit-frame-pointer -fno-optimize-sibling-calls) +else() + add_compile_options(-fomit-frame-pointer) +endif() + +if(CONFIG_STACK_CANARIES) + add_compile_options(-fstack-protector-all) +endif() + +if(CONFIG_ARCH_COVERAGE_ALL) + add_compile_options(-fprofile-generate -ftest-coverage) +endif() + +if(CONFIG_MM_UBSAN_ALL) + add_compile_options(${CONFIG_MM_UBSAN_OPTION}) +endif() + +if(CONFIG_MM_UBSAN_TRAP_ON_ERROR) + add_compile_options(-fsanitize-undefined-trap-on-error) +endif() + +if(CONFIG_MM_KASAN_ALL) + add_compile_options(-fsanitize=kernel-address) +endif() + +if(CONFIG_ARCH_INSTRUMENT_ALL) + add_compile_options(-finstrument-functions) +endif() + +if(CONFIG_ARCH_FPU) + add_compile_options(-D_LDBL_EQ_DBL) +endif() + +set(ARCHCFLAGS + "-Wstrict-prototypes -fno-common -Wall -Wshadow -Werror -Wundef -Wno-attributes -Wno-unknown-pragmas" +) +set(ARCHCXXFLAGS + "-fno-common -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas") + +if(NOT CONFIG_LIBCXXTOOLCHAIN) + set(ARCHCXXFLAGS "${ARCHCXXFLAGS} -nostdinc++") +endif() + +if(NOT ${CONFIG_ARCH_TOOLCHAIN_CLANG}) + string(APPEND ARCHCFLAGS " -Wno-psabi") + string(APPEND ARCHCXXFLAGS " -Wno-psabi") +endif() + +if(${CONFIG_CXX_STANDARD}) + string(APPEND ARCHCXXFLAGS " -std=${CONFIG_CXX_STANDARD}") +endif() + +if(NOT ${CONFIG_CXX_EXCEPTION}) + string(APPEND ARCHCXXFLAGS " -fno-exceptions -fcheck-new") +endif() + +if(NOT ${CONFIG_CXX_RTTI}) + string(APPEND ARCHCXXFLAGS " -fno-rtti") +endif() + +add_link_options(-nostdlib) + +if(CONFIG_DEBUG_OPT_UNUSED_SECTIONS) + add_link_options(-Wl,--gc-sections) + add_compile_options(-ffunction-sections -fdata-sections) +endif() + +if(CONFIG_DEBUG_LINK_MAP) + add_link_options(-Wl,-cref,-Map=nuttx.map) +endif() + +if(CONFIG_DEBUG_SYMBOLS) + add_compile_options(-g) +endif() + +if(CONFIG_ARCH_TOOLCHAIN_GNU) + if(NOT GCCVER) + + execute_process(COMMAND ${CMAKE_C_COMPILER} --version + OUTPUT_VARIABLE GCC_VERSION_INFO) + + string(REGEX MATCH "[0-9]+\\.[0-9]+" GCC_VERSION ${GCC_VERSION_INFO}) + string(REGEX REPLACE "\\..*" "" GCCVER ${GCC_VERSION}) + + endif() + + if(GCCVER EQUAL 12) + add_link_options(-Wl,--no-warn-rwx-segments) + endif() +endif() + +if(NOT "${CMAKE_C_FLAGS}" STREQUAL "") + string(REGEX MATCH "${ARCHCFLAGS}" EXISTS_FLAGS "${CMAKE_C_FLAGS}") +endif() +if(NOT EXISTS_FLAGS) + set(CMAKE_ASM_FLAGS + "${CMAKE_ASM_FLAGS} ${ARCHCFLAGS}" + CACHE STRING "" FORCE) + set(CMAKE_C_FLAGS + "${CMAKE_C_FLAGS} ${ARCHCFLAGS}" + CACHE STRING "" FORCE) + set(CMAKE_CXX_FLAGS + "${CMAKE_CXX_FLAGS} ${ARCHCXXFLAGS}" + CACHE STRING "" FORCE) +endif() diff --git a/arch/arm64/src/cmake/platform.cmake b/arch/arm64/src/cmake/platform.cmake new file mode 100644 index 0000000000000..c8b3e61a95de8 --- /dev/null +++ b/arch/arm64/src/cmake/platform.cmake @@ -0,0 +1,54 @@ +# ############################################################################## +# arch/arm64/src/cmake/platform.cmake +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## +get_directory_property(NUTTX_EXTRA_FLAGS DIRECTORY ${CMAKE_SOURCE_DIR} + COMPILE_OPTIONS) +execute_process( + COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} ${NUTTX_EXTRA_FLAGS} + --print-libgcc-file-name + OUTPUT_STRIP_TRAILING_WHITESPACE + OUTPUT_VARIABLE extra_library) +list(APPEND EXTRA_LIB ${extra_library}) +if(NOT CONFIG_LIBM) + execute_process( + COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} ${NUTTX_EXTRA_FLAGS} + --print-file-name=libm.a + OUTPUT_STRIP_TRAILING_WHITESPACE + OUTPUT_VARIABLE extra_library) + list(APPEND EXTRA_LIB ${extra_library}) +endif() +if(CONFIG_LIBSUPCXX) + execute_process( + COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} ${NUTTX_EXTRA_FLAGS} + --print-file-name=libsupc++.a + OUTPUT_STRIP_TRAILING_WHITESPACE + OUTPUT_VARIABLE extra_library) + list(APPEND EXTRA_LIB ${extra_library}) +endif() +if(CONFIG_ARCH_COVERAGE) + execute_process( + COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} ${NUTTX_EXTRA_FLAGS} + --print-file-name=libgcov.a + OUTPUT_STRIP_TRAILING_WHITESPACE + OUTPUT_VARIABLE extra_library) + list(APPEND EXTRA_LIB ${extra_library}) +endif() +set_property(GLOBAL APPEND PROPERTY NUTTX_EXTRA_LIBRARIES ${EXTRA_LIB}) +separate_arguments(CMAKE_C_FLAG_ARGS NATIVE_COMMAND ${CMAKE_C_FLAGS}) +set(PREPROCES ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} -E -P -x c) diff --git a/arch/arm64/src/common/CMakeLists.txt b/arch/arm64/src/common/CMakeLists.txt new file mode 100644 index 0000000000000..3358c52b7b483 --- /dev/null +++ b/arch/arm64/src/common/CMakeLists.txt @@ -0,0 +1,117 @@ +# ############################################################################## +# arch/arm64/src/common/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS arm64_head.S) + +# TODO: support kernel startup obj ctr0 + +list(APPEND SRCS arm64_vector_table.S arm64_vectors.S arm64_smccc.S) +list(APPEND SRCS arm64_cpu_idle.S arm64_fork_func.S) + +if(CONFIG_ARCH_HAVE_TESTSET) + list(APPEND SRCS arm64_testset.S) +endif() + +# Common C source files ( OS call up_xxx) +list(APPEND SRCS arm64_initialize.c arm64_initialstate.c arm64_boot.c) +list(APPEND SRCS arm64_nputs.c arm64_idle.c arm64_copystate.c + arm64_createstack.c) +list(APPEND SRCS arm64_releasestack.c arm64_stackframe.c arm64_usestack.c) +list(APPEND SRCS arm64_exit.c arm64_fork.c arm64_switchcontext.c) +list(APPEND SRCS arm64_schedulesigaction.c arm64_sigdeliver.c) +list(APPEND SRCS arm64_getintstack.c arm64_registerdump.c) +list(APPEND SRCS arm64_perf.c arm64_tcbinfo.c) + +# Common C source files ( hardware BSP ) +list(APPEND SRCS arm64_arch_timer.c arm64_cache.c) +list(APPEND SRCS arm64_doirq.c arm64_fatal.c) +list(APPEND SRCS arm64_syscall.c) + +# Use common heap allocation for now (may need to be customized later) +list(APPEND SRCS arm64_allocateheap.c) + +if(CONFIG_ARM_GIC_VERSION EQUAL 3) + list(APPEND SRCS arm64_gicv3.c) +endif() + +if(CONFIG_ARM_GIC_VERSION EQUAL 2) + list(APPEND SRCS arm64_gicv2.c) +endif() + +if(CONFIG_ARCH_HAVE_MMU) + list(APPEND SRCS arm64_mmu.c) +endif() + +if(CONFIG_ARCH_HAVE_MPU) + list(APPEND SRCS arm64_mpu.c) +endif() + +if(CONFIG_ARCH_HAVE_PSCI) + list(APPEND SRCS arm64_cpu_psci.c arm64_systemreset.c) +endif() + +if(CONFIG_SMP) + list(APPEND SRCS arm64_cpuidlestack.c arm64_cpustart.c) + list(APPEND SRCS arm64_cpupause.c) +endif() + +if(CONFIG_BUILD_KERNEL) + list(APPEND SRCS arm64_task_start.c arm64_pthread_start.c + arm64_signal_dispatch.c) +endif() + +if(CONFIG_ARCH_ADDRENV) + list(APPEND SRCS arm64_addrenv.c arm64_addrenv_utils.c arm64_pgalloc.c) + if(CONFIG_ARCH_STACK_DYNAMIC) + list(APPEND SRCS arm64_addrenv_ustack.c) + endif() + if(CONFIG_ARCH_KERNEL_STACK) + list(APPEND SRCS arm64_addrenv_kstack.c) + endif() + if(CONFIG_ARCH_VMA_MAPPING) + list(APPEND SRCS arm64_addrenv_shm.c) + endif() +endif() + +if(CONFIG_MM_PGALLOC) + list(APPEND SRCS arm64_physpgaddr.c) + if(CONFIG_ARCH_PGPOOL_MAPPING) + list(APPEND SRCS arm64_virtpgaddr.c) + endif() +endif() + +if(CONFIG_ARCH_FPU) + list(APPEND SRCS arm64_fpu.c) + list(APPEND SRCS arm64_fpu_func.S) +endif() + +if(CONFIG_STACK_COLORATION) + list(APPEND SRCS arm64_checkstack.c) +endif() + +if(CONFIG_SCHED_BACKTRACE) + list(APPEND SRCS arm64_backtrace.c) +endif() + +if(CONFIG_ARM64_SEMIHOSTING_HOSTFS) + list(APPEND SRCS arm64_hostfs.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm64/src/common/Make.defs b/arch/arm64/src/common/Make.defs index 9576ed59bb275..00cb0b7099664 100644 --- a/arch/arm64/src/common/Make.defs +++ b/arch/arm64/src/common/Make.defs @@ -45,7 +45,7 @@ endif CMN_CSRCS = arm64_initialize.c arm64_initialstate.c arm64_boot.c CMN_CSRCS += arm64_nputs.c arm64_idle.c arm64_copystate.c arm64_createstack.c CMN_CSRCS += arm64_releasestack.c arm64_stackframe.c arm64_usestack.c -CMN_CSRCS += arm64_task_sched.c arm64_exit.c arm64_fork.c arm64_switchcontext.c +CMN_CSRCS += arm64_exit.c arm64_fork.c arm64_switchcontext.c CMN_CSRCS += arm64_schedulesigaction.c arm64_sigdeliver.c CMN_CSRCS += arm64_getintstack.c arm64_registerdump.c CMN_CSRCS += arm64_perf.c arm64_tcbinfo.c @@ -54,6 +54,7 @@ CMN_CSRCS += arm64_perf.c arm64_tcbinfo.c CMN_CSRCS += arm64_arch_timer.c arm64_cache.c CMN_CSRCS += arm64_doirq.c arm64_fatal.c CMN_CSRCS += arm64_syscall.c +CMN_CSRCS += arm64_modifyreg8.c arm64_modifyreg16.c arm64_modifyreg32.c # Use common heap allocation for now (may need to be customized later) CMN_CSRCS += arm64_allocateheap.c diff --git a/arch/arm64/src/common/arm64_arch.h b/arch/arm64/src/common/arm64_arch.h index 789ebebff0c1c..d3293653035f2 100644 --- a/arch/arm64/src/common/arm64_arch.h +++ b/arch/arm64/src/common/arm64_arch.h @@ -32,6 +32,7 @@ */ #ifndef __ASSEMBLY__ #include + #include #endif #include @@ -118,6 +119,8 @@ #define SPSR_MODE_EL1H (0x5) #define SPSR_MODE_EL2T (0x8) #define SPSR_MODE_EL2H (0x9) +#define SPSR_MODE_EL3T (0xc) +#define SPSR_MODE_EL3H (0xd) #define SPSR_MODE_MASK (0xf) /* CurrentEL: Current Exception Level */ @@ -143,8 +146,6 @@ * Pre-processor Definitions ****************************************************************************/ -#define STRINGIFY(x) #x - #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) /* MPIDR_EL1, Multiprocessor Affinity Register */ @@ -479,10 +480,18 @@ static inline void arch_nop(void) ::: "memory"); \ }) +/* Non-atomic modification of registers */ + #define modreg8(v,m,a) putreg8((getreg8(a) & ~(m)) | ((v) & (m)), (a)) #define modreg16(v,m,a) putreg16((getreg16(a) & ~(m)) | ((v) & (m)), (a)) #define modreg32(v,m,a) putreg32((getreg32(a) & ~(m)) | ((v) & (m)), (a)) +/* Atomic modification of registers */ + +void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits); +void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits); +void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits); + /**************************************************************************** * Name: * arch_get_exception_depth diff --git a/arch/arm64/src/common/arm64_backtrace.c b/arch/arm64/src/common/arm64_backtrace.c index 3ff4e2d1b0c1c..a0c5b67af50f4 100644 --- a/arch/arm64/src/common/arm64_backtrace.c +++ b/arch/arm64/src/common/arm64_backtrace.c @@ -109,10 +109,6 @@ int up_backtrace(struct tcb_s *tcb, { struct tcb_s *rtcb = (struct tcb_s *)arch_get_current_tcb(); struct regs_context * p_regs; - -#if CONFIG_ARCH_INTERRUPTSTACK > 7 - void *istacklimit; -#endif irqstate_t flags; int ret; @@ -131,13 +127,9 @@ int up_backtrace(struct tcb_s *tcb, if (up_interrupt_context()) { #if CONFIG_ARCH_INTERRUPTSTACK > 7 -# ifdef CONFIG_SMP - istacklimit = (void *)arm64_intstack_top(); -# else - istacklimit = g_interrupt_stack + INTSTACK_SIZE; -# endif /* CONFIG_SMP */ - ret = backtrace(istacklimit - (CONFIG_ARCH_INTERRUPTSTACK & ~15), - istacklimit, + void *istackbase = (void *)up_get_intstackbase(up_cpu_index()); + ret = backtrace(istackbase, + istackbase + INTSTACK_SIZE, (void *)__builtin_frame_address(0), NULL, buffer, size, &skip); #else diff --git a/arch/arm64/src/common/arm64_boot.c b/arch/arm64/src/common/arm64_boot.c index 42df595307555..a82028857c370 100644 --- a/arch/arm64/src/common/arm64_boot.c +++ b/arch/arm64/src/common/arm64_boot.c @@ -78,6 +78,11 @@ void arm64_boot_el3_init(void) reg = 0U; /* Reset */ reg |= SCR_NS_BIT; /* EL2 / EL3 non-secure */ reg |= (SCR_RES1 | /* RES1 */ +#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3 + SCR_IRQ_BIT | /* Route IRQs to EL3 */ + SCR_FIQ_BIT | /* Route FIQs to EL3 */ + SCR_EA_BIT | /* Route EAs to EL3 */ +#endif SCR_RW_BIT | /* EL2 execution state is AArch64 */ SCR_ST_BIT | /* Do not trap EL1 accesses to timer */ SCR_HCE_BIT | /* Do not trap HVC */ diff --git a/arch/arm64/src/common/arm64_checkstack.c b/arch/arm64/src/common/arm64_checkstack.c index fac5d6433bb5f..8a39f1e199b03 100644 --- a/arch/arm64/src/common/arm64_checkstack.c +++ b/arch/arm64/src/common/arm64_checkstack.c @@ -202,9 +202,9 @@ size_t up_check_tcbstack(struct tcb_s *tcb) } #if CONFIG_ARCH_INTERRUPTSTACK > 7 -size_t up_check_intstack(void) +size_t up_check_intstack(int cpu) { - return arm64_stack_check((void *)up_get_intstackbase(), + return arm64_stack_check((void *)up_get_intstackbase(cpu), STACK_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK)); } #endif diff --git a/arch/arm64/src/common/arm64_copystate.c b/arch/arm64/src/common/arm64_copystate.c index 47ddd39568aa7..8f3716f915e20 100644 --- a/arch/arm64/src/common/arm64_copystate.c +++ b/arch/arm64/src/common/arm64_copystate.c @@ -60,13 +60,13 @@ int arch_save_fpucontext(void *saveregs) { irqstate_t flags; - uint64_t *p_save; + uintptr_t p_save; /* Take a snapshot of the thread context right now */ flags = enter_critical_section(); - p_save = saveregs + XCPTCONTEXT_GP_SIZE; + p_save = (uintptr_t)saveregs + XCPTCONTEXT_GP_SIZE; arm64_fpu_save((struct fpu_reg *)p_save); ARM64_DSB(); diff --git a/arch/arm64/src/common/arm64_cpupause.c b/arch/arm64/src/common/arm64_cpupause.c index 0d7acefee8001..943b56c42181e 100644 --- a/arch/arm64/src/common/arm64_cpupause.c +++ b/arch/arm64/src/common/arm64_cpupause.c @@ -84,7 +84,7 @@ bool up_cpu_pausereq(int cpu) } /**************************************************************************** - * Name: up_cpu_paused + * Name: up_cpu_paused_save * * Description: * Handle a pause request from another CPU. Normally, this logic is @@ -93,16 +93,8 @@ bool up_cpu_pausereq(int cpu) * pause operation in other contexts where the interrupt cannot be taken * in order to avoid deadlocks. * - * This function performs the following operations: - * - * 1. It saves the current task state at the head of the current assigned - * task list. - * 2. It waits on a spinlock, then - * 3. Returns from interrupt, restoring the state of the new task at the - * head of the ready to run list. - * * Input Parameters: - * cpu - The index of the CPU to be paused + * None * * Returned Value: * On success, OK is returned. Otherwise, a negated errno value indicating @@ -110,7 +102,7 @@ bool up_cpu_pausereq(int cpu) * ****************************************************************************/ -int up_cpu_paused(int cpu) +int up_cpu_paused_save(void) { struct tcb_s *tcb = this_task(); @@ -130,6 +122,38 @@ int up_cpu_paused(int cpu) arm64_savestate(tcb->xcp.regs); + return OK; +} + +/**************************************************************************** + * Name: up_cpu_paused + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. + * + * This function performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. + * + * Input Parameters: + * cpu - The index of the CPU to be paused + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused(int cpu) +{ /* Release the g_cpu_paused spinlock to synchronize with the * requesting CPU. */ @@ -150,7 +174,31 @@ int up_cpu_paused(int cpu) * the (new) head of the assigned task list. */ - tcb = this_task(); + spin_unlock(&g_cpu_wait[cpu]); + spin_unlock(&g_cpu_resumed[cpu]); + + return OK; +} + +/**************************************************************************** + * Name: up_cpu_paused_restore + * + * Description: + * Restore the state of the CPU after it was paused via up_cpu_pause(), + * and resume normal tasking. + * + * Input Parameters: + * None + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused_restore(void) +{ + struct tcb_s *tcb = this_task(); #ifdef CONFIG_SCHED_INSTRUMENTATION /* Notify that we have resumed */ @@ -167,8 +215,6 @@ int up_cpu_paused(int cpu) */ arm64_restorestate(tcb->xcp.regs); - spin_unlock(&g_cpu_wait[cpu]); - spin_unlock(&g_cpu_resumed[cpu]); return OK; } diff --git a/arch/arm64/src/common/arm64_fork.c b/arch/arm64/src/common/arm64_fork.c index aea3d570442d8..8398058b61467 100644 --- a/arch/arm64/src/common/arm64_fork.c +++ b/arch/arm64/src/common/arm64_fork.c @@ -225,7 +225,11 @@ pid_t arm64_fork(const struct fork_s *context) pforkctx->regs[REG_X28] = context->regs[FORK_REG_X28]; pforkctx->regs[REG_X29] = newfp; +#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3 + pforkctx->spsr = SPSR_MODE_EL3H; +#else pforkctx->spsr = SPSR_MODE_EL1H; +#endif #ifdef CONFIG_SUPPRESS_INTERRUPTS pforkctx->spsr |= (DAIF_IRQ_BIT | DAIF_FIQ_BIT); diff --git a/arch/arm64/src/common/arm64_fpu.c b/arch/arm64/src/common/arm64_fpu.c index c8202b57a6243..69b458a9c524f 100644 --- a/arch/arm64/src/common/arm64_fpu.c +++ b/arch/arm64/src/common/arm64_fpu.c @@ -430,8 +430,10 @@ void arm64_fpu_disable(void) bool up_fpucmp(const void *saveregs1, const void *saveregs2) { - const uint64_t *regs1 = saveregs1 + XCPTCONTEXT_GP_SIZE; - const uint64_t *regs2 = saveregs2 + XCPTCONTEXT_GP_SIZE; + const uint64_t *regs1 = (uint64_t *)((uintptr_t)saveregs1 + + XCPTCONTEXT_GP_SIZE); + const uint64_t *regs2 = (uint64_t *)((uintptr_t)saveregs2 + + XCPTCONTEXT_GP_SIZE); /* Only compare callee-saved registers, caller-saved registers do not * need to be preserved. diff --git a/arch/arm64/src/common/arm64_getintstack.c b/arch/arm64/src/common/arm64_getintstack.c index 8da53fc19e6bb..2ef7d227f805f 100644 --- a/arch/arm64/src/common/arm64_getintstack.c +++ b/arch/arm64/src/common/arm64_getintstack.c @@ -36,13 +36,9 @@ * Name: up_get_intstackbase ****************************************************************************/ -#if CONFIG_ARCH_INTERRUPTSTACK > 7 -uintptr_t up_get_intstackbase(void) +#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 7 +uintptr_t up_get_intstackbase(int cpu) { -#ifdef CONFIG_SMP - return arm64_intstack_alloc(); -#else return (uintptr_t)g_interrupt_stack; -#endif } #endif diff --git a/arch/arm64/src/common/arm64_gicv2.c b/arch/arm64/src/common/arm64_gicv2.c index 11e695c428d83..3daa667263e43 100644 --- a/arch/arm64/src/common/arm64_gicv2.c +++ b/arch/arm64/src/common/arm64_gicv2.c @@ -647,7 +647,7 @@ static inline unsigned int arm_gic_nlines(void) return (field + 1) << 5; } -#ifdef CONFIG_ARCH_HAVE_TRUSTZONE +#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) /**************************************************************************** * Name: up_set_secure_irq * diff --git a/arch/arm64/src/common/arm64_gicv3.c b/arch/arm64/src/common/arm64_gicv3.c index f040b37aee803..9e2ab777a475b 100644 --- a/arch/arm64/src/common/arm64_gicv3.c +++ b/arch/arm64/src/common/arm64_gicv3.c @@ -71,6 +71,9 @@ #define SMP_FUNC_CALL_IPI GIC_IRQ_SGI3 +#define PENDING_GRP1NS_INTID 1021 +#define SPURIOUS_INT 1023 + /*************************************************************************** * Private Data ***************************************************************************/ @@ -361,7 +364,7 @@ static int arm64_gic_send_sgi(unsigned int sgi_id, uint64_t target_aff, unsigned long base; base = gic_get_rdist() + GICR_SGI_BASE_OFF; - assert(GIC_IS_SGI(sgi_id)); + ASSERT(GIC_IS_SGI(sgi_id)); /* Extract affinity fields from target */ @@ -505,7 +508,7 @@ static void gicv3_cpuif_init(void) write_sysreg(icc_sre, ICC_SRE_EL1); icc_sre = read_sysreg(ICC_SRE_EL1); - assert(icc_sre & ICC_SRE_ELX_SRE_BIT); + ASSERT(icc_sre & ICC_SRE_ELX_SRE_BIT); } write_sysreg(GIC_IDLE_PRIO, ICC_PMR_EL1); @@ -765,7 +768,7 @@ uint64_t * arm64_decodeirq(uint64_t * regs) * interrupt. */ - DEBUGASSERT(irq < NR_IRQS || irq == 1023); + DEBUGASSERT(irq < NR_IRQS || irq == SPURIOUS_INT); if (irq < NR_IRQS) { /* Dispatch the interrupt */ @@ -789,11 +792,33 @@ uint64_t * arm64_decodefiq(uint64_t * regs) irq = arm64_gic_get_active_fiq(); +#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3 + /* FIQ is group0 interrupt */ + + if (irq == PENDING_GRP1NS_INTID) + { + /* irq 1021 indicates that the irq being acked is expected at EL1/EL2. + * However, EL3 has no interrupts, only FIQs, see: + * 'Arm® Generic Interrupt Controller, Architecture Specification GIC + * architecture version 3 and version 4' Arm IHI 0069G (ID011821) + * 'Table 4-3 Interrupt signals for two Security states when EL3 is + * using AArch64 state' + * + * Thus we know there's an interrupt so let's handle it from group1. + */ + + regs = arm64_decodeirq(regs); + arm64_gic_eoi_fiq(irq); + + return regs; + } +#endif + /* Ignore spurions IRQs. ICCIAR will report 1023 if there is no pending * interrupt. */ - DEBUGASSERT(irq < NR_IRQS || irq == 1023); + DEBUGASSERT(irq < NR_IRQS || irq == SPURIOUS_INT); if (irq < NR_IRQS) { /* Dispatch the interrupt */ diff --git a/arch/arm64/src/common/arm64_head.S b/arch/arm64/src/common/arm64_head.S index 18ea5c97ea72f..55a89ec06eaf4 100644 --- a/arch/arm64/src/common/arm64_head.S +++ b/arch/arm64/src/common/arm64_head.S @@ -89,6 +89,8 @@ label: .asciz msg; \ * This must be the very first address in the loaded image. * It should be loaded at any 4K-aligned address. */ + + .section .start, "ax" .globl __start; __start: @@ -233,6 +235,15 @@ switch_el: bl arm64_boot_el3_init +#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3 + msr SPSel, #1 + + /* Set SP_EL3 (with SPSel = 1) */ + + mov sp, x24 + b el3_boot +#endif + /* Get next EL */ adr x0, switch_el @@ -266,6 +277,8 @@ switch_el: msr SPSel, #1 msr DAIFClr, #(DAIFCLR_ABT_BIT) + +el3_boot: isb jump_to_c_entry: diff --git a/arch/arm64/src/common/arm64_initialize.c b/arch/arm64/src/common/arm64_initialize.c index 3cb4aaa325159..acb3891286fa2 100644 --- a/arch/arm64/src/common/arm64_initialize.c +++ b/arch/arm64/src/common/arm64_initialize.c @@ -51,7 +51,7 @@ ****************************************************************************/ /* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt + * register storage structure. It is non-NULL only during interrupt * processing. Access to g_current_regs[] must be through the macro * CURRENT_REGS for portability. */ @@ -94,7 +94,7 @@ INIT_STACK_DEFINE(g_interrupt_fiq_stack, INTSTACK_SIZE); ****************************************************************************/ /**************************************************************************** - * Name: arm64_intstack_alloc + * Name: up_get_intstackbase * * Description: * Return a pointer to the "alloc" the correct interrupt stack allocation @@ -103,25 +103,10 @@ INIT_STACK_DEFINE(g_interrupt_fiq_stack, INTSTACK_SIZE); ****************************************************************************/ #ifdef CONFIG_SMP -uintptr_t arm64_intstack_alloc(void) +uintptr_t up_get_intstackbase(int cpu) { - return (uintptr_t)(g_interrupt_stacks[up_cpu_index()]); + return (uintptr_t)(g_interrupt_stacks[cpu]); } - -/**************************************************************************** - * Name: arm64_intstack_top - * - * Description: - * Return a pointer to the top the correct interrupt stack allocation - * for the current CPU. - * - ****************************************************************************/ - -uintptr_t arm64_intstack_top(void) -{ - return (uintptr_t)(g_interrupt_stacks[up_cpu_index()] + INTSTACK_SIZE); -} - #endif /**************************************************************************** @@ -137,11 +122,15 @@ uintptr_t arm64_intstack_top(void) static void up_color_intstack(void) { #ifdef CONFIG_SMP - void *ptr = (void *)g_interrupt_stacks[up_cpu_index()]; + int cpu; + + for (cpu = 0; cpu < CONFIG_SMP_NCPUS; cpu++) + { + arm64_stack_color((void *)up_get_intstackbase(cpu), INTSTACK_SIZE); + } #else - void *ptr = (void *)g_interrupt_stack; + arm64_stack_color((void *)g_interrupt_stack, INTSTACK_SIZE); #endif - arm64_stack_color(ptr, INTSTACK_SIZE); } #else # define up_color_intstack() diff --git a/arch/arm64/src/common/arm64_initialstate.c b/arch/arm64/src/common/arm64_initialstate.c index 0dc836e7a4725..1e4d776004e20 100644 --- a/arch/arm64/src/common/arm64_initialstate.c +++ b/arch/arm64/src/common/arm64_initialstate.c @@ -56,7 +56,7 @@ void arm64_new_task(struct tcb_s * tcb) { - char *stack_ptr = tcb->stack_base_ptr + tcb->adj_stack_size; + uint64_t stack_ptr = (uintptr_t)tcb->stack_base_ptr + tcb->adj_stack_size; struct regs_context *pinitctx; #ifdef CONFIG_ARCH_FPU @@ -67,16 +67,20 @@ void arm64_new_task(struct tcb_s * tcb) /* set fpu context */ arm64_init_fpu(tcb); - stack_ptr = (char *)pfpuctx; + stack_ptr = (uintptr_t)pfpuctx; #endif pinitctx = STACK_PTR_TO_FRAME(struct regs_context, stack_ptr); memset(pinitctx, 0, sizeof(struct regs_context)); pinitctx->elr = (uint64_t)tcb->start; - /* Keep using SP_EL1 */ + /* Keep using SP_EL1 or SP_EL3 */ +#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3 + pinitctx->spsr = SPSR_MODE_EL3H; +#else pinitctx->spsr = SPSR_MODE_EL1H; +#endif #ifdef CONFIG_SUPPRESS_INTERRUPTS pinitctx->spsr |= (DAIF_IRQ_BIT | DAIF_FIQ_BIT); diff --git a/arch/arm64/src/common/arm64_internal.h b/arch/arm64/src/common/arm64_internal.h index a1a98d456fab3..b05ff81044a6a 100644 --- a/arch/arm64/src/common/arm64_internal.h +++ b/arch/arm64/src/common/arm64_internal.h @@ -32,6 +32,7 @@ # include # include # include +# include #endif #include "arm64_arch.h" @@ -116,6 +117,18 @@ # define SMP_STACK_WORDS (SMP_STACK_SIZE >> 2) #endif +/* Context switching */ + +#define arm64_fullcontextrestore(restoreregs) \ + do \ + { \ + sys_call1(SYS_restore_context, (uintptr_t)restoreregs); \ + } \ + while (1) + +#define arm64_switchcontext(saveregs, restoreregs) \ + sys_call2(SYS_switch_context, (uintptr_t)saveregs, (uintptr_t)restoreregs) + /**************************************************************************** * Public Types ****************************************************************************/ @@ -167,9 +180,6 @@ INIT_STACK_ARRAY_DEFINE_EXTERN(g_interrupt_stacks, CONFIG_SMP_NCPUS, INIT_STACK_ARRAY_DEFINE_EXTERN(g_interrupt_fiq_stacks, CONFIG_SMP_NCPUS, INTSTACK_SIZE); #endif - -uintptr_t arm64_intstack_alloc(void); -uintptr_t arm64_intstack_top(void); #else /* idle thread stack for primary core */ @@ -270,11 +280,6 @@ int arm64_psci_init(const char *method); void __start(void); void arm64_secondary_start(void); -/* Context switching */ - -void arm64_fullcontextrestore(uint64_t *restoreregs) noreturn_function; -void arm64_switchcontext(uint64_t **saveregs, uint64_t *restoreregs); - /* Signal handling **********************************************************/ void arm64_sigdeliver(void); @@ -299,15 +304,19 @@ uint64_t *arm64_doirq(int irq, uint64_t *regs); /* Paging support */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING void arm64_pginitialize(void); -#else /* CONFIG_PAGING */ +#else /* CONFIG_LEGACY_PAGING */ # define arm64_pginitialize() -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ uint64_t * arm64_syscall_switch(uint64_t *regs); int arm64_syscall(uint64_t *regs); +/* Low level serial output **************************************************/ + +void arm64_lowputc(char ch); + #ifdef USE_SERIALDRIVER /**************************************************************************** * Name: arm64_serialinit diff --git a/arch/arm64/src/common/arm64_mmu.c b/arch/arm64/src/common/arm64_mmu.c index d4b949bbf9804..e16ee23b6d328 100644 --- a/arch/arm64/src/common/arm64_mmu.c +++ b/arch/arm64/src/common/arm64_mmu.c @@ -523,6 +523,40 @@ static void setup_page_tables(void) } } +#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3 +static void enable_mmu_el3(unsigned int flags) +{ + uint64_t value; + UNUSED(flags); + + /* Set MAIR, TCR and TBBR registers */ + + write_sysreg(MEMORY_ATTRIBUTES, mair_el3); + write_sysreg(get_tcr(3), tcr_el3); + write_sysreg((uint64_t)base_xlat_table, ttbr0_el3); + + /* Ensure these changes are seen before MMU is enabled */ + + ARM64_DSB(); + ARM64_ISB(); + + /* Enable the MMU and data cache */ + + value = read_sysreg(sctlr_el3); + write_sysreg((value | SCTLR_M_BIT +#ifndef CONFIG_ARM64_DCACHE_DISABLE + | SCTLR_C_BIT +#endif + ), sctlr_el3); + + /* Ensure the MMU enable takes effect immediately */ + + ARM64_ISB(); +#ifdef CONFIG_MMU_DEBUG + sinfo("MMU enabled with dcache\n"); +#endif +} +#else static void enable_mmu_el1(unsigned int flags) { uint64_t value; @@ -532,10 +566,11 @@ static void enable_mmu_el1(unsigned int flags) write_sysreg(MEMORY_ATTRIBUTES, mair_el1); write_sysreg(get_tcr(1), tcr_el1); - write_sysreg(((uint64_t)base_xlat_table), ttbr0_el1); + write_sysreg((uint64_t)base_xlat_table, ttbr0_el1); /* Ensure these changes are seen before MMU is enabled */ + ARM64_DSB(); ARM64_ISB(); /* Enable the MMU and data cache */ @@ -554,6 +589,7 @@ static void enable_mmu_el1(unsigned int flags) sinfo("MMU enabled with dcache\n"); #endif } +#endif /*************************************************************************** * Public Functions @@ -587,19 +623,30 @@ int arm64_mmu_set_memregion(const struct arm_mmu_region *region) int arm64_mmu_init(bool is_primary_core) { uint64_t val; + uint64_t el; unsigned flags = 0; - /* Current MMU code supports only EL1 */ + /* Current MMU code supports EL1 and EL3 */ - __asm__ volatile ("mrs %0, CurrentEL" : "=r" (val)); + __asm__ volatile ("mrs %0, CurrentEL" : "=r" (el)); - __MMU_ASSERT(GET_EL(val) == MODE_EL1, +#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3 + __MMU_ASSERT(GET_EL(el) == MODE_EL3, + "Exception level not EL3, MMU not enabled!\n"); + + /* Ensure that MMU is already not enabled */ + + __asm__ volatile ("mrs %0, sctlr_el3" : "=r" (val)); + __MMU_ASSERT((val & SCTLR_M_BIT) == 0, "MMU is already enabled\n"); +#else + __MMU_ASSERT(GET_EL(el) == MODE_EL1, "Exception level not EL1, MMU not enabled!\n"); /* Ensure that MMU is already not enabled */ __asm__ volatile ("mrs %0, sctlr_el1" : "=r" (val)); __MMU_ASSERT((val & SCTLR_M_BIT) == 0, "MMU is already enabled\n"); +#endif #ifdef CONFIG_MMU_DEBUG sinfo("xlat tables:\n"); @@ -616,9 +663,13 @@ int arm64_mmu_init(bool is_primary_core) setup_page_tables(); } - /* currently only EL1 is supported */ + /* Currently EL1 and EL3 are supported */ +#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3 + enable_mmu_el3(flags); +#else enable_mmu_el1(flags); +#endif return 0; } diff --git a/arch/arm64/src/common/arm64_modifyreg16.c b/arch/arm64/src/common/arm64_modifyreg16.c new file mode 100644 index 0000000000000..3c1fd2e498fad --- /dev/null +++ b/arch/arm64/src/common/arm64_modifyreg16.c @@ -0,0 +1,57 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_modifyreg16.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "arm64_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: modifyreg16 + * + * Description: + * Atomically modify the specified bits in a memory mapped register + * + ****************************************************************************/ + +void modifyreg16(unsigned int addr, uint16_t clearbits, uint16_t setbits) +{ + irqstate_t flags; + uint16_t regval; + + flags = spin_lock_irqsave(NULL); + regval = getreg16(addr); + regval &= ~clearbits; + regval |= setbits; + putreg16(regval, addr); + spin_unlock_irqrestore(NULL, flags); +} diff --git a/arch/arm64/src/common/arm64_modifyreg32.c b/arch/arm64/src/common/arm64_modifyreg32.c new file mode 100644 index 0000000000000..c3fc742739c1b --- /dev/null +++ b/arch/arm64/src/common/arm64_modifyreg32.c @@ -0,0 +1,57 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_modifyreg32.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "arm64_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: modifyreg32 + * + * Description: + * Atomically modify the specified bits in a memory mapped register + * + ****************************************************************************/ + +void modifyreg32(unsigned int addr, uint32_t clearbits, uint32_t setbits) +{ + irqstate_t flags; + uint32_t regval; + + flags = spin_lock_irqsave(NULL); + regval = getreg32(addr); + regval &= ~clearbits; + regval |= setbits; + putreg32(regval, addr); + spin_unlock_irqrestore(NULL, flags); +} diff --git a/arch/arm64/src/common/arm64_modifyreg8.c b/arch/arm64/src/common/arm64_modifyreg8.c new file mode 100644 index 0000000000000..cb230b257ea8e --- /dev/null +++ b/arch/arm64/src/common/arm64_modifyreg8.c @@ -0,0 +1,57 @@ +/**************************************************************************** + * arch/arm64/src/common/arm64_modifyreg8.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "arm64_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: modifyreg8 + * + * Description: + * Atomically modify the specified bits in a memory mapped register + * + ****************************************************************************/ + +void modifyreg8(unsigned int addr, uint8_t clearbits, uint8_t setbits) +{ + irqstate_t flags; + uint8_t regval; + + flags = spin_lock_irqsave(NULL); + regval = getreg8(addr); + regval &= ~clearbits; + regval |= setbits; + putreg8(regval, addr); + spin_unlock_irqrestore(NULL, flags); +} diff --git a/arch/arm64/src/common/arm64_schedulesigaction.c b/arch/arm64/src/common/arm64_schedulesigaction.c index 255a564e42a3e..eee31cd17f82a 100644 --- a/arch/arm64/src/common/arm64_schedulesigaction.c +++ b/arch/arm64/src/common/arm64_schedulesigaction.c @@ -74,7 +74,11 @@ void arm64_init_signal_process(struct tcb_s *tcb, struct regs_context *regs) /* Keep using SP_EL1 */ +#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3 + psigctx->spsr = SPSR_MODE_EL3H | DAIF_FIQ_BIT | DAIF_IRQ_BIT; +#else psigctx->spsr = SPSR_MODE_EL1H | DAIF_FIQ_BIT | DAIF_IRQ_BIT; +#endif psigctx->sp_elx = (uint64_t)stack_ptr; psigctx->sp_el0 = (uint64_t)psigctx; psigctx->exe_depth = 1; diff --git a/arch/arm64/src/common/arm64_task_sched.c b/arch/arm64/src/common/arm64_task_sched.c deleted file mode 100644 index 69f27df8c1a8f..0000000000000 --- a/arch/arm64/src/common/arm64_task_sched.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * arch/arm64/src/common/arm64_task_sched.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "sched/sched.h" -#include "group/group.h" -#include "arm64_internal.h" -#include "arm64_fatal.h" - -#ifdef CONFIG_ARCH_FPU -#include "arm64_fpu.h" -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: arm64_fullcontextrestore - * - * Description: - * Restore the current thread context. Full prototype is: - * - * void arm64_fullcontextrestore(uint64_t *restoreregs) noreturn_function; - * - * Returned Value: - * None - * - ****************************************************************************/ - -void arm64_fullcontextrestore(uint64_t *restoreregs) -{ - sys_call1(SYS_restore_context, (uintptr_t)restoreregs); - - __builtin_unreachable(); -} - -/**************************************************************************** - * Name: arm64_switchcontext - * - * Description: - * Save the current thread context and restore the specified context. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void arm64_switchcontext(uint64_t **saveregs, uint64_t *restoreregs) -{ - sys_call2(SYS_switch_context, (uintptr_t)saveregs, (uintptr_t)restoreregs); -} diff --git a/arch/arm64/src/common/arm64_vector_table.S b/arch/arm64/src/common/arm64_vector_table.S index 1f9fd33243ec0..e7b1eb005624d 100644 --- a/arch/arm64/src/common/arm64_vector_table.S +++ b/arch/arm64/src/common/arm64_vector_table.S @@ -69,8 +69,13 @@ stp x30, \xreg0, [sp, #8 * REG_X30] /* ELR and SPSR */ +#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3 + mrs \xreg0, elr_el3 + mrs \xreg1, spsr_el3 +#else mrs \xreg0, elr_el1 mrs \xreg1, spsr_el1 +#endif stp \xreg0, \xreg1, [sp, #8 * REG_ELR] /* increment exception depth */ @@ -246,8 +251,13 @@ arm64_exit_exc_fpu_done: /* restore spsr and elr at el1*/ ldp x0, x1, [sp, #8 * REG_ELR] +#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3 + msr elr_el3, x0 + msr spsr_el3, x1 +#else msr elr_el1, x0 msr spsr_el1, x1 +#endif /* decrement exception depth */ diff --git a/arch/arm64/src/common/arm64_vectors.S b/arch/arm64/src/common/arm64_vectors.S index e6541b519c57e..799b533ff2e50 100644 --- a/arch/arm64/src/common/arm64_vectors.S +++ b/arch/arm64/src/common/arm64_vectors.S @@ -92,8 +92,13 @@ SECTION_FUNC(text, up_saveusercontext) stp x30, x4, [x0, #8 * REG_X30] /* ELR and SPSR */ +#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3 + mrs x4, elr_el3 + mrs x5, spsr_el3 +#else mrs x4, elr_el1 mrs x5, spsr_el1 +#endif stp x4, x5, [x0, #8 * REG_ELR] arm64_exception_context_save x4 x5 x0 @@ -181,7 +186,11 @@ GTEXT(arm64_sync_exc) SECTION_FUNC(text, arm64_sync_exc) /* checking the EC value to see which exception need to be handle */ +#if CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3 + mrs x0, esr_el3 +#else mrs x0, esr_el1 +#endif lsr x1, x0, #26 #ifdef CONFIG_ARCH_FPU diff --git a/arch/arm64/src/common/crt0.c b/arch/arm64/src/common/crt0.c index ff6664f3cf90b..750a5e250b9db 100644 --- a/arch/arm64/src/common/crt0.c +++ b/arch/arm64/src/common/crt0.c @@ -91,7 +91,7 @@ static void sig_trampoline(void) ****************************************************************************/ /**************************************************************************** - * Name: _start + * Name: __start * * Description: * This function is the low level entry point into the main thread of @@ -110,7 +110,7 @@ static void sig_trampoline(void) * ****************************************************************************/ -void _start(int argc, char *argv[]) +void __start(int argc, char *argv[]) { int ret; diff --git a/arch/arm64/src/fvp-v8r/fvp_boot.c b/arch/arm64/src/fvp-v8r/fvp_boot.c index 78f0ef6c41637..255e508c13a6f 100644 --- a/arch/arm64/src/fvp-v8r/fvp_boot.c +++ b/arch/arm64/src/fvp-v8r/fvp_boot.c @@ -39,7 +39,8 @@ #include "arm64_mpu.h" #include "chip.h" #include "fvp_boot.h" -#include "serial_pl011.h" + +#include /**************************************************************************** * Private Data diff --git a/arch/arm64/src/fvp-v8r/fvp_lowputc.S b/arch/arm64/src/fvp-v8r/fvp_lowputc.S index 1aa6e204b1009..5d1231c95addd 100644 --- a/arch/arm64/src/fvp-v8r/fvp_lowputc.S +++ b/arch/arm64/src/fvp-v8r/fvp_lowputc.S @@ -26,7 +26,6 @@ #include #include "arm64_macro.inc" -#include "serial_pl011.h" /**************************************************************************** * Public Symbols diff --git a/arch/arm64/src/fvp-v8r/serial_pl011.h b/arch/arm64/src/fvp-v8r/serial_pl011.h deleted file mode 100644 index 39715a9741648..0000000000000 --- a/arch/arm64/src/fvp-v8r/serial_pl011.h +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** - * arch/arm64/src/fvp-v8r/serial_pl011.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_ARM64_SRC_FVP_V8R_SERIAL_PL011_H -#define __ARCH_ARM64_SRC_FVP_V8R_SERIAL_PL011_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_ARM64_SRC_FVP_V8R_SERIAL_PL011_H */ diff --git a/arch/arm64/src/goldfish/Make.defs b/arch/arm64/src/goldfish/Make.defs index fb50c61239e82..67bae71105275 100644 --- a/arch/arm64/src/goldfish/Make.defs +++ b/arch/arm64/src/goldfish/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# arch/arm64/src/qemu/Make.defs +# arch/arm64/src/goldfish/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/arch/arm64/src/goldfish/goldfish_boot.c b/arch/arm64/src/goldfish/goldfish_boot.c index bc9ce37ae2e34..aac71e1a2dd9c 100644 --- a/arch/arm64/src/goldfish/goldfish_boot.c +++ b/arch/arm64/src/goldfish/goldfish_boot.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif diff --git a/arch/arm64/src/imx8/imx8_boot.c b/arch/arm64/src/imx8/imx8_boot.c index 5d383430fcd9f..62e6b1f0fd720 100644 --- a/arch/arm64/src/imx8/imx8_boot.c +++ b/arch/arm64/src/imx8/imx8_boot.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif diff --git a/arch/arm64/src/imx9/Kconfig b/arch/arm64/src/imx9/Kconfig new file mode 100644 index 0000000000000..3f012563c9bbc --- /dev/null +++ b/arch/arm64/src/imx9/Kconfig @@ -0,0 +1,1010 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_IMX9 + +menu "i.MX9 Chip Selection" + +choice + prompt "i.MX9 Core Configuration" + default ARCH_CHIP_IMX93 + +config ARCH_CHIP_IMX93 + bool "i.MX9 Application Processor" + select ARCH_HAVE_MULTICPU + select ARMV8A_HAVE_GICv3 + select ARCH_CORTEX_A55 + select ARCH_HAVE_PSCI if !IMX9_BOOTLOADER + select ARCH_HAVE_PWM_MULTICHAN + select ARCH_HAVE_RESET + +endchoice # i.MX9 Chip Selection + +endmenu # "i.MX9 Chip Selection" + +config IMX9_DMA_ALLOC + bool "Enable DMA capable memory allocator" + depends on GRAN + default y if CONFIG_FAT_DMAMEMORY + +menu "DMA Allocator Configuration" + depends on IMX9_DMA_ALLOC + +config IMX9_DMA_ALLOC_POOL_SIZE + int "DMA allocator memory pool size in bytes" + default 4096 + +config IMX9_DMA_ALLOC_SECT + string "Section for DMA allocator memory pool, default is .bss" + default ".bss" + +endmenu # DMA Allocator Configuration + +config IMX9_FLEXIO_PWM + bool + select PWM_MULTICHAN + default n + +config IMX9_BOOTLOADER + bool "Bootloader" + select ARM64_DECODEFIQ + default n + ---help--- + Configure NuttX as the bootloader. NuttX will be compiled + into OCRAM. It will run in EL3 secure state. + +config BOOTLOADER_SYS_CLOCK + int "Bootloader system clock for timer" + default 1700000000 + depends on IMX9_BOOTLOADER + ---help--- + If the sysclk is set to a certain value, this should be it. + The value is used by the timer interrupt infrastructure. + +menu "i.MX9 Peripheral Selection" + +config IMX9_EDMA + bool "eDMA" + default n + select ARCH_DMA + +menu "USDHC" + +config IMX9_USDHC + bool + default n + select ARCH_HAVE_SDIO_PREFLIGHT + +config IMX9_USDHC1 + bool "USDHC1" + default n + select ARCH_HAVE_SDIO + select IMX9_USDHC + ---help--- + Support USDHC host controller 1 + +config IMX9_USDHC2 + bool "USDHC2" + default n + select ARCH_HAVE_SDIO + select IMX9_USDHC + ---help--- + Support USDHC host controller 2 + +menu "USDHC Configuration" + depends on IMX9_USDHC + +config IMX9_USDHC_DMA + bool "Support DMA data transfers" + default y + select SDIO_DMA + ---help--- + Support DMA data transfers. + Enable SD card DMA data transfers. This is marginally optional. + For most usages, SD accesses will cause data overruns if used without + DMA. + +choice + prompt "Bus width for USDHC1" + default IMX9_USDHC1_WIDTH_D1_ONLY + depends on IMX9_USDHC1 + +config IMX9_USDHC1_WIDTH_D1_ONLY + bool "One bit" + +config IMX9_USDHC1_WIDTH_D1_D4 + bool "Four bit" + +config IMX9_USDHC1_WIDTH_D1_D8 + bool "Eight bit" + +endchoice + +config IMX9_USDHC1_INVERT_CD + bool "Invert the USDHC1 CD" + default n + depends on IMX9_USDHC1 + ---help--- + If the board defines PIN_USDHC1_CD the CD_B input to the USDHC it is + assumed to be active low. Selecting IMX9_USDHC1_INVERT_CD will make it + active high. + + If the board defines PIN_USDHC1_CD_GPIO it is assumed to be active low. + Selecting IMX9_USDHC1_INVERT_CD will make it active high. + +choice + depends on IMX9_USDHC2 + prompt "Bus width for USDHC2" + default IMX9_USDHC2_WIDTH_D1_D4 + +config IMX9_USDHC2_WIDTH_D1_ONLY + bool "One bit" + +config IMX9_USDHC2_WIDTH_D1_D4 + bool "Four bit" + +endchoice + +config IMX9_USDHC2_INVERT_CD + bool "Invert the USDHC2 CD" + default n + depends on IMX9_USDHC2 + ---help--- + If the board defines PIN_USDHC2_CD the CD_B input to the USDHC it is + assumed to be active low. Selecting IMX9_USDHC_INVERT_CD will make it + active high. + + If the board defines PIN_USDHC2_CD_GPIO it is assumed to be active low. + Selecting IMX9_USDHC2_INVERT_CD will make it active high. + +endmenu # USDHC Configuration + +endmenu # USDHC + +menu "LPUART" + +config IMX9_LPUART + bool + default n + select ARCH_HAVE_SERIAL_TERMIOS + +config IMX9_LPUART1 + bool "LPUART1" + default n + select IMX9_LPUART + select LPUART1_SERIALDRIVER + +config IMX9_LPUART2 + bool "LPUART2" + default n + select IMX9_LPUART + select LPUART2_SERIALDRIVER + +config IMX9_LPUART3 + bool "LPUART3" + default n + select IMX9_LPUART + select LPUART3_SERIALDRIVER + +config IMX9_LPUART4 + bool "LPUART4" + default n + select IMX9_LPUART + select LPUART4_SERIALDRIVER + +config IMX9_LPUART5 + bool "LPUART5" + default n + select IMX9_LPUART + select LPUART5_SERIALDRIVER + +config IMX9_LPUART6 + bool "LPUART6" + default n + select IMX9_LPUART + select LPUART6_SERIALDRIVER + +config IMX9_LPUART7 + bool "LPUART7" + default n + select IMX9_LPUART + select LPUART7_SERIALDRIVER + +config IMX9_LPUART8 + bool "LPUART8" + default n + select IMX9_LPUART + select LPUART8_SERIALDRIVER + +menu "LPUART Configuration" + depends on IMX9_LPUART + +config IMX9_LPUART_INVERT + bool "Signal Invert Support" + default n + +config IMX9_LPUART_SINGLEWIRE + bool "Signal Wire Support" + default n + +config IMX9_SERIAL_RXDMA_BUFFER_SIZE + int "RX DMA buffer size" + default 64 + depends on LPUART1_RXDMA || LPUART2_RXDMA || LPUART3_RXDMA || LPUART4_RXDMA || \ + LPUART5_RXDMA || LPUART6_RXDMA || LPUART7_RXDMA || LPUART8_RXDMA + ---help--- + The DMA buffer size when using RX DMA to emulate a FIFO. + + When streaming data, the generic serial layer will be called + every time the FIFO receives half this number of bytes. + + Value given here will be rounded up to next multiple of 64 bytes. + +endmenu # LPUART Configuration + +endmenu # LPUART + +config IMX9_FLEXIO1_PWM + depends on PWM + bool "Enable FLEXIO1 based PWM generation" + select IMX9_FLEXIO_PWM + default n + +config IMX9_FLEXIO2_PWM + depends on PWM + bool "Enable FLEXIO2 based PWM generation" + select IMX9_FLEXIO_PWM + default n + +config IMX9_FLEXIO1_PWM_NCHANNELS + depends on IMX9_FLEXIO1_PWM + int "Number of channels for FLEXIO1" + default 4 + range 1 7 + +config IMX9_FLEXIO1_PWM_CHANNEL_PINS + depends on IMX9_FLEXIO1_PWM + hex "FlexIO outputs used for FLEXIO1 timers" + default 0x0000000007060504 + +config IMX9_FLEXIO2_PWM_NCHANNELS + depends on IMX9_FLEXIO2_PWM + int "Number of channels for FLEXIO2" + default 1 + range 1 7 + +config IMX9_FLEXIO2_PWM_CHANNEL_PINS + depends on IMX9_FLEXIO2_PWM + hex "FlexIO outputs used for FLEXIO2 timers" + default 0x0000000000000000 + +config IMX9_TPM_PWM + bool + select PWM_MULTICHAN + default n + +config IMX9_TPM1_PWM + depends on PWM + bool "Enable TPM1 based PWM generation" + select IMX9_TPM_PWM + default n + +config IMX9_TPM1_PWM_NCHANNELS + depends on IMX9_TPM1_PWM + int "Number of channels for TPM1" + default 1 + +config IMX9_TPM1_PWM_CHMUX + depends on IMX9_TPM1_PWM + hex "Channel mux for TPM1" + default 0x03020100 + +config IMX9_TPM2_PWM + depends on PWM + bool "Enable TPM2 based PWM generation" + select IMX9_TPM_PWM + default n + +config IMX9_TPM2_PWM_NCHANNELS + depends on IMX9_TPM2_PWM + int "Number of channels for TPM2" + default 1 + +config IMX9_TPM2_PWM_CHMUX + depends on IMX9_TPM2_PWM + hex "Channel mux for TPM2" + default 0x03020100 + +config IMX9_TPM3_PWM + depends on PWM + bool "Enable TPM3 based PWM generation" + select IMX9_TPM_PWM + default n + +config IMX9_TPM3_PWM_NCHANNELS + depends on IMX9_TPM3_PWM + int "Number of channels for TPM3" + default 1 + +config IMX9_TPM3_PWM_CHMUX + depends on IMX9_TPM3_PWM + hex "Channel mux for TPM3" + default 0x03020100 + +config IMX9_TPM4_PWM + depends on PWM + bool "Enable TPM4 based PWM generation" + select IMX9_TPM_PWM + default n + +config IMX9_TPM4_PWM_NCHANNELS + depends on IMX9_TPM4_PWM + int "Number of channels for TPM4" + default 1 + +config IMX9_TPM4_PWM_CHMUX + depends on IMX9_TPM4_PWM + hex "Channel mux for TPM4" + default 0x03020100 + +config IMX9_TPM5_PWM + depends on PWM + bool "Enable TPM5 based PWM generation" + select IMX9_TPM_PWM + default n + +config IMX9_TPM5_PWM_NCHANNELS + depends on IMX9_TPM5_PWM + int "Number of channels for TPM5" + default 1 + +config IMX9_TPM5_PWM_CHMUX + depends on IMX9_TPM5_PWM + hex "Channel mux for TPM5" + default 0x03020100 + +config IMX9_TPM6_PWM + depends on PWM + bool "Enable TPM6 based PWM generation" + select IMX9_TPM_PWM + default n + +config IMX9_TPM6_PWM_NCHANNELS + depends on IMX9_TPM6_PWM + int "Number of channels for TPM6" + default 1 + +config IMX9_TPM6_PWM_CHMUX + depends on IMX9_TPM6_PWM + hex "Channel mux for TPM6" + default 0x03020100 + +config IMX9_USBDEV + bool + default n + select USBDEV + +config IMX9_USBDEV_USBC1 + bool "USB Device using controller 1" + default n + select IMX9_USBDEV + +config IMX9_USBDEV_USBC2 + depends on !IMX9_USBDEV_USBC1 + bool "USB Device using controller 2" + default n + select IMX9_USBDEV + +if IMX9_USBDEV + +menu "USB device controller driver (DCD) options" + +config IMX9_USBDEV_NOVBUS + bool "No USB VBUS sensing" + default n + +config IMX9_USBDEV_FRAME_INTERRUPT + bool "USB frame interrupt" + default n + ---help--- + Handle USB Start-Of-Frame events. Enable reading SOF from interrupt + handler vs. simply reading on demand. Probably a bad idea... Unless + there is some issue with sampling the SOF from hardware asynchronously. + +config IMX9_USBDEV_REGDEBUG + bool "Register level debug" + depends on DEBUG_USB_INFO + default n + ---help--- + Output detailed register-level USB device debug information. Requires + also CONFIG_DEBUG_USB_INFO. + +endmenu # USB device controller driver (DCD) options + +endif # IMX9_USBDEV + +config IMX9_ENET + bool "Ethernet" + default n + select ARCH_HAVE_PHY + select ARCH_HAVE_NETDEV_STATISTICS + +config IMX9_GPIO_IRQ + bool "GPIO Interrupt Support" + default n + +config IMX9_LPI2C + bool "LPI2C support" + default n + +config IMX9_LPSPI + bool "LPSPI support" + default n + +menu "LPI2C Peripherals" + +menuconfig IMX9_LPI2C1 + bool "LPI2C1" + default n + select IMX9_LPI2C + +if IMX9_LPI2C1 + +config IMX9_LPI2C1_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config IMX9_LPI2C1_DMA + bool "Enable DMA for I2C1" + default n + depends on IMX9_LPI2C_DMA + +config IMX9_LPI2C1_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config IMX9_LPI2C1_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMX9_LPI2C1 + +menuconfig IMX9_LPI2C2 + bool "LPI2C2" + default n + select IMX9_LPI2C + +if IMX9_LPI2C2 + +config IMX9_LPI2C2_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config IMX9_LPI2C2_DMA + bool "Enable DMA for I2C2" + default n + depends on IMX9_LPI2C_DMA + +config IMX9_LPI2C2_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config IMX9_LPI2C2_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMX9_LPI2C2 + +menuconfig IMX9_LPI2C3 + bool "LPI2C3" + default n + select IMX9_LPI2C + +if IMX9_LPI2C3 + +config IMX9_LPI2C3_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config IMX9_LPI2C3_DMA + bool "Enable DMA for I2C3" + default n + depends on IMX9_LPI2C_DMA + +config IMX9_LPI2C3_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config IMX9_LPI2C3_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMX9_LPI2C3 + +menuconfig IMX9_LPI2C4 + bool "LPI2C4" + default n + select IMX9_LPI2C + +if IMX9_LPI2C4 + +config IMX9_LPI2C4_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config IMX9_LPI2C4_DMA + bool "Enable DMA for I2C4" + default n + depends on IMX9_LPI2C_DMA + +config IMX9_LPI2C4_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config IMX9_LPI2C4_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMX9_LPI2C4 + +menuconfig IMX9_LPI2C5 + bool "LPI2C5" + default n + select IMX9_LPI2C + +if IMX9_LPI2C5 + +config IMX9_LPI2C5_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config IMX9_LPI2C5_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config IMX9_LPI2C5_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMX9_LPI2C5 + +menuconfig IMX9_LPI2C6 + bool "LPI2C6" + default n + select IMX9_LPI2C + +if IMX9_LPI2C6 + +config IMX9_LPI2C6_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config IMX9_LPI2C6_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config IMX9_LPI2C6_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMX9_LPI2C6 + +menuconfig IMX9_LPI2C7 + bool "LPI2C7" + default n + select IMX9_LPI2C + +if IMX9_LPI2C7 + +config IMX9_LPI2C7_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config IMX9_LPI2C7_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config IMX9_LPI2C7_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMX9_LPI2C7 + +menuconfig IMX9_LPI2C8 + bool "LPI2C8" + default n + select IMX9_LPI2C + +if IMX9_LPI2C8 + +config IMX9_LPI2C8_BUSYIDLE + int "Bus idle timeout period in clock cycles" + default 0 + +config IMX9_LPI2C8_FILTSCL + int "I2C master digital glitch filters for SCL input in clock cycles" + default 0 + +config IMX9_LPI2C8_FILTSDA + int "I2C master digital glitch filters for SDA input in clock cycles" + default 0 + +endif # IMX9_LPI2C8 + +endmenu # LPI2C Peripherals + +menu "LPSPI Peripherals" + +menuconfig IMX9_LPSPI1 + bool "LPSPI1" + default n + select IMX9_LPSPI + +menuconfig IMX9_LPSPI2 + bool "LPSPI2" + default n + select IMX9_LPSPI + +menuconfig IMX9_LPSPI3 + bool "LPSPI3" + default n + select IMX9_LPSPI + +menuconfig IMX9_LPSPI4 + bool "LPSPI4" + default n + select IMX9_LPSPI + +menuconfig IMX9_LPSPI5 + bool "LPSPI5" + default n + select IMX9_LPSPI + +menuconfig IMX9_LPSPI6 + bool "LPSPI6" + default n + select IMX9_LPSPI + +menuconfig IMX9_LPSPI7 + bool "LPSPI7" + default n + select IMX9_LPSPI + +menuconfig IMX9_LPSPI8 + bool "LPSPI8" + default n + select IMX9_LPSPI + +endmenu # LPSPI Peripherals + +menu "eDMA Configuration" + depends on IMX9_EDMA + +config IMX9_EDMA_NTCD + int "Number of transfer descriptors" + default 0 + ---help--- + Number of pre-allocated transfer descriptors. Needed for scatter- + gather DMA. Make to be set to zero to disable in-memory TCDs in + which case only the TCD channel registers will be used and scatter- + will not be supported. + +config IMX9_EDMA_ELINK + bool "Channeling Linking" + default n + ---help--- + This option enables optional minor or major loop channel linking: + + Minor loop channel linking: As the channel completes the minor + loop, this flag enables linking to another channel. The link target + channel initiates a channel service request via an internal + mechanism that sets the TCDn_CSR[START] bit of the specified + channel. + + If minor loop channel linking is disabled, this link mechanism is + suppressed in favor of the major loop channel linking. + + Major loop channel linking: As the channel completes the minor + loop, this option enables the linking to another channel. The link + target channel initiates a channel service request via an internal + mechanism that sets the TCDn_CSR[START] bit of the linked channel. + +config IMX9_EDMA_ERCA + bool "Round Robin Channel Arbitration" + default n + ---help--- + Normally, a fixed priority arbitration is used for channel + selection. If this option is selected, round robin arbitration is + used for channel selection. + +config IMX9_EDMA_HOE + bool "Halt On Error" + default y + ---help--- + Any error causes the HALT bit to set. Subsequently, all service + requests are ignored until the HALT bit is cleared. + +config IMX9_EDMA_CLM + bool "Continuous Link Mode" + default n + ---help--- + By default, A minor loop channel link made to itself goes through + channel arbitration before being activated again. If this option is + selected, a minor loop channel link made to itself does not go + through channel arbitration before being activated again. Upon minor + loop completion, the channel activates again if that channel has a + minor loop channel link enabled and the link channel is itself. This + effectively applies the minor loop offsets and restarts the next + minor loop. + +config IMX9_EDMA_EMLIM + bool "Minor Loop Mapping" + default n + ---help--- + Normally TCD word 2 is a 32-bit NBYTES field. When this option is + enabled, TCD word 2 is redefined to include individual enable fields, + an offset field, and the NBYTES field. The individual enable fields + allow the minor loop offset to be applied to the source address, the + destination address, or both. The NBYTES field is reduced when either + offset is enabled. + +config IMX9_EDMA_EDBG + bool "Enable Debug" + default n + ---help--- + When in debug mode, the DMA stalls the start of a new channel. Executing + channels are allowed to complete. Channel execution resumes when the + system exits debug mode or the EDBG bit is cleared + +endmenu # eDMA Global Configuration + +menu "LPI2C Configuration" + depends on IMX9_LPI2C + +config IMX9_LPI2C_DMA + bool "I2C DMA Support" + default n + depends on IMX9_LPI2C && IMX9_EDMA && !I2C_POLLED + ---help--- + This option enables the DMA for I2C transfers. + Note: The user can define CONFIG_I2C_DMAPRIO: a custom priority value + for the I2C dma streams, else the default priority level is set to + medium. + +config IMX9_LPI2C_DMA_MAXMSG + int "Maximum number messages that will be DMAed" + default 8 + depends on IMX9_LPI2C_DMA + ---help--- + This option set the mumber of mesg that can be in a transfer. + It is used to allocate space for the 16 bit LPI2C commands + that will be DMA-ed to the LPI2C device. + +config IMX9_LPI2C_DYNTIMEO + bool "Use dynamic timeouts" + default n + depends on IMX9_LPI2C + +config IMX9_LPI2C_DYNTIMEO_USECPERBYTE + int "Timeout Microseconds per Byte" + default 500 + depends on IMX9_LPI2C_DYNTIMEO + +config IMX9_LPI2C_DYNTIMEO_STARTSTOP + int "Timeout for Start/Stop (Milliseconds)" + default 1000 + depends on IMX9_LPI2C_DYNTIMEO + +config IMX9_LPI2C_TIMEOSEC + int "Timeout seconds" + default 0 + depends on IMX9_LPI2C + +config IMX9_LPI2C_TIMEOMS + int "Timeout Milliseconds" + default 500 + depends on IMX9_LPI2C && !IMX9_LPI2C_DYNTIMEO + +config IMX9_LPI2C_TIMEOTICKS + int "Timeout for Done and Stop (ticks)" + default 500 + depends on IMX9_LPI2C && !IMX9_LPI2C_DYNTIMEO + +endmenu # LPI2C Configuration + +menu "LPSPI Configuration" + depends on IMX9_LPSPI + +config IMX9_LPSPI_DMA + bool "LPSPI DMA" + depends on IMX9_EDMA + default n + ---help--- + Use DMA to improve LPSPI transfer performance. + +config IMX9_LPSPI_DMATHRESHOLD + int "LPSPI DMA threshold" + default 4 + depends on IMX9_LPSPI_DMA + ---help--- + When SPI DMA is enabled, small DMA transfers will still be performed + by polling logic. But we need a threshold value to determine what + is small. + +config IMX9_LPSPI_DMA_BUFFER_SIZE + int "LPSPI DMA buffer size" + default 4096 + depends on IMX9_LPSPI_DMA + ---help--- + Set the LPSPI driver DMA buffer size. + +config IMX9_LPSPI1_DMA + bool "LPSPI1 DMA" + default n + depends on IMX9_LPSPI1 && IMX9_LPSPI_DMA + ---help--- + Use DMA to improve LPSPI1 transfer performance. + +config IMX9_LPSPI2_DMA + bool "LPSPI2 DMA" + default n + depends on IMX9_LPSPI2 && IMX9_LPSPI_DMA + ---help--- + Use DMA to improve LPSPI2 transfer performance. + +config IMX9_LPSPI3_DMA + bool "LPSPI3 DMA" + default n + depends on IMX9_LPSPI3 && IMX9_LPSPI_DMA + ---help--- + Use DMA to improve LPSPI3 transfer performance. + +config IMX9_LPSPI4_DMA + bool "LPSPI4 DMA" + default n + depends on IMX9_LPSPI4 && IMX9_LPSPI_DMA + ---help--- + Use DMA to improve SPI4 transfer performance. + +config IMX9_LPSPI5_DMA + bool "LPSPI5 DMA" + default n + depends on IMX9_LPSPI5 && IMX9_LPSPI_DMA + ---help--- + Use DMA to improve SPI5 transfer performance. + +config IMX9_LPSPI6_DMA + bool "LPSPI6 DMA" + default n + depends on IMX9_LPSPI6 && IMX9_LPSPI_DMA + ---help--- + Use DMA to improve SPI6 transfer performance. + +config IMX9_LPSPI7_DMA + bool "LPSPI7 DMA" + default n + depends on IMX9_LPSPI7 && IMX9_LPSPI_DMA + ---help--- + Use DMA to improve SPI7 transfer performance. + +config IMX9_LPSPI8_DMA + bool "LPSPI8 DMA" + default n + depends on IMX9_LPSPI8 && IMX9_LPSPI_DMA + ---help--- + Use DMA to improve SPI8 transfer performance. + +endmenu # LPSPI Configuration + +menu "Ethernet Configuration" + depends on IMX9_ENET + +config IMX9_ENET1 + bool "Ethernet MAC (non-QoS)" + depends on IMX9_ENET + default y + +config IMX9_ENET_NRXBUFFERS + int "Number of Rx buffers" + default 6 + +config IMX9_ENET_NTXBUFFERS + int "Number of Tx buffers" + default 2 + +config IMX9_ENET_USE_OTP_MAC + bool "Use MAC address from OCOTP" + default n + depends on IMX9_ENET + +config IMX9_ENET1_OTP_MAC_ADDR + hex "MAC address offset in OCOTP" + default 0x4ec + depends on IMX9_ENET_USE_OTP_MAC + +config IMX9_ENET1_PROMISCUOUS + bool "Set promiscuous mode" + depends on IMX9_ENET1 + default n + +choice + prompt "i.MX9 ENET1 interface type" + default IMX9_ENET1_RMII + depends on IMX9_ENET1 + +config IMX9_ENET1_RMII + bool "RMII" + +config IMX9_ENET1_RGMII + bool "RGMII" + +endchoice + +config IMX9_ENET1_PHY_AUTONEG + bool "ENET1 PHY autonegotiation enable" + default y + ---help--- + Enable PHY autonegotiation. If set to n, configure the speed + and duplex mode manually. Note that only disabling this doesn't + disable the autonegotiation completely; it just sets the MAC + speed and duplex, and disables autonegotiation advertisement + for other than the configured mode. To disable autonegotiation + completely, also set the FORCE_SPEED flag. + +choice + prompt "Select ENET1 PHY link duplex mode" + default IMX9_ENET1_PHY_FD + depends on !IMX9_ENET1_PHY_AUTONEG + +config IMX9_ENET1_PHY_FD + bool "Full Duplex" + +config IMX9_ENET1_PHY_HD + bool "Half Duplex" +endchoice + +choice + prompt "Select ENET1 PHY link speed" + default IMX9_ENET1_PHY_100MBPS if IMX9_ENET1_RMII + default IMX9_ENET1_PHY_1000MBPS if IMX9_ENET1_RGMII + depends on !IMX9_ENET1_PHY_AUTONEG + +config IMX9_ENET1_PHY_10MBPS + bool "10 MBPS" + +config IMX9_ENET1_PHY_100MBPS + bool "100 MBPS" + +config IMX9_ENET1_PHY_1000MBPS + bool "1000 MBPS" + depends on IMX9_ENET1_RGMII +endchoice + +config IMX9_ENET1_PHY_FORCE_SPEED + bool "Disable PHY autonegotiation and force speed and duplex" + depends on !IMX9_ENET1_PHY_AUTONEG + default n + ---help--- + This disables PHY autonegotiation completely. Note that + if the link partner has got autonegotiation enabled, the + duplex mode is not auto-detected by the link partner. Only + enable if you really know what you are doing! + +config IMX9_ENET1_PHYINIT + bool "Board-specific PHY Initialization for ENET1" + default n + ---help--- + Some boards require specialized initialization of the PHY before it + can be used. This may include such things as configuring GPIOs, + resetting the PHY, etc. If CONFIG_IMX9_ENET_PHYINIT is defined in + the configuration then the board specific logic must provide + imx9_phy_boardinitialize(); The i.MX9 ENET driver will call this + function one time before it first uses the PHY. + +endmenu # IMX9_ENET + +endmenu # iMX Peripheral Selection + +endif # ARCH_CHIP_IMX9 diff --git a/arch/arm64/src/imx9/Make.defs b/arch/arm64/src/imx9/Make.defs new file mode 100644 index 0000000000000..38466ba3704aa --- /dev/null +++ b/arch/arm64/src/imx9/Make.defs @@ -0,0 +1,69 @@ +############################################################################ +# arch/arm64/src/imx9/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include common/Make.defs + +# i.MX9-specific C source files + +CHIP_CSRCS = imx9_boot.c imx9_ccm.c imx9_clockconfig.c imx9_gpio.c imx9_iomuxc.c + +ifeq ($(CONFIG_ARCH_CHIP_IMX93),y) + CHIP_CSRCS += imx9_lpuart.c imx9_lowputc.c +endif + +ifeq ($(CONFIG_IMX9_GPIO_IRQ),y) + CHIP_CSRCS += imx9_gpioirq.c +endif + +ifeq ($(CONFIG_IMX9_FLEXIO_PWM),y) + CHIP_CSRCS += imx9_flexio_pwm.c +endif + +ifeq ($(CONFIG_IMX9_TPM_PWM),y) + CHIP_CSRCS += imx9_tpm_pwm.c +endif + +ifeq ($(CONFIG_IMX9_USBDEV),y) + CHIP_CSRCS += imx9_usbdev.c +endif + +ifeq ($(CONFIG_IMX9_LPI2C),y) + CHIP_CSRCS += imx9_lpi2c.c +endif + +ifeq ($(CONFIG_IMX9_LPSPI),y) + CHIP_CSRCS += imx9_lpspi.c +endif + +ifeq ($(CONFIG_IMX9_EDMA), y) + CHIP_CSRCS += imx9_edma.c +endif + +ifeq ($(CONFIG_IMX9_DMA_ALLOC),y) + CHIP_CSRCS += imx9_dma_alloc.c +endif + +ifeq ($(CONFIG_IMX9_ENET),y) + CHIP_CSRCS += imx9_enet.c +endif + +ifeq ($(CONFIG_IMX9_USDHC),y) + CHIP_CSRCS += imx9_usdhc.c +endif diff --git a/arch/arm64/src/imx9/chip.h b/arch/arm64/src/imx9/chip.h new file mode 100644 index 0000000000000..f9792f5518e30 --- /dev/null +++ b/arch/arm64/src/imx9/chip.h @@ -0,0 +1,44 @@ +/**************************************************************************** + * arch/arm64/src/imx9/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_CHIP_H +#define __ARCH_ARM64_SRC_IMX9_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Macro Definitions + ****************************************************************************/ + +#endif /* __ARCH_ARM64_SRC_IMX9_CHIP_H */ diff --git a/arch/arm64/src/imx9/hardware/imx93/imx93_ccm.h b/arch/arm64/src/imx9/hardware/imx93/imx93_ccm.h new file mode 100644 index 0000000000000..a86f4e72f200f --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx93/imx93_ccm.h @@ -0,0 +1,711 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx93/imx93_ccm.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_CCM_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_CCM_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define IMX9_CCM_CR_CTRL_OFFSET(n) (0x0000 + ((n) << 7)) /* Clock root control (CLOCK_ROOTn_CONTROL, n=0..94) */ +#define IMX9_CCM_CR_CTRL_SET_OFFSET(n) (0x0004 + ((n) << 7)) /* Clock root control (CLOCK_ROOTn_CONTROL_SET, n=0..94) */ +#define IMX9_CCM_CR_CTRL_CLR_OFFSET(n) (0x0008 + ((n) << 7)) /* Clock root control (CLOCK_ROOTn_CONTROL_CLR, n=0..94) */ +#define IMX9_CCM_CR_CTRL_TOG_OFFSET(n) (0x000c + ((n) << 7)) /* Clock root control (CLOCK_ROOTn_CONTROL_TOG, n=0..94) */ +#define IMX9_CCM_CR_STAT0_OFFSET(n) (0x0020 + ((n) << 7)) /* Clock root working status (CLOCK_ROOTn_STATUS0, n=0..94) */ +#define IMX9_CCM_CR_AUTH_OFFSET(n) (0x0030 + ((n) << 7)) /* Clock root access control (CLOCK_ROOTn_AUTHEN, n=0..94) */ +#define IMX9_CCM_CR_AUTH_SET_OFFSET(n) (0x0034 + ((n) << 7)) /* Clock root access control (CLOCK_ROOTn_AUTHEN_SET, n=0..94) */ +#define IMX9_CCM_CR_AUTH_CLR_OFFSET(n) (0x0038 + ((n) << 7)) /* Clock root access control (CLOCK_ROOTn_AUTHEN_CLR, n=0..94) */ +#define IMX9_CCM_CR_AUTH_TOG_OFFSET(n) (0x003c + ((n) << 7)) /* Clock root access control (CLOCK_ROOTn_AUTHEN_TOG, n=0..94) */ + +#define IMX9_CCM_GPR_SH_OFFSET(n) (0x4800 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn, n=0..7) */ +#define IMX9_CCM_GPR_SH_SET_OFFSET(n) (0x4804 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_SET, n=0..7) */ +#define IMX9_CCM_GPR_SH_CLR_OFFSET(n) (0x4808 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_CLR, n=0..7) */ +#define IMX9_CCM_GPR_SH_TOG_OFFSET(n) (0x480c + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_TOG, n=0..7) */ +#define IMX9_CCM_GPR_SH_AUTH_OFFSET(n) (0x4810 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_AUTHEN, n=0..7) */ +#define IMX9_CCM_GPR_SH_AUTH_SET_OFFSET(n) (0x4814 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_AUTHEN_SET, n=0..7) */ +#define IMX9_CCM_GPR_SH_AUTH_CLR_OFFSET(n) (0x4818 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_AUTHEN_CLR, n=0..7) */ +#define IMX9_CCM_GPR_SH_AUTH_TOG_OFFSET(n) (0x481c + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_AUTHEN_TOG, n=0..7) */ + +#define IMX9_CCM_GPR_PR_OFFSET(n) (0x4c00 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn, n=1..7) */ +#define IMX9_CCM_GPR_PR_SET_OFFSET(n) (0x4c04 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_SET, n=1..7) */ +#define IMX9_CCM_GPR_PR_CLR_OFFSET(n) (0x4c08 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_CLR, n=1..7) */ +#define IMX9_CCM_GPR_PR_TOG_OFFSET(n) (0x4c0c + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_TOG, n=1..7) */ +#define IMX9_CCM_GPR_PR_AUTH_OFFSET(n) (0x4c10 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_AUTHEN, n=1..7) */ +#define IMX9_CCM_GPR_PR_AUTH_SET_OFFSET(n) (0x4c14 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_AUTHEN_SET, n=1..7) */ +#define IMX9_CCM_GPR_PR_AUTH_CLR_OFFSET(n) (0x4c18 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_AUTHEN_CLR, n=1..7) */ +#define IMX9_CCM_GPR_PR_AUTH_TOG_OFFSET(n) (0x4c1c + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_AUTHEN_TOG, n=1..7) */ + +#define IMX9_CCM_OSCPLL_DIR_OFFSET(n) (0x5000 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */ +#define IMX9_CCM_OSCPLL_LPM_STAT0_OFFSET(n) (0x5004 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */ +#define IMX9_CCM_OSCPLL_LPM_STAT1_OFFSET(n) (0x5008 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */ +#define IMX9_CCM_OSCPLL_LPM0_OFFSET(n) (0x5010 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */ +#define IMX9_CCM_OSCPLL_LPM1_OFFSET(n) (0x5014 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */ +#define IMX9_CCM_OSCPLL_LPM_CUR_OFFSET(n) (0x501C + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */ +#define IMX9_CCM_OSCPLL_STAT0_OFFSET(n) (0x5020 + ((n) << 6)) /* Clock source working status (OSCPLLn_STATUS0, n=0..18) */ +#define IMX9_CCM_OSCPLL_STAT1_OFFSET(n) (0x5024 + ((n) << 6)) /* Clock source low power status (OSCPLLn_STATUS1, n=0..18) */ +#define IMX9_CCM_OSCPLL_AUTH_OFFSET(n) (0x5030 + ((n) << 6)) /* Clock source access control (OSCPLLn_AUTHEN, n=0..18) */ + +#define IMX9_CCM_LPCG_DIR_OFFSET(n) (0x8000 + ((n) << 6)) /* LPCG direct control (LPCGn_DIRECT, n=0..126) */ +#define IMX9_CCM_LPCG_LPM_STAT0_OFFSET(n) (0x8004 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */ +#define IMX9_CCM_LPCG_LPM_STAT1_OFFSET(n) (0x8008 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */ +#define IMX9_CCM_LPCG_LPM0_OFFSET(n) (0x8010 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */ +#define IMX9_CCM_LPCG_LPM1_OFFSET(n) (0x8014 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */ +#define IMX9_CCM_LPCG_LPM_CUR_OFFSET(n) (0x801C + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */ +#define IMX9_CCM_LPCG_STAT0_OFFSET(n) (0x8020 + ((n) << 6)) /* LPCG working status (LPCGn_STATUS0, n=0..126) */ +#define IMX9_CCM_LPCG_STAT1_OFFSET(n) (0x8024 + ((n) << 6)) /* LPCG low power status (LPCGn_STATUS1, n=0..126) */ +#define IMX9_CCM_LPCG_AUTH_OFFSET(n) (0x8030 + ((n) << 6)) /* LPCG access control (LPCGn_AUTHEN, n=0..126) */ + +/* Register addresses *******************************************************/ + +#define IMX9_CCM_CR_CTRL(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_CTRL_OFFSET(n)) +#define IMX9_CCM_CR_CTRL_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_CTRL_SET_OFFSET(n)) +#define IMX9_CCM_CR_CTRL_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_CTRL_CLR_OFFSET(n)) +#define IMX9_CCM_CR_CTRL_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_CTRL_TOG_OFFSET(n)) +#define IMX9_CCM_CR_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_STAT0_OFFSET(n)) +#define IMX9_CCM_CR_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_AUTH_OFFSET(n)) +#define IMX9_CCM_CR_AUTH_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_AUTH_SET_OFFSET(n)) +#define IMX9_CCM_CR_AUTH_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_AUTH_CLR_OFFSET(n)) +#define IMX9_CCM_CR_AUTH_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_AUTH_TOG_OFFSET(n)) + +#define IMX9_CCM_GPR_SH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_OFFSET(n)) +#define IMX9_CCM_GPR_SH_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_SET_OFFSET(n)) +#define IMX9_CCM_GPR_SH_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_CLR_OFFSET(n)) +#define IMX9_CCM_GPR_SH_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_TOG_OFFSET(n)) +#define IMX9_CCM_GPR_SH_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_AUTH_OFFSET(n)) +#define IMX9_CCM_GPR_SH_AUTH_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_AUTH_SET_OFFSET(n)) +#define IMX9_CCM_GPR_SH_AUTH_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_AUTH_CLR_OFFSET(n)) +#define IMX9_CCM_GPR_SH_AUTH_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_AUTH_TOG_OFFSET(n)) + +#define IMX9_CCM_GPR_PR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_OFFSET(n)) +#define IMX9_CCM_GPR_PR_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_SET_OFFSET(n)) +#define IMX9_CCM_GPR_PR_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_CLR_OFFSET(n)) +#define IMX9_CCM_GPR_PR_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_TOG_OFFSET(n)) +#define IMX9_CCM_GPR_PR_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_AUTH_OFFSET(n)) +#define IMX9_CCM_GPR_PR_AUTH_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_AUTH_SET_OFFSET(n)) +#define IMX9_CCM_GPR_PR_AUTH_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_AUTH_CLR_OFFSET(n)) +#define IMX9_CCM_GPR_PR_AUTH_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_AUTH_TOG_OFFSET(n)) + +#define IMX9_CCM_OSCPLL_DIR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_DIR_OFFSET(n)) +#define IMX9_CCM_OSCPLL_LPM_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM_STAT0_OFFSET(n)) +#define IMX9_CCM_OSCPLL_LPM_STAT1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM_STAT1_OFFSET(n)) +#define IMX9_CCM_OSCPLL_LPM0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM0_OFFSET(n)) +#define IMX9_CCM_OSCPLL_LPM1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM1_OFFSET(n)) +#define IMX9_CCM_OSCPLL_LPM_CUR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM1_OFFSET(n)) +#define IMX9_CCM_OSCPLL_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_STAT0_OFFSET(n)) +#define IMX9_CCM_OSCPLL_STAT1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_STAT1_OFFSET(n)) +#define IMX9_CCM_OSCPLL_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_AUTH_OFFSET(n)) + +#define IMX9_CCM_LPCG_DIR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_DIR_OFFSET(n)) +#define IMX9_CCM_LPCG_LPM_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM_STAT0_OFFSET(n)) +#define IMX9_CCM_LPCG_LPM_STAT1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM_STAT1_OFFSET(n)) +#define IMX9_CCM_LPCG_LPM0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM0_OFFSET(n)) +#define IMX9_CCM_LPCG_LPM1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM1_OFFSET(n)) +#define IMX9_CCM_LPCG_LPM_CUR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM1_OFFSET(n)) +#define IMX9_CCM_LPCG_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_STAT0_OFFSET(n)) +#define IMX9_CCM_LPCG_STAT1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_STAT1_OFFSET(n)) +#define IMX9_CCM_LPCG_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_AUTH_OFFSET(n)) + +/* Register bit definitions *************************************************/ + +/* Clock root control (CLOCK_ROOTn_CONTROL, n=0..94) */ + +#define CCM_CR_CTRL_DIV_SHIFT (0) /* Bits 0-7: Divide selected clock by DIV+1 (DIV) */ +#define CCM_CR_CTRL_DIV_MASK (0xff << CCM_CR_CTRL_DIV_SHIFT) +# define CCM_CR_CTRL_DIV(n) (((n)-1) << CCM_CR_CTRL_DIV_SHIFT) /* Divide selected clock by n */ + +#define CCM_CR_CTRL_MUX_SHIFT (8) /* Bits 8-9: Select clock from 8 clock sources (MUX) */ +#define CCM_CR_CTRL_MUX_MASK (0x03 << CCM_CR_CTRL_MUX_SHIFT) +# define CCM_CR_CTRL_MUX_SRCSEL(n) ((n) << CCM_CR_CTRL_MUX_SHIFT) /* Select clock source n */ + + /* Bits 11-23: Reserved */ +#define CCM_CR_CTRL_OFF (1 << 24) /* Bit 24: Shutdown clock root (OFF) */ + /* Bits 25-31: Reserved */ + +/* Clock root working status (CLOCK_ROOTn_STATUS0, n=0..94) */ + +#define CCM_CR_STAT0_DIV_SHIFT (0) /* Bits 0-7: Current clock root DIV setting (DIV) */ +#define CCM_CR_STAT0_DIV_MASK (0xff << CCM_CR_STAT0_DIV_SHIFT) +#define CCM_CR_STAT0_MUX_SHIFT (8) /* Bits 8-9: Current clock root MUX setting (MUX) */ +#define CCM_CR_STAT0_MUX_MASK (0x03 << CCM_CR_STAT0_MUX_SHIFT) + /* Bits 11-23: Reserved */ +#define CCM_CR_STAT0_OFF (1 << 24) /* Bit 24: Current clock root OFF setting (OFF) */ + /* Bits 25-27: Reserved */ +#define CCM_CR_STAT0_SLICE_BUSY (1 << 28) /* Bit 28: Clock generation logic is applying the new setting (SLICE_BUSY) */ +#define CCM_CR_STAT0_CHANGING (1 << 31) /* Bit 31: Clock generation logic is updating currently (CHANGING) */ + +/* Clock root access control (CLOCK_ROOTn_AUTHEN, n=0..94) */ + +#define CCM_CR_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock root can be changed in user mode (TZ_USER) */ +#define CCM_CR_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock root can be changed in non-secure mode (TZ_NS) */ + /* Bit 10: Reserved */ +#define CCM_CR_AUTH_LOCK_TZ (1 << 11) /* Bit 1: Lock TrustZone settings (LOCK_TZ) */ + /* Bits 12-14: Reserved */ +#define CCM_CR_AUTH_LOCK_LIST (1 << 12) /* Bit 15: Lock whitelist settings (LOCK_LIST) */ +#define CCM_CR_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */ +#define CCM_CR_AUTH_WHITE_LIST_MASK (0xffff << CCM_CR_AUTH_WHITE_LIST_SHIFT) + +/* General Purpose Register (GPR_SHAREDn, n=0..7) */ + +#define CCM_GPR_SH_GPR_SHIFT (0) /* Bits 0-31: General purpose register, shared for all CPU domains (GPR) */ +#define CCM_GPR_SH_GPR_MASK (0xffffffff << CCM_GPR_SH_GPR_SHIFT) +#define CCM_GPR_A55_CLK_SEL_SHIFT (0) +#define CCM_GPR_A55_CLK_SEL_MASK (0x01 << CCM_GPR_A55_CLK_SEL_SHIFT) +#define CCM_GPR_A55_CLK_SEL_CCM (0 << 0) +#define CCM_GPR_A55_CLK_SEL_PLL (1 << 0) + +/* General Purpose Register (GPR_SHAREDn_AUTHEN, n=0..7) */ + +#define CCM_GPR_SH_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock root can be changed in user mode (TZ_USER) */ +#define CCM_GPR_SH_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock root can be changed in non-secure mode (TZ_NS) */ + /* Bit 10: Reserved */ +#define CCM_GPR_SH_AUTH_LOCK_TZ (1 << 11) /* Bit 1: Lock TrustZone settings (LOCK_TZ) */ + /* Bits 12-14: Reserved */ +#define CCM_GPR_SH_AUTH_LOCK_LIST (1 << 12) /* Bit 15: Lock whitelist settings (LOCK_LIST) */ +#define CCM_GPR_SH_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */ +#define CCM_GPR_SH_AUTH_WHITE_LIST_MASK (0xffff << CCM_GPR_SH_AUTH_WHITE_LIST_SHIFT) + +/* General Purpose Register (GPR_PRIVATEn, n=1..7) */ + +#define CCM_GPR_PR_GPR_SHIFT (0) /* Bits 0-31: General purpose register, with dedicated bits for each domain (GPR) */ +#define CCM_GPR_PR_GPR_MASK (0xffffffff << CCM_GPR_PR_GPR_SHIFT) + +/* General Purpose Register (GPR_PRIVATEn_AUTHEN, n=1..7) */ + +#define CCM_GPR_PR_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock root can be changed in user mode (TZ_USER) */ +#define CCM_GPR_PR_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock root can be changed in non-secure mode (TZ_NS) */ + /* Bit 10: Reserved */ +#define CCM_GPR_PR_AUTH_LOCK_TZ (1 << 11) /* Bit 1: Lock TrustZone settings (LOCK_TZ) */ + /* Bits 12-14: Reserved */ +#define CCM_GPR_PR_AUTH_LOCK_LIST (1 << 12) /* Bit 15: Lock whitelist settings (LOCK_LIST) */ +#define CCM_GPR_PR_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */ +#define CCM_GPR_PR_AUTH_WHITE_LIST_MASK (0xffff << CCM_CR_AUTH_WHITE_LIST_SHIFT) + +/* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */ + +#define CCM_OSCPLL_DIR_ON (1 << 0) /* Bit 0: Turn on clock source (ON) */ + /* Bits 1-31: Reserved */ + +/* Clock source LPM status (OSCPLLn_LPM_STATUS0/1, n=0..18) */ + +#define CCM_OSCPLL_LPM_STAT_CPU_MODE_SHIFT (0) /* Bits 0-1: Current mode of CPU */ +#define CCM_OSCPLL_LPM_STAT_CPU_MODE_MASK (0x03 << CCM_OSCPLL_LPM_STAT_CPU_MODE_SHIFT) +#define CCM_OSCPLL_LPM_STAT_CPU_TRANS_REQ_SHIFT (2) /* Bit 2: Domain request pending */ +#define CCM_OSCPLL_LPM_STAT_CPU_TRANS_REQ_MASK (0x01 << CCM_OSCPLL_LPM_STAT_CPU_TRANS_REQ_SHIFT) +# define CCM_OSCPLL_LPM_STAT_ON (0) /* CPU is in RUN mode */ +# define CCM_OSCPLL_LPM_STAT_WAIT (1) /* CPU is in WAIT mode */ +# define CCM_OSCPLL_LPM_STAT_STOP (2) /* CPU is in STOP mode */ +# define CCM_OSCPLL_LPM_STAT_SUSPED (3) /* CPU is in SUSPEND mode */ + +/* CPU domain[n] from OSCPLLn_LPM_STATUS0/1 */ + +#define CCM_OSCPLL_LPM_STAT_CPU_DOMAIN_SHIFT (4) +#define CCM_OSCPLL_LPM_STAT_CPU_DOMAIN(n) ((n) * CCM_OSCPLL_LPM_STAT_CPU_DOMAIN_SHIFT) +#define CCM_OSCPLL_LPM_STAT_CPU_MODE_GET(n, v) (((v) >> CCM_OSCPLL_LPM_STAT_CPU_DOMAIN(n)) & CCM_OSCPLL_LPM_STAT_CPU_MODE_MASK) + +/* Clock source LPM mode (OSCPLLn_LPM_0/1 and _CUR, n=0..18) */ + +#define CCM_OSCPLL_LPM_MODE_SHIFT (0) /* Bits 0-2: Current mode of CPU */ +#define CCM_OSCPLL_LPM_MODE_MASK (0x07 << CCM_OSCPLL_LPM_MODE_SHIFT) +# define CCM_OSCPLL_LPM_MODE_OFF (0) /* Clock is off during all modes */ +# define CCM_OSCPLL_LPM_MODE_RUN (1) /* Clock is on in run mode, but off in WAIT and STOP modes */ +# define CCM_OSCPLL_LPM_MODE_RUNWAIT (2) /* Clock is on in run and wait modes, but off in STOP modes */ +# define CCM_OSCPLL_LPM_MODE_RUNWAITSTOP (3) /* Clock is on during all modes, except SUSPEND mode */ +# define CCM_OSCPLL_LPM_MODE_ALL (4) /* Clock is on during all modes */ + +/* CPU domain[n] from OSCPLLn_LPM_0/1 */ + +#define CCM_OSCPLL_LPM_MODE_CPU_DOMAIN_SHIFT (4) +#define CCM_OSCPLL_LPM_MODE_CPU_DOMAIN(n) ((n) * CCM_OSCPLL_LPM_MODE_CPU_DOMAIN_SHIFT) +#define CCM_OSCPLL_LPM_MODE_CPU_MODE_SET(n, v) ((v) & CCM_OSCPLL_LPM_MODE_MASK << CCM_LPCG_LPM_MODE_CPU_DOMAIN(n)) +#define CCM_OSCPLL_LPM_MODE_CPU_MODE_GET(n, v) (((v) >> CCM_LPCG_LPM_STAT_CPU_DOMAIN(n)) & CCM_OSCPLL_LPM_MODE_MASK) + +/* Clock source working status (OSCPLLn_STATUS0, n=0..18) */ + +#define CCM_OSCPLL_STAT0_ON (1 << 0) /* Bit 0: Clock source is turned on (ON) */ + /* Bits 1-3: Reserved */ +#define CCM_OSCPLL_STAT0_STATUS_EARLY (1 << 4) /* Bit 4: Clock source is active (STATUS_EARLY) */ +#define CCM_OSCPLL_STAT0_STATUS_LATE (1 << 5) /* Bit 5: Clock source is ready to use (STATUS_LATE) */ + /* Bits 6-11: Reserved */ +#define CCM_OSCPLL_STAT0_IN_USE (1 << 12) /* Bit 28: Indicates whether the clock source is being used by active clock roots (IN_USE) */ + /* Bits 16-31: Reserved */ + +/* Clock source low power status (OSCPLLn_STATUS1, n=0..18) */ + +#define CCM_OSCPLL_STAT1_DOM_ACTIVE_SHIFT (0) /* Bits 0-15: Domain active */ +#define CCM_OSCPLL_STAT1_DOM_ACTIVE_MASK (0xffff << CCM_OSCPLL_STAT1_DOM_ACTIVE_SHIFT) +#define CCM_OSCPLL_STAT1_DOM_ENABLE_SHIFT (16) /* Bits 16-32: Domain enabled */ +#define CCM_OSCPLL_STAT1_DOM_ENABLE_MASK (0xffff << CCM_OSCPLL_STAT1_DOM_ENABLE_SHIFT) + +/* Clock source access control (OSCPLLn_AUTHEN, n=0..18) */ + +#define CCM_OSCPLL_AUTH_CPULPM (1 << 2) /* Bit 2: CPU Low Power Mode (CPULPM) */ +#define CCM_OSCPLL_AUTH_AUTO_CTRL (1 << 3) /* Bit 2: Auto mode (AUTO_CTRL) */ +#define CCM_OSCPLL_AUTH_LOCK_MODE (1 << 7) /* Bit 7: Lock low power and access mode (LOCK_MODE) */ +#define CCM_OSCPLL_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock source can be changed in user mode (TZ_USER) */ +#define CCM_OSCPLL_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock source can be changed in non-secure mode (TZ_NS) */ + /* Bit 10: Reserved */ +#define CCM_OSCPLL_AUTH_LOCK_TZ (1 << 11) /* Bit 11: Lock TrustZone settings (LOCK_TZ) */ + /* Bits 12-14: Reserved */ +#define CCM_OSCPLL_AUTH_LOCK_LIST (1 << 15) /* Bit 15: Lock whitelist settings (LOCK_LIST) */ +#define CCM_OSCPLL_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */ +#define CCM_OSCPLL_AUTH_WHITE_LIST_MASK (0xffff << CCM_OSCPLL_AUTH_WHITE_LIST_SHIFT) + +/* LPCG direct control (LPCGn_DIRECT, n=0..126) */ + +#define CCM_LPCG_DIR_ON (1 << 0) /* Bit 0: LPCG on (ON) */ + /* Bit 1: Reserved */ +#define CCM_LPCG_ACK_TIMEOUT_EN (1 << 2) /* Bit 2: Ack timeout enable */ + /* Bits 3-31: Reserved */ + +/* Clock source LPM status (LPCGn_LPM_STATUS0/1, n=0..18) */ + +#define CCM_LPCG_LPM_STAT_CPU_MODE_SHIFT (0) /* Bits 0-1: Current mode of CPU */ +#define CCM_LPCG_LPM_STAT_CPU_MODE_MASK (0x03 << CCM_LPCG_LPM_STAT_CPU_MODE_SHIFT) +#define CCM_LPCG_LPM_STAT_CPU_TRANS_REQ_SHIFT (2) /* Bit 2: Domain request pending */ +#define CCM_LPCG_LPM_STAT_CPU_TRANS_REQ_MASK (0x01 << CCM_LPCG_LPM_STAT_CPU_TRANS_REQ_SHIFT) +# define CCM_LPCG_LPM_STAT_ON (0) /* CPU is in RUN mode */ +# define CCM_LPCG_LPM_STAT_WAIT (1) /* CPU is in WAIT mode */ +# define CCM_LPCG_LPM_STAT_STOP (2) /* CPU is in STOP mode */ +# define CCM_LPCG_LPM_STAT_SUSPED (3) /* CPU is in SUSPEND mode */ + +/* CPU domain[n] from OSCPLLn_LPM_STATUS0/1 */ + +#define CCM_LPCG_LPM_STAT_CPU_DOMAIN_SHIFT (4) +#define CCM_LPCG_LPM_STAT_CPU_DOMAIN(n) ((n) * CCM_LPCG_LPM_STAT_CPU_DOMAIN_SHIFT) +#define CCM_LPCG_LPM_STAT_CPU_MODE_GET(n, v) (((v) >> CCM_LPCG_LPM_STAT_CPU_DOMAIN(n)) & CCM_LPCG_LPM_STAT_CPU_MODE_MASK) + +/* Clock source LPM mode (LPCGn_LPM_0/1 and _CUR, n=0..18) */ + +#define CCM_LPCG_LPM_MODE_SHIFT (0) /* Bits 0-2: Current mode of CPU */ +#define CCM_LPCG_LPM_MODE_MASK (0x07 << CCM_LPCG_LPM_MODE_SHIFT) +# define CCM_LPCG_LPM_MODE_OFF (0) /* Clock is off during all modes */ +# define CCM_LPCG_LPM_MODE_RUN (1) /* Clock is on in run mode, but off in WAIT and STOP modes */ +# define CCM_LPCG_LPM_MODE_RUNWAIT (2) /* Clock is on in run and wait modes, but off in STOP modes */ +# define CCM_LPCG_LPM_MODE_RUNWAITSTOP (3) /* Clock is on during all modes, except SUSPEND mode */ +# define CCM_LPCG_LPM_MODE_ALL (4) /* Clock is on during all modes */ + +/* CPU domain[n] from LPCGn_LPM_0/1 */ + +#define CCM_LPCG_LPM_MODE_CPU_DOMAIN_SHIFT (4) +#define CCM_LPCG_LPM_MODE_CPU_DOMAIN(n) ((n) * CCM_LPCG_LPM_MODE_CPU_DOMAIN_SHIFT) +#define CCM_LPCG_LPM_MODE_CPU_MODE_SET(n, v) ((v) & CCM_LPCG_LPM_MODE_MASK << CCM_LPCG_LPM_MODE_CPU_DOMAIN(n)) +#define CCM_LPCG_LPM_MODE_CPU_MODE_GET(n, v) (((v) >> CCM_LPCG_LPM_MODE_CPU_DOMAIN(n)) & CCM_LPCG_LPM_MODE_MASK) + +/* LPCG working status (LPCGn_STATUS0, n=0..126) */ + +#define CCM_LPCG_STAT0_ON (1 << 0) /* Bit 0: Clock source is turned on (ON) */ + /* Bits 1-31 Reserved */ + +/* LPCG low power status (LPCGn_STATUS1, n=0..126) */ + +#define CCM_LPCG_STAT0_ACTIVE_DOMAIN_SHIFT (8) /* Bits 8-11: Domains that own this clock source according to whitelist (ACTIVE_DOMAIN) */ +#define CCM_LPCG_STAT0_ACTIVE_DOMAIN_MASK (0x0f << CCM_LPCG_STAT0_ACTIVE_DOMAIN_SHIFT) +#define CCM_LPCG_STAT0_DOMAIN_ENABLE_SHIFT (8) /* Bits 12-15: Enable status from each domain (DOMAIN_ENABLE) */ +#define CCM_LPCG_STAT0_DOMAIN_ENABLE_MASK (0x0f << CCM_LPCG_STAT0_DOMAIN_ENABLE_SHIFT) + /* Bits 16-31: Reserved */ + +/* LPCG access control (LPCGn_AUTHEN, n=0..126) */ + +#define CCM_LPCG_AUTH_CPULPM (1 << 2) /* Bit 2: CPU Low Power Mode (CPULPM) */ +#define CCM_LPCG_AUTH_LOCK_MODE (1 << 7) /* Bit 7: Lock low power and access mode (LOCK_MODE) */ +#define CCM_LPCG_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock source can be changed in user mode (TZ_USER) */ +#define CCM_LPCG_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock source can be changed in non-secure mode (TZ_NS) */ + /* Bit 10: Reserved */ +#define CCM_LPCG_AUTH_LOCK_TZ (1 << 11) /* Bit 11: Lock TrustZone settings (LOCK_TZ) */ + /* Bits 12-14: Reserved */ +#define CCM_LPCG_AUTH_LOCK_LIST (1 << 15) /* Bit 15: Lock whitelist settings (LOCK_LIST) */ +#define CCM_LPCG_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */ +#define CCM_LPCG_AUTH_WHITE_LIST_MASK (0xffff << CCM_LPCG_AUTH_WHITE_LIST_SHIFT) + +/* Clock roots */ + +#define CCM_CR_A55PERIPH 0 /* CLOCK Root Arm A55 Periph. */ +#define CCM_CR_A55MTRBUS 1 /* CLOCK Root Arm A55 MTR BUS. */ +#define CCM_CR_A55 2 /* CLOCK Root Arm A55. */ +#define CCM_CR_M33 3 /* CLOCK Root M33. */ +#define CCM_CR_SENTINEL 4 /* CLOCK Root Sentinel. */ +#define CCM_CR_BUSWAKEUP 5 /* CLOCK Root Bus Wakeup. */ +#define CCM_CR_BUSAON 6 /* CLOCK Root Bus Aon. */ +#define CCM_CR_WAKEUPAXI 7 /* CLOCK Root Wakeup Axi. */ +#define CCM_CR_SWOTRACE 8 /* CLOCK Root Swo Trace. */ +#define CCM_CR_M33SYSTICK 9 /* CLOCK Root M33 Systick. */ +#define CCM_CR_FLEXIO1 10 /* CLOCK Root Flexio1. */ +#define CCM_CR_FLEXIO2 11 /* CLOCK Root Flexio2. */ +#define CCM_CR_LPIT1 12 /* CLOCK Root Lpit1. */ +#define CCM_CR_LPIT2 13 /* CLOCK Root Lpit2. */ +#define CCM_CR_LPTMR1 14 /* CLOCK Root Lptmr1. */ +#define CCM_CR_LPTMR2 15 /* CLOCK Root Lptmr2. */ +#define CCM_CR_TPM1 16 /* CLOCK Root Tpm1. */ +#define CCM_CR_TPM2 17 /* CLOCK Root Tpm2. */ +#define CCM_CR_TPM3 18 /* CLOCK Root Tpm3. */ +#define CCM_CR_TPM4 19 /* CLOCK Root Tpm4. */ +#define CCM_CR_TPM5 20 /* CLOCK Root Tpm5. */ +#define CCM_CR_TPM6 21 /* CLOCK Root Tpm6. */ +#define CCM_CR_FLEXSPI1 22 /* CLOCK Root Flexspi1. */ +#define CCM_CR_CAN1 23 /* CLOCK Root Can1. */ +#define CCM_CR_CAN2 24 /* CLOCK Root Can2. */ +#define CCM_CR_LPUART1 25 /* CLOCK Root Lpuart1. */ +#define CCM_CR_LPUART2 26 /* CLOCK Root Lpuart2. */ +#define CCM_CR_LPUART3 27 /* CLOCK Root Lpuart3. */ +#define CCM_CR_LPUART4 28 /* CLOCK Root Lpuart4. */ +#define CCM_CR_LPUART5 29 /* CLOCK Root Lpuart5. */ +#define CCM_CR_LPUART6 30 /* CLOCK Root Lpuart6. */ +#define CCM_CR_LPUART7 31 /* CLOCK Root Lpuart7. */ +#define CCM_CR_LPUART8 32 /* CLOCK Root Lpuart8. */ +#define CCM_CR_LPI2C1 33 /* CLOCK Root Lpi2c1. */ +#define CCM_CR_LPI2C2 34 /* CLOCK Root Lpi2c2. */ +#define CCM_CR_LPI2C3 35 /* CLOCK Root Lpi2c3. */ +#define CCM_CR_LPI2C4 36 /* CLOCK Root Lpi2c4. */ +#define CCM_CR_LPI2C5 37 /* CLOCK Root Lpi2c5. */ +#define CCM_CR_LPI2C6 38 /* CLOCK Root Lpi2c6. */ +#define CCM_CR_LPI2C7 39 /* CLOCK Root Lpi2c7. */ +#define CCM_CR_LPI2C8 40 /* CLOCK Root Lpi2c8. */ +#define CCM_CR_LPSPI1 41 /* CLOCK Root Lpspi1. */ +#define CCM_CR_LPSPI2 42 /* CLOCK Root Lpspi2. */ +#define CCM_CR_LPSPI3 43 /* CLOCK Root Lpspi3. */ +#define CCM_CR_LPSPI4 44 /* CLOCK Root Lpspi4. */ +#define CCM_CR_LPSPI5 45 /* CLOCK Root Lpspi5. */ +#define CCM_CR_LPSPI6 46 /* CLOCK Root Lpspi6. */ +#define CCM_CR_LPSPI7 47 /* CLOCK Root Lpspi7. */ +#define CCM_CR_LPSPI8 48 /* CLOCK Root Lpspi8. */ +#define CCM_CR_I3C1 49 /* CLOCK Root I3c1. */ +#define CCM_CR_I3C2 50 /* CLOCK Root I3c2. */ +#define CCM_CR_USDHC1 51 /* CLOCK Root Usdhc1. */ +#define CCM_CR_USDHC2 52 /* CLOCK Root Usdhc2. */ +#define CCM_CR_USDHC3 53 /* CLOCK Root Usdhc3. */ +#define CCM_CR_SAI1 54 /* CLOCK Root Sai1. */ +#define CCM_CR_SAI2 55 /* CLOCK Root Sai2. */ +#define CCM_CR_SAI3 56 /* CLOCK Root Sai3. */ +#define CCM_CR_CCMCKO1 57 /* CLOCK Root Ccm Cko1. */ +#define CCM_CR_CCMCKO2 58 /* CLOCK Root Ccm Cko2. */ +#define CCM_CR_CCMCKO3 59 /* CLOCK Root Ccm Cko3. */ +#define CCM_CR_CCMCKO4 60 /* CLOCK Root Ccm Cko4. */ +#define CCM_CR_HSIO 61 /* CLOCK Root Hsio. */ +#define CCM_CR_HSIOUSBTEST60M 62 /* CLOCK Root Hsio Usb Test 60M. */ +#define CCM_CR_HSIOACSCAN80M 63 /* CLOCK Root Hsio Acscan 80M. */ +#define CCM_CR_HSIOACSCAN480M 64 /* CLOCK Root Hsio Acscan 480M. */ +#define CCM_CR_NIC 65 /* CLOCK Root Nic. */ +#define CCM_CR_NICAPB 66 /* CLOCK Root Nic Apb. */ +#define CCM_CR_MLAPB 67 /* CLOCK Root Ml Apb. */ +#define CCM_CR_ML 68 /* CLOCK Root Ml. */ +#define CCM_CR_MEDIAAXI 69 /* CLOCK Root Media Axi. */ +#define CCM_CR_MEDIAAPB 70 /* CLOCK Root Media Apb. */ +#define CCM_CR_MEDIALDB 71 /* CLOCK Root Media Ldb. */ +#define CCM_CR_MEDIADISPPIX 72 /* CLOCK Root Media Disp Pix. */ +#define CCM_CR_CAMPIX 73 /* CLOCK Root Cam Pix. */ +#define CCM_CR_MIPITESTBYTE 74 /* CLOCK Root Mipi Test Byte. */ +#define CCM_CR_MIPIPHYCFG 75 /* CLOCK Root Mipi Phy Cfg. */ +#define CCM_CR_DRAMALT 76 /* CLOCK Root Dram Alt. */ +#define CCM_CR_DRAMAPB 77 /* CLOCK Root Dram Apb. */ +#define CCM_CR_ADC 78 /* CLOCK Root Adc. */ +#define CCM_CR_PDM 79 /* CLOCK Root Pdm. */ +#define CCM_CR_TSTMR1 80 /* CLOCK Root Tstmr1. */ +#define CCM_CR_TSTMR2 81 /* CLOCK Root Tstmr2. */ +#define CCM_CR_MQS1 82 /* CLOCK Root MQS1. */ +#define CCM_CR_MQS2 83 /* CLOCK Root MQS2. */ +#define CCM_CR_AUDIOXCVR 84 /* CLOCK Root Audio XCVR. */ +#define CCM_CR_SPDIF 85 /* CLOCK Root Spdif. */ +#define CCM_CR_ENET 86 /* CLOCK Root Enet. */ +#define CCM_CR_ENETTIMER1 87 /* CLOCK Root Enet Timer1. */ +#define CCM_CR_ENETTIMER2 88 /* CLOCK Root Enet Timer2. */ +#define CCM_CR_ENETREF 89 /* CLOCK Root Enet Ref. */ +#define CCM_CR_ENETREFPHY 90 /* CLOCK Root Enet Ref Phy. */ +#define CCM_CR_I3C1SLOW 91 /* CLOCK Root I3c1Slow. */ +#define CCM_CR_I3C2SLOW 92 /* CLOCK Root I3c2Slow. */ +#define CCM_CR_USBPHYBURUNIN 93 /* CLOCK Root Usb Phy Burunin. */ +#define CCM_CR_PALCAMESCAN 94 /* CLOCK Root Pal Came Scan. */ + +/* Clock gates */ + +#define CCM_LPCG_A55 0 +#define CCM_LPCG_CM33 1 +#define CCM_LPCG_ARM_TROUT 2 +#define CCM_LPCG_SENTINEL 3 +#define CCM_LPCG_SIM_WAKEUP 4 +#define CCM_LPCG_SIM_AON 5 +#define CCM_LPCG_SIM_MEGA 6 +#define CCM_LPCG_ANADIG 7 +#define CCM_LPCG_SRC 8 +#define CCM_LPCG_CCM 9 +#define CCM_LPCG_GPC 10 +#define CCM_LPCG_ADC1 11 +#define CCM_LPCG_WDOG1 12 +#define CCM_LPCG_WDOG2 13 +#define CCM_LPCG_WDOG3 14 +#define CCM_LPCG_WDOG4 15 +#define CCM_LPCG_WDOG5 16 +#define CCM_LPCG_SEMA1 17 +#define CCM_LPCG_SEMA2 18 +#define CCM_LPCG_MU_A 19 +#define CCM_LPCG_MU_B 20 +#define CCM_LPCG_EDMA3 21 +#define CCM_LPCG_EDMA4 22 +#define CCM_LPCG_ROMCP_A55 23 +#define CCM_LPCG_ROMCP_M33 24 +#define CCM_LPCG_FLEXSPI1 25 +#define CCM_LPCG_AON_TRDC 26 +#define CCM_LPCG_WKUP_TRDC 27 +#define CCM_LPCG_OCOTP 28 +#define CCM_LPCG_BBSM_HP 29 +#define CCM_LPCG_BBSM 30 +#define CCM_LPCG_CSTRACE 31 +#define CCM_LPCG_CSSWO 32 +#define CCM_LPCG_IOMUXC 33 +#define CCM_LPCG_GPIO1 34 +#define CCM_LPCG_GPIO2 35 +#define CCM_LPCG_GPIO3 36 +#define CCM_LPCG_GPIO4 37 +#define CCM_LPCG_FLEXIO1 38 +#define CCM_LPCG_FLEXIO2 39 +#define CCM_LPCG_LPIT1 40 +#define CCM_LPCG_LPIT2 41 +#define CCM_LPCG_LPTMR1 42 +#define CCM_LPCG_LPTMR2 43 +#define CCM_LPCG_TPM1 44 +#define CCM_LPCG_TPM2 45 +#define CCM_LPCG_TPM3 46 +#define CCM_LPCG_TPM4 47 +#define CCM_LPCG_TPM5 48 +#define CCM_LPCG_TPM6 49 +#define CCM_LPCG_CAN1 50 +#define CCM_LPCG_CAN2 51 +#define CCM_LPCG_LPUART1 52 +#define CCM_LPCG_LPUART2 53 +#define CCM_LPCG_LPUART3 54 +#define CCM_LPCG_LPUART4 55 +#define CCM_LPCG_LPUART5 56 +#define CCM_LPCG_LPUART6 57 +#define CCM_LPCG_LPUART7 58 +#define CCM_LPCG_LPUART8 59 +#define CCM_LPCG_LPI2C1 60 +#define CCM_LPCG_LPI2C2 61 +#define CCM_LPCG_LPI2C3 62 +#define CCM_LPCG_LPI2C4 63 +#define CCM_LPCG_LPI2C5 64 +#define CCM_LPCG_LPI2C6 65 +#define CCM_LPCG_LPI2C7 66 +#define CCM_LPCG_LPI2C8 67 +#define CCM_LPCG_LPSPI1 68 +#define CCM_LPCG_LPSPI2 69 +#define CCM_LPCG_LPSPI3 70 +#define CCM_LPCG_LPSPI4 71 +#define CCM_LPCG_LPSPI5 72 +#define CCM_LPCG_LPSPI6 73 +#define CCM_LPCG_LPSPI7 74 +#define CCM_LPCG_LPSPI8 75 +#define CCM_LPCG_I3C1 76 +#define CCM_LPCG_I3C2 77 +#define CCM_LPCG_USDHC1 78 +#define CCM_LPCG_USDHC2 79 +#define CCM_LPCG_USDHC3 80 +#define CCM_LPCG_SAI1 81 +#define CCM_LPCG_SAI2 82 +#define CCM_LPCG_SAI3 83 +#define CCM_LPCG_SSI_W2AO 84 +#define CCM_LPCG_SSI_AO2W 85 +#define CCM_LPCG_MIPI_CSI 86 +#define CCM_LPCG_MIPI_DSI 87 +#define CCM_LPCG_LVDS 88 +#define CCM_LPCG_LCDIF 89 +#define CCM_LPCG_PXP 90 +#define CCM_LPCG_ISI 91 +#define CCM_LPCG_NIC_MEDIA 92 +#define CCM_LPCG_DDR_DFI 93 +#define CCM_LPCG_DDR_CTL 94 +#define CCM_LPCG_DDR_DFI_CTL 95 +#define CCM_LPCG_DDR_SSI 96 +#define CCM_LPCG_DDR_BYPASS 97 +#define CCM_LPCG_DDR_APB 98 +#define CCM_LPCG_DDR_DRAMPLL 99 +#define CCM_LPCG_DDR_CLK_CTL 100 +#define CCM_LPCG_NIC_CENTRAL 101 +#define CCM_LPCG_GIC600 102 +#define CCM_LPCG_NIC_APB 103 +#define CCM_LPCG_USB_CONTROLLER 104 +#define CCM_LPCG_USB_TEST_60M 105 +#define CCM_LPCG_HSIO_TROUT_24M 106 +#define CCM_LPCG_PDM 107 +#define CCM_LPCG_MQS1 108 +#define CCM_LPCG_MQS2 109 +#define CCM_LPCG_AUD_XCVR 110 +#define CCM_LPCG_NICMIX_MECC 111 +#define CCM_LPCG_SPDIF 112 +#define CCM_LPCG_SSI_ML2NIC 113 +#define CCM_LPCG_SSI_MED2NIC 114 +#define CCM_LPCG_SSI_HSIO2NIC 115 +#define CCM_LPCG_SSI_W2NIC 116 +#define CCM_LPCG_SSI_NIC2W 117 +#define CCM_LPCG_SSI_NIC2DDR 118 +#define CCM_LPCG_HSIO_32K 119 +#define CCM_LPCG_ENET1 120 +#define CCM_LPCG_ENET_QOS 121 +#define CCM_LPCG_SYS_CNT 122 +#define CCM_LPCG_TSTMR1 123 +#define CCM_LPCG_TSTMR2 124 +#define CCM_LPCG_TMC 125 +#define CCM_LPCG_PMRO 126 + +/* Shared register indices */ + +#define CCM_SHARED_EXT_CLK 0 +#define CCM_SHARED_A55_CLK 1 +#define CCM_SHARED_DRAM_CLK 2 + +/* Other parameters */ + +#define ROOT_MUX_MAX 4 /* Count of root clock MUX options */ +#define CCM_CR_COUNT 94 /* Count of clock roots */ +#define CCM_LPCG_COUNT 126 /* Counte of clock gates */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* NOTE: The PLL input (IN) clocks are not available in clock tree */ + +enum ccm_clock_name_e +{ + OSC_24M = 0, /* 24MHZ OSCILLATOR. */ + ARM_PLL = 1, /* ARM PLL */ + ARM_PLLOUT = 2, /* ARM PLL OUT */ + SYS_PLL1_IN = 3, /* SYSTEM PLL1 IN */ + SYS_PLL1PFD0_IN = 4, /* SYSTEM PLL1 PFD0 IN */ + SYS_PLL1PFD0 = 5, /* SYSTEM PLL1 PFD0 */ + SYS_PLL1PFD0DIV2 = 6, /* SYSTEM PLL1 PFD0 DIV2 */ + SYS_PLL1PFD1_IN = 7, /* SYSTEM PLL1 PFD1 IN */ + SYS_PLL1PFD1 = 8, /* SYSTEM PLL1 PFD1 */ + SYS_PLL1PFD1DIV2 = 9, /* SYSTEM PLL1 PFD1 DIV2 */ + SYS_PLL1PFD2_IN = 10, /* SYSTEM PLL1 PFD2 IN */ + SYS_PLL1PFD2 = 11, /* SYSTEM PLL1 PFD2 */ + SYS_PLL1PFD2DIV2 = 12, /* SYSTEM PLL1 PFD2 DIV2 */ + AUDIO_PLL1 = 13, /* AUDIO PLL1 */ + AUDIO_PLL1OUT = 14, /* AUDIO PLL1 OUT */ + DRAM_PLL = 15, /* DRAM PLL */ + DRAM_PLLOUT = 16, /* DRAM PLL OUT */ + VIDEO_PLL1 = 17, /* VIDEO PLL1 */ + VIDEO_PLL1OUT = 18, /* VIDEO PLL1 OUT */ + EXT = 19, /* EXT */ +}; + +/* This contains a simple LUT to find the corresponding MUX index per root */ + +static const int g_ccm_root_mux[][ROOT_MUX_MAX] = +{ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Arm A55 Periph */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Arm A55 MTR BUS */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Arm A55 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* M33 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Sentinel */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Bus Wakeup */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Bus Aon */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Wakeup Axi */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Swo Trace */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* M33 Systick */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Flexio1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Flexio2 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpit1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpit2 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lptmr1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lptmr2 */ + {OSC_24M, SYS_PLL1PFD0, AUDIO_PLL1OUT, EXT}, /* Tpm1 */ + {OSC_24M, SYS_PLL1PFD0, AUDIO_PLL1OUT, EXT}, /* Tpm2 */ + {OSC_24M, SYS_PLL1PFD0, AUDIO_PLL1OUT, EXT}, /* Tpm3 */ + {OSC_24M, SYS_PLL1PFD0, AUDIO_PLL1OUT, EXT}, /* Tpm4 */ + {OSC_24M, SYS_PLL1PFD0, AUDIO_PLL1OUT, EXT}, /* Tpm5 */ + {OSC_24M, SYS_PLL1PFD0, AUDIO_PLL1OUT, EXT}, /* Tpm6 */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Flexspi1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Can1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Can2 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpuart1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpuart2 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpuart3 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpuart4 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpuart5 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpuart6 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpuart7 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpuart8 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpi2c1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpi2c2 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpi2c3 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpi2c4 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpi2c5 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpi2c6 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpi2c7 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpi2c8 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpspi1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpspi2 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpspi3 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpspi4 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpspi5 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpspi6 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpspi7 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Lpspi8 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* I3c1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* I3c2 */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Usdhc1 */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Usdhc2 */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Usdhc3 */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, EXT}, /* Sai1 */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, EXT}, /* Sai2 */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, EXT}, /* Sai3 */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, AUDIO_PLL1OUT}, /* Ccm Cko1 */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, VIDEO_PLL1OUT}, /* Ccm Cko2 */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, AUDIO_PLL1OUT}, /* Ccm Cko3 */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, VIDEO_PLL1OUT}, /* Ccm Cko4 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Hsio */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Hsio Usb Test 60M */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Hsio Acscan 80M */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, SYS_PLL1PFD2}, /* Hsio Acscan 480M */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Nic */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Nic Apb */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Ml Apb */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Ml */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Media Axi */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Media Apb */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, SYS_PLL1PFD0}, /* Media Ldb */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, SYS_PLL1PFD0}, /* Media Disp Pix */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, SYS_PLL1PFD0}, /* Cam Pix */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, SYS_PLL1PFD0}, /* Mipi Test Byte */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, SYS_PLL1PFD0}, /* Mipi Phy Cfg */ + {OSC_24M, SYS_PLL1PFD0, SYS_PLL1PFD1, SYS_PLL1PFD2}, /* Dram Alt */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, SYS_PLL1PFD2DIV2}, /* Dram Apb */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Adc */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, EXT}, /* Pdm */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Tstmr1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Tstmr2 */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, EXT}, /* Mqs1 */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, EXT}, /* Mqs2 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, SYS_PLL1PFD2DIV2}, /* Audio XCVR */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, EXT}, /* Spdif */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, SYS_PLL1PFD2DIV2}, /* Enet */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Enet Timer1 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Enet Timer2 */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, SYS_PLL1PFD2DIV2}, /* Enet Ref */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Enet Ref Phy */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* I3c1 Slow */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* I3c2 Slow */ + {OSC_24M, SYS_PLL1PFD0DIV2, SYS_PLL1PFD1DIV2, VIDEO_PLL1OUT}, /* Usb Phy Burunin */ + {OSC_24M, AUDIO_PLL1OUT, VIDEO_PLL1OUT, SYS_PLL1PFD2}, /* Pal Came Scan */ +}; + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_CCM_H */ diff --git a/arch/arm64/src/imx9/hardware/imx93/imx93_dmamux.h b/arch/arm64/src/imx9/hardware/imx93/imx93_dmamux.h new file mode 100644 index 0000000000000..6301856ba547d --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx93/imx93_dmamux.h @@ -0,0 +1,209 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx93/imx93_dmamux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_DMAMUX_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_DMAMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "imx93_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Identify channel MUX from 9th bit */ + +#define EDMA3_MUX_ID 0x0000 +#define EDMA4_MUX_ID 0x0100 +#define EDMA_MUX_ID_MASK 0xff00 +#define EDMA_MUX_MASK 0x00ff + +/* eDMA3 MUXs */ + +#define DMA_REQUEST_DISABLED (0) /**< Channel disabled */ +#define DMA_REQUEST_MUXCAN1 (1 | EDMA3_MUX_ID) /**< CAN1 */ +#define DMA_REQUEST_MUXGPIO1_0 (3 | EDMA3_MUX_ID) /**< GPIO1 channel 0 */ +#define DMA_REQUEST_MUXGPIO1_1 (4 | EDMA3_MUX_ID) /**< GPIO1 channel 1 */ +#define DMA_REQUEST_MUXI3C1TOBUS (5 | EDMA3_MUX_ID) /**< I3C1 To-bus Request */ +#define DMA_REQUEST_MUXI3C1FROMBUS (6 | EDMA3_MUX_ID) /**< I3C1 From-bus Request */ +#define DMA_REQUEST_MUXLPI2C1TX (7 | EDMA3_MUX_ID) /**< LPI2C1 */ +#define DMA_REQUEST_MUXLPI2C1RX (8 | EDMA3_MUX_ID) /**< LPI2C1 */ +#define DMA_REQUEST_MUXLPI2C2TX (9 | EDMA3_MUX_ID) /**< LPI2C2 */ +#define DMA_REQUEST_MUXLPI2C2RX (10 | EDMA3_MUX_ID) /**< LPI2C2 */ +#define DMA_REQUEST_MUXLPSPI1TX (11 | EDMA3_MUX_ID) /**< LPSPI1 Transmit */ +#define DMA_REQUEST_MUXLPSPI1RX (12 | EDMA3_MUX_ID) /**< LPSPI1 Receive */ +#define DMA_REQUEST_MUXLPSPI2TX (13 | EDMA3_MUX_ID) /**< LPSPI2 Transmit */ +#define DMA_REQUEST_MUXLPSPI2RX (14 | EDMA3_MUX_ID) /**< LPSPI2 Receive */ +#define DMA_REQUEST_MUXLPTMR1 (15 | EDMA3_MUX_ID) /**< LPTMR1 Request */ +#define DMA_REQUEST_MUXLPUART1TX (16 | EDMA3_MUX_ID) /**< LPUART1 Transmit */ +#define DMA_REQUEST_MUXLPUART1RX (17 | EDMA3_MUX_ID) /**< LPUART1 Receive */ +#define DMA_REQUEST_MUXLPUART2TX (18 | EDMA3_MUX_ID) /**< LPUART2 Transmit */ +#define DMA_REQUEST_MUXLPUART2RX (19 | EDMA3_MUX_ID) /**< LPUART2 Receive */ +#define DMA_REQUEST_MUXEDGELOCK (20 | EDMA3_MUX_ID) /**< Edgelock enclave DMA Request */ +#define DMA_REQUEST_MUXSAI1TX (21 | EDMA3_MUX_ID) /**< SAI1 Transmit */ +#define DMA_REQUEST_MUXSAI1RX (22 | EDMA3_MUX_ID) /**< SAI1 Receive */ +#define DMA_REQUEST_MUXTPM1_0_2 (23 | EDMA3_MUX_ID) /**< TPM1 request 0 and request 2 */ +#define DMA_REQUEST_MUXTPM1_1_3 (24 | EDMA3_MUX_ID) /**< TPM1 request 1 and request 3 */ +#define DMA_REQUEST_MUXTPM1OVERFLOW (25 | EDMA3_MUX_ID) /**< TPM1 Overflow request */ +#define DMA_REQUEST_MUXTPM2_0_2 (26 | EDMA3_MUX_ID) /**< TPM2 request 0 and request 2 */ +#define DMA_REQUEST_MUXTPM2_1_3 (27 | EDMA3_MUX_ID) /**< TPM2 request 1 and request 3 */ +#define DMA_REQUEST_MUXTPM2OVERFLOW (28 | EDMA3_MUX_ID) /**< TPM2 Overflow request */ +#define DMA_REQUEST_MUXPDM (29 | EDMA3_MUX_ID) /**< PDM */ +#define DMA_REQUEST_MUXADC1 (30 | EDMA3_MUX_ID) /**< ADC1 */ + +#define DMA3_REQUEST_MUX_COUNT (31) + +/* eDMA4 MUXs */ + +#define DMA_REQUEST_MUXCAN2 (1 | EDMA4_MUX_ID) /**< CAN2 */ +#define DMA_REQUEST_MUXGPIO2_0 (2 | EDMA4_MUX_ID) /**< GPIO2 channel 0 */ +#define DMA_REQUEST_MUXGPIO2_1 (3 | EDMA4_MUX_ID) /**< GPIO2 channel 1 */ +#define DMA_REQUEST_MUXGPIO3_0 (4 | EDMA4_MUX_ID) /**< GPIO3 channel 0 */ +#define DMA_REQUEST_MUXGPIO3_1 (5 | EDMA4_MUX_ID) /**< GPIO3 channel 1 */ +#define DMA_REQUEST_MUXI3C2TOBUS (6 | EDMA4_MUX_ID) /**< I3C2 To-bus Request */ +#define DMA_REQUEST_MUXI3C2FROMBUS (7 | EDMA4_MUX_ID) /**< I3C2 From-bus Request */ +#define DMA_REQUEST_MUXLPI2C3TX (8 | EDMA4_MUX_ID) /**< LPI2C3 */ +#define DMA_REQUEST_MUXLPI2C3RX (9 | EDMA4_MUX_ID) /**< LPI2C3 */ +#define DMA_REQUEST_MUXLPI2C4TX (10 | EDMA4_MUX_ID) /**< LPI2C4 */ +#define DMA_REQUEST_MUXLPI2C4RX (11 | EDMA4_MUX_ID) /**< LPI2C4 */ +#define DMA_REQUEST_MUXLPSPI3TX (12 | EDMA4_MUX_ID) /**< LPSPI3 Transmit */ +#define DMA_REQUEST_MUXLPSPI3RX (13 | EDMA4_MUX_ID) /**< LPSPI3 Receive */ +#define DMA_REQUEST_MUXLPSPI4TX (14 | EDMA4_MUX_ID) /**< LPSPI4 Transmit */ +#define DMA_REQUEST_MUXLPSPI4RX (15 | EDMA4_MUX_ID) /**< LPSPI4 Receive */ +#define DMA_REQUEST_MUXLPTMR2 (16 | EDMA4_MUX_ID) /**< LPTMR2 Request */ +#define DMA_REQUEST_MUXLPUART3TX (17 | EDMA4_MUX_ID) /**< LPUART3 Transmit */ +#define DMA_REQUEST_MUXLPUART3RX (18 | EDMA4_MUX_ID) /**< LPUART3 Receive */ +#define DMA_REQUEST_MUXLPUART4TX (19 | EDMA4_MUX_ID) /**< LPUART4 Transmit */ +#define DMA_REQUEST_MUXLPUART4RX (20 | EDMA4_MUX_ID) /**< LPUART4 Receive */ +#define DMA_REQUEST_MUXLPUART5TX (21 | EDMA4_MUX_ID) /**< LPUART5 Transmit */ +#define DMA_REQUEST_MUXLPUART5RX (22 | EDMA4_MUX_ID) /**< LPUART5 Receive */ +#define DMA_REQUEST_MUXLPUART6TX (23 | EDMA4_MUX_ID) /**< LPUART6 Transmit */ +#define DMA_REQUEST_MUXLPUART6RX (24 | EDMA4_MUX_ID) /**< LPUART6 Receive */ +#define DMA_REQUEST_MUXTPM3_0_2 (25 | EDMA4_MUX_ID) /**< TPM3 request 0 and request 2 */ +#define DMA_REQUEST_MUXTPM3_1_3 (26 | EDMA4_MUX_ID) /**< TPM3 request 1 and request 3 */ +#define DMA_REQUEST_MUXTPM3OVERFLOW (27 | EDMA4_MUX_ID) /**< TPM3 Overflow request */ +#define DMA_REQUEST_MUXTPM4_0_2 (28 | EDMA4_MUX_ID) /**< TPM4 request 0 and request 2 */ +#define DMA_REQUEST_MUXTPM4_1_3 (29 | EDMA4_MUX_ID) /**< TPM4 request 1 and request 3 */ +#define DMA_REQUEST_MUXTPM4OVERFLOW (30 | EDMA4_MUX_ID) /**< TPM4 Overflow request */ +#define DMA_REQUEST_MUXTPM5_0_2 (31 | EDMA4_MUX_ID) /**< TPM5 request 0 and request 2 */ +#define DMA_REQUEST_MUXTPM5_1_3 (32 | EDMA4_MUX_ID) /**< TPM5 request 1 and request 3 */ +#define DMA_REQUEST_MUXTPM5OVERFLOW (33 | EDMA4_MUX_ID) /**< TPM5 Overflow request */ +#define DMA_REQUEST_MUXTPM6_0_2 (34 | EDMA4_MUX_ID) /**< TPM6 request 0 and request 2 */ +#define DMA_REQUEST_MUXTPM6_1_3 (35 | EDMA4_MUX_ID) /**< TPM6 request 1 and request 3 */ +#define DMA_REQUEST_MUXTPM6OVERFLOW (36 | EDMA4_MUX_ID) /**< TPM6 Overflow request */ +#define DMA_REQUEST_MUXFLEXIO1_0 (37 | EDMA4_MUX_ID) /**< FlexIO1 Request0 */ +#define DMA_REQUEST_MUXFLEXIO1_1 (38 | EDMA4_MUX_ID) /**< FlexIO1 Request1 */ +#define DMA_REQUEST_MUXFLEXIO1_2 (39 | EDMA4_MUX_ID) /**< FlexIO1 Request2 */ +#define DMA_REQUEST_MUXFLEXIO1_3 (40 | EDMA4_MUX_ID) /**< FlexIO1 Request3 */ +#define DMA_REQUEST_MUXFLEXIO1_4 (41 | EDMA4_MUX_ID) /**< FlexIO1 Request4 */ +#define DMA_REQUEST_MUXFLEXIO1_5 (42 | EDMA4_MUX_ID) /**< FlexIO1 Request5 */ +#define DMA_REQUEST_MUXFLEXIO1_6 (43 | EDMA4_MUX_ID) /**< FlexIO1 Request6 */ +#define DMA_REQUEST_MUXFLEXIO1_7 (44 | EDMA4_MUX_ID) /**< FlexIO1 Request7 */ +#define DMA_REQUEST_MUXFLEXIO2_0 (45 | EDMA4_MUX_ID) /**< FlexIO2 Request0 */ +#define DMA_REQUEST_MUXFLEXIO2_1 (46 | EDMA4_MUX_ID) /**< FlexIO2 Request1 */ +#define DMA_REQUEST_MUXFLEXIO2_2 (47 | EDMA4_MUX_ID) /**< FlexIO2 Request2 */ +#define DMA_REQUEST_MUXFLEXIO2_3 (48 | EDMA4_MUX_ID) /**< FlexIO2 Request3 */ +#define DMA_REQUEST_MUXFLEXIO2_4 (49 | EDMA4_MUX_ID) /**< FlexIO2 Request4 */ +#define DMA_REQUEST_MUXFLEXIO2_5 (50 | EDMA4_MUX_ID) /**< FlexIO2 Request5 */ +#define DMA_REQUEST_MUXFLEXIO2_6 (51 | EDMA4_MUX_ID) /**< FlexIO2 Request6 */ +#define DMA_REQUEST_MUXFLEXIO2_7 (52 | EDMA4_MUX_ID) /**< FlexIO2 Request7 */ +#define DMA_REQUEST_MUXFLEXSPI1TX (53 | EDMA4_MUX_ID) /**< FlexSPI1 Transmit */ +#define DMA_REQUEST_MUXFLEXSPI1RX (54 | EDMA4_MUX_ID) /**< FlexSPI1 Receive */ +#define DMA_REQUEST_MUXSAI2TX (58 | EDMA4_MUX_ID) /**< SAI2 Transmit */ +#define DMA_REQUEST_MUXSAI2RX (59 | EDMA4_MUX_ID) /**< SAI2 Receive */ +#define DMA_REQUEST_MUXSAI3TX (60 | EDMA4_MUX_ID) /**< SAI3 Transmit */ +#define DMA_REQUEST_MUXSAI3RX (61 | EDMA4_MUX_ID) /**< SAI3 Receive */ +#define DMA_REQUEST_MUXGPIO4_0 (62 | EDMA4_MUX_ID) /**< GPIO4 channel 0 */ +#define DMA_REQUEST_MUXGPIO4_1 (63 | EDMA4_MUX_ID) /**< GPIO4 channel 1 */ +#define DMA_REQUEST_MUXSPDIF (65 | EDMA4_MUX_ID) /**< SPDIF */ +#define DMA_REQUEST_MUXSPDIF_1 (66 | EDMA4_MUX_ID) /**< SPDIF */ +#define DMA_REQUEST_MUXENET (67 | EDMA4_MUX_ID) /**< ENET */ +#define DMA_REQUEST_MUXENET_1 (68 | EDMA4_MUX_ID) /**< ENET */ +#define DMA_REQUEST_MUXENET_2 (69 | EDMA4_MUX_ID) /**< ENET */ +#define DMA_REQUEST_MUXENET_3 (70 | EDMA4_MUX_ID) /**< ENET */ +#define DMA_REQUEST_MUXLPI2C5TX (71 | EDMA4_MUX_ID) /**< LPI2C5 */ +#define DMA_REQUEST_MUXLPI2C5RX (72 | EDMA4_MUX_ID) /**< LPI2C5 */ +#define DMA_REQUEST_MUXLPI2C6TX (73 | EDMA4_MUX_ID) /**< LPI2C6 */ +#define DMA_REQUEST_MUXLPI2C6RX (74 | EDMA4_MUX_ID) /**< LPI2C6 */ +#define DMA_REQUEST_MUXLPI2C7TX (75 | EDMA4_MUX_ID) /**< LPI2C7 */ +#define DMA_REQUEST_MUXLPI2C7RX (76 | EDMA4_MUX_ID) /**< LPI2C7 */ +#define DMA_REQUEST_MUXLPI2C8TX (77 | EDMA4_MUX_ID) /**< LPI2C8 */ +#define DMA_REQUEST_MUXLPI2C8RX (78 | EDMA4_MUX_ID) /**< LPI2C8 */ +#define DMA_REQUEST_MUXLPSPI5TX (79 | EDMA4_MUX_ID) /**< LPSPI5 Transmit */ +#define DMA_REQUEST_MUXLPSPI5RX (80 | EDMA4_MUX_ID) /**< LPSPI5 Receive */ +#define DMA_REQUEST_MUXLPSPI6TX (81 | EDMA4_MUX_ID) /**< LPSPI6 Transmit */ +#define DMA_REQUEST_MUXLPSPI6RX (82 | EDMA4_MUX_ID) /**< LPSPI6 Receive */ +#define DMA_REQUEST_MUXLPSPI7TX (83 | EDMA4_MUX_ID) /**< LPSPI7 Transmit */ +#define DMA_REQUEST_MUXLPSPI7RX (84 | EDMA4_MUX_ID) /**< LPSPI7 Receive */ +#define DMA_REQUEST_MUXLPSPI8TX (85 | EDMA4_MUX_ID) /**< LPSPI8 Transmit */ +#define DMA_REQUEST_MUXLPSPI8RX (86 | EDMA4_MUX_ID) /**< LPSPI8 Receive */ +#define DMA_REQUEST_MUXLPUART7TX (87 | EDMA4_MUX_ID) /**< LPUART7 Transmit */ +#define DMA_REQUEST_MUXLPUART7RX (88 | EDMA4_MUX_ID) /**< LPUART7 Receive */ +#define DMA_REQUEST_MUXLPUART8TX (89 | EDMA4_MUX_ID) /**< LPUART8 Transmit */ +#define DMA_REQUEST_MUXLPUART8RX (90 | EDMA4_MUX_ID) /**< LPUART8 Receive */ +#define DMA_REQUEST_MUXENET_QOS (91 | EDMA4_MUX_ID) /**< ENET_QOS */ +#define DMA_REQUEST_MUXENET_QOS_1 (92 | EDMA4_MUX_ID) /**< ENET_QOS */ +#define DMA_REQUEST_MUXENET_QOS_2 (93 | EDMA4_MUX_ID) /**< ENET_QOS */ +#define DMA_REQUEST_MUXENET_QOS_3 (94 | EDMA4_MUX_ID) /**< ENET_QOS */ + +#define DMA4_REQUEST_MUX_COUNT (95) + +/* Combined MUX count (eDMA3 and eDMA4) */ + +#define DMA_REQUEST_MUX_COUNT (DMA3_REQUEST_MUX_COUNT + DMA4_REQUEST_MUX_COUNT) + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_dmamux_get_dmabase + * + * Description: + * Get DMA engine base address from MUX identifier. + * + * Input Parameters: + * dmamux - The DMA MUX identifier. + * + * Returned Value: + * Base address of the associated DMA engine. + * + ****************************************************************************/ + +static inline uintptr_t imx9_dmamux_get_dmabase(uint16_t dmamux) +{ + if ((dmamux & EDMA_MUX_ID_MASK) == EDMA3_MUX_ID) + { + return IMX9_DMA3_BASE; + } + else + { + return IMX9_DMA4_BASE; + } +} + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_DMAMUX_H */ diff --git a/arch/arm64/src/imx9/hardware/imx93/imx93_edma.h b/arch/arm64/src/imx9/hardware/imx93/imx93_edma.h new file mode 100644 index 0000000000000..968b6e09db3fe --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx93/imx93_edma.h @@ -0,0 +1,436 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx93/imx93_edma.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_EDMA_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_EDMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "imx93_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* eDMA3 / eDMA4 Register Offsets */ + +#define IMX9_EDMA_CSR_OFFSET (0x000000) /* Management Page Control Register (CSR) */ +#define IMX9_EDMA_ES_OFFSET (0x000004) /* Management Page Error Status Register (ES) */ +#define IMX9_EDMA_CH_GRPRI_OFFSET(n) (0x000100 + ((n) << 2)) /* Channel n Arbitration Group Register (CHn_GRPRI) */ + +/* eDMA3 only */ + +#define IMX9_EDMA_INT_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT) */ +#define IMX9_EDMA_HRS_OFFSET (0x00000c) /* Management Page Hardware Request Status Register (HRS) */ + +/* eDMA4 only */ + +#define IMX9_EDMA_INT_LOW_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT_LOW) */ +#define IMX9_EDMA_INT_HIGH_OFFSET (0x00000c) /* Management Page Interrupt Request Status Register (INT_HIGH) */ +#define IMX9_EDMA_HRS_LOW_OFFSET (0x000010) /* Management Page Hardware Request Status Register (HRS_LOW) */ +#define IMX9_EDMA_HRS_HIGH_OFFSET (0x000014) /* Management Page Hardware Request Status Register (HRS_HIGH) */ + +/* eDMA3 / eDMA4 Register Addresses */ + +#define IMX9_EDMA_CSR(n) ((n) + IMX9_EDMA_CSR_OFFSET) +#define IMX9_EDMA_ES(n) ((n) + IMX9_EDMA_ES_OFFSET) +#define IMX9_EDMA_CH_GRPRI(n,c) ((n) + IMX9_EDMA_CH_GRPRI_OFFSET(n)) + +/* eDMA3 only */ + +#define IMX9_EDMA_INT (IMX9_DMA3_BASE + IMX9_EDMA_INT_OFFSET) +#define IMX9_EDMA_HRS (IMX9_DMA3_BASE + IMX9_EDMA_HRS_OFFSET) + +/* eDMA4 only */ + +#define IMX9_EDMA_INT_LOW (IMX9_DMA4_BASE + IMX9_EDMA_INT_LOW_OFFSET) +#define IMX9_EDMA_INT_HIGH (IMX9_DMA4_BASE + IMX9_EDMA_INT_HIGH_OFFSET) +#define IMX9_EDMA_HRS_LOW (IMX9_DMA4_BASE + IMX9_EDMA_HRS_LOW_OFFSET) +#define IMX9_EDMA_HRS_HIGH (IMX9_DMA4_BASE + IMX9_EDMA_HRS_HIGH_OFFSET) + +/* eDMA Transfer Control Descriptor (TCD) Register Offsets */ + +#define IMX9_EDMA_CH_CSR_OFFSET (0x000000) /* Channel Control and Status Register (CH0_CSR) */ +#define IMX9_EDMA_CH_ES_OFFSET (0x000004) /* Channel Error Status Register (CH0_ES) */ +#define IMX9_EDMA_CH_INT_OFFSET (0x000008) /* Channel Interrupt Status Register (CH0_INT) */ +#define IMX9_EDMA_CH_SBR_OFFSET (0x00000c) /* Channel System Bus Register (CH0_SBR) */ +#define IMX9_EDMA_CH_PRI_OFFSET (0x000010) /* Channel Priority Register (CH0_PRI) */ +#define IMX9_EDMA_CH_MUX_OFFSET (0x000014) /* Channel Multiplexor Configuration (CH0_MUX) (eDMA4 only) */ +#define IMX9_EDMA_CH_MATTR_OFFSET (0x000018) /* Memory Attributes Register (CH0_MATTR) (eDMA4 only) */ +#define IMX9_EDMA_TCD_SADDR_OFFSET (0x000020) /* TCD Source Address Register (TCD0_SADDR) */ +#define IMX9_EDMA_TCD_SOFF_OFFSET (0x000024) /* TCD Signed Source Address Offset Register (TCD0_SOFF) */ +#define IMX9_EDMA_TCD_ATTR_OFFSET (0x000026) /* TCD Transfer Attributes (TCD0_ATTR) */ +#define IMX9_EDMA_TCD_NBYTES_OFFSET (0x000028) /* TCD Transfer Size (TCD0_NBYTES) */ +#define IMX9_EDMA_TCD_SLAST_SDA_OFFSET (0x00002c) /* TCD Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */ +#define IMX9_EDMA_TCD_DADDR_OFFSET (0x000030) /* TCD Destination Address Register (TCD0_DADDR) */ +#define IMX9_EDMA_TCD_DOFF_OFFSET (0x000034) /* TCD Signed Destination Address Offset Register (TCD0_DOFF) */ +#define IMX9_EDMA_TCD_CITER_OFFSET (0x000036) /* TCD Current Major Loop Count Register (TCD0_CITER) */ +#define IMX9_EDMA_TCD_DLAST_SGA_OFFSET (0x000038) /* TCD Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/ +#define IMX9_EDMA_TCD_CSR_OFFSET (0x00003c) /* TCD Control and Status Register (TCD0_CSR) */ +#define IMX9_EDMA_TCD_BITER_OFFSET (0x00003e) /* TCD Beginning Major Loop Count Register (TCD0_BITER) */ + +/* eDMA 3 and eDMA 4 have TCD instance offsets, but same base offset */ + +#define IMX9_EDMA_TCD_BASE_OFFSET (0x10000) /* Offset to TCD for both eDMA3/4 */ +#define IMX9_EDMA3_TCD_INST_OFFSET (0x10000) /* Per instance TCD offset for eDMA3 */ +#define IMX9_EDMA4_TCD_INST_OFFSET (0x8000) /* Per instance TCD offset for eDMA4 */ +#define IMX9_EDMA_TCD_BASE(n) ((n) + IMX9_EDMA_TCD_BASE_OFFSET) +#define IMX9_EDMA_TCD_INST_OFFSET(n) ((n) == IMX9_DMA3_BASE ? IMX9_EDMA3_TCD_INST_OFFSET : IMX9_EDMA4_TCD_INST_OFFSET) +#define IMX9_EDMA_TCD(n,t) (IMX9_EDMA_TCD_BASE(n) + (t) * IMX9_EDMA_TCD_INST_OFFSET(n)) + +/* eDMA Transfer Control Descriptor (TCD) Register Addresses ****************/ + +#define IMX9_EDMA_CH_CSR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_CSR_OFFSET) +#define IMX9_EDMA_CH_ES(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_ES_OFFSET) +#define IMX9_EDMA_CH_INT(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_INT_OFFSET) +#define IMX9_EDMA_CH_SBR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_SBR_OFFSET) +#define IMX9_EDMA_CH_PRI(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_PRI_OFFSET) +#define IMX9_EDMA_CH_MUX(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_MUX_OFFSET) +#define IMX9_EDMA_TCD_SADDR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_SADDR_OFFSET) +#define IMX9_EDMA_TCD_SOFF(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_SOFF_OFFSET) +#define IMX9_EDMA_TCD_ATTR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_ATTR_OFFSET) +#define IMX9_EDMA_TCD_NBYTES(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_NBYTES_OFFSET) +#define IMX9_EDMA_TCD_SLAST_SDA(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_SLAST_SDA_OFFSET) +#define IMX9_EDMA_TCD_DADDR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_DADDR_OFFSET) +#define IMX9_EDMA_TCD_DOFF(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_DOFF_OFFSET) +#define IMX9_EDMA_TCD_CITER(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_CITER_OFFSET) +#define IMX9_EDMA_TCD_DLAST_SGA(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_DLAST_SGA_OFFSET) +#define IMX9_EDMA_TCD_CSR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_CSR_OFFSET) +#define IMX9_EDMA_TCD_BITER(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_BITER_OFFSET) + +/* eDMA Register Bitfield Definitions ***************************************/ + +/* Management Page Control Register (CSR) */ + + /* Bit 0: Reserved */ +#define EDMA_CSR_EDBG (1 << 1) /* Bit 1: Enable Debug (EDBG) */ +#define EDMA_CSR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration (ERCA) */ + /* Bit 3: Reserved */ +#define EDMA_CSR_HAE (1 << 4) /* Bit 4: Halt After Error (HAE) */ +#define EDMA_CSR_HALT (1 << 5) /* Bit 5: Halt DMA Operations (HALT) */ +#define EDMA_CSR_GCLC (1 << 6) /* Bit 6: Global Channel Linking Control (GCLC) */ +#define EDMA_CSR_GMRC (1 << 7) /* Bit 7: Global Master ID Replication Control (GMRC) */ +#define EDMA_CSR_ECX (1 << 8) /* Bit 8: Cancel Transfer With Error (ECX) */ +#define EDMA_CSR_CX (1 << 9) /* Bit 9: Cancel Transfer (CX) */ + /* Bits 10-23: Reserved */ +#define EDMA_CSR_ACTIVE_ID_SHIFT (24) /* Bits 24-28: Active Channel ID (ACTIVE_ID) */ +#define EDMA_CSR_ACTIVE_ID_MASK (0x1f << EDMA_CSR_ACTIVE_ID_SHIFT) + /* Bits 29-30: Reserved */ +#define EDMA_CSR_ACTIVE (1 << 31) /* Bit 31: DMA Active Status (ACTIVE) */ + +/* Management Page Error Status Register (ES) */ + +#define EDMA_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */ +#define EDMA_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */ +#define EDMA_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */ +#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */ +#define EDMA_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */ +#define EDMA_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */ +#define EDMA_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */ +#define EDMA_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */ +#define EDMA_ES_ECX (1 << 8) /* Bit 8: Transfer Canceled (ECX) */ + /* Bits 9-23: Reserved */ +#define EDMA_ES_ERRCHN_SHIFT (24) /* Bits 24-28: Error Channel Number or Canceled Channel Number (ERRCHN) */ +#define EDMA_ES_ERRCHN_MASK (0x1f << EDMA_ES_ERRCHN_SHIFT) + /* Bits 29-30: Reserved */ +#define EDMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status fields (VALID) */ + +/* Management Page Interrupt Request Status Register (INT) */ + +#define EDMA_INT(n) (1 << (n)) /* Bit n: Interrupt Request Status (INT) */ + +/* Management Page Hardware Request Status Register (HRS) */ + +#define EDMA_HRS(n) (1 << (n)) /* Bit n: Hardware Request Status (HRS) */ + +/* Channel n Arbitration Group Register (CHn_GRPRI) */ + +#define EDMA_CH_GRPRI_SHIFT (0) /* Bits 0-4: Arbitration Group For Channel n (GRPRI) */ +#define EDMA_CH_GRPRI_MASK (0x1f << EDMA_CH_GRPRI_SHIFT) + /* Bits 5-31: Reserved */ + +/* eDMA Transfer Control Descriptor (TCD) Bitfield Definitions **************/ + +/* Channel n Control and Status Register (CHn_CSR) */ + +#define EDMA_CH_CSR_ERQ (1 << 0) /* Bit 0: Enable DMA Request (ERQ) */ +#define EDMA_CH_CSR_EARQ (1 << 1) /* Bit 1: Enable Asynchronous DMA Request in Stop Mode for Channel (EARQ) */ +#define EDMA_CH_CSR_EEI (1 << 2) /* Bit 2: Enable Error Interrupt (EEI) */ +#define EDMA_CH_CSR_EBW (1 << 3) /* Bit 3: Enable Buffered Writes (EBW) */ + /* Bit 4-29: Reserved */ +#define EDMA_CH_CSR_DONE (1 << 30) /* Bit 30: Channel Done (DONE) */ +#define EDMA_CH_CSR_ACTIVE (1 << 31) /* Bit 31: CHannel Active (ACTIVE) */ + +/* Channel n Error Status Register (CHn_ES) */ + +#define EDMA_CH_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */ +#define EDMA_CH_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */ +#define EDMA_CH_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */ +#define EDMA_CH_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */ +#define EDMA_CH_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */ +#define EDMA_CH_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */ +#define EDMA_CH_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */ +#define EDMA_CH_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */ + /* Bit 8-30: Reserved */ +#define EDMA_CH_ES_ERR (1 << 31) /* Bit 31: Error in this channel (ERR) */ + +/* Channel n Interrupt Status Register (CHn_INT) */ + +#define EDMA_CH_INT (1 << 0) /* Bit 0: Interrupt Request (INT) */ + /* Bits 1-31: Reserved */ + +/* Channel n System Bus Register (CHn_SBR) */ + +#define EDMA_CH_SBR_MID_SHIFT (0) /* Bits 0-3: Master ID (MID) */ +#define EDMA_CH_SBR_MID_MASK (0x0f << EDMA_CH_SBR_MID_SHIFT) + /* Bits 4-13: Reserved */ +#define EDMA_CH_SBR_SEC (1 << 14) /* Bit 14: Security Level (SEC) */ +#define EDMA_CH_SBR_PAL (1 << 15) /* Bit 15: Privileged Access Level (PAL) */ +#define EDMA_CH_SBR_EMI (1 << 16) /* Bit 16: Enable Master ID Replication (EMI) */ +#define EDMA_CH_SBR_ATTR_SHIFT (17) /* Bits 17-19: Attribute Output (ATTR) */ +#define EDMA_CH_SBR_ATTR_MASK (0x07 << EDMA_CH_SBR_ATTR_SHIFT) + /* Bits 20-31: Reserved */ + +/* Channel n Priority Register (CHn_PRI) */ + +#define EDMA_CH_PRI_APL_SHIFT (0) /* Bits 0-2: Arbitration Priority Level (APL) */ +#define EDMA_CH_PRI_APL_MASK (0x07 << EDMA_CH_PRI_APL_SHIFT) + /* Bits 3-29: Reserved */ +#define EDMA_CH_PRI_DPA (1 << 30) /* Bit 30: Disable Preempt Ability (DPA) */ +#define EDMA_CH_PRI_ECP (1 << 31) /* Bit 31: Enable Channel Preemption (ECP) */ + +/* Channel Multiplexor Configuration (CHn_MUX) */ + +#define EDMA_CH_SRC_SHIFT (0) /* Bits 0-6: Service Request Source */ +#define EDMA_CH_SRC_MASK (0x7f << EDMA_CH_SRC_SHIFT) + +/* TCDn Source Address Register (TCDn_SADDR) */ + +#define EDMA_TCD_SADDR_SHIFT (0) /* Bits 0-31: Source Address (SADDR) */ +#define EDMA_TCD_SADDR_MASK (0xffffffff << EDMA_TCD_SADDR_SHIFT) + +/* TCDn Signed Source Address Offset Register (TCDn_SOFF) */ + +#define EDMA_TCD_SOFF_SHIFT (0) /* Bits 0-31: Source Address Signed Offset (SOFF) */ +#define EDMA_TCD_SOFF_MASK (0xffffffff << EDMA_TCD_SOFF_SHIFT) + +/* TCDn Transfer Attributes (TCDn_ATTR) */ + +#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination Data Transfer Size (DSIZE) */ +#define EDMA_TCD_ATTR_DSIZE_MASK (0x07 << EDMA_TCD_ATTR_DSIZE_SHIFT) +#define EDMA_TCD_ATTR_DSIZE(n) (((n) << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK) +#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo (DMOD) */ +#define EDMA_TCD_ATTR_DMOD_MASK (0x1f << EDMA_TCD_ATTR_DMOD_SHIFT) +#define EDMA_TCD_ATTR_DMOD(n) (((n) << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK) +#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source Data Transfer Size (SSIZE) */ +#define EDMA_TCD_ATTR_SSIZE_MASK (0x07 << EDMA_TCD_ATTR_SSIZE_SHIFT) +#define EDMA_TCD_ATTR_SSIZE(n) (((n) << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK) +# define EDMA_TCD_ATTR_SSIZE_8BIT (0x00 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */ +# define EDMA_TCD_ATTR_SSIZE_16BIT (0x01 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */ +# define EDMA_TCD_ATTR_SSIZE_32BIT (0x02 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */ +# define EDMA_TCD_ATTR_SSIZE_64BIT (0x03 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */ +# define EDMA_TCD_ATTR_SSIZE_16BYTE (0x04 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-byte */ +# define EDMA_TCD_ATTR_SSIZE_32BYTE (0x05 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte */ +# define EDMA_TCD_ATTR_SSIZE_64BYTE (0x06 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-byte */ + +#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo (SMOD) */ +#define EDMA_TCD_ATTR_SMOD_MASK (0x1f << EDMA_TCD_ATTR_SMOD_SHIFT) +#define EDMA_TCD_ATTR_SMOD(n) (((n) << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK) + +/* TCDn Transfer Size (TCDn_NBYTES) */ + +#define EDMA_TCD_NBYTES_SHIFT (0) /* Bits 0-29: Number of Bytes to Transfer per Service Request (NBYTES) */ +#define EDMA_TCD_NBYTES_MASK (0x3fffffff << EDMA_TCD_NBYTES_SHIFT) +#define EDMA_TCD_NBYTES_MASK_MLOFF (0x03ff << EDMA_TCD_NBYTES_SHIFT) +#define EDMA_TCD_NBYTES_MLOFF_SHIFT (10) /* Bits 10-29: Minor Loop Offset (MLOFF) */ +#define EDMA_TCD_NBYTES_MLOFF_MASK (0x0fffff << EDMA_TCD_NBYTES_MLOFF_SHIFT) +#define EDMA_TCD_NBYTES_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset Enable (DMLOE) */ +#define EDMA_TCD_NBYTES_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable (SMLOE) */ + +/* TCDn Last Source Address Adjustment / Store DADDR Address Register + * (TCDn_SLAST_SDA) + */ + +#define EDMA_TCD_SLAST_SDA_SHIFT (0) /* Bits 0-31: Last Source Address Adjustment / Store DADDR Address (SLAST_SDA) */ +#define EDMA_TCD_SLAST_SDA_MASK (0xffffffff << EDMA_TCD_SLAST_SDA_SHIFT) + +/* TCDn Destination Address Register (TCDn_DADDR) */ + +#define EDMA_TCD_DADDR_SHIFT (0) /* Bits 0-31: Destination Address (DADDR) */ +#define EDMA_TCD_DADDR_MASK (0xffffffff << EDMA_TCD_DADDR_SHIFT) + +/* TCDn Signed Destination Address Offset Register (TCDn_DOFF) */ + +#define EDMA_TCD_DOFF_SHIFT (0) /* Bits 0-15: Destination Address Signed Offset (DOFF) */ +#define EDMA_TCD_DOFF_MASK (0xffff << EDMA_TCD_DOFF_SHIFT) + +/* TCDn Current Major Loop Count Register (TCDn_CITER) */ + +#define EDMA_TCD_CITER_SHIFT (0) /* Bits 0-14: Current Major Iteration Count (CITER) */ +#define EDMA_TCD_CITER_MASK (0x7fff << EDMA_TCD_CITER_SHIFT) +#define EDMA_TCD_CITER_MASK_ELINK (0x01ff << EDMA_TCD_CITER_SHIFT) +#define EDMA_TCD_CITER_LINKCH_SHIFT (9) /* Bits 9-13: Minor Loop Link Channel Number (LINKCH) */ +#define EDMA_TCD_CITER_LINKCH_MASK (0x1f << EDMA_TCD_CITER_LINKCH_SHIFT) +#define EDMA_TCD_CITER_LINKCH(n) (((n) << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT) +#define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */ + +/* TCDn Last Destination Address Adjustment / Scatter Gather Address Register + * (TCDn_DLAST_SGA) + */ + +#define EDMA_TCD_DLAST_SGA_SHIFT (0) /* Bits 0-31: Last Destination Address Adjustment / Scatter Gather Address (DLAST_SGA) */ +#define EDMA_TCD_DLAST_SGA_MASK (0xffffffff << EDMA_TCD_DLAST_SGA_SHIFT) + +/* TCDn Control and Status Register (TCDn_CSR) */ + +#define EDMA_TCD_CSR_START (1 << 0) /* Bit 0: Channel Start (START) */ +#define EDMA_TCD_CSR_INTMAJOR (1 << 1) /* Bit 1: Enable Interrupt if Major count complete (INTMAJOR) */ +#define EDMA_TCD_CSR_INTHALF (1 << 2) /* Bit 2: Enable Interrupt if Major Count Half-complete (INTHALF) */ +#define EDMA_TCD_CSR_DREQ (1 << 3) /* Bit 3: Disable Request (DREQ) */ +#define EDMA_TCD_CSR_ESG (1 << 4) /* Bit 4: Enable Scatter/Gather Processing (ESG) */ +#define EDMA_TCD_CSR_MAJORELINK (1 << 5) /* Bit 5: Enable Link When Major Loop Complete (MAJORELINK) */ +#define EDMA_TCD_CSR_EEOP (1 << 6) /* Bit 6: Enable End-Of-Packet Processing (EEOP) */ +#define EDMA_TCD_CSR_ESDA (1 << 7) /* Bit 7: Enable Store Destination Address (ESDA) */ +#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-12: Major Loop Link Channel Number (MAJORLINKCH) */ +#define EDMA_TCD_CSR_MAJORLINKCH_MASK (0x1f << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) +#define EDMA_TCD_CSR_MAJORLINKCH(n) (((n) << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK) + /* Bit 13: Reserved */ +#define EDMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth Control (BWC) */ +#define EDMA_TCD_CSR_BWC_MASK (0x03 << EDMA_TCD_CSR_BWC_SHIFT) +# define EDMA_TCD_CSR_BWC_NOSTALL (0x00 << EDMA_TCD_CSR_BWC_SHIFT) /* No eDMA engine stalls */ +# define EDMA_TCD_CSR_BWC_HPE (0x01 << EDMA_TCD_CSR_BWC_SHIFT) /* Enable eDMA master high-priority elevation (HPE) mode */ +# define EDMA_TCD_CSR_BWC_4CYCLES (0x02 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 4 cycles after each R/W */ +# define EDMA_TCD_CSR_BWC_8CYCLES (0x03 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 8 cycles after each R/W */ + +/* TCDn Beginning Major Loop Count Register (TCDn_BITER) */ + +#define EDMA_TCD_BITER_SHIFT (0) /* Bits 0-14: Starting Major Iteration Count (BITER) */ +#define EDMA_TCD_BITER_MASK (0x7fff << EDMA_TCD_BITER_SHIFT) +#define EDMA_TCD_BITER_MASK_ELINK (0x01ff << EDMA_TCD_BITER_SHIFT) +#define EDMA_TCD_BITER_LINKCH_SHIFT (9) /* Bits 9-13: Link Channel Number (LINKCH) */ +#define EDMA_TCD_BITER_LINKCH_MASK (0x1f << EDMA_TCD_BITER_LINKCH_SHIFT) +#define EDMA_TCD_BITER_LINKCH(n) (((n) << EDMA_TCD_BITER_LINKCH_SHIFT) & EDMA_TCD_BITER_LINKCH_MASK) +#define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */ + +/* Amount of channels */ + +#define DMA3_CHANNEL_COUNT (31) +#define DMA4_CHANNEL_COUNT (64) +#define IMX9_EDMA_NCHANNELS (DMA3_CHANNEL_COUNT + DMA4_CHANNEL_COUNT) + +/* Amount of interrupt sources */ + +#define DMA3_IRQ_COUNT (32) /* Error interrupt not counted */ +#define DMA4_IRQ_COUNT (32) /* Error interrupt not counted */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* In-memory representation of the 32-byte Transfer Control Descriptor + * (TCD) + */ + +struct imx9_edmatcd_s +{ + uint32_t saddr; /* Offset: 0x0000 TCD Source Address */ + uint16_t soff; /* Offset: 0x0004 TCD Signed Source Address Offset */ + uint16_t attr; /* Offset: 0x0006 TCD Transfer Attributes */ + uint32_t nbytes; /* Offset: 0x0008 TCD Signed Minor Loop Offset / Byte Count */ + uint32_t slast; /* Offset: 0x000c TCD Last Source Address Adjustment */ + uint32_t daddr; /* Offset: 0x0010 TCD Destination Address */ + uint16_t doff; /* Offset: 0x0014 TCD Signed Destination Address Offset */ + uint16_t citer; /* Offset: 0x0016 TCD Current Minor Loop Link, Major Loop Count */ + uint32_t dlastsga; /* Offset: 0x0018 TCD Last Destination Address Adjustment/Scatter Gather Address */ + uint16_t csr; /* Offset: 0x001c TCD Control and Status */ + uint16_t biter; /* Offset: 0x001e TCD Beginning Minor Loop Link, Major Loop Count */ +}; + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_edma_tcdhasmux + * + * Description: + * Check if DMA TCD has TCD.MUX register. + * + * Input Parameters: + * dmabase - The eDMA base. + * + * Returned Value: + * true if TCD.MUX exists; false if not. + * + ****************************************************************************/ + +static inline bool imx9_edma_tcdhasmux(uintptr_t dmabase) +{ + /* Only eDMA4 has TCD.MUX register */ + + return dmabase == IMX9_DMA4_BASE ? true : false; +} + +/**************************************************************************** + * Name: imx9_edma_choffset + * + * Description: + * Channel offset in global channel list for dma base. + * + * Input Parameters: + * base - The eDMA base. + * + * Returned Value: + * Channel offset. + * + ****************************************************************************/ + +static inline uint32_t imx9_edma_choffset(uintptr_t base) +{ + return base == IMX9_DMA3_BASE ? 0 : DMA3_CHANNEL_COUNT; +} + +/**************************************************************************** + * Name: imx9_edma_chmax + * + * Description: + * Max channel in global channel list for dma base. + * + * Input Parameters: + * base - The eDMA base. + * + * Returned Value: + * Channel max. + * + ****************************************************************************/ + +static inline uint32_t imx9_edma_chmax(uintptr_t base) +{ + return base == IMX9_DMA3_BASE ? DMA3_CHANNEL_COUNT : IMX9_EDMA_NCHANNELS; +} + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_EDMA_H */ diff --git a/arch/arm64/src/imx9/hardware/imx93/imx93_gpio.h b/arch/arm64/src/imx9/hardware/imx93/imx93_gpio.h new file mode 100644 index 0000000000000..e00856d6780ac --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx93/imx93_gpio.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx93/imx93_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_GPIO_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "imx93_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IMX9_GPIO_VERID_OFFSET (0x0000) /* Version ID */ +#define IMX9_GPIO_PARAM_OFFSET (0x0004) /* Parameter */ +#define IMX9_GPIO_LOCK_OFFSET (0x000c) /* Lock */ +#define IMX9_GPIO_PCNS_OFFSET (0x0010) /* Pin Control Nonsecure */ +#define IMX9_GPIO_ICNS_OFFSET (0x0014) /* Interrupt Control Nonsecure */ +#define IMX9_GPIO_PCNP_OFFSET (0x0018) /* Pin Control Nonprivilege */ +#define IMX9_GPIO_ICNP_OFFSET (0x001c) /* Interrupt Control Nonprivilege */ +#define IMX9_GPIO_PDOR_OFFSET (0x0040) /* Port Data Output */ +#define IMX9_GPIO_PSOR_OFFSET (0x0044) /* Port Set Output */ +#define IMX9_GPIO_PCOR_OFFSET (0x0048) /* Port Clear Output */ +#define IMX9_GPIO_PTOR_OFFSET (0x004c) /* Port Toggle Output */ +#define IMX9_GPIO_PDIR_OFFSET (0x0050) /* Port Data Input */ +#define IMX9_GPIO_PDDR_OFFSET (0x0054) /* Port Data Direction */ +#define IMX9_GPIO_PIDR_OFFSET (0x0058) /* Port Input Disable */ +#define IMX9_GPIO_P0DR_OFFSET (0x0060) /* Pin Data (0-31 at offsets of n * 4h) */ +#define IMX9_GPIO_ICR0_OFFSET (0x0080) /* Interrupt Control (0-31 at offsets of n * 4h) */ +#define IMX9_GPIO_GICLR_OFFSET (0x0100) /* Global Interrupt Control Low */ +#define IMX9_GPIO_GICHR_OFFSET (0x0104) /* Global Interrupt Control High */ +#define IMX9_GPIO_ISFR0_OFFSET (0x0120) /* Interrupt Status Flag */ +#define IMX9_GPIO_ISFR1_OFFSET (0x0124) /* Interrupt Status Flag */ + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_GPIO_H */ diff --git a/arch/arm64/src/imx9/hardware/imx93/imx93_iomux.h b/arch/arm64/src/imx9/hardware/imx93/imx93_iomux.h new file mode 100644 index 0000000000000..afa9b388f7832 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx93/imx93_iomux.h @@ -0,0 +1,604 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx93/imx93_iomux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_IOMUX_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_IOMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets */ + +#define IOMUXC_MUX_CTL_DAP_TDI_OFFSET (0x0000) +#define IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET (0x0004) +#define IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET (0x0008) +#define IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET (0x000C) +#define IOMUXC_MUX_CTL_GPIO_IO00_OFFSET (0x0010) +#define IOMUXC_MUX_CTL_GPIO_IO01_OFFSET (0x0014) +#define IOMUXC_MUX_CTL_GPIO_IO02_OFFSET (0x0018) +#define IOMUXC_MUX_CTL_GPIO_IO03_OFFSET (0x001C) +#define IOMUXC_MUX_CTL_GPIO_IO04_OFFSET (0x0020) +#define IOMUXC_MUX_CTL_GPIO_IO05_OFFSET (0x0024) +#define IOMUXC_MUX_CTL_GPIO_IO06_OFFSET (0x0028) +#define IOMUXC_MUX_CTL_GPIO_IO07_OFFSET (0x002C) +#define IOMUXC_MUX_CTL_GPIO_IO08_OFFSET (0x0030) +#define IOMUXC_MUX_CTL_GPIO_IO09_OFFSET (0x0034) +#define IOMUXC_MUX_CTL_GPIO_IO10_OFFSET (0x0038) +#define IOMUXC_MUX_CTL_GPIO_IO11_OFFSET (0x003C) +#define IOMUXC_MUX_CTL_GPIO_IO12_OFFSET (0x0040) +#define IOMUXC_MUX_CTL_GPIO_IO13_OFFSET (0x0044) +#define IOMUXC_MUX_CTL_GPIO_IO14_OFFSET (0x0048) +#define IOMUXC_MUX_CTL_GPIO_IO15_OFFSET (0x004C) +#define IOMUXC_MUX_CTL_GPIO_IO16_OFFSET (0x0050) +#define IOMUXC_MUX_CTL_GPIO_IO17_OFFSET (0x0054) +#define IOMUXC_MUX_CTL_GPIO_IO18_OFFSET (0x0058) +#define IOMUXC_MUX_CTL_GPIO_IO19_OFFSET (0x005C) +#define IOMUXC_MUX_CTL_GPIO_IO20_OFFSET (0x0060) +#define IOMUXC_MUX_CTL_GPIO_IO21_OFFSET (0x0064) +#define IOMUXC_MUX_CTL_GPIO_IO22_OFFSET (0x0068) +#define IOMUXC_MUX_CTL_GPIO_IO23_OFFSET (0x006C) +#define IOMUXC_MUX_CTL_GPIO_IO24_OFFSET (0x0070) +#define IOMUXC_MUX_CTL_GPIO_IO25_OFFSET (0x0074) +#define IOMUXC_MUX_CTL_GPIO_IO26_OFFSET (0x0078) +#define IOMUXC_MUX_CTL_GPIO_IO27_OFFSET (0x007C) +#define IOMUXC_MUX_CTL_GPIO_IO28_OFFSET (0x0080) +#define IOMUXC_MUX_CTL_GPIO_IO29_OFFSET (0x0084) +#define IOMUXC_MUX_CTL_CCM_CLKO1_OFFSET (0x0088) +#define IOMUXC_MUX_CTL_CCM_CLKO2_OFFSET (0x008C) +#define IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET (0x0090) +#define IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET (0x0094) +#define IOMUXC_MUX_CTL_ENET1_MDC_OFFSET (0x0098) +#define IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET (0x009C) +#define IOMUXC_MUX_CTL_ENET1_TD3_OFFSET (0x00A0) +#define IOMUXC_MUX_CTL_ENET1_TD2_OFFSET (0x00A4) +#define IOMUXC_MUX_CTL_ENET1_TD1_OFFSET (0x00A8) +#define IOMUXC_MUX_CTL_ENET1_TD0_OFFSET (0x00AC) +#define IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET (0x00B0) +#define IOMUXC_MUX_CTL_ENET1_TXC_OFFSET (0x00B4) +#define IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET (0x00B8) +#define IOMUXC_MUX_CTL_ENET1_RXC_OFFSET (0x00BC) +#define IOMUXC_MUX_CTL_ENET1_RD0_OFFSET (0x00C0) +#define IOMUXC_MUX_CTL_ENET1_RD1_OFFSET (0x00C4) +#define IOMUXC_MUX_CTL_ENET1_RD2_OFFSET (0x00C8) +#define IOMUXC_MUX_CTL_ENET1_RD3_OFFSET (0x00CC) +#define IOMUXC_MUX_CTL_ENET2_MDC_OFFSET (0x00D0) +#define IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET (0x00D4) +#define IOMUXC_MUX_CTL_ENET2_TD3_OFFSET (0x00D8) +#define IOMUXC_MUX_CTL_ENET2_TD2_OFFSET (0x00DC) +#define IOMUXC_MUX_CTL_ENET2_TD1_OFFSET (0x00E0) +#define IOMUXC_MUX_CTL_ENET2_TD0_OFFSET (0x00E4) +#define IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET (0x00E8) +#define IOMUXC_MUX_CTL_ENET2_TXC_OFFSET (0x00EC) +#define IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET (0x00F0) +#define IOMUXC_MUX_CTL_ENET2_RXC_OFFSET (0x00F4) +#define IOMUXC_MUX_CTL_ENET2_RD0_OFFSET (0x00F8) +#define IOMUXC_MUX_CTL_ENET2_RD1_OFFSET (0x00FC) +#define IOMUXC_MUX_CTL_ENET2_RD2_OFFSET (0x0100) +#define IOMUXC_MUX_CTL_ENET2_RD3_OFFSET (0x0104) +#define IOMUXC_MUX_CTL_SD1_CLK_OFFSET (0x0108) +#define IOMUXC_MUX_CTL_SD1_CMD_OFFSET (0x010C) +#define IOMUXC_MUX_CTL_SD1_DATA0_OFFSET (0x0110) +#define IOMUXC_MUX_CTL_SD1_DATA1_OFFSET (0x0114) +#define IOMUXC_MUX_CTL_SD1_DATA2_OFFSET (0x0118) +#define IOMUXC_MUX_CTL_SD1_DATA3_OFFSET (0x011C) +#define IOMUXC_MUX_CTL_SD1_DATA4_OFFSET (0x0120) +#define IOMUXC_MUX_CTL_SD1_DATA5_OFFSET (0x0124) +#define IOMUXC_MUX_CTL_SD1_DATA6_OFFSET (0x0128) +#define IOMUXC_MUX_CTL_SD1_DATA7_OFFSET (0x012C) +#define IOMUXC_MUX_CTL_SD1_STROBE_OFFSET (0x0130) +#define IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET (0x0134) +#define IOMUXC_MUX_CTL_SD3_CLK_OFFSET (0x0138) +#define IOMUXC_MUX_CTL_SD3_CMD_OFFSET (0x013C) +#define IOMUXC_MUX_CTL_SD3_DATA0_OFFSET (0x0140) +#define IOMUXC_MUX_CTL_SD3_DATA1_OFFSET (0x0144) +#define IOMUXC_MUX_CTL_SD3_DATA2_OFFSET (0x0148) +#define IOMUXC_MUX_CTL_SD3_DATA3_OFFSET (0x014C) +#define IOMUXC_MUX_CTL_SD2_CD_B_OFFSET (0x0150) +#define IOMUXC_MUX_CTL_SD2_CLK_OFFSET (0x0154) +#define IOMUXC_MUX_CTL_SD2_CMD_OFFSET (0x0158) +#define IOMUXC_MUX_CTL_SD2_DATA0_OFFSET (0x015C) +#define IOMUXC_MUX_CTL_SD2_DATA1_OFFSET (0x0160) +#define IOMUXC_MUX_CTL_SD2_DATA2_OFFSET (0x0164) +#define IOMUXC_MUX_CTL_SD2_DATA3_OFFSET (0x0168) +#define IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET (0x016C) +#define IOMUXC_MUX_CTL_I2C1_SCL_OFFSET (0x0170) +#define IOMUXC_MUX_CTL_I2C1_SDA_OFFSET (0x0174) +#define IOMUXC_MUX_CTL_I2C2_SCL_OFFSET (0x0178) +#define IOMUXC_MUX_CTL_I2C2_SDA_OFFSET (0x017C) +#define IOMUXC_MUX_CTL_UART1_RXD_OFFSET (0x0180) +#define IOMUXC_MUX_CTL_UART1_TXD_OFFSET (0x0184) +#define IOMUXC_MUX_CTL_UART2_RXD_OFFSET (0x0188) +#define IOMUXC_MUX_CTL_UART2_TXD_OFFSET (0x018C) +#define IOMUXC_MUX_CTL_PDM_CLK_OFFSET (0x0190) +#define IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET (0x0194) +#define IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET (0x0198) +#define IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET (0x019C) +#define IOMUXC_MUX_CTL_SAI1_TXC_OFFSET (0x01A0) +#define IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET (0x01A4) +#define IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET (0x01A8) +#define IOMUXC_MUX_CTL_WDOG_ANY_OFFSET (0x01AC) + +#define IOMUXC_PAD_CTL_DAP_TDI_OFFSET (0x01B0) +#define IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET (0x01B4) +#define IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET (0x01B8) +#define IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET (0x01BC) +#define IOMUXC_PAD_CTL_GPIO_IO00_OFFSET (0x01C0) +#define IOMUXC_PAD_CTL_GPIO_IO01_OFFSET (0x01C4) +#define IOMUXC_PAD_CTL_GPIO_IO02_OFFSET (0x01C8) +#define IOMUXC_PAD_CTL_GPIO_IO03_OFFSET (0x01CC) +#define IOMUXC_PAD_CTL_GPIO_IO04_OFFSET (0x01D0) +#define IOMUXC_PAD_CTL_GPIO_IO05_OFFSET (0x01D4) +#define IOMUXC_PAD_CTL_GPIO_IO06_OFFSET (0x01D8) +#define IOMUXC_PAD_CTL_GPIO_IO07_OFFSET (0x01DC) +#define IOMUXC_PAD_CTL_GPIO_IO08_OFFSET (0x01E0) +#define IOMUXC_PAD_CTL_GPIO_IO09_OFFSET (0x01E4) +#define IOMUXC_PAD_CTL_GPIO_IO10_OFFSET (0x01E8) +#define IOMUXC_PAD_CTL_GPIO_IO11_OFFSET (0x01EC) +#define IOMUXC_PAD_CTL_GPIO_IO12_OFFSET (0x01F0) +#define IOMUXC_PAD_CTL_GPIO_IO13_OFFSET (0x01F4) +#define IOMUXC_PAD_CTL_GPIO_IO14_OFFSET (0x01F8) +#define IOMUXC_PAD_CTL_GPIO_IO15_OFFSET (0x01FC) +#define IOMUXC_PAD_CTL_GPIO_IO16_OFFSET (0x0200) +#define IOMUXC_PAD_CTL_GPIO_IO17_OFFSET (0x0204) +#define IOMUXC_PAD_CTL_GPIO_IO18_OFFSET (0x0208) +#define IOMUXC_PAD_CTL_GPIO_IO19_OFFSET (0x020C) +#define IOMUXC_PAD_CTL_GPIO_IO20_OFFSET (0x0210) +#define IOMUXC_PAD_CTL_GPIO_IO21_OFFSET (0x0214) +#define IOMUXC_PAD_CTL_GPIO_IO22_OFFSET (0x0218) +#define IOMUXC_PAD_CTL_GPIO_IO23_OFFSET (0x021C) +#define IOMUXC_PAD_CTL_GPIO_IO24_OFFSET (0x0220) +#define IOMUXC_PAD_CTL_GPIO_IO25_OFFSET (0x0224) +#define IOMUXC_PAD_CTL_GPIO_IO26_OFFSET (0x0228) +#define IOMUXC_PAD_CTL_GPIO_IO27_OFFSET (0x022C) +#define IOMUXC_PAD_CTL_GPIO_IO28_OFFSET (0x0230) +#define IOMUXC_PAD_CTL_GPIO_IO29_OFFSET (0x0234) +#define IOMUXC_PAD_CTL_CCM_CLKO1_OFFSET (0x0238) +#define IOMUXC_PAD_CTL_CCM_CLKO2_OFFSET (0x023C) +#define IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET (0x0240) +#define IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET (0x0244) +#define IOMUXC_PAD_CTL_ENET1_MDC_OFFSET (0x0248) +#define IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET (0x024C) +#define IOMUXC_PAD_CTL_ENET1_TD3_OFFSET (0x0250) +#define IOMUXC_PAD_CTL_ENET1_TD2_OFFSET (0x0254) +#define IOMUXC_PAD_CTL_ENET1_TD1_OFFSET (0x0258) +#define IOMUXC_PAD_CTL_ENET1_TD0_OFFSET (0x025C) +#define IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET (0x0260) +#define IOMUXC_PAD_CTL_ENET1_TXC_OFFSET (0x0264) +#define IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET (0x0268) +#define IOMUXC_PAD_CTL_ENET1_RXC_OFFSET (0x026C) +#define IOMUXC_PAD_CTL_ENET1_RD0_OFFSET (0x0270) +#define IOMUXC_PAD_CTL_ENET1_RD1_OFFSET (0x0274) +#define IOMUXC_PAD_CTL_ENET1_RD2_OFFSET (0x0278) +#define IOMUXC_PAD_CTL_ENET1_RD3_OFFSET (0x027C) +#define IOMUXC_PAD_CTL_ENET2_MDC_OFFSET (0x0280) +#define IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET (0x0284) +#define IOMUXC_PAD_CTL_ENET2_TD3_OFFSET (0x0288) +#define IOMUXC_PAD_CTL_ENET2_TD2_OFFSET (0x028C) +#define IOMUXC_PAD_CTL_ENET2_TD1_OFFSET (0x01B0) +#define IOMUXC_PAD_CTL_ENET2_TD0_OFFSET (0x01B0) +#define IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET (0x01B0) +#define IOMUXC_PAD_CTL_ENET2_TXC_OFFSET (0x029C) +#define IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET (0x02A0) +#define IOMUXC_PAD_CTL_ENET2_RXC_OFFSET (0x02A4) +#define IOMUXC_PAD_CTL_ENET2_RD0_OFFSET (0x02A8) +#define IOMUXC_PAD_CTL_ENET2_RD1_OFFSET (0x02AC) +#define IOMUXC_PAD_CTL_ENET2_RD2_OFFSET (0x02B0) +#define IOMUXC_PAD_CTL_ENET2_RD3_OFFSET (0x02B4) +#define IOMUXC_PAD_CTL_SD1_CLK_OFFSET (0x02B8) +#define IOMUXC_PAD_CTL_SD1_CMD_OFFSET (0x02BC) +#define IOMUXC_PAD_CTL_SD1_DATA0_OFFSET (0x02C0) +#define IOMUXC_PAD_CTL_SD1_DATA1_OFFSET (0x02C4) +#define IOMUXC_PAD_CTL_SD1_DATA2_OFFSET (0x02C8) +#define IOMUXC_PAD_CTL_SD1_DATA3_OFFSET (0x02CC) +#define IOMUXC_PAD_CTL_SD1_DATA4_OFFSET (0x02D0) +#define IOMUXC_PAD_CTL_SD1_DATA5_OFFSET (0x02D4) +#define IOMUXC_PAD_CTL_SD1_DATA6_OFFSET (0x02D8) +#define IOMUXC_PAD_CTL_SD1_DATA7_OFFSET (0x02DC) +#define IOMUXC_PAD_CTL_SD1_STROBE_OFFSET (0x02E0) +#define IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET (0x02E4) +#define IOMUXC_PAD_CTL_SD3_CLK_OFFSET (0x02E8) +#define IOMUXC_PAD_CTL_SD3_CMD_OFFSET (0x02EC) +#define IOMUXC_PAD_CTL_SD3_DATA0_OFFSET (0x02F0) +#define IOMUXC_PAD_CTL_SD3_DATA1_OFFSET (0x02F4) +#define IOMUXC_PAD_CTL_SD3_DATA2_OFFSET (0x02F8) +#define IOMUXC_PAD_CTL_SD3_DATA3_OFFSET (0x02FC) +#define IOMUXC_PAD_CTL_SD2_CD_B_OFFSET (0x0300) +#define IOMUXC_PAD_CTL_SD2_CLK_OFFSET (0x0304) +#define IOMUXC_PAD_CTL_SD2_CMD_OFFSET (0x0308) +#define IOMUXC_PAD_CTL_SD2_DATA0_OFFSET (0x030C) +#define IOMUXC_PAD_CTL_SD2_DATA1_OFFSET (0x0310) +#define IOMUXC_PAD_CTL_SD2_DATA2_OFFSET (0x0314) +#define IOMUXC_PAD_CTL_SD2_DATA3_OFFSET (0x0318) +#define IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET (0x031C) +#define IOMUXC_PAD_CTL_I2C1_SCL_OFFSET (0x0320) +#define IOMUXC_PAD_CTL_I2C1_SDA_OFFSET (0x0324) +#define IOMUXC_PAD_CTL_I2C2_SCL_OFFSET (0x0328) +#define IOMUXC_PAD_CTL_I2C2_SDA_OFFSET (0x032C) +#define IOMUXC_PAD_CTL_UART1_RXD_OFFSET (0x0330) +#define IOMUXC_PAD_CTL_UART1_TXD_OFFSET (0x0334) +#define IOMUXC_PAD_CTL_UART2_RXD_OFFSET (0x0338) +#define IOMUXC_PAD_CTL_UART2_TXD_OFFSET (0x033C) +#define IOMUXC_PAD_CTL_PDM_CLK_OFFSET (0x0340) +#define IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET (0x0344) +#define IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET (0x0348) +#define IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET (0x034C) +#define IOMUXC_PAD_CTL_SAI1_TXC_OFFSET (0x0350) +#define IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET (0x0354) +#define IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET (0x0358) +#define IOMUXC_PAD_CTL_WDOG_ANY_OFFSET (0x035C) + +#define CAN1_IPP_IND_CANRX_SELECT_INPUT_OFFSET (0x0360) +#define CAN2_IPP_IND_CANRX_SELECT_INPUT_OFFSET (0x0364) +#define CCMSRCGPCMIX_EXT1_CLK_SELECT_INPUT_OFFSET (0x0368) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0_OFFSET (0x036C) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1_OFFSET (0x0370) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2_OFFSET (0x0374) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3_OFFSET (0x0378) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4_OFFSET (0x037C) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5_OFFSET (0x0380) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6_OFFSET (0x0384) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7_OFFSET (0x0388) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8_OFFSET (0x038C) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9_OFFSET (0x0390) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10_OFFSET (0x0394) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11_OFFSET (0x0398) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13_OFFSET (0x039C) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14_OFFSET (0x03A0) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15_OFFSET (0x03A4) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16_OFFSET (0x03A8) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17_OFFSET (0x03AC) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18_OFFSET (0x03B0) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20_OFFSET (0x03B4) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22_OFFSET (0x03B8) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23_OFFSET (0x03BC) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24_OFFSET (0x03C0) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25_OFFSET (0x03C4) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27_OFFSET (0x03C8) +#define I3C2_PIN_SCL_IN_SELECT_INPUT_OFFSET (0x03CC) +#define I3C2_PIN_SDA_IN_SELECT_INPUT_OFFSET (0x03D0) +#define JTAG_MUX_TCK_SELECT_INPUT_OFFSET (0x03D4) +#define JTAG_MUX_TDI_SELECT_INPUT_OFFSET (0x03D8) +#define JTAG_MUX_TMS_SELECT_INPUT_OFFSET (0x03DC) +#define LP12C3_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x03E0) +#define LPI12C3_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x03E4) +#define LP12C5_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x03E8) +#define LP12C5_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x03EC) +#define LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x03F0) +#define LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x03F4) +#define LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x03F8) +#define LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x03FC) +#define LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x0400) +#define LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x0404) +#define LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_O_OFFSET (0x0408) +#define LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1_OFFSET (0x040C) +#define LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2_OFFSET (0x0410) +#define LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INP_OFFSET (0x0414) +#define LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x0418) +#define LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x041C) +#define LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INP_OFFSET (0x0420) +#define LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x0424) +#define LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x0428) +#define LPUARTS_IPP_IND_LPUART_CTS_N_SELECT_INP_OFFSET (0x042C) +#define LPUARTS_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x0430) +#define LPUARTS_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x0434) +#define SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT_OFFSET (0x0448) +#define SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET (0x044c) +#define SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET (0x0450) +#define SPDIF_SPDIF_I_SELECT_INPUT_OFFSET (0x0454) +#define USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT_OFFSET (0x0458) +#define USDHC3_IPP_CMD_IN_SELECT_INPUT_OFFSET (0x045C) +#define USDHC3_IPP_DATO_IN_SELECT_INPUT_OFFSET (0x0460) +#define USDHC3_IPP_DAT1_IN_SELECT_INPUT_OFFSET (0x0464) +#define USDHC3_IPP_DAT2_IN_SELECT_INPUT_OFFSET (0x0468) +#define USDHC3_IPP_DAT3_IN_SELECT_INPUT_OFFSET (0x046C) + +/* Register addresses */ + +#define IOMUXC_MUX_CTL_DAP_TDI (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TDI_OFFSET) +#define IOMUXC_MUX_CTL_DAP_TMS_SWDIO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET) +#define IOMUXC_MUX_CTL_DAP_TCLK_SWCLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET) +#define IOMUXC_MUX_CTL_DAP_TDO_TRACESWO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO00 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO00_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO01 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO01_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO02 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO02_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO03 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO03_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO04 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO04_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO05 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO05_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO06 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO06_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO07 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO07_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO08 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO08_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO09 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO09_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO10 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO10_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO11 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO11_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO12 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO12_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO13 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO13_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO14 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO14_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO15 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO15_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO16 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO16_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO17 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO17_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO18 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO18_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO19 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO19_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO20 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO20_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO21 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO21_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO22 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO22_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO23 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO23_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO24 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO24_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO25 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO25_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO26 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO26_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO27 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO27_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO28 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO28_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO29 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO29_OFFSET) +#define IOMUXC_MUX_CTL_CCM_CLKO1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO1_OFFSET) +#define IOMUXC_MUX_CTL_CCM_CLKO2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO2_OFFSET) +#define IOMUXC_MUX_CTL_CCM_CLKO3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET) +#define IOMUXC_MUX_CTL_CCM_CLKO4 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_MDC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_MDC_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD3_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD2_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD1_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD0_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TXC_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RXC_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD0_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD1_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD2_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD3_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_MDC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_MDC_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD3_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD2_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD1_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD0_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TXC_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RXC_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD0_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD1_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD2_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD3_OFFSET) +#define IOMUXC_MUX_CTL_SD1_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_CLK_OFFSET) +#define IOMUXC_MUX_CTL_SD1_CMD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_CMD_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA0_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA1_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA2_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA3_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA4 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA4_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA5 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA5_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA6 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA6_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA7 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA7_OFFSET) +#define IOMUXC_MUX_CTL_SD1_STROBE (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_STROBE_OFFSET) +#define IOMUXC_MUX_CTL_SD2_VSELECT (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET) +#define IOMUXC_MUX_CTL_SD3_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_CLK_OFFSET) +#define IOMUXC_MUX_CTL_SD3_CMD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_CMD_OFFSET) +#define IOMUXC_MUX_CTL_SD3_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA0_OFFSET) +#define IOMUXC_MUX_CTL_SD3_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA1_OFFSET) +#define IOMUXC_MUX_CTL_SD3_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA2_OFFSET) +#define IOMUXC_MUX_CTL_SD3_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA3_OFFSET) +#define IOMUXC_MUX_CTL_SD2_CD_B (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_CD_B_OFFSET) +#define IOMUXC_MUX_CTL_SD2_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_CLK_OFFSET) +#define IOMUXC_MUX_CTL_SD2_CMD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_CMD_OFFSET) +#define IOMUXC_MUX_CTL_SD2_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA0_OFFSET) +#define IOMUXC_MUX_CTL_SD2_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA1_OFFSET) +#define IOMUXC_MUX_CTL_SD2_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA2_OFFSET) +#define IOMUXC_MUX_CTL_SD2_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA3_OFFSET) +#define IOMUXC_MUX_CTL_SD2_RESET_B (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET) +#define IOMUXC_MUX_CTL_I2C1_SCL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C1_SCL_OFFSET) +#define IOMUXC_MUX_CTL_I2C1_SDA (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C1_SDA_OFFSET) +#define IOMUXC_MUX_CTL_I2C2_SCL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C2_SCL_OFFSET) +#define IOMUXC_MUX_CTL_I2C2_SDA (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C2_SDA_OFFSET) +#define IOMUXC_MUX_CTL_UART1_RXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART1_RXD_OFFSET) +#define IOMUXC_MUX_CTL_UART1_TXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART1_TXD_OFFSET) +#define IOMUXC_MUX_CTL_UART2_RXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART2_RXD_OFFSET) +#define IOMUXC_MUX_CTL_UART2_TXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART2_TXD_OFFSET) +#define IOMUXC_MUX_CTL_PDM_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_PDM_CLK_OFFSET) +#define IOMUXC_MUX_CTL_PDM_BIT_STREAM0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET) +#define IOMUXC_MUX_CTL_PDM_BIT_STREAM1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET) +#define IOMUXC_MUX_CTL_SAI1_TXFS (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET) +#define IOMUXC_MUX_CTL_SAI1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_TXC_OFFSET) +#define IOMUXC_MUX_CTL_SAI1_TXD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET) +#define IOMUXC_MUX_CTL_SAI1_RXD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET) +#define IOMUXC_MUX_CTL_WDOG_ANY (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_WDOG_ANY_OFFSET) + +#define IOMUXC_PAD_CTL_DAP_TDI (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TDI_OFFSET) +#define IOMUXC_PAD_CTL_DAP_TMS_SWDIO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET) +#define IOMUXC_PAD_CTL_DAP_TCLK_SWCLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET) +#define IOMUXC_PAD_CTL_DAP_TDO_TRACESWO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO00 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO00_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO01 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO01_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO02 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO02_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO03 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO03_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO04 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO04_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO05 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO05_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO06 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO06_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO07 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO07_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO08 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO08_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO09 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO09_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO10 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO10_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO11 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO11_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO12 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO12_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO13 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO13_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO14 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO14_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO15 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO15_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO16 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO16_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO17 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO17_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO18 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO18_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO19 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO19_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO20 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO20_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO21 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO21_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO22 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO22_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO23 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO23_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO24 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO24_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO25 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO25_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO26 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO26_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO27 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO27_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO28 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO28_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO29 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO29_OFFSET) +#define IOMUXC_PAD_CTL_CCM_CLKO1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO1_OFFSET) +#define IOMUXC_PAD_CTL_CCM_CLKO2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO2_OFFSET) +#define IOMUXC_PAD_CTL_CCM_CLKO3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET) +#define IOMUXC_PAD_CTL_CCM_CLKO4 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_MDC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_MDC_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD3_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD2_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD1_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD0_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TXC_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RXC_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD0_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD1_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD2_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD3_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_MDC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_MDC_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD3_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD2_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD1_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD0_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TXC_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RXC_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD0_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD1_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD2_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD3_OFFSET) +#define IOMUXC_PAD_CTL_SD1_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_CLK_OFFSET) +#define IOMUXC_PAD_CTL_SD1_CMD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_CMD_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA0_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA1_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA2_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA3_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA4 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA4_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA5 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA5_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA6 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA6_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA7 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA7_OFFSET) +#define IOMUXC_PAD_CTL_SD1_STROBE (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_STROBE_OFFSET) +#define IOMUXC_PAD_CTL_SD2_VSELECT (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET) +#define IOMUXC_PAD_CTL_SD3_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_CLK_OFFSET) +#define IOMUXC_PAD_CTL_SD3_CMD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_CMD_OFFSET) +#define IOMUXC_PAD_CTL_SD3_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA0_OFFSET) +#define IOMUXC_PAD_CTL_SD3_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA1_OFFSET) +#define IOMUXC_PAD_CTL_SD3_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA2_OFFSET) +#define IOMUXC_PAD_CTL_SD3_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA3_OFFSET) +#define IOMUXC_PAD_CTL_SD2_CD_B (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_CD_B_OFFSET) +#define IOMUXC_PAD_CTL_SD2_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_CLK_OFFSET) +#define IOMUXC_PAD_CTL_SD2_CMD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_CMD_OFFSET) +#define IOMUXC_PAD_CTL_SD2_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA0_OFFSET) +#define IOMUXC_PAD_CTL_SD2_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA1_OFFSET) +#define IOMUXC_PAD_CTL_SD2_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA2_OFFSET) +#define IOMUXC_PAD_CTL_SD2_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA3_OFFSET) +#define IOMUXC_PAD_CTL_SD2_RESET_B (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET) +#define IOMUXC_PAD_CTL_I2C1_SCL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C1_SCL_OFFSET) +#define IOMUXC_PAD_CTL_I2C1_SDA (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C1_SDA_OFFSET) +#define IOMUXC_PAD_CTL_I2C2_SCL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C2_SCL_OFFSET) +#define IOMUXC_PAD_CTL_I2C2_SDA (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C2_SDA_OFFSET) +#define IOMUXC_PAD_CTL_UART1_RXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART1_RXD_OFFSET) +#define IOMUXC_PAD_CTL_UART1_TXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART1_TXD_OFFSET) +#define IOMUXC_PAD_CTL_UART2_RXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART2_RXD_OFFSET) +#define IOMUXC_PAD_CTL_UART2_TXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART2_TXD_OFFSET) +#define IOMUXC_PAD_CTL_PDM_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_PDM_CLK_OFFSET) +#define IOMUXC_PAD_CTL_PDM_BIT_STREAM0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET) +#define IOMUXC_PAD_CTL_PDM_BIT_STREAM1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET) +#define IOMUXC_PAD_CTL_SAI1_TXFS (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET) +#define IOMUXC_PAD_CTL_SAI1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_TXC_OFFSET) +#define IOMUXC_PAD_CTL_SAI1_TXD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET) +#define IOMUXC_PAD_CTL_SAI1_RXD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET) +#define IOMUXC_PAD_CTL_WDOG_ANY (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_WDOG_ANY_OFFSET) + +#define CAN1_IPP_IND_CANRX_SELECT_INPUT (IMX9_IOMUXC1_BASE + CAN1_IPP_IND_CANRX_SELECT_INPUT_OFFSET) +#define CAN2_IPP_IND_CANRX_SELECT_INPUT (IMX9_IOMUXC1_BASE + CAN2_IPP_IND_CANRX_SELECT_INPUT_OFFSET) +#define CCMSRCGPCMIX_EXT1_CLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + CCMSRCGPCMIX_EXT1_CLK_SELECT_INPUT_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27_OFFSET) +#define I3C2_PIN_SCL_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + 13C2_PIN_SCL_IN_SELECT_INPUT_OFFSET) +#define I3C2_PIN_SDA_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + 13C2_PIN_SDA_IN_SELECT_INPUT_OFFSET) +#define JTAG_MUX_TCK_SELECT_INPUT (IMX9_IOMUXC1_BASE + JTAG_MUX_TCK_SELECT_INPUT_OFFSET) +#define JTAG_MUX_TDI_SELECT_INPUT (IMX9_IOMUXC1_BASE + JTAG_MUX_TDI_SELECT_INPUT_OFFSET) +#define JTAG_MUX_TMS_SELECT_INPUT (IMX9_IOMUXC1_BASE + JTAG_MUX_TMS_SELECT_INPUT_OFFSET) +#define LP12C3_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + LP12C3_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define LPI12C3_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI12C3_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define LP12C5_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + LP12C5_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define LP12C5_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + LP12C5_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_O (IMX9_IOMUXC1_BASE + LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_O_OFFSET) +#define LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1_OFFSET) +#define LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2_OFFSET) +#define LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INP (IMX9_IOMUXC1_BASE + LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INP_OFFSET) +#define LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET) +#define LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET) +#define LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INP (IMX9_IOMUXC1_BASE + LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INP_OFFSET) +#define LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET) +#define LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET) +#define LPUARTS_IPP_IND_LPUART_CTS_N_SELECT_INP (IMX9_IOMUXC1_BASE + LPUARTS_IPP_IND_LPUART_CTS_N_SELECT_INP_OFFSET) +#define LPUARTS_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPUARTS_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET) +#define LPUARTS_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPUARTS_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET) +#define SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT_OFFSET) +#define SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET) +#define SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT (IMX9_IOMUXC1_BASE + SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET) +#define SPDIF_SPDIF_I_SELECT_INPUT (IMX9_IOMUXC1_BASE + SPDIF_SPDIF_I_SELECT_INPUT_OFFSET) +#define USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT_OFFSET) +#define USDHC3_IPP_CMD_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + USDHC3_IPP_CMD_IN_SELECT_INPUT_OFFSET) +#define USDHC3_IPP_DATO_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + USDHC3_IPP_DATO_IN_SELECT_INPUT_OFFSET) +#define USDHC3_IPP_DAT1_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + USDHC3_IPP_DAT1_IN_SELECT_INPUT_OFFSET) +#define USDHC3_IPP_DAT2_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + USDHC3_IPP_DAT2_IN_SELECT_INPUT_OFFSET) +#define USDHC3_IPP_DAT3_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + USDHC3_IPP_DAT3_IN_SELECT_INPUT_OFFSET) + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_IOMUX_H */ diff --git a/arch/arm64/src/imx9/hardware/imx93/imx93_memorymap.h b/arch/arm64/src/imx9/hardware/imx93/imx93_memorymap.h new file mode 100644 index 0000000000000..0163770e912f4 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx93/imx93_memorymap.h @@ -0,0 +1,175 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx93/imx93_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_MEMORYMAP_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IMX9_GIC_DISTRIBUTOR_BASE (0x48000000UL) +#define IMX9_GIC_REDISTRIBUTOR_BASE (0x48040000UL) +#define IMX9_ANA_OSC_BASE (0x44480000UL) +#define IMX9_AXBS_BASE (0x44510000UL) +#define IMX9_BBNSM_BASE (0x44440000UL) +#define IMX9_BLK_CTRL_BBSMMIX1_BASE (0x44410000UL) +#define IMX9_BLK_CTRL_MLMIX_BASE (0x4A810000UL) +#define IMX9_BLK_CTRL_NIC_WRAPPER1_BASE (0x49000000UL) +#define IMX9_BLK_CTRL_NS_AONMIX1_BASE (0x44210000UL) +#define IMX9_BLK_CTRL_S_AONMIX2_BASE (0x444F0000UL) +#define IMX9_BLK_CTRL_WAKEUPMIX1_BASE (0x42420000UL) +#define IMX9_CAN1_BASE (0x443A0000UL) +#define IMX9_CAN2_BASE (0x425B0000UL) +#define IMX9_CCM_CTRL_BASE (0x44450000UL) +#define IMX9_CM33_MCM_BASE (0x44420000UL) +#define IMX9_DDR_CTRL_BASE (0x4E300000UL) +#define IMX9_BLK_CTRL_DDRMIX_BASE (0x4E010000UL) +#define IMX9_DMA3_BASE (0x44000000UL) +#define IMX9_DMA4_BASE (0x42000000UL) +#define IMX9_PMRO_BASE (0x44484000UL) +#define IMX9_ENET_BASE (0x42890000UL) +#define IMX9_ENET_QOS_BASE (0x428A0000UL) +#define IMX9_FLEXIO1_BASE (0x425C0000UL) +#define IMX9_FLEXIO2_BASE (0x425D0000UL) +#define IMX9_FLEXSPI_BASE (0x425E0000UL) +#define IMX9_FLEXSPI_ARDF_BASE (0x47420000UL) +#define IMX9_FLEXSPI_ATDF_BASE (0x47430000UL) +#define IMX9_GPC_CTRL_CM33_BASE (0x44470000UL) +#define IMX9_GPC_CTRL_CA55_0_BASE (0x44470800UL) +#define IMX9_GPC_CTRL_CA55_1_BASE (0x44471000UL) +#define IMX9_GPC_CTRL_CA55_CLUSTER_BASE (0x44471800UL) +#define IMX9_SAI1_BASE (0x443B0000UL) +#define IMX9_SAI2_BASE (0x42650000UL) +#define IMX9_SAI3_BASE (0x42660000UL) +#define IMX9_I3C1_BASE (0x44330000UL) +#define IMX9_I3C2_BASE (0x42520000UL) +#define IMX9_IOMUXC1_BASE (0x443C0000UL) +#define IMX9_ISI_BASE (0x4AE40000UL) +#define IMX9_LCDIF_BASE (0x4AE30000UL) +#define IMX9_LPI2C1_BASE (0x44340000UL) +#define IMX9_LPI2C2_BASE (0x44350000UL) +#define IMX9_LPI2C3_BASE (0x42530000UL) +#define IMX9_LPI2C4_BASE (0x42540000UL) +#define IMX9_LPI2C5_BASE (0x426B0000UL) +#define IMX9_LPI2C6_BASE (0x426C0000UL) +#define IMX9_LPI2C7_BASE (0x426D0000UL) +#define IMX9_LPI2C8_BASE (0x426E0000UL) +#define IMX9_LPIT1_BASE (0x442F0000UL) +#define IMX9_LPIT2_BASE (0x424C0000UL) +#define IMX9_LPSPI1_BASE (0x44360000UL) +#define IMX9_LPSPI2_BASE (0x44370000UL) +#define IMX9_LPSPI3_BASE (0x42550000UL) +#define IMX9_LPSPI4_BASE (0x42560000UL) +#define IMX9_LPSPI5_BASE (0x426F0000UL) +#define IMX9_LPSPI6_BASE (0x42700000UL) +#define IMX9_LPSPI7_BASE (0x42710000UL) +#define IMX9_LPSPI8_BASE (0x42720000UL) +#define IMX9_LPTMR1_BASE (0x44300000UL) +#define IMX9_LPTMR2_BASE (0x424D0000UL) +#define IMX9_LPUART1_BASE (0x44380000UL) +#define IMX9_LPUART2_BASE (0x44390000UL) +#define IMX9_LPUART3_BASE (0x42570000UL) +#define IMX9_LPUART4_BASE (0x42580000UL) +#define IMX9_LPUART5_BASE (0x42590000UL) +#define IMX9_LPUART6_BASE (0x425A0000UL) +#define IMX9_LPUART7_BASE (0x42690000UL) +#define IMX9_LPUART8_BASE (0x426A0000UL) +#define IMX9_M33_CACHE_MCM_BASE (0x44401000UL) +#define IMX9_BLK_CTRL_MEDIAMIX_BASE (0x4AC10000UL) +#define IMX9_MIPI_CSI_CSR_BASE (0x4AE00000UL) +#define IMX9_MIPI_DSI_BASE (0x4AE10000UL) +#define IMX9_MU1__MUB_BASE (0x44230000UL) +#define IMX9_MU2__MUB_BASE (0x42440000UL) +#define IMX9_S3MUA_BASE (0x47520000UL) +#define IMX9_NPU_BASE (0x4A900000UL) +#define IMX9_OCOTP_BASE (0x47518000UL) +#define IMX9_OCRAM_MECC1_BASE (0x490A0000UL) +#define IMX9_FLEXSPI_OTFAD1_BASE (0x425E0C00UL) +#define IMX9_PDM_BASE (0x44520000UL) +#define IMX9_ARMPLL_BASE (0x44481000UL) +#define IMX9_AUDIOPLL_BASE (0x44481200UL) +#define IMX9_DRAMPLL_BASE (0x44481300UL) +#define IMX9_SYSPLL_BASE (0x44481100UL) +#define IMX9_VIDEOPLL_BASE (0x44481400UL) +#define IMX9_PXP_BASE (0x4AE20000UL) +#define IMX9_GPIO1_BASE (0x47400000UL) +#define IMX9_GPIO2_BASE (0x43810000UL) +#define IMX9_GPIO3_BASE (0x43820000UL) +#define IMX9_GPIO4_BASE (0x43830000UL) +#define IMX9_ROMCP1_BASE (0x44430000UL) +#define IMX9_ROMCP2_BASE (0x42640000UL) +#define IMX9_ADC1_BASE (0x44530000UL) +#define IMX9_SEMA42_1_BASE (0x44260000UL) +#define IMX9_SEMA42_2_BASE (0x42450000UL) +#define IMX9_SFA_BASE (0x44483000UL) +#define IMX9_SPDIF_BASE (0x42680000UL) +#define IMX9_SRC_SENTINEL_SLICE_BASE (0x44460400UL) +#define IMX9_SRC_AON_SLICE_BASE (0x44460800UL) +#define IMX9_SRC_WKUP_SLICE_BASE (0x44460C00UL) +#define IMX9_SRC_DDR_SLICE_BASE (0x44461000UL) +#define IMX9_SRC_DPHY_SLICE_BASE (0x44461400UL) +#define IMX9_SRC_ML_SLICE_BASE (0x44461800UL) +#define IMX9_SRC_NIC_SLICE_BASE (0x44461C00UL) +#define IMX9_SRC_HSIO_SLICE_BASE (0x44462000UL) +#define IMX9_SRC_MEDIA_SLICE_BASE (0x44462400UL) +#define IMX9_SRC_M33P_SLICE_BASE (0x44462800UL) +#define IMX9_SRC_A55C0_SLICE_BASE (0x44462C00UL) +#define IMX9_SRC_A55C1_SLICE_BASE (0x44463000UL) +#define IMX9_SRC_A55P_SLICE_BASE (0x44463400UL) +#define IMX9_M33_PCF1_BASE (0x443E0000UL) +#define IMX9_M33_PSF1_BASE (0x443F0000UL) +#define IMX9_SYS_CTR_COMPARE_BASE (0x442A0000UL) +#define IMX9_SYS_CTR_CONTROL_BASE (0x44290000UL) +#define IMX9_SYS_CTR_READ_BASE (0x442B0000UL) +#define IMX9_TMU_BASE (0x44482000UL) +#define IMX9_TPM1_BASE (0x44310000UL) +#define IMX9_TPM2_BASE (0x44320000UL) +#define IMX9_TPM3_BASE (0x424E0000UL) +#define IMX9_TPM4_BASE (0x424F0000UL) +#define IMX9_TPM5_BASE (0x42500000UL) +#define IMX9_TPM6_BASE (0x42510000UL) +#define IMX9_TRDC1_BASE (0x44270000UL) +#define IMX9_TRDC2_BASE (0x42460000UL) +#define IMX9_TRGMUX_BASE (0x44531000UL) +#define IMX9_TSTMR1_BASE (0x442C0000UL) +#define IMX9_TSTMR2_BASE (0x42480000UL) +#define IMX9_USB_OTG1_BASE (0x4C100000UL) +#define IMX9_USB_OTG2_BASE (0x4C200000UL) +#define IMX9_USBNC_OTG1_BASE (0x4C100200UL) +#define IMX9_USBNC_OTG2_BASE (0x4C200200UL) +#define IMX9_USDHC1_BASE (0x42850000UL) +#define IMX9_USDHC2_BASE (0x42860000UL) +#define IMX9_USDHC3_BASE (0x428B0000UL) +#define IMX9_WDOG1_BASE (0x442D0000UL) +#define IMX9_WDOG2_BASE (0x442E0000UL) +#define IMX9_WDOG3_BASE (0x42490000UL) +#define IMX9_WDOG4_BASE (0x424A0000UL) +#define IMX9_WDOG5_BASE (0x424B0000UL) +#define IMX9_LPCAC_PC_BASE (0x44400000UL) +#define IMX9_LPCAC_PS_BASE (0x44400800UL) + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_MEMORYMAP_H */ diff --git a/arch/arm64/src/imx9/hardware/imx93/imx93_pinmux.h b/arch/arm64/src/imx9/hardware/imx93/imx93_pinmux.h new file mode 100644 index 0000000000000..2a3487d98530a --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx93/imx93_pinmux.h @@ -0,0 +1,634 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx93/imx93_pinmux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_PINMUX_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_PINMUX_H + +#define IOMUXC_PAD_DAP_TDI_JTAG_MUX_TDI IOMUX_PADCFG(0x443c0000, 0x0, 0x443c03d8, 0x00000000, 0x443c01b0) +#define IOMUXC_PAD_DAP_TDI_MQS2_LEFT IOMUX_PADCFG(0x443c0000, 0x1, 0x00000000, 0x00000000, 0x443c01b0) +#define IOMUXC_PAD_DAP_TDI_CAN2_TX IOMUX_PADCFG(0x443c0000, 0x3, 0x00000000, 0x00000000, 0x443c01b0) +#define IOMUXC_PAD_DAP_TDI_FLEXIO2_FLEXIO30 IOMUX_PADCFG(0x443c0000, 0x4, 0x00000000, 0x00000000, 0x443c01b0) +#define IOMUXC_PAD_DAP_TDI_GPIO3_IO28 IOMUX_PADCFG(0x443c0000, 0x5, 0x00000000, 0x00000000, 0x443c01b0) +#define IOMUXC_PAD_DAP_TDI_LPUART5_RX IOMUX_PADCFG(0x443c0000, 0x6, 0x443c0430, 0x00000000, 0x443c01b0) +#define IOMUXC_PAD_DAP_TMS_SWDIO_JTAG_MUX_TMS IOMUX_PADCFG(0x443c0004, 0x0, 0x443c03dc, 0x00000000, 0x443c01b4) +#define IOMUXC_PAD_DAP_TMS_SWDIO_FLEXIO2_FLEXIO31 IOMUX_PADCFG(0x443c0004, 0x4, 0x00000000, 0x00000000, 0x443c01b4) +#define IOMUXC_PAD_DAP_TMS_SWDIO_GPIO3_IO29 IOMUX_PADCFG(0x443c0004, 0x5, 0x00000000, 0x00000000, 0x443c01b4) +#define IOMUXC_PAD_DAP_TMS_SWDIO_LPUART5_RTS_B IOMUX_PADCFG(0x443c0004, 0x6, 0x00000000, 0x00000000, 0x443c01b4) +#define IOMUXC_PAD_DAP_TCLK_SWCLK_JTAG_MUX_TCK IOMUX_PADCFG(0x443c0008, 0x0, 0x443c03d4, 0x00000000, 0x443c01b8) +#define IOMUXC_PAD_DAP_TCLK_SWCLK_FLEXIO1_FLEXIO30 IOMUX_PADCFG(0x443c0008, 0x4, 0x00000000, 0x00000000, 0x443c01b8) +#define IOMUXC_PAD_DAP_TCLK_SWCLK_GPIO3_IO30 IOMUX_PADCFG(0x443c0008, 0x5, 0x00000000, 0x00000000, 0x443c01b8) +#define IOMUXC_PAD_DAP_TCLK_SWCLK_LPUART5_CTS_B IOMUX_PADCFG(0x443c0008, 0x6, 0x443c042c, 0x00000000, 0x443c01b8) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_JTAG_MUX_TDO IOMUX_PADCFG(0x443c000c, 0x0, 0x00000000, 0x00000000, 0x443c01bc) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_MQS2_RIGHT IOMUX_PADCFG(0x443c000c, 0x1, 0x00000000, 0x00000000, 0x443c01bc) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_CAN2_RX IOMUX_PADCFG(0x443c000c, 0x3, 0x443c0364, 0x00000000, 0x443c01bc) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_FLEXIO1_FLEXIO31 IOMUX_PADCFG(0x443c000c, 0x4, 0x00000000, 0x00000000, 0x443c01bc) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_GPIO3_IO31 IOMUX_PADCFG(0x443c000c, 0x5, 0x00000000, 0x00000000, 0x443c01bc) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_LPUART5_TX IOMUX_PADCFG(0x443c000c, 0x6, 0x443c0434, 0x00000000, 0x443c01bc) +#define IOMUXC_PAD_GPIO_IO00_GPIO2_IO00 IOMUX_PADCFG(0x443c0010, 0x0, 0x00000000, 0x00000000, 0x443c01c0) +#define IOMUXC_PAD_GPIO_IO00_LPI2C3_SDA IOMUX_PADCFG(0x443c0010, 0x1, 0x443c03e4, 0x00000000, 0x443c01c0) +#define IOMUXC_PAD_GPIO_IO00_MEDIAMIX_CAM_CLK IOMUX_PADCFG(0x443c0010, 0x2, 0x00000000, 0x00000000, 0x443c01c0) +#define IOMUXC_PAD_GPIO_IO00_MEDIAMIX_DISP_CLK IOMUX_PADCFG(0x443c0010, 0x3, 0x00000000, 0x00000000, 0x443c01c0) +#define IOMUXC_PAD_GPIO_IO00_LPSPI6_PCS0 IOMUX_PADCFG(0x443c0010, 0x4, 0x00000000, 0x00000000, 0x443c01c0) +#define IOMUXC_PAD_GPIO_IO00_LPUART5_TX IOMUX_PADCFG(0x443c0010, 0x5, 0x443c0434, 0x00000001, 0x443c01c0) +#define IOMUXC_PAD_GPIO_IO00_LPI2C5_SDA IOMUX_PADCFG(0x443c0010, 0x6, 0x443c03ec, 0x00000000, 0x443c01c0) +#define IOMUXC_PAD_GPIO_IO00_FLEXIO1_FLEXIO00 IOMUX_PADCFG(0x443c0010, 0x7, 0x443c036c, 0x00000000, 0x443c01c0) +#define IOMUXC_PAD_GPIO_IO01_GPIO2_IO01 IOMUX_PADCFG(0x443c0014, 0x0, 0x00000000, 0x00000000, 0x443c01c4) +#define IOMUXC_PAD_GPIO_IO01_LPI2C3_SCL IOMUX_PADCFG(0x443c0014, 0x1, 0x443c03e0, 0x00000000, 0x443c01c4) +#define IOMUXC_PAD_GPIO_IO01_MEDIAMIX_CAM_DATA00 IOMUX_PADCFG(0x443c0014, 0x2, 0x00000000, 0x00000000, 0x443c01c4) +#define IOMUXC_PAD_GPIO_IO01_MEDIAMIX_DISP_DE IOMUX_PADCFG(0x443c0014, 0x3, 0x00000000, 0x00000000, 0x443c01c4) +#define IOMUXC_PAD_GPIO_IO01_LPSPI6_SIN IOMUX_PADCFG(0x443c0014, 0x4, 0x00000000, 0x00000000, 0x443c01c4) +#define IOMUXC_PAD_GPIO_IO01_LPUART5_RX IOMUX_PADCFG(0x443c0014, 0x5, 0x443c0430, 0x00000001, 0x443c01c4) +#define IOMUXC_PAD_GPIO_IO01_LPI2C5_SCL IOMUX_PADCFG(0x443c0014, 0x6, 0x443c03e8, 0x00000000, 0x443c01c4) +#define IOMUXC_PAD_GPIO_IO01_FLEXIO1_FLEXIO01 IOMUX_PADCFG(0x443c0014, 0x7, 0x443c0370, 0x00000000, 0x443c01c4) +#define IOMUXC_PAD_GPIO_IO02_GPIO2_IO02 IOMUX_PADCFG(0x443c0018, 0x0, 0x00000000, 0x00000000, 0x443c01c8) +#define IOMUXC_PAD_GPIO_IO02_LPI2C4_SDA IOMUX_PADCFG(0x443c0018, 0x1, 0x00000000, 0x00000000, 0x443c01c8) +#define IOMUXC_PAD_GPIO_IO02_MEDIAMIX_CAM_VSYNC IOMUX_PADCFG(0x443c0018, 0x2, 0x00000000, 0x00000000, 0x443c01c8) +#define IOMUXC_PAD_GPIO_IO02_MEDIAMIX_DISP_VSYNC IOMUX_PADCFG(0x443c0018, 0x3, 0x00000000, 0x00000000, 0x443c01c8) +#define IOMUXC_PAD_GPIO_IO02_LPSPI6_SOUT IOMUX_PADCFG(0x443c0018, 0x4, 0x00000000, 0x00000000, 0x443c01c8) +#define IOMUXC_PAD_GPIO_IO02_LPUART5_CTS_B IOMUX_PADCFG(0x443c0018, 0x5, 0x443c042c, 0x00000001, 0x443c01c8) +#define IOMUXC_PAD_GPIO_IO02_LPI2C6_SDA IOMUX_PADCFG(0x443c0018, 0x6, 0x443c03f4, 0x00000000, 0x443c01c8) +#define IOMUXC_PAD_GPIO_IO02_FLEXIO1_FLEXIO02 IOMUX_PADCFG(0x443c0018, 0x7, 0x443c0374, 0x00000000, 0x443c01c8) +#define IOMUXC_PAD_GPIO_IO03_GPIO2_IO03 IOMUX_PADCFG(0x443c001c, 0x0, 0x00000000, 0x00000000, 0x443c01cc) +#define IOMUXC_PAD_GPIO_IO03_LPI2C4_SCL IOMUX_PADCFG(0x443c001c, 0x1, 0x00000000, 0x00000000, 0x443c01cc) +#define IOMUXC_PAD_GPIO_IO03_MEDIAMIX_CAM_HSYNC IOMUX_PADCFG(0x443c001c, 0x2, 0x00000000, 0x00000000, 0x443c01cc) +#define IOMUXC_PAD_GPIO_IO03_MEDIAMIX_DISP_HSYNC IOMUX_PADCFG(0x443c001c, 0x3, 0x00000000, 0x00000000, 0x443c01cc) +#define IOMUXC_PAD_GPIO_IO03_LPSPI6_SCK IOMUX_PADCFG(0x443c001c, 0x4, 0x00000000, 0x00000000, 0x443c01cc) +#define IOMUXC_PAD_GPIO_IO03_LPUART5_RTS_B IOMUX_PADCFG(0x443c001c, 0x5, 0x00000000, 0x00000000, 0x443c01cc) +#define IOMUXC_PAD_GPIO_IO03_LPI2C6_SCL IOMUX_PADCFG(0x443c001c, 0x6, 0x443c03f0, 0x00000000, 0x443c01cc) +#define IOMUXC_PAD_GPIO_IO03_FLEXIO1_FLEXIO03 IOMUX_PADCFG(0x443c001c, 0x7, 0x443c0378, 0x00000000, 0x443c01cc) +#define IOMUXC_PAD_GPIO_IO04_GPIO2_IO04 IOMUX_PADCFG(0x443c0020, 0x0, 0x00000000, 0x00000000, 0x443c01d0) +#define IOMUXC_PAD_GPIO_IO04_TPM3_CH0 IOMUX_PADCFG(0x443c0020, 0x1, 0x00000000, 0x00000000, 0x443c01d0) +#define IOMUXC_PAD_GPIO_IO04_PDM_CLK IOMUX_PADCFG(0x443c0020, 0x2, 0x00000000, 0x00000000, 0x443c01d0) +#define IOMUXC_PAD_GPIO_IO04_MEDIAMIX_DISP_DATA00 IOMUX_PADCFG(0x443c0020, 0x3, 0x00000000, 0x00000000, 0x443c01d0) +#define IOMUXC_PAD_GPIO_IO04_LPSPI7_PCS0 IOMUX_PADCFG(0x443c0020, 0x4, 0x00000000, 0x00000000, 0x443c01d0) +#define IOMUXC_PAD_GPIO_IO04_LPUART6_TX IOMUX_PADCFG(0x443c0020, 0x5, 0x00000000, 0x00000000, 0x443c01d0) +#define IOMUXC_PAD_GPIO_IO04_LPI2C6_SDA IOMUX_PADCFG(0x443c0020, 0x6, 0x443c03f4, 0x00000001, 0x443c01d0) +#define IOMUXC_PAD_GPIO_IO04_FLEXIO1_FLEXIO04 IOMUX_PADCFG(0x443c0020, 0x7, 0x443c037c, 0x00000000, 0x443c01d0) +#define IOMUXC_PAD_GPIO_IO05_GPIO2_IO05 IOMUX_PADCFG(0x443c0024, 0x0, 0x00000000, 0x00000000, 0x443c01d4) +#define IOMUXC_PAD_GPIO_IO05_TPM4_CH0 IOMUX_PADCFG(0x443c0024, 0x1, 0x00000000, 0x00000000, 0x443c01d4) +#define IOMUXC_PAD_GPIO_IO05_PDM_BIT_STREAM00 IOMUX_PADCFG(0x443c0024, 0x2, 0x443c0438, 0x00000000, 0x443c01d4) +#define IOMUXC_PAD_GPIO_IO05_MEDIAMIX_DISP_DATA01 IOMUX_PADCFG(0x443c0024, 0x3, 0x00000000, 0x00000000, 0x443c01d4) +#define IOMUXC_PAD_GPIO_IO05_LPSPI7_SIN IOMUX_PADCFG(0x443c0024, 0x4, 0x00000000, 0x00000000, 0x443c01d4) +#define IOMUXC_PAD_GPIO_IO05_LPUART6_RX IOMUX_PADCFG(0x443c0024, 0x5, 0x00000000, 0x00000000, 0x443c01d4) +#define IOMUXC_PAD_GPIO_IO05_LPI2C6_SCL IOMUX_PADCFG(0x443c0024, 0x6, 0x443c03f0, 0x00000001, 0x443c01d4) +#define IOMUXC_PAD_GPIO_IO05_FLEXIO1_FLEXIO05 IOMUX_PADCFG(0x443c0024, 0x7, 0x443c0380, 0x00000000, 0x443c01d4) +#define IOMUXC_PAD_GPIO_IO06_GPIO2_IO06 IOMUX_PADCFG(0x443c0028, 0x0, 0x00000000, 0x00000000, 0x443c01d8) +#define IOMUXC_PAD_GPIO_IO06_TPM5_CH0 IOMUX_PADCFG(0x443c0028, 0x1, 0x00000000, 0x00000000, 0x443c01d8) +#define IOMUXC_PAD_GPIO_IO06_PDM_BIT_STREAM01 IOMUX_PADCFG(0x443c0028, 0x2, 0x443c043c, 0x00000000, 0x443c01d8) +#define IOMUXC_PAD_GPIO_IO06_MEDIAMIX_DISP_DATA02 IOMUX_PADCFG(0x443c0028, 0x3, 0x00000000, 0x00000000, 0x443c01d8) +#define IOMUXC_PAD_GPIO_IO06_LPSPI7_SOUT IOMUX_PADCFG(0x443c0028, 0x4, 0x00000000, 0x00000000, 0x443c01d8) +#define IOMUXC_PAD_GPIO_IO06_LPUART6_CTS_B IOMUX_PADCFG(0x443c0028, 0x5, 0x00000000, 0x00000000, 0x443c01d8) +#define IOMUXC_PAD_GPIO_IO06_LPI2C7_SDA IOMUX_PADCFG(0x443c0028, 0x6, 0x443c03fc, 0x00000000, 0x443c01d8) +#define IOMUXC_PAD_GPIO_IO06_FLEXIO1_FLEXIO06 IOMUX_PADCFG(0x443c0028, 0x7, 0x443c0384, 0x00000000, 0x443c01d8) +#define IOMUXC_PAD_GPIO_IO07_GPIO2_IO07 IOMUX_PADCFG(0x443c002c, 0x0, 0x00000000, 0x00000000, 0x443c01dc) +#define IOMUXC_PAD_GPIO_IO07_LPSPI3_PCS1 IOMUX_PADCFG(0x443c002c, 0x1, 0x00000000, 0x00000000, 0x443c01dc) +#define IOMUXC_PAD_GPIO_IO07_MEDIAMIX_CAM_DATA01 IOMUX_PADCFG(0x443c002c, 0x2, 0x00000000, 0x00000000, 0x443c01dc) +#define IOMUXC_PAD_GPIO_IO07_MEDIAMIX_DISP_DATA03 IOMUX_PADCFG(0x443c002c, 0x3, 0x00000000, 0x00000000, 0x443c01dc) +#define IOMUXC_PAD_GPIO_IO07_LPSPI7_SCK IOMUX_PADCFG(0x443c002c, 0x4, 0x00000000, 0x00000000, 0x443c01dc) +#define IOMUXC_PAD_GPIO_IO07_LPUART6_RTS_B IOMUX_PADCFG(0x443c002c, 0x5, 0x00000000, 0x00000000, 0x443c01dc) +#define IOMUXC_PAD_GPIO_IO07_LPI2C7_SCL IOMUX_PADCFG(0x443c002c, 0x6, 0x443c03f8, 0x00000000, 0x443c01dc) +#define IOMUXC_PAD_GPIO_IO07_FLEXIO1_FLEXIO07 IOMUX_PADCFG(0x443c002c, 0x7, 0x443c0388, 0x00000000, 0x443c01dc) +#define IOMUXC_PAD_GPIO_IO08_GPIO2_IO08 IOMUX_PADCFG(0x443c0030, 0x0, 0x00000000, 0x00000000, 0x443c01e0) +#define IOMUXC_PAD_GPIO_IO08_LPSPI3_PCS0 IOMUX_PADCFG(0x443c0030, 0x1, 0x00000000, 0x00000000, 0x443c01e0) +#define IOMUXC_PAD_GPIO_IO08_MEDIAMIX_CAM_DATA02 IOMUX_PADCFG(0x443c0030, 0x2, 0x00000000, 0x00000000, 0x443c01e0) +#define IOMUXC_PAD_GPIO_IO08_MEDIAMIX_DISP_DATA04 IOMUX_PADCFG(0x443c0030, 0x3, 0x00000000, 0x00000000, 0x443c01e0) +#define IOMUXC_PAD_GPIO_IO08_TPM6_CH0 IOMUX_PADCFG(0x443c0030, 0x4, 0x00000000, 0x00000000, 0x443c01e0) +#define IOMUXC_PAD_GPIO_IO08_LPUART7_TX IOMUX_PADCFG(0x443c0030, 0x5, 0x00000000, 0x00000000, 0x443c01e0) +#define IOMUXC_PAD_GPIO_IO08_LPI2C7_SDA IOMUX_PADCFG(0x443c0030, 0x6, 0x443c03fc, 0x00000001, 0x443c01e0) +#define IOMUXC_PAD_GPIO_IO08_FLEXIO1_FLEXIO08 IOMUX_PADCFG(0x443c0030, 0x7, 0x443c038c, 0x00000000, 0x443c01e0) +#define IOMUXC_PAD_GPIO_IO09_GPIO2_IO09 IOMUX_PADCFG(0x443c0034, 0x0, 0x00000000, 0x00000000, 0x443c01e4) +#define IOMUXC_PAD_GPIO_IO09_LPSPI3_SIN IOMUX_PADCFG(0x443c0034, 0x1, 0x00000000, 0x00000000, 0x443c01e4) +#define IOMUXC_PAD_GPIO_IO09_MEDIAMIX_CAM_DATA03 IOMUX_PADCFG(0x443c0034, 0x2, 0x00000000, 0x00000000, 0x443c01e4) +#define IOMUXC_PAD_GPIO_IO09_MEDIAMIX_DISP_DATA05 IOMUX_PADCFG(0x443c0034, 0x3, 0x00000000, 0x00000000, 0x443c01e4) +#define IOMUXC_PAD_GPIO_IO09_TPM3_EXTCLK IOMUX_PADCFG(0x443c0034, 0x4, 0x00000000, 0x00000000, 0x443c01e4) +#define IOMUXC_PAD_GPIO_IO09_LPUART7_RX IOMUX_PADCFG(0x443c0034, 0x5, 0x00000000, 0x00000000, 0x443c01e4) +#define IOMUXC_PAD_GPIO_IO09_LPI2C7_SCL IOMUX_PADCFG(0x443c0034, 0x6, 0x443c03f8, 0x00000001, 0x443c01e4) +#define IOMUXC_PAD_GPIO_IO09_FLEXIO1_FLEXIO09 IOMUX_PADCFG(0x443c0034, 0x7, 0x443c0390, 0x00000000, 0x443c01e4) +#define IOMUXC_PAD_GPIO_IO10_GPIO2_IO10 IOMUX_PADCFG(0x443c0038, 0x0, 0x00000000, 0x00000000, 0x443c01e8) +#define IOMUXC_PAD_GPIO_IO10_LPSPI3_SOUT IOMUX_PADCFG(0x443c0038, 0x1, 0x00000000, 0x00000000, 0x443c01e8) +#define IOMUXC_PAD_GPIO_IO10_MEDIAMIX_CAM_DATA04 IOMUX_PADCFG(0x443c0038, 0x2, 0x00000000, 0x00000000, 0x443c01e8) +#define IOMUXC_PAD_GPIO_IO10_MEDIAMIX_DISP_DATA06 IOMUX_PADCFG(0x443c0038, 0x3, 0x00000000, 0x00000000, 0x443c01e8) +#define IOMUXC_PAD_GPIO_IO10_TPM4_EXTCLK IOMUX_PADCFG(0x443c0038, 0x4, 0x00000000, 0x00000000, 0x443c01e8) +#define IOMUXC_PAD_GPIO_IO10_LPUART7_CTS_B IOMUX_PADCFG(0x443c0038, 0x5, 0x00000000, 0x00000000, 0x443c01e8) +#define IOMUXC_PAD_GPIO_IO10_LPI2C8_SDA IOMUX_PADCFG(0x443c0038, 0x6, 0x443c0404, 0x00000000, 0x443c01e8) +#define IOMUXC_PAD_GPIO_IO10_FLEXIO1_FLEXIO10 IOMUX_PADCFG(0x443c0038, 0x7, 0x443c0394, 0x00000000, 0x443c01e8) +#define IOMUXC_PAD_GPIO_IO11_GPIO2_IO11 IOMUX_PADCFG(0x443c003c, 0x0, 0x00000000, 0x00000000, 0x443c01ec) +#define IOMUXC_PAD_GPIO_IO11_LPSPI3_SCK IOMUX_PADCFG(0x443c003c, 0x1, 0x00000000, 0x00000000, 0x443c01ec) +#define IOMUXC_PAD_GPIO_IO11_MEDIAMIX_CAM_DATA05 IOMUX_PADCFG(0x443c003c, 0x2, 0x00000000, 0x00000000, 0x443c01ec) +#define IOMUXC_PAD_GPIO_IO11_MEDIAMIX_DISP_DATA07 IOMUX_PADCFG(0x443c003c, 0x3, 0x00000000, 0x00000000, 0x443c01ec) +#define IOMUXC_PAD_GPIO_IO11_TPM5_EXTCLK IOMUX_PADCFG(0x443c003c, 0x4, 0x00000000, 0x00000000, 0x443c01ec) +#define IOMUXC_PAD_GPIO_IO11_LPUART7_RTS_B IOMUX_PADCFG(0x443c003c, 0x5, 0x00000000, 0x00000000, 0x443c01ec) +#define IOMUXC_PAD_GPIO_IO11_LPI2C8_SCL IOMUX_PADCFG(0x443c003c, 0x6, 0x443c0400, 0x00000000, 0x443c01ec) +#define IOMUXC_PAD_GPIO_IO11_FLEXIO1_FLEXIO11 IOMUX_PADCFG(0x443c003c, 0x7, 0x443c0398, 0x00000000, 0x443c01ec) +#define IOMUXC_PAD_GPIO_IO12_GPIO2_IO12 IOMUX_PADCFG(0x443c0040, 0x0, 0x00000000, 0x00000000, 0x443c01f0) +#define IOMUXC_PAD_GPIO_IO12_TPM3_CH2 IOMUX_PADCFG(0x443c0040, 0x1, 0x00000000, 0x00000000, 0x443c01f0) +#define IOMUXC_PAD_GPIO_IO12_PDM_BIT_STREAM02 IOMUX_PADCFG(0x443c0040, 0x2, 0x443c0440, 0x00000000, 0x443c01f0) +#define IOMUXC_PAD_GPIO_IO12_MEDIAMIX_DISP_DATA08 IOMUX_PADCFG(0x443c0040, 0x3, 0x00000000, 0x00000000, 0x443c01f0) +#define IOMUXC_PAD_GPIO_IO12_LPSPI8_PCS0 IOMUX_PADCFG(0x443c0040, 0x4, 0x00000000, 0x00000000, 0x443c01f0) +#define IOMUXC_PAD_GPIO_IO12_LPUART8_TX IOMUX_PADCFG(0x443c0040, 0x5, 0x00000000, 0x00000000, 0x443c01f0) +#define IOMUXC_PAD_GPIO_IO12_LPI2C8_SDA IOMUX_PADCFG(0x443c0040, 0x6, 0x443c0404, 0x00000001, 0x443c01f0) +#define IOMUXC_PAD_GPIO_IO12_SAI3_RX_SYNC IOMUX_PADCFG(0x443c0040, 0x7, 0x443c0450, 0x00000000, 0x443c01f0) +#define IOMUXC_PAD_GPIO_IO13_GPIO2_IO13 IOMUX_PADCFG(0x443c0044, 0x0, 0x00000000, 0x00000000, 0x443c01f4) +#define IOMUXC_PAD_GPIO_IO13_TPM4_CH2 IOMUX_PADCFG(0x443c0044, 0x1, 0x00000000, 0x00000000, 0x443c01f4) +#define IOMUXC_PAD_GPIO_IO13_PDM_BIT_STREAM03 IOMUX_PADCFG(0x443c0044, 0x2, 0x443c0444, 0x00000000, 0x443c01f4) +#define IOMUXC_PAD_GPIO_IO13_MEDIAMIX_DISP_DATA09 IOMUX_PADCFG(0x443c0044, 0x3, 0x00000000, 0x00000000, 0x443c01f4) +#define IOMUXC_PAD_GPIO_IO13_LPSPI8_SIN IOMUX_PADCFG(0x443c0044, 0x4, 0x00000000, 0x00000000, 0x443c01f4) +#define IOMUXC_PAD_GPIO_IO13_LPUART8_RX IOMUX_PADCFG(0x443c0044, 0x5, 0x00000000, 0x00000000, 0x443c01f4) +#define IOMUXC_PAD_GPIO_IO13_LPI2C8_SCL IOMUX_PADCFG(0x443c0044, 0x6, 0x443c0400, 0x00000001, 0x443c01f4) +#define IOMUXC_PAD_GPIO_IO13_FLEXIO1_FLEXIO13 IOMUX_PADCFG(0x443c0044, 0x7, 0x443c039c, 0x00000000, 0x443c01f4) +#define IOMUXC_PAD_GPIO_IO14_GPIO2_IO14 IOMUX_PADCFG(0x443c0048, 0x0, 0x00000000, 0x00000000, 0x443c01f8) +#define IOMUXC_PAD_GPIO_IO14_LPUART3_TX IOMUX_PADCFG(0x443c0048, 0x1, 0x443c041c, 0x00000000, 0x443c01f8) +#define IOMUXC_PAD_GPIO_IO14_MEDIAMIX_CAM_DATA06 IOMUX_PADCFG(0x443c0048, 0x2, 0x00000000, 0x00000000, 0x443c01f8) +#define IOMUXC_PAD_GPIO_IO14_MEDIAMIX_DISP_DATA10 IOMUX_PADCFG(0x443c0048, 0x3, 0x00000000, 0x00000000, 0x443c01f8) +#define IOMUXC_PAD_GPIO_IO14_LPSPI8_SOUT IOMUX_PADCFG(0x443c0048, 0x4, 0x00000000, 0x00000000, 0x443c01f8) +#define IOMUXC_PAD_GPIO_IO14_LPUART8_CTS_B IOMUX_PADCFG(0x443c0048, 0x5, 0x00000000, 0x00000000, 0x443c01f8) +#define IOMUXC_PAD_GPIO_IO14_LPUART4_TX IOMUX_PADCFG(0x443c0048, 0x6, 0x443c0428, 0x00000000, 0x443c01f8) +#define IOMUXC_PAD_GPIO_IO14_FLEXIO1_FLEXIO14 IOMUX_PADCFG(0x443c0048, 0x7, 0x443c03a0, 0x00000000, 0x443c01f8) +#define IOMUXC_PAD_GPIO_IO15_GPIO2_IO15 IOMUX_PADCFG(0x443c004c, 0x0, 0x00000000, 0x00000000, 0x443c01fc) +#define IOMUXC_PAD_GPIO_IO15_LPUART3_RX IOMUX_PADCFG(0x443c004c, 0x1, 0x443c0418, 0x00000000, 0x443c01fc) +#define IOMUXC_PAD_GPIO_IO15_MEDIAMIX_CAM_DATA07 IOMUX_PADCFG(0x443c004c, 0x2, 0x00000000, 0x00000000, 0x443c01fc) +#define IOMUXC_PAD_GPIO_IO15_MEDIAMIX_DISP_DATA11 IOMUX_PADCFG(0x443c004c, 0x3, 0x00000000, 0x00000000, 0x443c01fc) +#define IOMUXC_PAD_GPIO_IO15_LPSPI8_SCK IOMUX_PADCFG(0x443c004c, 0x4, 0x00000000, 0x00000000, 0x443c01fc) +#define IOMUXC_PAD_GPIO_IO15_LPUART8_RTS_B IOMUX_PADCFG(0x443c004c, 0x5, 0x00000000, 0x00000000, 0x443c01fc) +#define IOMUXC_PAD_GPIO_IO15_LPUART4_RX IOMUX_PADCFG(0x443c004c, 0x6, 0x443c0424, 0x00000000, 0x443c01fc) +#define IOMUXC_PAD_GPIO_IO15_FLEXIO1_FLEXIO15 IOMUX_PADCFG(0x443c004c, 0x7, 0x443c03a4, 0x00000000, 0x443c01fc) +#define IOMUXC_PAD_GPIO_IO16_GPIO2_IO16 IOMUX_PADCFG(0x443c0050, 0x0, 0x00000000, 0x00000000, 0x443c0200) +#define IOMUXC_PAD_GPIO_IO16_SAI3_TX_BCLK IOMUX_PADCFG(0x443c0050, 0x1, 0x00000000, 0x00000000, 0x443c0200) +#define IOMUXC_PAD_GPIO_IO16_PDM_BIT_STREAM02 IOMUX_PADCFG(0x443c0050, 0x2, 0x443c0440, 0x00000001, 0x443c0200) +#define IOMUXC_PAD_GPIO_IO16_MEDIAMIX_DISP_DATA12 IOMUX_PADCFG(0x443c0050, 0x3, 0x00000000, 0x00000000, 0x443c0200) +#define IOMUXC_PAD_GPIO_IO16_LPUART3_CTS_B IOMUX_PADCFG(0x443c0050, 0x4, 0x443c0414, 0x00000000, 0x443c0200) +#define IOMUXC_PAD_GPIO_IO16_LPSPI4_PCS2 IOMUX_PADCFG(0x443c0050, 0x5, 0x00000000, 0x00000000, 0x443c0200) +#define IOMUXC_PAD_GPIO_IO16_LPUART4_CTS_B IOMUX_PADCFG(0x443c0050, 0x6, 0x443c0420, 0x00000000, 0x443c0200) +#define IOMUXC_PAD_GPIO_IO16_FLEXIO1_FLEXIO16 IOMUX_PADCFG(0x443c0050, 0x7, 0x443c03a8, 0x00000000, 0x443c0200) +#define IOMUXC_PAD_GPIO_IO17_GPIO2_IO17 IOMUX_PADCFG(0x443c0054, 0x0, 0x00000000, 0x00000000, 0x443c0204) +#define IOMUXC_PAD_GPIO_IO17_SAI3_MCLK IOMUX_PADCFG(0x443c0054, 0x1, 0x00000000, 0x00000000, 0x443c0204) +#define IOMUXC_PAD_GPIO_IO17_MEDIAMIX_CAM_DATA08 IOMUX_PADCFG(0x443c0054, 0x2, 0x00000000, 0x00000000, 0x443c0204) +#define IOMUXC_PAD_GPIO_IO17_MEDIAMIX_DISP_DATA13 IOMUX_PADCFG(0x443c0054, 0x3, 0x00000000, 0x00000000, 0x443c0204) +#define IOMUXC_PAD_GPIO_IO17_LPUART3_RTS_B IOMUX_PADCFG(0x443c0054, 0x4, 0x00000000, 0x00000000, 0x443c0204) +#define IOMUXC_PAD_GPIO_IO17_LPSPI4_PCS1 IOMUX_PADCFG(0x443c0054, 0x5, 0x00000000, 0x00000000, 0x443c0204) +#define IOMUXC_PAD_GPIO_IO17_LPUART4_RTS_B IOMUX_PADCFG(0x443c0054, 0x6, 0x00000000, 0x00000000, 0x443c0204) +#define IOMUXC_PAD_GPIO_IO17_FLEXIO1_FLEXIO17 IOMUX_PADCFG(0x443c0054, 0x7, 0x443c03ac, 0x00000000, 0x443c0204) +#define IOMUXC_PAD_GPIO_IO18_GPIO2_IO18 IOMUX_PADCFG(0x443c0058, 0x0, 0x00000000, 0x00000000, 0x443c0208) +#define IOMUXC_PAD_GPIO_IO18_SAI3_RX_BCLK IOMUX_PADCFG(0x443c0058, 0x1, 0x443c044c, 0x00000000, 0x443c0208) +#define IOMUXC_PAD_GPIO_IO18_MEDIAMIX_CAM_DATA09 IOMUX_PADCFG(0x443c0058, 0x2, 0x00000000, 0x00000000, 0x443c0208) +#define IOMUXC_PAD_GPIO_IO18_MEDIAMIX_DISP_DATA14 IOMUX_PADCFG(0x443c0058, 0x3, 0x00000000, 0x00000000, 0x443c0208) +#define IOMUXC_PAD_GPIO_IO18_LPSPI5_PCS0 IOMUX_PADCFG(0x443c0058, 0x4, 0x00000000, 0x00000000, 0x443c0208) +#define IOMUXC_PAD_GPIO_IO18_LPSPI4_PCS0 IOMUX_PADCFG(0x443c0058, 0x5, 0x00000000, 0x00000000, 0x443c0208) +#define IOMUXC_PAD_GPIO_IO18_TPM5_CH2 IOMUX_PADCFG(0x443c0058, 0x6, 0x00000000, 0x00000000, 0x443c0208) +#define IOMUXC_PAD_GPIO_IO18_FLEXIO1_FLEXIO18 IOMUX_PADCFG(0x443c0058, 0x7, 0x443c03b0, 0x00000000, 0x443c0208) +#define IOMUXC_PAD_GPIO_IO19_GPIO2_IO19 IOMUX_PADCFG(0x443c005c, 0x0, 0x00000000, 0x00000000, 0x443c020c) +#define IOMUXC_PAD_GPIO_IO19_SAI3_RX_SYNC IOMUX_PADCFG(0x443c005c, 0x1, 0x443c0450, 0x00000001, 0x443c020c) +#define IOMUXC_PAD_GPIO_IO19_PDM_BIT_STREAM03 IOMUX_PADCFG(0x443c005c, 0x2, 0x443c0444, 0x00000001, 0x443c020c) +#define IOMUXC_PAD_GPIO_IO19_MEDIAMIX_DISP_DATA15 IOMUX_PADCFG(0x443c005c, 0x3, 0x00000000, 0x00000000, 0x443c020c) +#define IOMUXC_PAD_GPIO_IO19_LPSPI5_SIN IOMUX_PADCFG(0x443c005c, 0x4, 0x00000000, 0x00000000, 0x443c020c) +#define IOMUXC_PAD_GPIO_IO19_LPSPI4_SIN IOMUX_PADCFG(0x443c005c, 0x5, 0x00000000, 0x00000000, 0x443c020c) +#define IOMUXC_PAD_GPIO_IO19_TPM6_CH2 IOMUX_PADCFG(0x443c005c, 0x6, 0x00000000, 0x00000000, 0x443c020c) +#define IOMUXC_PAD_GPIO_IO19_SAI3_TX_DATA00 IOMUX_PADCFG(0x443c005c, 0x7, 0x00000000, 0x00000000, 0x443c020c) +#define IOMUXC_PAD_GPIO_IO20_GPIO2_IO20 IOMUX_PADCFG(0x443c0060, 0x0, 0x00000000, 0x00000000, 0x443c0210) +#define IOMUXC_PAD_GPIO_IO20_SAI3_RX_DATA00 IOMUX_PADCFG(0x443c0060, 0x1, 0x00000000, 0x00000000, 0x443c0210) +#define IOMUXC_PAD_GPIO_IO20_PDM_BIT_STREAM00 IOMUX_PADCFG(0x443c0060, 0x2, 0x443c0438, 0x00000001, 0x443c0210) +#define IOMUXC_PAD_GPIO_IO20_MEDIAMIX_DISP_DATA16 IOMUX_PADCFG(0x443c0060, 0x3, 0x00000000, 0x00000000, 0x443c0210) +#define IOMUXC_PAD_GPIO_IO20_LPSPI5_SOUT IOMUX_PADCFG(0x443c0060, 0x4, 0x00000000, 0x00000000, 0x443c0210) +#define IOMUXC_PAD_GPIO_IO20_LPSPI4_SOUT IOMUX_PADCFG(0x443c0060, 0x5, 0x00000000, 0x00000000, 0x443c0210) +#define IOMUXC_PAD_GPIO_IO20_TPM3_CH1 IOMUX_PADCFG(0x443c0060, 0x6, 0x00000000, 0x00000000, 0x443c0210) +#define IOMUXC_PAD_GPIO_IO20_FLEXIO1_FLEXIO20 IOMUX_PADCFG(0x443c0060, 0x7, 0x443c03b4, 0x00000000, 0x443c0210) +#define IOMUXC_PAD_GPIO_IO21_GPIO2_IO21 IOMUX_PADCFG(0x443c0064, 0x0, 0x00000000, 0x00000000, 0x443c0214) +#define IOMUXC_PAD_GPIO_IO21_SAI3_TX_DATA00 IOMUX_PADCFG(0x443c0064, 0x1, 0x00000000, 0x00000000, 0x443c0214) +#define IOMUXC_PAD_GPIO_IO21_PDM_CLK IOMUX_PADCFG(0x443c0064, 0x2, 0x00000000, 0x00000000, 0x443c0214) +#define IOMUXC_PAD_GPIO_IO21_MEDIAMIX_DISP_DATA17 IOMUX_PADCFG(0x443c0064, 0x3, 0x00000000, 0x00000000, 0x443c0214) +#define IOMUXC_PAD_GPIO_IO21_LPSPI5_SCK IOMUX_PADCFG(0x443c0064, 0x4, 0x00000000, 0x00000000, 0x443c0214) +#define IOMUXC_PAD_GPIO_IO21_LPSPI4_SCK IOMUX_PADCFG(0x443c0064, 0x5, 0x00000000, 0x00000000, 0x443c0214) +#define IOMUXC_PAD_GPIO_IO21_TPM4_CH1 IOMUX_PADCFG(0x443c0064, 0x6, 0x00000000, 0x00000000, 0x443c0214) +#define IOMUXC_PAD_GPIO_IO21_SAI3_RX_BCLK IOMUX_PADCFG(0x443c0064, 0x7, 0x443c044c, 0x00000001, 0x443c0214) +#define IOMUXC_PAD_GPIO_IO22_GPIO2_IO22 IOMUX_PADCFG(0x443c0068, 0x0, 0x00000000, 0x00000000, 0x443c0218) +#define IOMUXC_PAD_GPIO_IO22_USDHC3_CLK IOMUX_PADCFG(0x443c0068, 0x1, 0x443c0458, 0x00000000, 0x443c0218) +#define IOMUXC_PAD_GPIO_IO22_SPDIF_IN IOMUX_PADCFG(0x443c0068, 0x2, 0x443c0454, 0x00000000, 0x443c0218) +#define IOMUXC_PAD_GPIO_IO22_MEDIAMIX_DISP_DATA18 IOMUX_PADCFG(0x443c0068, 0x3, 0x00000000, 0x00000000, 0x443c0218) +#define IOMUXC_PAD_GPIO_IO22_TPM5_CH1 IOMUX_PADCFG(0x443c0068, 0x4, 0x00000000, 0x00000000, 0x443c0218) +#define IOMUXC_PAD_GPIO_IO22_TPM6_EXTCLK IOMUX_PADCFG(0x443c0068, 0x5, 0x00000000, 0x00000000, 0x443c0218) +#define IOMUXC_PAD_GPIO_IO22_LPI2C5_SDA IOMUX_PADCFG(0x443c0068, 0x6, 0x443c03ec, 0x00000001, 0x443c0218) +#define IOMUXC_PAD_GPIO_IO22_FLEXIO1_FLEXIO22 IOMUX_PADCFG(0x443c0068, 0x7, 0x443c03b8, 0x00000000, 0x443c0218) +#define IOMUXC_PAD_GPIO_IO23_GPIO2_IO23 IOMUX_PADCFG(0x443c006c, 0x0, 0x00000000, 0x00000000, 0x443c021c) +#define IOMUXC_PAD_GPIO_IO23_USDHC3_CMD IOMUX_PADCFG(0x443c006c, 0x1, 0x443c045c, 0x00000000, 0x443c021c) +#define IOMUXC_PAD_GPIO_IO23_SPDIF_OUT IOMUX_PADCFG(0x443c006c, 0x2, 0x00000000, 0x00000000, 0x443c021c) +#define IOMUXC_PAD_GPIO_IO23_MEDIAMIX_DISP_DATA19 IOMUX_PADCFG(0x443c006c, 0x3, 0x00000000, 0x00000000, 0x443c021c) +#define IOMUXC_PAD_GPIO_IO23_TPM6_CH1 IOMUX_PADCFG(0x443c006c, 0x4, 0x00000000, 0x00000000, 0x443c021c) +#define IOMUXC_PAD_GPIO_IO23_LPI2C5_SCL IOMUX_PADCFG(0x443c006c, 0x6, 0x443c03e8, 0x00000001, 0x443c021c) +#define IOMUXC_PAD_GPIO_IO23_FLEXIO1_FLEXIO23 IOMUX_PADCFG(0x443c006c, 0x7, 0x443c03bc, 0x00000000, 0x443c021c) +#define IOMUXC_PAD_GPIO_IO24_GPIO2_IO24 IOMUX_PADCFG(0x443c0070, 0x0, 0x00000000, 0x00000000, 0x443c0220) +#define IOMUXC_PAD_GPIO_IO24_USDHC3_DATA0 IOMUX_PADCFG(0x443c0070, 0x1, 0x443c0460, 0x00000000, 0x443c0220) +#define IOMUXC_PAD_GPIO_IO24_MEDIAMIX_DISP_DATA20 IOMUX_PADCFG(0x443c0070, 0x3, 0x00000000, 0x00000000, 0x443c0220) +#define IOMUXC_PAD_GPIO_IO24_TPM3_CH3 IOMUX_PADCFG(0x443c0070, 0x4, 0x00000000, 0x00000000, 0x443c0220) +#define IOMUXC_PAD_GPIO_IO24_JTAG_MUX_TDO IOMUX_PADCFG(0x443c0070, 0x5, 0x00000000, 0x00000000, 0x443c0220) +#define IOMUXC_PAD_GPIO_IO24_LPSPI6_PCS1 IOMUX_PADCFG(0x443c0070, 0x6, 0x00000000, 0x00000000, 0x443c0220) +#define IOMUXC_PAD_GPIO_IO24_FLEXIO1_FLEXIO24 IOMUX_PADCFG(0x443c0070, 0x7, 0x443c03c0, 0x00000000, 0x443c0220) +#define IOMUXC_PAD_GPIO_IO25_GPIO2_IO25 IOMUX_PADCFG(0x443c0074, 0x0, 0x00000000, 0x00000000, 0x443c0224) +#define IOMUXC_PAD_GPIO_IO25_USDHC3_DATA1 IOMUX_PADCFG(0x443c0074, 0x1, 0x443c0464, 0x00000000, 0x443c0224) +#define IOMUXC_PAD_GPIO_IO25_CAN2_TX IOMUX_PADCFG(0x443c0074, 0x2, 0x00000000, 0x00000000, 0x443c0224) +#define IOMUXC_PAD_GPIO_IO25_MEDIAMIX_DISP_DATA21 IOMUX_PADCFG(0x443c0074, 0x3, 0x00000000, 0x00000000, 0x443c0224) +#define IOMUXC_PAD_GPIO_IO25_TPM4_CH3 IOMUX_PADCFG(0x443c0074, 0x4, 0x00000000, 0x00000000, 0x443c0224) +#define IOMUXC_PAD_GPIO_IO25_JTAG_MUX_TCK IOMUX_PADCFG(0x443c0074, 0x5, 0x443c03d4, 0x00000001, 0x443c0224) +#define IOMUXC_PAD_GPIO_IO25_LPSPI7_PCS1 IOMUX_PADCFG(0x443c0074, 0x6, 0x00000000, 0x00000000, 0x443c0224) +#define IOMUXC_PAD_GPIO_IO25_FLEXIO1_FLEXIO25 IOMUX_PADCFG(0x443c0074, 0x7, 0x443c03c4, 0x00000000, 0x443c0224) +#define IOMUXC_PAD_GPIO_IO26_GPIO2_IO26 IOMUX_PADCFG(0x443c0078, 0x0, 0x00000000, 0x00000000, 0x443c0228) +#define IOMUXC_PAD_GPIO_IO26_USDHC3_DATA2 IOMUX_PADCFG(0x443c0078, 0x1, 0x443c0468, 0x00000000, 0x443c0228) +#define IOMUXC_PAD_GPIO_IO26_PDM_BIT_STREAM01 IOMUX_PADCFG(0x443c0078, 0x2, 0x443c043c, 0x00000001, 0x443c0228) +#define IOMUXC_PAD_GPIO_IO26_MEDIAMIX_DISP_DATA22 IOMUX_PADCFG(0x443c0078, 0x3, 0x00000000, 0x00000000, 0x443c0228) +#define IOMUXC_PAD_GPIO_IO26_TPM5_CH3 IOMUX_PADCFG(0x443c0078, 0x4, 0x00000000, 0x00000000, 0x443c0228) +#define IOMUXC_PAD_GPIO_IO26_JTAG_MUX_TDI IOMUX_PADCFG(0x443c0078, 0x5, 0x443c03d8, 0x00000001, 0x443c0228) +#define IOMUXC_PAD_GPIO_IO26_LPSPI8_PCS1 IOMUX_PADCFG(0x443c0078, 0x6, 0x00000000, 0x00000000, 0x443c0228) +#define IOMUXC_PAD_GPIO_IO26_SAI3_TX_SYNC IOMUX_PADCFG(0x443c0078, 0x7, 0x00000000, 0x00000000, 0x443c0228) +#define IOMUXC_PAD_GPIO_IO27_GPIO2_IO27 IOMUX_PADCFG(0x443c007c, 0x0, 0x00000000, 0x00000000, 0x443c022c) +#define IOMUXC_PAD_GPIO_IO27_USDHC3_DATA3 IOMUX_PADCFG(0x443c007c, 0x1, 0x443c046c, 0x00000000, 0x443c022c) +#define IOMUXC_PAD_GPIO_IO27_CAN2_RX IOMUX_PADCFG(0x443c007c, 0x2, 0x443c0364, 0x00000001, 0x443c022c) +#define IOMUXC_PAD_GPIO_IO27_MEDIAMIX_DISP_DATA23 IOMUX_PADCFG(0x443c007c, 0x3, 0x00000000, 0x00000000, 0x443c022c) +#define IOMUXC_PAD_GPIO_IO27_TPM6_CH3 IOMUX_PADCFG(0x443c007c, 0x4, 0x00000000, 0x00000000, 0x443c022c) +#define IOMUXC_PAD_GPIO_IO27_JTAG_MUX_TMS IOMUX_PADCFG(0x443c007c, 0x5, 0x443c03dc, 0x00000001, 0x443c022c) +#define IOMUXC_PAD_GPIO_IO27_LPSPI5_PCS1 IOMUX_PADCFG(0x443c007c, 0x6, 0x00000000, 0x00000000, 0x443c022c) +#define IOMUXC_PAD_GPIO_IO27_FLEXIO1_FLEXIO27 IOMUX_PADCFG(0x443c007c, 0x7, 0x443c03c8, 0x00000000, 0x443c022c) +#define IOMUXC_PAD_GPIO_IO28_GPIO2_IO28 IOMUX_PADCFG(0x443c0080, 0x0, 0x00000000, 0x00000000, 0x443c0230) +#define IOMUXC_PAD_GPIO_IO28_LPI2C3_SDA IOMUX_PADCFG(0x443c0080, 0x1, 0x443c03e4, 0x00000001, 0x443c0230) +#define IOMUXC_PAD_GPIO_IO28_FLEXIO1_FLEXIO28 IOMUX_PADCFG(0x443c0080, 0x7, 0x00000000, 0x00000000, 0x443c0230) +#define IOMUXC_PAD_GPIO_IO29_GPIO2_IO29 IOMUX_PADCFG(0x443c0084, 0x0, 0x00000000, 0x00000000, 0x443c0234) +#define IOMUXC_PAD_GPIO_IO29_LPI2C3_SCL IOMUX_PADCFG(0x443c0084, 0x1, 0x443c03e0, 0x00000001, 0x443c0234) +#define IOMUXC_PAD_GPIO_IO29_FLEXIO1_FLEXIO29 IOMUX_PADCFG(0x443c0084, 0x7, 0x00000000, 0x00000000, 0x443c0234) +#define IOMUXC_PAD_CCM_CLKO1_CCMSRCGPCMIX_CLKO1 IOMUX_PADCFG(0x443c0088, 0x0, 0x00000000, 0x00000000, 0x443c0238) +#define IOMUXC_PAD_CCM_CLKO1_FLEXIO1_FLEXIO26 IOMUX_PADCFG(0x443c0088, 0x4, 0x00000000, 0x00000000, 0x443c0238) +#define IOMUXC_PAD_CCM_CLKO1_GPIO3_IO26 IOMUX_PADCFG(0x443c0088, 0x5, 0x00000000, 0x00000000, 0x443c0238) +#define IOMUXC_PAD_CCM_CLKO2_GPIO3_IO27 IOMUX_PADCFG(0x443c008c, 0x5, 0x00000000, 0x00000000, 0x443c023c) +#define IOMUXC_PAD_CCM_CLKO2_CCMSRCGPCMIX_CLKO2 IOMUX_PADCFG(0x443c008c, 0x0, 0x00000000, 0x00000000, 0x443c023c) +#define IOMUXC_PAD_CCM_CLKO2_FLEXIO1_FLEXIO27 IOMUX_PADCFG(0x443c008c, 0x4, 0x443c03c8, 0x00000001, 0x443c023c) +#define IOMUXC_PAD_CCM_CLKO3_CCMSRCGPCMIX_CLKO3 IOMUX_PADCFG(0x443c0090, 0x0, 0x00000000, 0x00000000, 0x443c0240) +#define IOMUXC_PAD_CCM_CLKO3_FLEXIO2_FLEXIO28 IOMUX_PADCFG(0x443c0090, 0x4, 0x00000000, 0x00000000, 0x443c0240) +#define IOMUXC_PAD_CCM_CLKO3_GPIO4_IO28 IOMUX_PADCFG(0x443c0090, 0x5, 0x00000000, 0x00000000, 0x443c0240) +#define IOMUXC_PAD_CCM_CLKO4_CCMSRCGPCMIX_CLKO4 IOMUX_PADCFG(0x443c0094, 0x0, 0x00000000, 0x00000000, 0x443c0244) +#define IOMUXC_PAD_CCM_CLKO4_FLEXIO2_FLEXIO29 IOMUX_PADCFG(0x443c0094, 0x4, 0x00000000, 0x00000000, 0x443c0244) +#define IOMUXC_PAD_CCM_CLKO4_GPIO4_IO29 IOMUX_PADCFG(0x443c0094, 0x5, 0x00000000, 0x00000000, 0x443c0244) +#define IOMUXC_PAD_ENET1_MDC_ENET_QOS_MDC IOMUX_PADCFG(0x443c0098, 0x0, 0x00000000, 0x00000000, 0x443c0248) +#define IOMUXC_PAD_ENET1_MDC_LPUART3_DCB_B IOMUX_PADCFG(0x443c0098, 0x1, 0x00000000, 0x00000000, 0x443c0248) +#define IOMUXC_PAD_ENET1_MDC_I3C2_SCL IOMUX_PADCFG(0x443c0098, 0x2, 0x443c03cc, 0x00000000, 0x443c0248) +#define IOMUXC_PAD_ENET1_MDC_HSIOMIX_OTG_ID1 IOMUX_PADCFG(0x443c0098, 0x3, 0x00000000, 0x00000000, 0x443c0248) +#define IOMUXC_PAD_ENET1_MDC_FLEXIO2_FLEXIO00 IOMUX_PADCFG(0x443c0098, 0x4, 0x00000000, 0x00000000, 0x443c0248) +#define IOMUXC_PAD_ENET1_MDC_GPIO4_IO00 IOMUX_PADCFG(0x443c0098, 0x5, 0x00000000, 0x00000000, 0x443c0248) +#define IOMUXC_PAD_ENET1_MDIO_ENET_QOS_MDIO IOMUX_PADCFG(0x443c009c, 0x0, 0x00000000, 0x00000000, 0x443c024c) +#define IOMUXC_PAD_ENET1_MDIO_LPUART3_RIN_B IOMUX_PADCFG(0x443c009c, 0x1, 0x00000000, 0x00000000, 0x443c024c) +#define IOMUXC_PAD_ENET1_MDIO_I3C2_SDA IOMUX_PADCFG(0x443c009c, 0x2, 0x443c03d0, 0x00000000, 0x443c024c) +#define IOMUXC_PAD_ENET1_MDIO_HSIOMIX_OTG_PWR1 IOMUX_PADCFG(0x443c009c, 0x3, 0x00000000, 0x00000000, 0x443c024c) +#define IOMUXC_PAD_ENET1_MDIO_FLEXIO2_FLEXIO01 IOMUX_PADCFG(0x443c009c, 0x4, 0x00000000, 0x00000000, 0x443c024c) +#define IOMUXC_PAD_ENET1_MDIO_GPIO4_IO01 IOMUX_PADCFG(0x443c009c, 0x5, 0x00000000, 0x00000000, 0x443c024c) +#define IOMUXC_PAD_ENET1_TD3_ENET_QOS_RGMII_TD3 IOMUX_PADCFG(0x443c00a0, 0x0, 0x00000000, 0x00000000, 0x443c0250) +#define IOMUXC_PAD_ENET1_TD3_CAN2_TX IOMUX_PADCFG(0x443c00a0, 0x2, 0x00000000, 0x00000000, 0x443c0250) +#define IOMUXC_PAD_ENET1_TD3_HSIOMIX_OTG_ID2 IOMUX_PADCFG(0x443c00a0, 0x3, 0x00000000, 0x00000000, 0x443c0250) +#define IOMUXC_PAD_ENET1_TD3_FLEXIO2_FLEXIO02 IOMUX_PADCFG(0x443c00a0, 0x4, 0x00000000, 0x00000000, 0x443c0250) +#define IOMUXC_PAD_ENET1_TD3_GPIO4_IO02 IOMUX_PADCFG(0x443c00a0, 0x5, 0x00000000, 0x00000000, 0x443c0250) +#define IOMUXC_PAD_ENET1_TD2_ENET_QOS_RGMII_TD2 IOMUX_PADCFG(0x443c00a4, 0x0, 0x00000000, 0x00000000, 0x443c0254) +#define IOMUXC_PAD_ENET1_TD2_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK IOMUX_PADCFG(0x443c00a4, 0x1, 0x00000000, 0x00000000, 0x443c0254) +#define IOMUXC_PAD_ENET1_TD2_CAN2_RX IOMUX_PADCFG(0x443c00a4, 0x2, 0x443c0364, 0x00000002, 0x443c0254) +#define IOMUXC_PAD_ENET1_TD2_HSIOMIX_OTG_OC2 IOMUX_PADCFG(0x443c00a4, 0x3, 0x00000000, 0x00000000, 0x443c0254) +#define IOMUXC_PAD_ENET1_TD2_FLEXIO2_FLEXIO03 IOMUX_PADCFG(0x443c00a4, 0x4, 0x00000000, 0x00000000, 0x443c0254) +#define IOMUXC_PAD_ENET1_TD2_GPIO4_IO03 IOMUX_PADCFG(0x443c00a4, 0x5, 0x00000000, 0x00000000, 0x443c0254) +#define IOMUXC_PAD_ENET1_TD1_ENET_QOS_RGMII_TD1 IOMUX_PADCFG(0x443c00a8, 0x0, 0x00000000, 0x00000000, 0x443c0258) +#define IOMUXC_PAD_ENET1_TD1_LPUART3_RTS_B IOMUX_PADCFG(0x443c00a8, 0x1, 0x00000000, 0x00000000, 0x443c0258) +#define IOMUXC_PAD_ENET1_TD1_I3C2_PUR IOMUX_PADCFG(0x443c00a8, 0x2, 0x00000000, 0x00000000, 0x443c0258) +#define IOMUXC_PAD_ENET1_TD1_HSIOMIX_OTG_OC1 IOMUX_PADCFG(0x443c00a8, 0x3, 0x00000000, 0x00000000, 0x443c0258) +#define IOMUXC_PAD_ENET1_TD1_FLEXIO2_FLEXIO04 IOMUX_PADCFG(0x443c00a8, 0x4, 0x00000000, 0x00000000, 0x443c0258) +#define IOMUXC_PAD_ENET1_TD1_GPIO4_IO04 IOMUX_PADCFG(0x443c00a8, 0x5, 0x00000000, 0x00000000, 0x443c0258) +#define IOMUXC_PAD_ENET1_TD1_I3C2_PUR_B IOMUX_PADCFG(0x443c00a8, 0x6, 0x00000000, 0x00000000, 0x443c0258) +#define IOMUXC_PAD_ENET1_TD0_ENET_QOS_RGMII_TD0 IOMUX_PADCFG(0x443c00ac, 0x0, 0x00000000, 0x00000000, 0x443c025c) +#define IOMUXC_PAD_ENET1_TD0_LPUART3_TX IOMUX_PADCFG(0x443c00ac, 0x1, 0x443c041c, 0x00000001, 0x443c025c) +#define IOMUXC_PAD_ENET1_TD0_FLEXIO2_FLEXIO05 IOMUX_PADCFG(0x443c00ac, 0x4, 0x00000000, 0x00000000, 0x443c025c) +#define IOMUXC_PAD_ENET1_TD0_GPIO4_IO05 IOMUX_PADCFG(0x443c00ac, 0x5, 0x00000000, 0x00000000, 0x443c025c) +#define IOMUXC_PAD_ENET1_TX_CTL_ENET_QOS_RGMII_TX_CTL IOMUX_PADCFG(0x443c00b0, 0x0, 0x00000000, 0x00000000, 0x443c0260) +#define IOMUXC_PAD_ENET1_TX_CTL_LPUART3_DTR_B IOMUX_PADCFG(0x443c00b0, 0x1, 0x00000000, 0x00000000, 0x443c0260) +#define IOMUXC_PAD_ENET1_TX_CTL_FLEXIO2_FLEXIO06 IOMUX_PADCFG(0x443c00b0, 0x4, 0x00000000, 0x00000000, 0x443c0260) +#define IOMUXC_PAD_ENET1_TX_CTL_GPIO4_IO06 IOMUX_PADCFG(0x443c00b0, 0x5, 0x00000000, 0x00000000, 0x443c0260) +#define IOMUXC_PAD_ENET1_TXC_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK IOMUX_PADCFG(0x443c00b4, 0x0, 0x00000000, 0x00000000, 0x443c0264) +#define IOMUXC_PAD_ENET1_TXC_ENET_QOS_TX_ER IOMUX_PADCFG(0x443c00b4, 0x1, 0x00000000, 0x00000000, 0x443c0264) +#define IOMUXC_PAD_ENET1_TXC_FLEXIO2_FLEXIO07 IOMUX_PADCFG(0x443c00b4, 0x4, 0x00000000, 0x00000000, 0x443c0264) +#define IOMUXC_PAD_ENET1_TXC_GPIO4_IO07 IOMUX_PADCFG(0x443c00b4, 0x5, 0x00000000, 0x00000000, 0x443c0264) +#define IOMUXC_PAD_ENET1_RX_CTL_ENET_QOS_RGMII_RX_CTL IOMUX_PADCFG(0x443c00b8, 0x0, 0x00000000, 0x00000000, 0x443c0268) +#define IOMUXC_PAD_ENET1_RX_CTL_LPUART3_DSR_B IOMUX_PADCFG(0x443c00b8, 0x1, 0x00000000, 0x00000000, 0x443c0268) +#define IOMUXC_PAD_ENET1_RX_CTL_HSIOMIX_OTG_PWR2 IOMUX_PADCFG(0x443c00b8, 0x3, 0x00000000, 0x00000000, 0x443c0268) +#define IOMUXC_PAD_ENET1_RX_CTL_FLEXIO2_FLEXIO08 IOMUX_PADCFG(0x443c00b8, 0x4, 0x00000000, 0x00000000, 0x443c0268) +#define IOMUXC_PAD_ENET1_RX_CTL_GPIO4_IO08 IOMUX_PADCFG(0x443c00b8, 0x5, 0x00000000, 0x00000000, 0x443c0268) +#define IOMUXC_PAD_ENET1_RXC_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK IOMUX_PADCFG(0x443c00bc, 0x0, 0x00000000, 0x00000000, 0x443c026c) +#define IOMUXC_PAD_ENET1_RXC_ENET_QOS_RX_ER IOMUX_PADCFG(0x443c00bc, 0x1, 0x00000000, 0x00000000, 0x443c026c) +#define IOMUXC_PAD_ENET1_RXC_FLEXIO2_FLEXIO09 IOMUX_PADCFG(0x443c00bc, 0x4, 0x00000000, 0x00000000, 0x443c026c) +#define IOMUXC_PAD_ENET1_RXC_GPIO4_IO09 IOMUX_PADCFG(0x443c00bc, 0x5, 0x00000000, 0x00000000, 0x443c026c) +#define IOMUXC_PAD_ENET1_RD0_ENET_QOS_RGMII_RD0 IOMUX_PADCFG(0x443c00c0, 0x0, 0x00000000, 0x00000000, 0x443c0270) +#define IOMUXC_PAD_ENET1_RD0_LPUART3_RX IOMUX_PADCFG(0x443c00c0, 0x1, 0x443c0418, 0x00000001, 0x443c0270) +#define IOMUXC_PAD_ENET1_RD0_FLEXIO2_FLEXIO10 IOMUX_PADCFG(0x443c00c0, 0x4, 0x00000000, 0x00000000, 0x443c0270) +#define IOMUXC_PAD_ENET1_RD0_GPIO4_IO10 IOMUX_PADCFG(0x443c00c0, 0x5, 0x00000000, 0x00000000, 0x443c0270) +#define IOMUXC_PAD_ENET1_RD1_ENET_QOS_RGMII_RD1 IOMUX_PADCFG(0x443c00c4, 0x0, 0x00000000, 0x00000000, 0x443c0274) +#define IOMUXC_PAD_ENET1_RD1_LPUART3_CTS_B IOMUX_PADCFG(0x443c00c4, 0x1, 0x443c0414, 0x00000001, 0x443c0274) +#define IOMUXC_PAD_ENET1_RD1_LPTMR2_ALT1 IOMUX_PADCFG(0x443c00c4, 0x3, 0x443c0408, 0x00000000, 0x443c0274) +#define IOMUXC_PAD_ENET1_RD1_FLEXIO2_FLEXIO11 IOMUX_PADCFG(0x443c00c4, 0x4, 0x00000000, 0x00000000, 0x443c0274) +#define IOMUXC_PAD_ENET1_RD1_GPIO4_IO11 IOMUX_PADCFG(0x443c00c4, 0x5, 0x00000000, 0x00000000, 0x443c0274) +#define IOMUXC_PAD_ENET1_RD2_ENET_QOS_RGMII_RD2 IOMUX_PADCFG(0x443c00c8, 0x0, 0x00000000, 0x00000000, 0x443c0278) +#define IOMUXC_PAD_ENET1_RD2_LPTMR2_ALT2 IOMUX_PADCFG(0x443c00c8, 0x3, 0x443c040c, 0x00000000, 0x443c0278) +#define IOMUXC_PAD_ENET1_RD2_FLEXIO2_FLEXIO12 IOMUX_PADCFG(0x443c00c8, 0x4, 0x00000000, 0x00000000, 0x443c0278) +#define IOMUXC_PAD_ENET1_RD2_GPIO4_IO12 IOMUX_PADCFG(0x443c00c8, 0x5, 0x00000000, 0x00000000, 0x443c0278) +#define IOMUXC_PAD_ENET1_RD3_ENET_QOS_RGMII_RD3 IOMUX_PADCFG(0x443c00cc, 0x0, 0x00000000, 0x00000000, 0x443c027c) +#define IOMUXC_PAD_ENET1_RD3_FLEXSPI1_TESTER_TRIGGER IOMUX_PADCFG(0x443c00cc, 0x2, 0x00000000, 0x00000000, 0x443c027c) +#define IOMUXC_PAD_ENET1_RD3_LPTMR2_ALT3 IOMUX_PADCFG(0x443c00cc, 0x3, 0x443c0410, 0x00000000, 0x443c027c) +#define IOMUXC_PAD_ENET1_RD3_FLEXIO2_FLEXIO13 IOMUX_PADCFG(0x443c00cc, 0x4, 0x00000000, 0x00000000, 0x443c027c) +#define IOMUXC_PAD_ENET1_RD3_GPIO4_IO13 IOMUX_PADCFG(0x443c00cc, 0x5, 0x00000000, 0x00000000, 0x443c027c) +#define IOMUXC_PAD_ENET2_MDC_ENET1_MDC IOMUX_PADCFG(0x443c00d0, 0x0, 0x00000000, 0x00000000, 0x443c0280) +#define IOMUXC_PAD_ENET2_MDC_LPUART4_DCB_B IOMUX_PADCFG(0x443c00d0, 0x1, 0x00000000, 0x00000000, 0x443c0280) +#define IOMUXC_PAD_ENET2_MDC_SAI2_RX_SYNC IOMUX_PADCFG(0x443c00d0, 0x2, 0x00000000, 0x00000000, 0x443c0280) +#define IOMUXC_PAD_ENET2_MDC_FLEXIO2_FLEXIO14 IOMUX_PADCFG(0x443c00d0, 0x4, 0x00000000, 0x00000000, 0x443c0280) +#define IOMUXC_PAD_ENET2_MDC_GPIO4_IO14 IOMUX_PADCFG(0x443c00d0, 0x5, 0x00000000, 0x00000000, 0x443c0280) +#define IOMUXC_PAD_ENET2_MDIO_ENET1_MDIO IOMUX_PADCFG(0x443c00d4, 0x0, 0x00000000, 0x00000000, 0x443c0284) +#define IOMUXC_PAD_ENET2_MDIO_LPUART4_RIN_B IOMUX_PADCFG(0x443c00d4, 0x1, 0x00000000, 0x00000000, 0x443c0284) +#define IOMUXC_PAD_ENET2_MDIO_SAI2_RX_BCLK IOMUX_PADCFG(0x443c00d4, 0x2, 0x00000000, 0x00000000, 0x443c0284) +#define IOMUXC_PAD_ENET2_MDIO_FLEXIO2_FLEXIO15 IOMUX_PADCFG(0x443c00d4, 0x4, 0x00000000, 0x00000000, 0x443c0284) +#define IOMUXC_PAD_ENET2_MDIO_GPIO4_IO15 IOMUX_PADCFG(0x443c00d4, 0x5, 0x00000000, 0x00000000, 0x443c0284) +#define IOMUXC_PAD_ENET2_TD3_SAI2_RX_DATA00 IOMUX_PADCFG(0x443c00d8, 0x2, 0x00000000, 0x00000000, 0x443c0288) +#define IOMUXC_PAD_ENET2_TD3_FLEXIO2_FLEXIO16 IOMUX_PADCFG(0x443c00d8, 0x4, 0x00000000, 0x00000000, 0x443c0288) +#define IOMUXC_PAD_ENET2_TD3_GPIO4_IO16 IOMUX_PADCFG(0x443c00d8, 0x5, 0x00000000, 0x00000000, 0x443c0288) +#define IOMUXC_PAD_ENET2_TD3_ENET1_RGMII_TD3 IOMUX_PADCFG(0x443c00d8, 0x0, 0x00000000, 0x00000000, 0x443c0288) +#define IOMUXC_PAD_ENET2_TD2_ENET1_RGMII_TD2 IOMUX_PADCFG(0x443c00dc, 0x0, 0x00000000, 0x00000000, 0x443c028c) +#define IOMUXC_PAD_ENET2_TD2_ENET1_TX_CLK IOMUX_PADCFG(0x443c00dc, 0x1, 0x00000000, 0x00000000, 0x443c028c) +#define IOMUXC_PAD_ENET2_TD2_SAI2_RX_DATA01 IOMUX_PADCFG(0x443c00dc, 0x2, 0x00000000, 0x00000000, 0x443c028c) +#define IOMUXC_PAD_ENET2_TD2_FLEXIO2_FLEXIO17 IOMUX_PADCFG(0x443c00dc, 0x4, 0x00000000, 0x00000000, 0x443c028c) +#define IOMUXC_PAD_ENET2_TD2_GPIO4_IO17 IOMUX_PADCFG(0x443c00dc, 0x5, 0x00000000, 0x00000000, 0x443c028c) +#define IOMUXC_PAD_ENET2_TD1_ENET1_RGMII_TD1 IOMUX_PADCFG(0x443c00e0, 0x0, 0x00000000, 0x00000000, 0x443c0290) +#define IOMUXC_PAD_ENET2_TD1_LPUART4_RTS_B IOMUX_PADCFG(0x443c00e0, 0x1, 0x00000000, 0x00000000, 0x443c0290) +#define IOMUXC_PAD_ENET2_TD1_SAI2_RX_DATA02 IOMUX_PADCFG(0x443c00e0, 0x2, 0x00000000, 0x00000000, 0x443c0290) +#define IOMUXC_PAD_ENET2_TD1_FLEXIO2_FLEXIO18 IOMUX_PADCFG(0x443c00e0, 0x4, 0x00000000, 0x00000000, 0x443c0290) +#define IOMUXC_PAD_ENET2_TD1_GPIO4_IO18 IOMUX_PADCFG(0x443c00e0, 0x5, 0x00000000, 0x00000000, 0x443c0290) +#define IOMUXC_PAD_ENET2_TD0_ENET1_RGMII_TD0 IOMUX_PADCFG(0x443c00e4, 0x0, 0x00000000, 0x00000000, 0x443c0294) +#define IOMUXC_PAD_ENET2_TD0_LPUART4_TX IOMUX_PADCFG(0x443c00e4, 0x1, 0x443c0428, 0x00000001, 0x443c0294) +#define IOMUXC_PAD_ENET2_TD0_SAI2_RX_DATA03 IOMUX_PADCFG(0x443c00e4, 0x2, 0x00000000, 0x00000000, 0x443c0294) +#define IOMUXC_PAD_ENET2_TD0_FLEXIO2_FLEXIO19 IOMUX_PADCFG(0x443c00e4, 0x4, 0x00000000, 0x00000000, 0x443c0294) +#define IOMUXC_PAD_ENET2_TD0_GPIO4_IO19 IOMUX_PADCFG(0x443c00e4, 0x5, 0x00000000, 0x00000000, 0x443c0294) +#define IOMUXC_PAD_ENET2_TX_CTL_ENET1_RGMII_TX_CTL IOMUX_PADCFG(0x443c00e8, 0x0, 0x00000000, 0x00000000, 0x443c0298) +#define IOMUXC_PAD_ENET2_TX_CTL_LPUART4_DTR_B IOMUX_PADCFG(0x443c00e8, 0x1, 0x00000000, 0x00000000, 0x443c0298) +#define IOMUXC_PAD_ENET2_TX_CTL_SAI2_TX_SYNC IOMUX_PADCFG(0x443c00e8, 0x2, 0x00000000, 0x00000000, 0x443c0298) +#define IOMUXC_PAD_ENET2_TX_CTL_FLEXIO2_FLEXIO20 IOMUX_PADCFG(0x443c00e8, 0x4, 0x00000000, 0x00000000, 0x443c0298) +#define IOMUXC_PAD_ENET2_TX_CTL_GPIO4_IO20 IOMUX_PADCFG(0x443c00e8, 0x5, 0x00000000, 0x00000000, 0x443c0298) +#define IOMUXC_PAD_ENET2_TXC_ENET1_RGMII_TXC IOMUX_PADCFG(0x443c00ec, 0x0, 0x00000000, 0x00000000, 0x443c029c) +#define IOMUXC_PAD_ENET2_TXC_ENET1_TX_ER IOMUX_PADCFG(0x443c00ec, 0x1, 0x00000000, 0x00000000, 0x443c029c) +#define IOMUXC_PAD_ENET2_TXC_SAI2_TX_BCLK IOMUX_PADCFG(0x443c00ec, 0x2, 0x00000000, 0x00000000, 0x443c029c) +#define IOMUXC_PAD_ENET2_TXC_FLEXIO2_FLEXIO21 IOMUX_PADCFG(0x443c00ec, 0x4, 0x00000000, 0x00000000, 0x443c029c) +#define IOMUXC_PAD_ENET2_TXC_GPIO4_IO21 IOMUX_PADCFG(0x443c00ec, 0x5, 0x00000000, 0x00000000, 0x443c029c) +#define IOMUXC_PAD_ENET2_RX_CTL_ENET1_RGMII_RX_CTL IOMUX_PADCFG(0x443c00f0, 0x0, 0x00000000, 0x00000000, 0x443c02a0) +#define IOMUXC_PAD_ENET2_RX_CTL_LPUART4_DSR_B IOMUX_PADCFG(0x443c00f0, 0x1, 0x00000000, 0x00000000, 0x443c02a0) +#define IOMUXC_PAD_ENET2_RX_CTL_SAI2_TX_DATA00 IOMUX_PADCFG(0x443c00f0, 0x2, 0x00000000, 0x00000000, 0x443c02a0) +#define IOMUXC_PAD_ENET2_RX_CTL_FLEXIO2_FLEXIO22 IOMUX_PADCFG(0x443c00f0, 0x4, 0x00000000, 0x00000000, 0x443c02a0) +#define IOMUXC_PAD_ENET2_RX_CTL_GPIO4_IO22 IOMUX_PADCFG(0x443c00f0, 0x5, 0x00000000, 0x00000000, 0x443c02a0) +#define IOMUXC_PAD_ENET2_RXC_ENET1_RGMII_RXC IOMUX_PADCFG(0x443c00f4, 0x0, 0x00000000, 0x00000000, 0x443c02a4) +#define IOMUXC_PAD_ENET2_RXC_ENET1_RX_ER IOMUX_PADCFG(0x443c00f4, 0x1, 0x00000000, 0x00000000, 0x443c02a4) +#define IOMUXC_PAD_ENET2_RXC_SAI2_TX_DATA01 IOMUX_PADCFG(0x443c00f4, 0x2, 0x00000000, 0x00000000, 0x443c02a4) +#define IOMUXC_PAD_ENET2_RXC_FLEXIO2_FLEXIO23 IOMUX_PADCFG(0x443c00f4, 0x4, 0x00000000, 0x00000000, 0x443c02a4) +#define IOMUXC_PAD_ENET2_RXC_GPIO4_IO23 IOMUX_PADCFG(0x443c00f4, 0x5, 0x00000000, 0x00000000, 0x443c02a4) +#define IOMUXC_PAD_ENET2_RD0_ENET1_RGMII_RD0 IOMUX_PADCFG(0x443c00f8, 0x0, 0x00000000, 0x00000000, 0x443c02a8) +#define IOMUXC_PAD_ENET2_RD0_LPUART4_RX IOMUX_PADCFG(0x443c00f8, 0x1, 0x443c0424, 0x00000001, 0x443c02a8) +#define IOMUXC_PAD_ENET2_RD0_SAI2_TX_DATA02 IOMUX_PADCFG(0x443c00f8, 0x2, 0x00000000, 0x00000000, 0x443c02a8) +#define IOMUXC_PAD_ENET2_RD0_FLEXIO2_FLEXIO24 IOMUX_PADCFG(0x443c00f8, 0x4, 0x00000000, 0x00000000, 0x443c02a8) +#define IOMUXC_PAD_ENET2_RD0_GPIO4_IO24 IOMUX_PADCFG(0x443c00f8, 0x5, 0x00000000, 0x00000000, 0x443c02a8) +#define IOMUXC_PAD_ENET2_RD1_ENET1_RGMII_RD1 IOMUX_PADCFG(0x443c00fc, 0x0, 0x00000000, 0x00000000, 0x443c02ac) +#define IOMUXC_PAD_ENET2_RD1_SPDIF_IN IOMUX_PADCFG(0x443c00fc, 0x1, 0x443c0454, 0x00000001, 0x443c02ac) +#define IOMUXC_PAD_ENET2_RD1_SAI2_TX_DATA03 IOMUX_PADCFG(0x443c00fc, 0x2, 0x00000000, 0x00000000, 0x443c02ac) +#define IOMUXC_PAD_ENET2_RD1_FLEXIO2_FLEXIO25 IOMUX_PADCFG(0x443c00fc, 0x4, 0x00000000, 0x00000000, 0x443c02ac) +#define IOMUXC_PAD_ENET2_RD1_GPIO4_IO25 IOMUX_PADCFG(0x443c00fc, 0x5, 0x00000000, 0x00000000, 0x443c02ac) +#define IOMUXC_PAD_ENET2_RD2_ENET1_RGMII_RD2 IOMUX_PADCFG(0x443c0100, 0x0, 0x00000000, 0x00000000, 0x443c02b0) +#define IOMUXC_PAD_ENET2_RD2_LPUART4_CTS_B IOMUX_PADCFG(0x443c0100, 0x1, 0x443c0420, 0x00000001, 0x443c02b0) +#define IOMUXC_PAD_ENET2_RD2_SAI2_MCLK IOMUX_PADCFG(0x443c0100, 0x2, 0x00000000, 0x00000000, 0x443c02b0) +#define IOMUXC_PAD_ENET2_RD2_MQS2_RIGHT IOMUX_PADCFG(0x443c0100, 0x3, 0x00000000, 0x00000000, 0x443c02b0) +#define IOMUXC_PAD_ENET2_RD2_FLEXIO2_FLEXIO26 IOMUX_PADCFG(0x443c0100, 0x4, 0x00000000, 0x00000000, 0x443c02b0) +#define IOMUXC_PAD_ENET2_RD2_GPIO4_IO26 IOMUX_PADCFG(0x443c0100, 0x5, 0x00000000, 0x00000000, 0x443c02b0) +#define IOMUXC_PAD_ENET2_RD3_ENET1_RGMII_RD3 IOMUX_PADCFG(0x443c0104, 0x0, 0x00000000, 0x00000000, 0x443c02b4) +#define IOMUXC_PAD_ENET2_RD3_SPDIF_OUT IOMUX_PADCFG(0x443c0104, 0x1, 0x00000000, 0x00000000, 0x443c02b4) +#define IOMUXC_PAD_ENET2_RD3_SPDIF_IN IOMUX_PADCFG(0x443c0104, 0x2, 0x443c0454, 0x00000002, 0x443c02b4) +#define IOMUXC_PAD_ENET2_RD3_MQS2_LEFT IOMUX_PADCFG(0x443c0104, 0x3, 0x00000000, 0x00000000, 0x443c02b4) +#define IOMUXC_PAD_ENET2_RD3_FLEXIO2_FLEXIO27 IOMUX_PADCFG(0x443c0104, 0x4, 0x00000000, 0x00000000, 0x443c02b4) +#define IOMUXC_PAD_ENET2_RD3_GPIO4_IO27 IOMUX_PADCFG(0x443c0104, 0x5, 0x00000000, 0x00000000, 0x443c02b4) +#define IOMUXC_PAD_SD1_CLK_FLEXIO1_FLEXIO08 IOMUX_PADCFG(0x443c0108, 0x4, 0x443c038c, 0x00000001, 0x443c02b8) +#define IOMUXC_PAD_SD1_CLK_GPIO3_IO08 IOMUX_PADCFG(0x443c0108, 0x5, 0x00000000, 0x00000000, 0x443c02b8) +#define IOMUXC_PAD_SD1_CLK_USDHC1_CLK IOMUX_PADCFG(0x443c0108, 0x0, 0x00000000, 0x00000000, 0x443c02b8) +#define IOMUXC_PAD_SD1_CMD_USDHC1_CMD IOMUX_PADCFG(0x443c010c, 0x0, 0x00000000, 0x00000000, 0x443c02bc) +#define IOMUXC_PAD_SD1_CMD_FLEXIO1_FLEXIO09 IOMUX_PADCFG(0x443c010c, 0x4, 0x443c0390, 0x00000001, 0x443c02bc) +#define IOMUXC_PAD_SD1_CMD_GPIO3_IO09 IOMUX_PADCFG(0x443c010c, 0x5, 0x00000000, 0x00000000, 0x443c02bc) +#define IOMUXC_PAD_SD1_DATA0_USDHC1_DATA0 IOMUX_PADCFG(0x443c0110, 0x0, 0x00000000, 0x00000000, 0x443c02c0) +#define IOMUXC_PAD_SD1_DATA0_FLEXIO1_FLEXIO10 IOMUX_PADCFG(0x443c0110, 0x4, 0x443c0394, 0x00000001, 0x443c02c0) +#define IOMUXC_PAD_SD1_DATA0_GPIO3_IO10 IOMUX_PADCFG(0x443c0110, 0x5, 0x00000000, 0x00000000, 0x443c02c0) +#define IOMUXC_PAD_SD1_DATA1_USDHC1_DATA1 IOMUX_PADCFG(0x443c0114, 0x0, 0x00000000, 0x00000000, 0x443c02c4) +#define IOMUXC_PAD_SD1_DATA1_FLEXIO1_FLEXIO11 IOMUX_PADCFG(0x443c0114, 0x4, 0x443c0398, 0x00000001, 0x443c02c4) +#define IOMUXC_PAD_SD1_DATA1_GPIO3_IO11 IOMUX_PADCFG(0x443c0114, 0x5, 0x00000000, 0x00000000, 0x443c02c4) +#define IOMUXC_PAD_SD1_DATA1_CCMSRCGPCMIX_INT_BOOT IOMUX_PADCFG(0x443c0114, 0x6, 0x00000000, 0x00000000, 0x443c02c4) +#define IOMUXC_PAD_SD1_DATA2_USDHC1_DATA2 IOMUX_PADCFG(0x443c0118, 0x0, 0x00000000, 0x00000000, 0x443c02c8) +#define IOMUXC_PAD_SD1_DATA2_FLEXIO1_FLEXIO12 IOMUX_PADCFG(0x443c0118, 0x4, 0x00000000, 0x00000000, 0x443c02c8) +#define IOMUXC_PAD_SD1_DATA2_GPIO3_IO12 IOMUX_PADCFG(0x443c0118, 0x5, 0x00000000, 0x00000000, 0x443c02c8) +#define IOMUXC_PAD_SD1_DATA2_CCMSRCGPCMIX_PMIC_READY IOMUX_PADCFG(0x443c0118, 0x6, 0x00000000, 0x00000000, 0x443c02c8) +#define IOMUXC_PAD_SD1_DATA3_USDHC1_DATA3 IOMUX_PADCFG(0x443c011c, 0x0, 0x00000000, 0x00000000, 0x443c02cc) +#define IOMUXC_PAD_SD1_DATA3_FLEXSPI1_A_SS1_B IOMUX_PADCFG(0x443c011c, 0x1, 0x00000000, 0x00000000, 0x443c02cc) +#define IOMUXC_PAD_SD1_DATA3_FLEXIO1_FLEXIO13 IOMUX_PADCFG(0x443c011c, 0x4, 0x443c039c, 0x00000001, 0x443c02cc) +#define IOMUXC_PAD_SD1_DATA3_GPIO3_IO13 IOMUX_PADCFG(0x443c011c, 0x5, 0x00000000, 0x00000000, 0x443c02cc) +#define IOMUXC_PAD_SD1_DATA4_USDHC1_DATA4 IOMUX_PADCFG(0x443c0120, 0x0, 0x00000000, 0x00000000, 0x443c02d0) +#define IOMUXC_PAD_SD1_DATA4_FLEXSPI1_A_DATA04 IOMUX_PADCFG(0x443c0120, 0x1, 0x00000000, 0x00000000, 0x443c02d0) +#define IOMUXC_PAD_SD1_DATA4_FLEXIO1_FLEXIO14 IOMUX_PADCFG(0x443c0120, 0x4, 0x443c03a0, 0x00000001, 0x443c02d0) +#define IOMUXC_PAD_SD1_DATA4_GPIO3_IO14 IOMUX_PADCFG(0x443c0120, 0x5, 0x00000000, 0x00000000, 0x443c02d0) +#define IOMUXC_PAD_SD1_DATA5_USDHC1_DATA5 IOMUX_PADCFG(0x443c0124, 0x0, 0x00000000, 0x00000000, 0x443c02d4) +#define IOMUXC_PAD_SD1_DATA5_FLEXSPI1_A_DATA05 IOMUX_PADCFG(0x443c0124, 0x1, 0x00000000, 0x00000000, 0x443c02d4) +#define IOMUXC_PAD_SD1_DATA5_USDHC1_RESET_B IOMUX_PADCFG(0x443c0124, 0x2, 0x00000000, 0x00000000, 0x443c02d4) +#define IOMUXC_PAD_SD1_DATA5_FLEXIO1_FLEXIO15 IOMUX_PADCFG(0x443c0124, 0x4, 0x443c03a4, 0x00000001, 0x443c02d4) +#define IOMUXC_PAD_SD1_DATA5_GPIO3_IO15 IOMUX_PADCFG(0x443c0124, 0x5, 0x00000000, 0x00000000, 0x443c02d4) +#define IOMUXC_PAD_SD1_DATA6_USDHC1_DATA6 IOMUX_PADCFG(0x443c0128, 0x0, 0x00000000, 0x00000000, 0x443c02d8) +#define IOMUXC_PAD_SD1_DATA6_FLEXSPI1_A_DATA06 IOMUX_PADCFG(0x443c0128, 0x1, 0x00000000, 0x00000000, 0x443c02d8) +#define IOMUXC_PAD_SD1_DATA6_USDHC1_CD_B IOMUX_PADCFG(0x443c0128, 0x2, 0x00000000, 0x00000000, 0x443c02d8) +#define IOMUXC_PAD_SD1_DATA6_FLEXIO1_FLEXIO16 IOMUX_PADCFG(0x443c0128, 0x4, 0x443c03a8, 0x00000001, 0x443c02d8) +#define IOMUXC_PAD_SD1_DATA6_GPIO3_IO16 IOMUX_PADCFG(0x443c0128, 0x5, 0x00000000, 0x00000000, 0x443c02d8) +#define IOMUXC_PAD_SD1_DATA7_USDHC1_DATA7 IOMUX_PADCFG(0x443c012c, 0x0, 0x00000000, 0x00000000, 0x443c02dc) +#define IOMUXC_PAD_SD1_DATA7_FLEXSPI1_A_DATA07 IOMUX_PADCFG(0x443c012c, 0x1, 0x00000000, 0x00000000, 0x443c02dc) +#define IOMUXC_PAD_SD1_DATA7_USDHC1_WP IOMUX_PADCFG(0x443c012c, 0x2, 0x00000000, 0x00000000, 0x443c02dc) +#define IOMUXC_PAD_SD1_DATA7_FLEXIO1_FLEXIO17 IOMUX_PADCFG(0x443c012c, 0x4, 0x443c03ac, 0x00000001, 0x443c02dc) +#define IOMUXC_PAD_SD1_DATA7_GPIO3_IO17 IOMUX_PADCFG(0x443c012c, 0x5, 0x00000000, 0x00000000, 0x443c02dc) +#define IOMUXC_PAD_SD1_STROBE_USDHC1_STROBE IOMUX_PADCFG(0x443c0130, 0x0, 0x00000000, 0x00000000, 0x443c02e0) +#define IOMUXC_PAD_SD1_STROBE_FLEXSPI1_A_DQS IOMUX_PADCFG(0x443c0130, 0x1, 0x00000000, 0x00000000, 0x443c02e0) +#define IOMUXC_PAD_SD1_STROBE_FLEXIO1_FLEXIO18 IOMUX_PADCFG(0x443c0130, 0x4, 0x443c03b0, 0x00000001, 0x443c02e0) +#define IOMUXC_PAD_SD1_STROBE_GPIO3_IO18 IOMUX_PADCFG(0x443c0130, 0x5, 0x00000000, 0x00000000, 0x443c02e0) +#define IOMUXC_PAD_SD2_VSELECT_USDHC2_VSELECT IOMUX_PADCFG(0x443c0134, 0x0, 0x00000000, 0x00000000, 0x443c02e4) +#define IOMUXC_PAD_SD2_VSELECT_USDHC2_WP IOMUX_PADCFG(0x443c0134, 0x1, 0x00000000, 0x00000000, 0x443c02e4) +#define IOMUXC_PAD_SD2_VSELECT_LPTMR2_ALT3 IOMUX_PADCFG(0x443c0134, 0x2, 0x443c0410, 0x00000001, 0x443c02e4) +#define IOMUXC_PAD_SD2_VSELECT_FLEXIO1_FLEXIO19 IOMUX_PADCFG(0x443c0134, 0x4, 0x00000000, 0x00000000, 0x443c02e4) +#define IOMUXC_PAD_SD2_VSELECT_GPIO3_IO19 IOMUX_PADCFG(0x443c0134, 0x5, 0x00000000, 0x00000000, 0x443c02e4) +#define IOMUXC_PAD_SD2_VSELECT_CCMSRCGPCMIX_EXT_CLK1 IOMUX_PADCFG(0x443c0134, 0x6, 0x443c0368, 0x00000000, 0x443c02e4) +#define IOMUXC_PAD_SD3_CLK_USDHC3_CLK IOMUX_PADCFG(0x443c0138, 0x0, 0x443c0458, 0x00000001, 0x443c02e8) +#define IOMUXC_PAD_SD3_CLK_FLEXSPI1_A_SCLK IOMUX_PADCFG(0x443c0138, 0x1, 0x00000000, 0x00000000, 0x443c02e8) +#define IOMUXC_PAD_SD3_CLK_FLEXIO1_FLEXIO20 IOMUX_PADCFG(0x443c0138, 0x4, 0x443c03b4, 0x00000001, 0x443c02e8) +#define IOMUXC_PAD_SD3_CLK_GPIO3_IO20 IOMUX_PADCFG(0x443c0138, 0x5, 0x00000000, 0x00000000, 0x443c02e8) +#define IOMUXC_PAD_SD3_CMD_USDHC3_CMD IOMUX_PADCFG(0x443c013c, 0x0, 0x443c045c, 0x00000001, 0x443c02ec) +#define IOMUXC_PAD_SD3_CMD_FLEXSPI1_A_SS0_B IOMUX_PADCFG(0x443c013c, 0x1, 0x00000000, 0x00000000, 0x443c02ec) +#define IOMUXC_PAD_SD3_CMD_FLEXIO1_FLEXIO21 IOMUX_PADCFG(0x443c013c, 0x4, 0x00000000, 0x00000000, 0x443c02ec) +#define IOMUXC_PAD_SD3_CMD_GPIO3_IO21 IOMUX_PADCFG(0x443c013c, 0x5, 0x00000000, 0x00000000, 0x443c02ec) +#define IOMUXC_PAD_SD3_DATA0_USDHC3_DATA0 IOMUX_PADCFG(0x443c0140, 0x0, 0x443c0460, 0x00000001, 0x443c02f0) +#define IOMUXC_PAD_SD3_DATA0_FLEXSPI1_A_DATA00 IOMUX_PADCFG(0x443c0140, 0x1, 0x00000000, 0x00000000, 0x443c02f0) +#define IOMUXC_PAD_SD3_DATA0_FLEXIO1_FLEXIO22 IOMUX_PADCFG(0x443c0140, 0x4, 0x443c03b8, 0x00000001, 0x443c02f0) +#define IOMUXC_PAD_SD3_DATA0_GPIO3_IO22 IOMUX_PADCFG(0x443c0140, 0x5, 0x00000000, 0x00000000, 0x443c02f0) +#define IOMUXC_PAD_SD3_DATA1_USDHC3_DATA1 IOMUX_PADCFG(0x443c0144, 0x0, 0x443c0464, 0x00000001, 0x443c02f4) +#define IOMUXC_PAD_SD3_DATA1_FLEXSPI1_A_DATA01 IOMUX_PADCFG(0x443c0144, 0x1, 0x00000000, 0x00000000, 0x443c02f4) +#define IOMUXC_PAD_SD3_DATA1_FLEXIO1_FLEXIO23 IOMUX_PADCFG(0x443c0144, 0x4, 0x443c03bc, 0x00000001, 0x443c02f4) +#define IOMUXC_PAD_SD3_DATA1_GPIO3_IO23 IOMUX_PADCFG(0x443c0144, 0x5, 0x00000000, 0x00000000, 0x443c02f4) +#define IOMUXC_PAD_SD3_DATA2_USDHC3_DATA2 IOMUX_PADCFG(0x443c0148, 0x0, 0x443c0468, 0x00000001, 0x443c02f8) +#define IOMUXC_PAD_SD3_DATA2_FLEXSPI1_A_DATA02 IOMUX_PADCFG(0x443c0148, 0x1, 0x00000000, 0x00000000, 0x443c02f8) +#define IOMUXC_PAD_SD3_DATA2_FLEXIO1_FLEXIO24 IOMUX_PADCFG(0x443c0148, 0x4, 0x443c03c0, 0x00000001, 0x443c02f8) +#define IOMUXC_PAD_SD3_DATA2_GPIO3_IO24 IOMUX_PADCFG(0x443c0148, 0x5, 0x00000000, 0x00000000, 0x443c02f8) +#define IOMUXC_PAD_SD3_DATA3_USDHC3_DATA3 IOMUX_PADCFG(0x443c014c, 0x0, 0x443c046c, 0x00000001, 0x443c02fc) +#define IOMUXC_PAD_SD3_DATA3_FLEXSPI1_A_DATA03 IOMUX_PADCFG(0x443c014c, 0x1, 0x00000000, 0x00000000, 0x443c02fc) +#define IOMUXC_PAD_SD3_DATA3_FLEXIO1_FLEXIO25 IOMUX_PADCFG(0x443c014c, 0x4, 0x443c03c4, 0x00000001, 0x443c02fc) +#define IOMUXC_PAD_SD3_DATA3_GPIO3_IO25 IOMUX_PADCFG(0x443c014c, 0x5, 0x00000000, 0x00000000, 0x443c02fc) +#define IOMUXC_PAD_SD2_CD_B_USDHC2_CD_B IOMUX_PADCFG(0x443c0150, 0x0, 0x00000000, 0x00000000, 0x443c0300) +#define IOMUXC_PAD_SD2_CD_B_ENET_QOS_1588_EVENT0_IN IOMUX_PADCFG(0x443c0150, 0x1, 0x00000000, 0x00000000, 0x443c0300) +#define IOMUXC_PAD_SD2_CD_B_I3C2_SCL IOMUX_PADCFG(0x443c0150, 0x2, 0x443c03cc, 0x00000001, 0x443c0300) +#define IOMUXC_PAD_SD2_CD_B_FLEXIO1_FLEXIO00 IOMUX_PADCFG(0x443c0150, 0x4, 0x443c036c, 0x00000001, 0x443c0300) +#define IOMUXC_PAD_SD2_CD_B_GPIO3_IO00 IOMUX_PADCFG(0x443c0150, 0x5, 0x00000000, 0x00000000, 0x443c0300) +#define IOMUXC_PAD_SD2_CLK_USDHC2_CLK IOMUX_PADCFG(0x443c0154, 0x0, 0x00000000, 0x00000000, 0x443c0304) +#define IOMUXC_PAD_SD2_CLK_ENET_QOS_1588_EVENT0_OUT IOMUX_PADCFG(0x443c0154, 0x1, 0x00000000, 0x00000000, 0x443c0304) +#define IOMUXC_PAD_SD2_CLK_I3C2_SDA IOMUX_PADCFG(0x443c0154, 0x2, 0x443c03d0, 0x00000001, 0x443c0304) +#define IOMUXC_PAD_SD2_CLK_FLEXIO1_FLEXIO01 IOMUX_PADCFG(0x443c0154, 0x4, 0x443c0370, 0x00000001, 0x443c0304) +#define IOMUXC_PAD_SD2_CLK_GPIO3_IO01 IOMUX_PADCFG(0x443c0154, 0x5, 0x00000000, 0x00000000, 0x443c0304) +#define IOMUXC_PAD_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 IOMUX_PADCFG(0x443c0154, 0x6, 0x00000000, 0x00000000, 0x443c0304) +#define IOMUXC_PAD_SD2_CMD_USDHC2_CMD IOMUX_PADCFG(0x443c0158, 0x0, 0x00000000, 0x00000000, 0x443c0308) +#define IOMUXC_PAD_SD2_CMD_ENET1_1588_EVENT0_IN IOMUX_PADCFG(0x443c0158, 0x1, 0x00000000, 0x00000000, 0x443c0308) +#define IOMUXC_PAD_SD2_CMD_I3C2_PUR IOMUX_PADCFG(0x443c0158, 0x2, 0x00000000, 0x00000000, 0x443c0308) +#define IOMUXC_PAD_SD2_CMD_I3C2_PUR_B IOMUX_PADCFG(0x443c0158, 0x3, 0x00000000, 0x00000000, 0x443c0308) +#define IOMUXC_PAD_SD2_CMD_FLEXIO1_FLEXIO02 IOMUX_PADCFG(0x443c0158, 0x4, 0x443c0374, 0x00000001, 0x443c0308) +#define IOMUXC_PAD_SD2_CMD_GPIO3_IO02 IOMUX_PADCFG(0x443c0158, 0x5, 0x00000000, 0x00000000, 0x443c0308) +#define IOMUXC_PAD_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 IOMUX_PADCFG(0x443c0158, 0x6, 0x00000000, 0x00000000, 0x443c0308) +#define IOMUXC_PAD_SD2_DATA0_USDHC2_DATA0 IOMUX_PADCFG(0x443c015c, 0x0, 0x00000000, 0x00000000, 0x443c030c) +#define IOMUXC_PAD_SD2_DATA0_ENET1_1588_EVENT0_OUT IOMUX_PADCFG(0x443c015c, 0x1, 0x00000000, 0x00000000, 0x443c030c) +#define IOMUXC_PAD_SD2_DATA0_CAN2_TX IOMUX_PADCFG(0x443c015c, 0x2, 0x00000000, 0x00000000, 0x443c030c) +#define IOMUXC_PAD_SD2_DATA0_FLEXIO1_FLEXIO03 IOMUX_PADCFG(0x443c015c, 0x4, 0x443c0378, 0x00000001, 0x443c030c) +#define IOMUXC_PAD_SD2_DATA0_GPIO3_IO03 IOMUX_PADCFG(0x443c015c, 0x5, 0x00000000, 0x00000000, 0x443c030c) +#define IOMUXC_PAD_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 IOMUX_PADCFG(0x443c015c, 0x6, 0x00000000, 0x00000000, 0x443c030c) +#define IOMUXC_PAD_SD2_DATA1_USDHC2_DATA1 IOMUX_PADCFG(0x443c0160, 0x0, 0x00000000, 0x00000000, 0x443c0310) +#define IOMUXC_PAD_SD2_DATA1_ENET1_1588_EVENT1_IN IOMUX_PADCFG(0x443c0160, 0x1, 0x00000000, 0x00000000, 0x443c0310) +#define IOMUXC_PAD_SD2_DATA1_CAN2_RX IOMUX_PADCFG(0x443c0160, 0x2, 0x443c0364, 0x00000003, 0x443c0310) +#define IOMUXC_PAD_SD2_DATA1_FLEXIO1_FLEXIO04 IOMUX_PADCFG(0x443c0160, 0x4, 0x443c037c, 0x00000001, 0x443c0310) +#define IOMUXC_PAD_SD2_DATA1_GPIO3_IO04 IOMUX_PADCFG(0x443c0160, 0x5, 0x00000000, 0x00000000, 0x443c0310) +#define IOMUXC_PAD_SD2_DATA1_CCMSRCGPCMIX_WAIT IOMUX_PADCFG(0x443c0160, 0x6, 0x00000000, 0x00000000, 0x443c0310) +#define IOMUXC_PAD_SD2_DATA2_USDHC2_DATA2 IOMUX_PADCFG(0x443c0164, 0x0, 0x00000000, 0x00000000, 0x443c0314) +#define IOMUXC_PAD_SD2_DATA2_ENET1_1588_EVENT1_OUT IOMUX_PADCFG(0x443c0164, 0x1, 0x00000000, 0x00000000, 0x443c0314) +#define IOMUXC_PAD_SD2_DATA2_MQS2_RIGHT IOMUX_PADCFG(0x443c0164, 0x2, 0x00000000, 0x00000000, 0x443c0314) +#define IOMUXC_PAD_SD2_DATA2_FLEXIO1_FLEXIO05 IOMUX_PADCFG(0x443c0164, 0x4, 0x443c0380, 0x00000001, 0x443c0314) +#define IOMUXC_PAD_SD2_DATA2_GPIO3_IO05 IOMUX_PADCFG(0x443c0164, 0x5, 0x00000000, 0x00000000, 0x443c0314) +#define IOMUXC_PAD_SD2_DATA2_CCMSRCGPCMIX_STOP IOMUX_PADCFG(0x443c0164, 0x6, 0x00000000, 0x00000000, 0x443c0314) +#define IOMUXC_PAD_SD2_DATA3_USDHC2_DATA3 IOMUX_PADCFG(0x443c0168, 0x0, 0x00000000, 0x00000000, 0x443c0318) +#define IOMUXC_PAD_SD2_DATA3_LPTMR2_ALT1 IOMUX_PADCFG(0x443c0168, 0x1, 0x443c0408, 0x00000001, 0x443c0318) +#define IOMUXC_PAD_SD2_DATA3_MQS2_LEFT IOMUX_PADCFG(0x443c0168, 0x2, 0x00000000, 0x00000000, 0x443c0318) +#define IOMUXC_PAD_SD2_DATA3_FLEXIO1_FLEXIO06 IOMUX_PADCFG(0x443c0168, 0x4, 0x443c0384, 0x00000001, 0x443c0318) +#define IOMUXC_PAD_SD2_DATA3_GPIO3_IO06 IOMUX_PADCFG(0x443c0168, 0x5, 0x00000000, 0x00000000, 0x443c0318) +#define IOMUXC_PAD_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET IOMUX_PADCFG(0x443c0168, 0x6, 0x00000000, 0x00000000, 0x443c0318) +#define IOMUXC_PAD_SD2_RESET_B_USDHC2_RESET_B IOMUX_PADCFG(0x443c016c, 0x0, 0x00000000, 0x00000000, 0x443c031c) +#define IOMUXC_PAD_SD2_RESET_B_LPTMR2_ALT2 IOMUX_PADCFG(0x443c016c, 0x1, 0x443c040c, 0x00000001, 0x443c031c) +#define IOMUXC_PAD_SD2_RESET_B_FLEXIO1_FLEXIO07 IOMUX_PADCFG(0x443c016c, 0x4, 0x443c0388, 0x00000001, 0x443c031c) +#define IOMUXC_PAD_SD2_RESET_B_GPIO3_IO07 IOMUX_PADCFG(0x443c016c, 0x5, 0x00000000, 0x00000000, 0x443c031c) +#define IOMUXC_PAD_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET IOMUX_PADCFG(0x443c016c, 0x6, 0x00000000, 0x00000000, 0x443c031c) +#define IOMUXC_PAD_I2C1_SCL_LPI2C1_SCL IOMUX_PADCFG(0x443c0170, 0x0, 0x00000000, 0x00000000, 0x443c0320) +#define IOMUXC_PAD_I2C1_SCL_I3C1_SCL IOMUX_PADCFG(0x443c0170, 0x1, 0x00000000, 0x00000000, 0x443c0320) +#define IOMUXC_PAD_I2C1_SCL_LPUART1_DCB_B IOMUX_PADCFG(0x443c0170, 0x2, 0x00000000, 0x00000000, 0x443c0320) +#define IOMUXC_PAD_I2C1_SCL_TPM2_CH0 IOMUX_PADCFG(0x443c0170, 0x3, 0x00000000, 0x00000000, 0x443c0320) +#define IOMUXC_PAD_I2C1_SCL_GPIO1_IO00 IOMUX_PADCFG(0x443c0170, 0x5, 0x00000000, 0x00000000, 0x443c0320) +#define IOMUXC_PAD_I2C1_SDA_LPI2C1_SDA IOMUX_PADCFG(0x443c0174, 0x0, 0x00000000, 0x00000000, 0x443c0324) +#define IOMUXC_PAD_I2C1_SDA_I3C1_SDA IOMUX_PADCFG(0x443c0174, 0x1, 0x00000000, 0x00000000, 0x443c0324) +#define IOMUXC_PAD_I2C1_SDA_LPUART1_RIN_B IOMUX_PADCFG(0x443c0174, 0x2, 0x00000000, 0x00000000, 0x443c0324) +#define IOMUXC_PAD_I2C1_SDA_TPM2_CH1 IOMUX_PADCFG(0x443c0174, 0x3, 0x00000000, 0x00000000, 0x443c0324) +#define IOMUXC_PAD_I2C1_SDA_GPIO1_IO01 IOMUX_PADCFG(0x443c0174, 0x5, 0x00000000, 0x00000000, 0x443c0324) +#define IOMUXC_PAD_I2C2_SCL_LPI2C2_SCL IOMUX_PADCFG(0x443c0178, 0x0, 0x00000000, 0x00000000, 0x443c0328) +#define IOMUXC_PAD_I2C2_SCL_I3C1_PUR IOMUX_PADCFG(0x443c0178, 0x1, 0x00000000, 0x00000000, 0x443c0328) +#define IOMUXC_PAD_I2C2_SCL_LPUART2_DCB_B IOMUX_PADCFG(0x443c0178, 0x2, 0x00000000, 0x00000000, 0x443c0328) +#define IOMUXC_PAD_I2C2_SCL_TPM2_CH2 IOMUX_PADCFG(0x443c0178, 0x3, 0x00000000, 0x00000000, 0x443c0328) +#define IOMUXC_PAD_I2C2_SCL_SAI1_RX_SYNC IOMUX_PADCFG(0x443c0178, 0x4, 0x00000000, 0x00000000, 0x443c0328) +#define IOMUXC_PAD_I2C2_SCL_GPIO1_IO02 IOMUX_PADCFG(0x443c0178, 0x5, 0x00000000, 0x00000000, 0x443c0328) +#define IOMUXC_PAD_I2C2_SCL_I3C1_PUR_B IOMUX_PADCFG(0x443c0178, 0x6, 0x00000000, 0x00000000, 0x443c0328) +#define IOMUXC_PAD_I2C2_SDA_LPI2C2_SDA IOMUX_PADCFG(0x443c017c, 0x0, 0x00000000, 0x00000000, 0x443c032c) +#define IOMUXC_PAD_I2C2_SDA_LPUART2_RIN_B IOMUX_PADCFG(0x443c017c, 0x2, 0x00000000, 0x00000000, 0x443c032c) +#define IOMUXC_PAD_I2C2_SDA_TPM2_CH3 IOMUX_PADCFG(0x443c017c, 0x3, 0x00000000, 0x00000000, 0x443c032c) +#define IOMUXC_PAD_I2C2_SDA_SAI1_RX_BCLK IOMUX_PADCFG(0x443c017c, 0x4, 0x00000000, 0x00000000, 0x443c032c) +#define IOMUXC_PAD_I2C2_SDA_GPIO1_IO03 IOMUX_PADCFG(0x443c017c, 0x5, 0x00000000, 0x00000000, 0x443c032c) +#define IOMUXC_PAD_UART1_RXD_LPUART1_RX IOMUX_PADCFG(0x443c0180, 0x0, 0x00000000, 0x00000000, 0x443c0330) +#define IOMUXC_PAD_UART1_RXD_S400_UART_RX IOMUX_PADCFG(0x443c0180, 0x1, 0x00000000, 0x00000000, 0x443c0330) +#define IOMUXC_PAD_UART1_RXD_LPSPI2_SIN IOMUX_PADCFG(0x443c0180, 0x2, 0x00000000, 0x00000000, 0x443c0330) +#define IOMUXC_PAD_UART1_RXD_TPM1_CH0 IOMUX_PADCFG(0x443c0180, 0x3, 0x00000000, 0x00000000, 0x443c0330) +#define IOMUXC_PAD_UART1_RXD_GPIO1_IO04 IOMUX_PADCFG(0x443c0180, 0x5, 0x00000000, 0x00000000, 0x443c0330) +#define IOMUXC_PAD_UART1_TXD_LPUART1_TX IOMUX_PADCFG(0x443c0184, 0x0, 0x00000000, 0x00000000, 0x443c0334) +#define IOMUXC_PAD_UART1_TXD_S400_UART_TX IOMUX_PADCFG(0x443c0184, 0x1, 0x00000000, 0x00000000, 0x443c0334) +#define IOMUXC_PAD_UART1_TXD_LPSPI2_PCS0 IOMUX_PADCFG(0x443c0184, 0x2, 0x00000000, 0x00000000, 0x443c0334) +#define IOMUXC_PAD_UART1_TXD_TPM1_CH1 IOMUX_PADCFG(0x443c0184, 0x3, 0x00000000, 0x00000000, 0x443c0334) +#define IOMUXC_PAD_UART1_TXD_GPIO1_IO05 IOMUX_PADCFG(0x443c0184, 0x5, 0x00000000, 0x00000000, 0x443c0334) +#define IOMUXC_PAD_UART2_RXD_LPUART2_RX IOMUX_PADCFG(0x443c0188, 0x0, 0x00000000, 0x00000000, 0x443c0338) +#define IOMUXC_PAD_UART2_RXD_LPUART1_CTS_B IOMUX_PADCFG(0x443c0188, 0x1, 0x00000000, 0x00000000, 0x443c0338) +#define IOMUXC_PAD_UART2_RXD_LPSPI2_SOUT IOMUX_PADCFG(0x443c0188, 0x2, 0x00000000, 0x00000000, 0x443c0338) +#define IOMUXC_PAD_UART2_RXD_TPM1_CH2 IOMUX_PADCFG(0x443c0188, 0x3, 0x00000000, 0x00000000, 0x443c0338) +#define IOMUXC_PAD_UART2_RXD_SAI1_MCLK IOMUX_PADCFG(0x443c0188, 0x4, 0x443c0448, 0x00000000, 0x443c0338) +#define IOMUXC_PAD_UART2_RXD_GPIO1_IO06 IOMUX_PADCFG(0x443c0188, 0x5, 0x00000000, 0x00000000, 0x443c0338) +#define IOMUXC_PAD_UART2_TXD_LPUART2_TX IOMUX_PADCFG(0x443c018c, 0x0, 0x00000000, 0x00000000, 0x443c033c) +#define IOMUXC_PAD_UART2_TXD_LPUART1_RTS_B IOMUX_PADCFG(0x443c018c, 0x1, 0x00000000, 0x00000000, 0x443c033c) +#define IOMUXC_PAD_UART2_TXD_LPSPI2_SCK IOMUX_PADCFG(0x443c018c, 0x2, 0x00000000, 0x00000000, 0x443c033c) +#define IOMUXC_PAD_UART2_TXD_TPM1_CH3 IOMUX_PADCFG(0x443c018c, 0x3, 0x00000000, 0x00000000, 0x443c033c) +#define IOMUXC_PAD_UART2_TXD_GPIO1_IO07 IOMUX_PADCFG(0x443c018c, 0x5, 0x00000000, 0x00000000, 0x443c033c) +#define IOMUXC_PAD_PDM_CLK_PDM_CLK IOMUX_PADCFG(0x443c0190, 0x0, 0x00000000, 0x00000000, 0x443c0340) +#define IOMUXC_PAD_PDM_CLK_MQS1_LEFT IOMUX_PADCFG(0x443c0190, 0x1, 0x00000000, 0x00000000, 0x443c0340) +#define IOMUXC_PAD_PDM_CLK_LPTMR1_ALT1 IOMUX_PADCFG(0x443c0190, 0x4, 0x00000000, 0x00000000, 0x443c0340) +#define IOMUXC_PAD_PDM_CLK_GPIO1_IO08 IOMUX_PADCFG(0x443c0190, 0x5, 0x00000000, 0x00000000, 0x443c0340) +#define IOMUXC_PAD_PDM_CLK_CAN1_TX IOMUX_PADCFG(0x443c0190, 0x6, 0x00000000, 0x00000000, 0x443c0340) +#define IOMUXC_PAD_PDM_BIT_STREAM0_PDM_BIT_STREAM00 IOMUX_PADCFG(0x443c0194, 0x0, 0x443c0438, 0x00000002, 0x443c0344) +#define IOMUXC_PAD_PDM_BIT_STREAM0_MQS1_RIGHT IOMUX_PADCFG(0x443c0194, 0x1, 0x00000000, 0x00000000, 0x443c0344) +#define IOMUXC_PAD_PDM_BIT_STREAM0_LPSPI1_PCS1 IOMUX_PADCFG(0x443c0194, 0x2, 0x00000000, 0x00000000, 0x443c0344) +#define IOMUXC_PAD_PDM_BIT_STREAM0_TPM1_EXTCLK IOMUX_PADCFG(0x443c0194, 0x3, 0x00000000, 0x00000000, 0x443c0344) +#define IOMUXC_PAD_PDM_BIT_STREAM0_LPTMR1_ALT2 IOMUX_PADCFG(0x443c0194, 0x4, 0x00000000, 0x00000000, 0x443c0344) +#define IOMUXC_PAD_PDM_BIT_STREAM0_GPIO1_IO09 IOMUX_PADCFG(0x443c0194, 0x5, 0x00000000, 0x00000000, 0x443c0344) +#define IOMUXC_PAD_PDM_BIT_STREAM0_CAN1_RX IOMUX_PADCFG(0x443c0194, 0x6, 0x443c0360, 0x00000000, 0x443c0344) +#define IOMUXC_PAD_PDM_BIT_STREAM1_PDM_BIT_STREAM01 IOMUX_PADCFG(0x443c0198, 0x0, 0x443c043c, 0x00000002, 0x443c0348) +#define IOMUXC_PAD_PDM_BIT_STREAM1_NMI_GLUE_NMI IOMUX_PADCFG(0x443c0198, 0x1, 0x00000000, 0x00000000, 0x443c0348) +#define IOMUXC_PAD_PDM_BIT_STREAM1_LPSPI2_PCS1 IOMUX_PADCFG(0x443c0198, 0x2, 0x00000000, 0x00000000, 0x443c0348) +#define IOMUXC_PAD_PDM_BIT_STREAM1_TPM2_EXTCLK IOMUX_PADCFG(0x443c0198, 0x3, 0x00000000, 0x00000000, 0x443c0348) +#define IOMUXC_PAD_PDM_BIT_STREAM1_LPTMR1_ALT3 IOMUX_PADCFG(0x443c0198, 0x4, 0x00000000, 0x00000000, 0x443c0348) +#define IOMUXC_PAD_PDM_BIT_STREAM1_GPIO1_IO10 IOMUX_PADCFG(0x443c0198, 0x5, 0x00000000, 0x00000000, 0x443c0348) +#define IOMUXC_PAD_PDM_BIT_STREAM1_CCMSRCGPCMIX_EXT_CLK1 IOMUX_PADCFG(0x443c0198, 0x6, 0x443c0368, 0x00000001, 0x443c0348) +#define IOMUXC_PAD_SAI1_TXFS_SAI1_TX_SYNC IOMUX_PADCFG(0x443c019c, 0x0, 0x00000000, 0x00000000, 0x443c034c) +#define IOMUXC_PAD_SAI1_TXFS_SAI1_TX_DATA01 IOMUX_PADCFG(0x443c019c, 0x1, 0x00000000, 0x00000000, 0x443c034c) +#define IOMUXC_PAD_SAI1_TXFS_LPSPI1_PCS0 IOMUX_PADCFG(0x443c019c, 0x2, 0x00000000, 0x00000000, 0x443c034c) +#define IOMUXC_PAD_SAI1_TXFS_LPUART2_DTR_B IOMUX_PADCFG(0x443c019c, 0x3, 0x00000000, 0x00000000, 0x443c034c) +#define IOMUXC_PAD_SAI1_TXFS_MQS1_LEFT IOMUX_PADCFG(0x443c019c, 0x4, 0x00000000, 0x00000000, 0x443c034c) +#define IOMUXC_PAD_SAI1_TXFS_GPIO1_IO11 IOMUX_PADCFG(0x443c019c, 0x5, 0x00000000, 0x00000000, 0x443c034c) +#define IOMUXC_PAD_SAI1_TXC_SAI1_TX_BCLK IOMUX_PADCFG(0x443c01a0, 0x0, 0x00000000, 0x00000000, 0x443c0350) +#define IOMUXC_PAD_SAI1_TXC_LPUART2_CTS_B IOMUX_PADCFG(0x443c01a0, 0x1, 0x00000000, 0x00000000, 0x443c0350) +#define IOMUXC_PAD_SAI1_TXC_LPSPI1_SIN IOMUX_PADCFG(0x443c01a0, 0x2, 0x00000000, 0x00000000, 0x443c0350) +#define IOMUXC_PAD_SAI1_TXC_LPUART1_DSR_B IOMUX_PADCFG(0x443c01a0, 0x3, 0x00000000, 0x00000000, 0x443c0350) +#define IOMUXC_PAD_SAI1_TXC_CAN1_RX IOMUX_PADCFG(0x443c01a0, 0x4, 0x443c0360, 0x00000001, 0x443c0350) +#define IOMUXC_PAD_SAI1_TXC_GPIO1_IO12 IOMUX_PADCFG(0x443c01a0, 0x5, 0x00000000, 0x00000000, 0x443c0350) +#define IOMUXC_PAD_SAI1_TXD0_SAI1_TX_DATA00 IOMUX_PADCFG(0x443c01a4, 0x0, 0x00000000, 0x00000000, 0x443c0354) +#define IOMUXC_PAD_SAI1_TXD0_LPUART2_RTS_B IOMUX_PADCFG(0x443c01a4, 0x1, 0x00000000, 0x00000000, 0x443c0354) +#define IOMUXC_PAD_SAI1_TXD0_LPSPI1_SCK IOMUX_PADCFG(0x443c01a4, 0x2, 0x00000000, 0x00000000, 0x443c0354) +#define IOMUXC_PAD_SAI1_TXD0_LPUART1_DTR_B IOMUX_PADCFG(0x443c01a4, 0x3, 0x00000000, 0x00000000, 0x443c0354) +#define IOMUXC_PAD_SAI1_TXD0_CAN1_TX IOMUX_PADCFG(0x443c01a4, 0x4, 0x00000000, 0x00000000, 0x443c0354) +#define IOMUXC_PAD_SAI1_TXD0_GPIO1_IO13 IOMUX_PADCFG(0x443c01a4, 0x5, 0x00000000, 0x00000000, 0x443c0354) +#define IOMUXC_PAD_SAI1_RXD0_SAI1_RX_DATA00 IOMUX_PADCFG(0x443c01a8, 0x0, 0x00000000, 0x00000000, 0x443c0358) +#define IOMUXC_PAD_SAI1_RXD0_SAI1_MCLK IOMUX_PADCFG(0x443c01a8, 0x1, 0x443c0448, 0x00000001, 0x443c0358) +#define IOMUXC_PAD_SAI1_RXD0_LPSPI1_SOUT IOMUX_PADCFG(0x443c01a8, 0x2, 0x00000000, 0x00000000, 0x443c0358) +#define IOMUXC_PAD_SAI1_RXD0_LPUART2_DSR_B IOMUX_PADCFG(0x443c01a8, 0x3, 0x00000000, 0x00000000, 0x443c0358) +#define IOMUXC_PAD_SAI1_RXD0_MQS1_RIGHT IOMUX_PADCFG(0x443c01a8, 0x4, 0x00000000, 0x00000000, 0x443c0358) +#define IOMUXC_PAD_SAI1_RXD0_GPIO1_IO14 IOMUX_PADCFG(0x443c01a8, 0x5, 0x00000000, 0x00000000, 0x443c0358) +#define IOMUXC_PAD_WDOG_ANY_WDOG1_WDOG_ANY IOMUX_PADCFG(0x443c01ac, 0x0, 0x00000000, 0x00000000, 0x443c035c) +#define IOMUXC_PAD_WDOG_ANY_GPIO1_IO15 IOMUX_PADCFG(0x443c01ac, 0x5, 0x00000000, 0x00000000, 0x443c035c) + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_PINMUX_H */ diff --git a/arch/arm64/src/imx9/hardware/imx93/imx93_pll.h b/arch/arm64/src/imx9/hardware/imx93/imx93_pll.h new file mode 100644 index 0000000000000..fb0a5af737360 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx93/imx93_pll.h @@ -0,0 +1,195 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx93/imx93_pll.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_PLL_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_PLL_H + +/* All registers besides STATUS have SET, CLR, TGL and VAL shadow registers */ + +#define PLL_REG_VAL_OFFSET (0x00) +#define PLL_REG_SET_OFFSET (0x04) +#define PLL_REG_CLR_OFFSET (0x08) +#define PLL_REG_TGL_OFFSET (0x0c) + +/* User can access the individual registers via these macros */ + +#define PLL_VAL(n) ((n) + PLL_REG_VAL_OFFSET) /* Same as the register itself */ +#define PLL_SET(n) ((n) + PLL_REG_SET_OFFSET) +#define PLL_CLR(n) ((n) + PLL_REG_CLR_OFFSET) +#define PLL_TGL(n) ((n) + PLL_REG_TGL_OFFSET) + +/* Common offsets for all PLL registers, existence depends on the register + * itself + */ + +#define PLL_CTRL_OFFSET (0x00) /* PLL Control */ +#define PLL_SPREAD_SPECTRUM_OFFSET (0x30) /* Spread Spectrum */ +#define PLL_NUMERATOR_OFFSET (0x40) /* Numerator */ +#define PLL_DENOMINATOR_OFFSET (0x50) /* Denominator */ +#define PLL_DIV_OFFSET (0x60) /* PLL Dividers */ +#define PLL_DFS_CTRL_0_OFFSET (0x70) /* DFS Control */ +#define PLL_DFS_DIV_0_OFFSET (0x80) /* DFS Division_0 */ +#define PLL_DFS_CTRL_1_OFFSET (0x90) /* DFS Control */ +#define PLL_DFS_DIV_1_OFFSET (0xa0) /* DFS Division_1 */ +#define PLL_DFS_CTRL_2_OFFSET (0xb0) /* DFS Control */ +#define PLL_DFS_DIV_2_OFFSET (0xc0) /* DFS Division_2 */ +#define PLL_PLL_STATUS_OFFSET (0xf0) /* PLL Status */ +#define PLL_DFS_STATUS_OFFSET (0xf4) /* DFS Status */ + +/* Register addresses */ + +#define PLL_CTRL(n) ((n) + PLL_CTRL_OFFSET) +#define PLL_SPREAD_SPECTRUM(n) ((n) + PLL_SPREAD_SPECTRUM_OFFSET) +#define PLL_NUMERATOR(n) ((n) + PLL_NUMERATOR_OFFSET) +#define PLL_DENOMINATOR(n) ((n) + PLL_DENOMINATOR_OFFSET) +#define PLL_DIV(n) ((n) + PLL_DIV_OFFSET) +#define PLL_DFS_CTRL_0(n) ((n) + PLL_DFS_CTRL_0_OFFSET) +#define PLL_DFS_DIV_0(n) ((n) + PLL_DFS_DIV_0_OFFSET) +#define PLL_DFS_CTRL_1(n) ((n) + PLL_DFS_CTRL_1_OFFSET) +#define PLL_DFS_DIV_1(n) ((n) + PLL_DFS_DIV_1_OFFSET) +#define PLL_DFS_CTRL_2(n) ((n) + PLL_DFS_CTRL_2_OFFSET) +#define PLL_DFS_DIV_2(n) ((n) + PLL_DFS_DIV_2_OFFSET) +#define PLL_PLL_STATUS(n) ((n) + PLL_PLL_STATUS_OFFSET) +#define PLL_DFS_STATUS(n) ((n) + PLL_DFS_STATUS_OFFSET) + +/* SYSPLL registers */ + +#define SYSPLL_CTRL (IMX9_SYSPLL_BASE + PLL_CTRL_OFFSET) +#define SYSPLL_SPREAD_SPECTRUM (IMX9_SYSPLL_BASE + PLL_SPREAD_SPECTRUM_OFFSET) +#define SYSPLL_NUMERATOR (IMX9_SYSPLL_BASE + PLL_NUMERATOR_OFFSET) +#define SYSPLL_DENOMINATOR (IMX9_SYSPLL_BASE + PLL_DENOMINATOR_OFFSET) +#define SYSPLL_DIV (IMX9_SYSPLL_BASE + PLL_DIV_OFFSET) +#define SYSPLL_DFS_CTRL_0 (IMX9_SYSPLL_BASE + PLL_DFS_CTRL_0_OFFSET) +#define SYSPLL_DFS_DIV_0 (IMX9_SYSPLL_BASE + PLL_DFS_DIV_0_OFFSET) +#define SYSPLL_DFS_CTRL_1 (IMX9_SYSPLL_BASE + PLL_DFS_CTRL_1_OFFSET) +#define SYSPLL_DFS_DIV_1 (IMX9_SYSPLL_BASE + PLL_DFS_DIV_1_OFFSET) +#define SYSPLL_DFS_CTRL_2 (IMX9_SYSPLL_BASE + PLL_DFS_CTRL_2_OFFSET) +#define SYSPLL_DFS_DIV_2 (IMX9_SYSPLL_BASE + PLL_DFS_DIV_2_OFFSET) +#define SYSPLL_PLL_STATUS (IMX9_SYSPLL_BASE + PLL_PLL_STATUS_OFFSET) +#define SYSPLL_DFS_STATUS (IMX9_SYSPLL_BASE + PLL_DFS_STATUS_OFFSET) + +/* ARMPLL registers */ + +#define ARMPLL_CTRL (IMX9_ARMPLL_BASE + PLL_CTRL_OFFSET) +#define ARMPLL_DIV (IMX9_ARMPLL_BASE + PLL_DIV_OFFSET) +#define ARMPLL_PLL_STATUS (IMX9_ARMPLL_BASE + PLL_PLL_STATUS_OFFSET) + +/* AUDIOPLL registers */ + +#define AUDIOPLL_CTRL (IMX9_AUDIOPLL_BASE + PLL_CTRL_OFFSET) +#define AUDIOPLL_SPREAD_SPECTRUM (IMX9_AUDIOPLL_BASE + PLL_SPREAD_SPECTRUM_OFFSET) +#define AUDIOPLL_NUMERATOR (IMX9_AUDIOPLL_BASE + PLL_NUMERATOR_OFFSET) +#define AUDIOPLL_DENOMINATOR (IMX9_AUDIOPLL_BASE + PLL_DENOMINATOR_OFFSET) +#define AUDIOPLL_DIV (IMX9_AUDIOPLL_BASE + PLL_DIV_OFFSET) +#define AUDIOPLL_PLL_STATUS (IMX9_AUDIOPLL_BASE + PLL_PLL_STATUS_OFFSET) + +/* DRAMPLL registers */ + +#define DRAMPLL_CTRL (IMX9_AUDIOPLL_BASE + PLL_CTRL_OFFSET) +#define DRAMPLL_SPREAD_SPECTRUM (IMX9_AUDIOPLL_BASE + PLL_SPREAD_SPECTRUM_OFFSET) +#define DRAMPLL_NUMERATOR (IMX9_AUDIOPLL_BASE + PLL_NUMERATOR_OFFSET) +#define DRAMPLL_DENOMINATOR (IMX9_AUDIOPLL_BASE + PLL_DENOMINATOR_OFFSET) +#define DRAMPLL_DIV (IMX9_AUDIOPLL_BASE + PLL_DIV_OFFSET) +#define DRAMPLL_PLL_STATUS (IMX9_AUDIOPLL_BASE + PLL_PLL_STATUS_OFFSET) + +/* VIDEOPLL registers */ + +#define VIDEOPLL_CTRL (IMX9_VIDEOPLL_BASE + PLL_CTRL_OFFSET) +#define VIDEOPLL_SPREAD_SPECTRUM (IMX9_VIDEOPLL_BASE + PLL_SPREAD_SPECTRUM_OFFSET) +#define VIDEOPLL_NUMERATOR (IMX9_VIDEOPLL_BASE + PLL_NUMERATOR_OFFSET) +#define VIDEOPLL_DENOMINATOR (IMX9_VIDEOPLL_BASE + PLL_DENOMINATOR_OFFSET) +#define VIDEOPLL_DIV (IMX9_VIDEOPLL_BASE + PLL_DIV_OFFSET) +#define VIDEOPLL_PLL_STATUS (IMX9_VIDEOPLL_BASE + PLL_PLL_STATUS_OFFSET) + +/* PLL Control (CTRL) */ + +#define PLL_CTRL_POWERUP (1 << 0) /* Bit 0: Power up PLL */ +#define PLL_CTRL_CLKMUX_EN (1 << 1) /* Bit 1: Enable CLKMUX output */ +#define PLL_CTRL_CLKMUX_BYPASS (1 << 2) /* Bit 2: Enable CLKMUX bypass */ +#define PLL_CTRL_SPREADCTL (1 << 8) /* Bit 8: Modulation Type Select */ +#define PLL_CTRL_HW_CTRL_SEL (1 << 16) /* Bit 16: Hardware Control Select */ +#define PLL_CTRL_LOCK_BYPASS (1 << 31) /* Bit 31: Lock bypass */ + +/* Spread Spectrum (SPREAD_SPECTRUM) */ + +#define PLL_SPREAD_SPECTRUM_STEP_SHIFT (0) /* Bits 14-0: Set spread spectrum step */ +#define PLL_SPREAD_SPECTRUM_STEP_MASK (0x7fff << PLL_SPREAD_SPECTRUM_STEP_SHIFT) +#define PLL_SPREAD_SPECTRUM_STEP(n) (((n) << PLL_SPREAD_SPECTRUM_STEP_SHIFT) & PLL_SPREAD_SPECTRUM_STEP_MASK) +#define PLL_SPREAD_SPECTRUM_ENABLE (1 << 15) /* Bit 15: Enable spread spectrum */ +#define PLL_SPREAD_SPECTRUM_STOP_SHIFT (16) /* Bits 16-31: Set spread spectrum stop */ +#define PLL_SPREAD_SPECTRUM_STOP_MASK (0xffff << PLL_SPREAD_SPECTRUM_STOP_SHIFT) +#define PLL_SPREAD_SPECTRUM_STOP(n) (((n) << PLL_SPREAD_SPECTRUM_STOP_SHIFT) & PLL_SPREAD_SPECTRUM_STOP_MASK) + +/* Numerator (NUMERATOR) */ + +#define PLL_NUMERATOR_MFN_SHIFT (2) /* Bits 2-31: Numerator MFN value */ +#define PLL_NUMERATOR_MFN_MASK (0x3fffffff << PLL_NUMERATOR_MFN_SHIFT) +#define PLL_NUMERATOR_MFN(n) (((n) << PLL_NUMERATOR_MFN_SHIFT) & PLL_NUMERATOR_MFN_MASK) + +/* Denominator (DENOMINATOR) */ + +#define PLL_DENOMINATOR_MFD_SHIFT (0) /* Bits 0-29: Denominator MFD value */ +#define PLL_DENOMINATOR_MFD_MASK (0x3fffffff << PLL_DENOMINATOR_MFD_SHIFT) +#define PLL_DENOMINATOR_MFD(n) (((n) << PLL_DENOMINATOR_MFD_SHIFT) & PLL_DENOMINATOR_MFD_MASK) + +/* PLL Dividers (DIV) */ + +#define PLL_DIV_ODIV_SHIFT (0) /* Bits 0-7: Output Frequency Divider for Clock Output */ +#define PLL_DIV_ODIV_MASK (0xff << PLL_DIV_ODIV_SHIFT) +#define PLL_DIV_ODIV(n) (((n) << PLL_DIV_ODIV_SHIFT) & PLL_DIV_ODIV_MASK) +#define PLL_DIV_RDIV_SHIFT (13) /* Bits 13-15: Input Clock Predivider */ +#define PLL_DIV_RDIV_MASK (0x7 << PLL_DIV_RDIV_SHIFT) +#define PLL_DIV_RDIV(n) (((n) << PLL_DIV_RDIV_SHIFT) & PLL_DIV_RDIV_MASK) +#define PLL_DIV_MFI_SHIFT (16) /* Bits 16-24: Integer Portion of Loop Divider */ +#define PLL_DIV_MFI_MASK (0x1ff << PLL_DIV_MFI_SHIFT) +#define PLL_DIV_MFI(n) (((n) << PLL_DIV_MFI_SHIFT) & PLL_DIV_MFI_MASK) + +/* DFS Control (DFS_CTRL_0 - DFS_CTRL_2) */ + +#define PLL_DFS_HW_CTRL_SEL (1 << 16) /* Bit 16: Hardware Control Select */ +#define PLL_DFS_BYPASS_EN (1 << 23) /* Bit 23: Bypass Enable */ +#define PLL_DFS_CLKOUT_DIVBY2_EN (1 << 29) /* Bit 29: DFS Clock Output Divide by 2 Enable */ +#define PLL_DFS_CLKOUT_EN (1 << 30) /* Bit 30: DFS Clock Output Enable */ +#define PLL_DFS_ENABLE (1 << 31) /* Bit 31: DFS Block Enable */ + +/* DFS Division_a (DFS_DIV_0 - DFS_DIV_2) */ + +#define PLL_DFS_MFN_SHIFT (0) /* Bits 0-2: MFN */ +#define PLL_DFS_MFN_MASK (0x7 << PLL_DFS_MFN_SHIFT) +#define PLL_DFS_MFN(n) (((n) << PLL_DFS_MFN_SHIFT) & PLL_DFS_MFN_MASK) +#define PLL_DFS_MFI_SHIFT (8) /* Bits 8-15: MFI */ +#define PLL_DFS_MFI_MASK (0xff << PLL_DFS_MFI_SHIFT) +#define PLL_DFS_MFI(n) (((n) << PLL_DFS_MFI_SHIFT) & PLL_DFS_MFI_MASK) + +/* PLL Dividers (DIV) */ + +#define PLL_PLL_STATUS_PLL_LOCK (1 << 0) /* Bit 0: PLL is locked */ +#define PLL_PLL_STATUS_PLL_LOL (1 << 1) /* Bit 1: PLL lock is lost */ +#define PLL_PLL_STATUS_ANA_MFN_SHIFT (2) +#define PLL_PLL_STATUS_ANA_MFN_MASK (0x3fffffff << PLL_PLL_STATUS_ANA_MFN_SHIFT) +#define PLL_PLL_STATUS_ANA_MFN(n) (((n) << PLL_PLL_STATUS_ANA_MFN_SHIFT) & PLL_PLL_STATUS_ANA_MFN_MASK) + +/* DFS Status (DFS_STATUS) */ + +#define PLL_DFS_STATUS_DFS_OK_SHIFT (0) /* Bits 0-2: DFS OK status */ +#define PLL_DFS_STATUS_DFS_OK_MASK (0x7 << PLL_DFS_STATUS_DFS_OK_SHIFT) +#define PLL_DFS_STATUS_DFS_OK(n) (((n) << PLL_DFS_STATUS_DFS_OK_SHIFT) & PLL_DFS_STATUS_DFS_OK_MASK) + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_PLL_H_*/ diff --git a/arch/arm64/src/imx9/hardware/imx9_ccm.h b/arch/arm64/src/imx9/hardware/imx9_ccm.h new file mode 100644 index 0000000000000..f4a68a0a31514 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_ccm.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_ccm.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_CCM_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_CCM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/imx9_memorymap.h" + +#if defined(CONFIG_ARCH_CHIP_IMX93) +# include "hardware/imx93/imx93_ccm.h" +# include "hardware/imx93/imx93_pll.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_CCM_H_ */ diff --git a/arch/arm64/src/imx9/hardware/imx9_dmamux.h b/arch/arm64/src/imx9/hardware/imx9_dmamux.h new file mode 100644 index 0000000000000..c9a7e6bbc9331 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_dmamux.h @@ -0,0 +1,36 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_dmamux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_DMAMUX_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_DMAMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX93) +# include "hardware/imx93/imx93_dmamux.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_DMAMUX_H */ diff --git a/arch/arm64/src/imx9/hardware/imx9_edma.h b/arch/arm64/src/imx9/hardware/imx9_edma.h new file mode 100644 index 0000000000000..d08610e7b5e1f --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_edma.h @@ -0,0 +1,36 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_edma.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_EDMA_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_EDMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX93) +# include "hardware/imx93/imx93_edma.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_EDMA_H */ diff --git a/arch/arm64/src/imx9/hardware/imx9_enet.h b/arch/arm64/src/imx9/hardware/imx9_enet.h new file mode 100644 index 0000000000000..67a7493722d5b --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_enet.h @@ -0,0 +1,646 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_enet.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_ENET_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_ENET_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define IMX9_ENET_EIR_OFFSET 0x0004 /* Interrupt Event Register */ +#define IMX9_ENET_EIMR_OFFSET 0x0008 /* Interrupt Mask Register */ +#define IMX9_ENET_RDAR_OFFSET 0x0010 /* Receive Descriptor Active Register */ +#define IMX9_ENET_TDAR_OFFSET 0x0014 /* Transmit Descriptor Active Register */ +#define IMX9_ENET_ECR_OFFSET 0x0024 /* Ethernet Control Register */ +#define IMX9_ENET_MMFR_OFFSET 0x0040 /* MII Management Frame Register */ +#define IMX9_ENET_MSCR_OFFSET 0x0044 /* MII Speed Control Register */ +#define IMX9_ENET_MIBC_OFFSET 0x0064 /* MIB Control Register */ +#define IMX9_ENET_RCR_OFFSET 0x0084 /* Receive Control Register */ +#define IMX9_ENET_TCR_OFFSET 0x00c4 /* Transmit Control Register */ +#define IMX9_ENET_PALR_OFFSET 0x00e4 /* Physical Address Lower Register */ +#define IMX9_ENET_PAUR_OFFSET 0x00e8 /* Physical Address Upper Register */ +#define IMX9_ENET_OPD_OFFSET 0x00ec /* Opcode/Pause Duration Register */ +#define IMX9_ENET_TXIC_OFFSET 0x00f0 /* Transmit Interrupt Coalescing Register */ +#define IMX9_ENET_RXIC_OFFSET 0x0100 /* Receive Interrupt Coalescing Register */ +#define IMX9_ENET_IAUR_OFFSET 0x0118 /* Descriptor Individual Upper Address Register */ +#define IMX9_ENET_IALR_OFFSET 0x011c /* Descriptor Individual Lower Address Register */ +#define IMX9_ENET_GAUR_OFFSET 0x0120 /* Descriptor Group Upper Address Register */ +#define IMX9_ENET_GALR_OFFSET 0x0124 /* Descriptor Group Lower Address Register */ +#define IMX9_ENET_TFWR_OFFSET 0x0144 /* Transmit FIFO Watermark Register */ +#define IMX9_ENET_RDSR1_OFFSET 0x0160 /* Receive Descriptor Ring 1 Start Register */ +#define IMX9_ENET_TDSR1_OFFSET 0x0164 /* Transmit Buffer Descriptor Ring 1 Start Register */ +#define IMX9_ENET_MRBR1_OFFSET 0x0168 /* Maximum Receive Buffer Size Register - Ring 1 */ +#define IMX9_ENET_RDSR2_OFFSET 0x0170 /* Receive Descriptor Ring 2 Start Register */ +#define IMX9_ENET_TDSR2_OFFSET 0x0174 /* Transmit Buffer Descriptor Ring 2 Start Register */ +#define IMX9_ENET_MRBR2_OFFSET 0x0178 /* Maximum Receive Buffer Size Register - Ring 2 */ +#define IMX9_ENET_RDSR_OFFSET 0x0180 /* Receive Descriptor Ring Start Register */ +#define IMX9_ENET_TDSR_OFFSET 0x0184 /* Transmit Buffer Descriptor Ring Start Register */ +#define IMX9_ENET_MRBR_OFFSET 0x0188 /* Maximum Receive Buffer Size Register */ +#define IMX9_ENET_RSFL_OFFSET 0x0190 /* Receive FIFO Section Full Threshold */ +#define IMX9_ENET_RSEM_OFFSET 0x0194 /* Receive FIFO Section Empty Threshold */ +#define IMX9_ENET_RAEM_OFFSET 0x0198 /* Receive FIFO Almost Empty Threshold */ +#define IMX9_ENET_RAFL_OFFSET 0x019c /* Receive FIFO Almost Full Threshold */ +#define IMX9_ENET_TSEM_OFFSET 0x01a0 /* Transmit FIFO Section Empty Threshold */ +#define IMX9_ENET_TAEM_OFFSET 0x01a4 /* Transmit FIFO Almost Empty Threshold */ +#define IMX9_ENET_TAFL_OFFSET 0x01a8 /* Transmit FIFO Almost Full Threshold */ +#define IMX9_ENET_TIPG_OFFSET 0x01ac /* Transmit Inter-Packet Gap */ +#define IMX9_ENET_FTRL_OFFSET 0x01b0 /* Frame Truncation Length */ +#define IMX9_ENET_TACC_OFFSET 0x01c0 /* Transmit Accelerator Function Configuration */ +#define IMX9_ENET_RACC_OFFSET 0x01c4 /* Receive Accelerator Function Configuration */ + +#define IMX9_ENET_ATCR_OFFSET 0x0400 /* Timer Control Register */ +#define IMX9_ENET_ATVR_OFFSET 0x0404 /* Timer Value Register */ +#define IMX9_ENET_ATOFF_OFFSET 0x0408 /* Timer Offset Register */ +#define IMX9_ENET_ATPER_OFFSET 0x040c /* Timer Period Register */ +#define IMX9_ENET_ATCOR_OFFSET 0x0410 /* Timer Correction Register */ +#define IMX9_ENET_ATINC_OFFSET 0x0414 /* Time-Stamping Clock Period Register */ +#define IMX9_ENET_ATSTMP_OFFSET 0x0418 /* Timestamp of Last Transmitted Frame */ + +#define IMX9_ENET_TGSR_OFFSET 0x0604 /* Timer Global Status Register */ +#define IMX9_ENET_TCSR0_OFFSET 0x0608 /* Timer Control Status Register */ +#define IMX9_ENET_TCCR0_OFFSET 0x060c /* Timer Compare Capture Register */ +#define IMX9_ENET_TCSR1_OFFSET 0x0610 /* Timer Control Status Register */ +#define IMX9_ENET_TCCR1_OFFSET 0x0614 /* Timer Compare Capture Register */ +#define IMX9_ENET_TCSR2_OFFSET 0x0618 /* Timer Control Status Register */ +#define IMX9_ENET_TCCR2_OFFSET 0x061c /* Timer Compare Capture Register */ +#define IMX9_ENET_TCSR3_OFFSET 0x0620 /* Timer Control Status Register */ +#define IMX9_ENET_TCCR3_OFFSET 0x0624 /* Timer Compare Capture Register */ + +/* Register Addresses *******************************************************/ + +#define IMX9_ENET_EIR (IMX9_ENET_BASE+IMX9_ENET_EIR_OFFSET) +#define IMX9_ENET_EIMR (IMX9_ENET_BASE+IMX9_ENET_EIMR_OFFSET) +#define IMX9_ENET_RDAR (IMX9_ENET_BASE+IMX9_ENET_RDAR_OFFSET) +#define IMX9_ENET_TDAR (IMX9_ENET_BASE+IMX9_ENET_TDAR_OFFSET) +#define IMX9_ENET_ECR (IMX9_ENET_BASE+IMX9_ENET_ECR_OFFSET) +#define IMX9_ENET_MMFR (IMX9_ENET_BASE+IMX9_ENET_MMFR_OFFSET) +#define IMX9_ENET_MSCR (IMX9_ENET_BASE+IMX9_ENET_MSCR_OFFSET) +#define IMX9_ENET_MIBC (IMX9_ENET_BASE+IMX9_ENET_MIBC_OFFSET) +#define IMX9_ENET_RCR (IMX9_ENET_BASE+IMX9_ENET_RCR_OFFSET) +#define IMX9_ENET_TCR (IMX9_ENET_BASE+IMX9_ENET_TCR_OFFSET) +#define IMX9_ENET_PALR (IMX9_ENET_BASE+IMX9_ENET_PALR_OFFSET) +#define IMX9_ENET_PAUR (IMX9_ENET_BASE+IMX9_ENET_PAUR_OFFSET) +#define IMX9_ENET_OPD (IMX9_ENET_BASE+IMX9_ENET_OPD_OFFSET) +#define IMX9_ENET_IAUR (IMX9_ENET_BASE+IMX9_ENET_IAUR_OFFSET) +#define IMX9_ENET_IALR (IMX9_ENET_BASE+IMX9_ENET_IALR_OFFSET) +#define IMX9_ENET_GAUR (IMX9_ENET_BASE+IMX9_ENET_GAUR_OFFSET) +#define IMX9_ENET_GALR (IMX9_ENET_BASE+IMX9_ENET_GALR_OFFSET) +#define IMX9_ENET_TFWR (IMX9_ENET_BASE+IMX9_ENET_TFWR_OFFSET) +#define IMX9_ENET_RDSR (IMX9_ENET_BASE+IMX9_ENET_RDSR_OFFSET) +#define IMX9_ENET_TDSR (IMX9_ENET_BASE+IMX9_ENET_TDSR_OFFSET) +#define IMX9_ENET_MRBR (IMX9_ENET_BASE+IMX9_ENET_MRBR_OFFSET) +#define IMX9_ENET_RSFL (IMX9_ENET_BASE+IMX9_ENET_RSFL_OFFSET) +#define IMX9_ENET_RSEM (IMX9_ENET_BASE+IMX9_ENET_RSEM_OFFSET) +#define IMX9_ENET_RAEM (IMX9_ENET_BASE+IMX9_ENET_RAEM_OFFSET) +#define IMX9_ENET_RAFL (IMX9_ENET_BASE+IMX9_ENET_RAFL_OFFSET) +#define IMX9_ENET_TSEM (IMX9_ENET_BASE+IMX9_ENET_TSEM_OFFSET) +#define IMX9_ENET_TAEM (IMX9_ENET_BASE+IMX9_ENET_TAEM_OFFSET) +#define IMX9_ENET_TAFL (IMX9_ENET_BASE+IMX9_ENET_TAFL_OFFSET) +#define IMX9_ENET_TIPG (IMX9_ENET_BASE+IMX9_ENET_TIPG_OFFSET) +#define IMX9_ENET_FTRL (IMX9_ENET_BASE+IMX9_ENET_FTRL_OFFSET) +#define IMX9_ENET_TACC (IMX9_ENET_BASE+IMX9_ENET_TACC_OFFSET) +#define IMX9_ENET_RACC (IMX9_ENET_BASE+IMX9_ENET_RACC_OFFSET) + +#define IMX9_ENET_ATCR (IMX9_ENET_BASE+IMX9_ENET_ATCR_OFFSET) +#define IMX9_ENET_ATVR (IMX9_ENET_BASE+IMX9_ENET_ATVR_OFFSET) +#define IMX9_ENET_ATOFF (IMX9_ENET_BASE+IMX9_ENET_ATOFF_OFFSET) +#define IMX9_ENET_ATPER (IMX9_ENET_BASE+IMX9_ENET_ATPER_OFFSET) +#define IMX9_ENET_ATCOR (IMX9_ENET_BASE+IMX9_ENET_ATCOR_OFFSET) +#define IMX9_ENET_ATINC (IMX9_ENET_BASE+IMX9_ENET_ATINC_OFFSET) +#define IMX9_ENET_ATSTMP (IMX9_ENET_BASE+IMX9_ENET_ATSTMP_OFFSET) + +#define IMX9_ENET_TGSR (IMX9_ENET_BASE+IMX9_ENET_TGSR_OFFSET) +#define IMX9_ENET_TCSR0 (IMX9_ENET_BASE+IMX9_ENET_TCSR0_OFFSET) +#define IMX9_ENET_TCCR0 (IMX9_ENET_BASE+IMX9_ENET_TCCR0_OFFSET) +#define IMX9_ENET_TCSR1 (IMX9_ENET_BASE+IMX9_ENET_TCSR1_OFFSET) +#define IMX9_ENET_TCCR1 (IMX9_ENET_BASE+IMX9_ENET_TCCR1_OFFSET) +#define IMX9_ENET_TCSR2 (IMX9_ENET_BASE+IMX9_ENET_TCSR2_OFFSET) +#define IMX9_ENET_TCCR2 (IMX9_ENET_BASE+IMX9_ENET_TCCR2_OFFSET) +#define IMX9_ENET_TCSR3 (IMX9_ENET_BASE+IMX9_ENET_TCSR3_OFFSET) +#define IMX9_ENET_TCCR3 (IMX9_ENET_BASE+IMX9_ENET_TCCR3_OFFSET) + +/* Register Bit Definitions *************************************************/ + +/* Interrupt Event Register, Interrupt Mask Register */ + +#define ENET_RXB1 (1 << 0) /* Receive buffer interrupt, class 1 */ +#define ENET_RXF1 (1 << 1) /* Receive frame interrupt, class 1 */ +#define ENET_TXB1 (1 << 2) /* Transmit buffer interrupt, class 1 */ +#define ENET_TXF1 (1 << 3) /* Transmit frame interrupt, class 1 */ +#define ENET_RXB2 (1 << 4) /* Receive buffer interrupt, class 2 */ +#define ENET_RXF2 (1 << 5) /* Receive frame interrupt, class 2 */ +#define ENET_TXB2 (1 << 6) /* Transmit buffer interrupt, class 2 */ +#define ENET_TXF2 (1 << 7) /* Transmit frame interrupt, class 2 */ +#define ENET_RXFLUSH_0 (1 << 12) /* RX DMA Ring 0 flush indication */ +#define ENET_RXFLUSH_1 (1 << 13) /* RX DMA Ring 1 flush indication */ +#define ENET_RXFLUSH_2 (1 << 14) /* RX DMA Ring 2 flush indication */ +#define ENET_INT_TS_TIMER (1 << 15) /* Bit 15: Timestamp timer */ +#define ENET_INT_TS_AVAIL (1 << 16) /* Bit 16: Transmit timestamp available */ +#define ENET_INT_WAKEUP (1 << 17) /* Bit 17: Node wake-up request indication */ +#define ENET_INT_PLR (1 << 18) /* Bit 18: Payload receive error */ +#define ENET_INT_UN (1 << 19) /* Bit 19: Transmit FIFO underrun */ +#define ENET_INT_RL (1 << 20) /* Bit 20: Collision Retry Limit */ +#define ENET_INT_LC (1 << 21) /* Bit 21: Late Collision */ +#define ENET_INT_EBERR (1 << 22) /* Bit 22: Ethernet Bus Error */ +#define ENET_INT_MII (1 << 23) /* Bit 23: MII Interrupt */ +#define ENET_INT_RXB (1 << 24) /* Bit 24: Receive Buffer Interrupt */ +#define ENET_INT_RXF (1 << 25) /* Bit 25: Receive Frame Interrupt */ +#define ENET_INT_TXB (1 << 26) /* Bit 26: Transmit Buffer Interrupt */ +#define ENET_INT_TXF (1 << 27) /* Bit 27: Transmit Frame Interrupt */ +#define ENET_INT_GRA (1 << 28) /* Bit 28: Graceful Stop Complete */ +#define ENET_INT_BABT (1 << 29) /* Bit 29: Babbling Transmit Error */ +#define ENET_INT_BABR (1 << 30) /* Bit 30: Babbling Receive Error */ + /* Bit 31: Reserved */ + +/* Receive Descriptor Active Register */ + + /* Bits 0-23: Reserved */ +#define ENET_RDAR (1 << 24) /* Bit 24: Receive descriptor active */ + /* Bits 25-31: Reserved */ + +/* Transmit Descriptor Active Register */ + + /* Bits 0-23: Reserved */ +#define ENET_TDAR (1 << 24) /* Bit 24: Transmit descriptor active */ + /* Bits 25-31: Reserved */ + +/* Ethernet Control Register */ + +#define ENET_ECR_RESET (1 << 0) /* Bit 0: Ethernet MAC reset */ +#define ENET_ECR_ETHEREN (1 << 1) /* Bit 1: Ethernet enable */ +#define ENET_ECR_MAGICEN (1 << 2) /* Bit 2: Magic packet detection enable */ +#define ENET_ECR_SLEEP (1 << 3) /* Bit 3: Sleep mode enable */ +#define ENET_ECR_EN1588 (1 << 4) /* Bit 4: EN1588 enable */ +#define ENET_ECR_SPEED (1 << 5) /* Bit 5: 10/100-Mbit/s or 1000-Mbit/s mode */ +#define ENET_ECR_DBGEN (1 << 6) /* Bit 6: Debug enable */ + /* Bit 7: Reserved, always write 0 */ +#define ENET_ECR_DBSWP (1 << 8) /* Bit 8: Swap bytes; always write 1 after reset */ +#define ENET_ECR_SVLANEN (1 << 9) /* Bit 9: S-VLAN enable */ +#define ENET_ECR_VLANUSE2ND (1 << 10) /* Bit 10: VLAN use second tag */ +#define ENET_ECR_SVLANDBL (1 << 11) /* Bit 11: S-VLAN double tag */ +#define ENET_ECR_TXC_DLY (1 << 16) /* Bit 16: Transmit clock delay */ +#define ENET_ECR_RXC_DLY (1 << 17) /* Bit 17: Receive clock delay */ + /* Bits 12-15: Reserved, always write 0 */ +#define ENET_ECR_RESV_MASK (0x3ffff << 18) /* Reserved, always write 0x1c00 */ + +/* MII Management Frame Register */ + +#define ENET_MMFR_DATA_SHIFT (0) /* Bits 0-15: Management frame data */ +#define ENET_MMFR_DATA_MASK (0xffff << ENET_MMFR_DATA_SHIFT) +#define ENET_MMFR_TA_SHIFT (16) /* Bits 16-17: Turn around */ +#define ENET_MMFR_TA_MASK (0x3 << ENET_MMFR_TA_SHIFT) +#define ENET_MMFR_RA_SHIFT (18) /* Bits 18-22: Register address */ +#define ENET_MMFR_RA_MASK (0x1f << ENET_MMFR_RA_SHIFT) +#define ENET_MMFR_PA_SHIFT (23) /* Bits 23-27: PHY address */ +#define ENET_MMFR_PA_MASK (0x1f << ENET_MMFR_PA_SHIFT) +#define ENET_MMFR_OP_SHIFT (28) /* Bits 28-29: Operation code */ +#define ENET_MMFR_OP_MASK (0x3 << ENET_MMFR_OP_SHIFT) +# define ENET_MMFR_OP_WRNOTMII (0 << ENET_MMFR_OP_SHIFT) /* Write frame, not MII compliant */ +# define ENET_MMFR_OP_WRMII (1 << ENET_MMFR_OP_SHIFT) /* Write frame, MII management frame */ +# define ENET_MMFR_OP_RDMII (2 << ENET_MMFR_OP_SHIFT) /* Read frame, MII management frame */ +# define ENET_MMFR_OP_RDNOTMII (3 << ENET_MMFR_OP_SHIFT) /* Read frame, not MII compliant */ + +#define ENET_MMFR_ST_SHIFT (30) /* Bits 30-31: Start of frame delimiter */ +#define ENET_MMFR_ST_MASK (0x3 << ENET_MMFR_ST_SHIFT) + +/* MII Speed Control Register */ + + /* Bit 0: Reserved */ +#define ENET_MSCR_MII_SPEED_SHIFT (1) /* Bits 1-6: MII speed */ +#define ENET_MSCR_MII_SPEED_MASK (0x3f << ENET_MSCR_MII_SPEED_SHIFT) +# define ENET_MSCR_MII_SPEED_25MHz (0x4) /* Optimum value for IPS bus 25 MHz clock */ +# define ENET_MSCR_MII_SPEED_33MHz (0x6) /* Optimum value for IPS bus 33 MHz clock */ +# define ENET_MSCR_MII_SPEED_40MHz (0x7) /* Optimum value for IPS bus 40 MHz clock */ +# define ENET_MSCR_MII_SPEED_50MHz (0x9) /* Optimum value for IPS bus 50 MHz clock */ +# define ENET_MSCR_MII_SPEED_66MHz (0xd) /* Optimum value for IPS bus 60 MHz clock */ +#define ENET_MSCR_DIS_PRE (1 << 7) /* Bit 7: Disable preamble */ +#define ENET_MSCR_HOLDTIME_SHIFT (8) /* Bits 8-10: Holdtime on MDIO output */ +#define ENET_MSCR_HOLDTIME_MASK (0x7 << ENET_MSCR_HOLDTIME_SHIFT) +# define ENET_MSCR_HOLDTIME_1CYCLE (0 << ENET_MSCR_HOLDTIME_SHIFT) /* 1 internal module clock cycle */ +# define ENET_MSCR_HOLDTIME_2CYCLES (1 << ENET_MSCR_HOLDTIME_SHIFT) /* 2 internal module clock cycles */ +# define ENET_MSCR_HOLDTIME_3CYCLES (2 << ENET_MSCR_HOLDTIME_SHIFT) /* 3 internal module clock cycles */ +# define ENET_MSCR_HOLDTIME_8CYCLES (7 << ENET_MSCR_HOLDTIME_SHIFT) /* 8 internal module clock cycles */ + +/* MIB Control Register */ + + /* Bits 0-28: Reserved */ +#define ENET_MIBC_MIB_CLEAR (1 << 29) /* Bit 29: MIB clear */ +#define ENET_MIBC_MIB_IDLE (1 << 30) /* Bit 30: MIB idle */ +#define ENET_MIBC_MIB_DIS (1 << 31) /* Bit 31: Disable MIB logic */ + +/* Receive Control Register */ + +#define ENET_RCR_LOOP (1 << 0) /* Bit 0: Internal loopback */ +#define ENET_RCR_DRT (1 << 1) /* Bit 1: Disable receive on transmit */ +#define ENET_RCR_MII_MODE (1 << 2) /* Bit 2: Media independent interface mode */ +#define ENET_RCR_PROM (1 << 3) /* Bit 3: Promiscuous mode */ +#define ENET_RCR_BC_REJ (1 << 4) /* Bit 4: Broadcast frame reject */ +#define ENET_RCR_FCE (1 << 5) /* Bit 5: Flow control enable */ +#define ENET_RCR_RGMII_EN (1 << 6) /* Bit 6: RGMII mode enable */ + /* Bit 7: Reserved */ +#define ENET_RCR_RMII_MODE (1 << 8) /* Bit 8: RGMII mode enable */ +#define ENET_RCR_RMII_10T (1 << 9) /* Bit 9: Enables 10-Mbps mode of the RMII */ + /* Bits 10-11: Reserved */ +#define ENET_RCR_PADEN (1 << 12) /* Bit 12: Enable frame padding remove on receive */ +#define ENET_RCR_PAUFWD (1 << 13) /* Bit 13: Terminate/forward pause frames */ +#define ENET_RCR_CRCFWD (1 << 14) /* Bit 14: Terminate/forward received CRC */ +#define ENET_RCR_CFEN (1 << 15) /* Bit 15: MAC control frame enable */ +#define ENET_RCR_MAX_FL_SHIFT (16) /* Bits 16-29: Maximum frame length */ +#define ENET_RCR_MAX_FL_MASK (0x3fff << ENET_RCR_MAX_FL_SHIFT) +#define ENET_RCR_NLC (1 << 30) /* Bit 30: Payload length check disable */ +#define ENET_RCR_GRS (1 << 31) /* Bit 31: Graceful receive stopped */ + +/* Transmit Control Register */ + +#define ENET_TCR_GTS (1 << 0) /* Bit 0: Graceful transmit stop */ + /* Bit 1: Reserved */ +#define ENET_TCR_FDEN (1 << 2) /* Bit 2: Full duplex enable */ +#define ENET_TCR_TFC_PAUSE (1 << 3) /* Bit 3: Transmit frame control pause */ +#define ENET_TCR_RFC_PAUSE (1 << 4) /* Bit 4: Receive frame control pause */ +#define ENET_TCR_ADDSEL_SHIFT (5) /* Bits 5-7: Source MAC address select on transmit */ +#define ENET_TCR_ADDSEL_MASK (0x7 << ENET_TCR_ADDSEL_SHIFT) +#define ENET_TCR_ADDSEL_PADDR12 (0 << ENET_TCR_ADDSEL_SHIFT) +#define ENET_TCR_ADDINS (1 << 8) /* Bit 8: Set MAC address on transmit */ +#define ENET_TCR_CRCFWD (1 << 9) /* Bit 9: Forward frame from application with CRC */ + /* Bits 10-31: Reserved, 10 must be written to 0 */ + +/* Physical Address Lower/Upper Register (32-bits of 48-address) */ + +/* Physical Address Upper Register */ + +#define ENET_PAUR_TYPE_SHIFT (0) /* Bits 0-15: Type field in PAUSE frame */ +#define ENET_PAUR_TYPE_MASK (0xffff << ENET_PAUR_TYPE_MASK) +#define ENET_PAUR_PADDR2_SHIFT (16) /* Bits 16-31: Bytes 4 and 5 of the 6-byte address */ +#define ENET_PAUR_PADDR2_MASK (0xffff << ENET_PAUR_PADDR2_SHIFT) + +/* Opcode/Pause Duration Register */ + +#define ENET_OPD_PAUSE_DUR_SHIFT (0) /* Bits 0-15: Pause duration */ +#define ENET_OPD_PAUSE_DUR_MASK (0xffff << ENET_OPD_PAUSE_DUR_SHIFT) +#define ENET_OPD_OPCODE_SHIFT (16) /* Bits 16-31: Opcode field in PAUSE frames */ +#define ENET_OPD_OPCODE_MASK (0xffff << ENET_OPD_OPCODE_SHIFT) + +/* Descriptor Individual Upper/Lower Address Register + * (64-bit address in two 32-bit registers) + */ + +/* Descriptor Group Upper/Lower Address Register + * (64-bit address in two 32-bit registers) + */ + +/* Transmit Interrupt Coalescing Register */ + +#define ENET_TXIC_ICTT_SHIFT (0) /* Bits 0-15: Interrupt coalescing timer threshold */ +#define ENET_TXIC_ICTT_SHIFT_MASK (0xffff << ENET_TXIC_ICTT_SHIFT) + /* Bits 16-19: Reserved */ +#define ENET_TXIC_ICFT_SHIFT (20) /* Bits 0-15: Interrupt coalescing timer threshold */ +#define ENET_TXIC_ICFT_SHIFT_MASK (0xff << ENET_TXIC_ICFT_SHIFT) +#define ENET_TXIC_ICTT_ICCS (1 << 30) /* Bit 30: Interrupt Coalescing Timer Clock Source Select */ +#define ENET_TXIC_ICTT_ICEN (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */ + +/* Receive Interrupt Coalescing Register */ + +#define ENET_RXIC_ICTT_SHIFT (0) /* Bits 0-15: Interrupt coalescing timer threshold */ +#define ENET_RXIC_ICTT_SHIFT_MASK (0xffff << ENET_TXIC_ICTT_SHIFT) + /* Bits 16-19: Reserved */ +#define ENET_RXIC_ICFT_SHIFT (20) /* Bits 0-15: Interrupt coalescing timer threshold */ +#define ENET_RXIC_ICFT_SHIFT_MASK (0xff << ENET_TXIC_ICFT_SHIFT) +#define ENET_RXIC_ICTT_ICCS (1 << 30) /* Bit 30: Interrupt Coalescing Timer Clock Source Select */ +#define ENET_RXIC_ICTT_ICEN (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */ + +/* Transmit FIFO Watermark Register */ + +#define ENET_TFWR_TFWR_SHIFT (0) /* Bits 0-5: Transmit FIFO write */ + /* Bits 6-7: Reserved */ +#define ENET_TFWR_TFWR_MASK (0x3f << ENET_TFWR_TFWR_SHIFT) +#define ENET_TFWR_STRFWD (1 << 8) /* Bit 8: Store and forward enable */ + /* Bits 9-31: Reserved */ + +/* Receive Descriptor Ring Start Register */ + + /* Bits 0-2: Reserved */ +#define ENET_RDSR_SHIFT (3) /* Bits 3-31: Start of the receive buffer descriptor queue */ +#define ENET_RDSR_MASK (0xfffffff8) + +/* Transmit Buffer Descriptor Ring Start Register */ + + /* Bits 0-2: Reserved */ +#define ENET_TDSR_SHIFT (3) /* Bits 3-31: Start of the transmit buffer descriptor queue */ +#define ENET_TDSR_MASK (0xfffffff8) + +/* Maximum Receive Buffer Size Register */ + + /* Bits 14-31: Reserved */ +#define ENET_MRBR_SHIFT (4) /* Bits 4-13: Receive buffer size in bytes */ +#define ENET_MRBR_MASK (0x3ff << ENET_MRBR_SHIFT) + /* Bits 0-3: Reserved */ + +/* Receive FIFO Section Full Threshold */ + + /* Bits 10-31: Reserved */ +#define ENET_RSFL_SHIFT (0) /* Bits 0-9: Value of receive FIFO section full threshold */ +#define ENET_RSFL_MASK (0x3ff << ENET_RSFL_SHIFT) + +/* Receive FIFO Section Empty Threshold */ + +#define ENET_RSEM_RX_EMPTY_SHIFT (0) /* Bits 0-9: Value of the receive FIFO section empty threshold */ +#define ENET_RSEM_RX_EMPTY_MASK (0x3ff << ENET_RSEM_RX_EMPTY_SHIFT) + /* Bits 10-15: Reserved */ +#define ENET_RSEM_SEC_EMPTY_SHIFT (16) /* Bits 16-20: RX Status FIFO Section Empty Threshold */ +#define ENET_RSEM_SEC_EMPTY_MASK (0x1f << ENET_RSEM_SEC_EMPTY_SHIFT) + +/* Receive FIFO Almost Empty Threshold */ + +#define ENET_RAEM_SHIFT (0) /* Bits 0-9: Value of the receive FIFO almost empty threshold */ +#define ENET_RAEM_MASK (0x3ff << ENET_RAEM_SHIFT) + /* Bits 10-31: Reserved */ + +/* Receive FIFO Almost Full Threshold */ + +#define ENET_RAFL_SHIFT (0) /* Bits 0-9: Value of the receive FIFO almost full threshold */ +#define ENET_RAFL_MASK (0x3ff << ENET_RAFL_SHIFT) + /* Bits 10-31: Reserved */ + +/* Transmit FIFO Section Empty Threshold */ + +#define ENET_TSEM_SHIFT (0) /* Bits 0-9: Value of the transmit FIFO section empty threshold */ +#define ENET_TSEM_MASK (0x3ff << ENET_TSEM_SHIFT) + /* Bits 10-31: Reserved */ + +/* Transmit FIFO Almost Empty Threshold */ + +#define ENET_TAEM_SHIFT (0) /* Bits 0-9: Value of the transmit FIFO section empty threshold */ +#define ENET_TAEM_MASK (0x3ff << ENET_TAEM_SHIFT) + /* Bits 10-31: Reserved */ + +/* Transmit FIFO Almost Full Threshold */ + +#define ENET_TAFL_SHIFT (0) /* Bits 0-9: Value of the transmit FIFO section empty threshold */ +#define ENET_TAFL_MASK (0x3ff << ENET_TAFL_SHIFT) + /* Bits 10-31: Reserved */ + +/* Transmit Inter-Packet Gap */ + +#define ENET_TIPG_SHIFT (0) /* Bits 0-4: Value of the transmit FIFO section empty threshold */ +#define ENET_TIPG_MASK (0x1f << ENET_TIPG_SHIFT) + /* Bits 5-31: Reserved */ + +/* Frame Truncation Length */ + +#define ENET_FTRL_SHIFT (0) /* Bits 0-13: Value of the transmit FIFO section empty threshold */ +#define ENET_FTRL_MASK (0x3fff << ENET_FTRL_SHIFT) + /* Bits 14-31: Reserved */ + +/* Transmit Accelerator Function Configuration */ + +#define ENET_TACC_SHIFT16 (1 << 0) /* Bit 0: TX FIFO shift-16 */ + /* Bits 1-2: Reserved */ +#define ENET_TACC_IPCHK (1 << 3) /* Bit 3: Enables insertion of IP header checksum */ +#define ENET_TACC_PROCHK (1 << 4) /* Bit 4: Enables insertion of protocol checksum */ + /* Bits 5-31: Reserved */ + +/* Receive Accelerator Function Configuration */ + +#define ENET_RACC_PADREM (1 << 0) /* Bit 0: Enable padding removal for short IP frames */ +#define ENET_RACC_IPDIS (1 << 1) /* Bit 1: Enable discard of frames with wrong IPv4 header checksum */ +#define ENET_RACC_PRODIS (1 << 2) /* Bit 2: Enable discard of frames with wrong protocol checksum */ + /* Bits 3-5: Reserved */ +#define ENET_RACC_LINEDIS (1 << 6) /* Bit 6: Enable discard of frames with MAC layer errors */ +#define ENET_RACC_SHIFT16 (1 << 7) /* Bit 7: RX FIFO shift-16 */ + /* Bits 8-31: Reserved */ + +/* Timer Control Register */ + +#define ENET_ATCR_EN (1 << 0) /* Bit 0: Enable timer */ + /* Bit 1: Reserved */ +#define ENET_ATCR_OFFEN (1 << 2) /* Bit 2: Enable one-shot offset event */ +#define ENET_ATCR_OFFRST (1 << 3) /* Bit 3: Reset timer on offset event */ +#define ENET_ATCR_PEREN (1 << 4) /* Bit 4: Enable periodical event */ + /* Bits 5-6: Reserved */ +#define ENET_ATCR_PINPER (1 << 7) /* Bit 7: Enables event signal output assertion on period event */ + /* Bit 8: Reserved */ +#define ENET_ATCR_RESTART (1 << 9) /* Bit 9: Reset timer */ + /* Bit 10: Reserved */ +#define ENET_ATCR_CAPTURE (1 << 11) /* Bit 11: Capture timer value */ + /* Bit 12: Reserved */ +#define ENET_ATCR_SLAVE (1 << 13) /* Bit 13: Enable timer slave mode */ + /* Bits 14-31: Reserved */ + +/* Timer Value Register (32-bit timer value) */ + +/* Timer Offset Register (32-bit offset value) */ + +/* Timer Period Register (32-bit timer period) */ + +/* Timer Correction Register */ + +#define ENET_ATCOR_MASK (0x7fffffff) /* Bits 0-3: Correction counter wrap-around value */ + /* Bit 31: Reserved */ + +/* Time-Stamping Clock Period Register */ + +#define ENET_ATINC_INC_SHIFT (0) /* Bits 0-6: Clock period of the timestamping clock (ts_clk) in nanoseconds */ +#define ENET_ATINC_INC_MASK (0x7f << ENET_ATINC_INC_SHIFT) + /* Bit 7: Reserved */ +#define ENET_ATINC_INC_CORR_SHIFT (8) /* Bits 8-14: Correction increment value */ +#define ENET_ATINC_INC_CORR_MASK (0x7f << ENET_ATINC_INC_CORR_SHIFT) + /* Bits 15-31: Reserved */ + +/* Timestamp of Last Transmitted Frame (32-bit timestamp) */ + +/* Timer Global Status Register */ + +#define ENET_TGSR_TF0 (1 << 0) /* Bit 0: Copy of Timer Flag for channel 0 */ +#define ENET_TGSR_TF1 (1 << 1) /* Bit 1: Copy of Timer Flag for channel 1 */ +#define ENET_TGSR_TF2 (1 << 2) /* Bit 2: Copy of Timer Flag for channel 2 */ +#define ENET_TGSR_TF3 (1 << 3) /* Bit 3: Copy of Timer Flag for channel 3 */ + /* Bits 4-31: Reserved */ + +/* Timer Control Status Register n */ + +#define ENET_TCSR_TDRE (1 << 0) /* Bit 0: Timer DMA Request Enable */ + /* Bit 1: Reserved */ +#define ENET_TCSR_TMODE_SHIFT (2) /* Bits 2-5: Timer Mode */ +#define ENET_TCSR_TMODE_MASK (0xf << ENET_TCSR_TMODE_SHIFT) +# define ENET_TCSR_TMODE_DISABLED (0 << ENET_TCSR_TMODE_SHIFT) /* Disabled */ +# define ENET_TCSR_TMODE_ICRISING (1 << ENET_TCSR_TMODE_SHIFT) /* Input Capture on rising edge */ +# define ENET_TCSR_TMODE_ICFALLLING (2 << ENET_TCSR_TMODE_SHIFT) /* Input Capture on falling edge */ +# define ENET_TCSR_TMODE_ICBOTH (3 << ENET_TCSR_TMODE_SHIFT) /* Input Capture on both edges */ +# define ENET_TCSR_TMODE_OCSW (4 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, S/W only */ +# define ENET_TCSR_TMODE_OCTOGGLE (5 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, toggle on compare */ +# define ENET_TCSR_TMODE_OCCLR (6 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, clear on compare */ +# define ENET_TCSR_TMODE_OCSET (7 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, set on compare */ +# define ENET_TCSR_TMODE_OCSETCLR (9 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, set on compare, clear on overflow */ +# define ENET_TCSR_TMODE_OCCLRSET (10 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, clear on compare, set on overflow */ +# define ENET_TCSR_TMODE_PCPULSEL (14 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, pulse low on compare */ +# define ENET_TCSR_TMODE_PCPULSEH (15 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, pulse high on compare */ + +#define ENET_TCSR_TIE (1 << 6) /* Bit 6: Timer interrupt enable */ +#define ENET_TCSR_TF (1 << 7) /* Bit 7: Timer Flag */ + /* Bits 8-31: Reserved */ + +/* Timer Compare Capture Register (32-bit compare value) */ + +/* Buffer Descriptors *******************************************************/ + +/* Endian-independent descriptor offsets */ + +#define DESC_STATUS1_OFFSET (0) +#define DESC_LENGTH_OFFSET (2) +#define DESC_DATAPTR_OFFSET (4) +#define DESC_LEGACY_LEN (8) + +#define DESC_STATUS2_OFFSET (8) +#define DESC_LENPROTO_OFFSET (12) +#define DESC_CHECKSUM_OFFSET (14) +#define DESC_BDU_OFFSET (16) +#define DESC_TIMESTAMP_OFFSET (20) +#define DESC_ENHANCED_LEN (32) + +/* Legacy/Common TX Buffer Descriptor Bit Definitions. */ + +#define IMX9_USE_DBSWAP + +# define TXDESC_TC (1 << 10) /* Common */ +# define TXDESC_L (1 << 11) /* Common */ +# define TXDESC_TO2 (1 << 12) /* Common */ +# define TXDESC_W (1 << 13) /* Common */ +# define TXDESC_TO1 (1 << 14) /* Common */ +# define TXDESC_R (1 << 15) /* Common */ + +/* Enhanced TX Buffer Descriptor Bit Definitions */ + +# define TXDESC_TSE (1 << 8) +# define TXDESC_OE (1 << 9) +# define TXDESC_LCE (1 << 10) +# define TXDESC_FE (1 << 11) +# define TXDESC_EE (1 << 12) +# define TXDESC_UE (1 << 13) +# define TXDESC_TXE (1 << 15) + +# define TDXESC_FTYPE_N (0 << 20) +# define TDXESC_FTYPE_A (1 << 20) +# define TDXESC_FTYPE_B (2 << 20) +# define TXDESC_UTLT (1 << 24) +# define TXDESC_IINS (1 << 27) +# define TXDESC_PINS (1 << 28) +# define TXDESC_TS (1 << 29) +# define TXDESC_INT (1 << 30) + +# define TXDESC_BDU (1 << 31) + +/* Legacy (and Common) RX Buffer Descriptor Bit Definitions */ + +# define RXDESC_TR (1 << 0) +# define RXDESC_OV (1 << 1) +# define RXDESC_CR (1 << 2) +# define RXDESC_NO (1 << 4) +# define RXDESC_LG (1 << 5) +# define RXDESC_MC (1 << 6) +# define RXDESC_BC (1 << 7) +# define RXDESC_M (1 << 8) +# define RXDESC_L (1 << 11) +# define RXDESC_R02 (1 << 12) +# define RXDESC_W (1 << 13) +# define RXDESC_R01 (1 << 14) +# define RXDESC_E (1 << 15) + +/* Enhanced (only) RX Buffer Descriptor Bit Definitions */ + +# define RXDESC_FRAG (1 << 0) +# define RXDESC_IPV6 (1 << 1) +# define RXDESC_VLAN (1 << 2) +# define RXDESC_PCR (1 << 4) +# define RXDESC_ICE (1 << 5) +# define RXDESC_INT (1 << 23) +# define RXDESC_UC (1 << 24) +# define RXDESC_CE (1 << 25) +# define RXDESC_PE (1 << 26) +# define RXDESC_ME (1 << 31) + +# define RXDESC_BDU (1 << 31) + +#define RXDESC_STATUS1_ERRORS (RXDESC_TR | RXDESC_OV | RXDESC_CR | RXDESC_NO | RXDESC_LG) +#define RXDESC_STATUS2_ERRORS (RXDESC_CE | RXDESC_PE | RXDESC_ME) + +#define TXDESC_STATUS2_ERRORS (TXDESC_TSE | TXDESC_OE | TXDESC_LCE | TXDESC_FE | TXDESC_EE | TXDESC_UE | TXDESC_TXE) + +/* From ref manual TDSR/RDSR description + * For optimal performance the pointer should be 512-bit aligned, that is, + * evenly divisible by 64. NOTE: This is also cache-line size + */ + +#define ENET_ALIGN 64 +#define ENET_ALIGN_MASK (ENET_ALIGN - 1) +#define ENET_ALIGN_UP(n) (((n) + ENET_ALIGN_MASK) & ~ENET_ALIGN_MASK) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Buffer Descriptors *******************************************************/ + +/* Little endian descriptor order, with ECR[DBSWP] = 1 */ + +struct enet_desc_s +{ + uint16_t length; /* Data length */ + uint16_t status1; /* Control and status */ + uint32_t data; /* Buffer address */ + uint32_t status2; /* Extended status */ + uint16_t checksum; /* Payload checksum */ + uint16_t lenproto; /* Header length + Protocol type */ + uint32_t bdu; /* BDU */ + uint32_t timestamp; /* Time stamp */ + uint32_t reserved1; /* unused */ + uint32_t reserved2; /* unused */ +}; + +/* This is a 64-byte descriptor pair used for TX. Two descriptors are used + * for each TX transmission to match descriptors used for a single + * transmission on a a single cache line + */ + +struct enet_txdesc_s +{ + struct enet_desc_s d1; + struct enet_desc_s d2; +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_ENET_H */ diff --git a/arch/arm64/src/imx9/hardware/imx9_flexio.h b/arch/arm64/src/imx9/hardware/imx9_flexio.h new file mode 100644 index 0000000000000..2d1c9cabe5410 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_flexio.h @@ -0,0 +1,823 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_flexio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_FLEXIO_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_FLEXIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/imx9_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IMX9_FLEXIO_VERID_OFFSET 0x0000 /* Version ID Register, offset: 0x0 */ +#define IMX9_FLEXIO_PARAM_OFFSET 0x0004 /* Parameter Register, offset: 0x4 */ +#define IMX9_FLEXIO_CTRL_OFFSET 0x0008 /* FlexIO Control Register, offset: 0x8 */ +#define IMX9_FLEXIO_PIN_OFFSET 0x000c /* Pin State Register, offset: 0xC */ +#define IMX9_FLEXIO_SHIFTSTAT_OFFSET 0x0010 /* Shifter Status Register, offset: 0x10 */ +#define IMX9_FLEXIO_SHIFTERR_OFFSET 0x0014 /* Shifter Error Register, offset: 0x14 */ +#define IMX9_FLEXIO_TIMSTAT_OFFSET 0x0018 /* Timer Status Register, offset: 0x18 */ +#define IMX9_FLEXIO_SHIFTSIEN_OFFSET 0x0020 /* Shifter Status Interrupt Enable, offset: 0x20 */ +#define IMX9_FLEXIO_SHIFTEIEN_OFFSET 0x0024 /* Shifter Error Interrupt Enable, offset: 0x24 */ +#define IMX9_FLEXIO_TIMIEN_OFFSET 0x0028 /* Timer Interrupt Enable Register, offset: 0x28 */ +#define IMX9_FLEXIO_SHIFTSDEN_OFFSET 0x0030 /* Shifter Status DMA Enable, offset: 0x30 */ +#define IMX9_FLEXIO_SHIFTSTATE_OFFSET 0x0040 /* Shifter State Register, offset: 0x40 */ +#define IMX9_FLEXIO_TRGSTAT_OFFSET 0x0048 /* Trigger Status */ +#define IMX9_FLEXIO_TRIGIEN_OFFSET 0x004c /* External Trigger Interrupt Enable */ +#define IMX9_FLEXIO_PINSTAT_OFFSET 0x0050 /* Pin Status */ +#define IMX9_FLEXIO_PINIEN_OFFSET 0x0054 /* Pin Interrupt Enable */ +#define IMX9_FLEXIO_PINREN_OFFSET 0x0058 /* Pin Rising Edge Enable */ +#define IMX9_FLEXIO_PINFEN_OFFSET 0x005c /* Pin Falling Edge Enable */ +#define IMX9_FLEXIO_PINOUTD_OFFSET 0x0060 /* Pin Output Data */ +#define IMX9_FLEXIO_PINOUTE_OFFSET 0x0064 /* Pin Output Enable */ +#define IMX9_FLEXIO_PINOUTDIS_OFFSET 0x0068 /* Pin Output Disable */ +#define IMX9_FLEXIO_PINOUTCLR_OFFSET 0x006c /* Pin Output Clear */ +#define IMX9_FLEXIO_PINOUTSET_OFFSET 0x0070 /* Pin Output Set */ +#define IMX9_FLEXIO_PINOUTTOG_OFFSET 0x0074 /* Pin Output Toggle */ +#define IMX9_FLEXIO_SHIFTCTL0_OFFSET 0x0080 /* Shifter Control N Register, array offset: 0x80, array step: 0x4 */ +#define IMX9_FLEXIO_SHIFTCTL1_OFFSET 0x0084 +#define IMX9_FLEXIO_SHIFTCTL2_OFFSET 0x0088 +#define IMX9_FLEXIO_SHIFTCTL3_OFFSET 0x008c +#define IMX9_FLEXIO_SHIFTCTL4_OFFSET 0x0090 +#define IMX9_FLEXIO_SHIFTCTL5_OFFSET 0x0094 +#define IMX9_FLEXIO_SHIFTCTL6_OFFSET 0x0098 +#define IMX9_FLEXIO_SHIFTCTL7_OFFSET 0x009c +#define IMX9_FLEXIO_SHIFTCFG0_OFFSET 0x0100 /* Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ +#define IMX9_FLEXIO_SHIFTCFG1_OFFSET 0x0104 +#define IMX9_FLEXIO_SHIFTCFG2_OFFSET 0x0108 +#define IMX9_FLEXIO_SHIFTCFG3_OFFSET 0x010c +#define IMX9_FLEXIO_SHIFTCFG4_OFFSET 0x0110 +#define IMX9_FLEXIO_SHIFTCFG5_OFFSET 0x0114 +#define IMX9_FLEXIO_SHIFTCFG6_OFFSET 0x0118 +#define IMX9_FLEXIO_SHIFTCFG7_OFFSET 0x011c +#define IMX9_FLEXIO_SHIFTBUF0_OFFSET 0x0200 /* Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ +#define IMX9_FLEXIO_SHIFTBUF1_OFFSET 0x0204 +#define IMX9_FLEXIO_SHIFTBUF2_OFFSET 0x0208 +#define IMX9_FLEXIO_SHIFTBUF3_OFFSET 0x020c +#define IMX9_FLEXIO_SHIFTBUF4_OFFSET 0x0210 +#define IMX9_FLEXIO_SHIFTBUF5_OFFSET 0x0214 +#define IMX9_FLEXIO_SHIFTBUF6_OFFSET 0x0218 +#define IMX9_FLEXIO_SHIFTBUF7_OFFSET 0x021c +#define IMX9_FLEXIO_SHIFTBUFBIS0_OFFSET 0x0280 /* Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ +#define IMX9_FLEXIO_SHIFTBUFBIS1_OFFSET 0x0284 +#define IMX9_FLEXIO_SHIFTBUFBIS2_OFFSET 0x0288 +#define IMX9_FLEXIO_SHIFTBUFBIS3_OFFSET 0x028c +#define IMX9_FLEXIO_SHIFTBUFBIS4_OFFSET 0x0290 +#define IMX9_FLEXIO_SHIFTBUFBIS5_OFFSET 0x0294 +#define IMX9_FLEXIO_SHIFTBUFBIS6_OFFSET 0x0298 +#define IMX9_FLEXIO_SHIFTBUFBIS7_OFFSET 0x029c +#define IMX9_FLEXIO_SHIFTBUFBYS0_OFFSET 0x0300 /* Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ +#define IMX9_FLEXIO_SHIFTBUFBYS1_OFFSET 0x0304 +#define IMX9_FLEXIO_SHIFTBUFBYS2_OFFSET 0x0308 +#define IMX9_FLEXIO_SHIFTBUFBYS3_OFFSET 0x030c +#define IMX9_FLEXIO_SHIFTBUFBYS4_OFFSET 0x0310 +#define IMX9_FLEXIO_SHIFTBUFBYS5_OFFSET 0x0314 +#define IMX9_FLEXIO_SHIFTBUFBYS6_OFFSET 0x0318 +#define IMX9_FLEXIO_SHIFTBUFBYS7_OFFSET 0x031c +#define IMX9_FLEXIO_SHIFTBUFBBS0_OFFSET 0x0380 /* Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ +#define IMX9_FLEXIO_SHIFTBUFBBS1_OFFSET 0x0384 +#define IMX9_FLEXIO_SHIFTBUFBBS2_OFFSET 0x0388 +#define IMX9_FLEXIO_SHIFTBUFBBS3_OFFSET 0x038c +#define IMX9_FLEXIO_SHIFTBUFBBS4_OFFSET 0x0390 +#define IMX9_FLEXIO_SHIFTBUFBBS5_OFFSET 0x0394 +#define IMX9_FLEXIO_SHIFTBUFBBS6_OFFSET 0x0398 +#define IMX9_FLEXIO_SHIFTBUFBBS7_OFFSET 0x039c +#define IMX9_FLEXIO_TIMCTL0_OFFSET 0x0400 /* Timer Control N Register, array offset: 0x400, array step: 0x4 */ +#define IMX9_FLEXIO_TIMCTL1_OFFSET 0x0404 +#define IMX9_FLEXIO_TIMCTL2_OFFSET 0x0408 +#define IMX9_FLEXIO_TIMCTL3_OFFSET 0x040c +#define IMX9_FLEXIO_TIMCTL4_OFFSET 0x0410 +#define IMX9_FLEXIO_TIMCTL5_OFFSET 0x0414 +#define IMX9_FLEXIO_TIMCTL6_OFFSET 0x0418 +#define IMX9_FLEXIO_TIMCTL7_OFFSET 0x041c +#define IMX9_FLEXIO_TIMCTL_OFFSET(x) (IMX9_FLEXIO_TIMCTL0_OFFSET + (x) * 4) +#define IMX9_FLEXIO_TIMCFG0_OFFSET 0x0480 /* Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ +#define IMX9_FLEXIO_TIMCFG1_OFFSET 0x0484 +#define IMX9_FLEXIO_TIMCFG2_OFFSET 0x0488 +#define IMX9_FLEXIO_TIMCFG3_OFFSET 0x048c +#define IMX9_FLEXIO_TIMCFG4_OFFSET 0x0490 +#define IMX9_FLEXIO_TIMCFG5_OFFSET 0x0494 +#define IMX9_FLEXIO_TIMCFG6_OFFSET 0x0498 +#define IMX9_FLEXIO_TIMCFG7_OFFSET 0x049c +#define IMX9_FLEXIO_TIMCFG_OFFSET(x) (IMX9_FLEXIO_TIMCFG0_OFFSET + (x) * 4) +#define IMX9_FLEXIO_TIMCMP0_OFFSET 0x0500 /* Timer Compare N Register, array offset: 0x500, array step: 0x4 */ +#define IMX9_FLEXIO_TIMCMP1_OFFSET 0x0504 +#define IMX9_FLEXIO_TIMCMP2_OFFSET 0x0508 +#define IMX9_FLEXIO_TIMCMP3_OFFSET 0x050c +#define IMX9_FLEXIO_TIMCMP4_OFFSET 0x0510 +#define IMX9_FLEXIO_TIMCMP5_OFFSET 0x0514 +#define IMX9_FLEXIO_TIMCMP6_OFFSET 0x0518 +#define IMX9_FLEXIO_TIMCMP7_OFFSET 0x051c +#define IMX9_FLEXIO_TIMCMP_OFFSET(x) (IMX9_FLEXIO_TIMCMP0_OFFSET + (x) * 4) +#define IMX9_FLEXIO_SHIFTBUFNBS0_OFFSET 0x0680 /* Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */ +#define IMX9_FLEXIO_SHIFTBUFNBS1_OFFSET 0x0684 +#define IMX9_FLEXIO_SHIFTBUFNBS2_OFFSET 0x0688 +#define IMX9_FLEXIO_SHIFTBUFNBS3_OFFSET 0x068c +#define IMX9_FLEXIO_SHIFTBUFNBS4_OFFSET 0x0690 +#define IMX9_FLEXIO_SHIFTBUFNBS5_OFFSET 0x0694 +#define IMX9_FLEXIO_SHIFTBUFNBS6_OFFSET 0x0698 +#define IMX9_FLEXIO_SHIFTBUFNBS7_OFFSET 0x069c +#define IMX9_FLEXIO_SHIFTBUFHWS0_OFFSET 0x0700 /* Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */ +#define IMX9_FLEXIO_SHIFTBUFHWS1_OFFSET 0x0704 +#define IMX9_FLEXIO_SHIFTBUFHWS2_OFFSET 0x0708 +#define IMX9_FLEXIO_SHIFTBUFHWS3_OFFSET 0x070c +#define IMX9_FLEXIO_SHIFTBUFHWS4_OFFSET 0x0710 +#define IMX9_FLEXIO_SHIFTBUFHWS5_OFFSET 0x0714 +#define IMX9_FLEXIO_SHIFTBUFHWS6_OFFSET 0x0718 +#define IMX9_FLEXIO_SHIFTBUFHWS7_OFFSET 0x071c +#define IMX9_FLEXIO_SHIFTBUFNIS0_OFFSET 0x0780 /* Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */ +#define IMX9_FLEXIO_SHIFTBUFNIS1_OFFSET 0x0784 +#define IMX9_FLEXIO_SHIFTBUFNIS2_OFFSET 0x0788 +#define IMX9_FLEXIO_SHIFTBUFNIS3_OFFSET 0x078c +#define IMX9_FLEXIO_SHIFTBUFNIS4_OFFSET 0x0790 +#define IMX9_FLEXIO_SHIFTBUFNIS5_OFFSET 0x0794 +#define IMX9_FLEXIO_SHIFTBUFNIS6_OFFSET 0x0798 +#define IMX9_FLEXIO_SHIFTBUFNIS7_OFFSET 0x079c +#define IMX9_FLEXIO_SHIFTBUFOES0_OFFSET 0x0800 /* Shifter Buffer N Odd Even Swapped, array offset: 0x800, array step: 0x4 */ +#define IMX9_FLEXIO_SHIFTBUFOES1_OFFSET 0x0804 +#define IMX9_FLEXIO_SHIFTBUFOES2_OFFSET 0x0808 +#define IMX9_FLEXIO_SHIFTBUFOES3_OFFSET 0x080c +#define IMX9_FLEXIO_SHIFTBUFOES4_OFFSET 0x0810 +#define IMX9_FLEXIO_SHIFTBUFOES5_OFFSET 0x0814 +#define IMX9_FLEXIO_SHIFTBUFOES6_OFFSET 0x0818 +#define IMX9_FLEXIO_SHIFTBUFOES7_OFFSET 0x081c +#define IMX9_FLEXIO_SHIFTBUFEOS0_OFFSET 0x0880 /* Shifter Buffer N Even Odd Swapped, array offset: 0x880, array step: 0x4 */ +#define IMX9_FLEXIO_SHIFTBUFEOS1_OFFSET 0x0884 +#define IMX9_FLEXIO_SHIFTBUFEOS2_OFFSET 0x0888 +#define IMX9_FLEXIO_SHIFTBUFEOS3_OFFSET 0x088c +#define IMX9_FLEXIO_SHIFTBUFEOS4_OFFSET 0x0890 +#define IMX9_FLEXIO_SHIFTBUFEOS5_OFFSET 0x0894 +#define IMX9_FLEXIO_SHIFTBUFEOS6_OFFSET 0x0898 +#define IMX9_FLEXIO_SHIFTBUFEOS7_OFFSET 0x089c +#define IMX9_FLEXIO_SHIFTBUFHBS0_OFFSET 0x0900 /* Shifter Buffer N Halfword Byte Swapped, array offset: 0x900, array step: 0x4 */ +#define IMX9_FLEXIO_SHIFTBUFHBS1_OFFSET 0x0904 +#define IMX9_FLEXIO_SHIFTBUFHBS2_OFFSET 0x0908 +#define IMX9_FLEXIO_SHIFTBUFHBS3_OFFSET 0x090c +#define IMX9_FLEXIO_SHIFTBUFHBS4_OFFSET 0x0910 +#define IMX9_FLEXIO_SHIFTBUFHBS5_OFFSET 0x0914 +#define IMX9_FLEXIO_SHIFTBUFHBS6_OFFSET 0x0918 +#define IMX9_FLEXIO_SHIFTBUFHBS7_OFFSET 0x091c + +/* VERID - Version ID Register */ + +#define FLEXIO_VERID_FEATURE_MASK (0xffffu) +#define FLEXIO_VERID_FEATURE_SHIFT (0u) + +/* FEATURE - Feature Specification Number + * 0b0000000000000000..Standard features implemented. + * 0b0000000000000001..Supports state, logic and parallel modes. + */ + +#define FLEXIO_VERID_FEATURE(x) ((((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT) & FLEXIO_VERID_FEATURE_MASK) + +#define FLEXIO_VERID_MINOR_MASK (0xff0000u) +#define FLEXIO_VERID_MINOR_SHIFT (16u) + +/* MINOR - Minor Version Number */ + +#define FLEXIO_VERID_MINOR(x) ((((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT) & FLEXIO_VERID_MINOR_MASK) + +#define FLEXIO_VERID_MAJOR_MASK (0xff000000u) +#define FLEXIO_VERID_MAJOR_SHIFT (24u) + +/* MAJOR - Major Version Number */ +#define FLEXIO_VERID_MAJOR(x) ((((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT) & FLEXIO_VERID_MAJOR_MASK) + +/* PARAM - Parameter Register */ + +#define FLEXIO_PARAM_SHIFTER_MASK (0xffu) +#define FLEXIO_PARAM_SHIFTER_SHIFT (0u) + +/* SHIFTER - Shifter Number */ +#define FLEXIO_PARAM_SHIFTER(x) ((((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT) & FLEXIO_PARAM_SHIFTER_MASK) + +#define FLEXIO_PARAM_TIMER_MASK (0xff00u) +#define FLEXIO_PARAM_TIMER_SHIFT (8u) + +/* TIMER - Timer Number */ + +#define FLEXIO_PARAM_TIMER(x) ((((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT) & FLEXIO_PARAM_TIMER_MASK) + +#define FLEXIO_PARAM_PIN_MASK (0xff0000u) +#define FLEXIO_PARAM_PIN_SHIFT (16u) + +/* PIN - Pin Number */ +#define FLEXIO_PARAM_PIN(x) ((((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT) & FLEXIO_PARAM_PIN_MASK) + +#define FLEXIO_PARAM_TRIGGER_MASK (0xff000000u) +#define FLEXIO_PARAM_TRIGGER_SHIFT (24u) + +/* TRIGGER - Trigger Number */ + +#define FLEXIO_PARAM_TRIGGER(x) ((((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT) & FLEXIO_PARAM_TRIGGER_MASK) + +/* CTRL - FlexIO Control Register */ + +#define FLEXIO_CTRL_FLEXEN_MASK (0x1u) +#define FLEXIO_CTRL_FLEXEN_SHIFT (0u) + +/* FLEXEN - FlexIO Enable + * 0b0..FlexIO module is disabled. + * 0b1..FlexIO module is enabled. + */ + +#define FLEXIO_CTRL_FLEXEN(x) ((((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT) & FLEXIO_CTRL_FLEXEN_MASK) + +#define FLEXIO_CTRL_SWRST_MASK (0x2u) +#define FLEXIO_CTRL_SWRST_SHIFT (1u) + +/* SWRST - Software Reset + * 0b0..Software reset is disabled + * 0b1..Software reset is enabled, all FlexIO registers except the Control + * Register are reset. + */ + +#define FLEXIO_CTRL_SWRST(x) ((((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT) & FLEXIO_CTRL_SWRST_MASK) + +#define FLEXIO_CTRL_FASTACC_MASK (0x4u) +#define FLEXIO_CTRL_FASTACC_SHIFT (2u) + +/* FASTACC - Fast Access + * 0b0..Configures for normal register accesses to FlexIO + * 0b1..Configures for fast register accesses to FlexIO + */ + +#define FLEXIO_CTRL_FASTACC(x) ((((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT) & FLEXIO_CTRL_FASTACC_MASK) + +#define FLEXIO_CTRL_DBGE_MASK (0x40000000u) +#define FLEXIO_CTRL_DBGE_SHIFT (30u) + +/* DBGE - Debug Enable + * 0b0..FlexIO is disabled in debug modes. + * 0b1..FlexIO is enabled in debug modes + */ + +#define FLEXIO_CTRL_DBGE(x) ((((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT) & FLEXIO_CTRL_DBGE_MASK) + +#define FLEXIO_CTRL_DOZEN_MASK (0x80000000u) +#define FLEXIO_CTRL_DOZEN_SHIFT (31u) + +/* DOZEN - Doze Enable + * 0b0..FlexIO enabled in Doze modes. + * 0b1..FlexIO disabled in Doze modes. + */ + +#define FLEXIO_CTRL_DOZEN(x) ((((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT) & FLEXIO_CTRL_DOZEN_MASK) + +/* PIN - Pin State Register */ + +#define FLEXIO_PIN_PDI_MASK (0xffffffffu) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */ +#define FLEXIO_PIN_PDI_SHIFT (0u) + +/* PDI - Pin Data Input */ + +#define FLEXIO_PIN_PDI(x) ((((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT) & FLEXIO_PIN_PDI_MASK) /* Merged from fields with different position or width, of widths (16, 32), largest definition used */ + +/* SHIFTSTAT - Shifter Status Register */ + +#define FLEXIO_SHIFTSTAT_SSF_MASK (0xffu) +#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0u) + +/* SSF - Shifter Status Flag */ + +#define FLEXIO_SHIFTSTAT_SSF(x) ((((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT) & FLEXIO_SHIFTSTAT_SSF_MASK) + +/* SHIFTERR - Shifter Error Register */ + +#define FLEXIO_SHIFTERR_SEF_MASK (0xffu) +#define FLEXIO_SHIFTERR_SEF_SHIFT (0u) + +/* SEF - Shifter Error Flags */ + +#define FLEXIO_SHIFTERR_SEF(x) ((((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT) & FLEXIO_SHIFTERR_SEF_MASK) + +/* TIMSTAT - Timer Status Register */ + +#define FLEXIO_TIMSTAT_TSF_MASK (0xffu) +#define FLEXIO_TIMSTAT_TSF_SHIFT (0u) + +/* TSF - Timer Status Flags */ + +#define FLEXIO_TIMSTAT_TSF(x) ((((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT) & FLEXIO_TIMSTAT_TSF_MASK) + +/* SHIFTSIEN - Shifter Status Interrupt Enable */ + +#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xffu) +#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0u) + +/* SSIE - Shifter Status Interrupt Enable */ + +#define FLEXIO_SHIFTSIEN_SSIE(x) ((((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT) & FLEXIO_SHIFTSIEN_SSIE_MASK) + +/* SHIFTEIEN - Shifter Error Interrupt Enable */ + +#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xffu) +#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0u) + +/* SEIE - Shifter Error Interrupt Enable */ + +#define FLEXIO_SHIFTEIEN_SEIE(x) ((((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT) & FLEXIO_SHIFTEIEN_SEIE_MASK) + +/* TIMIEN - Timer Interrupt Enable Register */ + +#define FLEXIO_TIMIEN_TEIE_MASK (0xffu) +#define FLEXIO_TIMIEN_TEIE_SHIFT (0u) + +/* TEIE - Timer Status Interrupt Enable */ + +#define FLEXIO_TIMIEN_TEIE(x) ((((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT) & FLEXIO_TIMIEN_TEIE_MASK) + +/* SHIFTSDEN - Shifter Status DMA Enable */ + +#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xffu) +#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0u) + +/* SSDE - Shifter Status DMA Enable */ + +#define FLEXIO_SHIFTSDEN_SSDE(x) ((((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT) & FLEXIO_SHIFTSDEN_SSDE_MASK) + +/* TIMERSDEN - Timer Status DMA Enable */ + +#define FLEXIO_TIMERSDEN_TSDE_MASK (0xffu) +#define FLEXIO_TIMERSDEN_TSDE_SHIFT (0u) + +/* TSDE - Timer Status DMA Enable */ + +#define FLEXIO_TIMERSDEN_TSDE(x) ((((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT) & FLEXIO_TIMERSDEN_TSDE_MASK) + +/* SHIFTSTATE - Shifter State Register */ + +#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7u) +#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0u) + +/* STATE - Current State Pointer */ + +#define FLEXIO_SHIFTSTATE_STATE(x) ((((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT) & FLEXIO_SHIFTSTATE_STATE_MASK) + +/* TRGSTAT - Trigger Status */ + +#define FLEXIO_TRGSTAT_ETSF_MASK (0xfu) +#define FLEXIO_TRGSTAT_ETSF_SHIFT (0u) + +#define FLEXIO_TRGSTAT_ETSF(x) ((((uint32_t)(x)) << FLEXIO_TRGSTAT_ETSF_SHIFT) & FLEXIO_TRGSTAT_ETSF_MASK) + +/* TRIGIEN - External Trigger Interrupt Enable */ + +#define FLEXIO_TRIGIEN_TRIE_MASK (0xfu) +#define FLEXIO_TRIGIEN_TRIE_SHIFT (0u) + +#define FLEXIO_TRIGIEN_TRIE(x) ((((uint32_t)(x)) << FLEXIO_TRIGIEN_TRIE_SHIFT) & FLEXIO_TRIGIEN_TRIE_MASK) + +/* SHIFTCTL - Shifter Control N Register */ + +#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7u) +#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0u) + +/* SMOD - Shifter Mode + * 0b000..Disabled. + * 0b001..Receive mode. Captures the current Shifter content into the + * SHIFTBUF on expiration of the Timer. + * 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on + * expiration of the Timer. + * 0b011..Reserved. + * 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on + * expiration of the Timer. + * 0b101..Match Continuous mode. Shifter data is continuously compared to + * SHIFTBUF contents. + * 0b110..State mode. SHIFTBUF contents are used for storing programmable + * state attributes. + * 0b111..Logic mode. SHIFTBUF contents are used for implementing + * programmable logic look up table. + */ + +#define FLEXIO_SHIFTCTL_SMOD(x) ((((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT) & FLEXIO_SHIFTCTL_SMOD_MASK) + +#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80u) +#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7u) + +/* PINPOL - Shifter Pin Polarity + * 0b0..Pin is active high + * 0b1..Pin is active low + */ + +#define FLEXIO_SHIFTCTL_PINPOL(x) ((((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT) & FLEXIO_SHIFTCTL_PINPOL_MASK) + +#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1f00u) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ +#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8u) + +/* PINSEL - Shifter Pin Select */ + +#define FLEXIO_SHIFTCTL_PINSEL(x) ((((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT) & FLEXIO_SHIFTCTL_PINSEL_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ + +#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000u) +#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16u) + +/* PINCFG - Shifter Pin Configuration + * 0b00..Shifter pin output disabled + * 0b01..Shifter pin open drain or bidirectional output enable + * 0b10..Shifter pin bidirectional output data + * 0b11..Shifter pin output + */ + +#define FLEXIO_SHIFTCTL_PINCFG(x) ((((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT) & FLEXIO_SHIFTCTL_PINCFG_MASK) + +#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000u) +#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23u) + +/* TIMPOL - Timer Polarity + * 0b0..Shift on posedge of Shift clock + * 0b1..Shift on negedge of Shift clock + */ + +#define FLEXIO_SHIFTCTL_TIMPOL(x) ((((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT) & FLEXIO_SHIFTCTL_TIMPOL_MASK) + +#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000u) +#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24u) + +/* TIMSEL - Timer Select */ + +#define FLEXIO_SHIFTCTL_TIMSEL(x) ((((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT) & FLEXIO_SHIFTCTL_TIMSEL_MASK) + +/* The count of FLEXIO_SHIFTCTL */ + +#define FLEXIO_SHIFTCTL_COUNT (8u) + +/* SHIFTCFG - Shifter Configuration N Register */ + +#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3u) +#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0u) + +/* SSTART - Shifter Start bit + * 0b00..Start bit disabled for transmitter/receiver/match store, + * transmitter loads data on enable + * 0b01..Start bit disabled for transmitter/receiver/match store, + * transmitter loads data on first shift + * 0b10..Transmitter outputs start bit value 0 before loading data on first + * shift, receiver/match store sets error flag if start bit is not 0 + * 0b11..Transmitter outputs start bit value 1 before loading data on first + * shift, receiver/match store sets error flag if start bit is not 1 + */ + +#define FLEXIO_SHIFTCFG_SSTART(x) ((((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT) & FLEXIO_SHIFTCFG_SSTART_MASK) + +#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30u) +#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4u) + +/* SSTOP - Shifter Stop bit + * 0b00..Stop bit disabled for transmitter/receiver/match store + * 0b01..Reserved for transmitter/receiver/match store + * 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store + * sets error flag if stop bit is not 0 + * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store + * sets error flag if stop bit is not 1 + */ + +#define FLEXIO_SHIFTCFG_SSTOP(x) ((((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT) & FLEXIO_SHIFTCFG_SSTOP_MASK) + +#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100u) +#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8u) + +/* INSRC - Input Source + * 0b0..Pin + * 0b1..Shifter N+1 Output + */ + +#define FLEXIO_SHIFTCFG_INSRC(x) ((((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT) & FLEXIO_SHIFTCFG_INSRC_MASK) + +/* LATST - Late Store */ + +#define FLEXIO_SHIFTCFG_LATST_MASK (0x200u) +#define FLEXIO_SHIFTCFG_LATST_SHIFT (9u) + +#define FLEXIO_SHIFTCFG_LATST(x) ((((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT) & FLEXIO_SHIFTCFG_LATST_MASK) + +/* SSIZE - Shifter Size */ + +#define FLEXIO_SHIFTCFG_SSIZE_MASK (0x1000u) +#define FLEXIO_SHIFTCFG_SSIZE_SHIFT (12u) + +#define FLEXIO_SHIFTCFG_SSIZE(x) ((((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSIZE_SHIFT) & FLEXIO_SHIFTCFG_SSIZE_MASK) + +#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1f0000u) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ +#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16u) + +/* PWIDTH - Parallel Width */ + +#define FLEXIO_SHIFTCFG_PWIDTH(x) ((((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT) & FLEXIO_SHIFTCFG_PWIDTH_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ + +/* The count of FLEXIO_SHIFTCFG */ + +#define FLEXIO_SHIFTCFG_COUNT (8u) + +/* SHIFTBUF - Shifter Buffer N Register */ + +#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xffffffffu) +#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0u) + +/* SHIFTBUF - Shift Buffer */ + +#define FLEXIO_SHIFTBUF_SHIFTBUF(x) ((((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) + +/* The count of FLEXIO_SHIFTBUF */ + +#define FLEXIO_SHIFTBUF_COUNT (8u) + +/* SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ + +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xffffffffu) +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0u) + +/* SHIFTBUFBIS - Shift Buffer */ + +#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) ((((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) + +/* The count of FLEXIO_SHIFTBUFBIS */ + +#define FLEXIO_SHIFTBUFBIS_COUNT (8u) + +/* SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ + +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xffffffffu) +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0u) + +/* SHIFTBUFBYS - Shift Buffer */ + +#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) ((((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) + +/* The count of FLEXIO_SHIFTBUFBYS */ + +#define FLEXIO_SHIFTBUFBYS_COUNT (8u) + +/* SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ + +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xffffffffu) +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0u) + +/* SHIFTBUFBBS - Shift Buffer */ + +#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) ((((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) + +/* The count of FLEXIO_SHIFTBUFBBS */ + +#define FLEXIO_SHIFTBUFBBS_COUNT (8u) + +/* TIMCTL - Timer Control N Register */ + +#define FLEXIO_TIMCTL_TIMOD_MASK (0x3u) +#define FLEXIO_TIMCTL_TIMOD_SHIFT (0u) + +/* TIMOD - Timer Mode + * 0b000..Timer Disabled. + * 0b001..Dual 8-bit counters baud mode. + * 0b010..Dual 8-bit counters PWM high mode. + * 0b011..Single 16-bit counter mode. + * 0b100..Single 16-bit counter disable mode. + * 0b101..Dual 8-bit counters word mode. + * 0b110..Dual 8-bit counters PWM low mode. + * 0b111..Single 16-bit input capture mode. + */ + +#define FLEXIO_TIMCTL_TIMOD(x) ((((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT) & FLEXIO_TIMCTL_TIMOD_MASK) + +#define FLEXIO_TIMCTL_PINPOL_MASK (0x80u) +#define FLEXIO_TIMCTL_PINPOL_SHIFT (7u) + +/* PINPOL - Timer Pin Polarity + * 0b0..Pin is active high + * 0b1..Pin is active low + */ + +#define FLEXIO_TIMCTL_PINPOL(x) ((((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT) & FLEXIO_TIMCTL_PINPOL_MASK) + +#define FLEXIO_TIMCTL_PINSEL_MASK (0x1f00u) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ +#define FLEXIO_TIMCTL_PINSEL_SHIFT (8u) + +/* PINSEL - Timer Pin Select */ + +#define FLEXIO_TIMCTL_PINSEL(x) ((((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT) & FLEXIO_TIMCTL_PINSEL_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ + +#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000u) +#define FLEXIO_TIMCTL_PINCFG_SHIFT (16u) + +/* PINCFG - Timer Pin Configuration + * 0b00..Timer pin output disabled + * 0b01..Timer pin open drain or bidirectional output enable + * 0b10..Timer pin bidirectional output data + * 0b11..Timer pin output + */ + +#define FLEXIO_TIMCTL_PINCFG(x) ((((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT) & FLEXIO_TIMCTL_PINCFG_MASK) + +#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000u) +#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22u) + +/* TRGSRC - Trigger Source + * 0b0..External trigger selected + * 0b1..Internal trigger selected + */ + +#define FLEXIO_TIMCTL_TRGSRC(x) ((((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT) & FLEXIO_TIMCTL_TRGSRC_MASK) + +#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000u) +#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23u) + +/* TRGPOL - Trigger Polarity + * 0b0..Trigger active high + * 0b1..Trigger active low + */ + +#define FLEXIO_TIMCTL_TRGPOL(x) ((((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT) & FLEXIO_TIMCTL_TRGPOL_MASK) + +#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3f000000u) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ +#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24u) + +/* TRGSEL - Trigger Select */ + +#define FLEXIO_TIMCTL_TRGSEL(x) ((((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT) & FLEXIO_TIMCTL_TRGSEL_MASK) /* Merged from fields with different position or width, of widths (5, 6), largest definition used */ + +/* The count of FLEXIO_TIMCTL */ + +#define FLEXIO_TIMCTL_COUNT (8u) + +/* TIMCFG - Timer Configuration N Register */ + +#define FLEXIO_TIMCFG_TSTART_MASK (0x2u) +#define FLEXIO_TIMCFG_TSTART_SHIFT (1u) + +/* TSTART - Timer Start Bit + * 0b0..Start bit disabled + * 0b1..Start bit enabled + */ + +#define FLEXIO_TIMCFG_TSTART(x) ((((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT) & FLEXIO_TIMCFG_TSTART_MASK) + +#define FLEXIO_TIMCFG_TSTOP_MASK (0x30u) +#define FLEXIO_TIMCFG_TSTOP_SHIFT (4u) + +/* TSTOP - Timer Stop Bit + * 0b00..Stop bit disabled + * 0b01..Stop bit is enabled on timer compare + * 0b10..Stop bit is enabled on timer disable + * 0b11..Stop bit is enabled on timer compare and timer disable + */ + +#define FLEXIO_TIMCFG_TSTOP(x) ((((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT) & FLEXIO_TIMCFG_TSTOP_MASK) + +#define FLEXIO_TIMCFG_TIMENA_MASK (0x700u) +#define FLEXIO_TIMCFG_TIMENA_SHIFT (8u) + +/* TIMENA - Timer Enable + * 0b000..Timer always enabled + * 0b001..Timer enabled on Timer N-1 enable + * 0b010..Timer enabled on Trigger high + * 0b011..Timer enabled on Trigger high and Pin high + * 0b100..Timer enabled on Pin rising edge + * 0b101..Timer enabled on Pin rising edge and Trigger high + * 0b110..Timer enabled on Trigger rising edge + * 0b111..Timer enabled on Trigger rising or falling edge + */ + +#define FLEXIO_TIMCFG_TIMENA(x) ((((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT) & FLEXIO_TIMCFG_TIMENA_MASK) + +#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000u) +#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12u) + +/* TIMDIS - Timer Disable + * 0b000..Timer never disabled + * 0b001..Timer disabled on Timer N-1 disable + * 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement) + * 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) + * and Trigger Low + * 0b100..Timer disabled on Pin rising or falling edge + * 0b101..Timer disabled on Pin rising or falling edge provided Trigger is + * high + * 0b110..Timer disabled on Trigger falling edge + * 0b111..Reserved + */ + +#define FLEXIO_TIMCFG_TIMDIS(x) ((((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT) & FLEXIO_TIMCFG_TIMDIS_MASK) + +#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000u) +#define FLEXIO_TIMCFG_TIMRST_SHIFT (16u) + +/* TIMRST - Timer Reset + * 0b000..Timer never reset + * 0b001..Reserved + * 0b010..Timer reset on Timer Pin equal to Timer Output + * 0b011..Timer reset on Timer Trigger equal to Timer Output + * 0b100..Timer reset on Timer Pin rising edge + * 0b101..Reserved + * 0b110..Timer reset on Trigger rising edge + * 0b111..Timer reset on Trigger rising or falling edge + */ + +#define FLEXIO_TIMCFG_TIMRST(x) ((((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT) & FLEXIO_TIMCFG_TIMRST_MASK) + +#define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000u) +#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) + +/* TIMDEC - Timer Decrement + * 0b00..Decrement counter on FlexIO clock, Shift clock equals Timer output. + * 0b01..Decrement counter on Trigger input (both edges), Shift clock equals + * Timer output. + * 0b10..Decrement counter on Pin input (both edges), Shift clock equals Pin + * input. + * 0b11..Decrement counter on Trigger input (both edges), Shift clock equals + * Trigger input. + */ + +#define FLEXIO_TIMCFG_TIMDEC(x) ((((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT) & FLEXIO_TIMCFG_TIMDEC_MASK) + +#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000u) +#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24u) + +/* TIMOUT - Timer Output + * 0b00..Timer output is logic one when enabled and is not affected by timer + * reset + * 0b01..Timer output is logic zero when enabled and is not affected by + * timer reset + * 0b10..Timer output is logic one when enabled and on timer reset + * 0b11..Timer output is logic zero when enabled and on timer reset + */ + +#define FLEXIO_TIMCFG_TIMOUT(x) ((((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT) & FLEXIO_TIMCFG_TIMOUT_MASK) + +/* The count of FLEXIO_TIMCFG */ + +#define FLEXIO_TIMCFG_COUNT (8u) + +/* TIMCMP - Timer Compare N Register */ + +#define FLEXIO_TIMCMP_CMP_MASK (0xffffu) +#define FLEXIO_TIMCMP_CMP_SHIFT (0u) + +/* CMP - Timer Compare Value */ + +#define FLEXIO_TIMCMP_CMP(x) ((((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT) & FLEXIO_TIMCMP_CMP_MASK) + +/* The count of FLEXIO_TIMCMP */ + +#define FLEXIO_TIMCMP_COUNT (8u) + +/* SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ + +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xffffffffu) +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0u) + +/* SHIFTBUFNBS - Shift Buffer */ + +#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) ((((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) + +/* The count of FLEXIO_SHIFTBUFNBS */ + +#define FLEXIO_SHIFTBUFNBS_COUNT (8u) + +/* SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */ + +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xffffffffu) +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0u) + +/* SHIFTBUFHWS - Shift Buffer */ + +#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) ((((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) + +/* The count of FLEXIO_SHIFTBUFHWS */ + +#define FLEXIO_SHIFTBUFHWS_COUNT (8u) + +/* SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ + +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xffffffffu) +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0u) + +/* SHIFTBUFNIS - Shift Buffer */ + +#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) ((((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) + +/* The count of FLEXIO_SHIFTBUFNIS */ + +#define FLEXIO_SHIFTBUFNIS_COUNT (8u) + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_FLEXIO_H */ diff --git a/arch/arm64/src/imx9/hardware/imx9_gpio.h b/arch/arm64/src/imx9/hardware/imx9_gpio.h new file mode 100644 index 0000000000000..b13be0eaf6b6a --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_gpio.h @@ -0,0 +1,106 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPIO_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX93) +# include "hardware/imx93/imx93_gpio.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define GPIO1 0 /* Port 1 index */ +#define GPIO2 1 /* Port 2 index */ +#define GPIO3 2 /* Port 3 index */ +#define GPIO4 3 /* Port 4 index */ +#define GPIO5 4 /* Port 5 index */ +#define GPIO6 5 /* Port 6 index */ +#define GPIO7 6 /* Port 7 index */ +#define GPIO8 7 /* Port 8 index */ +#define GPIO9 8 /* Port 9 index */ +#define GPIO10 9 /* Port 10 index */ +#define GPIO11 10 /* Port 11 index */ +#define GPIO12 11 /* Port 12 index */ +#define GPIO13 12 /* Port 13 index */ + +#define IMX9_GPIO_NPINS 32 /* Up to 32 pins per port */ + +/* Register bit definitions *************************************************/ + +/* Most registers are laid out simply with one bit per pin */ + +#define GPIO_PIN(n) (1 << (n)) /* Bit n: Pin n, n=0-31 */ + +/* ICRN Register */ + +#define IMX9_GPIO_ICRN_ISF (1 << 24) /* Bit 24: Interrupt Status Flag */ +#define IMX9_GPIO_ICRN_LK (1 << 23) /* Bit 23: Lock Register */ +#define IMX9_GPIO_ICRN_IRQS (1 << 20) /* Bit 20: Configures the selected interrupt, or DMA request. */ +#define IMX9_GPIO_ICRN_SHIFT (16) /* Bits 16-19: Interrupt Configuration */ +#define IMX9_GPIO_ICRN_MASK (0xf << IMX9_GPIO_ICRN_SHIFT) +# define IMX9_GPIO_ICRN_DISABLED (0 << IMX9_GPIO_ICRN_SHIFT) /* Interrupt Status Flag (ISF) is disabled */ +# define IMX9_GPIO_ICRN_DMARISING (1 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and DMA request on rising edge */ +# define IMX9_GPIO_ICRN_DMAFALLING (2 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and DMA request on falling edge */ +# define IMX9_GPIO_ICRN_DMABOTH (3 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and DMA request on either edge */ +# define IMX9_GPIO_ICRN_ISFRISING (5 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag sets on rising edge */ +# define IMX9_GPIO_ICRN_ISFFALLING (6 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag sets on falling edge */ +# define IMX9_GPIO_ICRN_ISFBOTH (7 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag sets on either edge */ +# define IMX9_GPIO_ICRN_ZERO (8 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt when logic 0 */ +# define IMX9_GPIO_ICRN_RISING (9 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt on rising-edge */ +# define IMX9_GPIO_ICRN_FALLING (10 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt on falling-edge */ +# define IMX9_GPIO_ICRN_BOTH (11 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt on either edge */ +# define IMX9_GPIO_ICRN_ONE (12 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt when logic 1 */ + +/* Global Interrupt Control Low Register */ + +#define IMX9_GPIO_GICLR_GIWD_SHIFT (0) /* Bits 0-15: Global Interrupt Write Data */ +#define IMX9_GPIO_GICLR_GIWD_MASK (0xffff << IMX9_GPIO_GICLR_GIWD_SHIFT) +# define IMX9_GPIO_GICLR_GIWD_PIN(n) ((uint32_t)(n) << IMX9_GPIO_GICLR_GIWD_SHIFT) /* Pin n=0..15 */ + +#define IMX9_GPIO_GICLR_GIWE_SHIFT (16) /* Bits 16-31: Global Interrupt Write Enable */ +#define IMX9_GPIO_GICLR_GIWE_MASK (0xffff << IMX9_GPIO_GICLR_GIWE_SHIFT) +# define IMX9_GPIO_GICLR_GIWE_PIN(n) ((uint32_t)(n) << IMX9_GPIO_GICLR_GIWE_SHIFT) /* Pin n=0..15 */ + +/* Global Interrupt Control High Register */ + +#define IMX9_GPIO_GICHR_GIWD_SHIFT (0) /* Bits 0-15: Global Interrupt Write Data */ +#define IMX9_GPIO_GICHR_GIWD_MASK (0xffff << IMX9_GPIO_GICHR_GIWD_SHIFT) +# define IMX9_GPIO_GICHR_GIWD_PIN(n) ((uint32_t)((n) - 16) << IMX9_GPIO_GICHR_GIWD_SHIFT) /* Pin n=16..31 */ + +#define IMX9_GPIO_GICHR_GIWE_SHIFT (16) /* Bits 16-31: Global Interrupt Write Enable */ +#define IMX9_GPIO_GICHR_GIWE_MASK (0xffff << IMX9_GPIO_GICHR_GIWE_SHIFT) +# define IMX9_GPIO_GICHR_GIWE_PIN(n) ((uint32_t)((n) - 16) << IMX9_GPIO_GICHR_GIWE_SHIFT) /* Pin n=16..31 */ + +/* Interrupt Status Flag Register */ + +#define IMX9_GPIO_ISFR(n) (1 << (n)) /* Interrupt Status Flag, n=0-31 */ + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPIO_H */ diff --git a/arch/arm64/src/imx9/hardware/imx9_iomuxc.h b/arch/arm64/src/imx9/hardware/imx9_iomuxc.h new file mode 100644 index 0000000000000..6e6fe9979c509 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_iomuxc.h @@ -0,0 +1,104 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_iomuxc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_IOMUXC_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_IOMUXC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX93) +# include "hardware/imx93/imx93_iomux.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Pad muxing */ + +#define IOMUXC_MUX_MODE_SHIFT (0) /* MODE: pin alternate function */ +#define IOMUXC_MUX_MODE_MASK (0x03 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT0 (0 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT1 (1 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT2 (2 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT3 (3 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT4 (4 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT5 (5 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT6 (6 << IOMUXC_MUX_MODE_SHIFT) + +#define IOMUXC_MUX_SION_SHIFT (4) /* SION: Force input path */ +#define IPMUXC_MUX_SION_MASK (0x01 << IOMUXC_MUX_SION_SHIFT) +#define IOMUXC_MUX_SION_OFF (0 << IOMUXC_MUX_SION_SHIFT) +#define IOMUXC_MUX_SION_ON (1 << IOMUXC_MUX_SION_SHIFT) + +/* Pad control */ + +#define IOMUXC_PAD_DSE_SHIFT (1) /* DSE: Drive strength */ +#define IOMUXC_PAD_DSE_MASK (0x3f << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X0 (0x00 << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X1 (0x01 << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X2 (0x03 << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X3 (0x07 << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X4 (0x0f << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X5 (0x1f << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X6 (0x3f << IOMUXC_PAD_DSE_SHIFT) + +#define IOMUXC_PAD_FSEL_SHIFT (7) /* FSEL: Slew rate control */ +#define IOMUXC_PAD_FSEL_MASK (0x02 << IOMUXC_PAD_FSEL_SHIFT) +#define IOMUXC_PAD_FSEL_SLOW (0 << IOMUXC_PAD_FSEL_SHIFT) +#define IOMUXC_PAD_FSEL_SSLOW (1 << IOMUXC_PAD_FSEL_SHIFT) /* Slightly slow */ +#define IOMUXC_PAD_FSEL_SFAST (2 << IOMUXC_PAD_FSEL_SHIFT) /* Slightly fast */ +#define IOMUXC_PAD_FSEL_FAST (3 << IOMUXC_PAD_FSEL_SHIFT) + +#define IOMUXC_PAD_PU_SHIFT (9) /* PU: Pull-up */ +#define IOMUXC_PAD_PU_MASK (0x01 << IOMUXC_PAD_PU_SHIFT) +#define IOMUXC_PAD_PU_OFF (0 << IOMUXC_PAD_PU_SHIFT) +#define IOMUXC_PAD_PU_ON (1 << IOMUXC_PAD_PU_SHIFT) + +#define IOMUXC_PAD_PD_SHIFT (10) /* PD: Pull-down */ +#define IOMUXC_PAD_PD_MASK (0x01 << IOMUXC_PAD_PD_SHIFT) +#define IOMUXC_PAD_PD_OFF (0 << IOMUXC_PAD_PD_SHIFT) +#define IOMUXC_PAD_PD_ON (1 << IOMUXC_PAD_PD_SHIFT) + +#define IOMUXC_PAD_OD_SHIFT (11) /* OD: Open-drain */ +#define IOMUXC_PAD_OD_MASK (0x01 << IOMUXC_PAD_OD_SHIFT) +#define IOMUXC_PAD_OD_DISABE (0 << IOMUXC_PAD_OD_SHIFT) +#define IOMUXC_PAD_OD_ENABLE (1 << IOMUXC_PAD_OD_SHIFT) + +#define IOMUXC_PAD_HYS_SHIFT (12) /* HYS: Enable schmitt-trigger on input */ +#define IOMUXC_PAD_HYS_MASK (0x01 << IOMUXC_PAD_HYS_SHIFT) +#define IOMUXC_PAD_HYS_ST_OFF (0 << IOMUXC_PAD_HYS_SHIFT) /* Schmitt-trigger off */ +#define IOMUXC_PAD_HYS_ST_ON (1 << IOMUXC_PAD_HYS_SHIFT) /* Schmitt-trigger on */ + +#define IOMUXC_PAD_APC_SHIFT (24) /* APC: Access control */ +#define IOMUXC_PAD_APC_MASK (0xff << IOMUXC_PAD_APC_SHIFT) + +/* Daisy chain control, 2 bits seems to be enough */ + +#define IOMUXC_DSY_SHIFT (0) +#define IOMUXC_DSY_MASK (0x03 << IOMUXC_DSY_SHIFT) + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_IOMUXC_H */ diff --git a/arch/arm64/src/imx9/hardware/imx9_lpi2c.h b/arch/arm64/src/imx9/hardware/imx9_lpi2c.h new file mode 100644 index 0000000000000..1c7e47aa88833 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_lpi2c.h @@ -0,0 +1,622 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_lpi2c.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPI2C_H_ +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPI2C_H_ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define IMX9_LPI2C_VERID_OFFSET 0x0000 /* Version ID Register offset */ +#define IMX9_LPI2C_PARAM_OFFSET 0x0004 /* Parameter Register offset */ +#define IMX9_LPI2C_MCR_OFFSET 0x0010 /* Master Control Register offset */ +#define IMX9_LPI2C_MSR_OFFSET 0x0014 /* Master Status Register offset */ +#define IMX9_LPI2C_MIER_OFFSET 0x0018 /* Master Interrupt Enable Register offset */ +#define IMX9_LPI2C_MDER_OFFSET 0x001c /* Master DMA Enable Register offset */ +#define IMX9_LPI2C_MCFGR0_OFFSET 0x0020 /* Master Config Register 0 offset */ +#define IMX9_LPI2C_MCFGR1_OFFSET 0x0024 /* Master Config Register 1 offset */ +#define IMX9_LPI2C_MCFGR2_OFFSET 0x0028 /* Master Config Register 2 offset */ +#define IMX9_LPI2C_MCFGR3_OFFSET 0x002c /* Master Config Register 3 offset */ +#define IMX9_LPI2C_MDMR_OFFSET 0x0040 /* Master Data Match Register offset */ +#define IMX9_LPI2C_MCCR0_OFFSET 0x0048 /* Master Clock Configuration Register 0 offset */ +#define IMX9_LPI2C_MCCR1_OFFSET 0x0050 /* Master Clock Configuration Register 1 offset */ +#define IMX9_LPI2C_MFCR_OFFSET 0x0058 /* Master FIFO Control Register offset */ +#define IMX9_LPI2C_MFSR_OFFSET 0x005C /* Master FIFO Status Register offset */ +#define IMX9_LPI2C_MTDR_OFFSET 0x0060 /* Master Transmit Data Register offset */ +#define IMX9_LPI2C_MRDR_OFFSET 0x0070 /* Master Receive Data Register offset */ +#define IMX9_LPI2C_SCR_OFFSET 0x0110 /* Slave Control Register offset */ +#define IMX9_LPI2C_SSR_OFFSET 0x0114 /* Slave Status Register offset */ +#define IMX9_LPI2C_SIER_OFFSET 0x0118 /* Slave Interrupt Enable Register offset */ +#define IMX9_LPI2C_SDER_OFFSET 0x011c /* Slave DMA Enable Register offset */ +#define IMX9_LPI2C_SCFGR1_OFFSET 0x0124 /* Slave Config Register 1 offset */ +#define IMX9_LPI2C_SCFGR2_OFFSET 0x0128 /* Slave Config Register 2 offset */ +#define IMX9_LPI2C_SAMR_OFFSET 0x0140 /* Slave Address Match Register offset */ +#define IMX9_LPI2C_SASR_OFFSET 0x0150 /* Slave Address Status Register offset */ +#define IMX9_LPI2C_STAR_OFFSET 0x0154 /* Slave Transmit ACK Register offset */ +#define IMX9_LPI2C_STDR_OFFSET 0x0160 /* Slave Transmit Data Register offset */ +#define IMX9_LPI2C_SRDR_OFFSET 0x0170 /* Slave Receive Data Register offset */ + +/* Register addresses *******************************************************/ + +/* LPI2C1 Registers */ + +#define IMX9_LPI2C1_VERID (IMX9_LPI2C1_BASE + IMX9_LPI2C_VERID_OFFSET) /* Version ID Register */ +#define IMX9_LPI2C1_PARAM (IMX9_LPI2C1_BASE + IMX9_LPI2C_PARAM_OFFSET) /* Parameter Register */ +#define IMX9_LPI2C1_MCR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCR_OFFSET) /* Master Control Register */ +#define IMX9_LPI2C1_MSR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MSR_OFFSET) /* Master Status Register */ +#define IMX9_LPI2C1_MIER (IMX9_LPI2C1_BASE + IMX9_LPI2C_MIER_OFFSET) /* Master Interrupt Enable Register */ +#define IMX9_LPI2C1_MDER (IMX9_LPI2C1_BASE + IMX9_LPI2C_MDER_OFFSET) /* Master DMA Enable Register */ +#define IMX9_LPI2C1_MCFGR0 (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCFGR0_OFFSET) /* Master Config Register 0 */ +#define IMX9_LPI2C1_MCFGR1 (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCFGR1_OFFSET) /* Master Config Register 1 */ +#define IMX9_LPI2C1_MCFGR2 (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCFGR2_OFFSET) /* Master Config Register 2 */ +#define IMX9_LPI2C1_MCFGR3 (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCFGR3_OFFSET) /* Master Config Register 3 */ +#define IMX9_LPI2C1_MDMR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MDMR_OFFSET) /* Master Data Match Register */ +#define IMX9_LPI2C1_MCCR0 (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCCR0_OFFSET) /* Master Clock Configuration Register 0 */ +#define IMX9_LPI2C1_MCCR1 (IMX9_LPI2C1_BASE + IMX9_LPI2C_MCCR1_OFFSET) /* Master Clock Configuration Register 1 */ +#define IMX9_LPI2C1_MFCR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MFCR_OFFSET) /* Master FIFO Control Register */ +#define IMX9_LPI2C1_MFSR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MFSR_OFFSET) /* Master FIFO Status Register */ +#define IMX9_LPI2C1_MTDR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MTDR_OFFSET) /* Master Transmit Data Register */ +#define IMX9_LPI2C1_MRDR (IMX9_LPI2C1_BASE + IMX9_LPI2C_MRDR_OFFSET) /* Master Receive Data Register */ +#define IMX9_LPI2C1_SCR (IMX9_LPI2C1_BASE + IMX9_LPI2C_SCR_OFFSET) /* Slave Control Register */ +#define IMX9_LPI2C1_SSR (IMX9_LPI2C1_BASE + IMX9_LPI2C_SSR_OFFSET) /* Slave Status Register */ +#define IMX9_LPI2C1_SIER (IMX9_LPI2C1_BASE + IMX9_LPI2C_SIER_OFFSET) /* Slave Interrupt Enable Register */ +#define IMX9_LPI2C1_SDER (IMX9_LPI2C1_BASE + IMX9_LPI2C_SDER_OFFSET) /* Slave DMA Enable Register */ +#define IMX9_LPI2C1_SCFGR1 (IMX9_LPI2C1_BASE + IMX9_LPI2C_SCFGR1_OFFSET) /* Slave Config Register 1 */ +#define IMX9_LPI2C1_SCFGR2 (IMX9_LPI2C1_BASE + IMX9_LPI2C_SCFGR2_OFFSET) /* Slave Config Register 2 */ +#define IMX9_LPI2C1_SAMR (IMX9_LPI2C1_BASE + IMX9_LPI2C_SAMR_OFFSET) /* Slave Address Match Register */ +#define IMX9_LPI2C1_SASR (IMX9_LPI2C1_BASE + IMX9_LPI2C_SASR_OFFSET) /* Slave Address Status Register */ +#define IMX9_LPI2C1_STAR (IMX9_LPI2C1_BASE + IMX9_LPI2C_STAR_OFFSET) /* Slave Transmit ACK Register */ +#define IMX9_LPI2C1_STDR (IMX9_LPI2C1_BASE + IMX9_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */ +#define IMX9_LPI2C1_SRDR (IMX9_LPI2C1_BASE + IMX9_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */ + +/* LPI2C2 Registers */ + +#define IMX9_LPI2C2_VERID (IMX9_LPI2C2_BASE + IMX9_LPI2C_VERID_OFFSET) /* Version ID Register */ +#define IMX9_LPI2C2_PARAM (IMX9_LPI2C2_BASE + IMX9_LPI2C_PARAM_OFFSET) /* Parameter Register */ +#define IMX9_LPI2C2_MCR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCR_OFFSET) /* Master Control Register */ +#define IMX9_LPI2C2_MSR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MSR_OFFSET) /* Master Status Register */ +#define IMX9_LPI2C2_MIER (IMX9_LPI2C2_BASE + IMX9_LPI2C_MIER_OFFSET) /* Master Interrupt Enable Register */ +#define IMX9_LPI2C2_MDER (IMX9_LPI2C2_BASE + IMX9_LPI2C_MDER_OFFSET) /* Master DMA Enable Register */ +#define IMX9_LPI2C2_MCFGR0 (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCFGR0_OFFSET) /* Master Config Register 0 */ +#define IMX9_LPI2C2_MCFGR1 (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCFGR1_OFFSET) /* Master Config Register 1 */ +#define IMX9_LPI2C2_MCFGR2 (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCFGR2_OFFSET) /* Master Config Register 2 */ +#define IMX9_LPI2C2_MCFGR3 (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCFGR3_OFFSET) /* Master Config Register 3 */ +#define IMX9_LPI2C2_MDMR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MDMR_OFFSET) /* Master Data Match Register */ +#define IMX9_LPI2C2_MCCR0 (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCCR0_OFFSET) /* Master Clock Configuration Register 0 */ +#define IMX9_LPI2C2_MCCR1 (IMX9_LPI2C2_BASE + IMX9_LPI2C_MCCR1_OFFSET) /* Master Clock Configuration Register 1 */ +#define IMX9_LPI2C2_MFCR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MFCR_OFFSET) /* Master FIFO Control Register */ +#define IMX9_LPI2C2_MFSR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MFSR_OFFSET) /* Master FIFO Status Register */ +#define IMX9_LPI2C2_MTDR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MTDR_OFFSET) /* Master Transmit Data Register */ +#define IMX9_LPI2C2_MRDR (IMX9_LPI2C2_BASE + IMX9_LPI2C_MRDR_OFFSET) /* Master Receive Data Register */ +#define IMX9_LPI2C2_SCR (IMX9_LPI2C2_BASE + IMX9_LPI2C_SCR_OFFSET) /* Slave Control Register */ +#define IMX9_LPI2C2_SSR (IMX9_LPI2C2_BASE + IMX9_LPI2C_SSR_OFFSET) /* Slave Status Register */ +#define IMX9_LPI2C2_SIER (IMX9_LPI2C2_BASE + IMX9_LPI2C_SIER_OFFSET) /* Slave Interrupt Enable Register */ +#define IMX9_LPI2C2_SDER (IMX9_LPI2C2_BASE + IMX9_LPI2C_SDER_OFFSET) /* Slave DMA Enable Register */ +#define IMX9_LPI2C2_SCFGR1 (IMX9_LPI2C2_BASE + IMX9_LPI2C_SCFGR1_OFFSET) /* Slave Config Register 1 */ +#define IMX9_LPI2C2_SCFGR2 (IMX9_LPI2C2_BASE + IMX9_LPI2C_SCFGR2_OFFSET) /* Slave Config Register 2 */ +#define IMX9_LPI2C2_SAMR (IMX9_LPI2C2_BASE + IMX9_LPI2C_SAMR_OFFSET) /* Slave Address Match Register */ +#define IMX9_LPI2C2_SASR (IMX9_LPI2C2_BASE + IMX9_LPI2C_SASR_OFFSET) /* Slave Address Status Register */ +#define IMX9_LPI2C2_STAR (IMX9_LPI2C2_BASE + IMX9_LPI2C_STAR_OFFSET) /* Slave Transmit ACK Register */ +#define IMX9_LPI2C2_STDR (IMX9_LPI2C2_BASE + IMX9_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */ +#define IMX9_LPI2C2_SRDR (IMX9_LPI2C2_BASE + IMX9_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */ + +/* LPI2C3 Registers */ + +#define IMX9_LPI2C3_VERID (IMX9_LPI2C3_BASE + IMX9_LPI2C_VERID_OFFSET) /* Version ID Register */ +#define IMX9_LPI2C3_PARAM (IMX9_LPI2C3_BASE + IMX9_LPI2C_PARAM_OFFSET) /* Parameter Register */ +#define IMX9_LPI2C3_MCR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCR_OFFSET) /* Master Control Register */ +#define IMX9_LPI2C3_MSR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MSR_OFFSET) /* Master Status Register */ +#define IMX9_LPI2C3_MIER (IMX9_LPI2C3_BASE + IMX9_LPI2C_MIER_OFFSET) /* Master Interrupt Enable Register */ +#define IMX9_LPI2C3_MDER (IMX9_LPI2C3_BASE + IMX9_LPI2C_MDER_OFFSET) /* Master DMA Enable Register */ +#define IMX9_LPI2C3_MCFGR0 (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCFGR0_OFFSET) /* Master Config Register 0 */ +#define IMX9_LPI2C3_MCFGR1 (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCFGR1_OFFSET) /* Master Config Register 1 */ +#define IMX9_LPI2C3_MCFGR2 (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCFGR2_OFFSET) /* Master Config Register 2 */ +#define IMX9_LPI2C3_MCFGR3 (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCFGR3_OFFSET) /* Master Config Register 3 */ +#define IMX9_LPI2C3_MDMR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MDMR_OFFSET) /* Master Data Match Register */ +#define IMX9_LPI2C3_MCCR0 (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCCR0_OFFSET) /* Master Clock Configuration Register 0 */ +#define IMX9_LPI2C3_MCCR1 (IMX9_LPI2C3_BASE + IMX9_LPI2C_MCCR1_OFFSET) /* Master Clock Configuration Register 1 */ +#define IMX9_LPI2C3_MFCR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MFCR_OFFSET) /* Master FIFO Control Register */ +#define IMX9_LPI2C3_MFSR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MFSR_OFFSET) /* Master FIFO Status Register */ +#define IMX9_LPI2C3_MTDR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MTDR_OFFSET) /* Master Transmit Data Register */ +#define IMX9_LPI2C3_MRDR (IMX9_LPI2C3_BASE + IMX9_LPI2C_MRDR_OFFSET) /* Master Receive Data Register */ +#define IMX9_LPI2C3_SCR (IMX9_LPI2C3_BASE + IMX9_LPI2C_SCR_OFFSET) /* Slave Control Register */ +#define IMX9_LPI2C3_SSR (IMX9_LPI2C3_BASE + IMX9_LPI2C_SSR_OFFSET) /* Slave Status Register */ +#define IMX9_LPI2C3_SIER (IMX9_LPI2C3_BASE + IMX9_LPI2C_SIER_OFFSET) /* Slave Interrupt Enable Register */ +#define IMX9_LPI2C3_SDER (IMX9_LPI2C3_BASE + IMX9_LPI2C_SDER_OFFSET) /* Slave DMA Enable Register */ +#define IMX9_LPI2C3_SCFGR1 (IMX9_LPI2C3_BASE + IMX9_LPI2C_SCFGR1_OFFSET) /* Slave Config Register 1 */ +#define IMX9_LPI2C3_SCFGR2 (IMX9_LPI2C3_BASE + IMX9_LPI2C_SCFGR2_OFFSET) /* Slave Config Register 2 */ +#define IMX9_LPI2C3_SAMR (IMX9_LPI2C3_BASE + IMX9_LPI2C_SAMR_OFFSET) /* Slave Address Match Register */ +#define IMX9_LPI2C3_SASR (IMX9_LPI2C3_BASE + IMX9_LPI2C_SASR_OFFSET) /* Slave Address Status Register */ +#define IMX9_LPI2C3_STAR (IMX9_LPI2C3_BASE + IMX9_LPI2C_STAR_OFFSET) /* Slave Transmit ACK Register */ +#define IMX9_LPI2C3_STDR (IMX9_LPI2C3_BASE + IMX9_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */ +#define IMX9_LPI2C3_SRDR (IMX9_LPI2C3_BASE + IMX9_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */ + +/* LPI2C4 Registers */ + +#define IMX9_LPI2C4_VERID (IMX9_LPI2C4_BASE + IMX9_LPI2C_VERID_OFFSET) /* Version ID Register */ +#define IMX9_LPI2C4_PARAM (IMX9_LPI2C4_BASE + IMX9_LPI2C_PARAM_OFFSET) /* Parameter Register */ +#define IMX9_LPI2C4_MCR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCR_OFFSET) /* Master Control Register */ +#define IMX9_LPI2C4_MSR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MSR_OFFSET) /* Master Status Register */ +#define IMX9_LPI2C4_MIER (IMX9_LPI2C4_BASE + IMX9_LPI2C_MIER_OFFSET) /* Master Interrupt Enable Register */ +#define IMX9_LPI2C4_MDER (IMX9_LPI2C4_BASE + IMX9_LPI2C_MDER_OFFSET) /* Master DMA Enable Register */ +#define IMX9_LPI2C4_MCFGR0 (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCFGR0_OFFSET) /* Master Config Register 0 */ +#define IMX9_LPI2C4_MCFGR1 (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCFGR1_OFFSET) /* Master Config Register 1 */ +#define IMX9_LPI2C4_MCFGR2 (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCFGR2_OFFSET) /* Master Config Register 2 */ +#define IMX9_LPI2C4_MCFGR3 (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCFGR3_OFFSET) /* Master Config Register 3 */ +#define IMX9_LPI2C4_MDMR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MDMR_OFFSET) /* Master Data Match Register */ +#define IMX9_LPI2C4_MCCR0 (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCCR0_OFFSET) /* Master Clock Configuration Register 0 */ +#define IMX9_LPI2C4_MCCR1 (IMX9_LPI2C4_BASE + IMX9_LPI2C_MCCR1_OFFSET) /* Master Clock Configuration Register 1 */ +#define IMX9_LPI2C4_MFCR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MFCR_OFFSET) /* Master FIFO Control Register */ +#define IMX9_LPI2C4_MFSR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MFSR_OFFSET) /* Master FIFO Status Register */ +#define IMX9_LPI2C4_MTDR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MTDR_OFFSET) /* Master Transmit Data Register */ +#define IMX9_LPI2C4_MRDR (IMX9_LPI2C4_BASE + IMX9_LPI2C_MRDR_OFFSET) /* Master Receive Data Register */ +#define IMX9_LPI2C4_SCR (IMX9_LPI2C4_BASE + IMX9_LPI2C_SCR_OFFSET) /* Slave Control Register */ +#define IMX9_LPI2C4_SSR (IMX9_LPI2C4_BASE + IMX9_LPI2C_SSR_OFFSET) /* Slave Status Register */ +#define IMX9_LPI2C4_SIER (IMX9_LPI2C4_BASE + IMX9_LPI2C_SIER_OFFSET) /* Slave Interrupt Enable Register */ +#define IMX9_LPI2C4_SDER (IMX9_LPI2C4_BASE + IMX9_LPI2C_SDER_OFFSET) /* Slave DMA Enable Register */ +#define IMX9_LPI2C4_SCFGR1 (IMX9_LPI2C4_BASE + IMX9_LPI2C_SCFGR1_OFFSET) /* Slave Config Register 1 */ +#define IMX9_LPI2C4_SCFGR2 (IMX9_LPI2C4_BASE + IMX9_LPI2C_SCFGR2_OFFSET) /* Slave Config Register 2 */ +#define IMX9_LPI2C4_SAMR (IMX9_LPI2C4_BASE + IMX9_LPI2C_SAMR_OFFSET) /* Slave Address Match Register */ +#define IMX9_LPI2C4_SASR (IMX9_LPI2C4_BASE + IMX9_LPI2C_SASR_OFFSET) /* Slave Address Status Register */ +#define IMX9_LPI2C4_STAR (IMX9_LPI2C4_BASE + IMX9_LPI2C_STAR_OFFSET) /* Slave Transmit ACK Register */ +#define IMX9_LPI2C4_STDR (IMX9_LPI2C4_BASE + IMX9_LPI2C_STDR_OFFSET) /* Slave Transmit Data Register */ +#define IMX9_LPI2C4_SRDR (IMX9_LPI2C4_BASE + IMX9_LPI2C_SRDR_OFFSET) /* Slave Receive Data Register */ + +/* Register bit definitions *************************************************/ + +/* LPI2C Version ID Register */ + +#define LPI2C_VERID_FEATURE_SHIFT (0) +#define LPI2C_VERID_FEATURE_MASK (0xffff << LPI2C_VERID_FEATURE_SHIFT) +#define LPI2C_VERID_MINOR_SHIFT (16) +#define LPI2C_VERID_MINOR_MASK (0xff << LPI2C_VERID_MINOR_SHIFT) +#define LPI2C_VERID_MAJOR_SHIFT (24) +#define LPI2C_VERID_MAJOR_MASK (0xff << LPI2C_VERID_MAJOR_SHIFT) + +/* LPI2C Parameter Register */ + +#define LPI2C_PARAM_MTXFIFO_MASK (0x0f) /* Config number of words in master transmit fifo to 2^MTXFIFO (pow(2,MTXFIFO )) */ +# define LPI2C_PARAM_MTXFIFO_1_WORDS (0) +# define LPI2C_PARAM_MTXFIFO_2_WORDS (1) +# define LPI2C_PARAM_MTXFIFO_4_WORDS (2) +# define LPI2C_PARAM_MTXFIFO_8_WORDS (3) +# define LPI2C_PARAM_MTXFIFO_16_WORDS (4) +# define LPI2C_PARAM_MTXFIFO_32_WORDS (5) +# define LPI2C_PARAM_MTXFIFO_64_WORDS (6) +# define LPI2C_PARAM_MTXFIFO_128_WORDS (7) +# define LPI2C_PARAM_MTXFIFO_256_WORDS (8) +# define LPI2C_PARAM_MTXFIFO_512_WORDS (9) +# define LPI2C_PARAM_MTXFIFO_1024_WORDS (10) +# define LPI2C_PARAM_MTXFIFO_2048_WORDS (11) +# define LPI2C_PARAM_MTXFIFO_4096_WORDS (12) +# define LPI2C_PARAM_MTXFIFO_8192_WORDS (13) +# define LPI2C_PARAM_MTXFIFO_16384_WORDS (14) +# define LPI2C_PARAM_MTXFIFO_32768_WORDS (15) + +#define LPI2C_PARAM_MRXFIFO_SHIFT (8) +#define LPI2C_PARAM_MRXFIFO_MASK (0x0f << LPI2C_PARAM_MRXFIFO_SHIFT) /* Config number of words in master receive fifo 2^MRXFIFO (pow(2,MTRFIFO )) */ +# define LPI2C_PARAM_MRXFIFO_1_WORDS (0 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_2_WORDS (1 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_4_WORDS (2 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_8_WORDS (3 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_16_WORDS (4 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_32_WORDS (5 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_64_WORDS (6 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_128_WORDS (7 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_256_WORDS (8 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_512_WORDS (9 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_1024_WORDS (10 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_2048_WORDS (11 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_4096_WORDS (12 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_8192_WORDS (13 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_16384_WORDS (14 << LPI2C_PARAM_MRXFIFO_SHIFT) +# define LPI2C_PARAM_MRXFIFO_32768_WORDS (15 << LPI2C_PARAM_MRXFIFO_SHIFT) + +/* LPI2C Master Control Register */ + +#define LPI2C_MCR_MEN (1 << 0) /* Master Enable Bit */ +#define LPI2C_MCR_RST (1 << 1) /* Software Reset Bit */ +#define LPI2C_MCR_DOZEN (1 << 2) /* Doze Mode Enable Bit */ +#define LPI2C_MCR_DBGEN (1 << 3) /* Debug Enable Bit */ + /* Bits 7-4 Reserved */ +#define LPI2C_MCR_RTF (1 << 8) /* Reset Transmit FIFO Bit */ +#define LPI2C_MCR_RRF (1 << 9) /* Reset Receive FIFO Bit */ + /* Bits 31-10 Reserved */ + +/* LPI2C Master Status Register */ + +#define LPI2C_MSR_TDF (1 << 0) /* Transmit Data Flag Bit */ +#define LPI2C_MSR_RDF (1 << 1) /* Receive Data Flag Bit */ + /* Bits 7-2 Reserved */ +#define LPI2C_MSR_EPF (1 << 8) /* End Packet Flag Bit */ +#define LPI2C_MSR_SDF (1 << 9) /* STOP Detect Flag Bit */ +#define LPI2C_MSR_NDF (1 << 10) /* NACK Detect Flag Bit */ +#define LPI2C_MSR_ALF (1 << 11) /* Arbitration Lost Flag Bit */ +#define LPI2C_MSR_FEF (1 << 12) /* FIFO Error Flag Bit */ +#define LPI2C_MSR_PLTF (1 << 13) /* Pin Low Timeout Flag Bit */ +#define LPI2C_MSR_DMF (1 << 14) /* Data Match Flag Bit */ + /* Bits 23-15 Reserved */ +#define LPI2C_MSR_MBF (1 << 24) /* Master Busy Flag Bit */ +#define LPI2C_MSR_BBF (1 << 25) /* Bus Busy Flag Bit */ + /* Bits 31-26 Reserved */ +#define LPI2C_MSR_ERROR_MASK (LPI2C_MSR_NDF | LPI2C_MSR_ALF | \ + LPI2C_MSR_FEF) + +/* LPI2C Master Interrupt Enable Register */ + +#define LPI2C_MIER_TDIE (1 << 0) /* Transmit Data Interrupt Enable Bit */ +#define LPI2C_MIER_RDIE (1 << 1) /* Receive Data Interrupt Enable Bit */ + /* Bits 7-2 Reserved */ +#define LPI2C_MIER_EPIE (1 << 8) /* End Packet Interrupt Enable Bit */ +#define LPI2C_MIER_SDIE (1 << 9) /* STOP Detect Interrupt Enable Bit */ +#define LPI2C_MIER_NDIE (1 << 10) /* NACK Detect Interrupt Enable Bit */ +#define LPI2C_MIER_ALIE (1 << 11) /* Arbitration Lost Interrupt Enable Bit */ +#define LPI2C_MIER_FEIE (1 << 12) /* FIFO Error Interrupt Enable Bit */ +#define LPI2C_MIER_PLTIE (1 << 13) /* Pin Low Timeout Interrupt Enable Bit */ +#define LPI2C_MIER_DMIE (1 << 14) /* Data Match Interrupt Enable Bit */ + /* Bits 31-15 Reserved */ + +/* LPI2C Master DMA Enable Register */ + +#define LPI2C_MDER_TDDE (1 << 0) /* Transmit Data DMA Enable Bit */ +#define LPI2C_MDER_RDDE (1 << 1) /* Transmit Data DMA Enable Bit */ + /* Bits 31-2 Reserved */ + +/* LPI2C Master Config Register 0 */ + +#define LPI2C_MCFG0_HREN (1 << 0) /* Host Request Enable Bit */ +#define LPI2C_MCFG0_HRPOL (1 << 1) /* Host Request Polarity Bit */ +#define LPI2C_MCFG0_HRSEL (1 << 2) /* Host Request Select Bit */ + /* Bits 7-3 Reserved */ +#define LPI2C_MCFG0_CIRFIFO (1 << 8) /* Circular FIFO Enable Bit */ +#define LPI2C_MCFG0_RDMO (1 << 9) /* Receive Data Match Only Bit */ + /* Bits 31-10 Reserved */ + +/* LPI2C Master Config Register 1 */ + +#define LPI2C_MCFGR1_PRESCALE_MASK (7 << 0) /* Clock Prescaler Bit Mask */ +#define LPI2C_MCFGR1_PRESCALE(n) ((n) & LPI2C_MCFGR1_PRESCALE_MASK) +# define LPI2C_MCFGR1_PRESCALE_1 (0) +# define LPI2C_MCFGR1_PRESCALE_2 (1) +# define LPI2C_MCFGR1_PRESCALE_4 (2) +# define LPI2C_MCFGR1_PRESCALE_8 (3) +# define LPI2C_MCFGR1_PRESCALE_16 (4) +# define LPI2C_MCFGR1_PRESCALE_32 (5) +# define LPI2C_MCFGR1_PRESCALE_64 (6) +# define LPI2C_MCFGR1_PRESCALE_128 (7) +#define LPI2C_MCFGR1_AUTOSTOP (1 << 8) /* Automatic STOP Generation Bit */ +#define LPI2C_MCFGR1_IGNACK (1 << 9) /* Ignore NACK Bit */ +#define LPI2C_MCFGR1_TIMECFG (1 << 10) /* Timeout Configuration Bit */ + /* Bits 15-11 Reserved */ +#define LPI2C_MCFGR1_MATCFG_SHIFT (16) +#define LPI2C_MCFGR1_MATCFG_MASK (7 << LPI2C_MCFGR1_MATCFG_SHIFT) /* Match Configuration Bit Mask */ +#define LPI2C_MCFGR1_MATCFG(n) (((n) << LPI2C_MCFGR1_MATCFG_SHIFT) & LPI2C_MCFGR1_MATCFG_MASK) +# define LPI2C_MCFGR1_MATCFG_DISABLE (0 << LPI2C_MCFGR1_MATCFG_SHIFT) + /* LPI2C_MCFG1_MATCFG = 001b Reserved */ +# define LPI2C_MCFGR1_MATCFG2 (2 << LPI2C_MCFGR1_MATCFG_SHIFT) +# define LPI2C_MCFGR1_MATCFG3 (3 << LPI2C_MCFGR1_MATCFG_SHIFT) +# define LPI2C_MCFGR1_MATCFG4 (4 << LPI2C_MCFGR1_MATCFG_SHIFT) +# define LPI2C_MCFGR1_MATCFG5 (5 << LPI2C_MCFGR1_MATCFG_SHIFT) +# define LPI2C_MCFGR1_MATCFG6 (6 << LPI2C_MCFGR1_MATCFG_SHIFT) +# define LPI2C_MCFGR1_MATCFG7 (7 << LPI2C_MCFGR1_MATCFG_SHIFT) + /* Bits 23-19 Reserved */ +#define LPI2C_MCFGR1_PINCFG_SHIFT (24) +#define LPI2C_MCFGR1_PINCFG_MASK (7 << LPI2C_MCFGR1_PINCFG_SHIFT) /* Pin Configuration Bit Mask */ +#define LPI2C_MCFGR1_PINCFG(n) (((n) << LPI2C_MCFGR1_PINCFG_SHIFT) & LPI2C_MCFGR1_PINCFG_MASK) +# define LPI2C_MCFGR1_PINCFG0 (0 << LPI2C_MCFGR1_PINCFG_SHIFT) +# define LPI2C_MCFGR1_PINCFG1 (1 << LPI2C_MCFGR1_PINCFG_SHIFT) +# define LPI2C_MCFGR1_PINCFG2 (2 << LPI2C_MCFGR1_PINCFG_SHIFT) +# define LPI2C_MCFGR1_PINCFG3 (3 << LPI2C_MCFGR1_PINCFG_SHIFT) +# define LPI2C_MCFGR1_PINCFG4 (4 << LPI2C_MCFGR1_PINCFG_SHIFT) +# define LPI2C_MCFGR1_PINCFG5 (5 << LPI2C_MCFGR1_PINCFG_SHIFT) +# define LPI2C_MCFGR1_PINCFG6 (6 << LPI2C_MCFGR1_PINCFG_SHIFT) +# define LPI2C_MCFGR1_PINCFG7 (7 << LPI2C_MCFGR1_PINCFG_SHIFT) + /* Bits 31-27 Reserved */ + +/* LPI2C Master Config Register 2 */ + +#define LPI2C_MCFG2_BUSIDLE_MASK (0xfff << 0) /* Bus Idle Timeout Period in Clock Cycles */ +#define LPI2C_MCFG2_BUSIDLE_DISABLE (0) +#define LPI2C_MCFG2_BUSIDLE(n) ((n) & LPI2C_MCFG2_BUSIDLE_MASK) + /* Bits 15-12 Reserved */ +#define LPI2C_MCFG2_FILTSCL_SHIFT (16) +#define LPI2C_MCFG2_FILTSCL_MASK (15 << LPI2C_MCFG2_FILTSCL_SHIFT) /* Glitch Filter SCL */ +#define LPI2C_MCFG2_FILTSCL_DISABLE (0 << LPI2C_MCFG2_FILTSCL_SHIFT) +#define LPI2C_MCFG2_FILTSCL_CYCLES(n) (((n) << LPI2C_MCFG2_FILTSCL_SHIFT) & LPI2C_MCFG2_FILTSCL_MASK) + /* Bits 23-20 Reserved */ +#define LPI2C_MCFG2_FILTSDA_SHIFT (24) +#define LPI2C_MCFG2_FILTSDA_MASK (15 << LPI2C_MCFG2_FILTSDA_SHIFT) /* Glitch Filter SDA */ +#define LPI2C_MCFG2_FILTSDA_DISABLE (0 << LPI2C_MCFG2_FILTSDA_SHIFT) +#define LPI2C_MCFG2_FILTSDA_CYCLES(n) (((n) << LPI2C_MCFG2_FILTSDA_SHIFT) & LPI2C_MCFG2_FILTSDA_MASK) + /* Bits 31-28 Reserved */ + +/* LPI2C Master Config Register 3 */ + + /* Bits 7-0 Reserved */ +#define LPI2C_MCFG3_PINLOW_SHIFT (8) +#define LPI2C_MCFG3_PINLOW_MASK (0xfff << LPI2C_MCFG3_PINLOW_SHIFT) /* Configure The Pin Low Timeout in Clock Cycles */ +#define LPI2C_MCFG3_PINLOW_CYCLES(n) (((n) << LPI2C_MCFG3_PINLOW_SHIFT) & LPI2C_MCFG3_PINLOW_MASK) + /* Bits 31-20 Reserved */ + +/* LPI2C Master Data Match Register */ + +#define LPI2C_MDMR_MATCH0_SHIFT (0) +#define LPI2C_MDMR_MATCH0_MASK (0xff << LPI2C_MDMR_MATCH0_SHIFT) /* Match 0 Value */ +#define LPI2C_MDMR_MATCH0(n) (((n) << LPI2C_MDMR_MATCH0_SHIFT) & LPI2C_MDMR_MATCH0_MASK) + /* Bits 15-8 Reserved */ +#define LPI2C_MDMR_MATCH1_SHIFT (16) +#define LPI2C_MDMR_MATCH1_MASK (0xff << LPI2C_MDMR_MATCH1_SHIFT) /* Match 1 Value */ +#define LPI2C_MDMR_MATCH1(n) (((n) << LPI2C_MDMR_MATCH1_SHIFT) & LPI2C_MDMR_MATCH1_MASK) + /* Bits 31-24 Reserved */ + +/* LPI2C Master Clock Configuration Register 0 */ + +#define LPI2C_MCCR0_CLKLO_SHIFT (0) +#define LPI2C_MCCR0_CLKLO_MASK (0x3f << LPI2C_MCCR0_CLKLO_SHIFT) /* Clock Low Period */ +#define LPI2C_MCCR0_CLKLO(n) (((n) << LPI2C_MCCR0_CLKLO_SHIFT) & LPI2C_MCCR0_CLKLO_MASK) + /* Bits 7-6 Reserved */ +#define LPI2C_MCCR0_CLKHI_SHIFT (8) +#define LPI2C_MCCR0_CLKHI_MASK (0x3f << LPI2C_MCCR0_CLKHI_SHIFT) /* Clock High Period */ +#define LPI2C_MCCR0_CLKHI(n) (((n) << LPI2C_MCCR0_CLKHI_SHIFT) & LPI2C_MCCR0_CLKHI_MASK) + /* Bits 15-14 Reserved */ +#define LPI2C_MCCR0_SETHOLD_SHIFT (16) +#define LPI2C_MCCR0_SETHOLD_MASK (0x3f << LPI2C_MCCR0_SETHOLD_SHIFT) /* Setup Hold Delay */ +#define LPI2C_MCCR0_SETHOLD(n) (((n) << LPI2C_MCCR0_SETHOLD_SHIFT) & LPI2C_MCCR0_SETHOLD_MASK) + /* Bits 23-22 Reserved */ +#define LPI2C_MCCR0_DATAVD_SHIFT (24) +#define LPI2C_MCCR0_DATAVD_MASK (0x3f << LPI2C_MCCR0_DATAVD_SHIFT) /* Setup Hold Delay */ +#define LPI2C_MCCR0_DATAVD(n) (((n) << LPI2C_MCCR0_DATAVD_SHIFT) & LPI2C_MCCR0_DATAVD_MASK) + /* Bits 31-30 Reserved */ + +/* LPI2C Master Clock Configuration Register 1 */ + +#define LPI2C_MCCR1_CLKLO_SHIFT (0) +#define LPI2C_MCCR1_CLKLO_MASK (0x3f << LPI2C_MCCR1_CLKLO_SHIFT) /* Clock Low Period */ +#define LPI2C_MCCR1_CLKLO(n) (((n) << LPI2C_MCCR1_CLKLO_SHIFT) & LPI2C_MCCR1_CLKLO_MASK) + /* Bits 7-6 Reserved */ +#define LPI2C_MCCR1_CLKHI_SHIFT (8) +#define LPI2C_MCCR1_CLKHI_MASK (0x3f << LPI2C_MCCR1_CLKHI_SHIFT) /* Clock High Period */ +#define LPI2C_MCCR1_CLKHI(n) (((n) << LPI2C_MCCR1_CLKHI_SHIFT) & LPI2C_MCCR1_CLKHI_MASK) + /* Bits 15-14 Reserved */ +#define LPI2C_MCCR1_SETHOLD_SHIFT (16) +#define LPI2C_MCCR1_SETHOLD_MASK (0x3f << LPI2C_MCCR1_SETHOLD_SHIFT) /* Setup Hold Delay */ +#define LPI2C_MCCR1_SETHOLD(n) (((n) << LPI2C_MCCR1_SETHOLD_SHIFT) & LPI2C_MCCR1_SETHOLD_MASK) + + /* Bits 23-22 Reserved */ +#define LPI2C_MCCR1_DATAVD_SHIFT (24) +#define LPI2C_MCCR1_DATAVD_MASK (0x3f << LPI2C_MCCR1_DATAVD_SHIFT) /* Setup Hold Delay */ +#define LPI2C_MCCR1_DATAVD(n) (((n) << LPI2C_MCCR1_DATAVD_SHIFT) & LPI2C_MCCR1_DATAVD_MASK) + + /* Bits 31-30 Reserved */ + +/* LPI2C Master FIFO Control Register */ + +#define LPI2C_MFCR_TXWATER_SHIFT (0) +#define LPI2C_MFCR_TXWATER_MASK (3 << LPI2C_MFCR_TXWATER_SHIFT) /* Transmit FIFO Watermark*/ + +#define LPI2C_MFCR_TXWATER(n) (((n) << LPI2C_MFCR_TXWATER_SHIFT) & LPI2C_MFCR_TXWATER_MASK) /* Transmit FIFO Watermark */ + + /* Bits 15-2 Reserved */ +#define LPI2C_MFCR_RXWATER_SHIFT (16) +#define LPI2C_MFCR_RXWATER_MASK (3 << LPI2C_MFCR_RXWATER_SHIFT) /* Receive FIFO Watermark */ + +#define LPI2C_MFCR_RXWATER(n) (((n) << LPI2C_MFCR_RXWATER_SHIFT) & LPI2C_MFCR_RXWATER_MASK) /* Transmit FIFO Watermark */ + + /* Bits 31-18 Reserved */ + +/* LPI2C Master FIFO Status Register */ + +#define LPI2C_MFSR_TXCOUNT_SHIFT (0) +#define LPI2C_MFSR_TXCOUNT_MASK (3 << LPI2C_MFSR_TXCOUNT_SHIFT) /* Transmit FIFO Count */ + + /* Bits 15-2 Reserved */ +#define LPI2C_MFSR_RXCOUNT_SHIFT (16) +#define LPI2C_MFSR_RXCOUNT_MASK (3 << LPI2C_MFSR_RXCOUNT_SHIFT) /* Receive FIFO Count */ + + /* Bits 31-18 Reserved */ + +/* LPI2C Master Transmit Data Register */ + +#define LPI2C_MTDR_DATA_SHIFT (0) +#define LPI2C_MTDR_DATA_MASK (0xff << LPI2C_MTDR_DATA_SHIFT) /* Transmit Data */ +#define LPI2C_MTDR_DATA(n) ((n) & LPI2C_MTDR_DATA_MASK) +#define LPI2C_MTDR_CMD_SHIFT (8) +#define LPI2C_MTDR_CMD_MASK (7 << LPI2C_MTDR_CMD_SHIFT) /* Command Data */ +#define LPI2C_MTDR_CMD(n) (((n) << LPI2C_MTDR_CMD_SHIFT) & LPI2C_MTDR_CMD_MASK) +# define LPI2C_MTDR_CMD_TXD (0 << LPI2C_MTDR_CMD_SHIFT) +# define LPI2C_MTDR_CMD_RXD (1 << LPI2C_MTDR_CMD_SHIFT) +# define LPI2C_MTDR_CMD_STOP (2 << LPI2C_MTDR_CMD_SHIFT) +# define LPI2C_MTDR_CMD_RXD_DISC (3 << LPI2C_MTDR_CMD_SHIFT) +# define LPI2C_MTDR_CMD_START (4 << LPI2C_MTDR_CMD_SHIFT) +# define LPI2C_MTDR_CMD_START_NACK (5 << LPI2C_MTDR_CMD_SHIFT) +# define LPI2C_MTDR_CMD_START_HI (6 << LPI2C_MTDR_CMD_SHIFT) +# define LPI2C_MTDR_CMD_START_HI_NACK (7 << LPI2C_MTDR_CMD_SHIFT) + + /* Bits 31-11 Reserved */ + +/* LPI2C Master Receive Data Register */ + +#define LPI2C_MRDR_DATA_SHIFT (0) +#define LPI2C_MRDR_DATA_MASK (0xff << LPI2C_MRDR_DATA_SHIFT) /* Receive Data */ + + /* Bits 13-8 Reserved */ +#define LPI2C_MRDR_RXEMPTY_SHIFT (14) +#define LPI2C_MRDR_RXEMPTY_MASK (1 << LPI2C_MRDR_RXEMPTY_SHIFT) /* Rx Empty */ + + /* Bits 31-15 Reserved */ + +/* LPI2C Slave Control Register */ + +#define LPI2C_SCR_SEN (1 << 0) /* Slave Enable Bit */ +#define LPI2C_SCR_RST (1 << 1) /* Software Reset Bit */ + /* Bits 3-2 Reserved */ +#define LPI2C_SCR_FILTEN (1 << 4) /* Filter Enable Bit */ +#define LPI2C_SCR_FILTDZ (1 << 5) /* Filter Doze Enable Bit */ + /* Bits 7-4 Reserved */ +#define LPI2C_SCR_RTF (1 << 8) /* Reset Transmit FIFO Bit */ +#define LPI2C_SCR_RRF (1 << 9) /* Reset Receive FIFO Bit */ + /* Bits 31-10 Reserved */ + +/* LPI2C Slave Status Register */ + +#define LPI2C_SSR_TDF (1 << 0) /* Transmit Data Flag Bit */ +#define LPI2C_SSR_RDF (1 << 1) /* Receive Data Flag Bit */ +#define LPI2C_SSR_AVF (1 << 2) /* Address Valid Flag Bit */ +#define LPI2C_SSR_TAF (1 << 3) /* Transmit ACK Flag Bit */ + /* Bits 7-4 Reserved */ +#define LPI2C_SSR_RSF (1 << 8) /* Repeated Start Flag Bit */ +#define LPI2C_SSR_SDF (1 << 9) /* STOP Detect Flag Bit */ +#define LPI2C_SSR_BEF (1 << 10) /* Bit Error Flag Bit */ +#define LPI2C_SSR_FEF (1 << 11) /* FIFO Error Flag Bit */ +#define LPI2C_SSR_AM0F (1 << 12) /* Address Match 0 Flag Bit */ +#define LPI2C_SSR_AM1F (1 << 13) /* Address Match 1 Flag Bit */ +#define LPI2C_SSR_GCF (1 << 14) /* General Call Flag Bit */ +#define LPI2C_SSR_SARF (1 << 15) /* SMBus Alert Response Flag Bit */ + /* Bits 23-16 Reserved */ +#define LPI2C_MSR_SBF (1 << 24) /* Slave Busy Flag Bit */ +#define LPI2C_MSR_BBF (1 << 25) /* Bus Busy Flag Bit */ + /* Bits 31-26 Reserved */ + +/* LPI2C Slave Interrupt Enable Register */ + +#define LPI2C_SIER_TDIE (1 << 0) /* Transmit Data Interrupt Enable Bit */ +#define LPI2C_SIER_RDIE (1 << 1) /* Receive Data Interrupt Enable Bit */ +#define LPI2C_SIER_AVIE (1 << 2) /* Address Valid Interrupt Enable Bit */ +#define LPI2C_SIER_TAIE (1 << 3) /* Transmit ACK Interrupt Enable Bit */ + /* Bits 7-4 Reserved */ +#define LPI2C_SIER_RSIE (1 << 8) /* Repeated Start Interrupt Enable Bit */ +#define LPI2C_SIER_SDIE (1 << 9) /* STOP Detect Interrupt Enable Bit */ +#define LPI2C_SIER_BEIE (1 << 10) /* Bit Error Interrupt Enable Bit */ +#define LPI2C_SIER_FEIE (1 << 11) /* FIFO Error Interrupt Enable Bit */ +#define LPI2C_SIER_AM0IE (1 << 12) /* Address Match 0 Interrupt Enable Bit */ +#define LPI2C_SIER_AM1IE (1 << 13) /* Address Match 1 Interrupt Enable Bit */ +#define LPI2C_SIER_GCIE (1 << 14) /* General Call Interrupt Enable Bit */ +#define LPI2C_SIER_SARIE (1 << 15) /* SMBus Alert Response Interrupt Enable Bit */ + /* Bits 31-16 Reserved */ + +/* LPI2C Slave DMA Enable Register */ + +#define LPI2C_SDER_TDDE (1 << 0) /* Transmit Data DMA Enable Bit */ +#define LPI2C_SDER_RDDE (1 << 1) /* Transmit Data DMA Enable Bit */ +#define LPI2C_SDER_AVDE (1 << 2) /* Address Valid DMA Enable Bit */ + /* Bits 31-3 Reserved */ + +/* LPI2C Slave Configuration Register 1 */ + +#define LPI2C_SCFGR1_ADRSTALL (1 << 0) /* Address SCL Stall */ +#define LPI2C_SCFGR1_RXSTALL (1 << 1) /* RX SCL Stall */ +#define LPI2C_SCFGR1_TXSTALL (1 << 2) /* TX Data SCL Stall */ +#define LPI2C_SCFGR1_ACKSTALL (1 << 3) /* ACK SCL Stall */ + /* Bits 7-4 Reserved */ +#define LPI2C_SCFGR1_GCEN (1 << 8) /* General Call Enable */ +#define LPI2C_SCFGR1_SAEN (1 << 9) /* SMBus Alert Enable */ +#define LPI2C_SCFGR1_TXCFG (1 << 10) /* Transmit Flag Configuration */ +#define LPI2C_SCFGR1_RXCFG (1 << 11) /* Receive Data Configuration */ +#define LPI2C_SCFGR1_IFNACK (1 << 12) /* Ignore NACK */ +#define LPI2C_SCFGR1_HSMEN (1 << 13) /* High Speed Mode Enable */ + /* Bits 15-14 Reserved */ +#define LPI2C_SCFG1_ADDRCFG_SHIFT (16) +#define LPI2C_SCFG1_ADDRCFG_MASK (7 << LPI2C_SCFG1_ADDRCFG_SHIFT) /* Address Configuration Bit Mask */ +#define LPI2C_SCFG1_ADDRCFG(n) (((n) << LPI2C_SCFG1_ADDRCFG_SHIFT) & LPI2C_SCFG1_ADDRCFG_MASK) +# define LPI2C_SCFG1_ADDRCFG0 (0 << LPI2C_SCFG1_ADDRCFG_SHIFT) +# define LPI2C_SCFG1_ADDRCFG1 (2 << LPI2C_SCFG1_ADDRCFG_SHIFT) +# define LPI2C_SCFG1_ADDRCFG2 (2 << LPI2C_SCFG1_ADDRCFG_SHIFT) +# define LPI2C_SCFG1_ADDRCFG3 (3 << LPI2C_SCFG1_ADDRCFG_SHIFT) +# define LPI2C_SCFG1_ADDRCFG4 (4 << LPI2C_SCFG1_ADDRCFG_SHIFT) +# define LPI2C_SCFG1_ADDRCFG5 (5 << LPI2C_SCFG1_ADDRCFG_SHIFT) +# define LPI2C_SCFG1_ADDRCFG6 (6 << LPI2C_SCFG1_ADDRCFG_SHIFT) +# define LPI2C_SCFG1_ADDRCFG7 (7 << LPI2C_SCFG1_ADDRCFG_SHIFT) + /* Bits 31-19 Reserved */ + +/* LPI2C Slave Configuration Register 2 */ + +#define LPI2C_SCFG2_CLKHOLD_MASK (15 << 0) /* Clock Hold Time */ +#define LPI2C_SCFG2_CLKHOLD(n) ((n) & LPI2C_SCFG2_CLKHOLD_MASK) + /* Bits 7-4 Reserved */ +#define LPI2C_SCFG2_DATAVD_SHIFT (8) +#define LPI2C_SCFG2_DATAVD_MASK (0x3f << LPI2C_SCFG2_DATAVD_SHIFT) /* Data Valid Delay */ +#define LPI2C_SCFG2_DATAVD(n) (((n) << LPI2C_SCFG2_DATAVD_SHIFT) & LPI2C_SCFG2_DATAVD_MASK) + /* Bits 15-14 Reserved */ +#define LPI2C_SCFG2_FILTSCL_SHIFT (16) +#define LPI2C_SCFG2_FILTSCL_MASK (15 << LPI2C_SCFG2_FILTSCL_SHIFT) /* Glitch Filter SCL */ +#define LPI2C_SCFG2_FILTSCL_DISABLE (0 << LPI2C_SCFG2_FILTSCL_SHIFT) +#define LPI2C_SCFG2_FILTSCL_CYCLES(n) (((n) << LPI2C_SCFG2_FILTSCL_SHIFT) & LPI2C_SCFG2_FILTSCL_MASK) + /* Bits 23-20 Reserved */ +#define LPI2C_SCFG2_FILTSDA_SHIFT (24) +#define LPI2C_SCFG2_FILTSDA_MASK (15 << LPI2C_SCFG2_FILTSDA_SHIFT) /* Glitch Filter SDA */ +#define LPI2C_SCFG2_FILTSDA_DISABLE (0 << LPI2C_SCFG2_FILTSDA_SHIFT) +#define LPI2C_SCFG2_FILTSDA_CYCLES(n) (((n) << LPI2C_SCFG2_FILTSDA_SHIFT) & LPI2C_SCFG2_FILTSDA_MASK) + /* Bits 31-28 Reserved */ + +/* LPI2C Slave Address Match Register */ + + /* Bit 0 Reserved */ +#define LPI2C_SAMR_ADDR0_SHIFT (1) +#define LPI2C_SAMR_ADDR0_MASK (0x3ff << LPI2C_SAMR_ADDR0_SHIFT) /* Address 0 Value */ +#define LPI2C_SAMR_ADDR0(n) (((n) << LPI2C_SAMR_ADDR0_SHIFT) & LPI2C_SAMR_ADDR0_MASK) + /* Bits 16-11 Reserved */ +#define LPI2C_SAMR_ADDR1_SHIFT (17) +#define LPI2C_SAMR_ADDR1_MASK (0x3ff << LPI2C_SAMR_ADDR1_SHIFT) /* Address 1 Value */ +#define LPI2C_SAMR_ADDR1(n) (((n) << LPI2C_SAMR_ADDR1_SHIFT) & LPI2C_SAMR_ADDR1_MASK) + /* Bits 31-27 Reserved */ + +/* LPI2C Slave Address Status Register */ + +#define LPI2C_SASR_RADDR_MASK (0x7ff << 0) /* Received Address */ + +/* Bits 16-11 + * Reserved + */ + +#define LPI2C_SASR_ANV (1 << 14) /* Address Not Valid */ + /* Bits 31-15 Reserved */ + +/* LPI2C Slave Transmit ACK Register */ + +#define LPI2C_STAR_TXNACK (1 << 0) /* Transmit NACK */ + /* Bits 31-1 Reserved */ + +/* LPI2C Slave Transmit Data Register */ + +#define LPI2C_STDR_DATA_SHIFT (0) +#define LPI2C_STDR_DATA_MASK (0xff << LPI2C_STDR_DATA_SHIFT) /* Transmit Data */ +#define LPI2C_STDR_DATA(n) (((n) << LPI2C_STDR_DATA_SHIFT) & LPI2C_STDR_DATA_MASK) + /* Bits 31-8 Reserved */ + +/* LPI2C Slave Receive Data Register */ + +#define LPI2C_SRDR_DATA_SHIFT (0) +#define LPI2C_SRDR_DATA_MASK (0xff << LPI2C_SRDR_DATA_SHIFT) /* Receive Data */ +#define LPI2C_SRDR_DATA(n) (((n) << LPI2C_SRDR_DATA_SHIFT) & LPI2C_SRDR_DATA_MASK) + /* Bits 13-8 Reserved */ +#define LPI2C_STAR_SOF (1 << 14) /* RX Empty */ +#define LPI2C_STAR_RXEMPTY (1 << 15) /* Start Of Frame */ + /* Bits 31-16 Reserved */ + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPI2C_H_ */ diff --git a/arch/arm64/src/imx9/hardware/imx9_lpit.h b/arch/arm64/src/imx9/hardware/imx9_lpit.h new file mode 100644 index 0000000000000..5d1d32b494396 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_lpit.h @@ -0,0 +1,125 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_lpit.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPIT_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPIT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define IMX9_LPIT_VERID_OFFSET 0x0000 /* Version ID */ +#define IMX9_LPIT_PARAM_OFFSET 0x0004 /* Parameter */ +#define IMX9_LPIT_MCR_OFFSET 0x0008 /* Module Control */ +#define IMX9_LPIT_MSR_OFFSET 0x000c /* Module Status Register */ +#define IMX9_LPIT_MIER_OFFSET 0x0010 /* Moduel Interrupt Enable */ +#define IMX9_LPIT_SETTEN_OFFSET 0x0014 /* Set Timer Enable */ +#define IMX9_LPIT_CLRTEN_OFFSET 0x0018 /* Clear Timer Enable */ +#define IMX9_LPIT_TVAL0_OFFSET 0x0020 /* Timer Channel 0 Value */ +#define IMX9_LPIT_CVAL0_OFFSET 0x0024 /* Current Timer Channel 0 Value */ +#define IMX9_LPIT_TCTRL0_OFFSET 0x0028 /* Timer Channel 0 Control */ +#define IMX9_LPIT_TVAL1_OFFSET 0x0030 /* Timer Channel 1 Value */ +#define IMX9_LPIT_CVAL1_OFFSET 0x0034 /* Current Timer Channel 1 Value */ +#define IMX9_LPIT_TCTRL1_OFFSET 0x0048 /* Timer Channel 1 Control */ +#define IMX9_LPIT_TVAL2_OFFSET 0x0040 /* Timer Channel 2 Value */ +#define IMX9_LPIT_CVAL2_OFFSET 0x0044 /* Current Timer Channel 2 Value */ +#define IMX9_LPIT_TCTRL2_OFFSET 0x0048 /* Timer Channel 2 Control */ +#define IMX9_LPIT_TVAL3_OFFSET 0x0050 /* Timer Channel 3 Value */ +#define IMX9_LPIT_CVAL3_OFFSET 0x0054 /* Current Timer Channel 3 Value */ +#define IMX9_LPIT_TCTRL3_OFFSET 0x0058 /* Timer Channel 3 Control */ + +/* Register access */ + +#define LPIT_VERID(n) ((n) + IMX9_LPIT_VERID_OFFSET) +#define LPIT_PARAM(n) ((n) + IMX9_LPIT_PARAM_OFFSET) +#define LPIT_MCR(n) ((n) + IMX9_LPIT_MCR_OFFSET) +#define LPIT_MSR(n) ((n) + IMX9_LPIT_MSR_OFFSET) +#define LPIT_MIER(n) ((n) + IMX9_LPIT_MIER_OFFSET) +#define LPIT_SETTEN(n) ((n) + IMX9_LPIT_SETTEN_OFFSET) +#define LPIT_CLRTEN(n) ((n) + IMX9_LPIT_CLRTEN_OFFSET) +#define LPIT_TVAL0(n) ((n) + IMX9_LPIT_TVAL0_OFFSET) +#define LPIT_CVAL0(n) ((n) + IMX9_LPIT_CVAL0_OFFSET) +#define LPIT_TCTRL0(n) ((n) + IMX9_LPIT_TCTRL0_OFFSET) +#define LPIT_TVAL1(n) ((n) + IMX9_LPIT_TVAL1_OFFSET) +#define LPIT_CVAL1(n) ((n) + IMX9_LPIT_CVAL1_OFFSET) +#define LPIT_TCTRL1(n) ((n) + IMX9_LPIT_TCTRL1_OFFSET) +#define LPIT_TVAL2(n) ((n) + IMX9_LPIT_TVAL2_OFFSET) +#define LPIT_CVAL2(n) ((n) + IMX9_LPIT_CVAL2_OFFSET) +#define LPIT_TCTRL2(n) ((n) + IMX9_LPIT_TCTRL2_OFFSET) +#define LPIT_TVAL3(n) ((n) + IMX9_LPIT_TVAL3_OFFSET) +#define LPIT_CVAL3(n) ((n) + IMX9_LPIT_CVAL3_OFFSET) +#define LPIT_TCTRL3(n) ((n) + IMX9_LPIT_TCTRL3_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +#define LPIT_PARAM_EXT_TRIG_SHIFT (8) /* Bit[15:8]: Number of External Trigger Inputs */ +#define LPIT_PARAM_EXT_TRIG_MASK (0xff << LPIT_PARAM_EXT_TRIG_SHIFT) + +#define LPIT_PARAM_CHANNEL_SHIFT (0) /* Bit[7:0]: Number of Timer Channels */ +#define LPIT_PARAM_CHANNEL_MASK (0xff << LPIT_PARAM_CHANNEL_SHIFT) + +#define LPIT_MCR_DBG_EN (1 << 3) /* Stop Timer when in Debug Mode */ +#define LPIT_MCR_DOZE_EN (1 << 2) /* DOZE Mode Enable */ +#define LPIT_MCR_SW_RST (1 << 1) /* Software Reset Bit */ +#define LPIT_MCR_M_CEN (1 << 0) /* Module Clock Enable */ + +#define LPIT_MSR_TIF3 (1 << 3) /* Channel 3 Timer Interrupt Flag */ +#define LPIT_MSR_TIF2 (1 << 2) /* Channel 2 Timer Interrupt Flag */ +#define LPIT_MSR_TIF1 (1 << 1) /* Channel 1 Timer Interrupt Flag */ +#define LPIT_MSR_TIF0 (1 << 0) /* Channel 0 Timer Interrupt Flag */ + +#define LPIT_MIER_TIE3 (1 << 3) /* Channel 3 Timer Interrupt Enable */ +#define LPIT_MIER_TIE2 (1 << 2) /* Channel 2 Timer Interrupt Enable */ +#define LPIT_MIER_TIE1 (1 << 1) /* Channel 1 Timer Interrupt Enable */ +#define LPIT_MIER_TIE0 (1 << 0) /* Channel 0 Timer Interrupt Enable */ + +#define LPIT_TCTRL_TRG_SEL_SHIFT (27) /* Bit[27:24]: Trigger Select */ +#define LPIT_TCTRL_TRG_SEL_MASK (0xf << LPIT_TCTRL_TRG_SEL_SHIFT) +#define LPIT_TCTRL_TRG_SEL_CHAN0 (0 << LPIT_TCTRL_TRG_SEL_SHIFT) +#define LPIT_TCTRL_TRG_SEL_CHAN1 (1 << LPIT_TCTRL_TRG_SEL_SHIFT) +#define LPIT_TCTRL_TRG_SEL_CHAN2 (2 << LPIT_TCTRL_TRG_SEL_SHIFT) +#define LPIT_TCTRL_TRG_SEL_CHAN3 (3 << LPIT_TCTRL_TRG_SEL_SHIFT) + +#define LPIT_TCTRL_TRG_SRC_SHIFT (23) /* Bit23: Trigger Source */ +#define LPIT_TCTRL_TRG_SRC_MASK (1 << LPIT_TCTRL_TRG_SRC_SHIFT) +#define LPIT_TCTRL_TRG_SRC_EXTER (0 << LPIT_TCTRL_TRG_SRC_SHIFT) /* external */ +#define LPIT_TCTRL_TRG_SRC_INTER (1 << LPIT_TCTRL_TRG_SRC_SHIFT) /* internal */ + +#define LPIT_TCTRL_TROT (1 << 18) /* Timer Reload On Trigger */ +#define LPIT_TCTRL_TSOI (1 << 17) /* Timer Stop On Interrupt */ +#define LPIT_TCTRL_TSOT (1 << 16) /* Timer Start On Trigger */ + +#define LPIT_TCTRL_MODE_SHIFT (2) +#define LPIT_TCTRL_MODE_MASK (3 << LPIT_TCTRL_MODE_SHIFT) +#define LPIT_TCTRL_MODE_32PC (0 << LPIT_TCTRL_MODE_SHIFT) /* 32 Bit periodic Counter */ +#define LPIT_TCTRL_MODE_D16PC (1 << LPIT_TCTRL_MODE_SHIFT) /* Dual 16-bit periodic Counter */ +#define LPIT_TCTRL_MODE_32TA (2 << LPIT_TCTRL_MODE_SHIFT) /* 32 bit Trigger Accumulator */ +#define LPIT_TCTRL_MODE_32TIC (3 << LPIT_TCTRL_MODE_SHIFT) /* 32 bit Trigger Input Capture */ + +#define LPIT_TCTRL_CHAIN (1 << 1) /* Chain Channel */ +#define LPIT_TCTRL_T_EN (1 << 0) /* Timer Enable */ + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPIT_H */ diff --git a/arch/arm64/src/imx9/hardware/imx9_lpspi.h b/arch/arm64/src/imx9/hardware/imx9_lpspi.h new file mode 100644 index 0000000000000..06f7b02dc5227 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_lpspi.h @@ -0,0 +1,351 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_lpspi.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPSPI_H_ +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPSPI_H_ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define IMX9_LPSPI_VERID_OFFSET (0x0000) /* Version ID Register (VERID) */ +#define IMX9_LPSPI_PARAM_OFFSET (0x0004) /* Parameter Register (PARAM) */ +#define IMX9_LPSPI_CR_OFFSET (0x0010) /* Control Register (CR) */ +#define IMX9_LPSPI_SR_OFFSET (0x0014) /* Status Register (SR) */ +#define IMX9_LPSPI_IER_OFFSET (0x0018) /* Interrupt Enable Register (IER) */ +#define IMX9_LPSPI_DER_OFFSET (0x001c) /* DMA Enable Register (DER) */ +#define IMX9_LPSPI_CFGR0_OFFSET (0x0020) /* Configuration Register 0 (CFGR0) */ +#define IMX9_LPSPI_CFGR1_OFFSET (0x0024) /* Configuration Register 1 (CFGR1) */ +#define IMX9_LPSPI_DMR0_OFFSET (0x0030) /* Data Match Register 0 (DMR0) */ +#define IMX9_LPSPI_DMR1_OFFSET (0x0034) /* Data Match Register 1 (DMR1) */ +#define IMX9_LPSPI_CCR_OFFSET (0x0040) /* Clock Configuration Register (CCR) */ +#define IMX9_LPSPI_CCR1_OFFSET (0x0044) /* Clock Configuration Register 1 (CCR1) */ +#define IMX9_LPSPI_FCR_OFFSET (0x0058) /* FIFO Control Register (FCR) */ +#define IMX9_LPSPI_FSR_OFFSET (0x005c) /* FIFO Status Register (FSR) */ +#define IMX9_LPSPI_TCR_OFFSET (0x0060) /* Transmit Command Register (TCR) */ +#define IMX9_LPSPI_TDR_OFFSET (0x0064) /* Transmit Data Register (TDR) */ +#define IMX9_LPSPI_RSR_OFFSET (0x0070) /* Receive Status Register (RSR) */ +#define IMX9_LPSPI_RDR_OFFSET (0x0074) /* Receive Data Register (RDR) */ +#define IMX9_LPSPI_RDROR_OFFSET (0x0078) /* Receive Data Read Only Register (RDROR) */ +#define IMX9_LPSPI_TCBR_OFFSET (0x03fc) /* Transmit Command Burst Register (TCBR) */ + +#define IMX9_LPSPI_TDBR_OFFSET(n) (0x0400 + ((n) << 2)) /* Transmit Data Burst Register n=0..127 (TDBRn) */ +#define IMX9_LPSPI_RDBR_OFFSET(n) (0x0600 + ((n) << 2)) /* Receive Data Burst Register n=0..127 (RDBRn) */ + +/* Register addresses *******************************************************/ + +#define IMX9_LPSPI0_VERID(n) ((n) + IMX9_LPSPI_VERID_OFFSET) +#define IMX9_LPSPI0_PARAM(n) ((n) + IMX9_LPSPI_PARAM_OFFSET) +#define IMX9_LPSPI0_CR(n) ((n) + IMX9_LPSPI_CR_OFFSET) +#define IMX9_LPSPI0_SR(n) ((n) + IMX9_LPSPI_SR_OFFSET) +#define IMX9_LPSPI0_IER(n) ((n) + IMX9_LPSPI_IER_OFFSET) +#define IMX9_LPSPI0_DER(n) ((n) + IMX9_LPSPI_DER_OFFSET) +#define IMX9_LPSPI0_CFGR0(n) ((n) + IMX9_LPSPI_CFGR0_OFFSET) +#define IMX9_LPSPI0_CFGR1(n) ((n) + IMX9_LPSPI_CFGR1_OFFSET) +#define IMX9_LPSPI0_DMR0(n) ((n) + IMX9_LPSPI_DMR0_OFFSET) +#define IMX9_LPSPI0_DMR1(n) ((n) + IMX9_LPSPI_DMR1_OFFSET) +#define IMX9_LPSPI0_CCR(n) ((n) + IMX9_LPSPI_CCR_OFFSET) +#define IMX9_LPSPI0_CCR1(n) ((n) + IMX9_LPSPI_CCR1_OFFSET) +#define IMX9_LPSPI0_FCR(n) ((n) + IMX9_LPSPI_FCR_OFFSET) +#define IMX9_LPSPI0_FSR(n) ((n) + IMX9_LPSPI_FSR_OFFSET) +#define IMX9_LPSPI0_TCR(n) ((n) + IMX9_LPSPI_TCR_OFFSET) +#define IMX9_LPSPI0_TDR(n) ((n) + IMX9_LPSPI_TDR_OFFSET) +#define IMX9_LPSPI0_RSR(n) ((n) + IMX9_LPSPI_RSR_OFFSET) +#define IMX9_LPSPI0_RDR(n) ((n) + IMX9_LPSPI_RDR_OFFSET) +#define IMX9_LPSPI0_RDROR(n) ((n) + IMX9_LPSPI_RDROR_OFFSET) +#define IMX9_LPSPI0_TCBR(n) ((n) + IMX9_LPSPI_TCBR_OFFSET) +#define IMX9_LPSPI0_TDBR(n,v) ((n) + IMX9_LPSPI_TDBR_OFFSET(v)) +#define IMX9_LPSPI0_RDBR(n,v) ((n) + IMX9_LPSPI_RDBR_OFFSET(v)) + +/* Register bit definitions *************************************************/ + +/* Version ID Register (VERID) */ + +#define LPSPI_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Module Identification Number (FEATURE) */ +#define LPSPI_VERID_FEATURE_MASK (0xffff << LPSPI_VERID_FEATURE_SHIFT) +#define LPSPI_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number (MINOR) */ +#define LPSPI_VERID_MINOR_MASK (0xff << LPSPI_VERID_MINOR_SHIFT) +#define LPSPI_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number (MAJOR) */ +#define LPSPI_VERID_MAJOR_MASK (0xff << LPSPI_VERID_MAJOR_SHIFT) + +/* Parameter Register (PARAM) */ + +#define LPSPI_PARAM_TXFIFO_SHIFT (0) /* Bits 0-7: Transmit FIFO Size (TXFIFO) */ +#define LPSPI_PARAM_TXFIFO_MASK (0xff << LPSPI_PARAM_TXFIFO_SHIFT) +#define LPSPI_PARAM_RXFIFO_SHIFT (8) /* Bits 8-15: Receive FIFO Size (RXFIFO) */ +#define LPSPI_PARAM_RXFIFO_MASK (0xff << LPSPI_PARAM_RXFIFO_SHIFT) +#define LPSPI_PARAM_PCSNUM_SHIFT (16) /* Bits 16-23: PCS Number (PCSNUM) */ +#define LPSPI_PARAM_PCSNUM_MASK (0xff << LPSPI_PARAM_PCSNUM_SHIFT) + /* Bits 24-31: Reserved */ + +/* Control Register (CR) */ + +#define LPSPI_CR_MEN (1 << 0) /* Bit 0: Module Enable (MEN) */ +#define LPSPI_CR_RST (1 << 1) /* Bit 1: Software Reset (RST) */ + /* Bit 2: Reserved */ +#define LPSPI_CR_DBGEN (1 << 3) /* Bit 3: Debug Enable (DBGEN) */ + /* Bits 4-7: Reserved */ +#define LPSPI_CR_RTF (1 << 8) /* Bit 8: Reset Transmit FIFO (RTF) */ +#define LPSPI_CR_RRF (1 << 9) /* Bit 9: Reset Receive FIFO (RRF) */ + /* Bits 10-31: Reserved */ + +/* Status Register (SR) */ + +#define LPSPI_SR_TDF (1 << 0) /* Bit 0: Transmit Data Flag (TDF) */ +#define LPSPI_SR_RDF (1 << 1) /* Bit 1: Receive Data Flag (RDF) */ + /* Bits 2-7: Reserved */ +#define LPSPI_SR_WCF (1 << 8) /* Bit 8: Word Complete Flag (WCF) */ +#define LPSPI_SR_FCF (1 << 9) /* Bit 9: Frame Complete Flag (FCF) */ +#define LPSPI_SR_TCF (1 << 10) /* Bit 10: Transfer Complete Flag (TCF) */ +#define LPSPI_SR_TEF (1 << 11) /* Bit 11: Transmit Error Flag (TEF) */ +#define LPSPI_SR_REF (1 << 12) /* Bit 12: Receive Error Flag (REF) */ +#define LPSPI_SR_DMF (1 << 13) /* Bit 13: Data Match Flag (DMF) */ + /* Bits 14-23: Reserved */ +#define LPSPI_SR_MBF (1 << 24) /* Bit 24: Module Busy Flag (MBF) */ + /* Bits 25-31: Reserved */ + +/* Interrupt Enable Register (IER) */ + +#define LPSPI_IER_TDIE (1 << 0) /* Bit 0: Transmit Data Interrupt Enable (TDIE) */ +#define LPSPI_IER_RDIE (1 << 1) /* Bit 1: Receive Data Interrupt Enable (RDIE) */ + /* Bits 2-7: Reserved */ +#define LPSPI_IER_WCIE (1 << 8) /* Bit 8: Word Complete Interrupt Enable (WCIE) */ +#define LPSPI_IER_FCIE (1 << 9) /* Bit 9: Frame Complete Interrupt Enable (FCIE) */ +#define LPSPI_IER_TCIE (1 << 10) /* Bit 10: Transfer Complete Interrupt Enable (TCIE) */ +#define LPSPI_IER_TEIE (1 << 11) /* Bit 11: Transmit Error Interrupt Enable (TEIE) */ +#define LPSPI_IER_REIE (1 << 12) /* Bit 12: Receive Error Interrupt Enable (REIE) */ +#define LPSPI_IER_DMIE (1 << 13) /* Bit 13: Data Match Interrupt Enable (DMIE) */ + /* Bits 14-31: Reserved */ + +/* DMA Enable Register (DER) */ + +#define LPSPI_DER_TDDE (1 << 0) /* Bit 0: Transmit Data DMA Enable (TDDE) */ +#define LPSPI_DER_RDDE (1 << 1) /* Bit 1: Receive Data DMA Enable (RDDE) */ + /* Bits 2-31: Reserved */ + +/* Configuration Register 0 (CFGR0) */ + +#define LPSPI_CFGR0_HREN (1 << 0) /* Bit 0: Host Request Enable (HREN) */ +#define LPSPI_CFGR0_HRPOL (1 << 1) /* Bit 1: Host Request Polarity (HRPOL) */ +# define LPSPI_CFGR0_HRPOL_HIGH (0 << 1) /* HREQ pin or input trigger is active high */ +# define LPSPI_CFGR0_HRPOL_LOW (1 << 1) /* HREQ pin or input trigger is active low */ +#define LPSPI_CFGR0_HRSEL (1 << 2) /* Bit 2: Host Request Select (HRSEL) */ +# define LPSPI_CFGR0_HRSEL_HREQ (0 << 2) /* Host request input is the LPSPI_HREQ pin */ +# define LPSPI_CFGR0_HRSEL_INTR (1 << 2) /* Host request input is the input trigger */ +#define LPSPI_CFGR0_HRDIR (1 << 3) /* Bit 3: Host Request Direction (HRDIR) */ +# define LPSPI_CFGR0_HRDIR_INPUT (0 << 3) /* HREQ pin is configured as input */ +# define LPSPI_CFGR0_HRDIR_OUTPUT (1 << 3) /* HREQ pin is configured as output */ + /* Bits 4-7: Reserved */ +#define LPSPI_CFGR0_CIRFIFO (1 << 8) /* Bit 8: Circular FIFO Enable (CIRCFIFO) */ +#define LPSPI_CFGR0_RDMO (1 << 9) /* Bit 9: Receive Data Match Only (RDMO) */ +# define LPSPI_CFGR0_RDMO_FIFO (0 << 9) /* Received data is stored in the receive FIFO as in normal operations */ +# define LPSPI_CFGR0_RDMO_DMF (1 << 9) /* Received data is discarded unless the Data Match Flag (DMF) is set */ + /* Bits 10-31: Reserved */ + +/* Configuration Register 1 (CFGR1) */ + +#define LPSPI_CFGR1_MASTER (1 << 0) /* Bit 0: Master Mode (MASTER) */ +#define LPSPI_CFGR1_SAMPLE (1 << 1) /* Bit 1: Sample Point (SAMPLE) */ +# define LPSPI_CFGR1_SAMPLE_SCK (0 << 1) /* Input data is sampled on SCK edge */ +# define LPSPI_CFGR1_SAMPLE_DELAY (1 << 1) /* Input data is sampled on delayed SCK edge */ +#define LPSPI_CFGR1_AUTOPCS (1 << 2) /* Bit 2: Automatic PCS (AUTOPCS) */ +#define LPSPI_CFGR1_NOSTALL (1 << 3) /* Bit 3: No Stall (NOSTALL) */ +#define LPSPI_CFGR1_PARTIAL (1 << 4) /* Bit 4: Partial Enable (PARTIAL) */ + /* Bits 5-7: Reserved */ +#define LPSPI_CFGR1_PCSPOL_SHIFT (8) /* Bits 8-15: Peripheral Chip Select Polarity (PCSPOL) */ +#define LPSPI_CFGR1_PCSPOL_MASK (0xff << LPSPI_CFGR1_PCSPOL_SHIFT) +# define LPSPI_CFGR1_PCSPOL_LOW(n) (0 << (LPSPI_CFGR1_PCSPOL_SHIFT + (n))) /* The Peripheral Chip Select PCS[n] pin is active low */ +# define LPSPI_CFGR1_PCSPOL_HIGH(n) (1 << (LPSPI_CFGR1_PCSPOL_SHIFT + (n))) /* The Peripheral Chip Select PCS[n] pin is active high */ + +#define LPSPI_CFGR1_MATCFG_SHIFT (16) /* Bits 16-18: Match Configuration (MATCFG) */ +#define LPSPI_CFGR1_MATCFG_MASK (0x07 << LPSPI_CFGR1_MATCFG_SHIFT) +#define LPSPI_CFGR1_MATCFG_DIS (0x00 << LPSPI_CFGR1_MATCFG_SHIFT) /* Match is disabled */ + + /* Bits 19-23: Reserved */ +#define LPSPI_CFGR1_PINCFG_SHIFT (24) /* Bits 24-25: Pin Configuration (PINCFG) */ +#define LPSPI_CFGR1_PINCFG_MASK (0x03 << LPSPI_CFGR1_PINCFG_SHIFT) +# define LPSPI_CFGR1_PINCFG_SIN_SOUT (0x00 << LPSPI_CFGR1_PINCFG_SHIFT) /* SIN is used for input data and SOUT is used for output data */ +# define LPSPI_CFGR1_PINCFG_SIN_SIN (0x01 << LPSPI_CFGR1_PINCFG_SHIFT) /* SIN is used for both input and output data */ +# define LPSPI_CFGR1_PINCFG_SOUT_SOUT (0x02 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for both input and output data */ +# define LPSPI_CFGR1_PINCFG_SOUT_SIN (0x03 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for input data and SIN is used for output data */ +# define LPSPI_CFGR1_PINCFG(n) ((n) << LPSPI_CFGR1_PINCFG_SHIFT) + +#define LPSPI_CFGR1_OUTCFG (1 << 26) /* Bit 26: Output Config (OUTCFG) */ +# define LPSPI_CFGR1_OUTCFG_RETAIN (0 << 26) /* Output data retains last value when chip select is negated */ +# define LPSPI_CFGR1_OUTCFG_TRISTATE (1 << 26) /* Output data is tristated when chip select is negated */ +#define LPSPI_CFGR1_PCSCFG_SHIFT (27) /* Bits 27-28: Peripheral Chip Select Configuration (PCSCFG) */ +#define LPSPI_CFGR1_PCSCFG_MASK (0x03 << LPSPI_CFGR1_PCSCFG_SHIFT) +# define LPSPI_CFGR1_PCSCFG_PCS (0x00 << LPSPI_CFGR1_PCSCFG_SHIFT) /* PCS[2:7] are configured for chip select function */ +# define LPSPI_CFGR1_PCSCFG_4BIT (0x01 << LPSPI_CFGR1_PCSCFG_SHIFT) /* PCS[2:3] are configured for half-duplex 4-bit transfers */ +# define LPSPI_CFGR1_PCSCFG_8BIT (0x03 << LPSPI_CFGR1_PCSCFG_SHIFT) /* PCS[2:7] are configured for half-duplex 4-bit and 8-bit transfers */ + + /* Bits 29-31: Reserved */ + +/* Data Match Register 0 (DMR0) */ + +#define LPSPI_DMR0_MATCH0_SHIFT (0) /* Bits 0-31: Match 0 Value (MATCH0) */ +#define LPSPI_DMR0_MATCH0_MASK (0xffffffff << LPSPI_DMR0_MATCH0_SHIFT) + +/* Data Match Register 0 (DMR1) */ + +#define LPSPI_DMR1_MATCH1_SHIFT (0) /* Bits 0-31: Match 1 Value (MATCH1) */ +#define LPSPI_DMR1_MATCH1_MASK (0xffffffff << LPSPI_DMR1_MATCH1_SHIFT) + +/* Clock Configuration Register (CCR) */ + +#define LPSPI_CCR_SCKDIV_SHIFT (0) /* Bits 0-7: SCK Divider (SCKDIV) */ +#define LPSPI_CCR_SCKDIV_MASK (0xff << LPSPI_CCR_SCKDIV_SHIFT) +# define LPSPI_CCR_SCKDIV(n) (((uint32_t)(n) << LPSPI_CCR_SCKDIV_SHIFT) & LPSPI_CCR_SCKDIV_MASK) +#define LPSPI_CCR_DBT_SHIFT (8) /* Bits 8-15: Delay Between Transfers (DBT) */ +#define LPSPI_CCR_DBT_MASK (0xff << LPSPI_CCR_DBT_SHIFT) +# define LPSPI_CCR_DBT(n) (((uint32_t)(n) << LPSPI_CCR_DBT_SHIFT) & LPSPI_CCR_DBT_MASK) +#define LPSPI_CCR_PCSSCK_SHIFT (16) /* Bits 16-23: PCS-to-SCK Delay (PCSSCK) */ +#define LPSPI_CCR_PCSSCK_MASK (0xff << LPSPI_CCR_PCSSCK_SHIFT) +# define LPSPI_CCR_PCSSCK(n) (((uint32_t)(n) << LPSPI_CCR_PCSSCK_SHIFT) & LPSPI_CCR_PCSSCK_MASK) +#define LPSPI_CCR_SCKPCS_SHIFT (24) /* Bits 24-31: SCK-to-PCS Delay (SCKPCS) */ +#define LPSPI_CCR_SCKPCS_MASK (0xff << LPSPI_CCR_SCKPCS_SHIFT) +# define LPSPI_CCR_SCKPCS(n) (((uint32_t)(n) << LPSPI_CCR_SCKPCS_SHIFT) & LPSPI_CCR_SCKPCS_MASK) + +/* Clock Configuration Register 1 (CCR1) */ + +#define LPSPI_CCR1_SCKSET_SHIFT (0) /* Bits 0-7: SCK Setup (SCKSET) */ +#define LPSPI_CCR1_SCKSET_MASK (0xff << LPSPI_CCR1_SCKSET_SHIFT) +#define LPSPI_CCR1_SCKHLD_SHIFT (8) /* Bits 8-15: SCK Hold (SCKHLD) */ +#define LPSPI_CCR1_SCKHLD_MASK (0xff << LPSPI_CCR1_SCKHLD_SHIFT) +#define LPSPI_CCR1_PCSPCS_SHIFT (16) /* Bits 16-23: PCS to PCS Delay (PCSPCS) */ +#define LPSPI_CCR1_PCSPCS_MASK (0xff << LPSPI_CCR1_PCSPCS_SHIFT) +#define LPSPI_CCR1_SCKSCK_SHIFT (24) /* Bits 24-31: SCK Inter-Frame Delay (SCKSCK) */ +#define LPSPI_CCR1_SCKSCK_MASK (0xff << LPSPI_CCR1_SCKSCK_SHIFT) + +/* FIFO Control Register (FCR) */ + +#define LPSPI_FCR_TXWATER_SHIFT (0) /* Bits 0-1: Transmit FIFO Watermark (TXWATER) */ +#define LPSPI_FCR_TXWATER_MASK (0x03 << LPSPI_FCR_TXWATER_SHIFT) +# define LPSPI_FCR_TXWATER(n) ((uint32_t)(n) << LPSPI_FCR_TXWATER_SHIFT) + /* Bits 2-15: Reserved */ +#define LPSPI_FCR_RXWATER_SHIFT (16) /* Bits 16-17: Receive FIFO Watermark (RXWATER) */ +#define LPSPI_FCR_RXWATER_MASK (0x03 << LPSPI_FCR_RXWATER_SHIFT) +# define LPSPI_FCR_RXWATER(n) ((uint32_t)(n) << LPSPI_FCR_RXWATER_SHIFT) + /* Bits 18-31: Reserved */ + +/* FIFO Status Register (FSR) */ + +#define LPSPI_FSR_TXCOUNT_SHIFT (0) /* Bits 0-2: Transmit FIFO Count (TXCOUNT) */ +#define LPSPI_FSR_TXCOUNT_MASK (0x07 << LPSPI_FSR_TXCOUNT_SHIFT) + /* Bits 3-15: Reserved */ +#define LPSPI_FSR_RXCOUNT_SHIFT (16) /* Bits 16-18: Receive FIFO Count (RXCOUNT) */ +#define LPSPI_FSR_RXCOUNT_MASK (0x07 << LPSPI_FSR_RXCOUNT_SHIFT) + /* Bits 19-31: Reserved */ + +/* Transmit Command Register (TCR) */ + +#define LPSPI_TCR_FRAMESZ_SHIFT (0) /* Bits 0-11: Frame Size (FRAMESZ) */ +#define LPSPI_TCR_FRAMESZ_MASK (0x0fff << LPSPI_TCR_FRAMESZ_SHIFT) +# define LPSPI_TCR_FRAMESZ(n) ((uint32_t)(n) << LPSPI_TCR_FRAMESZ_SHIFT) + /* Bits 12-15: Reserved */ +#define LPSPI_TCR_WIDTH_SHIFT (16) /* Bits 16-17: Transfer Width (WIDTH) */ +#define LPSPI_TCR_WIDTH_MASK (0x03 << LPSPI_TCR_WIDTH_SHIFT) +# define LPSPI_TCR_WIDTH_1BIT (0x00 << LPSPI_TCR_WIDTH_SHIFT) /* 1 bit transfer */ +# define LPSPI_TCR_WIDTH_2BIT (0x01 << LPSPI_TCR_WIDTH_SHIFT) /* 2 bit transfer */ +# define LPSPI_TCR_WIDTH_4BIT (0x02 << LPSPI_TCR_WIDTH_SHIFT) /* 4 bit transfer */ +# define LPSPI_TCR_WIDTH_8BIT (0x03 << LPSPI_TCR_WIDTH_SHIFT) /* 8 bit transfer */ + +#define LPSPI_TCR_TXMSK (1 << 18) /* Bit 18: Transmit Data Mask (TXMSK) */ +#define LPSPI_TCR_RXMSK (1 << 19) /* Bit 19: Receive Data Mask (RXMSK) */ +#define LPSPI_TCR_CONTC (1 << 20) /* Bit 20: Continuing Command (CONTC) */ +#define LPSPI_TCR_CONT (1 << 21) /* Bit 21: Continuous Transfer (CONT) */ +#define LPSPI_TCR_BYSW (1 << 22) /* Bit 22: Byte Swap (BYSW) */ +#define LPSPI_TCR_LSBF (1 << 23) /* Bit 23: LSB First (LSBF) */ +# define LPSPI_TCR_MSBF (0 << 23) /* MSB First */ +#define LPSPI_TCR_PCS_SHIFT (24) /* Bits 24-26: Peripheral Chip Select (PCS) */ +#define LPSPI_TCR_PCS_MASK (0x07 << LPSPI_TCR_PCS_SHIFT) +# define LPSPI_TCR_PCS_0 (0x00 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[0] */ +# define LPSPI_TCR_PCS_1 (0x01 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[1] */ +# define LPSPI_TCR_PCS_2 (0x02 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[2] */ +# define LPSPI_TCR_PCS_3 (0x03 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[3] */ +# define LPSPI_TCR_PCS_4 (0x04 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[4] */ +# define LPSPI_TCR_PCS_5 (0x05 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[5] */ +# define LPSPI_TCR_PCS_6 (0x06 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[6] */ +# define LPSPI_TCR_PCS_7 (0x07 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[7] */ + +#define LPSPI_TCR_PRESCALE_SHIFT (27) /* Bits 27-29: Prescaler Value (PRESCALE) */ +#define LPSPI_TCR_PRESCALE_MASK (0x07 << LPSPI_TCR_PRESCALE_SHIFT) +# define LPSPI_TCR_PRESCALE_DIV1 (0x00 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 1 */ +# define LPSPI_TCR_PRESCALE_DIV2 (0x01 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 2 */ +# define LPSPI_TCR_PRESCALE_DIV4 (0x02 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 4 */ +# define LPSPI_TCR_PRESCALE_DIV8 (0x03 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 8 */ +# define LPSPI_TCR_PRESCALE_DIV16 (0x04 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 16 */ +# define LPSPI_TCR_PRESCALE_DIV32 (0x05 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 32 */ +# define LPSPI_TCR_PRESCALE_DIV64 (0x06 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 64 */ +# define LPSPI_TCR_PRESCALE_DIV128 (0x07 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 128 */ +# define LPSPI_TCR_PRESCALE(n) ((n) << LPSPI_TCR_PRESCALE_SHIFT) + +#define LPSPI_TCR_CPHA (1 << 30) /* Bit 30: Clock Phase (CPHA) */ +# define LPSPI_TCR_CPHA_CAPTURED (0 << 30) /* Data is captured on the leading edge of SCK and changed on the following edge of SCK */ +# define LPSPI_TCR_CPHA_CHANGED (1 << 30) /* Data is changed on the leading edge of SCK and captured on the following edge of SCK */ +#define LPSPI_TCR_CPOL (1 << 31) /* Bit 31: Clock Polarity (CPOL) */ +# define LPSPI_TCR_CPOL_LOW (0 << 31) /* The inactive state value of SCK is low */ +# define LPSPI_TCR_CPOL_HIGH (1 << 31) /* The inactive state value of SCK is high */ + +/* Transmit Data Register (TDR) */ + +#define LPSPI_TDR_DATA_SHIFT (0) /* Bits 0-31: Transmit Data (DATA) */ +#define LPSPI_TDR_DATA_MASK (0xffffffff << LPSPI_TDR_DATA_SHIFT) + +/* Receive Status Register (RSR) */ + +#define LPSPI_RSR_SOF (1 << 0) /* Bit 0: Start Of Frame (SOF) */ +#define LPSPI_RSR_RXEMPTY (1 << 1) /* Bit 1: RX FIFO Empty (RXEMPTY) */ + /* Bits 2-31: Reserved */ + +/* Receive Data Register (RDR) */ + +#define LPSPI_RDR_DATA_SHIFT (0) /* Bits 0-31: Receive Data (DATA) */ +#define LPSPI_RDR_DATA_MASK (0xffffffff << LPSPI_RDR_DATA_SHIFT) + +/* Receive Data Read Only Register (RDROR) */ + +#define LPSPI_RDROR_DATA_SHIFT (0) /* Bits 0-31: Receive Data (DATA) */ +#define LPSPI_RDROR_DATA_MASK (0xffffffff << LPSPI_RDROR_DATA_SHIFT) + +/* Transmit Command Burst Register (TCBR) */ + +#define LPSPI_TCBR_DATA_SHIFT (0) /* Bits 0-31: Command Data (DATA) */ +#define LPSPI_TCBR_DATA_MASK (0xffffffff << LPSPI_TCBR_DATA_SHIFT) + +/* Transmit Data Burst Register (TDBR) */ + +#define LPSPI_TDBR_DATA_SHIFT (0) /* Bits 0-31: Data (DATA) */ +#define LPSPI_TDBR_DATA_MASK (0xffffffff << LPSPI_TDBR_DATA_SHIFT) + +/* Receive Data Burst Register (RDBR) */ + +#define LPSPI_RDBR_DATA_SHIFT (0) /* Bits 0-31: Data (DATA) */ +#define LPSPI_RDBR_DATA_MASK (0xffffffff << LPSPI_RDBR_DATA_SHIFT) + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPSPI_H_ */ diff --git a/arch/arm64/src/imx9/hardware/imx9_lptmr.h b/arch/arm64/src/imx9/hardware/imx9_lptmr.h new file mode 100644 index 0000000000000..73efc0d5a6961 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_lptmr.h @@ -0,0 +1,100 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_lptmr.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPTMR_H_ +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPTMR_H_ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define IMX9_LPTMR_CSR_OFFSET 0x0000 /* Control Status */ +#define IMX9_LPTMR_PSR_OFFSET 0x0004 /* Prescale */ +#define IMX9_LPTMR_CMR_OFFSET 0x0008 /* Compare */ +#define IMX9_LPTMR_CNR_OFFSET 0x000c /* Counter */ + +/* Register Address *********************************************************/ + +#define LPTMR_CSR(n) ((n) + IMX9_LPTMR_CSR_OFFSET) +#define LPTMR_PSR(n) ((n) + IMX9_LPTMR_PSR_OFFSET) +#define LPTMR_CMR(n) ((n) + IMX9_LPTMR_CMR_OFFSET) +#define LPTMR_CNR(n) ((n) + IMX9_LPTMR_CNR_OFFSET) + +/* Register Bitfield Definitions ********************************************/ + +#define LPTMR_CSR_TDRE (1 << 8) /* Timer DMA Request Enable */ +#define LPTMR_CSR_TCF (1 << 7) /* Timer Compare Flag */ +#define LPTMR_CSR_TIE (1 << 6) /* Timer Interrupt Enable */ + +#define LPTMR_CSR_TPS_SHIFT (4) /* Bit[5:4]: Timer Pin Select */ +#define LPTMR_CSR_TPS_MASK (3 << LPTMR_CSR_TPS_SHIFT) +#define LPTMR_CSR_TPS0 (0 << LPTMR_CSR_TPS_SHIFT) +#define LPTMR_CSR_TPS1 (1 << LPTMR_CSR_TPS_SHIFT) +#define LPTMR_CSR_TPS2 (2 << LPTMR_CSR_TPS_SHIFT) +#define LPTMR_CSR_TPS3 (3 << LPTMR_CSR_TPS_SHIFT) + +#define LPTMR_CSR_TPP (1 << 3) /* Timer Pin Polarity */ +#define LPTMR_CSR_TFC (1 << 2) /* Timer Free-Running Counter */ +#define LPTMR_CSR_TMS (1 << 1) /* Timer Mode Select */ +#define LPTMR_CSR_TEN (1 << 0) /* Timer Enable */ + +#define LPTMR_PSR_PRESCALE_SHIFT (3) /* Bit[6:3]: Prescale Value */ +#define LPTMR_PSR_PRESCALE_MASK (0xf << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV2 (0 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV4 (1 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV8 (2 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV16 (3 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV32 (4 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV64 (5 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV128 (6 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV256 (7 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV512 (8 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV1024 (9 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV2048 (10 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV4096 (11 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV8192 (12 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV16384 (13 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV32768 (14 << LPTMR_PSR_PRESCALE_SHIFT) +#define LPTMR_PSR_PRESCALE_DIV65536 (15 << LPTMR_PSR_PRESCALE_SHIFT) + +#define LPTMR_PSR_PBYP (1 << 2) /* Prescaler Bypass */ + +/* Clock sources (module clock / root clock) + * ipg_clk_irclk -> lptmrx_clk_root + * ipg_clk_1khz -> 32k_clk_root + * ipg_clk_32khz -> 32k_clk_root + * ipg_clk_ercl -> 32k_clk_root + */ + +#define LPTMR_PSR_PCS_SHIFT (0) /* Bit[1:0]: Prescaler Clock Select */ +#define LPTMR_PSR_PCS_MASK (3 << LPTMR_PSR_PCS_SHIFT) +#define LPTMR_PSR_PCS_REF_INT (0 << LPTMR_PSR_PCS_SHIFT) /* Internal reference clock */ +#define LPTMR_PSR_PCS_LPO (1 << LPTMR_PSR_PCS_SHIFT) /* LPO 1K Hz */ +#define LPTMR_PSR_PCS_RTC (2 << LPTMR_PSR_PCS_SHIFT) /* RTC 32768 Hz */ +#define LPTMR_PSR_PCS_REF_EXT (3 << LPTMR_PSR_PCS_SHIFT) /* External reference clock */ +# define LPTMR_PSR_PCS_SOSC LPTMR_PSR_PCS_RFOSC + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPTMR_H_ */ diff --git a/arch/arm64/src/imx9/hardware/imx9_lpuart.h b/arch/arm64/src/imx9/hardware/imx9_lpuart.h new file mode 100644 index 0000000000000..c688d5966a14e --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_lpuart.h @@ -0,0 +1,313 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_lpuart.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPUART_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPUART_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LPUART Register Offsets **************************************************/ + +#define IMX9_LPUART_VERID_OFFSET (0x00) /* Version ID Register (VERID) */ +#define IMX9_LPUART_PARAM_OFFSET (0x04) /* Parameter Register (PARAM) */ +#define IMX9_LPUART_GLOBAL_OFFSET (0x08) /* LPUART Global Register (GLOBAL) */ +#define IMX9_LPUART_PINCFG_OFFSET (0x0c) /* LPUART Pin Configuration Register (PINCFG) */ +#define IMX9_LPUART_BAUD_OFFSET (0x10) /* LPUART Baud Rate Register (BAUD) */ +#define IMX9_LPUART_STAT_OFFSET (0x14) /* LPUART Status Register (STAT) */ +#define IMX9_LPUART_CTRL_OFFSET (0x18) /* LPUART Control Register (CTRL) */ +#define IMX9_LPUART_DATA_OFFSET (0x1c) /* LPUART Data Register (DATA) */ +#define IMX9_LPUART_MATCH_OFFSET (0x20) /* LPUART Match Address Register (MATCH) */ +#define IMX9_LPUART_MODIR_OFFSET (0x24) /* LPUART Modem IrDA Register (MODIR) */ +#define IMX9_LPUART_FIFO_OFFSET (0x28) /* LPUART FIFO Register (FIFO) */ +#define IMX9_LPUART_WATER_OFFSET (0x2c) /* LPUART Watermark Register (WATER) */ +#define IMX9_LPUART_DATARO_OFFSET (0x30) /* Data read-only Register (DATARO) */ + +/* Register bit definitions *************************************************/ + +/* Version ID Register (VERID) */ + +#define LPUART_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Feature Identification Number (FEATURE) */ +#define LPUART_VERID_FEATURE_MASK (0xffff << LPUART_VERID_FEATURE_SHIFT) +# define LPUART_VERID_FEATURE_STD (1 << LPUART_VERID_FEATURE_SHIFT) /* Standard feature set */ +# define LPUART_VERID_FEATURE_MODEM (3 << LPUART_VERID_FEATURE_SHIFT) /* MODEM/IrDA support */ + +#define LPUART_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number (MINOR) */ +#define LPUART_VERID_MINOR_MASK (0xff << LPUART_VERID_MINOR_SHIFT) +#define LPUART_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number (MAJOR) */ +#define LPUART_VERID_MAJOR_MASK (0xff << LPUART_VERID_MAJOR_SHIFT) + +/* Parameter Register (PARAM) */ + +#define LPUART_PARAM_TXFIFO_SHIFT (0) /* Bits 0-7: Transmit FIFO Size (TXFIFO) */ +#define LPUART_PARAM_TXFIFO_MASK (0xff << LPUART_PARAM_TXFIFO_SHIFT) +#define LPUART_PARAM_RXFIFO_SHIFT (8) /* Bits 8-15: Receive FIFO Size (RXFIFO) */ +#define LPUART_PARAM_RXFIFO_MASK (0xff << LPUART_PARAM_RXFIFO_SHIFT) + /* Bits 16-31: Reserved */ + +/* LPUART Global Register (GLOBAL) */ + + /* Bit 0: Reserved */ +#define LPUART_GLOBAL_RST (1 << 1) /* Bit 1: Software Reset (RST) */ + /* Bits 2-31: Reserved */ + +/* LPUART Pin Configuration Register (PINCFG) */ + +#define LPUART_PINCFG_TRGSEL_SHIFT (0) /* Bits 0-1: Trigger Select (TRGSEL) */ +#define LPUART_PINCFG_TRGSEL_MASK (0x03 << LPUART_PINCFG_TRGSEL_SHIFT) +# define LPUART_PINCFG_TRGSEL_DISABLE (0 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger disabled */ +# define LPUART_PINCFG_TRGSEL_RXD (1 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of RXD pin */ +# define LPUART_PINCFG_TRGSEL_CTSB (2 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of CTS_B pin */ +# define LPUART_PINCFG_TRGSEL_TXDMOD (3 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used to modulate the TXD output */ + + /* Bits 2-31: Reserved */ + +/* LPUART Baud Rate Register (BAUD) */ + +#define LPUART_BAUD_SBR_SHIFT (0) /* Bits 0-12: Baud Rate Modulo Divisor (SBR) */ +#define LPUART_BAUD_SBR_MASK (0x1fff << LPUART_BAUD_SBR_SHIFT) +# define LPUART_BAUD_SBR(n) ((n) << LPUART_BAUD_SBR_SHIFT) +#define LPUART_BAUD_SBNS (1 << 13) /* Bit 13: Stop Bit Number Select (SBNS) */ +#define LPUART_BAUD_RXEDGIE (1 << 14) /* Bit 14: RX Input Active Edge Interrupt Enable (RXEDGIE) */ +#define LPUART_BAUD_LBKDIE (1 << 15) /* Bit 15: LIN Break Detect Interrupt Enable (LBKDIE) */ +#define LPUART_BAUD_RESYNCDIS (1 << 16) /* Bit 16: Resynchronization Disable (RESYNCDIS) */ +#define LPUART_BAUD_BOTHEDGE (1 << 17) /* Bit 17: Both Edge Sampling (BOTHEDGE) */ +#define LPUART_BAUD_MATCFG_SHIFT (18) /* Bits 18-19: Match Configuration (MATCFG) */ +#define LPUART_BAUD_MATCFG_MASK (0x03 << LPUART_BAUD_MATCFG_SHIFT) +# define LPUART_BAUD_MATCFG_ADDR (0 << LPUART_BAUD_MATCFG_SHIFT) /* Address Match Wakeup */ +# define LPUART_BAUD_MATCFG_IDLE (1 << LPUART_BAUD_MATCFG_SHIFT) /* Idle Match Wakeup */ +# define LPUART_BAUD_MATCFG_ONOFF (2 << LPUART_BAUD_MATCFG_SHIFT) /* Match On and Match Off */ +# define LPUART_BAUD_MATCFG_RWUENAB (3 << LPUART_BAUD_MATCFG_SHIFT) /* Enables RWU on Data Match and Match On/Off for transmitter CTS input */ + + /* Bit 20: Reserved */ +#define LPUART_BAUD_RDMAE (1 << 21) /* Bit 21: Receiver Full DMA Enable (RDMAE) */ + /* Bit 22: Reserved */ +#define LPUART_BAUD_TDMAE (1 << 23) /* Bit 23: Transmitter DMA Enable (TDMAE) */ +#define LPUART_BAUD_OSR_SHIFT (24) /* Bits 24-29: Oversampling Ratio (OSR) */ +#define LPUART_BAUD_OSR_MASK (0x1f << LPUART_BAUD_OSR_SHIFT) +# define LPUART_BAUD_OSR(n) (((n) - 1) << LPUART_BAUD_OSR_SHIFT) /* n=4..32 */ + +#define LPUART_BAUD_M10 (1 << 29) /* Bit 29: 10-bit Mode Select (M10) */ +#define LPUART_BAUD_MAEN2 (1 << 30) /* Bit 30: Match Address Mode Enable 2 (MAEN2) */ +#define LPUART_BAUD_MAEN1 (1 << 31) /* Bit 31: Match Address Mode Enable 1 (MAEN1) */ + +/* LPUART Status Register (STAT) */ + +#define LPUART_STAT_LBKFE (1 << 0) /* Bit 0: LIN Break Flag Enable (LBKFE) */ +#define LPUART_STAT_AME (1 << 1) /* Bit 1: Address Mark Enable (AME) */ + /* Bits 2-13: Reserved */ +#define LPUART_STAT_MA2F (1 << 14) /* Bit 14: Match 2 Flag (MA2F) */ +#define LPUART_STAT_MA1F (1 << 15) /* Bit 15: Match 1 Flag (MA1F) */ +#define LPUART_STAT_PF (1 << 16) /* Bit 16: Parity Error Flag (PF) */ +#define LPUART_STAT_FE (1 << 17) /* Bit 17: Framing Error Flag (FE) */ +#define LPUART_STAT_NF (1 << 18) /* Bit 18: Noise Flag (NF) */ +#define LPUART_STAT_OR (1 << 19) /* Bit 19: Receiver Overrun Flag (OR) */ +#define LPUART_STAT_IDLE (1 << 20) /* Bit 20: Idle Line Flag (IDLE) */ +#define LPUART_STAT_RDRF (1 << 21) /* Bit 21: Receive Data Register Full Flag (RDRF) */ +#define LPUART_STAT_TC (1 << 22) /* Bit 22: Transmission Complete Flag (TC) */ +#define LPUART_STAT_TDRE (1 << 23) /* Bit 23: Transmit Data Register Empty Flag (TDRE) */ +#define LPUART_STAT_RAF (1 << 24) /* Bit 24: Receiver Active Flag (RAF) */ +#define LPUART_STAT_LBKDE (1 << 25) /* Bit 25: LIN Break Detection Enable (LBKDE) */ +#define LPUART_STAT_BRK13 (1 << 26) /* Bit 26: Break Character Generation Length (BRK13) */ +#define LPUART_STAT_RWUID (1 << 27) /* Bit 27: Receive Wake Up Idle Detect (RWUID) */ +#define LPUART_STAT_RXINV (1 << 28) /* Bit 28: Receive Data Inversion (RXINV) */ +#define LPUART_STAT_MSBF (1 << 29) /* Bit 29: MSB First (MSBF) */ +#define LPUART_STAT_RXEDGIF (1 << 30) /* Bit 30: RXD Pin Active Edge Interrupt Flag (RXEDGIF) */ +#define LPUART_STAT_LBKDIF (1 << 31) /* Bit 31: LIN Break Detect Interrupt Flag (LBKDIF) */ + +/* LPUART Control Register (CTRL) */ + +#define LPUART_CTRL_PT (1 << 0) /* Bit 0: Parity Type */ +# define LPUART_CTRL_PT_EVEN (0 << 0) /* Even parity */ +# define LPUART_CTRL_PT_ODD (1 << 0) /* Odd parity */ +#define LPUART_CTRL_PE (1 << 1) /* Bit 1: Parity Enable */ +#define LPUART_CTRL_ILT (1 << 2) /* Bit 2: Idle Line Type Select */ +#define LPUART_CTRL_WAKE (1 << 3) /* Bit 3: Receiver Wakeup Method Select */ +#define LPUART_CTRL_M (1 << 4) /* Bit 4: 9-Bit or 8-Bit Mode Select */ +#define LPUART_CTRL_RSRC (1 << 5) /* Bit 5: Receiver Source Select */ +#define LPUART_CTRL_DOZEEN (1 << 6) /* Bit 6: Doze Enable */ +#define LPUART_CTRL_LOOPS (1 << 7) /* Bit 7: Loop Mode Select */ +#define LPUART_CTRL_IDLECFG_SHIFT (8) /* Bits 8-10: Idle Configuration */ +#define LPUART_CTRL_IDLECFG_MASK (0x07 << LPUART_CTRL_IDLECFG_SHIFT) +# define LPUART_CTRL_IDLECFG_1 (0 << LPUART_CTRL_IDLECFG_SHIFT) /* 1 idle character */ +# define LPUART_CTRL_IDLECFG_2 (1 << LPUART_CTRL_IDLECFG_SHIFT) /* 2 idle characters */ +# define LPUART_CTRL_IDLECFG_4 (2 << LPUART_CTRL_IDLECFG_SHIFT) /* 4 idle characters */ +# define LPUART_CTRL_IDLECFG_8 (3 << LPUART_CTRL_IDLECFG_SHIFT) /* 8 idle characters */ +# define LPUART_CTRL_IDLECFG_16 (4 << LPUART_CTRL_IDLECFG_SHIFT) /* 6 idle characters */ +# define LPUART_CTRL_IDLECFG_32 (5 << LPUART_CTRL_IDLECFG_SHIFT) /* 32 idle characters */ +# define LPUART_CTRL_IDLECFG_64 (6 << LPUART_CTRL_IDLECFG_SHIFT) /* 64 idle characters */ +# define LPUART_CTRL_IDLECFG_128 (7 << LPUART_CTRL_IDLECFG_SHIFT) /* 128 idle characters */ + +#define LPUART_CTRL_M7 (1 << 11) /* Bit 11: 7-Bit Mode Select (M7) */ + /* Bits 12-13: Reserved */ +#define LPUART_CTRL_MA2IE (1 << 14) /* Bit 14: Match 2 Interrupt Enable (MA2IE) */ +#define LPUART_CTRL_MA1IE (1 << 15) /* Bit 15: Match 1 Interrupt Enable (MA1IE) */ +#define LPUART_CTRL_SBK (1 << 16) /* Bit 16: Send Break (SBK) */ +#define LPUART_CTRL_RWU (1 << 17) /* Bit 17: Receiver Wakeup Control (RWU) */ +#define LPUART_CTRL_RE (1 << 18) /* Bit 18: Receiver Enable (RE) */ +#define LPUART_CTRL_TE (1 << 19) /* Bit 19: Transmitter Enable (TE) */ +#define LPUART_CTRL_ILIE (1 << 20) /* Bit 20: Idle Line Interrupt Enable (ILIE) */ +#define LPUART_CTRL_RIE (1 << 21) /* Bit 21: Receiver Interrupt Enable (RIE) */ +#define LPUART_CTRL_TCIE (1 << 22) /* Bit 22: Transmission Complete Interrupt Enable (TCIE) */ +#define LPUART_CTRL_TIE (1 << 23) /* Bit 23: Transmit Interrupt Enable (TIE) */ +#define LPUART_CTRL_PEIE (1 << 24) /* Bit 24: Parity Error Interrupt Enable (PEIE) */ +#define LPUART_CTRL_FEIE (1 << 25) /* Bit 25: Framing Error Interrupt Enable (FEIE) */ +#define LPUART_CTRL_NEIE (1 << 26) /* Bit 26: Noise Error Interrupt Enable (NEIE) */ +#define LPUART_CTRL_ORIE (1 << 27) /* Bit 27: Overrun Interrupt Enable (ORIE) */ +#define LPUART_CTRL_TXINV (1 << 28) /* Bit 28: Transmit Data Inversion (TXINV) */ +#define LPUART_CTRL_TXDIR (1 << 29) /* Bit 29: TXD Pin Direction in Single-Wire Mode (TXDIR) */ +#define LPUART_CTRL_R9T8 (1 << 30) /* Bit 30: Receive Bit 9 / Transmit Bit 8 (R9T8) */ +#define LPUART_CTRL_R8T9 (1 << 31) /* Bit 31: Receive Bit 8 / Transmit Bit 9 (R8T9) */ + +#define LPUART_ALL_INTS (LPUART_CTRL_ORIE | LPUART_CTRL_NEIE | LPUART_CTRL_FEIE | \ + LPUART_CTRL_PEIE | LPUART_CTRL_TIE | LPUART_CTRL_TCIE | \ + LPUART_CTRL_RIE | LPUART_CTRL_ILIE | LPUART_CTRL_MA1IE | \ + LPUART_CTRL_MA2IE) + +/* LPUART Data Register (DATA) */ + +#define LPUART_DATA_SHIFT (0) /* Bits 0-9: Data bits 0-9 (DATA)*/ +#define LPUART_DATA_MASK (0x03ff << LPUART_DATA_SHIFT) +#define LPUART_DATA_LINBRK (1 << 10) /* Bit 10: LIN Break (LINBRK) */ +#define LPUART_DATA_STATUS_SHIFT (11) /* Bits 11-15: Status */ +#define LPUART_DATA_IDLINE (1 << 11) /* Bit 11: Idle Line (IDLINE) */ +#define LPUART_DATA_RXEMPT (1 << 12) /* Bit 12: Receive Buffer Empty (RXEMPT) */ +#define LPUART_DATA_FRETSC (1 << 13) /* Bit 13: Frame Error / Transmit Special Character (FRETSC) */ +#define LPUART_DATA_PARITYE (1 << 14) /* Bit 14: Parity Error (PARITYE) */ +#define LPUART_DATA_NOISY (1 << 15) /* Bit 15: Noisy Data Received (NOISY) */ + /* Bits 16-31: Reserved */ + +/* LPUART Match Address Register (MATCH) */ + +#define LPUART_MATCH_MA1_SHIFT (0) /* Bits 0-9: Match Address 1 (MA1) */ +#define LPUART_MATCH_MA1_MASK (0x03ff << LPUART_MATCH_MA1_SHIFT) +# define LPUART_MATCH_MA1(n) ((n) << LPUART_MATCH_MA1_SHIFT) + /* Bits 10-15: Reserved */ +#define LPUART_MATCH_MA2_SHIFT (16) /* Bits 16-25: Match Address 2 (MA2) */ +#define LPUART_MATCH_MA2_MASK (0x03ff << LPUART_MATCH_MA2_SHIFT) +# define LPUART_MATCH_MA2(n) ((n) << LPUART_MATCH_MA2_SHIFT) + /* Bits 26-31: Reserved */ + +/* LPUART Modem IrDA Register (MODIR) */ + +#define LPUART_MODIR_TXCTSE (1 << 0) /* Bit 0: Transmitter clear-to-send enable (TXCTSE) */ +#define LPUART_MODIR_TXRTSE (1 << 1) /* Bit 1: Transmitter request-to-send enable (TXRTSE) */ +#define LPUART_MODIR_TXRTSPOL (1 << 2) /* Bit 2: Transmitter request-to-send polarity (TXRTSPOL) */ +#define LPUART_MODIR_RXRTSE (1 << 3) /* Bit 3: Receiver request-to-send enable (RXRTSE) */ +#define LPUART_MODIR_TXCTSC (1 << 4) /* Bit 4: Transmit CTS Configuration (TXCTSC) */ +# define LPUART_MODIR_TXCTSC_START (0 << 4) /* CTS sampled at start of character */ +# define LPUART_MODIR_TXCTSC_IDLE (1 << 4) /* CTS sampled when transmitter idle */ +#define LPUART_MODIR_TXCTSSRC (1 << 5) /* Bit 5: Transmit CTS Source (TXCTSSRC) */ +# define LPUART_MODIR_TXCTSSRC_CTSB (0 << 5) /* CTS input is CTS_B pin */ +# define LPUART_MODIR_TXCTSSRC_RXMAT (1 << 5) /* CTS input is receiver address match result */ + /* Bits 6-7: Reserved */ +#define LPUART_MODIR_RTSWATER_SHIFT (8) /* Bits 8-9: Receive RTS Configuration (RTSWATER) */ +#define LPUART_MODIR_RTSWATER_MASK (0x03 << LPUART_MODIR_RTSWATER_SHIFT) +# define LPUART_MODIR_RTSWATER(n) ((n) << LPUART_MODIR_RTSWATER_SHIFT) + /* Bits 10-15: Reserved */ +#define LPUART_MODIR_TNP_SHIFT (16) /* Bits 16-17: Transmitter narrow pulse (TNP) */ +#define LPUART_MODIR_TNP_MASK (0x03 << LPUART_MODIR_TNP_SHIFT) +# define LPUART_MODIR_TNP(n) (((n) - 1) << LPUART_MODIR_TNP_SHIFT) /* n/OSR */ + +#define LPUART_MODIR_IREN (1 << 18) /* Bit 18: Infrared enable (IREN) */ + /* Bits 19-31: Reserved */ + +/* LPUART FIFO Register (FIFO) */ + +#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0) /* Bits 0-2: Receive FIFO Buffer Depth (RXFIFOSIZE) */ +#define LPUART_FIFO_RXFIFOSIZE_MASK (0x07 << LPUART_FIFO_RXFIFOSIZE_SHIFT) +# define LPUART_FIFO_RXFIFOSIZE_1 (0 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 1 dataword */ +# define LPUART_FIFO_RXFIFOSIZE_4 (1 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 4 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_8 (2 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 8 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_16 (3 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 16 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_32 (4 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 32 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_64 (5 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 64 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_128 (6 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 128 datawords */ +# define LPUART_FIFO_RXFIFOSIZE_256 (7 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 256 datawords */ + +#define LPUART_FIFO_RXFE (1 << 3) /* Bit 3: Receive FIFO Enable (RXFE) */ +#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4) /* Bits 4-6: Transmit FIFO Buffer Depth (TXFIFOSIZE) */ +#define LPUART_FIFO_TXFIFOSIZE_MASK (0x07 << LPUART_FIFO_TXFIFOSIZE_SHIFT) +# define LPUART_FIFO_TXFIFOSIZE_1 (0 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 1 dataword */ +# define LPUART_FIFO_TXFIFOSIZE_4 (1 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 4 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_8 (2 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 8 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_16 (3 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 16 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_32 (4 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 32 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_64 (5 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 64 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_128 (6 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 128 datawords */ +# define LPUART_FIFO_TXFIFOSIZE_256 (7 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 256 datawords */ + +#define LPUART_FIFO_TXFE (1 << 7) /* Bit 7: Transmit FIFO Enable (TXFE) */ +#define LPUART_FIFO_RXUFE (1 << 8) /* Bit 8: Receive FIFO Underflow Interrupt Enable (RXUFE) */ +#define LPUART_FIFO_TXOFE (1 << 9) /* Bit 9: Transmit FIFO Overflow Interrupt Enable (TXOFE) */ +#define LPUART_FIFO_RXIDEN_SHIFT (10) /* Bits 10-12: Receiver Idle Empty Enable (RXIDEN) */ +#define LPUART_FIFO_RXIDEN_MASK (0x07 << LPUART_FIFO_RXIDEN_SHIFT) +# define LPUART_FIFO_RXIDEN_DISABLE (0 << LPUART_FIFO_RXIDEN_SHIFT) /* Disable RDRF assertion when receiver is idle */ +# define LPUART_FIFO_RXIDEN_1 (1 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 1 character */ +# define LPUART_FIFO_RXIDEN_2 (2 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 2 characters */ +# define LPUART_FIFO_RXIDEN_4 (3 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 4 characters */ +# define LPUART_FIFO_RXIDEN_8 (4 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 8 characters */ +# define LPUART_FIFO_RXIDEN_16 (5 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 16 characters */ +# define LPUART_FIFO_RXIDEN_32 (6 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 32 characters */ +# define LPUART_FIFO_RXIDEN_64 (7 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 64 characters */ + + /* Bit 13: Reserved */ +#define LPUART_FIFO_RXFLUSH (1 << 14) /* Bit 14: Receive FIFO Flush (RXFLUSH) */ +#define LPUART_FIFO_TXFLUSH (1 << 15) /* Bit 15: Transmit FIFO Flush (TXFLUSH) */ +#define LPUART_FIFO_RXUF (1 << 16) /* Bit 16: Receiver FIFO Underflow Flag (RXUF) */ +#define LPUART_FIFO_TXOF (1 << 17) /* Bit 17: Transmitter FIFO Overflow Flag (TXOF) */ + /* Bits 18-21: Reserved */ +#define LPUART_FIFO_RXEMPT (1 << 22) /* Bit 22: Receive Buffer/FIFO Empty (RXEMPT) */ +#define LPUART_FIFO_TXEMPT (1 << 23) /* Bit 23: Transmit Buffer/FIFO Empty (TXEMPT) */ + /* Bits 24-31: Reserved */ + +/* LPUART Watermark Register (WATER) */ + +#define LPUART_WATER_TXWATER_SHIFT (0) /* Bits 0-1: Transmit Watermark (TXWATER) */ +#define LPUART_WATER_TXWATER_MASK (0x03 << LPUART_WATER_TXWATER_SHIFT) +# define LPUART_WATER_TXWATER(n) ((n) << LPUART_WATER_TXWATER_SHIFT) + /* Bits 2-7: Reserved */ +#define LPUART_WATER_TXCOUNT_SHIFT (8) /* Bits 8-10: Transmit Counter (TXCOUNT) */ +#define LPUART_WATER_TXCOUNT_MASK (0x07 << LPUART_WATER_TXCOUNT_SHIFT) +# define LPUART_WATER_TXCOUNT(n) ((n) << LPUART_WATER_TXCOUNT_SHIFT) + /* Bits 11-15: Reserved */ +#define LPUART_WATER_RXWATER_SHIFT (16) /* Bits 16-17: Receive Watermark (RXWATER) */ +#define LPUART_WATER_RXWATER_MASK (0x03 << LPUART_WATER_RXWATER_SHIFT) +# define LPUART_WATER_RXWATER(n) ((n) << LPUART_WATER_RXWATER_SHIFT) + /* Bits 18-23: Reserved */ +#define LPUART_WATER_RXCOUNT_SHIFT (24) /* Bits 24-26: Receive Counter (RXCOUNT) */ +#define LPUART_WATER_RXCOUNT_MASK (0x07 << LPUART_WATER_RXCOUNT_SHIFT) +# define LPUART_WATER_RXCOUNT(n) ((n) << LPUART_WATER_RXCOUNT_SHIFT) + /* Bits 27-31: Reserved */ + +/* Data read-only Register (DATARO) */ + +#define LPUART_DATARO_DATA_SHIFT (0) /* Bits 0-15: Receive Data (DATA) */ +#define LPUART_DATARO_DATA_MASK (0xffff << LPUART_DATARO_DATA_SHIFT) + /* Bits 16-31: Reserved */ + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_LPUART_H */ diff --git a/arch/arm64/src/imx9/hardware/imx9_memorymap.h b/arch/arm64/src/imx9/hardware/imx9_memorymap.h new file mode 100644 index 0000000000000..cf682d25a211b --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_memorymap.h @@ -0,0 +1,36 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_MEMORYMAP_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX93) +# include "hardware/imx93/imx93_memorymap.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_MEMORYMAP_H */ diff --git a/arch/arm64/src/imx9/hardware/imx9_pinmux.h b/arch/arm64/src/imx9/hardware/imx9_pinmux.h new file mode 100644 index 0000000000000..689485dff6db7 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_pinmux.h @@ -0,0 +1,36 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_pinmux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_PINMUX_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_PINMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX93) +# include "hardware/imx93/imx93_pinmux.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_PINMUX_H */ diff --git a/arch/arm64/src/imx9/hardware/imx9_tpm.h b/arch/arm64/src/imx9/hardware/imx9_tpm.h new file mode 100644 index 0000000000000..0b6c3b5dc84eb --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_tpm.h @@ -0,0 +1,206 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_tpm.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_TPM_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_TPM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define IMX9_TPM_VERID_OFFSET 0x0000 /* Version ID */ +#define IMX9_TPM_PARAM_OFFSET 0x0004 /* Parameter */ +#define IMX9_TPM_GLOBAL_OFFSET 0x0008 /* TPM Global */ +#define IMX9_TPM_SC_OFFSET 0x0010 /* Status and Control */ +#define IMX9_TPM_CNT_OFFSET 0x0014 /* Counter */ +#define IMX9_TPM_MOD_OFFSET 0x0018 /* Modulo */ +#define IMX9_TPM_STATUS_OFFSET 0x001c /* Capture and Compare Status */ +#define IMX9_TPM_CXSC_OFFSET(ch) (0x0020 + (ch) * 8) /* Channel Status and Control */ +#define IMX9_TPM_CXV_OFFSET(ch) (0x0024 + (ch) * 8) /* Channel Value */ +#define IMX9_TPM_C1SC_OFFSET 0x0028 /* Channel n Status and Control */ +#define IMX9_TPM_C1V_OFFSET 0x002c /* Channel n Value */ +#define IMX9_TPM_C2SC_OFFSET 0x0030 /* Channel n Status and Control */ +#define IMX9_TPM_C2V_OFFSET 0x0034 /* Channel n Value */ +#define IMX9_TPM_C3SC_OFFSET 0x0038 /* Channel n Status and Control */ +#define IMX9_TPM_C3V_OFFSET 0x003c /* Channel n Value */ +#define IMX9_TPM_COMBINE_OFFSET 0x0064 /* Combine Channel */ +#define IMX9_TPM_TRIG_OFFSET 0x006c /* Channel Trigger */ +#define IMX9_TPM_POL_OFFSET 0x0070 /* Channel Polarity */ +#define IMX9_TPM_FILTER_OFFSET 0x0078 /* Filter Control */ +#define IMX9_TPM_QDCTRL_OFFSET 0x0080 /* Quadrature Decoder Control and Status */ +#define IMX9_TPM_CONF_OFFSET 0x0084 /* Configuration */ + +/* Register Bitfield Definitions ********************************************/ + +/* PARAM */ + +#define TPM_PARAM_WIDTH_SHIFT (16) /* Bit[23:16]: Width of the counter and timer channels */ +#define TPM_PARAM_WIDTH_MASK (0xff << TPM_PARAM_WIDTH_SHIFT) + +#define TPM_PARAM_TRIG_SHIFT (8) /* Bit[15:8]: Number of triggers that TPM implements */ +#define TPM_PARAM_TRIG_MASK (0xff << LPIT_PARAM_TRIG_SHIFT) + +#define TPM_PARAM_CHAN_SHIFT (0) /* Bit[7:0]: Number of timer channels */ +#define TPM_PARAM_CHAN_MASK (0xff << TPM_PARAM_CHAN_SHIFT) + +/* GLOBAL */ + +#define TPM_GLOBAL_RST_SHIFT (1) /* Bit[1]: Software Reset */ +#define TPM_GLOBAL_RST_MASK (0x1 << TPM_GLOBAL_RST_SHIFT) + +#define TPM_GLOBAL_NOUPDATE_SHIFT (0) /* Bit[0]: Block updates to internal registers */ +#define TPM_GLOBAL_NOUPDATE_MASK (0x1 << TPM_GLOBAL_NOUPDATE_SHIFT) + +/* SC */ + +#define TPM_SC_DMA_SHIFT (8) /* Bit[8]: DMA Enable */ +#define TPM_SC_DMA_MASK (0x1 << TPM_SC_DMA_SHIFT) + +#define TPM_SC_TOF_SHIFT (7) /* Bit[7]: Timer Overflow Flag */ +#define TPM_SC_TOF_MASK (0x1 << TPM_SC_TOF_SHIFT) + +#define TPM_SC_TOIE_SHIFT (6) /* Bit[6]: Timer Overflow Interrupt Enable */ +#define TPM_SC_TOIE_MASK (0x1 << TPM_SC_TOIE_SHIFT) + +#define TPM_SC_CPWMS_SHIFT (5) /* Bit[5]: Center-Aligned PWM Select */ +#define TPM_SC_CPWMS_MASK (0x1 << TPM_SC_CPWMS_SHIFT) + +#define TPM_SC_CMOD_SHIFT (3) /* Bit[4:3]: Clock Mode Selection */ +#define TPM_SC_CMOD_MASK (0x3 << TPM_SC_CMOD_SHIFT) + +#define TPM_SC_PS_SHIFT (0) /* Bit[2:0]: Prescale Factor Selection */ +#define TPM_SC_PS_MASK (0x7 << TPM_SC_PS_SHIFT) + +/* STATUS */ + +#define TPM_STATUS_TOF_SHIFT (8) /* Bit[8]: Timer Overflow Flag */ +#define TPM_STATUS_TOF_MASK (0x1 << TPM_STATUS_TOF_SHIFT) + +#define TPM_STATUS_CH3F_SHIFT (3) /* Bit[3]: Channel 3 Flag */ +#define TPM_STATUS_CH3F_MASK (0x1 << TPM_STATUS_CH3F_SHIFT) + +#define TPM_STATUS_CH2F_SHIFT (2) /* Bit[2]: Channel 2 Flag */ +#define TPM_STATUS_CH2F_MASK (0x1 << TPM_STATUS_CH2F_SHIFT) + +#define TPM_STATUS_CH1F_SHIFT (1) /* Bit[1]: Channel 1 Flag */ +#define TPM_STATUS_CH1F_MASK (0x1 << TPM_STATUS_CH1F_SHIFT) + +#define TPM_STATUS_CH0F_SHIFT (0) /* Bit[0]: Channel 0 Flag */ +#define TPM_STATUS_CH0F_MASK (0x1 << TPM_STATUS_CH0F_SHIFT) + +/* C0SC - C3SC */ + +#define TPM_CXSC_CHF_SHIFT (7) /* Bit[7]: Channel Flag */ +#define TPM_CXSC_CHF_MASK (0x1 << TPM_CXSC_CHF_SHIFT) + +#define TPM_CXSC_CHIE_SHIFT (6) /* Bit[6]: Channel Interrupt Enable */ +#define TPM_CXSC_CHIE_MASK (0x1 << TPM_CXSC_CHIE_SHIFT) + +#define TPM_CXSC_MSB_SHIFT (5) /* Bit[5]: Channel Mode Select B */ +#define TPM_CXSC_MSB_MASK (0x1 << TPM_CXSC_MSB_SHIFT) + +#define TPM_CXSC_MSA_SHIFT (4) /* Bit[4]: Channel Mode Select A */ +#define TPM_CXSC_MSA_MASK (0x1 << TPM_CXSC_MSA_SHIFT) + +#define TPM_CXSC_ELSB_SHIFT (3) /* Bit[3]: Edge or Level Select B */ +#define TPM_CXSC_ELSB_MASK (0x1 << TPM_CXSC_ELSB_SHIFT) + +#define TPM_CXSC_ELSA_SHIFT (2) /* Bit[2]: Edge or Level Select A */ +#define TPM_CXSC_ELSA_MASK (0x1 << TPM_CXSC_ELSA_SHIFT) + +#define TPM_CXSC_DMA_SHIFT (0) /* Bit[0]: DMA Enable */ +#define TPM_CXSC_DMA_MASK (0x1 << TPM_CXSC_DMA_SHIFT) + +/* COMBINE */ + +#define TPM_COMBINE_COMSWAP1_SHIFT (9) /* Bit[9]: Combine Channels 2 and 3 Swap */ +#define TPM_COMBINE_COMSWAP1_MASK (0x1 << TPM_COMBINE_COMSWAP1_SHIFT) + +#define TPM_COMBINE_COMBINE1_SHIFT (8) /* Bit[8]: Combine Channels 2 and 3 */ +#define TPM_COMBINE_COMBINE1_MASK (0x1 << TPM_COMBINE_COMBINE1_SHIFT) + +#define TPM_COMBINE_COMSWAP0_SHIFT (1) /* Bit[1]: Combine Channel 0 and 1 Swap */ +#define TPM_COMBINE_COMSWAP0_MASK (0x1 << TPM_COMBINE_COMSWAP0_SHIFT) + +#define TPM_COMBINE_COMBINE0_SHIFT (0) /* Bit[0]: Combine Channels 0 and 1 */ +#define TPM_COMBINE_COMBINE0_MASK (0x1 << TPM_COMBINE_COMBINE0_SHIFT) + +/* TRIG */ + +#define TPM_TRIG_TRIGX_MASK(ch) (0x1 << (ch)) /* Channel trigger configure */ + +/* POL */ + +#define TPM_POL_POLX_MASK(ch) (0x1 < (ch)) /* Channel polarity active low */ + +/* FILTER */ + +#define TPM_FILTER_CHXFVAL_MASK(ch) (0xf << ((ch) * 4))) /* Channel filter value */ + +/* QDCTRL */ + +#define TPM_QDCTRL_QUADMODE_SHIFT (3) /* Bit[3]: Quadrature Decoder Mode */ +#define TPM_QDCTRL_QUADMODE_MASK (0x1 << TPM_QDCTRL_QUADMODE_SHIFT) + +#define TPM_QDCTRL_QUADIR_SHIFT (2) /* Bit[2]: Counter Direction */ +#define TPM_QDCTRL_QUADIR_MASK (0x1 << TPM_QDCTRL_QUADIR_SHIFT) + +#define TPM_QDCTRL_TOFDIR_SHIFT (1) /* Bit[1]: Timer Overflow Direction */ +#define TPM_QDCTRL_TOFDIR_MASK (0x1 << TPM_QDCTRL_TOFDIR_SHIFT) + +#define TPM_QDCTRL_QUADEN_SHIFT (0) /* Bit[0]: Quadrature Decoder Enable */ +#define TPM_QDCTRL_QUADEN_MASK (0x1 << TPM_QDCTRL_QUADEN_SHIFT) + +/* CONF */ + +#define TPM_CONF_TRGSEL_SHIFT (24) /* Bit[25:24]: Trigger Select */ +#define TPM_CONF_TRGSEL_MASK (0x3 << TPM_CONF_TRGSEL_SHIFT) + +#define TPM_CONF_TRGSRC_SHIFT (23) /* Bit[23]: Trigger Source select */ +#define TPM_CONF_TRGSRC_MASK (0x1 << TPM_CONF_TRGSRC_SHIFT) + +#define TPM_CONF_TRGPOL_SHIFT (22) /* Bit[22]: Trigger Polarity */ +#define TPM_CONF_TRGPOL_MASK (0x1 << TPM_CONF_TRGPOL_SHIFT) + +#define TPM_CONF_CPOT_SHIFT (19) /* Bit[19]: Counter Pause on Trigger */ +#define TPM_CONF_CPOT_MASK (0x1 << TPM_CONF_CPOT_SHIFT) + +#define TPM_CONF_CROT_SHIFT (18) /* Bit[18]: Counter Reload on Trigger */ +#define TPM_CONF_CROT_MASK (0x1 << TPM_CONF_CROT_SHIFT) + +#define TPM_CONF_CSOO_SHIFT (17) /* Bit[17]: Counter Stop on Overflow */ +#define TPM_CONF_CSOO_MASK (0x1 << TPM_CONF_CSOO_SHIFT) + +#define TPM_CONF_CSOT_SHIFT (16) /* Bit[16]: Counter Start on Trigger */ +#define TPM_CONF_CSOT_MASK (0x1 << TPM_CONF_CSOT_SHIFT) + +#define TPM_CONF_DBGMODE_SHIFT (6) /* Bit[7:6]: Debug Mode */ +#define TPM_CONF_DBGMODE_MASK (0x3 << TPM_CONF_DBGMODE_SHIFT) + +#define TPM_CONF_DOZEEN_SHIFT (5) /* Bit[5]: Doze Enable */ +#define TPM_CONF_DOZEEN_MASK (0x1 << TPM_CONF_DOZEEN_SHIFT) + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_TPM_H */ diff --git a/arch/arm64/src/imx9/hardware/imx9_usbotg.h b/arch/arm64/src/imx9/hardware/imx9_usbotg.h new file mode 100644 index 0000000000000..c59119e8dd9f5 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_usbotg.h @@ -0,0 +1,665 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_usbotg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_USBOTG_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_USBOTG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IMX9_EHCI_NRHPORT 1 + +#define IMX9_USBOTG_ID_OFFSET 0x000 /* Identification */ +#define IMX9_USBHOST_HWGENERAL_OFFSET 0x004 /* Hardware General */ +#define IMX9_USBHOST_HWHOST_OFFSET 0x008 /* Host Hardware Parameters */ +#define IMX9_USBHOST_HWDEVICE_OFFSET 0x00c /* Device Hardware Parameters */ +#define IMX9_USBHOST_HWTXBUF_OFFSET 0x010 /* TX Buffer Hardware Parameters */ +#define IMX9_USBHOST_HWRXBUF_OFFSET 0x014 /* RX Buffer Hardware Parameters */ +#define IMX9_USBHOST_GPTIMER0LD_OFFSET 0x080 /* General Purpose Timer #0 Load */ +#define IMX9_USBHOST_GPTIMER0CTRL_OFFSET 0x084 /* General Purpose Timer #0 Controller */ +#define IMX9_USBHOST_GPTIMER1LD_OFFSET 0x088 /* General Purpose Timer #1 Load */ +#define IMX9_USBHOST_GPTIMER1CTRL_OFFSET 0x08c /* General Purpose Timer #1 Controller */ +#define IMX9_USBHOST_SBUSCFG_OFFSET 0x090 /* System Bus Config */ + +/* Device/host capability registers */ + +#define IMX9_USBOTG_CAPLENGTH_OFFSET 0x100 /* Capability register length (8-bit) */ +#define IMX9_USBHOST_HCIVERSION_OFFSET 0x102 /* Host interface version number (16-bit) */ +#define IMX9_USBHOST_HCSPARAMS_OFFSET 0x104 /* Host controller structural parameters */ +#define IMX9_USBHOST_HCCPARAMS_OFFSET 0x108 /* Host controller capability parameters */ +#define IMX9_USBDEV_DCIVERSION_OFFSET 0x120 /* Device interface version number */ +#define IMX9_USBDEV_DCCPARAMS_OFFSET 0x124 /* Device controller capability parameters */ + +/* Device/host/OTG operational registers */ + +#define IMX9_USBOTG_USBCMD_OFFSET 0x140 /* USB command (both) */ +#define IMX9_USBOTG_USBSTS_OFFSET 0x144 /* USB status (both) */ +#define IMX9_USBOTG_USBINTR_OFFSET 0x148 /* USB interrupt enable (both) */ +#define IMX9_USBOTG_FRINDEX_OFFSET 0x14c /* USB frame index (both) */ +#define IMX9_USBOTG_DEVICEADDR_OFFSET 0x154 /* USB device address (device) */ +#define IMX9_USBOTG_ASYNCLISTADDR_OFFSET 0x158 /* Next asynchronous list address (host) */ +#define IMX9_USBOTG_ENDPOINTLIST_OFFSET 0x158 /* Address of endpoint list in memory (device) */ +#define IMX9_USBOTG_BURSTSIZE_OFFSET 0x160 /* Programmable burst size (both) */ +#define IMX9_USBOTG_TXFILLTUNING_OFFSET 0x164 /* Host transmit pre-buffer packet tuning (host) */ +#define IMX9_USBOTG_ENDPTNAK_OFFSET 0x178 /* Endpoint NAK (device) */ +#define IMX9_USBOTG_ENDPTNAKEN_OFFSET 0x17c /* Endpoint NAK Enable (device) */ +#define IMX9_USBOTG_CONFIGFLAG_OFFSET 0x180 /* Configured flag register (not used in lpc313x) */ +#define IMX9_USBOTG_PORTSC1_OFFSET 0x184 /* Port status/control 1 (both) */ +#define IMX9_USBOTG_OTGSC_OFFSET 0x1a4 /* OTG status and control (otg) */ +#define IMX9_USBOTG_USBMODE_OFFSET 0x1a8 /* USB device mode (both) */ + +#define IMX9_USBDEV_USBCMD_OFFSET 0x140 /* USB command (both) */ +#define IMX9_USBDEV_USBSTS_OFFSET 0x144 /* USB status (both) */ +#define IMX9_USBDEV_USBINTR_OFFSET 0x148 /* USB interrupt enable (both) */ +#define IMX9_USBDEV_FRINDEX_OFFSET 0x14c /* USB frame index (both) */ +#define IMX9_USBDEV_DEVICEADDR_OFFSET 0x154 /* USB device address (device) */ +#define IMX9_USBDEV_ENDPOINTLIST_OFFSET 0x158 /* Address of endpoint list in memory (device) */ +#define IMX9_USBDEV_BURSTSIZE_OFFSET 0x160 /* Programmable burst size (both) */ +#define IMX9_USBDEV_ENDPTNAK_OFFSET 0x178 /* Endpoint NAK (device) */ +#define IMX9_USBDEV_ENDPTNAKEN_OFFSET 0x17c /* Endpoint NAK Enable (device) */ +#define IMX9_USBDEV_PORTSC1_OFFSET 0x184 /* Port status/control 1 (both) */ +#define IMX9_USBDEV_USBMODE_OFFSET 0x1a8 /* USB device mode (both) */ + +#define IMX9_USBHOST_USBCMD_OFFSET 0x140 /* USB command (both) */ +#define IMX9_USBHOST_USBSTS_OFFSET 0x144 /* USB status (both) */ +#define IMX9_USBHOST_USBINTR_OFFSET 0x148 /* USB interrupt enable (both) */ +#define IMX9_USBHOST_FRINDEX_OFFSET 0x14c /* USB frame index (both) */ +#define IMX9_USBHOST_PERIODICLIST_OFFSET 0x154 /* Frame list base address (host) */ +#define IMX9_USBHOST_ASYNCLISTADDR_OFFSET 0x158 /* Next asynchronous list address (host) */ +#define IMX9_USBHOST_TTCTRL_OFFSET 0x15c /* Asynchronous buffer status for embedded TT (host) */ +#define IMX9_USBHOST_BURSTSIZE_OFFSET 0x160 /* Programmable burst size (both) */ +#define IMX9_USBHOST_TXFILLTUNING_OFFSET 0x164 /* Host transmit pre-buffer packet tuning (host) */ +#define IMX9_USBHOST_PORTSC1_OFFSET 0x184 /* Port status/control 1 (both) */ +#define IMX9_USBHOST_USBMODE_OFFSET 0x1a8 /* USB device mode (both) */ + +/* Device endpoint registers */ + +#define IMX9_USBDEV_ENDPTSETUPSTAT_OFFSET 0x1ac /* Endpoint setup status */ +#define IMX9_USBDEV_ENDPTPRIME_OFFSET 0x1b0 /* Endpoint initialization */ +#define IMX9_USBDEV_ENDPTFLUSH_OFFSET 0x1b4 /* Endpoint de-initialization */ +#define IMX9_USBDEV_ENDPTSTATUS_OFFSET 0x1b8 /* Endpoint status */ +#define IMX9_USBDEV_ENDPTCOMPLETE_OFFSET 0x1bc /* Endpoint complete */ + +#define IMX9_USBDEV_ENDPTCTRL_OFFSET(n) (IMX9_USBDEV_ENDPTCTRL0_OFFSET + ((n) * 4)) +#define IMX9_USBDEV_ENDPTCTRL0_OFFSET 0x1c0 /* Endpoint control 0 */ +#define IMX9_USBDEV_ENDPTCTRL1_OFFSET 0x1c4 /* Endpoint control 1 */ +#define IMX9_USBDEV_ENDPTCTRL2_OFFSET 0x1c8 /* Endpoint control 2 */ +#define IMX9_USBDEV_ENDPTCTRL3_OFFSET 0x1cc /* Endpoint control 3 */ +#define IMX9_USBDEV_ENDPTCTRL4_OFFSET 0x1d0 /* Endpoint control 4 */ +#define IMX9_USBDEV_ENDPTCTRL5_OFFSET 0x1d4 /* Endpoint control 5 */ +#define IMX9_USBDEV_ENDPTCTRL6_OFFSET 0x1d8 /* Endpoint control 6 */ +#define IMX9_USBDEV_ENDPTCTRL7_OFFSET 0x1dc /* Endpoint control 7 */ + +/* USB Non-core memory map & register definition */ + +#define IMX9_USBNC_CTRL1_OFFSET 0x0200 /* USB OTG Control Register 1 */ +#define IMX9_USBNC_CTRL2_OFFSET 0x0204 /* USB OTG Control Register 2 */ +#define IMX9_USBNC_UTMIPHY_CFG1_OFFSET 0x0230 /* PHY Configure 1 */ + +/* USBOTG register bit definitions ******************************************/ + +/* Device/host capability registers */ + +/* CAPLENGTH */ + +#define USBOTG_CAPLENGTH_SHIFT (0) /* Bits 0-7: Offset from register base to operational regs */ +#define USBOTG_CAPLENGTH_MASK (0xff << USBOTG_CAPLENGTH_SHIFT) + +/* HCIVERSION */ + +#define USBHOST_HCIVERSION_SHIFT (0) /* Bits 0-15: BCD encoding of the EHCI revision number */ +#define USBHOST_HCIVERSION_MASK (0xffff << USBHOST_HCIVERSION_SHIFT) + +/* HCSPARAMS */ + +#define USBHOST_HCSPARAMS_NTT_SHIFT (24) /* Bits 24-27: Number of Transaction Translators */ +#define USBHOST_HCSPARAMS_NTT_MASK (0xf << USBHOST_HCSPARAMS_NTT_SHIFT) +#define USBHOST_HCSPARAMS_NPTT_SHIFT (20) /* Bits 20-23: Number of Ports per Transaction Translator */ +#define USBHOST_HCSPARAMS_NPTT_MASK (15 << USBHOST_HCSPARAMS_NPTT_SHIFT) +#define USBHOST_HCSPARAMS_PI (1 << 16) /* Bit 16: Port indicators */ +#define USBHOST_HCSPARAMS_NCC_SHIFT (12) /* Bits 12-15: Number of Companion Controller */ +#define USBHOST_HCSPARAMS_NCC_MASK (0xf << USBHOST_HCSPARAMS_NCC_SHIFT) +#define USBHOST_HCSPARAMS_NPCC_SHIFT (8) /* Bits 8-11: Number of Ports per Companion Controller */ +#define USBHOST_HCSPARAMS_NPCC_MASK (0xf << USBHOST_HCSPARAMS_NPCC_SHIFT) +#define USBHOST_HCSPARAMS_PPC (1 << 4) /* Bit 4: Port Power Control */ +#define USBHOST_HCSPARAMS_NPORTS_SHIF (0) /* Bits 0-3: Number of downstream ports */ +#define USBHOST_HCSPARAMS_NPORTS_MASK (0xf << USBHOST_HCSPARAMS_NPORTS_SHIFT) + +/* HCCPARAMS */ + +#define USBHOST_HCCPARAMS_EECP_SHIFT (8) /* Bits 8-15: EHCI Extended Capabilities Pointer */ +#define USBHOST_HCCPARAMS_EECP_MASK (0xff << USBHOST_HCCPARAMS_EECP_SHIFT) +#define USBHOST_HCCPARAMS_IST_SHIFT (4) /* Bits 4-7: Isochronous Scheduling Threshold */ +#define USBHOST_HCCPARAMS_IST_MASK (0xf << USBHOST_HCCPARAMS_IST_SHIFT) +#define USBHOST_HCCPARAMS_ASP (1 << 2) /* Bit 2: Asynchronous Schedule Park Capability */ +#define USBHOST_HCCPARAMS_PFL (1 << 1) /* Bit 1: Programmable Frame List Flag */ +#define USBHOST_HCCPARAMS_ADC (1 << 0) /* Bit 0: 64-bit Addressing Capability */ + +/* DCIVERSION */ + +#define USBDEV_DCIVERSION_SHIFT (0) /* Bits 0-15: BCD encoding of the device interface */ +#define USBDEV_DCIVERSION_MASK (0xffff << USBDEV_DCIVERSION_SHIFT) + +/* DCCPARAMS */ + +#define USBDEV_DCCPARAMS_HC (1 << 8) /* Bit 8: Host Capable */ +#define USBDEV_DCCPARAMS_DC (1 << 7) /* Bit 7: Device Capable */ +#define USBDEV_DCCPARAMS_DEN_SHIFT (0) /* Bits 0-4: DEN Device Endpoint Number */ +#define USBDEV_DCCPARAMS_DEN_MASK (0x1f << USBDEV_DCCPARAMS_DEN_SHIFT) + +/* Device/host operational registers */ + +/* USB Command register USBCMD -- Device Mode */ + +#define USBDEV_USBCMD_ITC_SHIFT (16) /* Bits 16-23: Interrupt threshold control */ +#define USBDEV_USBCMD_ITC_MASK (0xff << USBDEV_USBCMD_ITC_SHIFT) +# define USBDEV_USBCMD_ITCIMME (0 << USBDEV_USBCMD_ITC_SHIFT) /* Immediate (no threshold) */ +# define USBDEV_USBCMD_ITC1UF (1 << USBDEV_USBCMD_ITC_SHIFT) /* 1 micro frame */ +# define USBDEV_USBCMD_ITC2UF (2 << USBDEV_USBCMD_ITC_SHIFT) /* 2 micro frames */ +# define USBDEV_USBCMD_ITC4UF (4 << USBDEV_USBCMD_ITC_SHIFT) /* 4 micro frames */ +# define USBDEV_USBCMD_ITC8UF (8 << USBDEV_USBCMD_ITC_SHIFT) /* 8 micro frames */ +# define USBDEV_USBCMD_ITC16UF (16 << USBDEV_USBCMD_ITC_SHIFT) /* 16 micro frames */ +# define USBDEV_USBCMD_ITC32UF (32 << USBDEV_USBCMD_ITC_SHIFT) /* 32 micro frames */ +# define USBDEV_USBCMD_ITC64UF (64 << USBDEV_USBCMD_ITC_SHIFT) /* 64 micro frames */ + +#define USBDEV_USBCMD_ATDTW (1 << 14) /* Bit 14: Add dTD trip wire */ +#define USBDEV_USBCMD_SUTW (1 << 13) /* Bit 13: Setup trip wire */ +#define USBDEV_USBCMD_RST (1 << 1) /* Bit 1: 1 Controller reset */ +#define USBDEV_USBCMD_RS (1 << 0) /* Bit 0: 0 Run/Stop */ + +/* USB Command register USBCMD -- Host Mode */ + +#define USBHOST_USBCMD_ITC_SHIFT (16) /* Bits 16-13: Interrupt threshold control */ +#define USBHOST_USBCMD_ITC_MASK (0xff << USBHOST_USBCMD_ITC_SHIFT) +# define USBHOST_USBCMD_ITCIMMED (0 << USBHOST_USBCMD_ITC_SHIFT) /* Immediate (no threshold) */ +# define USBHOST_USBCMD_ITC1UF (1 << USBHOST_USBCMD_ITC_SHIFT) /* 1 micro frame */ +# define USBHOST_USBCMD_ITC2UF (2 << USBHOST_USBCMD_ITC_SHIFT) /* 2 micro frames */ +# define USBHOST_USBCMD_ITC4UF (4 << USBHOST_USBCMD_ITC_SHIFT) /* 4 micro frames */ +# define USBHOST_USBCMD_ITC8UF (8 << USBHOST_USBCMD_ITC_SHIFT) /* 8 micro frames */ +# define USBHOST_USBCMD_ITC16UF (16 << USBHOST_USBCMD_ITC_SHIFT) /* 16 micro frames */ +# define USBHOST_USBCMD_ITC32UF (32 << USBHOST_USBCMD_ITC_SHIFT) /* 32 micro frames */ +# define USBHOST_USBCMD_ITC64UF (64 << USBHOST_USBCMD_ITC_SHIFT) /* 64 micro frames */ + +#define USBHOST_USBCMD_FS2 (1 << 15) /* Bit 15: Bit 2 of the Frame List Size bits */ +#define USBHOST_USBCMD_ASPE (1 << 11) /* Bit 11: Asynchronous Schedule Park Mode Enable */ +#define USBHOST_USBCMD_ASP_SHIFT (8) /* Bits 8-9: Asynchronous schedule park mode */ +#define USBHOST_USBCMD_ASP_MASK (0x3 << USBHOST_USBCMD_ASP_SHIFT) +#define USBHOST_USBCMD_IAA (1 << 6) /* Bit 6: Interrupt next asynchronous schedule */ +#define USBHOST_USBCMD_ASE (1 << 5) /* Bit 5: Skips processing asynchronous schedule */ +#define USBHOST_USBCMD_PSE (1 << 4) /* Bit 4: Skips processing periodic schedule */ +#define USBHOST_USBCMD_FS1 (1 << 3) /* Bit 3: Bit 1 of the Frame List Size bits */ +#define USBHOST_USBCMD_FS0 (1 << 2) /* Bit 2: Bit 0 of the Frame List Size bits */ +#define USBHOST_USBCMD_RST (1 << 1) /* Bit 1: Controller reset */ +#define USBHOST_USBCMD_RS (1 << 0) /* Bit 0: Run/Stop */ + +/* USB Status register USBSTS -- Device Mode */ + +#define USBDEV_USBSTS_NAKI (1 << 16) /* Bit 16: NAK interrupt bit */ +#define USBDEV_USBSTS_SLI (1 << 8) /* Bit 8: DCSuspend */ +#define USBDEV_USBSTS_SRI (1 << 7) /* Bit 7: SOF received */ +#define USBDEV_USBSTS_URI (1 << 6) /* Bit 6: USB reset received */ +#define USBDEV_USBSTS_PCI (1 << 2) /* Bit 2: Port change detect */ +#define USBDEV_USBSTS_UEI (1 << 1) /* Bit 1: USB error interrupt */ +#define USBDEV_USBSTS_UI (1 << 0) /* Bit 0: USB interrupt */ + +/* USB Status register USBSTS -- Host Mode */ + +#define USBHOST_USBSTS_UPI (1 << 19) /* Bit 19: USB host periodic interrupt */ +#define USBHOST_USBSTS_UAI (1 << 18) /* Bit 18: USB host asynchronous interrupt */ +#define USBHOST_USBSTS_AS (1 << 15) /* Bit 15: Asynchronous schedule status */ +#define USBHOST_USBSTS_PS (1 << 14) /* Bit 14: Periodic schedule status */ +#define USBHOST_USBSTS_RCL (1 << 13) /* Bit 13: Reclamation */ +#define USBHOST_USBSTS_HCH (1 << 12) /* Bit 12: HCHalted */ +#define USBHOST_USBSTS_SRI (1 << 7) /* Bit 7: SOF received */ +#define USBHOST_USBSTS_AAI (1 << 5) /* Bit 5: Interrupt on async advance */ +#define USBHOST_USBSTS_FRI (1 << 3) /* Bit 3: Frame list roll-over */ +#define USBHOST_USBSTS_PCI (1 << 2) /* Bit 2: Port change detect */ +#define USBHOST_USBSTS_UEI (1 << 1) /* Bit 1: USB error interrupt */ +#define USBHOST_USBSTS_UI (1 << 0) /* Bit 0: USB interrupt */ + +/* USB interrupt register USBINTR -- Device Mode */ + +#define USBDEV_USBINTR_NAKE (1 << 16) /* Bit 16: NAK interrupt enable */ +#define USBDEV_USBINTR_SLE (1 << 8) /* Bit 8: Sleep enable */ +#define USBDEV_USBINTR_SRE (1 << 7) /* Bit 7: SOF received enable */ +#define USBDEV_USBINTR_URE (1 << 6) /* Bit 6: USB reset enable */ +#define USBDEV_USBINTR_PCE (1 << 2) /* Bit 2: Port change detect enable */ +#define USBDEV_USBINTR_UEE (1 << 1) /* Bit 1: USB error interrupt enable */ +#define USBDEV_USBINTR_UE (1 << 0) /* Bit 0: USB interrupt enable */ + +/* USB interrupt register USBINTR (address 0x19000148) -- Host Mode */ + +#define USBHOST_USBINTR_UPIE (1 << 19) /* Bit 19: USB host periodic interrupt enable */ +#define USBHOST_USBINTR_UAIE (1 << 18) /* Bit 18: USB host asynchronous interrupt enable */ +#define USBHOST_USBINTR_SRE (1 << 7) /* Bit 7: SOF timer interrupt enable */ +#define USBHOST_USBINTR_AAE (1 << 5) /* Bit 5: Interrupt on asynchronous advance enable */ +#define USBHOST_USBINTR_FRE (1 << 3) /* Bit 3: Frame list rollover enable */ +#define USBHOST_USBINTR_PCE (1 << 2) /* Bit 2: Port change detect enable */ +#define USBHOST_USBINTR_UEE (1 << 1) /* Bit 1: USB error interrupt enable */ +#define USBHOST_USBINTR_UE (1 << 0) /* Bit 0: USB interrupt enable */ + +/* Frame index register FRINDEX -- Device Mode */ + +#define USBDEV_FRINDEX_LFN_SHIFT (3) /* Bits 3-13: Frame number of last frame transmitted */ +#define USBDEV_FRINDEX_LFN_MASK (0x7ff << USBDEV_FRINDEX_LFN_SHIFT) +#define USBDEV_FRINDEX_CUFN_SHIFT (0) /* Bits 0-2: Current micro frame number */ +#define USBDEV_FRINDEX_CUFN_MASK (7 << USBDEV_FRINDEX_CUFN_SHIFT) + +/* Frame index register FRINDEX -- Host Mode */ + +#define USBHOST_FRINDEX_FLI_SHIFT (3) /* Bits 3-13: Frame list current index */ +#define USBHOST_FRINDEX_FLI_MASK(n) (0x7ff << ((n) + USBHOST_FRINDEX_FLI_SHIFT - 1) +#define USBHOST_FRINDEX_CUFN_SHIFT (0) /* Bits 0-2: Current micro frame number */ +#define USBHOST_FRINDEX_CUFN_MASK (0x7 << USBHOST_FRINDEX_CUFN_SHIFT) + +/* USB Device Address register DEVICEADDR -- Device Mode */ + +#define USBDEV_DEVICEADDR_SHIFT (25) /* Bits 25-31: USBADR USB device address */ +#define USBDEV_DEVICEADDR_MASK (0x7f << USBDEV_DEVICEADDR_SHIFT) +#define USBDEV_DEVICEADDR_USBADRA (1 << 24) /* Bit 24: Device address advance */ + +/* USB Periodic List Base register PERIODICLIST -- Host Mode */ + +#define USBHOST_PERIODICLIST_BASEADR_SHIFT (12) /* Bits 12-31: Base Address (Low) */ +#define USBHOST_PERIODICLIST_BASEADR_MASK (0xfffff << USBHOST_PERIODICLIST_PERBASE_SHIFT) + +/* USB Asynchronous List Address register ASYNCLISTADDR -- Host Mode */ + +#define USBHOST_ASYNCLISTADDR_ASYBASE_SHIFT (5) /* Bits 5-31: Link pointer (Low) LPL */ +#define USBHOST_ASYNCLISTADDR_ASYBASE_MASK (0x07ffffff << USBHOST_ASYNCLISTADDR_ASYBASE_SHIFT) + +/* USB Endpoint List Address register ENDPOINTLISTADDR -- Device Mode */ + +#define USBDEV_ENDPOINTLIST_EPBASE_SHIFT (11) /* Bits 11-31: Endpoint list pointer (low) */ +#define USBDEV_ENDPOINTLIST_EPBASE_MASK (0x1fffff << USBDEV_ENDPOINTLIST_EPBASE_SHIFT) + +/* USB burst size register BURSTSIZE -- Device/Host Mode */ + +#define USBDEV_BURSTSIZE_TXPBURST_SHIFT (8) /* Bits 8-15: Programmable TX burst length */ +#define USBDEV_BURSTSIZE_TXPBURST_MASK (0xff << USBDEV_BURSTSIZE_TXPBURST_SHIFT) +#define USBDEV_BURSTSIZE_RXPBURST_SHIFT (0) /* Bits 0-7: RXPBURST Programmable RX burst length */ +#define USBDEV_BURSTSIZE_RXPBURST_MASK (0xff << USBDEV_BURSTSIZE_RXPBURST_SHIFT) + +#define USBHOST_BURSTSIZE_TXPBURST_SHIFT (8) /* Bits 8-15: Programmable TX burst length */ +#define USBHOST_BURSTSIZE_TXPBURST_MASK (0xff << USBHOST_BURSTSIZE_TXPBURST_SHIFT) +#define USBHOST_BURSTSIZE_RXPBURST_SHIFT (0) /* Bits 0-7: RXPBURST Programmable RX burst length */ +#define USBHOST_BURSTSIZE_RXPBURST_MASK (0xff << USBHOST_BURSTSIZE_RXPBURST_SHIFT) + +/* USB Transfer buffer Fill Tuning register TXFIFOFILLTUNING -- Host Mode */ + +#define USBHOST_TXFILLTUNING_FIFOTHRES_SHIFT (16) /* Bits 16-21: Scheduler overhead */ +#define USBHOST_TXFILLTUNING_FIFOTHRES_MASK (0x3f << USBHOST_TXFILLTUNING_FIFOTHRES_SHIFT) +#define USBHOST_TXFILLTUNING_SCHEATLTH_SHIFT (8) /* Bits 8-12: Scheduler health counter */ +#define USBHOST_TXFILLTUNING_SCHEATLTH_MASK (0x1f << USBHOST_TXFILLTUNING_SCHEATLTH_SHIFT) +#define USBHOST_TXFILLTUNING_SCHOH_SHIFT (0) /* Bits 0-7: FIFO burst threshold */ +#define USBHOST_TXFILLTUNING_SCHOH_MASK (0x7f << USBHOST_TXFILLTUNING_SCHOH_SHIFT) + +/* USB endpoint NAK register ENDPTNAK -- Device Mode */ + +#define USBDEV_ENDPTNAK_EPTN_SHIFT (16) /* Bits 16-23: Tx endpoint NAK */ +#define USBDEV_ENDPTNAK_EPTN_MASK (0xff << USBDEV_ENDPTNAK_EPTN_SHIFT) +#define USBDEV_ENDPTNAK_EPRN_SHIFT (0) /* Bits 0-7: Rx endpoint NAK */ +#define USBDEV_ENDPTNAK_EPRN_MASK (0xff << USBDEV_ENDPTNAK_EPRN_SHIFT) + +/* USB Endpoint NAK Enable register ENDPTNAKEN -- Device Mode */ + +#define USBDEV_ENDPTNAK_EPTNE_SHIFT (16) /* Bits 16-23: Tx endpoint NAK enable */ +#define USBDEV_ENDPTNAK_EPTNE_MASK (0xff << USBDEV_ENDPTNAK_EPTNE_SHIFT) +#define USBDEV_ENDPTNAK_EPRNE_SHIFT (0) /* Bits 0-7: Rx endpoint NAK enable */ +#define USBDEV_ENDPTNAK_EPRNE_MASK (0xff << USBDEV_ENDPTNAK_EPRNE_SHIFT) + +/* Configure Flag register CONFIGFLAG -- Not used, returns 1 */ + +#define USBDEV_CONFIGFLAG_CF (1) + +/* Port Status and Control register PRTSC1 -- Device Mode */ + +#define USBDEV_PRTSC1_PSPD_SHIFT (26) /* Bits 26-27: Port speed */ +#define USBDEV_PRTSC1_PSPD_MASK (0x3 << USBDEV_PRTSC1_PSPD_SHIFT) +# define USBDEV_PRTSC1_PSPD_FS (0 << USBDEV_PRTSC1_PSPD_SHIFT) /* Full-speed */ +# define USBDEV_PRTSC1_PSPD_LS (1 << USBDEV_PRTSC1_PSPD_SHIFT) /* Low-speed */ +# define USBDEV_PRTSC1_PSPD_HS (2 << USBDEV_PRTSC1_PSPD_SHIFT) /* High-speed */ + +#define USBDEV_PRTSC1_PFSC (1 << 24) /* Bit 24: Port force full speed connect */ +#define USBDEV_PRTSC1_PHCD (1 << 23) /* Bit 23: PHY low power suspend - clock disable (PLPSCD) */ +#define USBDEV_PRTSC1_PTC_SHIFT (16) /* Bits 16-19: 19: Port test control */ +#define USBDEV_PRTSC1_PTC_MASK (0xf << USBDEV_PRTSC1_PTC_SHIFT) +# define USBDEV_PRTSC1_PTC_DISABLE (0 << USBDEV_PRTSC1_PTC_SHIFT) /* TEST_MODE_DISABLE */ +# define USBDEV_PRTSC1_PTC_JSTATE (1 << USBDEV_PRTSC1_PTC_SHIFT) /* J_STATE */ +# define USBDEV_PRTSC1_PTC_KSTATE (2 << USBDEV_PRTSC1_PTC_SHIFT) /* K_STATE */ +# define USBDEV_PRTSC1_PTC_SE0 (3 << USBDEV_PRTSC1_PTC_SHIFT) /* SE0 (host)/NAK (device) */ +# define USBDEV_PRTSC1_PTC_PACKET (4 << USBDEV_PRTSC1_PTC_SHIFT) /* Packet */ +# define USBDEV_PRTSC1_PTC_HS (5 << USBDEV_PRTSC1_PTC_SHIFT) /* FORCE_ENABLE_HS */ +# define USBDEV_PRTSC1_PTC_FS (6 << USBDEV_PRTSC1_PTC_SHIFT) /* FORCE_ENABLE_FS */ + +#define USBDEV_PRTSC1_PIC_SHIFT (14) /* Bits 14-15: Port indicator control */ +#define USBDEV_PRTSC1_PIC_MASK (0x3 << USBDEV_PRTSC1_PIC_SHIFT) +# define USBDEV_PRTSC1_PIC_OFF (0 << USBDEV_PRTSC1_PIC_SHIFT) /* 00 Port indicators are off */ +# define USBDEV_PRTSC1_PIC_AMBER (1 << USBDEV_PRTSC1_PIC_SHIFT) /* 01 amber */ +# define USBDEV_PRTSC1_PIC_GREEN (2 << USBDEV_PRTSC1_PIC_SHIFT) /* 10 green */ + +#define USBDEV_PRTSC1_HSP (1 << 9) /* Bit 9: High-speed status */ +#define USBDEV_PRTSC1_PR (1 << 8) /* Bit 8: Port reset */ +#define USBDEV_PRTSC1_SUSP (1 << 7) /* Bit 7: Suspend */ +#define USBDEV_PRTSC1_FPR (1 << 6) /* Bit 6: Force port resume */ +#define USBDEV_PRTSC1_PEC (1 << 3) /* Bit 3: Port enable/disable change */ +#define USBDEV_PRTSC1_PE (1 << 2) /* Bit 2: Port enable */ +#define USBDEV_PRTSC1_CCS (1 << 0) /* Bit 0: Current connect status */ + +/* Port Status and Control register PRTSC1 -- Host Mode */ + +#define USBHOST_PRTSC1_PSPD_SHIFT (26) /* Bits 26-27: Port speed */ +#define USBHOST_PRTSC1_PSPD_MASK (0x3 << USBHOST_PRTSC1_PSPD_SHIFT) +# define USBHOST_PRTSC1_PSPD_FS (0 << USBHOST_PRTSC1_PSPD_SHIFT) /* Full-speed */ +# define USBHOST_PRTSC1_PSPD_LS (1 << USBHOST_PRTSC1_PSPD_SHIFT) /* Low-speed */ +# define USBHOST_PRTSC1_PSPD_HS (2 << USBHOST_PRTSC1_PSPD_SHIFT) /* High-speed */ + +#define USBHOST_PRTSC1_PFSC (1 << 24) /* Bit 24: Port force full speed connect */ +#define USBHOST_PRTSC1_PHCD (1 << 23) /* Bit 23: PHY low power suspend - clock disable (PLPSCD) */ +#define USBHOST_PRTSC1_WKOC (1 << 22) /* Bit 22: Wake on over-current enable (WKOC_E) */ +#define USBHOST_PRTSC1_WKDC (1 << 21) /* Bit 21: Wake on disconnect enable (WKDSCNNT_E) */ +#define USBHOST_PRTSC1_WKCN (1 << 20) /* Bit 20: Wake on connect enable (WKCNNT_E) */ +#define USBHOST_PRTSC1_PTC_SHIFT (16) /* Bits 16-19: Port test control */ +#define USBHOST_PRTSC1_PTC_MASK (0xf << USBHOST_PRTSC1_PTC_SHIFT) +# define USBHOST_PRTSC1_PTC_DISABLE (0 << USBHOST_PRTSC1_PTC_SHIFT) /* 0000 TEST_MODE_DISABLE */ +# define USBHOST_PRTSC1_PTC_JSTATE (1 << USBHOST_PRTSC1_PTC_SHIFT) /* 0001 J_STATE */ +# define USBHOST_PRTSC1_PTC_KSTATE (2 << USBHOST_PRTSC1_PTC_SHIFT) /* 0010 K_STATE */ +# define USBHOST_PRTSC1_PTC_SE0 (3 << USBHOST_PRTSC1_PTC_SHIFT) /* 0011 SE0 (host)/NAK (device) */ +# define USBHOST_PRTSC1_PTC_PACKET (4 << USBHOST_PRTSC1_PTC_SHIFT) /* 0100 Packet */ +# define USBHOST_PRTSC1_PTC_HS (5 << USBHOST_PRTSC1_PTC_SHIFT) /* 0101 FORCE_ENABLE_HS */ +# define USBHOST_PRTSC1_PTC_FS (6 << USBHOST_PRTSC1_PTC_SHIFT) /* 0110 FORCE_ENABLE_FS */ +# define USBHOST_PRTSC1_PTC_LS (7 << USBHOST_PRTSC1_PTC_SHIFT) /* 0111 FORCE_ENABLE_LS */ + +#define USBHOST_PRTSC1_PIC_SHIFT (14) /* Bits 14-15: Port indicator control */ +#define USBHOST_PRTSC1_PIC_MASK (0x3 << USBHOST_PRTSC1_PIC_SHIFT) +# define USBHOST_PRTSC1_PIC_OFF (0 << USBHOST_PRTSC1_PIC_SHIFT) /* 00 Port indicators are off */ +# define USBHOST_PRTSC1_PIC_AMBER (1 << USBHOST_PRTSC1_PIC_SHIFT) /* 01 Amber */ +# define USBHOST_PRTSC1_PIC_GREEN (2 << USBHOST_PRTSC1_PIC_SHIFT) /* 10 Green */ + +#define USBHOST_PRTSC1_PP (1 << 12) /* Bit 12: Port power control */ +#define USBHOST_PRTSC1_LS_SHIFT (10) /* Bits 10-11: Line status */ +#define USBHOST_PRTSC1_LS_MASK (0x3 << USBHOST_PRTSC1_LS_SHIFT) +# define USBHOST_PRTSC1_LS_SE0 (0 << USBHOST_PRTSC1_LS_SHIFT) /* SE0 (USB_DP and USB_DM LOW) */ +# define USBHOST_PRTSC1_LS_JSTATE (2 << USBHOST_PRTSC1_LS_SHIFT) /* J-state (USB_DP HIGH and USB_DM LOW) */ +# define USBHOST_PRTSC1_LS_KSTATE (1 << USBHOST_PRTSC1_LS_SHIFT) /* K-state (USB_DP LOW and USB_DM HIGH) */ + +#define USBHOST_PRTSC1_HSP (1 << 9) /* Bit 9: High-speed status */ +#define USBHOST_PRTSC1_PR (1 << 8) /* Bit 8: Port reset */ +#define USBHOST_PRTSC1_SUSP (1 << 7) /* Bit 7: Suspend */ +#define USBHOST_PRTSC1_FPR (1 << 6) /* Bit 6: Force port resume */ +#define USBHOST_PRTSC1_OCC (1 << 5) /* Bit 5: Over-current change */ +#define USBHOST_PRTSC1_OCA (1 << 4) /* Bit 4: Over-current active */ +#define USBHOST_PRTSC1_PEC (1 << 3) /* Bit 3: Port disable/enable change */ +#define USBHOST_PRTSC1_PE (1 << 2) /* Bit 2: Port enable */ +#define USBHOST_PRTSC1_CSC (1 << 1) /* Bit 1: Connect status change */ +#define USBHOST_PRTSC1_CCS (1 << 0) /* Bit 0: Current connect status */ + +/* OTG Status and Control register (OTGSC) */ + +/* OTG interrupt enable */ + +#define USBOTG_OTGSC_DPIE (1 << 30) /* Bit 30: Data pulse interrupt enable */ +#define USBOTG_OTGSC_1MSE (1 << 29) /* Bit 29: 1 millisecond timer interrupt enable */ +#define USBOTG_OTGSC_BSEIE (1 << 28) /* Bit 28: B-session end interrupt enable */ +#define USBOTG_OTGSC_BSVIE (1 << 27) /* Bit 27: B-session valid interrupt enable */ +#define USBOTG_OTGSC_ASVIE (1 << 26) /* Bit 26: A-session valid interrupt enable */ +#define USBOTG_OTGSC_AVVIE (1 << 25) /* Bit 25: A-VBUS valid interrupt enable */ +#define USBOTG_OTGSC_IDIE (1 << 24) /* Bit 24: USB ID interrupt enable */ + +/* OTG interrupt status */ + +#define USBOTG_OTGSC_DPIS (1 << 22) /* Bit 22: Data pulse interrupt status */ +#define USBOTG_OTGSC_1MSS (1 << 21) /* Bit 21: 1 millisecond timer interrupt status */ +#define USBOTG_OTGSC_BSEIS (1 << 20) /* Bit 20: B-Session end interrupt status */ +#define USBOTG_OTGSC_BSVIS (1 << 19) /* Bit 19: B-Session valid interrupt status */ +#define USBOTG_OTGSC_ASVIS (1 << 18) /* Bit 18: A-Session valid interrupt status */ +#define USBOTG_OTGSC_AVVIS (1 << 17) /* Bit 17: A-VBUS valid interrupt status */ +#define USBOTG_OTGSC_IDIS (1 << 16) /* Bit 16: USB ID interrupt status */ + +/* OTG status inputs */ + +#define USBOTG_OTGSC_DPS (1 << 14) /* Bit 14: Data bus pulsing status */ +#define USBOTG_OTGSC_1MST (1 << 13) /* Bit 13: 1 millisecond timer toggle */ +#define USBOTG_OTGSC_BSE (1 << 12) /* Bit 12: B-session end */ +#define USBOTG_OTGSC_BSV (1 << 11) /* Bit 11: B-session valid */ +#define USBOTG_OTGSC_ASV (1 << 10) /* Bit 10: A-session valid */ +#define USBOTG_OTGSC_AVV (1 << 9) /* Bit 9: A-VBUS valid */ +#define USBOTG_OTGSC_ID (1 << 8) /* Bit 8: USB ID */ + +/* OTG controls */ + +#define USBOTG_OTGSC_IDPU (1 << 5) /* Bit 5: ID pull-up */ +#define USBOTG_OTGSC_DP (1 << 4) /* Bit 4: Data pulsing */ +#define USBOTG_OTGSC_OT (1 << 3) /* Bit 3: OTG termination */ +#define USBOTG_OTGSC_VC (1 << 1) /* Bit 1: VBUS_Charge */ +#define USBOTG_OTGSC_VD (1 << 0) /* Bit 0: VBUS_Discharge */ + +/* USB Mode register USBMODE -- Device Mode */ + +#define USBDEV_USBMODE_SDIS (1 << 4) /* Bit 4: Stream disable mode */ +#define USBDEV_USBMODE_SLOM (1 << 3) /* Bit 3: Setup Lockout mode */ +#define USBDEV_USBMODE_ES (1 << 2) /* Bit 2: Endian select */ +#define USBDEV_USBMODE_CM_SHIFT (0) /* Bits 0-1: Controller mode */ +#define USBDEV_USBMODE_CM_MASK (0x3 << USBDEV_USBMODE_CM_SHIFT) +# define USBDEV_USBMODE_CM_IDLE (0 << USBDEV_USBMODE_CM_SHIFT) /* Idle */ +# define USBDEV_USBMODE_CM_DEVICE (2 << USBDEV_USBMODE_CM_SHIFT) /* Device controller */ +# define USBDEV_USBMODE_CM_HOST (3 << USBDEV_USBMODE_CM_SHIFT) /* Host controller */ + +/* USB Mode register USBMODE -- Host Mode */ + +#define USBHOST_USBMODE_SDIS (1 << 4) /* Bit 4: Stream disable mode */ +#define USBHOST_USBMODE_ES (1 << 2) /* Bit 2: Endian select */ +#define USBHOST_USBMODE_CM_SHIFT (0) /* Bits 0-1: Controller mode */ +#define USBHOST_USBMODE_CM_MASK (0x3 << USBHOST_USBMODE_CM_SHIFT) +# define USBHOST_USBMODE_CM_IDLE (0 << USBHOST_USBMODE_CM_SHIFT) /* Idle */ +# define USBHOST_USBMODE_CM_DEVICE (2 << USBHOST_USBMODE_CM_SHIFT) /* Device controller */ +# define USBHOST_USBMODE_CM_HOST (3 << USBHOST_USBMODE_CM_SHIFT) /* Host controller */ + +/* Device endpoint registers */ + +/* USB Endpoint Setup Status register ENDPTSETUPSTAT */ + +#define USBDEV_ENDPTSETSTAT_STAT15 (1 << 15) /* Bit 15: Setup EP status for logical EP 15 */ +#define USBDEV_ENDPTSETSTAT_STAT14 (1 << 14) /* Bit 14: Setup EP status for logical EP 14 */ +#define USBDEV_ENDPTSETSTAT_STAT13 (1 << 13) /* Bit 13: Setup EP status for logical EP 13 */ +#define USBDEV_ENDPTSETSTAT_STAT12 (1 << 12) /* Bit 12: Setup EP status for logical EP 12 */ +#define USBDEV_ENDPTSETSTAT_STAT11 (1 << 11) /* Bit 11: Setup EP status for logical EP 11 */ +#define USBDEV_ENDPTSETSTAT_STAT10 (1 << 10) /* Bit 10: Setup EP status for logical EP 10 */ +#define USBDEV_ENDPTSETSTAT_STAT9 (1 << 9) /* Bit 9: Setup EP status for logical EP 9 */ +#define USBDEV_ENDPTSETSTAT_STAT8 (1 << 8) /* Bit 8: Setup EP status for logical EP 8 */ +#define USBDEV_ENDPTSETSTAT_STAT7 (1 << 7) /* Bit 7: Setup EP status for logical EP 7 */ +#define USBDEV_ENDPTSETSTAT_STAT6 (1 << 6) /* Bit 6: Setup EP status for logical EP 6 */ +#define USBDEV_ENDPTSETSTAT_STAT5 (1 << 5) /* Bit 5: Setup EP status for logical EP 5 */ +#define USBDEV_ENDPTSETSTAT_STAT4 (1 << 4) /* Bit 4: Setup EP status for logical EP 4 */ +#define USBDEV_ENDPTSETSTAT_STAT3 (1 << 3) /* Bit 3: Setup EP status for logical EP 3 */ +#define USBDEV_ENDPTSETSTAT_STAT2 (1 << 2) /* Bit 2: Setup EP status for logical EP 2 */ +#define USBDEV_ENDPTSETSTAT_STAT1 (1 << 1) /* Bit 1: Setup EP status for logical EP 1 */ +#define USBDEV_ENDPTSETSTAT_STAT0 (1 << 0) /* Bit 0: Setup EP status for logical EP 0 */ + +/* USB Endpoint Prime register ENDPTPRIME */ + +#define USBDEV_ENDPTPRIM_PETB7 (1 << 23) /* Bit 23: Prime EP xmt buffer for physical IN EP 7 */ +#define USBDEV_ENDPTPRIM_PETB6 (1 << 22) /* Bit 22: Prime EP xmt buffer for physical IN EP 6 */ +#define USBDEV_ENDPTPRIM_PETB5 (1 << 21) /* Bit 21: Prime EP xmt buffer for physical IN EP 5 */ +#define USBDEV_ENDPTPRIM_PETB4 (1 << 20) /* Bit 20: Prime EP xmt buffer for physical IN EP 4 */ +#define USBDEV_ENDPTPRIM_PETB3 (1 << 19) /* Bit 19: Prime EP xmt buffer for physical IN EP 3 */ +#define USBDEV_ENDPTPRIM_PETB2 (1 << 18) /* Bit 18: Prime EP xmt buffer for physical IN EP 2 */ +#define USBDEV_ENDPTPRIM_PETB1 (1 << 17) /* Bit 17: Prime EP xmt buffer for physical IN EP 1 */ +#define USBDEV_ENDPTPRIM_PETB0 (1 << 16) /* Bit 16: Prime EP xmt buffer for physical IN EP 0 */ +#define USBDEV_ENDPTPRIM_PERB7 (1 << 7) /* Bit 7: Prime EP recv buffer for physical OUT EP 7 */ +#define USBDEV_ENDPTPRIM_PERB6 (1 << 6) /* Bit 6: Prime EP recv buffer for physical OUT EP 6 */ +#define USBDEV_ENDPTPRIM_PERB5 (1 << 5) /* Bit 5: Prime EP recv buffer for physical OUT EP 5 */ +#define USBDEV_ENDPTPRIM_PERB4 (1 << 4) /* Bit 4: Prime EP recv buffer for physical OUT EP 4 */ +#define USBDEV_ENDPTPRIM_PERB3 (1 << 3) /* Bit 3: Prime EP recv buffer for physical OUT EP 3 */ +#define USBDEV_ENDPTPRIM_PERB2 (1 << 2) /* Bit 2: Prime EP recv buffer for physical OUT EP 2 */ +#define USBDEV_ENDPTPRIM_PERB1 (1 << 1) /* Bit 1: Prime EP recv buffer for physical OUT EP 1 */ +#define USBDEV_ENDPTPRIM_PERB0 (1 << 0) /* Bit 0: Prime EP recv buffer for physical OUT EP 0 */ + +/* USB Endpoint Flush register ENDPTFLUSH */ + +#define USBDEV_ENDPTFLUSH_FETB7 (1 << 23) /* Bit 23: Flush EP xmt buffer for physical IN EP 7 */ +#define USBDEV_ENDPTFLUSH_FETB6 (1 << 22) /* Bit 22: Flush EP xmt buffer for physical IN EP 6 */ +#define USBDEV_ENDPTFLUSH_FETB5 (1 << 21) /* Bit 21: Flush EP xmt buffer for physical IN EP 5 */ +#define USBDEV_ENDPTFLUSH_FETB4 (1 << 20) /* Bit 20: Flush EP xmt buffer for physical IN EP 4 */ +#define USBDEV_ENDPTFLUSH_FETB3 (1 << 19) /* Bit 19: Flush EP xmt buffer for physical IN EP 3 */ +#define USBDEV_ENDPTFLUSH_FETB2 (1 << 18) /* Bit 18: Flush EP xmt buffer for physical IN EP 2 */ +#define USBDEV_ENDPTFLUSH_FETB1 (1 << 17) /* Bit 17: Flush EP xmt buffer for physical IN EP 1 */ +#define USBDEV_ENDPTFLUSH_FETB0 (1 << 16) /* Bit 16: Flush EP xmt buffer for physical IN EP 0 */ +#define USBDEV_ENDPTFLUSH_FERB7 (1 << 7) /* Bit 7: Flush EP recv buffer for physical OUT EP 7 */ +#define USBDEV_ENDPTFLUSH_FERB6 (1 << 6) /* Bit 6: Flush EP recv buffer for physical OUT EP 6 */ +#define USBDEV_ENDPTFLUSH_FERB5 (1 << 5) /* Bit 5: Flush EP recv buffer for physical OUT EP 5 */ +#define USBDEV_ENDPTFLUSH_FERB4 (1 << 4) /* Bit 4: Flush EP recv buffer for physical OUT EP 4 */ +#define USBDEV_ENDPTFLUSH_FERB3 (1 << 3) /* Bit 3: Flush EP recv buffer for physical OUT EP 3 */ +#define USBDEV_ENDPTFLUSH_FERB2 (1 << 2) /* Bit 2: Flush EP recv buffer for physical OUT EP 2 */ +#define USBDEV_ENDPTFLUSH_FERB1 (1 << 1) /* Bit 1: Flush EP recv buffer for physical OUT EP 1 */ +#define USBDEV_ENDPTFLUSH_FERB0 (1 << 0) /* Bit 0: Flush EP recv buffer for physical OUT EP 0 */ + +/* USB Endpoint Status register ENDPTSTATUS */ + +#define USBDEV_ENDPTSTATUS_ETBR7 (1 << 23) /* Bit 23: EP xmt buffer ready for physical IN EP 7 */ +#define USBDEV_ENDPTSTATUS_ETBR6 (1 << 22) /* Bit 22: EP xmt buffer ready for physical IN EP 6 */ +#define USBDEV_ENDPTSTATUS_ETBR5 (1 << 21) /* Bit 21: EP xmt buffer ready for physical IN EP 5 */ +#define USBDEV_ENDPTSTATUS_ETBR4 (1 << 20) /* Bit 20: EP xmt buffer ready for physical IN EP 4 */ +#define USBDEV_ENDPTSTATUS_ETBR3 (1 << 19) /* Bit 19: EP xmt buffer ready for physical IN EP 3 */ +#define USBDEV_ENDPTSTATUS_ETBR2 (1 << 18) /* Bit 18: EP xmt buffer ready for physical IN EP 2 */ +#define USBDEV_ENDPTSTATUS_ETBR1 (1 << 17) /* Bit 17: EP xmt buffer ready for physical IN EP 1 */ +#define USBDEV_ENDPTSTATUS_ETBR0 (1 << 16) /* Bit 16: EP xmt buffer ready for physical IN EP 0 */ +#define USBDEV_ENDPTSTATUS_ERBR7 (1 << 7) /* Bit 7: EP recv buffer ready for physical OUT EP 7 */ +#define USBDEV_ENDPTSTATUS_ERBR6 (1 << 6) /* Bit 6: EP recv buffer ready for physical OUT EP 6 */ +#define USBDEV_ENDPTSTATUS_ERBR5 (1 << 5) /* Bit 5: EP recv buffer ready for physical OUT EP 5 */ +#define USBDEV_ENDPTSTATUS_ERBR4 (1 << 4) /* Bit 4: EP recv buffer ready for physical OUT EP 4 */ +#define USBDEV_ENDPTSTATUS_ERBR3 (1 << 3) /* Bit 3: EP recv buffer ready for physical OUT EP 3 */ +#define USBDEV_ENDPTSTATUS_ERBR2 (1 << 2) /* Bit 2: EP recv buffer ready for physical OUT EP 2 */ +#define USBDEV_ENDPTSTATUS_ERBR1 (1 << 1) /* Bit 1: EP recv buffer ready for physical OUT EP 1 */ +#define USBDEV_ENDPTSTATUS_ERBR0 (1 << 0) /* Bit 0: EP recv buffer ready for physical OUT EP 0 */ + +/* USB Endpoint Complete register ENDPTCOMPLETE */ + +#define USBDEV_ENDPTCOMPLETE_ETCE7 (1 << 23) /* Bit 23: EP xmt complete event for physical IN EP 7 */ +#define USBDEV_ENDPTCOMPLETE_ETCE6 (1 << 22) /* Bit 22: EP xmt complete event for physical IN EP 6 */ +#define USBDEV_ENDPTCOMPLETE_ETCE5 (1 << 21) /* Bit 21: EP xmt complete event for physical IN EP 5 */ +#define USBDEV_ENDPTCOMPLETE_ETCE4 (1 << 20) /* Bit 20: EP xmt complete event for physical IN EP 4 */ +#define USBDEV_ENDPTCOMPLETE_ETCE3 (1 << 19) /* Bit 19: EP xmt complete event for physical IN EP 3 */ +#define USBDEV_ENDPTCOMPLETE_ETCE2 (1 << 18) /* Bit 18: EP xmt complete event for physical IN EP 2 */ +#define USBDEV_ENDPTCOMPLETE_ETCE1 (1 << 17) /* Bit 17: EP xmt complete event for physical IN EP 1 */ +#define USBDEV_ENDPTCOMPLETE_ETCE0 (1 << 16) /* Bit 16: EP xmt complete event for physical IN EP 0 */ +#define USBDEV_ENDPTCOMPLETE_ERCE7 (1 << 7) /* Bit 7: EP recv complete event for physical OUT EP 7 */ +#define USBDEV_ENDPTCOMPLETE_ERCE6 (1 << 6) /* Bit 6: EP recv complete event for physical OUT EP 6 */ +#define USBDEV_ENDPTCOMPLETE_ERCE5 (1 << 5) /* Bit 5: EP recv complete event for physical OUT EP 5 */ +#define USBDEV_ENDPTCOMPLETE_ERCE4 (1 << 4) /* Bit 4: EP recv complete event for physical OUT EP 4 */ +#define USBDEV_ENDPTCOMPLETE_ERCE3 (1 << 3) /* Bit 3: EP recv complete event for physical OUT EP 3 */ +#define USBDEV_ENDPTCOMPLETE_ERCE2 (1 << 2) /* Bit 2: EP recv complete event for physical OUT EP 2 */ +#define USBDEV_ENDPTCOMPLETE_ERCE1 (1 << 1) /* Bit 1: EP recv complete event for physical OUT EP 1 */ +#define USBDEV_ENDPTCOMPLETE_ERCE0 (1 << 0) /* Bit 0: EP recv complete event for physical OUT EP 0 */ + +/* USB Endpoint 0 Control register ENDPTCTRL0 */ + +#define USBDEV_ENDPTCTRL0_TXE (1 << 23) /* Bit 23: Tx endpoint enable */ +#define USBDEV_ENDPTCTRL0_TXT_SHIFT (18) /* Bits 18-19: Tx endpoint type */ +#define USBDEV_ENDPTCTRL0_TXT_MASK (0x3 << USBDEV_ENDPTCTRL0_TXT_SHIFT) +# define USBDEV_ENDPTCTRL0_TXT_CTRL (0 << USBDEV_ENDPTCTRL0_TXT_SHIFT) /* Control */ + +#define USBDEV_ENDPTCTRL0_TXS (1 << 16) /* Bit 16: Tx endpoint stall */ +#define USBDEV_ENDPTCTRL0_RXE (1 << 7) /* Bit 7: Rx endpoint enable */ +#define USBDEV_ENDPTCTRL0_RXT_SHIFT (2) /* Bits 2-3: Endpoint type */ +#define USBDEV_ENDPTCTR0L_RXT_MASK (0x3 << USBDEV_ENDPTCTRL0_RXT_SHIFT) +# define USBDEV_ENDPTCTRL0_RXT_CTRL (0 << USBDEV_ENDPTCTRL0_RXT_SHIFT) /* Control */ + +#define USBDEV_ENDPTCTRL0_RXS (1 << 0) /* Bit 0: Rx endpoint stall */ + +/* USB Endpoint 1-7 control registers ENDPTCTRL1-ENDPPTCTRL7 */ + +#define USBDEV_ENDPTCTRL_TXE (1 << 23) /* Bit 23: Tx endpoint enable */ +#define USBDEV_ENDPTCTRL_TXR (1 << 22) /* Bit 22: Tx data toggle reset */ +#define USBDEV_ENDPTCTRL_TXI (1 << 21) /* Bit 21: Tx data toggle inhibit */ +#define USBDEV_ENDPTCTRL_TXT_SHIFT (18) /* Bits 18-19: Tx endpoint type */ +#define USBDEV_ENDPTCTRL_TXT_MASK (0x3 << USBDEV_ENDPTCTRL_TXT_SHIFT) +# define USBDEV_ENDPTCTRL_TXT_CTRL (0 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Control */ +# define USBDEV_ENDPTCTRL_TXT_ISOC (1 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Isochronous */ +# define USBDEV_ENDPTCTRL_TXT_BULK (2 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Bulk */ +# define USBDEV_ENDPTCTRL_TXT_INTR (3 << USBDEV_ENDPTCTRL_TXT_SHIFT) /* Interrupt */ + +#define USBDEV_ENDPTCTRL_TXS (1 << 16) /* Bit 16: Tx endpoint stall */ +#define USBDEV_ENDPTCTRL_RXE (1 << 7) /* Bit 7: Rx endpoint enable */ +#define USBDEV_ENDPTCTRL_RXR (1 << 6) /* Bit 6: Rx data toggle reset */ +#define USBDEV_ENDPTCTRL_RXI (1 << 5) /* Bit 5: Rx data toggle inhibit */ +#define USBDEV_ENDPTCTRL_RXT_SHIFT (2) /* Bits 2-3: Endpoint type */ +#define USBDEV_ENDPTCTRL_RXT_MASK (0x3 << USBDEV_ENDPTCTRL_RXT_SHIFT) +# define USBDEV_ENDPTCTRL_RXT_CTRL (0 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Control */ +# define USBDEV_ENDPTCTRL_RXT_ISOC (1 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Isochronous */ +# define USBDEV_ENDPTCTRL_RXT_BULK (2 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Bulk */ +# define USBDEV_ENDPTCTRL_RXT_INTR (3 << USBDEV_ENDPTCTRL_RXT_SHIFT) /* Interrupt */ + +#define USBDEV_ENDPTCTRL_RXS (1 << 0) /* Bit 0: Rx endpoint stall */ + +/* Device non-core registers */ + +/* USB OTG Control register 1 */ + +#define USBNC_CTRL1_WIR (1 << 31) /* Bit 31: Wake-up Interrupt Request */ +#define USBNC_CTRL1_WKUP_DPDM_EN (1 << 29) /* Bit 29: Wake-up on DP/DM change enable */ +#define USBNC_CTRL1_WKUP_VBUS_EN (1 << 17) /* Bit 17: Wake-up on VBUS change enable */ +#define USBNC_CTRL1_WKUP_ID_EN (1 << 16) /* Bit 16: Wake-up on ID change enable */ +#define USBNC_CTRL1_WKUP_SW (1 << 15) /* Bit 15: Software Wake-up */ +#define USBNC_CTRL1_WKUP_SW_EN (1 << 14) /* Bit 14: Software Wake-up Enable */ +#define USBNC_CTRL1_WIE (1 << 10) /* Bit 10: Wake-up Interrupt Enable */ +#define USBNC_CTRL1_PWR_POL (1 << 9) /* Bit 9: Power Polarity */ +#define USBNC_CTRL1_OVER_CUR_POL (1 << 8) /* Bit 8: Polarity of Overcurrent */ +#define USBNC_CTRL1_OVER_CUR_DIS (1 << 7) /* Bit 7: Disable Overcurrent Detection */ + +/* USB OTG Control register 2 */ + +#define USBNC_CTRL2_UTMI_CLK_VLD (1 << 31) /* Bit 31: UTMI clock to the USB PHY is valid */ +#define USBNC_CTRL2_SHORT_PKT_EN (1 << 23) /* Bit 23: Short Packet Interrupt enable */ +#define USBNC_CTRL2_LOWSPEED_EN (1 << 3) /* Bit 3: Low speed enable */ +#define USBNC_CTRL2_AUTURESUME_EN (1 << 2) /* Bit 2: Auto Resume Enable */ +#define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK (0x3) /* Bits 0-1: VBUS source select at VBUS wakeup event */ + +/* PHY Configure 1 -- internal control register bits of the PHY clock */ + +#define USBNC_UTMIPHY_CFG1_TXPREEMPPULSETUNE0 (1 << 30) /* Bit 30: HS Transmitter Pre-Emphasis Duration Control */ +#define USBNC_UTMIPHY_CFG1_TXPREEMPAMPTUNE0_SHIFT (28) /* Bits 28-29: HS Transmitter Pre-Emphasis Current Control */ +#define USBNC_UTMIPHY_CFG1_TXPREEMPAMPTUNE0_MASK (0x3 << 28) +#define USBNC_UTMIPHY_CFG1_TXRESTUNE0_SHIFT (26) /* Bits 26-27: USB Source Impedance Adjustment */ +#define USBNC_UTMIPHY_CFG1_TXRESTUNE0_MASK (0x3 << 26) +#define USBNC_UTMIPHY_CFG1_TXRISETUNE0_SHIFT (24) /* Bits 24-25: HS Transmitter Rise/Fall Time Adjustment */ +#define USBNC_UTMIPHY_CFG1_TXRISETUNE0_MASK (0x3 << 24) +#define USBNC_UTMIPHY_CFG1_TXVREFTUNE0_SHIFT (20) /* Bits 20-23: HS DC Voltage Level Adjustment */ +#define USBNC_UTMIPHY_CFG1_TXVREFTUNE0_MASK (0xf << 20) +#define USBNC_UTMIPHY_CFG1_TXFSLSTUNE0_SHIFT (16) /* Bits 16-19: FS/LS Source Impedance Adjustment */ +#define USBNC_UTMIPHY_CFG1_TXFSLSTUNE0_MASK (0xf << 16) +#define USBNC_UTMIPHY_CFG1_PHY_POR_SW (1 << 15) /* Bit 15 : PHY software POR */ +#define USBNC_UTMIPHY_CFG1_TXHSXVTUNE_SHIFT (13) /* Bits 13-14: Transmitter High-Speed Crossover Adjustment */ +#define USBNC_UTMIPHY_CFG1_TXHSXVTUNE_MASK (0x3 << 13) +#define USBNC_UTMIPHY_CFG1_OTGTUNE0_SHIFT (10) /* Bits 10-12: VBUS Valid Threshold Adjustment */ +#define USBNC_UTMIPHY_CFG1_OTGTUNE0_MASK (0x7 << 10) +#define USBNC_UTMIPHY_CFG1_SQRXTUNE0_SHIFT (7) /* Bits 7-9: Squelch Threshold Adjustment */ +#define USBNC_UTMIPHY_CFG1_SQRXTUNE0_MASK (0x7 << 7) +#define USBNC_UTMIPHY_CFG1_COMPDISTUNE0_SHIFT (4) /* Bits 4-6: Disconnect Threshold Adjustment */ +#define USBNC_UTMIPHY_CFG1_COMPDISTUNE0_MASK (0x7 << 4) + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_USBOTG_H */ diff --git a/arch/arm64/src/imx9/hardware/imx9_usdhc.h b/arch/arm64/src/imx9/hardware/imx9_usdhc.h new file mode 100644 index 0000000000000..0ef608feb9ebd --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_usdhc.h @@ -0,0 +1,704 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_usdhc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_USDHC_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_USDHC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define IMX9_USDHC_DSADDR_OFFSET 0x0000 /* DMA System Address Register */ +#define IMX9_USDHC_BLKATTR_OFFSET 0x0004 /* Block Attributes Register */ +#define IMX9_USDHC_CMDARG_OFFSET 0x0008 /* Command Argument Register */ +#define IMX9_USDHC_XFERTYP_OFFSET 0x000c /* Transfer Type Register */ +#define IMX9_USDHC_CMDRSP0_OFFSET 0x0010 /* Command Response 0 */ +#define IMX9_USDHC_CMDRSP1_OFFSET 0x0014 /* Command Response 1 */ +#define IMX9_USDHC_CMDRSP2_OFFSET 0x0018 /* Command Response 2 */ +#define IMX9_USDHC_CMDRSP3_OFFSET 0x001c /* Command Response 3 */ +#define IMX9_USDHC_DATAPORT_OFFSET 0x0020 /* Buffer Data Port Register */ +#define IMX9_USDHC_PRSSTAT_OFFSET 0x0024 /* Present State Register */ +#define IMX9_USDHC_PROCTL_OFFSET 0x0028 /* Protocol Control Register */ +#define IMX9_USDHC_SYSCTL_OFFSET 0x002c /* System Control Register */ +#define IMX9_USDHC_IRQSTAT_OFFSET 0x0030 /* Interrupt Status Register */ +#define IMX9_USDHC_IRQSTATEN_OFFSET 0x0034 /* Interrupt Status Enable Register */ +#define IMX9_USDHC_IRQSIGEN_OFFSET 0x0038 /* Interrupt Signal Enable Register */ +#define IMX9_USDHC_AC12ERR_OFFSET 0x003c /* Auto CMD12 Error Status Register */ +#define IMX9_USDHC_HTCAPBLT_OFFSET 0x0040 /* Host Controller Capabilities */ +#define IMX9_USDHC_WML_OFFSET 0x0044 /* Watermark Level Register */ +#define IMX9_USDHC_MIX_OFFSET 0x0048 /* Mixer Control Register */ +#define IMX9_USDHC_FEVT_OFFSET 0x0050 /* Force Event Register */ +#define IMX9_USDHC_ADMAES_OFFSET 0x0054 /* ADMA Error Status Register */ +#define IMX9_USDHC_ADSADDR_OFFSET 0x0058 /* ADMA System Address Register */ +#define IMX9_USDHC_DLL_CONTROL_OFFSET 0x0060 /* DLL Control Register */ +#define IMX9_USDHC_DLL_STATUS_OFFSET 0x0064 /* DLL Status Register */ +#define IMX9_USDHC_CLK_TUNE_CTRL_OFFSET 0x0068 /* Clock turing control Register */ +#define IMX9_USDHC_VENDOR_OFFSET 0x00c0 /* Vendor Specific Register */ +#define IMX9_USDHC_MMCBOOT_OFFSET 0x00c4 /* MMC Boot Register */ +#define IMX9_USDHC_VENDOR2_OFFSET 0x00c8 /* Vendor 2 Register */ +#define IMX9_USDHC_TC_OFFSET 0x00cc /* Tuning Control Register */ +#define IMX9_USDHC_CQVER_OFFSET 0x0100 /* Command Queuing Version */ +#define IMX9_USDHC_CQCAP_OFFSET 0x0104 /* Command Queuing Capabilities */ +#define IMX9_USDHC_CQCFG_OFFSET 0x0108 /* Command Queuing Configuration */ +#define IMX9_USDHC_CQCTL_OFFSET 0x010c /* Command Queuing Control */ +#define IMX9_USDHC_CQIS_OFFSET 0x0110 /* Command Queuing Interrupt Status */ +#define IMX9_USDHC_CQISTE_OFFSET 0x0114 /* Command Queuing Interrupt Status Enable */ +#define IMX9_USDHC_CQISGE_OFFSET 0x0118 /* Command Queuing Interrupt Signal Enable */ +#define IMX9_USDHC_CQIC_OFFSET 0x011c /* Command Queuing Interrupt Coalescing */ +#define IMX9_USDHC_CQTDLBA_OFFSET 0x0120 /* Command Queuing Task Descriptor List Base Address */ +#define IMX9_USDHC_CQTDLBAU_OFFSET 0x0124 /* Command Queuing Task Descriptor List Base Address Upper 32 Bits */ +#define IMX9_USDHC_CQTDBR_OFFSET 0x0128 /* Command Queuing Task Doorbell */ +#define IMX9_USDHC_CQTCN_OFFSET 0x012c /* Command Queuing Task Completion Notification */ +#define IMX9_USDHC_CQDQS_OFFSET 0x0130 /* Command Queuing Device Queue Status */ +#define IMX9_USDHC_CQDPT_OFFSET 0x0134 /* Command Queuing Device Pending Tasks */ +#define IMX9_USDHC_CQTCLR_OFFSET 0x0138 /* Command Queuing Task Clear */ +#define IMX9_USDHC_CQSSC1_OFFSET 0x0140 /* Command Queuing Send Status Configuration 1 */ +#define IMX9_USDHC_CQSSC2_OFFSET 0x0144 /* Command Queuing Send Status Configuration 2 */ +#define IMX9_USDHC_CQCRDCT_OFFSET 0x0148 /* Command Queuing Command Response for Direct-Command Task */ +#define IMX9_USDHC_CQRMEM_OFFSET 0x0150 /* Command Queuing Response Mode Error Mask */ +#define IMX9_USDHC_CQTERRI_OFFSET 0x0154 /* Command Queuing Task Error Information */ +#define IMX9_USDHC_CQCRI_OFFSET 0x0158 /* Command Queuing Command Response Index */ +#define IMX9_USDHC_CQCRA_OFFSET 0x015c /* Command Queuing Command Response Argument */ + +/* Register Addresses *******************************************************/ + +/* For USDHC1 ... */ + +#define IMX9_USDHC1_DSADDR (IMX9_USDHC1_BASE + IMX9_USDHC_DSADDR_OFFSET) +#define IMX9_USDHC1_BLKATTR (IMX9_USDHC1_BASE + IMX9_USDHC_BLKATTR_OFFSET) +#define IMX9_USDHC1_CMDARG (IMX9_USDHC1_BASE + IMX9_USDHC_CMDARG_OFFSET) +#define IMX9_USDHC1_XFERTYP (IMX9_USDHC1_BASE + IMX9_USDHC_XFERTYP_OFFSET) +#define IMX9_USDHC1_CMDRSP0 (IMX9_USDHC1_BASE + IMX9_USDHC_CMDRSP0_OFFSET) +#define IMX9_USDHC1_CMDRSP1 (IMX9_USDHC1_BASE + IMX9_USDHC_CMDRSP1_OFFSET) +#define IMX9_USDHC1_CMDRSP2 (IMX9_USDHC1_BASE + IMX9_USDHC_CMDRSP2_OFFSET) +#define IMX9_USDHC1_CMDRSP3 (IMX9_USDHC1_BASE + IMX9_USDHC_CMDRSP3_OFFSET) +#define IMX9_USDHC1_DATAPORT (IMX9_USDHC1_BASE + IMX9_USDHC_DATAPORT_OFFSET) +#define IMX9_USDHC1_PRSSTAT (IMX9_USDHC1_BASE + IMX9_USDHC_PRSSTAT_OFFSET) +#define IMX9_USDHC1_PROCTL (IMX9_USDHC1_BASE + IMX9_USDHC_PROCTL_OFFSET) +#define IMX9_USDHC1_SYSCTL (IMX9_USDHC1_BASE + IMX9_USDHC_SYSCTL_OFFSET) +#define IMX9_USDHC1_IRQSTAT (IMX9_USDHC1_BASE + IMX9_USDHC_IRQSTAT_OFFSET) +#define IMX9_USDHC1_IRQSTATEN (IMX9_USDHC1_BASE + IMX9_USDHC_IRQSTATEN_OFFSET) +#define IMX9_USDHC1_IRQSIGEN (IMX9_USDHC1_BASE + IMX9_USDHC_IRQSIGEN_OFFSET) +#define IMX9_USDHC1_AC12ERR (IMX9_USDHC1_BASE + IMX9_USDHC_AC12ERR_OFFSET) +#define IMX9_USDHC1_HTCAPBLT (IMX9_USDHC1_BASE + IMX9_USDHC_HTCAPBLT_OFFSET) +#define IMX9_USDHC1_WML (IMX9_USDHC1_BASE + IMX9_USDHC_WML_OFFSET) +#define IMX9_USDHC1_MIX (IMX9_USDHC1_BASE + IMX9_USDHC_MIX_OFFSET) +#define IMX9_USDHC1_FEVT (IMX9_USDHC1_BASE + IMX9_USDHC_FEVT_OFFSET) +#define IMX9_USDHC1_ADMAES (IMX9_USDHC1_BASE + IMX9_USDHC_ADMAES_OFFSET) +#define IMX9_USDHC1_ADSADDR (IMX9_USDHC1_BASE + IMX9_USDHC_ADSADDR_OFFSET) +#define IMX9_USDHC1_DLL_CONTROL (IMX9_USDHC1_BASE + IMX9_USDHC_DLL_CONTROL_OFFSET) +#define IMX9_USDHC1_DLL_STATUS (IMX9_USDHC1_BASE + IMX9_USDHC_DLL_STATUS) +#define IMX9_USDHC1_CLK_TUNE_CTRL (IMX9_USDHC1_BASE + IMX9_USDHC_CLK_TUNE_CTRL) +#define IMX9_USDHC1_VENDOR (IMX9_USDHC1_BASE + IMX9_USDHC_VENDOR_OFFSET) +#define IMX9_USDHC1_MMCBOOT (IMX9_USDHC1_BASE + IMX9_USDHC_MMCBOOT_OFFSET) +#define IMX9_USDHC1_VENDOR2 (IMX9_USDHC1_BASE + IMX9_USDHC_VENDOR2_OFFSET) +#define IMX9_USDHC1_TC (IMX9_USDHC1_BASE + IMX9_USDHC_TC_OFFSET) +#define IMX9_USDHC1_CQVER (IMX9_USDHC1_BASE + IMX9_USDHC_CQVER_OFFSET) +#define IMX9_USDHC1_CQCAP (IMX9_USDHC1_BASE + IMX9_USDHC_CQCAP_OFFSET) +#define IMX9_USDHC1_CQCFG (IMX9_USDHC1_BASE + IMX9_USDHC_CQCFG_OFFSET) +#define IMX9_USDHC1_CQCTL (IMX9_USDHC1_BASE + IMX9_USDHC_CQCTL_OFFSET) +#define IMX9_USDHC1_CQIS (IMX9_USDHC1_BASE + IMX9_USDHC_CQIS_OFFSET) +#define IMX9_USDHC1_CQISTE (IMX9_USDHC1_BASE + IMX9_USDHC_CQISTE_OFFSET) +#define IMX9_USDHC1_CQISGE (IMX9_USDHC1_BASE + IMX9_USDHC_CQISGE_OFFSET) +#define IMX9_USDHC1_CQIC (IMX9_USDHC1_BASE + IMX9_USDHC_CQIC_OFFSET) +#define IMX9_USDHC1_CQTDLBA (IMX9_USDHC1_BASE + IMX9_USDHC_CQTDLBA_OFFSET) +#define IMX9_USDHC1_CQTDLBAU (IMX9_USDHC1_BASE + IMX9_USDHC_CQTDLBAU_OFFSET) +#define IMX9_USDHC1_CQTDBR (IMX9_USDHC1_BASE + IMX9_USDHC_CQTDBR_OFFSET) +#define IMX9_USDHC1_CQTCN (IMX9_USDHC1_BASE + IMX9_USDHC_CQTCN_OFFSET) +#define IMX9_USDHC1_CQDQS (IMX9_USDHC1_BASE + IMX9_USDHC_CQDQS_OFFSET) +#define IMX9_USDHC1_CQDPT (IMX9_USDHC1_BASE + IMX9_USDHC_CQDPT_OFFSET) +#define IMX9_USDHC1_CQTCL (IMX9_USDHC1_BASE + IMX9_USDHC_CQTCLR_OFFSET) +#define IMX9_USDHC1_CQSSC1 (IMX9_USDHC1_BASE + IMX9_USDHC_CQSSC1_OFFSET) +#define IMX9_USDHC1_CQSSC2 (IMX9_USDHC1_BASE + IMX9_USDHC_CQSSC2_OFFSET) +#define IMX9_USDHC1_CQCRDCT (IMX9_USDHC1_BASE + IMX9_USDHC_CQCRDCT_OFFSET) +#define IMX9_USDHC1_CQRMEM (IMX9_USDHC1_BASE + IMX9_USDHC_CQRMEM_OFFSET) +#define IMX9_USDHC1_CQTERRI (IMX9_USDHC1_BASE + IMX9_USDHC_CQTERRI_OFFSET) +#define IMX9_USDHC1_CQCRI (IMX9_USDHC1_BASE + IMX9_USDHC_CQCRI_OFFSET) +#define IMX9_USDHC1_CQCRA (IMX9_USDHC1_BASE + IMX9_USDHC_CQCRA_OFFSET) + +/* For USDHC2 ... */ + +#define IMX9_USDHC2_DSADDR (IMX9_USDHC2_BASE + IMX9_USDHC_DSADDR_OFFSET) +#define IMX9_USDHC2_BLKATTR (IMX9_USDHC2_BASE + IMX9_USDHC_BLKATTR_OFFSET) +#define IMX9_USDHC2_CMDARG (IMX9_USDHC2_BASE + IMX9_USDHC_CMDARG_OFFSET) +#define IMX9_USDHC2_XFERTYP (IMX9_USDHC2_BASE + IMX9_USDHC_XFERTYP_OFFSET) +#define IMX9_USDHC2_CMDRSP0 (IMX9_USDHC2_BASE + IMX9_USDHC_CMDRSP0_OFFSET) +#define IMX9_USDHC2_CMDRSP1 (IMX9_USDHC2_BASE + IMX9_USDHC_CMDRSP1_OFFSET) +#define IMX9_USDHC2_CMDRSP2 (IMX9_USDHC2_BASE + IMX9_USDHC_CMDRSP2_OFFSET) +#define IMX9_USDHC2_CMDRSP3 (IMX9_USDHC2_BASE + IMX9_USDHC_CMDRSP3_OFFSET) +#define IMX9_USDHC2_DATAPORT (IMX9_USDHC2_BASE + IMX9_USDHC_DATPORT_OFFSET) +#define IMX9_USDHC2_PRSSTAT (IMX9_USDHC2_BASE + IMX9_USDHC_PRSSTAT_OFFSET) +#define IMX9_USDHC2_PROCTL (IMX9_USDHC2_BASE + IMX9_USDHC_PROCTL_OFFSET) +#define IMX9_USDHC2_SYSCTL (IMX9_USDHC2_BASE + IMX9_USDHC_SYSCTL_OFFSET) +#define IMX9_USDHC2_IRQSTAT (IMX9_USDHC2_BASE + IMX9_USDHC_IRQSTAT_OFFSET) +#define IMX9_USDHC2_IRQSTATEN (IMX9_USDHC2_BASE + IMX9_USDHC_IRQSTATEN_OFFSET) +#define IMX9_USDHC2_IRQSIGEN (IMX9_USDHC2_BASE + IMX9_USDHC_IRQSIGEN_OFFSET) +#define IMX9_USDHC2_AC12ERR (IMX9_USDHC2_BASE + IMX9_USDHC_AC12ERR_OFFSET) +#define IMX9_USDHC2_HTCAPBLT (IMX9_USDHC2_BASE + IMX9_USDHC_HTCAPBLT_OFFSET) +#define IMX9_USDHC2_WML (IMX9_USDHC2_BASE + IMX9_USDHC_WML_OFFSET) +#define IMX9_USDHC2_MIX (IMX9_USDHC2_BASE + IMX9_USDHC_MIX_OFFSET) +#define IMX9_USDHC2_FEVT (IMX9_USDHC2_BASE + IMX9_USDHC_FEVT_OFFSET) +#define IMX9_USDHC2_ADMAES (IMX9_USDHC2_BASE + IMX9_USDHC_ADMAES_OFFSET) +#define IMX9_USDHC2_ADSADDR (IMX9_USDHC2_BASE + IMX9_USDHC_ADSADDR_OFFSET) +#define IMX9_USDHC2_DLL_CONTROL (IMX9_USDHC2_BASE + IMX9_USDHC_DLL_CONTROL_OFFSET) +#define IMX9_USDHC2_DLL_STATUS (IMX9_USDHC2_BASE + IMX9_USDHC_DLL_STATUS) +#define IMX9_USDHC2_CLK_TUNE_CTRL (IMX9_USDHC2_BASE + IMX9_USDHC_CLK_TUNE_CTRL) +#define IMX9_USDHC2_VENDOR (IMX9_USDHC2_BASE + IMX9_USDHC_VENDOR_OFFSET) +#define IMX9_USDHC2_MMCBOOT (IMX9_USDHC2_BASE + IMX9_USDHC_MMCBOOT_OFFSET) +#define IMX9_USDHC2_VENDOR2 (IMX9_USDHC2_BASE + IMX9_USDHC_VENDOR2_OFFSET) +#define IMX9_USDHC2_TC (IMX9_USDHC2_BASE + IMX9_USDHC_TC_OFFSET) +#define IMX9_USDHC2_CQVER (IMX9_USDHC2_BASE + IMX9_USDHC_CQVER_OFFSET) +#define IMX9_USDHC2_CQCAP (IMX9_USDHC2_BASE + IMX9_USDHC_CQCAP_OFFSET) +#define IMX9_USDHC2_CQCFG (IMX9_USDHC2_BASE + IMX9_USDHC_CQCFG_OFFSET) +#define IMX9_USDHC2_CQCTL (IMX9_USDHC2_BASE + IMX9_USDHC_CQCTL_OFFSET) +#define IMX9_USDHC2_CQIS (IMX9_USDHC2_BASE + IMX9_USDHC_CQIS_OFFSET) +#define IMX9_USDHC2_CQISTE (IMX9_USDHC2_BASE + IMX9_USDHC_CQISTE_OFFSET) +#define IMX9_USDHC2_CQISGE (IMX9_USDHC2_BASE + IMX9_USDHC_CQISGE_OFFSET) +#define IMX9_USDHC2_CQIC (IMX9_USDHC2_BASE + IMX9_USDHC_CQIC_OFFSET) +#define IMX9_USDHC2_CQTDLBA (IMX9_USDHC2_BASE + IMX9_USDHC_CQTDLBA_OFFSET) +#define IMX9_USDHC2_CQTDLBAU (IMX9_USDHC2_BASE + IMX9_USDHC_CQTDLBAU_OFFSET) +#define IMX9_USDHC2_CQTDBR (IMX9_USDHC2_BASE + IMX9_USDHC_CQTDBR_OFFSET) +#define IMX9_USDHC2_CQTCN (IMX9_USDHC2_BASE + IMX9_USDHC_CQTCN_OFFSET) +#define IMX9_USDHC2_CQDQS (IMX9_USDHC2_BASE + IMX9_USDHC_CQDQS_OFFSET) +#define IMX9_USDHC2_CQDPT (IMX9_USDHC2_BASE + IMX9_USDHC_CQDPT_OFFSET) +#define IMX9_USDHC2_CQTCL (IMX9_USDHC2_BASE + IMX9_USDHC_CQTCLR_OFFSET) +#define IMX9_USDHC2_CQSSC1 (IMX9_USDHC2_BASE + IMX9_USDHC_CQSSC1_OFFSET) +#define IMX9_USDHC2_CQSSC2 (IMX9_USDHC2_BASE + IMX9_USDHC_CQSSC2_OFFSET) +#define IMX9_USDHC2_CQCRDCT (IMX9_USDHC2_BASE + IMX9_USDHC_CQCRDCT_OFFSET) +#define IMX9_USDHC2_CQRMEM (IMX9_USDHC2_BASE + IMX9_USDHC_CQRMEM_OFFSET) +#define IMX9_USDHC2_CQTERRI (IMX9_USDHC2_BASE + IMX9_USDHC_CQTERRI_OFFSET) +#define IMX9_USDHC2_CQCRI (IMX9_USDHC2_BASE + IMX9_USDHC_CQCRI_OFFSET) +#define IMX9_USDHC2_CQCRA (IMX9_USDHC2_BASE + IMX9_USDHC_CQCRA_OFFSET) + +/* Register Bit Definitions *************************************************/ + +/* DMA System Address Register */ + +#define USDHC_DSADDR_SHIFT (0) /* Bits 2-31: DMA System Address */ +#define USDHC_DSADDR_MASK (0xfffffffc) /* Bits 0-1: 32 bit aligned, low bits Reserved */ + +/* Block Attributes Register */ + +#define USDHC_BLKATTR_SIZE_SHIFT (0) /* Bits 0-12: Transfer Block Size */ +#define USDHC_BLKATTR_SIZE_MASK (0x1fff << USDHC_BLKATTR_SIZE_SHIFT) +# define USDHC_BLKATTR_SIZE(n) ((n) << USDHC_BLKATTR_SIZE_SHIFT) + /* Bits 13-15: Reserved */ +#define USDHC_BLKATTR_CNT_SHIFT (16) /* Bits 16-31: Blocks Count For Current Transfer */ +#define USDHC_BLKATTR_CNT_MASK (0xffff << USDHC_BLKATTR_CNT_SHIFT) +# define USDHC_BLKATTR_CNT(n) ((n) << USDHC_BLKATTR_CNT_SHIFT) + +/* Command Argument Register (32-bit cmd/arg data) */ + +/* Transfer Type Register */ + +#define USDHC_XFERTYP_DMAEN (1 << 0) /* Bit 0: Enable DMA functionality */ +#define USDHC_XFERTYP_BCEN (1 << 1) /* Bit 1: Enable the Block Count register */ +#define USDHC_XFERTYP_AC12EN (1 << 2) /* Bit 2: Enable automatic CMD12 */ +#define USDHC_XFERTYP_DDREN (1 << 3) /* Bit 3: Dual data rate mode selection */ +#define USDHC_XFERTYP_DTDSEL (1 << 4) /* Bit 4: The direction of DATA line data transfers */ +#define USDHC_XFERTYP_MSBSEL (1 << 5) /* Bit 5: Enable multiple block DATA line data transfers */ +#define USDHC_XFERTYP_NIBBLE_POS (1 << 6) /* Bit 6: The nibble position */ +#define USDHC_XFERTYP_AC23EN (1 << 7) /* Bit 7: Enable automatic CMD23 */ + /* Bits 8-15: Reserved */ +#define USDHC_XFERTYP_RSPTYP_SHIFT (16) /* Bits 16-17: Response Type Select */ +#define USDHC_XFERTYP_RSPTYP_MASK (3 << USDHC_XFERTYP_RSPTYP_SHIFT) +# define USDHC_XFERTYP_RSPTYP_NONE (0 << USDHC_XFERTYP_RSPTYP_SHIFT) /* No response */ +# define USDHC_XFERTYP_RSPTYP_LEN136 (1 << USDHC_XFERTYP_RSPTYP_SHIFT) /* Response length 136 */ +# define USDHC_XFERTYP_RSPTYP_LEN48 (2 << USDHC_XFERTYP_RSPTYP_SHIFT) /* Response length 48 */ +# define USDHC_XFERTYP_RSPTYP_LEN48BSY (3 << USDHC_XFERTYP_RSPTYP_SHIFT) /* Response length 48, check busy */ + + /* Bit 18: Reserved */ +#define USDHC_XFERTYP_CCCEN (1 << 19) /* Bit 19: Command CRC Check Enable */ +#define USDHC_XFERTYP_CICEN (1 << 20) /* Bit 20: Command Index Check Enable */ +#define USDHC_XFERTYP_DPSEL (1 << 21) /* Bit 21: Data Present Select */ +#define USDHC_XFERTYP_CMDTYP_SHIFT (22) /* Bits 22-23: Command Type */ +#define USDHC_XFERTYP_CMDTYP_MASK (3 << USDHC_XFERTYP_CMDTYP_SHIFT) +# define USDHC_XFERTYP_CMDTYP_NORMAL (0 << USDHC_XFERTYP_CMDTYP_SHIFT) /* Normal other commands */ +# define USDHC_XFERTYP_CMDTYP_SUSPEND (1 << USDHC_XFERTYP_CMDTYP_SHIFT) /* Suspend CMD52 for writing bus suspend in CCCR */ +# define USDHC_XFERTYP_CMDTYP_RESUME (2 << USDHC_XFERTYP_CMDTYP_SHIFT) /* Resume CMD52 for writing function select in CCCR */ +# define USDHC_XFERTYP_CMDTYP_ABORT (3 << USDHC_XFERTYP_CMDTYP_SHIFT) /* Abort CMD12, CMD52 for writing I/O abort in CCCR */ + +#define USDHC_XFERTYP_CMDINX_SHIFT (24) /* Bits 24-29: Command Index */ +#define USDHC_XFERTYP_CMDINX_MASK (0x3f << USDHC_XFERTYP_CMDINX_SHIFT) + /* Bits 30-31: Reserved */ + +/* Command Response 0-3 (32-bit response data) */ + +/* Buffer Data Port Register (32-bit data content) */ + +/* Present State Register */ + +#define USDHC_PRSSTAT_CIHB (1 << 0) /* Bit 0: Command Inhibit (CMD) */ +#define USDHC_PRSSTAT_CDIHB (1 << 1) /* Bit 1: Command Inhibit (DAT) */ +#define USDHC_PRSSTAT_DLA (1 << 2) /* Bit 2: Data Line Active */ +#define USDHC_PRSSTAT_SDSTB (1 << 3) /* Bit 3: SD Clock Stable */ + /* Bits 4-7: Reserved */ +#define USDHC_PRSSTAT_WTA (1 << 8) /* Bit 8: Write Transfer Active */ +#define USDHC_PRSSTAT_RTA (1 << 9) /* Bit 9: Read Transfer Active */ +#define USDHC_PRSSTAT_BWEN (1 << 10) /* Bit 10: Buffer Write Enable */ +#define USDHC_PRSSTAT_BREN (1 << 11) /* Bit 11: Buffer Read Enable */ +#define USDHC_PRSSTAT_RTR (1 << 12) /* Bit 12: Retuning request */ + /* Bits 13-14: Reserved */ +#define USDHC_PRSSTAT_TSCD (1 << 15) /* Bit 15: Tape Select Change Done */ +#define USDHC_PRSSTAT_CINS (1 << 16) /* Bit 16: Card Inserted */ + /* Bit 17: Reserved */ +#define USDHC_PRSSTAT_CDPL (1 << 18) /* Bit 18: Card Detect Pin Level */ +#define USDHC_PRSSTAT_WPSPL (1 << 19) /* Bit 19: Write Protect Switch Pin Level */ + /* Bits 20-22: Reserved */ +#define USDHC_PRSSTAT_CLSL (1 << 23) /* Bit 23: CMD Line Signal Level */ +#define USDHC_PRSSTAT_DLSL_SHIFT (24) /* Bits 24-31: DAT Line Signal Level */ +#define USDHC_PRSSTAT_DLSL_MASK (0xff << USDHC_PRSSTAT_DLSL_SHIFT) +# define USDHC_PRSSTAT_DLSL_DAT0 (0x01 << USDHC_PRSSTAT_DLSL_SHIFT) +# define USDHC_PRSSTAT_DLSL_DAT1 (0x02 << USDHC_PRSSTAT_DLSL_SHIFT) +# define USDHC_PRSSTAT_DLSL_DAT2 (0x04 << USDHC_PRSSTAT_DLSL_SHIFT) +# define USDHC_PRSSTAT_DLSL_DAT3 (0x08 << USDHC_PRSSTAT_DLSL_SHIFT) +# define USDHC_PRSSTAT_DLSL_DAT4 (0x10 << USDHC_PRSSTAT_DLSL_SHIFT) +# define USDHC_PRSSTAT_DLSL_DAT5 (0x20 << USDHC_PRSSTAT_DLSL_SHIFT) +# define USDHC_PRSSTAT_DLSL_DAT6 (0x40 << USDHC_PRSSTAT_DLSL_SHIFT) +# define USDHC_PRSSTAT_DLSL_DAT7 (0x80 << USDHC_PRSSTAT_DLSL_SHIFT) + +/* Protocol Control Register */ + + /* Bit 0: Reserved */ +#define USDHC_PROCTL_DTW_SHIFT (1) /* Bits 1-2: Data Transfer Width */ +#define USDHC_PROCTL_DTW_MASK (3 << USDHC_PROCTL_DTW_SHIFT) +# define USDHC_PROCTL_DTW_1BIT (0 << USDHC_PROCTL_DTW_SHIFT) /* 1-bit mode */ +# define USDHC_PROCTL_DTW_4BIT (1 << USDHC_PROCTL_DTW_SHIFT) /* 4-bit mode */ +# define USDHC_PROCTL_DTW_8BIT (2 << USDHC_PROCTL_DTW_SHIFT) /* 8-bit mode */ + +#define USDHC_PROCTL_D3CD (1 << 3) /* Bit 3: DAT3 as Card Detection Pin */ +#define USDHC_PROCTL_EMODE_SHIFT (4) /* Bits 4-5: Endian mode */ +#define USDHC_PROCTL_EMODE_MASK (3 << USDHC_PROCTL_EMODE_SHIFT) +# define USDHC_PROCTL_EMODE_BE (0 << USDHC_PROCTL_EMODE_SHIFT)/* Big endian mode */ +# define USDHC_PROCTL_EMODE_HWBE (1 << USDHC_PROCTL_EMODE_SHIFT)/* Half word big endian mode */ +# define USDHC_PROCTL_EMODE_LE (2 << USDHC_PROCTL_EMODE_SHIFT)/* Little endian mode */ + /* Bits 6-7: Reserved */ +#define USDHC_PROCTL_DMAS_SHIFT (8) /* Bits 8-9: DMA Select */ +#define USDHC_PROCTL_DMAS_MASK (3 << USDHC_PROCTL_DMAS_SHIFT) +# define USDHC_PROCTL_DMAS_NODMA (0 << USDHC_PROCTL_DMAS_SHIFT) /* No DMA or simple DMA is selected */ +# define USDHC_PROCTL_DMAS_ADMA1 (1 << USDHC_PROCTL_DMAS_SHIFT) /* ADMA1 is selected */ +# define USDHC_PROCTL_DMAS_ADMA2 (2 << USDHC_PROCTL_DMAS_SHIFT) /* ADMA2 is selected */ + + /* Bits 10-25: Reserved */ +#define USDHC_PROCTL_SABGREQ (1 << 16) /* Bit 16: Stop At Block Gap Request */ +#define USDHC_PROCTL_CREQ (1 << 17) /* Bit 17: Continue Request */ +#define USDHC_PROCTL_RWCTL (1 << 18) /* Bit 18: Read Wait Control */ +#define USDHC_PROCTL_IABG (1 << 19) /* Bit 19: Interrupt At Block Gap */ +#define USDHC_PROCTL_RDDONENO8CLK (1 << 20) /* Bit 20: Read done to 8 clock */ +#define USDHC_PROCTL_RESV2023 (4 << 21) /* Bits 21-23: Reserved, write as 0x100 */ +#define USDHC_PROCTL_WECINT (1 << 24) /* Bit 24: Wakeup Event Enable On Card Interrupt */ +#define USDHC_PROCTL_WECINS (1 << 25) /* Bit 25: Wakeup Event Enable On SD Card Insertion */ +#define USDHC_PROCTL_WECRM (1 << 26) /* Bit 26: Wakeup Event Enable On SD Card Removal */ + /* Bits 27-29: Reserved */ +#define USDHC_PROTCTL_NEBLKRD (1 << 30) /* Bit 30: Non-exect block read */ + /* Bit 31: Reserved */ + +/* System Control Register */ + +#define USDHC_SYSCTL_RES0 (0x0F << 0) /* Bit 0-3: Reserved, set to 1 */ +#define USDHC_SYSCTL_DVS_SHIFT (4) /* Bits 4-7: Divisor */ +#define USDHC_SYSCTL_DVS_MASK (0x0f << USDHC_SYSCTL_DVS_SHIFT) +# define USDHC_SYSCTL_DVS_DIV(n) (((n) - 1) << USDHC_SYSCTL_DVS_SHIFT) /* Divide by n, n=1,2,15,16 */ + +#define USDHC_SYSCTL_SDCLKFS_SHIFT (8) /* Bits 8-15: SDCLK Frequency Select */ +#define USDHC_SYSCTL_SDCLKFS_MASK (0xff << USDHC_SYSCTL_SDCLKFS_SHIFT) +# define USDHC_SYSCTL_SDCLKFS_BYPASS (0x00 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Bypass the prescaler */ +# define USDHC_SYSCTL_SDCLKFS_DIV2 (0x01 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 2 */ +# define USDHC_SYSCTL_SDCLKFS_DIV4 (0x02 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 4 */ +# define USDHC_SYSCTL_SDCLKFS_DIV8 (0x04 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 8 */ +# define USDHC_SYSCTL_SDCLKFS_DIV16 (0x08 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 16 */ +# define USDHC_SYSCTL_SDCLKFS_DIV32 (0x10 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 32 */ +# define USDHC_SYSCTL_SDCLKFS_DIV64 (0x20 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 64 */ +# define USDHC_SYSCTL_SDCLKFS_DIV128 (0x40 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 128 */ +# define USDHC_SYSCTL_SDCLKFS_DIV256 (0x80 << USDHC_SYSCTL_SDCLKFS_SHIFT) /* Base clock / 256 */ + +#define USDHC_SYSCTL_DTOCV_SHIFT (16) /* Bits 16-19: Data Timeout Counter Value */ +#define USDHC_SYSCTL_DTOCV_MASK (0xf << USDHC_SYSCTL_DTOCV_SHIFT) +# define USDHC_SYSCTL_DTOCV_PWR32 (0x0 << USDHC_SYSCTL_DTOCV_SHIFT) /* SDCLK x 2^32 */ +# define USDHC_SYSCTL_DTOCV_PWR33 (0x1 << USDHC_SYSCTL_DTOCV_SHIFT) /* SDCLK x 2^33 */ +# define USDHC_SYSCTL_DTOCV_PWR18 (0x2 << USDHC_SYSCTL_DTOCV_SHIFT) /* SDCLK x 2^18 */ +# define USDHC_SYSCTL_DTOCV_PWR19 (0x3 << USDHC_SYSCTL_DTOCV_SHIFT) /* SDCLK x 2^19 */ +# define USDHC_SYSCTL_DTOCV_PWR29 (0xd << USDHC_SYSCTL_DTOCV_SHIFT) /* SDCLK x 2^29 */ +# define USDHC_SYSCTL_DTOCV_PWR30 (0xe << USDHC_SYSCTL_DTOCV_SHIFT) /* SDCLK x 2^30 */ +# define USDHC_SYSCTL_DTOCV_PWR31 (0xf << USDHC_SYSCTL_DTOCV_SHIFT) /* SDCLK x 2^31 */ + + /* Bits 20-21: Reserved */ +#define USDHC_SYSCTL_RSTF (1 << 22) /* Bit 24: Reset the async FIFO */ +#define USDHC_SYSCTL_IPPRSTN (1 << 23) /* Bit 23: Card /reset (default 1) */ +#define USDHC_SYSCTL_RSTA (1 << 24) /* Bit 24: Software Reset For ALL */ +#define USDHC_SYSCTL_RSTC (1 << 25) /* Bit 25: Software Reset For CMD Line */ +#define USDHC_SYSCTL_RSTD (1 << 26) /* Bit 26: Software Reset For DAT Line */ +#define USDHC_SYSCTL_INITA (1 << 27) /* Bit 27: Initialization Active */ +#define USDHC_SYSCTL_RSTT (1 << 28) /* Bit 28: Reset tuning */ + /* Bits 29-31: Reserved */ + +/* Interrupt Status Register, Interrupt Status Enable Register and + * Interrupt Signal Enable Register + * Common interrupt bit definitions + */ + +#define USDHC_INT_CC (1 << 0) /* Bit 0: Command Complete */ +#define USDHC_INT_TC (1 << 1) /* Bit 1: Transfer Complete */ +#define USDHC_INT_BGE (1 << 2) /* Bit 2: Block Gap Event */ +#define USDHC_INT_DINT (1 << 3) /* Bit 3: DMA Interrupt */ +#define USDHC_INT_BWR (1 << 4) /* Bit 4: Buffer Write Ready */ +#define USDHC_INT_BRR (1 << 5) /* Bit 5: Buffer Read Ready */ +#define USDHC_INT_CINS (1 << 6) /* Bit 6: Card Insertion */ +#define USDHC_INT_CRM (1 << 7) /* Bit 7: Card Removal */ +#define USDHC_INT_CINT (1 << 8) /* Bit 8: Card Interrupt */ + /* Bits 9-11: Reserved */ +#define USDHC_INT_RTR (1 << 12) /* Bit 12: Re-tuning event */ +#define USDHC_INT_TP (1 << 13) /* Bit 13: Tuning pass */ +#define USDHC_INT_CQI (1 << 14) /* Bit 14: Command queuing interrupt */ +#define USDHC_INT_STATUS (1 << 15) /* Bit 15: Error Interrupt Status / Reserved */ +#define USDHC_INT_CTOE (1 << 16) /* Bit 16: Command Timeout Error */ +#define USDHC_INT_CCE (1 << 17) /* Bit 17: Command CRC Error */ +#define USDHC_INT_CEBE (1 << 18) /* Bit 18: Command End Bit Error */ +#define USDHC_INT_CIE (1 << 19) /* Bit 19: Command Index Error */ +#define USDHC_INT_DTOE (1 << 20) /* Bit 20: Data Timeout Error */ +#define USDHC_INT_DCE (1 << 21) /* Bit 21: Data CRC Error */ +#define USDHC_INT_DEBE (1 << 22) /* Bit 22: Data End Bit Error */ + /* Bit 23: Reserved */ +#define USDHC_INT_AC12E (1 << 24) /* Bit 24: Auto CMD12 Error */ + /* Bit 25: Reserved */ +#define USDHC_INT_TNE (1 << 26) /* Bit 26: Tuning error */ + /* Bit 27: Reserved */ +#define USDHC_INT_DMAE (1 << 28) /* Bit 28: DMA Error */ + /* Bits 29-31: Reserved */ +#define USDHC_INT_ALL 0x117f01ff + +/* Auto CMD12 Error Status Register */ + +#define USDHC_AC12ERR_NE (1 << 0) /* Bit 0: Auto CMD12 Not Executed */ +#define USDHC_AC12ERR_TOE (1 << 1) /* Bit 1: Auto CMD12/23 Timeout Error */ +#define USDHC_AC12ERR_CE (1 << 2) /* Bit 2: Auto CMD12/23 CRC Error */ +#define USDHC_AC12ERR_EBE (1 << 3) /* Bit 3: Auto CMD12/23 End Bit Error */ +#define USDHC_AC12ERR_IE (1 << 4) /* Bit 4: Auto CMD12/23 Index Error */ + /* Bits 5-6: Reserved */ +#define USDHC_AC12ERR_CNI (1 << 7) /* Bit 7: Command Not Issued By Auto CMD12 Error */ + /* Bits 8-21: Reserved */ +#define USDHC_AC12ERR_EXECUTE_TUNING (1 << 22) /* Bit 22: Execute Tuning */ +#define USDHC_AC12ERR_SMP_CLK_SEL (1 << 23) /* Bit 23: Sample clock sel */ + /* Bits 24-31: Reserved */ + +/* Host Controller Capabilities */ + +#define USDHC_HTCAPBLT_SDR50 (1 << 0) /* Bit 0: SDR50 support indication */ +#define USDHC_HTCAPBLT_SDR104 (1 << 1) /* Bit 1: SDR104 support indication */ +#define USDHC_HTCAPBLT_DDR50 (1 << 2) /* Bit 2: DDR50 support indication */ + /* Bits 3-7: Reserved */ + /* Bits 8-12: Reserved */ +#define USDHC_HTCAPBLT_USE_TUNING_SDR50 (1 << 13) /* Bit 13: Use tuning for SDR50 */ +#define USDHC_HTCAPBLT_MBL_SHIFT (16) /* Bits 16-18: Max Block Length */ +#define USDHC_HTCAPBLT_MBL_MASK (7 << USDHC_HTCAPBLT_MBL_SHIFT) +# define USDHC_HTCAPBLT_MBL_512BYTES (0 << USDHC_HTCAPBLT_MBL_SHIFT) +# define USDHC_HTCAPBLT_MBL_1KB (1 << USDHC_HTCAPBLT_MBL_SHIFT) +# define USDHC_HTCAPBLT_MBL_2KB (2 << USDHC_HTCAPBLT_MBL_SHIFT) +# define USDHC_HTCAPBLT_MBL_4KB (3 << USDHC_HTCAPBLT_MBL_SHIFT) + /* Bit 19: Reserved */ +#define USDHC_HTCAPBLT_ADMAS (1 << 20) /* Bit 20: ADMA Support */ +#define USDHC_HTCAPBLT_HSS (1 << 21) /* Bit 21: High Speed Support */ +#define USDHC_HTCAPBLT_DMAS (1 << 22) /* Bit 22: DMA Support */ +#define USDHC_HTCAPBLT_SRS (1 << 23) /* Bit 23: Suspend/Resume Support */ +#define USDHC_HTCAPBLT_VS33 (1 << 24) /* Bit 24: Voltage Support 3.3 V */ +#define USDHC_HTCAPBLT_VS30 (1 << 25) /* Bit 25: Voltage Support 3.0 V */ + /* Bits 26-31: Reserved */ + +/* Watermark Level Register */ + +#define USDHC_WML_RD_SHIFT (0) /* Bits 0-7: Read Watermark Level */ +#define USDHC_WML_RD_MASK (0xff << USDHC_WML_RDWML_SHIFT) +# define USDHC_WML_RD(n) ((n) << SDHC_WML_RDWML_SHIFT) + /* Bits 8-15: Reserved */ +#define USDHC_WML_WR_SHIFT (16) /* Bits 16-23: Write Watermark Level */ +#define USDHC_WML_WR_MASK (0xff << USDHC_WML_WRWML_SHIFT) +# define USDHC_WML_WR(n) ((n) << SDHC_WML_WRWML_SHIFT) + /* Bits 24-31: Reserved */ + +/* Mixer Control Register */ + +#define USDHC_MC_DEFAULTVAL (0x80000000) /* Bit 31 is always set */ +#define USDHC_MC_DMAEN (1 << 0) /* Bit 0: DMA Enable */ +#define USDHC_MC_BCEN (1 << 1) /* Bit 1: Block Count Enable */ +#define USDHC_MC_AC12EN (1 << 2) /* Bit 2: Auto CMD12 Enable */ +#define USDHC_MC_DDR_EN (1 << 3) /* Bit 3: DDR mode enable */ +#define USDHC_MC_DTDSEL (1 << 4) /* Bit 4: Data Transfer direction select */ +#define USDHC_MC_MSBSEL (1 << 5) /* Bit 5: Multi/single block select */ +#define USDHC_MC_NIBBLE_POS (1 << 6) /* Bit 6: Nibble position for DDR 4 bit */ +#define USDHC_MC_AC23EN (1 << 7) /* Bit 7: Auto CMD23 Enable */ + /* Bits 8-21: Reserved */ +#define USDHC_MC_EXE_TUNE (1 << 22) /* Bit 22: Execute Tuning */ +#define USDHC_MC_SMP_CLK_SEL (1 << 23) /* Bit 23: SMP Clock Sel */ +#define USDHC_MC_AUTO_TUNE_EN (1 << 24) /* Bit 24: Auto tune enable */ +#define USDHC_MC_FBCLK_SEL (1 << 25) /* Bit 25: Feedback clock source selection */ +#define USDHC_MC_HS400EN (1 << 26) /* Bit 26: Enable HS400 mode */ +#define USDHC_MC_EHS400EN (1 << 27) /* Bit 27: Enable enhance HS400 mode */ + /* Bits 28-31: reserved */ + +/* Force Event Register */ + +#define USDHC_FEVT_AC12NE (1 << 0) /* Bit 0: Force Event Auto Command 12 Not Executed */ +#define USDHC_FEVT_AC12TOE (1 << 1) /* Bit 1: Force Event Auto Command 12 Time Out Error */ +#define USDHC_FEVT_AC12CE (1 << 2) /* Bit 2: Force Event Auto Command 12 CRC Error */ +#define USDHC_FEVT_AC12EBE (1 << 3) /* Bit 3: Force Event Auto Command 12 End Bit Error */ +#define USDHC_FEVT_AC12IE (1 << 4) /* Bit 4: Force Event Auto Command 12 Index Error */ + /* Bits 5-6: Reserved */ +#define USDHC_FEVT_CNIBAC12E (1 << 7) /* Bit 7: Force Event Command Not Executed By Auto Command 12 Error */ + /* Bits 8-15: Reserved */ +#define USDHC_FEVT_CTOE (1 << 16) /* Bit 16: Force Event Command Time Out Error */ +#define USDHC_FEVT_CCE (1 << 17) /* Bit 17: Force Event Command CRC Error */ +#define USDHC_FEVT_CEBE (1 << 18) /* Bit 18: Force Event Command End Bit Error */ +#define USDHC_FEVT_CIE (1 << 19) /* Bit 19: Force Event Command Index Error */ +#define USDHC_FEVT_DTOE (1 << 20) /* Bit 20: Force Event Data Time Out Error */ +#define USDHC_FEVT_DCE (1 << 21) /* Bit 21: Force Event Data CRC Error */ +#define USDHC_FEVT_DEBE (1 << 22) /* Bit 22: Force Event Data End Bit Error */ + /* Bit 23: Reserved */ +#define USDHC_FEVT_AC12E (1 << 24) /* Bit 24: Force Event Auto Command 12 Error */ + /* Bit 25: Reserved */ +#define USDHC_FEVT_TTNE (1 << 26) /* Bit 26: Force tuning error */ + /* Bit 27: reserved */ +#define USDHC_FEVT_DMAE (1 << 28) /* Bit 28: Force Event DMA Error */ + /* Bits 29-30: Reserved */ +#define USDHC_FEVT_CINT (1 << 31) /* Bit 31: Force Event Card Interrupt */ + +/* ADMA Error Status Register */ + +#define USDHC_ADMAES_SHIFT (0) /* Bits 0-1: ADMA Error State (when ADMA Error is occurred) */ +#define USDHC_ADMAES_MASK (3 << USDHC_ADMAES_ADMAES_SHIFT) +# define USDHC_ADMAES_STOP (0 << USDHC_ADMAES_ADMAES_SHIFT) /* Stop DMA */ +# define USDHC_ADMAES_FDS (1 << USDHC_ADMAES_ADMAES_SHIFT) /* Fetch descriptor */ +# define USDHC_ADMAES_CADR (2 << USDHC_ADMAES_ADMAES_SHIFT) /* Change address */ +# define USDHC_ADMAES_TFR (3 << USDHC_ADMAES_ADMAES_SHIFT) /* Transfer data */ + +#define USDHC_ADMAES_LME (1 << 2) /* Bit 2: ADMA Length Mismatch Error */ +#define USDHC_ADMAES_DCE (1 << 3) /* Bit 3: ADMA Descriptor Error */ + /* Bits 4-31: Reserved */ + +/* ADMA System Address Register */ + +#define USDHC_ADSADDR_SHIFT (0) /* Bits 1-31: ADMA System Address */ +#define USDHC_ADSADDR_MASK (0xfffffffc) /* Bits 0-1: Reserved */ + +/* Delay Line Control */ + +#define USDHC_DL_CTRL_EN (1 << 0) /* Bit 0: Delay Line enable */ +#define USDHC_DL_CTRL_RST (1 << 1) /* Bit 1: Delay line reset */ +#define USDHC_DL_CTRL_SLV_FORCE_UP (1 << 2) /* Bit 2: SLV Force update */ +#define USDHC_DL_SLV_DLY_TGT0_SHIFT (3) /* Bits 3-6: Delay Target 0 */ +#define USDHC_DL_SLV_DLY_TGT0_MASK (0xf << USDHC_DL_SLV_DLY_TGT0_SHIFT) +# define USDHC_DL_SLV_DLY_TGT0(n) ((n) << USDHC_DL_SLV_DLY_TGT0_SHIFT) +#define USDHC_DL_CTRL_SLV_UPD (1 << 7) /* Bit 7: Delay Control Gate update */ +#define USDHC_DL_CTRL_SLV_OVR (1 << 8) /* Bit 8: Delay Control Gate override */ +#define USDHC_DL_CTRL_OVR_VAL_SHIFT (9) /* Bits 9-15: Override Value */ +#define USDHC_DL_CTRL_OVR_VAL_MASK (0x7f << USDHC_DL_CTRL_OVR_VAL_SHIFT) +# define USDHC_DL_CTRL_OVR_VAL(n) ((n) << USDHC_DL_CTRL_OVR_VAL_SHIFT) +#define USDHC_DL_SLV_DLY_TGT1_SHIFT (16) /* Bits 16-18: Delay Target 1 */ +#define USDHC_DL_SLV_DLY_TGT1_MASK (0x7 << USDHC_DL_SLV_DLY_TGT1_SHIFT) +# define USDHC_DL_SLV_DLY_TGT1(n) ((n) << USDHC_DL_SLV_DLY_TGT1_SHIFT) + /* Bit 19: Reserved */ +#define USDHC_DL_CTRL_SLV_UPDINT_SHIFT (20) /* Bits 20-27: DLL Control SLV Update Interval */ +#define USDHC_DL_CTRL_SLV_UPDINT_MASK (0xff << USDHC_DL_CTRL_SLV_UPDINT_SHIFT) +# define USDHC_DL_CTRL_SLV_UPDINT(n) ((n) << USDHC_DL_CTRL_SLV_UPDINT_SHIFT) +#define USDHC_DL_CTRL_REF_UPDINT_SHIFT (28) /* Bits 28-31: DLL Control Reference Update Interval */ +#define USDHC_DL_CTRL_REF_UPDINT_MASK (0xf << USDHC_DL_CTRL_REF_UPDINT_SHIFT) +# define USDHC_DL_CTRL_REF_UPDINT(n) ((n)<< USDHC_DL_CTRL_REF_UPDINT_SHIFT) + +/* Delay Line Status */ + +#define USDHC_DL_STAT_SLV_LOCK (1 << 0) /* Bit 0: Slave delay-line lock status */ +#define USDHC_DL_STAT_REF_LOCK (1 << 1) /* Bit 1: Reference delay-line lock status */ +#define USDHC_DL_STAT_SLV_SEL_SHIFT (2) /* Bits 2-8: Slave delay line select status */ +#define USDHC_DL_STAT_SLV_SEL_MASK (0x7f << USDHC_DL_STAT_SLV_SEL_SHIFT) +# define USDHC_DL_STAT_SLV_SEL(n) ((n) << USDHC_DL_STAT_SLV_SEL_SHIFT) +#define USDHC_DL_STAT_REF_SEL_SHIFT (9) /* Bits 9-15: Reference delay line select taps */ +#define USDHC_DL_STAT_REF_SEL_MASK (0x7f << USDHC_DL_STAT_REF_SEL_SHIFT) +# define USDHC_DL_STAT_REF_SEL(n) ((n) << USDHC_DL_STAT_REF_SEL_SHIFT) + /* Bits 16-31: Reserved */ + +/* Clk tuning control and status */ + +#define USDHC_CLKTUNE_CS_DCS_POST_SHIFT (0) /* Bits 0-3: Set delay cells between CLK_OUT and CLK_POST*/ +#define USDHC_CLKTUNE_CS_DCS_POST_MASK (0xf << USDHC_CLKTUNE_CS_DCS_POST_SHIFT) +# define USDHC_CLKTUNE_CS_DCS_POST(n) ((n) << USDHC_CLKTUNE_CS_DCS_POST_SHIFT) +#define USDHC_CLKTUNE_CS_DCS_OUT_SHIFT (4) /* Bits 4-7: Set delay cells between CLK_PRE and CLK_OUT */ +#define USDHC_CLKTUNE_CS_DCS_OUT_MASK (0xf << USDHC_CLKTUNE_CS_DCS_OUT_SHIFT) +# define USDHC_CLKTUNE_CS_DCS_OUT(n) ((n) << USDHC_CLKTUNE_CS_DCS_OUT_SHIFT) +#define USDHC_CLKTUNE_CS_DCS_PRE_SHIFT (8) /* Bits 8-14: Set celay cells between the feedback clock and CLK_PRE */ +#define USDHC_CLKTUNE_CS_DCS_PRE_MASK (0x7f << USDHC_CLKTUNE_CS_DCS_PRE_SHIFT) +# define USDHC_CLKTUNE_CS_DCS_PRE(n) ((n) << USDHC_CLKTUNE_CS_DCS_PRE_SHIFT) +#define USDHC_CLKTUNE_CS_NXT_ERR (1 << 15) /* Bit 15: NXT error */ +#define USDHC_CLKTUNE_CS_TS_POST_SHIFT (16) /* Bits 16-19: Delay cells between CLK_OUT and CLK_POST */ +#define USDHC_CLKTUNE_CS_TS_POST_MASK (0xf << USDHC_CLKTUNE_CS_TS_POST_SHIFT) +# define USDHC_CLKTUNE_CS_TS_POST(n) ((n) << USDHC_CLKTUNE_CS_TS_POST_SHIFT) +#define USDHC_CLKTUNE_CS_TS_OUT_SHIFT (20) /* Bits 20-23: Delay cells between CLK_PRE and CLK_OUT */ +#define USDHC_CLKTUNE_CS_TS_OUT_MASK (0xf << USDHC_CLKTUNE_CS_TS_OUT_SHIFT) +# define USDHC_CLKTUNE_CS_TS_OUT(n) ((n) << USDHC_CLKTUNE_CS_TS_OUT_SHIFT) +#define USDHC_CLKTUNE_CS_TS_PRE_SHIFT (24) /* Bits 24-30: Delay cells between the feedback clock and CLK_PRE */ +#define USDHC_CLKTUNE_CS_TS_PRE_MASK (0x7f << USDHC_CLKTUNE_CS_TS_PRE_SHIFT) +# define USDHC_CLKTUNE_CS_TS_PRE_OUT(n) ((n) << USDHC_CLKTUNE_CS_TS_PRE_SHIFT) +#define USDHC_CLKTUNE_CS_PRE_ERR (1 << 31) /* Bit 31: PRE error */ + +/* Strobe DLL control */ + +/* Strobe DLL status */ + +/* Vendor Specific Register */ + + /* Bit 0: Reserved */ +#define USHDC_VENDOR_VSELECT (1 << 1) /* Bit 1: Voltage selection */ + /* Bit 2: Reserved */ +#define USDHC_VENDOR_CHKBUSY_ON (1 << 3) /* Bit 3: Enable Check busy */ + /* Bit 4-7: Reserved */ +#define USDHC_VENDOR_FRC_SDCLK_ON (1 << 8) /* Bit 8: Force clock active */ + /* Bits 9-14: Reserved */ +#define USDHC_VENDOR_CRC_CHECK_OFF (1 << 15) /* Bit 15: Switch off CRC checking */ + /* Bits 16:30 Reserved */ +#define USHDC_VENDOR_DEFAULTVAL (0x20000000) /* Bit 29 is always set */ +#define USDHC_VENDOR_CMDBYTEACC_ON (1 << 31) /* Bit 31: Enable command byte access */ + +/* MMC Boot Register */ + +#define USDHC_MMCBOOT_DTOCVACK_SHIFT (0) /* Bits 0-3: Boot ACK time out counter value */ +#define USDHC_MMCBOOT_DTOCVACK_MASK (0xf << USDHC_MMCBOOT_DTOCVACK_SHIFT) +# define USDHC_MMCBOOT_DTOCVACK_PWR32 (0x0 << USDHC_MMCBOOT_DTOCVACK_SHIFT) /* SDCLK x 2^32 */ +# define USDHC_MMCBOOT_DTOCVACK_PWR33 (0x1 << USDHC_MMCBOOT_DTOCVACK_SHIFT) /* SDCLK x 2^33 */ +# define USDHC_MMCBOOT_DTOCVACK_PWR18 (0x2 << USDHC_MMCBOOT_DTOCVACK_SHIFT) /* SDCLK x 2^18 */ +# define USDHC_MMCBOOT_DTOCVACK_PWR19 (0x3 << USDHC_MMCBOOT_DTOCVACK_SHIFT) /* SDCLK x 2^19 */ +# define USDHC_MMCBOOT_DTOCVACK_PWR20 (0x4 << USDHC_MMCBOOT_DTOCVACK_SHIFT) /* SDCLK x 2^20 */ +# define USDHC_MMCBOOT_DTOCVACK_PWR21 (0x5 << USDHC_MMCBOOT_DTOCVACK_SHIFT) /* SDCLK x 2^21 */ +# define USDHC_MMCBOOT_DTOCVACK_PWR22 (0x6 << USDHC_MMCBOOT_DTOCVACK_SHIFT) /* SDCLK x 2^22 */ +# define USDHC_MMCBOOT_DTOCVACK_PWR23 (0x7 << USDHC_MMCBOOT_DTOCVACK_SHIFT) /* SDCLK x 2^23 */ +# define USDHC_MMCBOOT_DTOCVACK_PWR30 (0xe << USDHC_MMCBOOT_DTOCVACK_SHIFT) /* SDCLK x 2^30 */ +# define USDHC_MMCBOOT_DTOCVACK_PWR31 (0xf << USDHC_MMCBOOT_DTOCVACK_SHIFT) /* SDCLK x 2^31 */ + +#define USDHC_MMCBOOT_BOOTACK (1 << 4) /* Bit 4: Boot ack mode select */ +#define USDHC_MMCBOOT_BOOTMODE (1 << 5) /* Bit 5: Boot mode select */ +#define USDHC_MMCBOOT_BOOTEN (1 << 6) /* Bit 6: Boot mode enable */ +#define USDHC_MMCBOOT_AUTOSABGEN (1 << 7) /* Bit 7: Enable auto stop at block gap function */ +#define USDHC_MMCBOOT_DISABLETO (1 << 8) /* Bit 8: Timeout enable */ + /* Bits 9-15: Reserved */ +#define USDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16) /* Bits 16-31: Stop at block gap value of automatic mode */ +#define USDHC_MMCBOOT_BOOTBLKCNT_MASK (0xffff << USDHC_MMCBOOT_BOOTBLKCNT_SHIFT) +#define USDHC_MMCBOOT_BOOTBLKCNT(n) ((n) << USDHC_MMCBOOT_BOOTBLKCNT_SHIFT) + +/* Vendor specific register 2 */ + + /* Bits 0-2: Reserved */ +#define USDHC_VS2_CARDINTD3 (1 << 3) /* Bit 3: Card interrupt detection test */ +#define USDHC_VS2_TUNINGBITEN_SHIFT (4) /* Bits 4-5: Tuning bit enable */ +#define USDHC_VS2_TUNINGBITEN_MASK (0x3 << USDHC_VS2_TUNINGBITEN_SHIFT) +# define USDHC_VS2_TUNINGBITEN_30 (0 << USDHC_VS2_TUNINGBITEN_SHIFT) /* Enable Tuning circuit for DATA[3:0] */ +# define USDHC_VS2_TUNINGBITEN_70 (1 << USDHC_VS2_TUNINGBITEN_SHIFT) /* Enable Tuning circuit for DATA[7:0] */ +# define USDHC_VS2_TUNINGBITEN_0 (2 << USDHC_VS2_TUNINGBITEN_SHIFT) /* Enable Tuning circuit for DATA[0] */ + +#define USDHC_VS2_TUNINGCMDEN (1 << 6) /* Bit 6: Tuning CMD enable */ + /* Bits 7-9: Reserved */ +#define USDHC_VS2_HS400WRCLKSEN (1 << 10) /* Bit 10: HS400 write clock stop enable */ +#define USDHC_VS2_HS400RDCLKSEN (1 << 11) /* Bit 11: HS400 read clock stop enable */ +#define USDHC_VS2_ACMD23ARGU2 (1 << 12) /* Bit 12: Argument 2 register enable for ACMD23 */ + /* Bit 13: Reserved */ +#define USDHC_VS2_BUSRESET (1 << 14) /* Bit 14: Bus reset (undocumented!) */ +#define USDHC_VS2_32KCLKEN (1 << 15) /* Bit 15: Use low power clock for card detection */ +#define USDHC_VS2_FBCLK_TAP_SEL_SHIFT (16) /* Bits 16-31: Enable extra delay on internal feedback clock */ +#define USDHC_VS2_FBCLK_TAP_SEL_MASK (0xffff << USDHC_VS2_FBCLK_TAP_SEL_SHIFT) +#define USDHC_VS2_FBCLK_TAP_SEL(n) ((n) << USDHC_VS2_FBCLK_TAP_SEL_SHIFT) + +/* Tuning Control Register */ + +#define USDHC_TC_STARTTAP_SHIFT (0) /* Bits 0-6: Start TAP for CMD19 tuning */ +#define USDHC_TC_STARTTAP_MASK (0x7f << USDHC_TC_STARTTAP_SHIFT) +# define USDHC_TC_STARTTAP(n) ((n) << USDHC_TC_STARTTAP_SHIFT) +#define USDHC_TC_DIS_CMD (1 << 7) /* Bit 7: Disable command check for standard tuning */ +#define USDHC_TC_COUNT_SHIFT (8) /* Bits 8-15: Count for CMD19 tuning */ +#define USDHC_TC_COUNT_MASK (0xff << USDHC_TC_COUNT_SHIFT) +# define USDHC_TC_COUNT(n) ((n) << USDHC_TC_COUNT_SHIFT) + /* Bit 19: Reserved */ +#define USDHC_TC_WINDOW_SHIFT (20) /* Bits 20-22: Tuning window */ +#define USDHC_TC_WINDOW_MASK (0x7 << USDHC_TC_WINDOWS_SHIFT) +# define USDHC_TC_WINDOW(n) ((n) << USDHC_TC_WINDOW_SHIFT) + /* Bit 23: Reserved */ +#define USDHC_TC_TUNINGEN (1 << 24) /* Bit 24: Tuning enable */ + /* Bits 25-31: Reserved */ + +/* Command Queuing Version */ + +/* Command Queuing Capabilities */ + +/* Command Queuing Configuration */ + +/* Command Queuing Control */ + +/* Command Queuing Interrupt Status */ + +/* Command Queuing Interrupt Status Enable */ + +/* Command Queuing Interrupt Signal Enable */ + +/* Command Queuing Interrupt Coalescing */ + +/* Command Queuing Task Descriptor List Base Address */ + +/* Command Queuing Task Descriptor List Base Address Upper 32 Bits */ + +/* Command Queuing Task Doorbell */ + +/* Command Queuing Task Completion Notification */ + +/* Command Queuing Device Queue Status */ + +/* Command Queuing Device Pending Tasks */ + +/* Command Queuing Task Clear */ + +/* Command Queuing Send Status Configuration 1 */ + +/* Command Queuing Send Status Configuration 2 */ + +/* Command Queuing Command Response for Direct-Command Task */ + +/* Command Queuing Response Mode Error Mask */ + +/* Command Queuing Task Error Information */ + +/* Command Queuing Command Response Index */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_USDHC_H */ diff --git a/arch/arm64/src/imx9/imx9_boot.c b/arch/arm64/src/imx9/imx9_boot.c new file mode 100644 index 0000000000000..bb8b8093f080d --- /dev/null +++ b/arch/arm64/src/imx9/imx9_boot.c @@ -0,0 +1,149 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#ifdef CONFIG_PAGING +# include +#endif + +#include +#include "arm64_arch.h" +#include "arm64_internal.h" +#include "arm64_mmu.h" + +#include "imx9_boot.h" +#include "imx9_clockconfig.h" +#include "imx9_serial.h" +#include "imx9_gpio.h" +#include "imx9_lowputc.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct arm_mmu_region g_mmu_regions[] = +{ + MMU_REGION_FLAT_ENTRY("DEVICE_REGION", + CONFIG_DEVICEIO_BASEADDR, CONFIG_DEVICEIO_SIZE, + MT_DEVICE_NGNRNE | MT_RW | MT_SECURE), + + MMU_REGION_FLAT_ENTRY("DRAM0_S0", + CONFIG_RAMBANK1_ADDR, CONFIG_RAMBANK1_SIZE, + MT_NORMAL | MT_RW | MT_SECURE), + + MMU_REGION_FLAT_ENTRY("OCRAM", + CONFIG_OCRAM_BASE_ADDR, CONFIG_OCRAM_SIZE, + MT_NORMAL | MT_RW | MT_SECURE), + + MMU_REGION_FLAT_ENTRY("FSPI_PERIPHERAL", + CONFIG_FSPI_PER_BASEADDR, CONFIG_FSPI_PER_SIZE, + MT_DEVICE_NGNRNE | MT_RW | MT_SECURE), +}; + +const struct arm_mmu_config g_mmu_config = +{ + .num_regions = nitems(g_mmu_regions), + .mmu_regions = g_mmu_regions, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm64_el_init + * + * Description: + * The function called from arm64_head.S at very early stage for these + * platform, it's use to: + * - Handling special hardware initialize routine which is need to + * run at high ELs + * - Initialize system software such as hypervisor or security firmware + * which is need to run at high ELs + * + ****************************************************************************/ + +void arm64_el_init(void) +{ +#if (CONFIG_ARCH_ARM64_EXCEPTION_LEVEL == 3) + /* At EL3, cntfrq_el0 is uninitialized. It must be set. */ + + write_sysreg(CONFIG_BOOTLOADER_SYS_CLOCK, cntfrq_el0); +#endif +} + +/**************************************************************************** + * Name: arm64_chip_boot + * + * Description: + * Complete boot operations started in arm64_head.S + * + ****************************************************************************/ + +void arm64_chip_boot(void) +{ + /* MAP IO and DRAM, enable MMU. */ + + arm64_mmu_init(true); + + /* Initialize system clocks to some sensible state */ + + imx9_clockconfig(); + + /* Do UART early initialization & pin muxing */ + +#ifdef CONFIG_IMX9_LPUART + imx9_lowsetup(); +#endif + +#if defined(CONFIG_SMP) || defined(CONFIG_ARCH_HAVE_PSCI) + arm64_psci_init("smc"); +#endif + + /* Initialize pin interrupt support */ + +#ifdef CONFIG_IMX9_GPIO_IRQ + imx9_gpioirq_initialize(); +#endif + + /* Perform board-specific device initialization. This would include + * configuration of board specific resources such as GPIOs, LEDs, etc. + */ + + imx9_board_initialize(); + +#ifdef USE_EARLYSERIALINIT + /* Perform early serial initialization if we are going to use the serial + * driver. + */ + + arm64_earlyserialinit(); +#endif +} diff --git a/arch/arm64/src/imx9/imx9_boot.h b/arch/arm64/src/imx9/imx9_boot.h new file mode 100644 index 0000000000000..cfd10b7e1b2b1 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_boot.h @@ -0,0 +1,79 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_boot.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_BOOT_H +#define __ARCH_ARM64_SRC_IMX9_IMX9_BOOT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: imx9_board_initialize + * + * Description: + * All i.MX9 architectures must provide the following entry point. This + * entry point is called in the initialization phase -- after + * imx_memory_initialize and after all memory has been configured and + * mapped but before any devices have been initialized. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx9_board_initialize(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM64_SRC_IMX9_IMX9_BOOT_H */ diff --git a/arch/arm64/src/imx9/imx9_ccm.c b/arch/arm64/src/imx9/imx9_ccm.c new file mode 100644 index 0000000000000..1d8cef9562462 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_ccm.c @@ -0,0 +1,197 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_ccm.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "barriers.h" + +#include "arm64_internal.h" +#include "imx9_ccm.h" + +#include "hardware/imx9_ccm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define mb() \ + do \ + { \ + ARM64_DSB(); \ + ARM64_ISB(); \ + } \ + while (0) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_ccm_configure_root_clock + * + * Description: + * Change root clock source and divider. Leaves the clock running state + * unaltered. + * + * Input Parameters: + * root - The root clock index. + * src - The root clock MUX source. + * div - The root clock divider. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int imx9_ccm_configure_root_clock(int root, int src, uint32_t div) +{ + uint32_t value; + int i; + + if (root >= CCM_CR_COUNT || div == 0 || div > 255) + { + return -EINVAL; + } + + /* Find the corresponding MUX register value for root and source */ + + for (i = 0; i < ROOT_MUX_MAX; i++) + { + if (g_ccm_root_mux[root][i] == src) + { + break; + } + } + + if (i == ROOT_MUX_MAX) + { + return -EINVAL; + } + + /* Set the new value */ + + value = CCM_CR_CTRL_MUX_SRCSEL(i) | CCM_CR_CTRL_DIV(div); + putreg32(value, IMX9_CCM_CR_CTRL(root)); + mb(); + + /* Wait for the clock state change */ + + while (getreg32(IMX9_CCM_CR_STAT0(root)) & CCM_CR_STAT0_CHANGING); + + return OK; +} + +/**************************************************************************** + * Name: imx9_ccm_root_clock_on + * + * Description: + * Enable / disable root clock. + * + * Input Parameters: + * root - The root clock index. + * enabled - True enables the clock; false disables it. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int imx9_ccm_root_clock_on(int root, bool enabled) +{ + if (root >= CCM_CR_COUNT) + { + return -EINVAL; + } + + if (enabled) + { + putreg32(CCM_CR_CTRL_OFF, IMX9_CCM_CR_CTRL_CLR(root)); + } + else + { + putreg32(CCM_CR_CTRL_OFF, IMX9_CCM_CR_CTRL_SET(root)); + } + + mb(); + + /* Wait for the clock state change */ + + while (getreg32(IMX9_CCM_CR_STAT0(root)) & CCM_CR_STAT0_CHANGING); + + return OK; +} + +/**************************************************************************** + * Name: imx9_ccm_gate_on + * + * Description: + * Enable / disable clock. + * + * Input Parameters: + * gate - The clock gate index. + * enabled - True enables the clock; false disables it. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int imx9_ccm_gate_on(int gate, bool enabled) +{ + uint32_t value; + + if (gate >= CCM_LPCG_COUNT) + { + return -EINVAL; + } + + /* Make sure direct mode is on, which is what we support */ + + value = getreg32(IMX9_CCM_LPCG_AUTH(gate)); + if (value & CCM_LPCG_AUTH_CPULPM) + { + value &= ~CCM_LPCG_AUTH_CPULPM; + putreg32(value, IMX9_CCM_LPCG_AUTH(gate)); + mb(); + } + + value = enabled ? 1 : 0; + putreg32(value, IMX9_CCM_LPCG_DIR(gate)); + mb(); + + /* Wait for the clock state change */ + + while ((getreg32(IMX9_CCM_LPCG_STAT0(gate)) & CCM_LPCG_STAT0_ON) != value); + + return OK; +} diff --git a/arch/arm64/src/imx9/imx9_ccm.h b/arch/arm64/src/imx9/imx9_ccm.h new file mode 100644 index 0000000000000..fa2017b314a54 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_ccm.h @@ -0,0 +1,88 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_ccm.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_CCM_H +#define __ARCH_ARM64_SRC_IMX9_IMX9_CCM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Name: imx9_ccm_configure_root_clock + * + * Description: + * Change root clock source and divider. Leaves the clock running state + * unaltered. + * + * Input Parameters: + * root - The root clock index. + * src - The root clock MUX source. + * div - The root clock divider. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int imx9_ccm_configure_root_clock(int root, int src, uint32_t div); + +/**************************************************************************** + * Name: imx9_ccm_root_clock_on + * + * Description: + * Enable / disable root clock. + * + * Input Parameters: + * root - The root clock index. + * enabled - True enables the clock; false disables it. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int imx9_ccm_root_clock_on(int root, bool enabled); + +/**************************************************************************** + * Name: imx9_ccm_gate_on + * + * Description: + * Enable / disable clock. + * + * Input Parameters: + * gate - The clock gate index. + * enabled - True enables the clock; false disables it. + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int imx9_ccm_gate_on(int gate, bool enabled); + +#endif /* __ARCH_ARM64_SRC_IMX9_IMX9_CCM_H */ diff --git a/arch/arm64/src/imx9/imx9_clockconfig.c b/arch/arm64/src/imx9/imx9_clockconfig.c new file mode 100644 index 0000000000000..156e1f5a2a966 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_clockconfig.c @@ -0,0 +1,526 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_clockconfig.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "barriers.h" + +#include "arm64_internal.h" +#include "imx9_ccm.h" +#include "imx9_clockconfig.h" + +#include "hardware/imx9_ccm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The base oscillator frequency is 24MHz */ + +#define XTAL_FREQ 24000000u + +/* Common barrier */ + +#define mb() \ + do \ + { \ + ARM64_DSB(); \ + ARM64_ISB(); \ + } \ + while (0) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifdef CONFIG_IMX9_BOOTLOADER +static int pll_init(uintptr_t reg, bool frac, struct pll_parms_s *parm) +{ + uint32_t val; + + /* Bypass and disable PLL */ + + putreg32(PLL_CTRL_CLKMUX_BYPASS, PLL_SET(PLL_CTRL(reg))); + putreg32(PLL_CTRL_CLKMUX_EN | PLL_CTRL_POWERUP, PLL_CLR(PLL_CTRL(reg))); + + /* Set the integer dividers */ + + val = PLL_DIV_RDIV(parm->rdiv) | + PLL_DIV_MFI(parm->mfi) | + PLL_DIV_ODIV(parm->odiv); + + putreg32(val, PLL_DIV(reg)); + + /* Disable spread spectrum */ + + putreg32(PLL_SPREAD_SPECTRUM_ENABLE, PLL_CLR(PLL_SPREAD_SPECTRUM(reg))); + + /* Set the fractional parts */ + + if (frac) + { + putreg32(PLL_NUMERATOR_MFN(parm->mfn), PLL_NUMERATOR(reg)); + putreg32(PLL_DENOMINATOR_MFD(parm->mfd), PLL_DENOMINATOR(reg)); + } + + /* Power it back up and wait for lock */ + + putreg32(PLL_CTRL_POWERUP, PLL_SET(PLL_CTRL(reg))); + mb(); + + while (!(getreg32(PLL_PLL_STATUS(reg)) & PLL_PLL_STATUS_PLL_LOCK)); + + /* Enable PLL and its output */ + + putreg32(PLL_CTRL_CLKMUX_EN, PLL_SET(PLL_CTRL(reg))); + putreg32(PLL_CTRL_CLKMUX_BYPASS, PLL_CLR(PLL_CTRL(reg))); + mb(); + + return OK; +} + +static int pll_pfd_init(uintptr_t reg, int pfd, struct pfd_parms_s *pfdparm) +{ + uint32_t ctrl; + uint32_t div; + uint32_t val; + + /* Determine the PFD register set */ + + switch (pfd) + { + case 0: + ctrl = PLL_DFS_CTRL_0(reg); + div = PLL_DFS_DIV_0(reg); + break; + + case 1: + ctrl = PLL_DFS_CTRL_1(reg); + div = PLL_DFS_DIV_1(reg); + break; + + case 2: + ctrl = PLL_DFS_CTRL_2(reg); + div = PLL_DFS_DIV_2(reg); + break; + + default: + return -EINVAL; + } + + /* Bypass and disable DFS */ + + putreg32(PLL_DFS_BYPASS_EN, PLL_SET(ctrl)); + putreg32(PLL_DFS_CLKOUT_EN | PLL_DFS_CLKOUT_DIVBY2_EN | PLL_DFS_ENABLE, + PLL_CLR(ctrl)); + + /* Set the divider */ + + val = PLL_DFS_MFI(pfdparm->mfi) | PLL_DFS_MFN(pfdparm->mfn); + putreg32(val, PLL_VAL(div)); + + /* Enable (or disable) the divby2 output */ + + if (pfdparm->divby2_en) + { + putreg32(PLL_DFS_CLKOUT_DIVBY2_EN, PLL_SET(ctrl)); + } + else + { + putreg32(PLL_DFS_CLKOUT_DIVBY2_EN, PLL_CLR(ctrl)); + } + + /* Enable DFS and wait for lock */ + + putreg32(PLL_DFS_ENABLE, PLL_SET(ctrl)); + mb(); + + /* Wait until the clock output is valid */ + + while (!(getreg32(PLL_DFS_STATUS(reg)) & (1 << pfd))); + + /* Then disable bypass */ + + putreg32(PLL_DFS_BYPASS_EN, PLL_CLR(ctrl)); + mb(); + + return OK; +} +#endif + +static uint32_t calculate_vco_freq(const struct pll_parms_s *parm, bool frac) +{ + /* Base clock is common for all VCO:s */ + + if (frac) + { + return (uint64_t)XTAL_FREQ * (parm->mfi * parm->mfd + parm->mfn) / + parm->mfd / parm->rdiv; + } + else + { + return (uint64_t)XTAL_FREQ * parm->mfi / parm->rdiv; + } +} + +static uint32_t vco_freq_out(uintptr_t reg, bool frac) +{ + struct pll_parms_s parm; + uint32_t ctrl; + uint32_t status; + uint32_t div; + + /* Check if the PLL on or off */ + + ctrl = getreg32(PLL_CTRL(reg)); + if ((ctrl & PLL_CTRL_POWERUP) == 0) + { + return 0; + } + + /* Check if the PLL is stable */ + + status = getreg32(PLL_PLL_STATUS(reg)); + if ((status & PLL_PLL_STATUS_PLL_LOCK) == 0) + { + return 0; + } + + /* Populate the integer and fractional PLL parameters */ + + div = getreg32(PLL_DIV(reg)); + parm.rdiv = (div & PLL_DIV_RDIV_MASK) >> PLL_DIV_RDIV_SHIFT; + parm.mfi = (div & PLL_DIV_MFI_MASK) >> PLL_DIV_MFI_SHIFT; + + /* RDIV values 0 and 1 both mean a divisor of 1 */ + + if (parm.rdiv == 0) + { + parm.rdiv = 1; + } + + if (frac) + { + /* Fill the fractional parameters */ + + parm.mfn = getreg32(PLL_NUMERATOR(reg)) & PLL_NUMERATOR_MFN_MASK; + parm.mfn >>= PLL_NUMERATOR_MFN_SHIFT; + parm.mfd = getreg32(PLL_DENOMINATOR(reg)) & PLL_DENOMINATOR_MFD_MASK; + parm.mfd >>= PLL_DENOMINATOR_MFD_SHIFT; + } + + return calculate_vco_freq(&parm, frac); +} + +static uint32_t pll_freq_out(uintptr_t reg, bool frac) +{ + uint32_t ctrl; + uint32_t div; + uint32_t vco; + + /* Read the MUX control register and check if bypass mode is enabled */ + + ctrl = getreg32(PLL_CTRL(reg)); + if (ctrl & PLL_CTRL_CLKMUX_BYPASS) + { + return XTAL_FREQ; + } + + /* If the mux is disabled output frequency is 0 */ + + if ((ctrl & PLL_CTRL_CLKMUX_EN) == 0) + { + return 0; + } + + /* Get input VCO frequency */ + + vco = vco_freq_out(reg, frac); + if (vco == 0) + { + /* The VCO is off or unstable */ + + return 0; + } + + /* Calculate the output clock divider */ + + div = (getreg32(PLL_DIV(reg)) & PLL_DIV_ODIV_MASK) >> PLL_DIV_ODIV_SHIFT; + + /* According to spec, div0 = 2 and div1 = 3 */ + + if (div == 0) + { + div = 2; + } + else if (div == 1) + { + div = 3; + } + + return vco / div; +} + +static uint32_t pll_pfd_freq_out(uintptr_t reg, int pfd, int div2) +{ + struct pfd_parms_s parm; + uint32_t ctrl; + uint32_t div; + uint32_t vco; + + /* Read the correct PFD register set */ + + switch (pfd) + { + case 0: + ctrl = getreg32(PLL_DFS_CTRL_0(reg)); + div = getreg32(PLL_DFS_DIV_0(reg)); + break; + + case 1: + ctrl = getreg32(PLL_DFS_CTRL_1(reg)); + div = getreg32(PLL_DFS_DIV_1(reg)); + break; + + case 2: + ctrl = getreg32(PLL_DFS_CTRL_2(reg)); + div = getreg32(PLL_DFS_DIV_2(reg)); + break; + + default: + return 0; + } + + /* Get input VCO frequency */ + + vco = vco_freq_out(reg, true); + if (vco == 0) + { + /* The VCO is off or unstable */ + + return 0; + } + + /* If the DFS part is bypassed, the output is the VCO directly */ + + if (ctrl & PLL_DFS_BYPASS_EN) + { + return vco; + } + + /* Check if the DFS part is disabled */ + + if ((ctrl & PLL_DFS_ENABLE) == 0) + { + return 0; + } + + /* Populate the DFS parameters */ + + parm.mfi = (div & PLL_DFS_MFI_MASK) >> PLL_DFS_MFI_SHIFT; + parm.mfn = (div & PLL_DFS_MFN_MASK) >> PLL_DFS_MFN_SHIFT; + + return ((uint64_t)vco * 5) / (parm.mfi * 5 + parm.mfn) / div2; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_clockconfig + * + * Description: + * Called to initialize the i.IMX9. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. + * + ****************************************************************************/ + +void imx9_clockconfig(void) +{ +#ifdef CONFIG_IMX9_BOOTLOADER + struct imx9_pll_cfg_s pll_cfgs[] = PLL_CFGS; + struct imx9_pfd_cfg_s pfd_cfgs[] = PFD_CFGS; + struct imx9_pll_cfg_s pll_arm = ARMPLL_CFG; + int i; + + /* Set the CPU clock */ + + putreg32(CCM_GPR_A55_CLK_SEL_PLL, IMX9_CCM_GPR_SH_CLR(CCM_SHARED_A55_CLK)); + pll_init(pll_arm.reg, pll_arm.frac, &pll_arm.parms); + putreg32(CCM_GPR_A55_CLK_SEL_PLL, IMX9_CCM_GPR_SH_SET(CCM_SHARED_A55_CLK)); + + /* Run the PLL configuration */ + + for (i = 0; i < nitems(pll_cfgs); i++) + { + struct imx9_pll_cfg_s *cfg = &pll_cfgs[i]; + pll_init(cfg->reg, cfg->frac, &cfg->parms); + } + + /* Run the PFD configuration */ + + for (i = 0; i < nitems(pfd_cfgs); i++) + { + struct imx9_pfd_cfg_s *cfg = &pfd_cfgs[i]; + pll_pfd_init(cfg->reg, cfg->pfd, &cfg->parms); + } +#endif +} + +/**************************************************************************** + * Name: imx9_get_clock + * + * Description: + * This function returns the clock frequency of the specified functional + * clock. + * + * Input Parameters: + * clkname - Identifies the clock of interest + * frequency - The location where the peripheral clock frequency will be + * returned + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. -ENODEV is returned if the clock is not enabled or is not + * being clocked. + * + ****************************************************************************/ + +int imx9_get_clock(int clkname, uint32_t *frequency) +{ + switch (clkname) + { + case OSC_24M: + *frequency = XTAL_FREQ; + break; + + case ARM_PLL: + *frequency = pll_freq_out(IMX9_ARMPLL_BASE, false); + break; + + case SYS_PLL1_IN: + *frequency = pll_freq_out(IMX9_SYSPLL_BASE, false); + break; + + case SYS_PLL1PFD0: + *frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 0, 1); + break; + + case SYS_PLL1PFD0DIV2: + *frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 0, 2); + break; + + case SYS_PLL1PFD1: + *frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 1, 1); + break; + + case SYS_PLL1PFD1DIV2: + *frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 1, 2); + break; + + case SYS_PLL1PFD2: + *frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 2, 1); + break; + + case SYS_PLL1PFD2DIV2: + *frequency = pll_pfd_freq_out(IMX9_SYSPLL_BASE, 2, 2); + break; + + case AUDIO_PLL1OUT: + *frequency = pll_freq_out(IMX9_AUDIOPLL_BASE, true); + break; + + case DRAM_PLLOUT: + *frequency = pll_freq_out(IMX9_DRAMPLL_BASE, true); + break; + + case VIDEO_PLL1OUT: + *frequency = pll_freq_out(IMX9_VIDEOPLL_BASE, true); + break; + + default: + return -ENODEV; + } + + return OK; +} + +/**************************************************************************** + * Name: imx9_get_rootclock + * + * Description: + * This function returns the clock frequency of the specified root + * functional clock. + * + * Input Parameters: + * clkroot - Identifies the peripheral clock of interest + * frequency - The location where the peripheral clock frequency will be + * returned + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. -ENODEV is returned if the clock is not enabled or is not + * being clocked. + * + ****************************************************************************/ + +int imx9_get_rootclock(int clkroot, uint32_t *frequency) +{ + uint32_t reg; + uint32_t div; + uint32_t mux; + int clk_name; + + if (clkroot <= CCM_CR_COUNT) + { + reg = getreg32(IMX9_CCM_CR_CTRL(clkroot)); + + if ((reg & CCM_CR_CTRL_OFF) == CCM_CR_CTRL_OFF) + { + *frequency = 0; + } + else + { + mux = (reg & CCM_CR_CTRL_MUX_MASK) >> CCM_CR_CTRL_MUX_SHIFT; + clk_name = g_ccm_root_mux[clkroot][mux]; + imx9_get_clock(clk_name, frequency); + div = ((reg & CCM_CR_CTRL_DIV_MASK) >> CCM_CR_CTRL_DIV_SHIFT) + 1; + *frequency = *frequency / div; + } + + return OK; + } + + return -ENODEV; +} diff --git a/arch/arm64/src/imx9/imx9_clockconfig.h b/arch/arm64/src/imx9/imx9_clockconfig.h new file mode 100644 index 0000000000000..cf8ffc1f45441 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_clockconfig.h @@ -0,0 +1,169 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_clockconfig.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_CLOCKCONFIG_H +#define __ARCH_ARM64_SRC_IMX9_IMX9_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PLL_PARMS(_rdiv, _odiv, _mfi, _mfn, _mfd) \ + { \ + .rdiv = (_rdiv), \ + .odiv = (_odiv), \ + .mfi = (_mfi), \ + .mfn = (_mfn), \ + .mfd = (_mfd), \ + } + +#define PLL_CFG(_reg, _frac, _parms) \ + { \ + .reg = (_reg), \ + .frac = (_frac), \ + .parms = _parms, \ + } + +#define PFD_PARMS(_mfi, _mfn, _div2) \ + { \ + .mfi = (_mfi), \ + .mfn = (_mfn), \ + .divby2_en = (_div2) \ + } + +#define PFD_CFG(_reg, _pfd, _parms) \ + { \ + .reg = (_reg), \ + .pfd = (_pfd), \ + .parms = _parms, \ + } + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct pll_parms_s +{ + /* Integer part (DIV) */ + + struct + { + uint32_t rdiv; /* Input clock divider */ + uint32_t odiv; /* PLL output divider */ + uint32_t mfi; /* PLL integer divider */ + }; + + /* Fractional part (NUMERATOR / DENOMINATOR) */ + + struct + { + uint32_t mfn; /* PLL fractional divider numerator */ + uint32_t mfd; /* PLL fractional divider denominator */ + }; +}; + +struct pfd_parms_s +{ + uint32_t mfi; /* PLL integer divider */ + uint32_t mfn; /* PLL fractional divider numerator */ + bool divby2_en; /* Enable the divide-by-2 output */ +}; + +struct imx9_pll_cfg_s +{ + uintptr_t reg; /* The PLL register base */ + bool frac; /* Fractional PLL ? */ + struct pll_parms_s parms; /* The PLL parameters */ +}; + +struct imx9_pfd_cfg_s +{ + uintptr_t reg; /* The PLL register base */ + int pfd; /* The PFD number */ + struct pfd_parms_s parms; /* The PFD parameters */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_clockconfig + * + * Description: + * Called to initialize the i.IMX9. This does whatever setup is needed to + * put the SoC in a usable state. This includes the initialization of + * clocking using the settings in board.h. + * + ****************************************************************************/ + +void imx9_clockconfig(void); + +/**************************************************************************** + * Name: imx9_get_clock + * + * Description: + * This function returns the clock frequency of the specified functional + * clock. + * + * Input Parameters: + * clkname - Identifies the clock of interest + * frequency - The location where the peripheral clock frequency will be + * returned + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. -ENODEV is returned if the clock is not enabled or is not + * being clocked. + * + ****************************************************************************/ + +int imx9_get_clock(int clkname, uint32_t *frequency); + +/**************************************************************************** + * Name: imx9_get_rootclock + * + * Description: + * This function returns the clock frequency of the specified root + * functional clock. + * + * Input Parameters: + * clkroot - Identifies the peripheral clock of interest + * frequency - The location where the peripheral clock frequency will be + * returned + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. -ENODEV is returned if the clock is not enabled or is not + * being clocked. + * + ****************************************************************************/ + +int imx9_get_rootclock(int clkroot, uint32_t *frequency); + +#endif /* __ARCH_ARM64_SRC_IMX9_IMX9_CLOCKCONFIG_H */ diff --git a/arch/arm64/src/imx9/imx9_dma_alloc.c b/arch/arm64/src/imx9/imx9_dma_alloc.c new file mode 100644 index 0000000000000..1708e1ae69e3e --- /dev/null +++ b/arch/arm64/src/imx9/imx9_dma_alloc.c @@ -0,0 +1,153 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_dma_alloc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#if defined(CONFIG_IMX9_DMA_ALLOC) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* DMA buffers must be aligned with the D-Cache line boundaries to facilitate + * cache operations on the DMA buffers when the D-Cache is enabled. + */ + +#define DMA_ALIGN ARMV8A_DCACHE_LINESIZE +#define DMA_ALIGN_MASK (DMA_ALIGN - 1) +#define DMA_ALIGN_UP(n) (((n) + DMA_ALIGN_MASK) & ~DMA_ALIGN_MASK) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static GRAN_HANDLE dma_allocator; + +/* The DMA heap size constrains the total number of things that can be + * ready to do DMA at a time. + * + * For example, FAT DMA depends on one sector-sized buffer per filesystem + * plus one sector-sized buffer per file. + * + * We use a fundamental alignment / granule size of 64B; it fulfills the + * requirement for any DMA engine. + */ + +static uint8_t g_dma_heap[CONFIG_IMX9_DMA_ALLOC_POOL_SIZE] +aligned_data(DMA_ALIGN) locate_data(CONFIG_IMX9_DMA_ALLOC_SECT); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_dma_alloc_init + * + * Description: + * Initialize the DMA memory allocator. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int imx9_dma_alloc_init(void) +{ + /* Allocate 64B granules with 64B alignment */ + + dma_allocator = gran_initialize(g_dma_heap, sizeof(g_dma_heap), 6, 6); + + if (dma_allocator == NULL) + { + return -ENOMEM; + } + + return OK; +} + +/**************************************************************************** + * Name: imx9_dma_alloc + * + * Description: + * Allocate a contiguous block of physical memory for DMA. + * + * Input Parameters: + * size - Size of the requested block in bytes. + * + * Returned Value: + * Physical address of the first page on success; NULL on failure. + * + ****************************************************************************/ + +void *imx9_dma_alloc(size_t size) +{ + return gran_alloc(dma_allocator, size); +} + +/**************************************************************************** + * Name: imx9_dma_free + * + * Description: + * Free a previously allocated DMA memory block. + * + * Input Parameters: + * memory - Physical address of the first page of DMA memory. + * size - Size of the allocated block in bytes. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void imx9_dma_free(void *memory, size_t size) +{ + gran_free(dma_allocator, memory, size); +} + +#ifdef CONFIG_FAT_DMAMEMORY +FAR void *fat_dma_alloc(size_t size) +{ + return imx9_dma_alloc(size); +} + +void fat_dma_free(FAR void *memory, size_t size) +{ + imx9_dma_free(memory, size); +} +#endif + +#endif /* CONFIG_IMX9_DMA_ALLOC */ diff --git a/arch/arm64/src/imx9/imx9_dma_alloc.h b/arch/arm64/src/imx9/imx9_dma_alloc.h new file mode 100644 index 0000000000000..d0c78ec451eb0 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_dma_alloc.h @@ -0,0 +1,83 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_dma_alloc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_DMA_ALLOC_H +#define __ARCH_ARM64_SRC_IMX9_IMX9_DMA_ALLOC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_dma_alloc_init + * + * Description: + * Initialize the DMA memory allocator. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int imx9_dma_alloc_init(void); + +/**************************************************************************** + * Name: imx9_dma_alloc + * + * Description: + * Allocate a contiguous block of physical memory for DMA. + * + * Input Parameters: + * size - Size of the requested block in bytes. + * + * Returned Value: + * Physical address of the first page on success; NULL on failure. + * + ****************************************************************************/ + +void *imx9_dma_alloc(size_t size); + +/**************************************************************************** + * Name: imx9_dma_free + * + * Description: + * Free a previously allocated DMA memory block. + * + * Input Parameters: + * memory - Physical address of the first page of DMA memory. + * size - Size of the allocated block in bytes. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void imx9_dma_free(void *memory, size_t size); + +#endif /* __ARCH_ARM64_SRC_IMX9_IMX9_DMA_ALLOC_H */ diff --git a/arch/arm64/src/imx9/imx9_edma.c b/arch/arm64/src/imx9/imx9_edma.c new file mode 100644 index 0000000000000..67a2cd3ef362f --- /dev/null +++ b/arch/arm64/src/imx9/imx9_edma.c @@ -0,0 +1,1509 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_edma.c + * + * Copyright (C) 2019, 2021, 2023 Gregory Nutt. All rights reserved. + * Copyright 2022 NXP + * Authors: Gregory Nutt + * David Sidrane + * Peter van der Perk + * + * This file was leveraged from the NuttX S32K3 port. Portions of that eDMA + * logic derived from NXP sample code which has a compatible BSD 3-clause + * license: + * + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "arm64_internal.h" +#include "sched/sched.h" + +#include "chip.h" +#include "imx9_edma.h" +#include "imx9_ccm.h" + +#include "hardware/imx9_ccm.h" +#include "hardware/imx9_edma.h" +#include "hardware/imx9_dmamux.h" + +#ifdef CONFIG_IMX9_EDMA + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* TCD Alignment. + * + * eDMA TCDs must be aligned with the D-Cache line boundaries to facilitate + * cache operations on the TCDs when the D-Cache is enabled. + * + * NOTE: The TCDs are 32-bytes in length. We implicitly assume that the + * D-Cache line size is also 32-bits. Otherwise, padding would be required + * at the ends of the TCDS and buffers to protect data after the end of from + * invalidation. + */ + +#define EDMA_ALIGN ARMV8A_DCACHE_LINESIZE +#define EDMA_ALIGN_MASK (EDMA_ALIGN - 1) +#define EDMA_ALIGN_UP(n) (((n) + EDMA_ALIGN_MASK) & ~EDMA_ALIGN_MASK) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* State of a DMA channel */ + +enum imx9_dmastate_e +{ + IMX9_DMA_IDLE = 0, /* No DMA in progress */ + IMX9_DMA_CONFIGURED, /* DMA configured, but not yet started */ + IMX9_DMA_ACTIVE /* DMA has been started and is in progress */ +}; + +/* This structure describes one DMA channel */ + +struct imx9_dmach_s +{ + uintptr_t base; /* DMA engine base address */ + uint32_t flags; /* DMA channel flags */ + bool inuse; /* true: The DMA channel is in use */ + uint8_t dmamux; /* DMAMUX channel number */ + uint8_t chan; /* DMA channel number (either eDMA3 or eDMA4) */ + uint8_t state; /* Channel state. See enum imx9_dmastate_e */ + edma_callback_t callback; /* Callback invoked when the DMA completes */ + void *arg; /* Argument passed to callback function */ +#if CONFIG_IMX9_EDMA_NTCD > 0 + /* That TCD list is linked through the DLAST SGA field. The first transfer + * to be performed is at the head of the list. Subsequent TCDs are added + * at the tail of the list. + */ + + struct imx9_edmatcd_s *head; /* First TCD in the list */ + struct imx9_edmatcd_s *tail; /* Last TCD in the list */ +#endif +}; + +/* This structure describes the state of the eDMA controller */ + +struct imx9_edma_s +{ + /* These mutex protect the DMA channel and descriptor tables */ + + mutex_t chlock; /* Protects channel table */ +#if CONFIG_IMX9_EDMA_NTCD > 0 + sem_t dsem; /* Supports wait for free descriptors */ +#endif + + /* This array describes each DMA channel */ + + struct imx9_dmach_s dmach[IMX9_EDMA_NCHANNELS]; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* The state of the eDMA */ + +static struct imx9_edma_s g_edma = +{ + .chlock = NXMUTEX_INITIALIZER, +#if CONFIG_IMX9_EDMA_NTCD > 0 + .dsem = SEM_INITIALIZER(CONFIG_IMX9_EDMA_NTCD), +#endif +}; + +#if CONFIG_IMX9_EDMA_NTCD > 0 +/* This is a singly-linked list of free TCDs */ + +static sq_queue_t g_tcd_free; + +/* This is a pool of pre-allocated TCDs */ + +static struct imx9_edmatcd_s g_tcd_pool[CONFIG_IMX9_EDMA_NTCD] + aligned_data(EDMA_ALIGN); +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_tcd_alloc + * + * Description: + * Allocate an in-memory, TCD + * + ****************************************************************************/ + +#if CONFIG_IMX9_EDMA_NTCD > 0 +static struct imx9_edmatcd_s *imx9_tcd_alloc(void) +{ + struct imx9_edmatcd_s *tcd; + irqstate_t flags; + + /* Take the 'dsem'. When we hold the the 'dsem', then we know that one + * TCD is reserved for us in the free list. + * + * NOTE: We use a critical section here because we may block waiting for + * the 'dsem'. The critical section will be suspended while we are + * waiting. + */ + + flags = enter_critical_section(); + nxsem_wait_uninterruptible(&g_edma.dsem); + + /* Now there should be a TCD in the free list reserved just for us */ + + tcd = (struct imx9_edmatcd_s *)sq_remfirst(&g_tcd_free); + DEBUGASSERT(tcd != NULL); + + leave_critical_section(flags); + return tcd; +} +#endif + +/**************************************************************************** + * Name: imx9_tcd_free + * + * Description: + * Free an in-memory, TCD + * + ****************************************************************************/ + +#if CONFIG_IMX9_EDMA_NTCD > 0 +static void imx9_tcd_free(struct imx9_edmatcd_s *tcd) +{ + irqstate_t flags; + + /* Add the the TCD to the end of the free list and post the 'dsem', + * possibly waking up another thread that might be waiting for + * a TCD. + */ + + flags = spin_lock_irqsave(NULL); + sq_addlast((sq_entry_t *)tcd, &g_tcd_free); + nxsem_post(&g_edma.dsem); + spin_unlock_irqrestore(NULL, flags); +} +#endif + +/**************************************************************************** + * Name: imx9_tcd_initialize() + * + * Description: + * Initialize the TCD free list from the pool of pre-allocated TCDs. + * + * Assumptions: + * Called early in the initialization sequence so no special protection is + * necessary. + * + ****************************************************************************/ + +#if CONFIG_IMX9_EDMA_NTCD > 0 +static inline void imx9_tcd_initialize(void) +{ + sq_entry_t *tcd; + int i; + + /* Add each pre-allocated TCD to the tail of the TCD free list */ + + sq_init(&g_tcd_free); + for (i = 0; i < CONFIG_IMX9_EDMA_NTCD; i++) + { + tcd = (sq_entry_t *)&g_tcd_pool[i]; + sq_addlast(tcd, &g_tcd_free); + } +} +#endif + +/**************************************************************************** + * Name: imx9_tcd_chanlink + * + * Description: + * This function configures either a minor link or a major link. The minor + * link means the channel link is triggered every time CITER decreases by 1 + * The major link means that the channel link is triggered when the CITER + * is exhausted. + * + * NOTE: Users should ensure that DONE flag is cleared before calling this + * interface, or the configuration is invalid. + * + * Input Parameters: + * tcd - Point to the TCD structure. + * type - Channel link type. + * chan - The linked channel number. + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_EDMA_ELINK +static inline void imx9_tcd_chanlink(uint8_t flags, + struct imx9_dmach_s *linkch, + struct imx9_edmatcd_s *tcd) +{ + uint16_t regval16; + + flags &= EDMA_CONFIG_LINKTYPE_MASK; + + if (linkch == NULL || flags == EDMA_CONFIG_LINKTYPE_LINKNONE) + { + /* No link or no link channel provided */ + + /* Disable minor links */ + + /* Disable major link */ + + tcd->csr &= ~EDMA_TCD_CSR_MAJORELINK; + } + else if (flags == EDMA_CONFIG_LINKTYPE_MINORLINK) /* Minor link config */ + { + /* Enable minor link */ + + tcd->citer |= EDMA_TCD_CITER_ELINK; + tcd->biter |= EDMA_TCD_BITER_ELINK; + + /* Set linked channel */ + + regval16 = tcd->citer; + regval16 &= ~EDMA_TCD_CITER_LINKCH_MASK; + regval16 |= EDMA_TCD_CITER_LINKCH(linkch->chan); + tcd->citer = regval16; + + regval16 = tcd->biter; + regval16 &= ~EDMA_TCD_BITER_LINKCH_MASK; + regval16 |= EDMA_TCD_BITER_LINKCH(linkch->chan); + tcd->biter = regval16; + } + else /* if (flags == EDMA_CONFIG_LINKTYPE_MAJORLINK) Major link config */ + { + /* Enable major link */ + + regval16 = tcd->csr; + regval16 |= EDMA_TCD_CSR_MAJORELINK; + tcd->csr = regval16; + + /* Set major linked channel */ + + regval16 &= ~EDMA_TCD_CSR_MAJORLINKCH_MASK; + regval16 |= EDMA_TCD_CSR_MAJORLINKCH(linkch->chan); + tcd->csr = regval16; + } +} +#endif + +/**************************************************************************** + * Name: imx9_tcd_configure + * + * Description: + * Configure all TCD registers to the specified values. 'tcd' is an + * 'overlay' that may refer either to either the TCD register set or to an + * in-memory TCD structure. + * + ****************************************************************************/ + +static inline void imx9_tcd_configure(struct imx9_edmatcd_s *tcd, + const struct imx9_edma_xfrconfig_s *config) +{ + tcd->saddr = config->saddr; + tcd->soff = config->soff; + tcd->attr = EDMA_TCD_ATTR_SSIZE(config->ssize) | /* Transfer Attributes */ + EDMA_TCD_ATTR_DSIZE(config->dsize); +#ifdef CONFIG_IMX9_EDMA_MOD + tcd->attr |= EDMA_TCD_ATTR_SMOD(config->smod) | /* Transfer Attributes */ + EDMA_TCD_ATTR_DMOD(config->dmod); +#endif + tcd->nbytes = config->nbytes; + tcd->slast = config->flags & EDMA_CONFIG_LOOPSRC ? + -(config->iter * config->nbytes) : 0; + + tcd->daddr = config->daddr; + tcd->doff = config->doff; + tcd->citer = config->iter & EDMA_TCD_CITER_MASK; + tcd->biter = config->iter & EDMA_TCD_BITER_MASK; + tcd->csr = config->flags & EDMA_CONFIG_LOOP_MASK ? + 0 : EDMA_TCD_CSR_DREQ; + tcd->csr |= config->flags & EDMA_CONFIG_INTHALF ? + EDMA_TCD_CSR_INTHALF : 0; + tcd->dlastsga = config->flags & EDMA_CONFIG_LOOPDEST ? + -(config->iter * config->nbytes) : 0; + + /* And special case flags */ + +#ifdef CONFIG_IMX9_EDMA_ELINK + /* Configure major/minor link mapping */ + + imx9_tcd_chanlink(config->flags, (struct imx9_dmach_s *)config->linkch, + tcd); +#endif +} + +/**************************************************************************** + * Name: imx9_tcd_instantiate + * + * Description: + * Copy an in-memory TCD into eDMA channel TCD registers + * + ****************************************************************************/ + +#if CONFIG_IMX9_EDMA_NTCD > 0 +static void imx9_tcd_instantiate(struct imx9_dmach_s *dmach, + const struct imx9_edmatcd_s *tcd) +{ + uintptr_t base = IMX9_EDMA_TCD(dmach->base, dmach->chan); + + /* Push tcd into hardware TCD register */ + + /* Clear DONE bit first, otherwise ESG cannot be set */ + + putreg16(0, base + IMX9_EDMA_TCD_CSR_OFFSET); + + putreg32(tcd->saddr, base + IMX9_EDMA_TCD_SADDR_OFFSET); + putreg16(tcd->soff, base + IMX9_EDMA_TCD_SOFF_OFFSET); + putreg16(tcd->attr, base + IMX9_EDMA_TCD_ATTR_OFFSET); + putreg32(tcd->nbytes, base + IMX9_EDMA_TCD_NBYTES_OFFSET); + putreg32(tcd->slast, base + IMX9_EDMA_TCD_SLAST_SDA_OFFSET); + putreg32(tcd->daddr, base + IMX9_EDMA_TCD_DADDR_OFFSET); + putreg16(tcd->doff, base + IMX9_EDMA_TCD_DOFF_OFFSET); + putreg16(tcd->citer, base + IMX9_EDMA_TCD_CITER_OFFSET); + putreg32(tcd->dlastsga, base + IMX9_EDMA_TCD_DLAST_SGA_OFFSET); + + putreg16(tcd->csr, base + IMX9_EDMA_TCD_CSR_OFFSET); + + putreg16(tcd->biter, base + IMX9_EDMA_TCD_BITER_OFFSET); +} +#endif + +/**************************************************************************** + * Name: imx9_dmaterminate + * + * Description: + * Terminate the DMA transfer and disable the DMA channel + * + ****************************************************************************/ + +static void imx9_dmaterminate(struct imx9_dmach_s *dmach, int result) +{ + uintptr_t base = IMX9_EDMA_TCD(dmach->base, dmach->chan); +#if CONFIG_IMX9_EDMA_NTCD > 0 + struct imx9_edmatcd_s *tcd; + struct imx9_edmatcd_s *next; +#endif + edma_callback_t callback; + void *arg; + + /* Disable channel IRQ requests */ + + putreg32(EDMA_CH_INT, base + IMX9_EDMA_CH_INT_OFFSET); + + /* Clear CSR to disable channel. Because if the given channel started, + * transfer CSR will be not zero. Because if it is the last transfer, DREQ + * will be set. If not, ESG will be set. + */ + + putreg32(0, base + IMX9_EDMA_CH_CSR_OFFSET); + + putreg16(0, base + IMX9_EDMA_TCD_CSR_OFFSET); + + /* Cancel next TCD transfer. */ + + putreg32(0, base + IMX9_EDMA_TCD_DLAST_SGA_OFFSET); + +#if CONFIG_IMX9_EDMA_NTCD > 0 + /* Return all allocated TCDs to the free list */ + + for (tcd = dmach->head; tcd != NULL; tcd = next) + { + /* If channel looped to itself we are done + * if not continue to free tcds in chain + */ + + next = dmach->flags & EDMA_CONFIG_LOOPDEST ? + NULL : (struct imx9_edmatcd_s *)((uintptr_t)tcd->dlastsga); + + imx9_tcd_free(tcd); + } + + dmach->head = NULL; + dmach->tail = NULL; +#endif + + /* Perform the DMA complete callback */ + + callback = dmach->callback; + arg = dmach->arg; + + dmach->callback = NULL; + dmach->arg = NULL; + dmach->state = IMX9_DMA_IDLE; + + if (callback) + { + callback((DMACH_HANDLE)dmach, arg, true, result); + } +} + +/**************************************************************************** + * Name: imx9_edma_intstatus + * + * Description: + * DMA interrupt status per eDMA engine and channel. + * + ****************************************************************************/ + +static inline uint32_t imx9_edma_intstatus(uintptr_t base, uint8_t chan) +{ + /* The status register varies depending on eDMA instance and channel */ + +#ifdef IMX9_DMA3_BASE + /* eDMA3 uses the normal INT register */ + + if (base == IMX9_DMA3_BASE) + { + return getreg32(IMX9_EDMA_INT); + } +#endif + +#ifdef IMX9_DMA4_BASE + /* eDMA4 has two INT status registers, holding 32 statuses each */ + + if (chan > 31) + { + return getreg32(IMX9_EDMA_INT_HIGH); + } + + return getreg32(IMX9_EDMA_INT_LOW); +#endif +} + +/**************************************************************************** + * Name: imx9_edma_isr + * + * Description: + * DMA interrupt service routine. The vector handler calls this with the + * appropriate parameters. + * + ****************************************************************************/ + +static int imx9_edma_isr(int irq, void *context, void *arg) +{ + struct imx9_dmach_s *dmach; + uintptr_t base; + uint32_t regval32; + uint32_t errval32; + uint8_t chan; + int result; + + /* 'arg' should the DMA channel instance. */ + + dmach = (struct imx9_dmach_s *)arg; + DEBUGASSERT(dmach != NULL); + + chan = dmach->chan; + base = IMX9_EDMA_TCD(dmach->base, dmach->chan); + + /* Get the eDMA Error Status register value. */ + + errval32 = getreg32(base + IMX9_EDMA_CH_ES_OFFSET); + + if (errval32 & EDMA_CH_ES_ERR) + { + DEBUGASSERT(dmach->state == IMX9_DMA_ACTIVE); + + /* Clear the error */ + + putreg32(EDMA_CH_ES_ERR, base + IMX9_EDMA_CH_ES_OFFSET); + + /* Clear the pending eDMA channel interrupt */ + + putreg32(EDMA_CH_INT, base + IMX9_EDMA_CH_INT_OFFSET); + + imx9_dmaterminate(dmach, -EIO); + return OK; + } + + /* Check for an eDMA pending interrupt on this channel */ + + regval32 = imx9_edma_intstatus(dmach->base, dmach->chan); + if ((regval32 & EDMA_INT(chan % 31)) != 0) + { + /* An interrupt is pending. + * This should only happen if the channel is active. + */ + + DEBUGASSERT(dmach->state == IMX9_DMA_ACTIVE); + + /* Clear the pending eDMA channel interrupt */ + + putreg32(EDMA_CH_INT, base + IMX9_EDMA_CH_INT_OFFSET); + + /* Get the eDMA TCD Control and Status register value. */ + + regval32 = getreg32(base + IMX9_EDMA_CH_CSR_OFFSET); + + /* Check if transfer has finished. */ + + if ((regval32 & EDMA_CH_CSR_DONE) != 0) + { + /* Clear the pending DONE interrupt status. */ + + regval32 |= EDMA_CH_CSR_DONE; + putreg32(regval32, base + IMX9_EDMA_CH_CSR_OFFSET); + result = OK; + } + else + { + /* Perform the half or end-of-major-cycle DMA callback */ + + if (dmach->callback != NULL) + { + dmach->callback((DMACH_HANDLE)dmach, dmach->arg, false, OK); + } + + return OK; + } + + /* Terminate the transfer when it is done. */ + + if ((dmach->flags & EDMA_CONFIG_LOOP_MASK) == 0) + { + imx9_dmaterminate(dmach, result); + } + else if (dmach->callback != NULL) + { + dmach->callback((DMACH_HANDLE)dmach, dmach->arg, true, result); + } + } + + return OK; +} + +/**************************************************************************** + * Name: imx9_edma_interrupt + * + * Description: + * DMA interrupt handler. This function clears the channel major + * interrupt flag and calls the callback function if it is not NULL. + * + * NOTE: For the case using TCD queue, when the major iteration count is + * exhausted, additional operations are performed. These include the + * final address adjustments and reloading of the BITER field into the + * CITER. Assertion of an optional interrupt request also occurs at this + * time, as does a possible fetch of a new TCD from memory using the + * scatter/gather address pointer included in the descriptor (if scatter/ + * gather is enabled). + * + ****************************************************************************/ + +static int imx9_edma_interrupt(int irq, void *context, void *arg) +{ + struct imx9_dmach_s *dmach = (struct imx9_dmach_s *)arg; + +#ifdef IMX9_DMA3_BASE + if ((irq >= IMX9_IRQ_DMA3_0) && (irq <= IMX9_IRQ_DMA3_30)) + { + /* eDMA3 interrupt has a single source */ + + imx9_edma_isr(irq, context, dmach); + } +#endif + +#ifdef IMX9_DMA4_BASE + if ((irq >= IMX9_IRQ_DMA4_0_1) && (irq <= IMX9_IRQ_DMA4_62_63)) + { + /* eDMA4 interrupt has two sources */ + + imx9_edma_isr(irq, context, dmach); + imx9_edma_isr(irq, context, dmach + 1); + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: imx9_edma_configure + * + * Description: + * Configure eDMA instance. + * + ****************************************************************************/ + +static void imx9_edma_configure(uintptr_t base) +{ + uint32_t regval; + + /* Configure the eDMA controllers */ + + regval = getreg32(IMX9_EDMA_CSR(base)); + regval &= ~(EDMA_CSR_EDBG | EDMA_CSR_ERCA | EDMA_CSR_HAE | EDMA_CSR_GCLC | + EDMA_CSR_GMRC); + +#ifdef CONFIG_IMX9_EDMA_EDBG + regval |= EDMA_CSR_EDBG; /* Enable Debug */ +#endif +#ifdef CONFIG_IMX9_EDMA_ERCA + regval |= EDMA_CSR_ERCA; /* Enable Round Robin Channel Arbitration */ +#endif +#ifdef CONFIG_IMX9_EDMA_ERGA + regval |= EDMA_CSR_ERGA; /* Enable Round Robin Group Arbitration */ +#endif +#ifdef CONFIG_IMX9_EDMA_HOE + regval |= EDMA_CSR_HAE; /* Halt On Error */ +#endif +#ifdef CONFIG_IMX9_EDMA_CLM + regval |= EDMA_CSR_GCLC; /* Continuous Link Mode / Global Channel Linking Control */ +#endif +#ifdef CONFIG_IMX9_EDMA_EMLIM + regval |= EDMA_CSR_GMRC; /* Enable Minor Loop Mapping / Global Master ID Replication Control */ +#endif + + putreg32(regval, IMX9_EDMA_CSR(base)); +} + +/**************************************************************************** + * Name: imx9_find_free_ch + * + * Description: + * Configure eDMA instance. + * + ****************************************************************************/ + +static struct imx9_dmach_s * imx9_find_free_ch(uint16_t dmamux) +{ + struct imx9_dmach_s *candidate; + uintptr_t base; + unsigned int chndx; + + /* eDMA base for MUX */ + + base = imx9_dmamux_get_dmabase(dmamux); + +#ifdef IMX9_DMA3_BASE + /* For eDMA3 the channel must match the MUX number */ + + if (base == IMX9_DMA3_BASE) + { + chndx = dmamux & EDMA_MUX_MASK; + candidate = &g_edma.dmach[chndx]; + if (!candidate->inuse) + { + return candidate; + } + } +#endif + +#ifdef IMX9_DMA4_BASE + /* For eDMA4 any free channel is good */ + + if (base == IMX9_DMA4_BASE) + { + unsigned int offset; + unsigned int max; + + /* Iterate relevant channel range from the global LUT */ + + offset = imx9_edma_choffset(base); + max = imx9_edma_chmax(base); + + for (chndx = offset; chndx < max; chndx++) + { + candidate = &g_edma.dmach[chndx]; + if (!candidate->inuse) + { + return candidate; + } + } + } +#endif + + return NULL; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_dma_initialize + * + * Description: + * Initialize the DMA subsystem + * + * Returned Value: + * None + * + ****************************************************************************/ + +void weak_function arm64_dma_initialize(void) +{ + struct imx9_dmach_s *dmach; + uintptr_t base; + int chan; + int i; + + dmainfo("Initialize eDMA\n"); + + /* Enable root clock */ + + imx9_ccm_configure_root_clock(CCM_CR_WAKEUPAXI, SYS_PLL1PFD0, 4); + + /* Configure the instances */ + + dmach = &g_edma.dmach[0]; + +#ifdef IMX9_DMA3_BASE + /* Enable peripheral clock */ + + imx9_ccm_gate_on(CCM_LPCG_EDMA3, true); + + imx9_edma_configure(IMX9_DMA3_BASE); + + /* Initialize the channel */ + + for (i = 0; i < DMA3_CHANNEL_COUNT; i++, dmach++) + { + dmach->base = IMX9_DMA3_BASE; + dmach->chan = i; + + irq_attach(IMX9_IRQ_DMA3_0 + i, imx9_edma_interrupt, dmach); + } +#endif + +#ifdef IMX9_DMA4_BASE + /* Enable peripheral clock */ + + imx9_ccm_gate_on(CCM_LPCG_EDMA4, true); + + imx9_edma_configure(IMX9_DMA4_BASE); + + /* Initialize the channel */ + + for (i = 0; i < DMA4_CHANNEL_COUNT; i++, dmach++) + { + dmach->base = IMX9_DMA4_BASE; + dmach->chan = i; + + /* Attach interrupt for every second channel */ + + if ((i & 0x01) == 0) + { + irq_attach(IMX9_IRQ_DMA4_0_1 + (i >> 1), imx9_edma_interrupt, + dmach); + } + } +#endif + +#if CONFIG_IMX9_EDMA_NTCD > 0 + /* Initialize the list of free TCDs from the pool of pre-allocated TCDs. */ + + imx9_tcd_initialize(); +#endif + + /* Disable all DMA channel interrupts at the eDMA controller */ + + for (i = 0; i < IMX9_EDMA_NCHANNELS; i++) + { + /* DMA engine base and TCD channel */ + + base = g_edma.dmach[i].base; + chan = g_edma.dmach[i].chan; + + /* Disable all DMA channels and DMA channel interrupts */ + + putreg32(0, IMX9_EDMA_TCD(base, chan) + IMX9_EDMA_CH_CSR_OFFSET); + + /* Set all TCD CSR, biter and citer entries to 0 so that + * will be 0 when DONE is not set so that imx9_dmach_getcount + * reports 0. + */ + + putreg16(0, IMX9_EDMA_TCD(base, chan) + IMX9_EDMA_TCD_CSR_OFFSET); + putreg16(0, IMX9_EDMA_TCD(base, chan) + IMX9_EDMA_TCD_CITER_OFFSET); + putreg16(0, IMX9_EDMA_TCD(base, chan) + IMX9_EDMA_TCD_BITER_OFFSET); + } + +#ifdef IMX9_DMA3_BASE + /* Clear all pending DMA channel interrupts */ + + putreg32(0xffffffff, IMX9_EDMA_INT); + + /* Enable the channel interrupts at the NVIC (still disabled at the eDMA + * controller). + */ + + for (i = 0; i < DMA3_IRQ_COUNT; i++) + { + up_enable_irq(IMX9_IRQ_DMA3_0 + i); + } +#endif + +#ifdef IMX9_DMA4_BASE + /* Clear all pending DMA channel interrupts */ + + putreg32(0xffffffff, IMX9_EDMA_INT_LOW); + putreg32(0xffffffff, IMX9_EDMA_INT_HIGH); + + /* Enable the channel interrupts at the NVIC (still disabled at the eDMA + * controller). + */ + + for (i = 0; i < DMA4_IRQ_COUNT; i++) + { + up_enable_irq(IMX9_IRQ_DMA4_0_1 + i); + } +#endif +} + +/**************************************************************************** + * Name: imx9_dmach_alloc + * + * Allocate a DMA channel. This function sets aside a DMA channel, + * initializes the DMAMUX for the channel, then gives the caller exclusive + * access to the DMA channel. + * + * Input Parameters: + * + * dmamux - DMAMUX configuration see DMAMUX channel configuration register + * bit-field definitions in hardware/imx9_dmamux.h. + * Settings include: + * + * DMAMUX_CHCFG_SOURCE Chip-specific DMA source (required) + * DMAMUX_CHCFG_TRIG DMA Channel Trigger Enable (optional) + * DMAMUX_CHCFG_ENBL DMA Mux Channel Enable (required) + * + * A value of zero will disable the DMAMUX channel. + * dchpri - DCHPRI channel priority configuration. See DCHPRI channel + * configuration register bit-field definitions in + * hardware/imx9_edma.h. Meaningful settings include: + * + * EDMA_DCHPRI_CHPRI Channel Arbitration Priority + * DCHPRI_DPA Disable Preempt Ability + * DCHPRI_ECP Enable Channel Preemption + * + * The power-on default, 0x05, is a reasonable choice. + * + * Returned Value: + * If a DMA channel is available, this function returns a non-NULL, void* + * DMA channel handle. NULL is returned on any failure. + * + ****************************************************************************/ + +DMACH_HANDLE imx9_dmach_alloc(uint16_t dmamux, uint8_t dchpri) +{ + struct imx9_dmach_s *dmach; + uintptr_t base; + int ret; + + /* Search for an available DMA channel */ + + dmach = NULL; + ret = nxmutex_lock(&g_edma.chlock); + if (ret < 0) + { + return NULL; + } + + /* Find channel for this DMA MUX */ + + dmach = imx9_find_free_ch(dmamux); + if (dmach) + { + dmach->inuse = true; + dmach->state = IMX9_DMA_IDLE; + dmach->dmamux = dmamux & EDMA_MUX_MASK; + + /* TCD register base */ + + base = IMX9_EDMA_TCD(dmach->base, dmach->chan); + + /* Clear any pending interrupts on the channel */ + + putreg32(0, base + IMX9_EDMA_CH_CSR_OFFSET); + + /* Make sure that the channel is disabled. */ + + putreg32(EDMA_CH_INT, base + IMX9_EDMA_CH_INT_OFFSET); + + /* Set the DMAMUX source */ + + if (imx9_edma_tcdhasmux(dmach->base)) + { + dmainfo("CH%d: MUX:%u->%p\n", dmach->chan, dmach->dmamux, + (void *)(base + IMX9_EDMA_CH_MUX_OFFSET)); + putreg8(dmach->dmamux, base + IMX9_EDMA_CH_MUX_OFFSET); + } + } + + nxmutex_unlock(&g_edma.chlock); + + /* Show the result of the allocation */ + + if (dmach != NULL) + { + dmainfo("CH%d: returning dmach: %p\n", dmach->chan, dmach); + } + else + { + dmaerr("ERROR: Failed allocate eDMA channel\n"); + } + + return (DMACH_HANDLE)dmach; +} + +/**************************************************************************** + * Name: imx9_dmach_free + * + * Description: + * Release a DMA channel. NOTE: The 'handle' used in this argument must + * NEVER be used again until imx9_dmach_alloc() is called again to + * re-gain a valid handle. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx9_dmach_free(DMACH_HANDLE handle) +{ + struct imx9_dmach_s *dmach = (struct imx9_dmach_s *)handle; + uintptr_t base = IMX9_EDMA_TCD(dmach->base, dmach->chan); + + dmainfo("dmach: %p\n", dmach); + DEBUGASSERT(dmach != NULL && dmach->inuse && + dmach->state != IMX9_DMA_ACTIVE); + + /* Mark the channel no longer in use. Clearing the inuse flag is an atomic + * operation and so should be safe. + */ + + dmach->flags = 0; + dmach->inuse = false; /* No longer in use */ + dmach->state = IMX9_DMA_IDLE; /* Better not be active! */ + + /* Make sure that the channel is disabled. */ + + putreg32(EDMA_CH_INT, base + IMX9_EDMA_CH_INT_OFFSET); + + /* Disable the associated DMAMUX */ + + if (imx9_edma_tcdhasmux(dmach->base)) + { + putreg8(0, base + IMX9_EDMA_CH_MUX_OFFSET); + } +} + +/**************************************************************************** + * Name: imx9_dmach_xfrsetup + * + * Description: + * This function adds the eDMA transfer to the DMA sequence. The request + * is setup according to the content of the transfer configuration + * structure. For "normal" DMA, imx9_dmach_xfrsetup is called only once. + * Scatter/gather DMA is accomplished by calling this function repeatedly, + * once for each transfer in the sequence. Scatter/gather DMA processing + * is enabled automatically when the second transfer configuration is + * received. + * + * This function may be called multiple times to handle multiple, + * discontinuous transfers (scatter-gather) + * + * Input Parameters: + * handle - DMA channel handle created by imx9_dmach_alloc() + * config - A DMA transfer configuration instance, populated by the + * The content of 'config' describes the transfer + * + * Returned Value + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int imx9_dmach_xfrsetup(DMACH_HANDLE *handle, + const struct imx9_edma_xfrconfig_s *config) +{ + struct imx9_dmach_s *dmach = (struct imx9_dmach_s *)handle; + uintptr_t base = IMX9_EDMA_TCD(dmach->base, dmach->chan); +#if CONFIG_IMX9_EDMA_NTCD > 0 + struct imx9_edmatcd_s *tcd; + struct imx9_edmatcd_s *prev; + uint16_t mask = config->flags & EDMA_CONFIG_INTMAJOR ? 0 : + EDMA_TCD_CSR_INTMAJOR; + uint16_t regval16; +#else + uint32_t regval32; +#endif + + DEBUGASSERT(dmach != NULL); + dmainfo("dmach%u: %p config: %p\n", dmach->chan, dmach, config); + + dmach->flags = config->flags; + +#if CONFIG_IMX9_EDMA_NTCD > 0 + /* Scatter/gather DMA is supported */ + + /* Allocate a TCD, waiting if necessary */ + + tcd = imx9_tcd_alloc(); + + /* Configure current TCD block transfer. */ + + imx9_tcd_configure(tcd, config); + + /* Enable the interrupt when the major iteration count completes for this + * TCD. For "normal" DMAs, this will correspond to the DMA DONE + * interrupt; for scatter gather DMAs, multiple interrupts will be + * generated with the final being the DONE interrupt. + */ + + tcd->csr |= EDMA_TCD_CSR_INTMAJOR; + + /* Is this the first descriptor in the list? */ + + if (dmach->head == NULL) + { + /* Yes.. add it to the list */ + + dmach->head = tcd; + dmach->tail = tcd; + + /* And instantiate the first TCD in the DMA channel TCD registers. */ + + imx9_tcd_instantiate(dmach, tcd); + } + else + { + /* Cannot mix transfer types */ + + if (dmach->flags & EDMA_CONFIG_LOOP_MASK) + { + imx9_tcd_free(tcd); + return -EINVAL; + } + + /* Chain from previous descriptor in the list. */ + + /* Enable scatter/gather feature in the previous TCD. */ + + prev = dmach->tail; + regval16 = prev->csr; + regval16 &= ~(EDMA_TCD_CSR_DREQ | mask); + regval16 |= EDMA_TCD_CSR_ESG; + prev->csr = regval16; + + prev->dlastsga = (uint32_t)((uintptr_t)tcd); + dmach->tail = tcd; + + /* Clean cache associated with the previous TCD memory */ + + up_clean_dcache((uintptr_t)prev, + (uintptr_t)prev + sizeof(struct imx9_edmatcd_s)); + + /* Check if the TCD block in the DMA channel registers is the same as + * the previous previous TCD. This can happen if the previous TCD was + * the first TCD and has already be loaded into the TCD registers. + */ + + if (dmach->head == prev) + { + /* Enable scatter/gather also in the TCD registers. */ + + regval16 = getreg16(base + IMX9_EDMA_TCD_CSR_OFFSET); + regval16 &= ~(EDMA_TCD_CSR_DREQ | mask); + regval16 |= EDMA_TCD_CSR_ESG; + putreg16(regval16, base + IMX9_EDMA_TCD_CSR_OFFSET); + + putreg32((uint32_t)((uintptr_t)tcd), + base + IMX9_EDMA_TCD_DLAST_SGA_OFFSET); + } + } + + /* Clean cache associated with the TCD memory */ + + up_clean_dcache((uintptr_t)tcd, + (uintptr_t)tcd + sizeof(struct imx9_edmatcd_s)); +#else + + /* Scatter/gather DMA is NOT supported */ + + /* Check if eDMA is busy: if the channel has started transfer, CSR will be + * non-zero. + */ + + regval32 = getreg32(base + IMX9_EDMA_CH_CSR_OFFSET); + + if (regval32 != 0 && (regval32 & EDMA_CH_CSR_DONE) == 0) + { + return -EBUSY; + } + + /* Configure channel TCD registers to the values specified in config. */ + + imx9_tcd_configure((struct imx9_edmatcd_s *) + (base + IMX9_EDMA_TCD_SADDR_OFFSET), config); + + /* Enable the DONE interrupt when the major iteration count completes. */ + + modifyreg16(base + IMX9_EDMA_TCD_CSR_OFFSET, 0, EDMA_TCD_CSR_INTMAJOR); +#endif + + dmach->state = IMX9_DMA_CONFIGURED; + return OK; +} + +/**************************************************************************** + * Name: imx9_dmach_start + * + * Description: + * Start the DMA transfer. This function should be called after the final + * call to imx9_dmach_xfrsetup() in order to avoid race conditions. + * + * At the conclusion of each major DMA loop, a callback to the user + * provided function is made: |For "normal" DMAs, this will correspond to + * the DMA DONE interrupt; for scatter gather DMAs, + * this will be generated with the final TCD. + * + * At the conclusion of the DMA, the DMA channel is reset, all TCDs are + * freed, and the callback function is called with the the success/fail + * result of the DMA. + * + * NOTE: On Rx DMAs (peripheral-to-memory or memory-to-memory), it is + * necessary to invalidate the destination memory. That is not done + * automatically by the DMA module. Invalidation of the destination memory + * regions is the responsibility of the caller. + * + * Input Parameters: + * handle - DMA channel handle created by imx9_dmach_alloc() + * callback - The callback to be invoked when the DMA is completes or is + * aborted. + * arg - An argument that accompanies the callback + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int imx9_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, + void *arg) +{ + struct imx9_dmach_s *dmach = (struct imx9_dmach_s *)handle; + uintptr_t base = IMX9_EDMA_TCD(dmach->base, dmach->chan); + irqstate_t flags; + uint32_t regval; + uint8_t chan; + + DEBUGASSERT(dmach != NULL && dmach->state == IMX9_DMA_CONFIGURED); + chan = dmach->chan; + dmainfo("dmach%u: %p callback: %p arg: %p\n", chan, dmach, callback, arg); + + /* Save the callback info. This will be invoked when the DMA completes */ + + flags = spin_lock_irqsave(NULL); + dmach->callback = callback; + dmach->arg = arg; + +#if CONFIG_IMX9_EDMA_NTCD > 0 + /* Although it is not recommended, it might be possible to call this + * function multiple times while adding TCDs on the fly. + */ + + if (dmach->state != IMX9_DMA_ACTIVE) +#endif + { + dmach->state = IMX9_DMA_ACTIVE; + + regval = getreg32(base + IMX9_EDMA_CH_CSR_OFFSET); + regval |= EDMA_CH_CSR_ERQ | EDMA_CH_CSR_EEI; + putreg32(regval, base + IMX9_EDMA_CH_CSR_OFFSET); + } + + spin_unlock_irqrestore(NULL, flags); + return OK; +} + +/**************************************************************************** + * Name: imx9_dmach_stop + * + * Description: + * Cancel the DMA. After imx9_dmach_stop() is called, the DMA channel + * is reset, all TCDs are freed, and imx9_dmarx/txsetup() must be called + * before imx9_dmach_start() can be called again. + * + * Input Parameters: + * handle - DMA channel handle created by imx9_dmach_alloc() + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void imx9_dmach_stop(DMACH_HANDLE handle) +{ + struct imx9_dmach_s *dmach = (struct imx9_dmach_s *)handle; + irqstate_t flags; + + dmainfo("dmach: %p\n", dmach); + DEBUGASSERT(dmach != NULL); + + flags = spin_lock_irqsave(NULL); + imx9_dmaterminate(dmach, -EINTR); + spin_unlock_irqrestore(NULL, flags); +} + +/**************************************************************************** + * Name: imx9_dmach_getcount + * + * Description: + * This function checks the TCD (Task Control Descriptor) status for a + * specified eDMA channel and returns the the number of major loop counts + * that have not finished. + * + * NOTES: + * 1. This function can only be used to get unfinished major loop count of + * transfer without the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly + * from registers while the channel is running. + * + * Because to calculate the remaining bytes, the initial NBYTES configured + * in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not + * support getting it while a channel is active. In another words, the + * NBYTES value reading is always the actual (decrementing) NBYTES value + * the dma_engine is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved + * initial value of NBYTES (for example copied before enabling the channel) + * is needed. The formula to calculate it is shown below: + * + * RemainingBytes = RemainingMajorLoopCount * + * NBYTES(initially configured) + * + * Input Parameters: + * handle - DMA channel handle created by imx9_dmach_alloc() + * + * Returned Value: + * Major loop count which has not been transferred yet for the current TCD. + * + ****************************************************************************/ + +unsigned int imx9_dmach_getcount(DMACH_HANDLE *handle) +{ + struct imx9_dmach_s *dmach = (struct imx9_dmach_s *)handle; + uintptr_t base = IMX9_EDMA_TCD(dmach->base, dmach->chan); + unsigned int remaining = 0; + uintptr_t regval32; + uint16_t regval16; + + DEBUGASSERT(dmach != NULL); + + /* If the DMA is done, then the remaining count is zero */ + + regval32 = getreg32(base + IMX9_EDMA_CH_CSR_OFFSET); + + if ((regval32 & EDMA_CH_CSR_DONE) == 0) + { + /* Calculate the unfinished bytes */ + + regval16 = getreg16(base + IMX9_EDMA_TCD_CITER_OFFSET); + + if ((regval16 & EDMA_TCD_CITER_ELINK) != 0) + { + remaining = (regval16 & EDMA_TCD_CITER_MASK_ELINK) >> + EDMA_TCD_CITER_SHIFT; + } + else + { + remaining = (regval16 & EDMA_TCD_CITER_MASK) >> + EDMA_TCD_CITER_SHIFT; + } + } + + return remaining; +} + +/**************************************************************************** + * Name: imx9_dmach_idle + * + * Description: + * This function checks if the dma is idle + * + * Returned Value: + * 0 - if idle + * !0 - not + * + ****************************************************************************/ + +unsigned int imx9_dmach_idle(DMACH_HANDLE handle) +{ + struct imx9_dmach_s *dmach = (struct imx9_dmach_s *)handle; + return dmach->state == IMX9_DMA_IDLE ? 0 : -1; +} + +/**************************************************************************** + * Name: imx9_dmasample + * + * Description: + * Sample DMA register contents + * + * Assumptions: + * - DMA handle allocated by imx9_dmach_alloc() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void imx9_dmasample(DMACH_HANDLE handle, struct imx9_dmaregs_s *regs) +{ + struct imx9_dmach_s *dmach = (struct imx9_dmach_s *)handle; + unsigned int chan; + irqstate_t flags; + uintptr_t base = IMX9_EDMA_TCD(dmach->base, dmach->chan); + + DEBUGASSERT(dmach != NULL && regs != NULL); + chan = dmach->chan; + regs->chan = chan; + + /* eDMA Global Registers */ + + flags = spin_lock_irqsave(NULL); + + /* REVISIT: eDMA4 does not show INT_HIGH / HRS_HIGH values correctly */ + + regs->cr = getreg32(IMX9_EDMA_CSR(base)); /* Control */ + regs->es = getreg32(IMX9_EDMA_ES(base)); /* Error Status */ + regs->req = getreg32(IMX9_EDMA_INT); /* Interrupt Request */ + regs->hrs = getreg32(IMX9_EDMA_HRS); /* Hardware Request Status */ + + /* eDMA TCD */ + + regs->saddr = getreg32(base + IMX9_EDMA_TCD_SADDR_OFFSET); + regs->soff = getreg16(base + IMX9_EDMA_TCD_SOFF_OFFSET); + regs->attr = getreg16(base + IMX9_EDMA_TCD_ATTR_OFFSET); + regs->nbml = getreg32(base + IMX9_EDMA_TCD_NBYTES_OFFSET); + regs->slast = getreg32(base + IMX9_EDMA_TCD_SLAST_SDA_OFFSET); + regs->daddr = getreg32(base + IMX9_EDMA_TCD_DADDR_OFFSET); + regs->doff = getreg16(base + IMX9_EDMA_TCD_DOFF_OFFSET); + regs->citer = getreg16(base + IMX9_EDMA_TCD_CITER_OFFSET); + regs->dlastsga = getreg32(base + IMX9_EDMA_TCD_DLAST_SGA_OFFSET); + regs->csr = getreg16(base + IMX9_EDMA_TCD_CSR_OFFSET); + regs->biter = getreg16(base + IMX9_EDMA_TCD_BITER_OFFSET); + + /* DMAMUX registers */ + + if (imx9_edma_tcdhasmux(dmach->base)) + { + regs->dmamux = getreg32(base + IMX9_EDMA_CH_MUX_OFFSET); + } + else + { + regs->dmamux = 0; + } + + spin_unlock_irqrestore(NULL, flags); +} +#endif /* CONFIG_DEBUG_DMA */ + +/**************************************************************************** + * Name: imx9_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + * Assumptions: + * - DMA handle allocated by imx9_dmach_alloc() + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void imx9_dmadump(const struct imx9_dmaregs_s *regs, const char *msg) +{ + unsigned int chan; + + DEBUGASSERT(regs != NULL && msg != NULL); + + chan = regs->chan; + DEBUGASSERT(chan < IMX9_EDMA_NCHANNELS); + + dmainfo("%s\n", msg); + dmainfo(" eDMA Global Registers:\n"); + dmainfo(" CR: %08x\n", (unsigned int)regs->cr); + dmainfo(" ES: %08x\n", (unsigned int)regs->es); + dmainfo(" INT: %08x\n", (unsigned int)regs->req); + dmainfo(" EARS: %08x\n", (unsigned int)regs->hrs); + + /* eDMA Channel registers */ + + dmainfo(" eDMA Channel %u Registers:\n", chan); + dmainfo(" DCHPRI: %02x\n", regs->dchpri); + + /* eDMA TCD */ + + dmainfo(" eDMA Channel %u TCD Registers:\n", chan); + dmainfo(" SADDR: %08x\n", (unsigned int)regs->saddr); + dmainfo(" SOFF: %04x\n", (unsigned int)regs->soff); + dmainfo(" ATTR: %04x\n", (unsigned int)regs->attr); + dmainfo(" NBML: %05x\n", (unsigned int)regs->nbml); + dmainfo(" SLAST: %05x\n", (unsigned int)regs->slast); + dmainfo(" DADDR: %05x\n", (unsigned int)regs->daddr); + dmainfo(" DOFF: %04x\n", (unsigned int)regs->doff); + dmainfo(" CITER: %04x\n", (unsigned int)regs->citer); + dmainfo(" DLASTSGA: %08x\n", (unsigned int)regs->dlastsga); + dmainfo(" CSR: %04x\n", (unsigned int)regs->csr); + dmainfo(" BITER: %04x\n", (unsigned int)regs->biter); + + /* DMAMUX registers */ + + dmainfo(" DMAMUX Channel %u Registers:\n", chan); + dmainfo(" DMAMUX: %08x\n", (unsigned int)regs->dmamux); +} +#endif /* CONFIG_DEBUG_DMA */ +#endif /* CONFIG_IMX9_EDMA */ diff --git a/arch/arm64/src/imx9/imx9_edma.h b/arch/arm64/src/imx9/imx9_edma.h new file mode 100644 index 0000000000000..4f3a4ac73eafa --- /dev/null +++ b/arch/arm64/src/imx9/imx9_edma.h @@ -0,0 +1,482 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_edma.h + * + * Copyright (C) 2019, 2021, 2023 Gregory Nutt. All rights reserved. + * Copyright 2022 NXP + * Authors: Gregory Nutt + * David Sidrane + * Peter van der Perk + * + * This file was leveraged from the NuttX S32K1 port. Portions of that eDMA + * logic derived from NXP sample code which has a compatible BSD 3-clause + * license: + * + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * Copyright 2016-2017 NXP + * All rights reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_EDMA_H +#define __ARCH_ARM64_SRC_IMX9_IMX9_EDMA_H + +/* General Usage: + * + * 1. Allocate a DMA channel + * + * DMACH_HANDLE handle; + * handle = edma_dmach_alloc(dmamux, dchpri); + * + * Where 'dmamux' is the channel DMAMUX configuration register setting and + * 'dchpri' is the channel DCHPRIO priority register setting. + * + * 2. Create the transfer configuration: + * + * struct imx9_edma_xfrconfig_s config; + * config.saddr = ..; + * config.daddr = ..; + * etc. + * + * 3. Setup the transfer in hardware: + * + * int ret; + * ret = imx9_dmach_xfrsetup(handle, &config); + * + * 4. If you are setting up a scatter gather DMA + * (with CONFIG_IMX9_EDMA_NTCD > 0), then repeat steps 2 and 3 for + * each segment of the transfer. + * + * 5. Start the DMA: + * + * ret = imx9_dmach_start(handle, my_callback_func, priv); + * + * Where my_callback_func() is called when the DMA completes or an error + * occurs. 'priv' represents some internal driver state that will be + * provided with the callback. + * + * 6. If you need to stop the DMA and free resources (such as if a timeout + * occurs), then: + * + * i mxrt_dmach_stop(handle); + * + * 7. The callback will be received when the DMA completes (or an error + * occurs). After that, you may free the DMA channel, or re-use it on + * subsequent DMAs. + * + * imx9_dmach_free(handle); + * + * Almost non-invasive debug instrumentation is available. You may call + * imx9_dmasample() to save the current state of the eDMA registers at + * any given point in time. At some later, postmortem analysis, you can + * dump the content of the buffered registers with imx9_dmadump(). + * imx9_dmasample() is also available for monitoring DMA progress. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration flags. + * + * REVISIT: Many missing options that should be represented as flags: + * 1. Bandwidth + * 2. Source/Destination modulo + */ + +#define EDMA_CONFIG_LINKTYPE_SHIFT (0) /* Bits 0-1: Link type */ +#define EDMA_CONFIG_LINKTYPE_MASK (3 << EDMA_CONFIG_LINKTYPE_SHIFT) +# define EDMA_CONFIG_LINKTYPE_LINKNONE (0 << EDMA_CONFIG_LINKTYPE_SHIFT) /* No channel link */ +# define EDMA_CONFIG_LINKTYPE_MINORLINK (1 << EDMA_CONFIG_LINKTYPE_SHIFT) /* Channel link after each minor loop */ +# define EDMA_CONFIG_LINKTYPE_MAJORLINK (2 << EDMA_CONFIG_LINKTYPE_SHIFT) /* Channel link when major loop count exhausted */ + +#define EDMA_CONFIG_LOOP_SHIFT (2) /* Bits 2: Loop type */ +#define EDMA_CONFIG_LOOP_MASK (3 << EDMA_CONFIG_LOOP_SHIFT) +# define EDMA_CONFIG_LOOPNONE (0 << EDMA_CONFIG_LOOP_SHIFT) /* No looping */ +# define EDMA_CONFIG_LOOPSRC (1 << EDMA_CONFIG_LOOP_SHIFT) /* Source looping */ +# define EDMA_CONFIG_LOOPDEST (2 << EDMA_CONFIG_LOOP_SHIFT) /* Dest looping */ + +#define EDMA_CONFIG_INTHALF (1 << 4) /* Bits 4: Int on HALF */ +#define EDMA_CONFIG_INTMAJOR (1 << 5) /* Bits 5: Int on all Major completion + * Default is only on last completion + * if using scatter gather + */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef void *DMACH_HANDLE; +typedef void (*edma_callback_t)(DMACH_HANDLE handle, + void *arg, bool done, int result); + +/* eDMA transfer type */ + +enum imx9_edma_xfrtype_e +{ + EDMA_MEM2MEM = 0, /* Transfer from memory to memory */ + EDMA_PERIPH2MEM, /* Transfer from peripheral to memory */ + EDMA_MEM2PERIPH, /* Transfer from memory to peripheral */ +}; + +/* eDMA transfer sises */ + +enum imx9_edma_sizes_e +{ + EDMA_8BIT = 0, /* Transfer data size 8 */ + EDMA_16BIT = 1, /* Transfer data size 16 */ + EDMA_32BIT = 2, /* Transfer data size 32 */ + EDMA_64BIT = 3, /* Transfer data size 64 */ + EDMA_16BYTE = 4, /* Transfer data size 16-byte */ + EDMA_32BYTE = 5, /* Transfer data size 32-byte */ + EDMA_64BYTE = 6, /* Transfer data size 64-byte */ +}; + +/* This structure holds the source/destination transfer attribute + * configuration. + */ + +struct imx9_edma_xfrconfig_s +{ + uintptr_t saddr; /* Source data address. */ + uintptr_t daddr; /* Destination data address. */ + int16_t soff; /* Sign-extended offset for current source address. */ + int16_t doff; /* Sign-extended offset for current destination address. */ + uint16_t iter; /* Major loop iteration count. */ + uint8_t flags; /* See EDMA_CONFIG_* definitions */ + uint8_t ssize; /* Source data transfer size (see TCD_ATTR_SIZE_* definitions in rdware/. */ + uint8_t dsize; /* Destination data transfer size. */ +#ifdef CONFIG_IMX9_EDMA_EMLIM + uint16_t nbytes; /* Bytes to transfer in a minor loop */ +#else + uint32_t nbytes; /* Bytes to transfer in a minor loop */ +#endif +#ifdef CONFIG_IMX9_EDMA_MOD + uint8_t smod; + uint8_t dmod; +#endif +#ifdef CONFIG_IMX9_EDMA_BWC + uint8_t bwc; +#endif +#ifdef CONFIG_IMX9_EDMA_ELINK + DMACH_HANDLE linkch; /* Link channel (With EDMA_CONFIG_LINKTYPE_* flags) */ +#endif +}; + +/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA + * is selected + */ + +#ifdef CONFIG_DEBUG_DMA +struct imx9_dmaregs_s +{ + uint8_t chan; /* Sampled channel */ + + /* eDMA Global Registers */ + + uint32_t cr; /* Control */ + uint32_t es; /* Error Status */ + uint32_t req; /* Interrupt Request */ + uint32_t hrs; /* Hardware Request Status */ + + /* eDMA Channel registers */ + + uint8_t dchpri; /* Channel priority */ + + /* eDMA TCD */ + + uint32_t saddr; /* TCD Source Address */ + uint16_t soff; /* TCD Signed Source Address Offset */ + uint16_t attr; /* TCD Transfer Attributes */ + uint32_t nbml; /* TCD Signed Minor Loop Offset / Byte Count */ + uint32_t slast; /* TCD Last Source Address Adjustment */ + uint32_t daddr; /* TCD Destination Address */ + uint16_t doff; /* TCD Signed Destination Address Offset */ + uint16_t citer; /* TCD Current Minor Loop Link, Major Loop Count */ + uint32_t dlastsga; /* TCD Last Destination Address Adjustment/Scatter Gather Address */ + uint16_t csr; /* TCD Control and Status */ + uint16_t biter; /* TCD Beginning Minor Loop Link, Major Loop Count */ + + /* DMAMUX registers */ + + uint32_t dmamux; /* Channel configuration */ +}; +#endif /* CONFIG_DEBUG_DMA */ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_dmach_alloc + * + * Allocate a DMA channel. This function sets aside a DMA channel, + * initializes the DMAMUX for the channel, then gives the caller exclusive + * access to the DMA channel. + * + * Input Parameters: + * dmamux - DMAMUX configuration see DMAMUX channel configuration register + * bit-field definitions in hardware/imx9_dmamux.h. + * Settings include: + * + * DMAMUX_CHCFG_SOURCE Chip-specific DMA source (required) + * DMAMUX_CHCFG_TRIG DMA Channel Trigger Enable (optional) + * DMAMUX_CHCFG_ENBL DMA Mux Channel Enable (required) + * + * A value of zero will disable the DMAMUX channel. + * dchpri - DCHPRI channel priority configuration. See DCHPRI channel + * configuration register bit-field definitions in + * hardware/imx9_edma.h. Meaningful settings include: + * + * EDMA_DCHPRI_CHPRI Channel Arbitration Priority + * DCHPRI_DPA Disable Preempt Ability + * DCHPRI_ECP Enable Channel Preemption + * + * The power-on default, 0x05, is a reasonable choice. + * + * Returned Value: + * If a DMA channel is available, this function returns a non-NULL, void* + * DMA channel handle. NULL is returned on any failure. + * + ****************************************************************************/ + +DMACH_HANDLE imx9_dmach_alloc(uint16_t dmamux, uint8_t dchpri); + +/**************************************************************************** + * Name: imx9_dmach_free + * + * Description: + * Release a DMA channel. + * NOTE: The 'handle' used in this argument must NEVER be used again + * until imx9_dmach_alloc() is called again to re-gain a valid handle. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx9_dmach_free(DMACH_HANDLE handle); + +/**************************************************************************** + * Name: imx9_dmach_xfrsetup + * + * Description: + * This function adds the eDMA transfer to the DMA sequence. The request + * is setup according to the content of the transfer configuration + * structure. For "normal" DMA, imx9_dmach_xfrsetup is called only + * once. + * Scatter/gather DMA is accomplished by calling this function repeatedly, + * once for each transfer in the sequence. Scatter/gather DMA processing + * is enabled automatically when the second transfer configuration is + * received. + * + * This function may be called multiple times to handle multiple, + * discontinuous transfers (scatter-gather) + * + * Input Parameters: + * handle - DMA channel handle created by imx9_dmach_alloc() + * config - A DMA transfer configuration instance, populated by the + * The content of 'config' describes the transfer + * + * Returned Value + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int imx9_dmach_xfrsetup(DMACH_HANDLE *handle, + const struct imx9_edma_xfrconfig_s *config); + +/**************************************************************************** + * Name: imx9_dmach_start + * + * Description: + * Start the DMA transfer by enabling the channel DMA request. + * This function should be called after the final call to + * imx9_dmasetup() in order to avoid race conditions. + * + * At the conclusion of each major DMA loop, a callback to the + * user-provided function is made: |For "normal" DMAs, this will + * correspond to the DMA DONE interrupt; for scatter gather DMAs, multiple + * interrupts will be generated with the final being the DONE interrupt. + * + * At the conclusion of the DMA, the DMA channel is reset, all TCDs are + * freed, and the callback function is called with the the success/fail + * result of the DMA. + * + * NOTE: + * On Rx DMAs (peripheral-to-memory or memory-to-memory), it is necessary + * to invalidate the destination memory. That is not done automatically + * by the DMA module. Invalidation of the destination memory regions is + * the responsibility of the caller. + * + * Input Parameters: + * handle - DMA channel handle created by imx9_dmach_alloc() + * callback - The callback to be invoked when the DMA is completes or is + * aborted. + * arg - An argument that accompanies the callback + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int imx9_dmach_start(DMACH_HANDLE handle, edma_callback_t callback, + void *arg); + +/**************************************************************************** + * Name: imx9_dmach_stop + * + * Description: + * Cancel the DMA. After imx9_dmach_stop() is called, the DMA channel + * is reset, all TCDs are freed, and imx9_dmarx/txsetup() must be called + * before imx9_dmach_start() can be called again + * + * Input Parameters: + * handle - DMA channel handle created by imx9_dmach_alloc() + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void imx9_dmach_stop(DMACH_HANDLE handle); + +/**************************************************************************** + * Name: imx9_dmach_getcount + * + * Description: + * This function checks the TCD (Task Control Descriptor) status for a + * specified eDMA channel and returns the the number of major loop counts + * that have not finished. + * + * NOTES: + * 1. This function can only be used to get unfinished major loop count of + * transfer without the next TCD, or it might be inaccuracy. + * 2. The unfinished/remaining transfer bytes cannot be obtained directly + * from registers while the channel is running. + * + * Because to calculate the remaining bytes, the initial NBYTES configured + * in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not + * support getting it while a channel is active. In another words, the + * NBYTES value reading is always the actual (decrementing) NBYTES value + * the dma_engine is working with while a channel is running. + * Consequently, to get the remaining transfer bytes, a software-saved + * initial value of NBYTES (for example copied before enabling the channel) + * is needed. The formula to calculate it is shown below: + * + * RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured) + * + * Input Parameters: + * handle - DMA channel handle created by imx9_dmach_alloc() + * + * Returned Value: + * Major loop count which has not been transferred yet for the current TCD. + * + ****************************************************************************/ + +unsigned int imx9_dmach_getcount(DMACH_HANDLE *handle); + +/**************************************************************************** + * Name: imx9_dmach_idle + * + * Description: + * This function checks if the dma is idle + * + * Returned Value: + * 0 - if idle + * !0 - not + * + ****************************************************************************/ + +unsigned int imx9_dmach_idle(DMACH_HANDLE handle); + +/**************************************************************************** + * Name: imx9_dmasample + * + * Description: + * Sample DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void imx9_dmasample(DMACH_HANDLE handle, struct imx9_dmaregs_s *regs); +#else +# define imx9_dmasample(handle,regs) +#endif + +/**************************************************************************** + * Name: imx9_dmadump + * + * Description: + * Dump previously sampled DMA register contents + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_DMA +void imx9_dmadump(const struct imx9_dmaregs_s *regs, const char *msg); +#else +# define imx9_dmadump(handle,regs,msg) +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM64_SRC_IMX9_IMX9_EDMA_H */ diff --git a/arch/arm64/src/imx9/imx9_enet.c b/arch/arm64/src/imx9/imx9_enet.c new file mode 100644 index 0000000000000..b6a501362bfc5 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_enet.c @@ -0,0 +1,3215 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_enet.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_NET_PKT +# include +#endif + +#include + +#include "arm64_internal.h" +#include "chip.h" +#include "hardware/imx9_enet.h" +#include "imx9_enet.h" + +#include "imx9_ccm.h" +#include "imx9_iomuxc.h" +#include "hardware/imx9_ccm.h" +#include "hardware/imx9_pinmux.h" + +#ifdef CONFIG_IMX9_ENET + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If processing is not done at the interrupt level, then work queue support + * is required. + */ + +#if !defined(CONFIG_SCHED_LPWORK) +# error LPWORK queue support is required +#endif + +#define ETHWORK LPWORK + +/* We need at least two TX buffers for reliable operation */ + +#if CONFIG_IMX9_ENET_NTXBUFFERS < 1 +#define IMX9_ENET_NTXBUFFERS 1 +#else +#define IMX9_ENET_NTXBUFFERS CONFIG_IMX9_ENET_NTXBUFFERS +#endif + +/* We need an even number of RX buffers, since RX descriptors are + * freed for the DMA in pairs due to two descriptors always fitting + * in one cache line (cahce line size is 64, descriptor size is 32) + */ + +#if CONFIG_IMX9_ENET_NRXBUFFERS < 2 +#define IMX9_ENET_NRXBUFFERS 2 +#elif CONFIG_IMX9_ENET_NRXBUFFERS & 1 +#define IMX9_ENET_NRXBUFFERS (CONFIG_IMX9_ENET_NRXBUFFERS + 1) +#else +#define IMX9_ENET_NRXBUFFERS CONFIG_IMX9_ENET_NRXBUFFERS +#endif + +#define nitems(_a) (sizeof(_a) / sizeof(0[(_a)])) + +#define ALIGNED_BUFSIZE ENET_ALIGN_UP(CONFIG_NET_ETH_PKTSIZE + \ + CONFIG_NET_GUARDSIZE) + +/* TX timeout = 1 second */ + +#define IMX9_TXTIMEOUT (CLK_TCK) +#define MII_MAXPOLLS (0x1ffff) +#define LINK_WAITUS (100 * 1000) +#define LINK_NLOOPS (50) + +/* PHY reset tim in loop counts */ + +#define PHY_RESET_WAIT_COUNT (10) + +/* Estimate the MII_SPEED in order to get an MDC close to 2.5MHz, + * based on the internal module (ENET) clock: + + * MII clock frequency = 133 MHz / ((26 + 1) x 2) = 2.5 MHz + * + * TODO: This is hard-coded for now, could be properly calculated + */ + +#define IMX9_MII_SPEED 26 + +/* Interrupt groups */ + +#define RX_INTERRUPTS (ENET_INT_RXF | ENET_INT_RXB) +#define TX_INTERRUPTS ENET_INT_TXF +#define ERROR_INTERRUPTS (ENET_INT_UN | ENET_INT_RL | ENET_INT_LC | \ + ENET_INT_EBERR | ENET_INT_BABT | ENET_INT_BABR) + +/* The subset of errors that require us to reset the hardware - this list + * may need to be revisited if it's found that some error above leads to a + * locking up of the Ethernet interface. + */ + +#define CRITICAL_ERROR (ENET_INT_UN | ENET_INT_RL | ENET_INT_EBERR) + +/* This is a helper pointer for accessing + * the contents of the Ethernet header + */ + +#define BUF ((struct eth_hdr_s *)priv->dev.d_buf) + +#define IMX93_OCOTP_UID_OFFSET 0xc0 + +#define MMD1 1 +#define MMD1_PMA_STATUS1 1 +#define MMD1_PS1_RECEIVE_LINK_STATUS (1 << 2) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +enum phy_type_t +{ + PHY_NONE = 0, + PHY_RMII = 1, + PHY_RGMII = 2, +}; + +/* The imx9_driver_s encapsulates all state information for + * a single hardware interface + */ + +struct imx9_driver_s +{ + struct net_driver_s dev; /* Interface understood by the network */ + const uint32_t base; /* Base address of ENET controller */ + const int clk_gate; /* Enet clock gate */ + const int irq; /* Enet interrupt */ + const struct phy_desc_s * phy_list; /* Supported PHYs for this IF */ + const int n_phys; /* Number of supported PHYs */ + struct enet_txdesc_s * const txdesc; /* A pointer to the list of TX descriptor */ + struct enet_desc_s * const rxdesc; /* A pointer to the list of RX descriptors */ + const uintptr_t buffer_pool; /* DMA buffer pool */ +#ifdef CONFIG_IMX9_ENET_USE_OTP_MAC + const off_t otp_mac_off; /* MAC address offset in OTP */ +#endif + const bool promiscuous; /* Set promiscuous mode */ + const enum phy_type_t phy_type; /* PHY type */ + const bool autoneg; /* Phy autonegotiation enabled */ + const bool force_speed; /* Disable autonegotiation and force speed */ + bool full_duplex; /* Manually set to full duplex mode */ + bool s_10mbps; /* Manually set to 10 MBPS */ + bool s_100mbps; /* Manually set to 100 M0BPS */ + bool s_1000mbps; /* Manually set to 1GBPS */ + const struct phy_desc_s * cur_phy; /* Currently selected phy */ + bool bifup; /* true:ifup false:ifdown */ + uint8_t txhead; /* The next TX descriptor to use */ + uint8_t rxtail; /* The next RX descriptor to use */ + uint8_t phyaddr; /* Selected PHY address */ + struct wdog_s txtimeout; /* TX timeout timer */ + uint32_t ints; /* Enabled interrupts */ + struct work_s irqwork; /* For deferring interrupt work to the work queue */ + struct work_s pollwork; /* For deferring poll work to the work queue */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Utility functions */ + +static inline uint32_t imx9_enet_getreg32(struct imx9_driver_s *priv, + uint32_t offset); +static inline void imx9_enet_putreg32(struct imx9_driver_s *priv, + uint32_t value, uint32_t offset); + +static inline void imx9_enet_modifyreg32(struct imx9_driver_s *priv, + unsigned int offset, + uint32_t clearbits, + uint32_t setbits); + +/* Common TX logic */ + +static bool imx9_txringfull(struct imx9_driver_s *priv); +static int imx9_transmit(struct imx9_driver_s *priv, + uint32_t *buf_swap); +static int imx9_txpoll(struct net_driver_s *dev); + +/* Interrupt handling */ + +static void imx9_dispatch(struct imx9_driver_s *priv); +static void imx9_receive(struct imx9_driver_s *priv); +static void imx9_txdone(struct imx9_driver_s *priv); + +static void imx9_enet_interrupt_work(void *arg); +static int imx9_enet_interrupt(int irq, void *context, void *arg); + +/* Watchdog timer expirations */ + +static void imx9_txtimeout_work(void *arg); +static void imx9_txtimeout_expiry(wdparm_t arg); + +/* NuttX callback functions */ + +static int imx9_ifup(struct net_driver_s *dev); +static int imx9_ifdown(struct net_driver_s *dev); + +static void imx9_txavail_work(void *arg); +static int imx9_txavail(struct net_driver_s *dev); + +/* Internal ifup function that allows phy reset to be optional */ + +static int imx9_ifup_action(struct net_driver_s *dev, bool resetphy); + +#ifdef CONFIG_NET_MCASTGROUP +static int imx9_addmac(struct net_driver_s *dev, const uint8_t *mac); +static int imx9_rmmac(struct net_driver_s *dev, const uint8_t *mac); +#endif + +#ifdef CONFIG_NETDEV_IOCTL +static int imx9_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg); +#endif + +/* PHY/MII support */ + +static int imx9_phy_is(struct imx9_driver_s *priv, const char *name); +static int imx9_determine_phy(struct imx9_driver_s *priv); + +#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) +static int imx9_phyintenable(struct imx9_driver_s *priv); +#endif +static inline void imx9_initmii(struct imx9_driver_s *priv); +static int imx9_writemii(struct imx9_driver_s *priv, uint8_t regaddr, + uint16_t data); +static int imx9_readmii(struct imx9_driver_s *priv, uint8_t regaddr, + uint16_t *data); +static int imx9_initphy(struct imx9_driver_s *priv, bool renogphy); + +static int imx9_readmmd(struct imx9_driver_s *priv, uint8_t mmd, + uint16_t regaddr, uint16_t *data); +#if 0 +static int imx9_writemmd(struct imx9_driver_s *priv, uint8_t mmd, + uint16_t regaddr, uint16_t data); +#endif + +/* Initialization */ + +static void imx9_initbuffers(struct imx9_driver_s *priv); +static void imx9_reset(struct imx9_driver_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_IMX9_ENET1 + +/* If the board didn't provide a list of known PHYs, we can still work with + * autonegotiation disabled and setting the speed manually + */ + +#ifndef BOARD_ENET1_PHY_LIST +#define BOARD_ENET1_PHY_LIST {} +#endif + +static const struct phy_desc_s g_enet1_phy_list[] = BOARD_ENET1_PHY_LIST; + +/* The DMA descriptors */ + +static struct enet_txdesc_s g_enet1_tx_desc_pool[IMX9_ENET_NTXBUFFERS] + aligned_data(ENET_ALIGN); +static struct enet_desc_s g_enet1_rx_desc_pool[IMX9_ENET_NRXBUFFERS] + aligned_data(ENET_ALIGN); + +/* The DMA buffers */ + +static uint8_t g_enet_1_buffer_pool + [IMX9_ENET_NTXBUFFERS + IMX9_ENET_NRXBUFFERS][ALIGNED_BUFSIZE] + aligned_data(ENET_ALIGN); +#endif + +static struct imx9_driver_s g_enet[] = +{ +#ifdef CONFIG_IMX9_ENET1 + { + .dev = + { + .d_ifup = imx9_ifup, + .d_ifdown = imx9_ifdown, + .d_txavail = imx9_txavail, + +# ifdef CONFIG_NET_MCASTGROUP + .d_addmac = imx9_addmac, + .d_rmmac = imx9_rmmac, +# endif + +# ifdef CONFIG_NETDEV_IOCTL + .d_ioctl = imx9_ioctl, +# endif + }, + .base = IMX9_ENET_BASE, + .clk_gate = CCM_LPCG_ENET1, + .irq = IMX9_IRQ_ENET, + .phy_list = g_enet1_phy_list, + .n_phys = nitems(g_enet1_phy_list), + .txdesc = g_enet1_tx_desc_pool, + .rxdesc = g_enet1_rx_desc_pool, + .buffer_pool = (const uintptr_t)g_enet_1_buffer_pool, + +# ifdef CONFIG_IMX9_ENET_USE_OTP_MAC + .otp_mac_off = CONFIG_IMX9_ENET1_OTP_MAC_ADDR, +# endif + +# ifdef CONFIG_IMX9_ENET1_PROMISCUOUS + .promiscuous = trued +# endif + +# ifdef CONFIG_IMX9_ENET1_RGMII + .phy_type = PHY_RGMII, +# elif defined(CONFIG_IMX9_ENET1_RMII) + .phy_type = PHY_RMII, +# else +# error PHY must be RGMII or RMII +# endif + + /* Duplex: default to FD */ + +# if defined(CONFIG_IMX9_ENET1_PHY_FD) || defined(CONFIG_IMX9_ENET1_PHY_AUTONEG) + .full_duplex = true, +# endif + + /* 10 mbps, default to false */ + +# ifdef CONFIG_IMX9_ENET1_PHY_10MBPS + .s_10mbps = true, +# endif + + /* 100 mbps, default to true */ + +# if defined(CONFIG_IMX9_ENET1_PHY_100MBPS) || defined(CONFIG_IMX9_ENET1_PHY_AUTONEG) + .s_100mbps = true, +# endif + + /* 1000 mbps, default to false */ + +# ifdef CONFIG_IMX9_ENET1_PHY_1000MBPS + .s_1000mbps = true, +# endif + +# ifdef CONFIG_IMX9_ENET1_PHY_AUTONEG + .autoneg = true, +# else +# ifdef CONFIG_IMX9_ENET1_PHY_FORCE_SPEED + .force_speed = true, +# endif +# endif + }, +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_enet_getreg32 + * + * Description: + * Get the contents of the ENET register at offset + * + * Input Parameters: + * priv - private ENET device structure + * offset - offset to the register of interest + * + * Returned Value: + * The contents of the 32-bit register + * + ****************************************************************************/ + +static inline uint32_t imx9_enet_getreg32(struct imx9_driver_s *priv, + uint32_t offset) +{ + return getreg32(priv->base + offset); +} + +/**************************************************************************** + * Name: imx9_enet_putreg32 + * + * Description: + * Atomically modify the specified bits in a memory mapped register + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * clearbits - the 32-bit value to be written as 0s + * setbits - the 32-bit value to be written as 1s + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void imx9_enet_modifyreg32(struct imx9_driver_s *priv, + unsigned int offset, + uint32_t clearbits, + uint32_t setbits) +{ + modifyreg32(priv->base + offset, clearbits, setbits); +} + +/**************************************************************************** + * Name: imx9_enet_putreg32 + * + * Description: + * Write a 16-bit value to the ENET register at offset + * + * Input Parameters: + * priv - private SPI device structure + * value - the 32-bit value to be written + * offset - offset to the register of interest + * + * Returned Value: + * The contents of the 32-bit register + * + ****************************************************************************/ + +static inline void imx9_enet_putreg32(struct imx9_driver_s *priv, + uint32_t value, uint32_t offset) +{ + putreg32(value, priv->base + offset); +} + +/**************************************************************************** + * Function: dump_descriptor + * + * Description: + * Can be used for debugging; dumps the content of a DMA descriptor + * + * Input Parameters: + * desc - Pointer to DMA descriptor + * + * Returned Value: + * None + * + ****************************************************************************/ + +inline static void dump_descriptor(struct enet_desc_s *desc) +{ + _alert("length %d\n", desc->length); + _alert("status1 0x%04x\n", desc->status1); + _alert("data 0x%08x\n", desc->data); + _alert("status2 0x%08x\n", desc->status2); + _alert("checksum 0x%08x\n", desc->checksum); + _alert("lenproto 0x%08x\n", desc->lenproto); + _alert("bdu 0x%08x\n", desc->bdu); + _alert("timestamp 0x%08x\n", desc->timestamp); +} + +/**************************************************************************** + * Function: imx9_txringfull + * + * Description: + * Check if all of the TX descriptors are in use. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * true is the TX ring is full; false if there are free slots at the + * head index. + * + ****************************************************************************/ + +static bool imx9_txringfull(struct imx9_driver_s *priv) +{ + struct enet_desc_s *txdesc = &priv->txdesc[priv->txhead].d1; + struct enet_desc_s *txdesc2 = &priv->txdesc[priv->txhead].d2; + + up_invalidate_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct enet_txdesc_s)); + + return (txdesc2->status1 & TXDESC_R) != 0; +} + +/**************************************************************************** + * Function: imx9_transmit + * + * Description: + * Start hardware transmission. Called either from the txdone interrupt + * handling or from watchdog based polling. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static int imx9_transmit(struct imx9_driver_s *priv, uint32_t *buf_swap) +{ + struct enet_desc_s *txdesc = &priv->txdesc[priv->txhead].d1; + struct enet_desc_s *txdesc2 = &priv->txdesc[priv->txhead].d2; + int split; + uint32_t buf = (uintptr_t)priv->dev.d_buf; + int len = priv->dev.d_len; + + DEBUGASSERT(len > 0 && buf != 0); + DEBUGASSERT((buf & ENET_ALIGN_MASK) == 0); + + if (imx9_txringfull(priv)) + { + /* Ring is full; this can only happen if transmit is called directly + * from the receive path. The buffer is lost. + */ + + nerr("TX ring full, packet lost\n"); + NETDEV_TXERRORS(&priv->dev); + return -EBUSY; + } + + if (len > ALIGNED_BUFSIZE) + { + nerr("TX frame too large %d, max %d\n", len, + ALIGNED_BUFSIZE); + } + + /* We are done with the provided buffer after transmit */ + + priv->dev.d_buf = NULL; + priv->dev.d_len = 0; + + /* Increment statistics */ + + NETDEV_TXPACKETS(&priv->dev); + + /* Optimize the two-descriptor usage; if possible, align the second part + * on 64-byte boundary. Note that 0-length buffers are not accepted by + * the DMA, so we must put some data to both descriptors. + */ + + split = len > 64 ? 64 : 1; + + txdesc->length = split; + txdesc->status2 = TXDESC_TS /* | TXDESC_IINS | TXDESC_PINS */; + txdesc->bdu = 0x00000000; + + txdesc2->length = len - split; + txdesc2->status2 = TXDESC_TS | TXDESC_INT /* | TXDESC_IINS | TXDESC_PINS */; + txdesc2->bdu = 0x00000000; + + if (buf_swap) + { + /* Data was written into the RX buffer, so swap the TX and RX buffers */ + + DEBUGASSERT(*buf_swap == buf); + *buf_swap = txdesc->data; + txdesc->data = buf; + } + else + { + DEBUGASSERT(txdesc->data == buf); + } + + txdesc2->data = buf + split; + + ARM64_DSB(); + + /* Make sure the buffer data is in memory */ + + up_clean_dcache(buf, buf + len); + + /* Descriptors & buffer data are ready to send */ + + txdesc2->status1 = (txdesc2->status1 & TXDESC_W) | + (TXDESC_TC | TXDESC_L | TXDESC_R); + + /* Proceed to next descriptors */ + + priv->txhead++; + if (priv->txhead >= IMX9_ENET_NTXBUFFERS) + { + priv->txhead = 0; + } + + /* If all TX descriptors are in-flight, then we have to disable receive + * interrupts too. This is because receive events can trigger more un- + * stoppable transmit events. + */ + + if (imx9_txringfull(priv)) + { + priv->ints &= ~RX_INTERRUPTS; + } + + /* Enable TX interrupts */ + + priv->ints |= TX_INTERRUPTS; + imx9_enet_putreg32(priv, priv->ints, IMX9_ENET_EIMR_OFFSET); + + /* The latter descriptor was update first. This ensures that the DMA + * won't start before all the descriptor data has been updated and it + * is safe to clean the cache + */ + + ARM64_DMB(); + txdesc->status1 = TXDESC_R; + ARM64_DSB(); + + /* Make sure the descriptors are written from cache to memory */ + + up_clean_dcache((uintptr_t)txdesc, + (uintptr_t)txdesc + sizeof(struct enet_txdesc_s)); + + /* Start the TX transfer (if it was not already waiting for buffers) */ + + imx9_enet_putreg32(priv, ENET_TDAR, IMX9_ENET_TDAR_OFFSET); + + /* Setup the TX timeout watchdog (perhaps restarting the timer) */ + + wd_start(&priv->txtimeout, IMX9_TXTIMEOUT, + imx9_txtimeout_expiry, (wdparm_t)priv); + + return OK; +} + +/**************************************************************************** + * Function: imx9_txpoll + * + * Description: + * The transmitter is available, check if the network has any outgoing + * packets ready to send. This is a callback from devif_poll(). + * devif_poll() may be called: + * + * 1. When the preceding TX packet send is complete, + * 2. When the preceding TX packet send timesout and the interface is reset + * 3. During normal TX polling + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static int imx9_txpoll(struct net_driver_s *dev) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)dev; + + /* Send the packet */ + + imx9_transmit(priv, NULL); + + /* Check if the next TX descriptor is owned by the Ethernet DMA or + * CPU. We cannot perform the TX poll if we are unable to accept + * another packet for transmission. + */ + + if (imx9_txringfull(priv)) + { + return -EBUSY; + } + + /* Return 0 to continue polling */ + + return 0; +} + +/**************************************************************************** + * Function: imx9_dopoll + * + * Description: + * The function is called in order to perform an out-of-sequence TX poll. + * This is done: + * + * 1. After completion of a transmission (stm32_txdone), + * 2. When new TX data is available (stm32_txavail_process), and + * 3. After a TX timeout to restart the sending process + * (stm32_txtimeout_process). + * + * Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by interrupt handling logic. + * + ****************************************************************************/ + +static void imx9_dopoll(struct imx9_driver_s *priv) +{ + struct net_driver_s *dev = &priv->dev; + struct enet_desc_s *txdesc; + struct enet_desc_s *txdesc2; + + /* Check if the next TX descriptor is owned by the Ethernet DMA or + * CPU. We cannot perform the TX poll if we are unable to accept + * another packet for transmission. + */ + + if (!imx9_txringfull(priv)) + { + DEBUGASSERT(dev->d_len == 0 && dev->d_buf == NULL); + + txdesc = &priv->txdesc[priv->txhead].d1; + txdesc2 = &priv->txdesc[priv->txhead].d2; + + /* Debug: check for any errors in the previously sent descriptors. + * Note: cache line was invalidated in the imx9_txringfull already + */ + + if ((txdesc->status2 & TXDESC_STATUS2_ERRORS) != 0) + { + nerr("d1 status1 %x, status2 %x\n", txdesc->status1 & TXDESC_TXE, + txdesc->status2 & TXDESC_STATUS2_ERRORS); + } + + if ((txdesc2->status2 & TXDESC_STATUS2_ERRORS) != 0) + { + nerr("d2 status1 %x, status2 %x\n", txdesc2->status1 & TXDESC_TXE, + txdesc2->status2 & TXDESC_STATUS2_ERRORS); + } + + /* Poll for new data */ + + dev->d_buf = (uint8_t *)(uintptr_t)txdesc->data; + devif_poll(dev, imx9_txpoll); + dev->d_buf = NULL; + dev->d_len = 0; + } + else + { + nerr("TX ring full\n"); + } +} + +/**************************************************************************** + * Function: imx9_dispatch + * + * Description: + * A new Rx packet was received; dispatch that packet to the network layer + * as necessary. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by interrupt handling logic. + * + ****************************************************************************/ + +static inline void imx9_dispatch(struct imx9_driver_s *priv) +{ + /* Update statistics */ + + NETDEV_RXPACKETS(&priv->dev); + +#ifdef CONFIG_NET_PKT + /* When packet sockets are enabled, feed the frame into the tap */ + + pkt_input(&priv->dev); +#endif + +#ifdef CONFIG_NET_IPv4 + /* Check for an IPv4 packet */ + + if (BUF->type == HTONS(ETHTYPE_IP)) + { + ninfo("IPv4 frame\n"); + NETDEV_RXIPV4(&priv->dev); + + /* Receive an IPv4 packet from the network device */ + + ipv4_input(&priv->dev); + } + else +#endif +#ifdef CONFIG_NET_IPv6 + /* Check for an IPv6 packet */ + + if (BUF->type == HTONS(ETHTYPE_IP6)) + { + ninfo("IPv6 frame\n"); + NETDEV_RXIPV6(&priv->dev); + + /* Give the IPv6 packet to the network layer */ + + ipv6_input(&priv->dev); + } + else +#endif +#ifdef CONFIG_NET_ARP + /* Check for an ARP packet */ + + if (BUF->type == HTONS(ETHTYPE_ARP)) + { + NETDEV_RXARP(&priv->dev); + arp_input(&priv->dev); + } +#endif + else + { + priv->dev.d_buf = NULL; + priv->dev.d_len = 0; + NETDEV_RXDROPPED(&priv->dev); + } +} + +inline static bool imx9_rxdesc_full(struct enet_desc_s *rxdesc) +{ + up_invalidate_dcache((uintptr_t)rxdesc, + (uintptr_t)rxdesc + sizeof(struct enet_desc_s)); + + /* Check if the data buffer associated with the descriptor has + * been filled or reception terminated for errors + */ + + return (rxdesc->status1 & RXDESC_E) == 0; +} + +/**************************************************************************** + * Function: imx9_receive + * + * Description: + * An interrupt was received indicating the availability of a new RX packet + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by interrupt handling logic. + * + ****************************************************************************/ + +static void imx9_receive(struct imx9_driver_s *priv) +{ + static uint32_t swap_data[2]; + int tail = priv->rxtail; + int swap_d_n; + struct enet_desc_s *rxdesc; + bool received; + + /* Loop while there are received packets to be processed */ + + do + { + rxdesc = &priv->rxdesc[tail]; + received = imx9_rxdesc_full(rxdesc); + if (received) + { + /* Copy the buffer pointer to priv->dev.d_buf. Set amount of data + * in priv->dev.d_len + */ + + DEBUGASSERT(priv->dev.d_buf == NULL); + + if ((rxdesc->status1 & RXDESC_STATUS1_ERRORS) != 0 || + (rxdesc->status2 & RXDESC_STATUS2_ERRORS) != 0) + { + nerr("status1 %x, status2 %x", + rxdesc->status1 & RXDESC_STATUS1_ERRORS, + rxdesc->status2 & RXDESC_STATUS2_ERRORS); + } + + DEBUGASSERT(rxdesc->length > 0 && + ((uintptr_t)rxdesc->data & ENET_ALIGN_MASK) == 0); + + priv->dev.d_len = rxdesc->length; + priv->dev.d_buf = (uint8_t *)(uintptr_t)rxdesc->data; + + /* Invalidate the buffer so that the correct packet will be re-read + * from memory when the packet content is accessed. + */ + + up_invalidate_dcache((uintptr_t)priv->dev.d_buf, + (uintptr_t)priv->dev.d_buf + priv->dev.d_len); + + /* Dispatch (or drop) the newly received packet */ + + imx9_dispatch(priv); + + /* If the dispatch resulted in data that should + * be sent out on the network, the field d_len will set to a + * value > 0. In this case imx9_transmit will just directly use + * the provided buffer to transmit, and swap the rx / tx buffers + */ + + swap_d_n = tail & 1; + swap_data[swap_d_n] = rxdesc->data; + if (priv->dev.d_len > 0) + { + /* And send the packet */ + + imx9_transmit(priv, &swap_data[swap_d_n]); + + /* Assume that the upper levels didn't write to the tx buffer + * beyond the d_len, so the transmit buffer cache is clean. + * If this wouldn't be the case, we'd have to invalidate here! + * up_invalidate_dcache(swap_data[swap_d_n], + * swap_data[swap_d_n] + ALIGNED_BUFSIZE); + */ + } + + /* We are done with the buffers - let's not leave the pointers + * laying around + */ + + priv->dev.d_buf = NULL; + priv->dev.d_len = 0; + + /* RX descriptor size is 32 bytes, but the cache line size is 64. + * This means that we can only free the rx descriptors in pairs. + * If we are the second descriptor of the pair, we update both + */ + + if (swap_d_n == 1) + { + /* First update the second descriptor - RX DMA may not start + * before both are updated + */ + + rxdesc->data = swap_data[1]; + rxdesc->length = 0; + rxdesc->status2 = RXDESC_INT; + rxdesc->bdu = 0x00000000; + rxdesc->status1 = (rxdesc->status1 & RXDESC_W) | RXDESC_E; + + /* Now update the first descriptor of the pair */ + + rxdesc -= 1; + rxdesc->data = swap_data[0]; + rxdesc->length = 0; + rxdesc->status2 = RXDESC_INT; + rxdesc->bdu = 0x00000000; + + /* Make sure both descriptors are fully updated before updating + * the first descriptor's status1; this allows DMA to proceed + * to this descriptor pair. + */ + + ARM64_DMB(); + rxdesc->status1 = RXDESC_E; + ARM64_DSB(); + + up_clean_dcache((uintptr_t)&rxdesc[(-1)], + (uintptr_t)&rxdesc[(-1)] + + 2 * sizeof(rxdesc[0])); + + /* Indicate that we produced empty receive buffers */ + + imx9_enet_putreg32(priv, ENET_RDAR, IMX9_ENET_RDAR_OFFSET); + } + + tail++; + if (tail >= IMX9_ENET_NRXBUFFERS) + { + tail = 0; + } + } + } + while (received); + + /* Update the index to the next empty descriptor */ + + priv->rxtail = tail; +} + +/**************************************************************************** + * Function: imx9_txdone + * + * Description: + * An interrupt was received indicating that the last TX packet(s) is done + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * The network is locked. + * + ****************************************************************************/ + +static void imx9_txdone(struct imx9_driver_s *priv) +{ + DEBUGASSERT(priv->dev.d_len == 0 && priv->dev.d_buf == NULL); + + /* Cancel the timeout watchdog */ + + wd_cancel(&priv->txtimeout); + + /* Update statistics */ + + NETDEV_TXDONE(&priv->dev); + + priv->ints |= RX_INTERRUPTS; + imx9_enet_putreg32(priv, priv->ints, IMX9_ENET_EIMR_OFFSET); + + /* Poll the network for new XMIT data */ + + imx9_dopoll(priv); +} + +/**************************************************************************** + * Function: imx9_enet_interrupt_work + * + * Description: + * Perform interrupt related work from the worker thread + * + * Input Parameters: + * arg - The argument passed when work_queue() was called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static void imx9_enet_interrupt_work(void *arg) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)arg; + uint32_t pending; +#ifdef CONFIG_NET_MCASTGROUP + uint32_t gaurstore; + uint32_t galrstore; +#endif + + /* Process pending Ethernet interrupts */ + + net_lock(); + + /* Get the set of unmasked, pending interrupt. */ + + pending = imx9_enet_getreg32(priv, IMX9_ENET_EIR_OFFSET) & priv->ints; + + /* Clear the pending interrupts */ + + imx9_enet_putreg32(priv, pending, IMX9_ENET_EIR_OFFSET); + + /* Check for errors */ + + if (pending & ERROR_INTERRUPTS) + { + /* An error has occurred, update statistics */ + + NETDEV_ERRORS(&priv->dev); + + nerr("pending %" PRIx32 " ints %" PRIx32 "\n", pending, priv->ints); + } + + if (pending & CRITICAL_ERROR) + { + nerr("Critical error, restarting Ethernet interface\n"); + + /* Bring the Ethernet chip down and back up but with no need to + * reset/renegotiate the phy. + */ + +#ifdef CONFIG_NET_MCASTGROUP + /* Just before we pull the rug lets make sure we retain the + * multicast hash table. + */ + + gaurstore = imx9_enet_getreg32(priv, IMX9_ENET_GAUR_OFFSET); + galrstore = imx9_enet_getreg32(priv, IMX9_ENET_GALR_OFFSET); +#endif + + imx9_ifdown(&priv->dev); + imx9_ifup_action(&priv->dev, false); + +#ifdef CONFIG_NET_MCASTGROUP + /* Now write the multicast table back */ + + imx9_enet_putreg32(priv, gaurstore, IMX9_ENET_GAUR_OFFSET); + imx9_enet_putreg32(priv, galrstore, IMX9_ENET_GALR_OFFSET); +#endif + + /* Then poll the network for new XMIT data */ + + imx9_dopoll(priv); + } + else + { + /* Check for the receipt of a packet */ + + if ((pending & ENET_INT_RXF) != 0) + { + /* A packet has been received, call imx9_receive() to handle the + * packet. + */ + + imx9_receive(priv); + } + + /* Check if a packet transmission has completed */ + + if ((pending & ENET_INT_TXF) != 0) + { + /* Call imx9_txdone to handle the end of transfer */ + + imx9_txdone(priv); + } + } + + net_unlock(); + + /* Re-enable Ethernet interrupts */ + + imx9_enet_putreg32(priv, priv->ints, IMX9_ENET_EIMR_OFFSET); +} + +/**************************************************************************** + * Function: imx9_enet_interrupt + * + * Description: + * Three interrupt sources will vector to this function: + * 1. Ethernet MAC transmit interrupt handler + * 2. Ethernet MAC receive interrupt handler + * 3. + * + * Input Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static int imx9_enet_interrupt(int irq, void *context, void *arg) +{ + register struct imx9_driver_s *priv = (struct imx9_driver_s *)arg; + + /* Mask all the interrupts */ + + imx9_enet_putreg32(priv, 0, IMX9_ENET_EIMR_OFFSET); + + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->irqwork, imx9_enet_interrupt_work, priv, 0); + return OK; +} + +/**************************************************************************** + * Function: imx9_txtimeout_work + * + * Description: + * Perform TX timeout related work from the worker thread + * + * Input Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static void imx9_txtimeout_work(void *arg) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)arg; + + /* Increment statistics and dump debug info */ + + nerr("Resetting interface\n"); + + /* Take the interface down and bring it back up. That is the most + * aggressive hardware reset. + */ + + NETDEV_TXTIMEOUTS(&priv->dev); + imx9_ifdown(&priv->dev); + imx9_ifup_action(&priv->dev, false); + + /* Then poll the network for new XMIT data */ + + net_lock(); + imx9_dopoll(priv); + net_unlock(); +} + +/**************************************************************************** + * Function: imx9_txtimeout_expiry + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. + * + * Input Parameters: + * arg - The argument + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +static void imx9_txtimeout_expiry(wdparm_t arg) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)arg; + + /* Disable further Ethernet interrupts. This will prevent some race + * conditions with interrupt work. + */ + + imx9_enet_putreg32(priv, 0, IMX9_ENET_EIMR_OFFSET); + priv->ints = 0; + + /* Schedule to perform the TX timeout processing on the worker thread, + * canceling any pending interrupt work. + */ + + work_queue(ETHWORK, &priv->irqwork, imx9_txtimeout_work, priv, 0); +} + +/**************************************************************************** + * Function: imx9_ifup_action + * + * Description: + * Internal action routine to bring up the Ethernet interface + * which makes the resetting of the phy (which takes considerable time) + * optional. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * resetphy - Flag indicating if Phy is to be reset. If not then the + * phy configuration is just re-loaded into the ethernet + * interface + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int imx9_ifup_action(struct net_driver_s *dev, bool resetphy) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)dev; + uint8_t *mac = dev->d_mac.ether.ether_addr_octet; + uint32_t ecr; + int ret; + + ninfo("Bringing up: %u.%u.%u.%u\n", + ip4_addr1(dev->d_ipaddr), ip4_addr2(dev->d_ipaddr), + ip4_addr3(dev->d_ipaddr), ip4_addr4(dev->d_ipaddr)); + + /* Initialize ENET buffers */ + + imx9_initbuffers(priv); + + /* Configure the MII interface */ + + imx9_initmii(priv); + + /* Take MAC out of reset */ + + ecr = ENET_ECR_EN1588 | ENET_ECR_DBSWP; + imx9_enet_putreg32(priv, ecr, IMX9_ENET_ECR_OFFSET); + + /* Enable store and forward mode */ + + imx9_enet_putreg32(priv, ENET_TFWR_STRFWD, IMX9_ENET_TFWR_OFFSET); + + /* Set the MAC address */ + + imx9_enet_putreg32(priv, (mac[0] << 24) | (mac[1] << 16) | + (mac[2] << 8) | mac[3], IMX9_ENET_PALR_OFFSET); + imx9_enet_putreg32(priv, (mac[4] << 24) | (mac[5] << 16), + IMX9_ENET_PAUR_OFFSET); + + /* Configure the PHY */ + + ret = imx9_determine_phy(priv); + if (ret < 0) + { + nwarn("Unrecognized PHY\n"); + } + + ret = imx9_initphy(priv, resetphy); + if (ret < 0) + { + nerr("ERROR: Failed to configure the PHY: %d\n", ret); + return ret; + } + + /* Set the RX buffer size */ + + imx9_enet_putreg32(priv, ALIGNED_BUFSIZE, IMX9_ENET_MRBR_OFFSET); + + /* Point to the start of the circular RX buffer descriptor queue */ + + imx9_enet_putreg32(priv, (uint32_t)(uintptr_t)priv->rxdesc, + IMX9_ENET_RDSR_OFFSET); + + /* Point to the start of the circular TX buffer descriptor queue */ + + imx9_enet_putreg32(priv, (uint32_t)(uintptr_t)priv->txdesc, + IMX9_ENET_TDSR_OFFSET); + + /* Mask and clear all ENET interrupts */ + + imx9_enet_putreg32(priv, 0, IMX9_ENET_EIMR_OFFSET); + + imx9_enet_putreg32(priv, 0xffffffff, IMX9_ENET_EIR_OFFSET); + + /* Set 1GBPS if link is set to that */ + + if (priv->s_1000mbps) + { + ecr |= ENET_ECR_SPEED; + } + + /* And enable the MAC */ + + ecr |= ENET_ECR_ETHEREN; + + imx9_enet_putreg32(priv, ecr, IMX9_ENET_ECR_OFFSET); + + /* Enable RX and error interrupts at the controller */ + + priv->ints = RX_INTERRUPTS | ERROR_INTERRUPTS; + imx9_enet_putreg32(priv, priv->ints, IMX9_ENET_EIMR_OFFSET); + + /* Mark the interface "up" and enable interrupts */ + + priv->bifup = true; + up_enable_irq(priv->irq); + + /* Indicate that there have been empty receive buffers produced */ + + imx9_enet_putreg32(priv, ENET_RDAR, IMX9_ENET_RDAR_OFFSET); + + return OK; +} + +/**************************************************************************** + * Function: imx9_ifup + * + * Description: + * NuttX Callback: Bring up the Ethernet interface when an IP address is + * provided + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int imx9_ifup(struct net_driver_s *dev) +{ + /* The externally available ifup action includes resetting the phy */ + + return imx9_ifup_action(dev, true); +} + +/**************************************************************************** + * Function: imx9_ifdown + * + * Description: + * NuttX Callback: Stop the interface. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int imx9_ifdown(struct net_driver_s *dev) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)dev; + + ninfo("Taking down: %u.%u.%u.%u\n", + ip4_addr1(dev->d_ipaddr), ip4_addr2(dev->d_ipaddr), + ip4_addr3(dev->d_ipaddr), ip4_addr4(dev->d_ipaddr)); + + /* Cancel the TX timeout timers */ + + wd_cancel(&priv->txtimeout); + + /* Flush and disable the Ethernet interrupts */ + + up_disable_irq(priv->irq); + + imx9_enet_putreg32(priv, 0, IMX9_ENET_EIMR_OFFSET); + priv->ints = 0; + + /* Put the EMAC in its reset, non-operational state. This should be + * a known configuration that will guarantee the imx9_ifup() always + * successfully brings the interface back up. + */ + + imx9_reset(priv); + + /* Clear any pending interrupts */ + + imx9_enet_putreg32(priv, 0xffffffff, IMX9_ENET_EIR_OFFSET); + + /* Mark the device "down" */ + + priv->bifup = false; + + return OK; +} + +/**************************************************************************** + * Function: imx9_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Input Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ + +static void imx9_txavail_work(void *arg) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)arg; + + /* Ignore the notification if the interface is not yet up */ + + net_lock(); + if (priv->bifup) + { + /* Poll the network for new XMIT data */ + + imx9_dopoll(priv); + } + + net_unlock(); +} + +/**************************************************************************** + * Function: imx9_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int imx9_txavail(struct net_driver_s *dev) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)dev; + + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->pollwork)) + { + /* Schedule to serialize the poll on the worker thread. */ + + work_queue(ETHWORK, &priv->pollwork, imx9_txavail_work, priv, 0); + } + + return OK; +} + +/**************************************************************************** + * Function: imx9_calcethcrc + * + * Description: + * Function to calculate the CRC used by IMX9 to check an Ethernet frame + * + * Input Parameters: + * data - the data to be checked + * length - length of the data + * + * Returned Value: + * crc32 + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NET_MCASTGROUP +static uint32_t imx9_calcethcrc(const uint8_t *data, size_t length) +{ + uint32_t crc = 0xffffffffu; + uint32_t count1 = 0; + uint32_t count2 = 0; + + /* Calculates the CRC-32 polynomial on the multicast group address. */ + + for (count1 = 0; count1 < length; count1++) + { + uint8_t c = data[count1]; + + for (count2 = 0; count2 < 0x08u; count2++) + { + if ((c ^ crc) & 1U) + { + crc >>= 1U; + c >>= 1U; + crc ^= 0xedb88320u; + } + else + { + crc >>= 1U; + c >>= 1U; + } + } + } + + return crc; +} +#endif + +/**************************************************************************** + * Function: imx9_enet_hash_index + * + * Description: + * Function to find the hash index for multicast address filter + * + * Input Parameters: + * mac - The MAC address + * + * Returned Value: + * hash index + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NET_MCASTGROUP +static uint32_t imx9_enet_hash_index(const uint8_t *mac) +{ + uint32_t crc; + uint32_t hashindex; + + ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + + crc = imx9_calcethcrc(mac, 6); + hashindex = (crc >> 26) & 0x3f; + + return hashindex; +} +#endif + +/**************************************************************************** + * Function: imx9_addmac + * + * Description: + * NuttX Callback: Add the specified MAC address to the hardware multicast + * address filtering + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be added + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NET_MCASTGROUP +static int imx9_addmac(struct net_driver_s *dev, const uint8_t *mac) +{ + uint32_t hashindex; + uint32_t temp; + uint32_t registeraddress; + struct imx9_driver_s *priv = (struct imx9_driver_s *)dev; + + hashindex = imx9_enet_hash_index(mac); + + /* Add the MAC address to the hardware multicast routing table */ + + if (hashindex > 31) + { + registeraddress = IMX9_ENET_GAUR_OFFSET; + hashindex -= 32; + } + else + { + registeraddress = IMX9_ENET_GALR_OFFSET; + } + + temp = imx9_enet_getreg32(priv, registeraddress); + temp |= 1 << hashindex; + imx9_enet_putreg32(priv, temp, registeraddress); + + return OK; +} +#endif + +/**************************************************************************** + * Function: imx9_rmmac + * + * Description: + * NuttX Callback: Remove the specified MAC address from the hardware + * multicast address filtering + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be removed + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NET_MCASTGROUP +static int imx9_rmmac(struct net_driver_s *dev, const uint8_t *mac) +{ + uint32_t hashindex; + uint32_t temp; + uint32_t registeraddress; + struct imx9_driver_s *priv = (struct imx9_driver_s *)dev; + + /* Remove the MAC address from the hardware multicast routing table */ + + hashindex = imx9_enet_hash_index(mac); + + if (hashindex > 31) + { + registeraddress = IMX9_ENET_GAUR_OFFSET; + hashindex -= 32; + } + else + { + registeraddress = IMX9_ENET_GALR_OFFSET; + } + + temp = imx9_enet_getreg32(priv, registeraddress); + temp &= ~(1 << hashindex); + imx9_enet_putreg32(priv, temp, registeraddress); + + return OK; +} +#endif + +/**************************************************************************** + * Function: imx9_ioctl + * + * Description: + * PHY ioctl command handler + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * cmd - ioctl command + * arg - Argument accompanying the command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NETDEV_IOCTL +static int imx9_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) +{ +#ifdef CONFIG_NETDEV_PHY_IOCTL + struct imx9_driver_s *priv = (struct imx9_driver_s *)dev; +#endif + int ret; + + switch (cmd) + { +#ifdef CONFIG_NETDEV_PHY_IOCTL +#ifdef CONFIG_ARCH_PHY_INTERRUPT + case SIOCMIINOTIFY: /* Set up for PHY event notifications */ + { + struct mii_ioctl_notify_s *req = + (struct mii_ioctl_notify_s *)((uintptr_t)arg); + + ret = phy_notify_subscribe(dev->d_ifname, req->pid, &req->event); + if (ret == OK) + { + /* Enable PHY link up/down interrupts */ + + ret = imx9_phyintenable(priv); + } + } + break; +#endif + + case SIOCGMIIPHY: /* Get MII PHY address */ + { + struct mii_ioctl_data_s *req = + (struct mii_ioctl_data_s *)((uintptr_t)arg); + req->phy_id = priv->phyaddr; + ret = OK; + } + break; + + case SIOCGMIIREG: /* Get register from MII PHY */ + { + struct mii_ioctl_data_s *req = + (struct mii_ioctl_data_s *)((uintptr_t)arg); + if (priv->cur_phy && priv->cur_phy->clause == 45 && + MII_MSR == req->reg_num) + { + ret = imx9_readmmd(priv, MMD1, MMD1_PMA_STATUS1, + &req->val_out); + } + else + { + ret = imx9_readmii(priv, req->reg_num, &req->val_out); + } + } + break; + + case SIOCSMIIREG: /* Set register in MII PHY */ + { + struct mii_ioctl_data_s *req = + (struct mii_ioctl_data_s *)((uintptr_t)arg); + ret = imx9_writemii(priv, req->reg_num, req->val_in); + } + break; +#endif /* CONFIG_NETDEV_PHY_IOCTL */ + + default: + ret = -ENOTTY; + break; + } + + return ret; +} +#endif /* CONFIG_NETDEV_IOCTL */ + +/**************************************************************************** + * Function: imx9_phyintenable + * + * Description: + * Enable link up/down PHY interrupts. The interrupt protocol is like this: + * + * - Interrupt status is cleared when the interrupt is enabled. + * - Interrupt occurs. Interrupt is disabled (at the processor level) when + * is received. + * - Interrupt status is cleared when the interrupt is re-enabled. + * + * Input Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * OK on success; Negated errno (-ETIMEDOUT) on failure. + * + ****************************************************************************/ + +#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) +static int imx9_phyintenable(struct imx9_driver_s *priv) +{ + uint16_t phyval; + int ret; + uint16_t mask; + uint8_t rreg; + uint8_t wreg; + + if (imx9_phy_is(priv, MII_YT8512_NAME)) + { + mask = MII_YT8512_IMR_LD_EN | MII_YT8512_IMR_LU_EN; + rreg = MII_YT8512_ISR; + wreg = MII_YT8512_IMR; + } + else if (imx9_phy_is(priv, MII_KSZ8051_NAME) || + imx9_phy_is(priv, MII_KSZ8061_NAME) || + imx9_phy_is(priv, MII_KSZ8081_NAME) || + imx9_phy_is(priv, MII_DP83825I_NAME)) + { + mask = MII_KSZ80X1_INT_LDEN | MII_KSZ80X1_INT_LUEN; + rreg = MII_KSZ8081_INT; + wreg = rreg; + } + else + { + return -ENOSYS; + } + + /* Read the interrupt status register in order to clear any pending + * interrupts + */ + + ret = imx9_readmii(priv, rreg, &phyval); + if (ret == OK) + { + /* Enable link up/down interrupts */ + + ret = imx9_writemii(priv, wreg, mask); + } + + return ret; +} +#endif + +/**************************************************************************** + * Function: imx9_initmii + * + * Description: + * Configure the MII interface + * + * Input Parameters: + * priv - Reference to the private ENET driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void imx9_initmii(struct imx9_driver_s *priv) +{ + /* Speed is based on the peripheral (bus) clock; hold time is 2 module + * clock. This hold time value may need to be increased on some platforms + */ + + imx9_enet_putreg32(priv, ENET_MSCR_HOLDTIME_2CYCLES | + IMX9_MII_SPEED << ENET_MSCR_MII_SPEED_SHIFT, + IMX9_ENET_MSCR_OFFSET); +} + +/**************************************************************************** + * Function: imx9_writemii + * + * Description: + * Write a 16-bit value to a PHY register. + * + * Input Parameters: + * priv - Reference to the private ENET driver state structure + * phyaddr - The PHY address + * regaddr - The PHY register address + * data - The data to write to the PHY register + * + * Returned Value: + * Zero on success, a negated errno value on failure. + * + ****************************************************************************/ + +static int imx9_writemii(struct imx9_driver_s *priv, + uint8_t regaddr, uint16_t data) +{ + int timeout; + + /* Clear the MII interrupt bit */ + + imx9_enet_putreg32(priv, ENET_INT_MII, IMX9_ENET_EIR_OFFSET); + + /* Initiate the MII Management write */ + + imx9_enet_putreg32(priv, data | + 2 << ENET_MMFR_TA_SHIFT | + (uint32_t)regaddr << ENET_MMFR_RA_SHIFT | + (uint32_t)priv->phyaddr << ENET_MMFR_PA_SHIFT | + ENET_MMFR_OP_WRMII | + 1 << ENET_MMFR_ST_SHIFT, + IMX9_ENET_MMFR_OFFSET); + + /* Wait for the transfer to complete */ + + for (timeout = 0; timeout < MII_MAXPOLLS; timeout++) + { + if ((imx9_enet_getreg32(priv, IMX9_ENET_EIR_OFFSET) & + ENET_INT_MII) != 0) + { + break; + } + } + + /* Check for a timeout */ + + if (timeout == MII_MAXPOLLS) + { + return -ETIMEDOUT; + } + + /* Clear the MII interrupt bit */ + + imx9_enet_putreg32(priv, ENET_INT_MII, IMX9_ENET_EIR_OFFSET); + return OK; +} + +/**************************************************************************** + * Function: imx9_reademii + * + * Description: + * Read a 16-bit value from a PHY register. + * + * Input Parameters: + * priv - Reference to the private ENET driver state structure + * regaddr - The PHY register address + * data - A pointer to the location to return the data + * + * Returned Value: + * Zero on success, a negated errno value on failure. + * + ****************************************************************************/ + +static int imx9_readmii(struct imx9_driver_s *priv, + uint8_t regaddr, uint16_t *data) +{ + int timeout; + + /* Clear the MII interrupt bit */ + + imx9_enet_putreg32(priv, ENET_INT_MII, IMX9_ENET_EIR_OFFSET); + + /* Initiate the MII Management read */ + + imx9_enet_putreg32(priv, 2 << ENET_MMFR_TA_SHIFT | + (uint32_t)regaddr << ENET_MMFR_RA_SHIFT | + (uint32_t)priv->phyaddr << ENET_MMFR_PA_SHIFT | + ENET_MMFR_OP_RDMII | + 1 << ENET_MMFR_ST_SHIFT, + IMX9_ENET_MMFR_OFFSET); + + /* Wait for the transfer to complete */ + + for (timeout = 0; timeout < MII_MAXPOLLS; timeout++) + { + if ((imx9_enet_getreg32(priv, IMX9_ENET_EIR_OFFSET) & + ENET_INT_MII) != 0) + { + break; + } + } + + /* Check for a timeout */ + + if (timeout >= MII_MAXPOLLS) + { + nerr("ERROR: Timed out waiting for transfer to complete\n"); + return -ETIMEDOUT; + } + + /* Clear the MII interrupt bit */ + + imx9_enet_putreg32(priv, ENET_INT_MII, IMX9_ENET_EIR_OFFSET); + + /* And return the MII data */ + + *data = (uint16_t)(imx9_enet_getreg32(priv, IMX9_ENET_MMFR_OFFSET) & + ENET_MMFR_DATA_MASK); + return OK; +} + +/**************************************************************************** + * Function: imx9_read_phy_status + * + * Description: + * Read the phy status from the current phy + * + * Input Parameters: + * priv - Reference to the private ENET driver state structure + * + * Returned Value: + * 0 on success, -1 on any error + * + ****************************************************************************/ + +int imx9_read_phy_status(struct imx9_driver_s *priv) +{ + int ret; + int retries; + uint16_t page = 0; + uint16_t prev_page; + uint16_t page_reg; + uint16_t mask; + uint16_t status; + + if (priv->cur_phy == NULL) + { + /* We don't support guessing the link speed based ou our and link + * partner's capabilities. For now, user must manually set the + * speed and duplex if the phy is unknown + */ + + nerr("Unknown PHY, can't read link speed\n"); + return ERROR; + } + + /* Special handling for rtl8211f, which needs to chage page */ + + if (imx9_phy_is(priv, GMII_RTL8211F_NAME)) + { + page_reg = GMII_RTL8211F_PAGSR; + page = 0xa43; + } + + if (page) + { + /* Get current page */ + + ret = imx9_readmii(priv, page_reg, &prev_page); + + /* Set page */ + + if (ret >= 0) + { + ninfo("Changing PHY page from 0x%x to 0x%x\n", prev_page, page); + ret = imx9_writemii(priv, page_reg, page); + if (ret < 0) + { + return ERROR; + } + } + } + + retries = 0; + do + { + status = 0xffff; + ret = imx9_readmii(priv, priv->cur_phy->status, &status); + } + while ((ret < 0 || status == 0xffff) && ++retries < 3); + + if (status != 0xffff) + { + ninfo("%s: PHY status %x: %04x\n", priv->cur_phy->name, + priv->cur_phy->status, status); + + /* Set the current link information */ + + mask = priv->cur_phy->speed_mask; + + priv->full_duplex = (status & priv->cur_phy->duplex) != 0; + priv->s_10mbps = (status & mask) == priv->cur_phy->mbps10; + priv->s_100mbps = (status & mask) == priv->cur_phy->mbps100; + priv->s_1000mbps = (status & mask) == priv->cur_phy->mbps1000; + } + + if (page) + { + /* Restore original page */ + + ninfo("Restoring PHY page to 0x%x\n", prev_page); + imx9_writemii(priv, page_reg, prev_page); + } + + return OK; +} + +/**************************************************************************** + * Function: imx9_determine_phy + * + * Description: + * Uses the board.h supplied PHY list to determine which PHY + * is populated on this board. + * + * Input Parameters: + * priv - Reference to the private ENET driver state structure + * + * Returned Value: + * Zero on success, a -ENOENT errno value on failure. + * + ****************************************************************************/ + +static int imx9_determine_phy(struct imx9_driver_s *priv) +{ + int i; + uint16_t phydata = 0xffff; + uint8_t last_phyaddr = 0; + int retries; + int ret; + + for (i = 0; i < priv->n_phys; i++) + { + priv->phyaddr = (uint8_t)priv->phy_list[i].address_lo; + last_phyaddr = priv->phy_list[i].address_high == 0xffff ? + priv->phyaddr : + (uint8_t)priv->phy_list[i].address_high; + + for (; priv->phyaddr <= last_phyaddr; priv->phyaddr++) + { + retries = 0; + do + { + nxsig_usleep(100); + phydata = 0xffff; + ret = imx9_readmii(priv, MII_PHYID1, &phydata); + ninfo("phy %s addr %d received PHYID1 %x\n", + priv->phy_list[i].name, priv->phyaddr, + phydata); + } + while ((ret < 0 || phydata == 0xffff) && ++retries < 3); + + if (retries <= 3 && ret == 0 && + phydata == priv->phy_list[i].id1) + { + do + { + nxsig_usleep(100); + phydata = 0xffff; + ret = imx9_readmii(priv, MII_PHYID2, &phydata); + ninfo("phy %s addr %d received PHYID2 %x\n", + priv->phy_list[i].name, priv->phyaddr, + phydata); + } + while ((ret < 0 || phydata == 0xffff) && ++retries < 3); + if (retries <= 3 && ret == 0 && + (phydata & 0xfff0) == + (priv->phy_list[i].id2 & 0xfff0)) + { + priv->cur_phy = & priv->phy_list[i]; + ninfo("Found phy %s addr %d\n", + priv->cur_phy->name, priv->phyaddr); + return OK; + } + } + } + } + + nerr("No PHY found\n"); + + priv->cur_phy = NULL; + return -ENOENT; +} + +/**************************************************************************** + * Function: imx9_phy_is + * + * Description: + * Compares the name with the current selected PHY's name + * + * Input Parameters: + * priv - Reference to the private ENET driver state structure + * name - a pointer to comapre to. + * + * Returned Value: + * 1 on match, a 0 on no match. + * + ****************************************************************************/ + +static int imx9_phy_is(struct imx9_driver_s *priv, const char *name) +{ + return priv->cur_phy && strcmp(priv->cur_phy->name, name) == 0; +} + +#if 0 +/**************************************************************************** + * Function: imx9_writemmd + * + * Description: + * Write a 16-bit value to a the selected MMD PHY register. + * + * Input Parameters: + * priv - Reference to the private ENET driver state structure + * mmd - The Selected MMD Space + * regaddr - The PHY register address + * data - The data to write to the PHY register + * + * Returned Value: + * Zero on success, a negated errno value on failure. + * + ****************************************************************************/ + +static int imx9_writemmd(struct imx9_driver_s *priv, + uint8_t mmd, uint16_t regaddr, uint16_t data) +{ + int timeout; + + /* Clear the MII interrupt bit */ + + imx9_enet_putreg32(priv, ENET_INT_MII, IMX9_ENET_EIR_OFFSET); + + /* Initiate the MMD Management write - Address Phase */ + + imx9_enet_putreg32(priv, + 0 << ENET_MMFR_ST_SHIFT | + ENET_MMFR_OP_WRNOTMII | + (uint32_t)mmd << ENET_MMFR_RA_SHIFT | + (uint32_t)priv->phyaddr << ENET_MMFR_PA_SHIFT | + 2 << ENET_MMFR_TA_SHIFT | + regaddr, + IMX9_ENET_MMFR_OFFSET); + + /* Wait for the transfer to complete */ + + for (timeout = 0; timeout < MII_MAXPOLLS; timeout++) + { + if ((imx9_enet_getreg32(priv, IMX9_ENET_EIR_OFFSET) & + ENET_INT_MII) != 0) + { + break; + } + } + + imx9_enet_putreg32(priv, ENET_INT_MII, IMX9_ENET_EIR_OFFSET); + + /* Check for a timeout */ + + if (timeout == MII_MAXPOLLS) + { + return -ETIMEDOUT; + } + + /* Initiate the MMD Management write - Data Phase */ + + imx9_enet_putreg32(priv, + 0 << ENET_MMFR_ST_SHIFT | + ENET_MMFR_OP_WRMII | + (uint32_t)mmd << ENET_MMFR_RA_SHIFT | + (uint32_t)priv->phyaddr << ENET_MMFR_PA_SHIFT | + 2 << ENET_MMFR_TA_SHIFT | + data, + IMX9_ENET_MMFR_OFFSET); + + /* Wait for the transfer to complete */ + + for (timeout = 0; timeout < MII_MAXPOLLS; timeout++) + { + if ((imx9_enet_getreg32(priv, IMX9_ENET_EIR_OFFSET) & + ENET_INT_MII) != 0) + { + break; + } + } + + /* Clear the MII interrupt bit */ + + imx9_enet_putreg32(priv, ENET_INT_MII, IMX9_ENET_EIR_OFFSET); + + /* Check for a timeout */ + + if (timeout == MII_MAXPOLLS) + { + return -ETIMEDOUT; + } + + return OK; +} +#endif + +/**************************************************************************** + * Function: imx9_reademmd + * + * Description: + * Read a 16-bit value from a PHY register. + * + * Input Parameters: + * priv - Reference to the private ENET driver state structure + * mmd - The Selected MMD Space + * regaddr - The PHY register address + * data - A pointer to the location to return the data + * + * Returned Value: + * Zero on success, a negated errno value on failure. + * + ****************************************************************************/ + +static int imx9_readmmd(struct imx9_driver_s *priv, + uint8_t mmd, uint16_t regaddr, uint16_t *data) +{ + int timeout; + + /* Clear the MII interrupt bit */ + + imx9_enet_putreg32(priv, ENET_INT_MII, IMX9_ENET_EIR_OFFSET); + + /* Initiate the MMD Management read - Address Phase */ + + imx9_enet_putreg32(priv, + 0 << ENET_MMFR_ST_SHIFT | + ENET_MMFR_OP_WRNOTMII | + (uint32_t)mmd << ENET_MMFR_RA_SHIFT | + (uint32_t)priv->phyaddr << ENET_MMFR_PA_SHIFT | + 2 << ENET_MMFR_TA_SHIFT | + regaddr, + IMX9_ENET_MMFR_OFFSET); + + /* Wait for the transfer to complete */ + + for (timeout = 0; timeout < MII_MAXPOLLS; timeout++) + { + if ((imx9_enet_getreg32(priv, IMX9_ENET_EIR_OFFSET) & + ENET_INT_MII) != 0) + { + break; + } + } + + /* Clear the MII interrupt bit */ + + imx9_enet_putreg32(priv, ENET_INT_MII, IMX9_ENET_EIR_OFFSET); + + /* Check for a timeout */ + + if (timeout >= MII_MAXPOLLS) + { + nerr("ERROR: Timed out waiting for transfer to complete\n"); + return -ETIMEDOUT; + } + + /* Initiate the MMD Management read - Data Phase */ + + imx9_enet_putreg32(priv, + 0 << ENET_MMFR_ST_SHIFT | + ENET_MMFR_OP_RDNOTMII | + (uint32_t)mmd << ENET_MMFR_RA_SHIFT | + (uint32_t)priv->phyaddr << ENET_MMFR_PA_SHIFT | + 2 << ENET_MMFR_TA_SHIFT, + IMX9_ENET_MMFR_OFFSET); + + /* Wait for the transfer to complete */ + + for (timeout = 0; timeout < MII_MAXPOLLS; timeout++) + { + if ((imx9_enet_getreg32(priv, IMX9_ENET_EIR_OFFSET) & + ENET_INT_MII) != 0) + { + break; + } + } + + /* Clear the MII interrupt bit */ + + imx9_enet_putreg32(priv, ENET_INT_MII, IMX9_ENET_EIR_OFFSET); + + /* Check for a timeout */ + + if (timeout == MII_MAXPOLLS) + { + return -ETIMEDOUT; + } + + /* And return the MII data */ + + *data = (uint16_t)(imx9_enet_getreg32(priv, IMX9_ENET_MMFR_OFFSET) & + ENET_MMFR_DATA_MASK); + return OK; +} + +int imx9_reset_phy(struct imx9_driver_s *priv) +{ + int timeout; + int ret; + int result; + uint16_t mcr; + + /* Reset the PHY */ + + ret = imx9_writemii(priv, MII_MCR, MII_MCR_RESET); + + if (ret < 0) + { + nerr("ERROR: mpfs_phywrite failed: %d\n", ret); + } + + /* Wait for the PHY reset to complete */ + + ret = -ETIMEDOUT; + for (timeout = 0; timeout < PHY_RESET_WAIT_COUNT; timeout++) + { + nxsig_usleep(100); + result = imx9_readmii(priv, MII_MCR, &mcr); + if (result < 0) + { + nerr("ERROR: Failed to read the MCR register: %d\n", ret); + ret = result; + } + else if ((mcr & MII_MCR_RESET) == 0) + { + ninfo("MII reset complete: %x\n", mcr); + ret = OK; + break; + } + else + { + nerr("MCR data %x\n", mcr); + } + } + + return ret; +} + +/**************************************************************************** + * Function: imx9_phy_set_speed + * + * Description: + * Set or start to autonegotiate the link speed + * + * Input Parameters: + * priv - Reference to the private ENET driver state structure + * autonegotiate - true: autonegotiate with default advertisement + * false: autonegotiate, but disable other speeds + * Returned Value: + * Zero (OK) returned on success; a negated errno value is returned on any + * failure; + * + * Assumptions: + * + ****************************************************************************/ + +static int imx9_phy_set_speed(struct imx9_driver_s *priv, bool autonegotiate) +{ + uint16_t advertise; + uint16_t mcr; + uint16_t force_mcr; + uint16_t btcr; + int ret; + + /* Read initial MCR and take link down */ + + ret = imx9_readmii(priv, MII_MCR, &mcr); + + if (ret < 0) + { + nerr("ERROR: Failed to read MCR register: %d\n", ret); + return ret; + } + + ret = imx9_writemii(priv, MII_MCR, mcr | MII_MCR_PDOWN); + + /* If we are trying to manually set the speed, disable advertisement of the + * other ones. In case we want to force the speed setting on the PHY, + * set the speed in MCR and disable autonegotiation completely. + */ + + force_mcr = mcr; + if (!autonegotiate) + { + /* Read the Auto_negotiation Advertisement Register defaults */ + + ret = imx9_readmii(priv, MII_ADVERTISE, &advertise); + + if (ret < 0) + { + nerr("ERROR: Failed to read ADVERTISE register: %d\n", ret); + return ret; + } + + if (priv->phy_type == PHY_RGMII) + { + ret = imx9_readmii(priv, GMII_1000BTCR, &btcr); + if (ret < 0) + { + nerr("ERROR: Failed to read GMII_1000BTCR register\n"); + return ret; + } + } + + if (priv->full_duplex) + { + advertise &= ~(MII_ADVERTISE_1000XHALF | + MII_ADVERTISE_100BASETXHALF | + MII_ADVERTISE_10BASETXHALF); + btcr &= ~GMII_1000BTCR_1000BASETHALF; + force_mcr |= MII_MCR_FULLDPLX; + } + else + { + advertise &= ~(MII_ADVERTISE_1000XFULL | + MII_ADVERTISE_100BASETXFULL | + MII_ADVERTISE_10BASETXFULL); + btcr &= ~GMII_1000BTCR_1000BASETFULL; + force_mcr &= ~MII_MCR_FULLDPLX; + } + + if (priv->s_10mbps) + { + advertise &= ~(MII_ADVERTISE_100BASETXFULL | + MII_ADVERTISE_100BASETXHALF | + MII_ADVERTISE_1000XFULL | + MII_ADVERTISE_1000XHALF); + btcr &= ~(GMII_1000BTCR_1000BASETHALF | + GMII_1000BTCR_1000BASETFULL); + force_mcr &= ~(MII_MCR_SPEED100 | GMII_MCR_SPEED1000); + } + + if (priv->s_100mbps) + { + advertise &= ~(MII_ADVERTISE_10BASETXFULL | + MII_ADVERTISE_10BASETXHALF | + MII_ADVERTISE_1000XFULL | + MII_ADVERTISE_1000XHALF); + btcr &= ~(GMII_1000BTCR_1000BASETHALF | + GMII_1000BTCR_1000BASETFULL); + force_mcr &= ~GMII_MCR_SPEED1000; + force_mcr |= MII_MCR_SPEED100; + } + + if (priv->s_1000mbps) + { + advertise &= ~(MII_ADVERTISE_10BASETXFULL | + MII_ADVERTISE_10BASETXHALF | + MII_ADVERTISE_100BASETXFULL | + MII_ADVERTISE_100BASETXHALF); + force_mcr &= ~MII_MCR_SPEED100; + force_mcr |= GMII_MCR_SPEED1000; + } + + ret = imx9_writemii(priv, MII_ADVERTISE, advertise); + + if (ret < 0) + { + nerr("ERROR: Failed to write ADVERTISE register\n"); + return ret; + } + + if (priv->phy_type == PHY_RGMII) + { + ret = imx9_writemii(priv, GMII_1000BTCR, btcr); + if (ret < 0) + { + nerr("ERROR: Failed to write GMII_1000BTCR register\n"); + return ret; + } + } + } + + /* Enable autonegotiation and take link back up */ + + if (!priv->force_speed) + { + mcr |= (MII_MCR_ANENABLE | MII_MCR_ANRESTART); + } + else + { + mcr = force_mcr & (~(MII_MCR_ANENABLE | MII_MCR_ANRESTART)); + } + + ret = imx9_writemii(priv, MII_MCR, mcr); + if (ret < 0) + { + nerr("ERROR: Failed to write MCR register: %d\n", ret); + return ret; + } + + return OK; +} + +/**************************************************************************** + * Function: imx9_phy_wait_autoneg_complete + * + * Description: + * Wait for autonegotiation to complete + * + * Input Parameters: + * priv - Reference to the private ENET driver state structure + * + * Returned Value: + * Zero (OK) returned on success; a negated errno value is returned on any + * failure; + * + * Assumptions: + * + ****************************************************************************/ + +static int imx9_phy_wait_autoneg_complete(struct imx9_driver_s *priv) +{ + int ret; + uint16_t msr; + int timeout; + + /* Wait for autonegotiation to complete */ + + for (timeout = 0; timeout < LINK_NLOOPS; timeout++) + { + ret = imx9_readmii(priv, MII_MSR, &msr); + if (ret < 0) + { + nerr("ERROR: Failed to read MSR register: %d\n", ret); + return ret; + } + + /* Check for completion of autonegotiation */ + + if ((msr & MII_MSR_ANEGCOMPLETE) != 0) + { + /* Yes break out of the loop */ + + ninfo("Autonegotiate complete, MSR %x\n", msr); + break; + } + + nxsig_usleep(LINK_WAITUS); + } + + if (timeout == LINK_NLOOPS) + { + ninfo("Autonegotiate failed, MSR %x\n", msr); + return -ETIMEDOUT; + } + + return imx9_read_phy_status(priv); +} + +/**************************************************************************** + * Function: imx9_initphy + * + * Description: + * Configure the PHY + * + * Input Parameters: + * priv - Reference to the private ENET driver state structure + * renogphy - Flag indicating if to perform negotiation of the link + * + * Returned Value: + * Zero (OK) returned on success; a negated errno value is returned on any + * failure; + * + * Assumptions: + * + ****************************************************************************/ + +static inline int imx9_initphy(struct imx9_driver_s *priv, bool renogphy) +{ + uint32_t rcr; + uint32_t tcr; + uint32_t racc; + uint16_t phydata; + int retries; + int ret; + const char *phy_name = priv->cur_phy ? priv->cur_phy->name : "Unknown"; + + if (renogphy) + { + /* Loop until we successfully communicate + * with the PHY. This is 'standard stuff' that should work for any PHY + * - we are not communicating with it's 'special' registers + * at this point. + */ + + ninfo("%s: Try phyaddr: %u\n", phy_name, priv->phyaddr); + + /* Try to read PHYID1 few times using this address */ + + retries = 0; + do + { + nxsig_usleep(LINK_WAITUS); + + ninfo("%s: Read PHYID1, retries=%d\n", phy_name, retries + 1); + + phydata = 0xffff; + ret = imx9_readmii(priv, MII_PHYID1, &phydata); + } + while ((ret < 0 || phydata == 0xffff) && ++retries < 3); + + if (retries >= 3) + { + nerr("ERROR: Failed to read %s PHYID1 at address %d\n", + phy_name, priv->phyaddr); + return -ENOENT; + } + + ninfo("%s: Using PHY address %u\n", phy_name, priv->phyaddr); + + /* Verify PHYID1. Compare OUI bits 3-18 */ + + ninfo("%s: PHYID1: %04x\n", phy_name, phydata); + if (priv->cur_phy && phydata != priv->cur_phy->id1) + { + nerr("ERROR: PHYID1=%04x incorrect for %s. Expected %04x\n", + phydata, phy_name, priv->cur_phy->id1); + return -ENXIO; + } + + /* Read PHYID2 */ + + ret = imx9_readmii(priv, MII_PHYID2, &phydata); + if (ret < 0) + { + nerr("ERROR: Failed to read %s PHYID2: %d\n", phy_name, ret); + return ret; + } + + ninfo("%s: PHYID2: %04x\n", phy_name, phydata); + + /* Verify PHYID2: Compare OUI bits 19-24 and the 6-bit model number + * (ignoring the 4-bit revision number). + */ + + if (priv->cur_phy && + (phydata & 0xfff0) != (priv->cur_phy->id2 & 0xfff0)) + { + nerr("ERROR: PHYID2=%04x incorrect for %s. Expected %04x\n", + (phydata & 0xfff0), phy_name, + (priv->cur_phy->id2 & 0xfff0)); + return -ENXIO; + } + + if (imx9_phy_is(priv, MII_LAN8720_NAME) || + imx9_phy_is(priv, MII_LAN8742A_NAME)) + { + /* Make sure that PHY comes up in correct mode when it's reset */ + + imx9_writemii(priv, MII_LAN8720_MODES, + MII_LAN8720_MODES_RESV | MII_LAN8720_MODES_ALL | + MII_LAN8720_MODES_PHYAD(priv->phyaddr)); + } + + ret = imx9_reset_phy(priv); + if (ret < 0) + { + nerr("ERROR: PHY reset failed: %d\n", ret); + return ret; + } + + ret = imx9_phy_set_speed(priv, priv->autoneg); + + if (ret < 0) + { + nerr("ERROR: PHY setting speed failed: %d\n", ret); + return ret; + } + + /* If this is an unknown phy, we can't read the current link speed. In + * that case, just set the default speed and duplex settings. + */ + + if (!priv->cur_phy || !priv->autoneg) + { + nwarn("Can't read PHY status, using default speed and duplex\n"); + imx9_phy_set_speed(priv, false); + } + else + { + ret = imx9_phy_wait_autoneg_complete(priv); + if (ret < 0) + { + return ret; + } + } + } + + /* Set up the transmit and receive control registers based on the + * configuration and the auto negotiation results. + */ + + rcr = (ENET_RCR_CRCFWD | ((CONFIG_NET_ETH_PKTSIZE + CONFIG_NET_GUARDSIZE) + << ENET_RCR_MAX_FL_SHIFT) | + ENET_RCR_FCE | ENET_RCR_MII_MODE); + + if (priv->phy_type == PHY_RGMII) + { + rcr |= ENET_RCR_RGMII_EN; + } + else + { + rcr |= ENET_RCR_RMII_MODE; + } + + if (priv->promiscuous) + { + rcr |= ENET_RCR_PROM; + } + + tcr = 0; + + imx9_enet_putreg32(priv, tcr, IMX9_ENET_TCR_OFFSET); + + /* Enable Discard Of Frames With MAC Layer Errors. + * Enable Discard Of Frames With Wrong Protocol Checksum. + * Bit 1: Enable discard of frames with wrong IPv4 header checksum. + */ + + racc = ENET_RACC_PRODIS | ENET_RACC_LINEDIS | ENET_RACC_IPDIS; + imx9_enet_putreg32(priv, racc, IMX9_ENET_RACC_OFFSET); + + /* Setup half or full duplex */ + + if (priv->full_duplex) + { + /* Full duplex */ + + ninfo("%s: Full duplex\n", phy_name); + tcr |= ENET_TCR_FDEN; + } + else + { + /* Half duplex */ + + ninfo("%s: Half duplex\n", phy_name); + rcr |= ENET_RCR_DRT; + } + + if (priv->s_10mbps) + { + /* 10 Mbps */ + + ninfo("%s: 10 Base-T\n", phy_name); + rcr |= ENET_RCR_RMII_10T; + } + else if (priv->s_100mbps) + { + /* 100 Mbps */ + + ninfo("%s: 100 Base-T\n", phy_name); + } + else if (priv->s_1000mbps) + { + /* 1000 Mbps */ + + ninfo("%s: 1000 Base-T\n", phy_name); + } + else + { + /* This might happen if Autonegotiation did not complete(?) */ + + nerr("ERROR: No 10-, 100-, or 1000-BaseT reported: PHY STATUS=%04x\n", + phydata); + return -EIO; + } + + imx9_enet_putreg32(priv, rcr, IMX9_ENET_RCR_OFFSET); + imx9_enet_putreg32(priv, tcr, IMX9_ENET_TCR_OFFSET); + return OK; +} + +/**************************************************************************** + * Function: imx9_initbuffers + * + * Description: + * Initialize ENET buffers and descriptors + * + * Input Parameters: + * priv - Reference to the private ENET driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void imx9_initbuffers(struct imx9_driver_s *priv) +{ + uintptr_t addr; + int i; + + /* Get the beginning of the first aligned buffer */ + + addr = priv->buffer_pool; + + /* Then fill in the TX descriptors */ + + memset(priv->txdesc, 0, IMX9_ENET_NTXBUFFERS * sizeof(priv->txdesc[0])); + + for (i = 0; i < IMX9_ENET_NTXBUFFERS; i++) + { + priv->txdesc[i].d1.data = addr; + priv->txdesc[i].d1.bdu = TXDESC_BDU; + + priv->txdesc[i].d2.bdu = TXDESC_BDU; + addr += ALIGNED_BUFSIZE; + } + + /* Then fill in the RX descriptors */ + + memset(priv->rxdesc, 0, IMX9_ENET_NRXBUFFERS * sizeof(priv->rxdesc[0])); + + for (i = 0; i < IMX9_ENET_NRXBUFFERS; i++) + { + priv->rxdesc[i].status1 = RXDESC_E; + priv->rxdesc[i].data = addr; + priv->rxdesc[i].status2 = RXDESC_INT; + addr += ALIGNED_BUFSIZE; + } + + /* Set the wrap bit in the last descriptors to form a ring */ + + priv->txdesc[IMX9_ENET_NTXBUFFERS - 1].d2.status1 |= TXDESC_W; + priv->rxdesc[IMX9_ENET_NRXBUFFERS - 1].status1 |= RXDESC_W; + + ARM64_DSB(); + + up_clean_dcache((uintptr_t)priv->txdesc, + (uintptr_t)priv->txdesc + + IMX9_ENET_NTXBUFFERS * sizeof(priv->txdesc[0])); + up_clean_dcache((uintptr_t)priv->rxdesc, + (uintptr_t)priv->rxdesc + + IMX9_ENET_NRXBUFFERS * sizeof(priv->rxdesc[0])); + + /* We start with RX descriptor 0 and with no TX descriptors in use */ + + priv->txhead = 0; + priv->rxtail = 0; +} + +/**************************************************************************** + * Function: imx9_reset + * + * Description: + * Put the EMAC in the non-operational, reset state + * + * Input Parameters: + * priv - Reference to the private ENET driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void imx9_reset(struct imx9_driver_s *priv) +{ + /* Set the reset bit and wait for the enable to clear */ + + imx9_enet_putreg32(priv, ENET_ECR_RESET, IMX9_ENET_ECR_OFFSET); + + while (imx9_enet_getreg32(priv, IMX9_ENET_ECR_OFFSET) & ENET_ECR_ETHEREN) + { + asm volatile ("nop"); + } +} + +/**************************************************************************** + * Function: imx9_enet_mux_io + * + * Description: + * Mux all the IO pins + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void imx9_enet_mux_io(void) +{ +#ifdef CONFIG_IMX9_ENET1 + imx9_iomux_configure(MUX_ENET1_MDIO); + imx9_iomux_configure(MUX_ENET1_MDC); + + imx9_iomux_configure(MUX_ENET1_RX_DATA00); + imx9_iomux_configure(MUX_ENET1_RX_DATA01); + + imx9_iomux_configure(MUX_ENET1_TX_DATA00); + imx9_iomux_configure(MUX_ENET1_TX_DATA01); + +# if defined(CONFIG_IMX9_ENET1_RGMII) + imx9_iomux_configure(MUX_ENET1_RX_DATA02); + imx9_iomux_configure(MUX_ENET1_RX_DATA03); + imx9_iomux_configure(MUX_ENET1_TX_DATA02); + imx9_iomux_configure(MUX_ENET1_TX_DATA03); + imx9_iomux_configure(MUX_ENET1_RXC); + imx9_iomux_configure(MUX_ENET1_TX_CTL); + imx9_iomux_configure(MUX_ENET1_RX_CTL); +# else /* RMII */ + imx9_iomux_configure(MUX_ENET1_TX_EN); + imx9_iomux_configure(MUX_ENET1_REF_CLK); + imx9_iomux_configure(MUX_ENET1_CRS_DV); +# endif + +# ifdef MUX_ENET1_RX_ER + imx9_iomux_configure(MUX_ENET1_RX_ER); +# endif +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: imx9_netinitialize + * + * Description: + * Initialize the Ethernet controller and driver + * + * Input Parameters: + * intf - In the case where there are multiple EMACs, this value + * identifies which EMAC is to be initialized. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +int imx9_netinitialize(int intf) +{ + struct imx9_driver_s *priv; + uint32_t uidl; + uint32_t uidml; + uint8_t *mac; + int ret; + + /* Get the interface structure associated with this interface number. */ + + priv = &g_enet[intf]; + + /* Disable the ENET clock */ + + imx9_ccm_gate_on(priv->clk_gate, false); + + /* Enet ref to 125 MHz */ + + imx9_ccm_configure_root_clock(CCM_CR_ENETREF, SYS_PLL1PFD0DIV2, 2); + + /* Enet timer 1 to 125MHz */ + + imx9_ccm_configure_root_clock(CCM_CR_ENETTIMER1, SYS_PLL1PFD0DIV2, 2); + + /* Enet ref clock to 25 MHz */ + + imx9_ccm_configure_root_clock(CCM_CR_ENETREFPHY, SYS_PLL1PFD0DIV2, 20); + + /* Enable the ENET clock */ + + imx9_ccm_gate_on(priv->clk_gate, true); + + /* Attach the Ethernet interrupt handler */ + + if (irq_attach(priv->irq, imx9_enet_interrupt, priv)) + { + /* We could not attach the ISR to the interrupt */ + + nerr("ERROR: Failed to attach EMACTX IRQ\n"); + return -EAGAIN; + } + + /* TODO: 1588 features */ + + /* Attach the Ethernet MAC IEEE 1588 timer interrupt handler */ + +#if 0 + if (irq_attach(IMX9_IRQ_ENET_1588, imx9_enet_interrupt, priv)) + { + /* We could not attach the ISR to the interrupt */ + + nerr("ERROR: Failed to attach EMACTMR IRQ\n"); + return -EAGAIN; + } +#endif + +#ifdef CONFIG_IMX9_ENET_USE_OTP_MAC + + /* Boards like the imx93-evk have a unique (official) + * MAC address stored in OTP. + */ + + uidl = getreg32(IMX9_OCOTP_BASE + priv->otp_mac_off); + uidml = getreg32(IMX9_OCOTP_BASE + priv->otp_mac_off + 4); + mac = priv->dev.d_mac.ether.ether_addr_octet; + + mac[0] = (uidml & 0x0000ff00) >> 8; + mac[1] = (uidml & 0x000000ff) >> 0; + mac[2] = (uidl & 0xff000000) >> 24; + mac[3] = (uidl & 0x00ff0000) >> 16; + mac[4] = (uidl & 0x0000ff00) >> 8; + mac[5] = (uidl & 0x000000ff) >> 0; + +#else + + /* Determine a semi-unique MAC address from MCU UID + * We use UID Low and Mid Low registers to get 64 bits, from which we keep + * 40 bits. We then force locally administered bits in mac[0] based on + * interface number (0x2,0x6,0xa,0xe for if 0,1,2,3) + */ + + uidl = getreg32(IMX9_OCOTP_BASE + IMX93_OCOTP_UID_OFFSET); + uidml = getreg32(IMX9_OCOTP_BASE + IMX93_OCOTP_UID_OFFSET + 4); + mac = priv->dev.d_mac.ether.ether_addr_octet; + + mac[0] = (0x2 | (intf << 2)); + mac[1] = (uidml & 0x000000ff); + mac[2] = (uidl & 0xff000000) >> 24; + mac[3] = (uidl & 0x00ff0000) >> 16; + mac[4] = (uidl & 0x0000ff00) >> 8; + mac[5] = (uidl & 0x000000ff); + +#endif + +#ifdef CONFIG_IMX9_ENET_PHYINIT + /* Perform any necessary, one-time, board-specific PHY initialization */ + + ret = imx9_phy_boardinitialize(intf); + if (ret < 0) + { + nerr("ERROR: Failed to initialize the PHY: %d\n", ret); + return ret; + } +#endif + + /* Put the interface in the down state. This usually amounts to resetting + * the device and/or calling imx9_ifdown(). + */ + + imx9_ifdown(&priv->dev); + + /* Register the device with the OS so that socket IOCTLs can be performed */ + + netdev_register(&priv->dev, NET_LL_ETHERNET); + + UNUSED(ret); + return OK; +} + +/**************************************************************************** + * Name: arm_netinitialize + * + * Description: + * Initialize the first network interface. If there are more than one + * interface in the chip, then board-specific logic will have to provide + * this function to determine which, if any, Ethernet controllers should + * be initialized. + * + ****************************************************************************/ + +#if !defined(CONFIG_NETDEV_LATEINIT) +void arm64_netinitialize(void) +{ + int i; + + /* Configure all ENET/MII pins */ + + imx9_enet_mux_io(); + + /* Initialize all IFs */ + + for (i = 0; i < nitems(g_enet); i++) + { + imx9_netinitialize(i); + } +} +#endif + +#endif /* CONFIG_IMX9_ENET */ diff --git a/arch/arm64/src/imx9/imx9_enet.h b/arch/arm64/src/imx9/imx9_enet.h new file mode 100644 index 0000000000000..e37cdc6464a8a --- /dev/null +++ b/arch/arm64/src/imx9/imx9_enet.h @@ -0,0 +1,106 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_enet.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_ENET_H +#define __ARCH_ARM64_SRC_IMX9_IMX9_ENET_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "hardware/imx9_enet.h" + +#ifdef CONFIG_IMX9_ENET + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Definitions for use with imx9_phy_boardinitialize */ + +#define EMAC_INTF 0 + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Function: imx9_netinitialize + * + * Description: + * Initialize the Ethernet controller and driver + * + * Input Parameters: + * intf - In the case where there are multiple EMACs, this value + * identifies which EMAC is to be initialized. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +int imx9_netinitialize(int intf); + +/**************************************************************************** + * Function: imx9_phy_boardinitialize + * + * Description: + * Some boards require specialized initialization of the PHY before it can + * be used. This may include such things as configuring GPIOs, resetting + * the PHY, etc. If CONFIG_IMX9_ENET_PHYINIT is defined in the + * configuration then the board specific logic must provide + * imx9_phyinitialize(); The i.MX RT Ethernet driver will call this + * function one time before it first uses the PHY. + * + * Input Parameters: + * intf - Always zero for now. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_ENET_PHYINIT +int imx9_phy_boardinitialize(int intf); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_IMX9_ENET */ +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_ENET_H */ diff --git a/arch/arm64/src/imx9/imx9_flexio_pwm.c b/arch/arm64/src/imx9/imx9_flexio_pwm.c new file mode 100644 index 0000000000000..1e93a1ffdc45c --- /dev/null +++ b/arch/arm64/src/imx9/imx9_flexio_pwm.c @@ -0,0 +1,755 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_flexio_pwm.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "imx9_flexio_pwm.h" +#include "arm64_arch.h" +#include "imx9_ccm.h" +#include "imx9_iomuxc.h" +#include "hardware/imx9_ccm.h" +#include "hardware/imx9_pinmux.h" +#include "hardware/imx9_flexio.h" + +#ifdef CONFIG_IMX9_FLEXIO_PWM + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PIN_FOR_TIMER(priv, timer) ((uint8_t)(priv->pins >> (timer * 8))) + +#ifdef CONFIG_IMX9_FLEXIO1_PWM +# if (CONFIG_PWM_NCHANNELS < CONFIG_IMX9_FLEXIO1_PWM_NCHANNELS) +# error CONFIG_PWM_NCHANNELS < CONFIG_IMX9_FLEXIO1_PWM_NCHANNELS +# endif +#endif + +#ifdef CONFIG_IMX9_FLEXIO2_PWM +# if (CONFIG_PWM_NCHANNELS < CONFIG_IMX9_FLEXIO2_PWM_NCHANNELS) +# error CONFIG_PWM_NCHANNELS < CONFIG_IMX9_FLEXIO2_PWM_NCHANNELS +# endif +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure represents the state of one PWM timer */ + +struct imx9_pwmtimer_s +{ + const struct pwm_ops_s *ops; /* PWM operations */ + const flexio_pwm_id_t id; /* PWM_FLEXIO1 or PWM_FLEXIO2 */ + const int nchannels; /* Number of channels used */ + const uintptr_t base; /* The base address of the FLEXIO */ + const uint64_t pins; /* Mapping of timer outputs to flexio outputs */ + const int int_trigger; /* Uses flex-io internal timer for frequency */ + int trigger_ch; /* Trigger channel */ + unsigned frequency; /* Current frequency setting */ + int period; /* PWM period in ticks of functional clock */ +}; + +/**************************************************************************** + * Static Function Prototypes + ****************************************************************************/ + +/* PWM driver methods */ + +static int pwm_setup(struct pwm_lowerhalf_s *dev); +static int pwm_shutdown(struct pwm_lowerhalf_s *dev); + +static int pwm_start(struct pwm_lowerhalf_s *dev, + const struct pwm_info_s *info); + +static int pwm_stop(struct pwm_lowerhalf_s *dev); +static int pwm_ioctl(struct pwm_lowerhalf_s *dev, + int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This is the list of lower half PWM driver methods used by the upper half + * driver + */ + +static const struct pwm_ops_s g_pwmops = +{ + .setup = pwm_setup, + .shutdown = pwm_shutdown, + .start = pwm_start, + .stop = pwm_stop, + .ioctl = pwm_ioctl, +}; + +static struct imx9_pwmtimer_s g_pwmdev[] = +{ +#ifdef CONFIG_IMX9_FLEXIO1_PWM + { + .ops = &g_pwmops, + .id = PWM_FLEXIO1, + .nchannels = CONFIG_IMX9_FLEXIO1_PWM_NCHANNELS, + .base = IMX9_FLEXIO1_BASE, + .pins = CONFIG_IMX9_FLEXIO1_PWM_CHANNEL_PINS, + .int_trigger = 1, + }, +#endif + +#ifdef CONFIG_IMX9_FLEXIO2_PWM + { + .ops = &g_pwmops, + .id = PWM_FLEXIO2, + .nchannels = CONFIG_IMX9_FLEXIO2_PWM_NCHANNELS, + .base = IMX9_FLEXIO2_BASE, + .pins = CONFIG_IMX9_FLEXIO2_PWM_CHANNEL_PINS, + .int_trigger = 1, + }, +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: flexio_getreg + * + * Description: + * Read the value of a flex-io register. + * + * Input Parameters: + * priv - A reference to the PWM block + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static inline uint32_t flexio_getreg(struct imx9_pwmtimer_s *priv, + int offset) +{ + return getreg32(priv->base + offset); +} + +/**************************************************************************** + * Name: flexio_putreg + * + * Description: + * Read the value of an PWM timer register. + * + * Input Parameters: + * priv - A reference to the PWM block status + * offset - The offset to the register to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void flexio_putreg(struct imx9_pwmtimer_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->base + offset); +} + +/**************************************************************************** + * Name: flexio_mux + * + * Description: + * Mux the flex-io output pins to pads. The macros FLEXIOn_PWMx_MUX + * need to be defined in the board.h file + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void flexio_mux(void) +{ +#ifdef CONFIG_IMX9_FLEXIO1_PWM + +# ifdef FLEXIO1_PWM0_MUX + imx9_iomux_configure(FLEXIO1_PWM0_MUX); +# endif + +# ifdef FLEXIO1_PWM1_MUX + imx9_iomux_configure(FLEXIO1_PWM1_MUX); +# endif + +# ifdef FLEXIO1_PWM2_MUX + imx9_iomux_configure(FLEXIO1_PWM2_MUX); +# endif + +# ifdef FLEXIO1_PWM3_MUX + imx9_iomux_configure(FLEXIO1_PWM3_MUX); +# endif + +# ifdef FLEXIO1_PWM4_MUX + imx9_iomux_configure(FLEXIO1_PWM4_MUX); +# endif + +# ifdef FLEXIO1_PWM5_MUX + imx9_iomux_configure(FLEXIO1_PWM5_MUX); +# endif + +# ifdef FLEXIO1_PWM6_MUX + imx9_iomux_configure(FLEXIO1_PWM6_MUX); +# endif + +# ifdef FLEXIO1_PWM7_MUX + imx9_iomux_configure(FLEXIO1_PWM7_MUX); +# endif + +#endif + +#ifdef CONFIG_IMX9_FLEXIO2_PWM + +# ifdef FLEXIO2_PWM0_MUX + imx9_iomux_configure(FLEXIO2_PWM0_MUX); +# endif + +# ifdef FLEXIO2_PWM1_MUX + imx9_iomux_configure(FLEXIO2_PWM1_MUX); +# endif + +# ifdef FLEXIO2_PWM2_MUX + imx9_iomux_configure(FLEXIO2_PWM2_MUX); +# endif + +# ifdef FLEXIO2_PWM3_MUX + imx9_iomux_configure(FLEXIO2_PWM3_MUX); +# endif + +# ifdef FLEXIO2_PWM4_MUX + imx9_iomux_configure(FLEXIO2_PWM4_MUX); +# endif + +# ifdef FLEXIO2_PWM5_MUX + imx9_iomux_configure(FLEXIO2_PWM5_MUX); +# endif + +# ifdef FLEXIO2_PWM6_MUX + imx9_iomux_configure(FLEXIO2_PWM6_MUX); +# endif + +# ifdef FLEXIO2_PWM7_MUX + imx9_iomux_configure(FLEXIO2_PWM7_MUX); +# endif + +#endif +} + +/**************************************************************************** + * Name: pwm_init_trigger_timer + * + * Description: + * Initialize the timer trigger, generating the PWM frequency + * + * Input Parameters: + * priv - A reference to the lower half PWM driver state structure + * + * Returned Value: + * OK on success, ERROR if the timer initialization fails + * + ****************************************************************************/ + +static int pwm_init_trigger_timer(struct imx9_pwmtimer_s *priv) +{ + uint32_t reg; + int num_timers; + + /* For now, use the last available flexio timer to produce internal + * trigger. This can be later expanded to use external trigger from + * LPIT timer, if one more PWM channel is required + */ + + /* Get parameter register and number of supported timers */ + + reg = flexio_getreg(priv, IMX9_FLEXIO_PARAM_OFFSET); + num_timers = (reg & FLEXIO_PARAM_TIMER_MASK) >> FLEXIO_PARAM_TIMER_SHIFT; + + num_timers--; + if (num_timers < priv->nchannels) + { + pwmerr("PWM%d max channels %d\n", priv->id, num_timers); + return ERROR; + } + + priv->trigger_ch = num_timers; + + return OK; +} + +/**************************************************************************** + * Name: pwm_select_func_clock + * + * Description: + * Select best suitable functional clock for the flexio + * + * Input Parameters: + * priv - A reference to the lower half PWM driver state structure + * freq - The requested PWM frequency for this flexio block + * + * Returned Value: + * Zero on success, negated error value on failure + * + ****************************************************************************/ + +static int pwm_select_func_clock(struct imx9_pwmtimer_s *priv, int freq) +{ + const int max_div = 24000000 / 65536 + 1; /* for 1 Hz */ + int div; + uint32_t period; + + if (freq == 0) + { + priv->period = 0; + return 0; + } + + /* Use the 24MHz OSC clock, and find the best divider to get as much + * resolution as possible using 16 bit timer + */ + + for (div = 1; div < max_div; div++) + { + period = 24000000 / div / freq; + if (period < 65536) + { + priv->period = period; + break; + } + } + + imx9_ccm_configure_root_clock(CCM_CR_FLEXIO1 + priv->id, OSC_24M, div); + + /* Enable peripheral clock */ + + imx9_ccm_gate_on(CCM_LPCG_FLEXIO1 + priv->id , true); + + return 0; +} + +/**************************************************************************** + * Name: pwm_update_frequency + * + * Description: + * Initialize the timer trigger, generating the PWM freuency + * + * Input Parameters: + * priv - A reference to the lower half PWM driver state structure + * freq - The requested PWM frequency for this flexio block + * + * Returned Value: + * Zero on success, negated error value on failure + * + ****************************************************************************/ + +static int pwm_update_frequency(struct imx9_pwmtimer_s *priv, int freq) +{ + int ret = pwm_select_func_clock(priv, freq); + if (ret < 0) + { + return ret; + } + + /* Configure the timer to produce internal trigger. The following + * setting produces 50/50 pulse where duty cycle is defined by + * TIMCMP: + * + * TIMCFG: + * TIMOUT = 0 Timer output is logic one when enabled and not + * affected by timer reset + * TIMDEC = 0 Decrement counter on FLEXIO clock + * TIMRST = 0x0 Timer never reset + * TIMDIS = 0x0 Timer never disabled + * TIMENA = 0x0 Timer always enabled + * TIMCTL: + * TIMOD = 0x3 Single 16-bit counter + * PINCFG = 0x0 Output pin disabled + * TIMCMP: frequency / 2 + */ + + flexio_putreg(priv, IMX9_FLEXIO_TIMCMP_OFFSET(priv->trigger_ch), + priv->period / 2); + + /* Enable / disable timer */ + + flexio_putreg(priv, IMX9_FLEXIO_TIMCTL_OFFSET(priv->trigger_ch), + freq > 0 ? FLEXIO_TIMCTL_TIMOD(0x3) : + FLEXIO_TIMCTL_TIMOD(0x0)); + + return ret; +} + +/**************************************************************************** + * Name: pwm_update_duty + * + * Description: + * Change the channel duty cycle. + * + * Input Parameters: + * priv - A reference to the lower half PWM driver state structure + * channel - Channel to by updated + * duty - New duty cycle as fraction of 65536 + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_update_duty(struct imx9_pwmtimer_s *priv, int pwm_ch, + ub16_t duty16) +{ + uint32_t edge = ub16toi(duty16 * priv->period + b16HALF); + int timer = pwm_ch - 1; /* map pwm ch 1 to timer 0 etc.. */ + uint32_t regval; + + if (pwm_ch == 0 || pwm_ch > priv->nchannels) + { + pwmerr("ERROR: PWM%d has no such channel: %u\n", priv->id, pwm_ch); + return -EINVAL; + } + + /* Now configure the flexio timers in 16-bit counter mode */ + + /* Timers 0-6: + * TIMCFG: + * TIMOUT = 0 Timer output is 1 when enabled and not affected by reset + * TIMDEC = 0 Decrement counter on FLEXIO clock + * TIMRST = 0x0 Timer never reset + * TIMDIS = 0x2 Timer disabled on counter 0 + * TIMENA = 0x6 Timer enabled on Trigger rising edge + * TIMCTL: + * TIMOD = 0x3 single 16-bit counter + * TRGSEL = 4 * trg_ch + 3 timer "trg_ch" trigger output + * TRGSRC = 1 internal trigger + * PINCFG = 0x3 Timer pin output + * PINSEL = timer number + mux conf + * TIMCMP: duty cycle + */ + + /* If this is the first time configuring the PWMs, configure the + * timer fully, otherwise just update the duty cycle + */ + + flexio_putreg(priv, IMX9_FLEXIO_TIMCMP_OFFSET(timer), edge); + + if (priv->frequency == 0) + { + flexio_putreg(priv, IMX9_FLEXIO_TIMCFG_OFFSET(timer), + FLEXIO_TIMCFG_TIMDIS(0x2) | + FLEXIO_TIMCFG_TIMENA(0x6)); + + /* When initially configuring PINCFG=11b, FLEXIO may briefly drive the + * pin low. To avoid this, configure PINCFG=10b along with the rest of + * the control register and then perform a subsequent write to set + * PINCFG=11b + */ + + regval = (FLEXIO_TIMCTL_TIMOD(0x3) | + FLEXIO_TIMCTL_TRGSEL(4 * priv->trigger_ch + 3) | + FLEXIO_TIMCTL_TRGSRC(priv->int_trigger) | + FLEXIO_TIMCTL_PINSEL(PIN_FOR_TIMER(priv, timer))); + + flexio_putreg(priv, IMX9_FLEXIO_TIMCTL_OFFSET(timer), + regval | FLEXIO_TIMCTL_PINCFG(0x2)); + + flexio_putreg(priv, IMX9_FLEXIO_TIMCTL_OFFSET(timer), + regval | FLEXIO_TIMCTL_PINCFG(0x3)); + } + + pwminfo("PWM%d channel %d, p: %d e: %" PRIu32 "\n", priv->id, pwm_ch, + priv->period, edge); + + return 0; +} + +/**************************************************************************** + * Name: pwm_setup + * + * Description: + * This method is called when the driver is opened. The lower half driver + * should configure and initialize the device so that it is ready for use. + * It should not, however, output pulses until the start method is called. + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * Assumptions: + * + ****************************************************************************/ + +static int pwm_setup(struct pwm_lowerhalf_s *dev) +{ + return OK; +} + +/**************************************************************************** + * Name: pwm_shutdown + * + * Description: + * This method is called when the driver is closed. The lower half driver + * stop pulsed output, free any resources, disable the timer hardware, and + * put the system into the lowest possible power usage state + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_shutdown(struct pwm_lowerhalf_s *dev) +{ + /* Make sure that the output has been stopped */ + + pwm_stop(dev); + + return OK; +} + +/**************************************************************************** + * Name: pwm_start + * + * Description: + * (Re-)initialize the timer resources and start the pulsed output + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * info - A reference to the characteristics of the pulsed output + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_start(struct pwm_lowerhalf_s *dev, + const struct pwm_info_s *info) +{ + struct imx9_pwmtimer_s *priv = (struct imx9_pwmtimer_s *)dev; + int ret = OK; + int i; + + if (priv == NULL || info == NULL || info->frequency == 0) + { + return -EINVAL; + } + + /* Set the frequency if not changed */ + + if (info->frequency != priv->frequency) + { + ret = pwm_update_frequency(priv, info->frequency); + } + + /* Handle channel specific setup */ + + for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) + { + if (ret != OK || info->channels[i].channel == -1) + { + break; + } + + ret = pwm_update_duty(priv, info->channels[i].channel, + info->channels[i].duty); + } + + if (ret == OK) + { + priv->frequency = info->frequency; + } + + return ret; +} + +/**************************************************************************** + * Name: pwm_stop + * + * Description: + * Stop the pulsed output and reset the timer resources + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * Assumptions: + * This function is called to stop the pulsed output at anytime. + * + ****************************************************************************/ + +static int pwm_stop(struct pwm_lowerhalf_s *dev) +{ + struct imx9_pwmtimer_s *priv = (struct imx9_pwmtimer_s *)dev; + int i; + + pwminfo("PWM%d stop\n", priv->id); + + /* Check that timer is valid */ + + if (priv == NULL) + { + return -EINVAL; + } + + /* Disable all the channels */ + + for (i = 0; i < priv->nchannels; i++) + { + flexio_putreg(priv, IMX9_FLEXIO_TIMCTL_OFFSET(i), + FLEXIO_TIMCTL_PINCFG(0x2)); + flexio_putreg(priv, IMX9_FLEXIO_TIMCTL_OFFSET(i), 0); + } + + /* Setting frequency to zero disables trigger clock */ + + return pwm_update_frequency(priv, 0); +} + +/**************************************************************************** + * Name: pwm_ioctl + * + * Description: + * Lower-half logic may support platform-specific ioctl commands + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * cmd - The ioctl command + * arg - The argument accompanying the ioctl command + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd, + unsigned long arg) +{ + return -ENOTTY; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_flexio_pwm_init + * + * Description: + * Initialize flexio blocks to generate EPWM. + * + * Input Parameters: + * pwmid - A number identifying the pwm block. The number of valid + * IDs varies depending on the configuration. + * + * Returned Value: + * On success, a pointer to the lower half PWM driver is + * returned. NULL is returned on any failure. + * + ****************************************************************************/ + +struct pwm_lowerhalf_s *imx9_flexio_pwm_init(flexio_pwm_id_t pwmid) +{ + struct imx9_pwmtimer_s *lower = NULL; + int i; + + for (i = 0; i < sizeof(g_pwmdev) / sizeof(struct imx9_pwmtimer_s); i++) + { + if (pwmid == g_pwmdev[i].id) + { + lower = &g_pwmdev[i]; + break; + } + } + + if (lower) + { + /* IO mux */ + + flexio_mux(); + + /* Reset FlexIO */ + + flexio_putreg(lower, IMX9_FLEXIO_CTRL_OFFSET, FLEXIO_CTRL_SWRST(1)); + + /* Enable FlexIO and de-assert reset */ + + flexio_putreg(lower, IMX9_FLEXIO_CTRL_OFFSET, FLEXIO_CTRL_FLEXEN(1)); + + /* Make sure that FlexIO is enabled and reset is cleared */ + + while (flexio_getreg(lower, IMX9_FLEXIO_CTRL_OFFSET) != + FLEXIO_CTRL_FLEXEN_MASK); + + /* Initialize the trigger timer used for PWM period generation */ + + if (pwm_init_trigger_timer(lower) != OK) + { + /* Disable FlexIO */ + + flexio_putreg(lower, IMX9_FLEXIO_CTRL_OFFSET, 0); + + return NULL; + } + + pwminfo("PWM%d at 0x%" PRIxPTR " configured\n", pwmid, lower->base); + } + else + { + pwmerr("ERROR: No such timer configured %d\n", pwmid); + } + + return (struct pwm_lowerhalf_s *)lower; +} + +#endif diff --git a/arch/arm64/src/imx9/imx9_flexio_pwm.h b/arch/arm64/src/imx9/imx9_flexio_pwm.h new file mode 100644 index 0000000000000..a4b3f8d97d529 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_flexio_pwm.h @@ -0,0 +1,104 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_flexio_pwm.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_FLEXIO_PWM_H +#define __ARCH_ARM64_SRC_IMX9_IMX9_FLEXIO_PWM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Check if PWM support for any channel is enabled. */ + +#ifdef CONFIG_IMX9_FLEXIO_PWM + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/imx9_flexio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef enum +{ + PWM_FLEXIO1 = 0, + PWM_FLEXIO2 = 1, +} flexio_pwm_id_t; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_flexio_pwm_init + * + * Description: + * Initialize a FLEXIO block for EPWM usage. + * + * Input Parameters: + * pwmid - A number identifying the pwm block. + * + * Returned Value: + * On success, a pointer to the lower half of the PWM driver is + * returned. NULL is returned on any failure. + * + ****************************************************************************/ + +struct pwm_lowerhalf_s *imx9_flexio_pwm_init(flexio_pwm_id_t pwmid); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_IMX9_FLEXIO_PWM */ +#endif /* __ARCH_ARM64_SRC_IMX9_IMX9_FLEXIO_PWM_H */ diff --git a/arch/arm64/src/imx9/imx9_gpio.c b/arch/arm64/src/imx9/imx9_gpio.c new file mode 100644 index 0000000000000..54db67a1469b5 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_gpio.c @@ -0,0 +1,278 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include + +#include "chip.h" +#include "arm64_internal.h" +#include "imx9_iomuxc.h" +#include "imx9_gpio.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_gpio_dirout + ****************************************************************************/ + +static inline void imx9_gpio_dirout(uint32_t port, uint32_t pin) +{ + uint32_t regval = getreg32(IMX9_GPIO_PDDR(port)); + regval |= GPIO_PIN(pin); + putreg32(regval, IMX9_GPIO_PDDR(port)); +} + +/**************************************************************************** + * Name: imx9_gpio_dirin + ****************************************************************************/ + +static inline void imx9_gpio_dirin(uint32_t port, uint32_t pin) +{ + uint32_t regval = getreg32(IMX9_GPIO_PDDR(port)); + regval &= ~GPIO_PIN(pin); + putreg32(regval, IMX9_GPIO_PDDR(port)); +} + +/**************************************************************************** + * Name: imx9_gpio_setoutput + ****************************************************************************/ + +static void imx9_gpio_setoutput(uint32_t port, uint32_t pin, bool value) +{ + uintptr_t regaddr = IMX9_GPIO_PDOR(port); + uint32_t regval; + + regval = getreg32(regaddr); + if (value) + { + regval |= GPIO_PIN(pin); + } + else + { + regval &= ~GPIO_PIN(pin); + } + + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: imx9_gpio_getpin_status + ****************************************************************************/ + +static inline bool imx9_gpio_get_pinstatus(uint32_t port, uint32_t pin) +{ + uintptr_t regaddr = IMX9_GPIO_PSOR(port); + uint32_t regval; + + regval = getreg32(regaddr); + return ((regval & GPIO_PIN(pin)) != 0); +} + +/**************************************************************************** + * Name: imx9_gpio_getinput + ****************************************************************************/ + +static inline bool imx9_gpio_getinput(uint32_t port, uint32_t pin) +{ + uintptr_t regaddr = IMX9_GPIO_PDIR(port); + uint32_t regval; + + regval = getreg32(regaddr); + return ((regval & GPIO_PIN(pin)) != 0); +} + +/**************************************************************************** + * Name: imx9_gpio_configinput + ****************************************************************************/ + +static int imx9_gpio_configinput(gpio_pinset_t pinset) +{ + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS); + + /* Configure pin as in input */ + + imx9_gpio_dirin(port, pin); + + return OK; +} + +/**************************************************************************** + * Name: imx9_gpio_configoutput + ****************************************************************************/ + +static inline int imx9_gpio_configoutput(gpio_pinset_t pinset) +{ + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + bool value = ((pinset & GPIO_OUTPUT_ONE) != 0); + + DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS); + + /* Set the output value */ + + imx9_gpio_setoutput(port, pin, value); + + /* Convert the configured input GPIO to an output */ + + imx9_gpio_dirout(port, pin); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_config_gpio + * + * Description: + * Configure a GPIO pin based on pin-encoded description of the pin. + * + ****************************************************************************/ + +int imx9_config_gpio(gpio_pinset_t pinset) +{ + irqstate_t flags; + int ret; + + /* Configure the pin as an input initially to avoid any spurious outputs */ + + flags = enter_critical_section(); + + /* Configure based upon the pin mode */ + + switch (pinset & GPIO_MODE_MASK) + { + case GPIO_INPUT: + { + /* Configure the pin as a GPIO input */ + + ret = imx9_gpio_configinput(pinset); + } + break; + + case GPIO_OUTPUT: + { + /* First configure the pin as a GPIO input to avoid output + * glitches. + */ + + ret = imx9_gpio_configinput(pinset); + if (ret >= 0) + { + /* Convert the input to an output */ + + ret = imx9_gpio_configoutput(pinset); + } + } + break; + +#ifdef CONFIG_IMX9_GPIO_IRQ + case GPIO_INTERRUPT: + { + /* Configure the pin as a GPIO input */ + + ret = imx9_gpio_configinput(pinset); + if (ret == OK) + { + ret = imx9_gpioirq_configure(pinset); + } + } + break; +#endif + + default: + ret = -EINVAL; + break; + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: imx9_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void imx9_gpio_write(gpio_pinset_t pinset, bool value) +{ + irqstate_t flags; + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS); + + flags = enter_critical_section(); + imx9_gpio_setoutput(port, pin, value); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: imx9_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool imx9_gpio_read(gpio_pinset_t pinset) +{ + irqstate_t flags; + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + bool value; + + DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS); + + flags = enter_critical_section(); + if ((pinset & (GPIO_OUTPUT)) == (GPIO_OUTPUT)) + { + value = imx9_gpio_get_pinstatus(port, pin); + } + else + { + value = imx9_gpio_getinput(port, pin); + } + + leave_critical_section(flags); + return value; +} diff --git a/arch/arm64/src/imx9/imx9_gpio.h b/arch/arm64/src/imx9/imx9_gpio.h new file mode 100644 index 0000000000000..1c7f44a53f6fe --- /dev/null +++ b/arch/arm64/src/imx9/imx9_gpio.h @@ -0,0 +1,337 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_GPIO_H +#define __ARCH_ARM64_SRC_IMX9_IMX9_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "hardware/imx9_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* GPIO pinset is a 16-bit word used to configure the GPIO settings. The + * encoding is as follows... + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ENCODING MMVX BEEG GGGP PPPP + * GPIO INPUT 00.. BEEG GGGP PPPP + * INT INPUT 11.. BEEG GGGP PPPP + * GPIO OUTPUT 01V. ...G GGGP PPPP + */ + +/* Input/Output Selection: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ENCODING MM.. .... .... .... + */ + +#define GPIO_MODE_SHIFT (14) /* Bits 14-15: Pin mode */ +#define GPIO_MODE_MASK (0x3 << GPIO_MODE_SHIFT) +# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* GPIO input */ +# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* GPIO output */ +# define GPIO_INTERRUPT (2 << GPIO_MODE_SHIFT) /* Interrupt input */ + +/* Initial Output Value: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * GPIO OUTPUT 01V. .... .... .... + */ + +#define GPIO_OUTPUT_SHIFT (13) /* Bit 13: Initial output */ +#define GPIO_OUTPUT_MASK (0x1 << GPIO_OUTPUT_SHIFT) +# define GPIO_OUTPUT_ZERO (0 << GPIO_OUTPUT_SHIFT) /* Bit 29: 0=Initial output is low */ +# define GPIO_OUTPUT_ONE (1 << GPIO_OUTPUT_SHIFT) /* Bit 29: 1=Initial output is high */ + +/* Interrupt on both edges configuration + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * INT INPUT 11.. B... .... .... + */ + +#define GPIO_INTBOTHCFG_SHIFT (11) /* Bit 11: Interrupt both edges configuration */ +#define GPIO_INTBOTHCFG_MASK (1 << GPIO_INTBOTHCFG_SHIFT) +# define GPIO_INTBOTH_EDGES (1 << GPIO_INTBOTHCFG_SHIFT) + +/* Interrupt edge/level configuration + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * INT INPUT 11.. .EE. .... .... + */ + +#define GPIO_INTCFG_SHIFT (9) /* Bits 9-10: Interrupt edge/level configuration */ +#define GPIO_INTCFG_MASK (0x3 << GPIO_INTCFG_SHIFT) +# define GPIO_INT_LOWLEVEL (0 << GPIO_INTCFG_SHIFT) +# define GPIO_INT_HIGHLEVEL (1 << GPIO_INTCFG_SHIFT) +# define GPIO_INT_RISINGEDGE (2 << GPIO_INTCFG_SHIFT) +# define GPIO_INT_FALLINGEDGE (3 << GPIO_INTCFG_SHIFT) + +/* GPIO Port Number + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * GPIO IN/OUT .... ...G GGG. .... + */ + +#define GPIO_PORT_SHIFT (5) /* Bits 5-8: GPIO port index */ +#define GPIO_PORT_MASK (0xf << GPIO_PORT_SHIFT) +# define GPIO_PORT1 (GPIO1 << GPIO_PORT_SHIFT) /* GPIO1 */ +# define GPIO_PORT2 (GPIO2 << GPIO_PORT_SHIFT) /* GPIO2 */ +# define GPIO_PORT3 (GPIO3 << GPIO_PORT_SHIFT) /* GPIO3 */ +# define GPIO_PORT4 (GPIO4 << GPIO_PORT_SHIFT) /* GPIO4 */ +# define GPIO_PORT5 (GPIO5 << GPIO_PORT_SHIFT) /* GPIO5 */ +# define GPIO_PORT6 (GPIO6 << GPIO_PORT_SHIFT) /* GPIO6 */ +# define GPIO_PORT7 (GPIO7 << GPIO_PORT_SHIFT) /* GPIO7 */ +# define GPIO_PORT8 (GPIO8 << GPIO_PORT_SHIFT) /* GPIO8 */ +# define GPIO_PORT9 (GPIO9 << GPIO_PORT_SHIFT) /* GPIO9 */ +# define GPIO_PORT10 (GPIO10 << GPIO_PORT_SHIFT) /* GPIO10 */ +# define GPIO_PORT11 (GPIO11 << GPIO_PORT_SHIFT) /* GPIO11 */ +# define GPIO_PORT12 (GPIO12 << GPIO_PORT_SHIFT) /* GPIO12 */ +# define GPIO_PORT13 (GPIO13 << GPIO_PORT_SHIFT) /* GPIO13 */ + +/* GPIO Pin Number: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * GPIO IN/OUT .... .... ...P PPPP + */ + +#define GPIO_PIN_SHIFT (0) /* Bits 0-4: GPIO pin number */ +#define GPIO_PIN_MASK (0x1f << GPIO_PIN_SHIFT) +# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) /* Pin 0 */ +# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) /* Pin 1 */ +# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) /* Pin 2 */ +# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) /* Pin 3 */ +# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) /* Pin 4 */ +# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) /* Pin 5 */ +# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) /* Pin 6 */ +# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) /* Pin 7 */ +# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) /* Pin 8 */ +# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) /* Pin 9 */ +# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) /* Pin 10 */ +# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) /* Pin 11 */ +# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) /* Pin 12 */ +# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) /* Pin 13 */ +# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) /* Pin 14 */ +# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) /* Pin 15 */ +# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) /* Pin 16 */ +# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) /* Pin 17 */ +# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) /* Pin 18 */ +# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) /* Pin 19 */ +# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) /* Pin 20 */ +# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) /* Pin 21 */ +# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) /* Pin 22 */ +# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) /* Pin 23 */ +# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) /* Pin 24 */ +# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) /* Pin 25 */ +# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) /* Pin 26 */ +# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) /* Pin 27 */ +# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) /* Pin 28 */ +# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) /* Pin 29 */ +# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) /* Pin 30 */ +# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) /* Pin 31 */ + +/* Port access via global LUT */ + +#define IMX9_GPIO_BASE(n) g_gpio_base[n] /* Use GPIO1..GPIOn macros as indices */ + +#define IMX9_GPIO_VERID(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_VERID_OFFSET) +#define IMX9_GPIO_PARAM(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PARAM_OFFSET) +#define IMX9_GPIO_LOCK(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_LOCK_OFFSET) +#define IMX9_GPIO_PCNS(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PCNS_OFFSET) +#define IMX9_GPIO_ICNS(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ICNS_OFFSET) +#define IMX9_GPIO_PCNP(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PCNP_OFFSET) +#define IMX9_GPIO_ICNP(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ICNP_OFFSET) +#define IMX9_GPIO_PDOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PDOR_OFFSET) +#define IMX9_GPIO_PSOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PSOR_OFFSET) +#define IMX9_GPIO_PCOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PCOR_OFFSET) +#define IMX9_GPIO_PTOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PTOR_OFFSET) +#define IMX9_GPIO_PDIR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PDIR_OFFSET) +#define IMX9_GPIO_PDDR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PDDR_OFFSET) +#define IMX9_GPIO_PIDR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PIDR_OFFSET) +#define IMX9_GPIO_GICLR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_GICLR_OFFSET) +#define IMX9_GPIO_GICHR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_GICHR_OFFSET) + +/* Interrupt status flags, these have two channels. Channel is selected by + * setting / clearing ICRN.IRQS bit. + */ + +#define IMX9_GPIO_ISFR0(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ISFR0_OFFSET) +#define IMX9_GPIO_ISFR1(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ISFR1_OFFSET) + +/* GPIO PIN[0...31] and ICR[0...31] */ + +#define IMX9_GPIO_P0DR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_P0DR_OFFSET) +#define IMX9_GPIO_PNDR(n, p) (IMX9_GPIO_P0DR(n) + ((p) * 0x4)) +#define IMX9_GPIO_ICR0(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ICR0_OFFSET) +#define IMX9_GPIO_ICRN(n, p) (IMX9_GPIO_ICR0(n) + ((p) * 0x4)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* The smallest integer type that can hold the GPIO encoding */ + +typedef uint16_t gpio_pinset_t; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* Look-up table that maps GPIO1..GPIOn indexes into GPIO register base + * addresses + */ + +EXTERN const uintptr_t g_gpio_base[]; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_gpioirq_initialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_GPIO_IRQ +void imx9_gpioirq_initialize(void); +#else +# define imx9_gpioirq_initialize() +#endif + +/**************************************************************************** + * Name: imx9_config_gpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int imx9_config_gpio(gpio_pinset_t pinset); + +/**************************************************************************** + * Name: imx9_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void imx9_gpio_write(gpio_pinset_t pinset, bool value); + +/**************************************************************************** + * Name: imx9_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool imx9_gpio_read(gpio_pinset_t pinset); + +/**************************************************************************** + * Name: imx9_gpioirq_attach + * + * Description: + * Attach a pin interrupt handler. + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_GPIO_IRQ +int imx9_gpioirq_attach(gpio_pinset_t pinset, xcpt_t isr, void *arg); +#else +#define imx9_gpioirq_attach(pinset, isr, arg) 0 +#endif + +/**************************************************************************** + * Name: imx9_gpioirq_configure + * + * Description: + * Configure an interrupt for the specified GPIO pin. + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_GPIO_IRQ +int imx9_gpioirq_configure(gpio_pinset_t pinset); +#else +# define imx9_gpioirq_configure(pinset) 0 +#endif + +/**************************************************************************** + * Name: imx9_gpioirq_enable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_GPIO_IRQ +int imx9_gpioirq_enable(gpio_pinset_t pinset); +#else +# define imx9_gpioirq_enable(pinset) 0 +#endif + +/**************************************************************************** + * Name: imx9_gpioirq_disable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_GPIO_IRQ +int imx9_gpioirq_disable(gpio_pinset_t pinset); +#else +# define imx9_gpioirq_disable(pinset) 0 +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ARCH_ARM64_SRC_IMX9_IMX9_GPIO_H */ diff --git a/arch/arm64/src/imx9/imx9_gpiobase.c b/arch/arm64/src/imx9/imx9_gpiobase.c new file mode 100644 index 0000000000000..cf5e1f0ddb117 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_gpiobase.c @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_gpiobase.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "imx9_gpio.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#if defined(CONFIG_ARCH_CHIP_IMX93) +/* Base address for the GPIO memory mapped registers */ + +const uintptr_t g_gpio_base[] = +{ + IMX9_GPIO1_BASE, + IMX9_GPIO2_BASE, + IMX9_GPIO3_BASE, + IMX9_GPIO4_BASE, +}; +#else +# error Unrecognized i.MX9 architecture +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm64/src/imx9/imx9_gpioirq.c b/arch/arm64/src/imx9/imx9_gpioirq.c new file mode 100644 index 0000000000000..7290ff6852e24 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_gpioirq.c @@ -0,0 +1,300 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_gpioirq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm64_internal.h" +#include "imx9_gpio.h" + +#ifdef CONFIG_IMX9_GPIO_IRQ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct imx9_portisr_s +{ + struct + { + xcpt_t isr; /* The interrupt service routine */ + void *arg; /* Argument passed to it */ + } + pins[IMX9_GPIO_NPINS]; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct imx9_portisr_s g_isrtab[IMX9_GPIO_NPORTS]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_gpio_interrupt + * + * Description: + * GPIO interrupt handlers. iMX9 has two interrupt sources for each pin, + * the NuttX driver uses source 0. + * + ****************************************************************************/ + +static int imx9_gpio_interrupt(int irq, void *context, void *arg) +{ + uint32_t port = (uint32_t)((uintptr_t)arg) >> GPIO_PORT_SHIFT; + uint32_t status; + uint32_t pin; + uint32_t regaddr; + + /* Get the pending interrupt indications */ + + regaddr = IMX9_GPIO_ISFR0(port); + status = getreg32(regaddr); + + /* Decode the pending interrupts */ + + for (pin = 0; pin < 32 && status != 0; pin++) + { + /* Is the IRQ associated with this pin pending? */ + + uint32_t mask = (1 << pin); + if ((status & mask) != 0) + { + struct imx9_portisr_s *isrtab; + + /* Yes, clear the status bit and dispatch the interrupt */ + + putreg32(mask, regaddr); + status &= ~mask; + + /* Get the interrupt table for this port */ + + isrtab = &g_isrtab[port]; + if (isrtab->pins[pin].isr != NULL) + { + /* Run the user handler with the user's argument */ + + isrtab->pins[pin].isr(irq, context, isrtab->pins[pin].arg); + } + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_gpioirq_initialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. + * + ****************************************************************************/ + +void imx9_gpioirq_initialize(void) +{ + uint32_t port; + uint32_t pin; + + /* Disable all GPIO interrupts at the source */ + + for (port = 0; port < IMX9_GPIO_NPORTS; port++) + { + for (pin = 0; pin < IMX9_GPIO_NPINS; pin++) + { + /* Reset the interrupt configuration, disabling the interrupt */ + + putreg32(0, IMX9_GPIO_ICRN(port, pin)); + } + } + + /* Disable all GPIO interrupts */ + + up_disable_irq(IMX9_IRQ_GPIO1_0); + up_disable_irq(IMX9_IRQ_GPIO1_1); + + up_disable_irq(IMX9_IRQ_GPIO2_0); + up_disable_irq(IMX9_IRQ_GPIO2_1); + + up_disable_irq(IMX9_IRQ_GPIO3_0); + up_disable_irq(IMX9_IRQ_GPIO3_1); + + up_disable_irq(IMX9_IRQ_GPIO4_0); + up_disable_irq(IMX9_IRQ_GPIO4_1); + + /* Attach the common GPIO interrupt handler and enable the interrupt */ + + DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO1_0, + imx9_gpio_interrupt, (void *)GPIO_PORT1)); + up_enable_irq(IMX9_IRQ_GPIO1_0); + + DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO2_0, + imx9_gpio_interrupt, (void *)GPIO_PORT2)); + up_enable_irq(IMX9_IRQ_GPIO2_0); + + DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO3_0, + imx9_gpio_interrupt, (void *)GPIO_PORT3)); + up_enable_irq(IMX9_IRQ_GPIO3_0); + + DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO4_0, + imx9_gpio_interrupt, (void *)GPIO_PORT4)); + up_enable_irq(IMX9_IRQ_GPIO4_0); +} + +/**************************************************************************** + * Name: imx9_gpioirq_attach + * + * Description: + * Attach a pin interrupt handler. + * + ****************************************************************************/ + +int imx9_gpioirq_attach(gpio_pinset_t pinset, xcpt_t isr, void *arg) +{ + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Atomically change the handler */ + + irqstate_t flags = enter_critical_section(); + + g_isrtab[port].pins[pin].isr = isr; + g_isrtab[port].pins[pin].arg = arg; + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: imx9_gpioirq_configure + * + * Description: + * Configure an interrupt for the specified GPIO pin. + * + ****************************************************************************/ + +int imx9_gpioirq_configure(gpio_pinset_t pinset) +{ + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Nothing much to do here, just reset the IRQ config */ + + putreg32(0, IMX9_GPIO_ICRN(port, pin)); + + return OK; +} + +/**************************************************************************** + * Name: imx9_gpioirq_enable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +int imx9_gpioirq_enable(gpio_pinset_t pinset) +{ + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + uint32_t both = (pinset & GPIO_INTBOTHCFG_MASK) >> GPIO_INTBOTHCFG_SHIFT; + uint32_t icr = (pinset & GPIO_INTCFG_MASK); + uint32_t regval; + uintptr_t regaddr; + + /* Perform RMW to the specific pin */ + + regaddr = IMX9_GPIO_ICRN(port, pin); + regval = getreg32(regaddr); + regval &= ~IMX9_GPIO_ICRN_MASK; + + if (both) + { + regval |= IMX9_GPIO_ICRN_BOTH; + } + else if (icr == GPIO_INT_LOWLEVEL) + { + regval |= IMX9_GPIO_ICRN_ZERO; + } + else if (icr == GPIO_INT_HIGHLEVEL) + { + regval |= IMX9_GPIO_ICRN_ONE; + } + else if (icr == GPIO_INT_RISINGEDGE) + { + regval |= IMX9_GPIO_ICRN_RISING; + } + else /* GPIO_INT_FALLINGEDGE */ + { + regval |= IMX9_GPIO_ICRN_FALLING; + } + + putreg32(regval, regaddr); + return OK; +} + +/**************************************************************************** + * Name: imx9_gpioirq_disable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +int imx9_gpioirq_disable(gpio_pinset_t pinset) +{ + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + uint32_t regval; + uintptr_t regaddr; + + /* Perform RMW to the specific pin */ + + regaddr = IMX9_GPIO_ICRN(port, pin); + regval = getreg32(regaddr); + regval &= ~IMX9_GPIO_ICRN_MASK; + + putreg32(regval, regaddr); + return OK; +} + +#endif /* CONFIG_IMX9_GPIO_IRQ */ diff --git a/arch/arm64/src/imx9/imx9_iomuxc.c b/arch/arm64/src/imx9/imx9_iomuxc.c new file mode 100644 index 0000000000000..b5f8b657cf996 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_iomuxc.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_iomuxc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "arm64_internal.h" +#include "imx9_iomuxc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_iomux_configure + * + * Description: + * This function writes the encoded pad configuration to the Pad Control + * register. + * + * Input Parameters: + * cfg - The IOMUX configuration + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int imx9_iomux_configure(iomux_cfg_t cfg) +{ + if (!cfg.padcfg.ctlreg) + { + return -EINVAL; + } + + putreg32(cfg.padcfg.mode | cfg.mux, cfg.padcfg.ctlreg); + + if (cfg.padcfg.dsyreg) + { + putreg32(cfg.padcfg.dsy, cfg.padcfg.dsyreg); + } + + if (cfg.padcfg.padreg) + { + putreg32(cfg.pad, cfg.padcfg.padreg); + } + + return OK; +} + +/**************************************************************************** + * Name: imx9_iomux_configure + * + * Description: + * This can be used to forcibly set a pad to GPIO mode. This overrides and + * disconnects any peripheral using the pin. + * + * Input Parameters: + * cfg - The IOMUX configuration. + * sion - if true; sets SION, otherwise clears it. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int imx9_iomux_gpio(iomux_cfg_t cfg, bool sion) +{ + uint32_t reg_sion; + + if (!cfg.padcfg.ctlreg) + { + return -EINVAL; + } + + /* Set sion if requested to do so */ + + reg_sion = sion ? IOMUXC_MUX_SION_ON : 0; + + /* Based on pad number, either ALT0/ALT5 sets the pad as GPIO */ + + if ((cfg.padcfg.ctlreg >= IOMUXC_MUX_CTL_GPIO_IO00_OFFSET) && + (cfg.padcfg.ctlreg <= IOMUXC_MUX_CTL_GPIO_IO29_OFFSET)) + { + putreg32(IOMUXC_MUX_MODE_ALT0 | reg_sion, cfg.padcfg.ctlreg); + } + else + { + putreg32(IOMUXC_MUX_MODE_ALT5 | reg_sion, cfg.padcfg.ctlreg); + } + + return OK; +} diff --git a/arch/arm64/src/imx9/imx9_iomuxc.h b/arch/arm64/src/imx9/imx9_iomuxc.h new file mode 100644 index 0000000000000..6b9c8617b3051 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_iomuxc.h @@ -0,0 +1,139 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_iomuxc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_IOMUXC_H +#define __ARCH_ARM64_SRC_IMX9_IMX9_IOMUXC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "hardware/imx9_iomuxc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IOMUX_PADCFG(_ctlreg, _mode, _dsyreg, _dsy, _padreg) \ + { \ + .ctlreg = (_ctlreg), \ + .padreg = (_padreg), \ + .dsyreg = (_dsyreg), \ + .mode = (_mode), \ + .dsy = (_dsy), \ + } + +#define IOMUX_CFG(_padcfg, _pad, _mux) \ + (iomux_cfg_t) \ + { \ + .padcfg = _padcfg, \ + .pad = (_pad), \ + .mux = (_mux), \ + } + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Information for the pad alternate function */ + +struct iomux_padcfg_s +{ + /* Register offsets for PAD */ + + uintptr_t ctlreg; + uintptr_t padreg; + uintptr_t dsyreg; + + /* ALT and input daisy configuration for pad */ + + uint32_t mode; + uint32_t dsy; +}; + +struct iomux_cfg_s +{ + struct iomux_padcfg_s padcfg; + + /* Register values */ + + uint32_t pad; + uint32_t mux; +}; +typedef struct iomux_cfg_s iomux_cfg_t; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: imx9_iomux_configure + * + * Description: + * This function writes the encoded pad configuration to the Pad Control + * register. + * + * Input Parameters: + * cfg - The IOMUX configuration + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int imx9_iomux_configure(iomux_cfg_t cfg); + +/**************************************************************************** + * Name: imx9_iomux_configure + * + * Description: + * This can be used to forcibly set a pad to GPIO mode. This overrides and + * disconnects any peripheral using the pin. + * + * Input Parameters: + * cfg - The IOMUX configuration. + * sion - if true; sets SION, otherwise clears it. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int imx9_iomux_gpio(iomux_cfg_t cfg, bool sion); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ARCH_ARM64_SRC_IMX9_IMX9_IOMUXC_H */ diff --git a/arch/arm64/src/imx9/imx9_lowputc.c b/arch/arm64/src/imx9/imx9_lowputc.c new file mode 100644 index 0000000000000..c41f6f43eed12 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_lowputc.c @@ -0,0 +1,532 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_lowputc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "hardware/imx9_pinmux.h" +#include "hardware/imx9_lpuart.h" + +#include "arm64_internal.h" + +#include "imx9_lowputc.h" +#include "imx9_ccm.h" +#include "imx9_iomuxc.h" +#include "hardware/imx9_ccm.h" +#include "hardware/imx9_pinmux.h" + +#include /* Include last: has dependencies */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) +# define IMX9_CONSOLE_DEVOFF 0 +# define IMX9_CONSOLE_BASE IMX9_LPUART1_BASE +# define IMX9_CONSOLE_BAUD CONFIG_LPUART1_BAUD +# define IMX9_CONSOLE_BITS CONFIG_LPUART1_BITS +# define IMX9_CONSOLE_PARITY CONFIG_LPUART1_PARITY +# define IMX9_CONSOLE_2STOP CONFIG_LPUART1_2STOP +#elif defined(CONFIG_LPUART2_SERIAL_CONSOLE) +# define IMX9_CONSOLE_DEVNUM 1 +# define IMX9_CONSOLE_BASE IMX9_LPUART2_BASE +# define IMX9_CONSOLE_BAUD CONFIG_LPUART2_BAUD +# define IMX9_CONSOLE_BITS CONFIG_LPUART2_BITS +# define IMX9_CONSOLE_PARITY CONFIG_LPUART2_PARITY +# define IMX9_CONSOLE_2STOP CONFIG_LPUART2_2STOP +#elif defined(CONFIG_LPUART3_SERIAL_CONSOLE) +# define IMX9_CONSOLE_DEVNUM 2 +# define IMX9_CONSOLE_BASE IMX9_LPUART3_BASE +# define IMX9_CONSOLE_BAUD CONFIG_LPUART3_BAUD +# define IMX9_CONSOLE_BITS CONFIG_LPUART3_BITS +# define IMX9_CONSOLE_PARITY CONFIG_LPUART3_PARITY +# define IMX9_CONSOLE_2STOP CONFIG_LPUART3_2STOP +#elif defined(CONFIG_LPUART4_SERIAL_CONSOLE) +# define IMX9_CONSOLE_DEVNUM 3 +# define IMX9_CONSOLE_BASE IMX9_LPUART4_BASE +# define IMX9_CONSOLE_BAUD CONFIG_LPUART4_BAUD +# define IMX9_CONSOLE_BITS CONFIG_LPUART4_BITS +# define IMX9_CONSOLE_PARITY CONFIG_LPUART4_PARITY +# define IMX9_CONSOLE_2STOP CONFIG_LPUART4_2STOP +#elif defined(CONFIG_LPUART5_SERIAL_CONSOLE) +# define IMX9_CONSOLE_DEVNUM 4 +# define IMX9_CONSOLE_BASE IMX9_LPUART5_BASE +# define IMX9_CONSOLE_BAUD CONFIG_LPUART5_BAUD +# define IMX9_CONSOLE_BITS CONFIG_LPUART5_BITS +# define IMX9_CONSOLE_PARITY CONFIG_LPUART5_PARITY +# define IMX9_CONSOLE_2STOP CONFIG_LPUART5_2STOP +#elif defined(CONFIG_LPUART6_SERIAL_CONSOLE) +# define IMX9_CONSOLE_DEVNUM 5 +# define IMX9_CONSOLE_BASE IMX9_LPUART6_BASE +# define IMX9_CONSOLE_BAUD CONFIG_LPUART6_BAUD +# define IMX9_CONSOLE_BITS CONFIG_LPUART6_BITS +# define IMX9_CONSOLE_PARITY CONFIG_LPUART6_PARITY +# define IMX9_CONSOLE_2STOP CONFIG_LPUART6_2STOP +#elif defined(CONFIG_LPUART7_SERIAL_CONSOLE) +# define IMX9_CONSOLE_DEVNUM 6 +# define IMX9_CONSOLE_BASE IMX9_LPUART7_BASE +# define IMX9_CONSOLE_BAUD CONFIG_LPUART7_BAUD +# define IMX9_CONSOLE_BITS CONFIG_LPUART7_BITS +# define IMX9_CONSOLE_PARITY CONFIG_LPUART7_PARITY +# define IMX9_CONSOLE_2STOP CONFIG_LPUART7_2STOP +#elif defined(CONFIG_LPUART8_SERIAL_CONSOLE) +# define IMX9_CONSOLE_DEVNUM 7 +# define IMX9_CONSOLE_BASE IMX9_LPUART8_BASE +# define IMX9_CONSOLE_BAUD CONFIG_LPUART8_BAUD +# define IMX9_CONSOLE_BITS CONFIG_LPUART8_BITS +# define IMX9_CONSOLE_PARITY CONFIG_LPUART8_PARITY +# define IMX9_CONSOLE_2STOP CONFIG_LPUART8_2STOP +#endif + +#define ABS(n) (((n) < 0) ? -(n) : (n)) + +/* Clocking *****************************************************************/ + +/* Functional clocking is provided via the PCC. The PCC clocking must + * be configured by board-specific logic prior to using the LPUART. + */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef IMX9_CONSOLE_BASE +static const struct uart_config_s g_console_config = +{ + .baud = IMX9_CONSOLE_BAUD, /* Configured baud */ + .parity = IMX9_CONSOLE_PARITY, /* 0=none, 1=odd, 2=even */ + .bits = IMX9_CONSOLE_BITS, /* Number of bits (5-9) */ + .stopbits2 = IMX9_CONSOLE_2STOP, /* true: Configure with 2 stop bits instead of 1 */ +}; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level + * initialization including setup of the console UART. This UART done + * early so that the serial console is available for debugging very early + * in the boot sequence. + * + ****************************************************************************/ + +void imx9_lowsetup(void) +{ +#ifndef CONFIG_SUPPRESS_LPUART_CONFIG + +#ifdef CONFIG_IMX9_LPUART1 + /* Configure LPUART1 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + imx9_iomux_configure(MUX_LPUART1_RX); + imx9_iomux_configure(MUX_LPUART1_TX); +#ifdef CONFIG_LPUART1_OFLOWCONTROL + imx9_iomux_configure(MUX_LPUART1_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL))) + imx9_iomux_configure(MUX_LPUART1_RTS); +#endif +#endif + +#ifdef CONFIG_IMX9_LPUART2 + + /* Configure LPUART2 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + imx9_iomux_configure(MUX_LPUART2_RX); + imx9_iomux_configure(MUX_LPUART2_TX); +#ifdef CONFIG_LPUART2_OFLOWCONTROL + imx9_iomux_configure(MUX_LPUART2_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL))) + imx9_iomux_configure(MUX_LPUART2_RTS); +#endif +#endif + +#ifdef CONFIG_IMX9_LPUART3 + + /* Configure LPUART3 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + imx9_iomux_configure(MUX_LPUART3_RX); + imx9_iomux_configure(MUX_LPUART3_TX); +#ifdef CONFIG_LPUART3_OFLOWCONTROL + imx9_iomux_configure(MUX_LPUART3_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL))) + imx9_iomux_configure(MUX_LPUART3_RTS); +#endif +#endif + +#ifdef CONFIG_IMX9_LPUART4 + + /* Configure LPUART4 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + imx9_iomux_configure(LPUART4_RX); + imx9_iomux_configure(LPUART4_TX); +#ifdef CONFIG_LPUART4_OFLOWCONTROL + imx9_iomux_configure(LPUART4_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL))) + imx9_iomux_configure(LPUART4_RTS); +#endif +#endif + +#ifdef CONFIG_IMX9_LPUART5 + + /* Configure LPUART5 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + imx9_iomux_configure(MUX_LPUART5_RX); + imx9_iomux_configure(MUX_LPUART5_TX); +#ifdef CONFIG_LPUART5_OFLOWCONTROL + imx9_iomux_configure(MUX_LPUART5_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL))) + imx9_iomux_configure(MUX_LPUART5_RTS); +#endif +#endif + +#ifdef CONFIG_IMX9_LPUART6 + + /* Configure LPUART6 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + imx9_iomux_configure(MUX_LPUART6_RX); + imx9_iomux_configure(MUX_LPUART6_TX); +#ifdef CONFIG_LPUART6_OFLOWCONTROL + imx9_iomux_configure(MUX_LPUART6_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL))) + imx9_iomux_configure(MUX_LPUART6_RTS); +#endif +#endif + +#ifdef CONFIG_IMX9_LPUART7 + + /* Configure LPUART7 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + imx9_iomux_configure(MUX_LPUART7_RX); + imx9_iomux_configure(MUX_LPUART7_TX); +#ifdef CONFIG_LPUART7_OFLOWCONTROL + imx9_iomux_configure(MUX_LPUART7_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL))) + imx9_iomux_configure(MUX_LPUART7_RTS); +#endif +#endif + +#ifdef CONFIG_IMX9_LPUART8 + + /* Configure LPUART8 pins: RXD and TXD. Also configure RTS and CTS if flow + * control is enabled. + */ + + imx9_iomux_configure(MUX_LPUART8_RX); + imx9_iomux_configure(MUX_LPUART8_TX); +#ifdef CONFIG_LPUART0_OFLOWCONTROL + imx9_iomux_configure(MUX_LPUART8_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL))) + imx9_iomux_configure(MUX_LPUART8_RTS); +#endif +#endif + +#ifdef IMX9_CONSOLE_BASE + /* Configure the serial console for initial, non-interrupt driver mode */ + + imx9_lpuart_configure(IMX9_CONSOLE_BASE, IMX9_CONSOLE_DEVOFF, + &g_console_config); +#endif + +#endif /* CONFIG_SUPPRESS_LPUART_CONFIG */ +} + +/**************************************************************************** + * Name: imx9_lpuart_configure + * + * Description: + * Configure a UART for non-interrupt driven operation + * + ****************************************************************************/ + +int imx9_lpuart_configure(uint32_t base, int uartnum, + const struct uart_config_s *config) +{ + int lpuart_freq = 24000000; + uint16_t sbr; + uint16_t temp_sbr; + uint32_t osr; + uint32_t temp_osr; + int temp_diff; + int calculated_baud; + int baud_diff; + uint32_t regval; + + /* Configure root clock to 24MHz OSC */ + + imx9_ccm_configure_root_clock(CCM_CR_LPUART1 + uartnum - 1, OSC_24M, 1); + + /* Enable peripheral clock */ + + imx9_ccm_gate_on(CCM_LPCG_LPUART1 + uartnum - 1, true); + + /* This LPUART instantiation uses a slightly different baud rate + * calculation. The idea is to use the best OSR (over-sampling rate) + * possible. + * + * NOTE: OSR is typically hard-set to 16 in other LPUART instantiations + * loop to find the best OSR value possible, one that generates minimum + * baud_diff iterate through the rest of the supported values of OSR + */ + + baud_diff = config->baud; + osr = 0; + sbr = 0; + + for (temp_osr = 4; temp_osr <= 32; temp_osr++) + { + /* Calculate the temporary sbr value */ + + temp_sbr = (lpuart_freq / (config->baud * temp_osr)); + + /* Set temp_sbr to 1 if the sourceClockInHz can not satisfy the + * desired baud rate. + */ + + if (temp_sbr == 0) + { + temp_sbr = 1; + } + + /* Calculate the baud rate based on the temporary OSR and SBR values */ + + calculated_baud = (lpuart_freq / (temp_osr * temp_sbr)); + temp_diff = ABS(calculated_baud - config->baud); + + /* Select the better value between srb and (sbr + 1) */ + + calculated_baud = (lpuart_freq / (temp_osr * (temp_sbr + 1))); + if (temp_diff > + ABS(calculated_baud - config->baud)) + { + temp_diff = ABS(calculated_baud - config->baud); + temp_sbr++; + } + + if (temp_diff <= baud_diff) + { + baud_diff = temp_diff; + osr = temp_osr; + sbr = temp_sbr; + } + } + + if (baud_diff > ((config->baud * 3) / 100)) + { + /* Unacceptable baud rate difference of more than 3% */ + + return ERROR; + } + + /* Reset all internal logic and registers, except the Global Register */ + + regval = getreg32(base + IMX9_LPUART_GLOBAL_OFFSET); + regval |= LPUART_GLOBAL_RST; + putreg32(regval, base + IMX9_LPUART_GLOBAL_OFFSET); + + regval &= ~LPUART_GLOBAL_RST; + putreg32(regval, base + IMX9_LPUART_GLOBAL_OFFSET); + + /* Construct MODIR register */ + + regval = 0; + + if (config->userts) + { + regval |= LPUART_MODIR_RXRTSE; + } + else if (config->users485) + { + /* Both TX and RX side can't control RTS, so this gives + * the RX side precedence. This should have been filtered + * in layers above anyway, but it's just a precaution. + */ + + regval |= LPUART_MODIR_TXRTSE; + } + + if (config->usects) + { + regval |= LPUART_MODIR_TXCTSE; + } + + if (config->invrts) + { + regval |= LPUART_MODIR_TXRTSPOL; + } + + putreg32(regval, base + IMX9_LPUART_MODIR_OFFSET); + + regval = 0; + + if ((osr > 3) && (osr < 8)) + { + regval |= LPUART_BAUD_BOTHEDGE; + } + + if (config->stopbits2) + { + regval |= LPUART_BAUD_SBNS; + } + + regval |= LPUART_BAUD_OSR(osr) | LPUART_BAUD_SBR(sbr); + putreg32(regval, base + IMX9_LPUART_BAUD_OFFSET); + + regval = 0; + if (config->parity == 1) + { + regval |= LPUART_CTRL_PE | LPUART_CTRL_PT_ODD; + } + else if (config->parity == 2) + { + regval |= LPUART_CTRL_PE | LPUART_CTRL_PT_EVEN; + } + + if (config->bits == 9 || (config->bits == 8 && config->parity != 0)) + { + regval |= LPUART_CTRL_M; + } + else if ((config->bits == 8)) + { + regval &= ~LPUART_CTRL_M; + } + else + { + /* REVISIT: Here should be added support of other bit modes. */ + + return -ENOSYS; + } + + regval |= LPUART_CTRL_RE | LPUART_CTRL_TE; + putreg32(regval, base + IMX9_LPUART_CTRL_OFFSET); + + return OK; +} + +/**************************************************************************** + * Name: arm64_earlyprintinit + * + * Description: + * Configure LPUART1 for non-interrupt driven operation + * + ****************************************************************************/ + +void arm64_earlyprintinit(char ch) +{ + /* Assume bootloader has already set up the LPUART1 */ +} + +/**************************************************************************** + * Name: arm64_lowputc + * + * Description: + * Output a byte with as few system dependencies as possible. This will + * even work BEFORE the console is initialized if we are booting from U- + * Boot (and the same UART is used for the console, of course.) + * + ****************************************************************************/ + +void arm64_lowputc(char ch) +{ +#ifdef IMX9_CONSOLE_BASE + while ((getreg32(IMX9_CONSOLE_BASE + IMX9_LPUART_STAT_OFFSET) & + LPUART_STAT_TDRE) == 0) + { + } + + /* If the character to output is a newline, + * then pre-pend a carriage return + */ + + if (ch == '\n') + { + /* Send the carriage return by writing it into the UART_TXD register. */ + + putreg32((uint32_t)'\r', + IMX9_CONSOLE_BASE + IMX9_LPUART_DATA_OFFSET); + + /* Wait for the transmit register to be emptied. When the TXFE bit is + * non-zero, the TX Buffer FIFO is empty. + */ + + while ((getreg32(IMX9_CONSOLE_BASE + IMX9_LPUART_STAT_OFFSET) & + LPUART_STAT_TDRE) == 0) + { + } + } + + /* Send the character by writing it into the UART_TXD register. */ + + putreg32((uint32_t)ch, IMX9_CONSOLE_BASE + IMX9_LPUART_DATA_OFFSET); + + /* Wait for the transmit register to be emptied. When the TXFE bit is + * non-zero, the TX Buffer FIFO is empty. + */ + + while ((getreg32(IMX9_CONSOLE_BASE + IMX9_LPUART_STAT_OFFSET) & + LPUART_STAT_TDRE) == 0) + { + } +#endif +} diff --git a/arch/arm64/src/imx9/imx9_lowputc.h b/arch/arm64/src/imx9/imx9_lowputc.h new file mode 100644 index 0000000000000..30aceed681c28 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_lowputc.h @@ -0,0 +1,84 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_lowputc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_LOWPUTC_H +#define __ARCH_ARM_SRC_IMX9_IMX9_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include "arm64_internal.h" + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* This structure describes the configuration of an UART */ + +struct uart_config_s +{ + uint32_t baud; /* Configured baud */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (5-9) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ + bool userts; /* True: Assert RTS when there are data to be sent */ + bool invrts; /* True: Invert sense of RTS pin (true=active high) */ + bool usects; /* True: Condition transmission on CTS asserted */ + bool users485; /* True: Assert RTS while transmission progresses */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_lowsetup + * + * Description: + * Called at the very beginning of _start. Performs low level + * initialization including setup of the console UART. This UART done + * early so that the serial console is available for debugging very early + * in the boot sequence. + * + ****************************************************************************/ + +void imx9_lowsetup(void); + +/**************************************************************************** + * Name: imx9_lpuart_configure + * + * Description: + * Configure a UART for non-interrupt driven operation + * + ****************************************************************************/ + +int imx9_lpuart_configure(uint32_t base, + int uartnum, + const struct uart_config_s *config); + +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_LOWPUTC_H */ diff --git a/arch/arm64/src/imx9/imx9_lpi2c.c b/arch/arm64/src/imx9/imx9_lpi2c.c new file mode 100644 index 0000000000000..c1122b1ddcb7e --- /dev/null +++ b/arch/arm64/src/imx9/imx9_lpi2c.c @@ -0,0 +1,2579 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_lpi2c.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "arm64_internal.h" +#include "imx9_ccm.h" +#include "imx9_clockconfig.h" +#include "imx9_gpio.h" +#include "imx9_iomuxc.h" +#include "imx9_lpi2c.h" + +#include "hardware/imx9_ccm.h" +#include "hardware/imx9_pinmux.h" +#include "hardware/imx9_lpi2c.h" + +#ifdef CONFIG_IMX9_LPI2C_DMA +# include "chip.h" +# include "imx9_edma.h" +# include "hardware/imx9_dmamux.h" +#endif + +/* At least one I2C peripheral must be enabled */ + +#ifdef CONFIG_IMX9_LPI2C + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* CONFIG_I2C_POLLED may be set so that I2C interrupts will not be used. + * Instead, CPU-intensive polling will be used. + */ + +/* Interrupt wait timeout in seconds and milliseconds */ + +#if !defined(CONFIG_IMX9_LPI2C_TIMEOSEC) && \ + !defined(CONFIG_IMX9_LPI2C_TIMEOMS) +# define CONFIG_IMX9_LPI2C_TIMEOSEC 0 +# define CONFIG_IMX9_LPI2C_TIMEOMS 500 /* Default is 500 milliseconds */ +#elif !defined(CONFIG_IMX9_LPI2C_TIMEOSEC) +# define CONFIG_IMX9_LPI2C_TIMEOSEC 0 /* User provided milliseconds */ +#elif !defined(CONFIG_IMX9_LPI2C_TIMEOMS) +# define CONFIG_IMX9_LPI2C_TIMEOMS 0 /* User provided seconds */ +#endif + +/* Interrupt wait time timeout in system timer ticks */ + +#ifndef CONFIG_IMX9_LPI2C_TIMEOTICKS +# define CONFIG_IMX9_LPI2C_TIMEOTICKS \ + (SEC2TICK(CONFIG_IMX9_LPI2C_TIMEOSEC) + \ + MSEC2TICK(CONFIG_IMX9_LPI2C_TIMEOMS)) +#endif + +#ifndef CONFIG_IMX9_LPI2C_DYNTIMEO_STARTSTOP +# define CONFIG_IMX9_LPI2C_DYNTIMEO_STARTSTOP \ + TICK2USEC(CONFIG_IMX9_LPI2C_TIMEOTICKS) +#endif + +/* Debug ********************************************************************/ + +/* I2C event trace logic. NOTE: trace uses the internal, non-standard, + * low-level debug interface syslog() but does not require that any other + * debug is enabled. + */ + +#ifndef CONFIG_I2C_TRACE +# define imx9_lpi2c_tracereset(p) +# define imx9_lpi2c_tracenew(p,s) +# define imx9_lpi2c_traceevent(p,e,a) +# define imx9_lpi2c_tracedump(p) +#endif + +#ifndef CONFIG_I2C_NTRACE +# define CONFIG_I2C_NTRACE 32 +#endif + +#ifdef CONFIG_I2C_SLAVE +# error I2C slave logic is not supported yet for IMX9 +#endif + +#define LPI2C_MASTER 1 +#define LPI2C_SLAVE 2 + +#define LPI2C_MSR_LIMITED_ERROR_MASK (LPI2C_MSR_ERROR_MASK & ~(LPI2C_MSR_FEF)) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Interrupt state */ + +enum imx9_intstate_e +{ + INTSTATE_IDLE = 0, /* No I2C activity */ + INTSTATE_WAITING, /* Waiting for completion of interrupt activity */ + INTSTATE_DONE, /* Interrupt activity complete */ +}; + +/* Trace events */ + +enum imx9_trace_e +{ + I2CEVENT_NONE = 0, /* No events have occurred with this status */ + I2CEVENT_SENDADDR, /* Start/Master bit set and address sent, param = msgc */ + I2CEVENT_SENDBYTE, /* Send byte, param = dcnt */ + I2CEVENT_RCVBYTE, /* Read more dta, param = dcnt */ + I2CEVENT_NOSTART, /* BTF on last byte with no restart, param = msgc */ + I2CEVENT_STARTRESTART, /* Last byte sent, re-starting, param = msgc */ + I2CEVENT_STOP, /* Last byte sten, send stop, param = 0 */ + I2CEVENT_ERROR /* Error occurred, param = 0 */ +}; + +/* Trace data */ + +struct imx9_trace_s +{ + uint32_t status; /* I2C 32-bit SR2|SR1 status */ + uint32_t count; /* Interrupt count when status change */ + enum imx9_intstate_e event; /* Last event that occurred with this status */ + uint32_t parm; /* Parameter associated with the event */ + clock_t time; /* First of event or first status */ +}; + +/* I2C Device hardware configuration */ + +struct imx9_lpi2c_config_s +{ + uint32_t base; /* LPI2C base address */ + uint8_t clk_root; /* LPI2C clock root */ + uint8_t clk_gate; /* LPI2C clock gate */ + uint16_t busy_idle; /* LPI2C Bus Idle Timeout */ + uint8_t filtscl; /* Glitch Filter for SCL pin */ + uint8_t filtsda; /* Glitch Filter for SDA pin */ + iomux_cfg_t scl_pin; /* Peripheral configuration for SCL as SCL */ + iomux_cfg_t sda_pin; /* Peripheral configuration for SDA as SDA */ +#if defined(CONFIG_I2C_RESET) + gpio_pinset_t reset_scl_pin; /* GPIO configuration for SCL as GPIO */ + gpio_pinset_t reset_sda_pin; /* GPIO configuration for SDA as GPIO */ +#endif + uint8_t mode; /* Master or Slave mode */ +#ifndef CONFIG_I2C_POLLED + uint32_t irq; /* Event IRQ */ +#endif +#ifdef CONFIG_IMX9_LPI2C_DMA + uint32_t dma_rxreqsrc; /* DMA mux rx source */ + uint32_t dma_txreqsrc; /* DMA mux tx source */ +#endif +}; + +/* I2C Device Private Data */ + +struct imx9_lpi2c_priv_s +{ + /* Standard I2C operations */ + + const struct i2c_ops_s *ops; + + /* Port configuration */ + + const struct imx9_lpi2c_config_s *config; + + int refs; /* Reference count */ + mutex_t lock; /* Mutual exclusion mutex */ +#ifndef CONFIG_I2C_POLLED + sem_t sem_isr; /* Interrupt wait semaphore */ +#endif + volatile uint8_t intstate; /* Interrupt handshake (see enum imx9_intstate_e) */ + + uint8_t msgc; /* Message count */ + struct i2c_msg_s *msgv; /* Message list */ + uint8_t *ptr; /* Current message buffer */ + uint32_t frequency; /* Current I2C frequency */ + int dcnt; /* Current message length */ + uint16_t flags; /* Current message flags */ + + /* I2C trace support */ + +#ifdef CONFIG_I2C_TRACE + int tndx; /* Trace array index */ + clock_t start_time; /* Time when the trace was started */ + + /* The actual trace data */ + + struct imx9_trace_s trace[CONFIG_I2C_NTRACE]; +#endif + + uint32_t status; /* End of transfer SR2|SR1 status */ + +#ifdef CONFIG_IMX9_LPI2C_DMA + DMACH_HANDLE rxdma; /* rx DMA handle */ + DMACH_HANDLE txdma; /* tx DMA handle */ + uint16_t cmnds[CONFIG_IMX9_LPI2C_DMA_MAXMSG]; /* Commands */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint32_t +imx9_lpi2c_getreg(struct imx9_lpi2c_priv_s *priv, uint16_t offset); +static inline void imx9_lpi2c_putreg(struct imx9_lpi2c_priv_s *priv, + uint16_t offset, uint32_t value); +static inline void imx9_lpi2c_modifyreg(struct imx9_lpi2c_priv_s *priv, + uint16_t offset, uint32_t clearbits, + uint32_t setbits); + +#ifdef CONFIG_IMX9_LPI2C_DYNTIMEO +static uint32_t imx9_lpi2c_toticks(int msgc, struct i2c_msg_s *msgs); +#endif /* CONFIG_IMX9_LPI2C_DYNTIMEO */ + +static inline int +imx9_lpi2c_sem_waitdone(struct imx9_lpi2c_priv_s *priv); + +#ifdef CONFIG_I2C_TRACE +static void imx9_lpi2c_tracereset(struct imx9_lpi2c_priv_s *priv); +static void imx9_lpi2c_tracenew(struct imx9_lpi2c_priv_s *priv, + uint32_t status); +static void imx9_lpi2c_traceevent(struct imx9_lpi2c_priv_s *priv, + enum imx9_trace_e event, uint32_t parm); +static void imx9_lpi2c_tracedump(struct imx9_lpi2c_priv_s *priv); +#endif /* CONFIG_I2C_TRACE */ + +static void imx9_lpi2c_setclock(struct imx9_lpi2c_priv_s *priv, + uint32_t frequency); +static inline void imx9_lpi2c_sendstart(struct imx9_lpi2c_priv_s *priv, + uint8_t address); +static inline void imx9_lpi2c_sendstop(struct imx9_lpi2c_priv_s *priv); +static inline uint32_t +imx9_lpi2c_getstatus(struct imx9_lpi2c_priv_s *priv); + +static int imx9_lpi2c_isr_process(struct imx9_lpi2c_priv_s *priv); + +#ifndef CONFIG_I2C_POLLED +static int imx9_lpi2c_isr(int irq, void *context, void *arg); +#endif /* !CONFIG_I2C_POLLED */ + +static void imx9_lpi2c_clock_enable(struct imx9_lpi2c_priv_s *priv); +static void imx9_lpi2c_clock_disable(struct imx9_lpi2c_priv_s *priv); +static int imx9_lpi2c_init(struct imx9_lpi2c_priv_s *priv); +static int imx9_lpi2c_deinit(struct imx9_lpi2c_priv_s *priv); +static int imx9_lpi2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, int count); +#ifdef CONFIG_I2C_RESET +static int imx9_lpi2c_reset(struct i2c_master_s *dev); +#endif + +#ifdef CONFIG_IMX9_LPI2C_DMA +static void imx9_rxdma_callback(DMACH_HANDLE handle, void *arg, bool done, + int result); +static void imx9_txdma_callback(DMACH_HANDLE handle, void *arg, bool done, + int result); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Trace events strings */ + +#ifdef CONFIG_I2C_TRACE +static const char *g_trace_names[] = +{ + "NONE ", + "SENDADDR ", + "SENDBYTE ", + "RCVBYTE ", + "NOSTART ", + "START/RESTART ", + "STOP ", + "ERROR " +}; +#endif + +/* I2C interface */ + +static const struct i2c_ops_s imx9_lpi2c_ops = +{ + .transfer = imx9_lpi2c_transfer, +#ifdef CONFIG_I2C_RESET + .reset = imx9_lpi2c_reset, +#endif +}; + +/* I2C device structures */ + +#ifdef CONFIG_IMX9_LPI2C1 +static const struct imx9_lpi2c_config_s imx9_lpi2c1_config = +{ + .base = IMX9_LPI2C1_BASE, + .clk_root = CCM_CR_LPI2C1, + .clk_gate = CCM_LPCG_LPI2C1, + .busy_idle = CONFIG_IMX9_LPI2C1_BUSYIDLE, + .filtscl = CONFIG_IMX9_LPI2C1_FILTSCL, + .filtsda = CONFIG_IMX9_LPI2C1_FILTSDA, + .scl_pin = MUX_LPI2C1_SCL, + .sda_pin = MUX_LPI2C1_SDA, +#if defined(CONFIG_I2C_RESET) + .reset_scl_pin = GPIO_LPI2C1_SCL_RESET, + .reset_sda_pin = GPIO_LPI2C1_SDA_RESET, +#endif +#ifndef CONFIG_I2C_SLAVE + .mode = LPI2C_MASTER, +#else + .mode = LPI2C_SLAVE, +#endif +#ifndef CONFIG_I2C_POLLED + .irq = IMX9_IRQ_LPI2C1, +#endif +#ifdef CONFIG_IMX9_LPI2C1_DMA + .dma_rxreqsrc = DMA_REQUEST_MUXLPI2C1RX, + .dma_txreqsrc = DMA_REQUEST_MUXLPI2C1TX, +#endif +}; + +static struct imx9_lpi2c_priv_s imx9_lpi2c1_priv = +{ + .ops = &imx9_lpi2c_ops, + .config = &imx9_lpi2c1_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_IMX9_LPI2C2 +static const struct imx9_lpi2c_config_s imx9_lpi2c2_config = +{ + .base = IMX9_LPI2C2_BASE, + .clk_root = CCM_CR_LPI2C2, + .clk_gate = CCM_LPCG_LPI2C2, + .busy_idle = CONFIG_IMX9_LPI2C2_BUSYIDLE, + .filtscl = CONFIG_IMX9_LPI2C2_FILTSCL, + .filtsda = CONFIG_IMX9_LPI2C2_FILTSDA, + .scl_pin = MUX_LPI2C2_SCL, + .sda_pin = MUX_LPI2C2_SDA, +#if defined(CONFIG_I2C_RESET) + .reset_scl_pin = GPIO_LPI2C2_SCL_RESET, + .reset_sda_pin = GPIO_LPI2C2_SDA_RESET, +#endif +#ifndef CONFIG_I2C_SLAVE + .mode = LPI2C_MASTER, +#else + .mode = LPI2C_SLAVE, +#endif +#ifndef CONFIG_I2C_POLLED + .irq = IMX9_IRQ_LPI2C2, +#endif +#ifdef CONFIG_IMX9_LPI2C2_DMA + .dma_rxreqsrc = DMA_REQUEST_MUXLPI2C2RX, + .dma_txreqsrc = DMA_REQUEST_MUXLPI2C2TX, +#endif +}; + +static struct imx9_lpi2c_priv_s imx9_lpi2c2_priv = +{ + .ops = &imx9_lpi2c_ops, + .config = &imx9_lpi2c2_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_IMX9_LPI2C3 +static const struct imx9_lpi2c_config_s imx9_lpi2c3_config = +{ + .base = IMX9_LPI2C3_BASE, + .clk_root = CCM_CR_LPI2C3, + .clk_gate = CCM_LPCG_LPI2C3, + .busy_idle = CONFIG_IMX9_LPI2C3_BUSYIDLE, + .filtscl = CONFIG_IMX9_LPI2C3_FILTSCL, + .filtsda = CONFIG_IMX9_LPI2C3_FILTSDA, + .scl_pin = MUX_LPI2C3_SCL, + .sda_pin = MUX_LPI2C3_SDA, +#if defined(CONFIG_I2C_RESET) + .reset_scl_pin = GPIO_LPI2C3_SCL_RESET, + .reset_sda_pin = GPIO_LPI2C3_SDA_RESET, +#endif +#ifndef CONFIG_I2C_SLAVE + .mode = LPI2C_MASTER, +#else + .mode = LPI2C_SLAVE, +#endif +#ifndef CONFIG_I2C_POLLED + .irq = IMX9_IRQ_LPI2C3, +#endif +#ifdef CONFIG_IMX9_LPI2C3_DMA + .dma_rxreqsrc = DMA_REQUEST_MUXLPI2C3RX, + .dma_txreqsrc = DMA_REQUEST_MUXLPI2C3TX, +#endif +}; + +static struct imx9_lpi2c_priv_s imx9_lpi2c3_priv = +{ + .ops = &imx9_lpi2c_ops, + .config = &imx9_lpi2c3_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_IMX9_LPI2C4 +static const struct imx9_lpi2c_config_s imx9_lpi2c4_config = +{ + .base = IMX9_LPI2C4_BASE, + .clk_root = CCM_CR_LPI2C4, + .clk_gate = CCM_LPCG_LPI2C4, + .busy_idle = CONFIG_IMX9_LPI2C4_BUSYIDLE, + .filtscl = CONFIG_IMX9_LPI2C4_FILTSCL, + .filtsda = CONFIG_IMX9_LPI2C4_FILTSDA, + .scl_pin = MUX_LPI2C4_SCL, + .sda_pin = MUX_LPI2C4_SDA, +#if defined(CONFIG_I2C_RESET) + .reset_scl_pin = GPIO_LPI2C4_SCL_RESET, + .reset_sda_pin = GPIO_LPI2C4_SDA_RESET, +#endif +#ifndef CONFIG_I2C_SLAVE + .mode = LPI2C_MASTER, +#else + .mode = LPI2C_SLAVE, +#endif +#ifndef CONFIG_I2C_POLLED + .irq = IMX9_IRQ_LPI2C4, +#endif +#ifdef CONFIG_IMX9_LPI2C4_DMA + .dma_rxreqsrc = DMA_REQUEST_MUXLPI2C4RX, + .dma_txreqsrc = DMA_REQUEST_MUXLPI2C4TX, +#endif +}; + +static struct imx9_lpi2c_priv_s imx9_lpi2c4_priv = +{ + .ops = &imx9_lpi2c_ops, + .config = &imx9_lpi2c4_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_IMX9_LPI2C5 +static const struct imx9_lpi2c_config_s imx9_lpi2c5_config = +{ + .base = IMX9_LPI2C5_BASE, + .clk_root = CCM_CR_LPI2C5, + .clk_gate = CCM_LPCG_LPI2C5, + .busy_idle = CONFIG_IMX9_LPI2C5_BUSYIDLE, + .filtscl = CONFIG_IMX9_LPI2C5_FILTSCL, + .filtsda = CONFIG_IMX9_LPI2C5_FILTSDA, + .scl_pin = MUX_LPI2C5_SCL, + .sda_pin = MUX_LPI2C5_SDA, +#if defined(CONFIG_I2C_RESET) + .reset_scl_pin = GPIO_LPI2C5_SCL_RESET, + .reset_sda_pin = GPIO_LPI2C5_SDA_RESET, +#endif +#ifndef CONFIG_I2C_SLAVE + .mode = LPI2C_MASTER, +#else + .mode = LPI2C_SLAVE, +#endif +#ifndef CONFIG_I2C_POLLED + .irq = IMX9_IRQ_LPI2C5, +#endif +#ifdef CONFIG_IMX9_LPI2C5_DMA + .dma_rxreqsrc = DMA_REQUEST_MUXLPI2C5RX, + .dma_txreqsrc = DMA_REQUEST_MUXLPI2C5TX, +#endif +}; + +static struct imx9_lpi2c_priv_s imx9_lpi2c5_priv = +{ + .ops = &imx9_lpi2c_ops, + .config = &imx9_lpi2c5_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_IMX9_LPI2C6 +static const struct imx9_lpi2c_config_s imx9_lpi2c6_config = +{ + .base = IMX9_LPI2C6_BASE, + .clk_root = CCM_CR_LPI2C6, + .clk_gate = CCM_LPCG_LPI2C6, + .busy_idle = CONFIG_IMX9_LPI2C6_BUSYIDLE, + .filtscl = CONFIG_IMX9_LPI2C6_FILTSCL, + .filtsda = CONFIG_IMX9_LPI2C6_FILTSDA, + .scl_pin = MUX_LPI2C6_SCL, + .sda_pin = MUX_LPI2C6_SDA, +#if defined(CONFIG_I2C_RESET) + .reset_scl_pin = GPIO_LPI2C6_SCL_RESET, + .reset_sda_pin = GPIO_LPI2C6_SDA_RESET, +#endif +#ifndef CONFIG_I2C_SLAVE + .mode = LPI2C_MASTER, +#else + .mode = LPI2C_SLAVE, +#endif +#ifndef CONFIG_I2C_POLLED + .irq = IMX9_IRQ_LPI2C6, +#endif +#ifdef CONFIG_IMX9_LPI2C6_DMA + .dma_rxreqsrc = DMA_REQUEST_MUXLPI2C6RX, + .dma_txreqsrc = DMA_REQUEST_MUXLPI2C6TX, +#endif +}; + +static struct imx9_lpi2c_priv_s imx9_lpi2c6_priv = +{ + .ops = &imx9_lpi2c_ops, + .config = &imx9_lpi2c6_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_IMX9_LPI2C7 +static const struct imx9_lpi2c_config_s imx9_lpi2c7_config = +{ + .base = IMX9_LPI2C7_BASE, + .clk_root = CCM_CR_LPI2C7, + .clk_gate = CCM_LPCG_LPI2C7, + .busy_idle = CONFIG_IMX9_LPI2C7_BUSYIDLE, + .filtscl = CONFIG_IMX9_LPI2C7_FILTSCL, + .filtsda = CONFIG_IMX9_LPI2C7_FILTSDA, + .scl_pin = MUX_LPI2C7_SCL, + .sda_pin = MUX_LPI2C7_SDA, +#if defined(CONFIG_I2C_RESET) + .reset_scl_pin = GPIO_LPI2C7_SCL_RESET, + .reset_sda_pin = GPIO_LPI2C7_SDA_RESET, +#endif +#ifndef CONFIG_I2C_SLAVE + .mode = LPI2C_MASTER, +#else + .mode = LPI2C_SLAVE, +#endif +#ifndef CONFIG_I2C_POLLED + .irq = IMX9_IRQ_LPI2C7, +#endif +#ifdef CONFIG_IMX9_LPI2C7_DMA + .dma_rxreqsrc = DMA_REQUEST_MUXLPI2C7RX, + .dma_txreqsrc = DMA_REQUEST_MUXLPI2C7TX, +#endif +}; + +static struct imx9_lpi2c_priv_s imx9_lpi2c7_priv = +{ + .ops = &imx9_lpi2c_ops, + .config = &imx9_lpi2c7_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +#ifdef CONFIG_IMX9_LPI2C8 +static const struct imx9_lpi2c_config_s imx9_lpi2c8_config = +{ + .base = IMX9_LPI2C8_BASE, + .clk_root = CCM_CR_LPI2C8, + .clk_gate = CCM_LPCG_LPI2C8, + .busy_idle = CONFIG_IMX9_LPI2C8_BUSYIDLE, + .filtscl = CONFIG_IMX9_LPI2C8_FILTSCL, + .filtsda = CONFIG_IMX9_LPI2C8_FILTSDA, + .scl_pin = MUX_LPI2C8_SCL, + .sda_pin = MUX_LPI2C8_SDA, +#if defined(CONFIG_I2C_RESET) + .reset_scl_pin = GPIO_LPI2C8_SCL_RESET, + .reset_sda_pin = GPIO_LPI2C8_SDA_RESET, +#endif +#ifndef CONFIG_I2C_SLAVE + .mode = LPI2C_MASTER, +#else + .mode = LPI2C_SLAVE, +#endif +#ifndef CONFIG_I2C_POLLED + .irq = IMX9_IRQ_LPI2C8, +#endif +#ifdef CONFIG_IMX9_LPI2C8_DMA + .dma_rxreqsrc = DMA_REQUEST_MUXLPI2C8RX, + .dma_txreqsrc = DMA_REQUEST_MUXLPI2C8TX, +#endif +}; + +static struct imx9_lpi2c_priv_s imx9_lpi2c8_priv = +{ + .ops = &imx9_lpi2c_ops, + .config = &imx9_lpi2c8_config, + .refs = 0, + .lock = NXMUTEX_INITIALIZER, +#ifndef CONFIG_I2C_POLLED + .sem_isr = SEM_INITIALIZER(0), +#endif + .intstate = INTSTATE_IDLE, + .msgc = 0, + .msgv = NULL, + .ptr = NULL, + .dcnt = 0, + .flags = 0, + .status = 0 +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_lpi2c_getreg + * + * Description: + * Get a 32-bit register value by offset + * + ****************************************************************************/ + +static inline uint32_t +imx9_lpi2c_getreg(struct imx9_lpi2c_priv_s *priv, uint16_t offset) +{ + return getreg32(priv->config->base + offset); +} + +/**************************************************************************** + * Name: imx9_lpi2c_putreg + * + * Description: + * Put a 32-bit register value by offset + * + ****************************************************************************/ + +static inline void imx9_lpi2c_putreg(struct imx9_lpi2c_priv_s *priv, + uint16_t offset, uint32_t value) +{ + putreg32(value, priv->config->base + offset); +} + +/**************************************************************************** + * Name: imx9_lpi2c_modifyreg + * + * Description: + * Modify a 32-bit register value by offset + * + ****************************************************************************/ + +static inline void imx9_lpi2c_modifyreg(struct imx9_lpi2c_priv_s *priv, + uint16_t offset, uint32_t clearbits, + uint32_t setbits) +{ + modifyreg32(priv->config->base + offset, clearbits, setbits); +} + +/**************************************************************************** + * Name: imx9_lpi2c_toticks + * + * Description: + * Return a micro-second delay based on the number of bytes left to be + * processed. + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPI2C_DYNTIMEO +static uint32_t imx9_lpi2c_toticks(int msgc, struct i2c_msg_s *msgs) +{ + int i; + size_t bytecount = 0; + uint32_t tick = 0; + + /* Count the number of bytes left to process */ + + for (i = 0; i < msgc; i++) + { + bytecount += msgs[i].length; + } + + /* Then return a number of microseconds based on a user provided scaling + * factor. + */ + + tick = USEC2TICK(CONFIG_IMX9_LPI2C_DYNTIMEO_USECPERBYTE * bytecount); + if (tick == 0) + { + tick = 1; + } + + return tick; +} +#endif + +/**************************************************************************** + * Name: imx9_lpi2c_sem_waitdone + * + * Description: + * Wait for a transfer to complete + * + ****************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +static inline int +imx9_lpi2c_sem_waitdone(struct imx9_lpi2c_priv_s *priv) +{ + irqstate_t flags; + uint32_t regval; + int ret; + + flags = enter_critical_section(); + +#ifdef CONFIG_IMX9_LPI2C_DMA + if (priv->rxdma == NULL && priv->txdma == NULL) + { +#endif + /* Clear the TX and RX FIFOs */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCR_OFFSET, 0, + LPI2C_MCR_RTF | LPI2C_MCR_RRF); + + /* Enable Interrupts when master mode */ + + if (priv->config->mode == LPI2C_MASTER) + { + if ((priv->flags & I2C_M_READ) != 0) + { + regval = LPI2C_MIER_TDIE | LPI2C_MIER_RDIE | + LPI2C_MIER_NDIE | LPI2C_MIER_ALIE | + LPI2C_MIER_SDIE; + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MIER_OFFSET, regval); + } + else + { + regval = LPI2C_MIER_TDIE | LPI2C_MIER_NDIE | + LPI2C_MIER_ALIE | LPI2C_MIER_SDIE; + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MIER_OFFSET, regval); + } + } + +#ifdef CONFIG_I2C_SLAVE + /* Enable Interrupts when slave mode */ + + else + { + /* REVISIT: Slave mode has not been implemented */ + } +#endif + +#ifdef CONFIG_IMX9_LPI2C_DMA + } +#endif + + do + { + /* Wait until either the transfer is complete or the timeout expires */ + +#ifdef CONFIG_IMX9_LPI2C_DYNTIMEO + ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, + imx9_lpi2c_toticks(priv->msgc, priv->msgv)); +#else + ret = nxsem_tickwait_uninterruptible(&priv->sem_isr, + CONFIG_IMX9_LPI2C_TIMEOTICKS); +#endif + if (ret < 0) + { + /* Break out of the loop on irrecoverable errors. This would + * include timeouts and mystery errors reported by + * nxsem_tickwait_uninterruptible. + */ + + break; + } + } + + /* Loop until the interrupt level transfer is complete. */ + + while (priv->intstate != INTSTATE_DONE); + + /* Set the interrupt state back to IDLE */ + + priv->intstate = INTSTATE_IDLE; + + /* Disable I2C interrupts */ + + if (priv->config->mode == LPI2C_MASTER) + { + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MIER_OFFSET, 0); + } + else + { + imx9_lpi2c_putreg(priv, IMX9_LPI2C_SIER_OFFSET, 0); + } + + leave_critical_section(flags); + return ret; +} +#else +static inline int +imx9_lpi2c_sem_waitdone(struct imx9_lpi2c_priv_s *priv) +{ + clock_t timeout; + clock_t start; + clock_t elapsed; + int ret; + + /* Get the timeout value */ + +#ifdef CONFIG_IMX9_LPI2C_DYNTIMEO + timeout = imx9_lpi2c_toticks(priv->msgc, priv->msgv); +#else + timeout = CONFIG_IMX9_LPI2C_TIMEOTICKS; +#endif + start = clock_systime_ticks(); + + do + { + /* Calculate the elapsed time */ + + elapsed = clock_systime_ticks() - start; + + /* Poll by simply calling the timer interrupt handler until it + * reports that it is done. + */ + + imx9_lpi2c_isr_process(priv); + } + + /* Loop until the transfer is complete. */ + + while (priv->intstate != INTSTATE_DONE && elapsed < timeout); + + i2cinfo("intstate: %d elapsed: %ld threshold: %ld status: %08x\n", + priv->intstate, (long)elapsed, (long)timeout, priv->status); + + /* Set the interrupt state back to IDLE */ + + ret = priv->intstate == INTSTATE_DONE ? OK : -ETIMEDOUT; + priv->intstate = INTSTATE_IDLE; + return ret; +} +#endif + +/**************************************************************************** + * Name: imx9_lpi2c_sem_waitstop + * + * Description: + * Wait for a STOP to complete + * + ****************************************************************************/ + +static inline void +imx9_lpi2c_sem_waitstop(struct imx9_lpi2c_priv_s *priv) +{ + clock_t start; + clock_t elapsed; + clock_t timeout; + uint32_t regval; + + /* Select a timeout */ + +#ifdef CONFIG_IMX9_LPI2C_DYNTIMEO + timeout = USEC2TICK(CONFIG_IMX9_LPI2C_DYNTIMEO_STARTSTOP); +#else + timeout = CONFIG_IMX9_LPI2C_TIMEOTICKS; +#endif + + /* Wait as stop might still be in progress; but stop might also + * be set because of a timeout error: "The [STOP] bit is set and + * cleared by software, cleared by hardware when a Stop condition is + * detected, set by hardware when a timeout error is detected." + */ + + start = clock_systime_ticks(); + do + { + /* Calculate the elapsed time */ + + elapsed = clock_systime_ticks() - start; + + /* Check for STOP condition */ + + if (priv->config->mode == LPI2C_MASTER) + { + regval = imx9_lpi2c_getreg(priv, IMX9_LPI2C_MSR_OFFSET); + if ((regval & LPI2C_MSR_SDF) == LPI2C_MSR_SDF) + { + return; + } + } + + /* Enable Interrupts when slave mode */ + + else + { + regval = imx9_lpi2c_getreg(priv, IMX9_LPI2C_SSR_OFFSET); + if ((regval & LPI2C_SSR_SDF) == LPI2C_SSR_SDF) + { + return; + } + } + + /* Check for NACK error */ + + if (priv->config->mode == LPI2C_MASTER) + { + regval = imx9_lpi2c_getreg(priv, IMX9_LPI2C_MSR_OFFSET); + if ((regval & LPI2C_MSR_NDF) == LPI2C_MSR_NDF) + { + return; + } + } + +#ifdef CONFIG_I2C_SLAVE + /* Enable Interrupts when slave mode */ + + else + { + /* REVISIT: Slave mode has not been implemented */ + } +#endif + } + + /* Loop until the stop is complete or a timeout occurs. */ + + while (elapsed < timeout); + + /* If we get here then a timeout occurred with the STOP condition + * still pending. + */ + + i2cinfo("Timeout with Status Register: %" PRIx32 "\n", regval); +} + +/**************************************************************************** + * Name: imx9_rxdma_callback + * + * Description: + * This function performs the next I2C operation + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPI2C_DMA +static void imx9_rxdma_callback(DMACH_HANDLE handle, void *arg, bool done, + int result) +{ + struct imx9_lpi2c_priv_s *priv = (struct imx9_lpi2c_priv_s *)arg; + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MIER_OFFSET, 0, + LPI2C_MIER_SDIE); + + if (result == OK) + { + if ((priv->flags & I2C_M_NOSTOP) == 0) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_STOP, 0); + imx9_lpi2c_sendstop(priv); + } + } + else + { + uint32_t status = imx9_lpi2c_getstatus(priv); + + if ((status & LPI2C_MSR_ERROR_MASK) != 0) + { + i2cerr("ERROR: MSR: status: 0x0%" PRIx32 "\n", status); + + imx9_lpi2c_traceevent(priv, I2CEVENT_ERROR, 0); + } + } +} +#endif + +/**************************************************************************** + * Name: imx9_txdma_callback + * + * Description: + * This function performs the next I2C operation + * + ****************************************************************************/ +#ifdef CONFIG_IMX9_LPI2C_DMA +static void imx9_txdma_callback(DMACH_HANDLE handle, void *arg, bool done, + int result) +{ + struct imx9_lpi2c_priv_s *priv = (struct imx9_lpi2c_priv_s *)arg; + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MIER_OFFSET, 0, + LPI2C_MIER_SDIE); + + if (result == OK) + { + if ((priv->flags & I2C_M_NOSTOP) == 0) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_STOP, 0); + imx9_lpi2c_sendstop(priv); + } + } + else + { + uint32_t status = imx9_lpi2c_getstatus(priv); + + if ((status & LPI2C_MSR_ERROR_MASK) != 0) + { + i2cerr("ERROR: MSR: status: 0x0%" PRIx32 "\n", status); + + imx9_lpi2c_traceevent(priv, I2CEVENT_ERROR, 0); + } + } +} +#endif + +/**************************************************************************** + * Name: imx9_lpi2c_trace* + * + * Description: + * I2C trace instrumentation + * + ****************************************************************************/ + +#ifdef CONFIG_I2C_TRACE +static void imx9_lpi2c_traceclear(struct imx9_lpi2c_priv_s *priv) +{ + struct imx9_trace_s *trace = &priv->trace[priv->tndx]; + + trace->status = 0; /* I2C 32-bit SR2|SR1 status */ + trace->count = 0; /* Interrupt count when status change */ + trace->event = I2CEVENT_NONE; /* Last event that occurred with this status */ + trace->parm = 0; /* Parameter associated with the event */ + trace->time = 0; /* Time of first status or event */ +} + +static void imx9_lpi2c_tracereset(struct imx9_lpi2c_priv_s *priv) +{ + /* Reset the trace info for a new data collection */ + + priv->tndx = 0; + priv->start_time = clock_systime_ticks(); + imx9_lpi2c_traceclear(priv); +} + +static void imx9_lpi2c_tracenew(struct imx9_lpi2c_priv_s *priv, + uint32_t status) +{ + struct imx9_trace_s *trace = &priv->trace[priv->tndx]; + + /* Is the current entry uninitialized? Has the status changed? */ + + if (trace->count == 0 || status != trace->status) + { + /* Yes.. Was it the status changed? */ + + if (trace->count != 0) + { + /* Yes.. bump up the trace index (unless out of trace entries) */ + + if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) + { + i2cerr("ERROR: Trace table overflow\n"); + return; + } + + priv->tndx++; + trace = &priv->trace[priv->tndx]; + } + + /* Initialize the new trace entry */ + + imx9_lpi2c_traceclear(priv); + trace->status = status; + trace->count = 1; + trace->time = clock_systime_ticks(); + } + else + { + /* Just increment the count of times that we have seen this status */ + + trace->count++; + } +} + +static void imx9_lpi2c_traceevent(struct imx9_lpi2c_priv_s *priv, + enum imx9_trace_e event, uint32_t parm) +{ + struct imx9_trace_s *trace; + + if (event != I2CEVENT_NONE) + { + trace = &priv->trace[priv->tndx]; + + /* Initialize the new trace entry */ + + trace->event = event; + trace->parm = parm; + + /* Bump up the trace index (unless we are out of trace entries) */ + + if (priv->tndx >= (CONFIG_I2C_NTRACE - 1)) + { + i2cerr("ERROR: Trace table overflow\n"); + return; + } + + priv->tndx++; + imx9_lpi2c_traceclear(priv); + } +} + +static void imx9_lpi2c_tracedump(struct imx9_lpi2c_priv_s *priv) +{ + struct imx9_trace_s *trace; + int i; + + syslog(LOG_DEBUG, "Elapsed time: %ld\n", + (long)(clock_systime_ticks() - priv->start_time)); + + for (i = 0; i < priv->tndx; i++) + { + trace = &priv->trace[i]; + syslog(LOG_DEBUG, + "%2d. STATUS: %08x COUNT: %3d EVENT: %s(%2d) PARM: %08x " + "TIME: %d\n", + i + 1, trace->status, trace->count, + g_trace_names[trace->event], + trace->event, trace->parm, trace->time - priv->start_time); + } +} +#endif /* CONFIG_I2C_TRACE */ + +/**************************************************************************** + * Name: imx9_lpi2c_setclock + * + * Description: + * Set the I2C clock + * + ****************************************************************************/ + +static void imx9_lpi2c_setclock(struct imx9_lpi2c_priv_s *priv, + uint32_t frequency) +{ + uint32_t src_freq = 0; + uint32_t regval; + uint32_t men; + uint32_t prescale = 0; + uint32_t best_prescale = 0; + uint32_t best_clk_hi = 0; + uint32_t abs_error = 0; + uint32_t best_error = 0xffffffff; + uint32_t clk_hi_cycle; + uint32_t computed_rate; + uint32_t count; + + /* Has the I2C bus frequency changed? */ + + if (priv->config->mode == LPI2C_MASTER) + { + if (frequency != priv->frequency) + { + /* Disable the selected LPI2C peripheral to configure the new + * clock if it is enabled. + */ + + men = imx9_lpi2c_getreg(priv, IMX9_LPI2C_MCR_OFFSET) & + LPI2C_MCR_MEN; + if (men) + { + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCR_OFFSET, + LPI2C_MCR_MEN, 0); + } + + /* Get the LPI2C clock source frequency */ + + imx9_get_rootclock(priv->config->clk_root, &src_freq); + + /* LPI2C output frequency = (Source Clock (Hz)/ 2^prescale) / + * (CLKLO + 1 + CLKHI + 1 + ROUNDDOWN((2 + FILTSCL) / 2^prescale) + * + * Assume CLKLO = 2 * CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI / 2 + */ + + for (prescale = 1; + (prescale <= 128) && (best_error != 0); + prescale *= 2) + { + for (clk_hi_cycle = 1; clk_hi_cycle < 32; clk_hi_cycle++) + { + if (clk_hi_cycle == 1) + { + computed_rate = (src_freq / prescale) / + (6 + (2 / prescale)); + } + else + { + computed_rate = (src_freq / prescale) / + ((3 * clk_hi_cycle + 2) + + (2 / prescale)); + } + + if (frequency > computed_rate) + { + abs_error = frequency - computed_rate; + } + else + { + abs_error = computed_rate - frequency; + } + + if (abs_error < best_error) + { + best_prescale = prescale; + best_clk_hi = clk_hi_cycle; + best_error = abs_error; + + if (abs_error == 0) + { + break; + } + } + } + } + + regval = LPI2C_MCCR0_CLKHI(best_clk_hi); + + if (best_clk_hi < 2) + { + regval |= LPI2C_MCCR0_CLKLO(3) | LPI2C_MCCR0_SETHOLD(2) | + LPI2C_MCCR0_DATAVD(1); + } + else + { + regval |= LPI2C_MCCR0_CLKLO(2 * best_clk_hi) | + LPI2C_MCCR0_SETHOLD(best_clk_hi) | + LPI2C_MCCR0_DATAVD(best_clk_hi / 2); + } + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MCCR0_OFFSET, regval); + + for (count = 0; count < 8; count++) + { + if (best_prescale == (1 << count)) + { + best_prescale = count; + break; + } + } + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCFGR1_OFFSET, + LPI2C_MCFGR1_PRESCALE_MASK, + LPI2C_MCFGR1_PRESCALE(best_prescale)); + + /* Re-enable LPI2C if it was enabled previously */ + + if (men) + { + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCR_OFFSET, 0, + LPI2C_MCR_MEN); + } + + /* Save the new LPI2C frequency */ + + priv->frequency = frequency; + } + } +} + +/**************************************************************************** + * Name: imx9_lpi2c_sendstart + * + * Description: + * Send the START conditions/force Master mode + * + ****************************************************************************/ + +static inline void imx9_lpi2c_sendstart(struct imx9_lpi2c_priv_s *priv, + uint8_t address) +{ + uint32_t txcount = 0; + uint32_t status = 0; + uint8_t addr; + + /* Generate START condition and send the address */ + + /* Disable AUTOSTOP and turn NAK Ignore off */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCFGR1_OFFSET, + LPI2C_MCFGR1_IGNACK | LPI2C_MCFGR1_AUTOSTOP, 0); + + do + { + txcount = (imx9_lpi2c_getreg(priv, IMX9_LPI2C_MFSR_OFFSET) & + LPI2C_MFSR_TXCOUNT_MASK) >> LPI2C_MFSR_TXCOUNT_SHIFT; + txcount = 4 - txcount; + + status = imx9_lpi2c_getreg(priv, IMX9_LPI2C_MSR_OFFSET); + + if (status & LPI2C_MSR_ERROR_MASK) + { + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MSR_OFFSET, + status & LPI2C_MSR_ERROR_MASK); + } + } + while (txcount == 0); + + if ((priv->flags & I2C_M_READ) != 0) + { + addr = I2C_READADDR8(address); + } + else + { + addr = I2C_WRITEADDR8(address); + } + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MTDR_OFFSET, + (LPI2C_MTDR_CMD_START | LPI2C_MTDR_DATA(addr))); +} + +/**************************************************************************** + * Name: imx9_lpi2c_sendstop + * + * Description: + * Send the STOP conditions + * + ****************************************************************************/ + +static inline void imx9_lpi2c_sendstop(struct imx9_lpi2c_priv_s *priv) +{ + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MTDR_OFFSET, LPI2C_MTDR_CMD_STOP); +} + +/**************************************************************************** + * Name: imx9_lpi2c_getstatus + * + * Description: + * Get 32-bit status + * + ****************************************************************************/ + +static inline uint32_t +imx9_lpi2c_getstatus(struct imx9_lpi2c_priv_s *priv) +{ + return imx9_lpi2c_getreg(priv, IMX9_LPI2C_MSR_OFFSET); +} + +/**************************************************************************** + * Name: imx9_lpi2c_getenabledints + * + * Description: + * Get 32-bit status + * + ****************************************************************************/ + +static inline uint32_t +imx9_lpi2c_getenabledints(struct imx9_lpi2c_priv_s *priv) +{ + return imx9_lpi2c_getreg(priv, IMX9_LPI2C_MIER_OFFSET); +} + +/**************************************************************************** + * Name: imx9_lpi2c_isr_process + * + * Description: + * Common Interrupt Service Routine + * + ****************************************************************************/ + +static int imx9_lpi2c_isr_process(struct imx9_lpi2c_priv_s *priv) +{ + uint32_t status = imx9_lpi2c_getstatus(priv); + +#ifdef CONFIG_IMX9_LPI2C_DMA + uint32_t current_status = status; + + if (priv->rxdma != NULL || priv->txdma != NULL) + { + /* Condition the status with only the enabled interrupts */ + + status &= imx9_lpi2c_getenabledints(priv); + + /* Is there an Error condition */ + + if (current_status & LPI2C_MSR_LIMITED_ERROR_MASK) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_ERROR, 0); + + /* Return the full error status */ + + priv->status = current_status; + } + + /* End of packet or Stop */ + + if ((status & (LPI2C_MSR_SDF | LPI2C_MSR_EPF)) != 0) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_STOP, 0); + + /* Acknowledge End of packet or Stop */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MSR_OFFSET, status & + (LPI2C_MSR_SDF | + LPI2C_MSR_EPF)); + + /* Mark that this transaction stopped */ + + priv->msgv = NULL; + priv->msgc = 0; + priv->dcnt = -1; + + if (priv->intstate == INTSTATE_WAITING) + { + /* inform the thread that transfer is complete + * and wake it up + */ + + imx9_dmach_stop(priv->txdma); + imx9_dmach_stop(priv->rxdma); + + priv->intstate = INTSTATE_DONE; + nxsem_post(&priv->sem_isr); + } + } + + /* Clear the error */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MSR_OFFSET, + (current_status & (LPI2C_MSR_NDF | + LPI2C_MSR_ALF | + LPI2C_MSR_FEF))); + return OK; + } + +#endif + /* Check for new trace setup */ + + imx9_lpi2c_tracenew(priv, status); + + if ((status & LPI2C_MSR_LIMITED_ERROR_MASK) == 0) + { + /* Check if there is more bytes to send */ + + if (((priv->flags & I2C_M_READ) == 0) && + (status & LPI2C_MSR_TDF) != 0) + { + if (priv->dcnt > 0) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_SENDBYTE, priv->dcnt); + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MTDR_OFFSET, + LPI2C_MTDR_CMD_TXD | + LPI2C_MTDR_DATA(*priv->ptr++)); + priv->dcnt--; + + /* Last byte of last message? */ + + if ((priv->msgc <= 0) && (priv->dcnt == 0)) + { + if ((priv->flags & I2C_M_NOSTOP) == 0) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_STOP, 0); + + /* Do this once */ + + priv->flags |= I2C_M_NOSTOP; + imx9_lpi2c_sendstop(priv); + } + } + } + } + + /* Check if there is more bytes to read */ + + else if (((priv->flags & I2C_M_READ) != 0) && + (status & LPI2C_MSR_RDF) != 0) + { + /* Read a byte, if dcnt goes < 0, read dummy bytes to ack ISRs */ + + if (priv->dcnt > 0) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt); + + /* No interrupts or context switches should occur in the + * following sequence. Otherwise, additional bytes may be + * sent by the device. + */ + + #ifdef CONFIG_I2C_POLLED + irqstate_t flags = enter_critical_section(); + #endif + + /* Receive a byte */ + + *priv->ptr++ = imx9_lpi2c_getreg(priv, + IMX9_LPI2C_MRDR_OFFSET) & + LPI2C_MRDR_DATA_MASK; + priv->dcnt--; + + #ifdef CONFIG_I2C_POLLED + leave_critical_section(flags); + #endif + /* Last byte of last message? */ + + if ((priv->msgc <= 0) && (priv->dcnt == 0)) + { + if ((priv->flags & I2C_M_NOSTOP) == 0) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_STOP, 0); + + /* Do this once */ + + priv->flags |= I2C_M_NOSTOP; + imx9_lpi2c_sendstop(priv); + } + } + } + else + { + /* Read and discard data */ + + imx9_lpi2c_getreg(priv, IMX9_LPI2C_MRDR_OFFSET); + } + } + + /* Start the first or next message */ + + if (priv->dcnt <= 0 && (status & (LPI2C_MSR_EPF | LPI2C_MSR_SDF)) == 0) + { + if (priv->msgc > 0 && priv->msgv != NULL) + { + priv->ptr = priv->msgv->buffer; + priv->dcnt = priv->msgv->length; + priv->flags = priv->msgv->flags; + + if ((priv->flags & I2C_M_NOSTART) == 0) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_STARTRESTART, + priv->msgc); + + /* Do this once */ + + priv->flags |= I2C_M_NOSTART; + + imx9_lpi2c_sendstart(priv, priv->msgv->addr); + } + else + { + imx9_lpi2c_traceevent(priv, I2CEVENT_NOSTART, priv->msgc); + } + + priv->msgv++; + priv->msgc--; + + if ((priv->flags & I2C_M_READ) != 0) + { +#ifndef CONFIG_I2C_POLLED + /* Stop TX interrupt */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MIER_OFFSET, + LPI2C_MIER_TDIE, LPI2C_MIER_RDIE); +#endif + /* Set LPI2C in read mode */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MTDR_OFFSET, + LPI2C_MTDR_CMD_RXD | + LPI2C_MTDR_DATA((priv->dcnt - 1))); + } + else + { + /* Send the first byte from tx buffer */ + + imx9_lpi2c_traceevent(priv, I2CEVENT_SENDBYTE, + priv->dcnt); + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MTDR_OFFSET, + LPI2C_MTDR_CMD_TXD | + LPI2C_MTDR_DATA(*priv->ptr++)); + priv->dcnt--; + + /* Last byte of last message? */ + + if ((priv->msgc <= 0) && (priv->dcnt == 0)) + { + if ((priv->flags & I2C_M_NOSTOP) == 0) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_STOP, 0); + + /* Do this once */ + + priv->flags |= I2C_M_NOSTOP; + imx9_lpi2c_sendstop(priv); + } + } + } + } + } + } + else + { + imx9_lpi2c_traceevent(priv, I2CEVENT_ERROR, 0); + + priv->status = status; + + if ((priv->flags & I2C_M_NOSTOP) == 0) + { + imx9_lpi2c_traceevent(priv, I2CEVENT_STOP, 0); + + /* Do this once */ + + priv->flags |= I2C_M_NOSTOP; + imx9_lpi2c_sendstop(priv); + } + + /* Clear the error */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MSR_OFFSET, + (status & (LPI2C_MSR_NDF | LPI2C_MSR_ALF | + LPI2C_MSR_FEF | LPI2C_MSR_EPF))); + } + + /* Check for endof packet or Stop */ + + if ((status & (LPI2C_MSR_EPF | LPI2C_MSR_SDF)) != 0) + { + /* Reset either or both */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MSR_OFFSET, status & + (LPI2C_MSR_EPF | LPI2C_MSR_SDF)); + + /* Was it both End of packet and Stop */ + + if ((status & (LPI2C_MSR_EPF | LPI2C_MSR_SDF)) == + (LPI2C_MSR_EPF | LPI2C_MSR_SDF)) + { +#ifndef CONFIG_I2C_POLLED + if (priv->intstate == INTSTATE_WAITING) + { + /* inform the thread that transfer is complete + * and wake it up + */ + + priv->intstate = INTSTATE_DONE; + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MIER_OFFSET, + LPI2C_MIER_TDIE | LPI2C_MIER_RDIE | + LPI2C_MIER_NDIE | LPI2C_MIER_ALIE | + LPI2C_MIER_SDIE | LPI2C_MIER_EPIE, 0); + nxsem_post(&priv->sem_isr); + } +#else + priv->intstate = INTSTATE_DONE; +#endif + } + } + + return OK; +} + +/**************************************************************************** + * Name: imx9_lpi2c_isr + * + * Description: + * Common I2C interrupt service routine + * + ****************************************************************************/ + +#ifndef CONFIG_I2C_POLLED +static int imx9_lpi2c_isr(int irq, void *context, void *arg) +{ + struct imx9_lpi2c_priv_s *priv = (struct imx9_lpi2c_priv_s *)arg; + + DEBUGASSERT(priv != NULL); + return imx9_lpi2c_isr_process(priv); +} +#endif + +/**************************************************************************** + * Name: imx9_lpi2c_clock_enable + * + * Description: + * Ungate LPI2C clock + * + ****************************************************************************/ + +static void imx9_lpi2c_clock_enable(struct imx9_lpi2c_priv_s *priv) +{ + imx9_ccm_gate_on(priv->config->clk_gate, true); +} + +/**************************************************************************** + * Name: imx9_lpi2c_clock_disable + * + * Description: + * Gate LPI2C clock + * + ****************************************************************************/ + +void imx9_lpi2c_clock_disable(struct imx9_lpi2c_priv_s *priv) +{ + imx9_ccm_gate_on(priv->config->clk_gate, false); +} + +/**************************************************************************** + * Name: imx9_lpi2c_init + * + * Description: + * Setup the I2C hardware, ready for operation with defaults + * + ****************************************************************************/ + +static int imx9_lpi2c_init(struct imx9_lpi2c_priv_s *priv) +{ + /* Power-up and configure GPIOs */ + + /* Configure pins */ + + imx9_iomux_configure(priv->config->scl_pin); + imx9_iomux_configure(priv->config->sda_pin); + + /* Enable power and reset the peripheral */ + + imx9_lpi2c_clock_enable(priv); + + /* Reset LPI2C before configuring it */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MCR_OFFSET, LPI2C_MCR_RST); + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MCR_OFFSET, 0); + + /* Disable doze mode (Set DOZEN bit in 1 to disable) */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MCR_OFFSET, LPI2C_MCR_DOZEN); + + /* Disable host request */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCFGR0_OFFSET, + LPI2C_MCFG0_HREN | LPI2C_MCFG0_HRSEL, + LPI2C_MCFG0_HRPOL); + + /* Disable AUTOSTOP and turn NAK Ignore off */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCFGR1_OFFSET, + LPI2C_MCFGR1_IGNACK | LPI2C_MCFGR1_AUTOSTOP, 0); + + /* Set tx and rx watermarks */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MFCR_OFFSET, + LPI2C_MFCR_TXWATER(0) | LPI2C_MFCR_RXWATER(0)); + + /* Force a frequency update */ + + priv->frequency = 0; + imx9_lpi2c_setclock(priv, 100000); + + /* Set scl, sda glitch filters and busy idle */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MCFGR2_OFFSET, + LPI2C_MCFG2_BUSIDLE(priv->config->busy_idle) | + LPI2C_MCFG2_FILTSCL_CYCLES(priv->config->filtscl) | + LPI2C_MCFG2_FILTSDA_CYCLES(priv->config->filtsda)); + + /* Set pin low cycles to 0 (disable) */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MCFGR3_OFFSET, + LPI2C_MCFG3_PINLOW_CYCLES(0)); + + /* Attach ISRs */ + +#ifndef CONFIG_I2C_POLLED + irq_attach(priv->config->irq, imx9_lpi2c_isr, priv); + up_enable_irq(priv->config->irq); +#endif + + /* Enable I2C */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCR_OFFSET, 0, LPI2C_MCR_MEN); + return OK; +} + +/**************************************************************************** + * Name: imx9_lpi2c_deinit + * + * Description: + * Shutdown the I2C hardware + * + ****************************************************************************/ + +static int imx9_lpi2c_deinit(struct imx9_lpi2c_priv_s *priv) +{ + /* Disable I2C */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCR_OFFSET, LPI2C_MCR_MEN, 0); + + /* Reset LPI2C */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MCR_OFFSET, LPI2C_MCR_RST); + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MCR_OFFSET, 0); + + /* Disable and detach interrupts */ + +#ifndef CONFIG_I2C_POLLED + up_disable_irq(priv->config->irq); + irq_detach(priv->config->irq); +#endif + + /* Disable clocking */ + + imx9_lpi2c_clock_disable(priv); + + return OK; +} + +/**************************************************************************** + * Device Driver Operations + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_lpi2c_dma_command_configure + * + * Description: + * Create a command TCD + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPI2C_DMA +static int imx9_lpi2c_dma_command_configure(struct imx9_lpi2c_priv_s *priv, + uint16_t *ccmd, uint32_t ncmd) +{ + struct imx9_edma_xfrconfig_s config; + memset(&config, 0, sizeof(config)); + + config.saddr = (uintptr_t) ccmd; + config.daddr = priv->config->base + IMX9_LPI2C_MTDR_OFFSET; + config.soff = sizeof(uint16_t); + config.doff = 0; + config.iter = 1; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE; + config.ssize = EDMA_16BIT; + config.dsize = EDMA_16BIT; + config.nbytes = sizeof(uint16_t) * ncmd; + + up_clean_dcache((uintptr_t)config.saddr, + (uintptr_t)config.saddr + config.nbytes); + + return imx9_dmach_xfrsetup(priv->txdma, &config); +} +#endif + +/**************************************************************************** + * Name: imx9_lpi2c_dma_data_configure + * + * Description: + * Create a data TCD + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPI2C_DMA +static int imx9_lpi2c_dma_data_configure(struct imx9_lpi2c_priv_s *priv, + struct i2c_msg_s *msg) +{ + DMACH_HANDLE dma; + struct imx9_edma_xfrconfig_s config; + memset(&config, 0, sizeof(config)); + + config.iter = msg->length; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE; + config.ssize = EDMA_8BIT; + config.dsize = EDMA_8BIT; + config.nbytes = sizeof(msg->buffer[0]); + + if (msg->flags & I2C_M_READ) + { + dma = priv->rxdma; + config.saddr = priv->config->base + IMX9_LPI2C_MRDR_OFFSET; + config.daddr = (uintptr_t) msg->buffer; + config.soff = 0; + config.doff = sizeof(msg->buffer[0]); + up_invalidate_dcache((uintptr_t)msg->buffer, + (uintptr_t)msg->buffer + msg->length); + } + else + { + dma = priv->txdma; + config.saddr = (uintptr_t) msg->buffer; + config.daddr = priv->config->base + IMX9_LPI2C_MTDR_OFFSET; + config.soff = sizeof(msg->buffer[0]); + config.doff = 0; + up_clean_dcache((uintptr_t)msg->buffer, + (uintptr_t)msg->buffer + msg->length); + } + + return imx9_dmach_xfrsetup(dma, &config) ? 0 : msg->length; +} +#endif + +/**************************************************************************** + * Name: imx9_lpi2c_form_command_list + * + * Description: + * Form the DMA command list + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPI2C_DMA +static int imx9_lpi2c_form_command_list(struct imx9_lpi2c_priv_s *priv, + struct i2c_msg_s *msg, int ncmds) +{ + ssize_t length = 0; + + if (priv->flags & I2C_M_NOSTART) + { + if (priv->flags & I2C_M_READ) + { + /* No start read operation */ + + priv->cmnds[ncmds++] = LPI2C_MTDR_CMD_RXD | + LPI2C_MTDR_DATA(msg->length - 1); + } + } + else + { + /* A start based read or write operation */ + + /* Create bus address with R/W */ + + uint16_t badd = (priv->flags & I2C_M_READ) ? I2C_READADDR8(msg->addr) : + I2C_WRITEADDR8(msg->addr); + + priv->cmnds[ncmds++] = LPI2C_MTDR_CMD_START | LPI2C_MTDR_DATA(badd); + + if (badd & I2C_READBIT) + { + length = msg->length; + while (length) + { + if (length > 256u) + { + priv->cmnds[ncmds++] = LPI2C_MTDR_CMD_RXD | + LPI2C_MTDR_DATA(256u - 1); + length -= 256u; + } + else + { + priv->cmnds[ncmds++] = LPI2C_MTDR_CMD_RXD | + LPI2C_MTDR_DATA(length - 1); + length = 0; + } + } + } + } + + return ncmds; +} +#endif + +/**************************************************************************** + * Name: imx9_lpi2c_dma_transfer + * + * Description: + * DMA based I2C transfer function + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPI2C_DMA +static int imx9_lpi2c_dma_transfer(struct imx9_lpi2c_priv_s *priv) +{ + int m; + int ntotcmds = 0; + int ncmds = 0; + uint16_t *ccmnd = NULL; + + /* Disable Interrupts */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MIER_OFFSET, 0); + + /* Disable DMA */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MDER_OFFSET, LPI2C_MDER_TDDE | + LPI2C_MDER_RDDE, 0); + + /* Enable AUTOSTOP and NAK Ignore */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCFGR1_OFFSET, 0, + LPI2C_MCFGR1_IGNACK | LPI2C_MCFGR1_AUTOSTOP); + + /* Form chains of TCDs to process the messages */ + + for (m = 0; m < priv->msgc; m++) + { + ncmds = 0; + priv->flags = priv->msgv[m].flags; + + /* Form a command list */ + + ccmnd = &priv->cmnds[ntotcmds]; + + ncmds = imx9_lpi2c_form_command_list(priv, &priv->msgv[m], ntotcmds); + + /* Have commands for this message ? */ + + if (ncmds != 0) + { + /* Build up a TCD with the command from this message */ + + imx9_lpi2c_dma_command_configure(priv, ccmnd, ncmds - ntotcmds); + + ntotcmds += ncmds; + + DEBUGASSERT(ntotcmds < CONFIG_IMX9_LPI2C_DMA_MAXMSG); + + imx9_lpi2c_dma_data_configure(priv, &priv->msgv[m]); + } + } + + /* Clear the TX and RX FIFOs */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MCR_OFFSET, 0, + LPI2C_MCR_RTF | LPI2C_MCR_RRF); + + /* Reset the Error bits */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MSR_OFFSET, LPI2C_MSR_NDF | + LPI2C_MSR_ALF | + LPI2C_MSR_FEF); + + /* Enable the Iterrupts */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MIER_OFFSET, + LPI2C_MIER_NDIE | LPI2C_MIER_ALIE | + LPI2C_MIER_PLTIE); + + /* Start The DMA */ + + imx9_dmach_start(priv->rxdma, imx9_rxdma_callback, (void *)priv); + imx9_dmach_start(priv->txdma, imx9_txdma_callback, (void *)priv); + + /* Enable the DMA Request */ + + imx9_lpi2c_modifyreg(priv, IMX9_LPI2C_MDER_OFFSET, 0, + LPI2C_MDER_TDDE | LPI2C_MDER_RDDE); + return OK; +} +#endif + +/**************************************************************************** + * Name: imx9_lpi2c_transfer + * + * Description: + * Generic I2C transfer function + * + ****************************************************************************/ + +static int imx9_lpi2c_transfer(struct i2c_master_s *dev, + struct i2c_msg_s *msgs, int count) +{ + struct imx9_lpi2c_priv_s *priv = (struct imx9_lpi2c_priv_s *)dev; + int ret; +#ifdef CONFIG_IMX9_LPI2C_DMA + int m; +#endif + + DEBUGASSERT(count > 0); + + /* Ensure that address or flags don't change meanwhile */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + /* Clear any pending error interrupts */ + + imx9_lpi2c_putreg(priv, IMX9_LPI2C_MSR_OFFSET, 0xffffffff); + + /* Old transfers are done */ + + /* Reset ptr and dcnt to ensure an unexpected data interrupt doesn't + * overwrite stale data. + */ + + priv->dcnt = 0; + priv->ptr = NULL; + + priv->msgv = msgs; + priv->msgc = count; + priv->flags = msgs->flags; + + i2cinfo("Flags %x, len %ld\n", msgs->flags, msgs->length); + + /* Reset I2C trace logic */ + + imx9_lpi2c_tracereset(priv); + + /* Set I2C clock frequency */ + + imx9_lpi2c_setclock(priv, msgs->frequency); + + priv->status = 0; + + /* Signal the interrupt handler that we are waiting. NOTE: Interrupts + * are currently disabled but will be temporarily re-enabled below when + * nxsem_tickwait_uninterruptible() sleeps. + */ + + priv->intstate = INTSTATE_WAITING; + + /* Wait for an ISR, if there was a timeout, fetch latest status to get + * the BUSY flag. + */ + +#ifdef CONFIG_IMX9_LPI2C_DMA + if (priv->rxdma || priv->txdma) + { + imx9_lpi2c_dma_transfer(priv); + } +#endif + + if (imx9_lpi2c_sem_waitdone(priv) < 0) + { +#ifdef CONFIG_IMX9_LPI2C_DMA + if (priv->rxdma != NULL) + { + imx9_dmach_stop(priv->rxdma); + } + + if (priv->txdma != NULL) + { + imx9_dmach_stop(priv->txdma); + } + +#endif + ret = -ETIMEDOUT; + i2cerr("ERROR: Timed out: MSR: status: 0x0%" PRIx32 "\n", + priv->status); + } + + /* Check for error status conditions */ + + else if ((priv->status & LPI2C_MSR_ERROR_MASK) != 0) + { + /* I2C_SR1_ERRORMASK is the 'OR' of the following individual bits: */ + + if (priv->status & LPI2C_MSR_ALF) + { + /* Arbitration Lost (master mode) */ + + i2cerr("Arbitration lost\n"); + ret = -EAGAIN; + } + else if (priv->status & LPI2C_MSR_NDF) + { + /* Acknowledge Failure */ + + i2cerr("Ack failure\n"); + ret = -ENXIO; + } + else + { + /* FIFO Error */ + + i2cerr("Transfer without start condition\n"); + ret = -EINVAL; + } + } + + /* Dump the trace result */ + + imx9_lpi2c_tracedump(priv); + + /* Ensure that any ISR happening after we finish can't overwrite any user + * data. + */ + + priv->dcnt = 0; + priv->ptr = NULL; + +#ifdef CONFIG_IMX9_LPI2C_DMA + if (priv->rxdma) + { + for (m = 0; m < count; m++) + { + if (msgs[m].flags & I2C_M_READ) + { + up_invalidate_dcache((uintptr_t)msgs[m].buffer, + (uintptr_t)msgs[m].buffer + + msgs[m].length); + } + } + } +#endif + + nxmutex_unlock(&priv->lock); + return ret; +} + +/**************************************************************************** + * Name: imx9_lpi2c_reset + * + * Description: + * Perform an I2C bus reset in an attempt to break loose stuck I2C devices. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_I2C_RESET +static int imx9_lpi2c_reset(struct i2c_master_s *dev) +{ + struct imx9_lpi2c_priv_s *priv = (struct imx9_lpi2c_priv_s *)dev; + unsigned int clock_count; + unsigned int stretch_count; + uint32_t scl_gpio; + uint32_t sda_gpio; + uint32_t frequency; + int ret; + + DEBUGASSERT(dev); + + /* Our caller must own a ref */ + + DEBUGASSERT(priv->refs > 0); + + /* Lock out other clients */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + ret = -EIO; + + /* Save the current frequency */ + + frequency = priv->frequency; + + /* De-init the port */ + + imx9_lpi2c_deinit(priv); + + /* Use GPIO configuration to un-wedge the bus */ + + imx9_iomux_gpio(priv->config->scl_pin, true); + imx9_iomux_gpio(priv->config->sda_pin, true); + + scl_gpio = priv->config->reset_scl_pin; + sda_gpio = priv->config->reset_sda_pin; + + imx9_config_gpio(scl_gpio); + imx9_config_gpio(sda_gpio); + + /* Let SDA go high */ + + imx9_gpio_write(sda_gpio, 1); + + /* Clock the bus until any slaves currently driving it let it go. */ + + clock_count = 0; + while (!imx9_gpio_read(sda_gpio)) + { + /* Give up if we have tried too hard */ + + if (clock_count++ > 10) + { + goto out; + } + + /* Sniff to make sure that clock stretching has finished. + * + * If the bus never relaxes, the reset has failed. + */ + + stretch_count = 0; + while (!imx9_gpio_read(scl_gpio)) + { + /* Give up if we have tried too hard */ + + if (stretch_count++ > 10) + { + goto out; + } + + up_udelay(10); + } + + /* Drive SCL low */ + + imx9_gpio_write(scl_gpio, 0); + up_udelay(10); + + /* Drive SCL high again */ + + imx9_gpio_write(scl_gpio, 1); + up_udelay(10); + } + + /* Generate a start followed by a stop to reset slave + * state machines. + */ + + imx9_gpio_write(sda_gpio, 0); + up_udelay(10); + imx9_gpio_write(scl_gpio, 0); + up_udelay(10); + imx9_gpio_write(scl_gpio, 1); + up_udelay(10); + imx9_gpio_write(sda_gpio, 1); + up_udelay(10); + + /* Re-init the port */ + + imx9_lpi2c_init(priv); + + /* Restore the frequency */ + + imx9_lpi2c_setclock(priv, frequency); + ret = OK; + +out: + + /* Release the port for re-use by other clients */ + + nxmutex_unlock(&priv->lock); + return ret; +} +#endif /* CONFIG_I2C_RESET */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_i2cbus_initialize + * + * Description: + * Initialize one I2C bus + * + ****************************************************************************/ + +struct i2c_master_s *imx9_i2cbus_initialize(int port) +{ + struct imx9_lpi2c_priv_s * priv = NULL; + irqstate_t flags; + + /* Get I2C private structure */ + + switch (port) + { +#ifdef CONFIG_IMX9_LPI2C1 + case 1: + priv = (struct imx9_lpi2c_priv_s *)&imx9_lpi2c1_priv; + break; +#endif +#ifdef CONFIG_IMX9_LPI2C2 + case 2: + priv = (struct imx9_lpi2c_priv_s *)&imx9_lpi2c2_priv; + break; +#endif +#ifdef CONFIG_IMX9_LPI2C3 + case 3: + priv = (struct imx9_lpi2c_priv_s *)&imx9_lpi2c3_priv; + break; +#endif +#ifdef CONFIG_IMX9_LPI2C4 + case 4: + priv = (struct imx9_lpi2c_priv_s *)&imx9_lpi2c4_priv; + break; +#endif +#ifdef CONFIG_IMX9_LPI2C5 + case 5: + priv = (struct imx9_lpi2c_priv_s *)&imx9_lpi2c5_priv; + break; +#endif +#ifdef CONFIG_IMX9_LPI2C6 + case 6: + priv = (struct imx9_lpi2c_priv_s *)&imx9_lpi2c6_priv; + break; +#endif +#ifdef CONFIG_IMX9_LPI2C7 + case 7: + priv = (struct imx9_lpi2c_priv_s *)&imx9_lpi2c7_priv; + break; +#endif +#ifdef CONFIG_IMX9_LPI2C8 + case 8: + priv = (struct imx9_lpi2c_priv_s *)&imx9_lpi2c8_priv; + break; +#endif + default: + return NULL; + } + + /* Initialize private data for the first time, increment reference count, + * power-up hardware and configure GPIOs. + */ + + flags = enter_critical_section(); + + if ((volatile int)priv->refs++ == 0) + { + imx9_lpi2c_init(priv); + +#ifdef CONFIG_IMX9_LPI2C_DMA + if (priv->config->dma_txreqsrc != 0) + { + priv->txdma = imx9_dmach_alloc(priv->config->dma_txreqsrc, 0); + DEBUGASSERT(priv->txdma != NULL); + } + + if (priv->config->dma_rxreqsrc != 0) + { + priv->rxdma = imx9_dmach_alloc(priv->config->dma_rxreqsrc, 0); + DEBUGASSERT(priv->rxdma != NULL); + } +#endif + } + + leave_critical_section(flags); + + return (struct i2c_master_s *)priv; +} + +/**************************************************************************** + * Name: imx9_i2cbus_uninitialize + * + * Description: + * Uninitialize an I2C bus + * + ****************************************************************************/ + +int imx9_i2cbus_uninitialize(struct i2c_master_s *dev) +{ + struct imx9_lpi2c_priv_s *priv = (struct imx9_lpi2c_priv_s *)dev; + irqstate_t flags; + + DEBUGASSERT(dev); + + /* Decrement reference count and check for underflow */ + + if (priv->refs == 0) + { + return ERROR; + } + + flags = enter_critical_section(); + + if (--priv->refs > 0) + { + leave_critical_section(flags); + return OK; + } + + leave_critical_section(flags); + + /* Disable power and other HW resource (GPIO's) */ + +#ifdef CONFIG_IMX9_LPI2C_DMA + if (priv->rxdma != NULL) + { + imx9_dmach_stop(priv->rxdma); + imx9_dmach_free(priv->rxdma); + priv->rxdma = NULL; + } + + if (priv->txdma != NULL) + { + imx9_dmach_stop(priv->txdma); + imx9_dmach_free(priv->txdma); + priv->txdma = NULL; + } +#endif + + imx9_lpi2c_deinit(priv); + + return OK; +} + +#endif /* CONFIG_IMX9_LPI2C */ diff --git a/arch/arm64/src/imx9/imx9_lpi2c.h b/arch/arm64/src/imx9/imx9_lpi2c.h new file mode 100644 index 0000000000000..d323871fa3183 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_lpi2c.h @@ -0,0 +1,71 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_lpi2c.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_LPI2C_H +#define __ARCH_ARM64_SRC_IMX9_IMX9_LPI2C_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_i2cbus_initialize + * + * Description: + * Initialize the selected I2C port. And return a unique instance of struct + * struct i2c_master_s. This function may be called to obtain multiple + * instances of the interface, each of which may be set up with a + * different frequency and slave address. + * + * Input Parameters: + * Port number (for hardware that has multiple I2C interfaces) + * + * Returned Value: + * Valid I2C device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct i2c_master_s *imx9_i2cbus_initialize(int port); + +/**************************************************************************** + * Name: imx9_i2cbus_uninitialize + * + * Description: + * De-initialize the selected I2C port, and power down the device. + * + * Input Parameters: + * Device structure as returned by the imx9_i2cbus_initialize() + * + * Returned Value: + * OK on success, ERROR when internal reference count mismatch or dev + * points to invalid hardware device. + * + ****************************************************************************/ + +int imx9_i2cbus_uninitialize(struct i2c_master_s *dev); + +#endif /* __ARCH_ARM64_SRC_IMX9_IMX9_LPI2C_H */ diff --git a/arch/arm64/src/imx9/imx9_lpspi.c b/arch/arm64/src/imx9/imx9_lpspi.c new file mode 100644 index 0000000000000..b373b04c8f213 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_lpspi.c @@ -0,0 +1,2096 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_lpspi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * The external functions, imx9_lpspi1/2/3/4select and + * imx9_lpspi1/2/3/4status must be provided by board-specific logic. + * They are implementations of the select and status methods of the SPI + * interface defined by struct imx9_lpspi_ops_s (see + * include/nuttx/spi/spi.h). All other methods (including + * imx9_lpspibus_initialize()) are provided by common IMX9 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in imx9_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide imx9_lpspi1/2/3/4select() and imx9_lpspi1/2/3/4status() + * functions in your board-specific logic. These functions will + * perform chip selection and status operations using GPIOs in the way + * your board is configured. + * 3. Add a calls to imx9_lpspibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by imx9_lpspibus_initialize() may then be + * used to bind the SPI driver to higher level logic (e.g., calling + * mmcsd_lpspislotinitialize(), for example, will bind the SPI + * driver to the SPI MMC/SD driver). + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "arm64_internal.h" +#include "imx9_ccm.h" +#include "imx9_clockconfig.h" +#include "imx9_dma_alloc.h" +#include "imx9_gpio.h" +#include "imx9_iomuxc.h" +#include "imx9_lpspi.h" + +#include "hardware/imx9_ccm.h" +#include "hardware/imx9_lpspi.h" +#include "hardware/imx9_pinmux.h" + +#ifdef CONFIG_IMX9_LPSPI_DMA +# include "chip.h" +# include "imx9_edma.h" +# include "hardware/imx9_dmamux.h" +#endif + +#ifdef CONFIG_IMX9_LPSPI + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* SPI interrupts */ + +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS +# error "Interrupt driven SPI not yet supported" +#endif + +/* Can't have both interrupt driven SPI and SPI DMA */ + +#if defined(CONFIG_IMX9_LPSPI_INTERRUPTS) && defined(CONFIG_IMX9_LPSPI_DMA) +# error "Cannot enable both interrupt mode and DMA mode for SPI" +#endif + +#define SPI_SR_CLEAR (LPSPI_SR_WCF | LPSPI_SR_FCF | LPSPI_SR_TCF | \ + LPSPI_SR_TEF | LPSPI_SR_REF | LPSPI_SR_DMF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct imx9_lpspidev_s +{ + struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ + uint32_t spibase; /* SPIn base address */ + uint8_t clk_root; /* SPIn clock root */ + uint8_t clk_gate; /* SPIn clock gate */ +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS + uint8_t spiirq; /* SPI IRQ number */ +#endif + mutex_t lock; /* Held while chip is selected for mutual exclusion */ + uint32_t frequency; /* Requested clock frequency */ + uint32_t actual; /* Actual clock frequency */ + int8_t nbits; /* Width of word in bits */ + uint8_t mode; /* Mode 0,1,2,3 */ +#ifdef CONFIG_IMX9_LPSPI_DMA + volatile uint32_t rxresult; /* Result of the RX DMA */ + volatile uint32_t txresult; /* Result of the TX DMA */ + const uint16_t rxch; /* The RX DMA channel number */ + const uint16_t txch; /* The TX DMA channel number */ + DMACH_HANDLE rxdma; /* DMA channel handle for RX transfers */ + DMACH_HANDLE txdma; /* DMA channel handle for TX transfers */ + sem_t rxsem; /* Wait for RX DMA to complete */ + sem_t txsem; /* Wait for TX DMA to complete */ + void *txbuf; /* Driver DMA safe buffer for TX */ + void *rxbuf; /* Driver DMA safe buffer for RX */ +#endif +}; + +enum imx9_delay_e +{ + LPSPI_PCS_TO_SCK = 1, /* PCS-to-SCK delay. */ + LPSPI_LAST_SCK_TO_PCS, /* Last SCK edge to PCS delay. */ + LPSPI_BETWEEN_TRANSFER /* Delay between transfers. */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Helpers */ + +static inline uint32_t +imx9_lpspi_getreg32(struct imx9_lpspidev_s *priv, uint8_t offset); +static inline void imx9_lpspi_putreg32(struct imx9_lpspidev_s *priv, + uint8_t offset, uint32_t value); +static inline uint32_t imx9_lpspi_readword( + struct imx9_lpspidev_s *priv); +static inline void imx9_lpspi_writeword(struct imx9_lpspidev_s *priv, + uint16_t byte); +static inline bool imx9_lpspi_9to16bitmode( + struct imx9_lpspidev_s *priv); +static inline void imx9_lpspi_master_set_delays(struct imx9_lpspidev_s + *priv, uint32_t delay_ns, + enum imx9_delay_e type); +static inline void imx9_lpspi_master_set_delay_scaler( + struct imx9_lpspidev_s *priv, + uint32_t scaler, + enum imx9_delay_e type); + +/* DMA support */ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static int spi_dmarxwait(struct imx9_lpspidev_s *priv); +static int spi_dmatxwait(struct imx9_lpspidev_s *priv); +static inline void spi_dmarxwakeup(struct imx9_lpspidev_s *priv); +static inline void spi_dmatxwakeup(struct imx9_lpspidev_s *priv); +static void spi_dmarxcallback(DMACH_HANDLE handle, void *arg, + bool done, int result); +static void spi_dmatxcallback(DMACH_HANDLE handle, void *arg, + bool done, int result); +static inline void spi_dmarxstart(struct imx9_lpspidev_s *priv); +static inline void spi_dmatxstart(struct imx9_lpspidev_s *priv); +#endif + +/* SPI methods */ + +static int imx9_lpspi_lock(struct spi_dev_s *dev, bool lock); +static uint32_t imx9_lpspi_setfrequency(struct spi_dev_s *dev, + uint32_t frequency); +static void imx9_lpspi_setmode(struct spi_dev_s *dev, + enum spi_mode_e mode); +static void imx9_lpspi_setbits(struct spi_dev_s *dev, int nbits); +#ifdef CONFIG_SPI_HWFEATURES +static int imx9_lpspi_hwfeatures(struct spi_dev_s *dev, + imx9_lpspi_hwfeatures_t features); +#endif +static uint32_t imx9_lpspi_send(struct spi_dev_s *dev, uint32_t wd); +static void imx9_lpspi_exchange(struct spi_dev_s *dev, + const void *txbuffer, + void *rxbuffer, + size_t nwords); +#ifndef CONFIG_SPI_EXCHANGE +static void imx9_lpspi_sndblock(struct spi_dev_s *dev, + const void *txbuffer, size_t nwords); +static void imx9_lpspi_recvblock(struct spi_dev_s *dev, + void *rxbuffer, + size_t nwords); +#endif + +/* Initialization */ + +static void imx9_lpspi_bus_initialize(struct imx9_lpspidev_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct spi_ops_s g_spiops = +{ + .lock = imx9_lpspi_lock, + .select = imx9_lpspi_select, + .setfrequency = imx9_lpspi_setfrequency, + .setmode = imx9_lpspi_setmode, + .setbits = imx9_lpspi_setbits, +#ifdef CONFIG_SPI_HWFEATURES + .hwfeatures = imx9_lpspi_hwfeatures, +#endif + .status = imx9_lpspi_status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = imx9_lpspi_cmddata, +#endif + .send = imx9_lpspi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = imx9_lpspi_exchange, +#else + .sndblock = imx9_lpspi_sndblock, + .recvblock = imx9_lpspi_recvblock, +#endif +#ifdef CONFIG_SPI_CALLBACK + .registercallback = imx9_lpspi_register, /* Provided externally */ +#else + .registercallback = 0, /* Not implemented */ +#endif +}; + +#ifdef CONFIG_IMX9_LPSPI1 +static struct imx9_lpspidev_s g_lpspi1dev = +{ + .spidev = + { + .ops = &g_spiops, + }, + .spibase = IMX9_LPSPI1_BASE, + .clk_root = CCM_CR_LPSPI1, + .clk_gate = CCM_LPCG_LPSPI1, +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS + .spiirq = IMX9_IRQ_LPSPI1, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_IMX9_LPSPI1_DMA + .rxch = DMA_REQUEST_MUXLPSPI1RX, + .txch = DMA_REQUEST_MUXLPSPI1TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif +}; +#endif + +#ifdef CONFIG_IMX9_LPSPI2 +static struct imx9_lpspidev_s g_lpspi2dev = +{ + .spidev = + { + .ops = &g_spi2ops, + }, + .spibase = IMX9_LPSPI2_BASE, + .clk_root = CCM_CR_LPSPI2, + .clk_gate = CCM_LPCG_LPSPI2, +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS + .spiirq = IMX9_IRQ_LPSPI2, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_IMX9_LPSPI2_DMA + .rxch = DMA_REQUEST_MUXLPSPI2RX, + .txch = DMA_REQUEST_MUXLPSPI2TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif +}; +#endif + +#ifdef CONFIG_IMX9_LPSPI3 +static struct imx9_lpspidev_s g_lpspi3dev = +{ + .spidev = + { + .ops = &g_spi3ops, + }, + .spibase = IMX9_LPSPI3_BASE, + .clk_root = CCM_CR_LPSPI3, + .clk_gate = CCM_LPCG_LPSPI3, +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS + .spiirq = IMX9_IRQ_LPSPI3, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_IMX9_LPSPI3_DMA + .rxch = DMA_REQUEST_MUXLPSPI3RX, + .txch = DMA_REQUEST_MUXLPSPI3TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif +}; +#endif + +#ifdef CONFIG_IMX9_LPSPI4 +static struct imx9_lpspidev_s g_lpspi4dev = +{ + .spidev = + { + .ops = &g_spiops, + }, + .spibase = IMX9_LPSPI4_BASE, + .clk_root = CCM_CR_LPSPI4, + .clk_gate = CCM_LPCG_LPSPI4, +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS + .spiirq = IMX9_IRQ_LPSPI4, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_IMX9_LPSPI4_DMA + .rxch = DMA_REQUEST_MUXLPSPI4RX, + .txch = DMA_REQUEST_MUXLPSPI4TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif +}; +#endif + +#ifdef CONFIG_IMX9_LPSPI5 +static struct imx9_lpspidev_s g_lpspi5dev = +{ + .spidev = + { + &g_spiops + }, + .spibase = IMX9_LPSPI5_BASE, + .clk_root = CCM_CR_LPSPI5, + .clk_gate = CCM_LPCG_LPSPI5, +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS + .spiirq = IMX9_IRQ_LPSPI5, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_IMX9_LPSPI5_DMA + .rxch = DMA_REQUEST_MUXLPSPI5RX, + .txch = DMA_REQUEST_MUXLPSPI5TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif +}; +#endif + +#ifdef CONFIG_IMX9_LPSPI6 +static struct imx9_lpspidev_s g_lpspi6dev = +{ + .spidev = + { + &g_spiops + }, + .spibase = IMX9_LPSPI6_BASE, + .clk_root = CCM_CR_LPSPI6, + .clk_gate = CCM_LPCG_LPSPI6, +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS + .spiirq = IMX9_IRQ_LPSPI6, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_IMX9_LPSPI6_DMA + .rxch = DMA_REQUEST_MUXLPSPI6RX, + .txch = DMA_REQUEST_MUXLPSPI6TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif +}; +#endif + +#ifdef CONFIG_IMX9_LPSPI7 +static struct imx9_lpspidev_s g_lpspi7dev = +{ + .spidev = + { + &g_spiops + }, + .spibase = IMX9_LPSPI7_BASE, + .clk_root = CCM_CR_LPSPI7, + .clk_gate = CCM_LPCG_LPSPI7, +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS + .spiirq = IMX9_IRQ_LPSPI7, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_IMX9_LPSPI7_DMA + .rxch = DMA_REQUEST_MUXLPSPI7RX, + .txch = DMA_REQUEST_MUXLPSPI7TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif +}; +#endif + +#ifdef CONFIG_IMX9_LPSPI8 +static struct imx9_lpspidev_s g_lpspi8dev = +{ + .spidev = + { + &g_spiops + }, + .spibase = IMX9_LPSPI8_BASE, + .clk_root = CCM_CR_LPSPI8, + .clk_gate = CCM_LPCG_LPSPI8, +#ifdef CONFIG_IMX9_LPSPI_INTERRUPTS + .spiirq = IMX9_IRQ_LPSPI8, +#endif + .lock = NXMUTEX_INITIALIZER, +#ifdef CONFIG_IMX9_LPSPI6_DMA + .rxch = DMA_REQUEST_MUXLPSPI8RX, + .txch = DMA_REQUEST_MUXLPSPI8TX, + .rxsem = SEM_INITIALIZER(0), + .txsem = SEM_INITIALIZER(0), +#endif +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_lpspi_getreg + * + * Description: + * Get the contents of the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * + * Returned Value: + * The contents of the 32-bit register + * + ****************************************************************************/ + +static inline uint32_t +imx9_lpspi_getreg32(struct imx9_lpspidev_s *priv, uint8_t offset) +{ + return getreg32(priv->spibase + offset); +} + +/**************************************************************************** + * Name: imx9_lpspi_putreg + * + * Description: + * Write a 16-bit value to the SPI register at offset + * + * Input Parameters: + * priv - private SPI device structure + * offset - offset to the register of interest + * value - the 32-bit value to be written + * + * Returned Value: + * The contents of the 32-bit register + * + ****************************************************************************/ + +static inline void imx9_lpspi_putreg32(struct imx9_lpspidev_s *priv, + uint8_t offset, uint32_t value) +{ + putreg32(value, priv->spibase + offset); +} + +/**************************************************************************** + * Name: imx9_lpspi_readword + * + * Description: + * Read one word from SPI + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * word as read + * + ****************************************************************************/ + +static inline uint32_t +imx9_lpspi_readword(struct imx9_lpspidev_s *priv) +{ + /* Wait until the receive buffer is not empty */ + + while ((imx9_lpspi_getreg32(priv, IMX9_LPSPI_SR_OFFSET) + & LPSPI_SR_RDF) == 0); + + /* Then return the received byte */ + + return imx9_lpspi_getreg32(priv, IMX9_LPSPI_RDR_OFFSET); +} + +/**************************************************************************** + * Name: imx9_lpspi_writeword + * + * Description: + * Write one word to SPI + * + * Input Parameters: + * priv - Device-specific state data + * word - word to send + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void imx9_lpspi_writeword(struct imx9_lpspidev_s *priv, + uint16_t word) +{ + /* Wait until the transmit buffer is empty */ + + while ((imx9_lpspi_getreg32(priv, IMX9_LPSPI_SR_OFFSET) + & LPSPI_SR_TDF) == 0); + + /* Then send the word */ + + imx9_lpspi_putreg32(priv, IMX9_LPSPI_TDR_OFFSET, word); +} + +/**************************************************************************** + * Name: imx9_lpspi_9to16bitmode + * + * Description: + * Check if the SPI is operating in more then 8 bit mode + * + * Input Parameters: + * priv - Device-specific state data + * + * Returned Value: + * true: >8 bit mode-bit mode, false: <= 8-bit mode + * + ****************************************************************************/ + +static inline bool +imx9_lpspi_9to16bitmode(struct imx9_lpspidev_s *priv) +{ + bool ret; + + if (((imx9_lpspi_getreg32(priv, IMX9_LPSPI_TCR_OFFSET) & + LPSPI_TCR_FRAMESZ_MASK) + 1) < 9) + { + ret = false; + } + else + { + ret = true; + } + + return ret; +} + +/**************************************************************************** + * Name: imx9_lpspi_modifyreg32 + * + * Description: + * Clear and set bits in register + * + * Input Parameters: + * priv - Device-specific state data + * offset - Register offset + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void imx9_lpspi_modifyreg32(struct imx9_lpspidev_s *priv, + uint8_t offset, uint32_t clrbits, + uint32_t setbits) +{ + modifyreg32(priv->spibase + offset, clrbits, setbits); +} + +/**************************************************************************** + * Name: imx9_lpspi_modifyreg32 + * + * Description: + * Clear and set bits TCR register. Need a safe wrapper as TCR expects + * LPSPI is _enabled_ when writing. + * + * Input Parameters: + * priv - Device-specific state data + * offset - Register offset + * clrbits - The bits to clear + * setbits - The bits to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void imx9_lpspi_modifytcr(struct imx9_lpspidev_s *priv, + uint32_t clrbits, uint32_t setbits) +{ + uint32_t men; + + /* Enable LPSPI if it was disabled previously */ + + men = imx9_lpspi_getreg32(priv, IMX9_LPSPI_CR_OFFSET) & LPSPI_CR_MEN; + if (!men) + { + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, 0, + LPSPI_CR_MEN); + } + + /* Update the register */ + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_TCR_OFFSET, clrbits, setbits); + + /* Disable LPSPI if it was disabled */ + + if (!men) + { + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, + LPSPI_CR_MEN, 0); + } +} + +/**************************************************************************** + * Name: imx9_lpspi_master_set_delays + * + * Description: + * SET LPSPI Delay times + * + * Input Parameters: + * priv - Device-specific state data + * scaler - scaler value + * type - delay time type + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void imx9_lpspi_master_set_delay_scaler( + struct imx9_lpspidev_s *priv, + uint32_t scaler, + enum imx9_delay_e type) +{ + uint32_t ccr1; + uint32_t dbt; + uint32_t sckdiv; + + /* Read from SCKDIV and DTB will always return 0. In order to preserve the + * old values we must calculate them here locally from CCR1 values. + */ + + ccr1 = imx9_lpspi_getreg32(priv, IMX9_LPSPI_CCR1_OFFSET); + dbt = (ccr1 & LPSPI_CCR1_SCKSCK_MASK) >> LPSPI_CCR1_SCKSCK_SHIFT; + sckdiv = (ccr1 & LPSPI_CCR1_SCKHLD_MASK) >> LPSPI_CCR1_SCKHLD_SHIFT; + sckdiv += (ccr1 & LPSPI_CCR1_SCKSET_MASK) >> LPSPI_CCR1_SCKSET_SHIFT; + + switch (type) + { + case LPSPI_PCS_TO_SCK: + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CCR_OFFSET, + LPSPI_CCR_PCSSCK_MASK, 0); + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CCR_OFFSET, 0, + LPSPI_CCR_DBT(dbt) | + LPSPI_CCR_PCSSCK(scaler) | + LPSPI_CCR_SCKDIV(sckdiv)); + break; + + case LPSPI_LAST_SCK_TO_PCS: + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CCR_OFFSET, + LPSPI_CCR_SCKPCS_MASK, 0); + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CCR_OFFSET, 0, + LPSPI_CCR_DBT(dbt) | + LPSPI_CCR_PCSSCK(scaler) | + LPSPI_CCR_SCKDIV(sckdiv)); + break; + + case LPSPI_BETWEEN_TRANSFER: + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CCR_OFFSET, + LPSPI_CCR_DBT_MASK, 0); + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CCR_OFFSET, 0, + LPSPI_CCR_DBT(dbt) | + LPSPI_CCR_PCSSCK(scaler) | + LPSPI_CCR_SCKDIV(sckdiv)); + break; + } +} + +/**************************************************************************** + * Name: imx9_lpspi_master_set_delays + * + * Description: + * SET LPSPI Delay times + * + * Input Parameters: + * priv - Device-specific state data + * delay_ns - delay time in nano seconds + * type - delay time type + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void imx9_lpspi_master_set_delays( + struct imx9_lpspidev_s *priv, + uint32_t delay_ns, + enum imx9_delay_e type) +{ + uint32_t src_freq; + uint64_t real_delay; + uint32_t scaler; + uint32_t best_scaler; + uint32_t diff; + uint32_t min_diff; + uint64_t initial_delay_ns; + uint32_t clock_div_prescaler; + uint32_t additional_scaler; + + imx9_get_rootclock(priv->clk_root, &src_freq); + + clock_div_prescaler = src_freq / + (1 << ((imx9_lpspi_getreg32(priv, IMX9_LPSPI_TCR_OFFSET) & + LPSPI_TCR_PRESCALE_MASK) >> LPSPI_TCR_PRESCALE_SHIFT)); + + min_diff = 0xffffffff; + + /* Initialize scaler to max value to generate the max delay */ + + best_scaler = 0xff; + + if (type == LPSPI_BETWEEN_TRANSFER) + { + /* First calculate the initial, default delay, note min delay is 2 + * clock cycles. Due to large size of * calculated values (uint64_t), + * we need to break up the calculation into several steps to ensure + * accurate calculated results + */ + + initial_delay_ns = 1000000000U; + initial_delay_ns *= 2; + initial_delay_ns /= clock_div_prescaler; + + additional_scaler = 1U; + } + else + { + /* First calculate the initial, default delay, min delay is 1 clock + * cycle. Due to large size of calculated values (uint64_t), we need to + * break up the calculation into several steps to ensure accurate + * calculated * results. + */ + + initial_delay_ns = 1000000000U; + initial_delay_ns /= clock_div_prescaler; + + additional_scaler = 0; + } + + /* If the initial, default delay is already greater than the desired delay, + * then * set the delay to their initial value (0) and return the delay. In + * other words, * there is no way to decrease the delay value further. + */ + + if (initial_delay_ns >= delay_ns) + { + imx9_lpspi_master_set_delay_scaler(priv, 0, type); + } + else + { + /* If min_diff = 0, the exit for loop */ + + for (scaler = 0; (scaler < 256) && min_diff; scaler++) + { + /* Calculate the real delay value as we cycle through the scaler + * values. Due to large size of calculated values (uint64_t), + * we need to break up the calculation into several steps to + * ensure accurate calculated results + */ + + real_delay = 1000000000U; + real_delay *= (scaler + 1 + additional_scaler); + real_delay /= clock_div_prescaler; + + /* calculate the delay difference based on the conditional + * statement that states that the calculated delay must not be + * less then the desired delay + */ + + if (real_delay >= delay_ns) + { + diff = real_delay - delay_ns; + if (min_diff > diff) + { + /* A better match found */ + + min_diff = diff; + best_scaler = scaler; + } + } + } + + imx9_lpspi_master_set_delay_scaler(priv, best_scaler, type); + } +} + +/**************************************************************************** + * Name: imx9_lpspi_lock + * + * Description: + * On SPI buses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the buses for a sequence of + * transfers. The bus should be locked before the chip is selected. After + * locking the SPI bus, the caller should then also call the setfrequency, + * setbits, and setmode methods to make sure that the SPI is properly + * configured for the device. If the SPI bus is being shared, then it + * may have been left in an incompatible state. + * + * Input Parameters: + * dev - Device-specific state data + * lock - true: Lock spi bus, false: unlock SPI bus + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int imx9_lpspi_lock(struct spi_dev_s *dev, bool lock) +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)dev; + int ret; + + if (lock) + { + ret = nxmutex_lock(&priv->lock); + } + else + { + ret = nxmutex_unlock(&priv->lock); + } + + return ret; +} + +/**************************************************************************** + * Name: imx9_lpspi_setfrequency + * + * Description: + * Set the SPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static uint32_t imx9_lpspi_setfrequency(struct spi_dev_s *dev, + uint32_t frequency) +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)dev; + + uint32_t men; + uint32_t src_freq = 0; + uint32_t prescaler; + uint32_t best_prescaler; + uint32_t scaler; + uint32_t best_scaler; + uint32_t real_frequency; + uint32_t best_frequency; + uint32_t diff; + uint32_t min_diff; + + /* Has the LPSPI bus frequency changed? */ + + if (frequency != priv->frequency) + { + /* Disable LPSPI if it is enabled */ + + men = imx9_lpspi_getreg32(priv, IMX9_LPSPI_CR_OFFSET) & LPSPI_CR_MEN; + if (men) + { + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, + LPSPI_CR_MEN, 0); + } + + imx9_get_rootclock(priv->clk_root, &src_freq); + + min_diff = 0xffffffff; + best_prescaler = 7; + best_scaler = 255; + best_frequency = 0; + + for (prescaler = 0; (prescaler < 8) && min_diff; prescaler++) + { + for (scaler = 0; (scaler < 256) && min_diff; scaler++) + { + real_frequency = src_freq / ((1 << prescaler) * (scaler + 2)); + + /* Calculate the frequency difference based on conditional + * statement that states that the calculated frequency must not + * exceed desired frequency. + */ + + if (frequency >= real_frequency) + { + diff = frequency - real_frequency; + if (min_diff > diff) + { + /* A better match found */ + + min_diff = diff; + best_prescaler = prescaler; + best_scaler = scaler; + best_frequency = real_frequency; + } + } + } + } + + /* Write the best values in the CCR register */ + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CCR_OFFSET, + LPSPI_CCR_SCKDIV_MASK, + LPSPI_CCR_SCKDIV(best_scaler)); + + /* Update TCR */ + + imx9_lpspi_modifytcr(priv, LPSPI_TCR_PRESCALE_MASK, + LPSPI_TCR_PRESCALE(best_prescaler)); + + priv->frequency = frequency; + priv->actual = best_frequency; + imx9_lpspi_master_set_delays(priv, 1000000000 / best_frequency, + LPSPI_PCS_TO_SCK); + imx9_lpspi_master_set_delays(priv, 1000000000 / best_frequency, + LPSPI_LAST_SCK_TO_PCS); + imx9_lpspi_master_set_delays(priv, 1000000000 / best_frequency, + LPSPI_BETWEEN_TRANSFER); + + /* Re-enable LPSPI if it was enabled previously */ + + if (men) + { + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, 0, + LPSPI_CR_MEN); + } + } + + return priv->actual; +} + +/**************************************************************************** + * Name: imx9_lpspi_setmode + * + * Description: + * Set the SPI mode. see enum spi_mode_e mode for mode definitions + * + * Input Parameters: + * dev - Device-specific state data + * mode - The SPI mode requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static void imx9_lpspi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)dev; + uint32_t setbits; + uint32_t clrbits; + + spiinfo("mode=%d\n", mode); + + /* Has the mode changed? */ + + if (mode != priv->mode) + { + /* Disable LPSPI if it is enabled */ + + switch (mode) + { + case SPIDEV_MODE0: /* CPOL=0; CPHA=0 */ + setbits = 0; + clrbits = LPSPI_TCR_CPOL | LPSPI_TCR_CPHA; + break; + + case SPIDEV_MODE1: /* CPOL=0; CPHA=1 */ + setbits = LPSPI_TCR_CPHA; + clrbits = LPSPI_TCR_CPOL; + break; + + case SPIDEV_MODE2: /* CPOL=1; CPHA=0 */ + setbits = LPSPI_TCR_CPOL; + clrbits = LPSPI_TCR_CPHA; + break; + + case SPIDEV_MODE3: /* CPOL=1; CPHA=1 */ + setbits = LPSPI_TCR_CPOL | LPSPI_TCR_CPHA; + clrbits = 0; + break; + + default: + return; + } + + /* Update TCR register */ + + imx9_lpspi_modifytcr(priv, clrbits, setbits); + + while ((imx9_lpspi_getreg32(priv, IMX9_LPSPI_RSR_OFFSET) & + LPSPI_RSR_RXEMPTY) != LPSPI_RSR_RXEMPTY) + { + /* Flush SPI read FIFO */ + + imx9_lpspi_getreg32(priv, IMX9_LPSPI_RSR_OFFSET); + } + + /* Save the mode so that subsequent re-configurations will be faster */ + + priv->mode = mode; + } +} + +/**************************************************************************** + * Name: imx9_lpspi_setbits + * + * Description: + * Set the number of bits per word. + * + * Input Parameters: + * dev - Device-specific state data + * nbits - The number of bits requested + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void imx9_lpspi_setbits(struct spi_dev_s *dev, int nbits) +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)dev; + + spiinfo("nbits=%d\n", nbits); + + /* Has the number of bits changed? */ + + if (nbits != priv->nbits) + { + if (nbits < 2 || nbits > 4096) + { + return; + } + + /* Update TCR */ + + imx9_lpspi_modifytcr(priv, LPSPI_TCR_FRAMESZ_MASK, + LPSPI_TCR_FRAMESZ(nbits - 1)); + + /* Save the selection so the subsequent re-configurations + * will be faster. + */ + + priv->nbits = nbits; + } +} + +/**************************************************************************** + * Name: imx9_lpspi_hwfeatures + * + * Description: + * Set hardware-specific feature flags. + * + * Input Parameters: + * dev - Device-specific state data + * features - H/W feature flags + * + * Returned Value: + * Zero (OK) if the selected H/W features are enabled; A negated errno + * value if any H/W feature is not supportable. + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_HWFEATURES +static int imx9_lpspi_hwfeatures(struct spi_dev_s *dev, + imx9_lpspi_hwfeatures_t features) +{ +#ifdef CONFIG_SPI_BITORDER + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)dev; + uint32_t setbits; + uint32_t clrbits; + + spiinfo("features=%08x\n", features); + + /* Transfer data LSB first? */ + + if ((features & HWFEAT_LSBFIRST) != 0) + { + setbits = LPSPI_TCR_LSBF; + clrbits = 0; + } + else + { + setbits = 0; + clrbits = LPSPI_TCR_LSBF; + } + + imx9_lpspi_modifytcr(priv, clrbits, setbits); + + /* Other H/W features are not supported */ + + return ((features & ~HWFEAT_LSBFIRST) == 0) ? OK : -ENOSYS; +#else + return -ENOSYS; +#endif +} +#endif + +/**************************************************************************** + * Name: imx9_lpspi_send + * + * Description: + * Exchange one word on SPI + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * response + * + ****************************************************************************/ + +static uint32_t imx9_lpspi_send(struct spi_dev_s *dev, uint32_t wd) +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)dev; + uint32_t regval; + uint32_t ret; + + DEBUGASSERT(priv && priv->spibase); + + imx9_lpspi_writeword(priv, wd); + + while ((imx9_lpspi_getreg32(priv, IMX9_LPSPI_SR_OFFSET) & + LPSPI_SR_RDF) != LPSPI_SR_RDF); + + ret = imx9_lpspi_readword(priv); + + /* Check and clear any error flags (Reading from the SR clears the error + * flags). + */ + + regval = imx9_lpspi_getreg32(priv, IMX9_LPSPI_SR_OFFSET); + + spiinfo( + "Sent: %04" PRIx32 " Return: %04" PRIx32 " Status: %02" PRIx32 "\n", + wd, ret, regval); + + UNUSED(regval); + return ret; +} + +/**************************************************************************** + * Name: imx9_lpspi_exchange (no DMA). aka imx9_lpspi_exchange_nodma + * + * Description: + * Exchange a block of data on SPI without using DMA + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to a buffer in which to receive data + * nwords - the length of data to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed + * into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if !defined(CONFIG_IMX9_LPSPI_DMA) +static void imx9_lpspi_exchange(struct spi_dev_s *dev, + const void *txbuffer, + void *rxbuffer, + size_t nwords) +#else +static void imx9_lpspi_exchange_nodma(struct spi_dev_s *dev, + const void *txbuffer, + void *rxbuffer, size_t nwords) +#endif +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)dev; + DEBUGASSERT(priv && priv->spibase); + + spiinfo("txbuffer=%p rxbuffer=%p nwords=%lu\n", txbuffer, rxbuffer, + nwords); + + /* 8- or 16-bit mode? */ + + if (imx9_lpspi_9to16bitmode(priv)) + { + /* 16-bit mode */ + + const uint16_t *src = txbuffer; + uint16_t *dest = rxbuffer; + uint16_t word; + + while (nwords-- > 0) + { + /* Get the next word to write. Is there a source buffer? */ + + if (src) + { + word = *src++; + } + else + { + word = 0xffff; + } + + /* Exchange one word */ + + word = (uint16_t) imx9_lpspi_send(dev, (uint32_t) word); + + /* Is there a buffer to receive the return value? */ + + if (dest) + { + *dest++ = word; + } + } + } + else + { + /* 8-bit mode */ + + const uint8_t *src = txbuffer; + uint8_t *dest = rxbuffer; + uint8_t word; + + while (nwords-- > 0) + { + /* Get the next word to write. Is there a source buffer? */ + + if (src) + { + word = *src++; + } + else + { + word = 0xff; + } + + /* Exchange one word */ + + word = (uint8_t)imx9_lpspi_send(dev, word); + + /* Is there a buffer to receive the return value? */ + + if (dest) + { + *dest++ = word; + } + } + } +} + +/**************************************************************************** + * Name: spi_exchange (with DMA capability) + * + * Description: + * Exchange a block of data on SPI using DMA + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to a buffer in which to receive data + * nwords - the length of data to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits > 8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static void imx9_lpspi_exchange(struct spi_dev_s *dev, + const void *txbuffer, + void *rxbuffer, size_t nwords) +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)dev; + int ret; + size_t adjust; + ssize_t nbytes; + static uint8_t rxdummy[4] aligned_data(4); + static const uint16_t txdummy = 0xffff; + uint32_t regval; + + DEBUGASSERT(priv != NULL); + DEBUGASSERT(priv && priv->spibase); + spiinfo("txbuffer=%p rxbuffer=%p nwords=%lu\n", txbuffer, rxbuffer, + nwords); + + /* Convert the number of word to a number of bytes */ + + nbytes = (priv->nbits > 8) ? nwords << 2 : nwords; + + /* Invalid DMA channels fall back to non-DMA method. */ + + if (priv->rxdma == NULL || priv->txdma == NULL +#ifdef CONFIG_IMX9_LPSPI_DMATHRESHOLD + /* If this is a small SPI transfer, then let + * imx9_lpspi_exchange_nodma() do the work. + */ + + || nbytes <= CONFIG_IMX9_LPSPI_DMATHRESHOLD +#endif + ) + { + imx9_lpspi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); + return; + } + + /* Check if the transfer is too long */ + + if (nbytes > CONFIG_IMX9_LPSPI_DMA_BUFFER_SIZE) + { + /* Transfer is too long, revert to slow non-DMA method */ + + spiwarn("frame %lu too long, fall back to no DMA transfer\n", nbytes); + imx9_lpspi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); + return; + } + + /* Disable SPI when we are configuring it */ + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, LPSPI_CR_MEN, 0); + + /* ERR050456 workaround: Reset FIFOs using CR[RST] bit */ + + regval = imx9_lpspi_getreg32(priv, IMX9_LPSPI_CFGR1_OFFSET); + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, + LPSPI_CR_RTF | LPSPI_CR_RRF, + LPSPI_CR_RTF | LPSPI_CR_RRF); + + imx9_lpspi_putreg32(priv, IMX9_LPSPI_CFGR1_OFFSET, regval); + + /* Clear all status bits */ + + imx9_lpspi_putreg32(priv, IMX9_LPSPI_SR_OFFSET, SPI_SR_CLEAR); + + /* disable DMA */ + + imx9_lpspi_putreg32(priv, IMX9_LPSPI_DER_OFFSET, 0); + + if (txbuffer) + { + /* Move the user data to device internal buffer */ + + memcpy(priv->txbuf, txbuffer, nbytes); + + /* And flush it to RAM */ + + up_clean_dcache((uintptr_t)priv->txbuf, + (uintptr_t)priv->txbuf + nbytes); + } + + if (rxbuffer) + { + /* Prepare the RX buffer for DMA */ + + up_invalidate_dcache((uintptr_t)priv->rxbuf, + (uintptr_t)priv->rxbuf + nbytes); + } + + /* Set up the DMA */ + + adjust = (priv->nbits > 8) ? 2 : 1; + + struct imx9_edma_xfrconfig_s config; + + config.saddr = priv->spibase + IMX9_LPSPI_RDR_OFFSET; + config.daddr = (uintptr_t) (rxbuffer ? priv->rxbuf : rxdummy); + config.soff = 0; + config.doff = rxbuffer ? adjust : 0; + config.iter = nbytes; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE; + config.ssize = adjust == 1 ? EDMA_8BIT : EDMA_16BIT; + config.dsize = adjust == 1 ? EDMA_8BIT : EDMA_16BIT; + config.nbytes = adjust; +#ifdef CONFIG_IMX9_EDMA_ELINK + config.linkch = NULL; +#endif + imx9_dmach_xfrsetup(priv->rxdma, &config); + + config.saddr = (uintptr_t) (txbuffer ? priv->txbuf : &txdummy); + config.daddr = priv->spibase + IMX9_LPSPI_TDR_OFFSET; + config.soff = txbuffer ? adjust : 0; + config.doff = 0; + config.iter = nbytes; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE; + config.ssize = adjust == 1 ? EDMA_8BIT : EDMA_16BIT; + config.dsize = adjust == 1 ? EDMA_8BIT : EDMA_16BIT; + config.nbytes = adjust; +#ifdef CONFIG_IMX9_EDMA_ELINK + config.linkch = NULL; +#endif + imx9_dmach_xfrsetup(priv->txdma, &config); + + /* Start the DMAs */ + + spi_dmarxstart(priv); + spi_dmatxstart(priv); + + /* Enable SPI again */ + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN); + + /* Invoke SPI DMA */ + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_DER_OFFSET, + 0, LPSPI_DER_TDDE | LPSPI_DER_RDDE); + + /* Then wait for each to complete */ + + ret = spi_dmarxwait(priv); + + if (ret < 0) + { + ret = spi_dmatxwait(priv); + } + + /* Reset any status */ + + imx9_lpspi_putreg32(priv, IMX9_LPSPI_SR_OFFSET, SPI_SR_CLEAR); + + /* Disable DMA */ + + imx9_lpspi_putreg32(priv, IMX9_LPSPI_DER_OFFSET, 0); + + if (rxbuffer && ret >= 0) + { + /* Flush the RX data to ram */ + + up_invalidate_dcache((uintptr_t)priv->rxbuf, + (uintptr_t)priv->rxbuf + nbytes); + + /* Copy data to user buffer */ + + memcpy(rxbuffer, priv->rxbuf, nbytes); + } +} + +#endif /* CONFIG_IMX9_SPI_DMA */ + +/**************************************************************************** + * Name: imx9_lpspi_sndblock + * + * Description: + * Send a block of data on SPI + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of + * words. The wordsize is determined by the number of + * bits-per-word selected for the SPI interface. If nbits <= 8, + * the data is packed into uint8_t's; if nbits >8, the data is + * packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void imx9_lpspi_sndblock(struct spi_dev_s *dev, + const void *txbuffer, size_t nwords) +{ + spiinfo("txbuffer=%p nwords=%lu\n", txbuffer, nwords); + return imx9_lpspi_exchange(dev, txbuffer, NULL, nwords); +} +#endif + +/**************************************************************************** + * Name: imx9_lpspi_recvblock + * + * Description: + * Receive a block of data from SPI + * + * Input Parameters: + * dev - Device-specific state data + * rxbuffer - A pointer to the buffer in which to receive data + * nwords - the length of data that can be received in the buffer in + * number of words. The wordsize is determined by the number of + * bits-per-word selected for the SPI interface. If nbits <= 8, + * the data is packed into uint8_t's; if nbits >8, the data is + * packed into uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void imx9_lpspi_recvblock(struct spi_dev_s *dev, + void *rxbuffer, size_t nwords) +{ + spiinfo("rxbuffer=%p nwords=%lu\n", rxbuffer, nwords); + return imx9_lpspi_exchange(dev, NULL, rxbuffer, nwords); +} +#endif + +/**************************************************************************** + * Name: imx9_lpspi_clock_enable + * + * Description: + * Ungate LPSPI clock + * + ****************************************************************************/ + +static void imx9_lpspi_clock_enable(struct imx9_lpspidev_s *priv) +{ + imx9_ccm_gate_on(priv->clk_gate, true); +} + +/**************************************************************************** + * Name: imx9_lpspi_bus_initialize + * + * Description: + * Initialize the selected SPI bus in its default state + * (Master, 8-bit, mode 0, etc.) + * + * Input Parameters: + * priv - private SPI device structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void imx9_lpspi_bus_initialize(struct imx9_lpspidev_s *priv) +{ + uint32_t reg = 0; + + /* Enable power and reset the peripheral */ + + imx9_lpspi_clock_enable(priv); + + /* Reset to known status */ + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, 0, LPSPI_CR_RST); + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, 0, + LPSPI_CR_RTF | LPSPI_CR_RRF); + imx9_lpspi_putreg32(priv, IMX9_LPSPI_CR_OFFSET, 0x00); + + /* Set LPSPI to master */ + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CFGR1_OFFSET, 0, + LPSPI_CFGR1_MASTER); + + /* Set specific PCS to active high or low + * TODO: Not needed for now + */ + + /* Set Configuration Register 1 related setting. */ + + reg = imx9_lpspi_getreg32(priv, IMX9_LPSPI_CFGR1_OFFSET); + reg &= ~(LPSPI_CFGR1_OUTCFG | LPSPI_CFGR1_PINCFG_MASK | + LPSPI_CFGR1_NOSTALL); + reg |= LPSPI_CFGR1_OUTCFG_RETAIN | LPSPI_CFGR1_PINCFG_SIN_SOUT; + imx9_lpspi_putreg32(priv, IMX9_LPSPI_CFGR1_OFFSET, reg); + + /* Set frequency and delay times */ + + imx9_lpspi_setfrequency((struct spi_dev_s *)priv, 400000); + + /* Set default watermarks */ + + imx9_lpspi_putreg32(priv, IMX9_LPSPI_FCR_OFFSET, + LPSPI_FCR_TXWATER(0) | LPSPI_FCR_RXWATER(0)); + + /* Set Transmit Command Register */ + + imx9_lpspi_setbits((struct spi_dev_s *)priv, 8); + + imx9_lpspi_setmode((struct spi_dev_s *)priv, SPIDEV_MODE0); + + /* Enable LPSPI */ + + imx9_lpspi_modifyreg32(priv, IMX9_LPSPI_CR_OFFSET, 0, LPSPI_CR_MEN); +} + +/**************************************************************************** + * Name: spi_dmarxwait + * + * Description: + * Wait for DMA to complete. + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static int spi_dmarxwait(struct imx9_lpspidev_s *priv) +{ + int ret; + + /* Take the semaphore (perhaps waiting). If the result is zero, then the + * DMA must not really have completed. + */ + + do + { + ret = nxsem_wait_uninterruptible(&priv->rxsem); + + /* The only expected error is ECANCELED which would occur if the + * calling thread were canceled. + */ + + DEBUGASSERT(ret == OK || ret == -ECANCELED); + } + while (priv->rxresult == 0 && ret == OK); + + return ret; +} +#endif + +/**************************************************************************** + * Name: spi_dmatxwait + * + * Description: + * Wait for DMA to complete. + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static int spi_dmatxwait(struct imx9_lpspidev_s *priv) +{ + int ret; + + /* Take the semaphore (perhaps waiting). If the result is zero, then the + * DMA must not really have completed. + */ + + do + { + ret = nxsem_wait_uninterruptible(&priv->txsem); + + /* The only expected error is ECANCELED which would occur if the + * calling thread were canceled. + */ + + DEBUGASSERT(ret == OK || ret == -ECANCELED); + } + while (priv->txresult == 0 && ret == OK); + + return ret; +} +#endif + +/**************************************************************************** + * Name: spi_dmarxwakeup + * + * Description: + * Signal that DMA is complete + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static inline void spi_dmarxwakeup(struct imx9_lpspidev_s *priv) +{ + nxsem_post(&priv->rxsem); +} +#endif + +/**************************************************************************** + * Name: spi_dmatxwakeup + * + * Description: + * Signal that DMA is complete + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static inline void spi_dmatxwakeup(struct imx9_lpspidev_s *priv) +{ + nxsem_post(&priv->txsem); +} +#endif + +/**************************************************************************** + * Name: spi_dmarxcallback + * + * Description: + * Called when the RX DMA completes + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static void spi_dmarxcallback(DMACH_HANDLE handle, void *arg, bool done, + int result) +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)arg; + + priv->rxresult = result | 0x80000000; /* assure non-zero */ + spi_dmarxwakeup(priv); +} +#endif + +/**************************************************************************** + * Name: spi_dmatxcallback + * + * Description: + * Called when the RX DMA completes + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static void spi_dmatxcallback(DMACH_HANDLE handle, void *arg, bool done, + int result) +{ + struct imx9_lpspidev_s *priv = (struct imx9_lpspidev_s *)arg; + + /* Wake-up the SPI driver */ + + priv->txresult = result | 0x80000000; /* assure non-zero */ + spi_dmatxwakeup(priv); +} +#endif + +/**************************************************************************** + * Name: spi_dmarxstart + * + * Description: + * Start RX DMA + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static inline void spi_dmarxstart(struct imx9_lpspidev_s *priv) +{ + priv->rxresult = 0; + imx9_dmach_start(priv->rxdma, spi_dmarxcallback, priv); +} +#endif + +/**************************************************************************** + * Name: spi_dmatxstart + * + * Description: + * Start TX DMA + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI_DMA +static inline void spi_dmatxstart(struct imx9_lpspidev_s *priv) +{ + priv->txresult = 0; + imx9_dmach_start(priv->txdma, spi_dmatxcallback, priv); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_lpspibus_initialize + * + * Description: + * Initialize the selected SPI bus + * + * Input Parameters: + * Port number (for hardware that has multiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct spi_dev_s *imx9_lpspibus_initialize(int bus) +{ + struct imx9_lpspidev_s *priv = NULL; + + irqstate_t flags = enter_critical_section(); + +#ifdef CONFIG_IMX9_LPSPI1 + if (bus == 1) + { + /* Select SPI1 */ + + priv = &g_lpspi1dev; + + /* Only configure if the bus is not already configured */ + + if ((imx9_lpspi_getreg32(priv, IMX9_LPSPI_CR_OFFSET) + & LPSPI_CR_MEN) == 0) + { + /* Configure SPI1 pins: SCK, MISO, and MOSI */ + + imx9_iomux_configure(MUX_LPSPI1_SCK); + imx9_iomux_configure(MUX_LPSPI1_MISO); + imx9_iomux_configure(MUX_LPSPI1_MOSI); +#if defined(MUX_LPSPI1_CS) && defined(GPIO_LPSPI1_CS) + imx9_iomux_configure(MUX_LPSPI1_CS); + imx9_config_gpio(GPIO_LPSPI1_CS); +#endif +#if defined(GPIO_LPSPI1_DC) && defined(CONFIG_SPI_CMDDATA) + imx9_iomux_configure(GPIO_LPSPI1_DC); +#endif + + /* Set up default configuration: Master, 8-bit, etc. */ + + imx9_lpspi_bus_initialize(priv); + } + } + else +#endif +#ifdef CONFIG_IMX9_LPSPI2 + if (bus == 2) + { + /* Select SPI2 */ + + priv = &g_lpspi2dev; + + /* Only configure if the bus is not already configured */ + + if ((imx9_lpspi_getreg32(priv, IMX9_LPSPI_CR_OFFSET) + & LPSPI_CR_MEN) == 0) + { + /* Configure SPI2 pins: SCK, MISO, and MOSI */ + + imx9_iomux_configure(MUX_LPSPI2_SCK); + imx9_iomux_configure(MUX_LPSPI2_MISO); + imx9_iomux_configure(MUX_LPSPI2_MOSI); +#if defined(MUX_LPSPI2_CS) && defined(GPIO_LPSPI2_CS) + imx9_iomux_configure(MUX_LPSPI2_CS); + imx9_config_gpio(GPIO_LPSPI2_CS); +#endif +#if defined(GPIO_LPSPI2_DC) && defined(CONFIG_SPI_CMDDATA) + imx9_iomux_configure(GPIO_LPSPI2_DC); +#endif + + /* Set up default configuration: Master, 8-bit, etc. */ + + imx9_lpspi_bus_initialize(priv); + } + } + else +#endif +#ifdef CONFIG_IMX9_LPSPI3 + if (bus == 3) + { + /* Select SPI3 */ + + priv = &g_lpspi3dev; + + /* Only configure if the bus is not already configured */ + + if ((imx9_lpspi_getreg32(priv, IMX9_LPSPI_CR_OFFSET) + & LPSPI_CR_MEN) == 0) + { + /* Configure SPI3 pins: SCK, MISO, and MOSI */ + + imx9_iomux_configure(MUX_LPSPI3_SCK); + imx9_iomux_configure(MUX_LPSPI3_MISO); + imx9_iomux_configure(MUX_LPSPI3_MOSI); +#if defined(MUX_LPSPI3_CS) && defined(GPIO_LPSPI3_CS) + imx9_iomux_configure(MUX_LPSPI3_CS); + imx9_config_gpio(GPIO_LPSPI3_CS); +#endif +#if defined(GPIO_LPSPI3_DC) && defined(CONFIG_SPI_CMDDATA) + imx9_iomux_configure(GPIO_LPSPI3_DC); +#endif + + /* Set up default configuration: Master, 8-bit, etc. */ + + imx9_lpspi_bus_initialize(priv); + } + } + else +#endif +#ifdef CONFIG_IMX9_LPSPI4 + if (bus == 4) + { + /* Select SPI4 */ + + priv = &g_lpspi4dev; + + /* Only configure if the bus is not already configured */ + + if ((imx9_lpspi_getreg32(priv, IMX9_LPSPI_CR_OFFSET) + & LPSPI_CR_MEN) == 0) + { + /* Configure SPI4 pins: SCK, MISO, and MOSI */ + + imx9_iomux_configure(MUX_LPSPI4_SCK); + imx9_iomux_configure(MUX_LPSPI4_MISO); + imx9_iomux_configure(MUX_LPSPI4_MOSI); +#if defined(MUX_LPSPI4_CS) && defined(GPIO_LPSPI4_CS) + imx9_iomux_configure(MUX_LPSPI4_CS); + imx9_config_gpio(GPIO_LPSPI4_CS); +#endif +#if defined(GPIO_LPSPI4_DC) && defined(CONFIG_SPI_CMDDATA) + imx9_iomux_configure(GPIO_LPSPI4_DC); +#endif + + /* Set up default configuration: Master, 8-bit, etc. */ + + imx9_lpspi_bus_initialize(priv); + } + } + else +#endif +#ifdef CONFIG_IMX9_LPSPI5 + if (bus == 5) + { + /* Select SPI5 */ + + priv = &g_lpspi5dev; + + /* Only configure if the bus is not already configured */ + + if ((imx9_lpspi_getreg32(priv, IMX9_LPSPI_CR_OFFSET) + & LPSPI_CR_MEN) == 0) + { + /* Configure SPI5 pins: SCK, MISO, and MOSI */ + + imx9_iomux_configure(MUX_LPSPI5_SCK); + imx9_iomux_configure(MUX_LPSPI5_MISO); + imx9_iomux_configure(MUX_LPSPI5_MOSI); +#if defined(MUX_LPSPI5_CS) && defined(GPIO_LPSPI5_CS) + imx9_iomux_configure(MUX_LPSPI5_CS); + imx9_config_gpio(GPIO_LPSPI5_CS); +#endif +#if defined(GPIO_LPSPI5_DC) && defined(CONFIG_SPI_CMDDATA) + imx9_iomux_configure(GPIO_LPSPI5_DC); +#endif + + /* Set up default configuration: Master, 8-bit, etc. */ + + imx9_lpspi_bus_initialize(priv); + } + } + else +#endif +#ifdef CONFIG_IMX9_LPSPI6 + if (bus == 6) + { + /* Select SPI6 */ + + priv = &g_lpspi6dev; + + /* Only configure if the bus is not already configured */ + + if ((imx9_lpspi_getreg32(priv, IMX9_LPSPI_CR_OFFSET) + & LPSPI_CR_MEN) == 0) + { + /* Configure SPI6 pins: SCK, MISO, and MOSI */ + + imx9_iomux_configure(MUX_LPSPI6_SCK); + imx9_iomux_configure(MUX_LPSPI6_MISO); + imx9_iomux_configure(MUX_LPSPI6_MOSI); +#if defined(MUX_LPSPI6_CS) && defined(GPIO_LPSPI6_CS) + imx9_iomux_configure(MUX_LPSPI6_CS); + imx9_config_gpio(GPIO_LPSPI6_CS); +#endif +#if defined(GPIO_LPSPI6_DC) && defined(CONFIG_SPI_CMDDATA) + imx9_iomux_configure(GPIO_LPSPI6_DC); +#endif + + /* Set up default configuration: Master, 8-bit, etc. */ + + imx9_lpspi_bus_initialize(priv); + } + } + else +#endif +#ifdef CONFIG_IMX9_LPSPI7 + if (bus == 7) + { + /* Select SPI7 */ + + priv = &g_lpspi7dev; + + /* Only configure if the bus is not already configured */ + + if ((imx9_lpspi_getreg32(priv, IMX9_LPSPI_CR_OFFSET) + & LPSPI_CR_MEN) == 0) + { + /* Configure SPI7 pins: SCK, MISO, and MOSI */ + + imx9_iomux_configure(MUX_LPSPI7_SCK); + imx9_iomux_configure(MUX_LPSPI7_MISO); + imx9_iomux_configure(MUX_LPSPI7_MOSI); +#if defined(MUX_LPSPI7_CS) && defined(GPIO_LPSPI7_CS) + imx9_iomux_configure(MUX_LPSPI7_CS); + imx9_config_gpio(GPIO_LPSPI7_CS); +#endif +#if defined(GPIO_LPSPI7_DC) && defined(CONFIG_SPI_CMDDATA) + imx9_iomux_configure(GPIO_LPSPI7_DC); +#endif + + /* Set up default configuration: Master, 8-bit, etc. */ + + imx9_lpspi_bus_initialize(priv); + } + } + else +#endif +#ifdef CONFIG_IMX9_LPSPI8 + if (bus == 8) + { + /* Select SPI8 */ + + priv = &g_lpspi8dev; + + /* Only configure if the bus is not already configured */ + + if ((imx9_lpspi_getreg32(priv, IMX9_LPSPI_CR_OFFSET) + & LPSPI_CR_MEN) == 0) + { + /* Configure SPI6 pins: SCK, MISO, and MOSI */ + + imx9_iomux_configure(MUX_LPSPI8_SCK); + imx9_iomux_configure(MUX_LPSPI8_MISO); + imx9_iomux_configure(MUX_LPSPI8_MOSI); +#if defined(MUX_LPSPI8_CS) && defined(GPIO_LPSPI8_CS) + imx9_iomux_configure(MUX_LPSPI8_CS); + imx9_config_gpio(GPIO_LPSPI8_CS); +#endif +#if defined(GPIO_LPSPI8_DC) && defined(CONFIG_SPI_CMDDATA) + imx9_iomux_configure(GPIO_LPSPI8_DC); +#endif + + /* Set up default configuration: Master, 8-bit, etc. */ + + imx9_lpspi_bus_initialize(priv); + } + } + else +#endif + { + spierr("ERROR: Unsupported SPI bus: %d\n", bus); + } + +#ifdef CONFIG_IMX9_LPSPI_DMA + if (priv->rxch && priv->txch) + { + if (priv->txdma == NULL && priv->rxdma == NULL) + { + priv->txdma = imx9_dmach_alloc(priv->txch, 0); + priv->rxdma = imx9_dmach_alloc(priv->rxch, 0); + DEBUGASSERT(priv->rxdma && priv->txdma); + } + + if (priv->txbuf == NULL && priv->rxbuf == NULL) + { + priv->txbuf = imx9_dma_alloc(CONFIG_IMX9_LPSPI_DMA_BUFFER_SIZE); + priv->rxbuf = imx9_dma_alloc(CONFIG_IMX9_LPSPI_DMA_BUFFER_SIZE); + DEBUGASSERT(priv->txbuf && priv->rxbuf); + } + } + else + { + priv->rxdma = NULL; + priv->txdma = NULL; + } +#endif + + leave_critical_section(flags); + + return (struct spi_dev_s *)priv; +} + +#endif /* CONFIG_IMX9_LPSPI */ diff --git a/arch/arm64/src/imx9/imx9_lpspi.h b/arch/arm64/src/imx9/imx9_lpspi.h new file mode 100644 index 0000000000000..00907320698d5 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_lpspi.h @@ -0,0 +1,139 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_lpspi.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_LPSPI_H +#define __ARCH_ARM64_SRC_IMX9_IMX9_LPSPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "chip.h" +#include "hardware/imx9_lpspi.h" + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +struct spi_dev_s; /* Forward reference */ + +/**************************************************************************** + * Name: imx9_lpspibus_initialize + * + * Description: + * Initialize the selected SPI bus + * + * Input Parameters: + * bus number (for hardware that has multiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct spi_dev_s *imx9_lpspibus_initialize(int bus); + +/**************************************************************************** + * Name: imx9_lpspi1/2/...select and imx9_lpspi1/2/...status + * + * Description: + * The external functions, imx9_lpspi1/2/...select, + * imx9_lpspi1/2/...status, and imx9_lpspi1/2/...cmddata must be + * provided by board-specific logic. These are implementations of the + * select, status, and cmddata methods of the SPI interface defined by + * struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including imx9_lpspibus_initialize()) are provided by common IMX9 + * logic. To use this common SPI logic on your board: + * + * 1. Provide logic in imx9_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide imx9_lpspi1/2/...select() and imx9_lpspi1/2/...status() + * functions in your board-specific logic. These functions will perform + * chip selection and status operations using GPIOs in the way your + * board is configured. + * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, + * then provide imx9_lpspi1/2/...cmddata() functions in your + * board-specific logic. These functions will perform cmd/data selection + * operations using GPIOs in the way your board is configured. + * 4. Add a calls to imx9_lpspibus_initialize() in your low level + * application initialization logic + * 5. The handle returned by imx9_lpspibus_initialize() may then be used + * to bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +void imx9_lpspi_select(struct spi_dev_s *dev, + uint32_t devid, bool selected); +uint8_t imx9_lpspi_status(struct spi_dev_s *dev, uint32_t devid); +int imx9_lpspi_cmddata(struct spi_dev_s *dev, + uint32_t devid, bool cmd); + +/**************************************************************************** + * Name: imx9_lpspi1/2/...register + * + * Description: + * If the board supports a card detect callback to inform the SPI-based + * MMC/SD driver when an SD card is inserted or removed, then + * CONFIG_SPI_CALLBACK should be defined and the following function(s) + * must be implemented. These functions implements the registercallback + * method of the SPI interface (see include/nuttx/spi/spi.h for details) + * + * Input Parameters: + * dev - Device-specific state data + * callback - The function to call on the media change + * arg - A caller provided value to return with the callback + * + * Returned Value: + * 0 on success; negated errno on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CALLBACK +int imx9_lpspi_register(struct spi_dev_s *dev, + spi_mediachange_t callback, + void *arg); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM64_SRC_IMX9_IMX9_LPSPI_H */ diff --git a/arch/arm64/src/imx9/imx9_lpuart.c b/arch/arm64/src/imx9/imx9_lpuart.c new file mode 100644 index 0000000000000..601770b01f840 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_lpuart.c @@ -0,0 +1,2821 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_lpuart.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "arm64_internal.h" +#include "hardware/imx9_lpuart.h" +#include "hardware/imx9_pinmux.h" +#include "imx9_lowputc.h" +#include "imx9_serial.h" + +#if defined(SERIAL_HAVE_TXDMA) || defined(SERIAL_HAVE_RXDMA) +# include "chip.h" +# include "imx9_edma.h" +# include "hardware/imx9_dmamux.h" +#endif + +#ifdef USE_SERIALDRIVER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The DMA buffer size when using RX DMA to emulate a FIFO. + * + * When streaming data, the generic serial layer will be called every time + * the FIFO receives half this number of bytes. + * + * This buffer size should be an even multiple of the Cortex-A55 D-Cache line + * size, ARMV8A_DCACHE_LINESIZE, so that it can be individually invalidated. + */ + +# if !defined(ARMV8A_DCACHE_LINESIZE) || ARMV8A_DCACHE_LINESIZE == 0 +# undef ARMV8A_DCACHE_LINESIZE +# define ARMV8A_DCACHE_LINESIZE 64 +# endif + +# if !defined(CONFIG_IMX9_SERIAL_RXDMA_BUFFER_SIZE) || \ + (CONFIG_IMX9_SERIAL_RXDMA_BUFFER_SIZE < ARMV8A_DCACHE_LINESIZE) +# undef CONFIG_IMX9_SERIAL_RXDMA_BUFFER_SIZE +# define CONFIG_IMX9_SERIAL_RXDMA_BUFFER_SIZE ARMV8A_DCACHE_LINESIZE +# endif + +# define RXDMA_BUFFER_MASK (ARMV8A_DCACHE_LINESIZE - 1) +# define RXDMA_BUFFER_SIZE ((CONFIG_IMX9_SERIAL_RXDMA_BUFFER_SIZE \ + + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) + +/* The DMA buffer size when using TX DMA. + * + * This TX buffer size should be an even multiple of the Cortex-A55 D-Cache + * line size, ARMV8A_DCACHE_LINESIZE, so that it can be individually + * invalidated. + */ + +#define TXDMA_BUFFER_MASK (ARMV8A_DCACHE_LINESIZE - 1) +#define TXDMA_BUFFER_SIZE ((CONFIG_IMX9_SERIAL_RXDMA_BUFFER_SIZE \ + + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK) + +/* Buffers need to be aligned and multiples of ARMV8A_DCACHE_LINESIZE */ + +#if defined(CONFIG_ARM64_DCACHE_DISABLE) +# define TXDMA_BUF_SIZE(b) (b) +# define TXDMA_BUF_ALIGN +#else +# define TXDMA_BUF_SIZE(b) (((b) + TXDMA_BUFFER_MASK) & ~TXDMA_BUFFER_MASK) +# define TXDMA_BUF_ALIGN aligned_data(ARMV8A_DCACHE_LINESIZE); +#endif + +#if !defined(CONFIG_LPUART1_TXDMA) +# define LPUART1_TXBUFSIZE_ADJUSTED CONFIG_LPUART1_TXBUFSIZE +# define LPUART1_TXBUFSIZE_ALGN +#else +# define LPUART1_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART1_TXBUFSIZE) +# define LPUART1_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART2_TXDMA) +# define LPUART2_TXBUFSIZE_ADJUSTED CONFIG_LPUART2_TXBUFSIZE +# define LPUART2_TXBUFSIZE_ALGN +#else +# define LPUART2_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART2_TXBUFSIZE) +# define LPUART2_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART3_TXDMA) +# define LPUART3_TXBUFSIZE_ADJUSTED CONFIG_LPUART3_TXBUFSIZE +# define LPUART3_TXBUFSIZE_ALGN +#else +# define LPUART3_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART3_TXBUFSIZE) +# define LPUART3_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART4_TXDMA) +# define LPUART4_TXBUFSIZE_ADJUSTED CONFIG_LPUART4_TXBUFSIZE +# define LPUART4_TXBUFSIZE_ALGN +#else +# define LPUART4_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART4_TXBUFSIZE) +# define LPUART4_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART5_TXDMA) +# define LPUART5_TXBUFSIZE_ADJUSTED CONFIG_LPUART5_TXBUFSIZE +# define LPUART5_TXBUFSIZE_ALGN +#else +# define LPUART5_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART5_TXBUFSIZE) +# define LPUART5_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART6_TXDMA) +# define LPUART6_TXBUFSIZE_ADJUSTED CONFIG_LPUART6_TXBUFSIZE +# define LPUART6_TXBUFSIZE_ALGN +#else +# define LPUART6_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART6_TXBUFSIZE) +# define LPUART6_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART7_TXDMA) +# define LPUART7_TXBUFSIZE_ADJUSTED CONFIG_LPUART7_TXBUFSIZE +# define LPUART7_TXBUFSIZE_ALGN +#else +# define LPUART7_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART7_TXBUFSIZE) +# define LPUART7_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +#if !defined(CONFIG_LPUART8_TXDMA) +# define LPUART8_TXBUFSIZE_ADJUSTED CONFIG_LPUART8_TXBUFSIZE +# define LPUART8_TXBUFSIZE_ALGN +#else +# define LPUART8_TXBUFSIZE_ADJUSTED TXDMA_BUF_SIZE(CONFIG_LPUART8_TXBUFSIZE) +# define LPUART8_TXBUFSIZE_ALGN TXDMA_BUF_ALIGN +#endif + +/* Which LPUART with be console? */ + +#if defined(CONFIG_LPUART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_lpuart1priv /* LPUART1 is console */ +# if defined(CONFIG_LPUART1_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART1_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif +#elif defined(CONFIG_LPUART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_lpuart2priv /* LPUART2 is console */ +# if defined(CONFIG_LPUART2_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART2_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif +#elif defined(CONFIG_LPUART3_SERIAL_CONSOLE) +# define CONSOLE_DEV g_lpuart3priv /* LPUART3 is console */ +# if defined(CONFIG_LPUART3_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART3_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif +#elif defined(CONFIG_LPUART4_SERIAL_CONSOLE) +# define CONSOLE_DEV g_lpuart4priv /* LPUART4 is console */ +# if defined(CONFIG_LPUART4_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART4_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif +#elif defined(CONFIG_LPUART5_SERIAL_CONSOLE) +# define CONSOLE_DEV g_lpuart5priv /* LPUART5 is console */ +# if defined(CONFIG_LPUART5_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART5_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif +#elif defined(CONFIG_LPUART6_SERIAL_CONSOLE) +# define CONSOLE_DEV g_lpuart6priv /* LPUART6 is console */ +# if defined(CONFIG_LPUART6_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART6_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif +#elif defined(CONFIG_LPUART7_SERIAL_CONSOLE) +# define CONSOLE_DEV g_lpuart7priv /* LPUART7 is console */ +# if defined(CONFIG_LPUART7_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART7_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif +#elif defined(CONFIG_LPUART8_SERIAL_CONSOLE) +# define CONSOLE_DEV g_lpuart8priv /* LPUART8 is console */ +# if defined(CONFIG_LPUART8_RXDMA) +# define SERIAL_HAVE_CONSOLE_RXDMA 1 +# endif +# if defined(CONFIG_LPUART8_TXDMA) +# define SERIAL_HAVE_CONSOLE_TXDMA 1 +# endif +#endif + +#if defined(SERIAL_HAVE_CONSOLE_RXDMA) || defined(SERIAL_HAVE_CONSOLE_TXDMA) +# define SERIAL_HAVE_CONSOLE_DMA +#endif + +#ifdef CONFIG_IMX9_LPUART1 +#define TTYS0_DEV g_lpuart1priv /* LPUART1 is ttyS0 */ +#endif + +#ifdef CONFIG_IMX9_LPUART2 +#define TTYS1_DEV g_lpuart2priv /* LPUART2 is ttyS1 */ +#endif + +#ifdef CONFIG_IMX9_LPUART3 +#define TTYS2_DEV g_lpuart3priv /* LPUART3 is ttyS2 */ +#endif + +#ifdef CONFIG_IMX9_LPUART4 +#define TTYS3_DEV g_lpuart4priv /* LPUART4 is ttyS3 */ +#endif + +#ifdef CONFIG_IMX9_LPUART5 +#define TTYS4_DEV g_lpuart5priv /* LPUART5 is ttyS4 */ +#endif + +#ifdef CONFIG_IMX9_LPUART6 +#define TTYS5_DEV g_lpuart6priv /* LPUART6 is ttyS5 */ +#endif + +#ifdef CONFIG_IMX9_LPUART7 +#define TTYS6_DEV g_lpuart7priv /* LPUART7 is ttyS6 */ +#endif + +#ifdef CONFIG_IMX9_LPUART8 +#define TTYS7_DEV g_lpuart8priv /* LPUART8 is ttyS7 */ +#endif + +/* Power management definitions */ + +#if defined(CONFIG_PM) && !defined(CONFIG_IMX9_PM_SERIAL_ACTIVITY) +# define CONFIG_IMX9_PM_SERIAL_ACTIVITY 10 +#endif + +#if defined(CONFIG_PM) +# define PM_IDLE_DOMAIN 0 /* Revisit */ +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct imx9_uart_s +{ + struct uart_dev_s dev; /* Generic UART device */ + const uint32_t uartbase; /* Base address of UART registers */ + const int uartnum; /* LPUART number 1-8 */ + uint32_t baud; /* Configured baud */ + uint32_t ie; /* Saved enabled interrupts */ + uint8_t irq; /* IRQ associated with this UART */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ +#if defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL) + uint8_t inviflow:1; /* Invert RTS sense */ + const uint32_t rts_gpio; /* LPUART RTS GPIO pin configuration */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + const uint32_t cts_gpio; /* LPUART CTS GPIO pin configuration */ +#endif + uint8_t stopbits2:1; /* 1: Configure with 2 stop bits vs 1 */ +#ifdef CONFIG_SERIAL_IFLOWCONTROL + uint8_t iflow:1; /* input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + uint8_t oflow:1; /* output flow control (CTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_RS485CONTROL + uint8_t rs485mode:1; /* We are in RS485 (RTS on TX) mode */ +#endif + /* TX DMA state */ + +#ifdef SERIAL_HAVE_TXDMA + const unsigned int txch; /* DMAMUX source of TX DMA request */ + DMACH_HANDLE txdma; /* currently-open transmit DMA stream */ +#endif + + /* RX DMA state */ + +#ifdef SERIAL_HAVE_RXDMA + const unsigned int rxch; /* DMAMUX source of RX DMA request */ + DMACH_HANDLE rxdma; /* currently-open receive DMA stream */ + bool rxenable; /* DMA-based reception en/disable */ + uint32_t rxdmanext; /* Next byte in the DMA buffer to be read */ +#ifndef CONFIG_ARM64_DCACHE_DISABLE + uint32_t rxdmaavail; /* Number of bytes available without need to + * to invalidate the data cache */ +#endif + char *const rxfifo; /* Receive DMA buffer */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline uint32_t imx9_serialin(struct imx9_uart_s *priv, + uint32_t offset); +static inline void imx9_serialout(struct imx9_uart_s *priv, + uint32_t offset, uint32_t value); +static inline void imx9_disableuartint(struct imx9_uart_s *priv, + uint32_t *ie); +static inline void imx9_restoreuartint(struct imx9_uart_s *priv, + uint32_t ie); + +static int imx9_setup(struct uart_dev_s *dev); +static void imx9_shutdown(struct uart_dev_s *dev); +static int imx9_attach(struct uart_dev_s *dev); +static void imx9_detach(struct uart_dev_s *dev); +static int imx9_interrupt(int irq, void *context, void *arg); +static int imx9_ioctl(struct file *filep, int cmd, unsigned long arg); +#if !defined(SERIAL_HAVE_ONLY_RXDMA) +static int imx9_receive(struct uart_dev_s *dev, unsigned int *status); +static void imx9_rxint(struct uart_dev_s *dev, bool enable); +static bool imx9_rxavailable(struct uart_dev_s *dev); +#endif +#if !defined(SERIAL_HAVE_ONLY_TXDMA) +static void imx9_txint(struct uart_dev_s *dev, bool enable); +#endif + +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool imx9_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper); +#endif +static void imx9_send(struct uart_dev_s *dev, int ch); + +static bool imx9_txready(struct uart_dev_s *dev); + +#ifdef SERIAL_HAVE_TXDMA +static void imx9_dma_send(struct uart_dev_s *dev); +static void imx9_dma_txint(struct uart_dev_s *dev, bool enable); +static void imx9_dma_txavailable(struct uart_dev_s *dev); +static void imx9_dma_txcallback(DMACH_HANDLE handle, void *arg, bool done, + int result); +#endif + +#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA) +static int imx9_dma_setup(struct uart_dev_s *dev); +static void imx9_dma_shutdown(struct uart_dev_s *dev); +#endif + +#ifdef SERIAL_HAVE_RXDMA +static int imx9_dma_receive(struct uart_dev_s *dev, + unsigned int *status); +#ifdef CONFIG_PM +static void imx9_dma_reenable(struct imx9_uart_s *priv); +#endif +static void imx9_dma_rxint(struct uart_dev_s *dev, bool enable); +static bool imx9_dma_rxavailable(struct uart_dev_s *dev); + +static void imx9_dma_rxcallback(DMACH_HANDLE handle, void *arg, bool done, + int result); +#endif + +static bool imx9_txempty(struct uart_dev_s *dev); + +#ifdef CONFIG_PM +static void up_pm_notify(struct pm_callback_s *cb, int dowmin, + enum pm_state_e pmstate); +static int up_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Serial driver UART operations */ + +#if !defined(SERIAL_HAVE_ONLY_TXDMA) && !defined(SERIAL_HAVE_ONLY_RXDMA) +static const struct uart_ops_s g_lpuart_ops = +{ + .setup = imx9_setup, + .shutdown = imx9_shutdown, + .attach = imx9_attach, + .detach = imx9_detach, + .ioctl = imx9_ioctl, + .receive = imx9_receive, + .rxint = imx9_rxint, + .rxavailable = imx9_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = imx9_rxflowcontrol, +#endif + .send = imx9_send, + .txint = imx9_txint, + .txready = imx9_txready, + .txempty = imx9_txempty, +}; +#endif + +#if defined(SERIAL_HAVE_RXDMA) && defined(SERIAL_HAVE_TXDMA) +static const struct uart_ops_s g_lpuart_rxtxdma_ops = +{ + .setup = imx9_dma_setup, + .shutdown = imx9_dma_shutdown, + .attach = imx9_attach, + .detach = imx9_detach, + .ioctl = imx9_ioctl, + .receive = imx9_dma_receive, + .rxint = imx9_dma_rxint, + .rxavailable = imx9_dma_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = imx9_rxflowcontrol, +#endif + .send = imx9_send, + .txint = imx9_dma_txint, + .txready = imx9_txready, + .txempty = imx9_txempty, + .dmatxavail = imx9_dma_txavailable, + .dmasend = imx9_dma_send, +}; +#endif + +#if !defined(SERIAL_HAVE_ONLY_DMA) && defined(SERIAL_HAVE_RXDMA) +static const struct uart_ops_s g_lpuart_rxdma_ops = +{ + .setup = imx9_dma_setup, + .shutdown = imx9_dma_shutdown, + .attach = imx9_attach, + .detach = imx9_detach, + .ioctl = imx9_ioctl, + .receive = imx9_dma_receive, + .rxint = imx9_dma_rxint, + .rxavailable = imx9_dma_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = imx9_rxflowcontrol, +#endif + .send = imx9_send, + .txint = imx9_txint, + .txready = imx9_txready, + .txempty = imx9_txempty, +}; +#endif + +#if !defined(SERIAL_HAVE_ONLY_DMA) && defined(SERIAL_HAVE_TXDMA) +static const struct uart_ops_s g_lpuart_txdma_ops = +{ + .setup = imx9_dma_setup, + .shutdown = imx9_dma_shutdown, + .attach = imx9_attach, + .detach = imx9_detach, + .ioctl = imx9_ioctl, + .receive = imx9_receive, + .rxint = imx9_rxint, + .rxavailable = imx9_rxavailable, + #ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = imx9_rxflowcontrol, + #endif + .send = imx9_send, + .txint = imx9_dma_txint, + .txready = imx9_txready, + .txempty = imx9_txempty, + .dmatxavail = imx9_dma_txavailable, + .dmasend = imx9_dma_send, +}; +#endif + +/* Avoid unused warning */ +#if !defined(SERIAL_HAVE_ONLY_DMA) && defined(SERIAL_HAVE_RXDMA) +const struct uart_ops_s *g_o0 = &g_lpuart_rxdma_ops; +#endif +#if !defined(SERIAL_HAVE_ONLY_DMA) && defined(SERIAL_HAVE_TXDMA) +const struct uart_ops_s *g_o1 = &g_lpuart_txdma_ops; +#endif + +/* I/O buffers */ + +#ifdef CONFIG_LPUART1_RXDMA +static char g_lpuart1rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV8A_DCACHE_LINESIZE); +#endif + +# ifdef CONFIG_LPUART2_RXDMA +static char g_lpuart2rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV8A_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART3_RXDMA +static char g_lpuart3rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV8A_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART4_RXDMA +static char g_lpuart4rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV8A_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART5_RXDMA +static char g_lpuart5rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV8A_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART6_RXDMA +static char g_lpuart6rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV8A_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART7_RXDMA +static char g_lpuart7rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV8A_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_LPUART8_RXDMA +static char g_lpuart8rxfifo[RXDMA_BUFFER_SIZE] + aligned_data(ARMV8A_DCACHE_LINESIZE); +#endif + +#ifdef CONFIG_IMX9_LPUART1 +static char g_lpuart1rxbuffer[CONFIG_LPUART1_RXBUFSIZE]; +static char g_lpuart1txbuffer[LPUART1_TXBUFSIZE_ADJUSTED] + LPUART1_TXBUFSIZE_ALGN; +#endif + +#ifdef CONFIG_IMX9_LPUART2 +static char g_lpuart2rxbuffer[CONFIG_LPUART2_RXBUFSIZE]; +static char g_lpuart2txbuffer[LPUART2_TXBUFSIZE_ADJUSTED] + LPUART2_TXBUFSIZE_ALGN; +#endif + +#ifdef CONFIG_IMX9_LPUART3 +static char g_lpuart3rxbuffer[CONFIG_LPUART3_RXBUFSIZE]; +static char g_lpuart3txbuffer[LPUART3_TXBUFSIZE_ADJUSTED] + LPUART3_TXBUFSIZE_ALGN; +#endif + +#ifdef CONFIG_IMX9_LPUART4 +static char g_lpuart4rxbuffer[CONFIG_LPUART4_RXBUFSIZE]; +static char g_lpuart4txbuffer[LPUART4_TXBUFSIZE_ADJUSTED] + LPUART4_TXBUFSIZE_ALGN; +#endif + +#ifdef CONFIG_IMX9_LPUART5 +static char g_lpuart5rxbuffer[CONFIG_LPUART5_RXBUFSIZE]; +static char g_lpuart5txbuffer[LPUART5_TXBUFSIZE_ADJUSTED] + LPUART5_TXBUFSIZE_ALGN; +#endif + +#ifdef CONFIG_IMX9_LPUART6 +static char g_lpuart6rxbuffer[CONFIG_LPUART6_RXBUFSIZE]; +static char g_lpuart6txbuffer[LPUART6_TXBUFSIZE_ADJUSTED] + LPUART6_TXBUFSIZE_ALGN; +#endif + +#ifdef CONFIG_IMX9_LPUART7 +static char g_lpuart7rxbuffer[CONFIG_LPUART7_RXBUFSIZE]; +static char g_lpuart7txbuffer[LPUART7_TXBUFSIZE_ADJUSTED] + LPUART7_TXBUFSIZE_ALGN; +#endif + +#ifdef CONFIG_IMX9_LPUART8 +static char g_lpuart8rxbuffer[CONFIG_LPUART8_RXBUFSIZE]; +static char g_lpuart8txbuffer[LPUART8_TXBUFSIZE_ADJUSTED] \ + LPUART8_TXBUFSIZE_ALGN; +#endif + +#ifdef CONFIG_IMX9_LPUART1 +static struct imx9_uart_s g_lpuart1priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_LPUART1_RXBUFSIZE, + .buffer = g_lpuart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART1_TXBUFSIZE, + .buffer = g_lpuart1txbuffer, + }, +# if defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, +# elif defined(CONFIG_LPUART1_RXDMA) && !defined(CONFIG_LPUART1_TXDMA) + .ops = &g_lpuart_rxdma_ops, +# elif !defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_TXDMA) + .ops = &g_lpuart_txdma_ops, +# else + .ops = &g_lpuart_ops, +# endif + }, + + .uartbase = IMX9_LPUART1_BASE, + .uartnum = 1, + .baud = CONFIG_LPUART1_BAUD, + .irq = IMX9_IRQ_LPUART1, + .parity = CONFIG_LPUART1_PARITY, + .bits = CONFIG_LPUART1_BITS, + .stopbits2 = CONFIG_LPUART1_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART1_OFLOWCONTROL) + .oflow = 1, + .cts_gpio = GPIO_LPUART1_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL) + .iflow = 1, +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART1_IFLOWCONTROL))) + .rts_gpio = GPIO_LPUART1_RTS, +# endif + +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART1_INVERTIFLOWCONTROL) + .inviflow = 1, +# endif + +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART1_RS485RTSCONTROL) + .rs485mode = 1, +# endif + +# ifdef CONFIG_LPUART1_TXDMA + .txch = DMA_REQUEST_MUXLPUART1TX, +# endif +# ifdef CONFIG_LPUART1_RXDMA + .rxch = DMA_REQUEST_MUXLPUART1RX, + .rxfifo = g_lpuart1rxfifo, +# endif +}; +#endif + +#ifdef CONFIG_IMX9_LPUART2 +static struct imx9_uart_s g_lpuart2priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_LPUART2_RXBUFSIZE, + .buffer = g_lpuart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART2_TXBUFSIZE, + .buffer = g_lpuart2txbuffer, + }, +# if defined(CONFIG_LPUART2_RXDMA) && defined(CONFIG_LPUART2_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, +# elif defined(CONFIG_LPUART2_RXDMA) && !defined(CONFIG_LPUART2_TXDMA) + .ops = &g_lpuart_rxdma_ops, +# elif !defined(CONFIG_LPUART2_RXDMA) && defined(CONFIG_LPUART2_TXDMA) + .ops = &g_lpuart_txdma_ops, +# else + .ops = &g_lpuart_ops, +# endif + }, + + .uartbase = IMX9_LPUART2_BASE, + .uartnum = 2, + .baud = CONFIG_LPUART2_BAUD, + .irq = IMX9_IRQ_LPUART2, + .parity = CONFIG_LPUART2_PARITY, + .bits = CONFIG_LPUART2_BITS, + .stopbits2 = CONFIG_LPUART2_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART2_OFLOWCONTROL) + .oflow = 1, + .cts_gpio = GPIO_LPUART2_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL) + .iflow = 1, +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART2_IFLOWCONTROL))) + .rts_gpio = GPIO_LPUART2_RTS, +# endif + +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART2_INVERTIFLOWCONTROL) + .inviflow = 1, +# endif + +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART2_RS485RTSCONTROL) + .rs485mode = 1, +# endif + +# ifdef CONFIG_LPUART2_TXDMA + .txch = DMA_REQUEST_MUXLPUART2TX, +# endif +# ifdef CONFIG_LPUART2_RXDMA + .rxch = DMA_REQUEST_MUXLPUART2RX, + .rxfifo = g_lpuart2rxfifo, +# endif +}; +#endif + +#ifdef CONFIG_IMX9_LPUART3 +static struct imx9_uart_s g_lpuart3priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_LPUART3_RXBUFSIZE, + .buffer = g_lpuart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART3_TXBUFSIZE, + .buffer = g_lpuart3txbuffer, + }, +# if defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, +# elif defined(CONFIG_LPUART3_RXDMA) && !defined(CONFIG_LPUART3_TXDMA) + .ops = &g_lpuart_rxdma_ops, +# elif !defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_TXDMA) + .ops = &g_lpuart_txdma_ops, +# else + .ops = &g_lpuart_ops, +# endif + }, + + .uartbase = IMX9_LPUART3_BASE, + .uartnum = 3, + .baud = CONFIG_LPUART3_BAUD, + .irq = IMX9_IRQ_LPUART3, + .parity = CONFIG_LPUART3_PARITY, + .bits = CONFIG_LPUART3_BITS, + .stopbits2 = CONFIG_LPUART3_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART3_OFLOWCONTROL) + .oflow = 1, + .cts_gpio = GPIO_LPUART3_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL) + .iflow = 1, +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART3_IFLOWCONTROL))) + .rts_gpio = GPIO_LPUART3_RTS, +# endif + +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART3_INVERTIFLOWCONTROL) + .inviflow = 1, +# endif + +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART3_RS485RTSCONTROL) + .rs485mode = 1, +# endif + +# ifdef CONFIG_LPUART3_TXDMA + .txch = DMA_REQUEST_MUXLPUART3TX, +# endif +# ifdef CONFIG_LPUART3_RXDMA + .rxch = DMA_REQUEST_MUXLPUART3RX, + .rxfifo = g_lpuart3rxfifo, +# endif +}; +#endif + +#ifdef CONFIG_IMX9_LPUART4 +static struct imx9_uart_s g_lpuart4priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_LPUART4_RXBUFSIZE, + .buffer = g_lpuart4rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART4_TXBUFSIZE, + .buffer = g_lpuart4txbuffer, + }, +# if defined(CONFIG_LPUART4_RXDMA) && defined(CONFIG_LPUART4_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, +# elif defined(CONFIG_LPUART4_RXDMA) && !defined(CONFIG_LPUART4_TXDMA) + .ops = &g_lpuart_rxdma_ops, +# elif !defined(CONFIG_LPUART4_RXDMA) && defined(CONFIG_LPUART4_TXDMA) + .ops = &g_lpuart_txdma_ops, +# else + .ops = &g_lpuart_ops, +# endif + }, + + .uartbase = IMX9_LPUART4_BASE, + .uartnum = 4, + .baud = CONFIG_LPUART4_BAUD, + .irq = IMX9_IRQ_LPUART4, + .parity = CONFIG_LPUART4_PARITY, + .bits = CONFIG_LPUART4_BITS, + .stopbits2 = CONFIG_LPUART4_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART4_OFLOWCONTROL) + .oflow = 1, + .cts_gpio = GPIO_LPUART4_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL) + .iflow = 1, +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART4_IFLOWCONTROL))) + .rts_gpio = GPIO_LPUART4_RTS, +# endif + +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART4_INVERTIFLOWCONTROL) + .inviflow = 1, +# endif + +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART4_RS485RTSCONTROL) + .rs485mode = 1, +# endif + +# ifdef CONFIG_LPUART4_TXDMA + .txch = DMA_REQUEST_MUXLPUART4TX, +# endif +# ifdef CONFIG_LPUART4_RXDMA + .rxch = DMA_REQUEST_MUXLPUART4RX, + .rxfifo = g_lpuart4rxfifo, +# endif +}; +#endif + +#ifdef CONFIG_IMX9_LPUART5 +static struct imx9_uart_s g_lpuart5priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_LPUART5_RXBUFSIZE, + .buffer = g_lpuart5rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART5_TXBUFSIZE, + .buffer = g_lpuart5txbuffer, + }, +# if defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, +# elif defined(CONFIG_LPUART5_RXDMA) && !defined(CONFIG_LPUART5_TXDMA) + .ops = &g_lpuart_rxdma_ops, +# elif !defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_TXDMA) + .ops = &g_lpuart_txdma_ops, +# else + .ops = &g_lpuart_ops, +# endif + }, + + .uartbase = IMX9_LPUART5_BASE, + .uartnum = 5, + .baud = CONFIG_LPUART5_BAUD, + .irq = IMX9_IRQ_LPUART5, + .parity = CONFIG_LPUART5_PARITY, + .bits = CONFIG_LPUART5_BITS, + .stopbits2 = CONFIG_LPUART5_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART5_OFLOWCONTROL) + .oflow = 1, + .cts_gpio = GPIO_LPUART5_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL) + .iflow = 1, +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART5_IFLOWCONTROL))) + .rts_gpio = GPIO_LPUART5_RTS, +# endif + +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART5_INVERTIFLOWCONTROL) + .inviflow = 1, +# endif + +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART5_RS485RTSCONTROL) + .rs485mode = 1, +# endif + +# ifdef CONFIG_LPUART5_TXDMA + .txch = DMA_REQUEST_MUXLPUART5TX, +# endif +# ifdef CONFIG_LPUART5_RXDMA + .rxch = DMA_REQUEST_MUXLPUART5RX, + .rxfifo = g_lpuart5rxfifo, +# endif +}; +#endif + +#ifdef CONFIG_IMX9_LPUART6 +static struct imx9_uart_s g_lpuart6priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_LPUART6_RXBUFSIZE, + .buffer = g_lpuart6rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART6_TXBUFSIZE, + .buffer = g_lpuart6txbuffer, + }, +# if defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, +# elif defined(CONFIG_LPUART6_RXDMA) && !defined(CONFIG_LPUART6_TXDMA) + .ops = &g_lpuart_rxdma_ops, +# elif !defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_TXDMA) + .ops = &g_lpuart_txdma_ops, +# else + .ops = &g_lpuart_ops, +# endif + }, + + .uartbase = IMX9_LPUART6_BASE, + .uartnum = 6, + .baud = CONFIG_LPUART6_BAUD, + .irq = IMX9_IRQ_LPUART6, + .parity = CONFIG_LPUART6_PARITY, + .bits = CONFIG_LPUART6_BITS, + .stopbits2 = CONFIG_LPUART6_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART6_OFLOWCONTROL) + .oflow = 1, + .cts_gpio = GPIO_LPUART6_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL) + .iflow = 1, +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART6_IFLOWCONTROL))) + .rts_gpio = GPIO_LPUART6_RTS, +# endif + +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART6_INVERTIFLOWCONTROL) + .inviflow = 1, +# endif + +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART6_RS485RTSCONTROL) + .rs485mode = 1, +# endif + +# ifdef CONFIG_LPUART6_TXDMA + .txch = DMA_REQUEST_MUXLPUART6TX, +# endif +# ifdef CONFIG_LPUART6_RXDMA + .rxch = DMA_REQUEST_MUXLPUART6RX, + .rxfifo = g_lpuart6rxfifo, +# endif +}; +#endif + +#ifdef CONFIG_IMX9_LPUART7 +static struct imx9_uart_s g_lpuart7priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_LPUART7_RXBUFSIZE, + .buffer = g_lpuart7rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART7_TXBUFSIZE, + .buffer = g_lpuart7txbuffer, + }, +# if defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, +# elif defined(CONFIG_LPUART7_RXDMA) && !defined(CONFIG_LPUART7_TXDMA) + .ops = &g_lpuart_rxdma_ops, +# elif !defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_TXDMA) + .ops = &g_lpuart_txdma_ops, +# else + .ops = &g_lpuart_ops, +# endif + }, + + .uartbase = IMX9_LPUART7_BASE, + .uartnum = 7, + .baud = CONFIG_LPUART7_BAUD, + .irq = IMX9_IRQ_LPUART7, + .parity = CONFIG_LPUART7_PARITY, + .bits = CONFIG_LPUART7_BITS, + .stopbits2 = CONFIG_LPUART7_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART7_OFLOWCONTROL) + .oflow = 1, + .cts_gpio = GPIO_LPUART7_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL) + .iflow = 1, +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART7_IFLOWCONTROL))) + .rts_gpio = GPIO_LPUART7_RTS, +# endif + +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART7_INVERTIFLOWCONTROL) + .inviflow = 1, +# endif + +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART7_RS485RTSCONTROL) + .rs485mode = 1, +# endif + +# ifdef CONFIG_LPUART7_TXDMA + .txch = DMA_REQUEST_MUXLPUART7TX, +# endif +# ifdef CONFIG_LPUART7_RXDMA + .rxch = DMA_REQUEST_MUXLPUART7RX, + .rxfifo = g_lpuart7rxfifo, +# endif +}; +#endif + +#ifdef CONFIG_IMX9_LPUART8 +static struct imx9_uart_s g_lpuart8priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_LPUART8_RXBUFSIZE, + .buffer = g_lpuart8rxbuffer, + }, + .xmit = + { + .size = CONFIG_LPUART8_TXBUFSIZE, + .buffer = g_lpuart8txbuffer, + }, + #if defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA) + .ops = &g_lpuart_rxtxdma_ops, + #elif defined(CONFIG_LPUART8_RXDMA) && !defined(CONFIG_LPUART8_TXDMA) + .ops = &g_lpuart_rxdma_ops, + #elif !defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_TXDMA) + .ops = &g_lpuart_txdma_ops, + #else + .ops = &g_lpuart_ops, + #endif + }, + + .uartbase = IMX9_LPUART8_BASE, + .uartnum = 8, + .baud = CONFIG_LPUART8_BAUD, + .irq = IMX9_IRQ_LPUART8, + .parity = CONFIG_LPUART8_PARITY, + .bits = CONFIG_LPUART8_BITS, + .stopbits2 = CONFIG_LPUART8_2STOP, +# if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_LPUART8_OFLOWCONTROL) + .oflow = 1, + .cts_gpio = GPIO_LPUART8_CTS, +# endif +# if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL) + .iflow = 1, +# endif +# if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_LPUART8_IFLOWCONTROL))) + .rts_gpio = GPIO_LPUART8_RTS, +# endif + +# if (defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL)) && \ + defined(CONFIG_LPUART8_INVERTIFLOWCONTROL) + .inviflow = 1, +# endif + +# if defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_LPUART8_RS485RTSCONTROL) + .rs485mode = 1, +# endif + +# ifdef CONFIG_LPUART8_TXDMA + .txch = DMA_REQUEST_MUXLPUART8TX, +# endif +# ifdef CONFIG_LPUART8_RXDMA + .rxch = DMA_REQUEST_MUXLPUART8RX, + .rxfifo = g_lpuart8rxfifo, +# endif +}; +#endif + +#ifdef CONFIG_PM +static struct pm_callback_s g_serial_pmcb = +{ + .notify = up_pm_notify, + .prepare = up_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_serialin + ****************************************************************************/ + +static inline uint32_t imx9_serialin(struct imx9_uart_s *priv, + uint32_t offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: imx9_serialout + ****************************************************************************/ + +static inline void imx9_serialout(struct imx9_uart_s *priv, + uint32_t offset, uint32_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: imx9_dma_nextrx + * + * Description: + * Returns the index into the RX FIFO where the DMA will place the next + * byte that it receives. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static int imx9_dma_nextrx(struct imx9_uart_s *priv) +{ + int dmaresidual = imx9_dmach_getcount(priv->rxdma); + DEBUGASSERT(dmaresidual <= RXDMA_BUFFER_SIZE); + + return (RXDMA_BUFFER_SIZE - dmaresidual) % RXDMA_BUFFER_SIZE; +} +#endif + +/**************************************************************************** + * Name: imx9_disableuartint + ****************************************************************************/ + +static inline void imx9_disableuartint(struct imx9_uart_s *priv, + uint32_t *ie) +{ + irqstate_t flags; + uint32_t regval; + + flags = spin_lock_irqsave(NULL); + regval = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET); + + /* Return the current Rx and Tx interrupt state */ + + if (ie != NULL) + { + *ie = regval & LPUART_ALL_INTS; + } + + regval &= ~LPUART_ALL_INTS; + imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, regval); + spin_unlock_irqrestore(NULL, flags); +} + +/**************************************************************************** + * Name: imx9_restoreuartint + ****************************************************************************/ + +static inline void imx9_restoreuartint(struct imx9_uart_s *priv, + uint32_t ie) +{ + irqstate_t flags; + uint32_t regval; + + /* Enable/disable any interrupts that are currently disabled but should be + * enabled/disabled. + */ + + flags = spin_lock_irqsave(NULL); + regval = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET); + regval &= ~LPUART_ALL_INTS; + regval |= ie; + imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, regval); + spin_unlock_irqrestore(NULL, flags); +} + +/**************************************************************************** + * Name: imx9_dma_setup + * + * Description: + * Configure the LPUART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA) +static int imx9_dma_setup(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; +#if defined(SERIAL_HAVE_RXDMA) + struct imx9_edma_xfrconfig_s config; +#endif + int result; + + /* Do the basic UART setup first, unless we are the console */ + + if (!dev->isconsole) + { + result = imx9_setup(dev); + if (result != OK) + { + return result; + } + } + +#if defined(SERIAL_HAVE_TXDMA) + /* Acquire the Tx DMA channel. This should always succeed. */ + + if (priv->txch != 0) + { + if (priv->txdma == NULL) + { + priv->txdma = imx9_dmach_alloc(priv->txch, 0); + if (priv->txdma == NULL) + { + return -EBUSY; + } + } + + /* Enable Tx DMA for the UART */ + + modifyreg32(priv->uartbase + IMX9_LPUART_BAUD_OFFSET, + 0, LPUART_BAUD_TDMAE); + } +#endif + +#if defined(SERIAL_HAVE_RXDMA) + /* Acquire the Rx DMA channel. This should always succeed. */ + + if (priv->rxch != 0) + { + if (priv->rxdma == NULL) + { + priv->rxdma = imx9_dmach_alloc(priv->rxch, 0); + + if (priv->rxdma == NULL) + { + return -EBUSY; + } + } + else + { + imx9_dmach_stop(priv->rxdma); + } + + /* Configure for circular DMA reception into the RX FIFO */ + + config.saddr = priv->uartbase + IMX9_LPUART_DATA_OFFSET; + config.daddr = (uintptr_t)priv->rxfifo; + config.soff = 0; + config.doff = 1; + config.iter = RXDMA_BUFFER_SIZE; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE | + EDMA_CONFIG_LOOPDEST | + EDMA_CONFIG_INTHALF | + EDMA_CONFIG_INTMAJOR; + config.ssize = EDMA_8BIT; + config.dsize = EDMA_8BIT; + config.nbytes = 1; +#ifdef CONFIG_IMX9_EDMA_ELINK + config.linkch = 0; +#endif + + imx9_dmach_xfrsetup(priv->rxdma , &config); + + /* Reset our DMA shadow pointer and Rx data availability count to + * match the address just programmed above. + */ + + priv->rxdmanext = 0; + +#ifndef CONFIG_ARM64_DCACHE_DISABLE + + /* Make sure the rx buffer area is all invalid or clean */ + + up_invalidate_dcache((uintptr_t)priv->rxfifo, + (uintptr_t)priv->rxfifo + RXDMA_BUFFER_SIZE); + priv->rxdmaavail = 0; +#endif + + /* Enable receive Rx DMA for the UART */ + + modifyreg32(priv->uartbase + IMX9_LPUART_BAUD_OFFSET, + 0, LPUART_BAUD_RDMAE); + + /* Enable interrupt on idle and erros */ + + modifyreg32(priv->uartbase + IMX9_LPUART_CTRL_OFFSET, 0, + LPUART_CTRL_PEIE | + LPUART_CTRL_FEIE | + LPUART_CTRL_NEIE | + LPUART_CTRL_ILIE); + + /* Start the DMA channel, and arrange for callbacks at the half and + * full points in the FIFO. This ensures that we have half a FIFO + * worth of time to claim bytes before they are overwritten. + */ + + imx9_dmach_start(priv->rxdma, imx9_dma_rxcallback, (void *)priv); + } +#endif + + return OK; +} +#endif + +/**************************************************************************** + * Name: imx9_setup + * + * Description: + * Configure the UART baud, bits, parity, fifos, etc. This + * method is called the first time that the serial priv is + * opened. + * + ****************************************************************************/ + +static int imx9_setup(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; +#ifndef CONFIG_SUPPRESS_LPUART_CONFIG + struct uart_config_s config = + { + 0 + }; + + int ret; + + /* Configure the UART */ + + config.baud = priv->baud; /* Configured baud */ + config.parity = priv->parity; /* 0=none, 1=odd, 2=even */ + config.bits = priv->bits; /* Number of bits (5-9) */ + config.stopbits2 = priv->stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_OFLOWCONTROL + config.usects = priv->oflow; /* Flow control on outbound side */ +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + /* Flow control on outbound side if not GPIO based */ + + if (priv->rts_gpio == 0) + { + config.userts = priv->iflow; + } + +#endif +#ifdef CONFIG_SERIAL_RS485CONTROL + config.users485 = priv->rs485mode; /* Switch into RS485 mode */ +#endif +#if defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL) + config.invrts = priv->inviflow; /* Inversion of outbound flow control */ +#endif + + ret = imx9_lpuart_configure(priv->uartbase, priv->uartnum, &config); + + priv->ie = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET) & \ + LPUART_ALL_INTS; + return ret; + +#else + priv->ie = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET) & \ + LPUART_ALL_INTS; + return OK; +#endif +} + +/**************************************************************************** + * Name: imx9_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * priv is closed + * + ****************************************************************************/ + +static void imx9_shutdown(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + /* Disable the UART */ + + imx9_serialout(priv, IMX9_LPUART_GLOBAL_OFFSET, LPUART_GLOBAL_RST); +} + +/**************************************************************************** + * Name: imx9_dma_shutdown + * + * Description: + * Disable the LPUART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +#if defined(SERIAL_HAVE_RXDMA) || defined(SERIAL_HAVE_TXDMA) +static void imx9_dma_shutdown(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + /* Perform the normal UART shutdown */ + + imx9_shutdown(dev); + +#if defined(SERIAL_HAVE_RXDMA) + /* Stop the RX DMA channel */ + + if (priv->rxch != 0) + { + imx9_dmach_stop(priv->rxdma); + + /* Release the RX DMA channel */ + + imx9_dmach_free(priv->rxdma); + priv->rxdma = NULL; + } +#endif + +#if defined(SERIAL_HAVE_TXDMA) + /* Stop the TX DMA channel */ + + if (priv->txch != 0) + { + imx9_dmach_stop(priv->txdma); + + /* Release the TX DMA channel */ + + imx9_dmach_free(priv->txdma); + priv->txdma = NULL; + } +#endif +} +#endif + +/**************************************************************************** + * Name: imx9_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method + * is called when the serial priv is opened. Normally, this is just after + * the setup() method is called, however, the serial console may operate + * in a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method (unless + * the hardware supprivs multiple levels of interrupt enabling). The RX + * and TX interrupts are not enabled until the txint() and rxint() methods + * are called. + * + ****************************************************************************/ + +static int imx9_attach(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + int ret; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->irq, imx9_interrupt, dev); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ + + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: imx9_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial priv is + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void imx9_detach(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + up_disable_irq(priv->irq); + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: imx9_interrupt (and front-ends) + * + * Description: + * This is the common UART interrupt handler. It will be invoked when an + * interrupt is received on the 'irq'. It should call uart_xmitchars or + * uart_recvchars to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'arg' to the + * appropriate uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int imx9_interrupt(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct imx9_uart_s *priv; + uint32_t usr; + uint32_t lsr; + int passes = 0; + bool handled; + + DEBUGASSERT(dev != NULL && dev != NULL); + priv = (struct imx9_uart_s *)dev; + +#if defined(CONFIG_PM) && CONFIG_IMX9_PM_SERIAL_ACTIVITY > 0 + /* Repriv serial activity to the power management logic */ + + pm_activity(PM_IDLE_DOMAIN, CONFIG_IMX9_PM_SERIAL_ACTIVITY); +#endif + + /* Loop until there are no characters to be transferred or, + * until we have been looping for a long time. + */ + + handled = true; + for (passes = 0; passes < 256 && handled; passes++) + { + handled = false; + + /* Get the current UART status and check for loop + * termination conditions + */ + + usr = imx9_serialin(priv, IMX9_LPUART_STAT_OFFSET); + + /* Removed all W1C from the last sr */ + + lsr = usr & ~(LPUART_STAT_LBKDIF | LPUART_STAT_RXEDGIF | + LPUART_STAT_IDLE | LPUART_STAT_OR | + LPUART_STAT_NF | LPUART_STAT_FE | + LPUART_STAT_PF | LPUART_STAT_MA1F | + LPUART_STAT_MA2F); + + /* Keep what we will service */ + + usr &= (LPUART_STAT_RDRF | LPUART_STAT_TDRE | LPUART_STAT_OR | + LPUART_STAT_FE | LPUART_STAT_NF | LPUART_STAT_PF | + LPUART_STAT_IDLE); + + /* Clear serial overrun, parity and framing errors */ + + if ((usr & LPUART_STAT_OR) != 0) + { + imx9_serialout(priv, IMX9_LPUART_STAT_OFFSET, + LPUART_STAT_OR | lsr); + } + + if ((usr & LPUART_STAT_NF) != 0) + { + imx9_serialout(priv, IMX9_LPUART_STAT_OFFSET, + LPUART_STAT_NF | lsr); + } + + if ((usr & LPUART_STAT_PF) != 0) + { + imx9_serialout(priv, IMX9_LPUART_STAT_OFFSET, + LPUART_STAT_PF | lsr); + } + + if ((usr & LPUART_STAT_FE) != 0) + { + imx9_serialout(priv, IMX9_LPUART_STAT_OFFSET, + LPUART_STAT_FE | lsr); + } + + if ((usr & (LPUART_STAT_FE | LPUART_STAT_PF | LPUART_STAT_NF)) != 0) + { + /* Discard data */ + + imx9_serialin(priv, IMX9_LPUART_DATA_OFFSET); + } + +#ifdef SERIAL_HAVE_RXDMA + /* The line going to idle, deliver any fractions of RX data */ + + if ((usr & LPUART_STAT_IDLE) != 0) + { + imx9_serialout(priv, IMX9_LPUART_STAT_OFFSET, + LPUART_STAT_IDLE | lsr); + imx9_dma_rxcallback(priv->rxdma, priv, false, LPUART_STAT_IDLE); + } +#endif + + /* Handle incoming, receive bytes */ + + if ((usr & LPUART_STAT_RDRF) != 0 && + (priv->ie & LPUART_CTRL_RIE) != 0) + { + uart_recvchars(dev); + handled = true; + } + + /* Handle outgoing, transmit bytes */ + + if ((usr & LPUART_STAT_TDRE) != 0 && + (priv->ie & LPUART_CTRL_TIE) != 0) + { + uart_xmitchars(dev); + handled = true; + } + } + + return OK; +} + +/**************************************************************************** + * Name: imx9_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int imx9_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#if defined(CONFIG_SERIAL_TIOCSERGSTRUCT) || defined(CONFIG_SERIAL_TERMIOS) + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; + irqstate_t flags; +#endif + int ret = OK; + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + case TIOCSERGSTRUCT: + { + struct imx9_uart_s *user = (struct imx9_uart_s *)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct imx9_uart_s)); + } + } + break; +#endif + +#ifdef CONFIG_SERIAL_TERMIOS + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + /* Return parity */ + + termiosp->c_cflag = ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0); + + /* Return stop bits */ + + termiosp->c_cflag |= (priv->stopbits2) ? CSTOPB : 0; + + /* Return flow control */ + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + termiosp->c_cflag |= ((priv->oflow) ? CCTS_OFLOW : 0); +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + termiosp->c_cflag |= ((priv->iflow) ? CRTS_IFLOW : 0); +#endif + /* Return baud */ + + cfsetispeed(termiosp, priv->baud); + + /* Return number of bits */ + + switch (priv->bits) + { + case 5: + termiosp->c_cflag |= CS5; + break; + + case 6: + termiosp->c_cflag |= CS6; + break; + + case 7: + termiosp->c_cflag |= CS7; + break; + + default: + case 8: + termiosp->c_cflag |= CS8; + break; + +#if defined(CS9) + case 9: + termiosp->c_cflag |= CS9; + break; +#endif + } + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + uint32_t baud; + uint32_t ie; + uint8_t parity; + uint8_t nbits; + bool stop2; + + if ((!termiosp) +#ifdef CONFIG_SERIAL_OFLOWCONTROL + || ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + || ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0)) +#endif + ) + { + ret = -EINVAL; + break; + } + + /* Decode baud. */ + + ret = OK; + baud = cfgetispeed(termiosp); + + /* Decode number of bits */ + + switch (termiosp->c_cflag & CSIZE) + { + case CS5: + nbits = 5; + break; + + case CS6: + nbits = 6; + break; + + case CS7: + nbits = 7; + break; + + case CS8: + nbits = 8; + break; + +#if defined(CS9) + case CS9: + nbits = 9; + break; +#endif + default: + ret = -EINVAL; + break; + } + + /* Decode parity */ + + if ((termiosp->c_cflag & PARENB) != 0) + { + parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + parity = 0; + } + + /* Decode stop bits */ + + stop2 = (termiosp->c_cflag & CSTOPB) != 0; + + /* Verify that all settings are valid before committing */ + + if (ret == OK) + { + /* Commit */ + + priv->baud = baud; + priv->parity = parity; + priv->bits = nbits; + priv->stopbits2 = stop2; +#ifdef CONFIG_SERIAL_OFLOWCONTROL + priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; +#endif + /* effect the changes immediately - note that we do not + * implement TCSADRAIN / TCSAFLUSH + */ + + flags = spin_lock_irqsave(NULL); + imx9_disableuartint(priv, &ie); + ret = dev->ops->setup(dev); + + /* Restore the interrupt state */ + + imx9_restoreuartint(priv, ie); + priv->ie = ie; + spin_unlock_irqrestore(NULL, flags); + } + } + break; +#endif /* CONFIG_SERIAL_TERMIOS */ + +#ifdef CONFIG_IMX9_LPUART_SINGLEWIRE + case TIOCSSINGLEWIRE: + { + uint32_t regval; + irqstate_t flags; + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + flags = spin_lock_irqsave(NULL); + regval = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET); + + if ((arg & SER_SINGLEWIRE_ENABLED) != 0) + { + regval |= LPUART_CTRL_LOOPS | LPUART_CTRL_RSRC; + } + else + { + regval &= ~(LPUART_CTRL_LOOPS | LPUART_CTRL_RSRC); + } + + imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, regval); + + spin_unlock_irqrestore(NULL, flags); + } + break; +#endif + +#ifdef CONFIG_IMX9_LPUART_INVERT + case TIOCSINVERT: + { + uint32_t ctrl; + uint32_t stat; + uint32_t regval; + irqstate_t flags; + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + flags = spin_lock_irqsave(NULL); + ctrl = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET); + stat = imx9_serialin(priv, IMX9_LPUART_STAT_OFFSET); + regval = ctrl; + + /* {R|T}XINV bit field can only be written when the receiver is + * disabled (RE=0). + */ + + regval &= ~LPUART_CTRL_RE; + + imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, regval); + + /* Enable/disable signal inversion. */ + + if (arg & SER_INVERT_ENABLED_RX) + { + stat |= LPUART_STAT_RXINV; + } + else + { + stat &= ~LPUART_STAT_RXINV; + } + + /* Do not invert TX when in TIOCSSINGLEWIRE */ + + if ((arg & SER_INVERT_ENABLED_TX) && + ((ctrl & LPUART_CTRL_LOOPS) != LPUART_CTRL_LOOPS)) + { + ctrl |= LPUART_CTRL_TXINV; + } + else + { + ctrl &= ~LPUART_CTRL_TXINV; + } + + imx9_serialout(priv, IMX9_LPUART_STAT_OFFSET, stat); + imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, ctrl); + + spin_unlock_irqrestore(NULL, flags); + } + break; +#endif + + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: imx9_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +#ifndef SERIAL_HAVE_ONLY_RXDMA +static int imx9_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + uint32_t rxd; + + rxd = imx9_serialin(priv, IMX9_LPUART_DATA_OFFSET); + *status = rxd >> LPUART_DATA_STATUS_SHIFT; + return (rxd & LPUART_DATA_MASK) >> LPUART_DATA_SHIFT; +} +#endif + +/**************************************************************************** + * Name: imx9_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +#ifndef SERIAL_HAVE_ONLY_RXDMA +static void imx9_rxint(struct uart_dev_s *dev, bool enable) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + irqstate_t flags; + uint32_t regval; + + /* Enable interrupts for data available at Rx */ + + flags = spin_lock_irqsave(NULL); + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ie |= LPUART_CTRL_RIE | LPUART_CTRL_FEIE | LPUART_CTRL_ORIE; +#endif + } + else + { + priv->ie &= ~(LPUART_CTRL_RIE | LPUART_CTRL_FEIE | LPUART_CTRL_ORIE); + } + + regval = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET); + regval &= ~LPUART_ALL_INTS; + regval |= priv->ie; + imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, regval); + spin_unlock_irqrestore(NULL, flags); +} +#endif + +/**************************************************************************** + * Name: imx9_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ****************************************************************************/ + +#ifndef SERIAL_HAVE_ONLY_RXDMA +static bool imx9_rxavailable(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + uint32_t regval; + + /* Return true is data is ready in the Rx FIFO */ + + regval = imx9_serialin(priv, IMX9_LPUART_STAT_OFFSET); + return ((regval & LPUART_STAT_RDRF) != 0); +} +#endif + +/**************************************************************************** + * Name: imx9_rxflowcontrol + * + * Description: + * Called when Rx buffer is full (or exceeds configured watermark levels + * if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is defined). + * Return true if UART activated RX flow control to block more incoming + * data + * + * Input Parameters: + * dev - UART device instance + * nbuffered - the number of characters currently buffered + * (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is + * not defined the value will be 0 for an empty buffer or the + * defined buffer size for a full buffer) + * upper - true indicates the upper watermark was crossed where + * false indicates the lower watermark has been crossed + * + * Returned Value: + * true if RX flow control activated. + * + ****************************************************************************/ + +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool imx9_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + if (priv->iflow && (priv->rts_gpio != 0)) + { + /* Assert/de-assert nRTS set it high resume/stop sending */ + + imx9_gpiowrite(priv->rts_gpio, upper); + + if (upper) + { + /* With heavy Rx traffic, RXNE might be set and data pending. + * Returning 'true' in such case would cause RXNE left unhandled + * and causing interrupt storm. Sending end might be also be slow + * to react on nRTS, and returning 'true' here would prevent + * processing that data. + * + * Therefore, return 'false' so input data is still being processed + * until sending end reacts on nRTS signal and stops sending more. + */ + + return false; + } + + return upper; + } + else + { + /* Is the RX buffer full? */ + + if (upper) + { + /* Disable Rx interrupt to prevent more data being from + * peripheral. When hardware RTS is enabled, this will + * prevent more data from coming in. + * + * This function is only called when UART recv buffer is full, + * that is: "dev->recv.head + 1 == dev->recv.tail". + * + * Logic in "uart_read" will automatically toggle Rx interrupts + * when buffer is read empty and thus we do not have to re- + * enable Rx interrupts. + */ + + uart_disablerxint(dev); + return true; + } + + /* No.. The RX buffer is empty */ + + else + { + /* We might leave Rx interrupt disabled if full recv buffer was + * read empty. Enable Rx interrupt to make sure that more input is + * received. + */ + + uart_enablerxint(dev); + } + } + + return false; +} +#endif + +/**************************************************************************** + * Name: imx9_dma_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the LPUART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static int imx9_dma_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + uint32_t nextrx = imx9_dma_nextrx(priv); + int c = 0; + + /* Check if more data is available */ + + if (nextrx != priv->rxdmanext) + { +#ifndef CONFIG_ARM64_DCACHE_DISABLE + /* If the data cache is enabled, then we will also need to manage + * cache coherency. Are any bytes available in the currently coherent + * region of the data cache? + */ + + if (priv->rxdmaavail == 0) + { + uint32_t rxdmaavail; + uintptr_t addr; + + /* No.. then we will have to invalidate additional space in the Rx + * DMA buffer. + */ + + if (nextrx > priv->rxdmanext) + { + /* Number of available bytes */ + + rxdmaavail = nextrx - priv->rxdmanext; + } + else + { + /* Number of available bytes up to the end of RXDMA buffer */ + + rxdmaavail = RXDMA_BUFFER_SIZE - priv->rxdmanext; + } + + /* Invalidate the DMA buffer range */ + + addr = (uintptr_t)&priv->rxfifo[priv->rxdmanext]; + up_invalidate_dcache(addr, addr + rxdmaavail); + + /* We don't need to invalidate the data cache for the next + * rxdmaavail number of next bytes. + */ + + priv->rxdmaavail = rxdmaavail; + } + + priv->rxdmaavail--; +#endif + + /* Now read from the DMA buffer */ + + c = priv->rxfifo[priv->rxdmanext]; + + priv->rxdmanext++; + + if (priv->rxdmanext == RXDMA_BUFFER_SIZE) + { + priv->rxdmanext = 0; + } + } + + /* NOTE: If no data is available, then we would return NULL which is, + * of course, valid binary data. The protocol is that the upper half + * driver must call imx9_dma_rxavailable prior to calling this + * function to assure that this never happens. + */ + + return c; +} +#endif + +/**************************************************************************** + * Name: imx9_dma_reenable + * + * Description: + * Call to re-enable RX DMA. + * + ****************************************************************************/ + +#if defined(SERIAL_HAVE_RXDMA) && defined(CONFIG_PM) +static void imx9_dma_reenable(struct imx9_uart_s *priv) +{ + struct imx9_edma_xfrconfig_s config; + + /* Stop an reset the RX DMA */ + + imx9_dmach_stop(priv->rxdma); + + /* Configure for circular DMA reception into the RX FIFO */ + + config.saddr = priv->uartbase + IMX9_LPUART_DATA_OFFSET; + config.daddr = (uint32_t) priv->rxfifo; + config.soff = 0; + config.doff = 1; + config.iter = RXDMA_BUFFER_SIZE; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE | + EDMA_CONFIG_LOOPDEST | + EDMA_CONFIG_INTHALF | + EDMA_CONFIG_INTMAJOR; + config.ssize = EDMA_8BIT; + config.dsize = EDMA_8BIT; + config.nbytes = 1; +#ifdef CONFIG_IMX9_EDMA_ELINK + config.linkch = 0; +#endif + + imx9_dmach_xfrsetup(priv->rxdma, &config); + + /* Reset our DMA shadow pointer and Rx data availability count to match + * the address just programmed above. + */ + + priv->rxdmanext = 0; +#ifndef CONFIG_ARM64_DCACHE_DISABLE + priv->rxdmaavail = 0; +#endif + + /* Start the DMA channel, and arrange for callbacks at the half and + * full points in the FIFO. This ensures that we have half a FIFO + * worth of time to claim bytes before they are overwritten. + */ + + imx9_dmach_start(priv->rxdma, imx9_dma_rxcallback, (void *)priv); + + /* Clear DMA suspended flag. */ + + priv->rxdmasusp = false; +} +#endif + +/**************************************************************************** + * Name: imx9_dma_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static void imx9_dma_rxint(struct uart_dev_s *dev, bool enable) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + /* Enable/disable DMA reception. + * + * Note that it is not safe to check for available bytes and immediately + * pass them to uart_recvchars as that could potentially recurse back + * to us again. Instead, bytes must wait until the next up_dma_poll or + * DMA event. + */ + + priv->rxenable = enable; +} +#endif + +/**************************************************************************** + * Name: imx9_dma_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static bool imx9_dma_rxavailable(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + /* Compare our receive pointer to the current DMA pointer, if they + * do not match, then there are bytes to be received. + */ + + return (imx9_dma_nextrx(priv) != priv->rxdmanext); +} +#endif + +/**************************************************************************** + * Name: imx9_dma_txcallback + * + * Description: + * This function clears dma buffer at complete of DMA transfer and wakes up + * threads waiting for space in buffer. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_TXDMA +static void imx9_dma_txcallback(DMACH_HANDLE handle, void *arg, bool done, + int result) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)arg; + + /* Update 'nbytes' indicating number of bytes actually transferred by DMA. + * This is important to free TX buffer space by 'uart_xmitchars_done'. + */ + + priv->dev.dmatx.nbytes = priv->dev.dmatx.length; +#if CONFIG_IMX9_EDMA_NTCD > 1 + priv->dev.dmatx.nbytes += priv->dev.dmatx.nlength; +#endif + + /* Adjust the pointers */ + + uart_xmitchars_done(&priv->dev); + + /* Send more data if available */ + + imx9_dma_txavailable(&priv->dev); +} +#endif + +/**************************************************************************** + * Name: imx9_dma_txavailable + * + * Description: + * Informs DMA that Tx data is available and is ready for transfer. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_TXDMA +static void imx9_dma_txavailable(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + + /* Only send when the DMA is idle */ + + if (imx9_dmach_idle(priv->txdma) == 0) + { + uart_xmitchars_dma(dev); + } +} +#endif + +/**************************************************************************** + * Name: imx9_dma_send + * + * Description: + * Called (usually) from the interrupt level to start DMA transfer. + * (Re-)Configures DMA Stream updating buffer and buffer length. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_TXDMA +static void imx9_dma_send(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + struct imx9_edma_xfrconfig_s config; + + /* We need to stop DMA before reconfiguration */ + + imx9_dmach_stop(priv->txdma); + + /* Reset the number sent */ + + dev->dmatx.nbytes = 0; + + /* Make use of setup function to update buffer and its length for next + * transfer + */ + + config.iter = dev->dmatx.length; + config.flags = EDMA_CONFIG_LINKTYPE_LINKNONE; + config.ssize = EDMA_8BIT; + config.dsize = EDMA_8BIT; + config.nbytes = 1; + config.saddr = (uintptr_t)dev->dmatx.buffer; + config.daddr = priv->uartbase + IMX9_LPUART_DATA_OFFSET; + config.soff = 1; + config.doff = 0; +#ifdef CONFIG_IMX9_EDMA_ELINK + config.linkch = 0; +#endif + + /* Flush the contents of the TX buffer into physical memory */ + + up_clean_dcache((uintptr_t)dev->dmatx.buffer, + (uintptr_t)dev->dmatx.buffer + dev->dmatx.length); + + /* Setup first half */ + + imx9_dmach_xfrsetup(priv->txdma, &config); + +#if CONFIG_IMX9_EDMA_NTCD > 1 + /* Is this a split transfer? */ + + if (dev->dmatx.nbuffer) + { + config.iter = priv->dev.dmatx.nlength; + config.saddr = (uintptr_t)priv->dev.dmatx.nbuffer; + + /* Flush the contents of the next TX buffer into physical memory */ + + up_clean_dcache((uintptr_t)dev->dmatx.nbuffer, + (uintptr_t)dev->dmatx.nbuffer + dev->dmatx.nlength); + + imx9_dmach_xfrsetup(priv->txdma, &config); + } +#endif + + /* Start transmission with the callback on DMA completion */ + + imx9_dmach_start(priv->txdma, imx9_dma_txcallback, (void *)priv); +} +#endif + +/**************************************************************************** + * Name: imx9_send + * + * Description: + * This method will send one byte on the UART + * + ****************************************************************************/ + +static void imx9_send(struct uart_dev_s *dev, int ch) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + +#ifdef CONSOLE_DEV + if (dev == &CONSOLE_DEV.dev && !dev->isconsole) + { + return; + } +#endif + + imx9_serialout(priv, IMX9_LPUART_DATA_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: imx9_dma_txint + * + * Description: + * Call to enable or disable TX interrupts from the UART. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_TXDMA +static void imx9_dma_txint(struct uart_dev_s *dev, bool enable) +{ + /* Nothing to do. */ + + /* In case of DMA transfer we do not want to make use of UART interrupts. + * Instead, we use DMA interrupts that are activated once during boot + * sequence. Furthermore we can use imx9_dma_txcallback() to handle + * stuff at half DMA transfer or after transfer completion (depending + * on the configuration). + */ +} +#endif + +/**************************************************************************** + * Name: imx9_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +#if !defined(SERIAL_HAVE_ONLY_TXDMA) +static void imx9_txint(struct uart_dev_s *dev, bool enable) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + irqstate_t flags; + uint32_t regval; + + /* Enable interrupt for TX complete */ + + flags = spin_lock_irqsave(NULL); + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->ie |= LPUART_CTRL_TIE; +#endif + } + else + { + priv->ie &= ~LPUART_CTRL_TIE; + } + + regval = imx9_serialin(priv, IMX9_LPUART_CTRL_OFFSET); + regval &= ~LPUART_ALL_INTS; + regval |= priv->ie; + imx9_serialout(priv, IMX9_LPUART_CTRL_OFFSET, regval); + spin_unlock_irqrestore(NULL, flags); +} +#endif + +/**************************************************************************** + * Name: imx9_txready + * + * Description: + * Return true if the transmit register is available to be written to + * + ****************************************************************************/ + +static bool imx9_txready(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + uint32_t regval; + + regval = imx9_serialin(priv, IMX9_LPUART_STAT_OFFSET); + return ((regval & LPUART_STAT_TDRE) != 0); +} + +/**************************************************************************** + * Name: imx9_txempty + * + * Description: + * Return true if the transmit reg is empty + * + ****************************************************************************/ + +static bool imx9_txempty(struct uart_dev_s *dev) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)dev; + uint32_t regval; + + regval = imx9_serialin(priv, IMX9_LPUART_STAT_OFFSET); + return ((regval & LPUART_STAT_TDRE) != 0); +} + +/**************************************************************************** + * Name: imx9_dma_rxcallback + * + * Description: + * This function checks the current DMA state and calls the generic + * serial stack when bytes appear to be available. + * + ****************************************************************************/ + +#ifdef SERIAL_HAVE_RXDMA +static void imx9_dma_rxcallback(DMACH_HANDLE handle, void *arg, bool done, + int result) +{ + struct imx9_uart_s *priv = (struct imx9_uart_s *)arg; + uint32_t sr; + + if (priv->rxenable && imx9_dma_rxavailable(&priv->dev)) + { + uart_recvchars(&priv->dev); + } + + /* Get the masked LPUART status word to check and clear error flags. + * + * When wake-up from low power mode was not fast enough, UART is resumed + * too late and sometimes exactly when character was coming over UART, + * resulting to frame error. + * If error flag is not cleared, Rx DMA will be stuck. Clearing errors + * will release Rx DMA. + */ + + sr = imx9_serialin(priv, IMX9_LPUART_STAT_OFFSET); + + if ((sr & (LPUART_STAT_OR | LPUART_STAT_NF | LPUART_STAT_FE)) != 0) + { + imx9_serialout(priv, IMX9_LPUART_STAT_OFFSET, + sr & (LPUART_STAT_OR | + LPUART_STAT_NF | + LPUART_STAT_FE)); + } +} +#endif + +/**************************************************************************** + * Name: up_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opprivunity to prepare for the new power state. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * None - The driver already agreed to transition to the low power + * consumption state when when it returned OK to the prepare() call. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void up_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case(PM_NORMAL): + { + /* Logic for PM_NORMAL goes here */ + } + break; + + case(PM_IDLE): + { + /* Logic for PM_IDLE goes here */ + } + break; + + case(PM_STANDBY): + { + /* Logic for PM_STANDBY goes here */ + } + break; + + case(PM_SLEEP): + { + /* Logic for PM_SLEEP goes here */ + } + break; + + default: + + /* Should not get here */ + + break; + } +} +#endif + +/**************************************************************************** + * Name: up_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + * Input Parameters: + * + * cb - Returned to the driver. The driver version of the callback + * structure may include additional, driver-specific state data at + * the end of the structure. + * + * pmstate - Identifies the new PM state + * + * Returned Value: + * Zero - (OK) means the event was successfully processed and that the + * driver is prepared for the PM state change. + * + * Non-zero - means that the driver is not prepared to perform the tasks + * needed achieve this power setting and will cause the state + * change to be aborted. NOTE: The prepare() method will also + * be called when reverting from lower back to higher power + * consumption modes (say because another driver refused a + * lower power state change). Drivers are not permitted to + * return non-zero values when reverting back to higher power + * consumption modes! + * + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int up_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* Logic to prepare for a reduced power state goes here. */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm64_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before arm64_serialinit. + * + ****************************************************************************/ + +void arm64_earlyserialinit(void) +{ + /* NOTE: This function assumes that low level hardware configuration + * -- including all clocking and pin configuration -- was performed by the + * function imx9_lowsetup() earlier in the boot sequence. + */ + + /* Enable the console UART. The other UARTs will be initialized if and + * when they are first opened. + */ + +#ifdef CONSOLE_DEV + CONSOLE_DEV.dev.isconsole = true; + imx9_setup(&CONSOLE_DEV.dev); +#endif +} + +/**************************************************************************** + * Name: arm64_serialinit + * + * Description: + * Register serial console and serial privs. This assumes + * that imx9_earlyserialinit was called previously. + * + ****************************************************************************/ + +void arm64_serialinit(void) +{ +#ifdef CONFIG_PM + int ret; + + /* Register to receive power management callbacks */ + + ret = pm_register(&g_serial_pmcb); + DEBUGASSERT(ret == OK); + UNUSED(ret); +#endif + +#ifdef CONSOLE_DEV + uart_register("/dev/console", &CONSOLE_DEV.dev); +#if defined(SERIAL_HAVE_CONSOLE_DMA) + imx9_dma_setup(&CONSOLE_DEV.dev); +#endif +#endif + + /* Register all UARTs */ + +#ifdef TTYS0_DEV + uart_register("/dev/ttyS0", &TTYS0_DEV.dev); +#endif +#ifdef TTYS1_DEV + uart_register("/dev/ttyS1", &TTYS1_DEV.dev); +#endif +#ifdef TTYS2_DEV + uart_register("/dev/ttyS2", &TTYS2_DEV.dev); +#endif +#ifdef TTYS3_DEV + uart_register("/dev/ttyS3", &TTYS3_DEV.dev); +#endif +#ifdef TTYS4_DEV + uart_register("/dev/ttyS4", &TTYS4_DEV.dev); +#endif +#ifdef TTYS5_DEV + uart_register("/dev/ttyS5", &TTYS5_DEV.dev); +#endif +#ifdef TTYS6_DEV + uart_register("/dev/ttyS6", &TTYS6_DEV.dev); +#endif +#ifdef TTYS7_DEV + uart_register("/dev/ttyS7", &TTYS7_DEV.dev); +#endif +} + +#endif /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to suppriv OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef CONSOLE_DEV + struct imx9_uart_s *priv = (struct imx9_uart_s *)&CONSOLE_DEV; + uint32_t ie; + + if (!CONSOLE_DEV.dev.isconsole) + { + return ch; + } + + imx9_disableuartint(priv, &ie); +#endif + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + arm64_lowputc('\r'); + } + + arm64_lowputc(ch); +#ifdef CONSOLE_DEV + imx9_restoreuartint(priv, ie); +#endif + return ch; +} diff --git a/arch/arm64/src/imx9/imx9_serial.h b/arch/arm64/src/imx9/imx9_serial.h new file mode 100644 index 0000000000000..e9c175a8ce14d --- /dev/null +++ b/arch/arm64/src/imx9/imx9_serial.h @@ -0,0 +1,242 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_serial.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_SERIAL_H +#define __ARCH_ARM64_SRC_IMX9_IMX9_SERIAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_IMX9_LPUART1) || defined(CONFIG_IMX9_LPUART2) || \ + defined(CONFIG_IMX9_LPUART3) || defined(CONFIG_IMX9_LPUART4) || \ + defined(CONFIG_IMX9_LPUART5) || defined(CONFIG_IMX9_LPUART6) || \ + defined(CONFIG_IMX9_LPUART7) || defined(CONFIG_IMX9_LPUART8) +# define HAVE_UART 1 +#endif + +/* Assume DMA is not used on the console UART */ + +#undef SERIAL_HAVE_CONSOLE_RXDMA +#undef SERIAL_HAVE_CONSOLE_TXDMA + +#if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA) +# undef CONFIG_LPUART1_RXDMA +# undef CONFIG_LPUART1_TXDMA +# undef CONFIG_LPUART2_RXDMA +# undef CONFIG_LPUART2_TXDMA +# undef CONFIG_LPUART3_RXDMA +# undef CONFIG_LPUART3_TXDMA +# undef CONFIG_LPUART4_RXDMA +# undef CONFIG_LPUART4_TXDMA +# undef CONFIG_LPUART5_RXDMA +# undef CONFIG_LPUART5_TXDMA +# undef CONFIG_LPUART6_RXDMA +# undef CONFIG_LPUART6_TXDMA +# undef CONFIG_LPUART7_RXDMA +# undef CONFIG_LPUART7_TXDMA +# undef CONFIG_LPUART8_RXDMA +# undef CONFIG_LPUART8_TXDMA +#endif + +/* Disable the DMA configuration on all unused LPUARTs */ + +#ifndef CONFIG_IMX9_LPUART1 +# undef CONFIG_LPUART1_RXDMA +# undef CONFIG_LPUART1_TXDMA +#endif + +#ifndef CONFIG_IMX9_LPUART2 +# undef CONFIG_LPUART2_RXDMA +# undef CONFIG_LPUART2_TXDMA +#endif + +#ifndef CONFIG_IMX9_LPUART3 +# undef CONFIG_LPUART3_RXDMA +# undef CONFIG_LPUART3_TXDMA +#endif + +#ifndef CONFIG_IMX9_LPUART4 +# undef CONFIG_LPUART4_RXDMA +# undef CONFIG_LPUART4_TXDMA +#endif + +#ifndef CONFIG_IMX9_LPUART5 +# undef CONFIG_LPUART5_RXDMA +# undef CONFIG_LPUART5_TXDMA +#endif + +#ifndef CONFIG_IMX9_LPUART6 +# undef CONFIG_LPUART6_RXDMA +# undef CONFIG_LPUART6_TXDMA +#endif + +#ifndef CONFIG_IMX9_LPUART8 +# undef CONFIG_LPUART7_RXDMA +# undef CONFIG_LPUART7_TXDMA +#endif + +/* Is RX DMA available on any (enabled) LPUART? */ + +#undef SERIAL_HAVE_RXDMA +#if defined(CONFIG_LPUART1_RXDMA) || defined(CONFIG_LPUART2_RXDMA) || \ + defined(CONFIG_LPUART3_RXDMA) || defined(CONFIG_LPUART4_RXDMA) || \ + defined(CONFIG_LPUART5_RXDMA) || defined(CONFIG_LPUART6_RXDMA) || \ + defined(CONFIG_LPUART7_RXDMA) || defined(CONFIG_LPUART8_RXDMA) +# define SERIAL_HAVE_RXDMA 1 +#endif + +/* Is TX DMA available on any (enabled) LPUART? */ +#undef SERIAL_HAVE_TXDMA +#if defined(CONFIG_LPUART1_TXDMA) || defined(CONFIG_LPUART2_TXDMA) || \ + defined(CONFIG_LPUART3_TXDMA) || defined(CONFIG_LPUART4_TXDMA) || \ + defined(CONFIG_LPUART5_TXDMA) || defined(CONFIG_LPUART6_TXDMA) || \ + defined(CONFIG_LPUART7_TXDMA) || defined(CONFIG_LPUART8_TXDMA) +# define SERIAL_HAVE_TXDMA 1 +#endif + +/* Is RX DMA used on all (enabled) LPUARTs */ + +#define SERIAL_HAVE_ONLY_RXDMA 1 +#if defined(CONFIG_IMX9_LPUART1) && !defined(CONFIG_LPUART1_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_IMX9_LPUART2) && !defined(CONFIG_LPUART2_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_IMX9_LPUART3) && !defined(CONFIG_LPUART3_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_IMX9_LPUART4) && !defined(CONFIG_LPUART4_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_IMX9_LPUART5) && !defined(CONFIG_LPUART5_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_IMX9_LPUART6) && !defined(CONFIG_LPUART6_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_IMX9_LPUART7) && !defined(CONFIG_LPUART7_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#elif defined(CONFIG_IMX9_LPUART8) && !defined(CONFIG_LPUART8_RXDMA) +# undef SERIAL_HAVE_ONLY_RXDMA +#endif + +/* Is TX DMA used on all (enabled) LPUARTs */ + +#define SERIAL_HAVE_ONLY_TXDMA 1 +#if defined(CONFIG_IMX9_LPUART1) && !defined(CONFIG_LPUART1_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_IMX9_LPUART2) && !defined(CONFIG_LPUART2_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_IMX9_LPUART3) && !defined(CONFIG_LPUART3_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_IMX9_LPUART4) && !defined(CONFIG_LPUART4_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_IMX9_LPUART5) && !defined(CONFIG_LPUART5_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_IMX9_LPUART6) && !defined(CONFIG_LPUART6_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_IMX9_LPUART7) && !defined(CONFIG_LPUART7_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#elif defined(CONFIG_IMX9_LPUART8) && !defined(CONFIG_LPUART8_TXDMA) +# undef SERIAL_HAVE_ONLY_TXDMA +#endif + +#undef SERIAL_HAVE_ONLY_DMA +#if defined(SERIAL_HAVE_ONLY_RXDMA) && defined(SERIAL_HAVE_ONLY_TXDMA) +#define SERIAL_HAVE_ONLY_DMA +#endif + +/* Verify that DMA has been enabled and the DMA channel has been defined. + */ + +#if defined(SERIAL_HAVE_TXDMA) || defined(SERIAL_HAVE_RXDMA) +# ifndef CONFIG_IMX9_EDMA +# error IMXRT LPUART receive or transmit DMA requires CONFIG_IMX9_EDMA +# endif +#endif + +#if defined(SERIAL_HAVE_RXDMA) +/* Currently RS-485 support cannot be enabled when RXDMA is in use due to + * lack of testing. + */ + +# if (defined(CONFIG_LPUART1_RXDMA) && defined(CONFIG_LPUART1_RS485)) || \ + (defined(CONFIG_LPUART2_RXDMA) && defined(CONFIG_LPUART2_RS485)) || \ + (defined(CONFIG_LPUART3_RXDMA) && defined(CONFIG_LPUART3_RS485)) || \ + (defined(CONFIG_LPUART4_RXDMA) && defined(CONFIG_LPUART4_RS485)) || \ + (defined(CONFIG_LPUART5_RXDMA) && defined(CONFIG_LPUART5_RS485)) || \ + (defined(CONFIG_LPUART6_RXDMA) && defined(CONFIG_LPUART6_RS485)) || \ + (defined(CONFIG_LPUART7_RXDMA) && defined(CONFIG_LPUART7_RS485)) || \ + (defined(CONFIG_LPUART8_RXDMA) && defined(CONFIG_LPUART8_RS485)) +# error "RXDMA and RS-485 cannot be enabled at the same time for the same LPUART" +# endif +#endif /* SERIAL_HAVE_RXDMA */ + +/* Currently RS-485 support cannot be enabled when TXDMA is in use due to + * lack of testing. + */ + +# if (defined(CONFIG_LPUART1_TXDMA) && defined(CONFIG_LPUART1_RS485)) || \ + (defined(CONFIG_LPUART2_TXDMA) && defined(CONFIG_LPUART2_RS485)) || \ + (defined(CONFIG_LPUART3_TXDMA) && defined(CONFIG_LPUART3_RS485)) || \ + (defined(CONFIG_LPUART4_TXDMA) && defined(CONFIG_LPUART4_RS485)) || \ + (defined(CONFIG_LPUART5_TXDMA) && defined(CONFIG_LPUART5_RS485)) || \ + (defined(CONFIG_LPUART6_TXDMA) && defined(CONFIG_LPUART6_RS485)) || \ + (defined(CONFIG_LPUART7_TXDMA) && defined(CONFIG_LPUART7_RS485)) || \ + (defined(CONFIG_LPUART8_TXDMA) && defined(CONFIG_LPUART8_RS485)) +# error "TXDMA and RS-485 cannot be enabled at the same time for the same LPUART" +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM64_SRC_IMX9_IMX9_SERIAL_H */ diff --git a/arch/arm64/src/imx9/imx9_tpm_pwm.c b/arch/arm64/src/imx9/imx9_tpm_pwm.c new file mode 100644 index 0000000000000..8194ac6ea11bd --- /dev/null +++ b/arch/arm64/src/imx9/imx9_tpm_pwm.c @@ -0,0 +1,693 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_tpm_pwm.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "arm64_arch.h" +#include "imx9_tpm_pwm.h" +#include "imx9_iomuxc.h" +#include "imx9_ccm.h" + +#include "hardware/imx9_iomuxc.h" +#include "hardware/imx9_pinmux.h" +#include "hardware/imx9_ccm.h" + +#ifdef CONFIG_IMX9_TPM_PWM + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CHMUX(priv, x) ((((priv)->chmux) >> (x)) & 0xff) + +/* This is a temporary shortcut to configure TPM1 and TPM3 + * frequencies correctly; they don't have an own root clock + * + * TODO: Determine the frequencies in a more proper way + */ + +#define AON_CLK_FREQ 133333333 +#define WAKEUP_CLK_FREQ 133333333 +#define OSC_24_CLK_FREQ 24000000 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure represents the state of one PWM timer */ + +struct imx9_pwmtimer_s +{ + const struct pwm_ops_s *ops; /* PWM operations */ + const tpm_pwm_id_t id; /* PWM_TPM1...PWM_TPM6 */ + const uintptr_t base; /* The base address of the TPM */ + const int n_channels; /* Number of channels used for TPM block */ + const uint32_t chmux; /* Additional muxing of TPM outputs */ + const int clk; /* Input clock frequency for the TPM */ + uint32_t period; + unsigned frequency; /* Current frequency setting */ +}; + +/**************************************************************************** + * Static Function Prototypes + ****************************************************************************/ + +/* PWM driver methods */ + +static int pwm_setup(struct pwm_lowerhalf_s *dev); +static int pwm_shutdown(struct pwm_lowerhalf_s *dev); + +static int pwm_start(struct pwm_lowerhalf_s *dev, + const struct pwm_info_s *info); + +static int pwm_stop(struct pwm_lowerhalf_s *dev); +static int pwm_ioctl(struct pwm_lowerhalf_s *dev, + int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This is the list of lower half PWM driver methods used by the upper half + * driver + */ + +static const struct pwm_ops_s g_pwmops = +{ + .setup = pwm_setup, + .shutdown = pwm_shutdown, + .start = pwm_start, + .stop = pwm_stop, + .ioctl = pwm_ioctl, +}; + +static struct imx9_pwmtimer_s g_pwmdev[] = +{ +#ifdef CONFIG_IMX9_TPM1_PWM + { + .ops = &g_pwmops, + .id = PWM_TPM1, + .base = IMX9_TPM1_BASE, + .n_channels = CONFIG_IMX9_TPM1_PWM_NCHANNELS, + .chmux = CONFIG_IMX9_TPM1_PWM_CHMUX, + .clk = AON_CLK_FREQ, + }, +#endif + +#ifdef CONFIG_IMX9_TPM2_PWM + { + .ops = &g_pwmops, + .id = PWM_TPM2, + .base = IMX9_TPM2_BASE, + .n_channels = CONFIG_IMX9_TPM2_PWM_NCHANNELS, + .chmux = CONFIG_IMX9_TPM2_PWM_CHMUX, + .clk = OSC_24_CLK_FREQ, + }, +#endif + +#ifdef CONFIG_IMX9_TPM3_PWM + { + .ops = &g_pwmops, + .id = PWM_TPM3, + .base = IMX9_TPM3_BASE, + .n_channels = CONFIG_IMX9_TPM3_PWM_NCHANNELS, + .chmux = CONFIG_IMX9_TPM3_PWM_CHMUX, + .clk = WAKEUP_CLK_FREQ, + }, +#endif + +#ifdef CONFIG_IMX9_TPM4_PWM + { + .ops = &g_pwmops, + .id = PWM_TPM4, + .base = IMX9_TPM4_BASE, + .n_channels = CONFIG_IMX9_TPM4_PWM_NCHANNELS, + .chmux = CONFIG_IMX9_TPM4_PWM_CHMUX, + .clk = OSC_24_CLK_FREQ, + }, +#endif + +#ifdef CONFIG_IMX9_TPM5_PWM + { + .ops = &g_pwmops, + .id = PWM_TPM5, + .base = IMX9_TPM5_BASE, + .n_channels = CONFIG_IMX9_TPM5_PWM_NCHANNELS, + .chmux = CONFIG_IMX9_TPM5_PWM_CHMUX, + .clk = OSC_24_CLK_FREQ, + }, +#endif + +#ifdef CONFIG_IMX9_TPM6_PWM + { + .ops = &g_pwmops, + .id = PWM_TPM6, + .base = IMX9_TPM6_BASE, + .n_channels = CONFIG_IMX9_TPM6_PWM_NCHANNELS, + .chmux = CONFIG_IMX9_TPM6_PWM_CHMUX, + .clk = OSC_24_CLK_FREQ, + }, +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pwm_getreg + * + * Description: + * Read the value of an PWM timer register. + * + * Input Parameters: + * priv - A reference to the PWM block status + * offset - The offset to the register to read + * + * Returned Value: + * The current contents of the specified register + * + ****************************************************************************/ + +static inline uint32_t pwm_getreg(struct imx9_pwmtimer_s *priv, int offset) +{ + return getreg32(priv->base + offset); +} + +/**************************************************************************** + * Name: pwm_putreg + * + * Description: + * Read the value of an PWM timer register. + * + * Input Parameters: + * priv - A reference to the PWM block status + * offset - The offset to the register to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void pwm_putreg(struct imx9_pwmtimer_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->base + offset); +} + +/**************************************************************************** + * Name: tpm_mux + * + * Description: + * Mux the tpm output pins to pads. The macros TPMn_PWMx_MUX + * need to be defined in the board.h file + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void tpm_mux(void) +{ +#ifdef CONFIG_IMX9_TPM1_PWM +# ifdef TPM1_PWM0_MUX + imx9_iomux_configure(TPM1_PWM0_MUX); +# endif + +# ifdef TPM1_PWM1_MUX + imx9_iomux_configure(TPM1_PWM1_MUX); +# endif + +# ifdef TPM1_PWM2_MUX + imx9_iomux_configure(TPM1_PWM2_MUX); +# endif + +# ifdef TPM1_PWM3_MUX + imx9_iomux_configure(TPM1_PWM3_MUX); +# endif +#endif + +#ifdef CONFIG_IMX9_TPM2_PWM +# ifdef TPM2_PWM0_MUX + imx9_iomux_configure(TPM2_PWM0_MUX); +# endif + +# ifdef TPM2_PWM1_MUX + imx9_iomux_configure(TPM2_PWM1_MUX); +# endif + +# ifdef TPM2_PWM2_MUX + imx9_iomux_configure(TPM2_PWM2_MUX); +# endif + +# ifdef TPM2_PWM3_MUX + imx9_iomux_configure(TPM2_PWM3_MUX); +# endif +#endif + +#ifdef CONFIG_IMX9_TPM3_PWM +# ifdef TPM3_PWM0_MUX + imx9_iomux_configure(TPM3_PWM0_MUX); +# endif + +# ifdef TPM3_PWM1_MUX + imx9_iomux_configure(TPM3_PWM1_MUX); +# endif + +# ifdef TPM3_PWM2_MUX + imx9_iomux_configure(TPM3_PWM2_MUX); +# endif + +# ifdef TPM3_PWM3_MUX + imx9_iomux_configure(TPM3_PWM3_MUX); +# endif +#endif + +#ifdef CONFIG_IMX9_TPM4_PWM +# ifdef TPM4_PWM0_MUX + imx9_iomux_configure(TPM4_PWM0_MUX); +# endif + +# ifdef TPM4_PWM1_MUX + imx9_iomux_configure(TPM4_PWM1_MUX); +# endif + +# ifdef TPM4_PWM2_MUX + imx9_iomux_configure(TPM4_PWM2_MUX); +# endif + +# ifdef TPM4_PWM3_MUX + imx9_iomux_configure(TPM4_PWM3_MUX); +# endif +#endif + +#ifdef CONFIG_IMX9_TPM5_PWM +# ifdef TPM5_PWM0_MUX + imx9_iomux_configure(TPM5_PWM0_MUX); +# endif + +# ifdef TPM5_PWM1_MUX + imx9_iomux_configure(TPM5_PWM1_MUX); +# endif + +# ifdef TPM5_PWM2_MUX + imx9_iomux_configure(TPM5_PWM2_MUX); +# endif + +# ifdef TPM5_PWM3_MUX + imx9_iomux_configure(TPM5_PWM3_MUX); +# endif +#endif + +#ifdef CONFIG_IMX9_TPM6_PWM +# ifdef TPM6_PWM0_MUX + imx9_iomux_configure(TPM6_PWM0_MUX); +# endif + +# ifdef TPM6_PWM1_MUX + imx9_iomux_configure(TPM6_PWM1_MUX); +# endif + +# ifdef TPM6_PWM2_MUX + imx9_iomux_configure(TPM6_PWM2_MUX); +# endif + +# ifdef TPM6_PWM3_MUX + imx9_iomux_configure(TPM6_PWM3_MUX); +# endif +#endif +} + +/**************************************************************************** + * Name: pwm_update_frequency + * + * Description: + * Initialize the timer trigger, generating the PWM freuency + * + * Input Parameters: + * priv - A reference to the lower half PWM driver state structure + * freq - The requested PWM frequency for this flexio block + * + * Returned Value: + * Zero on success, negated error value on failure + * + ****************************************************************************/ + +static int pwm_update_frequency(struct imx9_pwmtimer_s *priv, int freq) +{ + int i; + + if (freq != priv->frequency) + { + /* Start PWM on all channels if it was previously stopped */ + + if (freq > 0 && priv->frequency == 0) + { + /* Set the EPWM mode for all the configured channels: + * + * High-true pulses (clear output on counter match, set output + * on counter reload, clear output when counter first enabled + * or paused) + * SC[CPWMS] = 0, MSnB:MSnA = 1:0 ELSnB:ELSnA = 0 + */ + + for (i = 0; i < priv->n_channels; i++) + { + pwm_putreg(priv, IMX9_TPM_CXSC_OFFSET(CHMUX(priv, i)), + TPM_CXSC_MSB_MASK); + } + } + + priv->period = freq > 0 ? priv->clk / freq : 0; + + pwminfo("PWM%d frequency: %" PRIu32" period: %" PRIu32 "\n", priv->id, + freq, priv->period); + + /* Set the period */ + + pwm_putreg(priv, IMX9_TPM_MOD_OFFSET, priv->period); + + priv->frequency = freq; + } + + return OK; +} + +/**************************************************************************** + * Name: pwm_update_duty + * + * Description: + * Change the channel duty cycle. + * + * Input Parameters: + * priv - A reference to the lower half PWM driver state structure + * period - PWM pulse width in timer ticks + * channel - Channel to by updated + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_update_duty(struct imx9_pwmtimer_s *priv, int pwm_ch, + ub16_t duty16) +{ + uint64_t duty = duty16 & 0xffffffff; + uint32_t edge = (duty * priv->period + 0x8000) >> 16; + int timer = pwm_ch - 1; + + if (pwm_ch == 0 || timer > priv->n_channels) + { + pwmerr("ERROR: PWM%d has no such channel: %d\n", priv->id, timer); + return -EINVAL; + } + + pwminfo("PWM%d channel %d, p: %d e: %" PRIu32 "\n", priv->id, + CHMUX(priv, timer), priv->period, edge); + + pwm_putreg(priv, IMX9_TPM_CXV_OFFSET(CHMUX(priv, timer)), edge); + + return OK; +} + +/**************************************************************************** + * Name: pwm_setup + * + * Description: + * This method is called when the driver is opened. The lower half driver + * should configure and initialize the device so that it is ready for use. + * It should not, however, output pulses until the start method is called. + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * Assumptions: + * + ****************************************************************************/ + +static int pwm_setup(struct pwm_lowerhalf_s *dev) +{ + return OK; +} + +/**************************************************************************** + * Name: pwm_shutdown + * + * Description: + * This method is called when the driver is closed. The lower half driver + * stop pulsed output, free any resources, disable the timer hardware, and + * put the system into the lowest possible power usage state + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_shutdown(struct pwm_lowerhalf_s *dev) +{ + /* Make sure that the output has been stopped */ + + pwm_stop(dev); + + return OK; +} + +/**************************************************************************** + * Name: pwm_start + * + * Description: + * (Re-)initialize the timer resources and start the pulsed output + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * info - A reference to the characteristics of the pulsed output + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_start(struct pwm_lowerhalf_s *dev, + const struct pwm_info_s *info) +{ + struct imx9_pwmtimer_s *priv = (struct imx9_pwmtimer_s *)dev; + int ret = OK; + int i; + + if (priv == NULL || info == NULL || info->frequency == 0) + { + return -EINVAL; + } + + /* Set the frequency if not changed */ + + if (pwm_update_frequency(priv, info->frequency) == OK) + { + /* Handle channel specific setup */ + + for (i = 0; i < CONFIG_PWM_NCHANNELS; i++) + { + if (ret != OK || info->channels[i].channel == -1) + { + break; + } + + pwm_update_duty(priv, info->channels[i].channel, + info->channels[i].duty); + } + } + + return ret; +} + +/**************************************************************************** + * Name: pwm_stop + * + * Description: + * Stop the pulsed output and reset the timer resources + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + * Assumptions: + * This function is called to stop the pulsed output at anytime. + * + ****************************************************************************/ + +static int pwm_stop(struct pwm_lowerhalf_s *dev) +{ + struct imx9_pwmtimer_s *priv = (struct imx9_pwmtimer_s *)dev; + int i; + + pwminfo("PWM%d stop\n", priv->id); + + /* Check that timer is valid */ + + if (priv == NULL) + { + return -EINVAL; + } + + /* Disable the channels */ + + for (i = 0; i < priv->n_channels; i++) + { + pwm_putreg(priv, IMX9_TPM_CXSC_OFFSET(CHMUX(priv, i)), 0); + } + + /* Set frequency to 0 */ + + pwm_update_frequency(priv, 0); + + return OK; +} + +/**************************************************************************** + * Name: pwm_ioctl + * + * Description: + * Lower-half logic may support platform-specific ioctl commands + * + * Input Parameters: + * dev - A reference to the lower half PWM driver state structure + * cmd - The ioctl command + * arg - The argument accompanying the ioctl command + * + * Returned Value: + * Zero on success; a negated errno value on failure + * + ****************************************************************************/ + +static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd, + unsigned long arg) +{ + return -ENOTTY; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_tpm_pwm_init + * + * Description: + * Initialize tpm blocks to generate EPWM. + * + * Input Parameters: + * pwmid - A number identifying the pwm block. The number of valid + * IDs varies depending on the configuration. + * + * Returned Value: + * On success, a pointer to the lower half PWM driver is + * returned. NULL is returned on any failure. + * + ****************************************************************************/ + +struct pwm_lowerhalf_s *imx9_tpm_pwm_init(tpm_pwm_id_t pwmid) +{ + struct imx9_pwmtimer_s *lower = NULL; + int i; + + for (i = 0; i < sizeof(g_pwmdev) / sizeof(g_pwmdev[0]); i++) + { + if (pwmid == g_pwmdev[i].id) + { + lower = &g_pwmdev[i]; + break; + } + } + + if (lower) + { + /* IO mux */ + + tpm_mux(); + + /* Reset TPM */ + + pwm_putreg(lower, IMX9_TPM_GLOBAL_OFFSET, TPM_GLOBAL_RST_MASK); + pwm_putreg(lower, IMX9_TPM_GLOBAL_OFFSET, 0); + while (pwm_getreg(lower, IMX9_TPM_GLOBAL_OFFSET) != 0); + + /* TPM 1 is always clocked by AON bus and TPM3 by WAKEUP bus */ + + if (pwmid != PWM_TPM1 && pwmid != PWM_TPM3) + { + /* 24 MHz source clock */ + + imx9_ccm_configure_root_clock(CCM_CR_TPM1 + pwmid, OSC_24M, 1); + + /* Enable peripheral clock */ + + imx9_ccm_gate_on(CCM_LPCG_TPM1 + pwmid, true); + } + + /* Set status and control: + * CMOD = 1 (increment on every clock) + * PS = 0 (clock divider 1) + */ + + pwm_putreg(lower, IMX9_TPM_SC_OFFSET, 1 << TPM_SC_CMOD_SHIFT); + + pwminfo("PWM%d at %" PRIxPTR " configured\n", pwmid, lower->base); + } + else + { + pwmerr("ERROR: No such timer configured %d\n", pwmid); + } + + return (struct pwm_lowerhalf_s *)lower; +} + +#endif diff --git a/arch/arm64/src/imx9/imx9_tpm_pwm.h b/arch/arm64/src/imx9/imx9_tpm_pwm.h new file mode 100644 index 0000000000000..f6bdfde28e701 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_tpm_pwm.h @@ -0,0 +1,97 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_tpm_pwm.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_TPM_PWM_H +#define __ARCH_ARM64_SRC_IMX9_IMX9_TPM_PWM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include "hardware/imx9_tpm.h" + +/* Check if PWM support for any channel is enabled. */ + +#ifdef CONFIG_IMX9_TPM_PWM + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef enum +{ + PWM_TPM1 = 0, + PWM_TPM2 = 1, + PWM_TPM3 = 2, + PWM_TPM4 = 3, + PWM_TPM5 = 4, + PWM_TPM6 = 5, +} tpm_pwm_id_t; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_tpm_pwm_init + * + * Description: + * Initialize a TPM block for EPWM usage. + * + * Input Parameters: + * pwmid - A number identifying the pwm block. + * + * Returned Value: + * On success, a pointer to the lower half of the PWM driver is + * returned. NULL is returned on any failure. + * + ****************************************************************************/ + +struct pwm_lowerhalf_s *imx9_tpm_pwm_init(tpm_pwm_id_t pwmid); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_IMX9_TPM_PWM */ +#endif /* __ARCH_ARM64_SRC_IMX9_IMX9_TPM_PWM_H */ diff --git a/arch/arm64/src/imx9/imx9_usbdev.c b/arch/arm64/src/imx9/imx9_usbdev.c new file mode 100644 index 0000000000000..d34f6919c7fc8 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_usbdev.c @@ -0,0 +1,3141 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_usbdev.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include "chip.h" +#include "arm64_internal.h" +#include "imx9_ccm.h" +#include "hardware/imx9_memorymap.h" +#include "hardware/imx9_usbotg.h" +#include "hardware/imx9_ccm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(ARMV8A_DCACHE_LINESIZE) || ARMV8A_DCACHE_LINESIZE == 0 +# undef ARMV8A_DCACHE_LINESIZE +# define ARMV8A_DCACHE_LINESIZE 64 +#endif + +#define DCACHE_LINEMASK (ARMV8A_DCACHE_LINESIZE - 1) + +#if !defined(CONFIG_ARM64_DCACHE_DISABLE) +# define cache_aligned_alloc(s) kmm_memalign(ARMV8A_DCACHE_LINESIZE,(s)) +# define CACHE_ALIGNED_DATA aligned_data(ARMV8A_DCACHE_LINESIZE) +#else +# define cache_aligned_alloc kmm_malloc +# define CACHE_ALIGNED_DATA +#endif + +/* Configuration ************************************************************/ + +#ifndef CONFIG_USBDEV_EP0_MAXSIZE +# define CONFIG_USBDEV_EP0_MAXSIZE 64 +#endif + +#ifndef CONFIG_USBDEV_MAXPOWER +# define CONFIG_USBDEV_MAXPOWER 100 /* mA */ +#endif + +/* Enable reading SOF from interrupt handler vs. simply reading on demand. + * Probably a bad idea... Unless there is some issue with sampling the SOF + * from hardware asynchronously. + */ + +#ifdef CONFIG_IMX9_USB_FRAME_INTERRUPT +# define USB_FRAME_INT USBDEV_USBINTR_SRE +#else +# define USB_FRAME_INT 0 +#endif + +#ifdef CONFIG_DEBUG_FEATURES +# define USB_ERROR_INT USBDEV_USBINTR_UEE +#else +# define USB_ERROR_INT 0 +#endif + +/* Debug ********************************************************************/ + +/* Trace error codes */ + +#define IMX9_TRACEERR_ALLOCFAIL 0x0001 +#define IMX9_TRACEERR_BADCLEARFEATURE 0x0002 +#define IMX9_TRACEERR_BADDEVGETSTATUS 0x0003 +#define IMX9_TRACEERR_BADEPNO 0x0004 +#define IMX9_TRACEERR_BADEPGETSTATUS 0x0005 +#define IMX9_TRACEERR_BADEPTYPE 0x0006 +#define IMX9_TRACEERR_BADGETCONFIG 0x0007 +#define IMX9_TRACEERR_BADGETSETDESC 0x0008 +#define IMX9_TRACEERR_BADGETSTATUS 0x0009 +#define IMX9_TRACEERR_BADSETADDRESS 0x000a +#define IMX9_TRACEERR_BADSETCONFIG 0x000b +#define IMX9_TRACEERR_BADSETFEATURE 0x000c +#define IMX9_TRACEERR_BINDFAILED 0x000d +#define IMX9_TRACEERR_DISPATCHSTALL 0x000e +#define IMX9_TRACEERR_DRIVER 0x000f +#define IMX9_TRACEERR_DRIVERREGISTERED 0x0010 +#define IMX9_TRACEERR_EP0SETUPSTALLED 0x0011 +#define IMX9_TRACEERR_EPINNULLPACKET 0x0012 +#define IMX9_TRACEERR_EPOUTNULLPACKET 0x0013 +#define IMX9_TRACEERR_INVALIDCTRLREQ 0x0014 +#define IMX9_TRACEERR_INVALIDPARMS 0x0015 +#define IMX9_TRACEERR_IRQREGISTRATION 0x0016 +#define IMX9_TRACEERR_NOEP 0x0017 +#define IMX9_TRACEERR_NOTCONFIGURED 0x0018 +#define IMX9_TRACEERR_REQABORTED 0x0019 + +/* Trace interrupt codes */ + +#define IMX9_TRACEINTID_USB 0x0001 +#define IMX9_TRACEINTID_CLEARFEATURE 0x0002 +#define IMX9_TRACEINTID_DEVGETSTATUS 0x0003 +#define IMX9_TRACEINTID_DEVRESET 0x0004 +#define IMX9_TRACEINTID_DISPATCH 0x0005 +#define IMX9_TRACEINTID_EP0COMPLETE 0x0006 +#define IMX9_TRACEINTID_EP0NAK 0x0007 +#define IMX9_TRACEINTID_EP0SETUP 0x0008 +#define IMX9_TRACEINTID_EPGETSTATUS 0x0009 +#define IMX9_TRACEINTID_EPIN 0x000a +#define IMX9_TRACEINTID_EPINQEMPTY 0x000b +#define IMX9_TRACEINTID_EP0INSETADDRESS 0x000c +#define IMX9_TRACEINTID_EPOUT 0x000d +#define IMX9_TRACEINTID_EPOUTQEMPTY 0x000e +#define IMX9_TRACEINTID_EP0SETUPSETADDRESS 0x000f +#define IMX9_TRACEINTID_FRAME 0x0010 +#define IMX9_TRACEINTID_GETCONFIG 0x0011 +#define IMX9_TRACEINTID_GETSETDESC 0x0012 +#define IMX9_TRACEINTID_GETSETIF 0x0013 +#define IMX9_TRACEINTID_GETSTATUS 0x0014 +#define IMX9_TRACEINTID_IFGETSTATUS 0x0015 +#define IMX9_TRACEINTID_SETCONFIG 0x0016 +#define IMX9_TRACEINTID_SETFEATURE 0x0017 +#define IMX9_TRACEINTID_SUSPENDED 0x0018 +#define IMX9_TRACEINTID_RESUMED 0x0019 +#define IMX9_TRACEINTID_SYNCHFRAME 0x001a + +#ifdef CONFIG_USBDEV_TRACE_STRINGS +const struct trace_msg_t g_usb_trace_strings_deverror[] = +{ + TRACE_STR(IMX9_TRACEERR_ALLOCFAIL), + TRACE_STR(IMX9_TRACEERR_BADCLEARFEATURE), + TRACE_STR(IMX9_TRACEERR_BADDEVGETSTATUS), + TRACE_STR(IMX9_TRACEERR_BADEPNO), + TRACE_STR(IMX9_TRACEERR_BADEPGETSTATUS), + TRACE_STR(IMX9_TRACEERR_BADEPTYPE), + TRACE_STR(IMX9_TRACEERR_BADGETCONFIG), + TRACE_STR(IMX9_TRACEERR_BADGETSETDESC), + TRACE_STR(IMX9_TRACEERR_BADGETSTATUS), + TRACE_STR(IMX9_TRACEERR_BADSETADDRESS), + TRACE_STR(IMX9_TRACEERR_BADSETCONFIG), + TRACE_STR(IMX9_TRACEERR_BADSETFEATURE), + TRACE_STR(IMX9_TRACEERR_BINDFAILED), + TRACE_STR(IMX9_TRACEERR_DISPATCHSTALL), + TRACE_STR(IMX9_TRACEERR_DRIVER), + TRACE_STR(IMX9_TRACEERR_DRIVERREGISTERED), + TRACE_STR(IMX9_TRACEERR_EP0SETUPSTALLED), + TRACE_STR(IMX9_TRACEERR_EPINNULLPACKET), + TRACE_STR(IMX9_TRACEERR_EPOUTNULLPACKET), + TRACE_STR(IMX9_TRACEERR_INVALIDCTRLREQ), + TRACE_STR(IMX9_TRACEERR_INVALIDPARMS), + TRACE_STR(IMX9_TRACEERR_IRQREGISTRATION), + TRACE_STR(IMX9_TRACEERR_NOEP), + TRACE_STR(IMX9_TRACEERR_NOTCONFIGURED), + TRACE_STR(IMX9_TRACEERR_REQABORTED), + TRACE_STR_END +}; + +const struct trace_msg_t g_usb_trace_strings_intdecode[] = +{ + TRACE_STR(IMX9_TRACEINTID_USB), + TRACE_STR(IMX9_TRACEINTID_CLEARFEATURE), + TRACE_STR(IMX9_TRACEINTID_DEVGETSTATUS), + TRACE_STR(IMX9_TRACEINTID_DEVRESET), + TRACE_STR(IMX9_TRACEINTID_DISPATCH), + TRACE_STR(IMX9_TRACEINTID_EP0COMPLETE), + TRACE_STR(IMX9_TRACEINTID_EP0NAK), + TRACE_STR(IMX9_TRACEINTID_EP0SETUP), + TRACE_STR(IMX9_TRACEINTID_EPGETSTATUS), + TRACE_STR(IMX9_TRACEINTID_EPIN), + TRACE_STR(IMX9_TRACEINTID_EPINQEMPTY), + TRACE_STR(IMX9_TRACEINTID_EP0INSETADDRESS), + TRACE_STR(IMX9_TRACEINTID_EPOUT), + TRACE_STR(IMX9_TRACEINTID_EPOUTQEMPTY), + TRACE_STR(IMX9_TRACEINTID_EP0SETUPSETADDRESS), + TRACE_STR(IMX9_TRACEINTID_FRAME), + TRACE_STR(IMX9_TRACEINTID_GETCONFIG), + TRACE_STR(IMX9_TRACEINTID_GETSETDESC), + TRACE_STR(IMX9_TRACEINTID_GETSETIF), + TRACE_STR(IMX9_TRACEINTID_GETSTATUS), + TRACE_STR(IMX9_TRACEINTID_IFGETSTATUS), + TRACE_STR(IMX9_TRACEINTID_SETCONFIG), + TRACE_STR(IMX9_TRACEINTID_SETFEATURE), + TRACE_STR(IMX9_TRACEINTID_SUSPENDED), + TRACE_STR(IMX9_TRACEINTID_RESUMED), + TRACE_STR(IMX9_TRACEINTID_SYNCHFRAME), + TRACE_STR_END +}; +#endif + +/* Hardware interface *******************************************************/ + +/* This represents a Endpoint Transfer Descriptor dQH overlay (32 bytes) */ + +#define IMX9_DTD_S \ + volatile uint32_t nextdesc; /* Address of the next DMA descripto in RAM */ \ + volatile uint32_t config; /* Misc. bit encoded configuration information */ \ + uint32_t buffer0; /* Buffer start address */ \ + uint32_t buffer1; /* Buffer start address */ \ + uint32_t buffer2; /* Buffer start address */ \ + uint32_t buffer3; /* Buffer start address */ \ + uint32_t buffer4; /* Buffer start address */ \ + uint32_t xfer_len; /* Software only - transfer len that was queued */ \ + +struct imx9_dtd_ovl_s +{ + IMX9_DTD_S +}; + +/* This represents a Endpoint Transfer Descriptor - cache line aligned */ + +struct imx9_dtd_s +{ + IMX9_DTD_S +} CACHE_ALIGNED_DATA; + +/* DTD nextdesc field */ + +#define DTD_NEXTDESC_INVALID (1 << 0) /* Bit 0 : Next Descriptor Invalid. The "Terminate" bit. */ + +/* DTD config field */ + +#define DTD_CONFIG_LENGTH(n) ((n) << 16) /* Bits 16-31 : Total bytes to transfer */ +#define DTD_CONFIG_IOC (1 << 15) /* Bit 15 : Interrupt on Completion */ +#define DTD_CONFIG_MULT_VARIABLE (0 << 10) /* Bits 10-11 : Number of packets executed per transacation descriptor (override) */ +#define DTD_CONFIG_MULT_NUM(n) ((n) << 10) +#define DTD_CONFIG_ACTIVE (1 << 7) /* Bit 7 : Status Active */ +#define DTD_CONFIG_HALTED (1 << 6) /* Bit 6 : Status Halted */ +#define DTD_CONFIG_BUFFER_ERROR (1 << 5) /* Bit 6 : Status Buffer Error */ +#define DTD_CONFIG_TRANSACTION_ERROR (1 << 3) /* Bit 3 : Status Transaction Error */ + +/* This represents a queue head */ + +struct imx9_dqh_s +{ + uint32_t capability; /* Endpoint capability */ + uint32_t currdesc; /* Current dTD pointer */ + struct imx9_dtd_ovl_s overlay; /* DTD overlay */ + volatile uint32_t setup[2]; /* Set-up buffer */ +} CACHE_ALIGNED_DATA; + +/* DQH capability field */ + +#define DQH_CAPABILITY_MULT_VARIABLE (0 << 30) /* Bits 30-31 : Number of packets executed per transaction descriptor */ +#define DQH_CAPABILITY_MULT_NUM(n) ((n) << 30) +#define DQH_CAPABILITY_ZLT (1 << 29) /* Bit 29 : Zero Length Termination Select */ +#define DQH_CAPABILITY_MAX_PACKET(n) ((n) << 16) /* Bits 16-29 : Maximum packet size of associated endpoint (<1024) */ +#define DQH_CAPABILITY_IOS (1 << 15) /* Bit 15 : Interrupt on Setup */ + +/* Endpoints ****************************************************************/ + +/* Number of endpoints */ + +#define IMX9_NLOGENDPOINTS (8) /* ep0-7 */ +#define IMX9_NPHYSENDPOINTS (16) /* x2 for IN and OUT */ + +/* Odd physical endpoint numbers are IN; even are OUT */ + +#define IMX9_EPPHYIN(epphy) (((epphy) & 1) != 0) +#define IMX9_EPPHYOUT(epphy) (((epphy) & 1) == 0) + +#define IMX9_EPPHYIN2LOG(epphy) (((uint8_t)(epphy) >> 1) |USB_DIR_IN) +#define IMX9_EPPHYOUT2LOG(epphy) (((uint8_t)(epphy) >> 1) | USB_DIR_OUT) + +/* Endpoint 0 is special... */ + +#define IMX9_EP0_OUT (0) +#define IMX9_EP0_IN (1) + +/* Each endpoint has somewhat different characteristics */ + +#define IMX9_EPALLSET (0xffff) /* All endpoints */ +#define IMX9_EPOUTSET (0x5555) /* Even phy endpoint numbers are OUT EPs */ +#define IMX9_EPINSET (0xaaaa) /* Odd endpoint numbers are IN EPs */ +#define IMX9_EPCTRLSET (0x0003) /* EP0 IN/OUT are control endpoints */ +#define IMX9_EPINTRSET (0x000c) /* Interrupt endpoints */ +#define IMX9_EPBULKSET (0x0ff0) /* Bulk endpoints */ +#define IMX9_EPISOCSET (0xf000) /* Isochronous endpoints */ + +/* Maximum packet sizes for endpoints */ + +#define IMX9_EP0MAXPACKET (64) /* EP0 max packet size (1-64) */ +#define IMX9_BULKMAXPACKET (512) /* Bulk endpoint max packet (8/16/32/64/512) */ +#define IMX9_INTRMAXPACKET (1024) /* Interrupt endpoint max packet (1 to 1024) */ +#define IMX9_ISOCMAXPACKET (512) /* Acutally 1..1023 */ + +/* Endpoint bit position in SETUPSTAT, PRIME, FLUSH, STAT, COMPLETE + * registers + */ + +#define IMX9_ENDPTSHIFT(epphy) (IMX9_EPPHYIN(epphy) ? (16 + ((epphy) >> 1)) : ((epphy) >> 1)) +#define IMX9_ENDPTMASK(epphy) (1 << IMX9_ENDPTSHIFT(epphy)) +#define IMX9_ENDPTMASK_ALL 0x00ff00ff + +/* Request queue operations *************************************************/ + +#define imx9_rqempty(ep) ((ep)->head == NULL) +#define imx9_rqpeek(ep) ((ep)->head) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* A container for a request so that the request may be retained in a list */ + +struct imx9_req_s +{ + struct usbdev_req_s req; /* Standard USB request */ + struct imx9_req_s *flink; /* Supports a singly linked list */ +}; + +/* This is the internal representation of an endpoint */ + +struct imx9_ep_s +{ + /* Common endpoint fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_ep_s + * to struct imx9_ep_s. + */ + + struct usbdev_ep_s ep; /* Standard endpoint structure */ + + /* IMX9XX-specific fields */ + + struct imx9_usb_s *dev; /* Reference to private driver data */ + struct imx9_req_s *head; /* Request list for this endpoint */ + struct imx9_req_s *tail; + uint8_t epphy; /* Physical EP address */ + uint8_t stalled:1; /* 1: Endpoint is stalled */ +}; + +/* Structure for ep0 short transfers */ + +struct imx9_ep0_s +{ + uint8_t * const buf; /* buffer for EP0 short transfers */ + uint16_t buf_len; /* buffer length */ + struct usb_ctrlreq_s ctrl; /* structure for EP0 short transfers */ + uint8_t state; /* state of certain EP0 operations */ +}; + +/* This structure retains the state of the USB device controller */ + +struct imx9_usb_s +{ + /* Common device fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_s + * to struct imx9_usb_s. + */ + + struct usbdev_s usbdev; + + /* The bound device class driver */ + + struct usbdevclass_driver_s *driver; + + const int id; /* Id of the usb controller */ + const uintptr_t base; /* Base address of the controller */ + uint8_t paddr; /* Address assigned by SETADDRESS */ + uint8_t stalled:1; /* 1: Protocol stalled */ + uint8_t selfpowered:1; /* 1: Device is self powered */ + uint8_t paddrset:1; /* 1: Peripheral addr has been set */ + uint8_t attached:1; /* 1: Host attached */ + uint8_t suspended:1; /* 1: Suspended */ + uint32_t softprio; /* Bitset of high priority interrupts */ + uint32_t epavail; /* Bitset of available endpoints */ +#ifdef CONFIG_IMX9_USB_FRAME_INTERRUPT + uint32_t sof; /* Last start-of-frame */ +#endif + + struct imx9_ep0_s ep0; /* ep0 */ + + /* The endpoint list */ + + struct imx9_ep_s eplist[IMX9_NPHYSENDPOINTS]; + struct imx9_dqh_s * const qh; + struct imx9_dtd_s * const td; +}; + +#define EP0STATE_IDLE 0 /* Idle State, leave on receiving a setup packet or epsubmit */ +#define EP0STATE_SETUP_OUT 1 /* Setup Packet received - SET/CLEAR */ +#define EP0STATE_SETUP_IN 2 /* Setup Packet received - GET */ +#define EP0STATE_SHORTREAD 3 /* Short read without a usb_request */ +#define EP0STATE_SHORTWRITE 4 /* Short write without a usb_request */ +#define EP0STATE_WAIT_NAK_OUT 5 /* Waiting for Host to illicit status phase (GET) */ +#define EP0STATE_WAIT_NAK_IN 6 /* Waiting for Host to illicit status phase (SET/CLEAR) */ +#define EP0STATE_WAIT_STATUS_OUT 7 /* Wait for status phase to complete */ +#define EP0STATE_WAIT_STATUS_IN 8 /* Wait for status phase to complete */ +#define EP0STATE_DATA_IN 9 +#define EP0STATE_DATA_OUT 10 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations ******************************************************/ + +#ifdef CONFIG_IMX9_USB_REGDEBUG +static uint32_t imx9_getreg(struct imx9_usb_s *priv, off_t offset); +static void imx9_putreg(struct imx9_usb_s *priv, off_t offset, uint32_t val); +#else +# define imx9_getreg(priv, offset) getreg32(priv->base + offset) +# define imx9_putreg(priv, offset, val) putreg32(val,priv->base + offset) +#endif + +static inline void imx9_modifyreg(struct imx9_usb_s *priv, + off_t offset, + uint32_t clear, + uint32_t set); + +/* Request queue operations *************************************************/ + +static struct imx9_req_s *imx9_rqdequeue( + struct imx9_ep_s *privep); +static bool imx9_rqenqueue(struct imx9_ep_s *privep, + struct imx9_req_s *req); + +/* Low level data transfers and request operations **************************/ + +static inline void imx9_writedtd(struct imx9_dtd_s *dtd, + const uint8_t *data, + uint32_t nbytes); +static inline void imx9_queuedtd(struct imx9_usb_s *priv, uint8_t epphy, + struct imx9_dtd_s *dtd); +static inline void imx9_ep0xfer(struct imx9_usb_s *priv, uint8_t epphy, + uint8_t *data, + uint32_t nbytes); +static void imx9_readsetup(struct imx9_usb_s *priv, uint8_t epphy, + struct usb_ctrlreq_s *ctrl); +static inline void imx9_set_address(struct imx9_usb_s *priv, + uint16_t address); + +static void imx9_flushep(struct imx9_ep_s *privep); + +static int imx9_progressep(struct imx9_ep_s *privep); +static void imx9_reqcomplete(struct imx9_ep_s *privep, + struct imx9_req_s *privreq, int16_t result); + +static void imx9_cancelrequests(struct imx9_ep_s *privep, + int16_t status); + +/* Interrupt handling *******************************************************/ + +static struct imx9_ep_s *imx9_epfindbyaddr(struct imx9_usb_s *priv, + uint16_t eplog); +static void imx9_dispatchrequest(struct imx9_usb_s *priv, + const struct usb_ctrlreq_s *ctrl); +static void imx9_ep0configure(struct imx9_usb_s *priv); +static void imx9_usbreset(struct imx9_usb_s *priv); +static inline void imx9_ep0state(struct imx9_usb_s *priv, + uint16_t state); +static void imx9_ep0setup(struct imx9_usb_s *priv); +static void imx9_ep0complete(struct imx9_usb_s *priv, + uint8_t epphy); +static void imx9_ep0nak(struct imx9_usb_s *priv, uint8_t epphy); +static bool imx9_epcomplete(struct imx9_usb_s *priv, + uint8_t epphy); +static int imx9_usbinterrupt(int irq, void *context, + void *arg); + +/* Endpoint operations ******************************************************/ + +/* USB device controller operations *****************************************/ + +static int imx9_epconfigure(struct usbdev_ep_s *ep, + const struct usb_epdesc_s *desc, bool last); +static int imx9_epdisable(struct usbdev_ep_s *ep); +static struct usbdev_req_s *imx9_epallocreq(struct usbdev_ep_s *ep); +static void imx9_epfreereq(struct usbdev_ep_s *ep, + struct usbdev_req_s *); +#ifdef CONFIG_USBDEV_DMA +static void *imx9_epallocbuffer(struct usbdev_ep_s *ep, + uint16_t bytes); +static void imx9_epfreebuffer(struct usbdev_ep_s *ep, + void *buf); +#endif +static int imx9_epsubmit(struct usbdev_ep_s *ep, + struct usbdev_req_s *req); +static int imx9_epcancel(struct usbdev_ep_s *ep, + struct usbdev_req_s *req); +static int imx9_epstall(struct usbdev_ep_s *ep, bool resume); + +static struct usbdev_ep_s *imx9_allocep(struct usbdev_s *dev, + uint8_t epno, bool in, uint8_t eptype); +static void imx9_freeep(struct usbdev_s *dev, + struct usbdev_ep_s *ep); +static int imx9_getframe(struct usbdev_s *dev); +static int imx9_wakeup(struct usbdev_s *dev); +static int imx9_selfpowered(struct usbdev_s *dev, bool selfpowered); +static int imx9_pullup(struct usbdev_s *dev, bool enable); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Note: dqh lists must be aligned to a 2048 byte + * boundary, since ENDPTLISTADDR register last 10 bits are tied to 0 + */ + +#ifdef CONFIG_IMX9_USBDEV_USBC1 +static uint8_t g_usb0_ep0buf[64] CACHE_ALIGNED_DATA; +static struct imx9_dqh_s g_usb0_qh[IMX9_NPHYSENDPOINTS] aligned_data(2048); +static struct imx9_dtd_s g_usb0_td[IMX9_NPHYSENDPOINTS]; +#endif + +#ifdef CONFIG_IMX9_USBDEV_USBC2 +static uint8_t g_usb1_ep0buf[64] CACHE_ALIGNED_DATA; +static struct imx9_dqh_s g_usb1_qh[IMX9_NPHYSENDPOINTS] aligned_data(2048); +static struct imx9_dtd_s g_usb1_td[IMX9_NPHYSENDPOINTS]; +#endif + +static struct imx9_usb_s g_usbdev[] = +{ +#ifdef CONFIG_IMX9_USBDEV_USBC1 + { + .id = 0, + .base = IMX9_USB_OTG1_BASE, + .ep0.buf = g_usb0_ep0buf, + .qh = g_usb0_qh, + .td = g_usb0_td, + }, +#endif + +#ifdef CONFIG_IMX9_USBDEV_USBC2 + { + .id = 1, + .base = IMX9_USB_OTG2_BASE, + .ep0.buf = g_usb1_ep0buf, + .qh = g_usb1_qh, + .td = g_usb1_td, + }, +#endif +}; + +static const int n_usbdevs = sizeof(g_usbdev) / sizeof(g_usbdev[0]); + +static const struct usbdev_epops_s g_epops = +{ + .configure = imx9_epconfigure, + .disable = imx9_epdisable, + .allocreq = imx9_epallocreq, + .freereq = imx9_epfreereq, +#ifdef CONFIG_USBDEV_DMA + .allocbuffer = imx9_epallocbuffer, + .freebuffer = imx9_epfreebuffer, +#endif + .submit = imx9_epsubmit, + .cancel = imx9_epcancel, + .stall = imx9_epstall, +}; + +static const struct usbdev_ops_s g_devops = +{ + .allocep = imx9_allocep, + .freeep = imx9_freeep, + .getframe = imx9_getframe, + .wakeup = imx9_wakeup, + .selfpowered = imx9_selfpowered, + .pullup = imx9_pullup, +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_getreg + * + * Description: + * Get the contents of an IMX93x register + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_USB_REGDEBUG +static uint32_t imx9_getreg(struct imx9_usb_s *priv, off_t offset) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + + /* Read the value from the register */ + + uint32_t val = getreg32(priv->base + offset); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + uinfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + uinfo("[repeats %d more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + uinfo("%08x->%08x\n", priv->base + offset, val); + return val; +} +#endif + +/**************************************************************************** + * Name: imx9_putreg + * + * Description: + * Set the contents of an IMX93x register to a value + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_USB_REGDEBUG +static void imx9_putreg(struct imx9_usb_s *priv, off_t offset, uint32_t val) +{ + /* Show the register value being written */ + + uinfo("%08x<-%08x\n", priv->base + offset, val); + + /* Write the value */ + + putreg32(val, priv->base + offset); +} +#endif + +/**************************************************************************** + * Name: imx9_modifyreg + * + * Description: + * Change bits in a register + * + ****************************************************************************/ + +static inline void imx9_modifyreg(struct imx9_usb_s *priv, off_t offset, + uint32_t clear, uint32_t set) +{ + uint32_t reg = imx9_getreg(priv, offset); + reg &= ~clear; + reg |= set; + imx9_putreg(priv, offset, reg); +} + +/**************************************************************************** + * Name: imx9_rqdequeue + * + * Description: + * Remove a request from an endpoint request queue + * + ****************************************************************************/ + +static struct imx9_req_s *imx9_rqdequeue(struct imx9_ep_s *privep) +{ + struct imx9_req_s *ret = privep->head; + + if (ret) + { + privep->head = ret->flink; + if (!privep->head) + { + privep->tail = NULL; + } + + ret->flink = NULL; + } + + return ret; +} + +/**************************************************************************** + * Name: imx9_rqenqueue + * + * Description: + * Add a request from an endpoint request queue + * + ****************************************************************************/ + +static bool imx9_rqenqueue(struct imx9_ep_s *privep, + struct imx9_req_s *req) +{ + bool is_empty = !privep->head; + + req->flink = NULL; + if (is_empty) + { + privep->head = req; + privep->tail = req; + } + else + { + privep->tail->flink = req; + privep->tail = req; + } + + return is_empty; +} + +/**************************************************************************** + * Name: imx9_writedtd + * + * Description: + * Initialise a DTD to transfer the data + * + ****************************************************************************/ + +static inline void imx9_writedtd(struct imx9_dtd_s *dtd, + const uint8_t *data, + uint32_t nbytes) +{ + dtd->nextdesc = DTD_NEXTDESC_INVALID; + dtd->config = DTD_CONFIG_LENGTH(nbytes) | DTD_CONFIG_IOC | + DTD_CONFIG_ACTIVE; + dtd->buffer0 = (uint32_t)((uintptr_t) data); + dtd->buffer1 = (uint32_t)(((uintptr_t) data) + 0x1000) & 0xfffff000; + dtd->buffer2 = (uint32_t)(((uintptr_t) data) + 0x2000) & 0xfffff000; + dtd->buffer3 = (uint32_t)(((uintptr_t) data) + 0x3000) & 0xfffff000; + dtd->buffer4 = (uint32_t)(((uintptr_t) data) + 0x4000) & 0xfffff000; + dtd->xfer_len = nbytes; + + up_clean_dcache((uintptr_t)dtd, + (uintptr_t)dtd + sizeof(struct imx9_dtd_s)); + up_clean_dcache((uintptr_t)data, + (uintptr_t)data + nbytes); +} + +/**************************************************************************** + * Name: imx9_queuedtd + * + * Description: + * Add the DTD to the device list + * + * Assumptions: + * DTD is already flushed to RAM. + * + ****************************************************************************/ + +static void imx9_queuedtd(struct imx9_usb_s *priv, uint8_t epphy, + struct imx9_dtd_s *dtd) +{ + struct imx9_dqh_s *dqh = &priv->qh[epphy]; + + /* Queue the DTD onto the Endpoint + * NOTE - this only works when no DTD is currently queued + */ + + dqh->overlay.nextdesc = (uint32_t)(uintptr_t)dtd; + dqh->overlay.config &= ~(DTD_CONFIG_ACTIVE | DTD_CONFIG_HALTED); + + up_flush_dcache((uintptr_t)dqh, + (uintptr_t)dqh + sizeof(struct imx9_dqh_s)); + + uint32_t bit = IMX9_ENDPTMASK(epphy); + + imx9_modifyreg(priv, IMX9_USBDEV_ENDPTPRIME_OFFSET, 0, bit); + + while (imx9_getreg(priv, IMX9_USBDEV_ENDPTPRIME_OFFSET) & bit); +} + +/**************************************************************************** + * Name: imx9_ep0xfer + * + * Description: + * Schedule a short transfer for Endpoint 0 (IN or OUT) + * + ****************************************************************************/ + +static inline void imx9_ep0xfer(struct imx9_usb_s *priv, uint8_t epphy, + uint8_t *buf, uint32_t nbytes) +{ + struct imx9_dtd_s *dtd = &priv->td[epphy]; + + imx9_writedtd(dtd, buf, nbytes); + + imx9_queuedtd(priv, epphy, dtd); +} + +/**************************************************************************** + * Name: imx9_readsetup + * + * Description: + * Read a Setup packet from the DTD. + * + ****************************************************************************/ + +static void imx9_readsetup(struct imx9_usb_s *priv, uint8_t epphy, + struct usb_ctrlreq_s *ctrl) +{ + struct imx9_dqh_s *dqh = &priv->qh[epphy]; + int i; + + do + { + /* Set the trip wire */ + + imx9_modifyreg(priv, IMX9_USBDEV_USBCMD_OFFSET, 0, USBDEV_USBCMD_SUTW); + + up_invalidate_dcache((uintptr_t)dqh, + (uintptr_t)dqh + sizeof(struct imx9_dqh_s)); + + /* Copy the request... */ + + for (i = 0; i < 8; i++) + { + ((uint8_t *) ctrl)[i] = ((uint8_t *) dqh->setup)[i]; + } + } + + while (!(imx9_getreg(priv, + IMX9_USBDEV_USBCMD_OFFSET) & USBDEV_USBCMD_SUTW)); + + /* Clear the trip wire */ + + imx9_modifyreg(priv, IMX9_USBDEV_USBCMD_OFFSET, USBDEV_USBCMD_SUTW, 0); + + up_clean_dcache((uintptr_t)dqh, + (uintptr_t)dqh + sizeof(struct imx9_dqh_s)); + + /* Clear the Setup Interrupt */ + + imx9_putreg(priv, IMX9_USBDEV_ENDPTSETUPSTAT_OFFSET, + IMX9_ENDPTMASK(IMX9_EP0_OUT)); +} + +/**************************************************************************** + * Name: imx9_set_address + * + * Description: + * Set the devices USB address + * + ****************************************************************************/ + +static inline void imx9_set_address(struct imx9_usb_s *priv, + uint16_t address) +{ + priv->paddr = address; + priv->paddrset = address != 0; + + imx9_modifyreg(priv, IMX9_USBDEV_DEVICEADDR_OFFSET, USBDEV_DEVICEADDR_MASK, + priv->paddr << USBDEV_DEVICEADDR_SHIFT); +} + +/**************************************************************************** + * Name: imx9_flushep + * + * Description: + * Flush any primed descriptors from this ep + * + ****************************************************************************/ + +static void imx9_flushep(struct imx9_ep_s *privep) +{ + uint32_t mask = IMX9_ENDPTMASK(privep->epphy); + struct imx9_usb_s *priv = privep->dev; + + do + { + imx9_putreg(priv, IMX9_USBDEV_ENDPTFLUSH_OFFSET, mask); + while ((imx9_getreg(priv, IMX9_USBDEV_ENDPTFLUSH_OFFSET) & mask) != 0); + } + while ((imx9_getreg(priv, IMX9_USBDEV_ENDPTSTATUS_OFFSET) & mask) != 0); +} + +/**************************************************************************** + * Name: imx9_progressep + * + * Description: + * Progress the Endpoint by priming the first request into the queue head + * + ****************************************************************************/ + +static int imx9_progressep(struct imx9_ep_s *privep) +{ + struct imx9_usb_s *priv = privep->dev; + struct imx9_dtd_s *dtd = &priv->td[privep->epphy]; + struct imx9_req_s *privreq; + + /* Check the request from the head of the endpoint request queue */ + + privreq = imx9_rqpeek(privep); + if (!privreq) + { + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_EPINQEMPTY), 0); + return OK; + } + + /* Ignore any attempt to send a zero length packet */ + + if (privreq->req.len == 0) + { + /* If the class driver is responding to a setup packet, then wait for + * the host to illicit the response + */ + + if (privep->epphy == IMX9_EP0_IN && + privep->dev->ep0.state == EP0STATE_SETUP_OUT) + { + imx9_ep0state(priv, EP0STATE_WAIT_NAK_IN); + } + else + { + if (IMX9_EPPHYIN(privep->epphy)) + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_EPINNULLPACKET), 0); + } + else + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_EPOUTNULLPACKET), 0); + } + } + + imx9_reqcomplete(privep, imx9_rqdequeue(privep), OK); + return OK; + } + + if (privep->epphy == IMX9_EP0_IN) + { + imx9_ep0state(priv, EP0STATE_DATA_IN); + } + else if (privep->epphy == IMX9_EP0_OUT) + { + imx9_ep0state(priv, EP0STATE_DATA_OUT); + } + + int bytesleft = privreq->req.len - privreq->req.xfrd; + + if (IMX9_EPPHYIN(privep->epphy)) + { + usbtrace(TRACE_WRITE(privep->epphy), privreq->req.xfrd); + } + else + { + usbtrace(TRACE_READ(privep->epphy), privreq->req.xfrd); + } + + /* Initialise the DTD to transfer the next chunk */ + + imx9_writedtd(dtd, privreq->req.buf + privreq->req.xfrd, bytesleft); + + /* Then queue onto the DQH */ + + imx9_queuedtd(priv, privep->epphy, dtd); + + return OK; +} + +/**************************************************************************** + * Name: imx9_reqcomplete + * + * Description: + * Handle termination of the request at the head of the endpoint request + * queue. + * + ****************************************************************************/ + +static void imx9_reqcomplete(struct imx9_ep_s *privep, + struct imx9_req_s *privreq, int16_t result) +{ + /* If endpoint 0, temporarily reflect the state of protocol stalled + * in the callback. + */ + + bool stalled = privep->stalled; + if (privep->epphy == IMX9_EP0_IN) + privep->stalled = privep->dev->stalled; + + /* Save the result in the request structure */ + + privreq->req.result = result; + + /* Callback to the request completion handler */ + + privreq->req.callback(&privep->ep, &privreq->req); + + /* Restore the stalled indication */ + + privep->stalled = stalled; +} + +/**************************************************************************** + * Name: imx9_cancelrequests + * + * Description: + * Cancel all pending requests for an endpoint + * + ****************************************************************************/ + +static void imx9_cancelrequests(struct imx9_ep_s *privep, int16_t status) +{ + if (!imx9_rqempty(privep)) + imx9_flushep(privep); + + while (!imx9_rqempty(privep)) + { + /* FIXME: the entry at the head should be sync'd with the DTD + * FIXME: only report the error status if the transfer hasn't completed + */ + + usbtrace(TRACE_COMPLETE(privep->epphy), + (imx9_rqpeek(privep))->req.xfrd); + imx9_reqcomplete(privep, imx9_rqdequeue(privep), status); + } +} + +/**************************************************************************** + * Name: imx9_epfindbyaddr + * + * Description: + * Find the physical endpoint structure corresponding to a logic endpoint + * address + * + ****************************************************************************/ + +static struct imx9_ep_s *imx9_epfindbyaddr(struct imx9_usb_s *priv, + uint16_t eplog) +{ + struct imx9_ep_s *privep; + int i; + + /* Endpoint zero is a special case */ + + if (USB_EPNO(eplog) == 0) + { + return &priv->eplist[0]; + } + + /* Handle the remaining */ + + for (i = 1; i < IMX9_NPHYSENDPOINTS; i++) + { + privep = &priv->eplist[i]; + + /* Same logical endpoint number? (includes direction bit) */ + + if (eplog == privep->ep.eplog) + { + /* Return endpoint found */ + + return privep; + } + } + + /* Return endpoint not found */ + + return NULL; +} + +/**************************************************************************** + * Name: imx9_dispatchrequest + * + * Description: + * Provide unhandled setup actions to the class driver. This is logically + * part of the USB interrupt handler. + * + ****************************************************************************/ + +static void imx9_dispatchrequest(struct imx9_usb_s *priv, + const struct usb_ctrlreq_s *ctrl) +{ + int ret = -EIO; + + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_DISPATCH), 0); + if (priv->driver) + { + /* Invalidate buffer data cache */ + + up_invalidate_dcache((uintptr_t)priv->ep0.buf, + (uintptr_t)priv->ep0.buf + sizeof(priv->ep0.buf)); + + /* Forward to the control request to the class driver implementation */ + + ret = CLASS_SETUP(priv->driver, &priv->usbdev, ctrl, priv->ep0.buf, + priv->ep0.buf_len); + } + + if (ret < 0) + { + /* Stall on failure */ + + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_DISPATCHSTALL), 0); + priv->stalled = true; + } +} + +/**************************************************************************** + * Name: imx9_ep0configure + * + * Description: + * Reset Usb engine + * + ****************************************************************************/ + +static void imx9_ep0configure(struct imx9_usb_s *priv) +{ + /* Enable ep0 IN and ep0 OUT */ + + priv->qh[IMX9_EP0_OUT].capability = + (DQH_CAPABILITY_MAX_PACKET(CONFIG_USBDEV_EP0_MAXSIZE) | + DQH_CAPABILITY_IOS | DQH_CAPABILITY_ZLT); + + priv->qh[IMX9_EP0_IN].capability = + (DQH_CAPABILITY_MAX_PACKET(CONFIG_USBDEV_EP0_MAXSIZE) | + DQH_CAPABILITY_IOS | DQH_CAPABILITY_ZLT); + + priv->qh[IMX9_EP0_OUT].currdesc = DTD_NEXTDESC_INVALID; + priv->qh[IMX9_EP0_IN].currdesc = DTD_NEXTDESC_INVALID; + + up_clean_dcache((uintptr_t)priv->qh, + (uintptr_t)priv->qh + (sizeof(struct imx9_dqh_s) * 2)); + + /* Enable EP0 */ + + imx9_modifyreg(priv, IMX9_USBDEV_ENDPTCTRL0_OFFSET, 0, + USBDEV_ENDPTCTRL0_RXE | USBDEV_ENDPTCTRL0_TXE); +} + +/**************************************************************************** + * Name: imx9_usbreset + * + * Description: + * Reset Usb engine + * + ****************************************************************************/ + +static void imx9_usbreset(struct imx9_usb_s *priv) +{ + int epphy; + + /* Disable all endpoints. Control endpoint 0 is always enabled */ + + imx9_modifyreg(priv, IMX9_USBDEV_ENDPTCTRL1_OFFSET, + USBDEV_ENDPTCTRL_RXE | USBDEV_ENDPTCTRL_TXE, 0); + imx9_modifyreg(priv, IMX9_USBDEV_ENDPTCTRL2_OFFSET, + USBDEV_ENDPTCTRL_RXE | USBDEV_ENDPTCTRL_TXE, 0); + imx9_modifyreg(priv, IMX9_USBDEV_ENDPTCTRL3_OFFSET, + USBDEV_ENDPTCTRL_RXE | USBDEV_ENDPTCTRL_TXE, 0); + imx9_modifyreg(priv, IMX9_USBDEV_ENDPTCTRL4_OFFSET, + USBDEV_ENDPTCTRL_RXE | USBDEV_ENDPTCTRL_TXE, 0); + imx9_modifyreg(priv, IMX9_USBDEV_ENDPTCTRL5_OFFSET, + USBDEV_ENDPTCTRL_RXE | USBDEV_ENDPTCTRL_TXE, 0); + + /* Clear all pending interrupts */ + + imx9_putreg(priv, IMX9_USBDEV_ENDPTNAK_OFFSET, + imx9_getreg(priv, IMX9_USBDEV_ENDPTNAK_OFFSET)); + + imx9_putreg(priv, IMX9_USBDEV_ENDPTSETUPSTAT_OFFSET, + imx9_getreg(priv, IMX9_USBDEV_ENDPTSETUPSTAT_OFFSET)); + + imx9_putreg(priv, IMX9_USBDEV_ENDPTCOMPLETE_OFFSET, + imx9_getreg(priv, IMX9_USBDEV_ENDPTCOMPLETE_OFFSET)); + + /* Wait for all prime operations to have completed and then flush all + * DTDs + */ + + while (imx9_getreg(priv, IMX9_USBDEV_ENDPTPRIME_OFFSET) != 0); + + imx9_putreg(priv, IMX9_USBDEV_ENDPTFLUSH_OFFSET, IMX9_ENDPTMASK_ALL); + + while (imx9_getreg(priv, IMX9_USBDEV_ENDPTFLUSH_OFFSET)); + + /* Reset endpoints */ + + for (epphy = 0; epphy < IMX9_NPHYSENDPOINTS; epphy++) + { + struct imx9_ep_s *privep = &priv->eplist[epphy]; + + imx9_cancelrequests(privep, -ESHUTDOWN); + + /* Reset endpoint status */ + + privep->stalled = false; + } + + /* Tell the class driver that we are disconnected. The class + * driver should then accept any new configurations. + */ + + if (priv->driver) + { + CLASS_DISCONNECT(priv->driver, &priv->usbdev); + } + + /* Set the interrupt Threshold control interval to 0 */ + + imx9_modifyreg(priv, IMX9_USBDEV_USBCMD_OFFSET, USBDEV_USBCMD_ITC_MASK, + USBDEV_USBCMD_ITCIMME); + + /* Zero out the Endpoint queue heads */ + + memset ((void *)priv->qh, 0, sizeof(priv->qh)); + memset ((void *)priv->td, 0, sizeof(priv->td)); + + up_clean_dcache((uintptr_t)priv->qh, + (uintptr_t)priv->qh + sizeof(priv->qh)); + up_clean_dcache((uintptr_t)priv->td, + (uintptr_t)priv->td + sizeof(priv->td)); + + /* Set USB address to 0 */ + + imx9_set_address(priv, 0); + + /* Initialise the Enpoint List Address */ + + imx9_putreg(priv, IMX9_USBDEV_ENDPOINTLIST_OFFSET, + (uint32_t)(uintptr_t)priv->qh); + + /* EndPoint 0 initialization */ + + imx9_ep0configure(priv); + + /* Enable Device interrupts */ + + imx9_putreg(priv, IMX9_USBDEV_USBINTR_OFFSET, + USB_FRAME_INT | USB_ERROR_INT | USBDEV_USBINTR_NAKE | + USBDEV_USBINTR_SLE | USBDEV_USBINTR_URE | USBDEV_USBINTR_PCE | + USBDEV_USBINTR_UE); +} + +/**************************************************************************** + * Name: imx9_setstate + * + * Description: + * Sets the EP0 state and manages the NAK interrupts + * + ****************************************************************************/ + +static inline void imx9_ep0state(struct imx9_usb_s *priv, + uint16_t state) +{ + priv->ep0.state = state; + + switch (state) + { + case EP0STATE_WAIT_NAK_IN: + imx9_putreg(priv, IMX9_USBDEV_ENDPTNAKEN_OFFSET, + IMX9_ENDPTMASK(IMX9_EP0_IN)); + break; + + case EP0STATE_WAIT_NAK_OUT: + imx9_putreg(priv, IMX9_USBDEV_ENDPTNAKEN_OFFSET, + IMX9_ENDPTMASK(IMX9_EP0_OUT)); + break; + + default: + imx9_putreg(priv, IMX9_USBDEV_ENDPTNAKEN_OFFSET, 0); + break; + } +} + +/**************************************************************************** + * Name: imx9_ep0setup + * + * Description: + * USB Ctrl EP Setup Event. This is logically part of the USB interrupt + * handler. This event occurs when a setup packet is receive on EP0 OUT. + * + ****************************************************************************/ + +static inline void imx9_ep0setup(struct imx9_usb_s *priv) +{ + struct imx9_ep_s *privep; + struct usb_ctrlreq_s *ctrl; + uint16_t value; + uint16_t index; + uint16_t len; + + ctrl = &priv->ep0.ctrl; + + /* Terminate any pending requests - since all DTDs will have been retired + * because of the setup packet. + */ + + imx9_cancelrequests(&priv->eplist[IMX9_EP0_OUT], -EPROTO); + imx9_cancelrequests(&priv->eplist[IMX9_EP0_IN], -EPROTO); + + /* Assume NOT stalled */ + + priv->eplist[IMX9_EP0_OUT].stalled = false; + priv->eplist[IMX9_EP0_IN].stalled = false; + priv->stalled = false; + + /* Read EP0 setup data */ + + imx9_readsetup(priv, IMX9_EP0_OUT, ctrl); + + /* And extract the little-endian 16-bit values to host order */ + + value = GETUINT16(ctrl->value); + index = GETUINT16(ctrl->index); + len = GETUINT16(ctrl->len); + + priv->ep0.buf_len = len; + + uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n", + ctrl->type, ctrl->req, value, index, len); + + /* Starting a control request - update state */ + + if (ctrl->type & USB_REQ_DIR_IN) + { + imx9_ep0state(priv, EP0STATE_SETUP_IN); + } + else + { + imx9_ep0state(priv, EP0STATE_SETUP_OUT); + + if (len > 0) + { + imx9_ep0state(priv, EP0STATE_SHORTREAD); + imx9_ep0xfer(priv, IMX9_EP0_OUT, priv->ep0.buf, len); + return; + } + } + + /* Dispatch any non-standard requests */ + + if ((ctrl->type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) + { + imx9_dispatchrequest(priv, ctrl); + } + else + { + /* Handle standard request. Pick off the things of interest to the USB + * device controller driver; pass what is left to the class driver. + */ + + switch (ctrl->req) + { + case USB_REQ_GETSTATUS: + { + /* type: device-to-host; recipient = device, interface, endpoint + * value: 0 + * index: zero interface endpoint + * len: 2; data = status + */ + + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_GETSTATUS), 0); + if (!priv->paddrset || len != 2 || + (ctrl->type & USB_REQ_DIR_IN) == 0 || value != 0) + { + priv->stalled = true; + } + else + { + switch (ctrl->type & USB_REQ_RECIPIENT_MASK) + { + case USB_REQ_RECIPIENT_ENDPOINT: + { + usbtrace( + TRACE_INTDECODE(IMX9_TRACEINTID_EPGETSTATUS), 0); + privep = imx9_epfindbyaddr(priv, index); + if (!privep) + { + usbtrace( + TRACE_DEVERROR(IMX9_TRACEERR_BADEPGETSTATUS), + 0); + priv->stalled = true; + } + else + { + if (privep->stalled) + { + priv->ep0.buf[0] = 1; /* Stalled */ + } + else + { + priv->ep0.buf[0] = 0; /* Not stalled */ + } + + priv->ep0.buf[1] = 0; + + imx9_ep0xfer(priv, IMX9_EP0_IN, priv->ep0.buf, 2); + imx9_ep0state(priv, EP0STATE_SHORTWRITE); + } + } + break; + + case USB_REQ_RECIPIENT_DEVICE: + { + if (index == 0) + { + usbtrace( + TRACE_INTDECODE(IMX9_TRACEINTID_DEVGETSTATUS), + 0); + + /* Features: Remote Wakeup=YES; selfpowered=? */ + + priv->ep0.buf[0] = + (priv->selfpowered << USB_FEATURE_SELFPOWERED) | + (1 << USB_FEATURE_REMOTEWAKEUP); + priv->ep0.buf[1] = 0; + + imx9_ep0xfer(priv, IMX9_EP0_IN, priv->ep0.buf, 2); + imx9_ep0state(priv, EP0STATE_SHORTWRITE); + } + else + { + usbtrace( + TRACE_DEVERROR(IMX9_TRACEERR_BADDEVGETSTATUS), + 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_RECIPIENT_INTERFACE: + { + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_IFGETSTATUS), + 0); + priv->ep0.buf[0] = 0; + priv->ep0.buf[1] = 0; + + imx9_ep0xfer(priv, IMX9_EP0_IN, priv->ep0.buf, 2); + imx9_ep0state(priv, EP0STATE_SHORTWRITE); + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_BADGETSTATUS), + 0); + priv->stalled = true; + } + break; + } + } + } + break; + + case USB_REQ_CLEARFEATURE: + { + /* type: host-to-device; recipient = device, interface or endpoint + * value: feature selector + * index: zero interface endpoint; + * len: zero, data = none + */ + + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_CLEARFEATURE), 0); + if ((ctrl->type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_ENDPOINT) + { + imx9_dispatchrequest(priv, ctrl); + } + else if (priv->paddrset != 0 && + value == USB_FEATURE_ENDPOINTHALT && + len == 0 && (privep = imx9_epfindbyaddr(priv, index)) != NULL) + { + imx9_epstall(&privep->ep, true); + imx9_ep0state(priv, EP0STATE_WAIT_NAK_IN); + } + else + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_BADCLEARFEATURE), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_SETFEATURE: + { + /* type: host-to-device; recipient = device, interface, endpoint + * value: feature selector + * index: zero interface endpoint; + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_SETFEATURE), 0); + if (((ctrl->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) && value == USB_FEATURE_TESTMODE) + { + uinfo("test mode: %d\n", index); + } + else if ((ctrl->type & USB_REQ_RECIPIENT_MASK) != + USB_REQ_RECIPIENT_ENDPOINT) + { + imx9_dispatchrequest(priv, ctrl); + } + else if (priv->paddrset != 0 && + value == USB_FEATURE_ENDPOINTHALT && + len == 0 && (privep = imx9_epfindbyaddr(priv, index)) != NULL) + { + imx9_epstall(&privep->ep, false); + imx9_ep0state(priv, EP0STATE_WAIT_NAK_IN); + } + else + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_BADSETFEATURE), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_SETADDRESS: + { + /* type: host-to-device; recipient = device + * value: device address + * index: 0 + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_EP0SETUPSETADDRESS), + value); + if (((ctrl->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) && + index == 0 && len == 0 && value < 128) + { + /* Save the address. We cannot actually change to the next + * address until the completion of the status phase. + */ + + priv->paddr = ctrl->value[0]; + priv->paddrset = false; + imx9_ep0state(priv, EP0STATE_WAIT_NAK_IN); + } + else + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_BADSETADDRESS), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_GETDESCRIPTOR: + /* type: device-to-host; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + case USB_REQ_SETDESCRIPTOR: + /* type: host-to-device; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + { + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_GETSETDESC), 0); + if ((ctrl->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) + { + imx9_dispatchrequest(priv, ctrl); + } + else + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_BADGETSETDESC), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_GETCONFIGURATION: + /* type: device-to-host; recipient = device + * value: 0; + * index: 0; + * len: 1; data = configuration value + */ + + { + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_GETCONFIG), 0); + if (priv->paddrset && + ((ctrl->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) && + value == 0 && index == 0 && len == 1) + { + imx9_dispatchrequest(priv, ctrl); + } + else + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_BADGETCONFIG), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_SETCONFIGURATION: + /* type: host-to-device; recipient = device + * value: configuration value + * index: 0; + * len: 0; data = none + */ + + { + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_SETCONFIG), 0); + if (((ctrl->type & USB_REQ_RECIPIENT_MASK) == + USB_REQ_RECIPIENT_DEVICE) && index == 0 && len == 0) + { + imx9_dispatchrequest(priv, ctrl); + } + else + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_BADSETCONFIG), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_GETINTERFACE: + /* type: device-to-host; recipient = interface + * value: 0 + * index: interface; + * len: 1; data = alt interface + */ + + case USB_REQ_SETINTERFACE: + /* type: host-to-device; recipient = interface + * value: alternate setting + * index: interface; + * len: 0; data = none + */ + + { + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_GETSETIF), 0); + imx9_dispatchrequest(priv, ctrl); + } + break; + + case USB_REQ_SYNCHFRAME: + /* type: device-to-host; recipient = endpoint + * value: 0 + * index: endpoint; + * len: 2; data = frame number + */ + + { + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_SYNCHFRAME), 0); + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_INVALIDCTRLREQ), 0); + priv->stalled = true; + } + break; + } + } + + if (priv->stalled) + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_EP0SETUPSTALLED), + priv->ep0.state); + imx9_epstall(&priv->eplist[IMX9_EP0_IN].ep, false); + imx9_epstall(&priv->eplist[IMX9_EP0_OUT].ep, false); + } +} + +/**************************************************************************** + * Name: imx9_ep0complete + * + * Description: + * Transfer complete handler for Endpoint 0 + * + ****************************************************************************/ + +static void imx9_ep0complete(struct imx9_usb_s *priv, uint8_t epphy) +{ + struct imx9_ep_s *privep = &priv->eplist[epphy]; + + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_EP0COMPLETE), + (uint16_t)priv->ep0.state); + + switch (priv->ep0.state) + { + case EP0STATE_DATA_IN: + if (imx9_rqempty(privep)) + { + return; + } + + if (imx9_epcomplete(priv, epphy)) + { + imx9_ep0state(priv, EP0STATE_WAIT_NAK_OUT); + } + break; + + case EP0STATE_DATA_OUT: + if (imx9_rqempty(privep)) + { + return; + } + + if (imx9_epcomplete(priv, epphy)) + { + imx9_ep0state(priv, EP0STATE_WAIT_NAK_IN); + } + break; + + case EP0STATE_SHORTREAD: + imx9_dispatchrequest(priv, &priv->ep0.ctrl); + imx9_ep0state(priv, EP0STATE_WAIT_NAK_IN); + break; + + case EP0STATE_SHORTWRITE: + imx9_ep0state(priv, EP0STATE_WAIT_NAK_OUT); + break; + + case EP0STATE_WAIT_STATUS_IN: + imx9_ep0state(priv, EP0STATE_IDLE); + + /* If we've received a SETADDRESS packet, then we set the address + * now that the status phase has completed + */ + + if (!priv->paddrset && priv->paddr != 0) + { + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_EP0INSETADDRESS), + (uint16_t)priv->paddr); + imx9_set_address(priv, priv->paddr); + } + + break; + + case EP0STATE_WAIT_STATUS_OUT: + imx9_ep0state(priv, EP0STATE_IDLE); + break; + + default: +#ifdef CONFIG_DEBUG_FEATURES + DEBUGASSERT(priv->ep0.state != EP0STATE_DATA_IN && + priv->ep0.state != EP0STATE_DATA_OUT && + priv->ep0.state != EP0STATE_SHORTWRITE && + priv->ep0.state != EP0STATE_WAIT_STATUS_IN && + priv->ep0.state != EP0STATE_WAIT_STATUS_OUT); +#endif + priv->stalled = true; + break; + } + + if (priv->stalled) + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_EP0SETUPSTALLED), + priv->ep0.state); + imx9_epstall(&priv->eplist[IMX9_EP0_IN].ep, false); + imx9_epstall(&priv->eplist[IMX9_EP0_OUT].ep, false); + } +} + +/**************************************************************************** + * Name: imx9_ep0nak + * + * Description: + * Handle a NAK interrupt on EP0 + * + ****************************************************************************/ + +static void imx9_ep0nak(struct imx9_usb_s *priv, uint8_t epphy) +{ + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_EP0NAK), + (uint16_t)priv->ep0.state); + + switch (priv->ep0.state) + { + case EP0STATE_WAIT_NAK_IN: + imx9_ep0xfer(priv, IMX9_EP0_IN, NULL, 0); + imx9_ep0state(priv, EP0STATE_WAIT_STATUS_IN); + break; + + case EP0STATE_WAIT_NAK_OUT: + imx9_ep0xfer(priv, IMX9_EP0_OUT, NULL, 0); + imx9_ep0state(priv, EP0STATE_WAIT_STATUS_OUT); + break; + + default: +#ifdef CONFIG_DEBUG_FEATURES + DEBUGASSERT(priv->ep0.state != EP0STATE_WAIT_NAK_IN && + priv->ep0.state != EP0STATE_WAIT_NAK_OUT); +#endif + priv->stalled = true; + break; + } + + if (priv->stalled) + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_EP0SETUPSTALLED), + priv->ep0.state); + imx9_epstall(&priv->eplist[IMX9_EP0_IN].ep, false); + imx9_epstall(&priv->eplist[IMX9_EP0_OUT].ep, false); + } +} + +/**************************************************************************** + * Name: imx9_epcomplete + * + * Description: + * Transfer complete handler for Endpoints other than 0 + * returns whether the request at the head has completed + * + ****************************************************************************/ + +bool imx9_epcomplete(struct imx9_usb_s *priv, uint8_t epphy) +{ + struct imx9_ep_s *privep = &priv->eplist[epphy]; + struct imx9_req_s *privreq = privep->head; + struct imx9_dtd_s *dtd = &priv->td[epphy]; + + if (privreq == NULL) /* This shouldn't really happen */ + { + if (IMX9_EPPHYOUT(privep->epphy)) + { + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_EPINQEMPTY), 0); + } + else + { + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_EPOUTQEMPTY), 0); + } + + return true; + } + + /* Make sure we have updated data after the DMA transfer. */ + + up_invalidate_dcache((uintptr_t)dtd, + (uintptr_t)dtd + sizeof(struct imx9_dtd_s)); + up_invalidate_dcache((uintptr_t)dtd->buffer0, + (uintptr_t)dtd->buffer0 + dtd->xfer_len); + + int xfrd = dtd->xfer_len - (dtd->config >> 16); + + privreq->req.xfrd += xfrd; + + bool complete = true; + if (IMX9_EPPHYOUT(privep->epphy)) + { + /* read(OUT) completes when request filled, or a short transfer is + * received + */ + + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_EPIN), complete); + } + else + { + /* write(IN) completes when request finished, unless we need to + * terminate with a ZLP + */ + + bool need_zlp = (xfrd == privep->ep.maxpacket) && + ((privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0); + + complete = (privreq->req.xfrd >= privreq->req.len && !need_zlp); + + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_EPOUT), complete); + } + + /* If the transfer is complete, then dequeue and progress any further + * queued requests + */ + + if (complete) + { + privreq = imx9_rqdequeue(privep); + } + + if (!imx9_rqempty(privep)) + { + imx9_progressep(privep); + } + + /* Now it's safe to call the completion callback as it may well submit a + * new request + */ + + if (complete) + { + usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); + imx9_reqcomplete(privep, privreq, OK); + } + + return complete; +} + +/**************************************************************************** + * Name: imx9_usbinterrupt + * + * Description: + * USB interrupt handler + * + ****************************************************************************/ + +static int imx9_usbinterrupt(int irq, void *context, void *arg) +{ + struct imx9_usb_s *priv = (struct imx9_usb_s *)arg; + uint32_t disr; + uint32_t portsc1; + uint32_t n; + + usbtrace(TRACE_INTENTRY(IMX9_TRACEINTID_USB), 0); + + /* Read the interrupts and then clear them */ + + disr = imx9_getreg(priv, IMX9_USBDEV_USBSTS_OFFSET); + imx9_putreg(priv, IMX9_USBDEV_USBSTS_OFFSET, disr); + + if (disr & USBDEV_USBSTS_URI) + { + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_DEVRESET), 0); + + imx9_usbreset(priv); + + usbtrace(TRACE_INTEXIT(IMX9_TRACEINTID_USB), 0); + return OK; + } + + /* When the device controller enters a suspend state from an active state, + * the SLI bit will be set to a one. + */ + + if (!priv->suspended && (disr & USBDEV_USBSTS_SLI) != 0) + { + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_SUSPENDED), 0); + + /* Inform the Class driver of the suspend event */ + + priv->suspended = 1; + if (priv->driver) + { + CLASS_SUSPEND(priv->driver, &priv->usbdev); + } + + /* TODO: Perform power management operations here. */ + } + + /* The device controller clears the SLI bit upon exiting from a suspend + * state. This bit can also be cleared by software writing a one to it. + */ + + else if (priv->suspended && (disr & USBDEV_USBSTS_SLI) == 0) + { + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_RESUMED), 0); + + /* Inform the Class driver of the resume event */ + + priv->suspended = 0; + if (priv->driver) + { + CLASS_RESUME(priv->driver, &priv->usbdev); + } + + /* TODO: Perform power management operations here. */ + } + + if (disr & USBDEV_USBSTS_PCI) + { + portsc1 = imx9_getreg(priv, IMX9_USBDEV_PORTSC1_OFFSET); + + if (portsc1 & USBDEV_PRTSC1_HSP) + priv->usbdev.speed = USB_SPEED_HIGH; + else + priv->usbdev.speed = USB_SPEED_FULL; + + if (portsc1 & USBDEV_PRTSC1_FPR) + { + /* FIXME: this occurs because of a J-to-K transition detected + * while the port is in SUSPEND state - presumambly this + * is where the host is resuming the device? + * + * - but do we need to "ack" the interrupt + */ + } + } + +#ifdef CONFIG_IMX9_USB_FRAME_INTERRUPT + if (disr & USBDEV_USBSTS_SRI) + { + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_FRAME), 0); + + uint32_t frindex = imx9_getreg(IMX9_USB_FRINDEX); + uint16_t frame_num = + (frindex & USBDEV_FRINDEX_LFN_MASK) >> USBDEV_FRINDEX_LFN_SHIFT; + + priv->sof = frame_num; + } +#endif + + if (disr & USBDEV_USBSTS_UEI) + { + /* FIXME: these occur when a transfer results in an error condition + * it is set alongside USBINT if the DTD also had its IOC + * bit set. + */ + } + + if (disr & USBDEV_USBSTS_UI) + { + /* Handle completion interrupts */ + + uint32_t mask = imx9_getreg(priv, IMX9_USBDEV_ENDPTCOMPLETE_OFFSET); + + if (mask) + { + /* Clear any NAK interrupt and completion interrupts */ + + imx9_putreg(priv, IMX9_USBDEV_ENDPTNAK_OFFSET, mask); + imx9_putreg(priv, IMX9_USBDEV_ENDPTCOMPLETE_OFFSET, mask); + + if (mask & IMX9_ENDPTMASK(0)) + { + imx9_ep0complete(priv, 0); + } + + if (mask & IMX9_ENDPTMASK(1)) + { + imx9_ep0complete(priv, 1); + } + + for (n = 1; n < IMX9_NLOGENDPOINTS; n++) + { + if (mask & IMX9_ENDPTMASK((n << 1))) + { + imx9_epcomplete(priv, (n << 1)); + } + + if (mask & IMX9_ENDPTMASK((n << 1)+1)) + { + imx9_epcomplete(priv, (n << 1)+1); + } + } + } + + /* Handle setup interrupts */ + + uint32_t setupstat = imx9_getreg(priv, + IMX9_USBDEV_ENDPTSETUPSTAT_OFFSET); + if (setupstat) + { + /* Clear the endpoint complete CTRL OUT and IN when a Setup is + * received + */ + + imx9_putreg(priv, IMX9_USBDEV_ENDPTCOMPLETE_OFFSET, + IMX9_ENDPTMASK(IMX9_EP0_IN) | + IMX9_ENDPTMASK(IMX9_EP0_OUT)); + + if (setupstat & IMX9_ENDPTMASK(IMX9_EP0_OUT)) + { + usbtrace(TRACE_INTDECODE(IMX9_TRACEINTID_EP0SETUP), + setupstat); + imx9_ep0setup(priv); + } + } + } + + if (disr & USBDEV_USBSTS_NAKI) + { + uint32_t pending = imx9_getreg(priv, IMX9_USBDEV_ENDPTNAK_OFFSET) & + imx9_getreg(priv, IMX9_USBDEV_ENDPTNAKEN_OFFSET); + + if (pending) + { + /* We shouldn't see NAK interrupts except on Endpoint 0 */ + + if (pending & IMX9_ENDPTMASK(0)) + { + imx9_ep0nak(priv, 0); + } + + if (pending & IMX9_ENDPTMASK(1)) + { + imx9_ep0nak(priv, 1); + } + } + + /* Clear the interrupts */ + + imx9_putreg(priv, IMX9_USBDEV_ENDPTNAK_OFFSET, pending); + } + + usbtrace(TRACE_INTEXIT(IMX9_TRACEINTID_USB), 0); + return OK; +} + +/**************************************************************************** + * Endpoint operations + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_epconfigure + * + * Description: + * Configure endpoint, making it usable + * + * Input Parameters: + * ep - the struct usbdev_ep_s instance obtained from allocep() + * desc - A struct usb_epdesc_s instance describing the endpoint + * last - true if this is the last endpoint to be configured. Some + * hardware needs to take special action when all of the endpoints + * have been configured. + * + ****************************************************************************/ + +static int imx9_epconfigure(struct usbdev_ep_s *ep, + const struct usb_epdesc_s *desc, + bool last) +{ + struct imx9_ep_s *privep = (struct imx9_ep_s *)ep; + struct imx9_usb_s *priv = privep->dev; + struct imx9_dqh_s *dqh = &priv->qh[privep->epphy]; + + usbtrace(TRACE_EPCONFIGURE, privep->epphy); + DEBUGASSERT(desc->addr == ep->eplog); + + /* Initialise EP capabilities */ + + uint16_t maxsize = GETUINT16(desc->mxpacketsize); + if ((desc->attr & USB_EP_ATTR_XFERTYPE_MASK) == USB_EP_ATTR_XFER_ISOC) + { + dqh->capability = (DQH_CAPABILITY_MAX_PACKET(maxsize) | + DQH_CAPABILITY_IOS | + DQH_CAPABILITY_ZLT); + } + else + { + dqh->capability = (DQH_CAPABILITY_MAX_PACKET(maxsize) | + DQH_CAPABILITY_ZLT); + } + + up_clean_dcache((uintptr_t)dqh, + (uintptr_t)dqh + sizeof(struct imx9_dqh_s)); + + /* Setup Endpoint Control Register */ + + if (IMX9_EPPHYIN(privep->epphy)) + { + /* Reset the data toggles */ + + uint32_t cfg = USBDEV_ENDPTCTRL_TXR; + + /* Set the endpoint type */ + + switch (desc->attr & USB_EP_ATTR_XFERTYPE_MASK) + { + case USB_EP_ATTR_XFER_CONTROL: + cfg |= USBDEV_ENDPTCTRL_TXT_CTRL; break; + case USB_EP_ATTR_XFER_ISOC: + cfg |= USBDEV_ENDPTCTRL_TXT_ISOC; break; + case USB_EP_ATTR_XFER_BULK: + cfg |= USBDEV_ENDPTCTRL_TXT_BULK; break; + case USB_EP_ATTR_XFER_INT: + cfg |= USBDEV_ENDPTCTRL_TXT_INTR; break; + } + + imx9_modifyreg(priv, IMX9_USBDEV_ENDPTCTRL_OFFSET(privep->epphy >> 1), + 0xffff0000, cfg); + } + else + { + /* Reset the data toggles */ + + uint32_t cfg = USBDEV_ENDPTCTRL_RXR; + + /* Set the endpoint type */ + + switch (desc->attr & USB_EP_ATTR_XFERTYPE_MASK) + { + case USB_EP_ATTR_XFER_CONTROL: + cfg |= USBDEV_ENDPTCTRL_RXT_CTRL; break; + case USB_EP_ATTR_XFER_ISOC: + cfg |= USBDEV_ENDPTCTRL_RXT_ISOC; break; + case USB_EP_ATTR_XFER_BULK: + cfg |= USBDEV_ENDPTCTRL_RXT_BULK; break; + case USB_EP_ATTR_XFER_INT: + cfg |= USBDEV_ENDPTCTRL_RXT_INTR; break; + } + + imx9_modifyreg(priv, IMX9_USBDEV_ENDPTCTRL_OFFSET(privep->epphy >> 1), + 0xffff0000, cfg); + } + + /* Reset endpoint status */ + + privep->stalled = false; + + /* Enable the endpoint */ + + if (IMX9_EPPHYIN(privep->epphy)) + { + imx9_modifyreg(priv, IMX9_USBDEV_ENDPTCTRL_OFFSET(privep->epphy >> 1), + 0, USBDEV_ENDPTCTRL_TXE); + } + else + { + imx9_modifyreg(priv, IMX9_USBDEV_ENDPTCTRL_OFFSET(privep->epphy >> 1), + 0, USBDEV_ENDPTCTRL_RXE); + } + + return OK; +} + +/**************************************************************************** + * Name: imx9_epdisable + * + * Description: + * The endpoint will no longer be used + * + ****************************************************************************/ + +static int imx9_epdisable(struct usbdev_ep_s *ep) +{ + struct imx9_ep_s *privep = (struct imx9_ep_s *)ep; + struct imx9_usb_s *priv = privep->dev; + irqstate_t flags; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep) + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPDISABLE, privep->epphy); + + flags = enter_critical_section(); + + /* Disable Endpoint */ + + if (IMX9_EPPHYIN(privep->epphy)) + { + imx9_modifyreg(priv, IMX9_USBDEV_ENDPTCTRL_OFFSET(privep->epphy >> 1), + USBDEV_ENDPTCTRL_TXE, 0); + } + else + { + imx9_modifyreg(priv, IMX9_USBDEV_ENDPTCTRL_OFFSET(privep->epphy >> 1), + USBDEV_ENDPTCTRL_RXE, 0); + } + + privep->stalled = true; + + /* Cancel any ongoing activity */ + + imx9_cancelrequests(privep, -ESHUTDOWN); + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: imx9_epallocreq + * + * Description: + * Allocate an I/O request + * + ****************************************************************************/ + +static struct usbdev_req_s *imx9_epallocreq(struct usbdev_ep_s *ep) +{ + struct imx9_req_s *privreq; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep) + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_INVALIDPARMS), 0); + return NULL; + } +#endif + + usbtrace(TRACE_EPALLOCREQ, ((struct imx9_ep_s *)ep)->epphy); + + privreq = kmm_malloc(sizeof(struct imx9_req_s)); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_ALLOCFAIL), 0); + return NULL; + } + + memset(privreq, 0, sizeof(struct imx9_req_s)); + return &privreq->req; +} + +/**************************************************************************** + * Name: imx9_epfreereq + * + * Description: + * Free an I/O request + * + ****************************************************************************/ + +static void imx9_epfreereq(struct usbdev_ep_s *ep, + struct usbdev_req_s *req) +{ + struct imx9_req_s *privreq = (struct imx9_req_s *)req; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_INVALIDPARMS), 0); + return; + } +#endif + + usbtrace(TRACE_EPFREEREQ, ((struct imx9_ep_s *)ep)->epphy); + kmm_free(privreq); +} + +/**************************************************************************** + * Name: imx9_epallocbuffer + * + * Description: + * Allocate an I/O buffer + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_DMA +static void *imx9_epallocbuffer(struct usbdev_ep_s *ep, uint16_t bytes) +{ + /* The USB peripheral DMA is very forgiving, as the dTD allows the buffer + * to start at any address. Hence, no need for alignment. + */ + + struct imx9_ep_s *privep = (struct imx9_ep_s *)ep; + UNUSED(privep); + + usbtrace(TRACE_EPALLOCBUFFER, privep->epphy); +#ifdef CONFIG_USBDEV_DMAMEMORY + return usbdev_dma_alloc(bytes); +#else + return cache_aligned_alloc(bytes); +#endif +} +#endif + +/**************************************************************************** + * Name: imx9_epfreebuffer + * + * Description: + * Free an I/O buffer + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_DMA +static void imx9_epfreebuffer(struct usbdev_ep_s *ep, void *buf) +{ + struct imx9_ep_s *privep = (struct imx9_ep_s *)ep; + UNUSED(privep); + + usbtrace(TRACE_EPFREEBUFFER, privep->epphy); + +#ifdef CONFIG_USBDEV_DMAMEMORY + usbdev_dma_free(buf); +#else + kmm_free(buf); +#endif +} +#endif + +/**************************************************************************** + * Name: imx9_epsubmit + * + * Description: + * Submit an I/O request to the endpoint + * + ****************************************************************************/ + +static int imx9_epsubmit(struct usbdev_ep_s *ep, + struct usbdev_req_s *req) +{ + struct imx9_req_s *privreq = (struct imx9_req_s *)req; + struct imx9_ep_s *privep = (struct imx9_ep_s *)ep; + struct imx9_usb_s *priv; + irqstate_t flags; + int ret = OK; + +#ifdef CONFIG_DEBUG_FEATURES + if (!req || !req->callback || !req->buf || !ep) + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_INVALIDPARMS), 0); + uinfo("req=%p callback=%p buf=%p ep=%p\n", req, + req->callback, req->buf, ep); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPSUBMIT, privep->epphy); + priv = privep->dev; + + if (!priv->driver || priv->usbdev.speed == USB_SPEED_UNKNOWN) + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_NOTCONFIGURED), + priv->usbdev.speed); + return -ESHUTDOWN; + } + + /* Handle the request from the class driver */ + + req->result = -EINPROGRESS; + req->xfrd = 0; + + /* Disable Interrupts */ + + flags = enter_critical_section(); + + /* If we are stalled, then drop all requests on the floor */ + + if (privep->stalled) + { + ret = -EBUSY; + } + else + { + /* Add the new request to the request queue for the endpoint */ + + if (IMX9_EPPHYIN(privep->epphy)) + { + usbtrace(TRACE_INREQQUEUED(privep->epphy), privreq->req.len); + } + else + { + usbtrace(TRACE_OUTREQQUEUED(privep->epphy), privreq->req.len); + } + + if (imx9_rqenqueue(privep, privreq)) + { + imx9_progressep(privep); + } + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: imx9_epcancel + * + * Description: + * Cancel an I/O request previously sent to an endpoint + * + ****************************************************************************/ + +static int imx9_epcancel(struct usbdev_ep_s *ep, + struct usbdev_req_s *req) +{ + struct imx9_ep_s *privep = (struct imx9_ep_s *)ep; + irqstate_t flags; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPCANCEL, privep->epphy); + + flags = enter_critical_section(); + + /* FIXME: if the request is the first, then we need to flush the EP + * otherwise just remove it from the list + * + * but ... all other implementations cancel all requests ... + */ + + imx9_cancelrequests(privep, -ESHUTDOWN); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: imx9_epstall + * + * Description: + * Stall or resume and endpoint + * + ****************************************************************************/ + +static int imx9_epstall(struct usbdev_ep_s *ep, bool resume) +{ + struct imx9_ep_s *privep = (struct imx9_ep_s *)ep; + struct imx9_usb_s *priv = privep->dev; + irqstate_t flags; + + /* STALL or RESUME the endpoint */ + + flags = enter_critical_section(); + usbtrace(resume ? TRACE_EPRESUME : TRACE_EPSTALL, privep->epphy); + + uint32_t offs = IMX9_USBDEV_ENDPTCTRL_OFFSET(privep->epphy >> 1); + uint32_t ctrl_xs = IMX9_EPPHYIN(privep->epphy) ? + USBDEV_ENDPTCTRL_TXS : USBDEV_ENDPTCTRL_RXS; + uint32_t ctrl_xr = IMX9_EPPHYIN(privep->epphy) ? + USBDEV_ENDPTCTRL_TXR : USBDEV_ENDPTCTRL_RXR; + + if (resume) + { + privep->stalled = false; + + /* Clear stall and reset the data toggle */ + + imx9_modifyreg(priv, offs, ctrl_xs | ctrl_xr, ctrl_xr); + } + else + { + privep->stalled = true; + + imx9_modifyreg(priv, offs, 0, ctrl_xs); + } + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Device operations + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_allocep + * + * Description: + * Allocate an endpoint matching the parameters. + * + * Input Parameters: + * eplog - 7-bit logical endpoint number (direction bit ignored). Zero + * means that any endpoint matching the other requirements will + * suffice. The assigned endpoint can be found in the eplog field. + * in - true: IN (device-to-host) endpoint requested + * eptype - Endpoint type. One of {USB_EP_ATTR_XFER_ISOC, + * USB_EP_ATTR_XFER_BULK, USB_EP_ATTR_XFER_INT} + * + ****************************************************************************/ + +static struct usbdev_ep_s *imx9_allocep(struct usbdev_s *dev, + uint8_t eplog, + bool in, uint8_t eptype) +{ + struct imx9_usb_s *priv = (struct imx9_usb_s *)dev; + uint32_t epset = IMX9_EPALLSET & ~IMX9_EPCTRLSET; + irqstate_t flags; + int epndx = 0; + + usbtrace(TRACE_DEVALLOCEP, (uint16_t)eplog); + + /* Ignore any direction bits in the logical address */ + + eplog = USB_EPNO(eplog); + + /* A logical address of 0 means that any endpoint will do */ + + if (eplog > 0) + { + /* Otherwise, we will return the endpoint structure only for the + * requested 'logical' endpoint. All of the other checks will still be + * performed. + * + * First, verify that the logical endpoint is in the range supported by + * by the hardware. + */ + + if (eplog >= IMX9_NLOGENDPOINTS) + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_BADEPNO), (uint16_t)eplog); + return NULL; + } + + /* Convert the logical address to a physical OUT endpoint address and + * remove all of the candidate endpoints from the bitset except for the + * the IN/OUT pair for this logical address. + */ + + epset &= 3 << (eplog << 1); + } + + /* Get the subset matching the requested direction */ + + if (in) + { + epset &= IMX9_EPINSET; + } + else + { + epset &= IMX9_EPOUTSET; + } + + /* Get the subset matching the requested type */ + + switch (eptype) + { + case USB_EP_ATTR_XFER_INT: /* Interrupt endpoint */ + epset &= IMX9_EPINTRSET; + break; + + case USB_EP_ATTR_XFER_BULK: /* Bulk endpoint */ + epset &= IMX9_EPBULKSET; + break; + + case USB_EP_ATTR_XFER_ISOC: /* Isochronous endpoint */ + epset &= IMX9_EPISOCSET; + break; + + case USB_EP_ATTR_XFER_CONTROL: /* Control endpoint -- not a valid choice */ + default: + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_BADEPTYPE), (uint16_t)eptype); + return NULL; + } + + /* Is the resulting endpoint supported by the IMX9? */ + + if (epset) + { + /* Yes.. now see if any of the request endpoints are available */ + + flags = enter_critical_section(); + epset &= priv->epavail; + if (epset) + { + /* Select the lowest bit in the set of matching, available + * endpoints + */ + + for (epndx = 2; epndx < IMX9_NPHYSENDPOINTS; epndx++) + { + uint32_t bit = 1 << epndx; + if ((epset & bit) != 0) + { + /* Mark endpoint no longer available */ + + priv->epavail &= ~bit; + leave_critical_section(flags); + + /* And return the pointer to the standard endpoint + * structure + */ + + return &priv->eplist[epndx].ep; + } + } + + /* Shouldn't get here */ + } + + leave_critical_section(flags); + } + + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_NOEP), (uint16_t)eplog); + return NULL; +} + +/**************************************************************************** + * Name: imx9_freeep + * + * Description: + * Free the previously allocated endpoint + * + ****************************************************************************/ + +static void imx9_freeep(struct usbdev_s *dev, + struct usbdev_ep_s *ep) +{ + struct imx9_usb_s *priv = (struct imx9_usb_s *)dev; + struct imx9_ep_s *privep = (struct imx9_ep_s *)ep; + irqstate_t flags; + + usbtrace(TRACE_DEVFREEEP, (uint16_t)privep->epphy); + + if (priv && privep) + { + /* Mark the endpoint as available */ + + flags = enter_critical_section(); + priv->epavail |= (1 << privep->epphy); + leave_critical_section(flags); + } +} + +/**************************************************************************** + * Name: imx9_getframe + * + * Description: + * Returns the current frame number + * + ****************************************************************************/ + +static int imx9_getframe(struct usbdev_s *dev) +{ + struct imx9_usb_s *priv = (struct imx9_usb_s *)dev; + +#ifdef CONFIG_IMX9_USB_FRAME_INTERRUPT + /* Return last valid value of SOF read by the interrupt handler */ + + usbtrace(TRACE_DEVGETFRAME, (uint16_t)priv->sof); + return priv->sof; +#else + uint32_t frindex = imx9_getreg(priv, IMX9_USBDEV_FRINDEX_OFFSET); + uint16_t frame_num = + (frindex & USBDEV_FRINDEX_LFN_MASK) >> USBDEV_FRINDEX_LFN_SHIFT; + + /* Return the last frame number detected by the hardware */ + + usbtrace(TRACE_DEVGETFRAME, frame_num); + + return (int)(frame_num); +#endif +} + +/**************************************************************************** + * Name: imx9_wakeup + * + * Description: + * Tries to wake up the host connected to this device + * + ****************************************************************************/ + +static int imx9_wakeup(struct usbdev_s *dev) +{ + irqstate_t flags; + struct imx9_usb_s *priv = (struct imx9_usb_s *)dev; + + usbtrace(TRACE_DEVWAKEUP, 0); + + flags = enter_critical_section(); + imx9_modifyreg(priv, IMX9_USBDEV_PORTSC1_OFFSET, 0, USBDEV_PRTSC1_FPR); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: imx9_selfpowered + * + * Description: + * Sets/clears the device selfpowered feature + * + ****************************************************************************/ + +static int imx9_selfpowered(struct usbdev_s *dev, bool selfpowered) +{ + struct imx9_usb_s *priv = (struct imx9_usb_s *)dev; + + usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); + +#ifdef CONFIG_DEBUG_FEATURES + if (!dev) + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_INVALIDPARMS), 0); + return -ENODEV; + } +#endif + + priv->selfpowered = selfpowered; + return OK; +} + +/**************************************************************************** + * Name: imx9_pullup + * + * Description: + * Software-controlled connect to/disconnect from USB host + * + ****************************************************************************/ + +static int imx9_pullup(struct usbdev_s *dev, bool enable) +{ + struct imx9_usb_s *priv = (struct imx9_usb_s *)dev; + + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + + irqstate_t flags = enter_critical_section(); + if (enable) + { + imx9_modifyreg(priv, IMX9_USBDEV_USBCMD_OFFSET, 0, USBDEV_USBCMD_RS); + +#ifdef CONFIG_IMX9_USB0DEV_NOVBUS + /* Create a 'false' power event on the USB port so the MAC connects */ + + imx9_modifyreg(priv, IMX9_USBOTG_OTGSC_OFFSET, USBOTG_OTGSC_VD, 0); + imx9_modifyreg(priv, IMX9_USBOTG_OTGSC_OFFSET, 0, USBOTG_OTGSC_VC); +#endif + } + else + { + imx9_modifyreg(priv, IMX9_USBDEV_USBCMD_OFFSET, USBDEV_USBCMD_RS, 0); + } + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_vbus_detect + * + * Description: + * Read the VBUS state from the USB OTG controller. This can be used + * to poll the VBUS state + * + * Input Parameters: + * id: IMX9_USBC1 or IMX9_USBC2 + * + * Returned Value: + * true if VBUS is valid; false otherwise + * + ****************************************************************************/ + +bool imx9_vbus_detect(imx9_usb_id_t id) +{ + int i; + struct imx9_usb_s *priv; + uint32_t otgsc = 0; + + /* Find the correct device to which the driver is bound to */ + + for (i = 0; i < n_usbdevs; i++) + { + if (id == g_usbdev[i].id) + { + break; + } + } + + if (i < n_usbdevs) + { + priv = &g_usbdev[i]; + otgsc = imx9_getreg(priv, IMX9_USBOTG_OTGSC_OFFSET); + } + + return (otgsc & USBOTG_OTGSC_AVV) != 0; +} + +/**************************************************************************** + * Name: arm64_usbinitialize + * + * Description: + * Initialize USB hardware. + * + * Assumptions: + * - This function is called very early in the initialization sequence + * + ****************************************************************************/ + +void arm64_usbinitialize(void) +{ + /* For now, this driver supports just one usb device, either + * USBC1 or USBC2. The configured one is in g_usbdev[0]. + */ + + struct imx9_usb_s *priv = &g_usbdev[0]; + int i; + irqstate_t flags; + + flags = enter_critical_section(); + + /* Initialize the device state structure */ + + priv->usbdev.ops = &g_devops; + priv->usbdev.ep0 = &priv->eplist[IMX9_EP0_IN].ep; + priv->epavail = IMX9_EPALLSET & ~IMX9_EPCTRLSET; + + /* Initialize the endpoint list */ + + for (i = 0; i < IMX9_NPHYSENDPOINTS; i++) + { + uint32_t bit = 1 << i; + + /* Set endpoint operations, reference to driver structure and + * the physical endpoint number (which is just the index to the + * endpoint). + */ + + priv->eplist[i].ep.ops = &g_epops; + priv->eplist[i].dev = priv; + + /* The index, i, is the physical endpoint address; Map this + * to a logical endpoint address usable by the class driver. + */ + + priv->eplist[i].epphy = i; + if (IMX9_EPPHYIN(i)) + { + priv->eplist[i].ep.eplog = IMX9_EPPHYIN2LOG(i); + } + else + { + priv->eplist[i].ep.eplog = IMX9_EPPHYOUT2LOG(i); + } + + /* The maximum packet size may depend on the type of endpoint */ + + if ((IMX9_EPCTRLSET & bit) != 0) + { + priv->eplist[i].ep.maxpacket = IMX9_EP0MAXPACKET; + } + else if ((IMX9_EPINTRSET & bit) != 0) + { + priv->eplist[i].ep.maxpacket = IMX9_INTRMAXPACKET; + } + else if ((IMX9_EPBULKSET & bit) != 0) + { + priv->eplist[i].ep.maxpacket = IMX9_BULKMAXPACKET; + } + else /* if ((IMX9_EPISOCSET & bit) != 0) */ + { + priv->eplist[i].ep.maxpacket = IMX9_ISOCMAXPACKET; + } + } + + /* Clock gate on */ + + imx9_ccm_gate_on(CCM_LPCG_USB_CONTROLLER, true); + + /* Disable USB interrupts */ + + imx9_putreg(priv, IMX9_USBDEV_USBINTR_OFFSET, 0); + + /* Soft reset PHY and enable clock - not needed for on-chip USB2 phy */ + + /* Disconnect device */ + + imx9_pullup(&priv->usbdev, false); + + /* Reset the controller */ + + imx9_modifyreg(priv, IMX9_USBDEV_USBCMD_OFFSET, 0, USBDEV_USBCMD_RST); + while (imx9_getreg(priv, IMX9_USBDEV_USBCMD_OFFSET) & USBDEV_USBCMD_RST); + + /* Power up the PHY - not needed for on-chip USB2 phy */ + + /* Program the controller to be the USB device controller */ + + imx9_putreg(priv, IMX9_USBDEV_USBMODE_OFFSET, + USBDEV_USBMODE_SDIS | USBDEV_USBMODE_SLOM | + USBDEV_USBMODE_CM_DEVICE); + + /* Attach USB controller interrupt handler */ + + irq_attach(IMX9_IRQ_USB1 + priv->id, imx9_usbinterrupt, priv); + up_enable_irq(IMX9_IRQ_USB1 + priv->id); + + leave_critical_section(flags); + + /* Reset/Re-initialize the USB hardware */ + + imx9_usbreset(priv); +} + +/**************************************************************************** + * Name: arm_usbuninitialize + ****************************************************************************/ + +void arm64_usbuninitialize(void) +{ + struct imx9_usb_s *priv = &g_usbdev[0]; + irqstate_t flags; + + usbtrace(TRACE_DEVUNINIT, 0); + + if (priv->driver) + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_DRIVERREGISTERED), 0); + usbdev_unregister(priv->driver); + } + + flags = enter_critical_section(); + + /* Disconnect device */ + + imx9_pullup(&priv->usbdev, false); + priv->usbdev.speed = USB_SPEED_UNKNOWN; + + /* Disable and detach IRQs */ + + up_disable_irq(IMX9_IRQ_USB1 + priv->id); + irq_detach(IMX9_IRQ_USB1 + priv->id); + + /* Reset the controller */ + + imx9_modifyreg(priv, IMX9_USBDEV_USBCMD_OFFSET, 0, USBDEV_USBCMD_RST); + while (imx9_getreg(priv, IMX9_USBDEV_USBCMD_OFFSET) & USBDEV_USBCMD_RST); + + /* Turn off USB power and clocking */ + + /* Power down the PHY */ + + /* Clock gate off - NOTE: this turns off the clock from both controllers. + * Add reference counting if expanding this to support several ones. + */ + + imx9_ccm_gate_on(CCM_LPCG_USB_CONTROLLER, false); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: usbdev_register + * + * Description: + * Register a USB device class driver. The class driver's bind() method + * will be called to bind it to a USB device driver. + * + ****************************************************************************/ + +int usbdev_register(struct usbdevclass_driver_s *driver) +{ + int ret; + + usbtrace(TRACE_DEVREGISTER, 0); + +#ifdef CONFIG_DEBUG_FEATURES + if (!driver || !driver->ops->bind || !driver->ops->unbind || + !driver->ops->disconnect || !driver->ops->setup) + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } + + if (g_usbdev[0].driver) + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_DRIVER), 0); + return -EBUSY; + } +#endif + + /* First hook up the driver */ + + g_usbdev[0].driver = driver; + + /* Then bind the class driver */ + + ret = CLASS_BIND(driver, &g_usbdev[0].usbdev); + if (ret) + { + usbtrace(TRACE_DEVERROR(IMX9_TRACEERR_BINDFAILED), (uint16_t)-ret); + g_usbdev[0].driver = NULL; + } + else + { + /* Enable USB controller interrupts */ + + up_enable_irq(IMX9_IRQ_USB1 + g_usbdev[0].id); + } + + return ret; +} + +/**************************************************************************** + * Name: usbdev_unregister + * + * Description: + * Un-register usbdev class driver.If the USB device is connected to a USB + * host, it will first disconnect(). The driver is also requested to + * unbind() and clean up any device state, before this procedure finally + * returns. + * + ****************************************************************************/ + +int usbdev_unregister(struct usbdevclass_driver_s *driver) +{ + int i; + + usbtrace(TRACE_DEVUNREGISTER, 0); + + /* Find the correct device to which the driver is bound to */ + + for (i = 0; i < n_usbdevs; i++) + { + if (driver == g_usbdev[i].driver) + { + break; + } + } + + if (i == n_usbdevs) + { + return -EINVAL; + } + + /* Unbind the class driver */ + + CLASS_UNBIND(driver, &g_usbdev[i].usbdev); + + /* Disable USB controller interrupts */ + + up_disable_irq(IMX9_IRQ_USB1 + g_usbdev[i].id); + + /* Unhook the driver */ + + g_usbdev[i].driver = NULL; + + return OK; +} + diff --git a/arch/arm64/src/imx9/imx9_usbdev.h b/arch/arm64/src/imx9/imx9_usbdev.h new file mode 100644 index 0000000000000..b18008c3545b5 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_usbdev.h @@ -0,0 +1,86 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_usbdev.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_USBDEV_H +#define __ARCH_ARM64_SRC_IMX9_IMX9_USBDEV_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef enum +{ + IMX9_USBC1 = 0, + IMX9_USBC2 = 1, +} imx9_usb_id_t; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_vbus_detect + * + * Description: + * Read the VBUS state from the USB OTG controller. This can be used + * to poll the VBUS state + * + * Input Parameters: + * id: IMX9_USBC1 or IMX9_USBC2 + * + * Returned Value: + * true if VBUS is valid; false otherwise + * + ****************************************************************************/ + +bool imx9_vbus_detect(imx9_usb_id_t id); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM64_SRC_IMX9_IMX9_USBDEV_H */ diff --git a/arch/arm64/src/imx9/imx9_usdhc.c b/arch/arm64/src/imx9/imx9_usdhc.c new file mode 100644 index 0000000000000..29f0501c7be66 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_usdhc.c @@ -0,0 +1,3430 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_usdhc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "arm64_internal.h" +#include "imx9_gpio.h" +#include "hardware/imx9_pinmux.h" +#include "hardware/imx9_ccm.h" +#include "imx9_iomuxc.h" +#include "imx9_ccm.h" +#include "imx9_clockconfig.h" +#include "imx9_usdhc.h" + +#ifdef CONFIG_IMX9_USDHC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(ARMV8A_DCACHE_LINESIZE) || ARMV8A_DCACHE_LINESIZE == 0 +# undef ARMV8A_DCACHE_LINESIZE +# define ARMV8A_DCACHE_LINESIZE 64 +#endif + +#define DCACHE_LINEMASK (ARMV8A_DCACHE_LINESIZE - 1) + +#if !defined(CONFIG_ARM64_DCACHE_DISABLE) +# define cache_aligned_alloc(s) kmm_memalign(ARMV8A_DCACHE_LINESIZE,(s)) +# define CACHE_ALIGNED_DATA aligned_data(ARMV8A_DCACHE_LINESIZE) +#else +# define cache_aligned_alloc kmm_malloc +# define CACHE_ALIGNED_DATA +#endif + +/* Configuration ************************************************************/ + +#if ((defined(CONFIG_IMX9_USDHC1) && !defined(CONFIG_IMX9_USDHC2)) || \ + (defined(CONFIG_IMX9_USDHC2) && !defined(CONFIG_IMX9_USDHC1))) +# define IMX9_MAX_SDHC_DEV_SLOTS 1 +#elif (defined(CONFIG_IMX9_USDHC1) && defined(CONFIG_IMX9_USDHC2)) +# define IMX9_MAX_SDHC_DEV_SLOTS 2 +#else +#error Unrecognised number of SDHC slots +#endif + +#if !defined(CONFIG_IMX9_USDHC_DMA) +# warning "Large Non-DMA transfer may result in RX overrun failures" +#elif !defined(CONFIG_SDIO_DMA) +# warning CONFIG_SDIO_DMA should be defined with CONFIG_IMX9_USDHC_DMA +#endif + +#if !defined(CONFIG_SCHED_WORKQUEUE) || !defined(CONFIG_SCHED_HPWORK) +# error "Callback support requires CONFIG_SCHED_WORKQUEUE and CONFIG_SCHED_HPWORK" +#endif + +#if !defined(CONFIG_SDIO_BLOCKSETUP) +# error "CONFIG_SDIO_BLOCKSETUP is mandatory for this driver" +#endif + +#ifndef CONFIG_DEBUG_MEMCARD_INFO +# undef CONFIG_SDIO_XFRDEBUG +#endif + +/* Timing in ms for commands wait response */ + +#define USDHC_CMDTIMEOUT MSEC2TICK(100) +#define USDHC_LONGTIMEOUT MSEC2TICK(500) + +/* Big DTOCV setting. + * 1101 - SDCLK x 2 29, + * recommend to use for supported speed modes + * except HS200, HS400, SDR104 mode + * + * 1110 - SDCLK x 2 30, recommend to use for HS200 and SDR104 mode + */ + +#define USDHC_DTOCV_MAXTIMEOUT (13) + +/* Maximum watermark value */ + +#define USDHC_MAX_WATERMARK 128 + +/* Block size for multi-block transfers */ + +#define SDMMC_MAX_BLOCK_SIZE (512) + +/* Data transfer / Event waiting interrupt mask bits */ + +#define USDHC_RESPERR_INTS (USDHC_INT_CCE | USDHC_INT_CTOE | \ + USDHC_INT_CEBE | USDHC_INT_CIE) +#define USDHC_RESPDONE_INTS (USDHC_RESPERR_INTS | USDHC_INT_CC) + +#define USDHC_XFRERR_INTS (USDHC_INT_DCE | USDHC_INT_DTOE | \ + USDHC_INT_DEBE) +#define USDHC_RCVDONE_INTS (USDHC_XFRERR_INTS | USDHC_INT_BRR | \ + USDHC_INT_TC) +#define USDHC_SNDDONE_INTS (USDHC_XFRERR_INTS | USDHC_INT_BWR | \ + USDHC_INT_TC) +#define USDHC_XFRDONE_INTS (USDHC_XFRERR_INTS | USDHC_INT_BRR | \ + USDHC_INT_BWR | USDHC_INT_TC) + +/* CD Detect Types */ + +/* For DMA operations DINT is not interesting TC will indicate completions */ + +#define USDHC_DMAERR_INTS (USDHC_XFRERR_INTS | USDHC_INT_DMAE) +#define USDHC_DMADONE_INTS (USDHC_DMAERR_INTS | USDHC_INT_TC) + +#define USDHC_WAITALL_INTS (USDHC_RESPDONE_INTS | \ + USDHC_XFRDONE_INTS | \ + USDHC_DMADONE_INTS) + +/* Register logging support */ + +#ifdef CONFIG_SDIO_XFRDEBUG +# if defined(CONFIG_IMX9_USDHC1) +# define DBG_BASE_ADDR IMX9_USDHC1_BASE +# else +# define DBG_BASE_ADDR IMX9_USDHC2_BASE +# endif +# define SAMPLENDX_BEFORE_SETUP 0 +# define SAMPLENDX_AFTER_SETUP 1 +# define SAMPLENDX_END_TRANSFER 2 +# define DEBUG_NSAMPLES 3 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure defines the state of the Imx9 SDIO interface */ + +struct imx9_dev_s +{ + struct sdio_dev_s dev; /* Standard, base SDIO interface */ + + /* Imx9-specific extensions */ + + /* Event support */ + + sem_t waitsem; /* Implements event waiting */ + sdio_eventset_t waitevents; /* Set of events to be waited for */ + uint32_t waitints; /* Interrupt enables for event waiting */ + volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */ + struct wdog_s waitwdog; /* Watchdog that handles event timeouts */ + + /* Callback support */ + + sdio_statset_t cdstatus; /* Card status */ + sdio_eventset_t cbevents; /* Set of events to be cause callbacks */ + worker_t callback; /* Registered callback function */ + void *cbarg; /* Registered callback argument */ + struct work_s cbwork; /* Callback work queue structure */ + + /* Interrupt mode data transfer support */ + + uint32_t *buffer; /* Address of current R/W buffer */ + size_t remaining; /* Number of bytes remaining in the + * transfer */ + uint32_t xfrints; /* Interrupt enables for data transfer */ + +#ifdef CONFIG_IMX9_USDHC_DMA + /* DMA data transfer support */ + + volatile uint8_t xfrflags; /* Used to synchronize SDIO and DMA + * completion */ + /* DMA buffer for unaligned transfers */ +#if !defined(CONFIG_ARM64_DCACHE_DISABLE) + uint32_t blocksize; /* Current block size */ + uint8_t rxbuffer[SDMMC_MAX_BLOCK_SIZE] + __attribute__((aligned(ARMV8A_DCACHE_LINESIZE))); + bool unaligned_rx; /* buffer is not cache-line aligned */ +#endif +#endif + + /* Card interrupt support for SDIO */ + + uint32_t cintints; /* Interrupt enables for card ints */ + int (*do_sdio_card)(void *); /* SDIO card ISR */ + void *do_sdio_arg; /* arg for SDIO card ISR */ + + uint32_t addr; /* Base address of this instances */ + uint32_t sw_cd_gpio; /* If a non USDHCx CD pin is used, + * this is its GPIO */ + uint32_t cd_invert; /* If true invert the CD pin */ +}; + +/* Register logging support */ + +#ifdef CONFIG_SDIO_XFRDEBUG +struct imx9_sdhcregs_s +{ + /* All read-able USDHC registers */ + + uint32_t dsaddr; /* DMA System Address Register */ + uint32_t blkattr; /* Block Attributes Register */ + uint32_t cmdarg; /* Command Argument Register */ + uint32_t xferty; /* Transfer Type Register */ + uint32_t cmdrsp0; /* Command Response 0 */ + uint32_t cmdrsp1; /* Command Response 1 */ + uint32_t cmdrsp2; /* Command Response 2 */ + uint32_t cmdrsp3; /* Command Response 3 */ + uint32_t dbap; /* Data buffer access port */ + uint32_t prsstat; /* Present State Register */ + uint32_t proctl; /* Protocol Control Register */ + uint32_t sysctl; /* System Control Register */ + uint32_t irqstat; /* Interrupt Status Register */ + uint32_t irqstaten; /* Interrupt Status Enable Register */ + uint32_t irqsigen; /* Interrupt Signal Enable Register */ + uint32_t ac12err; /* Auto CMD12 Error Status Register */ + uint32_t htcapblt; /* Host Controller Capabilities */ + uint32_t wml; /* Watermark Level Register */ + uint32_t mixctrl; /* Mixer Control */ + uint32_t fevent; /* Force Event */ + uint32_t admaes; /* ADMA Error Status Register */ + uint32_t adsaddr; /* ADMA System Address Register */ + uint32_t dllctrl; /* Delay line control */ + uint32_t dllstat; /* Delay line status */ + uint32_t clktune; /* Clock tune and control */ + uint32_t vendor; /* Vendor Specific Register */ + uint32_t mmcboot; /* MMC Boot Register */ + uint32_t vendor2; /* Vendor Specific Register 2 */ + uint32_t tuningctrl; /* Tuning Control */ +}; +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Low-level helpers ********************************************************/ + +static void imx9_configwaitints(struct imx9_dev_s *priv, uint32_t waitints, + sdio_eventset_t waitevents, sdio_eventset_t wkupevents); +static void imx9_configxfrints(struct imx9_dev_s *priv, uint32_t xfrints); + +/* DMA Helpers **************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void imx9_sampleinit(void); +static void imx9_sdhcsample(struct imx9_sdhcregs_s *regs); +static void imx9_sample(struct imx9_dev_s *priv, int index); +static void imx9_dumpsample(struct imx9_dev_s *priv, + struct imx9_sdhcregs_s *regs, const char *msg); +static void imx9_dumpsamples(struct imx9_dev_s *priv); +static void imx9_showregs(struct imx9_dev_s *priv, const char *msg); + +#else +# define imx9_sampleinit() +# define imx9_sample(priv, index) +# define imx9_dumpsamples(priv) +# define imx9_showregs(priv, msg) +#endif + +/* Data Transfer Helpers ****************************************************/ + +static void imx9_dataconfig(struct imx9_dev_s *priv, bool bwrite, + unsigned int datalen, unsigned int timeout); + +#ifndef CONFIG_IMX9_USDHC_DMA +static void imx9_transmit(struct imx9_dev_s *priv); +static void imx9_receive(struct imx9_dev_s *priv); +#if !defined(CONFIG_ARM64_DCACHE_DISABLE) +static void imx9_recvdma(struct imx9_dev_s *priv); +#endif +#endif + +static void imx9_eventtimeout(wdparm_t arg); +static void imx9_endwait(struct imx9_dev_s *priv, + sdio_eventset_t wkupevent); +static void imx9_endtransfer(struct imx9_dev_s *priv, + sdio_eventset_t wkupevent); + +/* Interrupt Handling *******************************************************/ + +static int imx9_interrupt(int irq, void *context, void *arg); + +/* SDIO interface methods ***************************************************/ + +/* Mutual exclusion */ + +#ifdef CONFIG_SDIO_MUXBUS +static int imx9_lock(struct sdio_dev_s *dev, bool lock); +#endif + +/* Initialization/setup */ + +static void imx9_reset(struct sdio_dev_s *dev); +static sdio_capset_t imx9_capabilities(struct sdio_dev_s *dev); +static sdio_statset_t imx9_status(struct sdio_dev_s *dev); +static void imx9_widebus(struct sdio_dev_s *dev, bool enable); + +#ifdef CONFIG_IMX9_USDHC_ABSFREQ +static void imx9_frequency(struct sdio_dev_s *dev, uint32_t frequency); +#endif + +static void imx9_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate); +static int imx9_attach(struct sdio_dev_s *dev); + +/* Command/Status/Data Transfer */ + +static int imx9_sendcmd(struct sdio_dev_s *dev, uint32_t cmd, + uint32_t arg); + +#ifdef CONFIG_SDIO_BLOCKSETUP +static void imx9_blocksetup(struct sdio_dev_s *dev, + unsigned int blocklen, unsigned int nblocks); +#endif + +#ifndef CONFIG_IMX9_USDHC_DMA +static int imx9_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, + size_t nbytes); +static int imx9_sendsetup(struct sdio_dev_s *dev, + const uint8_t *buffer, size_t nbytes); +#endif + +static int imx9_cancel(struct sdio_dev_s *dev); +static int imx9_waitresponse(struct sdio_dev_s *dev, uint32_t cmd); +static int imx9_recvshortcrc(struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort); +static int imx9_recvlong(struct sdio_dev_s *dev, uint32_t cmd, + uint32_t rlong[4]); +static int imx9_recvshort(struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort); + +/* EVENT handler */ + +static void imx9_waitenable(struct sdio_dev_s *dev, + sdio_eventset_t eventset, uint32_t timeout); +static sdio_eventset_t imx9_eventwait(struct sdio_dev_s *dev); +static void imx9_callbackenable(struct sdio_dev_s *dev, + sdio_eventset_t eventset); +static int imx9_registercallback(struct sdio_dev_s *dev, + worker_t callback, void *arg); + +/* DMA */ + +#ifdef CONFIG_IMX9_USDHC_DMA +# if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) +static int imx9_dmapreflight(struct sdio_dev_s *dev, + const uint8_t *buffer, size_t buflen); +# endif +static int imx9_dmarecvsetup(struct sdio_dev_s *dev, + uint8_t *buffer, size_t buflen); +static int imx9_dmasendsetup(struct sdio_dev_s *dev, + const uint8_t *buffer, size_t buflen); +#endif + +/* Initialization/uninitialization/reset ************************************/ + +static void imx9_callback(void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct imx9_dev_s g_sdhcdev[IMX9_MAX_SDHC_DEV_SLOTS] = +{ +#ifdef CONFIG_IMX9_USDHC1 + { + .addr = IMX9_USDHC1_BASE, +#if defined(PIN_USDHC1_CD_GPIO) + .sw_cd_gpio = PIN_USDHC1_CD_GPIO, +#endif +#if defined(CONFIG_IMX9_USDHC1_INVERT_CD) + .cd_invert = true, +#endif + .dev = + { +#ifdef CONFIG_SDIO_MUXBUS + .lock = imx9_lock, +#endif + .reset = imx9_reset, + .capabilities = imx9_capabilities, + .status = imx9_status, + .widebus = imx9_widebus, + .clock = imx9_clock, + .attach = imx9_attach, + .sendcmd = imx9_sendcmd, +#ifdef CONFIG_SDIO_BLOCKSETUP + .blocksetup = imx9_blocksetup, +#endif + +#ifndef CONFIG_IMX9_USDHC_DMA + .recvsetup = imx9_recvsetup, + .sendsetup = imx9_sendsetup, +#else + .recvsetup = imx9_dmarecvsetup, + .sendsetup = imx9_dmasendsetup, +#endif + .cancel = imx9_cancel, + .waitresponse = imx9_waitresponse, + .recv_r1 = imx9_recvshortcrc, + .recv_r2 = imx9_recvlong, + .recv_r3 = imx9_recvshort, + .recv_r4 = imx9_recvshort, + .recv_r5 = imx9_recvshortcrc, + .recv_r6 = imx9_recvshortcrc, + .recv_r7 = imx9_recvshort, + .waitenable = imx9_waitenable, + .eventwait = imx9_eventwait, + .callbackenable = imx9_callbackenable, + .registercallback = imx9_registercallback, +#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_IMX9_USDHC_DMA +# if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) + .dmapreflight = imx9_dmapreflight, +# endif + .dmarecvsetup = imx9_dmarecvsetup, + .dmasendsetup = imx9_dmasendsetup, +#else + .dmarecvsetup = imx9_recvsetup, + .dmasendsetup = imx9_sendsetup, +#endif +#endif + }, + .waitsem = SEM_INITIALIZER(0), + }, +#endif + +#ifdef CONFIG_IMX9_USDHC2 + { + .addr = IMX9_USDHC2_BASE, +#if defined(PIN_USDHC2_CD_GPIO) + .sw_cd_gpio = PIN_USDHC2_CD_GPIO, +#endif +#if defined(CONFIG_IMX9_USDHC2_INVERT_CD) + .cd_invert = true, +#endif + .dev = + { +#ifdef CONFIG_SDIO_MUXBUS + .lock = imx9_lock, +#endif + .reset = imx9_reset, + .capabilities = imx9_capabilities, + .status = imx9_status, + .widebus = imx9_widebus, + .clock = imx9_clock, + .attach = imx9_attach, + .sendcmd = imx9_sendcmd, +#ifdef CONFIG_SDIO_BLOCKSETUP + .blocksetup = imx9_blocksetup, +#endif + +#ifndef CONFIG_IMX9_USDHC_DMA + .recvsetup = imx9_recvsetup, + .sendsetup = imx9_sendsetup, +#else + .recvsetup = imx9_dmarecvsetup, + .sendsetup = imx9_dmasendsetup, +#endif + .cancel = imx9_cancel, + .waitresponse = imx9_waitresponse, + .recv_r1 = imx9_recvshortcrc, + .recv_r2 = imx9_recvlong, + .recv_r3 = imx9_recvshort, + .recv_r4 = imx9_recvshort, + .recv_r5 = imx9_recvshortcrc, + .recv_r6 = imx9_recvshortcrc, + .recv_r7 = imx9_recvshort, + .waitenable = imx9_waitenable, + .eventwait = imx9_eventwait, + .callbackenable = imx9_callbackenable, + .registercallback = imx9_registercallback, +#ifdef CONFIG_SDIO_DMA +#ifdef CONFIG_IMX9_USDHC_DMA +# if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) + .dmapreflight = imx9_dmapreflight, +# endif + .dmarecvsetup = imx9_dmarecvsetup, + .dmasendsetup = imx9_dmasendsetup, +#else + .dmarecvsetup = imx9_recvsetup, + .dmasendsetup = imx9_sendsetup, +#endif +#endif + }, + .waitsem = SEM_INITIALIZER(0), + } +#endif +}; + +#ifdef CONFIG_SDIO_XFRDEBUG +/* Register logging support */ + +static struct imx9_sdhcregs_s g_sampleregs[DEBUG_NSAMPLES]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_configwaitints + * + * Description: + * Enable/disable SDIO interrupts needed to support the wait function + * + * Input Parameters: + * priv - A reference to the SDIO device state structure + * waitints - The set of bits in the SDIO MASK register to set + * waitevents - Waited for events + * wkupevent - Wake-up events + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void imx9_configwaitints(struct imx9_dev_s *priv, uint32_t waitints, + sdio_eventset_t waitevents, + sdio_eventset_t wkupevent) +{ + irqstate_t flags; + + /* Save all of the data and set the new interrupt mask in one, atomic + * operation. + */ + + flags = enter_critical_section(); + priv->waitevents = waitevents; + priv->wkupevent = wkupevent; + priv->waitints = waitints; + +#ifdef CONFIG_IMX9_USDHC_DMA + priv->xfrflags = 0; +#endif + putreg32(priv->xfrints | priv->waitints | priv->cintints, + priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: imx9_configxfrints + * + * Description: + * Enable SDIO interrupts needed to support the data transfer event + * + * Input Parameters: + * priv - A reference to the SDIO device state structure + * xfrints - The set of bits in the SDIO MASK register to set + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void imx9_configxfrints(struct imx9_dev_s *priv, uint32_t xfrints) +{ + irqstate_t flags; + + flags = enter_critical_section(); + priv->xfrints = xfrints; + putreg32(priv->xfrints | priv->waitints | priv->cintints, + priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: imx9_sampleinit + * + * Description: + * Setup prior to collecting DMA samples + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void imx9_sampleinit(void) +{ + memset(g_sampleregs, 0xff, + DEBUG_NSAMPLES * sizeof(struct imx9_sdhcregs_s)); +} +#endif + +/**************************************************************************** + * Name: imx9_sdhcsample + * + * Description: + * Sample SDIO registers + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void imx9_sdhcsample(struct imx9_sdhcregs_s *regs) +{ + regs->dsaddr = getreg32(DBG_BASE_ADDR + IMX9_USDHC_DSADDR_OFFSET); + regs->blkattr = getreg32(DBG_BASE_ADDR + IMX9_USDHC_BLKATTR_OFFSET); + regs->cmdarg = getreg32(DBG_BASE_ADDR + IMX9_USDHC_CMDARG_OFFSET); + regs->xferty = getreg32(DBG_BASE_ADDR + IMX9_USDHC_XFERTYP_OFFSET); + regs->cmdrsp0 = getreg32(DBG_BASE_ADDR + IMX9_USDHC_CMDRSP0_OFFSET); + regs->cmdrsp1 = getreg32(DBG_BASE_ADDR + IMX9_USDHC_CMDRSP1_OFFSET); + regs->cmdrsp2 = getreg32(DBG_BASE_ADDR + IMX9_USDHC_CMDRSP2_OFFSET); + regs->cmdrsp3 = getreg32(DBG_BASE_ADDR + IMX9_USDHC_CMDRSP3_OFFSET); + regs->prsstat = getreg32(DBG_BASE_ADDR + IMX9_USDHC_PRSSTAT_OFFSET); + regs->proctl = getreg32(DBG_BASE_ADDR + IMX9_USDHC_PROCTL_OFFSET); + regs->sysctl = getreg32(DBG_BASE_ADDR + IMX9_USDHC_SYSCTL_OFFSET); + regs->irqstat = getreg32(DBG_BASE_ADDR + IMX9_USDHC_IRQSTAT_OFFSET); + regs->irqstaten = getreg32(DBG_BASE_ADDR + IMX9_USDHC_IRQSTATEN_OFFSET); + regs->irqsigen = getreg32(DBG_BASE_ADDR + IMX9_USDHC_IRQSIGEN_OFFSET); + regs->ac12err = getreg32(DBG_BASE_ADDR + IMX9_USDHC_AC12ERR_OFFSET); + regs->htcapblt = getreg32(DBG_BASE_ADDR + IMX9_USDHC_HTCAPBLT_OFFSET); + regs->wml = getreg32(DBG_BASE_ADDR + IMX9_USDHC_WML_OFFSET); + regs->admaes = getreg32(DBG_BASE_ADDR + IMX9_USDHC_ADMAES_OFFSET); + regs->adsaddr = getreg32(DBG_BASE_ADDR + IMX9_USDHC_ADSADDR_OFFSET); + regs->vendor = getreg32(DBG_BASE_ADDR + IMX9_USDHC_VENDOR_OFFSET); + regs->vendor2 = getreg32(DBG_BASE_ADDR + IMX9_USDHC_VENDOR2_OFFSET); + regs->mmcboot = getreg32(DBG_BASE_ADDR + IMX9_USDHC_MMCBOOT_OFFSET); + regs->mixctrl = getreg32(DBG_BASE_ADDR + IMX9_USDHC_MIX_OFFSET); +} +#endif + +/**************************************************************************** + * Name: imx9_sample + * + * Description: + * Sample SDIO/DMA registers + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void imx9_sample(struct imx9_dev_s *priv, int index) +{ + if (priv->addr == DBG_BASE_ADDR) + { + imx9_sdhcsample(&g_sampleregs[index]); + } +} +#endif + +/**************************************************************************** + * Name: imx9_dumpsample + * + * Description: + * Dump one register sample + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void imx9_dumpsample(struct imx9_dev_s *priv, + struct imx9_sdhcregs_s *regs, const char *msg) +{ + mcinfo("USDHC Registers: %s\n", msg); + mcinfo(" DSADDR[%08x]: %08x\n", + IMX9_USDHC_DSADDR_OFFSET, regs->dsaddr); + mcinfo(" BLKATTR[%08x]: %08x\n", + IMX9_USDHC_BLKATTR_OFFSET, regs->blkattr); + mcinfo(" CMDARG[%08x]: %08x\n", + IMX9_USDHC_CMDARG_OFFSET, regs->cmdarg); + mcinfo(" XFERTY[%08x]: %08x\n", + IMX9_USDHC_XFERTYP_OFFSET, regs->xferty); + mcinfo(" CMDRSP0[%08x]: %08x\n", + IMX9_USDHC_CMDRSP0_OFFSET, regs->cmdrsp0); + mcinfo(" CMDRSP1[%08x]: %08x\n", + IMX9_USDHC_CMDRSP1_OFFSET, regs->cmdrsp1); + mcinfo(" CMDRSP2[%08x]: %08x\n", + IMX9_USDHC_CMDRSP2_OFFSET, regs->cmdrsp2); + mcinfo(" CMDRSP3[%08x]: %08x\n", + IMX9_USDHC_CMDRSP3_OFFSET, regs->cmdrsp3); + mcinfo(" PRSSTAT[%08x]: %08x\n", + IMX9_USDHC_PRSSTAT_OFFSET, regs->prsstat); + mcinfo(" PROCTL[%08x]: %08x\n", + IMX9_USDHC_PROCTL_OFFSET, regs->proctl); + mcinfo(" SYSCTL[%08x]: %08x\n", + IMX9_USDHC_SYSCTL_OFFSET, regs->sysctl); + mcinfo(" IRQSTAT[%08x]: %08x\n", + IMX9_USDHC_IRQSTAT_OFFSET, regs->irqstat); + mcinfo("IRQSTATEN[%08x]: %08x\n", + IMX9_USDHC_IRQSTATEN_OFFSET, regs->irqstaten); + mcinfo(" IRQSIGEN[%08x]: %08x\n", + IMX9_USDHC_IRQSIGEN_OFFSET, regs->irqsigen); + mcinfo(" AC12ERR[%08x]: %08x\n", + IMX9_USDHC_AC12ERR_OFFSET, regs->ac12err); + mcinfo(" HTCAPBLT[%08x]: %08x\n", + IMX9_USDHC_HTCAPBLT_OFFSET, regs->htcapblt); + mcinfo(" WML[%08x]: %08x\n", + IMX9_USDHC_WML_OFFSET, regs->wml); + mcinfo(" MIX[%08x]: %08x\n", + IMX9_USDHC_MIX_OFFSET, regs->mixctrl); + mcinfo(" ADMAES[%08x]: %08x\n", + IMX9_USDHC_ADMAES_OFFSET, regs->admaes); + mcinfo(" ADSADDR[%08x]: %08x\n", + IMX9_USDHC_ADSADDR_OFFSET, regs->adsaddr); + mcinfo(" VENDOR[%08x]: %08x\n", + IMX9_USDHC_VENDOR_OFFSET, regs->vendor); + mcinfo(" VENDOR2[%08x]: %08x\n", + IMX9_USDHC_VENDOR2_OFFSET, regs->vendor2); + mcinfo(" MMCBOOT[%08x]: %08x\n", + IMX9_USDHC_MMCBOOT_OFFSET, regs->mmcboot); +} +#endif + +/**************************************************************************** + * Name: imx9_dumpsamples + * + * Description: + * Dump all sampled register data + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void imx9_dumpsamples(struct imx9_dev_s *priv) +{ + imx9_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], + "Before setup"); + imx9_dumpsample(priv, &g_sampleregs[SAMPLENDX_AFTER_SETUP], + "After setup"); + imx9_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], + "End of transfer"); +} +#endif + +/**************************************************************************** + * Name: imx9_showregs + * + * Description: + * Dump the current state of all registers + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_XFRDEBUG +static void imx9_showregs(struct imx9_dev_s *priv, const char *msg) +{ + struct imx9_sdhcregs_s regs; + + imx9_sdhcsample(®s); + imx9_dumpsample(priv, ®s, msg); +} +#endif + +/**************************************************************************** + * Data Transfer Helpers + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_dataconfig + * + * Description: + * Configure the SDIO data path for the next data transfer + * + ****************************************************************************/ + +static void imx9_dataconfig(struct imx9_dev_s *priv, bool bwrite, + unsigned int datalen, unsigned int timeout) +{ + unsigned int watermark; + uint32_t regval = 0; + + /* Set the data timeout value in the USDHC_SYSCTL field to the selected + * value. + */ + + regval = getreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET); + regval &= ~USDHC_SYSCTL_DTOCV_MASK; + regval |= timeout << USDHC_SYSCTL_DTOCV_SHIFT; + putreg32(regval, priv->addr + IMX9_USDHC_SYSCTL_OFFSET); + +#if defined(CONFIG_IMX9_USDHC_DMA) && !defined(CONFIG_ARM64_DCACHE_DISABLE) + /* If cache is enabled, and this is an unaligned receive, + * receive one block at a time to the internal buffer + */ + + if (!bwrite && priv->unaligned_rx) + { + DEBUGASSERT(priv->blocksize <= sizeof(priv->rxbuffer)); + datalen = priv->blocksize; + } +#endif + + /* Set the watermark level */ + + /* Set the Read Watermark Level to the datalen to be read (limited to half + * of the maximum watermark value). BRR will be set when the number of + * queued words is greater than or equal to this value. + */ + + watermark = (datalen + 3) >> 2; + if (watermark > (USDHC_MAX_WATERMARK / 2)) + { + watermark = (USDHC_MAX_WATERMARK / 2); + } + + /* When the watermark level requirement is met in data transfer, and the + * internal DMA is enabled, the data buffer block sends a DMA request to + * the crossbar switch interface. + */ + + if (bwrite) + { + /* The USDHC will not start data transmission until the number of + * words set in the WML register can be held in the buffer. If the + * buffer is empty and the host system does not write data in time, + * the USDHC will stop the SD_CLK to avoid the data buffer under-run + * situation. + */ + + putreg32(watermark << USDHC_WML_WR_SHIFT, + priv->addr + IMX9_USDHC_WML_OFFSET); + } + else + { + /* The USDHC will not start data transmission until the number of words + * set in the WML register are in the buffer. If the buffer is full and + * the Host System does not read data in time, the USDHC will stop the + * USDHC_DCLK to avoid the data buffer over-run situation. + */ + + putreg32(watermark << USDHC_WML_RD_SHIFT, + priv->addr + IMX9_USDHC_WML_OFFSET); + } +} + +/**************************************************************************** + * Name: imx9_transmit + * + * Description: + * Send SDIO data in interrupt mode + * + * Input Parameters: + * priv - An instance of the SDIO device interface + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_IMX9_USDHC_DMA +static void imx9_transmit(struct imx9_dev_s *priv) +{ + union + { + uint32_t w; + uint8_t b[4]; + } data; + + /* Loop while there is more data to be sent, while buffer write enable + * (PRSSTAT.BWEN) + */ + + mcinfo("Entry: remaining: %lu IRQSTAT: %08x\n", priv->remaining, + getreg32(priv->addr + IMX9_USDHC_IRQSTAT_OFFSET)); + + while (priv->remaining > 0 && + (getreg32(priv->addr + IMX9_USDHC_PRSSTAT_OFFSET) & + USDHC_PRSSTAT_BWEN) != 0) + { + /* Is there a full word remaining in the user buffer? */ + + if (priv->remaining >= sizeof(uint32_t)) + { + /* Yes, transfer the word to the TX FIFO */ + + data.w = *priv->buffer++; + priv->remaining -= sizeof(uint32_t); + } + else + { + /* No.. transfer just the bytes remaining in the user buffer, + * padding with zero as necessary to extend to a full word. + */ + + uint8_t *ptr = (uint8_t *)priv->remaining; + int i; + + data.w = 0; + for (i = 0; i < priv->remaining; i++) + { + data.b[i] = *ptr++; + } + + /* Now the transfer is finished */ + + priv->remaining = 0; + } + + /* Put the word in the FIFO */ + + putreg32(data.w, priv->addr + IMX9_USDHC_DATAPORT_OFFSET); + } + + /* Clear BWR. If there is more data in the buffer, writing to the buffer + * should reset BWR. + */ + + putreg32(USDHC_INT_BWR, priv->addr + IMX9_USDHC_IRQSTAT_OFFSET); + + mcinfo("Exit: remaining: %lu IRQSTAT: %08x\n", priv->remaining, + getreg32(priv->addr + IMX9_USDHC_IRQSTAT_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: imx9_receive + * + * Description: + * Receive SDIO data in interrupt mode + * + * Input Parameters: + * priv - An instance of the SDIO device interface + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_IMX9_USDHC_DMA +static void imx9_receive(struct imx9_dev_s *priv) +{ + unsigned int watermark; + union + { + uint32_t w; + uint8_t b[4]; + } data; + + /* Set the Read Watermark Level to 1: BRR will be set when the number of + * queued words is greater than or equal to 1. + */ + + putreg32(1 << USDHC_WML_RD_SHIFT, priv->addr + IMX9_USDHC_WML_OFFSET); + + /* Loop while there is space to store the data, waiting for buffer + * read ready (BRR) + */ + + mcinfo("Entry: remaining: %lu IRQSTAT: %08x\n", priv->remaining, + getreg32(priv->addr + IMX9_USDHC_IRQSTAT_OFFSET)); + + while (priv->remaining > 0 && + (getreg32(priv->addr + IMX9_USDHC_IRQSTAT_OFFSET) & + USDHC_INT_BRR) != 0) + { + /* Clear BRR. If there is more data in the buffer, reading from the + * buffer should reset BRR. + */ + + putreg32(USDHC_INT_BRR, priv->addr + IMX9_USDHC_IRQSTAT_OFFSET); + + /* Read the next word from the RX buffer */ + + data.w = getreg32(priv->addr + IMX9_USDHC_DATAPORT_OFFSET); + if (priv->remaining >= sizeof(uint32_t)) + { + /* Transfer the whole word to the user buffer */ + + *priv->buffer++ = data.w; + priv->remaining -= sizeof(uint32_t); + } + else + { + /* Transfer any trailing fractional word */ + + uint8_t *ptr = (uint8_t *)priv->buffer; + int i; + + for (i = 0; i < priv->remaining; i++) + { + *ptr++ = data.b[i]; + } + + /* Now the transfer is finished */ + + priv->remaining = 0; + } + } + + /* Set the Read Watermark Level either the number of remaining words to be + * read (limited to half of the maximum watermark value) + */ + + watermark = ((priv->remaining + 3) >> 2); + if (watermark > (USDHC_MAX_WATERMARK / 2)) + { + watermark = (USDHC_MAX_WATERMARK / 2); + } + + putreg32(watermark << USDHC_WML_RD_SHIFT, + priv->addr + IMX9_USDHC_WML_OFFSET); + + mcinfo("Exit: remaining: %lu IRQSTAT: %08x WML: %08x\n", priv->remaining, + getreg32(priv->addr + IMX9_USDHC_IRQSTAT_OFFSET), + getreg32(priv->addr + IMX9_USDHC_WML_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: imx9_recvdma + * + * Description: + * Receive SDIO data in dma mode + * + * Input Parameters: + * priv - Instance of the SDMMC private state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_IMX9_USDHC_DMA) && !defined(CONFIG_ARM64_DCACHE_DISABLE) +static void imx9_recvdma(struct imx9_dev_s *priv) +{ + unsigned int watermark; + + if (priv->unaligned_rx) + { + /* If we are receiving multiple blocks to an unaligned buffers, + * we receive them one-by-one + */ + + /* Invalidate the cache before receiving next block */ + + up_invalidate_dcache((uintptr_t)priv->rxbuffer, + (uintptr_t)priv->rxbuffer + priv->blocksize); + + /* Copy the received data to client buffer */ + + memcpy(priv->buffer, priv->rxbuffer, priv->blocksize); + + /* Update how much there is left to receive */ + + priv->remaining -= priv->blocksize; + } + else + { + /* In an aligned case, we have always received all blocks */ + + priv->remaining = 0; + } + + if (priv->remaining == 0) + { + /* no data remaining, end the transfer */ + + imx9_endtransfer(priv, SDIOWAIT_TRANSFERDONE); + } + else + { + /* We end up here only in unaligned rx-buffers case, and are receiving + * the data one block at a time + */ + + /* Update where to receive the following block */ + + priv->buffer = (uint32_t *)((uintptr_t)priv->buffer + priv->blocksize); + + watermark = (priv->blocksize + 3) >> 2; + if (watermark > (USDHC_MAX_WATERMARK / 2)) + { + watermark = (USDHC_MAX_WATERMARK / 2); + } + + /* Re-enable datapath and wait for next block */ + + putreg32(watermark << USDHC_WML_RD_SHIFT, + priv->addr + IMX9_USDHC_WML_OFFSET); + } +} + +#endif +/**************************************************************************** + * Name: imx9_eventtimeout + * + * Description: + * The watchdog timeout setup when the event wait start has expired without + * any other waited-for event occurring. + * + * Input Parameters: + * arg - The argument + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +static void imx9_eventtimeout(wdparm_t arg) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)arg; + + DEBUGASSERT(priv != NULL); + DEBUGASSERT((priv->waitevents & SDIOWAIT_TIMEOUT) != 0); + + /* Is a data transfer complete event expected? */ + + if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0) + { + /* Yes.. Sample registers at the time of the timeout */ + + imx9_sample(priv, SAMPLENDX_END_TRANSFER); + + /* Wake up any waiting threads */ + + imx9_endwait(priv, SDIOWAIT_TIMEOUT); + mcerr("ERROR: Timeout: remaining: %lu\n", priv->remaining); + } +} + +/**************************************************************************** + * Name: imx9_endwait + * + * Description: + * Wake up a waiting thread if the waited-for event has occurred. + * + * Input Parameters: + * priv - An instance of the SDIO device interface + * wkupevent - The event that caused the wait to end + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +static void imx9_endwait(struct imx9_dev_s *priv, + sdio_eventset_t wkupevent) +{ + /* Cancel the watchdog timeout */ + + wd_cancel(&priv->waitwdog); + + /* Disable event-related interrupts */ + + imx9_configwaitints(priv, 0, 0, wkupevent); + + /* Wake up the waiting thread */ + + nxsem_post(&priv->waitsem); +} + +/**************************************************************************** + * Name: imx9_endtransfer + * + * Description: + * Terminate a transfer with the provided status. This function is called + * only from the SDIO interrupt handler when end-of-transfer conditions + * are detected. + * + * Input Parameters: + * priv - An instance of the SDIO device interface + * wkupevent - The event that caused the transfer to end + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +static void imx9_endtransfer(struct imx9_dev_s *priv, + sdio_eventset_t wkupevent) +{ + /* Disable all transfer related interrupts */ + + imx9_configxfrints(priv, 0); + + /* Clearing pending interrupt status on all transfer related interrupts */ + + putreg32(USDHC_XFRDONE_INTS | USDHC_DMADONE_INTS, + priv->addr + IMX9_USDHC_IRQSTAT_OFFSET); + + /* Mark the transfer finished */ + + priv->remaining = 0; + + /* Debug instrumentation */ + + imx9_sample(priv, SAMPLENDX_END_TRANSFER); + + /* Is a thread wait for these data transfer complete events? */ + + if ((priv->waitevents & wkupevent) != 0) + { + /* Yes.. wake up any waiting threads */ + + imx9_endwait(priv, wkupevent); + } +} + +/**************************************************************************** + * Name: imx9_interrupt + * + * Description: + * SDIO interrupt handler + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int imx9_interrupt(int irq, void *context, void *arg) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)arg; + uint32_t enabled; + uint32_t pending; + uint32_t regval; + + /* Check the USDHC IRQSTAT register. Mask out all bits that don't + * correspond to enabled interrupts. (This depends on the fact that bits + * are ordered the same in both the IRQSTAT and IRQSIGEN registers). + * If there are non-zero bits remaining, then we have work to do here. + */ + + regval = getreg32(priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET); + enabled = getreg32(priv->addr + IMX9_USDHC_IRQSTAT_OFFSET) & regval; + + mcinfo("IRQSTAT: %08" PRIx32 " IRQSIGEN %08" PRIx32 + " enabled: %08" PRIx32 "\n", + getreg32(priv->addr + IMX9_USDHC_IRQSTAT_OFFSET), regval, enabled); + + /* Clear all pending interrupts */ + + putreg32(enabled, priv->addr + IMX9_USDHC_IRQSTAT_OFFSET); + + /* Handle in progress, interrupt driven data transfers ********************/ + + pending = enabled & priv->xfrints; + if (pending != 0) + { +#ifndef CONFIG_IMX9_USDHC_DMA + /* Is the RX buffer read ready? Is so then we must be processing a + * non-DMA receive transaction. + */ + + if ((pending & USDHC_INT_BRR) != 0) + { + /* Receive data from the RX buffer */ + + imx9_receive(priv); + } + + /* Otherwise, Is the TX buffer write ready? If so we must be processing + * non-DMA send transaction. NOTE: We can't be processing both! + */ + + else if ((pending & USDHC_INT_BWR) != 0) + { + /* Send data via the TX FIFO */ + + imx9_transmit(priv); + } +#endif + + /* ... transfer complete events */ + + if ((pending & USDHC_INT_TC) != 0) + { + /* Terminate the transfer */ +#if defined(CONFIG_IMX9_USDHC_DMA) && !defined(CONFIG_ARM64_DCACHE_DISABLE) + imx9_recvdma(priv); +#else + imx9_endtransfer(priv, SDIOWAIT_TRANSFERDONE); +#endif + } + + /* ... data block send/receive CRC failure */ + + else if ((pending & USDHC_INT_DCE) != 0) + { + /* Terminate the transfer with an error */ + + mcerr("ERROR: Data block CRC failure, remaining: %lu\n", + priv->remaining); + imx9_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); + } + + /* ... data timeout error */ + + else if ((pending & USDHC_INT_DTOE) != 0) + { + /* Terminate the transfer with an error */ + + mcerr("ERROR: Data timeout, remaining: %lu\n", priv->remaining); + imx9_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT); + } + } + + /* Handle Card interrupt events *******************************************/ + + pending = enabled & priv->cintints; + if ((pending & USDHC_INT_CINT) != 0) + { + if (priv->do_sdio_card) + { + (priv->do_sdio_card)(priv->do_sdio_arg); + } + + /* We don't want any more ints now, so switch it off */ + + regval &= ~USDHC_INT_CINT; + priv->cintints = regval; + putreg32(regval, priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET); + } + + if ((pending & USDHC_INT_CINS) != 0 || (pending & USDHC_INT_CRM) != 0) + { + if (up_interrupt_context()) + { + /* Yes.. queue it */ + + mcinfo("Queuing callback to %p(%p)\n", + priv->callback, priv->cbarg); + + work_queue(HPWORK, &priv->cbwork, priv->callback, + priv->cbarg, 0); + } + else + { + /* No.. then just call the callback here */ + + mcinfo("Callback to %p(%p)\n", priv->callback, priv->cbarg); + + priv->callback(priv->cbarg); + } + } + + /* Handle wait events *****************************************************/ + + pending = enabled & priv->waitints; + if (pending != 0) + { + /* Is this a response completion event? */ + + if ((pending & USDHC_RESPDONE_INTS) != 0) + { + /* Yes.. Is there a thread waiting for response done? */ + + if ((priv->waitevents & + (SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE)) != 0) + { + /* Yes.. mask further interrupts and wake the thread up */ + + regval = getreg32(priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET); + regval &= ~USDHC_RESPDONE_INTS; + putreg32(regval, priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET); + + imx9_endwait(priv, SDIOWAIT_RESPONSEDONE); + } + } + } + + return OK; +} + +/**************************************************************************** + * SDIO Interface Methods + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_lock + * + * Description: + * Locks the bus. Function calls low-level multiplexed bus routines to + * resolve bus requests and acknowledgment issues. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * lock - TRUE to lock, FALSE to unlock. + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_MUXBUS +static int imx9_lock(struct sdio_dev_s *dev, bool lock) +{ + /* The multiplex bus is part of board support package. */ + + /* FIXME: Implement the below function to support bus share: + * + * imx9_muxbus_sdio_lock((dev - g_sdhcdev) / + * sizeof(struct imx9_dev_s), lock); + */ + + return OK; +} +#endif + +/**************************************************************************** + * Name: imx9_reset + * + * Description: + * Reset the SDIO controller. Undo all setup and initialization. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void imx9_reset(struct sdio_dev_s *dev) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + + /* Disable all interrupts so that nothing interferes with the following. */ + + putreg32(0, priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET); + + /* Reset the USDHC block, putting registers in their default, reset state. + * Initiate the reset by setting the RSTA bit in the SYSCTL register. + * USDHC_VS2_BUSRESET has not been documented in i.MX93 ref manual. + */ + + modifyreg32(priv->addr + IMX9_USDHC_VENDOR2_OFFSET, 0, USDHC_VS2_BUSRESET); + modifyreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET, 0, USDHC_SYSCTL_RSTA); + modifyreg32(priv->addr + IMX9_USDHC_VENDOR2_OFFSET, + USDHC_VS2_BUSRESET | USDHC_VS2_ACMD23ARGU2, 0); + + /* The USDHC will reset the RSTA bit to 0 when the capabilities registers + * are valid and the host driver can read them. + */ + + while ((getreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET) & + USDHC_SYSCTL_RSTA) != 0) + { + } + + mcinfo("Reset complete\n"); + + /* Make sure that all clocking is disabled */ + + imx9_clock(dev, CLOCK_SDIO_DISABLED); + + /* Enable all status bits (these could not all be potential sources of + * interrupts. + */ + + putreg32(USDHC_INT_ALL, priv->addr + IMX9_USDHC_IRQSTATEN_OFFSET); + + mcinfo("SYSCTL: %08" PRIx32 " PRSSTAT: %08" PRIx32 + " IRQSTATEN: %08" PRIx32 "\n", + getreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET), + getreg32(priv->addr + IMX9_USDHC_PRSSTAT_OFFSET), + getreg32(priv->addr + IMX9_USDHC_IRQSTATEN_OFFSET)); + + /* The next phase of the hardware reset would be to set the SYSCTRL INITA + * bit to send 80 clock ticks for card to power up and then reset the card + * with CMD0. This is done elsewhere. + */ + + /* Reset state data */ + + priv->waitevents = 0; /* Set of events to be waited for */ + priv->waitints = 0; /* Interrupt enables for event waiting */ + priv->wkupevent = 0; /* The event that caused the wakeup */ +#ifdef CONFIG_IMX9_USDHC_DMA + priv->xfrflags = 0; /* Used to synchronize SDIO and DMA completion */ +#endif + + wd_cancel(&priv->waitwdog); /* Cancel any timeouts */ + + /* Interrupt mode data transfer support */ + + priv->buffer = 0; /* Address of current R/W buffer */ + priv->remaining = 0; /* Number of bytes remaining in the transfer */ + priv->xfrints = 0; /* Interrupt enables for data transfer */ +} + +/**************************************************************************** + * Name: imx9_capabilities + * + * Description: + * Get capabilities (and limitations) of the SDIO driver (optional) + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Returns a bitset of status values (see SDIO_CAPS_* defines) + * + ****************************************************************************/ + +static sdio_capset_t imx9_capabilities(struct sdio_dev_s *dev) +{ + sdio_capset_t caps = 0; + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + + switch (priv->addr) + { + case IMX9_USDHC1_BASE: +#ifdef CONFIG_IMX9_USDHC1_WIDTH_D1_ONLY + caps |= SDIO_CAPS_1BIT_ONLY; +#endif +#ifdef CONFIG_IMX9_USDHC1_WIDTH_D1_D4 + caps |= SDIO_CAPS_4BIT; +#endif +#ifdef CONFIG_IMX9_USDHC1_WIDTH_D1_D8 + caps |= SDIO_CAPS_8BIT; +#endif + break; + + case IMX9_USDHC2_BASE: +#ifdef CONFIG_IMX9_USDHC2_WIDTH_D1_ONLY + caps |= SDIO_CAPS_1BIT_ONLY; +#endif +#ifdef CONFIG_IMX9_USDHC2_WIDTH_D1_D4 + caps |= SDIO_CAPS_4BIT; +#endif + break; + + default: + break; + } + +#ifdef CONFIG_IMX9_USDHC_DMA + caps |= SDIO_CAPS_DMASUPPORTED; +#endif + caps |= SDIO_CAPS_DMABEFOREWRITE; + + return caps; +} + +/**************************************************************************** + * Name: imx9_status + * + * Description: + * Get SDIO status. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Returns a bitset of status values (see imx9_status_* defines) + * + ****************************************************************************/ + +static sdio_statset_t imx9_status(struct sdio_dev_s *dev) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + bool present = false; + + /* Board did not use one of the GPIO_USDHCn_CD pins + * but instead a GPIO was used and defined in board.h + * as PIN_USDHCx_CD_GPIO + */ + + if (priv->sw_cd_gpio != 0) + { + present = priv->cd_invert ^ !imx9_gpio_read(priv->sw_cd_gpio); + } + else + { + /* This register reflects the state of CD no matter if it's a separate pin + * or DAT3 + */ + + present = ((getreg32(priv->addr + IMX9_USDHC_PRSSTAT_OFFSET) & + USDHC_PRSSTAT_CINS) != 0) ^ priv->cd_invert; + } + + if (present) + { + priv->cdstatus |= SDIO_STATUS_PRESENT; + } + else + { + priv->cdstatus &= ~SDIO_STATUS_PRESENT; + } + + mcinfo("cdstatus=%02x\n", priv->cdstatus); + + return priv->cdstatus; +} + +/**************************************************************************** + * Name: imx9_widebus + * + * Description: + * Called after change in Bus width has been selected (via ACMD6). Most + * controllers will need to perform some special operations to work + * correctly in the new bus mode. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * wide - true: wide bus (4-bit) bus mode enabled + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void imx9_widebus(struct sdio_dev_s *dev, bool wide) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + uint32_t regval; + + /* Set the Data Transfer Width (DTW) field in the PROCTL register. */ + + regval = getreg32(priv->addr + IMX9_USDHC_PROCTL_OFFSET); + regval &= ~USDHC_PROCTL_DTW_MASK; + if (wide) + { + regval |= USDHC_PROCTL_DTW_4BIT; + } + else + { + regval |= USDHC_PROCTL_DTW_1BIT; + } + + putreg32(regval, priv->addr + IMX9_USDHC_PROCTL_OFFSET); +} + +/**************************************************************************** + * Name: imx9_frequency + * + * Description: + * Set the SD clock frequency + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * frequency - The frequency to use + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_USDHC_ABSFREQ +static void imx9_frequency(struct sdio_dev_s *dev, uint32_t frequency) +{ + uint32_t sdclkfs; + uint32_t prescaled; + uint32_t regval; + unsigned int prescaler; + unsigned int divisor; + + /* The SDCLK frequency is determined by + * (1) the frequency of the base clock that was selected as the + * input clock, and + * (2) by a prescaler and a divisor that are selected here: + * + * SDCLK frequency = (base clock) / (prescaler * divisor) + * + * The prescaler is available only for the values: 2, 4, 8, 16, 32, + * 64, 128, and 256. Pick the smallest value of SDCLKFS that would + * result in an in-range frequency. For example, if the base clock + * frequency is 96 MHz, and the target frequency is 25 MHz, the + * following logic will select prescaler: + * + * NOTE: USDHC_SYSCTL_SDCLKFS_DIVs are for Single Data Rate mode. + * See Reference manual for further details. + * + * 96MHz / 2 <= 25MHz <= 96MHz / 2 /16 -- YES, prescaler == 2 + * + * If the target frequency is 400 kHz, the following logic will + * select prescaler: + * + * 96MHz / 2 <= 400KHz <= 96MHz / 2 / 16 -- NO + * 96MHz / 4 <= 400KHz <= 96MHz / 4 / 16 -- NO + * 96MHz / 8 <= 400KHz <= 96MHz / 8 / 16 -- NO + * 96MHz / 16 <=400KHz <= 96MHz / 16 / 16 -- YES, prescaler == 16 + */ + + if (/* frequency >= (BOARD_CORECLK_FREQ / 2) && */ + frequency <= (BOARD_CORECLK_FREQ / 2 / 16)) + { + sdclkfs = USDHC_SYSCTL_SDCLKFS_DIV2; + prescaler = 2; + } + else if (frequency >= (BOARD_CORECLK_FREQ / 4) && + frequency <= (BOARD_CORECLK_FREQ / 4 / 16)) + { + sdclkfs = USDHC_SYSCTL_SDCLKFS_DIV4; + prescaler = 4; + } + else if (frequency >= (BOARD_CORECLK_FREQ / 8) && + frequency <= (BOARD_CORECLK_FREQ / 8 / 16)) + { + sdclkfs = USDHC_SYSCTL_SDCLKFS_DIV8; + prescaler = 8; + } + else if (frequency >= (BOARD_CORECLK_FREQ / 16) && + frequency <= (BOARD_CORECLK_FREQ / 16 / 16)) + { + sdclkfs = USDHC_SYSCTL_SDCLKFS_DIV16; + prescaler = 16; + } + else if (frequency >= (BOARD_CORECLK_FREQ / 32) && + frequency <= (BOARD_CORECLK_FREQ / 32 / 16)) + { + sdclkfs = USDHC_SYSCTL_SDCLKFS_DIV32; + prescaler = 32; + } + else if (frequency >= (BOARD_CORECLK_FREQ / 64) && + frequency <= (BOARD_CORECLK_FREQ / 64 / 16)) + { + sdclkfs = USDHC_SYSCTL_SDCLKFS_DIV64; + prescaler = 64; + } + else if (frequency >= (BOARD_CORECLK_FREQ / 128) && + frequency <= (BOARD_CORECLK_FREQ / 128 / 16)) + { + sdclkfs = USDHC_SYSCTL_SDCLKFS_DIV128; + prescaler = 128; + } + else + { + sdclkfs = USDHC_SYSCTL_SDCLKFS_DIV256; + prescaler = 256; + } + + /* The optimal divider can than be calculated. For example, if the base + * clock frequency is 96 MHz, the target frequency is 25 MHz, and the + * selected prescaler value is 2, then + * + * prescaled = 96MHz / 2 = 48MHz + * divisor = (48MHz + 12.5HMz/ 25MHz = 2 + * + * And the resulting frequency will be 24MHz. Or, for example, if the + * target frequency is 400 kHz and the selected prescaler is 16, the + * following logic will select prescaler: + * + * prescaled = 96MHz / 16 = 6MHz + * divisor = (6MHz + 200KHz) / 400KHz = 15 + * + * And the resulting frequency will be exactly 400KHz. + */ + + prescaled = frequency / prescaler; + divisor = (prescaled + (frequency >> 1)) / frequency; + + /* Set the new divisor information and enable all clocks in the SYSCTRL + * register. TODO: Investigate using the automatically gated clocks to + * reduce power consumption. + */ + + regval = getreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET); + regval &= ~(USDHC_SYSCTL_SDCLKFS_MASK | USDHC_SYSCTL_DVS_MASK); + regval |= (sdclkfs | USDHC_SYSCTL_DVS_DIV(divisor)); + regval |= (USDHC_SYSCTL_SDCLKEN | USDHC_SYSCTL_PEREN | + USDHC_SYSCTL_HCKEN | USDHC_SYSCTL_IPGEN); + + putreg32(regval, priv->addr + IMX9_USDHC_SYSCTL_OFFSET); + + mcinfo("SYSCTRL: %08x\n", + getreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: imx9_clock + * + * Description: + * Enable/disable SDIO clocking + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * rate - Specifies the clocking to use (see enum sdio_clock_e) + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void imx9_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + uint32_t regval; + + /* Clear the old prescaler and divisor values so that new ones can be + * ORed in. + */ + + regval = getreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET); + regval &= ~(USDHC_SYSCTL_SDCLKFS_MASK | USDHC_SYSCTL_DVS_MASK); + + /* Select the new prescaler and divisor values based on the requested + * mode and the settings from the board.h file. Clocks are automatically + * gated by the driver when not needed. + */ + + switch (rate) + { + default: + case CLOCK_SDIO_DISABLED: /* Clock is disabled */ + { + /* Clear the prescaler and divisor settings */ + + putreg32(regval, priv->addr + IMX9_USDHC_SYSCTL_OFFSET); + mcinfo("DISABLED, SYSCTRL: %08" PRIx32 "\n", + getreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET)); return; + } + break; + + case CLOCK_IDMODE: + { + /* Initial ID mode clocking (<400KHz) */ + + mcinfo("IDMODE\n"); + + /* Put out an additional 80 clocks in case this is a power-up + * sequence. + */ + + regval |= (BOARD_USDHC_IDMODE_PRESCALER | + BOARD_USDHC_IDMODE_DIVISOR | + USDHC_SYSCTL_INITA); + } + break; + + case CLOCK_MMC_TRANSFER: + { + /* MMC normal operation clocking */ + + mcinfo("MMCTRANSFER\n"); + regval |= (BOARD_USDHC_MMCMODE_PRESCALER | + BOARD_USDHC_MMCMODE_DIVISOR); + } + break; + + case CLOCK_SD_TRANSFER_1BIT: + { + /* SD normal operation clocking (narrow 1-bit mode) */ + + mcinfo("1BITTRANSFER\n"); + regval |= (BOARD_USDHC_SD1MODE_PRESCALER | + BOARD_USDHC_SD1MODE_DIVISOR); + } + break; + + case CLOCK_SD_TRANSFER_4BIT: + { + /* SD normal operation clocking (wide 4-bit mode) */ + + mcinfo("4BITTRANSFER\n"); + regval |= (BOARD_USDHC_SD4MODE_PRESCALER | + BOARD_USDHC_SD4MODE_DIVISOR); + } + break; + } + + putreg32(regval, priv->addr + IMX9_USDHC_SYSCTL_OFFSET); + + /* Wait for clock to become stable */ + + while ((getreg32(priv->addr + IMX9_USDHC_PRSSTAT_OFFSET) & + USDHC_PRSSTAT_SDSTB) == 0) + { + } + + mcinfo("SYSCTRL: %08" PRIx32 "\n", + getreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET)); +} + +/**************************************************************************** + * Name: imx9_attach + * + * Description: + * Attach and prepare interrupts + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * + * Returned Value: + * OK on success; A negated errno on failure. + * + ****************************************************************************/ + +static int imx9_attach(struct sdio_dev_s *dev) +{ + int ret; + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + int usdhc2_dev = (IMX9_MAX_SDHC_DEV_SLOTS > 1) ? 1 : 0; + + /* Attach the SDIO interrupt handler */ + + if (priv->addr == IMX9_USDHC1_BASE) + { + ret = irq_attach(IMX9_IRQ_USDHC1, imx9_interrupt, &g_sdhcdev[0]); + } + else + { + if (priv->addr == IMX9_USDHC2_BASE) + { + ret = irq_attach(IMX9_IRQ_USDHC2, imx9_interrupt, + &g_sdhcdev[usdhc2_dev]); + } + else + { + PANIC(); + } + } + + if (ret == OK) + { + /* Disable all interrupts at the SDIO controller and clear all pending + * interrupts. + */ + + putreg32(0, priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET); + putreg32(USDHC_INT_ALL, priv->addr + IMX9_USDHC_IRQSTAT_OFFSET); + + /* Enable SDIO interrupts at the NVIC. They can now be enabled at the + * SDIO controller as needed. + */ + + if (priv->addr == IMX9_USDHC1_BASE) + { + up_enable_irq(IMX9_IRQ_USDHC1); + } + else if (priv->addr == IMX9_USDHC2_BASE) + { + up_enable_irq(IMX9_IRQ_USDHC2); + } + } + + return ret; +} + +/**************************************************************************** + * Name: imx9_sendcmd + * + * Description: + * Send the SDIO command + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * cmd - The command to send (32-bits, encoded) + * arg - 32-bit argument required with some commands + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int imx9_sendcmd(struct sdio_dev_s *dev, uint32_t cmd, + uint32_t arg) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + clock_t timeout; + clock_t start; + clock_t elapsed; + uint32_t regval; + uint32_t mcrregval; + uint32_t cmdidx; + + /* Initialize the command index */ + + cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT; + regval = cmdidx << USDHC_XFERTYP_CMDINX_SHIFT; + mcrregval = USDHC_MC_DEFAULTVAL; + + mcinfo("cmdidx: %d\n", cmdidx); + + if (cmdidx == SD_ACMDIDX53) + { + /* Dynamically set parameters for ACMD53 because it can accommodate + * different transmission characteristics (single and multi-block, + * rx & tx). + */ + + if (arg & (1 << 31)) + { + /* Transmit mode */ + + cmd |= MMCSD_WRDATAXFR; + } + else + { + /* Receive mode */ + + cmd |= MMCSD_RDDATAXFR; + } + + if (arg & (1 << 27)) + { + /* In block mode */ + + cmd |= SDIO_MULTIBLOCK; + } + } + + /* Check if a data transfer accompanies the command */ + + switch (cmd & MMCSD_DATAXFR_MASK) + { + default: + case MMCSD_NODATAXFR: + { + /* No.. no data transfer */ + } + break; + + /* The following two cases are probably missing some setup logic */ + + case MMCSD_RDSTREAM: + { + /* Yes.. streaming read data transfer */ + + regval |= USDHC_XFERTYP_DPSEL; + mcrregval |= USDHC_MC_DTDSEL; + } + break; + + case MMCSD_WRSTREAM: + { + /* Yes.. streaming write data transfer */ + + regval |= USDHC_XFERTYP_DPSEL; + } + break; + + case MMCSD_RDDATAXFR: + { + /* Yes.. normal read data transfer */ + + regval |= USDHC_XFERTYP_DPSEL; + mcrregval |= USDHC_MC_DTDSEL; + } + break; + + case MMCSD_WRDATAXFR: + { + /* Yes.. normal write data transfer */ + + regval |= USDHC_XFERTYP_DPSEL; + } + break; + } + + /* Is it a multi-block transfer? */ + + if ((cmd & (MMCSD_MULTIBLOCK | SDIO_MULTIBLOCK)) != 0) + { + mcrregval |= USDHC_MC_MSBSEL; + + /* Yes.. should the transfer be stopped with ACMD12? */ + + if (((cmd & MMCSD_MULTIBLOCK) != 0) && + ((cmd & MMCSD_STOPXFR) != 0)) + { + /* Yes.. Indefinite block transfer (not SDIO) */ + + mcrregval |= USDHC_MC_AC12EN; + } + else + { + /* No.. Fixed block transfer */ + + mcrregval |= USDHC_MC_BCEN; + } + } + + /* Configure response type bits */ + + switch (cmd & MMCSD_RESPONSE_MASK) + { + case MMCSD_NO_RESPONSE: + { + /* No response */ + + regval |= USDHC_XFERTYP_RSPTYP_NONE; + } + break; + + case MMCSD_R1B_RESPONSE: + { + /* Response length 48, check busy & cmdindex */ + + regval |= + (USDHC_XFERTYP_RSPTYP_LEN48BSY | USDHC_XFERTYP_CICEN | + USDHC_XFERTYP_CCCEN); + } + break; + + case MMCSD_R1_RESPONSE: /* Response length 48, check cmdindex */ + case MMCSD_R5_RESPONSE: + case MMCSD_R6_RESPONSE: + { + regval |= + (USDHC_XFERTYP_RSPTYP_LEN48 | USDHC_XFERTYP_CICEN | + USDHC_XFERTYP_CCCEN); + } + break; + + case MMCSD_R2_RESPONSE: + { + /* Response length 136, check CRC */ + + regval |= (USDHC_XFERTYP_RSPTYP_LEN136 | USDHC_XFERTYP_CCCEN); + } + break; + + case MMCSD_R3_RESPONSE: /* Response length 48 */ + case MMCSD_R4_RESPONSE: + case MMCSD_R7_RESPONSE: + { + regval |= USDHC_XFERTYP_RSPTYP_LEN48; + } + break; + } + +#ifdef CONFIG_IMX9_USDHC_DMA + /* Enable DMA */ + + /* Internal DMA is used */ + + mcrregval |= USDHC_MC_DMAEN; +#endif + + /* Check for abort. TODO: Check Suspend/Resume bits too in + * XFR_TYP::CMDTYP. + */ + + if (cmd & MMCSD_STOPXFR) + { + regval |= USDHC_XFERTYP_CMDTYP_ABORT; + } + + mcinfo("cmd: %08" PRIx32 " arg: %08" PRIx32 + " regval: %08" PRIx32 " mcrval: %08" PRIx32 "\n", cmd, arg, + regval, mcrregval); + + /* If there has been a response error then perform a reset and wait for it + * to complete. + */ + + if ((getreg32(priv->addr + IMX9_USDHC_IRQSTAT_OFFSET) & + USDHC_RESPERR_INTS) != 0) + { + modifyreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET, 0, + USDHC_SYSCTL_RSTC); + while ((getreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET) & + USDHC_SYSCTL_RSTC) != 0) + { + } + } + + /* The Command Inhibit (CIHB) bit is set in the PRSSTAT bit immediately + * after the transfer type register is written. This bit is cleared + * when the command response is received. If this status bit is 0, it + * indicates that the CMD line is not in use and the USDHC can issue a + * SD/MMC Command using the CMD line. CIHB should always be clear before + * this function is called, but this check is performed here to provide + * overlap and maximum performance. + */ + + timeout = USDHC_CMDTIMEOUT; + start = clock_systime_ticks(); + while ((getreg32(priv->addr + IMX9_USDHC_PRSSTAT_OFFSET) & + USDHC_PRSSTAT_CIHB) != 0) + { + /* Calculate the elapsed time */ + + elapsed = clock_systime_ticks() - start; + if (elapsed >= timeout) + { + mcerr("ERROR: Timeout (waiting CIHB) cmd: %08" PRIx32 + " PRSSTAT: %08" PRIx32 "\n", + cmd, getreg32(priv->addr + IMX9_USDHC_PRSSTAT_OFFSET)); + return -EBUSY; + } + } + + /* Set the USDHC Argument value */ + + putreg32(arg, priv->addr + IMX9_USDHC_CMDARG_OFFSET); + + /* Clear interrupt status and write the USDHC CMD */ + + putreg32(USDHC_RESPDONE_INTS, priv->addr + IMX9_USDHC_IRQSTAT_OFFSET); + putreg32(mcrregval, priv->addr + IMX9_USDHC_MIX_OFFSET); + putreg32(regval, priv->addr + IMX9_USDHC_XFERTYP_OFFSET); + + return OK; +} + +/**************************************************************************** + * Name: imx9_blocksetup + * + * Description: + * Configure block size and the number of blocks for next transfer + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * blocklen - The selected block size. + * nblocklen - The number of blocks to transfer + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SDIO_BLOCKSETUP +static void imx9_blocksetup(struct sdio_dev_s *dev, + unsigned int blocklen, + unsigned int nblocks) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + + mcinfo("blocklen=%d, total transfer=%d (%d blocks)\n", blocklen, + blocklen * nblocks, nblocks); + + /* Configure block size for next transfer */ + +#if !defined(CONFIG_ARM64_DCACHE_DISABLE) + priv->blocksize = blocklen; +#endif + + putreg32(USDHC_BLKATTR_SIZE(blocklen) | USDHC_BLKATTR_CNT(nblocks), + priv->addr + IMX9_USDHC_BLKATTR_OFFSET); +} +#endif + +/**************************************************************************** + * Name: imx9_recvsetup + * + * Description: + * Setup hardware in preparation for data transfer from the card in non- + * DMA (interrupt driven mode). This method will do whatever controller + * setup is necessary. This would be called for SD memory just BEFORE + * sending CMD13 (SEND_STATUS), CMD17 (READ_SINGLE_BLOCK), CMD18 + * (READ_MULTIPLE_BLOCKS), ACMD51 (SEND_SCR), etc. Normally, + * SDIO_WAITEVENT will be called to receive the indication that the + * transfer is complete. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * buffer - Address of the buffer in which to receive the data + * nbytes - The number of bytes in the transfer + * + * Returned Value: + * Number of bytes sent on success; a negated errno on failure + * + ****************************************************************************/ + +#ifndef CONFIG_IMX9_USDHC_DMA +static int imx9_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer, + size_t nbytes) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0); + DEBUGASSERT(((uint64_t) buffer & 3) == 0); + + /* Reset the DPSM configuration */ + + imx9_sampleinit(); + imx9_sample(priv, SAMPLENDX_BEFORE_SETUP); + + /* Save the destination buffer information for use by the interrupt + * handler and DMA memory invalidation. + */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = nbytes; + + /* Then set up the SDIO data path */ + + imx9_dataconfig(priv, false, nbytes, USDHC_DTOCV_MAXTIMEOUT); + + /* And enable interrupts */ + + imx9_configxfrints(priv, USDHC_RCVDONE_INTS); + imx9_sample(priv, SAMPLENDX_AFTER_SETUP); return OK; +} +#endif + +/**************************************************************************** + * Name: imx9_sendsetup + * + * Description: + * Setup hardware in preparation for data transfer from the card. This + * method will do whatever controller setup is necessary. This would be + * called for SD memory just AFTER sending CMD24 (WRITE_BLOCK), CMD25 + * (WRITE_MULTIPLE_BLOCK), ... and before SDIO_SENDDATA is called. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * buffer - Address of the buffer containing the data to send + * nbytes - The number of bytes in the transfer + * + * Returned Value: + * Number of bytes sent on success; a negated errno on failure + * + ****************************************************************************/ + +#ifndef CONFIG_IMX9_USDHC_DMA +static int imx9_sendsetup(struct sdio_dev_s *dev, + const uint8_t *buffer, + size_t nbytes) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0); + DEBUGASSERT(((uint64_t) buffer & 3) == 0); + + /* Reset the DPSM configuration */ + + imx9_sampleinit(); + imx9_sample(priv, SAMPLENDX_BEFORE_SETUP); + + /* Save the source buffer information for use by the interrupt handler */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = nbytes; + + /* Then set up the SDIO data path */ + + imx9_dataconfig(priv, true, nbytes, USDHC_DTOCV_MAXTIMEOUT); + + /* Enable TX interrupts */ + + imx9_configxfrints(priv, USDHC_SNDDONE_INTS); + imx9_sample(priv, SAMPLENDX_AFTER_SETUP); return OK; +} +#endif + +/**************************************************************************** + * Name: imx9_cancel + * + * Description: + * Cancel the data transfer setup of SDIO_RECVSETUP, SDIO_SENDSETUP, + * SDIO_DMARECVSETUP or SDIO_DMASENDSETUP. This must be called to cancel + * the data transfer setup if, for some reason, you cannot perform the + * transfer. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * + * Returned Value: + * OK is success; a negated errno on failure + * + ****************************************************************************/ + +static int imx9_cancel(struct sdio_dev_s *dev) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + +#ifdef CONFIG_IMX9_USDHC_DMA + uint32_t regval; +#endif + + /* Disable all transfer- and event- related interrupts */ + + imx9_configxfrints(priv, 0); imx9_configwaitints(priv, 0, 0, 0); + + /* Clearing pending interrupt status on all transfer- and event- related + * interrupts + */ + + putreg32(USDHC_WAITALL_INTS, priv->addr + IMX9_USDHC_IRQSTAT_OFFSET); + + /* Cancel any watchdog timeout */ + + wd_cancel(&priv->waitwdog); + + /* If this was a DMA transfer, make sure that DMA is stopped */ + +#ifdef CONFIG_IMX9_USDHC_DMA + + /* Stop the DMA by resetting the data path */ + + regval = getreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET); + regval |= USDHC_SYSCTL_RSTD; + putreg32(regval, priv->addr + IMX9_USDHC_SYSCTL_OFFSET); +#endif + + /* Mark no transfer in progress */ + + priv->remaining = 0; + + return OK; +} + +/**************************************************************************** + * Name: imx9_waitresponse + * + * Description: + * Poll-wait for the response to the last command to be ready. This + * function should be called even after sending commands that have no + * response (such as CMD0) to make sure that the hardware is ready to + * receive the next command. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * cmd - The command that was sent. See 32-bit command definitions above. + * + * Returned Value: + * OK is success; a negated errno on failure + * + ****************************************************************************/ + +static int imx9_waitresponse(struct sdio_dev_s *dev, uint32_t cmd) +{ + clock_t timeout; + clock_t start; + clock_t elapsed; + uint32_t errors; + uint32_t enerrors; + + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + int ret = OK; + + switch (cmd & MMCSD_RESPONSE_MASK) + { + case MMCSD_NO_RESPONSE: + timeout = USDHC_CMDTIMEOUT; + errors = 0; + break; + + case MMCSD_R1_RESPONSE: + case MMCSD_R1B_RESPONSE: + case MMCSD_R2_RESPONSE: + case MMCSD_R4_RESPONSE: + case MMCSD_R5_RESPONSE: + case MMCSD_R6_RESPONSE: + { + timeout = USDHC_LONGTIMEOUT; + errors = USDHC_RESPERR_INTS; + } + break; + + case MMCSD_R3_RESPONSE: + case MMCSD_R7_RESPONSE: + { + timeout = USDHC_CMDTIMEOUT; + errors = USDHC_RESPERR_INTS; + } + break; + + default: + return -EINVAL; + } + + /* Then wait for the Command Complete (CC) indication (or timeout). The + * CC bit is set when the end bit of the command response is received + * (except Auto CMD12). + */ + + start = clock_systime_ticks(); + while ((getreg32(priv->addr + IMX9_USDHC_IRQSTAT_OFFSET) & + USDHC_INT_CC) == 0) + { + /* Calculate the elapsed time */ + + elapsed = clock_systime_ticks() - start; + if (elapsed >= timeout) + { + mcerr("ERROR: Timeout cmd: %08" PRIx32 + " IRQSTAT: %08" PRIx32 "\n", cmd, + getreg32(priv->addr + IMX9_USDHC_IRQSTAT_OFFSET)); + ret = -ETIMEDOUT; + break; + } + } + + /* Check for hardware detected errors */ + + enerrors = getreg32(priv->addr + IMX9_USDHC_IRQSTAT_OFFSET) & errors; + if (enerrors != 0) + { + mcerr("ERROR: cmd: %08" PRIx32 " errors: %08" PRIx32 ", " + "fired %08" PRIx32 " IRQSTAT: %08" PRIx32 "\n", + cmd, errors, enerrors, + getreg32(priv->addr + IMX9_USDHC_IRQSTAT_OFFSET)); + + ret = -EIO; + } + + return ret; +} + +/**************************************************************************** + * Name: imx9_recv* + * + * Description: + * Receive response to SDIO command. Only the critical payload is + * returned -- that is 32 bits for 48 bit status and 128 bits for 136 bit + * status. The driver implementation should verify the correctness of + * the remaining, non-returned bits (CRCs, CMD index, etc.). + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * Rx - Buffer in which to receive the response + * + * Returned Value: + * Number of bytes sent on success; a negated errno on failure. Here a + * failure means only a failure to obtain the requested response (due to + * transport problem -- timeout, CRC, etc.). The implementation only + * assures that the response is returned intact and does not check errors + * within the response itself. + * + ****************************************************************************/ + +static int imx9_recvshortcrc(struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + uint32_t regval; + int ret = OK; + + /* R1 Command response (48-bit) + * 47 0 Start bit + * 46 0 Transmission bit (0=from card) + * 45:40 bit5 - bit0 Command index (0-63) + * 39:8 bit31- bit0 32-bit card status + * 7:1 bit6 - bit0 CRC7 + * 0 1 End bit + * + * R1b Identical to R1 with the additional busy signalling via the data + * line. + * R6 Published RCA Response (48-bit, SD card only) + * 47 0 Start bit + * 46 0 Transmission bit (0=from card) + * 45:40 bit5 - bit0 Command index (0-63) + * 39:8 bit31 - bit0 32-bit Argument Field, consisting of: + * [31:16] New published RCA of card + * [15:0] Card status bits + * {23,22,19,12:0} + * 7:1 bit6 - bit0 CRC7 + * 0 1 End bit + */ + +#ifdef CONFIG_DEBUG_FEATURES + if (!rshort) + { + mcerr("ERROR: rshort=NULL\n"); + ret = -EINVAL; + } + + /* Check that this is the correct response to this command */ + + else if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R5_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE) + { + mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd); + ret = -EINVAL; + } + else +#endif + { + /* Check if a timeout or CRC error occurred */ + + regval = getreg32(priv->addr + IMX9_USDHC_IRQSTAT_OFFSET); + if ((regval & USDHC_INT_CTOE) != 0) + { + mcerr("ERROR: Command timeout: %08" PRIx32 "\n", regval); + ret = -ETIMEDOUT; + } + else if ((regval & USDHC_INT_CCE) != 0) + { + mcerr("ERROR: CRC failure: %08" PRIx32 "\n", regval); ret = -EIO; + } + } + + /* Return the R1/R1b/R6 response. These responses are returned in + * CDMRSP0. NOTE: This is not true for R1b (Auto CMD12 response) which is + * returned in CMDRSP3. + */ + + *rshort = getreg32(priv->addr + IMX9_USDHC_CMDRSP0_OFFSET); + return ret; +} + +static int imx9_recvlong(struct sdio_dev_s *dev, uint32_t cmd, + uint32_t rlong[4]) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + uint32_t regval; + int ret = OK; + + /* R2 CID, CSD register (136-bit) + * 135 0 Start bit + * 134 0 Transmission bit (0=from card) + * 133:128 bit5 - bit0 Reserved + * 127:1 bit127 - bit1 127-bit CID or CSD register (including int. CRC) + * 0 1 End bit + */ + +#ifdef CONFIG_DEBUG_FEATURES + /* Check that R1 is the correct response to this command */ + + if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE) + { + mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd); + ret = -EINVAL; + } + else +#endif + { + /* Check if a timeout or CRC error occurred */ + + regval = getreg32(priv->addr + IMX9_USDHC_IRQSTAT_OFFSET); + if (regval & USDHC_INT_CTOE) + { + mcerr("ERROR: Timeout IRQSTAT: %08" PRIx32 "\n", regval); + ret = -ETIMEDOUT; + } + else if (regval & USDHC_INT_CCE) + { + mcerr("ERROR: CRC fail IRQSTAT: %08" PRIx32 "\n", regval); + ret = -EIO; + } + } + + /* Return the long response in CMDRSP3..0 */ + + if (rlong) + { + uint32_t rsp3 = getreg32(priv->addr + IMX9_USDHC_CMDRSP3_OFFSET); + uint32_t rsp2 = getreg32(priv->addr + IMX9_USDHC_CMDRSP2_OFFSET); + uint32_t rsp1 = getreg32(priv->addr + IMX9_USDHC_CMDRSP1_OFFSET); + uint32_t rsp0 = getreg32(priv->addr + IMX9_USDHC_CMDRSP0_OFFSET); + + rlong[0] = rsp3 << 8 | rsp2 >> 24; + rlong[1] = rsp2 << 8 | rsp1 >> 24; + rlong[2] = rsp1 << 8 | rsp0 >> 24; rlong[3] = rsp0 << 8; + } + + return ret; +} + +static int imx9_recvshort(struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + uint32_t regval; + int ret = OK; + + /* R3 OCR (48-bit) + * 47 0 Start bit + * 46 0 Transmission bit (0=from card) + * 45:40 bit5 - bit0 Reserved + * 39:8 bit31- bit0 32-bit OCR register + * 7:1 bit6 - bit0 Reserved + * 0 1 End bit + */ + + /* Check that this is the correct response to this command */ + +#ifdef CONFIG_DEBUG_FEATURES + if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R4_RESPONSE && + (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE) + { + mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd); + ret = -EINVAL; + } + else +#endif + { + /* Check if a timeout occurred (Apparently a CRC error can terminate a + * good response) + */ + + regval = getreg32(priv->addr + IMX9_USDHC_IRQSTAT_OFFSET); + if (regval & USDHC_INT_CTOE) + { + mcerr("ERROR: Timeout IRQSTAT: %08" PRIx32 "\n", regval); + ret = -ETIMEDOUT; + } + } + + /* Return the short response in CMDRSP0 */ + + if (rshort) + { + *rshort = getreg32(priv->addr + IMX9_USDHC_CMDRSP0_OFFSET); + } + + return ret; +} + +/**************************************************************************** + * Name: imx9_waitenable + * + * Description: + * Enable/disable of a set of SDIO wait events. This is part of the + * the SDIO_WAITEVENT sequence. The set of to-be-waited-for events is + * configured before calling imx9_eventwait. This is done in this way + * to help the driver to eliminate race conditions between the command + * setup and the subsequent events. + * + * The enabled events persist until either (1) SDIO_WAITENABLE is called + * again specifying a different set of wait events, or (2) SDIO_EVENTWAIT + * returns. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * eventset - A bitset of events to enable or disable (see SDIOWAIT_* + * definitions). 0=disable; 1=enable. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void imx9_waitenable(struct sdio_dev_s *dev, + sdio_eventset_t eventset, uint32_t timeout) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + uint32_t waitints; + + DEBUGASSERT(priv != NULL); + + /* Disable event-related interrupts */ + + imx9_configwaitints(priv, 0, 0, 0); + + /* Select the interrupt mask that will give us the appropriate wakeup + * interrupts. + */ + + waitints = 0; + if ((eventset & (SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE)) != 0) + { + waitints |= USDHC_RESPDONE_INTS; + } + + if ((eventset & SDIOWAIT_TRANSFERDONE) != 0) + { +#ifdef CONFIG_IMX9_USDHC_DMA + waitints |= USDHC_DMADONE_INTS; +#else + waitints |= USDHC_XFRDONE_INTS; +#endif + } + + /* Enable event-related interrupts */ + + imx9_configwaitints(priv, waitints, eventset, 0); + + /* Check if the timeout event is specified in the event set */ + + if ((priv->waitevents & SDIOWAIT_TIMEOUT) != 0) + { + int delay; + int ret; + + /* Yes.. Handle a corner case */ + + if (!timeout) + { + priv->wkupevent = SDIOWAIT_TIMEOUT; + return; + } + + /* Start the watchdog timer */ + + delay = MSEC2TICK(timeout); + ret = wd_start(&priv->waitwdog, delay, + imx9_eventtimeout, (wdparm_t)priv); + + if (ret < 0) + { + mcerr("ERROR: wd_start failed: %d\n", ret); + } + } +} + +/**************************************************************************** + * Name: imx9_eventwait + * + * Description: + * Wait for one of the enabled events to occur (or a timeout). Note that + * all events enabled by SDIO_WAITEVENTS are disabled when imx9_eventwait + * returns. SDIO_WAITEVENTS must be called again before imx9_eventwait + * can be used again. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * timeout - Maximum time in milliseconds to wait. Zero means immediate + * timeout with no wait. The timeout value is ignored if + * SDIOWAIT_TIMEOUT is not included in the waited-for eventset. + * + * Returned Value: + * Event set containing the event(s) that ended the wait. Should always + * be non-zero. All events are disabled after the wait concludes. + * + ****************************************************************************/ + +static sdio_eventset_t imx9_eventwait(struct sdio_dev_s *dev) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + sdio_eventset_t wkupevent = 0; int ret; + + /* There is a race condition here... the event may have completed before + * we get here. In this case waitevents will be zero, but wkupevents + * will be non-zero (and, hopefully, the semaphore count will also be + * non-zero. + */ + + DEBUGASSERT((priv->waitevents != 0 && priv->wkupevent == 0) || + (priv->waitevents == 0 && priv->wkupevent != 0)); + + /* Loop until the event (or the timeout occurs). Race conditions are + * avoided by calling imx9_waitenable prior to triggering the logic + * that will cause the wait to terminate. Under certain race + * conditions, the waited-for may have already occurred before this + * function was called! + */ + + for (; ; ) + { + /* Wait for an event in event set to occur. If this the event has + * already occurred, then the semaphore will already have been + * incremented and there will be no wait. + */ + + ret = nxsem_wait_uninterruptible(&priv->waitsem); + if (ret < 0) + { + /* Task canceled. Cancel the wdog (assuming it was started) and + * return an SDIO error. + */ + + wd_cancel(&priv->waitwdog); + return SDIOWAIT_ERROR; + } + + wkupevent = priv->wkupevent; + + /* Check if the event has occurred. When the event has occurred, then + * evenset will be set to 0 and wkupevent will be set to a non-zero + * value. + */ + + if (wkupevent != 0) + { + /* Yes... break out of the loop with wkupevent non-zero */ + + break; + } + } + + /* Disable event-related interrupts */ + + imx9_configwaitints(priv, 0, 0, 0); +#ifdef CONFIG_IMX9_USDHC_DMA + priv->xfrflags = 0; +#endif + imx9_dumpsamples(priv); + return wkupevent; +} + +/**************************************************************************** + * Name: imx9_callbackenable + * + * Description: + * Enable/disable of a set of SDIO callback events. This is part of the + * the SDIO callback sequence. The set of events is configured to enabled + * callbacks to the function provided in imx9_registercallback. + * + * Events are automatically disabled once the callback is performed and no + * further callback events will occur until they are again enabled by + * calling this method. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * eventset - A bitset of events to enable or disable (see SDIOMEDIA_* + * definitions). 0=disable; 1=enable. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void imx9_callbackenable(struct sdio_dev_s *dev, + sdio_eventset_t eventset) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + + mcinfo("eventset: %02x\n", eventset); + DEBUGASSERT(priv != NULL); + + priv->cbevents = eventset; + imx9_callback(priv); +} + +/**************************************************************************** + * Name: imx9_registercallback + * + * Description: + * Register a callback that that will be invoked on any media status + * change. Callbacks should not be made from interrupt handlers, rather + * interrupt level events should be handled by calling back on the work + * thread. + * + * When this method is called, all callbacks should be disabled until they + * are enabled via a call to SDIO_CALLBACKENABLE + * + * Input Parameters: + * dev - Device-specific state data + * callback - The function to call on the media change + * arg - A caller provided value to return with the callback + * + * Returned Value: + * 0 on success; negated errno on failure. + * + ****************************************************************************/ + +static int imx9_registercallback(struct sdio_dev_s *dev, + worker_t callback, void *arg) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + + /* Disable callbacks and register this callback and is argument */ + + mcinfo("Register %p(%p)\n", callback, arg); + + DEBUGASSERT(priv != NULL); + priv->cbevents = 0; + priv->cbarg = arg; + priv->callback = callback; + return OK; +} + +/**************************************************************************** + * Name: imx9_dmapreflight + * + * Description: + * Preflight an SDIO DMA operation. If the buffer is not well-formed for + * SDIO DMA transfer (alignment, size, etc.) returns an error. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * buffer - The memory to DMA to/from + * buflen - The size of the DMA transfer in bytes + * + * Returned Value: + * OK on success; a negated errno on failure + ****************************************************************************/ + +#if defined(CONFIG_IMX9_USDHC_DMA) && defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) +static int imx9_dmapreflight(struct sdio_dev_s *dev, + const uint8_t *buffer, size_t buflen) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + DEBUGASSERT(priv != NULL && buflen > 0); + + /* DMA must be possible to the buffer and it must be word (4 bytes) aligned + */ + + if (buffer != priv->rxbuffer && ((uintptr_t)buffer & 3) != 0) + { + mcerr("non word aligned buffer:%p\n", buffer); + return -EFAULT; + } + +#if !defined(CONFIG_ARM64_DCACHE_DISABLE) + /* buffer alignment is required for DMA transfers with dcache in buffered + * mode (not write-through) because a) arch_invalidate_dcache could lose + * buffered writes and b) arch_flush_dcache could corrupt adjacent memory + * if the maddr and the mend+1, the next next address are not on + * ARMV8A_DCACHE_LINESIZE boundaries. + */ + + if (buffer != priv->rxbuffer && + (((uintptr_t)buffer & (ARMV8A_DCACHE_LINESIZE - 1)) != 0 || + ((uintptr_t)(buffer + buflen) & (ARMV8A_DCACHE_LINESIZE - 1)) != 0)) + { + mcerr("dcache unaligned buffer:%p end:%p\n", + buffer, buffer + buflen - 1); + return -EFAULT; + } +#endif + + return 0; +} +#endif + +/**************************************************************************** + * Name: imx9_dmarecvsetup + * + * Description: + * Setup to perform a read DMA. If the processor supports a data cache, + * then this method will also make sure that the contents of the DMA memory + * and the data cache are coherent. For read transfers this may mean + * invalidating the data cache. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * buffer - The memory to DMA from + * buflen - The size of the DMA transfer in bytes + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_USDHC_DMA +static int imx9_dmarecvsetup(struct sdio_dev_s *dev, + uint8_t *buffer, size_t buflen) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); + +#if defined(CONFIG_ARCH_HAVE_SDIO_PREFLIGHT) + /* Normaly imx9_dmapreflight is called prior to imx9_dmarecvsetup + * except for the case where the CSR read is done at initalization + * + * With a total read size of less then priv->rxbuffer we can + * handle the unaligned case herein, using the rxbuffer. + * + * Any other case is a fault. + */ + + DEBUGASSERT(buflen <= sizeof(priv->rxbuffer) || + imx9_dmapreflight(dev, buffer, buflen) == 0); +#endif + + /* Begin sampling register values */ + + imx9_sampleinit(); + imx9_sample(priv, SAMPLENDX_BEFORE_SETUP); + +#if !defined(CONFIG_ARM64_DCACHE_DISABLE) + if (((uintptr_t)buffer & (ARMV8A_DCACHE_LINESIZE - 1)) != 0 || + (buflen & (ARMV8A_DCACHE_LINESIZE - 1)) != 0) + { + /* The read buffer is not cache-line aligned, but will fit in + * the rxbuffer. So read to an internal buffer instead. + */ + + up_invalidate_dcache((uintptr_t)priv->rxbuffer, + (uintptr_t)priv->rxbuffer + priv->blocksize); + + priv->unaligned_rx = true; + } + else + { + up_invalidate_dcache((uintptr_t)buffer, + (uintptr_t)buffer + buflen); + + priv->unaligned_rx = false; + } +#endif + + /* Save the destination buffer information for use by the interrupt + * handler + */ + + priv->buffer = (uint32_t *)buffer; + priv->remaining = buflen; + + /* Then set up the SDIO data path */ + + imx9_dataconfig(priv, false, buflen, USDHC_DTOCV_MAXTIMEOUT); + + /* Configure the RX DMA */ + + imx9_configxfrints(priv, USDHC_DMADONE_INTS); +#if !defined(CONFIG_ARM64_DCACHE_DISABLE) + if (priv->unaligned_rx) + { + putreg32((uint64_t) priv->rxbuffer, + priv->addr + IMX9_USDHC_DSADDR_OFFSET); + } + else +#endif + { + putreg32((uint64_t) priv->buffer, + priv->addr + IMX9_USDHC_DSADDR_OFFSET); + } + + /* Sample the register state */ + + imx9_sample(priv, SAMPLENDX_AFTER_SETUP); + return OK; +} +#endif + +/**************************************************************************** + * Name: imx9_dmasendsetup + * + * Description: + * Setup to perform a write DMA. If the processor supports a data cache, + * then this method will also make sure that the contents of the DMA memory + * and the data cache are coherent. For write transfers, this may mean + * flushing the data cache. + * + * Input Parameters: + * dev - An instance of the SDIO device interface + * buffer - The memory to DMA into + * buflen - The size of the DMA transfer in bytes + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_USDHC_DMA +static int imx9_dmasendsetup(struct sdio_dev_s *dev, + const uint8_t *buffer, size_t buflen) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0); + DEBUGASSERT(((uint64_t) buffer & 3) == 0); + + /* Begin sampling register values */ + + imx9_sampleinit(); + imx9_sample(priv, SAMPLENDX_BEFORE_SETUP); + + /* Save the source buffer information for use by the interrupt handler */ + +#if !defined(CONFIG_ARM64_DCACHE_DISABLE) + priv->unaligned_rx = false; + + /* Flush cache to physical memory when not in DTCM memory */ + + up_clean_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen); + +#endif + priv->buffer = (uint32_t *)buffer; + priv->remaining = buflen; + + /* Then set up the SDIO data path */ + + imx9_dataconfig(priv, true, buflen, USDHC_DTOCV_MAXTIMEOUT); + + /* Configure the TX DMA */ + + putreg32((uint64_t) buffer, priv->addr + IMX9_USDHC_DSADDR_OFFSET); + + /* Sample the register state */ + + imx9_sample(priv, SAMPLENDX_AFTER_SETUP); + + /* Enable TX interrupts */ + + imx9_configxfrints(priv, USDHC_DMADONE_INTS); + return OK; +} +#endif + +/**************************************************************************** + * Name: imx9_callback + * + * Description: + * Perform callback. + * + * Assumptions: + * This function does not execute in the context of an interrupt handler. + * It may be invoked on any user thread or scheduled on the work thread + * from an interrupt handler. + * + ****************************************************************************/ + +static void imx9_callback(void *arg) +{ + struct imx9_dev_s *priv = (struct imx9_dev_s *)arg; + + /* Is a callback registered? */ + + DEBUGASSERT(priv != NULL); + mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", priv->callback, + priv->cbarg, priv->cbevents, priv->cdstatus); + + if (priv->callback) + { + /* Yes.. Check for enabled callback events */ + + if ((priv->cdstatus & SDIO_STATUS_PRESENT) != 0) + { + /* Media is present. Is the media inserted event enabled? */ + + if ((priv->cbevents & SDIOMEDIA_INSERTED) == 0) + { + /* No... return without performing the callback */ + + return; + } + } + else + { + /* Media is not present. Is the media eject event enabled? */ + + if ((priv->cbevents & SDIOMEDIA_EJECTED) == 0) + { + /* No... return without performing the callback */ + + return; + } + } + + /* Perform the callback, disabling further callbacks. Of course, the + * the callback can (and probably should) re-enable callbacks. + */ + + priv->cbevents = 0; + + /* Callbacks cannot be performed in the context of an interrupt + * handler. If we are in an interrupt handler, then queue the + * callback to be performed later on the work thread. + */ + + if (up_interrupt_context()) + { + /* Yes.. queue it */ + + mcinfo("Queuing callback to %p(%p)\n", + priv->callback, priv->cbarg); + + work_queue(HPWORK, &priv->cbwork, priv->callback, + priv->cbarg, 0); + } + else + { + /* No.. then just call the callback here */ + + mcinfo("Callback to %p(%p)\n", + priv->callback, priv->cbarg); + + priv->callback(priv->cbarg); + } + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_usdhc_set_sdio_card_isr + * + * Description: + * SDIO card generates interrupt via SDIO_DATA_1 pin. + * Called by board-specific logic to register an ISR for SDIO card. + * + * Input Parameters: + * func - callback function. + * arg - arg to be passed to the function. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx9_usdhc_set_sdio_card_isr(struct sdio_dev_s *dev, + int (*func)(void *), void *arg) +{ + irqstate_t flags; + uint32_t regval; + struct imx9_dev_s *priv = (struct imx9_dev_s *)dev; + + priv->do_sdio_card = func; + priv->do_sdio_arg = arg; + + if (priv->do_sdio_card != NULL) + { + priv->cintints = USDHC_INT_CINT; + } + else + { + priv->cintints = 0; + } + +#if defined(CONFIG_MMCSD_HAVE_CARDDETECT) + if (priv->sw_cd_gpio == 0) + { + priv->cintints |= USDHC_INT_CINS | USDHC_INT_CRM; + } +#endif + + flags = enter_critical_section(); + regval = getreg32(priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET); + regval = (regval & ~USDHC_INT_CINT) | priv->cintints; + putreg32(regval, priv->addr + IMX9_USDHC_IRQSIGEN_OFFSET); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: imx9_sdhc_initialize + * + * Description: + * Initialize SDIO for operation. + * + * Input Parameters: + * slotno - Slot to be used + * + * Returned Value: + * A reference to an SDIO interface structure. + * NULL is returned on failures. + * + ****************************************************************************/ + +struct sdio_dev_s *imx9_usdhc_initialize(int slotno) +{ + DEBUGASSERT(slotno < IMX9_MAX_SDHC_DEV_SLOTS); + struct imx9_dev_s *priv = &g_sdhcdev[slotno]; + + /* Initialize the USDHC slot structure data structure */ + + switch (priv->addr) + { +#if defined(CONFIG_IMX9_USDHC1) + case IMX9_USDHC1_BASE: + +# if defined(CONFIG_IMX9_USDHC1_WIDTH_D1_D4) || defined(CONFIG_IMX9_USDHC1_WIDTH_D1_D8) + imx9_iomux_configure(PIN_USDHC1_D1_MUX); + imx9_iomux_configure(PIN_USDHC1_D2_MUX); + imx9_iomux_configure(PIN_USDHC1_D3_MUX); +# endif + +# if defined(CONFIG_IMX9_USDHC1_WIDTH_D1_D8) + imx9_iomux_configure(PIN_USDHC1_D4_MUX); + imx9_iomux_configure(PIN_USDHC1_D5_MUX); + imx9_iomux_configure(PIN_USDHC1_D6_MUX); + imx9_iomux_configure(PIN_USDHC1_D7_MUX); +# endif + + /* Clocking and CMD pins (all data widths) */ + + imx9_iomux_configure(PIN_USDHC1_D0_MUX); + imx9_iomux_configure(PIN_USDHC1_DCLK_MUX); + imx9_iomux_configure(PIN_USDHC1_CMD_MUX); + +# if defined(CONFIG_MMCSD_HAVE_CARDDETECT) +# if defined(PIN_USDHC1_CD) + imx9_iomux_configure(PIN_USDHC1_CD_MUX); +# elif defined (PIN_USDHC2_CD_GPIO) + if (priv->sw_cd_gpio != 0) + { + imx9_config_gpio(priv->sw_cd_gpio); + imx9_iomux_configure(PIN_USDHC1_CD_GPIO_MUX); + } +# endif +# endif + + /* Enable clocks */ + + imx9_ccm_configure_root_clock(CCM_CR_USDHC2, SYS_PLL1PFD1, 4); + + imx9_ccm_gate_on(CCM_LPCG_USDHC1, true); + + break; +#endif + +#if defined(CONFIG_IMX9_USDHC2) + case IMX9_USDHC2_BASE: +# if defined(CONFIG_IMX9_USDHC2_WIDTH_D1_D4) + imx9_iomux_configure(PIN_USDHC2_D1_MUX); + imx9_iomux_configure(PIN_USDHC2_D2_MUX); + imx9_iomux_configure(PIN_USDHC2_D3_MUX); +# endif + + imx9_iomux_configure(PIN_USDHC2_D0_MUX); + imx9_iomux_configure(PIN_USDHC2_DCLK_MUX); + imx9_iomux_configure(PIN_USDHC2_CMD_MUX); + +# if defined(CONFIG_MMCSD_HAVE_CARDDETECT) +# if defined(PIN_USDHC2_CD) + imx9_iomux_configure(PIN_USDHC2_CD_MUX); +# elif defined (PIN_USDHC2_CD_GPIO) + if (priv->sw_cd_gpio != 0) + { + imx9_config_gpio(priv->sw_cd_gpio); + imx9_iomux_configure(PIN_USDHC2_CD_GPIO_MUX); + } +# endif +# endif + + imx9_iomux_configure(PIN_USDHC2_VSELECT_MUX); + + /* Enable clocks */ + + imx9_ccm_configure_root_clock(CCM_CR_USDHC2, SYS_PLL1PFD1, 4); + + imx9_ccm_gate_on(CCM_LPCG_USDHC2, true); + + mcinfo("Enabled clocks\n"); + + break; +#endif + default: + return NULL; + } + + imx9_reset(&priv->dev); + imx9_showregs(priv, "After reset"); + + return &g_sdhcdev[slotno].dev; +} + +#endif /* CONFIG_IMX9_USDHC */ diff --git a/arch/arm64/src/imx9/imx9_usdhc.h b/arch/arm64/src/imx9/imx9_usdhc.h new file mode 100644 index 0000000000000..0b830914e2805 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_usdhc.h @@ -0,0 +1,75 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_usdhc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_USDHC_H +#define __ARCH_ARM64_SRC_IMX9_IMX9_USDHC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "chip.h" +#include "hardware/imx9_usdhc.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_usdhc_set_sdio_card_isr + * + * Description: + * SDIO card generates interrupt via SDIO_DATA_1 pin. + * Called by board-specific logic to register an ISR for SDIO card. + * + * Input Parameters: + * func - callback function. + * arg - arg to be passed to the function. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx9_usdhc_set_sdio_card_isr(struct sdio_dev_s *dev, + int (*func)(void *), void *arg); + +/**************************************************************************** + * Name: imx9_usdhc_initialize + * + * Description: + * Initialize USDHC for operation. + * + * Input Parameters: + * slotno - Not used. + * + * Returned Value: + * A reference to an USDIO interface structure. NULL is returned on + * failures. + * + ****************************************************************************/ + +struct sdio_dev_s *imx9_usdhc_initialize(int slotno); + +#endif /* __ARCH_ARM64_SRC_IMX9_IMX9_USDHC_H */ diff --git a/arch/arm64/src/qemu/CMakeLists.txt b/arch/arm64/src/qemu/CMakeLists.txt new file mode 100644 index 0000000000000..eda0e13e2ef36 --- /dev/null +++ b/arch/arm64/src/qemu/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# arch/arm64/src/qemu/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## +set(SRCS qemu_boot.c qemu_serial.c) + +if(CONFIG_ARCH_EARLY_PRINT) + list(APPEND SRCS qemu_lowputc.S) +endif() +if(CONFIG_ARCH_USE_TEXT_HEAP) + list(APPEND SRCS qemu_textheap.c) +endif() +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm64/src/qemu/qemu_boot.c b/arch/arm64/src/qemu/qemu_boot.c index e9e28ec5748eb..151a7101a3c65 100644 --- a/arch/arm64/src/qemu/qemu_boot.c +++ b/arch/arm64/src/qemu/qemu_boot.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif diff --git a/arch/arm64/src/rk3399/rk3399_boot.c b/arch/arm64/src/rk3399/rk3399_boot.c index 85cdb6f8ba7b6..3d77452d03689 100644 --- a/arch/arm64/src/rk3399/rk3399_boot.c +++ b/arch/arm64/src/rk3399/rk3399_boot.c @@ -29,7 +29,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include #endif diff --git a/arch/avr/include/avr32/types.h b/arch/avr/include/avr32/types.h index ec18719c7724d..ad3be5ba959bc 100644 --- a/arch/avr/include/avr32/types.h +++ b/arch/avr/include/avr32/types.h @@ -79,7 +79,7 @@ typedef int _wchar_t; */ #define unsigned signed -typedef __SIZE_TYPE__ _ssize_t; +typedef int _ssize_t; /* Keep avr32-gcc 4.4.7 happy. */ #undef unsigned typedef __SIZE_TYPE__ _size_t; #elif defined(CONFIG_ARCH_SIZET_LONG) diff --git a/arch/avr/include/irq.h b/arch/avr/include/irq.h index 60cd9197a0498..3b6ba6793e6d6 100644 --- a/arch/avr/include/irq.h +++ b/arch/avr/include/irq.h @@ -74,7 +74,7 @@ extern "C" #ifndef __ASSEMBLY__ /* This holds a references to the current interrupt level register storage - * structure. If is non-NULL only during interrupt processing. + * structure. It is non-NULL only during interrupt processing. */ #ifdef CONFIG_ARCH_FAMILY_AVR32 diff --git a/arch/avr/src/Makefile b/arch/avr/src/Makefile index 22d5465791f0b..da50e27beea9a 100644 --- a/arch/avr/src/Makefile +++ b/arch/avr/src/Makefile @@ -18,7 +18,7 @@ # ############################################################################ -include $(TOPDIR)/Make.defs +include $(TOPDIR)/tools/apps-or-nuttx-Make.defs include chip/Make.defs ifeq ($(CONFIG_ARCH_FAMILY_AVR32),y) diff --git a/arch/avr/src/at32uc3/at32uc3b_pinmux.h b/arch/avr/src/at32uc3/at32uc3b_pinmux.h index 4c5c51f50b28f..087bc0f5f7c0d 100644 --- a/arch/avr/src/at32uc3/at32uc3b_pinmux.h +++ b/arch/avr/src/at32uc3/at32uc3b_pinmux.h @@ -1,5 +1,4 @@ /**************************************************************************** - * arch/avr/src/at32uc3/at32uc3b_pinmux.h * * Licensed to the Apache Software Foundation (ASF) under one or more diff --git a/arch/avr/src/avr/Toolchain.defs b/arch/avr/src/avr/Toolchain.defs index ea98f72bcbff1..d60a34c24cfce 100644 --- a/arch/avr/src/avr/Toolchain.defs +++ b/arch/avr/src/avr/Toolchain.defs @@ -99,11 +99,15 @@ else endif ARCHCFLAGS += -fno-common -ARCHCXXFLAGS += -fno-common -nostdinc++ +ARCHCXXFLAGS += -fno-common ARCHCFLAGS += -Wall -Wstrict-prototypes -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas ARCHCXXFLAGS += -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas +ifneq ($(CONFIG_LIBCXXTOOLCHAIN),y) + ARCHCXXFLAGS += -nostdinc++ +endif + ifneq ($(CONFIG_CXX_STANDARD),) ARCHCXXFLAGS += -std=$(CONFIG_CXX_STANDARD) endif diff --git a/arch/avr/src/avr/avr_checkstack.c b/arch/avr/src/avr/avr_checkstack.c index 270fe1cb10391..e53dfd37f1230 100644 --- a/arch/avr/src/avr/avr_checkstack.c +++ b/arch/avr/src/avr/avr_checkstack.c @@ -149,7 +149,7 @@ size_t up_check_tcbstack(FAR struct tcb_s *tcb) } #if CONFIG_ARCH_INTERRUPTSTACK > 3 -size_t up_check_intstack(void) +size_t up_check_intstack(int cpu) { uintptr_t start = (uintptr_t)g_intstackalloc; return avr_stack_check(start, CONFIG_ARCH_INTERRUPTSTACK & ~3); diff --git a/arch/avr/src/avr32/Toolchain.defs b/arch/avr/src/avr32/Toolchain.defs index 8c9d19510cecc..97ce2fd174dd1 100644 --- a/arch/avr/src/avr32/Toolchain.defs +++ b/arch/avr/src/avr32/Toolchain.defs @@ -46,11 +46,15 @@ else endif ARCHCFLAGS += -fno-common -ARCHCXXFLAGS += -fno-common -nostdinc++ +ARCHCXXFLAGS += -fno-common ARCHCFLAGS += -Wall -Wstrict-prototypes -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas ARCHCXXFLAGS += -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas +ifneq ($(CONFIG_LIBCXXTOOLCHAIN),y) + ARCHCXXFLAGS += -nostdinc++ +endif + ifneq ($(CONFIG_CXX_STANDARD),) ARCHCXXFLAGS += -std=$(CONFIG_CXX_STANDARD) endif diff --git a/arch/avr/src/common/avr_exit.c b/arch/avr/src/common/avr_exit.c index 5dd28dc7baed3..99da35aecdf88 100644 --- a/arch/avr/src/common/avr_exit.c +++ b/arch/avr/src/common/avr_exit.c @@ -61,8 +61,6 @@ void up_exit(int status) enter_critical_section(); - sinfo("TCB=%p exiting\n", tcb); - nxsched_dumponexit(); /* Destroy the task at the head of the ready to run list. */ diff --git a/arch/avr/src/common/avr_getintstack.c b/arch/avr/src/common/avr_getintstack.c index 8baceec9ddc94..fa2e979113a8a 100644 --- a/arch/avr/src/common/avr_getintstack.c +++ b/arch/avr/src/common/avr_getintstack.c @@ -37,7 +37,7 @@ ****************************************************************************/ #if CONFIG_ARCH_INTERRUPTSTACK > 3 -uintptr_t up_get_intstackbase(void) +uintptr_t up_get_intstackbase(int cpu) { return (uintptr_t)g_intstackalloc; } diff --git a/arch/ceva/include/irq.h b/arch/ceva/include/irq.h index 36e9c63940682..8762b1e7904d1 100644 --- a/arch/ceva/include/irq.h +++ b/arch/ceva/include/irq.h @@ -94,7 +94,7 @@ extern "C" #endif /* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt + * register storage structure. It is non-NULL only during interrupt * processing. Access to g_current_regs[] must be through the macro * CURRENT_REGS for portability. */ diff --git a/arch/ceva/src/Makefile b/arch/ceva/src/Makefile index a4518d1768e2c..cd0c91c132e92 100644 --- a/arch/ceva/src/Makefile +++ b/arch/ceva/src/Makefile @@ -18,7 +18,7 @@ # ############################################################################ --include $(TOPDIR)/Make.defs +include $(TOPDIR)/tools/apps-or-nuttx-Make.defs -include chip$(DELIM)Make.defs ifeq ($(CONFIG_ARCH_XC5),y) diff --git a/arch/ceva/src/common/ceva_checkstack.c b/arch/ceva/src/common/ceva_checkstack.c index 3d0fe35914867..eb0f295677d0f 100644 --- a/arch/ceva/src/common/ceva_checkstack.c +++ b/arch/ceva/src/common/ceva_checkstack.c @@ -143,7 +143,7 @@ size_t up_check_tcbstack(struct tcb_s *tcb) tcb->adj_stack_size); } -size_t up_check_intstack(void) +size_t up_check_intstack(int cpu) { return ceva_stack_check((uintptr_t)g_intstackalloc, g_intstackbase - g_intstackalloc); diff --git a/arch/ceva/src/common/ceva_doirq.c b/arch/ceva/src/common/ceva_doirq.c index 0763410e94a58..7a24a146714c5 100644 --- a/arch/ceva/src/common/ceva_doirq.c +++ b/arch/ceva/src/common/ceva_doirq.c @@ -34,7 +34,7 @@ ****************************************************************************/ /* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt + * register storage structure. It is non-NULL only during interrupt * processing. Access to g_current_regs[] must be through the macro * CURRENT_REGS for portability. */ diff --git a/arch/ceva/src/common/ceva_getintstack.c b/arch/ceva/src/common/ceva_getintstack.c index 5b7ffd25f5c82..877eac7f66ac9 100644 --- a/arch/ceva/src/common/ceva_getintstack.c +++ b/arch/ceva/src/common/ceva_getintstack.c @@ -37,7 +37,7 @@ ****************************************************************************/ #if CONFIG_ARCH_INTERRUPTSTACK > 3 -uintptr_t up_get_intstackbase(void) +uintptr_t up_get_intstackbase(int cpu) { return (uintptr_t)g_intstackalloc; } diff --git a/arch/ceva/src/xc5/Toolchain.defs b/arch/ceva/src/xc5/Toolchain.defs index 966851da06b02..4baa578d512e7 100644 --- a/arch/ceva/src/xc5/Toolchain.defs +++ b/arch/ceva/src/xc5/Toolchain.defs @@ -65,11 +65,15 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y) endif ARCHCFLAGS += -fno-common -ARCHCXXFLAGS += -fno-common -nostdinc++ +ARCHCXXFLAGS += -fno-common ARCHCFLAGS += -Wall -Wstrict-prototypes -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas ARCHCXXFLAGS += -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas +ifneq ($(CONFIG_LIBCXXTOOLCHAIN),y) + ARCHCXXFLAGS += -nostdinc++ +endif + ARCHCPUFLAGS = -mrtl-version-$(RTL_VERSION) -Wa,-rtl$(RTL_VERSION) ARCHCPUFLAGS += -Wa,-p -mmsg-full-path -TARG:arch=cevaxc5 -Wa,-vdiv4 -Wno-unused diff --git a/arch/ceva/src/xm6/Toolchain.defs b/arch/ceva/src/xm6/Toolchain.defs index 256d4dec3ca19..9bc12639058dc 100644 --- a/arch/ceva/src/xm6/Toolchain.defs +++ b/arch/ceva/src/xm6/Toolchain.defs @@ -65,11 +65,15 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y) endif ARCHCFLAGS += -fno-common -ARCHCXXFLAGS += -fno-common -nostdinc++ +ARCHCXXFLAGS += -fno-common ARCHCFLAGS += -Wall -Wstrict-prototypes -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas ARCHCXXFLAGS += -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas +ifneq ($(CONFIG_LIBCXXTOOLCHAIN),y) + ARCHCXXFLAGS += -nostdinc++ +endif + ARCHCPUFLAGS = -mrtl-version-$(RTL_VERSION) -Wa,-rtl$(RTL_VERSION) ARCHCPUFLAGS += -Wa,-p diff --git a/arch/hc/include/irq.h b/arch/hc/include/irq.h index 01d604548b605..a4736e0b44e13 100644 --- a/arch/hc/include/irq.h +++ b/arch/hc/include/irq.h @@ -91,7 +91,7 @@ static inline uint16_t up_getsp(void) ****************************************************************************/ /* This holds a references to the current interrupt level register storage - * structure. If is non-NULL only during interrupt processing. + * structure. It is non-NULL only during interrupt processing. */ EXTERN volatile uint8_t *g_current_regs; diff --git a/arch/hc/src/Makefile b/arch/hc/src/Makefile index 3d08b1704d547..607b1f72195c6 100644 --- a/arch/hc/src/Makefile +++ b/arch/hc/src/Makefile @@ -18,7 +18,7 @@ # ############################################################################ -include $(TOPDIR)/Make.defs +include $(TOPDIR)/tools/apps-or-nuttx-Make.defs include chip/Make.defs ifeq ($(CONFIG_ARCH_HC12),y) diff --git a/arch/hc/src/common/hc_exit.c b/arch/hc/src/common/hc_exit.c index 447f417cdebb5..7f5c454da2a20 100644 --- a/arch/hc/src/common/hc_exit.c +++ b/arch/hc/src/common/hc_exit.c @@ -60,8 +60,6 @@ void up_exit(int status) enter_critical_section(); - sinfo("TCB=%p exiting\n", tcb); - nxsched_dumponexit(); /* Destroy the task at the head of the ready to run list. */ diff --git a/arch/hc/src/common/hc_getintstack.c b/arch/hc/src/common/hc_getintstack.c index b3d30b2859a04..1264c32ad14fe 100644 --- a/arch/hc/src/common/hc_getintstack.c +++ b/arch/hc/src/common/hc_getintstack.c @@ -37,7 +37,7 @@ ****************************************************************************/ #if CONFIG_ARCH_INTERRUPTSTACK > 3 -uintptr_t up_get_intstackbase(void) +uintptr_t up_get_intstackbase(int cpu) { return (uintptr_t)g_intstackalloc; } diff --git a/arch/mips/src/Makefile b/arch/mips/src/Makefile index 67437f36a7c1d..722e4c272f088 100644 --- a/arch/mips/src/Makefile +++ b/arch/mips/src/Makefile @@ -18,7 +18,7 @@ # ############################################################################ -include $(TOPDIR)/Make.defs +include $(TOPDIR)/tools/apps-or-nuttx-Make.defs include chip/Make.defs ifeq ($(CONFIG_ARCH_MIPS),y) diff --git a/arch/mips/src/common/mips_exit.c b/arch/mips/src/common/mips_exit.c index ff95efca41f86..ea0b36cc983af 100644 --- a/arch/mips/src/common/mips_exit.c +++ b/arch/mips/src/common/mips_exit.c @@ -62,8 +62,6 @@ void up_exit(int status) enter_critical_section(); - sinfo("TCB=%p exiting\n", tcb); - nxsched_dumponexit(); /* Destroy the task at the head of the ready to run list. */ diff --git a/arch/mips/src/common/mips_getintstack.c b/arch/mips/src/common/mips_getintstack.c index 435f36c2a97d0..e019c004524dd 100644 --- a/arch/mips/src/common/mips_getintstack.c +++ b/arch/mips/src/common/mips_getintstack.c @@ -37,7 +37,7 @@ ****************************************************************************/ #if CONFIG_ARCH_INTERRUPTSTACK > 3 -uintptr_t up_get_intstackbase(void) +uintptr_t up_get_intstackbase(int cpu) { return (uintptr_t)g_intstackalloc; } diff --git a/arch/mips/src/mips32/Toolchain.defs b/arch/mips/src/mips32/Toolchain.defs index 9f852c354acc8..92853e588049e 100644 --- a/arch/mips/src/mips32/Toolchain.defs +++ b/arch/mips/src/mips32/Toolchain.defs @@ -260,11 +260,15 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y) endif ARCHCFLAGS += -fno-common -ARCHCXXFLAGS += -fno-common -nostdinc++ +ARCHCXXFLAGS += -fno-common ARCHCFLAGS += -Wall -Wstrict-prototypes -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas ARCHCXXFLAGS += -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas +ifneq ($(CONFIG_LIBCXXTOOLCHAIN),y) + ARCHCXXFLAGS += -nostdinc++ +endif + ifneq ($(CONFIG_CXX_STANDARD),) ARCHCXXFLAGS += -std=$(CONFIG_CXX_STANDARD) endif diff --git a/arch/mips/src/pic32mx/pic32mx_serial.c b/arch/mips/src/pic32mx/pic32mx_serial.c index 24d81d53363b3..1726f628d5432 100644 --- a/arch/mips/src/pic32mx/pic32mx_serial.c +++ b/arch/mips/src/pic32mx/pic32mx_serial.c @@ -305,10 +305,10 @@ static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im) * of bits in im. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); up_rxint(dev, RX_ENABLED(im)); up_txint(dev, TX_ENABLED(im)); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -320,14 +320,14 @@ static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (im) { *im = priv->im; } up_restoreuartint(dev, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/mips/src/pic32mz/pic32mz_serial.c b/arch/mips/src/pic32mz/pic32mz_serial.c index d1db65104e337..8f5353010e20b 100644 --- a/arch/mips/src/pic32mz/pic32mz_serial.c +++ b/arch/mips/src/pic32mz/pic32mz_serial.c @@ -622,10 +622,10 @@ static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im) * in im */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); up_rxint(dev, RX_ENABLED(im)); up_txint(dev, TX_ENABLED(im)); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -637,14 +637,14 @@ static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (im) { *im = priv->im; } up_restoreuartint(dev, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/misoc/include/irq.h b/arch/misoc/include/irq.h index ea5d6f9592b36..d2ebb92f03b28 100644 --- a/arch/misoc/include/irq.h +++ b/arch/misoc/include/irq.h @@ -77,7 +77,7 @@ static inline uint32_t up_getsp(void) ****************************************************************************/ /* This holds a references to the current interrupt level register storage - * structure. If is non-NULL only during interrupt processing. + * structure. It is non-NULL only during interrupt processing. */ EXTERN volatile uint32_t *g_current_regs; diff --git a/arch/misoc/src/Makefile b/arch/misoc/src/Makefile index 172fa55722004..6773d6e8cd226 100644 --- a/arch/misoc/src/Makefile +++ b/arch/misoc/src/Makefile @@ -18,7 +18,7 @@ # ############################################################################ -include $(TOPDIR)/Make.defs +include $(TOPDIR)/tools/apps-or-nuttx-Make.defs include chip/Make.defs ifeq ($(CONFIG_ARCH_CHIP_LM32),y) diff --git a/arch/misoc/src/lm32/Toolchain.defs b/arch/misoc/src/lm32/Toolchain.defs index bde979f0053d8..42772a0d277b3 100644 --- a/arch/misoc/src/lm32/Toolchain.defs +++ b/arch/misoc/src/lm32/Toolchain.defs @@ -1,5 +1,5 @@ ############################################################################ -# arch/misco/src/lm32/Toolchain.defs +# arch/misoc/src/lm32/Toolchain.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with @@ -72,11 +72,15 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y) endif ARCHCFLAGS += -fno-common -ARCHCXXFLAGS += -fno-common -nostdinc++ +ARCHCXXFLAGS += -fno-common ARCHCFLAGS += -Wall -Wstrict-prototypes -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas ARCHCXXFLAGS += -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas +ifneq ($(CONFIG_LIBCXXTOOLCHAIN),y) + ARCHCXXFLAGS += -nostdinc++ +endif + ifneq ($(CONFIG_CXX_STANDARD),) ARCHCXXFLAGS += -std=$(CONFIG_CXX_STANDARD) endif diff --git a/arch/misoc/src/lm32/lm32_exit.c b/arch/misoc/src/lm32/lm32_exit.c index 535186f41674d..455d25dc0d950 100644 --- a/arch/misoc/src/lm32/lm32_exit.c +++ b/arch/misoc/src/lm32/lm32_exit.c @@ -62,8 +62,6 @@ void up_exit(int status) enter_critical_section(); - sinfo("TCB=%p exiting\n", tcb); - nxsched_dumponexit(); /* Destroy the task at the head of the ready to run list. */ diff --git a/arch/misoc/src/minerva/Toolchain.defs b/arch/misoc/src/minerva/Toolchain.defs index 2848a97968916..05ae535e9681c 100644 --- a/arch/misoc/src/minerva/Toolchain.defs +++ b/arch/misoc/src/minerva/Toolchain.defs @@ -44,7 +44,7 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y) endif ARCHCFLAGS += -fno-common -ARCHCXXFLAGS += -fno-common -nostdinc++ +ARCHCXXFLAGS += -fno-common ARCHCFLAGS += -Wall -Wstrict-prototypes -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas ARCHCXXFLAGS += -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas @@ -65,6 +65,10 @@ OBJDUMP = $(CROSSDEV)objdump EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-libgcc-file-name)) +ifneq ($(CONFIG_LIBCXXTOOLCHAIN),y) + ARCHCXXFLAGS += -nostdinc++ +endif + ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a)) endif diff --git a/arch/misoc/src/minerva/minerva_exit.c b/arch/misoc/src/minerva/minerva_exit.c index 36f771839d671..f3d6c17898018 100644 --- a/arch/misoc/src/minerva/minerva_exit.c +++ b/arch/misoc/src/minerva/minerva_exit.c @@ -62,8 +62,6 @@ void up_exit(int status) enter_critical_section(); - sinfo("TCB=%p exiting\n", tcb); - nxsched_dumponexit(); /* Destroy the task at the head of the ready to run list. */ diff --git a/arch/or1k/include/irq.h b/arch/or1k/include/irq.h index 11b0857cdfd91..8a22a21039f6d 100644 --- a/arch/or1k/include/irq.h +++ b/arch/or1k/include/irq.h @@ -75,7 +75,7 @@ extern "C" #endif /* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt + * register storage structure. It is non-NULL only during interrupt * processing. Access to g_current_regs[] must be through the macro * CURRENT_REGS for portability. */ diff --git a/arch/or1k/src/Makefile b/arch/or1k/src/Makefile index d0210d1a15903..48fcd3ff5ee2b 100644 --- a/arch/or1k/src/Makefile +++ b/arch/or1k/src/Makefile @@ -18,7 +18,7 @@ # ############################################################################ -include $(TOPDIR)/Make.defs +include $(TOPDIR)/tools/apps-or-nuttx-Make.defs include chip/Make.defs ifeq ($(CONFIG_ARCH_MOR1KX),y) # OpenRISC mor1kx diff --git a/arch/or1k/src/common/or1k_checkstack.c b/arch/or1k/src/common/or1k_checkstack.c index e4cde1a9d3e9e..c317d5d039707 100644 --- a/arch/or1k/src/common/or1k_checkstack.c +++ b/arch/or1k/src/common/or1k_checkstack.c @@ -120,7 +120,7 @@ size_t up_check_tcbstack(struct tcb_s *tcb) } #if CONFIG_ARCH_INTERRUPTSTACK > 3 -size_t up_check_intstack(void) +size_t up_check_intstack(int cpu) { return or1k_stack_check((uintptr_t)g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3)); diff --git a/arch/or1k/src/common/or1k_exit.c b/arch/or1k/src/common/or1k_exit.c index a5360b6570db0..eef1a01c302c8 100644 --- a/arch/or1k/src/common/or1k_exit.c +++ b/arch/or1k/src/common/or1k_exit.c @@ -62,8 +62,6 @@ void up_exit(int status) enter_critical_section(); - sinfo("TCB=%p exiting\n", tcb); - nxsched_dumponexit(); /* Destroy the task at the head of the ready to run list. */ diff --git a/arch/or1k/src/common/or1k_getintstack.c b/arch/or1k/src/common/or1k_getintstack.c index dcfcf16075fb9..b202eeaa418b6 100644 --- a/arch/or1k/src/common/or1k_getintstack.c +++ b/arch/or1k/src/common/or1k_getintstack.c @@ -37,7 +37,7 @@ ****************************************************************************/ #if CONFIG_ARCH_INTERRUPTSTACK > 3 -uintptr_t up_get_intstackbase(void) +uintptr_t up_get_intstackbase(int cpu) { return (uintptr_t)g_intstackalloc; } diff --git a/arch/or1k/src/mor1kx/Toolchain.defs b/arch/or1k/src/mor1kx/Toolchain.defs index e048f11583278..eb49f87d56fcd 100644 --- a/arch/or1k/src/mor1kx/Toolchain.defs +++ b/arch/or1k/src/mor1kx/Toolchain.defs @@ -55,11 +55,15 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y) endif ARCHCFLAGS += -fno-common -ARCHCXXFLAGS += -fno-common -nostdinc++ +ARCHCXXFLAGS += -fno-common ARCHCFLAGS += -Wall -Wstrict-prototypes -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas ARCHCXXFLAGS += -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas +ifneq ($(CONFIG_LIBCXXTOOLCHAIN),y) + ARCHCXXFLAGS += -nostdinc++ +endif + ifneq ($(CONFIG_CXX_STANDARD),) ARCHCXXFLAGS += -std=$(CONFIG_CXX_STANDARD) endif diff --git a/arch/or1k/src/mor1kx/mor1kx_serial.c b/arch/or1k/src/mor1kx/mor1kx_serial.c index e57a54ce68300..0bebdcdec3c6f 100644 --- a/arch/or1k/src/mor1kx/mor1kx_serial.c +++ b/arch/or1k/src/mor1kx/mor1kx_serial.c @@ -115,7 +115,7 @@ int up_putc(int ch) * interrupts from firing in the serial driver code. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); /* Check for LF */ @@ -128,7 +128,7 @@ int up_putc(int ch) /* or1k_lowputc(ch); */ - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); #endif return ch; } diff --git a/arch/renesas/include/irq.h b/arch/renesas/include/irq.h index c0c2c919bac78..a85c534abbb30 100644 --- a/arch/renesas/include/irq.h +++ b/arch/renesas/include/irq.h @@ -59,7 +59,7 @@ extern "C" ****************************************************************************/ /* This holds a references to the current interrupt level - * register storage structure. If is non-NULL only during + * register storage structure. It is non-NULL only during * interrupt processing. */ diff --git a/arch/renesas/src/Makefile b/arch/renesas/src/Makefile index 4f7501986e7a3..13cbc84940a16 100644 --- a/arch/renesas/src/Makefile +++ b/arch/renesas/src/Makefile @@ -18,7 +18,7 @@ # ############################################################################ -include $(TOPDIR)/Make.defs +include $(TOPDIR)/tools/apps-or-nuttx-Make.defs include chip/Make.defs ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src diff --git a/arch/renesas/src/common/renesas_exit.c b/arch/renesas/src/common/renesas_exit.c index 35e16d1d981fb..27abbdd009a8d 100644 --- a/arch/renesas/src/common/renesas_exit.c +++ b/arch/renesas/src/common/renesas_exit.c @@ -60,8 +60,6 @@ void up_exit(int status) enter_critical_section(); - sinfo("TCB=%p exiting\n", tcb); - nxsched_dumponexit(); /* Destroy the task at the head of the ready to run list. */ diff --git a/arch/renesas/src/common/renesas_getintstack.c b/arch/renesas/src/common/renesas_getintstack.c index 0e384a588cc6a..a7e4f8219de6d 100644 --- a/arch/renesas/src/common/renesas_getintstack.c +++ b/arch/renesas/src/common/renesas_getintstack.c @@ -37,7 +37,7 @@ ****************************************************************************/ #if CONFIG_ARCH_INTERRUPTSTACK > 3 -uintptr_t up_get_intstackbase(void) +uintptr_t up_get_intstackbase(int cpu) { return (uintptr_t)g_intstackalloc; } diff --git a/arch/renesas/src/common/renesas_initialize.c b/arch/renesas/src/common/renesas_initialize.c index de395e4e4b176..6f531076e9442 100644 --- a/arch/renesas/src/common/renesas_initialize.c +++ b/arch/renesas/src/common/renesas_initialize.c @@ -33,7 +33,7 @@ ****************************************************************************/ /* This holds a references to the current interrupt level register storage - * structure. If is non-NULL only during interrupt processing. + * structure. It is non-NULL only during interrupt processing. */ /* Actually a pointer to the beginning of a uint8_t array */ diff --git a/arch/risc-v/Kconfig b/arch/risc-v/Kconfig index f521a14fb5abf..428768b320711 100644 --- a/arch/risc-v/Kconfig +++ b/arch/risc-v/Kconfig @@ -46,6 +46,8 @@ config ARCH_CHIP_LITEX select ARCH_DCACHE select ARCH_HAVE_TICKLESS select ARCH_HAVE_RESET + select LIBC_FDT + select DEVICE_TREE ---help--- Enjoy Digital LITEX VEXRISCV softcore processor (RV32IMA). @@ -90,14 +92,47 @@ config ARCH_CHIP_ESP32C3 ---help--- Espressif ESP32-C3 (RV32IMC). +config ARCH_CHIP_ESP32C3_GENERIC + bool "ESP32-C3" + select ARCH_RV32 + select ARCH_RV_ISA_M + select ARCH_RV_ISA_C + select ARCH_VECNOTIRQ + select ARCH_HAVE_BOOTLOADER if !ESPRESSIF_SIMPLE_BOOT + select ARCH_HAVE_MPU + select ARCH_HAVE_RESET + select ARCH_HAVE_RNG + select ARCH_HAVE_TICKLESS + select LIBC_ARCH_ATOMIC + select LIBC_ARCH_MEMCPY + select LIBC_ARCH_MEMCHR + select LIBC_ARCH_MEMCMP + select LIBC_ARCH_MEMMOVE + select LIBC_ARCH_MEMSET + select LIBC_ARCH_STRCHR + select LIBC_ARCH_STRCMP + select LIBC_ARCH_STRCPY + select LIBC_ARCH_STRLCPY + select LIBC_ARCH_STRNCPY + select LIBC_ARCH_STRLEN + select LIBC_ARCH_STRNLEN + select ESPRESSIF_SOC_RTC_MEM_SUPPORTED + select ARCH_CHIP_ESPRESSIF + ---help--- + ESP32-C3 chip with a single RISC-V IMC core, no embedded Flash memory + config ARCH_CHIP_ESP32C6 - bool "Espressif ESP32-C6" + bool "ESP32-C6" select ARCH_RV32 select ARCH_RV_ISA_M select ARCH_RV_ISA_A select ARCH_RV_ISA_C select ARCH_VECNOTIRQ + select ARCH_HAVE_BOOTLOADER if !ESPRESSIF_SIMPLE_BOOT + select ARCH_HAVE_MPU select ARCH_HAVE_RESET + select ARCH_HAVE_RNG + select ARCH_HAVE_TICKLESS select LIBC_ARCH_MEMCPY select LIBC_ARCH_MEMCHR select LIBC_ARCH_MEMCMP @@ -110,13 +145,40 @@ config ARCH_CHIP_ESP32C6 select LIBC_ARCH_STRNCPY select LIBC_ARCH_STRLEN select LIBC_ARCH_STRNLEN + select ESPRESSIF_SOC_RTC_MEM_SUPPORTED + select ARCH_CHIP_ESPRESSIF ---help--- Espressif ESP32-C6 (RV32IMAC). -config ARCH_CHIP_ESPRESSIF - bool "Espressif ESP32 family" +config ARCH_CHIP_ESP32H2 + bool "ESP32-H2" + select ARCH_RV32 + select ARCH_RV_ISA_M + select ARCH_RV_ISA_C + select ARCH_VECNOTIRQ + select ARCH_HAVE_BOOTLOADER if !ESPRESSIF_SIMPLE_BOOT + select ARCH_HAVE_MPU + select ARCH_HAVE_RESET + select ARCH_HAVE_RNG + select ARCH_HAVE_TICKLESS + select LIBC_ARCH_ATOMIC + select LIBC_ARCH_MEMCPY + select LIBC_ARCH_MEMCHR + select LIBC_ARCH_MEMCMP + select LIBC_ARCH_MEMMOVE + select LIBC_ARCH_MEMSET + select LIBC_ARCH_STRCHR + select LIBC_ARCH_STRCMP + select LIBC_ARCH_STRCPY + select LIBC_ARCH_STRLCPY + select LIBC_ARCH_STRNCPY + select LIBC_ARCH_STRLEN + select LIBC_ARCH_STRNLEN + select ESPRESSIF_ESPTOOLPY_NO_STUB + select ESPRESSIF_SOC_RTC_MEM_SUPPORTED + select ARCH_CHIP_ESPRESSIF ---help--- - Family of RISC-V based microcontrollers from Espressif Systems. + Espressif ESP32-H2 (RV32IMC). config ARCH_CHIP_C906 bool "THEAD C906" @@ -141,7 +203,6 @@ config ARCH_CHIP_MPFS select ARCH_HAVE_FPU select ARCH_HAVE_DPFPU select ARCH_HAVE_MPU - select ARCH_HAVE_MMU select ARCH_MMU_TYPE_SV39 select ARCH_HAVE_ADDRENV select ARCH_NEED_ADDRENV_MAPPING @@ -168,17 +229,28 @@ config ARCH_CHIP_QEMU_RV select ARCH_HAVE_DPFPU select ARCH_HAVE_MULTICPU select ARCH_HAVE_MPU - select ARCH_HAVE_MMU select ARCH_MMU_TYPE_SV39 if ARCH_CHIP_QEMU_RV64 select ARCH_MMU_TYPE_SV32 if ARCH_CHIP_QEMU_RV32 select ARCH_HAVE_ADDRENV select ARCH_NEED_ADDRENV_MAPPING select ARCH_HAVE_S_MODE + select ARCH_HAVE_ELF_EXECUTABLE select ONESHOT select ALARM_ARCH ---help--- QEMU Generic RV32/RV64 processor +config ARCH_CHIP_HPM6000 + bool "Hpmicro HPM6000" + select ARCH_RV32 + select ARCH_RV_ISA_M + select ARCH_RV_ISA_A + select ARCH_RV_ISA_C + select ONESHOT + select ALARM_ARCH + ---help--- + Hpmicro HPM6000 processor (D45 RISC-V Core with MAC extensions). + config ARCH_CHIP_HPM6750 bool "Hpmicro HPM6750" select ARCH_RV32 @@ -200,7 +272,6 @@ config ARCH_CHIP_JH7110 select ARCH_HAVE_DPFPU select ARCH_HAVE_MULTICPU select ARCH_HAVE_MPU - select ARCH_HAVE_MMU select ARCH_MMU_TYPE_SV39 select ARCH_HAVE_ADDRENV select ARCH_NEED_ADDRENV_MAPPING @@ -220,7 +291,6 @@ config ARCH_CHIP_BL808 select ARCH_HAVE_DPFPU select ARCH_HAVE_MULTICPU select ARCH_HAVE_MPU - select ARCH_HAVE_MMU select ARCH_MMU_TYPE_SV39 select ARCH_HAVE_ADDRENV select ARCH_NEED_ADDRENV_MAPPING @@ -240,24 +310,25 @@ config ARCH_CHIP_K230 select ARCH_HAVE_DPFPU select ARCH_HAVE_MISALIGN_EXCEPTION select ARCH_HAVE_MPU - select ARCH_HAVE_MMU - select ARCH_MMU_TYPE_SV39 select ARCH_HAVE_ADDRENV - select ARCH_NEED_ADDRENV_MAPPING + select ARCH_HAVE_RESET select ARCH_HAVE_S_MODE + select ARCH_HAVE_ELF_EXECUTABLE + select ARCH_MMU_TYPE_SV39 + select ARCH_NEED_ADDRENV_MAPPING + select NUTTSBI_LATE_INIT if NUTTSBI select ONESHOT select ALARM_ARCH ---help--- Kendryte K230 SoC (RV64GCV and RV64GCVX C908 cores). - config ARCH_CHIP_RISCV_CUSTOM bool "Custom RISC-V chip" select ARCH_CHIP_CUSTOM ---help--- Select this option if there is no directory for the chip under arch/risc-v/src/. -endchoice +endchoice # RISC-V chip selection config ARCH_RV32 bool @@ -281,36 +352,101 @@ config ARCH_RV_ISA_C bool default n +config ARCH_RV_ISA_V + bool + default n + depends on ARCH_FPU + +if ARCH_RV_ISA_V + +config ARCH_RV_VECTOR_BYTE_LENGTH + int "Vector Register Length in bytes" + default 32 + ---help--- + Predefined vector register length. If CSR vlenb is greater than the + current reserved value, appropriate memory will be allocated to + save/restore the vector registers. + The XLEN-bit-wide read-only CSR vlenb holds the value VLEN/8, i.e., + the vector register length in bytes. The value in vlenb is a + design-time constant in any implementation. Without this CSR, several + instructions are needed to calculate VLEN in bytes. The code has to + disturb current vl and vtype settings which require them to be saved and restored. + +endif + +config ARCH_RV_ISA_ZICSR_ZIFENCEI + bool + default y + ---help--- + https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=aed44286efa8ae8717a77d94b51ac3614e2ca6dc + https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=98416dbb0a62579d4a7a4a76bab51b5b52fec2cd + GCC-12.1.0 bumped the default ISA spec to the newer 20191213 version, + which moves some instructions from the I extension to the Zicsr and + Zifencei extensions. This requires explicitly specifying Zicsr and + Zifencei when GCC >= 12.1.0. To make life easier, and avoid forcing + toolchains that default to a newer ISA spec to version 2.2. For + clang < 17 or GCC < 11.3.0, for which this is not possible or need + special treatment. + +config ARCH_RV_EXPERIMENTAL_EXTENSIONS + string "LLVM RISC-V Experimental Extensions" + default "" + depends on RISCV_TOOLCHAIN_CLANG + ---help--- + This option allows the platform to enable experimental extensions, + LLVM supports (to various degrees) a number of experimental extensions. + All experimental extensions have experimental- as a prefix. There is + explicitly no compatibility promised between versions of the toolchain, + and regular users are strongly advised not to make use of experimental + extensions before they reach ratification. + +config ARCH_RV_ISA_VENDOR_EXTENSIONS + string "Vendor Custom RISC-V Instruction Set Architecture Extensions" + default "" + ---help--- + This option allows the platform to enable some vendor-customized ISA extensions, + E.g OpenHW, SiFive, T-Head. + + SiFive Intelligence Extensions: + SiFive Vector Coprocessor Interface(VCIX): xsfvcp + SiFive FP32-to-int8 Ranged Clip Instructions: Xsfvfnrclipxfqf + SiFive Matrix Multiply Accumulate Instructions: Xsfvfwmaccqqq + SiFive Int8 Matrix Multiplication Instructions: XSFvqmaccqoq + Command Line: + xsfvcp0p1_xsfvfnrclipxfqf0p1_xsfvfwmaccqqq0p1_xsfvqmaccqoq0p1 + config ARCH_RV_MMIO_BITS int # special cases - default 32 if ARCH_CHIP_K230 + default 32 if ARCH_CHIP_K230 # general fallbacks - default 32 if ARCH_RV32 - default 64 if ARCH_RV64 + default 32 if ARCH_RV32 + default 64 if ARCH_RV64 config ARCH_FAMILY string - default "rv32" if ARCH_RV32 - default "rv64" if ARCH_RV64 + default "rv32" if ARCH_RV32 + default "rv64" if ARCH_RV64 config ARCH_CHIP string - default "fe310" if ARCH_CHIP_FE310 - default "k210" if ARCH_CHIP_K210 - default "litex" if ARCH_CHIP_LITEX - default "bl602" if ARCH_CHIP_BL602 - default "esp32c3" if ARCH_CHIP_ESP32C3 - default "esp32c6" if ARCH_CHIP_ESP32C6 - default "espressif" if ARCH_CHIP_ESPRESSIF - default "c906" if ARCH_CHIP_C906 - default "mpfs" if ARCH_CHIP_MPFS - default "rv32m1" if ARCH_CHIP_RV32M1 - default "qemu-rv" if ARCH_CHIP_QEMU_RV - default "hpm6750" if ARCH_CHIP_HPM6750 - default "jh7110" if ARCH_CHIP_JH7110 - default "bl808" if ARCH_CHIP_BL808 - default "k230" if ARCH_CHIP_K230 + default "fe310" if ARCH_CHIP_FE310 + default "k210" if ARCH_CHIP_K210 + default "litex" if ARCH_CHIP_LITEX + default "bl602" if ARCH_CHIP_BL602 + default "esp32c3-legacy" if ARCH_CHIP_ESP32C3 + default "esp32c3" if ARCH_CHIP_ESP32C3_GENERIC + default "esp32c6" if ARCH_CHIP_ESP32C6 + default "esp32h2" if ARCH_CHIP_ESP32H2 + default "c906" if ARCH_CHIP_C906 + default "mpfs" if ARCH_CHIP_MPFS + default "rv32m1" if ARCH_CHIP_RV32M1 + default "qemu-rv" if ARCH_CHIP_QEMU_RV + default "hpm6000" if ARCH_CHIP_HPM6000 + default "hpm6750" if ARCH_CHIP_HPM6750 + default "jh7110" if ARCH_CHIP_JH7110 + default "bl808" if ARCH_CHIP_BL808 + default "k230" if ARCH_CHIP_K230 config ARCH_RISCV_INTXCPT_EXTENSIONS bool "RISC-V Integer Context Extensions" @@ -331,10 +467,12 @@ endif config ARCH_MMU_TYPE_SV39 bool default n + select ARCH_HAVE_MMU config ARCH_MMU_TYPE_SV32 bool default n + select ARCH_HAVE_MMU config ARCH_HAVE_S_MODE bool @@ -351,6 +489,16 @@ config RISCV_MISALIGNED_HANDLER depends on ARCH_HAVE_MISALIGN_EXCEPTION default y +config RISCV_PERCPU_SCRATCH + bool "Enable Scratch-based Per-CPU storage" + default n + ---help--- + In some special chipsets, multiple CPUs may be bundled in one hardware + thread cluster, which results in hartid and cpuindex not being exactly + the same. + This option will enable Scratch-based Per-CPU storage to distinguish + the real cpu index. + # Option to run NuttX in supervisor mode. This is obviously not usable in # flat mode, is questionable in protected mode, but is mandatory in kernel # mode. @@ -366,11 +514,17 @@ config ARCH_USE_S_MODE bool "Run the NuttX kernel in S-mode" default n depends on ARCH_HAVE_S_MODE && BUILD_KERNEL && ARCH_USE_MMU + select RISCV_PERCPU_SCRATCH ---help--- Most of the RISC-V implementations run in M-mode (flat addressing) and/or U-mode (in case of separate kernel-/userspaces). This provides an option to run the kernel in S-mode, if the target supports it. +config ARCH_RV_EXT_SSTC + bool "Enable RISC-V SSTC extension support" + default n + depends on ARCH_USE_S_MODE + choice prompt "Toolchain Selection" default RISCV_TOOLCHAIN_GNU_RV64 @@ -389,7 +543,11 @@ config RISCV_TOOLCHAIN_GNU_RV32 This option should work for any modern GNU toolchain (GCC 5.2 or newer) configured for riscv32-unknown-elf. -endchoice +config RISCV_TOOLCHAIN_CLANG + bool "LLVM Clang toolchain" + select ARCH_TOOLCHAIN_CLANG + +endchoice # Toolchain Selection config RISCV_SEMIHOSTING_HOSTFS bool "Semihosting HostFS" @@ -408,7 +566,7 @@ config RISCV_SEMIHOSTING_HOSTFS_CACHE_COHERENCE ---help--- Flush & Invalidte cache before & after bkpt instruction. -endif +endif # RISCV_SEMIHOSTING_HOSTFS if ARCH_CHIP_LITEX @@ -422,7 +580,6 @@ config LITEX_CORE_VEXRISCV config LITEX_CORE_VEXRISCV_SMP bool "vexriscv_smp core" select ARCH_HAVE_MPU - select ARCH_HAVE_MMU select ARCH_RV_ISA_C select ARCH_MMU_TYPE_SV32 select ARCH_HAVE_ADDRENV @@ -430,9 +587,9 @@ config LITEX_CORE_VEXRISCV_SMP select ARCH_HAVE_S_MODE select ARCH_HAVE_ELF_EXECUTABLE -endchoice +endchoice # LITEX Core Selection -endif +endif # ARCH_CHIP_LITEX source "arch/risc-v/src/opensbi/Kconfig" source "arch/risc-v/src/nuttsbi/Kconfig" @@ -450,13 +607,16 @@ if ARCH_CHIP_BL602 source "arch/risc-v/src/bl602/Kconfig" endif if ARCH_CHIP_ESP32C3 +source "arch/risc-v/src/esp32c3-legacy/Kconfig" +endif +if ARCH_CHIP_ESP32C3_GENERIC source "arch/risc-v/src/esp32c3/Kconfig" endif if ARCH_CHIP_ESP32C6 source "arch/risc-v/src/esp32c6/Kconfig" endif -if ARCH_CHIP_ESPRESSIF -source "arch/risc-v/src/espressif/Kconfig" +if ARCH_CHIP_ESP32H2 +source "arch/risc-v/src/esp32h2/Kconfig" endif if ARCH_CHIP_C906 source "arch/risc-v/src/c906/Kconfig" @@ -470,6 +630,9 @@ endif if ARCH_CHIP_QEMU_RV source "arch/risc-v/src/qemu-rv/Kconfig" endif +if ARCH_CHIP_HPM6000 +source "arch/risc-v/src/hpm6000/Kconfig" +endif if ARCH_CHIP_HPM6750 source "arch/risc-v/src/hpm6750/Kconfig" endif @@ -482,4 +645,4 @@ endif if ARCH_CHIP_K230 source "arch/risc-v/src/k230/Kconfig" endif -endif +endif # ARCH_RISCV diff --git a/arch/risc-v/include/arch.h b/arch/risc-v/include/arch.h index 6425a897f441d..c885e03118866 100644 --- a/arch/risc-v/include/arch.h +++ b/arch/risc-v/include/arch.h @@ -64,8 +64,9 @@ /* A task group must have its L1 table in memory always, and the rest can * be dynamically committed to memory (and even swapped). * - * In this implementation every level tables besides the final level N are - * kept in memory always, while the level N tables are dynamically allocated. + * In this implementation level tables except the final level N are always + * kept in static memory, while the level N tables are always dynamically + * allocated. There is one static page per level in `spgtables[]`. * * The implications ? They depend on the MMU type. * diff --git a/arch/risc-v/include/csr.h b/arch/risc-v/include/csr.h index e719b2a29f996..01506883c0d18 100644 --- a/arch/risc-v/include/csr.h +++ b/arch/risc-v/include/csr.h @@ -135,10 +135,19 @@ #define CSR_STVAL 0x143 #define CSR_SIP 0x144 +/* Supervisor Environment Configuration Registers */ + +#define CSR_SENVCFG 0x10a + /* Supervisor Protection and Translation Registers */ #define CSR_SATP 0x180 +/* Supervisor Time Registers */ + +#define CSR_STIMECMP 0x14d +#define CSR_STIMECMPH 0x15d + /* Machine Information Registers */ #define CSR_MVENDORID 0xf11 @@ -164,6 +173,11 @@ #define CSR_MTVAL 0x343 #define CSR_MIP 0x344 +/* Machine Environment Configuration Registers */ + +#define CSR_MENVCFG 0x30a +#define CSR_MENVCFGH 0x31a + /* Machine Protection and Translation */ #define CSR_PMPCFG0 0x3a0 @@ -286,16 +300,33 @@ /* Debug/Trace Registers */ -#define CSR_TSELECT 0x7a0 -#define CSR_TDATA1 0x7a1 -#define CSR_TDATA2 0x7a2 -#define CSR_TDATA3 0x7a3 +#define CSR_TSELECT 0x7a0 /* Trigger Select */ +#define CSR_TDATA1 0x7a1 /* Trigger Data 1 */ +#define CSR_TDATA2 0x7a2 /* Trigger Data 2 */ +#define CSR_TDATA3 0x7a3 /* Trigger Data 3 */ +#define CSR_TINFO 0x7a4 /* Trigger Info */ +#define CSR_TCONTROL 0x7a5 /* Trigger Control */ +#define CSR_MCONTEXT 0x7a8 /* Machine Context */ +#define CSR_MSCONTEXT 0x7aa /* Machine Supervisor Context */ +#define CSR_SCONTEXT 0x5a8 /* Supervisor Context */ +#define CSR_HCONTEXT 0x5aa /* Hypervisor Context */ /* Debug interface CSRs */ -#define CSR_DCSR 0x7b0 -#define CSR_DPC 0x7b1 -#define CSR_DSCRATCH 0x7b2 +#define CSR_DCSR 0x7b0 /* Debug Control and Status */ +#define CSR_DPC 0x7b1 /* Debug PC */ +#define CSR_DSCRATCH0 0x7b2 /* Debug Scratch 0 */ +#define CSR_DSCRATCH1 0x7b3 /* Debug Scratch 1 */ + +/* Vector CSRs */ + +#define CSR_VSTART 0x008 /* Vector Start Position */ +#define CSR_VXSAT 0x009 /* Fixed-Point Saturate Flag */ +#define CSR_VXRM 0x00a /* Fixed-Point Rounding Mode */ +#define CSR_VCSR 0x00f /* Vector Control and Status */ +#define CSR_VL 0xc20 /* Vector Length */ +#define CSR_VTYPE 0xc21 /* Vector Data Type */ +#define CSR_VLENB 0xc22 /* Vector Length in Bytes (VLEN/8) */ /* In mstatus register */ @@ -306,6 +337,10 @@ #define MSTATUS_MPIE (0x1 << 7) /* Machine Previous Interrupt Enable */ #define MSTATUS_SPPU (0x0 << 8) /* Supervisor Previous Privilege (u-mode) */ #define MSTATUS_SPPS (0x1 << 8) /* Supervisor Previous Privilege (s-mode) */ +#define MSTATUS_VS (0x3 << 9) /* Machine Vector-extension Status */ +#define MSTATUS_VS_INIT (0x1 << 9) +#define MSTATUS_VS_CLEAN (0x2 << 9) +#define MSTATUS_VS_DIRTY (0x3 << 9) #define MSTATUS_MPPU (0x0 << 11) /* Machine Previous Privilege (u-mode) */ #define MSTATUS_MPPS (0x1 << 11) /* Machine Previous Privilege (s-mode) */ #define MSTATUS_MPPM (0x3 << 11) /* Machine Previous Privilege (m-mode) */ @@ -314,6 +349,10 @@ #define MSTATUS_FS_INIT (0x1 << 13) #define MSTATUS_FS_CLEAN (0x2 << 13) #define MSTATUS_FS_DIRTY (0x3 << 13) +#define MSTATUS_XS (0x3 << 15) /* Machine additional-extension Status */ +#define MSTATUS_XS_INIT (0x1 << 15) +#define MSTATUS_XS_CLEAN (0x2 << 15) +#define MSTATUS_XS_DIRTY (0x3 << 15) #define MSTATUS_MPRV (0x1 << 17) /* Modify Privilege */ #define MSTATUS_SUM (0x1 << 18) /* S mode access to U mode memory */ #define MSTATUS_MXR (0x1 << 19) /* Make executable / readable */ @@ -329,6 +368,23 @@ #define MSTATUS_WPRI (UINT64_C(0x1ffffff) << 38 | UINT64_C(0x1ff) << 23 | 0x15) #endif +/* In menvcfg register */ +#define MENVCFG_FIOM (0x1 << 0) +#define MENVCFG_CBIE (0x3 << 4) +#define MENVCFG_CBIE_ILL (0x0 << 4) +#define MENVCFG_CBIE_FLUSH (0x1 << 4) +#define MENVCFG_CBIE_INV (0x3 << 4) +#define MENVCFG_CBCFE (0x1 << 6) +#define MENVCFG_CBZE (0x1 << 7) + +#ifdef CONFIG_ARCH_RV32 +#define MENVCFG_PBMTE (0x1 << 30) +#define MENVCFG_STCE (0x1 << 31) +#else +#define MENVCFG_PBMTE (UINT64_C(0x1) << 62) +#define MENVCFG_STCE (UINT64_C(0x1) << 63) +#endif + /* In mie (machine interrupt enable) register */ #define MIE_SSIE (0x1 << 1) /* Supervisor Software Interrupt Enable */ @@ -341,9 +397,11 @@ /* In mip (machine interrupt pending) register */ #define MIP_SSIP (0x1 << 1) +#define MIP_MSIP (0x1 << 3) #define MIP_STIP (0x1 << 5) #define MIP_MTIP (0x1 << 7) #define MIP_SEIP (0x1 << 9) +#define MIP_MEIP (0x1 << 11) /* In sstatus register (which is a view of mstatus) */ @@ -351,10 +409,18 @@ #define SSTATUS_SPIE MSTATUS_SPIE #define SSTATUS_SPPU MSTATUS_SPPU #define SSTATUS_SPPS MSTATUS_SPPS +#define SSTATUS_VS MSTATUS_VS +#define SSTATUS_VS_INIT MSTATUS_VS_INIT +#define SSTATUS_VS_CLEAN MSTATUS_VS_CLEAN +#define SSTATUS_VS_DIRTY MSTATUS_VS_DIRTY #define SSTATUS_FS MSTATUS_FS #define SSTATUS_FS_INIT MSTATUS_FS_INIT #define SSTATUS_FS_CLEAN MSTATUS_FS_CLEAN #define SSTATUS_FS_DIRTY MSTATUS_FS_DIRTY +#define SSTATUS_XS MSTATUS_XS +#define SSTATUS_XS_INIT MSTATUS_XS_INIT +#define SSTATUS_XS_CLEAN MSTATUS_XS_CLEAN +#define SSTATUS_XS_DIRTY MSTATUS_XS_DIRTY #define SSTATUS_SUM MSTATUS_SUM #define SSTATUS_MXR MSTATUS_MXR @@ -370,6 +436,15 @@ #define SIP_STIP MIP_STIP #define SIP_SEIP MIP_SEIP +/* In senvcfg register */ +#define SENVCFG_FIOM MENVCFG_FIOM +#define SENVCFG_CBIE MENVCFG_CBIE +#define SENVCFG_CBIE_ILL MENVCFG_CBIE_ILL +#define SENVCFG_CBIE_FLUSH MENVCFG_CBIE_FLUSH +#define SENVCFG_CBIE_INV MENVCFG_CBIE_INV +#define SENVCFG_CBCFE MENVCFG_CBCFE +#define SENVCFG_CBZE MENVCFG_CBZE + /* In pmpcfg (PMP configuration) register */ #define PMPCFG_R (1 << 0) /* readable ? */ @@ -383,6 +458,40 @@ #define PMPCFG_A_MASK (3 << 3) /* address-matching mode mask */ #define PMPCFG_L (1 << 7) /* locked ? */ +/* In mcounteren/scounteren register */ +#define COUNTEREN_CY (0x1 << 0) +#define COUNTEREN_TM (0x1 << 1) +#define COUNTEREN_IR (0x1 << 2) +#define COUNTEREN_HPM3 (0x1 << 3) +#define COUNTEREN_HPM4 (0x1 << 4) +#define COUNTEREN_HPM5 (0x1 << 5) +#define COUNTEREN_HPM6 (0x1 << 6) +#define COUNTEREN_HPM7 (0x1 << 7) +#define COUNTEREN_HPM8 (0x1 << 8) +#define COUNTEREN_HPM9 (0x1 << 9) +#define COUNTEREN_HPM10 (0x1 << 10) +#define COUNTEREN_HPM11 (0x1 << 11) +#define COUNTEREN_HPM12 (0x1 << 12) +#define COUNTEREN_HPM13 (0x1 << 13) +#define COUNTEREN_HPM14 (0x1 << 14) +#define COUNTEREN_HPM15 (0x1 << 15) +#define COUNTEREN_HPM16 (0x1 << 16) +#define COUNTEREN_HPM17 (0x1 << 17) +#define COUNTEREN_HPM18 (0x1 << 18) +#define COUNTEREN_HPM19 (0x1 << 19) +#define COUNTEREN_HPM20 (0x1 << 20) +#define COUNTEREN_HPM21 (0x1 << 21) +#define COUNTEREN_HPM22 (0x1 << 22) +#define COUNTEREN_HPM23 (0x1 << 23) +#define COUNTEREN_HPM24 (0x1 << 24) +#define COUNTEREN_HPM25 (0x1 << 25) +#define COUNTEREN_HPM26 (0x1 << 26) +#define COUNTEREN_HPM27 (0x1 << 27) +#define COUNTEREN_HPM28 (0x1 << 28) +#define COUNTEREN_HPM29 (0x1 << 29) +#define COUNTEREN_HPM30 (0x1 << 30) +#define COUNTEREN_HPM31 (0x1 << 31) + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/risc-v/include/esp32c3-legacy/chip.h b/arch/risc-v/include/esp32c3-legacy/chip.h new file mode 100644 index 0000000000000..58a0a7f3a6cdb --- /dev/null +++ b/arch/risc-v/include/esp32c3-legacy/chip.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/risc-v/include/esp32c3-legacy/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_ESP32C3_LEGACY_CHIP_H +#define __ARCH_RISCV_INCLUDE_ESP32C3_LEGACY_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Characterize each supported ESP32-C3 part */ + +#define ESP32C3_NGPIOS 22 /* GPIO0-21 */ + +#endif /* __ARCH_RISCV_INCLUDE_ESP32C3_LEGACY_CHIP_H */ diff --git a/arch/risc-v/include/esp32c3/esp_efuse_table.h b/arch/risc-v/include/esp32c3-legacy/esp_efuse_table.h similarity index 99% rename from arch/risc-v/include/esp32c3/esp_efuse_table.h rename to arch/risc-v/include/esp32c3-legacy/esp_efuse_table.h index a8a7d5d69e8fc..960f68766015a 100644 --- a/arch/risc-v/include/esp32c3/esp_efuse_table.h +++ b/arch/risc-v/include/esp32c3-legacy/esp_efuse_table.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/include/esp32c3/esp_efuse_table.h + * arch/risc-v/include/esp32c3-legacy/esp_efuse_table.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/include/esp32c3-legacy/irq.h b/arch/risc-v/include/esp32c3-legacy/irq.h new file mode 100644 index 0000000000000..c05200fb8be68 --- /dev/null +++ b/arch/risc-v/include/esp32c3-legacy/irq.h @@ -0,0 +1,241 @@ +/**************************************************************************** + * arch/risc-v/include/esp32c3-legacy/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_ESP32C3_IRQ_H +#define __ARCH_RISCV_INCLUDE_ESP32C3_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ESP32C3_INT_PRIO_DEF 1 + +/* Interrupt Matrix + * + * The Interrupt Matrix embedded in the ESP32C3 independently allocates + * peripheral interrupt sources to the CPUs’ peripheral interrupts. + * This configuration is highly flexible in order to meet many different + * needs. + * + * Features + * - Accepts 62 peripheral interrupt sources as input. + * - Generate 31 peripheral interrupts to CPU as output. + * - Queries current interrupt status of peripheral interrupt sources. + */ + +/* RESERVED interrupts: 0 to 14 */ + +#define ESP32C3_PERIPH_WMAC 1 /* Reserved, but needed by WiFi driver */ + +#define ESP32C3_PERIPH_BT_BB 5 /* Reserved, but needed by BLE driver */ +#define ESP32C3_PERIPH_RWBLE 8 /* Reserved, but needed by BLE driver */ + +#define ESP32C3_PERIPH_UHCI0 15 +#define ESP32C3_PERIPH_GPIO 16 +#define ESP32C3_PERIPH_GPIO_NMI 17 + +/* RESERVED interrupt 18 */ + +#define ESP32C3_PERIPH_SPI2 19 + +#define ESP32C3_PERIPH_I2S1 20 +#define ESP32C3_PERIPH_UART0 21 +#define ESP32C3_PERIPH_UART1 22 +#define ESP32C3_PERIPH_LEDC 23 +#define ESP32C3_PERIPH_EFUSE 24 +#define ESP32C3_PERIPH_TWAI 25 +#define ESP32C3_PERIPH_USB 26 +#define ESP32C3_PERIPH_RTC_CORE 27 +#define ESP32C3_PERIPH_RMT 28 +#define ESP32C3_PERIPH_I2C_EXT0 29 + +/* RESERVED interrupts 30-31 */ + +#define ESP32C3_PERIPH_TG0_T0 32 +#define ESP32C3_PERIPH_TG0_WDT 33 +#define ESP32C3_PERIPH_TG1_T0 34 +#define ESP32C3_PERIPH_TG1_WDT 35 + +/* RESERVED interrupt 36 */ + +#define ESP32C3_PERIPH_SYSTIMER_T0 37 +#define ESP32C3_PERIPH_SYSTIMER_T1 38 +#define ESP32C3_PERIPH_SYSTIMER_T2 39 + +/* RESERVED interrupts 40-42 */ + +#define ESP32C3_PERIPH_APB_ADC 43 +#define ESP32C3_PERIPH_DMA_CH0 44 +#define ESP32C3_PERIPH_DMA_CH1 45 +#define ESP32C3_PERIPH_DMA_CH2 46 +#define ESP32C3_PERIPH_RSA 47 +#define ESP32C3_PERIPH_AES 48 +#define ESP32C3_PERIPH_SHA 49 + +#define ESP32C3_PERIPH_FROM_CPU_INT0 50 +#define ESP32C3_PERIPH_FROM_CPU_INT1 51 +#define ESP32C3_PERIPH_FROM_CPU_INT2 52 +#define ESP32C3_PERIPH_FROM_CPU_INT3 53 +#define ESP32C3_PERIPH_ASSIST_DEBUG 54 +#define ESP32C3_PERIPH_DMA_APBPERI_PMS 55 +#define ESP32C3_PERIPH_CORE0_IRAM0_PMS 56 +#define ESP32C3_PERIPH_CORE0_DRAM0_PMS 57 +#define ESP32C3_PERIPH_CORE0_PIF_PMS 58 +#define ESP32C3_PERIPH_CORE0_PIF_PMS_SZIE 59 + +/* RESERVED interrupts 60-61 */ + +/* Total number of peripherals */ + +#define ESP32C3_NPERIPHERALS 62 + +/* CPU Interrupts. + * + * The ESP32-C3 CPU interrupt controller accepts 31 asynchronous interrupts. + */ + +#define ESP32C3_NCPUINTS 32 +#define ESP32C3_CPUINT_MAX (ESP32C3_NCPUINTS - 1) + +#define ESP32C3_CPUINT_ALWAYS_RSVD 0 + +#define ESP32C3_CPUINT_PERIPHSET 0xffffffff + +/* Reserved CPU interrupt for specific drivers */ + +#define ESP32C3_CPUINT_WMAC 1 /* Wi-Fi MAC */ +#define ESP32C3_CPUINT_BT_BB 5 /* BT BB */ +#define ESP32C3_CPUINT_RWBLE 8 /* RW BLE */ + +/* IRQ numbers. */ + +/* ecall is dispatched like normal interrupts. It occupies an IRQ number. */ + +#define RISCV_NIRQ_INTERRUPTS 16 /* Number of RISC-V dispatched interrupts. */ +#define ESP32C3_IRQ_FIRSTPERIPH 16 /* First peripheral IRQ number */ + +/* IRQ numbers for peripheral interrupts coming through the Interrupt + * Matrix. + */ + +#define ESP32C3_IRQ2PERIPH(irq) ((irq) - ESP32C3_IRQ_FIRSTPERIPH) +#define ESP32C3_PERIPH2IRQ(id) ((id) + ESP32C3_IRQ_FIRSTPERIPH) + +/* Peripheral IRQs */ + +#define ESP32C3_IRQ_WMAC (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_WMAC) + +#define ESP32C3_IRQ_BT_BB (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_BT_BB) +#define ESP32C3_IRQ_RWBLE (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RWBLE) + +#define ESP32C3_IRQ_UHCI0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_UHCI0) +#define ESP32C3_IRQ_GPIO (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_GPIO) +#define ESP32C3_IRQ_GPIO_NMI (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_GPIO_NMI) + +#define ESP32C3_IRQ_SPI2 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SPI2) +#define ESP32C3_IRQ_I2S1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_I2S1) +#define ESP32C3_IRQ_UART0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_UART0) +#define ESP32C3_IRQ_UART1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_UART1) +#define ESP32C3_IRQ_LEDC (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_LEDC) +#define ESP32C3_IRQ_EFUSE (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_EFUSE) +#define ESP32C3_IRQ_TWAI (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TWAI) +#define ESP32C3_IRQ_USB (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_USB) +#define ESP32C3_IRQ_RTC_CORE (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RTC_CORE) +#define ESP32C3_IRQ_RMT (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RMT) +#define ESP32C3_IRQ_I2C_EXT0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_I2C_EXT0) + +#define ESP32C3_IRQ_TG0_T0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TG0_T0) +#define ESP32C3_IRQ_TG0_WDT (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TG0_WDT) +#define ESP32C3_IRQ_TG1_T0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TG1_T0) +#define ESP32C3_IRQ_TG1_WDT (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TG1_WDT) + +#define ESP32C3_IRQ_SYSTIMER_T0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SYSTIMER_T0) +#define ESP32C3_IRQ_SYSTIMER_T1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SYSTIMER_T1) +#define ESP32C3_IRQ_SYSTIMER_T2 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SYSTIMER_T2) + +#define ESP32C3_IRQ_APB_ADC (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_APB_ADC) +#define ESP32C3_IRQ_DMA_CH0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH0) +#define ESP32C3_IRQ_DMA_CH1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH1) +#define ESP32C3_IRQ_DMA_CH2 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH2) +#define ESP32C3_IRQ_RSA (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RSA) +#define ESP32C3_IRQ_AES (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_AES) +#define ESP32C3_IRQ_SHA (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SHA) +#define ESP32C3_IRQ_FROM_CPU_INT0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_FROM_CPU_INT0) +#define ESP32C3_IRQ_FROM_CPU_INT1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_FROM_CPU_INT1) +#define ESP32C3_IRQ_FROM_CPU_INT2 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_FROM_CPU_INT2) +#define ESP32C3_IRQ_FROM_CPU_INT3 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_FROM_CPU_INT3) +#define ESP32C3_IRQ_ASSIST_DEBUG (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_ASSIST_DEBUG) +#define ESP32C3_IRQ_DMA_APBPERI_PMS (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_APBPERI_PMS) +#define ESP32C3_IRQ_CORE0_IRAM0_PMS (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_CORE0_IRAM0_PMS) +#define ESP32C3_IRQ_CORE0_DRAM0_PMS (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_CORE0_DRAM0_PMS) +#define ESP32C3_IRQ_CORE0_PIF_PMS (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_CORE0_PIF_PMS) +#define ESP32C3_IRQ_CORE0_PIF_PMS_SZIE (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_CORE0_PIF_PMS_SZIE) + +#define ESP32C3_NIRQ_PERIPH ESP32C3_NPERIPHERALS + +/* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched + * as a second level of decoding: The first level dispatches to the GPIO + * interrupt handler. The second to the decoded GPIO interrupt handler. + */ + +#ifdef CONFIG_ESP32C3_GPIO_IRQ +# define ESP32C3_NIRQ_GPIO 22 +# define ESP32C3_FIRST_GPIOIRQ (RISCV_NIRQ_INTERRUPTS + ESP32C3_NIRQ_PERIPH) +# define ESP32C3_LAST_GPIOIRQ (ESP32C3_FIRST_GPIOIRQ + ESP32C3_NIRQ_GPIO - 1) +# define ESP32C3_PIN2IRQ(p) ((p) + ESP32C3_FIRST_GPIOIRQ) +# define ESP32C3_IRQ2PIN(i) ((i) - ESP32C3_FIRST_GPIOIRQ) +#else +# define ESP32C3_NIRQ_GPIO 0 +#endif + +#ifdef CONFIG_ESP32C3_RTCIO_IRQ + +/* Second level RTC interrupts. RTC interrupts are decoded and dispatched + * as a second level of decoding: The first level dispatches to the RTC + * interrupt handler. The second to the decoded RTC interrupt handler. + * A third level might be required to be implemented on the driver. + */ + +# define ESP32C3_NIRQ_RTCIO 9 + +# define ESP32C3_FIRST_RTCIOIRQ (RISCV_NIRQ_INTERRUPTS+ESP32C3_NIRQ_PERIPH+ESP32C3_NIRQ_GPIO) +# define ESP32C3_LAST_RTCIOIRQ (ESP32C3_FIRST_RTCIOIRQ+ESP32C3_NIRQ_RTCIO-1) +# define ESP32C3_IRQ_RTC_SLP_WAKEUP (ESP32C3_FIRST_RTCIOIRQ+0) +# define ESP32C3_IRQ_RTC_SLP_REJECT (ESP32C3_FIRST_RTCIOIRQ+1) +# define ESP32C3_IRQ_RTC_WDT (ESP32C3_FIRST_RTCIOIRQ+2) +# define ESP32C3_IRQ_RTC_BROWN_OUT (ESP32C3_FIRST_RTCIOIRQ+3) +# define ESP32C3_IRQ_RTC_MAIN_TIMER (ESP32C3_FIRST_RTCIOIRQ+4) +# define ESP32C3_IRQ_RTC_SWD (ESP32C3_FIRST_RTCIOIRQ+5) +# define ESP32C3_IRQ_RTC_XTAL32K_DEAD (ESP32C3_FIRST_RTCIOIRQ+6) +# define ESP32C3_IRQ_RTC_GLITCH_DET (ESP32C3_FIRST_RTCIOIRQ+7) +# define ESP32C3_IRQ_RTC_BBPLL_CAL (ESP32C3_FIRST_RTCIOIRQ+8) +#else +# define ESP32C3_NIRQ_RTCIO 0 +#endif + +/* Total number of IRQs: ecall + Peripheral IRQs + GPIOs IRQs + RTCIO IRQs. */ + +#define NR_IRQS (RISCV_NIRQ_INTERRUPTS + ESP32C3_NIRQ_PERIPH + ESP32C3_NIRQ_GPIO + ESP32C3_NIRQ_RTCIO) + +#endif /* __ARCH_RISCV_INCLUDE_ESP32C3_IRQ_H */ diff --git a/arch/risc-v/include/espressif/.gitignore b/arch/risc-v/include/esp32c3/.gitignore similarity index 100% rename from arch/risc-v/include/espressif/.gitignore rename to arch/risc-v/include/esp32c3/.gitignore diff --git a/arch/risc-v/include/esp32c3/chip.h b/arch/risc-v/include/esp32c3/chip.h index cb640d57d3ef8..44938d956c6e7 100644 --- a/arch/risc-v/include/esp32c3/chip.h +++ b/arch/risc-v/include/esp32c3/chip.h @@ -25,14 +25,8 @@ * Included Files ****************************************************************************/ -#include - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Characterize each supported ESP32-C3 part */ - -#define ESP32C3_NGPIOS 22 /* GPIO0-21 */ - #endif /* __ARCH_RISCV_INCLUDE_ESP32C3_CHIP_H */ diff --git a/arch/risc-v/include/esp32c3/irq.h b/arch/risc-v/include/esp32c3/irq.h deleted file mode 100644 index b778f7859d2fd..0000000000000 --- a/arch/risc-v/include/esp32c3/irq.h +++ /dev/null @@ -1,241 +0,0 @@ -/**************************************************************************** - * arch/risc-v/include/esp32c3/irq.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_INCLUDE_ESP32C3_IRQ_H -#define __ARCH_RISCV_INCLUDE_ESP32C3_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ESP32C3_INT_PRIO_DEF 1 - -/* Interrupt Matrix - * - * The Interrupt Matrix embedded in the ESP32C3 independently allocates - * peripheral interrupt sources to the CPUs’ peripheral interrupts. - * This configuration is highly flexible in order to meet many different - * needs. - * - * Features - * - Accepts 62 peripheral interrupt sources as input. - * - Generate 31 peripheral interrupts to CPU as output. - * - Queries current interrupt status of peripheral interrupt sources. - */ - -/* RESERVED interrupts: 0 to 14 */ - -#define ESP32C3_PERIPH_WMAC 1 /* Reserved, but needed by WiFi driver */ - -#define ESP32C3_PERIPH_BT_BB 5 /* Reserved, but needed by BLE driver */ -#define ESP32C3_PERIPH_RWBLE 8 /* Reserved, but needed by BLE driver */ - -#define ESP32C3_PERIPH_UHCI0 15 -#define ESP32C3_PERIPH_GPIO 16 -#define ESP32C3_PERIPH_GPIO_NMI 17 - -/* RESERVED interrupt 18 */ - -#define ESP32C3_PERIPH_SPI2 19 - -#define ESP32C3_PERIPH_I2S1 20 -#define ESP32C3_PERIPH_UART0 21 -#define ESP32C3_PERIPH_UART1 22 -#define ESP32C3_PERIPH_LEDC 23 -#define ESP32C3_PERIPH_EFUSE 24 -#define ESP32C3_PERIPH_TWAI 25 -#define ESP32C3_PERIPH_USB 26 -#define ESP32C3_PERIPH_RTC_CORE 27 -#define ESP32C3_PERIPH_RMT 28 -#define ESP32C3_PERIPH_I2C_EXT0 29 - -/* RESERVED interrupts 30-31 */ - -#define ESP32C3_PERIPH_TG0_T0 32 -#define ESP32C3_PERIPH_TG0_WDT 33 -#define ESP32C3_PERIPH_TG1_T0 34 -#define ESP32C3_PERIPH_TG1_WDT 35 - -/* RESERVED interrupt 36 */ - -#define ESP32C3_PERIPH_SYSTIMER_T0 37 -#define ESP32C3_PERIPH_SYSTIMER_T1 38 -#define ESP32C3_PERIPH_SYSTIMER_T2 39 - -/* RESERVED interrupts 40-42 */ - -#define ESP32C3_PERIPH_APB_ADC 43 -#define ESP32C3_PERIPH_DMA_CH0 44 -#define ESP32C3_PERIPH_DMA_CH1 45 -#define ESP32C3_PERIPH_DMA_CH2 46 -#define ESP32C3_PERIPH_RSA 47 -#define ESP32C3_PERIPH_AES 48 -#define ESP32C3_PERIPH_SHA 49 - -#define ESP32C3_PERIPH_FROM_CPU_INT0 50 -#define ESP32C3_PERIPH_FROM_CPU_INT1 51 -#define ESP32C3_PERIPH_FROM_CPU_INT2 52 -#define ESP32C3_PERIPH_FROM_CPU_INT3 53 -#define ESP32C3_PERIPH_ASSIST_DEBUG 54 -#define ESP32C3_PERIPH_DMA_APBPERI_PMS 55 -#define ESP32C3_PERIPH_CORE0_IRAM0_PMS 56 -#define ESP32C3_PERIPH_CORE0_DRAM0_PMS 57 -#define ESP32C3_PERIPH_CORE0_PIF_PMS 58 -#define ESP32C3_PERIPH_CORE0_PIF_PMS_SZIE 59 - -/* RESERVED interrupts 60-61 */ - -/* Total number of peripherals */ - -#define ESP32C3_NPERIPHERALS 62 - -/* CPU Interrupts. - * - * The ESP32-C3 CPU interrupt controller accepts 31 asynchronous interrupts. - */ - -#define ESP32C3_NCPUINTS 32 -#define ESP32C3_CPUINT_MAX (ESP32C3_NCPUINTS - 1) - -#define ESP32C3_CPUINT_ALWAYS_RSVD 0 - -#define ESP32C3_CPUINT_PERIPHSET 0xffffffff - -/* Reserved CPU interrupt for specific drivers */ - -#define ESP32C3_CPUINT_WMAC 1 /* Wi-Fi MAC */ -#define ESP32C3_CPUINT_BT_BB 5 /* BT BB */ -#define ESP32C3_CPUINT_RWBLE 8 /* RW BLE */ - -/* IRQ numbers. */ - -/* ecall is dispatched like normal interrupts. It occupies an IRQ number. */ - -#define RISCV_NIRQ_INTERRUPTS 16 /* Number of RISC-V dispatched interrupts. */ -#define ESP32C3_IRQ_FIRSTPERIPH 16 /* First peripheral IRQ number */ - -/* IRQ numbers for peripheral interrupts coming through the Interrupt - * Matrix. - */ - -#define ESP32C3_IRQ2PERIPH(irq) ((irq) - ESP32C3_IRQ_FIRSTPERIPH) -#define ESP32C3_PERIPH2IRQ(id) ((id) + ESP32C3_IRQ_FIRSTPERIPH) - -/* Peripheral IRQs */ - -#define ESP32C3_IRQ_WMAC (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_WMAC) - -#define ESP32C3_IRQ_BT_BB (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_BT_BB) -#define ESP32C3_IRQ_RWBLE (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RWBLE) - -#define ESP32C3_IRQ_UHCI0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_UHCI0) -#define ESP32C3_IRQ_GPIO (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_GPIO) -#define ESP32C3_IRQ_GPIO_NMI (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_GPIO_NMI) - -#define ESP32C3_IRQ_SPI2 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SPI2) -#define ESP32C3_IRQ_I2S1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_I2S1) -#define ESP32C3_IRQ_UART0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_UART0) -#define ESP32C3_IRQ_UART1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_UART1) -#define ESP32C3_IRQ_LEDC (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_LEDC) -#define ESP32C3_IRQ_EFUSE (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_EFUSE) -#define ESP32C3_IRQ_TWAI (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TWAI) -#define ESP32C3_IRQ_USB (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_USB) -#define ESP32C3_IRQ_RTC_CORE (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RTC_CORE) -#define ESP32C3_IRQ_RMT (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RMT) -#define ESP32C3_IRQ_I2C_EXT0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_I2C_EXT0) - -#define ESP32C3_IRQ_TG0_T0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TG0_T0) -#define ESP32C3_IRQ_TG0_WDT (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TG0_WDT) -#define ESP32C3_IRQ_TG1_T0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TG1_T0) -#define ESP32C3_IRQ_TG1_WDT (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_TG1_WDT) - -#define ESP32C3_IRQ_SYSTIMER_T0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SYSTIMER_T0) -#define ESP32C3_IRQ_SYSTIMER_T1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SYSTIMER_T1) -#define ESP32C3_IRQ_SYSTIMER_T2 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SYSTIMER_T2) - -#define ESP32C3_IRQ_APB_ADC (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_APB_ADC) -#define ESP32C3_IRQ_DMA_CH0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH0) -#define ESP32C3_IRQ_DMA_CH1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH1) -#define ESP32C3_IRQ_DMA_CH2 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_CH2) -#define ESP32C3_IRQ_RSA (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_RSA) -#define ESP32C3_IRQ_AES (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_AES) -#define ESP32C3_IRQ_SHA (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_SHA) -#define ESP32C3_IRQ_FROM_CPU_INT0 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_FROM_CPU_INT0) -#define ESP32C3_IRQ_FROM_CPU_INT1 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_FROM_CPU_INT1) -#define ESP32C3_IRQ_FROM_CPU_INT2 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_FROM_CPU_INT2) -#define ESP32C3_IRQ_FROM_CPU_INT3 (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_FROM_CPU_INT3) -#define ESP32C3_IRQ_ASSIST_DEBUG (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_ASSIST_DEBUG) -#define ESP32C3_IRQ_DMA_APBPERI_PMS (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_DMA_APBPERI_PMS) -#define ESP32C3_IRQ_CORE0_IRAM0_PMS (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_CORE0_IRAM0_PMS) -#define ESP32C3_IRQ_CORE0_DRAM0_PMS (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_CORE0_DRAM0_PMS) -#define ESP32C3_IRQ_CORE0_PIF_PMS (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_CORE0_PIF_PMS) -#define ESP32C3_IRQ_CORE0_PIF_PMS_SZIE (ESP32C3_IRQ_FIRSTPERIPH + ESP32C3_PERIPH_CORE0_PIF_PMS_SZIE) - -#define ESP32C3_NIRQ_PERIPH ESP32C3_NPERIPHERALS - -/* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched - * as a second level of decoding: The first level dispatches to the GPIO - * interrupt handler. The second to the decoded GPIO interrupt handler. - */ - -#ifdef CONFIG_ESP32C3_GPIO_IRQ -# define ESP32C3_NIRQ_GPIO 22 -# define ESP32C3_FIRST_GPIOIRQ (RISCV_NIRQ_INTERRUPTS + ESP32C3_NIRQ_PERIPH) -# define ESP32C3_LAST_GPIOIRQ (ESP32C3_FIRST_GPIOIRQ + ESP32C3_NIRQ_GPIO - 1) -# define ESP32C3_PIN2IRQ(p) ((p) + ESP32C3_FIRST_GPIOIRQ) -# define ESP32C3_IRQ2PIN(i) ((i) - ESP32C3_FIRST_GPIOIRQ) -#else -# define ESP32C3_NIRQ_GPIO 0 -#endif - -#ifdef CONFIG_ESP32C3_RTCIO_IRQ - -/* Second level RTC interrupts. RTC interrupts are decoded and dispatched - * as a second level of decoding: The first level dispatches to the RTC - * interrupt handler. The second to the decoded RTC interrupt handler. - * A third level might be required to be implemented on the driver. - */ - -# define ESP32C3_NIRQ_RTCIO 9 - -# define ESP32C3_FIRST_RTCIOIRQ (RISCV_NIRQ_INTERRUPTS+ESP32C3_NIRQ_PERIPH+ESP32C3_NIRQ_GPIO) -# define ESP32C3_LAST_RTCIOIRQ (ESP32C3_FIRST_RTCIOIRQ+ESP32C3_NIRQ_RTCIO-1) -# define ESP32C3_IRQ_RTC_SLP_WAKEUP (ESP32C3_FIRST_RTCIOIRQ+0) -# define ESP32C3_IRQ_RTC_SLP_REJECT (ESP32C3_FIRST_RTCIOIRQ+1) -# define ESP32C3_IRQ_RTC_WDT (ESP32C3_FIRST_RTCIOIRQ+2) -# define ESP32C3_IRQ_RTC_BROWN_OUT (ESP32C3_FIRST_RTCIOIRQ+3) -# define ESP32C3_IRQ_RTC_MAIN_TIMER (ESP32C3_FIRST_RTCIOIRQ+4) -# define ESP32C3_IRQ_RTC_SWD (ESP32C3_FIRST_RTCIOIRQ+5) -# define ESP32C3_IRQ_RTC_XTAL32K_DEAD (ESP32C3_FIRST_RTCIOIRQ+6) -# define ESP32C3_IRQ_RTC_GLITCH_DET (ESP32C3_FIRST_RTCIOIRQ+7) -# define ESP32C3_IRQ_RTC_BBPLL_CAL (ESP32C3_FIRST_RTCIOIRQ+8) -#else -# define ESP32C3_NIRQ_RTCIO 0 -#endif - -/* Total number of IRQs: ecall + Peripheral IRQs + GPIOs IRQs + RTCIO IRQs. */ - -#define NR_IRQS (RISCV_NIRQ_INTERRUPTS + ESP32C3_NIRQ_PERIPH + ESP32C3_NIRQ_GPIO + ESP32C3_NIRQ_RTCIO) - -#endif /* __ARCH_RISCV_INCLUDE_ESP32C3_IRQ_H */ diff --git a/arch/risc-v/include/esp32c6/.gitignore b/arch/risc-v/include/esp32c6/.gitignore new file mode 100644 index 0000000000000..a9e61e717ee17 --- /dev/null +++ b/arch/risc-v/include/esp32c6/.gitignore @@ -0,0 +1,2 @@ +/gpio_sig_map.h +/irq.h diff --git a/arch/risc-v/include/esp32c6/chip.h b/arch/risc-v/include/esp32c6/chip.h index 66e8238e3268d..12b241b8b7344 100644 --- a/arch/risc-v/include/esp32c6/chip.h +++ b/arch/risc-v/include/esp32c6/chip.h @@ -21,4 +21,12 @@ #ifndef __ARCH_RISCV_INCLUDE_ESP32C6_CHIP_H #define __ARCH_RISCV_INCLUDE_ESP32C6_CHIP_H +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + #endif /* __ARCH_RISCV_INCLUDE_ESP32C6_CHIP_H */ diff --git a/arch/risc-v/include/esp32c6/irq.h b/arch/risc-v/include/esp32c6/irq.h deleted file mode 100644 index 2c72d25393e05..0000000000000 --- a/arch/risc-v/include/esp32c6/irq.h +++ /dev/null @@ -1,260 +0,0 @@ -/**************************************************************************** - * arch/risc-v/include/esp32c6/irq.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_INCLUDE_ESP32C6_IRQ_H -#define __ARCH_RISCV_INCLUDE_ESP32C6_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -# include -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Interrupt Matrix - * The Interrupt Matrix embedded in the ESP32-C6 independently allocates - * peripheral interrupt sources to the CPUs’ peripheral interrupts. - * This configuration is highly flexible in order to meet many different - * needs. - * - * Features - * - Accepts 77 peripheral interrupt sources as input. - * - Generate 31 peripheral interrupts to CPU as output. - * - Queries current interrupt status of peripheral interrupt sources. - */ - -#define ESP32C6_WIFI_MAC_PERIPH 0 /* interrupt of WiFi MAC, level */ -#define ESP32C6_WIFI_MAC_NMI_PERIPH 1 /* interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI */ -#define ESP32C6_WIFI_PWR_PERIPH 2 -#define ESP32C6_WIFI_BB_PERIPH 3 /* interrupt of WiFi BB, level, we can do some calibartion */ -#define ESP32C6_BT_MAC_PERIPH 4 -#define ESP32C6_BT_BB_PERIPH 5 /* interrupt of BT BB, level */ -#define ESP32C6_BT_BB_NMI_PERIPH 6 /* interrupt of BT BB, NMI, use if BB have bug to fix in NMI */ -#define ESP32C6_LP_TIMER_PERIPH 7 -#define ESP32C6_COEX_PERIPH 8 -#define ESP32C6_BLE_TIMER_PERIPH 9 -#define ESP32C6_BLE_SEC_PERIPH 10 -#define ESP32C6_I2C_MASTER_PERIPH 11 /* interrupt of I2C Master, level */ -#define ESP32C6_ZB_MAC_PERIPH 12 -#define ESP32C6_PMU_PERIPH 13 -#define ESP32C6_EFUSE_PERIPH 14 /* interrupt of efuse, level, not likely to use */ -#define ESP32C6_LP_RTC_TIMER_PERIPH 15 -#define ESP32C6_LP_UART_PERIPH 16 -#define ESP32C6_LP_I2C_PERIPH 17 -#define ESP32C6_LP_WDT_PERIPH 18 -#define ESP32C6_LP_PERI_TIMEOUT_PERIPH 19 -#define ESP32C6_LP_APM_M0_PERIPH 20 -#define ESP32C6_LP_APM_M1_PERIPH 21 -#define ESP32C6_FROM_CPU_PERIPH0 22 /* interrupt0 generated from a CPU, level */ -#define ESP32C6_FROM_CPU_PERIPH1 23 /* interrupt1 generated from a CPU, level */ -#define ESP32C6_FROM_CPU_PERIPH2 24 /* interrupt2 generated from a CPU, level */ -#define ESP32C6_FROM_CPU_PERIPH3 25 /* interrupt3 generated from a CPU, level */ -#define ESP32C6_ASSIST_DEBUG_PERIPH 26 /* interrupt of Assist debug module, level */ -#define ESP32C6_TRACE_PERIPH 27 -#define ESP32C6_CACHE_PERIPH 28 -#define ESP32C6_CPU_PERI_TIMEOUT_PERIPH 29 -#define ESP32C6_GPIO_PERIPH 30 /* interrupt of GPIO, level */ -#define ESP32C6_GPIO_NMI_PERIPH 31 /* interrupt of GPIO, NMI */ -#define ESP32C6_PAU_PERIPH 32 -#define ESP32C6_HP_PERI_TIMEOUT_PERIPH 33 -#define ESP32C6_MODEM_PERI_TIMEOUT_PERIPH 34 -#define ESP32C6_HP_APM_M0_PERIPH 35 -#define ESP32C6_HP_APM_M1_PERIPH 36 -#define ESP32C6_HP_APM_M2_PERIPH 37 -#define ESP32C6_HP_APM_M3_PERIPH 38 -#define ESP32C6_LP_APM0_PERIPH 39 -#define ESP32C6_MSPI_PERIPH 40 -#define ESP32C6_I2S1_PERIPH 41 /* interrupt of I2S1, level */ -#define ESP32C6_UHCI0_PERIPH 42 /* interrupt of UHCI0, level */ -#define ESP32C6_UART0_PERIPH 43 /* interrupt of UART0, level */ -#define ESP32C6_UART1_PERIPH 44 /* interrupt of UART1, level */ -#define ESP32C6_LEDC_PERIPH 45 /* interrupt of LED PWM, level */ -#define ESP32C6_TWAI0_PERIPH 46 /* interrupt of can0, level */ -#define ESP32C6_TWAI1_PERIPH 47 /* interrupt of can1, level */ -#define ESP32C6_USB_SERIAL_JTAG_PERIPH 48 /* interrupt of USB, level */ -#define ESP32C6_RMT_PERIPH 49 /* interrupt of remote controller, level */ -#define ESP32C6_I2C_EXT0_PERIPH 50 /* interrupt of I2C controller1, level */ -#define ESP32C6_TG0_T0_LEVEL_PERIPH 51 /* interrupt of TIMER_GROUP0, TIMER0, level */ -#define ESP32C6_TG0_T1_LEVEL_PERIPH 52 /* interrupt of TIMER_GROUP0, TIMER1, level */ -#define ESP32C6_TG0_WDT_LEVEL_PERIPH 53 /* interrupt of TIMER_GROUP0, WATCH DOG, level */ -#define ESP32C6_TG1_T0_LEVEL_PERIPH 54 /* interrupt of TIMER_GROUP1, TIMER0, level */ -#define ESP32C6_TG1_T1_LEVEL_PERIPH 55 /* interrupt of TIMER_GROUP1, TIMER1, level */ -#define ESP32C6_TG1_WDT_LEVEL_PERIPH 56 /* interrupt of TIMER_GROUP1, WATCHDOG, level */ -#define ESP32C6_SYSTIMER_TARGET0_EDGE_PERIPH 57 /* interrupt of system timer 0, EDGE */ -#define ESP32C6_SYSTIMER_TARGET1_EDGE_PERIPH 58 /* interrupt of system timer 1, EDGE */ -#define ESP32C6_SYSTIMER_TARGET2_EDGE_PERIPH 59 /* interrupt of system timer 2, EDGE */ -#define ESP32C6_APB_ADC_PERIPH 60 /* interrupt of APB ADC, level */ -#define ESP32C6_MCPWM0_PERIPH 61 /* interrupt of MCPWM0, level */ -#define ESP32C6_PCNT_PERIPH 62 -#define ESP32C6_PARL_IO_PERIPH 63 -#define ESP32C6_SLC0_PERIPH 64 -#define ESP32C6_SLC_PERIPH 65 -#define ESP32C6_DMA_IN_CH0_PERIPH 66 /* interrupt of general DMA IN channel 0, level */ -#define ESP32C6_DMA_IN_CH1_PERIPH 67 /* interrupt of general DMA IN channel 1, level */ -#define ESP32C6_DMA_IN_CH2_PERIPH 68 /* interrupt of general DMA IN channel 2, level */ -#define ESP32C6_DMA_OUT_CH0_PERIPH 69 /* interrupt of general DMA OUT channel 0, level */ -#define ESP32C6_DMA_OUT_CH1_PERIPH 70 /* interrupt of general DMA OUT channel 1, level */ -#define ESP32C6_DMA_OUT_CH2_PERIPH 71 /* interrupt of general DMA OUT channel 2, level */ -#define ESP32C6_GSPI2_PERIPH 72 -#define ESP32C6_AES_PERIPH 73 /* interrupt of AES accelerator, level */ -#define ESP32C6_SHA_PERIPH 74 /* interrupt of SHA accelerator, level */ -#define ESP32C6_RSA_PERIPH 75 /* interrupt of RSA accelerator, level */ -#define ESP32C6_ECC_PERIPH 76 /* interrupt of ECC accelerator, level */ - -/* Total number of peripherals */ - -#define ESP32C6_NPERIPHERALS 77 - -/* CPU Interrupts. - * The ESP32-C6 CPU interrupt controller accepts 31 asynchronous interrupts. - */ - -#define ESP32C6_CPUINT_MIN 1 -#define ESP32C6_CPUINT_MAX 31 - -#define ESP32C6_NCPUINTS 32 - -#define ESP32C6_CPUINT_PERIPHSET 0xffffffff - -/* IRQ numbers. */ - -/* ecall is dispatched like normal interrupts. It occupies an IRQ number. */ - -#define RISCV_NIRQ_INTERRUPTS 16 /* Number of RISC-V dispatched interrupts. */ -#define ESP32C6_IRQ_FIRSTPERIPH 16 /* First peripheral IRQ number */ - -/* IRQ numbers for peripheral interrupts coming through the Interrupt - * Matrix. - */ - -#define ESP32C6_IRQ2PERIPH(irq) ((irq) - ESP32C6_IRQ_FIRSTPERIPH) -#define ESP32C6_PERIPH2IRQ(id) ((id) + ESP32C6_IRQ_FIRSTPERIPH) - -/* Peripheral IRQs */ - -#define ESP32C6_IRQ_WIFI_MAC (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_WIFI_MAC_PERIPH) -#define ESP32C6_IRQ_WIFI_MAC_NMI (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_WIFI_MAC_NMI_PERIPH) -#define ESP32C6_IRQ_WIFI_PWR (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_WIFI_PWR_PERIPH) -#define ESP32C6_IRQ_WIFI_BB (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_WIFI_BB_PERIPH) - -#define ESP32C6_IRQ_BT_MAC (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_BT_MAC_PERIPH) -#define ESP32C6_IRQ_BT_BB (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_BT_BB_PERIPH) -#define ESP32C6_IRQ_BT_BB_NMI (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_BT_BB_NMI_PERIPH) -#define ESP32C6_IRQ_LP_TIMER (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LP_TIMER_PERIPH) - -#define ESP32C6_IRQ_COEX (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_COEX_PERIPH) -#define ESP32C6_IRQ_BLE_TIMER (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_BLE_TIMER_PERIPH) -#define ESP32C6_IRQ_BLE_SEC (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_BLE_SEC_PERIPH) -#define ESP32C6_IRQ_I2C_MASTER (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_I2C_MASTER_PERIPH) - -#define ESP32C6_IRQ_ZB_MAC (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_ZB_MAC_PERIPH) -#define ESP32C6_IRQ_PMU (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_PMU_PERIPH) -#define ESP32C6_IRQ_EFUSE (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_EFUSE_PERIPH) -#define ESP32C6_IRQ_LP_RTC_TIMER (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LP_RTC_TIMER_PERIPH) - -#define ESP32C6_IRQ_LP_UART (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LP_UART_PERIPH) -#define ESP32C6_IRQ_LP_I2C (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LP_I2C_PERIPH) -#define ESP32C6_IRQ_LP_WDT (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LP_WDT_PERIPH) -#define ESP32C6_IRQ_LP_PERI_TIMEOUT (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LP_PERI_TIMEOUT_PERIPH) - -#define ESP32C6_IRQ_LP_APM_M0 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LP_APM_M0_PERIPH) -#define ESP32C6_IRQ_LP_APM_M1 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LP_APM_M1_PERIPH) -#define ESP32C6_IRQ_FROM_CPU_PERIPH0 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_FROM_CPU_PERIPH0) -#define ESP32C6_IRQ_FROM_CPU_PERIPH1 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_FROM_CPU_PERIPH1) - -#define ESP32C6_IRQ_FROM_CPU_PERIPH2 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_FROM_CPU_PERIPH2) -#define ESP32C6_IRQ_FROM_CPU_PERIPH3 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_FROM_CPU_PERIPH3) -#define ESP32C6_IRQ_ASSIST_DEBUG (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_ASSIST_DEBUG_PERIPH) -#define ESP32C6_IRQ_TRACE (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_TRACE_PERIPH) - -#define ESP32C6_IRQ_CACHE (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_CACHE_PERIPH) -#define ESP32C6_IRQ_CPU_PERI_TIMEOUT (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_CPU_PERI_TIMEOUT_PERIPH) -#define ESP32C6_IRQ_GPIO (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_GPIO_PERIPH) -#define ESP32C6_IRQ_GPIO_NMI (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_GPIO_NMI_PERIPH) - -#define ESP32C6_IRQ_PAU (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_PAU_PERIPH) -#define ESP32C6_IRQ_HP_PERI_TIMEOUT (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_HP_PERI_TIMEOUT_PERIPH) -#define ESP32C6_IRQ_MODEM_PERI_TIMEOUT (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_MODEM_PERI_TIMEOUT_PERIPH) -#define ESP32C6_IRQ_HP_APM_M0 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_HP_APM_M0_PERIPH) - -#define ESP32C6_IRQ_HP_APM_M1 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_HP_APM_M1_PERIPH) -#define ESP32C6_IRQ_HP_APM_M2 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_HP_APM_M2_PERIPH) -#define ESP32C6_IRQ_HP_APM_M3 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_HP_APM_M3_PERIPH) -#define ESP32C6_IRQ_LP_APM0 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LP_APM0_PERIPH) - -#define ESP32C6_IRQ_MSPI (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_MSPI_PERIPH) -#define ESP32C6_IRQ_I2S1 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_I2S1_PERIPH) -#define ESP32C6_IRQ_UHCI0 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_UHCI0_PERIPH) -#define ESP32C6_IRQ_UART0 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_UART0_PERIPH) - -#define ESP32C6_IRQ_UART1 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_UART1_PERIPH) -#define ESP32C6_IRQ_LEDC (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_LEDC_PERIPH) -#define ESP32C6_IRQ_TWAI0 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_TWAI0_PERIPH) -#define ESP32C6_IRQ_TWAI1 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_TWAI1_PERIPH) - -#define ESP32C6_IRQ_USB_SERIAL_JTAG (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_USB_SERIAL_JTAG_PERIPH) -#define ESP32C6_IRQ_RMT (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_RMT_PERIPH) -#define ESP32C6_IRQ_I2C_EXT0 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_I2C_EXT0_PERIPH) -#define ESP32C6_IRQ_TG0_T0_LEVEL (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_TG0_T0_LEVEL_PERIPH) - -#define ESP32C6_IRQ_TG0_T1_LEVEL (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_TG0_T1_LEVEL_PERIPH) -#define ESP32C6_IRQ_TG0_WDT_LEVEL (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_TG0_WDT_LEVEL_PERIPH) -#define ESP32C6_IRQ_TG1_T0_LEVEL (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_TG1_T0_LEVEL_PERIPH) -#define ESP32C6_IRQ_TG1_T1_LEVEL (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_TG1_T1_LEVEL_PERIPH) - -#define ESP32C6_IRQ_TG1_WDT_LEVEL (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_TG1_WDT_LEVEL_PERIPH) -#define ESP32C6_IRQ_SYSTIMER_TARGET0_EDGE (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_SYSTIMER_TARGET0_EDGE_PERIPH) -#define ESP32C6_IRQ_SYSTIMER_TARGET1_EDGE (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_SYSTIMER_TARGET1_EDGE_PERIPH) -#define ESP32C6_IRQ_SYSTIMER_TARGET2_EDGE (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_SYSTIMER_TARGET2_EDGE_PERIPH) - -#define ESP32C6_IRQ_APB_ADC (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_APB_ADC_PERIPH) -#define ESP32C6_IRQ_MCPWM0 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_MCPWM0_PERIPH) -#define ESP32C6_IRQ_PCNT (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_PCNT_PERIPH) -#define ESP32C6_IRQ_PARL_IO (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_PARL_IO_PERIPH) - -#define ESP32C6_IRQ_SLC0 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_SLC0_PERIPH) -#define ESP32C6_IRQ_SLC (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_SLC_PERIPH) -#define ESP32C6_IRQ_DMA_IN_CH0 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_DMA_IN_CH0_PERIPH) -#define ESP32C6_IRQ_DMA_IN_CH1 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_DMA_IN_CH1_PERIPH) - -#define ESP32C6_IRQ_DMA_IN_CH2 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_DMA_IN_CH2_PERIPH) -#define ESP32C6_IRQ_DMA_OUT_CH0 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_DMA_OUT_CH0_PERIPH) -#define ESP32C6_IRQ_DMA_OUT_CH1 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_DMA_OUT_CH1_PERIPH) -#define ESP32C6_IRQ_DMA_OUT_CH2 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_DMA_OUT_CH2_PERIPH) - -#define ESP32C6_IRQ_GSPI2 (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_GSPI2_PERIPH) -#define ESP32C6_IRQ_AES (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_AES_PERIPH) -#define ESP32C6_IRQ_SHA (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_SHA_PERIPH) -#define ESP32C6_IRQ_RSA (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_RSA_PERIPH) - -#define ESP32C6_IRQ_CACHE_CORE0_ACS (ESP32C6_IRQ_FIRSTPERIPH + ESP32C6_ECC_PERIPH) - -#define ESP32C6_NIRQ_PERIPH ESP32C6_NPERIPHERALS - -/* Total number of IRQs: ecall + Number of peripheral IRQs + GPIOs IRQs. */ - -#define NR_IRQS (RISCV_NIRQ_INTERRUPTS + ESP32C6_NIRQ_PERIPH) - -#endif /* __ARCH_RISCV_INCLUDE_ESP32C6_IRQ_H */ diff --git a/arch/risc-v/include/esp32h2/.gitignore b/arch/risc-v/include/esp32h2/.gitignore new file mode 100644 index 0000000000000..a9e61e717ee17 --- /dev/null +++ b/arch/risc-v/include/esp32h2/.gitignore @@ -0,0 +1,2 @@ +/gpio_sig_map.h +/irq.h diff --git a/arch/risc-v/include/esp32h2/chip.h b/arch/risc-v/include/esp32h2/chip.h new file mode 100644 index 0000000000000..64d4e2b27dda0 --- /dev/null +++ b/arch/risc-v/include/esp32h2/chip.h @@ -0,0 +1,32 @@ +/**************************************************************************** + * arch/risc-v/include/esp32h2/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_ESP32H2_CHIP_H +#define __ARCH_RISCV_INCLUDE_ESP32H2_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_RISCV_INCLUDE_ESP32H2_CHIP_H */ diff --git a/arch/risc-v/include/espressif/chip.h b/arch/risc-v/include/espressif/chip.h deleted file mode 100644 index 58e4ba5435468..0000000000000 --- a/arch/risc-v/include/espressif/chip.h +++ /dev/null @@ -1,32 +0,0 @@ -/**************************************************************************** - * arch/risc-v/include/espressif/chip.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_INCLUDE_ESPRESSIF_CHIP_H -#define __ARCH_RISCV_INCLUDE_ESPRESSIF_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#endif /* __ARCH_RISCV_INCLUDE_ESPRESSIF_CHIP_H */ diff --git a/arch/risc-v/include/hpm6000/chip.h b/arch/risc-v/include/hpm6000/chip.h new file mode 100644 index 0000000000000..b0d4be386711a --- /dev/null +++ b/arch/risc-v/include/hpm6000/chip.h @@ -0,0 +1,24 @@ +/**************************************************************************** + * arch/risc-v/include/hpm6000/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_HPM6000_CHIP_H +#define __ARCH_RISCV_INCLUDE_HPM6000_CHIP_H + +#endif /* __ARCH_RISCV_INCLUDE_HPM6000_CHIP_H */ diff --git a/arch/risc-v/include/hpm6000/hpm_irq.h b/arch/risc-v/include/hpm6000/hpm_irq.h new file mode 100644 index 0000000000000..74fe30481561d --- /dev/null +++ b/arch/risc-v/include/hpm6000/hpm_irq.h @@ -0,0 +1,119 @@ +/**************************************************************************** + * arch/risc-v/include/hpm6000/hpm_irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_HPM6000_HPM_IRQ_H +#define __ARCH_RISCV_INCLUDE_HPM6000_HPM_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Map RISC-V exception code to NuttX IRQ */ + +#define HPM_IRQ_PERI_START (RISCV_IRQ_ASYNC + 20) + +/* Machine Global External Interrupt */ + +#define HPM_IRQ_GPIO0_A (HPM_IRQ_PERI_START + 1) +#define HPM_IRQ_GPIO0_B (HPM_IRQ_PERI_START + 2) +#define HPM_IRQ_GPIO0_C (HPM_IRQ_PERI_START + 3) +#define HPM_IRQ_GPIO0_D (HPM_IRQ_PERI_START + 4) +#define HPM_IRQ_GPIO0_X (HPM_IRQ_PERI_START + 5) +#define HPM_IRQ_GPIO0_Y (HPM_IRQ_PERI_START + 6) +#define HPM_IRQ_GPIO0_Z (HPM_IRQ_PERI_START + 7) +#define HPM_IRQ_ADC0 (HPM_IRQ_PERI_START + 8) +#define HPM_IRQ_ADC1 (HPM_IRQ_PERI_START + 9) +#define HPM_IRQ_ADC2 (HPM_IRQ_PERI_START + 10) +#define HPM_IRQ_DAC (HPM_IRQ_PERI_START + 11) +#define HPM_IRQ_ACMP0 (HPM_IRQ_PERI_START + 12) +#define HPM_IRQ_ACMP1 (HPM_IRQ_PERI_START + 13) +#define HPM_IRQ_SPI0 (HPM_IRQ_PERI_START + 14) +#define HPM_IRQ_SPI1 (HPM_IRQ_PERI_START + 15) +#define HPM_IRQ_SPI2 (HPM_IRQ_PERI_START + 16) +#define HPM_IRQ_SPI3 (HPM_IRQ_PERI_START + 17) +#define HPM_IRQ_UART0 (HPM_IRQ_PERI_START + 18) +#define HPM_IRQ_UART1 (HPM_IRQ_PERI_START + 19) +#define HPM_IRQ_UART2 (HPM_IRQ_PERI_START + 20) +#define HPM_IRQ_UART3 (HPM_IRQ_PERI_START + 21) +#define HPM_IRQ_UART4 (HPM_IRQ_PERI_START + 22) +#define HPM_IRQ_UART5 (HPM_IRQ_PERI_START + 23) +#define HPM_IRQ_UART6 (HPM_IRQ_PERI_START + 24) +#define HPM_IRQ_UART7 (HPM_IRQ_PERI_START + 25) +#define HPM_IRQ_CAN0 (HPM_IRQ_PERI_START + 26) +#define HPM_IRQ_CAN1 (HPM_IRQ_PERI_START + 27) +#define HPM_IRQ_PTPC (HPM_IRQ_PERI_START + 28) +#define HPM_IRQ_WDG0 (HPM_IRQ_PERI_START + 29) +#define HPM_IRQ_WDG1 (HPM_IRQ_PERI_START + 30) +#define HPM_IRQ_TSNS (HPM_IRQ_PERI_START + 31) +#define HPM_IRQ_MBX0A (HPM_IRQ_PERI_START + 32) +#define HPM_IRQ_MBX0B (HPM_IRQ_PERI_START + 33) +#define HPM_IRQ_GPTMR0 (HPM_IRQ_PERI_START + 34) +#define HPM_IRQ_GPTMR1 (HPM_IRQ_PERI_START + 35) +#define HPM_IRQ_GPTMR2 (HPM_IRQ_PERI_START + 36) +#define HPM_IRQ_GPTMR3 (HPM_IRQ_PERI_START + 37) +#define HPM_IRQ_I2C0 (HPM_IRQ_PERI_START + 38) +#define HPM_IRQ_I2C1 (HPM_IRQ_PERI_START + 39) +#define HPM_IRQ_I2C2 (HPM_IRQ_PERI_START + 40) +#define HPM_IRQ_I2C3 (HPM_IRQ_PERI_START + 41) +#define HPM_IRQ_PWM0 (HPM_IRQ_PERI_START + 42) +#define HPM_IRQ_HALL0 (HPM_IRQ_PERI_START + 43) +#define HPM_IRQ_QEI0 (HPM_IRQ_PERI_START + 44) +#define HPM_IRQ_PWM1 (HPM_IRQ_PERI_START + 45) +#define HPM_IRQ_HALL1 (HPM_IRQ_PERI_START + 46) +#define HPM_IRQ_QEI1 (HPM_IRQ_PERI_START + 47) +#define HPM_IRQ_SDP (HPM_IRQ_PERI_START + 48) +#define HPM_IRQ_XPI0 (HPM_IRQ_PERI_START + 49) +#define HPM_IRQ_XPI1 (HPM_IRQ_PERI_START + 50) +#define HPM_IRQ_XDMA (HPM_IRQ_PERI_START + 51) +#define HPM_IRQ_HDMA (HPM_IRQ_PERI_START + 52) +#define HPM_IRQ_FEMC (HPM_IRQ_PERI_START + 53) +#define HPM_IRQ_RNG (HPM_IRQ_PERI_START + 54) +#define HPM_IRQ_I2S0 (HPM_IRQ_PERI_START + 55) +#define HPM_IRQ_I2S1 (HPM_IRQ_PERI_START + 56) +#define HPM_IRQ_DAO (HPM_IRQ_PERI_START + 57) +#define HPM_IRQ_PDM (HPM_IRQ_PERI_START + 58) +#define HPM_IRQ_EFA (HPM_IRQ_PERI_START + 59) +#define HPM_IRQ_NTMR0 (HPM_IRQ_PERI_START + 60) +#define HPM_IRQ_USB0 (HPM_IRQ_PERI_START + 61) +#define HPM_IRQ_ENET0 (HPM_IRQ_PERI_START + 62) +#define HPM_IRQ_SDXC0 (HPM_IRQ_PERI_START + 63) +#define HPM_IRQ_PSEC (HPM_IRQ_PERI_START + 64) +#define HPM_IRQ_PGPIO (HPM_IRQ_PERI_START + 65) +#define HPM_IRQ_PWDG (HPM_IRQ_PERI_START + 66) +#define HPM_IRQ_PTMR (HPM_IRQ_PERI_START + 67) +#define HPM_IRQ_PUART (HPM_IRQ_PERI_START + 68) +#define HPM_IRQ_FUSE (HPM_IRQ_PERI_START + 69) +#define HPM_IRQ_SECMON (HPM_IRQ_PERI_START + 70) +#define HPM_IRQ_RTC (HPM_IRQ_PERI_START + 71) +#define HPM_IRQ_BUTN (HPM_IRQ_PERI_START + 72) +#define HPM_IRQ_BGPIO (HPM_IRQ_PERI_START + 73) +#define HPM_IRQ_BVIO (HPM_IRQ_PERI_START + 74) +#define HPM_IRQ_BROWNOUT (HPM_IRQ_PERI_START + 75) +#define HPM_IRQ_SYSCTL (HPM_IRQ_PERI_START + 76) + +/* Total number of IRQs */ + +#define NR_IRQS (HPM_IRQ_PERI_START + 76) + +#endif /* __ARCH_RISCV_INCLUDE_HPM6000_HPM_IRQ_H */ diff --git a/arch/risc-v/include/hpm6000/irq.h b/arch/risc-v/include/hpm6000/irq.h new file mode 100644 index 0000000000000..c9ec41a1ae3c8 --- /dev/null +++ b/arch/risc-v/include/hpm6000/irq.h @@ -0,0 +1,34 @@ +/**************************************************************************** + * arch/risc-v/include/hpm6000/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_HPM6000_IRQ_H +#define __ARCH_RISCV_INCLUDE_HPM6000_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hpm_irq.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_RISCV_INCLUDE_HPM6000_IRQ_H */ diff --git a/arch/risc-v/include/irq.h b/arch/risc-v/include/irq.h index 9d587b6d3d980..ed3da17edb641 100644 --- a/arch/risc-v/include/irq.h +++ b/arch/risc-v/include/irq.h @@ -124,7 +124,7 @@ #define REG_X3_NDX 3 #define REG_X4_NDX 4 -/* $5-$7 = t0-t3: Temporary registers */ +/* $5-$7 = t0-t2: Temporary registers */ #define REG_X5_NDX 5 #define REG_X6_NDX 6 @@ -134,7 +134,7 @@ #define REG_X8_NDX 8 -/* $89 s1 Saved register */ +/* $9 s1 Saved register */ #define REG_X9_NDX 9 @@ -257,6 +257,29 @@ #define XCPTCONTEXT_SIZE (INT_XCPT_SIZE + FPU_XCPT_SIZE) #endif +#ifdef CONFIG_ARCH_RV_ISA_V +# define REG_VSTART_NDX (0) +# define REG_VTYPE_NDX (1) +# define REG_VL_NDX (2) +# define REG_VCSR_NDX (3) +# define REG_VLENB_NDX (4) + +# define VPU_XCPT_REGS (5) +# define VPU_XCPT_SIZE (INT_REG_SIZE * VPU_XCPT_REGS) + +# if CONFIG_ARCH_RV_VECTOR_BYTE_LENGTH > 0 + +/* There are 32 vector registers(v0 - v31) with vlenb length. */ + +# define VPU_XCPTC_SIZE (CONFIG_ARCH_RV_VECTOR_BYTE_LENGTH * 32 + VPU_XCPT_SIZE) + +# endif +#else /* !CONFIG_ARCH_RV_ISA_V */ +# define VPU_XCPT_REGS (0) +# define VPU_XCPT_SIZE (0) +# define VPU_XCPTC_SIZE (0) +#endif /* CONFIG_ARCH_RV_ISA_V */ + /* In assembly language, values have to be referenced as byte address * offsets. But in C, it is more convenient to reference registers as * register save table offsets. @@ -333,6 +356,14 @@ # define REG_FCSR (INT_REG_SIZE*REG_FCSR_NDX) #endif +#ifdef CONFIG_ARCH_RV_ISA_V +# define REG_VSTART (INT_REG_SIZE*REG_VSTART_NDX) +# define REG_VTYPE (INT_REG_SIZE*REG_VTYPE_NDX) +# define REG_VL (INT_REG_SIZE*REG_VL_NDX) +# define REG_VCSR (INT_REG_SIZE*REG_VCSR_NDX) +# define REG_VLENB (INT_REG_SIZE*REG_VLENB_NDX) +#endif + #else # define REG_EPC REG_EPC_NDX # define REG_X1 REG_X1_NDX @@ -404,6 +435,14 @@ # define REG_FCSR REG_FCSR_NDX #endif +#ifdef CONFIG_ARCH_RV_ISA_V +# define REG_VSTART REG_VSTART_NDX +# define REG_VTYPE REG_VTYPE_NDX +# define REG_VL REG_VL_NDX +# define REG_VCSR REG_VCSR_NDX +# define REG_VLENB REG_VLENB_NDX +#endif + #endif /* Now define more user friendly alternative name that can be used either @@ -579,6 +618,16 @@ struct xcptcontext #if defined(CONFIG_ARCH_FPU) && defined(CONFIG_ARCH_LAZYFPU) uintptr_t fregs[FPU_XCPT_REGS]; #endif + +#ifdef CONFIG_ARCH_RV_ISA_V +# if CONFIG_ARCH_RV_VECTOR_BYTE_LENGTH > 0 + /* There are 32 vector registers(v0 - v31) with vlenb length. */ + + uintptr_t vregs[VPU_XCPTC_SIZE]; +# else + uintptr_t *vregs; +# endif +#endif }; #endif /* __ASSEMBLY__ */ @@ -620,7 +669,7 @@ extern "C" #endif /* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt + * register storage structure. It is non-NULL only during interrupt * processing. Access to g_current_regs[] must be through the macro * CURRENT_REGS for portability. */ diff --git a/arch/risc-v/include/k230/irq.h b/arch/risc-v/include/k230/irq.h index 4e527c7c82d58..4b9b439a4e797 100644 --- a/arch/risc-v/include/k230/irq.h +++ b/arch/risc-v/include/k230/irq.h @@ -31,8 +31,22 @@ /* Map RISC-V exception code to NuttX IRQ */ -#define K230_IRQ_UART0 (RISCV_IRQ_MEXT + 16) +#ifndef CONFIG_BUILD_KERNEL +# define K230_IRQ_TIMER (RISCV_IRQ_MTIMER) +# define K230_IRQ_UART0 (RISCV_IRQ_MEXT + 16) +#else +# define K230_IRQ_TIMER (RISCV_IRQ_STIMER) +# define K230_IRQ_UART0 (RISCV_IRQ_SEXT + 16) +#endif -#define NR_IRQS (K230_IRQ_UART0 + 1) +#define K230_IRQ_UART3 (K230_IRQ_UART0 + 3) +#define K230_IRQ_IPI0 (K230_IRQ_UART0 + 93) +#define K230_IRQ_IPI3 (K230_IRQ_IPI0 + 3) + +#define K230_PLIC_IRQS 208 + +/* NR_IRQS is needed by NuttX */ + +#define NR_IRQS (K230_IRQ_IPI3 + 1) #endif /* __ARCH_RISCV_INCLUDE_K230_IRQ_H */ diff --git a/arch/risc-v/include/litex/irq.h b/arch/risc-v/include/litex/irq.h index 22e4660c8df4c..e01b4143910fc 100644 --- a/arch/risc-v/include/litex/irq.h +++ b/arch/risc-v/include/litex/irq.h @@ -46,7 +46,7 @@ /* The last hardware IRQ number */ -#define LITEX_LAST_IRQ (LITEX_IRQ_GPIO_BASE + LITEX_IRQ_GPIO_LENGTH) +#define LITEX_IRQ_LAST (LITEX_IRQ_GPIO_BASE + LITEX_IRQ_GPIO_LENGTH) /* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched * as a second level of decoding: The first level dispatches to the GPIO diff --git a/arch/risc-v/include/mode.h b/arch/risc-v/include/mode.h index 8e112a2b4e5c7..27bff35806dfd 100644 --- a/arch/risc-v/include/mode.h +++ b/arch/risc-v/include/mode.h @@ -36,13 +36,15 @@ /* CSR definitions */ -# define CSR_STATUS sstatus /* Global status register */ -# define CSR_SCRATCH sscratch /* Scratch register */ -# define CSR_EPC sepc /* Exception program counter */ -# define CSR_IE sie /* Interrupt enable register */ -# define CSR_CAUSE scause /* Interrupt cause register */ -# define CSR_TVAL stval /* Trap value register */ -# define CSR_TVEC stvec /* Trap vector base addr register */ +# define CSR_STATUS CSR_SSTATUS /* Global status register */ +# define CSR_SCRATCH CSR_SSCRATCH /* Scratch register */ +# define CSR_EPC CSR_SEPC /* Exception program counter */ +# define CSR_IE CSR_SIE /* Interrupt enable register */ +# define CSR_IP CSR_SIP /* Interrupt pending register */ +# define CSR_CAUSE CSR_SCAUSE /* Interrupt cause register */ +# define CSR_TVAL CSR_STVAL /* Trap value register */ +# define CSR_TVEC CSR_STVEC /* Trap vector base addr register */ +# define CSR_ENVCFG CSR_SENVCFG /* Env configuration register */ /* In status register */ @@ -57,6 +59,12 @@ # define IE_SIE SIE_SSIE /* Software interrupt enable */ # define IE_TIE SIE_STIE /* Timer interrupt enable */ +/* Interrupt pending bits */ + +# define IP_EIP SIP_SEIP /* External interrupt pending */ +# define IP_SIP SIP_SSIP /* Software interrupt pending */ +# define IP_TIP SIP_STIP /* Timer interrupt pending */ + /* External, timer and software interrupt */ # define RISCV_IRQ_EXT RISCV_IRQ_SEXT /* PLIC IRQ */ @@ -71,13 +79,15 @@ /* CSR definitions */ -# define CSR_STATUS mstatus /* Global status register */ -# define CSR_SCRATCH mscratch /* Scratch register */ -# define CSR_EPC mepc /* Exception program counter */ -# define CSR_IE mie /* Interrupt enable register */ -# define CSR_CAUSE mcause /* Interrupt cause register */ -# define CSR_TVAL mtval /* Trap value register */ -# define CSR_TVEC mtvec /* Trap vector base addr register */ +# define CSR_STATUS CSR_MSTATUS /* Global status register */ +# define CSR_SCRATCH CSR_MSCRATCH /* Scratch register */ +# define CSR_EPC CSR_MEPC /* Exception program counter */ +# define CSR_IE CSR_MIE /* Interrupt enable register */ +# define CSR_IP CSR_MIP /* Interrupt pending register */ +# define CSR_CAUSE CSR_MCAUSE /* Interrupt cause register */ +# define CSR_TVAL CSR_MTVAL /* Trap value register */ +# define CSR_TVEC CSR_MTVEC /* Trap vector base addr register */ +# define CSR_ENVCFG CSR_MENVCFG /* Env configuration register */ /* In status register */ @@ -92,6 +102,12 @@ # define IE_SIE MIE_MSIE /* Software interrupt enable */ # define IE_TIE MIE_MTIE /* Timer interrupt enable */ +/* Interrupt pending bits */ + +# define IP_EIP MIP_MEIP /* External interrupt pending */ +# define IP_SIP MIP_MSIP /* Software interrupt pending */ +# define IP_TIP MIP_MTIP /* Timer interrupt pending */ + /* External, timer and software interrupt */ # define RISCV_IRQ_EXT RISCV_IRQ_MEXT /* PLIC IRQ */ diff --git a/arch/risc-v/include/thead/c9xx_csr.h b/arch/risc-v/include/thead/c9xx_csr.h new file mode 100644 index 0000000000000..426181ce96fe3 --- /dev/null +++ b/arch/risc-v/include/thead/c9xx_csr.h @@ -0,0 +1,163 @@ +/**************************************************************************** + * arch/risc-v/include/thead/c9xx_csr.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_INCLUDE_THEAD_C9XX_CSR_H +#define __ARCH_RISCV_INCLUDE_THEAD_C9XX_CSR_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* T-HEAD C9xx Machine Control and Status extension Registers */ +#define THEAD_CSR_MXSTATUS 0x7c0 +#define THEAD_CSR_MHCR 0x7c1 +#define THEAD_CSR_MCOR 0x7c2 +#define THEAD_CSR_MCCR2 0x7c3 +#define THEAD_CSR_MCER2 0x7c4 +#define THEAD_CSR_MHINT 0x7c5 +#define THEAD_CSR_MRMR 0x7c6 +#define THEAD_CSR_MRVBR 0x7c7 +#define THEAD_CSR_MCER 0x7c8 +#define THEAD_CSR_MCOUNTERWEN 0x7c9 +#define THEAD_CSR_MCOUNTERINTEN 0x7ca +#define THEAD_CSR_MCOUNTEROF 0x7cb +#define THEAD_CSR_MHINT2 0x7cc +#define THEAD_CSR_MHINT3 0x7cd +#define THEAD_CSR_MRADDR 0x7e0 +#define THEAD_CSR_MEXSTATUS 0x7e1 +#define THEAD_CSR_MNMICAUSE 0x7e2 +#define THEAD_CSR_MNMIPC 0x7e3 +#define THEAD_CSR_MHPMCR 0x7f0 +#define THEAD_CSR_MHPMSR 0x7f1 +#define THEAD_CSR_MHPMER 0x7f2 +#define THEAD_CSR_MTEECFG 0x7f4 +#define THEAD_CSR_MZONEID 0x7f5 +#define THEAD_CSR_ML2CPID 0x7f6 +#define THEAD_CSR_ML2WP 0x7f7 +#define THEAD_CSR_MDTCMCR 0x7f8 +#define THEAD_CSR_USP 0x7d1 +#define THEAD_CSR_MEICR 0x7d6 +#define THEAD_CSR_MEICR2 0x7d7 +#define THEAD_CSR_MBEADDR 0x7d8 +#define THEAD_CSR_MWMSR 0xfc2 + +/* T-HEAD C9xx Machine Cache Access extension Registers */ +#define THEAD_CSR_MCINS 0x7d2 +#define THEAD_CSR_MCINDEX 0x7d3 +#define THEAD_CSR_MCDATA0 0x7d4 +#define THEAD_CSR_MCDATA1 0x7d5 + +/* T-HEAD C9xx Machine CPU model extension Registers */ +#define THEAD_CSR_MCPUID 0xfc0 +#define THEAD_CSR_MAPBADDR 0xfc1 + +/* T-HEAD C9xx Machine Multi-core extension Registers */ +#define THEAD_CSR_MSMPR 0x7f3 + +/* T-HEAD C9xx Machine Debug Registers. */ +#define THEAD_CSR_MHALTCAUSE 0xfe0 +#define THEAD_CSR_MDBGINFO 0xfe1 +#define THEAD_CSR_MPCFIFO 0xfe2 + +/* T-HEAD C9xx Supervisor Control and Status extension Registers */ +#define THEAD_CSR_SXSTATUS 0x5c0 +#define THEAD_CSR_SHCR 0x5c1 +#define THEAD_CSR_SCER2 0x5c2 +#define THEAD_CSR_SCER 0x5c3 +#define THEAD_CSR_SCOUNTERINTEN 0x5c4 +#define THEAD_CSR_SCOUNTEROF 0x5c5 +#define THEAD_CSR_SHINT 0x5c6 +#define THEAD_CSR_SHINT2 0x5c7 +#define THEAD_CSR_SHPMINHIBIT 0x5c8 +#define THEAD_CSR_SHPMCR 0x5c9 +#define THEAD_CSR_SHPMSR 0x5ca +#define THEAD_CSR_SHPMER 0x5cb +#define THEAD_CSR_SL2CPID 0x5cc +#define THEAD_CSR_SL2WP 0x5cd +#define THEAD_CSR_SBEADDR 0x5d0 +#define THEAD_CSR_SCYCLE 0x5e0 +#define THEAD_CSR_SINSTRET 0x5e2 +#define THEAD_CSR_SHPMCOUNTER1 0x5e1 +#define THEAD_CSR_SHPMCOUNTER2 0x5e2 +#define THEAD_CSR_SHPMCOUNTER3 0x5e3 +#define THEAD_CSR_SHPMCOUNTER4 0x5e4 +#define THEAD_CSR_SHPMCOUNTER5 0x5e5 +#define THEAD_CSR_SHPMCOUNTER6 0x5e6 +#define THEAD_CSR_SHPMCOUNTER7 0x5e7 +#define THEAD_CSR_SHPMCOUNTER8 0x5e8 +#define THEAD_CSR_SHPMCOUNTER9 0x5e9 +#define THEAD_CSR_SHPMCOUNTER10 0x5ea +#define THEAD_CSR_SHPMCOUNTER11 0x5eb +#define THEAD_CSR_SHPMCOUNTER12 0x5ec +#define THEAD_CSR_SHPMCOUNTER13 0x5ed +#define THEAD_CSR_SHPMCOUNTER14 0x5ee +#define THEAD_CSR_SHPMCOUNTER15 0x5ef +#define THEAD_CSR_SHPMCOUNTER16 0x5f0 +#define THEAD_CSR_SHPMCOUNTER17 0x5f1 +#define THEAD_CSR_SHPMCOUNTER18 0x5f2 +#define THEAD_CSR_SHPMCOUNTER19 0x5f3 +#define THEAD_CSR_SHPMCOUNTER20 0x5f4 +#define THEAD_CSR_SHPMCOUNTER21 0x5f5 +#define THEAD_CSR_SHPMCOUNTER22 0x5f6 +#define THEAD_CSR_SHPMCOUNTER23 0x5f7 +#define THEAD_CSR_SHPMCOUNTER24 0x5f8 +#define THEAD_CSR_SHPMCOUNTER25 0x5f9 +#define THEAD_CSR_SHPMCOUNTER26 0x5fa +#define THEAD_CSR_SHPMCOUNTER27 0x5fb +#define THEAD_CSR_SHPMCOUNTER28 0x5fc +#define THEAD_CSR_SHPMCOUNTER29 0x5fd +#define THEAD_CSR_SHPMCOUNTER30 0x5fe +#define THEAD_CSR_SHPMCOUNTER31 0x5ff + +/* T-HEAD C9xx Supervisor MMU extension Registers */ +#define THEAD_CSR_SMIR 0x9c0 +#define THEAD_CSR_SMEL 0x9c1 +#define THEAD_CSR_SMEH 0x9c2 +#define THEAD_CSR_SMCIR 0x9c3 + +/* T-HEAD C9xx User Floating-point control Registers. */ +#define THEAD_CSR_FXCR 0x800 + +/* In mxstatus register */ + +/* U-mode performance monitoring count enable */ +#define THEAD_MXSTATUS_PMDU (1 << 10) +/* S-mode performance monitoring count enable */ +#define THEAD_MXSTATUS_PMDS (1 << 11) +/* M-mode performance monitoring count enable */ +#define THEAD_MXSTATUS_PMDM (1 << 13) +/* PMP minimum granularity control */ +#define THEAD_MXSTATUS_PMP4K (1 << 14) +/* Misaligned access enable */ +#define THEAD_MXSTATUS_MM (1 << 15) +/* Execute extended cache instructions in U-mode */ +#define THEAD_MXSTATUS_UCME (1 << 16) +/* Clint timer/software interrupt supervisor extension enable */ +#define THEAD_MXSTATUS_CLINTEE (1 << 17) +/* Disable hardware writeback */ +#define THEAD_MXSTATUS_MHRD (1 << 18) +/* Disable Icache snoop D-Cache */ +#define THEAD_MXSTATUS_INSDE (1 << 19) +/* Extend MMU address attribute */ +#define THEAD_MXSTATUS_MAEE (1 << 21) +/* Enables extended instruction sets */ +#define THEAD_MXSTATUS_ISAEE (1 << 22) + +#endif /* __ARCH_RISCV_INCLUDE_THEAD_C9XX_CSR_H */ diff --git a/arch/risc-v/src/CMakeLists.txt b/arch/risc-v/src/CMakeLists.txt index 8dda0f61b0569..6aaeb2bd658b6 100644 --- a/arch/risc-v/src/CMakeLists.txt +++ b/arch/risc-v/src/CMakeLists.txt @@ -21,11 +21,16 @@ add_subdirectory(${NUTTX_CHIP_ABS_DIR} EXCLUDE_FROM_ALL exclude_chip) add_subdirectory(common) +if(CONFIG_BUILD_KERNEL) + add_subdirectory(nuttsbi) + target_include_directories(arch BEFORE PUBLIC ${NUTTX_CHIP_ABS_DIR} nuttsbi) +endif() + # Include directories (before system ones) as PUBLIC so that it can be exposed # to libboard target_include_directories(arch BEFORE PUBLIC ${NUTTX_CHIP_ABS_DIR} common) -if(NOT CONFIG_BUILD_FLAT) +if(CONFIG_BUILD_PROTECTED) target_include_directories(arch_interface BEFORE PUBLIC ${NUTTX_CHIP_ABS_DIR} common) endif() diff --git a/arch/risc-v/src/Makefile b/arch/risc-v/src/Makefile index 0b23888be0eed..6a057638f938a 100644 --- a/arch/risc-v/src/Makefile +++ b/arch/risc-v/src/Makefile @@ -18,7 +18,7 @@ # ############################################################################ -include $(TOPDIR)/Make.defs +include $(TOPDIR)/tools/apps-or-nuttx-Make.defs include chip/Make.defs ifeq ($(CONFIG_OPENSBI),y) include opensbi/Make.defs @@ -26,12 +26,6 @@ else ifeq ($(CONFIG_NUTTSBI),y) include nuttsbi/Make.defs endif -# Kernel runs in supervisor mode or machine mode ? - -ifeq ($(CONFIG_ARCH_USE_S_MODE),y) -include common/supervisor/Make.defs -endif - ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip @@ -107,11 +101,13 @@ ifeq ($(LD),$(CC)) # -fstack-protector-explicit STRIPCFLAGS = $(filter -fstack-protector%,$(CFLAGS)) endif + LDENTRY ?= -Wl,--entry=__start LDSTARTGROUP ?= -Wl,--start-group LDENDGROUP ?= -Wl,--end-group LDFLAGS := $(addprefix -Xlinker ,$(LDFLAGS)) LDFLAGS += $(filter-out $(STRIPCFLAGS),$(CFLAGS)) else + LDENTRY ?= --entry=__start LDSTARTGROUP ?= --start-group LDENDGROUP ?= --end-group endif @@ -130,6 +126,7 @@ endif VPATH += chip VPATH += common +VPATH += common/espressif VPATH += $(SBI_DIR) VPATH += $(ARCH_SUBDIR) VPATH += $(CHIP_DIR) @@ -161,13 +158,27 @@ $(KBIN): $(OBJS) board/libboard$(LIBEXT): $(Q) $(MAKE) -C board libboard$(LIBEXT) EXTRAFLAGS="$(EXTRAFLAGS)" -define LINK_ALLSYMS - $(Q) $(TOPDIR)/tools/mkallsyms.py $(NUTTX) allsyms.tmp +# When multiple linking, these two additional linking objects will be included + +ifeq ($(CONFIG_MM_KASAN_GLOBAL),y) +EXTRA_LIBS += kasan_globals$(OBJEXT) +endif +ifeq ($(CONFIG_ALLSYMS),y) +EXTRA_LIBS += allsyms$(OBJEXT) +endif + +define LINK_ALLSYMS_KASAN + $(if $(CONFIG_ALLSYMS), + $(Q) $(TOPDIR)/tools/mkallsyms.py $(NUTTX) allsyms.tmp --orderbyname $(CONFIG_SYMTAB_ORDEREDBYNAME) $(Q) $(call COMPILE, allsyms.tmp, allsyms$(OBJEXT), -x c) - $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ - -o $(NUTTX) $(HEAD_OBJ) allsyms$(OBJEXT) $(EXTRA_OBJS) \ + $(Q) $(call DELFILE, allsyms.tmp)) + $(if $(CONFIG_MM_KASAN_GLOBAL), + $(Q) $(TOPDIR)/tools/kasan_global.py -e $(NUTTX) -o kasan_globals.tmp + $(Q) $(call COMPILE, kasan_globals.tmp, kasan_globals$(OBJEXT) -fno-sanitize=kernel-address, -x c) + $(Q) $(call DELFILE, kasan_globals.tmp)) + $(Q) $(LD) $(LDENTRY) $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ + -o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \ $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) - $(Q) $(call DELFILE, allsyms.tmp allsyms$(OBJEXT)) endef $(addsuffix .tmp,$(ARCHSCRIPT)): $(ARCHSCRIPT) @@ -175,17 +186,19 @@ $(addsuffix .tmp,$(ARCHSCRIPT)): $(ARCHSCRIPT) nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT) $(addsuffix .tmp,$(ARCHSCRIPT)) $(Q) echo "LD: nuttx" -ifneq ($(CONFIG_ALLSYMS),y) - $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ +ifeq ($(CONFIG_ALLSYMS)$(CONFIG_MM_KASAN_GLOBAL),) + $(Q) $(LD) $(LDENTRY) $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ -o $(NUTTX) $(HEAD_OBJ) $(EXTRA_OBJS) \ $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) else - $(Q) # Link and generate default table - $(Q) $(if $(wildcard $(shell echo $(NUTTX))),,$(call LINK_ALLSYMS,$^)) - $(Q) # Extract all symbols - $(Q) $(call LINK_ALLSYMS, $^) - $(Q) # Extract again since the table offset may changed - $(Q) $(call LINK_ALLSYMS, $^) + $(Q) $(call LINK_ALLSYMS_KASAN) + $(Q) $(call LINK_ALLSYMS_KASAN) + $(Q) $(call LINK_ALLSYMS_KASAN) + $(Q) $(call LINK_ALLSYMS_KASAN) +endif +ifeq ($(CONFIG_MM_KASAN_GLOBAL),y) + $(Q) $(OBJCOPY) -R .kasan.global $(NUTTX) + $(Q) $(OBJCOPY) -R .kasan.unused $(NUTTX) endif ifneq ($(CONFIG_WINDOWS_NATIVE),y) $(Q) $(NM) $(NUTTX) | \ diff --git a/arch/risc-v/src/bl602/bl602_allocateheap.c b/arch/risc-v/src/bl602/bl602_allocateheap.c index 2f6d79876f07a..f0d8eea3c14d3 100644 --- a/arch/risc-v/src/bl602/bl602_allocateheap.c +++ b/arch/risc-v/src/bl602/bl602_allocateheap.c @@ -28,13 +28,13 @@ #include #include "chip.h" +#include "riscv_internal.h" /**************************************************************************** * Public Variables ****************************************************************************/ -extern uint8_t _heap_start[]; -extern uint8_t _heap_size[]; +extern uint8_t __heap_end[]; extern uint8_t _heap_wifi_start[]; extern uint8_t _heap_wifi_size[]; @@ -59,8 +59,8 @@ extern uint8_t _heap_wifi_size[]; void up_allocate_heap(void **heap_start, size_t *heap_size) { - *heap_start = (void *)_heap_start; - *heap_size = (size_t)_heap_size; + *heap_start = (void *)g_idle_topstack; + *heap_size = (size_t)((uintptr_t)__heap_end - g_idle_topstack); } /**************************************************************************** diff --git a/arch/risc-v/src/bl602/bl602_head.S b/arch/risc-v/src/bl602/bl602_head.S index ce14082bdb846..b98c2f8e1d19f 100644 --- a/arch/risc-v/src/bl602/bl602_head.S +++ b/arch/risc-v/src/bl602/bl602_head.S @@ -25,6 +25,8 @@ #include #include +#include "riscv_internal.h" + .section .init .globl bl602_start .globl __start @@ -40,16 +42,13 @@ bl602_start: /*disable IRQ*/ li t0, MSTATUS_MIE - csrc mstatus, t0 + csrc CSR_MSTATUS, t0 la gp, __global_pointer$ .option pop - la sp, g_idle_stack - add s11, sp, zero - - li t0, CONFIG_IDLETHREAD_STACKSIZE + la sp, _ebss + li t0, SMP_STACK_SIZE add sp, sp, t0 - andi sp, sp, ~0xF #ifndef RUN_IN_RAM @@ -104,8 +103,8 @@ bl602_entry_load_data_section_end: /* Clear bss section */ - la a0, __bss_start - la a1, __bss_end + la a0, _sbss + la a1, _ebss bgeu a0, a1, bl602_entry_zero_bss_end bl602_entry_zero_bss_loop: diff --git a/arch/risc-v/src/bl602/bl602_irq.c b/arch/risc-v/src/bl602/bl602_irq.c index cad2b281b9d66..f93e1bc80746e 100644 --- a/arch/risc-v/src/bl602/bl602_irq.c +++ b/arch/risc-v/src/bl602/bl602_irq.c @@ -108,7 +108,7 @@ void up_disable_irq(int irq) { /* Read mstatus & clear machine software interrupt enable in mie */ - CLEAR_CSR(mie, MIE_MSIE); + CLEAR_CSR(CSR_MIE, MIE_MSIE); } else if (irq == RISCV_IRQ_MTIMER) { @@ -116,7 +116,7 @@ void up_disable_irq(int irq) /* Read mstatus & clear machine timer interrupt enable in mie */ - CLEAR_CSR(mie, MIE_MTIE); + CLEAR_CSR(CSR_MIE, MIE_MTIE); } else { @@ -139,7 +139,7 @@ void up_enable_irq(int irq) { /* Read mstatus & set machine software interrupt enable in mie */ - SET_CSR(mie, MIE_MSIE); + SET_CSR(CSR_MIE, MIE_MSIE); } else if (irq == RISCV_IRQ_MTIMER) { @@ -147,7 +147,7 @@ void up_enable_irq(int irq) /* Read mstatus & set machine timer interrupt enable in mie */ - SET_CSR(mie, MIE_MTIE | 0x1 << 11); + SET_CSR(CSR_MIE, MIE_MTIE | 0x1 << 11); } else { @@ -182,10 +182,10 @@ irqstate_t up_irq_enable(void) /* Enable MEIE (machine external interrupt enable) */ - SET_CSR(mie, MIE_MEIE); + SET_CSR(CSR_MIE, MIE_MEIE); /* Read mstatus & set machine interrupt enable (MIE) in mstatus */ - oldstat = READ_AND_SET_CSR(mstatus, MSTATUS_MIE); + oldstat = READ_AND_SET_CSR(CSR_MSTATUS, MSTATUS_MIE); return oldstat; } diff --git a/arch/risc-v/src/bl602/bl602_netdev.c b/arch/risc-v/src/bl602/bl602_netdev.c index 9ca67224ef730..539655441e350 100644 --- a/arch/risc-v/src/bl602/bl602_netdev.c +++ b/arch/risc-v/src/bl602/bl602_netdev.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/risc-v/src/bl602/bl602_os_hal.c b/arch/risc-v/src/bl602/bl602_os_hal.c index 4a3120498b1b4..06c06cb8f44ca 100644 --- a/arch/risc-v/src/bl602/bl602_os_hal.c +++ b/arch/risc-v/src/bl602/bl602_os_hal.c @@ -933,7 +933,7 @@ void *bl_os_timer_create(void *func, void *argv) struct timer_adpt *timer = kmm_malloc(sizeof(struct timer_adpt)); if (!timer) { - assert(0); + ASSERT(0); } memset((void *)timer, 0, sizeof(struct timer_adpt)); @@ -1066,7 +1066,7 @@ void *bl_os_workqueue_create(void) struct work_s *work = kmm_calloc(1, sizeof(struct work_s)); if (!work) { - assert(0); + ASSERT(0); } return (void *)work; diff --git a/arch/risc-v/src/bl602/bl602_serial.c b/arch/risc-v/src/bl602/bl602_serial.c index 21db1149eabdd..f9b5d033349e2 100644 --- a/arch/risc-v/src/bl602/bl602_serial.c +++ b/arch/risc-v/src/bl602/bl602_serial.c @@ -888,7 +888,7 @@ void riscv_serialinit(void) int up_putc(int ch) { #ifdef HAVE_SERIAL_CONSOLE - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(NULL); /* Check for LF */ @@ -900,7 +900,7 @@ int up_putc(int ch) } riscv_lowputc(ch); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); #endif return ch; } diff --git a/arch/risc-v/src/bl602/bl602_start.c b/arch/risc-v/src/bl602/bl602_start.c index e50f77bd864f2..104a72bc2f56f 100644 --- a/arch/risc-v/src/bl602/bl602_start.c +++ b/arch/risc-v/src/bl602/bl602_start.c @@ -52,25 +52,10 @@ #define showprogress(c) #endif -#define BL602_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE) - /**************************************************************************** * Private Data ****************************************************************************/ -/* g_idle_topstack: _sbss is the start of the BSS region as defined by the - * linker script. _ebss lies at the end of the BSS region. The idle task - * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. - * The IDLE thread is the thread that the system boots on and, eventually, - * becomes the IDLE, do nothing task that runs only when there is nothing - * else to run. The heap continues from there until the end of memory. - * g_idle_topstack is a read-only variable the provides this computed - * address. - */ - -uint8_t g_idle_stack[BL602_IDLESTACK_SIZE] - locate_data(".noinit_idle_stack"); - /* Dont change the name of variable, since we refer this * g_boot2_partition_table in linker script */ @@ -81,8 +66,6 @@ static struct boot2_partition_table_s g_boot2_partition_table used_data; * Public Data ****************************************************************************/ -uintptr_t g_idle_topstack; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -165,10 +148,6 @@ void bfl_main(void) asm volatile("csrw mtvec, %0" ::"r"((uintptr_t)exception_common + 2)); - /* Configure IDLE stack */ - - g_idle_topstack = ((uint32_t)g_idle_stack + BL602_IDLESTACK_SIZE); - /* Configure the UART so we can get debug output */ bl602_lowsetup(); diff --git a/arch/risc-v/src/bl808/bl808_head.S b/arch/risc-v/src/bl808/bl808_head.S index 3b8258640266d..090fd9125241d 100644 --- a/arch/risc-v/src/bl808/bl808_head.S +++ b/arch/risc-v/src/bl808/bl808_head.S @@ -29,6 +29,7 @@ #include "chip.h" #include "riscv_internal.h" +#include "riscv_macros.S" /**************************************************************************** * Public Symbols @@ -68,13 +69,6 @@ __start: real_start: - /* Set stack pointer to the idle thread stack */ - - bnez a0, 1f - la sp, BL808_IDLESTACK_TOP - j 2f -1: - /* Load the number of CPUs that the kernel supports */ #ifdef CONFIG_SMP @@ -86,45 +80,19 @@ real_start: /* If a0 (hartid) >= t1 (the number of CPUs), stop here */ blt a0, t1, 3f - csrw sie, zero + csrw CSR_SIE, zero wfi 3: - /* To get g_cpu_basestack[hartid], must get g_cpu_basestack first */ - - la t0, g_cpu_basestack - - /* Offset = pointer width * hart id */ - -#ifdef CONFIG_ARCH_RV32 - slli t1, a0, 2 -#else - slli t1, a0, 3 -#endif - add t0, t0, t1 - - /* Load idle stack base to sp */ - - REGLOAD sp, 0(t0) - - /* - * sp (stack top) = sp + idle stack size - XCPTCONTEXT_SIZE - * - * Note: Reserve some space used by up_initial_state since we are already - * running and using the per CPU idle stack. - */ - - li t0, STACK_ALIGN_UP(CONFIG_IDLETHREAD_STACKSIZE - XCPTCONTEXT_SIZE) - add sp, sp, t0 - -2: + /* Set stack pointer to the idle thread stack */ + riscv_set_inital_sp BL808_IDLESTACK_BASE, SMP_STACK_SIZE, a0 /* Disable all interrupts (i.e. timer, external) in sie */ - csrw sie, zero + csrw CSR_SIE, zero la t0, __trap_vec - csrw stvec, t0 + csrw CSR_STVEC, t0 /* Jump to bl808_start */ diff --git a/arch/risc-v/src/bl808/bl808_irq.c b/arch/risc-v/src/bl808/bl808_irq.c index 1e52f1580d68c..841c1c82ade38 100644 --- a/arch/risc-v/src/bl808/bl808_irq.c +++ b/arch/risc-v/src/bl808/bl808_irq.c @@ -33,6 +33,7 @@ #include #include "riscv_internal.h" +#include "riscv_ipi.h" #include "chip.h" /**************************************************************************** @@ -86,9 +87,9 @@ void up_irqinitialize(void) putreg32(0, BL808_PLIC_THRESHOLD); #ifdef CONFIG_SMP - /* Clear RISCV_IPI for CPU0 */ + /* Clear IPI for CPU0 */ - putreg32(0, RISCV_IPI); + riscv_ipi_clear(0); up_enable_irq(RISCV_IRQ_SOFT); #endif diff --git a/arch/risc-v/src/bl808/bl808_memorymap.h b/arch/risc-v/src/bl808/bl808_memorymap.h index 7dff2e7795cdb..d820cc412ce33 100644 --- a/arch/risc-v/src/bl808/bl808_memorymap.h +++ b/arch/risc-v/src/bl808/bl808_memorymap.h @@ -39,7 +39,4 @@ #define BL808_IDLESTACK_BASE _ebss #endif -#define BL808_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3) -#define BL808_IDLESTACK_TOP (BL808_IDLESTACK_BASE + BL808_IDLESTACK_SIZE) - #endif /* __ARCH_RISCV_SRC_BL808_BL808_MEMORYMAP_H */ diff --git a/arch/risc-v/src/bl808/bl808_mm_init.c b/arch/risc-v/src/bl808/bl808_mm_init.c index 2a0ee3d29b2d3..9245af153fe13 100644 --- a/arch/risc-v/src/bl808/bl808_mm_init.c +++ b/arch/risc-v/src/bl808/bl808_mm_init.c @@ -74,8 +74,8 @@ #define SLAB_COUNT (sizeof(m_l3_pgtable) / RV_MMU_PAGE_SIZE) #define KMM_PAGE_SIZE RV_MMU_L3_PAGE_SIZE -#define KMM_PBASE PGT_L3_PBASE -#define KMM_PBASE_IDX 3 +#define KMM_PBASE PGT_L3_PBASE +#define KMM_PBASE_IDX 3 #define KMM_SPBASE PGT_L2_PBASE #define KMM_SPBASE_IDX 2 @@ -171,7 +171,7 @@ static uintptr_t slab_alloc(void) ****************************************************************************/ static void map_region(uintptr_t paddr, uintptr_t vaddr, size_t size, - uint32_t mmuflags) + uint64_t mmuflags) { uintptr_t endaddr; uintptr_t pbase; @@ -235,8 +235,7 @@ void bl808_kernel_mappings(void) /* Begin mapping memory to MMU; note that at this point the MMU is not yet * active, so the page table virtual addresses are actually physical - * addresses and so forth. M-mode does not perform translations anyhow, so - * this mapping is quite simple to do + * addresses and so forth. */ /* Map I/O region, use enough large page tables for the IO region. */ @@ -291,8 +290,35 @@ void bl808_mm_init(void) bl808_kernel_mappings(); - /* Enable MMU (note: system is still in M-mode) */ + /* Enable MMU */ binfo("mmu_enable: satp=%" PRIuPTR "\n", g_kernel_pgt_pbase); mmu_enable(g_kernel_pgt_pbase, 0); } + +/**************************************************************************** + * Name: mmu_flush_cache + * + * Description: + * Flush the MMU Cache for T-Head C906. Called by mmu_write_satp() after + * updating the MMU SATP Register, when swapping MMU Page Tables. + * This operation executes RISC-V Instructions that are specific to + * T-Head C906. + * + ****************************************************************************/ + +void weak_function mmu_flush_cache(uintptr_t reg) +{ + UNUSED(reg); + __asm__ __volatile__ + ( + + /* DCACHE.IALL: Invalidate all Page Table Entries in the D-Cache */ + + ".long 0x0020000b\n" + + /* SYNC.S: Ensure that all Cache Operations are completed */ + + ".long 0x0190000b\n" + ); +} diff --git a/arch/risc-v/src/bl808/bl808_start.c b/arch/risc-v/src/bl808/bl808_start.c index 62fedf2acb50f..7e0663b6038dc 100644 --- a/arch/risc-v/src/bl808/bl808_start.c +++ b/arch/risc-v/src/bl808/bl808_start.c @@ -58,12 +58,6 @@ extern void __trap_vec(void); * Public Data ****************************************************************************/ -/* NOTE: g_idle_topstack needs to point the top of the idle stack - * for CPU0 and this value is used in up_initial_state() - */ - -uintptr_t g_idle_topstack = BL808_IDLESTACK_TOP; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -113,7 +107,7 @@ static void bl808_copy_overlap(uint8_t *dest, const uint8_t *src, static void bl808_copy_ramdisk(void) { const char *header = "-rom1fs-"; - const uint8_t *limit = (uint8_t *)BL808_IDLESTACK_TOP + (256 * 1024); + const uint8_t *limit = (uint8_t *)g_idle_topstack + (256 * 1024); uint8_t *ramdisk_addr = NULL; uint8_t *addr; uint32_t size; @@ -122,9 +116,9 @@ static void bl808_copy_ramdisk(void) * Limit search to 256 KB after Idle Stack Top. */ - binfo("_edata=%p, _sbss=%p, _ebss=%p, BL808_IDLESTACK_TOP=%p\n", + binfo("_edata=%p, _sbss=%p, _ebss=%p, idlestack_top=%p\n", (void *)_edata, (void *)_sbss, (void *)_ebss, - (void *)BL808_IDLESTACK_TOP); + (void *)g_idle_topstack); for (addr = _edata; addr < limit; addr++) { if (memcmp(addr, header, strlen(header)) == 0) @@ -145,9 +139,9 @@ static void bl808_copy_ramdisk(void) /* RAM Disk must be after Idle Stack, to prevent overwriting */ - if (ramdisk_addr <= (uint8_t *)BL808_IDLESTACK_TOP) + if (ramdisk_addr <= (uint8_t *)g_idle_topstack) { - const size_t pad = (size_t)BL808_IDLESTACK_TOP - (size_t)ramdisk_addr; + const size_t pad = (size_t)g_idle_topstack - (size_t)ramdisk_addr; _err("RAM Disk must be after Idle Stack. Increase initrd padding " "by %ul bytes.", pad); PANIC(); @@ -284,11 +278,11 @@ void bl808_start(int mhartid) /* Disable MMU */ - WRITE_CSR(satp, 0x0); + WRITE_CSR(CSR_SATP, 0x0); /* Set the trap vector for S-mode */ - WRITE_CSR(stvec, (uintptr_t)__trap_vec); + WRITE_CSR(CSR_STVEC, (uintptr_t)__trap_vec); /* Start S-mode */ diff --git a/arch/risc-v/src/bl808/bl808_timerisr.c b/arch/risc-v/src/bl808/bl808_timerisr.c index 6b3db6eafd2d1..2cfc5c0cc358b 100644 --- a/arch/risc-v/src/bl808/bl808_timerisr.c +++ b/arch/risc-v/src/bl808/bl808_timerisr.c @@ -29,62 +29,16 @@ #include #include -#include -#include -#include -#include #include -#include #include "riscv_internal.h" #include "riscv_mtimer.h" -#include "riscv_percpu.h" -#include "hardware/bl808_memorymap.h" /**************************************************************************** - * Private Data + * Pre-processor Definitions ****************************************************************************/ -static uint32_t g_stimer_pending = false; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: bl808_ssoft_interrupt - * - * Description: - * This function is S-mode software interrupt handler to proceed - * the OS timer - * - ****************************************************************************/ - -static int bl808_ssoft_interrupt(int irq, void *context, void *arg) -{ - /* Cleaer Supervisor Software Interrupt */ - - CLEAR_CSR(sip, SIP_SSIP); - - if (g_stimer_pending) - { - g_stimer_pending = false; - - /* Proceed the OS timer */ - - nxsched_process_timer(); - } -#ifdef CONFIG_SMP - else - { - /* We assume IPI has been issued */ - - riscv_pause_handler(irq, context, arg); - } -#endif - - return 0; -} +#define MTIMER_FREQ 1000000 /**************************************************************************** * Public Functions @@ -101,6 +55,15 @@ static int bl808_ssoft_interrupt(int irq, void *context, void *arg) void up_timer_initialize(void) { - irq_attach(RISCV_IRQ_SSOFT, bl808_ssoft_interrupt, NULL); - up_enable_irq(RISCV_IRQ_SSOFT); + struct oneshot_lowerhalf_s *lower; + + /* Initialize the OpenSBI Timer. mtime and mtimecmp are unused for + * OpenSBI. + */ + + lower = riscv_mtimer_initialize(0, 0, RISCV_IRQ_STIMER, MTIMER_FREQ); + + DEBUGASSERT(lower != NULL); + + up_alarm_set_lowerhalf(lower); } diff --git a/arch/risc-v/src/c906/c906_head.S b/arch/risc-v/src/c906/c906_head.S index a5ad86eadcbc0..707b62db8174b 100644 --- a/arch/risc-v/src/c906/c906_head.S +++ b/arch/risc-v/src/c906/c906_head.S @@ -59,16 +59,14 @@ __start: * mxstatus is a CSR which locates at 0x7C0. */ -#ifdef __riscv_xthead - li t0, (1 << 22) | (1 << 21) | (1 << 15) - csrr t1, mxstatus + li t0, THEAD_MXSTATUS_ISAEE | THEAD_MXSTATUS_MAEE | THEAD_MXSTATUS_MM + csrr t1, THEAD_CSR_MXSTATUS or t0, t1, t0 - csrw mxstatus, t0 -#endif + csrw THEAD_CSR_MXSTATUS, t0 /* Load mhartid (cpuid) */ - csrr a0, mhartid + csrr a0, CSR_MHARTID /* Set stack pointer to the idle thread stack */ @@ -76,13 +74,13 @@ __start: /* Disable all interrupts (i.e. timer, external) in mie */ - csrw mie, zero - csrw mip, zero + csrw CSR_MIE, zero + csrw CSR_MIP, zero /* Initialize the Machine Trap Vector */ la t0, __trap_vec - csrw mtvec, t0 + csrw CSR_MTVEC, t0 /* Jump to __c906_start with mhartid */ diff --git a/arch/risc-v/src/c906/c906_irq.c b/arch/risc-v/src/c906/c906_irq.c index 980959f39fc73..f79d5dd9b7c72 100644 --- a/arch/risc-v/src/c906/c906_irq.c +++ b/arch/risc-v/src/c906/c906_irq.c @@ -111,13 +111,13 @@ void up_disable_irq(int irq) { /* Read mstatus & clear machine software interrupt enable in mie */ - CLEAR_CSR(mie, MIE_MSIE); + CLEAR_CSR(CSR_MIE, MIE_MSIE); } else if (irq == RISCV_IRQ_MTIMER) { /* Read mstatus & clear machine timer interrupt enable in mie */ - CLEAR_CSR(mie, MIE_MTIE); + CLEAR_CSR(CSR_MIE, MIE_MTIE); } else if (irq >= C906_IRQ_PERI_START) { @@ -153,13 +153,13 @@ void up_enable_irq(int irq) { /* Read mstatus & set machine software interrupt enable in mie */ - SET_CSR(mie, MIE_MSIE); + SET_CSR(CSR_MIE, MIE_MSIE); } else if (irq == RISCV_IRQ_MTIMER) { /* Read mstatus & set machine timer interrupt enable in mie */ - SET_CSR(mie, MIE_MTIE); + SET_CSR(CSR_MIE, MIE_MTIE); } else if (irq >= C906_IRQ_PERI_START) { @@ -207,10 +207,10 @@ irqstate_t up_irq_enable(void) /* TODO: should move to up_enable_irq() */ - SET_CSR(mie, MIE_MEIE); + SET_CSR(CSR_MIE, MIE_MEIE); /* Read mstatus & set machine interrupt enable (MIE) in mstatus */ - oldstat = READ_AND_SET_CSR(mstatus, MSTATUS_MIE); + oldstat = READ_AND_SET_CSR(CSR_MSTATUS, MSTATUS_MIE); return oldstat; } diff --git a/arch/risc-v/src/c906/c906_memorymap.h b/arch/risc-v/src/c906/c906_memorymap.h index 4f7a01254e93f..8ee10abee2d50 100644 --- a/arch/risc-v/src/c906/c906_memorymap.h +++ b/arch/risc-v/src/c906/c906_memorymap.h @@ -44,7 +44,7 @@ #define C906_IDLESTACK_BASE _ebss #endif -#define C906_IDLESTACK0_TOP (C906_IDLESTACK_BASE + CONFIG_IDLETHREAD_STACKSIZE) +#define C906_IDLESTACK0_TOP (C906_IDLESTACK_BASE + SMP_STACK_SIZE) #define C906_IDLESTACK_TOP (C906_IDLESTACK0_TOP) #endif /* __ARCH_RISCV_SRC_C906_C906_MEMORYMAP_H */ diff --git a/arch/risc-v/src/c906/c906_serial.c b/arch/risc-v/src/c906/c906_serial.c index e7e43837fbee0..fb1341d11542f 100644 --- a/arch/risc-v/src/c906/c906_serial.c +++ b/arch/risc-v/src/c906/c906_serial.c @@ -214,12 +214,12 @@ static void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) { - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(NULL); priv->im = im; up_serialout(priv, UART_IE_OFFSET, im); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -228,7 +228,7 @@ static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) { - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(NULL); /* Return the current interrupt mask value */ @@ -241,7 +241,7 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) priv->im = 0; up_serialout(priv, UART_IE_OFFSET, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/risc-v/src/c906/c906_start.c b/arch/risc-v/src/c906/c906_start.c index 9ac201fa03c25..a6ec7d9d3811d 100644 --- a/arch/risc-v/src/c906/c906_start.c +++ b/arch/risc-v/src/c906/c906_start.c @@ -48,18 +48,6 @@ * Public Data ****************************************************************************/ -/* g_idle_topstack: _sbss is the start of the BSS region as defined by the - * linker script. _ebss lies at the end of the BSS region. The idle task - * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. - * The IDLE thread is the thread that the system boots on and, eventually, - * becomes the IDLE, do nothing task that runs only when there is nothing - * else to run. The heap continues from there until the end of memory. - * g_idle_topstack is a read-only variable the provides this computed - * address. - */ - -uintptr_t g_idle_topstack = C906_IDLESTACK_TOP; - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/risc-v/src/c906/chip.h b/arch/risc-v/src/c906/chip.h index 8c94eaa9f6f22..4c9ae770a27d1 100644 --- a/arch/risc-v/src/c906/chip.h +++ b/arch/risc-v/src/c906/chip.h @@ -26,6 +26,7 @@ ****************************************************************************/ #include +#include #include "c906_memorymap.h" diff --git a/arch/risc-v/src/cmake/Toolchain.cmake b/arch/risc-v/src/cmake/Toolchain.cmake index 55152fd42e067..a72460c048e54 100644 --- a/arch/risc-v/src/cmake/Toolchain.cmake +++ b/arch/risc-v/src/cmake/Toolchain.cmake @@ -24,21 +24,28 @@ set(CMAKE_SYSTEM_VERSION 1) set(CMAKE_C_COMPILER_FORCED TRUE) set(CMAKE_CXX_COMPILER_FORCED TRUE) -if(CONFIG_RISCV_TOOLCHAIN_GNU_RV32 OR CONFIG_RISCV_TOOLCHAIN_GNU_RV64) +if(CONFIG_RISCV_TOOLCHAIN_GNU_RV32 + OR CONFIG_RISCV_TOOLCHAIN_GNU_RV64 + OR CONFIG_RISCV_TOOLCHAIN_CLANG) if(NOT CONFIG_RISCV_TOOLCHAIN) set(CONFIG_RISCV_TOOLCHAIN GNU_RVG) endif() endif() # Default toolchain -find_program(RV_COMPILER riscv-none-elf-gcc) -if(RV_COMPILER) - set(TOOLCHAIN_PREFIX riscv-none-elf) + +if(CONFIG_ARCH_TOOLCHAIN_CLANG) + set(TOOLCHAIN_PREFIX riscv64-unknown-elf) else() - if(CONFIG_RISCV_TOOLCHAIN_GNU_RV32) - set(TOOLCHAIN_PREFIX riscv32-unknown-elf) + find_program(RV_COMPILER riscv-none-elf-gcc) + if(RV_COMPILER) + set(TOOLCHAIN_PREFIX riscv-none-elf) else() - set(TOOLCHAIN_PREFIX riscv64-unknown-elf) + if(CONFIG_RISCV_TOOLCHAIN_GNU_RV32) + set(TOOLCHAIN_PREFIX riscv32-unknown-elf) + else() + set(TOOLCHAIN_PREFIX riscv64-unknown-elf) + endif() endif() endif() @@ -46,26 +53,56 @@ set(CMAKE_LIBRARY_ARCHITECTURE ${TOOLCHAIN_PREFIX}) set(CMAKE_C_COMPILER_TARGET ${TOOLCHAIN_PREFIX}) set(CMAKE_CXX_COMPILER_TARGET ${TOOLCHAIN_PREFIX}) -set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) -set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}-gcc) -set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}-g++) -set(CMAKE_STRIP ${TOOLCHAIN_PREFIX}-strip --strip-unneeded) -set(CMAKE_OBJCOPY ${TOOLCHAIN_PREFIX}-objcopy) -set(CMAKE_OBJDUMP ${TOOLCHAIN_PREFIX}-objdump) -set(CMAKE_LINKER ${TOOLCHAIN_PREFIX}-gcc) -set(CMAKE_LD ${TOOLCHAIN_PREFIX}-ld) -set(CMAKE_AR ${TOOLCHAIN_PREFIX}-ar) -set(CMAKE_NM ${TOOLCHAIN_PREFIX}-nm) -set(CMAKE_RANLIB ${TOOLCHAIN_PREFIX}-gcc-ranlib) - -if(CONFIG_LTO_FULL) - add_compile_options(-flto) - if(${CONFIG_RISCV_TOOLCHAIN} STREQUAL "GNU_RVG") +if(CONFIG_ARCH_TOOLCHAIN_CLANG) + set(CMAKE_ASM_COMPILER ${TOOLCHAIN_PREFIX}-clang) + set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}-clang) + set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}-clang++) + set(CMAKE_STRIP ${TOOLCHAIN_PREFIX}-llvm-strip --strip-unneeded) + set(CMAKE_OBJCOPY ${TOOLCHAIN_PREFIX}-llvm-objcopy) + set(CMAKE_OBJDUMP ${TOOLCHAIN_PREFIX}-llvm-objdump) + set(CMAKE_LINKER ${TOOLCHAIN_PREFIX}-ld) + set(CMAKE_LD ${TOOLCHAIN_PREFIX}-ld) + set(CMAKE_AR ${TOOLCHAIN_PREFIX}-llvm-ar) + set(CMAKE_NM ${TOOLCHAIN_PREFIX}-llvm-nm) + set(CMAKE_RANLIB ${TOOLCHAIN_PREFIX}-llvm-ranlib) + + # Since the no_builtin attribute is not fully supported on Clang disable the + # built-in functions, refer: + # https://github.com/apache/incubator-nuttx/pull/5971 + + add_compile_options(-fno-builtin) +else() + set(CMAKE_ASM_COMPILER ${TOOLCHAIN_PREFIX}-gcc) + set(CMAKE_C_COMPILER ${CMAKE_ASM_COMPILER}) + set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}-g++) + set(CMAKE_STRIP ${TOOLCHAIN_PREFIX}-strip --strip-unneeded) + set(CMAKE_OBJCOPY ${TOOLCHAIN_PREFIX}-objcopy) + set(CMAKE_OBJDUMP ${TOOLCHAIN_PREFIX}-objdump) + + if(CONFIG_LTO_FULL AND CONFIG_ARCH_TOOLCHAIN_GNU) + set(CMAKE_LINKER ${TOOLCHAIN_PREFIX}-gcc) set(CMAKE_LD ${TOOLCHAIN_PREFIX}-gcc) set(CMAKE_AR ${TOOLCHAIN_PREFIX}-gcc-ar) set(CMAKE_NM ${TOOLCHAIN_PREFIX}-gcc-nm) - add_compile_options(-fuse-linker-plugin) + set(CMAKE_RANLIB ${TOOLCHAIN_PREFIX}-gcc-ranlib) + else() + set(CMAKE_LINKER ${TOOLCHAIN_PREFIX}-ld) + set(CMAKE_LD ${TOOLCHAIN_PREFIX}-ld) + set(CMAKE_AR ${TOOLCHAIN_PREFIX}-ar) + set(CMAKE_NM ${TOOLCHAIN_PREFIX}-nm) + set(CMAKE_RANLIB ${TOOLCHAIN_PREFIX}-ranlib) + endif() +endif() + +# Link Time Optimization + +if(CONFIG_LTO_THIN) + add_compile_options(-flto=thin) +elseif(CONFIG_LTO_FULL) + add_compile_options(-flto) + if(CONFIG_ARCH_TOOLCHAIN_GNU) add_compile_options(-fno-builtin) + add_compile_options(-fuse-linker-plugin) endif() endif() @@ -78,7 +115,11 @@ set(CMAKE_ASM_ARCHIVE_CREATE " rcs ") if(CONFIG_DEBUG_CUSTOMOPT) add_compile_options(${CONFIG_DEBUG_OPTLEVEL}) elseif(CONFIG_DEBUG_FULLOPT) - add_compile_options(-Os) + if(CONFIG_ARCH_TOOLCHAIN_CLANG) + add_compile_options(-Oz) + else() + add_compile_options(-Os) + endif() endif() if(NOT CONFIG_DEBUG_NOOPT) @@ -113,8 +154,11 @@ set(ARCHCFLAGS "-Wstrict-prototypes -fno-common -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas" ) set(ARCHCXXFLAGS - "-nostdinc++ -fno-common -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas" -) + "-fno-common -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas") + +if(NOT CONFIG_LIBCXXTOOLCHAIN) + set(ARCHCXXFLAGS "${ARCHCXXFLAGS} -nostdinc++") +endif() if(NOT ${CONFIG_ARCH_TOOLCHAIN_CLANG}) string(APPEND ARCHCFLAGS " -Wno-psabi") @@ -145,7 +189,7 @@ if(CONFIG_DEBUG_OPT_UNUSED_SECTIONS) add_compile_options(-ffunction-sections -fdata-sections) endif() -add_link_options(-Wl,-nostdlib) +add_link_options(-nostdlib) add_link_options(-Wl,--entry=__start) if(CONFIG_DEBUG_LINK_MAP) @@ -175,33 +219,58 @@ endif() # Generic GNU RVG toolchain if(${CONFIG_RISCV_TOOLCHAIN} STREQUAL GNU_RVG) - execute_process(COMMAND ${TOOLCHAIN_PREFIX}-gcc --version - OUTPUT_VARIABLE GCC_VERSION_OUTPUT) - string(REGEX MATCH "[0-9]+\\.[0-9]+\\.[0-9]+" GCC_VERSION - ${GCC_VERSION_OUTPUT}) - string(REGEX MATCH "^[0-9]+" GCC_VERSION_MAJOR ${GCC_VERSION}) - if(GCC_VERSION GREATER_EQUAL 12) - set(ARCHRVISAZ "_zicsr_zifencei") - endif() + set(ARCHCPUEXTFLAGS i) if(CONFIG_ARCH_RV_ISA_M) - set(ARCHRVISAM m) + set(ARCHCPUEXTFLAGS ${ARCHCPUEXTFLAGS}m) endif() if(CONFIG_ARCH_RV_ISA_A) - set(ARCHRVISAA a) + set(ARCHCPUEXTFLAGS ${ARCHCPUEXTFLAGS}a) + endif() + + if(CONFIG_ARCH_FPU) + set(ARCHCPUEXTFLAGS ${ARCHCPUEXTFLAGS}f) + endif() + + if(CONFIG_ARCH_DPFPU) + set(ARCHCPUEXTFLAGS ${ARCHCPUEXTFLAGS}d) + endif() + + if(CONFIG_ARCH_QPFPU) + set(ARCHCPUEXTFLAGS ${ARCHCPUEXTFLAGS}q) endif() if(CONFIG_ARCH_RV_ISA_C) - set(ARCHRVISAC c) + set(ARCHCPUEXTFLAGS ${ARCHCPUEXTFLAGS}c) endif() - if(CONFIG_ARCH_FPU) - set(ARCHRVISAF f) + if(CONFIG_ARCH_RV_ISA_V) + set(ARCHCPUEXTFLAGS ${ARCHCPUEXTFLAGS}v) endif() - if(CONFIG_ARCH_DPFPU) - set(ARCHRVISAD d) + if(CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI) + if(NOT DEFINED GCCVER) + execute_process(COMMAND ${CMAKE_CXX_COMPILER} --version + OUTPUT_VARIABLE GCC_VERSION_OUTPUT) + string(REGEX MATCH "\\+\\+.* ([0-9]+)\\.[0-9]+" GCC_VERSION_REGEX + "${GCC_VERSION_OUTPUT}") + set(GCCVER ${CMAKE_MATCH_1}) + endif() + if(GCCVER GREATER_EQUAL 12 OR CONFIG_ARCH_TOOLCHAIN_CLANG) + set(ARCHCPUEXTFLAGS ${ARCHCPUEXTFLAGS}_zicsr_zifencei) + endif() + endif() + + if(CONFIG_ARCH_RV_EXPERIMENTAL_EXTENSIONS) + set(ARCHCPUEXTFLAGS + ${ARCHCPUEXTFLAGS}_${CONFIG_ARCH_RV_EXPERIMENTAL_EXTENSIONS}) + add_compile_options(-menable-experimental-extensions) + endif() + + if(CONFIG_ARCH_RV_ISA_VENDOR_EXTENSIONS) + set(ARCHCPUEXTFLAGS + ${ARCHCPUEXTFLAGS}_${CONFIG_ARCH_RV_ISA_VENDOR_EXTENSIONS}) endif() # Detect abi type @@ -218,9 +287,6 @@ if(${CONFIG_RISCV_TOOLCHAIN} STREQUAL GNU_RVG) # Construct arch flags - set(ARCHCPUEXTFLAGS - i${ARCHRVISAM}${ARCHRVISAA}${ARCHRVISAF}${ARCHRVISAD}${ARCHRVISAC}${ARCHRVISAZ} - ) set(ARCHCPUFLAGS -march=${ARCHTYPE}${ARCHCPUEXTFLAGS}) # Construct arch abi flags @@ -246,21 +312,21 @@ if(${CONFIG_RISCV_TOOLCHAIN} STREQUAL GNU_RVG) # These models can't cover all implementation of RISCV, but it's enough for # most cases. - set(PLATFORM_FLAGS) + set(LLVM_CPUFLAGS) if(CONFIG_ARCH_RV32) if(${ARCHCPUEXTFLAGS} STREQUAL imc) - list(APPEND PLATFORM_FLAGS -mcpu=sifive-e20) + list(APPEND LLVM_CPUFLAGS -mcpu=sifive-e20) elseif(${ARCHCPUEXTFLAGS} STREQUAL imac) - list(APPEND PLATFORM_FLAGS -mcpu=sifive-e31) + list(APPEND LLVM_CPUFLAGS -mcpu=sifive-e31) elseif(${ARCHCPUEXTFLAGS} STREQUAL imafc) - list(APPEND PLATFORM_FLAGS -mcpu=sifive-e76) + list(APPEND LLVM_CPUFLAGS -mcpu=sifive-e76) endif() else() if(${ARCHCPUEXTFLAGS} STREQUAL imac) - list(APPEND PLATFORM_FLAGS -mcpu=sifive-s51) + list(APPEND LLVM_CPUFLAGS -mcpu=sifive-s51) elseif(${ARCHCPUEXTFLAGS} STREQUAL imafdc) - list(APPEND PLATFORM_FLAGS -mcpu=sifive-u54) + list(APPEND LLVM_CPUFLAGS -mcpu=sifive-u54) endif() endif() diff --git a/arch/risc-v/src/cmake/platform.cmake b/arch/risc-v/src/cmake/platform.cmake index 79893f8388ed8..9f2f3fc9d62e6 100644 --- a/arch/risc-v/src/cmake/platform.cmake +++ b/arch/risc-v/src/cmake/platform.cmake @@ -1,5 +1,5 @@ # ############################################################################## -# ./arch/risc-v/src/cmake/platform.cmake +# arch/risc-v/src/cmake/platform.cmake # # Licensed to the Apache Software Foundation (ASF) under one or more contributor # license agreements. See the NOTICE file distributed with this work for @@ -21,8 +21,10 @@ get_directory_property(NUTTX_EXTRA_FLAGS DIRECTORY ${CMAKE_SOURCE_DIR} COMPILE_OPTIONS) +separate_arguments(CMAKE_C_FLAG_ARGS NATIVE_COMMAND ${CMAKE_C_FLAGS}) + execute_process( - COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} ${NUTTX_EXTRA_FLAGS} + COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} ${NUTTX_EXTRA_FLAGS} --print-libgcc-file-name OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE extra_library) @@ -31,7 +33,7 @@ list(APPEND EXTRA_LIB ${extra_library}) if(NOT CONFIG_LIBM) execute_process( - COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} ${NUTTX_EXTRA_FLAGS} + COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} ${NUTTX_EXTRA_FLAGS} --print-file-name=libm.a OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE extra_library) @@ -40,7 +42,7 @@ endif() if(CONFIG_LIBSUPCXX) execute_process( - COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} ${NUTTX_EXTRA_FLAGS} + COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} ${NUTTX_EXTRA_FLAGS} --print-file-name=libsupc++.a OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE extra_library) @@ -49,7 +51,7 @@ endif() if(CONFIG_ARCH_COVERAGE) execute_process( - COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} ${NUTTX_EXTRA_FLAGS} + COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} ${NUTTX_EXTRA_FLAGS} --print-file-name=libgcov.a OUTPUT_STRIP_TRAILING_WHITESPACE OUTPUT_VARIABLE extra_library) @@ -58,5 +60,4 @@ endif() nuttx_add_extra_library(${EXTRA_LIB}) -separate_arguments(CMAKE_C_FLAG_ARGS NATIVE_COMMAND ${CMAKE_C_FLAGS}) set(PREPROCES ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} -E -P -x c) diff --git a/arch/risc-v/src/common/CMakeLists.txt b/arch/risc-v/src/common/CMakeLists.txt index f704b210d0eb1..82e16738d337e 100644 --- a/arch/risc-v/src/common/CMakeLists.txt +++ b/arch/risc-v/src/common/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# arch/arm/src/common/CMakeLists.txt +# arch/risc-v/src/common/CMakeLists.txt # # Licensed to the Apache Software Foundation (ASF) under one or more contributor # license agreements. See the NOTICE file distributed with this work for @@ -51,7 +51,9 @@ endif() if(NOT CONFIG_BUILD_FLAT) list(APPEND SRCS riscv_task_start.c riscv_pthread_start.c riscv_signal_dispatch.c) - list(APPEND SRCS riscv_signal_handler.S) + if(CONFIG_BUILD_PROTECTED) + target_sources(arch_interface PRIVATE riscv_signal_handler.S) + endif() endif() if(CONFIG_SCHED_BACKTRACE) @@ -74,6 +76,10 @@ if(CONFIG_ARCH_FPU) list(APPEND SRCS riscv_fpu.S riscv_fpucmp.c) endif() +if(CONFIG_ARCH_RV_ISA_V) + list(APPEND SRCS riscv_vpu.S) +endif() + if(CONFIG_ARCH_RV_ISA_A) list(APPEND SRCS riscv_testset.S) endif() @@ -91,7 +97,7 @@ if(CONFIG_ARCH_USE_MMU) endif() if(CONFIG_ARCH_KERNEL_STACK) - list(APPEND SRCS riscv_addrenv_kstack.c) + list(APPEND SRCS riscv_addrenv_kstack.c riscv_ksp.c) endif() if(CONFIG_ARCH_ADDRENV) @@ -99,4 +105,12 @@ if(CONFIG_ARCH_ADDRENV) list(APPEND SRCS riscv_addrenv_utils.c riscv_addrenv_shm.c) endif() +if(CONFIG_RISCV_PERCPU_SCRATCH) + list(APPEND SRCS riscv_percpu.c) +endif() + +if(CONFIG_BUILD_KERNEL) + add_subdirectory(supervisor) +endif() + target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/risc-v/src/common/Make.defs b/arch/risc-v/src/common/Make.defs index 7431752c944cd..f5f1bc637ae9e 100644 --- a/arch/risc-v/src/common/Make.defs +++ b/arch/risc-v/src/common/Make.defs @@ -79,6 +79,10 @@ CMN_ASRCS += riscv_fpu.S CMN_CSRCS += riscv_fpucmp.c endif +ifeq ($(CONFIG_ARCH_RV_ISA_V),y) +CMN_ASRCS += riscv_vpu.S +endif + ifeq ($(CONFIG_ARCH_RV_ISA_A),y) CMN_ASRCS += riscv_testset.S endif @@ -104,3 +108,13 @@ ifeq ($(CONFIG_ARCH_ADDRENV),y) CMN_CSRCS += riscv_addrenv.c riscv_pgalloc.c riscv_addrenv_perms.c CMN_CSRCS += riscv_addrenv_utils.c riscv_addrenv_shm.c riscv_addrenv_pgmap.c endif + +ifeq ($(CONFIG_RISCV_PERCPU_SCRATCH),y) +CMN_CSRCS += riscv_percpu.c +endif + +# Kernel runs in supervisor mode or machine mode ? + +ifeq ($(CONFIG_ARCH_USE_S_MODE),y) +include common/supervisor/Make.defs +endif diff --git a/arch/risc-v/src/common/Toolchain.defs b/arch/risc-v/src/common/Toolchain.defs index 3d0e5296a948a..c9e09c22618e4 100644 --- a/arch/risc-v/src/common/Toolchain.defs +++ b/arch/risc-v/src/common/Toolchain.defs @@ -31,6 +31,8 @@ ifeq ($(filter y, $(CONFIG_RISCV_TOOLCHAIN_GNU_RV64)),y) CONFIG_RISCV_TOOLCHAIN ?= GNU_RVG else ifeq ($(filter y, $(CONFIG_RISCV_TOOLCHAIN_GNU_RV32)),y) CONFIG_RISCV_TOOLCHAIN ?= GNU_RVG +else ifeq ($(filter y, $(CONFIG_RISCV_TOOLCHAIN_CLANG)),y) + CONFIG_RISCV_TOOLCHAIN ?= GNU_RVG endif # @@ -48,7 +50,11 @@ endif ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) ARCHOPTIMIZATION += $(CONFIG_DEBUG_OPTLEVEL) else ifeq ($(CONFIG_DEBUG_FULLOPT),y) - ARCHOPTIMIZATION += -Os + ifeq ($(CONFIG_ARCH_TOOLCHAIN_CLANG),y) + ARCHOPTIMIZATION += -Oz + else + ARCHOPTIMIZATION += -Os + endif endif ifneq ($(CONFIG_DEBUG_NOOPT),y) @@ -78,7 +84,7 @@ ifeq ($(CONFIG_ARCH_COVERAGE_ALL),y) endif ARCHCFLAGS += -fno-common -ARCHCXXFLAGS += -fno-common -nostdinc++ +ARCHCXXFLAGS += -fno-common ARCHCFLAGS += -Wall -Wstrict-prototypes -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas ARCHCXXFLAGS += -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas @@ -87,6 +93,10 @@ ARCHCXXFLAGS += -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas # we can safely disregard warnings of the type "parameter passing for X changed in GCC 7.1." # Refer to : https://stackoverflow.com/questions/48149323/what-does-the-gcc-warning-project-parameter-passing-for-x-changed-in-gcc-7-1-m +ifneq ($(CONFIG_LIBCXXTOOLCHAIN),y) + ARCHCXXFLAGS += -nostdinc++ +endif + ifneq ($(CONFIG_ARCH_TOOLCHAIN_CLANG),y) ARCHCFLAGS += -Wno-psabi ARCHCXXFLAGS += -Wno-psabi @@ -117,7 +127,8 @@ ifeq ($(CONFIG_DEBUG_OPT_UNUSED_SECTIONS),y) ARCHOPTIMIZATION += -ffunction-sections -fdata-sections endif -LDFLAGS += -nostdlib +LDFLAGS += -nostdlib +ARCHOPTIMIZATION += -nostdlib # Debug link map @@ -136,41 +147,77 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG) # Generic GNU RVG toolchain, prefer to use riscv-none-elf-gcc from xPack # if CROSSDEV is not defined. - ifeq ($(shell riscv-none-elf-gcc --version > /dev/null 2>&1; echo $$?), 0) - CROSSDEV ?= riscv-none-elf- + ifeq ($(CONFIG_ARCH_TOOLCHAIN_CLANG),y) + CROSSDEV ?= riscv64-unknown-elf- else - ifeq ($(CONFIG_RISCV_TOOLCHAIN_GNU_RV32),y) - CROSSDEV ?= riscv32-unknown-elf- + ifeq ($(shell riscv-none-elf-gcc --version > /dev/null 2>&1; echo $$?), 0) + CROSSDEV ?= riscv-none-elf- else - CROSSDEV ?= riscv64-unknown-elf- + ifeq ($(CONFIG_RISCV_TOOLCHAIN_GNU_RV32),y) + CROSSDEV ?= riscv32-unknown-elf- + else + CROSSDEV ?= riscv64-unknown-elf- + endif endif endif - # Detect cpu ISA support flags + # Detect cpu ISA support flags: + # + # Naming Convention + # RISC-V defines an exact order that must be used to define the RISC-V ISA subset: + # + # RV [32, 64, 128] I, M, A, F, D, G, Q, L, C, B, J, T, P, V, N + # + # For example, RV32IMAFDQC is legal, whereas RV32IMAFDCQ is not. + + ARCHCPUEXTFLAGS = i ifeq ($(CONFIG_ARCH_RV_ISA_M),y) - ARCHRVISAM = m + ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)m endif ifeq ($(CONFIG_ARCH_RV_ISA_A),y) - ARCHRVISAA = a + ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)a + endif + + ifeq ($(CONFIG_ARCH_FPU),y) + ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)f + endif + + ifeq ($(CONFIG_ARCH_DPFPU),y) + ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)d + endif + + ifeq ($(CONFIG_ARCH_QPFPU),y) + ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)q endif ifeq ($(CONFIG_ARCH_RV_ISA_C),y) - ARCHRVISAC = c + ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)c endif - ifeq ($(CONFIG_ARCH_FPU),y) - ARCHRVISAF = f + ifeq ($(CONFIG_ARCH_RV_ISA_V),y) + ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)v endif - ifeq ($(CONFIG_ARCH_DPFPU),y) - ARCHRVISAD = d + ifeq ($(CONFIG_ARCH_RV_ISA_ZICSR_ZIFENCEI),y) + ifeq ($(GCCVER),) + export GCCVER = ${shell $(CROSSDEV)gcc --version | grep gcc | grep -oE '[0-9]+\.[0-9]+\.[0-9]+' | tail -n 1 | cut -d"." -f1 } + endif + ifeq ($(shell expr $(GCCVER) \>= 12), 1) + ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)_zicsr_zifencei + endif + endif + + ARCH_RV_EXPERIMENTAL_EXTENSIONS = $(strip $(subst ",,$(CONFIG_ARCH_RV_EXPERIMENTAL_EXTENSIONS))) + ifneq ($(ARCH_RV_EXPERIMENTAL_EXTENSIONS),) + ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)_$(ARCH_RV_EXPERIMENTAL_EXTENSIONS) + ARCHOPTIMIZATION += -menable-experimental-extensions endif - GCC_VERSION = ${shell $(CROSSDEV)gcc --version | grep gcc | grep -oE '[0-9]+\.[0-9]+\.[0-9]+' | tail -n 1 | cut -d"." -f1 } - ifeq ($(shell expr $(GCC_VERSION) \>= 12), 1) - ARCHRVISAZ = _zicsr_zifencei + ARCH_RV_ISA_VENDOR_EXTENSIONS = $(strip $(subst ",,$(CONFIG_ARCH_RV_ISA_VENDOR_EXTENSIONS))) + ifneq ($(ARCH_RV_ISA_VENDOR_EXTENSIONS),) + ARCHCPUEXTFLAGS := $(ARCHCPUEXTFLAGS)_$(ARCH_RV_ISA_VENDOR_EXTENSIONS) endif # Detect abi type @@ -189,7 +236,6 @@ ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG) # Construct arch flags - ARCHCPUEXTFLAGS = i$(ARCHRVISAM)$(ARCHRVISAA)$(ARCHRVISAF)$(ARCHRVISAD)$(ARCHRVISAC)$(ARCHRVISAZ) ARCHCPUFLAGS += -march=$(ARCHTYPE)$(ARCHCPUEXTFLAGS) # Construct arch abi flags @@ -235,6 +281,10 @@ ifeq ($(CONFIG_MM_KASAN_ALL),y) ARCHOPTIMIZATION += -fsanitize=kernel-address endif +ifeq ($(CONFIG_MM_KASAN_GLOBAL),y) + ARCHOPTIMIZATION += --param asan-globals=1 +endif + ifeq ($(CONFIG_MM_KASAN_DISABLE_READS_CHECK),y) ARCHOPTIMIZATION += --param asan-instrument-reads=0 endif @@ -257,34 +307,78 @@ ifeq ($(CONFIG_ARCH_INSTRUMENT_ALL),y) ARCHOPTIMIZATION += -finstrument-functions endif +# Link Time Optimization + +ifeq ($(CONFIG_LTO_THIN),y) + ARCHOPTIMIZATION += -flto=thin +else ifeq ($(CONFIG_LTO_FULL),y) + ARCHOPTIMIZATION += -flto + ifeq ($(CONFIG_ARM_TOOLCHAIN_GNU_EABI),y) + ARCHOPTIMIZATION += -fuse-linker-plugin + endif +endif + +# Clang toolchain + +ifeq ($(CONFIG_ARCH_TOOLCHAIN_CLANG),y) + + CC = $(CROSSDEV)clang + CXX = $(CROSSDEV)clang++ + CPP = $(CROSSDEV)clang -E -P -x c + LD = $(CROSSDEV)clang + STRIP = $(CROSSDEV)llvm-strip --strip-unneeded + AR = $(CROSSDEV)llvm-ar rcs + NM = $(CROSSDEV)llvm-nm + OBJCOPY = $(CROSSDEV)llvm-objcopy + OBJDUMP = $(CROSSDEV)llvm-objdump + + # Since the no_builtin attribute is not fully supported on Clang + # disable the built-in functions, refer: + # https://github.com/apache/nuttx/pull/5971 + + ARCHOPTIMIZATION += -fno-builtin + + ARCHOPTIMIZATION += -fshort-enums + # Default toolchain -CC = $(CROSSDEV)gcc -CXX = $(CROSSDEV)g++ -CPP = $(CROSSDEV)gcc -E -P -x c -STRIP = $(CROSSDEV)strip --strip-unneeded -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump -LD = $(CROSSDEV)ld -AR = $(CROSSDEV)ar rcs -NM = $(CROSSDEV)nm +else + + CC = $(CROSSDEV)gcc + CXX = $(CROSSDEV)g++ + CPP = $(CROSSDEV)gcc -E -P -x c + STRIP = $(CROSSDEV)strip --strip-unneeded + OBJCOPY = $(CROSSDEV)objcopy + OBJDUMP = $(CROSSDEV)objdump + LD = $(CROSSDEV)ld + AR = $(CROSSDEV)ar rcs + NM = $(CROSSDEV)nm # Link Time Optimization -ifeq ($(CONFIG_LTO_FULL),y) - ARCHOPTIMIZATION += -flto - ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG) - LD := $(CROSSDEV)gcc - AR := $(CROSSDEV)gcc-ar rcs - NM := $(CROSSDEV)gcc-nm - ARCHOPTIMIZATION += -fuse-linker-plugin - ARCHOPTIMIZATION += -fno-builtin + ifeq ($(CONFIG_LTO_FULL),y) + ifeq ($(CONFIG_RISCV_TOOLCHAIN),GNU_RVG) + LD := $(CROSSDEV)gcc + AR := $(CROSSDEV)gcc-ar rcs + NM := $(CROSSDEV)gcc-nm + ARCHOPTIMIZATION += -fno-builtin + endif endif + endif # Add the builtin library -EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-libgcc-file-name)) +COMPILER_RT_LIB = $(shell $(CC) $(ARCHCPUFLAGS) --print-libgcc-file-name) +ifeq ($(CONFIG_ARCH_TOOLCHAIN_CLANG),y) + ifeq ($(wildcard $(COMPILER_RT_LIB)),) + # if "--print-libgcc-file-name" unable to find the correct libgcc PATH + # then go ahead and try "--print-file-name" + COMPILER_RT_LIB := $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name $(notdir $(COMPILER_RT_LIB)))) + endif +endif + +EXTRA_LIBS += $(COMPILER_RT_LIB) ifeq ($(CONFIG_LIBM_TOOLCHAIN),y) EXTRA_LIBS += $(wildcard $(shell $(CC) $(ARCHCPUFLAGS) --print-file-name=libm.a)) diff --git a/arch/risc-v/src/common/crt0.c b/arch/risc-v/src/common/crt0.c index fdad28381cfa9..77cd07959b22c 100644 --- a/arch/risc-v/src/common/crt0.c +++ b/arch/risc-v/src/common/crt0.c @@ -143,7 +143,7 @@ static void exec_dtors(void) ****************************************************************************/ /**************************************************************************** - * Name: _start + * Name: __start * * Description: * This function is the low level entry point into the main thread of @@ -162,7 +162,7 @@ static void exec_dtors(void) * ****************************************************************************/ -void _start(int argc, char *argv[]) +void __start(int argc, char *argv[]) { int ret; diff --git a/arch/risc-v/src/espressif/.gitignore b/arch/risc-v/src/common/espressif/.gitignore similarity index 100% rename from arch/risc-v/src/espressif/.gitignore rename to arch/risc-v/src/common/espressif/.gitignore diff --git a/arch/risc-v/src/common/espressif/Bootloader.mk b/arch/risc-v/src/common/espressif/Bootloader.mk new file mode 100644 index 0000000000000..25d9f15cf851d --- /dev/null +++ b/arch/risc-v/src/common/espressif/Bootloader.mk @@ -0,0 +1,130 @@ +############################################################################ +# arch/risc-v/src/common/espressif/Bootloader.mk +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Remove quotes from CONFIG_ESPRESSIF_CHIP_SERIES configuration + +CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES)) + +TOOLSDIR = $(TOPDIR)/tools/espressif +CHIPDIR = $(TOPDIR)/arch/risc-v/src/chip +HALDIR = $(CHIPDIR)/esp-hal-3rdparty +BOOTLOADER_SRCDIR = $(CHIPDIR)/bootloader +BOOTLOADER_OUTDIR = $(BOOTLOADER_SRCDIR)/out +BOOTLOADER_CONFIG = $(BOOTLOADER_SRCDIR)/bootloader.conf + +# MCUboot + +MCUBOOT_SRCDIR = $(BOOTLOADER_SRCDIR)/mcuboot +MCUBOOT_ESPDIR = $(MCUBOOT_SRCDIR)/boot/espressif +MCUBOOT_URL = https://github.com/mcu-tools/mcuboot + +# IDFboot + +BLBIN_VERSION = latest +BLBIN_URL = https://github.com/espressif/esp-nuttx-bootloader/releases/download/$(BLBIN_VERSION) + +# Helpers for creating the configuration file + +cfg_en = echo "$(1)=$(if $(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT),1,y)"; +cfg_dis = echo "$(1)=$(if $(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT),0,n)"; +cfg_val = echo "$(1)=$(2)"; + +$(BOOTLOADER_SRCDIR): + $(Q) mkdir -p $(BOOTLOADER_SRCDIR) &>/dev/null + +$(BOOTLOADER_CONFIG): $(TOPDIR)/.config $(BOOTLOADER_SRCDIR) + $(Q) echo "Creating Bootloader configuration" + $(Q) { \ + $(if $(CONFIG_ESPRESSIF_FLASH_2M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_2MB)) \ + $(if $(CONFIG_ESPRESSIF_FLASH_4M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_4MB)) \ + $(if $(CONFIG_ESPRESSIF_FLASH_MODE_DIO),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_DIO)) \ + $(if $(CONFIG_ESPRESSIF_FLASH_MODE_DOUT),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_DOUT)) \ + $(if $(CONFIG_ESPRESSIF_FLASH_MODE_QIO),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_QIO)) \ + $(if $(CONFIG_ESPRESSIF_FLASH_MODE_QOUT),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_QOUT)) \ + $(if $(CONFIG_ESPRESSIF_FLASH_FREQ_80M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_80M)) \ + $(if $(CONFIG_ESPRESSIF_FLASH_FREQ_48M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_48M)) \ + $(if $(CONFIG_ESPRESSIF_FLASH_FREQ_40M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_40M)) \ + $(if $(CONFIG_ESPRESSIF_FLASH_FREQ_26M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_26M)) \ + $(if $(CONFIG_ESPRESSIF_FLASH_FREQ_20M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_20M)) \ + } > $(BOOTLOADER_CONFIG) +ifeq ($(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT),y) + $(Q) { \ + $(call cfg_val,CONFIG_ESP_BOOTLOADER_OFFSET,0x0000) \ + $(call cfg_val,CONFIG_ESP_BOOTLOADER_SIZE,0xF000) \ + $(call cfg_val,CONFIG_ESP_IMAGE0_PRIMARY_START_ADDRESS,$(CONFIG_ESPRESSIF_OTA_PRIMARY_SLOT_OFFSET)) \ + $(call cfg_val,CONFIG_ESP_APPLICATION_SIZE,$(CONFIG_ESPRESSIF_OTA_SLOT_SIZE)) \ + $(call cfg_val,CONFIG_ESP_IMAGE0_SECONDARY_START_ADDRESS,$(CONFIG_ESPRESSIF_OTA_SECONDARY_SLOT_OFFSET)) \ + $(call cfg_en,CONFIG_ESP_MCUBOOT_WDT_ENABLE) \ + $(call cfg_val,CONFIG_ESP_SCRATCH_OFFSET,$(CONFIG_ESPRESSIF_OTA_SCRATCH_OFFSET)) \ + $(call cfg_val,CONFIG_ESP_SCRATCH_SIZE,$(CONFIG_ESPRESSIF_OTA_SCRATCH_SIZE)) \ + $(call cfg_en,CONFIG_ESP_CONSOLE_UART) \ + $(if $(CONFIG_UART0_SERIAL_CONSOLE),$(call cfg_val,CONFIG_ESP_CONSOLE_UART_NUM,0)) \ + $(if $(CONFIG_UART1_SERIAL_CONSOLE),$(call cfg_val,CONFIG_ESP_CONSOLE_UART_NUM,1)) \ + } >> $(BOOTLOADER_CONFIG) +else + $(Q) { \ + $(call cfg_en,CONFIG_PARTITION_TABLE_CUSTOM) \ + $(call cfg_val,CONFIG_PARTITION_TABLE_CUSTOM_FILENAME,\"partitions.csv\") \ + $(call cfg_val,CONFIG_PARTITION_TABLE_OFFSET,$(CONFIG_ESPRESSIF_PARTITION_TABLE_OFFSET)) \ + } >> $(BOOTLOADER_CONFIG) +endif + +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) +bootloader: + $(Q) echo "Using direct bootloader to boot NuttX." +else +ifeq ($(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT),y) + +BOOTLOADER_BIN = $(TOPDIR)/mcuboot-$(CHIP_SERIES).bin + +$(MCUBOOT_SRCDIR): $(BOOTLOADER_SRCDIR) + $(Q) echo "Cloning MCUboot" + $(Q) git clone --quiet $(MCUBOOT_URL) $(MCUBOOT_SRCDIR) + $(Q) git -C "$(MCUBOOT_SRCDIR)" checkout --quiet $(CONFIG_ESPRESSIF_MCUBOOT_VERSION) + $(Q) git -C "$(MCUBOOT_SRCDIR)" submodule --quiet update --init --recursive ext/mbedtls + +$(BOOTLOADER_BIN): chip/$(ESP_HAL_3RDPARTY_REPO) $(MCUBOOT_SRCDIR) $(BOOTLOADER_CONFIG) + $(Q) echo "Building MCUboot" + $(Q) $(TOOLSDIR)/build_mcuboot.sh \ + -c $(CHIP_SERIES) \ + -f $(BOOTLOADER_CONFIG) \ + -p $(BOOTLOADER_SRCDIR) \ + -e $(HALDIR) + $(call COPYFILE, $(BOOTLOADER_OUTDIR)/mcuboot-$(CHIP_SERIES).bin, $(TOPDIR)) + +bootloader: $(BOOTLOADER_CONFIG) $(BOOTLOADER_BIN) + +clean_bootloader: + $(call DELDIR,$(BOOTLOADER_SRCDIR)) + $(call DELFILE,$(BOOTLOADER_BIN)) + +else + +bootloader: + $(Q) echo "Downloading Bootloader binaries" + $(call DOWNLOAD,$(BLBIN_URL),bootloader-$(CHIP_SERIES).bin,$(TOPDIR)/bootloader-$(CHIP_SERIES).bin) + $(call DOWNLOAD,$(BLBIN_URL),partition-table-$(CHIP_SERIES).bin,$(TOPDIR)/partition-table-$(CHIP_SERIES).bin) + +clean_bootloader: + $(call DELFILE,$(TOPDIR)/bootloader-$(CHIP_SERIES).bin) + $(call DELFILE,$(TOPDIR)/partition-table-$(CHIP_SERIES).bin) + +endif +endif diff --git a/arch/risc-v/src/common/espressif/Kconfig b/arch/risc-v/src/common/espressif/Kconfig new file mode 100644 index 0000000000000..4db4627d62fa7 --- /dev/null +++ b/arch/risc-v/src/common/espressif/Kconfig @@ -0,0 +1,1124 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_ESPRESSIF || ARCH_CHIP_ESP32C6 || ARCH_CHIP_ESP32H2 || ARCH_CHIP_ESP32C3_GENERIC + +choice ESPRESSIF_CHIP_SERIES + prompt "Chip Series" + default ESPRESSIF_ESP32C3 + +config ESPRESSIF_ESP32C3 + bool "ESP32-C3" + ---help--- + ESP32-C3 chip with a single RISC-V IMC core, no embedded Flash memory + +config ESPRESSIF_ESP32C6 + bool "ESP32-C6" + ---help--- + Espressif ESP32-C6 (RV32IMAC). + +config ESPRESSIF_ESP32H2 + bool "ESP32-H2" + ---help--- + Espressif ESP32-H2 (RV32IMC). + +endchoice # ESPRESSIF_CHIP_SERIES + +config ESPRESSIF_CHIP_SERIES + string + default "esp32c3" if ESPRESSIF_ESP32C3 + default "esp32c6" if ESPRESSIF_ESP32C6 + default "esp32h2" if ESPRESSIF_ESP32H2 + default "unknown" + +choice ESPRESSIF_FLASH + prompt "Flash Size" + default ESPRESSIF_FLASH_4M if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2 + +config ESPRESSIF_FLASH_2M + bool "2 MB" + +config ESPRESSIF_FLASH_4M + bool "4 MB" + +config ESPRESSIF_FLASH_8M + bool "8 MB" + +config ESPRESSIF_FLASH_16M + bool "16 MB" + +endchoice # ESPRESSIF_FLASH + +config ESPRESSIF_FLASH_DETECT + bool "Auto-detect FLASH size" + default n + ---help--- + Auto detect flash size when flashing. + +config ESPRESSIF_NUM_CPUS + int + default 1 if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2 + +choice ESPRESSIF_CPU_FREQ + prompt "CPU frequency" + default ESPRESSIF_CPU_FREQ_160 if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 + default ESPRESSIF_CPU_FREQ_96 if ESPRESSIF_ESP32H2 + ---help--- + CPU frequency to be set on application startup. + +config ESPRESSIF_CPU_FREQ_40 + bool "40 MHz" + depends on ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 + ---help--- + Set the CPU frequency to 40 MHz. + +config ESPRESSIF_CPU_FREQ_48 + bool "48 MHz" + depends on ESPRESSIF_ESP32H2 + ---help--- + Set the CPU frequency to 48 MHz. + +config ESPRESSIF_CPU_FREQ_64 + bool "64 MHz" + depends on ESPRESSIF_ESP32H2 + ---help--- + Set the CPU frequency to 64 MHz. + +config ESPRESSIF_CPU_FREQ_80 + bool "80 MHz" + depends on ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 + ---help--- + Set the CPU frequency to 80 MHz. + +config ESPRESSIF_CPU_FREQ_96 + bool "96 MHz" + depends on ESPRESSIF_ESP32H2 + ---help--- + Set the CPU frequency to 96 MHz. + +config ESPRESSIF_CPU_FREQ_160 + bool "160 MHz" + depends on ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 + ---help--- + Set the CPU frequency to 160 MHz. + +endchoice # ESPRESSIF_CPU_FREQ + +config ESPRESSIF_CPU_FREQ_MHZ + int + default 40 if ESPRESSIF_CPU_FREQ_40 + default 48 if ESPRESSIF_CPU_FREQ_48 + default 64 if ESPRESSIF_CPU_FREQ_64 + default 80 if ESPRESSIF_CPU_FREQ_80 + default 96 if ESPRESSIF_CPU_FREQ_96 + default 160 if ESPRESSIF_CPU_FREQ_160 + +config ESPRESSIF_REGION_PROTECTION + bool "Enable region protection" + default y + select ARCH_USE_MPU + ---help--- + Configure the MPU to disable access to invalid memory regions. + +config ESPRESSIF_RUN_IRAM + bool "Run from IRAM" + default n + ---help--- + This loads all of NuttX inside IRAM. Used to test somewhat small + images that can fit entirely in IRAM. + +config ESPRESSIF_ESPTOOLPY_NO_STUB + bool "Disable download stub" + default n + ---help--- + The flasher tool sends a precompiled download stub first by default. + That stub allows things like compressed downloads and more. + Usually you should not need to disable that feature. + It is only required to be disabled in certain scenarios when either + Secure Boot V2 or Flash Encryption is enabled. + +config ESPRESSIF_HAL_ASSERTIONS + bool "Enable HAL assertions" + depends on DEBUG_ASSERTIONS + default y + ---help--- + Enable the assertions implemented in the HAL. Otherwise, the assertions + are replaced by empty macros. + +config ESPRESSIF_SOC_RTC_MEM_SUPPORTED + bool + default n + +menu "Bootloader and Image Configuration" + +config ESPRESSIF_SIMPLE_BOOT + bool + depends on !ESPRESSIF_BOOTLOADER_MCUBOOT + default y + +config ESPRESSIF_BOOTLOADER_MCUBOOT + bool "Enable MCUboot-bootable format" + select ESPRESSIF_HAVE_OTA_PARTITION + depends on ESPRESSIF_ESP32C3 + ---help--- + Enables the Espressif port of MCUboot to be used as 2nd stage bootloader. + +config ESPRESSIF_MCUBOOT_VERSION + string "MCUboot version" + depends on ESPRESSIF_BOOTLOADER_MCUBOOT + default "aa7e2b1faae623dbe01bbc6094e71ab44ec9d80a" + +choice ESPRESSIF_ESPTOOL_TARGET_SLOT + prompt "Target slot for image flashing" + default ESPRESSIF_ESPTOOL_TARGET_PRIMARY + depends on ESPRESSIF_HAVE_OTA_PARTITION + ---help--- + Slot to which ESPTOOL will flash the generated binary image. + +config ESPRESSIF_ESPTOOL_TARGET_PRIMARY + bool "Application image primary slot" + ---help--- + This assumes that the generated image is already pre-validated. + This is the recommended option for the initial stages of the + application firmware image development. + +config ESPRESSIF_ESPTOOL_TARGET_SECONDARY + bool "Application image secondary slot" + ---help--- + The application needs to confirm the generated image as valid, + otherwise the bootloader may consider it invalid and perform the + rollback of the update after a reset. + This is the choice most suitable for the development and verification + of a secure firmware update workflow. + +endchoice + +config ESPRESSIF_APP_MCUBOOT_HEADER_SIZE + int "Application image header size (in bytes)" + default 32 + depends on ESPRESSIF_BOOTLOADER_MCUBOOT + +config ESPRESSIF_PARTITION_TABLE_OFFSET + hex "Partition Table offset" + default 0x8000 + depends on !ESPRESSIF_BOOTLOADER_MCUBOOT && !ESPRESSIF_SIMPLE_BOOT + +config ESPRESSIF_HAVE_OTA_PARTITION + bool + default n + +if ESPRESSIF_HAVE_OTA_PARTITION + +comment "Application Image OTA Update support" + +config ESPRESSIF_OTA_PRIMARY_SLOT_OFFSET + hex "Application image primary slot offset" + default 0x10000 + +config ESPRESSIF_OTA_PRIMARY_SLOT_DEVPATH + string "Application image primary slot device path" + default "/dev/ota0" + +config ESPRESSIF_OTA_SECONDARY_SLOT_OFFSET + hex "Application image secondary slot offset" + default 0x110000 + +config ESPRESSIF_OTA_SECONDARY_SLOT_DEVPATH + string "Application image secondary slot device path" + default "/dev/ota1" + +config ESPRESSIF_OTA_SLOT_SIZE + hex "Application image slot size (in bytes)" + default 0x100000 + +config ESPRESSIF_OTA_SCRATCH_OFFSET + hex "Scratch partition offset" + default 0x210000 + +config ESPRESSIF_OTA_SCRATCH_SIZE + hex "Scratch partition size" + default 0x40000 + +config ESPRESSIF_OTA_SCRATCH_DEVPATH + string "Scratch partition device path" + default "/dev/otascratch" + +endif # ESPRESSIF_HAVE_OTA_PARTITION + +endmenu # Bootloader and Image Configuration + +menu "Peripheral Support" + +config ESPRESSIF_UART + bool + default n + +config ESPRESSIF_UART0 + bool "UART0" + default y + select ESPRESSIF_UART + select UART0_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config ESPRESSIF_UART1 + bool "UART1" + default n + select ESPRESSIF_UART + select UART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config ESPRESSIF_TWAI + bool "TWAI (CAN)" + default n + select ARCH_HAVE_CAN_ERRORS + select CAN + +config ESPRESSIF_TWAI0 + bool "TWAI0 (CAN)" + default n + select ESPRESSIF_TWAI + select ARCH_HAVE_CAN_ERRORS + select CAN + +config ESPRESSIF_TWAI1 + bool "TWAI1 (CAN)" + default n + depends on ESPRESSIF_ESP32C6 + select ESPRESSIF_TWAI + select ARCH_HAVE_CAN_ERRORS + select CAN + +config ESPRESSIF_USBSERIAL + bool "USB-Serial-JTAG Driver" + default n + select OTHER_UART_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config ESPRESSIF_GPIO_IRQ + bool "GPIO pin interrupts" + default n + ---help--- + Enable support for interrupting GPIO pins + +config ESPRESSIF_RTCIO_IRQ + bool "RTC IO interrupts" + default n + depends on !ARCH_CHIP_ESP32H2 && !ARCH_CHIP_ESP32C6 + ---help--- + Enable support for RTC peripherals interrupts. + +config ESPRESSIF_LEDC + bool "LEDC (PWM)" + default n + select PWM + select ARCH_HAVE_PWM_MULTICHAN + +config ESPRESSIF_SPIFLASH + bool "SPI Flash" + default n + +config ESPRESSIF_HR_TIMER + bool + default RTC_DRIVER + ---help--- + A high-resolution hardware timer for supporting the management of + kernel events. + The HR Timer is built on top of the System Timer (SYSTIMER) peripheral. + Timer callbacks are dispatched from a high-priority kernel task. + +config ESPRESSIF_WDT + bool + default n + select WATCHDOG + +config ESPRESSIF_MWDT0 + bool "Main System Watchdog Timer (Group 0)" + default n + select ESPRESSIF_WDT + ---help--- + Includes MWDT0. This watchdog timer is part of the Group 0 + timer submodule. + +config ESPRESSIF_MWDT1 + bool "Main System Watchdog Timer (Group 1)" + default n + select ESPRESSIF_WDT + ---help--- + Includes MWDT1. This watchdog timer is part of the Group 1 + timer submodule. + +config ESPRESSIF_RWDT + bool "RTC Watchdog Timer" + default n + select ESPRESSIF_WDT + ---help--- + Includes RWDT. This watchdog timer is from the RTC module. + When it is selected, if the developer sets it to reset on expiration + it will reset Main System and the RTC module. If you don't want + to have the RTC module reset, please, use the Timers' Module WDTs. + They will only reset Main System. + +config ESPRESSIF_BROWNOUT_DET + bool "Brownout Detector" + default y + ---help--- + A built-in brownout detector which can detect if the voltage is lower + than a specific value. If this happens, it will reset the chip in + order to prevent unintended behaviour. + +config ESP_RMT + bool "Remote Control Module (RMT)" + default n + depends on RMT + ---help--- + The RMT (Remote Control Transceiver) peripheral was designed to act as + an infrared transceiver. However, due to the flexibility of its data + format, RMT can be extended to a versatile and general-purpose + transceiver, transmitting or receiving many other types of signals. + +config ESP_WIRELESS + bool + default n + select NET + select ARCH_PHY_INTERRUPT + select RTC + select RTC_DRIVER + select ESPRESSIF_HR_TIMER + +config ESPRESSIF_WIFI + bool "Wi-Fi" + depends on ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 + default n + select ESP_WIRELESS + ---help--- + Enable Wi-Fi support + +config ESP_COEX_SW_COEXIST_ENABLE + bool "Software WiFi/Bluetooth/IEEE 802.15.4 coexistence" + depends on (ESPRESSIF_WIFI && ESPRESSIF_BLE) || \ + (ESPRESSIF_WIFI && ESP_IEEE802154) || \ + (ESP_IEEE802154 && ESPRESSIF_BLE) + default y + ---help--- + If enabled, WiFi & Bluetooth coexistence is controlled by software rather than hardware. + Recommended for heavy traffic scenarios. Both coexistence configuration options are + automatically managed, no user intervention is required. + If only Bluetooth is used, it is recommended to disable this option to reduce binary file + size. + +endmenu # Peripheral Support + +menu "Wi-Fi Configuration" + depends on ESPRESSIF_WIFI + +menu "ESP WPA-Supplicant" + +config WPA_WAPI_PSK + bool "Enable WAPI PSK support" + default n + ---help--- + Select this option to enable WAPI-PSK + which is a Chinese National Standard Encryption for Wireless LANs (GB 15629.11-2003). + +config WPA_SUITE_B_192 + bool "Enable NSA suite B support with 192-bit key" + default n + select ESPRESSIF_WIFI_GCMP_SUPPORT + select ESPRESSIF_WIFI_GMAC_SUPPORT + ---help--- + Select this option to enable 192-bit NSA suite-B. + This is necessary to support WPA3 192-bit security. + +config ESP_WPA_DEBUG_PRINT + bool "Print debug messages from Espressif's WPA Supplicant" + default n + ---help--- + Select this option to print logging information from WPA supplicant, + this includes handshake information and key hex dumps depending + on the project logging level. + + Enabling this could increase the build size ~60kb + depending on the project logging level. + +endmenu # ESP WPA-Supplicant + +choice ESPRESSIF_WIFI_MODE + prompt "ESP Wi-Fi mode" + default ESPRESSIF_WIFI_STATION + +config ESPRESSIF_WIFI_STATION + bool "Station mode" + +config ESPRESSIF_WIFI_SOFTAP + bool "SoftAP mode" + +config ESPRESSIF_WIFI_STATION_SOFTAP + bool "Station + SoftAP" + +endchoice # ESPRESSIF_WIFI_MODE + +config ESPRESSIF_WIFI_ENABLE_WPA3_SAE + bool "Enable WPA3-Personal" + default y + ---help--- + Select this option to allow the device to establish a WPA3-Personal connection with eligible AP's. + PMF (Protected Management Frames) is a prerequisite feature for a WPA3 connection, it needs to be + explicitly configured before attempting connection. Please refer to the Wi-Fi Driver API Guide for details. + +config ESPRESSIF_WIFI_ENABLE_SAE_PK + bool "Enable SAE-PK" + depends on ESPRESSIF_WIFI_ENABLE_WPA3_SAE + default y + ---help--- + Select this option to enable SAE-PK + +config ESPRESSIF_WIFI_SOFTAP_SAE_SUPPORT + bool "Enable WPA3 Personal(SAE) SoftAP" + default y + depends on ESPRESSIF_WIFI_ENABLE_WPA3_SAE + depends on ESPRESSIF_WIFI_SOFTAP || ESPRESSIF_WIFI_STATION_SOFTAP + ---help--- + Select this option to enable SAE support in softAP mode. + +config ESPRESSIF_WIFI_ENABLE_WPA3_OWE_STA + bool "Enable OWE STA" + default y + ---help--- + Select this option to allow the device to establish OWE connection with eligible AP's. + PMF (Protected Management Frames) is a prerequisite feature for a WPA3 connection, it needs to be + explicitly configured before attempting connection. Please refer to the Wi-Fi Driver API Guide for details. + +config ESPRESSIF_WIFI_STATIC_RX_BUFFER_NUM + int "Max number of WiFi static RX buffers" + range 2 25 if !ESPRESSIF_ESP32C6 + range 2 128 if ESPRESSIF_ESP32C6 + default 10 + ---help--- + Set the number of WiFi static RX buffers. Each buffer takes approximately 1.6KB of RAM. + The static rx buffers are allocated when esp_wifi_init is called, they are not freed + until esp_wifi_deinit is called. + + WiFi hardware use these buffers to receive all 802.11 frames. + A higher number may allow higher throughput but increases memory use. If ESPRESSIF_WIFI_AMPDU_RX_ENABLED + is enabled, this value is recommended to set equal or bigger than ESPRESSIF_WIFI_RX_BA_WIN in order to + achieve better throughput and compatibility with both stations and APs. + +config ESPRESSIF_WIFI_DYNAMIC_RX_BUFFER_NUM + int "Max number of WiFi dynamic RX buffers" + default 32 + ---help--- + Set the number of WiFi dynamic RX buffers, 0 means unlimited RX buffers will be allocated + (provided sufficient free RAM). The size of each dynamic RX buffer depends on the size of + the received data frame. + + For each received data frame, the WiFi driver makes a copy to an RX buffer and then delivers + it to the high layer TCP/IP stack. The dynamic RX buffer is freed after the higher layer has + successfully received the data frame. + + For some applications, WiFi data frames may be received faster than the application can + process them. In these cases we may run out of memory if RX buffer number is unlimited (0). + + If a dynamic RX buffer limit is set, it should be at least the number of static RX buffers. + +config ESPRESSIF_WIFI_DYNAMIC_TX_BUFFER_NUM + int "Max number of WiFi dynamic TX buffers" + range 1 128 + default 32 + ---help--- + Set the number of WiFi dynamic TX buffers. The size of each dynamic TX buffer is not fixed, + it depends on the size of each transmitted data frame. + + For each transmitted frame from the higher layer TCP/IP stack, the WiFi driver makes a copy + of it in a TX buffer. For some applications, especially UDP applications, the upper layer + can deliver frames faster than WiFi layer can transmit. In these cases, we may run out of TX + buffers. + +config ESPRESSIF_WIFI_AMPDU_TX_ENABLED + bool "Wi-Fi TX AMPDU" + default y + ---help--- + Select this option to enable AMPDU TX feature + +config ESPRESSIF_WIFI_TX_BA_WIN + int "WiFi AMPDU TX BA window size" + depends on ESPRESSIF_WIFI_AMPDU_TX_ENABLED + range 2 32 if !ESPRESSIF_ESP32C6 + range 2 64 if ESPRESSIF_ESP32C6 + default 6 + +config ESPRESSIF_WIFI_AMPDU_RX_ENABLED + bool "WiFi AMPDU RX" + default y + ---help--- + Select this option to enable AMPDU RX feature + +config ESPRESSIF_WIFI_RX_BA_WIN + int "WiFi AMPDU RX BA window size" + depends on ESPRESSIF_WIFI_AMPDU_RX_ENABLED + range 2 32 if !ESPRESSIF_ESP32C6 + range 2 64 if ESPRESSIF_ESP32C6 + default 6 + ---help--- + Set the size of WiFi Block Ack RX window. Generally a bigger value means higher throughput and better + compatibility but more memory. Most of time we should NOT change the default value unless special + reason, e.g. test the maximum UDP RX throughput with iperf etc. For iperf test in shieldbox, the + recommended value is 9~12. If PSRAM is used and WiFi memory is prefered to allocat in PSRAM first, + the default and minimum value should be 16 to achieve better throughput and compatibility with both + stations and APs. + +config ESPRESSIF_WIFI_GCMP_SUPPORT + bool "WiFi GCMP Support(GCMP128 and GCMP256)" + default n + ---help--- + Select this option to enable GCMP support. GCMP support is compulsory for WiFi Suite-B support. + +config ESPRESSIF_WIFI_GMAC_SUPPORT + bool "WiFi GMAC Support(GMAC128 and GMAC256)" + default n + ---help--- + Select this option to enable GMAC support. GMAC support is compulsory for WiFi 192-bit certification. + +config ESPRESSIF_WIFI_CONNECT_TIMEOUT + int "Connect timeout in second" + default 10 + ---help--- + Max waiting time of connecting to AP. + +config ESPRESSIF_WIFI_SCAN_RESULT_SIZE + int "Scan result buffer" + default 4096 + ---help--- + Maximum scan result buffer size. + +config ESPRESSIF_WIFI_STA_DISCONNECT_PM + bool "Power Management for station when disconnected" + default y + ---help--- + Select this option to enable power management for station when disconnected. + Chip will do modem-sleep when RF module is not in use anymore. + +choice ESP_POWER_SAVE_MODE + prompt "Wi-Fi Power save mode" + default ESP_POWER_SAVE_MIN_MODEM if ESPRESSIF_WIFI_BT_COEXIST + default ESP_POWER_SAVE_NONE + ---help--- + Wi-Fi supports the Modem-sleep mode which refers to the legacy power-saving mode in the IEEE 802.11 protocol. + Modem-sleep mode works in station-only mode and the station must connect to the AP first. If the Modem-sleep + mode is enabled, station will switch between active and sleep state periodically. In sleep state, RF, PHY and + BB are turned off in order to reduce power consumption. Station can keep connection with AP in modem-sleep mode. + + Modem-sleep mode includes minimum and maximum power-saving modes. + + In minimum power-saving mode, station wakes + up every DTIM to receive beacon. Broadcast data will not be lost because it is transmitted after DTIM. + However, it cannot save much more power if DTIM is short for DTIM is determined by AP. + + In maximum power-saving mode, station wakes up in every listen interval to receive beacon. This listen interval + can be set to be longer than the AP DTIM period. Broadcast data may be lost because station may be in sleep + state at DTIM time. If listen interval is longer, more power is saved, but broadcast data is more easy to lose. + Listen interval can be configured by setting ESPRESSIF_WIFI_LISTEN_INTERVAL. + + ESP_POWER_SAVE_NONE disables Modem-sleep mode entirely. Disabling it increases power consumption, but + minimizes the delay in receiving Wi-Fi data in real time. When Modem-sleep mode is enabled, the delay in + receiving Wi-Fi data may be the same as the DTIM cycle (minimum power-saving mode) or the listening interval + (maximum power-saving mode). Setting ESP_POWER_SAVE_NONE is suitable when high throughput is required. + +config ESP_POWER_SAVE_NONE + bool "No power save" + +config ESP_POWER_SAVE_MIN_MODEM + bool "Minimum modem power saving." + +config ESP_POWER_SAVE_MAX_MODEM + bool "Maximum modem power saving" + +endchoice # ESP_POWER_SAVE_MODE + +endmenu # ESPRESSIF_WIFI + +menu "UART Configuration" + depends on ESPRESSIF_UART + +if ESPRESSIF_UART0 + +config ESPRESSIF_UART0_TXPIN + int "UART0 TX Pin" + default 21 if ESPRESSIF_ESP32C3 + default 16 if ESPRESSIF_ESP32C6 + default 24 if ESPRESSIF_ESP32H2 + range 0 21 if ESPRESSIF_ESP32C3 + range 0 30 if ESPRESSIF_ESP32C6 + range 0 27 if ESPRESSIF_ESP32H2 + +config ESPRESSIF_UART0_RXPIN + int "UART0 RX Pin" + default 20 if ESPRESSIF_ESP32C3 + default 17 if ESPRESSIF_ESP32C6 + default 23 if ESPRESSIF_ESP32H2 + range 0 21 if ESPRESSIF_ESP32C3 + range 0 30 if ESPRESSIF_ESP32C6 + range 0 27 if ESPRESSIF_ESP32H2 + +config ESPRESSIF_UART0_RTSPIN + int "UART0 RTS Pin" + depends on SERIAL_IFLOWCONTROL + default 16 if ESPRESSIF_ESP32C3 + default 15 if ESPRESSIF_ESP32C6 + default 22 if ESPRESSIF_ESP32H2 + range 0 21 if ESPRESSIF_ESP32C3 + range 0 30 if ESPRESSIF_ESP32C6 + range 0 27 if ESPRESSIF_ESP32H2 + +config ESPRESSIF_UART0_CTSPIN + int "UART0 CTS Pin" + depends on SERIAL_OFLOWCONTROL + default 15 if ESPRESSIF_ESP32C3 + default 14 if ESPRESSIF_ESP32C6 + default 21 if ESPRESSIF_ESP32H2 + range 0 21 if ESPRESSIF_ESP32C3 + range 0 30 if ESPRESSIF_ESP32C6 + range 0 27 if ESPRESSIF_ESP32H2 + +endif # ESPRESSIF_UART0 + +if ESPRESSIF_UART1 + +config ESPRESSIF_UART1_TXPIN + int "UART1 TX Pin" + default 8 if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2 + +config ESPRESSIF_UART1_RXPIN + int "UART1 RX Pin" + default 9 if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2 + +config ESPRESSIF_UART1_RTSPIN + int "UART1 RTS Pin" + depends on SERIAL_IFLOWCONTROL + default 1 if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2 + range 0 21 if ESPRESSIF_ESP32C3 + range 0 30 if ESPRESSIF_ESP32C6 + range 0 27 if ESPRESSIF_ESP32H2 + +config ESPRESSIF_UART1_CTSPIN + int "UART1 CTS Pin" + depends on SERIAL_OFLOWCONTROL + default 2 if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2 + range 0 21 if ESPRESSIF_ESP32C3 + range 0 30 if ESPRESSIF_ESP32C6 + range 0 27 if ESPRESSIF_ESP32H2 + +endif # ESPRESSIF_UART1 + +endmenu # UART Configuration + +menu "TWAI driver options" + depends on ESPRESSIF_TWAI + +if ESPRESSIF_TWAI0 + +config ESPRESSIF_TWAI0_TXPIN + int "TWAI0 TX Pin" + default 2 + +config ESPRESSIF_TWAI0_RXPIN + int "TWAI0 RX Pin" + default 3 + +choice ESPRESSIF_TWAI0_TIMING + prompt "TWAI0 Timing config" + default TWAI0_TIMING_100KBITS + ---help--- + These options control timing of TWAI0. + +config TWAI0_TIMING_100KBITS + bool "100 KBits" + +config TWAI0_TIMING_125KBITS + bool "125 KBits" + +config TWAI0_TIMING_250KBITS + bool "250 KBits" + +config TWAI0_TIMING_500KBITS + bool "500 KBits" + +config TWAI0_TIMING_800KBITS + bool "800 KBits" + +endchoice # ESPRESSIF_TWAI0_TIMING + +config ESPRESSIF_TWAI0_SAM + bool "TWAI0 sampling" + default n + ---help--- + The bus is sampled 3 times (recommended for low to medium speed buses + to spikes on the bus-line). + +endif # ESPRESSIF_TWAI0 + +if ESPRESSIF_TWAI1 + +config ESPRESSIF_TWAI1_TXPIN + int "TWAI1 TX Pin" + default 4 + +config ESPRESSIF_TWAI1_RXPIN + int "TWAI1 RX Pin" + default 5 + +choice ESPRESSIF_TWAI1_TIMING + prompt "TWAI1 Timing config" + default TWAI1_TIMING_100KBITS + ---help--- + These options control timing of TWAI1. + +config TWAI1_TIMING_100KBITS + bool "100 KBits" + +config TWAI1_TIMING_125KBITS + bool "125 KBits" + +config TWAI1_TIMING_250KBITS + bool "250 KBits" + +config TWAI1_TIMING_500KBITS + bool "500 KBits" + +config TWAI1_TIMING_800KBITS + bool "800 KBits" + +endchoice # ESPRESSIF_TWAI1_TIMING + +config ESPRESSIF_TWAI1_SAM + bool "TWAI1 sampling" + default n + ---help--- + The bus is sampled 3 times (recommended for low to medium speed buses + to spikes on the bus-line). + +endif # ESPRESSIF_TWAI1 + +config ESPRESSIF_TWAI_TEST_MODE + bool "TWAI character driver loopback test mode (for testing only)" + default n + depends on CAN_LOOPBACK + ---help--- + This enables a loopback test mode that attaches the transmitter + to the receiver internally, being able to test the TWAI + peripheral without any external connection. + +endmenu #ESPRESSIF_TWAI + +menu "SPI Flash Configuration" + +choice ESPRESSIF_FLASH_MODE + prompt "SPI Flash mode" + default ESPRESSIF_FLASH_MODE_DIO + ---help--- + These options control how many I/O pins are used for communication with the attached SPI Flash chip. + The option selected here is then used by esptool when flashing. + +config ESPRESSIF_FLASH_MODE_DIO + bool "Dual IO (DIO)" + +config ESPRESSIF_FLASH_MODE_DOUT + bool "Dual Output (DOUT)" + +config ESPRESSIF_FLASH_MODE_QIO + bool "Quad IO (QIO)" + +config ESPRESSIF_FLASH_MODE_QOUT + bool "Quad Output (QOUT)" + +endchoice # ESPRESSIF_FLASH_MODE + +if ESPRESSIF_SPIFLASH +comment "General storage MTD configuration" + +config ESPRESSIF_MTD + bool "MTD driver" + default y + select MTD + select MTD_BYTE_WRITE + select MTD_PARTITION + ---help--- + Initialize an MTD driver for the SPI Flash, which will + add an entry at /dev for application access from userspace. + +config ESPRESSIF_SPIFLASH_MTD_BLKSIZE + int "Storage MTD block size" + default 64 + depends on ESPRESSIF_MTD + ---help--- + Block size for MTD driver in kB. This size must be divisible by 2 + +config ESPRESSIF_STORAGE_MTD_DEBUG + bool "Storage MTD Debug" + default n + depends on ESPRESSIF_MTD && DEBUG_FS_INFO + ---help--- + If this option is enabled, Storage MTD driver read and write functions + will output input parameters and return values (if applicable). +endif # ESPRESSIF_SPIFLASH + +choice ESPRESSIF_FLASH_FREQ + prompt "SPI Flash frequency" + default ESPRESSIF_FLASH_FREQ_80M if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 + default ESPRESSIF_FLASH_FREQ_48M if ESPRESSIF_ESP32H2 + ---help--- + SPI Flash frequency. + +config ESPRESSIF_FLASH_FREQ_80M + bool "80 MHz" + depends on ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 + +config ESPRESSIF_FLASH_FREQ_48M + bool "48 MHz" + depends on ESPRESSIF_ESP32H2 + +config ESPRESSIF_FLASH_FREQ_40M + bool "40 MHz" + depends on ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 + +config ESPRESSIF_FLASH_FREQ_26M + bool "26 MHz" + depends on ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 + +config ESPRESSIF_FLASH_FREQ_20M + bool "20 MHz" + depends on ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 + +endchoice # ESPRESSIF_FLASH_FREQ + +config ESPRESSIF_SPI_FLASH_USE_ROM_CODE + bool "Use SPI flash driver in ROM" + default n + depends on ESPRESSIF_ESP32C3 + ---help--- + Use functions in ROM for SPI flash driver instead of + source code. + +config ESPRESSIF_SPI_FLASH_USE_32BIT_ADDRESS + bool "SPI flash uses 32-bit address" + default n + ---help--- + SPI flash driver in ROM only support 24-bit address access, + if select the option, it will force to use source code instead + of functions in ROM, so that SPI flash driver can access full + 32-bit address. + +config ESPRESSIF_STORAGE_MTD_OFFSET + hex "Storage MTD base address in SPI Flash" + default 0x180000 + depends on ESPRESSIF_MTD + ---help--- + MTD base address in SPI Flash. + +config ESPRESSIF_STORAGE_MTD_SIZE + hex "Storage MTD size in SPI Flash" + default 0x100000 + depends on ESPRESSIF_MTD + ---help--- + MTD size in SPI Flash. + +endmenu # SPI Flash Configuration + +menu "LEDC configuration" + depends on ESPRESSIF_LEDC + +config ESPRESSIF_LEDC_HPOINT + hex "LEDC hpoint value" + default 0x0000 + range 0x0 0xfffff + +menuconfig ESPRESSIF_LEDC_TIMER0 + bool "Timer 0" + default n + +if ESPRESSIF_LEDC_TIMER0 + +config ESPRESSIF_LEDC_TIMER0_CHANNELS + int "Number of Timer 0 channels" + default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1 + default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1 + range 0 6 + +config ESPRESSIF_LEDC_TIMER0_RESOLUTION + int "Timer 0 resolution" + default 13 + range 1 14 if ESPRESSIF_ESP32C3 && !(ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2) + range 1 20 if !ESPRESSIF_ESP32C3 && (ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2) + ---help--- + Timer resolution in bits. The resolution is the number of bits used to by the timer + counter to generate the PWM signal. The duty cycle provided by the upper layers + will be scaled to fit the resolution. + +endif # ESPRESSIF_LEDC_TIMER0 + +menuconfig ESPRESSIF_LEDC_TIMER1 + bool "Timer 1" + default n + +if ESPRESSIF_LEDC_TIMER1 + +config ESPRESSIF_LEDC_TIMER1_CHANNELS + int "Number of Timer 1 channels" + default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1 + default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1 + range 0 6 + +config ESPRESSIF_LEDC_TIMER1_RESOLUTION + int "Timer 1 resolution" + default 13 + range 1 14 if ESPRESSIF_ESP32C3 && !(ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2) + range 1 20 if !ESPRESSIF_ESP32C3 && (ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2) + ---help--- + Timer resolution in bits. The resolution is the number of bits used to by the timer + counter to generate the PWM signal. The duty cycle provided by the upper layers + will be scaled to fit the resolution. + +endif # ESPRESSIF_LEDC_TIMER1 + +menuconfig ESPRESSIF_LEDC_TIMER2 + bool "Timer 2" + default n + +if ESPRESSIF_LEDC_TIMER2 + +config ESPRESSIF_LEDC_TIMER2_CHANNELS + int "Number of Timer 2 channels" + default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1 + default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1 + range 0 6 + +config ESPRESSIF_LEDC_TIMER2_RESOLUTION + int "Timer 2 resolution" + default 13 + range 1 14 if ESPRESSIF_ESP32C3 && !(ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2) + range 1 20 if !ESPRESSIF_ESP32C3 && (ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2) + ---help--- + Timer resolution in bits. The resolution is the number of bits used to by the timer + counter to generate the PWM signal. The duty cycle provided by the upper layers + will be scaled to fit the resolution. + +endif # ESPRESSIF_LEDC_TIMER2 + +menuconfig ESPRESSIF_LEDC_TIMER3 + bool "Timer 3" + default n + +if ESPRESSIF_LEDC_TIMER3 + +config ESPRESSIF_LEDC_TIMER3_CHANNELS + int "Number of Timer 3 channels" + default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1 + default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1 + range 0 6 + +config ESPRESSIF_LEDC_TIMER3_RESOLUTION + int "Timer 3 resolution" + default 13 + range 1 14 if ESPRESSIF_ESP32C3 && !(ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2) + range 1 20 if !ESPRESSIF_ESP32C3 && (ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2) + ---help--- + Timer resolution in bits. The resolution is the number of bits used to by the timer + counter to generate the PWM signal. The duty cycle provided by the upper layers + will be scaled to fit the resolution. + +endif # ESPRESSIF_LEDC_TIMER3 + +config ESPRESSIF_LEDC_CHANNEL0_PIN + int "Channel 0 pin" + default 2 + +config ESPRESSIF_LEDC_CHANNEL1_PIN + int "Channel 1 pin" + default 3 + +config ESPRESSIF_LEDC_CHANNEL2_PIN + int "Channel 2 pin" + default 4 + +config ESPRESSIF_LEDC_CHANNEL3_PIN + int "Channel 3 pin" + default 5 + +if PWM_MULTICHAN && PWM_NCHANNELS > 1 + +config ESPRESSIF_LEDC_CHANNEL4_PIN + int "Channel 4 pin" + default 6 + +config ESPRESSIF_LEDC_CHANNEL5_PIN + int "Channel 5 pin" + default 7 + +endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 + +endmenu # LEDC configuration + +menu "High Resolution Timer" + depends on ESPRESSIF_HR_TIMER + +config ESPRESSIF_HR_TIMER_TASK_NAME + string "High Resolution Timer task name" + default "hr_timer" + +config ESPRESSIF_HR_TIMER_TASK_PRIORITY + int "High Resolution Timer task priority" + default 223 + ---help--- + Priority level of the High Resolution Timer task. + Must be lower than the SCHED_HPWORKPRIORITY. + +config ESPRESSIF_HR_TIMER_TASK_STACK_SIZE + int "High Resolution Timer task stack size" + default 2048 + +endmenu # High Resolution Timer + +menu "Brownout Detector Configuration" + depends on ESPRESSIF_BROWNOUT_DET + +choice ESPRESSIF_BROWNOUT_DET_LVL_SEL + prompt "Brownout voltage level" + default ESPRESSIF_BROWNOUT_DET_LVL_SEL_7 + ---help--- + The brownout detector will reset the chip when the supply voltage is + approximately below this level. Note that there may be some variation + of brownout voltage level between each chip. + +config ESPRESSIF_BROWNOUT_DET_LVL_SEL_7 + bool "2.51V" + +config ESPRESSIF_BROWNOUT_DET_LVL_SEL_6 + bool "2.64V" + +config ESPRESSIF_BROWNOUT_DET_LVL_SEL_5 + bool "2.76V" + +config ESPRESSIF_BROWNOUT_DET_LVL_SEL_4 + bool "2.92V" + +config ESPRESSIF_BROWNOUT_DET_LVL_SEL_3 + bool "3.10V" + +config ESPRESSIF_BROWNOUT_DET_LVL_SEL_2 + bool "3.27V" + +endchoice # ESPRESSIF_BROWNOUT_DET_LVL_SEL + +config ESPRESSIF_BROWNOUT_DET_LVL + int + default 2 if ESPRESSIF_BROWNOUT_DET_LVL_SEL_2 + default 3 if ESPRESSIF_BROWNOUT_DET_LVL_SEL_3 + default 4 if ESPRESSIF_BROWNOUT_DET_LVL_SEL_4 + default 5 if ESPRESSIF_BROWNOUT_DET_LVL_SEL_5 + default 6 if ESPRESSIF_BROWNOUT_DET_LVL_SEL_6 + default 7 if ESPRESSIF_BROWNOUT_DET_LVL_SEL_7 + +endmenu # ESPRESSIF_BROWNOUT_DET + +endif # ARCH_CHIP_ESPRESSIF diff --git a/arch/risc-v/src/common/espressif/Make.defs b/arch/risc-v/src/common/espressif/Make.defs new file mode 100644 index 0000000000000..a0ca100eb554c --- /dev/null +++ b/arch/risc-v/src/common/espressif/Make.defs @@ -0,0 +1,164 @@ +############################################################################ +# arch/risc-v/src/common/espressif/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# The start-up, "head", file. May be either a .S or a .c file. + +HEAD_ASRC = esp_head.S + +# Skip common RISC-V vector table in favor of Espressif's custom vector +# table. + +CMN_ASRCS := $(filter-out riscv_vectors.S,$(CMN_ASRCS)) +CHIP_ASRCS = esp_vectors.S + +# Required Espressif chip's files (arch/risc-v/src/common/espressif) + +CHIP_CSRCS = esp_allocateheap.c esp_start.c esp_idle.c +CHIP_CSRCS += esp_irq.c esp_gpio.c esp_rtc_gpio.c esp_libc_stubs.c +CHIP_CSRCS += esp_lowputc.c esp_serial.c +CHIP_CSRCS += esp_systemreset.c + +ifeq ($(CONFIG_SCHED_TICKLESS),y) + CHIP_CSRCS += esp_tickless.c +else + CHIP_CSRCS += esp_timerisr.c +endif + +ifeq ($(CONFIG_ESPRESSIF_WDT),y) + CHIP_CSRCS += esp_wdt.c +endif + +ifneq ($(CONFIG_DEV_RANDOM)$(CONFIG_DEV_URANDOM_ARCH),) + CHIP_CSRCS += esp_random.c +endif + +ifeq ($(CONFIG_TIMER),y) + CHIP_CSRCS += esp_timer.c +endif + +ifeq ($(CONFIG_ONESHOT),y) + CHIP_CSRCS += esp_oneshot.c +endif + +ifeq ($(CONFIG_RTC),y) + CHIP_CSRCS += esp_rtc.c +endif + +ifeq ($(CONFIG_ESPRESSIF_HR_TIMER),y) + CHIP_CSRCS += esp_hr_timer.c esp_ets_timer_legacy.c +endif + +ifeq ($(CONFIG_ESPRESSIF_TWAI),y) + CHIP_CSRCS += esp_twai.c +endif + +ifeq ($(CONFIG_ESPRESSIF_LEDC),y) + CHIP_CSRCS += esp_ledc.c +endif + +ifeq ($(CONFIG_ESPRESSIF_USBSERIAL),y) + CHIP_CSRCS += esp_usbserial.c +endif + +ifeq ($(CONFIG_ESP_RMT),y) + CHIP_CSRCS += esp_rmt.c + ifeq ($(CONFIG_WS2812_NON_SPI_DRIVER),y) + CHIP_CSRCS += esp_ws2812.c + endif +endif + +ifeq ($(CONFIG_ESPRESSIF_SPIFLASH),y) + CHIP_CSRCS += esp_spiflash.c + ifeq ($(CONFIG_ESPRESSIF_MTD),y) + CHIP_CSRCS += esp_spiflash_mtd.c + endif +endif + +ifeq ($(CONFIG_ESP_WIRELESS),y) + ifeq ($(CONFIG_ESPRESSIF_WIFI),y) + CHIP_CSRCS += esp_wifi_init.c + CHIP_CSRCS += esp_wlan.c + CHIP_CSRCS += esp_wifi_utils.c + endif +endif + +############################################################################# +# Espressif HAL for 3rd Party Platforms +############################################################################# + +# Fetch source files and add them to build + +ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty +ifndef ESP_HAL_3RDPARTY_VERSION + ESP_HAL_3RDPARTY_VERSION = ee8c7b0ad6a117465312d4c9a6e654cb7b2b9469 +endif + +ifndef ESP_HAL_3RDPARTY_URL + ESP_HAL_3RDPARTY_URL = https://github.com/espressif/esp-hal-3rdparty.git +endif + +ifndef DISABLE_GIT_DEPTH +ifndef GIT_DEPTH + GIT_DEPTH=1 +endif + GIT_DEPTH_PARAMETER = --depth=$(GIT_DEPTH) +endif + +chip/$(ESP_HAL_3RDPARTY_REPO): + $(Q) echo "Cloning Espressif HAL for 3rd Party Platforms" + $(Q) git clone --quiet $(ESP_HAL_3RDPARTY_URL) chip/$(ESP_HAL_3RDPARTY_REPO) + $(Q) echo "Espressif HAL for 3rd Party Platforms: ${ESP_HAL_3RDPARTY_VERSION}" + $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) checkout --quiet $(ESP_HAL_3RDPARTY_VERSION) +ifeq ($(CONFIG_ESP_WIRELESS),y) + $(Q) echo "Espressif HAL for 3rd Party Platforms: initializing submodules..." + $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) submodule --quiet update --init $(GIT_DEPTH_PARAMETER) components/mbedtls/mbedtls components/esp_phy/lib components/esp_wifi/lib components/esp_coex/lib + $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls reset --quiet --hard + $(Q) echo "Applying patches..." + $(Q) cd chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls && git apply ../../../nuttx/patches/components/mbedtls/mbedtls/*.patch +endif + +include common$(DELIM)espressif$(DELIM)Bootloader.mk + +# Silent preprocessor warnings + +CFLAGS += -Wno-undef -Wno-unused-variable + +# Remove quotes from CONFIG_ESPRESSIF_CHIP_SERIES configuration + +CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES)) + +include chip/hal_${CHIP_SERIES}.mk + +ifeq ($(CONFIG_ESP_WIRELESS),y) + include common$(DELIM)espressif$(DELIM)Wireless.mk +endif + +context:: chip/$(ESP_HAL_3RDPARTY_REPO) + $(call COPYFILE,chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/include/soc/gpio_sig_map.h,../include/chip/) + $(call COPYFILE,chip/$(ESP_HAL_3RDPARTY_REPO)/nuttx/$(CHIP_SERIES)/include/irq.h,../include/chip/) + +distclean:: + $(call DELFILE,../include/chip/gpio_sig_map.h) + $(call DELFILE,../include/chip/irq.h) + $(call DELDIR,chip/$(ESP_HAL_3RDPARTY_REPO)) + +INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)common$(DELIM)espressif +INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)common$(DELIM)espressif$(DELIM)platform_include +VPATH += common$(DELIM)espressif diff --git a/arch/risc-v/src/common/espressif/Wireless.mk b/arch/risc-v/src/common/espressif/Wireless.mk new file mode 100644 index 0000000000000..e2e627ca9f47a --- /dev/null +++ b/arch/risc-v/src/common/espressif/Wireless.mk @@ -0,0 +1,242 @@ +############################################################################ +# arch/risc-v/src/common/espressif/Wireless.mk +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)include$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_coex$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)esp_wifi + +EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_coex$(DELIM)lib$(DELIM)$(CHIP_SERIES) +EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)lib$(DELIM)$(CHIP_SERIES) +EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)lib$(DELIM)$(CHIP_SERIES) + +EXTRA_LIBS += -lphy -lcoexist -lmesh + +ifeq ($(CONFIG_ESPRESSIF_WIFI),y) + +ifeq ($(CONFIG_WPA_WAPI_PSK),y) +EXTRA_LIBS += -lwapi +endif + +## ESP-IDF's mbedTLS + +VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)library + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)library +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls + +### Define Espressif's configs for mbedTLS + +CFLAGS += $(DEFINE_PREFIX)MBEDTLS_CONFIG_FILE="" + +CHIP_CSRCS += aes.c +CHIP_CSRCS += aria.c +CHIP_CSRCS += bignum_core.c +CHIP_CSRCS += bignum.c +CHIP_CSRCS += ccm.c +CHIP_CSRCS += cipher_wrap.c +CHIP_CSRCS += cipher.c +CHIP_CSRCS += cmac.c +CHIP_CSRCS += constant_time.c +CHIP_CSRCS += ctr_drbg.c +CHIP_CSRCS += ecp_curves.c +CHIP_CSRCS += ecp.c +CHIP_CSRCS += entropy.c +CHIP_CSRCS += gcm.c +CHIP_CSRCS += md.c +CHIP_CSRCS += pkcs5.c +CHIP_CSRCS += platform_util.c +CHIP_CSRCS += platform.c +CHIP_CSRCS += sha1.c +CHIP_CSRCS += sha256.c +CHIP_CSRCS += sha512.c +CHIP_CSRCS += pk.c +CHIP_CSRCS += pk_wrap.c +CHIP_CSRCS += pkparse.c +CHIP_CSRCS += ecdsa.c +CHIP_CSRCS += asn1parse.c +CHIP_CSRCS += asn1write.c +CHIP_CSRCS += rsa.c +CHIP_CSRCS += md5.c +CHIP_CSRCS += oid.c +CHIP_CSRCS += pem.c +CHIP_CSRCS += hmac_drbg.c +CHIP_CSRCS += hash_info.c +CHIP_CSRCS += rsa_alt_helpers.c +CHIP_CSRCS += ecdh.c + +VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port + +CHIP_CSRCS += esp_hardware.c +CHIP_CSRCS += esp_mem.c +CHIP_CSRCS += esp_timing.c + +VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)md + +CHIP_CSRCS += esp_md.c + +## WPA Supplicant + +WIFI_WPA_SUPPLICANT = chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)wpa_supplicant + +CFLAGS += $(DEFINE_PREFIX)__ets__ +CFLAGS += $(DEFINE_PREFIX)CONFIG_CRYPTO_MBEDTLS +CFLAGS += $(DEFINE_PREFIX)CONFIG_ECC +CFLAGS += $(DEFINE_PREFIX)CONFIG_IEEE80211W +CFLAGS += $(DEFINE_PREFIX)CONFIG_WPA3_SAE +CFLAGS += $(DEFINE_PREFIX)EAP_PEER_METHOD +CFLAGS += $(DEFINE_PREFIX)ESP_PLATFORM=1 +CFLAGS += $(DEFINE_PREFIX)ESP_SUPPLICANT +CFLAGS += $(DEFINE_PREFIX)ESPRESSIF_USE +CFLAGS += $(DEFINE_PREFIX)IEEE8021X_EAPOL +CFLAGS += $(DEFINE_PREFIX)USE_WPA2_TASK +CFLAGS += $(DEFINE_PREFIX)CONFIG_SHA256 +CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE + +ifeq ($(CONFIG_ESPRESSIF_WIFI_ENABLE_SAE_PK),y) +CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE_PK +endif + +ifeq ($(CONFIG_ESPRESSIF_WIFI_ENABLE_WPA3_OWE_STA),y) +CFLAGS += $(DEFINE_PREFIX)CONFIG_OWE_STA +endif + +ifeq ($(CONFIG_ESPRESSIF_WIFI_GCMP_SUPPORT),y) +CFLAGS += $(DEFINE_PREFIX)CONFIG_GCMP +endif + +ifeq ($(CONFIG_ESPRESSIF_WIFI_GMAC_SUPPORT),y) +CFLAGS += $(DEFINE_PREFIX)CONFIG_GMAC +endif + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src + +VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)ap + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)ap + +CHIP_CSRCS += ap_config.c +CHIP_CSRCS += ieee802_11.c +CHIP_CSRCS += comeback_token.c +CHIP_CSRCS += pmksa_cache_auth.c +CHIP_CSRCS += sta_info.c +CHIP_CSRCS += wpa_auth_ie.c +CHIP_CSRCS += wpa_auth.c + +VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)common + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)common + +CHIP_CSRCS += dragonfly.c +CHIP_CSRCS += sae.c +CHIP_CSRCS += wpa_common.c +CHIP_CSRCS += sae_pk.c +CHIP_CSRCS += bss.c +CHIP_CSRCS += scan.c +CHIP_CSRCS += ieee802_11_common.c + +VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)crypto + +CHIP_CSRCS += aes-ccm.c +CHIP_CSRCS += aes-gcm.c +CHIP_CSRCS += aes-omac1.c +CHIP_CSRCS += aes-unwrap.c +CHIP_CSRCS += aes-wrap.c +CHIP_CSRCS += ccmp.c +CHIP_CSRCS += crypto_ops.c +CHIP_CSRCS += des-internal.c +CHIP_CSRCS += dh_groups.c +CHIP_CSRCS += rc4.c +CHIP_CSRCS += sha1-prf.c +CHIP_CSRCS += sha256-kdf.c +CHIP_CSRCS += sha256-prf.c + +VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)eap_peer + +CHIP_CSRCS += chap.c +CHIP_CSRCS += eap_common.c +CHIP_CSRCS += eap_mschapv2.c +CHIP_CSRCS += eap_peap_common.c +CHIP_CSRCS += eap_peap.c +CHIP_CSRCS += eap_tls_common.c +CHIP_CSRCS += eap_tls.c +CHIP_CSRCS += eap_ttls.c +CHIP_CSRCS += eap.c +CHIP_CSRCS += mschapv2.c + +VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)rsn_supp + +CHIP_CSRCS += pmksa_cache.c +CHIP_CSRCS += wpa_ie.c +CHIP_CSRCS += wpa.c + +VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)utils + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)utils + +CHIP_CSRCS += base64.c +CHIP_CSRCS += bitfield.c +CHIP_CSRCS += common.c +CHIP_CSRCS += ext_password.c +CHIP_CSRCS += json.c +CHIP_CSRCS += uuid.c +CHIP_CSRCS += wpa_debug.c +CHIP_CSRCS += wpabuf.c + +VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)port + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)port$(DELIM)include + +CHIP_CSRCS += eloop.c +CHIP_CSRCS += os_xtensa.c + +## ESP Supplicant (Espressif's WPA supplicant extension) + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)include + +VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src + +CHIP_CSRCS += esp_common.c +CHIP_CSRCS += esp_hostap.c +CHIP_CSRCS += esp_wpa_main.c +CHIP_CSRCS += esp_wpa2.c +CHIP_CSRCS += esp_wpa3.c +CHIP_CSRCS += esp_wpas_glue.c +CHIP_CSRCS += esp_owe.c +CHIP_CSRCS += esp_scan.c + +VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src$(DELIM)crypto + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)crypto + +CHIP_CSRCS += crypto_mbedtls-bignum.c +CHIP_CSRCS += crypto_mbedtls-ec.c +CHIP_CSRCS += crypto_mbedtls-rsa.c +CHIP_CSRCS += crypto_mbedtls.c +CHIP_CSRCS += tls_mbedtls.c +CHIP_CSRCS += aes-siv.c + +endif diff --git a/arch/risc-v/src/common/espressif/chip.h b/arch/risc-v/src/common/espressif/chip.h new file mode 100644 index 0000000000000..6c16bb48dc49c --- /dev/null +++ b/arch/risc-v/src/common/espressif/chip.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_CHIP_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "esp_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Section for exception handler. */ + +#define EXCEPTION_SECTION .iram1 + +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_CHIP_H */ diff --git a/arch/risc-v/src/espressif/esp_allocateheap.c b/arch/risc-v/src/common/espressif/esp_allocateheap.c similarity index 95% rename from arch/risc-v/src/espressif/esp_allocateheap.c rename to arch/risc-v/src/common/espressif/esp_allocateheap.c index c8383a9b1b6f5..4c3343c199bbb 100644 --- a/arch/risc-v/src/espressif/esp_allocateheap.c +++ b/arch/risc-v/src/common/espressif/esp_allocateheap.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_allocateheap.c + * arch/risc-v/src/common/espressif/esp_allocateheap.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -32,6 +32,7 @@ #include #include +#include "riscv_internal.h" #include "rom/rom_layout.h" /**************************************************************************** @@ -74,13 +75,11 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) * Check boards/risc-v/espressif. */ - extern uint8_t _sheap[]; - board_autoled_on(LED_HEAPALLOCATE); - *heap_start = _sheap; + *heap_start = (void *)g_idle_topstack; *heap_size = (uintptr_t)ets_rom_layout_p->dram0_rtos_reserved_start - - (uintptr_t)_sheap; + g_idle_topstack; } /**************************************************************************** diff --git a/arch/risc-v/src/espressif/esp_config.h b/arch/risc-v/src/common/espressif/esp_config.h similarity index 91% rename from arch/risc-v/src/espressif/esp_config.h rename to arch/risc-v/src/common/espressif/esp_config.h index ac113f83c3a18..7a7477dfc441b 100644 --- a/arch/risc-v/src/espressif/esp_config.h +++ b/arch/risc-v/src/common/espressif/esp_config.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_config.h + * arch/risc-v/src/common/espressif/esp_config.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESPRESSIF_ESP_CONFIG_H -#define __ARCH_RISCV_SRC_ESPRESSIF_ESP_CONFIG_H +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_CONFIG_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_CONFIG_H /**************************************************************************** * Included Files @@ -68,4 +68,4 @@ # define HAVE_UART_DEVICE 1 #endif -#endif /* __ARCH_RISCV_SRC_ESPRESSIF_ESP_CONFIG_H */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_CONFIG_H */ diff --git a/arch/risc-v/src/common/espressif/esp_ets_timer_legacy.c b/arch/risc-v/src/common/espressif/esp_ets_timer_legacy.c new file mode 100644 index 0000000000000..f083778246d00 --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_ets_timer_legacy.c @@ -0,0 +1,263 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_ets_timer_legacy.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this args for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* ets_timer module implements a set of legacy timer APIs which are + * used by the WiFi driver. This is done on top of the esp_hr_timer APIs. + * Applications should not use ets_timer functions, as they may change + * without notice. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +#include "sdkconfig.h" +#include "esp_timer.h" +#include "rom/ets_sys.h" +#include "esp_attr.h" + +#include "espressif/esp_hr_timer.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* We abuse 'timer_arg' field of ETSTimer structure to hold a + * pointer to esp_hr_timer. + */ + +#define ESP_TIMER(p_ets_timer) \ + ((struct esp_hr_timer_s *) (p_ets_timer)->timer_arg) + +/* Override internal name to be compliant with NuttX C Coding Standard */ + +#define ets_timer ETSTimer +#define ets_timer_func ETSTimerFunc + +/* We abuse 'timer_expire' field of ETSTimer structure to hold a magic value + * signifying that the contents of the timer was zeroed out. + */ + +#define TIMER_INITIALIZED_FIELD(p_ets_timer) ((p_ets_timer)->timer_expire) +#define TIMER_INITIALIZED_VAL 0x12121212 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static bool timer_initialized(ets_timer *ptimer); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: timer_initialized + * + * Description: + * This function checks if the given ETS timer is initialized. + * + * Input Parameters: + * ptimer - Pointer to the ETS timer structure. + * + * Returned Value: + * Returns true if the timer is initialized, false otherwise. + * + ****************************************************************************/ + +static bool IRAM_ATTR timer_initialized(ets_timer *ptimer) +{ + return TIMER_INITIALIZED_FIELD(ptimer) == TIMER_INITIALIZED_VAL; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ets_timer_setfn + * + * Description: + * Set timer callback function and argument. + * + * Input Parameters: + * ptimer - Timer struct pointer + * pfunction - Timer callback + * parg - Timer callback argument + * + * Returned Value: + * None + * + ****************************************************************************/ + +void ets_timer_setfn(ets_timer *ptimer, + ets_timer_func *pfunction, + void *parg) +{ + int ret = OK; + + if (!timer_initialized(ptimer)) + { + memset(ptimer, 0, sizeof(*ptimer)); + TIMER_INITIALIZED_FIELD(ptimer) = TIMER_INITIALIZED_VAL; + } + + if (ESP_TIMER(ptimer) == NULL) + { + struct esp_hr_timer_args_s hr_timer_args; + struct esp_hr_timer_s *hr_timers_p; + + hr_timer_args.arg = parg; + hr_timer_args.callback = pfunction; + + ret = esp_hr_timer_create(&hr_timer_args, &hr_timers_p); + + if (ret) + { + tmrerr("Failed to create ets_timer error=%d\n", ret); + } + else + { + ptimer->timer_arg = hr_timers_p; + } + } +} + +/**************************************************************************** + * Name: ets_timer_arm_us + * + * Description: + * Arms an ETS timer. The timer range is from 640 us to 429496 ms. + * + * Input Parameters: + * ptimer - Pointer to the timer structure. + * time_us - Timer value in microseconds. The range is 1 to 429496729. + * repeat_flag - Specifies if the timer is periodically repeated. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR ets_timer_arm_us(ets_timer *ptimer, + uint32_t time_us, + bool repeat_flag) +{ + assert(timer_initialized(ptimer)); + + esp_hr_timer_stop(ESP_TIMER(ptimer)); + + if (!repeat_flag) + { + esp_hr_timer_start(ESP_TIMER(ptimer), time_us, false); + } + else + { + esp_hr_timer_start(ESP_TIMER(ptimer), time_us, true); + } +} + +/**************************************************************************** + * Name: ets_timer_arm + * + * Description: + * Arms an ETS timer. The timer range is from 640 us to 429496 ms. + * + * Input Parameters: + * ptimer - Pointer to the timer structure. + * time_us - Timer value in microseconds. The range is 1 to 429496. + * repeat_flag - Specifies if the timer is periodically repeated. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR ets_timer_arm(ets_timer *ptimer, + uint32_t time_ms, + bool repeat_flag) +{ + uint64_t time_us = 1000LL * (uint64_t) time_ms; + + assert(timer_initialized(ptimer)); + + esp_hr_timer_stop(ESP_TIMER(ptimer)); + + if (!repeat_flag) + { + esp_hr_timer_start(ESP_TIMER(ptimer), time_us, false); + } + else + { + esp_hr_timer_start(ESP_TIMER(ptimer), time_us, true); + } +} + +/**************************************************************************** + * Name: ets_timer_done + * + * Description: + * Unset timer callback and argument to NULL. + * + * Input Parameters: + * ptimer - timer data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +void ets_timer_done(ets_timer *ptimer) +{ + if (timer_initialized(ptimer)) + { + esp_hr_timer_delete(ESP_TIMER(ptimer)); + ptimer->timer_arg = NULL; + TIMER_INITIALIZED_FIELD(ptimer) = 0; + } +} + +/**************************************************************************** + * Name: ets_timer_disarm + * + * Description: + * Disarm an ets timer. + * + * Input Parameters: + * ptimer - timer data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR ets_timer_disarm(ets_timer *ptimer) +{ + if (timer_initialized(ptimer)) + { + esp_hr_timer_stop(ESP_TIMER(ptimer)); + } +} diff --git a/arch/risc-v/src/espressif/esp_gpio.c b/arch/risc-v/src/common/espressif/esp_gpio.c similarity index 99% rename from arch/risc-v/src/espressif/esp_gpio.c rename to arch/risc-v/src/common/espressif/esp_gpio.c index beb0526a937fc..be39e5b1d96ef 100644 --- a/arch/risc-v/src/espressif/esp_gpio.c +++ b/arch/risc-v/src/common/espressif/esp_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_gpio.c + * arch/risc-v/src/common/espressif/esp_gpio.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/espressif/esp_gpio.h b/arch/risc-v/src/common/espressif/esp_gpio.h similarity index 91% rename from arch/risc-v/src/espressif/esp_gpio.h rename to arch/risc-v/src/common/espressif/esp_gpio.h index cac9aae8ca4e1..6c9651e591db1 100644 --- a/arch/risc-v/src/espressif/esp_gpio.h +++ b/arch/risc-v/src/common/espressif/esp_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_gpio.h + * arch/risc-v/src/common/espressif/esp_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESPRESSIF_ESP_GPIO_H -#define __ARCH_RISCV_SRC_ESPRESSIF_ESP_GPIO_H +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_GPIO_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_GPIO_H /**************************************************************************** * Included Files @@ -98,6 +98,24 @@ #define ONLOW 0x04 #define ONHIGH 0x05 +/* Check whether it is a valid GPIO number */ + +#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num >= 0) && \ + (((1ULL << (gpio_num)) & \ + SOC_GPIO_VALID_GPIO_MASK) != 0)) + +/* Check whether it can be a valid GPIO number of output mode */ + +#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) \ + ((gpio_num >= 0) && \ + (((1ULL << (gpio_num)) & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) != 0)) + +/* Check whether it can be a valid digital I/O pad */ + +#define GPIO_IS_VALID_DIGITAL_IO_PAD(gpio_num) \ + ((gpio_num >= 0) && \ + (((1ULL << (gpio_num)) & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK) != 0)) + /**************************************************************************** * Public Types ****************************************************************************/ @@ -298,4 +316,4 @@ void esp_gpioirqdisable(int irq); #undef EXTERN #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESPRESSIF_ESP_GPIO_H */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_GPIO_H */ diff --git a/arch/risc-v/src/espressif/esp_head.S b/arch/risc-v/src/common/espressif/esp_head.S similarity index 92% rename from arch/risc-v/src/espressif/esp_head.S rename to arch/risc-v/src/common/espressif/esp_head.S index 7286186eb30e2..aed416631b299 100644 --- a/arch/risc-v/src/espressif/esp_head.S +++ b/arch/risc-v/src/common/espressif/esp_head.S @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_head.S + * arch/risc-v/src/common/espressif/esp_head.S * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -26,6 +26,7 @@ #include +#include "riscv_internal.h" #include "chip.h" /**************************************************************************** @@ -50,8 +51,9 @@ __start: /* Set stack pointer to the idle thread stack */ - lui sp, %hi(ESP_IDLESTACK_TOP) - addi sp, sp, %lo(ESP_IDLESTACK_TOP) + la sp, _ebss + li t0, SMP_STACK_SIZE + add sp, sp, t0 /* Set gp pointer */ @@ -59,7 +61,7 @@ __start: /* Disable all interrupts (i.e. timer, external) in mstatus */ - csrw mstatus, zero + csrw CSR_MSTATUS, zero .option pop @@ -67,7 +69,7 @@ __start: lui t0, %hi(_vector_table) addi t0, t0, %lo(_vector_table) - csrw mtvec, t0 + csrw CSR_MTVEC, t0 /* Jump to __esp_start */ diff --git a/arch/risc-v/src/espressif/esp_hr_timer.c b/arch/risc-v/src/common/espressif/esp_hr_timer.c similarity index 95% rename from arch/risc-v/src/espressif/esp_hr_timer.c rename to arch/risc-v/src/common/espressif/esp_hr_timer.c index 53e20cfec5546..e3be4daf9df0d 100644 --- a/arch/risc-v/src/espressif/esp_hr_timer.c +++ b/arch/risc-v/src/common/espressif/esp_hr_timer.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_hr_timer.c + * arch/risc-v/src/common/espressif/esp_hr_timer.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -33,6 +33,7 @@ #include #include +#include #include #include #include @@ -96,6 +97,8 @@ static struct esp_hr_timer_context_s g_hr_timer_context = .toutsem = SEM_INITIALIZER(0), }; +static bool g_hr_timer_initialized; + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -117,7 +120,7 @@ static struct esp_hr_timer_context_s g_hr_timer_context = * ****************************************************************************/ -static int esp_hr_timer_thread(int argc, char *argv[]) +IRAM_ATTR static int esp_hr_timer_thread(int argc, char *argv[]) { struct esp_hr_timer_context_s *priv = &g_hr_timer_context; @@ -310,8 +313,8 @@ static int IRAM_ATTR esp_hr_timer_isr(int irq, void *context, void *arg) * ****************************************************************************/ -int esp_hr_timer_create(const struct esp_hr_timer_args_s *args, - struct esp_hr_timer_s **timer_handle) +int IRAM_ATTR esp_hr_timer_create(const struct esp_hr_timer_args_s *args, + struct esp_hr_timer_s **timer_handle) { struct esp_hr_timer_s *timer; @@ -350,9 +353,9 @@ int esp_hr_timer_create(const struct esp_hr_timer_args_s *args, * ****************************************************************************/ -void esp_hr_timer_start(struct esp_hr_timer_s *timer, - uint64_t timeout, - bool repeat) +void IRAM_ATTR esp_hr_timer_start(struct esp_hr_timer_s *timer, + uint64_t timeout, + bool repeat) { struct esp_hr_timer_context_s *priv = &g_hr_timer_context; bool inserted = false; @@ -435,7 +438,7 @@ void esp_hr_timer_start(struct esp_hr_timer_s *timer, * ****************************************************************************/ -void esp_hr_timer_stop(struct esp_hr_timer_s *timer) +void IRAM_ATTR esp_hr_timer_stop(struct esp_hr_timer_s *timer) { struct esp_hr_timer_context_s *priv = &g_hr_timer_context; @@ -490,6 +493,23 @@ void esp_hr_timer_stop(struct esp_hr_timer_s *timer) } } } + else if (timer->state == HR_TIMER_TIMEOUT) + { + /* If the timer is in the timeout list, remove it from the list, + * execute its callback function and set its state to idle. + */ + + DEBUGASSERT(!list_is_empty(&priv->toutlist)); + + list_delete(&timer->list); + timer->state = HR_TIMER_IDLE; + + spin_unlock_irqrestore(&priv->lock, flags); + + timer->callback(timer->arg); + + flags = spin_lock_irqsave(&priv->lock); + } spin_unlock_irqrestore(&priv->lock, flags); } @@ -648,7 +668,6 @@ void IRAM_ATTR esp_hr_timer_calibration(uint64_t time_us) int esp_hr_timer_init(void) { - static bool g_hr_timer_initialized = false; struct esp_hr_timer_context_s *priv; int pid; diff --git a/arch/risc-v/src/espressif/esp_hr_timer.h b/arch/risc-v/src/common/espressif/esp_hr_timer.h similarity index 96% rename from arch/risc-v/src/espressif/esp_hr_timer.h rename to arch/risc-v/src/common/espressif/esp_hr_timer.h index 9c594d756711a..bb48bca7f199f 100644 --- a/arch/risc-v/src/espressif/esp_hr_timer.h +++ b/arch/risc-v/src/common/espressif/esp_hr_timer.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_hr_timer.h + * arch/risc-v/src/common/espressif/esp_hr_timer.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESPRESSIF_ESP_HR_TIMER_H -#define __ARCH_RISCV_SRC_ESPRESSIF_ESP_HR_TIMER_H +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_HR_TIMER_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_HR_TIMER_H /**************************************************************************** * Included Files @@ -229,4 +229,4 @@ int esp_hr_timer_init(void); #endif #undef EXTERN -#endif /* __ARCH_RISCV_SRC_ESPRESSIF_ESP_HR_TIMER_H */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_HR_TIMER_H */ diff --git a/arch/risc-v/src/espressif/esp_idle.c b/arch/risc-v/src/common/espressif/esp_idle.c similarity index 98% rename from arch/risc-v/src/espressif/esp_idle.c rename to arch/risc-v/src/common/espressif/esp_idle.c index b0da0797654d2..29ee677eeb520 100644 --- a/arch/risc-v/src/espressif/esp_idle.c +++ b/arch/risc-v/src/common/espressif/esp_idle.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_idle.c + * arch/risc-v/src/common/espressif/esp_idle.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/espressif/esp_irq.c b/arch/risc-v/src/common/espressif/esp_irq.c similarity index 78% rename from arch/risc-v/src/espressif/esp_irq.c rename to arch/risc-v/src/common/espressif/esp_irq.c index 6b294bd19cc75..749e80494aaa9 100644 --- a/arch/risc-v/src/espressif/esp_irq.c +++ b/arch/risc-v/src/common/espressif/esp_irq.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_irq.c + * arch/risc-v/src/common/espressif/esp_irq.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -37,6 +37,7 @@ #include "esp_gpio.h" #include "esp_irq.h" +#include "esp_rtc_gpio.h" #include "esp_attr.h" #include "esp_bit_defs.h" @@ -68,6 +69,7 @@ #define CPUINT_FREE(cpuint) ((cpuint).val = 0) #define CPUINT_ISENABLED(cpuint) ((cpuint).cpuint_en == 1) #define CPUINT_ISASSIGNED(cpuint) ((cpuint).assigned == 1) +#define CPUINT_ISRESERVED(cpuint) ((cpuint).reserved0 == 1) #define CPUINT_ISFREE(cpuint) (!CPUINT_ISASSIGNED(cpuint)) /* CPU interrupts can be detached from any interrupt source by setting the @@ -113,7 +115,21 @@ static volatile uint8_t g_irq_map[NR_IRQS]; * devices. */ -static uint32_t g_cpuint_freelist = ESP_CPUINT_PERIPHSET; +static uint32_t g_cpuint_freelist = ESP_CPUINT_PERIPHSET & \ + ~ESP_WIRELESS_RESERVE_INT; + +/* This bitmask has an 1 if the int should be disabled + * when the flash is disabled. + */ + +static uint32_t non_iram_int_mask[CONFIG_ESPRESSIF_NUM_CPUS]; + +/* This bitmask has 1 in it if the int was disabled + * using esp_intr_noniram_disable. + */ + +static uint32_t non_iram_int_disabled[CONFIG_ESPRESSIF_NUM_CPUS]; +static bool non_iram_int_disabled_flag[CONFIG_ESPRESSIF_NUM_CPUS]; /**************************************************************************** * Private Functions @@ -140,7 +156,7 @@ static int esp_cpuint_alloc(int irq) { uint32_t bitmask; uint32_t intset; - int cpuint; + int cpuint = ESP_NCPUINTS; /* Check if there are CPU interrupts with the requested properties * available. @@ -187,8 +203,7 @@ static int esp_cpuint_alloc(int irq) DEBUGASSERT(CPUINT_ISFREE(g_cpuint_map[cpuint])); - CPUINT_ASSIGN(g_cpuint_map[cpuint], irq); - g_irq_map[irq] = cpuint; + esp_set_irq(irq, cpuint); return cpuint; } @@ -280,6 +295,15 @@ static void esp_cpuint_initialize(void) void up_irqinitialize(void) { + /* All CPU ints are non-IRAM interrupts at the beginning and should be + * disabled during a SPI flash operation + */ + + for (int i = 0; i < CONFIG_SMP_NCPUS; i++) + { + non_iram_int_mask[i] = UINT32_MAX; + } + /* Indicate that no interrupt sources are assigned to CPU interrupts */ for (int i = 0; i < NR_IRQS; i++) @@ -297,6 +321,10 @@ void up_irqinitialize(void) esp_gpioirqinitialize(); #endif + /* Initialize RTCIO interrupt support */ + + esp_rtcioirqinitialize(); + /* Attach the common interrupt handler */ riscv_exception_attach(); @@ -581,6 +609,126 @@ irqstate_t up_irq_enable(void) /* Read mstatus & set machine interrupt enable (MIE) in mstatus */ - flags = READ_AND_SET_CSR(mstatus, MSTATUS_MIE); + flags = READ_AND_SET_CSR(CSR_MSTATUS, MSTATUS_MIE); return flags; } + +/**************************************************************************** + * Name: esp_intr_noniram_disable + * + * Description: + * Disable interrupts that aren't specifically marked as running from IRAM. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void IRAM_ATTR esp_intr_noniram_disable(void) +{ + uint32_t oldint; + irqstate_t irqstate; + uint32_t cpu; + uint32_t non_iram_ints; + + irqstate = enter_critical_section(); + cpu = esp_cpu_get_core_id(); + non_iram_ints = non_iram_int_mask[cpu]; + + if (non_iram_int_disabled_flag[cpu]) + { + abort(); + } + + non_iram_int_disabled_flag[cpu] = true; + oldint = esp_cpu_intr_get_enabled_mask(); + esp_cpu_intr_disable(non_iram_ints); + + /* Save disabled ints */ + + non_iram_int_disabled[cpu] = oldint & non_iram_ints; + leave_critical_section(irqstate); +} + +/**************************************************************************** + * Name: esp_intr_noniram_enable + * + * Description: + * Enable interrupts that aren't specifically marked as running from IRAM. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void IRAM_ATTR esp_intr_noniram_enable(void) +{ + irqstate_t irqstate; + uint32_t cpu; + int non_iram_ints; + + irqstate = enter_critical_section(); + cpu = esp_cpu_get_core_id(); + non_iram_ints = non_iram_int_disabled[cpu]; + + if (!non_iram_int_disabled_flag[cpu]) + { + abort(); + } + + non_iram_int_disabled_flag[cpu] = false; + esp_cpu_intr_enable(non_iram_ints); + leave_critical_section(irqstate); +} + +/**************************************************************************** + * Name: esp_get_irq + * + * Description: + * This function returns the IRQ associated with a CPU interrupt + * + * Input Parameters: + * cpuint - The CPU interrupt associated to the IRQ + * + * Returned Value: + * The IRQ associated with such CPU interrupt or CPUINT_UNASSIGNED if + * IRQ is not yet assigned to a CPU interrupt. + * + ****************************************************************************/ + +int esp_get_irq(int cpuint) +{ + return CPUINT_GETIRQ(g_cpuint_map[cpuint]); +} + +/**************************************************************************** + * Name: esp_set_irq + * + * Description: + * This function assigns a CPU interrupt to a specific IRQ number. It + * updates the mapping between IRQ numbers and CPU interrupts, allowing + * the system to correctly route hardware interrupts to the appropriate + * handlers. Please note that this function is intended to be used only + * when a CPU interrupt is already assigned to an IRQ number. Otherwise, + * please check esp_setup_irq. + * + * Input Parameters: + * irq - The IRQ number to be associated with the CPU interrupt. + * cpuint - The CPU interrupt to be associated with the IRQ number. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp_set_irq(int irq, int cpuint) +{ + CPUINT_ASSIGN(g_cpuint_map[cpuint], irq); + g_irq_map[irq] = cpuint; +} diff --git a/arch/risc-v/src/common/espressif/esp_irq.h b/arch/risc-v/src/common/espressif/esp_irq.h new file mode 100644 index 0000000000000..648665430e284 --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_irq.h @@ -0,0 +1,222 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_IRQ_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* CPU interrupt trigger types */ + +typedef enum irq_trigger_e +{ + ESP_IRQ_TRIGGER_LEVEL = 0, /* Level-triggered interrupts */ + ESP_IRQ_TRIGGER_EDGE = 1, /* Edge-triggered interrupts */ +} irq_trigger_t; + +/* CPU interrupt priority levels */ + +typedef enum irq_priority_e +{ + ESP_IRQ_PRIORITY_1 = 1, /* Priority Level 1 */ + ESP_IRQ_PRIORITY_2 = 2, /* Priority Level 2 */ + ESP_IRQ_PRIORITY_3 = 3, /* Priority Level 3 */ + ESP_IRQ_PRIORITY_4 = 4, /* Priority Level 4 */ + ESP_IRQ_PRIORITY_5 = 5, /* Priority Level 5 */ + ESP_IRQ_PRIORITY_6 = 6, /* Priority Level 6 */ + ESP_IRQ_PRIORITY_7 = 7, /* Priority Level 7 */ + ESP_IRQ_PRIORITY_8 = 8, /* Priority Level 8 */ + ESP_IRQ_PRIORITY_9 = 9, /* Priority Level 9 */ + ESP_IRQ_PRIORITY_10 = 10, /* Priority Level 10 */ + ESP_IRQ_PRIORITY_11 = 11, /* Priority Level 11 */ + ESP_IRQ_PRIORITY_12 = 12, /* Priority Level 12 */ + ESP_IRQ_PRIORITY_13 = 13, /* Priority Level 13 */ + ESP_IRQ_PRIORITY_14 = 14, /* Priority Level 14 */ + ESP_IRQ_PRIORITY_15 = 15, /* Priority Level 15 */ + ESP_IRQ_PRIORITY_DEFAULT = ESP_IRQ_PRIORITY_1 /* Default Priority */ +} irq_priority_t; + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_route_intr + * + * Description: + * Assign an interrupt source to a pre-allocated CPU interrupt. + * + * Input Parameters: + * source - Interrupt source (see irq.h) to be assigned to a CPU + * interrupt. + * cpuint - Pre-allocated CPU interrupt to which the interrupt + * source will be assigned. + * priority - Interrupt priority. + * type - Interrupt trigger type. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_route_intr(int source, int cpuint, irq_priority_t priority, + irq_trigger_t type); + +/**************************************************************************** + * Name: esp_setup_irq + * + * Description: + * This function sets up the IRQ. It allocates a CPU interrupt of the given + * priority and type and attaches it to a given interrupt source. + * + * Input Parameters: + * source - The interrupt source from irq.h to be assigned to + * a CPU interrupt. + * priority - Interrupt priority. + * type - Interrupt trigger type. + * + * Returned Value: + * Allocated CPU interrupt. + * + ****************************************************************************/ + +int esp_setup_irq(int source, irq_priority_t priority, irq_trigger_t type); + +/**************************************************************************** + * Name: esp_teardown_irq + * + * Description: + * This function undoes the operations done by esp_setup_irq. + * It detaches an interrupt source from a CPU interrupt and frees the + * CPU interrupt. + * + * Input Parameters: + * source - The interrupt source from irq.h to be detached from the + * CPU interrupt. + * cpuint - The CPU interrupt from which the interrupt source will + * be detached. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_teardown_irq(int source, int cpuint); + +/**************************************************************************** + * Name: esp_intr_noniram_disable + * + * Description: + * Disable interrupts that aren't specifically marked as running from IRAM. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_intr_noniram_disable(void); + +/**************************************************************************** + * Name: esp_intr_noniram_enable + * + * Description: + * Enable interrupts that aren't specifically marked as running from IRAM. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_intr_noniram_enable(void); + +/**************************************************************************** + * Name: esp_get_irq + * + * Description: + * This function returns the IRQ associated with a CPU interrupt + * + * Input Parameters: + * cpuint - The CPU interrupt associated to the IRQ + * + * Returned Value: + * The IRQ associated with such CPU interrupt or CPUINT_UNASSIGNED if + * IRQ is not yet assigned to a CPU interrupt. + * + ****************************************************************************/ + +int esp_get_irq(int cpuint); + +/**************************************************************************** + * Name: esp_set_irq + * + * Description: + * This function assigns a CPU interrupt to a specific IRQ number. It + * updates the mapping between IRQ numbers and CPU interrupts, allowing + * the system to correctly route hardware interrupts to the appropriate + * handlers. Please note that this function is intended to be used only + * when a CPU interrupt is already assigned to an IRQ number. Otherwise, + * please check esp_setup_irq. + * + * Input Parameters: + * irq - The IRQ number to be associated with the CPU interrupt. + * cpuint - The CPU interrupt to be associated with the IRQ number. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp_set_irq(int irq, int cpuint); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_IRQ_H */ diff --git a/arch/risc-v/src/espressif/esp_ledc.c b/arch/risc-v/src/common/espressif/esp_ledc.c similarity index 99% rename from arch/risc-v/src/espressif/esp_ledc.c rename to arch/risc-v/src/common/espressif/esp_ledc.c index 30f868ee74363..e0b43b756dbd4 100644 --- a/arch/risc-v/src/espressif/esp_ledc.c +++ b/arch/risc-v/src/common/espressif/esp_ledc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_ledc.c + * arch/risc-v/src/common/espressif/esp_ledc.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/espressif/esp_ledc.h b/arch/risc-v/src/common/espressif/esp_ledc.h similarity index 90% rename from arch/risc-v/src/espressif/esp_ledc.h rename to arch/risc-v/src/common/espressif/esp_ledc.h index c5153c8c994c3..484a869ca8098 100644 --- a/arch/risc-v/src/espressif/esp_ledc.h +++ b/arch/risc-v/src/common/espressif/esp_ledc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_ledc.h + * arch/risc-v/src/common/espressif/esp_ledc.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESPRESSIF_ESP_LEDC_H -#define __ARCH_RISCV_SRC_ESPRESSIF_ESP_LEDC_H +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_LEDC_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_LEDC_H /**************************************************************************** * Included Files @@ -49,4 +49,4 @@ struct pwm_lowerhalf_s *esp_ledc_init(int timer); -#endif /* __ARCH_RISCV_SRC_ESPRESSIF_ESP_LEDC_H */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_LEDC_H */ diff --git a/arch/risc-v/src/espressif/esp_libc_stubs.c b/arch/risc-v/src/common/espressif/esp_libc_stubs.c similarity index 87% rename from arch/risc-v/src/espressif/esp_libc_stubs.c rename to arch/risc-v/src/common/espressif/esp_libc_stubs.c index da6eddf4c76c0..f7cb7afca3e9b 100644 --- a/arch/risc-v/src/espressif/esp_libc_stubs.c +++ b/arch/risc-v/src/common/espressif/esp_libc_stubs.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_libc_stubs.c + * arch/risc-v/src/common/espressif/esp_libc_stubs.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -45,8 +45,6 @@ * Pre-processor Definitions ****************************************************************************/ -#define _lock_t int - #define ROM_MUTEX_MAGIC 0xbb10c433 /**************************************************************************** @@ -180,64 +178,108 @@ void _raise_r(struct _reent *r) void _lock_init(_lock_t *lock) { - nxmutex_init(&g_nxlock_common); - nxsem_get_value(&g_nxlock_common.sem, lock); + mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t)); + + nxmutex_init(mutex); + + *lock = (_lock_t)mutex; } void _lock_init_recursive(_lock_t *lock) { - nxmutex_init(&g_nxlock_recursive); - nxsem_get_value(&g_nxlock_recursive.sem, lock); + rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t)); + + nxrmutex_init(rmutex); + + *lock = (_lock_t)rmutex; } void _lock_close(_lock_t *lock) { - nxmutex_destroy(&g_nxlock_common); + mutex_t *mutex = (mutex_t *)(*lock); + + nxmutex_destroy(mutex); + kmm_free(*lock); *lock = 0; } void _lock_close_recursive(_lock_t *lock) { - nxmutex_destroy(&g_nxlock_recursive); + rmutex_t *rmutex = (rmutex_t *)(*lock); + + nxrmutex_destroy(rmutex); + kmm_free(*lock); *lock = 0; } void _lock_acquire(_lock_t *lock) { - nxmutex_lock(&g_nxlock_common); - nxsem_get_value(&g_nxlock_common.sem, lock); + if (*lock == NULL) + { + mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t)); + + nxmutex_init(mutex); + + *lock = (_lock_t)mutex; + } + + nxmutex_lock((mutex_t *)(*lock)); } void _lock_acquire_recursive(_lock_t *lock) { - nxmutex_lock(&g_nxlock_recursive); - nxsem_get_value(&g_nxlock_recursive.sem, lock); + if (*lock == NULL) + { + rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t)); + + nxrmutex_init(rmutex); + + *lock = (_lock_t)rmutex; + } + + nxrmutex_lock((rmutex_t *)(*lock)); } int _lock_try_acquire(_lock_t *lock) { - nxmutex_trylock(&g_nxlock_common); - nxsem_get_value(&g_nxlock_common.sem, lock); - return 0; + if (*lock == NULL) + { + mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t)); + + nxmutex_init(mutex); + + *lock = (_lock_t)mutex; + } + + return nxmutex_trylock((mutex_t *)(*lock)); } int _lock_try_acquire_recursive(_lock_t *lock) { - nxmutex_trylock(&g_nxlock_recursive); - nxsem_get_value(&g_nxlock_recursive.sem, lock); - return 0; + if (*lock == NULL) + { + rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t)); + + nxrmutex_init(rmutex); + + *lock = (_lock_t)rmutex; + } + + return nxrmutex_trylock((rmutex_t *)(*lock)); } void _lock_release(_lock_t *lock) { - nxmutex_unlock(&g_nxlock_common); - nxsem_get_value(&g_nxlock_common.sem, lock); + mutex_t *mutex = (mutex_t *)(*lock); + + nxmutex_unlock(mutex); } void _lock_release_recursive(_lock_t *lock) { - nxmutex_unlock(&g_nxlock_recursive); - nxsem_get_value(&g_nxlock_recursive.sem, lock); + rmutex_t *rmutex = (rmutex_t *)(*lock); + + nxrmutex_unlock(rmutex); } #if ESP_ROM_HAS_RETARGETABLE_LOCKING diff --git a/arch/risc-v/src/espressif/esp_libc_stubs.h b/arch/risc-v/src/common/espressif/esp_libc_stubs.h similarity index 88% rename from arch/risc-v/src/espressif/esp_libc_stubs.h rename to arch/risc-v/src/common/espressif/esp_libc_stubs.h index 9ed6084e1ec60..c26de3a6681f3 100644 --- a/arch/risc-v/src/espressif/esp_libc_stubs.h +++ b/arch/risc-v/src/common/espressif/esp_libc_stubs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_libc_stubs.h + * arch/risc-v/src/common/espressif/esp_libc_stubs.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESPRESSIF_ESP_LIBC_STUBS_H -#define __ARCH_RISCV_SRC_ESPRESSIF_ESP_LIBC_STUBS_H +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_LIBC_STUBS_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_LIBC_STUBS_H /**************************************************************************** * Included Files @@ -48,4 +48,4 @@ void esp_setup_syscall_table(void); -#endif /* __ARCH_RISCV_SRC_ESPRESSIF_ESP_LIBC_STUBS_H */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_LIBC_STUBS_H */ diff --git a/arch/risc-v/src/espressif/esp_lowputc.c b/arch/risc-v/src/common/espressif/esp_lowputc.c similarity index 98% rename from arch/risc-v/src/espressif/esp_lowputc.c rename to arch/risc-v/src/common/espressif/esp_lowputc.c index dca8f2b92f9ef..e630a70b83d7e 100644 --- a/arch/risc-v/src/espressif/esp_lowputc.c +++ b/arch/risc-v/src/common/espressif/esp_lowputc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_lowputc.c + * arch/risc-v/src/common/espressif/esp_lowputc.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -207,7 +207,7 @@ void esp_lowputc_disable_all_uart_int(const struct esp_uart_s *priv, { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (current_status != NULL) { @@ -224,7 +224,7 @@ void esp_lowputc_disable_all_uart_int(const struct esp_uart_s *priv, uart_hal_clr_intsts_mask(priv->hal, UINT32_MAX); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -263,12 +263,12 @@ void esp_lowputc_config_pins(const struct esp_uart_s *priv) { /* Configure the pins */ - esp_configgpio(priv->txpin, OUTPUT); - esp_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0); - esp_configgpio(priv->rxpin, INPUT | PULLUP); esp_gpio_matrix_in(priv->rxpin, priv->rxsig, 0); + esp_configgpio(priv->txpin, OUTPUT); + esp_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0); + #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { diff --git a/arch/risc-v/src/espressif/esp_lowputc.h b/arch/risc-v/src/common/espressif/esp_lowputc.h similarity index 96% rename from arch/risc-v/src/espressif/esp_lowputc.h rename to arch/risc-v/src/common/espressif/esp_lowputc.h index 39d99cd65486b..41adb3c737227 100644 --- a/arch/risc-v/src/espressif/esp_lowputc.h +++ b/arch/risc-v/src/common/espressif/esp_lowputc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_lowputc.h + * arch/risc-v/src/common/espressif/esp_lowputc.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESPRESSIF_ESP_LOWPUTC_H -#define __ARCH_RISCV_SRC_ESPRESSIF_ESP_LOWPUTC_H +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_LOWPUTC_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_LOWPUTC_H /**************************************************************************** * Included Files @@ -183,4 +183,4 @@ void esp_lowputc_restore_pins(const struct esp_uart_s *priv); void esp_lowsetup(void); -#endif /* __ARCH_RISCV_SRC_ESPRESSIF_ESP_LOWPUTC_H */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_LOWPUTC_H */ diff --git a/arch/risc-v/src/espressif/esp_memorymap.h b/arch/risc-v/src/common/espressif/esp_memorymap.h similarity index 75% rename from arch/risc-v/src/espressif/esp_memorymap.h rename to arch/risc-v/src/common/espressif/esp_memorymap.h index d30ed4b589344..0a34a43ee2492 100644 --- a/arch/risc-v/src/espressif/esp_memorymap.h +++ b/arch/risc-v/src/common/espressif/esp_memorymap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_memorymap.h + * arch/risc-v/src/common/espressif/esp_memorymap.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESPRESSIF_ESP_MEMORYMAP_H -#define __ARCH_RISCV_SRC_ESPRESSIF_ESP_MEMORYMAP_H +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_MEMORYMAP_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_MEMORYMAP_H /**************************************************************************** * Included Files @@ -27,18 +27,10 @@ #include +#include "riscv_common_memorymap.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Idle thread stack starts from _ebss */ - -#ifndef __ASSEMBLY__ -#define ESP_IDLESTACK_BASE (uint32_t)&g_idlestack -#else -#define ESP_IDLESTACK_BASE g_idlestack -#endif - -#define ESP_IDLESTACK_TOP (ESP_IDLESTACK_BASE + CONFIG_IDLETHREAD_STACKSIZE) - -#endif /* __ARCH_RISCV_SRC_ESPRESSIF_ESP_MEMORYMAP_H */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_MEMORYMAP_H */ diff --git a/arch/risc-v/src/espressif/esp_oneshot.c b/arch/risc-v/src/common/espressif/esp_oneshot.c similarity index 99% rename from arch/risc-v/src/espressif/esp_oneshot.c rename to arch/risc-v/src/common/espressif/esp_oneshot.c index fdd0e3bac6618..81972faba4b27 100644 --- a/arch/risc-v/src/espressif/esp_oneshot.c +++ b/arch/risc-v/src/common/espressif/esp_oneshot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_oneshot.c + * arch/risc-v/src/common/espressif/esp_oneshot.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/espressif/esp_oneshot.h b/arch/risc-v/src/common/espressif/esp_oneshot.h similarity index 88% rename from arch/risc-v/src/espressif/esp_oneshot.h rename to arch/risc-v/src/common/espressif/esp_oneshot.h index a42cdce1bedaa..61db61ea07815 100644 --- a/arch/risc-v/src/espressif/esp_oneshot.h +++ b/arch/risc-v/src/common/espressif/esp_oneshot.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_oneshot.h + * arch/risc-v/src/common/espressif/esp_oneshot.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESPRESSIF_ESP_ONESHOT_H -#define __ARCH_RISCV_SRC_ESPRESSIF_ESP_ONESHOT_H +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_ONESHOT_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_ONESHOT_H /**************************************************************************** * Included Files @@ -48,4 +48,4 @@ int esp_oneshot_initialize(void); -#endif /* __ARCH_RISCV_SRC_ESPRESSIF_ESP_ONESHOT_H */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_ONESHOT_H */ diff --git a/arch/risc-v/src/espressif/esp_random.c b/arch/risc-v/src/common/espressif/esp_random.c similarity index 98% rename from arch/risc-v/src/espressif/esp_random.c rename to arch/risc-v/src/common/espressif/esp_random.c index e2290b770effd..261b7238ec8b5 100644 --- a/arch/risc-v/src/espressif/esp_random.c +++ b/arch/risc-v/src/common/espressif/esp_random.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_random.c + * arch/risc-v/src/common/espressif/esp_random.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/common/espressif/esp_rmt.c b/arch/risc-v/src/common/espressif/esp_rmt.c new file mode 100644 index 0000000000000..2502c5d9e8c8b --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_rmt.c @@ -0,0 +1,1940 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_rmt.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "esp_gpio.h" +#include "esp_irq.h" + +#include "esp_attr.h" +#include "hal/gpio_types.h" +#include "hal/rmt_hal.h" +#include "hal/rmt_ll.h" +#include "periph_ctrl.h" +#include "soc/gpio_sig_map.h" +#include "soc/rmt_periph.h" +#include "soc/soc_caps.h" +#include "esp_clk_tree.h" + +#include "esp_rmt.h" + +#ifdef CONFIG_ESP_RMT + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RMT_RX_CHANNEL_ENCODING_START \ + (SOC_RMT_CHANNELS_PER_GROUP-SOC_RMT_TX_CANDIDATES_PER_GROUP) +#define RMT_TX_CHANNEL_ENCODING_END (SOC_RMT_TX_CANDIDATES_PER_GROUP-1) + +#define RMT_IS_RX_CHANNEL(channel) \ + ((channel) >= RMT_RX_CHANNEL_ENCODING_START) +#define RMT_IS_TX_CHANNEL(channel) \ + ((channel) <= RMT_TX_CHANNEL_ENCODING_END) +#define RMT_DECODE_RX_CHANNEL(encode_chan) \ + ((encode_chan - RMT_RX_CHANNEL_ENCODING_START)) +#define RMT_ENCODE_RX_CHANNEL(decode_chan) \ + ((decode_chan + RMT_RX_CHANNEL_ENCODING_START)) + +/* Default configuration for TX channel */ + +#define RMT_DEFAULT_CONFIG_TX(gpio, channel_id) \ + { \ + .rmt_mode = RMT_MODE_TX, \ + .channel = channel_id, \ + .gpio_num = gpio, \ + .clk_div = RMT_DEFAULT_CLK_DIV, \ + .mem_block_num = 1, \ + .flags = 0, \ + .tx_config = { \ + .carrier_freq_hz = 38000, \ + .carrier_level = RMT_CARRIER_LEVEL_HIGH, \ + .idle_level = RMT_IDLE_LEVEL_LOW, \ + .carrier_duty_percent = 33, \ + .loop_count = 0, \ + .carrier_en = false, \ + .loop_en = false, \ + .idle_output_en = true, \ + } \ + } + +/* Default configuration for RX channel */ + +#define RMT_DEFAULT_CONFIG_RX(gpio, channel_id) \ + { \ + .rmt_mode = RMT_MODE_RX, \ + .channel = channel_id, \ + .gpio_num = gpio, \ + .clk_div = RMT_DEFAULT_CLK_DIV, \ + .mem_block_num = 1, \ + .flags = 0, \ + .rx_config = { \ + .idle_threshold = 12000, \ + .filter_ticks_thresh = 100, \ + .filter_en = true, \ + } \ + } + +#define rmt_item32_t rmt_symbol_word_t + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* RMT channel ID */ + +enum rmt_channel_e +{ + RMT_CHANNEL_0, /* RMT channel number 0 */ + RMT_CHANNEL_1, /* RMT channel number 1 */ + RMT_CHANNEL_2, /* RMT channel number 2 */ + RMT_CHANNEL_3, /* RMT channel number 3 */ +#if SOC_RMT_CHANNELS_PER_GROUP > 4 + RMT_CHANNEL_4, /* RMT channel number 4 */ + RMT_CHANNEL_5, /* RMT channel number 5 */ + RMT_CHANNEL_6, /* RMT channel number 6 */ + RMT_CHANNEL_7, /* RMT channel number 7 */ +#endif + RMT_CHANNEL_MAX /* Number of RMT channels */ +}; + +typedef enum rmt_channel_e rmt_channel_t; + +/* RMT Channel Working Mode (TX or RX) */ + +enum rmt_mode_e +{ + RMT_MODE_TX, /* RMT TX mode */ + RMT_MODE_RX, /* RMT RX mode */ + RMT_MODE_MAX +}; + +typedef enum rmt_mode_e rmt_mode_t; + +/* RMT Idle Level */ + +enum rmt_idle_level_e +{ + RMT_IDLE_LEVEL_LOW, /* RMT TX idle level: low Level */ + RMT_IDLE_LEVEL_HIGH, /* RMT TX idle level: high Level */ + RMT_IDLE_LEVEL_MAX, +}; + +typedef enum rmt_idle_level_e rmt_idle_level_t; + +/* RMT Carrier Level */ + +enum rmt_carrier_level_e +{ + RMT_CARRIER_LEVEL_LOW, /* RMT carrier wave is modulated for low Level output */ + RMT_CARRIER_LEVEL_HIGH, /* RMT carrier wave is modulated for high Level output */ + RMT_CARRIER_LEVEL_MAX +}; + +typedef enum rmt_carrier_level_e rmt_carrier_level_t; + +/* RMT Channel Status */ + +enum rmt_channel_status_e +{ + RMT_CHANNEL_UNINIT, /* RMT channel uninitialized */ + RMT_CHANNEL_IDLE, /* RMT channel status idle */ + RMT_CHANNEL_BUSY, /* RMT channel status busy */ +}; + +typedef enum rmt_channel_status_e rmt_channel_status_t; + +/* RMT hardware memory layout */ + +struct rmt_channel_data_s +{ + volatile rmt_item32_t data32[SOC_RMT_MEM_WORDS_PER_CHANNEL]; +}; + +struct rmt_mem_s +{ + struct rmt_channel_data_s chan[SOC_RMT_CHANNELS_PER_GROUP]; +}; + +typedef struct rmt_mem_s rmt_mem_t; + +struct rmt_dev_common_s +{ + rmt_hal_context_t hal; /* HAL context */ + rmutex_t rmt_driver_isr_lock; + + /* Mutex lock for protecting concurrent register/unregister of the RMT + * channels' ISR. + */ + + spinlock_t rmt_spinlock; + + /* Bitmask of installed drivers' channels, used to protect concurrent + * register/unregister of the RMT channels' ISR. + */ + + uint8_t rmt_driver_channels; + bool rmt_module_enabled; + + /* Bitmap of channels already added in the synchronous group */ + + uint32_t synchro_channel_mask; +}; + +struct rmt_dev_lowerhalf_s +{ + /* The following block is part of the upper-half device struct */ + + FAR const struct rmt_ops_s *ops; + FAR struct circbuf_s *circbuf; + sem_t *recvsem; + int minor; + + /* The following is private to the ESP32 RMT driver */ + + rmt_mode_t mode; + struct rmt_dev_common_s *common; /* RMT peripheral common parameters */ +}; + +struct rmt_obj_s +{ + size_t tx_offset; + size_t tx_len_rem; + size_t tx_sub_len; + bool wait_done; /* Mark whether wait tx done */ + bool loop_autostop; /* Mark whether loop auto-stop is enabled */ + rmt_channel_t channel; + const rmt_item32_t *tx_data; + sem_t tx_sem; +#ifdef CONFIG_SPIRAM_USE_MALLOC + int intr_alloc_flags; + sem_t tx_sem_buffer; +#endif + rmt_item32_t *tx_buf; + struct circbuf_s rx_buf; + sem_t rx_sem; +#ifdef SOC_RMT_SUPPORT_RX_PINGPONG + rmt_item32_t *rx_item_buf; + uint32_t rx_item_buf_size; + uint32_t rx_item_len; + int rx_item_start_idx; +#endif + void *tx_context; + size_t sample_size_remain; + const uint8_t *sample_cur; +}; + +typedef struct rmt_obj_s rmt_obj_t; + +/* Data struct of RMT TX configure parameters */ + +struct rmt_tx_config_s +{ + uint32_t carrier_freq_hz; /* RMT carrier frequency */ + rmt_carrier_level_t carrier_level; /* Level of the RMT output, when the carrier is applied */ + rmt_idle_level_t idle_level; /* RMT idle level */ + uint8_t carrier_duty_percent; /* RMT carrier duty (%) */ + uint32_t loop_count; /* Maximum loop count, only take effect for chips that is capable of `SOC_RMT_SUPPORT_TX_LOOP_COUNT` */ + bool carrier_en; /* RMT carrier enable */ + bool loop_en; /* Enable sending RMT items in a loop */ + bool idle_output_en; /* RMT idle level output enable */ +}; + +/* Data struct of RMT RX configure parameters */ + +struct rmt_rx_config_s +{ + uint16_t idle_threshold; /* RMT RX idle threshold */ + uint8_t filter_ticks_thresh; /* RMT filter tick number */ + bool filter_en; /* RMT receiver filter enable */ +#if SOC_RMT_SUPPORT_RX_DEMODULATION + bool rm_carrier; /* RMT receiver remove carrier enable */ + uint32_t carrier_freq_hz; /* RMT carrier frequency */ + uint8_t carrier_duty_percent; /* RMT carrier duty (%) */ + rmt_carrier_level_t carrier_level; /* The level to remove the carrier */ +#endif +}; + +struct rmt_channel_config_s +{ + rmt_mode_t rmt_mode; /* RMT mode: transmitter or receiver */ + rmt_channel_t channel; /* RMT channel */ + int gpio_num; /* RMT GPIO number */ + uint8_t clk_div; /* RMT channel counter divider */ + uint8_t mem_block_num; /* RMT memory block number */ + uint32_t flags; /* RMT channel extra configurations, OR'd with RMT_CHANNEL_FLAGS_[*] */ + union + { + struct rmt_tx_config_s tx_config; /* RMT TX parameter */ + struct rmt_rx_config_s rx_config; /* RMT RX parameter */ + }; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void rmt_module_enable(void); +static int rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst); +static int rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst); +static int rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en); +static int rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, + uint16_t evt_thresh); +static int rmt_set_gpio(rmt_channel_t channel, rmt_mode_t mode, + gpio_num_t gpio_num, bool invert_signal); +static bool rmt_is_channel_number_valid(rmt_channel_t channel, uint8_t mode); +static int rmt_internal_config(rmt_dev_t *dev, + const struct rmt_channel_config_s *rmt_param); +static int rmt_config(const struct rmt_channel_config_s *rmt_param); +static void rmt_fill_memory(rmt_channel_t channel, const rmt_item32_t *item, + uint16_t item_num, uint16_t mem_offset); +static int rmt_isr_register(int (*fn)(int, void *, void *), void *arg, + int intr_alloc_flags); +static int rmt_driver_isr_default(int irq, void *context, void *arg); +static int rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, + int intr_alloc_flags); +static int rmt_write_items(rmt_channel_t channel, + const rmt_item32_t *rmt_item, + int item_num, + bool wait_tx_done); +static ssize_t esp_rmt_read(struct rmt_dev_s *dev, char *buffer, + size_t buflen); +static ssize_t esp_rmt_write(FAR struct rmt_dev_s *dev, + FAR const char *buffer, + size_t buflen); +static struct rmt_dev_s + *esp_rmtinitialize(struct rmt_channel_config_s config); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct rmt_ops_s g_rmtops = +{ + .read = esp_rmt_read, + .write = esp_rmt_write, +}; + +static struct rmt_dev_common_s g_rmtdev_common = +{ + .hal.regs = &RMT, + .rmt_driver_isr_lock = NXRMUTEX_INITIALIZER, + .rmt_driver_channels = 0, + .rmt_module_enabled = false, + .synchro_channel_mask = 0 +}; + +static struct rmt_obj_s *p_rmt_obj[RMT_CHANNEL_MAX]; + +#ifdef CONFIG_RMT_LOOP_TEST_MODE +static rmt_channel_t g_tx_channel = RMT_CHANNEL_MAX; +static rmt_channel_t g_rx_channel = RMT_CHANNEL_MAX; +#endif + +#if SOC_RMT_CHANNEL_CLK_INDEPENDENT +uint32_t g_rmt_source_clock_hz[RMT_CHANNEL_MAX]; +#else +uint32_t g_rmt_source_clock_hz; +#endif + +/* RMTMEM address is declared in .peripherals.ld */ + +extern rmt_mem_t RMTMEM; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rmt_module_enable + * + * Description: + * This function enables the RMT (Remote Control) module if it's not + * already enabled. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void rmt_module_enable(void) +{ + irqstate_t flags; + + flags = spin_lock_irqsave(g_rmtdev_common.rmt_spinlock); + + if (g_rmtdev_common.rmt_module_enabled == false) + { + periph_module_reset(rmt_periph_signals.groups[0].module); + periph_module_enable(rmt_periph_signals.groups[0].module); + g_rmtdev_common.rmt_module_enabled = true; + } + + spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); +} + +/**************************************************************************** + * Name: rmt_set_rx_thr_intr_en + * + * Description: + * This function enables or disables the RMT RX threshold interrupt. When + * the number of received items reaches the threshold, an interrupt is + * triggered if this feature is enabled. + * + * Input Parameters: + * channel - The RMT channel. + * en - Enable (true) or disable (false) the RX threshold int. + * evt_thresh - The number of received items that triggers the interrupt. + * + * Returned Value: + * Returns 0 on success; a negated errno value is returned on any failure. + * + ****************************************************************************/ + +#ifdef SOC_RMT_SUPPORT_RX_PINGPONG +static int rmt_set_rx_thr_intr_en(rmt_channel_t channel, bool en, + uint16_t evt_thresh) +{ + irqstate_t flags; + uint32_t mask; + + DEBUGASSERT(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX); + + if (en) + { + uint32_t item_block_len = + rmt_ll_rx_get_mem_blocks(g_rmtdev_common.hal.regs, + RMT_DECODE_RX_CHANNEL(channel)) * RMT_MEM_ITEM_NUM; + + if (evt_thresh >= item_block_len) + { + rmterr("Invalid threshold value %d\n", evt_thresh); + return -EINVAL; + } + + flags = spin_lock_irqsave(g_rmtdev_common.rmt_spinlock); + rmt_ll_rx_set_limit(g_rmtdev_common.hal.regs, + RMT_DECODE_RX_CHANNEL(channel), evt_thresh); + mask = RMT_LL_EVENT_RX_THRES(RMT_DECODE_RX_CHANNEL(channel)); + rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, mask, true); + spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + } + else + { + flags = spin_lock_irqsave(g_rmtdev_common.rmt_spinlock); + mask = RMT_LL_EVENT_RX_THRES(RMT_DECODE_RX_CHANNEL(channel)); + rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, mask, false); + spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: rmt_rx_start + * + * Description: + * This function starts the RMT module in receiving mode for a specific + * channel. + * + * Input Parameters: + * channel - The RMT peripheral channel number. + * rx_idx_rst - If true, the RX index for the channel is reset, which means + * the receiving process will start from the beginning of the + * RMT memory block. + * + * Returned Value: + * Returns OK on successful start of the RMT module in receiving mode; a + * negated errno value is returned on any failure. + * + ****************************************************************************/ + +static int rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst) +{ + irqstate_t flags; + rmt_channel_t ch = RMT_DECODE_RX_CHANNEL(channel); +#ifdef SOC_RMT_SUPPORT_RX_PINGPONG + const uint32_t item_block_len = + rmt_ll_rx_get_mem_blocks(g_rmtdev_common.hal.regs, ch) * + RMT_MEM_ITEM_NUM; +#endif + + DEBUGASSERT(RMT_IS_RX_CHANNEL(channel)); + + flags = spin_lock_irqsave(g_rmtdev_common.rmt_spinlock); + + rmt_ll_rx_enable(g_rmtdev_common.hal.regs, ch, false); + if (rx_idx_rst) + { + rmt_ll_rx_reset_pointer(g_rmtdev_common.hal.regs, ch); + } + + rmt_ll_clear_interrupt_status(g_rmtdev_common.hal.regs, + RMT_LL_EVENT_RX_DONE(ch)); + rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, + RMT_LL_EVENT_RX_DONE(ch), true); + +#ifdef SOC_RMT_SUPPORT_RX_PINGPONG + p_rmt_obj[channel]->rx_item_start_idx = 0; + p_rmt_obj[channel]->rx_item_len = 0; + rmt_set_rx_thr_intr_en(channel, true, item_block_len / 2); +#endif + + rmt_ll_rx_enable(g_rmtdev_common.hal.regs, ch, true); + + spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + + return OK; +} + +/**************************************************************************** + * Name: rmt_tx_start + * + * Description: + * This function starts sending RMT items from the specific channel. + * + * Input Parameters: + * channel - The RMT peripheral channel number. + * tx_idx_rst - Set it true to reset memory index for TX. + * + * Returned Value: + * Returns OK on successful start of transmission. + * + ****************************************************************************/ + +static int rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst) +{ + irqstate_t flags; + + DEBUGASSERT(RMT_IS_TX_CHANNEL(channel)); + + flags = spin_lock_irqsave(g_rmtdev_common.rmt_spinlock); + if (tx_idx_rst) + { + rmt_ll_tx_reset_pointer(g_rmtdev_common.hal.regs, channel); + } + + rmt_ll_clear_interrupt_status(g_rmtdev_common.hal.regs, + RMT_LL_EVENT_TX_DONE(channel)); + + /* Enable tx end interrupt in non-loop mode */ + + if (!rmt_ll_tx_is_loop_enabled(g_rmtdev_common.hal.regs, channel)) + { + rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, + RMT_LL_EVENT_TX_DONE(channel), true); + } + else + { +#if SOC_RMT_SUPPORT_TX_LOOP_COUNT + rmt_ll_tx_reset_loop_count(g_rmtdev_common.hal.regs, channel); + rmt_ll_tx_enable_loop_count(g_rmtdev_common.hal.regs, channel, true); + rmt_ll_clear_interrupt_status(g_rmtdev_common.hal.regs, + RMT_LL_EVENT_TX_LOOP_END(channel)); + rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, + RMT_LL_EVENT_TX_LOOP_END(channel), true); +#endif + } + + rmt_ll_tx_start(g_rmtdev_common.hal.regs, channel); + spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + + return OK; +} + +/**************************************************************************** + * Name: rmt_set_tx_loop_mode + * + * Description: + * This function enables or disables the loop mode for RMT transmission on + * the specified channel. The loop mode, when enabled, allows the RMT + * transmitter to continuously send items. + * + * Input Parameters: + * channel - The RMT peripheral channel number. + * loop_en - A boolean indicating whether to enable (true) or disable + * (false) the loop mode. + * + * Returned Value: + * Returns OK on successful setting of the loop mode. + * + ****************************************************************************/ + +static int rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en) +{ + irqstate_t flags; + + DEBUGASSERT(RMT_IS_TX_CHANNEL(channel)); + + flags = spin_lock_irqsave(g_rmtdev_common.rmt_spinlock); + rmt_ll_tx_enable_loop(g_rmtdev_common.hal.regs, channel, loop_en); + spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + + return OK; +} + +/**************************************************************************** + * Name: rmt_set_tx_thr_intr_en + * + * Description: + * This function enables or disables the RMT TX threshold interrupt for the + * specified channel. The threshold is set to trigger an interrupt when the + * number of transmitted items reaches the specified value. + * + * Input Parameters: + * channel - The RMT peripheral channel number. + * en - A boolean indicating whether to enable (true) or disable + * (false) the TX threshold interrupt. + * evt_thresh - The number of transmitted items at which to trigger the + * interrupt. + * + * Returned Value: + * Returns OK on successful setting of the interrupt. + * + ****************************************************************************/ + +static int rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, + uint16_t evt_thresh) +{ + irqstate_t flags; + + DEBUGASSERT(RMT_IS_TX_CHANNEL(channel)); + + if (en) + { + uint32_t item_block_len = + rmt_ll_tx_get_mem_blocks(g_rmtdev_common.hal.regs, channel) * \ + RMT_MEM_ITEM_NUM; + + DEBUGASSERT(evt_thresh <= item_block_len); + + flags = spin_lock_irqsave(g_rmtdev_common.rmt_spinlock); + rmt_ll_tx_set_limit(g_rmtdev_common.hal.regs, channel, evt_thresh); + rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, + RMT_LL_EVENT_TX_THRES(channel), true); + spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + } + else + { + flags = spin_lock_irqsave(g_rmtdev_common.rmt_spinlock); + rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, + RMT_LL_EVENT_TX_THRES(channel), false); + spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + } + + return OK; +} + +/**************************************************************************** + * Name: rmt_set_gpio + * + * Description: + * This function configures the GPIO for the specified RMT (Remote Control) + * channel and mode. It sets the GPIO to the appropriate input or output + * function based on the mode, and configures the signal inversion if + * necessary. + * + * Input Parameters: + * channel - The RMT peripheral channel number. + * mode - The mode of operation for the RMT channel (RMT_MODE_TX + * for transmission, RMT_MODE_RX for reception). + * gpio_num - The GPIO number to configure for the RMT channel. + * invert_signal - A boolean indicating whether to invert the signal. + * + * Returned Value: + * Returns OK on successful configuration of the GPIO. + * + ****************************************************************************/ + +static int rmt_set_gpio(rmt_channel_t channel, rmt_mode_t mode, + gpio_num_t gpio_num, bool invert_signal) +{ + int ret; + + DEBUGASSERT(channel < RMT_CHANNEL_MAX); + DEBUGASSERT(mode < RMT_MODE_MAX); + DEBUGASSERT((GPIO_IS_VALID_GPIO(gpio_num) && (mode == RMT_MODE_RX)) || + (GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) && + (mode == RMT_MODE_TX))); + + if (mode == RMT_MODE_TX) + { + DEBUGASSERT(RMT_IS_TX_CHANNEL(channel)); + esp_configgpio(gpio_num, OUTPUT); + esp_gpio_matrix_out( + gpio_num, + rmt_periph_signals.groups[0].channels[channel].tx_sig, + invert_signal, 0); + } + else + { + DEBUGASSERT(RMT_IS_RX_CHANNEL(channel)); + esp_configgpio(gpio_num, INPUT); + esp_gpio_matrix_in( + gpio_num, + rmt_periph_signals.groups[0].channels[channel].rx_sig, + invert_signal); + } + + return OK; +} + +/**************************************************************************** + * Name: rmt_is_channel_number_valid + * + * Description: + * This function checks if the provided RMT channel number is valid for the + * specified mode (TX or RX). For RX mode, it checks if the channel number + * is within the range of valid RX channels and less than the maximum + * channel number. For TX mode, it checks if the channel number is a valid + * TX channel. + * + * Input Parameters: + * channel - The RMT peripheral channel number. + * mode - The mode of operation for the RMT channel (RMT_MODE_TX for + * transmission, RMT_MODE_RX for reception). + * + * Returned Value: + * Returns true if the channel number is valid, false otherwise. + * + ****************************************************************************/ + +static bool rmt_is_channel_number_valid(rmt_channel_t channel, uint8_t mode) +{ + if (mode == RMT_MODE_RX) + { + return RMT_IS_RX_CHANNEL(channel) && (channel < RMT_CHANNEL_MAX); + } + + return (channel >= 0) && RMT_IS_TX_CHANNEL(channel); +} + +/**************************************************************************** + * Name: rmt_internal_config + * + * Description: + * This function configures the RMT peripheral with provided parameters. + * It sets the mode (TX or RX), channel, GPIO number, memory block number, + * clock divider, carrier frequency, and carrier enable flag. It also + * configures the clock source, memory access, idle level, carrier + * modulation, and other settings based on the mode and parameters. + * + * Input Parameters: + * dev - Pointer to the RMT peripheral device structure. + * rmt_param - Pointer to the structure containing the RMT channel + * configuration parameters. + * + * Returned Value: + * Returns OK on successful configuration of the RMT peripheral. + * + ****************************************************************************/ + +static int rmt_internal_config(rmt_dev_t *dev, + const struct rmt_channel_config_s *rmt_param) +{ + uint8_t mode = rmt_param->rmt_mode; + uint8_t channel = rmt_param->channel; + uint8_t gpio_num = rmt_param->gpio_num; + uint8_t mem_cnt = rmt_param->mem_block_num; + uint8_t clk_div = rmt_param->clk_div; + uint32_t carrier_freq_hz = rmt_param->tx_config.carrier_freq_hz; + bool carrier_en = rmt_param->tx_config.carrier_en; + uint32_t rmt_source_clk_hz; + irqstate_t flags; + + if (!rmt_is_channel_number_valid(channel, mode)) + { + rmterr("Invalid channel number %u for %s mode!", + channel, mode == RMT_MODE_TX ? "transmitter" : "receiver"); + return -EINVAL; + } + + DEBUGASSERT(mem_cnt + channel <= SOC_RMT_CHANNELS_PER_GROUP && + mem_cnt > 0); + DEBUGASSERT(clk_div > 0); + + if (mode == RMT_MODE_TX && carrier_en && carrier_freq_hz <= 0) + { + return -EINVAL; + } + + flags = spin_lock_irqsave(g_rmtdev_common.rmt_spinlock); + + rmt_ll_enable_mem_access_nonfifo(dev, true); + + if (rmt_param->flags & RMT_CHANNEL_FLAGS_AWARE_DFS) + { +#if SOC_RMT_SUPPORT_XTAL + + /* clock src: XTAL_CLK */ + + esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_XTAL, + ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, + &rmt_source_clk_hz); + rmt_ll_set_group_clock_src(dev, channel, + (rmt_clock_source_t)RMT_BASECLK_XTAL, + 1, 0, 0); +#elif SOC_RMT_SUPPORT_REF_TICK + + /* clock src: REF_CLK */ + + esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_REF, + ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, + &rmt_source_clk_hz); + rmt_ll_set_group_clock_src(dev, channel, + (rmt_clock_source_t)RMT_BASECLK_REF, + 1, 0, 0); +#else +#error "No clock source is aware of DFS" +#endif + } + else + { + /* fallback to use default clock source */ + + esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_DEFAULT, + ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, + &rmt_source_clk_hz); + rmt_ll_set_group_clock_src(dev, channel, + (rmt_clock_source_t)RMT_BASECLK_DEFAULT, + 1, 0, 0); + } + + spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + +#if SOC_RMT_CHANNEL_CLK_INDEPENDENT + g_rmt_source_clock_hz[channel] = rmt_source_clk_hz; +#else + if (g_rmt_source_clock_hz && rmt_source_clk_hz != g_rmt_source_clock_hz) + { + rmterr("RMT clock source has been configured to %"PRIu32" by other " + "channel, now reconfigure it to %"PRIu32"", + g_rmt_source_clock_hz, rmt_source_clk_hz); + } + + g_rmt_source_clock_hz = rmt_source_clk_hz; +#endif + rmtinfo("rmt_source_clk_hz: %"PRIu32, rmt_source_clk_hz); + + if (mode == RMT_MODE_TX) + { + uint16_t carrier_duty_percent = + rmt_param->tx_config.carrier_duty_percent; + uint8_t carrier_level = rmt_param->tx_config.carrier_level; + uint8_t idle_level = rmt_param->tx_config.idle_level; + + flags = spin_lock_irqsave(g_rmtdev_common.rmt_spinlock); + rmt_ll_tx_set_channel_clock_div(dev, channel, clk_div); + rmt_ll_tx_set_mem_blocks(dev, channel, mem_cnt); + rmt_ll_tx_reset_pointer(dev, channel); + rmt_ll_tx_enable_loop(dev, channel, rmt_param->tx_config.loop_en); +#if SOC_RMT_SUPPORT_TX_LOOP_COUNT + if (rmt_param->tx_config.loop_en) + { + rmt_ll_tx_set_loop_count(dev, channel, + rmt_param->tx_config.loop_count); + } +#endif + + /* always enable tx ping-pong */ + + rmt_ll_tx_enable_wrap(dev, channel, true); + + /* Set idle level */ + + rmt_ll_tx_fix_idle_level(dev, channel, idle_level, + rmt_param->tx_config.idle_output_en); + + /* Set carrier */ + + rmt_ll_tx_enable_carrier_modulation(dev, channel, carrier_en); + if (carrier_en) + { + uint32_t duty_div; + uint32_t duty_h; + uint32_t duty_l; + duty_div = rmt_source_clk_hz / carrier_freq_hz; + duty_h = duty_div * carrier_duty_percent / 100; + duty_l = duty_div - duty_h; + rmt_ll_tx_set_carrier_level(dev, channel, carrier_level); + rmt_ll_tx_set_carrier_high_low_ticks(dev, channel, duty_h, duty_l); + } + else + { + rmt_ll_tx_set_carrier_level(dev, channel, 0); + } + + spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + + rmtinfo("Rmt Tx Channel %u|Gpio %u|Sclk_Hz %"PRIu32"|Div %u|Carrier_Hz" + " %"PRIu32"|Duty %u", channel, gpio_num, rmt_source_clk_hz, + clk_div, carrier_freq_hz, carrier_duty_percent); + } + else if (RMT_MODE_RX == mode) + { + uint8_t filter_cnt = rmt_param->rx_config.filter_ticks_thresh; + uint16_t threshold = rmt_param->rx_config.idle_threshold; + + flags = spin_lock_irqsave(g_rmtdev_common.rmt_spinlock); + rmt_ll_rx_set_channel_clock_div(dev, RMT_DECODE_RX_CHANNEL(channel), + clk_div); + rmt_ll_rx_set_mem_blocks(dev, RMT_DECODE_RX_CHANNEL(channel), mem_cnt); + rmt_ll_rx_reset_pointer(dev, RMT_DECODE_RX_CHANNEL(channel)); + rmt_ll_rx_set_mem_owner(dev, RMT_DECODE_RX_CHANNEL(channel), + RMT_LL_MEM_OWNER_HW); + + /* Set idle threshold */ + + rmt_ll_rx_set_idle_thres(dev, RMT_DECODE_RX_CHANNEL(channel), + threshold); + + /* Set RX filter */ + + rmt_ll_rx_set_filter_thres(dev, RMT_DECODE_RX_CHANNEL(channel), + filter_cnt); + rmt_ll_rx_enable_filter(dev, RMT_DECODE_RX_CHANNEL(channel), + rmt_param->rx_config.filter_en); + +#ifdef SOC_RMT_SUPPORT_RX_PINGPONG + + /* always enable rx ping-pong */ + + rmt_ll_rx_enable_wrap(dev, RMT_DECODE_RX_CHANNEL(channel), true); +#endif + +#if SOC_RMT_SUPPORT_RX_DEMODULATION + rmt_ll_rx_enable_carrier_demodulation(dev, + RMT_DECODE_RX_CHANNEL(channel), + rmt_param->rx_config.rm_carrier); + if (rmt_param->rx_config.rm_carrier) + { + uint32_t duty_total; + uint32_t duty_high; + uint32_t ch_clk_div = + rmt_ll_rx_get_channel_clock_div(dev, + RMT_DECODE_RX_CHANNEL(channel)); + duty_total = rmt_source_clk_hz / \ + ch_clk_div / \ + rmt_param->rx_config.carrier_freq_hz; + duty_high = duty_total * + rmt_param->rx_config.carrier_duty_percent / 100; + + /* there could be residual in timing the carrier pulse, so double + * enlarge the theoretical value. + */ + + rmt_ll_rx_set_carrier_high_low_ticks( + dev, RMT_DECODE_RX_CHANNEL(channel), duty_high * 2, + (duty_total - duty_high) * 2); + rmt_ll_rx_set_carrier_level(dev, RMT_DECODE_RX_CHANNEL(channel), + rmt_param->rx_config.carrier_level); + } +#endif + + spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + + rmtinfo("Rmt Rx Channel %u|Gpio %u|Sclk_Hz %"PRIu32"|Div %u|Thresold " + "%u|Filter %u", channel, gpio_num, rmt_source_clk_hz, clk_div, + threshold, filter_cnt); + } + + return OK; +} + +/**************************************************************************** + * Name: rmt_config + * + * Description: + * This function configures the RMT channel with the provided parameters. + * It enables the RMT module, sets the GPIO for the RMT channel, and + * configures the RMT peripheral using the internal configuration function. + * + * Input Parameters: + * rmt_param - Pointer to the structure containing the RMT channel + * configuration parameters. + * + * Returned Value: + * Returns OK on successful configuration of the RMT channel; a negated + * errno value is returned on any failure. + * + ****************************************************************************/ + +static int rmt_config(const struct rmt_channel_config_s *rmt_param) +{ + int ret = ERROR; + + rmt_module_enable(); + + rmt_set_gpio(rmt_param->channel, rmt_param->rmt_mode, rmt_param->gpio_num, + rmt_param->flags & RMT_CHANNEL_FLAGS_INVERT_SIG); + + ret = rmt_internal_config(&RMT, rmt_param); + + return ret; +} + +/**************************************************************************** + * Name: rmt_fill_memory + * + * Description: + * This function fills the RMT memory with the provided items. It copies + * the items from the source to the RMT memory for the specified channel, + * starting at the specified memory offset. + * + * Input Parameters: + * channel - The RMT peripheral channel number. + * item - Pointer to the items to be copied to the RMT memory. + * item_num - The number of items to be copied. + * mem_offset - The memory offset at which to start copying. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void IRAM_ATTR rmt_fill_memory(rmt_channel_t channel, + const rmt_item32_t *item, + uint16_t item_num, + uint16_t mem_offset) +{ + uint32_t *from = (uint32_t *)item; + volatile uint32_t *to = + (volatile uint32_t *)&RMTMEM.chan[channel].data32[0].val; + + to += mem_offset; + + while (item_num--) + { + *to++ = *from++; + } +} + +/**************************************************************************** + * Name: rmt_isr_register + * + * Description: + * This function registers an interrupt service routine (ISR) for the RMT + * peripheral. It allocates a CPU interrupt, attaches the ISR to the + * interrupt, and returns the status of the operation. + * + * Input Parameters: + * fn - Pointer to the ISR function. + * arg - Pointer to the argument to be passed to the ISR. + * intr_alloc_flags - Flags for the interrupt allocation. + * + * Returned Value: + * Returns OK on successful registration of the ISR; a negated errno value + * is returned on any failure. + * + ****************************************************************************/ + +static int rmt_isr_register(int (*fn)(int, void *, void *), void *arg, + int intr_alloc_flags) +{ + int cpuint; + int ret; + int cpu = up_cpu_index(); + + DEBUGASSERT(fn); + DEBUGASSERT(g_rmtdev_common.rmt_driver_channels == 0); + + cpuint = esp_setup_irq(rmt_periph_signals.groups[0].irq, + ESP_IRQ_PRIORITY_DEFAULT, + ESP_IRQ_TRIGGER_LEVEL); + if (cpuint < 0) + { + rmterr("Failed to allocate a CPU interrupt.\n"); + return -ENOMEM; + } + + ret = irq_attach(ESP_SOURCE2IRQ(rmt_periph_signals.groups[0].irq), + fn, &g_rmtdev_common.hal); + if (ret < 0) + { + rmterr("Couldn't attach IRQ to handler.\n"); + esp_teardown_irq(rmt_periph_signals.groups[0].irq, cpuint); + return ret; + } + + up_enable_irq(ESP_SOURCE2IRQ(rmt_periph_signals.groups[0].irq)); + + return ret; +} + +/**************************************************************************** + * Name: rmt_driver_isr_default + * + * Description: + * This function is the default interrupt service routine (ISR) for the RMT + * peripheral. It handles TX end, TX threshold, RX end, RX threshold, loop + * count, RX error, and TX error interrupts. For each interrupt type, it + * checks the status, clears the interrupt, and performs the appropriate + * actions based on the RMT object associated with the channel. + * + * Input Parameters: + * irq - The interrupt request number. + * context - Pointer to the interrupt context. + * arg - Pointer to the argument to be passed to the ISR. + * + * Returned Value: + * Returns OK after handling all active interrupts. + * + ****************************************************************************/ + +static int IRAM_ATTR rmt_driver_isr_default(int irq, void *context, + void *arg) +{ + uint32_t status = 0; + rmt_item32_t *addr = NULL; + uint8_t channel = 0; + rmt_hal_context_t *hal = (rmt_hal_context_t *)arg; + + /* Tx end interrupt */ + + status = rmt_ll_get_tx_end_interrupt_status(hal->regs); + while (status) + { + channel = __builtin_ffs(status) - 1; + status &= ~(1 << channel); + rmt_obj_t *p_rmt = p_rmt_obj[channel]; + if (p_rmt) + { + nxsem_post(&p_rmt->tx_sem); + rmt_ll_tx_reset_pointer(g_rmtdev_common.hal.regs, channel); + p_rmt->tx_data = NULL; + p_rmt->tx_len_rem = 0; + p_rmt->tx_offset = 0; + p_rmt->tx_sub_len = 0; + p_rmt->sample_cur = NULL; + } + + rmt_ll_clear_interrupt_status(hal->regs, + RMT_LL_EVENT_TX_DONE(channel)); + } + + /* Tx thres interrupt */ + + status = rmt_ll_get_tx_thres_interrupt_status(hal->regs); + while (status) + { + channel = __builtin_ffs(status) - 1; + status &= ~(1 << channel); + rmt_obj_t *p_rmt = p_rmt_obj[channel]; + if (p_rmt) + { + const rmt_item32_t *pdata = p_rmt->tx_data; + size_t len_rem = p_rmt->tx_len_rem; + rmt_idle_level_t idle_level = + rmt_ll_tx_get_idle_level(hal->regs, channel); + rmt_item32_t stop_data = (rmt_item32_t) + { + .level0 = idle_level, + .duration0 = 0, + }; + + if (len_rem >= p_rmt->tx_sub_len) + { + rmt_fill_memory(channel, pdata, p_rmt->tx_sub_len, + p_rmt->tx_offset); + p_rmt->tx_data += p_rmt->tx_sub_len; + p_rmt->tx_len_rem -= p_rmt->tx_sub_len; + } + else if (len_rem == 0) + { + rmt_fill_memory(channel, &stop_data, 1, p_rmt->tx_offset); + } + else + { + rmt_fill_memory(channel, pdata, len_rem, p_rmt->tx_offset); + rmt_fill_memory(channel, &stop_data, 1, + p_rmt->tx_offset + len_rem); + p_rmt->tx_data += len_rem; + p_rmt->tx_len_rem -= len_rem; + } + + if (p_rmt->tx_offset == 0) + { + p_rmt->tx_offset = p_rmt->tx_sub_len; + } + else + { + p_rmt->tx_offset = 0; + } + } + + rmt_ll_clear_interrupt_status(hal->regs, + RMT_LL_EVENT_TX_THRES(channel)); + } + + /* Rx end interrupt */ + + status = rmt_ll_get_rx_end_interrupt_status(hal->regs); + while (status) + { + channel = __builtin_ffs(status) - 1; + status &= ~(1 << channel); + rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)]; + if (p_rmt) + { + int item_len; + rmt_ll_rx_enable(g_rmtdev_common.hal.regs, channel, false); + item_len = + rmt_ll_rx_get_memory_writer_offset(g_rmtdev_common.hal.regs, + channel); + rmt_ll_rx_set_mem_owner(g_rmtdev_common.hal.regs, channel, + RMT_LL_MEM_OWNER_SW); + if (circbuf_is_init(&p_rmt->rx_buf)) + { + int bytes; + + addr = (rmt_item32_t *) + RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32; +#ifdef SOC_RMT_SUPPORT_RX_PINGPONG + if (item_len > p_rmt->rx_item_start_idx) + { + item_len = item_len - p_rmt->rx_item_start_idx; + } + + /* Check for RX buffer max length */ + + if ((p_rmt->rx_item_len + item_len) > \ + (p_rmt->rx_item_buf_size / 4)) + { + int remaining_len = (p_rmt->rx_item_buf_size / 4) - \ + p_rmt->rx_item_len; + rmterr("ERROR: RX buffer too small: %d items dropped\n", + item_len - remaining_len); + item_len = remaining_len; + } + + memcpy((void *)(p_rmt->rx_item_buf + p_rmt->rx_item_len), + (void *)(addr + p_rmt->rx_item_start_idx), + item_len * 4); + p_rmt->rx_item_len += item_len; + bytes = circbuf_write(&p_rmt->rx_buf, + (void *)(p_rmt->rx_item_buf), + p_rmt->rx_item_len * 4); +#else + bytes = circbuf_write(&p_rmt->rx_buf, (void *)addr, + item_len * 4); +#endif + nxsem_post(&p_rmt->rx_sem); + if (bytes < (item_len * 4)) + { + rmterr("RMT RX BUFFER FULL"); + } + } + else + { + rmterr("RMT RX BUFFER ERROR"); + } + +#ifdef SOC_RMT_SUPPORT_RX_PINGPONG + p_rmt->rx_item_start_idx = 0; + p_rmt->rx_item_len = 0; + memset((void *)p_rmt->rx_item_buf, 0, p_rmt->rx_item_buf_size); +#endif + rmt_ll_rx_reset_pointer(g_rmtdev_common.hal.regs, channel); + rmt_ll_rx_set_mem_owner(g_rmtdev_common.hal.regs, channel, + RMT_LL_MEM_OWNER_HW); + rmt_ll_rx_enable(g_rmtdev_common.hal.regs, channel, true); + } + + rmt_ll_clear_interrupt_status(hal->regs, + RMT_LL_EVENT_RX_DONE(channel)); + } + +#ifdef SOC_RMT_SUPPORT_RX_PINGPONG + + /* Rx thres interrupt */ + + status = rmt_ll_get_rx_thres_interrupt_status(hal->regs); + while (status) + { + int mem_item_size; + int rx_thres_lim; + int item_len; + + channel = __builtin_ffs(status) - 1; + status &= ~(1 << channel); + rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)]; + mem_item_size = rmt_ll_rx_get_mem_blocks(g_rmtdev_common.hal.regs, + channel) * RMT_MEM_ITEM_NUM; + rx_thres_lim = rmt_ll_rx_get_limit(g_rmtdev_common.hal.regs, channel); + item_len = (p_rmt->rx_item_start_idx == 0) ? rx_thres_lim : \ + (mem_item_size - rx_thres_lim); + if ((p_rmt->rx_item_len + item_len) > (p_rmt->rx_item_buf_size / 4)) + { + int remaining_len = (p_rmt->rx_item_buf_size / 4) - \ + p_rmt->rx_item_len; + rmterr("ERROR: RX buffer too small!\n"); + item_len = remaining_len; + } + + rmt_ll_rx_set_mem_owner(g_rmtdev_common.hal.regs, channel, + RMT_LL_MEM_OWNER_SW); + memcpy( + (void *)(p_rmt->rx_item_buf + p_rmt->rx_item_len), + (void *)(RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32 \ + + p_rmt->rx_item_start_idx), item_len * 4); + rmt_ll_rx_set_mem_owner(g_rmtdev_common.hal.regs, channel, + RMT_LL_MEM_OWNER_HW); + p_rmt->rx_item_len += item_len; + p_rmt->rx_item_start_idx += item_len; + if (p_rmt->rx_item_start_idx >= mem_item_size) + { + p_rmt->rx_item_start_idx = 0; + } + + rmt_ll_clear_interrupt_status(hal->regs, + RMT_LL_EVENT_RX_THRES(channel)); + } +#endif + +#if SOC_RMT_SUPPORT_TX_LOOP_COUNT + + /* loop count interrupt */ + + status = rmt_ll_get_tx_loop_interrupt_status(hal->regs); + while (status) + { + channel = __builtin_ffs(status) - 1; + status &= ~(1 << channel); + rmt_obj_t *p_rmt = p_rmt_obj[channel]; + if (p_rmt) + { + if (p_rmt->loop_autostop) + { +#ifndef SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP + + /* hardware doesn't support automatically stop output so driver + * should stop output here (possibility already overshotted + * several us). + */ + + rmt_ll_tx_stop(g_rmtdev_common.hal.regs, channel); + rmt_ll_tx_reset_pointer(g_rmtdev_common.hal.regs, channel); +#endif + } + + nxsem_post(&p_rmt->tx_sem); + } + + rmt_ll_clear_interrupt_status(hal->regs, + RMT_LL_EVENT_TX_LOOP_END(channel)); + } +#endif + + /* RX Err interrupt */ + + status = rmt_ll_get_rx_err_interrupt_status(hal->regs); + while (status) + { + channel = __builtin_ffs(status) - 1; + status &= ~(1 << channel); + rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)]; + if (p_rmt) + { + /* Reset the receiver's write/read addresses to prevent endless + * err interrupts. + */ + + rmt_ll_rx_reset_pointer(g_rmtdev_common.hal.regs, channel); + rmtinfo("RMT RX channel %d error", channel); + rmtinfo("status: 0x%08lx", + rmt_ll_rx_get_status_word(g_rmtdev_common.hal.regs, + channel)); + } + + rmt_ll_clear_interrupt_status(hal->regs, + RMT_LL_EVENT_RX_ERROR(channel)); + } + + /* TX Err interrupt */ + + status = rmt_ll_get_tx_err_interrupt_status(hal->regs); + while (status) + { + channel = __builtin_ffs(status) - 1; + status &= ~(1 << channel); + rmt_obj_t *p_rmt = p_rmt_obj[channel]; + if (p_rmt) + { + /* Reset the transmitter's write/read addresses to prevent + * endless err interrupts. + */ + + rmt_ll_tx_reset_pointer(g_rmtdev_common.hal.regs, channel); + rmtinfo("RMT TX channel %d error", channel); + rmtinfo("status: 0x%08lx", + rmt_ll_tx_get_status_word(g_rmtdev_common.hal.regs, + channel)); + } + + rmt_ll_clear_interrupt_status(hal->regs, + RMT_LL_EVENT_TX_ERROR(channel)); + } + + return OK; +} + +/**************************************************************************** + * Name: rmt_driver_install + * + * Description: + * This function installs the RMT driver for a specific channel. It + * allocates memory for the RMT object, initializes the object properties, + * and sets up the RX buffer if specified. It also registers the default + * ISR if this is the first RMT channel using the driver, and resets the + * RMT channel. + * + * Input Parameters: + * channel - The RMT peripheral channel number. + * rx_buf_size - The size of the RX buffer. + * intr_alloc_flags - Flags for the interrupt allocation. + * + * Returned Value: + * Returns OK on successful installation of the RMT driver; a negated errno + * value is returned on any failure. + * + ****************************************************************************/ + +static int rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, + int intr_alloc_flags) +{ + DEBUGASSERT(channel < RMT_CHANNEL_MAX); + + int ret = OK; + + if (p_rmt_obj[channel]) + { + rmtwarn("RMT driver already installed"); + return ERROR; + } + +#if CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH + if (intr_alloc_flags & ESP_INTR_FLAG_IRAM) + { + rmterr("ringbuf ISR functions in flash, but used in IRAM interrupt"); + return -EINVAL; + } +#endif + +#ifndef CONFIG_SPIRAM_USE_MALLOC + p_rmt_obj[channel] = kmm_calloc(1, sizeof(rmt_obj_t)); +#else + if (!(intr_alloc_flags & ESP_INTR_FLAG_IRAM)) + { + p_rmt_obj[channel] = calloc(1, sizeof(rmt_obj_t)); + } + else + { + p_rmt_obj[channel] = kmm_calloc(1, sizeof(rmt_obj_t)); + } +#endif + + if (p_rmt_obj[channel] == NULL) + { + rmterr("RMT driver malloc error"); + return -ENOMEM; + } + + p_rmt_obj[channel]->tx_len_rem = 0; + p_rmt_obj[channel]->tx_data = NULL; + p_rmt_obj[channel]->channel = channel; + p_rmt_obj[channel]->tx_offset = 0; + p_rmt_obj[channel]->tx_sub_len = 0; + p_rmt_obj[channel]->wait_done = false; + p_rmt_obj[channel]->loop_autostop = false; + +#ifndef CONFIG_SPIRAM_USE_MALLOC + nxsem_init(&p_rmt_obj[channel]->tx_sem, 0, 0); + nxsem_init(&p_rmt_obj[channel]->rx_sem, 0, 0); +#endif + + nxsem_post(&p_rmt_obj[channel]->tx_sem); + + if (!circbuf_is_init(&p_rmt_obj[channel]->rx_buf) && rx_buf_size > 0) + { + circbuf_init(&p_rmt_obj[channel]->rx_buf, NULL, rx_buf_size); + } + +#ifdef SOC_RMT_SUPPORT_RX_PINGPONG + if (p_rmt_obj[channel]->rx_item_buf == NULL && rx_buf_size > 0) + { +# ifndef CONFIG_SPIRAM_USE_MALLOC + p_rmt_obj[channel]->rx_item_buf = kmm_calloc(1, rx_buf_size); +# else + if (!(p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM)) + { + p_rmt_obj[channel]->rx_item_buf = calloc(1, rx_buf_size); + } + else + { + p_rmt_obj[channel]->rx_item_buf = kmm_calloc(1, rx_buf_size); + } + +# endif + if (p_rmt_obj[channel]->rx_item_buf == NULL) + { + rmterr("RMT malloc fail"); + nxsem_destroy(&p_rmt_obj[channel]->rx_sem); + return -ENOMEM; + } + + p_rmt_obj[channel]->rx_item_buf_size = rx_buf_size; + } +#endif + + nxrmutex_lock(&(g_rmtdev_common.rmt_driver_isr_lock)); + + if (g_rmtdev_common.rmt_driver_channels == 0) + { + /* first RMT channel using driver */ + + ret = rmt_isr_register(rmt_driver_isr_default, &g_rmtdev_common.hal, + intr_alloc_flags); + } + + if (ret == OK) + { + g_rmtdev_common.rmt_driver_channels |= BIT(channel); + } + + nxrmutex_unlock(&(g_rmtdev_common.rmt_driver_isr_lock)); + + rmt_module_enable(); + + if (RMT_IS_RX_CHANNEL(channel)) + { + rmt_hal_rx_channel_reset(&g_rmtdev_common.hal, + RMT_DECODE_RX_CHANNEL(channel)); + } + else + { + rmt_hal_tx_channel_reset(&g_rmtdev_common.hal, channel); + } + + return OK; +} + +/**************************************************************************** + * Name: rmt_write_items + * + * Description: + * This function writes items to the RMT memory for a specific channel. It + * checks the validity of the parameters, calculates the memory blocks and + * item lengths, and fills the memory with the items. If the number of + * items is greater than the memory block length, it enables the TX + * threshold interrupt and sets up the remaining items to be sent. If the + * number of items is less than the memory block length, it fills the + * remaining memory with idle level items. It then starts the TX process + * and waits for it to finish if specified. + * + * Input Parameters: + * channel - The RMT peripheral channel number. + * rmt_item - Pointer to the items to be written to the RMT memory. + * item_num - The number of items to be written. + * wait_tx_done - Flag to indicate whether to wait for the TX process to + * finish. + * + * Returned Value: + * Returns OK on successful writing of the items to the RMT memory; a + * negated errno value is returned on any failure. + * + ****************************************************************************/ + +static int rmt_write_items(rmt_channel_t channel, + const rmt_item32_t *rmt_item, + int item_num, + bool wait_tx_done) +{ + DEBUGASSERT(RMT_IS_TX_CHANNEL(channel)); + DEBUGASSERT(p_rmt_obj[channel]); + DEBUGASSERT(rmt_item); + DEBUGASSERT(item_num > 0); + + uint32_t mem_blocks = rmt_ll_tx_get_mem_blocks(g_rmtdev_common.hal.regs, + channel); + + DEBUGASSERT(mem_blocks + channel <= SOC_RMT_CHANNELS_PER_GROUP); +#ifdef CONFIG_SPIRAM_USE_MALLOC + if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) + { + if (!esp_ptr_internal(rmt_item)) + { + rmterr(RMT_PSRAM_BUFFER_WARN_STR); + return ESP_ERR_INVALID_ARG; + } + } +#endif + + rmt_obj_t *p_rmt = p_rmt_obj[channel]; + int item_block_len = mem_blocks * RMT_MEM_ITEM_NUM; + int item_sub_len = mem_blocks * RMT_MEM_ITEM_NUM / 2; + int len_rem = item_num; + nxsem_wait(&p_rmt->tx_sem); + + /* fill the memory block first */ + + if (item_num >= item_block_len) + { + rmt_fill_memory(channel, rmt_item, item_block_len, 0); + len_rem -= item_block_len; + rmt_set_tx_loop_mode(channel, false); + rmt_set_tx_thr_intr_en(channel, 1, item_sub_len); + p_rmt->tx_data = rmt_item + item_block_len; + p_rmt->tx_len_rem = len_rem; + p_rmt->tx_offset = 0; + p_rmt->tx_sub_len = item_sub_len; + } + else + { + rmt_idle_level_t idle_level; + rmt_fill_memory(channel, rmt_item, len_rem, 0); + idle_level = rmt_ll_tx_get_idle_level(g_rmtdev_common.hal.regs, + channel); + rmt_item32_t stop_data = (rmt_item32_t) + { + .level0 = idle_level, + .duration0 = 0, + }; + + rmt_fill_memory(channel, &stop_data, 1, len_rem); + p_rmt->tx_len_rem = 0; + } + + rmt_tx_start(channel, true); + p_rmt->wait_done = wait_tx_done; + if (wait_tx_done) + { + /* wait loop done */ + + if (rmt_ll_tx_is_loop_enabled(g_rmtdev_common.hal.regs, channel)) + { +#if SOC_RMT_SUPPORT_TX_LOOP_COUNT + nxsem_wait(&p_rmt->tx_sem); + nxsem_post(&p_rmt->tx_sem); +#endif + } + else + { + /* wait tx end */ + + nxsem_wait(&p_rmt->tx_sem); + nxsem_post(&p_rmt->tx_sem); + } + } + + return OK; +} + +/**************************************************************************** + * Name: esp_rmt_read + * + * Description: + * This function reads data from the RMT device. + * It starts the RMT module in receiving mode for a specific channel and + * checks for any errors. If an error occurs during the start of the RMT + * module, it returns the error code. Please note that this function + * starts the receiver, but the actual data is read from the ring buffer + * by the upper half driver. + * + * Input Parameters: + * dev - Pointer to the RMT device structure. + * buffer - Pointer to the buffer where the read data should be stored. + * buflen - The maximum amount of data to be read. + * + * Returned Value: + * Returns the number of bytes read from the RMT device; a negated errno + * value is returned on any failure. + * + ****************************************************************************/ + +static ssize_t esp_rmt_read(struct rmt_dev_s *dev, char *buffer, + size_t buflen) +{ + struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)dev; + rmt_mode_t mode = priv->mode; + int channel = priv->minor; + int ret; + ssize_t nread; + + if (mode != RMT_MODE_RX) + { + rmterr("ERROR: RMT channel %d is not in RX mode\n", channel); + return -EINVAL; + } + + DEBUGASSERT((buflen % 4) == 0); + + if ((buflen / 4) > (CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE / 4)) + { + rmtwarn("WARN: RMT RX buffer (%d bytes) is smaller than requested " + "read bytes (%d bytes). A partial read will take place!\n", + CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE, + buflen); + } + +#ifndef SOC_RMT_SUPPORT_RX_PINGPONG + if ((buflen / 4) > RMT_MEM_ITEM_NUM) + { + rmtwarn("WARN: RMT RX channel is able to receive up to " + "%d RMT items (%d bytes)!", + RMT_MEM_ITEM_NUM, RMT_MEM_ITEM_NUM * 4); + } +#endif + + ret = rmt_rx_start(channel, true); + if (ret < 0) + { + rmterr("ERROR: rmt_rx_start failed: %d\n", ret); + return (ssize_t)ret; + } + + return (ssize_t)ret; +} + +/**************************************************************************** + * Name: esp_rmt_write + * + * Description: + * This function writes data to the RMT memory for a specific channel. It + * asserts that the length of the data is a multiple of 4, then calls the + * rmt_write_items function to write the items to the RMT memory. + * + * Input Parameters: + * dev - Pointer to the RMT device structure. + * buffer - Pointer to the data to be written to the RMT memory. + * buflen - The length of the data to be written. + * + * Returned Value: + * Returns the number of items written to the RMT memory. + * + ****************************************************************************/ + +static ssize_t esp_rmt_write(struct rmt_dev_s *dev, const char *buffer, + size_t buflen) +{ + struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)dev; + rmt_mode_t mode = priv->mode; + int channel = priv->minor; + int ret; + struct timespec timeout; + + if (mode != RMT_MODE_TX) + { + rmterr("ERROR: RMT channel %d is not in TX mode\n", channel); + return -EINVAL; + } + + DEBUGASSERT((buflen % 4) == 0); + + ret = rmt_write_items(channel, (const rmt_item32_t *)buffer, + (buflen / 4), true); + + if (ret < 0) + { + rmterr("ERROR: rmt_write_items failed: %d\n", ret); + return (ssize_t)0; + } + + return (ssize_t)buflen; +} + +/**************************************************************************** + * Name: esp_rmtinitialize + * + * Description: + * This function initializes the specified RMT (Remote Control) device + * with the provided configuration. + * + * Input Parameters: + * config - A structure containing the configuration settings for the + * RMT channel to be initialized. + * + * Returned Value: + * On success, this function returns a valid pointer to the RMT device + * structure. If the initialization fails, it returns NULL. + * + ****************************************************************************/ + +static struct rmt_dev_s + *esp_rmtinitialize(struct rmt_channel_config_s config) +{ + struct rmt_dev_lowerhalf_s *priv; + int ret; +#ifdef CONFIG_RMT_LOOP_TEST_MODE + uint8_t channel; +#endif + +#if (CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE % 4) != 0 +# error "CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE must be a multiple of 4" +#endif + + priv = kmm_zalloc(sizeof(struct rmt_dev_lowerhalf_s)); + if (priv) + { + ret = rmt_config(&config); + if (ret < 0) + { + rmterr("ERROR: rmt_config failed: %d\n", ret); + return NULL; + } + +#ifdef CONFIG_RMT_LOOP_TEST_MODE + if (config.rmt_mode == RMT_MODE_TX) + { + if (g_tx_channel != RMT_CHANNEL_MAX) + { + rmterr("ERROR: only one TX channel can be used in loop test " + "mode\n"); + PANIC(); + } + + g_tx_channel = config.channel; + } + else + { + if (g_rx_channel != RMT_CHANNEL_MAX) + { + rmterr("ERROR: only one RX channel can be used in loop test " + "mode\n"); + PANIC(); + } + + g_rx_channel = config.channel; + } + + if (g_rx_channel != RMT_CHANNEL_MAX && g_tx_channel != RMT_CHANNEL_MAX) + { + esp_configgpio(config.gpio_num, OUTPUT | INPUT); + esp_gpio_matrix_out(config.gpio_num, + RMT_SIG_OUT0_IDX + g_tx_channel, + 0, 0); + esp_gpio_matrix_in(config.gpio_num, + RMT_SIG_IN0_IDX + g_rx_channel, + 0); + rmtwarn("RX channel %d and TX channel %d are used in loop test " + "mode\n", g_rx_channel, g_tx_channel); + } +#endif + + ret = rmt_driver_install(config.channel, + config.rmt_mode == RMT_MODE_RX ? \ + CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE : 0, 0); + if (ret < 0) + { + rmterr("ERROR: rmt_driver_install failed: %d\n", ret); + return NULL; + } + + priv->ops = &g_rmtops; + priv->recvsem = &p_rmt_obj[config.channel]->rx_sem; + priv->circbuf = &p_rmt_obj[config.channel]->rx_buf; + priv->minor = config.channel; + + priv->common = &g_rmtdev_common; + priv->mode = config.rmt_mode; + } + else + { + rmterr("ERROR: memory allocation failed\n"); + return NULL; + } + + return (struct rmt_dev_s *)priv; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_rmt_tx_init + * + * Description: + * Initialize the selected RMT device in TX mode + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the TX channel + * + * Returned Value: + * Valid RMT device structure reference on success; NULL, otherwise. + * + ****************************************************************************/ + +struct rmt_dev_s *esp_rmt_tx_init(int ch, int pin) +{ + struct rmt_channel_config_s config = RMT_DEFAULT_CONFIG_TX(pin, ch); + + return esp_rmtinitialize(config); +} + +/**************************************************************************** + * Name: esp_rmt_rx_init + * + * Description: + * Initialize the selected RMT device in RC mode + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the RX channel + * + * Returned Value: + * Valid RMT device structure reference on success; NULL, otherwise. + * + ****************************************************************************/ + +struct rmt_dev_s *esp_rmt_rx_init(int ch, int pin) +{ + struct rmt_channel_config_s config = RMT_DEFAULT_CONFIG_RX(pin, ch); + + return esp_rmtinitialize(config); +} + +#endif diff --git a/arch/risc-v/src/common/espressif/esp_rmt.h b/arch/risc-v/src/common/espressif/esp_rmt.h new file mode 100644 index 0000000000000..84bec403e9c4e --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_rmt.h @@ -0,0 +1,109 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_rmt.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISC_V_SRC_COMMON_ESPRESSIF_ESP_RMT_H +#define __ARCH_RISC_V_SRC_COMMON_ESPRESSIF_ESP_RMT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RMT_MEM_ITEM_NUM SOC_RMT_MEM_WORDS_PER_CHANNEL + +#define RMT_DEFAULT_CLK_DIV 1 + +/* Channel can work during APB clock scaling */ + +#define RMT_CHANNEL_FLAGS_AWARE_DFS (1 << 0) + +/* Invert RMT signal */ + +#define RMT_CHANNEL_FLAGS_INVERT_SIG (1 << 1) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#if defined(CONFIG_ESP_RMT) + +/**************************************************************************** + * Name: esp_rmt_tx_init + * + * Description: + * Initialize the selected RMT device in TX mode + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the TX channel + * + * Returned Value: + * Valid RMT device structure reference on success; NULL, otherwise. + * + ****************************************************************************/ + +struct rmt_dev_s *esp_rmt_tx_init(int ch, int pin); + +/**************************************************************************** + * Name: esp_rmt_rx_init + * + * Description: + * Initialize the selected RMT device in RC mode + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the RX channel + * + * Returned Value: + * Valid RMT device structure reference on success; NULL, otherwise. + * + ****************************************************************************/ + +struct rmt_dev_s *esp_rmt_rx_init(int ch, int pin); + +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_RISC_V_SRC_COMMON_ESPRESSIF_ESP_RMT_H */ diff --git a/arch/risc-v/src/espressif/esp_rtc.c b/arch/risc-v/src/common/espressif/esp_rtc.c similarity index 99% rename from arch/risc-v/src/espressif/esp_rtc.c rename to arch/risc-v/src/common/espressif/esp_rtc.c index cf819ea7f9619..2aba3c9edc76a 100644 --- a/arch/risc-v/src/espressif/esp_rtc.c +++ b/arch/risc-v/src/common/espressif/esp_rtc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_rtc.c + * arch/risc-v/src/common/espressif/esp_rtc.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -865,7 +865,11 @@ int esp_rtc_driverinit(void) /* Enable HR-Timer */ - VERIFY(esp_hr_timer_init()); + ret = esp_hr_timer_init(); + if (ret < 0) + { + return ret; + } g_hr_timer_enabled = true; diff --git a/arch/risc-v/src/espressif/esp_rtc.h b/arch/risc-v/src/common/espressif/esp_rtc.h similarity index 89% rename from arch/risc-v/src/espressif/esp_rtc.h rename to arch/risc-v/src/common/espressif/esp_rtc.h index 0ddc9d2ac1028..ef2dfee402e0c 100644 --- a/arch/risc-v/src/espressif/esp_rtc.h +++ b/arch/risc-v/src/common/espressif/esp_rtc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_rtc.h + * arch/risc-v/src/common/espressif/esp_rtc.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESPRESSIF_ESP_RTC_H -#define __ARCH_RISCV_SRC_ESPRESSIF_ESP_RTC_H +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_RTC_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_RTC_H /**************************************************************************** * Included Files @@ -48,4 +48,4 @@ int esp_rtc_driverinit(void); -#endif /* __ARCH_RISCV_SRC_ESPRESSIF_ESP_RTC_H */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_RTC_H */ diff --git a/arch/risc-v/src/common/espressif/esp_rtc_gpio.c b/arch/risc-v/src/common/espressif/esp_rtc_gpio.c new file mode 100644 index 0000000000000..62dc537bd6bf7 --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_rtc_gpio.c @@ -0,0 +1,264 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_rtc_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "irq.h" +#include "riscv_internal.h" +#include "esp_irq.h" +#include "esp_rtc_gpio.h" +#include "soc/rtc_io_periph.h" +#include "hal/rtc_io_hal.h" +#include "soc/rtc_cntl_periph.h" +#include "soc/periph_defs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_ARCH_CHIP_ESP32C3_GENERIC +#ifdef CONFIG_ESPRESSIF_RTCIO_IRQ +static int g_rtcio_cpuint; +static uint32_t last_status; + +#ifdef CONFIG_ARCH_CHIP_ESP32C3_GENERIC +static const int rtc_irq_reg_shift[ESP_NIRQ_RTCIO] = +{ + RTC_CNTL_SLP_WAKEUP_INT_ENA_S, + RTC_CNTL_SLP_REJECT_INT_ENA_S, + RTC_CNTL_WDT_INT_ENA_S, + RTC_CNTL_BROWN_OUT_INT_ENA_S, + RTC_CNTL_MAIN_TIMER_INT_ENA_S, + RTC_CNTL_SWD_INT_ENA_S, + RTC_CNTL_XTAL32K_DEAD_INT_ENA_S, + RTC_CNTL_GLITCH_DET_INT_ENA_S, + RTC_CNTL_BBPLL_CAL_INT_ENA_S +}; +#define RTC_IRQ_REG_SHIFT(x) rtc_irq_reg_shift[x] +#endif /* CONFIG_ARCH_CHIP_ESP32C3 */ +#endif /* CONFIG_ESPRESSIF_RTCIO_IRQ */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rtcio_dispatch + * + * Description: + * Second level dispatch for the RTC interrupt. + * + * Input Parameters: + * irq - The IRQ number; + * reg_status - Pointer to a copy of the interrupt status register. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_RTCIO_IRQ +static void rtcio_dispatch(int irq, uint32_t *reg_status) +{ + uint32_t status = *reg_status; + uint32_t mask; + int i; + + /* Check each bit in the status register */ + + for (i = 0; i < ESP_NIRQ_RTCIO && status != 0; i++) + { + /* Check if there is an interrupt pending for this type */ + + mask = (UINT32_C(1) << RTC_IRQ_REG_SHIFT(i)); + if ((status & mask) != 0) + { + /* Yes... perform the second level dispatch. The IRQ context will + * contain the contents of the status register. + */ + + irq_dispatch(irq + i, (void *)reg_status); + + /* Clear the bit in the status so that we might execute this loop + * sooner. + */ + + status &= ~mask; + } + } +} + +/**************************************************************************** + * Name: rtcio_interrupt + * + * Description: + * RTC interrupt handler. + * + * Input Parameters: + * irq - The IRQ number; + * context - The interrupt context; + * args - The arguments passed to the handler. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +static int rtcio_interrupt(int irq, void *context, void *arg) +{ + /* Read and clear the lower RTC interrupt status */ + + last_status = getreg32(RTC_CNTL_INT_ST_REG); + putreg32(last_status, RTC_CNTL_INT_CLR_REG); + + /* Dispatch pending interrupts in the RTC status register */ + + rtcio_dispatch(ESP_FIRST_RTCIOIRQ, &last_status); + + return OK; +} +#endif /* CONFIG_ESPRESSIF_RTCIO_IRQ */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_rtcioirqinitialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * RTC IRQs. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_RTCIO_IRQ +void esp_rtcioirqinitialize(void) +{ + /* Setup the RTCIO interrupt. */ + + g_rtcio_cpuint = esp_setup_irq(ETS_RTC_CORE_INTR_SOURCE, + 1, ESP_IRQ_TRIGGER_LEVEL); + DEBUGASSERT(g_rtcio_cpuint >= 0); + + /* Attach and enable the interrupt handler */ + + DEBUGVERIFY(irq_attach(ESP_IRQ_RTC_CORE, rtcio_interrupt, NULL)); + up_enable_irq(ESP_IRQ_RTC_CORE); +} + +/**************************************************************************** + * Name: esp_rtcioirqenable + * + * Description: + * Enable the interrupt for the specified RTC peripheral IRQ. + * + * Input Parameters: + * irq - The IRQ number. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_rtcioirqenable(int irq) +{ + uintptr_t regaddr = RTC_CNTL_INT_ENA_REG; + uint32_t regval; + int bit; + + DEBUGASSERT(irq >= ESP_FIRST_RTCIOIRQ && + irq <= ESP_LAST_RTCIOIRQ); + + /* Convert the IRQ number to the corresponding bit */ + + bit = RTC_IRQ_REG_SHIFT(irq - ESP_FIRST_RTCIOIRQ); + + /* Get the address of the GPIO PIN register for this pin */ + + up_disable_irq(ESP_IRQ_RTC_CORE); + + regval = getreg32(regaddr) | (UINT32_C(1) << bit); + putreg32(regval, regaddr); + + up_enable_irq(ESP_IRQ_RTC_CORE); +} + +/**************************************************************************** + * Name: esp_rtcioirqdisable + * + * Description: + * Disable the interrupt for the specified RTC peripheral IRQ. + * + * Input Parameters: + * irq - The IRQ number. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_rtcioirqdisable(int irq) +{ + uintptr_t regaddr = RTC_CNTL_INT_ENA_REG; + uint32_t regval; + int bit; + + DEBUGASSERT(irq >= ESP_FIRST_RTCIOIRQ && + irq <= ESP_LAST_RTCIOIRQ); + + /* Convert the IRQ number to the corresponding bit */ + + bit = RTC_IRQ_REG_SHIFT(irq - ESP_FIRST_RTCIOIRQ); + + /* Disable IRQ */ + + up_disable_irq(ESP_IRQ_RTC_CORE); + + regval = getreg32(regaddr) & (~(UINT32_C(1) << bit)); + putreg32(regval, regaddr); + + up_enable_irq(ESP_IRQ_RTC_CORE); +} +#endif /* CONFIG_ESPRESSIF_RTCIO_IRQ */ +#endif /* CONFIG_ARCH_CHIP_ESP32C3_GENERIC */ diff --git a/arch/risc-v/src/common/espressif/esp_rtc_gpio.h b/arch/risc-v/src/common/espressif/esp_rtc_gpio.h new file mode 100644 index 0000000000000..81535aa71f536 --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_rtc_gpio.h @@ -0,0 +1,113 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_rtc_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISC_V_SRC_COMMON_ESPRESSIF_ESP_RTC_GPIO_H +#define __ARCH_RISC_V_SRC_COMMON_ESPRESSIF_ESP_RTC_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_rtcioirqinitialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * RTC IRQs. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_RTCIO_IRQ +void esp_rtcioirqinitialize(void); +#else +# define esp_rtcioirqinitialize() +#endif + +/**************************************************************************** + * Name: esp_rtcioirqenable + * + * Description: + * Enable the interrupt for the specified RTC peripheral IRQ. + * + * Input Parameters: + * irq - The IRQ number. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_RTCIO_IRQ +void esp_rtcioirqenable(int irq); +#else +# define esp_rtcioirqenable(irq) +#endif + +/**************************************************************************** + * Name: esp_rtcioirqdisable + * + * Description: + * Disable the interrupt for the specified RTC peripheral IRQ. + * + * Input Parameters: + * irq - The IRQ number. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_RTCIO_IRQ +void esp_rtcioirqdisable(int irq); +#else +# define esp_rtcioirqdisable(irq) +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISC_V_SRC_COMMON_ESPRESSIF_ESP_RTC_GPIO_H */ diff --git a/arch/risc-v/src/espressif/esp_serial.c b/arch/risc-v/src/common/espressif/esp_serial.c similarity index 99% rename from arch/risc-v/src/espressif/esp_serial.c rename to arch/risc-v/src/common/espressif/esp_serial.c index 61dd3f80891c7..51c022c960695 100644 --- a/arch/risc-v/src/espressif/esp_serial.c +++ b/arch/risc-v/src/common/espressif/esp_serial.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_serial.c + * arch/risc-v/src/common/espressif/esp_serial.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/common/espressif/esp_spiflash.c b/arch/risc-v/src/common/espressif/esp_spiflash.c new file mode 100644 index 0000000000000..3d2b92e00aaf7 --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_spiflash.c @@ -0,0 +1,617 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_spiflash.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include "riscv_internal.h" +#include "riscv/rv_utils.h" + +#include +#include +#include "esp_spiflash.h" +#include "esp_attr.h" +#include "memspi_host_driver.h" +#include "spi_flash_defs.h" +#include "hal/spimem_flash_ll.h" +#include "hal/spi_flash_ll.h" +#include "esp_rom_spiflash.h" +#include "esp_irq.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_ESPRESSIF_SPI_FLASH_USE_ROM_CODE +/* SPI buffer size */ + +# define SPI_BUFFER_WORDS (16) +# define SPI_BUFFER_BYTES (SPI_BUFFER_WORDS * 4) + +/* SPI flash hardware definition */ + +# define FLASH_SECTOR_SIZE (4096) + +/* SPI flash SR1 bits */ + +# define FLASH_SR1_BUSY ESP_ROM_SPIFLASH_BUSY_FLAG +# define FLASH_SR1_WREN ESP_ROM_SPIFLASH_WRENABLE_FLAG + +/* SPI flash operation */ + +# define FLASH_CMD_WRDI CMD_WRDI +# define FLASH_CMD_WREN CMD_WREN +# define FLASH_CMD_RDSR CMD_RDSR +#ifdef CONFIG_ESPRESSIF_SPI_FLASH_USE_32BIT_ADDRESS +# define ADDR_BITS(addr) (((addr) & 0xff000000) ? 32 : 24) +# define READ_CMD(addr) (ADDR_BITS(addr) == 32 ? \ + CMD_FASTRD_4B : CMD_FASTRD) +# define WRITE_CMD(addr) (ADDR_BITS(addr) == 32 ? CMD_PROGRAM_PAGE_4B : \ + CMD_PROGRAM_PAGE) +# define ERASE_CMD(addr) (ADDR_BITS(addr) == 32 ? CMD_SECTOR_ERASE_4B : \ + CMD_SECTOR_ERASE) +# define READ_DUMMY(addr) (8) +#else +# define ADDR_BITS(addr) (24) +# define READ_CMD(addr) CMD_FASTRD +# define WRITE_CMD(addr) CMD_PROGRAM_PAGE +# define ERASE_CMD(addr) CMD_SECTOR_ERASE +# define READ_DUMMY(addr) (8) +#endif + +# define SEND_CMD8_TO_FLASH(cmd) \ + esp_spi_trans((cmd), 8, \ + 0, 0, \ + NULL, 0, \ + NULL, 0, \ + 0) + +# define READ_SR1_FROM_FLASH(cmd, status) \ + esp_spi_trans((cmd), 8, \ + 0, 0, \ + NULL, 0, \ + (status), 1, \ + 0) + +# define ERASE_FLASH_SECTOR(addr) \ + esp_spi_trans(ERASE_CMD(addr), 8, \ + (addr), ADDR_BITS(addr), \ + NULL, 0, \ + NULL, 0, \ + 0) + +# define WRITE_DATA_TO_FLASH(addr, buffer, size) \ + esp_spi_trans(WRITE_CMD(addr), 8, \ + (addr), ADDR_BITS(addr), \ + buffer, size, \ + NULL, 0, \ + 0) + +# define READ_DATA_FROM_FLASH(addr, buffer, size) \ + esp_spi_trans(READ_CMD(addr), 8, \ + (addr), ADDR_BITS(addr), \ + NULL, 0, \ + buffer, size, \ + READ_DUMMY(addr)) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +spi_mem_dev_t *dev = spimem_flash_ll_get_hw(SPI1_HOST); +#endif /* CONFIG_ESPRESSIF_SPI_FLASH_USE_ROM_CODE */ + +/**************************************************************************** + * Private Functions Declaration + ****************************************************************************/ + +static void spiflash_start(void); +static void spiflash_end(void); +#ifndef CONFIG_ESPRESSIF_SPI_FLASH_USE_ROM_CODE +extern bool spi_flash_check_and_flush_cache(size_t start_addr, + size_t length); +#endif /* CONFIG_ESPRESSIF_SPI_FLASH_USE_ROM_CODE */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct spiflash_guard_funcs g_spi_flash_guard_funcs = +{ + .start = spiflash_start, + .end = spiflash_end, + .op_lock = NULL, + .op_unlock = NULL, + .address_is_safe = NULL, + .yield = NULL, +}; + +static mutex_t s_flash_op_mutex; +static uint32_t s_flash_op_cache_state[CONFIG_ESPRESSIF_NUM_CPUS]; +static volatile bool s_sched_suspended[CONFIG_ESPRESSIF_NUM_CPUS]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: spiflash_start + * + * Description: + * Prepare for an SPIFLASH operation. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static IRAM_ATTR void spiflash_start(void) +{ + extern uint32_t cache_suspend_icache(void); + int cpu; + irqstate_t flags; + uint32_t regval; + + nxmutex_lock(&s_flash_op_mutex); + flags = enter_critical_section(); + cpu = up_cpu_index(); + s_sched_suspended[cpu] = true; + + esp_intr_noniram_disable(); + + s_flash_op_cache_state[cpu] = cache_suspend_icache() << 16; + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: spiflash_end + * + * Description: + * Undo all the steps of opstart. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static IRAM_ATTR void spiflash_end(void) +{ + extern void cache_resume_icache(uint32_t); + extern void cache_invalidate_icache_all(void); + + int cpu; + irqstate_t flags; + + flags = enter_critical_section(); + + cpu = up_cpu_index(); + + cache_invalidate_icache_all(); + cache_resume_icache(s_flash_op_cache_state[cpu] >> 16); + + esp_intr_noniram_enable(); + s_sched_suspended[cpu] = false; + + leave_critical_section(flags); + nxmutex_unlock(&s_flash_op_mutex); +} + +/**************************************************************************** + * Name: esp_spi_trans + * + * Description: + * Transmit given command, address and data. + * + * Input Parameters: + * command - command value + * command_bits - command bits + * address - address value + * address_bits - address bits + * tx_buffer - write buffer + * tx_bytes - write buffer size + * rx_buffer - read buffer + * rx_bytes - read buffer size + * dummy_bits - dummy bits + * + * Returned Value: + * 0 if success or a negative value if fail. + * + ****************************************************************************/ + +#ifndef CONFIG_ESPRESSIF_SPI_FLASH_USE_ROM_CODE +static IRAM_ATTR void esp_spi_trans(uint32_t command, + uint32_t command_bits, + uint32_t address, + uint32_t address_bits, + uint32_t *tx_buffer, + uint32_t tx_bytes, + uint32_t *rx_buffer, + uint32_t rx_bytes, + uint32_t dummy_bits) +{ + /* Initiliaze SPI user register */ + + spi_flash_ll_reset(dev); + + while (!spi_flash_ll_host_idle(dev)); + + /* Set command bits and value, and command is always needed */ + + spi_flash_ll_set_command(dev, command, command_bits); + + /* Set address bits and value */ + + if (address_bits) + { + spi_flash_ll_set_addr_bitlen(dev, address_bits); + spi_flash_ll_set_address(dev, address); + } + + /* Set dummy */ + + if (dummy_bits) + { + spi_flash_ll_set_dummy(dev, dummy_bits); + } + + /* Set TX data */ + + if (tx_bytes) + { + spi_flash_ll_set_mosi_bitlen(dev, tx_bytes * 8); + spi_flash_ll_set_buffer_data(dev, tx_buffer, tx_bytes); + } + + /* Set RX data */ + + if (rx_bytes) + { + spi_flash_ll_set_miso_bitlen(dev, rx_bytes * 8); + } + + /* Set I/O mode */ + + spi_flash_ll_set_read_mode(dev, SPI_FLASH_FASTRD); + + /* Set clock and delay */ + + spimem_flash_ll_suspend_cmd_setup(dev, 0); + + /* Start transmision */ + + spi_flash_ll_user_start(dev); + + /* Wait until transmission is done */ + + while (!spi_flash_ll_cmd_is_done(dev)); + + /* Get read data */ + + if (rx_bytes) + { + spi_flash_ll_get_buffer_data(dev, rx_buffer, rx_bytes); + } +} + +/**************************************************************************** + * Name: wait_flash_idle + * + * Description: + * Wait until flash enters idle state + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static IRAM_ATTR void wait_flash_idle(void) +{ + uint32_t status; + + do + { + READ_SR1_FROM_FLASH(FLASH_CMD_RDSR, &status); + if ((status & FLASH_SR1_BUSY) == 0) + { + break; + } + } + while (1); +} + +/**************************************************************************** + * Name: enable_flash_write + * + * Description: + * Enable Flash write mode + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static IRAM_ATTR void enable_flash_write(void) +{ + uint32_t status; + + do + { + SEND_CMD8_TO_FLASH(FLASH_CMD_WREN); + READ_SR1_FROM_FLASH(FLASH_CMD_RDSR, &status); + + if ((status & FLASH_SR1_WREN) != 0) + { + break; + } + } + while (1); +} + +/**************************************************************************** + * Name: disable_flash_write + * + * Description: + * Disable Flash write mode + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static IRAM_ATTR void disable_flash_write(void) +{ + uint32_t status; + + do + { + SEND_CMD8_TO_FLASH(FLASH_CMD_WRDI); + READ_SR1_FROM_FLASH(FLASH_CMD_RDSR, &status); + + if ((status & FLASH_SR1_WREN) == 0) + { + break; + } + } + while (1); +} + +/**************************************************************************** + * Name: spi_flash_read + * + * Description: + * Read data from Flash. + * + * Parameters: + * address - source address of the data in Flash. + * buffer - pointer to the destination buffer + * length - length of data + * + * Returned Values: + * Zero (OK) is returned or a negative error. + * + ****************************************************************************/ + +IRAM_ATTR int spi_flash_read(uint32_t address, void *buffer, uint32_t length) +{ + int ret = OK; + uint8_t *rx_buf = (uint8_t *)buffer; + uint32_t rx_bytes = length; + uint32_t rx_addr = address; + + spiflash_start(); + + for (uint32_t i = 0; i < length; i += SPI_BUFFER_BYTES) + { + uint32_t spi_buffer[SPI_BUFFER_WORDS]; + uint32_t n = MIN(rx_bytes, SPI_BUFFER_BYTES); + + READ_DATA_FROM_FLASH(rx_addr, spi_buffer, n); + + memcpy(rx_buf, spi_buffer, n); + rx_bytes -= n; + rx_buf += n; + rx_addr += n; + } + + spiflash_end(); + + return ret; +} + +/**************************************************************************** + * Name: spi_flash_erase_sector + * + * Description: + * Erase the Flash sector. + * + * Parameters: + * sector - Sector number, the count starts at sector 0, 4KB per sector. + * + * Returned Values: esp_err_t + * Zero (OK) is returned or a negative error. + * + ****************************************************************************/ + +IRAM_ATTR int spi_flash_erase_sector(uint32_t sector) +{ + int ret = OK; + uint32_t addr = sector * FLASH_SECTOR_SIZE; + + spiflash_start(); + + wait_flash_idle(); + enable_flash_write(); + + ERASE_FLASH_SECTOR(addr); + + wait_flash_idle(); + disable_flash_write(); + + spiflash_end(); + + return ret; +} + +/**************************************************************************** + * Name: spi_flash_erase_range + * + * Description: + * Erase a range of flash sectors + * + * Parameters: + * start_address - Address where erase operation has to start. + * Must be 4kB-aligned + * size - Size of erased range, in bytes. Must be divisible by + * 4kB. + * + * Returned Values: + * Zero (OK) is returned or a negative error. + * + ****************************************************************************/ + +IRAM_ATTR int spi_flash_erase_range(uint32_t start_address, uint32_t size) +{ + int ret = OK; + uint32_t addr = start_address; + + spiflash_start(); + + for (uint32_t i = 0; i < size; i += FLASH_SECTOR_SIZE) + { + wait_flash_idle(); + enable_flash_write(); + + ERASE_FLASH_SECTOR(addr); + addr += FLASH_SECTOR_SIZE; + } + + wait_flash_idle(); + disable_flash_write(); + spi_flash_check_and_flush_cache(start_address, size); + + spiflash_end(); + + return ret; +} + +/**************************************************************************** + * Name: spi_flash_write + * + * Description: + * Write data to Flash. + * + * Parameters: + * dest_addr - Destination address in Flash. + * buffer - Pointer to the source buffer. + * size - Length of data, in bytes. + * + * Returned Values: + * Zero (OK) is returned or a negative error. + * + ****************************************************************************/ + +IRAM_ATTR int spi_flash_write(uint32_t dest_addr, + const void *buffer, + uint32_t size) +{ + int ret = OK; + const uint8_t *tx_buf = (const uint8_t *)buffer; + uint32_t tx_bytes = size; + uint32_t tx_addr = dest_addr; + + spiflash_start(); + + for (int i = 0; i < size; i += SPI_BUFFER_BYTES) + { + uint32_t spi_buffer[SPI_BUFFER_WORDS]; + uint32_t n = MIN(tx_bytes, SPI_BUFFER_BYTES); + + memcpy(spi_buffer, tx_buf, n); + + wait_flash_idle(); + enable_flash_write(); + + WRITE_DATA_TO_FLASH(tx_addr, spi_buffer, n); + + tx_bytes -= n; + tx_buf += n; + tx_addr += n; + } + + wait_flash_idle(); + disable_flash_write(); + spi_flash_check_and_flush_cache(dest_addr, size); + + spiflash_end(); + + return ret; +} +#endif /* CONFIG_ESPRESSIF_SPI_FLASH_USE_ROM_CODE */ + +/**************************************************************************** + * Name: esp_spiflash_init + * + * Description: + * Initialize ESP SPI flash driver. + * + * Input Parameters: + * None. + * + * Returned Value: + * OK if success or a negative value if fail. + * + ****************************************************************************/ + +int esp_spiflash_init(void) +{ + extern void spi_flash_guard_set(const struct spiflash_guard_funcs *); + + nxmutex_init(&s_flash_op_mutex); + + spi_flash_guard_set(&g_spi_flash_guard_funcs); + + return OK; +} diff --git a/arch/risc-v/src/common/espressif/esp_spiflash.h b/arch/risc-v/src/common/espressif/esp_spiflash.h new file mode 100644 index 0000000000000..0aedef7f5125d --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_spiflash.h @@ -0,0 +1,188 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_spiflash.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_SPIFLASH_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_SPIFLASH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/** + * Structure holding SPI flash access critical sections management functions. + * + * Flash API uses two types of functions for flash access management: + * 1) Functions which prepare/restore flash cache and interrupts before + * calling appropriate ROM functions (spi_flash_write, spi_flash_read, + * spi_flash_erase_sector and spi_flash_erase_range): + * - 'start' function should disable flash cache and non-IRAM interrupts + * and is invoked before the call to one of ROM functions from + * "struct spiflash_guard_funcs". + * - 'end' function should restore state of flash cache and non-IRAM + * interrupts and is invoked after the call to one of ROM + * functions from "struct spiflash_guard_funcs". + * These two functions are not reentrant. + * 2) Functions which synchronizes access to internal data used by flash API. + * These functions are mostly intended to synchronize access to flash API + * internal data in multithreaded environment and use OS primitives: + * - 'op_lock' locks access to flash API internal data. + * - 'op_unlock' unlocks access to flash API internal data. + * These two functions are reentrant and can be used around the outside of + * multiple calls to 'start' & 'end', in order to create atomic multi-part + * flash operations. + * + * Structure and corresponding guard functions should not reside + * in flash. For example structure can be placed in DRAM and functions + * in IRAM sections. + */ + +struct spiflash_guard_funcs +{ + void (*start)(void); /* critical section start function */ + void (*end)(void); /* critical section end function */ + void (*op_lock)(void); /* flash access API lock function */ + void (*op_unlock)(void); /* flash access API unlock function */ + + /* checks flash write addresses */ + + bool (*address_is_safe)(size_t addr, size_t size); + + void (*yield)(void); /* yield to the OS during flash erase */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: spi_flash_read + * + * Description: + * Read data from Flash. + * + * Parameters: + * address - source address of the data in Flash. + * buffer - pointer to the destination buffer + * length - length of data + * + * Returned Values: + * Zero (OK) is returned or a negative error. + * + ****************************************************************************/ + +int spi_flash_read(uint32_t address, void *buffer, uint32_t length); + +/**************************************************************************** + * Name: spi_flash_erase_sector + * + * Description: + * Erase the Flash sector. + * + * Parameters: + * sector - Sector number, the count starts at sector 0, 4KB per sector. + * + * Returned Values: esp_err_t + * Zero (OK) is returned or a negative error. + * + ****************************************************************************/ + +int spi_flash_erase_sector(uint32_t sector); + +/**************************************************************************** + * Name: spi_flash_erase_range + * + * Description: + * Erase a range of flash sectors + * + * Parameters: + * start_address - Address where erase operation has to start. + * Must be 4kB-aligned + * size - Size of erased range, in bytes. Must be divisible by + * 4kB. + * + * Returned Values: + * Zero (OK) is returned or a negative error. + * + ****************************************************************************/ + +int spi_flash_erase_range(uint32_t start_address, uint32_t size); + +/**************************************************************************** + * Name: spi_flash_write + * + * Description: + * Write data to Flash. + * + * Parameters: + * dest_addr - Destination address in Flash. + * src - Pointer to the source buffer. + * size - Length of data, in bytes. + * + * Returned Values: + * Zero (OK) is returned or a negative error. + * + ****************************************************************************/ + +int spi_flash_write(uint32_t dest_addr, const void *buffer, uint32_t size); + +/**************************************************************************** + * Name: esp_spiflash_init + * + * Description: + * Initialize ESP SPI flash driver. + * + * Input Parameters: + * None. + * + * Returned Value: + * OK if success or a negative value if fail. + * + ****************************************************************************/ + +int esp_spiflash_init(void); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_SPIFLASH_H */ diff --git a/arch/risc-v/src/common/espressif/esp_spiflash_mtd.c b/arch/risc-v/src/common/espressif/esp_spiflash_mtd.c new file mode 100644 index 0000000000000..bd033bc30fbe3 --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_spiflash_mtd.c @@ -0,0 +1,540 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_spiflash_mtd.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "esp_attr.h" +#include "esp_spiflash.h" +#include "esp_rom_spiflash.h" +#include "esp_rom_spiflash_defs.h" +#include "esp_spiflash_mtd.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MTD_BLK_SIZE CONFIG_ESPRESSIF_SPIFLASH_MTD_BLKSIZE +#define MTD_ERASE_SIZE 4096 +#define MTD_ERASED_STATE (0xff) + +#define MTD2PRIV(_dev) ((struct esp_mtd_dev_s *)_dev) +#define MTD_SIZE(_priv) ((*(_priv)->data)->chip.chip_size) +#define MTD_BLK2SIZE(_priv, _b) (MTD_BLK_SIZE * (_b)) +#define MTD_SIZE2BLK(_priv, _s) ((_s) / MTD_BLK_SIZE) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* ESP SPI Flash device private data */ + +struct esp_mtd_dev_s +{ + struct mtd_dev_s mtd; + + /* SPI Flash data */ + + const esp_rom_spiflash_legacy_data_t **data; +}; + +/**************************************************************************** + * Private Functions Prototypes + ****************************************************************************/ + +/* MTD driver methods */ + +static int esp_erase(struct mtd_dev_s *dev, off_t startblock, + size_t nblocks); +static ssize_t esp_read(struct mtd_dev_s *dev, off_t offset, + size_t nbytes, uint8_t *buffer); +static ssize_t esp_bread(struct mtd_dev_s *dev, off_t startblock, + size_t nblocks, uint8_t *buffer); +static ssize_t esp_write(struct mtd_dev_s *dev, off_t offset, + size_t nbytes, const uint8_t *buffer); +static ssize_t esp_bwrite(struct mtd_dev_s *dev, off_t startblock, + size_t nblocks, const uint8_t *buffer); +static int esp_ioctl(struct mtd_dev_s *dev, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct esp_mtd_dev_s g_esp_spiflash = +{ + .mtd = + { + .erase = esp_erase, + .bread = esp_bread, + .bwrite = esp_bwrite, + .read = esp_read, + .ioctl = esp_ioctl, +#ifdef CONFIG_MTD_BYTE_WRITE + .write = esp_write, +#endif + .name = "esp_spiflash" + }, + .data = (const esp_rom_spiflash_legacy_data_t **)&rom_spiflash_legacy_data, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_erase + * + * Description: + * Erase SPI Flash designated sectors. + * + * Input Parameters: + * dev - MTD device data + * startblock - start block number, it is not equal to SPI Flash's block + * nblocks - Number of blocks + * + * Returned Value: + * Erased blocks if success or a negative value if fail. + * + ****************************************************************************/ + +static int esp_erase(struct mtd_dev_s *dev, off_t startblock, + size_t nblocks) +{ + ssize_t ret; + uint32_t offset = startblock * MTD_ERASE_SIZE; + uint32_t nbytes = nblocks * MTD_ERASE_SIZE; + struct esp_mtd_dev_s *priv = (struct esp_mtd_dev_s *)dev; + irqstate_t flags; + + if ((offset > MTD_SIZE(priv)) || ((offset + nbytes) > MTD_SIZE(priv))) + { + return -EINVAL; + } + +#ifdef CONFIG_ESPRESSIF_STORAGE_MTD_DEBUG + finfo("%s(%p, 0x%x, %d)\n", __func__, dev, startblock, nblocks); + + finfo("spi_flash_erase_range(0x%x, %d)\n", offset, nbytes); +#endif + + flags = enter_critical_section(); + ret = spi_flash_erase_range(offset, nbytes); + leave_critical_section(flags); + + if (ret == OK) + { + ret = nblocks; + } + else + { +#ifdef CONFIG_ESPRESSIF_STORAGE_MTD_DEBUG + finfo("Failed to erase the flash range!\n"); +#endif + ret = -1; + } + +#ifdef CONFIG_ESPRESSIF_STORAGE_MTD_DEBUG + finfo("%s()=%d\n", __func__, ret); +#endif + + return ret; +} + +/**************************************************************************** + * Name: esp_read + * + * Description: + * Read data from SPI Flash at designated address. + * + * Input Parameters: + * dev - MTD device data + * offset - target address offset + * nbytes - data number + * buffer - data buffer pointer + * + * Returned Value: + * Read data bytes if success or a negative value if fail. + * + ****************************************************************************/ + +static ssize_t esp_read(struct mtd_dev_s *dev, off_t offset, + size_t nbytes, uint8_t *buffer) +{ + ssize_t ret; + irqstate_t flags; + +#ifdef CONFIG_ESPRESSIF_STORAGE_MTD_DEBUG + finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, offset, nbytes, buffer); + + finfo("spi_flash_read(0x%x, %p, %d)\n", offset, buffer, nbytes); +#endif + + flags = enter_critical_section(); + ret = spi_flash_read(offset, (uint32_t *)buffer, nbytes); + leave_critical_section(flags); + + if (ret == OK) + { + ret = nbytes; + } + +#ifdef CONFIG_ESPRESSIF_STORAGE_MTD_DEBUG + finfo("%s()=%d\n", __func__, ret); +#endif + + return ret; +} + +/**************************************************************************** + * Name: esp_bread + * + * Description: + * Read data from designated blocks. + * + * Input Parameters: + * dev - MTD device data + * startblock - start block number, it is not equal to SPI Flash's block + * nblocks - blocks number + * buffer - data buffer pointer + * + * Returned Value: + * Read block number if success or a negative value if fail. + * + ****************************************************************************/ + +static ssize_t esp_bread(struct mtd_dev_s *dev, off_t startblock, + size_t nblocks, uint8_t *buffer) +{ + ssize_t ret; + uint32_t addr = startblock * MTD_BLK_SIZE; + uint32_t size = nblocks * MTD_BLK_SIZE; + irqstate_t flags; + +#ifdef CONFIG_ESPRESSIF_STORAGE_MTD_DEBUG + finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, startblock, nblocks, + buffer); + + finfo("spi_flash_read(0x%x, %p, %d)\n", addr, buffer, size); +#endif + + flags = enter_critical_section(); + ret = spi_flash_read(addr, (uint32_t *)buffer, size); + leave_critical_section(flags); + + if (ret == OK) + { + ret = nblocks; + } + +#ifdef CONFIG_ESPRESSIF_STORAGE_MTD_DEBUG + finfo("%s()=%d\n", __func__, ret); +#endif + + return ret; +} + +/**************************************************************************** + * Name: esp_write + * + * Description: + * write data to SPI Flash at designated address. + * + * Input Parameters: + * dev - MTD device data + * offset - target address offset + * nbytes - data number + * buffer - data buffer pointer + * + * Returned Value: + * Writen bytes if success or a negative value if fail. + * + ****************************************************************************/ + +static ssize_t esp_write(struct mtd_dev_s *dev, off_t offset, + size_t nbytes, const uint8_t *buffer) +{ + ssize_t ret; + struct esp_mtd_dev_s *priv = (struct esp_mtd_dev_s *)dev; + irqstate_t flags; + + ASSERT(buffer); + + if ((offset > MTD_SIZE(priv)) || ((offset + nbytes) > MTD_SIZE(priv))) + { + return -EINVAL; + } + +#ifdef CONFIG_ESPRESSIF_STORAGE_MTD_DEBUG + finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, offset, nbytes, buffer); + + finfo("spi_flash_write(0x%x, %p, %d)\n", offset, buffer, nbytes); +#endif + + flags = enter_critical_section(); + ret = spi_flash_write(offset, (uint32_t *)buffer, nbytes); + leave_critical_section(flags); + + if (ret == OK) + { + ret = nbytes; + } + +#ifdef CONFIG_ESPRESSIF_STORAGE_MTD_DEBUG + finfo("%s()=%d\n", __func__, ret); +#endif + + return ret; +} + +/**************************************************************************** + * Name: esp_bwrite + * + * Description: + * Write data to designated blocks. + * + * Input Parameters: + * dev - MTD device data + * startblock - start MTD block number, + * it is not equal to SPI Flash's block + * nblocks - blocks number + * buffer - data buffer pointer + * + * Returned Value: + * Writen block number if success or a negative value if fail. + * + ****************************************************************************/ + +static ssize_t esp_bwrite(struct mtd_dev_s *dev, off_t startblock, + size_t nblocks, const uint8_t *buffer) +{ + ssize_t ret; + uint32_t addr = startblock * MTD_BLK_SIZE; + uint32_t size = nblocks * MTD_BLK_SIZE; + irqstate_t flags; + +#ifdef CONFIG_ESPRESSIF_STORAGE_MTD_DEBUG + finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, startblock, + nblocks, buffer); + + finfo("spi_flash_write(0x%x, %p, %d)\n", addr, buffer, size); +#endif + + flags = enter_critical_section(); + ret = spi_flash_write(addr, (uint32_t *)buffer, size); + leave_critical_section(flags); + + if (ret == OK) + { + ret = nblocks; + } + +#ifdef CONFIG_ESPRESSIF_STORAGE_MTD_DEBUG + finfo("%s()=%d\n", __func__, ret); +#endif + + return ret; +} + +/**************************************************************************** + * Name: esp_ioctl + * + * Description: + * Set/Get option to/from ESP SPI Flash MTD device data. + * + * Input Parameters: + * dev - ESP MTD device data + * cmd - operation command + * arg - operation argument + * + * Returned Value: + * 0 if success or a negative value if fail. + * + ****************************************************************************/ + +static int esp_ioctl(struct mtd_dev_s *dev, int cmd, + unsigned long arg) +{ + int ret = OK; + finfo("cmd: %d\n", cmd); + + switch (cmd) + { + case MTDIOC_GEOMETRY: + { + struct esp_mtd_dev_s *priv = (struct esp_mtd_dev_s *)dev; + struct mtd_geometry_s *geo = (struct mtd_geometry_s *)arg; + if (geo) + { + memset(geo, 0, sizeof(*geo)); + + geo->blocksize = MTD_BLK_SIZE; + geo->erasesize = MTD_ERASE_SIZE; + geo->neraseblocks = MTD_SIZE(priv) / MTD_ERASE_SIZE; + ret = OK; + + finfo("blocksize: %" PRId32 " erasesize: %" PRId32 \ + " neraseblocks: %" PRId32 "\n", + geo->blocksize, geo->erasesize, geo->neraseblocks); + } + } + break; + + case BIOC_PARTINFO: + { + struct esp_mtd_dev_s *priv = (struct esp_mtd_dev_s *)dev; + struct partition_info_s *info = (struct partition_info_s *)arg; + if (info != NULL) + { + info->numsectors = MTD_SIZE(priv) / MTD_BLK_SIZE; + info->sectorsize = MTD_BLK_SIZE; + info->startsector = 0; + info->parent[0] = '\0'; + } + } + break; + + case MTDIOC_ERASESTATE: + { + uint8_t *result = (uint8_t *)arg; + *result = MTD_ERASED_STATE; + + ret = OK; + } + break; + + default: + ret = -ENOTTY; + break; + } + + finfo("return %d\n", ret); + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_spiflash_alloc_mtdpart + * + * Description: + * Allocate an MTD partition from the ESP SPI Flash. + * + * Input Parameters: + * mtd_offset - MTD Partition offset from the base address in SPI Flash. + * mtd_size - Size for the MTD partition. + * + * Returned Value: + * ESP SPI Flash MTD data pointer if success or NULL if fail. + * + ****************************************************************************/ + +struct mtd_dev_s *esp_spiflash_alloc_mtdpart(uint32_t mtd_offset, + uint32_t mtd_size) +{ + const struct esp_mtd_dev_s *priv; + const esp_rom_spiflash_chip_t *chip; + struct mtd_dev_s *mtd_part; + uint32_t blocks; + uint32_t startblock; + uint32_t size; + + priv = &g_esp_spiflash; + + chip = &(*priv->data)->chip; + + finfo("ESP SPI Flash information:\n"); + finfo("\tID = 0x%" PRIx32 "\n", chip->device_id); + finfo("\tStatus mask = 0x%" PRIx32 "\n", chip->status_mask); + finfo("\tChip size = %" PRId32 " KB\n", chip->chip_size / 1024); + finfo("\tPage size = %" PRId32 " B\n", chip->page_size); + finfo("\tSector size = %" PRId32 " KB\n", chip->sector_size / 1024); + finfo("\tBlock size = %" PRId32 " KB\n", chip->block_size / 1024); + + ASSERT((mtd_offset + mtd_size) <= chip->chip_size); + ASSERT((mtd_offset % chip->sector_size) == 0); + ASSERT((mtd_size % chip->sector_size) == 0); + + if (mtd_size == 0) + { + size = chip->chip_size - mtd_offset; + } + else + { + size = mtd_size; + } + + finfo("\tMTD offset = 0x%" PRIx32 "\n", mtd_offset); + finfo("\tMTD size = 0x%" PRIx32 "\n", size); + + startblock = MTD_SIZE2BLK(priv, mtd_offset); + blocks = MTD_SIZE2BLK(priv, size); + + mtd_part = mtd_partition((struct mtd_dev_s *)&priv->mtd, startblock, + blocks); + if (!mtd_part) + { + ferr("ERROR: Failed to create MTD partition\n"); + return NULL; + } + + return mtd_part; +} + +/**************************************************************************** + * Name: esp_spiflash_mtd + * + * Description: + * Get SPI Flash MTD. + * + * Input Parameters: + * None + * + * Returned Value: + * ESP SPI Flash MTD pointer. + * + ****************************************************************************/ + +struct mtd_dev_s *esp_spiflash_mtd(void) +{ + struct esp_mtd_dev_s *priv = + (struct esp_mtd_dev_s *)&g_esp_spiflash; + + return &priv->mtd; +} diff --git a/arch/risc-v/src/common/espressif/esp_spiflash_mtd.h b/arch/risc-v/src/common/espressif/esp_spiflash_mtd.h new file mode 100644 index 0000000000000..83946835d5f27 --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_spiflash_mtd.h @@ -0,0 +1,89 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_spiflash_mtd.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_SPIFLASH_MTD_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_SPIFLASH_MTD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_spiflash_mtd + * + * Description: + * Get SPI Flash MTD. + * + * Input Parameters: + * None + * + * Returned Value: + * SPI Flash MTD pointer. + * + ****************************************************************************/ + +struct mtd_dev_s *esp_spiflash_mtd(void); + +/**************************************************************************** + * Name: esp_spiflash_alloc_mtdpart + * + * Description: + * Allocate an MTD partition from the SPI Flash. + * + * Input Parameters: + * mtd_offset - MTD Partition offset from the base address in SPI Flash. + * mtd_size - Size for the MTD partition. + * + * Returned Value: + * SPI Flash MTD data pointer if success or NULL if fail. + * + ****************************************************************************/ + +struct mtd_dev_s *esp_spiflash_alloc_mtdpart(uint32_t mtd_offset, + uint32_t mtd_size); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_SPIFLASH_MTD_H */ diff --git a/arch/risc-v/src/common/espressif/esp_start.c b/arch/risc-v/src/common/espressif/esp_start.c new file mode 100644 index 0000000000000..25685998bff41 --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_start.c @@ -0,0 +1,509 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_start.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "riscv_internal.h" + +#include "esp_irq.h" +#include "esp_libc_stubs.h" +#include "esp_lowputc.h" +#include "esp_start.h" + +#include "esp_clk_internal.h" +#include "esp_cpu.h" +#include "esp_private/brownout.h" +#include "hal/wdt_hal.h" +#include "hal/mmu_hal.h" +#include "hal/mmu_types.h" +#include "hal/cache_types.h" +#include "hal/cache_ll.h" +#include "hal/cache_hal.h" +#include "soc/ext_mem_defs.h" +#include "soc/extmem_reg.h" +#include "soc/mmu.h" +#include "soc/reg_base.h" +#include "spi_flash_mmap.h" +#include "rom/cache.h" + +#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT +#include "bootloader_init.h" +#include "bootloader_flash_priv.h" +#include "esp_rom_uart.h" +#include "esp_rom_sys.h" +#include "esp_app_format.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES +# define showprogress(c) riscv_lowputc(c) +#else +# define showprogress(c) +#endif + +#if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) +#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT +# define PRIMARY_SLOT_OFFSET CONFIG_ESPRESSIF_OTA_PRIMARY_SLOT_OFFSET +# define MMU_FLASH_MASK (~(MMU_BLOCK_SIZE - 1)) +#else +/* Force offset to the beginning of the whole image + */ + +# define PRIMARY_SLOT_OFFSET 0 +#endif +# define HDR_ATTR __attribute__((section(".entry_addr"))) \ + __attribute__((used)) +# define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE) +# define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t)) +# define MMU_BLOCK_SIZE 0x00010000 /* 64 KB */ +# define CACHE_REG EXTMEM_ICACHE_CTRL1_REG +# define CACHE_MASK (EXTMEM_ICACHE_SHUT_IBUS_M | \ + EXTMEM_ICACHE_SHUT_DBUS_M) + +# define CHECKSUM_ALIGN 16 +# define IS_PADD(addr) ((addr) == 0) +# define IS_DRAM(addr) ((addr) >= SOC_DRAM_LOW && (addr) < SOC_DRAM_HIGH) +# define IS_IRAM(addr) ((addr) >= SOC_IRAM_LOW && (addr) < SOC_IRAM_HIGH) +# define IS_IROM(addr) ((addr) >= SOC_IROM_LOW && (addr) < SOC_IROM_HIGH) +# define IS_DROM(addr) ((addr) >= SOC_DROM_LOW && (addr) < SOC_DROM_HIGH) +# define IS_SRAM(addr) (IS_IRAM(addr) || IS_DRAM(addr)) +# define IS_MMAP(addr) (IS_IROM(addr) || IS_DROM(addr)) +# ifdef SOC_RTC_FAST_MEM_SUPPORTED +# define IS_RTC_FAST_IRAM(addr) \ + ((addr) >= SOC_RTC_IRAM_LOW \ + && (addr) < SOC_RTC_IRAM_HIGH) +# define IS_RTC_FAST_DRAM(addr) \ + ((addr) >= SOC_RTC_DRAM_LOW \ + && (addr) < SOC_RTC_DRAM_HIGH) +# else +# define IS_RTC_FAST_IRAM(addr) false +# define IS_RTC_FAST_DRAM(addr) false +# endif +# ifdef SOC_RTC_SLOW_MEM_SUPPORTED +# define IS_RTC_SLOW_DRAM(addr) \ + ((addr) >= SOC_RTC_DATA_LOW \ + && (addr) < SOC_RTC_DATA_HIGH) +# else +# define IS_RTC_SLOW_DRAM(addr) false +# endif +# define IS_NONE(addr) (!IS_IROM(addr) \ + && !IS_DROM(addr) \ + && !IS_IRAM(addr) \ + && !IS_DRAM(addr) \ + && !IS_RTC_FAST_IRAM(addr) \ + && !IS_RTC_FAST_DRAM(addr) \ + && !IS_RTC_SLOW_DRAM(addr) \ + && !IS_PADD(addr)) + +# define IS_MAPPING(addr) IS_IROM(addr) || IS_DROM(addr) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) +extern uint8_t _image_irom_vma[]; +extern uint8_t _image_irom_lma[]; +extern uint8_t _image_irom_size[]; + +extern uint8_t _image_drom_vma[]; +extern uint8_t _image_drom_lma[]; +extern uint8_t _image_drom_size[]; +#endif + +/**************************************************************************** + * ROM Function Prototypes + ****************************************************************************/ + +#if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) +extern int ets_printf(const char *fmt, ...) printf_like(1, 2); +#endif + +extern void cache_set_idrom_mmu_size(uint32_t irom_size, uint32_t drom_size); + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) +IRAM_ATTR noreturn_function void __start(void); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) +HDR_ATTR static void (*_entry_point)(void) = __start; +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +extern uint8_t _instruction_reserved_start[]; +extern uint8_t _instruction_reserved_end[]; +extern uint8_t _rodata_reserved_start[]; +extern uint8_t _rodata_reserved_end[]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: calc_mmu_pages + * + * Description: + * Calculate the number of cache pages to map. + * + * Input Parameters: + * size - Size of data to map + * vaddr - Virtual address where data will be mapped + * + * Returned Value: + * Number of cache MMU pages required to do the mapping. + * + ****************************************************************************/ + +#if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) +static inline uint32_t calc_mmu_pages(uint32_t size, uint32_t vaddr) +{ + return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_BLOCK_SIZE - 1) / + MMU_BLOCK_SIZE; +} +#endif + +/**************************************************************************** + * Name: map_rom_segments + * + * Description: + * Configure the MMU and Cache peripherals for accessing ROM code and data. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ + defined(CONFIG_ESPRESSIF_SIMPLE_BOOT) +static int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, + uint32_t app_drom_size, uint32_t app_irom_start, + uint32_t app_irom_vaddr, uint32_t app_irom_size) +{ + uint32_t rc = 0; + uint32_t actual_mapped_len = 0; + uint32_t app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK; + uint32_t app_irom_vaddr_aligned = app_irom_vaddr & MMU_FLASH_MASK; + uint32_t app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK; + uint32_t app_drom_vaddr_aligned = app_drom_vaddr & MMU_FLASH_MASK; +#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT + esp_image_header_t image_header; /* Header for entire image */ + esp_image_segment_header_t WORD_ALIGNED_ATTR segment_hdr; + bool padding_checksum = false; + unsigned int segments = 0; + unsigned int ram_segments = 0; + unsigned int rom_segments = 0; + size_t offset = CONFIG_BOOTLOADER_OFFSET_IN_FLASH; +#endif + +#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT + + /* Read image header */ + + if (bootloader_flash_read(offset, &image_header, + sizeof(esp_image_header_t), + true) != ESP_OK) + { + ets_printf("Failed to load image header!\n"); + abort(); + } + + offset += sizeof(esp_image_header_t); + + /* Iterate for segment information parsing */ + + while (segments++ < 16 && rom_segments < 2) + { + /* Read segment header */ + + if (bootloader_flash_read(offset, &segment_hdr, + sizeof(esp_image_segment_header_t), + true) != ESP_OK) + { + ets_printf("failed to read segment header at %x\n", offset); + abort(); + } + + if (IS_NONE(segment_hdr.load_addr)) + { + /* Total segment count = (segments - 1) */ + + break; + } + + if (IS_RTC_FAST_IRAM(segment_hdr.load_addr) || + IS_RTC_FAST_DRAM(segment_hdr.load_addr) || + IS_RTC_SLOW_DRAM(segment_hdr.load_addr)) + { + /* RTC segment is loaded by ROM bootloader */ + + ram_segments++; + } + + ets_printf("%s: lma 0x%08x vma 0x%08lx len 0x%-6lx (%lu)\n", + IS_NONE(segment_hdr.load_addr) ? "???" : + IS_RTC_FAST_IRAM(segment_hdr.load_addr) || + IS_RTC_FAST_DRAM(segment_hdr.load_addr) || + IS_RTC_SLOW_DRAM(segment_hdr.load_addr) ? "rtc" : + IS_MMAP(segment_hdr.load_addr) ? + IS_IROM(segment_hdr.load_addr) ? "imap" : "dmap" : + IS_PADD(segment_hdr.load_addr) ? "padd" : + IS_DRAM(segment_hdr.load_addr) ? "dram" : "iram", + offset + sizeof(esp_image_segment_header_t), + segment_hdr.load_addr, segment_hdr.data_len, + segment_hdr.data_len); + + /* Fix drom and irom produced be the linker, as this + * is later invalidated by the elf2image command. + */ + + if (IS_DROM(segment_hdr.load_addr) && + segment_hdr.load_addr == (uint32_t)_image_drom_vma) + { + app_drom_start = offset + sizeof(esp_image_segment_header_t); + app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK; + rom_segments++; + } + + if (IS_IROM(segment_hdr.load_addr) && + segment_hdr.load_addr == (uint32_t)_image_irom_vma) + { + app_irom_start = offset + sizeof(esp_image_segment_header_t); + app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK; + rom_segments++; + } + + if (IS_SRAM(segment_hdr.load_addr)) + { + ram_segments++; + } + + offset += sizeof(esp_image_segment_header_t) + segment_hdr.data_len; + if (ram_segments == image_header.segment_count && !padding_checksum) + { + offset += (CHECKSUM_ALIGN - 1) - (offset % CHECKSUM_ALIGN) + 1; + padding_checksum = true; + } + } + + if (segments == 0 || segments == 16) + { + ets_printf("Error parsing segments\n"); + } + + ets_printf("total segments stored %d\n", segments - 1); +#endif + + cache_hal_disable(CACHE_TYPE_ALL); + + /* Clear the MMU entries that are already set up, + * so the new app only has the mappings it creates. + */ + + mmu_hal_unmap_all(); + + mmu_hal_map_region(0, MMU_TARGET_FLASH0, + app_drom_vaddr_aligned, app_drom_start_aligned, + app_drom_size, &actual_mapped_len); + + mmu_hal_map_region(0, MMU_TARGET_FLASH0, + app_irom_vaddr_aligned, app_irom_start_aligned, + app_irom_size, &actual_mapped_len); + + /* ------------------Enable corresponding buses--------------------- */ + + cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, app_drom_vaddr_aligned, + app_drom_size); + cache_ll_l1_enable_bus(0, bus_mask); + bus_mask = cache_ll_l1_get_bus(0, app_irom_vaddr_aligned, app_irom_size); + cache_ll_l1_enable_bus(0, bus_mask); +#if CONFIG_ESPRESSIF_NUM_CPUS > 1 + bus_mask = cache_ll_l1_get_bus(1, app_drom_vaddr_aligned, app_drom_size); + cache_ll_l1_enable_bus(1, bus_mask); + bus_mask = cache_ll_l1_get_bus(1, app_irom_vaddr_aligned, app_irom_size); + cache_ll_l1_enable_bus(1, bus_mask); +#endif + + /* ------------------Enable Cache----------------------------------- */ + + cache_hal_enable(CACHE_TYPE_ALL); + + return (int)rc; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __esp_start + ****************************************************************************/ + +void __esp_start(void) +{ +#ifdef CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE + uint32_t _instruction_size; + uint32_t cache_mmu_irom_size; +#endif + +#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT + if (bootloader_init() != 0) + { + ets_printf("Hardware init failed, aborting\n"); + while (true); + } +#endif + +#if defined(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT) || \ + defined(CONFIG_ESPRESSIF_SIMPLE_BOOT) + size_t partition_offset = PRIMARY_SLOT_OFFSET; + uint32_t app_irom_start = partition_offset + (uint32_t)_image_irom_lma; + uint32_t app_irom_size = (uint32_t)_image_irom_size; + uint32_t app_irom_vaddr = (uint32_t)_image_irom_vma; + uint32_t app_drom_start = partition_offset + (uint32_t)_image_drom_lma; + uint32_t app_drom_size = (uint32_t)_image_drom_size; + uint32_t app_drom_vaddr = (uint32_t)_image_drom_vma; + + if (map_rom_segments(app_drom_start, app_drom_vaddr, app_drom_size, + app_irom_start, app_irom_vaddr, app_irom_size) != 0) + { + ets_printf("Failed to setup XIP, aborting\n"); + while (true); + } +#endif + +#if CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE + _instruction_size = (uint32_t)&_instruction_reserved_end - \ + (uint32_t)&_instruction_reserved_start; + cache_mmu_irom_size = + ((_instruction_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / \ + SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t); + + /* Configure the Cache MMU size for instruction and rodata in flash. */ + + cache_set_idrom_mmu_size(cache_mmu_irom_size, + CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size); +#endif /* CONFIG_ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE */ + +#ifdef CONFIG_ESPRESSIF_REGION_PROTECTION + /* Configure region protection */ + + esp_cpu_configure_region_protection(); +#endif + + /* Configures the CPU clock, RTC slow and fast clocks, and performs + * RTC slow clock calibration. + */ + + esp_clk_init(); + + /* Disable clock of unused peripherals */ + + esp_perip_clk_init(); + +#ifdef CONFIG_ESPRESSIF_BROWNOUT_DET + /* Initialize hardware brownout check and reset */ + + esp_brownout_init(); +#endif + + /* Configure the UART so we can get debug output */ + + esp_lowsetup(); + +#ifdef USE_EARLYSERIALINIT + /* Perform early serial initialization */ + + riscv_earlyserialinit(); +#endif + + showprogress('A'); + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (uint32_t *dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; ) + { + *dest++ = 0; + } + + /* Setup the syscall table needed by the ROM code */ + + esp_setup_syscall_table(); + + showprogress('B'); + + /* The 2nd stage bootloader enables RTC WDT to monitor any issues that may + * prevent the startup sequence from finishing correctly. Hence disable it + * as NuttX is about to start. + */ + + wdt_hal_context_t rwdt_ctx = RWDT_HAL_CONTEXT_DEFAULT(); + wdt_hal_write_protect_disable(&rwdt_ctx); + wdt_hal_disable(&rwdt_ctx); + wdt_hal_write_protect_enable(&rwdt_ctx); + + /* Initialize onboard resources */ + + esp_board_initialize(); + + showprogress('C'); + + /* Bring up NuttX */ + + nx_start(); + + for (; ; ); +} diff --git a/arch/risc-v/src/espressif/esp_start.h b/arch/risc-v/src/common/espressif/esp_start.h similarity index 88% rename from arch/risc-v/src/espressif/esp_start.h rename to arch/risc-v/src/common/espressif/esp_start.h index 99b056e57651d..ed513d0963f39 100644 --- a/arch/risc-v/src/espressif/esp_start.h +++ b/arch/risc-v/src/common/espressif/esp_start.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_start.h + * arch/risc-v/src/common/espressif/esp_start.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESPRESSIF_ESP_START_H -#define __ARCH_RISCV_SRC_ESPRESSIF_ESP_START_H +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_START_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_START_H /**************************************************************************** * Included Files @@ -46,4 +46,4 @@ void esp_board_initialize(void); -#endif /* __ARCH_RISCV_SRC_ESPRESSIF_ESP_START_H */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_START_H */ diff --git a/arch/risc-v/src/espressif/esp_systemreset.c b/arch/risc-v/src/common/espressif/esp_systemreset.c similarity index 98% rename from arch/risc-v/src/espressif/esp_systemreset.c rename to arch/risc-v/src/common/espressif/esp_systemreset.c index f515e592b80f4..a808ca9dacc71 100644 --- a/arch/risc-v/src/espressif/esp_systemreset.c +++ b/arch/risc-v/src/common/espressif/esp_systemreset.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_systemreset.c + * arch/risc-v/src/common/espressif/esp_systemreset.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/espressif/esp_systemreset.h b/arch/risc-v/src/common/espressif/esp_systemreset.h similarity index 93% rename from arch/risc-v/src/espressif/esp_systemreset.h rename to arch/risc-v/src/common/espressif/esp_systemreset.h index bf8ea3d58b1a4..509c604bc641a 100644 --- a/arch/risc-v/src/espressif/esp_systemreset.h +++ b/arch/risc-v/src/common/espressif/esp_systemreset.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_systemreset.h + * arch/risc-v/src/common/espressif/esp_systemreset.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESPRESSIF_ESP_SYSTEMRESET_H -#define __ARCH_RISCV_SRC_ESPRESSIF_ESP_SYSTEMRESET_H +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_SYSTEMRESET_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_SYSTEMRESET_H /**************************************************************************** * Included Files @@ -108,4 +108,4 @@ void up_shutdown_handler(void); #undef EXTERN #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESPRESSIF_ESP_SYSTEMRESET_H */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_SYSTEMRESET_H */ diff --git a/arch/risc-v/src/espressif/esp_tickless.c b/arch/risc-v/src/common/espressif/esp_tickless.c similarity index 99% rename from arch/risc-v/src/espressif/esp_tickless.c rename to arch/risc-v/src/common/espressif/esp_tickless.c index 981e53893a215..1f8a43e4f57a4 100644 --- a/arch/risc-v/src/espressif/esp_tickless.c +++ b/arch/risc-v/src/common/espressif/esp_tickless.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_tickless.c + * arch/risc-v/src/common/espressif/esp_tickless.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/espressif/esp_tickless.h b/arch/risc-v/src/common/espressif/esp_tickless.h similarity index 90% rename from arch/risc-v/src/espressif/esp_tickless.h rename to arch/risc-v/src/common/espressif/esp_tickless.h index c0c9f106c6e91..88f6d2fc25d74 100644 --- a/arch/risc-v/src/espressif/esp_tickless.h +++ b/arch/risc-v/src/common/espressif/esp_tickless.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_tickless.h + * arch/risc-v/src/common/espressif/esp_tickless.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESPRESSIF_ESP_TICKLESS_H -#define __ARCH_RISCV_SRC_ESPRESSIF_ESP_TICKLESS_H +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_TICKLESS_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_TICKLESS_H /**************************************************************************** * Included Files @@ -66,4 +66,4 @@ uint32_t up_get_idletime(void); void up_step_idletime(uint32_t idletime_us); -#endif /* __ARCH_RISCV_SRC_ESPRESSIF_ESP_TICKLESS_H */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_TICKLESS_H */ diff --git a/arch/risc-v/src/espressif/esp_timer.c b/arch/risc-v/src/common/espressif/esp_timer.c similarity index 99% rename from arch/risc-v/src/espressif/esp_timer.c rename to arch/risc-v/src/common/espressif/esp_timer.c index d85e03593f724..1e9dd861d8343 100644 --- a/arch/risc-v/src/espressif/esp_timer.c +++ b/arch/risc-v/src/common/espressif/esp_timer.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_timer.c + * arch/risc-v/src/common/espressif/esp_timer.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/espressif/esp_timer.h b/arch/risc-v/src/common/espressif/esp_timer.h similarity index 89% rename from arch/risc-v/src/espressif/esp_timer.h rename to arch/risc-v/src/common/espressif/esp_timer.h index fe6663a05b7b1..17adff7e344e5 100644 --- a/arch/risc-v/src/espressif/esp_timer.h +++ b/arch/risc-v/src/common/espressif/esp_timer.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_timer.h + * arch/risc-v/src/common/espressif/esp_timer.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESPRESSIF_ESP_TIMER_H -#define __ARCH_RISCV_SRC_ESPRESSIF_ESP_TIMER_H +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_TIMER_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_TIMER_H /**************************************************************************** * Included Files @@ -50,4 +50,4 @@ int esp_timer_initialize(uint32_t timer_id); -#endif /* __ARCH_RISCV_SRC_ESPRESSIF_ESP_TIMER_H */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_TIMER_H */ diff --git a/arch/risc-v/src/espressif/esp_timerisr.c b/arch/risc-v/src/common/espressif/esp_timerisr.c similarity index 99% rename from arch/risc-v/src/espressif/esp_timerisr.c rename to arch/risc-v/src/common/espressif/esp_timerisr.c index 6c4eb0ba86298..f758b88d83533 100644 --- a/arch/risc-v/src/espressif/esp_timerisr.c +++ b/arch/risc-v/src/common/espressif/esp_timerisr.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_timerisr.c + * arch/risc-v/src/common/espressif/esp_timerisr.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/common/espressif/esp_twai.c b/arch/risc-v/src/common/espressif/esp_twai.c new file mode 100644 index 0000000000000..11ffc26f07c9c --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_twai.c @@ -0,0 +1,855 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_twai.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "riscv_internal.h" + +#include "esp_gpio.h" +#include "esp_twai.h" +#include "esp_irq.h" +#include "esp_clk.h" + +#include "periph_ctrl.h" +#include "hal/twai_hal.h" +#include "hal/twai_ll.h" +#include "soc/gpio_sig_map.h" +#include "soc/reg_base.h" + +#if defined(CONFIG_ESPRESSIF_TWAI) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +# if defined(CONFIG_CAN_LOOPBACK) && defined(CONFIG_ESPRESSIF_TWAI_TEST_MODE) +# define TX_PIN_ATTR (OUTPUT_FUNCTION_1 | INPUT_FUNCTION_1) +# define RX_PIN_ATTR (OUTPUT_FUNCTION_1 | INPUT_FUNCTION_1) +# else +# define TX_PIN_ATTR OUTPUT_FUNCTION_1 +# define RX_PIN_ATTR INPUT_FUNCTION_1 +# endif + +# ifdef CONFIG_ESPRESSIF_TWAI0 +# ifdef CONFIG_TWAI0_TIMING_100KBITS + #define TWAI0_TIMING_CONFIG TWAI_TIMING_CONFIG_100KBITS() +# elif CONFIG_TWAI0_TIMING_125KBITS + #define TWAI0_TIMING_CONFIG TWAI_TIMING_CONFIG_125KBITS() +# elif CONFIG_TWAI0_TIMING_250KBITS + #define TWAI0_TIMING_CONFIG TWAI_TIMING_CONFIG_250KBITS() +# elif CONFIG_TWAI0_TIMING_500KBITS + #define TWAI0_TIMING_CONFIG TWAI_TIMING_CONFIG_500KBITS() +# else + #define TWAI0_TIMING_CONFIG TWAI_TIMING_CONFIG_800KBITS() +# endif +# endif + +# ifdef CONFIG_ESPRESSIF_TWAI1 +# ifdef CONFIG_TWAI1_TIMING_100KBITS + #define TWAI1_TIMING_CONFIG TWAI_TIMING_CONFIG_100KBITS() +# elif CONFIG_TWAI1_TIMING_125KBITS + #define TWAI1_TIMING_CONFIG TWAI_TIMING_CONFIG_125KBITS() +# elif CONFIG_TWAI1_TIMING_250KBITS + #define TWAI1_TIMING_CONFIG TWAI_TIMING_CONFIG_250KBITS() +# elif CONFIG_TWAI1_TIMING_500KBITS + #define TWAI1_TIMING_CONFIG TWAI_TIMING_CONFIG_500KBITS() +# else + #define TWAI1_TIMING_CONFIG TWAI_TIMING_CONFIG_800KBITS() +# endif +# endif + +# ifdef CONFIG_ESPRESSIF_ESP32C3 +# define INT_ENA_REG(hw) hw->interrupt_enable_reg.val +# define PERIPH_TWAI0_MODULE PERIPH_TWAI_MODULE +# define TWAI0_TX_IDX TWAI_TX_IDX +# define TWAI0_RX_IDX TWAI_RX_IDX +# define ETS_TWAI0_INTR_SOURCE ETS_TWAI_INTR_SOURCE +# define ESP_IRQ_TWAI0 ESP_IRQ_TWAI +# else +# define INT_ENA_REG(hw) hw->interrupt_enable.val +# endif /* CONFIG_ESPRESSIF_ESP32C3 */ + +# ifdef CONFIG_ESPRESSIF_ESP32H2 +# define TWAI0_TX_IDX TWAI_TX_IDX +# define TWAI0_RX_IDX TWAI_RX_IDX +# endif /* CONFIG_ESPRESSIF_ESP32H2 */ + +/* Configuration ************************************************************/ + +# ifndef CONFIG_CAN_EXTID +# define EXTID 0 +# else +# define EXTID 1 +# endif + +# ifndef CONFIG_CAN_LOOPBACK +# define LOOPBACK 0 +# else +# define LOOPBACK 1 +# endif + +/* Default values written to various registers on initialization */ + +# define TWAI_DEFAULT_INTERRUPTS 0xe7 /* Exclude data overrun (bit[3]) and brp_div (bit[4]) */ + +struct esp_twai_dev_s +{ + /* Device configuration */ + + uint8_t port; /* TWAI port number */ + uint8_t periph; /* Peripheral ID */ + uint8_t irq; /* IRQ associated with this TWAI */ + int8_t cpuint; /* CPU interrupt assigned to this TWAI */ + twai_hal_context_t ctx; /* Context struct of common layer */ + twai_timing_config_t t_config; /* Timing struct of common layer */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* TWAI methods */ + +static void esp_twai_reset(struct can_dev_s *dev); +static int esp_twai_setup(struct can_dev_s *dev); +static void esp_twai_shutdown(struct can_dev_s *dev); +static void esp_twai_rxint(struct can_dev_s *dev, bool enable); +static void esp_twai_txint(struct can_dev_s *dev, bool enable); +static int esp_twai_ioctl(struct can_dev_s *dev, int cmd, + unsigned long arg); +static int esp_twai_remoterequest(struct can_dev_s *dev, uint16_t id); +static int esp_twai_send(struct can_dev_s *dev, struct can_msg_s *msg); +static bool esp_twai_txready(struct can_dev_s *dev); +static bool esp_twai_txempty(struct can_dev_s *dev); + +/* TWAI interrupts */ + +static int esp_twai_interrupt(int irq, void *context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct can_ops_s g_twaiops = +{ + .co_reset = esp_twai_reset, + .co_setup = esp_twai_setup, + .co_shutdown = esp_twai_shutdown, + .co_rxint = esp_twai_rxint, + .co_txint = esp_twai_txint, + .co_ioctl = esp_twai_ioctl, + .co_remoterequest = esp_twai_remoterequest, + .co_send = esp_twai_send, + .co_txready = esp_twai_txready, + .co_txempty = esp_twai_txempty, +}; + +#ifdef CONFIG_ESPRESSIF_TWAI0 +static struct esp_twai_dev_s g_twai0priv = +{ + .port = 0, + .periph = ETS_TWAI0_INTR_SOURCE, + .irq = ESP_IRQ_TWAI0, + .cpuint = -ENOMEM, + .t_config = TWAI0_TIMING_CONFIG, +}; + +static struct can_dev_s g_twai0dev = +{ + .cd_ops = &g_twaiops, + .cd_priv = &g_twai0priv, +}; +#endif /* CONFIG_ESPRESSIF_TWAI0 */ + +#ifdef CONFIG_ESPRESSIF_TWAI1 +static struct esp_twai_dev_s g_twai1priv = +{ + .port = 1, + .periph = ETS_TWAI1_INTR_SOURCE, + .irq = ESP_IRQ_TWAI1, + .cpuint = -ENOMEM, + .t_config = TWAI1_TIMING_CONFIG, +}; + +static struct can_dev_s g_twai1dev = +{ + .cd_ops = &g_twaiops, + .cd_priv = &g_twai1priv, +}; +#endif /* CONFIG_ESPRESSIF_TWAI1 */ + +static const twai_filter_config_t f_config = TWAI_FILTER_CONFIG_ACCEPT_ALL(); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_twai_reset + * + * Description: + * Reset the TWAI device. Called early to initialize the hardware. This + * function is called, before esp_twai_setup() and on error conditions. + * + * Input Parameters: + * dev - An instance of the "upper half" CAN driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_twai_reset(struct can_dev_s *dev) +{ + struct esp_twai_dev_s *priv = (struct esp_twai_dev_s *)dev->cd_priv; + irqstate_t flags; + int ret; + twai_hal_config_t hal_config = + { + .clock_source_hz = esp_clk_apb_freq(), + .controller_id = priv->port, + }; + + caninfo("TWAI%" PRIu8 "\n", priv->port); + + flags = enter_critical_section(); + + ret = twai_hal_init(&priv->ctx, &hal_config); + ASSERT(ret); + twai_hal_configure(&priv->ctx, &priv->t_config, &f_config, + TWAI_DEFAULT_INTERRUPTS, 0); + + /* Restart the TWAI */ + +#ifdef CONFIG_CAN_LOOPBACK + twai_hal_start(&priv->ctx, TWAI_MODE_NO_ACK); /* Leave Reset Mode, enter Test Mode */ +#else + twai_hal_start(&priv->ctx, TWAI_MODE_NORMAL); /* Leave Reset Mode */ +#endif + + /* Abort transmission, release RX buffer and clear overrun. + * Command register can only be modified when in Operation Mode. + */ + + twai_ll_set_cmd_release_rx_buffer(priv->ctx.dev); + twai_ll_set_cmd_abort_tx(priv->ctx.dev); + twai_ll_set_cmd_clear_data_overrun(priv->ctx.dev); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: esp_twai_setup + * + * Description: + * Configure the TWAI. This method is called the first time that the TWAI + * the device is opened and it configures and attaches the TWAI interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" CAN driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int esp_twai_setup(struct can_dev_s *dev) +{ + struct esp_twai_dev_s *priv = (struct esp_twai_dev_s *)dev->cd_priv; + irqstate_t flags; + int ret = OK; + + caninfo("TWAI%" PRIu8 "\n", priv->port); + + flags = enter_critical_section(); + + twai_ll_set_enabled_intrs(priv->ctx.dev, TWAI_DEFAULT_INTERRUPTS); + + twai_ll_get_and_clear_intrs(priv->ctx.dev); /* clear latched interrupts */ + + if (priv->cpuint != -ENOMEM) + { + /* Disable the provided CPU Interrupt to configure it. */ + + up_disable_irq(priv->irq); + } + + priv->cpuint = esp_setup_irq(priv->periph, + ESP_IRQ_PRIORITY_DEFAULT, + ESP_IRQ_TRIGGER_LEVEL); + if (priv->cpuint < 0) + { + /* Failed to allocate a CPU interrupt of this type. */ + + ret = priv->cpuint; + leave_critical_section(flags); + + return ret; + } + + ret = irq_attach(priv->irq, esp_twai_interrupt, dev); + if (ret != OK) + { + /* Failed to attach IRQ, so CPU interrupt must be freed. */ + + esp_teardown_irq(priv->periph, priv->cpuint); + priv->cpuint = -ENOMEM; + leave_critical_section(flags); + + return ret; + } + + /* Enable the CPU interrupt that is linked to the TWAI device. */ + + up_enable_irq(priv->irq); + + leave_critical_section(flags); + + return ret; +} + +/**************************************************************************** + * Name: esp_twai_shutdown + * + * Description: + * Disable the TWAI. This method is called when the TWAI device is closed. + * This method reverses the operation the setup method. + * + * Input Parameters: + * dev - An instance of the "upper half" CAN driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_twai_shutdown(struct can_dev_s *dev) +{ + struct esp_twai_dev_s *priv = (struct esp_twai_dev_s *)dev->cd_priv; + +#ifdef CONFIG_DEBUG_CAN_INFO + caninfo("shutdown TWAI%" PRIu8 "\n", priv->port); +#endif + + if (priv->cpuint != -ENOMEM) + { + /* Disable cpu interrupt */ + + up_disable_irq(priv->irq); + + /* Dissociate the IRQ from the ISR */ + + irq_detach(priv->irq); + + /* Free cpu interrupt that is attached to this peripheral */ + + esp_teardown_irq(priv->periph, priv->cpuint); + priv->cpuint = -ENOMEM; + } +} + +/**************************************************************************** + * Name: esp_twai_rxint + * + * Description: + * Call to enable or disable RX interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" CAN driver state structure. + * enable - Enable or disable receive interrupt. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_twai_rxint(struct can_dev_s *dev, bool enable) +{ + struct esp_twai_dev_s *priv = (struct esp_twai_dev_s *)dev->cd_priv; + uint32_t regval; + irqstate_t flags; + + caninfo("TWAI%" PRIu8 " enable: %d\n", priv->port, enable); + + /* The INT_ENA register is also modified from the interrupt handler, + * so we have to protect this code section. + */ + + flags = enter_critical_section(); + regval = twai_ll_get_and_clear_intrs(priv->ctx.dev); + if (enable == true) + { + regval |= TWAI_LL_INTR_RI; + } + else + { + regval &= ~TWAI_LL_INTR_RI; + } + + twai_ll_set_enabled_intrs(priv->ctx.dev, regval); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: esp_twai_txint + * + * Description: + * Call to enable or disable TX interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" CAN driver state structure. + * enable - Enable or disable transmit interrupt. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_twai_txint(struct can_dev_s *dev, bool enable) +{ + struct esp_twai_dev_s *priv = (struct esp_twai_dev_s *)dev->cd_priv; + uint32_t regval; + irqstate_t flags; + + caninfo("TWAI%" PRIu8 " enable: %d\n", priv->port, enable); + + /* Only disabling of the TX interrupt is supported here. The TX interrupt + * is automatically enabled just before a message is sent in order to avoid + * lost TX interrupts. + */ + + if (enable == false) + { + /* TX interrupts are also disabled from the interrupt handler, so we + * have to protect this code section. + */ + + flags = enter_critical_section(); + + /* Disable all TX interrupts */ + + regval = INT_ENA_REG(priv->ctx.dev); + regval &= ~TWAI_LL_INTR_TI; + twai_ll_set_enabled_intrs(priv->ctx.dev, regval); + leave_critical_section(flags); + } +} + +/**************************************************************************** + * Name: esp_twai_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + * Input Parameters: + * dev - An instance of the "upper half" CAN driver state structure. + * cmd - A ioctl command. + * arg - A ioctl argument. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int esp_twai_ioctl(struct can_dev_s *dev, int cmd, unsigned long arg) +{ + struct esp_twai_dev_s *priv = (struct esp_twai_dev_s *)dev->cd_priv; + int ret = -ENOTTY; + + caninfo("TWAI%" PRIu8 " cmd=%04x arg=%lu\n", priv->port, cmd, arg); + + /* Handle the command */ + + switch (cmd) + { + /* CANIOC_GET_BITTIMING: + * Description: Return the current bit timing settings + * Argument: A pointer to a write-able instance of struct + * canioc_bittiming_s in which current bit timing + * values will be returned. + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR) is returned with the errno variable set + * to indicate the nature of the error. + * Dependencies: None + */ + + case CANIOC_GET_BITTIMING: + { + struct canioc_bittiming_s *bt = + (struct canioc_bittiming_s *)arg; + uint32_t timing0; + uint32_t timing1; + uint32_t brp; + + DEBUGASSERT(bt != NULL); + + brp = (priv->t_config.brp + 1) * 2; + bt->bt_sjw = priv->t_config.sjw + 1; + bt->bt_tseg1 = priv->t_config.tseg_1 + 1; + bt->bt_tseg2 = priv->t_config.tseg_2 + 1; + + bt->bt_baud = esp_clk_apb_freq() / + (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); + + ret = OK; + } + break; + + /* Unsupported/unrecognized command */ + + default: + canerr("ERROR: Unrecognized command: %04x\n", cmd); + break; + } + + return ret; +} + +/**************************************************************************** + * Name: esp_twai_remoterequest + * + * Description: + * Send a remote request + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * id - Requested 11-bit data frame identifier + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int esp_twai_remoterequest(struct can_dev_s *dev, uint16_t id) +{ + canwarn("Remote request not implemented\n"); + return -ENOSYS; +} + +/**************************************************************************** + * Name: esp_twai_send + * + * Description: + * Send one TWAI message. + * + * One TWAI-message consists of a maximum of 10 bytes. A message is + * composed of at least the first 2 bytes (when there are no data bytes). + * + * Byte 0: Bits 0-7: Bits 3-10 of the 11-bit TWAI identifier + * Byte 1: Bits 5-7: Bits 0-2 of the 11-bit TWAI identifier + * Bit 4: Remote Transmission Request (RTR) + * Bits 0-3: Data Length Code (DLC) + * Bytes 2-10: TWAI data + * + * Input Parameters: + * dev - An instance of the "upper half" CAN driver state structure. + * msg - A message to send. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int esp_twai_send(struct can_dev_s *dev, struct can_msg_s *msg) +{ + struct esp_twai_dev_s *priv = (struct esp_twai_dev_s *)dev->cd_priv; + uint32_t regval; + uint32_t i; + uint32_t len; + uint32_t id; + uint32_t twai_flags; + irqstate_t flags; + int ret = OK; + + caninfo("TWAI%" PRIu8 " ID: %" PRIu32 " DLC: %" PRIu8 "\n", + priv->port, (uint32_t)msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc); + + len = (uint32_t)msg->cm_hdr.ch_dlc; + if (len > CAN_MAXDATALEN) + { + len = CAN_MAXDATALEN; + } + + flags = enter_critical_section(); + + /* Make sure that TX interrupts are enabled BEFORE sending the + * message. + * + * NOTE: The INT_ENA is also modified from the interrupt handler, but the + * following is safe because interrupts are disabled here. + */ + + regval = INT_ENA_REG(priv->ctx.dev); + regval |= TWAI_LL_INTR_TI; + twai_ll_set_enabled_intrs(priv->ctx.dev, regval); + + twai_hal_frame_t tx_frame; + + /* Adjustments from NuttX TWAI message struct to common layer TWAI struct */ + + twai_flags = ((EXTID << TWAI_MSG_FLAG_EXTD) | + (msg->cm_hdr.ch_rtr << TWAI_MSG_FLAG_RTR) | + (LOOPBACK << TWAI_MSG_FLAG_SELF)); + + /* Set up the transfer */ + + twai_ll_format_frame_buffer(msg->cm_hdr.ch_id, len, + msg->cm_data, twai_flags, &tx_frame); + twai_ll_set_tx_buffer(priv->ctx.dev, &tx_frame); + + /* Send the message */ + +#ifdef CONFIG_CAN_LOOPBACK + twai_ll_set_cmd_self_rx_request(priv->ctx.dev); +#else + twai_ll_set_cmd_tx(priv->ctx.dev); +#endif + + leave_critical_section(flags); + + return ret; +} + +/**************************************************************************** + * Name: esp_twai_txready + * + * Description: + * Return true if the TWAI hardware can accept another TX message. + * + * Input Parameters: + * dev - An instance of the "upper half" CAN driver state structure. + * + * Returned Value: + * True if the TWAI hardware is ready to accept another TX message. + * + ****************************************************************************/ + +static bool esp_twai_txready(struct can_dev_s *dev) +{ + struct esp_twai_dev_s *priv = dev->cd_priv; + uint32_t regval = twai_ll_get_status(priv->ctx.dev); + caninfo("TWAI%" PRIu8 " txready: %d\n", priv->port, + ((regval & TWAI_LL_STATUS_TBS) != 0)); + return ((regval & TWAI_LL_STATUS_TBS) != 0); +} + +/**************************************************************************** + * Name: esp_twai_txempty + * + * Description: + * Return true if all message have been sent. If for example, the TWAI + * hardware implements FIFOs, then this would mean the transmit FIFO is + * empty. This method is called when the driver needs to make sure that + * all characters are "drained" from the TX hardware before calling + * co_shutdown(). + * + * Input Parameters: + * dev - An instance of the "upper half" CAN driver state structure. + * + * Returned Value: + * True if there are no pending TX transfers in the TWAI hardware. + * + ****************************************************************************/ + +static bool esp_twai_txempty(struct can_dev_s *dev) +{ + struct esp_twai_dev_s *priv = dev->cd_priv; + uint32_t regval = twai_ll_get_status(priv->ctx.dev); + + caninfo("TWAI%" PRIu8 " txempty: %d\n", priv->port, + ((regval & TWAI_LL_STATUS_TBS) != 0)); + return ((regval & TWAI_LL_STATUS_TBS) != 0); +} + +/**************************************************************************** + * Name: esp_twai_interrupt + * + * Description: + * TWAI RX/TX interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * arg - The pointer to driver structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int esp_twai_interrupt(int irq, void *context, void *arg) +{ + struct can_dev_s *dev = (struct can_dev_s *)arg; + struct esp_twai_dev_s *priv = dev->cd_priv; + struct can_hdr_s hdr; + uint8_t data[8]; + uint32_t regval; + twai_hal_frame_t rx_frame; + uint32_t flags = 0; + uint32_t id; + uint8_t dlc; + + /* Read the interrupt register results in clearing bits */ + + regval = twai_ll_get_and_clear_intrs(priv->ctx.dev); + + /* Check for a receive interrupt */ + + if ((regval & TWAI_LL_INTR_RI) != 0) + { + memset(&hdr, 0, sizeof(hdr)); + memset(data, 0, sizeof(data)); + + twai_ll_get_rx_buffer(priv->ctx.dev, &rx_frame); + + /* Release the receive buffer */ + + twai_ll_set_cmd_release_rx_buffer(priv->ctx.dev); + twai_ll_parse_frame_buffer(&rx_frame, &id, &dlc, data, &flags); + hdr.ch_id = id; + hdr.ch_dlc = dlc; + hdr.ch_rtr = (flags && TWAI_MSG_FLAG_RTR) ? 1 : 0; + + can_receive(dev, &hdr, data); + } + + /* Check for TX buffer complete */ + + if ((regval & TWAI_LL_INTR_TI) != 0) + { + /* Disable all further TX buffer interrupts */ + + esp_twai_txint(dev, false); + + /* Indicate that the TX is done and a new TX buffer is available */ + + can_txdone(dev); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_twaiinitialize + * + * Description: + * Initialize TWAI peripheral + * + * Input Parameters: + * port - Port number (for hardware that has multiple TWAI interfaces) + * + * Returned Value: + * Valid TWAI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct can_dev_s *esp_twaiinitialize(int port) +{ + struct can_dev_s *dev; + irqstate_t flags; + + caninfo("TWAI%" PRIu8 "\n", port); + + flags = enter_critical_section(); + +#ifdef CONFIG_ESPRESSIF_TWAI0 + if (port == 0) + { + /* Enable power to the TWAI module and + * Enable clocking to the TWAI module + */ + + periph_module_reset(PERIPH_TWAI0_MODULE); + periph_module_enable(PERIPH_TWAI0_MODULE); + + /* Configure CAN GPIO pins */ + + esp_gpio_matrix_out(CONFIG_ESPRESSIF_TWAI0_TXPIN, TWAI0_TX_IDX, 0, 0); + esp_configgpio(CONFIG_ESPRESSIF_TWAI0_TXPIN, TX_PIN_ATTR); + + esp_configgpio(CONFIG_ESPRESSIF_TWAI0_RXPIN, RX_PIN_ATTR); + esp_gpio_matrix_in(CONFIG_ESPRESSIF_TWAI0_RXPIN, TWAI0_RX_IDX, 0); + + dev = &g_twai0dev; + } + else +#endif + +#ifdef CONFIG_ESPRESSIF_TWAI1 + if (port == 1) + { + /* Enable power to the TWAI module and + * Enable clocking to the TWAI module + */ + + periph_module_reset(PERIPH_TWAI1_MODULE); + periph_module_enable(PERIPH_TWAI1_MODULE); + + /* Configure CAN GPIO pins */ + + esp_gpio_matrix_out(CONFIG_ESPRESSIF_TWAI1_TXPIN, TWAI1_TX_IDX, 0, 0); + esp_configgpio(CONFIG_ESPRESSIF_TWAI1_TXPIN, TX_PIN_ATTR); + + esp_configgpio(CONFIG_ESPRESSIF_TWAI1_RXPIN, RX_PIN_ATTR); + esp_gpio_matrix_in(CONFIG_ESPRESSIF_TWAI1_RXPIN, TWAI1_RX_IDX, 0); + + dev = &g_twai1dev; + } + else +#endif + + { + canerr("ERROR: Unsupported port: %d\n", port); + leave_critical_section(flags); + return NULL; + } + + /* Then just perform a TWAI reset operation */ + + esp_twai_reset(dev); + + leave_critical_section(flags); + + return dev; +} +#endif /* CONFIG_ESPRESSIF_TWAI */ diff --git a/arch/risc-v/src/common/espressif/esp_twai.h b/arch/risc-v/src/common/espressif/esp_twai.h new file mode 100644 index 0000000000000..ca168d6331a3d --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_twai.h @@ -0,0 +1,76 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_twai.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_TWAI_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_TWAI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_twaiinitialize + * + * Description: + * Initialize CAN port + * + * Input Parameters: + * port - Port number (for hardware that has multiple TWAI interfaces) + * + * Returned Value: + * Valid TWAI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +#if defined(CONFIG_CAN) && defined(CONFIG_ESPRESSIF_TWAI) +struct can_dev_s *esp_twaiinitialize(int port); +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_TWAI_H */ diff --git a/arch/risc-v/src/espressif/esp_usbserial.c b/arch/risc-v/src/common/espressif/esp_usbserial.c similarity index 99% rename from arch/risc-v/src/espressif/esp_usbserial.c rename to arch/risc-v/src/common/espressif/esp_usbserial.c index 5c5586798d4e3..088ae9a1a7f93 100644 --- a/arch/risc-v/src/espressif/esp_usbserial.c +++ b/arch/risc-v/src/common/espressif/esp_usbserial.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_usbserial.c + * arch/risc-v/src/common/espressif/esp_usbserial.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/espressif/esp_usbserial.h b/arch/risc-v/src/common/espressif/esp_usbserial.h similarity index 89% rename from arch/risc-v/src/espressif/esp_usbserial.h rename to arch/risc-v/src/common/espressif/esp_usbserial.h index b4767b30113f7..7b3414844d260 100644 --- a/arch/risc-v/src/espressif/esp_usbserial.h +++ b/arch/risc-v/src/common/espressif/esp_usbserial.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_usbserial.h + * arch/risc-v/src/common/espressif/esp_usbserial.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESPRESSIF_ESP_USBSERIAL_H -#define __ARCH_RISCV_SRC_ESPRESSIF_ESP_USBSERIAL_H +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_USBSERIAL_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_USBSERIAL_H /**************************************************************************** * Included Files @@ -48,4 +48,4 @@ extern uart_dev_t g_uart_usbserial; void esp_usbserial_write(char ch); -#endif /* __ARCH_RISCV_SRC_ESPRESSIF_ESP_USBSERIAL_H */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_USBSERIAL_H */ diff --git a/arch/risc-v/src/espressif/esp_vectors.S b/arch/risc-v/src/common/espressif/esp_vectors.S similarity index 96% rename from arch/risc-v/src/espressif/esp_vectors.S rename to arch/risc-v/src/common/espressif/esp_vectors.S index 96c44e4442b42..28d50a5843ff5 100644 --- a/arch/risc-v/src/espressif/esp_vectors.S +++ b/arch/risc-v/src/common/espressif/esp_vectors.S @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/espressif/esp_vectors.S + * arch/risc-v/src/common/espressif/esp_vectors.S * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -24,7 +24,6 @@ #include -#include #include #include "chip.h" diff --git a/arch/risc-v/src/common/espressif/esp_wdt.c b/arch/risc-v/src/common/espressif/esp_wdt.c new file mode 100644 index 0000000000000..f059fcb3708e5 --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_wdt.c @@ -0,0 +1,770 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_wdt.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "esp_irq.h" +#include "esp_wdt.h" +#include "esp_clk.h" +#include "esp_rtc_gpio.h" + +#include "hal/mwdt_ll.h" +#include "hal/rwdt_ll.h" +#include "hal/wdt_hal.h" +#include "soc/rtc.h" +#include "periph_ctrl.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* MWDT clock period in microseconds */ + +#define MWDT_CLK_PERIOD_US (500) + +/* Number of MWDT cycles per microseconds */ + +#define MWDT_CYCLES_PER_MS (USEC_PER_MSEC / MWDT_CLK_PERIOD_US) + +/* Convert MWDT timeout cycles to milliseconds */ + +#define MWDT_TIMEOUT_MS(t) ((t) * MWDT_CYCLES_PER_MS) + +/* Maximum number of MWDT cycles supported for timeout */ + +#define MWDT_MAX_TIMEOUT_MS (UINT32_MAX / MWDT_CYCLES_PER_MS) + +/* Maximum number of cycles supported for a RWDT stage timeout */ + +#define RWDT_FULL_STAGE (UINT32_MAX) + +/* Convert RWDT timeout cycles to milliseconds */ + +#define RWDT_TIMEOUT_MS(t) (t * rtc_clk_slow_freq_get_hz() / 1000ULL) + +#define WDT_INTR_ENABLE(timer, ctx, en) (timer == RTC ? \ + rwdt_ll_set_intr_enable(ctx->rwdt_dev, en) : \ + mwdt_ll_set_intr_enable(ctx->mwdt_dev, en)) + +/* Helpers for converting from Q13.19 fixed-point format to float */ + +#define N 19 +#define Q_TO_FLOAT(x) ((float)x/(float)(1<started) + { + /* Return EBUSY to indicate that the timer was already running */ + + return -EBUSY; + } + + priv->started = true; + + wdt_hal_write_protect_disable(priv->ctx); + + if (priv->handler == NULL) + { + /* No user handler, so configure WDT to reset on timeout */ + + if (priv->peripheral == TIMER) + { + priv->action = WDT_STAGE_ACTION_RESET_SYSTEM; + timeout = MWDT_TIMEOUT_MS(priv->timeout); + } + else + { + priv->action = WDT_STAGE_ACTION_RESET_RTC; + timeout = RWDT_TIMEOUT_MS(priv->timeout); + } + + wdt_hal_config_stage(priv->ctx, WDT_STAGE0, + timeout, + priv->action); + } + else + { + /* Configure WDT to call the user handler on timeout */ + + if (priv->peripheral == TIMER) + { + priv->action = WDT_STAGE_ACTION_INT; + timeout = MWDT_TIMEOUT_MS(priv->timeout); + } + else + { + priv->action = WDT_STAGE_ACTION_INT; + timeout = RWDT_TIMEOUT_MS(priv->timeout); + } + + wdt_hal_config_stage(priv->ctx, WDT_STAGE0, + timeout, + priv->action); + + /* Enable interrupt */ + + WDT_INTR_ENABLE(priv->peripheral, priv->ctx, true); + } + + flags = enter_critical_section(); + priv->lastreset = clock_systime_ticks(); + wdt_hal_enable(priv->ctx); + leave_critical_section(flags); + + wdt_hal_write_protect_enable(priv->ctx); + + return ret; +} + +/**************************************************************************** + * Name: wdt_stop + * + * Description: + * Stop the watchdog timer. In case a callback was previously configured, + * unregister and deallocate it. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int wdt_stop(struct watchdog_lowerhalf_s *lower) +{ + struct esp_wdt_lowerhalf_s *priv = (struct esp_wdt_lowerhalf_s *)lower; + + wdt_hal_write_protect_disable(priv->ctx); + + /* Disable the WDT */ + + wdt_hal_disable(priv->ctx); + + /* In case there is a callback registered, ensure WDT interrupts are + * disabled. + */ + + if (priv->handler != NULL) + { + WDT_INTR_ENABLE(priv->peripheral, priv->ctx, false); + } + + wdt_hal_write_protect_enable(priv->ctx); + + priv->started = false; + + return OK; +} + +/**************************************************************************** + * Name: wdt_keepalive + * + * Description: + * Reset the watchdog timer, prevent any + * imminent watchdog timeouts. This is sometimes referred as "pinging" + * the watchdog timer or "petting the dog". + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int wdt_keepalive(struct watchdog_lowerhalf_s *lower) +{ + struct esp_wdt_lowerhalf_s *priv = (struct esp_wdt_lowerhalf_s *)lower; + irqstate_t flags; + + wdt_hal_write_protect_disable(priv->ctx); + + /* Feed the dog and update the time of last reset */ + + flags = enter_critical_section(); + priv->lastreset = clock_systime_ticks(); + wdt_hal_feed(priv->ctx); + leave_critical_section(flags); + + wdt_hal_write_protect_enable(priv->ctx); + + return OK; +} + +/**************************************************************************** + * Name: wdt_getstatus + * + * Description: + * Get the current watchdog timer status + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * status - The location to return the watchdog status information. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int wdt_getstatus(struct watchdog_lowerhalf_s *lower, + struct watchdog_status_s *status) +{ + struct esp_wdt_lowerhalf_s *priv = (struct esp_wdt_lowerhalf_s *)lower; + uint32_t ticks; + uint32_t elapsed; + + DEBUGASSERT(priv != NULL); + + status->flags = 0; + + /* If no handler was settled, then RESET on expiration. + * Otherwise, call the user handler. + */ + + if (priv->handler == NULL) + { + status->flags |= WDFLAGS_RESET; + } + else + { + status->flags |= WDFLAGS_CAPTURE; + } + + if (priv->started) + { + status->flags |= WDFLAGS_ACTIVE; + } + + /* Return the current timeout in milliseconds */ + + status->timeout = priv->timeout; + + /* Get the elapsed time since the last ping */ + + ticks = clock_systime_ticks() - priv->lastreset; + elapsed = (uint32_t)TICK2MSEC(ticks); + + if (elapsed < priv->timeout) + { + /* Return the approximate time until the watchdog timer expiration */ + + status->timeleft = priv->timeout - elapsed; + } + else + { + status->timeleft = 0; + } + + return OK; +} + +/**************************************************************************** + * Name: wdt_settimeout + * + * Description: + * Set a new timeout value (and reset the watchdog timer) + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * timeout - The new timeout value in milliseconds. + * + * Returned Values: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int wdt_settimeout(struct watchdog_lowerhalf_s *lower, + uint32_t timeout) +{ + struct esp_wdt_lowerhalf_s *priv = (struct esp_wdt_lowerhalf_s *)lower; + uint16_t rtc_cycles = 0; + uint32_t rtc_ms_max = 0; + + wdinfo("Entry: timeout=%" PRIu32 "\n", timeout); + + DEBUGASSERT(priv != NULL); + + wdt_hal_write_protect_disable(priv->ctx); + + priv->timeout = timeout; + + if (priv->peripheral == TIMER) + { + if (timeout == 0 || timeout > MWDT_MAX_TIMEOUT_MS) + { + wderr("ERROR: Cannot represent timeout=%"PRIu32" > %"PRIu32"\n", + timeout, MWDT_MAX_TIMEOUT_MS); + return -ERANGE; + } + + timeout = MWDT_TIMEOUT_MS(priv->timeout); + } + else + { + uint32_t period_13q19 = esp_clk_slowclk_cal_get(); + float period = Q_TO_FLOAT(period_13q19); + rtc_cycles = 1000.0f / period; + rtc_ms_max = (RWDT_FULL_STAGE / (uint32_t)rtc_cycles); + + /* Is this timeout a valid value for RTC WDT? */ + + if (timeout == 0 || timeout > rtc_ms_max) + { + wderr("ERROR: Cannot represent timeout=%"PRIu32" > %"PRIu32"\n", + timeout, rtc_ms_max); + return -ERANGE; + } + + timeout = timeout * rtc_cycles; + } + + wdt_hal_config_stage(priv->ctx, WDT_STAGE0, + timeout, + priv->action); + + wdt_hal_feed(priv->ctx); + + wdt_hal_write_protect_enable(priv->ctx); + + return OK; +} + +/**************************************************************************** + * Name: wdt_capture + * + * Description: + * Don't reset on watchdog timer timeout; instead, call this user provider + * timeout handler. NOTE: Providing handler==NULL will restore the reset + * behavior. + * + * Input Parameters: + * lower - A pointer the publicly visible representation of the + * "lower-half" driver state structure. + * handler - The new watchdog expiration function pointer. If this + * function pointer is NULL, then the reset-on-expiration + * behavior is restored. + * + * Returned Value: + * The previous watchdog expiration function pointer or NULL if there was + * no previous function pointer, i.e., if the previous behavior was + * reset-on-expiration (NULL is also returned if an error occurs). + * + ****************************************************************************/ + +static xcpt_t wdt_capture(struct watchdog_lowerhalf_s *lower, xcpt_t handler) +{ + struct esp_wdt_lowerhalf_s *priv = (struct esp_wdt_lowerhalf_s *)lower; + irqstate_t flags; + xcpt_t oldhandler; + uint32_t timeout; + + DEBUGASSERT(priv != NULL); + + wdinfo("Entry: handler=%p\n", handler); + + oldhandler = priv->handler; + + wdt_hal_write_protect_disable(priv->ctx); + + flags = enter_critical_section(); + + /* Save the new user handler */ + + priv->handler = handler; + + /* There is a user callback and the timer has already been started. + * The user wants to set a callback after starting the WDT or wants to + * change the callback function once a callback has already been settled. + */ + + if (priv->handler != NULL && priv->started) + { + if (oldhandler == NULL) + { + /* If it was previous configured to reset on timeout + * then change to interrupt. + */ + + if (priv->peripheral == TIMER) + { + timeout = MWDT_TIMEOUT_MS(priv->timeout); + } + else + { + timeout = RWDT_TIMEOUT_MS(priv->timeout); + } + + priv->action = WDT_STAGE_ACTION_INT; + + wdt_hal_config_stage(priv->ctx, WDT_STAGE0, + timeout, + priv->action); + } + + WDT_INTR_ENABLE(priv->peripheral, priv->ctx, true); + } + + /* In case the user wants to disable the callback */ + + else + { + if (priv->peripheral == TIMER) + { + timeout = MWDT_TIMEOUT_MS(priv->timeout); + priv->action = WDT_STAGE_ACTION_RESET_SYSTEM; + } + else + { + timeout = RWDT_TIMEOUT_MS(priv->timeout); + priv->action = WDT_STAGE_ACTION_RESET_RTC; + } + + WDT_INTR_ENABLE(priv->peripheral, priv->ctx, false); + + /* Then configure it to reset on WDT expiration */ + + wdt_hal_config_stage(priv->ctx, WDT_STAGE0, + timeout, + priv->action); + } + + leave_critical_section(flags); + + wdt_hal_write_protect_enable(priv->ctx); + + return oldhandler; +} + +/**************************************************************************** + * Name: wdt_handler + * + * Description: + * This is the WDT interrupt handler. It will be invoked when an + * interrupt is received on the device. + * + * Input Parameters: + * irq - IRQ associated to that interrupt. + * context - Interrupt register state save info. + * arg - A pointer to the argument provided when the interrupt + * was registered. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int wdt_handler(int irq, void *context, void *arg) +{ + struct esp_wdt_lowerhalf_s *priv = (struct esp_wdt_lowerhalf_s *)arg; + + /* Run the user callback */ + + priv->handler(irq, context, priv->upper); + + /* Clear the Interrupt */ + + wdt_hal_write_protect_disable(priv->ctx); + wdt_hal_handle_intr(priv->ctx); + wdt_hal_write_protect_enable(priv->ctx); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_wdt_initialize + * + * Description: + * Initialize the watchdog timer. + * + * Input Parameters: + * devpath - The full path to the watchdog. This should + * be of the form /dev/watchdogX + * wdt_id - A Watchdog Timer instance to be initialized. + * + * Returned Values: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int esp_wdt_initialize(const char *devpath, enum esp_wdt_inst_e wdt_id) +{ + struct esp_wdt_lowerhalf_s *lower = NULL; + + switch (wdt_id) + { +#ifdef CONFIG_ESPRESSIF_MWDT0 + case ESP_WDT_MWDT0: + { + lower = &g_esp_mwdt0_lowerhalf; + periph_module_enable(PERIPH_TIMG0_MODULE); + wdt_hal_init(lower->ctx, WDT_MWDT0, + MWDT_LL_DEFAULT_CLK_PRESCALER, true); + + break; + } + +#endif + +#ifdef CONFIG_ESPRESSIF_MWDT1 + case ESP_WDT_MWDT1: + { + lower = &g_esp_mwdt1_lowerhalf; + periph_module_enable(PERIPH_TIMG1_MODULE); + wdt_hal_init(lower->ctx, WDT_MWDT1, + MWDT_LL_DEFAULT_CLK_PRESCALER, true); + + break; + } + +#endif + +#ifdef CONFIG_ESPRESSIF_RWDT + case ESP_WDT_RWDT: + { + lower = &g_esp_rwdt_lowerhalf; + wdt_hal_init(lower->ctx, WDT_RWDT, 0, true); + esp_rtcioirqenable(lower->irq); + break; + } +#endif + + default: + { + wderr("ERROR: unsupported WDT %d\n", wdt_id); + return ERROR; + } + } + + /* Initialize the elements of lower half state structure */ + + lower->handler = NULL; + lower->timeout = 0; + lower->started = wdt_hal_is_enabled(lower->ctx); + + /* Register the watchdog driver as /dev/watchdogX. If the registration goes + * right the returned value from watchdog_register is a pointer to + * watchdog_upperhalf_s that can be either used with watchdog_unregister() + * or with the handler's arg. + */ + + lower->upper = watchdog_register(devpath, + (struct watchdog_lowerhalf_s *)lower); + if (lower->upper == NULL) + { + /* The actual cause of the failure may have been a failure to allocate + * perhaps a failure to register the watchdog driver (such as if the + * 'devpath' were not unique). We know here but we return EEXIST to + * indicate the failure (implying the non-unique devpath). + */ + + return -EEXIST; + } + + esp_setup_irq(lower->periph, + ESP_IRQ_PRIORITY_DEFAULT, + ESP_IRQ_TRIGGER_LEVEL); + + /* Attach the handler for the timer IRQ */ + + irq_attach(lower->irq, (xcpt_t)wdt_handler, lower); + + /* Enable the allocated CPU interrupt */ + + up_enable_irq(lower->irq); + + return OK; +} diff --git a/arch/risc-v/src/common/espressif/esp_wdt.h b/arch/risc-v/src/common/espressif/esp_wdt.h new file mode 100644 index 0000000000000..e3f904c202d1e --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_wdt.h @@ -0,0 +1,66 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_wdt.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_WDT_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_WDT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Instances of Watchdog Timer */ + +enum esp_wdt_inst_e +{ + ESP_WDT_MWDT0 = 0, /* Main System Watchdog Timer (MWDT) of Timer Group 0 */ + ESP_WDT_MWDT1, /* Main System Watchdog Timer (MWDT) of Timer Group 1 */ + ESP_WDT_RWDT /* RTC Watchdog Timer (RWDT) */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_wdt_initialize + * + * Description: + * Initialize the watchdog timer. + * + * Input Parameters: + * devpath - The full path to the watchdog. This should + * be of the form /dev/watchdogX + * wdt_id - A Watchdog Timer instance to be initialized. + * + * Returned Values: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int esp_wdt_initialize(const char *devpath, enum esp_wdt_inst_e wdt_id); + +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_WDT_H */ diff --git a/arch/risc-v/src/common/espressif/esp_wifi_init.c b/arch/risc-v/src/common/espressif/esp_wifi_init.c new file mode 100644 index 0000000000000..ba94d12eaf8f4 --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_wifi_init.c @@ -0,0 +1,465 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_wifi_init.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this args for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include "esp_log.h" +#include "esp_private/wifi.h" +#include "esp_private/adc_share_hw_ctrl.h" +#include "esp_private/sleep_modem.h" +#include "esp_sleep.h" +#include "esp_private/esp_clk.h" +#include "esp_wpa.h" +#include "esp_coexist_internal.h" +#include "esp_phy_init.h" +#include "esp_private/phy.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if (CONFIG_ESPRESSIF_WIFI_RX_BA_WIN > CONFIG_ESPRESSIF_WIFI_DYNAMIC_RX_BUFFER_NUM) +#error "WiFi configuration check: WARNING, WIFI_RX_BA_WIN should not be larger than WIFI_DYNAMIC_RX_BUFFER_NUM!" +#endif + +#if (CONFIG_ESPRESSIF_WIFI_RX_BA_WIN > (CONFIG_ESPRESSIF_WIFI_STATIC_RX_BUFFER_NUM << 1)) +#error "WiFi configuration check: WARNING, WIFI_RX_BA_WIN should not be larger than double of the WIFI_STATIC_RX_BUFFER_NUM!" +#endif + +#if SOC_PM_SUPPORT_PMU_MODEM_STATE +# define WIFI_BEACON_MONITOR_CONFIG_DEFAULT(ena) { \ + .enable = (ena), \ + .loss_timeout = CONFIG_ESP_WIFI_SLP_BEACON_LOST_TIMEOUT, \ + .loss_threshold = CONFIG_ESP_WIFI_SLP_BEACON_LOST_THRESHOLD, \ + .delta_intr_early = 0, \ + .delta_loss_timeout = 0, \ + .beacon_abort = 1, \ + .broadcast_wakeup = 1, \ + .tsf_time_sync_deviation = 5, \ + .modem_state_consecutive = 10, \ + .rf_ctrl_wait_cycle = 20 \ +} +#else +# define WIFI_BEACON_MONITOR_CONFIG_DEFAULT(ena) { \ + .enable = (ena), \ + .loss_timeout = CONFIG_ESP_WIFI_SLP_BEACON_LOST_TIMEOUT, \ + .loss_threshold = CONFIG_ESP_WIFI_SLP_BEACON_LOST_THRESHOLD, \ + .delta_intr_early = CONFIG_ESP_WIFI_SLP_PHY_ON_DELTA_EARLY_TIME, \ + .delta_loss_timeout = CONFIG_ESP_WIFI_SLP_PHY_OFF_DELTA_TIMEOUT_TIME \ +} +#endif + +/* Set additional WiFi features and capabilities */ + +uint64_t g_wifi_feature_caps = +#if CONFIG_ESP_WIFI_ENABLE_WPA3_SAE + CONFIG_FEATURE_WPA3_SAE_BIT | +#endif +#if CONFIG_SPIRAM + CONFIG_FEATURE_CACHE_TX_BUF_BIT | +#endif +#if CONFIG_ESP_WIFI_FTM_INITIATOR_SUPPORT + CONFIG_FEATURE_FTM_INITIATOR_BIT | +#endif +#if CONFIG_ESP_WIFI_FTM_RESPONDER_SUPPORT + CONFIG_FEATURE_FTM_RESPONDER_BIT | +#endif + 0; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void esp_wifi_set_log_level(void); +static void esp_wifi_config_info(void); + +extern uint8_t esp_wifi_get_user_init_flag_internal(void); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +ESP_EVENT_DEFINE_BASE(WIFI_EVENT); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_wifi_set_log_level + * + * Description: + * Sets the log level for the ESP32 WiFi module based on preprocessor + * definitions. The log level can be verbose, warning, or error. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_wifi_set_log_level(void) +{ + wifi_log_level_t wifi_log_level = WIFI_LOG_NONE; + + /* set WiFi log level */ + +#if defined(CONFIG_DEBUG_WIRELESS_INFO) + wifi_log_level = WIFI_LOG_VERBOSE; +#elif defined(CONFIG_DEBUG_WIRELESS_WARN) + wifi_log_level = WIFI_LOG_WARNING; +#elif defined(CONFIG_LOG_MAXIMUM_LEVEL) + wifi_log_level = WIFI_LOG_ERROR; +#endif + + esp_wifi_internal_set_log_level(wifi_log_level); +} + +/**************************************************************************** + * Name: esp_wifi_config_info + * + * Description: + * This function logs the current configuration settings for the Wi-Fi + * module. It checks for various configuration options and logs if they + * are enabled. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_wifi_config_info(void) +{ +#ifdef CONFIG_ESPRESSIF_WIFI_RX_BA_WIN + wlinfo("rx ba win: %d", CONFIG_ESPRESSIF_WIFI_RX_BA_WIN); +#endif + +#ifdef CONFIG_SPIRAM_TRY_ALLOCATE_WIFI_LWIP + wlinfo("WiFi/LWIP prefer SPIRAM"); +#endif + +#ifdef CONFIG_ESP_WIFI_IRAM_OPT + wlinfo("WiFi IRAM OP enabled"); +#endif + +#ifdef CONFIG_ESP_WIFI_RX_IRAM_OPT + wlinfo("WiFi RX IRAM OP enabled"); +#endif + +#ifdef CONFIG_ESP_WIFI_SLP_IRAM_OPT + wlinfo("WiFi SLP IRAM OP enabled"); +#endif + +#ifdef CONFIG_LWIP_IRAM_OPTIMIZATION + wlinfo("LWIP IRAM OP enabled"); +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifndef CONFIG_ESP_WIFI_FTM_ENABLE + +/**************************************************************************** + * Name: ieee80211_ftm_attach + * + * Description: + * This function initializes and attaches the Fine Timing Measurement (FTM) + * capabilities to the IEEE 802.11 Wi-Fi driver. FTM is used for precise + * distance measurements between Wi-Fi devices. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void ieee80211_ftm_attach(void) +{ + /* Do not remove, stub to overwrite weak link in Wi-Fi Lib */ +} +#endif + +#ifndef CONFIG_ESP_WIFI_SOFTAP_SUPPORT + +/**************************************************************************** + * Name: net80211_softap_funcs_init + * + * Description: + * This function is a placeholder for initializing the SoftAP (Software + * Access Point) functionalities of the IEEE 802.11 Wi-Fi driver. It is + * only compiled if the CONFIG_ESP_WIFI_SOFTAP_SUPPORT configuration + * option is not set. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void net80211_softap_funcs_init(void) +{ +} +#endif + +#ifndef CONFIG_ESP_WIFI_NAN_ENABLE + +/**************************************************************************** + * Name: nan_start + * + * Description: + * This function is a stub to overwrite a weak link in the Wi-Fi library. + * It is used to start the NAN (Neighbor Awareness Networking) service. + * + * Input Parameters: + * None + * + * Returned Value: + * Always returns ESP_OK. + * + ****************************************************************************/ + +esp_err_t nan_start(void) +{ + /* Do not remove, stub to overwrite weak link in Wi-Fi Lib */ + + return ESP_OK; +} + +/**************************************************************************** + * Name: nan_stop + * + * Description: + * This function is a stub to overwrite a weak link in the Wi-Fi library. + * It is used to stop the NAN (Neighbor Awareness Networking) service. + * + * Input Parameters: + * None + * + * Returned Value: + * Always returns ESP_OK. + * + ****************************************************************************/ + +esp_err_t nan_stop(void) +{ + /* Do not remove, stub to overwrite weak link in Wi-Fi Lib */ + + return ESP_OK; +} + +/**************************************************************************** + * Name: nan_input + * + * Description: + * This function is a stub to overwrite a weak link in the Wi-Fi library. + * It is used to handle input for the NAN (Neighbor Awareness Networking) + * service. + * + * Input Parameters: + * p1 - First parameter for the input function. + * p2 - Second parameter for the input function. + * p3 - Third parameter for the input function. + * + * Returned Value: + * Always returns 0. + * + ****************************************************************************/ + +int nan_input(void *p1, int p2, int p3) +{ + /* Do not remove, stub to overwrite weak link in Wi-Fi Lib */ + + return 0; +} + +/**************************************************************************** + * Name: nan_sm_handle_event + * + * Description: + * This function is a stub to overwrite a weak link in the Wi-Fi library. + * It is used to handle events for the NAN (Neighbor Awareness Networking) + * service state machine. + * + * Input Parameters: + * p1 - First parameter for the event handler. + * p2 - Second parameter for the event handler. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void nan_sm_handle_event(void *p1, int p2) +{ + /* Do not remove, stub to overwrite weak link in Wi-Fi Lib */ +} +#endif + +/**************************************************************************** + * Name: esp_wifi_deinit + * + * Description: + * Deinitialize Wi-Fi and free resource + * + * Input Parameters: + * None + * + * Returned Values: esp_err_t + * Zero (OK) is returned or a negative error. + * + ****************************************************************************/ + +esp_err_t esp_wifi_deinit(void) +{ + esp_err_t err = ESP_OK; +#ifdef CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT + wifi_beacon_monitor_config_t monitor_config; +#endif + + if (esp_wifi_get_user_init_flag_internal()) + { + wlerr("Wi-Fi not stop"); + return ESP_ERR_WIFI_NOT_STOPPED; + } + + if (esp_wifi_internal_reg_rxcb(WIFI_IF_STA, NULL) != ESP_OK || + esp_wifi_internal_reg_rxcb(WIFI_IF_AP, NULL) != ESP_OK) + { + wlerr("Failed to unregister Rx callbacks"); + } + + esp_supplicant_deinit(); + err = esp_wifi_deinit_internal(); + if (err != ESP_OK) + { + wlerr("Failed to deinit Wi-Fi driver (0x%x)", err); + return err; + } + +#ifdef CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT + monitor_config = WIFI_BEACON_MONITOR_CONFIG_DEFAULT(false); + esp_wifi_beacon_monitor_configure(&monitor_config); +#endif + +#if CONFIG_MAC_BB_PD + esp_unregister_mac_bb_pd_callback(pm_mac_sleep); + esp_unregister_mac_bb_pu_callback(pm_mac_wakeup); +#endif + esp_wifi_power_domain_off(); +#if CONFIG_MAC_BB_PD + esp_wifi_internal_set_mac_sleep(false); + esp_mac_bb_pd_mem_deinit(); +#endif + esp_phy_modem_deinit(); + + return err; +} + +/**************************************************************************** + * Name: esp_wifi_init + * + * Description: + * Initialize Wi-Fi + * + * Input Parameters: + * config - Initialization config parameters + * + * Returned Values: esp_err_t + * Zero (OK) is returned or a negative error. + * + ****************************************************************************/ + +esp_err_t esp_wifi_init(const wifi_init_config_t *config) +{ + esp_err_t result = ESP_OK; +#ifdef CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT + wifi_beacon_monitor_config_t monitor_config; +#endif + + if ((config->feature_caps & CONFIG_FEATURE_CACHE_TX_BUF_BIT) && + (WIFI_CACHE_TX_BUFFER_NUM == 0)) + { + wlerr("Number of WiFi cache TX buffers should not equal 0 when" + "enable SPIRAM"); + return ESP_ERR_NOT_SUPPORTED; + } + + esp_wifi_power_domain_on(); + +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + coex_init(); +#endif + esp_wifi_set_log_level(); + + result = esp_wifi_init_internal(config); + if (result == ESP_OK) + { +#if CONFIG_MAC_BB_PD + esp_mac_bb_pd_mem_init(); + esp_wifi_internal_set_mac_sleep(true); +#endif + esp_phy_modem_init(); + + result = esp_supplicant_init(); + if (result != ESP_OK) + { + esp_err_t deinit_ret; + + wlerr("Failed to init supplicant (0x%x)", result); + + deinit_ret = esp_wifi_deinit(); + if (deinit_ret != ESP_OK) + { + wlerr("Failed to deinit Wi-Fi (0x%x)", deinit_ret); + } + + return result; + } + } + +#if CONFIG_ESP_WIFI_SLP_BEACON_LOST_OPT + monitor_config = WIFI_BEACON_MONITOR_CONFIG_DEFAULT(true); + esp_wifi_beacon_monitor_configure(&monitor_config); +#endif + adc2_cal_include(); /* This enables the ADC2 calibration constructor at start up */ + + esp_wifi_config_info(); + + return result; +} diff --git a/arch/risc-v/src/common/espressif/esp_wifi_utils.c b/arch/risc-v/src/common/espressif/esp_wifi_utils.c new file mode 100644 index 0000000000000..21019a78f4f6c --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_wifi_utils.c @@ -0,0 +1,654 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_wifi_utils.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "esp_wifi_adapter.h" + +#include "esp_log.h" +#include "esp_mac.h" +#include "esp_private/phy.h" +#include "esp_private/wifi.h" +#include "esp_random.h" +#include "esp_timer.h" +#include "esp_wpa.h" +#include "rom/ets_sys.h" +#include "soc/soc_caps.h" + +#include "esp_wifi_utils.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Helper to get iw_event size */ + +#define ESP_IW_EVENT_SIZE(field) \ + (offsetof(struct iw_event, u) + sizeof(((union iwreq_data *)0)->field)) + +#ifdef CONFIG_ESPRESSIF_WIFI_SCAN_RESULT_SIZE +# define WIFI_SCAN_RESULT_SIZE CONFIG_ESPRESSIF_WIFI_SCAN_RESULT_SIZE +#else +# define WIFI_SCAN_RESULT_SIZE (4096) +#endif + +#define SCAN_TIME_SEC (5) + +/* Maximum number of channels for Wi-Fi 2.4Ghz */ + +#define CHANNEL_MAX_NUM (14) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +enum scan_status_e +{ + ESP_SCAN_DISABLED = 0, + ESP_SCAN_RUN, + ESP_SCAN_DONE +}; + +/* Wi-Fi scan result information */ + +struct wifi_scan_result +{ + enum scan_status_e scan_status; /* Scan status */ + sem_t scan_signal; /* Scan notification signal */ + uint8_t *scan_result; /* Temp buffer that holds results */ + unsigned int scan_result_size; /* Current size of temp buffer */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct wifi_scan_result g_scan_priv = +{ + .scan_signal = SEM_INITIALIZER(0), +}; +static uint8_t g_channel_num; +static uint8_t g_channel_list[CHANNEL_MAX_NUM]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_wifi_start_scan + * + * Description: + * Scan all available APs. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_start_scan(struct iwreq *iwr) +{ + struct wifi_scan_result *priv = &g_scan_priv; + wifi_scan_config_t *config = NULL; + struct iw_scan_req *req; + int ret = 0; + int i; + uint8_t target_mac[MAC_LEN]; + uint8_t target_ssid[SSID_MAX_LEN + 1]; + memset(target_ssid, 0x0, sizeof(SSID_MAX_LEN + 1)); + + if (iwr == NULL) + { + wlerr("ERROR: Invalid ioctl cmd.\n"); + return -EINVAL; + } + + if (g_scan_priv.scan_status != ESP_SCAN_DISABLED) + { + return OK; + } + + config = kmm_calloc(1, sizeof(wifi_scan_config_t)); + if (config == NULL) + { + wlerr("ERROR: Cannot allocate result buffer\n"); + return -ENOMEM; + } + + g_channel_num = 0; + memset(g_channel_list, 0x0, CHANNEL_MAX_NUM); + + if (iwr->u.data.pointer && + iwr->u.data.length >= sizeof(struct iw_scan_req)) + { + req = (struct iw_scan_req *)iwr->u.data.pointer; + config->scan_type = (req->scan_type == IW_SCAN_TYPE_ACTIVE ? + WIFI_SCAN_TYPE_ACTIVE : WIFI_SCAN_TYPE_PASSIVE); + if (iwr->u.data.flags & IW_SCAN_THIS_ESSID && + req->essid_len < sizeof(target_ssid)) + { + /* Scan specific ESSID */ + + config->show_hidden = true; + config->bssid = NULL; + memcpy(&target_ssid[0], req->essid, req->essid_len); + config->ssid = &target_ssid[0]; + config->ssid[req->essid_len] = '\0'; + } + + if (iwr->u.data.flags & IW_SCAN_THIS_FREQ && + req->num_channels > 0) + { + /* Scan specific channels */ + + DEBUGASSERT(req->num_channels <= CHANNEL_MAX_NUM); + g_channel_num = req->num_channels; + if (req->num_channels == 1) + { + config->channel = req->channel_list[0].m; + } + else + { + for (i = 0; i < req->num_channels; i++) + { + g_channel_list[i] = req->channel_list[i].m; + } + } + } + + memset(target_mac, 0xff, MAC_LEN); + if (memcmp(req->bssid.sa_data, target_mac, MAC_LEN) != 0) + { + /* Scan specific bssid */ + + memcpy(target_mac, req->bssid.sa_data, MAC_LEN); + config->bssid = &target_mac[0]; + } + } + else + { + /* Default scan parameters */ + + wlinfo("INFO: Use default scan parameters\n"); + config->scan_type = WIFI_SCAN_TYPE_ACTIVE; /* Active scan */ + } + + esp_wifi_start(); + ret = esp_wifi_scan_start(config, false); + if (ret != OK) + { + wlerr("ERROR: Scan error, ret: %d\n", ret); + ret = ERROR; + } + else + { + /* Allocate buffer to store scan result */ + + if (priv->scan_result == NULL) + { + priv->scan_result = kmm_malloc(WIFI_SCAN_RESULT_SIZE); + if (priv->scan_result == NULL) + { + wlerr("ERROR: Cannot allocate result buffer\n"); + ret = -ENOMEM; + } + else + { + memset(priv->scan_result, 0x0, WIFI_SCAN_RESULT_SIZE); + } + } + } + + if (config) + { + kmm_free(config); + config = NULL; + } + + if (ret == OK) + { + wlinfo("INFO: start scan\n"); + g_scan_priv.scan_status = ESP_SCAN_RUN; + } + + return ret; +} + +/**************************************************************************** + * Name: esp_wifi_get_scan_results + * + * Description: + * Get scan result + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_get_scan_results(struct iwreq *iwr) +{ + int ret = OK; + static bool scan_block = false; + struct wifi_scan_result *priv = &g_scan_priv; + + if (g_scan_priv.scan_status == ESP_SCAN_RUN) + { + irqstate_t irqstate = enter_critical_section(); + if (!scan_block) + { + scan_block = true; + leave_critical_section(irqstate); + nxsem_tickwait(&priv->scan_signal, SEC2TICK(SCAN_TIME_SEC)); + scan_block = false; + } + else + { + leave_critical_section(irqstate); + ret = -EINVAL; + goto exit_failed; + } + } + else if (g_scan_priv.scan_status == ESP_SCAN_DISABLED) + { + ret = -EINVAL; + goto exit_failed; + } + + if ((iwr == NULL) || (g_scan_priv.scan_status != ESP_SCAN_DONE)) + { + ret = -EINVAL; + goto exit_failed; + } + + if (priv->scan_result == NULL) + { + /* Result have already been requested */ + + ret = OK; + iwr->u.data.length = 0; + goto exit_failed; + } + + if (priv->scan_result_size <= 0) + { + ret = OK; + iwr->u.data.length = 0; + goto exit_free_buffer; + } + + if (iwr->u.data.pointer == NULL || + iwr->u.data.length < priv->scan_result_size) + { + /* Stat request, return scan_result_size */ + + ret = -E2BIG; + iwr->u.data.pointer = NULL; + iwr->u.data.length = priv->scan_result_size; + return ret; + } + + /* Copy result to user buffer */ + + if (iwr->u.data.length > priv->scan_result_size) + { + iwr->u.data.length = priv->scan_result_size; + } + + memcpy(iwr->u.data.pointer, priv->scan_result, iwr->u.data.length); + +exit_free_buffer: + + /* Free scan result buffer */ + + kmm_free(priv->scan_result); + priv->scan_result = NULL; + priv->scan_result_size = 0; + g_scan_priv.scan_status = ESP_SCAN_DISABLED; + +exit_failed: + if (ret < 0) + { + iwr->u.data.length = 0; + } + + return ret; +} + +/**************************************************************************** + * Name: esp_wifi_scan_event_parse + * + * Description: + * Parse scan information + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp_wifi_scan_event_parse(void) +{ + struct wifi_scan_result *priv = &g_scan_priv; + wifi_ap_record_t *ap_list_buffer = NULL; + uint16_t bss_total = 0; + uint8_t bss_count = 0; + bool parse_done = false; + + if (priv->scan_status != ESP_SCAN_RUN) + { + return; + } + + esp_wifi_scan_get_ap_num(&bss_total); + if (bss_total == 0) + { + priv->scan_status = ESP_SCAN_DONE; + wlinfo("INFO: None AP is scanned\n"); + nxsem_post(&priv->scan_signal); + return; + } + + ap_list_buffer = kmm_calloc(bss_total, sizeof(wifi_ap_record_t)); + if (ap_list_buffer == NULL) + { + priv->scan_status = ESP_SCAN_DONE; + wlerr("ERROR: Failed to calloc buffer to print scan results"); + nxsem_post(&priv->scan_signal); + return; + } + + if (esp_wifi_scan_get_ap_records(&bss_total, + (wifi_ap_record_t *)ap_list_buffer) == OK) + { + struct iw_event *iwe; + unsigned int result_size; + size_t essid_len; + size_t essid_len_aligned; + bool is_target_channel = true; + int i; + + for (bss_count = 0; bss_count < bss_total; bss_count++) + { + if (g_channel_num > 1) + { + is_target_channel = false; + for (i = 0; i < g_channel_num; i++) + { + if (g_channel_list[i] == ap_list_buffer[bss_count].primary) + { + is_target_channel = true; + break; + } + } + } + else + { + is_target_channel = true; + } + + if (is_target_channel) + { + result_size = WIFI_SCAN_RESULT_SIZE - priv->scan_result_size; + + /* Copy BSSID */ + + if (result_size < ESP_IW_EVENT_SIZE(ap_addr)) + { + goto scan_result_full; + } + + iwe = (struct iw_event *) + &priv->scan_result[priv->scan_result_size]; + iwe->len = ESP_IW_EVENT_SIZE(ap_addr); + iwe->cmd = SIOCGIWAP; + memcpy(&iwe->u.ap_addr.sa_data, + ap_list_buffer[bss_count].bssid, + sizeof(ap_list_buffer[bss_count].bssid)); + iwe->u.ap_addr.sa_family = ARPHRD_ETHER; + priv->scan_result_size += ESP_IW_EVENT_SIZE(ap_addr); + result_size -= ESP_IW_EVENT_SIZE(ap_addr); + + /* Copy ESSID */ + + essid_len = MIN(strlen((const char *) + ap_list_buffer[bss_count].ssid), SSID_MAX_LEN); + essid_len_aligned = (essid_len + 3) & -4; + if (result_size < ESP_IW_EVENT_SIZE(essid) + essid_len_aligned) + { + goto scan_result_full; + } + + iwe = (struct iw_event *) + &priv->scan_result[priv->scan_result_size]; + iwe->len = ESP_IW_EVENT_SIZE(essid) + essid_len_aligned; + iwe->cmd = SIOCGIWESSID; + iwe->u.essid.flags = 0; + iwe->u.essid.length = essid_len; + + /* Special processing for iw_point, set offset + * in pointer field. + */ + + iwe->u.essid.pointer = (void *)sizeof(iwe->u.essid); + memcpy(&iwe->u.essid + 1, + ap_list_buffer[bss_count].ssid, essid_len); + + wlinfo("INFO: ssid %s\n", ap_list_buffer[bss_count].ssid); + + priv->scan_result_size += + ESP_IW_EVENT_SIZE(essid) + essid_len_aligned; + result_size -= ESP_IW_EVENT_SIZE(essid) + essid_len_aligned; + + /* Copy link quality info */ + + if (result_size < ESP_IW_EVENT_SIZE(qual)) + { + goto scan_result_full; + } + + iwe = (struct iw_event *) + &priv->scan_result[priv->scan_result_size]; + iwe->len = ESP_IW_EVENT_SIZE(qual); + iwe->cmd = IWEVQUAL; + iwe->u.qual.qual = 0x00; + + wlinfo("INFO: signal %d\n", ap_list_buffer[bss_count].rssi); + + iwe->u.qual.level = ap_list_buffer[bss_count].rssi; + iwe->u.qual.noise = 0x00; + iwe->u.qual.updated = IW_QUAL_DBM | IW_QUAL_ALL_UPDATED; + + priv->scan_result_size += ESP_IW_EVENT_SIZE(qual); + result_size -= ESP_IW_EVENT_SIZE(qual); + + /* Copy AP mode */ + + if (result_size < ESP_IW_EVENT_SIZE(mode)) + { + goto scan_result_full; + } + + iwe = (struct iw_event *) + &priv->scan_result[priv->scan_result_size]; + iwe->len = ESP_IW_EVENT_SIZE(mode); + iwe->cmd = SIOCGIWMODE; + iwe->u.mode = IW_MODE_MASTER; + priv->scan_result_size += ESP_IW_EVENT_SIZE(mode); + result_size -= ESP_IW_EVENT_SIZE(mode); + + /* Copy AP encryption mode */ + + if (result_size < ESP_IW_EVENT_SIZE(data)) + { + goto scan_result_full; + } + + iwe = (struct iw_event *) + &priv->scan_result[priv->scan_result_size]; + iwe->len = ESP_IW_EVENT_SIZE(data); + iwe->cmd = SIOCGIWENCODE; + iwe->u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; + iwe->u.data.length = 0; + iwe->u.essid.pointer = NULL; + + priv->scan_result_size += ESP_IW_EVENT_SIZE(data); + result_size -= ESP_IW_EVENT_SIZE(data); + + /* Copy AP channel */ + + if (result_size < ESP_IW_EVENT_SIZE(freq)) + { + goto scan_result_full; + } + + iwe = (struct iw_event *) + &priv->scan_result[priv->scan_result_size]; + iwe->len = ESP_IW_EVENT_SIZE(freq); + iwe->cmd = SIOCGIWFREQ; + iwe->u.freq.e = 0; + iwe->u.freq.m = ap_list_buffer[bss_count].primary; + + priv->scan_result_size += ESP_IW_EVENT_SIZE(freq); + result_size -= ESP_IW_EVENT_SIZE(freq); + } + } + + parse_done = true; + } + +scan_result_full: + + /* Continue instead of break to log dropped AP results */ + + if (!parse_done) + { + wlerr("ERROR: No more space in scan_result buffer\n"); + } + + if (ap_list_buffer) + { + kmm_free(ap_list_buffer); + ap_list_buffer = NULL; + } + + priv->scan_status = ESP_SCAN_DONE; + nxsem_post(&priv->scan_signal); +} + +/**************************************************************************** + * Name: esp_wifi_to_errno + * + * Description: + * Transform from ESP Wi-Fi error code to NuttX error code + * + * Input Parameters: + * err - ESP Wi-Fi error code + * + * Returned Value: + * NuttX error code defined in errno.h + * + ****************************************************************************/ + +int32_t esp_wifi_to_errno(int err) +{ + int ret; + + if (err < ESP_ERR_WIFI_BASE) + { + /* Unmask component error bits */ + + ret = err & 0xfff; + + switch (ret) + { + case ESP_OK: + ret = OK; + break; + case ESP_ERR_NO_MEM: + ret = -ENOMEM; + break; + + case ESP_ERR_INVALID_ARG: + ret = -EINVAL; + break; + + case ESP_ERR_INVALID_STATE: + ret = -EIO; + break; + + case ESP_ERR_INVALID_SIZE: + ret = -EINVAL; + break; + + case ESP_ERR_NOT_FOUND: + ret = -ENOSYS; + break; + + case ESP_ERR_NOT_SUPPORTED: + ret = -ENOSYS; + break; + + case ESP_ERR_TIMEOUT: + ret = -ETIMEDOUT; + break; + + case ESP_ERR_INVALID_MAC: + ret = -EINVAL; + break; + + default: + ret = ERROR; + break; + } + } + else + { + ret = ERROR; + } + + if (ret != OK) + { + wlerr("ERROR: %s\n", esp_err_to_name(err)); + } + + return ret; +} diff --git a/arch/risc-v/src/common/espressif/esp_wifi_utils.h b/arch/risc-v/src/common/espressif/esp_wifi_utils.h new file mode 100644 index 0000000000000..738fbbed08ee5 --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_wifi_utils.h @@ -0,0 +1,120 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_wifi_utils.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_WIFI_UTILS_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_WIFI_UTILS_H + +#include +#include + +#ifndef __ASSEMBLY__ + +#include + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_wifi_start_scan + * + * Description: + * Scan all available APs. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_start_scan(struct iwreq *iwr); + +/**************************************************************************** + * Name: esp_wifi_get_scan_results + * + * Description: + * Get scan result + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_get_scan_results(struct iwreq *iwr); + +/**************************************************************************** + * Name: esp_wifi_scan_event_parse + * + * Description: + * Parse scan information + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp_wifi_scan_event_parse(void); + +/**************************************************************************** + * Name: esp_wifi_to_errno + * + * Description: + * Transform from ESP Wi-Fi error code to NuttX error code + * + * Input Parameters: + * err - ESP Wi-Fi error code + * + * Returned Value: + * NuttX error code defined in errno.h + * + ****************************************************************************/ + +int32_t esp_wifi_to_errno(int err); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_WIFI_UTILS_H */ diff --git a/arch/risc-v/src/common/espressif/esp_wlan.c b/arch/risc-v/src/common/espressif/esp_wlan.c new file mode 100644 index 0000000000000..443b8d525caad --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_wlan.c @@ -0,0 +1,1731 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_wlan.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_ESPRESSIF_WIFI + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_NET_PKT) +# include +#endif + +#include "esp_systemreset.h" +#include "esp_wlan.h" +#include "esp_wifi_utils.h" +#include "esp_wifi_adapter.h" + +#include "esp_attr.h" +#include "esp_mac.h" +#include "esp_private/wifi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* TX timeout = 1 minute */ + +#define WLAN_TXTOUT (60 * CLK_TCK) + +/* Low-priority work queue processes RX/TX */ + +#define WLAN_WORK LPWORK + +/* Ethernet frame: + * Resource address : 6 bytes + * Destination address: 6 bytes + * Type : 2 bytes + * Payload : MAX 1500 + * Checksum : Ignore + * + * Total size : 1514 + */ + +#define WLAN_BUF_SIZE (CONFIG_NET_ETH_PKTSIZE + \ + CONFIG_NET_LL_GUARDSIZE + \ + CONFIG_NET_GUARDSIZE) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* WLAN operations */ + +struct wlan_ops +{ + int (*start)(void); + int (*send)(void *pdata, size_t n); + int (*essid)(struct iwreq *iwr, bool set); + int (*bssid)(struct iwreq *iwr, bool set); + int (*passwd)(struct iwreq *iwr, bool set); + int (*mode)(struct iwreq *iwr, bool set); + int (*auth)(struct iwreq *iwr, bool set); + int (*freq)(struct iwreq *iwr, bool set); + int (*bitrate)(struct iwreq *iwr, bool set); + int (*txpower)(struct iwreq *iwr, bool set); + int (*channel)(struct iwreq *iwr, bool set); + int (*country)(struct iwreq *iwr, bool set); + int (*rssi)(struct iwreq *iwr, bool set); + int (*connect)(void); + int (*disconnect)(void); + int (*event)(pid_t pid, struct sigevent *event); + int (*stop)(void); +}; + +/* The wlan_priv_s encapsulates all state information for a single + * hardware interface + */ + +struct wlan_priv_s +{ + int ref; /* Reference count */ + + bool ifup; /* true:ifup false:ifdown */ + + struct wdog_s txtimeout; /* TX timeout timer */ + + struct work_s rxwork; /* Send packet work */ + struct work_s txwork; /* Receive packet work */ + struct work_s pollwork; /* Poll work */ + struct work_s toutwork; /* Send packet timeout work */ + + const struct wlan_ops *ops; /* WLAN operations */ + + /* This holds the information visible to the NuttX network */ + + struct net_driver_s dev; + + /* RX packet queue */ + + struct iob_queue_s rxb; + + /* TX ready packet queue */ + + struct iob_queue_s txb; + + /* Flat buffer swap */ + + uint8_t flatbuf[WLAN_BUF_SIZE]; + + spinlock_t lock; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Reference count of register Wi-Fi handler */ + +static uint8_t g_callback_register_ref; + +static struct wlan_priv_s g_wlan_priv[ESP_WLAN_DEVS]; + +#ifdef ESP_WLAN_HAS_STA +static const struct wlan_ops g_sta_ops = +{ + .start = esp_wifi_sta_start, + .send = esp_wifi_sta_send_data, + .essid = esp_wifi_sta_essid, + .bssid = esp_wifi_sta_bssid, + .passwd = esp_wifi_sta_password, + .mode = esp_wifi_sta_mode, + .auth = esp_wifi_sta_auth, + .freq = esp_wifi_sta_freq, + .bitrate = esp_wifi_sta_bitrate, + .txpower = esp_wifi_sta_txpower, + .channel = esp_wifi_sta_channel, + .country = esp_wifi_sta_country, + .rssi = esp_wifi_sta_rssi, + .connect = esp_wifi_sta_connect, + .disconnect = esp_wifi_sta_disconnect, + .event = esp_wifi_notify_subscribe, + .stop = esp_wifi_sta_stop +}; +#endif /* ESP_WLAN_HAS_STA */ + +#ifdef ESP_WLAN_HAS_SOFTAP +static const struct wlan_ops g_softap_ops = +{ + .start = esp_wifi_softap_start, + .send = esp_wifi_softap_send_data, + .essid = esp_wifi_softap_essid, + .bssid = esp_wifi_softap_bssid, + .passwd = esp_wifi_softap_password, + .mode = esp_wifi_softap_mode, + .auth = esp_wifi_softap_auth, + .freq = esp_wifi_softap_freq, + .bitrate = esp_wifi_softap_bitrate, + .txpower = esp_wifi_softap_txpower, + .channel = esp_wifi_softap_channel, + .country = esp_wifi_softap_country, + .rssi = esp_wifi_softap_rssi, + .connect = esp_wifi_softap_connect, + .disconnect = esp_wifi_softap_disconnect, + .event = esp_wifi_notify_subscribe, + .stop = esp_wifi_softap_stop +}; +#endif /* ESP_WLAN_HAS_SOFTAP */ + +/* Wi-Fi station TX done callback function */ + +static wifi_tx_done_cb_t g_sta_txdone_cb; + +/* Wi-Fi SoftAP TX done callback function */ + +static wifi_tx_done_cb_t g_softap_txdone_cb; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Common TX logic */ + +static void wlan_transmit(struct wlan_priv_s *priv); +static void wlan_rxpoll(void *arg); +static int wlan_txpoll(struct net_driver_s *dev); +static void wlan_dopoll(struct wlan_priv_s *priv); + +/* Watchdog timer expirations */ + +static void wlan_txtimeout_work(void *arg); +static void wlan_txtimeout_expiry(wdparm_t arg); + +/* NuttX callback functions */ + +static int wlan_ifup(struct net_driver_s *dev); +static int wlan_ifdown(struct net_driver_s *dev); + +static void wlan_txavail_work(void *arg); +static int wlan_txavail(struct net_driver_s *dev); + +#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6) +static int wlan_addmac(struct net_driver_s *dev, const uint8_t *mac); +#endif + +#ifdef CONFIG_NET_MCASTGROUP +static int wlan_rmmac(struct net_driver_s *dev, const uint8_t *mac); +#endif + +#ifdef CONFIG_NETDEV_IOCTL +static int wlan_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg); +#endif + +static void esp_wifi_stop_callback(void); +static void esp_wifi_free_eb(void *eb); +#ifdef ESP_WLAN_HAS_STA +static int esp_wifi_sta_register_recv_cb(int (*recv_cb)(void *buffer, + uint16_t len, + void *eb)); +static void esp_wifi_sta_register_txdone_cb(wifi_tx_done_cb_t cb); +#endif /* ESP_WLAN_HAS_STA */ +#ifdef ESP_WLAN_HAS_SOFTAP +static int esp_wifi_softap_register_recv_cb(int (*recv_cb)(void *buffer, + uint16_t len, + void *eb)); +static void esp_wifi_softap_register_txdone_cb(wifi_tx_done_cb_t cb); +#endif /* ESP_WLAN_HAS_SOFTAP */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Note: + * All TX done/RX done/Error trigger functions are not called from + * interrupts, this is much different from ethernet driver, including: + * * wlan_rx_done + * * wlan_tx_done + * + * These functions are called in a Wi-Fi private thread. So we just use + * mutex/semaphore instead of disable interrupt, if necessary. + */ + +/**************************************************************************** + * Function: wlan_cache_txpkt_tail + * + * Description: + * Cache packet from dev->d_buf into tail of TX ready queue. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void wlan_cache_txpkt_tail(struct wlan_priv_s *priv) +{ + if (priv->dev.d_iob) + { + iob_tryadd_queue(priv->dev.d_iob, &priv->txb); + } + + netdev_iob_clear(&priv->dev); +} + +/**************************************************************************** + * Function: wlan_recvframe + * + * Description: + * Try to receive RX packet from RX done packet queue. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * RX packet if success or NULl if no packet in queue. + * + ****************************************************************************/ + +static struct iob_s *wlan_recvframe(struct wlan_priv_s *priv) +{ + struct iob_s *iob; + + iob = iob_remove_queue(&priv->rxb); + + return iob; +} + +/**************************************************************************** + * Name: wlan_transmit + * + * Description: + * Try to send all TX packets in TX ready queue to Wi-Fi driver. If this + * sending fails, then breaks loop and returns. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wlan_transmit(struct wlan_priv_s *priv) +{ + uint16_t llhdrlen = NET_LL_HDRLEN(&priv->dev); + unsigned int offset = CONFIG_NET_LL_GUARDSIZE - llhdrlen; + struct iob_s *iob; + int ret; + + while ((iob = iob_peek_queue(&priv->txb)) != NULL) + { + iob_copyout(priv->flatbuf + llhdrlen, iob, iob->io_pktlen, 0); + memcpy(priv->flatbuf, iob->io_data + offset, llhdrlen); + + ret = priv->ops->send(priv->flatbuf, iob->io_pktlen + llhdrlen); + if (ret == -ENOMEM) + { + wd_start(&priv->txtimeout, WLAN_TXTOUT, + wlan_txtimeout_expiry, (uint32_t)priv); + break; + } + else + { + if (ret < 0) + { + nwarn("WARN: Failed to send pkt, ret: %d\n", ret); + } + + iob_remove_queue(&priv->txb); + + /* And free the I/O buffer chain */ + + iob_free_chain(iob); + } + } +} + +/**************************************************************************** + * Name: wlan_tx_done + * + * Description: + * Wi-Fi TX done callback function. If this is called, it means sending + * next packet. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wlan_tx_done(struct wlan_priv_s *priv) +{ + wd_cancel(&priv->txtimeout); + + wlan_txavail(&priv->dev); +} + +/**************************************************************************** + * Function: wlan_rx_done + * + * Description: + * Wi-Fi RX done callback function. If this is called, it means receiving + * packet. + * + * Input Parameters: + * priv - Reference to the driver state structure + * buffer - Wi-Fi received packet buffer + * len - Length of received packet + * eb - Wi-Fi receive callback input eb pointer + * + * Returned Value: + * 0 on success or a negated errno on failure + * + ****************************************************************************/ + +static int wlan_rx_done(struct wlan_priv_s *priv, void *buffer, + uint16_t len, void *eb) +{ + struct net_driver_s *dev = &priv->dev; + struct iob_s *iob = NULL; + irqstate_t flags; + int ret = 0; + + if (!priv->ifup) + { + goto out; + } + + if (len > WLAN_BUF_SIZE) + { + nwarn("ERROR: Wlan receive %d larger than %d\n", + len, WLAN_BUF_SIZE); + ret = -EINVAL; + goto out; + } + + if (len > iob_navail(false) * CONFIG_IOB_BUFSIZE) + { + ret = -ENOBUFS; + goto out; + } + + iob = iob_tryalloc(false); + if (iob == NULL) + { + ret = -ENOBUFS; + goto out; + } + + iob_reserve(iob, CONFIG_NET_LL_GUARDSIZE - NET_LL_HDRLEN(dev)); + + ret = iob_trycopyin(iob, buffer, len, 0, false); + if (ret != len) + { + ret = -ENOBUFS; + goto out; + } + + flags = spin_lock_irqsave(&priv->lock); + ret = iob_tryadd_queue(iob, &priv->rxb); + spin_unlock_irqrestore(&priv->lock, flags); + + if (ret < 0) + { + ret = -ENOBUFS; + goto out; + } + +out: + + if (eb != NULL) + { + esp_wifi_free_eb(eb); + } + + if (ret != OK && iob != NULL) + { + iob_free_chain(iob); + } + + if (work_available(&priv->rxwork)) + { + work_queue(WLAN_WORK, &priv->rxwork, wlan_rxpoll, priv, 0); + } + + wlan_txavail(&priv->dev); + + return ret; +} + +/**************************************************************************** + * Function: wlan_rxpoll + * + * Description: + * Try to receive packets from RX done queue and pass packets into IP + * stack and send packets which is from IP stack if necessary. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wlan_rxpoll(void *arg) +{ + struct wlan_priv_s *priv = (struct wlan_priv_s *)arg; + struct net_driver_s *dev = &priv->dev; + struct eth_hdr_s *eth_hdr; + struct iob_s *iob; + + /* Try to send all cached TX packets for TX ack and so on */ + + wlan_transmit(priv); + + /* Loop while while iob_remove_queue() successfully retrieves valid + * Ethernet frames. + */ + + net_lock(); + + while ((iob = wlan_recvframe(priv)) != NULL) + { + dev->d_iob = iob; + dev->d_len = iob->io_pktlen; + + iob_reserve(iob, CONFIG_NET_LL_GUARDSIZE); + +#ifdef CONFIG_NET_PKT + + /* When packet sockets are enabled, + * feed the frame into the packet tap. + */ + + pkt_input(&priv->dev); +#endif + + eth_hdr = (struct eth_hdr_s *) + &dev->d_iob->io_data[CONFIG_NET_LL_GUARDSIZE - + NET_LL_HDRLEN(dev)]; + + /* We only accept IP packets of the configured type and ARP packets */ + +#ifdef CONFIG_NET_IPv4 + if (eth_hdr->type == HTONS(ETHTYPE_IP)) + { + ninfo("IPv4 frame\n"); + + /* Receive an IPv4 packet from the network device */ + + ipv4_input(&priv->dev); + + /* If the above function invocation resulted in data + * that should be sent out on the network, + * the field d_len will set to a value > 0. + */ + + if (priv->dev.d_len > 0) + { + /* And send the packet */ + + wlan_cache_txpkt_tail(priv); + } + } + else +#endif +#ifdef CONFIG_NET_IPv6 + if (eth_hdr->type == HTONS(ETHTYPE_IP6)) + { + ninfo("IPv6 frame\n"); + + /* Give the IPv6 packet to the network layer */ + + ipv6_input(&priv->dev); + + /* If the above function invocation resulted in data + * that should be sent out on the network, the field + * d_len will set to a value > 0. + */ + + if (priv->dev.d_len > 0) + { + /* And send the packet */ + + wlan_cache_txpkt_tail(priv); + } + } + else +#endif +#ifdef CONFIG_NET_ARP + if (eth_hdr->type == HTONS(ETHTYPE_ARP)) + { + ninfo("ARP frame\n"); + + /* Handle ARP packet */ + + arp_input(&priv->dev); + + /* If the above function invocation resulted in data + * that should be sent out on the network, the field + * d_len will set to a value > 0. + */ + + if (priv->dev.d_len > 0) + { + wlan_cache_txpkt_tail(priv); + } + } + else +#endif + { + ninfo("INFO: Dropped, Unknown type: %04x\n", eth_hdr->type); + } + + netdev_iob_release(&priv->dev); + } + + /* Try to send all cached TX packets */ + + wlan_transmit(priv); + + net_unlock(); +} + +/**************************************************************************** + * Name: wlan_txpoll + * + * Description: + * The transmitter is available, check if the network has any outgoing + * packets ready to send. This is a callback from devif_poll(). + * devif_poll() may be called: + * + * 1. When the preceding TX packets send times out and the interface is + * reset + * 2. During normal TX polling + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +static int wlan_txpoll(struct net_driver_s *dev) +{ + struct wlan_priv_s *priv = dev->d_private; + + wlan_cache_txpkt_tail(priv); + wlan_transmit(priv); + + return OK; +} + +/**************************************************************************** + * Function: wlan_dopoll + * + * Description: + * The function is called in order to perform an out-of-sequence TX poll. + * This is done: + * + * 1. When new TX data is available (wlan_txavail) + * 2. After a TX timeout to restart the sending process + * (wlan_txtimeout_expiry). + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wlan_dopoll(struct wlan_priv_s *priv) +{ + struct net_driver_s *dev = &priv->dev; + + /* Try to let TCP/IP to send all packets to netcard driver */ + + while (devif_poll(dev, wlan_txpoll)); + + /* Try to send all cached TX packets */ + + wlan_transmit(priv); +} + +/**************************************************************************** + * Function: wlan_txtimeout_work + * + * Description: + * Perform TX timeout related work from the worker thread + * + * Input Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + ****************************************************************************/ + +static void wlan_txtimeout_work(void *arg) +{ + struct wlan_priv_s *priv = (struct wlan_priv_s *)arg; + + /* Try to send all cached TX packets */ + + wlan_transmit(priv); + + net_lock(); + + wlan_ifdown(&priv->dev); + wlan_ifup(&priv->dev); + + /* Then poll for new XMIT data */ + + wlan_dopoll(priv); + + net_unlock(); +} + +/**************************************************************************** + * Function: wlan_txtimeout_expiry + * + * Description: + * Our TX watchdog timed out. Called from the timer callback handler. + * The last TX never completed. Reset the hardware and start again. + * + * Input Parameters: + * arg - The reference of the private driver structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wlan_txtimeout_expiry(wdparm_t arg) +{ + struct wlan_priv_s *priv = (struct wlan_priv_s *)arg; + + /* Schedule to perform the TX timeout processing on the worker thread. */ + + if (work_available(&priv->toutwork)) + { + work_queue(WLAN_WORK, &priv->toutwork, wlan_txtimeout_work, priv, 0); + } +} + +/**************************************************************************** + * Name: wlan_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Input Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ + +static void wlan_txavail_work(void *arg) +{ + struct wlan_priv_s *priv = (struct wlan_priv_s *)arg; + + /* Try to send all cached TX packets even if net is down */ + + wlan_transmit(priv); + + /* Lock the network and serialize driver operations if necessary. + * NOTE: Serialization is only required in the case where the driver work + * is performed on an LP worker thread and where more than one LP worker + * thread has been configured. + */ + + net_lock(); + + /* Ignore the notification if the interface is not yet up */ + + if (priv->ifup) + { + /* Poll the network for new XMIT data */ + + wlan_dopoll(priv); + } + + net_unlock(); +} + +/**************************************************************************** + * Name: wlan_ifup + * + * Description: + * NuttX Callback: Bring up the Ethernet interface when an IP address is + * provided + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int wlan_ifup(struct net_driver_s *dev) +{ + int ret; + struct wlan_priv_s *priv = (struct wlan_priv_s *)dev->d_private; + +#ifdef CONFIG_NET_IPv4 + ninfo("Bringing up: %u.%u.%u.%u\n", + ip4_addr1(dev->d_ipaddr), ip4_addr2(dev->d_ipaddr), + ip4_addr3(dev->d_ipaddr), ip4_addr4(dev->d_ipaddr)); +#endif +#ifdef CONFIG_NET_IPv6 + ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", + dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2], + dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5], + dev->d_ipv6addr[6], dev->d_ipv6addr[7]); +#endif + + net_lock(); + + if (priv->ifup) + { + net_unlock(); + return OK; + } + + ret = priv->ops->start(); + if (ret < 0) + { + net_unlock(); + nerr("ERROR: Failed to start Wi-Fi ret=%d\n", ret); + return ret; + } + + IOB_QINIT(&priv->rxb); + IOB_QINIT(&priv->txb); + + priv->dev.d_buf = NULL; + priv->dev.d_len = 0; + + priv->ifup = true; + if (g_callback_register_ref == 0) + { + ret = esp_register_shutdown_handler(esp_wifi_stop_callback); + if (ret < 0) + { + nwarn("WARN: Failed to register handler ret=%d\n", ret); + } + } + + ++g_callback_register_ref; + net_unlock(); + + return OK; +} + +/**************************************************************************** + * Name: wlan_ifdown + * + * Description: + * NuttX Callback: Stop the interface. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int wlan_ifdown(struct net_driver_s *dev) +{ + int ret; + struct wlan_priv_s *priv = (struct wlan_priv_s *)dev->d_private; + + net_lock(); + + if (!priv->ifup) + { + net_unlock(); + return OK; + } + + /* Cancel the TX poll timer and TX timeout timers */ + + wd_cancel(&priv->txtimeout); + + /* Mark the device "down" */ + + priv->ifup = false; + + iob_free_queue(&priv->rxb); + iob_free_queue(&priv->txb); + + ret = priv->ops->stop(); + if (ret < 0) + { + nerr("ERROR: Failed to stop Wi-Fi ret=%d\n", ret); + } + + --g_callback_register_ref; + if (g_callback_register_ref == 0) + { + ret = esp_unregister_shutdown_handler(esp_wifi_stop_callback); + if (ret < 0) + { + nwarn("WARN: Failed to unregister handler ret=%d\n", ret); + } + } + + net_unlock(); + + return OK; +} + +/**************************************************************************** + * Name: wlan_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int wlan_txavail(struct net_driver_s *dev) +{ + struct wlan_priv_s *priv = (struct wlan_priv_s *)dev->d_private; + + if (work_available(&priv->txwork)) + { + /* Schedule to serialize the poll on the worker thread. */ + + work_queue(WLAN_WORK, &priv->txwork, wlan_txavail_work, priv, 0); + } + + return OK; +} + +/**************************************************************************** + * Name: wlan_addmac + * + * Description: + * NuttX Callback: Add the specified MAC address to the hardware multicast + * address filtering + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be added + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6) +static int wlan_addmac(struct net_driver_s *dev, const uint8_t *mac) +{ + struct wlan_priv_s *priv = (struct wlan_priv_s *)dev->d_private; + + /* Add the MAC address to the hardware multicast routing table */ + + return OK; +} +#endif + +/**************************************************************************** + * Name: wlan_rmmac + * + * Description: + * NuttX Callback: Remove the specified MAC address from the + * hardware multicast address filtering + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be removed + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_NET_MCASTGROUP +static int wlan_rmmac(struct net_driver_s *dev, const uint8_t *mac) +{ + struct wlan_priv_s *priv = (struct wlan_priv_s *)dev->d_private; + + /* Add the MAC address to the hardware multicast routing table */ + + return OK; +} +#endif + +/**************************************************************************** + * Name: wlan_ioctl + * + * Description: + * Handle network IOCTL commands directed to this device. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * cmd - The IOCTL command + * arg - The argument for the IOCTL command + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_NETDEV_IOCTL +static int wlan_ioctl(struct net_driver_s *dev, + int cmd, + unsigned long arg) +{ + int ret; + struct iwreq *iwr = (struct iwreq *)arg; + struct wlan_priv_s *priv = (struct wlan_priv_s *)dev->d_private; + const struct wlan_ops *ops = priv->ops; + + /* Decode and dispatch the driver-specific IOCTL command */ + + switch (cmd) + { +#ifdef CONFIG_NETDEV_PHY_IOCTL +#ifdef CONFIG_ARCH_PHY_INTERRUPT + case SIOCMIINOTIFY: /* Set up for PHY event notifications */ + { + struct mii_ioctl_notify_s *req = (struct mii_ioctl_notify_s *)arg; + ret = ops->event(req->pid, &req->event); + if (ret < 0) + { + nerr("ERROR: Failed to subscribe event\n"); + } + } + break; +#endif +#endif + + case SIOCSIWENCODEEXT: + ret = ops->passwd(iwr, true); + + break; + + case SIOCGIWENCODEEXT: + ret = ops->passwd(iwr, false); + break; + + case SIOCSIWESSID: + if ((iwr->u.essid.flags == IW_ESSID_ON) || + (iwr->u.essid.flags == IW_ESSID_DELAY_ON)) + { + ret = ops->essid(iwr, true); + if (ret < 0) + { + break; + } + + if (iwr->u.essid.flags == IW_ESSID_ON) + { + ret = ops->connect(); + if (ret < 0) + { + nerr("ERROR: Failed to connect\n"); + break; + } + } + } + else + { + ret = ops->disconnect(); + if (ret < 0) + { + nerr("ERROR: Failed to disconnect\n"); + break; + } + } + + break; + + case SIOCGIWESSID: /* Get ESSID */ + ret = ops->essid(iwr, false); + break; + + case SIOCSIWAP: /* Set access point MAC addresses */ + if (iwr->u.ap_addr.sa_data[0] != 0 && + iwr->u.ap_addr.sa_data[1] != 0 && + iwr->u.ap_addr.sa_data[2] != 0) + { + ret = ops->bssid(iwr, true); + if (ret < 0) + { + nerr("ERROR: Failed to set BSSID\n"); + break; + } + + ret = ops->connect(); + if (ret < 0) + { + nerr("ERROR: Failed to connect\n"); + break; + } + } + else + { + ret = ops->disconnect(); + if (ret < 0) + { + nerr("ERROR: Failed to disconnect\n"); + break; + } + } + + break; + + case SIOCGIWAP: /* Get access point MAC addresses */ + ret = ops->bssid(iwr, false); + break; + + case SIOCSIWSCAN: + ret = esp_wifi_start_scan(iwr); + break; + + case SIOCGIWSCAN: + ret = esp_wifi_get_scan_results(iwr); + break; + + case SIOCSIWCOUNTRY: /* Set country code */ + ret = ops->country(iwr, true); + break; + + case SIOCGIWSENS: /* Get sensitivity (dBm) */ + ret = ops->rssi(iwr, false); + break; + + case SIOCSIWMODE: /* Set operation mode */ + ret = ops->mode(iwr, true); + break; + + case SIOCGIWMODE: /* Get operation mode */ + ret = ops->mode(iwr, false); + break; + + case SIOCSIWAUTH: /* Set authentication mode params */ + ret = ops->auth(iwr, true); + break; + + case SIOCGIWAUTH: /* Get authentication mode params */ + ret = ops->auth(iwr, false); + break; + + case SIOCSIWFREQ: /* Set channel/frequency (MHz) */ + ret = ops->freq(iwr, true); + break; + + case SIOCGIWFREQ: /* Get channel/frequency (MHz) */ + ret = ops->freq(iwr, false); + break; + + case SIOCSIWRATE: /* Set default bit rate (Mbps) */ + wlwarn("WARNING: SIOCSIWRATE not implemented\n"); + ret = -ENOSYS; + break; + + case SIOCGIWRATE: /* Get default bit rate (Mbps) */ + ret = ops->bitrate(iwr, false); + break; + + case SIOCSIWTXPOW: /* Set transmit power (dBm) */ + ret = ops->txpower(iwr, true); + break; + + case SIOCGIWTXPOW: /* Get transmit power (dBm) */ + ret = ops->txpower(iwr, false); + break; + + case SIOCGIWRANGE: /* Get range of parameters */ + ret = ops->channel(iwr, false); + break; + + default: + nerr("ERROR: Unrecognized IOCTL command: %d\n", cmd); + ret = -ENOTTY; /* Special return value for this case */ + break; + } + + return ret; +} +#endif /* CONFIG_NETDEV_IOCTL */ + +/**************************************************************************** + * Name: esp_net_initialize + * + * Description: + * Initialize the network driver. + * + * Input Parameters: + * devno - The device number. + * mac_addr - MAC address. + * ops - A pointer to the structure containing the WLAN operations + * functions. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +static int esp_net_initialize(int devno, uint8_t *mac_addr, + const struct wlan_ops *ops) +{ + int ret; + struct wlan_priv_s *priv; + struct net_driver_s *netdev; + + priv = &g_wlan_priv[devno]; + if (priv->ref) + { + priv->ref++; + return OK; + } + + netdev = &priv->dev; + + /* Initialize the driver structure */ + + memset(priv, 0, sizeof(struct wlan_priv_s)); + + netdev->d_ifup = wlan_ifup; /* I/F down callback */ + netdev->d_ifdown = wlan_ifdown; /* I/F up (new IP address) callback */ + netdev->d_txavail = wlan_txavail; /* New TX data callback */ +#ifdef CONFIG_NET_MCASTGROUP + netdev->d_addmac = wlan_addmac; /* Add multicast MAC address */ + netdev->d_rmmac = wlan_rmmac; /* Remove multicast MAC address */ +#endif +#ifdef CONFIG_NETDEV_IOCTL + netdev->d_ioctl = wlan_ioctl; /* Handle network IOCTL commands */ +#endif + + /* Used to recover private state from dev */ + + netdev->d_private = (void *)priv; + + memcpy(netdev->d_mac.ether.ether_addr_octet, mac_addr, MAC_LEN); + + ret = netdev_register(netdev, NET_LL_IEEE80211); + if (ret < 0) + { + nerr("ERROR: Initialization of IEEE 802.11 block failed: %d\n", ret); + return ret; + } + + priv->ops = ops; + + priv->ref++; + + ninfo("INFO: Initialize Wi-Fi adapter No.%d success\n", devno); + + return OK; +} + +/**************************************************************************** + * Function: wlan_sta_rx_done + * + * Description: + * Wi-Fi station RX done callback function. If this is called, it means + * station receiveing packet. + * + * Input Parameters: + * buffer - Wi-Fi received packet buffer + * len - Length of received packet + * eb - Wi-Fi receive callback input eb pointer + * + * Returned Value: + * 0 on success or a negated errno on failure + * + ****************************************************************************/ + +#ifdef ESP_WLAN_HAS_STA +static int wlan_sta_rx_done(void *buffer, uint16_t len, void *eb) +{ + struct wlan_priv_s *priv = &g_wlan_priv[ESP_WLAN_STA_DEVNO]; + + return wlan_rx_done(priv, buffer, len, eb); +} + +/**************************************************************************** + * Name: wlan_sta_tx_done + * + * Description: + * Wi-Fi station TX done callback function. If this is called, it means + * station sending next packet. + * + * Input Parameters: + * ifidx - The interface ID that the TX callback has been triggered from. + * data - Pointer to the data transmitted. + * len - Length of the data transmitted. + * status - True if data was transmitted successfully or false if failed. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wlan_sta_tx_done(uint8_t ifidx, + uint8_t *data, + uint16_t *len, + bool status) +{ + struct wlan_priv_s *priv = &g_wlan_priv[ESP_WLAN_STA_DEVNO]; + + wlan_tx_done(priv); +} +#endif /* ESP_WLAN_HAS_STA */ + +/**************************************************************************** + * Function: wlan_softap_rx_done + * + * Description: + * Wi-Fi softAP RX done callback function. If this is called, it means + * softAP receiveing packet. + * + * Input Parameters: + * buffer - Wi-Fi received packet buffer + * len - Length of received packet + * eb - Wi-Fi receive callback input eb pointer + * + * Returned Value: + * 0 on success or a negated errno on failure + * + ****************************************************************************/ + +#ifdef ESP_WLAN_HAS_SOFTAP +static int wlan_softap_rx_done(void *buffer, uint16_t len, void *eb) +{ + struct wlan_priv_s *priv = &g_wlan_priv[ESP_WLAN_SOFTAP_DEVNO]; + + return wlan_rx_done(priv, buffer, len, eb); +} + +/**************************************************************************** + * Name: wlan_softap_tx_done + * + * Description: + * Wi-Fi softAP TX done callback function. If this is called, it means + * softAP sending next packet. + * + * Input Parameters: + * ifidx - The interface ID that the TX callback has been triggered from. + * data - Pointer to the data transmitted. + * len - Length of the data transmitted. + * status - True if data was transmitted successfully or false if failed. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wlan_softap_tx_done(uint8_t ifidx, + uint8_t *data, + uint16_t *len, + bool status) +{ + struct wlan_priv_s *priv = &g_wlan_priv[ESP_WLAN_SOFTAP_DEVNO]; + + wlan_tx_done(priv); +} +#endif /* ESP_WLAN_HAS_SOFTAP */ + +/**************************************************************************** + * Name: esp_wifi_stop_callback + * + * Description: + * Callback to stop Wi-Fi. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_wifi_stop_callback(void) +{ + wlinfo("INFO: Try to stop Wi-Fi\n"); + + int ret = esp_wifi_stop(); + if (ret) + { + wlerr("ERROR: Failed to stop Wi-Fi ret=%d\n", ret); + DEBUGPANIC(); + } +} + +/**************************************************************************** + * Name: esp_wifi_free_eb + * + * Description: + * Free Wi-Fi receive callback input eb pointer + * + * Input Parameters: + * eb - Wi-Fi receive callback input eb pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_wifi_free_eb(void *eb) +{ + esp_wifi_internal_free_rx_buffer(eb); +} + +/**************************************************************************** + * Name: esp_wifi_sta_register_recv_cb + * + * Description: + * Register Wi-Fi station receive packet callback function + * + * Input Parameters: + * recv_cb - Receive callback function + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +#ifdef ESP_WLAN_HAS_STA +static int esp_wifi_sta_register_recv_cb(int (*recv_cb)(void *buffer, + uint16_t len, + void *eb)) +{ + int ret; + + ret = esp_wifi_internal_reg_rxcb(ESP_IF_WIFI_STA, (wifi_rxcb_t)recv_cb); + + return esp_wifi_to_errno(ret); +} + +/**************************************************************************** + * Name: esp_wifi_sta_register_txdone_cb + * + * Description: + * Register the station TX done callback function. + * + * Input Parameters: + * cb - The callback function + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_wifi_sta_register_txdone_cb(wifi_tx_done_cb_t cb) +{ + g_sta_txdone_cb = cb; +} +#endif /* ESP_WLAN_HAS_STA */ + +/**************************************************************************** + * Name: esp_wifi_softap_register_recv_cb + * + * Description: + * Register Wi-Fi SoftAP receive packet callback function + * + * Input Parameters: + * recv_cb - Receive callback function + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +#ifdef ESP_WLAN_HAS_SOFTAP +static int esp_wifi_softap_register_recv_cb(int (*recv_cb)(void *buffer, + uint16_t len, + void *eb)) +{ + int ret; + + ret = esp_wifi_internal_reg_rxcb(ESP_IF_WIFI_AP, (wifi_rxcb_t)recv_cb); + + return esp_wifi_to_errno(ret); +} + +/**************************************************************************** + * Name: esp_wifi_softap_register_txdone_cb + * + * Description: + * Register the SoftAP TX done callback function. + * + * Input Parameters: + * cb - The callback function + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp_wifi_softap_register_txdone_cb(wifi_tx_done_cb_t cb) +{ + g_softap_txdone_cb = cb; +} +#endif /* ESP_WLAN_HAS_SOFTAP */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_wlan_sta_set_linkstatus + * + * Description: + * Set Wi-Fi station link status + * + * Parameters: + * linkstatus - true Notifies the networking layer about an available + * carrier, false Notifies the networking layer about an + * disappeared carrier. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +#ifdef ESP_WLAN_HAS_STA +int esp_wlan_sta_set_linkstatus(bool linkstatus) +{ + struct wlan_priv_s *priv = &g_wlan_priv[ESP_WLAN_STA_DEVNO]; + + if (linkstatus) + { + netdev_carrier_on(&priv->dev); + } + else + { + netdev_carrier_off(&priv->dev); + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wlan_sta_initialize + * + * Description: + * Initialize the WLAN station netcard driver + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp_wlan_sta_initialize(void) +{ + int ret; + uint8_t mac[6]; + + ret = esp_wifi_adapter_init(); + if (ret < 0) + { + nerr("ERROR: Initialize Wi-Fi adapter error: %d\n", ret); + return ret; + } + + ret = esp_read_mac(mac, ESP_MAC_WIFI_STA); + if (ret < 0) + { + nerr("ERROR: Failed to read MAC address\n"); + return ret; + } + + ninfo("Wi-Fi station MAC: %02X:%02X:%02X:%02X:%02X:%02X\n", + mac[0], mac[1], mac[2], + mac[3], mac[4], mac[5]); + + ret = esp_net_initialize(ESP_WLAN_STA_DEVNO, mac, &g_sta_ops); + if (ret < 0) + { + nerr("ERROR: Failed to initialize net\n"); + return ret; + } + + ret = esp_wifi_sta_register_recv_cb(wlan_sta_rx_done); + if (ret < 0) + { + nerr("ERROR: Failed to register RX callback\n"); + return ret; + } + + esp_wifi_sta_register_txdone_cb(wlan_sta_tx_done); + + ninfo("INFO: Initialize Wi-Fi station success net\n"); + + return OK; +} +#endif /* ESP_WLAN_HAS_STA */ + +/**************************************************************************** + * Name: esp_wlan_softap_initialize + * + * Description: + * Initialize the ESP32-S3 WLAN softAP netcard driver + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +#ifdef ESP_WLAN_HAS_SOFTAP +int esp_wlan_softap_initialize(void) +{ + int ret; + uint8_t mac[6]; + + ret = esp_wifi_adapter_init(); + if (ret < 0) + { + nerr("ERROR: Initialize Wi-Fi adapter error: %d\n", ret); + return ret; + } + + ret = esp_read_mac(mac, ESP_MAC_WIFI_SOFTAP); + if (ret < 0) + { + nerr("ERROR: Failed to read MAC address\n"); + return ret; + } + + ninfo("Wi-Fi softAP MAC: %02X:%02X:%02X:%02X:%02X:%02X\n", + mac[0], mac[1], mac[2], + mac[3], mac[4], mac[5]); + + ret = esp_net_initialize(ESP_WLAN_SOFTAP_DEVNO, mac, + &g_softap_ops); + if (ret < 0) + { + nerr("ERROR: Failed to initialize net\n"); + return ret; + } + + ret = esp_wifi_softap_register_recv_cb(wlan_softap_rx_done); + if (ret < 0) + { + nerr("ERROR: Failed to register RX callback\n"); + return ret; + } + + esp_wifi_softap_register_txdone_cb(wlan_softap_tx_done); + + ninfo("INFO: Initialize Wi-Fi softAP net success\n"); + + return OK; +} +#endif /* ESP_WLAN_HAS_SOFTAP */ + +/**************************************************************************** + * Name: esp_wifi_tx_done_cb + * + * Description: + * Wi-Fi TX done callback function. + * + * Input Parameters: + * ifidx - The interface id that the tx callback has been triggered from + * data - Pointer to the data transmitted + * data_len - Length of the data transmitted + * txstatus - True:if the data was transmitted sucessfully False: if data + * transmission failed + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp_wifi_tx_done_cb(uint8_t ifidx, + uint8_t *data, + uint16_t *len, + bool txstatus) +{ +#ifdef ESP_WLAN_HAS_STA + if (ifidx == ESP_IF_WIFI_STA) + { + if (g_sta_txdone_cb) + { + g_sta_txdone_cb(ifidx, data, len, txstatus); + } + } + else +#endif /* ESP_WLAN_HAS_STA */ + +#ifdef ESP_WLAN_HAS_SOFTAP + if (ifidx == ESP_IF_WIFI_AP) + { + if (g_softap_txdone_cb) + { + g_softap_txdone_cb(ifidx, data, len, txstatus); + } + } + else +#endif /* ESP_WLAN_HAS_SOFTAP */ + { + wlerr("ifidx=%d is error\n", ifidx); + } +} + +#endif /* CONFIG_ESPRESSIF_WIFI */ diff --git a/arch/risc-v/src/common/espressif/esp_wlan.h b/arch/risc-v/src/common/espressif/esp_wlan.h new file mode 100644 index 0000000000000..f23c215268bf3 --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_wlan.h @@ -0,0 +1,177 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_wlan.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_WLAN_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_WLAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_ESPRESSIF_WIFI_STATION) +# define ESP_WLAN_HAS_STA +# define ESP_WLAN_STA_DEVNO 0 +# define ESP_WLAN_DEVS 1 +#elif defined(CONFIG_ESPRESSIF_WIFI_SOFTAP) +# define ESP_WLAN_HAS_SOFTAP +# define ESP_WLAN_SOFTAP_DEVNO 0 +# define ESP_WLAN_DEVS 1 +#elif defined(CONFIG_ESPRESSIF_WIFI_STATION_SOFTAP) +# define ESP_WLAN_HAS_STA +# define ESP_WLAN_HAS_SOFTAP +# define ESP_WLAN_STA_DEVNO 0 +# define ESP_WLAN_SOFTAP_DEVNO 1 +# define ESP_WLAN_DEVS 2 +#endif + +#define MAC_LEN (6) + +#ifdef CONFIG_ESPRESSIF_WIFI + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nuttx_err_to_freertos + * + * Description: + * Transform from Nuttx OS error code to FreeRTOS's pdTRUE or pdFALSE. + * + * Input Parameters: + * ret - NuttX error code + * + * Returned Value: + * Wi-Fi adapter error code + * + ****************************************************************************/ + +static inline int32_t nuttx_err_to_freertos(int ret) +{ + return ret >= 0; +} + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef ESP_WLAN_HAS_STA + +/**************************************************************************** + * Name: esp_wlan_sta_set_linkstatus + * + * Description: + * Set Wi-Fi station link status + * + * Parameters: + * linkstatus - true Notifies the networking layer about an available + * carrier, false Notifies the networking layer about an + * disappeared carrier. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp_wlan_sta_set_linkstatus(bool linkstatus); + +/**************************************************************************** + * Name: esp_wlan_sta_initialize + * + * Description: + * Initialize the ESP32-S3 WLAN station netcard driver + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp_wlan_sta_initialize(void); +#endif /* ESP_WLAN_HAS_STA */ + +/**************************************************************************** + * Name: esp_wlan_softap_initialize + * + * Description: + * Initialize the ESP32-S3 WLAN softAP netcard driver + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +#ifdef ESP_WLAN_HAS_SOFTAP +int esp_wlan_softap_initialize(void); +#endif /* ESP_WLAN_HAS_SOFTAP */ + +/**************************************************************************** + * Name: esp_wifi_tx_done_cb + * + * Description: + * Wi-Fi TX done callback function. + * + * Input Parameters: + * ifidx - The interface id that the tx callback has been triggered from + * data - Pointer to the data transmitted + * data_len - Length of the data transmitted + * txstatus - True:if the data was transmitted sucessfully False: if data + * transmission failed + * + * Returned Value: + * none + * + ****************************************************************************/ + +void esp_wifi_tx_done_cb(uint8_t ifidx, + uint8_t *data, + uint16_t *len, + bool txstatus); + +#endif /* CONFIG_ESPRESSIF_WIFI */ +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_WLAN_H */ diff --git a/arch/risc-v/src/common/espressif/esp_ws2812.c b/arch/risc-v/src/common/espressif/esp_ws2812.c new file mode 100644 index 0000000000000..cc4e14865a4b0 --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_ws2812.c @@ -0,0 +1,667 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_ws2812.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "hal/rmt_types.h" +#include "soc/soc.h" + +#include "esp_rmt.h" + +#include "esp_ws2812.h" + +#ifdef CONFIG_WS2812 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define rmt_item32_t rmt_symbol_word_t + +/**************************************************************************** + * Private Type + ****************************************************************************/ + +struct rgbw_led_s +{ + union + { + struct + { + uint8_t b; + uint8_t g; + uint8_t r; + uint8_t w; + }; + uint32_t val; + }; +}; + +struct esp_ws2812_dev_s +{ + struct rmt_dev_s *rmt; + uint8_t *buf; + size_t buflen; + size_t open_count; /* Number of opens on this instance. */ +}; + +/* RMT channel ID */ + +enum rmt_channel_e +{ + RMT_CHANNEL_0, /* RMT channel number 0 */ + RMT_CHANNEL_1, /* RMT channel number 1 */ + RMT_CHANNEL_2, /* RMT channel number 2 */ + RMT_CHANNEL_3, /* RMT channel number 3 */ +#if SOC_RMT_CHANNELS_PER_GROUP > 4 + RMT_CHANNEL_4, /* RMT channel number 4 */ + RMT_CHANNEL_5, /* RMT channel number 5 */ + RMT_CHANNEL_6, /* RMT channel number 6 */ + RMT_CHANNEL_7, /* RMT channel number 7 */ +#endif + RMT_CHANNEL_MAX /* Number of RMT channels */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static uint32_t map_byte_to_words(struct esp_ws2812_dev_s *dev, + uint8_t byte, + uint32_t *dst); +static int map_leds_to_words(struct esp_ws2812_dev_s *dev, + struct rgbw_led_s *leds, + uint32_t n_leds, + uint32_t *dst, + bool has_white); +static int esp_open(struct file *filep); +static int esp_close(struct file *filep); +static int esp_write(struct file *filep, const char *data, size_t len); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if SOC_RMT_CHANNEL_CLK_INDEPENDENT +extern uint32_t g_rmt_source_clock_hz[RMT_CHANNEL_MAX]; +#else +extern uint32_t g_rmt_source_clock_hz; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: map_byte_to_words + * + * Description: + * Maps a byte to a sequence of RMT items. Each bit in the byte is + * represented by an RMT item (32-bit value). The function iterates over + * each bit in the byte, creating an RMT item for each bit, HIGH or LOW. + * The created RMT items are stored in the destination array. + * + * Input Parameters: + * dev - Pointer to the RMT-based WS2812 device structure. + * byte - The byte to be mapped. + * dst - Destination array for the RMT items. + * + * Returned Value: + * Number of RMT items mapped. + * + ****************************************************************************/ + +static uint32_t map_byte_to_words(struct esp_ws2812_dev_s *dev, + uint8_t byte, + uint32_t *dst) +{ + uint32_t mapped; + uint8_t mask; + uint16_t t0h; + uint16_t t0l; + uint16_t t1h; + uint16_t t1l; + uint32_t clock_period_ps; + uint32_t rmt_period_ps; + +#if SOC_RMT_CHANNEL_CLK_INDEPENDENT + clock_period_ps = 1000000000000 / g_rmt_source_clock_hz[dev->rmt->minor]; +#else + clock_period_ps = 1000000000000 / g_rmt_source_clock_hz; +#endif + rmt_period_ps = clock_period_ps / RMT_DEFAULT_CLK_DIV; + + /* Calculate the RMT period to encode WS2812 frames */ + + t0h = ((uint16_t)(350000 / rmt_period_ps)); + t0l = ((uint16_t)(900000 / rmt_period_ps)); + t1h = ((uint16_t)(900000 / rmt_period_ps)); + t1l = ((uint16_t)(350000 / rmt_period_ps)); + + mapped = 0; + mask = 0x80; + for (int i = 0; i < 8; i++) + { + uint32_t word; + uint8_t bit = (byte & mask); + + mask >>= 1; + + if (bit) + { + word = (t1l << 16) | (0x8000 | t1h); + } + else + { + word = (t0l << 16) | (0x8000 | t0h); + } + + *dst = word; + dst++; + mapped++; + } + + return mapped; +} + +/**************************************************************************** + * Name: map_leds_to_words + * + * Description: + * Maps an array of LEDs to a sequence of RMT items. Each LED in the array + * is represented by a sequence of RMT items, one for each bit in the RGB + * (and optionally white) values. Iterates over each LED in the array, + * mapping the RGB (and optionally white) values to RMT items using the + * map_byte_to_words function. The RMT items are stored in the destination + * array. + * + * Input Parameters: + * dev - Pointer to the RMT-based WS2812 device structure. + * leds - Pointer to the array of LEDs. + * n_leds - Number of LEDs in the array. + * dst - Destination array for the RMT items. + * has_white - Flag indicating if the LEDs include a white component. + * + * Returned Value: + * Number of RMT items mapped; a negated errno value is returned on + * failure. + * + ****************************************************************************/ + +static int map_leds_to_words(struct esp_ws2812_dev_s *dev, + struct rgbw_led_s *leds, + uint32_t n_leds, + uint32_t *dst, + bool has_white) +{ + uint32_t dst_offset; + + if (!dst || !leds) + { + return -EINVAL; + } + + dst_offset = 0; + for (uint32_t led_idx = 0; led_idx < n_leds; led_idx++) + { + dst_offset += map_byte_to_words(dev, + leds[led_idx].g, + dst + dst_offset); + dst_offset += map_byte_to_words(dev, + leds[led_idx].r, + dst + dst_offset); + dst_offset += map_byte_to_words(dev, + leds[led_idx].b, + dst + dst_offset); + if (has_white) + { + dst_offset += map_byte_to_words(dev, + leds[led_idx].w, + dst + dst_offset); + } + } + + return dst_offset; +} + +/**************************************************************************** + * Name: esp_open + * + * Description: + * This function opens a WS2812 device instance. It locks the device, + * checks if the device has already been initialized, and if not, it + * allocates and initializes the pixel buffer. It then increases the open + * count and unlocks the device. + * + * Input Parameters: + * filep - Pointer to the file structure. + * + * Returned Value: + * Returns OK on successful open of the device; a negated errno value + * is returned on any failure. + * + ****************************************************************************/ + +static int esp_open(struct file *filep) +{ + struct inode *inode = filep->f_inode; + struct ws2812_dev_s *dev_data = inode->i_private; + struct esp_ws2812_dev_s *priv; + uint8_t colors; + irqstate_t flags; + size_t buflen; + int i; + int ret; + + priv = (struct esp_ws2812_dev_s *)dev_data->private; + + flags = enter_critical_section(); + + if (priv->buf != NULL) + { + /* We've already been initialized. Keep on truckin' */ + + ledinfo("esp_ws2812 re-open dev: 0x%p\n", dev_data); + + ret = OK; + goto post_and_return; + } + + ledinfo("esp_ws2812 open dev: 0x%p\n", dev_data); + + /* Allocate the pixel buffer */ + + if (priv->open_count == 0) + { + struct rgbw_led_s *led; + + /* Number of colors of each LED */ + + colors = (dev_data->has_white ? 4 : 3); + + /* Each LED color is represented by 8 RMT items + 1 last item. Each RMT + * item is 32-bit long. + */ + + buflen = (dev_data->nleds * colors * 8 + 1) * sizeof(rmt_item32_t); + + priv->buf = kmm_zalloc(buflen); + + if (priv->buf == NULL) + { + lederr("esp_ws2812 open: out of memory\n"); + + ret = -ENOMEM; + goto post_and_return; + } + + priv->buflen = buflen; + + /* Clear all LEDs in the LED strip */ + + led = kmm_zalloc(sizeof(struct rgbw_led_s)); + + if (led == NULL) + { + lederr("esp_ws2812 open: out of memory\n"); + + ret = -ENOMEM; + goto post_and_return; + } + + for (i = 0; i < dev_data->nleds; i++) + { + map_leds_to_words(priv, + led, + 1, + ((uint32_t *)priv->buf + i * colors * 8), + dev_data->has_white); + } + + kmm_free(led); + } + else + { + ledwarn("esp_ws2812 open: already open\n"); + } + + priv->open_count += 1; + + ret = OK; + +post_and_return: + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: esp_close + * + * Description: + * This function closes a previously opened WS2812 device instance. It + * locks the device, decreases the open count, and if no other instances + * are open, it frees the buffer associated with the device. It then + * unlocks the device and returns OK. + * + * Input Parameters: + * filep - Pointer to the file structure. + * + * Returned Value: + * Returns OK on successful close of the device; a negated errno value + * is returned on any failure. + * + ****************************************************************************/ + +static int esp_close(struct file *filep) +{ + struct inode *inode = filep->f_inode; + struct ws2812_dev_s *dev_data = inode->i_private; + struct esp_ws2812_dev_s *priv; + + priv = (struct esp_ws2812_dev_s *)dev_data->private; + + nxmutex_lock(&dev_data->lock); + + ledinfo("esp_ws2812 close dev: 0x%p\n", dev_data); + + priv->open_count -= 1; + + if (priv->open_count == 0) + { + kmm_free(priv->buf); + priv->buf = NULL; + } + + nxmutex_unlock(&dev_data->lock); + return OK; +} + +/**************************************************************************** + * Name: esp_write + * + * Description: + * This function writes the LED data to the WS2812 device. It checks if the + * data and length are valid, locks the device, maps the LED data to the + * buffer, updates the file position, writes the buffer to the RMT device, + * and unlocks the device. It returns the number of LED pixels that had + * their values changed. + * + * Input Parameters: + * filep - Pointer to the file structure. + * data - Pointer to the LED data to be written. + * len - The length of the data to be written. + * + * Returned Value: + * Returns the number of LED pixels that had their values changed on + * successful write; a negated errno value is returned on any failure. + * + ****************************************************************************/ + +static ssize_t esp_write(struct file *filep, const char *data, size_t len) +{ + struct inode *inode = filep->f_inode; + struct ws2812_dev_s *dev = inode->i_private; + struct esp_ws2812_dev_s *priv = + (struct esp_ws2812_dev_s *)dev->private; + int position = filep->f_pos; + uint32_t n_leds = len / WS2812_RW_PIXEL_SIZE; + uint8_t colors = (dev->has_white ? 4 : 3); + uint8_t *bp = priv->buf + position; + int rmt_bytes; + int n_leds_written; + int ret; + + /* Check if LED data isn't NULL */ + + if (data == NULL) + { + lederr("esp_ws2812 write failed: NULL data\n"); + set_errno(EINVAL); + return 0; + } + + /* Check if the number of LEDs to be updated is valid */ + + if (n_leds > dev->nleds) + { + lederr("esp_ws2812 write failed: invalid len for the LEDs buffer\n"); + set_errno(EINVAL); + return 0; + } + + nxmutex_lock(&dev->lock); + + if (len > 0) + { + /* Check if the lenght to be updated, considering the current position, + * is valid. The number of LEDs to be updated should, starting from the + * current offset should be less than the LED strip total length. + */ + + if (((position + len) / WS2812_RW_PIXEL_SIZE) > dev->nleds) + { + ledwarn("esp_ws2812 write truncated:\n\t\tLED position: %d\n" + "\t\tLED requested to be written: %ld\n" + "\t\tLED strip LED count: %d\n" + "\t\tLED being written: %d\n", + position / WS2812_RW_PIXEL_SIZE, + n_leds, + dev->nleds, + dev->nleds - (position / WS2812_RW_PIXEL_SIZE)); + n_leds = dev->nleds - (position / WS2812_RW_PIXEL_SIZE); + } + + ret = map_leds_to_words(priv, + (struct rgbw_led_s *)data, + n_leds, + (uint32_t *)bp, + dev->has_white); + if (ret < 0) + { + lederr("esp_ws2812 write failed: %d\n", ret); + nxmutex_unlock(&dev->lock); + set_errno(-ret); + return ret; + } + + /* Update the file position: each LED color is represented by 8 RMT + * items. The position is, then, the number of LEDs to be update times + * the size of a LED color in bytes. + */ + + position += n_leds * WS2812_RW_PIXEL_SIZE; + + filep->f_pos = position; + } + + /* Write the buffer to the RMT device */ + + rmt_bytes = priv->rmt->ops->write(priv->rmt, + (const char *)priv->buf, + priv->buflen); + + /* n_leds_written is the number of LEDs that had their values changed: + * Each LED color is represented by 8 RMT items. We also added a last + * RMT item to the buffer, so we need to subtract 1 from the total number. + * Finally, we divide by the number of colors to get the number of LEDs. + */ + + n_leds_written = ((rmt_bytes / sizeof(rmt_item32_t)) - 1) / (colors * 8); + + /* Compare n_leds_written with the value representing the full LED strip */ + + if (n_leds_written < dev->nleds) + { + lederr("esp_ws2812 write failed: %d\n", n_leds_written); + nxmutex_unlock(&dev->lock); + set_errno(-EIO); + return -EIO; + } + + nxmutex_unlock(&dev->lock); + + /* Return the number of LEDs pixels that had their values changed */ + + return n_leds * WS2812_RW_PIXEL_SIZE; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_ws2812_setup + * + * Description: + * This function sets up a WS2812 device instance. It allocates memory for + * the device structures, initializes the device with the provided + * parameters, and registers the device with the system. + * + * Input Parameters: + * path - The device path. + * rmt - Pointer to the RMT device structure. + * pixel_count - The number of pixels in the WS2812 strip. + * has_white - Flag indicating if the WS2812 strip includes a white LED. + * + * Returned Value: + * Returns a pointer to the WS2812 device structure on successful setup; + * NULL is returned on any failure, with errno set appropriately. + * + ****************************************************************************/ + +struct ws2812_dev_s *esp_ws2812_setup(const char *path, + struct rmt_dev_s *rmt, + uint16_t pixel_count, + bool has_white) +{ + struct ws2812_dev_s *dev; + struct esp_ws2812_dev_s *priv; + int err; + + /* Allocate struct holding generic WS2812 device data */ + + dev = kmm_zalloc(sizeof(struct ws2812_dev_s)); + + if (dev == NULL) + { + lederr("esp_ws2812 setup: out of memory\n"); + set_errno(ENOMEM); + return NULL; + } + + /* Allocate struct holding Espressif's WS2812 (RMT-enabled) device data */ + + priv = kmm_zalloc(sizeof(struct esp_ws2812_dev_s)); + + if (priv == NULL) + { + lederr("esp_ws2812 open: out of memory\n"); + kmm_free(dev); + set_errno(ENOMEM); + return NULL; + } + + priv->rmt = rmt; + + dev->open = esp_open; + dev->close = esp_close; + dev->write = esp_write; + dev->private = priv; + dev->clock = CONFIG_WS2812_FREQUENCY; + dev->port = priv->rmt->minor; + dev->nleds = pixel_count; + dev->has_white = has_white; + + nxmutex_init(&dev->lock); + + ledinfo("register dev: 0x%p\n", dev); + + /* Register the WS2812 RGB addressable LED strip device */ + + err = ws2812_register(path, dev); + + if (err != OK) + { + set_errno(err); + return NULL; + } + + return (void *)dev; +} + +/**************************************************************************** + * Name: esp_ws2812_release + * + * Description: + * This function releases a previously opened WS2812 device instance. It + * checks if the device is currently open, and if not, it frees the private + * data structure and sets the private field of the device to NULL. If the + * device is still open, it returns an error. + * + * Input Parameters: + * driver - Pointer to the instance of the WS2812 device driver to be + * released. + * + * Returned Value: + * Returns OK on successful release of the device; a negated errno value + * is returned on any failure. + * + ****************************************************************************/ + +int esp_ws2812_release(void * driver) +{ + struct ws2812_dev_s *dev = driver; + struct esp_ws2812_dev_s *priv; + int ret = OK; + + priv = (struct esp_ws2812_dev_s *)dev->private; + + nxmutex_lock(&dev->lock); + + if (priv->open_count == 0) + { + dev->private = NULL; + + nxmutex_unlock(&dev->lock); + + kmm_free(priv); + } + else + { + ret = -EBUSY; + nxmutex_unlock(&dev->lock); + } + + return ret; +} + +#endif /* CONFIG_WS2812 */ diff --git a/arch/risc-v/src/common/espressif/esp_ws2812.h b/arch/risc-v/src/common/espressif/esp_ws2812.h new file mode 100644 index 0000000000000..4c6b62f843aa5 --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_ws2812.h @@ -0,0 +1,100 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_ws2812.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISC_V_SRC_COMMON_ESPRESSIF_ESP_WS2812_H +#define __ARCH_RISC_V_SRC_COMMON_ESPRESSIF_ESP_WS2812_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#ifndef __ASSEMBLY__ +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#ifdef CONFIG_WS2812 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_ws2812_setup + * + * Description: + * This function sets up a WS2812 device instance. It allocates memory for + * the device structures, initializes the device with the provided + * parameters, and registers the device with the system. + * + * Input Parameters: + * path - The device path. + * rmt - Pointer to the RMT device structure. + * pixel_count - The number of pixels in the WS2812 strip. + * has_white - Flag indicating if the WS2812 strip includes a white LED. + * + * Returned Value: + * Returns a pointer to the WS2812 device structure on successful setup; + * NULL is returned on any failure, with errno set appropriately. + * + ****************************************************************************/ + +struct ws2812_dev_s *esp_ws2812_setup(const char *path, + struct rmt_dev_s *rmt, + uint16_t pixel_count, + bool has_white); +/**************************************************************************** + * Name: esp_ws2812_release + * + * Description: + * This function releases a previously opened WS2812 device instance. It + * checks if the device is currently open, and if not, it frees the private + * data structure and sets the private field of the device to NULL. If the + * device is still open, it returns an error. + * + * Input Parameters: + * driver - Pointer to the instance of the WS2812 device driver to be + * released. + * + * Returned Value: + * Returns OK on successful release of the device; a negated errno value + * is returned on any failure. + * + ****************************************************************************/ + +int esp_ws2812_release(void * driver); + +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISC_V_SRC_COMMON_ESPRESSIF_ESP_WS2812_H */ diff --git a/arch/risc-v/src/common/espressif/platform_include/sys/lock.h b/arch/risc-v/src/common/espressif/platform_include/sys/lock.h new file mode 100644 index 0000000000000..4f177097bcf36 --- /dev/null +++ b/arch/risc-v/src/common/espressif/platform_include/sys/lock.h @@ -0,0 +1,213 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/platform_include/sys/lock.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#pragma once + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include_next + +#ifdef _RETARGETABLE_LOCKING + +/**************************************************************************** + * Public Type Definitions + ****************************************************************************/ + +/* Actual platfrom-specific definition of struct __lock. + * The size here should be sufficient for a NuttX mutex and recursive mutex. + * This is checked by a static assertion in _libc_stubs.c + */ + +struct __lock +{ + int reserved[4]; +}; + +typedef _LOCK_T _lock_t; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: _lock_init + * + * Description: + * Allocate lock related resources. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * None + * + ****************************************************************************/ + +void _lock_init(_lock_t *plock); + +/**************************************************************************** + * Name: _lock_init_recursive + * + * Description: + * Allocate recursive lock related resources. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * None + * + ****************************************************************************/ + +void _lock_init_recursive(_lock_t *plock); + +/**************************************************************************** + * Name: _lock_close + * + * Description: + * Free lock related resources. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * None + * + ****************************************************************************/ + +void _lock_close(_lock_t *plock); + +/**************************************************************************** + * Name: _lock_close_recursive + * + * Description: + * Free recursive lock related resources. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * None + * + ****************************************************************************/ + +void _lock_close_recursive(_lock_t *plock); + +/**************************************************************************** + * Name: _lock_acquire + * + * Description: + * Acquire lock immediately after the lock object is available. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * None + * + ****************************************************************************/ + +void _lock_acquire(_lock_t *plock); + +/**************************************************************************** + * Name: _lock_acquire_recursive + * + * Description: + * Acquire recursive lock immediately after the lock object is available. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * None + * + ****************************************************************************/ + +void _lock_acquire_recursive(_lock_t *plock); + +/**************************************************************************** + * Name: _lock_try_acquire + * + * Description: + * Acquire lock if the lock object is available. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * Zero for success and non-zero to indicate that the lock cannot be + * acquired + * + ****************************************************************************/ + +int _lock_try_acquire(_lock_t *plock); + +/**************************************************************************** + * Name: _lock_try_acquire_recursive + * + * Description: + * Acquire recursive lock if the lock object is available. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * Zero for success and non-zero to indicate that the lock cannot be + * acquired + * + ****************************************************************************/ + +int _lock_try_acquire_recursive(_lock_t *plock); + +/**************************************************************************** + * Name: _lock_release + * + * Description: + * Relinquish the lock ownership. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * None + * + ****************************************************************************/ + +void _lock_release(_lock_t *plock); + +/**************************************************************************** + * Name: _lock_release_recursive + * + * Description: + * Relinquish the recursive lock ownership. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * None + * + ****************************************************************************/ + +void _lock_release_recursive(_lock_t *plock); + +#endif // _RETARGETABLE_LOCKING diff --git a/arch/risc-v/src/common/riscv_addrenv.c b/arch/risc-v/src/common/riscv_addrenv.c index f26a5d11c2869..20695ed1e6eec 100644 --- a/arch/risc-v/src/common/riscv_addrenv.c +++ b/arch/risc-v/src/common/riscv_addrenv.c @@ -282,7 +282,13 @@ static int create_region(arch_addrenv_t *addrenv, uintptr_t vaddr, /* Then allocate memory for the region data */ - for (j = 0; j < ENTRIES_PER_PGT && nmapped < size; j++) + for (j = 0; +#ifdef CONFIG_PAGING + j < 1; +#else + j < ENTRIES_PER_PGT && nmapped < size; +#endif + j++) { paddr = mm_pgalloc(1); if (!paddr) @@ -533,7 +539,10 @@ int up_addrenv_destroy(arch_addrenv_t *addrenv) ptprev = (uintptr_t *)riscv_pgvaddr(addrenv->spgtables[ARCH_SPGTS - 1]); if (ptprev) { - for (i = 0; i < ENTRIES_PER_PGT; i++, vaddr += pgsize) + /* walk user space only */ + + i = (ARCH_SPGTS < 2) ? vaddr / pgsize : 0; + for (; i < ENTRIES_PER_PGT; i++, vaddr += pgsize) { ptlast = (uintptr_t *)riscv_pgvaddr(mmu_pte_to_paddr(ptprev[i])); if (ptlast) diff --git a/arch/risc-v/src/common/riscv_addrenv_pgmap.c b/arch/risc-v/src/common/riscv_addrenv_pgmap.c index da9e250e7652f..08335387a0295 100644 --- a/arch/risc-v/src/common/riscv_addrenv_pgmap.c +++ b/arch/risc-v/src/common/riscv_addrenv_pgmap.c @@ -147,6 +147,26 @@ bool up_addrenv_user_vaddr(uintptr_t vaddr) return riscv_uservaddr(vaddr); } +/**************************************************************************** + * Name: up_addrenv_page_wipe + * + * Description: + * Wipe a page of physical memory, first mapping it into kernel virtual + * memory. + * + * Input Parameters: + * page - The page physical address. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void up_addrenv_page_wipe(uintptr_t page) +{ + riscv_pgwipe(page); +} + #ifdef CONFIG_MM_KMAP /**************************************************************************** @@ -178,7 +198,7 @@ int up_addrenv_kmap_init(void) next = g_kernel_pgt_pbase; vaddr = CONFIG_ARCH_KMAP_VBASE; - for (i = 0; i < (ARCH_SPGTS - 1); i++) + for (i = 0; i < ARCH_SPGTS; i++) { /* Connect the static page tables */ @@ -191,6 +211,10 @@ int up_addrenv_kmap_init(void) addrenv->satp = mmu_satp_reg(g_kernel_pgt_pbase, 0); + /* When all is set and done, flush the data caches */ + + __DMB(); + return OK; } diff --git a/arch/risc-v/src/common/riscv_checkstack.c b/arch/risc-v/src/common/riscv_checkstack.c index 7ab1dc1ec94e8..8e7d3d7736b8c 100644 --- a/arch/risc-v/src/common/riscv_checkstack.c +++ b/arch/risc-v/src/common/riscv_checkstack.c @@ -181,7 +181,7 @@ size_t up_check_tcbstack(struct tcb_s *tcb) } #if CONFIG_ARCH_INTERRUPTSTACK > 15 -size_t up_check_intstack(void) +size_t up_check_intstack(int cpu) { return riscv_stack_check((uintptr_t)g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~15)); diff --git a/arch/risc-v/src/common/riscv_common_memorymap.h b/arch/risc-v/src/common/riscv_common_memorymap.h index f9b6312b8dcac..f6352fb48e9d2 100644 --- a/arch/risc-v/src/common/riscv_common_memorymap.h +++ b/arch/risc-v/src/common/riscv_common_memorymap.h @@ -45,6 +45,10 @@ #define _START_TBSS _stbss #define _END_TBSS _etbss +#define SMP_STACK_MASK (15) +#define SMP_STACK_SIZE \ + ((CONFIG_IDLETHREAD_STACKSIZE + SMP_STACK_MASK) & ~SMP_STACK_MASK) + /**************************************************************************** * Public Types ****************************************************************************/ @@ -63,7 +67,8 @@ EXTERN uintptr_t g_idle_topstack; /* Address of per-cpu idle stack base */ -EXTERN const uint8_t * const g_cpu_basestack[CONFIG_SMP_NCPUS]; +#define g_cpux_idlestack(cpuid) \ + (g_idle_topstack - SMP_STACK_SIZE * (CONFIG_SMP_NCPUS - (cpuid))) /* Address of the saved user stack pointer */ diff --git a/arch/risc-v/src/common/riscv_cpuidlestack.c b/arch/risc-v/src/common/riscv_cpuidlestack.c index 88625488c843d..6bde88ace6014 100644 --- a/arch/risc-v/src/common/riscv_cpuidlestack.c +++ b/arch/risc-v/src/common/riscv_cpuidlestack.c @@ -37,76 +37,18 @@ * Pre-processor Definitions ****************************************************************************/ -#define SMP_STACK_MASK 15 -#define SMP_STACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~15) #define STACK_ISALIGNED(a) ((uintptr_t)(a) & ~SMP_STACK_MASK) /**************************************************************************** * Private Data ****************************************************************************/ -/* Note: - * 1. QEMU-RV supports up to 8 cores currently. - * 2. RISC-V requires a 16-byte stack alignment. - */ - -#if CONFIG_SMP_NCPUS > 1 -static uint8_t aligned_data(16) cpu1_idlestack[CONFIG_IDLETHREAD_STACKSIZE]; -#endif - -#if CONFIG_SMP_NCPUS > 2 -static uint8_t aligned_data(16) cpu2_idlestack[CONFIG_IDLETHREAD_STACKSIZE]; -#endif - -#if CONFIG_SMP_NCPUS > 3 -static uint8_t aligned_data(16) cpu3_idlestack[CONFIG_IDLETHREAD_STACKSIZE]; -#endif - -#if CONFIG_SMP_NCPUS > 4 -static uint8_t aligned_data(16) cpu4_idlestack[CONFIG_IDLETHREAD_STACKSIZE]; -#endif - -#if CONFIG_SMP_NCPUS > 5 -static uint8_t aligned_data(16) cpu5_idlestack[CONFIG_IDLETHREAD_STACKSIZE]; -#endif - -#if CONFIG_SMP_NCPUS > 6 -static uint8_t aligned_data(16) cpu6_idlestack[CONFIG_IDLETHREAD_STACKSIZE]; -#endif - -#if CONFIG_SMP_NCPUS > 7 -static uint8_t aligned_data(16) cpu7_idlestack[CONFIG_IDLETHREAD_STACKSIZE]; -#endif - /**************************************************************************** * Public Data ****************************************************************************/ -const uint8_t * const g_cpu_basestack[CONFIG_SMP_NCPUS] = -{ - (uint8_t *)_ebss, -#if CONFIG_SMP_NCPUS > 1 - cpu1_idlestack, -#endif -#if CONFIG_SMP_NCPUS > 2 - cpu2_idlestack, -#endif -#if CONFIG_SMP_NCPUS > 3 - cpu3_idlestack, -#endif -#if CONFIG_SMP_NCPUS > 4 - cpu4_idlestack, -#endif -#if CONFIG_SMP_NCPUS > 5 - cpu5_idlestack, -#endif -#if CONFIG_SMP_NCPUS > 6 - cpu6_idlestack, -#endif -#if CONFIG_SMP_NCPUS > 7 - cpu7_idlestack, -#endif -}; +uintptr_t g_idle_topstack = (uintptr_t)_ebss + + SMP_STACK_SIZE * CONFIG_SMP_NCPUS; /**************************************************************************** * Public Functions @@ -155,6 +97,7 @@ const uint8_t * const g_cpu_basestack[CONFIG_SMP_NCPUS] = * ****************************************************************************/ +#ifdef CONFIG_SMP int up_cpu_idlestack(int cpu, struct tcb_s *tcb, size_t stack_size) { uintptr_t stack_alloc; @@ -164,7 +107,7 @@ int up_cpu_idlestack(int cpu, struct tcb_s *tcb, size_t stack_size) /* Get the top of the stack */ - stack_alloc = (uintptr_t)g_cpu_basestack[cpu]; + stack_alloc = (uintptr_t)g_cpux_idlestack(cpu); DEBUGASSERT(stack_alloc != 0 && STACK_ISALIGNED(stack_alloc)); tcb->adj_stack_size = SMP_STACK_SIZE; @@ -172,3 +115,4 @@ int up_cpu_idlestack(int cpu, struct tcb_s *tcb, size_t stack_size) tcb->stack_base_ptr = tcb->stack_alloc_ptr; return OK; } +#endif /* CONFIG_SMP */ diff --git a/arch/risc-v/src/common/riscv_cpupause.c b/arch/risc-v/src/common/riscv_cpupause.c index 8f5c292433050..be6708edbd634 100644 --- a/arch/risc-v/src/common/riscv_cpupause.c +++ b/arch/risc-v/src/common/riscv_cpupause.c @@ -36,6 +36,7 @@ #include "sched/sched.h" #include "riscv_internal.h" +#include "riscv_ipi.h" #include "chip.h" /**************************************************************************** @@ -85,7 +86,7 @@ bool up_cpu_pausereq(int cpu) } /**************************************************************************** - * Name: up_cpu_paused + * Name: up_cpu_paused_save * * Description: * Handle a pause request from another CPU. Normally, this logic is @@ -94,16 +95,8 @@ bool up_cpu_pausereq(int cpu) * pause operation in other contexts where the interrupt cannot be taken * in order to avoid deadlocks. * - * This function performs the following operations: - * - * 1. It saves the current task state at the head of the current assigned - * task list. - * 2. It waits on a spinlock, then - * 3. Returns from interrupt, restoring the state of the new task at the - * head of the ready to run list. - * * Input Parameters: - * cpu - The index of the CPU to be paused + * None * * Returned Value: * On success, OK is returned. Otherwise, a negated errno value indicating @@ -111,7 +104,7 @@ bool up_cpu_pausereq(int cpu) * ****************************************************************************/ -int up_cpu_paused(int cpu) +int up_cpu_paused_save(void) { struct tcb_s *tcb = this_task(); @@ -131,6 +124,38 @@ int up_cpu_paused(int cpu) riscv_savecontext(tcb); + return OK; +} + +/**************************************************************************** + * Name: up_cpu_paused + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. + * + * This function performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. + * + * Input Parameters: + * cpu - The index of the CPU to be paused + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused(int cpu) +{ /* Wait for the spinlock to be released */ spin_unlock(&g_cpu_paused[cpu]); @@ -141,11 +166,31 @@ int up_cpu_paused(int cpu) spin_lock(&g_cpu_wait[cpu]); - /* Restore the exception context of the tcb at the (new) head of the - * assigned task list. - */ + spin_unlock(&g_cpu_wait[cpu]); + spin_unlock(&g_cpu_resumed[cpu]); + + return OK; +} + +/**************************************************************************** + * Name: up_cpu_paused_restore + * + * Description: + * Restore the state of the CPU after it was paused via up_cpu_pause(), + * and resume normal tasking. + * + * Input Parameters: + * None + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ - tcb = this_task(); +int up_cpu_paused_restore(void) +{ + struct tcb_s *tcb = this_task(); #ifdef CONFIG_SCHED_INSTRUMENTATION /* Notify that we have resumed */ @@ -163,9 +208,6 @@ int up_cpu_paused(int cpu) riscv_restorecontext(tcb); - spin_unlock(&g_cpu_wait[cpu]); - spin_unlock(&g_cpu_resumed[cpu]); - return OK; } @@ -189,7 +231,7 @@ int riscv_pause_handler(int irq, void *c, void *arg) /* Clear IPI (Inter-Processor-Interrupt) */ - putreg32(0, (uintptr_t)RISCV_IPI + (4 * cpu)); + riscv_ipi_clear(cpu); /* Check for false alarms. Such false could occur as a consequence of * some deadlock breaking logic that might have already serviced the SG2 @@ -265,7 +307,7 @@ int up_cpu_pause(int cpu) /* Execute Pause IRQ to CPU(cpu) */ - putreg32(1, (uintptr_t)RISCV_IPI + (4 * cpu)); + riscv_ipi_send(cpu); /* Wait for the other CPU to unlock g_cpu_paused meaning that * it is fully paused and ready for up_cpu_resume(); @@ -280,7 +322,7 @@ int up_cpu_pause(int cpu) * called. g_cpu_paused will be unlocked in any case. */ - return 0; + return OK; } /**************************************************************************** @@ -330,5 +372,5 @@ int up_cpu_resume(int cpu) spin_unlock(&g_cpu_resumed[cpu]); - return 0; + return OK; } diff --git a/arch/risc-v/src/common/riscv_cpustart.c b/arch/risc-v/src/common/riscv_cpustart.c index 068cbce8fe056..244b9caa8958f 100644 --- a/arch/risc-v/src/common/riscv_cpustart.c +++ b/arch/risc-v/src/common/riscv_cpustart.c @@ -38,6 +38,7 @@ #include "sched/sched.h" #include "init/init.h" #include "riscv_internal.h" +#include "riscv_ipi.h" #ifdef CONFIG_BUILD_KERNEL # include "riscv_mmu.h" @@ -67,7 +68,7 @@ void riscv_cpu_boot(int cpu) { /* Clear IPI for CPU(cpu) */ - putreg32(0, (uintptr_t)RISCV_IPI + (4 * cpu)); + riscv_ipi_clear(cpu); /* Enable machine software interrupt for IPI to boot */ @@ -77,11 +78,13 @@ void riscv_cpu_boot(int cpu) asm("WFI"); -#ifdef CONFIG_BUILD_KERNEL +#ifdef CONFIG_RISCV_PERCPU_SCRATCH /* Initialize the per CPU areas */ riscv_percpu_add_hart((uintptr_t)cpu); +#endif +#ifdef CONFIG_BUILD_KERNEL /* Enable MMU */ binfo("mmu_enable: satp=%lx\n", g_kernel_pgt_pbase); @@ -105,7 +108,7 @@ void riscv_cpu_boot(int cpu) /* Clear machine software interrupt for CPU(cpu) */ - putreg32(0, (uintptr_t)RISCV_IPI + (4 * cpu)); + riscv_ipi_clear(cpu); #ifdef CONFIG_SCHED_INSTRUMENTATION /* Notify that this CPU has started */ @@ -159,7 +162,7 @@ int up_cpu_start(int cpu) /* Send IPI to CPU(cpu) */ - putreg32(1, (uintptr_t)RISCV_IPI + (cpu * 4)); + riscv_ipi_send(cpu); return 0; } diff --git a/arch/risc-v/src/common/riscv_exception.c b/arch/risc-v/src/common/riscv_exception.c index f560a60b0a0be..68c34a0ad1881 100644 --- a/arch/risc-v/src/common/riscv_exception.c +++ b/arch/risc-v/src/common/riscv_exception.c @@ -30,7 +30,16 @@ #include #include +#ifdef CONFIG_PAGING +# include +#endif + +#ifdef CONFIG_PAGING +# include "pgalloc.h" +# include "riscv_mmu.h" +#endif +#include "sched/sched.h" #include "riscv_internal.h" #include "chip.h" @@ -72,6 +81,9 @@ static const char *g_reasons_str[RISCV_MAX_EXCEPTION + 1] = int riscv_exception(int mcause, void *regs, void *args) { +#ifdef CONFIG_ARCH_KERNEL_STACK + FAR struct tcb_s *tcb = this_task(); +#endif uintptr_t cause = mcause & RISCV_IRQ_MASK; _alert("EXCEPTION: %s. MCAUSE: %" PRIxREG ", EPC: %" PRIxREG @@ -79,13 +91,151 @@ int riscv_exception(int mcause, void *regs, void *args) mcause > RISCV_MAX_EXCEPTION ? "Unknown" : g_reasons_str[cause], cause, READ_CSR(CSR_EPC), READ_CSR(CSR_TVAL)); - _alert("PANIC!!! Exception = %" PRIxREG "\n", cause); - up_irq_save(); - CURRENT_REGS = regs; - PANIC_WITH_REGS("panic", regs); +#ifdef CONFIG_ARCH_KERNEL_STACK + if ((tcb->flags & TCB_FLAG_TTYPE_MASK) != TCB_FLAG_TTYPE_KERNEL) + { +# if CONFIG_TASK_NAME_SIZE > 0 + _alert("Segmentation fault in PID %d: %s\n", tcb->pid, tcb->name); +# else + _alert("Segmentation fault in PID %d\n", tcb->pid); +# endif + + tcb->flags |= TCB_FLAG_FORCED_CANCEL; + + /* Return to _exit function in privileged mode with argument SIGSEGV */ + + CURRENT_REGS[REG_EPC] = (uintptr_t)_exit; + CURRENT_REGS[REG_A0] = SIGSEGV; + CURRENT_REGS[REG_INT_CTX] |= STATUS_PPP; + + /* Continue with kernel stack in use. The frame(s) in kernel stack + * are no longer needed, so just set it to top + */ + + CURRENT_REGS[REG_SP] = (uintptr_t)tcb->xcp.ktopstk; + } + else +#endif + { + _alert("PANIC!!! Exception = %" PRIxREG "\n", cause); + up_irq_save(); + CURRENT_REGS = regs; + PANIC_WITH_REGS("panic", regs); + } + + return 0; +} + +/**************************************************************************** + * Name: riscv_fillpage + * + * Description: + * This function is an exception handler for page faults in a RISC-V. + * It is invoked when a page fault exception occurs, which is typically + * when a process tries to access a page that is not currently in memory. + * + * The function takes as arguments the machine cause (mcause) which + * indicates the cause of the exception, a pointer to the register state + * at the time of the exception (regs), and a pointer to any additional + * arguments (args). + * + * The function should handle the exception appropriately, typically by + * loading the required page into memory and updating the page table. + * + * Input Parameters: + * mcause - The machine cause of the exception. + * regs - A pointer to the register state at the time of the exception. + * args - A pointer to any additional arguments. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_PAGING +int riscv_fillpage(int mcause, void *regs, void *args) +{ + uintptr_t cause = mcause & RISCV_IRQ_MASK; + uintptr_t ptlast; + uintptr_t ptprev; + uintptr_t paddr; + uintptr_t vaddr; + uint32_t ptlevel; + uintptr_t satp; + uint32_t mmuflags; + + _info("EXCEPTION: %s. MCAUSE: %" PRIxREG ", EPC: %" PRIxREG + ", MTVAL: %" PRIxREG "\n", + mcause > RISCV_MAX_EXCEPTION ? "Unknown" : g_reasons_str[cause], + cause, READ_CSR(CSR_EPC), READ_CSR(CSR_TVAL)); + vaddr = MM_PGALIGNDOWN(READ_CSR(CSR_TVAL)); + if (vaddr >= CONFIG_ARCH_TEXT_VBASE && vaddr <= ARCH_TEXT_VEND) + { + mmuflags = MMU_UTEXT_FLAGS; + + /* Write access to .text region needs to be set according to + * https://github.com/apache/nuttx/pull/6193. + */ + + mmuflags |= PTE_W; + } + else if (vaddr >= CONFIG_ARCH_DATA_VBASE && vaddr <= ARCH_DATA_VEND) + { + mmuflags = MMU_UDATA_FLAGS; + } + else if (vaddr >= CONFIG_ARCH_HEAP_VBASE && vaddr <= ARCH_HEAP_VEND) + { + mmuflags = MMU_UDATA_FLAGS; + } + else + { + _alert("PANIC!!! virtual address not mappable: %" PRIxPTR "\n", vaddr); + up_irq_save(); + CURRENT_REGS = regs; + PANIC_WITH_REGS("panic", regs); + } + + satp = READ_CSR(CSR_SATP); + ptprev = riscv_pgvaddr(mmu_satp_to_paddr(satp)); + ptlevel = ARCH_SPGTS; + paddr = mmu_pte_to_paddr(mmu_ln_getentry(ptlevel, ptprev, vaddr)); + if (!paddr) + { + /* Nothing yet, allocate one page for final level page table */ + + paddr = mm_pgalloc(1); + if (!paddr) + { + return -ENOMEM; + } + + /* Map the page table to the prior level */ + + mmu_ln_setentry(ptlevel, ptprev, paddr, vaddr, MMU_UPGT_FLAGS); + + /* This is then used to map the final level */ + + riscv_pgwipe(paddr); + } + + ptlast = riscv_pgvaddr(paddr); + paddr = mm_pgalloc(1); + if (!paddr) + { + return -ENOMEM; + } + + /* Wipe the physical page memory */ + + riscv_pgwipe(paddr); + + /* Then map the virtual address to the physical address */ + + mmu_ln_setentry(ptlevel + 1, ptlast, paddr, vaddr, mmuflags); return 0; } +#endif /* CONFIG_PAGING */ /**************************************************************************** * Name: riscv_exception_attach @@ -130,9 +280,16 @@ void riscv_exception_attach(void) #endif irq_attach(RISCV_IRQ_INSTRUCTIONPF, riscv_exception, NULL); + +#ifdef CONFIG_PAGING + irq_attach(RISCV_IRQ_LOADPF, riscv_fillpage, NULL); + irq_attach(RISCV_IRQ_STOREPF, riscv_fillpage, NULL); +#else irq_attach(RISCV_IRQ_LOADPF, riscv_exception, NULL); - irq_attach(RISCV_IRQ_RESERVED, riscv_exception, NULL); irq_attach(RISCV_IRQ_STOREPF, riscv_exception, NULL); +#endif + + irq_attach(RISCV_IRQ_RESERVED, riscv_exception, NULL); #ifdef CONFIG_SMP irq_attach(RISCV_IRQ_SOFT, riscv_pause_handler, NULL); diff --git a/arch/risc-v/src/common/riscv_exception_common.S b/arch/risc-v/src/common/riscv_exception_common.S index 9d78b65c09673..97553a0d4424c 100644 --- a/arch/risc-v/src/common/riscv_exception_common.S +++ b/arch/risc-v/src/common/riscv_exception_common.S @@ -182,7 +182,7 @@ exception_common: /* Total required interrupt stack size */ -#define STACK_ALLOC_SIZE (CONFIG_ARCH_INTERRUPTSTACK * CONFIG_SMP_NCPUS) +#define STACK_ALLOC_SIZE (INT_STACK_SIZE * CONFIG_SMP_NCPUS) #if CONFIG_ARCH_INTERRUPTSTACK > 15 .bss diff --git a/arch/risc-v/src/common/riscv_exit.c b/arch/risc-v/src/common/riscv_exit.c index 8260754a75882..86619cb3f5a6f 100644 --- a/arch/risc-v/src/common/riscv_exit.c +++ b/arch/risc-v/src/common/riscv_exit.c @@ -62,8 +62,6 @@ void up_exit(int status) enter_critical_section(); - sinfo("TCB=%p exiting\n", tcb); - nxsched_dumponexit(); /* Destroy the task at the head of the ready to run list. */ diff --git a/arch/risc-v/src/common/riscv_getintstack.c b/arch/risc-v/src/common/riscv_getintstack.c index 9222f21a112ef..de06859c5d79a 100644 --- a/arch/risc-v/src/common/riscv_getintstack.c +++ b/arch/risc-v/src/common/riscv_getintstack.c @@ -37,8 +37,8 @@ ****************************************************************************/ #if CONFIG_ARCH_INTERRUPTSTACK > 3 -uintptr_t up_get_intstackbase(void) +uintptr_t up_get_intstackbase(int cpu) { - return (uintptr_t)g_intstackalloc; + return (uintptr_t)g_intstacktop - cpu * INT_STACK_SIZE; } #endif diff --git a/arch/risc-v/src/common/riscv_getnewintctx.c b/arch/risc-v/src/common/riscv_getnewintctx.c index 2588ff2841dc4..cd6a98c7ac34c 100644 --- a/arch/risc-v/src/common/riscv_getnewintctx.c +++ b/arch/risc-v/src/common/riscv_getnewintctx.c @@ -67,6 +67,9 @@ uintptr_t riscv_get_newintctx(void) return (status | STATUS_PPP | STATUS_SUM | STATUS_PIE #ifdef CONFIG_ARCH_FPU | MSTATUS_FS_INIT +#endif +#ifdef CONFIG_ARCH_RV_ISA_V + | MSTATUS_VS_INIT #endif ); } diff --git a/arch/risc-v/src/common/riscv_initialstate.c b/arch/risc-v/src/common/riscv_initialstate.c index 08895958befdb..f13203a51916a 100644 --- a/arch/risc-v/src/common/riscv_initialstate.c +++ b/arch/risc-v/src/common/riscv_initialstate.c @@ -30,6 +30,7 @@ #include #include +#include #include #include "addrenv.h" @@ -56,6 +57,9 @@ void up_initial_state(struct tcb_s *tcb) { struct xcptcontext *xcp = &tcb->xcp; +#if defined(CONFIG_ARCH_RV_ISA_V) && (CONFIG_ARCH_RV_VECTOR_BYTE_LENGTH == 0) + uintptr_t *vregs = tcb->vregs; +#endif uintptr_t regval; uintptr_t topstack; #ifdef CONFIG_ARCH_KERNEL_STACK @@ -66,14 +70,36 @@ void up_initial_state(struct tcb_s *tcb) memset(xcp, 0, sizeof(struct xcptcontext)); +#if defined(CONFIG_ARCH_RV_ISA_V) && (CONFIG_ARCH_RV_VECTOR_BYTE_LENGTH == 0) + + /* Initialize vector registers */ + + if (vregs == NULL) + { + regval = READ_CSR(CSR_VLENB); + if (regval != 0) + { + /* There are 32 vector registers(v0 - v31) with vlenb length. */ + + xcp->vregs = kmm_calloc(1, regval * 32 + VPU_XCPT_SIZE); + DEBUGASSERT(xcp->vregs != NULL); + } + } + else + { + /* Keep the vector region if task restart */ + + xcp->vregs = vregs; + } +#endif + /* Initialize the idle thread stack */ if (tcb->pid == IDLE_PROCESS_ID) { - tcb->stack_alloc_ptr = (void *)(g_idle_topstack - - CONFIG_IDLETHREAD_STACKSIZE); + tcb->stack_alloc_ptr = (void *)g_cpux_idlestack(riscv_mhartid()); tcb->stack_base_ptr = tcb->stack_alloc_ptr; - tcb->adj_stack_size = CONFIG_IDLETHREAD_STACKSIZE; + tcb->adj_stack_size = SMP_STACK_SIZE; #ifdef CONFIG_STACK_COLORATION /* If stack debug is enabled, then fill the stack with a diff --git a/arch/risc-v/src/common/riscv_internal.h b/arch/risc-v/src/common/riscv_internal.h index ac16c0bd87f93..d2a09e456e4ff 100644 --- a/arch/risc-v/src/common/riscv_internal.h +++ b/arch/risc-v/src/common/riscv_internal.h @@ -81,6 +81,9 @@ #define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) #define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) +/* Interrupt Stack macros */ +#define INT_STACK_SIZE (STACK_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK)) + /* Format output with register width and hex */ #ifdef CONFIG_ARCH_RV32 @@ -133,16 +136,16 @@ #define READ_CSR(reg) \ ({ \ - uintptr_t reg##_val; \ - __asm__ __volatile__("csrr %0, " __STR(reg) : "=r"(reg##_val)); \ - reg##_val; \ + uintptr_t __regval; \ + __asm__ __volatile__("csrr %0, " __STR(reg) : "=r"(__regval)); \ + __regval; \ }) #define READ_AND_SET_CSR(reg, bits) \ ({ \ - uintptr_t reg##_val; \ - __asm__ __volatile__("csrrs %0, " __STR(reg) ", %1": "=r"(reg##_val) : "rK"(bits)); \ - reg##_val; \ + uintptr_t __regval; \ + __asm__ __volatile__("csrrs %0, " __STR(reg) ", %1": "=r"(__regval) : "rK"(bits)); \ + __regval; \ }) #define WRITE_CSR(reg, val) \ @@ -160,8 +163,45 @@ __asm__ __volatile__("csrc " __STR(reg) ", %0" :: "rK"(bits)); \ }) +#define riscv_append_pmp_region(a, b, s) \ + riscv_config_pmp_region(riscv_next_free_pmp_region(), a, b, s) + #endif +/* SBI Extension IDs */ + +#define SBI_EXT_HSM 0x48534D +#define SBI_EXT_IPI 0x735049 +#define SBI_EXT_TIME 0x54494D45 +#define SBI_EXT_SRST 0x53525354 + +/* SBI function IDs for TIME extension */ + +#define SBI_EXT_TIME_SET_TIMER 0x0 + +/* SBI function IDs for HSM extension */ + +#define SBI_EXT_HSM_HART_START 0x0 + +/* SBI function IDs for IPI extension */ + +#define SBI_EXT_IPI_SEND_IPI 0x0 + +/* SBI function IDs for SRST extension */ + +#define SBI_EXT_SRST_SYS_RESET 0x0 + +/* SBI system reset type */ + +#define SBI_SRST_TYPE_SHUTDOWN 0 +#define SBI_SRST_TYPE_REBOOT_COLD 1 +#define SBI_SRST_TYPE_REBOOT_WARM 1 + +/* SBI system reset reason */ + +#define SBI_SRST_REASON_NONE 0 +#define SBI_SRST_REASON_FAILURE 1 + /**************************************************************************** * Public Types ****************************************************************************/ @@ -228,6 +268,24 @@ static inline uintptr_t *riscv_fpuregs(struct tcb_s *tcb) # define riscv_fpuregs(tcb) #endif +#ifdef CONFIG_ARCH_RV_ISA_V +void riscv_vpuconfig(void); +void riscv_savevpu(uintptr_t *regs, uintptr_t *vregs); +void riscv_restorevpu(uintptr_t *regs, uintptr_t *vregs); + +/* Get VPU register save area */ + +static inline uintptr_t *riscv_vpuregs(struct tcb_s *tcb) +{ + return tcb->xcp.vregs; +} +#else +# define riscv_vpuconfig() +# define riscv_savevpu(regs, vregs) +# define riscv_restorevpu(regs, vregs) +# define riscv_vpuregs(tcb) +#endif + /* Save / restore context of task */ static inline void riscv_savecontext(struct tcb_s *tcb) @@ -239,6 +297,12 @@ static inline void riscv_savecontext(struct tcb_s *tcb) riscv_savefpu(tcb->xcp.regs, riscv_fpuregs(tcb)); #endif + +#ifdef CONFIG_ARCH_RV_ISA_V + /* Save current process VPU state to TCB */ + + riscv_savevpu(tcb->xcp.regs, riscv_vpuregs(tcb)); +#endif } static inline void riscv_restorecontext(struct tcb_s *tcb) @@ -250,6 +314,12 @@ static inline void riscv_restorecontext(struct tcb_s *tcb) riscv_restorefpu(tcb->xcp.regs, riscv_fpuregs(tcb)); #endif + +#ifdef CONFIG_ARCH_RV_ISA_V + /* Restore VPU state for next process */ + + riscv_restorevpu(tcb->xcp.regs, riscv_vpuregs(tcb)); +#endif } /* RISC-V PMP Config ********************************************************/ @@ -264,8 +334,12 @@ int riscv_next_free_pmp_region(void); /* RISC-V SBI wrappers ******************************************************/ #ifdef CONFIG_ARCH_USE_S_MODE +uintptr_t riscv_sbi_send_ipi(uint32_t hmask, uintptr_t hbase); void riscv_sbi_set_timer(uint64_t stime_value); uint64_t riscv_sbi_get_time(void); +uintptr_t riscv_sbi_boot_secondary(uint32_t hartid, uintptr_t addr, + uintptr_t a1); +uintptr_t riscv_sbi_system_reset(uint32_t type, uint32_t reason); #endif /* Power management *********************************************************/ @@ -312,6 +386,7 @@ void riscv_netinitialize(void); uintptr_t *riscv_doirq(int irq, uintptr_t *regs); int riscv_exception(int mcause, void *regs, void *args); +int riscv_fillpage(int mcause, void *regs, void *args); int riscv_misaligned(int irq, void *context, void *arg); /* Debug ********************************************************************/ diff --git a/arch/risc-v/src/common/riscv_ipi.h b/arch/risc-v/src/common/riscv_ipi.h new file mode 100644 index 0000000000000..1b2b649f3ba8e --- /dev/null +++ b/arch/risc-v/src/common/riscv_ipi.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/risc-v/src/common/riscv_ipi.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_COMMON_RISCV_IPI_H +#define __ARCH_RISCV_SRC_COMMON_RISCV_IPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "riscv_internal.h" +#include "chip.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +static inline void riscv_ipi_send(int cpu) +{ +#if defined(CONFIG_ARCH_USE_S_MODE) + riscv_sbi_send_ipi(0x1, cpu); +#elif defined(RISCV_IPI) + putreg32(1, (uintptr_t)RISCV_IPI + (4 * cpu)); +#else +# error "No IPI support for this SoC" +#endif +} + +static inline void riscv_ipi_clear(int cpu) +{ +#if defined(RISCV_IPI) + putreg32(0, (uintptr_t)RISCV_IPI + (4 * cpu)); +#endif + CLEAR_CSR(CSR_IP, IP_SIP); +} + +#endif /* __ARCH_RISCV_SRC_COMMON_RISCV_IPI_H */ diff --git a/arch/risc-v/src/common/riscv_macros.S b/arch/risc-v/src/common/riscv_macros.S index 5f9bd12f65a88..0ab8358d507d9 100644 --- a/arch/risc-v/src/common/riscv_macros.S +++ b/arch/risc-v/src/common/riscv_macros.S @@ -140,6 +140,48 @@ .endm +/**************************************************************************** + * Name: riscv_savevpu + * + * Parameter: + * in - Pointer to where the save is performed (e.g. sp) + * + * Description: + * Save the VPU context registers (i.e. work / temp / etc). + * + ****************************************************************************/ + +.macro riscv_savevpu in + + /* Store all vector registers */ + + mv t1, \in + + csrr t0, CSR_VSTART + REGSTORE t0, REG_VSTART(t1) + csrr t0, CSR_VTYPE + REGSTORE t0, REG_VTYPE(t1) + csrr t0, CSR_VL + REGSTORE t0, REG_VL(t1) + csrr t0, CSR_VCSR + REGSTORE t0, REG_VCSR(t1) + csrr t0, CSR_VLENB + REGSTORE t0, REG_VLENB(t1) + + addi t1, t1, VPU_XCPT_SIZE + + vsetvli t2, x0, e8, m8, ta, ma + + vse8.v v0, (t1) + add t1, t1, t2 + vse8.v v8, (t1) + add t1, t1, t2 + vse8.v v16, (t1) + add t1, t1, t2 + vse8.v v24, (t1) + +.endm + /**************************************************************************** * Name: load_ctx * @@ -243,6 +285,47 @@ .endm +/**************************************************************************** + * Name: riscv_loadvpu + * + * Parameter: + * out - Pointer to where the load is performed (e.g. sp) + * + * Description: + * Load the VPU context registers (i.e. work / temp / etc). + * + ****************************************************************************/ + +.macro riscv_loadvpu out + + /* Load all vector registers */ + + mv t0, \out + addi t1, t0, VPU_XCPT_SIZE + + vsetvli t2, x0, e8, m8, ta, ma + + vle8.v v0, (t1) + add t1, t1, t2 + vle8.v v8, (t1) + add t1, t1, t2 + vle8.v v16, (t1) + add t1, t1, t2 + vle8.v v24, (t1) + + mv t1, t0 + + REGLOAD t0, REG_VTYPE(t1) + REGLOAD t3, REG_VL(t1) + vsetvl x0, t3, t0 + + REGLOAD t0, REG_VSTART(t1) + csrw CSR_VSTART, t0 + REGLOAD t0, REG_VCSR(t1) + csrw CSR_VCSR, t0 + +.endm + /**************************************************************************** * Name: setintstack * @@ -274,10 +357,52 @@ ****************************************************************************/ .macro riscv_mhartid out -#ifdef CONFIG_ARCH_USE_S_MODE +#ifdef CONFIG_RISCV_PERCPU_SCRATCH csrr \out, CSR_SCRATCH REGLOAD \out, RISCV_PERCPU_HARTID(\out) #else - csrr \out, mhartid + csrr \out, CSR_MHARTID #endif .endm + +/**************************************************************************** + * Name: riscv_set_inital_sp + * + * Description: + * Set inital sp for riscv core. This function should be only called + * when initing. + * + * sp (stack top) = sp base + idle stack size * hart id + * sp (stack base) = sp (stack top) + idle stack size * - XCPTCONTEXT_SIZE + * + * Note: The XCPTCONTEXT_SIZE byte after stack base is reserved for + * up_initial_state since we are already running and using + * the per CPU idle stack. + * + * TODO: Support non-zero boot hart. + * + * Parameter: + * base - Pointer to where the stack is allocated (e.g. _ebss) + * size - Stack size for pre cpu to allocate + * hartid - Hart id register of this hart (Usually a0) + * + ****************************************************************************/ +.macro riscv_set_inital_sp base, size, hartid + la t0, \base + li t1, \size + mul t1, \hartid, t1 + add t0, t0, t1 + + /* ensure the last XCPTCONTEXT_SIZE is reserved for non boot CPU */ + + bnez \hartid, 998f + li t1, STACK_ALIGN_DOWN(\size) + j 999f + +998: + li t1, STACK_ALIGN_DOWN(\size - XCPTCONTEXT_SIZE) + +999: + add t0, t0, t1 + mv sp, t0 +.endm diff --git a/arch/risc-v/src/common/riscv_mmu.h b/arch/risc-v/src/common/riscv_mmu.h index 0e6e1b2b3899c..a2cd9f0ee2339 100644 --- a/arch/risc-v/src/common/riscv_mmu.h +++ b/arch/risc-v/src/common/riscv_mmu.h @@ -21,6 +21,10 @@ #ifndef ___ARCH_RISC_V_SRC_COMMON_RISCV_MMU_H_ #define ___ARCH_RISC_V_SRC_COMMON_RISCV_MMU_H_ +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + /* RV32/64 page size */ #define RV_MMU_PAGE_SHIFT (12) @@ -150,6 +154,16 @@ extern uintptr_t g_kernel_pgt_pbase; +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +void weak_function mmu_flush_cache(uintptr_t); + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + /**************************************************************************** * Name: mmu_satp_reg * @@ -197,6 +211,13 @@ static inline void mmu_write_satp(uintptr_t reg) : "rK" (reg) : "memory" ); + + /* Flush the MMU Cache if needed (T-Head C906) */ + + if (mmu_flush_cache != NULL) + { + mmu_flush_cache(reg); + } } /**************************************************************************** diff --git a/arch/risc-v/src/common/riscv_mtimer.c b/arch/risc-v/src/common/riscv_mtimer.c index 5746c06774234..bd17bafe59f28 100644 --- a/arch/risc-v/src/common/riscv_mtimer.c +++ b/arch/risc-v/src/common/riscv_mtimer.c @@ -90,7 +90,7 @@ static uint64_t riscv_mtimer_get_mtime(struct riscv_mtimer_lowerhalf_s *priv) * it could be read from the CSR "time". */ - return -1 == priv->mtime ? READ_CSR(time) : getreg64(priv->mtime); + return -1 == priv->mtime ? READ_CSR(CSR_TIME) : getreg64(priv->mtime); #else uint32_t hi; uint32_t lo; @@ -127,6 +127,19 @@ static void riscv_mtimer_set_mtimecmp(struct riscv_mtimer_lowerhalf_s *priv, __MB(); } #else + +#ifdef CONFIG_ARCH_RV_EXT_SSTC +static inline void riscv_write_stime(uint64_t value) +{ +#ifdef CONFIG_ARCH_RV64 + WRITE_CSR(CSR_STIMECMP, value); +#else + WRITE_CSR(CSR_STIMECMP, (uint32_t)value); + WRITE_CSR(CSR_STIMECMPH, (uint32_t)(value >> 32)); +#endif +} +#endif + static uint64_t riscv_mtimer_get_mtime(struct riscv_mtimer_lowerhalf_s *priv) { UNUSED(priv); @@ -137,7 +150,11 @@ static void riscv_mtimer_set_mtimecmp(struct riscv_mtimer_lowerhalf_s *priv, uint64_t value) { UNUSED(priv); +#ifndef CONFIG_ARCH_RV_EXT_SSTC riscv_sbi_set_timer(value); +#else + riscv_write_stime(value); +#endif } #endif diff --git a/arch/risc-v/src/common/riscv_percpu.c b/arch/risc-v/src/common/riscv_percpu.c index 458682746ac9a..13072ff8cd3a4 100644 --- a/arch/risc-v/src/common/riscv_percpu.c +++ b/arch/risc-v/src/common/riscv_percpu.c @@ -41,7 +41,6 @@ ****************************************************************************/ #define HART_CNT (CONFIG_SMP_NCPUS) -#define STACK_SIZE (STACK_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK)) static_assert(RISCV_PERCPU_HARTID == offsetof(riscv_percpu_t, hartid), "RISCV_PERCPU_HARTID offset is wrong"); @@ -96,7 +95,7 @@ static void riscv_percpu_init(void) /* Set interrupt stack (if any) */ #if CONFIG_ARCH_INTERRUPTSTACK > 15 - g_percpu[i].irq_stack = (uintptr_t)g_intstacktop - i * STACK_SIZE; + g_percpu[i].irq_stack = (uintptr_t)g_intstacktop - i * INT_STACK_SIZE; #endif sq_addlast((struct sq_entry_s *) &g_percpu[i], &g_freelist); diff --git a/arch/risc-v/src/common/riscv_pmp.c b/arch/risc-v/src/common/riscv_pmp.c index e6074b5154b02..97b39b8fe8c0a 100644 --- a/arch/risc-v/src/common/riscv_pmp.c +++ b/arch/risc-v/src/common/riscv_pmp.c @@ -134,9 +134,9 @@ static bool pmp_check_region_attrs(uintptr_t base, uintptr_t size, case PMPCFG_A_NAPOT: { - /* For NAPOT, both base and size must be properly aligned */ + /* For NAPOT, Naturally aligned power-of-two region, >= 8 bytes */ - if ((base & 0x07) != 0 || size < 8) + if ((base & 0x07) != 0 || size < 8 || (size & (size - 1)) != 0) { return false; } @@ -180,16 +180,16 @@ static uintptr_t pmp_read_region_cfg(uintptr_t region) switch (region) { case 0 ... 3: - return PMP_READ_REGION_FROM_REG(region, pmpcfg0); + return PMP_READ_REGION_FROM_REG(region, CSR_PMPCFG0); case 4 ... 7: - return PMP_READ_REGION_FROM_REG(region, pmpcfg1); + return PMP_READ_REGION_FROM_REG(region, CSR_PMPCFG1); case 8 ... 11: - return PMP_READ_REGION_FROM_REG(region, pmpcfg2); + return PMP_READ_REGION_FROM_REG(region, CSR_PMPCFG2); case 12 ... 15: - return PMP_READ_REGION_FROM_REG(region, pmpcfg3); + return PMP_READ_REGION_FROM_REG(region, CSR_PMPCFG3); default: break; @@ -198,10 +198,10 @@ static uintptr_t pmp_read_region_cfg(uintptr_t region) switch (region) { case 0 ... 7: - return PMP_READ_REGION_FROM_REG(region, pmpcfg0); + return PMP_READ_REGION_FROM_REG(region, CSR_PMPCFG0); case 8 ... 15: - return PMP_READ_REGION_FROM_REG(region, pmpcfg2); + return PMP_READ_REGION_FROM_REG(region, CSR_PMPCFG2); default: break; @@ -232,52 +232,52 @@ static uintptr_t pmp_read_addr(uintptr_t region) switch (region) { case 0: - return READ_CSR(pmpaddr0); + return READ_CSR(CSR_PMPADDR0); case 1: - return READ_CSR(pmpaddr1); + return READ_CSR(CSR_PMPADDR1); case 2: - return READ_CSR(pmpaddr2); + return READ_CSR(CSR_PMPADDR2); case 3: - return READ_CSR(pmpaddr3); + return READ_CSR(CSR_PMPADDR3); case 4: - return READ_CSR(pmpaddr4); + return READ_CSR(CSR_PMPADDR4); case 5: - return READ_CSR(pmpaddr5); + return READ_CSR(CSR_PMPADDR5); case 6: - return READ_CSR(pmpaddr6); + return READ_CSR(CSR_PMPADDR6); case 7: - return READ_CSR(pmpaddr7); + return READ_CSR(CSR_PMPADDR7); case 8: - return READ_CSR(pmpaddr8); + return READ_CSR(CSR_PMPADDR8); case 9: - return READ_CSR(pmpaddr9); + return READ_CSR(CSR_PMPADDR9); case 10: - return READ_CSR(pmpaddr10); + return READ_CSR(CSR_PMPADDR10); case 11: - return READ_CSR(pmpaddr11); + return READ_CSR(CSR_PMPADDR11); case 12: - return READ_CSR(pmpaddr12); + return READ_CSR(CSR_PMPADDR12); case 13: - return READ_CSR(pmpaddr13); + return READ_CSR(CSR_PMPADDR13); case 14: - return READ_CSR(pmpaddr14); + return READ_CSR(CSR_PMPADDR14); case 15: - return READ_CSR(pmpaddr15); + return READ_CSR(CSR_PMPADDR15); default: break; @@ -440,67 +440,67 @@ int riscv_config_pmp_region(uintptr_t region, uintptr_t attr, switch (region) { case 0: - WRITE_CSR(pmpaddr0, addr); + WRITE_CSR(CSR_PMPADDR0, addr); break; case 1: - WRITE_CSR(pmpaddr1, addr); + WRITE_CSR(CSR_PMPADDR1, addr); break; case 2: - WRITE_CSR(pmpaddr2, addr); + WRITE_CSR(CSR_PMPADDR2, addr); break; case 3: - WRITE_CSR(pmpaddr3, addr); + WRITE_CSR(CSR_PMPADDR3, addr); break; case 4: - WRITE_CSR(pmpaddr4, addr); + WRITE_CSR(CSR_PMPADDR4, addr); break; case 5: - WRITE_CSR(pmpaddr5, addr); + WRITE_CSR(CSR_PMPADDR5, addr); break; case 6: - WRITE_CSR(pmpaddr6, addr); + WRITE_CSR(CSR_PMPADDR6, addr); break; case 7: - WRITE_CSR(pmpaddr7, addr); + WRITE_CSR(CSR_PMPADDR7, addr); break; case 8: - WRITE_CSR(pmpaddr8, addr); + WRITE_CSR(CSR_PMPADDR8, addr); break; case 9: - WRITE_CSR(pmpaddr9, addr); + WRITE_CSR(CSR_PMPADDR9, addr); break; case 10: - WRITE_CSR(pmpaddr10, addr); + WRITE_CSR(CSR_PMPADDR10, addr); break; case 11: - WRITE_CSR(pmpaddr11, addr); + WRITE_CSR(CSR_PMPADDR11, addr); break; case 12: - WRITE_CSR(pmpaddr12, addr); + WRITE_CSR(CSR_PMPADDR12, addr); break; case 13: - WRITE_CSR(pmpaddr13, addr); + WRITE_CSR(CSR_PMPADDR13, addr); break; case 14: - WRITE_CSR(pmpaddr14, addr); + WRITE_CSR(CSR_PMPADDR14, addr); break; case 15: - WRITE_CSR(pmpaddr15, addr); + WRITE_CSR(CSR_PMPADDR15, addr); break; default: @@ -513,27 +513,27 @@ int riscv_config_pmp_region(uintptr_t region, uintptr_t attr, switch (region) { case 0 ... 3: - cfg = READ_CSR(pmpcfg0); + cfg = READ_CSR(CSR_PMPCFG0); PMP_MASK_SET_ONE_REGION(region, attr, cfg); - WRITE_CSR(pmpcfg0, cfg); + WRITE_CSR(CSR_PMPCFG0, cfg); break; case 4 ... 7: - cfg = READ_CSR(pmpcfg1); + cfg = READ_CSR(CSR_PMPCFG1); PMP_MASK_SET_ONE_REGION(region, attr, cfg); - WRITE_CSR(pmpcfg1, cfg); + WRITE_CSR(CSR_PMPCFG1, cfg); break; case 8 ... 11: - cfg = READ_CSR(pmpcfg2); + cfg = READ_CSR(CSR_PMPCFG2); PMP_MASK_SET_ONE_REGION(region, attr, cfg); - WRITE_CSR(pmpcfg2, cfg); + WRITE_CSR(CSR_PMPCFG2, cfg); break; case 12 ... 15: - cfg = READ_CSR(pmpcfg3); + cfg = READ_CSR(CSR_PMPCFG3); PMP_MASK_SET_ONE_REGION(region, attr, cfg); - WRITE_CSR(pmpcfg3, cfg); + WRITE_CSR(CSR_PMPCFG3, cfg); break; default: @@ -543,15 +543,15 @@ int riscv_config_pmp_region(uintptr_t region, uintptr_t attr, switch (region) { case 0 ... 7: - cfg = READ_CSR(pmpcfg0); + cfg = READ_CSR(CSR_PMPCFG0); PMP_MASK_SET_ONE_REGION(region, attr, cfg); - WRITE_CSR(pmpcfg0, cfg); + WRITE_CSR(CSR_PMPCFG0, cfg); break; case 8 ... 15: - cfg = READ_CSR(pmpcfg2); + cfg = READ_CSR(CSR_PMPCFG2); PMP_MASK_SET_ONE_REGION(region, attr, cfg); - WRITE_CSR(pmpcfg2, cfg); + WRITE_CSR(CSR_PMPCFG2, cfg); break; default: diff --git a/arch/risc-v/src/common/riscv_releasestack.c b/arch/risc-v/src/common/riscv_releasestack.c index 72c22f5b36c42..884b52c723834 100644 --- a/arch/risc-v/src/common/riscv_releasestack.c +++ b/arch/risc-v/src/common/riscv_releasestack.c @@ -103,4 +103,13 @@ void up_release_stack(struct tcb_s *dtcb, uint8_t ttype) dtcb->stack_alloc_ptr = NULL; dtcb->stack_base_ptr = NULL; dtcb->adj_stack_size = 0; + + /* Release vector register context */ + +#if defined(CONFIG_ARCH_RV_ISA_V) && (CONFIG_ARCH_RV_VECTOR_BYTE_LENGTH == 0) + if (dtcb->xcp.vregs != NULL) + { + kmm_free(dtcb->xcp.vregs); + } +#endif } diff --git a/arch/risc-v/src/common/riscv_testset.S b/arch/risc-v/src/common/riscv_testset.S index bcbad08002e14..34ad27a23ec1f 100644 --- a/arch/risc-v/src/common/riscv_testset.S +++ b/arch/risc-v/src/common/riscv_testset.S @@ -32,11 +32,9 @@ ****************************************************************************/ #ifdef CONFIG_ARCH_RV32 -#define LR_INST lr.w -#define SC_INST sc.w +#define AMOSWAP amoswap.w #else -#define LR_INST lr.d -#define SC_INST sc.d +#define AMOSWAP amoswap.d #endif /**************************************************************************** @@ -86,18 +84,9 @@ up_testset: - li a1, SP_LOCKED - - /* Test if the spinlock is locked or not */ - -retry: - LR_INST a2, (a0) /* Test if spinlock is locked or not */ - beq a2, a1, locked /* Already locked? Go to locked: */ - - /* Not locked ... attempt to lock it */ - - SC_INST a2, a1, (a0) /* Attempt to set the locked state (a1) to (a0) */ - bnez a2, retry /* a2 will not be zero, if sc.b failed, try again */ + li a1, SP_LOCKED + AMOSWAP a2, a1, (a0) /* Attempt to acquire spinlock atomically */ + beq a2, a1, locked /* Already locked? Go to locked: */ /* Lock acquired -- return SP_UNLOCKED */ diff --git a/arch/risc-v/src/common/riscv_vpu.S b/arch/risc-v/src/common/riscv_vpu.S new file mode 100644 index 0000000000000..a2ae7638125c6 --- /dev/null +++ b/arch/risc-v/src/common/riscv_vpu.S @@ -0,0 +1,156 @@ +/**************************************************************************** + * arch/risc-v/src/common/riscv_vpu.S + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "riscv_macros.S" + +#ifdef CONFIG_ARCH_RV_ISA_V + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + .globl riscv_vpuconfig + .globl riscv_savevpu + .globl riscv_restorevpu + .file "riscv_vpu.S" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: riscv_vpuconfig + * + * Description: + * init vpu + * + * C Function Prototype: + * void riscv_vpuconfig(void); + * + * Input Parameters: + * None + * + * Returned Value: + * This function does not return anything explicitly. + * + ****************************************************************************/ + + .type riscv_vpuconfig, function + +riscv_vpuconfig: + li a0, MSTATUS_VS_INIT + csrs CSR_STATUS, a0 + + fence.i + ret + +/**************************************************************************** + * Name: riscv_savevpu + * + * Description: + * Given the pointer to a register save area (in A1), save the state of the + * vector point registers. + * + * C Function Prototype: + * void riscv_savevpu(uintptr_t *regs, uintptr_t *fregs); + * + * Input Parameters: + * regs - A pointer to the integer registers that contain the status + * fregs - A pointer to the register save area in which to save the + * vector point registers + * + * Returned Value: + * None + * + ****************************************************************************/ + + .type riscv_savevpu, function + +riscv_savevpu: + + REGLOAD t0, REG_INT_CTX(a0) + li t1, MSTATUS_VS + and t2, t0, t1 + li t1, MSTATUS_VS_DIRTY +#ifdef CONFIG_ARCH_LAZYVPU + bne t2, t1, 1f +#else + blt t2, t1, 1f +#endif + li t1, ~MSTATUS_VS + and t0, t0, t1 + li t1, MSTATUS_VS_CLEAN + or t0, t0, t1 + REGSTORE t0, REG_INT_CTX(a0) + + riscv_savevpu a1 + +1: + ret + +/**************************************************************************** + * Name: riscv_restorevpu + * + * Description: + * Given the pointer to a register save area (in A1), restore the state of + * the vector point registers. + * + * C Function Prototype: + * void riscv_restorevpu(uintptr_t *regs, uintptr_t *fregs); + * + * Input Parameters: + * regs - A pointer to the integer registers that contain the status + * fregs - A pointer to the register save area containing the vector + * point registers. + * + * Returned Value: + * This function does not return anything explicitly. However, it is + * called from interrupt level assembly logic that assumes that r0 is + * preserved. + * + ****************************************************************************/ + + .type riscv_restorevpu, function + +riscv_restorevpu: + + REGLOAD t0, REG_INT_CTX(a0) + li t1, MSTATUS_VS + and t2, t0, t1 + li t1, MSTATUS_VS_INIT + ble t2, t1, 1f + + riscv_loadvpu a1 + +1: + ret + +#endif /* CONFIG_ARCH_RV_ISA_V */ diff --git a/arch/risc-v/src/common/supervisor/CMakeLists.txt b/arch/risc-v/src/common/supervisor/CMakeLists.txt new file mode 100644 index 0000000000000..7ae71b030ede7 --- /dev/null +++ b/arch/risc-v/src/common/supervisor/CMakeLists.txt @@ -0,0 +1,29 @@ +# ############################################################################## +# arch/risc-v/src/common/supervisor/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +if(CONFIG_BUILD_KERNEL) + + set(SRCS) + + list(APPEND SRCS riscv_syscall.S riscv_perform_syscall.c riscv_sbi.c) + + target_sources(arch PRIVATE ${SRCS}) + +endif() diff --git a/arch/risc-v/src/common/supervisor/Make.defs b/arch/risc-v/src/common/supervisor/Make.defs index 11c80358e2c90..65375a3f0979a 100644 --- a/arch/risc-v/src/common/supervisor/Make.defs +++ b/arch/risc-v/src/common/supervisor/Make.defs @@ -22,7 +22,7 @@ CMN_ASRCS += riscv_syscall.S CMN_CSRCS += riscv_perform_syscall.c -CMN_CSRCS += riscv_percpu.c riscv_sbi.c +CMN_CSRCS += riscv_sbi.c INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)common$(DELIM)supervisor VPATH += common$(DELIM)supervisor diff --git a/arch/risc-v/src/common/supervisor/riscv_perform_syscall.c b/arch/risc-v/src/common/supervisor/riscv_perform_syscall.c index 88d8be77ee2e3..d1bf8503b4c0e 100644 --- a/arch/risc-v/src/common/supervisor/riscv_perform_syscall.c +++ b/arch/risc-v/src/common/supervisor/riscv_perform_syscall.c @@ -28,6 +28,7 @@ #include +#include "sched/sched.h" #include "riscv_internal.h" /**************************************************************************** @@ -59,6 +60,12 @@ void *riscv_perform_syscall(uintptr_t *regs) if (regs != CURRENT_REGS) { + /* Record the new "running" task. g_running_tasks[] is only used by + * assertion logic for reporting crashes. + */ + + g_running_tasks[this_cpu()] = this_task(); + /* Restore the cpu lock */ restore_critical_section(); diff --git a/arch/risc-v/src/common/supervisor/riscv_sbi.c b/arch/risc-v/src/common/supervisor/riscv_sbi.c index 743b8012b32ea..865a4a6f9c8d1 100644 --- a/arch/risc-v/src/common/supervisor/riscv_sbi.c +++ b/arch/risc-v/src/common/supervisor/riscv_sbi.c @@ -22,14 +22,6 @@ * Pre-processor Definitions ****************************************************************************/ -/* SBI Extension IDs */ - -#define SBI_EXT_TIME 0x54494D45 - -/* SBI function IDs for TIME extension */ - -#define SBI_EXT_TIME_SET_TIMER 0x0 - /**************************************************************************** * Included Files ****************************************************************************/ @@ -49,7 +41,6 @@ * Private Functions ****************************************************************************/ -#ifndef CONFIG_NUTTSBI static inline uintptr_t sbi_ecall(unsigned int extid, unsigned int fid, uintptr_t parm0, uintptr_t parm1, uintptr_t parm2, uintptr_t parm3, @@ -74,7 +65,6 @@ static inline uintptr_t sbi_ecall(unsigned int extid, unsigned int fid, return r1; } -#endif /* CONFIG_NUTTSBI */ /**************************************************************************** * Public Functions @@ -93,9 +83,6 @@ static inline uintptr_t sbi_ecall(unsigned int extid, unsigned int fid, void riscv_sbi_set_timer(uint64_t stime_value) { -#ifdef CONFIG_NUTTSBI - sbi_mcall_set_timer(stime_value); -#else #ifdef CONFIG_ARCH_RV64 sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, 0, 0, 0, 0, 0); @@ -103,7 +90,6 @@ void riscv_sbi_set_timer(uint64_t stime_value) sbi_ecall(SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, stime_value, stime_value >> 32, 0, 0, 0, 0); #endif -#endif } /**************************************************************************** @@ -120,22 +106,42 @@ void riscv_sbi_set_timer(uint64_t stime_value) uint64_t riscv_sbi_get_time(void) { #ifdef CONFIG_NUTTSBI - return sbi_mcall_get_time(); -#else -#ifdef CONFIG_ARCH_RV64 - return READ_CSR(time); + return sbi_ecall(SBI_EXT_FIRMWARE, SBI_EXT_FIRMWARE_GET_MTIME, 0, 0, + 0, 0, 0, 0); +#elif defined(CONFIG_ARCH_RV64) + return READ_CSR(CSR_TIME); #else uint32_t hi; uint32_t lo; do { - hi = READ_CSR(timeh); - lo = READ_CSR(time); + hi = READ_CSR(CSR_TIMEH); + lo = READ_CSR(CSR_TIME); } - while (hi != READ_CSR(timeh)); + while (hi != READ_CSR(CSR_TIMEH)); return (((uint64_t) hi) << 32) | lo; #endif -#endif } + +uintptr_t riscv_sbi_send_ipi(uint32_t hmask, uintptr_t hbase) +{ + return sbi_ecall(SBI_EXT_IPI, SBI_EXT_IPI_SEND_IPI, + hmask, hbase, 0, 0, 0, 0); +} + +#ifndef CONFIG_NUTTSBI +uintptr_t riscv_sbi_system_reset(uint32_t type, uint32_t reason) +{ + return sbi_ecall(SBI_EXT_SRST, SBI_EXT_SRST_SYS_RESET, + type, reason, 0, 0, 0, 0); +} + +uintptr_t riscv_sbi_boot_secondary(uint32_t hartid, uintptr_t addr, + uintptr_t a1) +{ + return sbi_ecall(SBI_EXT_HSM, SBI_EXT_HSM_HART_START, + hartid, addr, a1, 0, 0, 0); +} +#endif /* CONFIG_NUTTSBI */ diff --git a/arch/risc-v/src/esp32c3-legacy/.gitignore b/arch/risc-v/src/esp32c3-legacy/.gitignore new file mode 100644 index 0000000000000..9adccd80ae6d7 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/.gitignore @@ -0,0 +1,3 @@ +/esp-wireless-drivers-3rdparty +/esp-nuttx-bootloader +/*.zip diff --git a/arch/risc-v/src/esp32c3-legacy/Bootloader.mk b/arch/risc-v/src/esp32c3-legacy/Bootloader.mk new file mode 100644 index 0000000000000..ac636e610d667 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/Bootloader.mk @@ -0,0 +1,203 @@ +############################################################################ +# arch/risc-v/src/esp32c3-legacy/Bootloader.mk +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +ifeq ($(CONFIG_ESP32C3_BOOTLOADER_BUILD_FROM_SOURCE),y) + +TOOLSDIR = $(TOPDIR)/tools/espressif +CHIPDIR = $(TOPDIR)/arch/risc-v/src/chip +HALDIR = $(CHIPDIR)/esp-hal-3rdparty + +BOOTLOADER_DIR = $(CHIPDIR)/bootloader +BOOTLOADER_SRCDIR = $(BOOTLOADER_DIR)/esp-nuttx-bootloader +BOOTLOADER_VERSION = main +BOOTLOADER_URL = https://github.com/espressif/esp-nuttx-bootloader +BOOTLOADER_OUTDIR = out +BOOTLOADER_CONFIG = $(BOOTLOADER_DIR)/bootloader.conf + +MCUBOOT_SRCDIR = $(BOOTLOADER_DIR)/mcuboot +MCUBOOT_ESPDIR = $(MCUBOOT_SRCDIR)/boot/espressif +MCUBOOT_URL = https://github.com/mcu-tools/mcuboot + +# Helpers for creating the configuration file + +cfg_en = echo "$(1)=$(if $(CONFIG_ESP32C3_APP_FORMAT_MCUBOOT),1,y)"; +cfg_dis = echo "$(1)=$(if $(CONFIG_ESP32C3_APP_FORMAT_MCUBOOT),0,n)"; +cfg_val = echo "$(1)=$(2)"; + +# Commands for colored and formatted output + +RED = \033[1;31m +YELLOW = \033[1;33m +BOLD = \033[1m +RST = \033[0m + +$(BOOTLOADER_CONFIG): $(TOPDIR)/.config +ifeq ($(CONFIG_ESP32C3_SECURE_BOOT),y) + $(Q) if [ -z "$(ESPSEC_KEYDIR)" ]; then \ + echo ""; \ + echo "$(RED)bootloader error:$(RST) Missing argument for secure boot keys directory."; \ + echo "USAGE: make bootloader ESPSEC_KEYDIR="; \ + echo ""; \ + exit 1; \ + fi +endif + $(Q) echo "Creating Bootloader configuration" + $(Q) { \ + $(if $(CONFIG_ESP32C3_FLASH_2M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_2MB)) \ + $(if $(CONFIG_ESP32C3_FLASH_4M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_4MB)) \ + $(if $(CONFIG_ESP32C3_FLASH_8M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_8MB)) \ + $(if $(CONFIG_ESP32C3_FLASH_16M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_16MB)) \ + $(if $(CONFIG_ESP32C3_FLASH_MODE_DIO),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_DIO)) \ + $(if $(CONFIG_ESP32C3_FLASH_MODE_DOUT),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_DOUT)) \ + $(if $(CONFIG_ESP32C3_FLASH_MODE_QIO),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_QIO)) \ + $(if $(CONFIG_ESP32C3_FLASH_MODE_QOUT),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_QOUT)) \ + $(if $(CONFIG_ESP32C3_FLASH_FREQ_80M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_80M)) \ + $(if $(CONFIG_ESP32C3_FLASH_FREQ_40M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_40M)) \ + $(if $(CONFIG_ESP32C3_FLASH_FREQ_26M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_26M)) \ + $(if $(CONFIG_ESP32C3_FLASH_FREQ_20M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_20M)) \ + } > $(BOOTLOADER_CONFIG) +ifeq ($(CONFIG_ESP32C3_APP_FORMAT_MCUBOOT),y) + $(Q) { \ + $(if $(CONFIG_ESP32C3_SECURE_BOOT),$(call cfg_en,CONFIG_SECURE_BOOT)$(call cfg_en,CONFIG_SECURE_BOOT_V2_ENABLED)$(call cfg_val,CONFIG_ESP_SIGN_KEY_FILE,$(abspath $(TOPDIR)/$(ESPSEC_KEYDIR)/$(subst ",,$(CONFIG_ESP32C3_SECURE_BOOT_APP_SIGNING_KEY))))) \ + $(if $(CONFIG_ESP32C3_SECURE_SIGNED_APPS_SCHEME_RSA_2048),$(call cfg_en,CONFIG_ESP_USE_MBEDTLS)$(call cfg_en,CONFIG_ESP_SIGN_RSA)$(call cfg_val,CONFIG_ESP_SIGN_RSA_LEN,2048)) \ + $(if $(CONFIG_ESP32C3_SECURE_SIGNED_APPS_SCHEME_RSA_3072),$(call cfg_en,CONFIG_ESP_USE_MBEDTLS)$(call cfg_en,CONFIG_ESP_SIGN_RSA)$(call cfg_val,CONFIG_ESP_SIGN_RSA_LEN,3072)) \ + $(if $(CONFIG_ESP32C3_SECURE_SIGNED_APPS_SCHEME_ECDSA_P256),$(call cfg_en,CONFIG_ESP_USE_TINYCRYPT)$(call cfg_en,CONFIG_ESP_SIGN_EC256)) \ + $(if $(CONFIG_ESP32C3_SECURE_SIGNED_APPS_SCHEME_ED25519),$(call cfg_en,CONFIG_ESP_USE_TINYCRYPT)$(call cfg_en,CONFIG_ESP_SIGN_ED25519)) \ + $(if $(CONFIG_ESP32C3_SECURE_BOOT_ALLOW_JTAG),$(call cfg_en,CONFIG_SECURE_BOOT_ALLOW_JTAG)) \ + $(if $(CONFIG_ESP32C3_SECURE_BOOT_ALLOW_EFUSE_RD_DIS),$(call cfg_en,CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS)) \ + $(if $(CONFIG_ESP32C3_SECURE_DISABLE_ROM_DL_MODE),$(call cfg_en,CONFIG_SECURE_DISABLE_ROM_DL_MODE)) \ + $(if $(CONFIG_ESP32C3_SECURE_ENABLE_SECURE_ROM_DL_MODE),$(call cfg_en,CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE)) \ + $(if $(CONFIG_ESP32C3_SECURE_INSECURE_ALLOW_DL_MODE),$(call cfg_en,CONFIG_SECURE_INSECURE_ALLOW_DL_MODE)) \ + $(if $(CONFIG_ESP32C3_SECURE_FLASH_ENC_ENABLED),$(call cfg_en,CONFIG_SECURE_FLASH_ENC_ENABLED)) \ + $(if $(CONFIG_ESP32C3_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT),$(call cfg_en,CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT)) \ + $(if $(CONFIG_ESP32C3_SECURE_FLASH_ENCRYPTION_MODE_RELEASE),$(call cfg_en,CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE)) \ + $(if $(CONFIG_ESP32C3_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC),$(call cfg_en,CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC)) \ + $(if $(CONFIG_ESP32C3_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE),$(call cfg_en,CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE)) \ + $(if $(CONFIG_ESP32C3_SECURE_FLASH_REQUIRE_ALREADY_ENABLED),$(call cfg_en,CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED)) \ + $(call cfg_val,CONFIG_ESP_BOOTLOADER_OFFSET,0x1000) \ + $(call cfg_val,CONFIG_ESP_BOOTLOADER_SIZE,0xF000) \ + $(call cfg_val,CONFIG_ESP_IMAGE0_PRIMARY_START_ADDRESS,$(CONFIG_ESP32C3_OTA_PRIMARY_SLOT_OFFSET)) \ + $(call cfg_val,CONFIG_ESP_APPLICATION_SIZE,$(CONFIG_ESP32C3_OTA_SLOT_SIZE)) \ + $(call cfg_val,CONFIG_ESP_IMAGE0_SECONDARY_START_ADDRESS,$(CONFIG_ESP32C3_OTA_SECONDARY_SLOT_OFFSET)) \ + $(call cfg_en,CONFIG_ESP_MCUBOOT_WDT_ENABLE) \ + $(call cfg_val,CONFIG_ESP_SCRATCH_OFFSET,$(CONFIG_ESP32C3_OTA_SCRATCH_OFFSET)) \ + $(call cfg_val,CONFIG_ESP_SCRATCH_SIZE,$(CONFIG_ESP32C3_OTA_SCRATCH_SIZE)) \ + $(call cfg_en,CONFIG_ESP_CONSOLE_UART) \ + $(if $(CONFIG_UART0_SERIAL_CONSOLE),$(call cfg_val,CONFIG_ESP_CONSOLE_UART_NUM,0)) \ + $(if $(CONFIG_UART1_SERIAL_CONSOLE),$(call cfg_val,CONFIG_ESP_CONSOLE_UART_NUM,1)) \ + } >> $(BOOTLOADER_CONFIG) +else ifeq ($(CONFIG_ESP32C3_APP_FORMAT_LEGACY),y) + $(Q) { \ + $(call cfg_dis,CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE) \ + $(call cfg_en,CONFIG_PARTITION_TABLE_CUSTOM) \ + $(call cfg_val,CONFIG_PARTITION_TABLE_CUSTOM_FILENAME,\"partitions.csv\") \ + $(call cfg_val,CONFIG_PARTITION_TABLE_OFFSET,$(CONFIG_ESP32C3_PARTITION_TABLE_OFFSET)) \ + } >> $(BOOTLOADER_CONFIG) +endif + +ifeq ($(CONFIG_ESP32C3_APP_FORMAT_MCUBOOT),y) + +BOOTLOADER_BIN = $(TOPDIR)/mcuboot-esp32c3.bin +BOOTLOADER_SIGNED_BIN = $(TOPDIR)/mcuboot-esp32c3.signed.bin + +$(MCUBOOT_SRCDIR): + $(Q) echo "Cloning MCUboot" + $(Q) git clone --quiet $(MCUBOOT_URL) $(MCUBOOT_SRCDIR) + $(Q) git -C "$(MCUBOOT_SRCDIR)" checkout --quiet $(CONFIG_ESP32C3_MCUBOOT_VERSION) + $(Q) git -C "$(MCUBOOT_SRCDIR)" submodule --quiet update --init --recursive ext/mbedtls + +$(BOOTLOADER_BIN): chip/$(ESP_HAL_3RDPARTY_REPO) $(MCUBOOT_SRCDIR) $(BOOTLOADER_CONFIG) + $(Q) echo "Building Bootloader" + $(Q) $(TOOLSDIR)/build_mcuboot.sh \ + -c esp32c3 \ + -f $(BOOTLOADER_CONFIG) \ + -p $(BOOTLOADER_DIR) \ + -e $(HALDIR) + $(call COPYFILE, $(BOOTLOADER_DIR)/$(BOOTLOADER_OUTDIR)/mcuboot-esp32c3.bin, $(TOPDIR)) + +bootloader: $(BOOTLOADER_BIN) +ifeq ($(CONFIG_ESP32C3_SECURE_BOOT),y) + $(eval KEYDIR := $(TOPDIR)/$(ESPSEC_KEYDIR)) + $(eval BOOTLOADER_SIGN_KEY := $(abspath $(KEYDIR)/$(subst ",,$(CONFIG_ESP32C3_SECURE_BOOT_BOOTLOADER_SIGNING_KEY)))) +ifeq ($(CONFIG_ESP32C3_SECURE_BOOT_BUILD_SIGNED_BINARIES),y) + $(Q) if [ ! -f "$(BOOTLOADER_SIGN_KEY)" ]; then \ + echo ""; \ + echo "$(RED)bootloader error:$(RST) Bootloader signing key $(BOLD)$(CONFIG_ESP32C3_SECURE_BOOT_BOOTLOADER_SIGNING_KEY)$(RST) does not exist."; \ + echo "Generate using:"; \ + echo " espsecure.py generate_signing_key --version 2 $(CONFIG_ESP32C3_SECURE_BOOT_BOOTLOADER_SIGNING_KEY)"; \ + echo ""; \ + exit 1; \ + fi + $(Q) echo "Signing Bootloader" + espsecure.py sign_data --version 2 --keyfile $(BOOTLOADER_SIGN_KEY) -o $(BOOTLOADER_SIGNED_BIN) $(BOOTLOADER_BIN) +else + $(Q) echo "" + $(Q) echo "$(YELLOW)Bootloader not signed. Sign the bootloader before flashing.$(RST)" + $(Q) echo "To sign the bootloader, you can use this command:" + $(Q) echo " espsecure.py sign_data --version 2 --keyfile $(BOOTLOADER_SIGN_KEY) -o mcuboot-esp32c3.signed.bin mcuboot-esp32c3.bin" + $(Q) echo "" +endif +endif + +clean_bootloader: + $(call DELDIR,$(MCUBOOT_SRCDIR)) + $(call DELDIR,$(BOOTLOADER_DIR)/$(BOOTLOADER_OUTDIR)) + $(call DELFILE,$(BOOTLOADER_CONFIG)) + $(call DELFILE,$(BOOTLOADER_BIN)) + $(if $(CONFIG_ESP32C3_SECURE_BOOT_BUILD_SIGNED_BINARIES),$(call DELFILE,$(BOOTLOADER_SIGNED_BIN))) + +else ifeq ($(CONFIG_ESP32C3_APP_FORMAT_LEGACY),y) + +$(BOOTLOADER_SRCDIR): + $(Q) git clone $(BOOTLOADER_URL) $(BOOTLOADER_SRCDIR) -b $(BOOTLOADER_VERSION) + $(Q) git -C $(BOOTLOADER_SRCDIR) submodule update --init esp-idf + +bootloader: $(BOOTLOADER_SRCDIR) $(BOOTLOADER_CONFIG) + $(Q) echo "Building Bootloader binaries" + $(Q) $(BOOTLOADER_SRCDIR)/build_idfboot.sh -c esp32c3 -s -f $(BOOTLOADER_CONFIG) + $(call COPYFILE,$(BOOTLOADER_SRCDIR)/$(BOOTLOADER_OUTDIR)/bootloader-esp32c3.bin,$(TOPDIR)) + $(call COPYFILE,$(BOOTLOADER_SRCDIR)/$(BOOTLOADER_OUTDIR)/partition-table-esp32c3.bin,$(TOPDIR)) + +clean_bootloader: + $(call DELDIR,$(BOOTLOADER_SRCDIR)) + $(call DELFILE,$(BOOTLOADER_CONFIG)) + $(call DELFILE,$(TOPDIR)/bootloader-esp32c3.bin) + $(call DELFILE,$(TOPDIR)/partition-table-esp32c3.bin) + +endif + +else ifeq ($(CONFIG_ESP32C3_BOOTLOADER_DOWNLOAD_PREBUILT),y) + +BOOTLOADER_VERSION = latest +BOOTLOADER_URL = https://github.com/espressif/esp-nuttx-bootloader/releases/download/$(BOOTLOADER_VERSION) + +ifeq ($(CONFIG_ESP32C3_APP_FORMAT_LEGACY),y) + +bootloader: + $(call DOWNLOAD,$(BOOTLOADER_URL),bootloader-esp32c3.bin,$(TOPDIR)/bootloader-esp32c3.bin) + $(call DOWNLOAD,$(BOOTLOADER_URL),partition-table-esp32c3.bin,$(TOPDIR)/partition-table-esp32c3.bin) + +clean_bootloader: + $(call DELFILE,$(TOPDIR)/bootloader-esp32c3.bin) + $(call DELFILE,$(TOPDIR)/partition-table-esp32c3.bin) + +endif + +endif diff --git a/arch/risc-v/src/esp32c3-legacy/Kconfig b/arch/risc-v/src/esp32c3-legacy/Kconfig new file mode 100644 index 0000000000000..99d3140341e59 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/Kconfig @@ -0,0 +1,1221 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_ESP32C3 + +comment "ESP32-C3 Configuration Options" + +choice + prompt "ESP32-C3 Chip Selection" + default ARCH_CHIP_ESP32C3WROOM02 + +config ARCH_CHIP_ESP32C3X + bool "ESP32-C3" + select ESP32C3_ESP32C3XXX + ---help--- + ESP32-C3 chip with a single RISC-V IMC core, no embedded Flash memory + +config ARCH_CHIP_ESP32C3FX4 + bool "ESP32-C3Fx4" + select ESP32C3_ESP32C3XXX + select ESP32C3_FLASH_4M + ---help--- + ESP32-C3 chip with a single RISC-V IMC core, 4 MB of in-package Flash memory + +config ARCH_CHIP_ESP32C3MINI1 + bool "ESP32-C3-MINI-1" + select ESP32C3_ESP32C3XXX + select ESP32C3_FLASH_4M + ---help--- + Generic module with an embedded ESP32-C3Fx4 chip + +config ARCH_CHIP_ESP32C3WROOM02 + bool "ESP32-C3-WROOM-02" + select ESP32C3_ESP32C3XXX + select ESP32C3_FLASH_4M + ---help--- + Generic module with an embedded ESP32-C3 chip, 4 MB of Flash memory + +endchoice # ESP32-C3 Chip Selection + +config ESP32C3_SINGLE_CPU + bool + default n + +config ESP32C3_DUAL_CPU + bool + default n + +config ESP32C3_ESP32C3XXX + bool + default n + select ESP32C3_SINGLE_CPU + select ARCH_HAVE_I2CRESET + +config ESP32C3_FLASH_2M + bool + default n + +config ESP32C3_FLASH_4M + bool + default n + +config ESP32C3_FLASH_8M + bool + default n + +config ESP32C3_FLASH_16M + bool + default n + +config ESP32C3_ESPTOOLPY_NO_STUB + bool "Disable download stub" + default n + ---help--- + The flasher tool sends a precompiled download stub first by default. + That stub allows things like compressed downloads and more. + Usually you should not need to disable that feature. + It is only required to be disabled in certain scenarios when either + Secure Boot V2 or Flash Encryption is enabled. + +config ESP32C3_FLASH_DETECT + bool "Auto-detect FLASH size" + default n + ---help--- + Auto detect flash size when flashing. + +choice ESP32C3_CPU_FREQ + prompt "CPU frequency" + default ESP32C3_CPU_FREQ_160 + ---help--- + CPU frequency to be set on application startup. + +config ESP32C3_CPU_FREQ_40 + bool "40 MHz" + ---help--- + Set the CPU to 40 MHz. This frequency is obtained from the XTAL. + +config ESP32C3_CPU_FREQ_80 + bool "80 MHz" + ---help--- + Set the CPU to 80 MHz. This frequency is obtained from the 480 MHz PLL. + +config ESP32C3_CPU_FREQ_160 + bool "160 MHz" + ---help--- + Set the CPU to 160 MHz. This frequency is obtained from the 480 MHz PLL. + +endchoice # ESP32C3_CPU_FREQ + +config ESP32C3_CPU_FREQ_MHZ + int + default 40 if ESP32C3_CPU_FREQ_40 + default 80 if ESP32C3_CPU_FREQ_80 + default 160 if ESP32C3_CPU_FREQ_160 + +config ESP32C3_REGION_PROTECTION + bool "Enable region protection" + default y + select ARCH_USE_MPU + ---help--- + Configure the MPU to disable access to invalid memory regions. + +config ESP32C3_RT_TIMER + bool "Real-time Timer" + default n + select ESP32C3_TIMER + ---help--- + Real-time Timer is relying upon the Systimer 1. + +config ESP32C3_RTC_HEAP + bool "Use the RTC memory as a separate heap" + select ARCH_HAVE_EXTRA_HEAPS + default n + +config ESP32C3_EXCEPTION_ENABLE_CACHE + bool + default y + depends on ESP32C3_SPIFLASH + ---help--- + When exception triggers, panic function enables SPI Flash cache to + let functions be able to call functions which locate in SPI Flash. + +menu "ESP32-C3 Peripheral Support" + +config ESP32C3_ADC + bool + default n + select ANALOG + select ADC + +config ESP32C3_UART + bool + default n + +config ESP32C3_I2C + bool + default n + +config ESP32C3_TWAI + bool + default n + select CAN + +config ESP32C3_TIMER + bool + default n + +config ESP32C3_WDT + bool + default n + +config ESP32C3_EFUSE + bool "EFUSE support" + default n + ---help--- + Enable ESP32-C3 efuse support. + +config ESP32C3_SPI + bool + default n + +config ESP32C3_LEDC + bool "LEDC (PWM)" + default n + select PWM + select ARCH_HAVE_PWM_MULTICHAN + +config ESP32C3_GPIO_IRQ + bool "GPIO pin interrupts" + default n + ---help--- + Enable support for interrupting GPIO pins + +config ESP32C3_RTCIO_IRQ + bool "RTC IO interrupts" + default n + ---help--- + Enable support for RTC peripherals interrupts. + +config ESP32C3_UART0 + bool "UART0" + default y + select ESP32C3_UART + select UART0_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config ESP32C3_UART1 + bool "UART1" + default n + select ESP32C3_UART + select UART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config ESP32C3_USBSERIAL + bool "USB-Serial Driver" + default n + select OTHER_UART_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config ESP32C3_I2C0 + bool "I2C 0" + default n + select ESP32C3_I2C + +config ESP32C3_TWAI0 + bool "TWAI (CAN) 0" + default n + select ESP32C3_TWAI + +config ESP32C3_RNG + bool "Random Number Generator (RNG)" + default n + select ARCH_HAVE_RNG + ---help--- + ESP32-C3 supports an RNG that passed on Dieharder test suite. + +config ESP32C3_TIMER0 + bool "54-bit Timer 0 (Group 0 Timer 0)" + default n + select ESP32C3_TIMER + ---help--- + Enables Timer 0 + +config ESP32C3_TIMER1 + bool "54-bit Timer 0 (Group 1 Timer 0)" + default n + select ESP32C3_TIMER + ---help--- + Enables Timer 1 + +config ESP32C3_SPIFLASH + bool "SPI Flash" + default n + +config ESP32C3_SPI2 + bool "SPI 2" + default n + select ESP32C3_SPI + select SPI + +config ESP32C3_DMA + bool "General DMA (GDMA)" + default n + select ARCH_DMA + +config ESP32C3_MWDT0 + bool "Main System Watchdog Timer (Group 0)" + default n + select ESP32C3_WDT + ---help--- + Includes MWDT0. This watchdog timer is part of the Group 0 + timer submodule. + +config ESP32C3_MWDT1 + bool "Main System Watchdog Timer (Group 1)" + default n + select ESP32C3_WDT + ---help--- + Includes MWDT1. This watchdog timer is part of the Group 0 + timer submodule. + +config ESP32C3_RWDT + bool "RTC Watchdog Timer" + default n + select ESP32C3_WDT + select ESP32C3_RTCIO_IRQ + ---help--- + Includes RWDT. This watchdog timer is from the RTC module. + When it is selected, if the developer sets it to reset on expiration + it will reset Main System and the RTC module. If you don't want + to have the RTC module reset, please, use the Timers' Module WDTs. + They will only reset Main System. + +config ESP32C3_ADC1 + bool "ADC1" + default n + select ESP32C3_ADC + +config ESP32C3_WIRELESS + bool + default n + select NET + select ARCH_PHY_INTERRUPT + select ESP32C3_RT_TIMER + ---help--- + Enable Wireless support + +config ESP32C3_AES_ACCELERATOR + bool "AES Accelerator" + default n +config ESP32C3_SHA_ACCELERATOR + bool "SHA Accelerator" + default n + ---help--- + Enable ESP32-C3 SHA accelerator support. + +config ESP32C3_BIGNUM_ACCELERATOR + bool "BIGNUM Accelerator" + default n + ---help--- + Enable ESP32-C3 BIGNUM accelerator support. + +config ESP32C3_RSA_ACCELERATOR + bool "RSA Accelerator" + default n + ---help--- + Enable ESP32-C3 RSA accelerator support. + +config ESP32C3_WIFI + bool "Wi-Fi" + default n + select ESP32C3_WIRELESS + ---help--- + Enable Wi-Fi support + +config ESP32C3_BLE + bool "BLE" + default n + select ESP32C3_WIRELESS + ---help--- + Enable BLE support + +config ESP32C3_BROWNOUT_DET + bool "Brownout Detect" + default y + ---help--- + The ESP32-C3 has a built-in brownout detector which can detect if the voltage is lower than + a specific value. If this happens, it will reset the chip in order to prevent unintended + behaviour. + +endmenu # ESP32-C3 Peripheral Support + +menuconfig ESP32C3_WIFI_BT_COEXIST + bool "Wi-Fi and BT coexist" + default n + depends on ESP32C3_WIFI && ESP32C3_BLE + +menu "I2C Configuration" + depends on ESP32C3_I2C + +if ESP32C3_I2C0 + +config ESP32C3_I2C0_SCLPIN + int "I2C0 SCL Pin" + default 6 + range 0 21 + +config ESP32C3_I2C0_SDAPIN + int "I2C0 SDA Pin" + default 5 + range 0 21 + +endif # ESP32C3_I2C0 + +config ESP32C3_I2CTIMEOSEC + int "Timeout seconds" + default 0 + +config ESP32C3_I2CTIMEOMS + int "Timeout milliseconds" + default 500 + +endmenu # I2C configuration + +menu "TWAI driver options" + depends on ESP32C3_TWAI + +if ESP32C3_TWAI0 + +config ESP32C3_TWAI0_TXPIN + int "TWAI0 TX Pin" + default 2 + +config ESP32C3_TWAI0_RXPIN + int "TWAI0 RX Pin" + default 3 + +config ESP32C3_TWAI0_BITRATE + int "TWAI0 bitrate" + default 1000000 + ---help--- + TWAI0 bit rate. Required if ESP32C3_TWAI0 is defined. + +config ESP32C3_TWAI0_SAMPLEP + int "TWAI0 sample point" + default 80 + ---help--- + TWAI0 sample point location as a percent value. Required + if ESP32C3_TWAI0 is defined. + +config ESP32C3_TWAI0_SJW + int "TWAI0 synchronization jump width" + default 3 + ---help--- + SJW limits the number of Time Quanta corrections during bit + Resynchronization. Default: 3 + +config ESP32C3_TWAI0_SAM + bool "TWAI0 sampling" + default n + ---help--- + The bus is sampled 3 times (recommended for low to medium speed buses + to spikes on the bus-line). + +endif # ESP32C3_TWAI0 + +config ESP32C3_TWAI_REGDEBUG + bool "TWAI register level debug" + depends on DEBUG_CAN_INFO + default n + ---help--- + Output detailed register-level TWAI debug information. Requires also + CONFIG_DEBUG_CAN_INFO. + +endmenu #ESP32C3_TWAI + +menu "SPI configuration" + depends on ESP32C3_SPI + +config ESP32C3_SPI_SWCS + bool "SPI software CS" + default n + ---help--- + Use SPI software CS. + +config ESP32C3_SPI_UDCS + bool "User defined CS" + default n + depends on ESP32C3_SPI_SWCS + ---help--- + Use user-defined CS. + +if ESP32C3_SPI2 + +config ESP32C3_SPI2_SLAVE + bool "SPI2 Slave mode" + default n + depends on SPI_SLAVE + select ESP32C3_GPIO_IRQ + ---help--- + Configure SPI2 to operate in Slave mode. + +config ESP32C3_SPI2_DMA + bool "SPI2 use GDMA" + default n + depends on ESP32C3_DMA + ---help--- + Enable support for transfers using the GDMA engine. + +config ESP32C3_SPI2_DMADESC_NUM + int "SPI2 Master GDMA maximum number of descriptors" + default 2 + depends on ESP32C3_SPI2_DMA + ---help--- + Configure the maximum number of out-link/in-link descriptors to + be chained for a GDMA transfer. + +config ESP32C3_SPI2_DMATHRESHOLD + int "SPI2 Master GDMA threshold" + default 64 + depends on ESP32C3_SPI2_DMA + ---help--- + When SPI GDMA is enabled, GDMA transfers whose size are below the + defined threshold will be performed by polling logic. + +config ESP32C3_SPI2_SLAVE_BUFSIZE + int "SPI2 Slave buffer size" + default 2048 + depends on ESP32C3_SPI2_SLAVE + ---help--- + Configure the size of SPI2 Slave controller's internal buffers. + +config ESP32C3_SPI2_CSPIN + int "SPI2 CS Pin" + default 10 + range 0 21 + +config ESP32C3_SPI2_CLKPIN + int "SPI2 CLK Pin" + default 6 + range 0 21 + +config ESP32C3_SPI2_MOSIPIN + int "SPI2 MOSI Pin" + default 7 + range 0 21 + +config ESP32C3_SPI2_MISOPIN + int "SPI2 MISO Pin" + default 2 + range 0 21 + +endif # ESP32C3_SPI2 + +endmenu # SPI configuration + +menu "iCE40 Configuration" + depends on SPI_ICE40 + +config ESP32C3_ICE40_CSPIN + int "iCE40 CS Pin" + default 6 + range 0 21 + +config ESP32C3_ICE40_CDONEPIN + int "iCE40 CDONE Pin" + default 0 + range 0 21 + +config ESP32C3_ICE40_CRSTPIN + int "iCE40 CRST Pin" + default 1 + range 0 21 + +config ESP32C3_ICE40_SPI_PORT + int "iCE40 SPI port number" + default 2 + range 0 5 + +endmenu + +menu "UART configuration" + depends on ESP32C3_UART + +if ESP32C3_UART0 + +config ESP32C3_UART0_TXPIN + int "UART0 TX Pin" + default 21 + +config ESP32C3_UART0_RXPIN + int "UART0 RX Pin" + default 20 + +config ESP32C3_UART0_RTSPIN + int "UART0 RTS Pin" + depends on SERIAL_IFLOWCONTROL + default 16 + range 0 21 + +config ESP32C3_UART0_CTSPIN + int "UART0 CTS Pin" + depends on SERIAL_OFLOWCONTROL + default 15 + range 0 21 + +endif # ESP32C3_UART0 + +if ESP32C3_UART1 + +config ESP32C3_UART1_TXPIN + int "UART1 TX Pin" + default 8 + +config ESP32C3_UART1_RXPIN + int "UART1 RX Pin" + default 9 + +config ESP32C3_UART1_RTSPIN + int "UART1 RTS Pin" + depends on SERIAL_IFLOWCONTROL + default 1 + range 0 21 + +config ESP32C3_UART1_CTSPIN + int "UART1 CTS Pin" + depends on SERIAL_OFLOWCONTROL + default 2 + range 0 21 + +endif # ESP32C3_UART1 + +endmenu + +menu "Real-Time Timer" + depends on ESP32C3_RT_TIMER + +config ESP32C3_RT_TIMER_TASK_NAME + string "Timer task name" + default "rt_timer" + +config ESP32C3_RT_TIMER_TASK_PRIORITY + int "Timer task priority" + default 223 + ---help--- + Priority level of the RT Timer task. + Must be lower than the SCHED_HPWORKPRIORITY. + +config ESP32C3_RT_TIMER_TASK_STACK_SIZE + int "Timer task stack size" + default 2048 + +endmenu # Real-Time Timer + +if ESP32C3_TIMER +menu "Timer/counter Configuration" + +config ESP32C3_ONESHOT + bool "One-shot wrapper" + default n + ---help--- + Enable a wrapper around the low level timer/counter functions to + support one-shot timer. + +config ESP32C3_FREERUN + bool "TIM free-running wrapper" + default n + ---help--- + Enable a wrapper around the low level timer/counter functions to + support a free-running timer. + +endmenu # Timer/counter Configuration +endif # ESP32C3_TIMER + +menu "LEDC configuration" + depends on ESP32C3_LEDC + +menuconfig ESP32C3_LEDC_TIM0 + bool "Timer 0" + default n + +if ESP32C3_LEDC_TIM0 + +config ESP32C3_LEDC_TIM0_CHANNELS + int "Number of Timer 0 channels" + default 2 + +endif # ESP32C3_LEDC_TIM0 + +menuconfig ESP32C3_LEDC_TIM1 + bool "Timer 1" + default n + +if ESP32C3_LEDC_TIM1 + +config ESP32C3_LEDC_TIM1_CHANNELS + int "Number of Timer 1 channels" + default 2 + +endif # ESP32C3_LEDC_TIM1 + +menuconfig ESP32C3_LEDC_TIM2 + bool "Timer 2" + default n + +if ESP32C3_LEDC_TIM2 + +config ESP32C3_LEDC_TIM2_CHANNELS + int "Number of Timer 2 channels" + default 2 + +endif # ESP32C3_LEDC_TIM2 + +config ESP32C3_LEDC_CHANNEL0_PIN + int "Channel 0 pin" + default 2 + +config ESP32C3_LEDC_CHANNEL1_PIN + int "Channel 1 pin" + default 3 + +config ESP32C3_LEDC_CHANNEL2_PIN + int "Channel 2 pin" + default 4 + +config ESP32C3_LEDC_CHANNEL3_PIN + int "Channel 3 pin" + default 5 + +config ESP32C3_LEDC_CHANNEL4_PIN + int "Channel 4 pin" + default 6 + +config ESP32C3_LEDC_CHANNEL5_PIN + int "Channel 5 pin" + default 7 + +endmenu # LEDC configuration + +menu "ADC Configuration" + depends on ESP32C3_ADC + +if ESP32C3_ADC1 + +choice ESP32C3_ADC_VOL_RANGES + prompt "ADC1 voltage ranges" + default ESP32C3_ADC_VOL_750 + +config ESP32C3_ADC_VOL_750 + bool "0~750mV" + +config ESP32C3_ADC_VOL_1050 + bool "0~1050mV" + +config ESP32C3_ADC_VOL_1300 + bool "0~1300mV" + +config ESP32C3_ADC_VOL_2500 + bool "0~2500mV" + +endchoice + +config ESP32C3_ADC1_CHANNEL0 + bool "ADC1 channel 0" + default n + +config ESP32C3_ADC1_CHANNEL1 + bool "ADC1 channel 1" + default n + +config ESP32C3_ADC1_CHANNEL2 + bool "ADC1 channel 2" + default n + +config ESP32C3_ADC1_CHANNEL3 + bool "ADC1 channel 3" + default n + +config ESP32C3_ADC1_CHANNEL4 + bool "ADC1 channel 4" + default n + +endif # ESP32C3_ADC1 +endmenu # ADC Configuration + +menu "Wi-Fi configuration" + depends on ESP32C3_WIFI + +choice + prompt "ESP32-C3 Wi-Fi mode" + default ESP32C3_WIFI_STATION + +config ESP32C3_WIFI_STATION + bool "Station mode" + +config ESP32C3_WIFI_SOFTAP + bool "SoftAP mode" + +config ESP32C3_WIFI_STATION_SOFTAP + bool "Station + SoftAP" + +endchoice # ESP32-C3 Wi-Fi mode + +config ESP32C3_WIFI_STATIC_RXBUF_NUM + int "Wi-Fi static RX buffer number" + default 10 + +config ESP32C3_WIFI_DYNAMIC_RXBUF_NUM + int "Wi-Fi dynamic RX buffer number" + default 32 + +config ESP32C3_WIFI_DYNAMIC_TXBUF_NUM + int "Wi-Fi dynamic TX buffer number" + default 32 + +config ESP32C3_WIFI_TX_AMPDU + bool "Wi-Fi TX AMPDU" + default y + +config ESP32C3_WIFI_RX_AMPDU + bool "Wi-Fi RX AMPDU" + default y + +config ESP32C3_WIFI_RXBA_AMPDU_WZ + int "Wi-Fi RX BA AMPDU windown size" + default 6 + +config ESP32C3_WIFI_CONNECT_TIMEOUT + int "Connect timeout by second" + default 10 + ---help--- + Max waiting time of connecting to AP. + +config ESP32C3_WIFI_SCAN_RESULT_SIZE + int "Scan result buffer" + default 4096 + ---help--- + Maximum scan result buffer size. + +config ESP32C3_WIFI_STA_DISCONNECT_PM + bool "Power Management for station when disconnected" + default n + ---help--- + Select this option to enable power management for station when disconnected. + Chip will do modem-sleep when RF module is not in use anymore. + +config EXAMPLE_WIFI_LISTEN_INTERVAL + int "Wi-Fi listen interval" + default 3 + ---help--- + Interval for station to listen to beacon from AP. The unit of listen interval is one beacon interval. + For example, if beacon interval is 100 ms and listen interval is 3, the interval for station to listen + to beacon is 300 ms. + +choice EXAMPLE_POWER_SAVE_MODE + prompt "Power save mode" + default EXAMPLE_POWER_SAVE_NONE + ---help--- + Power save mode for the ESP32-C3 to use. Modem sleep mode includes minimum and maximum power save modes. + In minimum power save mode, station wakes up every DTIM to receive beacon. Broadcast data will not be + lost because it is transmitted after DTIM. However, it can not save much more power if DTIM is short + for DTIM is determined by AP. + In maximum power save mode, station wakes up every listen interval to receive beacon. Broadcast data + may be lost because station may be in sleep state at DTIM time. If listen interval is longer, more power + is saved but broadcast data is more easy to lose. + +config EXAMPLE_POWER_SAVE_NONE + bool "none" + +config EXAMPLE_POWER_SAVE_MIN_MODEM + bool "minimum modem" + +config EXAMPLE_POWER_SAVE_MAX_MODEM + bool "maximum modem" + +endchoice + +config ESP32C3_WIFI_RECONNECT + bool "Enable Wi-Fi to reconnect" + default n + ---help--- + Select this option to enable Wi-Fi to reconnect for station when disconnected. + +choice ESP32C3_WIFI_LOG_LEVEL + depends on DEBUG_INFO + prompt "WiFi debug log level" + default WIFI_LOG_LEVEL_INFO + ---help--- + The WiFi log is divided into the following levels: ERROR,WARNING,INFO,DEBUG,VERBOSE. + +config WIFI_LOG_LEVEL_NONE + bool "No output" + +config WIFI_LOG_LEVEL_ERROR + bool "Error" + +config WIFI_LOG_LEVEL_WARN + bool "Warning" + +config WIFI_LOG_LEVEL_INFO + bool "Info" + +config WIFI_LOG_LEVEL_DEBUG + bool "Debug" + +config WIFI_LOG_LEVEL_VERBOSE + bool "Verbose" + +endchoice + +config WIFI_LOG_LEVEL + int + default 0 if WIFI_LOG_LEVEL_NONE + default 1 if WIFI_LOG_LEVEL_ERROR + default 2 if WIFI_LOG_LEVEL_WARN + default 3 if WIFI_LOG_LEVEL_INFO + default 4 if WIFI_LOG_LEVEL_DEBUG + default 5 if WIFI_LOG_LEVEL_VERBOSE + +endmenu # Wi-Fi configuration + +menu "BLE Configuration" + depends on ESP32C3_BLE + +config ESP32C3_BLE_TTY_NAME + string "BLE TTY device name" + default "/dev/ttyHCI0" + depends on UART_BTH4 + +config ESP32C3_BLE_TASK_STACK_SIZE + int "Controller task stack size" + default 4096 + +config ESP32C3_BLE_TASK_PRIORITY + int "Controller task priority" + default 253 + +endmenu # BLE Configuration + +menu "SPI Flash configuration" + +choice ESP32C3_FLASH_MODE + prompt "SPI Flash mode" + default ESP32C3_FLASH_MODE_DIO + ---help--- + These options control how many I/O pins are used for communication with the attached SPI Flash chip. + The option selected here is then used by esptool when flashing. + +config ESP32C3_FLASH_MODE_DIO + bool "Dual IO (DIO)" + +config ESP32C3_FLASH_MODE_DOUT + bool "Dual Output (DOUT)" + +config ESP32C3_FLASH_MODE_QIO + bool "Quad IO (QIO)" + +config ESP32C3_FLASH_MODE_QOUT + bool "Quad Output (QOUT)" + +endchoice # ESP32C3_FLASH_MODE + +choice ESP32C3_FLASH_FREQ + prompt "SPI Flash frequency" + default ESP32C3_FLASH_FREQ_40M + ---help--- + SPI Flash frequency. + +config ESP32C3_FLASH_FREQ_80M + bool "80 MHz" + +config ESP32C3_FLASH_FREQ_40M + bool "40 MHz" + +config ESP32C3_FLASH_FREQ_26M + bool "26 MHz" + +config ESP32C3_FLASH_FREQ_20M + bool "20 MHz" + +endchoice # ESP32C3_FLASH_FREQ + +if ESP32C3_HAVE_OTA_PARTITION + +comment "Application Image OTA Update support" + +config ESP32C3_OTA_PARTITION_ENCRYPT + bool "Encrypt OTA partitions" + default y + depends on ESP32C3_SECURE_FLASH_ENC_ENABLED + +config ESP32C3_OTA_PRIMARY_SLOT_OFFSET + hex "Application image primary slot offset" + default 0x10000 + +config ESP32C3_OTA_PRIMARY_SLOT_DEVPATH + string "Application image primary slot device path" + default "/dev/ota0" + +config ESP32C3_OTA_SECONDARY_SLOT_OFFSET + hex "Application image secondary slot offset" + default 0x110000 + +config ESP32C3_OTA_SECONDARY_SLOT_DEVPATH + string "Application image secondary slot device path" + default "/dev/ota1" + +config ESP32C3_OTA_SLOT_SIZE + hex "Application image slot size (in bytes)" + default 0x100000 + +config ESP32C3_OTA_SCRATCH_OFFSET + hex "Scratch partition offset" + default 0x210000 + +config ESP32C3_OTA_SCRATCH_SIZE + hex "Scratch partition size" + default 0x40000 + +config ESP32C3_OTA_SCRATCH_DEVPATH + string "Scratch partition device path" + default "/dev/otascratch" + +endif + +if ESP32C3_SPIFLASH + +comment "General storage MTD configuration" + +config ESP32C3_MTD + bool "MTD driver" + default y + select MTD + select MTD_BYTE_WRITE + select MTD_PARTITION + ---help--- + Initialize an MTD driver for the ESP32-C3 SPI Flash, which will + add an entry at /dev for application access from userspace. + +config ESP32C3_SPIFLASH_MTD_BLKSIZE + int "Storage MTD block size" + default 64 + depends on ESP32C3_MTD + +config ESP32C3_STORAGE_MTD_DEBUG + bool "Storage MTD Debug" + default n + depends on ESP32C3_MTD && DEBUG_FS_INFO + ---help--- + If this option is enabled, Storage MTD driver read and write functions + will output input parameters and return values (if applicable). + +if ESP32C3_APP_FORMAT_LEGACY + +comment "Partition Table configuration" + +config ESP32C3_PARTITION_TABLE + bool "Create MTD partitions from Partition Table" + default n + select ESP32C3_BOOTLOADER_BUILD_FROM_SOURCE + ---help--- + Decode partition table and initialize partitions as MTD. + +config ESP32C3_PARTITION_MOUNTPT + string "Partition mount point" + default "/dev/esp/partition/" + depends on ESP32C3_PARTITION_TABLE + +endif # ESP32C3_APP_FORMAT_LEGACY + +endif # ESP32C3_SPIFLASH + +endmenu # SPI Flash configuration + +menu "GDMA Configuration" + depends on ESP32C3_DMA + +endmenu # GDMA Configuration + +config ESP32C3_AUTO_SLEEP + bool "Auto-sleep" + default n + select PM + select ESP32C3_RT_TIMER + select ESP32C3_TICKLESS + ---help--- + Enable ESP32-C3 Auto-sleep + +config ESP32C3_TICKLESS + bool "Enable ESP32-C3 tickless OS" + default n + select ARCH_HAVE_TICKLESS + select SCHED_TICKLESS + +config ESP32C3_HAVE_OTA_PARTITION + bool + default n + +menu "Bootloader and Image Configuration" + +config ESP32C3_APP_FORMAT_LEGACY + bool + default y if !ESP32C3_APP_FORMAT_MCUBOOT + depends on !ESP32C3_APP_FORMAT_MCUBOOT + ---help--- + This is the legacy application image format, as supported by the ESP-IDF + 2nd stage bootloader. + +config ESP32C3_APP_FORMAT_MCUBOOT + bool "Enable MCUboot-bootable format" + depends on !MCUBOOT_BOOTLOADER + select ESP32C3_HAVE_OTA_PARTITION + select ESP32C3_BOOTLOADER_BUILD_FROM_SOURCE + ---help--- + Enables the Espressif port of MCUboot to be used as 2nd stage bootloader. + +config ESP32C3_BOOTLOADER_DOWNLOAD_PREBUILT + bool + default y if !ESP32C3_BOOTLOADER_BUILD_FROM_SOURCE + depends on !ESP32C3_BOOTLOADER_BUILD_FROM_SOURCE + ---help--- + The build system will download the prebuilt binaries from + https://github.com/espressif/esp-nuttx-bootloader according to the chosen + Application Image Format (ESP32C3_APP_FORMAT_LEGACY or ESP32C3_APP_FORMAT_MCUBOOT) + +config ESP32C3_BOOTLOADER_BUILD_FROM_SOURCE + bool "Build binaries from source" + ---help--- + The build system will build all the required binaries from source. It will clone + the https://github.com/espressif/esp-nuttx-bootloader repository and build a + custom bootloader according to the chosen Application Image Format + (ESP32C3_APP_FORMAT_LEGACY or ESP32C3_APP_FORMAT_MCUBOOT) and partition information. + +choice + prompt "Target slot for image flashing" + default ESP32C3_ESPTOOL_TARGET_PRIMARY + depends on ESP32C3_HAVE_OTA_PARTITION + ---help--- + Slot to which ESPTOOL will flash the generated binary image. + +config ESP32C3_ESPTOOL_TARGET_PRIMARY + bool "Application image primary slot" + ---help--- + This assumes that the generated image is already pre-validated. + This is the recommended option for the initial stages of the + application firmware image development. + +config ESP32C3_ESPTOOL_TARGET_SECONDARY + bool "Application image secondary slot" + ---help--- + The application needs to confirm the generated image as valid, + otherwise the bootloader may consider it invalid and perform the + rollback of the update after a reset. + This is the choice most suitable for the development and verification + of a secure firmware update workflow. + +endchoice + +config ESP32C3_MCUBOOT_VERSION + string "MCUboot version" + depends on ESP32C3_APP_FORMAT_MCUBOOT + default "b206b99b1555ca15f790a3287e57dc98ef3df2ac" + +config ESP32C3_APP_MCUBOOT_HEADER_SIZE + int "Application image header size (in bytes)" + default 32 + depends on ESP32C3_APP_FORMAT_MCUBOOT + +config ESP32C3_PARTITION_TABLE_OFFSET_DEFAULT + hex + default 0x8000 + depends on ESP32C3_APP_FORMAT_LEGACY + +config ESP32C3_CUSTOM_PARTITION_TABLE_OFFSET + bool "Customize partition table offset" + default n + depends on ESP32C3_APP_FORMAT_LEGACY + select ESP32C3_BOOTLOADER_BUILD_FROM_SOURCE + ---help--- + Enable to select the offset of the partition table in the flash. + +if ESP32C3_CUSTOM_PARTITION_TABLE_OFFSET + +config ESP32C3_PARTITION_TABLE_OFFSET + hex "Partition Table offset" + default ESP32C3_PARTITION_TABLE_OFFSET_DEFAULT + depends on ESP32C3_APP_FORMAT_LEGACY + +endif # ESP32C3_CUSTOM_PARTITION_TABLE_OFFSET + +if !ESP32C3_CUSTOM_PARTITION_TABLE_OFFSET + +config ESP32C3_PARTITION_TABLE_OFFSET + hex + default ESP32C3_PARTITION_TABLE_OFFSET_DEFAULT + depends on ESP32C3_APP_FORMAT_LEGACY + +endif # !ESP32C3_CUSTOM_PARTITION_TABLE_OFFSET + +if BUILD_PROTECTED + +config ESP32C3_USER_IMAGE_OFFSET + hex "User image offset" + default 0x90000 + ---help--- + Offset in SPI Flash for flashing the User application firmware image. + +endif + +source "arch/risc-v/src/esp32c3-legacy/Kconfig.security" + +endmenu # Application Image Configuration + +menu "Brownout Detect Configuration" + depends on ESP32C3_BROWNOUT_DET + +choice ESP32C3_BROWNOUT_DET_LVL_SEL + prompt "Brownout voltage level" + default ESP32C3_BROWNOUT_DET_LVL_SEL_7 + ---help--- + The brownout detector will reset the chip when the supply voltage is approximately + below this level. Note that there may be some variation of brownout voltage level + between each chip. + + #The voltage levels here are estimates, more work needs to be done to figure out the exact voltages + #of the brownout threshold levels. + +config ESP32C3_BROWNOUT_DET_LVL_SEL_7 + bool "2.51V" + +config ESP32C3_BROWNOUT_DET_LVL_SEL_6 + bool "2.64V" + +config ESP32C3_BROWNOUT_DET_LVL_SEL_5 + bool "2.76V" + +config ESP32C3_BROWNOUT_DET_LVL_SEL_4 + bool "2.92V" + +config ESP32C3_BROWNOUT_DET_LVL_SEL_3 + bool "3.10V" + +config ESP32C3_BROWNOUT_DET_LVL_SEL_2 + bool "3.27V" + +endchoice + +config ESP32C3_BROWNOUT_DET_LVL + int + default 2 if ESP32C3_BROWNOUT_DET_LVL_SEL_2 + default 3 if ESP32C3_BROWNOUT_DET_LVL_SEL_3 + default 4 if ESP32C3_BROWNOUT_DET_LVL_SEL_4 + default 5 if ESP32C3_BROWNOUT_DET_LVL_SEL_5 + default 6 if ESP32C3_BROWNOUT_DET_LVL_SEL_6 + default 7 if ESP32C3_BROWNOUT_DET_LVL_SEL_7 + +endmenu # ESP32C3_BROWNOUT_DET + +endif # ARCH_CHIP_ESP32C3 diff --git a/arch/risc-v/src/esp32c3/Kconfig.security b/arch/risc-v/src/esp32c3-legacy/Kconfig.security similarity index 100% rename from arch/risc-v/src/esp32c3/Kconfig.security rename to arch/risc-v/src/esp32c3-legacy/Kconfig.security diff --git a/arch/risc-v/src/esp32c3-legacy/Make.defs b/arch/risc-v/src/esp32c3-legacy/Make.defs new file mode 100644 index 0000000000000..73ed5f333058d --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/Make.defs @@ -0,0 +1,260 @@ +############################################################################ +# arch/risc-v/src/esp32c3-legacy/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include common/Make.defs + +# Specify our HEAD assembly file. This will be linked as +# the first object file, so it will appear at address 0 + +HEAD_ASRC = esp32c3_head.S + +CHIP_ASRCS = esp32c3_vectors.S + +# Specify our general Assembly files + +CMN_ASRCS := $(filter-out riscv_vectors.S,$(CMN_ASRCS)) + +# Specify our C code within this directory to be included + +CHIP_CSRCS = esp32c3_allocateheap.c esp32c3_start.c esp32c3_wdt.c esp32c3_idle.c +CHIP_CSRCS += esp32c3_irq.c esp32c3_libc_stubs.c +CHIP_CSRCS += esp32c3_clockconfig.c esp32c3_gpio.c esp32c3_rtc_gpio.c +CHIP_CSRCS += esp32c3_lowputc.c esp32c3_serial.c +CHIP_CSRCS += esp32c3_systemreset.c esp32c3_resetcause.c +CHIP_CSRCS += esp32c3_uid.c esp32c3_perf.c + +ifeq ($(CONFIG_ESP32C3_REGION_PROTECTION),y) +CHIP_CSRCS += esp32c3_region.c +endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += esp32c3_userspace.c +endif + +ifeq ($(CONFIG_SCHED_TICKLESS),y) +CHIP_CSRCS += esp32c3_tickless.c +else +CHIP_CSRCS += esp32c3_timerisr.c +endif + +ifeq ($(CONFIG_ESP32C3_USBSERIAL),y) +CHIP_CSRCS += esp32c3_usbserial.c +endif + +ifeq ($(CONFIG_ESP32C3_RNG),y) +CHIP_CSRCS += esp32c3_rng.c +endif + +ifeq ($(CONFIG_ESP32C3_I2C),y) +CHIP_CSRCS += esp32c3_i2c.c +endif + +ifeq ($(CONFIG_ESP32C3_TWAI),y) +CHIP_CSRCS += esp32c3_twai.c +endif + +ifeq ($(CONFIG_ESP32C3_SPI),y) +CHIP_CSRCS += esp32c3_spi.c + ifeq ($(CONFIG_SPI_SLAVE),y) + CHIP_CSRCS += esp32c3_spi_slave.c + endif +endif + +ifeq ($(CONFIG_ESP32C3_SPIFLASH),y) +CHIP_CSRCS += esp32c3_spiflash.c + ifeq ($(CONFIG_ESP32C3_MTD),y) + CHIP_CSRCS += esp32c3_spiflash_mtd.c + endif +endif + +ifeq ($(CONFIG_ESP32C3_PARTITION_TABLE),y) +CHIP_CSRCS += esp32c3_partition.c +endif + +ifeq ($(CONFIG_WATCHDOG),y) +CHIP_CSRCS += esp32c3_wdt_lowerhalf.c +endif + +ifeq ($(CONFIG_ESP32C3_TIMER),y) +CHIP_CSRCS += esp32c3_tim.c +ifeq ($(CONFIG_TIMER),y) +CHIP_CSRCS += esp32c3_tim_lowerhalf.c +endif +endif + +ifeq ($(CONFIG_ESP32C3_ONESHOT),y) +CHIP_CSRCS += esp32c3_oneshot.c +ifeq ($(CONFIG_ONESHOT),y) +CHIP_CSRCS += esp32c3_oneshot_lowerhalf.c +endif +endif + +ifeq ($(CONFIG_ESP32C3_RT_TIMER),y) +CHIP_CSRCS += esp32c3_rt_timer.c +endif + +ifeq ($(CONFIG_ESP32C3_BIGNUM_ACCELERATOR),y) +CHIP_CSRCS += esp32c3_bignum.c +endif + +ifeq ($(CONFIG_ESP32C3_RSA_ACCELERATOR),y) +CHIP_CSRCS += esp32c3_rsa.c +endif + +ifeq ($(CONFIG_ESP32C3_SHA_ACCELERATOR),y) +CHIP_CSRCS += esp32c3_sha.c +endif + +ifeq ($(CONFIG_ESP32C3_FREERUN),y) +CHIP_CSRCS += esp32c3_freerun.c +endif + +ifeq ($(CONFIG_ESP32C3_DMA),y) +CHIP_CSRCS += esp32c3_dma.c +endif + +ifeq ($(CONFIG_PM),y) +ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) +CHIP_CSRCS += esp32c3_pminitialize.c +endif +CHIP_CSRCS += esp32c3_pm.c +endif + +CHIP_CSRCS += esp32c3_rtc.c + +ifeq ($(CONFIG_ESP32C3_LEDC),y) +CHIP_CSRCS += esp32c3_ledc.c +endif + +ifeq ($(CONFIG_ESP32C3_ADC),y) +CHIP_CSRCS += esp32c3_adc.c +endif + +ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE),y) +CHIP_CSRCS += esp32c3_crypto.c +endif + +ifeq ($(CONFIG_ESP32C3_AES_ACCELERATOR),y) +CHIP_CSRCS += esp32c3_aes.c +endif + +ifeq ($(CONFIG_ESP32C3_EFUSE),y) +CHIP_CSRCS += esp32c3_efuse.c +CHIP_CSRCS += esp32c3_efuse_table.c +CHIP_CSRCS += esp32c3_efuse_lowerhalf.c +endif + +ifeq ($(CONFIG_ARCH_HAVE_EXTRA_HEAPS),y) +CHIP_CSRCS += esp32c3_extraheaps.c +endif + +ifeq ($(CONFIG_ARCH_USE_TEXT_HEAP),y) +CHIP_CSRCS += esp32c3_textheap.c +endif + +ifeq ($(CONFIG_RTC_DRIVER),y) +CHIP_CSRCS += esp32c3_rtc_lowerhalf.c +endif + +ifeq ($(CONFIG_ESP32C3_RTC_HEAP),y) +CHIP_CSRCS += esp32c3_rtcheap.c +endif + +ifeq ($(CONFIG_ESP32C3_BROWNOUT_DET),y) +CHIP_CSRCS += esp32c3_brownout.c +endif + +ifeq ($(CONFIG_SPI_ICE40),y) +CHIP_CSRCS += esp32c3_ice40.c +endif + +ifeq ($(CONFIG_ESP32C3_WIRELESS),y) +WIRELESS_DRV_UNPACK = esp-wireless-drivers-3rdparty +WIRELESS_DRV_ID = 45701c0 +WIRELESS_DRV_ZIP = $(WIRELESS_DRV_ID).zip +WIRELESS_DRV_URL = https://github.com/espressif/esp-wireless-drivers-3rdparty/archive + +$(WIRELESS_DRV_ZIP): + $(call DOWNLOAD,$(WIRELESS_DRV_URL),$(WIRELESS_DRV_ZIP),chip/$(WIRELESS_DRV_ZIP)) + +chip/$(WIRELESS_DRV_UNPACK): $(WIRELESS_DRV_ZIP) + $(Q) echo "Unpacking: ESP Wireless Drivers" + $(Q) unzip -oqq chip/$(WIRELESS_DRV_ZIP) -d chip/ + $(Q) mv chip/$(WIRELESS_DRV_UNPACK)-$(WIRELESS_DRV_ID)* chip/$(WIRELESS_DRV_UNPACK) + $(Q) touch chip/$(WIRELESS_DRV_UNPACK) + +ifeq ($(wildcard chip/$(WIRELESS_DRV_UNPACK)/.git),) +context:: chip/$(WIRELESS_DRV_UNPACK) + +distclean:: + $(call DELFILE, chip/$(WIRELESS_DRV_ZIP)) + $(call DELDIR, chip/$(WIRELESS_DRV_UNPACK)) +endif + +INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)esp-wireless-drivers-3rdparty$(DELIM)include +INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)esp-wireless-drivers-3rdparty$(DELIM)include$(DELIM)esp32c3 + +EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)esp-wireless-drivers-3rdparty$(DELIM)libs$(DELIM)esp32c3 +EXTRA_LIBS += -lphy + +# Wireless interfaces. + +CHIP_CSRCS += esp32c3_wireless.c +endif + +ifeq ($(CONFIG_ESP32C3_WIFI),y) +CHIP_CSRCS += esp32c3_wlan.c esp32c3_wifi_utils.c esp32c3_wifi_adapter.c +EXTRA_LIBS += -lcore -lnet80211 -lpp -lsmartconfig -lcoexist -lespnow -lwpa_supplicant -lwapi -lmesh +endif + +ifeq ($(CONFIG_ESP32C3_BLE),y) +CHIP_CSRCS += esp32c3_ble_adapter.c esp32c3_ble.c +EXTRA_LIBS += -lbtbb -lbtdm_app +endif + +############################################################################# +# Espressif HAL for 3rd Party Platforms +############################################################################# + +# Fetch source files and add them to build + +ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty +ifndef ESP_HAL_3RDPARTY_VERSION + ESP_HAL_3RDPARTY_VERSION = 45c33111b441363e1267158186a60f42525228ca +endif + +ifndef ESP_HAL_3RDPARTY_URL + ESP_HAL_3RDPARTY_URL = https://github.com/espressif/esp-hal-3rdparty.git +endif + +chip/$(ESP_HAL_3RDPARTY_REPO): + $(Q) echo "Cloning Espressif HAL for 3rd Party Platforms" + $(Q) git clone --quiet $(ESP_HAL_3RDPARTY_URL) chip/$(ESP_HAL_3RDPARTY_REPO) + $(Q) echo "Espressif HAL for 3rd Party Platforms: ${ESP_HAL_3RDPARTY_VERSION}" + $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) checkout --quiet $(ESP_HAL_3RDPARTY_VERSION) + +# Silent preprocessor warnings + +CFLAGS += -Wno-undef -Wno-unused-variable + +include chip/Bootloader.mk + +distclean:: + $(call DELDIR,chip/$(ESP_HAL_3RDPARTY_REPO)) diff --git a/arch/risc-v/src/esp32c3-legacy/chip.h b/arch/risc-v/src/esp32c3-legacy/chip.h new file mode 100644 index 0000000000000..d7eccc23f75a8 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/chip.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_CHIP_H +#define __ARCH_RISCV_SRC_ESP32C3_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "esp32c3_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Section for exception handler. */ + +#define EXCEPTION_SECTION .iram1 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_CHIP_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3.h b/arch/risc-v/src/esp32c3-legacy/esp32c3.h similarity index 89% rename from arch/risc-v/src/esp32c3/esp32c3.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3.h index af3c28dadb22c..a332d20e70898 100644 --- a/arch/risc-v/src/esp32c3/esp32c3.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3.h + * arch/risc-v/src/esp32c3-legacy/esp32c3.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_H /**************************************************************************** * Included Files @@ -46,4 +46,4 @@ #endif -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_adc.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_adc.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_adc.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_adc.c index 28837306bcab5..50f262f50d5b8 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_adc.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_adc.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_adc.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_adc.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_adc.h similarity index 91% rename from arch/risc-v/src/esp32c3/esp32c3_adc.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_adc.h index f79bf3f025de7..a7577b34cc8db 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_adc.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_adc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_adc.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_adc.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_ADC_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_ADC_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_ADC_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_ADC_H /**************************************************************************** * Included Files @@ -76,4 +76,4 @@ struct adc_dev_s *esp32c3_adc_init(int channel); #undef EXTERN #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_ADC_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_ADC_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_aes.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_aes.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_aes.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_aes.c index 93e409a8af6e9..2eeddf0081ed2 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_aes.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_aes.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_aes.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_aes.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_aes.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_aes.h new file mode 100644 index 0000000000000..e906135696730 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_aes.h @@ -0,0 +1,217 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/esp32c3_aes.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_AES_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_AES_H + +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* AES private description */ + +struct esp32c3_aes_s +{ + uint32_t key[8]; /* Key data value */ + uint16_t keybits; /* Key data bits */ +}; + +/* AES XTS private description */ + +struct esp32c3_aes_xts_s +{ + struct esp32c3_aes_s crypt; /* AES block encryption/decryption */ + struct esp32c3_aes_s tweak; /* AES tweak encryption/decryption */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_aes_ecb_cypher + * + * Description: + * Process AES ECB encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_ecb_cypher(struct esp32c3_aes_s *aes, bool encrypt, + const void *input, void *output, uint32_t size); + +/**************************************************************************** + * Name: esp32c3_aes_cbc_cypher + * + * Description: + * Process AES CBC encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * ivptr - Initialization vector pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_cbc_cypher(struct esp32c3_aes_s *aes, bool encrypt, + void *ivptr, const void *input, void *output, + uint32_t size); + +/**************************************************************************** + * Name: esp32c3_aes_ctr_cypher + * + * Description: + * Process AES CTR encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * offptr - Offset buffer pointer + * cntptr - Counter buffer pointer + * cacheptr - Counter calculation buffer pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_ctr_cypher(struct esp32c3_aes_s *aes, uint32_t *offptr, + void *cntptr, void *cacheptr, const void *input, + void *output, uint32_t size); + +/**************************************************************************** + * Name: esp32c3_aes_xts_cypher + * + * Description: + * Process AES XTS encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * unitptr - Unit data buffer pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_xts_cypher(struct esp32c3_aes_xts_s *aes, bool encrypt, + void *unitptr, const void *input, void *output, + uint32_t size); + +/**************************************************************************** + * Name: esp32c3_aes_setkey + * + * Description: + * Configurate AES key. + * + * Input Parameters: + * aes - AES object data pointer + * keyptr - Key data pointer + * keybits - Key data bits + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_setkey(struct esp32c3_aes_s *aes, const void *keyptr, + uint16_t keybits); + +/**************************************************************************** + * Name: esp32c3_aes_xts_setkey + * + * Description: + * Configurate AES XTS key. + * + * Input Parameters: + * aes - AES object data pointer + * keyptr - Key data pointer + * keybits - Key data bits + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_xts_setkey(struct esp32c3_aes_xts_s *aes, const void *keyptr, + uint16_t keybits); + +/**************************************************************************** + * Name: esp32c3_aes_init + * + * Description: + * Initialize ESP32-C3 AES hardware driver. + * + * Input Parameters: + * None + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_aes_init(void); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_AES_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_allocateheap.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_allocateheap.c similarity index 93% rename from arch/risc-v/src/esp32c3/esp32c3_allocateheap.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_allocateheap.c index 6ede4bdec4d46..e6417ddfb235e 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_allocateheap.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_allocateheap.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_allocateheap.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_allocateheap.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -36,6 +36,7 @@ #include #endif +#include "riscv_internal.h" #include "esp32c3.h" #include "hardware/esp32c3_rom_layout.h" @@ -88,17 +89,16 @@ void up_allocate_heap(void **heap_start, size_t *heap_size) #else /* These values come from the linker scripts * (_sections.ld and flat_memory.ld). - * Check boards/risc-v/esp32c3. + * Check boards/risc-v/esp32c3-legacy. */ - extern uint8_t _sheap[]; extern const struct esp32c3_rom_layout_s *ets_rom_layout_p; board_autoled_on(LED_HEAPALLOCATE); - *heap_start = _sheap; - *heap_size = ets_rom_layout_p->dram0_rtos_reserved_start - - (uintptr_t)_sheap; + *heap_start = (void *)g_idle_topstack; + *heap_size = (uintptr_t)ets_rom_layout_p->dram0_rtos_reserved_start - + g_idle_topstack; #endif /* CONFIG_BUILD_PROTECTED && CONFIG_MM_KERNEL_HEAP */ } @@ -120,12 +120,10 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size) { /* These values come from the linker scripts (kernel-space.ld and * protected_memory.ld). - * Check boards/risc-v/esp32c3. + * Check boards/risc-v/esp32c3-legacy. */ - extern uint8_t _sheap[]; - - uintptr_t kbase = (uintptr_t)_sheap; + uintptr_t kbase = g_idle_topstack; uintptr_t ktop = KDRAM_END; size_t ksize = ktop - kbase; diff --git a/arch/risc-v/src/esp32c3/esp32c3_attr.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_attr.h similarity index 88% rename from arch/risc-v/src/esp32c3/esp32c3_attr.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_attr.h index e0c9818d07aec..960d46ed05b5d 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_attr.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_attr.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_attr.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_attr.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_ATTR_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_ATTR_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_ATTR_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_ATTR_H /**************************************************************************** * Pre-processor Definitions @@ -50,4 +50,4 @@ #define RTC_RODATA_ATTR locate_data(".rtc.rodata") -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_ATTR_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_ATTR_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_bignum.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_bignum.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_bignum.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_bignum.c index a21b36fcb36ae..8477e182c999a 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_bignum.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_bignum.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_bignum.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_bignum.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_bignum.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_bignum.h similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_bignum.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_bignum.h index 80d60430bbdd6..b8a5914b7bdd2 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_bignum.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_bignum.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_bignum.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_bignum.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BIGNUM_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BIGNUM_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_BIGNUM_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_BIGNUM_H /**************************************************************************** * Included Files @@ -869,4 +869,4 @@ int esp32c3_mpi_inv_mod(struct esp32c3_mpi_s *X, #undef EXTERN #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BIGNUM_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_BIGNUM_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_ble.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_ble.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_ble.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_ble.c index 98b0d99c48689..6c8f4bc2e61e3 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_ble.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_ble.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_ble.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_ble.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_ble.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_ble.h similarity index 88% rename from arch/risc-v/src/esp32c3/esp32c3_ble.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_ble.h index d1cd2c9bd1e65..ad5e50375219a 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_ble.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_ble.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_ble.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_ble.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BLE_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BLE_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_BLE_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_BLE_H /**************************************************************************** * Included Files @@ -47,4 +47,4 @@ int esp32c3_ble_initialize(void); -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BLE_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_BLE_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_ble_adapter.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_ble_adapter.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_ble_adapter.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_ble_adapter.c index 7bff497a0b41a..44f20362f7964 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_ble_adapter.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_ble_adapter.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_ble_adapter.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_ble_adapter.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_ble_adapter.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_ble_adapter.h similarity index 94% rename from arch/risc-v/src/esp32c3/esp32c3_ble_adapter.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_ble_adapter.h index 70260356e9501..d5898413cb27a 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_ble_adapter.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_ble_adapter.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_ble_adapter.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_ble_adapter.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BLE_ADAPTER_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BLE_ADAPTER_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_BLE_ADAPTER_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_BLE_ADAPTER_H /**************************************************************************** * Included Files @@ -158,4 +158,4 @@ void esp32c3_vhci_host_send_packet(uint8_t *data, uint16_t len); int esp32c3_vhci_register_callback( const esp_vhci_host_callback_t *callback); -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BLE_ADAPTER_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_BLE_ADAPTER_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_brownout.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_brownout.c similarity index 97% rename from arch/risc-v/src/esp32c3/esp32c3_brownout.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_brownout.c index b0dcf9d10c0ab..3e1cd857c4117 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_brownout.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_brownout.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_brownout.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_brownout.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_brownout.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_brownout.h similarity index 89% rename from arch/risc-v/src/esp32c3/esp32c3_brownout.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_brownout.h index 1afb757247cd4..363416219a9ff 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_brownout.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_brownout.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_brownout.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_brownout.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BROWNOUT_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BROWNOUT_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_BROWNOUT_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_BROWNOUT_H /**************************************************************************** * Included Files @@ -62,4 +62,4 @@ void esp32c3_brownout_init(void); #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_BROWNOUT_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_BROWNOUT_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_clockconfig.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_clockconfig.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_clockconfig.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_clockconfig.c index c68703d458eb3..11361f0ae069d 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_clockconfig.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_clockconfig.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_clockconfig.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_clockconfig.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_clockconfig.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_clockconfig.h similarity index 92% rename from arch/risc-v/src/esp32c3/esp32c3_clockconfig.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_clockconfig.h index 297a95ad964ad..d5262caaef5e8 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_clockconfig.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_clockconfig.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_clockconfig.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_clockconfig.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_CLOCKCONFIG_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_CLOCKCONFIG_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_CLOCKCONFIG_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_CLOCKCONFIG_H /**************************************************************************** * Included Files @@ -101,4 +101,4 @@ uint32_t IRAM_ATTR esp32c3_cpu_cycle_count(void); #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_CLOCKCONFIG_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_CLOCKCONFIG_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_config.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_config.h similarity index 91% rename from arch/risc-v/src/esp32c3/esp32c3_config.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_config.h index 0c520a4d3818e..c5057107cdba3 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_config.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_config.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_config.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_config.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_CONFIG_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_CONFIG_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_CONFIG_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_CONFIG_H /**************************************************************************** * Included Files @@ -68,4 +68,4 @@ # define HAVE_UART_DEVICE 1 #endif -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_CONFIG_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_CONFIG_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_crypto.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_crypto.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_crypto.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_crypto.c index de170596df320..76cb1d0a939cd 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_crypto.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_crypto.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_crypto.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_crypto.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_dma.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_dma.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_dma.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_dma.c index 88d21f300aed3..198328e82dcdf 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_dma.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_dma.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_dma.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_dma.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_dma.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_dma.h new file mode 100644 index 0000000000000..c0d4d9d59d79e --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_dma.h @@ -0,0 +1,225 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/esp32c3_dma.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_DMA_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_DMA_H + +#include +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ + +/* DMA max data length */ + +#define ESP32C3_DMA_DATALEN_MAX (0x1000 - 4) + +/* DMA max buffer length */ + +#define ESP32C3_DMA_BUFLEN_MAX ESP32C3_DMA_DATALEN_MAX + +/* DMA channel number */ + +#define ESP32C3_DMA_CHAN_MAX (3) + +/* DMA RX MAX priority */ + +#define ESP32C3_DMA_RX_PRIO_MAX (15) + +/* DMA TX MAX priority */ + +#define ESP32C3_DMA_TX_PRIO_MAX (15) + +/* DMA descriptor */ + +#define ESP32C3_DMA_CTRL_OWN (1 << 31) /* Owned by DMA */ +#define ESP32C3_DMA_CTRL_EOF (1 << 30) /* End of frame */ +#define ESP32C3_DMA_CTRL_ERREOF (1 << 28) /* Received data error */ +#define ESP32C3_DMA_CTRL_DATALEN_S (12) /* Data length shift */ +#define ESP32C3_DMA_CTRL_DATALEN_V (0xfff) /* Data length value */ +#define ESP32C3_DMA_CTRL_BUFLEN_S (0) /* Buffer length shift */ +#define ESP32C3_DMA_CTRL_BUFLEN_V (0xfff) /* Buffer length value */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum esp32c3_dma_periph_e +{ + ESP32C3_DMA_PERIPH_MEM = -1, + ESP32C3_DMA_PERIPH_SPI = 0, + ESP32C3_DMA_PERIPH_UCHI0 = 2, + ESP32C3_DMA_PERIPH_I2S = 3, + ESP32C3_DMA_PERIPH_RD0 = 4, + ESP32C3_DMA_PERIPH_RD1 = 5, + ESP32C3_DMA_PERIPH_AES = 6, + ESP32C3_DMA_PERIPH_SHA = 7, + ESP32C3_DMA_PERIPH_ADC = 8, + ESP32C3_DMA_PERIPH_NUM, +}; + +/* DMA descriptor type */ + +struct esp32c3_dmadesc_s +{ + uint32_t ctrl; /* DMA control block */ + const uint8_t *pbuf; /* DMA TX/RX buffer address */ + struct esp32c3_dmadesc_s *next; /* Next DMA descriptor address */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_dma_request + * + * Description: + * Request DMA channel and config it with given parameters. + * + * Input Parameters: + * periph - Peripheral for which the DMA channel request was made + * tx_prio - Interrupt priority + * rx_prio - Interrupt flags + * + * Returned Value: + * DMA channel number (>=0) if success or -1 if fail. + * + ****************************************************************************/ + +int32_t esp32c3_dma_request(enum esp32c3_dma_periph_e periph, + uint32_t tx_prio, + uint32_t rx_prio, + bool burst_en); + +/**************************************************************************** + * Name: esp32c3_dma_setup + * + * Description: + * Set up DMA descriptor with given parameters. + * + * Input Parameters: + * chan - DMA channel + * tx - true: TX mode; false: RX mode + * dmadesc - DMA descriptor pointer + * num - DMA descriptor number + * pbuf - Buffer pointer + * len - Buffer length by byte + * + * Returned Value: + * Bind pbuf data bytes. + * + ****************************************************************************/ + +uint32_t esp32c3_dma_setup(int chan, bool tx, + struct esp32c3_dmadesc_s *dmadesc, uint32_t num, + uint8_t *pbuf, uint32_t len); + +/**************************************************************************** + * Name: esp32c3_dma_enable + * + * Description: + * Enable DMA channel transmission. + * + * Input Parameters: + * chan - DMA channel + * tx - true: TX mode; false: RX mode + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_dma_enable(int chan, bool tx); + +/**************************************************************************** + * Name: esp32c3_dma_disable + * + * Description: + * Disable DMA channel transmission. + * + * Input Parameters: + * chan - DMA channel + * tx - true: TX mode; false: RX mode + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_dma_disable(int chan, bool tx); + +/**************************************************************************** + * Name: esp32c3_dma_wait_idle + * + * Description: + * Wait until transmission ends. + * + * Input Parameters: + * chan - DMA channel + * tx - true: TX mode; false: RX mode + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_dma_wait_idle(int chan, bool tx); + +/**************************************************************************** + * Name: esp32c3_dma_init + * + * Description: + * Initialize DMA driver. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_dma_init(void); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_DMA_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_efuse.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_efuse.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_efuse.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_efuse.c index 79edcf7e297ea..fc23911c9d6fe 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_efuse.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_efuse.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_efuse.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_efuse.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -28,7 +28,7 @@ #include #include #include -#include +#include #include "riscv_internal.h" #include "hardware/esp32c3_soc.h" diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_efuse.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_efuse.h new file mode 100644 index 0000000000000..c3d6b856565dd --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_efuse.h @@ -0,0 +1,189 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/esp32c3_efuse.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_EFUSE_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_EFUSE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Type of eFuse blocks for ESP32C3 */ + +typedef enum +{ + EFUSE_BLK0 = 0, /* Number of eFuse BLOCK0. REPEAT_DATA */ + + EFUSE_BLK1 = 1, /* Number of eFuse BLOCK1. MAC_SPI_8M_SYS */ + + EFUSE_BLK2 = 2, /* Number of eFuse BLOCK2. SYS_DATA_PART1 */ + EFUSE_BLK_SYS_DATA_PART1 = 2, /* Number of eFuse BLOCK2. SYS_DATA_PART1 */ + + EFUSE_BLK3 = 3, /* Number of eFuse BLOCK3. USER_DATA */ + EFUSE_BLK_USER_DATA = 3, /* Number of eFuse BLOCK3. USER_DATA */ + + EFUSE_BLK4 = 4, /* Number of eFuse BLOCK4. KEY0 */ + EFUSE_BLK_KEY0 = 4, /* Number of eFuse BLOCK4. KEY0 */ + + EFUSE_BLK5 = 5, /* Number of eFuse BLOCK5. KEY1 */ + EFUSE_BLK_KEY1 = 5, /* Number of eFuse BLOCK5. KEY1 */ + + EFUSE_BLK6 = 6, /* Number of eFuse BLOCK6. KEY2 */ + EFUSE_BLK_KEY2 = 6, /* Number of eFuse BLOCK6. KEY2 */ + + EFUSE_BLK7 = 7, /* Number of eFuse BLOCK7. KEY3 */ + EFUSE_BLK_KEY3 = 7, /* Number of eFuse BLOCK7. KEY3 */ + + EFUSE_BLK8 = 8, /* Number of eFuse BLOCK8. KEY4 */ + EFUSE_BLK_KEY4 = 8, /* Number of eFuse BLOCK8. KEY4 */ + + EFUSE_BLK9 = 9, /* Number of eFuse BLOCK9. KEY5 */ + EFUSE_BLK_KEY5 = 9, /* Number of eFuse BLOCK9. KEY5 */ + EFUSE_BLK_KEY_MAX = 10, + + EFUSE_BLK10 = 10, /* Number of eFuse BLOCK10. SYS_DATA_PART2 */ + EFUSE_BLK_SYS_DATA_PART2 = 10, /* Number of eFuse BLOCK10. SYS_DATA_PART2 */ + + EFUSE_BLK_MAX +} esp_efuse_block_t; + +/**************************************************************************** + * Name: efuse_func_proc_t + * + * Description: + * This is type of function that will handle the efuse field register. + * + * Input Parameters: + * num_reg - The register number in the block. + * bit_start - Start bit in the register. + * bit_count - The number of bits used in the register. + * arr - A pointer to an array or variable. + * bits_counter - Counter bits. + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +typedef int (*efuse_func_proc_t) (uint32_t num_reg, + int bit_start, + int bit_count, + void *arr, int *bits_counter); + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_efuse_read_field + * + * Description: + * Read value from EFUSE, writing it into an array. + * + * Input Parameters: + * field - A pointer to describing the fields of efuse + * dst - A pointer to array that contains the data for reading + * dst_size_bits - The number of bits required to read + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_efuse_read_field(const efuse_desc_t *field[], void *dst, + size_t dst_size_bits); + +/**************************************************************************** + * Name: esp32c3_efuse_write_field + * + * Description: + * Write array to EFUSE. + * + * Input Parameters: + * field - A pointer to describing the fields of efuse + * src - A pointer to array that contains the data for writing + * src_size_bits - The number of bits required to write + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_efuse_write_field(const efuse_desc_t *field[], + const void *src, size_t src_size_bits); + +/**************************************************************************** + * Name: esp32c3_efuse_burn_efuses + * + * Description: + * Burn values written to the efuse write registers. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_efuse_burn_efuses(void); + +/**************************************************************************** + * Name: esp32c3_efuse_initialize + * + * Description: + * Initialize the efuse driver. The efuse is initialized + * and registered as 'devpath'. + * + * Input Parameters: + * devpath - The full path to the efuse device. + * This should be of the form /dev/efuse + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_efuse_initialize(const char *devpath); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_EFUSE_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_efuse_lowerhalf.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_efuse_lowerhalf.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_efuse_lowerhalf.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_efuse_lowerhalf.c index e1d15d46fa5c7..0364e260d3296 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_efuse_lowerhalf.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_efuse_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_efuse_lowerhalf.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_efuse_lowerhalf.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_efuse_table.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_efuse_table.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_efuse_table.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_efuse_table.c index 9eaeef685c11a..98a0dba348974 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_efuse_table.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_efuse_table.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_efuse_table.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_efuse_table.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_extraheaps.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_extraheaps.c similarity index 97% rename from arch/risc-v/src/esp32c3/esp32c3_extraheaps.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_extraheaps.c index beb6b96fa6af4..4a10b735fcb2d 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_extraheaps.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_extraheaps.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_extraheaps.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_extraheaps.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_freerun.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_freerun.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_freerun.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_freerun.c index 85017ff46433d..4cc1b4d749b13 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_freerun.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_freerun.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_freerun.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_freerun.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_freerun.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_freerun.h similarity index 95% rename from arch/risc-v/src/esp32c3/esp32c3_freerun.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_freerun.h index d9842146cc15c..cc47c469a79d1 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_freerun.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_freerun.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_freerun.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_freerun.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_FREERUN_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_FREERUN_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_FREERUN_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_FREERUN_H /**************************************************************************** * Included Files @@ -142,4 +142,4 @@ int esp32c3_freerun_uninitialize(struct esp32c3_freerun_s *freerun); #endif #endif /* CONFIG_ESP32C3_FREERUN */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_FREERUN_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_FREERUN_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_gpio.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_gpio.c new file mode 100644 index 0000000000000..6fc1d056292db --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_gpio.c @@ -0,0 +1,420 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/esp32c3_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "riscv_internal.h" +#ifdef CONFIG_ESP32C3_GPIO_IRQ +#include "esp32c3_irq.h" +#endif +#include "hardware/esp32c3_iomux.h" +#include "hardware/esp32c3_gpio.h" +#include "hardware/esp32c3_usb_serial_jtag.h" + +#include "esp32c3_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define USB_JTAG_DM 18 +#define USB_JTAG_DP 19 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_GPIO_IRQ +static int g_gpio_cpuint; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpio_dispatch + * + * Description: + * Second level dispatch for GPIO interrupt handling. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_GPIO_IRQ +static void gpio_dispatch(int irq, uint32_t status, uint32_t *regs) +{ + int i; + int ndx = 0; + + /* Check set bits in the status register */ + + while ((i = __builtin_ffs(status))) + { + ndx += i; + irq_dispatch(irq + ndx - 1, regs); + status >>= i; + } +} +#endif + +/**************************************************************************** + * Name: gpio_interrupt + * + * Description: + * GPIO interrupt handler. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_GPIO_IRQ +static int gpio_interrupt(int irq, void *context, void *arg) +{ + uint32_t status; + + /* Read and clear the lower GPIO interrupt status */ + + status = getreg32(GPIO_STATUS_REG); + putreg32(status, GPIO_STATUS_W1TC_REG); + + /* Dispatch pending interrupts in the lower GPIO status register */ + + gpio_dispatch(ESP32C3_FIRST_GPIOIRQ, status, (uint32_t *)context); + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_configgpio + * + * Description: + * Configure a GPIO pin based on encoded pin attributes. + * + ****************************************************************************/ + +int esp32c3_configgpio(int pin, gpio_pinattr_t attr) +{ + uintptr_t regaddr; + uint32_t func; + uint32_t cntrl; + uint32_t pin2func; + + DEBUGASSERT(pin >= 0 && pin <= ESP32C3_NGPIOS); + + func = 0; + cntrl = 0; + + /* If pin 18 or 19 then disable the USB/JTAG function and pull-up */ + + if ((pin == USB_JTAG_DM) || (pin == USB_JTAG_DP)) + { + uint32_t regval; + + regval = getreg32(USB_SERIAL_JTAG_CONF0_REG); + regval &= ~(USB_SERIAL_JTAG_USB_PAD_ENABLE | + USB_SERIAL_JTAG_DP_PULLUP); + putreg32(regval, USB_SERIAL_JTAG_CONF0_REG); + } + + /* Handle input pins */ + + if ((attr & INPUT) != 0) + { + putreg32((1ul << pin), GPIO_ENABLE_W1TC_REG); + + /* Input enable */ + + func |= FUN_IE; + + if ((attr & PULLUP) != 0) + { + func |= FUN_PU; + } + else if ((attr & PULLDOWN) != 0) + { + func |= FUN_PD; + } + } + + /* Handle output pins */ + + if ((attr & OUTPUT) != 0) + { + putreg32((1ul << pin), GPIO_ENABLE_W1TS_REG); + } + + /* Add drivers */ + + func |= (uint32_t)(2ul << FUN_DRV_S); + + /* Select the pad's function. If no function was given, consider it a + * normal input or output (i.e. function1). + */ + + if ((attr & FUNCTION_MASK) != 0) + { + func |= (uint32_t)(((attr >> FUNCTION_SHIFT) - 1) << MCU_SEL_S); + } + else + { + func |= (uint32_t)(PIN_FUNC_GPIO << MCU_SEL_S); + } + + if ((attr & OPEN_DRAIN) != 0) + { + cntrl |= (1 << GPIO_PIN_PAD_DRIVER_S); + } + + /* Set the pin function to its register */ + + pin2func = (pin + 1) * 4; + regaddr = REG_IO_MUX_BASE + pin2func; + putreg32(func, regaddr); + + regaddr = GPIO_REG(pin); + putreg32(cntrl, regaddr); + return OK; +} + +/**************************************************************************** + * Name: esp32c3_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void esp32c3_gpiowrite(int pin, bool value) +{ + DEBUGASSERT(pin >= 0 && pin <= ESP32C3_NGPIOS); + + if (value) + { + putreg32(1ul << pin, GPIO_OUT_W1TS_REG); + } + else + { + putreg32(1ul << pin, GPIO_OUT_W1TC_REG); + } +} + +/**************************************************************************** + * Name: esp32c3_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool esp32c3_gpioread(int pin) +{ + uint32_t regval; + + DEBUGASSERT(pin >= 0 && pin <= ESP32C3_NGPIOS); + + regval = getreg32(GPIO_IN_REG); + return ((regval >> pin) & 1) != 0; +} + +/**************************************************************************** + * Name: esp32c3_gpio_matrix_in + * + * Description: + * Set gpio input to a signal + * NOTE: one gpio can input to several signals + * If gpio == 0x30, cancel input to the signal, input 0 to signal + * If gpio == 0x38, cancel input to the signal, input 1 to signal, + * for I2C pad + * + ****************************************************************************/ + +void esp32c3_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv) +{ + uint32_t regaddr = GPIO_FUNC0_IN_SEL_CFG_REG + (signal_idx * 4); + uint32_t regval = (gpio << GPIO_FUNC0_IN_SEL_S); + + if (inv) + { + regval |= GPIO_FUNC0_IN_INV_SEL; + } + + if (gpio != 0x34) + { + regval |= GPIO_SIG0_IN_SEL; + } + + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: esp32c3_gpio_matrix_out + * + * Description: + * Set signal output to gpio + * NOTE: one signal can output to several gpios + * If signal_idx == 0x100, cancel output put to the gpio + * + ****************************************************************************/ + +void esp32c3_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, + bool out_inv, bool oen_inv) +{ + uint32_t regaddr = GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio * 4); + uint32_t regval = signal_idx << GPIO_FUNC0_OUT_SEL_S; + + if (gpio >= ESP32C3_NGPIOS) + { + return; + } + + putreg32((1ul << gpio), GPIO_ENABLE_W1TS_REG); + + if (out_inv) + { + regval |= GPIO_FUNC0_OUT_INV_SEL; + } + + if (oen_inv) + { + regval |= GPIO_FUNC0_OEN_INV_SEL; + } + + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: esp32c3_gpioirqinitialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_GPIO_IRQ +void esp32c3_gpioirqinitialize(void) +{ + /* Setup the GPIO interrupt. */ + + g_gpio_cpuint = esp32c3_setup_irq(ESP32C3_PERIPH_GPIO, + 1, ESP32C3_INT_LEVEL); + DEBUGASSERT(g_gpio_cpuint > 0); + + /* Attach and enable the interrupt handler */ + + DEBUGVERIFY(irq_attach(ESP32C3_IRQ_GPIO, gpio_interrupt, NULL)); + up_enable_irq(ESP32C3_IRQ_GPIO); +} +#endif + +/**************************************************************************** + * Name: esp32c3_gpioirqenable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_GPIO_IRQ +void esp32c3_gpioirqenable(int irq, gpio_intrtype_t intrtype) +{ + uintptr_t regaddr; + uint32_t regval; + int pin; + + DEBUGASSERT(irq >= ESP32C3_FIRST_GPIOIRQ && irq <= ESP32C3_LAST_GPIOIRQ); + + /* Convert the IRQ number to a pin number */ + + pin = ESP32C3_IRQ2PIN(irq); + + /* Disable the GPIO interrupt during the configuration. */ + + up_disable_irq(ESP32C3_IRQ_GPIO); + + /* Get the address of the GPIO PIN register for this pin */ + + regaddr = GPIO_REG(pin); + regval = getreg32(regaddr); + regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M); + + /* Set the pin ENA field. */ + + regval |= (1 << GPIO_PIN0_INT_ENA_S); + regval |= (intrtype << GPIO_PIN_INT_TYPE_S); + putreg32(regval, regaddr); + + /* Configuration done. Re-enable the GPIO interrupt. */ + + up_enable_irq(ESP32C3_IRQ_GPIO); +} +#endif + +/**************************************************************************** + * Name: esp32c3_gpioirqdisable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_GPIO_IRQ +void esp32c3_gpioirqdisable(int irq) +{ + uintptr_t regaddr; + uint32_t regval; + int pin; + + DEBUGASSERT(irq >= ESP32C3_FIRST_GPIOIRQ && irq <= ESP32C3_LAST_GPIOIRQ); + + /* Convert the IRQ number to a pin number */ + + pin = ESP32C3_IRQ2PIN(irq); + + /* Get the address of the GPIO PIN register for this pin */ + + up_disable_irq(ESP32C3_IRQ_GPIO); + + regaddr = GPIO_REG(pin); + regval = getreg32(regaddr); + regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M); + putreg32(regval, regaddr); + + up_enable_irq(ESP32C3_IRQ_GPIO); +} +#endif + diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_gpio.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_gpio.h new file mode 100644 index 0000000000000..dc99f0a6911fa --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_gpio.h @@ -0,0 +1,225 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/esp32c3_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_GPIO_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */ +#define MATRIX_DETACH_IN_LOW_PIN 0x30 /* Detach non-inverted INPUT signal */ +#define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */ + +/* Bit-encoded input to esp32c3_configgpio() ********************************/ + +/* Encoded pin attributes used with esp32c3_configgpio() + * + * 8 7 6 5 4 3 2 1 0 + * -- -- -- -- -- -- -- -- -- + * FN FN FN OD PD PU F O I + */ + +#define PINMODE_SHIFT 0 +#define PINMODE_MASK (7 << PINMODE_SHIFT) +# define INPUT (1 << 0) +# define OUTPUT (1 << 1) +# define FUNCTION (1 << 2) + +#define PULLUP (1 << 3) +#define PULLDOWN (1 << 4) +#define OPEN_DRAIN (1 << 5) +#define FUNCTION_SHIFT 6 +#define FUNCTION_MASK (7 << FUNCTION_SHIFT) +# define FUNCTION_0 (1 << FUNCTION_SHIFT) +# define FUNCTION_1 (2 << FUNCTION_SHIFT) +# define FUNCTION_2 (3 << FUNCTION_SHIFT) +# define FUNCTION_3 (4 << FUNCTION_SHIFT) +# define FUNCTION_4 (5 << FUNCTION_SHIFT) + +#define INPUT_PULLUP (INPUT | PULLUP) +#define INPUT_PULLDOWN (INPUT | PULLDOWN) +#define OUTPUT_OPEN_DRAIN (OUTPUT | OPEN_DRAIN) +#define INPUT_FUNCTION (INPUT | FUNCTION) +# define INPUT_FUNCTION_0 (INPUT_FUNCTION | FUNCTION_0) +# define INPUT_FUNCTION_1 (INPUT_FUNCTION | FUNCTION_1) +# define INPUT_FUNCTION_2 (INPUT_FUNCTION | FUNCTION_2) +# define INPUT_FUNCTION_3 (INPUT_FUNCTION | FUNCTION_3) +# define INPUT_FUNCTION_4 (INPUT_FUNCTION | FUNCTION_4) +#define OUTPUT_FUNCTION (OUTPUT | FUNCTION) +# define OUTPUT_FUNCTION_0 (OUTPUT_FUNCTION | FUNCTION_0) +# define OUTPUT_FUNCTION_1 (OUTPUT_FUNCTION | FUNCTION_1) +# define OUTPUT_FUNCTION_2 (OUTPUT_FUNCTION | FUNCTION_2) +# define OUTPUT_FUNCTION_3 (OUTPUT_FUNCTION | FUNCTION_3) +# define OUTPUT_FUNCTION_4 (OUTPUT_FUNCTION | FUNCTION_4) + +/* Interrupt type used with esp32c3_gpioirqenable() */ + +#define DISABLED 0x00 +#define RISING 0x01 +#define FALLING 0x02 +#define CHANGE 0x03 +#define ONLOW 0x04 +#define ONHIGH 0x05 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* Must be big enough to hold the above encodings */ + +typedef uint16_t gpio_pinattr_t; +typedef uint8_t gpio_intrtype_t; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_configgpio + * + * Description: + * Configure a GPIO pin based on encoded pin attributes. + * + ****************************************************************************/ + +int esp32c3_configgpio(int pin, gpio_pinattr_t attr); + +/**************************************************************************** + * Name: esp32c3_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void esp32c3_gpiowrite(int pin, bool value); + +/**************************************************************************** + * Name: esp32c3_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool esp32c3_gpioread(int pin); + +/**************************************************************************** + * Name: esp32c3_gpio_matrix_in + * + * Description: + * Set gpio input to a signal + * NOTE: one gpio can input to several signals + * If signal_idx == 0x30, cancel input to the signal, input 0 to signal + * If signal_idx == 0x38, cancel input to the signal, input 1 to signal + * + ****************************************************************************/ + +void esp32c3_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); + +/**************************************************************************** + * Name: esp32c3_gpio_matrix_out + * + * Description: + * Set signal output to gpio + * NOTE: one signal can output to several gpios + * If signal_idx == 0x100, cancel output put to the gpio + * + ****************************************************************************/ + +void esp32c3_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, + bool out_inv, bool oen_inv); + +/**************************************************************************** + * Name: esp32c3_gpioirqinitialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_GPIO_IRQ +void esp32c3_gpioirqinitialize(void); +#else +# define esp32c3_gpioirqinitialize() +#endif + +/**************************************************************************** + * Name: esp32c3_gpioirqenable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_GPIO_IRQ +void esp32c3_gpioirqenable(int irq, gpio_intrtype_t intrtype); +#else +# define esp32c3_gpioirqenable(irq,intrtype) +#endif + +/**************************************************************************** + * Name: esp32c3_gpioirqdisable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_GPIO_IRQ +void esp32c3_gpioirqdisable(int irq); +#else +# define esp32c3_gpioirqdisable(irq) +#endif + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_GPIO_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_head.S b/arch/risc-v/src/esp32c3-legacy/esp32c3_head.S similarity index 92% rename from arch/risc-v/src/esp32c3/esp32c3_head.S rename to arch/risc-v/src/esp32c3-legacy/esp32c3_head.S index 457df34ab441d..14323dec1d28c 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_head.S +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_head.S @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_head.S + * arch/risc-v/src/esp32c3-legacy/esp32c3_head.S * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -25,6 +25,7 @@ #include #include +#include "riscv_internal.h" #include "chip.h" /**************************************************************************** @@ -49,8 +50,9 @@ __start: /* Set stack pointer to the idle thread stack */ - lui sp, %hi(ESP32C3_IDLESTACK_TOP) - addi sp, sp, %lo(ESP32C3_IDLESTACK_TOP) + la sp, _ebss + li t0, SMP_STACK_SIZE + add sp, sp, t0 /* Set gp pointer */ @@ -58,7 +60,7 @@ __start: /* Disable all interrupts (i.e. timer, external) in mstatus */ - csrw mstatus, zero + csrw CSR_MSTATUS, zero .option pop @@ -66,7 +68,7 @@ __start: lui t0, %hi(_vector_table) addi t0, t0, %lo(_vector_table) - csrw mtvec, t0 + csrw CSR_MTVEC, t0 /* Jump to __esp32c3_start */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_i2c.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_i2c.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_i2c.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_i2c.c index 49e6931da61e1..559fd43a0d0ca 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_i2c.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_i2c.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_i2c.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_i2c.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -1476,7 +1476,7 @@ struct i2c_master_s *esp32c3_i2cbus_initialize(int port) nxmutex_unlock(&priv->lock); i2cinfo("Returning previously initialized I2C bus. " - "Handler: %" PRIxPTR "\n", (uintptr_t)priv); + "Handler: %p\n", priv); return (struct i2c_master_s *)priv; } @@ -1525,7 +1525,7 @@ struct i2c_master_s *esp32c3_i2cbus_initialize(int port) esp32c3_i2c_init(priv); nxmutex_unlock(&priv->lock); - i2cinfo("I2C bus initialized! Handler: %" PRIxPTR "\n", (uintptr_t)priv); + i2cinfo("I2C bus initialized! Handler: %p\n", priv); return (struct i2c_master_s *)priv; } diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_i2c.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_i2c.h new file mode 100644 index 0000000000000..9b096dbb7f10b --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_i2c.h @@ -0,0 +1,94 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/esp32c3_i2c.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_I2C_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_I2C_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_i2cbus_initialize + * + * Description: + * Initialize the selected I2C port. And return a pointer to an unique + * instance of struct i2c_master_s. This function may be called to obtain + * multiple instances of the interface, each of which may be set up with a + * different frequency and slave address. + * + * Input Parameters: + * port - Port number of the I2C interface to be initialized. + * + * Returned Value: + * Pointer to valid I2C device structure is returned on success. + * A NULL pointer is returned on failure. + * + ****************************************************************************/ + +struct i2c_master_s *esp32c3_i2cbus_initialize(int port); + +/**************************************************************************** + * Name: esp32c3_i2cbus_uninitialize + * + * Description: + * De-initialize the selected I2C port and power down the device. + * + * Input Parameters: + * dev - Device structure as returned by + * esp32c3_i2cbus_initialize() + * + * Returned Value: + * OK is returned on success. ERROR is returned when internal reference + * count mismatches or dev points to invalid hardware device. + * + ****************************************************************************/ + +int esp32c3_i2cbus_uninitialize(struct i2c_master_s *dev); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_I2C_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_ice40.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_ice40.c new file mode 100644 index 0000000000000..823c4e15d8eb9 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_ice40.c @@ -0,0 +1,214 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/esp32c3_ice40.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "esp32c3_spi.h" +#include "hardware/esp32c3_spi.h" + +#include "hardware/esp32c3_gpio.h" +#include "hardware/esp32c3_gpio_sigmap.h" + +#include "esp32c3_ice40.h" + +#include "esp32c3_gpio.h" + +#include + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void ice40_reset(struct ice40_dev_s *dev, bool reset); +static void ice40_select(struct ice40_dev_s *dev, bool select); +static bool ice40_get_status(struct ice40_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct ice40_ops_s ice40_ops = +{ + .reset = ice40_reset, + .select = ice40_select, + .get_status = ice40_get_status, +}; + +struct esp32c3_ice40_dev_s +{ + struct ice40_dev_s base; + uint16_t cdone_gpio; + uint16_t crst_gpio; + uint16_t cs_gpio; +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ice40_reset + * + * Description: + * Reset ICE40 FPGA + * + * Input Parameters: + * reset - true to reset, false to release reset (inverse logic, active low) + * + ****************************************************************************/ + +static void +ice40_reset(struct ice40_dev_s *dev, bool reset) +{ + struct esp32c3_ice40_dev_s *priv + = container_of (dev, struct esp32c3_ice40_dev_s, base); + esp32c3_gpiowrite(priv->crst_gpio, !reset); +} + +/**************************************************************************** + * Name: ice40_select + * + * Description: + * Select ICE40 FPGA + * + * Input Parameters: + * select - true to select, false to deselect (inverse logic, active low) + * + ****************************************************************************/ + +static void +ice40_select(struct ice40_dev_s *dev, bool select) +{ + struct esp32c3_ice40_dev_s *priv + = container_of (dev, struct esp32c3_ice40_dev_s, base); + esp32c3_gpiowrite(priv->cs_gpio, !select); +} + +/**************************************************************************** + * Name: ice40_get_status + * + * Description: + * Get ICE40 FPGA status via CDONE pin. Important to know if the FPGA is + * programmed and ready to use. + * + * Returned Value: + * true if the FPGA is programmed and ready to use, false otherwise. + * + ****************************************************************************/ + +static bool +ice40_get_status(struct ice40_dev_s *dev) +{ + struct esp32c3_ice40_dev_s *priv + = container_of(dev, struct esp32c3_ice40_dev_s, base); + return esp32c3_gpioread (priv->cdone_gpio); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_ice40_initialize + * + * Description: + * Initialize ICE40 FPGA GPIOs and SPI. + * + * Input Parameters: + * + * + ****************************************************************************/ + +FAR struct ice40_dev_s * +esp32c3_ice40_initialize(const uint16_t cdone_gpio, + const uint16_t crst_gpio, + const uint16_t cs_gpio, + const uint16_t spi_port) +{ + struct esp32c3_ice40_dev_s *ice40_ptr; + + ice40_ptr = kmm_malloc(sizeof(struct esp32c3_ice40_dev_s)); + if (ice40_ptr == NULL) + { + spierr("ERROR: Failed to allocate memory for ICE40 driver\n"); + return NULL; + } + + memset(ice40_ptr, 0, sizeof (struct esp32c3_ice40_dev_s)); + + ice40_ptr->base.ops = &ice40_ops; + + /* Configure GPIO pins */ + + DEBUGASSERT(0 <= cdone_gpio && cdone_gpio < 32); + DEBUGASSERT(0 <= crst_gpio && crst_gpio < 32); + DEBUGASSERT(0 <= cs_gpio && cs_gpio < 32); + DEBUGASSERT(0 <= spi_port && spi_port < 3); + + esp32c3_gpio_matrix_out(cdone_gpio, SIG_GPIO_OUT_IDX, 0, 0); + esp32c3_gpio_matrix_out(crst_gpio, SIG_GPIO_OUT_IDX, 0, 0); + esp32c3_gpio_matrix_out(cs_gpio, SIG_GPIO_OUT_IDX, 0, 0); + + esp32c3_configgpio(cdone_gpio, INPUT_FUNCTION_1 | PULLDOWN); + esp32c3_configgpio(crst_gpio, OUTPUT_FUNCTION_1); + esp32c3_configgpio(cs_gpio, OUTPUT_FUNCTION_1); + + esp32c3_gpiowrite(crst_gpio, 1); + esp32c3_gpiowrite(cs_gpio, 1); + + ice40_ptr->cdone_gpio = cdone_gpio; + ice40_ptr->crst_gpio = crst_gpio; + ice40_ptr->cs_gpio = cs_gpio; + + /* Configure SPI */ + + ice40_ptr->base.spi = esp32c3_spibus_initialize(spi_port); + if (ice40_ptr->base.spi == NULL) + { + spierr("ERROR: Failed to initialize SPI port %d\n", + ice40_ptr->base.spi); + return NULL; + } + + return &ice40_ptr->base; +} diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_ice40.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_ice40.h new file mode 100644 index 0000000000000..1669fe7076729 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_ice40.h @@ -0,0 +1,91 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/esp32c3_ice40.h + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_ICE40_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_ICE40_H + +/**************************************************************************** + * Included Files + * *************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "hardware/esp32c3_gpio.h" +#include "hardware/esp32c3_gpio_sigmap.h" + +#include "esp32c3_gpio.h" + +#ifndef __ASSEMBLY__ +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_ice40_initialize + * + * Description: + * Initialize ICE40 FPGA GPIOs and SPI interface. + * + * Input Parameters: + * cdone_gpio - GPIO pin connected to the CDONE pin of the ICE40 FPGA. + * crst_gpio - GPIO pin connected to the CRST pin of the ICE40 FPGA. + * cs_gpio - GPIO pin connected to the CS pin of the ICE40 FPGA. + * spi_port - SPI port number to use for communication with the ICE40 FPGA. + * + * Returned Value: + * A reference to the initialized ICE40 FPGA driver instance. + * NULL in case of failure. + * + ****************************************************************************/ + + struct ice40_dev_s *esp32c3_ice40_initialize(const uint16_t cdone_gpio, + const uint16_t crst_gpio, + const uint16_t cs_gpio, + const uint16_t spi_port); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_ICE40_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_idle.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_idle.c similarity index 97% rename from arch/risc-v/src/esp32c3/esp32c3_idle.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_idle.c index b78bf30399423..5a7fa1c3a5762 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_idle.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_idle.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_idle.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_idle.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -200,7 +200,6 @@ static void up_idlepm(void) esp32c3_pmsleep(CONFIG_PM_SLEEP_WAKEUP_SEC * 1000000 + CONFIG_PM_SLEEP_WAKEUP_NSEC / 1000); } - break; default: break; @@ -208,13 +207,6 @@ static void up_idlepm(void) } else { - if (oldstate == PM_NORMAL) - { - /* Relax normal operation */ - - pm_relax(PM_IDLE_DOMAIN, PM_NORMAL); - } - #ifdef CONFIG_WATCHDOG /* Announce the power management state change to feed watchdog */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_irq.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_irq.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_irq.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_irq.c index 888f6b35fb4f8..ef8688902da7e 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_irq.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_irq.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_irq.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_irq.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -702,6 +702,6 @@ irqstate_t up_irq_enable(void) /* Read mstatus & set machine interrupt enable (MIE) in mstatus */ - flags = READ_AND_SET_CSR(mstatus, MSTATUS_MIE); + flags = READ_AND_SET_CSR(CSR_MSTATUS, MSTATUS_MIE); return flags; } diff --git a/arch/risc-v/src/esp32c3/esp32c3_irq.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_irq.h similarity index 95% rename from arch/risc-v/src/esp32c3/esp32c3_irq.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_irq.h index 3c31367ecc763..2e38073d3ae16 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_irq.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_irq.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_irq.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_irq.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_IRQ_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_IRQ_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_IRQ_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_IRQ_H /**************************************************************************** * Included Files @@ -143,4 +143,4 @@ void esp32c3_teardown_irq(int periphid, int cpuint); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_IRQ_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_IRQ_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_ledc.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_ledc.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_ledc.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_ledc.c index 74011eb820f11..c62b242fe13e6 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_ledc.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_ledc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_ledc.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_ledc.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -419,7 +419,7 @@ static void setup_timer(struct esp32c3_ledc_s *priv) prescaler = pwmclk * 256 / reload / priv->frequency; - pwminfo("PWM timer%" PRIu8 " frequency=%0.4f reload=%" PRIu32 " shift=%" \ + pwminfo("PWM timer%" PRIu8 " frequency=%0.4f reload=%" PRIu32 " shift=%" PRIu32 " prescaler=%0.4f\n", priv->num, (float)pwmclk / reload / ((float)prescaler / 256), reload, shift, (float)prescaler / 256); diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_ledc.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_ledc.h new file mode 100644 index 0000000000000..0046a22a8f75d --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_ledc.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/esp32c3_ledc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_LEDC_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_LEDC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_ledc_init + * + * Description: + * Initialize one LEDC timer for use with the upper_level PWM driver. + * + * Input Parameters: + * timer - A number identifying the timer use. + * + * Returned Value: + * On success, a pointer to the ESP32-C3 LEDC lower half PWM driver is + * returned. NULL is returned on any failure. + * + ****************************************************************************/ + +struct pwm_lowerhalf_s *esp32c3_ledc_init(int timer); + +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_LEDC_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_libc_stubs.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_libc_stubs.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_libc_stubs.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_libc_stubs.c index a3f0901f8e62c..0bd7866bbc429 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_libc_stubs.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_libc_stubs.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_libc_stubs.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_libc_stubs.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_lowputc.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_lowputc.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_lowputc.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_lowputc.c index 5fc1d6a546175..d5a36999b506d 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_lowputc.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_lowputc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_lowputc.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_lowputc.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -710,7 +710,7 @@ void esp32c3_lowputc_disable_all_uart_int(const struct esp32c3_uart_s *priv, { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (current_status != NULL) { @@ -727,7 +727,7 @@ void esp32c3_lowputc_disable_all_uart_int(const struct esp32c3_uart_s *priv, putreg32(0xffffffff, UART_INT_CLR_REG(priv->id)); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/risc-v/src/esp32c3/esp32c3_lowputc.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_lowputc.h similarity index 98% rename from arch/risc-v/src/esp32c3/esp32c3_lowputc.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_lowputc.h index ac0f58b1c1638..232e46664b2b1 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_lowputc.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_lowputc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_lowputc.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_lowputc.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_LOWPUTC_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_LOWPUTC_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_LOWPUTC_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_LOWPUTC_H /**************************************************************************** * Included Files @@ -489,4 +489,4 @@ void esp32c3_lowputc_restore_pins(const struct esp32c3_uart_s *priv); void esp32c3_lowsetup(void); -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_LOWPUTC_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_LOWPUTC_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_memorymap.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_memorymap.h new file mode 100644 index 0000000000000..9893d1d4667d2 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_memorymap.h @@ -0,0 +1,34 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/esp32c3_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_MEMORYMAP_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "riscv_common_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_MEMORYMAP_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_oneshot.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_oneshot.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_oneshot.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_oneshot.c index 25fdc13133f55..a499d42ae9efb 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_oneshot.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_oneshot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_oneshot.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_oneshot.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_oneshot.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_oneshot.h similarity index 97% rename from arch/risc-v/src/esp32c3/esp32c3_oneshot.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_oneshot.h index 3d5fe839ca815..6bba13c0575fd 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_oneshot.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_oneshot.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_oneshot.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_oneshot.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ONESHOT_H -#define __ARCH_RISCV_SRC_ESP32C3_ONESHOT_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ONESHOT_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ONESHOT_H /**************************************************************************** * Included Files @@ -201,4 +201,4 @@ int esp32c3_oneshot_current(struct esp32c3_oneshot_s *oneshot, #endif #endif /* CONFIG_ESP32C3_ONESHOT */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ONESHOT_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ONESHOT_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_oneshot_lowerhalf.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_oneshot_lowerhalf.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_oneshot_lowerhalf.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_oneshot_lowerhalf.c index dced59ae58ebf..ae400ca6d090a 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_oneshot_lowerhalf.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_oneshot_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_oneshot_lowerhalf.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_oneshot_lowerhalf.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_partition.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_partition.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_partition.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_partition.c index ad5e48c4fac04..338db2091c76e 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_partition.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_partition.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_partition.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_partition.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_partition.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_partition.h similarity index 89% rename from arch/risc-v/src/esp32c3/esp32c3_partition.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_partition.h index 033411303b0ec..de9413b163b92 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_partition.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_partition.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_partition.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_partition.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_PARTITION_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_PARTITION_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_PARTITION_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_PARTITION_H /**************************************************************************** * Included Files @@ -69,4 +69,4 @@ int esp32c3_partition_init(void); #undef EXTERN #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_PARTITION_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_PARTITION_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_perf.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_perf.c similarity index 98% rename from arch/risc-v/src/esp32c3/esp32c3_perf.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_perf.c index 5e187b4ac3e4d..0eb5e9d5126c5 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_perf.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_perf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_perf.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_perf.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_pm.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_pm.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_pm.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_pm.c index 3c9ce4e879c0c..7c578a49c0803 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_pm.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_pm.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_pm.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_pm.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_pm.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_pm.h similarity index 97% rename from arch/risc-v/src/esp32c3/esp32c3_pm.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_pm.h index 28dcec273c2b6..0b7eb87d35a7c 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_pm.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_pm.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_pm.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_pm.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -22,8 +22,8 @@ * Included Files ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_PM_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_PM_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_PM_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_PM_H /**************************************************************************** * Included Files @@ -281,4 +281,4 @@ int esp32c3_pm_unregister_skip_sleep_callback(skip_light_sleep_cb_t cb); #undef EXTERN #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_PM_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_PM_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_pminitialize.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_pminitialize.c similarity index 96% rename from arch/risc-v/src/esp32c3/esp32c3_pminitialize.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_pminitialize.c index 68fffcb8bb824..274b1cad7fec2 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_pminitialize.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_pminitialize.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_pminitialize.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_pminitialize.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_region.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_region.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_region.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_region.c index ebad5821c14e6..cf766993d4f27 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_region.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_region.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_region.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_region.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_region.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_region.h similarity index 90% rename from arch/risc-v/src/esp32c3/esp32c3_region.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_region.h index a81e1b5ed4b00..0528b7e9ffe7a 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_region.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_region.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_region.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_region.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_REGION_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_REGION_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_REGION_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_REGION_H /**************************************************************************** * Included Files @@ -68,4 +68,4 @@ void esp32c3_region_protection(void); #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_REGION_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_REGION_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_resetcause.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_resetcause.c similarity index 97% rename from arch/risc-v/src/esp32c3/esp32c3_resetcause.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_resetcause.c index 00ede72ff48c9..4d61d08b7b597 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_resetcause.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_resetcause.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_resetcause.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_resetcause.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_resetcause.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_resetcause.h similarity index 97% rename from arch/risc-v/src/esp32c3/esp32c3_resetcause.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_resetcause.h index abc9ae908a28f..fbbcc65005edb 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_resetcause.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_resetcause.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_resetcause.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_resetcause.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_rng.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_rng.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_rng.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_rng.c index f0e59e41b630f..e7d0d0f571fc6 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rng.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_rng.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_rng.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_rng.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_rsa.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_rsa.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_rsa.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_rsa.c index 965b610b213d1..a9d2057b47544 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rsa.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_rsa.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_rsa.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_rsa.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_rsa.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_rsa.h new file mode 100644 index 0000000000000..22e4c0a77ea32 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_rsa.h @@ -0,0 +1,511 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/esp32c3_rsa.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_RSA_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_RSA_H + +#include +#include +#include "esp32c3_bignum.h" + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Pre-processor Macros + ****************************************************************************/ + +/* RSA Error codes */ + +#define ESP32C3_ERR_RSA_BAD_INPUT_DATA -0x4080 /* Bad input parameters to function. */ +#define ESP32C3_ERR_RSA_INVALID_PADDING -0x4100 /* Input data contains invalid padding and is rejected. */ +#define ESP32C3_ERR_RSA_KEY_GEN_FAILED -0x4180 /* Something failed during generation of a key. */ +#define ESP32C3_ERR_RSA_KEY_CHECK_FAILED -0x4200 /* Key failed to pass the validity check of the library. */ +#define ESP32C3_ERR_RSA_PUBLIC_FAILED -0x4280 /* The public key operation failed. */ +#define ESP32C3_ERR_RSA_PRIVATE_FAILED -0x4300 /* The private key operation failed. */ +#define ESP32C3_ERR_RSA_VERIFY_FAILED -0x4380 /* The PKCS#1 verification failed. */ +#define ESP32C3_ERR_RSA_OUTPUT_TOO_LARGE -0x4400 /* The output buffer for decryption is not large enough. */ +#define ESP32C3_ERR_RSA_RNG_FAILED -0x4480 /* The random generator failed to generate non-zeros. */ + +/* RSA constants */ + +#define ESP32C3_RSA_PUBLIC 0 /* Request private key operation. */ +#define ESP32C3_RSA_PRIVATE 1 /* Request public key operation. */ + +#define ESP32C3_RSA_PKCS_V15 0 /* Use PKCS#1 v1.5 encoding. */ +#define ESP32C3_RSA_PKCS_V21 1 /* Use PKCS#1 v2.1 encoding. */ + +#define ESP32C3_RSA_SIGN 1 /* Identifier for RSA signature operations. */ +#define ESP32C3_RSA_CRYPT 2 /* Identifier for RSA encryption and decryption operations. */ + +#define ESP32C3_RSA_SALT_LEN_ANY -1 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* The RSA context structure. */ + +struct esp32c3_rsa_context_s +{ + int ver; /* Always 0 */ + size_t len; /* The size of \p N in Bytes */ + + struct esp32c3_mpi_s N; /* The public modulus */ + struct esp32c3_mpi_s E; /* The public exponent */ + + struct esp32c3_mpi_s D; /* The private exponent */ + struct esp32c3_mpi_s P; /* The first prime factor */ + struct esp32c3_mpi_s Q; /* The second prime factor */ + + struct esp32c3_mpi_s DP; /* D % (P - 1) */ + struct esp32c3_mpi_s DQ; /* D % (Q - 1) */ + struct esp32c3_mpi_s QP; /* 1 / (Q % P) */ + + struct esp32c3_mpi_s RN; /* cached R^2 mod N */ + + struct esp32c3_mpi_s RP; /* cached R^2 mod P */ + struct esp32c3_mpi_s RQ; /* cached R^2 mod Q */ + + struct esp32c3_mpi_s VI; /* The cached blinding value */ + struct esp32c3_mpi_s VF; /* The cached un-blinding value */ + + int padding; /* Selects padding mode */ + int hash_id; /* Hash identifier */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_rsa_init + * + * Description: + * Initializes an RSA context + * + * Input Parameters: + * ctx - The RSA context to initialize + * padding - The padding mode to use + * hash_id - The hash identifier of + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_rsa_init(struct esp32c3_rsa_context_s *ctx, + int padding, + int hash_id); + +/**************************************************************************** + * Name: esp32c3_rsa_import + * + * Description: + * Imports a set of core parameters into an RSA context. + * + * Input Parameters: + * ctx - The initialized RSA context to store the parameters in + * N - The RSA modulus + * P - The first prime factor of \p N + * Q - The second prime factor of \p N + * D - The private exponent + * E - The public exponent + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_import(struct esp32c3_rsa_context_s *ctx, + const struct esp32c3_mpi_s *N, + const struct esp32c3_mpi_s *P, + const struct esp32c3_mpi_s *Q, + const struct esp32c3_mpi_s *D, + const struct esp32c3_mpi_s *E); + +/**************************************************************************** + * Name: esp32c3_rsa_import_raw + * + * Description: + * Imports core RSA parameters into an RSA context. + * + * Input Parameters: + * ctx - The initialized RSA context to store the parameters in + * N - The RSA modulus + * NL - The Byte length of \p N + * P - The first prime factor of \p N + * PL - The Byte length of \p P + * Q - The second prime factor of \p N + * QL - The Byte length of \p Q + * D - The private exponent + * DL - The Byte length of \p D + * E - The public exponent + * EL - The Byte length of \p E + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_import_raw(struct esp32c3_rsa_context_s *ctx, + unsigned char const *N, size_t NL, + unsigned char const *P, size_t PL, + unsigned char const *Q, size_t QL, + unsigned char const *D, size_t DL, + unsigned char const *E, size_t EL); + +/**************************************************************************** + * Name: esp32c3_rsa_complete + * + * Description: + * Completes an RSA context from a set of imported core parameters. + * + * Input Parameters: + * ctx - The initialized RSA context holding imported parameters + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_complete(struct esp32c3_rsa_context_s *ctx); + +/**************************************************************************** + * Name: esp32c3_rsa_export + * + * Description: + * Exports the core parameters of an RSA key. + * + * Input Parameters: + * ctx - The initialized RSA context + * N - The MPI to hold the RSA modulus + * P - The MPI to hold the first prime factor of \p N + * Q - The MPI to hold the second prime factor of \p N + * D - The MPI to hold the private exponent + * E - The MPI to hold the public exponent + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_export(const struct esp32c3_rsa_context_s *ctx, + struct esp32c3_mpi_s *N, + struct esp32c3_mpi_s *P, + struct esp32c3_mpi_s *Q, + struct esp32c3_mpi_s *D, + struct esp32c3_mpi_s *E); + +/**************************************************************************** + * Name: esp32c3_rsa_export_raw + * + * Description: + * Eexports core parameters of an RSA key in raw big-endian binary format. + * + * Input Parameters: + * ctx - The initialized RSA context + * N - The Byte array to store the RSA modulus + * NL - The size of the buffer for the modulus + * P - The Byte array to hold the first prime factor of \p N + * PL - The size of the buffer for the first prime factor + * Q - The Byte array to hold the second prime factor of \p N + * QL - The size of the buffer for the second prime factor + * D - The Byte array to hold the private exponent + * DL - The size of the buffer for the private exponent + * E - The Byte array to hold the public exponent + * EL - The size of the buffer for the public exponent + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_export_raw(const struct esp32c3_rsa_context_s *ctx, + unsigned char *N, size_t NL, + unsigned char *P, size_t PL, + unsigned char *Q, size_t QL, + unsigned char *D, size_t DL, + unsigned char *E, size_t EL); + +/**************************************************************************** + * Name: esp32c3_rsa_export_crt + * + * Description: + * Exports CRT parameters of a private RSA key. + * + * Input Parameters: + * ctx - The initialized RSA context + * DP - The MPI to hold \c D modulo `P-1` + * DQ - The MPI to hold \c D modulo `Q-1` + * QP - The MPI to hold modular inverse of \c Q modulo \c P + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_export_crt(const struct esp32c3_rsa_context_s *ctx, + struct esp32c3_mpi_s *DP, + struct esp32c3_mpi_s *DQ, + struct esp32c3_mpi_s *QP); + +/**************************************************************************** + * Name: esp32c3_rsa_set_padding + * + * Description: + * Sets padding for an already initialized RSA context. + * + * Input Parameters: + * ctx - The initialized RSA context to be configured + * padding - The padding mode to use + * hash_id - The hash identifier + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_rsa_set_padding(struct esp32c3_rsa_context_s *ctx, + int padding, int hash_id); + +/**************************************************************************** + * Name: esp32c3_rsa_get_len + * + * Description: + * Exports CRT parameters of a private RSA key. + * + * Input Parameters: + * ctx - The initialized RSA context + * + * Returned Value: + * length of the RSA modulus in Bytes. + * + ****************************************************************************/ + +size_t esp32c3_rsa_get_len(const struct esp32c3_rsa_context_s *ctx); + +/**************************************************************************** + * Name: esp32c3_rsa_check_pubkey + * + * Description: + * checks if a context contains at least an RSA public key.. + * + * Input Parameters: + * ctx - The initialized RSA context to check + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_check_pubkey(const struct esp32c3_rsa_context_s *ctx); + +/**************************************************************************** + * Name: esp32c3_rsa_check_privkey + * + * Description: + * Checks if a context contains at least an RSA private key + * and perform basic consistency checks. + * + * Input Parameters: + * ctx - The initialized RSA context to check + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_check_privkey(const struct esp32c3_rsa_context_s *ctx); + +/**************************************************************************** + * Name: esp32c3_rsa_check_pub_priv + * + * Description: + * Checks a public-private RSA key pair. It checks each of the contexts, + * and makes sure they match. + * + * Input Parameters: + * pub - The initialized RSA context holding the public key + * prv - The initialized RSA context holding the private key + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_check_pub_priv(const struct esp32c3_rsa_context_s *pub, + const struct esp32c3_rsa_context_s *prv); + +/**************************************************************************** + * Name: esp32c3_rsa_public + * + * Description: + * Performs an RSA public key operation. + * + * Input Parameters: + * ctx - The initialized RSA context to use + * input - The input buffer + * output - The output buffer + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_public(struct esp32c3_rsa_context_s *ctx, + const unsigned char *input, + unsigned char *output); + +/**************************************************************************** + * Name: esp32c3_rsa_private + * + * Description: + * Performs an RSA private key operation. + * + * Input Parameters: + * ctx - The initialized RSA context to use + * f_rng - The RNG function + * p_rng - The RNG context to pass to \p f_rng + * input - The input buffer + * output - The output buffer + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_private(struct esp32c3_rsa_context_s *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + const unsigned char *input, + unsigned char *output); + +/**************************************************************************** + * Name: esp32c3_rsa_encrypt + * + * Description: + * Adds the message padding, then performs an RSA operation. It is the + * generic wrapper for performing a PKCS#1 encryption operation using the + * \p mode from the context. + * + * Input Parameters: + * ctx - The initialized RSA context to use + * f_rng - The RNG to use + * p_rng - The RNG context to be passed to \p f_rng + * mode - The mode of operation + * ilen - The length of the plaintext in Bytes + * input - The input data to encrypt + * output - The output buffer + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_encrypt(struct esp32c3_rsa_context_s *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t ilen, + const unsigned char *input, + unsigned char *output); + +/**************************************************************************** + * Name: esp32c3_rsa_decrypt + * + * Description: + * Performs an RSA operation, then removes the message padding. + * + * Input Parameters: + * ctx - The initialized RSA context to use + * f_rng - The RNG function + * p_rng - The RNG context to be passed to \p f_rng + * mode - The mode of operation + * olen - The point which to store the length of the plaintext + * input - The ciphertext buffer + * output - The buffer used to hold the plaintext + * output_max_len - The length in Bytes of the output buffer \p output + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_decrypt(struct esp32c3_rsa_context_s *ctx, + int (*f_rng)(void *, unsigned char *, size_t), + void *p_rng, + int mode, size_t *olen, + const unsigned char *input, + unsigned char *output, + size_t output_max_len); + +/**************************************************************************** + * Name: esp32c3_rsa_copy + * + * Description: + * Copies the components of an RSA context. + * + * Input Parameters: + * dst - The destination context + * src - The source context + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32c3_rsa_copy(struct esp32c3_rsa_context_s *dst, + const struct esp32c3_rsa_context_s *src); + +/**************************************************************************** + * Name: esp32c3_rsa_free + * + * Description: + * Frees the components of an RSA key. + * + * Input Parameters: + * ctx - The RSA context to free + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_rsa_free(struct esp32c3_rsa_context_s *ctx); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_RSA_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_rt_timer.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_rt_timer.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_rt_timer.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_rt_timer.c index 5880922492f02..c5bfa8cd98759 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rt_timer.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_rt_timer.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_rt_timer.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_rt_timer.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -33,6 +33,7 @@ #include #include +#include #include #include #include @@ -339,7 +340,7 @@ static int rt_timer_thread(int argc, char *argv[]) if (ret) { tmrerr("ERROR: Wait toutsem error=%d\n", ret); - assert(0); + ASSERT(0); } flags = enter_critical_section(); diff --git a/arch/risc-v/src/esp32c3/esp32c3_rt_timer.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_rt_timer.h similarity index 96% rename from arch/risc-v/src/esp32c3/esp32c3_rt_timer.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_rt_timer.h index 86cb10897e6c4..b54c7237a110a 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rt_timer.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_rt_timer.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_rt_timer.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_rt_timer.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RT_TIMER_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RT_TIMER_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_RT_TIMER_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_RT_TIMER_H /**************************************************************************** * Included Files @@ -241,4 +241,4 @@ void esp32c3_rt_timer_deinit(void); #endif #undef EXTERN -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RT_TIMER_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_RT_TIMER_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_rtc.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_rtc.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.c index af881e75f704b..8019e9a0ac9f6 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rtc.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_rtc.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_rtc.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.h similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_rtc.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.h index d26fbddbf770c..203b290237a9f 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rtc.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_rtc.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_rtc.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -22,8 +22,8 @@ * Included Files ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTC_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTC_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_RTC_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_RTC_H /**************************************************************************** * Included Files @@ -734,4 +734,4 @@ int up_rtc_timer_init(void); #undef EXTERN #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTC_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_RTC_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_rtc_gpio.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_gpio.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_rtc_gpio.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_gpio.c index a73209999ef87..d8c419303eb90 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rtc_gpio.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_rtc_gpio.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_gpio.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_rtc_gpio.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_gpio.h similarity index 94% rename from arch/risc-v/src/esp32c3/esp32c3_rtc_gpio.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_gpio.h index cccdfc216c168..7eb8a2f66741a 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rtc_gpio.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_gpio.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_rtc_gpio.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_gpio.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTC_GPIO_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTC_GPIO_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_RTC_GPIO_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_RTC_GPIO_H /**************************************************************************** * Included Files @@ -146,4 +146,4 @@ void esp32c3_rtcioirqdisable(int irq); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTC_GPIO_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_RTC_GPIO_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_rtc_lowerhalf.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_lowerhalf.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_rtc_lowerhalf.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_lowerhalf.c index 017c4a91a7e84..e962490f11075 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rtc_lowerhalf.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_rtc_lowerhalf.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_lowerhalf.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_rtc_lowerhalf.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_lowerhalf.h similarity index 88% rename from arch/risc-v/src/esp32c3/esp32c3_rtc_lowerhalf.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_lowerhalf.h index 452570d0e5454..8c42f967ce594 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rtc_lowerhalf.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_lowerhalf.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_rtc_lowerhalf.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_rtc_lowerhalf.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTC_LOWERHALF_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTC_LOWERHALF_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_RTC_LOWERHALF_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_RTC_LOWERHALF_H /**************************************************************************** * Included Files @@ -53,4 +53,4 @@ int esp32c3_rtc_driverinit(void); #endif /* CONFIG_RTC_DRIVER */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTC_LOWERHALF_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_RTC_LOWERHALF_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_rtcheap.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtcheap.c similarity index 98% rename from arch/risc-v/src/esp32c3/esp32c3_rtcheap.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_rtcheap.c index 7db37cd6cb197..c7ada6ed7699b 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rtcheap.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtcheap.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_rtcheap.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_rtcheap.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -54,7 +54,7 @@ void esp32c3_rtcheap_initialize(void) /* These values come from the linker scripts * (_sections.ld and flat_memory.ld). - * Check boards/risc-v/esp32c3. + * Check boards/risc-v/esp32c3-legacy. */ extern uint8_t _srtcheap[]; diff --git a/arch/risc-v/src/esp32c3/esp32c3_rtcheap.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtcheap.h similarity index 95% rename from arch/risc-v/src/esp32c3/esp32c3_rtcheap.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_rtcheap.h index 88ab9b68725a3..29253466802bb 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_rtcheap.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_rtcheap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_rtcheap.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_rtcheap.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTCHEAP_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTCHEAP_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_RTCHEAP_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_RTCHEAP_H /**************************************************************************** * Public Function Prototypes @@ -143,4 +143,4 @@ struct mallinfo esp32c3_rtcheap_mallinfo(void); } #endif -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RTCHEAP_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_RTCHEAP_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_serial.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_serial.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_serial.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_serial.c index 31a2532dd595c..f85d1a74188cd 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_serial.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_serial.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_serial.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_serial.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_sha.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_sha.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_sha.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_sha.c index db8ec46d768e2..cd83b72af769a 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_sha.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_sha.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_sha.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_sha.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_sha.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_sha.h new file mode 100644 index 0000000000000..a5ccdaf6f8c39 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_sha.h @@ -0,0 +1,269 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/esp32c3_sha.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_SHA_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_SHA_H + +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +enum esp32c3_sha_type_e +{ + ESP32C3_SHA1_1 = 0, + ESP32C3_SHA2_224, + ESP32C3_SHA2_256, + ESP32C3_SHA3_384, + ESP32C3_SHA3_512, + ESP32C3_SHA_TYPE_MAX +}; + +enum esp32c3_sha_state_e +{ + ESP32C3_SHA_STATE_INIT, + ESP32C3_SHA_STATE_IN_PROCESS +}; + +/* SHA-1 context structure */ + +struct esp32c3_sha1_context_s +{ + uint32_t total[2]; /* number of bytes processed */ + uint32_t state[5]; /* intermediate digest state */ + unsigned char buffer[64]; /* data block being processed */ + bool first_block; /* if first then true else false */ + enum esp32c3_sha_type_e mode; + enum esp32c3_sha_state_e sha_state; +}; + +/* SHA-256 context structure */ + +struct esp32c3_sha256_context_s +{ + uint32_t total[2]; /* number of bytes processed */ + uint32_t state[8]; /* intermediate digest state */ + unsigned char buffer[64]; /* data block being processed */ + bool first_block; /* if first then true, else false */ + enum esp32c3_sha_type_e mode; + enum esp32c3_sha_state_e sha_state; +}; + +/* SHA-512 context structure */ + +struct esp32c3_sha512_context_s +{ + uint64_t total[2]; /* number of bytes processed */ + uint64_t state[8]; /* intermediate digest state */ + uint8_t buffer[128]; /* data block being processed */ + + bool first_block; /* if first then true, else false */ + enum esp32c3_sha_type_e mode; + enum esp32c3_sha_state_e sha_state; +}; + +/**************************************************************************** + * Name: esp32c3_sha_init + * + * Description: + * Initialize ESP32-C3 SHA hardware. + * + * Input Parameters: + * None + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_sha_init(void); + +/**************************************************************************** + * Name: esp32c3_sha1_init + * + * Description: + * Initializes a SHA-1 context. + * + * Input Parameters: + * ctx - The SHA-1 context to initialize + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_sha1_init(struct esp32c3_sha1_context_s *ctx); + +/**************************************************************************** + * Name: esp32c3_sha1_starts + * + * Description: + * Starts a SHA-1 checksum calculation. + * + * Input Parameters: + * ctx - The SHA-1 context to initialize + * + * Returned Value: + * OK is returned on success. + * + ****************************************************************************/ + +int esp32c3_sha1_starts(struct esp32c3_sha1_context_s *ctx); + +/**************************************************************************** + * Name: esp32c3_sha1_update + * + * Description: + * Feeds an input buffer into an ongoing SHA-1 checksum calculation. + * + * Input Parameters: + * ctx - The SHA-1 context to use + * input - The buffer holding the input data + * ilen - The length of the input data in Bytes + * + * Returned Value: + * OK is returned on success. + * Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_sha1_update(struct esp32c3_sha1_context_s *ctx, + const unsigned char *input, + size_t ilen); + +/**************************************************************************** + * Name: esp32c3_sha1_finish + * + * Description: + * Finishes the SHA-1 operation, + * and writes the result to the output buffer. + * + * Input Parameters: + * ctx - The SHA-1 context to use + * output - The SHA-1 checksum result + * + * Returned Value: + * OK is returned on success. + * Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_sha1_finish(struct esp32c3_sha1_context_s *ctx, + unsigned char output[20]); + +/**************************************************************************** + * Name: esp32c3_sha256_init + * + * Description: + * Initializes a SHA-256 context. + * + * Input Parameters: + * ctx - The SHA-256 context to initialize + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_sha256_init(struct esp32c3_sha256_context_s *ctx); + +/**************************************************************************** + * Name: esp32c3_sha256_starts + * + * Description: + * Starts a SHA-224 or SHA-256 checksum calculation. + * + * Input Parameters: + * ctx - The SHA-256 context to initialize + * is224 - Determines which function to use + * + * Returned Value: + * OK is returned on success. + * + ****************************************************************************/ + +int esp32c3_sha256_starts(struct esp32c3_sha256_context_s *ctx, bool is224); + +/**************************************************************************** + * Name: esp32c3_sha256_update + * + * Description: + * Feeds an input buffer into an ongoing SHA-224 or SHA-256 + * checksum calculation. + * + * Input Parameters: + * ctx - The SHA-256 context to use + * input - The buffer holding the input data + * ilen - The length of the input data in Bytes + * + * Returned Value: + * OK is returned on success. + * Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_sha256_update(struct esp32c3_sha256_context_s *ctx, + const unsigned char *input, + size_t ilen); + +/**************************************************************************** + * Name: esp32c3_sha256_finish + * + * Description: + * Finishes the SHA-224 or SHA-256 operation, and writes the result to + * the output buffer. + * + * Input Parameters: + * ctx - The SHA-256 context to use + * output - The SHA-256 checksum result + * + * Returned Value: + * OK is returned on success. + * Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32c3_sha256_finish(struct esp32c3_sha256_context_s *ctx, + unsigned char output[32]); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_SHA_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_spi.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_spi.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_spi.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_spi.c index daab611eb6c87..f1ad8f840d7c4 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_spi.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_spi.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_spi.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_spi.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_spi.h new file mode 100644 index 0000000000000..68a62e8eb8582 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_spi.h @@ -0,0 +1,170 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/esp32c3_spi.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_SPI_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_SPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#ifdef CONFIG_ESP32C3_SPI + +#include + +#ifdef CONFIG_ESP32C3_SPI2 +# define ESP32C3_SPI2 2 +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_spibus_initialize + * + * Description: + * Initialize the selected SPI bus. + * + * Input Parameters: + * port - Port number (for hardware that has multiple SPI interfaces) + * + * Returned Value: + * Valid SPI device structure reference on success; NULL on failure + * + ****************************************************************************/ + +struct spi_dev_s *esp32c3_spibus_initialize(int port); + +/**************************************************************************** + * Name: esp32c3_spi[0|1]_select and esp32c3_spi[0|1]_status + * + * Description: + * The external functions, esp32c3_spi[0|1]_select, + * esp32c3_spi[0|1]_status, and esp32c3_spi[0|1]_cmddata must be provided + * by board-specific logic. + * These are implementations of the select, status, and cmddata methods of + * the SPI interface defined by struct spi_ops_s (include/nuttx/spi/spi.h). + * All other methods (including esp32c3_spibus_initialize()) are provided + * by common ESP32-C3 logic. To use this common SPI logic on your board: + * + * 1. Provide logic in esp32c3_board_initialize() to configure SPI chip + * select pins. + * 2. Provide esp32c3_spi[0|1]_select() and esp32c3_spi[0|1]_status() + * functions in your board-specific logic. These functions will perform + * chip selection and status operations using GPIOs in the way your + * board is configured. + * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, + * then provide esp32c3_spi[0|1]_cmddata() functions in your + * board-specific logic. These functions will perform cmd/data selection + * operations using GPIOs in the way your board is configured. + * 4. Add a call to esp32c3_spibus_initialize() in your low level + * application initialization logic. + * 5. The handle returned by esp32c3_spibus_initialize() may then be used + * to bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32C3_SPI2 +void esp32c3_spi2_select(struct spi_dev_s *dev, uint32_t devid, + bool selected); +uint8_t esp32c3_spi2_status(struct spi_dev_s *dev, uint32_t devid); +int esp32c3_spi2_cmddata(struct spi_dev_s *dev, + uint32_t devid, + bool cmd); +#endif + +/**************************************************************************** + * Name: esp32c3_spibus_uninitialize + * + * Description: + * Uninitialize an SPI bus. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_spibus_uninitialize(struct spi_dev_s *dev); + +/**************************************************************************** + * Name: esp32c3_spislave_ctrlr_initialize + * + * Description: + * Initialize the selected SPI Slave bus. + * + * Input Parameters: + * port - Port number (for hardware that has multiple SPI Slave interfaces) + * + * Returned Value: + * Valid SPI Slave controller structure reference on success; + * NULL on failure. + * + ****************************************************************************/ + +struct spi_slave_ctrlr_s *esp32c3_spislave_ctrlr_initialize(int port); + +/**************************************************************************** + * Name: esp32c3_spislave_ctrlr_uninitialize + * + * Description: + * Uninitialize an SPI Slave bus. + * + * Input Parameters: + * ctrlr - SPI Slave controller interface instance + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32c3_spislave_ctrlr_uninitialize(struct spi_slave_ctrlr_s *ctrlr); + +#endif /* CONFIG_ESP32C3_SPI */ + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_SPI_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_spi_slave.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_spi_slave.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_spi_slave.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_spi_slave.c index ef0f4d21ed739..3bc8e8b9b3f26 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_spi_slave.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_spi_slave.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_spi_slave.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_spi_slave.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_spiflash.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_spiflash.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash.c index 9cccbe02e350e..3f3efae19dd68 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_spiflash.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_spiflash.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash.h new file mode 100644 index 0000000000000..2747f6a0f04e3 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash.h @@ -0,0 +1,132 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_SPIFLASH_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_SPIFLASH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: spi_flash_read_encrypted + * + * Description: + * + * Read data from Encrypted Flash. + * + * If flash encryption is enabled, this function will transparently + * decrypt data as it is read. + * If flash encryption is not enabled, this function behaves the same as + * spi_flash_read(). + * + * See esp_flash_encryption_enabled() for a function to check if flash + * encryption is enabled. + * + * Parameters: + * addr - source address of the data in Flash. + * buffer - pointer to the destination buffer + * size - length of data + * + * Returned Values: esp_err_t + * + ****************************************************************************/ + +int spi_flash_read_encrypted(uint32_t addr, void *buffer, uint32_t size); + +/**************************************************************************** + * Name: esp32c3_spiflash_unmask_cpuint + * + * Description: + * Unmask CPU interrupt and keep this interrupt work when read, write, + * erase SPI Flash. + * + * By default, all CPU interrupts are masked. + * + * Input Parameters: + * cpuint - CPU interrupt ID + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_spiflash_unmask_cpuint(int cpuint); + +/**************************************************************************** + * Name: esp32c3_spiflash_unmask_cpuint + * + * Description: + * Mask CPU interrupt and disable this interrupt when read, write, + * erase SPI Flash. + * + * By default, all CPU interrupts are masked. + * + * Input Parameters: + * cpuint - CPU interrupt ID + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_spiflash_mask_cpuint(int cpuint); + +/**************************************************************************** + * Name: esp32c3_spiflash_init + * + * Description: + * Initialize ESP32-C3 SPI flash driver. + * + * Returned Value: + * OK if success or a negative value if fail. + * + ****************************************************************************/ + +int esp32c3_spiflash_init(void); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_SPIFLASH_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_spiflash_mtd.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash_mtd.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_spiflash_mtd.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash_mtd.c index 83c46b391aa0b..f7ec873ce7ac3 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_spiflash_mtd.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash_mtd.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_spiflash_mtd.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash_mtd.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_spiflash_mtd.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash_mtd.h similarity index 92% rename from arch/risc-v/src/esp32c3/esp32c3_spiflash_mtd.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash_mtd.h index 1d0700ac9343f..cc23bf09b545e 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_spiflash_mtd.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash_mtd.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_spiflash_mtd.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_spiflash_mtd.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SPIFLASH_MTD_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SPIFLASH_MTD_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_SPIFLASH_MTD_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_SPIFLASH_MTD_H /**************************************************************************** * Included Files @@ -105,4 +105,4 @@ struct mtd_dev_s *esp32c3_spiflash_alloc_mtdpart(uint32_t mtd_offset, #undef EXTERN #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SPIFLASH_MTD_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_SPIFLASH_MTD_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_start.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_start.c similarity index 97% rename from arch/risc-v/src/esp32c3/esp32c3_start.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_start.c index eba49d39ad7f2..29f5dc9febaa3 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_start.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_start.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_start.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_start.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -127,12 +127,6 @@ HDR_ATTR static void (*_entry_point)(void) = __start; * Public Data ****************************************************************************/ -/* Address of the IDLE thread */ - -uint8_t g_idlestack[CONFIG_IDLETHREAD_STACKSIZE] - aligned_data(16) locate_data(".noinit"); -uintptr_t g_idle_topstack = ESP32C3_IDLESTACK_TOP; - /**************************************************************************** * Private Functions ****************************************************************************/ diff --git a/arch/risc-v/src/esp32c3/esp32c3_start.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_start.h similarity index 90% rename from arch/risc-v/src/esp32c3/esp32c3_start.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_start.h index f32ba06a01f82..3e4db7ebe252d 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_start.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_start.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_start.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_start.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -22,8 +22,8 @@ * Included Files ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_START_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_START_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_START_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_START_H /**************************************************************************** * Included Files @@ -52,4 +52,4 @@ void esp32c3_board_initialize(void); -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_START_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_START_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_systemreset.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_systemreset.c similarity index 98% rename from arch/risc-v/src/esp32c3/esp32c3_systemreset.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_systemreset.c index 219f5735cceb9..b6a99c70031f3 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_systemreset.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_systemreset.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_systemreset.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_systemreset.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_systemreset.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_systemreset.h similarity index 93% rename from arch/risc-v/src/esp32c3/esp32c3_systemreset.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_systemreset.h index 184b50624416a..5ce011bb0fdac 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_systemreset.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_systemreset.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_systemreset.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_systemreset.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SYSTEMRESET_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SYSTEMRESET_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_SYSTEMRESET_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_SYSTEMRESET_H /**************************************************************************** * Included Files @@ -102,4 +102,4 @@ void up_shutdown_handler(void); #undef EXTERN #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SYSTEMRESET_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_SYSTEMRESET_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_textheap.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_textheap.c similarity index 98% rename from arch/risc-v/src/esp32c3/esp32c3_textheap.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_textheap.c index 52be45fe13095..6286d24f75e5e 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_textheap.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_textheap.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_textheap.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_textheap.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_tickless.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_tickless.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_tickless.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_tickless.c index 15752ab0095bd..127419dd86357 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_tickless.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_tickless.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_tickless.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_tickless.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_tickless.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_tickless.h similarity index 90% rename from arch/risc-v/src/esp32c3/esp32c3_tickless.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_tickless.h index 7c0609eac6a2b..8efee32e500d0 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_tickless.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_tickless.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_tickless.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_tickless.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_TICKLESS_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_TICKLESS_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_TICKLESS_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_TICKLESS_H /**************************************************************************** * Included Files @@ -64,4 +64,4 @@ uint32_t up_get_idletime(void); void up_step_idletime(uint32_t idletime_us); -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_TICKLESS_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_TICKLESS_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_tim.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_tim.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_tim.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_tim.c index 51e4aaf84afb2..280cd265b0870 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_tim.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_tim.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_tim.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_tim.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_tim.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_tim.h new file mode 100644 index 0000000000000..5d15492870584 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_tim.h @@ -0,0 +1,141 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/esp32c3_tim.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_TIM_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_TIM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Helpers ******************************************************************/ + +#define ESP32C3_TIM_START(d) ((d)->ops->start(d)) +#define ESP32C3_TIM_STOP(d) ((d)->ops->stop(d)) +#define ESP32C3_TIM_CLEAR(d) ((d)->ops->clear(d)) +#define ESP32C3_TIM_SETMODE(d, m) ((d)->ops->setmode(d, m)) +#define ESP32C3_TIM_CLK_SRC(d, s) ((d)->ops->setclksrc(d, s)) +#define ESP32C3_TIM_SETPRE(d, p) ((d)->ops->setpre(d, p)) +#define ESP32C3_TIM_GETCTR(d, v) ((d)->ops->getcounter(d, v)) +#define ESP32C3_TIM_SETCTR(d, v) ((d)->ops->setcounter(d, v)) +#define ESP32C3_TIM_RLD_NOW(d) ((d)->ops->reloadnow(d)) +#define ESP32C3_TIM_GETALRVL(d, v) ((d)->ops->getalarmvalue(d, v)) +#define ESP32C3_TIM_SETALRVL(d, v) ((d)->ops->setalarmvalue(d, v)) +#define ESP32C3_TIM_SETALRM(d, e) ((d)->ops->setalarm(d, e)) +#define ESP32C3_TIM_SETARLD(d, e) ((d)->ops->setautoreload(d, e)) +#define ESP32C3_TIM_SETISR(d, hnd, arg) ((d)->ops->setisr(d, hnd, arg)) +#define ESP32C3_TIM_ENABLEINT(d) ((d)->ops->enableint(d)) +#define ESP32C3_TIM_DISABLEINT(d) ((d)->ops->disableint(d)) +#define ESP32C3_TIM_ACKINT(d) ((d)->ops->ackint(d)) +#define ESP32C3_TIM_CHECKINT(d) ((d)->ops->checkint(d)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Instances of Timer */ + +enum esp32c3_tim_inst_e +{ + ESP32C3_TIMER0 = 0, /* Timer 0 from Timer Group 0 */ + ESP32C3_TIMER1, /* Timer 0 from Timer Group 1 */ + ESP32C3_SYSTIM, /* SYSTIMER 1 */ +}; + +/* Timer mode */ + +enum esp32c3_tim_clksrc_e +{ + ESP32C3_TIM_APB_CLK, + ESP32C3_TIM_XTAL_CLK, +}; + +/* Timer mode */ + +enum esp32c3_tim_mode_e +{ + ESP32C3_TIM_MODE_DOWN, + ESP32C3_TIM_MODE_UP, +}; + +/* ESP32-C3 TIM device */ + +struct esp32c3_tim_dev_s +{ + struct esp32c3_tim_ops_s *ops; +}; + +/* ESP32-C3 TIM ops */ + +/* This is a struct containing the pointers to the timer operations */ + +struct esp32c3_tim_ops_s +{ + /* Timer tasks */ + + void (*start)(struct esp32c3_tim_dev_s *dev); + void (*stop)(struct esp32c3_tim_dev_s *dev); + void (*clear)(struct esp32c3_tim_dev_s *dev); + + /* Timer operations */ + + void (*setmode)(struct esp32c3_tim_dev_s *dev, + enum esp32c3_tim_mode_e mode); + void (*setclksrc)(struct esp32c3_tim_dev_s *dev, + enum esp32c3_tim_clksrc_e src); + void (*setpre)(struct esp32c3_tim_dev_s *dev, uint16_t pre); + void (*getcounter)(struct esp32c3_tim_dev_s *dev, + uint64_t *value); + void (*setcounter)(struct esp32c3_tim_dev_s *dev, uint64_t value); + void (*reloadnow)(struct esp32c3_tim_dev_s *dev); + void (*getalarmvalue)(struct esp32c3_tim_dev_s *dev, + uint64_t *value); + void (*setalarmvalue)(struct esp32c3_tim_dev_s *dev, + uint64_t value); + void (*setalarm)(struct esp32c3_tim_dev_s *dev, bool enable); + void (*setautoreload)(struct esp32c3_tim_dev_s *dev, bool enable); + + /* Timer interrupts */ + + int (*setisr)(struct esp32c3_tim_dev_s *dev, xcpt_t handler, + void * arg); + void (*enableint)(struct esp32c3_tim_dev_s *dev); + void (*disableint)(struct esp32c3_tim_dev_s *dev); + void (*ackint)(struct esp32c3_tim_dev_s *dev); + int (*checkint)(struct esp32c3_tim_dev_s *dev); +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +struct esp32c3_tim_dev_s *esp32c3_tim_init(int timer); +void esp32c3_tim_deinit(struct esp32c3_tim_dev_s *dev); + +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_TIM_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_tim_lowerhalf.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_tim_lowerhalf.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_tim_lowerhalf.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_tim_lowerhalf.c index 89f5ff49857dc..6a45de98b6c39 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_tim_lowerhalf.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_tim_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_tim_lowerhalf.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_tim_lowerhalf.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_tim_lowerhalf.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_tim_lowerhalf.h similarity index 86% rename from arch/risc-v/src/esp32c3/esp32c3_tim_lowerhalf.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_tim_lowerhalf.h index 3648564744fc5..06f6839b6180e 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_tim_lowerhalf.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_tim_lowerhalf.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_tim_lowerhalf.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_tim_lowerhalf.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_TIM_LOWERHALF_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_TIM_LOWERHALF_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_TIM_LOWERHALF_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_TIM_LOWERHALF_H /**************************************************************************** * Included Files @@ -37,4 +37,4 @@ int esp32c3_timer_initialize(const char *devpath, uint8_t timer); -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_TIM_LOWERHALF_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_TIM_LOWERHALF_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_timerisr.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_timerisr.c similarity index 98% rename from arch/risc-v/src/esp32c3/esp32c3_timerisr.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_timerisr.c index 9560eb9e8b332..49536f0247ea2 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_timerisr.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_timerisr.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_timerisr.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_timerisr.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_twai.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_twai.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_twai.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_twai.c index b057fb6fd60eb..c99e091907dfc 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_twai.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_twai.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_twai.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_twai.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_twai.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_twai.h new file mode 100644 index 0000000000000..de007589db047 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_twai.h @@ -0,0 +1,77 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/esp32c3_twai.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_TWAI_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_TWAI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/esp32c3_twai.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_twaiinitialize + * + * Description: + * Initialize the selected CAN port + * + * Input Parameters: + * Port number (for hardware that has multiple TWAI interfaces) + * + * Returned Value: + * Valid TWAI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +#if defined(CONFIG_CAN) && defined(CONFIG_ESP32C3_TWAI) +struct can_dev_s; +struct can_dev_s *esp32c3_twaiinitialize(int port); +#endif + +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_TWAI_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_uid.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_uid.c new file mode 100644 index 0000000000000..bc31744f4e0ee --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_uid.c @@ -0,0 +1,55 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/esp32c3_uid.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "hardware/esp32c3_efuse.h" +#include "esp32c3.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_get_uniqueid + * + * Description: + * Get CPU unique ID. + * + * Parameters: + * uniqueid - unique ID buffer + * + ****************************************************************************/ + +void esp32c3_get_uniqueid(uint8_t *uniqueid) +{ + int i; + + for (i = 0; i < 16; i++) + { + uniqueid[i] = getreg8(EFUSE_RD_SYS_DATA_PART1_0_REG + i); + } +} diff --git a/arch/risc-v/src/esp32c3/esp32c3_uid.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_uid.h similarity index 88% rename from arch/risc-v/src/esp32c3/esp32c3_uid.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_uid.h index 51c113c3e6145..5c9e28db37038 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_uid.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_uid.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_uid.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_uid.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_UID_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_UID_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_UID_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_UID_H /**************************************************************************** * Included Files @@ -47,4 +47,4 @@ void esp32c3_get_uniqueid(uint8_t *uniqueid); -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_UID_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_UID_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_usbserial.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_usbserial.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_usbserial.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_usbserial.c index 8cbb3972dfce2..0fc2d518f7d75 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_usbserial.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_usbserial.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_usbserial.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_usbserial.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_usbserial.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_usbserial.h similarity index 88% rename from arch/risc-v/src/esp32c3/esp32c3_usbserial.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_usbserial.h index 9c5f3f958dec8..d9d2e5c75ac79 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_usbserial.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_usbserial.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_usbserial.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_usbserial.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_USBSERIAL_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_USBSERIAL_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_USBSERIAL_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_USBSERIAL_H /**************************************************************************** * Included Files @@ -48,4 +48,4 @@ extern uart_dev_t g_uart_usbserial; void esp32c3_usbserial_write(char ch); -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_USBSERIAL_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_USBSERIAL_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/esp32c3_userspace.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_userspace.c new file mode 100644 index 0000000000000..fd8137788d2f7 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_userspace.c @@ -0,0 +1,403 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/esp32c3_userspace.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include + +#include "riscv_internal.h" +#include "esp32c3.h" +#include "esp32c3_userspace.h" +#include "hardware/esp32c3_cache_memory.h" +#include "hardware/extmem_reg.h" + +#ifdef CONFIG_BUILD_PROTECTED + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define USER_IMAGE_OFFSET CONFIG_ESP32C3_USER_IMAGE_OFFSET + +#define MMU_BLOCK0_VADDR SOC_DROM_LOW +#define MMU_SIZE 0x3f0000 +#define MMU_BLOCK63_VADDR (MMU_BLOCK0_VADDR + MMU_SIZE) + +/* Cache MMU block size */ + +#define MMU_BLOCK_SIZE 0x00010000 /* 64 KB */ + +/* Cache MMU address mask (MMU tables ignore bits which are zero) */ + +#define MMU_FLASH_MASK (~(MMU_BLOCK_SIZE - 1)) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct user_image_load_header_s +{ + uintptr_t drom_vma; /* Destination address (VMA) for DROM region */ + uintptr_t drom_lma; /* Flash offset (LMA) for start of DROM region */ + uintptr_t drom_size; /* Size of DROM region */ + uintptr_t irom_vma; /* Destination address (VMA) for IROM region */ + uintptr_t irom_lma; /* Flash offset (LMA) for start of IROM region */ + uintptr_t irom_size; /* Size of IROM region */ +}; + +/**************************************************************************** + * ROM Function Prototypes + ****************************************************************************/ + +extern uint32_t cache_suspend_icache(void); +extern void cache_resume_icache(uint32_t val); +extern void cache_invalidate_icache_all(void); +extern int cache_dbus_mmu_set(uint32_t ext_ram, uint32_t vaddr, + uint32_t paddr, uint32_t psize, uint32_t num, + uint32_t fixed); +extern int cache_ibus_mmu_set(uint32_t ext_ram, uint32_t vaddr, + uint32_t paddr, uint32_t psize, uint32_t num, + uint32_t fixed); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct user_image_load_header_s g_header; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: calc_mmu_pages + * + * Description: + * Calculate the required number of MMU pages for mapping a given region + * from External Flash into Internal RAM. + * + * Input Parameters: + * size - Length of the region to map + * vaddr - Starting External Flash offset to map to Internal RAM + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static inline uint32_t calc_mmu_pages(uint32_t size, uint32_t vaddr) +{ + return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_BLOCK_SIZE - 1) / + MMU_BLOCK_SIZE; +} + +/**************************************************************************** + * Name: configure_mmu + * + * Description: + * Configure the External Flash MMU and Cache for enabling access to code + * and read-only data of the userspace image. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static noinline_function IRAM_ATTR void configure_mmu(void) +{ + uint32_t drom_lma_aligned; + uint32_t drom_vma_aligned; + uint32_t drom_page_count; + uint32_t irom_lma_aligned; + uint32_t irom_vma_aligned; + uint32_t irom_page_count; + + size_t partition_offset = USER_IMAGE_OFFSET; + uint32_t app_drom_lma = partition_offset + g_header.drom_lma; + uint32_t app_drom_size = g_header.drom_size; + uint32_t app_drom_vma = g_header.drom_vma; + uint32_t app_irom_lma = partition_offset + g_header.irom_lma; + uint32_t app_irom_size = g_header.irom_size; + uint32_t app_irom_vma = g_header.irom_vma; + + uint32_t autoload = cache_suspend_icache(); + cache_invalidate_icache_all(); + + drom_lma_aligned = app_drom_lma & MMU_FLASH_MASK; + drom_vma_aligned = app_drom_vma & MMU_FLASH_MASK; + drom_page_count = calc_mmu_pages(app_drom_size, app_drom_vma); + ASSERT(cache_dbus_mmu_set(MMU_ACCESS_FLASH, drom_vma_aligned, + drom_lma_aligned, 64, + (int)drom_page_count, 0) == 0); + + irom_lma_aligned = app_irom_lma & MMU_FLASH_MASK; + irom_vma_aligned = app_irom_vma & MMU_FLASH_MASK; + irom_page_count = calc_mmu_pages(app_irom_size, app_irom_vma); + ASSERT(cache_ibus_mmu_set(MMU_ACCESS_FLASH, irom_vma_aligned, + irom_lma_aligned, 64, + (int)irom_page_count, 0) == 0); + + cache_resume_icache(autoload); +} + +/**************************************************************************** + * Name: map_flash + * + * Description: + * Map a region of the External Flash memory to Internal RAM. + * + * Input Parameters: + * src_addr - Starting External Flash offset to map to Internal RAM + * size - Length of the region to map + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static noinline_function IRAM_ATTR const void *map_flash(uint32_t src_addr, + uint32_t size) +{ + uint32_t src_addr_aligned; + uint32_t page_count; + + uint32_t autoload = cache_suspend_icache(); + cache_invalidate_icache_all(); + + src_addr_aligned = src_addr & MMU_FLASH_MASK; + page_count = calc_mmu_pages(size, src_addr); + ASSERT(cache_dbus_mmu_set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, + src_addr_aligned, 64, (int)page_count, 0) == 0); + + cache_resume_icache(autoload); + + return (void *)(MMU_BLOCK63_VADDR + (src_addr - src_addr_aligned)); +} + +/**************************************************************************** + * Name: load_header + * + * Description: + * Load IROM and DROM information from image header to enable the correct + * configuration of the Flash MMU and Cache. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void load_header(void) +{ + size_t length = sizeof(struct user_image_load_header_s); + const uint8_t *data = + (const uint8_t *)map_flash(USER_IMAGE_OFFSET, length); + + DEBUGASSERT(data != NULL); + + memcpy(&g_header, data, length); +} + +/**************************************************************************** + * Name: initialize_data + * + * Description: + * Initialize data sections of the userspace image. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void initialize_data(void) +{ + uint8_t *dest; + uint8_t *end; + size_t length = USERSPACE->us_dataend - USERSPACE->us_datastart; + const uint8_t *src = + (const uint8_t *)map_flash(USER_IMAGE_OFFSET + USERSPACE->us_datasource, + length); + + DEBUGASSERT(src != NULL); + + dest = (uint8_t *)USERSPACE->us_datastart; + end = (uint8_t *)USERSPACE->us_dataend; + + while (dest != end) + { + *dest++ = *src++; + } +} + +/**************************************************************************** + * Name: configure_mpu + * + * Description: + * Configure the MPU for kernel/userspace separation. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void configure_mpu(void) +{ + const uintptr_t R = PMPCFG_R; + const uintptr_t RW = PMPCFG_R | PMPCFG_W; + const uintptr_t RX = PMPCFG_R | PMPCFG_X; + const uintptr_t RWX = PMPCFG_R | PMPCFG_W | PMPCFG_X; + + /* Ensure PMP had not been previously configured by the bootloader */ + + DEBUGASSERT(riscv_configured_pmp_regions() == 0); + + /* Region for the userspace read-only data in SPI Flash */ + + riscv_config_pmp_region(0, PMPCFG_A_TOR, UDROM_START, 0); + riscv_config_pmp_region(1, PMPCFG_A_TOR | R, UDROM_END, 0); + + /* Region for the userspace data. + * NOTE: User-space heap may extend further than UDRAM_END. + */ + + riscv_config_pmp_region(2, PMPCFG_A_TOR, UDRAM_START, 0); + riscv_config_pmp_region(3, PMPCFG_A_TOR | RW, SOC_DRAM_HIGH, 0); + + /* Region for the memory-mapped functions located in internal ROM */ + + riscv_config_pmp_region(4, PMPCFG_L | PMPCFG_A_NAPOT | R, + SOC_DROM_MASK_LOW, + SOC_DROM_MASK_HIGH - SOC_DROM_MASK_LOW); + + riscv_config_pmp_region(5, PMPCFG_L | PMPCFG_A_TOR | RX, + SOC_IROM_MASK_HIGH, + 0); + + /* Region for the exception vectors located in internal SRAM area reserved + * for the kernel space. + */ + + riscv_config_pmp_region(6, PMPCFG_A_NAPOT | RX, + VECTORS_START, + VECTORS_END - VECTORS_START); + + /* Region for the userspace code located in internal SRAM */ + + riscv_config_pmp_region(7, PMPCFG_A_TOR, UIRAM_START, 0); + riscv_config_pmp_region(8, PMPCFG_A_TOR | RWX, UIRAM_END, 0); + + /* Region for the userspace code in SPI Flash */ + + riscv_config_pmp_region(9, PMPCFG_A_TOR, UIROM_START, 0); + riscv_config_pmp_region(10, PMPCFG_A_TOR | RX, UIROM_END, 0); + + /* Region for peripheral addresses */ + + riscv_config_pmp_region(11, PMPCFG_A_TOR, SOC_PERIPHERAL_HIGH, 0); + + /* Region for the remainder of the address space */ + + riscv_config_pmp_region(12, PMPCFG_L | PMPCFG_A_TOR, UINT32_MAX, 0); + riscv_config_pmp_region(13, PMPCFG_L | PMPCFG_A_NA4, UINT32_MAX, 0); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_userspace + * + * Description: + * For the case of the separate user/kernel space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the userspace .data and .bss + * segments. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32c3_userspace(void) +{ + uint8_t *dest; + uint8_t *end; + + /* Load IROM and DROM information from image header */ + + load_header(); + + /* Configure the MMU for enabling access to the userspace image */ + + configure_mmu(); + + /* Clear all of userspace .bss */ + + DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && + USERSPACE->us_bssstart <= USERSPACE->us_bssend); + + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; + + while (dest != end) + { + *dest++ = 0; + } + + /* Initialize all of userspace .data */ + + DEBUGASSERT(USERSPACE->us_datasource != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart <= USERSPACE->us_dataend); + + initialize_data(); + + /* Configure MPU / PMP to grant access to the userspace */ + + configure_mpu(); +} + +#endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_userspace.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_userspace.h similarity index 88% rename from arch/risc-v/src/esp32c3/esp32c3_userspace.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_userspace.h index bc1d13517407b..216ec30d773c8 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_userspace.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_userspace.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_userspace.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_userspace.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_USERSPACE_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_USERSPACE_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_USERSPACE_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_USERSPACE_H /**************************************************************************** * Included Files @@ -46,4 +46,4 @@ void esp32c3_userspace(void); #endif -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_USERSPACE_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_USERSPACE_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_vectors.S b/arch/risc-v/src/esp32c3-legacy/esp32c3_vectors.S similarity index 95% rename from arch/risc-v/src/esp32c3/esp32c3_vectors.S rename to arch/risc-v/src/esp32c3-legacy/esp32c3_vectors.S index 25e16206099ed..ec69546f311ec 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_vectors.S +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_vectors.S @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_vectors.S + * arch/risc-v/src/esp32c3-legacy/esp32c3_vectors.S * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -24,7 +24,7 @@ #include #include -#include +#include #include "chip.h" diff --git a/arch/risc-v/src/esp32c3/esp32c3_wdt.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_wdt.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_wdt.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_wdt.c index e1cfe69a7bad2..a908dc00fd9c2 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wdt.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_wdt.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_wdt.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_wdt.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_wdt.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_wdt.h similarity index 96% rename from arch/risc-v/src/esp32c3/esp32c3_wdt.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_wdt.h index 82b09d5f85ec8..78f00761fc0fd 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wdt.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_wdt.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_wdt.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_wdt.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WDT_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WDT_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_WDT_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_WDT_H /**************************************************************************** * Included Files @@ -144,4 +144,4 @@ void esp32c3_wdt_early_deinit(void); void esp32c3_wdt_deinit(struct esp32c3_wdt_dev_s *dev); bool esp32c3_wdt_is_running(struct esp32c3_wdt_dev_s *dev); -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WDT_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_WDT_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_wdt_lowerhalf.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_wdt_lowerhalf.c index 490bf785357ab..e01295a956e6c 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_wdt_lowerhalf.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_wdt_lowerhalf.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -530,7 +530,7 @@ static xcpt_t esp32c3_wdt_capture(struct watchdog_lowerhalf_s *lower, DEBUGASSERT(priv); - wdinfo("Entry: handler=0x%" PRIxPTR "\n", (uintptr_t) handler); + wdinfo("Entry: handler=%p\n", handler); /* Get the old handler to return it */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_wdt_lowerhalf.h similarity index 89% rename from arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_wdt_lowerhalf.h index 354e0d48aeefa..b16f94ddd534c 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_wdt_lowerhalf.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_wdt_lowerhalf.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_wdt_lowerhalf.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WDT_LOWERHALF_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WDT_LOWERHALF_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_WDT_LOWERHALF_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_WDT_LOWERHALF_H /**************************************************************************** * Included Files @@ -55,4 +55,4 @@ int esp32c3_wdt_initialize(const char *devpath, enum esp32c3_wdt_inst_e wdt); -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WDT_LOWERHALF_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_WDT_LOWERHALF_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_adapter.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_adapter.c index 92a4377b36101..0512f59e3b9f4 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_adapter.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_adapter.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_adapter.h similarity index 98% rename from arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_adapter.h index b3165d45a0b28..5d81fa09549c2 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_adapter.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_adapter.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WIFI_ADAPTER_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WIFI_ADAPTER_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_WIFI_ADAPTER_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_WIFI_ADAPTER_H /**************************************************************************** * Included Files @@ -858,4 +858,4 @@ void esp_wifi_stop_callback(void); #undef EXTERN #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WIFI_ADAPTER_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_WIFI_ADAPTER_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_utils.c similarity index 98% rename from arch/risc-v/src/esp32c3/esp32c3_wifi_utils.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_utils.c index 8c9ed90935b77..df5388755e02f 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_utils.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_wifi_utils.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_utils.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -87,7 +87,7 @@ static struct wifi_scan_result_s g_scan_priv = { .scan_signal = SEM_INITIALIZER(0), }; -static uint8_t g_channel_num = 0; +static uint8_t g_channel_num; static uint8_t g_channel_list[CHANNEL_MAX_NUM]; /**************************************************************************** @@ -199,10 +199,10 @@ int esp_wifi_start_scan(struct iwreq *iwr) esp_wifi_start(); ret = esp_wifi_scan_start(config, false); - g_scan_priv.scan_status = ESP_SCAN_RUN; if (ret != OK) { wlerr("ERROR: Scan error, ret: %d\n", ret); + ret = ERROR; } else { @@ -223,11 +223,16 @@ int esp_wifi_start_scan(struct iwreq *iwr) } } - if (config != NULL) + if (config) { kmm_free(config); config = NULL; + } + + if (ret == OK) + { wlinfo("INFO: start scan\n"); + g_scan_priv.scan_status = ESP_SCAN_RUN; } return ret; @@ -257,7 +262,7 @@ int esp_wifi_get_scan_results(struct iwreq *iwr) if (g_scan_priv.scan_status == ESP_SCAN_RUN) { irqstate_t irqstate = enter_critical_section(); - if (scan_block == false) + if (!scan_block) { scan_block = true; leave_critical_section(irqstate); @@ -273,7 +278,8 @@ int esp_wifi_get_scan_results(struct iwreq *iwr) } else if (g_scan_priv.scan_status == ESP_SCAN_DISABLED) { - return -EINVAL; + ret = -EINVAL; + goto exit_failed; } if ((iwr == NULL) || (g_scan_priv.scan_status != ESP_SCAN_DONE)) @@ -291,6 +297,13 @@ int esp_wifi_get_scan_results(struct iwreq *iwr) goto exit_failed; } + if (priv->scan_result_size <= 0) + { + ret = OK; + iwr->u.data.length = 0; + goto exit_free_buffer; + } + if (iwr->u.data.pointer == NULL || iwr->u.data.length < priv->scan_result_size) { @@ -299,14 +312,7 @@ int esp_wifi_get_scan_results(struct iwreq *iwr) ret = -E2BIG; iwr->u.data.pointer = NULL; iwr->u.data.length = priv->scan_result_size; - goto exit_failed; - } - - if (priv->scan_result_size <= 0) - { - ret = OK; - iwr->u.data.length = 0; - goto exit_free_buffer; + return ret; } /* Copy result to user buffer */ @@ -410,7 +416,7 @@ void esp_wifi_scan_event_parse(void) is_target_channel = true; } - if (is_target_channel == true) + if (is_target_channel) { result_size = WIFI_SCAN_RESULT_SIZE - priv->scan_result_size; @@ -544,7 +550,7 @@ void esp_wifi_scan_event_parse(void) /* Continue instead of break to log dropped AP results */ - if (parse_done == false) + if (!parse_done) { wlerr("ERROR: No more space in scan_result buffer\n"); } diff --git a/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_utils.h similarity index 92% rename from arch/risc-v/src/esp32c3/esp32c3_wifi_utils.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_utils.h index 00b10d32aaa33..250b99f985f08 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wifi_utils.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_utils.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_wifi_utils.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_wifi_utils.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -22,8 +22,8 @@ * Included Files ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WIFI_UTILS_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WIFI_UTILS_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_WIFI_UTILS_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_WIFI_UTILS_H #include #include @@ -101,4 +101,4 @@ void esp_wifi_scan_event_parse(void); #undef EXTERN #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WIFI_UTILS_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_WIFI_UTILS_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_wireless.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_wireless.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_wireless.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_wireless.c index e19ad3b10f120..3c51037fce943 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wireless.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_wireless.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_wireless.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_wireless.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/arch/risc-v/src/esp32c3/esp32c3_wireless.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_wireless.h similarity index 95% rename from arch/risc-v/src/esp32c3/esp32c3_wireless.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_wireless.h index 14da611eb16fa..6f6bde1f93c19 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wireless.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_wireless.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_wireless.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_wireless.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WIRELESS_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WIRELESS_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_WIRELESS_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_WIRELESS_H /**************************************************************************** * Included Files @@ -191,4 +191,4 @@ int esp_read_mac(uint8_t *mac, esp_mac_type_t type); #undef EXTERN #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WIRELESS_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_WIRELESS_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_wlan.c b/arch/risc-v/src/esp32c3-legacy/esp32c3_wlan.c similarity index 99% rename from arch/risc-v/src/esp32c3/esp32c3_wlan.c rename to arch/risc-v/src/esp32c3-legacy/esp32c3_wlan.c index ecd1603b806b1..d56ae4ac0b477 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wlan.c +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_wlan.c @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_wlan.c + * arch/risc-v/src/esp32c3-legacy/esp32c3_wlan.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -146,7 +146,7 @@ struct wlan_priv_s /* Reference count of register Wi-Fi handler */ -static uint8_t g_callback_register_ref = 0; +static uint8_t g_callback_register_ref; static struct wlan_priv_s g_wlan_priv[ESP32C3_WLAN_DEVS]; @@ -1383,7 +1383,7 @@ int esp32c3_wlan_sta_set_linkstatus(bool linkstatus) { struct wlan_priv_s *priv = &g_wlan_priv[ESP32C3_WLAN_STA_DEVNO]; - if (linkstatus == true) + if (linkstatus) { netdev_carrier_on(&priv->dev); } diff --git a/arch/risc-v/src/esp32c3/esp32c3_wlan.h b/arch/risc-v/src/esp32c3-legacy/esp32c3_wlan.h similarity index 93% rename from arch/risc-v/src/esp32c3/esp32c3_wlan.h rename to arch/risc-v/src/esp32c3-legacy/esp32c3_wlan.h index 029aff1b0e5bc..7d649946dfbdb 100644 --- a/arch/risc-v/src/esp32c3/esp32c3_wlan.h +++ b/arch/risc-v/src/esp32c3-legacy/esp32c3_wlan.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_wlan.h + * arch/risc-v/src/esp32c3-legacy/esp32c3_wlan.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WLAN_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WLAN_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_WLAN_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_WLAN_H /**************************************************************************** * Included Files @@ -108,4 +108,4 @@ int esp32c3_wlan_softap_initialize(void); #undef EXTERN #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_WLAN_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ESP32C3_WLAN_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/apb_ctrl_reg.h b/arch/risc-v/src/esp32c3-legacy/hardware/apb_ctrl_reg.h similarity index 92% rename from arch/risc-v/src/esp32c3/hardware/apb_ctrl_reg.h rename to arch/risc-v/src/esp32c3-legacy/hardware/apb_ctrl_reg.h index 88549e04b77df..21467bbddb817 100644 --- a/arch/risc-v/src/esp32c3/hardware/apb_ctrl_reg.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/apb_ctrl_reg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/apb_ctrl_reg.h + * arch/risc-v/src/esp32c3-legacy/hardware/apb_ctrl_reg.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_APB_CTRL_REG_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_APB_CTRL_REG_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_APB_CTRL_REG_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_APB_CTRL_REG_H /**************************************************************************** * Included Files @@ -79,4 +79,4 @@ #define APB_CTRL_RETENTION_LINK_ADDR_V 0x7FFFFFF #define APB_CTRL_RETENTION_LINK_ADDR_S 0 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_APB_CTRL_REG_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_APB_CTRL_REG_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/bb_reg.h b/arch/risc-v/src/esp32c3-legacy/hardware/bb_reg.h similarity index 88% rename from arch/risc-v/src/esp32c3/hardware/bb_reg.h rename to arch/risc-v/src/esp32c3-legacy/hardware/bb_reg.h index d74bc01d44234..ad0164844d363 100644 --- a/arch/risc-v/src/esp32c3/hardware/bb_reg.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/bb_reg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/bb_reg.h + * arch/risc-v/src/esp32c3-legacy/hardware/bb_reg.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_BB_REG_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_BB_REG_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_BB_REG_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_BB_REG_H /**************************************************************************** * Included Files @@ -46,4 +46,4 @@ #define BB_DC_EST_FORCE_PU_V 1 #define BB_DC_EST_FORCE_PU_S 1 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_BB_REG_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_BB_REG_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_aes.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_aes.h new file mode 100644 index 0000000000000..7e1e6bfc4b3cc --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_aes.h @@ -0,0 +1,780 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_aes.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_AES_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_AES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* AES_KEY_0_REG register + * AES key register 0 + */ + +#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0) + +/* AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_0 0xFFFFFFFF +#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) +#define AES_KEY_0_V 0xFFFFFFFF +#define AES_KEY_0_S 0 + +/* AES_KEY_1_REG register + * AES key register 1 + */ + +#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4) + +/* AES_KEY_1 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_1 0xFFFFFFFF +#define AES_KEY_1_M (AES_KEY_1_V << AES_KEY_1_S) +#define AES_KEY_1_V 0xFFFFFFFF +#define AES_KEY_1_S 0 + +/* AES_KEY_2_REG register + * AES key register 2 + */ + +#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8) + +/* AES_KEY_2 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_2 0xFFFFFFFF +#define AES_KEY_2_M (AES_KEY_2_V << AES_KEY_2_S) +#define AES_KEY_2_V 0xFFFFFFFF +#define AES_KEY_2_S 0 + +/* AES_KEY_3_REG register + * AES key register 3 + */ + +#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc) + +/* AES_KEY_3 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_3 0xFFFFFFFF +#define AES_KEY_3_M (AES_KEY_3_V << AES_KEY_3_S) +#define AES_KEY_3_V 0xFFFFFFFF +#define AES_KEY_3_S 0 + +/* AES_KEY_4_REG register + * AES key register 4 + */ + +#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10) + +/* AES_KEY_4 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_4 0xFFFFFFFF +#define AES_KEY_4_M (AES_KEY_4_V << AES_KEY_4_S) +#define AES_KEY_4_V 0xFFFFFFFF +#define AES_KEY_4_S 0 + +/* AES_KEY_5_REG register + * AES key register 5 + */ + +#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14) + +/* AES_KEY_5 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_5 0xFFFFFFFF +#define AES_KEY_5_M (AES_KEY_5_V << AES_KEY_5_S) +#define AES_KEY_5_V 0xFFFFFFFF +#define AES_KEY_5_S 0 + +/* AES_KEY_6_REG register + * AES key register 6 + */ + +#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18) + +/* AES_KEY_6 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_6 0xFFFFFFFF +#define AES_KEY_6_M (AES_KEY_6_V << AES_KEY_6_S) +#define AES_KEY_6_V 0xFFFFFFFF +#define AES_KEY_6_S 0 + +/* AES_KEY_7_REG register + * AES key register 7 + */ + +#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c) + +/* AES_KEY_7 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_7 0xFFFFFFFF +#define AES_KEY_7_M (AES_KEY_7_V << AES_KEY_7_S) +#define AES_KEY_7_V 0xFFFFFFFF +#define AES_KEY_7_S 0 + +/* AES_TEXT_IN_0_REG register + * Source data register 0 + */ + +#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20) + +/* AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_0 0xFFFFFFFF +#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S) +#define AES_TEXT_IN_0_V 0xFFFFFFFF +#define AES_TEXT_IN_0_S 0 + +/* AES_TEXT_IN_1_REG register + * Source data register 1 + */ + +#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24) + +/* AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_1 0xFFFFFFFF +#define AES_TEXT_IN_1_M (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S) +#define AES_TEXT_IN_1_V 0xFFFFFFFF +#define AES_TEXT_IN_1_S 0 + +/* AES_TEXT_IN_2_REG register + * Source data register 2 + */ + +#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28) + +/* AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_2 0xFFFFFFFF +#define AES_TEXT_IN_2_M (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S) +#define AES_TEXT_IN_2_V 0xFFFFFFFF +#define AES_TEXT_IN_2_S 0 + +/* AES_TEXT_IN_3_REG register + * Source data register 3 + */ + +#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c) + +/* AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_3 0xFFFFFFFF +#define AES_TEXT_IN_3_M (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S) +#define AES_TEXT_IN_3_V 0xFFFFFFFF +#define AES_TEXT_IN_3_S 0 + +/* AES_TEXT_OUT_0_REG register + * Result data register 0 + */ + +#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30) + +/* AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_0 0xFFFFFFFF +#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S) +#define AES_TEXT_OUT_0_V 0xFFFFFFFF +#define AES_TEXT_OUT_0_S 0 + +/* AES_TEXT_OUT_1_REG register + * Result data register 1 + */ + +#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34) + +/* AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_1 0xFFFFFFFF +#define AES_TEXT_OUT_1_M (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S) +#define AES_TEXT_OUT_1_V 0xFFFFFFFF +#define AES_TEXT_OUT_1_S 0 + +/* AES_TEXT_OUT_2_REG register + * Result data register 2 + */ + +#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38) + +/* AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_2 0xFFFFFFFF +#define AES_TEXT_OUT_2_M (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S) +#define AES_TEXT_OUT_2_V 0xFFFFFFFF +#define AES_TEXT_OUT_2_S 0 + +/* AES_TEXT_OUT_3_REG register + * Result data register 3 + */ + +#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c) + +/* AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_3 0xFFFFFFFF +#define AES_TEXT_OUT_3_M (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S) +#define AES_TEXT_OUT_3_V 0xFFFFFFFF +#define AES_TEXT_OUT_3_S 0 + +/* AES_MODE_REG register + * AES working mode configuration register + */ + +#define AES_MODE_REG (DR_REG_AES_BASE + 0x40) + +/* AES_MODE : R/W; bitpos: [2:0]; default: 0; + * Defines the operation type of the AES Accelerator operating under the + * Typical AES working mode. + * & + * 0x0(AES_EN_128): AES-EN-128 # + * 0x1(AES_EN_192): AES-EN-192 # + * 0x2(AES_EN_256): AES-EN-256 # + * 0x4(AES_DE_128): AES-DE-128 # + * 0x5(AES_DE_192): AES-DE-192 # + * 0x6(AES_DE_256): AES-DE-256 + * & + */ + +#define AES_MODE 0x00000007 +#define AES_MODE_M (AES_MODE_V << AES_MODE_S) +#define AES_MODE_V 0x00000007 +#define AES_MODE_S 0 + +/* AES_ENDIAN_REG register + * Endian configuration register + */ + +#define AES_ENDIAN_REG (DR_REG_AES_BASE + 0x44) + +/* AES_ENDIAN : R/W; bitpos: [5:0]; default: 0; + * Defines the endianness of input and output texts. + * & + * [1:0] key endian # + * [3:2] text_in endian or in_stream endian # + * [5:4] text_out endian or out_stream endian # + * & + */ + +#define AES_ENDIAN 0x0000003F +#define AES_ENDIAN_M (AES_ENDIAN_V << AES_ENDIAN_S) +#define AES_ENDIAN_V 0x0000003F +#define AES_ENDIAN_S 0 + +/* AES_TRIGGER_REG register + * Operation start controlling register + */ + +#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48) + +/* AES_TRIGGER : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to start AES operation. + */ + +#define AES_TRIGGER (BIT(0)) +#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S) +#define AES_TRIGGER_V 0x00000001 +#define AES_TRIGGER_S 0 + +/* AES_STATE_REG register + * Operation status register + */ + +#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c) + +/* AES_STATE : RO; bitpos: [1:0]; default: 0; + * Stores the working status of the AES Accelerator. For details, see Table + * 3 for Typical AES working mode and Table 9 for DMA AES working mode. + * For typical AES; 0 = idle; 1 = busy. + * For DMA-AES; 0 = idle; 1 = busy; 2 = calculation_done. + */ + +#define AES_STATE 0x00000003 +#define AES_STATE_M (AES_STATE_V << AES_STATE_S) +#define AES_STATE_V 0x00000003 +#define AES_STATE_S 0 + +/* AES_IV_0_REG register + * initialization vector + */ + +#define AES_IV_0_REG (DR_REG_AES_BASE + 0x50) + +/* AES_IV_0 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 0th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_0 0xFFFFFFFF +#define AES_IV_0_M (AES_IV_0_V << AES_IV_0_S) +#define AES_IV_0_V 0xFFFFFFFF +#define AES_IV_0_S 0 + +/* AES_IV_1_REG register + * initialization vector + */ + +#define AES_IV_1_REG (DR_REG_AES_BASE + 0x54) + +/* AES_IV_1 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 1th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_1 0xFFFFFFFF +#define AES_IV_1_M (AES_IV_1_V << AES_IV_1_S) +#define AES_IV_1_V 0xFFFFFFFF +#define AES_IV_1_S 0 + +/* AES_IV_2_REG register + * initialization vector + */ + +#define AES_IV_2_REG (DR_REG_AES_BASE + 0x58) + +/* AES_IV_2 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 2th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_2 0xFFFFFFFF +#define AES_IV_2_M (AES_IV_2_V << AES_IV_2_S) +#define AES_IV_2_V 0xFFFFFFFF +#define AES_IV_2_S 0 + +/* AES_IV_3_REG register + * initialization vector + */ + +#define AES_IV_3_REG (DR_REG_AES_BASE + 0x5c) + +/* AES_IV_3 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 3th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_3 0xFFFFFFFF +#define AES_IV_3_M (AES_IV_3_V << AES_IV_3_S) +#define AES_IV_3_V 0xFFFFFFFF +#define AES_IV_3_S 0 + +/* AES_H_0_REG register + * GCM hash subkey + */ + +#define AES_H_0_REG (DR_REG_AES_BASE + 0x60) + +/* AES_H_0 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_0 0xFFFFFFFF +#define AES_H_0_M (AES_H_0_V << AES_H_0_S) +#define AES_H_0_V 0xFFFFFFFF +#define AES_H_0_S 0 + +/* AES_H_1_REG register + * GCM hash subkey + */ + +#define AES_H_1_REG (DR_REG_AES_BASE + 0x64) + +/* AES_H_1 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_1 0xFFFFFFFF +#define AES_H_1_M (AES_H_1_V << AES_H_1_S) +#define AES_H_1_V 0xFFFFFFFF +#define AES_H_1_S 0 + +/* AES_H_2_REG register + * GCM hash subkey + */ + +#define AES_H_2_REG (DR_REG_AES_BASE + 0x68) + +/* AES_H_2 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_2 0xFFFFFFFF +#define AES_H_2_M (AES_H_2_V << AES_H_2_S) +#define AES_H_2_V 0xFFFFFFFF +#define AES_H_2_S 0 + +/* AES_H_3_REG register + * GCM hash subkey + */ + +#define AES_H_3_REG (DR_REG_AES_BASE + 0x6c) + +/* AES_H_3 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_3 0xFFFFFFFF +#define AES_H_3_M (AES_H_3_V << AES_H_3_S) +#define AES_H_3_V 0xFFFFFFFF +#define AES_H_3_S 0 + +/* AES_J0_0_REG register + * J0 + */ + +#define AES_J0_0_REG (DR_REG_AES_BASE + 0x70) + +/* AES_J0_0 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 0th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_0 0xFFFFFFFF +#define AES_J0_0_M (AES_J0_0_V << AES_J0_0_S) +#define AES_J0_0_V 0xFFFFFFFF +#define AES_J0_0_S 0 + +/* AES_J0_1_REG register + * J0 + */ + +#define AES_J0_1_REG (DR_REG_AES_BASE + 0x74) + +/* AES_J0_1 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 1th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_1 0xFFFFFFFF +#define AES_J0_1_M (AES_J0_1_V << AES_J0_1_S) +#define AES_J0_1_V 0xFFFFFFFF +#define AES_J0_1_S 0 + +/* AES_J0_2_REG register + * J0 + */ + +#define AES_J0_2_REG (DR_REG_AES_BASE + 0x78) + +/* AES_J0_2 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 2th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_2 0xFFFFFFFF +#define AES_J0_2_M (AES_J0_2_V << AES_J0_2_S) +#define AES_J0_2_V 0xFFFFFFFF +#define AES_J0_2_S 0 + +/* AES_J0_3_REG register + * J0 + */ + +#define AES_J0_3_REG (DR_REG_AES_BASE + 0x7c) + +/* AES_J0_3 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 3th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_3 0xFFFFFFFF +#define AES_J0_3_M (AES_J0_3_V << AES_J0_3_S) +#define AES_J0_3_V 0xFFFFFFFF +#define AES_J0_3_S 0 + +/* AES_T0_0_REG register + * T0 + */ + +#define AES_T0_0_REG (DR_REG_AES_BASE + 0x80) + +/* AES_T0_0 : RO; bitpos: [31:0]; default: 0; + * This register stores the 0th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_0 0xFFFFFFFF +#define AES_T0_0_M (AES_T0_0_V << AES_T0_0_S) +#define AES_T0_0_V 0xFFFFFFFF +#define AES_T0_0_S 0 + +/* AES_T0_1_REG register + * T0 + */ + +#define AES_T0_1_REG (DR_REG_AES_BASE + 0x84) + +/* AES_T0_1 : RO; bitpos: [31:0]; default: 0; + * This register stores the 1th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_1 0xFFFFFFFF +#define AES_T0_1_M (AES_T0_1_V << AES_T0_1_S) +#define AES_T0_1_V 0xFFFFFFFF +#define AES_T0_1_S 0 + +/* AES_T0_2_REG register + * T0 + */ + +#define AES_T0_2_REG (DR_REG_AES_BASE + 0x88) + +/* AES_T0_2 : RO; bitpos: [31:0]; default: 0; + * This register stores the 2th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_2 0xFFFFFFFF +#define AES_T0_2_M (AES_T0_2_V << AES_T0_2_S) +#define AES_T0_2_V 0xFFFFFFFF +#define AES_T0_2_S 0 + +/* AES_T0_3_REG register + * T0 + */ + +#define AES_T0_3_REG (DR_REG_AES_BASE + 0x8c) + +/* AES_T0_3 : RO; bitpos: [31:0]; default: 0; + * This register stores the 3th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_3 0xFFFFFFFF +#define AES_T0_3_M (AES_T0_3_V << AES_T0_3_S) +#define AES_T0_3_V 0xFFFFFFFF +#define AES_T0_3_S 0 + +/* AES_DMA_ENABLE_REG register + * DMA enable register + */ + +#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90) + +/* AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0; + * Defines the working mode of the AES Accelerator. For details, see Table 1. + * 1'h0: typical AES operation + * 1'h1: DMA-AES operation + */ + +#define AES_DMA_ENABLE (BIT(0)) +#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S) +#define AES_DMA_ENABLE_V 0x00000001 +#define AES_DMA_ENABLE_S 0 + +/* AES_BLOCK_MODE_REG register + * Block operation type register + */ + +#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94) + +/* AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0; + * Defines the operation type of the AES Accelerator operating under the + * DMA-AES working mode. For details, see Table 8. + * & + * 3'h0(BLOCK_MODE_ECB): ECB # + * 3'h1(BLOCK_MODE_CBC): CBC # + * 3'h2(BLOCK_MODE_OFB): OFB # + * 3'h3(BLOCK_MODE_CTR): CTR # + * 3'h4(BLOCK_MODE_CFB8): CFB-8 # + * 3'h5(BLOCK_MODE_CFB128): CFB-128 # + * 3'h6(BLOCK_MODE_GCM): GCM + * & + */ + +#define AES_BLOCK_MODE 0x00000007 +#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S) +#define AES_BLOCK_MODE_V 0x00000007 +#define AES_BLOCK_MODE_S 0 + +/* AES_BLOCK_NUM_REG register + * Block number configuration register + */ + +#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98) + +/* AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; + * Stores the Block Number of plaintext or cipertext when the AES + * Accelerator operates under the DMA-AES working mode. For details, see + * Section 1.5.4. + */ + +#define AES_BLOCK_NUM 0xFFFFFFFF +#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S) +#define AES_BLOCK_NUM_V 0xFFFFFFFF +#define AES_BLOCK_NUM_S 0 + +/* AES_INC_SEL_REG register + * Standard incrementing function register + */ + +#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c) + +/* AES_INC_SEL : R/W; bitpos: [0]; default: 0; + * Defines the Standard Incrementing Function for CTR block operation. Set + * this bit to 0 or 1 to choose INC 32 or INC 128 . + */ + +#define AES_INC_SEL (BIT(0)) +#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S) +#define AES_INC_SEL_V 0x00000001 +#define AES_INC_SEL_S 0 + +/* AES_AAD_BLOCK_NUM_REG register + * AAD block number configuration register + */ + +#define AES_AAD_BLOCK_NUM_REG (DR_REG_AES_BASE + 0xa0) + +/* AES_AAD_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; + * Stores the ADD Block Number for the GCM operation. + */ + +#define AES_AAD_BLOCK_NUM 0xFFFFFFFF +#define AES_AAD_BLOCK_NUM_M (AES_AAD_BLOCK_NUM_V << AES_AAD_BLOCK_NUM_S) +#define AES_AAD_BLOCK_NUM_V 0xFFFFFFFF +#define AES_AAD_BLOCK_NUM_S 0 + +/* AES_REMAINDER_BIT_NUM_REG register + * Remainder bit number of plaintext/ciphertext + */ + +#define AES_REMAINDER_BIT_NUM_REG (DR_REG_AES_BASE + 0xa4) + +/* AES_REMAINDER_BIT_NUM : R/W; bitpos: [6:0]; default: 0; + * Stores the Remainder Bit Number for the GCM operation. + */ + +#define AES_REMAINDER_BIT_NUM 0x0000007F +#define AES_REMAINDER_BIT_NUM_M (AES_REMAINDER_BIT_NUM_V << AES_REMAINDER_BIT_NUM_S) +#define AES_REMAINDER_BIT_NUM_V 0x0000007F +#define AES_REMAINDER_BIT_NUM_S 0 + +/* AES_CONTINUE_REG register + * Operation continue controlling register + */ + +#define AES_CONTINUE_REG (DR_REG_AES_BASE + 0xa8) + +/* AES_CONTINUE : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to continue AES operation. + */ + +#define AES_CONTINUE (BIT(0)) +#define AES_CONTINUE_M (AES_CONTINUE_V << AES_CONTINUE_S) +#define AES_CONTINUE_V 0x00000001 +#define AES_CONTINUE_S 0 + +/* AES_INT_CLR_REG register + * DMA-AES interrupt clear register + */ + +#define AES_INT_CLR_REG (DR_REG_AES_BASE + 0xac) + +/* AES_INT_CLR : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to clear AES interrupt. + */ + +#define AES_INT_CLR (BIT(0)) +#define AES_INT_CLR_M (AES_INT_CLR_V << AES_INT_CLR_S) +#define AES_INT_CLR_V 0x00000001 +#define AES_INT_CLR_S 0 + +/* AES_INT_ENA_REG register + * DMA-AES interrupt enable register + */ + +#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0) + +/* AES_INT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. + */ + +#define AES_INT_ENA (BIT(0)) +#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S) +#define AES_INT_ENA_V 0x00000001 +#define AES_INT_ENA_S 0 + +/* AES_DATE_REG register + * Version control register + */ + +#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4) + +/* AES_DATE : R/W; bitpos: [29:0]; default: 538510612; + * Version control register + */ + +#define AES_DATE 0x3FFFFFFF +#define AES_DATE_M (AES_DATE_V << AES_DATE_S) +#define AES_DATE_V 0x3FFFFFFF +#define AES_DATE_S 0 + +/* AES_DMA_EXIT_REG register + * Operation exit controlling register + */ + +#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8) + +/* AES_DMA_EXIT : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to exit AES operation. This register is only effective + * for DMA-AES operation. + */ + +#define AES_DMA_EXIT (BIT(0)) +#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S) +#define AES_DMA_EXIT_V 0x00000001 +#define AES_DMA_EXIT_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_AES_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_cache_memory.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_cache_memory.h similarity index 93% rename from arch/risc-v/src/esp32c3/hardware/esp32c3_cache_memory.h rename to arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_cache_memory.h index 1a6e52968e867..51484d3419cfd 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_cache_memory.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_cache_memory.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_cache_memory.h + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_cache_memory.h * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -15,8 +15,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_CACHE_MEMORY_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_CACHE_MEMORY_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_CACHE_MEMORY_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_CACHE_MEMORY_H /**************************************************************************** * Included Files @@ -107,4 +107,4 @@ #define CACHE_MEMORY_IBANK0_ADDR 0x4037c000 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_CACHE_MEMORY_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_CACHE_MEMORY_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_dma.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_dma.h new file mode 100644 index 0000000000000..a31fb4845fe7a --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_dma.h @@ -0,0 +1,3898 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_dma.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_DMA_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_DMA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* DMA_INT_RAW_CH0_REG register + * DMA_INT_RAW_CH0_REG. + */ + +#define DMA_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x0) + +/* DMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx + * channel 0 is underflow. + */ + +#define DMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(12)) +#define DMA_OUTFIFO_UDF_CH0_INT_RAW_M (DMA_OUTFIFO_UDF_CH0_INT_RAW_V << DMA_OUTFIFO_UDF_CH0_INT_RAW_S) +#define DMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH0_INT_RAW_S 12 + +/* DMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx + * channel 0 is overflow. + */ + +#define DMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(11)) +#define DMA_OUTFIFO_OVF_CH0_INT_RAW_M (DMA_OUTFIFO_OVF_CH0_INT_RAW_V << DMA_OUTFIFO_OVF_CH0_INT_RAW_S) +#define DMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH0_INT_RAW_S 11 + +/* DMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx + * channel 0 is underflow. + */ + +#define DMA_INFIFO_UDF_CH0_INT_RAW (BIT(10)) +#define DMA_INFIFO_UDF_CH0_INT_RAW_M (DMA_INFIFO_UDF_CH0_INT_RAW_V << DMA_INFIFO_UDF_CH0_INT_RAW_S) +#define DMA_INFIFO_UDF_CH0_INT_RAW_V 0x00000001 +#define DMA_INFIFO_UDF_CH0_INT_RAW_S 10 + +/* DMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx + * channel 0 is overflow. + */ + +#define DMA_INFIFO_OVF_CH0_INT_RAW (BIT(9)) +#define DMA_INFIFO_OVF_CH0_INT_RAW_M (DMA_INFIFO_OVF_CH0_INT_RAW_V << DMA_INFIFO_OVF_CH0_INT_RAW_S) +#define DMA_INFIFO_OVF_CH0_INT_RAW_V 0x00000001 +#define DMA_INFIFO_OVF_CH0_INT_RAW_S 9 + +/* DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a + * outlink (includes one link descriptor or few link descriptors) is + * transmitted out for Tx channel 0. + */ + +#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S) +#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 8 + +/* DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by + * inlink is full and receiving data is not completed, but there is no more + * inlink for Rx channel 0. + */ + +#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S) +#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 7 + +/* DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink + * descriptor error, including owner error, the second and third word error + * of outlink descriptor for Tx channel 0. + */ + +#define DMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_M (DMA_OUT_DSCR_ERR_CH0_INT_RAW_V << DMA_OUT_DSCR_ERR_CH0_INT_RAW_S) +#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_S 6 + +/* DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink + * descriptor error, including owner error, the second and third word error + * of inlink descriptor for Rx channel 0. + */ + +#define DMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_RAW_M (DMA_IN_DSCR_ERR_CH0_INT_RAW_V << DMA_IN_DSCR_ERR_CH0_INT_RAW_S) +#define DMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH0_INT_RAW_S 5 + +/* DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one outlink descriptor has been read from memory for Tx channel 0. + */ + +#define DMA_OUT_EOF_CH0_INT_RAW (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_RAW_M (DMA_OUT_EOF_CH0_INT_RAW_V << DMA_OUT_EOF_CH0_INT_RAW_S) +#define DMA_OUT_EOF_CH0_INT_RAW_V 0x00000001 +#define DMA_OUT_EOF_CH0_INT_RAW_S 4 + +/* DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one outlink descriptor has been transmitted to peripherals for Tx channel + * 0. + */ + +#define DMA_OUT_DONE_CH0_INT_RAW (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_RAW_M (DMA_OUT_DONE_CH0_INT_RAW_V << DMA_OUT_DONE_CH0_INT_RAW_S) +#define DMA_OUT_DONE_CH0_INT_RAW_V 0x00000001 +#define DMA_OUT_DONE_CH0_INT_RAW_S 3 + +/* DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected + * only in the case that the peripheral is UHCI0 for Rx channel 0. For other + * peripherals, this raw interrupt is reserved. + */ + +#define DMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_RAW_M (DMA_IN_ERR_EOF_CH0_INT_RAW_V << DMA_IN_ERR_EOF_CH0_INT_RAW_S) +#define DMA_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001 +#define DMA_IN_ERR_EOF_CH0_INT_RAW_S 2 + +/* DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one inlink descriptor has been received for Rx channel 0. For UHCI0, the + * raw interrupt bit turns to high level when the last data pointed by one + * inlink descriptor has been received and no data error is detected for Rx + * channel 0. + */ + +#define DMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_RAW_M (DMA_IN_SUC_EOF_CH0_INT_RAW_V << DMA_IN_SUC_EOF_CH0_INT_RAW_S) +#define DMA_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001 +#define DMA_IN_SUC_EOF_CH0_INT_RAW_S 1 + +/* DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one inlink descriptor has been received for Rx channel 0. + */ + +#define DMA_IN_DONE_CH0_INT_RAW (BIT(0)) +#define DMA_IN_DONE_CH0_INT_RAW_M (DMA_IN_DONE_CH0_INT_RAW_V << DMA_IN_DONE_CH0_INT_RAW_S) +#define DMA_IN_DONE_CH0_INT_RAW_V 0x00000001 +#define DMA_IN_DONE_CH0_INT_RAW_S 0 + +/* DMA_INT_ST_CH0_REG register + * DMA_INT_ST_CH0_REG. + */ + +#define DMA_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x4) + +/* DMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_UDF_CH0_INT_ST (BIT(12)) +#define DMA_OUTFIFO_UDF_CH0_INT_ST_M (DMA_OUTFIFO_UDF_CH0_INT_ST_V << DMA_OUTFIFO_UDF_CH0_INT_ST_S) +#define DMA_OUTFIFO_UDF_CH0_INT_ST_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH0_INT_ST_S 12 + +/* DMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_OVF_CH0_INT_ST (BIT(11)) +#define DMA_OUTFIFO_OVF_CH0_INT_ST_M (DMA_OUTFIFO_OVF_CH0_INT_ST_V << DMA_OUTFIFO_OVF_CH0_INT_ST_S) +#define DMA_OUTFIFO_OVF_CH0_INT_ST_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH0_INT_ST_S 11 + +/* DMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_UDF_CH0_INT_ST (BIT(10)) +#define DMA_INFIFO_UDF_CH0_INT_ST_M (DMA_INFIFO_UDF_CH0_INT_ST_V << DMA_INFIFO_UDF_CH0_INT_ST_S) +#define DMA_INFIFO_UDF_CH0_INT_ST_V 0x00000001 +#define DMA_INFIFO_UDF_CH0_INT_ST_S 10 + +/* DMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_OVF_CH0_INT_ST (BIT(9)) +#define DMA_INFIFO_OVF_CH0_INT_ST_M (DMA_INFIFO_OVF_CH0_INT_ST_V << DMA_INFIFO_OVF_CH0_INT_ST_S) +#define DMA_INFIFO_OVF_CH0_INT_ST_V 0x00000001 +#define DMA_INFIFO_OVF_CH0_INT_ST_S 9 + +/* DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_M (DMA_OUT_TOTAL_EOF_CH0_INT_ST_V << DMA_OUT_TOTAL_EOF_CH0_INT_ST_S) +#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_S 8 + +/* DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_M (DMA_IN_DSCR_EMPTY_CH0_INT_ST_V << DMA_IN_DSCR_EMPTY_CH0_INT_ST_S) +#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_S 7 + +/* DMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_ST_M (DMA_OUT_DSCR_ERR_CH0_INT_ST_V << DMA_OUT_DSCR_ERR_CH0_INT_ST_S) +#define DMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH0_INT_ST_S 6 + +/* DMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_ERR_CH0_INT_ST (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_ST_M (DMA_IN_DSCR_ERR_CH0_INT_ST_V << DMA_IN_DSCR_ERR_CH0_INT_ST_S) +#define DMA_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH0_INT_ST_S 5 + +/* DMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_EOF_CH0_INT_ST (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_ST_M (DMA_OUT_EOF_CH0_INT_ST_V << DMA_OUT_EOF_CH0_INT_ST_S) +#define DMA_OUT_EOF_CH0_INT_ST_V 0x00000001 +#define DMA_OUT_EOF_CH0_INT_ST_S 4 + +/* DMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ + +#define DMA_OUT_DONE_CH0_INT_ST (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_ST_M (DMA_OUT_DONE_CH0_INT_ST_V << DMA_OUT_DONE_CH0_INT_ST_S) +#define DMA_OUT_DONE_CH0_INT_ST_V 0x00000001 +#define DMA_OUT_DONE_CH0_INT_ST_S 3 + +/* DMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ + +#define DMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_ST_M (DMA_IN_ERR_EOF_CH0_INT_ST_V << DMA_IN_ERR_EOF_CH0_INT_ST_S) +#define DMA_IN_ERR_EOF_CH0_INT_ST_V 0x00000001 +#define DMA_IN_ERR_EOF_CH0_INT_ST_S 2 + +/* DMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ + +#define DMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_ST_M (DMA_IN_SUC_EOF_CH0_INT_ST_V << DMA_IN_SUC_EOF_CH0_INT_ST_S) +#define DMA_IN_SUC_EOF_CH0_INT_ST_V 0x00000001 +#define DMA_IN_SUC_EOF_CH0_INT_ST_S 1 + +/* DMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ + +#define DMA_IN_DONE_CH0_INT_ST (BIT(0)) +#define DMA_IN_DONE_CH0_INT_ST_M (DMA_IN_DONE_CH0_INT_ST_V << DMA_IN_DONE_CH0_INT_ST_S) +#define DMA_IN_DONE_CH0_INT_ST_V 0x00000001 +#define DMA_IN_DONE_CH0_INT_ST_S 0 + +/* DMA_INT_ENA_CH0_REG register + * DMA_INT_ENA_CH0_REG. + */ + +#define DMA_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x8) + +/* DMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(12)) +#define DMA_OUTFIFO_UDF_CH0_INT_ENA_M (DMA_OUTFIFO_UDF_CH0_INT_ENA_V << DMA_OUTFIFO_UDF_CH0_INT_ENA_S) +#define DMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH0_INT_ENA_S 12 + +/* DMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(11)) +#define DMA_OUTFIFO_OVF_CH0_INT_ENA_M (DMA_OUTFIFO_OVF_CH0_INT_ENA_V << DMA_OUTFIFO_OVF_CH0_INT_ENA_S) +#define DMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH0_INT_ENA_S 11 + +/* DMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_UDF_CH0_INT_ENA (BIT(10)) +#define DMA_INFIFO_UDF_CH0_INT_ENA_M (DMA_INFIFO_UDF_CH0_INT_ENA_V << DMA_INFIFO_UDF_CH0_INT_ENA_S) +#define DMA_INFIFO_UDF_CH0_INT_ENA_V 0x00000001 +#define DMA_INFIFO_UDF_CH0_INT_ENA_S 10 + +/* DMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_OVF_CH0_INT_ENA (BIT(9)) +#define DMA_INFIFO_OVF_CH0_INT_ENA_M (DMA_INFIFO_OVF_CH0_INT_ENA_V << DMA_INFIFO_OVF_CH0_INT_ENA_S) +#define DMA_INFIFO_OVF_CH0_INT_ENA_V 0x00000001 +#define DMA_INFIFO_OVF_CH0_INT_ENA_S 9 + +/* DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S) +#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 8 + +/* DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S) +#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 7 + +/* DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_M (DMA_OUT_DSCR_ERR_CH0_INT_ENA_V << DMA_OUT_DSCR_ERR_CH0_INT_ENA_S) +#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_S 6 + +/* DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_ENA_M (DMA_IN_DSCR_ERR_CH0_INT_ENA_V << DMA_IN_DSCR_ERR_CH0_INT_ENA_S) +#define DMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH0_INT_ENA_S 5 + +/* DMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_EOF_CH0_INT_ENA (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_ENA_M (DMA_OUT_EOF_CH0_INT_ENA_V << DMA_OUT_EOF_CH0_INT_ENA_S) +#define DMA_OUT_EOF_CH0_INT_ENA_V 0x00000001 +#define DMA_OUT_EOF_CH0_INT_ENA_S 4 + +/* DMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ + +#define DMA_OUT_DONE_CH0_INT_ENA (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_ENA_M (DMA_OUT_DONE_CH0_INT_ENA_V << DMA_OUT_DONE_CH0_INT_ENA_S) +#define DMA_OUT_DONE_CH0_INT_ENA_V 0x00000001 +#define DMA_OUT_DONE_CH0_INT_ENA_S 3 + +/* DMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ + +#define DMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_ENA_M (DMA_IN_ERR_EOF_CH0_INT_ENA_V << DMA_IN_ERR_EOF_CH0_INT_ENA_S) +#define DMA_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001 +#define DMA_IN_ERR_EOF_CH0_INT_ENA_S 2 + +/* DMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ + +#define DMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_ENA_M (DMA_IN_SUC_EOF_CH0_INT_ENA_V << DMA_IN_SUC_EOF_CH0_INT_ENA_S) +#define DMA_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001 +#define DMA_IN_SUC_EOF_CH0_INT_ENA_S 1 + +/* DMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ + +#define DMA_IN_DONE_CH0_INT_ENA (BIT(0)) +#define DMA_IN_DONE_CH0_INT_ENA_M (DMA_IN_DONE_CH0_INT_ENA_V << DMA_IN_DONE_CH0_INT_ENA_S) +#define DMA_IN_DONE_CH0_INT_ENA_V 0x00000001 +#define DMA_IN_DONE_CH0_INT_ENA_S 0 + +/* DMA_INT_CLR_CH0_REG register + * DMA_INT_CLR_CH0_REG. + */ + +#define DMA_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0xc) + +/* DMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(12)) +#define DMA_OUTFIFO_UDF_CH0_INT_CLR_M (DMA_OUTFIFO_UDF_CH0_INT_CLR_V << DMA_OUTFIFO_UDF_CH0_INT_CLR_S) +#define DMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH0_INT_CLR_S 12 + +/* DMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(11)) +#define DMA_OUTFIFO_OVF_CH0_INT_CLR_M (DMA_OUTFIFO_OVF_CH0_INT_CLR_V << DMA_OUTFIFO_OVF_CH0_INT_CLR_S) +#define DMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH0_INT_CLR_S 11 + +/* DMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_UDF_CH0_INT_CLR (BIT(10)) +#define DMA_INFIFO_UDF_CH0_INT_CLR_M (DMA_INFIFO_UDF_CH0_INT_CLR_V << DMA_INFIFO_UDF_CH0_INT_CLR_S) +#define DMA_INFIFO_UDF_CH0_INT_CLR_V 0x00000001 +#define DMA_INFIFO_UDF_CH0_INT_CLR_S 10 + +/* DMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_OVF_CH0_INT_CLR (BIT(9)) +#define DMA_INFIFO_OVF_CH0_INT_CLR_M (DMA_INFIFO_OVF_CH0_INT_CLR_V << DMA_INFIFO_OVF_CH0_INT_CLR_S) +#define DMA_INFIFO_OVF_CH0_INT_CLR_V 0x00000001 +#define DMA_INFIFO_OVF_CH0_INT_CLR_S 9 + +/* DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S) +#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 8 + +/* DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S) +#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 7 + +/* DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_M (DMA_OUT_DSCR_ERR_CH0_INT_CLR_V << DMA_OUT_DSCR_ERR_CH0_INT_CLR_S) +#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_S 6 + +/* DMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_CLR_M (DMA_IN_DSCR_ERR_CH0_INT_CLR_V << DMA_IN_DSCR_ERR_CH0_INT_CLR_S) +#define DMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH0_INT_CLR_S 5 + +/* DMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_EOF_CH0_INT_CLR (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_CLR_M (DMA_OUT_EOF_CH0_INT_CLR_V << DMA_OUT_EOF_CH0_INT_CLR_S) +#define DMA_OUT_EOF_CH0_INT_CLR_V 0x00000001 +#define DMA_OUT_EOF_CH0_INT_CLR_S 4 + +/* DMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ + +#define DMA_OUT_DONE_CH0_INT_CLR (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_CLR_M (DMA_OUT_DONE_CH0_INT_CLR_V << DMA_OUT_DONE_CH0_INT_CLR_S) +#define DMA_OUT_DONE_CH0_INT_CLR_V 0x00000001 +#define DMA_OUT_DONE_CH0_INT_CLR_S 3 + +/* DMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ + +#define DMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_CLR_M (DMA_IN_ERR_EOF_CH0_INT_CLR_V << DMA_IN_ERR_EOF_CH0_INT_CLR_S) +#define DMA_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001 +#define DMA_IN_ERR_EOF_CH0_INT_CLR_S 2 + +/* DMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ + +#define DMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_CLR_M (DMA_IN_SUC_EOF_CH0_INT_CLR_V << DMA_IN_SUC_EOF_CH0_INT_CLR_S) +#define DMA_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001 +#define DMA_IN_SUC_EOF_CH0_INT_CLR_S 1 + +/* DMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ + +#define DMA_IN_DONE_CH0_INT_CLR (BIT(0)) +#define DMA_IN_DONE_CH0_INT_CLR_M (DMA_IN_DONE_CH0_INT_CLR_V << DMA_IN_DONE_CH0_INT_CLR_S) +#define DMA_IN_DONE_CH0_INT_CLR_V 0x00000001 +#define DMA_IN_DONE_CH0_INT_CLR_S 0 + +/* DMA_INT_RAW_CH1_REG register + * DMA_INT_RAW_CH1_REG. + */ + +#define DMA_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x10) + +/* DMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx + * channel 1 is underflow. + */ + +#define DMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(12)) +#define DMA_OUTFIFO_UDF_CH1_INT_RAW_M (DMA_OUTFIFO_UDF_CH1_INT_RAW_V << DMA_OUTFIFO_UDF_CH1_INT_RAW_S) +#define DMA_OUTFIFO_UDF_CH1_INT_RAW_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH1_INT_RAW_S 12 + +/* DMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx + * channel 1 is overflow. + */ + +#define DMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(11)) +#define DMA_OUTFIFO_OVF_CH1_INT_RAW_M (DMA_OUTFIFO_OVF_CH1_INT_RAW_V << DMA_OUTFIFO_OVF_CH1_INT_RAW_S) +#define DMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH1_INT_RAW_S 11 + +/* DMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx + * channel 1 is underflow. + */ + +#define DMA_INFIFO_UDF_CH1_INT_RAW (BIT(10)) +#define DMA_INFIFO_UDF_CH1_INT_RAW_M (DMA_INFIFO_UDF_CH1_INT_RAW_V << DMA_INFIFO_UDF_CH1_INT_RAW_S) +#define DMA_INFIFO_UDF_CH1_INT_RAW_V 0x00000001 +#define DMA_INFIFO_UDF_CH1_INT_RAW_S 10 + +/* DMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx + * channel 1 is overflow. + */ + +#define DMA_INFIFO_OVF_CH1_INT_RAW (BIT(9)) +#define DMA_INFIFO_OVF_CH1_INT_RAW_M (DMA_INFIFO_OVF_CH1_INT_RAW_V << DMA_INFIFO_OVF_CH1_INT_RAW_S) +#define DMA_INFIFO_OVF_CH1_INT_RAW_V 0x00000001 +#define DMA_INFIFO_OVF_CH1_INT_RAW_S 9 + +/* DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a + * outlink (includes one link descriptor or few link descriptors) is + * transmitted out for Tx channel 1. + */ + +#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S) +#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 8 + +/* DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by + * inlink is full and receiving data is not completed, but there is no more + * inlink for Rx channel 1. + */ + +#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S) +#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 7 + +/* DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink + * descriptor error, including owner error, the second and third word error + * of outlink descriptor for Tx channel 1. + */ + +#define DMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_M (DMA_OUT_DSCR_ERR_CH1_INT_RAW_V << DMA_OUT_DSCR_ERR_CH1_INT_RAW_S) +#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_S 6 + +/* DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink + * descriptor error, including owner error, the second and third word error + * of inlink descriptor for Rx channel 1. + */ + +#define DMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_RAW_M (DMA_IN_DSCR_ERR_CH1_INT_RAW_V << DMA_IN_DSCR_ERR_CH1_INT_RAW_S) +#define DMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH1_INT_RAW_S 5 + +/* DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one outlink descriptor has been read from memory for Tx channel 1. + */ + +#define DMA_OUT_EOF_CH1_INT_RAW (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_RAW_M (DMA_OUT_EOF_CH1_INT_RAW_V << DMA_OUT_EOF_CH1_INT_RAW_S) +#define DMA_OUT_EOF_CH1_INT_RAW_V 0x00000001 +#define DMA_OUT_EOF_CH1_INT_RAW_S 4 + +/* DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one outlink descriptor has been transmitted to peripherals for Tx channel + * 1. + */ + +#define DMA_OUT_DONE_CH1_INT_RAW (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_RAW_M (DMA_OUT_DONE_CH1_INT_RAW_V << DMA_OUT_DONE_CH1_INT_RAW_S) +#define DMA_OUT_DONE_CH1_INT_RAW_V 0x00000001 +#define DMA_OUT_DONE_CH1_INT_RAW_S 3 + +/* DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected + * only in the case that the peripheral is UHCI0 for Rx channel 1. For other + * peripherals, this raw interrupt is reserved. + */ + +#define DMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_RAW_M (DMA_IN_ERR_EOF_CH1_INT_RAW_V << DMA_IN_ERR_EOF_CH1_INT_RAW_S) +#define DMA_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001 +#define DMA_IN_ERR_EOF_CH1_INT_RAW_S 2 + +/* DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one inlink descriptor has been received for Rx channel 1. For UHCI0, the + * raw interrupt bit turns to high level when the last data pointed by one + * inlink descriptor has been received and no data error is detected for Rx + * channel 1. + */ + +#define DMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_RAW_M (DMA_IN_SUC_EOF_CH1_INT_RAW_V << DMA_IN_SUC_EOF_CH1_INT_RAW_S) +#define DMA_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001 +#define DMA_IN_SUC_EOF_CH1_INT_RAW_S 1 + +/* DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one inlink descriptor has been received for Rx channel 1. + */ + +#define DMA_IN_DONE_CH1_INT_RAW (BIT(0)) +#define DMA_IN_DONE_CH1_INT_RAW_M (DMA_IN_DONE_CH1_INT_RAW_V << DMA_IN_DONE_CH1_INT_RAW_S) +#define DMA_IN_DONE_CH1_INT_RAW_V 0x00000001 +#define DMA_IN_DONE_CH1_INT_RAW_S 0 + +/* DMA_INT_ST_CH1_REG register + * DMA_INT_ST_CH1_REG. + */ + +#define DMA_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x14) + +/* DMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_UDF_CH1_INT_ST (BIT(12)) +#define DMA_OUTFIFO_UDF_CH1_INT_ST_M (DMA_OUTFIFO_UDF_CH1_INT_ST_V << DMA_OUTFIFO_UDF_CH1_INT_ST_S) +#define DMA_OUTFIFO_UDF_CH1_INT_ST_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH1_INT_ST_S 12 + +/* DMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_OVF_CH1_INT_ST (BIT(11)) +#define DMA_OUTFIFO_OVF_CH1_INT_ST_M (DMA_OUTFIFO_OVF_CH1_INT_ST_V << DMA_OUTFIFO_OVF_CH1_INT_ST_S) +#define DMA_OUTFIFO_OVF_CH1_INT_ST_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH1_INT_ST_S 11 + +/* DMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_UDF_CH1_INT_ST (BIT(10)) +#define DMA_INFIFO_UDF_CH1_INT_ST_M (DMA_INFIFO_UDF_CH1_INT_ST_V << DMA_INFIFO_UDF_CH1_INT_ST_S) +#define DMA_INFIFO_UDF_CH1_INT_ST_V 0x00000001 +#define DMA_INFIFO_UDF_CH1_INT_ST_S 10 + +/* DMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_OVF_CH1_INT_ST (BIT(9)) +#define DMA_INFIFO_OVF_CH1_INT_ST_M (DMA_INFIFO_OVF_CH1_INT_ST_V << DMA_INFIFO_OVF_CH1_INT_ST_S) +#define DMA_INFIFO_OVF_CH1_INT_ST_V 0x00000001 +#define DMA_INFIFO_OVF_CH1_INT_ST_S 9 + +/* DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_M (DMA_OUT_TOTAL_EOF_CH1_INT_ST_V << DMA_OUT_TOTAL_EOF_CH1_INT_ST_S) +#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_S 8 + +/* DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_M (DMA_IN_DSCR_EMPTY_CH1_INT_ST_V << DMA_IN_DSCR_EMPTY_CH1_INT_ST_S) +#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_S 7 + +/* DMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_ST_M (DMA_OUT_DSCR_ERR_CH1_INT_ST_V << DMA_OUT_DSCR_ERR_CH1_INT_ST_S) +#define DMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH1_INT_ST_S 6 + +/* DMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_ERR_CH1_INT_ST (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_ST_M (DMA_IN_DSCR_ERR_CH1_INT_ST_V << DMA_IN_DSCR_ERR_CH1_INT_ST_S) +#define DMA_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH1_INT_ST_S 5 + +/* DMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_EOF_CH1_INT_ST (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_ST_M (DMA_OUT_EOF_CH1_INT_ST_V << DMA_OUT_EOF_CH1_INT_ST_S) +#define DMA_OUT_EOF_CH1_INT_ST_V 0x00000001 +#define DMA_OUT_EOF_CH1_INT_ST_S 4 + +/* DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ + +#define DMA_OUT_DONE_CH1_INT_ST (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_ST_M (DMA_OUT_DONE_CH1_INT_ST_V << DMA_OUT_DONE_CH1_INT_ST_S) +#define DMA_OUT_DONE_CH1_INT_ST_V 0x00000001 +#define DMA_OUT_DONE_CH1_INT_ST_S 3 + +/* DMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ + +#define DMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_ST_M (DMA_IN_ERR_EOF_CH1_INT_ST_V << DMA_IN_ERR_EOF_CH1_INT_ST_S) +#define DMA_IN_ERR_EOF_CH1_INT_ST_V 0x00000001 +#define DMA_IN_ERR_EOF_CH1_INT_ST_S 2 + +/* DMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ + +#define DMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_ST_M (DMA_IN_SUC_EOF_CH1_INT_ST_V << DMA_IN_SUC_EOF_CH1_INT_ST_S) +#define DMA_IN_SUC_EOF_CH1_INT_ST_V 0x00000001 +#define DMA_IN_SUC_EOF_CH1_INT_ST_S 1 + +/* DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ + +#define DMA_IN_DONE_CH1_INT_ST (BIT(0)) +#define DMA_IN_DONE_CH1_INT_ST_M (DMA_IN_DONE_CH1_INT_ST_V << DMA_IN_DONE_CH1_INT_ST_S) +#define DMA_IN_DONE_CH1_INT_ST_V 0x00000001 +#define DMA_IN_DONE_CH1_INT_ST_S 0 + +/* DMA_INT_ENA_CH1_REG register + * DMA_INT_ENA_CH1_REG. + */ + +#define DMA_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x18) + +/* DMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_UDF_CH1_INT_ENA (BIT(12)) +#define DMA_OUTFIFO_UDF_CH1_INT_ENA_M (DMA_OUTFIFO_UDF_CH1_INT_ENA_V << DMA_OUTFIFO_UDF_CH1_INT_ENA_S) +#define DMA_OUTFIFO_UDF_CH1_INT_ENA_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH1_INT_ENA_S 12 + +/* DMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_OVF_CH1_INT_ENA (BIT(11)) +#define DMA_OUTFIFO_OVF_CH1_INT_ENA_M (DMA_OUTFIFO_OVF_CH1_INT_ENA_V << DMA_OUTFIFO_OVF_CH1_INT_ENA_S) +#define DMA_OUTFIFO_OVF_CH1_INT_ENA_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH1_INT_ENA_S 11 + +/* DMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_UDF_CH1_INT_ENA (BIT(10)) +#define DMA_INFIFO_UDF_CH1_INT_ENA_M (DMA_INFIFO_UDF_CH1_INT_ENA_V << DMA_INFIFO_UDF_CH1_INT_ENA_S) +#define DMA_INFIFO_UDF_CH1_INT_ENA_V 0x00000001 +#define DMA_INFIFO_UDF_CH1_INT_ENA_S 10 + +/* DMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_OVF_CH1_INT_ENA (BIT(9)) +#define DMA_INFIFO_OVF_CH1_INT_ENA_M (DMA_INFIFO_OVF_CH1_INT_ENA_V << DMA_INFIFO_OVF_CH1_INT_ENA_S) +#define DMA_INFIFO_OVF_CH1_INT_ENA_V 0x00000001 +#define DMA_INFIFO_OVF_CH1_INT_ENA_S 9 + +/* DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S) +#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 8 + +/* DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S) +#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 7 + +/* DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_M (DMA_OUT_DSCR_ERR_CH1_INT_ENA_V << DMA_OUT_DSCR_ERR_CH1_INT_ENA_S) +#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_S 6 + +/* DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_ENA_M (DMA_IN_DSCR_ERR_CH1_INT_ENA_V << DMA_IN_DSCR_ERR_CH1_INT_ENA_S) +#define DMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH1_INT_ENA_S 5 + +/* DMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_EOF_CH1_INT_ENA (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_ENA_M (DMA_OUT_EOF_CH1_INT_ENA_V << DMA_OUT_EOF_CH1_INT_ENA_S) +#define DMA_OUT_EOF_CH1_INT_ENA_V 0x00000001 +#define DMA_OUT_EOF_CH1_INT_ENA_S 4 + +/* DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ + +#define DMA_OUT_DONE_CH1_INT_ENA (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_ENA_M (DMA_OUT_DONE_CH1_INT_ENA_V << DMA_OUT_DONE_CH1_INT_ENA_S) +#define DMA_OUT_DONE_CH1_INT_ENA_V 0x00000001 +#define DMA_OUT_DONE_CH1_INT_ENA_S 3 + +/* DMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ + +#define DMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_ENA_M (DMA_IN_ERR_EOF_CH1_INT_ENA_V << DMA_IN_ERR_EOF_CH1_INT_ENA_S) +#define DMA_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001 +#define DMA_IN_ERR_EOF_CH1_INT_ENA_S 2 + +/* DMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ + +#define DMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_ENA_M (DMA_IN_SUC_EOF_CH1_INT_ENA_V << DMA_IN_SUC_EOF_CH1_INT_ENA_S) +#define DMA_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001 +#define DMA_IN_SUC_EOF_CH1_INT_ENA_S 1 + +/* DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ + +#define DMA_IN_DONE_CH1_INT_ENA (BIT(0)) +#define DMA_IN_DONE_CH1_INT_ENA_M (DMA_IN_DONE_CH1_INT_ENA_V << DMA_IN_DONE_CH1_INT_ENA_S) +#define DMA_IN_DONE_CH1_INT_ENA_V 0x00000001 +#define DMA_IN_DONE_CH1_INT_ENA_S 0 + +/* DMA_INT_CLR_CH1_REG register + * DMA_INT_CLR_CH1_REG. + */ + +#define DMA_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x1c) + +/* DMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_UDF_CH1_INT_CLR (BIT(12)) +#define DMA_OUTFIFO_UDF_CH1_INT_CLR_M (DMA_OUTFIFO_UDF_CH1_INT_CLR_V << DMA_OUTFIFO_UDF_CH1_INT_CLR_S) +#define DMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH1_INT_CLR_S 12 + +/* DMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_OVF_CH1_INT_CLR (BIT(11)) +#define DMA_OUTFIFO_OVF_CH1_INT_CLR_M (DMA_OUTFIFO_OVF_CH1_INT_CLR_V << DMA_OUTFIFO_OVF_CH1_INT_CLR_S) +#define DMA_OUTFIFO_OVF_CH1_INT_CLR_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH1_INT_CLR_S 11 + +/* DMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_UDF_CH1_INT_CLR (BIT(10)) +#define DMA_INFIFO_UDF_CH1_INT_CLR_M (DMA_INFIFO_UDF_CH1_INT_CLR_V << DMA_INFIFO_UDF_CH1_INT_CLR_S) +#define DMA_INFIFO_UDF_CH1_INT_CLR_V 0x00000001 +#define DMA_INFIFO_UDF_CH1_INT_CLR_S 10 + +/* DMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_OVF_CH1_INT_CLR (BIT(9)) +#define DMA_INFIFO_OVF_CH1_INT_CLR_M (DMA_INFIFO_OVF_CH1_INT_CLR_V << DMA_INFIFO_OVF_CH1_INT_CLR_S) +#define DMA_INFIFO_OVF_CH1_INT_CLR_V 0x00000001 +#define DMA_INFIFO_OVF_CH1_INT_CLR_S 9 + +/* DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S) +#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 8 + +/* DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S) +#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 7 + +/* DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_M (DMA_OUT_DSCR_ERR_CH1_INT_CLR_V << DMA_OUT_DSCR_ERR_CH1_INT_CLR_S) +#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_S 6 + +/* DMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_CLR_M (DMA_IN_DSCR_ERR_CH1_INT_CLR_V << DMA_IN_DSCR_ERR_CH1_INT_CLR_S) +#define DMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH1_INT_CLR_S 5 + +/* DMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_EOF_CH1_INT_CLR (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_CLR_M (DMA_OUT_EOF_CH1_INT_CLR_V << DMA_OUT_EOF_CH1_INT_CLR_S) +#define DMA_OUT_EOF_CH1_INT_CLR_V 0x00000001 +#define DMA_OUT_EOF_CH1_INT_CLR_S 4 + +/* DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ + +#define DMA_OUT_DONE_CH1_INT_CLR (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_CLR_M (DMA_OUT_DONE_CH1_INT_CLR_V << DMA_OUT_DONE_CH1_INT_CLR_S) +#define DMA_OUT_DONE_CH1_INT_CLR_V 0x00000001 +#define DMA_OUT_DONE_CH1_INT_CLR_S 3 + +/* DMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ + +#define DMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_CLR_M (DMA_IN_ERR_EOF_CH1_INT_CLR_V << DMA_IN_ERR_EOF_CH1_INT_CLR_S) +#define DMA_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001 +#define DMA_IN_ERR_EOF_CH1_INT_CLR_S 2 + +/* DMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ + +#define DMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_CLR_M (DMA_IN_SUC_EOF_CH1_INT_CLR_V << DMA_IN_SUC_EOF_CH1_INT_CLR_S) +#define DMA_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001 +#define DMA_IN_SUC_EOF_CH1_INT_CLR_S 1 + +/* DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ + +#define DMA_IN_DONE_CH1_INT_CLR (BIT(0)) +#define DMA_IN_DONE_CH1_INT_CLR_M (DMA_IN_DONE_CH1_INT_CLR_V << DMA_IN_DONE_CH1_INT_CLR_S) +#define DMA_IN_DONE_CH1_INT_CLR_V 0x00000001 +#define DMA_IN_DONE_CH1_INT_CLR_S 0 + +/* DMA_INT_RAW_CH2_REG register + * DMA_INT_RAW_CH2_REG. + */ + +#define DMA_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x20) + +/* DMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx + * channel 2 is underflow. + */ + +#define DMA_OUTFIFO_UDF_CH2_INT_RAW (BIT(12)) +#define DMA_OUTFIFO_UDF_CH2_INT_RAW_M (DMA_OUTFIFO_UDF_CH2_INT_RAW_V << DMA_OUTFIFO_UDF_CH2_INT_RAW_S) +#define DMA_OUTFIFO_UDF_CH2_INT_RAW_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH2_INT_RAW_S 12 + +/* DMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Tx + * channel 2 is overflow. + */ + +#define DMA_OUTFIFO_OVF_CH2_INT_RAW (BIT(11)) +#define DMA_OUTFIFO_OVF_CH2_INT_RAW_M (DMA_OUTFIFO_OVF_CH2_INT_RAW_V << DMA_OUTFIFO_OVF_CH2_INT_RAW_S) +#define DMA_OUTFIFO_OVF_CH2_INT_RAW_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH2_INT_RAW_S 11 + +/* DMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx + * channel 2 is underflow. + */ + +#define DMA_INFIFO_UDF_CH2_INT_RAW (BIT(10)) +#define DMA_INFIFO_UDF_CH2_INT_RAW_M (DMA_INFIFO_UDF_CH2_INT_RAW_V << DMA_INFIFO_UDF_CH2_INT_RAW_S) +#define DMA_INFIFO_UDF_CH2_INT_RAW_V 0x00000001 +#define DMA_INFIFO_UDF_CH2_INT_RAW_S 10 + +/* DMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * This raw interrupt bit turns to high level when level 1 fifo of Rx + * channel 2 is overflow. + */ + +#define DMA_INFIFO_OVF_CH2_INT_RAW (BIT(9)) +#define DMA_INFIFO_OVF_CH2_INT_RAW_M (DMA_INFIFO_OVF_CH2_INT_RAW_V << DMA_INFIFO_OVF_CH2_INT_RAW_S) +#define DMA_INFIFO_OVF_CH2_INT_RAW_V 0x00000001 +#define DMA_INFIFO_OVF_CH2_INT_RAW_S 9 + +/* DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The raw interrupt bit turns to high level when data corresponding a + * outlink (includes one link descriptor or few link descriptors) is + * transmitted out for Tx channel 2. + */ + +#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S) +#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 8 + +/* DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The raw interrupt bit turns to high level when Rx buffer pointed by + * inlink is full and receiving data is not completed, but there is no more + * inlink for Rx channel 2. + */ + +#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S) +#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 7 + +/* DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The raw interrupt bit turns to high level when detecting outlink + * descriptor error, including owner error, the second and third word error + * of outlink descriptor for Tx channel 2. + */ + +#define DMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_M (DMA_OUT_DSCR_ERR_CH2_INT_RAW_V << DMA_OUT_DSCR_ERR_CH2_INT_RAW_S) +#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_S 6 + +/* DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The raw interrupt bit turns to high level when detecting inlink + * descriptor error, including owner error, the second and third word error + * of inlink descriptor for Rx channel 2. + */ + +#define DMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_RAW_M (DMA_IN_DSCR_ERR_CH2_INT_RAW_V << DMA_IN_DSCR_ERR_CH2_INT_RAW_S) +#define DMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH2_INT_RAW_S 5 + +/* DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one outlink descriptor has been read from memory for Tx channel 2. + */ + +#define DMA_OUT_EOF_CH2_INT_RAW (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_RAW_M (DMA_OUT_EOF_CH2_INT_RAW_V << DMA_OUT_EOF_CH2_INT_RAW_S) +#define DMA_OUT_EOF_CH2_INT_RAW_V 0x00000001 +#define DMA_OUT_EOF_CH2_INT_RAW_S 4 + +/* DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one outlink descriptor has been transmitted to peripherals for Tx channel + * 2. + */ + +#define DMA_OUT_DONE_CH2_INT_RAW (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_RAW_M (DMA_OUT_DONE_CH2_INT_RAW_V << DMA_OUT_DONE_CH2_INT_RAW_S) +#define DMA_OUT_DONE_CH2_INT_RAW_V 0x00000001 +#define DMA_OUT_DONE_CH2_INT_RAW_S 3 + +/* DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The raw interrupt bit turns to high level when data error is detected + * only in the case that the peripheral is UHCI0 for Rx channel 2. For other + * peripherals, this raw interrupt is reserved. + */ + +#define DMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_RAW_M (DMA_IN_ERR_EOF_CH2_INT_RAW_V << DMA_IN_ERR_EOF_CH2_INT_RAW_S) +#define DMA_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001 +#define DMA_IN_ERR_EOF_CH2_INT_RAW_S 2 + +/* DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one inlink descriptor has been received for Rx channel 2. For UHCI0, the + * raw interrupt bit turns to high level when the last data pointed by one + * inlink descriptor has been received and no data error is detected for Rx + * channel 2. + */ + +#define DMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_RAW_M (DMA_IN_SUC_EOF_CH2_INT_RAW_V << DMA_IN_SUC_EOF_CH2_INT_RAW_S) +#define DMA_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001 +#define DMA_IN_SUC_EOF_CH2_INT_RAW_S 1 + +/* DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The raw interrupt bit turns to high level when the last data pointed by + * one inlink descriptor has been received for Rx channel 2. + */ + +#define DMA_IN_DONE_CH2_INT_RAW (BIT(0)) +#define DMA_IN_DONE_CH2_INT_RAW_M (DMA_IN_DONE_CH2_INT_RAW_V << DMA_IN_DONE_CH2_INT_RAW_S) +#define DMA_IN_DONE_CH2_INT_RAW_V 0x00000001 +#define DMA_IN_DONE_CH2_INT_RAW_S 0 + +/* DMA_INT_ST_CH2_REG register + * DMA_INT_ST_CH2_REG. + */ + +#define DMA_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x24) + +/* DMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [12]; default: 0; + * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_UDF_CH2_INT_ST (BIT(12)) +#define DMA_OUTFIFO_UDF_CH2_INT_ST_M (DMA_OUTFIFO_UDF_CH2_INT_ST_V << DMA_OUTFIFO_UDF_CH2_INT_ST_S) +#define DMA_OUTFIFO_UDF_CH2_INT_ST_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH2_INT_ST_S 12 + +/* DMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [11]; default: 0; + * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_OVF_CH2_INT_ST (BIT(11)) +#define DMA_OUTFIFO_OVF_CH2_INT_ST_M (DMA_OUTFIFO_OVF_CH2_INT_ST_V << DMA_OUTFIFO_OVF_CH2_INT_ST_S) +#define DMA_OUTFIFO_OVF_CH2_INT_ST_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH2_INT_ST_S 11 + +/* DMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [10]; default: 0; + * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_UDF_CH2_INT_ST (BIT(10)) +#define DMA_INFIFO_UDF_CH2_INT_ST_M (DMA_INFIFO_UDF_CH2_INT_ST_V << DMA_INFIFO_UDF_CH2_INT_ST_S) +#define DMA_INFIFO_UDF_CH2_INT_ST_V 0x00000001 +#define DMA_INFIFO_UDF_CH2_INT_ST_S 10 + +/* DMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [9]; default: 0; + * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_OVF_CH2_INT_ST (BIT(9)) +#define DMA_INFIFO_OVF_CH2_INT_ST_M (DMA_INFIFO_OVF_CH2_INT_ST_V << DMA_INFIFO_OVF_CH2_INT_ST_S) +#define DMA_INFIFO_OVF_CH2_INT_ST_V 0x00000001 +#define DMA_INFIFO_OVF_CH2_INT_ST_S 9 + +/* DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [8]; default: 0; + * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_TOTAL_EOF_CH2_INT_ST (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_M (DMA_OUT_TOTAL_EOF_CH2_INT_ST_V << DMA_OUT_TOTAL_EOF_CH2_INT_ST_S) +#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_S 8 + +/* DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [7]; default: 0; + * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_M (DMA_IN_DSCR_EMPTY_CH2_INT_ST_V << DMA_IN_DSCR_EMPTY_CH2_INT_ST_S) +#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_S 7 + +/* DMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_OUT_DSCR_ERR_CH2_INT_ST (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_ST_M (DMA_OUT_DSCR_ERR_CH2_INT_ST_V << DMA_OUT_DSCR_ERR_CH2_INT_ST_S) +#define DMA_OUT_DSCR_ERR_CH2_INT_ST_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH2_INT_ST_S 6 + +/* DMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [5]; default: 0; + * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_ERR_CH2_INT_ST (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_ST_M (DMA_IN_DSCR_ERR_CH2_INT_ST_V << DMA_IN_DSCR_ERR_CH2_INT_ST_S) +#define DMA_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH2_INT_ST_S 5 + +/* DMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [4]; default: 0; + * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_EOF_CH2_INT_ST (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_ST_M (DMA_OUT_EOF_CH2_INT_ST_V << DMA_OUT_EOF_CH2_INT_ST_S) +#define DMA_OUT_EOF_CH2_INT_ST_V 0x00000001 +#define DMA_OUT_EOF_CH2_INT_ST_S 4 + +/* DMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [3]; default: 0; + * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. + */ + +#define DMA_OUT_DONE_CH2_INT_ST (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_ST_M (DMA_OUT_DONE_CH2_INT_ST_V << DMA_OUT_DONE_CH2_INT_ST_S) +#define DMA_OUT_DONE_CH2_INT_ST_V 0x00000001 +#define DMA_OUT_DONE_CH2_INT_ST_S 3 + +/* DMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0; + * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. + */ + +#define DMA_IN_ERR_EOF_CH2_INT_ST (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_ST_M (DMA_IN_ERR_EOF_CH2_INT_ST_V << DMA_IN_ERR_EOF_CH2_INT_ST_S) +#define DMA_IN_ERR_EOF_CH2_INT_ST_V 0x00000001 +#define DMA_IN_ERR_EOF_CH2_INT_ST_S 2 + +/* DMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; + * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. + */ + +#define DMA_IN_SUC_EOF_CH2_INT_ST (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_ST_M (DMA_IN_SUC_EOF_CH2_INT_ST_V << DMA_IN_SUC_EOF_CH2_INT_ST_S) +#define DMA_IN_SUC_EOF_CH2_INT_ST_V 0x00000001 +#define DMA_IN_SUC_EOF_CH2_INT_ST_S 1 + +/* DMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; + * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. + */ + +#define DMA_IN_DONE_CH2_INT_ST (BIT(0)) +#define DMA_IN_DONE_CH2_INT_ST_M (DMA_IN_DONE_CH2_INT_ST_V << DMA_IN_DONE_CH2_INT_ST_S) +#define DMA_IN_DONE_CH2_INT_ST_V 0x00000001 +#define DMA_IN_DONE_CH2_INT_ST_S 0 + +/* DMA_INT_ENA_CH2_REG register + * DMA_INT_ENA_CH2_REG. + */ + +#define DMA_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x28) + +/* DMA_OUTFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_UDF_CH2_INT_ENA (BIT(12)) +#define DMA_OUTFIFO_UDF_CH2_INT_ENA_M (DMA_OUTFIFO_UDF_CH2_INT_ENA_V << DMA_OUTFIFO_UDF_CH2_INT_ENA_S) +#define DMA_OUTFIFO_UDF_CH2_INT_ENA_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH2_INT_ENA_S 12 + +/* DMA_OUTFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_OVF_CH2_INT_ENA (BIT(11)) +#define DMA_OUTFIFO_OVF_CH2_INT_ENA_M (DMA_OUTFIFO_OVF_CH2_INT_ENA_V << DMA_OUTFIFO_OVF_CH2_INT_ENA_S) +#define DMA_OUTFIFO_OVF_CH2_INT_ENA_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH2_INT_ENA_S 11 + +/* DMA_INFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_UDF_CH2_INT_ENA (BIT(10)) +#define DMA_INFIFO_UDF_CH2_INT_ENA_M (DMA_INFIFO_UDF_CH2_INT_ENA_V << DMA_INFIFO_UDF_CH2_INT_ENA_S) +#define DMA_INFIFO_UDF_CH2_INT_ENA_V 0x00000001 +#define DMA_INFIFO_UDF_CH2_INT_ENA_S 10 + +/* DMA_INFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_OVF_CH2_INT_ENA (BIT(9)) +#define DMA_INFIFO_OVF_CH2_INT_ENA_M (DMA_INFIFO_OVF_CH2_INT_ENA_V << DMA_INFIFO_OVF_CH2_INT_ENA_S) +#define DMA_INFIFO_OVF_CH2_INT_ENA_V 0x00000001 +#define DMA_INFIFO_OVF_CH2_INT_ENA_S 9 + +/* DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S) +#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 8 + +/* DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M (DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S) +#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S 7 + +/* DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_OUT_DSCR_ERR_CH2_INT_ENA (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_M (DMA_OUT_DSCR_ERR_CH2_INT_ENA_V << DMA_OUT_DSCR_ERR_CH2_INT_ENA_S) +#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_S 6 + +/* DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_ERR_CH2_INT_ENA (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_ENA_M (DMA_IN_DSCR_ERR_CH2_INT_ENA_V << DMA_IN_DSCR_ERR_CH2_INT_ENA_S) +#define DMA_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH2_INT_ENA_S 5 + +/* DMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_EOF_CH2_INT_ENA (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_ENA_M (DMA_OUT_EOF_CH2_INT_ENA_V << DMA_OUT_EOF_CH2_INT_ENA_S) +#define DMA_OUT_EOF_CH2_INT_ENA_V 0x00000001 +#define DMA_OUT_EOF_CH2_INT_ENA_S 4 + +/* DMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. + */ + +#define DMA_OUT_DONE_CH2_INT_ENA (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_ENA_M (DMA_OUT_DONE_CH2_INT_ENA_V << DMA_OUT_DONE_CH2_INT_ENA_S) +#define DMA_OUT_DONE_CH2_INT_ENA_V 0x00000001 +#define DMA_OUT_DONE_CH2_INT_ENA_S 3 + +/* DMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. + */ + +#define DMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_ENA_M (DMA_IN_ERR_EOF_CH2_INT_ENA_V << DMA_IN_ERR_EOF_CH2_INT_ENA_S) +#define DMA_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001 +#define DMA_IN_ERR_EOF_CH2_INT_ENA_S 2 + +/* DMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. + */ + +#define DMA_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_ENA_M (DMA_IN_SUC_EOF_CH2_INT_ENA_V << DMA_IN_SUC_EOF_CH2_INT_ENA_S) +#define DMA_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001 +#define DMA_IN_SUC_EOF_CH2_INT_ENA_S 1 + +/* DMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the IN_DONE_CH_INT interrupt. + */ + +#define DMA_IN_DONE_CH2_INT_ENA (BIT(0)) +#define DMA_IN_DONE_CH2_INT_ENA_M (DMA_IN_DONE_CH2_INT_ENA_V << DMA_IN_DONE_CH2_INT_ENA_S) +#define DMA_IN_DONE_CH2_INT_ENA_V 0x00000001 +#define DMA_IN_DONE_CH2_INT_ENA_S 0 + +/* DMA_INT_CLR_CH2_REG register + * DMA_INT_CLR_CH2_REG. + */ + +#define DMA_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x2c) + +/* DMA_OUTFIFO_UDF_CH2_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_UDF_CH2_INT_CLR (BIT(12)) +#define DMA_OUTFIFO_UDF_CH2_INT_CLR_M (DMA_OUTFIFO_UDF_CH2_INT_CLR_V << DMA_OUTFIFO_UDF_CH2_INT_CLR_S) +#define DMA_OUTFIFO_UDF_CH2_INT_CLR_V 0x00000001 +#define DMA_OUTFIFO_UDF_CH2_INT_CLR_S 12 + +/* DMA_OUTFIFO_OVF_CH2_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_OUTFIFO_OVF_CH2_INT_CLR (BIT(11)) +#define DMA_OUTFIFO_OVF_CH2_INT_CLR_M (DMA_OUTFIFO_OVF_CH2_INT_CLR_V << DMA_OUTFIFO_OVF_CH2_INT_CLR_S) +#define DMA_OUTFIFO_OVF_CH2_INT_CLR_V 0x00000001 +#define DMA_OUTFIFO_OVF_CH2_INT_CLR_S 11 + +/* DMA_INFIFO_UDF_CH2_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_UDF_CH2_INT_CLR (BIT(10)) +#define DMA_INFIFO_UDF_CH2_INT_CLR_M (DMA_INFIFO_UDF_CH2_INT_CLR_V << DMA_INFIFO_UDF_CH2_INT_CLR_S) +#define DMA_INFIFO_UDF_CH2_INT_CLR_V 0x00000001 +#define DMA_INFIFO_UDF_CH2_INT_CLR_S 10 + +/* DMA_INFIFO_OVF_CH2_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. + */ + +#define DMA_INFIFO_OVF_CH2_INT_CLR (BIT(9)) +#define DMA_INFIFO_OVF_CH2_INT_CLR_M (DMA_INFIFO_OVF_CH2_INT_CLR_V << DMA_INFIFO_OVF_CH2_INT_CLR_S) +#define DMA_INFIFO_OVF_CH2_INT_CLR_V 0x00000001 +#define DMA_INFIFO_OVF_CH2_INT_CLR_S 9 + +/* DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M (DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S) +#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x00000001 +#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S 8 + +/* DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M (DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S) +#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001 +#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S 7 + +/* DMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_OUT_DSCR_ERR_CH2_INT_CLR (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_M (DMA_OUT_DSCR_ERR_CH2_INT_CLR_V << DMA_OUT_DSCR_ERR_CH2_INT_CLR_S) +#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_V 0x00000001 +#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_S 6 + +/* DMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. + */ + +#define DMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_CLR_M (DMA_IN_DSCR_ERR_CH2_INT_CLR_V << DMA_IN_DSCR_ERR_CH2_INT_CLR_S) +#define DMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001 +#define DMA_IN_DSCR_ERR_CH2_INT_CLR_S 5 + +/* DMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear the OUT_EOF_CH_INT interrupt. + */ + +#define DMA_OUT_EOF_CH2_INT_CLR (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_CLR_M (DMA_OUT_EOF_CH2_INT_CLR_V << DMA_OUT_EOF_CH2_INT_CLR_S) +#define DMA_OUT_EOF_CH2_INT_CLR_V 0x00000001 +#define DMA_OUT_EOF_CH2_INT_CLR_S 4 + +/* DMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear the OUT_DONE_CH_INT interrupt. + */ + +#define DMA_OUT_DONE_CH2_INT_CLR (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_CLR_M (DMA_OUT_DONE_CH2_INT_CLR_V << DMA_OUT_DONE_CH2_INT_CLR_S) +#define DMA_OUT_DONE_CH2_INT_CLR_V 0x00000001 +#define DMA_OUT_DONE_CH2_INT_CLR_S 3 + +/* DMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. + */ + +#define DMA_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_CLR_M (DMA_IN_ERR_EOF_CH2_INT_CLR_V << DMA_IN_ERR_EOF_CH2_INT_CLR_S) +#define DMA_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001 +#define DMA_IN_ERR_EOF_CH2_INT_CLR_S 2 + +/* DMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. + */ + +#define DMA_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_CLR_M (DMA_IN_SUC_EOF_CH2_INT_CLR_V << DMA_IN_SUC_EOF_CH2_INT_CLR_S) +#define DMA_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001 +#define DMA_IN_SUC_EOF_CH2_INT_CLR_S 1 + +/* DMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear the IN_DONE_CH_INT interrupt. + */ + +#define DMA_IN_DONE_CH2_INT_CLR (BIT(0)) +#define DMA_IN_DONE_CH2_INT_CLR_M (DMA_IN_DONE_CH2_INT_CLR_V << DMA_IN_DONE_CH2_INT_CLR_S) +#define DMA_IN_DONE_CH2_INT_CLR_V 0x00000001 +#define DMA_IN_DONE_CH2_INT_CLR_S 0 + +/* DMA_AHB_TEST_REG register + * DMA_AHB_TEST_REG. + */ + +#define DMA_AHB_TEST_REG (DR_REG_GDMA_BASE + 0x40) + +/* DMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; + * reserved + */ + +#define DMA_AHB_TESTADDR 0x00000003 +#define DMA_AHB_TESTADDR_M (DMA_AHB_TESTADDR_V << DMA_AHB_TESTADDR_S) +#define DMA_AHB_TESTADDR_V 0x00000003 +#define DMA_AHB_TESTADDR_S 4 + +/* DMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; + * reserved + */ + +#define DMA_AHB_TESTMODE 0x00000007 +#define DMA_AHB_TESTMODE_M (DMA_AHB_TESTMODE_V << DMA_AHB_TESTMODE_S) +#define DMA_AHB_TESTMODE_V 0x00000007 +#define DMA_AHB_TESTMODE_S 0 + +/* DMA_MISC_CONF_REG register + * DMA_MISC_CONF_REG. + */ + +#define DMA_MISC_CONF_REG (DR_REG_GDMA_BASE + 0x44) + +/* DMA_CLK_EN : R/W; bitpos: [3]; default: 0; + * reg_clk_en + */ + +#define DMA_CLK_EN (BIT(3)) +#define DMA_CLK_EN_M (DMA_CLK_EN_V << DMA_CLK_EN_S) +#define DMA_CLK_EN_V 0x00000001 +#define DMA_CLK_EN_S 3 + +/* DMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0; + * Set this bit to disable priority arbitration function. + */ + +#define DMA_ARB_PRI_DIS (BIT(2)) +#define DMA_ARB_PRI_DIS_M (DMA_ARB_PRI_DIS_V << DMA_ARB_PRI_DIS_S) +#define DMA_ARB_PRI_DIS_V 0x00000001 +#define DMA_ARB_PRI_DIS_S 2 + +/* DMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0; + * Set this bit, then clear this bit to reset the internal ahb FSM. + */ + +#define DMA_AHBM_RST_INTER (BIT(0)) +#define DMA_AHBM_RST_INTER_M (DMA_AHBM_RST_INTER_V << DMA_AHBM_RST_INTER_S) +#define DMA_AHBM_RST_INTER_V 0x00000001 +#define DMA_AHBM_RST_INTER_S 0 + +/* DMA_DATE_REG register + * DMA_DATE_REG. + */ + +#define DMA_DATE_REG (DR_REG_GDMA_BASE + 0x48) + +/* DMA_DATE : R/W; bitpos: [31:0]; default: 33587792; + * register version. + */ + +#define DMA_DATE 0xFFFFFFFF +#define DMA_DATE_M (DMA_DATE_V << DMA_DATE_S) +#define DMA_DATE_V 0xFFFFFFFF +#define DMA_DATE_S 0 + +/* DMA_IN_CONF0_CH0_REG register + * DMA_IN_CONF0_CH0_REG. + */ + +#define DMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x70) + +/* DMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to + * memory via DMA. + */ + +#define DMA_MEM_TRANS_EN_CH0 (BIT(4)) +#define DMA_MEM_TRANS_EN_CH0_M (DMA_MEM_TRANS_EN_CH0_V << DMA_MEM_TRANS_EN_CH0_S) +#define DMA_MEM_TRANS_EN_CH0_V 0x00000001 +#define DMA_MEM_TRANS_EN_CH0_S 4 + +/* DMA_IN_DATA_BURST_EN_CH0 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 + * receiving data when accessing internal SRAM. + */ + +#define DMA_IN_DATA_BURST_EN_CH0 (BIT(3)) +#define DMA_IN_DATA_BURST_EN_CH0_M (DMA_IN_DATA_BURST_EN_CH0_V << DMA_IN_DATA_BURST_EN_CH0_S) +#define DMA_IN_DATA_BURST_EN_CH0_V 0x00000001 +#define DMA_IN_DATA_BURST_EN_CH0_S 3 + +/* DMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading + * link descriptor when accessing internal SRAM. + */ + +#define DMA_INDSCR_BURST_EN_CH0 (BIT(2)) +#define DMA_INDSCR_BURST_EN_CH0_M (DMA_INDSCR_BURST_EN_CH0_V << DMA_INDSCR_BURST_EN_CH0_S) +#define DMA_INDSCR_BURST_EN_CH0_V 0x00000001 +#define DMA_INDSCR_BURST_EN_CH0_S 2 + +/* DMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * reserved + */ + +#define DMA_IN_LOOP_TEST_CH0 (BIT(1)) +#define DMA_IN_LOOP_TEST_CH0_M (DMA_IN_LOOP_TEST_CH0_V << DMA_IN_LOOP_TEST_CH0_S) +#define DMA_IN_LOOP_TEST_CH0_V 0x00000001 +#define DMA_IN_LOOP_TEST_CH0_S 1 + +/* DMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. + */ + +#define DMA_IN_RST_CH0 (BIT(0)) +#define DMA_IN_RST_CH0_M (DMA_IN_RST_CH0_V << DMA_IN_RST_CH0_S) +#define DMA_IN_RST_CH0_V 0x00000001 +#define DMA_IN_RST_CH0_S 0 + +/* DMA_IN_CONF1_CH0_REG register + * DMA_IN_CONF1_CH0_REG. + */ + +#define DMA_IN_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x74) + +/* DMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link + * descriptor. + */ + +#define DMA_IN_CHECK_OWNER_CH0 (BIT(12)) +#define DMA_IN_CHECK_OWNER_CH0_M (DMA_IN_CHECK_OWNER_CH0_V << DMA_IN_CHECK_OWNER_CH0_S) +#define DMA_IN_CHECK_OWNER_CH0_V 0x00000001 +#define DMA_IN_CHECK_OWNER_CH0_S 12 + +/* DMA_INFIFO_STATUS_CH0_REG register + * DMA_INFIFO_STATUS_CH0_REG. + */ + +#define DMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x78) + +/* DMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0; + * reserved + */ + +#define DMA_IN_BUF_HUNGRY_CH0 (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH0_M (DMA_IN_BUF_HUNGRY_CH0_V << DMA_IN_BUF_HUNGRY_CH0_S) +#define DMA_IN_BUF_HUNGRY_CH0_V 0x00000001 +#define DMA_IN_BUF_HUNGRY_CH0_S 27 + +/* DMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_CH0_M (DMA_IN_REMAIN_UNDER_4B_CH0_V << DMA_IN_REMAIN_UNDER_4B_CH0_S) +#define DMA_IN_REMAIN_UNDER_4B_CH0_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_4B_CH0_S 26 + +/* DMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_CH0_M (DMA_IN_REMAIN_UNDER_3B_CH0_V << DMA_IN_REMAIN_UNDER_3B_CH0_S) +#define DMA_IN_REMAIN_UNDER_3B_CH0_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_3B_CH0_S 25 + +/* DMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_CH0_M (DMA_IN_REMAIN_UNDER_2B_CH0_V << DMA_IN_REMAIN_UNDER_2B_CH0_S) +#define DMA_IN_REMAIN_UNDER_2B_CH0_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_2B_CH0_S 24 + +/* DMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_CH0_M (DMA_IN_REMAIN_UNDER_1B_CH0_V << DMA_IN_REMAIN_UNDER_1B_CH0_S) +#define DMA_IN_REMAIN_UNDER_1B_CH0_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_1B_CH0_S 23 + +/* DMA_INFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx + * channel 0. + */ + +#define DMA_INFIFO_CNT_CH0 0x0000003F +#define DMA_INFIFO_CNT_CH0_M (DMA_INFIFO_CNT_CH0_V << DMA_INFIFO_CNT_CH0_S) +#define DMA_INFIFO_CNT_CH0_V 0x0000003F +#define DMA_INFIFO_CNT_CH0_S 2 + +/* DMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 0. + */ + +#define DMA_INFIFO_EMPTY_CH0 (BIT(1)) +#define DMA_INFIFO_EMPTY_CH0_M (DMA_INFIFO_EMPTY_CH0_V << DMA_INFIFO_EMPTY_CH0_S) +#define DMA_INFIFO_EMPTY_CH0_V 0x00000001 +#define DMA_INFIFO_EMPTY_CH0_S 1 + +/* DMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 0. + */ + +#define DMA_INFIFO_FULL_CH0 (BIT(0)) +#define DMA_INFIFO_FULL_CH0_M (DMA_INFIFO_FULL_CH0_V << DMA_INFIFO_FULL_CH0_S) +#define DMA_INFIFO_FULL_CH0_V 0x00000001 +#define DMA_INFIFO_FULL_CH0_S 0 + +/* DMA_IN_POP_CH0_REG register + * DMA_IN_POP_CH0_REG. + */ + +#define DMA_IN_POP_CH0_REG (DR_REG_GDMA_BASE + 0x7c) + +/* DMA_INFIFO_POP_CH0 : R/W/SC; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ + +#define DMA_INFIFO_POP_CH0 (BIT(12)) +#define DMA_INFIFO_POP_CH0_M (DMA_INFIFO_POP_CH0_V << DMA_INFIFO_POP_CH0_S) +#define DMA_INFIFO_POP_CH0_V 0x00000001 +#define DMA_INFIFO_POP_CH0_S 12 + +/* DMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ + +#define DMA_INFIFO_RDATA_CH0 0x00000FFF +#define DMA_INFIFO_RDATA_CH0_M (DMA_INFIFO_RDATA_CH0_V << DMA_INFIFO_RDATA_CH0_S) +#define DMA_INFIFO_RDATA_CH0_V 0x00000FFF +#define DMA_INFIFO_RDATA_CH0_S 0 + +/* DMA_IN_LINK_CH0_REG register + * DMA_IN_LINK_CH0_REG. + */ + +#define DMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x80) + +/* DMA_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink + * descriptor's FSM is working. + */ + +#define DMA_INLINK_PARK_CH0 (BIT(24)) +#define DMA_INLINK_PARK_CH0_M (DMA_INLINK_PARK_CH0_V << DMA_INLINK_PARK_CH0_S) +#define DMA_INLINK_PARK_CH0_V 0x00000001 +#define DMA_INLINK_PARK_CH0_S 24 + +/* DMA_INLINK_RESTART_CH0 : R/W/SC; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ + +#define DMA_INLINK_RESTART_CH0 (BIT(23)) +#define DMA_INLINK_RESTART_CH0_M (DMA_INLINK_RESTART_CH0_V << DMA_INLINK_RESTART_CH0_S) +#define DMA_INLINK_RESTART_CH0_V 0x00000001 +#define DMA_INLINK_RESTART_CH0_S 23 + +/* DMA_INLINK_START_CH0 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ + +#define DMA_INLINK_START_CH0 (BIT(22)) +#define DMA_INLINK_START_CH0_M (DMA_INLINK_START_CH0_V << DMA_INLINK_START_CH0_S) +#define DMA_INLINK_START_CH0_V 0x00000001 +#define DMA_INLINK_START_CH0_S 22 + +/* DMA_INLINK_STOP_CH0 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ + +#define DMA_INLINK_STOP_CH0 (BIT(21)) +#define DMA_INLINK_STOP_CH0_M (DMA_INLINK_STOP_CH0_V << DMA_INLINK_STOP_CH0_S) +#define DMA_INLINK_STOP_CH0_V 0x00000001 +#define DMA_INLINK_STOP_CH0_S 21 + +/* DMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address, when there + * are some errors in current receiving data. + */ + +#define DMA_INLINK_AUTO_RET_CH0 (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH0_M (DMA_INLINK_AUTO_RET_CH0_V << DMA_INLINK_AUTO_RET_CH0_S) +#define DMA_INLINK_AUTO_RET_CH0_V 0x00000001 +#define DMA_INLINK_AUTO_RET_CH0_S 20 + +/* DMA_INLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink + * descriptor's address. + */ + +#define DMA_INLINK_ADDR_CH0 0x000FFFFF +#define DMA_INLINK_ADDR_CH0_M (DMA_INLINK_ADDR_CH0_V << DMA_INLINK_ADDR_CH0_S) +#define DMA_INLINK_ADDR_CH0_V 0x000FFFFF +#define DMA_INLINK_ADDR_CH0_S 0 + +/* DMA_IN_STATE_CH0_REG register + * DMA_IN_STATE_CH0_REG. + */ + +#define DMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x84) + +/* DMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ + +#define DMA_IN_STATE_CH0 0x00000007 +#define DMA_IN_STATE_CH0_M (DMA_IN_STATE_CH0_V << DMA_IN_STATE_CH0_S) +#define DMA_IN_STATE_CH0_V 0x00000007 +#define DMA_IN_STATE_CH0_S 20 + +/* DMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ + +#define DMA_IN_DSCR_STATE_CH0 0x00000003 +#define DMA_IN_DSCR_STATE_CH0_M (DMA_IN_DSCR_STATE_CH0_V << DMA_IN_DSCR_STATE_CH0_S) +#define DMA_IN_DSCR_STATE_CH0_V 0x00000003 +#define DMA_IN_DSCR_STATE_CH0_S 18 + +/* DMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ + +#define DMA_INLINK_DSCR_ADDR_CH0 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH0_M (DMA_INLINK_DSCR_ADDR_CH0_V << DMA_INLINK_DSCR_ADDR_CH0_S) +#define DMA_INLINK_DSCR_ADDR_CH0_V 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH0_S 0 + +/* DMA_IN_SUC_EOF_DES_ADDR_CH0_REG register + * DMA_IN_SUC_EOF_DES_ADDR_CH0_REG. + */ + +#define DMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x88) + +/* DMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF + * bit in this descriptor is 1. + */ + +#define DMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH0_M (DMA_IN_SUC_EOF_DES_ADDR_CH0_V << DMA_IN_SUC_EOF_DES_ADDR_CH0_S) +#define DMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 + +/* DMA_IN_ERR_EOF_DES_ADDR_CH0_REG register + * DMA_IN_ERR_EOF_DES_ADDR_CH0_REG. + */ + +#define DMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x8c) + +/* DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are + * some errors in current receiving data. Only used when peripheral is UHCI0. + */ + +#define DMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH0_M (DMA_IN_ERR_EOF_DES_ADDR_CH0_V << DMA_IN_ERR_EOF_DES_ADDR_CH0_S) +#define DMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 + +/* DMA_IN_DSCR_CH0_REG register + * DMA_IN_DSCR_CH0_REG. + */ + +#define DMA_IN_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x90) + +/* DMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ + +#define DMA_INLINK_DSCR_CH0 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH0_M (DMA_INLINK_DSCR_CH0_V << DMA_INLINK_DSCR_CH0_S) +#define DMA_INLINK_DSCR_CH0_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH0_S 0 + +/* DMA_IN_DSCR_BF0_CH0_REG register + * DMA_IN_DSCR_BF0_CH0_REG. + */ + +#define DMA_IN_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x94) + +/* DMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ + +#define DMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH0_M (DMA_INLINK_DSCR_BF0_CH0_V << DMA_INLINK_DSCR_BF0_CH0_S) +#define DMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH0_S 0 + +/* DMA_IN_DSCR_BF1_CH0_REG register + * DMA_IN_DSCR_BF1_CH0_REG. + */ + +#define DMA_IN_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x98) + +/* DMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + +#define DMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH0_M (DMA_INLINK_DSCR_BF1_CH0_V << DMA_INLINK_DSCR_BF1_CH0_S) +#define DMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH0_S 0 + +/* DMA_IN_PRI_CH0_REG register + * DMA_IN_PRI_CH0_REG. + */ + +#define DMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x9c) + +/* DMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 0. The larger of the value, the higher of the + * priority. + */ + +#define DMA_RX_PRI_CH0 0x0000000F +#define DMA_RX_PRI_CH0_M (DMA_RX_PRI_CH0_V << DMA_RX_PRI_CH0_S) +#define DMA_RX_PRI_CH0_V 0x0000000F +#define DMA_RX_PRI_CH0_S 0 + +/* DMA_IN_PERI_SEL_CH0_REG register + * DMA_IN_PERI_SEL_CH0_REG. + */ + +#define DMA_IN_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0xa0) + +/* DMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: + * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: + * ADC_DAC. + */ + +#define DMA_PERI_IN_SEL_CH0 0x0000003F +#define DMA_PERI_IN_SEL_CH0_M (DMA_PERI_IN_SEL_CH0_V << DMA_PERI_IN_SEL_CH0_S) +#define DMA_PERI_IN_SEL_CH0_V 0x0000003F +#define DMA_PERI_IN_SEL_CH0_S 0 + +/* DMA_OUT_CONF0_CH0_REG register + * DMA_OUT_CONF0_CH0_REG. + */ + +#define DMA_OUT_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0xd0) + +/* DMA_OUT_DATA_BURST_EN_CH0 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 + * transmitting data when accessing internal SRAM. + */ + +#define DMA_OUT_DATA_BURST_EN_CH0 (BIT(5)) +#define DMA_OUT_DATA_BURST_EN_CH0_M (DMA_OUT_DATA_BURST_EN_CH0_V << DMA_OUT_DATA_BURST_EN_CH0_S) +#define DMA_OUT_DATA_BURST_EN_CH0_V 0x00000001 +#define DMA_OUT_DATA_BURST_EN_CH0_S 5 + +/* DMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading + * link descriptor when accessing internal SRAM. + */ + +#define DMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) +#define DMA_OUTDSCR_BURST_EN_CH0_M (DMA_OUTDSCR_BURST_EN_CH0_V << DMA_OUTDSCR_BURST_EN_CH0_S) +#define DMA_OUTDSCR_BURST_EN_CH0_V 0x00000001 +#define DMA_OUTDSCR_BURST_EN_CH0_S 4 + +/* DMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx + * channel 0 is generated when data need to transmit has been popped from + * FIFO in DMA + */ + +#define DMA_OUT_EOF_MODE_CH0 (BIT(3)) +#define DMA_OUT_EOF_MODE_CH0_M (DMA_OUT_EOF_MODE_CH0_V << DMA_OUT_EOF_MODE_CH0_S) +#define DMA_OUT_EOF_MODE_CH0_V 0x00000001 +#define DMA_OUT_EOF_MODE_CH0_S 3 + +/* DMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in + * tx buffer has been transmitted. + */ + +#define DMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) +#define DMA_OUT_AUTO_WRBACK_CH0_M (DMA_OUT_AUTO_WRBACK_CH0_V << DMA_OUT_AUTO_WRBACK_CH0_S) +#define DMA_OUT_AUTO_WRBACK_CH0_V 0x00000001 +#define DMA_OUT_AUTO_WRBACK_CH0_S 2 + +/* DMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; + * reserved + */ + +#define DMA_OUT_LOOP_TEST_CH0 (BIT(1)) +#define DMA_OUT_LOOP_TEST_CH0_M (DMA_OUT_LOOP_TEST_CH0_V << DMA_OUT_LOOP_TEST_CH0_S) +#define DMA_OUT_LOOP_TEST_CH0_V 0x00000001 +#define DMA_OUT_LOOP_TEST_CH0_S 1 + +/* DMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. + */ + +#define DMA_OUT_RST_CH0 (BIT(0)) +#define DMA_OUT_RST_CH0_M (DMA_OUT_RST_CH0_V << DMA_OUT_RST_CH0_S) +#define DMA_OUT_RST_CH0_V 0x00000001 +#define DMA_OUT_RST_CH0_S 0 + +/* DMA_OUT_CONF1_CH0_REG register + * DMA_OUT_CONF1_CH0_REG. + */ + +#define DMA_OUT_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0xd4) + +/* DMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link + * descriptor. + */ + +#define DMA_OUT_CHECK_OWNER_CH0 (BIT(12)) +#define DMA_OUT_CHECK_OWNER_CH0_M (DMA_OUT_CHECK_OWNER_CH0_V << DMA_OUT_CHECK_OWNER_CH0_S) +#define DMA_OUT_CHECK_OWNER_CH0_V 0x00000001 +#define DMA_OUT_CHECK_OWNER_CH0_S 12 + +/* DMA_OUTFIFO_STATUS_CH0_REG register + * DMA_OUTFIFO_STATUS_CH0_REG. + */ + +#define DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0xd8) + +/* DMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_CH0_M (DMA_OUT_REMAIN_UNDER_4B_CH0_V << DMA_OUT_REMAIN_UNDER_4B_CH0_S) +#define DMA_OUT_REMAIN_UNDER_4B_CH0_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_4B_CH0_S 26 + +/* DMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_CH0_M (DMA_OUT_REMAIN_UNDER_3B_CH0_V << DMA_OUT_REMAIN_UNDER_3B_CH0_S) +#define DMA_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_3B_CH0_S 25 + +/* DMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_CH0_M (DMA_OUT_REMAIN_UNDER_2B_CH0_V << DMA_OUT_REMAIN_UNDER_2B_CH0_S) +#define DMA_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_2B_CH0_S 24 + +/* DMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_CH0_M (DMA_OUT_REMAIN_UNDER_1B_CH0_V << DMA_OUT_REMAIN_UNDER_1B_CH0_S) +#define DMA_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_1B_CH0_S 23 + +/* DMA_OUTFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx + * channel 0. + */ + +#define DMA_OUTFIFO_CNT_CH0 0x0000003F +#define DMA_OUTFIFO_CNT_CH0_M (DMA_OUTFIFO_CNT_CH0_V << DMA_OUTFIFO_CNT_CH0_S) +#define DMA_OUTFIFO_CNT_CH0_V 0x0000003F +#define DMA_OUTFIFO_CNT_CH0_S 2 + +/* DMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 0. + */ + +#define DMA_OUTFIFO_EMPTY_CH0 (BIT(1)) +#define DMA_OUTFIFO_EMPTY_CH0_M (DMA_OUTFIFO_EMPTY_CH0_V << DMA_OUTFIFO_EMPTY_CH0_S) +#define DMA_OUTFIFO_EMPTY_CH0_V 0x00000001 +#define DMA_OUTFIFO_EMPTY_CH0_S 1 + +/* DMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 0. + */ + +#define DMA_OUTFIFO_FULL_CH0 (BIT(0)) +#define DMA_OUTFIFO_FULL_CH0_M (DMA_OUTFIFO_FULL_CH0_V << DMA_OUTFIFO_FULL_CH0_S) +#define DMA_OUTFIFO_FULL_CH0_V 0x00000001 +#define DMA_OUTFIFO_FULL_CH0_S 0 + +/* DMA_OUT_PUSH_CH0_REG register + * DMA_OUT_PUSH_CH0_REG. + */ + +#define DMA_OUT_PUSH_CH0_REG (DR_REG_GDMA_BASE + 0xdc) + +/* DMA_OUTFIFO_PUSH_CH0 : R/W/SC; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ + +#define DMA_OUTFIFO_PUSH_CH0 (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH0_M (DMA_OUTFIFO_PUSH_CH0_V << DMA_OUTFIFO_PUSH_CH0_S) +#define DMA_OUTFIFO_PUSH_CH0_V 0x00000001 +#define DMA_OUTFIFO_PUSH_CH0_S 9 + +/* DMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ + +#define DMA_OUTFIFO_WDATA_CH0 0x000001FF +#define DMA_OUTFIFO_WDATA_CH0_M (DMA_OUTFIFO_WDATA_CH0_V << DMA_OUTFIFO_WDATA_CH0_S) +#define DMA_OUTFIFO_WDATA_CH0_V 0x000001FF +#define DMA_OUTFIFO_WDATA_CH0_S 0 + +/* DMA_OUT_LINK_CH0_REG register + * DMA_OUT_LINK_CH0_REG. + */ + +#define DMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0xe0) + +/* DMA_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink + * descriptor's FSM is working. + */ + +#define DMA_OUTLINK_PARK_CH0 (BIT(23)) +#define DMA_OUTLINK_PARK_CH0_M (DMA_OUTLINK_PARK_CH0_V << DMA_OUTLINK_PARK_CH0_S) +#define DMA_OUTLINK_PARK_CH0_V 0x00000001 +#define DMA_OUTLINK_PARK_CH0_S 23 + +/* DMA_OUTLINK_RESTART_CH0 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ + +#define DMA_OUTLINK_RESTART_CH0 (BIT(22)) +#define DMA_OUTLINK_RESTART_CH0_M (DMA_OUTLINK_RESTART_CH0_V << DMA_OUTLINK_RESTART_CH0_S) +#define DMA_OUTLINK_RESTART_CH0_V 0x00000001 +#define DMA_OUTLINK_RESTART_CH0_S 22 + +/* DMA_OUTLINK_START_CH0 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ + +#define DMA_OUTLINK_START_CH0 (BIT(21)) +#define DMA_OUTLINK_START_CH0_M (DMA_OUTLINK_START_CH0_V << DMA_OUTLINK_START_CH0_S) +#define DMA_OUTLINK_START_CH0_V 0x00000001 +#define DMA_OUTLINK_START_CH0_S 21 + +/* DMA_OUTLINK_STOP_CH0 : R/W/SC; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ + +#define DMA_OUTLINK_STOP_CH0 (BIT(20)) +#define DMA_OUTLINK_STOP_CH0_M (DMA_OUTLINK_STOP_CH0_V << DMA_OUTLINK_STOP_CH0_S) +#define DMA_OUTLINK_STOP_CH0_V 0x00000001 +#define DMA_OUTLINK_STOP_CH0_S 20 + +/* DMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ + +#define DMA_OUTLINK_ADDR_CH0 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH0_M (DMA_OUTLINK_ADDR_CH0_V << DMA_OUTLINK_ADDR_CH0_S) +#define DMA_OUTLINK_ADDR_CH0_V 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH0_S 0 + +/* DMA_OUT_STATE_CH0_REG register + * DMA_OUT_STATE_CH0_REG. + */ + +#define DMA_OUT_STATE_CH0_REG (DR_REG_GDMA_BASE + 0xe4) + +/* DMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; + * reserved + */ + +#define DMA_OUT_STATE_CH0 0x00000007 +#define DMA_OUT_STATE_CH0_M (DMA_OUT_STATE_CH0_V << DMA_OUT_STATE_CH0_S) +#define DMA_OUT_STATE_CH0_V 0x00000007 +#define DMA_OUT_STATE_CH0_S 20 + +/* DMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; + * reserved + */ + +#define DMA_OUT_DSCR_STATE_CH0 0x00000003 +#define DMA_OUT_DSCR_STATE_CH0_M (DMA_OUT_DSCR_STATE_CH0_V << DMA_OUT_DSCR_STATE_CH0_S) +#define DMA_OUT_DSCR_STATE_CH0_V 0x00000003 +#define DMA_OUT_DSCR_STATE_CH0_S 18 + +/* DMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ + +#define DMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH0_M (DMA_OUTLINK_DSCR_ADDR_CH0_V << DMA_OUTLINK_DSCR_ADDR_CH0_S) +#define DMA_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH0_S 0 + +/* DMA_OUT_EOF_DES_ADDR_CH0_REG register + * DMA_OUT_EOF_DES_ADDR_CH0_REG. + */ + +#define DMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xe8) + +/* DMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF + * bit in this descriptor is 1. + */ + +#define DMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH0_M (DMA_OUT_EOF_DES_ADDR_CH0_V << DMA_OUT_EOF_DES_ADDR_CH0_S) +#define DMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH0_S 0 + +/* DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register + * DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG. + */ + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xec) + +/* DMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the + * last outlink descriptor. + */ + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_M (DMA_OUT_EOF_BFR_DES_ADDR_CH0_V << DMA_OUT_EOF_BFR_DES_ADDR_CH0_S) +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 + +/* DMA_OUT_DSCR_CH0_REG register + * DMA_OUT_DSCR_CH0_REG. + */ + +#define DMA_OUT_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0xf0) + +/* DMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ + +#define DMA_OUTLINK_DSCR_CH0 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH0_M (DMA_OUTLINK_DSCR_CH0_V << DMA_OUTLINK_DSCR_CH0_S) +#define DMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH0_S 0 + +/* DMA_OUT_DSCR_BF0_CH0_REG register + * DMA_OUT_DSCR_BF0_CH0_REG. + */ + +#define DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0xf4) + +/* DMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ + +#define DMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH0_M (DMA_OUTLINK_DSCR_BF0_CH0_V << DMA_OUTLINK_DSCR_BF0_CH0_S) +#define DMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH0_S 0 + +/* DMA_OUT_DSCR_BF1_CH0_REG register + * DMA_OUT_DSCR_BF1_CH0_REG. + */ + +#define DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0xf8) + +/* DMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + +#define DMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH0_M (DMA_OUTLINK_DSCR_BF1_CH0_V << DMA_OUTLINK_DSCR_BF1_CH0_S) +#define DMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH0_S 0 + +/* DMA_OUT_PRI_CH0_REG register + * DMA_OUT_PRI_CH0_REG. + */ + +#define DMA_OUT_PRI_CH0_REG (DR_REG_GDMA_BASE + 0xfc) + +/* DMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 0. The larger of the value, the higher of the + * priority. + */ + +#define DMA_TX_PRI_CH0 0x0000000F +#define DMA_TX_PRI_CH0_M (DMA_TX_PRI_CH0_V << DMA_TX_PRI_CH0_S) +#define DMA_TX_PRI_CH0_V 0x0000000F +#define DMA_TX_PRI_CH0_S 0 + +/* DMA_OUT_PERI_SEL_CH0_REG register + * DMA_OUT_PERI_SEL_CH0_REG. + */ + +#define DMA_OUT_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x100) + +/* DMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: + * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: + * ADC_DAC. + */ + +#define DMA_PERI_OUT_SEL_CH0 0x0000003F +#define DMA_PERI_OUT_SEL_CH0_M (DMA_PERI_OUT_SEL_CH0_V << DMA_PERI_OUT_SEL_CH0_S) +#define DMA_PERI_OUT_SEL_CH0_V 0x0000003F +#define DMA_PERI_OUT_SEL_CH0_S 0 + +/* DMA_IN_CONF0_CH1_REG register + * DMA_IN_CONF0_CH1_REG. + */ + +#define DMA_IN_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x130) + +/* DMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to + * memory via DMA. + */ + +#define DMA_MEM_TRANS_EN_CH1 (BIT(4)) +#define DMA_MEM_TRANS_EN_CH1_M (DMA_MEM_TRANS_EN_CH1_V << DMA_MEM_TRANS_EN_CH1_S) +#define DMA_MEM_TRANS_EN_CH1_V 0x00000001 +#define DMA_MEM_TRANS_EN_CH1_S 4 + +/* DMA_IN_DATA_BURST_EN_CH1 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 + * receiving data when accessing internal SRAM. + */ + +#define DMA_IN_DATA_BURST_EN_CH1 (BIT(3)) +#define DMA_IN_DATA_BURST_EN_CH1_M (DMA_IN_DATA_BURST_EN_CH1_V << DMA_IN_DATA_BURST_EN_CH1_S) +#define DMA_IN_DATA_BURST_EN_CH1_V 0x00000001 +#define DMA_IN_DATA_BURST_EN_CH1_S 3 + +/* DMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading + * link descriptor when accessing internal SRAM. + */ + +#define DMA_INDSCR_BURST_EN_CH1 (BIT(2)) +#define DMA_INDSCR_BURST_EN_CH1_M (DMA_INDSCR_BURST_EN_CH1_V << DMA_INDSCR_BURST_EN_CH1_S) +#define DMA_INDSCR_BURST_EN_CH1_V 0x00000001 +#define DMA_INDSCR_BURST_EN_CH1_S 2 + +/* DMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * reserved + */ + +#define DMA_IN_LOOP_TEST_CH1 (BIT(1)) +#define DMA_IN_LOOP_TEST_CH1_M (DMA_IN_LOOP_TEST_CH1_V << DMA_IN_LOOP_TEST_CH1_S) +#define DMA_IN_LOOP_TEST_CH1_V 0x00000001 +#define DMA_IN_LOOP_TEST_CH1_S 1 + +/* DMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer. + */ + +#define DMA_IN_RST_CH1 (BIT(0)) +#define DMA_IN_RST_CH1_M (DMA_IN_RST_CH1_V << DMA_IN_RST_CH1_S) +#define DMA_IN_RST_CH1_V 0x00000001 +#define DMA_IN_RST_CH1_S 0 + +/* DMA_IN_CONF1_CH1_REG register + * DMA_IN_CONF1_CH1_REG. + */ + +#define DMA_IN_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x134) + +/* DMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link + * descriptor. + */ + +#define DMA_IN_CHECK_OWNER_CH1 (BIT(12)) +#define DMA_IN_CHECK_OWNER_CH1_M (DMA_IN_CHECK_OWNER_CH1_V << DMA_IN_CHECK_OWNER_CH1_S) +#define DMA_IN_CHECK_OWNER_CH1_V 0x00000001 +#define DMA_IN_CHECK_OWNER_CH1_S 12 + +/* DMA_INFIFO_STATUS_CH1_REG register + * DMA_INFIFO_STATUS_CH1_REG. + */ + +#define DMA_INFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x138) + +/* DMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0; + * reserved + */ + +#define DMA_IN_BUF_HUNGRY_CH1 (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH1_M (DMA_IN_BUF_HUNGRY_CH1_V << DMA_IN_BUF_HUNGRY_CH1_S) +#define DMA_IN_BUF_HUNGRY_CH1_V 0x00000001 +#define DMA_IN_BUF_HUNGRY_CH1_S 27 + +/* DMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_CH1_M (DMA_IN_REMAIN_UNDER_4B_CH1_V << DMA_IN_REMAIN_UNDER_4B_CH1_S) +#define DMA_IN_REMAIN_UNDER_4B_CH1_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_4B_CH1_S 26 + +/* DMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_CH1_M (DMA_IN_REMAIN_UNDER_3B_CH1_V << DMA_IN_REMAIN_UNDER_3B_CH1_S) +#define DMA_IN_REMAIN_UNDER_3B_CH1_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_3B_CH1_S 25 + +/* DMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_CH1_M (DMA_IN_REMAIN_UNDER_2B_CH1_V << DMA_IN_REMAIN_UNDER_2B_CH1_S) +#define DMA_IN_REMAIN_UNDER_2B_CH1_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_2B_CH1_S 24 + +/* DMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_CH1_M (DMA_IN_REMAIN_UNDER_1B_CH1_V << DMA_IN_REMAIN_UNDER_1B_CH1_S) +#define DMA_IN_REMAIN_UNDER_1B_CH1_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_1B_CH1_S 23 + +/* DMA_INFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx + * channel 1. + */ + +#define DMA_INFIFO_CNT_CH1 0x0000003F +#define DMA_INFIFO_CNT_CH1_M (DMA_INFIFO_CNT_CH1_V << DMA_INFIFO_CNT_CH1_S) +#define DMA_INFIFO_CNT_CH1_V 0x0000003F +#define DMA_INFIFO_CNT_CH1_S 2 + +/* DMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 1. + */ + +#define DMA_INFIFO_EMPTY_CH1 (BIT(1)) +#define DMA_INFIFO_EMPTY_CH1_M (DMA_INFIFO_EMPTY_CH1_V << DMA_INFIFO_EMPTY_CH1_S) +#define DMA_INFIFO_EMPTY_CH1_V 0x00000001 +#define DMA_INFIFO_EMPTY_CH1_S 1 + +/* DMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 1. + */ + +#define DMA_INFIFO_FULL_CH1 (BIT(0)) +#define DMA_INFIFO_FULL_CH1_M (DMA_INFIFO_FULL_CH1_V << DMA_INFIFO_FULL_CH1_S) +#define DMA_INFIFO_FULL_CH1_V 0x00000001 +#define DMA_INFIFO_FULL_CH1_S 0 + +/* DMA_IN_POP_CH1_REG register + * DMA_IN_POP_CH1_REG. + */ + +#define DMA_IN_POP_CH1_REG (DR_REG_GDMA_BASE + 0x13c) + +/* DMA_INFIFO_POP_CH1 : R/W/SC; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ + +#define DMA_INFIFO_POP_CH1 (BIT(12)) +#define DMA_INFIFO_POP_CH1_M (DMA_INFIFO_POP_CH1_V << DMA_INFIFO_POP_CH1_S) +#define DMA_INFIFO_POP_CH1_V 0x00000001 +#define DMA_INFIFO_POP_CH1_S 12 + +/* DMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ + +#define DMA_INFIFO_RDATA_CH1 0x00000FFF +#define DMA_INFIFO_RDATA_CH1_M (DMA_INFIFO_RDATA_CH1_V << DMA_INFIFO_RDATA_CH1_S) +#define DMA_INFIFO_RDATA_CH1_V 0x00000FFF +#define DMA_INFIFO_RDATA_CH1_S 0 + +/* DMA_IN_LINK_CH1_REG register + * DMA_IN_LINK_CH1_REG. + */ + +#define DMA_IN_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x140) + +/* DMA_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink + * descriptor's FSM is working. + */ + +#define DMA_INLINK_PARK_CH1 (BIT(24)) +#define DMA_INLINK_PARK_CH1_M (DMA_INLINK_PARK_CH1_V << DMA_INLINK_PARK_CH1_S) +#define DMA_INLINK_PARK_CH1_V 0x00000001 +#define DMA_INLINK_PARK_CH1_S 24 + +/* DMA_INLINK_RESTART_CH1 : R/W/SC; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ + +#define DMA_INLINK_RESTART_CH1 (BIT(23)) +#define DMA_INLINK_RESTART_CH1_M (DMA_INLINK_RESTART_CH1_V << DMA_INLINK_RESTART_CH1_S) +#define DMA_INLINK_RESTART_CH1_V 0x00000001 +#define DMA_INLINK_RESTART_CH1_S 23 + +/* DMA_INLINK_START_CH1 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ + +#define DMA_INLINK_START_CH1 (BIT(22)) +#define DMA_INLINK_START_CH1_M (DMA_INLINK_START_CH1_V << DMA_INLINK_START_CH1_S) +#define DMA_INLINK_START_CH1_V 0x00000001 +#define DMA_INLINK_START_CH1_S 22 + +/* DMA_INLINK_STOP_CH1 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ + +#define DMA_INLINK_STOP_CH1 (BIT(21)) +#define DMA_INLINK_STOP_CH1_M (DMA_INLINK_STOP_CH1_V << DMA_INLINK_STOP_CH1_S) +#define DMA_INLINK_STOP_CH1_V 0x00000001 +#define DMA_INLINK_STOP_CH1_S 21 + +/* DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address, when there + * are some errors in current receiving data. + */ + +#define DMA_INLINK_AUTO_RET_CH1 (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH1_M (DMA_INLINK_AUTO_RET_CH1_V << DMA_INLINK_AUTO_RET_CH1_S) +#define DMA_INLINK_AUTO_RET_CH1_V 0x00000001 +#define DMA_INLINK_AUTO_RET_CH1_S 20 + +/* DMA_INLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink + * descriptor's address. + */ + +#define DMA_INLINK_ADDR_CH1 0x000FFFFF +#define DMA_INLINK_ADDR_CH1_M (DMA_INLINK_ADDR_CH1_V << DMA_INLINK_ADDR_CH1_S) +#define DMA_INLINK_ADDR_CH1_V 0x000FFFFF +#define DMA_INLINK_ADDR_CH1_S 0 + +/* DMA_IN_STATE_CH1_REG register + * DMA_IN_STATE_CH1_REG. + */ + +#define DMA_IN_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x144) + +/* DMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ + +#define DMA_IN_STATE_CH1 0x00000007 +#define DMA_IN_STATE_CH1_M (DMA_IN_STATE_CH1_V << DMA_IN_STATE_CH1_S) +#define DMA_IN_STATE_CH1_V 0x00000007 +#define DMA_IN_STATE_CH1_S 20 + +/* DMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ + +#define DMA_IN_DSCR_STATE_CH1 0x00000003 +#define DMA_IN_DSCR_STATE_CH1_M (DMA_IN_DSCR_STATE_CH1_V << DMA_IN_DSCR_STATE_CH1_S) +#define DMA_IN_DSCR_STATE_CH1_V 0x00000003 +#define DMA_IN_DSCR_STATE_CH1_S 18 + +/* DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ + +#define DMA_INLINK_DSCR_ADDR_CH1 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH1_M (DMA_INLINK_DSCR_ADDR_CH1_V << DMA_INLINK_DSCR_ADDR_CH1_S) +#define DMA_INLINK_DSCR_ADDR_CH1_V 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH1_S 0 + +/* DMA_IN_SUC_EOF_DES_ADDR_CH1_REG register + * DMA_IN_SUC_EOF_DES_ADDR_CH1_REG. + */ + +#define DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x148) + +/* DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF + * bit in this descriptor is 1. + */ + +#define DMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH1_M (DMA_IN_SUC_EOF_DES_ADDR_CH1_V << DMA_IN_SUC_EOF_DES_ADDR_CH1_S) +#define DMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 + +/* DMA_IN_ERR_EOF_DES_ADDR_CH1_REG register + * DMA_IN_ERR_EOF_DES_ADDR_CH1_REG. + */ + +#define DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x14c) + +/* DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are + * some errors in current receiving data. Only used when peripheral is UHCI0. + */ + +#define DMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH1_M (DMA_IN_ERR_EOF_DES_ADDR_CH1_V << DMA_IN_ERR_EOF_DES_ADDR_CH1_S) +#define DMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 + +/* DMA_IN_DSCR_CH1_REG register + * DMA_IN_DSCR_CH1_REG. + */ + +#define DMA_IN_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x150) + +/* DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ + +#define DMA_INLINK_DSCR_CH1 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH1_M (DMA_INLINK_DSCR_CH1_V << DMA_INLINK_DSCR_CH1_S) +#define DMA_INLINK_DSCR_CH1_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH1_S 0 + +/* DMA_IN_DSCR_BF0_CH1_REG register + * DMA_IN_DSCR_BF0_CH1_REG. + */ + +#define DMA_IN_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x154) + +/* DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ + +#define DMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH1_M (DMA_INLINK_DSCR_BF0_CH1_V << DMA_INLINK_DSCR_BF0_CH1_S) +#define DMA_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH1_S 0 + +/* DMA_IN_DSCR_BF1_CH1_REG register + * DMA_IN_DSCR_BF1_CH1_REG. + */ + +#define DMA_IN_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x158) + +/* DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + +#define DMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH1_M (DMA_INLINK_DSCR_BF1_CH1_V << DMA_INLINK_DSCR_BF1_CH1_S) +#define DMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH1_S 0 + +/* DMA_IN_PRI_CH1_REG register + * DMA_IN_PRI_CH1_REG. + */ + +#define DMA_IN_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x15c) + +/* DMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 1. The larger of the value, the higher of the + * priority. + */ + +#define DMA_RX_PRI_CH1 0x0000000F +#define DMA_RX_PRI_CH1_M (DMA_RX_PRI_CH1_V << DMA_RX_PRI_CH1_S) +#define DMA_RX_PRI_CH1_V 0x0000000F +#define DMA_RX_PRI_CH1_S 0 + +/* DMA_IN_PERI_SEL_CH1_REG register + * DMA_IN_PERI_SEL_CH1_REG. + */ + +#define DMA_IN_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x160) + +/* DMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: + * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: + * ADC_DAC. + */ + +#define DMA_PERI_IN_SEL_CH1 0x0000003F +#define DMA_PERI_IN_SEL_CH1_M (DMA_PERI_IN_SEL_CH1_V << DMA_PERI_IN_SEL_CH1_S) +#define DMA_PERI_IN_SEL_CH1_V 0x0000003F +#define DMA_PERI_IN_SEL_CH1_S 0 + +/* DMA_OUT_CONF0_CH1_REG register + * DMA_OUT_CONF0_CH1_REG. + */ + +#define DMA_OUT_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x190) + +/* DMA_OUT_DATA_BURST_EN_CH1 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 + * transmitting data when accessing internal SRAM. + */ + +#define DMA_OUT_DATA_BURST_EN_CH1 (BIT(5)) +#define DMA_OUT_DATA_BURST_EN_CH1_M (DMA_OUT_DATA_BURST_EN_CH1_V << DMA_OUT_DATA_BURST_EN_CH1_S) +#define DMA_OUT_DATA_BURST_EN_CH1_V 0x00000001 +#define DMA_OUT_DATA_BURST_EN_CH1_S 5 + +/* DMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading + * link descriptor when accessing internal SRAM. + */ + +#define DMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) +#define DMA_OUTDSCR_BURST_EN_CH1_M (DMA_OUTDSCR_BURST_EN_CH1_V << DMA_OUTDSCR_BURST_EN_CH1_S) +#define DMA_OUTDSCR_BURST_EN_CH1_V 0x00000001 +#define DMA_OUTDSCR_BURST_EN_CH1_S 4 + +/* DMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx + * channel 1 is generated when data need to transmit has been popped from + * FIFO in DMA + */ + +#define DMA_OUT_EOF_MODE_CH1 (BIT(3)) +#define DMA_OUT_EOF_MODE_CH1_M (DMA_OUT_EOF_MODE_CH1_V << DMA_OUT_EOF_MODE_CH1_S) +#define DMA_OUT_EOF_MODE_CH1_V 0x00000001 +#define DMA_OUT_EOF_MODE_CH1_S 3 + +/* DMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in + * tx buffer has been transmitted. + */ + +#define DMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) +#define DMA_OUT_AUTO_WRBACK_CH1_M (DMA_OUT_AUTO_WRBACK_CH1_V << DMA_OUT_AUTO_WRBACK_CH1_S) +#define DMA_OUT_AUTO_WRBACK_CH1_V 0x00000001 +#define DMA_OUT_AUTO_WRBACK_CH1_S 2 + +/* DMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; + * reserved + */ + +#define DMA_OUT_LOOP_TEST_CH1 (BIT(1)) +#define DMA_OUT_LOOP_TEST_CH1_M (DMA_OUT_LOOP_TEST_CH1_V << DMA_OUT_LOOP_TEST_CH1_S) +#define DMA_OUT_LOOP_TEST_CH1_V 0x00000001 +#define DMA_OUT_LOOP_TEST_CH1_S 1 + +/* DMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. + */ + +#define DMA_OUT_RST_CH1 (BIT(0)) +#define DMA_OUT_RST_CH1_M (DMA_OUT_RST_CH1_V << DMA_OUT_RST_CH1_S) +#define DMA_OUT_RST_CH1_V 0x00000001 +#define DMA_OUT_RST_CH1_S 0 + +/* DMA_OUT_CONF1_CH1_REG register + * DMA_OUT_CONF1_CH1_REG. + */ + +#define DMA_OUT_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x194) + +/* DMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link + * descriptor. + */ + +#define DMA_OUT_CHECK_OWNER_CH1 (BIT(12)) +#define DMA_OUT_CHECK_OWNER_CH1_M (DMA_OUT_CHECK_OWNER_CH1_V << DMA_OUT_CHECK_OWNER_CH1_S) +#define DMA_OUT_CHECK_OWNER_CH1_V 0x00000001 +#define DMA_OUT_CHECK_OWNER_CH1_S 12 + +/* DMA_OUTFIFO_STATUS_CH1_REG register + * DMA_OUTFIFO_STATUS_CH1_REG. + */ + +#define DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x198) + +/* DMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_4B_CH1 (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_CH1_M (DMA_OUT_REMAIN_UNDER_4B_CH1_V << DMA_OUT_REMAIN_UNDER_4B_CH1_S) +#define DMA_OUT_REMAIN_UNDER_4B_CH1_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_4B_CH1_S 26 + +/* DMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_3B_CH1 (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_CH1_M (DMA_OUT_REMAIN_UNDER_3B_CH1_V << DMA_OUT_REMAIN_UNDER_3B_CH1_S) +#define DMA_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_3B_CH1_S 25 + +/* DMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_2B_CH1 (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_CH1_M (DMA_OUT_REMAIN_UNDER_2B_CH1_V << DMA_OUT_REMAIN_UNDER_2B_CH1_S) +#define DMA_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_2B_CH1_S 24 + +/* DMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_1B_CH1 (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_CH1_M (DMA_OUT_REMAIN_UNDER_1B_CH1_V << DMA_OUT_REMAIN_UNDER_1B_CH1_S) +#define DMA_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_1B_CH1_S 23 + +/* DMA_OUTFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx + * channel 1. + */ + +#define DMA_OUTFIFO_CNT_CH1 0x0000003F +#define DMA_OUTFIFO_CNT_CH1_M (DMA_OUTFIFO_CNT_CH1_V << DMA_OUTFIFO_CNT_CH1_S) +#define DMA_OUTFIFO_CNT_CH1_V 0x0000003F +#define DMA_OUTFIFO_CNT_CH1_S 2 + +/* DMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 1. + */ + +#define DMA_OUTFIFO_EMPTY_CH1 (BIT(1)) +#define DMA_OUTFIFO_EMPTY_CH1_M (DMA_OUTFIFO_EMPTY_CH1_V << DMA_OUTFIFO_EMPTY_CH1_S) +#define DMA_OUTFIFO_EMPTY_CH1_V 0x00000001 +#define DMA_OUTFIFO_EMPTY_CH1_S 1 + +/* DMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 1. + */ + +#define DMA_OUTFIFO_FULL_CH1 (BIT(0)) +#define DMA_OUTFIFO_FULL_CH1_M (DMA_OUTFIFO_FULL_CH1_V << DMA_OUTFIFO_FULL_CH1_S) +#define DMA_OUTFIFO_FULL_CH1_V 0x00000001 +#define DMA_OUTFIFO_FULL_CH1_S 0 + +/* DMA_OUT_PUSH_CH1_REG register + * DMA_OUT_PUSH_CH1_REG. + */ + +#define DMA_OUT_PUSH_CH1_REG (DR_REG_GDMA_BASE + 0x19c) + +/* DMA_OUTFIFO_PUSH_CH1 : R/W/SC; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ + +#define DMA_OUTFIFO_PUSH_CH1 (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH1_M (DMA_OUTFIFO_PUSH_CH1_V << DMA_OUTFIFO_PUSH_CH1_S) +#define DMA_OUTFIFO_PUSH_CH1_V 0x00000001 +#define DMA_OUTFIFO_PUSH_CH1_S 9 + +/* DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ + +#define DMA_OUTFIFO_WDATA_CH1 0x000001FF +#define DMA_OUTFIFO_WDATA_CH1_M (DMA_OUTFIFO_WDATA_CH1_V << DMA_OUTFIFO_WDATA_CH1_S) +#define DMA_OUTFIFO_WDATA_CH1_V 0x000001FF +#define DMA_OUTFIFO_WDATA_CH1_S 0 + +/* DMA_OUT_LINK_CH1_REG register + * DMA_OUT_LINK_CH1_REG. + */ + +#define DMA_OUT_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x1a0) + +/* DMA_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink + * descriptor's FSM is working. + */ + +#define DMA_OUTLINK_PARK_CH1 (BIT(23)) +#define DMA_OUTLINK_PARK_CH1_M (DMA_OUTLINK_PARK_CH1_V << DMA_OUTLINK_PARK_CH1_S) +#define DMA_OUTLINK_PARK_CH1_V 0x00000001 +#define DMA_OUTLINK_PARK_CH1_S 23 + +/* DMA_OUTLINK_RESTART_CH1 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ + +#define DMA_OUTLINK_RESTART_CH1 (BIT(22)) +#define DMA_OUTLINK_RESTART_CH1_M (DMA_OUTLINK_RESTART_CH1_V << DMA_OUTLINK_RESTART_CH1_S) +#define DMA_OUTLINK_RESTART_CH1_V 0x00000001 +#define DMA_OUTLINK_RESTART_CH1_S 22 + +/* DMA_OUTLINK_START_CH1 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ + +#define DMA_OUTLINK_START_CH1 (BIT(21)) +#define DMA_OUTLINK_START_CH1_M (DMA_OUTLINK_START_CH1_V << DMA_OUTLINK_START_CH1_S) +#define DMA_OUTLINK_START_CH1_V 0x00000001 +#define DMA_OUTLINK_START_CH1_S 21 + +/* DMA_OUTLINK_STOP_CH1 : R/W/SC; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ + +#define DMA_OUTLINK_STOP_CH1 (BIT(20)) +#define DMA_OUTLINK_STOP_CH1_M (DMA_OUTLINK_STOP_CH1_V << DMA_OUTLINK_STOP_CH1_S) +#define DMA_OUTLINK_STOP_CH1_V 0x00000001 +#define DMA_OUTLINK_STOP_CH1_S 20 + +/* DMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ + +#define DMA_OUTLINK_ADDR_CH1 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH1_M (DMA_OUTLINK_ADDR_CH1_V << DMA_OUTLINK_ADDR_CH1_S) +#define DMA_OUTLINK_ADDR_CH1_V 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH1_S 0 + +/* DMA_OUT_STATE_CH1_REG register + * DMA_OUT_STATE_CH1_REG. + */ + +#define DMA_OUT_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x1a4) + +/* DMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0; + * reserved + */ + +#define DMA_OUT_STATE_CH1 0x00000007 +#define DMA_OUT_STATE_CH1_M (DMA_OUT_STATE_CH1_V << DMA_OUT_STATE_CH1_S) +#define DMA_OUT_STATE_CH1_V 0x00000007 +#define DMA_OUT_STATE_CH1_S 20 + +/* DMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; + * reserved + */ + +#define DMA_OUT_DSCR_STATE_CH1 0x00000003 +#define DMA_OUT_DSCR_STATE_CH1_M (DMA_OUT_DSCR_STATE_CH1_V << DMA_OUT_DSCR_STATE_CH1_S) +#define DMA_OUT_DSCR_STATE_CH1_V 0x00000003 +#define DMA_OUT_DSCR_STATE_CH1_S 18 + +/* DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ + +#define DMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH1_M (DMA_OUTLINK_DSCR_ADDR_CH1_V << DMA_OUTLINK_DSCR_ADDR_CH1_S) +#define DMA_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH1_S 0 + +/* DMA_OUT_EOF_DES_ADDR_CH1_REG register + * DMA_OUT_EOF_DES_ADDR_CH1_REG. + */ + +#define DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1a8) + +/* DMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF + * bit in this descriptor is 1. + */ + +#define DMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH1_M (DMA_OUT_EOF_DES_ADDR_CH1_V << DMA_OUT_EOF_DES_ADDR_CH1_S) +#define DMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH1_S 0 + +/* DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register + * DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG. + */ + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1ac) + +/* DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the + * last outlink descriptor. + */ + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_M (DMA_OUT_EOF_BFR_DES_ADDR_CH1_V << DMA_OUT_EOF_BFR_DES_ADDR_CH1_S) +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 + +/* DMA_OUT_DSCR_CH1_REG register + * DMA_OUT_DSCR_CH1_REG. + */ + +#define DMA_OUT_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x1b0) + +/* DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ + +#define DMA_OUTLINK_DSCR_CH1 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH1_M (DMA_OUTLINK_DSCR_CH1_V << DMA_OUTLINK_DSCR_CH1_S) +#define DMA_OUTLINK_DSCR_CH1_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH1_S 0 + +/* DMA_OUT_DSCR_BF0_CH1_REG register + * DMA_OUT_DSCR_BF0_CH1_REG. + */ + +#define DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x1b4) + +/* DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ + +#define DMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH1_M (DMA_OUTLINK_DSCR_BF0_CH1_V << DMA_OUTLINK_DSCR_BF0_CH1_S) +#define DMA_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH1_S 0 + +/* DMA_OUT_DSCR_BF1_CH1_REG register + * DMA_OUT_DSCR_BF1_CH1_REG. + */ + +#define DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x1b8) + +/* DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + +#define DMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH1_M (DMA_OUTLINK_DSCR_BF1_CH1_V << DMA_OUTLINK_DSCR_BF1_CH1_S) +#define DMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH1_S 0 + +/* DMA_OUT_PRI_CH1_REG register + * DMA_OUT_PRI_CH1_REG. + */ + +#define DMA_OUT_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x1bc) + +/* DMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 1. The larger of the value, the higher of the + * priority. + */ + +#define DMA_TX_PRI_CH1 0x0000000F +#define DMA_TX_PRI_CH1_M (DMA_TX_PRI_CH1_V << DMA_TX_PRI_CH1_S) +#define DMA_TX_PRI_CH1_V 0x0000000F +#define DMA_TX_PRI_CH1_S 0 + +/* DMA_OUT_PERI_SEL_CH1_REG register + * DMA_OUT_PERI_SEL_CH1_REG. + */ + +#define DMA_OUT_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x1c0) + +/* DMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: + * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: + * ADC_DAC. + */ + +#define DMA_PERI_OUT_SEL_CH1 0x0000003F +#define DMA_PERI_OUT_SEL_CH1_M (DMA_PERI_OUT_SEL_CH1_V << DMA_PERI_OUT_SEL_CH1_S) +#define DMA_PERI_OUT_SEL_CH1_V 0x0000003F +#define DMA_PERI_OUT_SEL_CH1_S 0 + +/* DMA_IN_CONF0_CH2_REG register + * DMA_IN_CONF0_CH2_REG. + */ + +#define DMA_IN_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x1f0) + +/* DMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Set this bit 1 to enable automatic transmitting data from memory to + * memory via DMA. + */ + +#define DMA_MEM_TRANS_EN_CH2 (BIT(4)) +#define DMA_MEM_TRANS_EN_CH2_M (DMA_MEM_TRANS_EN_CH2_V << DMA_MEM_TRANS_EN_CH2_S) +#define DMA_MEM_TRANS_EN_CH2_V 0x00000001 +#define DMA_MEM_TRANS_EN_CH2_S 4 + +/* DMA_IN_DATA_BURST_EN_CH2 : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 + * receiving data when accessing internal SRAM. + */ + +#define DMA_IN_DATA_BURST_EN_CH2 (BIT(3)) +#define DMA_IN_DATA_BURST_EN_CH2_M (DMA_IN_DATA_BURST_EN_CH2_V << DMA_IN_DATA_BURST_EN_CH2_S) +#define DMA_IN_DATA_BURST_EN_CH2_V 0x00000001 +#define DMA_IN_DATA_BURST_EN_CH2_S 3 + +/* DMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading + * link descriptor when accessing internal SRAM. + */ + +#define DMA_INDSCR_BURST_EN_CH2 (BIT(2)) +#define DMA_INDSCR_BURST_EN_CH2_M (DMA_INDSCR_BURST_EN_CH2_V << DMA_INDSCR_BURST_EN_CH2_S) +#define DMA_INDSCR_BURST_EN_CH2_V 0x00000001 +#define DMA_INDSCR_BURST_EN_CH2_S 2 + +/* DMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; + * reserved + */ + +#define DMA_IN_LOOP_TEST_CH2 (BIT(1)) +#define DMA_IN_LOOP_TEST_CH2_M (DMA_IN_LOOP_TEST_CH2_V << DMA_IN_LOOP_TEST_CH2_S) +#define DMA_IN_LOOP_TEST_CH2_V 0x00000001 +#define DMA_IN_LOOP_TEST_CH2_S 1 + +/* DMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer. + */ + +#define DMA_IN_RST_CH2 (BIT(0)) +#define DMA_IN_RST_CH2_M (DMA_IN_RST_CH2_V << DMA_IN_RST_CH2_S) +#define DMA_IN_RST_CH2_V 0x00000001 +#define DMA_IN_RST_CH2_S 0 + +/* DMA_IN_CONF1_CH2_REG register + * DMA_IN_CONF1_CH2_REG. + */ + +#define DMA_IN_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x1f4) + +/* DMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link + * descriptor. + */ + +#define DMA_IN_CHECK_OWNER_CH2 (BIT(12)) +#define DMA_IN_CHECK_OWNER_CH2_M (DMA_IN_CHECK_OWNER_CH2_V << DMA_IN_CHECK_OWNER_CH2_S) +#define DMA_IN_CHECK_OWNER_CH2_V 0x00000001 +#define DMA_IN_CHECK_OWNER_CH2_S 12 + +/* DMA_INFIFO_STATUS_CH2_REG register + * DMA_INFIFO_STATUS_CH2_REG. + */ + +#define DMA_INFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x1f8) + +/* DMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [27]; default: 0; + * reserved + */ + +#define DMA_IN_BUF_HUNGRY_CH2 (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH2_M (DMA_IN_BUF_HUNGRY_CH2_V << DMA_IN_BUF_HUNGRY_CH2_S) +#define DMA_IN_BUF_HUNGRY_CH2_V 0x00000001 +#define DMA_IN_BUF_HUNGRY_CH2_S 27 + +/* DMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_CH2_M (DMA_IN_REMAIN_UNDER_4B_CH2_V << DMA_IN_REMAIN_UNDER_4B_CH2_S) +#define DMA_IN_REMAIN_UNDER_4B_CH2_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_4B_CH2_S 26 + +/* DMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_CH2_M (DMA_IN_REMAIN_UNDER_3B_CH2_V << DMA_IN_REMAIN_UNDER_3B_CH2_S) +#define DMA_IN_REMAIN_UNDER_3B_CH2_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_3B_CH2_S 25 + +/* DMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_CH2_M (DMA_IN_REMAIN_UNDER_2B_CH2_V << DMA_IN_REMAIN_UNDER_2B_CH2_S) +#define DMA_IN_REMAIN_UNDER_2B_CH2_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_2B_CH2_S 24 + +/* DMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; + * reserved + */ + +#define DMA_IN_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_CH2_M (DMA_IN_REMAIN_UNDER_1B_CH2_V << DMA_IN_REMAIN_UNDER_1B_CH2_S) +#define DMA_IN_REMAIN_UNDER_1B_CH2_V 0x00000001 +#define DMA_IN_REMAIN_UNDER_1B_CH2_S 23 + +/* DMA_INFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Rx FIFO for Rx + * channel 2. + */ + +#define DMA_INFIFO_CNT_CH2 0x0000003F +#define DMA_INFIFO_CNT_CH2_M (DMA_INFIFO_CNT_CH2_V << DMA_INFIFO_CNT_CH2_S) +#define DMA_INFIFO_CNT_CH2_V 0x0000003F +#define DMA_INFIFO_CNT_CH2_S 2 + +/* DMA_INFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; + * L1 Rx FIFO empty signal for Rx channel 2. + */ + +#define DMA_INFIFO_EMPTY_CH2 (BIT(1)) +#define DMA_INFIFO_EMPTY_CH2_M (DMA_INFIFO_EMPTY_CH2_V << DMA_INFIFO_EMPTY_CH2_S) +#define DMA_INFIFO_EMPTY_CH2_V 0x00000001 +#define DMA_INFIFO_EMPTY_CH2_S 1 + +/* DMA_INFIFO_FULL_CH2 : RO; bitpos: [0]; default: 1; + * L1 Rx FIFO full signal for Rx channel 2. + */ + +#define DMA_INFIFO_FULL_CH2 (BIT(0)) +#define DMA_INFIFO_FULL_CH2_M (DMA_INFIFO_FULL_CH2_V << DMA_INFIFO_FULL_CH2_S) +#define DMA_INFIFO_FULL_CH2_V 0x00000001 +#define DMA_INFIFO_FULL_CH2_S 0 + +/* DMA_IN_POP_CH2_REG register + * DMA_IN_POP_CH2_REG. + */ + +#define DMA_IN_POP_CH2_REG (DR_REG_GDMA_BASE + 0x1fc) + +/* DMA_INFIFO_POP_CH2 : R/W/SC; bitpos: [12]; default: 0; + * Set this bit to pop data from DMA FIFO. + */ + +#define DMA_INFIFO_POP_CH2 (BIT(12)) +#define DMA_INFIFO_POP_CH2_M (DMA_INFIFO_POP_CH2_V << DMA_INFIFO_POP_CH2_S) +#define DMA_INFIFO_POP_CH2_V 0x00000001 +#define DMA_INFIFO_POP_CH2_S 12 + +/* DMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048; + * This register stores the data popping from DMA FIFO. + */ + +#define DMA_INFIFO_RDATA_CH2 0x00000FFF +#define DMA_INFIFO_RDATA_CH2_M (DMA_INFIFO_RDATA_CH2_V << DMA_INFIFO_RDATA_CH2_S) +#define DMA_INFIFO_RDATA_CH2_V 0x00000FFF +#define DMA_INFIFO_RDATA_CH2_S 0 + +/* DMA_IN_LINK_CH2_REG register + * DMA_IN_LINK_CH2_REG. + */ + +#define DMA_IN_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x200) + +/* DMA_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1; + * 1: the inlink descriptor's FSM is in idle state. 0: the inlink + * descriptor's FSM is working. + */ + +#define DMA_INLINK_PARK_CH2 (BIT(24)) +#define DMA_INLINK_PARK_CH2_M (DMA_INLINK_PARK_CH2_V << DMA_INLINK_PARK_CH2_S) +#define DMA_INLINK_PARK_CH2_V 0x00000001 +#define DMA_INLINK_PARK_CH2_S 24 + +/* DMA_INLINK_RESTART_CH2 : R/W/SC; bitpos: [23]; default: 0; + * Set this bit to mount a new inlink descriptor. + */ + +#define DMA_INLINK_RESTART_CH2 (BIT(23)) +#define DMA_INLINK_RESTART_CH2_M (DMA_INLINK_RESTART_CH2_V << DMA_INLINK_RESTART_CH2_S) +#define DMA_INLINK_RESTART_CH2_V 0x00000001 +#define DMA_INLINK_RESTART_CH2_S 23 + +/* DMA_INLINK_START_CH2 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to start dealing with the inlink descriptors. + */ + +#define DMA_INLINK_START_CH2 (BIT(22)) +#define DMA_INLINK_START_CH2_M (DMA_INLINK_START_CH2_V << DMA_INLINK_START_CH2_S) +#define DMA_INLINK_START_CH2_V 0x00000001 +#define DMA_INLINK_START_CH2_S 22 + +/* DMA_INLINK_STOP_CH2 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to stop dealing with the inlink descriptors. + */ + +#define DMA_INLINK_STOP_CH2 (BIT(21)) +#define DMA_INLINK_STOP_CH2_M (DMA_INLINK_STOP_CH2_V << DMA_INLINK_STOP_CH2_S) +#define DMA_INLINK_STOP_CH2_V 0x00000001 +#define DMA_INLINK_STOP_CH2_S 21 + +/* DMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1; + * Set this bit to return to current inlink descriptor's address, when there + * are some errors in current receiving data. + */ + +#define DMA_INLINK_AUTO_RET_CH2 (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH2_M (DMA_INLINK_AUTO_RET_CH2_V << DMA_INLINK_AUTO_RET_CH2_S) +#define DMA_INLINK_AUTO_RET_CH2_V 0x00000001 +#define DMA_INLINK_AUTO_RET_CH2_S 20 + +/* DMA_INLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first inlink + * descriptor's address. + */ + +#define DMA_INLINK_ADDR_CH2 0x000FFFFF +#define DMA_INLINK_ADDR_CH2_M (DMA_INLINK_ADDR_CH2_V << DMA_INLINK_ADDR_CH2_S) +#define DMA_INLINK_ADDR_CH2_V 0x000FFFFF +#define DMA_INLINK_ADDR_CH2_S 0 + +/* DMA_IN_STATE_CH2_REG register + * DMA_IN_STATE_CH2_REG. + */ + +#define DMA_IN_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x204) + +/* DMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ + +#define DMA_IN_STATE_CH2 0x00000007 +#define DMA_IN_STATE_CH2_M (DMA_IN_STATE_CH2_V << DMA_IN_STATE_CH2_S) +#define DMA_IN_STATE_CH2_V 0x00000007 +#define DMA_IN_STATE_CH2_S 20 + +/* DMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ + +#define DMA_IN_DSCR_STATE_CH2 0x00000003 +#define DMA_IN_DSCR_STATE_CH2_M (DMA_IN_DSCR_STATE_CH2_V << DMA_IN_DSCR_STATE_CH2_S) +#define DMA_IN_DSCR_STATE_CH2_V 0x00000003 +#define DMA_IN_DSCR_STATE_CH2_S 18 + +/* DMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * This register stores the current inlink descriptor's address. + */ + +#define DMA_INLINK_DSCR_ADDR_CH2 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH2_M (DMA_INLINK_DSCR_ADDR_CH2_V << DMA_INLINK_DSCR_ADDR_CH2_S) +#define DMA_INLINK_DSCR_ADDR_CH2_V 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH2_S 0 + +/* DMA_IN_SUC_EOF_DES_ADDR_CH2_REG register + * DMA_IN_SUC_EOF_DES_ADDR_CH2_REG. + */ + +#define DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x208) + +/* DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when the EOF + * bit in this descriptor is 1. + */ + +#define DMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH2_M (DMA_IN_SUC_EOF_DES_ADDR_CH2_V << DMA_IN_SUC_EOF_DES_ADDR_CH2_S) +#define DMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH2_S 0 + +/* DMA_IN_ERR_EOF_DES_ADDR_CH2_REG register + * DMA_IN_ERR_EOF_DES_ADDR_CH2_REG. + */ + +#define DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x20c) + +/* DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the inlink descriptor when there are + * some errors in current receiving data. Only used when peripheral is UHCI0. + */ + +#define DMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH2_M (DMA_IN_ERR_EOF_DES_ADDR_CH2_V << DMA_IN_ERR_EOF_DES_ADDR_CH2_S) +#define DMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH2_S 0 + +/* DMA_IN_DSCR_CH2_REG register + * DMA_IN_DSCR_CH2_REG. + */ + +#define DMA_IN_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x210) + +/* DMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the current inlink descriptor x. + */ + +#define DMA_INLINK_DSCR_CH2 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH2_M (DMA_INLINK_DSCR_CH2_V << DMA_INLINK_DSCR_CH2_S) +#define DMA_INLINK_DSCR_CH2_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH2_S 0 + +/* DMA_IN_DSCR_BF0_CH2_REG register + * DMA_IN_DSCR_BF0_CH2_REG. + */ + +#define DMA_IN_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x214) + +/* DMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the last inlink descriptor x-1. + */ + +#define DMA_INLINK_DSCR_BF0_CH2 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH2_M (DMA_INLINK_DSCR_BF0_CH2_V << DMA_INLINK_DSCR_BF0_CH2_S) +#define DMA_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH2_S 0 + +/* DMA_IN_DSCR_BF1_CH2_REG register + * DMA_IN_DSCR_BF1_CH2_REG. + */ + +#define DMA_IN_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x218) + +/* DMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + +#define DMA_INLINK_DSCR_BF1_CH2 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH2_M (DMA_INLINK_DSCR_BF1_CH2_V << DMA_INLINK_DSCR_BF1_CH2_S) +#define DMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH2_S 0 + +/* DMA_IN_PRI_CH2_REG register + * DMA_IN_PRI_CH2_REG. + */ + +#define DMA_IN_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x21c) + +/* DMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; + * The priority of Rx channel 2. The larger of the value, the higher of the + * priority. + */ + +#define DMA_RX_PRI_CH2 0x0000000F +#define DMA_RX_PRI_CH2_M (DMA_RX_PRI_CH2_V << DMA_RX_PRI_CH2_S) +#define DMA_RX_PRI_CH2_V 0x0000000F +#define DMA_RX_PRI_CH2_S 0 + +/* DMA_IN_PERI_SEL_CH2_REG register + * DMA_IN_PERI_SEL_CH2_REG. + */ + +#define DMA_IN_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x220) + +/* DMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: + * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: + * ADC_DAC. + */ + +#define DMA_PERI_IN_SEL_CH2 0x0000003F +#define DMA_PERI_IN_SEL_CH2_M (DMA_PERI_IN_SEL_CH2_V << DMA_PERI_IN_SEL_CH2_S) +#define DMA_PERI_IN_SEL_CH2_V 0x0000003F +#define DMA_PERI_IN_SEL_CH2_S 0 + +/* DMA_OUT_CONF0_CH2_REG register + * DMA_OUT_CONF0_CH2_REG. + */ + +#define DMA_OUT_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x250) + +/* DMA_OUT_DATA_BURST_EN_CH2 : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 + * transmitting data when accessing internal SRAM. + */ + +#define DMA_OUT_DATA_BURST_EN_CH2 (BIT(5)) +#define DMA_OUT_DATA_BURST_EN_CH2_M (DMA_OUT_DATA_BURST_EN_CH2_V << DMA_OUT_DATA_BURST_EN_CH2_S) +#define DMA_OUT_DATA_BURST_EN_CH2_V 0x00000001 +#define DMA_OUT_DATA_BURST_EN_CH2_S 5 + +/* DMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [4]; default: 0; + * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading + * link descriptor when accessing internal SRAM. + */ + +#define DMA_OUTDSCR_BURST_EN_CH2 (BIT(4)) +#define DMA_OUTDSCR_BURST_EN_CH2_M (DMA_OUTDSCR_BURST_EN_CH2_V << DMA_OUTDSCR_BURST_EN_CH2_S) +#define DMA_OUTDSCR_BURST_EN_CH2_V 0x00000001 +#define DMA_OUTDSCR_BURST_EN_CH2_S 4 + +/* DMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1; + * EOF flag generation mode when transmitting data. 1: EOF flag for Tx + * channel 2 is generated when data need to transmit has been popped from + * FIFO in DMA + */ + +#define DMA_OUT_EOF_MODE_CH2 (BIT(3)) +#define DMA_OUT_EOF_MODE_CH2_M (DMA_OUT_EOF_MODE_CH2_V << DMA_OUT_EOF_MODE_CH2_S) +#define DMA_OUT_EOF_MODE_CH2_V 0x00000001 +#define DMA_OUT_EOF_MODE_CH2_S 3 + +/* DMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable automatic outlink-writeback when all the data in + * tx buffer has been transmitted. + */ + +#define DMA_OUT_AUTO_WRBACK_CH2 (BIT(2)) +#define DMA_OUT_AUTO_WRBACK_CH2_M (DMA_OUT_AUTO_WRBACK_CH2_V << DMA_OUT_AUTO_WRBACK_CH2_S) +#define DMA_OUT_AUTO_WRBACK_CH2_V 0x00000001 +#define DMA_OUT_AUTO_WRBACK_CH2_S 2 + +/* DMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; + * reserved + */ + +#define DMA_OUT_LOOP_TEST_CH2 (BIT(1)) +#define DMA_OUT_LOOP_TEST_CH2_M (DMA_OUT_LOOP_TEST_CH2_V << DMA_OUT_LOOP_TEST_CH2_S) +#define DMA_OUT_LOOP_TEST_CH2_V 0x00000001 +#define DMA_OUT_LOOP_TEST_CH2_S 1 + +/* DMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0; + * This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer. + */ + +#define DMA_OUT_RST_CH2 (BIT(0)) +#define DMA_OUT_RST_CH2_M (DMA_OUT_RST_CH2_V << DMA_OUT_RST_CH2_S) +#define DMA_OUT_RST_CH2_V 0x00000001 +#define DMA_OUT_RST_CH2_S 0 + +/* DMA_OUT_CONF1_CH2_REG register + * DMA_OUT_CONF1_CH2_REG. + */ + +#define DMA_OUT_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x254) + +/* DMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; + * Set this bit to enable checking the owner attribute of the link + * descriptor. + */ + +#define DMA_OUT_CHECK_OWNER_CH2 (BIT(12)) +#define DMA_OUT_CHECK_OWNER_CH2_M (DMA_OUT_CHECK_OWNER_CH2_V << DMA_OUT_CHECK_OWNER_CH2_S) +#define DMA_OUT_CHECK_OWNER_CH2_V 0x00000001 +#define DMA_OUT_CHECK_OWNER_CH2_S 12 + +/* DMA_OUTFIFO_STATUS_CH2_REG register + * DMA_OUTFIFO_STATUS_CH2_REG. + */ + +#define DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x258) + +/* DMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_4B_CH2 (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_CH2_M (DMA_OUT_REMAIN_UNDER_4B_CH2_V << DMA_OUT_REMAIN_UNDER_4B_CH2_S) +#define DMA_OUT_REMAIN_UNDER_4B_CH2_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_4B_CH2_S 26 + +/* DMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_3B_CH2 (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_CH2_M (DMA_OUT_REMAIN_UNDER_3B_CH2_V << DMA_OUT_REMAIN_UNDER_3B_CH2_S) +#define DMA_OUT_REMAIN_UNDER_3B_CH2_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_3B_CH2_S 25 + +/* DMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_2B_CH2 (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_CH2_M (DMA_OUT_REMAIN_UNDER_2B_CH2_V << DMA_OUT_REMAIN_UNDER_2B_CH2_S) +#define DMA_OUT_REMAIN_UNDER_2B_CH2_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_2B_CH2_S 24 + +/* DMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; + * reserved + */ + +#define DMA_OUT_REMAIN_UNDER_1B_CH2 (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_CH2_M (DMA_OUT_REMAIN_UNDER_1B_CH2_V << DMA_OUT_REMAIN_UNDER_1B_CH2_S) +#define DMA_OUT_REMAIN_UNDER_1B_CH2_V 0x00000001 +#define DMA_OUT_REMAIN_UNDER_1B_CH2_S 23 + +/* DMA_OUTFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; + * The register stores the byte number of the data in L1 Tx FIFO for Tx + * channel 2. + */ + +#define DMA_OUTFIFO_CNT_CH2 0x0000003F +#define DMA_OUTFIFO_CNT_CH2_M (DMA_OUTFIFO_CNT_CH2_V << DMA_OUTFIFO_CNT_CH2_S) +#define DMA_OUTFIFO_CNT_CH2_V 0x0000003F +#define DMA_OUTFIFO_CNT_CH2_S 2 + +/* DMA_OUTFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; + * L1 Tx FIFO empty signal for Tx channel 2. + */ + +#define DMA_OUTFIFO_EMPTY_CH2 (BIT(1)) +#define DMA_OUTFIFO_EMPTY_CH2_M (DMA_OUTFIFO_EMPTY_CH2_V << DMA_OUTFIFO_EMPTY_CH2_S) +#define DMA_OUTFIFO_EMPTY_CH2_V 0x00000001 +#define DMA_OUTFIFO_EMPTY_CH2_S 1 + +/* DMA_OUTFIFO_FULL_CH2 : RO; bitpos: [0]; default: 0; + * L1 Tx FIFO full signal for Tx channel 2. + */ + +#define DMA_OUTFIFO_FULL_CH2 (BIT(0)) +#define DMA_OUTFIFO_FULL_CH2_M (DMA_OUTFIFO_FULL_CH2_V << DMA_OUTFIFO_FULL_CH2_S) +#define DMA_OUTFIFO_FULL_CH2_V 0x00000001 +#define DMA_OUTFIFO_FULL_CH2_S 0 + +/* DMA_OUT_PUSH_CH2_REG register + * DMA_OUT_PUSH_CH2_REG. + */ + +#define DMA_OUT_PUSH_CH2_REG (DR_REG_GDMA_BASE + 0x25c) + +/* DMA_OUTFIFO_PUSH_CH2 : R/W/SC; bitpos: [9]; default: 0; + * Set this bit to push data into DMA FIFO. + */ + +#define DMA_OUTFIFO_PUSH_CH2 (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH2_M (DMA_OUTFIFO_PUSH_CH2_V << DMA_OUTFIFO_PUSH_CH2_S) +#define DMA_OUTFIFO_PUSH_CH2_V 0x00000001 +#define DMA_OUTFIFO_PUSH_CH2_S 9 + +/* DMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0; + * This register stores the data that need to be pushed into DMA FIFO. + */ + +#define DMA_OUTFIFO_WDATA_CH2 0x000001FF +#define DMA_OUTFIFO_WDATA_CH2_M (DMA_OUTFIFO_WDATA_CH2_V << DMA_OUTFIFO_WDATA_CH2_S) +#define DMA_OUTFIFO_WDATA_CH2_V 0x000001FF +#define DMA_OUTFIFO_WDATA_CH2_S 0 + +/* DMA_OUT_LINK_CH2_REG register + * DMA_OUT_LINK_CH2_REG. + */ + +#define DMA_OUT_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x260) + +/* DMA_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1; + * 1: the outlink descriptor's FSM is in idle state. 0: the outlink + * descriptor's FSM is working. + */ + +#define DMA_OUTLINK_PARK_CH2 (BIT(23)) +#define DMA_OUTLINK_PARK_CH2_M (DMA_OUTLINK_PARK_CH2_V << DMA_OUTLINK_PARK_CH2_S) +#define DMA_OUTLINK_PARK_CH2_V 0x00000001 +#define DMA_OUTLINK_PARK_CH2_S 23 + +/* DMA_OUTLINK_RESTART_CH2 : R/W/SC; bitpos: [22]; default: 0; + * Set this bit to restart a new outlink from the last address. + */ + +#define DMA_OUTLINK_RESTART_CH2 (BIT(22)) +#define DMA_OUTLINK_RESTART_CH2_M (DMA_OUTLINK_RESTART_CH2_V << DMA_OUTLINK_RESTART_CH2_S) +#define DMA_OUTLINK_RESTART_CH2_V 0x00000001 +#define DMA_OUTLINK_RESTART_CH2_S 22 + +/* DMA_OUTLINK_START_CH2 : R/W/SC; bitpos: [21]; default: 0; + * Set this bit to start dealing with the outlink descriptors. + */ + +#define DMA_OUTLINK_START_CH2 (BIT(21)) +#define DMA_OUTLINK_START_CH2_M (DMA_OUTLINK_START_CH2_V << DMA_OUTLINK_START_CH2_S) +#define DMA_OUTLINK_START_CH2_V 0x00000001 +#define DMA_OUTLINK_START_CH2_S 21 + +/* DMA_OUTLINK_STOP_CH2 : R/W/SC; bitpos: [20]; default: 0; + * Set this bit to stop dealing with the outlink descriptors. + */ + +#define DMA_OUTLINK_STOP_CH2 (BIT(20)) +#define DMA_OUTLINK_STOP_CH2_M (DMA_OUTLINK_STOP_CH2_V << DMA_OUTLINK_STOP_CH2_S) +#define DMA_OUTLINK_STOP_CH2_V 0x00000001 +#define DMA_OUTLINK_STOP_CH2_S 20 + +/* DMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0; + * This register stores the 20 least significant bits of the first outlink + * descriptor's address. + */ + +#define DMA_OUTLINK_ADDR_CH2 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH2_M (DMA_OUTLINK_ADDR_CH2_V << DMA_OUTLINK_ADDR_CH2_S) +#define DMA_OUTLINK_ADDR_CH2_V 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH2_S 0 + +/* DMA_OUT_STATE_CH2_REG register + * DMA_OUT_STATE_CH2_REG. + */ + +#define DMA_OUT_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x264) + +/* DMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0; + * reserved + */ + +#define DMA_OUT_STATE_CH2 0x00000007 +#define DMA_OUT_STATE_CH2_M (DMA_OUT_STATE_CH2_V << DMA_OUT_STATE_CH2_S) +#define DMA_OUT_STATE_CH2_V 0x00000007 +#define DMA_OUT_STATE_CH2_S 20 + +/* DMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; + * reserved + */ + +#define DMA_OUT_DSCR_STATE_CH2 0x00000003 +#define DMA_OUT_DSCR_STATE_CH2_M (DMA_OUT_DSCR_STATE_CH2_V << DMA_OUT_DSCR_STATE_CH2_S) +#define DMA_OUT_DSCR_STATE_CH2_V 0x00000003 +#define DMA_OUT_DSCR_STATE_CH2_S 18 + +/* DMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; + * This register stores the current outlink descriptor's address. + */ + +#define DMA_OUTLINK_DSCR_ADDR_CH2 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH2_M (DMA_OUTLINK_DSCR_ADDR_CH2_V << DMA_OUTLINK_DSCR_ADDR_CH2_S) +#define DMA_OUTLINK_DSCR_ADDR_CH2_V 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH2_S 0 + +/* DMA_OUT_EOF_DES_ADDR_CH2_REG register + * DMA_OUT_EOF_DES_ADDR_CH2_REG. + */ + +#define DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x268) + +/* DMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor when the EOF + * bit in this descriptor is 1. + */ + +#define DMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH2_M (DMA_OUT_EOF_DES_ADDR_CH2_V << DMA_OUT_EOF_DES_ADDR_CH2_S) +#define DMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH2_S 0 + +/* DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register + * DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG. + */ + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x26c) + +/* DMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; + * This register stores the address of the outlink descriptor before the + * last outlink descriptor. + */ + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_M (DMA_OUT_EOF_BFR_DES_ADDR_CH2_V << DMA_OUT_EOF_BFR_DES_ADDR_CH2_S) +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0 + +/* DMA_OUT_DSCR_CH2_REG register + * DMA_OUT_DSCR_CH2_REG. + */ + +#define DMA_OUT_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x270) + +/* DMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the current outlink descriptor y. + */ + +#define DMA_OUTLINK_DSCR_CH2 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH2_M (DMA_OUTLINK_DSCR_CH2_V << DMA_OUTLINK_DSCR_CH2_S) +#define DMA_OUTLINK_DSCR_CH2_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH2_S 0 + +/* DMA_OUT_DSCR_BF0_CH2_REG register + * DMA_OUT_DSCR_BF0_CH2_REG. + */ + +#define DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x274) + +/* DMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the last outlink descriptor y-1. + */ + +#define DMA_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH2_M (DMA_OUTLINK_DSCR_BF0_CH2_V << DMA_OUTLINK_DSCR_BF0_CH2_S) +#define DMA_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH2_S 0 + +/* DMA_OUT_DSCR_BF1_CH2_REG register + * DMA_OUT_DSCR_BF1_CH2_REG. + */ + +#define DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x278) + +/* DMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; + * The address of the second-to-last inlink descriptor x-2. + */ + +#define DMA_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH2_M (DMA_OUTLINK_DSCR_BF1_CH2_V << DMA_OUTLINK_DSCR_BF1_CH2_S) +#define DMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH2_S 0 + +/* DMA_OUT_PRI_CH2_REG register + * DMA_OUT_PRI_CH2_REG. + */ + +#define DMA_OUT_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x27c) + +/* DMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; + * The priority of Tx channel 2. The larger of the value, the higher of the + * priority. + */ + +#define DMA_TX_PRI_CH2 0x0000000F +#define DMA_TX_PRI_CH2_M (DMA_TX_PRI_CH2_V << DMA_TX_PRI_CH2_S) +#define DMA_TX_PRI_CH2_V 0x0000000F +#define DMA_TX_PRI_CH2_S 0 + +/* DMA_OUT_PERI_SEL_CH2_REG register + * DMA_OUT_PERI_SEL_CH2_REG. + */ + +#define DMA_OUT_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x280) + +/* DMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; + * This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: + * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: + * ADC_DAC. + */ + +#define DMA_PERI_OUT_SEL_CH2 0x0000003F +#define DMA_PERI_OUT_SEL_CH2_M (DMA_PERI_OUT_SEL_CH2_V << DMA_PERI_OUT_SEL_CH2_S) +#define DMA_PERI_OUT_SEL_CH2_V 0x0000003F +#define DMA_PERI_OUT_SEL_CH2_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_DMA_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_efuse.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_efuse.h new file mode 100644 index 0000000000000..dd0076fb2f224 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_efuse.h @@ -0,0 +1,3282 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_efuse.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_EFUSE_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_EFUSE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* EFUSE_PGM_DATA0_REG register + * Register 0 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) + +/* EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_0 0xFFFFFFFF +#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) +#define EFUSE_PGM_DATA_0_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_0_S 0 + +/* EFUSE_PGM_DATA1_REG register + * Register 1 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) + +/* EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_1 0xFFFFFFFF +#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) +#define EFUSE_PGM_DATA_1_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_1_S 0 + +/* EFUSE_PGM_DATA2_REG register + * Register 2 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) + +/* EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_2 0xFFFFFFFF +#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) +#define EFUSE_PGM_DATA_2_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_2_S 0 + +/* EFUSE_PGM_DATA3_REG register + * Register 3 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) + +/* EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; + * The content of the 3th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_3 0xFFFFFFFF +#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) +#define EFUSE_PGM_DATA_3_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_3_S 0 + +/* EFUSE_PGM_DATA4_REG register + * Register 4 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) + +/* EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; + * The content of the 4th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_4 0xFFFFFFFF +#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) +#define EFUSE_PGM_DATA_4_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_4_S 0 + +/* EFUSE_PGM_DATA5_REG register + * Register 5 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) + +/* EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; + * The content of the 5th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_5 0xFFFFFFFF +#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) +#define EFUSE_PGM_DATA_5_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_5_S 0 + +/* EFUSE_PGM_DATA6_REG register + * Register 6 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) + +/* EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; + * The content of the 6th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_6 0xFFFFFFFF +#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) +#define EFUSE_PGM_DATA_6_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_6_S 0 + +/* EFUSE_PGM_DATA7_REG register + * Register 7 that stores data to be programmed. + */ + +#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) + +/* EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; + * The content of the 7th 32-bit data to be programmed. + */ + +#define EFUSE_PGM_DATA_7 0xFFFFFFFF +#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) +#define EFUSE_PGM_DATA_7_V 0xFFFFFFFF +#define EFUSE_PGM_DATA_7_S 0 + +/* EFUSE_PGM_CHECK_VALUE0_REG register + * Register 0 that stores the RS code to be programmed. + */ + +#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) + +/* EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; + * The content of the 0th 32-bit RS code to be programmed. + */ + +#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) +#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_0_S 0 + +/* EFUSE_PGM_CHECK_VALUE1_REG register + * Register 1 that stores the RS code to be programmed. + */ + +#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) + +/* EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; + * The content of the 1th 32-bit RS code to be programmed. + */ + +#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) +#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_1_S 0 + +/* EFUSE_PGM_CHECK_VALUE2_REG register + * Register 2 that stores the RS code to be programmed. + */ + +#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) + +/* EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; + * The content of the 2th 32-bit RS code to be programmed. + */ + +#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) +#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF +#define EFUSE_PGM_RS_DATA_2_S 0 + +/* EFUSE_RD_WR_DIS_REG register + * Register 0 of BLOCK0. + */ + +#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) + +/* EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; + * Disables programming of individual eFuses. + */ + +#define EFUSE_WR_DIS 0xFFFFFFFF +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0xFFFFFFFF +#define EFUSE_WR_DIS_S 0 + +/* EFUSE_RD_REPEAT_DATA0_REG register + * Register 1 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) + +/* EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; + * Disables software reading from individual eFuse blocks (BLOCK4-10). + */ + +#define EFUSE_RD_DIS 0x0000007F +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000007F +#define EFUSE_RD_DIS_S 0 + +/* EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0; + * Set this bit to disable boot from RTC RAM. + */ + +#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_M (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S) +#define EFUSE_DIS_RTC_RAM_BOOT_V 0x00000001 +#define EFUSE_DIS_RTC_RAM_BOOT_S 7 + +/* EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; + * Set this bit to disable Icache. + */ + +#define EFUSE_DIS_ICACHE (BIT(8)) +#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) +#define EFUSE_DIS_ICACHE_V 0x00000001 +#define EFUSE_DIS_ICACHE_S 8 + +/* EFUSE_DIS_DCACHE : RO; bitpos: [9]; default: 0; + * Set this bit to disable Dcache. + */ + +#define EFUSE_DIS_DCACHE (BIT(9)) +#define EFUSE_DIS_DCACHE_M (EFUSE_DIS_DCACHE_V << EFUSE_DIS_DCACHE_S) +#define EFUSE_DIS_DCACHE_V 0x00000001 +#define EFUSE_DIS_DCACHE_S 9 + +/* EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0; + * Disables Icache when SoC is in Download mode. + */ + +#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 + +/* EFUSE_DIS_DOWNLOAD_DCACHE : RO; bitpos: [11]; default: 0; + * Disables Dcache when SoC is in Download mode. + */ + +#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) +#define EFUSE_DIS_DOWNLOAD_DCACHE_M (EFUSE_DIS_DOWNLOAD_DCACHE_V << EFUSE_DIS_DOWNLOAD_DCACHE_S) +#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 + +/* EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; + * Set this bit to disable the function that forces chip into download mode. + */ + +#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001 +#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 + +/* EFUSE_DIS_USB : RO; bitpos: [13]; default: 0; + * Set this bit to disable USB function. + */ + +#define EFUSE_DIS_USB (BIT(13)) +#define EFUSE_DIS_USB_M (EFUSE_DIS_USB_V << EFUSE_DIS_USB_S) +#define EFUSE_DIS_USB_V 0x00000001 +#define EFUSE_DIS_USB_S 13 + +/* EFUSE_DIS_CAN : RO; bitpos: [14]; default: 0; + * Set this bit to disable CAN function. + */ + +#define EFUSE_DIS_CAN (BIT(14)) +#define EFUSE_DIS_CAN_M (EFUSE_DIS_CAN_V << EFUSE_DIS_CAN_S) +#define EFUSE_DIS_CAN_V 0x00000001 +#define EFUSE_DIS_CAN_S 14 + +/* EFUSE_DIS_BOOT_REMAP : RO; bitpos: [15]; default: 0; + * Disables capability to Remap RAM to ROM address space. + */ + +#define EFUSE_DIS_BOOT_REMAP (BIT(15)) +#define EFUSE_DIS_BOOT_REMAP_M (EFUSE_DIS_BOOT_REMAP_V << EFUSE_DIS_BOOT_REMAP_S) +#define EFUSE_DIS_BOOT_REMAP_V 0x00000001 +#define EFUSE_DIS_BOOT_REMAP_S 15 + +/* EFUSE_DIS_EFUSE_ATE_WR : RO; bitpos: [16]; default: 0; */ + +#define EFUSE_DIS_EFUSE_ATE_WR (BIT(16)) +#define EFUSE_DIS_EFUSE_ATE_WR_M (EFUSE_DIS_EFUSE_ATE_WR_V << EFUSE_DIS_EFUSE_ATE_WR_S) +#define EFUSE_DIS_EFUSE_ATE_WR_V 0x00000001 +#define EFUSE_DIS_EFUSE_ATE_WR_S 16 + +/* EFUSE_SOFT_DIS_JTAG : RO; bitpos: [17]; default: 0; + * Software disables JTAG. When software disabled, JTAG can be activated + * temporarily by HMAC peripheral. + */ + +#define EFUSE_SOFT_DIS_JTAG (BIT(17)) +#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) +#define EFUSE_SOFT_DIS_JTAG_V 0x00000001 +#define EFUSE_SOFT_DIS_JTAG_S 17 + +/* EFUSE_HARD_DIS_JTAG : RO; bitpos: [18]; default: 0; + * Hardware disables JTAG permanently. + */ + +#define EFUSE_HARD_DIS_JTAG (BIT(18)) +#define EFUSE_HARD_DIS_JTAG_M (EFUSE_HARD_DIS_JTAG_V << EFUSE_HARD_DIS_JTAG_S) +#define EFUSE_HARD_DIS_JTAG_V 0x00000001 +#define EFUSE_HARD_DIS_JTAG_S 18 + +/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [19]; default: 0; + * Disables flash encryption when in download boot modes. + */ + +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(19)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 19 + +/* EFUSE_USB_DREFH : RO; bitpos: [21:20]; default: 0; + * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 + * mV, stored in eFuse. + */ + +#define EFUSE_USB_DREFH 0x00000003 +#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) +#define EFUSE_USB_DREFH_V 0x00000003 +#define EFUSE_USB_DREFH_S 20 + +/* EFUSE_USB_DREFL : RO; bitpos: [23:22]; default: 0; + * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of + * 80 mV, stored in eFuse. + */ + +#define EFUSE_USB_DREFL 0x00000003 +#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) +#define EFUSE_USB_DREFL_V 0x00000003 +#define EFUSE_USB_DREFL_S 22 + +/* EFUSE_USB_EXCHG_PINS : RO; bitpos: [24]; default: 0; + * Set this bit to exchange USB D+ and D- pins. + */ + +#define EFUSE_USB_EXCHG_PINS (BIT(24)) +#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) +#define EFUSE_USB_EXCHG_PINS_V 0x00000001 +#define EFUSE_USB_EXCHG_PINS_S 24 + +/* EFUSE_EXT_PHY_ENABLE : RO; bitpos: [25]; default: 0; + * Set this bit to enable external USB PHY. + */ + +#define EFUSE_EXT_PHY_ENABLE (BIT(25)) +#define EFUSE_EXT_PHY_ENABLE_M (EFUSE_EXT_PHY_ENABLE_V << EFUSE_EXT_PHY_ENABLE_S) +#define EFUSE_EXT_PHY_ENABLE_V 0x00000001 +#define EFUSE_EXT_PHY_ENABLE_S 25 + +/* EFUSE_USB_FORCE_NOPERSIST : RO; bitpos: [26]; default: 0; + * If set, forces USB BVALID to 1. + */ + +#define EFUSE_USB_FORCE_NOPERSIST (BIT(26)) +#define EFUSE_USB_FORCE_NOPERSIST_M (EFUSE_USB_FORCE_NOPERSIST_V << EFUSE_USB_FORCE_NOPERSIST_S) +#define EFUSE_USB_FORCE_NOPERSIST_V 0x00000001 +#define EFUSE_USB_FORCE_NOPERSIST_S 26 + +/* EFUSE_RPT4_RESERVED0 : RO; bitpos: [28:27]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED0 0x00000003 +#define EFUSE_RPT4_RESERVED0_M (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S) +#define EFUSE_RPT4_RESERVED0_V 0x00000003 +#define EFUSE_RPT4_RESERVED0_S 27 + +/* EFUSE_VDD_SPI_MODECURLIM : RO; bitpos: [29]; default: 0; + * SPI regulator switches current limit mode. + */ + +#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_M (EFUSE_VDD_SPI_MODECURLIM_V << EFUSE_VDD_SPI_MODECURLIM_S) +#define EFUSE_VDD_SPI_MODECURLIM_V 0x00000001 +#define EFUSE_VDD_SPI_MODECURLIM_S 29 + +/* EFUSE_VDD_SPI_DREFH : RO; bitpos: [31:30]; default: 0; + * SPI regulator high voltage reference. + */ + +#define EFUSE_VDD_SPI_DREFH 0x00000003 +#define EFUSE_VDD_SPI_DREFH_M (EFUSE_VDD_SPI_DREFH_V << EFUSE_VDD_SPI_DREFH_S) +#define EFUSE_VDD_SPI_DREFH_V 0x00000003 +#define EFUSE_VDD_SPI_DREFH_S 30 + +/* EFUSE_RD_REPEAT_DATA1_REG register + * Register 2 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) + +/* EFUSE_VDD_SPI_DREFM : RO; bitpos: [1:0]; default: 0; + * SPI regulator medium voltage reference. + */ + +#define EFUSE_VDD_SPI_DREFM 0x00000003 +#define EFUSE_VDD_SPI_DREFM_M (EFUSE_VDD_SPI_DREFM_V << EFUSE_VDD_SPI_DREFM_S) +#define EFUSE_VDD_SPI_DREFM_V 0x00000003 +#define EFUSE_VDD_SPI_DREFM_S 0 + +/* EFUSE_VDD_SPI_DREFL : RO; bitpos: [3:2]; default: 0; + * SPI regulator low voltage reference. + */ + +#define EFUSE_VDD_SPI_DREFL 0x00000003 +#define EFUSE_VDD_SPI_DREFL_M (EFUSE_VDD_SPI_DREFL_V << EFUSE_VDD_SPI_DREFL_S) +#define EFUSE_VDD_SPI_DREFL_V 0x00000003 +#define EFUSE_VDD_SPI_DREFL_S 2 + +/* EFUSE_VDD_SPI_XPD : RO; bitpos: [4]; default: 0; + * If VDD_SPI_FORCE is 1, this value determines if the VDD_SPI regulator is + * powered on. + */ + +#define EFUSE_VDD_SPI_XPD (BIT(4)) +#define EFUSE_VDD_SPI_XPD_M (EFUSE_VDD_SPI_XPD_V << EFUSE_VDD_SPI_XPD_S) +#define EFUSE_VDD_SPI_XPD_V 0x00000001 +#define EFUSE_VDD_SPI_XPD_S 4 + +/* EFUSE_VDD_SPI_TIEH : RO; bitpos: [5]; default: 0; + * If VDD_SPI_FORCE is 1, determines VDD_SPI voltage. 0: VDD_SPI connects to + * 1.8 V LDO; 1: VDD_SPI connects to VDD_RTC_IO. + */ + +#define EFUSE_VDD_SPI_TIEH (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_M (EFUSE_VDD_SPI_TIEH_V << EFUSE_VDD_SPI_TIEH_S) +#define EFUSE_VDD_SPI_TIEH_V 0x00000001 +#define EFUSE_VDD_SPI_TIEH_S 5 + +/* EFUSE_VDD_SPI_FORCE : RO; bitpos: [6]; default: 0; + * Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI + * LDO. + */ + +#define EFUSE_VDD_SPI_FORCE (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_M (EFUSE_VDD_SPI_FORCE_V << EFUSE_VDD_SPI_FORCE_S) +#define EFUSE_VDD_SPI_FORCE_V 0x00000001 +#define EFUSE_VDD_SPI_FORCE_S 6 + +/* EFUSE_VDD_SPI_EN_INIT : RO; bitpos: [7]; default: 0; + * Set SPI regulator to 0 to configure init[1:0]=0. + */ + +#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_M (EFUSE_VDD_SPI_EN_INIT_V << EFUSE_VDD_SPI_EN_INIT_S) +#define EFUSE_VDD_SPI_EN_INIT_V 0x00000001 +#define EFUSE_VDD_SPI_EN_INIT_S 7 + +/* EFUSE_VDD_SPI_ENCURLIM : RO; bitpos: [8]; default: 0; + * Set SPI regulator to 1 to enable output current limit. + */ + +#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_M (EFUSE_VDD_SPI_ENCURLIM_V << EFUSE_VDD_SPI_ENCURLIM_S) +#define EFUSE_VDD_SPI_ENCURLIM_V 0x00000001 +#define EFUSE_VDD_SPI_ENCURLIM_S 8 + +/* EFUSE_VDD_SPI_DCURLIM : RO; bitpos: [11:9]; default: 0; + * Tunes the current limit threshold of SPI regulator when tieh=0, about 800 + * mA/(8+d). + */ + +#define EFUSE_VDD_SPI_DCURLIM 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_M (EFUSE_VDD_SPI_DCURLIM_V << EFUSE_VDD_SPI_DCURLIM_S) +#define EFUSE_VDD_SPI_DCURLIM_V 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_S 9 + +/* EFUSE_VDD_SPI_INIT : RO; bitpos: [13:12]; default: 0; + * Adds resistor from LDO output to ground. 0: no resistance; 1: 6 K; 2: 4 + * K; 3: 2 K. + */ + +#define EFUSE_VDD_SPI_INIT 0x00000003 +#define EFUSE_VDD_SPI_INIT_M (EFUSE_VDD_SPI_INIT_V << EFUSE_VDD_SPI_INIT_S) +#define EFUSE_VDD_SPI_INIT_V 0x00000003 +#define EFUSE_VDD_SPI_INIT_S 12 + +/* EFUSE_VDD_SPI_DCAP : RO; bitpos: [15:14]; default: 0; + * Prevents SPI regulator from overshoot. + */ + +#define EFUSE_VDD_SPI_DCAP 0x00000003 +#define EFUSE_VDD_SPI_DCAP_M (EFUSE_VDD_SPI_DCAP_V << EFUSE_VDD_SPI_DCAP_S) +#define EFUSE_VDD_SPI_DCAP_V 0x00000003 +#define EFUSE_VDD_SPI_DCAP_S 14 + +/* EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; + * Selects RTC watchdog timeout threshold at startup. 0: 40,000 slow clock + * cycles; 1: 80,000 slow clock cycles; 2: 160,000 slow clock cycles; 3: + * 320,000 slow clock cycles. + */ + +#define EFUSE_WDT_DELAY_SEL 0x00000003 +#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) +#define EFUSE_WDT_DELAY_SEL_V 0x00000003 +#define EFUSE_WDT_DELAY_SEL_S 16 + +/* EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; + * Enables encryption and decryption, when an SPI boot mode is set. Feature + * is enabled 1 or 3 bits are set in the eFuse, disabled otherwise. + */ + +#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; + * If set, revokes use of secure boot key digest 0. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; + * If set, revokes use of secure boot key digest 1. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; + * If set, revokes use of secure boot key digest 2. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 + +/* EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; + * Purpose of KEY0. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_0 0x0000000F +#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) +#define EFUSE_KEY_PURPOSE_0_V 0x0000000F +#define EFUSE_KEY_PURPOSE_0_S 24 + +/* EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; + * Purpose of KEY1. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_1 0x0000000F +#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) +#define EFUSE_KEY_PURPOSE_1_V 0x0000000F +#define EFUSE_KEY_PURPOSE_1_S 28 + +/* EFUSE_RD_REPEAT_DATA2_REG register + * Register 3 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) + +/* EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; + * Purpose of KEY2. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_2 0x0000000F +#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) +#define EFUSE_KEY_PURPOSE_2_V 0x0000000F +#define EFUSE_KEY_PURPOSE_2_S 0 + +/* EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; + * Purpose of KEY3. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_3 0x0000000F +#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) +#define EFUSE_KEY_PURPOSE_3_V 0x0000000F +#define EFUSE_KEY_PURPOSE_3_S 4 + +/* EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; + * Purpose of KEY4. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_4 0x0000000F +#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) +#define EFUSE_KEY_PURPOSE_4_V 0x0000000F +#define EFUSE_KEY_PURPOSE_4_S 8 + +/* EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; + * Purpose of KEY5. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_5 0x0000000F +#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) +#define EFUSE_KEY_PURPOSE_5_V 0x0000000F +#define EFUSE_KEY_PURPOSE_5_S 12 + +/* EFUSE_KEY_PURPOSE_6 : RO; bitpos: [19:16]; default: 0; + * Purpose of KEY6. Refer to Table Key Purpose Values. + */ + +#define EFUSE_KEY_PURPOSE_6 0x0000000F +#define EFUSE_KEY_PURPOSE_6_M (EFUSE_KEY_PURPOSE_6_V << EFUSE_KEY_PURPOSE_6_S) +#define EFUSE_KEY_PURPOSE_6_V 0x0000000F +#define EFUSE_KEY_PURPOSE_6_S 16 + +/* EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; + * Set this bit to enable secure boot. + */ + +#define EFUSE_SECURE_BOOT_EN (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) +#define EFUSE_SECURE_BOOT_EN_V 0x00000001 +#define EFUSE_SECURE_BOOT_EN_S 20 + +/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; + * Set this bit to enable aggressive secure boot key revocation mode. + */ + +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001 +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 + +/* EFUSE_RPT4_RESERVED1 : RO; bitpos: [27:22]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED1 0x0000003F +#define EFUSE_RPT4_RESERVED1_M (EFUSE_RPT4_RESERVED1_V << EFUSE_RPT4_RESERVED1_S) +#define EFUSE_RPT4_RESERVED1_V 0x0000003F +#define EFUSE_RPT4_RESERVED1_S 22 + +/* EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; + * Configures flash startup delay after SoC power-up, in unit of (ms/2). + * When the value is 15, delay is 7.5 ms. + */ + +#define EFUSE_FLASH_TPUW 0x0000000F +#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) +#define EFUSE_FLASH_TPUW_V 0x0000000F +#define EFUSE_FLASH_TPUW_S 28 + +/* EFUSE_RD_REPEAT_DATA3_REG register + * Register 4 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) + +/* EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; + * Set this bit to disable all download boot modes. + */ + +#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) +#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_MODE_S 0 + +/* EFUSE_DIS_LEGACY_SPI_BOOT : RO; bitpos: [1]; default: 0; + * Set this bit to disable Legacy SPI boot mode. + */ + +#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_M (EFUSE_DIS_LEGACY_SPI_BOOT_V << EFUSE_DIS_LEGACY_SPI_BOOT_S) +#define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x00000001 +#define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 + +/* EFUSE_UART_PRINT_CHANNEL : RO; bitpos: [2]; default: 0; + * Selects the default UART for printing boot messages. 0: UART0; 1: UART1. + */ + +#define EFUSE_UART_PRINT_CHANNEL (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_M (EFUSE_UART_PRINT_CHANNEL_V << EFUSE_UART_PRINT_CHANNEL_S) +#define EFUSE_UART_PRINT_CHANNEL_V 0x00000001 +#define EFUSE_UART_PRINT_CHANNEL_S 2 + +/* EFUSE_RPT4_RESERVED3 : RO; bitpos: [3]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED3 (BIT(3)) +#define EFUSE_RPT4_RESERVED3_M (EFUSE_RPT4_RESERVED3_V << EFUSE_RPT4_RESERVED3_S) +#define EFUSE_RPT4_RESERVED3_V 0x00000001 +#define EFUSE_RPT4_RESERVED3_S 3 + +/* EFUSE_DIS_USB_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; + * Set this bit to disable use of USB in UART download boot mode. + */ + +#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (EFUSE_DIS_USB_DOWNLOAD_MODE_V << EFUSE_DIS_USB_DOWNLOAD_MODE_S) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x00000001 +#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 + +/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; + * Set this bit to enable secure UART download mode (read/write flash only). + */ + +#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001 +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 + +/* EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; + * Set the default UART boot message output mode. + * & + * 00: Enabled.# + * 01: Enable when GPIO46 is low at reset.# + * 10: Enable when GPIO46 is high at reset.# + * 11: Disabled. + * & + */ + +#define EFUSE_UART_PRINT_CONTROL 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) +#define EFUSE_UART_PRINT_CONTROL_V 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_S 6 + +/* EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0; + * Set default power supply for GPIO33-GPIO37, set when SPI flash is + * initialized. 0: VDD3P3_CPU; 1: VDD_SPI. + */ + +#define EFUSE_PIN_POWER_SELECTION (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_M (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S) +#define EFUSE_PIN_POWER_SELECTION_V 0x00000001 +#define EFUSE_PIN_POWER_SELECTION_S 8 + +/* EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0; + * SPI flash type. 0: maximum four data lines, 1: eight data lines. + */ + +#define EFUSE_FLASH_TYPE (BIT(9)) +#define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) +#define EFUSE_FLASH_TYPE_V 0x00000001 +#define EFUSE_FLASH_TYPE_S 9 + +/* EFUSE_FORCE_SEND_RESUME : RO; bitpos: [10]; default: 0; + * If set, forces ROM code to send an SPI flash resume command during SPI + * boot. + */ + +#define EFUSE_FORCE_SEND_RESUME (BIT(10)) +#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) +#define EFUSE_FORCE_SEND_RESUME_V 0x00000001 +#define EFUSE_FORCE_SEND_RESUME_S 10 + +/* EFUSE_SECURE_VERSION : RO; bitpos: [26:11]; default: 0; + * Secure version (used by ESP-IDF anti-rollback feature). + */ + +#define EFUSE_SECURE_VERSION 0x0000FFFF +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0x0000FFFF +#define EFUSE_SECURE_VERSION_S 11 + +/* EFUSE_RPT4_RESERVED2 : RO; bitpos: [31:27]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED2 0x0000001F +#define EFUSE_RPT4_RESERVED2_M (EFUSE_RPT4_RESERVED2_V << EFUSE_RPT4_RESERVED2_S) +#define EFUSE_RPT4_RESERVED2_V 0x0000001F +#define EFUSE_RPT4_RESERVED2_S 27 + +/* EFUSE_RD_REPEAT_DATA4_REG register + * Register 5 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) + +/* EFUSE_RPT4_RESERVED4 : RO; bitpos: [23:0]; default: 0; + * Reserved (used for four backups method). + */ + +#define EFUSE_RPT4_RESERVED4 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_M (EFUSE_RPT4_RESERVED4_V << EFUSE_RPT4_RESERVED4_S) +#define EFUSE_RPT4_RESERVED4_V 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_0_REG register + * Register 0 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) + +/* EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; + * Stores the low 32 bits of MAC address. + */ + +#define EFUSE_MAC_0 0xFFFFFFFF +#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) +#define EFUSE_MAC_0_V 0xFFFFFFFF +#define EFUSE_MAC_0_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_1_REG register + * Register 1 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) + +/* EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; + * Stores the high 16 bits of MAC address. + */ + +#define EFUSE_MAC_1 0x0000FFFF +#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) +#define EFUSE_MAC_1_V 0x0000FFFF +#define EFUSE_MAC_1_S 0 + +/* EFUSE_SPI_PAD_CONF_0 : RO; bitpos: [31:16]; default: 0; + * Stores the zeroth part of SPI_PAD_CONF. + */ + +#define EFUSE_SPI_PAD_CONF_0 0x0000FFFF +#define EFUSE_SPI_PAD_CONF_0_M (EFUSE_SPI_PAD_CONF_0_V << EFUSE_SPI_PAD_CONF_0_S) +#define EFUSE_SPI_PAD_CONF_0_V 0x0000FFFF +#define EFUSE_SPI_PAD_CONF_0_S 16 + +/* EFUSE_RD_MAC_SPI_SYS_2_REG register + * Register 2 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) + +/* EFUSE_SPI_PAD_CONF_1 : RO; bitpos: [31:0]; default: 0; + * Stores the first part of SPI_PAD_CONF. + */ + +#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF +#define EFUSE_SPI_PAD_CONF_1_M (EFUSE_SPI_PAD_CONF_1_V << EFUSE_SPI_PAD_CONF_1_S) +#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF +#define EFUSE_SPI_PAD_CONF_1_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_3_REG register + * Register 3 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) + +/* EFUSE_SPI_PAD_CONF_2 : RO; bitpos: [17:0]; default: 0; + * Stores the second part of SPI_PAD_CONF. + */ + +#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF +#define EFUSE_SPI_PAD_CONF_2_M (EFUSE_SPI_PAD_CONF_2_V << EFUSE_SPI_PAD_CONF_2_S) +#define EFUSE_SPI_PAD_CONF_2_V 0x0003FFFF +#define EFUSE_SPI_PAD_CONF_2_S 0 + +/* EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; + * Stores the zeroth part of the zeroth part of system data. + */ + +#define EFUSE_SYS_DATA_PART0_0 0x00003FFF +#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) +#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFF +#define EFUSE_SYS_DATA_PART0_0_S 18 + +/* EFUSE_RD_MAC_SPI_SYS_4_REG register + * Register 4 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) + +/* EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; + * Stores the fist part of the zeroth part of system data. + */ + +#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) +#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_1_S 0 + +/* EFUSE_RD_MAC_SPI_SYS_5_REG register + * Register 5 of BLOCK1. + */ + +#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) + +/* EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; + * Stores the second part of the zeroth part of system data. + */ + +#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) +#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART0_2_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_0_REG register + * Register 0 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_0_REG (DR_REG_EFUSE_BASE + 0x5c) + +/* EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) +#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_0_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_1_REG register + * Register 1 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_1_REG (DR_REG_EFUSE_BASE + 0x60) + +/* EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) +#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_1_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_2_REG register + * Register 2 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_2_REG (DR_REG_EFUSE_BASE + 0x64) + +/* EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) +#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_2_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_3_REG register + * Register 3 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_3_REG (DR_REG_EFUSE_BASE + 0x68) + +/* EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) +#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_3_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_4_REG register + * Register 4 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_4_REG (DR_REG_EFUSE_BASE + 0x6c) + +/* EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) +#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_4_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_5_REG register + * Register 5 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_5_REG (DR_REG_EFUSE_BASE + 0x70) + +/* EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) +#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_5_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_6_REG register + * Register 6 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_6_REG (DR_REG_EFUSE_BASE + 0x74) + +/* EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) +#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_6_S 0 + +/* EFUSE_RD_SYS_DATA_PART1_7_REG register + * Register 7 of BLOCK2 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART1_7_REG (DR_REG_EFUSE_BASE + 0x78) + +/* EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the first part of system data. + */ + +#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) +#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART1_7_S 0 + +/* EFUSE_RD_USR_DATA0_REG register + * Register 0 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) + +/* EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA0 0xFFFFFFFF +#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) +#define EFUSE_USR_DATA0_V 0xFFFFFFFF +#define EFUSE_USR_DATA0_S 0 + +/* EFUSE_RD_USR_DATA1_REG register + * Register 1 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) + +/* EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA1 0xFFFFFFFF +#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) +#define EFUSE_USR_DATA1_V 0xFFFFFFFF +#define EFUSE_USR_DATA1_S 0 + +/* EFUSE_RD_USR_DATA2_REG register + * Register 2 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) + +/* EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA2 0xFFFFFFFF +#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) +#define EFUSE_USR_DATA2_V 0xFFFFFFFF +#define EFUSE_USR_DATA2_S 0 + +/* EFUSE_RD_USR_DATA3_REG register + * Register 3 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) + +/* EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA3 0xFFFFFFFF +#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) +#define EFUSE_USR_DATA3_V 0xFFFFFFFF +#define EFUSE_USR_DATA3_S 0 + +/* EFUSE_RD_USR_DATA4_REG register + * Register 4 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) + +/* EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA4 0xFFFFFFFF +#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) +#define EFUSE_USR_DATA4_V 0xFFFFFFFF +#define EFUSE_USR_DATA4_S 0 + +/* EFUSE_RD_USR_DATA5_REG register + * Register 5 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) + +/* EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA5 0xFFFFFFFF +#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) +#define EFUSE_USR_DATA5_V 0xFFFFFFFF +#define EFUSE_USR_DATA5_S 0 + +/* EFUSE_RD_USR_DATA6_REG register + * Register 6 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) + +/* EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA6 0xFFFFFFFF +#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) +#define EFUSE_USR_DATA6_V 0xFFFFFFFF +#define EFUSE_USR_DATA6_S 0 + +/* EFUSE_RD_USR_DATA7_REG register + * Register 7 of BLOCK3 (user). + */ + +#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) + +/* EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of BLOCK3 (user). + */ + +#define EFUSE_USR_DATA7 0xFFFFFFFF +#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) +#define EFUSE_USR_DATA7_V 0xFFFFFFFF +#define EFUSE_USR_DATA7_S 0 + +/* EFUSE_RD_KEY0_DATA0_REG register + * Register 0 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) + +/* EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA0 0xFFFFFFFF +#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) +#define EFUSE_KEY0_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA0_S 0 + +/* EFUSE_RD_KEY0_DATA1_REG register + * Register 1 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) + +/* EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA1 0xFFFFFFFF +#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) +#define EFUSE_KEY0_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA1_S 0 + +/* EFUSE_RD_KEY0_DATA2_REG register + * Register 2 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) + +/* EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA2 0xFFFFFFFF +#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) +#define EFUSE_KEY0_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA2_S 0 + +/* EFUSE_RD_KEY0_DATA3_REG register + * Register 3 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) + +/* EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA3 0xFFFFFFFF +#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) +#define EFUSE_KEY0_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA3_S 0 + +/* EFUSE_RD_KEY0_DATA4_REG register + * Register 4 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) + +/* EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA4 0xFFFFFFFF +#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) +#define EFUSE_KEY0_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA4_S 0 + +/* EFUSE_RD_KEY0_DATA5_REG register + * Register 5 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) + +/* EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA5 0xFFFFFFFF +#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) +#define EFUSE_KEY0_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA5_S 0 + +/* EFUSE_RD_KEY0_DATA6_REG register + * Register 6 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) + +/* EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA6 0xFFFFFFFF +#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) +#define EFUSE_KEY0_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA6_S 0 + +/* EFUSE_RD_KEY0_DATA7_REG register + * Register 7 of BLOCK4 (KEY0). + */ + +#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) + +/* EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY0. + */ + +#define EFUSE_KEY0_DATA7 0xFFFFFFFF +#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) +#define EFUSE_KEY0_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY0_DATA7_S 0 + +/* EFUSE_RD_KEY1_DATA0_REG register + * Register 0 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) + +/* EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA0 0xFFFFFFFF +#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) +#define EFUSE_KEY1_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA0_S 0 + +/* EFUSE_RD_KEY1_DATA1_REG register + * Register 1 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) + +/* EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA1 0xFFFFFFFF +#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) +#define EFUSE_KEY1_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA1_S 0 + +/* EFUSE_RD_KEY1_DATA2_REG register + * Register 2 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) + +/* EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA2 0xFFFFFFFF +#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) +#define EFUSE_KEY1_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA2_S 0 + +/* EFUSE_RD_KEY1_DATA3_REG register + * Register 3 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) + +/* EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA3 0xFFFFFFFF +#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) +#define EFUSE_KEY1_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA3_S 0 + +/* EFUSE_RD_KEY1_DATA4_REG register + * Register 4 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) + +/* EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA4 0xFFFFFFFF +#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) +#define EFUSE_KEY1_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA4_S 0 + +/* EFUSE_RD_KEY1_DATA5_REG register + * Register 5 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) + +/* EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA5 0xFFFFFFFF +#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) +#define EFUSE_KEY1_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA5_S 0 + +/* EFUSE_RD_KEY1_DATA6_REG register + * Register 6 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) + +/* EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA6 0xFFFFFFFF +#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) +#define EFUSE_KEY1_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA6_S 0 + +/* EFUSE_RD_KEY1_DATA7_REG register + * Register 7 of BLOCK5 (KEY1). + */ + +#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) + +/* EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY1. + */ + +#define EFUSE_KEY1_DATA7 0xFFFFFFFF +#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) +#define EFUSE_KEY1_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY1_DATA7_S 0 + +/* EFUSE_RD_KEY2_DATA0_REG register + * Register 0 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) + +/* EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA0 0xFFFFFFFF +#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) +#define EFUSE_KEY2_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA0_S 0 + +/* EFUSE_RD_KEY2_DATA1_REG register + * Register 1 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) + +/* EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA1 0xFFFFFFFF +#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) +#define EFUSE_KEY2_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA1_S 0 + +/* EFUSE_RD_KEY2_DATA2_REG register + * Register 2 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) + +/* EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA2 0xFFFFFFFF +#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) +#define EFUSE_KEY2_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA2_S 0 + +/* EFUSE_RD_KEY2_DATA3_REG register + * Register 3 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) + +/* EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA3 0xFFFFFFFF +#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) +#define EFUSE_KEY2_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA3_S 0 + +/* EFUSE_RD_KEY2_DATA4_REG register + * Register 4 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) + +/* EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA4 0xFFFFFFFF +#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) +#define EFUSE_KEY2_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA4_S 0 + +/* EFUSE_RD_KEY2_DATA5_REG register + * Register 5 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) + +/* EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA5 0xFFFFFFFF +#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) +#define EFUSE_KEY2_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA5_S 0 + +/* EFUSE_RD_KEY2_DATA6_REG register + * Register 6 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) + +/* EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA6 0xFFFFFFFF +#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) +#define EFUSE_KEY2_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA6_S 0 + +/* EFUSE_RD_KEY2_DATA7_REG register + * Register 7 of BLOCK6 (KEY2). + */ + +#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) + +/* EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY2. + */ + +#define EFUSE_KEY2_DATA7 0xFFFFFFFF +#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) +#define EFUSE_KEY2_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY2_DATA7_S 0 + +/* EFUSE_RD_KEY3_DATA0_REG register + * Register 0 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) + +/* EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA0 0xFFFFFFFF +#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) +#define EFUSE_KEY3_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA0_S 0 + +/* EFUSE_RD_KEY3_DATA1_REG register + * Register 1 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) + +/* EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA1 0xFFFFFFFF +#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) +#define EFUSE_KEY3_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA1_S 0 + +/* EFUSE_RD_KEY3_DATA2_REG register + * Register 2 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) + +/* EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA2 0xFFFFFFFF +#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) +#define EFUSE_KEY3_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA2_S 0 + +/* EFUSE_RD_KEY3_DATA3_REG register + * Register 3 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) + +/* EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA3 0xFFFFFFFF +#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) +#define EFUSE_KEY3_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA3_S 0 + +/* EFUSE_RD_KEY3_DATA4_REG register + * Register 4 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) + +/* EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA4 0xFFFFFFFF +#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) +#define EFUSE_KEY3_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA4_S 0 + +/* EFUSE_RD_KEY3_DATA5_REG register + * Register 5 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) + +/* EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA5 0xFFFFFFFF +#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) +#define EFUSE_KEY3_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA5_S 0 + +/* EFUSE_RD_KEY3_DATA6_REG register + * Register 6 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) + +/* EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA6 0xFFFFFFFF +#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) +#define EFUSE_KEY3_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA6_S 0 + +/* EFUSE_RD_KEY3_DATA7_REG register + * Register 7 of BLOCK7 (KEY3). + */ + +#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) + +/* EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY3. + */ + +#define EFUSE_KEY3_DATA7 0xFFFFFFFF +#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) +#define EFUSE_KEY3_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY3_DATA7_S 0 + +/* EFUSE_RD_KEY4_DATA0_REG register + * Register 0 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) + +/* EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA0 0xFFFFFFFF +#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) +#define EFUSE_KEY4_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA0_S 0 + +/* EFUSE_RD_KEY4_DATA1_REG register + * Register 1 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) + +/* EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA1 0xFFFFFFFF +#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) +#define EFUSE_KEY4_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA1_S 0 + +/* EFUSE_RD_KEY4_DATA2_REG register + * Register 2 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) + +/* EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA2 0xFFFFFFFF +#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) +#define EFUSE_KEY4_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA2_S 0 + +/* EFUSE_RD_KEY4_DATA3_REG register + * Register 3 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) + +/* EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA3 0xFFFFFFFF +#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) +#define EFUSE_KEY4_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA3_S 0 + +/* EFUSE_RD_KEY4_DATA4_REG register + * Register 4 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) + +/* EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA4 0xFFFFFFFF +#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) +#define EFUSE_KEY4_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA4_S 0 + +/* EFUSE_RD_KEY4_DATA5_REG register + * Register 5 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) + +/* EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA5 0xFFFFFFFF +#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) +#define EFUSE_KEY4_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA5_S 0 + +/* EFUSE_RD_KEY4_DATA6_REG register + * Register 6 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) + +/* EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA6 0xFFFFFFFF +#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) +#define EFUSE_KEY4_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA6_S 0 + +/* EFUSE_RD_KEY4_DATA7_REG register + * Register 7 of BLOCK8 (KEY4). + */ + +#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) + +/* EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY4. + */ + +#define EFUSE_KEY4_DATA7 0xFFFFFFFF +#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) +#define EFUSE_KEY4_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY4_DATA7_S 0 + +/* EFUSE_RD_KEY5_DATA0_REG register + * Register 0 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) + +/* EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA0 0xFFFFFFFF +#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) +#define EFUSE_KEY5_DATA0_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA0_S 0 + +/* EFUSE_RD_KEY5_DATA1_REG register + * Register 1 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) + +/* EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA1 0xFFFFFFFF +#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) +#define EFUSE_KEY5_DATA1_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA1_S 0 + +/* EFUSE_RD_KEY5_DATA2_REG register + * Register 2 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) + +/* EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA2 0xFFFFFFFF +#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) +#define EFUSE_KEY5_DATA2_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA2_S 0 + +/* EFUSE_RD_KEY5_DATA3_REG register + * Register 3 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) + +/* EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA3 0xFFFFFFFF +#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) +#define EFUSE_KEY5_DATA3_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA3_S 0 + +/* EFUSE_RD_KEY5_DATA4_REG register + * Register 4 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) + +/* EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA4 0xFFFFFFFF +#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) +#define EFUSE_KEY5_DATA4_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA4_S 0 + +/* EFUSE_RD_KEY5_DATA5_REG register + * Register 5 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) + +/* EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA5 0xFFFFFFFF +#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) +#define EFUSE_KEY5_DATA5_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA5_S 0 + +/* EFUSE_RD_KEY5_DATA6_REG register + * Register 6 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) + +/* EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA6 0xFFFFFFFF +#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) +#define EFUSE_KEY5_DATA6_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA6_S 0 + +/* EFUSE_RD_KEY5_DATA7_REG register + * Register 7 of BLOCK9 (KEY5). + */ + +#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) + +/* EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of KEY5. + */ + +#define EFUSE_KEY5_DATA7 0xFFFFFFFF +#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) +#define EFUSE_KEY5_DATA7_V 0xFFFFFFFF +#define EFUSE_KEY5_DATA7_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_0_REG register + * Register 0 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_0_REG (DR_REG_EFUSE_BASE + 0x15c) + +/* EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; + * Stores the 0th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) +#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_0_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_1_REG register + * Register 1 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_1_REG (DR_REG_EFUSE_BASE + 0x160) + +/* EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; + * Stores the 1th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) +#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_1_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_2_REG register + * Register 2 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_2_REG (DR_REG_EFUSE_BASE + 0x164) + +/* EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; + * Stores the 2th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) +#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_2_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_3_REG register + * Register 3 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_3_REG (DR_REG_EFUSE_BASE + 0x168) + +/* EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; + * Stores the 3th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) +#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_3_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_4_REG register + * Register 4 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_4_REG (DR_REG_EFUSE_BASE + 0x16c) + +/* EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; + * Stores the 4th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) +#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_4_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_5_REG register + * Register 5 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_5_REG (DR_REG_EFUSE_BASE + 0x170) + +/* EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; + * Stores the 5th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) +#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_5_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_6_REG register + * Register 6 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_6_REG (DR_REG_EFUSE_BASE + 0x174) + +/* EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; + * Stores the 6th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) +#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_6_S 0 + +/* EFUSE_RD_SYS_DATA_PART2_7_REG register + * Register 7 of BLOCK10 (system). + */ + +#define EFUSE_RD_SYS_DATA_PART2_7_REG (DR_REG_EFUSE_BASE + 0x178) + +/* EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; + * Stores the 7th 32 bits of the 2nd part of system data. + */ + +#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) +#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFF +#define EFUSE_SYS_DATA_PART2_7_S 0 + +/* EFUSE_RD_REPEAT_ERR0_REG register + * Programming error record register 0 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) + +/* EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RD_DIS. + */ + +#define EFUSE_RD_DIS_ERR 0x0000007F +#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) +#define EFUSE_RD_DIS_ERR_V 0x0000007F +#define EFUSE_RD_DIS_ERR_S 0 + +/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_RTC_RAM_BOOT. + */ + +#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S) +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x00000001 +#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 + +/* EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_ICACHE. + */ + +#define EFUSE_DIS_ICACHE_ERR (BIT(8)) +#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) +#define EFUSE_DIS_ICACHE_ERR_V 0x00000001 +#define EFUSE_DIS_ICACHE_ERR_S 8 + +/* EFUSE_DIS_DCACHE_ERR : RO; bitpos: [9]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DCACHE. + */ + +#define EFUSE_DIS_DCACHE_ERR (BIT(9)) +#define EFUSE_DIS_DCACHE_ERR_M (EFUSE_DIS_DCACHE_ERR_V << EFUSE_DIS_DCACHE_ERR_S) +#define EFUSE_DIS_DCACHE_ERR_V 0x00000001 +#define EFUSE_DIS_DCACHE_ERR_S 9 + +/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DOWNLOAD_ICACHE. + */ + +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 + +/* EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO; bitpos: [11]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DOWNLOAD_DCACHE. + */ + +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V << EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11 + +/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_FORCE_DOWNLOAD. + */ + +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001 +#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 + +/* EFUSE_DIS_USB_ERR : RO; bitpos: [13]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_USB. + */ + +#define EFUSE_DIS_USB_ERR (BIT(13)) +#define EFUSE_DIS_USB_ERR_M (EFUSE_DIS_USB_ERR_V << EFUSE_DIS_USB_ERR_S) +#define EFUSE_DIS_USB_ERR_V 0x00000001 +#define EFUSE_DIS_USB_ERR_S 13 + +/* EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_CAN. + */ + +#define EFUSE_DIS_CAN_ERR (BIT(14)) +#define EFUSE_DIS_CAN_ERR_M (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S) +#define EFUSE_DIS_CAN_ERR_V 0x00000001 +#define EFUSE_DIS_CAN_ERR_S 14 + +/* EFUSE_DIS_BOOT_REMAP_ERR : RO; bitpos: [15]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_BOOT_REMAP. + */ + +#define EFUSE_DIS_BOOT_REMAP_ERR (BIT(15)) +#define EFUSE_DIS_BOOT_REMAP_ERR_M (EFUSE_DIS_BOOT_REMAP_ERR_V << EFUSE_DIS_BOOT_REMAP_ERR_S) +#define EFUSE_DIS_BOOT_REMAP_ERR_V 0x00000001 +#define EFUSE_DIS_BOOT_REMAP_ERR_S 15 + +/* EFUSE_DIS_EFUSE_ATE_WR_ERR : RO; bitpos: [16]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_EFUSE_ATE_WR. + */ + +#define EFUSE_DIS_EFUSE_ATE_WR_ERR (BIT(16)) +#define EFUSE_DIS_EFUSE_ATE_WR_ERR_M (EFUSE_DIS_EFUSE_ATE_WR_ERR_V << EFUSE_DIS_EFUSE_ATE_WR_ERR_S) +#define EFUSE_DIS_EFUSE_ATE_WR_ERR_V 0x00000001 +#define EFUSE_DIS_EFUSE_ATE_WR_ERR_S 16 + +/* EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [17]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SOFT_DIS_JTAG. + */ + +#define EFUSE_SOFT_DIS_JTAG_ERR (BIT(17)) +#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) +#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000001 +#define EFUSE_SOFT_DIS_JTAG_ERR_S 17 + +/* EFUSE_HARD_DIS_JTAG_ERR : RO; bitpos: [18]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_HARD_DIS_JTAG. + */ + +#define EFUSE_HARD_DIS_JTAG_ERR (BIT(18)) +#define EFUSE_HARD_DIS_JTAG_ERR_M (EFUSE_HARD_DIS_JTAG_ERR_V << EFUSE_HARD_DIS_JTAG_ERR_S) +#define EFUSE_HARD_DIS_JTAG_ERR_V 0x00000001 +#define EFUSE_HARD_DIS_JTAG_ERR_S 18 + +/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [19]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT. + */ + +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(19)) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 19 + +/* EFUSE_USB_DREFH_ERR : RO; bitpos: [21:20]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_USB_DREFH. + */ + +#define EFUSE_USB_DREFH_ERR 0x00000003 +#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) +#define EFUSE_USB_DREFH_ERR_V 0x00000003 +#define EFUSE_USB_DREFH_ERR_S 20 + +/* EFUSE_USB_DREFL_ERR : RO; bitpos: [23:22]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_USB_DREFL. + */ + +#define EFUSE_USB_DREFL_ERR 0x00000003 +#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) +#define EFUSE_USB_DREFL_ERR_V 0x00000003 +#define EFUSE_USB_DREFL_ERR_S 22 + +/* EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [24]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_USB_EXCHG_PINS. + */ + +#define EFUSE_USB_EXCHG_PINS_ERR (BIT(24)) +#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) +#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001 +#define EFUSE_USB_EXCHG_PINS_ERR_S 24 + +/* EFUSE_EXT_PHY_ENABLE_ERR : RO; bitpos: [25]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_EXT_PHY_ENABLE. + */ + +#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(25)) +#define EFUSE_EXT_PHY_ENABLE_ERR_M (EFUSE_EXT_PHY_ENABLE_ERR_V << EFUSE_EXT_PHY_ENABLE_ERR_S) +#define EFUSE_EXT_PHY_ENABLE_ERR_V 0x00000001 +#define EFUSE_EXT_PHY_ENABLE_ERR_S 25 + +/* EFUSE_USB_FORCE_NOPERSIST_ERR : RO; bitpos: [26]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_USB_FORCE_NOPERSIST. + */ + +#define EFUSE_USB_FORCE_NOPERSIST_ERR (BIT(26)) +#define EFUSE_USB_FORCE_NOPERSIST_ERR_M (EFUSE_USB_FORCE_NOPERSIST_ERR_V << EFUSE_USB_FORCE_NOPERSIST_ERR_S) +#define EFUSE_USB_FORCE_NOPERSIST_ERR_V 0x00000001 +#define EFUSE_USB_FORCE_NOPERSIST_ERR_S 26 + +/* EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [28:27]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED0. + */ + +#define EFUSE_RPT4_RESERVED0_ERR 0x00000003 +#define EFUSE_RPT4_RESERVED0_ERR_M (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S) +#define EFUSE_RPT4_RESERVED0_ERR_V 0x00000003 +#define EFUSE_RPT4_RESERVED0_ERR_S 27 + +/* EFUSE_VDD_SPI_MODECURLIM_ERR : RO; bitpos: [29]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_MODECURLIM. + */ + +#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) +#define EFUSE_VDD_SPI_MODECURLIM_ERR_M (EFUSE_VDD_SPI_MODECURLIM_ERR_V << EFUSE_VDD_SPI_MODECURLIM_ERR_S) +#define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29 + +/* EFUSE_VDD_SPI_DREFH_ERR : RO; bitpos: [31:30]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DREFH. + */ + +#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003 +#define EFUSE_VDD_SPI_DREFH_ERR_M (EFUSE_VDD_SPI_DREFH_ERR_V << EFUSE_VDD_SPI_DREFH_ERR_S) +#define EFUSE_VDD_SPI_DREFH_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_DREFH_ERR_S 30 + +/* EFUSE_RD_REPEAT_ERR1_REG register + * Programming error record register 1 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) + +/* EFUSE_VDD_SPI_DREFM_ERR : RO; bitpos: [1:0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DREFM. + */ + +#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003 +#define EFUSE_VDD_SPI_DREFM_ERR_M (EFUSE_VDD_SPI_DREFM_ERR_V << EFUSE_VDD_SPI_DREFM_ERR_S) +#define EFUSE_VDD_SPI_DREFM_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_DREFM_ERR_S 0 + +/* EFUSE_VDD_SPI_DREFL_ERR : RO; bitpos: [3:2]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DREFL. + */ + +#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003 +#define EFUSE_VDD_SPI_DREFL_ERR_M (EFUSE_VDD_SPI_DREFL_ERR_V << EFUSE_VDD_SPI_DREFL_ERR_S) +#define EFUSE_VDD_SPI_DREFL_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_DREFL_ERR_S 2 + +/* EFUSE_VDD_SPI_XPD_ERR : RO; bitpos: [4]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_XPD. + */ + +#define EFUSE_VDD_SPI_XPD_ERR (BIT(4)) +#define EFUSE_VDD_SPI_XPD_ERR_M (EFUSE_VDD_SPI_XPD_ERR_V << EFUSE_VDD_SPI_XPD_ERR_S) +#define EFUSE_VDD_SPI_XPD_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_XPD_ERR_S 4 + +/* EFUSE_VDD_SPI_TIEH_ERR : RO; bitpos: [5]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_TIEH. + */ + +#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) +#define EFUSE_VDD_SPI_TIEH_ERR_M (EFUSE_VDD_SPI_TIEH_ERR_V << EFUSE_VDD_SPI_TIEH_ERR_S) +#define EFUSE_VDD_SPI_TIEH_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_TIEH_ERR_S 5 + +/* EFUSE_VDD_SPI_FORCE_ERR : RO; bitpos: [6]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_FORCE. + */ + +#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) +#define EFUSE_VDD_SPI_FORCE_ERR_M (EFUSE_VDD_SPI_FORCE_ERR_V << EFUSE_VDD_SPI_FORCE_ERR_S) +#define EFUSE_VDD_SPI_FORCE_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_FORCE_ERR_S 6 + +/* EFUSE_VDD_SPI_EN_INIT_ERR : RO; bitpos: [7]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_EN_INIT. + */ + +#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) +#define EFUSE_VDD_SPI_EN_INIT_ERR_M (EFUSE_VDD_SPI_EN_INIT_ERR_V << EFUSE_VDD_SPI_EN_INIT_ERR_S) +#define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_EN_INIT_ERR_S 7 + +/* EFUSE_VDD_SPI_ENCURLIM_ERR : RO; bitpos: [8]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_ENCURLIM. + */ + +#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) +#define EFUSE_VDD_SPI_ENCURLIM_ERR_M (EFUSE_VDD_SPI_ENCURLIM_ERR_V << EFUSE_VDD_SPI_ENCURLIM_ERR_S) +#define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x00000001 +#define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8 + +/* EFUSE_VDD_SPI_DCURLIM_ERR : RO; bitpos: [11:9]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DCURLIM. + */ + +#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_ERR_M (EFUSE_VDD_SPI_DCURLIM_ERR_V << EFUSE_VDD_SPI_DCURLIM_ERR_S) +#define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x00000007 +#define EFUSE_VDD_SPI_DCURLIM_ERR_S 9 + +/* EFUSE_VDD_SPI_INIT_ERR : RO; bitpos: [13:12]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_INIT. + */ + +#define EFUSE_VDD_SPI_INIT_ERR 0x00000003 +#define EFUSE_VDD_SPI_INIT_ERR_M (EFUSE_VDD_SPI_INIT_ERR_V << EFUSE_VDD_SPI_INIT_ERR_S) +#define EFUSE_VDD_SPI_INIT_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_INIT_ERR_S 12 + +/* EFUSE_VDD_SPI_DCAP_ERR : RO; bitpos: [15:14]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_VDD_SPI_DCAP. + */ + +#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003 +#define EFUSE_VDD_SPI_DCAP_ERR_M (EFUSE_VDD_SPI_DCAP_ERR_V << EFUSE_VDD_SPI_DCAP_ERR_S) +#define EFUSE_VDD_SPI_DCAP_ERR_V 0x00000003 +#define EFUSE_VDD_SPI_DCAP_ERR_S 14 + +/* EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_WDT_DELAY_SEL. + */ + +#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 +#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) +#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003 +#define EFUSE_WDT_DELAY_SEL_ERR_S 16 + +/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SPI_BOOT_CRYPT_CNT. + */ + +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007 +#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_KEY_REVOKE0. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_KEY_REVOKE1. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 + +/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_KEY_REVOKE2. + */ + +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 + +/* EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_0. + */ + +#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) +#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_0_ERR_S 24 + +/* EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_1. + */ + +#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) +#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_1_ERR_S 28 + +/* EFUSE_RD_REPEAT_ERR2_REG register + * Programming error record register 2 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) + +/* EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_2. + */ + +#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) +#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_2_ERR_S 0 + +/* EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_3. + */ + +#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) +#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_3_ERR_S 4 + +/* EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_4. + */ + +#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) +#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_4_ERR_S 8 + +/* EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_5. + */ + +#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) +#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_5_ERR_S 12 + +/* EFUSE_KEY_PURPOSE_6_ERR : RO; bitpos: [19:16]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_KEY_PURPOSE_6. + */ + +#define EFUSE_KEY_PURPOSE_6_ERR 0x0000000F +#define EFUSE_KEY_PURPOSE_6_ERR_M (EFUSE_KEY_PURPOSE_6_ERR_V << EFUSE_KEY_PURPOSE_6_ERR_S) +#define EFUSE_KEY_PURPOSE_6_ERR_V 0x0000000F +#define EFUSE_KEY_PURPOSE_6_ERR_S 16 + +/* EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_EN. + */ + +#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) +#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) +#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_EN_ERR_S 20 + +/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE. + */ + +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001 +#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 + +/* EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [27:22]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED1. + */ + +#define EFUSE_RPT4_RESERVED1_ERR 0x0000003F +#define EFUSE_RPT4_RESERVED1_ERR_M (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S) +#define EFUSE_RPT4_RESERVED1_ERR_V 0x0000003F +#define EFUSE_RPT4_RESERVED1_ERR_S 22 + +/* EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_FLASH_TPUW. + */ + +#define EFUSE_FLASH_TPUW_ERR 0x0000000F +#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) +#define EFUSE_FLASH_TPUW_ERR_V 0x0000000F +#define EFUSE_FLASH_TPUW_ERR_S 28 + +/* EFUSE_RD_REPEAT_ERR3_REG register + * Programming error record register 3 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) + +/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_DOWNLOAD_MODE. + */ + +#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001 +#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 + +/* EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_LEGACY_SPI_BOOT. + */ + +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S) +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x00000001 +#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 + +/* EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_UART_PRINT_CHANNEL. + */ + +#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) +#define EFUSE_UART_PRINT_CHANNEL_ERR_M (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S) +#define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x00000001 +#define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 + +/* EFUSE_RPT4_RESERVED3_ERR : RO; bitpos: [3]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED3. + */ + +#define EFUSE_RPT4_RESERVED3_ERR (BIT(3)) +#define EFUSE_RPT4_RESERVED3_ERR_M (EFUSE_RPT4_RESERVED3_ERR_V << EFUSE_RPT4_RESERVED3_ERR_S) +#define EFUSE_RPT4_RESERVED3_ERR_V 0x00000001 +#define EFUSE_RPT4_RESERVED3_ERR_S 3 + +/* EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_DIS_USB_DOWNLOAD_MODE. + */ + +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S) +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x00000001 +#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 + +/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_ENABLE_SECURITY_DOWNLOAD. + */ + +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001 +#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 + +/* EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_UART_PRINT_CONTROL. + */ + +#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) +#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003 +#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 + +/* EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_PIN_POWER_SELECTION. + */ + +#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) +#define EFUSE_PIN_POWER_SELECTION_ERR_M (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S) +#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x00000001 +#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 + +/* EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_FLASH_TYPE. + */ + +#define EFUSE_FLASH_TYPE_ERR (BIT(9)) +#define EFUSE_FLASH_TYPE_ERR_M (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S) +#define EFUSE_FLASH_TYPE_ERR_V 0x00000001 +#define EFUSE_FLASH_TYPE_ERR_S 9 + +/* EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [10]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_FORCE_SEND_RESUME. + */ + +#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(10)) +#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) +#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001 +#define EFUSE_FORCE_SEND_RESUME_ERR_S 10 + +/* EFUSE_SECURE_VERSION_ERR : RO; bitpos: [26:11]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_SECURE_VERSION. + */ + +#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF +#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) +#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFF +#define EFUSE_SECURE_VERSION_ERR_S 11 + +/* EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [31:27]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED2. + */ + +#define EFUSE_RPT4_RESERVED2_ERR 0x0000001F +#define EFUSE_RPT4_RESERVED2_ERR_M (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S) +#define EFUSE_RPT4_RESERVED2_ERR_V 0x0000001F +#define EFUSE_RPT4_RESERVED2_ERR_S 27 + +/* EFUSE_RD_REPEAT_ERR4_REG register + * Programming error record register 4 of BLOCK0. + */ + +#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) + +/* EFUSE_RPT4_RESERVED4_ERR : RO; bitpos: [23:0]; default: 0; + * If any bit in this parameter is 1, means a programming error in + * EFUSE_RPT4_RESERVED4. + */ + +#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_ERR_M (EFUSE_RPT4_RESERVED4_ERR_V << EFUSE_RPT4_RESERVED4_ERR_S) +#define EFUSE_RPT4_RESERVED4_ERR_V 0x00FFFFFF +#define EFUSE_RPT4_RESERVED4_ERR_S 0 + +/* EFUSE_RD_RS_ERR0_REG register + * Programming error record register 0 of BLOCK1-10. + */ + +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) + +/* EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes in BLOCK1. + */ + +#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007 +#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) +#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007 +#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 + +/* EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of BLOCK1 is reliable; 1: Means + * that programming BLOCK1 data failed and the number of error bytes is over + * 5. + */ + +#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) +#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) +#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001 +#define EFUSE_MAC_SPI_8M_FAIL_S 3 + +/* EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes in BLOCK2. + */ + +#define EFUSE_SYS_PART1_NUM 0x00000007 +#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) +#define EFUSE_SYS_PART1_NUM_V 0x00000007 +#define EFUSE_SYS_PART1_NUM_S 4 + +/* EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of BLOCK2 is reliable; 1: Means + * that programming BLOCK2 data failed and the number of error bytes is over + * 5. + */ + +#define EFUSE_SYS_PART1_FAIL (BIT(7)) +#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) +#define EFUSE_SYS_PART1_FAIL_V 0x00000001 +#define EFUSE_SYS_PART1_FAIL_S 7 + +/* EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; + * The value of this signal means the number of error bytes in BLOCK3. + */ + +#define EFUSE_USR_DATA_ERR_NUM 0x00000007 +#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) +#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007 +#define EFUSE_USR_DATA_ERR_NUM_S 8 + +/* EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; + * 0: Means no failure and that the data of BLOCK3 is reliable; 1: Means + * that programming BLOCK3 data failed and the number of error bytes is over + * 5. + */ + +#define EFUSE_USR_DATA_FAIL (BIT(11)) +#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) +#define EFUSE_USR_DATA_FAIL_V 0x00000001 +#define EFUSE_USR_DATA_FAIL_S 11 + +/* EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; + * The value of this signal means the number of error bytes in KEY0. + */ + +#define EFUSE_KEY0_ERR_NUM 0x00000007 +#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) +#define EFUSE_KEY0_ERR_NUM_V 0x00000007 +#define EFUSE_KEY0_ERR_NUM_S 12 + +/* EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; + * 0: Means no failure and that the data of KEY0 is reliable; 1: Means that + * programming KEY0 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY0_FAIL (BIT(15)) +#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) +#define EFUSE_KEY0_FAIL_V 0x00000001 +#define EFUSE_KEY0_FAIL_S 15 + +/* EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; + * The value of this signal means the number of error bytes in KEY1. + */ + +#define EFUSE_KEY1_ERR_NUM 0x00000007 +#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) +#define EFUSE_KEY1_ERR_NUM_V 0x00000007 +#define EFUSE_KEY1_ERR_NUM_S 16 + +/* EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; + * 0: Means no failure and that the data of KEY1 is reliable; 1: Means that + * programming KEY1 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY1_FAIL (BIT(19)) +#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) +#define EFUSE_KEY1_FAIL_V 0x00000001 +#define EFUSE_KEY1_FAIL_S 19 + +/* EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; + * The value of this signal means the number of error bytes in KEY2. + */ + +#define EFUSE_KEY2_ERR_NUM 0x00000007 +#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) +#define EFUSE_KEY2_ERR_NUM_V 0x00000007 +#define EFUSE_KEY2_ERR_NUM_S 20 + +/* EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; + * 0: Means no failure and that the data of KEY2 is reliable; 1: Means that + * programming KEY2 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY2_FAIL (BIT(23)) +#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) +#define EFUSE_KEY2_FAIL_V 0x00000001 +#define EFUSE_KEY2_FAIL_S 23 + +/* EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; + * The value of this signal means the number of error bytes in KEY3. + */ + +#define EFUSE_KEY3_ERR_NUM 0x00000007 +#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) +#define EFUSE_KEY3_ERR_NUM_V 0x00000007 +#define EFUSE_KEY3_ERR_NUM_S 24 + +/* EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; + * 0: Means no failure and that the data of KEY3 is reliable; 1: Means that + * programming KEY3 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY3_FAIL (BIT(27)) +#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) +#define EFUSE_KEY3_FAIL_V 0x00000001 +#define EFUSE_KEY3_FAIL_S 27 + +/* EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; + * The value of this signal means the number of error bytes in KEY4. + */ + +#define EFUSE_KEY4_ERR_NUM 0x00000007 +#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) +#define EFUSE_KEY4_ERR_NUM_V 0x00000007 +#define EFUSE_KEY4_ERR_NUM_S 28 + +/* EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; + * 0: Means no failure and that the data of KEY4 is reliable; 1: Means that + * programming KEY4 failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY4_FAIL (BIT(31)) +#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) +#define EFUSE_KEY4_FAIL_V 0x00000001 +#define EFUSE_KEY4_FAIL_S 31 + +/* EFUSE_RD_RS_ERR1_REG register + * Programming error record register 1 of BLOCK1-10. + */ + +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) + +/* EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; + * The value of this signal means the number of error bytes in KEY5. + */ + +#define EFUSE_KEY5_ERR_NUM 0x00000007 +#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) +#define EFUSE_KEY5_ERR_NUM_V 0x00000007 +#define EFUSE_KEY5_ERR_NUM_S 0 + +/* EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; + * 0: Means no failure and that the data of KEY5 is reliable; 1: Means that + * programming user data failed and the number of error bytes is over 5. + */ + +#define EFUSE_KEY5_FAIL (BIT(3)) +#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) +#define EFUSE_KEY5_FAIL_V 0x00000001 +#define EFUSE_KEY5_FAIL_S 3 + +/* EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; + * The value of this signal means the number of error bytes in BLOCK10. + */ + +#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 +#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) +#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007 +#define EFUSE_SYS_PART2_ERR_NUM_S 4 + +/* EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; + * 0: Means no failure and that the data of BLOCK10 is reliable; 1: Means + * that programming BLOCK10 data failed and the number of error bytes is + * over 5. + */ + +#define EFUSE_SYS_PART2_FAIL (BIT(7)) +#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) +#define EFUSE_SYS_PART2_FAIL_V 0x00000001 +#define EFUSE_SYS_PART2_FAIL_S 7 + +/* EFUSE_CLK_REG register + * eFuse clock configuration register. + */ + +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) + +/* EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; + * If set, forces eFuse SRAM into power-saving mode. + */ + +#define EFUSE_EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_EFUSE_MEM_FORCE_PD_M (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S) +#define EFUSE_EFUSE_MEM_FORCE_PD_V 0x00000001 +#define EFUSE_EFUSE_MEM_FORCE_PD_S 0 + +/* EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; + * If set, forces to activate clock signal of eFuse SRAM. + */ + +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001 +#define EFUSE_MEM_CLK_FORCE_ON_S 1 + +/* EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; + * If set, forces eFuse SRAM into working mode. + */ + +#define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_EFUSE_MEM_FORCE_PU_M (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S) +#define EFUSE_EFUSE_MEM_FORCE_PU_V 0x00000001 +#define EFUSE_EFUSE_MEM_FORCE_PU_S 2 + +/* EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; + * If set, forces to enable clock signal of eFuse memory. + */ + +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001 +#define EFUSE_CLK_EN_S 16 + +/* EFUSE_CONF_REG register + * eFuse operation mode configuration register. + */ + +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) + +/* EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; + * 0x5A5A: Operate programming command; 0x5AA5: Operate read command. + */ + +#define EFUSE_OP_CODE 0x0000FFFF +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000FFFF +#define EFUSE_OP_CODE_S 0 + +/* EFUSE_STATUS_REG register + * eFuse status register. + */ + +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) + +/* EFUSE_STATE : RO; bitpos: [3:0]; default: 0; + * Indicates the state of the eFuse state machine. + */ + +#define EFUSE_STATE 0x0000000F +#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) +#define EFUSE_STATE_V 0x0000000F +#define EFUSE_STATE_S 0 + +/* EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; + * The value of OTP_LOAD_SW. + */ + +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) +#define EFUSE_OTP_LOAD_SW_V 0x00000001 +#define EFUSE_OTP_LOAD_SW_S 4 + +/* EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; + * The value of OTP_VDDQ_C_SYNC2. + */ + +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001 +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 + +/* EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; + * The value of OTP_STROBE_SW. + */ + +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) +#define EFUSE_OTP_STROBE_SW_V 0x00000001 +#define EFUSE_OTP_STROBE_SW_S 6 + +/* EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; + * The value of OTP_CSB_SW. + */ + +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) +#define EFUSE_OTP_CSB_SW_V 0x00000001 +#define EFUSE_OTP_CSB_SW_S 7 + +/* EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; + * The value of OTP_PGENB_SW. + */ + +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) +#define EFUSE_OTP_PGENB_SW_V 0x00000001 +#define EFUSE_OTP_PGENB_SW_S 8 + +/* EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; + * The value of OTP_VDDQ_IS_SW. + */ + +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001 +#define EFUSE_OTP_VDDQ_IS_SW_S 9 + +/* EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0; + * Indicates the number of error bits during programming BLOCK0. + */ + +#define EFUSE_REPEAT_ERR_CNT 0x000000FF +#define EFUSE_REPEAT_ERR_CNT_M (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S) +#define EFUSE_REPEAT_ERR_CNT_V 0x000000FF +#define EFUSE_REPEAT_ERR_CNT_S 10 + +/* EFUSE_CMD_REG register + * eFuse command register. + */ + +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) + +/* EFUSE_READ_CMD : R/W; bitpos: [0]; default: 0; + * Set this bit to send read command. + */ + +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001 +#define EFUSE_READ_CMD_S 0 + +/* EFUSE_PGM_CMD : R/W; bitpos: [1]; default: 0; + * Set this bit to send programming command. + */ + +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001 +#define EFUSE_PGM_CMD_S 1 + +/* EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; + * The serial number of the block to be programmed. Value 0-10 corresponds + * to block number 0-10, respectively. + */ + +#define EFUSE_BLK_NUM 0x0000000F +#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) +#define EFUSE_BLK_NUM_V 0x0000000F +#define EFUSE_BLK_NUM_S 2 + +/* EFUSE_INT_RAW_REG register + * eFuse raw interrupt register. + */ + +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) + +/* EFUSE_READ_DONE_INT_RAW : RO; bitpos: [0]; default: 0; + * The raw bit signal for read_done interrupt. + */ + +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001 +#define EFUSE_READ_DONE_INT_RAW_S 0 + +/* EFUSE_PGM_DONE_INT_RAW : RO; bitpos: [1]; default: 0; + * The raw bit signal for pgm_done interrupt. + */ + +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001 +#define EFUSE_PGM_DONE_INT_RAW_S 1 + +/* EFUSE_INT_ST_REG register + * eFuse interrupt status register. + */ + +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) + +/* EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; + * The status signal for read_done interrupt. + */ + +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001 +#define EFUSE_READ_DONE_INT_ST_S 0 + +/* EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; + * The status signal for pgm_done interrupt. + */ + +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001 +#define EFUSE_PGM_DONE_INT_ST_S 1 + +/* EFUSE_INT_ENA_REG register + * eFuse interrupt enable register. + */ + +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) + +/* EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable signal for read_done interrupt. + */ + +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001 +#define EFUSE_READ_DONE_INT_ENA_S 0 + +/* EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable signal for pgm_done interrupt. + */ + +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001 +#define EFUSE_PGM_DONE_INT_ENA_S 1 + +/* EFUSE_INT_CLR_REG register + * eFuse interrupt clear register. + */ + +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) + +/* EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0; + * The clear signal for read_done interrupt. + */ + +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001 +#define EFUSE_READ_DONE_INT_CLR_S 0 + +/* EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0; + * The clear signal for pgm_done interrupt. + */ + +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001 +#define EFUSE_PGM_DONE_INT_CLR_S 1 + +/* EFUSE_DAC_CONF_REG register + * Controls the eFuse programming voltage. + */ + +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) + +/* EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28; + * Controls the division factor of the rising clock of the programming + * voltage. + */ + +#define EFUSE_DAC_CLK_DIV 0x000000FF +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000FF +#define EFUSE_DAC_CLK_DIV_S 0 + +/* EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; + * Don't care. + */ + +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001 +#define EFUSE_DAC_CLK_PAD_SEL_S 8 + +/* EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; + * Controls the rising period of the programming voltage. + */ + +#define EFUSE_DAC_NUM 0x000000FF +#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) +#define EFUSE_DAC_NUM_V 0x000000FF +#define EFUSE_DAC_NUM_S 9 + +/* EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; + * Reduces the power supply of the programming voltage. + */ + +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) +#define EFUSE_OE_CLR_V 0x00000001 +#define EFUSE_OE_CLR_S 17 + +/* EFUSE_RD_TIM_CONF_REG register + * Configures read timing parameters. + */ + +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) + +/* EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; + * Configures the hold time of read operation. + */ + +#define EFUSE_THR_A 0x000000FF +#define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) +#define EFUSE_THR_A_V 0x000000FF +#define EFUSE_THR_A_S 0 + +/* EFUSE_TRD : R/W; bitpos: [15:8]; default: 1; + * Configures the length of pulse of read operation. + */ + +#define EFUSE_TRD 0x000000FF +#define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) +#define EFUSE_TRD_V 0x000000FF +#define EFUSE_TRD_S 8 + +/* EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; + * Configures the setup time of read operation. + */ + +#define EFUSE_TSUR_A 0x000000FF +#define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) +#define EFUSE_TSUR_A_V 0x000000FF +#define EFUSE_TSUR_A_S 16 + +/* EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; + * Configures the initial read time of eFuse. + */ + +#define EFUSE_READ_INIT_NUM 0x000000FF +#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) +#define EFUSE_READ_INIT_NUM_V 0x000000FF +#define EFUSE_READ_INIT_NUM_S 24 + +/* EFUSE_WR_TIM_CONF0_REG register + * Configuration register 0 of eFuse programming timing parameters. + */ + +#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1f0) + +/* EFUSE_THP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the hold time of programming operation. + */ + +#define EFUSE_THP_A 0x000000FF +#define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) +#define EFUSE_THP_A_V 0x000000FF +#define EFUSE_THP_A_S 0 + +/* EFUSE_TPGM_INACTIVE : R/W; bitpos: [15:8]; default: 1; + * Configures the length of pulse during programming 0 to eFuse. + */ + +#define EFUSE_TPGM_INACTIVE 0x000000FF +#define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) +#define EFUSE_TPGM_INACTIVE_V 0x000000FF +#define EFUSE_TPGM_INACTIVE_S 8 + +/* EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200; + * Configures the length of pulse during programming 1 to eFuse. + */ + +#define EFUSE_TPGM 0x0000FFFF +#define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) +#define EFUSE_TPGM_V 0x0000FFFF +#define EFUSE_TPGM_S 16 + +/* EFUSE_WR_TIM_CONF1_REG register + * Configuration register 1 of eFuse programming timing parameters. + */ + +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f4) + +/* EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; + * Configures the setup time of programming operation. + */ + +#define EFUSE_TSUP_A 0x000000FF +#define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) +#define EFUSE_TSUP_A_V 0x000000FF +#define EFUSE_TSUP_A_S 0 + +/* EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368; + * Configures the power up time for VDDQ. + */ + +#define EFUSE_PWR_ON_NUM 0x0000FFFF +#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) +#define EFUSE_PWR_ON_NUM_V 0x0000FFFF +#define EFUSE_PWR_ON_NUM_S 8 + +/* EFUSE_WR_TIM_CONF2_REG register + * Configuration register 2 of eFuse programming timing parameters. + */ + +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f8) + +/* EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; + * Configures the power outage time for VDDQ. + */ + +#define EFUSE_PWR_OFF_NUM 0x0000FFFF +#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) +#define EFUSE_PWR_OFF_NUM_V 0x0000FFFF +#define EFUSE_PWR_OFF_NUM_S 0 + +/* EFUSE_DATE_REG register + * eFuse version register. + */ + +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) + +/* EFUSE_EFUSE_DATE : R/W; bitpos: [31:0]; default: 419959040; + * Stores eFuse version. + */ + +#define EFUSE_EFUSE_DATE 0xFFFFFFFF +#define EFUSE_EFUSE_DATE_M (EFUSE_EFUSE_DATE_V << EFUSE_EFUSE_DATE_S) +#define EFUSE_EFUSE_DATE_V 0xFFFFFFFF +#define EFUSE_EFUSE_DATE_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_EFUSE_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_gpio.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_gpio.h new file mode 100644 index 0000000000000..98ae519502492 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_gpio.h @@ -0,0 +1,5314 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_GPIO_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-preprocessor Definitions + ****************************************************************************/ + +#define GPIO_REG(io_num) (GPIO_PIN0_REG + ((io_num) * 0x4)) + +#define GPIO_PIN_INT_ENA 0x0000001f +#define GPIO_PIN_INT_ENA_M ((GPIO_PIN_INT_ENA_V)<<(GPIO_PIN_INT_ENA_S)) +#define GPIO_PIN_INT_ENA_V 0x0000001f +#define GPIO_PIN_INT_ENA_S 13 + +#define GPIO_PIN_CONFIG 0x00000003 +#define GPIO_PIN_CONFIG_M ((GPIO_PIN_CONFIG_V)<<(GPIO_PIN_CONFIG_S)) +#define GPIO_PIN_CONFIG_V 0x00000003 +#define GPIO_PIN_CONFIG_S 11 + +#define GPIO_PIN_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN_WAKEUP_ENABLE_S 10 + +#define GPIO_PIN_INT_TYPE 0x00000007 +#define GPIO_PIN_INT_TYPE_M ((GPIO_PIN_INT_TYPE_V)<<(GPIO_PIN_INT_TYPE_S)) +#define GPIO_PIN_INT_TYPE_V 0x00000007 +#define GPIO_PIN_INT_TYPE_S 7 + +#define GPIO_PIN_CONFIG_MSB 12 +#define GPIO_PIN_CONFIG_LSB 11 +#define GPIO_PIN_CONFIG_MASK 0x00001800 +#define GPIO_PIN_CONFIG_GET(x) (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB) +#define GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK) + +#define GPIO_WAKEUP_ENABLE 1 +#define GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE) +#define GPIO_PIN_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB) +#define GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK) + +#define GPIO_PIN_INT_TYPE_MASK 0x380 +#define GPIO_PIN_INT_TYPE_MSB 9 +#define GPIO_PIN_INT_TYPE_LSB 7 +#define GPIO_PIN_INT_TYPE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB) +#define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK) + +#define GPIO_PIN_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN_SYNC1_BYPASS_M ((GPIO_PIN0_SYNC1_BYPASS_V)<<(GPIO_PIN0_SYNC1_BYPASS_S)) +#define GPIO_PIN_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN_SYNC1_BYPASS_S 3 + +#define GPIO_PIN_PAD_DRIVER (BIT(2)) +#define GPIO_PIN_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN_PAD_DRIVER_V 0x1 +#define GPIO_PIN_PAD_DRIVER_S 2 + +#define GPIO_PIN_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN_SYNC2_BYPASS_M ((GPIO_PIN0_SYNC2_BYPASS_V)<<(GPIO_PIN0_SYNC2_BYPASS_S)) +#define GPIO_PIN_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN_SYNC2_BYPASS_S 0 + +#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0) + +/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define GPIO_BT_SEL 0xffffffff +#define GPIO_BT_SEL_M ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S)) +#define GPIO_BT_SEL_V 0xffffffff +#define GPIO_BT_SEL_S 0 + +#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) + +/* GPIO_OUT_DATA : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ + +#define GPIO_OUT_DATA 0x03ffffff +#define GPIO_OUT_DATA_M ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S)) +#define GPIO_OUT_DATA_V 0x3ffffff +#define GPIO_OUT_DATA_S 0 + +#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) + +/* GPIO_OUT_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */ + +#define GPIO_OUT_W1TS 0x03ffffff +#define GPIO_OUT_W1TS_M ((GPIO_OUT_W1TS_V)<<(GPIO_OUT_W1TS_S)) +#define GPIO_OUT_W1TS_V 0x3ffffff +#define GPIO_OUT_W1TS_S 0 + +#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc) + +/* GPIO_OUT_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */ + +#define GPIO_OUT_W1TC 0x03ffffff +#define GPIO_OUT_W1TC_M ((GPIO_OUT_W1TC_V)<<(GPIO_OUT_W1TC_S)) +#define GPIO_OUT_W1TC_V 0x3ffffff +#define GPIO_OUT_W1TC_S 0 + +#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1c) + +/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ + +#define GPIO_SDIO_SEL 0x000000ff +#define GPIO_SDIO_SEL_M ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S)) +#define GPIO_SDIO_SEL_V 0xff +#define GPIO_SDIO_SEL_S 0 + +#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) + +/* GPIO_ENABLE_DATA : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ + +#define GPIO_ENABLE_DATA 0x03ffffff +#define GPIO_ENABLE_DATA_M ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S)) +#define GPIO_ENABLE_DATA_V 0x3ffffff +#define GPIO_ENABLE_DATA_S 0 + +#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) + +/* GPIO_ENABLE_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */ + +#define GPIO_ENABLE_W1TS 0x03ffffff +#define GPIO_ENABLE_W1TS_M ((GPIO_ENABLE_W1TS_V)<<(GPIO_ENABLE_W1TS_S)) +#define GPIO_ENABLE_W1TS_V 0x3ffffff +#define GPIO_ENABLE_W1TS_S 0 + +#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) + +/* GPIO_ENABLE_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */ + +#define GPIO_ENABLE_W1TC 0x03ffffff +#define GPIO_ENABLE_W1TC_M ((GPIO_ENABLE_W1TC_V)<<(GPIO_ENABLE_W1TC_S)) +#define GPIO_ENABLE_W1TC_V 0x3ffffff +#define GPIO_ENABLE_W1TC_S 0 + +#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38) + +/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default: ; */ + +#define GPIO_STRAPPING 0x0000ffff +#define GPIO_STRAPPING_M ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S)) +#define GPIO_STRAPPING_V 0xffff +#define GPIO_STRAPPING_S 0 + +#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c) + +/* GPIO_IN_DATA : RO ;bitpos:[25:0] ;default: ; */ + +#define GPIO_IN_DATA 0x03ffffff +#define GPIO_IN_DATA_M ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S)) +#define GPIO_IN_DATA_V 0x3ffffff +#define GPIO_IN_DATA_S 0 + +#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) + +/* GPIO_STATUS_INT : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ + +#define GPIO_STATUS_INT 0x03ffffff +#define GPIO_STATUS_INT_M ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S)) +#define GPIO_STATUS_INT_V 0x3ffffff +#define GPIO_STATUS_INT_S 0 + +#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) + +/* GPIO_STATUS_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */ + +#define GPIO_STATUS_W1TS 0x03ffffff +#define GPIO_STATUS_W1TS_M ((GPIO_STATUS_W1TS_V)<<(GPIO_STATUS_W1TS_S)) +#define GPIO_STATUS_W1TS_V 0x3ffffff +#define GPIO_STATUS_W1TS_S 0 + +#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c) + +/* GPIO_STATUS_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */ + +#define GPIO_STATUS_W1TC 0x03ffffff +#define GPIO_STATUS_W1TC_M ((GPIO_STATUS_W1TC_V)<<(GPIO_STATUS_W1TC_S)) +#define GPIO_STATUS_W1TC_V 0x3ffffff +#define GPIO_STATUS_W1TC_S 0 + +#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5c) + +/* GPIO_PROCPU_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */ + +#define GPIO_PROCPU_INT 0x03ffffff +#define GPIO_PROCPU_INT_M ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S)) +#define GPIO_PROCPU_INT_V 0x3ffffff +#define GPIO_PROCPU_INT_S 0 + +#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) + +/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */ + +#define GPIO_PROCPU_NMI_INT 0x03ffffff +#define GPIO_PROCPU_NMI_INT_M ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S)) +#define GPIO_PROCPU_NMI_INT_V 0x3ffffff +#define GPIO_PROCPU_NMI_INT_S 0 + +#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) + +/* GPIO_SDIO_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */ + +#define GPIO_SDIO_INT 0x03ffffff +#define GPIO_SDIO_INT_M ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S)) +#define GPIO_SDIO_INT_V 0x3ffffff +#define GPIO_SDIO_INT_S 0 + +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) + +/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN0_INT_ENA 0x0000001f +#define GPIO_PIN0_INT_ENA_M ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S)) +#define GPIO_PIN0_INT_ENA_V 0x1f +#define GPIO_PIN0_INT_ENA_S 13 + +/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN0_CONFIG 0x00000003 +#define GPIO_PIN0_CONFIG_M ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S)) +#define GPIO_PIN0_CONFIG_V 0x3 +#define GPIO_PIN0_CONFIG_S 11 + +/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN0_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN0_INT_TYPE 0x00000007 +#define GPIO_PIN0_INT_TYPE_M ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S)) +#define GPIO_PIN0_INT_TYPE_V 0x7 +#define GPIO_PIN0_INT_TYPE_S 7 + +/* GPIO_PIN0_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN0_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN0_SYNC1_BYPASS_M ((GPIO_PIN0_SYNC1_BYPASS_V)<<(GPIO_PIN0_SYNC1_BYPASS_S)) +#define GPIO_PIN0_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN0_SYNC1_BYPASS_S 3 + +/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN_PAD_DRIVER_S 2 + +#define GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_V 0x1 +#define GPIO_PIN0_PAD_DRIVER_S 2 + +/* GPIO_PIN0_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN0_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN0_SYNC2_BYPASS_M ((GPIO_PIN0_SYNC2_BYPASS_V)<<(GPIO_PIN0_SYNC2_BYPASS_S)) +#define GPIO_PIN0_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN0_SYNC2_BYPASS_S 0 + +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78) + +/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN1_INT_ENA 0x0000001f +#define GPIO_PIN1_INT_ENA_M ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S)) +#define GPIO_PIN1_INT_ENA_V 0x1f +#define GPIO_PIN1_INT_ENA_S 13 + +/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN1_CONFIG 0x00000003 +#define GPIO_PIN1_CONFIG_M ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S)) +#define GPIO_PIN1_CONFIG_V 0x3 +#define GPIO_PIN1_CONFIG_S 11 + +/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN1_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN1_INT_TYPE 0x00000007 +#define GPIO_PIN1_INT_TYPE_M ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S)) +#define GPIO_PIN1_INT_TYPE_V 0x7 +#define GPIO_PIN1_INT_TYPE_S 7 + +/* GPIO_PIN1_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN1_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN1_SYNC1_BYPASS_M ((GPIO_PIN1_SYNC1_BYPASS_V)<<(GPIO_PIN1_SYNC1_BYPASS_S)) +#define GPIO_PIN1_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN1_SYNC1_BYPASS_S 3 + +/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_V 0x1 +#define GPIO_PIN1_PAD_DRIVER_S 2 + +/* GPIO_PIN1_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN1_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN1_SYNC2_BYPASS_M ((GPIO_PIN1_SYNC2_BYPASS_V)<<(GPIO_PIN1_SYNC2_BYPASS_S)) +#define GPIO_PIN1_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN1_SYNC2_BYPASS_S 0 + +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c) + +/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN2_INT_ENA 0x0000001f +#define GPIO_PIN2_INT_ENA_M ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S)) +#define GPIO_PIN2_INT_ENA_V 0x1f +#define GPIO_PIN2_INT_ENA_S 13 + +/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN2_CONFIG 0x00000003 +#define GPIO_PIN2_CONFIG_M ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S)) +#define GPIO_PIN2_CONFIG_V 0x3 +#define GPIO_PIN2_CONFIG_S 11 + +/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN2_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN2_INT_TYPE 0x00000007 +#define GPIO_PIN2_INT_TYPE_M ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S)) +#define GPIO_PIN2_INT_TYPE_V 0x7 +#define GPIO_PIN2_INT_TYPE_S 7 + +/* GPIO_PIN2_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN2_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN2_SYNC1_BYPASS_M ((GPIO_PIN2_SYNC1_BYPASS_V)<<(GPIO_PIN2_SYNC1_BYPASS_S)) +#define GPIO_PIN2_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN2_SYNC1_BYPASS_S 3 + +/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_V 0x1 +#define GPIO_PIN2_PAD_DRIVER_S 2 + +/* GPIO_PIN2_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN2_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN2_SYNC2_BYPASS_M ((GPIO_PIN2_SYNC2_BYPASS_V)<<(GPIO_PIN2_SYNC2_BYPASS_S)) +#define GPIO_PIN2_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN2_SYNC2_BYPASS_S 0 + +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80) + +/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN3_INT_ENA 0x0000001f +#define GPIO_PIN3_INT_ENA_M ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S)) +#define GPIO_PIN3_INT_ENA_V 0x1f +#define GPIO_PIN3_INT_ENA_S 13 + +/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN3_CONFIG 0x00000003 +#define GPIO_PIN3_CONFIG_M ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S)) +#define GPIO_PIN3_CONFIG_V 0x3 +#define GPIO_PIN3_CONFIG_S 11 + +/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN3_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN3_INT_TYPE 0x00000007 +#define GPIO_PIN3_INT_TYPE_M ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S)) +#define GPIO_PIN3_INT_TYPE_V 0x7 +#define GPIO_PIN3_INT_TYPE_S 7 + +/* GPIO_PIN3_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN3_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN3_SYNC1_BYPASS_M ((GPIO_PIN3_SYNC1_BYPASS_V)<<(GPIO_PIN3_SYNC1_BYPASS_S)) +#define GPIO_PIN3_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN3_SYNC1_BYPASS_S 3 + +/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_V 0x1 +#define GPIO_PIN3_PAD_DRIVER_S 2 + +/* GPIO_PIN3_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN3_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN3_SYNC2_BYPASS_M ((GPIO_PIN3_SYNC2_BYPASS_V)<<(GPIO_PIN3_SYNC2_BYPASS_S)) +#define GPIO_PIN3_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN3_SYNC2_BYPASS_S 0 + +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84) + +/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN4_INT_ENA 0x0000001f +#define GPIO_PIN4_INT_ENA_M ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S)) +#define GPIO_PIN4_INT_ENA_V 0x1f +#define GPIO_PIN4_INT_ENA_S 13 + +/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN4_CONFIG 0x00000003 +#define GPIO_PIN4_CONFIG_M ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S)) +#define GPIO_PIN4_CONFIG_V 0x3 +#define GPIO_PIN4_CONFIG_S 11 + +/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN4_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN4_INT_TYPE 0x00000007 +#define GPIO_PIN4_INT_TYPE_M ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S)) +#define GPIO_PIN4_INT_TYPE_V 0x7 +#define GPIO_PIN4_INT_TYPE_S 7 + +/* GPIO_PIN4_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN4_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN4_SYNC1_BYPASS_M ((GPIO_PIN4_SYNC1_BYPASS_V)<<(GPIO_PIN4_SYNC1_BYPASS_S)) +#define GPIO_PIN4_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN4_SYNC1_BYPASS_S 3 + +/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_V 0x1 +#define GPIO_PIN4_PAD_DRIVER_S 2 + +/* GPIO_PIN4_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN4_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN4_SYNC2_BYPASS_M ((GPIO_PIN4_SYNC2_BYPASS_V)<<(GPIO_PIN4_SYNC2_BYPASS_S)) +#define GPIO_PIN4_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN4_SYNC2_BYPASS_S 0 + +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88) + +/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN5_INT_ENA 0x0000001f +#define GPIO_PIN5_INT_ENA_M ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S)) +#define GPIO_PIN5_INT_ENA_V 0x1f +#define GPIO_PIN5_INT_ENA_S 13 + +/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN5_CONFIG 0x00000003 +#define GPIO_PIN5_CONFIG_M ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S)) +#define GPIO_PIN5_CONFIG_V 0x3 +#define GPIO_PIN5_CONFIG_S 11 + +/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN5_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN5_INT_TYPE 0x00000007 +#define GPIO_PIN5_INT_TYPE_M ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S)) +#define GPIO_PIN5_INT_TYPE_V 0x7 +#define GPIO_PIN5_INT_TYPE_S 7 + +/* GPIO_PIN5_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN5_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN5_SYNC1_BYPASS_M ((GPIO_PIN5_SYNC1_BYPASS_V)<<(GPIO_PIN5_SYNC1_BYPASS_S)) +#define GPIO_PIN5_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN5_SYNC1_BYPASS_S 3 + +/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_V 0x1 +#define GPIO_PIN5_PAD_DRIVER_S 2 + +/* GPIO_PIN5_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN5_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN5_SYNC2_BYPASS_M ((GPIO_PIN5_SYNC2_BYPASS_V)<<(GPIO_PIN5_SYNC2_BYPASS_S)) +#define GPIO_PIN5_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN5_SYNC2_BYPASS_S 0 + +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c) + +/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN6_INT_ENA 0x0000001f +#define GPIO_PIN6_INT_ENA_M ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S)) +#define GPIO_PIN6_INT_ENA_V 0x1f +#define GPIO_PIN6_INT_ENA_S 13 + +/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN6_CONFIG 0x00000003 +#define GPIO_PIN6_CONFIG_M ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S)) +#define GPIO_PIN6_CONFIG_V 0x3 +#define GPIO_PIN6_CONFIG_S 11 + +/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN6_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN6_INT_TYPE 0x00000007 +#define GPIO_PIN6_INT_TYPE_M ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S)) +#define GPIO_PIN6_INT_TYPE_V 0x7 +#define GPIO_PIN6_INT_TYPE_S 7 + +/* GPIO_PIN6_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN6_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN6_SYNC1_BYPASS_M ((GPIO_PIN6_SYNC1_BYPASS_V)<<(GPIO_PIN6_SYNC1_BYPASS_S)) +#define GPIO_PIN6_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN6_SYNC1_BYPASS_S 3 + +/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_V 0x1 +#define GPIO_PIN6_PAD_DRIVER_S 2 + +/* GPIO_PIN6_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN6_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN6_SYNC2_BYPASS_M ((GPIO_PIN6_SYNC2_BYPASS_V)<<(GPIO_PIN6_SYNC2_BYPASS_S)) +#define GPIO_PIN6_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN6_SYNC2_BYPASS_S 0 + +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90) + +/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN7_INT_ENA 0x0000001f +#define GPIO_PIN7_INT_ENA_M ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S)) +#define GPIO_PIN7_INT_ENA_V 0x1f +#define GPIO_PIN7_INT_ENA_S 13 + +/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN7_CONFIG 0x00000003 +#define GPIO_PIN7_CONFIG_M ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S)) +#define GPIO_PIN7_CONFIG_V 0x3 +#define GPIO_PIN7_CONFIG_S 11 + +/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN7_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN7_INT_TYPE 0x00000007 +#define GPIO_PIN7_INT_TYPE_M ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S)) +#define GPIO_PIN7_INT_TYPE_V 0x7 +#define GPIO_PIN7_INT_TYPE_S 7 + +/* GPIO_PIN7_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN7_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN7_SYNC1_BYPASS_M ((GPIO_PIN7_SYNC1_BYPASS_V)<<(GPIO_PIN7_SYNC1_BYPASS_S)) +#define GPIO_PIN7_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN7_SYNC1_BYPASS_S 3 + +/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_V 0x1 +#define GPIO_PIN7_PAD_DRIVER_S 2 + +/* GPIO_PIN7_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN7_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN7_SYNC2_BYPASS_M ((GPIO_PIN7_SYNC2_BYPASS_V)<<(GPIO_PIN7_SYNC2_BYPASS_S)) +#define GPIO_PIN7_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN7_SYNC2_BYPASS_S 0 + +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94) + +/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN8_INT_ENA 0x0000001f +#define GPIO_PIN8_INT_ENA_M ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S)) +#define GPIO_PIN8_INT_ENA_V 0x1f +#define GPIO_PIN8_INT_ENA_S 13 + +/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN8_CONFIG 0x00000003 +#define GPIO_PIN8_CONFIG_M ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S)) +#define GPIO_PIN8_CONFIG_V 0x3 +#define GPIO_PIN8_CONFIG_S 11 + +/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN8_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN8_INT_TYPE 0x00000007 +#define GPIO_PIN8_INT_TYPE_M ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S)) +#define GPIO_PIN8_INT_TYPE_V 0x7 +#define GPIO_PIN8_INT_TYPE_S 7 + +/* GPIO_PIN8_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN8_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN8_SYNC1_BYPASS_M ((GPIO_PIN8_SYNC1_BYPASS_V)<<(GPIO_PIN8_SYNC1_BYPASS_S)) +#define GPIO_PIN8_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN8_SYNC1_BYPASS_S 3 + +/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_V 0x1 +#define GPIO_PIN8_PAD_DRIVER_S 2 + +/* GPIO_PIN8_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN8_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN8_SYNC2_BYPASS_M ((GPIO_PIN8_SYNC2_BYPASS_V)<<(GPIO_PIN8_SYNC2_BYPASS_S)) +#define GPIO_PIN8_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN8_SYNC2_BYPASS_S 0 + +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98) + +/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN9_INT_ENA 0x0000001f +#define GPIO_PIN9_INT_ENA_M ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S)) +#define GPIO_PIN9_INT_ENA_V 0x1f +#define GPIO_PIN9_INT_ENA_S 13 + +/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN9_CONFIG 0x00000003 +#define GPIO_PIN9_CONFIG_M ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S)) +#define GPIO_PIN9_CONFIG_V 0x3 +#define GPIO_PIN9_CONFIG_S 11 + +/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN9_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN9_INT_TYPE 0x00000007 +#define GPIO_PIN9_INT_TYPE_M ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S)) +#define GPIO_PIN9_INT_TYPE_V 0x7 +#define GPIO_PIN9_INT_TYPE_S 7 + +/* GPIO_PIN9_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN9_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN9_SYNC1_BYPASS_M ((GPIO_PIN9_SYNC1_BYPASS_V)<<(GPIO_PIN9_SYNC1_BYPASS_S)) +#define GPIO_PIN9_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN9_SYNC1_BYPASS_S 3 + +/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_V 0x1 +#define GPIO_PIN9_PAD_DRIVER_S 2 + +/* GPIO_PIN9_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN9_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN9_SYNC2_BYPASS_M ((GPIO_PIN9_SYNC2_BYPASS_V)<<(GPIO_PIN9_SYNC2_BYPASS_S)) +#define GPIO_PIN9_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN9_SYNC2_BYPASS_S 0 + +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c) + +/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN10_INT_ENA 0x0000001f +#define GPIO_PIN10_INT_ENA_M ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S)) +#define GPIO_PIN10_INT_ENA_V 0x1f +#define GPIO_PIN10_INT_ENA_S 13 + +/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN10_CONFIG 0x00000003 +#define GPIO_PIN10_CONFIG_M ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S)) +#define GPIO_PIN10_CONFIG_V 0x3 +#define GPIO_PIN10_CONFIG_S 11 + +/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN10_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN10_INT_TYPE 0x00000007 +#define GPIO_PIN10_INT_TYPE_M ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S)) +#define GPIO_PIN10_INT_TYPE_V 0x7 +#define GPIO_PIN10_INT_TYPE_S 7 + +/* GPIO_PIN10_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN10_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN10_SYNC1_BYPASS_M ((GPIO_PIN10_SYNC1_BYPASS_V)<<(GPIO_PIN10_SYNC1_BYPASS_S)) +#define GPIO_PIN10_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN10_SYNC1_BYPASS_S 3 + +/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_V 0x1 +#define GPIO_PIN10_PAD_DRIVER_S 2 + +/* GPIO_PIN10_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN10_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN10_SYNC2_BYPASS_M ((GPIO_PIN10_SYNC2_BYPASS_V)<<(GPIO_PIN10_SYNC2_BYPASS_S)) +#define GPIO_PIN10_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN10_SYNC2_BYPASS_S 0 + +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0) + +/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN11_INT_ENA 0x0000001f +#define GPIO_PIN11_INT_ENA_M ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S)) +#define GPIO_PIN11_INT_ENA_V 0x1f +#define GPIO_PIN11_INT_ENA_S 13 + +/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN11_CONFIG 0x00000003 +#define GPIO_PIN11_CONFIG_M ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S)) +#define GPIO_PIN11_CONFIG_V 0x3 +#define GPIO_PIN11_CONFIG_S 11 + +/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN11_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN11_INT_TYPE 0x00000007 +#define GPIO_PIN11_INT_TYPE_M ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S)) +#define GPIO_PIN11_INT_TYPE_V 0x7 +#define GPIO_PIN11_INT_TYPE_S 7 + +/* GPIO_PIN11_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN11_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN11_SYNC1_BYPASS_M ((GPIO_PIN11_SYNC1_BYPASS_V)<<(GPIO_PIN11_SYNC1_BYPASS_S)) +#define GPIO_PIN11_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN11_SYNC1_BYPASS_S 3 + +/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_V 0x1 +#define GPIO_PIN11_PAD_DRIVER_S 2 + +/* GPIO_PIN11_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN11_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN11_SYNC2_BYPASS_M ((GPIO_PIN11_SYNC2_BYPASS_V)<<(GPIO_PIN11_SYNC2_BYPASS_S)) +#define GPIO_PIN11_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN11_SYNC2_BYPASS_S 0 + +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4) + +/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN12_INT_ENA 0x0000001f +#define GPIO_PIN12_INT_ENA_M ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S)) +#define GPIO_PIN12_INT_ENA_V 0x1f +#define GPIO_PIN12_INT_ENA_S 13 + +/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN12_CONFIG 0x00000003 +#define GPIO_PIN12_CONFIG_M ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S)) +#define GPIO_PIN12_CONFIG_V 0x3 +#define GPIO_PIN12_CONFIG_S 11 + +/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN12_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN12_INT_TYPE 0x00000007 +#define GPIO_PIN12_INT_TYPE_M ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S)) +#define GPIO_PIN12_INT_TYPE_V 0x7 +#define GPIO_PIN12_INT_TYPE_S 7 + +/* GPIO_PIN12_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN12_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN12_SYNC1_BYPASS_M ((GPIO_PIN12_SYNC1_BYPASS_V)<<(GPIO_PIN12_SYNC1_BYPASS_S)) +#define GPIO_PIN12_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN12_SYNC1_BYPASS_S 3 + +/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_V 0x1 +#define GPIO_PIN12_PAD_DRIVER_S 2 + +/* GPIO_PIN12_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN12_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN12_SYNC2_BYPASS_M ((GPIO_PIN12_SYNC2_BYPASS_V)<<(GPIO_PIN12_SYNC2_BYPASS_S)) +#define GPIO_PIN12_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN12_SYNC2_BYPASS_S 0 + +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8) + +/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN13_INT_ENA 0x0000001f +#define GPIO_PIN13_INT_ENA_M ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S)) +#define GPIO_PIN13_INT_ENA_V 0x1f +#define GPIO_PIN13_INT_ENA_S 13 + +/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN13_CONFIG 0x00000003 +#define GPIO_PIN13_CONFIG_M ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S)) +#define GPIO_PIN13_CONFIG_V 0x3 +#define GPIO_PIN13_CONFIG_S 11 + +/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN13_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN13_INT_TYPE 0x00000007 +#define GPIO_PIN13_INT_TYPE_M ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S)) +#define GPIO_PIN13_INT_TYPE_V 0x7 +#define GPIO_PIN13_INT_TYPE_S 7 + +/* GPIO_PIN13_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN13_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN13_SYNC1_BYPASS_M ((GPIO_PIN13_SYNC1_BYPASS_V)<<(GPIO_PIN13_SYNC1_BYPASS_S)) +#define GPIO_PIN13_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN13_SYNC1_BYPASS_S 3 + +/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_V 0x1 +#define GPIO_PIN13_PAD_DRIVER_S 2 + +/* GPIO_PIN13_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN13_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN13_SYNC2_BYPASS_M ((GPIO_PIN13_SYNC2_BYPASS_V)<<(GPIO_PIN13_SYNC2_BYPASS_S)) +#define GPIO_PIN13_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN13_SYNC2_BYPASS_S 0 + +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac) + +/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN14_INT_ENA 0x0000001f +#define GPIO_PIN14_INT_ENA_M ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S)) +#define GPIO_PIN14_INT_ENA_V 0x1f +#define GPIO_PIN14_INT_ENA_S 13 + +/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN14_CONFIG 0x00000003 +#define GPIO_PIN14_CONFIG_M ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S)) +#define GPIO_PIN14_CONFIG_V 0x3 +#define GPIO_PIN14_CONFIG_S 11 + +/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN14_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN14_INT_TYPE 0x00000007 +#define GPIO_PIN14_INT_TYPE_M ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S)) +#define GPIO_PIN14_INT_TYPE_V 0x7 +#define GPIO_PIN14_INT_TYPE_S 7 + +/* GPIO_PIN14_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN14_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN14_SYNC1_BYPASS_M ((GPIO_PIN14_SYNC1_BYPASS_V)<<(GPIO_PIN14_SYNC1_BYPASS_S)) +#define GPIO_PIN14_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN14_SYNC1_BYPASS_S 3 + +/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_V 0x1 +#define GPIO_PIN14_PAD_DRIVER_S 2 + +/* GPIO_PIN14_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN14_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN14_SYNC2_BYPASS_M ((GPIO_PIN14_SYNC2_BYPASS_V)<<(GPIO_PIN14_SYNC2_BYPASS_S)) +#define GPIO_PIN14_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN14_SYNC2_BYPASS_S 0 + +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0) + +/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN15_INT_ENA 0x0000001f +#define GPIO_PIN15_INT_ENA_M ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S)) +#define GPIO_PIN15_INT_ENA_V 0x1f +#define GPIO_PIN15_INT_ENA_S 13 + +/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN15_CONFIG 0x00000003 +#define GPIO_PIN15_CONFIG_M ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S)) +#define GPIO_PIN15_CONFIG_V 0x3 +#define GPIO_PIN15_CONFIG_S 11 + +/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN15_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN15_INT_TYPE 0x00000007 +#define GPIO_PIN15_INT_TYPE_M ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S)) +#define GPIO_PIN15_INT_TYPE_V 0x7 +#define GPIO_PIN15_INT_TYPE_S 7 + +/* GPIO_PIN15_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN15_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN15_SYNC1_BYPASS_M ((GPIO_PIN15_SYNC1_BYPASS_V)<<(GPIO_PIN15_SYNC1_BYPASS_S)) +#define GPIO_PIN15_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN15_SYNC1_BYPASS_S 3 + +/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_V 0x1 +#define GPIO_PIN15_PAD_DRIVER_S 2 + +/* GPIO_PIN15_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN15_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN15_SYNC2_BYPASS_M ((GPIO_PIN15_SYNC2_BYPASS_V)<<(GPIO_PIN15_SYNC2_BYPASS_S)) +#define GPIO_PIN15_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN15_SYNC2_BYPASS_S 0 + +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4) + +/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN16_INT_ENA 0x0000001f +#define GPIO_PIN16_INT_ENA_M ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S)) +#define GPIO_PIN16_INT_ENA_V 0x1f +#define GPIO_PIN16_INT_ENA_S 13 + +/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN16_CONFIG 0x00000003 +#define GPIO_PIN16_CONFIG_M ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S)) +#define GPIO_PIN16_CONFIG_V 0x3 +#define GPIO_PIN16_CONFIG_S 11 + +/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN16_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN16_INT_TYPE 0x00000007 +#define GPIO_PIN16_INT_TYPE_M ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S)) +#define GPIO_PIN16_INT_TYPE_V 0x7 +#define GPIO_PIN16_INT_TYPE_S 7 + +/* GPIO_PIN16_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN16_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN16_SYNC1_BYPASS_M ((GPIO_PIN16_SYNC1_BYPASS_V)<<(GPIO_PIN16_SYNC1_BYPASS_S)) +#define GPIO_PIN16_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN16_SYNC1_BYPASS_S 3 + +/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_V 0x1 +#define GPIO_PIN16_PAD_DRIVER_S 2 + +/* GPIO_PIN16_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN16_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN16_SYNC2_BYPASS_M ((GPIO_PIN16_SYNC2_BYPASS_V)<<(GPIO_PIN16_SYNC2_BYPASS_S)) +#define GPIO_PIN16_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN16_SYNC2_BYPASS_S 0 + +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8) + +/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN17_INT_ENA 0x0000001f +#define GPIO_PIN17_INT_ENA_M ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S)) +#define GPIO_PIN17_INT_ENA_V 0x1f +#define GPIO_PIN17_INT_ENA_S 13 + +/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN17_CONFIG 0x00000003 +#define GPIO_PIN17_CONFIG_M ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S)) +#define GPIO_PIN17_CONFIG_V 0x3 +#define GPIO_PIN17_CONFIG_S 11 + +/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN17_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN17_INT_TYPE 0x00000007 +#define GPIO_PIN17_INT_TYPE_M ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S)) +#define GPIO_PIN17_INT_TYPE_V 0x7 +#define GPIO_PIN17_INT_TYPE_S 7 + +/* GPIO_PIN17_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN17_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN17_SYNC1_BYPASS_M ((GPIO_PIN17_SYNC1_BYPASS_V)<<(GPIO_PIN17_SYNC1_BYPASS_S)) +#define GPIO_PIN17_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN17_SYNC1_BYPASS_S 3 + +/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_V 0x1 +#define GPIO_PIN17_PAD_DRIVER_S 2 + +/* GPIO_PIN17_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN17_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN17_SYNC2_BYPASS_M ((GPIO_PIN17_SYNC2_BYPASS_V)<<(GPIO_PIN17_SYNC2_BYPASS_S)) +#define GPIO_PIN17_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN17_SYNC2_BYPASS_S 0 + +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc) + +/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN18_INT_ENA 0x0000001f +#define GPIO_PIN18_INT_ENA_M ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S)) +#define GPIO_PIN18_INT_ENA_V 0x1f +#define GPIO_PIN18_INT_ENA_S 13 + +/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN18_CONFIG 0x00000003 +#define GPIO_PIN18_CONFIG_M ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S)) +#define GPIO_PIN18_CONFIG_V 0x3 +#define GPIO_PIN18_CONFIG_S 11 + +/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN18_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN18_INT_TYPE 0x00000007 +#define GPIO_PIN18_INT_TYPE_M ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S)) +#define GPIO_PIN18_INT_TYPE_V 0x7 +#define GPIO_PIN18_INT_TYPE_S 7 + +/* GPIO_PIN18_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN18_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN18_SYNC1_BYPASS_M ((GPIO_PIN18_SYNC1_BYPASS_V)<<(GPIO_PIN18_SYNC1_BYPASS_S)) +#define GPIO_PIN18_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN18_SYNC1_BYPASS_S 3 + +/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_V 0x1 +#define GPIO_PIN18_PAD_DRIVER_S 2 + +/* GPIO_PIN18_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN18_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN18_SYNC2_BYPASS_M ((GPIO_PIN18_SYNC2_BYPASS_V)<<(GPIO_PIN18_SYNC2_BYPASS_S)) +#define GPIO_PIN18_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN18_SYNC2_BYPASS_S 0 + +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0) + +/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN19_INT_ENA 0x0000001f +#define GPIO_PIN19_INT_ENA_M ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S)) +#define GPIO_PIN19_INT_ENA_V 0x1f +#define GPIO_PIN19_INT_ENA_S 13 + +/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN19_CONFIG 0x00000003 +#define GPIO_PIN19_CONFIG_M ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S)) +#define GPIO_PIN19_CONFIG_V 0x3 +#define GPIO_PIN19_CONFIG_S 11 + +/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN19_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN19_INT_TYPE 0x00000007 +#define GPIO_PIN19_INT_TYPE_M ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S)) +#define GPIO_PIN19_INT_TYPE_V 0x7 +#define GPIO_PIN19_INT_TYPE_S 7 + +/* GPIO_PIN19_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN19_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN19_SYNC1_BYPASS_M ((GPIO_PIN19_SYNC1_BYPASS_V)<<(GPIO_PIN19_SYNC1_BYPASS_S)) +#define GPIO_PIN19_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN19_SYNC1_BYPASS_S 3 + +/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_V 0x1 +#define GPIO_PIN19_PAD_DRIVER_S 2 + +/* GPIO_PIN19_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN19_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN19_SYNC2_BYPASS_M ((GPIO_PIN19_SYNC2_BYPASS_V)<<(GPIO_PIN19_SYNC2_BYPASS_S)) +#define GPIO_PIN19_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN19_SYNC2_BYPASS_S 0 + +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4) + +/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN20_INT_ENA 0x0000001f +#define GPIO_PIN20_INT_ENA_M ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S)) +#define GPIO_PIN20_INT_ENA_V 0x1f +#define GPIO_PIN20_INT_ENA_S 13 + +/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN20_CONFIG 0x00000003 +#define GPIO_PIN20_CONFIG_M ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S)) +#define GPIO_PIN20_CONFIG_V 0x3 +#define GPIO_PIN20_CONFIG_S 11 + +/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN20_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN20_INT_TYPE 0x00000007 +#define GPIO_PIN20_INT_TYPE_M ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S)) +#define GPIO_PIN20_INT_TYPE_V 0x7 +#define GPIO_PIN20_INT_TYPE_S 7 + +/* GPIO_PIN20_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN20_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN20_SYNC1_BYPASS_M ((GPIO_PIN20_SYNC1_BYPASS_V)<<(GPIO_PIN20_SYNC1_BYPASS_S)) +#define GPIO_PIN20_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN20_SYNC1_BYPASS_S 3 + +/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_V 0x1 +#define GPIO_PIN20_PAD_DRIVER_S 2 + +/* GPIO_PIN20_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN20_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN20_SYNC2_BYPASS_M ((GPIO_PIN20_SYNC2_BYPASS_V)<<(GPIO_PIN20_SYNC2_BYPASS_S)) +#define GPIO_PIN20_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN20_SYNC2_BYPASS_S 0 + +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8) + +/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN21_INT_ENA 0x0000001f +#define GPIO_PIN21_INT_ENA_M ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S)) +#define GPIO_PIN21_INT_ENA_V 0x1f +#define GPIO_PIN21_INT_ENA_S 13 + +/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN21_CONFIG 0x00000003 +#define GPIO_PIN21_CONFIG_M ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S)) +#define GPIO_PIN21_CONFIG_V 0x3 +#define GPIO_PIN21_CONFIG_S 11 + +/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN21_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN21_INT_TYPE 0x00000007 +#define GPIO_PIN21_INT_TYPE_M ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S)) +#define GPIO_PIN21_INT_TYPE_V 0x7 +#define GPIO_PIN21_INT_TYPE_S 7 + +/* GPIO_PIN21_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN21_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN21_SYNC1_BYPASS_M ((GPIO_PIN21_SYNC1_BYPASS_V)<<(GPIO_PIN21_SYNC1_BYPASS_S)) +#define GPIO_PIN21_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN21_SYNC1_BYPASS_S 3 + +/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_V 0x1 +#define GPIO_PIN21_PAD_DRIVER_S 2 + +/* GPIO_PIN21_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN21_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN21_SYNC2_BYPASS_M ((GPIO_PIN21_SYNC2_BYPASS_V)<<(GPIO_PIN21_SYNC2_BYPASS_S)) +#define GPIO_PIN21_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN21_SYNC2_BYPASS_S 0 + +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc) + +/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN22_INT_ENA 0x0000001f +#define GPIO_PIN22_INT_ENA_M ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S)) +#define GPIO_PIN22_INT_ENA_V 0x1f +#define GPIO_PIN22_INT_ENA_S 13 + +/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN22_CONFIG 0x00000003 +#define GPIO_PIN22_CONFIG_M ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S)) +#define GPIO_PIN22_CONFIG_V 0x3 +#define GPIO_PIN22_CONFIG_S 11 + +/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN22_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN22_INT_TYPE 0x00000007 +#define GPIO_PIN22_INT_TYPE_M ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S)) +#define GPIO_PIN22_INT_TYPE_V 0x7 +#define GPIO_PIN22_INT_TYPE_S 7 + +/* GPIO_PIN22_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN22_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN22_SYNC1_BYPASS_M ((GPIO_PIN22_SYNC1_BYPASS_V)<<(GPIO_PIN22_SYNC1_BYPASS_S)) +#define GPIO_PIN22_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN22_SYNC1_BYPASS_S 3 + +/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN22_PAD_DRIVER (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_V 0x1 +#define GPIO_PIN22_PAD_DRIVER_S 2 + +/* GPIO_PIN22_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN22_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN22_SYNC2_BYPASS_M ((GPIO_PIN22_SYNC2_BYPASS_V)<<(GPIO_PIN22_SYNC2_BYPASS_S)) +#define GPIO_PIN22_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN22_SYNC2_BYPASS_S 0 + +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0) + +/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN23_INT_ENA 0x0000001f +#define GPIO_PIN23_INT_ENA_M ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S)) +#define GPIO_PIN23_INT_ENA_V 0x1f +#define GPIO_PIN23_INT_ENA_S 13 + +/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN23_CONFIG 0x00000003 +#define GPIO_PIN23_CONFIG_M ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S)) +#define GPIO_PIN23_CONFIG_V 0x3 +#define GPIO_PIN23_CONFIG_S 11 + +/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN23_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN23_INT_TYPE 0x00000007 +#define GPIO_PIN23_INT_TYPE_M ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S)) +#define GPIO_PIN23_INT_TYPE_V 0x7 +#define GPIO_PIN23_INT_TYPE_S 7 + +/* GPIO_PIN23_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN23_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN23_SYNC1_BYPASS_M ((GPIO_PIN23_SYNC1_BYPASS_V)<<(GPIO_PIN23_SYNC1_BYPASS_S)) +#define GPIO_PIN23_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN23_SYNC1_BYPASS_S 3 + +/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN23_PAD_DRIVER (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_V 0x1 +#define GPIO_PIN23_PAD_DRIVER_S 2 + +/* GPIO_PIN23_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN23_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN23_SYNC2_BYPASS_M ((GPIO_PIN23_SYNC2_BYPASS_V)<<(GPIO_PIN23_SYNC2_BYPASS_S)) +#define GPIO_PIN23_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN23_SYNC2_BYPASS_S 0 + +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4) + +/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN24_INT_ENA 0x0000001f +#define GPIO_PIN24_INT_ENA_M ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S)) +#define GPIO_PIN24_INT_ENA_V 0x1f +#define GPIO_PIN24_INT_ENA_S 13 + +/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN24_CONFIG 0x00000003 +#define GPIO_PIN24_CONFIG_M ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S)) +#define GPIO_PIN24_CONFIG_V 0x3 +#define GPIO_PIN24_CONFIG_S 11 + +/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN24_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN24_INT_TYPE 0x00000007 +#define GPIO_PIN24_INT_TYPE_M ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S)) +#define GPIO_PIN24_INT_TYPE_V 0x7 +#define GPIO_PIN24_INT_TYPE_S 7 + +/* GPIO_PIN24_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN24_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN24_SYNC1_BYPASS_M ((GPIO_PIN24_SYNC1_BYPASS_V)<<(GPIO_PIN24_SYNC1_BYPASS_S)) +#define GPIO_PIN24_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN24_SYNC1_BYPASS_S 3 + +/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN24_PAD_DRIVER (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_V 0x1 +#define GPIO_PIN24_PAD_DRIVER_S 2 + +/* GPIO_PIN24_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN24_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN24_SYNC2_BYPASS_M ((GPIO_PIN24_SYNC2_BYPASS_V)<<(GPIO_PIN24_SYNC2_BYPASS_S)) +#define GPIO_PIN24_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN24_SYNC2_BYPASS_S 0 + +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8) + +/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ + +#define GPIO_PIN25_INT_ENA 0x0000001f +#define GPIO_PIN25_INT_ENA_M ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S)) +#define GPIO_PIN25_INT_ENA_V 0x1f +#define GPIO_PIN25_INT_ENA_S 13 + +/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ + +#define GPIO_PIN25_CONFIG 0x00000003 +#define GPIO_PIN25_CONFIG_M ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S)) +#define GPIO_PIN25_CONFIG_V 0x3 +#define GPIO_PIN25_CONFIG_S 11 + +/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN25_WAKEUP_ENABLE_S 10 + +/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ + +#define GPIO_PIN25_INT_TYPE 0x00000007 +#define GPIO_PIN25_INT_TYPE_M ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S)) +#define GPIO_PIN25_INT_TYPE_V 0x7 +#define GPIO_PIN25_INT_TYPE_S 7 + +/* GPIO_PIN25_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ + +#define GPIO_PIN25_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN25_SYNC1_BYPASS_M ((GPIO_PIN25_SYNC1_BYPASS_V)<<(GPIO_PIN25_SYNC1_BYPASS_S)) +#define GPIO_PIN25_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN25_SYNC1_BYPASS_S 3 + +/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ + +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_V 0x1 +#define GPIO_PIN25_PAD_DRIVER_S 2 + +/* GPIO_PIN25_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ + +#define GPIO_PIN25_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN25_SYNC2_BYPASS_M ((GPIO_PIN25_SYNC2_BYPASS_V)<<(GPIO_PIN25_SYNC2_BYPASS_S)) +#define GPIO_PIN25_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN25_SYNC2_BYPASS_S 0 + +#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14c) + +/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[25:0] ;default: 26'h0 ; */ + +#define GPIO_STATUS_INTERRUPT_NEXT 0x03ffffff +#define GPIO_STATUS_INTERRUPT_NEXT_M ((GPIO_STATUS_INTERRUPT_NEXT_V)<<(GPIO_STATUS_INTERRUPT_NEXT_S)) +#define GPIO_STATUS_INTERRUPT_NEXT_V 0x3ffffff +#define GPIO_STATUS_INTERRUPT_NEXT_S 0 + +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) + +/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG0_IN_SEL (BIT(6)) +#define GPIO_SIG0_IN_SEL_M (BIT(6)) +#define GPIO_SIG0_IN_SEL_V 0x1 +#define GPIO_SIG0_IN_SEL_S 6 + +/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC0_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC0_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC0_IN_INV_SEL_V 0x1 +#define GPIO_FUNC0_IN_INV_SEL_S 5 + +/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC0_IN_SEL 0x0000001f +#define GPIO_FUNC0_IN_SEL_M ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S)) +#define GPIO_FUNC0_IN_SEL_V 0x1f +#define GPIO_FUNC0_IN_SEL_S 0 + +#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x158) + +/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG1_IN_SEL (BIT(6)) +#define GPIO_SIG1_IN_SEL_M (BIT(6)) +#define GPIO_SIG1_IN_SEL_V 0x1 +#define GPIO_SIG1_IN_SEL_S 6 + +/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC1_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC1_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC1_IN_INV_SEL_V 0x1 +#define GPIO_FUNC1_IN_INV_SEL_S 5 + +/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC1_IN_SEL 0x0000001f +#define GPIO_FUNC1_IN_SEL_M ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S)) +#define GPIO_FUNC1_IN_SEL_V 0x1f +#define GPIO_FUNC1_IN_SEL_S 0 + +#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15c) + +/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG2_IN_SEL (BIT(6)) +#define GPIO_SIG2_IN_SEL_M (BIT(6)) +#define GPIO_SIG2_IN_SEL_V 0x1 +#define GPIO_SIG2_IN_SEL_S 6 + +/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC2_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC2_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC2_IN_INV_SEL_V 0x1 +#define GPIO_FUNC2_IN_INV_SEL_S 5 + +/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC2_IN_SEL 0x0000001f +#define GPIO_FUNC2_IN_SEL_M ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S)) +#define GPIO_FUNC2_IN_SEL_V 0x1f +#define GPIO_FUNC2_IN_SEL_S 0 + +#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160) + +/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG3_IN_SEL (BIT(6)) +#define GPIO_SIG3_IN_SEL_M (BIT(6)) +#define GPIO_SIG3_IN_SEL_V 0x1 +#define GPIO_SIG3_IN_SEL_S 6 + +/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC3_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC3_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC3_IN_INV_SEL_V 0x1 +#define GPIO_FUNC3_IN_INV_SEL_S 5 + +/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC3_IN_SEL 0x0000001f +#define GPIO_FUNC3_IN_SEL_M ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S)) +#define GPIO_FUNC3_IN_SEL_V 0x1f +#define GPIO_FUNC3_IN_SEL_S 0 + +#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164) + +/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG4_IN_SEL (BIT(6)) +#define GPIO_SIG4_IN_SEL_M (BIT(6)) +#define GPIO_SIG4_IN_SEL_V 0x1 +#define GPIO_SIG4_IN_SEL_S 6 + +/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC4_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC4_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC4_IN_INV_SEL_V 0x1 +#define GPIO_FUNC4_IN_INV_SEL_S 5 + +/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC4_IN_SEL 0x0000001f +#define GPIO_FUNC4_IN_SEL_M ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S)) +#define GPIO_FUNC4_IN_SEL_V 0x1f +#define GPIO_FUNC4_IN_SEL_S 0 + +#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168) + +/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG5_IN_SEL (BIT(6)) +#define GPIO_SIG5_IN_SEL_M (BIT(6)) +#define GPIO_SIG5_IN_SEL_V 0x1 +#define GPIO_SIG5_IN_SEL_S 6 + +/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC5_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC5_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC5_IN_INV_SEL_V 0x1 +#define GPIO_FUNC5_IN_INV_SEL_S 5 + +/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC5_IN_SEL 0x0000001f +#define GPIO_FUNC5_IN_SEL_M ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S)) +#define GPIO_FUNC5_IN_SEL_V 0x1f +#define GPIO_FUNC5_IN_SEL_S 0 + +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c) + +/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG6_IN_SEL (BIT(6)) +#define GPIO_SIG6_IN_SEL_M (BIT(6)) +#define GPIO_SIG6_IN_SEL_V 0x1 +#define GPIO_SIG6_IN_SEL_S 6 + +/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC6_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC6_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC6_IN_INV_SEL_V 0x1 +#define GPIO_FUNC6_IN_INV_SEL_S 5 + +/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC6_IN_SEL 0x0000001f +#define GPIO_FUNC6_IN_SEL_M ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S)) +#define GPIO_FUNC6_IN_SEL_V 0x1f +#define GPIO_FUNC6_IN_SEL_S 0 + +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) + +/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG7_IN_SEL (BIT(6)) +#define GPIO_SIG7_IN_SEL_M (BIT(6)) +#define GPIO_SIG7_IN_SEL_V 0x1 +#define GPIO_SIG7_IN_SEL_S 6 + +/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC7_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC7_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC7_IN_INV_SEL_V 0x1 +#define GPIO_FUNC7_IN_INV_SEL_S 5 + +/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC7_IN_SEL 0x0000001f +#define GPIO_FUNC7_IN_SEL_M ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S)) +#define GPIO_FUNC7_IN_SEL_V 0x1f +#define GPIO_FUNC7_IN_SEL_S 0 + +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) + +/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG8_IN_SEL (BIT(6)) +#define GPIO_SIG8_IN_SEL_M (BIT(6)) +#define GPIO_SIG8_IN_SEL_V 0x1 +#define GPIO_SIG8_IN_SEL_S 6 + +/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC8_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC8_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC8_IN_INV_SEL_V 0x1 +#define GPIO_FUNC8_IN_INV_SEL_S 5 + +/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC8_IN_SEL 0x0000001f +#define GPIO_FUNC8_IN_SEL_M ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S)) +#define GPIO_FUNC8_IN_SEL_V 0x1f +#define GPIO_FUNC8_IN_SEL_S 0 + +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) + +/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG9_IN_SEL (BIT(6)) +#define GPIO_SIG9_IN_SEL_M (BIT(6)) +#define GPIO_SIG9_IN_SEL_V 0x1 +#define GPIO_SIG9_IN_SEL_S 6 + +/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC9_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC9_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC9_IN_INV_SEL_V 0x1 +#define GPIO_FUNC9_IN_INV_SEL_S 5 + +/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC9_IN_SEL 0x0000001f +#define GPIO_FUNC9_IN_SEL_M ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S)) +#define GPIO_FUNC9_IN_SEL_V 0x1f +#define GPIO_FUNC9_IN_SEL_S 0 + +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c) + +/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG10_IN_SEL (BIT(6)) +#define GPIO_SIG10_IN_SEL_M (BIT(6)) +#define GPIO_SIG10_IN_SEL_V 0x1 +#define GPIO_SIG10_IN_SEL_S 6 + +/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC10_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC10_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC10_IN_INV_SEL_V 0x1 +#define GPIO_FUNC10_IN_INV_SEL_S 5 + +/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC10_IN_SEL 0x0000001f +#define GPIO_FUNC10_IN_SEL_M ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S)) +#define GPIO_FUNC10_IN_SEL_V 0x1f +#define GPIO_FUNC10_IN_SEL_S 0 + +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) + +/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG11_IN_SEL (BIT(6)) +#define GPIO_SIG11_IN_SEL_M (BIT(6)) +#define GPIO_SIG11_IN_SEL_V 0x1 +#define GPIO_SIG11_IN_SEL_S 6 + +/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC11_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC11_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC11_IN_INV_SEL_V 0x1 +#define GPIO_FUNC11_IN_INV_SEL_S 5 + +/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC11_IN_SEL 0x0000001f +#define GPIO_FUNC11_IN_SEL_M ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S)) +#define GPIO_FUNC11_IN_SEL_V 0x1f +#define GPIO_FUNC11_IN_SEL_S 0 + +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) + +/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG12_IN_SEL (BIT(6)) +#define GPIO_SIG12_IN_SEL_M (BIT(6)) +#define GPIO_SIG12_IN_SEL_V 0x1 +#define GPIO_SIG12_IN_SEL_S 6 + +/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC12_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC12_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC12_IN_INV_SEL_V 0x1 +#define GPIO_FUNC12_IN_INV_SEL_S 5 + +/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC12_IN_SEL 0x0000001f +#define GPIO_FUNC12_IN_SEL_M ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S)) +#define GPIO_FUNC12_IN_SEL_V 0x1f +#define GPIO_FUNC12_IN_SEL_S 0 + +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) + +/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG13_IN_SEL (BIT(6)) +#define GPIO_SIG13_IN_SEL_M (BIT(6)) +#define GPIO_SIG13_IN_SEL_V 0x1 +#define GPIO_SIG13_IN_SEL_S 6 + +/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC13_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC13_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC13_IN_INV_SEL_V 0x1 +#define GPIO_FUNC13_IN_INV_SEL_S 5 + +/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC13_IN_SEL 0x0000001f +#define GPIO_FUNC13_IN_SEL_M ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S)) +#define GPIO_FUNC13_IN_SEL_V 0x1f +#define GPIO_FUNC13_IN_SEL_S 0 + +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c) + +/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG14_IN_SEL (BIT(6)) +#define GPIO_SIG14_IN_SEL_M (BIT(6)) +#define GPIO_SIG14_IN_SEL_V 0x1 +#define GPIO_SIG14_IN_SEL_S 6 + +/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC14_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC14_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC14_IN_INV_SEL_V 0x1 +#define GPIO_FUNC14_IN_INV_SEL_S 5 + +/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC14_IN_SEL 0x0000001f +#define GPIO_FUNC14_IN_SEL_M ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S)) +#define GPIO_FUNC14_IN_SEL_V 0x1f +#define GPIO_FUNC14_IN_SEL_S 0 + +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) + +/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG15_IN_SEL (BIT(6)) +#define GPIO_SIG15_IN_SEL_M (BIT(6)) +#define GPIO_SIG15_IN_SEL_V 0x1 +#define GPIO_SIG15_IN_SEL_S 6 + +/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC15_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC15_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC15_IN_INV_SEL_V 0x1 +#define GPIO_FUNC15_IN_INV_SEL_S 5 + +/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC15_IN_SEL 0x0000001f +#define GPIO_FUNC15_IN_SEL_M ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S)) +#define GPIO_FUNC15_IN_SEL_V 0x1f +#define GPIO_FUNC15_IN_SEL_S 0 + +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) + +/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG16_IN_SEL (BIT(6)) +#define GPIO_SIG16_IN_SEL_M (BIT(6)) +#define GPIO_SIG16_IN_SEL_V 0x1 +#define GPIO_SIG16_IN_SEL_S 6 + +/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC16_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC16_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC16_IN_INV_SEL_V 0x1 +#define GPIO_FUNC16_IN_INV_SEL_S 5 + +/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC16_IN_SEL 0x0000001f +#define GPIO_FUNC16_IN_SEL_M ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S)) +#define GPIO_FUNC16_IN_SEL_V 0x1f +#define GPIO_FUNC16_IN_SEL_S 0 + +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) + +/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG17_IN_SEL (BIT(6)) +#define GPIO_SIG17_IN_SEL_M (BIT(6)) +#define GPIO_SIG17_IN_SEL_V 0x1 +#define GPIO_SIG17_IN_SEL_S 6 + +/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC17_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC17_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC17_IN_INV_SEL_V 0x1 +#define GPIO_FUNC17_IN_INV_SEL_S 5 + +/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC17_IN_SEL 0x0000001f + +#define GPIO_FUNC17_IN_SEL_M ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S)) +#define GPIO_FUNC17_IN_SEL_V 0x1f +#define GPIO_FUNC17_IN_SEL_S 0 + +#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19c) + +/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG18_IN_SEL (BIT(6)) +#define GPIO_SIG18_IN_SEL_M (BIT(6)) +#define GPIO_SIG18_IN_SEL_V 0x1 +#define GPIO_SIG18_IN_SEL_S 6 + +/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC18_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC18_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC18_IN_INV_SEL_V 0x1 +#define GPIO_FUNC18_IN_INV_SEL_S 5 + +/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC18_IN_SEL 0x0000001f +#define GPIO_FUNC18_IN_SEL_M ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S)) +#define GPIO_FUNC18_IN_SEL_V 0x1f +#define GPIO_FUNC18_IN_SEL_S 0 + +#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0) + +/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG19_IN_SEL (BIT(6)) +#define GPIO_SIG19_IN_SEL_M (BIT(6)) +#define GPIO_SIG19_IN_SEL_V 0x1 +#define GPIO_SIG19_IN_SEL_S 6 + +/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC19_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC19_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC19_IN_INV_SEL_V 0x1 +#define GPIO_FUNC19_IN_INV_SEL_S 5 + +/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC19_IN_SEL 0x0000001f +#define GPIO_FUNC19_IN_SEL_M ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S)) +#define GPIO_FUNC19_IN_SEL_V 0x1f +#define GPIO_FUNC19_IN_SEL_S 0 + +#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a4) + +/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG20_IN_SEL (BIT(6)) +#define GPIO_SIG20_IN_SEL_M (BIT(6)) +#define GPIO_SIG20_IN_SEL_V 0x1 +#define GPIO_SIG20_IN_SEL_S 6 + +/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC20_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC20_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC20_IN_INV_SEL_V 0x1 +#define GPIO_FUNC20_IN_INV_SEL_S 5 + +/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC20_IN_SEL 0x0000001f +#define GPIO_FUNC20_IN_SEL_M ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S)) +#define GPIO_FUNC20_IN_SEL_V 0x1f +#define GPIO_FUNC20_IN_SEL_S 0 + +#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a8) + +/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG21_IN_SEL (BIT(6)) +#define GPIO_SIG21_IN_SEL_M (BIT(6)) +#define GPIO_SIG21_IN_SEL_V 0x1 +#define GPIO_SIG21_IN_SEL_S 6 + +/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC21_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC21_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC21_IN_INV_SEL_V 0x1 +#define GPIO_FUNC21_IN_INV_SEL_S 5 + +/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC21_IN_SEL 0x0000001f +#define GPIO_FUNC21_IN_SEL_M ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S)) +#define GPIO_FUNC21_IN_SEL_V 0x1f +#define GPIO_FUNC21_IN_SEL_S 0 + +#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ac) + +/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG22_IN_SEL (BIT(6)) +#define GPIO_SIG22_IN_SEL_M (BIT(6)) +#define GPIO_SIG22_IN_SEL_V 0x1 +#define GPIO_SIG22_IN_SEL_S 6 + +/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC22_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC22_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC22_IN_INV_SEL_V 0x1 +#define GPIO_FUNC22_IN_INV_SEL_S 5 + +/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC22_IN_SEL 0x0000001f +#define GPIO_FUNC22_IN_SEL_M ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S)) +#define GPIO_FUNC22_IN_SEL_V 0x1f +#define GPIO_FUNC22_IN_SEL_S 0 + +#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b0) + +/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG23_IN_SEL (BIT(6)) +#define GPIO_SIG23_IN_SEL_M (BIT(6)) +#define GPIO_SIG23_IN_SEL_V 0x1 +#define GPIO_SIG23_IN_SEL_S 6 + +/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC23_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC23_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC23_IN_INV_SEL_V 0x1 +#define GPIO_FUNC23_IN_INV_SEL_S 5 + +/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC23_IN_SEL 0x0000001f +#define GPIO_FUNC23_IN_SEL_M ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S)) +#define GPIO_FUNC23_IN_SEL_V 0x1f +#define GPIO_FUNC23_IN_SEL_S 0 + +#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b4) + +/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG24_IN_SEL (BIT(6)) +#define GPIO_SIG24_IN_SEL_M (BIT(6)) +#define GPIO_SIG24_IN_SEL_V 0x1 +#define GPIO_SIG24_IN_SEL_S 6 + +/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC24_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC24_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC24_IN_INV_SEL_V 0x1 +#define GPIO_FUNC24_IN_INV_SEL_S 5 + +/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC24_IN_SEL 0x0000001f +#define GPIO_FUNC24_IN_SEL_M ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S)) +#define GPIO_FUNC24_IN_SEL_V 0x1f +#define GPIO_FUNC24_IN_SEL_S 0 + +#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b8) + +/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG25_IN_SEL (BIT(6)) +#define GPIO_SIG25_IN_SEL_M (BIT(6)) +#define GPIO_SIG25_IN_SEL_V 0x1 +#define GPIO_SIG25_IN_SEL_S 6 + +/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC25_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC25_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC25_IN_INV_SEL_V 0x1 +#define GPIO_FUNC25_IN_INV_SEL_S 5 + +/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC25_IN_SEL 0x0000001f +#define GPIO_FUNC25_IN_SEL_M ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S)) +#define GPIO_FUNC25_IN_SEL_V 0x1f +#define GPIO_FUNC25_IN_SEL_S 0 + +#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1bc) + +/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG26_IN_SEL (BIT(6)) +#define GPIO_SIG26_IN_SEL_M (BIT(6)) +#define GPIO_SIG26_IN_SEL_V 0x1 +#define GPIO_SIG26_IN_SEL_S 6 + +/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC26_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC26_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC26_IN_INV_SEL_V 0x1 +#define GPIO_FUNC26_IN_INV_SEL_S 5 + +/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC26_IN_SEL 0x0000001f +#define GPIO_FUNC26_IN_SEL_M ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S)) +#define GPIO_FUNC26_IN_SEL_V 0x1f +#define GPIO_FUNC26_IN_SEL_S 0 + +#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c0) + +/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG27_IN_SEL (BIT(6)) +#define GPIO_SIG27_IN_SEL_M (BIT(6)) +#define GPIO_SIG27_IN_SEL_V 0x1 +#define GPIO_SIG27_IN_SEL_S 6 + +/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC27_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC27_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC27_IN_INV_SEL_V 0x1 +#define GPIO_FUNC27_IN_INV_SEL_S 5 + +/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC27_IN_SEL 0x0000001f +#define GPIO_FUNC27_IN_SEL_M ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S)) +#define GPIO_FUNC27_IN_SEL_V 0x1f +#define GPIO_FUNC27_IN_SEL_S 0 + +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4) + +/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG28_IN_SEL (BIT(6)) +#define GPIO_SIG28_IN_SEL_M (BIT(6)) +#define GPIO_SIG28_IN_SEL_V 0x1 +#define GPIO_SIG28_IN_SEL_S 6 + +/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC28_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC28_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC28_IN_INV_SEL_V 0x1 +#define GPIO_FUNC28_IN_INV_SEL_S 5 + +/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC28_IN_SEL 0x0000001f +#define GPIO_FUNC28_IN_SEL_M ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S)) +#define GPIO_FUNC28_IN_SEL_V 0x1f +#define GPIO_FUNC28_IN_SEL_S 0 + +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8) + +/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG29_IN_SEL (BIT(6)) +#define GPIO_SIG29_IN_SEL_M (BIT(6)) +#define GPIO_SIG29_IN_SEL_V 0x1 +#define GPIO_SIG29_IN_SEL_S 6 + +/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC29_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC29_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC29_IN_INV_SEL_V 0x1 +#define GPIO_FUNC29_IN_INV_SEL_S 5 + +/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC29_IN_SEL 0x0000001f +#define GPIO_FUNC29_IN_SEL_M ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S)) +#define GPIO_FUNC29_IN_SEL_V 0x1f +#define GPIO_FUNC29_IN_SEL_S 0 + +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc) + +/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG30_IN_SEL (BIT(6)) +#define GPIO_SIG30_IN_SEL_M (BIT(6)) +#define GPIO_SIG30_IN_SEL_V 0x1 +#define GPIO_SIG30_IN_SEL_S 6 + +/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC30_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC30_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC30_IN_INV_SEL_V 0x1 +#define GPIO_FUNC30_IN_INV_SEL_S 5 + +/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC30_IN_SEL 0x0000001f +#define GPIO_FUNC30_IN_SEL_M ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S)) +#define GPIO_FUNC30_IN_SEL_V 0x1f +#define GPIO_FUNC30_IN_SEL_S 0 + +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0) + +/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG31_IN_SEL (BIT(6)) +#define GPIO_SIG31_IN_SEL_M (BIT(6)) +#define GPIO_SIG31_IN_SEL_V 0x1 +#define GPIO_SIG31_IN_SEL_S 6 + +/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC31_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC31_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC31_IN_INV_SEL_V 0x1 +#define GPIO_FUNC31_IN_INV_SEL_S 5 + +/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC31_IN_SEL 0x0000001f +#define GPIO_FUNC31_IN_SEL_M ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S)) +#define GPIO_FUNC31_IN_SEL_V 0x1f +#define GPIO_FUNC31_IN_SEL_S 0 + +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4) + +/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG32_IN_SEL (BIT(6)) +#define GPIO_SIG32_IN_SEL_M (BIT(6)) +#define GPIO_SIG32_IN_SEL_V 0x1 +#define GPIO_SIG32_IN_SEL_S 6 + +/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC32_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC32_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC32_IN_INV_SEL_V 0x1 +#define GPIO_FUNC32_IN_INV_SEL_S 5 + +/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC32_IN_SEL 0x0000001f +#define GPIO_FUNC32_IN_SEL_M ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S)) +#define GPIO_FUNC32_IN_SEL_V 0x1f +#define GPIO_FUNC32_IN_SEL_S 0 + +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8) + +/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG33_IN_SEL (BIT(6)) +#define GPIO_SIG33_IN_SEL_M (BIT(6)) +#define GPIO_SIG33_IN_SEL_V 0x1 +#define GPIO_SIG33_IN_SEL_S 6 + +/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC33_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC33_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC33_IN_INV_SEL_V 0x1 +#define GPIO_FUNC33_IN_INV_SEL_S 5 + +/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC33_IN_SEL 0x0000001f +#define GPIO_FUNC33_IN_SEL_M ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S)) +#define GPIO_FUNC33_IN_SEL_V 0x1f +#define GPIO_FUNC33_IN_SEL_S 0 + +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc) + +/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG34_IN_SEL (BIT(6)) +#define GPIO_SIG34_IN_SEL_M (BIT(6)) +#define GPIO_SIG34_IN_SEL_V 0x1 +#define GPIO_SIG34_IN_SEL_S 6 + +/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC34_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC34_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC34_IN_INV_SEL_V 0x1 +#define GPIO_FUNC34_IN_INV_SEL_S 5 + +/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC34_IN_SEL 0x0000001f +#define GPIO_FUNC34_IN_SEL_M ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S)) +#define GPIO_FUNC34_IN_SEL_V 0x1f +#define GPIO_FUNC34_IN_SEL_S 0 + +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0) + +/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG35_IN_SEL (BIT(6)) +#define GPIO_SIG35_IN_SEL_M (BIT(6)) +#define GPIO_SIG35_IN_SEL_V 0x1 +#define GPIO_SIG35_IN_SEL_S 6 + +/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC35_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC35_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC35_IN_INV_SEL_V 0x1 +#define GPIO_FUNC35_IN_INV_SEL_S 5 + +/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC35_IN_SEL 0x0000001f +#define GPIO_FUNC35_IN_SEL_M ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S)) +#define GPIO_FUNC35_IN_SEL_V 0x1f +#define GPIO_FUNC35_IN_SEL_S 0 + +#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e4) + +/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG36_IN_SEL (BIT(6)) +#define GPIO_SIG36_IN_SEL_M (BIT(6)) +#define GPIO_SIG36_IN_SEL_V 0x1 +#define GPIO_SIG36_IN_SEL_S 6 + +/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC36_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC36_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC36_IN_INV_SEL_V 0x1 +#define GPIO_FUNC36_IN_INV_SEL_S 5 + +/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC36_IN_SEL 0x0000001f +#define GPIO_FUNC36_IN_SEL_M ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S)) +#define GPIO_FUNC36_IN_SEL_V 0x1f +#define GPIO_FUNC36_IN_SEL_S 0 + +#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e8) + +/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG37_IN_SEL (BIT(6)) +#define GPIO_SIG37_IN_SEL_M (BIT(6)) +#define GPIO_SIG37_IN_SEL_V 0x1 +#define GPIO_SIG37_IN_SEL_S 6 + +/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC37_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC37_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC37_IN_INV_SEL_V 0x1 +#define GPIO_FUNC37_IN_INV_SEL_S 5 + +/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC37_IN_SEL 0x0000001f +#define GPIO_FUNC37_IN_SEL_M ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S)) +#define GPIO_FUNC37_IN_SEL_V 0x1f +#define GPIO_FUNC37_IN_SEL_S 0 + +#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ec) + +/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG38_IN_SEL (BIT(6)) +#define GPIO_SIG38_IN_SEL_M (BIT(6)) +#define GPIO_SIG38_IN_SEL_V 0x1 +#define GPIO_SIG38_IN_SEL_S 6 + +/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC38_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC38_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC38_IN_INV_SEL_V 0x1 +#define GPIO_FUNC38_IN_INV_SEL_S 5 + +/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC38_IN_SEL 0x0000001f +#define GPIO_FUNC38_IN_SEL_M ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S)) +#define GPIO_FUNC38_IN_SEL_V 0x1f +#define GPIO_FUNC38_IN_SEL_S 0 + +#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f0) + +/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG39_IN_SEL (BIT(6)) +#define GPIO_SIG39_IN_SEL_M (BIT(6)) +#define GPIO_SIG39_IN_SEL_V 0x1 +#define GPIO_SIG39_IN_SEL_S 6 + +/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC39_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC39_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC39_IN_INV_SEL_V 0x1 +#define GPIO_FUNC39_IN_INV_SEL_S 5 + +/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC39_IN_SEL 0x0000001f +#define GPIO_FUNC39_IN_SEL_M ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S)) +#define GPIO_FUNC39_IN_SEL_V 0x1f +#define GPIO_FUNC39_IN_SEL_S 0 + +#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4) + +/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG40_IN_SEL (BIT(6)) +#define GPIO_SIG40_IN_SEL_M (BIT(6)) +#define GPIO_SIG40_IN_SEL_V 0x1 +#define GPIO_SIG40_IN_SEL_S 6 + +/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC40_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC40_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC40_IN_INV_SEL_V 0x1 +#define GPIO_FUNC40_IN_INV_SEL_S 5 + +/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC40_IN_SEL 0x0000001f +#define GPIO_FUNC40_IN_SEL_M ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S)) +#define GPIO_FUNC40_IN_SEL_V 0x1f +#define GPIO_FUNC40_IN_SEL_S 0 + +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8) + +/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG41_IN_SEL (BIT(6)) +#define GPIO_SIG41_IN_SEL_M (BIT(6)) +#define GPIO_SIG41_IN_SEL_V 0x1 +#define GPIO_SIG41_IN_SEL_S 6 + +/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC41_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC41_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC41_IN_INV_SEL_V 0x1 +#define GPIO_FUNC41_IN_INV_SEL_S 5 + +/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC41_IN_SEL 0x0000001f +#define GPIO_FUNC41_IN_SEL_M ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S)) +#define GPIO_FUNC41_IN_SEL_V 0x1f +#define GPIO_FUNC41_IN_SEL_S 0 + +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc) + +/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG42_IN_SEL (BIT(6)) +#define GPIO_SIG42_IN_SEL_M (BIT(6)) +#define GPIO_SIG42_IN_SEL_V 0x1 +#define GPIO_SIG42_IN_SEL_S 6 + +/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC42_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC42_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC42_IN_INV_SEL_V 0x1 +#define GPIO_FUNC42_IN_INV_SEL_S 5 + +/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC42_IN_SEL 0x0000001f +#define GPIO_FUNC42_IN_SEL_M ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S)) +#define GPIO_FUNC42_IN_SEL_V 0x1f +#define GPIO_FUNC42_IN_SEL_S 0 + +#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200) + +/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG43_IN_SEL (BIT(6)) +#define GPIO_SIG43_IN_SEL_M (BIT(6)) +#define GPIO_SIG43_IN_SEL_V 0x1 +#define GPIO_SIG43_IN_SEL_S 6 + +/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC43_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC43_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC43_IN_INV_SEL_V 0x1 +#define GPIO_FUNC43_IN_INV_SEL_S 5 + +/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC43_IN_SEL 0x0000001f +#define GPIO_FUNC43_IN_SEL_M ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S)) +#define GPIO_FUNC43_IN_SEL_V 0x1f +#define GPIO_FUNC43_IN_SEL_S 0 + +#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204) + +/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG44_IN_SEL (BIT(6)) +#define GPIO_SIG44_IN_SEL_M (BIT(6)) +#define GPIO_SIG44_IN_SEL_V 0x1 +#define GPIO_SIG44_IN_SEL_S 6 + +/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC44_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC44_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC44_IN_INV_SEL_V 0x1 +#define GPIO_FUNC44_IN_INV_SEL_S 5 + +/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC44_IN_SEL 0x0000001f +#define GPIO_FUNC44_IN_SEL_M ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S)) +#define GPIO_FUNC44_IN_SEL_V 0x1f +#define GPIO_FUNC44_IN_SEL_S 0 + +#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) + +/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG45_IN_SEL (BIT(6)) +#define GPIO_SIG45_IN_SEL_M (BIT(6)) +#define GPIO_SIG45_IN_SEL_V 0x1 +#define GPIO_SIG45_IN_SEL_S 6 + +/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC45_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC45_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC45_IN_INV_SEL_V 0x1 +#define GPIO_FUNC45_IN_INV_SEL_S 5 + +/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC45_IN_SEL 0x0000001f +#define GPIO_FUNC45_IN_SEL_M ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S)) +#define GPIO_FUNC45_IN_SEL_V 0x1f +#define GPIO_FUNC45_IN_SEL_S 0 + +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c) + +/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG46_IN_SEL (BIT(6)) +#define GPIO_SIG46_IN_SEL_M (BIT(6)) +#define GPIO_SIG46_IN_SEL_V 0x1 +#define GPIO_SIG46_IN_SEL_S 6 + +/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC46_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC46_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC46_IN_INV_SEL_V 0x1 +#define GPIO_FUNC46_IN_INV_SEL_S 5 + +/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC46_IN_SEL 0x0000001f +#define GPIO_FUNC46_IN_SEL_M ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S)) +#define GPIO_FUNC46_IN_SEL_V 0x1f +#define GPIO_FUNC46_IN_SEL_S 0 + +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) + +/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG47_IN_SEL (BIT(6)) +#define GPIO_SIG47_IN_SEL_M (BIT(6)) +#define GPIO_SIG47_IN_SEL_V 0x1 +#define GPIO_SIG47_IN_SEL_S 6 + +/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC47_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC47_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC47_IN_INV_SEL_V 0x1 +#define GPIO_FUNC47_IN_INV_SEL_S 5 + +/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC47_IN_SEL 0x0000001f +#define GPIO_FUNC47_IN_SEL_M ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S)) +#define GPIO_FUNC47_IN_SEL_V 0x1f +#define GPIO_FUNC47_IN_SEL_S 0 + +#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) + +/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG48_IN_SEL (BIT(6)) +#define GPIO_SIG48_IN_SEL_M (BIT(6)) +#define GPIO_SIG48_IN_SEL_V 0x1 +#define GPIO_SIG48_IN_SEL_S 6 + +/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC48_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC48_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC48_IN_INV_SEL_V 0x1 +#define GPIO_FUNC48_IN_INV_SEL_S 5 + +/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC48_IN_SEL 0x0000001f +#define GPIO_FUNC48_IN_SEL_M ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S)) +#define GPIO_FUNC48_IN_SEL_V 0x1f +#define GPIO_FUNC48_IN_SEL_S 0 + +#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) + +/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG49_IN_SEL (BIT(6)) +#define GPIO_SIG49_IN_SEL_M (BIT(6)) +#define GPIO_SIG49_IN_SEL_V 0x1 +#define GPIO_SIG49_IN_SEL_S 6 + +/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC49_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC49_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC49_IN_INV_SEL_V 0x1 +#define GPIO_FUNC49_IN_INV_SEL_S 5 + +/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC49_IN_SEL 0x0000001f +#define GPIO_FUNC49_IN_SEL_M ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S)) +#define GPIO_FUNC49_IN_SEL_V 0x1f +#define GPIO_FUNC49_IN_SEL_S 0 + +#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c) + +/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG50_IN_SEL (BIT(6)) +#define GPIO_SIG50_IN_SEL_M (BIT(6)) +#define GPIO_SIG50_IN_SEL_V 0x1 +#define GPIO_SIG50_IN_SEL_S 6 + +/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC50_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC50_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC50_IN_INV_SEL_V 0x1 +#define GPIO_FUNC50_IN_INV_SEL_S 5 + +/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC50_IN_SEL 0x0000001f +#define GPIO_FUNC50_IN_SEL_M ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S)) +#define GPIO_FUNC50_IN_SEL_V 0x1f +#define GPIO_FUNC50_IN_SEL_S 0 + +#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) + +/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG51_IN_SEL (BIT(6)) +#define GPIO_SIG51_IN_SEL_M (BIT(6)) +#define GPIO_SIG51_IN_SEL_V 0x1 +#define GPIO_SIG51_IN_SEL_S 6 + +/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC51_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC51_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC51_IN_INV_SEL_V 0x1 +#define GPIO_FUNC51_IN_INV_SEL_S 5 + +/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC51_IN_SEL 0x0000001f +#define GPIO_FUNC51_IN_SEL_M ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S)) +#define GPIO_FUNC51_IN_SEL_V 0x1f +#define GPIO_FUNC51_IN_SEL_S 0 + +#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) + +/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG52_IN_SEL (BIT(6)) +#define GPIO_SIG52_IN_SEL_M (BIT(6)) +#define GPIO_SIG52_IN_SEL_V 0x1 +#define GPIO_SIG52_IN_SEL_S 6 + +/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC52_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC52_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC52_IN_INV_SEL_V 0x1 +#define GPIO_FUNC52_IN_INV_SEL_S 5 + +/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC52_IN_SEL 0x0000001f +#define GPIO_FUNC52_IN_SEL_M ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S)) +#define GPIO_FUNC52_IN_SEL_V 0x1f +#define GPIO_FUNC52_IN_SEL_S 0 + +#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) + +/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG53_IN_SEL (BIT(6)) +#define GPIO_SIG53_IN_SEL_M (BIT(6)) +#define GPIO_SIG53_IN_SEL_V 0x1 +#define GPIO_SIG53_IN_SEL_S 6 + +/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC53_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC53_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC53_IN_INV_SEL_V 0x1 +#define GPIO_FUNC53_IN_INV_SEL_S 5 + +/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC53_IN_SEL 0x0000001f +#define GPIO_FUNC53_IN_SEL_M ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S)) +#define GPIO_FUNC53_IN_SEL_V 0x1f +#define GPIO_FUNC53_IN_SEL_S 0 + +#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c) + +/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG54_IN_SEL (BIT(6)) +#define GPIO_SIG54_IN_SEL_M (BIT(6)) +#define GPIO_SIG54_IN_SEL_V 0x1 +#define GPIO_SIG54_IN_SEL_S 6 + +/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC54_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC54_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC54_IN_INV_SEL_V 0x1 +#define GPIO_FUNC54_IN_INV_SEL_S 5 + +/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC54_IN_SEL 0x0000001f +#define GPIO_FUNC54_IN_SEL_M ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S)) +#define GPIO_FUNC54_IN_SEL_V 0x1f +#define GPIO_FUNC54_IN_SEL_S 0 + +#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230) + +/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG55_IN_SEL (BIT(6)) +#define GPIO_SIG55_IN_SEL_M (BIT(6)) +#define GPIO_SIG55_IN_SEL_V 0x1 +#define GPIO_SIG55_IN_SEL_S 6 + +/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC55_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC55_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC55_IN_INV_SEL_V 0x1 +#define GPIO_FUNC55_IN_INV_SEL_S 5 + +/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC55_IN_SEL 0x0000001f +#define GPIO_FUNC55_IN_SEL_M ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S)) +#define GPIO_FUNC55_IN_SEL_V 0x1f +#define GPIO_FUNC55_IN_SEL_S 0 + +#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234) + +/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG56_IN_SEL (BIT(6)) +#define GPIO_SIG56_IN_SEL_M (BIT(6)) +#define GPIO_SIG56_IN_SEL_V 0x1 +#define GPIO_SIG56_IN_SEL_S 6 + +/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC56_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC56_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC56_IN_INV_SEL_V 0x1 +#define GPIO_FUNC56_IN_INV_SEL_S 5 + +/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC56_IN_SEL 0x0000001f +#define GPIO_FUNC56_IN_SEL_M ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S)) +#define GPIO_FUNC56_IN_SEL_V 0x1f +#define GPIO_FUNC56_IN_SEL_S 0 + +#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238) + +/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG57_IN_SEL (BIT(6)) +#define GPIO_SIG57_IN_SEL_M (BIT(6)) +#define GPIO_SIG57_IN_SEL_V 0x1 +#define GPIO_SIG57_IN_SEL_S 6 + +/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC57_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC57_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC57_IN_INV_SEL_V 0x1 +#define GPIO_FUNC57_IN_INV_SEL_S 5 + +/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC57_IN_SEL 0x0000001f +#define GPIO_FUNC57_IN_SEL_M ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S)) +#define GPIO_FUNC57_IN_SEL_V 0x1f +#define GPIO_FUNC57_IN_SEL_S 0 + +#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23c) + +/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG58_IN_SEL (BIT(6)) +#define GPIO_SIG58_IN_SEL_M (BIT(6)) +#define GPIO_SIG58_IN_SEL_V 0x1 +#define GPIO_SIG58_IN_SEL_S 6 + +/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC58_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC58_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC58_IN_INV_SEL_V 0x1 +#define GPIO_FUNC58_IN_INV_SEL_S 5 + +/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC58_IN_SEL 0x0000001f +#define GPIO_FUNC58_IN_SEL_M ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S)) +#define GPIO_FUNC58_IN_SEL_V 0x1f +#define GPIO_FUNC58_IN_SEL_S 0 + +#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240) + +/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG59_IN_SEL (BIT(6)) +#define GPIO_SIG59_IN_SEL_M (BIT(6)) +#define GPIO_SIG59_IN_SEL_V 0x1 +#define GPIO_SIG59_IN_SEL_S 6 + +/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC59_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC59_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC59_IN_INV_SEL_V 0x1 +#define GPIO_FUNC59_IN_INV_SEL_S 5 + +/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC59_IN_SEL 0x0000001f +#define GPIO_FUNC59_IN_SEL_M ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S)) +#define GPIO_FUNC59_IN_SEL_V 0x1f +#define GPIO_FUNC59_IN_SEL_S 0 + +#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244) + +/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG60_IN_SEL (BIT(6)) +#define GPIO_SIG60_IN_SEL_M (BIT(6)) +#define GPIO_SIG60_IN_SEL_V 0x1 +#define GPIO_SIG60_IN_SEL_S 6 + +/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC60_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC60_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC60_IN_INV_SEL_V 0x1 +#define GPIO_FUNC60_IN_INV_SEL_S 5 + +/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC60_IN_SEL 0x0000001f +#define GPIO_FUNC60_IN_SEL_M ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S)) +#define GPIO_FUNC60_IN_SEL_V 0x1f +#define GPIO_FUNC60_IN_SEL_S 0 + +#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248) + +/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG61_IN_SEL (BIT(6)) +#define GPIO_SIG61_IN_SEL_M (BIT(6)) +#define GPIO_SIG61_IN_SEL_V 0x1 +#define GPIO_SIG61_IN_SEL_S 6 + +/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC61_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC61_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC61_IN_INV_SEL_V 0x1 +#define GPIO_FUNC61_IN_INV_SEL_S 5 + +/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC61_IN_SEL 0x0000001f +#define GPIO_FUNC61_IN_SEL_M ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S)) +#define GPIO_FUNC61_IN_SEL_V 0x1f +#define GPIO_FUNC61_IN_SEL_S 0 + +#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24c) + +/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG62_IN_SEL (BIT(6)) +#define GPIO_SIG62_IN_SEL_M (BIT(6)) +#define GPIO_SIG62_IN_SEL_V 0x1 +#define GPIO_SIG62_IN_SEL_S 6 + +/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC62_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC62_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC62_IN_INV_SEL_V 0x1 +#define GPIO_FUNC62_IN_INV_SEL_S 5 + +/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC62_IN_SEL 0x0000001f +#define GPIO_FUNC62_IN_SEL_M ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S)) +#define GPIO_FUNC62_IN_SEL_V 0x1f +#define GPIO_FUNC62_IN_SEL_S 0 + +#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) + +/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG63_IN_SEL (BIT(6)) +#define GPIO_SIG63_IN_SEL_M (BIT(6)) +#define GPIO_SIG63_IN_SEL_V 0x1 +#define GPIO_SIG63_IN_SEL_S 6 + +/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC63_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC63_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC63_IN_INV_SEL_V 0x1 +#define GPIO_FUNC63_IN_INV_SEL_S 5 + +/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC63_IN_SEL 0x0000001f +#define GPIO_FUNC63_IN_SEL_M ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S)) +#define GPIO_FUNC63_IN_SEL_V 0x1f +#define GPIO_FUNC63_IN_SEL_S 0 + +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) + +/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG64_IN_SEL (BIT(6)) +#define GPIO_SIG64_IN_SEL_M (BIT(6)) +#define GPIO_SIG64_IN_SEL_V 0x1 +#define GPIO_SIG64_IN_SEL_S 6 + +/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC64_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC64_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC64_IN_INV_SEL_V 0x1 +#define GPIO_FUNC64_IN_INV_SEL_S 5 + +/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC64_IN_SEL 0x0000001f +#define GPIO_FUNC64_IN_SEL_M ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S)) +#define GPIO_FUNC64_IN_SEL_V 0x1f +#define GPIO_FUNC64_IN_SEL_S 0 + +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) + +/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG65_IN_SEL (BIT(6)) +#define GPIO_SIG65_IN_SEL_M (BIT(6)) +#define GPIO_SIG65_IN_SEL_V 0x1 +#define GPIO_SIG65_IN_SEL_S 6 + +/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC65_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC65_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC65_IN_INV_SEL_V 0x1 +#define GPIO_FUNC65_IN_INV_SEL_S 5 + +/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC65_IN_SEL 0x0000001f +#define GPIO_FUNC65_IN_SEL_M ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S)) +#define GPIO_FUNC65_IN_SEL_V 0x1f +#define GPIO_FUNC65_IN_SEL_S 0 + +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c) + +/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG66_IN_SEL (BIT(6)) +#define GPIO_SIG66_IN_SEL_M (BIT(6)) +#define GPIO_SIG66_IN_SEL_V 0x1 +#define GPIO_SIG66_IN_SEL_S 6 + +/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC66_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC66_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC66_IN_INV_SEL_V 0x1 +#define GPIO_FUNC66_IN_INV_SEL_S 5 + +/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC66_IN_SEL 0x0000001f +#define GPIO_FUNC66_IN_SEL_M ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S)) +#define GPIO_FUNC66_IN_SEL_V 0x1f +#define GPIO_FUNC66_IN_SEL_S 0 + +#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) + +/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG67_IN_SEL (BIT(6)) +#define GPIO_SIG67_IN_SEL_M (BIT(6)) +#define GPIO_SIG67_IN_SEL_V 0x1 +#define GPIO_SIG67_IN_SEL_S 6 + +/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC67_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC67_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC67_IN_INV_SEL_V 0x1 +#define GPIO_FUNC67_IN_INV_SEL_S 5 + +/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC67_IN_SEL 0x0000001f +#define GPIO_FUNC67_IN_SEL_M ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S)) +#define GPIO_FUNC67_IN_SEL_V 0x1f +#define GPIO_FUNC67_IN_SEL_S 0 + +#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) + +/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG68_IN_SEL (BIT(6)) +#define GPIO_SIG68_IN_SEL_M (BIT(6)) +#define GPIO_SIG68_IN_SEL_V 0x1 +#define GPIO_SIG68_IN_SEL_S 6 + +/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC68_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC68_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC68_IN_INV_SEL_V 0x1 +#define GPIO_FUNC68_IN_INV_SEL_S 5 + +/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC68_IN_SEL 0x0000001f +#define GPIO_FUNC68_IN_SEL_M ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S)) +#define GPIO_FUNC68_IN_SEL_V 0x1f +#define GPIO_FUNC68_IN_SEL_S 0 + +#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) + +/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG69_IN_SEL (BIT(6)) +#define GPIO_SIG69_IN_SEL_M (BIT(6)) +#define GPIO_SIG69_IN_SEL_V 0x1 +#define GPIO_SIG69_IN_SEL_S 6 + +/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC69_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC69_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC69_IN_INV_SEL_V 0x1 +#define GPIO_FUNC69_IN_INV_SEL_S 5 + +/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC69_IN_SEL 0x0000001f +#define GPIO_FUNC69_IN_SEL_M ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S)) +#define GPIO_FUNC69_IN_SEL_V 0x1f +#define GPIO_FUNC69_IN_SEL_S 0 + +#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c) + +/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG70_IN_SEL (BIT(6)) +#define GPIO_SIG70_IN_SEL_M (BIT(6)) +#define GPIO_SIG70_IN_SEL_V 0x1 +#define GPIO_SIG70_IN_SEL_S 6 + +/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC70_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC70_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC70_IN_INV_SEL_V 0x1 +#define GPIO_FUNC70_IN_INV_SEL_S 5 + +/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC70_IN_SEL 0x0000001f +#define GPIO_FUNC70_IN_SEL_M ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S)) +#define GPIO_FUNC70_IN_SEL_V 0x1f +#define GPIO_FUNC70_IN_SEL_S 0 + +#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) + +/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG71_IN_SEL (BIT(6)) +#define GPIO_SIG71_IN_SEL_M (BIT(6)) +#define GPIO_SIG71_IN_SEL_V 0x1 +#define GPIO_SIG71_IN_SEL_S 6 + +/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC71_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC71_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC71_IN_INV_SEL_V 0x1 +#define GPIO_FUNC71_IN_INV_SEL_S 5 + +/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC71_IN_SEL 0x0000001f +#define GPIO_FUNC71_IN_SEL_M ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S)) +#define GPIO_FUNC71_IN_SEL_V 0x1f +#define GPIO_FUNC71_IN_SEL_S 0 + +#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) + +/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG72_IN_SEL (BIT(6)) +#define GPIO_SIG72_IN_SEL_M (BIT(6)) +#define GPIO_SIG72_IN_SEL_V 0x1 +#define GPIO_SIG72_IN_SEL_S 6 + +/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC72_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC72_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC72_IN_INV_SEL_V 0x1 +#define GPIO_FUNC72_IN_INV_SEL_S 5 + +/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC72_IN_SEL 0x0000001f +#define GPIO_FUNC72_IN_SEL_M ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S)) +#define GPIO_FUNC72_IN_SEL_V 0x1f +#define GPIO_FUNC72_IN_SEL_S 0 + +#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) + +/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG73_IN_SEL (BIT(6)) +#define GPIO_SIG73_IN_SEL_M (BIT(6)) +#define GPIO_SIG73_IN_SEL_V 0x1 +#define GPIO_SIG73_IN_SEL_S 6 + +/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC73_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC73_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC73_IN_INV_SEL_V 0x1 +#define GPIO_FUNC73_IN_INV_SEL_S 5 + +/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC73_IN_SEL 0x0000001f +#define GPIO_FUNC73_IN_SEL_M ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S)) +#define GPIO_FUNC73_IN_SEL_V 0x1f +#define GPIO_FUNC73_IN_SEL_S 0 + +#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x27c) + +/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG74_IN_SEL (BIT(6)) +#define GPIO_SIG74_IN_SEL_M (BIT(6)) +#define GPIO_SIG74_IN_SEL_V 0x1 +#define GPIO_SIG74_IN_SEL_S 6 + +/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC74_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC74_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC74_IN_INV_SEL_V 0x1 +#define GPIO_FUNC74_IN_INV_SEL_S 5 + +/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC74_IN_SEL 0x0000001f +#define GPIO_FUNC74_IN_SEL_M ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S)) +#define GPIO_FUNC74_IN_SEL_V 0x1f +#define GPIO_FUNC74_IN_SEL_S 0 + +#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280) + +/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG75_IN_SEL (BIT(6)) +#define GPIO_SIG75_IN_SEL_M (BIT(6)) +#define GPIO_SIG75_IN_SEL_V 0x1 +#define GPIO_SIG75_IN_SEL_S 6 + +/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC75_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC75_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC75_IN_INV_SEL_V 0x1 +#define GPIO_FUNC75_IN_INV_SEL_S 5 + +/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC75_IN_SEL 0x0000001f +#define GPIO_FUNC75_IN_SEL_M ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S)) +#define GPIO_FUNC75_IN_SEL_V 0x1f +#define GPIO_FUNC75_IN_SEL_S 0 + +#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284) + +/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG76_IN_SEL (BIT(6)) +#define GPIO_SIG76_IN_SEL_M (BIT(6)) +#define GPIO_SIG76_IN_SEL_V 0x1 +#define GPIO_SIG76_IN_SEL_S 6 + +/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC76_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC76_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC76_IN_INV_SEL_V 0x1 +#define GPIO_FUNC76_IN_INV_SEL_S 5 + +/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC76_IN_SEL 0x0000001f +#define GPIO_FUNC76_IN_SEL_M ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S)) +#define GPIO_FUNC76_IN_SEL_V 0x1f +#define GPIO_FUNC76_IN_SEL_S 0 + +#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288) + +/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG77_IN_SEL (BIT(6)) +#define GPIO_SIG77_IN_SEL_M (BIT(6)) +#define GPIO_SIG77_IN_SEL_V 0x1 +#define GPIO_SIG77_IN_SEL_S 6 + +/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC77_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC77_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC77_IN_INV_SEL_V 0x1 +#define GPIO_FUNC77_IN_INV_SEL_S 5 + +/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC77_IN_SEL 0x0000001f +#define GPIO_FUNC77_IN_SEL_M ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S)) +#define GPIO_FUNC77_IN_SEL_V 0x1f +#define GPIO_FUNC77_IN_SEL_S 0 + +#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28c) + +/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG78_IN_SEL (BIT(6)) +#define GPIO_SIG78_IN_SEL_M (BIT(6)) +#define GPIO_SIG78_IN_SEL_V 0x1 +#define GPIO_SIG78_IN_SEL_S 6 + +/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC78_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC78_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC78_IN_INV_SEL_V 0x1 +#define GPIO_FUNC78_IN_INV_SEL_S 5 + +/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC78_IN_SEL 0x0000001f +#define GPIO_FUNC78_IN_SEL_M ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S)) +#define GPIO_FUNC78_IN_SEL_V 0x1f +#define GPIO_FUNC78_IN_SEL_S 0 + +#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290) + +/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG79_IN_SEL (BIT(6)) +#define GPIO_SIG79_IN_SEL_M (BIT(6)) +#define GPIO_SIG79_IN_SEL_V 0x1 +#define GPIO_SIG79_IN_SEL_S 6 + +/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC79_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC79_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC79_IN_INV_SEL_V 0x1 +#define GPIO_FUNC79_IN_INV_SEL_S 5 + +/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC79_IN_SEL 0x0000001f +#define GPIO_FUNC79_IN_SEL_M ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S)) +#define GPIO_FUNC79_IN_SEL_V 0x1f +#define GPIO_FUNC79_IN_SEL_S 0 + +#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x294) + +/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG80_IN_SEL (BIT(6)) +#define GPIO_SIG80_IN_SEL_M (BIT(6)) +#define GPIO_SIG80_IN_SEL_V 0x1 +#define GPIO_SIG80_IN_SEL_S 6 + +/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC80_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC80_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC80_IN_INV_SEL_V 0x1 +#define GPIO_FUNC80_IN_INV_SEL_S 5 + +/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC80_IN_SEL 0x0000001f +#define GPIO_FUNC80_IN_SEL_M ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S)) +#define GPIO_FUNC80_IN_SEL_V 0x1f +#define GPIO_FUNC80_IN_SEL_S 0 + +#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) + +/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG81_IN_SEL (BIT(6)) +#define GPIO_SIG81_IN_SEL_M (BIT(6)) +#define GPIO_SIG81_IN_SEL_V 0x1 +#define GPIO_SIG81_IN_SEL_S 6 + +/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC81_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC81_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC81_IN_INV_SEL_V 0x1 +#define GPIO_FUNC81_IN_INV_SEL_S 5 + +/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC81_IN_SEL 0x0000001f +#define GPIO_FUNC81_IN_SEL_M ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S)) +#define GPIO_FUNC81_IN_SEL_V 0x1f +#define GPIO_FUNC81_IN_SEL_S 0 + +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29c) + +/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG82_IN_SEL (BIT(6)) +#define GPIO_SIG82_IN_SEL_M (BIT(6)) +#define GPIO_SIG82_IN_SEL_V 0x1 +#define GPIO_SIG82_IN_SEL_S 6 + +/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC82_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC82_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC82_IN_INV_SEL_V 0x1 +#define GPIO_FUNC82_IN_INV_SEL_S 5 + +/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC82_IN_SEL 0x0000001f +#define GPIO_FUNC82_IN_SEL_M ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S)) +#define GPIO_FUNC82_IN_SEL_V 0x1f +#define GPIO_FUNC82_IN_SEL_S 0 + +#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a0) + +/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG83_IN_SEL (BIT(6)) +#define GPIO_SIG83_IN_SEL_M (BIT(6)) +#define GPIO_SIG83_IN_SEL_V 0x1 +#define GPIO_SIG83_IN_SEL_S 6 + +/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC83_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC83_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC83_IN_INV_SEL_V 0x1 +#define GPIO_FUNC83_IN_INV_SEL_S 5 + +/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC83_IN_SEL 0x0000001f +#define GPIO_FUNC83_IN_SEL_M ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S)) +#define GPIO_FUNC83_IN_SEL_V 0x1f +#define GPIO_FUNC83_IN_SEL_S 0 + +#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a4) + +/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG84_IN_SEL (BIT(6)) +#define GPIO_SIG84_IN_SEL_M (BIT(6)) +#define GPIO_SIG84_IN_SEL_V 0x1 +#define GPIO_SIG84_IN_SEL_S 6 + +/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC84_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC84_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC84_IN_INV_SEL_V 0x1 +#define GPIO_FUNC84_IN_INV_SEL_S 5 + +/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC84_IN_SEL 0x0000001f +#define GPIO_FUNC84_IN_SEL_M ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S)) +#define GPIO_FUNC84_IN_SEL_V 0x1f +#define GPIO_FUNC84_IN_SEL_S 0 + +#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a8) + +/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG85_IN_SEL (BIT(6)) +#define GPIO_SIG85_IN_SEL_M (BIT(6)) +#define GPIO_SIG85_IN_SEL_V 0x1 +#define GPIO_SIG85_IN_SEL_S 6 + +/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC85_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC85_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC85_IN_INV_SEL_V 0x1 +#define GPIO_FUNC85_IN_INV_SEL_S 5 + +/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC85_IN_SEL 0x0000001f +#define GPIO_FUNC85_IN_SEL_M ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S)) +#define GPIO_FUNC85_IN_SEL_V 0x1f +#define GPIO_FUNC85_IN_SEL_S 0 + +#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ac) + +/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG86_IN_SEL (BIT(6)) +#define GPIO_SIG86_IN_SEL_M (BIT(6)) +#define GPIO_SIG86_IN_SEL_V 0x1 +#define GPIO_SIG86_IN_SEL_S 6 + +/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC86_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC86_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC86_IN_INV_SEL_V 0x1 +#define GPIO_FUNC86_IN_INV_SEL_S 5 + +/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC86_IN_SEL 0x0000001f +#define GPIO_FUNC86_IN_SEL_M ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S)) +#define GPIO_FUNC86_IN_SEL_V 0x1f +#define GPIO_FUNC86_IN_SEL_S 0 + +#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0) + +/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG87_IN_SEL (BIT(6)) +#define GPIO_SIG87_IN_SEL_M (BIT(6)) +#define GPIO_SIG87_IN_SEL_V 0x1 +#define GPIO_SIG87_IN_SEL_S 6 + +/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC87_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC87_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC87_IN_INV_SEL_V 0x1 +#define GPIO_FUNC87_IN_INV_SEL_S 5 + +/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC87_IN_SEL 0x0000001f +#define GPIO_FUNC87_IN_SEL_M ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S)) +#define GPIO_FUNC87_IN_SEL_V 0x1f +#define GPIO_FUNC87_IN_SEL_S 0 + +#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b4) + +/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG88_IN_SEL (BIT(6)) +#define GPIO_SIG88_IN_SEL_M (BIT(6)) +#define GPIO_SIG88_IN_SEL_V 0x1 +#define GPIO_SIG88_IN_SEL_S 6 + +/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC88_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC88_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC88_IN_INV_SEL_V 0x1 +#define GPIO_FUNC88_IN_INV_SEL_S 5 + +/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC88_IN_SEL 0x0000001f +#define GPIO_FUNC88_IN_SEL_M ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S)) +#define GPIO_FUNC88_IN_SEL_V 0x1f +#define GPIO_FUNC88_IN_SEL_S 0 + +#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b8) + +/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG89_IN_SEL (BIT(6)) +#define GPIO_SIG89_IN_SEL_M (BIT(6)) +#define GPIO_SIG89_IN_SEL_V 0x1 +#define GPIO_SIG89_IN_SEL_S 6 + +/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC89_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC89_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC89_IN_INV_SEL_V 0x1 +#define GPIO_FUNC89_IN_INV_SEL_S 5 + +/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC89_IN_SEL 0x0000001f +#define GPIO_FUNC89_IN_SEL_M ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S)) +#define GPIO_FUNC89_IN_SEL_V 0x1f +#define GPIO_FUNC89_IN_SEL_S 0 + +#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc) + +/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG90_IN_SEL (BIT(6)) +#define GPIO_SIG90_IN_SEL_M (BIT(6)) +#define GPIO_SIG90_IN_SEL_V 0x1 +#define GPIO_SIG90_IN_SEL_S 6 + +/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC90_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC90_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC90_IN_INV_SEL_V 0x1 +#define GPIO_FUNC90_IN_INV_SEL_S 5 + +/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC90_IN_SEL 0x0000001f +#define GPIO_FUNC90_IN_SEL_M ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S)) +#define GPIO_FUNC90_IN_SEL_V 0x1f +#define GPIO_FUNC90_IN_SEL_S 0 + +#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0) + +/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG91_IN_SEL (BIT(6)) +#define GPIO_SIG91_IN_SEL_M (BIT(6)) +#define GPIO_SIG91_IN_SEL_V 0x1 +#define GPIO_SIG91_IN_SEL_S 6 + +/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC91_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC91_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC91_IN_INV_SEL_V 0x1 +#define GPIO_FUNC91_IN_INV_SEL_S 5 + +/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC91_IN_SEL 0x0000001f +#define GPIO_FUNC91_IN_SEL_M ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S)) +#define GPIO_FUNC91_IN_SEL_V 0x1f +#define GPIO_FUNC91_IN_SEL_S 0 + +#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4) + +/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG92_IN_SEL (BIT(6)) +#define GPIO_SIG92_IN_SEL_M (BIT(6)) +#define GPIO_SIG92_IN_SEL_V 0x1 +#define GPIO_SIG92_IN_SEL_S 6 + +/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC92_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC92_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC92_IN_INV_SEL_V 0x1 +#define GPIO_FUNC92_IN_INV_SEL_S 5 + +/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC92_IN_SEL 0x0000001f +#define GPIO_FUNC92_IN_SEL_M ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S)) +#define GPIO_FUNC92_IN_SEL_V 0x1f +#define GPIO_FUNC92_IN_SEL_S 0 + +#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8) + +/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG93_IN_SEL (BIT(6)) +#define GPIO_SIG93_IN_SEL_M (BIT(6)) +#define GPIO_SIG93_IN_SEL_V 0x1 +#define GPIO_SIG93_IN_SEL_S 6 + +/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC93_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC93_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC93_IN_INV_SEL_V 0x1 +#define GPIO_FUNC93_IN_INV_SEL_S 5 + +/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC93_IN_SEL 0x0000001f +#define GPIO_FUNC93_IN_SEL_M ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S)) +#define GPIO_FUNC93_IN_SEL_V 0x1f +#define GPIO_FUNC93_IN_SEL_S 0 + +#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc) + +/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG94_IN_SEL (BIT(6)) +#define GPIO_SIG94_IN_SEL_M (BIT(6)) +#define GPIO_SIG94_IN_SEL_V 0x1 +#define GPIO_SIG94_IN_SEL_S 6 + +/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC94_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC94_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC94_IN_INV_SEL_V 0x1 +#define GPIO_FUNC94_IN_INV_SEL_S 5 + +/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC94_IN_SEL 0x0000001f +#define GPIO_FUNC94_IN_SEL_M ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S)) +#define GPIO_FUNC94_IN_SEL_V 0x1f +#define GPIO_FUNC94_IN_SEL_S 0 + +#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0) + +/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG95_IN_SEL (BIT(6)) +#define GPIO_SIG95_IN_SEL_M (BIT(6)) +#define GPIO_SIG95_IN_SEL_V 0x1 +#define GPIO_SIG95_IN_SEL_S 6 + +/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC95_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC95_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC95_IN_INV_SEL_V 0x1 +#define GPIO_FUNC95_IN_INV_SEL_S 5 + +/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC95_IN_SEL 0x0000001f +#define GPIO_FUNC95_IN_SEL_M ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S)) +#define GPIO_FUNC95_IN_SEL_V 0x1f +#define GPIO_FUNC95_IN_SEL_S 0 + +#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d4) + +/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG96_IN_SEL (BIT(6)) +#define GPIO_SIG96_IN_SEL_M (BIT(6)) +#define GPIO_SIG96_IN_SEL_V 0x1 +#define GPIO_SIG96_IN_SEL_S 6 + +/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC96_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC96_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC96_IN_INV_SEL_V 0x1 +#define GPIO_FUNC96_IN_INV_SEL_S 5 + +/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC96_IN_SEL 0x0000001f +#define GPIO_FUNC96_IN_SEL_M ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S)) +#define GPIO_FUNC96_IN_SEL_V 0x1f +#define GPIO_FUNC96_IN_SEL_S 0 + +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8) + +/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG97_IN_SEL (BIT(6)) +#define GPIO_SIG97_IN_SEL_M (BIT(6)) +#define GPIO_SIG97_IN_SEL_V 0x1 +#define GPIO_SIG97_IN_SEL_S 6 + +/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC97_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC97_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC97_IN_INV_SEL_V 0x1 +#define GPIO_FUNC97_IN_INV_SEL_S 5 + +/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC97_IN_SEL 0x0000001f +#define GPIO_FUNC97_IN_SEL_M ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S)) +#define GPIO_FUNC97_IN_SEL_V 0x1f +#define GPIO_FUNC97_IN_SEL_S 0 + +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc) + +/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG98_IN_SEL (BIT(6)) +#define GPIO_SIG98_IN_SEL_M (BIT(6)) +#define GPIO_SIG98_IN_SEL_V 0x1 +#define GPIO_SIG98_IN_SEL_S 6 + +/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC98_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC98_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC98_IN_INV_SEL_V 0x1 +#define GPIO_FUNC98_IN_INV_SEL_S 5 + +/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC98_IN_SEL 0x0000001f +#define GPIO_FUNC98_IN_SEL_M ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S)) +#define GPIO_FUNC98_IN_SEL_V 0x1f +#define GPIO_FUNC98_IN_SEL_S 0 + +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0) + +/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG99_IN_SEL (BIT(6)) +#define GPIO_SIG99_IN_SEL_M (BIT(6)) +#define GPIO_SIG99_IN_SEL_V 0x1 +#define GPIO_SIG99_IN_SEL_S 6 + +/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC99_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC99_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC99_IN_INV_SEL_V 0x1 +#define GPIO_FUNC99_IN_INV_SEL_S 5 + +/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC99_IN_SEL 0x0000001f +#define GPIO_FUNC99_IN_SEL_M ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S)) +#define GPIO_FUNC99_IN_SEL_V 0x1f +#define GPIO_FUNC99_IN_SEL_S 0 + +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4) + +/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG100_IN_SEL (BIT(6)) +#define GPIO_SIG100_IN_SEL_M (BIT(6)) +#define GPIO_SIG100_IN_SEL_V 0x1 +#define GPIO_SIG100_IN_SEL_S 6 + +/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC100_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC100_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC100_IN_INV_SEL_V 0x1 +#define GPIO_FUNC100_IN_INV_SEL_S 5 + +/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC100_IN_SEL 0x0000001f +#define GPIO_FUNC100_IN_SEL_M ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S)) +#define GPIO_FUNC100_IN_SEL_V 0x1f +#define GPIO_FUNC100_IN_SEL_S 0 + +#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8) + +/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG101_IN_SEL (BIT(6)) +#define GPIO_SIG101_IN_SEL_M (BIT(6)) +#define GPIO_SIG101_IN_SEL_V 0x1 +#define GPIO_SIG101_IN_SEL_S 6 + +/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC101_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC101_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC101_IN_INV_SEL_V 0x1 +#define GPIO_FUNC101_IN_INV_SEL_S 5 + +/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC101_IN_SEL 0x0000001f +#define GPIO_FUNC101_IN_SEL_M ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S)) +#define GPIO_FUNC101_IN_SEL_V 0x1f +#define GPIO_FUNC101_IN_SEL_S 0 + +#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) + +/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG102_IN_SEL (BIT(6)) +#define GPIO_SIG102_IN_SEL_M (BIT(6)) +#define GPIO_SIG102_IN_SEL_V 0x1 +#define GPIO_SIG102_IN_SEL_S 6 + +/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC102_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC102_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC102_IN_INV_SEL_V 0x1 +#define GPIO_FUNC102_IN_INV_SEL_S 5 + +/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC102_IN_SEL 0x0000001f +#define GPIO_FUNC102_IN_SEL_M ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S)) +#define GPIO_FUNC102_IN_SEL_V 0x1f +#define GPIO_FUNC102_IN_SEL_S 0 + +#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) + +/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG103_IN_SEL (BIT(6)) +#define GPIO_SIG103_IN_SEL_M (BIT(6)) +#define GPIO_SIG103_IN_SEL_V 0x1 +#define GPIO_SIG103_IN_SEL_S 6 + +/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC103_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC103_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC103_IN_INV_SEL_V 0x1 +#define GPIO_FUNC103_IN_INV_SEL_S 5 + +/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC103_IN_SEL 0x0000001f +#define GPIO_FUNC103_IN_SEL_M ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S)) +#define GPIO_FUNC103_IN_SEL_V 0x1f +#define GPIO_FUNC103_IN_SEL_S 0 + +#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) + +/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG104_IN_SEL (BIT(6)) +#define GPIO_SIG104_IN_SEL_M (BIT(6)) +#define GPIO_SIG104_IN_SEL_V 0x1 +#define GPIO_SIG104_IN_SEL_S 6 + +/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC104_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC104_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC104_IN_INV_SEL_V 0x1 +#define GPIO_FUNC104_IN_INV_SEL_S 5 + +/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC104_IN_SEL 0x0000001f +#define GPIO_FUNC104_IN_SEL_M ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S)) +#define GPIO_FUNC104_IN_SEL_V 0x1f +#define GPIO_FUNC104_IN_SEL_S 0 + +#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) + +/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG105_IN_SEL (BIT(6)) +#define GPIO_SIG105_IN_SEL_M (BIT(6)) +#define GPIO_SIG105_IN_SEL_V 0x1 +#define GPIO_SIG105_IN_SEL_S 6 + +/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC105_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC105_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC105_IN_INV_SEL_V 0x1 +#define GPIO_FUNC105_IN_INV_SEL_S 5 + +/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC105_IN_SEL 0x0000001f +#define GPIO_FUNC105_IN_SEL_M ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S)) +#define GPIO_FUNC105_IN_SEL_V 0x1f +#define GPIO_FUNC105_IN_SEL_S 0 + +#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) + +/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG106_IN_SEL (BIT(6)) +#define GPIO_SIG106_IN_SEL_M (BIT(6)) +#define GPIO_SIG106_IN_SEL_V 0x1 +#define GPIO_SIG106_IN_SEL_S 6 + +/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC106_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC106_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC106_IN_INV_SEL_V 0x1 +#define GPIO_FUNC106_IN_INV_SEL_S 5 + +/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC106_IN_SEL 0x0000001f +#define GPIO_FUNC106_IN_SEL_M ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S)) +#define GPIO_FUNC106_IN_SEL_V 0x1f +#define GPIO_FUNC106_IN_SEL_S 0 + +#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) + +/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG107_IN_SEL (BIT(6)) +#define GPIO_SIG107_IN_SEL_M (BIT(6)) +#define GPIO_SIG107_IN_SEL_V 0x1 +#define GPIO_SIG107_IN_SEL_S 6 + +/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC107_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC107_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC107_IN_INV_SEL_V 0x1 +#define GPIO_FUNC107_IN_INV_SEL_S 5 + +/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC107_IN_SEL 0x0000001f +#define GPIO_FUNC107_IN_SEL_M ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S)) +#define GPIO_FUNC107_IN_SEL_V 0x1f +#define GPIO_FUNC107_IN_SEL_S 0 + +#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) + +/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG108_IN_SEL (BIT(6)) +#define GPIO_SIG108_IN_SEL_M (BIT(6)) +#define GPIO_SIG108_IN_SEL_V 0x1 +#define GPIO_SIG108_IN_SEL_S 6 + +/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC108_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC108_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC108_IN_INV_SEL_V 0x1 +#define GPIO_FUNC108_IN_INV_SEL_S 5 + +/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC108_IN_SEL 0x0000001f +#define GPIO_FUNC108_IN_SEL_M ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S)) +#define GPIO_FUNC108_IN_SEL_V 0x1f +#define GPIO_FUNC108_IN_SEL_S 0 + +#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) + +/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG109_IN_SEL (BIT(6)) +#define GPIO_SIG109_IN_SEL_M (BIT(6)) +#define GPIO_SIG109_IN_SEL_V 0x1 +#define GPIO_SIG109_IN_SEL_S 6 + +/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC109_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC109_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC109_IN_INV_SEL_V 0x1 +#define GPIO_FUNC109_IN_INV_SEL_S 5 + +/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC109_IN_SEL 0x0000001f +#define GPIO_FUNC109_IN_SEL_M ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S)) +#define GPIO_FUNC109_IN_SEL_V 0x1f +#define GPIO_FUNC109_IN_SEL_S 0 + +#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c) + +/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG110_IN_SEL (BIT(6)) +#define GPIO_SIG110_IN_SEL_M (BIT(6)) +#define GPIO_SIG110_IN_SEL_V 0x1 +#define GPIO_SIG110_IN_SEL_S 6 + +/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC110_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC110_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC110_IN_INV_SEL_V 0x1 +#define GPIO_FUNC110_IN_INV_SEL_S 5 + +/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC110_IN_SEL 0x0000001f +#define GPIO_FUNC110_IN_SEL_M ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S)) +#define GPIO_FUNC110_IN_SEL_V 0x1f +#define GPIO_FUNC110_IN_SEL_S 0 + +#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) + +/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG111_IN_SEL (BIT(6)) +#define GPIO_SIG111_IN_SEL_M (BIT(6)) +#define GPIO_SIG111_IN_SEL_V 0x1 +#define GPIO_SIG111_IN_SEL_S 6 + +/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC111_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC111_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC111_IN_INV_SEL_V 0x1 +#define GPIO_FUNC111_IN_INV_SEL_S 5 + +/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC111_IN_SEL 0x0000001f +#define GPIO_FUNC111_IN_SEL_M ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S)) +#define GPIO_FUNC111_IN_SEL_V 0x1f +#define GPIO_FUNC111_IN_SEL_S 0 + +#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) + +/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG112_IN_SEL (BIT(6)) +#define GPIO_SIG112_IN_SEL_M (BIT(6)) +#define GPIO_SIG112_IN_SEL_V 0x1 +#define GPIO_SIG112_IN_SEL_S 6 + +/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC112_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC112_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC112_IN_INV_SEL_V 0x1 +#define GPIO_FUNC112_IN_INV_SEL_S 5 + +/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC112_IN_SEL 0x0000001f +#define GPIO_FUNC112_IN_SEL_M ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S)) +#define GPIO_FUNC112_IN_SEL_V 0x1f +#define GPIO_FUNC112_IN_SEL_S 0 + +#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) + +/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG113_IN_SEL (BIT(6)) +#define GPIO_SIG113_IN_SEL_M (BIT(6)) +#define GPIO_SIG113_IN_SEL_V 0x1 +#define GPIO_SIG113_IN_SEL_S 6 + +/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC113_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC113_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC113_IN_INV_SEL_V 0x1 +#define GPIO_FUNC113_IN_INV_SEL_S 5 + +/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC113_IN_SEL 0x0000001f +#define GPIO_FUNC113_IN_SEL_M ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S)) +#define GPIO_FUNC113_IN_SEL_V 0x1f +#define GPIO_FUNC113_IN_SEL_S 0 + +#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c) + +/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG114_IN_SEL (BIT(6)) +#define GPIO_SIG114_IN_SEL_M (BIT(6)) +#define GPIO_SIG114_IN_SEL_V 0x1 +#define GPIO_SIG114_IN_SEL_S 6 + +/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC114_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC114_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC114_IN_INV_SEL_V 0x1 +#define GPIO_FUNC114_IN_INV_SEL_S 5 + +/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC114_IN_SEL 0x0000001f +#define GPIO_FUNC114_IN_SEL_M ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S)) +#define GPIO_FUNC114_IN_SEL_V 0x1f +#define GPIO_FUNC114_IN_SEL_S 0 + +#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) + +/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG115_IN_SEL (BIT(6)) +#define GPIO_SIG115_IN_SEL_M (BIT(6)) +#define GPIO_SIG115_IN_SEL_V 0x1 +#define GPIO_SIG115_IN_SEL_S 6 + +/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC115_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC115_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC115_IN_INV_SEL_V 0x1 +#define GPIO_FUNC115_IN_INV_SEL_S 5 + +/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC115_IN_SEL 0x0000001f +#define GPIO_FUNC115_IN_SEL_M ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S)) +#define GPIO_FUNC115_IN_SEL_V 0x1f +#define GPIO_FUNC115_IN_SEL_S 0 + +#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) + +/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG116_IN_SEL (BIT(6)) +#define GPIO_SIG116_IN_SEL_M (BIT(6)) +#define GPIO_SIG116_IN_SEL_V 0x1 +#define GPIO_SIG116_IN_SEL_S 6 + +/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC116_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC116_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC116_IN_INV_SEL_V 0x1 +#define GPIO_FUNC116_IN_INV_SEL_S 5 + +/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC116_IN_SEL 0x0000001f +#define GPIO_FUNC116_IN_SEL_M ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S)) +#define GPIO_FUNC116_IN_SEL_V 0x1f +#define GPIO_FUNC116_IN_SEL_S 0 + +#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) + +/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG117_IN_SEL (BIT(6)) +#define GPIO_SIG117_IN_SEL_M (BIT(6)) +#define GPIO_SIG117_IN_SEL_V 0x1 +#define GPIO_SIG117_IN_SEL_S 6 + +/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC117_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC117_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC117_IN_INV_SEL_V 0x1 +#define GPIO_FUNC117_IN_INV_SEL_S 5 + +/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC117_IN_SEL 0x0000001f +#define GPIO_FUNC117_IN_SEL_M ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S)) +#define GPIO_FUNC117_IN_SEL_V 0x1f +#define GPIO_FUNC117_IN_SEL_S 0 + +#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c) + +/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG118_IN_SEL (BIT(6)) +#define GPIO_SIG118_IN_SEL_M (BIT(6)) +#define GPIO_SIG118_IN_SEL_V 0x1 +#define GPIO_SIG118_IN_SEL_S 6 + +/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC118_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC118_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC118_IN_INV_SEL_V 0x1 +#define GPIO_FUNC118_IN_INV_SEL_S 5 + +/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC118_IN_SEL 0x0000001f +#define GPIO_FUNC118_IN_SEL_M ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S)) +#define GPIO_FUNC118_IN_SEL_V 0x1f +#define GPIO_FUNC118_IN_SEL_S 0 + +#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) + +/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG119_IN_SEL (BIT(6)) +#define GPIO_SIG119_IN_SEL_M (BIT(6)) +#define GPIO_SIG119_IN_SEL_V 0x1 +#define GPIO_SIG119_IN_SEL_S 6 + +/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC119_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC119_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC119_IN_INV_SEL_V 0x1 +#define GPIO_FUNC119_IN_INV_SEL_S 5 + +/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC119_IN_SEL 0x0000001f +#define GPIO_FUNC119_IN_SEL_M ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S)) +#define GPIO_FUNC119_IN_SEL_V 0x1f +#define GPIO_FUNC119_IN_SEL_S 0 + +#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) + +/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG120_IN_SEL (BIT(6)) +#define GPIO_SIG120_IN_SEL_M (BIT(6)) +#define GPIO_SIG120_IN_SEL_V 0x1 +#define GPIO_SIG120_IN_SEL_S 6 + +/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC120_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC120_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC120_IN_INV_SEL_V 0x1 +#define GPIO_FUNC120_IN_INV_SEL_S 5 + +/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC120_IN_SEL 0x0000001f +#define GPIO_FUNC120_IN_SEL_M ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S)) +#define GPIO_FUNC120_IN_SEL_V 0x1f +#define GPIO_FUNC120_IN_SEL_S 0 + +#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) + +/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG121_IN_SEL (BIT(6)) +#define GPIO_SIG121_IN_SEL_M (BIT(6)) +#define GPIO_SIG121_IN_SEL_V 0x1 +#define GPIO_SIG121_IN_SEL_S 6 + +/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC121_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC121_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC121_IN_INV_SEL_V 0x1 +#define GPIO_FUNC121_IN_INV_SEL_S 5 + +/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC121_IN_SEL 0x0000001f +#define GPIO_FUNC121_IN_SEL_M ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S)) +#define GPIO_FUNC121_IN_SEL_V 0x1f +#define GPIO_FUNC121_IN_SEL_S 0 + +#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c) + +/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG122_IN_SEL (BIT(6)) +#define GPIO_SIG122_IN_SEL_M (BIT(6)) +#define GPIO_SIG122_IN_SEL_V 0x1 +#define GPIO_SIG122_IN_SEL_S 6 + +/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC122_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC122_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC122_IN_INV_SEL_V 0x1 +#define GPIO_FUNC122_IN_INV_SEL_S 5 + +/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC122_IN_SEL 0x0000001f +#define GPIO_FUNC122_IN_SEL_M ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S)) +#define GPIO_FUNC122_IN_SEL_V 0x1f +#define GPIO_FUNC122_IN_SEL_S 0 + +#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) + +/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG123_IN_SEL (BIT(6)) +#define GPIO_SIG123_IN_SEL_M (BIT(6)) +#define GPIO_SIG123_IN_SEL_V 0x1 +#define GPIO_SIG123_IN_SEL_S 6 + +/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC123_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC123_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC123_IN_INV_SEL_V 0x1 +#define GPIO_FUNC123_IN_INV_SEL_S 5 + +/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC123_IN_SEL 0x0000001f +#define GPIO_FUNC123_IN_SEL_M ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S)) +#define GPIO_FUNC123_IN_SEL_V 0x1f +#define GPIO_FUNC123_IN_SEL_S 0 + +#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) + +/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG124_IN_SEL (BIT(6)) +#define GPIO_SIG124_IN_SEL_M (BIT(6)) +#define GPIO_SIG124_IN_SEL_V 0x1 +#define GPIO_SIG124_IN_SEL_S 6 + +/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC124_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC124_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC124_IN_INV_SEL_V 0x1 +#define GPIO_FUNC124_IN_INV_SEL_S 5 + +/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ +#define GPIO_FUNC124_IN_SEL 0x0000001f +#define GPIO_FUNC124_IN_SEL_M ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S)) +#define GPIO_FUNC124_IN_SEL_V 0x1f +#define GPIO_FUNC124_IN_SEL_S 0 + +#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) + +/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG125_IN_SEL (BIT(6)) +#define GPIO_SIG125_IN_SEL_M (BIT(6)) +#define GPIO_SIG125_IN_SEL_V 0x1 +#define GPIO_SIG125_IN_SEL_S 6 + +/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC125_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC125_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC125_IN_INV_SEL_V 0x1 +#define GPIO_FUNC125_IN_INV_SEL_S 5 + +/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC125_IN_SEL 0x0000001f +#define GPIO_FUNC125_IN_SEL_M ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S)) +#define GPIO_FUNC125_IN_SEL_V 0x1f +#define GPIO_FUNC125_IN_SEL_S 0 + +#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c) + +/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG126_IN_SEL (BIT(6)) +#define GPIO_SIG126_IN_SEL_M (BIT(6)) +#define GPIO_SIG126_IN_SEL_V 0x1 +#define GPIO_SIG126_IN_SEL_S 6 + +/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC126_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC126_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC126_IN_INV_SEL_V 0x1 +#define GPIO_FUNC126_IN_INV_SEL_S 5 + +/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC126_IN_SEL 0x0000001f +#define GPIO_FUNC126_IN_SEL_M ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S)) +#define GPIO_FUNC126_IN_SEL_V 0x1f +#define GPIO_FUNC126_IN_SEL_S 0 + +#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) + +/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ + +#define GPIO_SIG127_IN_SEL (BIT(6)) +#define GPIO_SIG127_IN_SEL_M (BIT(6)) +#define GPIO_SIG127_IN_SEL_V 0x1 +#define GPIO_SIG127_IN_SEL_S 6 + +/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ + +#define GPIO_FUNC127_IN_INV_SEL (BIT(5)) +#define GPIO_FUNC127_IN_INV_SEL_M (BIT(5)) +#define GPIO_FUNC127_IN_INV_SEL_V 0x1 +#define GPIO_FUNC127_IN_INV_SEL_S 5 + +/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ + +#define GPIO_FUNC127_IN_SEL 0x0000001f +#define GPIO_FUNC127_IN_SEL_M ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S)) +#define GPIO_FUNC127_IN_SEL_V 0x1f +#define GPIO_FUNC127_IN_SEL_S 0 + +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) + +/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC0_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC0_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC0_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC0_OEN_INV_SEL_S 10 + +/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC0_OEN_SEL (BIT(9)) +#define GPIO_FUNC0_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC0_OEN_SEL_V 0x1 +#define GPIO_FUNC0_OEN_SEL_S 9 + +/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC0_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC0_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC0_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC0_OUT_INV_SEL_S 8 + +/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC0_OUT_SEL 0x000000ff +#define GPIO_FUNC0_OUT_SEL_M ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S)) +#define GPIO_FUNC0_OUT_SEL_V 0xff +#define GPIO_FUNC0_OUT_SEL_S 0 + +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558) + +/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC1_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC1_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC1_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC1_OEN_INV_SEL_S 10 + +/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC1_OEN_SEL (BIT(9)) +#define GPIO_FUNC1_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC1_OEN_SEL_V 0x1 +#define GPIO_FUNC1_OEN_SEL_S 9 + +/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC1_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC1_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC1_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC1_OUT_INV_SEL_S 8 + +/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC1_OUT_SEL 0x000000ff +#define GPIO_FUNC1_OUT_SEL_M ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S)) +#define GPIO_FUNC1_OUT_SEL_V 0xff +#define GPIO_FUNC1_OUT_SEL_S 0 + +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c) + +/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC2_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC2_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC2_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC2_OEN_INV_SEL_S 10 + +/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC2_OEN_SEL (BIT(9)) +#define GPIO_FUNC2_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC2_OEN_SEL_V 0x1 +#define GPIO_FUNC2_OEN_SEL_S 9 + +/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC2_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC2_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC2_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC2_OUT_INV_SEL_S 8 + +/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC2_OUT_SEL 0x000000ff +#define GPIO_FUNC2_OUT_SEL_M ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S)) +#define GPIO_FUNC2_OUT_SEL_V 0xff +#define GPIO_FUNC2_OUT_SEL_S 0 + +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560) + +/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC3_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC3_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC3_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC3_OEN_INV_SEL_S 10 + +/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC3_OEN_SEL (BIT(9)) +#define GPIO_FUNC3_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC3_OEN_SEL_V 0x1 +#define GPIO_FUNC3_OEN_SEL_S 9 + +/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC3_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC3_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC3_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC3_OUT_INV_SEL_S 8 + +/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC3_OUT_SEL 0x000000ff +#define GPIO_FUNC3_OUT_SEL_M ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S)) +#define GPIO_FUNC3_OUT_SEL_V 0xff +#define GPIO_FUNC3_OUT_SEL_S 0 + +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564) + +/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC4_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC4_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC4_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC4_OEN_INV_SEL_S 10 + +/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC4_OEN_SEL (BIT(9)) +#define GPIO_FUNC4_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC4_OEN_SEL_V 0x1 +#define GPIO_FUNC4_OEN_SEL_S 9 + +/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC4_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC4_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC4_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC4_OUT_INV_SEL_S 8 + +/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC4_OUT_SEL 0x000000ff +#define GPIO_FUNC4_OUT_SEL_M ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S)) +#define GPIO_FUNC4_OUT_SEL_V 0xff +#define GPIO_FUNC4_OUT_SEL_S 0 + +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568) + +/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC5_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC5_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC5_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC5_OEN_INV_SEL_S 10 + +/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC5_OEN_SEL (BIT(9)) +#define GPIO_FUNC5_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC5_OEN_SEL_V 0x1 +#define GPIO_FUNC5_OEN_SEL_S 9 + +/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC5_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC5_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC5_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC5_OUT_INV_SEL_S 8 + +/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC5_OUT_SEL 0x000000ff +#define GPIO_FUNC5_OUT_SEL_M ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S)) +#define GPIO_FUNC5_OUT_SEL_V 0xff +#define GPIO_FUNC5_OUT_SEL_S 0 + +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c) + +/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC6_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC6_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC6_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC6_OEN_INV_SEL_S 10 + +/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC6_OEN_SEL (BIT(9)) +#define GPIO_FUNC6_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC6_OEN_SEL_V 0x1 +#define GPIO_FUNC6_OEN_SEL_S 9 + +/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC6_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC6_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC6_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC6_OUT_INV_SEL_S 8 + +/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC6_OUT_SEL 0x000000ff +#define GPIO_FUNC6_OUT_SEL_M ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S)) +#define GPIO_FUNC6_OUT_SEL_V 0xff +#define GPIO_FUNC6_OUT_SEL_S 0 + +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570) + +/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC7_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC7_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC7_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC7_OEN_INV_SEL_S 10 + +/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC7_OEN_SEL (BIT(9)) +#define GPIO_FUNC7_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC7_OEN_SEL_V 0x1 +#define GPIO_FUNC7_OEN_SEL_S 9 + +/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC7_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC7_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC7_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC7_OUT_INV_SEL_S 8 + +/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC7_OUT_SEL 0x000000ff +#define GPIO_FUNC7_OUT_SEL_M ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S)) +#define GPIO_FUNC7_OUT_SEL_V 0xff +#define GPIO_FUNC7_OUT_SEL_S 0 + +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574) + +/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC8_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC8_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC8_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC8_OEN_INV_SEL_S 10 + +/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC8_OEN_SEL (BIT(9)) +#define GPIO_FUNC8_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC8_OEN_SEL_V 0x1 +#define GPIO_FUNC8_OEN_SEL_S 9 + +/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC8_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC8_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC8_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC8_OUT_INV_SEL_S 8 + +/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC8_OUT_SEL 0x000000ff +#define GPIO_FUNC8_OUT_SEL_M ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S)) +#define GPIO_FUNC8_OUT_SEL_V 0xff +#define GPIO_FUNC8_OUT_SEL_S 0 + +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578) + +/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC9_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC9_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC9_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC9_OEN_INV_SEL_S 10 + +/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC9_OEN_SEL (BIT(9)) +#define GPIO_FUNC9_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC9_OEN_SEL_V 0x1 +#define GPIO_FUNC9_OEN_SEL_S 9 + +/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC9_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC9_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC9_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC9_OUT_INV_SEL_S 8 + +/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC9_OUT_SEL 0x000000ff +#define GPIO_FUNC9_OUT_SEL_M ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S)) +#define GPIO_FUNC9_OUT_SEL_V 0xff +#define GPIO_FUNC9_OUT_SEL_S 0 + +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c) + +/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC10_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC10_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC10_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC10_OEN_INV_SEL_S 10 + +/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC10_OEN_SEL (BIT(9)) +#define GPIO_FUNC10_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC10_OEN_SEL_V 0x1 +#define GPIO_FUNC10_OEN_SEL_S 9 + +/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC10_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC10_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC10_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC10_OUT_INV_SEL_S 8 + +/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC10_OUT_SEL 0x000000ff +#define GPIO_FUNC10_OUT_SEL_M ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S)) +#define GPIO_FUNC10_OUT_SEL_V 0xff +#define GPIO_FUNC10_OUT_SEL_S 0 + +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580) + +/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC11_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC11_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC11_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC11_OEN_INV_SEL_S 10 + +/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC11_OEN_SEL (BIT(9)) +#define GPIO_FUNC11_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC11_OEN_SEL_V 0x1 +#define GPIO_FUNC11_OEN_SEL_S 9 + +/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC11_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC11_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC11_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC11_OUT_INV_SEL_S 8 + +/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC11_OUT_SEL 0x000000ff +#define GPIO_FUNC11_OUT_SEL_M ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S)) +#define GPIO_FUNC11_OUT_SEL_V 0xff +#define GPIO_FUNC11_OUT_SEL_S 0 + +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584) + +/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC12_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC12_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC12_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC12_OEN_INV_SEL_S 10 + +/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC12_OEN_SEL (BIT(9)) +#define GPIO_FUNC12_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC12_OEN_SEL_V 0x1 +#define GPIO_FUNC12_OEN_SEL_S 9 + +/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC12_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC12_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC12_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC12_OUT_INV_SEL_S 8 + +/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC12_OUT_SEL 0x000000ff +#define GPIO_FUNC12_OUT_SEL_M ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S)) +#define GPIO_FUNC12_OUT_SEL_V 0xff +#define GPIO_FUNC12_OUT_SEL_S 0 + +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588) + +/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC13_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC13_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC13_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC13_OEN_INV_SEL_S 10 + +/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC13_OEN_SEL (BIT(9)) +#define GPIO_FUNC13_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC13_OEN_SEL_V 0x1 +#define GPIO_FUNC13_OEN_SEL_S 9 + +/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC13_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC13_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC13_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC13_OUT_INV_SEL_S 8 + +/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC13_OUT_SEL 0x000000ff +#define GPIO_FUNC13_OUT_SEL_M ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S)) +#define GPIO_FUNC13_OUT_SEL_V 0xff +#define GPIO_FUNC13_OUT_SEL_S 0 + +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c) + +/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC14_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC14_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC14_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC14_OEN_INV_SEL_S 10 + +/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC14_OEN_SEL (BIT(9)) +#define GPIO_FUNC14_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC14_OEN_SEL_V 0x1 +#define GPIO_FUNC14_OEN_SEL_S 9 + +/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC14_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC14_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC14_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC14_OUT_INV_SEL_S 8 + +/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC14_OUT_SEL 0x000000ff +#define GPIO_FUNC14_OUT_SEL_M ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S)) +#define GPIO_FUNC14_OUT_SEL_V 0xff +#define GPIO_FUNC14_OUT_SEL_S 0 + +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590) + +/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC15_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC15_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC15_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC15_OEN_INV_SEL_S 10 + +/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC15_OEN_SEL (BIT(9)) +#define GPIO_FUNC15_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC15_OEN_SEL_V 0x1 +#define GPIO_FUNC15_OEN_SEL_S 9 + +/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC15_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC15_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC15_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC15_OUT_INV_SEL_S 8 + +/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC15_OUT_SEL 0x000000ff +#define GPIO_FUNC15_OUT_SEL_M ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S)) +#define GPIO_FUNC15_OUT_SEL_V 0xff +#define GPIO_FUNC15_OUT_SEL_S 0 + +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594) + +/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC16_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC16_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC16_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC16_OEN_INV_SEL_S 10 + +/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC16_OEN_SEL (BIT(9)) +#define GPIO_FUNC16_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC16_OEN_SEL_V 0x1 +#define GPIO_FUNC16_OEN_SEL_S 9 + +/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC16_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC16_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC16_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC16_OUT_INV_SEL_S 8 + +/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC16_OUT_SEL 0x000000ff +#define GPIO_FUNC16_OUT_SEL_M ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S)) +#define GPIO_FUNC16_OUT_SEL_V 0xff +#define GPIO_FUNC16_OUT_SEL_S 0 + +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598) + +/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC17_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC17_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC17_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC17_OEN_INV_SEL_S 10 + +/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC17_OEN_SEL (BIT(9)) +#define GPIO_FUNC17_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC17_OEN_SEL_V 0x1 +#define GPIO_FUNC17_OEN_SEL_S 9 + +/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC17_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC17_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC17_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC17_OUT_INV_SEL_S 8 + +/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC17_OUT_SEL 0x000000ff +#define GPIO_FUNC17_OUT_SEL_M ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S)) +#define GPIO_FUNC17_OUT_SEL_V 0xff +#define GPIO_FUNC17_OUT_SEL_S 0 + +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c) + +/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC18_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC18_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC18_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC18_OEN_INV_SEL_S 10 + +/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC18_OEN_SEL (BIT(9)) +#define GPIO_FUNC18_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC18_OEN_SEL_V 0x1 +#define GPIO_FUNC18_OEN_SEL_S 9 + +/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC18_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC18_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC18_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC18_OUT_INV_SEL_S 8 + +/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC18_OUT_SEL 0x000000ff +#define GPIO_FUNC18_OUT_SEL_M ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S)) +#define GPIO_FUNC18_OUT_SEL_V 0xff +#define GPIO_FUNC18_OUT_SEL_S 0 + +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0) + +/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC19_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC19_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC19_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC19_OEN_INV_SEL_S 10 + +/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC19_OEN_SEL (BIT(9)) +#define GPIO_FUNC19_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC19_OEN_SEL_V 0x1 +#define GPIO_FUNC19_OEN_SEL_S 9 + +/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC19_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC19_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC19_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC19_OUT_INV_SEL_S 8 + +/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC19_OUT_SEL 0x000000ff +#define GPIO_FUNC19_OUT_SEL_M ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S)) +#define GPIO_FUNC19_OUT_SEL_V 0xff +#define GPIO_FUNC19_OUT_SEL_S 0 + +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4) + +/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC20_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC20_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC20_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC20_OEN_INV_SEL_S 10 + +/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC20_OEN_SEL (BIT(9)) +#define GPIO_FUNC20_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC20_OEN_SEL_V 0x1 +#define GPIO_FUNC20_OEN_SEL_S 9 + +/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC20_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC20_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC20_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC20_OUT_INV_SEL_S 8 + +/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC20_OUT_SEL 0x000000ff +#define GPIO_FUNC20_OUT_SEL_M ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S)) +#define GPIO_FUNC20_OUT_SEL_V 0xff +#define GPIO_FUNC20_OUT_SEL_S 0 + +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8) + +/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC21_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC21_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC21_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC21_OEN_INV_SEL_S 10 + +/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC21_OEN_SEL (BIT(9)) +#define GPIO_FUNC21_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC21_OEN_SEL_V 0x1 +#define GPIO_FUNC21_OEN_SEL_S 9 + +/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC21_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC21_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC21_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC21_OUT_INV_SEL_S 8 + +/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC21_OUT_SEL 0x000000ff +#define GPIO_FUNC21_OUT_SEL_M ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S)) +#define GPIO_FUNC21_OUT_SEL_V 0xff +#define GPIO_FUNC21_OUT_SEL_S 0 + +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac) + +/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC22_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC22_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC22_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC22_OEN_INV_SEL_S 10 + +/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC22_OEN_SEL (BIT(9)) +#define GPIO_FUNC22_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC22_OEN_SEL_V 0x1 +#define GPIO_FUNC22_OEN_SEL_S 9 + +/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC22_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC22_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC22_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC22_OUT_INV_SEL_S 8 + +/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC22_OUT_SEL 0x000000ff +#define GPIO_FUNC22_OUT_SEL_M ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S)) +#define GPIO_FUNC22_OUT_SEL_V 0xff +#define GPIO_FUNC22_OUT_SEL_S 0 + +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0) + +/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC23_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC23_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC23_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC23_OEN_INV_SEL_S 10 + +/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC23_OEN_SEL (BIT(9)) +#define GPIO_FUNC23_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC23_OEN_SEL_V 0x1 +#define GPIO_FUNC23_OEN_SEL_S 9 + +/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC23_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC23_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC23_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC23_OUT_INV_SEL_S 8 + +/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC23_OUT_SEL 0x000000ff +#define GPIO_FUNC23_OUT_SEL_M ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S)) +#define GPIO_FUNC23_OUT_SEL_V 0xff +#define GPIO_FUNC23_OUT_SEL_S 0 + +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4) + +/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC24_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC24_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC24_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC24_OEN_INV_SEL_S 10 + +/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC24_OEN_SEL (BIT(9)) +#define GPIO_FUNC24_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC24_OEN_SEL_V 0x1 +#define GPIO_FUNC24_OEN_SEL_S 9 + +/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC24_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC24_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC24_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC24_OUT_INV_SEL_S 8 + +/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC24_OUT_SEL 0x000000ff +#define GPIO_FUNC24_OUT_SEL_M ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S)) +#define GPIO_FUNC24_OUT_SEL_V 0xff +#define GPIO_FUNC24_OUT_SEL_S 0 + +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8) + +/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ + +#define GPIO_FUNC25_OEN_INV_SEL (BIT(10)) +#define GPIO_FUNC25_OEN_INV_SEL_M (BIT(10)) +#define GPIO_FUNC25_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC25_OEN_INV_SEL_S 10 + +/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ + +#define GPIO_FUNC25_OEN_SEL (BIT(9)) +#define GPIO_FUNC25_OEN_SEL_M (BIT(9)) +#define GPIO_FUNC25_OEN_SEL_V 0x1 +#define GPIO_FUNC25_OEN_SEL_S 9 + +/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ + +#define GPIO_FUNC25_OUT_INV_SEL (BIT(8)) +#define GPIO_FUNC25_OUT_INV_SEL_M (BIT(8)) +#define GPIO_FUNC25_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC25_OUT_INV_SEL_S 8 + +/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ + +#define GPIO_FUNC25_OUT_SEL 0x000000ff +#define GPIO_FUNC25_OUT_SEL_M ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S)) +#define GPIO_FUNC25_OUT_SEL_V 0xff +#define GPIO_FUNC25_OUT_SEL_S 0 + +#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62c) + +/* GPIO_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ + +#define GPIO_CLK_EN (BIT(0)) +#define GPIO_CLK_EN_M (BIT(0)) +#define GPIO_CLK_EN_V 0x1 +#define GPIO_CLK_EN_S 0 + +#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x6fc) + +/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006130 ; */ + +#define GPIO_DATE 0x0fffffff +#define GPIO_DATE_M ((GPIO_DATE_V)<<(GPIO_DATE_S)) +#define GPIO_DATE_V 0xfffffff +#define GPIO_DATE_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_GPIO_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio_sigmap.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_gpio_sigmap.h similarity index 96% rename from arch/risc-v/src/esp32c3/hardware/esp32c3_gpio_sigmap.h rename to arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_gpio_sigmap.h index 17dc40e8de985..19bb79905c585 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio_sigmap.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_gpio_sigmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_gpio_sigmap.h + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_gpio_sigmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_GPIO_SIGMAP_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_GPIO_SIGMAP_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_GPIO_SIGMAP_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_GPIO_SIGMAP_H /**************************************************************************** * Pre-processor Definitions @@ -193,4 +193,4 @@ #define SIG_GPIO_OUT_IDX 128 #define GPIO_MAP_DATE_IDX 0x2006130 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_GPIO_SIGMAP_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_GPIO_SIGMAP_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_i2c.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_i2c.h new file mode 100644 index 0000000000000..3552e17b8728a --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_i2c.h @@ -0,0 +1,1226 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_i2c.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_I2C_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_I2C_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0) + +/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ + +#define I2C_SCL_LOW_PERIOD 0x000001FF +#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S)) +#define I2C_SCL_LOW_PERIOD_V 0x1FF +#define I2C_SCL_LOW_PERIOD_S 0 + +#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x4) + +/* I2C_ADDR_BROADCASTING_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ + +#define I2C_ADDR_BROADCASTING_EN (BIT(14)) +#define I2C_ADDR_BROADCASTING_EN_M (BIT(14)) +#define I2C_ADDR_BROADCASTING_EN_V 0x1 +#define I2C_ADDR_BROADCASTING_EN_S 14 + +/* I2C_ADDR_10BIT_RW_CHECK_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ + +#define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13)) +#define I2C_ADDR_10BIT_RW_CHECK_EN_M (BIT(13)) +#define I2C_ADDR_10BIT_RW_CHECK_EN_V 0x1 +#define I2C_ADDR_10BIT_RW_CHECK_EN_S 13 + +/* I2C_SLV_TX_AUTO_START_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +#define I2C_SLV_TX_AUTO_START_EN (BIT(12)) +#define I2C_SLV_TX_AUTO_START_EN_M (BIT(12)) +#define I2C_SLV_TX_AUTO_START_EN_V 0x1 +#define I2C_SLV_TX_AUTO_START_EN_S 12 + +/* I2C_CONF_UPGATE : WT ;bitpos:[11] ;default: 1'b0 ; */ + +#define I2C_CONF_UPGATE (BIT(11)) +#define I2C_CONF_UPGATE_M (BIT(11)) +#define I2C_CONF_UPGATE_V 0x1 +#define I2C_CONF_UPGATE_S 11 + +/* I2C_FSM_RST : WT ;bitpos:[10] ;default: 1'b0 ; */ + +#define I2C_FSM_RST (BIT(10)) +#define I2C_FSM_RST_M (BIT(10)) +#define I2C_FSM_RST_V 0x1 +#define I2C_FSM_RST_S 10 + +/* I2C_ARBITRATION_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ + +#define I2C_ARBITRATION_EN (BIT(9)) +#define I2C_ARBITRATION_EN_M (BIT(9)) +#define I2C_ARBITRATION_EN_V 0x1 +#define I2C_ARBITRATION_EN_S 9 + +/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +#define I2C_CLK_EN (BIT(8)) +#define I2C_CLK_EN_M (BIT(8)) +#define I2C_CLK_EN_V 0x1 +#define I2C_CLK_EN_S 8 + +/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */ + +#define I2C_RX_LSB_FIRST (BIT(7)) +#define I2C_RX_LSB_FIRST_M (BIT(7)) +#define I2C_RX_LSB_FIRST_V 0x1 +#define I2C_RX_LSB_FIRST_S 7 + +/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +#define I2C_TX_LSB_FIRST (BIT(6)) +#define I2C_TX_LSB_FIRST_M (BIT(6)) +#define I2C_TX_LSB_FIRST_V 0x1 +#define I2C_TX_LSB_FIRST_S 6 + +/* I2C_TRANS_START : WT ;bitpos:[5] ;default: 1'b0 ; */ + +#define I2C_TRANS_START (BIT(5)) +#define I2C_TRANS_START_M (BIT(5)) +#define I2C_TRANS_START_V 0x1 +#define I2C_TRANS_START_S 5 + +/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +#define I2C_MS_MODE (BIT(4)) +#define I2C_MS_MODE_M (BIT(4)) +#define I2C_MS_MODE_V 0x1 +#define I2C_MS_MODE_S 4 + +/* I2C_RX_FULL_ACK_LEVEL : R/W ;bitpos:[3] ;default: 1'b1 ; */ + +#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) +#define I2C_RX_FULL_ACK_LEVEL_M (BIT(3)) +#define I2C_RX_FULL_ACK_LEVEL_V 0x1 +#define I2C_RX_FULL_ACK_LEVEL_S 3 + +/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_V 0x1 +#define I2C_SAMPLE_SCL_LEVEL_S 2 + +/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */ + +#define I2C_SCL_FORCE_OUT (BIT(1)) +#define I2C_SCL_FORCE_OUT_M (BIT(1)) +#define I2C_SCL_FORCE_OUT_V 0x1 +#define I2C_SCL_FORCE_OUT_S 1 + +/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */ + +#define I2C_SDA_FORCE_OUT (BIT(0)) +#define I2C_SDA_FORCE_OUT_M (BIT(0)) +#define I2C_SDA_FORCE_OUT_V 0x1 +#define I2C_SDA_FORCE_OUT_S 0 + +#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x8) + +/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ + +#define I2C_SCL_STATE_LAST 0x00000007 +#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S)) +#define I2C_SCL_STATE_LAST_V 0x7 +#define I2C_SCL_STATE_LAST_S 28 + +/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ + +#define I2C_SCL_MAIN_STATE_LAST 0x00000007 +#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S)) +#define I2C_SCL_MAIN_STATE_LAST_V 0x7 +#define I2C_SCL_MAIN_STATE_LAST_S 24 + +/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */ + +#define I2C_TXFIFO_CNT 0x0000003F +#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S)) +#define I2C_TXFIFO_CNT_V 0x3F +#define I2C_TXFIFO_CNT_S 18 + +/* I2C_STRETCH_CAUSE : RO ;bitpos:[15:14] ;default: 2'h3 ; */ + +#define I2C_STRETCH_CAUSE 0x00000003 +#define I2C_STRETCH_CAUSE_M ((I2C_STRETCH_CAUSE_V)<<(I2C_STRETCH_CAUSE_S)) +#define I2C_STRETCH_CAUSE_V 0x3 +#define I2C_STRETCH_CAUSE_S 14 + +/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */ + +#define I2C_RXFIFO_CNT 0x0000003F +#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S)) +#define I2C_RXFIFO_CNT_V 0x3F +#define I2C_RXFIFO_CNT_S 8 + +/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */ + +#define I2C_SLAVE_ADDRESSED (BIT(5)) +#define I2C_SLAVE_ADDRESSED_M (BIT(5)) +#define I2C_SLAVE_ADDRESSED_V 0x1 +#define I2C_SLAVE_ADDRESSED_S 5 + +/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */ + +#define I2C_BUS_BUSY (BIT(4)) +#define I2C_BUS_BUSY_M (BIT(4)) +#define I2C_BUS_BUSY_V 0x1 +#define I2C_BUS_BUSY_S 4 + +/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */ + +#define I2C_ARB_LOST (BIT(3)) +#define I2C_ARB_LOST_M (BIT(3)) +#define I2C_ARB_LOST_V 0x1 +#define I2C_ARB_LOST_S 3 + +/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ + +#define I2C_SLAVE_RW (BIT(1)) +#define I2C_SLAVE_RW_M (BIT(1)) +#define I2C_SLAVE_RW_V 0x1 +#define I2C_SLAVE_RW_S 1 + +/* I2C_RESP_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ + +#define I2C_RESP_REC (BIT(0)) +#define I2C_RESP_REC_M (BIT(0)) +#define I2C_RESP_REC_V 0x1 +#define I2C_RESP_REC_S 0 + +#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0xC) + +/* I2C_TIME_OUT_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +#define I2C_TIME_OUT_EN (BIT(5)) +#define I2C_TIME_OUT_EN_M (BIT(5)) +#define I2C_TIME_OUT_EN_V 0x1 +#define I2C_TIME_OUT_EN_S 5 + +/* I2C_TIME_OUT_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ + +#define I2C_TIME_OUT_REG 0x0000001F +#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S)) +#define I2C_TIME_OUT_REG_V 0x1F +#define I2C_TIME_OUT_REG_S 0 + +#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x10) + +/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ + +#define I2C_ADDR_10BIT_EN (BIT(31)) +#define I2C_ADDR_10BIT_EN_M (BIT(31)) +#define I2C_ADDR_10BIT_EN_V 0x1 +#define I2C_ADDR_10BIT_EN_S 31 + +/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ + +#define I2C_SLAVE_ADDR 0x00007FFF +#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S)) +#define I2C_SLAVE_ADDR_V 0x7FFF +#define I2C_SLAVE_ADDR_S 0 + +#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x14) + +/* I2C_SLAVE_RW_POINT : RO ;bitpos:[29:22] ;default: 8'b0 ; */ + +#define I2C_SLAVE_RW_POINT 0x000000FF +#define I2C_SLAVE_RW_POINT_M ((I2C_SLAVE_RW_POINT_V)<<(I2C_SLAVE_RW_POINT_S)) +#define I2C_SLAVE_RW_POINT_V 0xFF +#define I2C_SLAVE_RW_POINT_S 22 + +/* I2C_TXFIFO_WADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */ + +#define I2C_TXFIFO_WADDR 0x0000001F +#define I2C_TXFIFO_WADDR_M ((I2C_TXFIFO_WADDR_V)<<(I2C_TXFIFO_WADDR_S)) +#define I2C_TXFIFO_WADDR_V 0x1F +#define I2C_TXFIFO_WADDR_S 15 + +/* I2C_TXFIFO_RADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */ + +#define I2C_TXFIFO_RADDR 0x0000001F +#define I2C_TXFIFO_RADDR_M ((I2C_TXFIFO_RADDR_V)<<(I2C_TXFIFO_RADDR_S)) +#define I2C_TXFIFO_RADDR_V 0x1F +#define I2C_TXFIFO_RADDR_S 10 + +/* I2C_RXFIFO_WADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */ + +#define I2C_RXFIFO_WADDR 0x0000001F +#define I2C_RXFIFO_WADDR_M ((I2C_RXFIFO_WADDR_V)<<(I2C_RXFIFO_WADDR_S)) +#define I2C_RXFIFO_WADDR_V 0x1F +#define I2C_RXFIFO_WADDR_S 5 + +/* I2C_RXFIFO_RADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */ + +#define I2C_RXFIFO_RADDR 0x0000001F +#define I2C_RXFIFO_RADDR_M ((I2C_RXFIFO_RADDR_V)<<(I2C_RXFIFO_RADDR_S)) +#define I2C_RXFIFO_RADDR_V 0x1F +#define I2C_RXFIFO_RADDR_S 0 + +#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x18) + +/* I2C_FIFO_PRT_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ + +#define I2C_FIFO_PRT_EN (BIT(14)) +#define I2C_FIFO_PRT_EN_M (BIT(14)) +#define I2C_FIFO_PRT_EN_V 0x1 +#define I2C_FIFO_PRT_EN_S 14 + +/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ + +#define I2C_TX_FIFO_RST (BIT(13)) +#define I2C_TX_FIFO_RST_M (BIT(13)) +#define I2C_TX_FIFO_RST_V 0x1 +#define I2C_TX_FIFO_RST_S 13 + +/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +#define I2C_RX_FIFO_RST (BIT(12)) +#define I2C_RX_FIFO_RST_M (BIT(12)) +#define I2C_RX_FIFO_RST_V 0x1 +#define I2C_RX_FIFO_RST_S 12 + +/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ + +#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_V 0x1 +#define I2C_FIFO_ADDR_CFG_EN_S 11 + +/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ + +#define I2C_NONFIFO_EN (BIT(10)) +#define I2C_NONFIFO_EN_M (BIT(10)) +#define I2C_NONFIFO_EN_V 0x1 +#define I2C_NONFIFO_EN_S 10 + +/* I2C_TXFIFO_WM_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ + +#define I2C_TXFIFO_WM_THRHD 0x0000001F +#define I2C_TXFIFO_WM_THRHD_M ((I2C_TXFIFO_WM_THRHD_V)<<(I2C_TXFIFO_WM_THRHD_S)) +#define I2C_TXFIFO_WM_THRHD_V 0x1F +#define I2C_TXFIFO_WM_THRHD_S 5 + +/* I2C_RXFIFO_WM_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */ + +#define I2C_RXFIFO_WM_THRHD 0x0000001F +#define I2C_RXFIFO_WM_THRHD_M ((I2C_RXFIFO_WM_THRHD_V)<<(I2C_RXFIFO_WM_THRHD_S)) +#define I2C_RXFIFO_WM_THRHD_V 0x1F +#define I2C_RXFIFO_WM_THRHD_S 0 + +#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x1C) + +/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */ + +#define I2C_FIFO_RDATA 0x000000FF +#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S)) +#define I2C_FIFO_RDATA_V 0xFF +#define I2C_FIFO_RDATA_S 0 + +#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x20) + +/* I2C_GENERAL_CALL_INT_RAW : R/SS/WTC ;bitpos:[17] ;default: 1'b0 ; */ + +#define I2C_GENERAL_CALL_INT_RAW (BIT(17)) +#define I2C_GENERAL_CALL_INT_RAW_M (BIT(17)) +#define I2C_GENERAL_CALL_INT_RAW_V 0x1 +#define I2C_GENERAL_CALL_INT_RAW_S 17 + +/* I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC ;bitpos:[16] ;default: 1'b0 ; */ + +#define I2C_SLAVE_STRETCH_INT_RAW (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_RAW_M (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_RAW_V 0x1 +#define I2C_SLAVE_STRETCH_INT_RAW_S 16 + +/* I2C_DET_START_INT_RAW : R/SS/WTC ;bitpos:[15] ;default: 1'b0 ; */ + +#define I2C_DET_START_INT_RAW (BIT(15)) +#define I2C_DET_START_INT_RAW_M (BIT(15)) +#define I2C_DET_START_INT_RAW_V 0x1 +#define I2C_DET_START_INT_RAW_S 15 + +/* I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[14] ;default: 1'b0 ; */ + +#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x1 +#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 + +/* I2C_SCL_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[13] ;default: 1'b0 ; */ + +#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) +#define I2C_SCL_ST_TO_INT_RAW_M (BIT(13)) +#define I2C_SCL_ST_TO_INT_RAW_V 0x1 +#define I2C_SCL_ST_TO_INT_RAW_S 13 + +/* I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[12] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) +#define I2C_RXFIFO_UDF_INT_RAW_M (BIT(12)) +#define I2C_RXFIFO_UDF_INT_RAW_V 0x1 +#define I2C_RXFIFO_UDF_INT_RAW_S 12 + +/* I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[11] ;default: 1'b0 ; */ + +#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) +#define I2C_TXFIFO_OVF_INT_RAW_M (BIT(11)) +#define I2C_TXFIFO_OVF_INT_RAW_V 0x1 +#define I2C_TXFIFO_OVF_INT_RAW_S 11 + +/* I2C_NACK_INT_RAW : R/SS/WTC ;bitpos:[10] ;default: 1'b0 ; */ + +#define I2C_NACK_INT_RAW (BIT(10)) +#define I2C_NACK_INT_RAW_M (BIT(10)) +#define I2C_NACK_INT_RAW_V 0x1 +#define I2C_NACK_INT_RAW_S 10 + +/* I2C_TRANS_START_INT_RAW : R/SS/WTC ;bitpos:[9] ;default: 1'b0 ; */ + +#define I2C_TRANS_START_INT_RAW (BIT(9)) +#define I2C_TRANS_START_INT_RAW_M (BIT(9)) +#define I2C_TRANS_START_INT_RAW_V 0x1 +#define I2C_TRANS_START_INT_RAW_S 9 + +/* I2C_TIME_OUT_INT_RAW : R/SS/WTC ;bitpos:[8] ;default: 1'b0 ; */ + +#define I2C_TIME_OUT_INT_RAW (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_M (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_V 0x1 +#define I2C_TIME_OUT_INT_RAW_S 8 + +/* I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC ;bitpos:[7] ;default: 1'b0 ; */ + +#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1 +#define I2C_TRANS_COMPLETE_INT_RAW_S 7 + +/* I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[6] ;default: 1'b0 ; */ + +#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_RAW_M (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x1 +#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 + +/* I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC ;bitpos:[5] ;default: 1'b0 ; */ + +#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1 +#define I2C_ARBITRATION_LOST_INT_RAW_S 5 + +/* I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC ;bitpos:[4] ;default: 1'b0 ; */ + +#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_RAW_M (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x1 +#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 + +/* I2C_END_DETECT_INT_RAW : R/SS/WTC ;bitpos:[3] ;default: 1'b0 ; */ + +#define I2C_END_DETECT_INT_RAW (BIT(3)) +#define I2C_END_DETECT_INT_RAW_M (BIT(3)) +#define I2C_END_DETECT_INT_RAW_V 0x1 +#define I2C_END_DETECT_INT_RAW_S 3 + +/* I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[2] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_V 0x1 +#define I2C_RXFIFO_OVF_INT_RAW_S 2 + +/* I2C_TXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'b1 ; */ + +#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) +#define I2C_TXFIFO_WM_INT_RAW_M (BIT(1)) +#define I2C_TXFIFO_WM_INT_RAW_V 0x1 +#define I2C_TXFIFO_WM_INT_RAW_S 1 + +/* I2C_RXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) +#define I2C_RXFIFO_WM_INT_RAW_M (BIT(0)) +#define I2C_RXFIFO_WM_INT_RAW_V 0x1 +#define I2C_RXFIFO_WM_INT_RAW_S 0 + +#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x24) + +/* I2C_GENERAL_CALL_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */ + +#define I2C_GENERAL_CALL_INT_CLR (BIT(17)) +#define I2C_GENERAL_CALL_INT_CLR_M (BIT(17)) +#define I2C_GENERAL_CALL_INT_CLR_V 0x1 +#define I2C_GENERAL_CALL_INT_CLR_S 17 + +/* I2C_SLAVE_STRETCH_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */ + +#define I2C_SLAVE_STRETCH_INT_CLR (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_CLR_M (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_CLR_V 0x1 +#define I2C_SLAVE_STRETCH_INT_CLR_S 16 + +/* I2C_DET_START_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */ + +#define I2C_DET_START_INT_CLR (BIT(15)) +#define I2C_DET_START_INT_CLR_M (BIT(15)) +#define I2C_DET_START_INT_CLR_V 0x1 +#define I2C_DET_START_INT_CLR_S 15 + +/* I2C_SCL_MAIN_ST_TO_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */ + +#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x1 +#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 + +/* I2C_SCL_ST_TO_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ + +#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) +#define I2C_SCL_ST_TO_INT_CLR_M (BIT(13)) +#define I2C_SCL_ST_TO_INT_CLR_V 0x1 +#define I2C_SCL_ST_TO_INT_CLR_S 13 + +/* I2C_RXFIFO_UDF_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) +#define I2C_RXFIFO_UDF_INT_CLR_M (BIT(12)) +#define I2C_RXFIFO_UDF_INT_CLR_V 0x1 +#define I2C_RXFIFO_UDF_INT_CLR_S 12 + +/* I2C_TXFIFO_OVF_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ + +#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) +#define I2C_TXFIFO_OVF_INT_CLR_M (BIT(11)) +#define I2C_TXFIFO_OVF_INT_CLR_V 0x1 +#define I2C_TXFIFO_OVF_INT_CLR_S 11 + +/* I2C_NACK_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ + +#define I2C_NACK_INT_CLR (BIT(10)) +#define I2C_NACK_INT_CLR_M (BIT(10)) +#define I2C_NACK_INT_CLR_V 0x1 +#define I2C_NACK_INT_CLR_S 10 + +/* I2C_TRANS_START_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ + +#define I2C_TRANS_START_INT_CLR (BIT(9)) +#define I2C_TRANS_START_INT_CLR_M (BIT(9)) +#define I2C_TRANS_START_INT_CLR_V 0x1 +#define I2C_TRANS_START_INT_CLR_S 9 + +/* I2C_TIME_OUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ + +#define I2C_TIME_OUT_INT_CLR (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_M (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_V 0x1 +#define I2C_TIME_OUT_INT_CLR_S 8 + +/* I2C_TRANS_COMPLETE_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ + +#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1 +#define I2C_TRANS_COMPLETE_INT_CLR_S 7 + +/* I2C_MST_TXFIFO_UDF_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ + +#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_CLR_M (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x1 +#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 + +/* I2C_ARBITRATION_LOST_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ + +#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1 +#define I2C_ARBITRATION_LOST_INT_CLR_S 5 + +/* I2C_BYTE_TRANS_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ + +#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_CLR_M (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x1 +#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 + +/* I2C_END_DETECT_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ + +#define I2C_END_DETECT_INT_CLR (BIT(3)) +#define I2C_END_DETECT_INT_CLR_M (BIT(3)) +#define I2C_END_DETECT_INT_CLR_V 0x1 +#define I2C_END_DETECT_INT_CLR_S 3 + +/* I2C_RXFIFO_OVF_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_V 0x1 +#define I2C_RXFIFO_OVF_INT_CLR_S 2 + +/* I2C_TXFIFO_WM_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ + +#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) +#define I2C_TXFIFO_WM_INT_CLR_M (BIT(1)) +#define I2C_TXFIFO_WM_INT_CLR_V 0x1 +#define I2C_TXFIFO_WM_INT_CLR_S 1 + +/* I2C_RXFIFO_WM_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) +#define I2C_RXFIFO_WM_INT_CLR_M (BIT(0)) +#define I2C_RXFIFO_WM_INT_CLR_V 0x1 +#define I2C_RXFIFO_WM_INT_CLR_S 0 + +#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x28) + +/* I2C_GENERAL_CALL_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ + +#define I2C_GENERAL_CALL_INT_ENA (BIT(17)) +#define I2C_GENERAL_CALL_INT_ENA_M (BIT(17)) +#define I2C_GENERAL_CALL_INT_ENA_V 0x1 +#define I2C_GENERAL_CALL_INT_ENA_S 17 + +/* I2C_SLAVE_STRETCH_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ + +#define I2C_SLAVE_STRETCH_INT_ENA (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ENA_M (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ENA_V 0x1 +#define I2C_SLAVE_STRETCH_INT_ENA_S 16 + +/* I2C_DET_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ + +#define I2C_DET_START_INT_ENA (BIT(15)) +#define I2C_DET_START_INT_ENA_M (BIT(15)) +#define I2C_DET_START_INT_ENA_V 0x1 +#define I2C_DET_START_INT_ENA_S 15 + +/* I2C_SCL_MAIN_ST_TO_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ + +#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x1 +#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 + +/* I2C_SCL_ST_TO_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ + +#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) +#define I2C_SCL_ST_TO_INT_ENA_M (BIT(13)) +#define I2C_SCL_ST_TO_INT_ENA_V 0x1 +#define I2C_SCL_ST_TO_INT_ENA_S 13 + +/* I2C_RXFIFO_UDF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ENA_M (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ENA_V 0x1 +#define I2C_RXFIFO_UDF_INT_ENA_S 12 + +/* I2C_TXFIFO_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ + +#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ENA_M (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ENA_V 0x1 +#define I2C_TXFIFO_OVF_INT_ENA_S 11 + +/* I2C_NACK_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ + +#define I2C_NACK_INT_ENA (BIT(10)) +#define I2C_NACK_INT_ENA_M (BIT(10)) +#define I2C_NACK_INT_ENA_V 0x1 +#define I2C_NACK_INT_ENA_S 10 + +/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ + +#define I2C_TRANS_START_INT_ENA (BIT(9)) +#define I2C_TRANS_START_INT_ENA_M (BIT(9)) +#define I2C_TRANS_START_INT_ENA_V 0x1 +#define I2C_TRANS_START_INT_ENA_S 9 + +/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ + +#define I2C_TIME_OUT_INT_ENA (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_M (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_V 0x1 +#define I2C_TIME_OUT_INT_ENA_S 8 + +/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1 +#define I2C_TRANS_COMPLETE_INT_ENA_S 7 + +/* I2C_MST_TXFIFO_UDF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ENA_M (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x1 +#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 + +/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1 +#define I2C_ARBITRATION_LOST_INT_ENA_S 5 + +/* I2C_BYTE_TRANS_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ + +#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ENA_M (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x1 +#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 + +/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +#define I2C_END_DETECT_INT_ENA (BIT(3)) +#define I2C_END_DETECT_INT_ENA_M (BIT(3)) +#define I2C_END_DETECT_INT_ENA_V 0x1 +#define I2C_END_DETECT_INT_ENA_S 3 + +/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_V 0x1 +#define I2C_RXFIFO_OVF_INT_ENA_S 2 + +/* I2C_TXFIFO_WM_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) +#define I2C_TXFIFO_WM_INT_ENA_M (BIT(1)) +#define I2C_TXFIFO_WM_INT_ENA_V 0x1 +#define I2C_TXFIFO_WM_INT_ENA_S 1 + +/* I2C_RXFIFO_WM_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) +#define I2C_RXFIFO_WM_INT_ENA_M (BIT(0)) +#define I2C_RXFIFO_WM_INT_ENA_V 0x1 +#define I2C_RXFIFO_WM_INT_ENA_S 0 + +#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2C) + +/* I2C_GENERAL_CALL_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ + +#define I2C_GENERAL_CALL_INT_ST (BIT(17)) +#define I2C_GENERAL_CALL_INT_ST_M (BIT(17)) +#define I2C_GENERAL_CALL_INT_ST_V 0x1 +#define I2C_GENERAL_CALL_INT_ST_S 17 + +/* I2C_SLAVE_STRETCH_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ + +#define I2C_SLAVE_STRETCH_INT_ST (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ST_M (BIT(16)) +#define I2C_SLAVE_STRETCH_INT_ST_V 0x1 +#define I2C_SLAVE_STRETCH_INT_ST_S 16 + +/* I2C_DET_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ + +#define I2C_DET_START_INT_ST (BIT(15)) +#define I2C_DET_START_INT_ST_M (BIT(15)) +#define I2C_DET_START_INT_ST_V 0x1 +#define I2C_DET_START_INT_ST_S 15 + +/* I2C_SCL_MAIN_ST_TO_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ + +#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ST_M (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x1 +#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 + +/* I2C_SCL_ST_TO_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ + +#define I2C_SCL_ST_TO_INT_ST (BIT(13)) +#define I2C_SCL_ST_TO_INT_ST_M (BIT(13)) +#define I2C_SCL_ST_TO_INT_ST_V 0x1 +#define I2C_SCL_ST_TO_INT_ST_S 13 + +/* I2C_RXFIFO_UDF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ST_M (BIT(12)) +#define I2C_RXFIFO_UDF_INT_ST_V 0x1 +#define I2C_RXFIFO_UDF_INT_ST_S 12 + +/* I2C_TXFIFO_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ + +#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ST_M (BIT(11)) +#define I2C_TXFIFO_OVF_INT_ST_V 0x1 +#define I2C_TXFIFO_OVF_INT_ST_S 11 + +/* I2C_NACK_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ + +#define I2C_NACK_INT_ST (BIT(10)) +#define I2C_NACK_INT_ST_M (BIT(10)) +#define I2C_NACK_INT_ST_V 0x1 +#define I2C_NACK_INT_ST_S 10 + +/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ + +#define I2C_TRANS_START_INT_ST (BIT(9)) +#define I2C_TRANS_START_INT_ST_M (BIT(9)) +#define I2C_TRANS_START_INT_ST_V 0x1 +#define I2C_TRANS_START_INT_ST_S 9 + +/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ + +#define I2C_TIME_OUT_INT_ST (BIT(8)) +#define I2C_TIME_OUT_INT_ST_M (BIT(8)) +#define I2C_TIME_OUT_INT_ST_V 0x1 +#define I2C_TIME_OUT_INT_ST_S 8 + +/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ + +#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_V 0x1 +#define I2C_TRANS_COMPLETE_INT_ST_S 7 + +/* I2C_MST_TXFIFO_UDF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ + +#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ST_M (BIT(6)) +#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x1 +#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 + +/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ + +#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_V 0x1 +#define I2C_ARBITRATION_LOST_INT_ST_S 5 + +/* I2C_BYTE_TRANS_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ + +#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ST_M (BIT(4)) +#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x1 +#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 + +/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ + +#define I2C_END_DETECT_INT_ST (BIT(3)) +#define I2C_END_DETECT_INT_ST_M (BIT(3)) +#define I2C_END_DETECT_INT_ST_V 0x1 +#define I2C_END_DETECT_INT_ST_S 3 + +/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_V 0x1 +#define I2C_RXFIFO_OVF_INT_ST_S 2 + +/* I2C_TXFIFO_WM_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ + +#define I2C_TXFIFO_WM_INT_ST (BIT(1)) +#define I2C_TXFIFO_WM_INT_ST_M (BIT(1)) +#define I2C_TXFIFO_WM_INT_ST_V 0x1 +#define I2C_TXFIFO_WM_INT_ST_S 1 + +/* I2C_RXFIFO_WM_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ + +#define I2C_RXFIFO_WM_INT_ST (BIT(0)) +#define I2C_RXFIFO_WM_INT_ST_M (BIT(0)) +#define I2C_RXFIFO_WM_INT_ST_V 0x1 +#define I2C_RXFIFO_WM_INT_ST_S 0 + +#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x30) + +/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ + +#define I2C_SDA_HOLD_TIME 0x000001FF +#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S)) +#define I2C_SDA_HOLD_TIME_V 0x1FF +#define I2C_SDA_HOLD_TIME_S 0 + +#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x34) + +/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ + +#define I2C_SDA_SAMPLE_TIME 0x000001FF +#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S)) +#define I2C_SDA_SAMPLE_TIME_V 0x1FF +#define I2C_SDA_SAMPLE_TIME_S 0 + +#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x38) + +/* I2C_SCL_WAIT_HIGH_PERIOD : R/W ;bitpos:[15:9] ;default: 7'b0 ; */ + +#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007F +#define I2C_SCL_WAIT_HIGH_PERIOD_M ((I2C_SCL_WAIT_HIGH_PERIOD_V)<<(I2C_SCL_WAIT_HIGH_PERIOD_S)) +#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x7F +#define I2C_SCL_WAIT_HIGH_PERIOD_S 9 + +/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ + +#define I2C_SCL_HIGH_PERIOD 0x000001FF +#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S)) +#define I2C_SCL_HIGH_PERIOD_V 0x1FF +#define I2C_SCL_HIGH_PERIOD_S 0 + +#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x40) + +/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ + +#define I2C_SCL_START_HOLD_TIME 0x000001FF +#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S)) +#define I2C_SCL_START_HOLD_TIME_V 0x1FF +#define I2C_SCL_START_HOLD_TIME_S 0 + +#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x44) + +/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ + +#define I2C_SCL_RSTART_SETUP_TIME 0x000001FF +#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S)) +#define I2C_SCL_RSTART_SETUP_TIME_V 0x1FF +#define I2C_SCL_RSTART_SETUP_TIME_S 0 + +#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x48) + +/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ + +#define I2C_SCL_STOP_HOLD_TIME 0x000001FF +#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S)) +#define I2C_SCL_STOP_HOLD_TIME_V 0x1FF +#define I2C_SCL_STOP_HOLD_TIME_S 0 + +#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x4C) + +/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ + +#define I2C_SCL_STOP_SETUP_TIME 0x000001FF +#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S)) +#define I2C_SCL_STOP_SETUP_TIME_V 0x1FF +#define I2C_SCL_STOP_SETUP_TIME_S 0 + +#define I2C_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x50) + +/* I2C_SDA_FILTER_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ + +#define I2C_SDA_FILTER_EN (BIT(9)) +#define I2C_SDA_FILTER_EN_M (BIT(9)) +#define I2C_SDA_FILTER_EN_V 0x1 +#define I2C_SDA_FILTER_EN_S 9 + +/* I2C_SCL_FILTER_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */ + +#define I2C_SCL_FILTER_EN (BIT(8)) +#define I2C_SCL_FILTER_EN_M (BIT(8)) +#define I2C_SCL_FILTER_EN_V 0x1 +#define I2C_SCL_FILTER_EN_S 8 + +/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[7:4] ;default: 4'b0 ; */ + +#define I2C_SDA_FILTER_THRES 0x0000000F +#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S)) +#define I2C_SDA_FILTER_THRES_V 0xF +#define I2C_SDA_FILTER_THRES_S 4 + +/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ + +#define I2C_SCL_FILTER_THRES 0x0000000F +#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S)) +#define I2C_SCL_FILTER_THRES_V 0xF +#define I2C_SCL_FILTER_THRES_S 0 + +#define I2C_CLK_CONF_REG(i) (REG_I2C_BASE(i) + 0x54) + +/* I2C_SCLK_ACTIVE : R/W ;bitpos:[21] ;default: 1'b1 ; */ + +#define I2C_SCLK_ACTIVE (BIT(21)) +#define I2C_SCLK_ACTIVE_M (BIT(21)) +#define I2C_SCLK_ACTIVE_V 0x1 +#define I2C_SCLK_ACTIVE_S 21 + +/* I2C_SCLK_SEL : R/W ;bitpos:[20] ;default: 1'b0 ; */ + +#define I2C_SCLK_SEL (BIT(20)) +#define I2C_SCLK_SEL_M (BIT(20)) +#define I2C_SCLK_SEL_V 0x1 +#define I2C_SCLK_SEL_S 20 + +/* I2C_SCLK_DIV_B : R/W ;bitpos:[19:14] ;default: 6'b0 ; */ + +#define I2C_SCLK_DIV_B 0x0000003F +#define I2C_SCLK_DIV_B_M ((I2C_SCLK_DIV_B_V)<<(I2C_SCLK_DIV_B_S)) +#define I2C_SCLK_DIV_B_V 0x3F +#define I2C_SCLK_DIV_B_S 14 + +/* I2C_SCLK_DIV_A : R/W ;bitpos:[13:8] ;default: 6'b0 ; */ + +#define I2C_SCLK_DIV_A 0x0000003F +#define I2C_SCLK_DIV_A_M ((I2C_SCLK_DIV_A_V)<<(I2C_SCLK_DIV_A_S)) +#define I2C_SCLK_DIV_A_V 0x3F +#define I2C_SCLK_DIV_A_S 8 + +/* I2C_SCLK_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ + +#define I2C_SCLK_DIV_NUM 0x000000FF +#define I2C_SCLK_DIV_NUM_M ((I2C_SCLK_DIV_NUM_V)<<(I2C_SCLK_DIV_NUM_S)) +#define I2C_SCLK_DIV_NUM_V 0xFF +#define I2C_SCLK_DIV_NUM_S 0 + +#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x58) + +/* I2C_COMMAND0_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ + +#define I2C_COMMAND0_DONE (BIT(31)) +#define I2C_COMMAND0_DONE_M (BIT(31)) +#define I2C_COMMAND0_DONE_V 0x1 +#define I2C_COMMAND0_DONE_S 31 + +/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ + +#define I2C_COMMAND0 0x00003FFF +#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S)) +#define I2C_COMMAND0_V 0x3FFF +#define I2C_COMMAND0_S 0 + +#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x5C) + +/* I2C_COMMAND1_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ + +#define I2C_COMMAND1_DONE (BIT(31)) +#define I2C_COMMAND1_DONE_M (BIT(31)) +#define I2C_COMMAND1_DONE_V 0x1 +#define I2C_COMMAND1_DONE_S 31 + +/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ + +#define I2C_COMMAND1 0x00003FFF +#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S)) +#define I2C_COMMAND1_V 0x3FFF +#define I2C_COMMAND1_S 0 + +#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x60) + +/* I2C_COMMAND2_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ + +#define I2C_COMMAND2_DONE (BIT(31)) +#define I2C_COMMAND2_DONE_M (BIT(31)) +#define I2C_COMMAND2_DONE_V 0x1 +#define I2C_COMMAND2_DONE_S 31 + +/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ + +#define I2C_COMMAND2 0x00003FFF +#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S)) +#define I2C_COMMAND2_V 0x3FFF +#define I2C_COMMAND2_S 0 + +#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x64) + +/* I2C_COMMAND3_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ + +#define I2C_COMMAND3_DONE (BIT(31)) +#define I2C_COMMAND3_DONE_M (BIT(31)) +#define I2C_COMMAND3_DONE_V 0x1 +#define I2C_COMMAND3_DONE_S 31 + +/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ + +#define I2C_COMMAND3 0x00003FFF +#define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S)) +#define I2C_COMMAND3_V 0x3FFF +#define I2C_COMMAND3_S 0 + +#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x68) + +/* I2C_COMMAND4_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ + +#define I2C_COMMAND4_DONE (BIT(31)) +#define I2C_COMMAND4_DONE_M (BIT(31)) +#define I2C_COMMAND4_DONE_V 0x1 +#define I2C_COMMAND4_DONE_S 31 + +/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ + +#define I2C_COMMAND4 0x00003FFF +#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S)) +#define I2C_COMMAND4_V 0x3FFF +#define I2C_COMMAND4_S 0 + +#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x6C) + +/* I2C_COMMAND5_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ + +#define I2C_COMMAND5_DONE (BIT(31)) +#define I2C_COMMAND5_DONE_M (BIT(31)) +#define I2C_COMMAND5_DONE_V 0x1 +#define I2C_COMMAND5_DONE_S 31 + +/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ + +#define I2C_COMMAND5 0x00003FFF +#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S)) +#define I2C_COMMAND5_V 0x3FFF +#define I2C_COMMAND5_S 0 + +#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x70) + +/* I2C_COMMAND6_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ + +#define I2C_COMMAND6_DONE (BIT(31)) +#define I2C_COMMAND6_DONE_M (BIT(31)) +#define I2C_COMMAND6_DONE_V 0x1 +#define I2C_COMMAND6_DONE_S 31 + +/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ + +#define I2C_COMMAND6 0x00003FFF +#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S)) +#define I2C_COMMAND6_V 0x3FFF +#define I2C_COMMAND6_S 0 + +#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x74) + +/* I2C_COMMAND7_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ + +#define I2C_COMMAND7_DONE (BIT(31)) +#define I2C_COMMAND7_DONE_M (BIT(31)) +#define I2C_COMMAND7_DONE_V 0x1 +#define I2C_COMMAND7_DONE_S 31 + +/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ + +#define I2C_COMMAND7 0x00003FFF +#define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S)) +#define I2C_COMMAND7_V 0x3FFF +#define I2C_COMMAND7_S 0 + +#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x78) + +/* I2C_SCL_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ + +#define I2C_SCL_ST_TO_REG 0x0000001F +#define I2C_SCL_ST_TO_REG_M ((I2C_SCL_ST_TO_REG_V)<<(I2C_SCL_ST_TO_REG_S)) +#define I2C_SCL_ST_TO_REG_V 0x1F +#define I2C_SCL_ST_TO_REG_S 0 + +#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x7C) + +/* I2C_SCL_MAIN_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ + +#define I2C_SCL_MAIN_ST_TO_REG 0x0000001F +#define I2C_SCL_MAIN_ST_TO_REG_M ((I2C_SCL_MAIN_ST_TO_REG_V)<<(I2C_SCL_MAIN_ST_TO_REG_S)) +#define I2C_SCL_MAIN_ST_TO_REG_V 0x1F +#define I2C_SCL_MAIN_ST_TO_REG_S 0 + +#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x80) + +/* I2C_SDA_PD_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ + +#define I2C_SDA_PD_EN (BIT(7)) +#define I2C_SDA_PD_EN_M (BIT(7)) +#define I2C_SDA_PD_EN_V 0x1 +#define I2C_SDA_PD_EN_S 7 + +/* I2C_SCL_PD_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ + +#define I2C_SCL_PD_EN (BIT(6)) +#define I2C_SCL_PD_EN_M (BIT(6)) +#define I2C_SCL_PD_EN_V 0x1 +#define I2C_SCL_PD_EN_S 6 + +/* I2C_SCL_RST_SLV_NUM : R/W ;bitpos:[5:1] ;default: 5'b0 ; */ + +#define I2C_SCL_RST_SLV_NUM 0x0000001F +#define I2C_SCL_RST_SLV_NUM_M ((I2C_SCL_RST_SLV_NUM_V)<<(I2C_SCL_RST_SLV_NUM_S)) +#define I2C_SCL_RST_SLV_NUM_V 0x1F +#define I2C_SCL_RST_SLV_NUM_S 1 + +/* I2C_SCL_RST_SLV_EN : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */ + +#define I2C_SCL_RST_SLV_EN (BIT(0)) +#define I2C_SCL_RST_SLV_EN_M (BIT(0)) +#define I2C_SCL_RST_SLV_EN_V 0x1 +#define I2C_SCL_RST_SLV_EN_S 0 + +#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x84) + +/* I2C_SLAVE_BYTE_ACK_LVL : R/W ;bitpos:[13] ;default: 1'b0 ; */ + +#define I2C_SLAVE_BYTE_ACK_LVL (BIT(13)) +#define I2C_SLAVE_BYTE_ACK_LVL_M (BIT(13)) +#define I2C_SLAVE_BYTE_ACK_LVL_V 0x1 +#define I2C_SLAVE_BYTE_ACK_LVL_S 13 + +/* I2C_SLAVE_BYTE_ACK_CTL_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +#define I2C_SLAVE_BYTE_ACK_CTL_EN (BIT(12)) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_M (BIT(12)) +#define I2C_SLAVE_BYTE_ACK_CTL_EN_V 0x1 +#define I2C_SLAVE_BYTE_ACK_CTL_EN_S 12 + +/* I2C_SLAVE_SCL_STRETCH_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ + +#define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) +#define I2C_SLAVE_SCL_STRETCH_CLR_M (BIT(11)) +#define I2C_SLAVE_SCL_STRETCH_CLR_V 0x1 +#define I2C_SLAVE_SCL_STRETCH_CLR_S 11 + +/* I2C_SLAVE_SCL_STRETCH_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ + +#define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) +#define I2C_SLAVE_SCL_STRETCH_EN_M (BIT(10)) +#define I2C_SLAVE_SCL_STRETCH_EN_V 0x1 +#define I2C_SLAVE_SCL_STRETCH_EN_S 10 + +/* I2C_STRETCH_PROTECT_NUM : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ + +#define I2C_STRETCH_PROTECT_NUM 0x000003FF +#define I2C_STRETCH_PROTECT_NUM_M ((I2C_STRETCH_PROTECT_NUM_V)<<(I2C_STRETCH_PROTECT_NUM_S)) +#define I2C_STRETCH_PROTECT_NUM_V 0x3FF +#define I2C_STRETCH_PROTECT_NUM_S 0 + +#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0xF8) + +/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h20070201 ; */ + +#define I2C_DATE 0xFFFFFFFF +#define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S)) +#define I2C_DATE_V 0xFFFFFFFF +#define I2C_DATE_S 0 + +#define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x100) + +#define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x180) + +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_I2C_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_interrupt.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_interrupt.h similarity index 99% rename from arch/risc-v/src/esp32c3/hardware/esp32c3_interrupt.h rename to arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_interrupt.h index 675a584e4c385..b776802f454df 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_interrupt.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_interrupt.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_interrupt.h + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_interrupt.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_INTERRUPT_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_INTERRUPT_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_INTERRUPT_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_INTERRUPT_H /**************************************************************************** * Included Files @@ -959,4 +959,4 @@ #define INTERRUPT_INTERRUPT_DATE_V 0xfffffff #define INTERRUPT_INTERRUPT_DATE_S 0 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_INTERRUPT_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_INTERRUPT_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_iomux.h similarity index 97% rename from arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h rename to arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_iomux.h index f3c4f29d114da..b75eb46c21806 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_iomux.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_iomux.h + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_iomux.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_IOMUX_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_IOMUX_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_IOMUX_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_IOMUX_H /**************************************************************************** * Included Files @@ -307,4 +307,4 @@ #define IO_MUX_DATE_S 0 #define IO_MUX_DATE_VERSION 0x2006050 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_IOMUX_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_IOMUX_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_ledc.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_ledc.h new file mode 100644 index 0000000000000..7fa402cd58230 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_ledc.h @@ -0,0 +1,2742 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_ledc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_LEDC_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_LEDC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LEDC_CH0_CONF0_REG register + * Configuration register 0 for channel 0 + */ + +#define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0) + +/* LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 0. + * + * 0: select timer0 + * + * 1: select timer1 + * + * 2: select timer2 + * + * 3: select timer3 + */ + +#define LEDC_TIMER_SEL_CH0 0x00000003 +#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) +#define LEDC_TIMER_SEL_CH0_V 0x00000003 +#define LEDC_TIMER_SEL_CH0_S 0 + +/* LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 0. + */ + +#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) +#define LEDC_SIG_OUT_EN_CH0_V 0x00000001 +#define LEDC_SIG_OUT_EN_CH0_S 2 + +/* LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 0 is inactive. + */ + +#define LEDC_IDLE_LV_CH0 (BIT(3)) +#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) +#define LEDC_IDLE_LV_CH0_V 0x00000001 +#define LEDC_IDLE_LV_CH0_S 3 + +/* LEDC_PARA_UP_CH0 : WO; bitpos: [4]; default: 0; + * This bit is used to update register LEDC_CH0_HPOINT and LEDC_CH0_DUTY for + * channel 0. + */ + +#define LEDC_PARA_UP_CH0 (BIT(4)) +#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) +#define LEDC_PARA_UP_CH0_V 0x00000001 +#define LEDC_PARA_UP_CH0_S 4 + +/* LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH0_INT interrupt will be triggered when channel 0 + * overflows for (LEDC_OVF_NUM_CH0 + 1) times. + */ + +#define LEDC_OVF_NUM_CH0 0x000003FF +#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) +#define LEDC_OVF_NUM_CH0_V 0x000003FF +#define LEDC_OVF_NUM_CH0_S 5 + +/* LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 0. + */ + +#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) +#define LEDC_OVF_CNT_EN_CH0_V 0x00000001 +#define LEDC_OVF_CNT_EN_CH0_S 15 + +/* LEDC_OVF_CNT_RESET_CH0 : WO; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 0. + */ + +#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) +#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001 +#define LEDC_OVF_CNT_RESET_CH0_S 16 + +/* LEDC_OVF_CNT_RESET_ST_CH0 : RO; bitpos: [17]; default: 0; + * This is the status bit of LEDC_OVF_CNT_RESET_CH0. + */ + +#define LEDC_OVF_CNT_RESET_ST_CH0 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_CH0_M (LEDC_OVF_CNT_RESET_ST_CH0_V << LEDC_OVF_CNT_RESET_ST_CH0_S) +#define LEDC_OVF_CNT_RESET_ST_CH0_V 0x00000001 +#define LEDC_OVF_CNT_RESET_ST_CH0_S 17 + +/* LEDC_CH0_HPOINT_REG register + * High point register for channel 0 + */ + +#define LEDC_CH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x4) + +/* LEDC_HPOINT_CH0 : R/W; bitpos: [13:0]; default: 0; + * The output value changes to high when the selected timers has reached the + * value specified by this register. + */ + +#define LEDC_HPOINT_CH0 0x00003FFF +#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) +#define LEDC_HPOINT_CH0_V 0x00003FFF +#define LEDC_HPOINT_CH0_S 0 + +/* LEDC_CH0_DUTY_REG register + * Initial duty cycle for channel 0 + */ + +#define LEDC_CH0_DUTY_REG (DR_REG_LEDC_BASE + 0x8) + +/* LEDC_DUTY_CH0 : R/W; bitpos: [18:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the + * Lpoint. + */ + +#define LEDC_DUTY_CH0 0x0007FFFF +#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) +#define LEDC_DUTY_CH0_V 0x0007FFFF +#define LEDC_DUTY_CH0_S 0 + +/* LEDC_CH0_CONF1_REG register + * Configuration register 1 for channel 0 + */ + +#define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc) + +/* LEDC_DUTY_SCALE_CH0 : R/W; bitpos: [9:0]; default: 0; + * This register is used to configure the changing step scale of duty on + * channel 0. + */ + +#define LEDC_DUTY_SCALE_CH0 0x000003FF +#define LEDC_DUTY_SCALE_CH0_M (LEDC_DUTY_SCALE_CH0_V << LEDC_DUTY_SCALE_CH0_S) +#define LEDC_DUTY_SCALE_CH0_V 0x000003FF +#define LEDC_DUTY_SCALE_CH0_S 0 + +/* LEDC_DUTY_CYCLE_CH0 : R/W; bitpos: [19:10]; default: 0; + * The duty will change every LEDC_DUTY_CYCLE_CH0 on channel 0. + */ + +#define LEDC_DUTY_CYCLE_CH0 0x000003FF +#define LEDC_DUTY_CYCLE_CH0_M (LEDC_DUTY_CYCLE_CH0_V << LEDC_DUTY_CYCLE_CH0_S) +#define LEDC_DUTY_CYCLE_CH0_V 0x000003FF +#define LEDC_DUTY_CYCLE_CH0_S 10 + +/* LEDC_DUTY_NUM_CH0 : R/W; bitpos: [29:20]; default: 0; + * This register is used to control the number of times the duty cycle will + * be changed. + */ + +#define LEDC_DUTY_NUM_CH0 0x000003FF +#define LEDC_DUTY_NUM_CH0_M (LEDC_DUTY_NUM_CH0_V << LEDC_DUTY_NUM_CH0_S) +#define LEDC_DUTY_NUM_CH0_V 0x000003FF +#define LEDC_DUTY_NUM_CH0_S 20 + +/* LEDC_DUTY_INC_CH0 : R/W; bitpos: [30]; default: 1; + * This register is used to increase or decrease the duty of output signal + * on channel 0. 1: Increase;0: Decrease. + */ + +#define LEDC_DUTY_INC_CH0 (BIT(30)) +#define LEDC_DUTY_INC_CH0_M (LEDC_DUTY_INC_CH0_V << LEDC_DUTY_INC_CH0_S) +#define LEDC_DUTY_INC_CH0_V 0x00000001 +#define LEDC_DUTY_INC_CH0_S 30 + +/* LEDC_DUTY_START_CH0 : R/W; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH0_CONF1_REG will start to take effect + * when this bit is set to 1. + */ + +#define LEDC_DUTY_START_CH0 (BIT(31)) +#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) +#define LEDC_DUTY_START_CH0_V 0x00000001 +#define LEDC_DUTY_START_CH0_S 31 + +/* LEDC_CH0_DUTY_R_REG register + * Current duty cycle for channel 0 + */ + +#define LEDC_CH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x10) + +/* LEDC_DUTY_R_CH0 : RO; bitpos: [18:0]; default: 0; + * This register stores the current duty of output signal on channel 0. + */ + +#define LEDC_DUTY_R_CH0 0x0007FFFF +#define LEDC_DUTY_R_CH0_M (LEDC_DUTY_R_CH0_V << LEDC_DUTY_R_CH0_S) +#define LEDC_DUTY_R_CH0_V 0x0007FFFF +#define LEDC_DUTY_R_CH0_S 0 + +/* LEDC_CH1_CONF0_REG register + * Configuration register 0 for channel 1 + */ + +#define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14) + +/* LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 1. + * + * 0: select timer0 + * + * 1: select timer1 + * + * 2: select timer2 + * + * 3: select timer3 + */ + +#define LEDC_TIMER_SEL_CH1 0x00000003 +#define LEDC_TIMER_SEL_CH1_M (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S) +#define LEDC_TIMER_SEL_CH1_V 0x00000003 +#define LEDC_TIMER_SEL_CH1_S 0 + +/* LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 1. + */ + +#define LEDC_SIG_OUT_EN_CH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH1_M (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S) +#define LEDC_SIG_OUT_EN_CH1_V 0x00000001 +#define LEDC_SIG_OUT_EN_CH1_S 2 + +/* LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 1 is inactive. + */ + +#define LEDC_IDLE_LV_CH1 (BIT(3)) +#define LEDC_IDLE_LV_CH1_M (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S) +#define LEDC_IDLE_LV_CH1_V 0x00000001 +#define LEDC_IDLE_LV_CH1_S 3 + +/* LEDC_PARA_UP_CH1 : WO; bitpos: [4]; default: 0; + * This bit is used to update register LEDC_CH1_HPOINT and LEDC_CH1_DUTY for + * channel 1. + */ + +#define LEDC_PARA_UP_CH1 (BIT(4)) +#define LEDC_PARA_UP_CH1_M (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S) +#define LEDC_PARA_UP_CH1_V 0x00000001 +#define LEDC_PARA_UP_CH1_S 4 + +/* LEDC_OVF_NUM_CH1 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH1_INT interrupt will be triggered when channel 1 + * overflows for (LEDC_OVF_NUM_CH1 + 1) times. + */ + +#define LEDC_OVF_NUM_CH1 0x000003FF +#define LEDC_OVF_NUM_CH1_M (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S) +#define LEDC_OVF_NUM_CH1_V 0x000003FF +#define LEDC_OVF_NUM_CH1_S 5 + +/* LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 1. + */ + +#define LEDC_OVF_CNT_EN_CH1 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH1_M (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S) +#define LEDC_OVF_CNT_EN_CH1_V 0x00000001 +#define LEDC_OVF_CNT_EN_CH1_S 15 + +/* LEDC_OVF_CNT_RESET_CH1 : WO; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 1. + */ + +#define LEDC_OVF_CNT_RESET_CH1 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH1_M (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S) +#define LEDC_OVF_CNT_RESET_CH1_V 0x00000001 +#define LEDC_OVF_CNT_RESET_CH1_S 16 + +/* LEDC_OVF_CNT_RESET_ST_CH1 : RO; bitpos: [17]; default: 0; + * This is the status bit of LEDC_OVF_CNT_RESET_CH1. + */ + +#define LEDC_OVF_CNT_RESET_ST_CH1 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_CH1_M (LEDC_OVF_CNT_RESET_ST_CH1_V << LEDC_OVF_CNT_RESET_ST_CH1_S) +#define LEDC_OVF_CNT_RESET_ST_CH1_V 0x00000001 +#define LEDC_OVF_CNT_RESET_ST_CH1_S 17 + +/* LEDC_CH1_HPOINT_REG register + * High point register for channel 1 + */ + +#define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18) + +/* LEDC_HPOINT_CH1 : R/W; bitpos: [13:0]; default: 0; + * The output value changes to high when the selected timers has reached the + * value specified by this register. + */ + +#define LEDC_HPOINT_CH1 0x00003FFF +#define LEDC_HPOINT_CH1_M (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S) +#define LEDC_HPOINT_CH1_V 0x00003FFF +#define LEDC_HPOINT_CH1_S 0 + +/* LEDC_CH1_DUTY_REG register + * Initial duty cycle for channel 1 + */ + +#define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c) + +/* LEDC_DUTY_CH1 : R/W; bitpos: [18:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the + * Lpoint. + */ + +#define LEDC_DUTY_CH1 0x0007FFFF +#define LEDC_DUTY_CH1_M (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S) +#define LEDC_DUTY_CH1_V 0x0007FFFF +#define LEDC_DUTY_CH1_S 0 + +/* LEDC_CH1_CONF1_REG register + * Configuration register 1 for channel 1 + */ + +#define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20) + +/* LEDC_DUTY_SCALE_CH1 : R/W; bitpos: [9:0]; default: 0; + * This register is used to configure the changing step scale of duty on + * channel 1. + */ + +#define LEDC_DUTY_SCALE_CH1 0x000003FF +#define LEDC_DUTY_SCALE_CH1_M (LEDC_DUTY_SCALE_CH1_V << LEDC_DUTY_SCALE_CH1_S) +#define LEDC_DUTY_SCALE_CH1_V 0x000003FF +#define LEDC_DUTY_SCALE_CH1_S 0 + +/* LEDC_DUTY_CYCLE_CH1 : R/W; bitpos: [19:10]; default: 0; + * The duty will change every LEDC_DUTY_CYCLE_CH1 on channel 1. + */ + +#define LEDC_DUTY_CYCLE_CH1 0x000003FF +#define LEDC_DUTY_CYCLE_CH1_M (LEDC_DUTY_CYCLE_CH1_V << LEDC_DUTY_CYCLE_CH1_S) +#define LEDC_DUTY_CYCLE_CH1_V 0x000003FF +#define LEDC_DUTY_CYCLE_CH1_S 10 + +/* LEDC_DUTY_NUM_CH1 : R/W; bitpos: [29:20]; default: 0; + * This register is used to control the number of times the duty cycle will + * be changed. + */ + +#define LEDC_DUTY_NUM_CH1 0x000003FF +#define LEDC_DUTY_NUM_CH1_M (LEDC_DUTY_NUM_CH1_V << LEDC_DUTY_NUM_CH1_S) +#define LEDC_DUTY_NUM_CH1_V 0x000003FF +#define LEDC_DUTY_NUM_CH1_S 20 + +/* LEDC_DUTY_INC_CH1 : R/W; bitpos: [30]; default: 1; + * This register is used to increase or decrease the duty of output signal + * on channel 1. 1: Increase;0: Decrease. + */ + +#define LEDC_DUTY_INC_CH1 (BIT(30)) +#define LEDC_DUTY_INC_CH1_M (LEDC_DUTY_INC_CH1_V << LEDC_DUTY_INC_CH1_S) +#define LEDC_DUTY_INC_CH1_V 0x00000001 +#define LEDC_DUTY_INC_CH1_S 30 + +/* LEDC_DUTY_START_CH1 : R/W; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH1_CONF1_REG will start to take effect + * when this bit is set to 1. + */ + +#define LEDC_DUTY_START_CH1 (BIT(31)) +#define LEDC_DUTY_START_CH1_M (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S) +#define LEDC_DUTY_START_CH1_V 0x00000001 +#define LEDC_DUTY_START_CH1_S 31 + +/* LEDC_CH1_DUTY_R_REG register + * Current duty cycle for channel 1 + */ + +#define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24) + +/* LEDC_DUTY_R_CH1 : RO; bitpos: [18:0]; default: 0; + * This register stores the current duty of output signal on channel 1. + */ + +#define LEDC_DUTY_R_CH1 0x0007FFFF +#define LEDC_DUTY_R_CH1_M (LEDC_DUTY_R_CH1_V << LEDC_DUTY_R_CH1_S) +#define LEDC_DUTY_R_CH1_V 0x0007FFFF +#define LEDC_DUTY_R_CH1_S 0 + +/* LEDC_CH2_CONF0_REG register + * Configuration register 0 for channel 2 + */ + +#define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28) + +/* LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 2. + * + * 0: select timer0 + * + * 1: select timer1 + * + * 2: select timer2 + * + * 3: select timer3 + */ + +#define LEDC_TIMER_SEL_CH2 0x00000003 +#define LEDC_TIMER_SEL_CH2_M (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S) +#define LEDC_TIMER_SEL_CH2_V 0x00000003 +#define LEDC_TIMER_SEL_CH2_S 0 + +/* LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 2. + */ + +#define LEDC_SIG_OUT_EN_CH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH2_M (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S) +#define LEDC_SIG_OUT_EN_CH2_V 0x00000001 +#define LEDC_SIG_OUT_EN_CH2_S 2 + +/* LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 2 is inactive. + */ + +#define LEDC_IDLE_LV_CH2 (BIT(3)) +#define LEDC_IDLE_LV_CH2_M (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S) +#define LEDC_IDLE_LV_CH2_V 0x00000001 +#define LEDC_IDLE_LV_CH2_S 3 + +/* LEDC_PARA_UP_CH2 : WO; bitpos: [4]; default: 0; + * This bit is used to update register LEDC_CH2_HPOINT and LEDC_CH2_DUTY for + * channel 2. + */ + +#define LEDC_PARA_UP_CH2 (BIT(4)) +#define LEDC_PARA_UP_CH2_M (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S) +#define LEDC_PARA_UP_CH2_V 0x00000001 +#define LEDC_PARA_UP_CH2_S 4 + +/* LEDC_OVF_NUM_CH2 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH2_INT interrupt will be triggered when channel 2 + * overflows for (LEDC_OVF_NUM_CH2 + 1) times. + */ + +#define LEDC_OVF_NUM_CH2 0x000003FF +#define LEDC_OVF_NUM_CH2_M (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S) +#define LEDC_OVF_NUM_CH2_V 0x000003FF +#define LEDC_OVF_NUM_CH2_S 5 + +/* LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 2. + */ + +#define LEDC_OVF_CNT_EN_CH2 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH2_M (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S) +#define LEDC_OVF_CNT_EN_CH2_V 0x00000001 +#define LEDC_OVF_CNT_EN_CH2_S 15 + +/* LEDC_OVF_CNT_RESET_CH2 : WO; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 2. + */ + +#define LEDC_OVF_CNT_RESET_CH2 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH2_M (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S) +#define LEDC_OVF_CNT_RESET_CH2_V 0x00000001 +#define LEDC_OVF_CNT_RESET_CH2_S 16 + +/* LEDC_OVF_CNT_RESET_ST_CH2 : RO; bitpos: [17]; default: 0; + * This is the status bit of LEDC_OVF_CNT_RESET_CH2. + */ + +#define LEDC_OVF_CNT_RESET_ST_CH2 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_CH2_M (LEDC_OVF_CNT_RESET_ST_CH2_V << LEDC_OVF_CNT_RESET_ST_CH2_S) +#define LEDC_OVF_CNT_RESET_ST_CH2_V 0x00000001 +#define LEDC_OVF_CNT_RESET_ST_CH2_S 17 + +/* LEDC_CH2_HPOINT_REG register + * High point register for channel 2 + */ + +#define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c) + +/* LEDC_HPOINT_CH2 : R/W; bitpos: [13:0]; default: 0; + * The output value changes to high when the selected timers has reached the + * value specified by this register. + */ + +#define LEDC_HPOINT_CH2 0x00003FFF +#define LEDC_HPOINT_CH2_M (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S) +#define LEDC_HPOINT_CH2_V 0x00003FFF +#define LEDC_HPOINT_CH2_S 0 + +/* LEDC_CH2_DUTY_REG register + * Initial duty cycle for channel 2 + */ + +#define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30) + +/* LEDC_DUTY_CH2 : R/W; bitpos: [18:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the + * Lpoint. + */ + +#define LEDC_DUTY_CH2 0x0007FFFF +#define LEDC_DUTY_CH2_M (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S) +#define LEDC_DUTY_CH2_V 0x0007FFFF +#define LEDC_DUTY_CH2_S 0 + +/* LEDC_CH2_CONF1_REG register + * Configuration register 1 for channel 2 + */ + +#define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34) + +/* LEDC_DUTY_SCALE_CH2 : R/W; bitpos: [9:0]; default: 0; + * This register is used to configure the changing step scale of duty on + * channel 2. + */ + +#define LEDC_DUTY_SCALE_CH2 0x000003FF +#define LEDC_DUTY_SCALE_CH2_M (LEDC_DUTY_SCALE_CH2_V << LEDC_DUTY_SCALE_CH2_S) +#define LEDC_DUTY_SCALE_CH2_V 0x000003FF +#define LEDC_DUTY_SCALE_CH2_S 0 + +/* LEDC_DUTY_CYCLE_CH2 : R/W; bitpos: [19:10]; default: 0; + * The duty will change every LEDC_DUTY_CYCLE_CH2 on channel 2. + */ + +#define LEDC_DUTY_CYCLE_CH2 0x000003FF +#define LEDC_DUTY_CYCLE_CH2_M (LEDC_DUTY_CYCLE_CH2_V << LEDC_DUTY_CYCLE_CH2_S) +#define LEDC_DUTY_CYCLE_CH2_V 0x000003FF +#define LEDC_DUTY_CYCLE_CH2_S 10 + +/* LEDC_DUTY_NUM_CH2 : R/W; bitpos: [29:20]; default: 0; + * This register is used to control the number of times the duty cycle will + * be changed. + */ + +#define LEDC_DUTY_NUM_CH2 0x000003FF +#define LEDC_DUTY_NUM_CH2_M (LEDC_DUTY_NUM_CH2_V << LEDC_DUTY_NUM_CH2_S) +#define LEDC_DUTY_NUM_CH2_V 0x000003FF +#define LEDC_DUTY_NUM_CH2_S 20 + +/* LEDC_DUTY_INC_CH2 : R/W; bitpos: [30]; default: 1; + * This register is used to increase or decrease the duty of output signal + * on channel 2. 1: Increase;0: Decrease. + */ + +#define LEDC_DUTY_INC_CH2 (BIT(30)) +#define LEDC_DUTY_INC_CH2_M (LEDC_DUTY_INC_CH2_V << LEDC_DUTY_INC_CH2_S) +#define LEDC_DUTY_INC_CH2_V 0x00000001 +#define LEDC_DUTY_INC_CH2_S 30 + +/* LEDC_DUTY_START_CH2 : R/W; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH2_CONF1_REG will start to take effect + * when this bit is set to 1. + */ + +#define LEDC_DUTY_START_CH2 (BIT(31)) +#define LEDC_DUTY_START_CH2_M (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S) +#define LEDC_DUTY_START_CH2_V 0x00000001 +#define LEDC_DUTY_START_CH2_S 31 + +/* LEDC_CH2_DUTY_R_REG register + * Current duty cycle for channel 2 + */ + +#define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38) + +/* LEDC_DUTY_R_CH2 : RO; bitpos: [18:0]; default: 0; + * This register stores the current duty of output signal on channel 2. + */ + +#define LEDC_DUTY_R_CH2 0x0007FFFF +#define LEDC_DUTY_R_CH2_M (LEDC_DUTY_R_CH2_V << LEDC_DUTY_R_CH2_S) +#define LEDC_DUTY_R_CH2_V 0x0007FFFF +#define LEDC_DUTY_R_CH2_S 0 + +/* LEDC_CH3_CONF0_REG register + * Configuration register 0 for channel 3 + */ + +#define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c) + +/* LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 3. + * + * 0: select timer0 + * + * 1: select timer1 + * + * 2: select timer2 + * + * 3: select timer3 + */ + +#define LEDC_TIMER_SEL_CH3 0x00000003 +#define LEDC_TIMER_SEL_CH3_M (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S) +#define LEDC_TIMER_SEL_CH3_V 0x00000003 +#define LEDC_TIMER_SEL_CH3_S 0 + +/* LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 3. + */ + +#define LEDC_SIG_OUT_EN_CH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH3_M (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S) +#define LEDC_SIG_OUT_EN_CH3_V 0x00000001 +#define LEDC_SIG_OUT_EN_CH3_S 2 + +/* LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 3 is inactive. + */ + +#define LEDC_IDLE_LV_CH3 (BIT(3)) +#define LEDC_IDLE_LV_CH3_M (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S) +#define LEDC_IDLE_LV_CH3_V 0x00000001 +#define LEDC_IDLE_LV_CH3_S 3 + +/* LEDC_PARA_UP_CH3 : WO; bitpos: [4]; default: 0; + * This bit is used to update register LEDC_CH3_HPOINT and LEDC_CH3_DUTY for + * channel 3. + */ + +#define LEDC_PARA_UP_CH3 (BIT(4)) +#define LEDC_PARA_UP_CH3_M (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S) +#define LEDC_PARA_UP_CH3_V 0x00000001 +#define LEDC_PARA_UP_CH3_S 4 + +/* LEDC_OVF_NUM_CH3 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH3_INT interrupt will be triggered when channel 3 + * overflows for (LEDC_OVF_NUM_CH3 + 1) times. + */ + +#define LEDC_OVF_NUM_CH3 0x000003FF +#define LEDC_OVF_NUM_CH3_M (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S) +#define LEDC_OVF_NUM_CH3_V 0x000003FF +#define LEDC_OVF_NUM_CH3_S 5 + +/* LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 3. + */ + +#define LEDC_OVF_CNT_EN_CH3 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH3_M (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S) +#define LEDC_OVF_CNT_EN_CH3_V 0x00000001 +#define LEDC_OVF_CNT_EN_CH3_S 15 + +/* LEDC_OVF_CNT_RESET_CH3 : WO; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 3. + */ + +#define LEDC_OVF_CNT_RESET_CH3 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH3_M (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S) +#define LEDC_OVF_CNT_RESET_CH3_V 0x00000001 +#define LEDC_OVF_CNT_RESET_CH3_S 16 + +/* LEDC_OVF_CNT_RESET_ST_CH3 : RO; bitpos: [17]; default: 0; + * This is the status bit of LEDC_OVF_CNT_RESET_CH3. + */ + +#define LEDC_OVF_CNT_RESET_ST_CH3 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_CH3_M (LEDC_OVF_CNT_RESET_ST_CH3_V << LEDC_OVF_CNT_RESET_ST_CH3_S) +#define LEDC_OVF_CNT_RESET_ST_CH3_V 0x00000001 +#define LEDC_OVF_CNT_RESET_ST_CH3_S 17 + +/* LEDC_CH3_HPOINT_REG register + * High point register for channel 3 + */ + +#define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40) + +/* LEDC_HPOINT_CH3 : R/W; bitpos: [13:0]; default: 0; + * The output value changes to high when the selected timers has reached the + * value specified by this register. + */ + +#define LEDC_HPOINT_CH3 0x00003FFF +#define LEDC_HPOINT_CH3_M (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S) +#define LEDC_HPOINT_CH3_V 0x00003FFF +#define LEDC_HPOINT_CH3_S 0 + +/* LEDC_CH3_DUTY_REG register + * Initial duty cycle for channel 3 + */ + +#define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44) + +/* LEDC_DUTY_CH3 : R/W; bitpos: [18:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the + * Lpoint. + */ + +#define LEDC_DUTY_CH3 0x0007FFFF +#define LEDC_DUTY_CH3_M (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S) +#define LEDC_DUTY_CH3_V 0x0007FFFF +#define LEDC_DUTY_CH3_S 0 + +/* LEDC_CH3_CONF1_REG register + * Configuration register 1 for channel 3 + */ + +#define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48) + +/* LEDC_DUTY_SCALE_CH3 : R/W; bitpos: [9:0]; default: 0; + * This register is used to configure the changing step scale of duty on + * channel 3. + */ + +#define LEDC_DUTY_SCALE_CH3 0x000003FF +#define LEDC_DUTY_SCALE_CH3_M (LEDC_DUTY_SCALE_CH3_V << LEDC_DUTY_SCALE_CH3_S) +#define LEDC_DUTY_SCALE_CH3_V 0x000003FF +#define LEDC_DUTY_SCALE_CH3_S 0 + +/* LEDC_DUTY_CYCLE_CH3 : R/W; bitpos: [19:10]; default: 0; + * The duty will change every LEDC_DUTY_CYCLE_CH3 on channel 3. + */ + +#define LEDC_DUTY_CYCLE_CH3 0x000003FF +#define LEDC_DUTY_CYCLE_CH3_M (LEDC_DUTY_CYCLE_CH3_V << LEDC_DUTY_CYCLE_CH3_S) +#define LEDC_DUTY_CYCLE_CH3_V 0x000003FF +#define LEDC_DUTY_CYCLE_CH3_S 10 + +/* LEDC_DUTY_NUM_CH3 : R/W; bitpos: [29:20]; default: 0; + * This register is used to control the number of times the duty cycle will + * be changed. + */ + +#define LEDC_DUTY_NUM_CH3 0x000003FF +#define LEDC_DUTY_NUM_CH3_M (LEDC_DUTY_NUM_CH3_V << LEDC_DUTY_NUM_CH3_S) +#define LEDC_DUTY_NUM_CH3_V 0x000003FF +#define LEDC_DUTY_NUM_CH3_S 20 + +/* LEDC_DUTY_INC_CH3 : R/W; bitpos: [30]; default: 1; + * This register is used to increase or decrease the duty of output signal + * on channel 3. 1: Increase;0: Decrease. + */ + +#define LEDC_DUTY_INC_CH3 (BIT(30)) +#define LEDC_DUTY_INC_CH3_M (LEDC_DUTY_INC_CH3_V << LEDC_DUTY_INC_CH3_S) +#define LEDC_DUTY_INC_CH3_V 0x00000001 +#define LEDC_DUTY_INC_CH3_S 30 + +/* LEDC_DUTY_START_CH3 : R/W; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH3_CONF1_REG will start to take effect + * when this bit is set to 1. + */ + +#define LEDC_DUTY_START_CH3 (BIT(31)) +#define LEDC_DUTY_START_CH3_M (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S) +#define LEDC_DUTY_START_CH3_V 0x00000001 +#define LEDC_DUTY_START_CH3_S 31 + +/* LEDC_CH3_DUTY_R_REG register + * Current duty cycle for channel 3 + */ + +#define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c) + +/* LEDC_DUTY_R_CH3 : RO; bitpos: [18:0]; default: 0; + * This register stores the current duty of output signal on channel 3. + */ + +#define LEDC_DUTY_R_CH3 0x0007FFFF +#define LEDC_DUTY_R_CH3_M (LEDC_DUTY_R_CH3_V << LEDC_DUTY_R_CH3_S) +#define LEDC_DUTY_R_CH3_V 0x0007FFFF +#define LEDC_DUTY_R_CH3_S 0 + +/* LEDC_CH4_CONF0_REG register + * Configuration register 0 for channel 4 + */ + +#define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50) + +/* LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 4. + * + * 0: select timer0 + * + * 1: select timer1 + * + * 2: select timer2 + * + * 3: select timer3 + */ + +#define LEDC_TIMER_SEL_CH4 0x00000003 +#define LEDC_TIMER_SEL_CH4_M (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S) +#define LEDC_TIMER_SEL_CH4_V 0x00000003 +#define LEDC_TIMER_SEL_CH4_S 0 + +/* LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 4. + */ + +#define LEDC_SIG_OUT_EN_CH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH4_M (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S) +#define LEDC_SIG_OUT_EN_CH4_V 0x00000001 +#define LEDC_SIG_OUT_EN_CH4_S 2 + +/* LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 4 is inactive. + */ + +#define LEDC_IDLE_LV_CH4 (BIT(3)) +#define LEDC_IDLE_LV_CH4_M (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S) +#define LEDC_IDLE_LV_CH4_V 0x00000001 +#define LEDC_IDLE_LV_CH4_S 3 + +/* LEDC_PARA_UP_CH4 : WO; bitpos: [4]; default: 0; + * This bit is used to update register LEDC_CH4_HPOINT and LEDC_CH4_DUTY for + * channel 4. + */ + +#define LEDC_PARA_UP_CH4 (BIT(4)) +#define LEDC_PARA_UP_CH4_M (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S) +#define LEDC_PARA_UP_CH4_V 0x00000001 +#define LEDC_PARA_UP_CH4_S 4 + +/* LEDC_OVF_NUM_CH4 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH4_INT interrupt will be triggered when channel 4 + * overflows for (LEDC_OVF_NUM_CH4 + 1) times. + */ + +#define LEDC_OVF_NUM_CH4 0x000003FF +#define LEDC_OVF_NUM_CH4_M (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S) +#define LEDC_OVF_NUM_CH4_V 0x000003FF +#define LEDC_OVF_NUM_CH4_S 5 + +/* LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 4. + */ + +#define LEDC_OVF_CNT_EN_CH4 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH4_M (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S) +#define LEDC_OVF_CNT_EN_CH4_V 0x00000001 +#define LEDC_OVF_CNT_EN_CH4_S 15 + +/* LEDC_OVF_CNT_RESET_CH4 : WO; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 4. + */ + +#define LEDC_OVF_CNT_RESET_CH4 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH4_M (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S) +#define LEDC_OVF_CNT_RESET_CH4_V 0x00000001 +#define LEDC_OVF_CNT_RESET_CH4_S 16 + +/* LEDC_OVF_CNT_RESET_ST_CH4 : RO; bitpos: [17]; default: 0; + * This is the status bit of LEDC_OVF_CNT_RESET_CH4. + */ + +#define LEDC_OVF_CNT_RESET_ST_CH4 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_CH4_M (LEDC_OVF_CNT_RESET_ST_CH4_V << LEDC_OVF_CNT_RESET_ST_CH4_S) +#define LEDC_OVF_CNT_RESET_ST_CH4_V 0x00000001 +#define LEDC_OVF_CNT_RESET_ST_CH4_S 17 + +/* LEDC_CH4_HPOINT_REG register + * High point register for channel 4 + */ + +#define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54) + +/* LEDC_HPOINT_CH4 : R/W; bitpos: [13:0]; default: 0; + * The output value changes to high when the selected timers has reached the + * value specified by this register. + */ + +#define LEDC_HPOINT_CH4 0x00003FFF +#define LEDC_HPOINT_CH4_M (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S) +#define LEDC_HPOINT_CH4_V 0x00003FFF +#define LEDC_HPOINT_CH4_S 0 + +/* LEDC_CH4_DUTY_REG register + * Initial duty cycle for channel 4 + */ + +#define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58) + +/* LEDC_DUTY_CH4 : R/W; bitpos: [18:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the + * Lpoint. + */ + +#define LEDC_DUTY_CH4 0x0007FFFF +#define LEDC_DUTY_CH4_M (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S) +#define LEDC_DUTY_CH4_V 0x0007FFFF +#define LEDC_DUTY_CH4_S 0 + +/* LEDC_CH4_CONF1_REG register + * Configuration register 1 for channel 4 + */ + +#define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c) + +/* LEDC_DUTY_SCALE_CH4 : R/W; bitpos: [9:0]; default: 0; + * This register is used to configure the changing step scale of duty on + * channel 4. + */ + +#define LEDC_DUTY_SCALE_CH4 0x000003FF +#define LEDC_DUTY_SCALE_CH4_M (LEDC_DUTY_SCALE_CH4_V << LEDC_DUTY_SCALE_CH4_S) +#define LEDC_DUTY_SCALE_CH4_V 0x000003FF +#define LEDC_DUTY_SCALE_CH4_S 0 + +/* LEDC_DUTY_CYCLE_CH4 : R/W; bitpos: [19:10]; default: 0; + * The duty will change every LEDC_DUTY_CYCLE_CH4 on channel 4. + */ + +#define LEDC_DUTY_CYCLE_CH4 0x000003FF +#define LEDC_DUTY_CYCLE_CH4_M (LEDC_DUTY_CYCLE_CH4_V << LEDC_DUTY_CYCLE_CH4_S) +#define LEDC_DUTY_CYCLE_CH4_V 0x000003FF +#define LEDC_DUTY_CYCLE_CH4_S 10 + +/* LEDC_DUTY_NUM_CH4 : R/W; bitpos: [29:20]; default: 0; + * This register is used to control the number of times the duty cycle will + * be changed. + */ + +#define LEDC_DUTY_NUM_CH4 0x000003FF +#define LEDC_DUTY_NUM_CH4_M (LEDC_DUTY_NUM_CH4_V << LEDC_DUTY_NUM_CH4_S) +#define LEDC_DUTY_NUM_CH4_V 0x000003FF +#define LEDC_DUTY_NUM_CH4_S 20 + +/* LEDC_DUTY_INC_CH4 : R/W; bitpos: [30]; default: 1; + * This register is used to increase or decrease the duty of output signal + * on channel 4. 1: Increase;0: Decrease. + */ + +#define LEDC_DUTY_INC_CH4 (BIT(30)) +#define LEDC_DUTY_INC_CH4_M (LEDC_DUTY_INC_CH4_V << LEDC_DUTY_INC_CH4_S) +#define LEDC_DUTY_INC_CH4_V 0x00000001 +#define LEDC_DUTY_INC_CH4_S 30 + +/* LEDC_DUTY_START_CH4 : R/W; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH4_CONF1_REG will start to take effect + * when this bit is set to 1. + */ + +#define LEDC_DUTY_START_CH4 (BIT(31)) +#define LEDC_DUTY_START_CH4_M (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S) +#define LEDC_DUTY_START_CH4_V 0x00000001 +#define LEDC_DUTY_START_CH4_S 31 + +/* LEDC_CH4_DUTY_R_REG register + * Current duty cycle for channel 4 + */ + +#define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60) + +/* LEDC_DUTY_R_CH4 : RO; bitpos: [18:0]; default: 0; + * This register stores the current duty of output signal on channel 4. + */ + +#define LEDC_DUTY_R_CH4 0x0007FFFF +#define LEDC_DUTY_R_CH4_M (LEDC_DUTY_R_CH4_V << LEDC_DUTY_R_CH4_S) +#define LEDC_DUTY_R_CH4_V 0x0007FFFF +#define LEDC_DUTY_R_CH4_S 0 + +/* LEDC_CH5_CONF0_REG register + * Configuration register 0 for channel 5 + */ + +#define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64) + +/* LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 5. + * + * 0: select timer0 + * + * 1: select timer1 + * + * 2: select timer2 + * + * 3: select timer3 + */ + +#define LEDC_TIMER_SEL_CH5 0x00000003 +#define LEDC_TIMER_SEL_CH5_M (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S) +#define LEDC_TIMER_SEL_CH5_V 0x00000003 +#define LEDC_TIMER_SEL_CH5_S 0 + +/* LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 5. + */ + +#define LEDC_SIG_OUT_EN_CH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH5_M (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S) +#define LEDC_SIG_OUT_EN_CH5_V 0x00000001 +#define LEDC_SIG_OUT_EN_CH5_S 2 + +/* LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 5 is inactive. + */ + +#define LEDC_IDLE_LV_CH5 (BIT(3)) +#define LEDC_IDLE_LV_CH5_M (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S) +#define LEDC_IDLE_LV_CH5_V 0x00000001 +#define LEDC_IDLE_LV_CH5_S 3 + +/* LEDC_PARA_UP_CH5 : WO; bitpos: [4]; default: 0; + * This bit is used to update register LEDC_CH5_HPOINT and LEDC_CH5_DUTY for + * channel 5. + */ + +#define LEDC_PARA_UP_CH5 (BIT(4)) +#define LEDC_PARA_UP_CH5_M (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S) +#define LEDC_PARA_UP_CH5_V 0x00000001 +#define LEDC_PARA_UP_CH5_S 4 + +/* LEDC_OVF_NUM_CH5 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH5_INT interrupt will be triggered when channel 5 + * overflows for (LEDC_OVF_NUM_CH5 + 1) times. + */ + +#define LEDC_OVF_NUM_CH5 0x000003FF +#define LEDC_OVF_NUM_CH5_M (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S) +#define LEDC_OVF_NUM_CH5_V 0x000003FF +#define LEDC_OVF_NUM_CH5_S 5 + +/* LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 5. + */ + +#define LEDC_OVF_CNT_EN_CH5 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH5_M (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S) +#define LEDC_OVF_CNT_EN_CH5_V 0x00000001 +#define LEDC_OVF_CNT_EN_CH5_S 15 + +/* LEDC_OVF_CNT_RESET_CH5 : WO; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 5. + */ + +#define LEDC_OVF_CNT_RESET_CH5 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH5_M (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S) +#define LEDC_OVF_CNT_RESET_CH5_V 0x00000001 +#define LEDC_OVF_CNT_RESET_CH5_S 16 + +/* LEDC_OVF_CNT_RESET_ST_CH5 : RO; bitpos: [17]; default: 0; + * This is the status bit of LEDC_OVF_CNT_RESET_CH5. + */ + +#define LEDC_OVF_CNT_RESET_ST_CH5 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_CH5_M (LEDC_OVF_CNT_RESET_ST_CH5_V << LEDC_OVF_CNT_RESET_ST_CH5_S) +#define LEDC_OVF_CNT_RESET_ST_CH5_V 0x00000001 +#define LEDC_OVF_CNT_RESET_ST_CH5_S 17 + +/* LEDC_CH5_HPOINT_REG register + * High point register for channel 5 + */ + +#define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68) + +/* LEDC_HPOINT_CH5 : R/W; bitpos: [13:0]; default: 0; + * The output value changes to high when the selected timers has reached the + * value specified by this register. + */ + +#define LEDC_HPOINT_CH5 0x00003FFF +#define LEDC_HPOINT_CH5_M (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S) +#define LEDC_HPOINT_CH5_V 0x00003FFF +#define LEDC_HPOINT_CH5_S 0 + +/* LEDC_CH5_DUTY_REG register + * Initial duty cycle for channel 5 + */ + +#define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c) + +/* LEDC_DUTY_CH5 : R/W; bitpos: [18:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the + * Lpoint. + */ + +#define LEDC_DUTY_CH5 0x0007FFFF +#define LEDC_DUTY_CH5_M (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S) +#define LEDC_DUTY_CH5_V 0x0007FFFF +#define LEDC_DUTY_CH5_S 0 + +/* LEDC_CH5_CONF1_REG register + * Configuration register 1 for channel 5 + */ + +#define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70) + +/* LEDC_DUTY_SCALE_CH5 : R/W; bitpos: [9:0]; default: 0; + * This register is used to configure the changing step scale of duty on + * channel 5. + */ + +#define LEDC_DUTY_SCALE_CH5 0x000003FF +#define LEDC_DUTY_SCALE_CH5_M (LEDC_DUTY_SCALE_CH5_V << LEDC_DUTY_SCALE_CH5_S) +#define LEDC_DUTY_SCALE_CH5_V 0x000003FF +#define LEDC_DUTY_SCALE_CH5_S 0 + +/* LEDC_DUTY_CYCLE_CH5 : R/W; bitpos: [19:10]; default: 0; + * The duty will change every LEDC_DUTY_CYCLE_CH5 on channel 5. + */ + +#define LEDC_DUTY_CYCLE_CH5 0x000003FF +#define LEDC_DUTY_CYCLE_CH5_M (LEDC_DUTY_CYCLE_CH5_V << LEDC_DUTY_CYCLE_CH5_S) +#define LEDC_DUTY_CYCLE_CH5_V 0x000003FF +#define LEDC_DUTY_CYCLE_CH5_S 10 + +/* LEDC_DUTY_NUM_CH5 : R/W; bitpos: [29:20]; default: 0; + * This register is used to control the number of times the duty cycle will + * be changed. + */ + +#define LEDC_DUTY_NUM_CH5 0x000003FF +#define LEDC_DUTY_NUM_CH5_M (LEDC_DUTY_NUM_CH5_V << LEDC_DUTY_NUM_CH5_S) +#define LEDC_DUTY_NUM_CH5_V 0x000003FF +#define LEDC_DUTY_NUM_CH5_S 20 + +/* LEDC_DUTY_INC_CH5 : R/W; bitpos: [30]; default: 1; + * This register is used to increase or decrease the duty of output signal + * on channel 5. 1: Increase;0: Decrease. + */ + +#define LEDC_DUTY_INC_CH5 (BIT(30)) +#define LEDC_DUTY_INC_CH5_M (LEDC_DUTY_INC_CH5_V << LEDC_DUTY_INC_CH5_S) +#define LEDC_DUTY_INC_CH5_V 0x00000001 +#define LEDC_DUTY_INC_CH5_S 30 + +/* LEDC_DUTY_START_CH5 : R/W; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH5_CONF1_REG will start to take effect + * when this bit is set to 1. + */ + +#define LEDC_DUTY_START_CH5 (BIT(31)) +#define LEDC_DUTY_START_CH5_M (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S) +#define LEDC_DUTY_START_CH5_V 0x00000001 +#define LEDC_DUTY_START_CH5_S 31 + +/* LEDC_CH5_DUTY_R_REG register + * Current duty cycle for channel 5 + */ + +#define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74) + +/* LEDC_DUTY_R_CH5 : RO; bitpos: [18:0]; default: 0; + * This register stores the current duty of output signal on channel 5. + */ + +#define LEDC_DUTY_R_CH5 0x0007FFFF +#define LEDC_DUTY_R_CH5_M (LEDC_DUTY_R_CH5_V << LEDC_DUTY_R_CH5_S) +#define LEDC_DUTY_R_CH5_V 0x0007FFFF +#define LEDC_DUTY_R_CH5_S 0 + +/* LEDC_CH6_CONF0_REG register + * Configuration register 0 for channel 6 + */ + +#define LEDC_CH6_CONF0_REG (DR_REG_LEDC_BASE + 0x78) + +/* LEDC_TIMER_SEL_CH6 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 6. + * + * 0: select timer0 + * + * 1: select timer1 + * + * 2: select timer2 + * + * 3: select timer3 + */ + +#define LEDC_TIMER_SEL_CH6 0x00000003 +#define LEDC_TIMER_SEL_CH6_M (LEDC_TIMER_SEL_CH6_V << LEDC_TIMER_SEL_CH6_S) +#define LEDC_TIMER_SEL_CH6_V 0x00000003 +#define LEDC_TIMER_SEL_CH6_S 0 + +/* LEDC_SIG_OUT_EN_CH6 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 6. + */ + +#define LEDC_SIG_OUT_EN_CH6 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH6_M (LEDC_SIG_OUT_EN_CH6_V << LEDC_SIG_OUT_EN_CH6_S) +#define LEDC_SIG_OUT_EN_CH6_V 0x00000001 +#define LEDC_SIG_OUT_EN_CH6_S 2 + +/* LEDC_IDLE_LV_CH6 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 6 is inactive. + */ + +#define LEDC_IDLE_LV_CH6 (BIT(3)) +#define LEDC_IDLE_LV_CH6_M (LEDC_IDLE_LV_CH6_V << LEDC_IDLE_LV_CH6_S) +#define LEDC_IDLE_LV_CH6_V 0x00000001 +#define LEDC_IDLE_LV_CH6_S 3 + +/* LEDC_PARA_UP_CH6 : WO; bitpos: [4]; default: 0; + * This bit is used to update register LEDC_CH6_HPOINT and LEDC_CH6_DUTY for + * channel 6. + */ + +#define LEDC_PARA_UP_CH6 (BIT(4)) +#define LEDC_PARA_UP_CH6_M (LEDC_PARA_UP_CH6_V << LEDC_PARA_UP_CH6_S) +#define LEDC_PARA_UP_CH6_V 0x00000001 +#define LEDC_PARA_UP_CH6_S 4 + +/* LEDC_OVF_NUM_CH6 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH6_INT interrupt will be triggered when channel 6 + * overflows for (LEDC_OVF_NUM_CH6 + 1) times. + */ + +#define LEDC_OVF_NUM_CH6 0x000003FF +#define LEDC_OVF_NUM_CH6_M (LEDC_OVF_NUM_CH6_V << LEDC_OVF_NUM_CH6_S) +#define LEDC_OVF_NUM_CH6_V 0x000003FF +#define LEDC_OVF_NUM_CH6_S 5 + +/* LEDC_OVF_CNT_EN_CH6 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 6. + */ + +#define LEDC_OVF_CNT_EN_CH6 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH6_M (LEDC_OVF_CNT_EN_CH6_V << LEDC_OVF_CNT_EN_CH6_S) +#define LEDC_OVF_CNT_EN_CH6_V 0x00000001 +#define LEDC_OVF_CNT_EN_CH6_S 15 + +/* LEDC_OVF_CNT_RESET_CH6 : WO; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 6. + */ + +#define LEDC_OVF_CNT_RESET_CH6 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH6_M (LEDC_OVF_CNT_RESET_CH6_V << LEDC_OVF_CNT_RESET_CH6_S) +#define LEDC_OVF_CNT_RESET_CH6_V 0x00000001 +#define LEDC_OVF_CNT_RESET_CH6_S 16 + +/* LEDC_OVF_CNT_RESET_ST_CH6 : RO; bitpos: [17]; default: 0; + * This is the status bit of LEDC_OVF_CNT_RESET_CH6. + */ + +#define LEDC_OVF_CNT_RESET_ST_CH6 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_CH6_M (LEDC_OVF_CNT_RESET_ST_CH6_V << LEDC_OVF_CNT_RESET_ST_CH6_S) +#define LEDC_OVF_CNT_RESET_ST_CH6_V 0x00000001 +#define LEDC_OVF_CNT_RESET_ST_CH6_S 17 + +/* LEDC_CH6_HPOINT_REG register + * High point register for channel 6 + */ + +#define LEDC_CH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x7c) + +/* LEDC_HPOINT_CH6 : R/W; bitpos: [13:0]; default: 0; + * The output value changes to high when the selected timers has reached the + * value specified by this register. + */ + +#define LEDC_HPOINT_CH6 0x00003FFF +#define LEDC_HPOINT_CH6_M (LEDC_HPOINT_CH6_V << LEDC_HPOINT_CH6_S) +#define LEDC_HPOINT_CH6_V 0x00003FFF +#define LEDC_HPOINT_CH6_S 0 + +/* LEDC_CH6_DUTY_REG register + * Initial duty cycle for channel 6 + */ + +#define LEDC_CH6_DUTY_REG (DR_REG_LEDC_BASE + 0x80) + +/* LEDC_DUTY_CH6 : R/W; bitpos: [18:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the + * Lpoint. + */ + +#define LEDC_DUTY_CH6 0x0007FFFF +#define LEDC_DUTY_CH6_M (LEDC_DUTY_CH6_V << LEDC_DUTY_CH6_S) +#define LEDC_DUTY_CH6_V 0x0007FFFF +#define LEDC_DUTY_CH6_S 0 + +/* LEDC_CH6_CONF1_REG register + * Configuration register 1 for channel 6 + */ + +#define LEDC_CH6_CONF1_REG (DR_REG_LEDC_BASE + 0x84) + +/* LEDC_DUTY_SCALE_CH6 : R/W; bitpos: [9:0]; default: 0; + * This register is used to configure the changing step scale of duty on + * channel 6. + */ + +#define LEDC_DUTY_SCALE_CH6 0x000003FF +#define LEDC_DUTY_SCALE_CH6_M (LEDC_DUTY_SCALE_CH6_V << LEDC_DUTY_SCALE_CH6_S) +#define LEDC_DUTY_SCALE_CH6_V 0x000003FF +#define LEDC_DUTY_SCALE_CH6_S 0 + +/* LEDC_DUTY_CYCLE_CH6 : R/W; bitpos: [19:10]; default: 0; + * The duty will change every LEDC_DUTY_CYCLE_CH6 on channel 6. + */ + +#define LEDC_DUTY_CYCLE_CH6 0x000003FF +#define LEDC_DUTY_CYCLE_CH6_M (LEDC_DUTY_CYCLE_CH6_V << LEDC_DUTY_CYCLE_CH6_S) +#define LEDC_DUTY_CYCLE_CH6_V 0x000003FF +#define LEDC_DUTY_CYCLE_CH6_S 10 + +/* LEDC_DUTY_NUM_CH6 : R/W; bitpos: [29:20]; default: 0; + * This register is used to control the number of times the duty cycle will + * be changed. + */ + +#define LEDC_DUTY_NUM_CH6 0x000003FF +#define LEDC_DUTY_NUM_CH6_M (LEDC_DUTY_NUM_CH6_V << LEDC_DUTY_NUM_CH6_S) +#define LEDC_DUTY_NUM_CH6_V 0x000003FF +#define LEDC_DUTY_NUM_CH6_S 20 + +/* LEDC_DUTY_INC_CH6 : R/W; bitpos: [30]; default: 1; + * This register is used to increase or decrease the duty of output signal + * on channel 6. 1: Increase;0: Decrease. + */ + +#define LEDC_DUTY_INC_CH6 (BIT(30)) +#define LEDC_DUTY_INC_CH6_M (LEDC_DUTY_INC_CH6_V << LEDC_DUTY_INC_CH6_S) +#define LEDC_DUTY_INC_CH6_V 0x00000001 +#define LEDC_DUTY_INC_CH6_S 30 + +/* LEDC_DUTY_START_CH6 : R/W; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH6_CONF1_REG will start to take effect + * when this bit is set to 1. + */ + +#define LEDC_DUTY_START_CH6 (BIT(31)) +#define LEDC_DUTY_START_CH6_M (LEDC_DUTY_START_CH6_V << LEDC_DUTY_START_CH6_S) +#define LEDC_DUTY_START_CH6_V 0x00000001 +#define LEDC_DUTY_START_CH6_S 31 + +/* LEDC_CH6_DUTY_R_REG register + * Current duty cycle for channel 6 + */ + +#define LEDC_CH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x88) + +/* LEDC_DUTY_R_CH6 : RO; bitpos: [18:0]; default: 0; + * This register stores the current duty of output signal on channel 6. + */ + +#define LEDC_DUTY_R_CH6 0x0007FFFF +#define LEDC_DUTY_R_CH6_M (LEDC_DUTY_R_CH6_V << LEDC_DUTY_R_CH6_S) +#define LEDC_DUTY_R_CH6_V 0x0007FFFF +#define LEDC_DUTY_R_CH6_S 0 + +/* LEDC_CH7_CONF0_REG register + * Configuration register 0 for channel 7 + */ + +#define LEDC_CH7_CONF0_REG (DR_REG_LEDC_BASE + 0x8c) + +/* LEDC_TIMER_SEL_CH7 : R/W; bitpos: [1:0]; default: 0; + * This field is used to select one of timers for channel 7. + * + * 0: select timer0 + * + * 1: select timer1 + * + * 2: select timer2 + * + * 3: select timer3 + */ + +#define LEDC_TIMER_SEL_CH7 0x00000003 +#define LEDC_TIMER_SEL_CH7_M (LEDC_TIMER_SEL_CH7_V << LEDC_TIMER_SEL_CH7_S) +#define LEDC_TIMER_SEL_CH7_V 0x00000003 +#define LEDC_TIMER_SEL_CH7_S 0 + +/* LEDC_SIG_OUT_EN_CH7 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable signal output on channel 7. + */ + +#define LEDC_SIG_OUT_EN_CH7 (BIT(2)) +#define LEDC_SIG_OUT_EN_CH7_M (LEDC_SIG_OUT_EN_CH7_V << LEDC_SIG_OUT_EN_CH7_S) +#define LEDC_SIG_OUT_EN_CH7_V 0x00000001 +#define LEDC_SIG_OUT_EN_CH7_S 2 + +/* LEDC_IDLE_LV_CH7 : R/W; bitpos: [3]; default: 0; + * This bit is used to control the output value when channel 7 is inactive. + */ + +#define LEDC_IDLE_LV_CH7 (BIT(3)) +#define LEDC_IDLE_LV_CH7_M (LEDC_IDLE_LV_CH7_V << LEDC_IDLE_LV_CH7_S) +#define LEDC_IDLE_LV_CH7_V 0x00000001 +#define LEDC_IDLE_LV_CH7_S 3 + +/* LEDC_PARA_UP_CH7 : WO; bitpos: [4]; default: 0; + * This bit is used to update register LEDC_CH7_HPOINT and LEDC_CH7_DUTY for + * channel 7. + */ + +#define LEDC_PARA_UP_CH7 (BIT(4)) +#define LEDC_PARA_UP_CH7_M (LEDC_PARA_UP_CH7_V << LEDC_PARA_UP_CH7_S) +#define LEDC_PARA_UP_CH7_V 0x00000001 +#define LEDC_PARA_UP_CH7_S 4 + +/* LEDC_OVF_NUM_CH7 : R/W; bitpos: [14:5]; default: 0; + * This register is used to configure the maximum times of overflow minus 1. + * + * The LEDC_OVF_CNT_CH7_INT interrupt will be triggered when channel 7 + * overflows for (LEDC_OVF_NUM_CH7 + 1) times. + */ + +#define LEDC_OVF_NUM_CH7 0x000003FF +#define LEDC_OVF_NUM_CH7_M (LEDC_OVF_NUM_CH7_V << LEDC_OVF_NUM_CH7_S) +#define LEDC_OVF_NUM_CH7_V 0x000003FF +#define LEDC_OVF_NUM_CH7_S 5 + +/* LEDC_OVF_CNT_EN_CH7 : R/W; bitpos: [15]; default: 0; + * This bit is used to enable the ovf_cnt of channel 7. + */ + +#define LEDC_OVF_CNT_EN_CH7 (BIT(15)) +#define LEDC_OVF_CNT_EN_CH7_M (LEDC_OVF_CNT_EN_CH7_V << LEDC_OVF_CNT_EN_CH7_S) +#define LEDC_OVF_CNT_EN_CH7_V 0x00000001 +#define LEDC_OVF_CNT_EN_CH7_S 15 + +/* LEDC_OVF_CNT_RESET_CH7 : WO; bitpos: [16]; default: 0; + * Set this bit to reset the ovf_cnt of channel 7. + */ + +#define LEDC_OVF_CNT_RESET_CH7 (BIT(16)) +#define LEDC_OVF_CNT_RESET_CH7_M (LEDC_OVF_CNT_RESET_CH7_V << LEDC_OVF_CNT_RESET_CH7_S) +#define LEDC_OVF_CNT_RESET_CH7_V 0x00000001 +#define LEDC_OVF_CNT_RESET_CH7_S 16 + +/* LEDC_OVF_CNT_RESET_ST_CH7 : RO; bitpos: [17]; default: 0; + * This is the status bit of LEDC_OVF_CNT_RESET_CH7. + */ + +#define LEDC_OVF_CNT_RESET_ST_CH7 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_CH7_M (LEDC_OVF_CNT_RESET_ST_CH7_V << LEDC_OVF_CNT_RESET_ST_CH7_S) +#define LEDC_OVF_CNT_RESET_ST_CH7_V 0x00000001 +#define LEDC_OVF_CNT_RESET_ST_CH7_S 17 + +/* LEDC_CH7_HPOINT_REG register + * High point register for channel 7 + */ + +#define LEDC_CH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x90) + +/* LEDC_HPOINT_CH7 : R/W; bitpos: [13:0]; default: 0; + * The output value changes to high when the selected timers has reached the + * value specified by this register. + */ + +#define LEDC_HPOINT_CH7 0x00003FFF +#define LEDC_HPOINT_CH7_M (LEDC_HPOINT_CH7_V << LEDC_HPOINT_CH7_S) +#define LEDC_HPOINT_CH7_V 0x00003FFF +#define LEDC_HPOINT_CH7_S 0 + +/* LEDC_CH7_DUTY_REG register + * Initial duty cycle for channel 7 + */ + +#define LEDC_CH7_DUTY_REG (DR_REG_LEDC_BASE + 0x94) + +/* LEDC_DUTY_CH7 : R/W; bitpos: [18:0]; default: 0; + * This register is used to change the output duty by controlling the Lpoint. + * + * The output value turns to low when the selected timers has reached the + * Lpoint. + */ + +#define LEDC_DUTY_CH7 0x0007FFFF +#define LEDC_DUTY_CH7_M (LEDC_DUTY_CH7_V << LEDC_DUTY_CH7_S) +#define LEDC_DUTY_CH7_V 0x0007FFFF +#define LEDC_DUTY_CH7_S 0 + +/* LEDC_CH7_CONF1_REG register + * Configuration register 1 for channel 7 + */ + +#define LEDC_CH7_CONF1_REG (DR_REG_LEDC_BASE + 0x98) + +/* LEDC_DUTY_SCALE_CH7 : R/W; bitpos: [9:0]; default: 0; + * This register is used to configure the changing step scale of duty on + * channel 7. + */ + +#define LEDC_DUTY_SCALE_CH7 0x000003FF +#define LEDC_DUTY_SCALE_CH7_M (LEDC_DUTY_SCALE_CH7_V << LEDC_DUTY_SCALE_CH7_S) +#define LEDC_DUTY_SCALE_CH7_V 0x000003FF +#define LEDC_DUTY_SCALE_CH7_S 0 + +/* LEDC_DUTY_CYCLE_CH7 : R/W; bitpos: [19:10]; default: 0; + * The duty will change every LEDC_DUTY_CYCLE_CH7 on channel 7. + */ + +#define LEDC_DUTY_CYCLE_CH7 0x000003FF +#define LEDC_DUTY_CYCLE_CH7_M (LEDC_DUTY_CYCLE_CH7_V << LEDC_DUTY_CYCLE_CH7_S) +#define LEDC_DUTY_CYCLE_CH7_V 0x000003FF +#define LEDC_DUTY_CYCLE_CH7_S 10 + +/* LEDC_DUTY_NUM_CH7 : R/W; bitpos: [29:20]; default: 0; + * This register is used to control the number of times the duty cycle will + * be changed. + */ + +#define LEDC_DUTY_NUM_CH7 0x000003FF +#define LEDC_DUTY_NUM_CH7_M (LEDC_DUTY_NUM_CH7_V << LEDC_DUTY_NUM_CH7_S) +#define LEDC_DUTY_NUM_CH7_V 0x000003FF +#define LEDC_DUTY_NUM_CH7_S 20 + +/* LEDC_DUTY_INC_CH7 : R/W; bitpos: [30]; default: 1; + * This register is used to increase or decrease the duty of output signal + * on channel 7. 1: Increase;0: Decrease. + */ + +#define LEDC_DUTY_INC_CH7 (BIT(30)) +#define LEDC_DUTY_INC_CH7_M (LEDC_DUTY_INC_CH7_V << LEDC_DUTY_INC_CH7_S) +#define LEDC_DUTY_INC_CH7_V 0x00000001 +#define LEDC_DUTY_INC_CH7_S 30 + +/* LEDC_DUTY_START_CH7 : R/W; bitpos: [31]; default: 0; + * Other configured fields in LEDC_CH7_CONF1_REG will start to take effect + * when this bit is set to 1. + */ + +#define LEDC_DUTY_START_CH7 (BIT(31)) +#define LEDC_DUTY_START_CH7_M (LEDC_DUTY_START_CH7_V << LEDC_DUTY_START_CH7_S) +#define LEDC_DUTY_START_CH7_V 0x00000001 +#define LEDC_DUTY_START_CH7_S 31 + +/* LEDC_CH7_DUTY_R_REG register + * Current duty cycle for channel 7 + */ + +#define LEDC_CH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x9c) + +/* LEDC_DUTY_R_CH7 : RO; bitpos: [18:0]; default: 0; + * This register stores the current duty of output signal on channel 7. + */ + +#define LEDC_DUTY_R_CH7 0x0007FFFF +#define LEDC_DUTY_R_CH7_M (LEDC_DUTY_R_CH7_V << LEDC_DUTY_R_CH7_S) +#define LEDC_DUTY_R_CH7_V 0x0007FFFF +#define LEDC_DUTY_R_CH7_S 0 + +/* LEDC_TIMER0_CONF_REG register + * Timer 0 configuration + */ + +#define LEDC_TIMER0_CONF_REG (DR_REG_LEDC_BASE + 0xa0) + +/* LEDC_TIMER0_DUTY_RES : R/W; bitpos: [3:0]; default: 0; + * This register is used to control the range of the counter in timer 0. + */ + +#define LEDC_TIMER0_DUTY_RES 0x0000000F +#define LEDC_TIMER0_DUTY_RES_M (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S) +#define LEDC_TIMER0_DUTY_RES_V 0x0000000F +#define LEDC_TIMER0_DUTY_RES_S 0 + +/* LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [21:4]; default: 0; + * This register is used to configure the divisor for the divider in timer 0. + * + * The least significant eight bits represent the fractional part. + */ + +#define LEDC_CLK_DIV_TIMER0 0x0003FFFF +#define LEDC_CLK_DIV_TIMER0_M (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S) +#define LEDC_CLK_DIV_TIMER0_V 0x0003FFFF +#define LEDC_CLK_DIV_TIMER0_S 4 + +/* LEDC_TIMER0_PAUSE : R/W; bitpos: [22]; default: 0; + * This bit is used to suspend the counter in timer 0. + */ + +#define LEDC_TIMER0_PAUSE (BIT(22)) +#define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) +#define LEDC_TIMER0_PAUSE_V 0x00000001 +#define LEDC_TIMER0_PAUSE_S 22 + +/* LEDC_TIMER0_RST : R/W; bitpos: [23]; default: 1; + * This bit is used to reset timer 0. The counter will show 0 after reset. + */ + +#define LEDC_TIMER0_RST (BIT(23)) +#define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) +#define LEDC_TIMER0_RST_V 0x00000001 +#define LEDC_TIMER0_RST_S 23 + +/* LEDC_TICK_SEL_TIMER0 : R/W; bitpos: [24]; default: 0; + * This bit is used to select clock for timer 0. When this bit is set to 1 + * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not + * accurate. + * + * 1'h0: SLOW_CLK 1'h1: REF_TICK + */ + +#define LEDC_TICK_SEL_TIMER0 (BIT(24)) +#define LEDC_TICK_SEL_TIMER0_M (LEDC_TICK_SEL_TIMER0_V << LEDC_TICK_SEL_TIMER0_S) +#define LEDC_TICK_SEL_TIMER0_V 0x00000001 +#define LEDC_TICK_SEL_TIMER0_S 24 + +/* LEDC_TIMER0_PARA_UP : WO; bitpos: [25]; default: 0; + * Set this bit to update LEDC_CLK_DIV_TIMER0 and LEDC_TIMER0_DUTY_RES. + */ + +#define LEDC_TIMER0_PARA_UP (BIT(25)) +#define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) +#define LEDC_TIMER0_PARA_UP_V 0x00000001 +#define LEDC_TIMER0_PARA_UP_S 25 + +/* LEDC_TIMER0_VALUE_REG register + * Timer 0 current counter value + */ + +#define LEDC_TIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0xa4) + +/* LEDC_TIMER0_CNT : RO; bitpos: [13:0]; default: 0; + * This register stores the current counter value of timer 0. + */ + +#define LEDC_TIMER0_CNT 0x00003FFF +#define LEDC_TIMER0_CNT_M (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S) +#define LEDC_TIMER0_CNT_V 0x00003FFF +#define LEDC_TIMER0_CNT_S 0 + +/* LEDC_TIMER1_CONF_REG register + * Timer 1 configuration + */ + +#define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8) + +/* LEDC_TIMER1_DUTY_RES : R/W; bitpos: [3:0]; default: 0; + * This register is used to control the range of the counter in timer 1. + */ + +#define LEDC_TIMER1_DUTY_RES 0x0000000F +#define LEDC_TIMER1_DUTY_RES_M (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S) +#define LEDC_TIMER1_DUTY_RES_V 0x0000000F +#define LEDC_TIMER1_DUTY_RES_S 0 + +/* LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [21:4]; default: 0; + * This register is used to configure the divisor for the divider in timer 1. + * + * The least significant eight bits represent the fractional part. + */ + +#define LEDC_CLK_DIV_TIMER1 0x0003FFFF +#define LEDC_CLK_DIV_TIMER1_M (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S) +#define LEDC_CLK_DIV_TIMER1_V 0x0003FFFF +#define LEDC_CLK_DIV_TIMER1_S 4 + +/* LEDC_TIMER1_PAUSE : R/W; bitpos: [22]; default: 0; + * This bit is used to suspend the counter in timer 1. + */ + +#define LEDC_TIMER1_PAUSE (BIT(22)) +#define LEDC_TIMER1_PAUSE_M (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S) +#define LEDC_TIMER1_PAUSE_V 0x00000001 +#define LEDC_TIMER1_PAUSE_S 22 + +/* LEDC_TIMER1_RST : R/W; bitpos: [23]; default: 1; + * This bit is used to reset timer 1. The counter will show 0 after reset. + */ + +#define LEDC_TIMER1_RST (BIT(23)) +#define LEDC_TIMER1_RST_M (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S) +#define LEDC_TIMER1_RST_V 0x00000001 +#define LEDC_TIMER1_RST_S 23 + +/* LEDC_TICK_SEL_TIMER1 : R/W; bitpos: [24]; default: 0; + * This bit is used to select clock for timer 1. When this bit is set to 1 + * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not + * accurate. + * + * 1'h0: SLOW_CLK 1'h1: REF_TICK + */ + +#define LEDC_TICK_SEL_TIMER1 (BIT(24)) +#define LEDC_TICK_SEL_TIMER1_M (LEDC_TICK_SEL_TIMER1_V << LEDC_TICK_SEL_TIMER1_S) +#define LEDC_TICK_SEL_TIMER1_V 0x00000001 +#define LEDC_TICK_SEL_TIMER1_S 24 + +/* LEDC_TIMER1_PARA_UP : WO; bitpos: [25]; default: 0; + * Set this bit to update LEDC_CLK_DIV_TIMER1 and LEDC_TIMER1_DUTY_RES. + */ + +#define LEDC_TIMER1_PARA_UP (BIT(25)) +#define LEDC_TIMER1_PARA_UP_M (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S) +#define LEDC_TIMER1_PARA_UP_V 0x00000001 +#define LEDC_TIMER1_PARA_UP_S 25 + +/* LEDC_TIMER1_VALUE_REG register + * Timer 1 current counter value + */ + +#define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac) + +/* LEDC_TIMER1_CNT : RO; bitpos: [13:0]; default: 0; + * This register stores the current counter value of timer 1. + */ + +#define LEDC_TIMER1_CNT 0x00003FFF +#define LEDC_TIMER1_CNT_M (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S) +#define LEDC_TIMER1_CNT_V 0x00003FFF +#define LEDC_TIMER1_CNT_S 0 + +/* LEDC_TIMER2_CONF_REG register + * Timer 2 configuration + */ + +#define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0) + +/* LEDC_TIMER2_DUTY_RES : R/W; bitpos: [3:0]; default: 0; + * This register is used to control the range of the counter in timer 2. + */ + +#define LEDC_TIMER2_DUTY_RES 0x0000000F +#define LEDC_TIMER2_DUTY_RES_M (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S) +#define LEDC_TIMER2_DUTY_RES_V 0x0000000F +#define LEDC_TIMER2_DUTY_RES_S 0 + +/* LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [21:4]; default: 0; + * This register is used to configure the divisor for the divider in timer 2. + * + * The least significant eight bits represent the fractional part. + */ + +#define LEDC_CLK_DIV_TIMER2 0x0003FFFF +#define LEDC_CLK_DIV_TIMER2_M (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S) +#define LEDC_CLK_DIV_TIMER2_V 0x0003FFFF +#define LEDC_CLK_DIV_TIMER2_S 4 + +/* LEDC_TIMER2_PAUSE : R/W; bitpos: [22]; default: 0; + * This bit is used to suspend the counter in timer 2. + */ + +#define LEDC_TIMER2_PAUSE (BIT(22)) +#define LEDC_TIMER2_PAUSE_M (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S) +#define LEDC_TIMER2_PAUSE_V 0x00000001 +#define LEDC_TIMER2_PAUSE_S 22 + +/* LEDC_TIMER2_RST : R/W; bitpos: [23]; default: 1; + * This bit is used to reset timer 2. The counter will show 0 after reset. + */ + +#define LEDC_TIMER2_RST (BIT(23)) +#define LEDC_TIMER2_RST_M (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S) +#define LEDC_TIMER2_RST_V 0x00000001 +#define LEDC_TIMER2_RST_S 23 + +/* LEDC_TICK_SEL_TIMER2 : R/W; bitpos: [24]; default: 0; + * This bit is used to select clock for timer 2. When this bit is set to 1 + * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not + * accurate. + * + * 1'h0: SLOW_CLK 1'h1: REF_TICK + */ + +#define LEDC_TICK_SEL_TIMER2 (BIT(24)) +#define LEDC_TICK_SEL_TIMER2_M (LEDC_TICK_SEL_TIMER2_V << LEDC_TICK_SEL_TIMER2_S) +#define LEDC_TICK_SEL_TIMER2_V 0x00000001 +#define LEDC_TICK_SEL_TIMER2_S 24 + +/* LEDC_TIMER2_PARA_UP : WO; bitpos: [25]; default: 0; + * Set this bit to update LEDC_CLK_DIV_TIMER2 and LEDC_TIMER2_DUTY_RES. + */ + +#define LEDC_TIMER2_PARA_UP (BIT(25)) +#define LEDC_TIMER2_PARA_UP_M (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S) +#define LEDC_TIMER2_PARA_UP_V 0x00000001 +#define LEDC_TIMER2_PARA_UP_S 25 + +/* LEDC_TIMER2_VALUE_REG register + * Timer 2 current counter value + */ + +#define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4) + +/* LEDC_TIMER2_CNT : RO; bitpos: [13:0]; default: 0; + * This register stores the current counter value of timer 2. + */ + +#define LEDC_TIMER2_CNT 0x00003FFF +#define LEDC_TIMER2_CNT_M (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S) +#define LEDC_TIMER2_CNT_V 0x00003FFF +#define LEDC_TIMER2_CNT_S 0 + +/* LEDC_TIMER3_CONF_REG register + * Timer 3 configuration + */ + +#define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8) + +/* LEDC_TIMER3_DUTY_RES : R/W; bitpos: [3:0]; default: 0; + * This register is used to control the range of the counter in timer 3. + */ + +#define LEDC_TIMER3_DUTY_RES 0x0000000F +#define LEDC_TIMER3_DUTY_RES_M (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S) +#define LEDC_TIMER3_DUTY_RES_V 0x0000000F +#define LEDC_TIMER3_DUTY_RES_S 0 + +/* LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [21:4]; default: 0; + * This register is used to configure the divisor for the divider in timer 3. + * + * The least significant eight bits represent the fractional part. + */ + +#define LEDC_CLK_DIV_TIMER3 0x0003FFFF +#define LEDC_CLK_DIV_TIMER3_M (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S) +#define LEDC_CLK_DIV_TIMER3_V 0x0003FFFF +#define LEDC_CLK_DIV_TIMER3_S 4 + +/* LEDC_TIMER3_PAUSE : R/W; bitpos: [22]; default: 0; + * This bit is used to suspend the counter in timer 3. + */ + +#define LEDC_TIMER3_PAUSE (BIT(22)) +#define LEDC_TIMER3_PAUSE_M (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S) +#define LEDC_TIMER3_PAUSE_V 0x00000001 +#define LEDC_TIMER3_PAUSE_S 22 + +/* LEDC_TIMER3_RST : R/W; bitpos: [23]; default: 1; + * This bit is used to reset timer 3. The counter will show 0 after reset. + */ + +#define LEDC_TIMER3_RST (BIT(23)) +#define LEDC_TIMER3_RST_M (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S) +#define LEDC_TIMER3_RST_V 0x00000001 +#define LEDC_TIMER3_RST_S 23 + +/* LEDC_TICK_SEL_TIMER3 : R/W; bitpos: [24]; default: 0; + * This bit is used to select clock for timer 3. When this bit is set to 1 + * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not + * accurate. + * + * 1'h0: SLOW_CLK 1'h1: REF_TICK + */ + +#define LEDC_TICK_SEL_TIMER3 (BIT(24)) +#define LEDC_TICK_SEL_TIMER3_M (LEDC_TICK_SEL_TIMER3_V << LEDC_TICK_SEL_TIMER3_S) +#define LEDC_TICK_SEL_TIMER3_V 0x00000001 +#define LEDC_TICK_SEL_TIMER3_S 24 + +/* LEDC_TIMER3_PARA_UP : WO; bitpos: [25]; default: 0; + * Set this bit to update LEDC_CLK_DIV_TIMER3 and LEDC_TIMER3_DUTY_RES. + */ + +#define LEDC_TIMER3_PARA_UP (BIT(25)) +#define LEDC_TIMER3_PARA_UP_M (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S) +#define LEDC_TIMER3_PARA_UP_V 0x00000001 +#define LEDC_TIMER3_PARA_UP_S 25 + +/* LEDC_TIMER3_VALUE_REG register + * Timer 3 current counter value + */ + +#define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc) + +/* LEDC_TIMER3_CNT : RO; bitpos: [13:0]; default: 0; + * This register stores the current counter value of timer 3. + */ + +#define LEDC_TIMER3_CNT 0x00003FFF +#define LEDC_TIMER3_CNT_M (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S) +#define LEDC_TIMER3_CNT_V 0x00003FFF +#define LEDC_TIMER3_CNT_S 0 + +/* LEDC_INT_RAW_REG register + * Raw interrupt status + */ + +#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0xc0) + +/* LEDC_TIMER0_OVF_INT_RAW : RO; bitpos: [0]; default: 0; + * Triggered when the timer0 has reached its maximum counter value. + */ + +#define LEDC_TIMER0_OVF_INT_RAW (BIT(0)) +#define LEDC_TIMER0_OVF_INT_RAW_M (LEDC_TIMER0_OVF_INT_RAW_V << LEDC_TIMER0_OVF_INT_RAW_S) +#define LEDC_TIMER0_OVF_INT_RAW_V 0x00000001 +#define LEDC_TIMER0_OVF_INT_RAW_S 0 + +/* LEDC_TIMER1_OVF_INT_RAW : RO; bitpos: [1]; default: 0; + * Triggered when the timer1 has reached its maximum counter value. + */ + +#define LEDC_TIMER1_OVF_INT_RAW (BIT(1)) +#define LEDC_TIMER1_OVF_INT_RAW_M (LEDC_TIMER1_OVF_INT_RAW_V << LEDC_TIMER1_OVF_INT_RAW_S) +#define LEDC_TIMER1_OVF_INT_RAW_V 0x00000001 +#define LEDC_TIMER1_OVF_INT_RAW_S 1 + +/* LEDC_TIMER2_OVF_INT_RAW : RO; bitpos: [2]; default: 0; + * Triggered when the timer2 has reached its maximum counter value. + */ + +#define LEDC_TIMER2_OVF_INT_RAW (BIT(2)) +#define LEDC_TIMER2_OVF_INT_RAW_M (LEDC_TIMER2_OVF_INT_RAW_V << LEDC_TIMER2_OVF_INT_RAW_S) +#define LEDC_TIMER2_OVF_INT_RAW_V 0x00000001 +#define LEDC_TIMER2_OVF_INT_RAW_S 2 + +/* LEDC_TIMER3_OVF_INT_RAW : RO; bitpos: [3]; default: 0; + * Triggered when the timer3 has reached its maximum counter value. + */ + +#define LEDC_TIMER3_OVF_INT_RAW (BIT(3)) +#define LEDC_TIMER3_OVF_INT_RAW_M (LEDC_TIMER3_OVF_INT_RAW_V << LEDC_TIMER3_OVF_INT_RAW_S) +#define LEDC_TIMER3_OVF_INT_RAW_V 0x00000001 +#define LEDC_TIMER3_OVF_INT_RAW_S 3 + +/* LEDC_DUTY_CHNG_END_CH0_INT_RAW : RO; bitpos: [4]; default: 0; + * Interrupt raw bit for channel 0. Triggered when the gradual change of + * duty has finished. + */ + +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_M (LEDC_DUTY_CHNG_END_CH0_INT_RAW_V << LEDC_DUTY_CHNG_END_CH0_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_S 4 + +/* LEDC_DUTY_CHNG_END_CH1_INT_RAW : RO; bitpos: [5]; default: 0; + * Interrupt raw bit for channel 1. Triggered when the gradual change of + * duty has finished. + */ + +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_M (LEDC_DUTY_CHNG_END_CH1_INT_RAW_V << LEDC_DUTY_CHNG_END_CH1_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_S 5 + +/* LEDC_DUTY_CHNG_END_CH2_INT_RAW : RO; bitpos: [6]; default: 0; + * Interrupt raw bit for channel 2. Triggered when the gradual change of + * duty has finished. + */ + +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_M (LEDC_DUTY_CHNG_END_CH2_INT_RAW_V << LEDC_DUTY_CHNG_END_CH2_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_S 6 + +/* LEDC_DUTY_CHNG_END_CH3_INT_RAW : RO; bitpos: [7]; default: 0; + * Interrupt raw bit for channel 3. Triggered when the gradual change of + * duty has finished. + */ + +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_M (LEDC_DUTY_CHNG_END_CH3_INT_RAW_V << LEDC_DUTY_CHNG_END_CH3_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_S 7 + +/* LEDC_DUTY_CHNG_END_CH4_INT_RAW : RO; bitpos: [8]; default: 0; + * Interrupt raw bit for channel 4. Triggered when the gradual change of + * duty has finished. + */ + +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_M (LEDC_DUTY_CHNG_END_CH4_INT_RAW_V << LEDC_DUTY_CHNG_END_CH4_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_S 8 + +/* LEDC_DUTY_CHNG_END_CH5_INT_RAW : RO; bitpos: [9]; default: 0; + * Interrupt raw bit for channel 5. Triggered when the gradual change of + * duty has finished. + */ + +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_M (LEDC_DUTY_CHNG_END_CH5_INT_RAW_V << LEDC_DUTY_CHNG_END_CH5_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_S 9 + +/* LEDC_DUTY_CHNG_END_CH6_INT_RAW : RO; bitpos: [10]; default: 0; + * Interrupt raw bit for channel 6. Triggered when the gradual change of + * duty has finished. + */ + +#define LEDC_DUTY_CHNG_END_CH6_INT_RAW (BIT(10)) +#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_M (LEDC_DUTY_CHNG_END_CH6_INT_RAW_V << LEDC_DUTY_CHNG_END_CH6_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_S 10 + +/* LEDC_DUTY_CHNG_END_CH7_INT_RAW : RO; bitpos: [11]; default: 0; + * Interrupt raw bit for channel 7. Triggered when the gradual change of + * duty has finished. + */ + +#define LEDC_DUTY_CHNG_END_CH7_INT_RAW (BIT(11)) +#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_M (LEDC_DUTY_CHNG_END_CH7_INT_RAW_V << LEDC_DUTY_CHNG_END_CH7_INT_RAW_S) +#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_S 11 + +/* LEDC_OVF_CNT_CH0_INT_RAW : RO; bitpos: [12]; default: 0; + * Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached + * the value specified by LEDC_OVF_NUM_CH0. + */ + +#define LEDC_OVF_CNT_CH0_INT_RAW (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_RAW_M (LEDC_OVF_CNT_CH0_INT_RAW_V << LEDC_OVF_CNT_CH0_INT_RAW_S) +#define LEDC_OVF_CNT_CH0_INT_RAW_V 0x00000001 +#define LEDC_OVF_CNT_CH0_INT_RAW_S 12 + +/* LEDC_OVF_CNT_CH1_INT_RAW : RO; bitpos: [13]; default: 0; + * Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached + * the value specified by LEDC_OVF_NUM_CH1. + */ + +#define LEDC_OVF_CNT_CH1_INT_RAW (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_RAW_M (LEDC_OVF_CNT_CH1_INT_RAW_V << LEDC_OVF_CNT_CH1_INT_RAW_S) +#define LEDC_OVF_CNT_CH1_INT_RAW_V 0x00000001 +#define LEDC_OVF_CNT_CH1_INT_RAW_S 13 + +/* LEDC_OVF_CNT_CH2_INT_RAW : RO; bitpos: [14]; default: 0; + * Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached + * the value specified by LEDC_OVF_NUM_CH2. + */ + +#define LEDC_OVF_CNT_CH2_INT_RAW (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_RAW_M (LEDC_OVF_CNT_CH2_INT_RAW_V << LEDC_OVF_CNT_CH2_INT_RAW_S) +#define LEDC_OVF_CNT_CH2_INT_RAW_V 0x00000001 +#define LEDC_OVF_CNT_CH2_INT_RAW_S 14 + +/* LEDC_OVF_CNT_CH3_INT_RAW : RO; bitpos: [15]; default: 0; + * Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached + * the value specified by LEDC_OVF_NUM_CH3. + */ + +#define LEDC_OVF_CNT_CH3_INT_RAW (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_RAW_M (LEDC_OVF_CNT_CH3_INT_RAW_V << LEDC_OVF_CNT_CH3_INT_RAW_S) +#define LEDC_OVF_CNT_CH3_INT_RAW_V 0x00000001 +#define LEDC_OVF_CNT_CH3_INT_RAW_S 15 + +/* LEDC_OVF_CNT_CH4_INT_RAW : RO; bitpos: [16]; default: 0; + * Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached + * the value specified by LEDC_OVF_NUM_CH4. + */ + +#define LEDC_OVF_CNT_CH4_INT_RAW (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_RAW_M (LEDC_OVF_CNT_CH4_INT_RAW_V << LEDC_OVF_CNT_CH4_INT_RAW_S) +#define LEDC_OVF_CNT_CH4_INT_RAW_V 0x00000001 +#define LEDC_OVF_CNT_CH4_INT_RAW_S 16 + +/* LEDC_OVF_CNT_CH5_INT_RAW : RO; bitpos: [17]; default: 0; + * Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached + * the value specified by LEDC_OVF_NUM_CH5. + */ + +#define LEDC_OVF_CNT_CH5_INT_RAW (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_RAW_M (LEDC_OVF_CNT_CH5_INT_RAW_V << LEDC_OVF_CNT_CH5_INT_RAW_S) +#define LEDC_OVF_CNT_CH5_INT_RAW_V 0x00000001 +#define LEDC_OVF_CNT_CH5_INT_RAW_S 17 + +/* LEDC_OVF_CNT_CH6_INT_RAW : RO; bitpos: [18]; default: 0; + * Interrupt raw bit for channel 6. Triggered when the ovf_cnt has reached + * the value specified by LEDC_OVF_NUM_CH6. + */ + +#define LEDC_OVF_CNT_CH6_INT_RAW (BIT(18)) +#define LEDC_OVF_CNT_CH6_INT_RAW_M (LEDC_OVF_CNT_CH6_INT_RAW_V << LEDC_OVF_CNT_CH6_INT_RAW_S) +#define LEDC_OVF_CNT_CH6_INT_RAW_V 0x00000001 +#define LEDC_OVF_CNT_CH6_INT_RAW_S 18 + +/* LEDC_OVF_CNT_CH7_INT_RAW : RO; bitpos: [19]; default: 0; + * Interrupt raw bit for channel 7. Triggered when the ovf_cnt has reached + * the value specified by LEDC_OVF_NUM_CH7. + */ + +#define LEDC_OVF_CNT_CH7_INT_RAW (BIT(19)) +#define LEDC_OVF_CNT_CH7_INT_RAW_M (LEDC_OVF_CNT_CH7_INT_RAW_V << LEDC_OVF_CNT_CH7_INT_RAW_S) +#define LEDC_OVF_CNT_CH7_INT_RAW_V 0x00000001 +#define LEDC_OVF_CNT_CH7_INT_RAW_S 19 + +/* LEDC_INT_ST_REG register + * Masked interrupt status + */ + +#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0xc4) + +/* LEDC_TIMER0_OVF_INT_ST : RO; bitpos: [0]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT + * interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. + */ + +#define LEDC_TIMER0_OVF_INT_ST (BIT(0)) +#define LEDC_TIMER0_OVF_INT_ST_M (LEDC_TIMER0_OVF_INT_ST_V << LEDC_TIMER0_OVF_INT_ST_S) +#define LEDC_TIMER0_OVF_INT_ST_V 0x00000001 +#define LEDC_TIMER0_OVF_INT_ST_S 0 + +/* LEDC_TIMER1_OVF_INT_ST : RO; bitpos: [1]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT + * interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. + */ + +#define LEDC_TIMER1_OVF_INT_ST (BIT(1)) +#define LEDC_TIMER1_OVF_INT_ST_M (LEDC_TIMER1_OVF_INT_ST_V << LEDC_TIMER1_OVF_INT_ST_S) +#define LEDC_TIMER1_OVF_INT_ST_V 0x00000001 +#define LEDC_TIMER1_OVF_INT_ST_S 1 + +/* LEDC_TIMER2_OVF_INT_ST : RO; bitpos: [2]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT + * interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. + */ + +#define LEDC_TIMER2_OVF_INT_ST (BIT(2)) +#define LEDC_TIMER2_OVF_INT_ST_M (LEDC_TIMER2_OVF_INT_ST_V << LEDC_TIMER2_OVF_INT_ST_S) +#define LEDC_TIMER2_OVF_INT_ST_V 0x00000001 +#define LEDC_TIMER2_OVF_INT_ST_S 2 + +/* LEDC_TIMER3_OVF_INT_ST : RO; bitpos: [3]; default: 0; + * This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT + * interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. + */ + +#define LEDC_TIMER3_OVF_INT_ST (BIT(3)) +#define LEDC_TIMER3_OVF_INT_ST_M (LEDC_TIMER3_OVF_INT_ST_V << LEDC_TIMER3_OVF_INT_ST_S) +#define LEDC_TIMER3_OVF_INT_ST_V 0x00000001 +#define LEDC_TIMER3_OVF_INT_ST_S 3 + +/* LEDC_DUTY_CHNG_END_CH0_INT_ST : RO; bitpos: [4]; default: 0; + * This is the masked interrupt status bit for the + * LEDC_DUTY_CHNG_END_CH0_INT interrupt when + * LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1. + */ + +#define LEDC_DUTY_CHNG_END_CH0_INT_ST (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_M (LEDC_DUTY_CHNG_END_CH0_INT_ST_V << LEDC_DUTY_CHNG_END_CH0_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH0_INT_ST_S 4 + +/* LEDC_DUTY_CHNG_END_CH1_INT_ST : RO; bitpos: [5]; default: 0; + * This is the masked interrupt status bit for the + * LEDC_DUTY_CHNG_END_CH1_INT interrupt when + * LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1. + */ + +#define LEDC_DUTY_CHNG_END_CH1_INT_ST (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_M (LEDC_DUTY_CHNG_END_CH1_INT_ST_V << LEDC_DUTY_CHNG_END_CH1_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH1_INT_ST_S 5 + +/* LEDC_DUTY_CHNG_END_CH2_INT_ST : RO; bitpos: [6]; default: 0; + * This is the masked interrupt status bit for the + * LEDC_DUTY_CHNG_END_CH2_INT interrupt when + * LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1. + */ + +#define LEDC_DUTY_CHNG_END_CH2_INT_ST (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_M (LEDC_DUTY_CHNG_END_CH2_INT_ST_V << LEDC_DUTY_CHNG_END_CH2_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH2_INT_ST_S 6 + +/* LEDC_DUTY_CHNG_END_CH3_INT_ST : RO; bitpos: [7]; default: 0; + * This is the masked interrupt status bit for the + * LEDC_DUTY_CHNG_END_CH3_INT interrupt when + * LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1. + */ + +#define LEDC_DUTY_CHNG_END_CH3_INT_ST (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_M (LEDC_DUTY_CHNG_END_CH3_INT_ST_V << LEDC_DUTY_CHNG_END_CH3_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH3_INT_ST_S 7 + +/* LEDC_DUTY_CHNG_END_CH4_INT_ST : RO; bitpos: [8]; default: 0; + * This is the masked interrupt status bit for the + * LEDC_DUTY_CHNG_END_CH4_INT interrupt when + * LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1. + */ + +#define LEDC_DUTY_CHNG_END_CH4_INT_ST (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_M (LEDC_DUTY_CHNG_END_CH4_INT_ST_V << LEDC_DUTY_CHNG_END_CH4_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH4_INT_ST_S 8 + +/* LEDC_DUTY_CHNG_END_CH5_INT_ST : RO; bitpos: [9]; default: 0; + * This is the masked interrupt status bit for the + * LEDC_DUTY_CHNG_END_CH5_INT interrupt when + * LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1. + */ + +#define LEDC_DUTY_CHNG_END_CH5_INT_ST (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_M (LEDC_DUTY_CHNG_END_CH5_INT_ST_V << LEDC_DUTY_CHNG_END_CH5_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH5_INT_ST_S 9 + +/* LEDC_DUTY_CHNG_END_CH6_INT_ST : RO; bitpos: [10]; default: 0; + * This is the masked interrupt status bit for the + * LEDC_DUTY_CHNG_END_CH6_INT interrupt when + * LEDC_DUTY_CHNG_END_CH6_INT_ENAIS set to 1. + */ + +#define LEDC_DUTY_CHNG_END_CH6_INT_ST (BIT(10)) +#define LEDC_DUTY_CHNG_END_CH6_INT_ST_M (LEDC_DUTY_CHNG_END_CH6_INT_ST_V << LEDC_DUTY_CHNG_END_CH6_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH6_INT_ST_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH6_INT_ST_S 10 + +/* LEDC_DUTY_CHNG_END_CH7_INT_ST : RO; bitpos: [11]; default: 0; + * This is the masked interrupt status bit for the + * LEDC_DUTY_CHNG_END_CH7_INT interrupt when + * LEDC_DUTY_CHNG_END_CH7_INT_ENAIS set to 1. + */ + +#define LEDC_DUTY_CHNG_END_CH7_INT_ST (BIT(11)) +#define LEDC_DUTY_CHNG_END_CH7_INT_ST_M (LEDC_DUTY_CHNG_END_CH7_INT_ST_V << LEDC_DUTY_CHNG_END_CH7_INT_ST_S) +#define LEDC_DUTY_CHNG_END_CH7_INT_ST_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH7_INT_ST_S 11 + +/* LEDC_OVF_CNT_CH0_INT_ST : RO; bitpos: [12]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT + * interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. + */ + +#define LEDC_OVF_CNT_CH0_INT_ST (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_ST_M (LEDC_OVF_CNT_CH0_INT_ST_V << LEDC_OVF_CNT_CH0_INT_ST_S) +#define LEDC_OVF_CNT_CH0_INT_ST_V 0x00000001 +#define LEDC_OVF_CNT_CH0_INT_ST_S 12 + +/* LEDC_OVF_CNT_CH1_INT_ST : RO; bitpos: [13]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT + * interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. + */ + +#define LEDC_OVF_CNT_CH1_INT_ST (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_ST_M (LEDC_OVF_CNT_CH1_INT_ST_V << LEDC_OVF_CNT_CH1_INT_ST_S) +#define LEDC_OVF_CNT_CH1_INT_ST_V 0x00000001 +#define LEDC_OVF_CNT_CH1_INT_ST_S 13 + +/* LEDC_OVF_CNT_CH2_INT_ST : RO; bitpos: [14]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT + * interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. + */ + +#define LEDC_OVF_CNT_CH2_INT_ST (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_ST_M (LEDC_OVF_CNT_CH2_INT_ST_V << LEDC_OVF_CNT_CH2_INT_ST_S) +#define LEDC_OVF_CNT_CH2_INT_ST_V 0x00000001 +#define LEDC_OVF_CNT_CH2_INT_ST_S 14 + +/* LEDC_OVF_CNT_CH3_INT_ST : RO; bitpos: [15]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT + * interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. + */ + +#define LEDC_OVF_CNT_CH3_INT_ST (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_ST_M (LEDC_OVF_CNT_CH3_INT_ST_V << LEDC_OVF_CNT_CH3_INT_ST_S) +#define LEDC_OVF_CNT_CH3_INT_ST_V 0x00000001 +#define LEDC_OVF_CNT_CH3_INT_ST_S 15 + +/* LEDC_OVF_CNT_CH4_INT_ST : RO; bitpos: [16]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT + * interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. + */ + +#define LEDC_OVF_CNT_CH4_INT_ST (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_ST_M (LEDC_OVF_CNT_CH4_INT_ST_V << LEDC_OVF_CNT_CH4_INT_ST_S) +#define LEDC_OVF_CNT_CH4_INT_ST_V 0x00000001 +#define LEDC_OVF_CNT_CH4_INT_ST_S 16 + +/* LEDC_OVF_CNT_CH5_INT_ST : RO; bitpos: [17]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT + * interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. + */ + +#define LEDC_OVF_CNT_CH5_INT_ST (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_ST_M (LEDC_OVF_CNT_CH5_INT_ST_V << LEDC_OVF_CNT_CH5_INT_ST_S) +#define LEDC_OVF_CNT_CH5_INT_ST_V 0x00000001 +#define LEDC_OVF_CNT_CH5_INT_ST_S 17 + +/* LEDC_OVF_CNT_CH6_INT_ST : RO; bitpos: [18]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH6_INT + * interrupt when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. + */ + +#define LEDC_OVF_CNT_CH6_INT_ST (BIT(18)) +#define LEDC_OVF_CNT_CH6_INT_ST_M (LEDC_OVF_CNT_CH6_INT_ST_V << LEDC_OVF_CNT_CH6_INT_ST_S) +#define LEDC_OVF_CNT_CH6_INT_ST_V 0x00000001 +#define LEDC_OVF_CNT_CH6_INT_ST_S 18 + +/* LEDC_OVF_CNT_CH7_INT_ST : RO; bitpos: [19]; default: 0; + * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH7_INT + * interrupt when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. + */ + +#define LEDC_OVF_CNT_CH7_INT_ST (BIT(19)) +#define LEDC_OVF_CNT_CH7_INT_ST_M (LEDC_OVF_CNT_CH7_INT_ST_V << LEDC_OVF_CNT_CH7_INT_ST_S) +#define LEDC_OVF_CNT_CH7_INT_ST_V 0x00000001 +#define LEDC_OVF_CNT_CH7_INT_ST_S 19 + +/* LEDC_INT_ENA_REG register + * Interrupt enable bits + */ + +#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xc8) + +/* LEDC_TIMER0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. + */ + +#define LEDC_TIMER0_OVF_INT_ENA (BIT(0)) +#define LEDC_TIMER0_OVF_INT_ENA_M (LEDC_TIMER0_OVF_INT_ENA_V << LEDC_TIMER0_OVF_INT_ENA_S) +#define LEDC_TIMER0_OVF_INT_ENA_V 0x00000001 +#define LEDC_TIMER0_OVF_INT_ENA_S 0 + +/* LEDC_TIMER1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. + */ + +#define LEDC_TIMER1_OVF_INT_ENA (BIT(1)) +#define LEDC_TIMER1_OVF_INT_ENA_M (LEDC_TIMER1_OVF_INT_ENA_V << LEDC_TIMER1_OVF_INT_ENA_S) +#define LEDC_TIMER1_OVF_INT_ENA_V 0x00000001 +#define LEDC_TIMER1_OVF_INT_ENA_S 1 + +/* LEDC_TIMER2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. + */ + +#define LEDC_TIMER2_OVF_INT_ENA (BIT(2)) +#define LEDC_TIMER2_OVF_INT_ENA_M (LEDC_TIMER2_OVF_INT_ENA_V << LEDC_TIMER2_OVF_INT_ENA_S) +#define LEDC_TIMER2_OVF_INT_ENA_V 0x00000001 +#define LEDC_TIMER2_OVF_INT_ENA_S 2 + +/* LEDC_TIMER3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. + */ + +#define LEDC_TIMER3_OVF_INT_ENA (BIT(3)) +#define LEDC_TIMER3_OVF_INT_ENA_M (LEDC_TIMER3_OVF_INT_ENA_V << LEDC_TIMER3_OVF_INT_ENA_S) +#define LEDC_TIMER3_OVF_INT_ENA_V 0x00000001 +#define LEDC_TIMER3_OVF_INT_ENA_S 3 + +/* LEDC_DUTY_CHNG_END_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_M (LEDC_DUTY_CHNG_END_CH0_INT_ENA_V << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_S 4 + +/* LEDC_DUTY_CHNG_END_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_M (LEDC_DUTY_CHNG_END_CH1_INT_ENA_V << LEDC_DUTY_CHNG_END_CH1_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_S 5 + +/* LEDC_DUTY_CHNG_END_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_M (LEDC_DUTY_CHNG_END_CH2_INT_ENA_V << LEDC_DUTY_CHNG_END_CH2_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_S 6 + +/* LEDC_DUTY_CHNG_END_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_M (LEDC_DUTY_CHNG_END_CH3_INT_ENA_V << LEDC_DUTY_CHNG_END_CH3_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_S 7 + +/* LEDC_DUTY_CHNG_END_CH4_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_M (LEDC_DUTY_CHNG_END_CH4_INT_ENA_V << LEDC_DUTY_CHNG_END_CH4_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_S 8 + +/* LEDC_DUTY_CHNG_END_CH5_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_M (LEDC_DUTY_CHNG_END_CH5_INT_ENA_V << LEDC_DUTY_CHNG_END_CH5_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_S 9 + +/* LEDC_DUTY_CHNG_END_CH6_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH6_INT_ENA (BIT(10)) +#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_M (LEDC_DUTY_CHNG_END_CH6_INT_ENA_V << LEDC_DUTY_CHNG_END_CH6_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_S 10 + +/* LEDC_DUTY_CHNG_END_CH7_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH7_INT_ENA (BIT(11)) +#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_M (LEDC_DUTY_CHNG_END_CH7_INT_ENA_V << LEDC_DUTY_CHNG_END_CH7_INT_ENA_S) +#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_S 11 + +/* LEDC_OVF_CNT_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH0_INT_ENA (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_ENA_M (LEDC_OVF_CNT_CH0_INT_ENA_V << LEDC_OVF_CNT_CH0_INT_ENA_S) +#define LEDC_OVF_CNT_CH0_INT_ENA_V 0x00000001 +#define LEDC_OVF_CNT_CH0_INT_ENA_S 12 + +/* LEDC_OVF_CNT_CH1_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH1_INT_ENA (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_ENA_M (LEDC_OVF_CNT_CH1_INT_ENA_V << LEDC_OVF_CNT_CH1_INT_ENA_S) +#define LEDC_OVF_CNT_CH1_INT_ENA_V 0x00000001 +#define LEDC_OVF_CNT_CH1_INT_ENA_S 13 + +/* LEDC_OVF_CNT_CH2_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH2_INT_ENA (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_ENA_M (LEDC_OVF_CNT_CH2_INT_ENA_V << LEDC_OVF_CNT_CH2_INT_ENA_S) +#define LEDC_OVF_CNT_CH2_INT_ENA_V 0x00000001 +#define LEDC_OVF_CNT_CH2_INT_ENA_S 14 + +/* LEDC_OVF_CNT_CH3_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH3_INT_ENA (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_ENA_M (LEDC_OVF_CNT_CH3_INT_ENA_V << LEDC_OVF_CNT_CH3_INT_ENA_S) +#define LEDC_OVF_CNT_CH3_INT_ENA_V 0x00000001 +#define LEDC_OVF_CNT_CH3_INT_ENA_S 15 + +/* LEDC_OVF_CNT_CH4_INT_ENA : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH4_INT_ENA (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_ENA_M (LEDC_OVF_CNT_CH4_INT_ENA_V << LEDC_OVF_CNT_CH4_INT_ENA_S) +#define LEDC_OVF_CNT_CH4_INT_ENA_V 0x00000001 +#define LEDC_OVF_CNT_CH4_INT_ENA_S 16 + +/* LEDC_OVF_CNT_CH5_INT_ENA : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH5_INT_ENA (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_ENA_M (LEDC_OVF_CNT_CH5_INT_ENA_V << LEDC_OVF_CNT_CH5_INT_ENA_S) +#define LEDC_OVF_CNT_CH5_INT_ENA_V 0x00000001 +#define LEDC_OVF_CNT_CH5_INT_ENA_S 17 + +/* LEDC_OVF_CNT_CH6_INT_ENA : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH6_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH6_INT_ENA (BIT(18)) +#define LEDC_OVF_CNT_CH6_INT_ENA_M (LEDC_OVF_CNT_CH6_INT_ENA_V << LEDC_OVF_CNT_CH6_INT_ENA_S) +#define LEDC_OVF_CNT_CH6_INT_ENA_V 0x00000001 +#define LEDC_OVF_CNT_CH6_INT_ENA_S 18 + +/* LEDC_OVF_CNT_CH7_INT_ENA : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for the LEDC_OVF_CNT_CH7_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH7_INT_ENA (BIT(19)) +#define LEDC_OVF_CNT_CH7_INT_ENA_M (LEDC_OVF_CNT_CH7_INT_ENA_V << LEDC_OVF_CNT_CH7_INT_ENA_S) +#define LEDC_OVF_CNT_CH7_INT_ENA_V 0x00000001 +#define LEDC_OVF_CNT_CH7_INT_ENA_S 19 + +/* LEDC_INT_CLR_REG register + * Interrupt clear bits + */ + +#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xcc) + +/* LEDC_TIMER0_OVF_INT_CLR : WO; bitpos: [0]; default: 0; + * Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. + */ + +#define LEDC_TIMER0_OVF_INT_CLR (BIT(0)) +#define LEDC_TIMER0_OVF_INT_CLR_M (LEDC_TIMER0_OVF_INT_CLR_V << LEDC_TIMER0_OVF_INT_CLR_S) +#define LEDC_TIMER0_OVF_INT_CLR_V 0x00000001 +#define LEDC_TIMER0_OVF_INT_CLR_S 0 + +/* LEDC_TIMER1_OVF_INT_CLR : WO; bitpos: [1]; default: 0; + * Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. + */ + +#define LEDC_TIMER1_OVF_INT_CLR (BIT(1)) +#define LEDC_TIMER1_OVF_INT_CLR_M (LEDC_TIMER1_OVF_INT_CLR_V << LEDC_TIMER1_OVF_INT_CLR_S) +#define LEDC_TIMER1_OVF_INT_CLR_V 0x00000001 +#define LEDC_TIMER1_OVF_INT_CLR_S 1 + +/* LEDC_TIMER2_OVF_INT_CLR : WO; bitpos: [2]; default: 0; + * Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. + */ + +#define LEDC_TIMER2_OVF_INT_CLR (BIT(2)) +#define LEDC_TIMER2_OVF_INT_CLR_M (LEDC_TIMER2_OVF_INT_CLR_V << LEDC_TIMER2_OVF_INT_CLR_S) +#define LEDC_TIMER2_OVF_INT_CLR_V 0x00000001 +#define LEDC_TIMER2_OVF_INT_CLR_S 2 + +/* LEDC_TIMER3_OVF_INT_CLR : WO; bitpos: [3]; default: 0; + * Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. + */ + +#define LEDC_TIMER3_OVF_INT_CLR (BIT(3)) +#define LEDC_TIMER3_OVF_INT_CLR_M (LEDC_TIMER3_OVF_INT_CLR_V << LEDC_TIMER3_OVF_INT_CLR_S) +#define LEDC_TIMER3_OVF_INT_CLR_V 0x00000001 +#define LEDC_TIMER3_OVF_INT_CLR_S 3 + +/* LEDC_DUTY_CHNG_END_CH0_INT_CLR : WO; bitpos: [4]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR (BIT(4)) +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_M (LEDC_DUTY_CHNG_END_CH0_INT_CLR_V << LEDC_DUTY_CHNG_END_CH0_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_S 4 + +/* LEDC_DUTY_CHNG_END_CH1_INT_CLR : WO; bitpos: [5]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR (BIT(5)) +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_M (LEDC_DUTY_CHNG_END_CH1_INT_CLR_V << LEDC_DUTY_CHNG_END_CH1_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_S 5 + +/* LEDC_DUTY_CHNG_END_CH2_INT_CLR : WO; bitpos: [6]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR (BIT(6)) +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_M (LEDC_DUTY_CHNG_END_CH2_INT_CLR_V << LEDC_DUTY_CHNG_END_CH2_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_S 6 + +/* LEDC_DUTY_CHNG_END_CH3_INT_CLR : WO; bitpos: [7]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR (BIT(7)) +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_M (LEDC_DUTY_CHNG_END_CH3_INT_CLR_V << LEDC_DUTY_CHNG_END_CH3_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_S 7 + +/* LEDC_DUTY_CHNG_END_CH4_INT_CLR : WO; bitpos: [8]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR (BIT(8)) +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_M (LEDC_DUTY_CHNG_END_CH4_INT_CLR_V << LEDC_DUTY_CHNG_END_CH4_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_S 8 + +/* LEDC_DUTY_CHNG_END_CH5_INT_CLR : WO; bitpos: [9]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR (BIT(9)) +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_M (LEDC_DUTY_CHNG_END_CH5_INT_CLR_V << LEDC_DUTY_CHNG_END_CH5_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_S 9 + +/* LEDC_DUTY_CHNG_END_CH6_INT_CLR : WO; bitpos: [10]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH6_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH6_INT_CLR (BIT(10)) +#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_M (LEDC_DUTY_CHNG_END_CH6_INT_CLR_V << LEDC_DUTY_CHNG_END_CH6_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_S 10 + +/* LEDC_DUTY_CHNG_END_CH7_INT_CLR : WO; bitpos: [11]; default: 0; + * Set this bit to clear the LEDC_DUTY_CHNG_END_CH7_INT interrupt. + */ + +#define LEDC_DUTY_CHNG_END_CH7_INT_CLR (BIT(11)) +#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_M (LEDC_DUTY_CHNG_END_CH7_INT_CLR_V << LEDC_DUTY_CHNG_END_CH7_INT_CLR_S) +#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_V 0x00000001 +#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_S 11 + +/* LEDC_OVF_CNT_CH0_INT_CLR : WO; bitpos: [12]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH0_INT_CLR (BIT(12)) +#define LEDC_OVF_CNT_CH0_INT_CLR_M (LEDC_OVF_CNT_CH0_INT_CLR_V << LEDC_OVF_CNT_CH0_INT_CLR_S) +#define LEDC_OVF_CNT_CH0_INT_CLR_V 0x00000001 +#define LEDC_OVF_CNT_CH0_INT_CLR_S 12 + +/* LEDC_OVF_CNT_CH1_INT_CLR : WO; bitpos: [13]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH1_INT_CLR (BIT(13)) +#define LEDC_OVF_CNT_CH1_INT_CLR_M (LEDC_OVF_CNT_CH1_INT_CLR_V << LEDC_OVF_CNT_CH1_INT_CLR_S) +#define LEDC_OVF_CNT_CH1_INT_CLR_V 0x00000001 +#define LEDC_OVF_CNT_CH1_INT_CLR_S 13 + +/* LEDC_OVF_CNT_CH2_INT_CLR : WO; bitpos: [14]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH2_INT_CLR (BIT(14)) +#define LEDC_OVF_CNT_CH2_INT_CLR_M (LEDC_OVF_CNT_CH2_INT_CLR_V << LEDC_OVF_CNT_CH2_INT_CLR_S) +#define LEDC_OVF_CNT_CH2_INT_CLR_V 0x00000001 +#define LEDC_OVF_CNT_CH2_INT_CLR_S 14 + +/* LEDC_OVF_CNT_CH3_INT_CLR : WO; bitpos: [15]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH3_INT_CLR (BIT(15)) +#define LEDC_OVF_CNT_CH3_INT_CLR_M (LEDC_OVF_CNT_CH3_INT_CLR_V << LEDC_OVF_CNT_CH3_INT_CLR_S) +#define LEDC_OVF_CNT_CH3_INT_CLR_V 0x00000001 +#define LEDC_OVF_CNT_CH3_INT_CLR_S 15 + +/* LEDC_OVF_CNT_CH4_INT_CLR : WO; bitpos: [16]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH4_INT_CLR (BIT(16)) +#define LEDC_OVF_CNT_CH4_INT_CLR_M (LEDC_OVF_CNT_CH4_INT_CLR_V << LEDC_OVF_CNT_CH4_INT_CLR_S) +#define LEDC_OVF_CNT_CH4_INT_CLR_V 0x00000001 +#define LEDC_OVF_CNT_CH4_INT_CLR_S 16 + +/* LEDC_OVF_CNT_CH5_INT_CLR : WO; bitpos: [17]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH5_INT_CLR (BIT(17)) +#define LEDC_OVF_CNT_CH5_INT_CLR_M (LEDC_OVF_CNT_CH5_INT_CLR_V << LEDC_OVF_CNT_CH5_INT_CLR_S) +#define LEDC_OVF_CNT_CH5_INT_CLR_V 0x00000001 +#define LEDC_OVF_CNT_CH5_INT_CLR_S 17 + +/* LEDC_OVF_CNT_CH6_INT_CLR : WO; bitpos: [18]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH6_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH6_INT_CLR (BIT(18)) +#define LEDC_OVF_CNT_CH6_INT_CLR_M (LEDC_OVF_CNT_CH6_INT_CLR_V << LEDC_OVF_CNT_CH6_INT_CLR_S) +#define LEDC_OVF_CNT_CH6_INT_CLR_V 0x00000001 +#define LEDC_OVF_CNT_CH6_INT_CLR_S 18 + +/* LEDC_OVF_CNT_CH7_INT_CLR : WO; bitpos: [19]; default: 0; + * Set this bit to clear the LEDC_OVF_CNT_CH7_INT interrupt. + */ + +#define LEDC_OVF_CNT_CH7_INT_CLR (BIT(19)) +#define LEDC_OVF_CNT_CH7_INT_CLR_M (LEDC_OVF_CNT_CH7_INT_CLR_V << LEDC_OVF_CNT_CH7_INT_CLR_S) +#define LEDC_OVF_CNT_CH7_INT_CLR_V 0x00000001 +#define LEDC_OVF_CNT_CH7_INT_CLR_S 19 + +/* LEDC_CONF_REG register + * Global ledc configuration register + */ + +#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0xd0) + +/* LEDC_APB_CLK_SEL : R/W; bitpos: [1:0]; default: 0; + * This bit is used to select clock source for the 4 timers . + * + * 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK + */ + +#define LEDC_APB_CLK_SEL 0x00000003 +#define LEDC_APB_CLK_SEL_M (LEDC_APB_CLK_SEL_V << LEDC_APB_CLK_SEL_S) +#define LEDC_APB_CLK_SEL_V 0x00000003 +#define LEDC_APB_CLK_SEL_S 0 + +/* LEDC_CLK_EN : R/W; bitpos: [31]; default: 0; + * This bit is used to control clock. + * + * 1'b1: Force clock on for register. 1'h0: Support clock only when + * application writes registers. + */ + +#define LEDC_CLK_EN (BIT(31)) +#define LEDC_CLK_EN_M (LEDC_CLK_EN_V << LEDC_CLK_EN_S) +#define LEDC_CLK_EN_V 0x00000001 +#define LEDC_CLK_EN_S 31 + +/* LEDC_DATE_REG register + * Version control register + */ + +#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0xfc) + +/* LEDC_DATE : R/W; bitpos: [31:0]; default: 419898881; + * This is the version control register. + */ + +#define LEDC_DATE 0xFFFFFFFF +#define LEDC_DATE_M (LEDC_DATE_V << LEDC_DATE_S) +#define LEDC_DATE_V 0xFFFFFFFF +#define LEDC_DATE_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_LEDC_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_memorymap.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_memorymap.h new file mode 100644 index 0000000000000..a8bc4e34297fb --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_memorymap.h @@ -0,0 +1,72 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_MEMORYMAP_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_MEMORYMAP_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ESP32C3_SYSTEM_BASE 0x600c0000 +#define ESP32C3_SENSITIVE_BASE 0x600c1000 +#define ESP32C3_INTERRUPT_BASE 0x600c2000 +#define ESP32C3_DMA_COPY_BASE 0x600c3000 +#define ESP32C3_EXTMEM_BASE 0x600c4000 +#define ESP32C3_MMU_TABLE 0x600c5000 +#define ESP32C3_AES_BASE 0x6003a000 +#define ESP32C3_SHA_BASE 0x6003b000 +#define ESP32C3_RSA_BASE 0x6003c000 +#define ESP32C3_HMAC_BASE 0x6003e000 +#define ESP32C3_DIGITAL_SIGNATURE_BASE 0x6003d000 +#define ESP32C3_GDMA_BASE 0x6003f000 +#define ESP32C3_ASSIST_DEBUG_BASE 0x600ce000 +#define ESP32C3_DEDICATED_GPIO_BASE 0x600cf000 +#define ESP32C3_WORLD_CNTL_BASE 0x600d0000 +#define ESP32C3_DPORT_END 0x600d3ffc +#define ESP32C3_UART_BASE 0x60000000 +#define ESP32C3_SPI1_BASE 0x60002000 +#define ESP32C3_SPI0_BASE 0x60003000 +#define ESP32C3_GPIO_BASE 0x60004000 +#define ESP32C3_FE2_BASE 0x60005000 +#define ESP32C3_FE_BASE 0x60006000 +#define ESP32C3_RTCCNTL_BASE 0x60008000 +#define ESP32C3_IO_MUX_BASE 0x60009000 +#define ESP32C3_RTC_I2C_BASE 0x6000e000 +#define ESP32C3_UART1_BASE 0x60010000 +#define ESP32C3_I2C_EXT_BASE 0x60013000 +#define ESP32C3_UHCI0_BASE 0x60014000 +#define ESP32C3_RMT_BASE 0x60016000 +#define ESP32C3_LEDC_BASE 0x60019000 +#define ESP32C3_EFUSE_BASE 0x60008800 +#define ESP32C3_NRX_BASE 0x6001cc00 +#define ESP32C3_BB_BASE 0x6001d000 +#define ESP32C3_TIMERGROUP0_BASE 0x6001f000 +#define ESP32C3_TIMERGROUP1_BASE 0x60020000 +#define ESP32C3_SYS_TIMER_BASE 0x60023000 +#define ESP32C3_SPI2_BASE 0x60024000 +#define ESP32C3_SYSCON_BASE 0x60026000 +#define ESP32C3_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON */ +#define ESP32C3_TWAI_BASE 0x6002b000 +#define ESP32C3_I2S0_BASE 0x6002d000 +#define ESP32C3_APB_SARADC_BASE 0x60040000 +#define ESP32C3_AES_XTS_BASE 0x600cc000 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_MEMORYMAP_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_pinmap.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_pinmap.h similarity index 86% rename from arch/risc-v/src/esp32c3/hardware/esp32c3_pinmap.h rename to arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_pinmap.h index 54465ecdc5880..febe9eccd0a65 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_pinmap.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_pinmap.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_pinmap.h + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_pinmap.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -22,8 +22,8 @@ * Included Files ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_PINMAP_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_PINMAP_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_PINMAP_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_PINMAP_H /**************************************************************************** * Pre-processor Definitions @@ -42,4 +42,4 @@ #define SPI2_IOMUX_WPPIN (5) #define SPI2_IOMUX_HDPIN (4) -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_PINMAP_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_PINMAP_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_rom_layout.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_rom_layout.h similarity index 91% rename from arch/risc-v/src/esp32c3/hardware/esp32c3_rom_layout.h rename to arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_rom_layout.h index f7a7e6b57542a..560b22d03d2aa 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_rom_layout.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_rom_layout.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_rom_layout.h + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_rom_layout.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_ROM_LAYOUT_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_ROM_LAYOUT_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_ROM_LAYOUT_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_ROM_LAYOUT_H /**************************************************************************** * Included Files @@ -90,5 +90,5 @@ struct esp32c3_rom_layout_s uintptr_t dram_end_uart_rom; }; -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_ROM_LAYOUT_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_ROM_LAYOUT_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_rsa.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_rsa.h new file mode 100644 index 0000000000000..162f58638751c --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_rsa.h @@ -0,0 +1,308 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_rsa.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_RSA_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_RSA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RSA_MEM_M_BLOCK_REG register + * Memory M + */ + +#define RSA_MEM_M_BLOCK_REG (DR_REG_RSA_BASE + 0x0) + +/* RSA_M_MEMORY : R/W; bitpos: [16:0]; default: 384; + * Memory M + */ + +#define RSA_M_MEMORY 0x0001FFFF +#define RSA_M_MEMORY_M (RSA_M_MEMORY_V << RSA_M_MEMORY_S) +#define RSA_M_MEMORY_V 0x0001FFFF +#define RSA_M_MEMORY_S 0 + +/* RSA_MEM_RB_BLOCK_REG register + * Memory RB + */ + +#define RSA_MEM_RB_BLOCK_REG (DR_REG_RSA_BASE + 0x200) + +/* RSA_RB_MEMORY : R/W; bitpos: [16:0]; default: 384; + * Memory RB + */ + +#define RSA_RB_MEMORY 0x0001FFFF +#define RSA_RB_MEMORY_M (RSA_RB_MEMORY_V << RSA_RB_MEMORY_S) +#define RSA_RB_MEMORY_V 0x0001FFFF +#define RSA_RB_MEMORY_S 0 + +/* RSA_MEM_Z_BLOCK_REG register + * Memory Z + */ + +#define RSA_MEM_Z_BLOCK_REG (DR_REG_RSA_BASE + 0x200) + +/* RSA_Z_MEMORY : R/W; bitpos: [16:0]; default: 384; + * Memory Z + */ + +#define RSA_Z_MEMORY 0x0001FFFF +#define RSA_Z_MEMORY_M (RSA_Z_MEMORY_V << RSA_Z_MEMORY_S) +#define RSA_Z_MEMORY_V 0x0001FFFF +#define RSA_Z_MEMORY_S 0 + +/* RSA_MEM_Y_BLOCK_REG register + * Memory Y + */ + +#define RSA_MEM_Y_BLOCK_REG (DR_REG_RSA_BASE + 0x400) + +/* RSA_Y_MEMORY : R/W; bitpos: [16:0]; default: 384; + * Memory Y + */ + +#define RSA_Y_MEMORY 0x0001FFFF +#define RSA_Y_MEMORY_M (RSA_Y_MEMORY_V << RSA_Y_MEMORY_S) +#define RSA_Y_MEMORY_V 0x0001FFFF +#define RSA_Y_MEMORY_S 0 + +/* RSA_MEM_X_BLOCK_REG register + * Memory X + */ + +#define RSA_MEM_X_BLOCK_REG (DR_REG_RSA_BASE + 0x600) + +/* RSA_X_MEMORY : R/W; bitpos: [16:0]; default: 384; + * Memory X + */ + +#define RSA_X_MEMORY 0x0001FFFF +#define RSA_X_MEMORY_M (RSA_X_MEMORY_V << RSA_X_MEMORY_S) +#define RSA_X_MEMORY_V 0x0001FFFF +#define RSA_X_MEMORY_S 0 + +/* RSA_M_PRIME_REG register + * Register to store M' + */ + +#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800) + +/* RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0; + * Stores M' + */ + +#define RSA_M_PRIME 0xFFFFFFFF +#define RSA_M_PRIME_M (RSA_M_PRIME_V << RSA_M_PRIME_S) +#define RSA_M_PRIME_V 0xFFFFFFFF +#define RSA_M_PRIME_S 0 + +/* RSA_MODE_REG register + * RSA length mode + */ + +#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804) + +/* RSA_MODE : R/W; bitpos: [6:0]; default: 0; + * Stores the mode of modular exponentiation. + */ + +#define RSA_MODE 0x0000007F +#define RSA_MODE_M (RSA_MODE_V << RSA_MODE_S) +#define RSA_MODE_V 0x0000007F +#define RSA_MODE_S 0 + +/* RSA_CLEAN_REG register + * RSA clean register + */ + +#define RSA_CLEAN_REG (DR_REG_RSA_BASE + 0x808) + +/* RSA_CLEAN : RO; bitpos: [0]; default: 0; + * The content of this bit is 1 when memories complete initialization. + */ + +#define RSA_CLEAN (BIT(0)) +#define RSA_CLEAN_M (RSA_CLEAN_V << RSA_CLEAN_S) +#define RSA_CLEAN_V 0x00000001 +#define RSA_CLEAN_S 0 + +/* RSA_MODEXP_START_REG register + * Modular exponentiation starting bit + */ + +#define RSA_MODEXP_START_REG (DR_REG_RSA_BASE + 0x80c) + +/* RSA_MODEXP_START : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to start the modular exponentiation. + */ + +#define RSA_MODEXP_START (BIT(0)) +#define RSA_MODEXP_START_M (RSA_MODEXP_START_V << RSA_MODEXP_START_S) +#define RSA_MODEXP_START_V 0x00000001 +#define RSA_MODEXP_START_S 0 + +/* RSA_MODMULT_START_REG register + * Modular multiplication starting bit + */ + +#define RSA_MODMULT_START_REG (DR_REG_RSA_BASE + 0x810) + +/* RSA_MODMULT_START : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to start the modular multiplication. + */ + +#define RSA_MODMULT_START (BIT(0)) +#define RSA_MODMULT_START_M (RSA_MODMULT_START_V << RSA_MODMULT_START_S) +#define RSA_MODMULT_START_V 0x00000001 +#define RSA_MODMULT_START_S 0 + +/* RSA_MULT_START_REG register + * Normal multiplicaiton starting bit + */ + +#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x814) + +/* RSA_MULT_START : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to start the multiplication. + */ + +#define RSA_MULT_START (BIT(0)) +#define RSA_MULT_START_M (RSA_MULT_START_V << RSA_MULT_START_S) +#define RSA_MULT_START_V 0x00000001 +#define RSA_MULT_START_S 0 + +/* RSA_IDLE_REG register + * RSA idle register + */ + +#define RSA_IDLE_REG (DR_REG_RSA_BASE + 0x818) + +/* RSA_IDLE : RO; bitpos: [0]; default: 0; + * The content of this bit is 1 when the RSA accelerator is idle. + */ + +#define RSA_IDLE (BIT(0)) +#define RSA_IDLE_M (RSA_IDLE_V << RSA_IDLE_S) +#define RSA_IDLE_V 0x00000001 +#define RSA_IDLE_S 0 + +/* RSA_CLEAR_INTERRUPT_REG register + * RSA clear interrupt register + */ + +#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81c) + +/* RSA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to clear the RSA interrupts. + */ + +#define RSA_CLEAR_INTERRUPT (BIT(0)) +#define RSA_CLEAR_INTERRUPT_M (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S) +#define RSA_CLEAR_INTERRUPT_V 0x00000001 +#define RSA_CLEAR_INTERRUPT_S 0 + +/* RSA_CONSTANT_TIME_REG register + * The constant_time option + */ + +#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820) + +/* RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1; + * Set this bit to 0 to enable the acceleration option of constant_time for + * modular exponentiation. Set to 1 to disable the acceleration (by default). + */ + +#define RSA_CONSTANT_TIME (BIT(0)) +#define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S) +#define RSA_CONSTANT_TIME_V 0x00000001 +#define RSA_CONSTANT_TIME_S 0 + +/* RSA_SEARCH_ENABLE_REG register + * The search option + */ + +#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824) + +/* RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 to enable the acceleration option of search for modular + * exponentiation. Set to 0 to disable the acceleration (by default). + */ + +#define RSA_SEARCH_ENABLE (BIT(0)) +#define RSA_SEARCH_ENABLE_M (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S) +#define RSA_SEARCH_ENABLE_V 0x00000001 +#define RSA_SEARCH_ENABLE_S 0 + +/* RSA_SEARCH_POS_REG register + * The search position + */ + +#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828) + +/* RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0; + * Is used to configure the starting address when the acceleration option of + * search is used. + */ + +#define RSA_SEARCH_POS 0x00000FFF +#define RSA_SEARCH_POS_M (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S) +#define RSA_SEARCH_POS_V 0x00000FFF +#define RSA_SEARCH_POS_S 0 + +/* RSA_INTERRUPT_ENA_REG register + * RSA interrupt enable register + */ + +#define RSA_INTERRUPT_ENA_REG (DR_REG_RSA_BASE + 0x82c) + +/* RSA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 to enable the RSA interrupt. This option is enabled by + * default. + */ + +#define RSA_INTERRUPT_ENA (BIT(0)) +#define RSA_INTERRUPT_ENA_M (RSA_INTERRUPT_ENA_V << RSA_INTERRUPT_ENA_S) +#define RSA_INTERRUPT_ENA_V 0x00000001 +#define RSA_INTERRUPT_ENA_S 0 + +/* RSA_DATE_REG register + * Version control register + */ + +#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830) + +/* RSA_DATE : R/W; bitpos: [29:0]; default: 538510373; + * Version control register + */ + +#define RSA_DATE 0x3FFFFFFF +#define RSA_DATE_M (RSA_DATE_V << RSA_DATE_S) +#define RSA_DATE_V 0x3FFFFFFF +#define RSA_DATE_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_RSA_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_rtccntl.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_rtccntl.h similarity index 99% rename from arch/risc-v/src/esp32c3/hardware/esp32c3_rtccntl.h rename to arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_rtccntl.h index f43aaa794bbd3..0905977844aba 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_rtccntl.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_rtccntl.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_rtccntl.h + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_rtccntl.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_RTCCNTL_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_RTCCNTL_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_RTCCNTL_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_RTCCNTL_H /**************************************************************************** * Included Files @@ -3624,4 +3624,4 @@ #define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG #define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_RTCCNTL_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_RTCCNTL_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_saradc.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_saradc.h similarity index 99% rename from arch/risc-v/src/esp32c3/hardware/esp32c3_saradc.h rename to arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_saradc.h index 3d6a281e1c3e0..edd6da0bc7faf 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_saradc.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_saradc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_saradc.h + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_saradc.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SARADC_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SARADC_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SARADC_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SARADC_H /**************************************************************************** * Included Files @@ -909,4 +909,4 @@ #define APB_SARADC_DATE_V 0xFFFFFFFF #define APB_SARADC_DATE_S 0 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SARADC_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SARADC_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_sha.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_sha.h new file mode 100644 index 0000000000000..d4d1383475cb8 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_sha.h @@ -0,0 +1,938 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_sha.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SHA_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SHA_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SHA_MODE_REG register + * Defines the algorithm of SHA accelerator + */ + +#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0) + +/* SHA_MODE : R/W; bitpos: [2:0]; default: 0; + * Defines the SHA algorithm. + */ + +#define SHA_MODE 0x00000007 +#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S) +#define SHA_MODE_V 0x00000007 +#define SHA_MODE_S 0 + +/* SHA_T_STRING_REG register + * String content register for calculating initial Hash Value (only + * effective for SHA-512/t) + */ + +#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4) + +/* SHA_T_STRING : R/W; bitpos: [31:0]; default: 0; + * Defines t_string for calculating the initial Hash value for SHA-512/t. + */ + +#define SHA_T_STRING 0xFFFFFFFF +#define SHA_T_STRING_M (SHA_T_STRING_V << SHA_T_STRING_S) +#define SHA_T_STRING_V 0xFFFFFFFF +#define SHA_T_STRING_S 0 + +/* SHA_T_LENGTH_REG register + * String length register for calculating initial Hash Value (only effective + * for SHA-512/t) + */ + +#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8) + +/* SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0; + * Defines t_string for calculating the initial Hash value for SHA-512/t. + */ + +#define SHA_T_LENGTH 0x0000003F +#define SHA_T_LENGTH_M (SHA_T_LENGTH_V << SHA_T_LENGTH_S) +#define SHA_T_LENGTH_V 0x0000003F +#define SHA_T_LENGTH_S 0 + +/* SHA_DMA_BLOCK_NUM_REG register + * Block number register (only effective for DMA-SHA) + */ + +#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc) + +/* SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0; + * Defines the DMA-SHA block number. + */ + +#define SHA_DMA_BLOCK_NUM 0x0000003F +#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S) +#define SHA_DMA_BLOCK_NUM_V 0x0000003F +#define SHA_DMA_BLOCK_NUM_S 0 + +/* SHA_START_REG register + * Starts the SHA accelerator for Typical SHA operation + */ + +#define SHA_START_REG (DR_REG_SHA_BASE + 0x10) + +/* SHA_START : WO; bitpos: [0]; default: 0; + * Write 1 to start Typical SHA calculation. + */ + +#define SHA_START (BIT(0)) +#define SHA_START_M (SHA_START_V << SHA_START_S) +#define SHA_START_V 0x00000001 +#define SHA_START_S 0 + +/* SHA_CONTINUE_REG register + * Continues SHA operation (only effective in Typical SHA mode) + */ + +#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14) + +/* SHA_CONTINUE : WO; bitpos: [0]; default: 0; + * Write 1 to continue Typical SHA calculation. + */ + +#define SHA_CONTINUE (BIT(0)) +#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S) +#define SHA_CONTINUE_V 0x00000001 +#define SHA_CONTINUE_S 0 + +/* SHA_BUSY_REG register + * Indicates if SHA Accelerator is busy or not + */ + +#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18) + +/* SHA_BUSY_STATE : RO; bitpos: [0]; default: 0; + * Indicates the states of SHA accelerator. + * #1'h0: idle + * #1'h1: busy + */ + +#define SHA_BUSY_STATE (BIT(0)) +#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S) +#define SHA_BUSY_STATE_V 0x00000001 +#define SHA_BUSY_STATE_S 0 + +/* SHA_DMA_START_REG register + * Starts the SHA accelerator for DMA-SHA operation + */ + +#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c) + +/* SHA_DMA_START : WO; bitpos: [0]; default: 0; + * Write 1 to start DMA-SHA calculation. + */ + +#define SHA_DMA_START (BIT(0)) +#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S) +#define SHA_DMA_START_V 0x00000001 +#define SHA_DMA_START_S 0 + +/* SHA_DMA_CONTINUE_REG register + * Continues SHA operation (only effective in DMA-SHA mode) + */ + +#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20) + +/* SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0; + * Write 1 to continue DMA-SHA calculation. + */ + +#define SHA_DMA_CONTINUE (BIT(0)) +#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S) +#define SHA_DMA_CONTINUE_V 0x00000001 +#define SHA_DMA_CONTINUE_S 0 + +/* SHA_INT_CLEAR_REG register + * DMA-SHA interrupt clear register + */ + +#define SHA_INT_CLEAR_REG (DR_REG_SHA_BASE + 0x24) + +/* SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0; + * Clears DMA-SHA interrupt. + */ + +#define SHA_CLEAR_INTERRUPT (BIT(0)) +#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S) +#define SHA_CLEAR_INTERRUPT_V 0x00000001 +#define SHA_CLEAR_INTERRUPT_S 0 + +/* SHA_INT_ENA_REG register + * DMA-SHA interrupt enable register + */ + +#define SHA_INT_ENA_REG (DR_REG_SHA_BASE + 0x28) + +/* SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0; + * Enables DMA-SHA interrupt. + */ + +#define SHA_INTERRUPT_ENA (BIT(0)) +#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S) +#define SHA_INTERRUPT_ENA_V 0x00000001 +#define SHA_INTERRUPT_ENA_S 0 + +/* SHA_DATE_REG register + * Version control register. + */ + +#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c) + +/* SHA_DATE : R/W; bitpos: [29:0]; default: 538510338; + * Version control register + */ + +#define SHA_DATE 0x3FFFFFFF +#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S) +#define SHA_DATE_V 0x3FFFFFFF +#define SHA_DATE_S 0 + +/* SHA_H_0_REG register + * Hash value + */ + +#define SHA_H_0_REG (DR_REG_SHA_BASE + 0x40) + +/* SHA_H_0 : R/W; bitpos: [31:0]; default: 0; + * Stores the 0th 32-bit piece of the Hash value. + */ + +#define SHA_H_0 0xFFFFFFFF +#define SHA_H_0_M (SHA_H_0_V << SHA_H_0_S) +#define SHA_H_0_V 0xFFFFFFFF +#define SHA_H_0_S 0 + +/* SHA_H_1_REG register + * Hash value + */ + +#define SHA_H_1_REG (DR_REG_SHA_BASE + 0x44) + +/* SHA_H_1 : R/W; bitpos: [31:0]; default: 0; + * Stores the 1th 32-bit piece of the Hash value. + */ + +#define SHA_H_1 0xFFFFFFFF +#define SHA_H_1_M (SHA_H_1_V << SHA_H_1_S) +#define SHA_H_1_V 0xFFFFFFFF +#define SHA_H_1_S 0 + +/* SHA_H_2_REG register + * Hash value + */ + +#define SHA_H_2_REG (DR_REG_SHA_BASE + 0x48) + +/* SHA_H_2 : R/W; bitpos: [31:0]; default: 0; + * Stores the 2th 32-bit piece of the Hash value. + */ + +#define SHA_H_2 0xFFFFFFFF +#define SHA_H_2_M (SHA_H_2_V << SHA_H_2_S) +#define SHA_H_2_V 0xFFFFFFFF +#define SHA_H_2_S 0 + +/* SHA_H_3_REG register + * Hash value + */ + +#define SHA_H_3_REG (DR_REG_SHA_BASE + 0x4c) + +/* SHA_H_3 : R/W; bitpos: [31:0]; default: 0; + * Stores the 3th 32-bit piece of the Hash value. + */ + +#define SHA_H_3 0xFFFFFFFF +#define SHA_H_3_M (SHA_H_3_V << SHA_H_3_S) +#define SHA_H_3_V 0xFFFFFFFF +#define SHA_H_3_S 0 + +/* SHA_H_4_REG register + * Hash value + */ + +#define SHA_H_4_REG (DR_REG_SHA_BASE + 0x50) + +/* SHA_H_4 : R/W; bitpos: [31:0]; default: 0; + * Stores the 4th 32-bit piece of the Hash value. + */ + +#define SHA_H_4 0xFFFFFFFF +#define SHA_H_4_M (SHA_H_4_V << SHA_H_4_S) +#define SHA_H_4_V 0xFFFFFFFF +#define SHA_H_4_S 0 + +/* SHA_H_5_REG register + * Hash value + */ + +#define SHA_H_5_REG (DR_REG_SHA_BASE + 0x54) + +/* SHA_H_5 : R/W; bitpos: [31:0]; default: 0; + * Stores the 5th 32-bit piece of the Hash value. + */ + +#define SHA_H_5 0xFFFFFFFF +#define SHA_H_5_M (SHA_H_5_V << SHA_H_5_S) +#define SHA_H_5_V 0xFFFFFFFF +#define SHA_H_5_S 0 + +/* SHA_H_6_REG register + * Hash value + */ + +#define SHA_H_6_REG (DR_REG_SHA_BASE + 0x58) + +/* SHA_H_6 : R/W; bitpos: [31:0]; default: 0; + * Stores the 6th 32-bit piece of the Hash value. + */ + +#define SHA_H_6 0xFFFFFFFF +#define SHA_H_6_M (SHA_H_6_V << SHA_H_6_S) +#define SHA_H_6_V 0xFFFFFFFF +#define SHA_H_6_S 0 + +/* SHA_H_7_REG register + * Hash value + */ + +#define SHA_H_7_REG (DR_REG_SHA_BASE + 0x5c) + +/* SHA_H_7 : R/W; bitpos: [31:0]; default: 0; + * Stores the 7th 32-bit piece of the Hash value. + */ + +#define SHA_H_7 0xFFFFFFFF +#define SHA_H_7_M (SHA_H_7_V << SHA_H_7_S) +#define SHA_H_7_V 0xFFFFFFFF +#define SHA_H_7_S 0 + +/* SHA_H_8_REG register + * Hash value + */ + +#define SHA_H_8_REG (DR_REG_SHA_BASE + 0x60) + +/* SHA_H_8 : R/W; bitpos: [31:0]; default: 0; + * Stores the 8th 32-bit piece of the Hash value. + */ + +#define SHA_H_8 0xFFFFFFFF +#define SHA_H_8_M (SHA_H_8_V << SHA_H_8_S) +#define SHA_H_8_V 0xFFFFFFFF +#define SHA_H_8_S 0 + +/* SHA_H_9_REG register + * Hash value + */ + +#define SHA_H_9_REG (DR_REG_SHA_BASE + 0x64) + +/* SHA_H_9 : R/W; bitpos: [31:0]; default: 0; + * Stores the 9th 32-bit piece of the Hash value. + */ + +#define SHA_H_9 0xFFFFFFFF +#define SHA_H_9_M (SHA_H_9_V << SHA_H_9_S) +#define SHA_H_9_V 0xFFFFFFFF +#define SHA_H_9_S 0 + +/* SHA_H_10_REG register + * Hash value + */ + +#define SHA_H_10_REG (DR_REG_SHA_BASE + 0x68) + +/* SHA_H_10 : R/W; bitpos: [31:0]; default: 0; + * Stores the 10th 32-bit piece of the Hash value. + */ + +#define SHA_H_10 0xFFFFFFFF +#define SHA_H_10_M (SHA_H_10_V << SHA_H_10_S) +#define SHA_H_10_V 0xFFFFFFFF +#define SHA_H_10_S 0 + +/* SHA_H_11_REG register + * Hash value + */ + +#define SHA_H_11_REG (DR_REG_SHA_BASE + 0x6c) + +/* SHA_H_11 : R/W; bitpos: [31:0]; default: 0; + * Stores the 11th 32-bit piece of the Hash value. + */ + +#define SHA_H_11 0xFFFFFFFF +#define SHA_H_11_M (SHA_H_11_V << SHA_H_11_S) +#define SHA_H_11_V 0xFFFFFFFF +#define SHA_H_11_S 0 + +/* SHA_H_12_REG register + * Hash value + */ + +#define SHA_H_12_REG (DR_REG_SHA_BASE + 0x70) + +/* SHA_H_12 : R/W; bitpos: [31:0]; default: 0; + * Stores the 12th 32-bit piece of the Hash value. + */ + +#define SHA_H_12 0xFFFFFFFF +#define SHA_H_12_M (SHA_H_12_V << SHA_H_12_S) +#define SHA_H_12_V 0xFFFFFFFF +#define SHA_H_12_S 0 + +/* SHA_H_13_REG register + * Hash value + */ + +#define SHA_H_13_REG (DR_REG_SHA_BASE + 0x74) + +/* SHA_H_13 : R/W; bitpos: [31:0]; default: 0; + * Stores the 13th 32-bit piece of the Hash value. + */ + +#define SHA_H_13 0xFFFFFFFF +#define SHA_H_13_M (SHA_H_13_V << SHA_H_13_S) +#define SHA_H_13_V 0xFFFFFFFF +#define SHA_H_13_S 0 + +/* SHA_H_14_REG register + * Hash value + */ + +#define SHA_H_14_REG (DR_REG_SHA_BASE + 0x78) + +/* SHA_H_14 : R/W; bitpos: [31:0]; default: 0; + * Stores the 14th 32-bit piece of the Hash value. + */ + +#define SHA_H_14 0xFFFFFFFF +#define SHA_H_14_M (SHA_H_14_V << SHA_H_14_S) +#define SHA_H_14_V 0xFFFFFFFF +#define SHA_H_14_S 0 + +/* SHA_H_15_REG register + * Hash value + */ + +#define SHA_H_15_REG (DR_REG_SHA_BASE + 0x7c) + +/* SHA_H_15 : R/W; bitpos: [31:0]; default: 0; + * Stores the 15th 32-bit piece of the Hash value. + */ + +#define SHA_H_15 0xFFFFFFFF +#define SHA_H_15_M (SHA_H_15_V << SHA_H_15_S) +#define SHA_H_15_V 0xFFFFFFFF +#define SHA_H_15_S 0 + +/* SHA_M_0_REG register + * Message + */ + +#define SHA_M_0_REG (DR_REG_SHA_BASE + 0x80) + +/* SHA_M_0 : R/W; bitpos: [31:0]; default: 0; + * Stores the 0th 32-bit piece of the message. + */ + +#define SHA_M_0 0xFFFFFFFF +#define SHA_M_0_M (SHA_M_0_V << SHA_M_0_S) +#define SHA_M_0_V 0xFFFFFFFF +#define SHA_M_0_S 0 + +/* SHA_M_1_REG register + * Message + */ + +#define SHA_M_1_REG (DR_REG_SHA_BASE + 0x84) + +/* SHA_M_1 : R/W; bitpos: [31:0]; default: 0; + * Stores the 1th 32-bit piece of the message. + */ + +#define SHA_M_1 0xFFFFFFFF +#define SHA_M_1_M (SHA_M_1_V << SHA_M_1_S) +#define SHA_M_1_V 0xFFFFFFFF +#define SHA_M_1_S 0 + +/* SHA_M_2_REG register + * Message + */ + +#define SHA_M_2_REG (DR_REG_SHA_BASE + 0x88) + +/* SHA_M_2 : R/W; bitpos: [31:0]; default: 0; + * Stores the 2th 32-bit piece of the message. + */ + +#define SHA_M_2 0xFFFFFFFF +#define SHA_M_2_M (SHA_M_2_V << SHA_M_2_S) +#define SHA_M_2_V 0xFFFFFFFF +#define SHA_M_2_S 0 + +/* SHA_M_3_REG register + * Message + */ + +#define SHA_M_3_REG (DR_REG_SHA_BASE + 0x8c) + +/* SHA_M_3 : R/W; bitpos: [31:0]; default: 0; + * Stores the 3th 32-bit piece of the message. + */ + +#define SHA_M_3 0xFFFFFFFF +#define SHA_M_3_M (SHA_M_3_V << SHA_M_3_S) +#define SHA_M_3_V 0xFFFFFFFF +#define SHA_M_3_S 0 + +/* SHA_M_4_REG register + * Message + */ + +#define SHA_M_4_REG (DR_REG_SHA_BASE + 0x90) + +/* SHA_M_4 : R/W; bitpos: [31:0]; default: 0; + * Stores the 4th 32-bit piece of the message. + */ + +#define SHA_M_4 0xFFFFFFFF +#define SHA_M_4_M (SHA_M_4_V << SHA_M_4_S) +#define SHA_M_4_V 0xFFFFFFFF +#define SHA_M_4_S 0 + +/* SHA_M_5_REG register + * Message + */ + +#define SHA_M_5_REG (DR_REG_SHA_BASE + 0x94) + +/* SHA_M_5 : R/W; bitpos: [31:0]; default: 0; + * Stores the 5th 32-bit piece of the message. + */ + +#define SHA_M_5 0xFFFFFFFF +#define SHA_M_5_M (SHA_M_5_V << SHA_M_5_S) +#define SHA_M_5_V 0xFFFFFFFF +#define SHA_M_5_S 0 + +/* SHA_M_6_REG register + * Message + */ + +#define SHA_M_6_REG (DR_REG_SHA_BASE + 0x98) + +/* SHA_M_6 : R/W; bitpos: [31:0]; default: 0; + * Stores the 6th 32-bit piece of the message. + */ + +#define SHA_M_6 0xFFFFFFFF +#define SHA_M_6_M (SHA_M_6_V << SHA_M_6_S) +#define SHA_M_6_V 0xFFFFFFFF +#define SHA_M_6_S 0 + +/* SHA_M_7_REG register + * Message + */ + +#define SHA_M_7_REG (DR_REG_SHA_BASE + 0x9c) + +/* SHA_M_7 : R/W; bitpos: [31:0]; default: 0; + * Stores the 7th 32-bit piece of the message. + */ + +#define SHA_M_7 0xFFFFFFFF +#define SHA_M_7_M (SHA_M_7_V << SHA_M_7_S) +#define SHA_M_7_V 0xFFFFFFFF +#define SHA_M_7_S 0 + +/* SHA_M_8_REG register + * Message + */ + +#define SHA_M_8_REG (DR_REG_SHA_BASE + 0xa0) + +/* SHA_M_8 : R/W; bitpos: [31:0]; default: 0; + * Stores the 8th 32-bit piece of the message. + */ + +#define SHA_M_8 0xFFFFFFFF +#define SHA_M_8_M (SHA_M_8_V << SHA_M_8_S) +#define SHA_M_8_V 0xFFFFFFFF +#define SHA_M_8_S 0 + +/* SHA_M_9_REG register + * Message + */ + +#define SHA_M_9_REG (DR_REG_SHA_BASE + 0xa4) + +/* SHA_M_9 : R/W; bitpos: [31:0]; default: 0; + * Stores the 9th 32-bit piece of the message. + */ + +#define SHA_M_9 0xFFFFFFFF +#define SHA_M_9_M (SHA_M_9_V << SHA_M_9_S) +#define SHA_M_9_V 0xFFFFFFFF +#define SHA_M_9_S 0 + +/* SHA_M_10_REG register + * Message + */ + +#define SHA_M_10_REG (DR_REG_SHA_BASE + 0xa8) + +/* SHA_M_10 : R/W; bitpos: [31:0]; default: 0; + * Stores the 10th 32-bit piece of the message. + */ + +#define SHA_M_10 0xFFFFFFFF +#define SHA_M_10_M (SHA_M_10_V << SHA_M_10_S) +#define SHA_M_10_V 0xFFFFFFFF +#define SHA_M_10_S 0 + +/* SHA_M_11_REG register + * Message + */ + +#define SHA_M_11_REG (DR_REG_SHA_BASE + 0xac) + +/* SHA_M_11 : R/W; bitpos: [31:0]; default: 0; + * Stores the 11th 32-bit piece of the message. + */ + +#define SHA_M_11 0xFFFFFFFF +#define SHA_M_11_M (SHA_M_11_V << SHA_M_11_S) +#define SHA_M_11_V 0xFFFFFFFF +#define SHA_M_11_S 0 + +/* SHA_M_12_REG register + * Message + */ + +#define SHA_M_12_REG (DR_REG_SHA_BASE + 0xb0) + +/* SHA_M_12 : R/W; bitpos: [31:0]; default: 0; + * Stores the 12th 32-bit piece of the message. + */ + +#define SHA_M_12 0xFFFFFFFF +#define SHA_M_12_M (SHA_M_12_V << SHA_M_12_S) +#define SHA_M_12_V 0xFFFFFFFF +#define SHA_M_12_S 0 + +/* SHA_M_13_REG register + * Message + */ + +#define SHA_M_13_REG (DR_REG_SHA_BASE + 0xb4) + +/* SHA_M_13 : R/W; bitpos: [31:0]; default: 0; + * Stores the 13th 32-bit piece of the message. + */ + +#define SHA_M_13 0xFFFFFFFF +#define SHA_M_13_M (SHA_M_13_V << SHA_M_13_S) +#define SHA_M_13_V 0xFFFFFFFF +#define SHA_M_13_S 0 + +/* SHA_M_14_REG register + * Message + */ + +#define SHA_M_14_REG (DR_REG_SHA_BASE + 0xb8) + +/* SHA_M_14 : R/W; bitpos: [31:0]; default: 0; + * Stores the 14th 32-bit piece of the message. + */ + +#define SHA_M_14 0xFFFFFFFF +#define SHA_M_14_M (SHA_M_14_V << SHA_M_14_S) +#define SHA_M_14_V 0xFFFFFFFF +#define SHA_M_14_S 0 + +/* SHA_M_15_REG register + * Message + */ + +#define SHA_M_15_REG (DR_REG_SHA_BASE + 0xbc) + +/* SHA_M_15 : R/W; bitpos: [31:0]; default: 0; + * Stores the 15th 32-bit piece of the message. + */ + +#define SHA_M_15 0xFFFFFFFF +#define SHA_M_15_M (SHA_M_15_V << SHA_M_15_S) +#define SHA_M_15_V 0xFFFFFFFF +#define SHA_M_15_S 0 + +/* SHA_M_16_REG register + * Message + */ + +#define SHA_M_16_REG (DR_REG_SHA_BASE + 0xc0) + +/* SHA_M_16 : R/W; bitpos: [31:0]; default: 0; + * Stores the 16th 32-bit piece of the message. + */ + +#define SHA_M_16 0xFFFFFFFF +#define SHA_M_16_M (SHA_M_16_V << SHA_M_16_S) +#define SHA_M_16_V 0xFFFFFFFF +#define SHA_M_16_S 0 + +/* SHA_M_17_REG register + * Message + */ + +#define SHA_M_17_REG (DR_REG_SHA_BASE + 0xc4) + +/* SHA_M_17 : R/W; bitpos: [31:0]; default: 0; + * Stores the 17th 32-bit piece of the message. + */ + +#define SHA_M_17 0xFFFFFFFF +#define SHA_M_17_M (SHA_M_17_V << SHA_M_17_S) +#define SHA_M_17_V 0xFFFFFFFF +#define SHA_M_17_S 0 + +/* SHA_M_18_REG register + * Message + */ + +#define SHA_M_18_REG (DR_REG_SHA_BASE + 0xc8) + +/* SHA_M_18 : R/W; bitpos: [31:0]; default: 0; + * Stores the 18th 32-bit piece of the message. + */ + +#define SHA_M_18 0xFFFFFFFF +#define SHA_M_18_M (SHA_M_18_V << SHA_M_18_S) +#define SHA_M_18_V 0xFFFFFFFF +#define SHA_M_18_S 0 + +/* SHA_M_19_REG register + * Message + */ + +#define SHA_M_19_REG (DR_REG_SHA_BASE + 0xcc) + +/* SHA_M_19 : R/W; bitpos: [31:0]; default: 0; + * Stores the 19th 32-bit piece of the message. + */ + +#define SHA_M_19 0xFFFFFFFF +#define SHA_M_19_M (SHA_M_19_V << SHA_M_19_S) +#define SHA_M_19_V 0xFFFFFFFF +#define SHA_M_19_S 0 + +/* SHA_M_20_REG register + * Message + */ + +#define SHA_M_20_REG (DR_REG_SHA_BASE + 0xd0) + +/* SHA_M_20 : R/W; bitpos: [31:0]; default: 0; + * Stores the 20th 32-bit piece of the message. + */ + +#define SHA_M_20 0xFFFFFFFF +#define SHA_M_20_M (SHA_M_20_V << SHA_M_20_S) +#define SHA_M_20_V 0xFFFFFFFF +#define SHA_M_20_S 0 + +/* SHA_M_21_REG register + * Message + */ + +#define SHA_M_21_REG (DR_REG_SHA_BASE + 0xd4) + +/* SHA_M_21 : R/W; bitpos: [31:0]; default: 0; + * Stores the 21th 32-bit piece of the message. + */ + +#define SHA_M_21 0xFFFFFFFF +#define SHA_M_21_M (SHA_M_21_V << SHA_M_21_S) +#define SHA_M_21_V 0xFFFFFFFF +#define SHA_M_21_S 0 + +/* SHA_M_22_REG register + * Message + */ + +#define SHA_M_22_REG (DR_REG_SHA_BASE + 0xd8) + +/* SHA_M_22 : R/W; bitpos: [31:0]; default: 0; + * Stores the 22th 32-bit piece of the message. + */ + +#define SHA_M_22 0xFFFFFFFF +#define SHA_M_22_M (SHA_M_22_V << SHA_M_22_S) +#define SHA_M_22_V 0xFFFFFFFF +#define SHA_M_22_S 0 + +/* SHA_M_23_REG register + * Message + */ + +#define SHA_M_23_REG (DR_REG_SHA_BASE + 0xdc) + +/* SHA_M_23 : R/W; bitpos: [31:0]; default: 0; + * Stores the 23th 32-bit piece of the message. + */ + +#define SHA_M_23 0xFFFFFFFF +#define SHA_M_23_M (SHA_M_23_V << SHA_M_23_S) +#define SHA_M_23_V 0xFFFFFFFF +#define SHA_M_23_S 0 + +/* SHA_M_24_REG register + * Message + */ + +#define SHA_M_24_REG (DR_REG_SHA_BASE + 0xe0) + +/* SHA_M_24 : R/W; bitpos: [31:0]; default: 0; + * Stores the 24th 32-bit piece of the message. + */ + +#define SHA_M_24 0xFFFFFFFF +#define SHA_M_24_M (SHA_M_24_V << SHA_M_24_S) +#define SHA_M_24_V 0xFFFFFFFF +#define SHA_M_24_S 0 + +/* SHA_M_25_REG register + * Message + */ + +#define SHA_M_25_REG (DR_REG_SHA_BASE + 0xe4) + +/* SHA_M_25 : R/W; bitpos: [31:0]; default: 0; + * Stores the 25th 32-bit piece of the message. + */ + +#define SHA_M_25 0xFFFFFFFF +#define SHA_M_25_M (SHA_M_25_V << SHA_M_25_S) +#define SHA_M_25_V 0xFFFFFFFF +#define SHA_M_25_S 0 + +/* SHA_M_26_REG register + * Message + */ + +#define SHA_M_26_REG (DR_REG_SHA_BASE + 0xe8) + +/* SHA_M_26 : R/W; bitpos: [31:0]; default: 0; + * Stores the 26th 32-bit piece of the message. + */ + +#define SHA_M_26 0xFFFFFFFF +#define SHA_M_26_M (SHA_M_26_V << SHA_M_26_S) +#define SHA_M_26_V 0xFFFFFFFF +#define SHA_M_26_S 0 + +/* SHA_M_27_REG register + * Message + */ + +#define SHA_M_27_REG (DR_REG_SHA_BASE + 0xec) + +/* SHA_M_27 : R/W; bitpos: [31:0]; default: 0; + * Stores the 27th 32-bit piece of the message. + */ + +#define SHA_M_27 0xFFFFFFFF +#define SHA_M_27_M (SHA_M_27_V << SHA_M_27_S) +#define SHA_M_27_V 0xFFFFFFFF +#define SHA_M_27_S 0 + +/* SHA_M_28_REG register + * Message + */ + +#define SHA_M_28_REG (DR_REG_SHA_BASE + 0xf0) + +/* SHA_M_28 : R/W; bitpos: [31:0]; default: 0; + * Stores the 28th 32-bit piece of the message. + */ + +#define SHA_M_28 0xFFFFFFFF +#define SHA_M_28_M (SHA_M_28_V << SHA_M_28_S) +#define SHA_M_28_V 0xFFFFFFFF +#define SHA_M_28_S 0 + +/* SHA_M_29_REG register + * Message + */ + +#define SHA_M_29_REG (DR_REG_SHA_BASE + 0xf4) + +/* SHA_M_29 : R/W; bitpos: [31:0]; default: 0; + * Stores the 29th 32-bit piece of the message. + */ + +#define SHA_M_29 0xFFFFFFFF +#define SHA_M_29_M (SHA_M_29_V << SHA_M_29_S) +#define SHA_M_29_V 0xFFFFFFFF +#define SHA_M_29_S 0 + +/* SHA_M_30_REG register + * Message + */ + +#define SHA_M_30_REG (DR_REG_SHA_BASE + 0xf8) + +/* SHA_M_30 : R/W; bitpos: [31:0]; default: 0; + * Stores the 30th 32-bit piece of the message. + */ + +#define SHA_M_30 0xFFFFFFFF +#define SHA_M_30_M (SHA_M_30_V << SHA_M_30_S) +#define SHA_M_30_V 0xFFFFFFFF +#define SHA_M_30_S 0 + +/* SHA_M_31_REG register + * Message + */ + +#define SHA_M_31_REG (DR_REG_SHA_BASE + 0xfc) + +/* SHA_M_31 : R/W; bitpos: [31:0]; default: 0; + * Stores the 31th 32-bit piece of the message. + */ + +#define SHA_M_31 0xFFFFFFFF +#define SHA_M_31_M (SHA_M_31_V << SHA_M_31_S) +#define SHA_M_31_V 0xFFFFFFFF +#define SHA_M_31_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SHA_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_soc.h similarity index 98% rename from arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h rename to arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_soc.h index ead5c1f7c5a9d..4cf63e6737274 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_soc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_soc.h + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_soc.h * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -15,8 +15,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SOC_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SOC_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SOC_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SOC_H /**************************************************************************** * Included Files @@ -326,4 +326,4 @@ static inline bool IRAM_ATTR esp32c3_ptr_rtc(const void *p) (intptr_t)p < SOC_RTC_RAM_HIGH); } -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SOC_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SOC_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_spi.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_spi.h new file mode 100644 index 0000000000000..f765015f1444e --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_spi.h @@ -0,0 +1,2214 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_spi.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SPI_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SPI_CMD_REG register + * Command control register + */ + +#define SPI_CMD_REG (DR_REG_SPI2_BASE + 0x0) + +/* SPI_USR : R/W/SC; bitpos: [24]; default: 0; + * User define command enable. An operation will be triggered when the bit + * is set. The bit will be cleared once the operation done.1: enable 0: + * disable. Can not be changed by CONF_buf. + */ + +#define SPI_USR (BIT(24)) +#define SPI_USR_M (SPI_USR_V << SPI_USR_S) +#define SPI_USR_V 0x00000001 +#define SPI_USR_S 24 + +/* SPI_UPDATE : WT; bitpos: [23]; default: 0; + * Set this bit to synchronize SPI registers from APB clock domain into SPI + * module clock domain, which is only used in SPI master mode. + */ + +#define SPI_UPDATE (BIT(23)) +#define SPI_UPDATE_M (SPI_UPDATE_V << SPI_UPDATE_S) +#define SPI_UPDATE_V 0x00000001 +#define SPI_UPDATE_S 23 + +/* SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0; + * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. + */ + +#define SPI_CONF_BITLEN 0x0003FFFF +#define SPI_CONF_BITLEN_M (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S) +#define SPI_CONF_BITLEN_V 0x0003FFFF +#define SPI_CONF_BITLEN_S 0 + +/* SPI_ADDR_REG register + * Address value register + */ + +#define SPI_ADDR_REG (DR_REG_SPI2_BASE + 0x4) + +/* SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; + * Address to slave. Can be configured in CONF state. + */ + +#define SPI_USR_ADDR_VALUE 0xFFFFFFFF +#define SPI_USR_ADDR_VALUE_M (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S) +#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFF +#define SPI_USR_ADDR_VALUE_S 0 + +/* SPI_CTRL_REG register + * SPI control register + */ + +#define SPI_CTRL_REG (DR_REG_SPI2_BASE + 0x8) + +/* SPI_WR_BIT_ORDER : R/W; bitpos: [26]; default: 0; + * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can + * be configured in CONF state. + */ + +#define SPI_WR_BIT_ORDER (BIT(26)) +#define SPI_WR_BIT_ORDER_M (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S) +#define SPI_WR_BIT_ORDER_V 0x00000001 +#define SPI_WR_BIT_ORDER_S 26 + +/* SPI_RD_BIT_ORDER : R/W; bitpos: [25]; default: 0; + * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in + * CONF state. + */ + +#define SPI_RD_BIT_ORDER (BIT(25)) +#define SPI_RD_BIT_ORDER_M (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S) +#define SPI_RD_BIT_ORDER_V 0x00000001 +#define SPI_RD_BIT_ORDER_S 25 + +/* SPI_WP_POL : R/W; bitpos: [21]; default: 1; + * Write protect signal output when SPI is idle. 1: output high, 0: output + * low. Can be configured in CONF state. + */ + +#define SPI_WP_POL (BIT(21)) +#define SPI_WP_POL_M (SPI_WP_POL_V << SPI_WP_POL_S) +#define SPI_WP_POL_V 0x00000001 +#define SPI_WP_POL_S 21 + +/* SPI_HOLD_POL : R/W; bitpos: [20]; default: 1; + * SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. + * Can be configured in CONF state. + */ + +#define SPI_HOLD_POL (BIT(20)) +#define SPI_HOLD_POL_M (SPI_HOLD_POL_V << SPI_HOLD_POL_S) +#define SPI_HOLD_POL_V 0x00000001 +#define SPI_HOLD_POL_S 20 + +/* SPI_D_POL : R/W; bitpos: [19]; default: 1; + * The bit is used to set MOSI line polarity, 1: high 0, low. Can be + * configured in CONF state. + */ + +#define SPI_D_POL (BIT(19)) +#define SPI_D_POL_M (SPI_D_POL_V << SPI_D_POL_S) +#define SPI_D_POL_V 0x00000001 +#define SPI_D_POL_S 19 + +/* SPI_Q_POL : R/W; bitpos: [18]; default: 1; + * The bit is used to set MISO line polarity, 1: high 0, low. Can be + * configured in CONF state. + */ + +#define SPI_Q_POL (BIT(18)) +#define SPI_Q_POL_M (SPI_Q_POL_V << SPI_Q_POL_S) +#define SPI_Q_POL_V 0x00000001 +#define SPI_Q_POL_S 18 + +/* SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0; + * In the read operations read-data phase apply 4 signals. 1: enable 0: + * disable. Can be configured in CONF state. + */ + +#define SPI_FREAD_QUAD (BIT(15)) +#define SPI_FREAD_QUAD_M (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S) +#define SPI_FREAD_QUAD_V 0x00000001 +#define SPI_FREAD_QUAD_S 15 + +/* SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0; + * In the read operations, read-data phase apply 2 signals. 1: enable 0: + * disable. Can be configured in CONF state. + */ + +#define SPI_FREAD_DUAL (BIT(14)) +#define SPI_FREAD_DUAL_M (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S) +#define SPI_FREAD_DUAL_V 0x00000001 +#define SPI_FREAD_DUAL_S 14 + +/* SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0; + * Apply 4 signals during command phase 1:enable 0: disable. Can be + * configured in CONF state. + */ + +#define SPI_FCMD_QUAD (BIT(9)) +#define SPI_FCMD_QUAD_M (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S) +#define SPI_FCMD_QUAD_V 0x00000001 +#define SPI_FCMD_QUAD_S 9 + +/* SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0; + * Apply 2 signals during command phase 1:enable 0: disable. Can be + * configured in CONF state. + */ + +#define SPI_FCMD_DUAL (BIT(8)) +#define SPI_FCMD_DUAL_M (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S) +#define SPI_FCMD_DUAL_V 0x00000001 +#define SPI_FCMD_DUAL_S 8 + +/* SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0; + * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured + * in CONF state. + */ + +#define SPI_FADDR_QUAD (BIT(6)) +#define SPI_FADDR_QUAD_M (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S) +#define SPI_FADDR_QUAD_V 0x00000001 +#define SPI_FADDR_QUAD_S 6 + +/* SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0; + * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured + * in CONF state. + */ + +#define SPI_FADDR_DUAL (BIT(5)) +#define SPI_FADDR_DUAL_M (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S) +#define SPI_FADDR_DUAL_V 0x00000001 +#define SPI_FADDR_DUAL_S 5 + +/* SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0; + * In the dummy phase the signal level of spi is output by the spi + * controller. Can be configured in CONF state. + */ + +#define SPI_DUMMY_OUT (BIT(3)) +#define SPI_DUMMY_OUT_M (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S) +#define SPI_DUMMY_OUT_V 0x00000001 +#define SPI_DUMMY_OUT_S 3 + +/* SPI_CLOCK_REG register + * SPI clock control register + */ + +#define SPI_CLOCK_REG (DR_REG_SPI2_BASE + 0xc) + +/* SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; + * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided + * from system clock. Can be configured in CONF state. + */ + +#define SPI_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_M (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S) +#define SPI_CLK_EQU_SYSCLK_V 0x00000001 +#define SPI_CLK_EQU_SYSCLK_S 31 + +/* SPI_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0; + * In the master mode it is pre-divider of spi_clk. Can be configured in + * CONF state. + */ + +#define SPI_CLKDIV_PRE 0x0000000F +#define SPI_CLKDIV_PRE_M (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S) +#define SPI_CLKDIV_PRE_V 0x0000000F +#define SPI_CLKDIV_PRE_S 18 + +/* SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3; + * In the master mode it is the divider of spi_clk. So spi_clk frequency is + * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF + * state. + */ + +#define SPI_CLKCNT_N 0x0000003F +#define SPI_CLKCNT_N_M (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S) +#define SPI_CLKCNT_N_V 0x0000003F +#define SPI_CLKCNT_N_S 12 + +/* SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1; + * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave + * mode it must be 0. Can be configured in CONF state. + */ + +#define SPI_CLKCNT_H 0x0000003F +#define SPI_CLKCNT_H_M (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S) +#define SPI_CLKCNT_H_V 0x0000003F +#define SPI_CLKCNT_H_S 6 + +/* SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3; + * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it + * must be 0. Can be configured in CONF state. + */ + +#define SPI_CLKCNT_L 0x0000003F +#define SPI_CLKCNT_L_M (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S) +#define SPI_CLKCNT_L_V 0x0000003F +#define SPI_CLKCNT_L_S 0 + +/* SPI_USER_REG register + * SPI USER control register + */ + +#define SPI_USER_REG (DR_REG_SPI2_BASE + 0x10) + +/* SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1; + * This bit enable the command phase of an operation. Can be configured in + * CONF state. + */ + +#define SPI_USR_COMMAND (BIT(31)) +#define SPI_USR_COMMAND_M (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S) +#define SPI_USR_COMMAND_V 0x00000001 +#define SPI_USR_COMMAND_S 31 + +/* SPI_USR_ADDR : R/W; bitpos: [30]; default: 0; + * This bit enable the address phase of an operation. Can be configured in + * CONF state. + */ + +#define SPI_USR_ADDR (BIT(30)) +#define SPI_USR_ADDR_M (SPI_USR_ADDR_V << SPI_USR_ADDR_S) +#define SPI_USR_ADDR_V 0x00000001 +#define SPI_USR_ADDR_S 30 + +/* SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0; + * This bit enable the dummy phase of an operation. Can be configured in + * CONF state. + */ + +#define SPI_USR_DUMMY (BIT(29)) +#define SPI_USR_DUMMY_M (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S) +#define SPI_USR_DUMMY_V 0x00000001 +#define SPI_USR_DUMMY_S 29 + +/* SPI_USR_MISO : R/W; bitpos: [28]; default: 0; + * This bit enable the read-data phase of an operation. Can be configured in + * CONF state. + */ + +#define SPI_USR_MISO (BIT(28)) +#define SPI_USR_MISO_M (SPI_USR_MISO_V << SPI_USR_MISO_S) +#define SPI_USR_MISO_V 0x00000001 +#define SPI_USR_MISO_S 28 + +/* SPI_USR_MOSI : R/W; bitpos: [27]; default: 0; + * This bit enable the write-data phase of an operation. Can be configured + * in CONF state. + */ + +#define SPI_USR_MOSI (BIT(27)) +#define SPI_USR_MOSI_M (SPI_USR_MOSI_V << SPI_USR_MOSI_S) +#define SPI_USR_MOSI_V 0x00000001 +#define SPI_USR_MOSI_S 27 + +/* SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; + * spi clock is disable in dummy phase when the bit is enable. Can be + * configured in CONF state. + */ + +#define SPI_USR_DUMMY_IDLE (BIT(26)) +#define SPI_USR_DUMMY_IDLE_M (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S) +#define SPI_USR_DUMMY_IDLE_V 0x00000001 +#define SPI_USR_DUMMY_IDLE_S 26 + +/* SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; + * write-data phase only access to high-part of the buffer spi_w8~spi_w15. + * 1: enable 0: disable. Can be configured in CONF state. + */ + +#define SPI_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_M (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S) +#define SPI_USR_MOSI_HIGHPART_V 0x00000001 +#define SPI_USR_MOSI_HIGHPART_S 25 + +/* SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; + * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: + * enable 0: disable. Can be configured in CONF state. + */ + +#define SPI_USR_MISO_HIGHPART (BIT(24)) +#define SPI_USR_MISO_HIGHPART_M (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S) +#define SPI_USR_MISO_HIGHPART_V 0x00000001 +#define SPI_USR_MISO_HIGHPART_S 24 + +/* SPI_SIO : R/W; bitpos: [17]; default: 0; + * Set the bit to enable 3-line half duplex communication mosi and miso + * signals share the same pin. 1: enable 0: disable. Can be configured in + * CONF state. + */ + +#define SPI_SIO (BIT(17)) +#define SPI_SIO_M (SPI_SIO_V << SPI_SIO_S) +#define SPI_SIO_V 0x00000001 +#define SPI_SIO_S 17 + +/* SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0; + * 1: Enable the DMA CONF phase of next seg-trans operation, which means + * seg-trans will continue. 0: The seg-trans will end after the current SPI + * seg-trans or this is not seg-trans mode. Can be configured in CONF state. + */ + +#define SPI_USR_CONF_NXT (BIT(15)) +#define SPI_USR_CONF_NXT_M (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S) +#define SPI_USR_CONF_NXT_V 0x00000001 +#define SPI_USR_CONF_NXT_S 15 + +/* SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0; + * In the write operations read-data phase apply 4 signals. Can be + * configured in CONF state. + */ + +#define SPI_FWRITE_QUAD (BIT(13)) +#define SPI_FWRITE_QUAD_M (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S) +#define SPI_FWRITE_QUAD_V 0x00000001 +#define SPI_FWRITE_QUAD_S 13 + +/* SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0; + * In the write operations read-data phase apply 2 signals. Can be + * configured in CONF state. + */ + +#define SPI_FWRITE_DUAL (BIT(12)) +#define SPI_FWRITE_DUAL_M (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S) +#define SPI_FWRITE_DUAL_V 0x00000001 +#define SPI_FWRITE_DUAL_S 12 + +/* SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; + * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay + * mode. Can be configured in CONF state. + */ + +#define SPI_CK_OUT_EDGE (BIT(9)) +#define SPI_CK_OUT_EDGE_M (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S) +#define SPI_CK_OUT_EDGE_V 0x00000001 +#define SPI_CK_OUT_EDGE_S 9 + +/* SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0; + * In the slave mode, this bit can be used to change the polarity of rsck. + * 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. + */ + +#define SPI_RSCK_I_EDGE (BIT(8)) +#define SPI_RSCK_I_EDGE_M (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S) +#define SPI_RSCK_I_EDGE_V 0x00000001 +#define SPI_RSCK_I_EDGE_S 8 + +/* SPI_CS_SETUP : R/W; bitpos: [7]; default: 1; + * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. + * Can be configured in CONF state. + */ + +#define SPI_CS_SETUP (BIT(7)) +#define SPI_CS_SETUP_M (SPI_CS_SETUP_V << SPI_CS_SETUP_S) +#define SPI_CS_SETUP_V 0x00000001 +#define SPI_CS_SETUP_S 7 + +/* SPI_CS_HOLD : R/W; bitpos: [6]; default: 1; + * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be + * configured in CONF state. + */ + +#define SPI_CS_HOLD (BIT(6)) +#define SPI_CS_HOLD_M (SPI_CS_HOLD_V << SPI_CS_HOLD_S) +#define SPI_CS_HOLD_V 0x00000001 +#define SPI_CS_HOLD_S 6 + +/* SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0; + * In the slave mode, this bit can be used to change the polarity of tsck. + * 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. + */ + +#define SPI_TSCK_I_EDGE (BIT(5)) +#define SPI_TSCK_I_EDGE_M (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S) +#define SPI_TSCK_I_EDGE_V 0x00000001 +#define SPI_TSCK_I_EDGE_S 5 + +/* SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0; + * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: + * others. Can be configured in CONF state. + */ + +#define SPI_QPI_MODE (BIT(3)) +#define SPI_QPI_MODE_M (SPI_QPI_MODE_V << SPI_QPI_MODE_S) +#define SPI_QPI_MODE_V 0x00000001 +#define SPI_QPI_MODE_S 3 + +/* SPI_DOUTDIN : R/W; bitpos: [0]; default: 0; + * Set the bit to enable full duplex communication. 1: enable 0: disable. + * Can be configured in CONF state. + */ + +#define SPI_DOUTDIN (BIT(0)) +#define SPI_DOUTDIN_M (SPI_DOUTDIN_V << SPI_DOUTDIN_S) +#define SPI_DOUTDIN_V 0x00000001 +#define SPI_DOUTDIN_S 0 + +/* SPI_USER1_REG register + * SPI USER control register 1 + */ + +#define SPI_USER1_REG (DR_REG_SPI2_BASE + 0x14) + +/* SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23; + * The length in bits of address phase. The register value shall be + * (bit_num-1). Can be configured in CONF state. + */ + +#define SPI_USR_ADDR_BITLEN 0x0000001F +#define SPI_USR_ADDR_BITLEN_M (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S) +#define SPI_USR_ADDR_BITLEN_V 0x0000001F +#define SPI_USR_ADDR_BITLEN_S 27 + +/* SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1; + * delay cycles of cs pin by spi clock this bits are combined with + * spi_cs_hold bit. Can be configured in CONF state. + */ + +#define SPI_CS_HOLD_TIME 0x0000001F +#define SPI_CS_HOLD_TIME_M (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S) +#define SPI_CS_HOLD_TIME_V 0x0000001F +#define SPI_CS_HOLD_TIME_S 22 + +/* SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0; + * (cycles+1) of prepare phase by spi clock this bits are combined with + * spi_cs_setup bit. Can be configured in CONF state. + */ + +#define SPI_CS_SETUP_TIME 0x0000001F +#define SPI_CS_SETUP_TIME_M (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S) +#define SPI_CS_SETUP_TIME_V 0x0000001F +#define SPI_CS_SETUP_TIME_S 17 + +/* SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1; + * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI + * master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull + * error is valid in GP-SPI master FD/HD-mode. + */ + +#define SPI_MST_WFULL_ERR_END_EN (BIT(16)) +#define SPI_MST_WFULL_ERR_END_EN_M (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S) +#define SPI_MST_WFULL_ERR_END_EN_V 0x00000001 +#define SPI_MST_WFULL_ERR_END_EN_S 16 + +/* SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7; + * The length in spi_clk cycles of dummy phase. The register value shall be + * (cycle_num-1). Can be configured in CONF state. + */ + +#define SPI_USR_DUMMY_CYCLELEN 0x000000FF +#define SPI_USR_DUMMY_CYCLELEN_M (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S) +#define SPI_USR_DUMMY_CYCLELEN_V 0x000000FF +#define SPI_USR_DUMMY_CYCLELEN_S 0 + +/* SPI_USER2_REG register + * SPI USER control register 2 + */ + +#define SPI_USER2_REG (DR_REG_SPI2_BASE + 0x18) + +/* SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; + * The length in bits of command phase. The register value shall be + * (bit_num-1). Can be configured in CONF state. + */ + +#define SPI_USR_COMMAND_BITLEN 0x0000000F +#define SPI_USR_COMMAND_BITLEN_M (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S) +#define SPI_USR_COMMAND_BITLEN_V 0x0000000F +#define SPI_USR_COMMAND_BITLEN_S 28 + +/* SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1; + * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in + * GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO + * read empty error is valid in GP-SPI master FD/HD-mode. + */ + +#define SPI_MST_REMPTY_ERR_END_EN (BIT(27)) +#define SPI_MST_REMPTY_ERR_END_EN_M (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S) +#define SPI_MST_REMPTY_ERR_END_EN_V 0x00000001 +#define SPI_MST_REMPTY_ERR_END_EN_S 27 + +/* SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; + * The value of command. Can be configured in CONF state. + */ + +#define SPI_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_USR_COMMAND_VALUE_M (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S) +#define SPI_USR_COMMAND_VALUE_V 0x0000FFFF +#define SPI_USR_COMMAND_VALUE_S 0 + +/* SPI_MS_DLEN_REG register + * SPI data bit length control register + */ + +#define SPI_MS_DLEN_REG (DR_REG_SPI2_BASE + 0x1c) + +/* SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0; + * The value of these bits is the configured SPI transmission data bit + * length in master mode DMA controlled transfer or CPU controlled transfer. + * The value is also the configured bit length in slave mode DMA RX + * controlled transfer. The register value shall be (bit_num-1). Can be + * configured in CONF state. + */ + +#define SPI_MS_DATA_BITLEN 0x0003FFFF +#define SPI_MS_DATA_BITLEN_M (SPI_MS_DATA_BITLEN_V << SPI_MS_DATA_BITLEN_S) +#define SPI_MS_DATA_BITLEN_V 0x0003FFFF +#define SPI_MS_DATA_BITLEN_S 0 + +/* SPI_MISC_REG register + * SPI misc register + */ + +#define SPI_MISC_REG (DR_REG_SPI2_BASE + 0x20) + +/* SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0; + * 1: spi quad input swap enable 0: spi quad input swap disable. Can be + * configured in CONF state. + */ + +#define SPI_QUAD_DIN_PIN_SWAP (BIT(31)) +#define SPI_QUAD_DIN_PIN_SWAP_M (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S) +#define SPI_QUAD_DIN_PIN_SWAP_V 0x00000001 +#define SPI_QUAD_DIN_PIN_SWAP_S 31 + +/* SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0; + * spi cs line keep low when the bit is set. Can be configured in CONF state. + */ + +#define SPI_CS_KEEP_ACTIVE (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_M (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S) +#define SPI_CS_KEEP_ACTIVE_V 0x00000001 +#define SPI_CS_KEEP_ACTIVE_S 30 + +/* SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0; + * 1: spi clk line is high when idle 0: spi clk line is low when idle. + * Can be configured in CONF state. + */ + +#define SPI_CK_IDLE_EDGE (BIT(29)) +#define SPI_CK_IDLE_EDGE_M (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S) +#define SPI_CK_IDLE_EDGE_V 0x00000001 +#define SPI_CK_IDLE_EDGE_S 29 + +/* SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0; + * spi slave input cs polarity select. 1: inv 0: not change. Can be + * configured in CONF state. + */ + +#define SPI_SLAVE_CS_POL (BIT(23)) +#define SPI_SLAVE_CS_POL_M (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S) +#define SPI_SLAVE_CS_POL_V 0x00000001 +#define SPI_SLAVE_CS_POL_S 23 + +/* SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0; + * In the master mode the bits are the polarity of spi cs line, the value is + * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. + */ + +#define SPI_MASTER_CS_POL 0x0000003F +#define SPI_MASTER_CS_POL_M (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S) +#define SPI_MASTER_CS_POL_V 0x0000003F +#define SPI_MASTER_CS_POL_S 7 + +/* SPI_CK_DIS : R/W; bitpos: [6]; default: 0; + * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF + * state. + */ + +#define SPI_CK_DIS (BIT(6)) +#define SPI_CK_DIS_M (SPI_CK_DIS_V << SPI_CK_DIS_S) +#define SPI_CK_DIS_V 0x00000001 +#define SPI_CK_DIS_S 6 + +/* SPI_CS5_DIS : R/W; bitpos: [5]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n + * pin. Can be configured in CONF state. + */ + +#define SPI_CS5_DIS (BIT(5)) +#define SPI_CS5_DIS_M (SPI_CS5_DIS_V << SPI_CS5_DIS_S) +#define SPI_CS5_DIS_V 0x00000001 +#define SPI_CS5_DIS_S 5 + +/* SPI_CS4_DIS : R/W; bitpos: [4]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n + * pin. Can be configured in CONF state. + */ + +#define SPI_CS4_DIS (BIT(4)) +#define SPI_CS4_DIS_M (SPI_CS4_DIS_V << SPI_CS4_DIS_S) +#define SPI_CS4_DIS_V 0x00000001 +#define SPI_CS4_DIS_S 4 + +/* SPI_CS3_DIS : R/W; bitpos: [3]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n + * pin. Can be configured in CONF state. + */ + +#define SPI_CS3_DIS (BIT(3)) +#define SPI_CS3_DIS_M (SPI_CS3_DIS_V << SPI_CS3_DIS_S) +#define SPI_CS3_DIS_V 0x00000001 +#define SPI_CS3_DIS_S 3 + +/* SPI_CS2_DIS : R/W; bitpos: [2]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n + * pin. Can be configured in CONF state. + */ + +#define SPI_CS2_DIS (BIT(2)) +#define SPI_CS2_DIS_M (SPI_CS2_DIS_V << SPI_CS2_DIS_S) +#define SPI_CS2_DIS_V 0x00000001 +#define SPI_CS2_DIS_S 2 + +/* SPI_CS1_DIS : R/W; bitpos: [1]; default: 1; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n + * pin. Can be configured in CONF state. + */ + +#define SPI_CS1_DIS (BIT(1)) +#define SPI_CS1_DIS_M (SPI_CS1_DIS_V << SPI_CS1_DIS_S) +#define SPI_CS1_DIS_V 0x00000001 +#define SPI_CS1_DIS_S 1 + +/* SPI_CS0_DIS : R/W; bitpos: [0]; default: 0; + * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n + * pin. Can be configured in CONF state. + */ + +#define SPI_CS0_DIS (BIT(0)) +#define SPI_CS0_DIS_M (SPI_CS0_DIS_V << SPI_CS0_DIS_S) +#define SPI_CS0_DIS_V 0x00000001 +#define SPI_CS0_DIS_S 0 + +/* SPI_DIN_MODE_REG register + * SPI input delay mode configuration + */ + +#define SPI_DIN_MODE_REG (DR_REG_SPI2_BASE + 0x24) + +/* SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0; + * 1:enable hclk in SPI input timing module. 0: disable it. Can be + * configured in CONF state. + */ + +#define SPI_TIMING_HCLK_ACTIVE (BIT(16)) +#define SPI_TIMING_HCLK_ACTIVE_M (SPI_TIMING_HCLK_ACTIVE_V << SPI_TIMING_HCLK_ACTIVE_S) +#define SPI_TIMING_HCLK_ACTIVE_V 0x00000001 +#define SPI_TIMING_HCLK_ACTIVE_S 16 + +/* SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input + * without delayed, 1: input with the posedge of clk_apb,2 input with the + * negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF + * state. + */ + +#define SPI_DIN3_MODE 0x00000003 +#define SPI_DIN3_MODE_M (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S) +#define SPI_DIN3_MODE_V 0x00000003 +#define SPI_DIN3_MODE_S 6 + +/* SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input + * without delayed, 1: input with the posedge of clk_apb,2 input with the + * negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF + * state. + */ + +#define SPI_DIN2_MODE 0x00000003 +#define SPI_DIN2_MODE_M (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S) +#define SPI_DIN2_MODE_V 0x00000003 +#define SPI_DIN2_MODE_S 4 + +/* SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input + * without delayed, 1: input with the posedge of clk_apb,2 input with the + * negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF + * state. + */ + +#define SPI_DIN1_MODE 0x00000003 +#define SPI_DIN1_MODE_M (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S) +#define SPI_DIN1_MODE_V 0x00000003 +#define SPI_DIN1_MODE_S 2 + +/* SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: input + * without delayed, 1: input with the posedge of clk_apb,2 input with the + * negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF + * state. + */ + +#define SPI_DIN0_MODE 0x00000003 +#define SPI_DIN0_MODE_M (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S) +#define SPI_DIN0_MODE_V 0x00000003 +#define SPI_DIN0_MODE_S 0 + +/* SPI_DIN_NUM_REG register + * SPI input delay number configuration + */ + +#define SPI_DIN_NUM_REG (DR_REG_SPI2_BASE + 0x28) + +/* SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + */ + +#define SPI_DIN3_NUM 0x00000003 +#define SPI_DIN3_NUM_M (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S) +#define SPI_DIN3_NUM_V 0x00000003 +#define SPI_DIN3_NUM_S 6 + +/* SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + */ + +#define SPI_DIN2_NUM 0x00000003 +#define SPI_DIN2_NUM_M (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S) +#define SPI_DIN2_NUM_V 0x00000003 +#define SPI_DIN2_NUM_S 4 + +/* SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + */ + +#define SPI_DIN1_NUM 0x00000003 +#define SPI_DIN1_NUM_M (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S) +#define SPI_DIN1_NUM_V 0x00000003 +#define SPI_DIN1_NUM_S 2 + +/* SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; + * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 + * cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. + */ + +#define SPI_DIN0_NUM 0x00000003 +#define SPI_DIN0_NUM_M (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S) +#define SPI_DIN0_NUM_V 0x00000003 +#define SPI_DIN0_NUM_S 0 + +/* SPI_DOUT_MODE_REG register + * SPI output delay mode configuration + */ + +#define SPI_DOUT_MODE_REG (DR_REG_SPI2_BASE + 0x2c) + +/* SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output + * without delayed, 1: output delay for a SPI module clock cycle at its + * negative edge. Can be configured in CONF state. + */ + +#define SPI_DOUT3_MODE (BIT(3)) +#define SPI_DOUT3_MODE_M (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S) +#define SPI_DOUT3_MODE_V 0x00000001 +#define SPI_DOUT3_MODE_S 3 + +/* SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output + * without delayed, 1: output delay for a SPI module clock cycle at its + * negative edge. Can be configured in CONF state. + */ + +#define SPI_DOUT2_MODE (BIT(2)) +#define SPI_DOUT2_MODE_M (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S) +#define SPI_DOUT2_MODE_V 0x00000001 +#define SPI_DOUT2_MODE_S 2 + +/* SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output + * without delayed, 1: output delay for a SPI module clock cycle at its + * negative edge. Can be configured in CONF state. + */ + +#define SPI_DOUT1_MODE (BIT(1)) +#define SPI_DOUT1_MODE_M (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S) +#define SPI_DOUT1_MODE_V 0x00000001 +#define SPI_DOUT1_MODE_S 1 + +/* SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0; + * The output signal $n is delayed by the SPI module clock, 0: output + * without delayed, 1: output delay for a SPI module clock cycle at its + * negative edge. Can be configured in CONF state. + */ + +#define SPI_DOUT0_MODE (BIT(0)) +#define SPI_DOUT0_MODE_M (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S) +#define SPI_DOUT0_MODE_V 0x00000001 +#define SPI_DOUT0_MODE_S 0 + +/* SPI_DMA_CONF_REG register + * SPI DMA control register + */ + +#define SPI_DMA_CONF_REG (DR_REG_SPI2_BASE + 0x30) + +/* SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0; + * Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI + * slave DMA controlled mode transfer. + */ + +#define SPI_DMA_AFIFO_RST (BIT(31)) +#define SPI_DMA_AFIFO_RST_M (SPI_DMA_AFIFO_RST_V << SPI_DMA_AFIFO_RST_S) +#define SPI_DMA_AFIFO_RST_V 0x00000001 +#define SPI_DMA_AFIFO_RST_S 31 + +/* SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0; + * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI + * slave CPU controlled mode transfer and master mode transfer. + */ + +#define SPI_BUF_AFIFO_RST (BIT(30)) +#define SPI_BUF_AFIFO_RST_M (SPI_BUF_AFIFO_RST_V << SPI_BUF_AFIFO_RST_S) +#define SPI_BUF_AFIFO_RST_V 0x00000001 +#define SPI_BUF_AFIFO_RST_S 30 + +/* SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0; + * Set this bit to reset RX AFIFO, which is used to receive data in SPI + * master and slave mode transfer. + */ + +#define SPI_RX_AFIFO_RST (BIT(29)) +#define SPI_RX_AFIFO_RST_M (SPI_RX_AFIFO_RST_V << SPI_RX_AFIFO_RST_S) +#define SPI_RX_AFIFO_RST_V 0x00000001 +#define SPI_RX_AFIFO_RST_S 29 + +/* SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0; + * Set this bit to enable SPI DMA controlled send data mode. + */ + +#define SPI_DMA_TX_ENA (BIT(28)) +#define SPI_DMA_TX_ENA_M (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S) +#define SPI_DMA_TX_ENA_V 0x00000001 +#define SPI_DMA_TX_ENA_S 28 + +/* SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0; + * Set this bit to enable SPI DMA controlled receive data mode. + */ + +#define SPI_DMA_RX_ENA (BIT(27)) +#define SPI_DMA_RX_ENA_M (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S) +#define SPI_DMA_RX_ENA_V 0x00000001 +#define SPI_DMA_RX_ENA_S 27 + +/* SPI_RX_EOF_EN : R/W; bitpos: [21]; default: 0; + * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is + * equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma + * transition. 0: spi_dma_inlink_eof is set by spi_trans_done in + * non-seg-trans or spi_dma_seg_trans_done in seg-trans. + */ + +#define SPI_RX_EOF_EN (BIT(21)) +#define SPI_RX_EOF_EN_M (SPI_RX_EOF_EN_V << SPI_RX_EOF_EN_S) +#define SPI_RX_EOF_EN_V 0x00000001 +#define SPI_RX_EOF_EN_S 21 + +/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0; + * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. + */ + +#define SPI_SLV_TX_SEG_TRANS_CLR_EN (BIT(20)) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V 0x00000001 +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S 20 + +/* SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0; + * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + * spi_dma_infifo_full_vld is cleared by spi_trans_done. + */ + +#define SPI_SLV_RX_SEG_TRANS_CLR_EN (BIT(19)) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V 0x00000001 +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 + +/* SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0; + * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: + * disable. + */ + +#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) +#define SPI_DMA_SLV_SEG_TRANS_EN_M (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S) +#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x00000001 +#define SPI_DMA_SLV_SEG_TRANS_EN_S 18 + +/* SPI_DMA_INT_ENA_REG register + * SPI DMA interrupt enable register + */ + +#define SPI_DMA_INT_ENA_REG (DR_REG_SPI2_BASE + 0x34) + +/* SPI_APP1_INT_ENA : R/W; bitpos: [20]; default: 0; + * The enable bit for SPI_APP1_INT interrupt. + */ + +#define SPI_APP1_INT_ENA (BIT(20)) +#define SPI_APP1_INT_ENA_M (SPI_APP1_INT_ENA_V << SPI_APP1_INT_ENA_S) +#define SPI_APP1_INT_ENA_V 0x00000001 +#define SPI_APP1_INT_ENA_S 20 + +/* SPI_APP2_INT_ENA : R/W; bitpos: [19]; default: 0; + * The enable bit for SPI_APP2_INT interrupt. + */ + +#define SPI_APP2_INT_ENA (BIT(19)) +#define SPI_APP2_INT_ENA_M (SPI_APP2_INT_ENA_V << SPI_APP2_INT_ENA_S) +#define SPI_APP2_INT_ENA_V 0x00000001 +#define SPI_APP2_INT_ENA_S 19 + +/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0; + * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V 0x00000001 +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S 18 + +/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0; + * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V 0x00000001 +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S 17 + +/* SPI_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; + * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + +#define SPI_SLV_CMD_ERR_INT_ENA (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ENA_M (SPI_SLV_CMD_ERR_INT_ENA_V << SPI_SLV_CMD_ERR_INT_ENA_S) +#define SPI_SLV_CMD_ERR_INT_ENA_V 0x00000001 +#define SPI_SLV_CMD_ERR_INT_ENA_S 16 + +/* SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; + * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M (SPI_SLV_BUF_ADDR_ERR_INT_ENA_V << SPI_SLV_BUF_ADDR_ERR_INT_ENA_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V 0x00000001 +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S 15 + +/* SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0; + * The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + +#define SPI_SEG_MAGIC_ERR_INT_ENA (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ENA_M (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S) +#define SPI_SEG_MAGIC_ERR_INT_ENA_V 0x00000001 +#define SPI_SEG_MAGIC_ERR_INT_ENA_S 14 + +/* SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; + * The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M (SPI_DMA_SEG_TRANS_DONE_INT_ENA_V << SPI_DMA_SEG_TRANS_DONE_INT_ENA_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V 0x00000001 +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S 13 + +/* SPI_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; + * The enable bit for SPI_TRANS_DONE_INT interrupt. + */ + +#define SPI_TRANS_DONE_INT_ENA (BIT(12)) +#define SPI_TRANS_DONE_INT_ENA_M (SPI_TRANS_DONE_INT_ENA_V << SPI_TRANS_DONE_INT_ENA_S) +#define SPI_TRANS_DONE_INT_ENA_V 0x00000001 +#define SPI_TRANS_DONE_INT_ENA_S 12 + +/* SPI_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0; + * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + +#define SPI_SLV_WR_BUF_DONE_INT_ENA (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_M (SPI_SLV_WR_BUF_DONE_INT_ENA_V << SPI_SLV_WR_BUF_DONE_INT_ENA_S) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_V 0x00000001 +#define SPI_SLV_WR_BUF_DONE_INT_ENA_S 11 + +/* SPI_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0; + * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + +#define SPI_SLV_RD_BUF_DONE_INT_ENA (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_M (SPI_SLV_RD_BUF_DONE_INT_ENA_V << SPI_SLV_RD_BUF_DONE_INT_ENA_S) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_V 0x00000001 +#define SPI_SLV_RD_BUF_DONE_INT_ENA_S 10 + +/* SPI_SLV_WR_DMA_DONE_INT_ENA : R/W; bitpos: [9]; default: 0; + * The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + +#define SPI_SLV_WR_DMA_DONE_INT_ENA (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_M (SPI_SLV_WR_DMA_DONE_INT_ENA_V << SPI_SLV_WR_DMA_DONE_INT_ENA_S) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_V 0x00000001 +#define SPI_SLV_WR_DMA_DONE_INT_ENA_S 9 + +/* SPI_SLV_RD_DMA_DONE_INT_ENA : R/W; bitpos: [8]; default: 0; + * The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + +#define SPI_SLV_RD_DMA_DONE_INT_ENA (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_M (SPI_SLV_RD_DMA_DONE_INT_ENA_V << SPI_SLV_RD_DMA_DONE_INT_ENA_S) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_V 0x00000001 +#define SPI_SLV_RD_DMA_DONE_INT_ENA_S 8 + +/* SPI_SLV_CMDA_INT_ENA : R/W; bitpos: [7]; default: 0; + * The enable bit for SPI slave CMDA interrupt. + */ + +#define SPI_SLV_CMDA_INT_ENA (BIT(7)) +#define SPI_SLV_CMDA_INT_ENA_M (SPI_SLV_CMDA_INT_ENA_V << SPI_SLV_CMDA_INT_ENA_S) +#define SPI_SLV_CMDA_INT_ENA_V 0x00000001 +#define SPI_SLV_CMDA_INT_ENA_S 7 + +/* SPI_SLV_CMD9_INT_ENA : R/W; bitpos: [6]; default: 0; + * The enable bit for SPI slave CMD9 interrupt. + */ + +#define SPI_SLV_CMD9_INT_ENA (BIT(6)) +#define SPI_SLV_CMD9_INT_ENA_M (SPI_SLV_CMD9_INT_ENA_V << SPI_SLV_CMD9_INT_ENA_S) +#define SPI_SLV_CMD9_INT_ENA_V 0x00000001 +#define SPI_SLV_CMD9_INT_ENA_S 6 + +/* SPI_SLV_CMD8_INT_ENA : R/W; bitpos: [5]; default: 0; + * The enable bit for SPI slave CMD8 interrupt. + */ + +#define SPI_SLV_CMD8_INT_ENA (BIT(5)) +#define SPI_SLV_CMD8_INT_ENA_M (SPI_SLV_CMD8_INT_ENA_V << SPI_SLV_CMD8_INT_ENA_S) +#define SPI_SLV_CMD8_INT_ENA_V 0x00000001 +#define SPI_SLV_CMD8_INT_ENA_S 5 + +/* SPI_SLV_CMD7_INT_ENA : R/W; bitpos: [4]; default: 0; + * The enable bit for SPI slave CMD7 interrupt. + */ + +#define SPI_SLV_CMD7_INT_ENA (BIT(4)) +#define SPI_SLV_CMD7_INT_ENA_M (SPI_SLV_CMD7_INT_ENA_V << SPI_SLV_CMD7_INT_ENA_S) +#define SPI_SLV_CMD7_INT_ENA_V 0x00000001 +#define SPI_SLV_CMD7_INT_ENA_S 4 + +/* SPI_SLV_EN_QPI_INT_ENA : R/W; bitpos: [3]; default: 0; + * The enable bit for SPI slave En_QPI interrupt. + */ + +#define SPI_SLV_EN_QPI_INT_ENA (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ENA_M (SPI_SLV_EN_QPI_INT_ENA_V << SPI_SLV_EN_QPI_INT_ENA_S) +#define SPI_SLV_EN_QPI_INT_ENA_V 0x00000001 +#define SPI_SLV_EN_QPI_INT_ENA_S 3 + +/* SPI_SLV_EX_QPI_INT_ENA : R/W; bitpos: [2]; default: 0; + * The enable bit for SPI slave Ex_QPI interrupt. + */ + +#define SPI_SLV_EX_QPI_INT_ENA (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ENA_M (SPI_SLV_EX_QPI_INT_ENA_V << SPI_SLV_EX_QPI_INT_ENA_S) +#define SPI_SLV_EX_QPI_INT_ENA_V 0x00000001 +#define SPI_SLV_EX_QPI_INT_ENA_S 2 + +/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W; bitpos: [1]; default: 0; + * The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V 0x00000001 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S 1 + +/* SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0; + * The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M (SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V << SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V 0x00000001 +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S 0 + +/* SPI_DMA_INT_CLR_REG register + * SPI DMA interrupt clear register + */ + +#define SPI_DMA_INT_CLR_REG (DR_REG_SPI2_BASE + 0x38) + +/* SPI_APP1_INT_CLR : WT; bitpos: [20]; default: 0; + * The clear bit for SPI_APP1_INT interrupt. + */ + +#define SPI_APP1_INT_CLR (BIT(20)) +#define SPI_APP1_INT_CLR_M (SPI_APP1_INT_CLR_V << SPI_APP1_INT_CLR_S) +#define SPI_APP1_INT_CLR_V 0x00000001 +#define SPI_APP1_INT_CLR_S 20 + +/* SPI_APP2_INT_CLR : WT; bitpos: [19]; default: 0; + * The clear bit for SPI_APP2_INT interrupt. + */ + +#define SPI_APP2_INT_CLR (BIT(19)) +#define SPI_APP2_INT_CLR_M (SPI_APP2_INT_CLR_V << SPI_APP2_INT_CLR_S) +#define SPI_APP2_INT_CLR_V 0x00000001 +#define SPI_APP2_INT_CLR_S 19 + +/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0; + * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V 0x00000001 +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S 18 + +/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0; + * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V 0x00000001 +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S 17 + +/* SPI_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0; + * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + +#define SPI_SLV_CMD_ERR_INT_CLR (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_CLR_M (SPI_SLV_CMD_ERR_INT_CLR_V << SPI_SLV_CMD_ERR_INT_CLR_S) +#define SPI_SLV_CMD_ERR_INT_CLR_V 0x00000001 +#define SPI_SLV_CMD_ERR_INT_CLR_S 16 + +/* SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0; + * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M (SPI_SLV_BUF_ADDR_ERR_INT_CLR_V << SPI_SLV_BUF_ADDR_ERR_INT_CLR_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V 0x00000001 +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S 15 + +/* SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0; + * The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + +#define SPI_SEG_MAGIC_ERR_INT_CLR (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_CLR_M (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S) +#define SPI_SEG_MAGIC_ERR_INT_CLR_V 0x00000001 +#define SPI_SEG_MAGIC_ERR_INT_CLR_S 14 + +/* SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT; bitpos: [13]; default: 0; + * The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M (SPI_DMA_SEG_TRANS_DONE_INT_CLR_V << SPI_DMA_SEG_TRANS_DONE_INT_CLR_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V 0x00000001 +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S 13 + +/* SPI_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0; + * The clear bit for SPI_TRANS_DONE_INT interrupt. + */ + +#define SPI_TRANS_DONE_INT_CLR (BIT(12)) +#define SPI_TRANS_DONE_INT_CLR_M (SPI_TRANS_DONE_INT_CLR_V << SPI_TRANS_DONE_INT_CLR_S) +#define SPI_TRANS_DONE_INT_CLR_V 0x00000001 +#define SPI_TRANS_DONE_INT_CLR_S 12 + +/* SPI_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0; + * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + +#define SPI_SLV_WR_BUF_DONE_INT_CLR (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_M (SPI_SLV_WR_BUF_DONE_INT_CLR_V << SPI_SLV_WR_BUF_DONE_INT_CLR_S) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_V 0x00000001 +#define SPI_SLV_WR_BUF_DONE_INT_CLR_S 11 + +/* SPI_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0; + * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + +#define SPI_SLV_RD_BUF_DONE_INT_CLR (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_M (SPI_SLV_RD_BUF_DONE_INT_CLR_V << SPI_SLV_RD_BUF_DONE_INT_CLR_S) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_V 0x00000001 +#define SPI_SLV_RD_BUF_DONE_INT_CLR_S 10 + +/* SPI_SLV_WR_DMA_DONE_INT_CLR : WT; bitpos: [9]; default: 0; + * The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + +#define SPI_SLV_WR_DMA_DONE_INT_CLR (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_M (SPI_SLV_WR_DMA_DONE_INT_CLR_V << SPI_SLV_WR_DMA_DONE_INT_CLR_S) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_V 0x00000001 +#define SPI_SLV_WR_DMA_DONE_INT_CLR_S 9 + +/* SPI_SLV_RD_DMA_DONE_INT_CLR : WT; bitpos: [8]; default: 0; + * The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + +#define SPI_SLV_RD_DMA_DONE_INT_CLR (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_M (SPI_SLV_RD_DMA_DONE_INT_CLR_V << SPI_SLV_RD_DMA_DONE_INT_CLR_S) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_V 0x00000001 +#define SPI_SLV_RD_DMA_DONE_INT_CLR_S 8 + +/* SPI_SLV_CMDA_INT_CLR : WT; bitpos: [7]; default: 0; + * The clear bit for SPI slave CMDA interrupt. + */ + +#define SPI_SLV_CMDA_INT_CLR (BIT(7)) +#define SPI_SLV_CMDA_INT_CLR_M (SPI_SLV_CMDA_INT_CLR_V << SPI_SLV_CMDA_INT_CLR_S) +#define SPI_SLV_CMDA_INT_CLR_V 0x00000001 +#define SPI_SLV_CMDA_INT_CLR_S 7 + +/* SPI_SLV_CMD9_INT_CLR : WT; bitpos: [6]; default: 0; + * The clear bit for SPI slave CMD9 interrupt. + */ + +#define SPI_SLV_CMD9_INT_CLR (BIT(6)) +#define SPI_SLV_CMD9_INT_CLR_M (SPI_SLV_CMD9_INT_CLR_V << SPI_SLV_CMD9_INT_CLR_S) +#define SPI_SLV_CMD9_INT_CLR_V 0x00000001 +#define SPI_SLV_CMD9_INT_CLR_S 6 + +/* SPI_SLV_CMD8_INT_CLR : WT; bitpos: [5]; default: 0; + * The clear bit for SPI slave CMD8 interrupt. + */ + +#define SPI_SLV_CMD8_INT_CLR (BIT(5)) +#define SPI_SLV_CMD8_INT_CLR_M (SPI_SLV_CMD8_INT_CLR_V << SPI_SLV_CMD8_INT_CLR_S) +#define SPI_SLV_CMD8_INT_CLR_V 0x00000001 +#define SPI_SLV_CMD8_INT_CLR_S 5 + +/* SPI_SLV_CMD7_INT_CLR : WT; bitpos: [4]; default: 0; + * The clear bit for SPI slave CMD7 interrupt. + */ + +#define SPI_SLV_CMD7_INT_CLR (BIT(4)) +#define SPI_SLV_CMD7_INT_CLR_M (SPI_SLV_CMD7_INT_CLR_V << SPI_SLV_CMD7_INT_CLR_S) +#define SPI_SLV_CMD7_INT_CLR_V 0x00000001 +#define SPI_SLV_CMD7_INT_CLR_S 4 + +/* SPI_SLV_EN_QPI_INT_CLR : WT; bitpos: [3]; default: 0; + * The clear bit for SPI slave En_QPI interrupt. + */ + +#define SPI_SLV_EN_QPI_INT_CLR (BIT(3)) +#define SPI_SLV_EN_QPI_INT_CLR_M (SPI_SLV_EN_QPI_INT_CLR_V << SPI_SLV_EN_QPI_INT_CLR_S) +#define SPI_SLV_EN_QPI_INT_CLR_V 0x00000001 +#define SPI_SLV_EN_QPI_INT_CLR_S 3 + +/* SPI_SLV_EX_QPI_INT_CLR : WT; bitpos: [2]; default: 0; + * The clear bit for SPI slave Ex_QPI interrupt. + */ + +#define SPI_SLV_EX_QPI_INT_CLR (BIT(2)) +#define SPI_SLV_EX_QPI_INT_CLR_M (SPI_SLV_EX_QPI_INT_CLR_V << SPI_SLV_EX_QPI_INT_CLR_S) +#define SPI_SLV_EX_QPI_INT_CLR_V 0x00000001 +#define SPI_SLV_EX_QPI_INT_CLR_S 2 + +/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT; bitpos: [1]; default: 0; + * The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V 0x00000001 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S 1 + +/* SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0; + * The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M (SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V << SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V 0x00000001 +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S 0 + +/* SPI_DMA_INT_RAW_REG register + * SPI DMA interrupt raw register + */ + +#define SPI_DMA_INT_RAW_REG (DR_REG_SPI2_BASE + 0x3c) + +/* SPI_APP1_INT_RAW : R/W/WTC; bitpos: [20]; default: 0; + * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by + * application. + */ + +#define SPI_APP1_INT_RAW (BIT(20)) +#define SPI_APP1_INT_RAW_M (SPI_APP1_INT_RAW_V << SPI_APP1_INT_RAW_S) +#define SPI_APP1_INT_RAW_V 0x00000001 +#define SPI_APP1_INT_RAW_S 20 + +/* SPI_APP2_INT_RAW : R/W/WTC; bitpos: [19]; default: 0; + * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by + * application. + */ + +#define SPI_APP2_INT_RAW (BIT(19)) +#define SPI_APP2_INT_RAW_M (SPI_APP2_INT_RAW_V << SPI_APP2_INT_RAW_S) +#define SPI_APP2_INT_RAW_V 0x00000001 +#define SPI_APP2_INT_RAW_S 19 + +/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/W/WTC/SS; bitpos: [18]; default: + * 0; + * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a + * TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: + * Others. + */ + +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V 0x00000001 +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S 18 + +/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/W/WTC/SS; bitpos: [17]; default: 0; + * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a + * RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. + */ + +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V 0x00000001 +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S 17 + +/* SPI_SLV_CMD_ERR_INT_RAW : R/W/WTC/SS; bitpos: [16]; default: 0; + * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value + * in the current SPI slave HD mode transmission is not supported. 0: Others. + */ + +#define SPI_SLV_CMD_ERR_INT_RAW (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_RAW_M (SPI_SLV_CMD_ERR_INT_RAW_V << SPI_SLV_CMD_ERR_INT_RAW_S) +#define SPI_SLV_CMD_ERR_INT_RAW_V 0x00000001 +#define SPI_SLV_CMD_ERR_INT_RAW_S 16 + +/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/W/WTC/SS; bitpos: [15]; default: 0; + * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data + * address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF + * transmission is bigger than 63. 0: Others. + */ + +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M (SPI_SLV_BUF_ADDR_ERR_INT_RAW_V << SPI_SLV_BUF_ADDR_ERR_INT_RAW_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V 0x00000001 +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S 15 + +/* SPI_SEG_MAGIC_ERR_INT_RAW : R/W/WTC/SS; bitpos: [14]; default: 0; + * The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in + * CONF buffer is error in the DMA seg-conf-trans. 0: others. + */ + +#define SPI_SEG_MAGIC_ERR_INT_RAW (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_RAW_M (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S) +#define SPI_SEG_MAGIC_ERR_INT_RAW_V 0x00000001 +#define SPI_SEG_MAGIC_ERR_INT_RAW_S 14 + +/* SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/W/WTC/SS; bitpos: [13]; default: 0; + * The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA + * full-duplex/half-duplex seg-conf-trans ends or slave half-duplex + * seg-trans ends. And data has been pushed to corresponding memory. 0: + * seg-conf-trans or seg-trans is not ended or not occurred. + */ + +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M (SPI_DMA_SEG_TRANS_DONE_INT_RAW_V << SPI_DMA_SEG_TRANS_DONE_INT_RAW_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V 0x00000001 +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S 13 + +/* SPI_TRANS_DONE_INT_RAW : R/W/WTC/SS; bitpos: [12]; default: 0; + * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode + * transmission is ended. 0: others. + */ + +#define SPI_TRANS_DONE_INT_RAW (BIT(12)) +#define SPI_TRANS_DONE_INT_RAW_M (SPI_TRANS_DONE_INT_RAW_V << SPI_TRANS_DONE_INT_RAW_S) +#define SPI_TRANS_DONE_INT_RAW_V 0x00000001 +#define SPI_TRANS_DONE_INT_RAW_S 12 + +/* SPI_SLV_WR_BUF_DONE_INT_RAW : R/W/WTC/SS; bitpos: [11]; default: 0; + * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode + * Wr_BUF transmission is ended. 0: Others. + */ + +#define SPI_SLV_WR_BUF_DONE_INT_RAW (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_M (SPI_SLV_WR_BUF_DONE_INT_RAW_V << SPI_SLV_WR_BUF_DONE_INT_RAW_S) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_V 0x00000001 +#define SPI_SLV_WR_BUF_DONE_INT_RAW_S 11 + +/* SPI_SLV_RD_BUF_DONE_INT_RAW : R/W/WTC/SS; bitpos: [10]; default: 0; + * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode + * Rd_BUF transmission is ended. 0: Others. + */ + +#define SPI_SLV_RD_BUF_DONE_INT_RAW (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_M (SPI_SLV_RD_BUF_DONE_INT_RAW_V << SPI_SLV_RD_BUF_DONE_INT_RAW_S) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_V 0x00000001 +#define SPI_SLV_RD_BUF_DONE_INT_RAW_S 10 + +/* SPI_SLV_WR_DMA_DONE_INT_RAW : R/W/WTC/SS; bitpos: [9]; default: 0; + * The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode + * Wr_DMA transmission is ended. 0: Others. + */ + +#define SPI_SLV_WR_DMA_DONE_INT_RAW (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_M (SPI_SLV_WR_DMA_DONE_INT_RAW_V << SPI_SLV_WR_DMA_DONE_INT_RAW_S) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_V 0x00000001 +#define SPI_SLV_WR_DMA_DONE_INT_RAW_S 9 + +/* SPI_SLV_RD_DMA_DONE_INT_RAW : R/W/WTC/SS; bitpos: [8]; default: 0; + * The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode + * Rd_DMA transmission is ended. 0: Others. + */ + +#define SPI_SLV_RD_DMA_DONE_INT_RAW (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_M (SPI_SLV_RD_DMA_DONE_INT_RAW_V << SPI_SLV_RD_DMA_DONE_INT_RAW_S) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_V 0x00000001 +#define SPI_SLV_RD_DMA_DONE_INT_RAW_S 8 + +/* SPI_SLV_CMDA_INT_RAW : R/W/WTC/SS; bitpos: [7]; default: 0; + * The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA + * transmission is ended. 0: Others. + */ + +#define SPI_SLV_CMDA_INT_RAW (BIT(7)) +#define SPI_SLV_CMDA_INT_RAW_M (SPI_SLV_CMDA_INT_RAW_V << SPI_SLV_CMDA_INT_RAW_S) +#define SPI_SLV_CMDA_INT_RAW_V 0x00000001 +#define SPI_SLV_CMDA_INT_RAW_S 7 + +/* SPI_SLV_CMD9_INT_RAW : R/W/WTC/SS; bitpos: [6]; default: 0; + * The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 + * transmission is ended. 0: Others. + */ + +#define SPI_SLV_CMD9_INT_RAW (BIT(6)) +#define SPI_SLV_CMD9_INT_RAW_M (SPI_SLV_CMD9_INT_RAW_V << SPI_SLV_CMD9_INT_RAW_S) +#define SPI_SLV_CMD9_INT_RAW_V 0x00000001 +#define SPI_SLV_CMD9_INT_RAW_S 6 + +/* SPI_SLV_CMD8_INT_RAW : R/W/WTC/SS; bitpos: [5]; default: 0; + * The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 + * transmission is ended. 0: Others. + */ + +#define SPI_SLV_CMD8_INT_RAW (BIT(5)) +#define SPI_SLV_CMD8_INT_RAW_M (SPI_SLV_CMD8_INT_RAW_V << SPI_SLV_CMD8_INT_RAW_S) +#define SPI_SLV_CMD8_INT_RAW_V 0x00000001 +#define SPI_SLV_CMD8_INT_RAW_S 5 + +/* SPI_SLV_CMD7_INT_RAW : R/W/WTC/SS; bitpos: [4]; default: 0; + * The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 + * transmission is ended. 0: Others. + */ + +#define SPI_SLV_CMD7_INT_RAW (BIT(4)) +#define SPI_SLV_CMD7_INT_RAW_M (SPI_SLV_CMD7_INT_RAW_V << SPI_SLV_CMD7_INT_RAW_S) +#define SPI_SLV_CMD7_INT_RAW_V 0x00000001 +#define SPI_SLV_CMD7_INT_RAW_S 4 + +/* SPI_SLV_EN_QPI_INT_RAW : R/W/WTC/SS; bitpos: [3]; default: 0; + * The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI + * transmission is ended. 0: Others. + */ + +#define SPI_SLV_EN_QPI_INT_RAW (BIT(3)) +#define SPI_SLV_EN_QPI_INT_RAW_M (SPI_SLV_EN_QPI_INT_RAW_V << SPI_SLV_EN_QPI_INT_RAW_S) +#define SPI_SLV_EN_QPI_INT_RAW_V 0x00000001 +#define SPI_SLV_EN_QPI_INT_RAW_S 3 + +/* SPI_SLV_EX_QPI_INT_RAW : R/W/WTC/SS; bitpos: [2]; default: 0; + * The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI + * transmission is ended. 0: Others. + */ + +#define SPI_SLV_EX_QPI_INT_RAW (BIT(2)) +#define SPI_SLV_EX_QPI_INT_RAW_M (SPI_SLV_EX_QPI_INT_RAW_V << SPI_SLV_EX_QPI_INT_RAW_S) +#define SPI_SLV_EX_QPI_INT_RAW_V 0x00000001 +#define SPI_SLV_EX_QPI_INT_RAW_S 2 + +/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/W/WTC/SS; bitpos: [1]; default: 0; + * 1: The current data rate of DMA TX is smaller than that of SPI. SPI will + * stop in master mode and send out all 0 in slave mode. 0: Others. + */ + +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V 0x00000001 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S 1 + +/* SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/W/WTC/SS; bitpos: [0]; default: 0; + * 1: The current data rate of DMA Rx is smaller than that of SPI, which + * will lose the receive data. 0: Others. + */ + +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M (SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V << SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V 0x00000001 +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S 0 + +/* SPI_DMA_INT_ST_REG register + * SPI DMA interrupt status register + */ + +#define SPI_DMA_INT_ST_REG (DR_REG_SPI2_BASE + 0x40) + +/* SPI_APP1_INT_ST : RO; bitpos: [20]; default: 0; + * The status bit for SPI_APP1_INT interrupt. + */ + +#define SPI_APP1_INT_ST (BIT(20)) +#define SPI_APP1_INT_ST_M (SPI_APP1_INT_ST_V << SPI_APP1_INT_ST_S) +#define SPI_APP1_INT_ST_V 0x00000001 +#define SPI_APP1_INT_ST_S 20 + +/* SPI_APP2_INT_ST : RO; bitpos: [19]; default: 0; + * The status bit for SPI_APP2_INT interrupt. + */ + +#define SPI_APP2_INT_ST (BIT(19)) +#define SPI_APP2_INT_ST_M (SPI_APP2_INT_ST_V << SPI_APP2_INT_ST_S) +#define SPI_APP2_INT_ST_V 0x00000001 +#define SPI_APP2_INT_ST_S 19 + +/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0; + * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. + */ + +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST (BIT(18)) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S) +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V 0x00000001 +#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S 18 + +/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0; + * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. + */ + +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST (BIT(17)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V 0x00000001 +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S 17 + +/* SPI_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0; + * The status bit for SPI_SLV_CMD_ERR_INT interrupt. + */ + +#define SPI_SLV_CMD_ERR_INT_ST (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ST_M (SPI_SLV_CMD_ERR_INT_ST_V << SPI_SLV_CMD_ERR_INT_ST_S) +#define SPI_SLV_CMD_ERR_INT_ST_V 0x00000001 +#define SPI_SLV_CMD_ERR_INT_ST_S 16 + +/* SPI_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0; + * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. + */ + +#define SPI_SLV_BUF_ADDR_ERR_INT_ST (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M (SPI_SLV_BUF_ADDR_ERR_INT_ST_V << SPI_SLV_BUF_ADDR_ERR_INT_ST_S) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V 0x00000001 +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S 15 + +/* SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0; + * The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. + */ + +#define SPI_SEG_MAGIC_ERR_INT_ST (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ST_M (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S) +#define SPI_SEG_MAGIC_ERR_INT_ST_V 0x00000001 +#define SPI_SEG_MAGIC_ERR_INT_ST_S 14 + +/* SPI_DMA_SEG_TRANS_DONE_INT_ST : RO; bitpos: [13]; default: 0; + * The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. + */ + +#define SPI_DMA_SEG_TRANS_DONE_INT_ST (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M (SPI_DMA_SEG_TRANS_DONE_INT_ST_V << SPI_DMA_SEG_TRANS_DONE_INT_ST_S) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V 0x00000001 +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S 13 + +/* SPI_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0; + * The status bit for SPI_TRANS_DONE_INT interrupt. + */ + +#define SPI_TRANS_DONE_INT_ST (BIT(12)) +#define SPI_TRANS_DONE_INT_ST_M (SPI_TRANS_DONE_INT_ST_V << SPI_TRANS_DONE_INT_ST_S) +#define SPI_TRANS_DONE_INT_ST_V 0x00000001 +#define SPI_TRANS_DONE_INT_ST_S 12 + +/* SPI_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0; + * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. + */ + +#define SPI_SLV_WR_BUF_DONE_INT_ST (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ST_M (SPI_SLV_WR_BUF_DONE_INT_ST_V << SPI_SLV_WR_BUF_DONE_INT_ST_S) +#define SPI_SLV_WR_BUF_DONE_INT_ST_V 0x00000001 +#define SPI_SLV_WR_BUF_DONE_INT_ST_S 11 + +/* SPI_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0; + * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. + */ + +#define SPI_SLV_RD_BUF_DONE_INT_ST (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ST_M (SPI_SLV_RD_BUF_DONE_INT_ST_V << SPI_SLV_RD_BUF_DONE_INT_ST_S) +#define SPI_SLV_RD_BUF_DONE_INT_ST_V 0x00000001 +#define SPI_SLV_RD_BUF_DONE_INT_ST_S 10 + +/* SPI_SLV_WR_DMA_DONE_INT_ST : RO; bitpos: [9]; default: 0; + * The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. + */ + +#define SPI_SLV_WR_DMA_DONE_INT_ST (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ST_M (SPI_SLV_WR_DMA_DONE_INT_ST_V << SPI_SLV_WR_DMA_DONE_INT_ST_S) +#define SPI_SLV_WR_DMA_DONE_INT_ST_V 0x00000001 +#define SPI_SLV_WR_DMA_DONE_INT_ST_S 9 + +/* SPI_SLV_RD_DMA_DONE_INT_ST : RO; bitpos: [8]; default: 0; + * The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. + */ + +#define SPI_SLV_RD_DMA_DONE_INT_ST (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ST_M (SPI_SLV_RD_DMA_DONE_INT_ST_V << SPI_SLV_RD_DMA_DONE_INT_ST_S) +#define SPI_SLV_RD_DMA_DONE_INT_ST_V 0x00000001 +#define SPI_SLV_RD_DMA_DONE_INT_ST_S 8 + +/* SPI_SLV_CMDA_INT_ST : RO; bitpos: [7]; default: 0; + * The status bit for SPI slave CMDA interrupt. + */ + +#define SPI_SLV_CMDA_INT_ST (BIT(7)) +#define SPI_SLV_CMDA_INT_ST_M (SPI_SLV_CMDA_INT_ST_V << SPI_SLV_CMDA_INT_ST_S) +#define SPI_SLV_CMDA_INT_ST_V 0x00000001 +#define SPI_SLV_CMDA_INT_ST_S 7 + +/* SPI_SLV_CMD9_INT_ST : RO; bitpos: [6]; default: 0; + * The status bit for SPI slave CMD9 interrupt. + */ + +#define SPI_SLV_CMD9_INT_ST (BIT(6)) +#define SPI_SLV_CMD9_INT_ST_M (SPI_SLV_CMD9_INT_ST_V << SPI_SLV_CMD9_INT_ST_S) +#define SPI_SLV_CMD9_INT_ST_V 0x00000001 +#define SPI_SLV_CMD9_INT_ST_S 6 + +/* SPI_SLV_CMD8_INT_ST : RO; bitpos: [5]; default: 0; + * The status bit for SPI slave CMD8 interrupt. + */ + +#define SPI_SLV_CMD8_INT_ST (BIT(5)) +#define SPI_SLV_CMD8_INT_ST_M (SPI_SLV_CMD8_INT_ST_V << SPI_SLV_CMD8_INT_ST_S) +#define SPI_SLV_CMD8_INT_ST_V 0x00000001 +#define SPI_SLV_CMD8_INT_ST_S 5 + +/* SPI_SLV_CMD7_INT_ST : RO; bitpos: [4]; default: 0; + * The status bit for SPI slave CMD7 interrupt. + */ + +#define SPI_SLV_CMD7_INT_ST (BIT(4)) +#define SPI_SLV_CMD7_INT_ST_M (SPI_SLV_CMD7_INT_ST_V << SPI_SLV_CMD7_INT_ST_S) +#define SPI_SLV_CMD7_INT_ST_V 0x00000001 +#define SPI_SLV_CMD7_INT_ST_S 4 + +/* SPI_SLV_EN_QPI_INT_ST : RO; bitpos: [3]; default: 0; + * The status bit for SPI slave En_QPI interrupt. + */ + +#define SPI_SLV_EN_QPI_INT_ST (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ST_M (SPI_SLV_EN_QPI_INT_ST_V << SPI_SLV_EN_QPI_INT_ST_S) +#define SPI_SLV_EN_QPI_INT_ST_V 0x00000001 +#define SPI_SLV_EN_QPI_INT_ST_S 3 + +/* SPI_SLV_EX_QPI_INT_ST : RO; bitpos: [2]; default: 0; + * The status bit for SPI slave Ex_QPI interrupt. + */ + +#define SPI_SLV_EX_QPI_INT_ST (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ST_M (SPI_SLV_EX_QPI_INT_ST_V << SPI_SLV_EX_QPI_INT_ST_S) +#define SPI_SLV_EX_QPI_INT_ST_V 0x00000001 +#define SPI_SLV_EX_QPI_INT_ST_S 2 + +/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO; bitpos: [1]; default: 0; + * The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. + */ + +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V 0x00000001 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S 1 + +/* SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0; + * The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. + */ + +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M (SPI_DMA_INFIFO_FULL_ERR_INT_ST_V << SPI_DMA_INFIFO_FULL_ERR_INT_ST_S) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V 0x00000001 +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S 0 + +/* SPI_W0_REG register + * SPI CPU-controlled buffer0 + */ + +#define SPI_W0_REG (DR_REG_SPI2_BASE + 0x98) + +/* SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF0 0xFFFFFFFF +#define SPI_BUF0_M (SPI_BUF0_V << SPI_BUF0_S) +#define SPI_BUF0_V 0xFFFFFFFF +#define SPI_BUF0_S 0 + +/* SPI_W1_REG register + * SPI CPU-controlled buffer1 + */ + +#define SPI_W1_REG (DR_REG_SPI2_BASE + 0x9c) + +/* SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF1 0xFFFFFFFF +#define SPI_BUF1_M (SPI_BUF1_V << SPI_BUF1_S) +#define SPI_BUF1_V 0xFFFFFFFF +#define SPI_BUF1_S 0 + +/* SPI_W2_REG register + * SPI CPU-controlled buffer2 + */ + +#define SPI_W2_REG (DR_REG_SPI2_BASE + 0xa0) + +/* SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF2 0xFFFFFFFF +#define SPI_BUF2_M (SPI_BUF2_V << SPI_BUF2_S) +#define SPI_BUF2_V 0xFFFFFFFF +#define SPI_BUF2_S 0 + +/* SPI_W3_REG register + * SPI CPU-controlled buffer3 + */ + +#define SPI_W3_REG (DR_REG_SPI2_BASE + 0xa4) + +/* SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF3 0xFFFFFFFF +#define SPI_BUF3_M (SPI_BUF3_V << SPI_BUF3_S) +#define SPI_BUF3_V 0xFFFFFFFF +#define SPI_BUF3_S 0 + +/* SPI_W4_REG register + * SPI CPU-controlled buffer4 + */ + +#define SPI_W4_REG (DR_REG_SPI2_BASE + 0xa8) + +/* SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF4 0xFFFFFFFF +#define SPI_BUF4_M (SPI_BUF4_V << SPI_BUF4_S) +#define SPI_BUF4_V 0xFFFFFFFF +#define SPI_BUF4_S 0 + +/* SPI_W5_REG register + * SPI CPU-controlled buffer5 + */ + +#define SPI_W5_REG (DR_REG_SPI2_BASE + 0xac) + +/* SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF5 0xFFFFFFFF +#define SPI_BUF5_M (SPI_BUF5_V << SPI_BUF5_S) +#define SPI_BUF5_V 0xFFFFFFFF +#define SPI_BUF5_S 0 + +/* SPI_W6_REG register + * SPI CPU-controlled buffer6 + */ + +#define SPI_W6_REG (DR_REG_SPI2_BASE + 0xb0) + +/* SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF6 0xFFFFFFFF +#define SPI_BUF6_M (SPI_BUF6_V << SPI_BUF6_S) +#define SPI_BUF6_V 0xFFFFFFFF +#define SPI_BUF6_S 0 + +/* SPI_W7_REG register + * SPI CPU-controlled buffer7 + */ + +#define SPI_W7_REG (DR_REG_SPI2_BASE + 0xb4) + +/* SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF7 0xFFFFFFFF +#define SPI_BUF7_M (SPI_BUF7_V << SPI_BUF7_S) +#define SPI_BUF7_V 0xFFFFFFFF +#define SPI_BUF7_S 0 + +/* SPI_W8_REG register + * SPI CPU-controlled buffer8 + */ + +#define SPI_W8_REG (DR_REG_SPI2_BASE + 0xb8) + +/* SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF8 0xFFFFFFFF +#define SPI_BUF8_M (SPI_BUF8_V << SPI_BUF8_S) +#define SPI_BUF8_V 0xFFFFFFFF +#define SPI_BUF8_S 0 + +/* SPI_W9_REG register + * SPI CPU-controlled buffer9 + */ + +#define SPI_W9_REG (DR_REG_SPI2_BASE + 0xbc) + +/* SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF9 0xFFFFFFFF +#define SPI_BUF9_M (SPI_BUF9_V << SPI_BUF9_S) +#define SPI_BUF9_V 0xFFFFFFFF +#define SPI_BUF9_S 0 + +/* SPI_W10_REG register + * SPI CPU-controlled buffer10 + */ + +#define SPI_W10_REG (DR_REG_SPI2_BASE + 0xc0) + +/* SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF10 0xFFFFFFFF +#define SPI_BUF10_M (SPI_BUF10_V << SPI_BUF10_S) +#define SPI_BUF10_V 0xFFFFFFFF +#define SPI_BUF10_S 0 + +/* SPI_W11_REG register + * SPI CPU-controlled buffer11 + */ + +#define SPI_W11_REG (DR_REG_SPI2_BASE + 0xc4) + +/* SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF11 0xFFFFFFFF +#define SPI_BUF11_M (SPI_BUF11_V << SPI_BUF11_S) +#define SPI_BUF11_V 0xFFFFFFFF +#define SPI_BUF11_S 0 + +/* SPI_W12_REG register + * SPI CPU-controlled buffer12 + */ + +#define SPI_W12_REG (DR_REG_SPI2_BASE + 0xc8) + +/* SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF12 0xFFFFFFFF +#define SPI_BUF12_M (SPI_BUF12_V << SPI_BUF12_S) +#define SPI_BUF12_V 0xFFFFFFFF +#define SPI_BUF12_S 0 + +/* SPI_W13_REG register + * SPI CPU-controlled buffer13 + */ + +#define SPI_W13_REG (DR_REG_SPI2_BASE + 0xcc) + +/* SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF13 0xFFFFFFFF +#define SPI_BUF13_M (SPI_BUF13_V << SPI_BUF13_S) +#define SPI_BUF13_V 0xFFFFFFFF +#define SPI_BUF13_S 0 + +/* SPI_W14_REG register + * SPI CPU-controlled buffer14 + */ + +#define SPI_W14_REG (DR_REG_SPI2_BASE + 0xd0) + +/* SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF14 0xFFFFFFFF +#define SPI_BUF14_M (SPI_BUF14_V << SPI_BUF14_S) +#define SPI_BUF14_V 0xFFFFFFFF +#define SPI_BUF14_S 0 + +/* SPI_W15_REG register + * SPI CPU-controlled buffer15 + */ + +#define SPI_W15_REG (DR_REG_SPI2_BASE + 0xd4) + +/* SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0; + * data buffer + */ + +#define SPI_BUF15 0xFFFFFFFF +#define SPI_BUF15_M (SPI_BUF15_V << SPI_BUF15_S) +#define SPI_BUF15_V 0xFFFFFFFF +#define SPI_BUF15_S 0 + +/* SPI_SLAVE_REG register + * SPI slave control register + */ + +#define SPI_SLAVE_REG (DR_REG_SPI2_BASE + 0xe0) + +/* SPI_USR_CONF : R/W; bitpos: [28]; default: 0; + * 1: Enable the DMA CONF phase of current seg-trans operation, which means + * seg-trans will start. 0: This is not seg-trans mode. + */ + +#define SPI_USR_CONF (BIT(28)) +#define SPI_USR_CONF_M (SPI_USR_CONF_V << SPI_USR_CONF_S) +#define SPI_USR_CONF_V 0x00000001 +#define SPI_USR_CONF_S 28 + +/* SPI_SOFT_RESET : WT; bitpos: [27]; default: 0; + * Software reset enable, reset the spi clock line cs line and data lines. + * Can be configured in CONF state. + */ + +#define SPI_SOFT_RESET (BIT(27)) +#define SPI_SOFT_RESET_M (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S) +#define SPI_SOFT_RESET_V 0x00000001 +#define SPI_SOFT_RESET_S 27 + +/* SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0; + * Set SPI work mode. 1: slave mode 0: master mode. + */ + +#define SPI_SLAVE_MODE (BIT(26)) +#define SPI_SLAVE_MODE_M (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S) +#define SPI_SLAVE_MODE_V 0x00000001 +#define SPI_SLAVE_MODE_S 26 + +/* SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10; + * The magic value of BM table in master DMA seg-trans. + */ + +#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000F +#define SPI_DMA_SEG_MAGIC_VALUE_M (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S) +#define SPI_DMA_SEG_MAGIC_VALUE_V 0x0000000F +#define SPI_DMA_SEG_MAGIC_VALUE_S 22 + +/* SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave + * data length in CPU controlled mode(Wr_BUF). 0: others + */ + +#define SPI_SLV_WRBUF_BITLEN_EN (BIT(11)) +#define SPI_SLV_WRBUF_BITLEN_EN_M (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S) +#define SPI_SLV_WRBUF_BITLEN_EN_V 0x00000001 +#define SPI_SLV_WRBUF_BITLEN_EN_S 11 + +/* SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data + * length in CPU controlled mode(Rd_BUF). 0: others + */ + +#define SPI_SLV_RDBUF_BITLEN_EN (BIT(10)) +#define SPI_SLV_RDBUF_BITLEN_EN_M (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S) +#define SPI_SLV_RDBUF_BITLEN_EN_V 0x00000001 +#define SPI_SLV_RDBUF_BITLEN_EN_S 10 + +/* SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave + * data length in DMA controlled mode(Wr_DMA). 0: others + */ + +#define SPI_SLV_WRDMA_BITLEN_EN (BIT(9)) +#define SPI_SLV_WRDMA_BITLEN_EN_M (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S) +#define SPI_SLV_WRDMA_BITLEN_EN_V 0x00000001 +#define SPI_SLV_WRDMA_BITLEN_EN_S 9 + +/* SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0; + * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data + * length in DMA controlled mode(Rd_DMA). 0: others + */ + +#define SPI_SLV_RDDMA_BITLEN_EN (BIT(8)) +#define SPI_SLV_RDDMA_BITLEN_EN_M (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S) +#define SPI_SLV_RDDMA_BITLEN_EN_V 0x00000001 +#define SPI_SLV_RDDMA_BITLEN_EN_S 8 + +/* SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0; + * It saves half a cycle when tsck is the same as rsck. 1: output data at + * rsck posedge 0: output data at tsck posedge + */ + +#define SPI_RSCK_DATA_OUT (BIT(3)) +#define SPI_RSCK_DATA_OUT_M (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S) +#define SPI_RSCK_DATA_OUT_V 0x00000001 +#define SPI_RSCK_DATA_OUT_S 3 + +/* SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0; + * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data + * B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data + * B[1]/B[6]. + */ + +#define SPI_CLK_MODE_13 (BIT(2)) +#define SPI_CLK_MODE_13_M (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S) +#define SPI_CLK_MODE_13_V 0x00000001 +#define SPI_CLK_MODE_13_S 2 + +/* SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; + * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is + * delayed one cycle after CS inactive 2: SPI clock is delayed two cycles + * after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF + * state. + */ + +#define SPI_CLK_MODE 0x00000003 +#define SPI_CLK_MODE_M (SPI_CLK_MODE_V << SPI_CLK_MODE_S) +#define SPI_CLK_MODE_V 0x00000003 +#define SPI_CLK_MODE_S 0 + +/* SPI_SLAVE1_REG register + * SPI slave control register 1 + */ + +#define SPI_SLAVE1_REG (DR_REG_SPI2_BASE + 0xe4) + +/* SPI_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0; + * In the slave mode it is the value of address. + */ + +#define SPI_SLV_LAST_ADDR 0x0000003F +#define SPI_SLV_LAST_ADDR_M (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S) +#define SPI_SLV_LAST_ADDR_V 0x0000003F +#define SPI_SLV_LAST_ADDR_S 26 + +/* SPI_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0; + * In the slave mode it is the value of command. + */ + +#define SPI_SLV_LAST_COMMAND 0x000000FF +#define SPI_SLV_LAST_COMMAND_M (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S) +#define SPI_SLV_LAST_COMMAND_V 0x000000FF +#define SPI_SLV_LAST_COMMAND_S 18 + +/* SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0; + * The transferred data bit length in SPI slave FD and HD mode. + */ + +#define SPI_SLV_DATA_BITLEN 0x0003FFFF +#define SPI_SLV_DATA_BITLEN_M (SPI_SLV_DATA_BITLEN_V << SPI_SLV_DATA_BITLEN_S) +#define SPI_SLV_DATA_BITLEN_V 0x0003FFFF +#define SPI_SLV_DATA_BITLEN_S 0 + +/* SPI_CLK_GATE_REG register + * SPI module clock and register clock control + */ + +#define SPI_CLK_GATE_REG (DR_REG_SPI2_BASE + 0xe8) + +/* SPI_MST_CLK_SEL : R/W; bitpos: [2]; default: 0; + * This bit is used to select SPI module clock source in master mode. 1: + * PLL_CLK_80M. 0: XTAL CLK. + */ + +#define SPI_MST_CLK_SEL (BIT(2)) +#define SPI_MST_CLK_SEL_M (SPI_MST_CLK_SEL_V << SPI_MST_CLK_SEL_S) +#define SPI_MST_CLK_SEL_V 0x00000001 +#define SPI_MST_CLK_SEL_S 2 + +/* SPI_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0; + * Set this bit to power on the SPI module clock. + */ + +#define SPI_MST_CLK_ACTIVE (BIT(1)) +#define SPI_MST_CLK_ACTIVE_M (SPI_MST_CLK_ACTIVE_V << SPI_MST_CLK_ACTIVE_S) +#define SPI_MST_CLK_ACTIVE_V 0x00000001 +#define SPI_MST_CLK_ACTIVE_S 1 + +/* SPI_CLK_EN : R/W; bitpos: [0]; default: 0; + * Set this bit to enable clk gate + */ + +#define SPI_CLK_EN (BIT(0)) +#define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) +#define SPI_CLK_EN_V 0x00000001 +#define SPI_CLK_EN_S 0 + +/* SPI_DATE_REG register + * Version control + */ + +#define SPI_DATE_REG (DR_REG_SPI2_BASE + 0xf0) + +/* SPI_DATE : R/W; bitpos: [27:0]; default: 33583648; + * SPI register version. + */ + +#define SPI_DATE 0x0FFFFFFF +#define SPI_DATE_M (SPI_DATE_V << SPI_DATE_S) +#define SPI_DATE_V 0x0FFFFFFF +#define SPI_DATE_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SPI_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_syscon.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_syscon.h similarity index 98% rename from arch/risc-v/src/esp32c3/hardware/esp32c3_syscon.h rename to arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_syscon.h index c7cf6b24b7b79..01a46aab89490 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_syscon.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_syscon.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_syscon.h + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_syscon.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SYSCON_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SYSCON_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SYSCON_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SYSCON_H /**************************************************************************** * Included Files @@ -639,4 +639,4 @@ #define SYSCON_DATE_V 0xFFFFFFFF #define SYSCON_DATE_S 0 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SYSCON_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SYSCON_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_system.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_system.h similarity index 99% rename from arch/risc-v/src/esp32c3/hardware/esp32c3_system.h rename to arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_system.h index 34ede266fb39b..1b49d6b56fa12 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_system.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_system.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_system.h + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_system.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SYSTEM_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SYSTEM_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SYSTEM_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SYSTEM_H /**************************************************************************** * Included Files @@ -1216,4 +1216,4 @@ #define SYSTEM_DATE_V 0xfffffff #define SYSTEM_DATE_S 0 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SYSTEM_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SYSTEM_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_systimer.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_systimer.h similarity index 98% rename from arch/risc-v/src/esp32c3/hardware/esp32c3_systimer.h rename to arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_systimer.h index ef317cb0201f1..a21aee905b6c0 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_systimer.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_systimer.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_systimer.h + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_systimer.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SYSTIMER_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SYSTIMER_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SYSTIMER_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SYSTIMER_H /**************************************************************************** * Included Files @@ -584,4 +584,4 @@ #define SYS_TIMER_DATE_V 0xffffffff #define SYS_TIMER_DATE_S 0 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SYSTIMER_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_SYSTIMER_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_tim.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_tim.h new file mode 100644 index 0000000000000..f8a812b7db250 --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_tim.h @@ -0,0 +1,537 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_tim.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_TIM_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_TIM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Offset relative to each watchdog timer instance memory base */ + +#define MWDT_CONFIG0_OFFSET 0x0048 + +/* MWDT */ + +#define MWDT_CLK_PRESCALE_OFFSET 0x004c +#define MWDT_STAGE0_TIMEOUT_OFFSET 0x0050 +#define MWDT_STAGE1_TIMEOUT_OFFSET 0x0054 +#define MWDT_STAGE2_TIMEOUT_OFFSET 0x0058 +#define MWDT_STAGE3_TIMEOUT_OFFSET 0x005c +#define MWDT_FEED_OFFSET 0x0060 +#define MWDT_WP_REG 0x0064 +#define MWDT_INT_ENA_REG_OFFSET 0x0070 +#define MWDT_INT_CLR_REG_OFFSET 0x007c + +/* The value that needs to be written to TIMG_WDT_WKEY to + * write-enable the WDT registers. + */ + +#define TIMG_WDT_WKEY_VALUE 0x50D83AA1 + +/* Possible values for TIMG_WDT_STGx */ + +#define TIMG_WDT_STG_SEL_OFF 0 +#define TIMG_WDT_STG_SEL_INT 1 +#define TIMG_WDT_STG_SEL_RESET_CPU 2 +#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3 + +#define TIMG_WDT_RESET_LENGTH_100_NS 0 +#define TIMG_WDT_RESET_LENGTH_200_NS 1 +#define TIMG_WDT_RESET_LENGTH_300_NS 2 +#define TIMG_WDT_RESET_LENGTH_400_NS 3 +#define TIMG_WDT_RESET_LENGTH_500_NS 4 +#define TIMG_WDT_RESET_LENGTH_800_NS 5 +#define TIMG_WDT_RESET_LENGTH_1600_NS 6 +#define TIMG_WDT_RESET_LENGTH_3200_NS 7 + +/* Maximum value in the high 22 bits from timer counters */ + +#define LOW_32_MASK 0xffffffff +#define LOW_22_MASK 0x003fffff +#define LOW_20_MASK 0x000fffff +#define LOW_26_MASK 0x03ffffff +#define SHIFT_32 32 + +#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000) + +/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ + +#define TIMG_T0_EN (BIT(31)) +#define TIMG_T0_EN_M (BIT(31)) +#define TIMG_T0_EN_V 0x1 +#define TIMG_T0_EN_S 31 + +/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ + +#define TIMG_T0_INCREASE (BIT(30)) +#define TIMG_T0_INCREASE_M (BIT(30)) +#define TIMG_T0_INCREASE_V 0x1 +#define TIMG_T0_INCREASE_S 30 + +/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ + +#define TIMG_T0_AUTORELOAD (BIT(29)) +#define TIMG_T0_AUTORELOAD_M (BIT(29)) +#define TIMG_T0_AUTORELOAD_V 0x1 +#define TIMG_T0_AUTORELOAD_S 29 + +/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ + +#define TIMG_T0_DIVIDER 0x0000FFFF +#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S)) +#define TIMG_T0_DIVIDER_V 0xFFFF +#define TIMG_T0_DIVIDER_S 13 + +/* TIMG_T0_DIVCNT_RST : WT ;bitpos:[12] ;default: 1'h0 ; */ + +#define TIMG_T0_DIVCNT_RST (BIT(12)) +#define TIMG_T0_DIVCNT_RST_M (BIT(12)) +#define TIMG_T0_DIVCNT_RST_V 0x1 +#define TIMG_T0_DIVCNT_RST_S 12 + +/* TIMG_T0_ALARM_EN : R/W/SC ;bitpos:[10] ;default: 1'h0 ; */ + +#define TIMG_T0_ALARM_EN (BIT(10)) +#define TIMG_T0_ALARM_EN_M (BIT(10)) +#define TIMG_T0_ALARM_EN_V 0x1 +#define TIMG_T0_ALARM_EN_S 10 + +/* TIMG_T0_USE_XTAL : R/W ;bitpos:[9] ;default: 1'd0 ; */ + +#define TIMG_T0_USE_XTAL (BIT(9)) +#define TIMG_T0_USE_XTAL_M (BIT(9)) +#define TIMG_T0_USE_XTAL_V 0x1 +#define TIMG_T0_USE_XTAL_S 9 + +#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004) + +/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define TIMG_T0_LO 0xFFFFFFFF +#define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S)) +#define TIMG_T0_LO_V 0xFFFFFFFF +#define TIMG_T0_LO_S 0 + +#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008) + +/* TIMG_T0_HI : RO ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define TIMG_T0_HI 0x003FFFFF +#define TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S)) +#define TIMG_T0_HI_V 0x3FFFFF +#define TIMG_T0_HI_S 0 + +#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c) + +/* TIMG_T0_UPDATE : R/W/SC ;bitpos:[31] ;default: 1'h0 ; */ + +#define TIMG_T0_UPDATE (BIT(31)) +#define TIMG_T0_UPDATE_M (BIT(31)) +#define TIMG_T0_UPDATE_V 0x1 +#define TIMG_T0_UPDATE_S 31 + +#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010) + +/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define TIMG_T0_ALARM_LO 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S)) +#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_S 0 + +#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014) + +/* TIMG_T0_ALARM_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define TIMG_T0_ALARM_HI 0x003FFFFF +#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S)) +#define TIMG_T0_ALARM_HI_V 0x3FFFFF +#define TIMG_T0_ALARM_HI_S 0 + +#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018) + +/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define TIMG_T0_LOAD_LO 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S)) +#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_S 0 + +#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c) + +/* TIMG_T0_LOAD_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ + +#define TIMG_T0_LOAD_HI 0x003FFFFF +#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S)) +#define TIMG_T0_LOAD_HI_V 0x3FFFFF +#define TIMG_T0_LOAD_HI_S 0 + +#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020) + +/* TIMG_T0_LOAD : WT ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define TIMG_T0_LOAD 0xFFFFFFFF +#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S)) +#define TIMG_T0_LOAD_V 0xFFFFFFFF +#define TIMG_T0_LOAD_S 0 + +#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048) + +/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ + +#define TIMG_WDT_EN (BIT(31)) +#define TIMG_WDT_EN_M (BIT(31)) +#define TIMG_WDT_EN_V 0x1 +#define TIMG_WDT_EN_S 31 + +/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 2'd0 ; */ + +#define TIMG_WDT_STG0 0x00000003 +#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S)) +#define TIMG_WDT_STG0_V 0x3 +#define TIMG_WDT_STG0_S 29 + +/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ + +#define TIMG_WDT_STG1 0x00000003 +#define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S)) +#define TIMG_WDT_STG1_V 0x3 +#define TIMG_WDT_STG1_S 27 + +/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 2'd0 ; */ + +#define TIMG_WDT_STG2 0x00000003 +#define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S)) +#define TIMG_WDT_STG2_V 0x3 +#define TIMG_WDT_STG2_S 25 + +/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 2'd0 ; */ + +#define TIMG_WDT_STG3 0x00000003 +#define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S)) +#define TIMG_WDT_STG3_V 0x3 +#define TIMG_WDT_STG3_S 23 + +/* TIMG_WDT_CONF_UPDATE_EN : WT ;bitpos:[22] ;default: 1'h0 ; */ + +#define TIMG_WDT_CONF_UPDATE_EN (BIT(22)) +#define TIMG_WDT_CONF_UPDATE_EN_M (BIT(22)) +#define TIMG_WDT_CONF_UPDATE_EN_V 0x1 +#define TIMG_WDT_CONF_UPDATE_EN_S 22 + +/* TIMG_WDT_USE_XTAL : R/W ;bitpos:[21] ;default: 1'h0 ; */ + +#define TIMG_WDT_USE_XTAL (BIT(21)) +#define TIMG_WDT_USE_XTAL_M (BIT(21)) +#define TIMG_WDT_USE_XTAL_V 0x1 +#define TIMG_WDT_USE_XTAL_S 21 + +/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */ + +#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007 +#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S)) +#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7 +#define TIMG_WDT_CPU_RESET_LENGTH_S 18 + +/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */ + +#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007 +#define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S)) +#define TIMG_WDT_SYS_RESET_LENGTH_V 0x7 +#define TIMG_WDT_SYS_RESET_LENGTH_S 15 + +/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ + +#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 + +/* TIMG_WDT_PROCPU_RESET_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */ + +#define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_M (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_V 0x1 +#define TIMG_WDT_PROCPU_RESET_EN_S 13 + +/* TIMG_WDT_APPCPU_RESET_EN : R/W ;bitpos:[12] ;default: 1'd0 ; */ + +#define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_M (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_V 0x1 +#define TIMG_WDT_APPCPU_RESET_EN_S 12 + +#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c) + +/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */ + +#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF +#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S)) +#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF +#define TIMG_WDT_CLK_PRESCALE_S 16 + +/* TIMG_WDT_DIVCNT_RST : WT ;bitpos:[0] ;default: 1'b0 ; */ + +#define TIMG_WDT_DIVCNT_RST (BIT(0)) +#define TIMG_WDT_DIVCNT_RST_M (BIT(0)) +#define TIMG_WDT_DIVCNT_RST_V 0x1 +#define TIMG_WDT_DIVCNT_RST_S 0 + +#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050) + +/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */ + +#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S)) +#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_S 0 + +#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054) + +/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */ + +#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S)) +#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_S 0 + +#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058) + +/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ + +#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S)) +#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_S 0 + +#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c) + +/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ + +#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S)) +#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_S 0 + +#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060) + +/* TIMG_WDT_FEED : WT ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define TIMG_WDT_FEED 0xFFFFFFFF +#define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S)) +#define TIMG_WDT_FEED_V 0xFFFFFFFF +#define TIMG_WDT_FEED_S 0 + +#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064) + +/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ + +#define TIMG_WDT_WKEY 0xFFFFFFFF +#define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S)) +#define TIMG_WDT_WKEY_V 0xFFFFFFFF +#define TIMG_WDT_WKEY_S 0 + +#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068) + +/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */ + +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (BIT(31)) +#define TIMG_RTC_CALI_START_V 0x1 +#define TIMG_RTC_CALI_START_S 31 + +/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */ + +#define TIMG_RTC_CALI_MAX 0x00007FFF +#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S)) +#define TIMG_RTC_CALI_MAX_V 0x7FFF +#define TIMG_RTC_CALI_MAX_S 16 + +/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */ + +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (BIT(15)) +#define TIMG_RTC_CALI_RDY_V 0x1 +#define TIMG_RTC_CALI_RDY_S 15 + +/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */ + +#define TIMG_RTC_CALI_CLK_SEL 0x00000003 +#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S)) +#define TIMG_RTC_CALI_CLK_SEL_V 0x3 +#define TIMG_RTC_CALI_CLK_SEL_S 13 + +/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */ + +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_V 0x1 +#define TIMG_RTC_CALI_START_CYCLING_S 12 + +#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c) + +/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */ + +#define TIMG_RTC_CALI_VALUE 0x01FFFFFF +#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S)) +#define TIMG_RTC_CALI_VALUE_V 0x1FFFFFF +#define TIMG_RTC_CALI_VALUE_S 7 + +/* TIMG_RTC_CALI_CYCLING_DATA_VLD : RO ;bitpos:[0] ;default: 1'b0 ; */ + +#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x1 +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 + +#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0070) + +/* TIMG_WDT_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ + +#define TIMG_WDT_INT_ENA (BIT(1)) +#define TIMG_WDT_INT_ENA_M (BIT(1)) +#define TIMG_WDT_INT_ENA_V 0x1 +#define TIMG_WDT_INT_ENA_S 1 + +/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ + +#define TIMG_T0_INT_ENA (BIT(0)) +#define TIMG_T0_INT_ENA_M (BIT(0)) +#define TIMG_T0_INT_ENA_V 0x1 +#define TIMG_T0_INT_ENA_S 0 + +#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0074) + +/* TIMG_WDT_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'h0 ; */ + +#define TIMG_WDT_INT_RAW (BIT(1)) +#define TIMG_WDT_INT_RAW_M (BIT(1)) +#define TIMG_WDT_INT_RAW_V 0x1 +#define TIMG_WDT_INT_RAW_S 1 + +/* TIMG_T0_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'h0 ; */ + +#define TIMG_T0_INT_RAW (BIT(0)) +#define TIMG_T0_INT_RAW_M (BIT(0)) +#define TIMG_T0_INT_RAW_V 0x1 +#define TIMG_T0_INT_RAW_S 0 + +#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0078) + +/* TIMG_WDT_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ + +#define TIMG_WDT_INT_ST (BIT(1)) +#define TIMG_WDT_INT_ST_M (BIT(1)) +#define TIMG_WDT_INT_ST_V 0x1 +#define TIMG_WDT_INT_ST_S 1 + +/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ + +#define TIMG_T0_INT_ST (BIT(0)) +#define TIMG_T0_INT_ST_M (BIT(0)) +#define TIMG_T0_INT_ST_V 0x1 +#define TIMG_T0_INT_ST_S 0 + +#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x007c) + +/* TIMG_WDT_INT_CLR : WT ;bitpos:[1] ;default: 1'h0 ; */ + +#define TIMG_WDT_INT_CLR (BIT(1)) +#define TIMG_WDT_INT_CLR_M (BIT(1)) +#define TIMG_WDT_INT_CLR_V 0x1 +#define TIMG_WDT_INT_CLR_S 1 + +/* TIMG_T0_INT_CLR : WT ;bitpos:[0] ;default: 1'h0 ; */ + +#define TIMG_T0_INT_CLR (BIT(0)) +#define TIMG_T0_INT_CLR_M (BIT(0)) +#define TIMG_T0_INT_CLR_V 0x1 +#define TIMG_T0_INT_CLR_S 0 + +#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x0080) + +/* TIMG_RTC_CALI_TIMEOUT_THRES : R/W ;bitpos:[31:7] ;default: 25'h1ffffff ; */ + +/* description: timeout if cali value counts over threshold */ + +#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFF +#define TIMG_RTC_CALI_TIMEOUT_THRES_M ((TIMG_RTC_CALI_TIMEOUT_THRES_V)<<(TIMG_RTC_CALI_TIMEOUT_THRES_S)) +#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x1FFFFFF +#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 + +/* TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W ;bitpos:[6:3] ;default: 4'd3 ; */ + +/* description: Cycles that release calibration timeout reset */ + +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000F +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M ((TIMG_RTC_CALI_TIMEOUT_RST_CNT_V)<<(TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)) +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0xF +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 + +/* TIMG_RTC_CALI_TIMEOUT : RO ;bitpos:[0] ;default: 1'h0 ; */ + +/* description: timeout indicator */ + +#define TIMG_RTC_CALI_TIMEOUT (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_M (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_V 0x1 +#define TIMG_RTC_CALI_TIMEOUT_S 0 + +#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8) + +/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006191 ; */ + +#define TIMG_NTIMERS_DATE 0x0FFFFFFF +#define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S)) +#define TIMG_NTIMERS_DATE_V 0xFFFFFFF +#define TIMG_NTIMERS_DATE_S 0 + +#define TIMG_CLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc) + +/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ + +#define TIMG_CLK_EN (BIT(31)) +#define TIMG_CLK_EN_M (BIT(31)) +#define TIMG_CLK_EN_V 0x1 +#define TIMG_CLK_EN_S 31 + +/* TIMG_TIMER_CLK_IS_ACTIVE : R/W ;bitpos:[30] ;default: 1'h1 ; */ + +#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30)) +#define TIMG_TIMER_CLK_IS_ACTIVE_M (BIT(30)) +#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x1 +#define TIMG_TIMER_CLK_IS_ACTIVE_S 30 + +/* TIMG_WDT_CLK_IS_ACTIVE : R/W ;bitpos:[29] ;default: 1'h1 ; */ + +#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29)) +#define TIMG_WDT_CLK_IS_ACTIVE_M (BIT(29)) +#define TIMG_WDT_CLK_IS_ACTIVE_V 0x1 +#define TIMG_WDT_CLK_IS_ACTIVE_S 29 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_TIM_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_twai.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_twai.h new file mode 100644 index 0000000000000..94161252d42ba --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_twai.h @@ -0,0 +1,856 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_twai.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_TWAI_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_TWAI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32c3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* TWAI_MODE_REG register + * Mode Register + */ + +#define TWAI_MODE_REG (DR_REG_TWAI_BASE + 0x0) + +/* TWAI_RX_FILTER_MODE : R/W; bitpos: [3]; default: 0; + * This bit is used to configure the filter mode. 0: Dual filter mode; 1: + * Single filter mode. + */ + +#define TWAI_RX_FILTER_MODE (BIT(3)) +#define TWAI_RX_FILTER_MODE_M (TWAI_RX_FILTER_MODE_V << TWAI_RX_FILTER_MODE_S) +#define TWAI_RX_FILTER_MODE_V 0x00000001 +#define TWAI_RX_FILTER_MODE_S 3 + +/* TWAI_SELF_TEST_MODE : R/W; bitpos: [2]; default: 0; + * 1: Self test mode. In this mode the TX nodes can perform a successful + * transmission without receiving the acknowledge signal. This mode is often + * used to test a single node with the self reception request command. + */ + +#define TWAI_SELF_TEST_MODE (BIT(2)) +#define TWAI_SELF_TEST_MODE_M (TWAI_SELF_TEST_MODE_V << TWAI_SELF_TEST_MODE_S) +#define TWAI_SELF_TEST_MODE_V 0x00000001 +#define TWAI_SELF_TEST_MODE_S 2 + +/* TWAI_LISTEN_ONLY_MODE : R/W; bitpos: [1]; default: 0; + * 1: Listen only mode. In this mode the nodes will only receive messages + * from the bus, without generating the acknowledge signal nor updating the + * RX error counter. + */ + +#define TWAI_LISTEN_ONLY_MODE (BIT(1)) +#define TWAI_LISTEN_ONLY_MODE_M (TWAI_LISTEN_ONLY_MODE_V << TWAI_LISTEN_ONLY_MODE_S) +#define TWAI_LISTEN_ONLY_MODE_V 0x00000001 +#define TWAI_LISTEN_ONLY_MODE_S 1 + +/* TWAI_RESET_MODE : R/W; bitpos: [0]; default: 1; + * This bit is used to configure the operating mode of the TWAI Controller. + * 1: Reset mode; 0: Operating mode. + */ + +#define TWAI_RESET_MODE (BIT(0)) +#define TWAI_RESET_MODE_M (TWAI_RESET_MODE_V << TWAI_RESET_MODE_S) +#define TWAI_RESET_MODE_V 0x00000001 +#define TWAI_RESET_MODE_S 0 + +/* TWAI_CMD_REG register + * Command Register + */ + +#define TWAI_CMD_REG (DR_REG_TWAI_BASE + 0x4) + +/* TWAI_SELF_RX_REQ : WO; bitpos: [4]; default: 0; + * Self reception request command. Set the bit to 1 to allow a message be + * transmitted and received simultaneously. + */ + +#define TWAI_SELF_RX_REQ (BIT(4)) +#define TWAI_SELF_RX_REQ_M (TWAI_SELF_RX_REQ_V << TWAI_SELF_RX_REQ_S) +#define TWAI_SELF_RX_REQ_V 0x00000001 +#define TWAI_SELF_RX_REQ_S 4 + +/* TWAI_CLR_OVERRUN : WO; bitpos: [3]; default: 0; + * Set the bit to 1 to clear the data overrun status bit. + */ + +#define TWAI_CLR_OVERRUN (BIT(3)) +#define TWAI_CLR_OVERRUN_M (TWAI_CLR_OVERRUN_V << TWAI_CLR_OVERRUN_S) +#define TWAI_CLR_OVERRUN_V 0x00000001 +#define TWAI_CLR_OVERRUN_S 3 + +/* TWAI_RELEASE_BUF : WO; bitpos: [2]; default: 0; + * Set the bit to 1 to release the RX buffer. + */ + +#define TWAI_RELEASE_BUF (BIT(2)) +#define TWAI_RELEASE_BUF_M (TWAI_RELEASE_BUF_V << TWAI_RELEASE_BUF_S) +#define TWAI_RELEASE_BUF_V 0x00000001 +#define TWAI_RELEASE_BUF_S 2 + +/* TWAI_ABORT_TX : WO; bitpos: [1]; default: 0; + * Set the bit to 1 to cancel a pending transmission request. + */ + +#define TWAI_ABORT_TX (BIT(1)) +#define TWAI_ABORT_TX_M (TWAI_ABORT_TX_V << TWAI_ABORT_TX_S) +#define TWAI_ABORT_TX_V 0x00000001 +#define TWAI_ABORT_TX_S 1 + +/* TWAI_TX_REQ : WO; bitpos: [0]; default: 0; + * Set the bit to 1 to allow the driving nodes start transmission. + */ + +#define TWAI_TX_REQ (BIT(0)) +#define TWAI_TX_REQ_M (TWAI_TX_REQ_V << TWAI_TX_REQ_S) +#define TWAI_TX_REQ_V 0x00000001 +#define TWAI_TX_REQ_S 0 + +/* TWAI_STATUS_REG register + * Status register + */ + +#define TWAI_STATUS_REG (DR_REG_TWAI_BASE + 0x8) + +/* TWAI_MISS_ST : RO; bitpos: [8]; default: 0; + * This bit reflects whether the data packet in the RX FIFO is complete. 1: + * The current packet is missing; 0: The current packet is complete + */ + +#define TWAI_MISS_ST (BIT(8)) +#define TWAI_MISS_ST_M (TWAI_MISS_ST_V << TWAI_MISS_ST_S) +#define TWAI_MISS_ST_V 0x00000001 +#define TWAI_MISS_ST_S 8 + +/* TWAI_BUS_OFF_ST : RO; bitpos: [7]; default: 0; + * 1: In bus-off status, the TWAI Controller is no longer involved in bus + * activities. + */ + +#define TWAI_BUS_OFF_ST (BIT(7)) +#define TWAI_BUS_OFF_ST_M (TWAI_BUS_OFF_ST_V << TWAI_BUS_OFF_ST_S) +#define TWAI_BUS_OFF_ST_V 0x00000001 +#define TWAI_BUS_OFF_ST_S 7 + +/* TWAI_ERR_ST : RO; bitpos: [6]; default: 0; + * 1: At least one of the RX/TX error counter has reached or exceeded the + * value set in register TWAI_ERR_WARNING_LIMIT_REG. + */ + +#define TWAI_ERR_ST (BIT(6)) +#define TWAI_ERR_ST_M (TWAI_ERR_ST_V << TWAI_ERR_ST_S) +#define TWAI_ERR_ST_V 0x00000001 +#define TWAI_ERR_ST_S 6 + +/* TWAI_TX_ST : RO; bitpos: [5]; default: 0; + * 1: The TWAI Controller is transmitting a message to the bus. + */ + +#define TWAI_TX_ST (BIT(5)) +#define TWAI_TX_ST_M (TWAI_TX_ST_V << TWAI_TX_ST_S) +#define TWAI_TX_ST_V 0x00000001 +#define TWAI_TX_ST_S 5 + +/* TWAI_RX_ST : RO; bitpos: [4]; default: 0; + * 1: The TWAI Controller is receiving a message from the bus. + */ + +#define TWAI_RX_ST (BIT(4)) +#define TWAI_RX_ST_M (TWAI_RX_ST_V << TWAI_RX_ST_S) +#define TWAI_RX_ST_V 0x00000001 +#define TWAI_RX_ST_S 4 + +/* TWAI_TX_COMPLETE : RO; bitpos: [3]; default: 0; + * 1: The TWAI controller has successfully received a packet from the bus. + */ + +#define TWAI_TX_COMPLETE (BIT(3)) +#define TWAI_TX_COMPLETE_M (TWAI_TX_COMPLETE_V << TWAI_TX_COMPLETE_S) +#define TWAI_TX_COMPLETE_V 0x00000001 +#define TWAI_TX_COMPLETE_S 3 + +/* TWAI_TX_BUF_ST : RO; bitpos: [2]; default: 0; + * 1: The TX buffer is empty, the CPU may write a message into it. + */ + +#define TWAI_TX_BUF_ST (BIT(2)) +#define TWAI_TX_BUF_ST_M (TWAI_TX_BUF_ST_V << TWAI_TX_BUF_ST_S) +#define TWAI_TX_BUF_ST_V 0x00000001 +#define TWAI_TX_BUF_ST_S 2 + +/* TWAI_OVERRUN_ST : RO; bitpos: [1]; default: 0; + * 1: The RX FIFO is full and data overrun has occurred. + */ + +#define TWAI_OVERRUN_ST (BIT(1)) +#define TWAI_OVERRUN_ST_M (TWAI_OVERRUN_ST_V << TWAI_OVERRUN_ST_S) +#define TWAI_OVERRUN_ST_V 0x00000001 +#define TWAI_OVERRUN_ST_S 1 + +/* TWAI_RX_BUF_ST : RO; bitpos: [0]; default: 0; + * 1: The data in the RX buffer is not empty, with at least one received + * data packet. + */ + +#define TWAI_RX_BUF_ST (BIT(0)) +#define TWAI_RX_BUF_ST_M (TWAI_RX_BUF_ST_V << TWAI_RX_BUF_ST_S) +#define TWAI_RX_BUF_ST_V 0x00000001 +#define TWAI_RX_BUF_ST_S 0 + +/* TWAI_INT_RAW_REG register + * Interrupt Register + */ + +#define TWAI_INT_RAW_REG (DR_REG_TWAI_BASE + 0xc) + +/* TWAI_BUS_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * Error interrupt. If this bit is set to 1, it indicates an error is + * detected on the bus. + */ + +#define TWAI_BUS_ERR_INT_ST (BIT(7)) +#define TWAI_BUS_ERR_INT_ST_M (TWAI_BUS_ERR_INT_ST_V << TWAI_BUS_ERR_INT_ST_S) +#define TWAI_BUS_ERR_INT_ST_V 0x00000001 +#define TWAI_BUS_ERR_INT_ST_S 7 + +/* TWAI_ARB_LOST_INT_ST : RO; bitpos: [6]; default: 0; + * Arbitration lost interrupt. If this bit is set to 1, it indicates an + * arbitration lost interrupt is generated. + */ + +#define TWAI_ARB_LOST_INT_ST (BIT(6)) +#define TWAI_ARB_LOST_INT_ST_M (TWAI_ARB_LOST_INT_ST_V << TWAI_ARB_LOST_INT_ST_S) +#define TWAI_ARB_LOST_INT_ST_V 0x00000001 +#define TWAI_ARB_LOST_INT_ST_S 6 + +/* TWAI_ERR_PASSIVE_INT_ST : RO; bitpos: [5]; default: 0; + * Error passive interrupt. If this bit is set to 1, it indicates the TWAI + * Controller is switched between error active status and error passive + * status due to the change of error counters. + */ + +#define TWAI_ERR_PASSIVE_INT_ST (BIT(5)) +#define TWAI_ERR_PASSIVE_INT_ST_M (TWAI_ERR_PASSIVE_INT_ST_V << TWAI_ERR_PASSIVE_INT_ST_S) +#define TWAI_ERR_PASSIVE_INT_ST_V 0x00000001 +#define TWAI_ERR_PASSIVE_INT_ST_S 5 + +/* TWAI_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0; + * Data overrun interrupt. If this bit is set to 1, it indicates a data + * overrun interrupt is generated in the RX FIFO. + */ + +#define TWAI_OVERRUN_INT_ST (BIT(3)) +#define TWAI_OVERRUN_INT_ST_M (TWAI_OVERRUN_INT_ST_V << TWAI_OVERRUN_INT_ST_S) +#define TWAI_OVERRUN_INT_ST_V 0x00000001 +#define TWAI_OVERRUN_INT_ST_S 3 + +/* TWAI_ERR_WARN_INT_ST : RO; bitpos: [2]; default: 0; + * Error warning interrupt. If this bit is set to 1, it indicates the error + * status signal and the bus-off status signal of Status register have + * changed (e.g., switched from 0 to 1 or from 1 to 0). + */ + +#define TWAI_ERR_WARN_INT_ST (BIT(2)) +#define TWAI_ERR_WARN_INT_ST_M (TWAI_ERR_WARN_INT_ST_V << TWAI_ERR_WARN_INT_ST_S) +#define TWAI_ERR_WARN_INT_ST_V 0x00000001 +#define TWAI_ERR_WARN_INT_ST_S 2 + +/* TWAI_TX_INT_ST : RO; bitpos: [1]; default: 0; + * Transmit interrupt. If this bit is set to 1, it indicates the message + * transmitting mis- sion is finished and a new transmission is able to + * execute. + */ + +#define TWAI_TX_INT_ST (BIT(1)) +#define TWAI_TX_INT_ST_M (TWAI_TX_INT_ST_V << TWAI_TX_INT_ST_S) +#define TWAI_TX_INT_ST_V 0x00000001 +#define TWAI_TX_INT_ST_S 1 + +/* TWAI_RX_INT_ST : RO; bitpos: [0]; default: 0; + * Receive interrupt. If this bit is set to 1, it indicates there are + * messages to be handled in the RX FIFO. + */ + +#define TWAI_RX_INT_ST (BIT(0)) +#define TWAI_RX_INT_ST_M (TWAI_RX_INT_ST_V << TWAI_RX_INT_ST_S) +#define TWAI_RX_INT_ST_V 0x00000001 +#define TWAI_RX_INT_ST_S 0 + +/* TWAI_INT_ENA_REG register + * Interrupt Enable Register + */ + +#define TWAI_INT_ENA_REG (DR_REG_TWAI_BASE + 0x10) + +/* TWAI_BUS_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * Set this bit to 1 to enable error interrupt. + */ + +#define TWAI_BUS_ERR_INT_ENA (BIT(7)) +#define TWAI_BUS_ERR_INT_ENA_M (TWAI_BUS_ERR_INT_ENA_V << TWAI_BUS_ERR_INT_ENA_S) +#define TWAI_BUS_ERR_INT_ENA_V 0x00000001 +#define TWAI_BUS_ERR_INT_ENA_S 7 + +/* TWAI_ARB_LOST_INT_ENA : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable arbitration lost interrupt. + */ + +#define TWAI_ARB_LOST_INT_ENA (BIT(6)) +#define TWAI_ARB_LOST_INT_ENA_M (TWAI_ARB_LOST_INT_ENA_V << TWAI_ARB_LOST_INT_ENA_S) +#define TWAI_ARB_LOST_INT_ENA_V 0x00000001 +#define TWAI_ARB_LOST_INT_ENA_S 6 + +/* TWAI_ERR_PASSIVE_INT_ENA : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable error passive interrupt. + */ + +#define TWAI_ERR_PASSIVE_INT_ENA (BIT(5)) +#define TWAI_ERR_PASSIVE_INT_ENA_M (TWAI_ERR_PASSIVE_INT_ENA_V << TWAI_ERR_PASSIVE_INT_ENA_S) +#define TWAI_ERR_PASSIVE_INT_ENA_V 0x00000001 +#define TWAI_ERR_PASSIVE_INT_ENA_S 5 + +/* TWAI_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable data overrun interrupt. + */ + +#define TWAI_OVERRUN_INT_ENA (BIT(3)) +#define TWAI_OVERRUN_INT_ENA_M (TWAI_OVERRUN_INT_ENA_V << TWAI_OVERRUN_INT_ENA_S) +#define TWAI_OVERRUN_INT_ENA_V 0x00000001 +#define TWAI_OVERRUN_INT_ENA_S 3 + +/* TWAI_ERR_WARN_INT_ENA : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable error warning interrupt. + */ + +#define TWAI_ERR_WARN_INT_ENA (BIT(2)) +#define TWAI_ERR_WARN_INT_ENA_M (TWAI_ERR_WARN_INT_ENA_V << TWAI_ERR_WARN_INT_ENA_S) +#define TWAI_ERR_WARN_INT_ENA_V 0x00000001 +#define TWAI_ERR_WARN_INT_ENA_S 2 + +/* TWAI_TX_INT_ENA : R/W; bitpos: [1]; default: 0; + * Set this bit to 1 to enable transmit interrupt. + */ + +#define TWAI_TX_INT_ENA (BIT(1)) +#define TWAI_TX_INT_ENA_M (TWAI_TX_INT_ENA_V << TWAI_TX_INT_ENA_S) +#define TWAI_TX_INT_ENA_V 0x00000001 +#define TWAI_TX_INT_ENA_S 1 + +/* TWAI_RX_INT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 to enable receive interrupt. + */ + +#define TWAI_RX_INT_ENA (BIT(0)) +#define TWAI_RX_INT_ENA_M (TWAI_RX_INT_ENA_V << TWAI_RX_INT_ENA_S) +#define TWAI_RX_INT_ENA_V 0x00000001 +#define TWAI_RX_INT_ENA_S 0 + +/* TWAI_BUS_TIMING_0_REG register + * Bus Timing Register 0 + */ + +#define TWAI_BUS_TIMING_0_REG (DR_REG_TWAI_BASE + 0x18) + +/* TWAI_SYNC_JUMP_WIDTH : RO | R/W; bitpos: [15:14]; default: 0; + * Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. + */ + +#define TWAI_SYNC_JUMP_WIDTH 0x00000003 +#define TWAI_SYNC_JUMP_WIDTH_M (TWAI_SYNC_JUMP_WIDTH_V << TWAI_SYNC_JUMP_WIDTH_S) +#define TWAI_SYNC_JUMP_WIDTH_V 0x00000003 +#define TWAI_SYNC_JUMP_WIDTH_S 14 + +/* TWAI_BAUD_PRESC : RO | R/W; bitpos: [13:0]; default: 0; + * Baud Rate Prescaler, determines the frequency dividing ratio. + */ + +#define TWAI_BAUD_PRESC 0x00003FFF +#define TWAI_BAUD_PRESC_M (TWAI_BAUD_PRESC_V << TWAI_BAUD_PRESC_S) +#define TWAI_BAUD_PRESC_V 0x00003FFF +#define TWAI_BAUD_PRESC_S 0 + +/* TWAI_BUS_TIMING_1_REG register + * Bus Timing Register 1 + */ + +#define TWAI_BUS_TIMING_1_REG (DR_REG_TWAI_BASE + 0x1c) + +/* TWAI_TIME_SAMP : RO | R/W; bitpos: [7]; default: 0; + * The number of sample points. 0: the bus is sampled once; 1: the bus is + * sampled three times + */ + +#define TWAI_TIME_SAMP (BIT(7)) +#define TWAI_TIME_SAMP_M (TWAI_TIME_SAMP_V << TWAI_TIME_SAMP_S) +#define TWAI_TIME_SAMP_V 0x00000001 +#define TWAI_TIME_SAMP_S 7 + +/* TWAI_TIME_SEG2 : RO | R/W; bitpos: [6:4]; default: 0; + * The width of PBS2. + */ + +#define TWAI_TIME_SEG2 0x00000007 +#define TWAI_TIME_SEG2_M (TWAI_TIME_SEG2_V << TWAI_TIME_SEG2_S) +#define TWAI_TIME_SEG2_V 0x00000007 +#define TWAI_TIME_SEG2_S 4 + +/* TWAI_TIME_SEG1 : RO | R/W; bitpos: [3:0]; default: 0; + * The width of PBS1. + */ + +#define TWAI_TIME_SEG1 0x0000000F +#define TWAI_TIME_SEG1_M (TWAI_TIME_SEG1_V << TWAI_TIME_SEG1_S) +#define TWAI_TIME_SEG1_V 0x0000000F +#define TWAI_TIME_SEG1_S 0 + +/* TWAI_ARB_LOST_CAP_REG register + * Arbitration Lost Capture Register + */ + +#define TWAI_ARB_LOST_CAP_REG (DR_REG_TWAI_BASE + 0x2c) + +/* TWAI_ARB_LOST_CAP : RO; bitpos: [4:0]; default: 0; + * This register contains information about the bit position of lost + * arbitration. + */ + +#define TWAI_ARB_LOST_CAP 0x0000001F +#define TWAI_ARB_LOST_CAP_M (TWAI_ARB_LOST_CAP_V << TWAI_ARB_LOST_CAP_S) +#define TWAI_ARB_LOST_CAP_V 0x0000001F +#define TWAI_ARB_LOST_CAP_S 0 + +/* TWAI_ERR_CODE_CAP_REG register + * Error Code Capture Register + */ + +#define TWAI_ERR_CODE_CAP_REG (DR_REG_TWAI_BASE + 0x30) + +/* TWAI_ECC_TYPE : RO; bitpos: [7:6]; default: 0; + * This register contains information about error types: 00: bit error; 01: + * form error; 10: stuff error; 11: other type of error + */ + +#define TWAI_ECC_TYPE 0x00000003 +#define TWAI_ECC_TYPE_M (TWAI_ECC_TYPE_V << TWAI_ECC_TYPE_S) +#define TWAI_ECC_TYPE_V 0x00000003 +#define TWAI_ECC_TYPE_S 6 + +/* TWAI_ECC_DIRECTION : RO; bitpos: [5]; default: 0; + * This register contains information about transmission direction of the + * node when error occurs. 1: Error occurs when receiving a message; 0: + * Error occurs when transmitting a message + */ + +#define TWAI_ECC_DIRECTION (BIT(5)) +#define TWAI_ECC_DIRECTION_M (TWAI_ECC_DIRECTION_V << TWAI_ECC_DIRECTION_S) +#define TWAI_ECC_DIRECTION_V 0x00000001 +#define TWAI_ECC_DIRECTION_S 5 + +/* TWAI_ECC_SEGMENT : RO; bitpos: [4:0]; default: 0; + * This register contains information about the location of errors, see + * Table 181 for details. + */ + +#define TWAI_ECC_SEGMENT 0x0000001F +#define TWAI_ECC_SEGMENT_M (TWAI_ECC_SEGMENT_V << TWAI_ECC_SEGMENT_S) +#define TWAI_ECC_SEGMENT_V 0x0000001F +#define TWAI_ECC_SEGMENT_S 0 + +/* TWAI_ERR_WARNING_LIMIT_REG register + * Error Warning Limit Register + */ + +#define TWAI_ERR_WARNING_LIMIT_REG (DR_REG_TWAI_BASE + 0x34) + +/* TWAI_ERR_WARNING_LIMIT : RO | R/W; bitpos: [7:0]; default: 96; + * Error warning threshold. In the case when any of a error counter value + * exceeds the threshold, or all the error counter values are below the + * threshold, an error warning interrupt will be triggered (given the enable + * signal is valid). + */ + +#define TWAI_ERR_WARNING_LIMIT 0x000000FF +#define TWAI_ERR_WARNING_LIMIT_M (TWAI_ERR_WARNING_LIMIT_V << TWAI_ERR_WARNING_LIMIT_S) +#define TWAI_ERR_WARNING_LIMIT_V 0x000000FF +#define TWAI_ERR_WARNING_LIMIT_S 0 + +/* TWAI_RX_ERR_CNT_REG register + * Receive Error Counter Register + */ + +#define TWAI_RX_ERR_CNT_REG (DR_REG_TWAI_BASE + 0x38) + +/* TWAI_RX_ERR_CNT : RO | R/W; bitpos: [7:0]; default: 0; + * The RX error counter register, reflects value changes under reception + * status. + */ + +#define TWAI_RX_ERR_CNT 0x000000FF +#define TWAI_RX_ERR_CNT_M (TWAI_RX_ERR_CNT_V << TWAI_RX_ERR_CNT_S) +#define TWAI_RX_ERR_CNT_V 0x000000FF +#define TWAI_RX_ERR_CNT_S 0 + +/* TWAI_TX_ERR_CNT_REG register + * Transmit Error Counter Register + */ + +#define TWAI_TX_ERR_CNT_REG (DR_REG_TWAI_BASE + 0x3c) + +/* TWAI_TX_ERR_CNT : RO | R/W; bitpos: [7:0]; default: 0; + * The TX error counter register, reflects value changes under transmission + * status. + */ + +#define TWAI_TX_ERR_CNT 0x000000FF +#define TWAI_TX_ERR_CNT_M (TWAI_TX_ERR_CNT_V << TWAI_TX_ERR_CNT_S) +#define TWAI_TX_ERR_CNT_V 0x000000FF +#define TWAI_TX_ERR_CNT_S 0 + +/* TWAI_DATA_0_REG register + * Data register 0 + */ + +#define TWAI_DATA_0_REG (DR_REG_TWAI_BASE + 0x40) + +/* TWAI_TX_BYTE_0 : WO; bitpos: [7:0]; default: 0; + * Stored the 0th byte information of the data to be transmitted under + * operating mode. + */ + +#define TWAI_TX_BYTE_0 0x000000FF +#define TWAI_TX_BYTE_0_M (TWAI_TX_BYTE_0_V << TWAI_TX_BYTE_0_S) +#define TWAI_TX_BYTE_0_V 0x000000FF +#define TWAI_TX_BYTE_0_S 0 + +/* TWAI_ACCEPTANCE_CODE_0 : WO; bitpos: [7:0]; default: 0; + * Stored the 0th byte of the filter code in reset mode. + */ + +#define TWAI_ACCEPTANCE_CODE_0 0x000000FF +#define TWAI_ACCEPTANCE_CODE_0_M (TWAI_ACCEPTANCE_CODE_0_V << TWAI_ACCEPTANCE_CODE_0_S) +#define TWAI_ACCEPTANCE_CODE_0_V 0x000000FF +#define TWAI_ACCEPTANCE_CODE_0_S 0 + +/* TWAI_DATA_1_REG register + * Data register 1 + */ + +#define TWAI_DATA_1_REG (DR_REG_TWAI_BASE + 0x44) + +/* TWAI_TX_BYTE_1 : WO; bitpos: [7:0]; default: 0; + * Stored the 1st byte information of the data to be transmitted under + * operating mode. + */ + +#define TWAI_TX_BYTE_1 0x000000FF +#define TWAI_TX_BYTE_1_M (TWAI_TX_BYTE_1_V << TWAI_TX_BYTE_1_S) +#define TWAI_TX_BYTE_1_V 0x000000FF +#define TWAI_TX_BYTE_1_S 0 + +/* TWAI_ACCEPTANCE_CODE_1 : WO; bitpos: [7:0]; default: 0; + * Stored the 1st byte of the filter code in reset mode. + */ + +#define TWAI_ACCEPTANCE_CODE_1 0x000000FF +#define TWAI_ACCEPTANCE_CODE_1_M (TWAI_ACCEPTANCE_CODE_1_V << TWAI_ACCEPTANCE_CODE_1_S) +#define TWAI_ACCEPTANCE_CODE_1_V 0x000000FF +#define TWAI_ACCEPTANCE_CODE_1_S 0 + +/* TWAI_DATA_2_REG register + * Data register 2 + */ + +#define TWAI_DATA_2_REG (DR_REG_TWAI_BASE + 0x48) + +/* TWAI_TX_BYTE_2 : WO; bitpos: [7:0]; default: 0; + * Stored the 2nd byte information of the data to be transmitted under + * operating mode. + */ + +#define TWAI_TX_BYTE_2 0x000000FF +#define TWAI_TX_BYTE_2_M (TWAI_TX_BYTE_2_V << TWAI_TX_BYTE_2_S) +#define TWAI_TX_BYTE_2_V 0x000000FF +#define TWAI_TX_BYTE_2_S 0 + +/* TWAI_ACCEPTANCE_CODE_2 : WO; bitpos: [7:0]; default: 0; + * Stored the 2nd byte of the filter code in reset mode. + */ + +#define TWAI_ACCEPTANCE_CODE_2 0x000000FF +#define TWAI_ACCEPTANCE_CODE_2_M (TWAI_ACCEPTANCE_CODE_2_V << TWAI_ACCEPTANCE_CODE_2_S) +#define TWAI_ACCEPTANCE_CODE_2_V 0x000000FF +#define TWAI_ACCEPTANCE_CODE_2_S 0 + +/* TWAI_DATA_3_REG register + * Data register 3 + */ + +#define TWAI_DATA_3_REG (DR_REG_TWAI_BASE + 0x4c) + +/* TWAI_TX_BYTE_3 : WO; bitpos: [7:0]; default: 0; + * Stored the 3rd byte information of the data to be transmitted under + * operating mode. + */ + +#define TWAI_TX_BYTE_3 0x000000FF +#define TWAI_TX_BYTE_3_M (TWAI_TX_BYTE_3_V << TWAI_TX_BYTE_3_S) +#define TWAI_TX_BYTE_3_V 0x000000FF +#define TWAI_TX_BYTE_3_S 0 + +/* TWAI_ACCEPTANCE_CODE_3 : WO; bitpos: [7:0]; default: 0; + * Stored the 3rd byte of the filter code in reset mode. + */ + +#define TWAI_ACCEPTANCE_CODE_3 0x000000FF +#define TWAI_ACCEPTANCE_CODE_3_M (TWAI_ACCEPTANCE_CODE_3_V << TWAI_ACCEPTANCE_CODE_3_S) +#define TWAI_ACCEPTANCE_CODE_3_V 0x000000FF +#define TWAI_ACCEPTANCE_CODE_3_S 0 + +/* TWAI_DATA_4_REG register + * Data register 4 + */ + +#define TWAI_DATA_4_REG (DR_REG_TWAI_BASE + 0x50) + +/* TWAI_TX_BYTE_4 : WO; bitpos: [7:0]; default: 0; + * Stored the 4th byte information of the data to be transmitted under + * operating mode. + */ + +#define TWAI_TX_BYTE_4 0x000000FF +#define TWAI_TX_BYTE_4_M (TWAI_TX_BYTE_4_V << TWAI_TX_BYTE_4_S) +#define TWAI_TX_BYTE_4_V 0x000000FF +#define TWAI_TX_BYTE_4_S 0 + +/* TWAI_ACCEPTANCE_MASK_0 : WO; bitpos: [7:0]; default: 0; + * Stored the 0th byte of the filter code in reset mode. + */ + +#define TWAI_ACCEPTANCE_MASK_0 0x000000FF +#define TWAI_ACCEPTANCE_MASK_0_M (TWAI_ACCEPTANCE_MASK_0_V << TWAI_ACCEPTANCE_MASK_0_S) +#define TWAI_ACCEPTANCE_MASK_0_V 0x000000FF +#define TWAI_ACCEPTANCE_MASK_0_S 0 + +/* TWAI_DATA_5_REG register + * Data register 5 + */ + +#define TWAI_DATA_5_REG (DR_REG_TWAI_BASE + 0x54) + +/* TWAI_TX_BYTE_5 : WO; bitpos: [7:0]; default: 0; + * Stored the 5th byte information of the data to be transmitted under + * operating mode. + */ + +#define TWAI_TX_BYTE_5 0x000000FF +#define TWAI_TX_BYTE_5_M (TWAI_TX_BYTE_5_V << TWAI_TX_BYTE_5_S) +#define TWAI_TX_BYTE_5_V 0x000000FF +#define TWAI_TX_BYTE_5_S 0 + +/* TWAI_ACCEPTANCE_MASK_1 : WO; bitpos: [7:0]; default: 0; + * Stored the 1st byte of the filter code in reset mode. + */ + +#define TWAI_ACCEPTANCE_MASK_1 0x000000FF +#define TWAI_ACCEPTANCE_MASK_1_M (TWAI_ACCEPTANCE_MASK_1_V << TWAI_ACCEPTANCE_MASK_1_S) +#define TWAI_ACCEPTANCE_MASK_1_V 0x000000FF +#define TWAI_ACCEPTANCE_MASK_1_S 0 + +/* TWAI_DATA_6_REG register + * Data register 6 + */ + +#define TWAI_DATA_6_REG (DR_REG_TWAI_BASE + 0x58) + +/* TWAI_TX_BYTE_6 : WO; bitpos: [7:0]; default: 0; + * Stored the 6th byte information of the data to be transmitted under + * operating mode. + */ + +#define TWAI_TX_BYTE_6 0x000000FF +#define TWAI_TX_BYTE_6_M (TWAI_TX_BYTE_6_V << TWAI_TX_BYTE_6_S) +#define TWAI_TX_BYTE_6_V 0x000000FF +#define TWAI_TX_BYTE_6_S 0 + +/* TWAI_ACCEPTANCE_MASK_2 : WO; bitpos: [7:0]; default: 0; + * Stored the 2nd byte of the filter code in reset mode. + */ + +#define TWAI_ACCEPTANCE_MASK_2 0x000000FF +#define TWAI_ACCEPTANCE_MASK_2_M (TWAI_ACCEPTANCE_MASK_2_V << TWAI_ACCEPTANCE_MASK_2_S) +#define TWAI_ACCEPTANCE_MASK_2_V 0x000000FF +#define TWAI_ACCEPTANCE_MASK_2_S 0 + +/* TWAI_DATA_7_REG register + * Data register 7 + */ + +#define TWAI_DATA_7_REG (DR_REG_TWAI_BASE + 0x5c) + +/* TWAI_TX_BYTE_7 : WO; bitpos: [7:0]; default: 0; + * Stored the 7th byte information of the data to be transmitted under + * operating mode. + */ + +#define TWAI_TX_BYTE_7 0x000000FF +#define TWAI_TX_BYTE_7_M (TWAI_TX_BYTE_7_V << TWAI_TX_BYTE_7_S) +#define TWAI_TX_BYTE_7_V 0x000000FF +#define TWAI_TX_BYTE_7_S 0 + +/* TWAI_ACCEPTANCE_MASK_3 : WO; bitpos: [7:0]; default: 0; + * Stored the 3th byte of the filter code in reset mode. + */ + +#define TWAI_ACCEPTANCE_MASK_3 0x000000FF +#define TWAI_ACCEPTANCE_MASK_3_M (TWAI_ACCEPTANCE_MASK_3_V << TWAI_ACCEPTANCE_MASK_3_S) +#define TWAI_ACCEPTANCE_MASK_3_V 0x000000FF +#define TWAI_ACCEPTANCE_MASK_3_S 0 + +/* TWAI_DATA_8_REG register + * Data register 8 + */ + +#define TWAI_DATA_8_REG (DR_REG_TWAI_BASE + 0x60) + +/* TWAI_TX_BYTE_8 : WO; bitpos: [7:0]; default: 0; + * Stored the 8th byte information of the data to be transmitted under + * operating mode. + */ + +#define TWAI_TX_BYTE_8 0x000000FF +#define TWAI_TX_BYTE_8_M (TWAI_TX_BYTE_8_V << TWAI_TX_BYTE_8_S) +#define TWAI_TX_BYTE_8_V 0x000000FF +#define TWAI_TX_BYTE_8_S 0 + +/* TWAI_DATA_9_REG register + * Data register 9 + */ + +#define TWAI_DATA_9_REG (DR_REG_TWAI_BASE + 0x64) + +/* TWAI_TX_BYTE_9 : WO; bitpos: [7:0]; default: 0; + * Stored the 9th byte information of the data to be transmitted under + * operating mode. + */ + +#define TWAI_TX_BYTE_9 0x000000FF +#define TWAI_TX_BYTE_9_M (TWAI_TX_BYTE_9_V << TWAI_TX_BYTE_9_S) +#define TWAI_TX_BYTE_9_V 0x000000FF +#define TWAI_TX_BYTE_9_S 0 + +/* TWAI_DATA_10_REG register + * Data register 10 + */ + +#define TWAI_DATA_10_REG (DR_REG_TWAI_BASE + 0x68) + +/* TWAI_TX_BYTE_10 : WO; bitpos: [7:0]; default: 0; + * Stored the 10th byte information of the data to be transmitted under + * operating mode. + */ + +#define TWAI_TX_BYTE_10 0x000000FF +#define TWAI_TX_BYTE_10_M (TWAI_TX_BYTE_10_V << TWAI_TX_BYTE_10_S) +#define TWAI_TX_BYTE_10_V 0x000000FF +#define TWAI_TX_BYTE_10_S 0 + +/* TWAI_DATA_11_REG register + * Data register 11 + */ + +#define TWAI_DATA_11_REG (DR_REG_TWAI_BASE + 0x6c) + +/* TWAI_TX_BYTE_11 : WO; bitpos: [7:0]; default: 0; + * Stored the 11th byte information of the data to be transmitted under + * operating mode. + */ + +#define TWAI_TX_BYTE_11 0x000000FF +#define TWAI_TX_BYTE_11_M (TWAI_TX_BYTE_11_V << TWAI_TX_BYTE_11_S) +#define TWAI_TX_BYTE_11_V 0x000000FF +#define TWAI_TX_BYTE_11_S 0 + +/* TWAI_DATA_12_REG register + * Data register 12 + */ + +#define TWAI_DATA_12_REG (DR_REG_TWAI_BASE + 0x70) + +/* TWAI_TX_BYTE_12 : WO; bitpos: [7:0]; default: 0; + * Stored the 12th byte information of the data to be transmitted under + * operating mode. + */ + +#define TWAI_TX_BYTE_12 0x000000FF +#define TWAI_TX_BYTE_12_M (TWAI_TX_BYTE_12_V << TWAI_TX_BYTE_12_S) +#define TWAI_TX_BYTE_12_V 0x000000FF +#define TWAI_TX_BYTE_12_S 0 + +/* TWAI_RX_MESSAGE_CNT_REG register + * Receive Message Counter Register + */ + +#define TWAI_RX_MESSAGE_CNT_REG (DR_REG_TWAI_BASE + 0x74) + +/* TWAI_RX_MESSAGE_COUNTER : RO; bitpos: [6:0]; default: 0; + * This register reflects the number of messages available within the RX + * FIFO. + */ + +#define TWAI_RX_MESSAGE_COUNTER 0x0000007F +#define TWAI_RX_MESSAGE_COUNTER_M (TWAI_RX_MESSAGE_COUNTER_V << TWAI_RX_MESSAGE_COUNTER_S) +#define TWAI_RX_MESSAGE_COUNTER_V 0x0000007F +#define TWAI_RX_MESSAGE_COUNTER_S 0 + +/* TWAI_CLOCK_DIVIDER_REG register + * Clock Divider register + */ + +#define TWAI_CLOCK_DIVIDER_REG (DR_REG_TWAI_BASE + 0x7c) + +/* TWAI_CLOCK_OFF : RO | R/W; bitpos: [8]; default: 0; + * This bit can be configured under reset mode. 1: Disable the external + * CLKOUT pin; 0: Enable the external CLKOUT pin + */ + +#define TWAI_CLOCK_OFF (BIT(8)) +#define TWAI_CLOCK_OFF_M (TWAI_CLOCK_OFF_V << TWAI_CLOCK_OFF_S) +#define TWAI_CLOCK_OFF_V 0x00000001 +#define TWAI_CLOCK_OFF_S 8 + +/* TWAI_CD : R/W; bitpos: [7:0]; default: 0; + * These bits are used to configure frequency dividing coefficients of the + * external CLKOUT pin. + */ + +#define TWAI_CD 0x000000FF +#define TWAI_CD_M (TWAI_CD_V << TWAI_CD_S) +#define TWAI_CD_V 0x000000FF +#define TWAI_CD_S 0 + +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_TWAI_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_uart.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_uart.h similarity index 99% rename from arch/risc-v/src/esp32c3/hardware/esp32c3_uart.h rename to arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_uart.h index 511104ff11272..7aff24a06988f 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_uart.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_uart.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_uart.h + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_uart.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_UART_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_UART_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_UART_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_UART_H /**************************************************************************** * Included Files @@ -2203,4 +2203,4 @@ #define UART_UPDATE_V 0x1 #define UART_UPDATE_S 31 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_UART_H */ \ No newline at end of file +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_UART_H */ \ No newline at end of file diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_usb_serial_jtag.h b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_usb_serial_jtag.h similarity index 99% rename from arch/risc-v/src/esp32c3/hardware/esp32c3_usb_serial_jtag.h rename to arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_usb_serial_jtag.h index 3295e07fbf17e..b51a892e52bb6 100644 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_usb_serial_jtag.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_usb_serial_jtag.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_usb_serial_jtag.h + * arch/risc-v/src/esp32c3-legacy/hardware/esp32c3_usb_serial_jtag.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_USB_SERIAL_JTAG_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_USB_SERIAL_JTAG_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_USB_SERIAL_JTAG_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_USB_SERIAL_JTAG_H /**************************************************************************** * Included Files @@ -1230,4 +1230,4 @@ #define USB_SERIAL_JTAG_DATE_V 0xffffffff #define USB_SERIAL_JTAG_DATE_S 0 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_USB_SERIAL_JTAG_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_ESP32C3_USB_SERIAL_JTAG_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/extmem_reg.h b/arch/risc-v/src/esp32c3-legacy/hardware/extmem_reg.h similarity index 93% rename from arch/risc-v/src/esp32c3/hardware/extmem_reg.h rename to arch/risc-v/src/esp32c3-legacy/hardware/extmem_reg.h index 07d112ab6d861..dfd110ed6779a 100644 --- a/arch/risc-v/src/esp32c3/hardware/extmem_reg.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/extmem_reg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/extmem_reg.h + * arch/risc-v/src/esp32c3-legacy/hardware/extmem_reg.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_EXTMEM_REG_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_EXTMEM_REG_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_EXTMEM_REG_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_EXTMEM_REG_H /**************************************************************************** * Included Files @@ -87,4 +87,4 @@ #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x1 #define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_EXTMEM_REG_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_EXTMEM_REG_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/fe_reg.h b/arch/risc-v/src/esp32c3-legacy/hardware/fe_reg.h similarity index 88% rename from arch/risc-v/src/esp32c3/hardware/fe_reg.h rename to arch/risc-v/src/esp32c3-legacy/hardware/fe_reg.h index f65c3008e1f7f..629d418615bf2 100644 --- a/arch/risc-v/src/esp32c3/hardware/fe_reg.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/fe_reg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/fe_reg.h + * arch/risc-v/src/esp32c3-legacy/hardware/fe_reg.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_FE_REG_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_FE_REG_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_FE_REG_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_FE_REG_H /**************************************************************************** * Included Files @@ -47,4 +47,4 @@ #define FE2_TX_INF_FORCE_PU_V 1 #define FE2_TX_INF_FORCE_PU_S 10 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_FE_REG_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_FE_REG_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/nrx_reg.h b/arch/risc-v/src/esp32c3-legacy/hardware/nrx_reg.h similarity index 89% rename from arch/risc-v/src/esp32c3/hardware/nrx_reg.h rename to arch/risc-v/src/esp32c3-legacy/hardware/nrx_reg.h index e0fa09113268b..fd8998e562284 100644 --- a/arch/risc-v/src/esp32c3/hardware/nrx_reg.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/nrx_reg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/nrx_reg.h + * arch/risc-v/src/esp32c3-legacy/hardware/nrx_reg.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_NRX_REG_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_NRX_REG_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_NRX_REG_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_NRX_REG_H /**************************************************************************** * Included Files @@ -49,4 +49,4 @@ #define NRX_DEMAP_FORCE_PU_V 1 #define NRX_DEMAP_FORCE_PU_S 1 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_NRX_REG_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_NRX_REG_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/regi2c_bbpll.h b/arch/risc-v/src/esp32c3-legacy/hardware/regi2c_bbpll.h similarity index 90% rename from arch/risc-v/src/esp32c3/hardware/regi2c_bbpll.h rename to arch/risc-v/src/esp32c3-legacy/hardware/regi2c_bbpll.h index cd36f2692e3db..fdee8afa8ac13 100644 --- a/arch/risc-v/src/esp32c3/hardware/regi2c_bbpll.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/regi2c_bbpll.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/regi2c_bbpll.h + * arch/risc-v/src/esp32c3-legacy/hardware/regi2c_bbpll.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_BBPLL_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_BBPLL_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_REGI2C_BBPLL_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_REGI2C_BBPLL_H /**************************************************************************** * Pre-processor Definitions @@ -72,4 +72,4 @@ #define I2C_BBPLL_OC_DIV_7_0_MSB 7 #define I2C_BBPLL_OC_DIV_7_0_LSB 0 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_BBPLL_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_REGI2C_BBPLL_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/regi2c_brownout.h b/arch/risc-v/src/esp32c3-legacy/hardware/regi2c_brownout.h similarity index 81% rename from arch/risc-v/src/esp32c3/hardware/regi2c_brownout.h rename to arch/risc-v/src/esp32c3-legacy/hardware/regi2c_brownout.h index c5a832d5d5b97..bf186d61020cf 100644 --- a/arch/risc-v/src/esp32c3/hardware/regi2c_brownout.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/regi2c_brownout.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/regi2c_brownout.h + * arch/risc-v/src/esp32c3-legacy/hardware/regi2c_brownout.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_BROWNOUT_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_BROWNOUT_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_REGI2C_BROWNOUT_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_REGI2C_BROWNOUT_H #define I2C_BOD 0x61 #define I2C_BOD_HOSTID 0 @@ -28,4 +28,4 @@ #define I2C_BOD_THRESHOLD_MSB 2 #define I2C_BOD_THRESHOLD_LSB 0 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_BROWNOUT_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_REGI2C_BROWNOUT_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/regi2c_ctrl.h b/arch/risc-v/src/esp32c3-legacy/hardware/regi2c_ctrl.h similarity index 91% rename from arch/risc-v/src/esp32c3/hardware/regi2c_ctrl.h rename to arch/risc-v/src/esp32c3-legacy/hardware/regi2c_ctrl.h index 785ac470b2999..ca2cf03a768b0 100644 --- a/arch/risc-v/src/esp32c3/hardware/regi2c_ctrl.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/regi2c_ctrl.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/regi2c_ctrl.h + * arch/risc-v/src/esp32c3-legacy/hardware/regi2c_ctrl.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_CTRL_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_CTRL_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_REGI2C_CTRL_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_REGI2C_CTRL_H /**************************************************************************** * Included Files @@ -66,4 +66,4 @@ extern void rom_i2c_writereg_mask(uint8_t block, uint8_t host_id, #define REGI2C_READ(block, reg_add) \ rom_i2c_readreg(block, block##_HOSTID, reg_add) -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_CTRL_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_REGI2C_CTRL_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/regi2c_dig_reg.h b/arch/risc-v/src/esp32c3-legacy/hardware/regi2c_dig_reg.h similarity index 88% rename from arch/risc-v/src/esp32c3/hardware/regi2c_dig_reg.h rename to arch/risc-v/src/esp32c3-legacy/hardware/regi2c_dig_reg.h index 1ced0993e64b4..d4ed9b6dc592f 100644 --- a/arch/risc-v/src/esp32c3/hardware/regi2c_dig_reg.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/regi2c_dig_reg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/regi2c_dig_reg.h + * arch/risc-v/src/esp32c3-legacy/hardware/regi2c_dig_reg.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_DIG_REG_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_DIG_REG_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_REGI2C_DIG_REG_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_REGI2C_DIG_REG_H /**************************************************************************** * Pre-processor Definitions @@ -56,4 +56,4 @@ #define I2C_DIG_REG_XPD_DIG_REG_MSB 3 #define I2C_DIG_REG_XPD_DIG_REG_LSB 3 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_DIG_REG_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_REGI2C_DIG_REG_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/regi2c_lp_bias.h b/arch/risc-v/src/esp32c3-legacy/hardware/regi2c_lp_bias.h similarity index 88% rename from arch/risc-v/src/esp32c3/hardware/regi2c_lp_bias.h rename to arch/risc-v/src/esp32c3-legacy/hardware/regi2c_lp_bias.h index b0f16d124f61f..b887e8b9e7f71 100644 --- a/arch/risc-v/src/esp32c3/hardware/regi2c_lp_bias.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/regi2c_lp_bias.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/regi2c_lp_bias.h + * arch/risc-v/src/esp32c3-legacy/hardware/regi2c_lp_bias.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_LP_BIAS_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_LP_BIAS_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_REGI2C_LP_BIAS_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_REGI2C_LP_BIAS_H /**************************************************************************** * Pre-processor Definitions @@ -57,4 +57,4 @@ #define I2C_ULP_EXT_CODE_MSB 7 #define I2C_ULP_EXT_CODE_LSB 0 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_LP_BIAS_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_REGI2C_LP_BIAS_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/hardware/regi2c_saradc.h b/arch/risc-v/src/esp32c3-legacy/hardware/regi2c_saradc.h new file mode 100644 index 0000000000000..74518d97d590b --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/hardware/regi2c_saradc.h @@ -0,0 +1,51 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3-legacy/hardware/regi2c_saradc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_REGI2C_SARADC_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_REGI2C_SARADC_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register definitions for analog to calibrate initial code for getting a + * more precise voltage of SAR ADC. + */ + +#define I2C_ADC (0x69) +#define I2C_ADC_HOSTID (0) + +#define I2C_ADC1_ENCAL_GND (0x7) +#define I2C_ADC1_ENCAL_GND_MSB (0x5) +#define I2C_ADC1_ENCAL_GND_LSB (0x5) + +#define I2C_ADC1_INITVAL_L (0x0) +#define I2C_ADC1_INITVAL_L_MSB (0x7) +#define I2C_ADC1_INITVAL_L_LSB (0x0) + +#define I2C_ADC1_INITVAL_H (0x1) +#define I2C_ADC1_INITVAL_H_MSB (0x3) +#define I2C_ADC1_INITVAL_H_LSB (0x0) + +#define I2C_ADC1_DEF (0x2) +#define I2C_ADC1_DEF_MSB (0x6) +#define I2C_ADC1_DEF_LSB (0x4) + +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_REGI2C_SARADC_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/spi_mem_reg.h b/arch/risc-v/src/esp32c3-legacy/hardware/spi_mem_reg.h similarity index 87% rename from arch/risc-v/src/esp32c3/hardware/spi_mem_reg.h rename to arch/risc-v/src/esp32c3-legacy/hardware/spi_mem_reg.h index fe402b4020679..eff6f4504351c 100644 --- a/arch/risc-v/src/esp32c3/hardware/spi_mem_reg.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/spi_mem_reg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/spi_mem_reg.h + * arch/risc-v/src/esp32c3-legacy/hardware/spi_mem_reg.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_SPI_MEM_REG_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_SPI_MEM_REG_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_SPI_MEM_REG_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_SPI_MEM_REG_H /**************************************************************************** * Included Files @@ -43,4 +43,4 @@ #define SPI_MEM_CLK_EN_V 0x1 #define SPI_MEM_CLK_EN_S 0 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_SPI_MEM_REG_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_SPI_MEM_REG_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/wdev_reg.h b/arch/risc-v/src/esp32c3-legacy/hardware/wdev_reg.h similarity index 83% rename from arch/risc-v/src/esp32c3/hardware/wdev_reg.h rename to arch/risc-v/src/esp32c3-legacy/hardware/wdev_reg.h index a25d3ac2bbe88..3d50359cbc9c3 100644 --- a/arch/risc-v/src/esp32c3/hardware/wdev_reg.h +++ b/arch/risc-v/src/esp32c3-legacy/hardware/wdev_reg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/wdev_reg.h + * arch/risc-v/src/esp32c3-legacy/hardware/wdev_reg.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_WDEV_REG_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_WDEV_REG_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_WDEV_REG_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_WDEV_REG_H /**************************************************************************** * Included Files @@ -31,4 +31,4 @@ #define WDEV_RND_REG 0x600260b0 -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_WDEV_REG_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_HARDWARE_WDEV_REG_H */ diff --git a/arch/risc-v/src/esp32c3/rom/esp32c3_libc_stubs.h b/arch/risc-v/src/esp32c3-legacy/rom/esp32c3_libc_stubs.h similarity index 94% rename from arch/risc-v/src/esp32c3/rom/esp32c3_libc_stubs.h rename to arch/risc-v/src/esp32c3-legacy/rom/esp32c3_libc_stubs.h index d540acab44f42..47e9f844173e8 100644 --- a/arch/risc-v/src/esp32c3/rom/esp32c3_libc_stubs.h +++ b/arch/risc-v/src/esp32c3-legacy/rom/esp32c3_libc_stubs.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/risc-v/src/esp32c3/rom/esp32c3_libc_stubs.h + * arch/risc-v/src/esp32c3-legacy/rom/esp32c3_libc_stubs.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __ARCH_RISCV_SRC_ESP32C3_ROM_ESP32C3_LIBC_STUBS_H -#define __ARCH_RISCV_SRC_ESP32C3_ROM_ESP32C3_LIBC_STUBS_H +#ifndef __ARCH_RISCV_SRC_ESP32C3_LEGACY_ROM_ESP32C3_LIBC_STUBS_H +#define __ARCH_RISCV_SRC_ESP32C3_LEGACY_ROM_ESP32C3_LIBC_STUBS_H /**************************************************************************** * Included Files @@ -110,4 +110,4 @@ extern const struct syscall_stub_table *syscall_table_ptr; void setup_syscall_table(void); -#endif /* __ARCH_RISCV_SRC_ESP32C3_ROM_ESP32C3_LIBC_STUBS_H */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_LEGACY_ROM_ESP32C3_LIBC_STUBS_H */ diff --git a/arch/risc-v/src/esp32c3-legacy/rom/esp32c3_spiflash.h b/arch/risc-v/src/esp32c3-legacy/rom/esp32c3_spiflash.h new file mode 100644 index 0000000000000..0e015be6fe01a --- /dev/null +++ b/arch/risc-v/src/esp32c3-legacy/rom/esp32c3_spiflash.h @@ -0,0 +1,1017 @@ +/***************************************************************************** + * arch/risc-v/src/esp32c3-legacy/rom/esp32c3_spiflash.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + *****************************************************************************/ + +#ifndef _ROM_SPI_FLASH_H_ +#define _ROM_SPI_FLASH_H_ + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/***************************************************************************** + * Pre-processor Definitions + *****************************************************************************/ + +#define PERIPHS_SPI_FLASH_CMD SPI_CMD_REG(1) +#define PERIPHS_SPI_FLASH_ADDR SPI_ADDR_REG(1) +#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL_REG(1) +#define PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1_REG(1) +#define PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS_REG(1) +#define PERIPHS_SPI_FLASH_USRREG SPI_USER_REG(1) +#define PERIPHS_SPI_FLASH_USRREG1 SPI_USER1_REG(1) +#define PERIPHS_SPI_FLASH_USRREG2 SPI_USER2_REG(1) +#define PERIPHS_SPI_FLASH_C0 SPI_W0_REG(1) +#define PERIPHS_SPI_FLASH_C1 SPI_W1_REG(1) +#define PERIPHS_SPI_FLASH_C2 SPI_W2_REG(1) +#define PERIPHS_SPI_FLASH_C3 SPI_W3_REG(1) +#define PERIPHS_SPI_FLASH_C4 SPI_W4_REG(1) +#define PERIPHS_SPI_FLASH_C5 SPI_W5_REG(1) +#define PERIPHS_SPI_FLASH_C6 SPI_W6_REG(1) +#define PERIPHS_SPI_FLASH_C7 SPI_W7_REG(1) +#define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC_REG(1) + +#define SPI0_R_QIO_DUMMY_CYCLELEN 3 +#define SPI0_R_QIO_ADDR_BITSLEN 31 +#define SPI0_R_FAST_DUMMY_CYCLELEN 7 +#define SPI0_R_DIO_DUMMY_CYCLELEN 1 +#define SPI0_R_DIO_ADDR_BITSLEN 27 +#define SPI0_R_FAST_ADDR_BITSLEN 23 +#define SPI0_R_SIO_ADDR_BITSLEN 23 + +#define SPI1_R_QIO_DUMMY_CYCLELEN 3 +#define SPI1_R_QIO_ADDR_BITSLEN 31 +#define SPI1_R_FAST_DUMMY_CYCLELEN 7 +#define SPI1_R_DIO_DUMMY_CYCLELEN 3 +#define SPI1_R_DIO_ADDR_BITSLEN 31 +#define SPI1_R_FAST_ADDR_BITSLEN 23 +#define SPI1_R_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 + +#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_WRSR_2B + +/* SPI address register */ + +#define ESP_ROM_SPIFLASH_BYTES_LEN 24 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 64 +#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0x3f + +/* SPI status register */ + +#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 +#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 +#define ESP_ROM_SPIFLASH_BP0 BIT2 +#define ESP_ROM_SPIFLASH_BP1 BIT3 +#define ESP_ROM_SPIFLASH_BP2 BIT4 +#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|\ + ESP_ROM_SPIFLASH_BP1|\ + ESP_ROM_SPIFLASH_BP2) +#define ESP_ROM_SPIFLASH_QE BIT9 + +/* Extra dummy for flash read */ + +#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0 +#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M 1 +#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M 2 + +#define FLASH_ID_GD25LQ32C 0xC86016 + +/***************************************************************************** + * Public Types + *****************************************************************************/ + +typedef enum +{ + ESP_ROM_SPIFLASH_QIO_MODE = 0, + ESP_ROM_SPIFLASH_QOUT_MODE, + ESP_ROM_SPIFLASH_DIO_MODE, + ESP_ROM_SPIFLASH_DOUT_MODE, + ESP_ROM_SPIFLASH_FASTRD_MODE, + ESP_ROM_SPIFLASH_SLOWRD_MODE +} esp_rom_spiflash_read_mode_t; + +typedef enum +{ + ESP_ROM_SPIFLASH_RESULT_OK, + ESP_ROM_SPIFLASH_RESULT_ERR, + ESP_ROM_SPIFLASH_RESULT_TIMEOUT +} esp_rom_spiflash_result_t; + +typedef struct +{ + uint32_t device_id; + uint32_t chip_size; /* chip size in bytes */ + uint32_t block_size; + uint32_t sector_size; + uint32_t page_size; + uint32_t status_mask; +} esp32c3_spiflash_chip_t; + +typedef struct +{ + uint8_t data_length; + uint8_t read_cmd0; + uint8_t read_cmd1; + uint8_t write_cmd; + uint16_t data_mask; + uint16_t data; +} esp_rom_spiflash_common_cmd_t; + +/* Global ROM spiflash data, as used by legacy SPI flash functions */ + +struct spiflash_legacy_data_s +{ + esp32c3_spiflash_chip_t chip; + uint8_t dummy_len_plus[3]; + uint8_t sig_matrix; +}; + +/* Structure holding SPI flash access critical sections management functions. + * + * Flash API uses two types of functions for flash access management: + * 1) Functions which prepare/restore flash cache and interrupts before + * calling appropriate ROM functions (SPIWrite, SPIRead and + * SPIEraseBlock): + * - 'start' function should disable flash cache and non-IRAM interrupts + * and is invoked before the call to one of ROM functions from + * "struct spiflash_guard_funcs_s". + * - 'end' function should restore state of flash cache and non-IRAM + * interrupts and is invoked after the call to one of ROM + * functions from "struct spiflash_guard_funcs_s". + * These two functions are not reentrant. + * 2) Functions which synchronizes access to internal data used by flash API. + * These functions are mostly intended to synchronize access to flash API + * internal data in multithreaded environment and use OS primitives: + * - 'op_lock' locks access to flash API internal data. + * - 'op_unlock' unlocks access to flash API internal data. + * These two functions are reentrant and can be used around the outside of + * multiple calls to 'start' & 'end', in order to create atomic multi-part + * flash operations. + * + * Different versions of the guarding functions should be used depending on + * the context of execution (with or without functional OS). In normal + * conditions when flash API is called from task the functions use OS + * primitives. + * When there is no OS at all or when it is not guaranteed that OS is + * functional (accessing flash from exception handler) these functions cannot + * use OS primitives or even does not need them (multithreaded access is + * not possible). + * + * Note: Structure and corresponding guard functions should not reside + * in flash. For example structure can be placed in DRAM and functions + * in IRAM sections. + */ + +struct spiflash_guard_funcs +{ + void (*start)(void); /* critical section start function */ + void (*end)(void); /* critical section end function */ + void (*op_lock)(void); /* flash access API lock function */ + void (*op_unlock)(void); /* flash access API unlock function */ + + /* checks flash write addresses */ + + bool (*address_is_safe)(size_t addr, size_t size); + + void (*yield)(void); /* yield to the OS during flash erase */ +}; + +/***************************************************************************** + * Public Function Prototypes + *****************************************************************************/ + +/***************************************************************************** + * Name: esp_rom_spiflash_fix_dummylen + * + * Description: + * Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High + * Speed. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write). + * + * uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, + * 1 for 80M. + * + * Returned Value: + * None + * + *****************************************************************************/ + +void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); + +/***************************************************************************** + * Name: esp_rom_spiflash_select_qiomode + * + * Description: + * Select SPI Flash to QIO mode when WP pad is read from Flash. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint8_t wp_gpio_num: WP gpio number. + * + * uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, + * bit[23:18] spics0, bit[29:24] spihd + * + * Returned Value: + * None + *****************************************************************************/ + +void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, + uint32_t ishspi); + +/***************************************************************************** + * Name: esp_rom_spiflash_set_drvs + * + * Description: + * Set SPI Flash pad drivers. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint8_t wp_gpio_num: WP gpio number. + * + * uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, + * bit[23:18] spics0, bit[29:24] spihd + * + * uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, + * drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid + * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp. + * Values usually read from flash by rom code, function + * usually callde by rom code. + * if value with bit(3) set, the value is valid, bit[2:0] + * is the real value. + * + * Returned Value: + * None + * + *****************************************************************************/ + +void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, + uint32_t ishspi, + uint8_t *drvs); + +/***************************************************************************** + * Name: esp_rom_spiflash_select_padsfunc + * + * Description: + * Select SPI Flash function for pads. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, + * bit[23:18] spics0, bit[29:24] spihd + * + * Returned Value: + * None + * + *****************************************************************************/ + +void esp_rom_spiflash_select_padsfunc(uint32_t ishspi); + +/***************************************************************************** + * Name: esp_rom_spiflash_attach + * + * Description: + * SPI Flash init, clock divisor is 4, use 1 line Slow read mode. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping + * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, + * bit[23:18] spics0, bit[29:24] spihd + * + * uint8_t legacy: In legacy mode, more SPI command is used in line. + * + * Returned Value: + * None + * + *****************************************************************************/ + +void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); + +/***************************************************************************** + * Name: esp_rom_spiflash_read_status + * + * Description: + * SPI Read Flash status register. We use CMD 0x05 (RDSR). + * + * Please do not call this function in SDK. + * + * Input Parameters: + * esp32c3_spiflash_chip_t *spi : The information for Flash, which is + * exported from ld file. + * + * uint32_t *status : The pointer to which to return the Flash status value. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_read_status(esp32c3_spiflash_chip_t *spi, + uint32_t *status); + +/***************************************************************************** + * Name: esp32c3_spiflash_read_statushigh + * + * Description: + * SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). + * + * Please do not call this function in SDK. + * + * Input Parameters: + * esp32c3_spiflash_chip_t *spi : The information for Flash, which is + * exported from ld file. + * + * uint32_t *status : The pointer to which to return the Flash status value. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp32c3_spiflash_read_statushigh(esp32c3_spiflash_chip_t *spi, + uint32_t *status); + +/***************************************************************************** + * Name: esp32c3_spiflash_write_status + * + * Description: + * Write status to Falsh status register. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * esp32c3_spiflash_chip_t *spi : The information for Flash, which is + * exported from ld file. + * + * uint32_t status_value : Value to . + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp32c3_spiflash_write_status(esp32c3_spiflash_chip_t *spi, + uint32_t status_value); + +/***************************************************************************** + * Name: esp_rom_spiflash_read_user_cmd + * + * Description: + * Use a command to Read Flash status register. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * esp32c3_spiflash_chip_t *spi : The information for Flash, which is + * exported from ld file. + * + * uint32_t*status : The pointer to which to return the Flash status value. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_read_user_cmd(uint32_t *status, + uint8_t cmd); + +/***************************************************************************** + * Name: esp_rom_spiflash_config_readmode + * + * Description: + * Config SPI Flash read mode when init. + * + * Please do not call this function in SDK. + * + * Input Parameter: + * esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. + * + * This function does not try to set the QIO Enable bit in the status + * register, caller is responsible for this. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode); + +/***************************************************************************** + * Name: esp_rom_spiflash_config_clk + * + * Description: + * Config SPI Flash clock divisor. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint8_t freqdiv: clock divisor. + * + * uint8_t spi: 0 for SPI0, 1 for SPI1. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : config OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : config error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_config_clk(uint8_t freqdiv, + uint8_t spi); + +/***************************************************************************** + * Name: esp_rom_spiflash_common_cmd + * + * Description: + * Send CommonCmd to Flash so that is can go into QIO mode, some Flash use + * different CMD. + * + * Please do not call this function in SDK. + * + * Input Paramater: + * esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a + * command. + * + * Returned Value: + * uint16_t 0 : do not send command any more. + * 1 : go to the next command. + * n > 1 : skip (n - 1) commands. + * + *****************************************************************************/ + +uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd); + +/***************************************************************************** + * Name: esp_rom_spiflash_unlock + * + * Description: + * Unlock SPI write protect. + * + * Please do not call this function in SDK. + * + * Input Value: + * None. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); + +/***************************************************************************** + * Name: esp_rom_spiflash_lock + * + * Description: + * SPI write protect. + * + * Please do not call this function in SDK. + * + * Input Parameter: + * None. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Lock OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Lock error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t esp_rom_spiflash_lock(void); + +/***************************************************************************** + * Name: esp_rom_spiflash_config_param + * + * Description: + * Update SPI Flash parameter. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint32_t deviceId : Device ID read from SPI, the low 32 bit. + * + * uint32_t chip_size : The Flash size. + * + * uint32_t block_size : The Flash block size. + * + * uint32_t sector_size : The Flash sector size. + * + * uint32_t page_size : The Flash page size. + * + * uint32_t status_mask : The Mask used when read status from Flash + * (use single CMD). + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Update OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_config_param(uint32_t deviceid, + uint32_t chip_size, + uint32_t block_size, + uint32_t sector_size, + uint32_t page_size, + uint32_t status_mask); + +/***************************************************************************** + * Name: esp_rom_spiflash_erase_chip + * + * Description: + * Erase whole flash chip. + * + * Please do not call this function in SDK. + * + * Input Parameter: + * None + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); + +/***************************************************************************** + * Name: esp_rom_spiflash_erase_block + * + * Description: + * Erase a 64KB block of flash + * Uses SPI flash command D8H. + * + * Please do not call this function in SDK. + * + * Input Parameter: + * uint32_t block_num : Which block to erase. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num); + +/***************************************************************************** + * Name: esp_rom_spiflash_erase_sector + * + * Description: + * Erase a sector of flash. + * Uses SPI flash command 20H. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint32_t sector_num : Which sector to erase. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num); + +/***************************************************************************** + * Name: esp_rom_spiflash_erase_area + * + * Description: + * Erase some sectors. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint32_t start_addr : Start addr to erase, should be sector aligned. + * + * uint32_t area_len : Length to erase, should be sector aligned. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_erase_area(uint32_t start_addr, + uint32_t area_len); + +/***************************************************************************** + * Name: esp_rom_spiflash_write + * + * Description: + * Write Data to Flash, you should Erase it yourself if need. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint32_t dest_addr : Address to write, should be 4 bytes aligned. + * + * const uint32_t *src : The pointer to data which is to write. + * + * uint32_t len : Length to write, should be 4 bytes aligned. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Write OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_write(uint32_t dest_addr, + const uint32_t *src, + int32_t len); + +/***************************************************************************** + * Name: esp_rom_spiflash_read + * + * Description: + * Read Data from Flash, you should Erase it yourself if need. + * + * Please do not call this function in SDK. + * + * Input Values: + * uint32_t src_addr : Address to read, should be 4 bytes aligned. + * + * uint32_t *dest : The buf to read the data. + * + * uint32_t len : Length to read, should be 4 bytes aligned. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Read OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_read(uint32_t src_addr, + uint32_t *dest, + int32_t len); + +/***************************************************************************** + * Name: esp_rom_spiflash_write_encrypted_enable + * + * Description: + * SPI1 go into encrypto mode. + * + * Please do not call this function in SDK. + * + *****************************************************************************/ + +void esp_rom_spiflash_write_encrypted_enable(void); + +/***************************************************************************** + * Name: esp_rom_spiflash_prepare_encrypted_data + * + * Description: + * Prepare 32 Bytes data to encrpto writing, you should Erase it yourself + * if need. + * + * Please do not call this function in SDK. + * + * Input Parameters: + * uint32_t flash_addr : Address to write, should be 32 bytes aligned. + * + * uint32_t *data : The pointer to data which is to write. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. + * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, + uint32_t *data); + +/***************************************************************************** + * Name: esp_rom_spiflash_write_encrypted_disable + * + * Description: + * SPI1 go out of encrypto mode. + * + * Please do not call this function in SDK. + * + *****************************************************************************/ + +void esp_rom_spiflash_write_encrypted_disable(void); + +/***************************************************************************** + * Name: esp_rom_spiflash_write_encrypted + * + * Description: + * Write data to flash with transparent encryption. + * Sectors to be written should already be erased. + * Please do not call this function in SDK. + * + * Input Parameters: + * uint32_t flash_addr : Address to write, should be 32 byte aligned. + * + * uint32_t *data : The pointer to data to write. Note, this pointer must + * be 32 bit aligned and the content of the data will be + * modified by the encryption function. + * + * uint32_t len : Length to write, should be 32 bytes aligned. + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. + * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. + * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t +esp_rom_spiflash_write_encrypted(uint32_t flash_addr, + uint32_t *data, + uint32_t len); + +/***************************************************************************** + * Name: esp_rom_spiflash_wait_idle + * + * Description: + * Wait until SPI flash write operation is complete + * + * Please do not call this function in SDK. + * + * Reads the Write In Progress bit of the SPI flash status register, + * repeats until this bit is zero (indicating write complete). + * + * Returned Value: + * ESP_ROM_SPIFLASH_RESULT_OK : Write is complete + * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. + * + *****************************************************************************/ + +esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp32c3_spiflash_chip_t + *spi); + +/***************************************************************************** + * Name: esp_rom_spiflash_select_qio_pins + * + * Description: + * Enable Quad I/O pin functions + * + * Please do not call this function in SDK. + * + * Sets the HD & WP pin functions for Quad I/O modes, based on the + * efuse SPI pin configuration. + * + * Input Parameters: + * wp_gpio_num - Number of the WP pin to reconfigure for quad I/O. + * spiconfig - Pin configuration, as returned from + * ets_efuse_get_spiconfig(). + * - If this parameter is 0, default SPI pins are used and + * wp_gpio_num parameter is ignored. + * - If this parameter is 1, default HSPI pins are used and + * wp_gpio_num parameter is ignored. + * - For other values, this parameter encodes the HD pin number + * and also the CLK pin number. CLK pin selection is used to + * determine if HSPI or SPI peripheral will be used (use HSPI + * if CLK pin is the HSPI clock pin, otherwise use SPI). + * Both HD & WP pins are configured via GPIO matrix to map to the selected + * peripheral. + * + *****************************************************************************/ + +void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, + uint32_t spiconfig); + +/***************************************************************************** + * Name: spi_flash_guard_set + * + * Description: + * Sets guard functions to access flash. + * + * Input Parameters: + * funcs - funcs pointer to structure holding flash access guard functions + * + * Returned Value: + * None + * + *****************************************************************************/ + +void spi_flash_guard_set(const struct spiflash_guard_funcs *funcs); + +/***************************************************************************** + * Name: spi_flash_write_encrypted + * + * Description: + * Write data encrypted to Flash. + * + * Flash encryption must be enabled for this function to work. + * + * Flash encryption must be enabled when calling this function. + * If flash encryption is disabled, the function returns + * ESP_ERR_INVALID_STATE. Use esp_flash_encryption_enabled() + * function to determine if flash encryption is enabled. + * + * Both dest_addr and size must be multiples of 16 bytes. For + * absolute best performance, both dest_addr and size arguments should + * be multiples of 32 bytes. + * + * Input Parameters: + * dest_addr - Destination address in Flash. Must be a multiple of 16 + * bytes. + * src - Pointer to the source buffer. + * size - Length of data, in bytes. Must be a multiple of 16 bytes. + * + * Returned Values: + * Zero (OK) is returned or a negative error. + * + *****************************************************************************/ + +int spi_flash_write_encrypted(uint32_t dest_addr, const void *src, + uint32_t size); + +/***************************************************************************** + * Name: spi_flash_write + * + * Description: + * + * Write data to Flash. + * + * Note: For fastest write performance, write a 4 byte aligned size at a + * 4 byte aligned offset in flash from a source buffer in DRAM. Varying + * any of these parameters will still work, but will be slower due to + * buffering. + * + * Writing more than 8KB at a time will be split into multiple + * write operations to avoid disrupting other tasks in the system. + * + * Parameters: + * dest_addr - Destination address in Flash. + * src - Pointer to the source buffer. + * size - Length of data, in bytes. + * + * Returned Values: + * Zero (OK) is returned or a negative error. + * + *****************************************************************************/ + +int spi_flash_write(uint32_t dest_addr, const void *src, uint32_t size); + +/***************************************************************************** + * Name: spi_flash_read + * + * Description: + * Read data from Flash. + * + * Note: For fastest read performance, all parameters should be + * 4 byte aligned. If source address and read size are not 4 byte + * aligned, read may be split into multiple flash operations. If + * destination buffer is not 4 byte aligned, a temporary buffer will + * be allocated on the stack. + * + * Reading more than 16KB of data at a time will be split + * into multiple reads to avoid disruption to other tasks in the + * system. Consider using spi_flash_mmap() to read large amounts + * of data. + * + * Parameters: + * src_addr - source address of the data in Flash. + * dest - pointer to the destination buffer + * size - length of data + * + * Returned Values: + * Zero (OK) is returned or a negative error. + * + *****************************************************************************/ + +int spi_flash_read(uint32_t src_addr, void *dest, uint32_t size); + +/***************************************************************************** + * Name: spi_flash_erase_sector + * + * Description: + * Erase the Flash sector. + * + * Parameters: + * sector - Sector number, the count starts at sector 0, 4KB per sector. + * + * Returned Values: esp_err_t + * Zero (OK) is returned or a negative error. + * + *****************************************************************************/ + +int spi_flash_erase_sector(uint32_t sector); + +/***************************************************************************** + * Name: spi_flash_erase_range + * + * Description: + * Erase a range of flash sectors + * + * Parameters: + * start_address - Address where erase operation has to start. + * Must be 4kB-aligned + * size - Size of erased range, in bytes. Must be divisible by + * 4kB. + * + * Returned Values: + * Zero (OK) is returned or a negative error. + * + *****************************************************************************/ + +int spi_flash_erase_range(uint32_t start_address, uint32_t size); + +/***************************************************************************** + * Name: spi_flash_cache_enabled + * + * Description: + * Check at runtime if flash cache is enabled on both CPUs. + * + * Returned Values: + * Return true if both CPUs have flash cache enabled, false otherwise. + * + *****************************************************************************/ + +bool spi_flash_cache_enabled(void); + +/***************************************************************************** + * Name: spi_flash_enable_cache + * + * Description: + * Re-enable cache for the core defined as cpuid parameter. + * + * Parameters: + * cpuid - core number to enable instruction cache for. + * + *****************************************************************************/ + +void spi_flash_enable_cache(uint32_t cpuid); + +/***************************************************************************** + * Public Data + *****************************************************************************/ + +extern const struct spiflash_legacy_data_s *rom_spiflash_legacy_data; + +#ifdef __cplusplus +} +#endif + +#endif /* _ROM_SPI_FLASH_H_ */ diff --git a/arch/risc-v/src/esp32c3/.gitignore b/arch/risc-v/src/esp32c3/.gitignore index 9adccd80ae6d7..d40b86f3a0dce 100644 --- a/arch/risc-v/src/esp32c3/.gitignore +++ b/arch/risc-v/src/esp32c3/.gitignore @@ -1,3 +1,4 @@ -/esp-wireless-drivers-3rdparty +/bootloader /esp-nuttx-bootloader /*.zip +/esp-hal-3rdparty diff --git a/arch/risc-v/src/esp32c3/Bootloader.mk b/arch/risc-v/src/esp32c3/Bootloader.mk deleted file mode 100644 index bd81934dda469..0000000000000 --- a/arch/risc-v/src/esp32c3/Bootloader.mk +++ /dev/null @@ -1,188 +0,0 @@ -############################################################################ -# arch/risc-v/src/esp32c3/Bootloader.mk -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -ifeq ($(CONFIG_ESP32C3_BOOTLOADER_BUILD_FROM_SOURCE),y) - -CHIPDIR = $(TOPDIR)/arch/risc-v/src/chip - -BOOTLOADER_SRCDIR = $(CHIPDIR)/esp-nuttx-bootloader -BOOTLOADER_VERSION = main -BOOTLOADER_URL = https://github.com/espressif/esp-nuttx-bootloader -BOOTLOADER_OUTDIR = out -BOOTLOADER_CONFIG = $(CHIPDIR)/bootloader.conf - -$(BOOTLOADER_SRCDIR): - $(Q) git clone $(BOOTLOADER_URL) $(BOOTLOADER_SRCDIR) -b $(BOOTLOADER_VERSION) - -# Helpers for creating the configuration file - -cfg_en = echo "$(1)=$(if $(CONFIG_ESP32C3_APP_FORMAT_MCUBOOT),1,y)"; -cfg_dis = echo "$(1)=$(if $(CONFIG_ESP32C3_APP_FORMAT_MCUBOOT),0,n)"; -cfg_val = echo "$(1)=$(2)"; - -# Commands for colored and formatted output - -RED = \033[1;31m -YELLOW = \033[1;33m -BOLD = \033[1m -RST = \033[0m - -$(BOOTLOADER_CONFIG): $(TOPDIR)/.config -ifeq ($(CONFIG_ESP32C3_SECURE_BOOT),y) - $(Q) if [ -z "$(ESPSEC_KEYDIR)" ]; then \ - echo ""; \ - echo "$(RED)bootloader error:$(RST) Missing argument for secure boot keys directory."; \ - echo "USAGE: make bootloader ESPSEC_KEYDIR="; \ - echo ""; \ - exit 1; \ - fi -endif - $(Q) echo "Creating Bootloader configuration" - $(Q) { \ - $(if $(CONFIG_ESP32C3_FLASH_2M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_2MB)) \ - $(if $(CONFIG_ESP32C3_FLASH_4M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_4MB)) \ - $(if $(CONFIG_ESP32C3_FLASH_8M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_8MB)) \ - $(if $(CONFIG_ESP32C3_FLASH_16M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_16MB)) \ - $(if $(CONFIG_ESP32C3_FLASH_MODE_DIO),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_DIO)) \ - $(if $(CONFIG_ESP32C3_FLASH_MODE_DOUT),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_DOUT)) \ - $(if $(CONFIG_ESP32C3_FLASH_MODE_QIO),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_QIO)) \ - $(if $(CONFIG_ESP32C3_FLASH_MODE_QOUT),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_QOUT)) \ - $(if $(CONFIG_ESP32C3_FLASH_FREQ_80M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_80M)) \ - $(if $(CONFIG_ESP32C3_FLASH_FREQ_40M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_40M)) \ - $(if $(CONFIG_ESP32C3_FLASH_FREQ_26M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_26M)) \ - $(if $(CONFIG_ESP32C3_FLASH_FREQ_20M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_20M)) \ - } > $(BOOTLOADER_CONFIG) -ifeq ($(CONFIG_ESP32C3_APP_FORMAT_MCUBOOT),y) - $(Q) { \ - $(if $(CONFIG_ESP32C3_SECURE_BOOT),$(call cfg_en,CONFIG_SECURE_BOOT)$(call cfg_en,CONFIG_SECURE_BOOT_V2_ENABLED)$(call cfg_val,CONFIG_ESP_SIGN_KEY_FILE,$(abspath $(TOPDIR)/$(ESPSEC_KEYDIR)/$(subst ",,$(CONFIG_ESP32C3_SECURE_BOOT_APP_SIGNING_KEY))))) \ - $(if $(CONFIG_ESP32C3_SECURE_SIGNED_APPS_SCHEME_RSA_2048),$(call cfg_en,CONFIG_ESP_USE_MBEDTLS)$(call cfg_en,CONFIG_ESP_SIGN_RSA)$(call cfg_val,CONFIG_ESP_SIGN_RSA_LEN,2048)) \ - $(if $(CONFIG_ESP32C3_SECURE_SIGNED_APPS_SCHEME_RSA_3072),$(call cfg_en,CONFIG_ESP_USE_MBEDTLS)$(call cfg_en,CONFIG_ESP_SIGN_RSA)$(call cfg_val,CONFIG_ESP_SIGN_RSA_LEN,3072)) \ - $(if $(CONFIG_ESP32C3_SECURE_SIGNED_APPS_SCHEME_ECDSA_P256),$(call cfg_en,CONFIG_ESP_USE_TINYCRYPT)$(call cfg_en,CONFIG_ESP_SIGN_EC256)) \ - $(if $(CONFIG_ESP32C3_SECURE_SIGNED_APPS_SCHEME_ED25519),$(call cfg_en,CONFIG_ESP_USE_TINYCRYPT)$(call cfg_en,CONFIG_ESP_SIGN_ED25519)) \ - $(if $(CONFIG_ESP32C3_SECURE_BOOT_ALLOW_JTAG),$(call cfg_en,CONFIG_SECURE_BOOT_ALLOW_JTAG)) \ - $(if $(CONFIG_ESP32C3_SECURE_BOOT_ALLOW_EFUSE_RD_DIS),$(call cfg_en,CONFIG_SECURE_BOOT_V2_ALLOW_EFUSE_RD_DIS)) \ - $(if $(CONFIG_ESP32C3_SECURE_DISABLE_ROM_DL_MODE),$(call cfg_en,CONFIG_SECURE_DISABLE_ROM_DL_MODE)) \ - $(if $(CONFIG_ESP32C3_SECURE_ENABLE_SECURE_ROM_DL_MODE),$(call cfg_en,CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE)) \ - $(if $(CONFIG_ESP32C3_SECURE_INSECURE_ALLOW_DL_MODE),$(call cfg_en,CONFIG_SECURE_INSECURE_ALLOW_DL_MODE)) \ - $(if $(CONFIG_ESP32C3_SECURE_FLASH_ENC_ENABLED),$(call cfg_en,CONFIG_SECURE_FLASH_ENC_ENABLED)) \ - $(if $(CONFIG_ESP32C3_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT),$(call cfg_en,CONFIG_SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT)) \ - $(if $(CONFIG_ESP32C3_SECURE_FLASH_ENCRYPTION_MODE_RELEASE),$(call cfg_en,CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE)) \ - $(if $(CONFIG_ESP32C3_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC),$(call cfg_en,CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC)) \ - $(if $(CONFIG_ESP32C3_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE),$(call cfg_en,CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_CACHE)) \ - $(if $(CONFIG_ESP32C3_SECURE_FLASH_REQUIRE_ALREADY_ENABLED),$(call cfg_en,CONFIG_SECURE_FLASH_REQUIRE_ALREADY_ENABLED)) \ - $(call cfg_val,CONFIG_ESP_BOOTLOADER_SIZE,0xF000) \ - $(call cfg_val,CONFIG_ESP_APPLICATION_PRIMARY_START_ADDRESS,$(CONFIG_ESP32C3_OTA_PRIMARY_SLOT_OFFSET)) \ - $(call cfg_val,CONFIG_ESP_APPLICATION_SIZE,$(CONFIG_ESP32C3_OTA_SLOT_SIZE)) \ - $(call cfg_val,CONFIG_ESP_APPLICATION_SECONDARY_START_ADDRESS,$(CONFIG_ESP32C3_OTA_SECONDARY_SLOT_OFFSET)) \ - $(call cfg_en,CONFIG_ESP_MCUBOOT_WDT_ENABLE) \ - $(call cfg_val,CONFIG_ESP_SCRATCH_OFFSET,$(CONFIG_ESP32C3_OTA_SCRATCH_OFFSET)) \ - $(call cfg_val,CONFIG_ESP_SCRATCH_SIZE,$(CONFIG_ESP32C3_OTA_SCRATCH_SIZE)) \ - } >> $(BOOTLOADER_CONFIG) -else ifeq ($(CONFIG_ESP32C3_APP_FORMAT_LEGACY),y) - $(Q) { \ - $(call cfg_dis,CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE) \ - $(call cfg_en,CONFIG_PARTITION_TABLE_CUSTOM) \ - $(call cfg_val,CONFIG_PARTITION_TABLE_CUSTOM_FILENAME,\"partitions.csv\") \ - $(call cfg_val,CONFIG_PARTITION_TABLE_OFFSET,$(CONFIG_ESP32C3_PARTITION_TABLE_OFFSET)) \ - } >> $(BOOTLOADER_CONFIG) -endif - -ifeq ($(CONFIG_ESP32C3_APP_FORMAT_MCUBOOT),y) - -BOOTLOADER_BIN = $(TOPDIR)/mcuboot-esp32c3.bin -BOOTLOADER_SIGNED_BIN = $(TOPDIR)/mcuboot-esp32c3.signed.bin - -$(BOOTLOADER_BIN): $(BOOTLOADER_CONFIG) - $(Q) echo "Building Bootloader" - $(Q) $(BOOTLOADER_SRCDIR)/build_mcuboot.sh -c esp32c3 -s -f $(BOOTLOADER_CONFIG) - $(call COPYFILE, $(BOOTLOADER_SRCDIR)/$(BOOTLOADER_OUTDIR)/mcuboot-esp32c3.bin, $(TOPDIR)) - -bootloader: $(BOOTLOADER_CONFIG) $(BOOTLOADER_SRCDIR) $(BOOTLOADER_BIN) -ifeq ($(CONFIG_ESP32C3_SECURE_BOOT),y) - $(eval KEYDIR := $(TOPDIR)/$(ESPSEC_KEYDIR)) - $(eval BOOTLOADER_SIGN_KEY := $(abspath $(KEYDIR)/$(subst ",,$(CONFIG_ESP32C3_SECURE_BOOT_BOOTLOADER_SIGNING_KEY)))) -ifeq ($(CONFIG_ESP32C3_SECURE_BOOT_BUILD_SIGNED_BINARIES),y) - $(Q) if [ ! -f "$(BOOTLOADER_SIGN_KEY)" ]; then \ - echo ""; \ - echo "$(RED)bootloader error:$(RST) Bootloader signing key $(BOLD)$(CONFIG_ESP32C3_SECURE_BOOT_BOOTLOADER_SIGNING_KEY)$(RST) does not exist."; \ - echo "Generate using:"; \ - echo " espsecure.py generate_signing_key --version 2 $(CONFIG_ESP32C3_SECURE_BOOT_BOOTLOADER_SIGNING_KEY)"; \ - echo ""; \ - exit 1; \ - fi - $(Q) echo "Signing Bootloader" - espsecure.py sign_data --version 2 --keyfile $(BOOTLOADER_SIGN_KEY) -o $(BOOTLOADER_SIGNED_BIN) $(BOOTLOADER_BIN) -else - $(Q) echo "" - $(Q) echo "$(YELLOW)Bootloader not signed. Sign the bootloader before flashing.$(RST)" - $(Q) echo "To sign the bootloader, you can use this command:" - $(Q) echo " espsecure.py sign_data --version 2 --keyfile $(BOOTLOADER_SIGN_KEY) -o mcuboot-esp32c3.signed.bin mcuboot-esp32c3.bin" - $(Q) echo "" -endif -endif - -clean_bootloader: - $(call DELDIR,$(BOOTLOADER_SRCDIR)) - $(call DELFILE,$(BOOTLOADER_CONFIG)) - $(call DELFILE,$(BOOTLOADER_BIN)) - $(if $(CONFIG_ESP32C3_SECURE_BOOT_BUILD_SIGNED_BINARIES),$(call DELFILE,$(BOOTLOADER_SIGNED_BIN))) - -else ifeq ($(CONFIG_ESP32C3_APP_FORMAT_LEGACY),y) - -bootloader: $(BOOTLOADER_SRCDIR) $(BOOTLOADER_CONFIG) - $(Q) echo "Building Bootloader binaries" - $(Q) $(BOOTLOADER_SRCDIR)/build_idfboot.sh -c esp32c3 -s -f $(BOOTLOADER_CONFIG) - $(call COPYFILE,$(BOOTLOADER_SRCDIR)/$(BOOTLOADER_OUTDIR)/bootloader-esp32c3.bin,$(TOPDIR)) - $(call COPYFILE,$(BOOTLOADER_SRCDIR)/$(BOOTLOADER_OUTDIR)/partition-table-esp32c3.bin,$(TOPDIR)) - -clean_bootloader: - $(call DELDIR,$(BOOTLOADER_SRCDIR)) - $(call DELFILE,$(BOOTLOADER_CONFIG)) - $(call DELFILE,$(TOPDIR)/bootloader-esp32c3.bin) - $(call DELFILE,$(TOPDIR)/partition-table-esp32c3.bin) - -endif - -else ifeq ($(CONFIG_ESP32C3_BOOTLOADER_DOWNLOAD_PREBUILT),y) - -BOOTLOADER_VERSION = latest -BOOTLOADER_URL = https://github.com/espressif/esp-nuttx-bootloader/releases/download/$(BOOTLOADER_VERSION) - -ifeq ($(CONFIG_ESP32C3_APP_FORMAT_MCUBOOT),y) - -bootloader: - $(call DOWNLOAD,$(BOOTLOADER_URL),mcuboot-esp32c3.bin,$(TOPDIR)/mcuboot-esp32c3.bin) - -clean_bootloader: - $(call DELFILE,$(TOPDIR)/mcuboot-esp32c3.bin) - -else ifeq ($(CONFIG_ESP32C3_APP_FORMAT_LEGACY),y) - -bootloader: - $(call DOWNLOAD,$(BOOTLOADER_URL),bootloader-esp32c3.bin,$(TOPDIR)/bootloader-esp32c3.bin) - $(call DOWNLOAD,$(BOOTLOADER_URL),partition-table-esp32c3.bin,$(TOPDIR)/partition-table-esp32c3.bin) - -clean_bootloader: - $(call DELFILE,$(TOPDIR)/bootloader-esp32c3.bin) - $(call DELFILE,$(TOPDIR)/partition-table-esp32c3.bin) - -endif - -endif diff --git a/arch/risc-v/src/esp32c3/Kconfig b/arch/risc-v/src/esp32c3/Kconfig index a8b1caa8f36e5..03dbd9ddf2ac6 100644 --- a/arch/risc-v/src/esp32c3/Kconfig +++ b/arch/risc-v/src/esp32c3/Kconfig @@ -3,1178 +3,8 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -if ARCH_CHIP_ESP32C3 +if ARCH_CHIP_ESP32C3_GENERIC -comment "ESP32-C3 Configuration Options" +source "arch/risc-v/src/common/espressif/Kconfig" -choice - prompt "ESP32-C3 Chip Selection" - default ARCH_CHIP_ESP32C3WROOM02 - -config ARCH_CHIP_ESP32C3X - bool "ESP32-C3" - select ESP32C3_ESP32C3XXX - ---help--- - ESP32-C3 chip with a single RISC-V IMC core, no embedded Flash memory - -config ARCH_CHIP_ESP32C3FX4 - bool "ESP32-C3Fx4" - select ESP32C3_ESP32C3XXX - select ESP32C3_FLASH_4M - ---help--- - ESP32-C3 chip with a single RISC-V IMC core, 4 MB of in-package Flash memory - -config ARCH_CHIP_ESP32C3MINI1 - bool "ESP32-C3-MINI-1" - select ESP32C3_ESP32C3XXX - select ESP32C3_FLASH_4M - ---help--- - Generic module with an embedded ESP32-C3Fx4 chip - -config ARCH_CHIP_ESP32C3WROOM02 - bool "ESP32-C3-WROOM-02" - select ESP32C3_ESP32C3XXX - select ESP32C3_FLASH_4M - ---help--- - Generic module with an embedded ESP32-C3 chip, 4 MB of Flash memory - -endchoice # ESP32-C3 Chip Selection - -config ESP32C3_SINGLE_CPU - bool - default n - -config ESP32C3_DUAL_CPU - bool - default n - -config ESP32C3_ESP32C3XXX - bool - default n - select ESP32C3_SINGLE_CPU - select ARCH_HAVE_I2CRESET - -config ESP32C3_FLASH_2M - bool - default n - -config ESP32C3_FLASH_4M - bool - default n - -config ESP32C3_FLASH_8M - bool - default n - -config ESP32C3_FLASH_16M - bool - default n - -config ESP32C3_ESPTOOLPY_NO_STUB - bool "Disable download stub" - default n - ---help--- - The flasher tool sends a precompiled download stub first by default. - That stub allows things like compressed downloads and more. - Usually you should not need to disable that feature. - It is only required to be disabled in certain scenarios when either - Secure Boot V2 or Flash Encryption is enabled. - -config ESP32C3_FLASH_DETECT - bool "Auto-detect FLASH size" - default n - ---help--- - Auto detect flash size when flashing. - -choice ESP32C3_CPU_FREQ - prompt "CPU frequency" - default ESP32C3_CPU_FREQ_160 - ---help--- - CPU frequency to be set on application startup. - -config ESP32C3_CPU_FREQ_40 - bool "40 MHz" - ---help--- - Set the CPU to 40 MHz. This frequency is obtained from the XTAL. - -config ESP32C3_CPU_FREQ_80 - bool "80 MHz" - ---help--- - Set the CPU to 80 MHz. This frequency is obtained from the 480 MHz PLL. - -config ESP32C3_CPU_FREQ_160 - bool "160 MHz" - ---help--- - Set the CPU to 160 MHz. This frequency is obtained from the 480 MHz PLL. - -endchoice # ESP32C3_CPU_FREQ - -config ESP32C3_CPU_FREQ_MHZ - int - default 40 if ESP32C3_CPU_FREQ_40 - default 80 if ESP32C3_CPU_FREQ_80 - default 160 if ESP32C3_CPU_FREQ_160 - -config ESP32C3_REGION_PROTECTION - bool "Enable region protection" - default y - select ARCH_USE_MPU - ---help--- - Configure the MPU to disable access to invalid memory regions. - -config ESP32C3_RT_TIMER - bool "Real-time Timer" - default n - select ESP32C3_TIMER - ---help--- - Real-time Timer is relying upon the Systimer 1. - -config ESP32C3_RTC_HEAP - bool "Use the RTC memory as a separate heap" - select ARCH_HAVE_EXTRA_HEAPS - default n - -config ESP32C3_EXCEPTION_ENABLE_CACHE - bool - default y - depends on ESP32C3_SPIFLASH - ---help--- - When exception triggers, panic function enables SPI Flash cache to - let functions be able to call functions which locate in SPI Flash. - -menu "ESP32-C3 Peripheral Support" - -config ESP32C3_ADC - bool - default n - select ANALOG - select ADC - -config ESP32C3_UART - bool - default n - -config ESP32C3_I2C - bool - default n - -config ESP32C3_TWAI - bool - default n - select CAN - -config ESP32C3_TIMER - bool - default n - -config ESP32C3_WDT - bool - default n - -config ESP32C3_EFUSE - bool "EFUSE support" - default n - ---help--- - Enable ESP32-C3 efuse support. - -config ESP32C3_SPI - bool - default n - -config ESP32C3_LEDC - bool "LEDC (PWM)" - default n - select PWM - select ARCH_HAVE_PWM_MULTICHAN - -config ESP32C3_GPIO_IRQ - bool "GPIO pin interrupts" - default n - ---help--- - Enable support for interrupting GPIO pins - -config ESP32C3_RTCIO_IRQ - bool "RTC IO interrupts" - default n - ---help--- - Enable support for RTC peripherals interrupts. - -config ESP32C3_UART0 - bool "UART0" - default y - select ESP32C3_UART - select UART0_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - -config ESP32C3_UART1 - bool "UART1" - default n - select ESP32C3_UART - select UART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - -config ESP32C3_USBSERIAL - bool "USB-Serial Driver" - default n - select OTHER_UART_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - -config ESP32C3_I2C0 - bool "I2C 0" - default n - select ESP32C3_I2C - -config ESP32C3_TWAI0 - bool "TWAI (CAN) 0" - default n - select ESP32C3_TWAI - -config ESP32C3_RNG - bool "Random Number Generator (RNG)" - default n - select ARCH_HAVE_RNG - ---help--- - ESP32-C3 supports an RNG that passed on Dieharder test suite. - -config ESP32C3_TIMER0 - bool "54-bit Timer 0 (Group 0 Timer 0)" - default n - select ESP32C3_TIMER - ---help--- - Enables Timer 0 - -config ESP32C3_TIMER1 - bool "54-bit Timer 0 (Group 1 Timer 0)" - default n - select ESP32C3_TIMER - ---help--- - Enables Timer 1 - -config ESP32C3_SPIFLASH - bool "SPI Flash" - default n - -config ESP32C3_SPI2 - bool "SPI 2" - default n - select ESP32C3_SPI - select SPI - -config ESP32C3_DMA - bool "General DMA (GDMA)" - default n - select ARCH_DMA - -config ESP32C3_MWDT0 - bool "Main System Watchdog Timer (Group 0)" - default n - select ESP32C3_WDT - ---help--- - Includes MWDT0. This watchdog timer is part of the Group 0 - timer submodule. - -config ESP32C3_MWDT1 - bool "Main System Watchdog Timer (Group 1)" - default n - select ESP32C3_WDT - ---help--- - Includes MWDT1. This watchdog timer is part of the Group 0 - timer submodule. - -config ESP32C3_RWDT - bool "RTC Watchdog Timer" - default n - select ESP32C3_WDT - select ESP32C3_RTCIO_IRQ - ---help--- - Includes RWDT. This watchdog timer is from the RTC module. - When it is selected, if the developer sets it to reset on expiration - it will reset Main System and the RTC module. If you don't want - to have the RTC module reset, please, use the Timers' Module WDTs. - They will only reset Main System. - -config ESP32C3_ADC1 - bool "ADC1" - default n - select ESP32C3_ADC - -config ESP32C3_WIRELESS - bool - default n - select NET - select ARCH_PHY_INTERRUPT - select ESP32C3_RT_TIMER - ---help--- - Enable Wireless support - -config ESP32C3_AES_ACCELERATOR - bool "AES Accelerator" - default n -config ESP32C3_SHA_ACCELERATOR - bool "SHA Accelerator" - default n - ---help--- - Enable ESP32-C3 SHA accelerator support. - -config ESP32C3_BIGNUM_ACCELERATOR - bool "BIGNUM Accelerator" - default n - ---help--- - Enable ESP32-C3 BIGNUM accelerator support. - -config ESP32C3_RSA_ACCELERATOR - bool "RSA Accelerator" - default n - ---help--- - Enable ESP32-C3 RSA accelerator support. - -config ESP32C3_WIFI - bool "Wi-Fi" - default n - select ESP32C3_WIRELESS - ---help--- - Enable Wi-Fi support - -config ESP32C3_BLE - bool "BLE" - default n - select ESP32C3_WIRELESS - ---help--- - Enable BLE support - -config ESP32C3_BROWNOUT_DET - bool "Brownout Detect" - default y - ---help--- - The ESP32-C3 has a built-in brownout detector which can detect if the voltage is lower than - a specific value. If this happens, it will reset the chip in order to prevent unintended - behaviour. - -endmenu # ESP32-C3 Peripheral Support - -menuconfig ESP32C3_WIFI_BT_COEXIST - bool "Wi-Fi and BT coexist" - default n - depends on ESP32C3_WIFI && ESP32C3_BLE - -menu "I2C Configuration" - depends on ESP32C3_I2C - -if ESP32C3_I2C0 - -config ESP32C3_I2C0_SCLPIN - int "I2C0 SCL Pin" - default 6 - range 0 21 - -config ESP32C3_I2C0_SDAPIN - int "I2C0 SDA Pin" - default 5 - range 0 21 - -endif # ESP32C3_I2C0 - -config ESP32C3_I2CTIMEOSEC - int "Timeout seconds" - default 0 - -config ESP32C3_I2CTIMEOMS - int "Timeout milliseconds" - default 500 - -endmenu # I2C configuration - -menu "TWAI driver options" - depends on ESP32C3_TWAI - -if ESP32C3_TWAI0 - -config ESP32C3_TWAI0_TXPIN - int "TWAI0 TX Pin" - default 2 - -config ESP32C3_TWAI0_RXPIN - int "TWAI0 RX Pin" - default 3 - -config ESP32C3_TWAI0_BITRATE - int "TWAI0 bitrate" - default 1000000 - ---help--- - TWAI0 bit rate. Required if ESP32C3_TWAI0 is defined. - -config ESP32C3_TWAI0_SAMPLEP - int "TWAI0 sample point" - default 80 - ---help--- - TWAI0 sample point location as a percent value. Required - if ESP32C3_TWAI0 is defined. - -config ESP32C3_TWAI0_SJW - int "TWAI0 synchronization jump width" - default 3 - ---help--- - SJW limits the number of Time Quanta corrections during bit - Resynchronization. Default: 3 - -config ESP32C3_TWAI0_SAM - bool "TWAI0 sampling" - default n - ---help--- - The bus is sampled 3 times (recommended for low to medium speed buses - to spikes on the bus-line). - -endif # ESP32C3_TWAI0 - -config ESP32C3_TWAI_REGDEBUG - bool "TWAI register level debug" - depends on DEBUG_CAN_INFO - default n - ---help--- - Output detailed register-level TWAI debug information. Requires also - CONFIG_DEBUG_CAN_INFO. - -endmenu #ESP32C3_TWAI - -menu "SPI configuration" - depends on ESP32C3_SPI - -config ESP32C3_SPI_SWCS - bool "SPI software CS" - default n - ---help--- - Use SPI software CS. - -config ESP32C3_SPI_UDCS - bool "User defined CS" - default n - depends on ESP32C3_SPI_SWCS - ---help--- - Use user-defined CS. - -if ESP32C3_SPI2 - -config ESP32C3_SPI2_SLAVE - bool "SPI2 Slave mode" - default n - depends on SPI_SLAVE - select ESP32C3_GPIO_IRQ - ---help--- - Configure SPI2 to operate in Slave mode. - -config ESP32C3_SPI2_DMA - bool "SPI2 use GDMA" - default n - depends on ESP32C3_DMA - ---help--- - Enable support for transfers using the GDMA engine. - -config ESP32C3_SPI2_DMADESC_NUM - int "SPI2 Master GDMA maximum number of descriptors" - default 2 - depends on ESP32C3_SPI2_DMA - ---help--- - Configure the maximum number of out-link/in-link descriptors to - be chained for a GDMA transfer. - -config ESP32C3_SPI2_DMATHRESHOLD - int "SPI2 Master GDMA threshold" - default 64 - depends on ESP32C3_SPI2_DMA - ---help--- - When SPI GDMA is enabled, GDMA transfers whose size are below the - defined threshold will be performed by polling logic. - -config ESP32C3_SPI2_SLAVE_BUFSIZE - int "SPI2 Slave buffer size" - default 2048 - depends on ESP32C3_SPI2_SLAVE - ---help--- - Configure the size of SPI2 Slave controller's internal buffers. - -config ESP32C3_SPI2_CSPIN - int "SPI2 CS Pin" - default 10 - range 0 21 - -config ESP32C3_SPI2_CLKPIN - int "SPI2 CLK Pin" - default 6 - range 0 21 - -config ESP32C3_SPI2_MOSIPIN - int "SPI2 MOSI Pin" - default 7 - range 0 21 - -config ESP32C3_SPI2_MISOPIN - int "SPI2 MISO Pin" - default 2 - range 0 21 - -endif # ESP32C3_SPI2 - -endmenu # SPI configuration - -menu "UART configuration" - depends on ESP32C3_UART - -if ESP32C3_UART0 - -config ESP32C3_UART0_TXPIN - int "UART0 TX Pin" - default 21 - -config ESP32C3_UART0_RXPIN - int "UART0 RX Pin" - default 20 - -config ESP32C3_UART0_RTSPIN - int "UART0 RTS Pin" - depends on SERIAL_IFLOWCONTROL - default 16 - range 0 21 - -config ESP32C3_UART0_CTSPIN - int "UART0 CTS Pin" - depends on SERIAL_OFLOWCONTROL - default 15 - range 0 21 - -endif # ESP32C3_UART0 - -if ESP32C3_UART1 - -config ESP32C3_UART1_TXPIN - int "UART1 TX Pin" - default 8 - -config ESP32C3_UART1_RXPIN - int "UART1 RX Pin" - default 9 - -config ESP32C3_UART1_RTSPIN - int "UART1 RTS Pin" - depends on SERIAL_IFLOWCONTROL - default 1 - range 0 21 - -config ESP32C3_UART1_CTSPIN - int "UART1 CTS Pin" - depends on SERIAL_OFLOWCONTROL - default 2 - range 0 21 - -endif # ESP32C3_UART1 - -endmenu - -menu "Real-Time Timer" - depends on ESP32C3_RT_TIMER - -config ESP32C3_RT_TIMER_TASK_NAME - string "Timer task name" - default "rt_timer" - -config ESP32C3_RT_TIMER_TASK_PRIORITY - int "Timer task priority" - default 223 - ---help--- - Priority level of the RT Timer task. - Must be lower than the SCHED_HPWORKPRIORITY. - -config ESP32C3_RT_TIMER_TASK_STACK_SIZE - int "Timer task stack size" - default 2048 - -endmenu # Real-Time Timer - -if ESP32C3_TIMER -menu "Timer/counter Configuration" - -config ESP32C3_ONESHOT - bool "One-shot wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support one-shot timer. - -config ESP32C3_FREERUN - bool "TIM free-running wrapper" - default n - ---help--- - Enable a wrapper around the low level timer/counter functions to - support a free-running timer. - -endmenu # Timer/counter Configuration -endif # ESP32C3_TIMER - -menu "LEDC configuration" - depends on ESP32C3_LEDC - -menuconfig ESP32C3_LEDC_TIM0 - bool "Timer 0" - default n - -if ESP32C3_LEDC_TIM0 - -config ESP32C3_LEDC_TIM0_CHANNELS - int "Number of Timer 0 channels" - default 2 - -endif # ESP32C3_LEDC_TIM0 - -menuconfig ESP32C3_LEDC_TIM1 - bool "Timer 1" - default n - -if ESP32C3_LEDC_TIM1 - -config ESP32C3_LEDC_TIM1_CHANNELS - int "Number of Timer 1 channels" - default 2 - -endif # ESP32C3_LEDC_TIM1 - -menuconfig ESP32C3_LEDC_TIM2 - bool "Timer 2" - default n - -if ESP32C3_LEDC_TIM2 - -config ESP32C3_LEDC_TIM2_CHANNELS - int "Number of Timer 2 channels" - default 2 - -endif # ESP32C3_LEDC_TIM2 - -config ESP32C3_LEDC_CHANNEL0_PIN - int "Channel 0 pin" - default 2 - -config ESP32C3_LEDC_CHANNEL1_PIN - int "Channel 1 pin" - default 3 - -config ESP32C3_LEDC_CHANNEL2_PIN - int "Channel 2 pin" - default 4 - -config ESP32C3_LEDC_CHANNEL3_PIN - int "Channel 3 pin" - default 5 - -config ESP32C3_LEDC_CHANNEL4_PIN - int "Channel 4 pin" - default 6 - -config ESP32C3_LEDC_CHANNEL5_PIN - int "Channel 5 pin" - default 7 - -endmenu # LEDC configuration - -menu "ADC Configuration" - depends on ESP32C3_ADC - -if ESP32C3_ADC1 - -choice ESP32C3_ADC_VOL_RANGES - prompt "ADC1 voltage ranges" - default ESP32C3_ADC_VOL_750 - -config ESP32C3_ADC_VOL_750 - bool "0~750mV" - -config ESP32C3_ADC_VOL_1050 - bool "0~1050mV" - -config ESP32C3_ADC_VOL_1300 - bool "0~1300mV" - -config ESP32C3_ADC_VOL_2500 - bool "0~2500mV" - -endchoice - -config ESP32C3_ADC1_CHANNEL0 - bool "ADC1 channel 0" - default n - -config ESP32C3_ADC1_CHANNEL1 - bool "ADC1 channel 1" - default n - -config ESP32C3_ADC1_CHANNEL2 - bool "ADC1 channel 2" - default n - -config ESP32C3_ADC1_CHANNEL3 - bool "ADC1 channel 3" - default n - -config ESP32C3_ADC1_CHANNEL4 - bool "ADC1 channel 4" - default n - -endif # ESP32C3_ADC1 -endmenu # ADC Configuration - -menu "Wi-Fi configuration" - depends on ESP32C3_WIFI - -choice - prompt "ESP32-C3 Wi-Fi mode" - default ESP32C3_WIFI_STATION - -config ESP32C3_WIFI_STATION - bool "Station mode" - -config ESP32C3_WIFI_SOFTAP - bool "SoftAP mode" - -config ESP32C3_WIFI_STATION_SOFTAP - bool "Station + SoftAP" - -endchoice # ESP32-C3 Wi-Fi mode - -config ESP32C3_WIFI_STATIC_RXBUF_NUM - int "Wi-Fi static RX buffer number" - default 10 - -config ESP32C3_WIFI_DYNAMIC_RXBUF_NUM - int "Wi-Fi dynamic RX buffer number" - default 32 - -config ESP32C3_WIFI_DYNAMIC_TXBUF_NUM - int "Wi-Fi dynamic TX buffer number" - default 32 - -config ESP32C3_WIFI_TX_AMPDU - bool "Wi-Fi TX AMPDU" - default y - -config ESP32C3_WIFI_RX_AMPDU - bool "Wi-Fi RX AMPDU" - default y - -config ESP32C3_WIFI_RXBA_AMPDU_WZ - int "Wi-Fi RX BA AMPDU windown size" - default 6 - -config ESP32C3_WIFI_CONNECT_TIMEOUT - int "Connect timeout by second" - default 10 - ---help--- - Max waiting time of connecting to AP. - -config ESP32C3_WIFI_SCAN_RESULT_SIZE - int "Scan result buffer" - default 4096 - ---help--- - Maximum scan result buffer size. - -config ESP32C3_WIFI_STA_DISCONNECT_PM - bool "Power Management for station when disconnected" - default n - ---help--- - Select this option to enable power management for station when disconnected. - Chip will do modem-sleep when RF module is not in use anymore. - -config EXAMPLE_WIFI_LISTEN_INTERVAL - int "Wi-Fi listen interval" - default 3 - ---help--- - Interval for station to listen to beacon from AP. The unit of listen interval is one beacon interval. - For example, if beacon interval is 100 ms and listen interval is 3, the interval for station to listen - to beacon is 300 ms. - -choice EXAMPLE_POWER_SAVE_MODE - prompt "Power save mode" - default EXAMPLE_POWER_SAVE_NONE - ---help--- - Power save mode for the ESP32-C3 to use. Modem sleep mode includes minimum and maximum power save modes. - In minimum power save mode, station wakes up every DTIM to receive beacon. Broadcast data will not be - lost because it is transmitted after DTIM. However, it can not save much more power if DTIM is short - for DTIM is determined by AP. - In maximum power save mode, station wakes up every listen interval to receive beacon. Broadcast data - may be lost because station may be in sleep state at DTIM time. If listen interval is longer, more power - is saved but broadcast data is more easy to lose. - -config EXAMPLE_POWER_SAVE_NONE - bool "none" - -config EXAMPLE_POWER_SAVE_MIN_MODEM - bool "minimum modem" - -config EXAMPLE_POWER_SAVE_MAX_MODEM - bool "maximum modem" - -endchoice - -config ESP32C3_WIFI_RECONNECT - bool "Enable Wi-Fi to reconnect" - default n - ---help--- - Select this option to enable Wi-Fi to reconnect for station when disconnected. - -choice ESP32C3_WIFI_LOG_LEVEL - depends on DEBUG_INFO - prompt "WiFi debug log level" - default WIFI_LOG_LEVEL_INFO - ---help--- - The WiFi log is divided into the following levels: ERROR,WARNING,INFO,DEBUG,VERBOSE. - -config WIFI_LOG_LEVEL_NONE - bool "No output" - -config WIFI_LOG_LEVEL_ERROR - bool "Error" - -config WIFI_LOG_LEVEL_WARN - bool "Warning" - -config WIFI_LOG_LEVEL_INFO - bool "Info" - -config WIFI_LOG_LEVEL_DEBUG - bool "Debug" - -config WIFI_LOG_LEVEL_VERBOSE - bool "Verbose" - -endchoice - -config WIFI_LOG_LEVEL - int - default 0 if WIFI_LOG_LEVEL_NONE - default 1 if WIFI_LOG_LEVEL_ERROR - default 2 if WIFI_LOG_LEVEL_WARN - default 3 if WIFI_LOG_LEVEL_INFO - default 4 if WIFI_LOG_LEVEL_DEBUG - default 5 if WIFI_LOG_LEVEL_VERBOSE - -endmenu # Wi-Fi configuration - -menu "BLE Configuration" - depends on ESP32C3_BLE - -config ESP32C3_BLE_TTY_NAME - string "BLE TTY device name" - default "/dev/ttyHCI0" - depends on UART_BTH4 - -config ESP32C3_BLE_TASK_STACK_SIZE - int "Controller task stack size" - default 4096 - -config ESP32C3_BLE_TASK_PRIORITY - int "Controller task priority" - default 253 - -endmenu # BLE Configuration - -menu "SPI Flash configuration" - -choice ESP32C3_FLASH_MODE - prompt "SPI Flash mode" - default ESP32C3_FLASH_MODE_DIO - ---help--- - These options control how many I/O pins are used for communication with the attached SPI Flash chip. - The option selected here is then used by esptool when flashing. - -config ESP32C3_FLASH_MODE_DIO - bool "Dual IO (DIO)" - -config ESP32C3_FLASH_MODE_DOUT - bool "Dual Output (DOUT)" - -config ESP32C3_FLASH_MODE_QIO - bool "Quad IO (QIO)" - -config ESP32C3_FLASH_MODE_QOUT - bool "Quad Output (QOUT)" - -endchoice # ESP32C3_FLASH_MODE - -choice ESP32C3_FLASH_FREQ - prompt "SPI Flash frequency" - default ESP32C3_FLASH_FREQ_40M - ---help--- - SPI Flash frequency. - -config ESP32C3_FLASH_FREQ_80M - bool "80 MHz" - -config ESP32C3_FLASH_FREQ_40M - bool "40 MHz" - -config ESP32C3_FLASH_FREQ_26M - bool "26 MHz" - -config ESP32C3_FLASH_FREQ_20M - bool "20 MHz" - -endchoice # ESP32C3_FLASH_FREQ - -if ESP32C3_HAVE_OTA_PARTITION - -comment "Application Image OTA Update support" - -config ESP32C3_OTA_PARTITION_ENCRYPT - bool "Encrypt OTA partitions" - default y - depends on ESP32C3_SECURE_FLASH_ENC_ENABLED - -config ESP32C3_OTA_PRIMARY_SLOT_OFFSET - hex "Application image primary slot offset" - default 0x10000 - -config ESP32C3_OTA_PRIMARY_SLOT_DEVPATH - string "Application image primary slot device path" - default "/dev/ota0" - -config ESP32C3_OTA_SECONDARY_SLOT_OFFSET - hex "Application image secondary slot offset" - default 0x110000 - -config ESP32C3_OTA_SECONDARY_SLOT_DEVPATH - string "Application image secondary slot device path" - default "/dev/ota1" - -config ESP32C3_OTA_SLOT_SIZE - hex "Application image slot size (in bytes)" - default 0x100000 - -config ESP32C3_OTA_SCRATCH_OFFSET - hex "Scratch partition offset" - default 0x210000 - -config ESP32C3_OTA_SCRATCH_SIZE - hex "Scratch partition size" - default 0x40000 - -config ESP32C3_OTA_SCRATCH_DEVPATH - string "Scratch partition device path" - default "/dev/otascratch" - -endif - -if ESP32C3_SPIFLASH - -comment "General storage MTD configuration" - -config ESP32C3_MTD - bool "MTD driver" - default y - select MTD - select MTD_BYTE_WRITE - select MTD_PARTITION - ---help--- - Initialize an MTD driver for the ESP32-C3 SPI Flash, which will - add an entry at /dev for application access from userspace. - -config ESP32C3_SPIFLASH_MTD_BLKSIZE - int "Storage MTD block size" - default 64 - depends on ESP32C3_MTD - -config ESP32C3_STORAGE_MTD_DEBUG - bool "Storage MTD Debug" - default n - depends on ESP32C3_MTD && DEBUG_FS_INFO - ---help--- - If this option is enabled, Storage MTD driver read and write functions - will output input parameters and return values (if applicable). - -if ESP32C3_APP_FORMAT_LEGACY - -comment "Partition Table configuration" - -config ESP32C3_PARTITION_TABLE - bool "Create MTD partitions from Partition Table" - default n - ---help--- - Decode partition table and initialize partitions as MTD. - -config ESP32C3_PARTITION_MOUNTPT - string "Partition mount point" - default "/dev/esp/partition/" - depends on ESP32C3_PARTITION_TABLE - -endif # ESP32C3_APP_FORMAT_LEGACY - -endif # ESP32C3_SPIFLASH - -endmenu # SPI Flash configuration - -menu "GDMA Configuration" - depends on ESP32C3_DMA - -endmenu # GDMA Configuration - -config ESP32C3_AUTO_SLEEP - bool "Auto-sleep" - default n - select PM - select ESP32C3_RT_TIMER - select ESP32C3_TICKLESS - ---help--- - Enable ESP32-C3 Auto-sleep - -config ESP32C3_TICKLESS - bool "Enable ESP32-C3 tickless OS" - default n - select ARCH_HAVE_TICKLESS - select SCHED_TICKLESS - -config ESP32C3_HAVE_OTA_PARTITION - bool - default n - -menu "Application Image Configuration" - -choice - prompt "Application Image Format" - default ESP32C3_APP_FORMAT_LEGACY - ---help--- - Depending on the chosen 2nd stage bootloader, the application may - be required to be perform a specific startup routine. Furthermore, - the image binary must be formatted according to the definition from - the 2nd stage bootloader. - -config ESP32C3_APP_FORMAT_LEGACY - bool "Legacy format" - ---help--- - This is the legacy application image format, as supported by the ESP-IDF - 2nd stage bootloader. - -config ESP32C3_APP_FORMAT_MCUBOOT - bool "MCUboot-bootable format" - depends on !MCUBOOT_BOOTLOADER - select ESP32C3_HAVE_OTA_PARTITION - ---help--- - The Espressif port of MCUboot supports the loading of unsegmented firmware - images. - -endchoice # Application Image Format - -choice - prompt "Source for bootloader binaries" - default ESP32C3_BOOTLOADER_DOWNLOAD_PREBUILT - ---help--- - Select the action to be taken by the build system for the - "make bootloader" target. - -config ESP32C3_BOOTLOADER_DOWNLOAD_PREBUILT - bool "Download prebuilt binaries" - ---help--- - The build system will download the prebuilt binaries from - https://github.com/espressif/esp-nuttx-bootloader according to the chosen - Application Image Format (ESP32C3_APP_FORMAT_LEGACY or ESP32C3_APP_FORMAT_MCUBOOT) - -config ESP32C3_BOOTLOADER_BUILD_FROM_SOURCE - bool "Build binaries from source" - ---help--- - The build system will build all the required binaries from source. It will clone - the https://github.com/espressif/esp-nuttx-bootloader repository and build a - custom bootloader according to the chosen Application Image Format - (ESP32C3_APP_FORMAT_LEGACY or ESP32C3_APP_FORMAT_MCUBOOT) and partition information. - -endchoice - -choice - prompt "Target slot for image flashing" - default ESP32C3_ESPTOOL_TARGET_PRIMARY - depends on ESP32C3_HAVE_OTA_PARTITION - ---help--- - Slot to which ESPTOOL will flash the generated binary image. - -config ESP32C3_ESPTOOL_TARGET_PRIMARY - bool "Application image primary slot" - ---help--- - This assumes that the generated image is already pre-validated. - This is the recommended option for the initial stages of the - application firmware image development. - -config ESP32C3_ESPTOOL_TARGET_SECONDARY - bool "Application image secondary slot" - ---help--- - The application needs to confirm the generated image as valid, - otherwise the bootloader may consider it invalid and perform the - rollback of the update after a reset. - This is the choice most suitable for the development and verification - of a secure firmware update workflow. - -endchoice - -config ESP32C3_APP_MCUBOOT_HEADER_SIZE - int "Application image header size (in bytes)" - default 32 - depends on ESP32C3_APP_FORMAT_MCUBOOT - -config ESP32C3_PARTITION_TABLE_OFFSET - hex "Partition Table offset" - default 0x8000 - depends on ESP32C3_APP_FORMAT_LEGACY - -if BUILD_PROTECTED - -config ESP32C3_USER_IMAGE_OFFSET - hex "User image offset" - default 0x90000 - ---help--- - Offset in SPI Flash for flashing the User application firmware image. - -endif - -source "arch/risc-v/src/esp32c3/Kconfig.security" - -endmenu # Application Image Configuration - -menu "Brownout Detect Configuration" - depends on ESP32C3_BROWNOUT_DET - -choice ESP32C3_BROWNOUT_DET_LVL_SEL - prompt "Brownout voltage level" - default ESP32C3_BROWNOUT_DET_LVL_SEL_7 - ---help--- - The brownout detector will reset the chip when the supply voltage is approximately - below this level. Note that there may be some variation of brownout voltage level - between each chip. - - #The voltage levels here are estimates, more work needs to be done to figure out the exact voltages - #of the brownout threshold levels. - -config ESP32C3_BROWNOUT_DET_LVL_SEL_7 - bool "2.51V" - -config ESP32C3_BROWNOUT_DET_LVL_SEL_6 - bool "2.64V" - -config ESP32C3_BROWNOUT_DET_LVL_SEL_5 - bool "2.76V" - -config ESP32C3_BROWNOUT_DET_LVL_SEL_4 - bool "2.92V" - -config ESP32C3_BROWNOUT_DET_LVL_SEL_3 - bool "3.10V" - -config ESP32C3_BROWNOUT_DET_LVL_SEL_2 - bool "3.27V" - -endchoice - -config ESP32C3_BROWNOUT_DET_LVL - int - default 2 if ESP32C3_BROWNOUT_DET_LVL_SEL_2 - default 3 if ESP32C3_BROWNOUT_DET_LVL_SEL_3 - default 4 if ESP32C3_BROWNOUT_DET_LVL_SEL_4 - default 5 if ESP32C3_BROWNOUT_DET_LVL_SEL_5 - default 6 if ESP32C3_BROWNOUT_DET_LVL_SEL_6 - default 7 if ESP32C3_BROWNOUT_DET_LVL_SEL_7 - -endmenu # ESP32C3_BROWNOUT_DET - -endif # ARCH_CHIP_ESP32C3 +endif # ARCH_CHIP_ESP32C3_GENERIC diff --git a/arch/risc-v/src/esp32c3/Make.defs b/arch/risc-v/src/esp32c3/Make.defs index 3e05468804d4f..97e5963f4bf44 100644 --- a/arch/risc-v/src/esp32c3/Make.defs +++ b/arch/risc-v/src/esp32c3/Make.defs @@ -18,210 +18,14 @@ # ############################################################################ -include chip/Bootloader.mk include common/Make.defs - -# Specify our HEAD assembly file. This will be linked as -# the first object file, so it will appear at address 0 - -HEAD_ASRC = esp32c3_head.S - -CHIP_ASRCS = esp32c3_vectors.S - -# Specify our general Assembly files - -CMN_ASRCS := $(filter-out riscv_vectors.S,$(CMN_ASRCS)) - -# Specify our C code within this directory to be included - -CHIP_CSRCS = esp32c3_allocateheap.c esp32c3_start.c esp32c3_wdt.c esp32c3_idle.c -CHIP_CSRCS += esp32c3_irq.c esp32c3_libc_stubs.c -CHIP_CSRCS += esp32c3_clockconfig.c esp32c3_gpio.c esp32c3_rtc_gpio.c -CHIP_CSRCS += esp32c3_lowputc.c esp32c3_serial.c -CHIP_CSRCS += esp32c3_systemreset.c esp32c3_resetcause.c -CHIP_CSRCS += esp32c3_uid.c esp32c3_perf.c - -ifeq ($(CONFIG_ESP32C3_REGION_PROTECTION),y) -CHIP_CSRCS += esp32c3_region.c -endif - -ifeq ($(CONFIG_BUILD_PROTECTED),y) -CHIP_CSRCS += esp32c3_userspace.c -endif - -ifeq ($(CONFIG_SCHED_TICKLESS),y) -CHIP_CSRCS += esp32c3_tickless.c -else -CHIP_CSRCS += esp32c3_timerisr.c -endif - -ifeq ($(CONFIG_ESP32C3_USBSERIAL),y) -CHIP_CSRCS += esp32c3_usbserial.c -endif - -ifeq ($(CONFIG_ESP32C3_RNG),y) -CHIP_CSRCS += esp32c3_rng.c -endif - -ifeq ($(CONFIG_ESP32C3_I2C),y) -CHIP_CSRCS += esp32c3_i2c.c -endif - -ifeq ($(CONFIG_ESP32C3_TWAI),y) -CHIP_CSRCS += esp32c3_twai.c -endif - -ifeq ($(CONFIG_ESP32C3_SPI),y) -CHIP_CSRCS += esp32c3_spi.c - ifeq ($(CONFIG_SPI_SLAVE),y) - CHIP_CSRCS += esp32c3_spi_slave.c - endif -endif - -ifeq ($(CONFIG_ESP32C3_SPIFLASH),y) -CHIP_CSRCS += esp32c3_spiflash.c - ifeq ($(CONFIG_ESP32C3_MTD),y) - CHIP_CSRCS += esp32c3_spiflash_mtd.c - endif -endif - -ifeq ($(CONFIG_ESP32C3_PARTITION_TABLE),y) -CHIP_CSRCS += esp32c3_partition.c -endif - -ifeq ($(CONFIG_WATCHDOG),y) -CHIP_CSRCS += esp32c3_wdt_lowerhalf.c -endif - -ifeq ($(CONFIG_ESP32C3_TIMER),y) -CHIP_CSRCS += esp32c3_tim.c -ifeq ($(CONFIG_TIMER),y) -CHIP_CSRCS += esp32c3_tim_lowerhalf.c -endif -endif - -ifeq ($(CONFIG_ESP32C3_ONESHOT),y) -CHIP_CSRCS += esp32c3_oneshot.c -ifeq ($(CONFIG_ONESHOT),y) -CHIP_CSRCS += esp32c3_oneshot_lowerhalf.c -endif -endif - -ifeq ($(CONFIG_ESP32C3_RT_TIMER),y) -CHIP_CSRCS += esp32c3_rt_timer.c -endif - -ifeq ($(CONFIG_ESP32C3_BIGNUM_ACCELERATOR),y) -CHIP_CSRCS += esp32c3_bignum.c -endif - -ifeq ($(CONFIG_ESP32C3_RSA_ACCELERATOR),y) -CHIP_CSRCS += esp32c3_rsa.c -endif - -ifeq ($(CONFIG_ESP32C3_SHA_ACCELERATOR),y) -CHIP_CSRCS += esp32c3_sha.c -endif - -ifeq ($(CONFIG_ESP32C3_FREERUN),y) -CHIP_CSRCS += esp32c3_freerun.c -endif - -ifeq ($(CONFIG_ESP32C3_DMA),y) -CHIP_CSRCS += esp32c3_dma.c -endif - -ifeq ($(CONFIG_PM),y) -ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) -CHIP_CSRCS += esp32c3_pminitialize.c -endif -CHIP_CSRCS += esp32c3_pm.c -endif - -CHIP_CSRCS += esp32c3_rtc.c - -ifeq ($(CONFIG_ESP32C3_LEDC),y) -CHIP_CSRCS += esp32c3_ledc.c -endif - -ifeq ($(CONFIG_ESP32C3_ADC),y) -CHIP_CSRCS += esp32c3_adc.c -endif - -ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE),y) -CHIP_CSRCS += esp32c3_crypto.c -endif - -ifeq ($(CONFIG_ESP32C3_AES_ACCELERATOR),y) -CHIP_CSRCS += esp32c3_aes.c -endif - -ifeq ($(CONFIG_ESP32C3_EFUSE),y) -CHIP_CSRCS += esp32c3_efuse.c -CHIP_CSRCS += esp32c3_efuse_table.c -CHIP_CSRCS += esp32c3_efuse_lowerhalf.c -endif - -ifeq ($(CONFIG_ARCH_HAVE_EXTRA_HEAPS),y) -CHIP_CSRCS += esp32c3_extraheaps.c -endif - -ifeq ($(CONFIG_ARCH_USE_TEXT_HEAP),y) -CHIP_CSRCS += esp32c3_textheap.c -endif - -ifeq ($(CONFIG_RTC_DRIVER),y) -CHIP_CSRCS += esp32c3_rtc_lowerhalf.c -endif - -ifeq ($(CONFIG_ESP32C3_RTC_HEAP),y) -CHIP_CSRCS += esp32c3_rtcheap.c -endif - -ifeq ($(CONFIG_ESP32C3_BROWNOUT_DET),y) -CHIP_CSRCS += esp32c3_brownout.c -endif - -ifeq ($(CONFIG_ESP32C3_WIRELESS),y) -WIRELESS_DRV_UNPACK = esp-wireless-drivers-3rdparty -WIRELESS_DRV_ID = 45701c0 -WIRELESS_DRV_ZIP = $(WIRELESS_DRV_ID).zip -WIRELESS_DRV_URL = https://github.com/espressif/esp-wireless-drivers-3rdparty/archive - -$(WIRELESS_DRV_ZIP): - $(call DOWNLOAD,$(WIRELESS_DRV_URL),$(WIRELESS_DRV_ZIP),chip/$(WIRELESS_DRV_ZIP)) - -chip/$(WIRELESS_DRV_UNPACK): $(WIRELESS_DRV_ZIP) - $(Q) echo "Unpacking: ESP Wireless Drivers" - $(Q) unzip -oqq chip/$(WIRELESS_DRV_ZIP) -d chip/ - $(Q) mv chip/$(WIRELESS_DRV_UNPACK)-$(WIRELESS_DRV_ID)* chip/$(WIRELESS_DRV_UNPACK) - $(Q) touch chip/$(WIRELESS_DRV_UNPACK) - -ifeq ($(wildcard chip/$(WIRELESS_DRV_UNPACK)/.git),) -context:: chip/$(WIRELESS_DRV_UNPACK) - -distclean:: - $(call DELFILE, chip/$(WIRELESS_DRV_ZIP)) - $(call DELDIR, chip/$(WIRELESS_DRV_UNPACK)) -endif - -INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)esp-wireless-drivers-3rdparty$(DELIM)include -INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)esp-wireless-drivers-3rdparty$(DELIM)include$(DELIM)esp32c3 - -EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)esp-wireless-drivers-3rdparty$(DELIM)libs$(DELIM)esp32c3 -EXTRA_LIBS += -lphy +include common/espressif/Make.defs # Wireless interfaces. -CHIP_CSRCS += esp32c3_wireless.c +ifeq ($(CONFIG_ESPRESSIF_WIFI),y) +CHIP_CSRCS += esp_coex_adapter.c esp_wifi_adapter.c +EXTRA_LIBS += -lcore -lnet80211 -lpp endif -ifeq ($(CONFIG_ESP32C3_WIFI),y) -CHIP_CSRCS += esp32c3_wlan.c esp32c3_wifi_utils.c esp32c3_wifi_adapter.c -EXTRA_LIBS += -lcore -lnet80211 -lpp -lsmartconfig -lcoexist -lespnow -lwpa_supplicant -lwapi -lmesh -endif - -ifeq ($(CONFIG_ESP32C3_BLE),y) -CHIP_CSRCS += esp32c3_ble_adapter.c esp32c3_ble.c -EXTRA_LIBS += -lbtbb -lbtdm_app -endif +CFLAGS += ${DEFINE_PREFIX}_RETARGETABLE_LOCKING diff --git a/arch/risc-v/src/esp32c3/chip.h b/arch/risc-v/src/esp32c3/chip.h deleted file mode 100644 index 2ae947ddaea0e..0000000000000 --- a/arch/risc-v/src/esp32c3/chip.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/chip.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_CHIP_H -#define __ARCH_RISCV_SRC_ESP32C3_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "esp32c3_memorymap.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Section for exception handler. */ - -#define EXCEPTION_SECTION .iram1 - -#endif /* __ARCH_RISCV_SRC_ESP32C3_CHIP_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_aes.h b/arch/risc-v/src/esp32c3/esp32c3_aes.h deleted file mode 100644 index 6ed25f17c07b6..0000000000000 --- a/arch/risc-v/src/esp32c3/esp32c3_aes.h +++ /dev/null @@ -1,217 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_aes.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_AES_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_AES_H - -#include -#include - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* AES private description */ - -struct esp32c3_aes_s -{ - uint32_t key[8]; /* Key data value */ - uint16_t keybits; /* Key data bits */ -}; - -/* AES XTS private description */ - -struct esp32c3_aes_xts_s -{ - struct esp32c3_aes_s crypt; /* AES block encryption/decryption */ - struct esp32c3_aes_s tweak; /* AES tweak encryption/decryption */ -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c3_aes_ecb_cypher - * - * Description: - * Process AES ECB encryption/decryption. - * - * Input Parameters: - * aes - AES object data pointer - * encrypt - True: encryption mode; False: decryption mode - * input - Input data pointer - * output - Output buffer pointer - * size - Data size in bytes - * - * Returned Value: - * OK is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp32c3_aes_ecb_cypher(struct esp32c3_aes_s *aes, bool encrypt, - const void *input, void *output, uint32_t size); - -/**************************************************************************** - * Name: esp32c3_aes_cbc_cypher - * - * Description: - * Process AES CBC encryption/decryption. - * - * Input Parameters: - * aes - AES object data pointer - * encrypt - True: encryption mode; False: decryption mode - * ivptr - Initialization vector pointer - * input - Input data pointer - * output - Output buffer pointer - * size - Data size in bytes - * - * Returned Value: - * OK is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp32c3_aes_cbc_cypher(struct esp32c3_aes_s *aes, bool encrypt, - void *ivptr, const void *input, void *output, - uint32_t size); - -/**************************************************************************** - * Name: esp32c3_aes_ctr_cypher - * - * Description: - * Process AES CTR encryption/decryption. - * - * Input Parameters: - * aes - AES object data pointer - * offptr - Offset buffer pointer - * cntptr - Counter buffer pointer - * cacheptr - Counter calculation buffer pointer - * input - Input data pointer - * output - Output buffer pointer - * size - Data size in bytes - * - * Returned Value: - * OK is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp32c3_aes_ctr_cypher(struct esp32c3_aes_s *aes, uint32_t *offptr, - void *cntptr, void *cacheptr, const void *input, - void *output, uint32_t size); - -/**************************************************************************** - * Name: esp32c3_aes_xts_cypher - * - * Description: - * Process AES XTS encryption/decryption. - * - * Input Parameters: - * aes - AES object data pointer - * encrypt - True: encryption mode; False: decryption mode - * unitptr - Unit data buffer pointer - * input - Input data pointer - * output - Output buffer pointer - * size - Data size in bytes - * - * Returned Value: - * OK is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp32c3_aes_xts_cypher(struct esp32c3_aes_xts_s *aes, bool encrypt, - void *unitptr, const void *input, void *output, - uint32_t size); - -/**************************************************************************** - * Name: esp32c3_aes_setkey - * - * Description: - * Configurate AES key. - * - * Input Parameters: - * aes - AES object data pointer - * keyptr - Key data pointer - * keybits - Key data bits - * - * Returned Value: - * OK is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp32c3_aes_setkey(struct esp32c3_aes_s *aes, const void *keyptr, - uint16_t keybits); - -/**************************************************************************** - * Name: esp32c3_aes_xts_setkey - * - * Description: - * Configurate AES XTS key. - * - * Input Parameters: - * aes - AES object data pointer - * keyptr - Key data pointer - * keybits - Key data bits - * - * Returned Value: - * OK is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp32c3_aes_xts_setkey(struct esp32c3_aes_xts_s *aes, const void *keyptr, - uint16_t keybits); - -/**************************************************************************** - * Name: esp32c3_aes_init - * - * Description: - * Initialize ESP32-C3 AES hardware driver. - * - * Input Parameters: - * None - * - * Returned Value: - * OK is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp32c3_aes_init(void); - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_AES_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_dma.h b/arch/risc-v/src/esp32c3/esp32c3_dma.h deleted file mode 100644 index 17272a9b37929..0000000000000 --- a/arch/risc-v/src/esp32c3/esp32c3_dma.h +++ /dev/null @@ -1,225 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_dma.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_DMA_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_DMA_H - -#include -#include -#include - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Pre-processor Macros - ****************************************************************************/ - -/* DMA max data length */ - -#define ESP32C3_DMA_DATALEN_MAX (0x1000 - 4) - -/* DMA max buffer length */ - -#define ESP32C3_DMA_BUFLEN_MAX ESP32C3_DMA_DATALEN_MAX - -/* DMA channel number */ - -#define ESP32C3_DMA_CHAN_MAX (3) - -/* DMA RX MAX priority */ - -#define ESP32C3_DMA_RX_PRIO_MAX (15) - -/* DMA TX MAX priority */ - -#define ESP32C3_DMA_TX_PRIO_MAX (15) - -/* DMA descriptor */ - -#define ESP32C3_DMA_CTRL_OWN (1 << 31) /* Owned by DMA */ -#define ESP32C3_DMA_CTRL_EOF (1 << 30) /* End of frame */ -#define ESP32C3_DMA_CTRL_ERREOF (1 << 28) /* Received data error */ -#define ESP32C3_DMA_CTRL_DATALEN_S (12) /* Data length shift */ -#define ESP32C3_DMA_CTRL_DATALEN_V (0xfff) /* Data length value */ -#define ESP32C3_DMA_CTRL_BUFLEN_S (0) /* Buffer length shift */ -#define ESP32C3_DMA_CTRL_BUFLEN_V (0xfff) /* Buffer length value */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -enum esp32c3_dma_periph_e -{ - ESP32C3_DMA_PERIPH_MEM = -1, - ESP32C3_DMA_PERIPH_SPI = 0, - ESP32C3_DMA_PERIPH_UCHI0 = 2, - ESP32C3_DMA_PERIPH_I2S = 3, - ESP32C3_DMA_PERIPH_RD0 = 4, - ESP32C3_DMA_PERIPH_RD1 = 5, - ESP32C3_DMA_PERIPH_AES = 6, - ESP32C3_DMA_PERIPH_SHA = 7, - ESP32C3_DMA_PERIPH_ADC = 8, - ESP32C3_DMA_PERIPH_NUM, -}; - -/* DMA descriptor type */ - -struct esp32c3_dmadesc_s -{ - uint32_t ctrl; /* DMA control block */ - const uint8_t *pbuf; /* DMA TX/RX buffer address */ - struct esp32c3_dmadesc_s *next; /* Next DMA descriptor address */ -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c3_dma_request - * - * Description: - * Request DMA channel and config it with given parameters. - * - * Input Parameters: - * periph - Peripheral for which the DMA channel request was made - * tx_prio - Interrupt priority - * rx_prio - Interrupt flags - * - * Returned Value: - * DMA channel number (>=0) if success or -1 if fail. - * - ****************************************************************************/ - -int32_t esp32c3_dma_request(enum esp32c3_dma_periph_e periph, - uint32_t tx_prio, - uint32_t rx_prio, - bool burst_en); - -/**************************************************************************** - * Name: esp32c3_dma_setup - * - * Description: - * Set up DMA descriptor with given parameters. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * dmadesc - DMA descriptor pointer - * num - DMA descriptor number - * pbuf - Buffer pointer - * len - Buffer length by byte - * - * Returned Value: - * Bind pbuf data bytes. - * - ****************************************************************************/ - -uint32_t esp32c3_dma_setup(int chan, bool tx, - struct esp32c3_dmadesc_s *dmadesc, uint32_t num, - uint8_t *pbuf, uint32_t len); - -/**************************************************************************** - * Name: esp32c3_dma_enable - * - * Description: - * Enable DMA channel transmission. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c3_dma_enable(int chan, bool tx); - -/**************************************************************************** - * Name: esp32c3_dma_disable - * - * Description: - * Disable DMA channel transmission. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c3_dma_disable(int chan, bool tx); - -/**************************************************************************** - * Name: esp32c3_dma_wait_idle - * - * Description: - * Wait until transmission ends. - * - * Input Parameters: - * chan - DMA channel - * tx - true: TX mode; false: RX mode - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c3_dma_wait_idle(int chan, bool tx); - -/**************************************************************************** - * Name: esp32c3_dma_init - * - * Description: - * Initialize DMA driver. - * - * Input Parameters: - * None - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c3_dma_init(void); - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_DMA_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_efuse.h b/arch/risc-v/src/esp32c3/esp32c3_efuse.h deleted file mode 100644 index f97b690a1e1ff..0000000000000 --- a/arch/risc-v/src/esp32c3/esp32c3_efuse.h +++ /dev/null @@ -1,189 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_efuse.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_EFUSE_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_EFUSE_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* Type of eFuse blocks for ESP32C3 */ - -typedef enum -{ - EFUSE_BLK0 = 0, /* Number of eFuse BLOCK0. REPEAT_DATA */ - - EFUSE_BLK1 = 1, /* Number of eFuse BLOCK1. MAC_SPI_8M_SYS */ - - EFUSE_BLK2 = 2, /* Number of eFuse BLOCK2. SYS_DATA_PART1 */ - EFUSE_BLK_SYS_DATA_PART1 = 2, /* Number of eFuse BLOCK2. SYS_DATA_PART1 */ - - EFUSE_BLK3 = 3, /* Number of eFuse BLOCK3. USER_DATA */ - EFUSE_BLK_USER_DATA = 3, /* Number of eFuse BLOCK3. USER_DATA */ - - EFUSE_BLK4 = 4, /* Number of eFuse BLOCK4. KEY0 */ - EFUSE_BLK_KEY0 = 4, /* Number of eFuse BLOCK4. KEY0 */ - - EFUSE_BLK5 = 5, /* Number of eFuse BLOCK5. KEY1 */ - EFUSE_BLK_KEY1 = 5, /* Number of eFuse BLOCK5. KEY1 */ - - EFUSE_BLK6 = 6, /* Number of eFuse BLOCK6. KEY2 */ - EFUSE_BLK_KEY2 = 6, /* Number of eFuse BLOCK6. KEY2 */ - - EFUSE_BLK7 = 7, /* Number of eFuse BLOCK7. KEY3 */ - EFUSE_BLK_KEY3 = 7, /* Number of eFuse BLOCK7. KEY3 */ - - EFUSE_BLK8 = 8, /* Number of eFuse BLOCK8. KEY4 */ - EFUSE_BLK_KEY4 = 8, /* Number of eFuse BLOCK8. KEY4 */ - - EFUSE_BLK9 = 9, /* Number of eFuse BLOCK9. KEY5 */ - EFUSE_BLK_KEY5 = 9, /* Number of eFuse BLOCK9. KEY5 */ - EFUSE_BLK_KEY_MAX = 10, - - EFUSE_BLK10 = 10, /* Number of eFuse BLOCK10. SYS_DATA_PART2 */ - EFUSE_BLK_SYS_DATA_PART2 = 10, /* Number of eFuse BLOCK10. SYS_DATA_PART2 */ - - EFUSE_BLK_MAX -} esp_efuse_block_t; - -/**************************************************************************** - * Name: efuse_func_proc_t - * - * Description: - * This is type of function that will handle the efuse field register. - * - * Input Parameters: - * num_reg - The register number in the block. - * bit_start - Start bit in the register. - * bit_count - The number of bits used in the register. - * arr - A pointer to an array or variable. - * bits_counter - Counter bits. - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise -1 (ERROR). - * - ****************************************************************************/ - -typedef int (*efuse_func_proc_t) (uint32_t num_reg, - int bit_start, - int bit_count, - void *arr, int *bits_counter); - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c3_efuse_read_field - * - * Description: - * Read value from EFUSE, writing it into an array. - * - * Input Parameters: - * field - A pointer to describing the fields of efuse - * dst - A pointer to array that contains the data for reading - * dst_size_bits - The number of bits required to read - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise -1 (ERROR). - * - ****************************************************************************/ - -int esp32c3_efuse_read_field(const efuse_desc_t *field[], void *dst, - size_t dst_size_bits); - -/**************************************************************************** - * Name: esp32c3_efuse_write_field - * - * Description: - * Write array to EFUSE. - * - * Input Parameters: - * field - A pointer to describing the fields of efuse - * src - A pointer to array that contains the data for writing - * src_size_bits - The number of bits required to write - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise -1 (ERROR). - * - ****************************************************************************/ - -int esp32c3_efuse_write_field(const efuse_desc_t *field[], - const void *src, size_t src_size_bits); - -/**************************************************************************** - * Name: esp32c3_efuse_burn_efuses - * - * Description: - * Burn values written to the efuse write registers. - * - * Input Parameters: - * None - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c3_efuse_burn_efuses(void); - -/**************************************************************************** - * Name: esp32c3_efuse_initialize - * - * Description: - * Initialize the efuse driver. The efuse is initialized - * and registered as 'devpath'. - * - * Input Parameters: - * devpath - The full path to the efuse device. - * This should be of the form /dev/efuse - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise -1 (ERROR). - * - ****************************************************************************/ - -int esp32c3_efuse_initialize(const char *devpath); - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_EFUSE_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_gpio.c b/arch/risc-v/src/esp32c3/esp32c3_gpio.c deleted file mode 100644 index abda9e09000de..0000000000000 --- a/arch/risc-v/src/esp32c3/esp32c3_gpio.c +++ /dev/null @@ -1,420 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_gpio.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "riscv_internal.h" -#ifdef CONFIG_ESP32C3_GPIO_IRQ -#include "esp32c3_irq.h" -#endif -#include "hardware/esp32c3_iomux.h" -#include "hardware/esp32c3_gpio.h" -#include "hardware/esp32c3_usb_serial_jtag.h" - -#include "esp32c3_gpio.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define USB_JTAG_DM 18 -#define USB_JTAG_DP 19 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_ESP32C3_GPIO_IRQ -static int g_gpio_cpuint; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: gpio_dispatch - * - * Description: - * Second level dispatch for GPIO interrupt handling. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32C3_GPIO_IRQ -static void gpio_dispatch(int irq, uint32_t status, uint32_t *regs) -{ - int i; - int ndx = 0; - - /* Check set bits in the status register */ - - while ((i = __builtin_ffs(status))) - { - ndx += i; - irq_dispatch(irq + ndx - 1, regs); - status >>= i; - } -} -#endif - -/**************************************************************************** - * Name: gpio_interrupt - * - * Description: - * GPIO interrupt handler. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32C3_GPIO_IRQ -static int gpio_interrupt(int irq, void *context, void *arg) -{ - uint32_t status; - - /* Read and clear the lower GPIO interrupt status */ - - status = getreg32(GPIO_STATUS_REG); - putreg32(status, GPIO_STATUS_W1TC_REG); - - /* Dispatch pending interrupts in the lower GPIO status register */ - - gpio_dispatch(ESP32C3_FIRST_GPIOIRQ, status, (uint32_t *)context); - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c3_configgpio - * - * Description: - * Configure a GPIO pin based on encoded pin attributes. - * - ****************************************************************************/ - -int esp32c3_configgpio(int pin, gpio_pinattr_t attr) -{ - uintptr_t regaddr; - uint32_t func; - uint32_t cntrl; - uint32_t pin2func; - - DEBUGASSERT(pin >= 0 && pin <= ESP32C3_NGPIOS); - - func = 0; - cntrl = 0; - - /* If pin 18 or 19 then disable the USB/JTAG function and pull-up */ - - if ((pin == USB_JTAG_DM) || (pin == USB_JTAG_DP)) - { - uint32_t regval; - - regval = getreg32(USB_SERIAL_JTAG_CONF0_REG); - regval &= ~(USB_SERIAL_JTAG_USB_PAD_ENABLE | - USB_SERIAL_JTAG_DP_PULLUP); - putreg32(regval, USB_SERIAL_JTAG_CONF0_REG); - } - - /* Handle input pins */ - - if ((attr & INPUT) != 0) - { - putreg32((1ul << pin), GPIO_ENABLE_W1TC_REG); - - /* Input enable */ - - func |= FUN_IE; - - if ((attr & PULLUP) != 0) - { - func |= FUN_PU; - } - else if ((attr & PULLDOWN) != 0) - { - func |= FUN_PD; - } - } - - /* Handle output pins */ - - if ((attr & OUTPUT) != 0) - { - putreg32((1ul << pin), GPIO_ENABLE_W1TS_REG); - } - - /* Add drivers */ - - func |= (uint32_t)(2ul << FUN_DRV_S); - - /* Select the pad's function. If no function was given, consider it a - * normal input or output (i.e. function1). - */ - - if ((attr & FUNCTION_MASK) != 0) - { - func |= (uint32_t)(((attr >> FUNCTION_SHIFT) - 1) << MCU_SEL_S); - } - else - { - func |= (uint32_t)(PIN_FUNC_GPIO << MCU_SEL_S); - } - - if ((attr & OPEN_DRAIN) != 0) - { - cntrl |= (1 << GPIO_PIN_PAD_DRIVER_S); - } - - /* Set the pin function to its register */ - - pin2func = (pin + 1) * 4; - regaddr = REG_IO_MUX_BASE + pin2func; - putreg32(func, regaddr); - - regaddr = GPIO_REG(pin); - putreg32(cntrl, regaddr); - return OK; -} - -/**************************************************************************** - * Name: esp32c3_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ****************************************************************************/ - -void esp32c3_gpiowrite(int pin, bool value) -{ - DEBUGASSERT(pin >= 0 && pin <= ESP32C3_NGPIOS); - - if (value) - { - putreg32(1ul << pin, GPIO_OUT_W1TS_REG); - } - else - { - putreg32(1ul << pin, GPIO_OUT_W1TC_REG); - } -} - -/**************************************************************************** - * Name: esp32c3_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ****************************************************************************/ - -bool esp32c3_gpioread(int pin) -{ - uint32_t regval; - - DEBUGASSERT(pin >= 0 && pin <= ESP32C3_NGPIOS); - - regval = getreg32(GPIO_IN_REG); - return ((regval >> pin) & 1) != 0; -} - -/**************************************************************************** - * Name: esp32c3_gpio_matrix_in - * - * Description: - * Set gpio input to a signal - * NOTE: one gpio can input to several signals - * If gpio == 0x30, cancel input to the signal, input 0 to signal - * If gpio == 0x38, cancel input to the signal, input 1 to signal, - * for I2C pad - * - ****************************************************************************/ - -void esp32c3_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv) -{ - uint32_t regaddr = GPIO_FUNC0_IN_SEL_CFG_REG + (signal_idx * 4); - uint32_t regval = (gpio << GPIO_FUNC0_IN_SEL_S); - - if (inv) - { - regval |= GPIO_FUNC0_IN_INV_SEL; - } - - if (gpio != 0x34) - { - regval |= GPIO_SIG0_IN_SEL; - } - - putreg32(regval, regaddr); -} - -/**************************************************************************** - * Name: esp32c3_gpio_matrix_out - * - * Description: - * Set signal output to gpio - * NOTE: one signal can output to several gpios - * If signal_idx == 0x100, cancel output put to the gpio - * - ****************************************************************************/ - -void esp32c3_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, - bool out_inv, bool oen_inv) -{ - uint32_t regaddr = GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio * 4); - uint32_t regval = signal_idx << GPIO_FUNC0_OUT_SEL_S; - - if (gpio >= ESP32C3_NGPIOS) - { - return; - } - - putreg32((1ul << gpio), GPIO_ENABLE_W1TS_REG); - - if (out_inv) - { - regval |= GPIO_FUNC0_OUT_INV_SEL; - } - - if (oen_inv) - { - regval |= GPIO_FUNC0_OEN_INV_SEL; - } - - putreg32(regval, regaddr); -} - -/**************************************************************************** - * Name: esp32c3_gpioirqinitialize - * - * Description: - * Initialize logic to support a second level of interrupt decoding for - * GPIO pins. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32C3_GPIO_IRQ -void esp32c3_gpioirqinitialize(void) -{ - /* Setup the GPIO interrupt. */ - - g_gpio_cpuint = esp32c3_setup_irq(ESP32C3_PERIPH_GPIO, - 1, ESP32C3_INT_LEVEL); - DEBUGASSERT(g_gpio_cpuint > 0); - - /* Attach and enable the interrupt handler */ - - DEBUGVERIFY(irq_attach(ESP32C3_IRQ_GPIO, gpio_interrupt, NULL)); - up_enable_irq(ESP32C3_IRQ_GPIO); -} -#endif - -/**************************************************************************** - * Name: esp32c3_gpioirqenable - * - * Description: - * Enable the interrupt for specified GPIO IRQ - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32C3_GPIO_IRQ -void esp32c3_gpioirqenable(int irq, gpio_intrtype_t intrtype) -{ - uintptr_t regaddr; - uint32_t regval; - int pin; - - DEBUGASSERT(irq >= ESP32C3_FIRST_GPIOIRQ && irq <= ESP32C3_LAST_GPIOIRQ); - - /* Convert the IRQ number to a pin number */ - - pin = ESP32C3_IRQ2PIN(irq); - - /* Disable the GPIO interrupt during the configuration. */ - - up_disable_irq(ESP32C3_IRQ_GPIO); - - /* Get the address of the GPIO PIN register for this pin */ - - regaddr = GPIO_REG(pin); - regval = getreg32(regaddr); - regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M); - - /* Set the pin ENA field. */ - - regval |= (1 << GPIO_PIN0_INT_ENA_S); - regval |= (intrtype << GPIO_PIN_INT_TYPE_S); - putreg32(regval, regaddr); - - /* Configuration done. Re-enable the GPIO interrupt. */ - - up_enable_irq(ESP32C3_IRQ_GPIO); -} -#endif - -/**************************************************************************** - * Name: esp32c3_gpioirqdisable - * - * Description: - * Disable the interrupt for specified GPIO IRQ - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32C3_GPIO_IRQ -void esp32c3_gpioirqdisable(int irq) -{ - uintptr_t regaddr; - uint32_t regval; - int pin; - - DEBUGASSERT(irq >= ESP32C3_FIRST_GPIOIRQ && irq <= ESP32C3_LAST_GPIOIRQ); - - /* Convert the IRQ number to a pin number */ - - pin = ESP32C3_IRQ2PIN(irq); - - /* Get the address of the GPIO PIN register for this pin */ - - up_disable_irq(ESP32C3_IRQ_GPIO); - - regaddr = GPIO_REG(pin); - regval = getreg32(regaddr); - regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M); - putreg32(regval, regaddr); - - up_enable_irq(ESP32C3_IRQ_GPIO); -} -#endif - diff --git a/arch/risc-v/src/esp32c3/esp32c3_gpio.h b/arch/risc-v/src/esp32c3/esp32c3_gpio.h deleted file mode 100644 index ba32098b13196..0000000000000 --- a/arch/risc-v/src/esp32c3/esp32c3_gpio.h +++ /dev/null @@ -1,225 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_gpio.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_GPIO_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_GPIO_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */ -#define MATRIX_DETACH_IN_LOW_PIN 0x30 /* Detach non-inverted INPUT signal */ -#define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */ - -/* Bit-encoded input to esp32c3_configgpio() ********************************/ - -/* Encoded pin attributes used with esp32c3_configgpio() - * - * 8 7 6 5 4 3 2 1 0 - * -- -- -- -- -- -- -- -- -- - * FN FN FN OD PD PU F O I - */ - -#define PINMODE_SHIFT 0 -#define PINMODE_MASK (7 << PINMODE_SHIFT) -# define INPUT (1 << 0) -# define OUTPUT (1 << 1) -# define FUNCTION (1 << 2) - -#define PULLUP (1 << 3) -#define PULLDOWN (1 << 4) -#define OPEN_DRAIN (1 << 5) -#define FUNCTION_SHIFT 6 -#define FUNCTION_MASK (7 << FUNCTION_SHIFT) -# define FUNCTION_0 (1 << FUNCTION_SHIFT) -# define FUNCTION_1 (2 << FUNCTION_SHIFT) -# define FUNCTION_2 (3 << FUNCTION_SHIFT) -# define FUNCTION_3 (4 << FUNCTION_SHIFT) -# define FUNCTION_4 (5 << FUNCTION_SHIFT) - -#define INPUT_PULLUP (INPUT | PULLUP) -#define INPUT_PULLDOWN (INPUT | PULLDOWN) -#define OUTPUT_OPEN_DRAIN (OUTPUT | OPEN_DRAIN) -#define INPUT_FUNCTION (INPUT | FUNCTION) -# define INPUT_FUNCTION_0 (INPUT_FUNCTION | FUNCTION_0) -# define INPUT_FUNCTION_1 (INPUT_FUNCTION | FUNCTION_1) -# define INPUT_FUNCTION_2 (INPUT_FUNCTION | FUNCTION_2) -# define INPUT_FUNCTION_3 (INPUT_FUNCTION | FUNCTION_3) -# define INPUT_FUNCTION_4 (INPUT_FUNCTION | FUNCTION_4) -#define OUTPUT_FUNCTION (OUTPUT | FUNCTION) -# define OUTPUT_FUNCTION_0 (OUTPUT_FUNCTION | FUNCTION_0) -# define OUTPUT_FUNCTION_1 (OUTPUT_FUNCTION | FUNCTION_1) -# define OUTPUT_FUNCTION_2 (OUTPUT_FUNCTION | FUNCTION_2) -# define OUTPUT_FUNCTION_3 (OUTPUT_FUNCTION | FUNCTION_3) -# define OUTPUT_FUNCTION_4 (OUTPUT_FUNCTION | FUNCTION_4) - -/* Interrupt type used with esp32c3_gpioirqenable() */ - -#define DISABLED 0x00 -#define RISING 0x01 -#define FALLING 0x02 -#define CHANGE 0x03 -#define ONLOW 0x04 -#define ONHIGH 0x05 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/* Must be big enough to hold the above encodings */ - -typedef uint16_t gpio_pinattr_t; -typedef uint8_t gpio_intrtype_t; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c3_configgpio - * - * Description: - * Configure a GPIO pin based on encoded pin attributes. - * - ****************************************************************************/ - -int esp32c3_configgpio(int pin, gpio_pinattr_t attr); - -/**************************************************************************** - * Name: esp32c3_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ****************************************************************************/ - -void esp32c3_gpiowrite(int pin, bool value); - -/**************************************************************************** - * Name: esp32c3_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ****************************************************************************/ - -bool esp32c3_gpioread(int pin); - -/**************************************************************************** - * Name: esp32c3_gpio_matrix_in - * - * Description: - * Set gpio input to a signal - * NOTE: one gpio can input to several signals - * If signal_idx == 0x30, cancel input to the signal, input 0 to signal - * If signal_idx == 0x38, cancel input to the signal, input 1 to signal - * - ****************************************************************************/ - -void esp32c3_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); - -/**************************************************************************** - * Name: esp32c3_gpio_matrix_out - * - * Description: - * Set signal output to gpio - * NOTE: one signal can output to several gpios - * If signal_idx == 0x100, cancel output put to the gpio - * - ****************************************************************************/ - -void esp32c3_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, - bool out_inv, bool oen_inv); - -/**************************************************************************** - * Name: esp32c3_gpioirqinitialize - * - * Description: - * Initialize logic to support a second level of interrupt decoding for - * GPIO pins. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32C3_GPIO_IRQ -void esp32c3_gpioirqinitialize(void); -#else -# define esp32c3_gpioirqinitialize() -#endif - -/**************************************************************************** - * Name: esp32c3_gpioirqenable - * - * Description: - * Enable the interrupt for specified GPIO IRQ - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32C3_GPIO_IRQ -void esp32c3_gpioirqenable(int irq, gpio_intrtype_t intrtype); -#else -# define esp32c3_gpioirqenable(irq,intrtype) -#endif - -/**************************************************************************** - * Name: esp32c3_gpioirqdisable - * - * Description: - * Disable the interrupt for specified GPIO IRQ - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32C3_GPIO_IRQ -void esp32c3_gpioirqdisable(int irq); -#else -# define esp32c3_gpioirqdisable(irq) -#endif - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_GPIO_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_i2c.h b/arch/risc-v/src/esp32c3/esp32c3_i2c.h deleted file mode 100644 index 115e7d0d13550..0000000000000 --- a/arch/risc-v/src/esp32c3/esp32c3_i2c.h +++ /dev/null @@ -1,94 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_i2c.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_I2C_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_I2C_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c3_i2cbus_initialize - * - * Description: - * Initialize the selected I2C port. And return a pointer to an unique - * instance of struct i2c_master_s. This function may be called to obtain - * multiple instances of the interface, each of which may be set up with a - * different frequency and slave address. - * - * Input Parameters: - * port - Port number of the I2C interface to be initialized. - * - * Returned Value: - * Pointer to valid I2C device structure is returned on success. - * A NULL pointer is returned on failure. - * - ****************************************************************************/ - -struct i2c_master_s *esp32c3_i2cbus_initialize(int port); - -/**************************************************************************** - * Name: esp32c3_i2cbus_uninitialize - * - * Description: - * De-initialize the selected I2C port and power down the device. - * - * Input Parameters: - * dev - Device structure as returned by - * esp32c3_i2cbus_initialize() - * - * Returned Value: - * OK is returned on success. ERROR is returned when internal reference - * count mismatches or dev points to invalid hardware device. - * - ****************************************************************************/ - -int esp32c3_i2cbus_uninitialize(struct i2c_master_s *dev); - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_I2C_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_ledc.h b/arch/risc-v/src/esp32c3/esp32c3_ledc.h deleted file mode 100644 index 73ece77f67114..0000000000000 --- a/arch/risc-v/src/esp32c3/esp32c3_ledc.h +++ /dev/null @@ -1,52 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_ledc.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_LEDC_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_LEDC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c3_ledc_init - * - * Description: - * Initialize one LEDC timer for use with the upper_level PWM driver. - * - * Input Parameters: - * timer - A number identifying the timer use. - * - * Returned Value: - * On success, a pointer to the ESP32-C3 LEDC lower half PWM driver is - * returned. NULL is returned on any failure. - * - ****************************************************************************/ - -struct pwm_lowerhalf_s *esp32c3_ledc_init(int timer); - -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_LEDC_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_memorymap.h b/arch/risc-v/src/esp32c3/esp32c3_memorymap.h deleted file mode 100644 index 1323d960acac1..0000000000000 --- a/arch/risc-v/src/esp32c3/esp32c3_memorymap.h +++ /dev/null @@ -1,42 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_memorymap.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_MEMORYMAP_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_MEMORYMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Idle thread stack starts from _ebss */ - -#ifndef __ASSEMBLY__ -#define ESP32C3_IDLESTACK_BASE (uint32_t)&g_idlestack -#else -#define ESP32C3_IDLESTACK_BASE g_idlestack -#endif - -#define ESP32C3_IDLESTACK_TOP (ESP32C3_IDLESTACK_BASE + CONFIG_IDLETHREAD_STACKSIZE) - -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_MEMORYMAP_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_rsa.h b/arch/risc-v/src/esp32c3/esp32c3_rsa.h deleted file mode 100644 index 9d99ca5c9c3a1..0000000000000 --- a/arch/risc-v/src/esp32c3/esp32c3_rsa.h +++ /dev/null @@ -1,511 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_rsa.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RSA_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RSA_H - -#include -#include -#include "esp32c3_bignum.h" - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Pre-processor Macros - ****************************************************************************/ - -/* RSA Error codes */ - -#define ESP32C3_ERR_RSA_BAD_INPUT_DATA -0x4080 /* Bad input parameters to function. */ -#define ESP32C3_ERR_RSA_INVALID_PADDING -0x4100 /* Input data contains invalid padding and is rejected. */ -#define ESP32C3_ERR_RSA_KEY_GEN_FAILED -0x4180 /* Something failed during generation of a key. */ -#define ESP32C3_ERR_RSA_KEY_CHECK_FAILED -0x4200 /* Key failed to pass the validity check of the library. */ -#define ESP32C3_ERR_RSA_PUBLIC_FAILED -0x4280 /* The public key operation failed. */ -#define ESP32C3_ERR_RSA_PRIVATE_FAILED -0x4300 /* The private key operation failed. */ -#define ESP32C3_ERR_RSA_VERIFY_FAILED -0x4380 /* The PKCS#1 verification failed. */ -#define ESP32C3_ERR_RSA_OUTPUT_TOO_LARGE -0x4400 /* The output buffer for decryption is not large enough. */ -#define ESP32C3_ERR_RSA_RNG_FAILED -0x4480 /* The random generator failed to generate non-zeros. */ - -/* RSA constants */ - -#define ESP32C3_RSA_PUBLIC 0 /* Request private key operation. */ -#define ESP32C3_RSA_PRIVATE 1 /* Request public key operation. */ - -#define ESP32C3_RSA_PKCS_V15 0 /* Use PKCS#1 v1.5 encoding. */ -#define ESP32C3_RSA_PKCS_V21 1 /* Use PKCS#1 v2.1 encoding. */ - -#define ESP32C3_RSA_SIGN 1 /* Identifier for RSA signature operations. */ -#define ESP32C3_RSA_CRYPT 2 /* Identifier for RSA encryption and decryption operations. */ - -#define ESP32C3_RSA_SALT_LEN_ANY -1 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* The RSA context structure. */ - -struct esp32c3_rsa_context_s -{ - int ver; /* Always 0 */ - size_t len; /* The size of \p N in Bytes */ - - struct esp32c3_mpi_s N; /* The public modulus */ - struct esp32c3_mpi_s E; /* The public exponent */ - - struct esp32c3_mpi_s D; /* The private exponent */ - struct esp32c3_mpi_s P; /* The first prime factor */ - struct esp32c3_mpi_s Q; /* The second prime factor */ - - struct esp32c3_mpi_s DP; /* D % (P - 1) */ - struct esp32c3_mpi_s DQ; /* D % (Q - 1) */ - struct esp32c3_mpi_s QP; /* 1 / (Q % P) */ - - struct esp32c3_mpi_s RN; /* cached R^2 mod N */ - - struct esp32c3_mpi_s RP; /* cached R^2 mod P */ - struct esp32c3_mpi_s RQ; /* cached R^2 mod Q */ - - struct esp32c3_mpi_s VI; /* The cached blinding value */ - struct esp32c3_mpi_s VF; /* The cached un-blinding value */ - - int padding; /* Selects padding mode */ - int hash_id; /* Hash identifier */ -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c3_rsa_init - * - * Description: - * Initializes an RSA context - * - * Input Parameters: - * ctx - The RSA context to initialize - * padding - The padding mode to use - * hash_id - The hash identifier of - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c3_rsa_init(struct esp32c3_rsa_context_s *ctx, - int padding, - int hash_id); - -/**************************************************************************** - * Name: esp32c3_rsa_import - * - * Description: - * Imports a set of core parameters into an RSA context. - * - * Input Parameters: - * ctx - The initialized RSA context to store the parameters in - * N - The RSA modulus - * P - The first prime factor of \p N - * Q - The second prime factor of \p N - * D - The private exponent - * E - The public exponent - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int esp32c3_rsa_import(struct esp32c3_rsa_context_s *ctx, - const struct esp32c3_mpi_s *N, - const struct esp32c3_mpi_s *P, - const struct esp32c3_mpi_s *Q, - const struct esp32c3_mpi_s *D, - const struct esp32c3_mpi_s *E); - -/**************************************************************************** - * Name: esp32c3_rsa_import_raw - * - * Description: - * Imports core RSA parameters into an RSA context. - * - * Input Parameters: - * ctx - The initialized RSA context to store the parameters in - * N - The RSA modulus - * NL - The Byte length of \p N - * P - The first prime factor of \p N - * PL - The Byte length of \p P - * Q - The second prime factor of \p N - * QL - The Byte length of \p Q - * D - The private exponent - * DL - The Byte length of \p D - * E - The public exponent - * EL - The Byte length of \p E - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int esp32c3_rsa_import_raw(struct esp32c3_rsa_context_s *ctx, - unsigned char const *N, size_t NL, - unsigned char const *P, size_t PL, - unsigned char const *Q, size_t QL, - unsigned char const *D, size_t DL, - unsigned char const *E, size_t EL); - -/**************************************************************************** - * Name: esp32c3_rsa_complete - * - * Description: - * Completes an RSA context from a set of imported core parameters. - * - * Input Parameters: - * ctx - The initialized RSA context holding imported parameters - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int esp32c3_rsa_complete(struct esp32c3_rsa_context_s *ctx); - -/**************************************************************************** - * Name: esp32c3_rsa_export - * - * Description: - * Exports the core parameters of an RSA key. - * - * Input Parameters: - * ctx - The initialized RSA context - * N - The MPI to hold the RSA modulus - * P - The MPI to hold the first prime factor of \p N - * Q - The MPI to hold the second prime factor of \p N - * D - The MPI to hold the private exponent - * E - The MPI to hold the public exponent - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int esp32c3_rsa_export(const struct esp32c3_rsa_context_s *ctx, - struct esp32c3_mpi_s *N, - struct esp32c3_mpi_s *P, - struct esp32c3_mpi_s *Q, - struct esp32c3_mpi_s *D, - struct esp32c3_mpi_s *E); - -/**************************************************************************** - * Name: esp32c3_rsa_export_raw - * - * Description: - * Eexports core parameters of an RSA key in raw big-endian binary format. - * - * Input Parameters: - * ctx - The initialized RSA context - * N - The Byte array to store the RSA modulus - * NL - The size of the buffer for the modulus - * P - The Byte array to hold the first prime factor of \p N - * PL - The size of the buffer for the first prime factor - * Q - The Byte array to hold the second prime factor of \p N - * QL - The size of the buffer for the second prime factor - * D - The Byte array to hold the private exponent - * DL - The size of the buffer for the private exponent - * E - The Byte array to hold the public exponent - * EL - The size of the buffer for the public exponent - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int esp32c3_rsa_export_raw(const struct esp32c3_rsa_context_s *ctx, - unsigned char *N, size_t NL, - unsigned char *P, size_t PL, - unsigned char *Q, size_t QL, - unsigned char *D, size_t DL, - unsigned char *E, size_t EL); - -/**************************************************************************** - * Name: esp32c3_rsa_export_crt - * - * Description: - * Exports CRT parameters of a private RSA key. - * - * Input Parameters: - * ctx - The initialized RSA context - * DP - The MPI to hold \c D modulo `P-1` - * DQ - The MPI to hold \c D modulo `Q-1` - * QP - The MPI to hold modular inverse of \c Q modulo \c P - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int esp32c3_rsa_export_crt(const struct esp32c3_rsa_context_s *ctx, - struct esp32c3_mpi_s *DP, - struct esp32c3_mpi_s *DQ, - struct esp32c3_mpi_s *QP); - -/**************************************************************************** - * Name: esp32c3_rsa_set_padding - * - * Description: - * Sets padding for an already initialized RSA context. - * - * Input Parameters: - * ctx - The initialized RSA context to be configured - * padding - The padding mode to use - * hash_id - The hash identifier - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c3_rsa_set_padding(struct esp32c3_rsa_context_s *ctx, - int padding, int hash_id); - -/**************************************************************************** - * Name: esp32c3_rsa_get_len - * - * Description: - * Exports CRT parameters of a private RSA key. - * - * Input Parameters: - * ctx - The initialized RSA context - * - * Returned Value: - * length of the RSA modulus in Bytes. - * - ****************************************************************************/ - -size_t esp32c3_rsa_get_len(const struct esp32c3_rsa_context_s *ctx); - -/**************************************************************************** - * Name: esp32c3_rsa_check_pubkey - * - * Description: - * checks if a context contains at least an RSA public key.. - * - * Input Parameters: - * ctx - The initialized RSA context to check - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int esp32c3_rsa_check_pubkey(const struct esp32c3_rsa_context_s *ctx); - -/**************************************************************************** - * Name: esp32c3_rsa_check_privkey - * - * Description: - * Checks if a context contains at least an RSA private key - * and perform basic consistency checks. - * - * Input Parameters: - * ctx - The initialized RSA context to check - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int esp32c3_rsa_check_privkey(const struct esp32c3_rsa_context_s *ctx); - -/**************************************************************************** - * Name: esp32c3_rsa_check_pub_priv - * - * Description: - * Checks a public-private RSA key pair. It checks each of the contexts, - * and makes sure they match. - * - * Input Parameters: - * pub - The initialized RSA context holding the public key - * prv - The initialized RSA context holding the private key - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int esp32c3_rsa_check_pub_priv(const struct esp32c3_rsa_context_s *pub, - const struct esp32c3_rsa_context_s *prv); - -/**************************************************************************** - * Name: esp32c3_rsa_public - * - * Description: - * Performs an RSA public key operation. - * - * Input Parameters: - * ctx - The initialized RSA context to use - * input - The input buffer - * output - The output buffer - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int esp32c3_rsa_public(struct esp32c3_rsa_context_s *ctx, - const unsigned char *input, - unsigned char *output); - -/**************************************************************************** - * Name: esp32c3_rsa_private - * - * Description: - * Performs an RSA private key operation. - * - * Input Parameters: - * ctx - The initialized RSA context to use - * f_rng - The RNG function - * p_rng - The RNG context to pass to \p f_rng - * input - The input buffer - * output - The output buffer - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int esp32c3_rsa_private(struct esp32c3_rsa_context_s *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - const unsigned char *input, - unsigned char *output); - -/**************************************************************************** - * Name: esp32c3_rsa_encrypt - * - * Description: - * Adds the message padding, then performs an RSA operation. It is the - * generic wrapper for performing a PKCS#1 encryption operation using the - * \p mode from the context. - * - * Input Parameters: - * ctx - The initialized RSA context to use - * f_rng - The RNG to use - * p_rng - The RNG context to be passed to \p f_rng - * mode - The mode of operation - * ilen - The length of the plaintext in Bytes - * input - The input data to encrypt - * output - The output buffer - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int esp32c3_rsa_encrypt(struct esp32c3_rsa_context_s *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - int mode, size_t ilen, - const unsigned char *input, - unsigned char *output); - -/**************************************************************************** - * Name: esp32c3_rsa_decrypt - * - * Description: - * Performs an RSA operation, then removes the message padding. - * - * Input Parameters: - * ctx - The initialized RSA context to use - * f_rng - The RNG function - * p_rng - The RNG context to be passed to \p f_rng - * mode - The mode of operation - * olen - The point which to store the length of the plaintext - * input - The ciphertext buffer - * output - The buffer used to hold the plaintext - * output_max_len - The length in Bytes of the output buffer \p output - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int esp32c3_rsa_decrypt(struct esp32c3_rsa_context_s *ctx, - int (*f_rng)(void *, unsigned char *, size_t), - void *p_rng, - int mode, size_t *olen, - const unsigned char *input, - unsigned char *output, - size_t output_max_len); - -/**************************************************************************** - * Name: esp32c3_rsa_copy - * - * Description: - * Copies the components of an RSA context. - * - * Input Parameters: - * dst - The destination context - * src - The source context - * - * Returned Value: - * OK on success; Negated errno on failure. - * - ****************************************************************************/ - -int esp32c3_rsa_copy(struct esp32c3_rsa_context_s *dst, - const struct esp32c3_rsa_context_s *src); - -/**************************************************************************** - * Name: esp32c3_rsa_free - * - * Description: - * Frees the components of an RSA key. - * - * Input Parameters: - * ctx - The RSA context to free - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c3_rsa_free(struct esp32c3_rsa_context_s *ctx); - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_RSA_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_sha.h b/arch/risc-v/src/esp32c3/esp32c3_sha.h deleted file mode 100644 index 8c732ffcba944..0000000000000 --- a/arch/risc-v/src/esp32c3/esp32c3_sha.h +++ /dev/null @@ -1,269 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_sha.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SHA_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SHA_H - -#include -#include - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -enum esp32c3_sha_type_e -{ - ESP32C3_SHA1_1 = 0, - ESP32C3_SHA2_224, - ESP32C3_SHA2_256, - ESP32C3_SHA3_384, - ESP32C3_SHA3_512, - ESP32C3_SHA_TYPE_MAX -}; - -enum esp32c3_sha_state_e -{ - ESP32C3_SHA_STATE_INIT, - ESP32C3_SHA_STATE_IN_PROCESS -}; - -/* SHA-1 context structure */ - -struct esp32c3_sha1_context_s -{ - uint32_t total[2]; /* number of bytes processed */ - uint32_t state[5]; /* intermediate digest state */ - unsigned char buffer[64]; /* data block being processed */ - bool first_block; /* if first then true else false */ - enum esp32c3_sha_type_e mode; - enum esp32c3_sha_state_e sha_state; -}; - -/* SHA-256 context structure */ - -struct esp32c3_sha256_context_s -{ - uint32_t total[2]; /* number of bytes processed */ - uint32_t state[8]; /* intermediate digest state */ - unsigned char buffer[64]; /* data block being processed */ - bool first_block; /* if first then true, else false */ - enum esp32c3_sha_type_e mode; - enum esp32c3_sha_state_e sha_state; -}; - -/* SHA-512 context structure */ - -struct esp32c3_sha512_context_s -{ - uint64_t total[2]; /* number of bytes processed */ - uint64_t state[8]; /* intermediate digest state */ - uint8_t buffer[128]; /* data block being processed */ - - bool first_block; /* if first then true, else false */ - enum esp32c3_sha_type_e mode; - enum esp32c3_sha_state_e sha_state; -}; - -/**************************************************************************** - * Name: esp32c3_sha_init - * - * Description: - * Initialize ESP32-C3 SHA hardware. - * - * Input Parameters: - * None - * - * Returned Value: - * OK is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp32c3_sha_init(void); - -/**************************************************************************** - * Name: esp32c3_sha1_init - * - * Description: - * Initializes a SHA-1 context. - * - * Input Parameters: - * ctx - The SHA-1 context to initialize - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c3_sha1_init(struct esp32c3_sha1_context_s *ctx); - -/**************************************************************************** - * Name: esp32c3_sha1_starts - * - * Description: - * Starts a SHA-1 checksum calculation. - * - * Input Parameters: - * ctx - The SHA-1 context to initialize - * - * Returned Value: - * OK is returned on success. - * - ****************************************************************************/ - -int esp32c3_sha1_starts(struct esp32c3_sha1_context_s *ctx); - -/**************************************************************************** - * Name: esp32c3_sha1_update - * - * Description: - * Feeds an input buffer into an ongoing SHA-1 checksum calculation. - * - * Input Parameters: - * ctx - The SHA-1 context to use - * input - The buffer holding the input data - * ilen - The length of the input data in Bytes - * - * Returned Value: - * OK is returned on success. - * Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp32c3_sha1_update(struct esp32c3_sha1_context_s *ctx, - const unsigned char *input, - size_t ilen); - -/**************************************************************************** - * Name: esp32c3_sha1_finish - * - * Description: - * Finishes the SHA-1 operation, - * and writes the result to the output buffer. - * - * Input Parameters: - * ctx - The SHA-1 context to use - * output - The SHA-1 checksum result - * - * Returned Value: - * OK is returned on success. - * Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp32c3_sha1_finish(struct esp32c3_sha1_context_s *ctx, - unsigned char output[20]); - -/**************************************************************************** - * Name: esp32c3_sha256_init - * - * Description: - * Initializes a SHA-256 context. - * - * Input Parameters: - * ctx - The SHA-256 context to initialize - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c3_sha256_init(struct esp32c3_sha256_context_s *ctx); - -/**************************************************************************** - * Name: esp32c3_sha256_starts - * - * Description: - * Starts a SHA-224 or SHA-256 checksum calculation. - * - * Input Parameters: - * ctx - The SHA-256 context to initialize - * is224 - Determines which function to use - * - * Returned Value: - * OK is returned on success. - * - ****************************************************************************/ - -int esp32c3_sha256_starts(struct esp32c3_sha256_context_s *ctx, bool is224); - -/**************************************************************************** - * Name: esp32c3_sha256_update - * - * Description: - * Feeds an input buffer into an ongoing SHA-224 or SHA-256 - * checksum calculation. - * - * Input Parameters: - * ctx - The SHA-256 context to use - * input - The buffer holding the input data - * ilen - The length of the input data in Bytes - * - * Returned Value: - * OK is returned on success. - * Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp32c3_sha256_update(struct esp32c3_sha256_context_s *ctx, - const unsigned char *input, - size_t ilen); - -/**************************************************************************** - * Name: esp32c3_sha256_finish - * - * Description: - * Finishes the SHA-224 or SHA-256 operation, and writes the result to - * the output buffer. - * - * Input Parameters: - * ctx - The SHA-256 context to use - * output - The SHA-256 checksum result - * - * Returned Value: - * OK is returned on success. - * Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp32c3_sha256_finish(struct esp32c3_sha256_context_s *ctx, - unsigned char output[32]); - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SHA_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_spi.h b/arch/risc-v/src/esp32c3/esp32c3_spi.h deleted file mode 100644 index 6f983c33710c6..0000000000000 --- a/arch/risc-v/src/esp32c3/esp32c3_spi.h +++ /dev/null @@ -1,170 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_spi.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SPI_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SPI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -#ifdef CONFIG_ESP32C3_SPI - -#include - -#ifdef CONFIG_ESP32C3_SPI2 -# define ESP32C3_SPI2 2 -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c3_spibus_initialize - * - * Description: - * Initialize the selected SPI bus. - * - * Input Parameters: - * port - Port number (for hardware that has multiple SPI interfaces) - * - * Returned Value: - * Valid SPI device structure reference on success; NULL on failure - * - ****************************************************************************/ - -struct spi_dev_s *esp32c3_spibus_initialize(int port); - -/**************************************************************************** - * Name: esp32c3_spi[0|1]_select and esp32c3_spi[0|1]_status - * - * Description: - * The external functions, esp32c3_spi[0|1]_select, - * esp32c3_spi[0|1]_status, and esp32c3_spi[0|1]_cmddata must be provided - * by board-specific logic. - * These are implementations of the select, status, and cmddata methods of - * the SPI interface defined by struct spi_ops_s (include/nuttx/spi/spi.h). - * All other methods (including esp32c3_spibus_initialize()) are provided - * by common ESP32-C3 logic. To use this common SPI logic on your board: - * - * 1. Provide logic in esp32c3_board_initialize() to configure SPI chip - * select pins. - * 2. Provide esp32c3_spi[0|1]_select() and esp32c3_spi[0|1]_status() - * functions in your board-specific logic. These functions will perform - * chip selection and status operations using GPIOs in the way your - * board is configured. - * 3. If CONFIG_SPI_CMDDATA is defined in your NuttX configuration file, - * then provide esp32c3_spi[0|1]_cmddata() functions in your - * board-specific logic. These functions will perform cmd/data selection - * operations using GPIOs in the way your board is configured. - * 4. Add a call to esp32c3_spibus_initialize() in your low level - * application initialization logic. - * 5. The handle returned by esp32c3_spibus_initialize() may then be used - * to bind the SPI driver to higher level logic (e.g., calling - * mmcsd_spislotinitialize(), for example, will bind the SPI driver to - * the SPI MMC/SD driver). - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32C3_SPI2 -void esp32c3_spi2_select(struct spi_dev_s *dev, uint32_t devid, - bool selected); -uint8_t esp32c3_spi2_status(struct spi_dev_s *dev, uint32_t devid); -int esp32c3_spi2_cmddata(struct spi_dev_s *dev, - uint32_t devid, - bool cmd); -#endif - -/**************************************************************************** - * Name: esp32c3_spibus_uninitialize - * - * Description: - * Uninitialize an SPI bus. - * - * Input Parameters: - * dev - Device-specific state data - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise -1 (ERROR). - * - ****************************************************************************/ - -int esp32c3_spibus_uninitialize(struct spi_dev_s *dev); - -/**************************************************************************** - * Name: esp32c3_spislave_ctrlr_initialize - * - * Description: - * Initialize the selected SPI Slave bus. - * - * Input Parameters: - * port - Port number (for hardware that has multiple SPI Slave interfaces) - * - * Returned Value: - * Valid SPI Slave controller structure reference on success; - * NULL on failure. - * - ****************************************************************************/ - -struct spi_slave_ctrlr_s *esp32c3_spislave_ctrlr_initialize(int port); - -/**************************************************************************** - * Name: esp32c3_spislave_ctrlr_uninitialize - * - * Description: - * Uninitialize an SPI Slave bus. - * - * Input Parameters: - * ctrlr - SPI Slave controller interface instance - * - * Returned Value: - * Zero (OK) is returned on success. Otherwise -1 (ERROR). - * - ****************************************************************************/ - -int esp32c3_spislave_ctrlr_uninitialize(struct spi_slave_ctrlr_s *ctrlr); - -#endif /* CONFIG_ESP32C3_SPI */ - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SPI_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_spiflash.h b/arch/risc-v/src/esp32c3/esp32c3_spiflash.h deleted file mode 100644 index 85125b8c14dce..0000000000000 --- a/arch/risc-v/src/esp32c3/esp32c3_spiflash.h +++ /dev/null @@ -1,132 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_spiflash.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SPIFLASH_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SPIFLASH_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: spi_flash_read_encrypted - * - * Description: - * - * Read data from Encrypted Flash. - * - * If flash encryption is enabled, this function will transparently - * decrypt data as it is read. - * If flash encryption is not enabled, this function behaves the same as - * spi_flash_read(). - * - * See esp_flash_encryption_enabled() for a function to check if flash - * encryption is enabled. - * - * Parameters: - * addr - source address of the data in Flash. - * buffer - pointer to the destination buffer - * size - length of data - * - * Returned Values: esp_err_t - * - ****************************************************************************/ - -int spi_flash_read_encrypted(uint32_t addr, void *buffer, uint32_t size); - -/**************************************************************************** - * Name: esp32c3_spiflash_unmask_cpuint - * - * Description: - * Unmask CPU interrupt and keep this interrupt work when read, write, - * erase SPI Flash. - * - * By default, all CPU interrupts are masked. - * - * Input Parameters: - * cpuint - CPU interrupt ID - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c3_spiflash_unmask_cpuint(int cpuint); - -/**************************************************************************** - * Name: esp32c3_spiflash_unmask_cpuint - * - * Description: - * Mask CPU interrupt and disable this interrupt when read, write, - * erase SPI Flash. - * - * By default, all CPU interrupts are masked. - * - * Input Parameters: - * cpuint - CPU interrupt ID - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c3_spiflash_mask_cpuint(int cpuint); - -/**************************************************************************** - * Name: esp32c3_spiflash_init - * - * Description: - * Initialize ESP32-C3 SPI flash driver. - * - * Returned Value: - * OK if success or a negative value if fail. - * - ****************************************************************************/ - -int esp32c3_spiflash_init(void); - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_SPIFLASH_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_tim.h b/arch/risc-v/src/esp32c3/esp32c3_tim.h deleted file mode 100644 index 3d5cda5393a78..0000000000000 --- a/arch/risc-v/src/esp32c3/esp32c3_tim.h +++ /dev/null @@ -1,141 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_tim.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_TIM_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Helpers ******************************************************************/ - -#define ESP32C3_TIM_START(d) ((d)->ops->start(d)) -#define ESP32C3_TIM_STOP(d) ((d)->ops->stop(d)) -#define ESP32C3_TIM_CLEAR(d) ((d)->ops->clear(d)) -#define ESP32C3_TIM_SETMODE(d, m) ((d)->ops->setmode(d, m)) -#define ESP32C3_TIM_CLK_SRC(d, s) ((d)->ops->setclksrc(d, s)) -#define ESP32C3_TIM_SETPRE(d, p) ((d)->ops->setpre(d, p)) -#define ESP32C3_TIM_GETCTR(d, v) ((d)->ops->getcounter(d, v)) -#define ESP32C3_TIM_SETCTR(d, v) ((d)->ops->setcounter(d, v)) -#define ESP32C3_TIM_RLD_NOW(d) ((d)->ops->reloadnow(d)) -#define ESP32C3_TIM_GETALRVL(d, v) ((d)->ops->getalarmvalue(d, v)) -#define ESP32C3_TIM_SETALRVL(d, v) ((d)->ops->setalarmvalue(d, v)) -#define ESP32C3_TIM_SETALRM(d, e) ((d)->ops->setalarm(d, e)) -#define ESP32C3_TIM_SETARLD(d, e) ((d)->ops->setautoreload(d, e)) -#define ESP32C3_TIM_SETISR(d, hnd, arg) ((d)->ops->setisr(d, hnd, arg)) -#define ESP32C3_TIM_ENABLEINT(d) ((d)->ops->enableint(d)) -#define ESP32C3_TIM_DISABLEINT(d) ((d)->ops->disableint(d)) -#define ESP32C3_TIM_ACKINT(d) ((d)->ops->ackint(d)) -#define ESP32C3_TIM_CHECKINT(d) ((d)->ops->checkint(d)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* Instances of Timer */ - -enum esp32c3_tim_inst_e -{ - ESP32C3_TIMER0 = 0, /* Timer 0 from Timer Group 0 */ - ESP32C3_TIMER1, /* Timer 0 from Timer Group 1 */ - ESP32C3_SYSTIM, /* SYSTIMER 1 */ -}; - -/* Timer mode */ - -enum esp32c3_tim_clksrc_e -{ - ESP32C3_TIM_APB_CLK, - ESP32C3_TIM_XTAL_CLK, -}; - -/* Timer mode */ - -enum esp32c3_tim_mode_e -{ - ESP32C3_TIM_MODE_DOWN, - ESP32C3_TIM_MODE_UP, -}; - -/* ESP32-C3 TIM device */ - -struct esp32c3_tim_dev_s -{ - struct esp32c3_tim_ops_s *ops; -}; - -/* ESP32-C3 TIM ops */ - -/* This is a struct containing the pointers to the timer operations */ - -struct esp32c3_tim_ops_s -{ - /* Timer tasks */ - - void (*start)(struct esp32c3_tim_dev_s *dev); - void (*stop)(struct esp32c3_tim_dev_s *dev); - void (*clear)(struct esp32c3_tim_dev_s *dev); - - /* Timer operations */ - - void (*setmode)(struct esp32c3_tim_dev_s *dev, - enum esp32c3_tim_mode_e mode); - void (*setclksrc)(struct esp32c3_tim_dev_s *dev, - enum esp32c3_tim_clksrc_e src); - void (*setpre)(struct esp32c3_tim_dev_s *dev, uint16_t pre); - void (*getcounter)(struct esp32c3_tim_dev_s *dev, - uint64_t *value); - void (*setcounter)(struct esp32c3_tim_dev_s *dev, uint64_t value); - void (*reloadnow)(struct esp32c3_tim_dev_s *dev); - void (*getalarmvalue)(struct esp32c3_tim_dev_s *dev, - uint64_t *value); - void (*setalarmvalue)(struct esp32c3_tim_dev_s *dev, - uint64_t value); - void (*setalarm)(struct esp32c3_tim_dev_s *dev, bool enable); - void (*setautoreload)(struct esp32c3_tim_dev_s *dev, bool enable); - - /* Timer interrupts */ - - int (*setisr)(struct esp32c3_tim_dev_s *dev, xcpt_t handler, - void * arg); - void (*enableint)(struct esp32c3_tim_dev_s *dev); - void (*disableint)(struct esp32c3_tim_dev_s *dev); - void (*ackint)(struct esp32c3_tim_dev_s *dev); - int (*checkint)(struct esp32c3_tim_dev_s *dev); -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -struct esp32c3_tim_dev_s *esp32c3_tim_init(int timer); -void esp32c3_tim_deinit(struct esp32c3_tim_dev_s *dev); - -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_TIM_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_twai.h b/arch/risc-v/src/esp32c3/esp32c3_twai.h deleted file mode 100644 index d844426a61658..0000000000000 --- a/arch/risc-v/src/esp32c3/esp32c3_twai.h +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_twai.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_TWAI_H -#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_TWAI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "hardware/esp32c3_twai.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" -{ -#endif - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c3_twaiinitialize - * - * Description: - * Initialize the selected CAN port - * - * Input Parameters: - * Port number (for hardware that has multiple TWAI interfaces) - * - * Returned Value: - * Valid TWAI device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -#if defined(CONFIG_CAN) && defined(CONFIG_ESP32C3_TWAI) -struct can_dev_s; -struct can_dev_s *esp32c3_twaiinitialize(int port); -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_TWAI_H */ diff --git a/arch/risc-v/src/esp32c3/esp32c3_uid.c b/arch/risc-v/src/esp32c3/esp32c3_uid.c deleted file mode 100644 index e823d05628500..0000000000000 --- a/arch/risc-v/src/esp32c3/esp32c3_uid.c +++ /dev/null @@ -1,55 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_uid.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "hardware/esp32c3_efuse.h" -#include "esp32c3.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c3_get_uniqueid - * - * Description: - * Get CPU unique ID. - * - * Parameters: - * uniqueid - unique ID buffer - * - ****************************************************************************/ - -void esp32c3_get_uniqueid(uint8_t *uniqueid) -{ - int i; - - for (i = 0; i < 16; i++) - { - uniqueid[i] = getreg8(EFUSE_RD_SYS_DATA_PART1_0_REG + i); - } -} diff --git a/arch/risc-v/src/esp32c3/esp32c3_userspace.c b/arch/risc-v/src/esp32c3/esp32c3_userspace.c deleted file mode 100644 index 5628c90603a83..0000000000000 --- a/arch/risc-v/src/esp32c3/esp32c3_userspace.c +++ /dev/null @@ -1,403 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/esp32c3_userspace.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include - -#include "riscv_internal.h" -#include "esp32c3.h" -#include "esp32c3_userspace.h" -#include "hardware/esp32c3_cache_memory.h" -#include "hardware/extmem_reg.h" - -#ifdef CONFIG_BUILD_PROTECTED - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define USER_IMAGE_OFFSET CONFIG_ESP32C3_USER_IMAGE_OFFSET - -#define MMU_BLOCK0_VADDR SOC_DROM_LOW -#define MMU_SIZE 0x3f0000 -#define MMU_BLOCK63_VADDR (MMU_BLOCK0_VADDR + MMU_SIZE) - -/* Cache MMU block size */ - -#define MMU_BLOCK_SIZE 0x00010000 /* 64 KB */ - -/* Cache MMU address mask (MMU tables ignore bits which are zero) */ - -#define MMU_FLASH_MASK (~(MMU_BLOCK_SIZE - 1)) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct user_image_load_header_s -{ - uintptr_t drom_vma; /* Destination address (VMA) for DROM region */ - uintptr_t drom_lma; /* Flash offset (LMA) for start of DROM region */ - uintptr_t drom_size; /* Size of DROM region */ - uintptr_t irom_vma; /* Destination address (VMA) for IROM region */ - uintptr_t irom_lma; /* Flash offset (LMA) for start of IROM region */ - uintptr_t irom_size; /* Size of IROM region */ -}; - -/**************************************************************************** - * ROM Function Prototypes - ****************************************************************************/ - -extern uint32_t cache_suspend_icache(void); -extern void cache_resume_icache(uint32_t val); -extern void cache_invalidate_icache_all(void); -extern int cache_dbus_mmu_set(uint32_t ext_ram, uint32_t vaddr, - uint32_t paddr, uint32_t psize, uint32_t num, - uint32_t fixed); -extern int cache_ibus_mmu_set(uint32_t ext_ram, uint32_t vaddr, - uint32_t paddr, uint32_t psize, uint32_t num, - uint32_t fixed); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct user_image_load_header_s g_header; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: calc_mmu_pages - * - * Description: - * Calculate the required number of MMU pages for mapping a given region - * from External Flash into Internal RAM. - * - * Input Parameters: - * size - Length of the region to map - * vaddr - Starting External Flash offset to map to Internal RAM - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static inline uint32_t calc_mmu_pages(uint32_t size, uint32_t vaddr) -{ - return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_BLOCK_SIZE - 1) / - MMU_BLOCK_SIZE; -} - -/**************************************************************************** - * Name: configure_mmu - * - * Description: - * Configure the External Flash MMU and Cache for enabling access to code - * and read-only data of the userspace image. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static noinline_function IRAM_ATTR void configure_mmu(void) -{ - uint32_t drom_lma_aligned; - uint32_t drom_vma_aligned; - uint32_t drom_page_count; - uint32_t irom_lma_aligned; - uint32_t irom_vma_aligned; - uint32_t irom_page_count; - - size_t partition_offset = USER_IMAGE_OFFSET; - uint32_t app_drom_lma = partition_offset + g_header.drom_lma; - uint32_t app_drom_size = g_header.drom_size; - uint32_t app_drom_vma = g_header.drom_vma; - uint32_t app_irom_lma = partition_offset + g_header.irom_lma; - uint32_t app_irom_size = g_header.irom_size; - uint32_t app_irom_vma = g_header.irom_vma; - - uint32_t autoload = cache_suspend_icache(); - cache_invalidate_icache_all(); - - drom_lma_aligned = app_drom_lma & MMU_FLASH_MASK; - drom_vma_aligned = app_drom_vma & MMU_FLASH_MASK; - drom_page_count = calc_mmu_pages(app_drom_size, app_drom_vma); - ASSERT(cache_dbus_mmu_set(MMU_ACCESS_FLASH, drom_vma_aligned, - drom_lma_aligned, 64, - (int)drom_page_count, 0) == 0); - - irom_lma_aligned = app_irom_lma & MMU_FLASH_MASK; - irom_vma_aligned = app_irom_vma & MMU_FLASH_MASK; - irom_page_count = calc_mmu_pages(app_irom_size, app_irom_vma); - ASSERT(cache_ibus_mmu_set(MMU_ACCESS_FLASH, irom_vma_aligned, - irom_lma_aligned, 64, - (int)irom_page_count, 0) == 0); - - cache_resume_icache(autoload); -} - -/**************************************************************************** - * Name: map_flash - * - * Description: - * Map a region of the External Flash memory to Internal RAM. - * - * Input Parameters: - * src_addr - Starting External Flash offset to map to Internal RAM - * size - Length of the region to map - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static noinline_function IRAM_ATTR const void *map_flash(uint32_t src_addr, - uint32_t size) -{ - uint32_t src_addr_aligned; - uint32_t page_count; - - uint32_t autoload = cache_suspend_icache(); - cache_invalidate_icache_all(); - - src_addr_aligned = src_addr & MMU_FLASH_MASK; - page_count = calc_mmu_pages(size, src_addr); - ASSERT(cache_dbus_mmu_set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, - src_addr_aligned, 64, (int)page_count, 0) == 0); - - cache_resume_icache(autoload); - - return (void *)(MMU_BLOCK63_VADDR + (src_addr - src_addr_aligned)); -} - -/**************************************************************************** - * Name: load_header - * - * Description: - * Load IROM and DROM information from image header to enable the correct - * configuration of the Flash MMU and Cache. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void load_header(void) -{ - size_t length = sizeof(struct user_image_load_header_s); - const uint8_t *data = - (const uint8_t *)map_flash(USER_IMAGE_OFFSET, length); - - DEBUGASSERT(data != NULL); - - memcpy(&g_header, data, length); -} - -/**************************************************************************** - * Name: initialize_data - * - * Description: - * Initialize data sections of the userspace image. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void initialize_data(void) -{ - uint8_t *dest; - uint8_t *end; - size_t length = USERSPACE->us_dataend - USERSPACE->us_datastart; - const uint8_t *src = - (const uint8_t *)map_flash(USER_IMAGE_OFFSET + USERSPACE->us_datasource, - length); - - DEBUGASSERT(src != NULL); - - dest = (uint8_t *)USERSPACE->us_datastart; - end = (uint8_t *)USERSPACE->us_dataend; - - while (dest != end) - { - *dest++ = *src++; - } -} - -/**************************************************************************** - * Name: configure_mpu - * - * Description: - * Configure the MPU for kernel/userspace separation. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void configure_mpu(void) -{ - const uintptr_t R = PMPCFG_R; - const uintptr_t RW = PMPCFG_R | PMPCFG_W; - const uintptr_t RX = PMPCFG_R | PMPCFG_X; - const uintptr_t RWX = PMPCFG_R | PMPCFG_W | PMPCFG_X; - - /* Ensure PMP had not been previously configured by the bootloader */ - - DEBUGASSERT(riscv_configured_pmp_regions() == 0); - - /* Region for the userspace read-only data in SPI Flash */ - - riscv_config_pmp_region(0, PMPCFG_A_TOR, UDROM_START, 0); - riscv_config_pmp_region(1, PMPCFG_A_TOR | R, UDROM_END, 0); - - /* Region for the userspace data. - * NOTE: User-space heap may extend further than UDRAM_END. - */ - - riscv_config_pmp_region(2, PMPCFG_A_TOR, UDRAM_START, 0); - riscv_config_pmp_region(3, PMPCFG_A_TOR | RW, SOC_DRAM_HIGH, 0); - - /* Region for the memory-mapped functions located in internal ROM */ - - riscv_config_pmp_region(4, PMPCFG_L | PMPCFG_A_NAPOT | R, - SOC_DROM_MASK_LOW, - SOC_DROM_MASK_HIGH - SOC_DROM_MASK_LOW); - - riscv_config_pmp_region(5, PMPCFG_L | PMPCFG_A_TOR | RX, - SOC_IROM_MASK_HIGH, - 0); - - /* Region for the exception vectors located in internal SRAM area reserved - * for the kernel space. - */ - - riscv_config_pmp_region(6, PMPCFG_A_NAPOT | RX, - VECTORS_START, - VECTORS_END - VECTORS_START); - - /* Region for the userspace code located in internal SRAM */ - - riscv_config_pmp_region(7, PMPCFG_A_TOR, UIRAM_START, 0); - riscv_config_pmp_region(8, PMPCFG_A_TOR | RWX, UIRAM_END, 0); - - /* Region for the userspace code in SPI Flash */ - - riscv_config_pmp_region(9, PMPCFG_A_TOR, UIROM_START, 0); - riscv_config_pmp_region(10, PMPCFG_A_TOR | RX, UIROM_END, 0); - - /* Region for peripheral addresses */ - - riscv_config_pmp_region(11, PMPCFG_A_TOR, SOC_PERIPHERAL_HIGH, 0); - - /* Region for the remainder of the address space */ - - riscv_config_pmp_region(12, PMPCFG_L | PMPCFG_A_TOR, UINT32_MAX, 0); - riscv_config_pmp_region(13, PMPCFG_L | PMPCFG_A_NA4, UINT32_MAX, 0); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c3_userspace - * - * Description: - * For the case of the separate user/kernel space build, perform whatever - * platform specific initialization of the user memory is required. - * Normally this just means initializing the userspace .data and .bss - * segments. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c3_userspace(void) -{ - uint8_t *dest; - uint8_t *end; - - /* Load IROM and DROM information from image header */ - - load_header(); - - /* Configure the MMU for enabling access to the userspace image */ - - configure_mmu(); - - /* Clear all of userspace .bss */ - - DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && - USERSPACE->us_bssstart <= USERSPACE->us_bssend); - - dest = (uint8_t *)USERSPACE->us_bssstart; - end = (uint8_t *)USERSPACE->us_bssend; - - while (dest != end) - { - *dest++ = 0; - } - - /* Initialize all of userspace .data */ - - DEBUGASSERT(USERSPACE->us_datasource != 0 && - USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && - USERSPACE->us_datastart <= USERSPACE->us_dataend); - - initialize_data(); - - /* Configure MPU / PMP to grant access to the userspace */ - - configure_mpu(); -} - -#endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/risc-v/src/esp32c3/esp_coex_adapter.c b/arch/risc-v/src/esp32c3/esp_coex_adapter.c new file mode 100644 index 0000000000000..d994285bd0999 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp_coex_adapter.c @@ -0,0 +1,587 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp_coex_adapter.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "esp_hr_timer.h" +#include "esp_wlan.h" + +#include "esp_attr.h" +#include "esp_timer.h" +#include "soc/rtc.h" +#include "esp_private/esp_clk.h" +#include "esp_coexist_adapter.h" +#include "rom/ets_sys.h" +#include "soc/soc_caps.h" +#include "soc/system_reg.h" +#include "esp_modem_wrapper.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define OSI_FUNCS_TIME_BLOCKING 0xffffffff + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int64_t esp_coex_esp_timer_get_time_wrapper(void); +static int32_t esp_coex_semphr_take_from_isr_wrapper(void *semphr, + void *hptw); +static int32_t esp_coex_semphr_give_from_isr_wrapper(void *semphr, + void *hptw); +static int esp_coex_is_in_isr_wrapper(void); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +coex_adapter_funcs_t g_coex_adapter_funcs = +{ + ._version = COEX_ADAPTER_VERSION, + ._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper, + ._semphr_create = esp_coex_common_semphr_create_wrapper, + ._semphr_delete = esp_coex_common_semphr_delete_wrapper, + ._semphr_take_from_isr = esp_coex_semphr_take_from_isr_wrapper, + ._semphr_give_from_isr = esp_coex_semphr_give_from_isr_wrapper, + ._semphr_take = esp_coex_common_semphr_take_wrapper, + ._semphr_give = esp_coex_common_semphr_give_wrapper, + ._is_in_isr = esp_coex_is_in_isr_wrapper, + ._malloc_internal = esp_coex_common_malloc_internal_wrapper, + ._free = free, + ._esp_timer_get_time = esp_coex_esp_timer_get_time_wrapper, + ._timer_disarm = esp_coex_common_timer_disarm_wrapper, + ._timer_done = esp_coex_common_timer_done_wrapper, + ._timer_setfn = esp_coex_common_timer_setfn_wrapper, + ._timer_arm_us = esp_coex_common_timer_arm_us_wrapper, + ._magic = COEX_ADAPTER_MAGIC, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_coex_esp_timer_get_time_wrapper + * + * Description: + * This function retrieves the current time of the High Resolution Timer + * in microseconds. It is a wrapper around the esp_hr_timer_time_us + * function, providing a consistent interface for the coexistence module. + * + * Input Parameters: + * None. + * + * Returned Value: + * The current time of the High Resolution Timer in microseconds, as a + * 64-bit integer. + * + ****************************************************************************/ + +static IRAM_ATTR int64_t esp_coex_esp_timer_get_time_wrapper(void) +{ + return (int64_t)esp_hr_timer_time_us(); +} + +/**************************************************************************** + * Name: esp_coex_semphr_take_from_isr_wrapper + * + * Description: + * Take a semaphore from an ISR + * + * Input Parameters: + * semphr - Semaphore data pointer. + * hptw - Unused. + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t IRAM_ATTR esp_coex_semphr_take_from_isr_wrapper(void *semphr, + void *hptw) +{ + *(int *)hptw = 0; + + return nuttx_err_to_freertos(nxsem_trywait(semphr)); +} + +/**************************************************************************** + * Name: esp_coex_semphr_give_from_isr_wrapper + * + * Description: + * Post semaphore + * + * Input Parameters: + * semphr - Semaphore data pointer + * hptw - Unused. + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t IRAM_ATTR esp_coex_semphr_give_from_isr_wrapper(void *semphr, + void *hptw) +{ + *(int *)hptw = 0; + + return esp_coex_common_semphr_give_wrapper(semphr); +} + +/**************************************************************************** + * Name: esp_coex_is_in_isr_wrapper + * + * Description: + * This function checks if the current context is an interrupt service + * routine (ISR). It is a wrapper around the NuttX up_interrupt_context + * function. + * + * Input Parameters: + * None + * + * Returned Value: + * Returns 1 if the current context is an ISR, 0 otherwise. + * + ****************************************************************************/ + +static int IRAM_ATTR esp_coex_is_in_isr_wrapper(void) +{ + return (int)up_interrupt_context(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_coex_common_env_is_chip_wrapper + * + * Description: + * This function checks if the environment is a chip or FPGA. + * + * Input Parameters: + * None + * + * Returned Value: + * Returns true if the environment is a chip, false if it's an FPGA. + * + ****************************************************************************/ + +bool IRAM_ATTR esp_coex_common_env_is_chip_wrapper(void) +{ +#ifdef CONFIG_IDF_ENV_FPGA + return false; +#else + return true; +#endif +} + +/**************************************************************************** + * Name: esp_coex_common_spin_lock_create_wrapper + * + * Description: + * Create spin lock in SMP mode + * + * Input Parameters: + * None + * + * Returned Value: + * Spin lock data pointer + * + ****************************************************************************/ + +void *esp_coex_common_spin_lock_create_wrapper(void) +{ + spinlock_t *lock; + int tmp; + + tmp = sizeof(*lock); + lock = kmm_malloc(tmp); + if (!lock) + { + wlerr("Failed to alloc %d memory\n", tmp); + DEBUGPANIC(); + } + + spin_initialize(lock, SP_UNLOCKED); + + return lock; +} + +/**************************************************************************** + * Name: esp_coex_common_int_disable_wrapper + * + * Description: + * Enter critical section by disabling interrupts and taking the spin lock + * if in SMP mode. + * + * Input Parameters: + * wifi_int_mux - Spin lock data pointer + * + * Returned Value: + * CPU PS value. + * + ****************************************************************************/ + +uint32_t IRAM_ATTR esp_coex_common_int_disable_wrapper(void *wifi_int_mux) +{ + irqstate_t flags; + + flags = spin_lock_irqsave((spinlock_t *)wifi_int_mux); + + return (uint32_t)flags; +} + +/**************************************************************************** + * Name: esp_coex_common_int_restore_wrapper + * + * Description: + * Exit from critical section by enabling interrupts and releasing the spin + * lock if in SMP mode. + * + * Input Parameters: + * wifi_int_mux - Spin lock data pointer + * tmp - CPU PS value. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp_coex_common_int_restore_wrapper(void *wifi_int_mux, + uint32_t tmp) +{ + irqstate_t flags = (irqstate_t)tmp; + + spin_unlock_irqrestore((spinlock_t *)wifi_int_mux, flags); +} + +/**************************************************************************** + * Name: esp_task_yield_from_isr + * + * Description: + * Perform a solicited context switch on FreeRTOS. Do nothing in NuttX. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp_coex_common_task_yield_from_isr_wrapper(void) +{ +} + +/**************************************************************************** + * Name: esp_coex_common_semphr_create_wrapper + * + * Description: + * Create and initialize semaphore + * + * Input Parameters: + * max - No meanining for NuttX + * init - semaphore initialization value + * + * Returned Value: + * Semaphore data pointer + * + ****************************************************************************/ + +void *esp_coex_common_semphr_create_wrapper(uint32_t max, uint32_t init) +{ + int ret; + sem_t *sem; + int tmp; + + tmp = sizeof(sem_t); + sem = kmm_malloc(tmp); + if (!sem) + { + wlerr("Failed to alloc %d memory\n", tmp); + return NULL; + } + + ret = nxsem_init(sem, 0, init); + if (ret) + { + wlerr("Failed to initialize sem error=%d\n", ret); + kmm_free(sem); + return NULL; + } + + return sem; +} + +/**************************************************************************** + * Name: esp_coex_common_semphr_delete_wrapper + * + * Description: + * Delete semaphore + * + * Input Parameters: + * semphr - Semaphore data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp_coex_common_semphr_delete_wrapper(void *semphr) +{ + sem_t *sem = (sem_t *)semphr; + + nxsem_destroy(sem); + kmm_free(sem); +} + +/**************************************************************************** + * Name: esp_coex_common_semphr_take_wrapper + * + * Description: + * This function attempts to take (wait for) a semaphore within a certain + * period of time. It is a wrapper around the NuttX nxsem_wait and + * nxsem_tickwait functions, providing error handling and translation + * between NuttX and ESP-IDF error codes. + * + * Input Parameters: + * semphr - Pointer to the semaphore data structure. + * block_time_tick - The maximum number of system ticks to wait. + * + * Returned Value: + * Returns 0 if the semaphore was successfully taken, or a negative error + * code if the operation failed or the timeout expired. + * + ****************************************************************************/ + +int32_t esp_coex_common_semphr_take_wrapper(void *semphr, + uint32_t block_time_tick) +{ + int ret; + sem_t *sem = (sem_t *)semphr; + + if (block_time_tick == OSI_FUNCS_TIME_BLOCKING) + { + ret = nxsem_wait(sem); + } + else + { + if (block_time_tick > 0) + { + ret = nxsem_tickwait(sem, block_time_tick); + } + else + { + ret = nxsem_trywait(sem); + } + } + + if (ret) + { + wlerr("ERROR: Failed to wait sem in %lu ticks. Error=%d\n", + block_time_tick, ret); + } + + return nuttx_err_to_freertos(ret); +} + +/**************************************************************************** + * Name: esp_coex_common_semphr_give_wrapper + * + * Description: + * This function posts (releases) a semaphore. It is a wrapper around the + * NuttX nxsem_post function, providing error handling and translation + * between NuttX and ESP-IDF error codes. + * + * Input Parameters: + * semphr - Pointer to the semaphore data structure. + * + * Returned Value: + * Returns 0 if the semaphore was successfully posted, or a negative error + * code if the operation failed. + * + ****************************************************************************/ + +int32_t esp_coex_common_semphr_give_wrapper(void *semphr) +{ + int ret; + sem_t *sem = (sem_t *)semphr; + + ret = nxsem_post(sem); + if (ret) + { + wlerr("Failed to post sem error=%d\n", ret); + } + + return nuttx_err_to_freertos(ret); +} + +/**************************************************************************** + * Name: esp_coex_common_timer_disarm_wrapper + * + * Description: + * Disable timer + * + * Input Parameters: + * timer - timer data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp_coex_common_timer_disarm_wrapper(void *timer) +{ + ets_timer_disarm(timer); +} + +/**************************************************************************** + * Name: esp_coex_common_timer_done_wrapper + * + * Description: + * Disable and free timer + * + * Input Parameters: + * ptimer - timer data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp_coex_common_timer_done_wrapper(void *ptimer) +{ + ets_timer_done(ptimer); +} + +/**************************************************************************** + * Name: esp_coex_common_timer_setfn_wrapper + * + * Description: + * Set timer callback function and private data + * + * Input Parameters: + * ptimer - Timer data pointer + * pfunction - Callback function + * parg - Callback function private data + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp_coex_common_timer_setfn_wrapper(void *ptimer, + void *pfunction, + void *parg) +{ + ets_timer_setfn(ptimer, pfunction, parg); +} + +/**************************************************************************** + * Name: esp_coex_common_timer_arm_us_wrapper + * + * Description: + * Set timer timeout period and repeat flag + * + * Input Parameters: + * ptimer - timer data pointer + * us - micro seconds + * repeat - true: run cycle, false: run once + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp_coex_common_timer_arm_us_wrapper(void *ptimer, + uint32_t us, + bool repeat) +{ + ets_timer_arm_us(ptimer, us, repeat); +} + +/**************************************************************************** + * Name: esp_coex_common_malloc_internal_wrapper + * + * Description: + * Drivers allocate a block of memory + * + * Input Parameters: + * size - memory size + * + * Returned Value: + * Memory pointer + * + ****************************************************************************/ + +IRAM_ATTR void *esp_coex_common_malloc_internal_wrapper(size_t size) +{ + return kmm_malloc(size); +} + +/**************************************************************************** + * Name: esp_coex_common_clk_slowclk_cal_get_wrapper + * + * Description: + * Get the calibration value of RTC slow clock + * + * Input Parameters: + * None + * + * Returned Value: + * The calibration value obtained using rtc_clk_cal + * + ****************************************************************************/ + +uint32_t esp_coex_common_clk_slowclk_cal_get_wrapper(void) +{ + /* The bit width of WiFi light sleep clock calibration is 12 while the one + * of system is 19. It should shift 19 - 12 = 7. + */ + + if (GET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_XTAL)) + { + uint64_t time_per_us = 1000000ULL; + return (((time_per_us << RTC_CLK_CAL_FRACT) / (MHZ)) >> + (RTC_CLK_CAL_FRACT - SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH)); + } + else + { + return (esp_clk_slowclk_cal_get() >> + (RTC_CLK_CAL_FRACT - SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH)); + } +} diff --git a/arch/risc-v/src/esp32c3/esp_wifi_adapter.c b/arch/risc-v/src/esp32c3/esp_wifi_adapter.c new file mode 100644 index 0000000000000..0ac761bd47e13 --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp_wifi_adapter.c @@ -0,0 +1,5615 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp_wifi_adapter.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "esp_irq.h" +#include "esp_hr_timer.h" + +#include "esp_types.h" +#include "esp_random.h" +#include "esp_mac.h" +#include "esp_intr_alloc.h" +#include "esp_attr.h" +#include "esp_log.h" +#include "esp_event.h" +#include "esp_timer.h" +#include "esp_private/wifi_os_adapter.h" +#include "esp_private/wifi.h" +#include "esp_phy_init.h" +#include "soc/rtc_cntl_reg.h" +#include "soc/syscon_reg.h" +#include "soc/system_reg.h" +#include "esp_private/periph_ctrl.h" +#include "esp_private/esp_clk.h" +#include "os.h" +#include "esp_smartconfig.h" +#include "esp_coexist_internal.h" +#include "rom/ets_sys.h" +#include "esp_modem_wrapper.h" + +#include "esp_wlan.h" +#include "esp_wifi_adapter.h" +#include "esp_wifi_utils.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MHZ (1000000) + +#define PHY_RF_MASK ((1 << PHY_BT_MODULE) | (1 << PHY_WIFI_MODULE)) + +#define WIFI_CONNECT_TIMEOUT CONFIG_ESPRESSIF_WIFI_CONNECT_TIMEOUT + +#define ESP_WIFI_11B_MAX_BITRATE 11 +#define ESP_WIFI_11G_MAX_BITRATE 54 +#define ESP_WIFI_11N_MCS7_HT20_BITRATE 72 +#define ESP_WIFI_11N_MCS7_HT40_BITRATE 150 + +#ifndef CONFIG_EXAMPLE_WIFI_LISTEN_INTERVAL +#define CONFIG_EXAMPLE_WIFI_LISTEN_INTERVAL 3 +#endif + +#define DEFAULT_LISTEN_INTERVAL CONFIG_EXAMPLE_WIFI_LISTEN_INTERVAL + +#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal + +#define ets_timer _ETSTIMER_ + +/* CONFIG_POWER_SAVE_MODEM */ + +#if defined(CONFIG_ESP_POWER_SAVE_MIN_MODEM) +# define DEFAULT_PS_MODE WIFI_PS_MIN_MODEM +#elif defined(CONFIG_ESP_POWER_SAVE_MAX_MODEM) +# define DEFAULT_PS_MODE WIFI_PS_MAX_MODEM +#elif defined(CONFIG_ESP_POWER_SAVE_NONE) +# define DEFAULT_PS_MODE WIFI_PS_NONE +#else +# define DEFAULT_PS_MODE WIFI_PS_NONE +#endif + +#define ESP_MAX_PRIORITIES (25) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Wi-Fi event ID */ + +enum wifi_adpt_evt_e +{ + WIFI_ADPT_EVT_SCAN_DONE = 0, + WIFI_ADPT_EVT_STA_START, + WIFI_ADPT_EVT_STA_CONNECT, + WIFI_ADPT_EVT_STA_DISCONNECT, + WIFI_ADPT_EVT_STA_AUTHMODE_CHANGE, + WIFI_ADPT_EVT_STA_STOP, + WIFI_ADPT_EVT_AP_START, + WIFI_ADPT_EVT_AP_STOP, + WIFI_ADPT_EVT_AP_STACONNECTED, + WIFI_ADPT_EVT_AP_STADISCONNECTED, + WIFI_ADPT_EVT_MAX, +}; + +/* Wi-Fi Station state */ + +enum wifi_sta_state +{ + WIFI_STA_STATE_NULL, + WIFI_STA_STATE_START, + WIFI_STA_STATE_CONNECT, + WIFI_STA_STATE_DISCONNECT, + WIFI_STA_STATE_STOP +}; + +/* Wi-Fi interrupt adapter private data */ + +struct irq_adpt +{ + void (*func)(void *arg); /* Interrupt callback function */ + void *arg; /* Interrupt private data */ +}; + +/* Wi-Fi message queue private data */ + +struct mq_adpt +{ + struct file mq; /* Message queue handle */ + uint32_t msgsize; /* Message size */ + char name[16]; /* Message queue name */ +}; + +/* Wi-Fi time private data */ + +struct time_adpt +{ + time_t sec; /* Second value */ + suseconds_t usec; /* Micro second value */ +}; + +/* Wi-Fi event private data */ + +struct evt_adpt +{ + sq_entry_t entry; /* Sequence entry */ + int32_t id; /* Event ID */ + uint8_t buf[0]; /* Event private data */ +}; + +/* Wi-Fi event notification private data */ + +struct wifi_notify +{ + bool assigned; /* Flag indicate if it is used */ + pid_t pid; /* Signal's target thread PID */ + struct sigevent event; /* Signal event private data */ + struct sigwork_s work; /* Signal work private data */ +}; + +/* Wi-Fi NVS private data */ + +struct nvs_adpt +{ + char *index_name; +}; + +/* Wi-Fi event callback function */ + +typedef void (*wifi_evt_cb_t)(void *p); + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Private functions order is defined as: + * - A first block containing the functions in the same order as of the + * ESP-IDF' corresponding `esp_adapter.c` to ease comparison; + * - A second block of auxiliary functions block ordered by ascending; + */ + +/* First block of functions */ + +static void *wifi_zalloc_wrapper(size_t size); +static void *wifi_create_queue(int queue_len, int item_size); +static void wifi_delete_queue(wifi_static_queue_t *queue); +static void *wifi_create_queue_wrapper(int queue_len, int item_size); +static void wifi_delete_queue_wrapper(void *queue); +static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, + uint32_t intr_num, int32_t intr_prio); +static void clear_intr_wrapper(uint32_t intr_source, uint32_t intr_num); +static void set_isr_wrapper(int32_t n, void *f, void *arg); +static void enable_intr_wrapper(uint32_t intr_mask); +static void disable_intr_wrapper(uint32_t intr_mask); +static bool is_from_isr_wrapper(void); +static void wifi_thread_semphr_free(void *data); +static void *wifi_thread_semphr_get_wrapper(void); +static void *recursive_mutex_create_wrapper(void); +static void *mutex_create_wrapper(void); +static void mutex_delete_wrapper(void *mutex); +static int32_t mutex_lock_wrapper(void *mutex); +static int32_t mutex_unlock_wrapper(void *mutex); +static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size); +static int32_t queue_send_wrapper(void *queue, + void *item, + uint32_t block_time_tick); +static int32_t queue_send_from_isr_wrapper(void *queue, + void *item, + void *hptw); +static int32_t queue_send_to_back_wrapper(void *queue, + void *item, + uint32_t block_time_tick); +static int32_t queue_send_to_front_wrapper(void *queue, + void *item, + uint32_t block_time_tick); +static int32_t queue_recv_wrapper(void *queue, + void *item, + uint32_t block_time_tick); +static uint32_t event_group_wait_bits_wrapper(void *event, + uint32_t bits_to_wait_for, + int clear_on_exit, + int wait_for_all_bits, + uint32_t block_time_tick); +static int32_t task_create_pinned_to_core_wrapper(void *task_func, + const char *name, + uint32_t stack_depth, + void *param, + uint32_t prio, + void *task_handle, + uint32_t core_id); +static int32_t task_create_wrapper(void *task_func, + const char *name, + uint32_t stack_depth, + void *param, + uint32_t prio, + void *task_handle); +static int32_t task_ms_to_tick_wrapper(uint32_t ms); +static int32_t task_get_max_priority_wrapper(void); +int32_t esp_event_post_wrapper(const char *event_base, + int32_t event_id, + void *event_data, + size_t event_data_size, + uint32_t ticks); +static void wifi_apb80m_request_wrapper(void); +static void wifi_apb80m_release_wrapper(void); +static void timer_arm_wrapper(void *timer, uint32_t tmout, bool repeat); +static void wifi_reset_mac_wrapper(void); +static void wifi_rtc_enable_iso_wrapper(void); +static void IRAM_ATTR wifi_rtc_disable_iso_wrapper(void); +static void wifi_clock_enable_wrapper(void); +static void wifi_clock_disable_wrapper(void); +static int get_time_wrapper(void *t); +static void *realloc_internal_wrapper(void *ptr, size_t size); +static void *calloc_internal_wrapper(size_t n, size_t size); +static void *zalloc_internal_wrapper(size_t size); +static int nvs_open_wrapper(const char *name, unsigned int open_mode, + uint32_t *out_handle); +static void esp_log_writev_wrapper(unsigned int level, + const char *tag, + const char *format, + va_list args); +static void esp_log_write_wrapper(unsigned int level, + const char *tag, + const char *format, ...); +static int esp_read_mac_wrapper(uint8_t *mac, unsigned int type); +static int coex_init_wrapper(void); +static void coex_deinit_wrapper(void); +static int coex_enable_wrapper(void); +static void coex_disable_wrapper(void); +static uint32_t coex_status_get_wrapper(void); +static int coex_wifi_request_wrapper(uint32_t event, + uint32_t latency, + uint32_t duration); +static int coex_wifi_release_wrapper(uint32_t event); +static int coex_wifi_channel_set_wrapper(uint8_t primary, + uint8_t secondary); +static int coex_event_duration_get_wrapper(uint32_t event, + uint32_t *duration); +static int coex_pti_get_wrapper(uint32_t event, uint8_t *pti); +static void coex_schm_status_bit_clear_wrapper(uint32_t type, + uint32_t status); +static void coex_schm_status_bit_set_wrapper(uint32_t type, + uint32_t status); +static int coex_schm_interval_set_wrapper(uint32_t interval); +static uint32_t coex_schm_interval_get_wrapper(void); +static uint8_t coex_schm_curr_period_get_wrapper(void); +static void *coex_schm_curr_phase_get_wrapper(void); +static int coex_register_start_cb_wrapper(int (* cb)(void)); +static int coex_schm_process_restart_wrapper(void); +static int coex_schm_register_cb_wrapper(int type, int(*cb)(int)); +static void esp_empty_wrapper(void); + +/* Second block of functions + * These functions are auxiliary functions that are used by the first block + * of functions or software adapters for the Wi-Fi driver + */ + +static int esp_event_id_map(int event_id); +static void esp_evt_work_cb(void *arg); +static int esp_freq_to_channel(uint16_t freq); +static uint32_t esp_get_free_heap_size(void); +static void *event_group_create_wrapper(void); +static void event_group_delete_wrapper(void *event); +static uint32_t event_group_set_bits_wrapper(void *event, uint32_t bits); +static uint32_t event_group_clear_bits_wrapper(void *event, uint32_t bits); +static int esp_int_adpt_cb(int irq, void *context, void *arg); +static int esp_nvs_commit(uint32_t handle); +static int esp_nvs_erase_key(uint32_t handle, const char *key); +static int esp_nvs_get_blob(uint32_t handle, + const char *key, + void *out_value, + size_t *length); +static int esp_nvs_set_blob(uint32_t handle, + const char *key, + const void *value, + size_t length); +static int esp_nvs_get_i8(uint32_t handle, + const char *key, + int8_t *out_value); +static int esp_nvs_set_i8(uint32_t handle, const char *key, int8_t value); +static int esp_nvs_get_u8(uint32_t handle, + const char *key, + uint8_t *out_value); +static int esp_nvs_set_u8(uint32_t handle, const char *key, uint8_t value); +static int esp_nvs_get_u16(uint32_t handle, + const char *key, + uint16_t *out_value); +static int esp_nvs_set_u16(uint32_t handle, const char *key, uint16_t value); +static void esp_nvs_close(uint32_t handle); +static void esp_update_time(struct timespec *timespec, uint32_t ticks); +static int esp_wifi_auth_trans(uint32_t wifi_auth); +static int esp_wifi_cipher_trans(uint32_t wifi_cipher); +static int esp_wifi_lock(bool lock); +static uint32_t queue_msg_waiting_wrapper(void *queue); +static void task_delay_wrapper(uint32_t tick); +static void task_delete_wrapper(void *task_handle); +static void *task_get_current_task_wrapper(void); +static void vqueue_delete_adapter(void *queue); +static void vsemaphore_delete_adapter(void *semphr); +static void *xqueue_create_adapter(uint32_t queue_len, uint32_t item_size); +static int32_t xqueue_send_adapter(void *queue, + void *item, + uint32_t ticks, + int prio); +void *xsemaphore_create_counting_adapter(uint32_t max, uint32_t init); + +#ifdef CONFIG_PM +extern void wifi_apb80m_request(void); +extern void wifi_apb80m_release(void); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Wi-Fi event private data */ + +static struct work_s g_wifi_evt_work; +static sq_queue_t g_wifi_evt_queue; +static struct wifi_notify g_wifi_notify[WIFI_ADPT_EVT_MAX]; +static mutex_t g_wifiexcl_lock = NXMUTEX_INITIALIZER; + +/* Wi-Fi adapter reference */ + +static int g_wifi_ref; + +#ifdef ESP_WLAN_HAS_STA + +/* If reconnect automatically */ + +static bool g_sta_reconnect; + +/* If Wi-Fi sta starts */ + +static bool g_sta_started; + +/* If Wi-Fi sta connected */ + +static bool g_sta_connected; + +/* Wi-Fi interface configuration */ + +static wifi_config_t g_sta_wifi_cfg; + +#endif /* ESP_WLAN_HAS_STA */ + +#ifdef ESP_WLAN_HAS_SOFTAP + +/* If Wi-Fi SoftAP starts */ + +static bool g_softap_started; + +/* Wi-Fi interface configuration */ + +static wifi_config_t g_softap_wifi_cfg; + +#endif /* ESP_WLAN_HAS_SOFTAP */ + +/* Device specific lock */ + +static spinlock_t g_lock; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Wi-Fi OS adapter data */ + +wifi_osi_funcs_t g_wifi_osi_funcs = +{ + ._version = ESP_WIFI_OS_ADAPTER_VERSION, + ._env_is_chip = esp_coex_common_env_is_chip_wrapper, + ._set_intr = set_intr_wrapper, + ._clear_intr = clear_intr_wrapper, + ._set_isr = set_isr_wrapper, + ._ints_on = enable_intr_wrapper, + ._ints_off = disable_intr_wrapper, + ._is_from_isr = is_from_isr_wrapper, + ._spin_lock_create = esp_coex_common_spin_lock_create_wrapper, + ._spin_lock_delete = free, + ._wifi_int_disable = esp_coex_common_int_disable_wrapper, + ._wifi_int_restore = esp_coex_common_int_restore_wrapper, + ._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper, + ._semphr_create = esp_coex_common_semphr_create_wrapper, + ._semphr_delete = esp_coex_common_semphr_delete_wrapper, + ._semphr_take = esp_coex_common_semphr_take_wrapper, + ._semphr_give = esp_coex_common_semphr_give_wrapper, + ._wifi_thread_semphr_get = wifi_thread_semphr_get_wrapper, + ._mutex_create = mutex_create_wrapper, + ._recursive_mutex_create = recursive_mutex_create_wrapper, + ._mutex_delete = mutex_delete_wrapper, + ._mutex_lock = mutex_lock_wrapper, + ._mutex_unlock = mutex_unlock_wrapper, + ._queue_create = queue_create_wrapper, + ._queue_delete = vqueue_delete_adapter, + ._queue_send = queue_send_wrapper, + ._queue_send_from_isr = queue_send_from_isr_wrapper, + ._queue_send_to_back = queue_send_to_back_wrapper, + ._queue_send_to_front = queue_send_to_front_wrapper, + ._queue_recv = queue_recv_wrapper, + ._queue_msg_waiting = queue_msg_waiting_wrapper, + ._event_group_create = event_group_create_wrapper, + ._event_group_delete = event_group_delete_wrapper, + ._event_group_set_bits = event_group_set_bits_wrapper, + ._event_group_clear_bits = event_group_clear_bits_wrapper, + ._event_group_wait_bits = event_group_wait_bits_wrapper, + ._task_create_pinned_to_core = task_create_pinned_to_core_wrapper, + ._task_create = task_create_wrapper, + ._task_delete = task_delete_wrapper, + ._task_delay = task_delay_wrapper, + ._task_ms_to_tick = task_ms_to_tick_wrapper, + ._task_get_current_task = task_get_current_task_wrapper, + ._task_get_max_priority = task_get_max_priority_wrapper, + ._malloc = malloc, + ._free = free, + ._event_post = esp_event_post_wrapper, + ._get_free_heap_size = esp_get_free_heap_size, + ._rand = esp_random, + ._dport_access_stall_other_cpu_start_wrap = + esp_empty_wrapper, + ._dport_access_stall_other_cpu_end_wrap = + esp_empty_wrapper, + ._wifi_apb80m_request = wifi_apb80m_request_wrapper, + ._wifi_apb80m_release = wifi_apb80m_release_wrapper, + ._phy_disable = esp_phy_disable, + ._phy_enable = esp_phy_enable, + ._phy_update_country_info = esp_phy_update_country_info, + ._read_mac = esp_read_mac_wrapper, + ._timer_arm = timer_arm_wrapper, + ._timer_disarm = esp_coex_common_timer_disarm_wrapper, + ._timer_done = esp_coex_common_timer_done_wrapper, + ._timer_setfn = esp_coex_common_timer_setfn_wrapper, + ._timer_arm_us = esp_coex_common_timer_arm_us_wrapper, + ._wifi_reset_mac = wifi_reset_mac_wrapper, + ._wifi_clock_enable = wifi_clock_enable_wrapper, + ._wifi_clock_disable = wifi_clock_disable_wrapper, + ._wifi_rtc_enable_iso = wifi_rtc_enable_iso_wrapper, + ._wifi_rtc_disable_iso = wifi_rtc_disable_iso_wrapper, + ._esp_timer_get_time = (int64_t(*)(void))esp_hr_timer_time_us, + ._nvs_set_i8 = esp_nvs_set_i8, + ._nvs_get_i8 = esp_nvs_get_i8, + ._nvs_set_u8 = esp_nvs_set_u8, + ._nvs_get_u8 = esp_nvs_get_u8, + ._nvs_set_u16 = esp_nvs_set_u16, + ._nvs_get_u16 = esp_nvs_get_u16, + ._nvs_open = nvs_open_wrapper, + ._nvs_close = esp_nvs_close, + ._nvs_commit = esp_nvs_commit, + ._nvs_set_blob = esp_nvs_set_blob, + ._nvs_get_blob = esp_nvs_get_blob, + ._nvs_erase_key = esp_nvs_erase_key, + ._get_random = os_get_random, + ._get_time = get_time_wrapper, + ._random = os_random, + ._slowclk_cal_get = esp_coex_common_clk_slowclk_cal_get_wrapper, + ._log_write = esp_log_write_wrapper, + ._log_writev = esp_log_writev_wrapper, + ._log_timestamp = esp_log_timestamp, + ._malloc_internal = esp_coex_common_malloc_internal_wrapper, + ._realloc_internal = realloc_internal_wrapper, + ._calloc_internal = calloc_internal_wrapper, + ._zalloc_internal = zalloc_internal_wrapper, + ._wifi_malloc = wifi_malloc, + ._wifi_realloc = wifi_realloc, + ._wifi_calloc = wifi_calloc, + ._wifi_zalloc = wifi_zalloc_wrapper, + ._wifi_create_queue = wifi_create_queue_wrapper, + ._wifi_delete_queue = wifi_delete_queue_wrapper, + ._coex_init = coex_init_wrapper, + ._coex_deinit = coex_deinit_wrapper, + ._coex_enable = coex_enable_wrapper, + ._coex_disable = coex_disable_wrapper, + ._coex_status_get = coex_status_get_wrapper, + ._coex_wifi_request = coex_wifi_request_wrapper, + ._coex_wifi_release = coex_wifi_release_wrapper, + ._coex_wifi_channel_set = coex_wifi_channel_set_wrapper, + ._coex_event_duration_get = coex_event_duration_get_wrapper, + ._coex_pti_get = coex_pti_get_wrapper, + ._coex_schm_status_bit_clear = coex_schm_status_bit_clear_wrapper, + ._coex_schm_status_bit_set = coex_schm_status_bit_set_wrapper, + ._coex_schm_interval_set = coex_schm_interval_set_wrapper, + ._coex_schm_interval_get = coex_schm_interval_get_wrapper, + ._coex_schm_curr_period_get = coex_schm_curr_period_get_wrapper, + ._coex_schm_curr_phase_get = coex_schm_curr_phase_get_wrapper, + ._coex_register_start_cb = coex_register_start_cb_wrapper, + ._coex_schm_process_restart = coex_schm_process_restart_wrapper, + ._coex_schm_register_cb = coex_schm_register_cb_wrapper, + ._magic = ESP_WIFI_OS_ADAPTER_MAGIC, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Private functions order is defined as: + * - A first block containing the functions in the same order as of the + * ESP-IDF' corresponding `esp_adapter.c` to ease comparison; + * - A second block of auxiliary functions block ordered by ascending; + */ + +/* First block of functions */ + +/**************************************************************************** + * Name: wifi_zalloc_wrapper + * + * Description: + * Applications allocate a block of memory and clear it with 0 + * + * Input Parameters: + * size - memory size + * + * Returned Value: + * New memory pointer + * + ****************************************************************************/ + +static IRAM_ATTR void *wifi_zalloc_wrapper(size_t size) +{ + return zalloc(size); +} + +/**************************************************************************** + * Name: wifi_create_queue + * + * Description: + * Create Wi-Fi static message queue + * + * Input Parameters: + * queue_len - queue message number + * item_size - message size + * + * Returned Value: + * Wi-Fi static message queue data pointer + * + ****************************************************************************/ + +static void *wifi_create_queue(int queue_len, int item_size) +{ + wifi_static_queue_t *wifi_queue; + + wifi_queue = kmm_malloc(sizeof(wifi_static_queue_t)); + if (!wifi_queue) + { + wlerr("Failed to kmm_malloc\n"); + return NULL; + } + + wifi_queue->handle = xqueue_create_adapter(queue_len, item_size); + if (!wifi_queue->handle) + { + wlerr("Failed to create queue\n"); + kmm_free(wifi_queue); + return NULL; + } + + return wifi_queue; +} + +/**************************************************************************** + * Name: wifi_delete_queue + * + * Description: + * Delete message queue + * + * Input Parameters: + * queue - Message queue data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wifi_delete_queue(wifi_static_queue_t *queue) +{ + if (queue) + { + vqueue_delete_adapter(queue->handle); + kmm_free(queue); + } +} + +/**************************************************************************** + * Name: wifi_create_queue_wrapper + * + * Description: + * This function creates a new queue for Wi-Fi operations. It is a wrapper + * around the wifi_create_queue function, providing a consistent interface + * for the Wi-Fi module. + * + * Input Parameters: + * queue_len - The maximum number of items that the queue can hold. + * item_size - The size of each item in the queue. + * + * Returned Value: + * A pointer to the newly created queue, or NULL if the operation failed. + * + ****************************************************************************/ + +static void *wifi_create_queue_wrapper(int queue_len, int item_size) +{ + return wifi_create_queue(queue_len, item_size); +} + +/**************************************************************************** + * Name: wifi_delete_queue_wrapper + * + * Description: + * Delete Wi-Fi static message queue + * + * Input Parameters: + * queue - Wi-Fi static message queue data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wifi_delete_queue_wrapper(void *queue) +{ + wifi_delete_queue(queue); +} + +/**************************************************************************** + * Name: set_intr_wrapper + * + * Description: + * Do nothing + * + * Input Parameters: + * cpu_no - The CPU which the interrupt number belongs. + * intr_source - The interrupt hardware source number. + * intr_num - The interrupt number CPU. + * intr_prio - The interrupt priority. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, + uint32_t intr_num, int32_t intr_prio) +{ + wlinfo("cpu_no=%" PRId32 ", intr_source=%" PRIu32 + ", intr_num=%" PRIu32 ", intr_prio=%" PRId32 "\n", + cpu_no, intr_source, intr_num, intr_prio); + + esp_route_intr(intr_source, intr_num, intr_prio, ESP_IRQ_TRIGGER_LEVEL); + esp_set_irq(ESP_SOURCE2IRQ(intr_source), intr_num); +} + +/**************************************************************************** + * Name: clear_intr_wrapper + * + * Description: + * This function is intended to clear a specific interrupt. However, this + * functionality is not supported in the current implementation. + * + * Input Parameters: + * intr_source - The source of the interrupt. + * intr_num - The number of the interrupt. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR clear_intr_wrapper(uint32_t intr_source, + uint32_t intr_num) +{ +} + +/**************************************************************************** + * Name: set_isr_wrapper + * + * Description: + * Register interrupt function + * + * Input Parameters: + * n - CPU interrupt number + * f - Interrupt function + * arg - Function private data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void set_isr_wrapper(int32_t n, void *f, void *arg) +{ + int ret; + uint32_t tmp; + struct irq_adpt *adapter; + int irq = esp_get_irq(n); + + wlinfo("n=%ld f=%p arg=%p irq=%d\n", n, f, arg, irq); + + if (g_irqvector[irq].handler && + g_irqvector[irq].handler != irq_unexpected_isr) + { + wlinfo("irq=%d has been set handler=%p\n", irq, + g_irqvector[irq].handler); + return; + } + + tmp = sizeof(struct irq_adpt); + adapter = kmm_malloc(tmp); + if (!adapter) + { + wlerr("Failed to alloc %ld memory\n", tmp); + PANIC(); + return; + } + + adapter->func = f; + adapter->arg = arg; + + ret = irq_attach(irq, esp_int_adpt_cb, adapter); + if (ret) + { + wlerr("Failed to attach IRQ %d\n", irq); + PANIC(); + return; + } +} + +/**************************************************************************** + * Name: enable_intr_wrapper + * + * Description: + * Enable a specific Wi-Fi interrupt. + * + * Input Parameters: + * intr_mask - A mask where the bit corresponding to the interrupt to be + * enabled is set. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void enable_intr_wrapper(uint32_t intr_mask) +{ + int cpuint = __builtin_ffs(intr_mask) - 1; + int irq = esp_get_irq(cpuint); + + wlinfo("intr_mask=%08lx cpuint=%d irq=%d\n", intr_mask, cpuint, irq); + + up_enable_irq(irq); +} + +/**************************************************************************** + * Name: disable_intr_wrapper + * + * Description: + * Disable a specific Wi-Fi interrupt. + * + * Input Parameters: + * intr_mask - A mask where the bit corresponding to the interrupt to be + * disabled is set. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void disable_intr_wrapper(uint32_t intr_mask) +{ + int cpuint = __builtin_ffs(intr_mask) - 1; + int irq = esp_get_irq(cpuint); + + wlinfo("intr_mask=%08lx cpuint=%d irq=%d\n", intr_mask, cpuint, irq); + + up_disable_irq(irq); +} + +/**************************************************************************** + * Name: is_from_isr_wrapper + * + * Description: + * Check current is in interrupt + * + * Input Parameters: + * None + * + * Returned Value: + * true if in interrupt or false if not + * + ****************************************************************************/ + +static bool IRAM_ATTR is_from_isr_wrapper(void) +{ + return up_interrupt_context(); +} + +/**************************************************************************** + * Name: wifi_thread_semphr_free + * + * Description: + * Delete thread self's semaphore + * + * Input Parameters: + * data - Semaphore data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wifi_thread_semphr_free(void *data) +{ + void *sem = (void *)data; + + if (sem) + { + vsemaphore_delete_adapter(sem); + } +} + +/**************************************************************************** + * Name: wifi_thread_semphr_get_wrapper + * + * Description: + * Get thread self's semaphore + * + * Input Parameters: + * None + * + * Returned Value: + * Semaphore data pointer + * + ****************************************************************************/ + +static void *wifi_thread_semphr_get_wrapper(void) +{ + static int wifi_task_key = -1; + int ret; + void *sem; + + if (wifi_task_key < 0) + { + ret = task_tls_alloc(wifi_thread_semphr_free); + if (ret < 0) + { + wlerr("Failed to create task local key\n"); + return NULL; + } + + wifi_task_key = ret; + } + + sem = (void *)task_tls_get_value(wifi_task_key); + if (sem == NULL) + { + sem = xsemaphore_create_counting_adapter(1, 0); + if (!sem) + { + wlerr("Failed to create semaphore\n"); + return NULL; + } + + ret = task_tls_set_value(wifi_task_key, (uintptr_t)sem); + if (ret != OK) + { + wlerr("Failed to save semaphore on task local storage: %d\n", ret); + vsemaphore_delete_adapter(sem); + return NULL; + } + } + + return sem; +} + +/**************************************************************************** + * Name: recursive_mutex_create_wrapper + * + * Description: + * Create recursive mutex + * + * Input Parameters: + * None + * + * Returned Value: + * Recursive mutex data pointer + * + ****************************************************************************/ + +static void *recursive_mutex_create_wrapper(void) +{ + int ret; + pthread_mutex_t *mutex; + pthread_mutexattr_t attr; + int tmp; + + ret = pthread_mutexattr_init(&attr); + if (ret) + { + wlerr("Failed to initialize attr error=%d\n", ret); + return NULL; + } + + ret = pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE); + if (ret) + { + wlerr("Failed to set attr type error=%d\n", ret); + return NULL; + } + + tmp = sizeof(pthread_mutex_t); + mutex = kmm_malloc(tmp); + if (!mutex) + { + wlerr("Failed to alloc %d memory\n", tmp); + return NULL; + } + + ret = pthread_mutex_init(mutex, &attr); + if (ret) + { + wlerr("Failed to initialize mutex error=%d\n", ret); + kmm_free(mutex); + return NULL; + } + + return mutex; +} + +/**************************************************************************** + * Name: mutex_create_wrapper + * + * Description: + * Create mutex + * + * Input Parameters: + * None + * + * Returned Value: + * Mutex data pointer + * + ****************************************************************************/ + +static void *mutex_create_wrapper(void) +{ + int ret; + pthread_mutex_t *mutex; + int tmp; + + tmp = sizeof(pthread_mutex_t); + mutex = kmm_malloc(tmp); + if (!mutex) + { + wlerr("Failed to alloc %d memory\n", tmp); + return NULL; + } + + ret = pthread_mutex_init(mutex, NULL); + if (ret) + { + wlerr("Failed to initialize mutex error=%d\n", ret); + kmm_free(mutex); + return NULL; + } + + return mutex; +} + +/**************************************************************************** + * Name: mutex_delete_wrapper + * + * Description: + * Delete mutex + * + * Input Parameters: + * mutex - mutex data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void mutex_delete_wrapper(void *mutex) +{ + pthread_mutex_t *mutex_data = (pthread_mutex_t *)mutex; + + pthread_mutex_destroy(mutex_data); + kmm_free(mutex_data); +} + +/**************************************************************************** + * Name: mutex_lock_wrapper + * + * Description: + * Lock mutex + * + * Input Parameters: + * mutex - mutex data pointer + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t IRAM_ATTR mutex_lock_wrapper(void *mutex) +{ + int ret; + pthread_mutex_t *mutex_data = (pthread_mutex_t *)mutex; + + ret = pthread_mutex_lock(mutex_data); + if (ret) + { + wlerr("Failed to lock mutex error=%d\n", ret); + } + + return nuttx_err_to_freertos(ret); +} + +/**************************************************************************** + * Name: mutex_unlock_wrapper + * + * Description: + * Unlock mutex + * + * Input Parameters: + * mutex - mutex data pointer + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t IRAM_ATTR mutex_unlock_wrapper(void *mutex) +{ + int ret; + pthread_mutex_t *mutex_data = (pthread_mutex_t *)mutex; + + ret = pthread_mutex_unlock(mutex_data); + if (ret) + { + wlerr("Failed to unlock mutex error=%d\n", ret); + } + + return nuttx_err_to_freertos(ret); +} + +/**************************************************************************** + * Name: queue_create_wrapper + * + * Description: + * This function creates a new queue adapter with the specified length and + * item size. It is a wrapper around the xqueue_create_adapter function. + * + * Input Parameters: + * queue_len - The maximum number of items that the queue can hold. + * item_size - The size of each item in the queue. + * + * Returned Value: + * A pointer to the newly created queue adapter, or NULL if the operation + * failed. + * + ****************************************************************************/ + +static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size) +{ + return xqueue_create_adapter(queue_len, item_size); +} + +/**************************************************************************** + * Name: queue_send_wrapper + * + * Description: + * Send message of low priority to queue within a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * ticks - Wait ticks + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t queue_send_wrapper(void *queue, void *item, uint32_t ticks) +{ + return xqueue_send_adapter(queue, item, ticks, 0); +} + +/**************************************************************************** + * Name: queue_send_from_isr_wrapper + * + * Description: + * Send message of low priority to queue in ISR within + * a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * hptw - Unused. + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t IRAM_ATTR queue_send_from_isr_wrapper(void *queue, + void *item, + void *hptw) +{ + *(int *)hptw = 0; + + return xqueue_send_adapter(queue, item, 0, 0); +} + +/**************************************************************************** + * Name: queue_send_to_back_wrapper + * + * Description: + * Send message of low priority to queue within a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * ticks - Wait ticks + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t queue_send_to_back_wrapper(void *queue, + void *item, + uint32_t ticks) +{ + return xqueue_send_adapter(queue, item, ticks, 0); +} + +/**************************************************************************** + * Name: queue_send_to_front_wrapper + * + * Description: + * Send message of high priority to queue within a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * ticks - Wait ticks + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t queue_send_to_front_wrapper(void *queue, + void *item, + uint32_t ticks) +{ + return xqueue_send_adapter(queue, item, ticks, 1); +} + +/**************************************************************************** + * Name: queue_recv_wrapper + * + * Description: + * Receive message from queue within a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * ticks - Wait ticks + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t queue_recv_wrapper(void *queue, void *item, uint32_t ticks) +{ + ssize_t ret; + struct timespec timeout; + unsigned int prio; + struct mq_adpt *mq_adpt = (struct mq_adpt *)queue; + + if (ticks == OSI_FUNCS_TIME_BLOCKING) + { + ret = file_mq_receive(&mq_adpt->mq, (char *)item, + mq_adpt->msgsize, &prio); + if (ret < 0) + { + wlerr("Failed to receive from mqueue error=%d\n", ret); + } + } + else + { + ret = clock_gettime(CLOCK_REALTIME, &timeout); + if (ret < 0) + { + wlerr("Failed to get time\n"); + return false; + } + + if (ticks) + { + esp_update_time(&timeout, ticks); + } + + ret = file_mq_timedreceive(&mq_adpt->mq, (char *)item, + mq_adpt->msgsize, &prio, &timeout); + if (ret < 0) + { + wlerr("Failed to timedreceive from mqueue error=%d\n", + ret); + } + } + + return ret > 0 ? true : false; +} + +/**************************************************************************** + * Name: event_group_wait_bits_wrapper + * + * Description: + * Don't support + * + ****************************************************************************/ + +static uint32_t event_group_wait_bits_wrapper(void *event, + uint32_t bits_to_wait_for, + int clear_on_exit, + int wait_for_all_bits, + uint32_t block_time_tick) +{ + DEBUGPANIC(); + + return false; +} + +/**************************************************************************** + * Name: task_create_pinned_to_core_wrapper + * + * Description: + * Create task and bind it to target CPU, the task will run when it + * is created + * + * Input Parameters: + * entry - Task entry + * name - Task name + * stack_depth - Task stack size + * param - Task private data + * prio - Task priority + * task_handle - Task handle pointer which is used to pause, resume + * and delete the task + * core_id - CPU which the task runs in + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t task_create_pinned_to_core_wrapper(void *entry, + const char *name, + uint32_t stack_depth, + void *param, + uint32_t prio, + void *task_handle, + uint32_t core_id) +{ + int pid; +#ifdef CONFIG_SMP + int ret; + cpu_set_t cpuset; +#endif + uint32_t target_prio = prio; + + if (target_prio < ESP_MAX_PRIORITIES) + { + target_prio += task_get_max_priority_wrapper() - ESP_MAX_PRIORITIES; + } + + pid = kthread_create(name, target_prio, stack_depth, entry, + (char * const *)param); + if (pid > 0) + { + if (task_handle != NULL) + { + *((int *)task_handle) = pid; + } + +#ifdef CONFIG_SMP + if (core_id < CONFIG_SMP_NCPUS) + { + CPU_ZERO(&cpuset); + CPU_SET(core_id, &cpuset); + ret = nxsched_set_affinity(pid, sizeof(cpuset), &cpuset); + if (ret) + { + wlerr("Failed to set affinity error=%d\n", ret); + return false; + } + } +#endif + } + else + { + wlerr("Failed to create task\n"); + } + + return pid > 0; +} + +/**************************************************************************** + * Name: task_create_wrapper + * + * Description: + * Create task and the task will run when it is created + * + * Input Parameters: + * entry - Task entry + * name - Task name + * stack_depth - Task stack size + * param - Task private data + * prio - Task priority + * task_handle - Task handle pointer which is used to pause, resume + * and delete the task + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t task_create_wrapper(void *entry, + const char *name, + uint32_t stack_depth, + void *param, + uint32_t prio, + void *task_handle) +{ + return task_create_pinned_to_core_wrapper(entry, + name, + stack_depth, + param, + prio, + task_handle, + UINT32_MAX); +} + +/**************************************************************************** + * Name: task_ms_to_tick_wrapper + * + * Description: + * This function converts a duration from milliseconds to system ticks. + * It is a wrapper around the NuttX MSEC2TICK macro. + * + * Input Parameters: + * ms - The duration in milliseconds. + * + * Returned Value: + * The duration in system ticks. + * + ****************************************************************************/ + +static int32_t task_ms_to_tick_wrapper(uint32_t ms) +{ + return MSEC2TICK(ms); +} + +/**************************************************************************** + * Name: task_get_max_priority_wrapper + * + * Description: + * Get OS task maximum priority + * + * Input Parameters: + * None + * + * Returned Value: + * Task maximum priority + * + ****************************************************************************/ + +static int32_t task_get_max_priority_wrapper(void) +{ + return SCHED_PRIORITY_MAX; +} + +/**************************************************************************** + * Name: esp_event_post_wrapper + * + * Description: + * Active work queue and let the work to process the cached event + * + * Input Parameters: + * event_base - Event set name + * event_id - Event ID + * event_data - Event private data + * event_data_size - Event data size + * ticks - Waiting system ticks + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +int32_t esp_event_post_wrapper(const char *event_base, + int32_t event_id, + void *event_data, + size_t event_data_size, + uint32_t ticks) +{ + size_t size; + int32_t id; + irqstate_t flags; + struct evt_adpt *evt_adpt; + + wlinfo("Event: base=%s id=%ld data=%p data_size=%d ticks=%lu\n", + event_base, event_id, event_data, event_data_size, ticks); + + id = esp_event_id_map(event_id); + if (id < 0) + { + wlinfo("No process event %ld\n", event_id); + return -1; + } + + size = event_data_size + sizeof(struct evt_adpt); + evt_adpt = kmm_malloc(size); + if (!evt_adpt) + { + wlerr("Failed to alloc %d memory\n", size); + return -1; + } + + evt_adpt->id = id; + memcpy(evt_adpt->buf, event_data, event_data_size); + + flags = spin_lock_irqsave(&g_lock); + sq_addlast(&evt_adpt->entry, &g_wifi_evt_queue); + spin_unlock_irqrestore(&g_lock, flags); + + work_queue(LPWORK, &g_wifi_evt_work, esp_evt_work_cb, NULL, 0); + + return 0; +} + +/**************************************************************************** + * Name: wifi_apb80m_request_wrapper + * + * Description: + * This function acquires the Wi-Fi lock in auto-sleep mode. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR wifi_apb80m_request_wrapper(void) +{ +#ifdef CONFIG_PM + wifi_apb80m_request(); +#endif +} + +/**************************************************************************** + * Name: wifi_apb80m_release_wrapper + * + * Description: + * This function releases the Wi-Fi lock in auto-sleep mode. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR wifi_apb80m_release_wrapper(void) +{ +#ifdef CONFIG_PM + wifi_apb80m_release(); +#endif +} + +/**************************************************************************** + * Name: timer_arm_wrapper + * + * Description: + * Set timer timeout period and repeat flag + * + * Input Parameters: + * ptimer - timer data pointer + * ms - millim seconds + * repeat - true: run cycle, false: run once + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR timer_arm_wrapper(void *ptimer, + uint32_t tmout, + bool repeat) +{ + ets_timer_arm(ptimer, tmout, repeat); +} + +/**************************************************************************** + * Name: wifi_reset_mac_wrapper + * + * Description: + * Reset Wi-Fi hardware MAC + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wifi_reset_mac_wrapper(void) +{ + periph_module_reset(PERIPH_WIFI_MODULE); +} + +/**************************************************************************** + * Name: wifi_rtc_enable_iso_wrapper + * + * Description: + * This function is a wrapper for enabling the isolation of the Wi-Fi + * Real-Time Clock (RTC). If the MAC/BB power down configuration option + * is set, it powers down the MAC/BB. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR wifi_rtc_enable_iso_wrapper(void) +{ +#if CONFIG_MAC_BB_PD + esp_mac_bb_power_down(); +#endif +} + +/**************************************************************************** + * Name: wifi_rtc_disable_iso_wrapper + * + * Description: + * This function is a wrapper for disabling the isolation of the Wi-Fi + * Real-Time Clock (RTC). If the MAC/BB power down configuration option + * is set, it powers up the MAC/BB. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR wifi_rtc_disable_iso_wrapper(void) +{ +#if CONFIG_MAC_BB_PD + esp_mac_bb_power_up(); +#endif +} + +/**************************************************************************** + * Name: wifi_clock_enable_wrapper + * + * Description: + * Enable Wi-Fi clock + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wifi_clock_enable_wrapper(void) +{ + wifi_module_enable(); +} + +/**************************************************************************** + * Name: wifi_clock_disable_wrapper + * + * Description: + * Disable Wi-Fi clock + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wifi_clock_disable_wrapper(void) +{ + wifi_module_disable(); +} + +/**************************************************************************** + * Name: get_time_wrapper + * + * Description: + * Get std C time + * + * Input Parameters: + * t - buffer to store time of type timeval + * + * Returned Value: + * Zero (OK) on success; -1 is returned on failure with the errno variable + * set appropriately. + * + ****************************************************************************/ + +static int get_time_wrapper(void *t) +{ + return os_get_time(t); +} + +/**************************************************************************** + * Name: realloc_internal_wrapper + * + * Description: + * Drivers allocate a block of memory by old memory block + * + * Input Parameters: + * ptr - old memory pointer + * size - memory size + * + * Returned Value: + * New memory pointer + * + ****************************************************************************/ + +static IRAM_ATTR void *realloc_internal_wrapper(void *ptr, size_t size) +{ + return kmm_realloc(ptr, size); +} + +/**************************************************************************** + * Name: calloc_internal_wrapper + * + * Description: + * Drivers allocate some continuous blocks of memory + * + * Input Parameters: + * n - memory block number + * size - memory block size + * + * Returned Value: + * New memory pointer + * + ****************************************************************************/ + +static IRAM_ATTR void *calloc_internal_wrapper(size_t n, size_t size) +{ + return kmm_calloc(n, size); +} + +/**************************************************************************** + * Name: zalloc_internal_wrapper + * + * Description: + * Drivers allocate a block of memory and clear it with 0 + * + * Input Parameters: + * size - memory size + * + * Returned Value: + * New memory pointer + * + ****************************************************************************/ + +static IRAM_ATTR void *zalloc_internal_wrapper(size_t size) +{ + return kmm_zalloc(size); +} + +/**************************************************************************** + * Name: nvs_open_wrapper + * + * Description: + * Create a file system storage data object + * + * Input Parameters: + * name - Storage index + * open_mode - Storage mode + * out_handle - Storage handle + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int nvs_open_wrapper(const char *name, + unsigned int open_mode, + uint32_t *out_handle) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_log_writev_wrapper + * + * Description: + * Output log with by format string and its arguments + * + * Input Parameters: + * level - log level, no mean here + * tag - log TAG, no mean here + * format - format string + * args - arguments list + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_log_writev_wrapper(unsigned int level, + const char *tag, + const char *format, + va_list args) +{ + esp_log_level_t max_level; + +#if defined (CONFIG_DEBUG_WIRELESS_INFO) + max_level = ESP_LOG_VERBOSE; +#elif defined (CONFIG_DEBUG_WIRELESS_WARN) + max_level = ESP_LOG_WARN; +#elif defined (CONFIG_DEBUG_WIRELESS_ERROR) + max_level = ESP_LOG_ERROR; +#else + max_level = ESP_LOG_NONE; +#endif + + if (level <= max_level) + { + esp_log_writev(level, tag, format, args); + } +} + +/**************************************************************************** + * Name: esp_log_write_wrapper + * + * Description: + * Output log with by format string and its arguments + * + * Input Parameters: + * level - log level, no mean here + * tag - log TAG, no mean here + * format - format string + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_log_write_wrapper(unsigned int level, + const char *tag, + const char *format, ...) +{ + esp_log_level_t max_level; + +#if defined (CONFIG_DEBUG_WIRELESS_INFO) + max_level = ESP_LOG_VERBOSE; +#elif defined (CONFIG_DEBUG_WIRELESS_WARN) + max_level = ESP_LOG_WARN; +#elif defined (CONFIG_DEBUG_WIRELESS_ERROR) + max_level = ESP_LOG_ERROR; +#else + max_level = ESP_LOG_NONE; +#endif + + if (level <= max_level) + { + va_list list; + va_start(list, format); + esp_log_writev(level, tag, format, list); + va_end(list); + } +} + +/**************************************************************************** + * Name: esp_read_mac_wrapper + * + * Description: + * Read MAC address from efuse + * + * Input Parameters: + * mac - MAC address buffer pointer + * type - MAC address type + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_read_mac_wrapper(uint8_t *mac, unsigned int type) +{ + return esp_read_mac(mac, type); +} + +/**************************************************************************** + * Name: coex_init_wrapper + * + * Description: + * Init software coexist + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int coex_init_wrapper(void) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_init(); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_deinit_wrapper + * + * Description: + * De-init software coexist + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void coex_deinit_wrapper(void) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + coex_deinit(); +#endif +} + +/**************************************************************************** + * Name: coex_enable_wrapper + * + * Description: + * Enable software coexist + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int coex_enable_wrapper(void) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_enable(); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_disable_wrapper + * + * Description: + * Disable software coexist + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void coex_disable_wrapper(void) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + coex_disable(); +#endif +} + +/**************************************************************************** + * Name: coex_status_get_wrapper + * + * Description: + * Get software coexist status. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static IRAM_ATTR uint32_t coex_status_get_wrapper(void) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_status_get(); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_wifi_request_wrapper + * + * Description: + * Request Wi-Fi coexistence. + * + * Input Parameters: + * event - WiFi event + * latency - WiFi will request coexistence after latency + * duration - duration for WiFi to request coexistence + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int coex_wifi_request_wrapper(uint32_t event, + uint32_t latency, + uint32_t duration) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_wifi_request(event, latency, duration); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_wifi_release_wrapper + * + * Description: + * Release Wi-Fi coexistence. + * + * Input Parameters: + * event - WiFi event + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static IRAM_ATTR int coex_wifi_release_wrapper(uint32_t event) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_wifi_release(event); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_wifi_channel_set_wrapper + * + * Description: + * Set Wi-Fi channel to coexistence module. + * + * Input Parameters: + * primary - WiFi primary channel + * secondary - WiFi secondary channel + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int coex_wifi_channel_set_wrapper(uint8_t primary, uint8_t secondary) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_wifi_channel_set(primary, secondary); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_event_duration_get_wrapper + * + * Description: + * Get coexistence event duration. + * + * Input Parameters: + * event - Coexistence event + * duration - Coexistence event duration + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static IRAM_ATTR int coex_event_duration_get_wrapper(uint32_t event, + uint32_t *duration) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_event_duration_get(event, duration); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_pti_get_wrapper + * + * Description: + * Get coexistence event priority. + * + * Input Parameters: + * event - Coexistence event + * pti - Coexistence event priority + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int coex_pti_get_wrapper(uint32_t event, uint8_t *pti) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_pti_get(event, pti); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_schm_status_bit_clear_wrapper + * + * Description: + * Clear coexistence status. + * + * Input Parameters: + * type - Coexistence status type + * status - Coexistence status + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void coex_schm_status_bit_clear_wrapper(uint32_t type, + uint32_t status) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + coex_schm_status_bit_clear(type, status); +#endif +} + +/**************************************************************************** + * Name: coex_schm_status_bit_set_wrapper + * + * Description: + * Set coexistence status. + * + * Input Parameters: + * type - Coexistence status type + * status - Coexistence status + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + coex_schm_status_bit_set(type, status); +#endif +} + +/**************************************************************************** + * Name: coex_schm_interval_set_wrapper + * + * Description: + * Set coexistence scheme interval. + * + * Input Parameters: + * interval - Coexistence scheme interval + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static IRAM_ATTR int coex_schm_interval_set_wrapper(uint32_t interval) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_schm_interval_set(interval); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_schm_interval_get_wrapper + * + * Description: + * Get coexistence scheme interval. + * + * Input Parameters: + * None + * + * Returned Value: + * Coexistence scheme interval + * + ****************************************************************************/ + +static uint32_t coex_schm_interval_get_wrapper(void) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_schm_interval_get(); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_schm_curr_period_get_wrapper + * + * Description: + * Get current coexistence scheme period. + * + * Input Parameters: + * None + * + * Returned Value: + * Coexistence scheme period + * + ****************************************************************************/ + +static uint8_t coex_schm_curr_period_get_wrapper(void) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_schm_curr_period_get(); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_schm_curr_phase_get_wrapper + * + * Description: + * Get current coexistence scheme phase. + * + * Input Parameters: + * None + * + * Returned Value: + * Coexistence scheme phase + * + ****************************************************************************/ + +static void *coex_schm_curr_phase_get_wrapper(void) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_schm_curr_phase_get(); +#else + return NULL; +#endif +} + +/**************************************************************************** + * Name: coex_register_start_cb_wrapper + * + * Description: + * Register Wi-Fi callback for coexistence starts. + * + * Input Parameters: + * cb - WiFi callback + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int coex_register_start_cb_wrapper(int (* cb)(void)) +{ +#if CONFIG_SW_COEXIST_ENABLE + return coex_register_start_cb(cb); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_schm_process_restart_wrapper + * + * Description: + * Restart current coexistence scheme. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int coex_schm_process_restart_wrapper(void) +{ +#if CONFIG_SW_COEXIST_ENABLE + return coex_schm_process_restart(); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_schm_register_cb_wrapper + * + * Description: + * Register callback for coexistence scheme. + * + * Input Parameters: + * type - callback type + * cb - callback + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int coex_schm_register_cb_wrapper(int type, int(*cb)(int)) +{ +#if CONFIG_SW_COEXIST_ENABLE + return coex_schm_register_callback(type, cb); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: esp_empty_wrapper + * + * Description: + * This function is an empty wrapper, designed to be used where a function + * pointer is required but no operation is needed. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp_empty_wrapper(void) +{ +} + +/* Second block of functions + * These functions are auxiliary functions that are used by the first block + * of functions or software adapters for the Wi-Fi driver + */ + +/**************************************************************************** + * Name: esp_event_id_map + * + * Description: + * Transform from esp-idf event ID to Wi-Fi adapter event ID + * + * Input Parameters: + * event_id - esp-idf event ID + * + * Returned Value: + * Wi-Fi adapter event ID + * + ****************************************************************************/ + +static int esp_event_id_map(int event_id) +{ + int id; + + switch (event_id) + { + case WIFI_EVENT_SCAN_DONE: + id = WIFI_ADPT_EVT_SCAN_DONE; + break; + +#ifdef ESP_WLAN_HAS_STA + case WIFI_EVENT_STA_START: + id = WIFI_ADPT_EVT_STA_START; + break; + + case WIFI_EVENT_STA_CONNECTED: + id = WIFI_ADPT_EVT_STA_CONNECT; + break; + + case WIFI_EVENT_STA_DISCONNECTED: + id = WIFI_ADPT_EVT_STA_DISCONNECT; + break; + + case WIFI_EVENT_STA_AUTHMODE_CHANGE: + id = WIFI_ADPT_EVT_STA_AUTHMODE_CHANGE; + break; + + case WIFI_EVENT_STA_STOP: + id = WIFI_ADPT_EVT_STA_STOP; + break; +#endif /* ESP_WLAN_HAS_STA */ + +#ifdef ESP_WLAN_HAS_SOFTAP + case WIFI_EVENT_AP_START: + id = WIFI_ADPT_EVT_AP_START; + break; + + case WIFI_EVENT_AP_STOP: + id = WIFI_ADPT_EVT_AP_STOP; + break; + + case WIFI_EVENT_AP_STACONNECTED: + id = WIFI_ADPT_EVT_AP_STACONNECTED; + break; + + case WIFI_EVENT_AP_STADISCONNECTED: + id = WIFI_ADPT_EVT_AP_STADISCONNECTED; + break; +#endif /* ESP_WLAN_HAS_SOFTAP */ + + default: + return -1; + } + + return id; +} + +/**************************************************************************** + * Name: esp_evt_work_cb + * + * Description: + * Process the cached event + * + * Input Parameters: + * arg - No mean + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_evt_work_cb(void *arg) +{ + int ret; + irqstate_t flags; + struct evt_adpt *evt_adpt; + struct wifi_notify *notify; + wifi_ps_type_t ps_type = DEFAULT_PS_MODE; + + while (1) + { + flags = spin_lock_irqsave(&g_lock); + evt_adpt = (struct evt_adpt *)sq_remfirst(&g_wifi_evt_queue); + spin_unlock_irqrestore(&g_lock, flags); + if (!evt_adpt) + { + break; + } + + esp_wifi_lock(true); + + switch (evt_adpt->id) + { + case WIFI_ADPT_EVT_SCAN_DONE: + esp_wifi_scan_event_parse(); + break; + +#ifdef ESP_WLAN_HAS_STA + case WIFI_ADPT_EVT_STA_START: + wlinfo("Wi-Fi sta start\n"); + + g_sta_connected = false; + + ret = esp_wifi_set_ps(ps_type); + if (ret) + { + wlerr("Failed to set power save type\n"); + break; + } + else + { + wlinfo("INFO: Set ps type=%d\n", ps_type); + } + + ret = esp_wifi_get_config(WIFI_IF_STA, &g_sta_wifi_cfg); + if (ret) + { + wlerr("Failed to get Wi-Fi config data ret=%d\n", ret); + } + break; + + case WIFI_ADPT_EVT_STA_CONNECT: + wlinfo("Wi-Fi sta connect\n"); + g_sta_connected = true; + ret = esp_wlan_sta_set_linkstatus(true); + if (ret < 0) + { + wlerr("ERROR: Failed to set Wi-Fi station link status\n"); + } + + break; + + case WIFI_ADPT_EVT_STA_DISCONNECT: + wlinfo("Wi-Fi sta disconnect\n"); + g_sta_connected = false; + ret = esp_wlan_sta_set_linkstatus(false); + if (ret < 0) + { + wlerr("ERROR: Failed to set Wi-Fi station link status\n"); + } + + if (g_sta_reconnect) + { + ret = esp_wifi_connect(); + if (ret) + { + wlerr("Failed to connect AP error=%d\n", ret); + } + } + break; + + case WIFI_ADPT_EVT_STA_STOP: + wlinfo("Wi-Fi sta stop\n"); + g_sta_connected = false; + break; +#endif /* ESP_WLAN_HAS_STA */ + +#ifdef ESP_WLAN_HAS_SOFTAP + case WIFI_ADPT_EVT_AP_START: + wlinfo("INFO: Wi-Fi softap start\n"); + + ret = esp_wifi_set_ps(ps_type); + if (ret) + { + wlerr("Failed to set power save type\n"); + break; + } + else + { + wlinfo("INFO: Set ps type=%d\n", ps_type); + } + + ret = esp_wifi_get_config(WIFI_IF_AP, &g_softap_wifi_cfg); + if (ret) + { + wlerr("Failed to get Wi-Fi config data ret=%d\n", ret); + } + break; + + case WIFI_ADPT_EVT_AP_STOP: + wlinfo("INFO: Wi-Fi softap stop\n"); + break; + + case WIFI_ADPT_EVT_AP_STACONNECTED: + wlinfo("INFO: Wi-Fi station join\n"); + break; + + case WIFI_ADPT_EVT_AP_STADISCONNECTED: + wlinfo("INFO: Wi-Fi station leave\n"); + break; +#endif /* ESP_WLAN_HAS_SOFTAP */ + default: + break; + } + + notify = &g_wifi_notify[evt_adpt->id]; + if (notify->assigned) + { + notify->event.sigev_value.sival_ptr = evt_adpt->buf; + + ret = nxsig_notification(notify->pid, ¬ify->event, + SI_QUEUE, ¬ify->work); + if (ret < 0) + { + wlwarn("nxsig_notification event ID=%ld failed: %d\n", + evt_adpt->id, ret); + } + } + + esp_wifi_lock(false); + + kmm_free(evt_adpt); + } +} + +/**************************************************************************** + * Name: esp_freq_to_channel + * + * Description: + * Converts Wi-Fi frequency to channel. + * + * Input Parameters: + * freq - Wi-Fi frequency + * + * Returned Value: + * Wi-Fi channel + * + ****************************************************************************/ + +static int esp_freq_to_channel(uint16_t freq) +{ + int channel = 0; + if (freq >= 2412 && freq <= 2484) + { + if (freq == 2484) + { + channel = 14; + } + else + { + channel = freq - 2407; + if (channel % 5) + { + return 0; + } + + channel /= 5; + } + + return channel; + } + + if (freq >= 5005 && freq < 5900) + { + if (freq % 5) + { + return 0; + } + + channel = (freq - 5000) / 5; + return channel; + } + + if (freq >= 4905 && freq < 5000) + { + if (freq % 5) + { + return 0; + } + + channel = (freq - 4000) / 5; + return channel; + } + + return 0; +} + +/**************************************************************************** + * Name: esp_get_free_heap_size + * + * Description: + * Get free heap size by byte + * + * Input Parameters: + * None + * + * Returned Value: + * Free heap size + * + ****************************************************************************/ + +static uint32_t esp_get_free_heap_size(void) +{ + struct mallinfo info; + + info = kmm_mallinfo(); + return info.fordblks; +} + +/**************************************************************************** + * Name: event_group_create_wrapper + * + * Description: + * Don't support + * + ****************************************************************************/ + +static void *event_group_create_wrapper(void) +{ + DEBUGPANIC(); + + return NULL; +} + +/**************************************************************************** + * Name: event_group_delete_wrapper + * + * Description: + * Don't support + * + ****************************************************************************/ + +static void event_group_delete_wrapper(void *event) +{ + DEBUGPANIC(); +} + +/**************************************************************************** + * Name: event_group_set_bits_wrapper + * + * Description: + * Don't support + * + ****************************************************************************/ + +static uint32_t event_group_set_bits_wrapper(void *event, uint32_t bits) +{ + DEBUGPANIC(); + + return false; +} + +/**************************************************************************** + * Name: event_group_clear_bits_wrapper + * + * Description: + * Don't support + * + ****************************************************************************/ + +static uint32_t event_group_clear_bits_wrapper(void *event, uint32_t bits) +{ + DEBUGPANIC(); + + return false; +} + +/**************************************************************************** + * Name: esp_int_adpt_cb + * + * Description: + * This is the callback function for the Wi-Fi interrupt adapter. It + * retrieves the adapter from the argument, then calls the function + * stored in the adapter with its argument. + * + * Input Parameters: + * irq - The IRQ number that caused this interrupt. + * context - The register context at the time of the interrupt. + * arg - A pointer to the interrupt adapter's private data. + * + * Returned Value: + * Always returns 0. + * + ****************************************************************************/ + +static int esp_int_adpt_cb(int irq, void *context, void *arg) +{ + struct irq_adpt *adapter = (struct irq_adpt *)arg; + + adapter->func(adapter->arg); + + return 0; +} + +/**************************************************************************** + * Name: esp_nvs_commit + * + * Description: + * This function has no practical effect + * + ****************************************************************************/ + +static int esp_nvs_commit(uint32_t handle) +{ + return 0; +} + +/**************************************************************************** + * Name: esp_nvs_erase_key + * + * Description: + * Read a block of data from file system + * + * Input Parameters: + * handle - NVS handle + * key - Data index + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_nvs_erase_key(uint32_t handle, const char *key) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_nvs_get_blob + * + * Description: + * Read a block of data from file system + * + * Input Parameters: + * handle - NVS handle + * key - Data index + * out_value - Read buffer pointer + * length - Buffer length + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_nvs_get_blob(uint32_t handle, + const char *key, + void *out_value, + size_t *length) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_nvs_set_blob + * + * Description: + * Save a block of data into file system + * + * Input Parameters: + * handle - NVS handle + * key - Data index + * value - Stored buffer pointer + * length - Buffer length + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_nvs_set_blob(uint32_t handle, + const char *key, + const void *value, + size_t length) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_nvs_get_i8 + * + * Description: + * Read data of type int8_t from file system + * + * Input Parameters: + * handle - NVS handle + * key - Data index + * out_value - Read buffer pointer + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_nvs_get_i8(uint32_t handle, + const char *key, + int8_t *out_value) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_nvs_set_i8 + * + * Description: + * Save data of type int8_t into file system + * + * Input Parameters: + * handle - NVS handle + * key - Data index + * value - Stored data + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_nvs_set_i8(uint32_t handle, + const char *key, + int8_t value) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_nvs_get_u8 + * + * Description: + * Read data of type uint8_t from file system + * + * Input Parameters: + * handle - NVS handle + * key - Data index + * out_value - Read buffer pointer + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_nvs_get_u8(uint32_t handle, + const char *key, + uint8_t *out_value) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_nvs_set_u8 + * + * Description: + * Save data of type uint8_t into file system + * + * Input Parameters: + * handle - NVS handle + * key - Data index + * value - Stored data + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_nvs_set_u8(uint32_t handle, + const char *key, + uint8_t value) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_nvs_get_u16 + * + * Description: + * Read data of type uint16_t from file system + * + * Input Parameters: + * handle - NVS handle + * key - Data index + * out_value - Read buffer pointer + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_nvs_get_u16(uint32_t handle, + const char *key, + uint16_t *out_value) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_nvs_set_u16 + * + * Description: + * Save data of type uint16_t into file system + * + * Input Parameters: + * handle - NVS handle + * key - Data index + * value - Stored data + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_nvs_set_u16(uint32_t handle, + const char *key, + uint16_t value) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_nvs_close + * + * Description: + * Close storage data object and free resource + * + * Input Parameters: + * handle - NVS handle + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static void esp_nvs_close(uint32_t handle) +{ + DEBUGPANIC(); +} + +/**************************************************************************** + * Name: esp_update_time + * + * Description: + * Transform ticks to time and add this time to timespec value + * + * Input Parameters: + * timespec - Input timespec data pointer + * ticks - System ticks + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_update_time(struct timespec *timespec, uint32_t ticks) +{ + uint32_t tmp; + + tmp = TICK2SEC(ticks); + timespec->tv_sec += tmp; + + ticks -= SEC2TICK(tmp); + tmp = TICK2NSEC(ticks); + + timespec->tv_nsec += tmp; +} + +#ifdef ESP_WLAN_HAS_STA + +/**************************************************************************** + * Name: esp_wifi_auth_trans + * + * Description: + * Converts an ESP32-C3 authenticate mode values to WEXT authenticate mode. + * + * Input Parameters: + * wifi_auth - ESP32-C3 authenticate mode + * + * Returned Value: + * authenticate mode + * + ****************************************************************************/ + +static int esp_wifi_auth_trans(uint32_t wifi_auth) +{ + int auth_mode = IW_AUTH_WPA_VERSION_DISABLED; + + switch (wifi_auth) + { + case WIFI_AUTH_OPEN: + auth_mode = IW_AUTH_WPA_VERSION_DISABLED; + break; + + case WIFI_AUTH_WPA_PSK: + auth_mode = IW_AUTH_WPA_VERSION_WPA; + break; + + case WIFI_AUTH_WPA2_PSK: + case WIFI_AUTH_WPA_WPA2_PSK: + auth_mode = IW_AUTH_WPA_VERSION_WPA2; + break; + + case WIFI_AUTH_WPA3_PSK: + case WIFI_AUTH_WPA2_WPA3_PSK: + auth_mode = IW_AUTH_WPA_VERSION_WPA3; + break; + + default: + wlerr("Failed to transfer wireless authmode: %ld", wifi_auth); + break; + } + + return auth_mode; +} + +/**************************************************************************** + * Name: esp_wifi_cipher_trans + * + * Description: + * Converts a ESP32-C3 cipher type values to WEXT cipher type values. + * + * Input Parameters: + * wifi_cipher - ESP32-C3 cipher type + * + * Returned Value: + * cipher type + * + ****************************************************************************/ + +static int esp_wifi_cipher_trans(uint32_t wifi_cipher) +{ + int cipher_mode = IW_AUTH_CIPHER_NONE; + + switch (wifi_cipher) + { + case WIFI_CIPHER_TYPE_NONE: + cipher_mode = IW_AUTH_CIPHER_NONE; + break; + + case WIFI_CIPHER_TYPE_WEP40: + cipher_mode = IW_AUTH_CIPHER_WEP40; + break; + + case WIFI_CIPHER_TYPE_WEP104: + cipher_mode = IW_AUTH_CIPHER_WEP104; + break; + + case WIFI_CIPHER_TYPE_TKIP: + cipher_mode = IW_AUTH_CIPHER_TKIP; + break; + + case WIFI_CIPHER_TYPE_CCMP: + case WIFI_CIPHER_TYPE_TKIP_CCMP: + cipher_mode = IW_AUTH_CIPHER_CCMP; + break; + + case WIFI_CIPHER_TYPE_AES_CMAC128: + cipher_mode = IW_AUTH_CIPHER_AES_CMAC; + break; + + default: + wlerr("Failed to transfer wireless authmode: %ld", + wifi_cipher); + break; + } + + return cipher_mode; +} + +#endif /* ESP_WLAN_HAS_STA */ + +/**************************************************************************** + * Name: esp_wifi_lock + * + * Description: + * Lock or unlock the event process + * + * Input Parameters: + * lock - true: Lock event process, false: unlock event process + * + * Returned Value: + * The result of lock or unlock the event process + * + ****************************************************************************/ + +static int esp_wifi_lock(bool lock) +{ + int ret; + + if (lock) + { + ret = nxmutex_lock(&g_wifiexcl_lock); + if (ret < 0) + { + wlinfo("Failed to lock Wi-Fi ret=%d\n", ret); + } + } + else + { + ret = nxmutex_unlock(&g_wifiexcl_lock); + if (ret < 0) + { + wlinfo("Failed to unlock Wi-Fi ret=%d\n", ret); + } + } + + return ret; +} + +/**************************************************************************** + * Name: queue_msg_waiting_wrapper + * + * Description: + * Get message number in the message queue + * + * Input Parameters: + * queue - Message queue data pointer + * + * Returned Value: + * Message number + * + ****************************************************************************/ + +static uint32_t queue_msg_waiting_wrapper(void *queue) +{ + int ret; + struct mq_attr attr; + struct mq_adpt *mq_adpt = (struct mq_adpt *)queue; + + ret = file_mq_getattr(&mq_adpt->mq, &attr); + if (ret < 0) + { + wlerr("Failed to get attr from mqueue error=%d\n", ret); + return 0; + } + + return attr.mq_curmsgs; +} + +/**************************************************************************** + * Name: task_delay_wrapper + * + * Description: + * Current task wait for some ticks + * + * Input Parameters: + * tick - Waiting ticks + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void task_delay_wrapper(uint32_t tick) +{ + useconds_t us = TICK2USEC(tick); + + nxsig_usleep(us); +} + +/**************************************************************************** + * Name: task_delete_wrapper + * + * Description: + * Delete the target task + * + * Input Parameters: + * task_handle - Task handle pointer which is used to pause, resume + * and delete the task + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void task_delete_wrapper(void *task_handle) +{ + pid_t pid = (pid_t)((uintptr_t)task_handle); + + kthread_delete(pid); +} + +/**************************************************************************** + * Name: task_get_current_task_wrapper + * + * Description: + * This function gets the current task's PID and returns it as a void + * pointer. This is a wrapper around the NuttX function nxsched_getpid. + * + * Input Parameters: + * None + * + * Returned Value: + * The current task's PID as a void pointer. + * + ****************************************************************************/ + +static void *task_get_current_task_wrapper(void) +{ + pid_t pid = nxsched_getpid(); + + return (void *)((uintptr_t)pid); +} + +/**************************************************************************** + * Name: vqueue_delete_adapter + * + * Description: + * This function deletes a queue adapter. It closes the message queue, + * unlinks it, and then frees the memory allocated for the queue adapter. + * + * Input Parameters: + * queue - A pointer to the queue adapter to be deleted. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void vqueue_delete_adapter(void *queue) +{ + struct mq_adpt *mq_adpt = (struct mq_adpt *)queue; + + file_mq_close(&mq_adpt->mq); + file_mq_unlink(mq_adpt->name); + kmm_free(mq_adpt); +} + +/**************************************************************************** + * Name: vsemaphore_delete_adapter + * + * Description: + * Delete semaphore + * + * Input Parameters: + * semphr - Semaphore data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void vsemaphore_delete_adapter(void *semphr) +{ + sem_t *sem = (sem_t *)semphr; + + nxsem_destroy(sem); + kmm_free(sem); +} + +/**************************************************************************** + * Name: xqueue_create_adapter + * + * Description: + * Create message queue + * + * Input Parameters: + * queue_len - queue message number + * item_size - message size + * + * Returned Value: + * Message queue data pointer + * + ****************************************************************************/ + +static void *xqueue_create_adapter(uint32_t queue_len, uint32_t item_size) +{ + struct mq_attr attr; + struct mq_adpt *mq_adpt; + int ret; + + mq_adpt = kmm_malloc(sizeof(struct mq_adpt)); + if (!mq_adpt) + { + wlerr("Failed to kmm_malloc\n"); + return NULL; + } + + snprintf(mq_adpt->name, sizeof(mq_adpt->name), + "/tmp/%p", mq_adpt); + + attr.mq_maxmsg = queue_len; + attr.mq_msgsize = item_size; + attr.mq_curmsgs = 0; + attr.mq_flags = 0; + + ret = file_mq_open(&mq_adpt->mq, mq_adpt->name, + O_RDWR | O_CREAT, 0644, &attr); + if (ret < 0) + { + wlerr("Failed to create mqueue\n"); + kmm_free(mq_adpt); + return NULL; + } + + mq_adpt->msgsize = item_size; + + return (void *)mq_adpt; +} + +/**************************************************************************** + * Name: xqueue_send_adapter + * + * Description: + * Generic send message to queue within a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * ticks - Wait ticks + * prio - Message priority + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t xqueue_send_adapter(void *queue, + void *item, + uint32_t ticks, + int prio) +{ + int ret; + struct timespec timeout; + struct mq_adpt *mq_adpt = (struct mq_adpt *)queue; + + if (ticks == OSI_FUNCS_TIME_BLOCKING || ticks == 0) + { + /* Wi-Fi interrupt function will call this adapter function to send + * message to message queue, so here we should call kernel API + * instead of application API + */ + + ret = file_mq_send(&mq_adpt->mq, (const char *)item, + mq_adpt->msgsize, prio); + if (ret < 0) + { + wlerr("Failed to send message to mqueue error=%d\n", + ret); + } + } + else + { + ret = clock_gettime(CLOCK_REALTIME, &timeout); + if (ret < 0) + { + wlerr("Failed to get time\n"); + return false; + } + + if (ticks) + { + esp_update_time(&timeout, ticks); + } + + ret = file_mq_timedsend(&mq_adpt->mq, (const char *)item, + mq_adpt->msgsize, prio, &timeout); + if (ret < 0) + { + wlerr("Failed to timedsend message to mqueue error=%d\n", + ret); + } + } + + return nuttx_err_to_freertos(ret); +} + +/**************************************************************************** + * Name: xsemaphore_create_counting_adapter + * + * Description: + * Create and initialize semaphore + * + * Input Parameters: + * max - No meanining for NuttX + * init - semaphore initialization value + * + * Returned Value: + * Semaphore data pointer + * + ****************************************************************************/ + +void *xsemaphore_create_counting_adapter(uint32_t max, uint32_t init) +{ + int ret; + sem_t *sem; + int tmp; + + tmp = sizeof(sem_t); + sem = kmm_malloc(tmp); + if (!sem) + { + wlerr("Failed to alloc %d memory\n", tmp); + return NULL; + } + + ret = nxsem_init(sem, 0, init); + if (ret) + { + wlerr("Failed to initialize sem error=%d\n", ret); + kmm_free(sem); + return NULL; + } + + return sem; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: wifi_malloc + * + * Description: + * Applications allocate a block of memory + * + * Input Parameters: + * size - memory size + * + * Returned Value: + * Memory pointer + * + ****************************************************************************/ + +IRAM_ATTR void *wifi_malloc(size_t size) +{ + return malloc(size); +} + +/**************************************************************************** + * Name: wifi_realloc + * + * Description: + * Applications allocate a block of memory by old memory block + * + * Input Parameters: + * ptr - old memory pointer + * size - memory size + * + * Returned Value: + * New memory pointer + * + ****************************************************************************/ + +IRAM_ATTR void *wifi_realloc(void *ptr, size_t size) +{ + return realloc(ptr, size); +} + +/**************************************************************************** + * Name: wifi_calloc + * + * Description: + * Applications allocate some continuous blocks of memory + * + * Input Parameters: + * n - memory block number + * size - memory block size + * + * Returned Value: + * New memory pointer + * + ****************************************************************************/ + +IRAM_ATTR void *wifi_calloc(size_t n, size_t size) +{ + return calloc(n, size); +} + +/**************************************************************************** + * Name: esp_wifi_notify_subscribe + * + * Description: + * Enable event notification + * + * Input Parameters: + * pid - Task PID + * event - Signal event data pointer + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +int esp_wifi_notify_subscribe(pid_t pid, struct sigevent *event) +{ + int id; + struct wifi_notify *notify; + int ret = -1; + + wlinfo("PID=%d event=%p\n", pid, event); + + esp_wifi_lock(true); + + if (event->sigev_notify == SIGEV_SIGNAL) + { + id = esp_event_id_map(event->sigev_signo); + if (id < 0) + { + wlerr("No process event %d\n", event->sigev_signo); + } + else + { + notify = &g_wifi_notify[id]; + + if (notify->assigned) + { + wlerr("sigev_signo %d has subscribed\n", + event->sigev_signo); + } + else + { + if (pid == 0) + { + pid = nxsched_getpid(); + wlinfo("Actual PID=%d\n", pid); + } + + notify->pid = pid; + notify->event = *event; + notify->assigned = true; + + ret = 0; + } + } + } + else if (event->sigev_notify == SIGEV_NONE) + { + id = esp_event_id_map(event->sigev_signo); + if (id < 0) + { + wlerr("No process event %d\n", event->sigev_signo); + } + else + { + notify = &g_wifi_notify[id]; + + if (!notify->assigned) + { + wlerr("sigev_signo %d has not subscribed\n", + event->sigev_signo); + } + else + { + notify->assigned = false; + + ret = 0; + } + } + } + else + { + wlerr("sigev_notify %d is invalid\n", event->sigev_signo); + } + + esp_wifi_lock(false); + + return ret; +} + +/**************************************************************************** + * Name: esp_wifi_adapter_init + * + * Description: + * Initialize ESP32-C3 Wi-Fi adapter + * + * Input Parameters: + * None + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +int esp_wifi_adapter_init(void) +{ + int ret; + wifi_init_config_t wifi_cfg = WIFI_INIT_CONFIG_DEFAULT(); + + esp_wifi_lock(true); + + if (g_wifi_ref) + { + wlinfo("Wi-Fi adapter is already initialized\n"); + g_wifi_ref++; + esp_wifi_lock(false); + return OK; + } + + sq_init(&g_wifi_evt_queue); + + wifi_cfg.nvs_enable = 0; + +#ifdef CONFIG_ESPRESSIF_WIFI_AMPDU_TX_ENABLED + wifi_cfg.ampdu_tx_enable = 1; +#else + wifi_cfg.ampdu_tx_enable = 0; +#endif + +#ifdef CONFIG_ESPRESSIF_WIFI_AMPDU_RX_ENABLED + wifi_cfg.ampdu_rx_enable = 1; +#else + wifi_cfg.ampdu_rx_enable = 0; +#endif + +#ifdef CONFIG_ESPRESSIF_WIFI_STA_DISCONNECT_PM + wifi_cfg.sta_disconnected_pm = true; +#else + wifi_cfg.sta_disconnected_pm = false; +#endif + + wifi_cfg.rx_ba_win = CONFIG_ESPRESSIF_WIFI_TX_BA_WIN; + wifi_cfg.static_rx_buf_num = CONFIG_ESPRESSIF_WIFI_STATIC_RX_BUFFER_NUM; + wifi_cfg.dynamic_rx_buf_num = CONFIG_ESPRESSIF_WIFI_DYNAMIC_RX_BUFFER_NUM; + wifi_cfg.dynamic_tx_buf_num = CONFIG_ESPRESSIF_WIFI_DYNAMIC_TX_BUFFER_NUM; + + ret = esp_wifi_init(&wifi_cfg); + if (ret) + { + wlerr("Failed to initialize Wi-Fi error=%d\n", ret); + ret = esp_wifi_to_errno(ret); + goto errout_init_wifi; + } + + ret = esp_wifi_set_tx_done_cb(esp_wifi_tx_done_cb); + if (ret) + { + wlerr("Failed to register TX done callback ret=%d\n", ret); + ret = esp_wifi_to_errno(ret); + goto errout_init_txdone; + } + + g_wifi_ref++; + + wlinfo("OK to initialize Wi-Fi adapter\n"); + + esp_wifi_lock(false); + + return OK; + +errout_init_txdone: + esp_wifi_deinit(); +errout_init_wifi: + esp_wifi_lock(false); + + return ret; +} + +/**************************************************************************** + * Station functions + ****************************************************************************/ + +#ifdef ESP_WLAN_HAS_STA + +/**************************************************************************** + * Name: esp_wifi_sta_start + * + * Description: + * Start Wi-Fi station. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_start(void) +{ + int ret; + wifi_mode_t mode; + + esp_wifi_lock(true); + + ret = esp_wifi_stop(); + if (ret) + { + wlinfo("Failed to stop Wi-Fi ret=%d\n", ret); + } + +#ifdef ESP_WLAN_HAS_SOFTAP + if (g_softap_started) + { + mode = WIFI_MODE_APSTA; + } + else +#endif /* ESP_WLAN_HAS_SOFTAP */ + { + mode = WIFI_MODE_STA; + } + + ret = esp_wifi_set_mode(mode); + if (ret) + { + wlerr("Failed to set Wi-Fi mode=%d ret=%d\n", mode, ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + + ret = esp_wifi_start(); + if (ret) + { + wlerr("Failed to start Wi-Fi with mode=%d ret=%d\n", mode, ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + + g_sta_started = true; + + wlinfo("OK to start Wi-Fi station\n"); + +errout: + esp_wifi_lock(false); + return ret; +} + +/**************************************************************************** + * Name: esp_wifi_sta_stop + * + * Description: + * Stop Wi-Fi station. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_stop(void) +{ + int ret; + + esp_wifi_lock(true); + + ret = esp_wifi_stop(); + if (ret) + { + wlinfo("Failed to stop Wi-Fi ret=%d\n", ret); + } + + g_sta_started = false; + +#ifdef ESP_WLAN_HAS_SOFTAP + if (g_softap_started) + { + ret = esp_wifi_set_mode(WIFI_MODE_AP); + if (ret) + { + wlerr("Failed to set Wi-Fi AP mode ret=%d\n", ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + + ret = esp_wifi_start(); + if (ret) + { + wlerr("Failed to start Wi-Fi AP ret=%d\n", ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + } +#endif /* ESP_WLAN_HAS_SOFTAP */ + + wlinfo("OK to stop Wi-Fi station\n"); + +#ifdef ESP_WLAN_HAS_SOFTAP +errout: +#endif /* ESP_WLAN_HAS_SOFTAP */ + + esp_wifi_lock(false); + return ret; +} + +/**************************************************************************** + * Name: esp_wifi_sta_send_data + * + * Description: + * Use Wi-Fi station interface to send 802.3 frame + * + * Input Parameters: + * pbuf - Packet buffer pointer + * len - Packet length + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_send_data(void *pbuf, size_t len) +{ + int ret; + + ret = esp_wifi_internal_tx(WIFI_IF_STA, pbuf, len); + + return esp_wifi_to_errno(ret); +} + +/**************************************************************************** + * Name: esp_wifi_set_password + * + * Description: + * Set/Get Wi-Fi station password + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_password(struct iwreq *iwr, bool set) +{ + int ret; + int size; + wifi_config_t wifi_cfg; + struct iw_encode_ext *ext = iwr->u.encoding.pointer; + uint8_t *pdata; + uint8_t len; +#ifdef CONFIG_DEBUG_WIRELESS_INFO + char buf[PWD_MAX_LEN + 1]; +#endif + + DEBUGASSERT(ext != NULL); + + pdata = ext->key; + + wifi_cfg = g_sta_wifi_cfg; + + if (set) + { + len = ext->key_len; + if (len > PWD_MAX_LEN) + { + return -EINVAL; + } + + memset(wifi_cfg.sta.password, 0x0, PWD_MAX_LEN); + + if (ext->alg != IW_ENCODE_ALG_NONE) + { + memcpy(wifi_cfg.sta.password, pdata, len); + } + + wifi_cfg.sta.pmf_cfg.capable = true; + + if (g_sta_connected) + { + ret = esp_wifi_sta_disconnect(); + if (ret) + { + wlerr("Failed to disconnect from Wi-Fi AP ret=%d\n", ret); + return ret; + } + + ret = esp_wifi_set_config(WIFI_IF_STA, &wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + ret = esp_wifi_sta_connect(); + if (ret) + { + wlerr("Failed to connect to Wi-Fi AP ret=%d\n", ret); + return ret; + } + } + + g_sta_wifi_cfg = wifi_cfg; + } + else + { + len = iwr->u.encoding.length - sizeof(*ext); + size = strnlen((char *)wifi_cfg.sta.password, PWD_MAX_LEN); + if (len < size) + { + return -EINVAL; + } + else + { + ext->key_len = size; + memcpy(pdata, wifi_cfg.sta.password, ext->key_len); + } + + if (g_sta_connected) + { + wifi_ap_record_t ap_info; + + ret = esp_wifi_sta_get_ap_info(&ap_info); + if (ret) + { + wlerr("Failed to get AP record ret=%d", ret); + return esp_wifi_to_errno(ret); + } + + switch (ap_info.pairwise_cipher) + { + case WIFI_CIPHER_TYPE_NONE: + ext->alg = IW_ENCODE_ALG_NONE; + break; + + case WIFI_CIPHER_TYPE_WEP40: + case WIFI_CIPHER_TYPE_WEP104: + ext->alg = IW_ENCODE_ALG_WEP; + break; + + case WIFI_CIPHER_TYPE_TKIP: + ext->alg = IW_ENCODE_ALG_TKIP; + break; + + case WIFI_CIPHER_TYPE_CCMP: + case WIFI_CIPHER_TYPE_TKIP_CCMP: + ext->alg = IW_ENCODE_ALG_CCMP; + break; + + case WIFI_CIPHER_TYPE_AES_CMAC128: + ext->alg = IW_ENCODE_ALG_AES_CMAC; + break; + + default: + wlerr("Failed to transfer wireless authmode: %d", + ap_info.pairwise_cipher); + return -EIO; + } + } + } + +#ifdef CONFIG_DEBUG_WIRELESS_INFO + memcpy(buf, pdata, len); + buf[len] = 0; + wlinfo("Wi-Fi station password=%s len=%d\n", buf, len); +#endif + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_sta_essid + * + * Description: + * Set/Get Wi-Fi station ESSID + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_essid(struct iwreq *iwr, bool set) +{ + int ret; + int size; + wifi_config_t wifi_cfg; + struct iw_point *essid = &iwr->u.essid; + uint8_t *pdata; + uint8_t len; +#ifdef CONFIG_DEBUG_WIRELESS_INFO + char buf[SSID_MAX_LEN + 1]; +#endif + + DEBUGASSERT(essid != NULL); + + pdata = essid->pointer; + len = essid->length; + + if (set && len > SSID_MAX_LEN) + { + return -EINVAL; + } + + wifi_cfg = g_sta_wifi_cfg; + + if (set) + { + memset(wifi_cfg.sta.ssid, 0x0, SSID_MAX_LEN); + memcpy(wifi_cfg.sta.ssid, pdata, len); + memset(wifi_cfg.sta.sae_h2e_identifier, 0x0, SAE_H2E_IDENTIFIER_LEN); + wifi_cfg.sta.sae_pwe_h2e = WPA3_SAE_PWE_BOTH; + + if (g_sta_connected) + { + ret = esp_wifi_sta_disconnect(); + if (ret) + { + wlerr("Failed to disconnect from Wi-Fi AP ret=%d\n", ret); + return ret; + } + + ret = esp_wifi_set_config(WIFI_IF_STA, &wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + ret = esp_wifi_sta_connect(); + if (ret) + { + wlerr("Failed to connect to Wi-Fi AP ret=%d\n", ret); + return ret; + } + } + + g_sta_wifi_cfg = wifi_cfg; + } + else + { + size = strnlen((char *)wifi_cfg.sta.ssid, SSID_MAX_LEN); + if (len < size) + { + return -EINVAL; + } + else + { + len = size; + memcpy(pdata, wifi_cfg.sta.ssid, len); + } + + if (g_sta_connected) + { + essid->flags = IW_ESSID_ON; + } + else + { + essid->flags = IW_ESSID_OFF; + } + } + +#ifdef CONFIG_DEBUG_WIRELESS_INFO + memcpy(buf, pdata, len); + buf[len] = 0; + wlinfo("Wi-Fi station ssid=%s len=%d\n", buf, len); +#endif + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_sta_bssid + * + * Description: + * Set/Get Wi-Fi station BSSID + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_bssid(struct iwreq *iwr, bool set) +{ + int ret; + wifi_config_t wifi_cfg; + struct sockaddr *sockaddr; + char *pdata; + + sockaddr = &iwr->u.ap_addr; + pdata = sockaddr->sa_data; + + wifi_cfg = g_sta_wifi_cfg; + + if (set) + { + wifi_cfg.sta.bssid_set = true; + memcpy(wifi_cfg.sta.bssid, pdata, MAC_LEN); + + if (g_sta_connected) + { + ret = esp_wifi_sta_disconnect(); + if (ret) + { + wlerr("Failed to disconnect from Wi-Fi AP ret=%d\n", ret); + return ret; + } + + ret = esp_wifi_set_config(WIFI_IF_STA, &wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + ret = esp_wifi_sta_connect(); + if (ret) + { + wlerr("Failed to connect to Wi-Fi AP ret=%d\n", ret); + return ret; + } + } + + g_sta_wifi_cfg = wifi_cfg; + } + else + { + memcpy(pdata, wifi_cfg.sta.bssid, MAC_LEN); + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_sta_connect + * + * Description: + * Trigger Wi-Fi station connection action + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_connect(void) +{ + int ret; + uint32_t ticks; + + esp_wifi_lock(true); + + if (g_sta_connected) + { + wlinfo("Wi-Fi has connected AP\n"); + esp_wifi_lock(false); + return OK; + } + + g_sta_reconnect = true; + + ret = esp_wifi_set_config(WIFI_IF_STA, &g_sta_wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + ret = esp_wifi_connect(); + if (ret) + { + wlerr("Failed to connect ret=%d\n", ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + + esp_wifi_lock(false); + + ticks = SEC2TICK(WIFI_CONNECT_TIMEOUT); + do + { + if (g_sta_connected) + { + break; + } + + task_delay_wrapper(1); + } + while (ticks--); + + if (!g_sta_connected) + { + g_sta_reconnect = false; + wlinfo("Failed to connect to AP\n"); + return -1; + } + + return OK; + +errout: + g_sta_reconnect = false; + esp_wifi_lock(false); + return ret; +} + +/**************************************************************************** + * Name: esp_wifi_sta_disconnect + * + * Description: + * Trigger Wi-Fi station disconnection action + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_disconnect(void) +{ + int ret; + + esp_wifi_lock(true); + + g_sta_reconnect = false; + + ret = esp_wifi_disconnect(); + if (ret) + { + wlerr("Failed to disconnect ret=%d\n", ret); + ret = esp_wifi_to_errno(ret); + } + else + { + wlinfo("OK to disconnect Wi-Fi station\n"); + } + + esp_wifi_lock(false); + return ret; +} + +/**************************************************************************** + * Name: esp_wifi_sta_mode + * + * Description: + * Set/Get Wi-Fi Station mode code. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_mode(struct iwreq *iwr, bool set) +{ + if (set == false) + { + iwr->u.mode = IW_MODE_INFRA; + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_sta_auth + * + * Description: + * Set/Get station authentication mode params. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_auth(struct iwreq *iwr, bool set) +{ + int ret; + int cmd; + wifi_config_t wifi_cfg; + wifi_ap_record_t ap_info; + + wifi_cfg = g_sta_wifi_cfg; + + if (set) + { + cmd = iwr->u.param.flags & IW_AUTH_INDEX; + switch (cmd) + { + case IW_AUTH_WPA_VERSION: + { + switch (iwr->u.param.value) + { + case IW_AUTH_WPA_VERSION_DISABLED: + wifi_cfg.sta.threshold.authmode = WIFI_AUTH_OPEN; + break; + + case IW_AUTH_WPA_VERSION_WPA: + wifi_cfg.sta.threshold.authmode = WIFI_AUTH_WPA_PSK; + break; + + case IW_AUTH_WPA_VERSION_WPA2: + wifi_cfg.sta.threshold.authmode = WIFI_AUTH_WPA2_PSK; + break; + + case IW_AUTH_WPA_VERSION_WPA3: + wifi_cfg.sta.threshold.authmode = WIFI_AUTH_WPA3_PSK; + break; + + default: + wlerr("Invalid wpa version %" PRId32 "\n", + iwr->u.param.value); + return -EINVAL; + } + } + + break; + case IW_AUTH_CIPHER_PAIRWISE: + case IW_AUTH_CIPHER_GROUP: + { + switch (iwr->u.param.value) + { + case IW_AUTH_CIPHER_NONE: + wifi_cfg.sta.threshold.authmode = WIFI_AUTH_OPEN; + break; + + case IW_AUTH_CIPHER_WEP40: + case IW_AUTH_CIPHER_WEP104: + wifi_cfg.sta.threshold.authmode = WIFI_AUTH_WEP; + break; + + case IW_AUTH_CIPHER_TKIP: + case IW_AUTH_CIPHER_CCMP: + case IW_AUTH_CIPHER_AES_CMAC: + break; + + default: + wlerr("Invalid cipher mode %" PRId32 "\n", + iwr->u.param.value); + return -EINVAL; + } + } + + break; + case IW_AUTH_KEY_MGMT: + case IW_AUTH_TKIP_COUNTERMEASURES: + case IW_AUTH_DROP_UNENCRYPTED: + case IW_AUTH_80211_AUTH_ALG: + case IW_AUTH_WPA_ENABLED: + case IW_AUTH_RX_UNENCRYPTED_EAPOL: + case IW_AUTH_ROAMING_CONTROL: + case IW_AUTH_PRIVACY_INVOKED: + default: + wlerr("Unknown cmd %d\n", cmd); + return -EINVAL; + } + + size_t password_len = strlen((const char *)wifi_cfg.sta.password); + wifi_auth_mode_t authmode = wifi_cfg.sta.threshold.authmode; + + if (g_sta_connected && + ((password_len > 0 && authmode != WIFI_AUTH_OPEN) || + (password_len == 0 && authmode == WIFI_AUTH_OPEN))) + { + ret = esp_wifi_sta_disconnect(); + if (ret) + { + wlerr("Failed to disconnect from Wi-Fi AP ret=%d\n", ret); + return ret; + } + + ret = esp_wifi_set_config(WIFI_IF_STA, &wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + ret = esp_wifi_sta_connect(); + if (ret) + { + wlerr("Failed to connect to Wi-Fi AP ret=%d\n", ret); + return ret; + } + } + + g_sta_wifi_cfg = wifi_cfg; + } + else + { + if (g_sta_connected == false) + { + return -ENOTCONN; + } + + ret = esp_wifi_sta_get_ap_info(&ap_info); + if (ret) + { + wlerr("Failed to get AP record ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + cmd = iwr->u.param.flags & IW_AUTH_INDEX; + switch (cmd) + { + case IW_AUTH_WPA_VERSION: + iwr->u.param.value = esp_wifi_auth_trans(ap_info.authmode); + break; + + case IW_AUTH_CIPHER_PAIRWISE: + iwr->u.param.value = + esp_wifi_cipher_trans(ap_info.pairwise_cipher); + break; + + case IW_AUTH_CIPHER_GROUP: + iwr->u.param.value = esp_wifi_cipher_trans(ap_info.group_cipher); + break; + + case IW_AUTH_KEY_MGMT: + case IW_AUTH_TKIP_COUNTERMEASURES: + case IW_AUTH_DROP_UNENCRYPTED: + case IW_AUTH_80211_AUTH_ALG: + case IW_AUTH_WPA_ENABLED: + case IW_AUTH_RX_UNENCRYPTED_EAPOL: + case IW_AUTH_ROAMING_CONTROL: + case IW_AUTH_PRIVACY_INVOKED: + default: + wlerr("Unknown cmd %d\n", cmd); + return -ENOSYS; + } + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_sta_freq + * + * Description: + * Set/Get station frequency. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_freq(struct iwreq *iwr, bool set) +{ + int ret; + + if (set && (iwr->u.freq.flags == IW_FREQ_FIXED)) + { + wifi_config_t wifi_cfg = g_sta_wifi_cfg; + + wifi_cfg.sta.channel = esp_freq_to_channel(iwr->u.freq.m); + + if (g_sta_connected) + { + ret = esp_wifi_sta_disconnect(); + if (ret) + { + wlerr("Failed to disconnect from Wi-Fi AP ret=%d\n", ret); + return ret; + } + + ret = esp_wifi_set_config(WIFI_IF_STA, &wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + ret = esp_wifi_sta_connect(); + if (ret) + { + wlerr("Failed to connect to Wi-Fi AP ret=%d\n", ret); + return ret; + } + } + + g_sta_wifi_cfg = wifi_cfg; + } + else + { + if (g_sta_connected) + { + wifi_ap_record_t ap_info; + + ret = esp_wifi_sta_get_ap_info(&ap_info); + if (ret) + { + wlerr("Failed to get AP record ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + iwr->u.freq.flags = IW_FREQ_FIXED; + iwr->u.freq.e = 0; + iwr->u.freq.m = 2407 + 5 * ap_info.primary; + } + else + { + iwr->u.freq.flags = IW_FREQ_AUTO; + iwr->u.freq.e = 0; + iwr->u.freq.m = 2412; + } + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_sta_bitrate + * + * Description: + * Get station default bit rate (Mbps). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_bitrate(struct iwreq *iwr, bool set) +{ + int ret; + wifi_ap_record_t ap_info; + + if (set) + { + return -ENOSYS; + } + else + { + if (g_sta_connected == false) + { + iwr->u.bitrate.fixed = IW_FREQ_AUTO; + return OK; + } + + ret = esp_wifi_sta_get_ap_info(&ap_info); + if (ret) + { + wlerr("Failed to get AP record ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + iwr->u.bitrate.fixed = IW_FREQ_FIXED; + if (ap_info.phy_11n) + { + if (ap_info.second) + { + iwr->u.bitrate.value = ESP_WIFI_11N_MCS7_HT40_BITRATE; + } + else + { + iwr->u.bitrate.value = ESP_WIFI_11N_MCS7_HT20_BITRATE; + } + } + else if (ap_info.phy_11g) + { + iwr->u.bitrate.value = ESP_WIFI_11G_MAX_BITRATE; + } + else if (ap_info.phy_11b) + { + iwr->u.bitrate.value = ESP_WIFI_11B_MAX_BITRATE; + } + else + { + return -EIO; + } + } + + return OK; +} + +#endif /* ESP_WLAN_HAS_STA */ + +/**************************************************************************** + * Name: esp_wifi_sta_get_txpower + * + * Description: + * Get station transmit power (dBm). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_txpower(struct iwreq *iwr, bool set) +{ + int ret; + int8_t power; + double power_dbm; + + if (set) + { + if (iwr->u.txpower.flags == IW_TXPOW_RELATIVE) + { + power = (int8_t)iwr->u.txpower.value; + } + else + { + if (iwr->u.txpower.flags == IW_TXPOW_MWATT) + { + power_dbm = ceil(10 * log10(iwr->u.txpower.value)); + } + else + { + power_dbm = iwr->u.txpower.value; + } + + power = (int8_t)(power_dbm * 4); + } + + /* The value set by this API will be mapped to the max_tx_power + * of the structure wifi_country_t variable. Param power unit is + * 0.25dBm, range is [8, 84] corresponding to 2dBm - 20dBm. + * Relationship between set value and actual value. + * As follows: {set value range, actual value} = + * {{[8, 19],8}, {[20, 27],20}, {[28, 33],28}, + * {[34, 43],34}, {[44, 51],44}, {[52, 55],52}, + * {[56, 59],56}, {[60, 65],60}, {[66, 71],66}, + * {[72, 79],72}, {[80, 84],80}}. + */ + + if (power < 8 || power > 84) + { + wlerr("Failed to set transmit power =%d\n", power); + return -ENOSYS; + } + + esp_wifi_set_max_tx_power(power); + return OK; + } + else + { + ret = esp_wifi_get_max_tx_power(&power); + if (ret) + { + wlerr("Failed to get transmit power ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + iwr->u.txpower.disabled = 0; + iwr->u.txpower.flags = IW_TXPOW_DBM; + iwr->u.txpower.value = power / 4; + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_sta_channel + * + * Description: + * Get station range of channel parameters. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_channel(struct iwreq *iwr, bool set) +{ + int ret; + int k; + wifi_country_t country; + struct iw_range *range; + + if (set) + { + return -ENOSYS; + } + else + { + ret = esp_wifi_get_country(&country); + if (ret) + { + wlerr("Failed to get country info ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + range = (struct iw_range *)iwr->u.data.pointer; + range->num_frequency = country.nchan; + for (k = 1; k <= range->num_frequency; k++) + { + range->freq[k - 1].i = k; + range->freq[k - 1].e = 0; + range->freq[k - 1].m = 2407 + 5 * k; + } + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_sta_country + * + * Description: + * Configure country info. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_country(struct iwreq *iwr, bool set) +{ + int ret; + char *country_code; + wifi_country_t country; + + if (set) + { + memset(&country, 0x00, sizeof(wifi_country_t)); + country.schan = 1; + country.policy = 0; + + country_code = (char *)iwr->u.data.pointer; + if (strlen(country_code) != 2) + { + wlerr("Invalid input arguments\n"); + return -EINVAL; + } + + if (strncmp(country_code, "US", 3) == 0 || + strncmp(country_code, "CA", 3) == 0) + { + country.nchan = 11; + } + else if(strncmp(country_code, "JP", 3) == 0) + { + country.nchan = 14; + } + else + { + country.nchan = 13; + } + + memcpy(country.cc, country_code, 2); + ret = esp_wifi_set_country(&country); + if (ret) + { + wlerr("Failed to Configure country ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + } + else + { + return -ENOSYS; + } + + return OK; +} + +#ifdef ESP_WLAN_HAS_STA + +/**************************************************************************** + * Name: esp_wifi_sta_rssi + * + * Description: + * Get Wi-Fi sensitivity (dBm). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_rssi(struct iwreq *iwr, bool set) +{ + int ret; + wifi_ap_record_t ap_info; + + if (set) + { + return -ENOSYS; + } + else + { + if (g_sta_connected == false) + { + iwr->u.sens.value = 128; + return OK; + } + + ret = esp_wifi_sta_get_ap_info(&ap_info); + if (ret) + { + wlerr("Failed to get AP record ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + iwr->u.sens.value = -(ap_info.rssi); + } + + return OK; +} +#endif /* ESP_WLAN_HAS_STA */ + +/**************************************************************************** + * SoftAP functions + ****************************************************************************/ + +#ifdef ESP_WLAN_HAS_SOFTAP + +/**************************************************************************** + * Name: esp_wifi_softap_start + * + * Description: + * Start Wi-Fi SoftAP. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_start(void) +{ + int ret; + wifi_mode_t mode; + + esp_wifi_lock(true); + + ret = esp_wifi_stop(); + if (ret) + { + wlinfo("Failed to stop Wi-Fi ret=%d\n", ret); + } + +#ifdef ESP_WLAN_HAS_STA + if (g_sta_started) + { + mode = WIFI_MODE_APSTA; + } + else +#endif /* ESP_WLAN_HAS_STA */ + { + mode = WIFI_MODE_AP; + } + + ret = esp_wifi_set_mode(mode); + if (ret) + { + wlerr("Failed to set Wi-Fi mode=%d ret=%d\n", mode, ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + + ret = esp_wifi_start(); + if (ret) + { + wlerr("Failed to start Wi-Fi with mode=%d ret=%d\n", mode, ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + + g_softap_started = true; + + wlinfo("OK to start Wi-Fi SoftAP\n"); + +errout: + esp_wifi_lock(false); + return ret; +} + +/**************************************************************************** + * Name: esp_wifi_softap_stop + * + * Description: + * Stop Wi-Fi SoftAP. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_stop(void) +{ + int ret; + + esp_wifi_lock(true); + + ret = esp_wifi_stop(); + if (ret) + { + wlinfo("Failed to stop Wi-Fi ret=%d\n", ret); + } + + g_softap_started = false; + +#ifdef ESP_WLAN_HAS_STA + if (g_sta_started) + { + ret = esp_wifi_set_mode(WIFI_MODE_STA); + if (ret) + { + wlerr("Failed to set Wi-Fi AP mode ret=%d\n", ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + + ret = esp_wifi_start(); + if (ret) + { + wlerr("Failed to start Wi-Fi STA ret=%d\n", ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + } +#endif /* ESP_WLAN_HAS_STA */ + + wlinfo("OK to stop Wi-Fi SoftAP\n"); + +#ifdef ESP_WLAN_HAS_STA +errout: +#endif /* ESP_WLAN_HAS_STA */ + + esp_wifi_lock(false); + return ret; +} + +/**************************************************************************** + * Name: esp_wifi_softap_send_data + * + * Description: + * Use Wi-Fi SoftAP interface to send 802.3 frame + * + * Input Parameters: + * pbuf - Packet buffer pointer + * len - Packet length + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_send_data(void *pbuf, size_t len) +{ + int ret; + + ret = esp_wifi_internal_tx(WIFI_IF_AP, pbuf, len); + + return esp_wifi_to_errno(ret); +} + +/**************************************************************************** + * Name: esp_wifi_softap_password + * + * Description: + * Set/Get Wi-Fi SoftAP password + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_password(struct iwreq *iwr, bool set) +{ + int ret; + int size; + wifi_config_t wifi_cfg; + struct iw_encode_ext *ext = iwr->u.encoding.pointer; + uint8_t *pdata; + uint8_t len; +#ifdef CONFIG_DEBUG_WIRELESS_INFO + char buf[PWD_MAX_LEN + 1]; +#endif + + DEBUGASSERT(ext != NULL); + + pdata = ext->key; + len = ext->key_len; + + if (set && len > PWD_MAX_LEN) + { + return -EINVAL; + } + + pdata = ext->key; + len = ext->key_len; + + wifi_cfg = g_softap_wifi_cfg; + + if (set) + { + /* Clear the password field and copy the user password to it */ + + memset(wifi_cfg.ap.password, 0x0, PWD_MAX_LEN); + + if (ext->alg != IW_ENCODE_ALG_NONE) + { + memcpy(wifi_cfg.sta.password, pdata, len); + } + + if (g_softap_started) + { + ret = esp_wifi_set_config(WIFI_IF_AP, &wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + } + + g_softap_wifi_cfg = wifi_cfg; + } + else + { + size = strnlen((char *)wifi_cfg.ap.password, PWD_MAX_LEN); + if (len < size) + { + return -EINVAL; + } + else + { + len = size; + memcpy(pdata, wifi_cfg.ap.password, len); + } + } + +#ifdef CONFIG_DEBUG_WIRELESS_INFO + memcpy(buf, pdata, len); + buf[len] = 0; + wlinfo("Wi-Fi SoftAP password=%s len=%d\n", buf, len); +#endif + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_softap_essid + * + * Description: + * Set/Get Wi-Fi SoftAP ESSID + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_essid(struct iwreq *iwr, bool set) +{ + int ret; + int size; + wifi_config_t wifi_cfg; + struct iw_point *essid = &iwr->u.essid; + uint8_t *pdata; + uint8_t len; +#ifdef CONFIG_DEBUG_WIRELESS_INFO + char buf[SSID_MAX_LEN + 1]; +#endif + + DEBUGASSERT(essid != NULL); + + pdata = essid->pointer; + len = essid->length; + + if (set && len > SSID_MAX_LEN) + { + return -EINVAL; + } + + wifi_cfg = g_softap_wifi_cfg; + + if (set) + { + memset(wifi_cfg.ap.ssid, 0x0, SSID_MAX_LEN); + memcpy(wifi_cfg.ap.ssid, pdata, len); + wifi_cfg.ap.ssid_len = len; + if (g_softap_started) + { + ret = esp_wifi_set_config(WIFI_IF_AP, &wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + } + + g_softap_wifi_cfg = wifi_cfg; + } + else + { + size = strnlen((char *)wifi_cfg.ap.ssid, SSID_MAX_LEN); + if (len < size) + { + return -EINVAL; + } + else + { + len = size; + memcpy(pdata, wifi_cfg.ap.ssid, len); + } + } + +#ifdef CONFIG_DEBUG_WIRELESS_INFO + memcpy(buf, pdata, len); + buf[len] = 0; + wlinfo("Wi-Fi SoftAP ssid=%s len=%d\n", buf, len); +#endif + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_softap_bssid + * + * Description: + * Set/Get Wi-Fi softAP BSSID + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_bssid(struct iwreq *iwr, bool set) +{ + return -ENOSYS; +} + +/**************************************************************************** + * Name: esp_wifi_softap_connect + * + * Description: + * Trigger Wi-Fi SoftAP accept connection action + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_connect(void) +{ + int ret; + + ret = esp_wifi_set_config(WIFI_IF_AP, &g_softap_wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_softap_disconnect + * + * Description: + * Trigger Wi-Fi SoftAP drop connection action + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_disconnect(void) +{ + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_softap_mode + * + * Description: + * Set/Get Wi-Fi SoftAP mode code. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_mode(struct iwreq *iwr, bool set) +{ + if (set == false) + { + iwr->u.mode = IW_MODE_MASTER; + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_softap_auth + * + * Description: + * Set/get authentication mode params. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_auth(struct iwreq *iwr, bool set) +{ + int ret; + int cmd; + wifi_config_t wifi_cfg; + + wifi_cfg = g_softap_wifi_cfg; + + if (set) + { + cmd = iwr->u.param.flags & IW_AUTH_INDEX; + switch (cmd) + { + case IW_AUTH_WPA_VERSION: + { + switch (iwr->u.param.value) + { + case IW_AUTH_WPA_VERSION_DISABLED: + wifi_cfg.ap.authmode = WIFI_AUTH_OPEN; + break; + + case IW_AUTH_WPA_VERSION_WPA: + wifi_cfg.ap.authmode = WIFI_AUTH_WPA_PSK; + break; + + case IW_AUTH_WPA_VERSION_WPA2: + wifi_cfg.ap.authmode = WIFI_AUTH_WPA2_PSK; + break; + + case IW_AUTH_WPA_VERSION_WPA3: + wifi_cfg.ap.pmf_cfg.required = true; + wifi_cfg.ap.pmf_cfg.capable = false; + wifi_cfg.ap.sae_pwe_h2e = WPA3_SAE_PWE_BOTH; + wifi_cfg.ap.authmode = WIFI_AUTH_WPA3_PSK; + break; + + default: + wlerr("Invalid wpa version %" PRId32 "\n", + iwr->u.param.value); + return -EINVAL; + } + } + + break; + case IW_AUTH_CIPHER_PAIRWISE: + case IW_AUTH_CIPHER_GROUP: + { + switch (iwr->u.param.value) + { + case IW_AUTH_CIPHER_NONE: + wifi_cfg.ap.authmode = WIFI_AUTH_OPEN; + break; + + case IW_AUTH_CIPHER_WEP40: + case IW_AUTH_CIPHER_WEP104: + wifi_cfg.ap.authmode = WIFI_AUTH_WEP; + break; + + case IW_AUTH_CIPHER_TKIP: + case IW_AUTH_CIPHER_CCMP: + case IW_AUTH_CIPHER_AES_CMAC: + break; + + default: + wlerr("Invalid cipher mode %" PRId32 "\n", + iwr->u.param.value); + return -EINVAL; + } + } + + break; + case IW_AUTH_KEY_MGMT: + case IW_AUTH_TKIP_COUNTERMEASURES: + case IW_AUTH_DROP_UNENCRYPTED: + case IW_AUTH_80211_AUTH_ALG: + case IW_AUTH_WPA_ENABLED: + case IW_AUTH_RX_UNENCRYPTED_EAPOL: + case IW_AUTH_ROAMING_CONTROL: + case IW_AUTH_PRIVACY_INVOKED: + default: + wlerr("Unknown cmd %d\n", cmd); + return -EINVAL; + } + + size_t password_len = strlen((const char *)wifi_cfg.ap.password); + + if (g_softap_started && + ((password_len > 0 && wifi_cfg.ap.authmode != WIFI_AUTH_OPEN) || + (password_len == 0 && wifi_cfg.ap.authmode == WIFI_AUTH_OPEN))) + { + ret = esp_wifi_set_config(WIFI_IF_AP, &wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + } + + g_softap_wifi_cfg = wifi_cfg; + } + else + { + return -ENOSYS; + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_softap_freq + * + * Description: + * Set/Get SoftAP frequency. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_freq(struct iwreq *iwr, bool set) +{ + int ret; + wifi_config_t wifi_cfg; + + wifi_cfg = g_softap_wifi_cfg; + + if (set) + { + int channel = esp_freq_to_channel(iwr->u.freq.m); + + wifi_cfg.ap.channel = channel; + + if (g_softap_started) + { + ret = esp_wifi_set_config(WIFI_IF_AP, &wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + } + + g_softap_wifi_cfg = wifi_cfg; + } + else + { + iwr->u.freq.flags = IW_FREQ_FIXED; + iwr->u.freq.e = 0; + iwr->u.freq.m = 2407 + 5 * wifi_cfg.ap.channel; + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_softap_get_bitrate + * + * Description: + * Get SoftAP default bit rate (Mbps). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_bitrate(struct iwreq *iwr, bool set) +{ + return -ENOSYS; +} + +/**************************************************************************** + * Name: esp_wifi_softap_txpower + * + * Description: + * Get SoftAP transmit power (dBm). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_txpower(struct iwreq *iwr, bool set) +{ + return esp_wifi_sta_txpower(iwr, set); +} + +/**************************************************************************** + * Name: esp_wifi_softap_channel + * + * Description: + * Get SoftAP range of channel parameters. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_channel(struct iwreq *iwr, bool set) +{ + return esp_wifi_sta_channel(iwr, set); +} + +/**************************************************************************** + * Name: esp_wifi_softap_country + * + * Description: + * Configure country info. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_country(struct iwreq *iwr, bool set) +{ + return esp_wifi_sta_country(iwr, set); +} + +/**************************************************************************** + * Name: esp_wifi_softap_rssi + * + * Description: + * Get Wi-Fi sensitivity (dBm). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_rssi(struct iwreq *iwr, bool set) +{ + return -ENOSYS; +} + +#endif /* ESP_WLAN_HAS_SOFTAP */ diff --git a/arch/risc-v/src/esp32c3/esp_wifi_adapter.h b/arch/risc-v/src/esp32c3/esp_wifi_adapter.h new file mode 100644 index 0000000000000..9ffb186a712ae --- /dev/null +++ b/arch/risc-v/src/esp32c3/esp_wifi_adapter.h @@ -0,0 +1,672 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c3/esp_wifi_adapter.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP_WIFI_ADAPTER_H +#define __ARCH_RISCV_SRC_ESP32C3_ESP_WIFI_ADAPTER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "esp_wlan.h" + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SSID_MAX_LEN (32) +#define PWD_MAX_LEN (64) + +#define CONFIG_IDF_TARGET_ESP32C3 1 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_wifi_adapter_init + * + * Description: + * Initialize ESP32S3 Wi-Fi adapter + * + * Input Parameters: + * None + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +int esp_wifi_adapter_init(void); + +/**************************************************************************** + * Name: esp_wifi_notify_subscribe + * + * Description: + * Enable event notification + * + * Input Parameters: + * pid - Task PID + * event - Signal event data pointer + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +int esp_wifi_notify_subscribe(pid_t pid, struct sigevent *event); + +#ifdef ESP_WLAN_HAS_STA + +/**************************************************************************** + * Name: esp_wifi_sta_start + * + * Description: + * Start Wi-Fi station. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_start(void); + +/**************************************************************************** + * Name: esp_wifi_sta_stop + * + * Description: + * Stop Wi-Fi station. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_stop(void); + +/**************************************************************************** + * Name: esp_wifi_sta_send_data + * + * Description: + * Use Wi-Fi station interface to send 802.3 frame + * + * Input Parameters: + * pbuf - Packet buffer pointer + * len - Packet length + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_send_data(void *pbuf, size_t len); + +/**************************************************************************** + * Name: esp_wifi_set_password + * + * Description: + * Set/Get Wi-Fi station password + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_password(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_essid + * + * Description: + * Set/Get Wi-Fi station ESSID + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_essid(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_bssid + * + * Description: + * Set/Get Wi-Fi station BSSID + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_bssid(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_connect + * + * Description: + * Trigger Wi-Fi station connection action + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_connect(void); + +/**************************************************************************** + * Name: esp_wifi_sta_disconnect + * + * Description: + * Trigger Wi-Fi station disconnection action + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_disconnect(void); + +/**************************************************************************** + * Name: esp_wifi_sta_mode + * + * Description: + * Set/Get Wi-Fi Station mode code. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_mode(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_auth + * + * Description: + * Set/Get station authentication mode params. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_auth(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_freq + * + * Description: + * Get station frequency. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_freq(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_bitrate + * + * Description: + * Get station default bit rate (Mbps). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_bitrate(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_get_txpower + * + * Description: + * Get station transmit power (dBm). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_txpower(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_get_channel_range + * + * Description: + * Get station range of channel parameters. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_channel(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_country + * + * Description: + * Configure country info. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_country(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_rssi + * + * Description: + * Get Wi-Fi sensitivity (dBm). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_rssi(struct iwreq *iwr, bool set); +#endif /* ESP_WLAN_HAS_STA */ + +#ifdef ESP_WLAN_HAS_SOFTAP + +/**************************************************************************** + * Name: esp_wifi_softap_start + * + * Description: + * Start Wi-Fi softAP. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_start(void); + +/**************************************************************************** + * Name: esp_wifi_softap_stop + * + * Description: + * Stop Wi-Fi softAP. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_stop(void); + +/**************************************************************************** + * Name: esp_wifi_softap_send_data + * + * Description: + * Use Wi-Fi softAP interface to send 802.3 frame + * + * Input Parameters: + * pbuf - Packet buffer pointer + * len - Packet length + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_send_data(void *pbuf, size_t len); + +/**************************************************************************** + * Name: esp_wifi_softap_password + * + * Description: + * Set/Get Wi-Fi SoftAP password + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_password(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_essid + * + * Description: + * Set/Get Wi-Fi SoftAP ESSID + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_essid(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_bssid + * + * Description: + * Set/Get Wi-Fi softAP BSSID + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_bssid(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_connect + * + * Description: + * Trigger Wi-Fi softAP accept connection action + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_connect(void); + +/**************************************************************************** + * Name: esp_wifi_softap_disconnect + * + * Description: + * Trigger Wi-Fi softAP drop connection action + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_disconnect(void); + +/**************************************************************************** + * Name: esp_wifi_softap_mode + * + * Description: + * Set/Get Wi-Fi SoftAP mode code. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_mode(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_auth + * + * Description: + * Set/Get authentication mode params. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_auth(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_freq + * + * Description: + * Set/Get SoftAP frequency. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_freq(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_get_bitrate + * + * Description: + * Get SoftAP default bit rate (Mbps). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_bitrate(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_txpower + * + * Description: + * Get SoftAP transmit power (dBm). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_txpower(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_channel + * + * Description: + * Get SoftAP range of channel parameters. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_channel(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_country + * + * Description: + * Configure country info. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_country(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_rssi + * + * Description: + * Get Wi-Fi sensitivity (dBm). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_rssi(struct iwreq *iwr, bool set); +#endif /* ESP_WLAN_HAS_SOFTAP */ + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP_WIFI_ADAPTER_H */ diff --git a/arch/risc-v/src/esp32c3/hal_esp32c3.mk b/arch/risc-v/src/esp32c3/hal_esp32c3.mk new file mode 100644 index 0000000000000..188aaf1ab5c7d --- /dev/null +++ b/arch/risc-v/src/esp32c3/hal_esp32c3.mk @@ -0,0 +1,169 @@ +############################################################################ +# arch/risc-v/src/esp32c3/esp32c3.mk +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Include header paths + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)driver$(DELIM)twai$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_event$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)esp_private +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include$(DELIM)private +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)public_compat +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)platform_port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash + +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)private_include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)include +endif + +# Linker scripts + +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.eco3.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.api.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.version.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).peripherals.ld + +# Source files + +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_api.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_utility.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_fields.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_rtc_calib.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_table.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_utility.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)src$(DELIM)esp_err_to_name.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)adc_share_hw_ctrl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)cpu.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)hw_random.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mac_addr.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)periph_ctrl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modem.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)adc2_init_cal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk_init.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_init.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_sleep.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_time.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)sar_periph_ctrl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)systimer.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)lib_printf.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_systimer.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)esp_err.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)brownout.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_hal_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)brownout_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)efuse_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gpio_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)systimer_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mpu_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mmu_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)twai_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)twai_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)wdt_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)efuse_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log_noos.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)interrupt.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gpio_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c + +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)bootloader_banner_wrap.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_console.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_console_loader.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_${CHIP_SERIES}.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_init.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common_loader.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash_config_${CHIP_SERIES}.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_init.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_loader.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_efuse.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_mem.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random_${CHIP_SERIES}.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)esp_image_format.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_sha.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)flash_encrypt.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_fields.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)efuse_controller$(DELIM)keys$(DELIM)with_key_purposes$(DELIM)esp_efuse_api_key.c + + LDFLAGS += --wrap=bootloader_print_banner +endif diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_aes.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_aes.h deleted file mode 100644 index ee1034b915038..0000000000000 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_aes.h +++ /dev/null @@ -1,780 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_aes.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_AES_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_AES_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32c3_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* AES_KEY_0_REG register - * AES key register 0 - */ - -#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0) - -/* AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; - * Stores AES keys. - */ - -#define AES_KEY_0 0xFFFFFFFF -#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) -#define AES_KEY_0_V 0xFFFFFFFF -#define AES_KEY_0_S 0 - -/* AES_KEY_1_REG register - * AES key register 1 - */ - -#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4) - -/* AES_KEY_1 : R/W; bitpos: [31:0]; default: 0; - * Stores AES keys. - */ - -#define AES_KEY_1 0xFFFFFFFF -#define AES_KEY_1_M (AES_KEY_1_V << AES_KEY_1_S) -#define AES_KEY_1_V 0xFFFFFFFF -#define AES_KEY_1_S 0 - -/* AES_KEY_2_REG register - * AES key register 2 - */ - -#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8) - -/* AES_KEY_2 : R/W; bitpos: [31:0]; default: 0; - * Stores AES keys. - */ - -#define AES_KEY_2 0xFFFFFFFF -#define AES_KEY_2_M (AES_KEY_2_V << AES_KEY_2_S) -#define AES_KEY_2_V 0xFFFFFFFF -#define AES_KEY_2_S 0 - -/* AES_KEY_3_REG register - * AES key register 3 - */ - -#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc) - -/* AES_KEY_3 : R/W; bitpos: [31:0]; default: 0; - * Stores AES keys. - */ - -#define AES_KEY_3 0xFFFFFFFF -#define AES_KEY_3_M (AES_KEY_3_V << AES_KEY_3_S) -#define AES_KEY_3_V 0xFFFFFFFF -#define AES_KEY_3_S 0 - -/* AES_KEY_4_REG register - * AES key register 4 - */ - -#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10) - -/* AES_KEY_4 : R/W; bitpos: [31:0]; default: 0; - * Stores AES keys. - */ - -#define AES_KEY_4 0xFFFFFFFF -#define AES_KEY_4_M (AES_KEY_4_V << AES_KEY_4_S) -#define AES_KEY_4_V 0xFFFFFFFF -#define AES_KEY_4_S 0 - -/* AES_KEY_5_REG register - * AES key register 5 - */ - -#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14) - -/* AES_KEY_5 : R/W; bitpos: [31:0]; default: 0; - * Stores AES keys. - */ - -#define AES_KEY_5 0xFFFFFFFF -#define AES_KEY_5_M (AES_KEY_5_V << AES_KEY_5_S) -#define AES_KEY_5_V 0xFFFFFFFF -#define AES_KEY_5_S 0 - -/* AES_KEY_6_REG register - * AES key register 6 - */ - -#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18) - -/* AES_KEY_6 : R/W; bitpos: [31:0]; default: 0; - * Stores AES keys. - */ - -#define AES_KEY_6 0xFFFFFFFF -#define AES_KEY_6_M (AES_KEY_6_V << AES_KEY_6_S) -#define AES_KEY_6_V 0xFFFFFFFF -#define AES_KEY_6_S 0 - -/* AES_KEY_7_REG register - * AES key register 7 - */ - -#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c) - -/* AES_KEY_7 : R/W; bitpos: [31:0]; default: 0; - * Stores AES keys. - */ - -#define AES_KEY_7 0xFFFFFFFF -#define AES_KEY_7_M (AES_KEY_7_V << AES_KEY_7_S) -#define AES_KEY_7_V 0xFFFFFFFF -#define AES_KEY_7_S 0 - -/* AES_TEXT_IN_0_REG register - * Source data register 0 - */ - -#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20) - -/* AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0; - * Stores the source data when the AES Accelerator operates in the Typical - * AES working mode. - */ - -#define AES_TEXT_IN_0 0xFFFFFFFF -#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S) -#define AES_TEXT_IN_0_V 0xFFFFFFFF -#define AES_TEXT_IN_0_S 0 - -/* AES_TEXT_IN_1_REG register - * Source data register 1 - */ - -#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24) - -/* AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0; - * Stores the source data when the AES Accelerator operates in the Typical - * AES working mode. - */ - -#define AES_TEXT_IN_1 0xFFFFFFFF -#define AES_TEXT_IN_1_M (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S) -#define AES_TEXT_IN_1_V 0xFFFFFFFF -#define AES_TEXT_IN_1_S 0 - -/* AES_TEXT_IN_2_REG register - * Source data register 2 - */ - -#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28) - -/* AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0; - * Stores the source data when the AES Accelerator operates in the Typical - * AES working mode. - */ - -#define AES_TEXT_IN_2 0xFFFFFFFF -#define AES_TEXT_IN_2_M (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S) -#define AES_TEXT_IN_2_V 0xFFFFFFFF -#define AES_TEXT_IN_2_S 0 - -/* AES_TEXT_IN_3_REG register - * Source data register 3 - */ - -#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c) - -/* AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0; - * Stores the source data when the AES Accelerator operates in the Typical - * AES working mode. - */ - -#define AES_TEXT_IN_3 0xFFFFFFFF -#define AES_TEXT_IN_3_M (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S) -#define AES_TEXT_IN_3_V 0xFFFFFFFF -#define AES_TEXT_IN_3_S 0 - -/* AES_TEXT_OUT_0_REG register - * Result data register 0 - */ - -#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30) - -/* AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0; - * Stores the result data when the AES Accelerator operates in the Typical - * AES working mode. - */ - -#define AES_TEXT_OUT_0 0xFFFFFFFF -#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S) -#define AES_TEXT_OUT_0_V 0xFFFFFFFF -#define AES_TEXT_OUT_0_S 0 - -/* AES_TEXT_OUT_1_REG register - * Result data register 1 - */ - -#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34) - -/* AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0; - * Stores the result data when the AES Accelerator operates in the Typical - * AES working mode. - */ - -#define AES_TEXT_OUT_1 0xFFFFFFFF -#define AES_TEXT_OUT_1_M (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S) -#define AES_TEXT_OUT_1_V 0xFFFFFFFF -#define AES_TEXT_OUT_1_S 0 - -/* AES_TEXT_OUT_2_REG register - * Result data register 2 - */ - -#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38) - -/* AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0; - * Stores the result data when the AES Accelerator operates in the Typical - * AES working mode. - */ - -#define AES_TEXT_OUT_2 0xFFFFFFFF -#define AES_TEXT_OUT_2_M (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S) -#define AES_TEXT_OUT_2_V 0xFFFFFFFF -#define AES_TEXT_OUT_2_S 0 - -/* AES_TEXT_OUT_3_REG register - * Result data register 3 - */ - -#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c) - -/* AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0; - * Stores the result data when the AES Accelerator operates in the Typical - * AES working mode. - */ - -#define AES_TEXT_OUT_3 0xFFFFFFFF -#define AES_TEXT_OUT_3_M (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S) -#define AES_TEXT_OUT_3_V 0xFFFFFFFF -#define AES_TEXT_OUT_3_S 0 - -/* AES_MODE_REG register - * AES working mode configuration register - */ - -#define AES_MODE_REG (DR_REG_AES_BASE + 0x40) - -/* AES_MODE : R/W; bitpos: [2:0]; default: 0; - * Defines the operation type of the AES Accelerator operating under the - * Typical AES working mode. - * & - * 0x0(AES_EN_128): AES-EN-128 # - * 0x1(AES_EN_192): AES-EN-192 # - * 0x2(AES_EN_256): AES-EN-256 # - * 0x4(AES_DE_128): AES-DE-128 # - * 0x5(AES_DE_192): AES-DE-192 # - * 0x6(AES_DE_256): AES-DE-256 - * & - */ - -#define AES_MODE 0x00000007 -#define AES_MODE_M (AES_MODE_V << AES_MODE_S) -#define AES_MODE_V 0x00000007 -#define AES_MODE_S 0 - -/* AES_ENDIAN_REG register - * Endian configuration register - */ - -#define AES_ENDIAN_REG (DR_REG_AES_BASE + 0x44) - -/* AES_ENDIAN : R/W; bitpos: [5:0]; default: 0; - * Defines the endianness of input and output texts. - * & - * [1:0] key endian # - * [3:2] text_in endian or in_stream endian # - * [5:4] text_out endian or out_stream endian # - * & - */ - -#define AES_ENDIAN 0x0000003F -#define AES_ENDIAN_M (AES_ENDIAN_V << AES_ENDIAN_S) -#define AES_ENDIAN_V 0x0000003F -#define AES_ENDIAN_S 0 - -/* AES_TRIGGER_REG register - * Operation start controlling register - */ - -#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48) - -/* AES_TRIGGER : WO; bitpos: [0]; default: 0; - * Set this bit to 1 to start AES operation. - */ - -#define AES_TRIGGER (BIT(0)) -#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S) -#define AES_TRIGGER_V 0x00000001 -#define AES_TRIGGER_S 0 - -/* AES_STATE_REG register - * Operation status register - */ - -#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c) - -/* AES_STATE : RO; bitpos: [1:0]; default: 0; - * Stores the working status of the AES Accelerator. For details, see Table - * 3 for Typical AES working mode and Table 9 for DMA AES working mode. - * For typical AES; 0 = idle; 1 = busy. - * For DMA-AES; 0 = idle; 1 = busy; 2 = calculation_done. - */ - -#define AES_STATE 0x00000003 -#define AES_STATE_M (AES_STATE_V << AES_STATE_S) -#define AES_STATE_V 0x00000003 -#define AES_STATE_S 0 - -/* AES_IV_0_REG register - * initialization vector - */ - -#define AES_IV_0_REG (DR_REG_AES_BASE + 0x50) - -/* AES_IV_0 : R/W; bitpos: [31:0]; default: 0; - * This register stores the 0th 32-bit piece of 128-bit initialization vector - */ - -#define AES_IV_0 0xFFFFFFFF -#define AES_IV_0_M (AES_IV_0_V << AES_IV_0_S) -#define AES_IV_0_V 0xFFFFFFFF -#define AES_IV_0_S 0 - -/* AES_IV_1_REG register - * initialization vector - */ - -#define AES_IV_1_REG (DR_REG_AES_BASE + 0x54) - -/* AES_IV_1 : R/W; bitpos: [31:0]; default: 0; - * This register stores the 1th 32-bit piece of 128-bit initialization vector - */ - -#define AES_IV_1 0xFFFFFFFF -#define AES_IV_1_M (AES_IV_1_V << AES_IV_1_S) -#define AES_IV_1_V 0xFFFFFFFF -#define AES_IV_1_S 0 - -/* AES_IV_2_REG register - * initialization vector - */ - -#define AES_IV_2_REG (DR_REG_AES_BASE + 0x58) - -/* AES_IV_2 : R/W; bitpos: [31:0]; default: 0; - * This register stores the 2th 32-bit piece of 128-bit initialization vector - */ - -#define AES_IV_2 0xFFFFFFFF -#define AES_IV_2_M (AES_IV_2_V << AES_IV_2_S) -#define AES_IV_2_V 0xFFFFFFFF -#define AES_IV_2_S 0 - -/* AES_IV_3_REG register - * initialization vector - */ - -#define AES_IV_3_REG (DR_REG_AES_BASE + 0x5c) - -/* AES_IV_3 : R/W; bitpos: [31:0]; default: 0; - * This register stores the 3th 32-bit piece of 128-bit initialization vector - */ - -#define AES_IV_3 0xFFFFFFFF -#define AES_IV_3_M (AES_IV_3_V << AES_IV_3_S) -#define AES_IV_3_V 0xFFFFFFFF -#define AES_IV_3_S 0 - -/* AES_H_0_REG register - * GCM hash subkey - */ - -#define AES_H_0_REG (DR_REG_AES_BASE + 0x60) - -/* AES_H_0 : RO; bitpos: [31:0]; default: 0; - * GCM hash subkey - */ - -#define AES_H_0 0xFFFFFFFF -#define AES_H_0_M (AES_H_0_V << AES_H_0_S) -#define AES_H_0_V 0xFFFFFFFF -#define AES_H_0_S 0 - -/* AES_H_1_REG register - * GCM hash subkey - */ - -#define AES_H_1_REG (DR_REG_AES_BASE + 0x64) - -/* AES_H_1 : RO; bitpos: [31:0]; default: 0; - * GCM hash subkey - */ - -#define AES_H_1 0xFFFFFFFF -#define AES_H_1_M (AES_H_1_V << AES_H_1_S) -#define AES_H_1_V 0xFFFFFFFF -#define AES_H_1_S 0 - -/* AES_H_2_REG register - * GCM hash subkey - */ - -#define AES_H_2_REG (DR_REG_AES_BASE + 0x68) - -/* AES_H_2 : RO; bitpos: [31:0]; default: 0; - * GCM hash subkey - */ - -#define AES_H_2 0xFFFFFFFF -#define AES_H_2_M (AES_H_2_V << AES_H_2_S) -#define AES_H_2_V 0xFFFFFFFF -#define AES_H_2_S 0 - -/* AES_H_3_REG register - * GCM hash subkey - */ - -#define AES_H_3_REG (DR_REG_AES_BASE + 0x6c) - -/* AES_H_3 : RO; bitpos: [31:0]; default: 0; - * GCM hash subkey - */ - -#define AES_H_3 0xFFFFFFFF -#define AES_H_3_M (AES_H_3_V << AES_H_3_S) -#define AES_H_3_V 0xFFFFFFFF -#define AES_H_3_S 0 - -/* AES_J0_0_REG register - * J0 - */ - -#define AES_J0_0_REG (DR_REG_AES_BASE + 0x70) - -/* AES_J0_0 : R/W; bitpos: [31:0]; default: 0; - * This register stores the 0th 32-bit piece of 128-bit J0 - */ - -#define AES_J0_0 0xFFFFFFFF -#define AES_J0_0_M (AES_J0_0_V << AES_J0_0_S) -#define AES_J0_0_V 0xFFFFFFFF -#define AES_J0_0_S 0 - -/* AES_J0_1_REG register - * J0 - */ - -#define AES_J0_1_REG (DR_REG_AES_BASE + 0x74) - -/* AES_J0_1 : R/W; bitpos: [31:0]; default: 0; - * This register stores the 1th 32-bit piece of 128-bit J0 - */ - -#define AES_J0_1 0xFFFFFFFF -#define AES_J0_1_M (AES_J0_1_V << AES_J0_1_S) -#define AES_J0_1_V 0xFFFFFFFF -#define AES_J0_1_S 0 - -/* AES_J0_2_REG register - * J0 - */ - -#define AES_J0_2_REG (DR_REG_AES_BASE + 0x78) - -/* AES_J0_2 : R/W; bitpos: [31:0]; default: 0; - * This register stores the 2th 32-bit piece of 128-bit J0 - */ - -#define AES_J0_2 0xFFFFFFFF -#define AES_J0_2_M (AES_J0_2_V << AES_J0_2_S) -#define AES_J0_2_V 0xFFFFFFFF -#define AES_J0_2_S 0 - -/* AES_J0_3_REG register - * J0 - */ - -#define AES_J0_3_REG (DR_REG_AES_BASE + 0x7c) - -/* AES_J0_3 : R/W; bitpos: [31:0]; default: 0; - * This register stores the 3th 32-bit piece of 128-bit J0 - */ - -#define AES_J0_3 0xFFFFFFFF -#define AES_J0_3_M (AES_J0_3_V << AES_J0_3_S) -#define AES_J0_3_V 0xFFFFFFFF -#define AES_J0_3_S 0 - -/* AES_T0_0_REG register - * T0 - */ - -#define AES_T0_0_REG (DR_REG_AES_BASE + 0x80) - -/* AES_T0_0 : RO; bitpos: [31:0]; default: 0; - * This register stores the 0th 32-bit piece of 128-bit T0 - */ - -#define AES_T0_0 0xFFFFFFFF -#define AES_T0_0_M (AES_T0_0_V << AES_T0_0_S) -#define AES_T0_0_V 0xFFFFFFFF -#define AES_T0_0_S 0 - -/* AES_T0_1_REG register - * T0 - */ - -#define AES_T0_1_REG (DR_REG_AES_BASE + 0x84) - -/* AES_T0_1 : RO; bitpos: [31:0]; default: 0; - * This register stores the 1th 32-bit piece of 128-bit T0 - */ - -#define AES_T0_1 0xFFFFFFFF -#define AES_T0_1_M (AES_T0_1_V << AES_T0_1_S) -#define AES_T0_1_V 0xFFFFFFFF -#define AES_T0_1_S 0 - -/* AES_T0_2_REG register - * T0 - */ - -#define AES_T0_2_REG (DR_REG_AES_BASE + 0x88) - -/* AES_T0_2 : RO; bitpos: [31:0]; default: 0; - * This register stores the 2th 32-bit piece of 128-bit T0 - */ - -#define AES_T0_2 0xFFFFFFFF -#define AES_T0_2_M (AES_T0_2_V << AES_T0_2_S) -#define AES_T0_2_V 0xFFFFFFFF -#define AES_T0_2_S 0 - -/* AES_T0_3_REG register - * T0 - */ - -#define AES_T0_3_REG (DR_REG_AES_BASE + 0x8c) - -/* AES_T0_3 : RO; bitpos: [31:0]; default: 0; - * This register stores the 3th 32-bit piece of 128-bit T0 - */ - -#define AES_T0_3 0xFFFFFFFF -#define AES_T0_3_M (AES_T0_3_V << AES_T0_3_S) -#define AES_T0_3_V 0xFFFFFFFF -#define AES_T0_3_S 0 - -/* AES_DMA_ENABLE_REG register - * DMA enable register - */ - -#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90) - -/* AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0; - * Defines the working mode of the AES Accelerator. For details, see Table 1. - * 1'h0: typical AES operation - * 1'h1: DMA-AES operation - */ - -#define AES_DMA_ENABLE (BIT(0)) -#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S) -#define AES_DMA_ENABLE_V 0x00000001 -#define AES_DMA_ENABLE_S 0 - -/* AES_BLOCK_MODE_REG register - * Block operation type register - */ - -#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94) - -/* AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0; - * Defines the operation type of the AES Accelerator operating under the - * DMA-AES working mode. For details, see Table 8. - * & - * 3'h0(BLOCK_MODE_ECB): ECB # - * 3'h1(BLOCK_MODE_CBC): CBC # - * 3'h2(BLOCK_MODE_OFB): OFB # - * 3'h3(BLOCK_MODE_CTR): CTR # - * 3'h4(BLOCK_MODE_CFB8): CFB-8 # - * 3'h5(BLOCK_MODE_CFB128): CFB-128 # - * 3'h6(BLOCK_MODE_GCM): GCM - * & - */ - -#define AES_BLOCK_MODE 0x00000007 -#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S) -#define AES_BLOCK_MODE_V 0x00000007 -#define AES_BLOCK_MODE_S 0 - -/* AES_BLOCK_NUM_REG register - * Block number configuration register - */ - -#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98) - -/* AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; - * Stores the Block Number of plaintext or cipertext when the AES - * Accelerator operates under the DMA-AES working mode. For details, see - * Section 1.5.4. - */ - -#define AES_BLOCK_NUM 0xFFFFFFFF -#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S) -#define AES_BLOCK_NUM_V 0xFFFFFFFF -#define AES_BLOCK_NUM_S 0 - -/* AES_INC_SEL_REG register - * Standard incrementing function register - */ - -#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c) - -/* AES_INC_SEL : R/W; bitpos: [0]; default: 0; - * Defines the Standard Incrementing Function for CTR block operation. Set - * this bit to 0 or 1 to choose INC 32 or INC 128 . - */ - -#define AES_INC_SEL (BIT(0)) -#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S) -#define AES_INC_SEL_V 0x00000001 -#define AES_INC_SEL_S 0 - -/* AES_AAD_BLOCK_NUM_REG register - * AAD block number configuration register - */ - -#define AES_AAD_BLOCK_NUM_REG (DR_REG_AES_BASE + 0xa0) - -/* AES_AAD_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; - * Stores the ADD Block Number for the GCM operation. - */ - -#define AES_AAD_BLOCK_NUM 0xFFFFFFFF -#define AES_AAD_BLOCK_NUM_M (AES_AAD_BLOCK_NUM_V << AES_AAD_BLOCK_NUM_S) -#define AES_AAD_BLOCK_NUM_V 0xFFFFFFFF -#define AES_AAD_BLOCK_NUM_S 0 - -/* AES_REMAINDER_BIT_NUM_REG register - * Remainder bit number of plaintext/ciphertext - */ - -#define AES_REMAINDER_BIT_NUM_REG (DR_REG_AES_BASE + 0xa4) - -/* AES_REMAINDER_BIT_NUM : R/W; bitpos: [6:0]; default: 0; - * Stores the Remainder Bit Number for the GCM operation. - */ - -#define AES_REMAINDER_BIT_NUM 0x0000007F -#define AES_REMAINDER_BIT_NUM_M (AES_REMAINDER_BIT_NUM_V << AES_REMAINDER_BIT_NUM_S) -#define AES_REMAINDER_BIT_NUM_V 0x0000007F -#define AES_REMAINDER_BIT_NUM_S 0 - -/* AES_CONTINUE_REG register - * Operation continue controlling register - */ - -#define AES_CONTINUE_REG (DR_REG_AES_BASE + 0xa8) - -/* AES_CONTINUE : WO; bitpos: [0]; default: 0; - * Set this bit to 1 to continue AES operation. - */ - -#define AES_CONTINUE (BIT(0)) -#define AES_CONTINUE_M (AES_CONTINUE_V << AES_CONTINUE_S) -#define AES_CONTINUE_V 0x00000001 -#define AES_CONTINUE_S 0 - -/* AES_INT_CLR_REG register - * DMA-AES interrupt clear register - */ - -#define AES_INT_CLR_REG (DR_REG_AES_BASE + 0xac) - -/* AES_INT_CLR : WO; bitpos: [0]; default: 0; - * Set this bit to 1 to clear AES interrupt. - */ - -#define AES_INT_CLR (BIT(0)) -#define AES_INT_CLR_M (AES_INT_CLR_V << AES_INT_CLR_S) -#define AES_INT_CLR_V 0x00000001 -#define AES_INT_CLR_S 0 - -/* AES_INT_ENA_REG register - * DMA-AES interrupt enable register - */ - -#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0) - -/* AES_INT_ENA : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. - */ - -#define AES_INT_ENA (BIT(0)) -#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S) -#define AES_INT_ENA_V 0x00000001 -#define AES_INT_ENA_S 0 - -/* AES_DATE_REG register - * Version control register - */ - -#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4) - -/* AES_DATE : R/W; bitpos: [29:0]; default: 538510612; - * Version control register - */ - -#define AES_DATE 0x3FFFFFFF -#define AES_DATE_M (AES_DATE_V << AES_DATE_S) -#define AES_DATE_V 0x3FFFFFFF -#define AES_DATE_S 0 - -/* AES_DMA_EXIT_REG register - * Operation exit controlling register - */ - -#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8) - -/* AES_DMA_EXIT : WO; bitpos: [0]; default: 0; - * Set this bit to 1 to exit AES operation. This register is only effective - * for DMA-AES operation. - */ - -#define AES_DMA_EXIT (BIT(0)) -#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S) -#define AES_DMA_EXIT_V 0x00000001 -#define AES_DMA_EXIT_S 0 - -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_AES_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_dma.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_dma.h deleted file mode 100644 index 78b5746d34f42..0000000000000 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_dma.h +++ /dev/null @@ -1,3898 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_dma.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_DMA_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_DMA_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32c3_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* DMA_INT_RAW_CH0_REG register - * DMA_INT_RAW_CH0_REG. - */ - -#define DMA_INT_RAW_CH0_REG (DR_REG_GDMA_BASE + 0x0) - -/* DMA_OUTFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Tx - * channel 0 is underflow. - */ - -#define DMA_OUTFIFO_UDF_CH0_INT_RAW (BIT(12)) -#define DMA_OUTFIFO_UDF_CH0_INT_RAW_M (DMA_OUTFIFO_UDF_CH0_INT_RAW_V << DMA_OUTFIFO_UDF_CH0_INT_RAW_S) -#define DMA_OUTFIFO_UDF_CH0_INT_RAW_V 0x00000001 -#define DMA_OUTFIFO_UDF_CH0_INT_RAW_S 12 - -/* DMA_OUTFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Tx - * channel 0 is overflow. - */ - -#define DMA_OUTFIFO_OVF_CH0_INT_RAW (BIT(11)) -#define DMA_OUTFIFO_OVF_CH0_INT_RAW_M (DMA_OUTFIFO_OVF_CH0_INT_RAW_V << DMA_OUTFIFO_OVF_CH0_INT_RAW_S) -#define DMA_OUTFIFO_OVF_CH0_INT_RAW_V 0x00000001 -#define DMA_OUTFIFO_OVF_CH0_INT_RAW_S 11 - -/* DMA_INFIFO_UDF_CH0_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Rx - * channel 0 is underflow. - */ - -#define DMA_INFIFO_UDF_CH0_INT_RAW (BIT(10)) -#define DMA_INFIFO_UDF_CH0_INT_RAW_M (DMA_INFIFO_UDF_CH0_INT_RAW_V << DMA_INFIFO_UDF_CH0_INT_RAW_S) -#define DMA_INFIFO_UDF_CH0_INT_RAW_V 0x00000001 -#define DMA_INFIFO_UDF_CH0_INT_RAW_S 10 - -/* DMA_INFIFO_OVF_CH0_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Rx - * channel 0 is overflow. - */ - -#define DMA_INFIFO_OVF_CH0_INT_RAW (BIT(9)) -#define DMA_INFIFO_OVF_CH0_INT_RAW_M (DMA_INFIFO_OVF_CH0_INT_RAW_V << DMA_INFIFO_OVF_CH0_INT_RAW_S) -#define DMA_INFIFO_OVF_CH0_INT_RAW_V 0x00000001 -#define DMA_INFIFO_OVF_CH0_INT_RAW_S 9 - -/* DMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a - * outlink (includes one link descriptor or few link descriptors) is - * transmitted out for Tx channel 0. - */ - -#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V << DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S) -#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x00000001 -#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 8 - -/* DMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when Rx buffer pointed by - * inlink is full and receiving data is not completed, but there is no more - * inlink for Rx channel 0. - */ - -#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V << DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S) -#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x00000001 -#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 7 - -/* DMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink - * descriptor error, including owner error, the second and third word error - * of outlink descriptor for Tx channel 0. - */ - -#define DMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_M (DMA_OUT_DSCR_ERR_CH0_INT_RAW_V << DMA_OUT_DSCR_ERR_CH0_INT_RAW_S) -#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x00000001 -#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_S 6 - -/* DMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink - * descriptor error, including owner error, the second and third word error - * of inlink descriptor for Rx channel 0. - */ - -#define DMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(5)) -#define DMA_IN_DSCR_ERR_CH0_INT_RAW_M (DMA_IN_DSCR_ERR_CH0_INT_RAW_V << DMA_IN_DSCR_ERR_CH0_INT_RAW_S) -#define DMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x00000001 -#define DMA_IN_DSCR_ERR_CH0_INT_RAW_S 5 - -/* DMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by - * one outlink descriptor has been read from memory for Tx channel 0. - */ - -#define DMA_OUT_EOF_CH0_INT_RAW (BIT(4)) -#define DMA_OUT_EOF_CH0_INT_RAW_M (DMA_OUT_EOF_CH0_INT_RAW_V << DMA_OUT_EOF_CH0_INT_RAW_S) -#define DMA_OUT_EOF_CH0_INT_RAW_V 0x00000001 -#define DMA_OUT_EOF_CH0_INT_RAW_S 4 - -/* DMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by - * one outlink descriptor has been transmitted to peripherals for Tx channel - * 0. - */ - -#define DMA_OUT_DONE_CH0_INT_RAW (BIT(3)) -#define DMA_OUT_DONE_CH0_INT_RAW_M (DMA_OUT_DONE_CH0_INT_RAW_V << DMA_OUT_DONE_CH0_INT_RAW_S) -#define DMA_OUT_DONE_CH0_INT_RAW_V 0x00000001 -#define DMA_OUT_DONE_CH0_INT_RAW_S 3 - -/* DMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when data error is detected - * only in the case that the peripheral is UHCI0 for Rx channel 0. For other - * peripherals, this raw interrupt is reserved. - */ - -#define DMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) -#define DMA_IN_ERR_EOF_CH0_INT_RAW_M (DMA_IN_ERR_EOF_CH0_INT_RAW_V << DMA_IN_ERR_EOF_CH0_INT_RAW_S) -#define DMA_IN_ERR_EOF_CH0_INT_RAW_V 0x00000001 -#define DMA_IN_ERR_EOF_CH0_INT_RAW_S 2 - -/* DMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by - * one inlink descriptor has been received for Rx channel 0. For UHCI0, the - * raw interrupt bit turns to high level when the last data pointed by one - * inlink descriptor has been received and no data error is detected for Rx - * channel 0. - */ - -#define DMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) -#define DMA_IN_SUC_EOF_CH0_INT_RAW_M (DMA_IN_SUC_EOF_CH0_INT_RAW_V << DMA_IN_SUC_EOF_CH0_INT_RAW_S) -#define DMA_IN_SUC_EOF_CH0_INT_RAW_V 0x00000001 -#define DMA_IN_SUC_EOF_CH0_INT_RAW_S 1 - -/* DMA_IN_DONE_CH0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by - * one inlink descriptor has been received for Rx channel 0. - */ - -#define DMA_IN_DONE_CH0_INT_RAW (BIT(0)) -#define DMA_IN_DONE_CH0_INT_RAW_M (DMA_IN_DONE_CH0_INT_RAW_V << DMA_IN_DONE_CH0_INT_RAW_S) -#define DMA_IN_DONE_CH0_INT_RAW_V 0x00000001 -#define DMA_IN_DONE_CH0_INT_RAW_S 0 - -/* DMA_INT_ST_CH0_REG register - * DMA_INT_ST_CH0_REG. - */ - -#define DMA_INT_ST_CH0_REG (DR_REG_GDMA_BASE + 0x4) - -/* DMA_OUTFIFO_UDF_CH0_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - -#define DMA_OUTFIFO_UDF_CH0_INT_ST (BIT(12)) -#define DMA_OUTFIFO_UDF_CH0_INT_ST_M (DMA_OUTFIFO_UDF_CH0_INT_ST_V << DMA_OUTFIFO_UDF_CH0_INT_ST_S) -#define DMA_OUTFIFO_UDF_CH0_INT_ST_V 0x00000001 -#define DMA_OUTFIFO_UDF_CH0_INT_ST_S 12 - -/* DMA_OUTFIFO_OVF_CH0_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - -#define DMA_OUTFIFO_OVF_CH0_INT_ST (BIT(11)) -#define DMA_OUTFIFO_OVF_CH0_INT_ST_M (DMA_OUTFIFO_OVF_CH0_INT_ST_V << DMA_OUTFIFO_OVF_CH0_INT_ST_S) -#define DMA_OUTFIFO_OVF_CH0_INT_ST_V 0x00000001 -#define DMA_OUTFIFO_OVF_CH0_INT_ST_S 11 - -/* DMA_INFIFO_UDF_CH0_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - -#define DMA_INFIFO_UDF_CH0_INT_ST (BIT(10)) -#define DMA_INFIFO_UDF_CH0_INT_ST_M (DMA_INFIFO_UDF_CH0_INT_ST_V << DMA_INFIFO_UDF_CH0_INT_ST_S) -#define DMA_INFIFO_UDF_CH0_INT_ST_V 0x00000001 -#define DMA_INFIFO_UDF_CH0_INT_ST_S 10 - -/* DMA_INFIFO_OVF_CH0_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - -#define DMA_INFIFO_OVF_CH0_INT_ST (BIT(9)) -#define DMA_INFIFO_OVF_CH0_INT_ST_M (DMA_INFIFO_OVF_CH0_INT_ST_V << DMA_INFIFO_OVF_CH0_INT_ST_S) -#define DMA_INFIFO_OVF_CH0_INT_ST_V 0x00000001 -#define DMA_INFIFO_OVF_CH0_INT_ST_S 9 - -/* DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - -#define DMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_M (DMA_OUT_TOTAL_EOF_CH0_INT_ST_V << DMA_OUT_TOTAL_EOF_CH0_INT_ST_S) -#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x00000001 -#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_S 8 - -/* DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - -#define DMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_M (DMA_IN_DSCR_EMPTY_CH0_INT_ST_V << DMA_IN_DSCR_EMPTY_CH0_INT_ST_S) -#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x00000001 -#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_S 7 - -/* DMA_OUT_DSCR_ERR_CH0_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - -#define DMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH0_INT_ST_M (DMA_OUT_DSCR_ERR_CH0_INT_ST_V << DMA_OUT_DSCR_ERR_CH0_INT_ST_S) -#define DMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x00000001 -#define DMA_OUT_DSCR_ERR_CH0_INT_ST_S 6 - -/* DMA_IN_DSCR_ERR_CH0_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - -#define DMA_IN_DSCR_ERR_CH0_INT_ST (BIT(5)) -#define DMA_IN_DSCR_ERR_CH0_INT_ST_M (DMA_IN_DSCR_ERR_CH0_INT_ST_V << DMA_IN_DSCR_ERR_CH0_INT_ST_S) -#define DMA_IN_DSCR_ERR_CH0_INT_ST_V 0x00000001 -#define DMA_IN_DSCR_ERR_CH0_INT_ST_S 5 - -/* DMA_OUT_EOF_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ - -#define DMA_OUT_EOF_CH0_INT_ST (BIT(4)) -#define DMA_OUT_EOF_CH0_INT_ST_M (DMA_OUT_EOF_CH0_INT_ST_V << DMA_OUT_EOF_CH0_INT_ST_S) -#define DMA_OUT_EOF_CH0_INT_ST_V 0x00000001 -#define DMA_OUT_EOF_CH0_INT_ST_S 4 - -/* DMA_OUT_DONE_CH0_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ - -#define DMA_OUT_DONE_CH0_INT_ST (BIT(3)) -#define DMA_OUT_DONE_CH0_INT_ST_M (DMA_OUT_DONE_CH0_INT_ST_V << DMA_OUT_DONE_CH0_INT_ST_S) -#define DMA_OUT_DONE_CH0_INT_ST_V 0x00000001 -#define DMA_OUT_DONE_CH0_INT_ST_S 3 - -/* DMA_IN_ERR_EOF_CH0_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ - -#define DMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) -#define DMA_IN_ERR_EOF_CH0_INT_ST_M (DMA_IN_ERR_EOF_CH0_INT_ST_V << DMA_IN_ERR_EOF_CH0_INT_ST_S) -#define DMA_IN_ERR_EOF_CH0_INT_ST_V 0x00000001 -#define DMA_IN_ERR_EOF_CH0_INT_ST_S 2 - -/* DMA_IN_SUC_EOF_CH0_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ - -#define DMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) -#define DMA_IN_SUC_EOF_CH0_INT_ST_M (DMA_IN_SUC_EOF_CH0_INT_ST_V << DMA_IN_SUC_EOF_CH0_INT_ST_S) -#define DMA_IN_SUC_EOF_CH0_INT_ST_V 0x00000001 -#define DMA_IN_SUC_EOF_CH0_INT_ST_S 1 - -/* DMA_IN_DONE_CH0_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ - -#define DMA_IN_DONE_CH0_INT_ST (BIT(0)) -#define DMA_IN_DONE_CH0_INT_ST_M (DMA_IN_DONE_CH0_INT_ST_V << DMA_IN_DONE_CH0_INT_ST_S) -#define DMA_IN_DONE_CH0_INT_ST_V 0x00000001 -#define DMA_IN_DONE_CH0_INT_ST_S 0 - -/* DMA_INT_ENA_CH0_REG register - * DMA_INT_ENA_CH0_REG. - */ - -#define DMA_INT_ENA_CH0_REG (DR_REG_GDMA_BASE + 0x8) - -/* DMA_OUTFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - -#define DMA_OUTFIFO_UDF_CH0_INT_ENA (BIT(12)) -#define DMA_OUTFIFO_UDF_CH0_INT_ENA_M (DMA_OUTFIFO_UDF_CH0_INT_ENA_V << DMA_OUTFIFO_UDF_CH0_INT_ENA_S) -#define DMA_OUTFIFO_UDF_CH0_INT_ENA_V 0x00000001 -#define DMA_OUTFIFO_UDF_CH0_INT_ENA_S 12 - -/* DMA_OUTFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - -#define DMA_OUTFIFO_OVF_CH0_INT_ENA (BIT(11)) -#define DMA_OUTFIFO_OVF_CH0_INT_ENA_M (DMA_OUTFIFO_OVF_CH0_INT_ENA_V << DMA_OUTFIFO_OVF_CH0_INT_ENA_S) -#define DMA_OUTFIFO_OVF_CH0_INT_ENA_V 0x00000001 -#define DMA_OUTFIFO_OVF_CH0_INT_ENA_S 11 - -/* DMA_INFIFO_UDF_CH0_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - -#define DMA_INFIFO_UDF_CH0_INT_ENA (BIT(10)) -#define DMA_INFIFO_UDF_CH0_INT_ENA_M (DMA_INFIFO_UDF_CH0_INT_ENA_V << DMA_INFIFO_UDF_CH0_INT_ENA_S) -#define DMA_INFIFO_UDF_CH0_INT_ENA_V 0x00000001 -#define DMA_INFIFO_UDF_CH0_INT_ENA_S 10 - -/* DMA_INFIFO_OVF_CH0_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - -#define DMA_INFIFO_OVF_CH0_INT_ENA (BIT(9)) -#define DMA_INFIFO_OVF_CH0_INT_ENA_M (DMA_INFIFO_OVF_CH0_INT_ENA_V << DMA_INFIFO_OVF_CH0_INT_ENA_S) -#define DMA_INFIFO_OVF_CH0_INT_ENA_V 0x00000001 -#define DMA_INFIFO_OVF_CH0_INT_ENA_S 9 - -/* DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - -#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V << DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S) -#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x00000001 -#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 8 - -/* DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - -#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V << DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S) -#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x00000001 -#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 7 - -/* DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - -#define DMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_M (DMA_OUT_DSCR_ERR_CH0_INT_ENA_V << DMA_OUT_DSCR_ERR_CH0_INT_ENA_S) -#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x00000001 -#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_S 6 - -/* DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - -#define DMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(5)) -#define DMA_IN_DSCR_ERR_CH0_INT_ENA_M (DMA_IN_DSCR_ERR_CH0_INT_ENA_V << DMA_IN_DSCR_ERR_CH0_INT_ENA_S) -#define DMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x00000001 -#define DMA_IN_DSCR_ERR_CH0_INT_ENA_S 5 - -/* DMA_OUT_EOF_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ - -#define DMA_OUT_EOF_CH0_INT_ENA (BIT(4)) -#define DMA_OUT_EOF_CH0_INT_ENA_M (DMA_OUT_EOF_CH0_INT_ENA_V << DMA_OUT_EOF_CH0_INT_ENA_S) -#define DMA_OUT_EOF_CH0_INT_ENA_V 0x00000001 -#define DMA_OUT_EOF_CH0_INT_ENA_S 4 - -/* DMA_OUT_DONE_CH0_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ - -#define DMA_OUT_DONE_CH0_INT_ENA (BIT(3)) -#define DMA_OUT_DONE_CH0_INT_ENA_M (DMA_OUT_DONE_CH0_INT_ENA_V << DMA_OUT_DONE_CH0_INT_ENA_S) -#define DMA_OUT_DONE_CH0_INT_ENA_V 0x00000001 -#define DMA_OUT_DONE_CH0_INT_ENA_S 3 - -/* DMA_IN_ERR_EOF_CH0_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ - -#define DMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) -#define DMA_IN_ERR_EOF_CH0_INT_ENA_M (DMA_IN_ERR_EOF_CH0_INT_ENA_V << DMA_IN_ERR_EOF_CH0_INT_ENA_S) -#define DMA_IN_ERR_EOF_CH0_INT_ENA_V 0x00000001 -#define DMA_IN_ERR_EOF_CH0_INT_ENA_S 2 - -/* DMA_IN_SUC_EOF_CH0_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ - -#define DMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) -#define DMA_IN_SUC_EOF_CH0_INT_ENA_M (DMA_IN_SUC_EOF_CH0_INT_ENA_V << DMA_IN_SUC_EOF_CH0_INT_ENA_S) -#define DMA_IN_SUC_EOF_CH0_INT_ENA_V 0x00000001 -#define DMA_IN_SUC_EOF_CH0_INT_ENA_S 1 - -/* DMA_IN_DONE_CH0_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ - -#define DMA_IN_DONE_CH0_INT_ENA (BIT(0)) -#define DMA_IN_DONE_CH0_INT_ENA_M (DMA_IN_DONE_CH0_INT_ENA_V << DMA_IN_DONE_CH0_INT_ENA_S) -#define DMA_IN_DONE_CH0_INT_ENA_V 0x00000001 -#define DMA_IN_DONE_CH0_INT_ENA_S 0 - -/* DMA_INT_CLR_CH0_REG register - * DMA_INT_CLR_CH0_REG. - */ - -#define DMA_INT_CLR_CH0_REG (DR_REG_GDMA_BASE + 0xc) - -/* DMA_OUTFIFO_UDF_CH0_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - -#define DMA_OUTFIFO_UDF_CH0_INT_CLR (BIT(12)) -#define DMA_OUTFIFO_UDF_CH0_INT_CLR_M (DMA_OUTFIFO_UDF_CH0_INT_CLR_V << DMA_OUTFIFO_UDF_CH0_INT_CLR_S) -#define DMA_OUTFIFO_UDF_CH0_INT_CLR_V 0x00000001 -#define DMA_OUTFIFO_UDF_CH0_INT_CLR_S 12 - -/* DMA_OUTFIFO_OVF_CH0_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - -#define DMA_OUTFIFO_OVF_CH0_INT_CLR (BIT(11)) -#define DMA_OUTFIFO_OVF_CH0_INT_CLR_M (DMA_OUTFIFO_OVF_CH0_INT_CLR_V << DMA_OUTFIFO_OVF_CH0_INT_CLR_S) -#define DMA_OUTFIFO_OVF_CH0_INT_CLR_V 0x00000001 -#define DMA_OUTFIFO_OVF_CH0_INT_CLR_S 11 - -/* DMA_INFIFO_UDF_CH0_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ - -#define DMA_INFIFO_UDF_CH0_INT_CLR (BIT(10)) -#define DMA_INFIFO_UDF_CH0_INT_CLR_M (DMA_INFIFO_UDF_CH0_INT_CLR_V << DMA_INFIFO_UDF_CH0_INT_CLR_S) -#define DMA_INFIFO_UDF_CH0_INT_CLR_V 0x00000001 -#define DMA_INFIFO_UDF_CH0_INT_CLR_S 10 - -/* DMA_INFIFO_OVF_CH0_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ - -#define DMA_INFIFO_OVF_CH0_INT_CLR (BIT(9)) -#define DMA_INFIFO_OVF_CH0_INT_CLR_M (DMA_INFIFO_OVF_CH0_INT_CLR_V << DMA_INFIFO_OVF_CH0_INT_CLR_S) -#define DMA_INFIFO_OVF_CH0_INT_CLR_V 0x00000001 -#define DMA_INFIFO_OVF_CH0_INT_CLR_S 9 - -/* DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ - -#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V << DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S) -#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x00000001 -#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 8 - -/* DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ - -#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V << DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S) -#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x00000001 -#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 7 - -/* DMA_OUT_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ - -#define DMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_M (DMA_OUT_DSCR_ERR_CH0_INT_CLR_V << DMA_OUT_DSCR_ERR_CH0_INT_CLR_S) -#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x00000001 -#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_S 6 - -/* DMA_IN_DSCR_ERR_CH0_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. - */ - -#define DMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(5)) -#define DMA_IN_DSCR_ERR_CH0_INT_CLR_M (DMA_IN_DSCR_ERR_CH0_INT_CLR_V << DMA_IN_DSCR_ERR_CH0_INT_CLR_S) -#define DMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x00000001 -#define DMA_IN_DSCR_ERR_CH0_INT_CLR_S 5 - -/* DMA_OUT_EOF_CH0_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ - -#define DMA_OUT_EOF_CH0_INT_CLR (BIT(4)) -#define DMA_OUT_EOF_CH0_INT_CLR_M (DMA_OUT_EOF_CH0_INT_CLR_V << DMA_OUT_EOF_CH0_INT_CLR_S) -#define DMA_OUT_EOF_CH0_INT_CLR_V 0x00000001 -#define DMA_OUT_EOF_CH0_INT_CLR_S 4 - -/* DMA_OUT_DONE_CH0_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ - -#define DMA_OUT_DONE_CH0_INT_CLR (BIT(3)) -#define DMA_OUT_DONE_CH0_INT_CLR_M (DMA_OUT_DONE_CH0_INT_CLR_V << DMA_OUT_DONE_CH0_INT_CLR_S) -#define DMA_OUT_DONE_CH0_INT_CLR_V 0x00000001 -#define DMA_OUT_DONE_CH0_INT_CLR_S 3 - -/* DMA_IN_ERR_EOF_CH0_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ - -#define DMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) -#define DMA_IN_ERR_EOF_CH0_INT_CLR_M (DMA_IN_ERR_EOF_CH0_INT_CLR_V << DMA_IN_ERR_EOF_CH0_INT_CLR_S) -#define DMA_IN_ERR_EOF_CH0_INT_CLR_V 0x00000001 -#define DMA_IN_ERR_EOF_CH0_INT_CLR_S 2 - -/* DMA_IN_SUC_EOF_CH0_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ - -#define DMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) -#define DMA_IN_SUC_EOF_CH0_INT_CLR_M (DMA_IN_SUC_EOF_CH0_INT_CLR_V << DMA_IN_SUC_EOF_CH0_INT_CLR_S) -#define DMA_IN_SUC_EOF_CH0_INT_CLR_V 0x00000001 -#define DMA_IN_SUC_EOF_CH0_INT_CLR_S 1 - -/* DMA_IN_DONE_CH0_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ - -#define DMA_IN_DONE_CH0_INT_CLR (BIT(0)) -#define DMA_IN_DONE_CH0_INT_CLR_M (DMA_IN_DONE_CH0_INT_CLR_V << DMA_IN_DONE_CH0_INT_CLR_S) -#define DMA_IN_DONE_CH0_INT_CLR_V 0x00000001 -#define DMA_IN_DONE_CH0_INT_CLR_S 0 - -/* DMA_INT_RAW_CH1_REG register - * DMA_INT_RAW_CH1_REG. - */ - -#define DMA_INT_RAW_CH1_REG (DR_REG_GDMA_BASE + 0x10) - -/* DMA_OUTFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Tx - * channel 1 is underflow. - */ - -#define DMA_OUTFIFO_UDF_CH1_INT_RAW (BIT(12)) -#define DMA_OUTFIFO_UDF_CH1_INT_RAW_M (DMA_OUTFIFO_UDF_CH1_INT_RAW_V << DMA_OUTFIFO_UDF_CH1_INT_RAW_S) -#define DMA_OUTFIFO_UDF_CH1_INT_RAW_V 0x00000001 -#define DMA_OUTFIFO_UDF_CH1_INT_RAW_S 12 - -/* DMA_OUTFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Tx - * channel 1 is overflow. - */ - -#define DMA_OUTFIFO_OVF_CH1_INT_RAW (BIT(11)) -#define DMA_OUTFIFO_OVF_CH1_INT_RAW_M (DMA_OUTFIFO_OVF_CH1_INT_RAW_V << DMA_OUTFIFO_OVF_CH1_INT_RAW_S) -#define DMA_OUTFIFO_OVF_CH1_INT_RAW_V 0x00000001 -#define DMA_OUTFIFO_OVF_CH1_INT_RAW_S 11 - -/* DMA_INFIFO_UDF_CH1_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Rx - * channel 1 is underflow. - */ - -#define DMA_INFIFO_UDF_CH1_INT_RAW (BIT(10)) -#define DMA_INFIFO_UDF_CH1_INT_RAW_M (DMA_INFIFO_UDF_CH1_INT_RAW_V << DMA_INFIFO_UDF_CH1_INT_RAW_S) -#define DMA_INFIFO_UDF_CH1_INT_RAW_V 0x00000001 -#define DMA_INFIFO_UDF_CH1_INT_RAW_S 10 - -/* DMA_INFIFO_OVF_CH1_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Rx - * channel 1 is overflow. - */ - -#define DMA_INFIFO_OVF_CH1_INT_RAW (BIT(9)) -#define DMA_INFIFO_OVF_CH1_INT_RAW_M (DMA_INFIFO_OVF_CH1_INT_RAW_V << DMA_INFIFO_OVF_CH1_INT_RAW_S) -#define DMA_INFIFO_OVF_CH1_INT_RAW_V 0x00000001 -#define DMA_INFIFO_OVF_CH1_INT_RAW_S 9 - -/* DMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a - * outlink (includes one link descriptor or few link descriptors) is - * transmitted out for Tx channel 1. - */ - -#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V << DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S) -#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x00000001 -#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 8 - -/* DMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when Rx buffer pointed by - * inlink is full and receiving data is not completed, but there is no more - * inlink for Rx channel 1. - */ - -#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V << DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S) -#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x00000001 -#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 7 - -/* DMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink - * descriptor error, including owner error, the second and third word error - * of outlink descriptor for Tx channel 1. - */ - -#define DMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_M (DMA_OUT_DSCR_ERR_CH1_INT_RAW_V << DMA_OUT_DSCR_ERR_CH1_INT_RAW_S) -#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x00000001 -#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_S 6 - -/* DMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink - * descriptor error, including owner error, the second and third word error - * of inlink descriptor for Rx channel 1. - */ - -#define DMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(5)) -#define DMA_IN_DSCR_ERR_CH1_INT_RAW_M (DMA_IN_DSCR_ERR_CH1_INT_RAW_V << DMA_IN_DSCR_ERR_CH1_INT_RAW_S) -#define DMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x00000001 -#define DMA_IN_DSCR_ERR_CH1_INT_RAW_S 5 - -/* DMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by - * one outlink descriptor has been read from memory for Tx channel 1. - */ - -#define DMA_OUT_EOF_CH1_INT_RAW (BIT(4)) -#define DMA_OUT_EOF_CH1_INT_RAW_M (DMA_OUT_EOF_CH1_INT_RAW_V << DMA_OUT_EOF_CH1_INT_RAW_S) -#define DMA_OUT_EOF_CH1_INT_RAW_V 0x00000001 -#define DMA_OUT_EOF_CH1_INT_RAW_S 4 - -/* DMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by - * one outlink descriptor has been transmitted to peripherals for Tx channel - * 1. - */ - -#define DMA_OUT_DONE_CH1_INT_RAW (BIT(3)) -#define DMA_OUT_DONE_CH1_INT_RAW_M (DMA_OUT_DONE_CH1_INT_RAW_V << DMA_OUT_DONE_CH1_INT_RAW_S) -#define DMA_OUT_DONE_CH1_INT_RAW_V 0x00000001 -#define DMA_OUT_DONE_CH1_INT_RAW_S 3 - -/* DMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when data error is detected - * only in the case that the peripheral is UHCI0 for Rx channel 1. For other - * peripherals, this raw interrupt is reserved. - */ - -#define DMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) -#define DMA_IN_ERR_EOF_CH1_INT_RAW_M (DMA_IN_ERR_EOF_CH1_INT_RAW_V << DMA_IN_ERR_EOF_CH1_INT_RAW_S) -#define DMA_IN_ERR_EOF_CH1_INT_RAW_V 0x00000001 -#define DMA_IN_ERR_EOF_CH1_INT_RAW_S 2 - -/* DMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by - * one inlink descriptor has been received for Rx channel 1. For UHCI0, the - * raw interrupt bit turns to high level when the last data pointed by one - * inlink descriptor has been received and no data error is detected for Rx - * channel 1. - */ - -#define DMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) -#define DMA_IN_SUC_EOF_CH1_INT_RAW_M (DMA_IN_SUC_EOF_CH1_INT_RAW_V << DMA_IN_SUC_EOF_CH1_INT_RAW_S) -#define DMA_IN_SUC_EOF_CH1_INT_RAW_V 0x00000001 -#define DMA_IN_SUC_EOF_CH1_INT_RAW_S 1 - -/* DMA_IN_DONE_CH1_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by - * one inlink descriptor has been received for Rx channel 1. - */ - -#define DMA_IN_DONE_CH1_INT_RAW (BIT(0)) -#define DMA_IN_DONE_CH1_INT_RAW_M (DMA_IN_DONE_CH1_INT_RAW_V << DMA_IN_DONE_CH1_INT_RAW_S) -#define DMA_IN_DONE_CH1_INT_RAW_V 0x00000001 -#define DMA_IN_DONE_CH1_INT_RAW_S 0 - -/* DMA_INT_ST_CH1_REG register - * DMA_INT_ST_CH1_REG. - */ - -#define DMA_INT_ST_CH1_REG (DR_REG_GDMA_BASE + 0x14) - -/* DMA_OUTFIFO_UDF_CH1_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - -#define DMA_OUTFIFO_UDF_CH1_INT_ST (BIT(12)) -#define DMA_OUTFIFO_UDF_CH1_INT_ST_M (DMA_OUTFIFO_UDF_CH1_INT_ST_V << DMA_OUTFIFO_UDF_CH1_INT_ST_S) -#define DMA_OUTFIFO_UDF_CH1_INT_ST_V 0x00000001 -#define DMA_OUTFIFO_UDF_CH1_INT_ST_S 12 - -/* DMA_OUTFIFO_OVF_CH1_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - -#define DMA_OUTFIFO_OVF_CH1_INT_ST (BIT(11)) -#define DMA_OUTFIFO_OVF_CH1_INT_ST_M (DMA_OUTFIFO_OVF_CH1_INT_ST_V << DMA_OUTFIFO_OVF_CH1_INT_ST_S) -#define DMA_OUTFIFO_OVF_CH1_INT_ST_V 0x00000001 -#define DMA_OUTFIFO_OVF_CH1_INT_ST_S 11 - -/* DMA_INFIFO_UDF_CH1_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - -#define DMA_INFIFO_UDF_CH1_INT_ST (BIT(10)) -#define DMA_INFIFO_UDF_CH1_INT_ST_M (DMA_INFIFO_UDF_CH1_INT_ST_V << DMA_INFIFO_UDF_CH1_INT_ST_S) -#define DMA_INFIFO_UDF_CH1_INT_ST_V 0x00000001 -#define DMA_INFIFO_UDF_CH1_INT_ST_S 10 - -/* DMA_INFIFO_OVF_CH1_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - -#define DMA_INFIFO_OVF_CH1_INT_ST (BIT(9)) -#define DMA_INFIFO_OVF_CH1_INT_ST_M (DMA_INFIFO_OVF_CH1_INT_ST_V << DMA_INFIFO_OVF_CH1_INT_ST_S) -#define DMA_INFIFO_OVF_CH1_INT_ST_V 0x00000001 -#define DMA_INFIFO_OVF_CH1_INT_ST_S 9 - -/* DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - -#define DMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_M (DMA_OUT_TOTAL_EOF_CH1_INT_ST_V << DMA_OUT_TOTAL_EOF_CH1_INT_ST_S) -#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x00000001 -#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_S 8 - -/* DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - -#define DMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_M (DMA_IN_DSCR_EMPTY_CH1_INT_ST_V << DMA_IN_DSCR_EMPTY_CH1_INT_ST_S) -#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x00000001 -#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_S 7 - -/* DMA_OUT_DSCR_ERR_CH1_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - -#define DMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH1_INT_ST_M (DMA_OUT_DSCR_ERR_CH1_INT_ST_V << DMA_OUT_DSCR_ERR_CH1_INT_ST_S) -#define DMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x00000001 -#define DMA_OUT_DSCR_ERR_CH1_INT_ST_S 6 - -/* DMA_IN_DSCR_ERR_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - -#define DMA_IN_DSCR_ERR_CH1_INT_ST (BIT(5)) -#define DMA_IN_DSCR_ERR_CH1_INT_ST_M (DMA_IN_DSCR_ERR_CH1_INT_ST_V << DMA_IN_DSCR_ERR_CH1_INT_ST_S) -#define DMA_IN_DSCR_ERR_CH1_INT_ST_V 0x00000001 -#define DMA_IN_DSCR_ERR_CH1_INT_ST_S 5 - -/* DMA_OUT_EOF_CH1_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ - -#define DMA_OUT_EOF_CH1_INT_ST (BIT(4)) -#define DMA_OUT_EOF_CH1_INT_ST_M (DMA_OUT_EOF_CH1_INT_ST_V << DMA_OUT_EOF_CH1_INT_ST_S) -#define DMA_OUT_EOF_CH1_INT_ST_V 0x00000001 -#define DMA_OUT_EOF_CH1_INT_ST_S 4 - -/* DMA_OUT_DONE_CH1_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ - -#define DMA_OUT_DONE_CH1_INT_ST (BIT(3)) -#define DMA_OUT_DONE_CH1_INT_ST_M (DMA_OUT_DONE_CH1_INT_ST_V << DMA_OUT_DONE_CH1_INT_ST_S) -#define DMA_OUT_DONE_CH1_INT_ST_V 0x00000001 -#define DMA_OUT_DONE_CH1_INT_ST_S 3 - -/* DMA_IN_ERR_EOF_CH1_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ - -#define DMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) -#define DMA_IN_ERR_EOF_CH1_INT_ST_M (DMA_IN_ERR_EOF_CH1_INT_ST_V << DMA_IN_ERR_EOF_CH1_INT_ST_S) -#define DMA_IN_ERR_EOF_CH1_INT_ST_V 0x00000001 -#define DMA_IN_ERR_EOF_CH1_INT_ST_S 2 - -/* DMA_IN_SUC_EOF_CH1_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ - -#define DMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) -#define DMA_IN_SUC_EOF_CH1_INT_ST_M (DMA_IN_SUC_EOF_CH1_INT_ST_V << DMA_IN_SUC_EOF_CH1_INT_ST_S) -#define DMA_IN_SUC_EOF_CH1_INT_ST_V 0x00000001 -#define DMA_IN_SUC_EOF_CH1_INT_ST_S 1 - -/* DMA_IN_DONE_CH1_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ - -#define DMA_IN_DONE_CH1_INT_ST (BIT(0)) -#define DMA_IN_DONE_CH1_INT_ST_M (DMA_IN_DONE_CH1_INT_ST_V << DMA_IN_DONE_CH1_INT_ST_S) -#define DMA_IN_DONE_CH1_INT_ST_V 0x00000001 -#define DMA_IN_DONE_CH1_INT_ST_S 0 - -/* DMA_INT_ENA_CH1_REG register - * DMA_INT_ENA_CH1_REG. - */ - -#define DMA_INT_ENA_CH1_REG (DR_REG_GDMA_BASE + 0x18) - -/* DMA_OUTFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - -#define DMA_OUTFIFO_UDF_CH1_INT_ENA (BIT(12)) -#define DMA_OUTFIFO_UDF_CH1_INT_ENA_M (DMA_OUTFIFO_UDF_CH1_INT_ENA_V << DMA_OUTFIFO_UDF_CH1_INT_ENA_S) -#define DMA_OUTFIFO_UDF_CH1_INT_ENA_V 0x00000001 -#define DMA_OUTFIFO_UDF_CH1_INT_ENA_S 12 - -/* DMA_OUTFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - -#define DMA_OUTFIFO_OVF_CH1_INT_ENA (BIT(11)) -#define DMA_OUTFIFO_OVF_CH1_INT_ENA_M (DMA_OUTFIFO_OVF_CH1_INT_ENA_V << DMA_OUTFIFO_OVF_CH1_INT_ENA_S) -#define DMA_OUTFIFO_OVF_CH1_INT_ENA_V 0x00000001 -#define DMA_OUTFIFO_OVF_CH1_INT_ENA_S 11 - -/* DMA_INFIFO_UDF_CH1_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - -#define DMA_INFIFO_UDF_CH1_INT_ENA (BIT(10)) -#define DMA_INFIFO_UDF_CH1_INT_ENA_M (DMA_INFIFO_UDF_CH1_INT_ENA_V << DMA_INFIFO_UDF_CH1_INT_ENA_S) -#define DMA_INFIFO_UDF_CH1_INT_ENA_V 0x00000001 -#define DMA_INFIFO_UDF_CH1_INT_ENA_S 10 - -/* DMA_INFIFO_OVF_CH1_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - -#define DMA_INFIFO_OVF_CH1_INT_ENA (BIT(9)) -#define DMA_INFIFO_OVF_CH1_INT_ENA_M (DMA_INFIFO_OVF_CH1_INT_ENA_V << DMA_INFIFO_OVF_CH1_INT_ENA_S) -#define DMA_INFIFO_OVF_CH1_INT_ENA_V 0x00000001 -#define DMA_INFIFO_OVF_CH1_INT_ENA_S 9 - -/* DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - -#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V << DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S) -#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x00000001 -#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 8 - -/* DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - -#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V << DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S) -#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x00000001 -#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 7 - -/* DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - -#define DMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_M (DMA_OUT_DSCR_ERR_CH1_INT_ENA_V << DMA_OUT_DSCR_ERR_CH1_INT_ENA_S) -#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x00000001 -#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_S 6 - -/* DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - -#define DMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(5)) -#define DMA_IN_DSCR_ERR_CH1_INT_ENA_M (DMA_IN_DSCR_ERR_CH1_INT_ENA_V << DMA_IN_DSCR_ERR_CH1_INT_ENA_S) -#define DMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x00000001 -#define DMA_IN_DSCR_ERR_CH1_INT_ENA_S 5 - -/* DMA_OUT_EOF_CH1_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ - -#define DMA_OUT_EOF_CH1_INT_ENA (BIT(4)) -#define DMA_OUT_EOF_CH1_INT_ENA_M (DMA_OUT_EOF_CH1_INT_ENA_V << DMA_OUT_EOF_CH1_INT_ENA_S) -#define DMA_OUT_EOF_CH1_INT_ENA_V 0x00000001 -#define DMA_OUT_EOF_CH1_INT_ENA_S 4 - -/* DMA_OUT_DONE_CH1_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ - -#define DMA_OUT_DONE_CH1_INT_ENA (BIT(3)) -#define DMA_OUT_DONE_CH1_INT_ENA_M (DMA_OUT_DONE_CH1_INT_ENA_V << DMA_OUT_DONE_CH1_INT_ENA_S) -#define DMA_OUT_DONE_CH1_INT_ENA_V 0x00000001 -#define DMA_OUT_DONE_CH1_INT_ENA_S 3 - -/* DMA_IN_ERR_EOF_CH1_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ - -#define DMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) -#define DMA_IN_ERR_EOF_CH1_INT_ENA_M (DMA_IN_ERR_EOF_CH1_INT_ENA_V << DMA_IN_ERR_EOF_CH1_INT_ENA_S) -#define DMA_IN_ERR_EOF_CH1_INT_ENA_V 0x00000001 -#define DMA_IN_ERR_EOF_CH1_INT_ENA_S 2 - -/* DMA_IN_SUC_EOF_CH1_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ - -#define DMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) -#define DMA_IN_SUC_EOF_CH1_INT_ENA_M (DMA_IN_SUC_EOF_CH1_INT_ENA_V << DMA_IN_SUC_EOF_CH1_INT_ENA_S) -#define DMA_IN_SUC_EOF_CH1_INT_ENA_V 0x00000001 -#define DMA_IN_SUC_EOF_CH1_INT_ENA_S 1 - -/* DMA_IN_DONE_CH1_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ - -#define DMA_IN_DONE_CH1_INT_ENA (BIT(0)) -#define DMA_IN_DONE_CH1_INT_ENA_M (DMA_IN_DONE_CH1_INT_ENA_V << DMA_IN_DONE_CH1_INT_ENA_S) -#define DMA_IN_DONE_CH1_INT_ENA_V 0x00000001 -#define DMA_IN_DONE_CH1_INT_ENA_S 0 - -/* DMA_INT_CLR_CH1_REG register - * DMA_INT_CLR_CH1_REG. - */ - -#define DMA_INT_CLR_CH1_REG (DR_REG_GDMA_BASE + 0x1c) - -/* DMA_OUTFIFO_UDF_CH1_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - -#define DMA_OUTFIFO_UDF_CH1_INT_CLR (BIT(12)) -#define DMA_OUTFIFO_UDF_CH1_INT_CLR_M (DMA_OUTFIFO_UDF_CH1_INT_CLR_V << DMA_OUTFIFO_UDF_CH1_INT_CLR_S) -#define DMA_OUTFIFO_UDF_CH1_INT_CLR_V 0x00000001 -#define DMA_OUTFIFO_UDF_CH1_INT_CLR_S 12 - -/* DMA_OUTFIFO_OVF_CH1_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - -#define DMA_OUTFIFO_OVF_CH1_INT_CLR (BIT(11)) -#define DMA_OUTFIFO_OVF_CH1_INT_CLR_M (DMA_OUTFIFO_OVF_CH1_INT_CLR_V << DMA_OUTFIFO_OVF_CH1_INT_CLR_S) -#define DMA_OUTFIFO_OVF_CH1_INT_CLR_V 0x00000001 -#define DMA_OUTFIFO_OVF_CH1_INT_CLR_S 11 - -/* DMA_INFIFO_UDF_CH1_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ - -#define DMA_INFIFO_UDF_CH1_INT_CLR (BIT(10)) -#define DMA_INFIFO_UDF_CH1_INT_CLR_M (DMA_INFIFO_UDF_CH1_INT_CLR_V << DMA_INFIFO_UDF_CH1_INT_CLR_S) -#define DMA_INFIFO_UDF_CH1_INT_CLR_V 0x00000001 -#define DMA_INFIFO_UDF_CH1_INT_CLR_S 10 - -/* DMA_INFIFO_OVF_CH1_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ - -#define DMA_INFIFO_OVF_CH1_INT_CLR (BIT(9)) -#define DMA_INFIFO_OVF_CH1_INT_CLR_M (DMA_INFIFO_OVF_CH1_INT_CLR_V << DMA_INFIFO_OVF_CH1_INT_CLR_S) -#define DMA_INFIFO_OVF_CH1_INT_CLR_V 0x00000001 -#define DMA_INFIFO_OVF_CH1_INT_CLR_S 9 - -/* DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ - -#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V << DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S) -#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x00000001 -#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 8 - -/* DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ - -#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V << DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S) -#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x00000001 -#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 7 - -/* DMA_OUT_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ - -#define DMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_M (DMA_OUT_DSCR_ERR_CH1_INT_CLR_V << DMA_OUT_DSCR_ERR_CH1_INT_CLR_S) -#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x00000001 -#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_S 6 - -/* DMA_IN_DSCR_ERR_CH1_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. - */ - -#define DMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(5)) -#define DMA_IN_DSCR_ERR_CH1_INT_CLR_M (DMA_IN_DSCR_ERR_CH1_INT_CLR_V << DMA_IN_DSCR_ERR_CH1_INT_CLR_S) -#define DMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x00000001 -#define DMA_IN_DSCR_ERR_CH1_INT_CLR_S 5 - -/* DMA_OUT_EOF_CH1_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ - -#define DMA_OUT_EOF_CH1_INT_CLR (BIT(4)) -#define DMA_OUT_EOF_CH1_INT_CLR_M (DMA_OUT_EOF_CH1_INT_CLR_V << DMA_OUT_EOF_CH1_INT_CLR_S) -#define DMA_OUT_EOF_CH1_INT_CLR_V 0x00000001 -#define DMA_OUT_EOF_CH1_INT_CLR_S 4 - -/* DMA_OUT_DONE_CH1_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ - -#define DMA_OUT_DONE_CH1_INT_CLR (BIT(3)) -#define DMA_OUT_DONE_CH1_INT_CLR_M (DMA_OUT_DONE_CH1_INT_CLR_V << DMA_OUT_DONE_CH1_INT_CLR_S) -#define DMA_OUT_DONE_CH1_INT_CLR_V 0x00000001 -#define DMA_OUT_DONE_CH1_INT_CLR_S 3 - -/* DMA_IN_ERR_EOF_CH1_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ - -#define DMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) -#define DMA_IN_ERR_EOF_CH1_INT_CLR_M (DMA_IN_ERR_EOF_CH1_INT_CLR_V << DMA_IN_ERR_EOF_CH1_INT_CLR_S) -#define DMA_IN_ERR_EOF_CH1_INT_CLR_V 0x00000001 -#define DMA_IN_ERR_EOF_CH1_INT_CLR_S 2 - -/* DMA_IN_SUC_EOF_CH1_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ - -#define DMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) -#define DMA_IN_SUC_EOF_CH1_INT_CLR_M (DMA_IN_SUC_EOF_CH1_INT_CLR_V << DMA_IN_SUC_EOF_CH1_INT_CLR_S) -#define DMA_IN_SUC_EOF_CH1_INT_CLR_V 0x00000001 -#define DMA_IN_SUC_EOF_CH1_INT_CLR_S 1 - -/* DMA_IN_DONE_CH1_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ - -#define DMA_IN_DONE_CH1_INT_CLR (BIT(0)) -#define DMA_IN_DONE_CH1_INT_CLR_M (DMA_IN_DONE_CH1_INT_CLR_V << DMA_IN_DONE_CH1_INT_CLR_S) -#define DMA_IN_DONE_CH1_INT_CLR_V 0x00000001 -#define DMA_IN_DONE_CH1_INT_CLR_S 0 - -/* DMA_INT_RAW_CH2_REG register - * DMA_INT_RAW_CH2_REG. - */ - -#define DMA_INT_RAW_CH2_REG (DR_REG_GDMA_BASE + 0x20) - -/* DMA_OUTFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Tx - * channel 2 is underflow. - */ - -#define DMA_OUTFIFO_UDF_CH2_INT_RAW (BIT(12)) -#define DMA_OUTFIFO_UDF_CH2_INT_RAW_M (DMA_OUTFIFO_UDF_CH2_INT_RAW_V << DMA_OUTFIFO_UDF_CH2_INT_RAW_S) -#define DMA_OUTFIFO_UDF_CH2_INT_RAW_V 0x00000001 -#define DMA_OUTFIFO_UDF_CH2_INT_RAW_S 12 - -/* DMA_OUTFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Tx - * channel 2 is overflow. - */ - -#define DMA_OUTFIFO_OVF_CH2_INT_RAW (BIT(11)) -#define DMA_OUTFIFO_OVF_CH2_INT_RAW_M (DMA_OUTFIFO_OVF_CH2_INT_RAW_V << DMA_OUTFIFO_OVF_CH2_INT_RAW_S) -#define DMA_OUTFIFO_OVF_CH2_INT_RAW_V 0x00000001 -#define DMA_OUTFIFO_OVF_CH2_INT_RAW_S 11 - -/* DMA_INFIFO_UDF_CH2_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Rx - * channel 2 is underflow. - */ - -#define DMA_INFIFO_UDF_CH2_INT_RAW (BIT(10)) -#define DMA_INFIFO_UDF_CH2_INT_RAW_M (DMA_INFIFO_UDF_CH2_INT_RAW_V << DMA_INFIFO_UDF_CH2_INT_RAW_S) -#define DMA_INFIFO_UDF_CH2_INT_RAW_V 0x00000001 -#define DMA_INFIFO_UDF_CH2_INT_RAW_S 10 - -/* DMA_INFIFO_OVF_CH2_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * This raw interrupt bit turns to high level when level 1 fifo of Rx - * channel 2 is overflow. - */ - -#define DMA_INFIFO_OVF_CH2_INT_RAW (BIT(9)) -#define DMA_INFIFO_OVF_CH2_INT_RAW_M (DMA_INFIFO_OVF_CH2_INT_RAW_V << DMA_INFIFO_OVF_CH2_INT_RAW_S) -#define DMA_INFIFO_OVF_CH2_INT_RAW_V 0x00000001 -#define DMA_INFIFO_OVF_CH2_INT_RAW_S 9 - -/* DMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * The raw interrupt bit turns to high level when data corresponding a - * outlink (includes one link descriptor or few link descriptors) is - * transmitted out for Tx channel 2. - */ - -#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V << DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S) -#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x00000001 -#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 8 - -/* DMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * The raw interrupt bit turns to high level when Rx buffer pointed by - * inlink is full and receiving data is not completed, but there is no more - * inlink for Rx channel 2. - */ - -#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V << DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S) -#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x00000001 -#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 7 - -/* DMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * The raw interrupt bit turns to high level when detecting outlink - * descriptor error, including owner error, the second and third word error - * of outlink descriptor for Tx channel 2. - */ - -#define DMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_M (DMA_OUT_DSCR_ERR_CH2_INT_RAW_V << DMA_OUT_DSCR_ERR_CH2_INT_RAW_S) -#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x00000001 -#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_S 6 - -/* DMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * The raw interrupt bit turns to high level when detecting inlink - * descriptor error, including owner error, the second and third word error - * of inlink descriptor for Rx channel 2. - */ - -#define DMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(5)) -#define DMA_IN_DSCR_ERR_CH2_INT_RAW_M (DMA_IN_DSCR_ERR_CH2_INT_RAW_V << DMA_IN_DSCR_ERR_CH2_INT_RAW_S) -#define DMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x00000001 -#define DMA_IN_DSCR_ERR_CH2_INT_RAW_S 5 - -/* DMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by - * one outlink descriptor has been read from memory for Tx channel 2. - */ - -#define DMA_OUT_EOF_CH2_INT_RAW (BIT(4)) -#define DMA_OUT_EOF_CH2_INT_RAW_M (DMA_OUT_EOF_CH2_INT_RAW_V << DMA_OUT_EOF_CH2_INT_RAW_S) -#define DMA_OUT_EOF_CH2_INT_RAW_V 0x00000001 -#define DMA_OUT_EOF_CH2_INT_RAW_S 4 - -/* DMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by - * one outlink descriptor has been transmitted to peripherals for Tx channel - * 2. - */ - -#define DMA_OUT_DONE_CH2_INT_RAW (BIT(3)) -#define DMA_OUT_DONE_CH2_INT_RAW_M (DMA_OUT_DONE_CH2_INT_RAW_V << DMA_OUT_DONE_CH2_INT_RAW_S) -#define DMA_OUT_DONE_CH2_INT_RAW_V 0x00000001 -#define DMA_OUT_DONE_CH2_INT_RAW_S 3 - -/* DMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * The raw interrupt bit turns to high level when data error is detected - * only in the case that the peripheral is UHCI0 for Rx channel 2. For other - * peripherals, this raw interrupt is reserved. - */ - -#define DMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) -#define DMA_IN_ERR_EOF_CH2_INT_RAW_M (DMA_IN_ERR_EOF_CH2_INT_RAW_V << DMA_IN_ERR_EOF_CH2_INT_RAW_S) -#define DMA_IN_ERR_EOF_CH2_INT_RAW_V 0x00000001 -#define DMA_IN_ERR_EOF_CH2_INT_RAW_S 2 - -/* DMA_IN_SUC_EOF_CH2_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by - * one inlink descriptor has been received for Rx channel 2. For UHCI0, the - * raw interrupt bit turns to high level when the last data pointed by one - * inlink descriptor has been received and no data error is detected for Rx - * channel 2. - */ - -#define DMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) -#define DMA_IN_SUC_EOF_CH2_INT_RAW_M (DMA_IN_SUC_EOF_CH2_INT_RAW_V << DMA_IN_SUC_EOF_CH2_INT_RAW_S) -#define DMA_IN_SUC_EOF_CH2_INT_RAW_V 0x00000001 -#define DMA_IN_SUC_EOF_CH2_INT_RAW_S 1 - -/* DMA_IN_DONE_CH2_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * The raw interrupt bit turns to high level when the last data pointed by - * one inlink descriptor has been received for Rx channel 2. - */ - -#define DMA_IN_DONE_CH2_INT_RAW (BIT(0)) -#define DMA_IN_DONE_CH2_INT_RAW_M (DMA_IN_DONE_CH2_INT_RAW_V << DMA_IN_DONE_CH2_INT_RAW_S) -#define DMA_IN_DONE_CH2_INT_RAW_V 0x00000001 -#define DMA_IN_DONE_CH2_INT_RAW_S 0 - -/* DMA_INT_ST_CH2_REG register - * DMA_INT_ST_CH2_REG. - */ - -#define DMA_INT_ST_CH2_REG (DR_REG_GDMA_BASE + 0x24) - -/* DMA_OUTFIFO_UDF_CH2_INT_ST : RO; bitpos: [12]; default: 0; - * The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - -#define DMA_OUTFIFO_UDF_CH2_INT_ST (BIT(12)) -#define DMA_OUTFIFO_UDF_CH2_INT_ST_M (DMA_OUTFIFO_UDF_CH2_INT_ST_V << DMA_OUTFIFO_UDF_CH2_INT_ST_S) -#define DMA_OUTFIFO_UDF_CH2_INT_ST_V 0x00000001 -#define DMA_OUTFIFO_UDF_CH2_INT_ST_S 12 - -/* DMA_OUTFIFO_OVF_CH2_INT_ST : RO; bitpos: [11]; default: 0; - * The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - -#define DMA_OUTFIFO_OVF_CH2_INT_ST (BIT(11)) -#define DMA_OUTFIFO_OVF_CH2_INT_ST_M (DMA_OUTFIFO_OVF_CH2_INT_ST_V << DMA_OUTFIFO_OVF_CH2_INT_ST_S) -#define DMA_OUTFIFO_OVF_CH2_INT_ST_V 0x00000001 -#define DMA_OUTFIFO_OVF_CH2_INT_ST_S 11 - -/* DMA_INFIFO_UDF_CH2_INT_ST : RO; bitpos: [10]; default: 0; - * The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - -#define DMA_INFIFO_UDF_CH2_INT_ST (BIT(10)) -#define DMA_INFIFO_UDF_CH2_INT_ST_M (DMA_INFIFO_UDF_CH2_INT_ST_V << DMA_INFIFO_UDF_CH2_INT_ST_S) -#define DMA_INFIFO_UDF_CH2_INT_ST_V 0x00000001 -#define DMA_INFIFO_UDF_CH2_INT_ST_S 10 - -/* DMA_INFIFO_OVF_CH2_INT_ST : RO; bitpos: [9]; default: 0; - * The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - -#define DMA_INFIFO_OVF_CH2_INT_ST (BIT(9)) -#define DMA_INFIFO_OVF_CH2_INT_ST_M (DMA_INFIFO_OVF_CH2_INT_ST_V << DMA_INFIFO_OVF_CH2_INT_ST_S) -#define DMA_INFIFO_OVF_CH2_INT_ST_V 0x00000001 -#define DMA_INFIFO_OVF_CH2_INT_ST_S 9 - -/* DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO; bitpos: [8]; default: 0; - * The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - -#define DMA_OUT_TOTAL_EOF_CH2_INT_ST (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_M (DMA_OUT_TOTAL_EOF_CH2_INT_ST_V << DMA_OUT_TOTAL_EOF_CH2_INT_ST_S) -#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_V 0x00000001 -#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_S 8 - -/* DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO; bitpos: [7]; default: 0; - * The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - -#define DMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_M (DMA_IN_DSCR_EMPTY_CH2_INT_ST_V << DMA_IN_DSCR_EMPTY_CH2_INT_ST_S) -#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x00000001 -#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_S 7 - -/* DMA_OUT_DSCR_ERR_CH2_INT_ST : RO; bitpos: [6]; default: 0; - * The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - -#define DMA_OUT_DSCR_ERR_CH2_INT_ST (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH2_INT_ST_M (DMA_OUT_DSCR_ERR_CH2_INT_ST_V << DMA_OUT_DSCR_ERR_CH2_INT_ST_S) -#define DMA_OUT_DSCR_ERR_CH2_INT_ST_V 0x00000001 -#define DMA_OUT_DSCR_ERR_CH2_INT_ST_S 6 - -/* DMA_IN_DSCR_ERR_CH2_INT_ST : RO; bitpos: [5]; default: 0; - * The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - -#define DMA_IN_DSCR_ERR_CH2_INT_ST (BIT(5)) -#define DMA_IN_DSCR_ERR_CH2_INT_ST_M (DMA_IN_DSCR_ERR_CH2_INT_ST_V << DMA_IN_DSCR_ERR_CH2_INT_ST_S) -#define DMA_IN_DSCR_ERR_CH2_INT_ST_V 0x00000001 -#define DMA_IN_DSCR_ERR_CH2_INT_ST_S 5 - -/* DMA_OUT_EOF_CH2_INT_ST : RO; bitpos: [4]; default: 0; - * The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. - */ - -#define DMA_OUT_EOF_CH2_INT_ST (BIT(4)) -#define DMA_OUT_EOF_CH2_INT_ST_M (DMA_OUT_EOF_CH2_INT_ST_V << DMA_OUT_EOF_CH2_INT_ST_S) -#define DMA_OUT_EOF_CH2_INT_ST_V 0x00000001 -#define DMA_OUT_EOF_CH2_INT_ST_S 4 - -/* DMA_OUT_DONE_CH2_INT_ST : RO; bitpos: [3]; default: 0; - * The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. - */ - -#define DMA_OUT_DONE_CH2_INT_ST (BIT(3)) -#define DMA_OUT_DONE_CH2_INT_ST_M (DMA_OUT_DONE_CH2_INT_ST_V << DMA_OUT_DONE_CH2_INT_ST_S) -#define DMA_OUT_DONE_CH2_INT_ST_V 0x00000001 -#define DMA_OUT_DONE_CH2_INT_ST_S 3 - -/* DMA_IN_ERR_EOF_CH2_INT_ST : RO; bitpos: [2]; default: 0; - * The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. - */ - -#define DMA_IN_ERR_EOF_CH2_INT_ST (BIT(2)) -#define DMA_IN_ERR_EOF_CH2_INT_ST_M (DMA_IN_ERR_EOF_CH2_INT_ST_V << DMA_IN_ERR_EOF_CH2_INT_ST_S) -#define DMA_IN_ERR_EOF_CH2_INT_ST_V 0x00000001 -#define DMA_IN_ERR_EOF_CH2_INT_ST_S 2 - -/* DMA_IN_SUC_EOF_CH2_INT_ST : RO; bitpos: [1]; default: 0; - * The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. - */ - -#define DMA_IN_SUC_EOF_CH2_INT_ST (BIT(1)) -#define DMA_IN_SUC_EOF_CH2_INT_ST_M (DMA_IN_SUC_EOF_CH2_INT_ST_V << DMA_IN_SUC_EOF_CH2_INT_ST_S) -#define DMA_IN_SUC_EOF_CH2_INT_ST_V 0x00000001 -#define DMA_IN_SUC_EOF_CH2_INT_ST_S 1 - -/* DMA_IN_DONE_CH2_INT_ST : RO; bitpos: [0]; default: 0; - * The raw interrupt status bit for the IN_DONE_CH_INT interrupt. - */ - -#define DMA_IN_DONE_CH2_INT_ST (BIT(0)) -#define DMA_IN_DONE_CH2_INT_ST_M (DMA_IN_DONE_CH2_INT_ST_V << DMA_IN_DONE_CH2_INT_ST_S) -#define DMA_IN_DONE_CH2_INT_ST_V 0x00000001 -#define DMA_IN_DONE_CH2_INT_ST_S 0 - -/* DMA_INT_ENA_CH2_REG register - * DMA_INT_ENA_CH2_REG. - */ - -#define DMA_INT_ENA_CH2_REG (DR_REG_GDMA_BASE + 0x28) - -/* DMA_OUTFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - -#define DMA_OUTFIFO_UDF_CH2_INT_ENA (BIT(12)) -#define DMA_OUTFIFO_UDF_CH2_INT_ENA_M (DMA_OUTFIFO_UDF_CH2_INT_ENA_V << DMA_OUTFIFO_UDF_CH2_INT_ENA_S) -#define DMA_OUTFIFO_UDF_CH2_INT_ENA_V 0x00000001 -#define DMA_OUTFIFO_UDF_CH2_INT_ENA_S 12 - -/* DMA_OUTFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - -#define DMA_OUTFIFO_OVF_CH2_INT_ENA (BIT(11)) -#define DMA_OUTFIFO_OVF_CH2_INT_ENA_M (DMA_OUTFIFO_OVF_CH2_INT_ENA_V << DMA_OUTFIFO_OVF_CH2_INT_ENA_S) -#define DMA_OUTFIFO_OVF_CH2_INT_ENA_V 0x00000001 -#define DMA_OUTFIFO_OVF_CH2_INT_ENA_S 11 - -/* DMA_INFIFO_UDF_CH2_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - */ - -#define DMA_INFIFO_UDF_CH2_INT_ENA (BIT(10)) -#define DMA_INFIFO_UDF_CH2_INT_ENA_M (DMA_INFIFO_UDF_CH2_INT_ENA_V << DMA_INFIFO_UDF_CH2_INT_ENA_S) -#define DMA_INFIFO_UDF_CH2_INT_ENA_V 0x00000001 -#define DMA_INFIFO_UDF_CH2_INT_ENA_S 10 - -/* DMA_INFIFO_OVF_CH2_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - */ - -#define DMA_INFIFO_OVF_CH2_INT_ENA (BIT(9)) -#define DMA_INFIFO_OVF_CH2_INT_ENA_M (DMA_INFIFO_OVF_CH2_INT_ENA_V << DMA_INFIFO_OVF_CH2_INT_ENA_S) -#define DMA_INFIFO_OVF_CH2_INT_ENA_V 0x00000001 -#define DMA_INFIFO_OVF_CH2_INT_ENA_S 9 - -/* DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - */ - -#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V << DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S) -#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x00000001 -#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 8 - -/* DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - */ - -#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M (DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V << DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S) -#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x00000001 -#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S 7 - -/* DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - */ - -#define DMA_OUT_DSCR_ERR_CH2_INT_ENA (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_M (DMA_OUT_DSCR_ERR_CH2_INT_ENA_V << DMA_OUT_DSCR_ERR_CH2_INT_ENA_S) -#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_V 0x00000001 -#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_S 6 - -/* DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - */ - -#define DMA_IN_DSCR_ERR_CH2_INT_ENA (BIT(5)) -#define DMA_IN_DSCR_ERR_CH2_INT_ENA_M (DMA_IN_DSCR_ERR_CH2_INT_ENA_V << DMA_IN_DSCR_ERR_CH2_INT_ENA_S) -#define DMA_IN_DSCR_ERR_CH2_INT_ENA_V 0x00000001 -#define DMA_IN_DSCR_ERR_CH2_INT_ENA_S 5 - -/* DMA_OUT_EOF_CH2_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - */ - -#define DMA_OUT_EOF_CH2_INT_ENA (BIT(4)) -#define DMA_OUT_EOF_CH2_INT_ENA_M (DMA_OUT_EOF_CH2_INT_ENA_V << DMA_OUT_EOF_CH2_INT_ENA_S) -#define DMA_OUT_EOF_CH2_INT_ENA_V 0x00000001 -#define DMA_OUT_EOF_CH2_INT_ENA_S 4 - -/* DMA_OUT_DONE_CH2_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - */ - -#define DMA_OUT_DONE_CH2_INT_ENA (BIT(3)) -#define DMA_OUT_DONE_CH2_INT_ENA_M (DMA_OUT_DONE_CH2_INT_ENA_V << DMA_OUT_DONE_CH2_INT_ENA_S) -#define DMA_OUT_DONE_CH2_INT_ENA_V 0x00000001 -#define DMA_OUT_DONE_CH2_INT_ENA_S 3 - -/* DMA_IN_ERR_EOF_CH2_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - */ - -#define DMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) -#define DMA_IN_ERR_EOF_CH2_INT_ENA_M (DMA_IN_ERR_EOF_CH2_INT_ENA_V << DMA_IN_ERR_EOF_CH2_INT_ENA_S) -#define DMA_IN_ERR_EOF_CH2_INT_ENA_V 0x00000001 -#define DMA_IN_ERR_EOF_CH2_INT_ENA_S 2 - -/* DMA_IN_SUC_EOF_CH2_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - */ - -#define DMA_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) -#define DMA_IN_SUC_EOF_CH2_INT_ENA_M (DMA_IN_SUC_EOF_CH2_INT_ENA_V << DMA_IN_SUC_EOF_CH2_INT_ENA_S) -#define DMA_IN_SUC_EOF_CH2_INT_ENA_V 0x00000001 -#define DMA_IN_SUC_EOF_CH2_INT_ENA_S 1 - -/* DMA_IN_DONE_CH2_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the IN_DONE_CH_INT interrupt. - */ - -#define DMA_IN_DONE_CH2_INT_ENA (BIT(0)) -#define DMA_IN_DONE_CH2_INT_ENA_M (DMA_IN_DONE_CH2_INT_ENA_V << DMA_IN_DONE_CH2_INT_ENA_S) -#define DMA_IN_DONE_CH2_INT_ENA_V 0x00000001 -#define DMA_IN_DONE_CH2_INT_ENA_S 0 - -/* DMA_INT_CLR_CH2_REG register - * DMA_INT_CLR_CH2_REG. - */ - -#define DMA_INT_CLR_CH2_REG (DR_REG_GDMA_BASE + 0x2c) - -/* DMA_OUTFIFO_UDF_CH2_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - */ - -#define DMA_OUTFIFO_UDF_CH2_INT_CLR (BIT(12)) -#define DMA_OUTFIFO_UDF_CH2_INT_CLR_M (DMA_OUTFIFO_UDF_CH2_INT_CLR_V << DMA_OUTFIFO_UDF_CH2_INT_CLR_S) -#define DMA_OUTFIFO_UDF_CH2_INT_CLR_V 0x00000001 -#define DMA_OUTFIFO_UDF_CH2_INT_CLR_S 12 - -/* DMA_OUTFIFO_OVF_CH2_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - */ - -#define DMA_OUTFIFO_OVF_CH2_INT_CLR (BIT(11)) -#define DMA_OUTFIFO_OVF_CH2_INT_CLR_M (DMA_OUTFIFO_OVF_CH2_INT_CLR_V << DMA_OUTFIFO_OVF_CH2_INT_CLR_S) -#define DMA_OUTFIFO_OVF_CH2_INT_CLR_V 0x00000001 -#define DMA_OUTFIFO_OVF_CH2_INT_CLR_S 11 - -/* DMA_INFIFO_UDF_CH2_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - */ - -#define DMA_INFIFO_UDF_CH2_INT_CLR (BIT(10)) -#define DMA_INFIFO_UDF_CH2_INT_CLR_M (DMA_INFIFO_UDF_CH2_INT_CLR_V << DMA_INFIFO_UDF_CH2_INT_CLR_S) -#define DMA_INFIFO_UDF_CH2_INT_CLR_V 0x00000001 -#define DMA_INFIFO_UDF_CH2_INT_CLR_S 10 - -/* DMA_INFIFO_OVF_CH2_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - */ - -#define DMA_INFIFO_OVF_CH2_INT_CLR (BIT(9)) -#define DMA_INFIFO_OVF_CH2_INT_CLR_M (DMA_INFIFO_OVF_CH2_INT_CLR_V << DMA_INFIFO_OVF_CH2_INT_CLR_S) -#define DMA_INFIFO_OVF_CH2_INT_CLR_V 0x00000001 -#define DMA_INFIFO_OVF_CH2_INT_CLR_S 9 - -/* DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - */ - -#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(8)) -#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M (DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V << DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S) -#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x00000001 -#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S 8 - -/* DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - */ - -#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(7)) -#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M (DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V << DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S) -#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x00000001 -#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S 7 - -/* DMA_OUT_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - */ - -#define DMA_OUT_DSCR_ERR_CH2_INT_CLR (BIT(6)) -#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_M (DMA_OUT_DSCR_ERR_CH2_INT_CLR_V << DMA_OUT_DSCR_ERR_CH2_INT_CLR_S) -#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_V 0x00000001 -#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_S 6 - -/* DMA_IN_DSCR_ERR_CH2_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. - */ - -#define DMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(5)) -#define DMA_IN_DSCR_ERR_CH2_INT_CLR_M (DMA_IN_DSCR_ERR_CH2_INT_CLR_V << DMA_IN_DSCR_ERR_CH2_INT_CLR_S) -#define DMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x00000001 -#define DMA_IN_DSCR_ERR_CH2_INT_CLR_S 5 - -/* DMA_OUT_EOF_CH2_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear the OUT_EOF_CH_INT interrupt. - */ - -#define DMA_OUT_EOF_CH2_INT_CLR (BIT(4)) -#define DMA_OUT_EOF_CH2_INT_CLR_M (DMA_OUT_EOF_CH2_INT_CLR_V << DMA_OUT_EOF_CH2_INT_CLR_S) -#define DMA_OUT_EOF_CH2_INT_CLR_V 0x00000001 -#define DMA_OUT_EOF_CH2_INT_CLR_S 4 - -/* DMA_OUT_DONE_CH2_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear the OUT_DONE_CH_INT interrupt. - */ - -#define DMA_OUT_DONE_CH2_INT_CLR (BIT(3)) -#define DMA_OUT_DONE_CH2_INT_CLR_M (DMA_OUT_DONE_CH2_INT_CLR_V << DMA_OUT_DONE_CH2_INT_CLR_S) -#define DMA_OUT_DONE_CH2_INT_CLR_V 0x00000001 -#define DMA_OUT_DONE_CH2_INT_CLR_S 3 - -/* DMA_IN_ERR_EOF_CH2_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - */ - -#define DMA_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) -#define DMA_IN_ERR_EOF_CH2_INT_CLR_M (DMA_IN_ERR_EOF_CH2_INT_CLR_V << DMA_IN_ERR_EOF_CH2_INT_CLR_S) -#define DMA_IN_ERR_EOF_CH2_INT_CLR_V 0x00000001 -#define DMA_IN_ERR_EOF_CH2_INT_CLR_S 2 - -/* DMA_IN_SUC_EOF_CH2_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - */ - -#define DMA_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) -#define DMA_IN_SUC_EOF_CH2_INT_CLR_M (DMA_IN_SUC_EOF_CH2_INT_CLR_V << DMA_IN_SUC_EOF_CH2_INT_CLR_S) -#define DMA_IN_SUC_EOF_CH2_INT_CLR_V 0x00000001 -#define DMA_IN_SUC_EOF_CH2_INT_CLR_S 1 - -/* DMA_IN_DONE_CH2_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the IN_DONE_CH_INT interrupt. - */ - -#define DMA_IN_DONE_CH2_INT_CLR (BIT(0)) -#define DMA_IN_DONE_CH2_INT_CLR_M (DMA_IN_DONE_CH2_INT_CLR_V << DMA_IN_DONE_CH2_INT_CLR_S) -#define DMA_IN_DONE_CH2_INT_CLR_V 0x00000001 -#define DMA_IN_DONE_CH2_INT_CLR_S 0 - -/* DMA_AHB_TEST_REG register - * DMA_AHB_TEST_REG. - */ - -#define DMA_AHB_TEST_REG (DR_REG_GDMA_BASE + 0x40) - -/* DMA_AHB_TESTADDR : R/W; bitpos: [5:4]; default: 0; - * reserved - */ - -#define DMA_AHB_TESTADDR 0x00000003 -#define DMA_AHB_TESTADDR_M (DMA_AHB_TESTADDR_V << DMA_AHB_TESTADDR_S) -#define DMA_AHB_TESTADDR_V 0x00000003 -#define DMA_AHB_TESTADDR_S 4 - -/* DMA_AHB_TESTMODE : R/W; bitpos: [2:0]; default: 0; - * reserved - */ - -#define DMA_AHB_TESTMODE 0x00000007 -#define DMA_AHB_TESTMODE_M (DMA_AHB_TESTMODE_V << DMA_AHB_TESTMODE_S) -#define DMA_AHB_TESTMODE_V 0x00000007 -#define DMA_AHB_TESTMODE_S 0 - -/* DMA_MISC_CONF_REG register - * DMA_MISC_CONF_REG. - */ - -#define DMA_MISC_CONF_REG (DR_REG_GDMA_BASE + 0x44) - -/* DMA_CLK_EN : R/W; bitpos: [3]; default: 0; - * reg_clk_en - */ - -#define DMA_CLK_EN (BIT(3)) -#define DMA_CLK_EN_M (DMA_CLK_EN_V << DMA_CLK_EN_S) -#define DMA_CLK_EN_V 0x00000001 -#define DMA_CLK_EN_S 3 - -/* DMA_ARB_PRI_DIS : R/W; bitpos: [2]; default: 0; - * Set this bit to disable priority arbitration function. - */ - -#define DMA_ARB_PRI_DIS (BIT(2)) -#define DMA_ARB_PRI_DIS_M (DMA_ARB_PRI_DIS_V << DMA_ARB_PRI_DIS_S) -#define DMA_ARB_PRI_DIS_V 0x00000001 -#define DMA_ARB_PRI_DIS_S 2 - -/* DMA_AHBM_RST_INTER : R/W; bitpos: [0]; default: 0; - * Set this bit, then clear this bit to reset the internal ahb FSM. - */ - -#define DMA_AHBM_RST_INTER (BIT(0)) -#define DMA_AHBM_RST_INTER_M (DMA_AHBM_RST_INTER_V << DMA_AHBM_RST_INTER_S) -#define DMA_AHBM_RST_INTER_V 0x00000001 -#define DMA_AHBM_RST_INTER_S 0 - -/* DMA_DATE_REG register - * DMA_DATE_REG. - */ - -#define DMA_DATE_REG (DR_REG_GDMA_BASE + 0x48) - -/* DMA_DATE : R/W; bitpos: [31:0]; default: 33587792; - * register version. - */ - -#define DMA_DATE 0xFFFFFFFF -#define DMA_DATE_M (DMA_DATE_V << DMA_DATE_S) -#define DMA_DATE_V 0xFFFFFFFF -#define DMA_DATE_S 0 - -/* DMA_IN_CONF0_CH0_REG register - * DMA_IN_CONF0_CH0_REG. - */ - -#define DMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x70) - -/* DMA_MEM_TRANS_EN_CH0 : R/W; bitpos: [4]; default: 0; - * Set this bit 1 to enable automatic transmitting data from memory to - * memory via DMA. - */ - -#define DMA_MEM_TRANS_EN_CH0 (BIT(4)) -#define DMA_MEM_TRANS_EN_CH0_M (DMA_MEM_TRANS_EN_CH0_V << DMA_MEM_TRANS_EN_CH0_S) -#define DMA_MEM_TRANS_EN_CH0_V 0x00000001 -#define DMA_MEM_TRANS_EN_CH0_S 4 - -/* DMA_IN_DATA_BURST_EN_CH0 : R/W; bitpos: [3]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 - * receiving data when accessing internal SRAM. - */ - -#define DMA_IN_DATA_BURST_EN_CH0 (BIT(3)) -#define DMA_IN_DATA_BURST_EN_CH0_M (DMA_IN_DATA_BURST_EN_CH0_V << DMA_IN_DATA_BURST_EN_CH0_S) -#define DMA_IN_DATA_BURST_EN_CH0_V 0x00000001 -#define DMA_IN_DATA_BURST_EN_CH0_S 3 - -/* DMA_INDSCR_BURST_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading - * link descriptor when accessing internal SRAM. - */ - -#define DMA_INDSCR_BURST_EN_CH0 (BIT(2)) -#define DMA_INDSCR_BURST_EN_CH0_M (DMA_INDSCR_BURST_EN_CH0_V << DMA_INDSCR_BURST_EN_CH0_S) -#define DMA_INDSCR_BURST_EN_CH0_V 0x00000001 -#define DMA_INDSCR_BURST_EN_CH0_S 2 - -/* DMA_IN_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; - * reserved - */ - -#define DMA_IN_LOOP_TEST_CH0 (BIT(1)) -#define DMA_IN_LOOP_TEST_CH0_M (DMA_IN_LOOP_TEST_CH0_V << DMA_IN_LOOP_TEST_CH0_S) -#define DMA_IN_LOOP_TEST_CH0_V 0x00000001 -#define DMA_IN_LOOP_TEST_CH0_S 1 - -/* DMA_IN_RST_CH0 : R/W; bitpos: [0]; default: 0; - * This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. - */ - -#define DMA_IN_RST_CH0 (BIT(0)) -#define DMA_IN_RST_CH0_M (DMA_IN_RST_CH0_V << DMA_IN_RST_CH0_S) -#define DMA_IN_RST_CH0_V 0x00000001 -#define DMA_IN_RST_CH0_S 0 - -/* DMA_IN_CONF1_CH0_REG register - * DMA_IN_CONF1_CH0_REG. - */ - -#define DMA_IN_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0x74) - -/* DMA_IN_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; - * Set this bit to enable checking the owner attribute of the link - * descriptor. - */ - -#define DMA_IN_CHECK_OWNER_CH0 (BIT(12)) -#define DMA_IN_CHECK_OWNER_CH0_M (DMA_IN_CHECK_OWNER_CH0_V << DMA_IN_CHECK_OWNER_CH0_S) -#define DMA_IN_CHECK_OWNER_CH0_V 0x00000001 -#define DMA_IN_CHECK_OWNER_CH0_S 12 - -/* DMA_INFIFO_STATUS_CH0_REG register - * DMA_INFIFO_STATUS_CH0_REG. - */ - -#define DMA_INFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0x78) - -/* DMA_IN_BUF_HUNGRY_CH0 : RO; bitpos: [27]; default: 0; - * reserved - */ - -#define DMA_IN_BUF_HUNGRY_CH0 (BIT(27)) -#define DMA_IN_BUF_HUNGRY_CH0_M (DMA_IN_BUF_HUNGRY_CH0_V << DMA_IN_BUF_HUNGRY_CH0_S) -#define DMA_IN_BUF_HUNGRY_CH0_V 0x00000001 -#define DMA_IN_BUF_HUNGRY_CH0_S 27 - -/* DMA_IN_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; - * reserved - */ - -#define DMA_IN_REMAIN_UNDER_4B_CH0 (BIT(26)) -#define DMA_IN_REMAIN_UNDER_4B_CH0_M (DMA_IN_REMAIN_UNDER_4B_CH0_V << DMA_IN_REMAIN_UNDER_4B_CH0_S) -#define DMA_IN_REMAIN_UNDER_4B_CH0_V 0x00000001 -#define DMA_IN_REMAIN_UNDER_4B_CH0_S 26 - -/* DMA_IN_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; - * reserved - */ - -#define DMA_IN_REMAIN_UNDER_3B_CH0 (BIT(25)) -#define DMA_IN_REMAIN_UNDER_3B_CH0_M (DMA_IN_REMAIN_UNDER_3B_CH0_V << DMA_IN_REMAIN_UNDER_3B_CH0_S) -#define DMA_IN_REMAIN_UNDER_3B_CH0_V 0x00000001 -#define DMA_IN_REMAIN_UNDER_3B_CH0_S 25 - -/* DMA_IN_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; - * reserved - */ - -#define DMA_IN_REMAIN_UNDER_2B_CH0 (BIT(24)) -#define DMA_IN_REMAIN_UNDER_2B_CH0_M (DMA_IN_REMAIN_UNDER_2B_CH0_V << DMA_IN_REMAIN_UNDER_2B_CH0_S) -#define DMA_IN_REMAIN_UNDER_2B_CH0_V 0x00000001 -#define DMA_IN_REMAIN_UNDER_2B_CH0_S 24 - -/* DMA_IN_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; - * reserved - */ - -#define DMA_IN_REMAIN_UNDER_1B_CH0 (BIT(23)) -#define DMA_IN_REMAIN_UNDER_1B_CH0_M (DMA_IN_REMAIN_UNDER_1B_CH0_V << DMA_IN_REMAIN_UNDER_1B_CH0_S) -#define DMA_IN_REMAIN_UNDER_1B_CH0_V 0x00000001 -#define DMA_IN_REMAIN_UNDER_1B_CH0_S 23 - -/* DMA_INFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; - * The register stores the byte number of the data in L1 Rx FIFO for Rx - * channel 0. - */ - -#define DMA_INFIFO_CNT_CH0 0x0000003F -#define DMA_INFIFO_CNT_CH0_M (DMA_INFIFO_CNT_CH0_V << DMA_INFIFO_CNT_CH0_S) -#define DMA_INFIFO_CNT_CH0_V 0x0000003F -#define DMA_INFIFO_CNT_CH0_S 2 - -/* DMA_INFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; - * L1 Rx FIFO empty signal for Rx channel 0. - */ - -#define DMA_INFIFO_EMPTY_CH0 (BIT(1)) -#define DMA_INFIFO_EMPTY_CH0_M (DMA_INFIFO_EMPTY_CH0_V << DMA_INFIFO_EMPTY_CH0_S) -#define DMA_INFIFO_EMPTY_CH0_V 0x00000001 -#define DMA_INFIFO_EMPTY_CH0_S 1 - -/* DMA_INFIFO_FULL_CH0 : RO; bitpos: [0]; default: 1; - * L1 Rx FIFO full signal for Rx channel 0. - */ - -#define DMA_INFIFO_FULL_CH0 (BIT(0)) -#define DMA_INFIFO_FULL_CH0_M (DMA_INFIFO_FULL_CH0_V << DMA_INFIFO_FULL_CH0_S) -#define DMA_INFIFO_FULL_CH0_V 0x00000001 -#define DMA_INFIFO_FULL_CH0_S 0 - -/* DMA_IN_POP_CH0_REG register - * DMA_IN_POP_CH0_REG. - */ - -#define DMA_IN_POP_CH0_REG (DR_REG_GDMA_BASE + 0x7c) - -/* DMA_INFIFO_POP_CH0 : R/W/SC; bitpos: [12]; default: 0; - * Set this bit to pop data from DMA FIFO. - */ - -#define DMA_INFIFO_POP_CH0 (BIT(12)) -#define DMA_INFIFO_POP_CH0_M (DMA_INFIFO_POP_CH0_V << DMA_INFIFO_POP_CH0_S) -#define DMA_INFIFO_POP_CH0_V 0x00000001 -#define DMA_INFIFO_POP_CH0_S 12 - -/* DMA_INFIFO_RDATA_CH0 : RO; bitpos: [11:0]; default: 2048; - * This register stores the data popping from DMA FIFO. - */ - -#define DMA_INFIFO_RDATA_CH0 0x00000FFF -#define DMA_INFIFO_RDATA_CH0_M (DMA_INFIFO_RDATA_CH0_V << DMA_INFIFO_RDATA_CH0_S) -#define DMA_INFIFO_RDATA_CH0_V 0x00000FFF -#define DMA_INFIFO_RDATA_CH0_S 0 - -/* DMA_IN_LINK_CH0_REG register - * DMA_IN_LINK_CH0_REG. - */ - -#define DMA_IN_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x80) - -/* DMA_INLINK_PARK_CH0 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink - * descriptor's FSM is working. - */ - -#define DMA_INLINK_PARK_CH0 (BIT(24)) -#define DMA_INLINK_PARK_CH0_M (DMA_INLINK_PARK_CH0_V << DMA_INLINK_PARK_CH0_S) -#define DMA_INLINK_PARK_CH0_V 0x00000001 -#define DMA_INLINK_PARK_CH0_S 24 - -/* DMA_INLINK_RESTART_CH0 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ - -#define DMA_INLINK_RESTART_CH0 (BIT(23)) -#define DMA_INLINK_RESTART_CH0_M (DMA_INLINK_RESTART_CH0_V << DMA_INLINK_RESTART_CH0_S) -#define DMA_INLINK_RESTART_CH0_V 0x00000001 -#define DMA_INLINK_RESTART_CH0_S 23 - -/* DMA_INLINK_START_CH0 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ - -#define DMA_INLINK_START_CH0 (BIT(22)) -#define DMA_INLINK_START_CH0_M (DMA_INLINK_START_CH0_V << DMA_INLINK_START_CH0_S) -#define DMA_INLINK_START_CH0_V 0x00000001 -#define DMA_INLINK_START_CH0_S 22 - -/* DMA_INLINK_STOP_CH0 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ - -#define DMA_INLINK_STOP_CH0 (BIT(21)) -#define DMA_INLINK_STOP_CH0_M (DMA_INLINK_STOP_CH0_V << DMA_INLINK_STOP_CH0_S) -#define DMA_INLINK_STOP_CH0_V 0x00000001 -#define DMA_INLINK_STOP_CH0_S 21 - -/* DMA_INLINK_AUTO_RET_CH0 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there - * are some errors in current receiving data. - */ - -#define DMA_INLINK_AUTO_RET_CH0 (BIT(20)) -#define DMA_INLINK_AUTO_RET_CH0_M (DMA_INLINK_AUTO_RET_CH0_V << DMA_INLINK_AUTO_RET_CH0_S) -#define DMA_INLINK_AUTO_RET_CH0_V 0x00000001 -#define DMA_INLINK_AUTO_RET_CH0_S 20 - -/* DMA_INLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; - * This register stores the 20 least significant bits of the first inlink - * descriptor's address. - */ - -#define DMA_INLINK_ADDR_CH0 0x000FFFFF -#define DMA_INLINK_ADDR_CH0_M (DMA_INLINK_ADDR_CH0_V << DMA_INLINK_ADDR_CH0_S) -#define DMA_INLINK_ADDR_CH0_V 0x000FFFFF -#define DMA_INLINK_ADDR_CH0_S 0 - -/* DMA_IN_STATE_CH0_REG register - * DMA_IN_STATE_CH0_REG. - */ - -#define DMA_IN_STATE_CH0_REG (DR_REG_GDMA_BASE + 0x84) - -/* DMA_IN_STATE_CH0 : RO; bitpos: [22:20]; default: 0; - * reserved - */ - -#define DMA_IN_STATE_CH0 0x00000007 -#define DMA_IN_STATE_CH0_M (DMA_IN_STATE_CH0_V << DMA_IN_STATE_CH0_S) -#define DMA_IN_STATE_CH0_V 0x00000007 -#define DMA_IN_STATE_CH0_S 20 - -/* DMA_IN_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; - * reserved - */ - -#define DMA_IN_DSCR_STATE_CH0 0x00000003 -#define DMA_IN_DSCR_STATE_CH0_M (DMA_IN_DSCR_STATE_CH0_V << DMA_IN_DSCR_STATE_CH0_S) -#define DMA_IN_DSCR_STATE_CH0_V 0x00000003 -#define DMA_IN_DSCR_STATE_CH0_S 18 - -/* DMA_INLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ - -#define DMA_INLINK_DSCR_ADDR_CH0 0x0003FFFF -#define DMA_INLINK_DSCR_ADDR_CH0_M (DMA_INLINK_DSCR_ADDR_CH0_V << DMA_INLINK_DSCR_ADDR_CH0_S) -#define DMA_INLINK_DSCR_ADDR_CH0_V 0x0003FFFF -#define DMA_INLINK_DSCR_ADDR_CH0_S 0 - -/* DMA_IN_SUC_EOF_DES_ADDR_CH0_REG register - * DMA_IN_SUC_EOF_DES_ADDR_CH0_REG. - */ - -#define DMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x88) - -/* DMA_IN_SUC_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF - * bit in this descriptor is 1. - */ - -#define DMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFF -#define DMA_IN_SUC_EOF_DES_ADDR_CH0_M (DMA_IN_SUC_EOF_DES_ADDR_CH0_V << DMA_IN_SUC_EOF_DES_ADDR_CH0_S) -#define DMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFF -#define DMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 - -/* DMA_IN_ERR_EOF_DES_ADDR_CH0_REG register - * DMA_IN_ERR_EOF_DES_ADDR_CH0_REG. - */ - -#define DMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x8c) - -/* DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are - * some errors in current receiving data. Only used when peripheral is UHCI0. - */ - -#define DMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFF -#define DMA_IN_ERR_EOF_DES_ADDR_CH0_M (DMA_IN_ERR_EOF_DES_ADDR_CH0_V << DMA_IN_ERR_EOF_DES_ADDR_CH0_S) -#define DMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFF -#define DMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 - -/* DMA_IN_DSCR_CH0_REG register - * DMA_IN_DSCR_CH0_REG. - */ - -#define DMA_IN_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0x90) - -/* DMA_INLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the current inlink descriptor x. - */ - -#define DMA_INLINK_DSCR_CH0 0xFFFFFFFF -#define DMA_INLINK_DSCR_CH0_M (DMA_INLINK_DSCR_CH0_V << DMA_INLINK_DSCR_CH0_S) -#define DMA_INLINK_DSCR_CH0_V 0xFFFFFFFF -#define DMA_INLINK_DSCR_CH0_S 0 - -/* DMA_IN_DSCR_BF0_CH0_REG register - * DMA_IN_DSCR_BF0_CH0_REG. - */ - -#define DMA_IN_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0x94) - -/* DMA_INLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor x-1. - */ - -#define DMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF0_CH0_M (DMA_INLINK_DSCR_BF0_CH0_V << DMA_INLINK_DSCR_BF0_CH0_S) -#define DMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF0_CH0_S 0 - -/* DMA_IN_DSCR_BF1_CH0_REG register - * DMA_IN_DSCR_BF1_CH0_REG. - */ - -#define DMA_IN_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0x98) - -/* DMA_INLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor x-2. - */ - -#define DMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF1_CH0_M (DMA_INLINK_DSCR_BF1_CH0_V << DMA_INLINK_DSCR_BF1_CH0_S) -#define DMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF1_CH0_S 0 - -/* DMA_IN_PRI_CH0_REG register - * DMA_IN_PRI_CH0_REG. - */ - -#define DMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x9c) - -/* DMA_RX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; - * The priority of Rx channel 0. The larger of the value, the higher of the - * priority. - */ - -#define DMA_RX_PRI_CH0 0x0000000F -#define DMA_RX_PRI_CH0_M (DMA_RX_PRI_CH0_V << DMA_RX_PRI_CH0_S) -#define DMA_RX_PRI_CH0_V 0x0000000F -#define DMA_RX_PRI_CH0_S 0 - -/* DMA_IN_PERI_SEL_CH0_REG register - * DMA_IN_PERI_SEL_CH0_REG. - */ - -#define DMA_IN_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0xa0) - -/* DMA_PERI_IN_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; - * This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: - * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: - * ADC_DAC. - */ - -#define DMA_PERI_IN_SEL_CH0 0x0000003F -#define DMA_PERI_IN_SEL_CH0_M (DMA_PERI_IN_SEL_CH0_V << DMA_PERI_IN_SEL_CH0_S) -#define DMA_PERI_IN_SEL_CH0_V 0x0000003F -#define DMA_PERI_IN_SEL_CH0_S 0 - -/* DMA_OUT_CONF0_CH0_REG register - * DMA_OUT_CONF0_CH0_REG. - */ - -#define DMA_OUT_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0xd0) - -/* DMA_OUT_DATA_BURST_EN_CH0 : R/W; bitpos: [5]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 - * transmitting data when accessing internal SRAM. - */ - -#define DMA_OUT_DATA_BURST_EN_CH0 (BIT(5)) -#define DMA_OUT_DATA_BURST_EN_CH0_M (DMA_OUT_DATA_BURST_EN_CH0_V << DMA_OUT_DATA_BURST_EN_CH0_S) -#define DMA_OUT_DATA_BURST_EN_CH0_V 0x00000001 -#define DMA_OUT_DATA_BURST_EN_CH0_S 5 - -/* DMA_OUTDSCR_BURST_EN_CH0 : R/W; bitpos: [4]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading - * link descriptor when accessing internal SRAM. - */ - -#define DMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) -#define DMA_OUTDSCR_BURST_EN_CH0_M (DMA_OUTDSCR_BURST_EN_CH0_V << DMA_OUTDSCR_BURST_EN_CH0_S) -#define DMA_OUTDSCR_BURST_EN_CH0_V 0x00000001 -#define DMA_OUTDSCR_BURST_EN_CH0_S 4 - -/* DMA_OUT_EOF_MODE_CH0 : R/W; bitpos: [3]; default: 1; - * EOF flag generation mode when transmitting data. 1: EOF flag for Tx - * channel 0 is generated when data need to transmit has been popped from - * FIFO in DMA - */ - -#define DMA_OUT_EOF_MODE_CH0 (BIT(3)) -#define DMA_OUT_EOF_MODE_CH0_M (DMA_OUT_EOF_MODE_CH0_V << DMA_OUT_EOF_MODE_CH0_S) -#define DMA_OUT_EOF_MODE_CH0_V 0x00000001 -#define DMA_OUT_EOF_MODE_CH0_S 3 - -/* DMA_OUT_AUTO_WRBACK_CH0 : R/W; bitpos: [2]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data in - * tx buffer has been transmitted. - */ - -#define DMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) -#define DMA_OUT_AUTO_WRBACK_CH0_M (DMA_OUT_AUTO_WRBACK_CH0_V << DMA_OUT_AUTO_WRBACK_CH0_S) -#define DMA_OUT_AUTO_WRBACK_CH0_V 0x00000001 -#define DMA_OUT_AUTO_WRBACK_CH0_S 2 - -/* DMA_OUT_LOOP_TEST_CH0 : R/W; bitpos: [1]; default: 0; - * reserved - */ - -#define DMA_OUT_LOOP_TEST_CH0 (BIT(1)) -#define DMA_OUT_LOOP_TEST_CH0_M (DMA_OUT_LOOP_TEST_CH0_V << DMA_OUT_LOOP_TEST_CH0_S) -#define DMA_OUT_LOOP_TEST_CH0_V 0x00000001 -#define DMA_OUT_LOOP_TEST_CH0_S 1 - -/* DMA_OUT_RST_CH0 : R/W; bitpos: [0]; default: 0; - * This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. - */ - -#define DMA_OUT_RST_CH0 (BIT(0)) -#define DMA_OUT_RST_CH0_M (DMA_OUT_RST_CH0_V << DMA_OUT_RST_CH0_S) -#define DMA_OUT_RST_CH0_V 0x00000001 -#define DMA_OUT_RST_CH0_S 0 - -/* DMA_OUT_CONF1_CH0_REG register - * DMA_OUT_CONF1_CH0_REG. - */ - -#define DMA_OUT_CONF1_CH0_REG (DR_REG_GDMA_BASE + 0xd4) - -/* DMA_OUT_CHECK_OWNER_CH0 : R/W; bitpos: [12]; default: 0; - * Set this bit to enable checking the owner attribute of the link - * descriptor. - */ - -#define DMA_OUT_CHECK_OWNER_CH0 (BIT(12)) -#define DMA_OUT_CHECK_OWNER_CH0_M (DMA_OUT_CHECK_OWNER_CH0_V << DMA_OUT_CHECK_OWNER_CH0_S) -#define DMA_OUT_CHECK_OWNER_CH0_V 0x00000001 -#define DMA_OUT_CHECK_OWNER_CH0_S 12 - -/* DMA_OUTFIFO_STATUS_CH0_REG register - * DMA_OUTFIFO_STATUS_CH0_REG. - */ - -#define DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_GDMA_BASE + 0xd8) - -/* DMA_OUT_REMAIN_UNDER_4B_CH0 : RO; bitpos: [26]; default: 1; - * reserved - */ - -#define DMA_OUT_REMAIN_UNDER_4B_CH0 (BIT(26)) -#define DMA_OUT_REMAIN_UNDER_4B_CH0_M (DMA_OUT_REMAIN_UNDER_4B_CH0_V << DMA_OUT_REMAIN_UNDER_4B_CH0_S) -#define DMA_OUT_REMAIN_UNDER_4B_CH0_V 0x00000001 -#define DMA_OUT_REMAIN_UNDER_4B_CH0_S 26 - -/* DMA_OUT_REMAIN_UNDER_3B_CH0 : RO; bitpos: [25]; default: 1; - * reserved - */ - -#define DMA_OUT_REMAIN_UNDER_3B_CH0 (BIT(25)) -#define DMA_OUT_REMAIN_UNDER_3B_CH0_M (DMA_OUT_REMAIN_UNDER_3B_CH0_V << DMA_OUT_REMAIN_UNDER_3B_CH0_S) -#define DMA_OUT_REMAIN_UNDER_3B_CH0_V 0x00000001 -#define DMA_OUT_REMAIN_UNDER_3B_CH0_S 25 - -/* DMA_OUT_REMAIN_UNDER_2B_CH0 : RO; bitpos: [24]; default: 1; - * reserved - */ - -#define DMA_OUT_REMAIN_UNDER_2B_CH0 (BIT(24)) -#define DMA_OUT_REMAIN_UNDER_2B_CH0_M (DMA_OUT_REMAIN_UNDER_2B_CH0_V << DMA_OUT_REMAIN_UNDER_2B_CH0_S) -#define DMA_OUT_REMAIN_UNDER_2B_CH0_V 0x00000001 -#define DMA_OUT_REMAIN_UNDER_2B_CH0_S 24 - -/* DMA_OUT_REMAIN_UNDER_1B_CH0 : RO; bitpos: [23]; default: 1; - * reserved - */ - -#define DMA_OUT_REMAIN_UNDER_1B_CH0 (BIT(23)) -#define DMA_OUT_REMAIN_UNDER_1B_CH0_M (DMA_OUT_REMAIN_UNDER_1B_CH0_V << DMA_OUT_REMAIN_UNDER_1B_CH0_S) -#define DMA_OUT_REMAIN_UNDER_1B_CH0_V 0x00000001 -#define DMA_OUT_REMAIN_UNDER_1B_CH0_S 23 - -/* DMA_OUTFIFO_CNT_CH0 : RO; bitpos: [7:2]; default: 0; - * The register stores the byte number of the data in L1 Tx FIFO for Tx - * channel 0. - */ - -#define DMA_OUTFIFO_CNT_CH0 0x0000003F -#define DMA_OUTFIFO_CNT_CH0_M (DMA_OUTFIFO_CNT_CH0_V << DMA_OUTFIFO_CNT_CH0_S) -#define DMA_OUTFIFO_CNT_CH0_V 0x0000003F -#define DMA_OUTFIFO_CNT_CH0_S 2 - -/* DMA_OUTFIFO_EMPTY_CH0 : RO; bitpos: [1]; default: 1; - * L1 Tx FIFO empty signal for Tx channel 0. - */ - -#define DMA_OUTFIFO_EMPTY_CH0 (BIT(1)) -#define DMA_OUTFIFO_EMPTY_CH0_M (DMA_OUTFIFO_EMPTY_CH0_V << DMA_OUTFIFO_EMPTY_CH0_S) -#define DMA_OUTFIFO_EMPTY_CH0_V 0x00000001 -#define DMA_OUTFIFO_EMPTY_CH0_S 1 - -/* DMA_OUTFIFO_FULL_CH0 : RO; bitpos: [0]; default: 0; - * L1 Tx FIFO full signal for Tx channel 0. - */ - -#define DMA_OUTFIFO_FULL_CH0 (BIT(0)) -#define DMA_OUTFIFO_FULL_CH0_M (DMA_OUTFIFO_FULL_CH0_V << DMA_OUTFIFO_FULL_CH0_S) -#define DMA_OUTFIFO_FULL_CH0_V 0x00000001 -#define DMA_OUTFIFO_FULL_CH0_S 0 - -/* DMA_OUT_PUSH_CH0_REG register - * DMA_OUT_PUSH_CH0_REG. - */ - -#define DMA_OUT_PUSH_CH0_REG (DR_REG_GDMA_BASE + 0xdc) - -/* DMA_OUTFIFO_PUSH_CH0 : R/W/SC; bitpos: [9]; default: 0; - * Set this bit to push data into DMA FIFO. - */ - -#define DMA_OUTFIFO_PUSH_CH0 (BIT(9)) -#define DMA_OUTFIFO_PUSH_CH0_M (DMA_OUTFIFO_PUSH_CH0_V << DMA_OUTFIFO_PUSH_CH0_S) -#define DMA_OUTFIFO_PUSH_CH0_V 0x00000001 -#define DMA_OUTFIFO_PUSH_CH0_S 9 - -/* DMA_OUTFIFO_WDATA_CH0 : R/W; bitpos: [8:0]; default: 0; - * This register stores the data that need to be pushed into DMA FIFO. - */ - -#define DMA_OUTFIFO_WDATA_CH0 0x000001FF -#define DMA_OUTFIFO_WDATA_CH0_M (DMA_OUTFIFO_WDATA_CH0_V << DMA_OUTFIFO_WDATA_CH0_S) -#define DMA_OUTFIFO_WDATA_CH0_V 0x000001FF -#define DMA_OUTFIFO_WDATA_CH0_S 0 - -/* DMA_OUT_LINK_CH0_REG register - * DMA_OUT_LINK_CH0_REG. - */ - -#define DMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0xe0) - -/* DMA_OUTLINK_PARK_CH0 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink - * descriptor's FSM is working. - */ - -#define DMA_OUTLINK_PARK_CH0 (BIT(23)) -#define DMA_OUTLINK_PARK_CH0_M (DMA_OUTLINK_PARK_CH0_V << DMA_OUTLINK_PARK_CH0_S) -#define DMA_OUTLINK_PARK_CH0_V 0x00000001 -#define DMA_OUTLINK_PARK_CH0_S 23 - -/* DMA_OUTLINK_RESTART_CH0 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ - -#define DMA_OUTLINK_RESTART_CH0 (BIT(22)) -#define DMA_OUTLINK_RESTART_CH0_M (DMA_OUTLINK_RESTART_CH0_V << DMA_OUTLINK_RESTART_CH0_S) -#define DMA_OUTLINK_RESTART_CH0_V 0x00000001 -#define DMA_OUTLINK_RESTART_CH0_S 22 - -/* DMA_OUTLINK_START_CH0 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ - -#define DMA_OUTLINK_START_CH0 (BIT(21)) -#define DMA_OUTLINK_START_CH0_M (DMA_OUTLINK_START_CH0_V << DMA_OUTLINK_START_CH0_S) -#define DMA_OUTLINK_START_CH0_V 0x00000001 -#define DMA_OUTLINK_START_CH0_S 21 - -/* DMA_OUTLINK_STOP_CH0 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ - -#define DMA_OUTLINK_STOP_CH0 (BIT(20)) -#define DMA_OUTLINK_STOP_CH0_M (DMA_OUTLINK_STOP_CH0_V << DMA_OUTLINK_STOP_CH0_S) -#define DMA_OUTLINK_STOP_CH0_V 0x00000001 -#define DMA_OUTLINK_STOP_CH0_S 20 - -/* DMA_OUTLINK_ADDR_CH0 : R/W; bitpos: [19:0]; default: 0; - * This register stores the 20 least significant bits of the first outlink - * descriptor's address. - */ - -#define DMA_OUTLINK_ADDR_CH0 0x000FFFFF -#define DMA_OUTLINK_ADDR_CH0_M (DMA_OUTLINK_ADDR_CH0_V << DMA_OUTLINK_ADDR_CH0_S) -#define DMA_OUTLINK_ADDR_CH0_V 0x000FFFFF -#define DMA_OUTLINK_ADDR_CH0_S 0 - -/* DMA_OUT_STATE_CH0_REG register - * DMA_OUT_STATE_CH0_REG. - */ - -#define DMA_OUT_STATE_CH0_REG (DR_REG_GDMA_BASE + 0xe4) - -/* DMA_OUT_STATE_CH0 : RO; bitpos: [22:20]; default: 0; - * reserved - */ - -#define DMA_OUT_STATE_CH0 0x00000007 -#define DMA_OUT_STATE_CH0_M (DMA_OUT_STATE_CH0_V << DMA_OUT_STATE_CH0_S) -#define DMA_OUT_STATE_CH0_V 0x00000007 -#define DMA_OUT_STATE_CH0_S 20 - -/* DMA_OUT_DSCR_STATE_CH0 : RO; bitpos: [19:18]; default: 0; - * reserved - */ - -#define DMA_OUT_DSCR_STATE_CH0 0x00000003 -#define DMA_OUT_DSCR_STATE_CH0_M (DMA_OUT_DSCR_STATE_CH0_V << DMA_OUT_DSCR_STATE_CH0_S) -#define DMA_OUT_DSCR_STATE_CH0_V 0x00000003 -#define DMA_OUT_DSCR_STATE_CH0_S 18 - -/* DMA_OUTLINK_DSCR_ADDR_CH0 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ - -#define DMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFF -#define DMA_OUTLINK_DSCR_ADDR_CH0_M (DMA_OUTLINK_DSCR_ADDR_CH0_V << DMA_OUTLINK_DSCR_ADDR_CH0_S) -#define DMA_OUTLINK_DSCR_ADDR_CH0_V 0x0003FFFF -#define DMA_OUTLINK_DSCR_ADDR_CH0_S 0 - -/* DMA_OUT_EOF_DES_ADDR_CH0_REG register - * DMA_OUT_EOF_DES_ADDR_CH0_REG. - */ - -#define DMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xe8) - -/* DMA_OUT_EOF_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF - * bit in this descriptor is 1. - */ - -#define DMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFF -#define DMA_OUT_EOF_DES_ADDR_CH0_M (DMA_OUT_EOF_DES_ADDR_CH0_V << DMA_OUT_EOF_DES_ADDR_CH0_S) -#define DMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFF -#define DMA_OUT_EOF_DES_ADDR_CH0_S 0 - -/* DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG register - * DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG. - */ - -#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0xec) - -/* DMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor before the - * last outlink descriptor. - */ - -#define DMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFF -#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_M (DMA_OUT_EOF_BFR_DES_ADDR_CH0_V << DMA_OUT_EOF_BFR_DES_ADDR_CH0_S) -#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFF -#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 - -/* DMA_OUT_DSCR_CH0_REG register - * DMA_OUT_DSCR_CH0_REG. - */ - -#define DMA_OUT_DSCR_CH0_REG (DR_REG_GDMA_BASE + 0xf0) - -/* DMA_OUTLINK_DSCR_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the current outlink descriptor y. - */ - -#define DMA_OUTLINK_DSCR_CH0 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_CH0_M (DMA_OUTLINK_DSCR_CH0_V << DMA_OUTLINK_DSCR_CH0_S) -#define DMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_CH0_S 0 - -/* DMA_OUT_DSCR_BF0_CH0_REG register - * DMA_OUT_DSCR_BF0_CH0_REG. - */ - -#define DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_GDMA_BASE + 0xf4) - -/* DMA_OUTLINK_DSCR_BF0_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor y-1. - */ - -#define DMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF0_CH0_M (DMA_OUTLINK_DSCR_BF0_CH0_V << DMA_OUTLINK_DSCR_BF0_CH0_S) -#define DMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF0_CH0_S 0 - -/* DMA_OUT_DSCR_BF1_CH0_REG register - * DMA_OUT_DSCR_BF1_CH0_REG. - */ - -#define DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_GDMA_BASE + 0xf8) - -/* DMA_OUTLINK_DSCR_BF1_CH0 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor x-2. - */ - -#define DMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF1_CH0_M (DMA_OUTLINK_DSCR_BF1_CH0_V << DMA_OUTLINK_DSCR_BF1_CH0_S) -#define DMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF1_CH0_S 0 - -/* DMA_OUT_PRI_CH0_REG register - * DMA_OUT_PRI_CH0_REG. - */ - -#define DMA_OUT_PRI_CH0_REG (DR_REG_GDMA_BASE + 0xfc) - -/* DMA_TX_PRI_CH0 : R/W; bitpos: [3:0]; default: 0; - * The priority of Tx channel 0. The larger of the value, the higher of the - * priority. - */ - -#define DMA_TX_PRI_CH0 0x0000000F -#define DMA_TX_PRI_CH0_M (DMA_TX_PRI_CH0_V << DMA_TX_PRI_CH0_S) -#define DMA_TX_PRI_CH0_V 0x0000000F -#define DMA_TX_PRI_CH0_S 0 - -/* DMA_OUT_PERI_SEL_CH0_REG register - * DMA_OUT_PERI_SEL_CH0_REG. - */ - -#define DMA_OUT_PERI_SEL_CH0_REG (DR_REG_GDMA_BASE + 0x100) - -/* DMA_PERI_OUT_SEL_CH0 : R/W; bitpos: [5:0]; default: 63; - * This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: - * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: - * ADC_DAC. - */ - -#define DMA_PERI_OUT_SEL_CH0 0x0000003F -#define DMA_PERI_OUT_SEL_CH0_M (DMA_PERI_OUT_SEL_CH0_V << DMA_PERI_OUT_SEL_CH0_S) -#define DMA_PERI_OUT_SEL_CH0_V 0x0000003F -#define DMA_PERI_OUT_SEL_CH0_S 0 - -/* DMA_IN_CONF0_CH1_REG register - * DMA_IN_CONF0_CH1_REG. - */ - -#define DMA_IN_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x130) - -/* DMA_MEM_TRANS_EN_CH1 : R/W; bitpos: [4]; default: 0; - * Set this bit 1 to enable automatic transmitting data from memory to - * memory via DMA. - */ - -#define DMA_MEM_TRANS_EN_CH1 (BIT(4)) -#define DMA_MEM_TRANS_EN_CH1_M (DMA_MEM_TRANS_EN_CH1_V << DMA_MEM_TRANS_EN_CH1_S) -#define DMA_MEM_TRANS_EN_CH1_V 0x00000001 -#define DMA_MEM_TRANS_EN_CH1_S 4 - -/* DMA_IN_DATA_BURST_EN_CH1 : R/W; bitpos: [3]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 - * receiving data when accessing internal SRAM. - */ - -#define DMA_IN_DATA_BURST_EN_CH1 (BIT(3)) -#define DMA_IN_DATA_BURST_EN_CH1_M (DMA_IN_DATA_BURST_EN_CH1_V << DMA_IN_DATA_BURST_EN_CH1_S) -#define DMA_IN_DATA_BURST_EN_CH1_V 0x00000001 -#define DMA_IN_DATA_BURST_EN_CH1_S 3 - -/* DMA_INDSCR_BURST_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading - * link descriptor when accessing internal SRAM. - */ - -#define DMA_INDSCR_BURST_EN_CH1 (BIT(2)) -#define DMA_INDSCR_BURST_EN_CH1_M (DMA_INDSCR_BURST_EN_CH1_V << DMA_INDSCR_BURST_EN_CH1_S) -#define DMA_INDSCR_BURST_EN_CH1_V 0x00000001 -#define DMA_INDSCR_BURST_EN_CH1_S 2 - -/* DMA_IN_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; - * reserved - */ - -#define DMA_IN_LOOP_TEST_CH1 (BIT(1)) -#define DMA_IN_LOOP_TEST_CH1_M (DMA_IN_LOOP_TEST_CH1_V << DMA_IN_LOOP_TEST_CH1_S) -#define DMA_IN_LOOP_TEST_CH1_V 0x00000001 -#define DMA_IN_LOOP_TEST_CH1_S 1 - -/* DMA_IN_RST_CH1 : R/W; bitpos: [0]; default: 0; - * This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer. - */ - -#define DMA_IN_RST_CH1 (BIT(0)) -#define DMA_IN_RST_CH1_M (DMA_IN_RST_CH1_V << DMA_IN_RST_CH1_S) -#define DMA_IN_RST_CH1_V 0x00000001 -#define DMA_IN_RST_CH1_S 0 - -/* DMA_IN_CONF1_CH1_REG register - * DMA_IN_CONF1_CH1_REG. - */ - -#define DMA_IN_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x134) - -/* DMA_IN_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; - * Set this bit to enable checking the owner attribute of the link - * descriptor. - */ - -#define DMA_IN_CHECK_OWNER_CH1 (BIT(12)) -#define DMA_IN_CHECK_OWNER_CH1_M (DMA_IN_CHECK_OWNER_CH1_V << DMA_IN_CHECK_OWNER_CH1_S) -#define DMA_IN_CHECK_OWNER_CH1_V 0x00000001 -#define DMA_IN_CHECK_OWNER_CH1_S 12 - -/* DMA_INFIFO_STATUS_CH1_REG register - * DMA_INFIFO_STATUS_CH1_REG. - */ - -#define DMA_INFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x138) - -/* DMA_IN_BUF_HUNGRY_CH1 : RO; bitpos: [27]; default: 0; - * reserved - */ - -#define DMA_IN_BUF_HUNGRY_CH1 (BIT(27)) -#define DMA_IN_BUF_HUNGRY_CH1_M (DMA_IN_BUF_HUNGRY_CH1_V << DMA_IN_BUF_HUNGRY_CH1_S) -#define DMA_IN_BUF_HUNGRY_CH1_V 0x00000001 -#define DMA_IN_BUF_HUNGRY_CH1_S 27 - -/* DMA_IN_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; - * reserved - */ - -#define DMA_IN_REMAIN_UNDER_4B_CH1 (BIT(26)) -#define DMA_IN_REMAIN_UNDER_4B_CH1_M (DMA_IN_REMAIN_UNDER_4B_CH1_V << DMA_IN_REMAIN_UNDER_4B_CH1_S) -#define DMA_IN_REMAIN_UNDER_4B_CH1_V 0x00000001 -#define DMA_IN_REMAIN_UNDER_4B_CH1_S 26 - -/* DMA_IN_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; - * reserved - */ - -#define DMA_IN_REMAIN_UNDER_3B_CH1 (BIT(25)) -#define DMA_IN_REMAIN_UNDER_3B_CH1_M (DMA_IN_REMAIN_UNDER_3B_CH1_V << DMA_IN_REMAIN_UNDER_3B_CH1_S) -#define DMA_IN_REMAIN_UNDER_3B_CH1_V 0x00000001 -#define DMA_IN_REMAIN_UNDER_3B_CH1_S 25 - -/* DMA_IN_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; - * reserved - */ - -#define DMA_IN_REMAIN_UNDER_2B_CH1 (BIT(24)) -#define DMA_IN_REMAIN_UNDER_2B_CH1_M (DMA_IN_REMAIN_UNDER_2B_CH1_V << DMA_IN_REMAIN_UNDER_2B_CH1_S) -#define DMA_IN_REMAIN_UNDER_2B_CH1_V 0x00000001 -#define DMA_IN_REMAIN_UNDER_2B_CH1_S 24 - -/* DMA_IN_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; - * reserved - */ - -#define DMA_IN_REMAIN_UNDER_1B_CH1 (BIT(23)) -#define DMA_IN_REMAIN_UNDER_1B_CH1_M (DMA_IN_REMAIN_UNDER_1B_CH1_V << DMA_IN_REMAIN_UNDER_1B_CH1_S) -#define DMA_IN_REMAIN_UNDER_1B_CH1_V 0x00000001 -#define DMA_IN_REMAIN_UNDER_1B_CH1_S 23 - -/* DMA_INFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; - * The register stores the byte number of the data in L1 Rx FIFO for Rx - * channel 1. - */ - -#define DMA_INFIFO_CNT_CH1 0x0000003F -#define DMA_INFIFO_CNT_CH1_M (DMA_INFIFO_CNT_CH1_V << DMA_INFIFO_CNT_CH1_S) -#define DMA_INFIFO_CNT_CH1_V 0x0000003F -#define DMA_INFIFO_CNT_CH1_S 2 - -/* DMA_INFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; - * L1 Rx FIFO empty signal for Rx channel 1. - */ - -#define DMA_INFIFO_EMPTY_CH1 (BIT(1)) -#define DMA_INFIFO_EMPTY_CH1_M (DMA_INFIFO_EMPTY_CH1_V << DMA_INFIFO_EMPTY_CH1_S) -#define DMA_INFIFO_EMPTY_CH1_V 0x00000001 -#define DMA_INFIFO_EMPTY_CH1_S 1 - -/* DMA_INFIFO_FULL_CH1 : RO; bitpos: [0]; default: 1; - * L1 Rx FIFO full signal for Rx channel 1. - */ - -#define DMA_INFIFO_FULL_CH1 (BIT(0)) -#define DMA_INFIFO_FULL_CH1_M (DMA_INFIFO_FULL_CH1_V << DMA_INFIFO_FULL_CH1_S) -#define DMA_INFIFO_FULL_CH1_V 0x00000001 -#define DMA_INFIFO_FULL_CH1_S 0 - -/* DMA_IN_POP_CH1_REG register - * DMA_IN_POP_CH1_REG. - */ - -#define DMA_IN_POP_CH1_REG (DR_REG_GDMA_BASE + 0x13c) - -/* DMA_INFIFO_POP_CH1 : R/W/SC; bitpos: [12]; default: 0; - * Set this bit to pop data from DMA FIFO. - */ - -#define DMA_INFIFO_POP_CH1 (BIT(12)) -#define DMA_INFIFO_POP_CH1_M (DMA_INFIFO_POP_CH1_V << DMA_INFIFO_POP_CH1_S) -#define DMA_INFIFO_POP_CH1_V 0x00000001 -#define DMA_INFIFO_POP_CH1_S 12 - -/* DMA_INFIFO_RDATA_CH1 : RO; bitpos: [11:0]; default: 2048; - * This register stores the data popping from DMA FIFO. - */ - -#define DMA_INFIFO_RDATA_CH1 0x00000FFF -#define DMA_INFIFO_RDATA_CH1_M (DMA_INFIFO_RDATA_CH1_V << DMA_INFIFO_RDATA_CH1_S) -#define DMA_INFIFO_RDATA_CH1_V 0x00000FFF -#define DMA_INFIFO_RDATA_CH1_S 0 - -/* DMA_IN_LINK_CH1_REG register - * DMA_IN_LINK_CH1_REG. - */ - -#define DMA_IN_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x140) - -/* DMA_INLINK_PARK_CH1 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink - * descriptor's FSM is working. - */ - -#define DMA_INLINK_PARK_CH1 (BIT(24)) -#define DMA_INLINK_PARK_CH1_M (DMA_INLINK_PARK_CH1_V << DMA_INLINK_PARK_CH1_S) -#define DMA_INLINK_PARK_CH1_V 0x00000001 -#define DMA_INLINK_PARK_CH1_S 24 - -/* DMA_INLINK_RESTART_CH1 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ - -#define DMA_INLINK_RESTART_CH1 (BIT(23)) -#define DMA_INLINK_RESTART_CH1_M (DMA_INLINK_RESTART_CH1_V << DMA_INLINK_RESTART_CH1_S) -#define DMA_INLINK_RESTART_CH1_V 0x00000001 -#define DMA_INLINK_RESTART_CH1_S 23 - -/* DMA_INLINK_START_CH1 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ - -#define DMA_INLINK_START_CH1 (BIT(22)) -#define DMA_INLINK_START_CH1_M (DMA_INLINK_START_CH1_V << DMA_INLINK_START_CH1_S) -#define DMA_INLINK_START_CH1_V 0x00000001 -#define DMA_INLINK_START_CH1_S 22 - -/* DMA_INLINK_STOP_CH1 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ - -#define DMA_INLINK_STOP_CH1 (BIT(21)) -#define DMA_INLINK_STOP_CH1_M (DMA_INLINK_STOP_CH1_V << DMA_INLINK_STOP_CH1_S) -#define DMA_INLINK_STOP_CH1_V 0x00000001 -#define DMA_INLINK_STOP_CH1_S 21 - -/* DMA_INLINK_AUTO_RET_CH1 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there - * are some errors in current receiving data. - */ - -#define DMA_INLINK_AUTO_RET_CH1 (BIT(20)) -#define DMA_INLINK_AUTO_RET_CH1_M (DMA_INLINK_AUTO_RET_CH1_V << DMA_INLINK_AUTO_RET_CH1_S) -#define DMA_INLINK_AUTO_RET_CH1_V 0x00000001 -#define DMA_INLINK_AUTO_RET_CH1_S 20 - -/* DMA_INLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0; - * This register stores the 20 least significant bits of the first inlink - * descriptor's address. - */ - -#define DMA_INLINK_ADDR_CH1 0x000FFFFF -#define DMA_INLINK_ADDR_CH1_M (DMA_INLINK_ADDR_CH1_V << DMA_INLINK_ADDR_CH1_S) -#define DMA_INLINK_ADDR_CH1_V 0x000FFFFF -#define DMA_INLINK_ADDR_CH1_S 0 - -/* DMA_IN_STATE_CH1_REG register - * DMA_IN_STATE_CH1_REG. - */ - -#define DMA_IN_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x144) - -/* DMA_IN_STATE_CH1 : RO; bitpos: [22:20]; default: 0; - * reserved - */ - -#define DMA_IN_STATE_CH1 0x00000007 -#define DMA_IN_STATE_CH1_M (DMA_IN_STATE_CH1_V << DMA_IN_STATE_CH1_S) -#define DMA_IN_STATE_CH1_V 0x00000007 -#define DMA_IN_STATE_CH1_S 20 - -/* DMA_IN_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; - * reserved - */ - -#define DMA_IN_DSCR_STATE_CH1 0x00000003 -#define DMA_IN_DSCR_STATE_CH1_M (DMA_IN_DSCR_STATE_CH1_V << DMA_IN_DSCR_STATE_CH1_S) -#define DMA_IN_DSCR_STATE_CH1_V 0x00000003 -#define DMA_IN_DSCR_STATE_CH1_S 18 - -/* DMA_INLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ - -#define DMA_INLINK_DSCR_ADDR_CH1 0x0003FFFF -#define DMA_INLINK_DSCR_ADDR_CH1_M (DMA_INLINK_DSCR_ADDR_CH1_V << DMA_INLINK_DSCR_ADDR_CH1_S) -#define DMA_INLINK_DSCR_ADDR_CH1_V 0x0003FFFF -#define DMA_INLINK_DSCR_ADDR_CH1_S 0 - -/* DMA_IN_SUC_EOF_DES_ADDR_CH1_REG register - * DMA_IN_SUC_EOF_DES_ADDR_CH1_REG. - */ - -#define DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x148) - -/* DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF - * bit in this descriptor is 1. - */ - -#define DMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFF -#define DMA_IN_SUC_EOF_DES_ADDR_CH1_M (DMA_IN_SUC_EOF_DES_ADDR_CH1_V << DMA_IN_SUC_EOF_DES_ADDR_CH1_S) -#define DMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFF -#define DMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 - -/* DMA_IN_ERR_EOF_DES_ADDR_CH1_REG register - * DMA_IN_ERR_EOF_DES_ADDR_CH1_REG. - */ - -#define DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x14c) - -/* DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are - * some errors in current receiving data. Only used when peripheral is UHCI0. - */ - -#define DMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFF -#define DMA_IN_ERR_EOF_DES_ADDR_CH1_M (DMA_IN_ERR_EOF_DES_ADDR_CH1_V << DMA_IN_ERR_EOF_DES_ADDR_CH1_S) -#define DMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFF -#define DMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 - -/* DMA_IN_DSCR_CH1_REG register - * DMA_IN_DSCR_CH1_REG. - */ - -#define DMA_IN_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x150) - -/* DMA_INLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the current inlink descriptor x. - */ - -#define DMA_INLINK_DSCR_CH1 0xFFFFFFFF -#define DMA_INLINK_DSCR_CH1_M (DMA_INLINK_DSCR_CH1_V << DMA_INLINK_DSCR_CH1_S) -#define DMA_INLINK_DSCR_CH1_V 0xFFFFFFFF -#define DMA_INLINK_DSCR_CH1_S 0 - -/* DMA_IN_DSCR_BF0_CH1_REG register - * DMA_IN_DSCR_BF0_CH1_REG. - */ - -#define DMA_IN_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x154) - -/* DMA_INLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor x-1. - */ - -#define DMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF0_CH1_M (DMA_INLINK_DSCR_BF0_CH1_V << DMA_INLINK_DSCR_BF0_CH1_S) -#define DMA_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF0_CH1_S 0 - -/* DMA_IN_DSCR_BF1_CH1_REG register - * DMA_IN_DSCR_BF1_CH1_REG. - */ - -#define DMA_IN_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x158) - -/* DMA_INLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor x-2. - */ - -#define DMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF1_CH1_M (DMA_INLINK_DSCR_BF1_CH1_V << DMA_INLINK_DSCR_BF1_CH1_S) -#define DMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF1_CH1_S 0 - -/* DMA_IN_PRI_CH1_REG register - * DMA_IN_PRI_CH1_REG. - */ - -#define DMA_IN_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x15c) - -/* DMA_RX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; - * The priority of Rx channel 1. The larger of the value, the higher of the - * priority. - */ - -#define DMA_RX_PRI_CH1 0x0000000F -#define DMA_RX_PRI_CH1_M (DMA_RX_PRI_CH1_V << DMA_RX_PRI_CH1_S) -#define DMA_RX_PRI_CH1_V 0x0000000F -#define DMA_RX_PRI_CH1_S 0 - -/* DMA_IN_PERI_SEL_CH1_REG register - * DMA_IN_PERI_SEL_CH1_REG. - */ - -#define DMA_IN_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x160) - -/* DMA_PERI_IN_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; - * This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: - * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: - * ADC_DAC. - */ - -#define DMA_PERI_IN_SEL_CH1 0x0000003F -#define DMA_PERI_IN_SEL_CH1_M (DMA_PERI_IN_SEL_CH1_V << DMA_PERI_IN_SEL_CH1_S) -#define DMA_PERI_IN_SEL_CH1_V 0x0000003F -#define DMA_PERI_IN_SEL_CH1_S 0 - -/* DMA_OUT_CONF0_CH1_REG register - * DMA_OUT_CONF0_CH1_REG. - */ - -#define DMA_OUT_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x190) - -/* DMA_OUT_DATA_BURST_EN_CH1 : R/W; bitpos: [5]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 - * transmitting data when accessing internal SRAM. - */ - -#define DMA_OUT_DATA_BURST_EN_CH1 (BIT(5)) -#define DMA_OUT_DATA_BURST_EN_CH1_M (DMA_OUT_DATA_BURST_EN_CH1_V << DMA_OUT_DATA_BURST_EN_CH1_S) -#define DMA_OUT_DATA_BURST_EN_CH1_V 0x00000001 -#define DMA_OUT_DATA_BURST_EN_CH1_S 5 - -/* DMA_OUTDSCR_BURST_EN_CH1 : R/W; bitpos: [4]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading - * link descriptor when accessing internal SRAM. - */ - -#define DMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) -#define DMA_OUTDSCR_BURST_EN_CH1_M (DMA_OUTDSCR_BURST_EN_CH1_V << DMA_OUTDSCR_BURST_EN_CH1_S) -#define DMA_OUTDSCR_BURST_EN_CH1_V 0x00000001 -#define DMA_OUTDSCR_BURST_EN_CH1_S 4 - -/* DMA_OUT_EOF_MODE_CH1 : R/W; bitpos: [3]; default: 1; - * EOF flag generation mode when transmitting data. 1: EOF flag for Tx - * channel 1 is generated when data need to transmit has been popped from - * FIFO in DMA - */ - -#define DMA_OUT_EOF_MODE_CH1 (BIT(3)) -#define DMA_OUT_EOF_MODE_CH1_M (DMA_OUT_EOF_MODE_CH1_V << DMA_OUT_EOF_MODE_CH1_S) -#define DMA_OUT_EOF_MODE_CH1_V 0x00000001 -#define DMA_OUT_EOF_MODE_CH1_S 3 - -/* DMA_OUT_AUTO_WRBACK_CH1 : R/W; bitpos: [2]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data in - * tx buffer has been transmitted. - */ - -#define DMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) -#define DMA_OUT_AUTO_WRBACK_CH1_M (DMA_OUT_AUTO_WRBACK_CH1_V << DMA_OUT_AUTO_WRBACK_CH1_S) -#define DMA_OUT_AUTO_WRBACK_CH1_V 0x00000001 -#define DMA_OUT_AUTO_WRBACK_CH1_S 2 - -/* DMA_OUT_LOOP_TEST_CH1 : R/W; bitpos: [1]; default: 0; - * reserved - */ - -#define DMA_OUT_LOOP_TEST_CH1 (BIT(1)) -#define DMA_OUT_LOOP_TEST_CH1_M (DMA_OUT_LOOP_TEST_CH1_V << DMA_OUT_LOOP_TEST_CH1_S) -#define DMA_OUT_LOOP_TEST_CH1_V 0x00000001 -#define DMA_OUT_LOOP_TEST_CH1_S 1 - -/* DMA_OUT_RST_CH1 : R/W; bitpos: [0]; default: 0; - * This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. - */ - -#define DMA_OUT_RST_CH1 (BIT(0)) -#define DMA_OUT_RST_CH1_M (DMA_OUT_RST_CH1_V << DMA_OUT_RST_CH1_S) -#define DMA_OUT_RST_CH1_V 0x00000001 -#define DMA_OUT_RST_CH1_S 0 - -/* DMA_OUT_CONF1_CH1_REG register - * DMA_OUT_CONF1_CH1_REG. - */ - -#define DMA_OUT_CONF1_CH1_REG (DR_REG_GDMA_BASE + 0x194) - -/* DMA_OUT_CHECK_OWNER_CH1 : R/W; bitpos: [12]; default: 0; - * Set this bit to enable checking the owner attribute of the link - * descriptor. - */ - -#define DMA_OUT_CHECK_OWNER_CH1 (BIT(12)) -#define DMA_OUT_CHECK_OWNER_CH1_M (DMA_OUT_CHECK_OWNER_CH1_V << DMA_OUT_CHECK_OWNER_CH1_S) -#define DMA_OUT_CHECK_OWNER_CH1_V 0x00000001 -#define DMA_OUT_CHECK_OWNER_CH1_S 12 - -/* DMA_OUTFIFO_STATUS_CH1_REG register - * DMA_OUTFIFO_STATUS_CH1_REG. - */ - -#define DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_GDMA_BASE + 0x198) - -/* DMA_OUT_REMAIN_UNDER_4B_CH1 : RO; bitpos: [26]; default: 1; - * reserved - */ - -#define DMA_OUT_REMAIN_UNDER_4B_CH1 (BIT(26)) -#define DMA_OUT_REMAIN_UNDER_4B_CH1_M (DMA_OUT_REMAIN_UNDER_4B_CH1_V << DMA_OUT_REMAIN_UNDER_4B_CH1_S) -#define DMA_OUT_REMAIN_UNDER_4B_CH1_V 0x00000001 -#define DMA_OUT_REMAIN_UNDER_4B_CH1_S 26 - -/* DMA_OUT_REMAIN_UNDER_3B_CH1 : RO; bitpos: [25]; default: 1; - * reserved - */ - -#define DMA_OUT_REMAIN_UNDER_3B_CH1 (BIT(25)) -#define DMA_OUT_REMAIN_UNDER_3B_CH1_M (DMA_OUT_REMAIN_UNDER_3B_CH1_V << DMA_OUT_REMAIN_UNDER_3B_CH1_S) -#define DMA_OUT_REMAIN_UNDER_3B_CH1_V 0x00000001 -#define DMA_OUT_REMAIN_UNDER_3B_CH1_S 25 - -/* DMA_OUT_REMAIN_UNDER_2B_CH1 : RO; bitpos: [24]; default: 1; - * reserved - */ - -#define DMA_OUT_REMAIN_UNDER_2B_CH1 (BIT(24)) -#define DMA_OUT_REMAIN_UNDER_2B_CH1_M (DMA_OUT_REMAIN_UNDER_2B_CH1_V << DMA_OUT_REMAIN_UNDER_2B_CH1_S) -#define DMA_OUT_REMAIN_UNDER_2B_CH1_V 0x00000001 -#define DMA_OUT_REMAIN_UNDER_2B_CH1_S 24 - -/* DMA_OUT_REMAIN_UNDER_1B_CH1 : RO; bitpos: [23]; default: 1; - * reserved - */ - -#define DMA_OUT_REMAIN_UNDER_1B_CH1 (BIT(23)) -#define DMA_OUT_REMAIN_UNDER_1B_CH1_M (DMA_OUT_REMAIN_UNDER_1B_CH1_V << DMA_OUT_REMAIN_UNDER_1B_CH1_S) -#define DMA_OUT_REMAIN_UNDER_1B_CH1_V 0x00000001 -#define DMA_OUT_REMAIN_UNDER_1B_CH1_S 23 - -/* DMA_OUTFIFO_CNT_CH1 : RO; bitpos: [7:2]; default: 0; - * The register stores the byte number of the data in L1 Tx FIFO for Tx - * channel 1. - */ - -#define DMA_OUTFIFO_CNT_CH1 0x0000003F -#define DMA_OUTFIFO_CNT_CH1_M (DMA_OUTFIFO_CNT_CH1_V << DMA_OUTFIFO_CNT_CH1_S) -#define DMA_OUTFIFO_CNT_CH1_V 0x0000003F -#define DMA_OUTFIFO_CNT_CH1_S 2 - -/* DMA_OUTFIFO_EMPTY_CH1 : RO; bitpos: [1]; default: 1; - * L1 Tx FIFO empty signal for Tx channel 1. - */ - -#define DMA_OUTFIFO_EMPTY_CH1 (BIT(1)) -#define DMA_OUTFIFO_EMPTY_CH1_M (DMA_OUTFIFO_EMPTY_CH1_V << DMA_OUTFIFO_EMPTY_CH1_S) -#define DMA_OUTFIFO_EMPTY_CH1_V 0x00000001 -#define DMA_OUTFIFO_EMPTY_CH1_S 1 - -/* DMA_OUTFIFO_FULL_CH1 : RO; bitpos: [0]; default: 0; - * L1 Tx FIFO full signal for Tx channel 1. - */ - -#define DMA_OUTFIFO_FULL_CH1 (BIT(0)) -#define DMA_OUTFIFO_FULL_CH1_M (DMA_OUTFIFO_FULL_CH1_V << DMA_OUTFIFO_FULL_CH1_S) -#define DMA_OUTFIFO_FULL_CH1_V 0x00000001 -#define DMA_OUTFIFO_FULL_CH1_S 0 - -/* DMA_OUT_PUSH_CH1_REG register - * DMA_OUT_PUSH_CH1_REG. - */ - -#define DMA_OUT_PUSH_CH1_REG (DR_REG_GDMA_BASE + 0x19c) - -/* DMA_OUTFIFO_PUSH_CH1 : R/W/SC; bitpos: [9]; default: 0; - * Set this bit to push data into DMA FIFO. - */ - -#define DMA_OUTFIFO_PUSH_CH1 (BIT(9)) -#define DMA_OUTFIFO_PUSH_CH1_M (DMA_OUTFIFO_PUSH_CH1_V << DMA_OUTFIFO_PUSH_CH1_S) -#define DMA_OUTFIFO_PUSH_CH1_V 0x00000001 -#define DMA_OUTFIFO_PUSH_CH1_S 9 - -/* DMA_OUTFIFO_WDATA_CH1 : R/W; bitpos: [8:0]; default: 0; - * This register stores the data that need to be pushed into DMA FIFO. - */ - -#define DMA_OUTFIFO_WDATA_CH1 0x000001FF -#define DMA_OUTFIFO_WDATA_CH1_M (DMA_OUTFIFO_WDATA_CH1_V << DMA_OUTFIFO_WDATA_CH1_S) -#define DMA_OUTFIFO_WDATA_CH1_V 0x000001FF -#define DMA_OUTFIFO_WDATA_CH1_S 0 - -/* DMA_OUT_LINK_CH1_REG register - * DMA_OUT_LINK_CH1_REG. - */ - -#define DMA_OUT_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x1a0) - -/* DMA_OUTLINK_PARK_CH1 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink - * descriptor's FSM is working. - */ - -#define DMA_OUTLINK_PARK_CH1 (BIT(23)) -#define DMA_OUTLINK_PARK_CH1_M (DMA_OUTLINK_PARK_CH1_V << DMA_OUTLINK_PARK_CH1_S) -#define DMA_OUTLINK_PARK_CH1_V 0x00000001 -#define DMA_OUTLINK_PARK_CH1_S 23 - -/* DMA_OUTLINK_RESTART_CH1 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ - -#define DMA_OUTLINK_RESTART_CH1 (BIT(22)) -#define DMA_OUTLINK_RESTART_CH1_M (DMA_OUTLINK_RESTART_CH1_V << DMA_OUTLINK_RESTART_CH1_S) -#define DMA_OUTLINK_RESTART_CH1_V 0x00000001 -#define DMA_OUTLINK_RESTART_CH1_S 22 - -/* DMA_OUTLINK_START_CH1 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ - -#define DMA_OUTLINK_START_CH1 (BIT(21)) -#define DMA_OUTLINK_START_CH1_M (DMA_OUTLINK_START_CH1_V << DMA_OUTLINK_START_CH1_S) -#define DMA_OUTLINK_START_CH1_V 0x00000001 -#define DMA_OUTLINK_START_CH1_S 21 - -/* DMA_OUTLINK_STOP_CH1 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ - -#define DMA_OUTLINK_STOP_CH1 (BIT(20)) -#define DMA_OUTLINK_STOP_CH1_M (DMA_OUTLINK_STOP_CH1_V << DMA_OUTLINK_STOP_CH1_S) -#define DMA_OUTLINK_STOP_CH1_V 0x00000001 -#define DMA_OUTLINK_STOP_CH1_S 20 - -/* DMA_OUTLINK_ADDR_CH1 : R/W; bitpos: [19:0]; default: 0; - * This register stores the 20 least significant bits of the first outlink - * descriptor's address. - */ - -#define DMA_OUTLINK_ADDR_CH1 0x000FFFFF -#define DMA_OUTLINK_ADDR_CH1_M (DMA_OUTLINK_ADDR_CH1_V << DMA_OUTLINK_ADDR_CH1_S) -#define DMA_OUTLINK_ADDR_CH1_V 0x000FFFFF -#define DMA_OUTLINK_ADDR_CH1_S 0 - -/* DMA_OUT_STATE_CH1_REG register - * DMA_OUT_STATE_CH1_REG. - */ - -#define DMA_OUT_STATE_CH1_REG (DR_REG_GDMA_BASE + 0x1a4) - -/* DMA_OUT_STATE_CH1 : RO; bitpos: [22:20]; default: 0; - * reserved - */ - -#define DMA_OUT_STATE_CH1 0x00000007 -#define DMA_OUT_STATE_CH1_M (DMA_OUT_STATE_CH1_V << DMA_OUT_STATE_CH1_S) -#define DMA_OUT_STATE_CH1_V 0x00000007 -#define DMA_OUT_STATE_CH1_S 20 - -/* DMA_OUT_DSCR_STATE_CH1 : RO; bitpos: [19:18]; default: 0; - * reserved - */ - -#define DMA_OUT_DSCR_STATE_CH1 0x00000003 -#define DMA_OUT_DSCR_STATE_CH1_M (DMA_OUT_DSCR_STATE_CH1_V << DMA_OUT_DSCR_STATE_CH1_S) -#define DMA_OUT_DSCR_STATE_CH1_V 0x00000003 -#define DMA_OUT_DSCR_STATE_CH1_S 18 - -/* DMA_OUTLINK_DSCR_ADDR_CH1 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ - -#define DMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFF -#define DMA_OUTLINK_DSCR_ADDR_CH1_M (DMA_OUTLINK_DSCR_ADDR_CH1_V << DMA_OUTLINK_DSCR_ADDR_CH1_S) -#define DMA_OUTLINK_DSCR_ADDR_CH1_V 0x0003FFFF -#define DMA_OUTLINK_DSCR_ADDR_CH1_S 0 - -/* DMA_OUT_EOF_DES_ADDR_CH1_REG register - * DMA_OUT_EOF_DES_ADDR_CH1_REG. - */ - -#define DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1a8) - -/* DMA_OUT_EOF_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF - * bit in this descriptor is 1. - */ - -#define DMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFF -#define DMA_OUT_EOF_DES_ADDR_CH1_M (DMA_OUT_EOF_DES_ADDR_CH1_V << DMA_OUT_EOF_DES_ADDR_CH1_S) -#define DMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFF -#define DMA_OUT_EOF_DES_ADDR_CH1_S 0 - -/* DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG register - * DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG. - */ - -#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x1ac) - -/* DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor before the - * last outlink descriptor. - */ - -#define DMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFF -#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_M (DMA_OUT_EOF_BFR_DES_ADDR_CH1_V << DMA_OUT_EOF_BFR_DES_ADDR_CH1_S) -#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFF -#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 - -/* DMA_OUT_DSCR_CH1_REG register - * DMA_OUT_DSCR_CH1_REG. - */ - -#define DMA_OUT_DSCR_CH1_REG (DR_REG_GDMA_BASE + 0x1b0) - -/* DMA_OUTLINK_DSCR_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the current outlink descriptor y. - */ - -#define DMA_OUTLINK_DSCR_CH1 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_CH1_M (DMA_OUTLINK_DSCR_CH1_V << DMA_OUTLINK_DSCR_CH1_S) -#define DMA_OUTLINK_DSCR_CH1_V 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_CH1_S 0 - -/* DMA_OUT_DSCR_BF0_CH1_REG register - * DMA_OUT_DSCR_BF0_CH1_REG. - */ - -#define DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_GDMA_BASE + 0x1b4) - -/* DMA_OUTLINK_DSCR_BF0_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor y-1. - */ - -#define DMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF0_CH1_M (DMA_OUTLINK_DSCR_BF0_CH1_V << DMA_OUTLINK_DSCR_BF0_CH1_S) -#define DMA_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF0_CH1_S 0 - -/* DMA_OUT_DSCR_BF1_CH1_REG register - * DMA_OUT_DSCR_BF1_CH1_REG. - */ - -#define DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_GDMA_BASE + 0x1b8) - -/* DMA_OUTLINK_DSCR_BF1_CH1 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor x-2. - */ - -#define DMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF1_CH1_M (DMA_OUTLINK_DSCR_BF1_CH1_V << DMA_OUTLINK_DSCR_BF1_CH1_S) -#define DMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF1_CH1_S 0 - -/* DMA_OUT_PRI_CH1_REG register - * DMA_OUT_PRI_CH1_REG. - */ - -#define DMA_OUT_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x1bc) - -/* DMA_TX_PRI_CH1 : R/W; bitpos: [3:0]; default: 0; - * The priority of Tx channel 1. The larger of the value, the higher of the - * priority. - */ - -#define DMA_TX_PRI_CH1 0x0000000F -#define DMA_TX_PRI_CH1_M (DMA_TX_PRI_CH1_V << DMA_TX_PRI_CH1_S) -#define DMA_TX_PRI_CH1_V 0x0000000F -#define DMA_TX_PRI_CH1_S 0 - -/* DMA_OUT_PERI_SEL_CH1_REG register - * DMA_OUT_PERI_SEL_CH1_REG. - */ - -#define DMA_OUT_PERI_SEL_CH1_REG (DR_REG_GDMA_BASE + 0x1c0) - -/* DMA_PERI_OUT_SEL_CH1 : R/W; bitpos: [5:0]; default: 63; - * This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: - * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: - * ADC_DAC. - */ - -#define DMA_PERI_OUT_SEL_CH1 0x0000003F -#define DMA_PERI_OUT_SEL_CH1_M (DMA_PERI_OUT_SEL_CH1_V << DMA_PERI_OUT_SEL_CH1_S) -#define DMA_PERI_OUT_SEL_CH1_V 0x0000003F -#define DMA_PERI_OUT_SEL_CH1_S 0 - -/* DMA_IN_CONF0_CH2_REG register - * DMA_IN_CONF0_CH2_REG. - */ - -#define DMA_IN_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x1f0) - -/* DMA_MEM_TRANS_EN_CH2 : R/W; bitpos: [4]; default: 0; - * Set this bit 1 to enable automatic transmitting data from memory to - * memory via DMA. - */ - -#define DMA_MEM_TRANS_EN_CH2 (BIT(4)) -#define DMA_MEM_TRANS_EN_CH2_M (DMA_MEM_TRANS_EN_CH2_V << DMA_MEM_TRANS_EN_CH2_S) -#define DMA_MEM_TRANS_EN_CH2_V 0x00000001 -#define DMA_MEM_TRANS_EN_CH2_S 4 - -/* DMA_IN_DATA_BURST_EN_CH2 : R/W; bitpos: [3]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 - * receiving data when accessing internal SRAM. - */ - -#define DMA_IN_DATA_BURST_EN_CH2 (BIT(3)) -#define DMA_IN_DATA_BURST_EN_CH2_M (DMA_IN_DATA_BURST_EN_CH2_V << DMA_IN_DATA_BURST_EN_CH2_S) -#define DMA_IN_DATA_BURST_EN_CH2_V 0x00000001 -#define DMA_IN_DATA_BURST_EN_CH2_S 3 - -/* DMA_INDSCR_BURST_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading - * link descriptor when accessing internal SRAM. - */ - -#define DMA_INDSCR_BURST_EN_CH2 (BIT(2)) -#define DMA_INDSCR_BURST_EN_CH2_M (DMA_INDSCR_BURST_EN_CH2_V << DMA_INDSCR_BURST_EN_CH2_S) -#define DMA_INDSCR_BURST_EN_CH2_V 0x00000001 -#define DMA_INDSCR_BURST_EN_CH2_S 2 - -/* DMA_IN_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; - * reserved - */ - -#define DMA_IN_LOOP_TEST_CH2 (BIT(1)) -#define DMA_IN_LOOP_TEST_CH2_M (DMA_IN_LOOP_TEST_CH2_V << DMA_IN_LOOP_TEST_CH2_S) -#define DMA_IN_LOOP_TEST_CH2_V 0x00000001 -#define DMA_IN_LOOP_TEST_CH2_S 1 - -/* DMA_IN_RST_CH2 : R/W; bitpos: [0]; default: 0; - * This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer. - */ - -#define DMA_IN_RST_CH2 (BIT(0)) -#define DMA_IN_RST_CH2_M (DMA_IN_RST_CH2_V << DMA_IN_RST_CH2_S) -#define DMA_IN_RST_CH2_V 0x00000001 -#define DMA_IN_RST_CH2_S 0 - -/* DMA_IN_CONF1_CH2_REG register - * DMA_IN_CONF1_CH2_REG. - */ - -#define DMA_IN_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x1f4) - -/* DMA_IN_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; - * Set this bit to enable checking the owner attribute of the link - * descriptor. - */ - -#define DMA_IN_CHECK_OWNER_CH2 (BIT(12)) -#define DMA_IN_CHECK_OWNER_CH2_M (DMA_IN_CHECK_OWNER_CH2_V << DMA_IN_CHECK_OWNER_CH2_S) -#define DMA_IN_CHECK_OWNER_CH2_V 0x00000001 -#define DMA_IN_CHECK_OWNER_CH2_S 12 - -/* DMA_INFIFO_STATUS_CH2_REG register - * DMA_INFIFO_STATUS_CH2_REG. - */ - -#define DMA_INFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x1f8) - -/* DMA_IN_BUF_HUNGRY_CH2 : RO; bitpos: [27]; default: 0; - * reserved - */ - -#define DMA_IN_BUF_HUNGRY_CH2 (BIT(27)) -#define DMA_IN_BUF_HUNGRY_CH2_M (DMA_IN_BUF_HUNGRY_CH2_V << DMA_IN_BUF_HUNGRY_CH2_S) -#define DMA_IN_BUF_HUNGRY_CH2_V 0x00000001 -#define DMA_IN_BUF_HUNGRY_CH2_S 27 - -/* DMA_IN_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; - * reserved - */ - -#define DMA_IN_REMAIN_UNDER_4B_CH2 (BIT(26)) -#define DMA_IN_REMAIN_UNDER_4B_CH2_M (DMA_IN_REMAIN_UNDER_4B_CH2_V << DMA_IN_REMAIN_UNDER_4B_CH2_S) -#define DMA_IN_REMAIN_UNDER_4B_CH2_V 0x00000001 -#define DMA_IN_REMAIN_UNDER_4B_CH2_S 26 - -/* DMA_IN_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; - * reserved - */ - -#define DMA_IN_REMAIN_UNDER_3B_CH2 (BIT(25)) -#define DMA_IN_REMAIN_UNDER_3B_CH2_M (DMA_IN_REMAIN_UNDER_3B_CH2_V << DMA_IN_REMAIN_UNDER_3B_CH2_S) -#define DMA_IN_REMAIN_UNDER_3B_CH2_V 0x00000001 -#define DMA_IN_REMAIN_UNDER_3B_CH2_S 25 - -/* DMA_IN_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; - * reserved - */ - -#define DMA_IN_REMAIN_UNDER_2B_CH2 (BIT(24)) -#define DMA_IN_REMAIN_UNDER_2B_CH2_M (DMA_IN_REMAIN_UNDER_2B_CH2_V << DMA_IN_REMAIN_UNDER_2B_CH2_S) -#define DMA_IN_REMAIN_UNDER_2B_CH2_V 0x00000001 -#define DMA_IN_REMAIN_UNDER_2B_CH2_S 24 - -/* DMA_IN_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; - * reserved - */ - -#define DMA_IN_REMAIN_UNDER_1B_CH2 (BIT(23)) -#define DMA_IN_REMAIN_UNDER_1B_CH2_M (DMA_IN_REMAIN_UNDER_1B_CH2_V << DMA_IN_REMAIN_UNDER_1B_CH2_S) -#define DMA_IN_REMAIN_UNDER_1B_CH2_V 0x00000001 -#define DMA_IN_REMAIN_UNDER_1B_CH2_S 23 - -/* DMA_INFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; - * The register stores the byte number of the data in L1 Rx FIFO for Rx - * channel 2. - */ - -#define DMA_INFIFO_CNT_CH2 0x0000003F -#define DMA_INFIFO_CNT_CH2_M (DMA_INFIFO_CNT_CH2_V << DMA_INFIFO_CNT_CH2_S) -#define DMA_INFIFO_CNT_CH2_V 0x0000003F -#define DMA_INFIFO_CNT_CH2_S 2 - -/* DMA_INFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; - * L1 Rx FIFO empty signal for Rx channel 2. - */ - -#define DMA_INFIFO_EMPTY_CH2 (BIT(1)) -#define DMA_INFIFO_EMPTY_CH2_M (DMA_INFIFO_EMPTY_CH2_V << DMA_INFIFO_EMPTY_CH2_S) -#define DMA_INFIFO_EMPTY_CH2_V 0x00000001 -#define DMA_INFIFO_EMPTY_CH2_S 1 - -/* DMA_INFIFO_FULL_CH2 : RO; bitpos: [0]; default: 1; - * L1 Rx FIFO full signal for Rx channel 2. - */ - -#define DMA_INFIFO_FULL_CH2 (BIT(0)) -#define DMA_INFIFO_FULL_CH2_M (DMA_INFIFO_FULL_CH2_V << DMA_INFIFO_FULL_CH2_S) -#define DMA_INFIFO_FULL_CH2_V 0x00000001 -#define DMA_INFIFO_FULL_CH2_S 0 - -/* DMA_IN_POP_CH2_REG register - * DMA_IN_POP_CH2_REG. - */ - -#define DMA_IN_POP_CH2_REG (DR_REG_GDMA_BASE + 0x1fc) - -/* DMA_INFIFO_POP_CH2 : R/W/SC; bitpos: [12]; default: 0; - * Set this bit to pop data from DMA FIFO. - */ - -#define DMA_INFIFO_POP_CH2 (BIT(12)) -#define DMA_INFIFO_POP_CH2_M (DMA_INFIFO_POP_CH2_V << DMA_INFIFO_POP_CH2_S) -#define DMA_INFIFO_POP_CH2_V 0x00000001 -#define DMA_INFIFO_POP_CH2_S 12 - -/* DMA_INFIFO_RDATA_CH2 : RO; bitpos: [11:0]; default: 2048; - * This register stores the data popping from DMA FIFO. - */ - -#define DMA_INFIFO_RDATA_CH2 0x00000FFF -#define DMA_INFIFO_RDATA_CH2_M (DMA_INFIFO_RDATA_CH2_V << DMA_INFIFO_RDATA_CH2_S) -#define DMA_INFIFO_RDATA_CH2_V 0x00000FFF -#define DMA_INFIFO_RDATA_CH2_S 0 - -/* DMA_IN_LINK_CH2_REG register - * DMA_IN_LINK_CH2_REG. - */ - -#define DMA_IN_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x200) - -/* DMA_INLINK_PARK_CH2 : RO; bitpos: [24]; default: 1; - * 1: the inlink descriptor's FSM is in idle state. 0: the inlink - * descriptor's FSM is working. - */ - -#define DMA_INLINK_PARK_CH2 (BIT(24)) -#define DMA_INLINK_PARK_CH2_M (DMA_INLINK_PARK_CH2_V << DMA_INLINK_PARK_CH2_S) -#define DMA_INLINK_PARK_CH2_V 0x00000001 -#define DMA_INLINK_PARK_CH2_S 24 - -/* DMA_INLINK_RESTART_CH2 : R/W/SC; bitpos: [23]; default: 0; - * Set this bit to mount a new inlink descriptor. - */ - -#define DMA_INLINK_RESTART_CH2 (BIT(23)) -#define DMA_INLINK_RESTART_CH2_M (DMA_INLINK_RESTART_CH2_V << DMA_INLINK_RESTART_CH2_S) -#define DMA_INLINK_RESTART_CH2_V 0x00000001 -#define DMA_INLINK_RESTART_CH2_S 23 - -/* DMA_INLINK_START_CH2 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to start dealing with the inlink descriptors. - */ - -#define DMA_INLINK_START_CH2 (BIT(22)) -#define DMA_INLINK_START_CH2_M (DMA_INLINK_START_CH2_V << DMA_INLINK_START_CH2_S) -#define DMA_INLINK_START_CH2_V 0x00000001 -#define DMA_INLINK_START_CH2_S 22 - -/* DMA_INLINK_STOP_CH2 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to stop dealing with the inlink descriptors. - */ - -#define DMA_INLINK_STOP_CH2 (BIT(21)) -#define DMA_INLINK_STOP_CH2_M (DMA_INLINK_STOP_CH2_V << DMA_INLINK_STOP_CH2_S) -#define DMA_INLINK_STOP_CH2_V 0x00000001 -#define DMA_INLINK_STOP_CH2_S 21 - -/* DMA_INLINK_AUTO_RET_CH2 : R/W; bitpos: [20]; default: 1; - * Set this bit to return to current inlink descriptor's address, when there - * are some errors in current receiving data. - */ - -#define DMA_INLINK_AUTO_RET_CH2 (BIT(20)) -#define DMA_INLINK_AUTO_RET_CH2_M (DMA_INLINK_AUTO_RET_CH2_V << DMA_INLINK_AUTO_RET_CH2_S) -#define DMA_INLINK_AUTO_RET_CH2_V 0x00000001 -#define DMA_INLINK_AUTO_RET_CH2_S 20 - -/* DMA_INLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0; - * This register stores the 20 least significant bits of the first inlink - * descriptor's address. - */ - -#define DMA_INLINK_ADDR_CH2 0x000FFFFF -#define DMA_INLINK_ADDR_CH2_M (DMA_INLINK_ADDR_CH2_V << DMA_INLINK_ADDR_CH2_S) -#define DMA_INLINK_ADDR_CH2_V 0x000FFFFF -#define DMA_INLINK_ADDR_CH2_S 0 - -/* DMA_IN_STATE_CH2_REG register - * DMA_IN_STATE_CH2_REG. - */ - -#define DMA_IN_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x204) - -/* DMA_IN_STATE_CH2 : RO; bitpos: [22:20]; default: 0; - * reserved - */ - -#define DMA_IN_STATE_CH2 0x00000007 -#define DMA_IN_STATE_CH2_M (DMA_IN_STATE_CH2_V << DMA_IN_STATE_CH2_S) -#define DMA_IN_STATE_CH2_V 0x00000007 -#define DMA_IN_STATE_CH2_S 20 - -/* DMA_IN_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; - * reserved - */ - -#define DMA_IN_DSCR_STATE_CH2 0x00000003 -#define DMA_IN_DSCR_STATE_CH2_M (DMA_IN_DSCR_STATE_CH2_V << DMA_IN_DSCR_STATE_CH2_S) -#define DMA_IN_DSCR_STATE_CH2_V 0x00000003 -#define DMA_IN_DSCR_STATE_CH2_S 18 - -/* DMA_INLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; - * This register stores the current inlink descriptor's address. - */ - -#define DMA_INLINK_DSCR_ADDR_CH2 0x0003FFFF -#define DMA_INLINK_DSCR_ADDR_CH2_M (DMA_INLINK_DSCR_ADDR_CH2_V << DMA_INLINK_DSCR_ADDR_CH2_S) -#define DMA_INLINK_DSCR_ADDR_CH2_V 0x0003FFFF -#define DMA_INLINK_DSCR_ADDR_CH2_S 0 - -/* DMA_IN_SUC_EOF_DES_ADDR_CH2_REG register - * DMA_IN_SUC_EOF_DES_ADDR_CH2_REG. - */ - -#define DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x208) - -/* DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when the EOF - * bit in this descriptor is 1. - */ - -#define DMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFF -#define DMA_IN_SUC_EOF_DES_ADDR_CH2_M (DMA_IN_SUC_EOF_DES_ADDR_CH2_V << DMA_IN_SUC_EOF_DES_ADDR_CH2_S) -#define DMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFF -#define DMA_IN_SUC_EOF_DES_ADDR_CH2_S 0 - -/* DMA_IN_ERR_EOF_DES_ADDR_CH2_REG register - * DMA_IN_ERR_EOF_DES_ADDR_CH2_REG. - */ - -#define DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x20c) - -/* DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the inlink descriptor when there are - * some errors in current receiving data. Only used when peripheral is UHCI0. - */ - -#define DMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFF -#define DMA_IN_ERR_EOF_DES_ADDR_CH2_M (DMA_IN_ERR_EOF_DES_ADDR_CH2_V << DMA_IN_ERR_EOF_DES_ADDR_CH2_S) -#define DMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFF -#define DMA_IN_ERR_EOF_DES_ADDR_CH2_S 0 - -/* DMA_IN_DSCR_CH2_REG register - * DMA_IN_DSCR_CH2_REG. - */ - -#define DMA_IN_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x210) - -/* DMA_INLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the current inlink descriptor x. - */ - -#define DMA_INLINK_DSCR_CH2 0xFFFFFFFF -#define DMA_INLINK_DSCR_CH2_M (DMA_INLINK_DSCR_CH2_V << DMA_INLINK_DSCR_CH2_S) -#define DMA_INLINK_DSCR_CH2_V 0xFFFFFFFF -#define DMA_INLINK_DSCR_CH2_S 0 - -/* DMA_IN_DSCR_BF0_CH2_REG register - * DMA_IN_DSCR_BF0_CH2_REG. - */ - -#define DMA_IN_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x214) - -/* DMA_INLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the last inlink descriptor x-1. - */ - -#define DMA_INLINK_DSCR_BF0_CH2 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF0_CH2_M (DMA_INLINK_DSCR_BF0_CH2_V << DMA_INLINK_DSCR_BF0_CH2_S) -#define DMA_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF0_CH2_S 0 - -/* DMA_IN_DSCR_BF1_CH2_REG register - * DMA_IN_DSCR_BF1_CH2_REG. - */ - -#define DMA_IN_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x218) - -/* DMA_INLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor x-2. - */ - -#define DMA_INLINK_DSCR_BF1_CH2 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF1_CH2_M (DMA_INLINK_DSCR_BF1_CH2_V << DMA_INLINK_DSCR_BF1_CH2_S) -#define DMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFF -#define DMA_INLINK_DSCR_BF1_CH2_S 0 - -/* DMA_IN_PRI_CH2_REG register - * DMA_IN_PRI_CH2_REG. - */ - -#define DMA_IN_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x21c) - -/* DMA_RX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; - * The priority of Rx channel 2. The larger of the value, the higher of the - * priority. - */ - -#define DMA_RX_PRI_CH2 0x0000000F -#define DMA_RX_PRI_CH2_M (DMA_RX_PRI_CH2_V << DMA_RX_PRI_CH2_S) -#define DMA_RX_PRI_CH2_V 0x0000000F -#define DMA_RX_PRI_CH2_S 0 - -/* DMA_IN_PERI_SEL_CH2_REG register - * DMA_IN_PERI_SEL_CH2_REG. - */ - -#define DMA_IN_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x220) - -/* DMA_PERI_IN_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; - * This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: - * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: - * ADC_DAC. - */ - -#define DMA_PERI_IN_SEL_CH2 0x0000003F -#define DMA_PERI_IN_SEL_CH2_M (DMA_PERI_IN_SEL_CH2_V << DMA_PERI_IN_SEL_CH2_S) -#define DMA_PERI_IN_SEL_CH2_V 0x0000003F -#define DMA_PERI_IN_SEL_CH2_S 0 - -/* DMA_OUT_CONF0_CH2_REG register - * DMA_OUT_CONF0_CH2_REG. - */ - -#define DMA_OUT_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x250) - -/* DMA_OUT_DATA_BURST_EN_CH2 : R/W; bitpos: [5]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 - * transmitting data when accessing internal SRAM. - */ - -#define DMA_OUT_DATA_BURST_EN_CH2 (BIT(5)) -#define DMA_OUT_DATA_BURST_EN_CH2_M (DMA_OUT_DATA_BURST_EN_CH2_V << DMA_OUT_DATA_BURST_EN_CH2_S) -#define DMA_OUT_DATA_BURST_EN_CH2_V 0x00000001 -#define DMA_OUT_DATA_BURST_EN_CH2_S 5 - -/* DMA_OUTDSCR_BURST_EN_CH2 : R/W; bitpos: [4]; default: 0; - * Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading - * link descriptor when accessing internal SRAM. - */ - -#define DMA_OUTDSCR_BURST_EN_CH2 (BIT(4)) -#define DMA_OUTDSCR_BURST_EN_CH2_M (DMA_OUTDSCR_BURST_EN_CH2_V << DMA_OUTDSCR_BURST_EN_CH2_S) -#define DMA_OUTDSCR_BURST_EN_CH2_V 0x00000001 -#define DMA_OUTDSCR_BURST_EN_CH2_S 4 - -/* DMA_OUT_EOF_MODE_CH2 : R/W; bitpos: [3]; default: 1; - * EOF flag generation mode when transmitting data. 1: EOF flag for Tx - * channel 2 is generated when data need to transmit has been popped from - * FIFO in DMA - */ - -#define DMA_OUT_EOF_MODE_CH2 (BIT(3)) -#define DMA_OUT_EOF_MODE_CH2_M (DMA_OUT_EOF_MODE_CH2_V << DMA_OUT_EOF_MODE_CH2_S) -#define DMA_OUT_EOF_MODE_CH2_V 0x00000001 -#define DMA_OUT_EOF_MODE_CH2_S 3 - -/* DMA_OUT_AUTO_WRBACK_CH2 : R/W; bitpos: [2]; default: 0; - * Set this bit to enable automatic outlink-writeback when all the data in - * tx buffer has been transmitted. - */ - -#define DMA_OUT_AUTO_WRBACK_CH2 (BIT(2)) -#define DMA_OUT_AUTO_WRBACK_CH2_M (DMA_OUT_AUTO_WRBACK_CH2_V << DMA_OUT_AUTO_WRBACK_CH2_S) -#define DMA_OUT_AUTO_WRBACK_CH2_V 0x00000001 -#define DMA_OUT_AUTO_WRBACK_CH2_S 2 - -/* DMA_OUT_LOOP_TEST_CH2 : R/W; bitpos: [1]; default: 0; - * reserved - */ - -#define DMA_OUT_LOOP_TEST_CH2 (BIT(1)) -#define DMA_OUT_LOOP_TEST_CH2_M (DMA_OUT_LOOP_TEST_CH2_V << DMA_OUT_LOOP_TEST_CH2_S) -#define DMA_OUT_LOOP_TEST_CH2_V 0x00000001 -#define DMA_OUT_LOOP_TEST_CH2_S 1 - -/* DMA_OUT_RST_CH2 : R/W; bitpos: [0]; default: 0; - * This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer. - */ - -#define DMA_OUT_RST_CH2 (BIT(0)) -#define DMA_OUT_RST_CH2_M (DMA_OUT_RST_CH2_V << DMA_OUT_RST_CH2_S) -#define DMA_OUT_RST_CH2_V 0x00000001 -#define DMA_OUT_RST_CH2_S 0 - -/* DMA_OUT_CONF1_CH2_REG register - * DMA_OUT_CONF1_CH2_REG. - */ - -#define DMA_OUT_CONF1_CH2_REG (DR_REG_GDMA_BASE + 0x254) - -/* DMA_OUT_CHECK_OWNER_CH2 : R/W; bitpos: [12]; default: 0; - * Set this bit to enable checking the owner attribute of the link - * descriptor. - */ - -#define DMA_OUT_CHECK_OWNER_CH2 (BIT(12)) -#define DMA_OUT_CHECK_OWNER_CH2_M (DMA_OUT_CHECK_OWNER_CH2_V << DMA_OUT_CHECK_OWNER_CH2_S) -#define DMA_OUT_CHECK_OWNER_CH2_V 0x00000001 -#define DMA_OUT_CHECK_OWNER_CH2_S 12 - -/* DMA_OUTFIFO_STATUS_CH2_REG register - * DMA_OUTFIFO_STATUS_CH2_REG. - */ - -#define DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_GDMA_BASE + 0x258) - -/* DMA_OUT_REMAIN_UNDER_4B_CH2 : RO; bitpos: [26]; default: 1; - * reserved - */ - -#define DMA_OUT_REMAIN_UNDER_4B_CH2 (BIT(26)) -#define DMA_OUT_REMAIN_UNDER_4B_CH2_M (DMA_OUT_REMAIN_UNDER_4B_CH2_V << DMA_OUT_REMAIN_UNDER_4B_CH2_S) -#define DMA_OUT_REMAIN_UNDER_4B_CH2_V 0x00000001 -#define DMA_OUT_REMAIN_UNDER_4B_CH2_S 26 - -/* DMA_OUT_REMAIN_UNDER_3B_CH2 : RO; bitpos: [25]; default: 1; - * reserved - */ - -#define DMA_OUT_REMAIN_UNDER_3B_CH2 (BIT(25)) -#define DMA_OUT_REMAIN_UNDER_3B_CH2_M (DMA_OUT_REMAIN_UNDER_3B_CH2_V << DMA_OUT_REMAIN_UNDER_3B_CH2_S) -#define DMA_OUT_REMAIN_UNDER_3B_CH2_V 0x00000001 -#define DMA_OUT_REMAIN_UNDER_3B_CH2_S 25 - -/* DMA_OUT_REMAIN_UNDER_2B_CH2 : RO; bitpos: [24]; default: 1; - * reserved - */ - -#define DMA_OUT_REMAIN_UNDER_2B_CH2 (BIT(24)) -#define DMA_OUT_REMAIN_UNDER_2B_CH2_M (DMA_OUT_REMAIN_UNDER_2B_CH2_V << DMA_OUT_REMAIN_UNDER_2B_CH2_S) -#define DMA_OUT_REMAIN_UNDER_2B_CH2_V 0x00000001 -#define DMA_OUT_REMAIN_UNDER_2B_CH2_S 24 - -/* DMA_OUT_REMAIN_UNDER_1B_CH2 : RO; bitpos: [23]; default: 1; - * reserved - */ - -#define DMA_OUT_REMAIN_UNDER_1B_CH2 (BIT(23)) -#define DMA_OUT_REMAIN_UNDER_1B_CH2_M (DMA_OUT_REMAIN_UNDER_1B_CH2_V << DMA_OUT_REMAIN_UNDER_1B_CH2_S) -#define DMA_OUT_REMAIN_UNDER_1B_CH2_V 0x00000001 -#define DMA_OUT_REMAIN_UNDER_1B_CH2_S 23 - -/* DMA_OUTFIFO_CNT_CH2 : RO; bitpos: [7:2]; default: 0; - * The register stores the byte number of the data in L1 Tx FIFO for Tx - * channel 2. - */ - -#define DMA_OUTFIFO_CNT_CH2 0x0000003F -#define DMA_OUTFIFO_CNT_CH2_M (DMA_OUTFIFO_CNT_CH2_V << DMA_OUTFIFO_CNT_CH2_S) -#define DMA_OUTFIFO_CNT_CH2_V 0x0000003F -#define DMA_OUTFIFO_CNT_CH2_S 2 - -/* DMA_OUTFIFO_EMPTY_CH2 : RO; bitpos: [1]; default: 1; - * L1 Tx FIFO empty signal for Tx channel 2. - */ - -#define DMA_OUTFIFO_EMPTY_CH2 (BIT(1)) -#define DMA_OUTFIFO_EMPTY_CH2_M (DMA_OUTFIFO_EMPTY_CH2_V << DMA_OUTFIFO_EMPTY_CH2_S) -#define DMA_OUTFIFO_EMPTY_CH2_V 0x00000001 -#define DMA_OUTFIFO_EMPTY_CH2_S 1 - -/* DMA_OUTFIFO_FULL_CH2 : RO; bitpos: [0]; default: 0; - * L1 Tx FIFO full signal for Tx channel 2. - */ - -#define DMA_OUTFIFO_FULL_CH2 (BIT(0)) -#define DMA_OUTFIFO_FULL_CH2_M (DMA_OUTFIFO_FULL_CH2_V << DMA_OUTFIFO_FULL_CH2_S) -#define DMA_OUTFIFO_FULL_CH2_V 0x00000001 -#define DMA_OUTFIFO_FULL_CH2_S 0 - -/* DMA_OUT_PUSH_CH2_REG register - * DMA_OUT_PUSH_CH2_REG. - */ - -#define DMA_OUT_PUSH_CH2_REG (DR_REG_GDMA_BASE + 0x25c) - -/* DMA_OUTFIFO_PUSH_CH2 : R/W/SC; bitpos: [9]; default: 0; - * Set this bit to push data into DMA FIFO. - */ - -#define DMA_OUTFIFO_PUSH_CH2 (BIT(9)) -#define DMA_OUTFIFO_PUSH_CH2_M (DMA_OUTFIFO_PUSH_CH2_V << DMA_OUTFIFO_PUSH_CH2_S) -#define DMA_OUTFIFO_PUSH_CH2_V 0x00000001 -#define DMA_OUTFIFO_PUSH_CH2_S 9 - -/* DMA_OUTFIFO_WDATA_CH2 : R/W; bitpos: [8:0]; default: 0; - * This register stores the data that need to be pushed into DMA FIFO. - */ - -#define DMA_OUTFIFO_WDATA_CH2 0x000001FF -#define DMA_OUTFIFO_WDATA_CH2_M (DMA_OUTFIFO_WDATA_CH2_V << DMA_OUTFIFO_WDATA_CH2_S) -#define DMA_OUTFIFO_WDATA_CH2_V 0x000001FF -#define DMA_OUTFIFO_WDATA_CH2_S 0 - -/* DMA_OUT_LINK_CH2_REG register - * DMA_OUT_LINK_CH2_REG. - */ - -#define DMA_OUT_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x260) - -/* DMA_OUTLINK_PARK_CH2 : RO; bitpos: [23]; default: 1; - * 1: the outlink descriptor's FSM is in idle state. 0: the outlink - * descriptor's FSM is working. - */ - -#define DMA_OUTLINK_PARK_CH2 (BIT(23)) -#define DMA_OUTLINK_PARK_CH2_M (DMA_OUTLINK_PARK_CH2_V << DMA_OUTLINK_PARK_CH2_S) -#define DMA_OUTLINK_PARK_CH2_V 0x00000001 -#define DMA_OUTLINK_PARK_CH2_S 23 - -/* DMA_OUTLINK_RESTART_CH2 : R/W/SC; bitpos: [22]; default: 0; - * Set this bit to restart a new outlink from the last address. - */ - -#define DMA_OUTLINK_RESTART_CH2 (BIT(22)) -#define DMA_OUTLINK_RESTART_CH2_M (DMA_OUTLINK_RESTART_CH2_V << DMA_OUTLINK_RESTART_CH2_S) -#define DMA_OUTLINK_RESTART_CH2_V 0x00000001 -#define DMA_OUTLINK_RESTART_CH2_S 22 - -/* DMA_OUTLINK_START_CH2 : R/W/SC; bitpos: [21]; default: 0; - * Set this bit to start dealing with the outlink descriptors. - */ - -#define DMA_OUTLINK_START_CH2 (BIT(21)) -#define DMA_OUTLINK_START_CH2_M (DMA_OUTLINK_START_CH2_V << DMA_OUTLINK_START_CH2_S) -#define DMA_OUTLINK_START_CH2_V 0x00000001 -#define DMA_OUTLINK_START_CH2_S 21 - -/* DMA_OUTLINK_STOP_CH2 : R/W/SC; bitpos: [20]; default: 0; - * Set this bit to stop dealing with the outlink descriptors. - */ - -#define DMA_OUTLINK_STOP_CH2 (BIT(20)) -#define DMA_OUTLINK_STOP_CH2_M (DMA_OUTLINK_STOP_CH2_V << DMA_OUTLINK_STOP_CH2_S) -#define DMA_OUTLINK_STOP_CH2_V 0x00000001 -#define DMA_OUTLINK_STOP_CH2_S 20 - -/* DMA_OUTLINK_ADDR_CH2 : R/W; bitpos: [19:0]; default: 0; - * This register stores the 20 least significant bits of the first outlink - * descriptor's address. - */ - -#define DMA_OUTLINK_ADDR_CH2 0x000FFFFF -#define DMA_OUTLINK_ADDR_CH2_M (DMA_OUTLINK_ADDR_CH2_V << DMA_OUTLINK_ADDR_CH2_S) -#define DMA_OUTLINK_ADDR_CH2_V 0x000FFFFF -#define DMA_OUTLINK_ADDR_CH2_S 0 - -/* DMA_OUT_STATE_CH2_REG register - * DMA_OUT_STATE_CH2_REG. - */ - -#define DMA_OUT_STATE_CH2_REG (DR_REG_GDMA_BASE + 0x264) - -/* DMA_OUT_STATE_CH2 : RO; bitpos: [22:20]; default: 0; - * reserved - */ - -#define DMA_OUT_STATE_CH2 0x00000007 -#define DMA_OUT_STATE_CH2_M (DMA_OUT_STATE_CH2_V << DMA_OUT_STATE_CH2_S) -#define DMA_OUT_STATE_CH2_V 0x00000007 -#define DMA_OUT_STATE_CH2_S 20 - -/* DMA_OUT_DSCR_STATE_CH2 : RO; bitpos: [19:18]; default: 0; - * reserved - */ - -#define DMA_OUT_DSCR_STATE_CH2 0x00000003 -#define DMA_OUT_DSCR_STATE_CH2_M (DMA_OUT_DSCR_STATE_CH2_V << DMA_OUT_DSCR_STATE_CH2_S) -#define DMA_OUT_DSCR_STATE_CH2_V 0x00000003 -#define DMA_OUT_DSCR_STATE_CH2_S 18 - -/* DMA_OUTLINK_DSCR_ADDR_CH2 : RO; bitpos: [17:0]; default: 0; - * This register stores the current outlink descriptor's address. - */ - -#define DMA_OUTLINK_DSCR_ADDR_CH2 0x0003FFFF -#define DMA_OUTLINK_DSCR_ADDR_CH2_M (DMA_OUTLINK_DSCR_ADDR_CH2_V << DMA_OUTLINK_DSCR_ADDR_CH2_S) -#define DMA_OUTLINK_DSCR_ADDR_CH2_V 0x0003FFFF -#define DMA_OUTLINK_DSCR_ADDR_CH2_S 0 - -/* DMA_OUT_EOF_DES_ADDR_CH2_REG register - * DMA_OUT_EOF_DES_ADDR_CH2_REG. - */ - -#define DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x268) - -/* DMA_OUT_EOF_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor when the EOF - * bit in this descriptor is 1. - */ - -#define DMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFF -#define DMA_OUT_EOF_DES_ADDR_CH2_M (DMA_OUT_EOF_DES_ADDR_CH2_V << DMA_OUT_EOF_DES_ADDR_CH2_S) -#define DMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFF -#define DMA_OUT_EOF_DES_ADDR_CH2_S 0 - -/* DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG register - * DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG. - */ - -#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x26c) - -/* DMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO; bitpos: [31:0]; default: 0; - * This register stores the address of the outlink descriptor before the - * last outlink descriptor. - */ - -#define DMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFF -#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_M (DMA_OUT_EOF_BFR_DES_ADDR_CH2_V << DMA_OUT_EOF_BFR_DES_ADDR_CH2_S) -#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFF -#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0 - -/* DMA_OUT_DSCR_CH2_REG register - * DMA_OUT_DSCR_CH2_REG. - */ - -#define DMA_OUT_DSCR_CH2_REG (DR_REG_GDMA_BASE + 0x270) - -/* DMA_OUTLINK_DSCR_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the current outlink descriptor y. - */ - -#define DMA_OUTLINK_DSCR_CH2 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_CH2_M (DMA_OUTLINK_DSCR_CH2_V << DMA_OUTLINK_DSCR_CH2_S) -#define DMA_OUTLINK_DSCR_CH2_V 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_CH2_S 0 - -/* DMA_OUT_DSCR_BF0_CH2_REG register - * DMA_OUT_DSCR_BF0_CH2_REG. - */ - -#define DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_GDMA_BASE + 0x274) - -/* DMA_OUTLINK_DSCR_BF0_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the last outlink descriptor y-1. - */ - -#define DMA_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF0_CH2_M (DMA_OUTLINK_DSCR_BF0_CH2_V << DMA_OUTLINK_DSCR_BF0_CH2_S) -#define DMA_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF0_CH2_S 0 - -/* DMA_OUT_DSCR_BF1_CH2_REG register - * DMA_OUT_DSCR_BF1_CH2_REG. - */ - -#define DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_GDMA_BASE + 0x278) - -/* DMA_OUTLINK_DSCR_BF1_CH2 : RO; bitpos: [31:0]; default: 0; - * The address of the second-to-last inlink descriptor x-2. - */ - -#define DMA_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF1_CH2_M (DMA_OUTLINK_DSCR_BF1_CH2_V << DMA_OUTLINK_DSCR_BF1_CH2_S) -#define DMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFF -#define DMA_OUTLINK_DSCR_BF1_CH2_S 0 - -/* DMA_OUT_PRI_CH2_REG register - * DMA_OUT_PRI_CH2_REG. - */ - -#define DMA_OUT_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x27c) - -/* DMA_TX_PRI_CH2 : R/W; bitpos: [3:0]; default: 0; - * The priority of Tx channel 2. The larger of the value, the higher of the - * priority. - */ - -#define DMA_TX_PRI_CH2 0x0000000F -#define DMA_TX_PRI_CH2_M (DMA_TX_PRI_CH2_V << DMA_TX_PRI_CH2_S) -#define DMA_TX_PRI_CH2_V 0x0000000F -#define DMA_TX_PRI_CH2_S 0 - -/* DMA_OUT_PERI_SEL_CH2_REG register - * DMA_OUT_PERI_SEL_CH2_REG. - */ - -#define DMA_OUT_PERI_SEL_CH2_REG (DR_REG_GDMA_BASE + 0x280) - -/* DMA_PERI_OUT_SEL_CH2 : R/W; bitpos: [5:0]; default: 63; - * This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: - * reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: - * ADC_DAC. - */ - -#define DMA_PERI_OUT_SEL_CH2 0x0000003F -#define DMA_PERI_OUT_SEL_CH2_M (DMA_PERI_OUT_SEL_CH2_V << DMA_PERI_OUT_SEL_CH2_S) -#define DMA_PERI_OUT_SEL_CH2_V 0x0000003F -#define DMA_PERI_OUT_SEL_CH2_S 0 - -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_DMA_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_efuse.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_efuse.h deleted file mode 100644 index ef92134a3d4b0..0000000000000 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_efuse.h +++ /dev/null @@ -1,3282 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_efuse.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_EFUSE_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_EFUSE_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32c3_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* EFUSE_PGM_DATA0_REG register - * Register 0 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) - -/* EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; - * The content of the 0th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_0 0xFFFFFFFF -#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) -#define EFUSE_PGM_DATA_0_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_0_S 0 - -/* EFUSE_PGM_DATA1_REG register - * Register 1 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) - -/* EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * The content of the 1th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_1 0xFFFFFFFF -#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) -#define EFUSE_PGM_DATA_1_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_1_S 0 - -/* EFUSE_PGM_DATA2_REG register - * Register 2 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) - -/* EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * The content of the 2th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_2 0xFFFFFFFF -#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) -#define EFUSE_PGM_DATA_2_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_2_S 0 - -/* EFUSE_PGM_DATA3_REG register - * Register 3 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) - -/* EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; - * The content of the 3th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_3 0xFFFFFFFF -#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) -#define EFUSE_PGM_DATA_3_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_3_S 0 - -/* EFUSE_PGM_DATA4_REG register - * Register 4 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) - -/* EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; - * The content of the 4th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_4 0xFFFFFFFF -#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) -#define EFUSE_PGM_DATA_4_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_4_S 0 - -/* EFUSE_PGM_DATA5_REG register - * Register 5 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) - -/* EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; - * The content of the 5th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_5 0xFFFFFFFF -#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) -#define EFUSE_PGM_DATA_5_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_5_S 0 - -/* EFUSE_PGM_DATA6_REG register - * Register 6 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) - -/* EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; - * The content of the 6th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_6 0xFFFFFFFF -#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) -#define EFUSE_PGM_DATA_6_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_6_S 0 - -/* EFUSE_PGM_DATA7_REG register - * Register 7 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) - -/* EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; - * The content of the 7th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_7 0xFFFFFFFF -#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) -#define EFUSE_PGM_DATA_7_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_7_S 0 - -/* EFUSE_PGM_CHECK_VALUE0_REG register - * Register 0 that stores the RS code to be programmed. - */ - -#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) - -/* EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; - * The content of the 0th 32-bit RS code to be programmed. - */ - -#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) -#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_0_S 0 - -/* EFUSE_PGM_CHECK_VALUE1_REG register - * Register 1 that stores the RS code to be programmed. - */ - -#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) - -/* EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * The content of the 1th 32-bit RS code to be programmed. - */ - -#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) -#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_1_S 0 - -/* EFUSE_PGM_CHECK_VALUE2_REG register - * Register 2 that stores the RS code to be programmed. - */ - -#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) - -/* EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * The content of the 2th 32-bit RS code to be programmed. - */ - -#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) -#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_2_S 0 - -/* EFUSE_RD_WR_DIS_REG register - * Register 0 of BLOCK0. - */ - -#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) - -/* EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; - * Disables programming of individual eFuses. - */ - -#define EFUSE_WR_DIS 0xFFFFFFFF -#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) -#define EFUSE_WR_DIS_V 0xFFFFFFFF -#define EFUSE_WR_DIS_S 0 - -/* EFUSE_RD_REPEAT_DATA0_REG register - * Register 1 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) - -/* EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; - * Disables software reading from individual eFuse blocks (BLOCK4-10). - */ - -#define EFUSE_RD_DIS 0x0000007F -#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) -#define EFUSE_RD_DIS_V 0x0000007F -#define EFUSE_RD_DIS_S 0 - -/* EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0; - * Set this bit to disable boot from RTC RAM. - */ - -#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_M (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S) -#define EFUSE_DIS_RTC_RAM_BOOT_V 0x00000001 -#define EFUSE_DIS_RTC_RAM_BOOT_S 7 - -/* EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; - * Set this bit to disable Icache. - */ - -#define EFUSE_DIS_ICACHE (BIT(8)) -#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) -#define EFUSE_DIS_ICACHE_V 0x00000001 -#define EFUSE_DIS_ICACHE_S 8 - -/* EFUSE_DIS_DCACHE : RO; bitpos: [9]; default: 0; - * Set this bit to disable Dcache. - */ - -#define EFUSE_DIS_DCACHE (BIT(9)) -#define EFUSE_DIS_DCACHE_M (EFUSE_DIS_DCACHE_V << EFUSE_DIS_DCACHE_S) -#define EFUSE_DIS_DCACHE_V 0x00000001 -#define EFUSE_DIS_DCACHE_S 9 - -/* EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0; - * Disables Icache when SoC is in Download mode. - */ - -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 - -/* EFUSE_DIS_DOWNLOAD_DCACHE : RO; bitpos: [11]; default: 0; - * Disables Dcache when SoC is in Download mode. - */ - -#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_M (EFUSE_DIS_DOWNLOAD_DCACHE_V << EFUSE_DIS_DOWNLOAD_DCACHE_S) -#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 - -/* EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; - * Set this bit to disable the function that forces chip into download mode. - */ - -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001 -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 - -/* EFUSE_DIS_USB : RO; bitpos: [13]; default: 0; - * Set this bit to disable USB function. - */ - -#define EFUSE_DIS_USB (BIT(13)) -#define EFUSE_DIS_USB_M (EFUSE_DIS_USB_V << EFUSE_DIS_USB_S) -#define EFUSE_DIS_USB_V 0x00000001 -#define EFUSE_DIS_USB_S 13 - -/* EFUSE_DIS_CAN : RO; bitpos: [14]; default: 0; - * Set this bit to disable CAN function. - */ - -#define EFUSE_DIS_CAN (BIT(14)) -#define EFUSE_DIS_CAN_M (EFUSE_DIS_CAN_V << EFUSE_DIS_CAN_S) -#define EFUSE_DIS_CAN_V 0x00000001 -#define EFUSE_DIS_CAN_S 14 - -/* EFUSE_DIS_BOOT_REMAP : RO; bitpos: [15]; default: 0; - * Disables capability to Remap RAM to ROM address space. - */ - -#define EFUSE_DIS_BOOT_REMAP (BIT(15)) -#define EFUSE_DIS_BOOT_REMAP_M (EFUSE_DIS_BOOT_REMAP_V << EFUSE_DIS_BOOT_REMAP_S) -#define EFUSE_DIS_BOOT_REMAP_V 0x00000001 -#define EFUSE_DIS_BOOT_REMAP_S 15 - -/* EFUSE_DIS_EFUSE_ATE_WR : RO; bitpos: [16]; default: 0; */ - -#define EFUSE_DIS_EFUSE_ATE_WR (BIT(16)) -#define EFUSE_DIS_EFUSE_ATE_WR_M (EFUSE_DIS_EFUSE_ATE_WR_V << EFUSE_DIS_EFUSE_ATE_WR_S) -#define EFUSE_DIS_EFUSE_ATE_WR_V 0x00000001 -#define EFUSE_DIS_EFUSE_ATE_WR_S 16 - -/* EFUSE_SOFT_DIS_JTAG : RO; bitpos: [17]; default: 0; - * Software disables JTAG. When software disabled, JTAG can be activated - * temporarily by HMAC peripheral. - */ - -#define EFUSE_SOFT_DIS_JTAG (BIT(17)) -#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) -#define EFUSE_SOFT_DIS_JTAG_V 0x00000001 -#define EFUSE_SOFT_DIS_JTAG_S 17 - -/* EFUSE_HARD_DIS_JTAG : RO; bitpos: [18]; default: 0; - * Hardware disables JTAG permanently. - */ - -#define EFUSE_HARD_DIS_JTAG (BIT(18)) -#define EFUSE_HARD_DIS_JTAG_M (EFUSE_HARD_DIS_JTAG_V << EFUSE_HARD_DIS_JTAG_S) -#define EFUSE_HARD_DIS_JTAG_V 0x00000001 -#define EFUSE_HARD_DIS_JTAG_S 18 - -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [19]; default: 0; - * Disables flash encryption when in download boot modes. - */ - -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(19)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 19 - -/* EFUSE_USB_DREFH : RO; bitpos: [21:20]; default: 0; - * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 - * mV, stored in eFuse. - */ - -#define EFUSE_USB_DREFH 0x00000003 -#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) -#define EFUSE_USB_DREFH_V 0x00000003 -#define EFUSE_USB_DREFH_S 20 - -/* EFUSE_USB_DREFL : RO; bitpos: [23:22]; default: 0; - * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of - * 80 mV, stored in eFuse. - */ - -#define EFUSE_USB_DREFL 0x00000003 -#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) -#define EFUSE_USB_DREFL_V 0x00000003 -#define EFUSE_USB_DREFL_S 22 - -/* EFUSE_USB_EXCHG_PINS : RO; bitpos: [24]; default: 0; - * Set this bit to exchange USB D+ and D- pins. - */ - -#define EFUSE_USB_EXCHG_PINS (BIT(24)) -#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) -#define EFUSE_USB_EXCHG_PINS_V 0x00000001 -#define EFUSE_USB_EXCHG_PINS_S 24 - -/* EFUSE_EXT_PHY_ENABLE : RO; bitpos: [25]; default: 0; - * Set this bit to enable external USB PHY. - */ - -#define EFUSE_EXT_PHY_ENABLE (BIT(25)) -#define EFUSE_EXT_PHY_ENABLE_M (EFUSE_EXT_PHY_ENABLE_V << EFUSE_EXT_PHY_ENABLE_S) -#define EFUSE_EXT_PHY_ENABLE_V 0x00000001 -#define EFUSE_EXT_PHY_ENABLE_S 25 - -/* EFUSE_USB_FORCE_NOPERSIST : RO; bitpos: [26]; default: 0; - * If set, forces USB BVALID to 1. - */ - -#define EFUSE_USB_FORCE_NOPERSIST (BIT(26)) -#define EFUSE_USB_FORCE_NOPERSIST_M (EFUSE_USB_FORCE_NOPERSIST_V << EFUSE_USB_FORCE_NOPERSIST_S) -#define EFUSE_USB_FORCE_NOPERSIST_V 0x00000001 -#define EFUSE_USB_FORCE_NOPERSIST_S 26 - -/* EFUSE_RPT4_RESERVED0 : RO; bitpos: [28:27]; default: 0; - * Reserved (used for four backups method). - */ - -#define EFUSE_RPT4_RESERVED0 0x00000003 -#define EFUSE_RPT4_RESERVED0_M (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S) -#define EFUSE_RPT4_RESERVED0_V 0x00000003 -#define EFUSE_RPT4_RESERVED0_S 27 - -/* EFUSE_VDD_SPI_MODECURLIM : RO; bitpos: [29]; default: 0; - * SPI regulator switches current limit mode. - */ - -#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_M (EFUSE_VDD_SPI_MODECURLIM_V << EFUSE_VDD_SPI_MODECURLIM_S) -#define EFUSE_VDD_SPI_MODECURLIM_V 0x00000001 -#define EFUSE_VDD_SPI_MODECURLIM_S 29 - -/* EFUSE_VDD_SPI_DREFH : RO; bitpos: [31:30]; default: 0; - * SPI regulator high voltage reference. - */ - -#define EFUSE_VDD_SPI_DREFH 0x00000003 -#define EFUSE_VDD_SPI_DREFH_M (EFUSE_VDD_SPI_DREFH_V << EFUSE_VDD_SPI_DREFH_S) -#define EFUSE_VDD_SPI_DREFH_V 0x00000003 -#define EFUSE_VDD_SPI_DREFH_S 30 - -/* EFUSE_RD_REPEAT_DATA1_REG register - * Register 2 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) - -/* EFUSE_VDD_SPI_DREFM : RO; bitpos: [1:0]; default: 0; - * SPI regulator medium voltage reference. - */ - -#define EFUSE_VDD_SPI_DREFM 0x00000003 -#define EFUSE_VDD_SPI_DREFM_M (EFUSE_VDD_SPI_DREFM_V << EFUSE_VDD_SPI_DREFM_S) -#define EFUSE_VDD_SPI_DREFM_V 0x00000003 -#define EFUSE_VDD_SPI_DREFM_S 0 - -/* EFUSE_VDD_SPI_DREFL : RO; bitpos: [3:2]; default: 0; - * SPI regulator low voltage reference. - */ - -#define EFUSE_VDD_SPI_DREFL 0x00000003 -#define EFUSE_VDD_SPI_DREFL_M (EFUSE_VDD_SPI_DREFL_V << EFUSE_VDD_SPI_DREFL_S) -#define EFUSE_VDD_SPI_DREFL_V 0x00000003 -#define EFUSE_VDD_SPI_DREFL_S 2 - -/* EFUSE_VDD_SPI_XPD : RO; bitpos: [4]; default: 0; - * If VDD_SPI_FORCE is 1, this value determines if the VDD_SPI regulator is - * powered on. - */ - -#define EFUSE_VDD_SPI_XPD (BIT(4)) -#define EFUSE_VDD_SPI_XPD_M (EFUSE_VDD_SPI_XPD_V << EFUSE_VDD_SPI_XPD_S) -#define EFUSE_VDD_SPI_XPD_V 0x00000001 -#define EFUSE_VDD_SPI_XPD_S 4 - -/* EFUSE_VDD_SPI_TIEH : RO; bitpos: [5]; default: 0; - * If VDD_SPI_FORCE is 1, determines VDD_SPI voltage. 0: VDD_SPI connects to - * 1.8 V LDO; 1: VDD_SPI connects to VDD_RTC_IO. - */ - -#define EFUSE_VDD_SPI_TIEH (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_M (EFUSE_VDD_SPI_TIEH_V << EFUSE_VDD_SPI_TIEH_S) -#define EFUSE_VDD_SPI_TIEH_V 0x00000001 -#define EFUSE_VDD_SPI_TIEH_S 5 - -/* EFUSE_VDD_SPI_FORCE : RO; bitpos: [6]; default: 0; - * Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI - * LDO. - */ - -#define EFUSE_VDD_SPI_FORCE (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_M (EFUSE_VDD_SPI_FORCE_V << EFUSE_VDD_SPI_FORCE_S) -#define EFUSE_VDD_SPI_FORCE_V 0x00000001 -#define EFUSE_VDD_SPI_FORCE_S 6 - -/* EFUSE_VDD_SPI_EN_INIT : RO; bitpos: [7]; default: 0; - * Set SPI regulator to 0 to configure init[1:0]=0. - */ - -#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_M (EFUSE_VDD_SPI_EN_INIT_V << EFUSE_VDD_SPI_EN_INIT_S) -#define EFUSE_VDD_SPI_EN_INIT_V 0x00000001 -#define EFUSE_VDD_SPI_EN_INIT_S 7 - -/* EFUSE_VDD_SPI_ENCURLIM : RO; bitpos: [8]; default: 0; - * Set SPI regulator to 1 to enable output current limit. - */ - -#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_M (EFUSE_VDD_SPI_ENCURLIM_V << EFUSE_VDD_SPI_ENCURLIM_S) -#define EFUSE_VDD_SPI_ENCURLIM_V 0x00000001 -#define EFUSE_VDD_SPI_ENCURLIM_S 8 - -/* EFUSE_VDD_SPI_DCURLIM : RO; bitpos: [11:9]; default: 0; - * Tunes the current limit threshold of SPI regulator when tieh=0, about 800 - * mA/(8+d). - */ - -#define EFUSE_VDD_SPI_DCURLIM 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_M (EFUSE_VDD_SPI_DCURLIM_V << EFUSE_VDD_SPI_DCURLIM_S) -#define EFUSE_VDD_SPI_DCURLIM_V 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_S 9 - -/* EFUSE_VDD_SPI_INIT : RO; bitpos: [13:12]; default: 0; - * Adds resistor from LDO output to ground. 0: no resistance; 1: 6 K; 2: 4 - * K; 3: 2 K. - */ - -#define EFUSE_VDD_SPI_INIT 0x00000003 -#define EFUSE_VDD_SPI_INIT_M (EFUSE_VDD_SPI_INIT_V << EFUSE_VDD_SPI_INIT_S) -#define EFUSE_VDD_SPI_INIT_V 0x00000003 -#define EFUSE_VDD_SPI_INIT_S 12 - -/* EFUSE_VDD_SPI_DCAP : RO; bitpos: [15:14]; default: 0; - * Prevents SPI regulator from overshoot. - */ - -#define EFUSE_VDD_SPI_DCAP 0x00000003 -#define EFUSE_VDD_SPI_DCAP_M (EFUSE_VDD_SPI_DCAP_V << EFUSE_VDD_SPI_DCAP_S) -#define EFUSE_VDD_SPI_DCAP_V 0x00000003 -#define EFUSE_VDD_SPI_DCAP_S 14 - -/* EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; - * Selects RTC watchdog timeout threshold at startup. 0: 40,000 slow clock - * cycles; 1: 80,000 slow clock cycles; 2: 160,000 slow clock cycles; 3: - * 320,000 slow clock cycles. - */ - -#define EFUSE_WDT_DELAY_SEL 0x00000003 -#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) -#define EFUSE_WDT_DELAY_SEL_V 0x00000003 -#define EFUSE_WDT_DELAY_SEL_S 16 - -/* EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; - * Enables encryption and decryption, when an SPI boot mode is set. Feature - * is enabled 1 or 3 bits are set in the eFuse, disabled otherwise. - */ - -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 - -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; - * If set, revokes use of secure boot key digest 0. - */ - -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 - -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; - * If set, revokes use of secure boot key digest 1. - */ - -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 - -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; - * If set, revokes use of secure boot key digest 2. - */ - -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 - -/* EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; - * Purpose of KEY0. Refer to Table Key Purpose Values. - */ - -#define EFUSE_KEY_PURPOSE_0 0x0000000F -#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) -#define EFUSE_KEY_PURPOSE_0_V 0x0000000F -#define EFUSE_KEY_PURPOSE_0_S 24 - -/* EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; - * Purpose of KEY1. Refer to Table Key Purpose Values. - */ - -#define EFUSE_KEY_PURPOSE_1 0x0000000F -#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) -#define EFUSE_KEY_PURPOSE_1_V 0x0000000F -#define EFUSE_KEY_PURPOSE_1_S 28 - -/* EFUSE_RD_REPEAT_DATA2_REG register - * Register 3 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) - -/* EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; - * Purpose of KEY2. Refer to Table Key Purpose Values. - */ - -#define EFUSE_KEY_PURPOSE_2 0x0000000F -#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) -#define EFUSE_KEY_PURPOSE_2_V 0x0000000F -#define EFUSE_KEY_PURPOSE_2_S 0 - -/* EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; - * Purpose of KEY3. Refer to Table Key Purpose Values. - */ - -#define EFUSE_KEY_PURPOSE_3 0x0000000F -#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) -#define EFUSE_KEY_PURPOSE_3_V 0x0000000F -#define EFUSE_KEY_PURPOSE_3_S 4 - -/* EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; - * Purpose of KEY4. Refer to Table Key Purpose Values. - */ - -#define EFUSE_KEY_PURPOSE_4 0x0000000F -#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) -#define EFUSE_KEY_PURPOSE_4_V 0x0000000F -#define EFUSE_KEY_PURPOSE_4_S 8 - -/* EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; - * Purpose of KEY5. Refer to Table Key Purpose Values. - */ - -#define EFUSE_KEY_PURPOSE_5 0x0000000F -#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) -#define EFUSE_KEY_PURPOSE_5_V 0x0000000F -#define EFUSE_KEY_PURPOSE_5_S 12 - -/* EFUSE_KEY_PURPOSE_6 : RO; bitpos: [19:16]; default: 0; - * Purpose of KEY6. Refer to Table Key Purpose Values. - */ - -#define EFUSE_KEY_PURPOSE_6 0x0000000F -#define EFUSE_KEY_PURPOSE_6_M (EFUSE_KEY_PURPOSE_6_V << EFUSE_KEY_PURPOSE_6_S) -#define EFUSE_KEY_PURPOSE_6_V 0x0000000F -#define EFUSE_KEY_PURPOSE_6_S 16 - -/* EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; - * Set this bit to enable secure boot. - */ - -#define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) -#define EFUSE_SECURE_BOOT_EN_V 0x00000001 -#define EFUSE_SECURE_BOOT_EN_S 20 - -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; - * Set this bit to enable aggressive secure boot key revocation mode. - */ - -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 - -/* EFUSE_RPT4_RESERVED1 : RO; bitpos: [27:22]; default: 0; - * Reserved (used for four backups method). - */ - -#define EFUSE_RPT4_RESERVED1 0x0000003F -#define EFUSE_RPT4_RESERVED1_M (EFUSE_RPT4_RESERVED1_V << EFUSE_RPT4_RESERVED1_S) -#define EFUSE_RPT4_RESERVED1_V 0x0000003F -#define EFUSE_RPT4_RESERVED1_S 22 - -/* EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; - * Configures flash startup delay after SoC power-up, in unit of (ms/2). - * When the value is 15, delay is 7.5 ms. - */ - -#define EFUSE_FLASH_TPUW 0x0000000F -#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) -#define EFUSE_FLASH_TPUW_V 0x0000000F -#define EFUSE_FLASH_TPUW_S 28 - -/* EFUSE_RD_REPEAT_DATA3_REG register - * Register 4 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) - -/* EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; - * Set this bit to disable all download boot modes. - */ - -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_MODE_S 0 - -/* EFUSE_DIS_LEGACY_SPI_BOOT : RO; bitpos: [1]; default: 0; - * Set this bit to disable Legacy SPI boot mode. - */ - -#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_M (EFUSE_DIS_LEGACY_SPI_BOOT_V << EFUSE_DIS_LEGACY_SPI_BOOT_S) -#define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x00000001 -#define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 - -/* EFUSE_UART_PRINT_CHANNEL : RO; bitpos: [2]; default: 0; - * Selects the default UART for printing boot messages. 0: UART0; 1: UART1. - */ - -#define EFUSE_UART_PRINT_CHANNEL (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_M (EFUSE_UART_PRINT_CHANNEL_V << EFUSE_UART_PRINT_CHANNEL_S) -#define EFUSE_UART_PRINT_CHANNEL_V 0x00000001 -#define EFUSE_UART_PRINT_CHANNEL_S 2 - -/* EFUSE_RPT4_RESERVED3 : RO; bitpos: [3]; default: 0; - * Reserved (used for four backups method). - */ - -#define EFUSE_RPT4_RESERVED3 (BIT(3)) -#define EFUSE_RPT4_RESERVED3_M (EFUSE_RPT4_RESERVED3_V << EFUSE_RPT4_RESERVED3_S) -#define EFUSE_RPT4_RESERVED3_V 0x00000001 -#define EFUSE_RPT4_RESERVED3_S 3 - -/* EFUSE_DIS_USB_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; - * Set this bit to disable use of USB in UART download boot mode. - */ - -#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (EFUSE_DIS_USB_DOWNLOAD_MODE_V << EFUSE_DIS_USB_DOWNLOAD_MODE_S) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x00000001 -#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 - -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; - * Set this bit to enable secure UART download mode (read/write flash only). - */ - -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 - -/* EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; - * Set the default UART boot message output mode. - * & - * 00: Enabled.# - * 01: Enable when GPIO46 is low at reset.# - * 10: Enable when GPIO46 is high at reset.# - * 11: Disabled. - * & - */ - -#define EFUSE_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) -#define EFUSE_UART_PRINT_CONTROL_V 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_S 6 - -/* EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0; - * Set default power supply for GPIO33-GPIO37, set when SPI flash is - * initialized. 0: VDD3P3_CPU; 1: VDD_SPI. - */ - -#define EFUSE_PIN_POWER_SELECTION (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_M (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S) -#define EFUSE_PIN_POWER_SELECTION_V 0x00000001 -#define EFUSE_PIN_POWER_SELECTION_S 8 - -/* EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0; - * SPI flash type. 0: maximum four data lines, 1: eight data lines. - */ - -#define EFUSE_FLASH_TYPE (BIT(9)) -#define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) -#define EFUSE_FLASH_TYPE_V 0x00000001 -#define EFUSE_FLASH_TYPE_S 9 - -/* EFUSE_FORCE_SEND_RESUME : RO; bitpos: [10]; default: 0; - * If set, forces ROM code to send an SPI flash resume command during SPI - * boot. - */ - -#define EFUSE_FORCE_SEND_RESUME (BIT(10)) -#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) -#define EFUSE_FORCE_SEND_RESUME_V 0x00000001 -#define EFUSE_FORCE_SEND_RESUME_S 10 - -/* EFUSE_SECURE_VERSION : RO; bitpos: [26:11]; default: 0; - * Secure version (used by ESP-IDF anti-rollback feature). - */ - -#define EFUSE_SECURE_VERSION 0x0000FFFF -#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) -#define EFUSE_SECURE_VERSION_V 0x0000FFFF -#define EFUSE_SECURE_VERSION_S 11 - -/* EFUSE_RPT4_RESERVED2 : RO; bitpos: [31:27]; default: 0; - * Reserved (used for four backups method). - */ - -#define EFUSE_RPT4_RESERVED2 0x0000001F -#define EFUSE_RPT4_RESERVED2_M (EFUSE_RPT4_RESERVED2_V << EFUSE_RPT4_RESERVED2_S) -#define EFUSE_RPT4_RESERVED2_V 0x0000001F -#define EFUSE_RPT4_RESERVED2_S 27 - -/* EFUSE_RD_REPEAT_DATA4_REG register - * Register 5 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) - -/* EFUSE_RPT4_RESERVED4 : RO; bitpos: [23:0]; default: 0; - * Reserved (used for four backups method). - */ - -#define EFUSE_RPT4_RESERVED4 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_M (EFUSE_RPT4_RESERVED4_V << EFUSE_RPT4_RESERVED4_S) -#define EFUSE_RPT4_RESERVED4_V 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_S 0 - -/* EFUSE_RD_MAC_SPI_SYS_0_REG register - * Register 0 of BLOCK1. - */ - -#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) - -/* EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; - * Stores the low 32 bits of MAC address. - */ - -#define EFUSE_MAC_0 0xFFFFFFFF -#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) -#define EFUSE_MAC_0_V 0xFFFFFFFF -#define EFUSE_MAC_0_S 0 - -/* EFUSE_RD_MAC_SPI_SYS_1_REG register - * Register 1 of BLOCK1. - */ - -#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) - -/* EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; - * Stores the high 16 bits of MAC address. - */ - -#define EFUSE_MAC_1 0x0000FFFF -#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) -#define EFUSE_MAC_1_V 0x0000FFFF -#define EFUSE_MAC_1_S 0 - -/* EFUSE_SPI_PAD_CONF_0 : RO; bitpos: [31:16]; default: 0; - * Stores the zeroth part of SPI_PAD_CONF. - */ - -#define EFUSE_SPI_PAD_CONF_0 0x0000FFFF -#define EFUSE_SPI_PAD_CONF_0_M (EFUSE_SPI_PAD_CONF_0_V << EFUSE_SPI_PAD_CONF_0_S) -#define EFUSE_SPI_PAD_CONF_0_V 0x0000FFFF -#define EFUSE_SPI_PAD_CONF_0_S 16 - -/* EFUSE_RD_MAC_SPI_SYS_2_REG register - * Register 2 of BLOCK1. - */ - -#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) - -/* EFUSE_SPI_PAD_CONF_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first part of SPI_PAD_CONF. - */ - -#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF -#define EFUSE_SPI_PAD_CONF_1_M (EFUSE_SPI_PAD_CONF_1_V << EFUSE_SPI_PAD_CONF_1_S) -#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF -#define EFUSE_SPI_PAD_CONF_1_S 0 - -/* EFUSE_RD_MAC_SPI_SYS_3_REG register - * Register 3 of BLOCK1. - */ - -#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) - -/* EFUSE_SPI_PAD_CONF_2 : RO; bitpos: [17:0]; default: 0; - * Stores the second part of SPI_PAD_CONF. - */ - -#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF -#define EFUSE_SPI_PAD_CONF_2_M (EFUSE_SPI_PAD_CONF_2_V << EFUSE_SPI_PAD_CONF_2_S) -#define EFUSE_SPI_PAD_CONF_2_V 0x0003FFFF -#define EFUSE_SPI_PAD_CONF_2_S 0 - -/* EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; - * Stores the zeroth part of the zeroth part of system data. - */ - -#define EFUSE_SYS_DATA_PART0_0 0x00003FFF -#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) -#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFF -#define EFUSE_SYS_DATA_PART0_0_S 18 - -/* EFUSE_RD_MAC_SPI_SYS_4_REG register - * Register 4 of BLOCK1. - */ - -#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) - -/* EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; - * Stores the fist part of the zeroth part of system data. - */ - -#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) -#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_1_S 0 - -/* EFUSE_RD_MAC_SPI_SYS_5_REG register - * Register 5 of BLOCK1. - */ - -#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) - -/* EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second part of the zeroth part of system data. - */ - -#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) -#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_2_S 0 - -/* EFUSE_RD_SYS_DATA_PART1_0_REG register - * Register 0 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART1_0_REG (DR_REG_EFUSE_BASE + 0x5c) - -/* EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_S 0 - -/* EFUSE_RD_SYS_DATA_PART1_1_REG register - * Register 1 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART1_1_REG (DR_REG_EFUSE_BASE + 0x60) - -/* EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1th 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_S 0 - -/* EFUSE_RD_SYS_DATA_PART1_2_REG register - * Register 2 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART1_2_REG (DR_REG_EFUSE_BASE + 0x64) - -/* EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2th 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_S 0 - -/* EFUSE_RD_SYS_DATA_PART1_3_REG register - * Register 3 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART1_3_REG (DR_REG_EFUSE_BASE + 0x68) - -/* EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3th 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_S 0 - -/* EFUSE_RD_SYS_DATA_PART1_4_REG register - * Register 4 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART1_4_REG (DR_REG_EFUSE_BASE + 0x6c) - -/* EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_S 0 - -/* EFUSE_RD_SYS_DATA_PART1_5_REG register - * Register 5 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART1_5_REG (DR_REG_EFUSE_BASE + 0x70) - -/* EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) -#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_S 0 - -/* EFUSE_RD_SYS_DATA_PART1_6_REG register - * Register 6 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART1_6_REG (DR_REG_EFUSE_BASE + 0x74) - -/* EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) -#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_S 0 - -/* EFUSE_RD_SYS_DATA_PART1_7_REG register - * Register 7 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART1_7_REG (DR_REG_EFUSE_BASE + 0x78) - -/* EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) -#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_S 0 - -/* EFUSE_RD_USR_DATA0_REG register - * Register 0 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) - -/* EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA0 0xFFFFFFFF -#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) -#define EFUSE_USR_DATA0_V 0xFFFFFFFF -#define EFUSE_USR_DATA0_S 0 - -/* EFUSE_RD_USR_DATA1_REG register - * Register 1 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) - -/* EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1th 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA1 0xFFFFFFFF -#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) -#define EFUSE_USR_DATA1_V 0xFFFFFFFF -#define EFUSE_USR_DATA1_S 0 - -/* EFUSE_RD_USR_DATA2_REG register - * Register 2 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) - -/* EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2th 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA2 0xFFFFFFFF -#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) -#define EFUSE_USR_DATA2_V 0xFFFFFFFF -#define EFUSE_USR_DATA2_S 0 - -/* EFUSE_RD_USR_DATA3_REG register - * Register 3 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) - -/* EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3th 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA3 0xFFFFFFFF -#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) -#define EFUSE_USR_DATA3_V 0xFFFFFFFF -#define EFUSE_USR_DATA3_S 0 - -/* EFUSE_RD_USR_DATA4_REG register - * Register 4 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) - -/* EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA4 0xFFFFFFFF -#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) -#define EFUSE_USR_DATA4_V 0xFFFFFFFF -#define EFUSE_USR_DATA4_S 0 - -/* EFUSE_RD_USR_DATA5_REG register - * Register 5 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) - -/* EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA5 0xFFFFFFFF -#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) -#define EFUSE_USR_DATA5_V 0xFFFFFFFF -#define EFUSE_USR_DATA5_S 0 - -/* EFUSE_RD_USR_DATA6_REG register - * Register 6 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) - -/* EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA6 0xFFFFFFFF -#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) -#define EFUSE_USR_DATA6_V 0xFFFFFFFF -#define EFUSE_USR_DATA6_S 0 - -/* EFUSE_RD_USR_DATA7_REG register - * Register 7 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) - -/* EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA7 0xFFFFFFFF -#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) -#define EFUSE_USR_DATA7_V 0xFFFFFFFF -#define EFUSE_USR_DATA7_S 0 - -/* EFUSE_RD_KEY0_DATA0_REG register - * Register 0 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) - -/* EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA0 0xFFFFFFFF -#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) -#define EFUSE_KEY0_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA0_S 0 - -/* EFUSE_RD_KEY0_DATA1_REG register - * Register 1 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) - -/* EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1th 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA1 0xFFFFFFFF -#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) -#define EFUSE_KEY0_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA1_S 0 - -/* EFUSE_RD_KEY0_DATA2_REG register - * Register 2 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) - -/* EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2th 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA2 0xFFFFFFFF -#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) -#define EFUSE_KEY0_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA2_S 0 - -/* EFUSE_RD_KEY0_DATA3_REG register - * Register 3 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) - -/* EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3th 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA3 0xFFFFFFFF -#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) -#define EFUSE_KEY0_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA3_S 0 - -/* EFUSE_RD_KEY0_DATA4_REG register - * Register 4 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) - -/* EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA4 0xFFFFFFFF -#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) -#define EFUSE_KEY0_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA4_S 0 - -/* EFUSE_RD_KEY0_DATA5_REG register - * Register 5 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) - -/* EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA5 0xFFFFFFFF -#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) -#define EFUSE_KEY0_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA5_S 0 - -/* EFUSE_RD_KEY0_DATA6_REG register - * Register 6 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) - -/* EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA6 0xFFFFFFFF -#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) -#define EFUSE_KEY0_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA6_S 0 - -/* EFUSE_RD_KEY0_DATA7_REG register - * Register 7 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) - -/* EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA7 0xFFFFFFFF -#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) -#define EFUSE_KEY0_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA7_S 0 - -/* EFUSE_RD_KEY1_DATA0_REG register - * Register 0 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) - -/* EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA0 0xFFFFFFFF -#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) -#define EFUSE_KEY1_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA0_S 0 - -/* EFUSE_RD_KEY1_DATA1_REG register - * Register 1 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) - -/* EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1th 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA1 0xFFFFFFFF -#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) -#define EFUSE_KEY1_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA1_S 0 - -/* EFUSE_RD_KEY1_DATA2_REG register - * Register 2 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) - -/* EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2th 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA2 0xFFFFFFFF -#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) -#define EFUSE_KEY1_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA2_S 0 - -/* EFUSE_RD_KEY1_DATA3_REG register - * Register 3 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) - -/* EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3th 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA3 0xFFFFFFFF -#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) -#define EFUSE_KEY1_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA3_S 0 - -/* EFUSE_RD_KEY1_DATA4_REG register - * Register 4 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) - -/* EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA4 0xFFFFFFFF -#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) -#define EFUSE_KEY1_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA4_S 0 - -/* EFUSE_RD_KEY1_DATA5_REG register - * Register 5 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) - -/* EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA5 0xFFFFFFFF -#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) -#define EFUSE_KEY1_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA5_S 0 - -/* EFUSE_RD_KEY1_DATA6_REG register - * Register 6 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) - -/* EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA6 0xFFFFFFFF -#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) -#define EFUSE_KEY1_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA6_S 0 - -/* EFUSE_RD_KEY1_DATA7_REG register - * Register 7 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) - -/* EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA7 0xFFFFFFFF -#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) -#define EFUSE_KEY1_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA7_S 0 - -/* EFUSE_RD_KEY2_DATA0_REG register - * Register 0 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) - -/* EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA0 0xFFFFFFFF -#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) -#define EFUSE_KEY2_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA0_S 0 - -/* EFUSE_RD_KEY2_DATA1_REG register - * Register 1 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) - -/* EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1th 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA1 0xFFFFFFFF -#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) -#define EFUSE_KEY2_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA1_S 0 - -/* EFUSE_RD_KEY2_DATA2_REG register - * Register 2 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) - -/* EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2th 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA2 0xFFFFFFFF -#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) -#define EFUSE_KEY2_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA2_S 0 - -/* EFUSE_RD_KEY2_DATA3_REG register - * Register 3 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) - -/* EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3th 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA3 0xFFFFFFFF -#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) -#define EFUSE_KEY2_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA3_S 0 - -/* EFUSE_RD_KEY2_DATA4_REG register - * Register 4 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) - -/* EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA4 0xFFFFFFFF -#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) -#define EFUSE_KEY2_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA4_S 0 - -/* EFUSE_RD_KEY2_DATA5_REG register - * Register 5 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) - -/* EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA5 0xFFFFFFFF -#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) -#define EFUSE_KEY2_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA5_S 0 - -/* EFUSE_RD_KEY2_DATA6_REG register - * Register 6 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) - -/* EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA6 0xFFFFFFFF -#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) -#define EFUSE_KEY2_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA6_S 0 - -/* EFUSE_RD_KEY2_DATA7_REG register - * Register 7 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) - -/* EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA7 0xFFFFFFFF -#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) -#define EFUSE_KEY2_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA7_S 0 - -/* EFUSE_RD_KEY3_DATA0_REG register - * Register 0 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) - -/* EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA0 0xFFFFFFFF -#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) -#define EFUSE_KEY3_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA0_S 0 - -/* EFUSE_RD_KEY3_DATA1_REG register - * Register 1 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) - -/* EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1th 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA1 0xFFFFFFFF -#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) -#define EFUSE_KEY3_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA1_S 0 - -/* EFUSE_RD_KEY3_DATA2_REG register - * Register 2 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) - -/* EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2th 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA2 0xFFFFFFFF -#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) -#define EFUSE_KEY3_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA2_S 0 - -/* EFUSE_RD_KEY3_DATA3_REG register - * Register 3 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) - -/* EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3th 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA3 0xFFFFFFFF -#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) -#define EFUSE_KEY3_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA3_S 0 - -/* EFUSE_RD_KEY3_DATA4_REG register - * Register 4 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) - -/* EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA4 0xFFFFFFFF -#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) -#define EFUSE_KEY3_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA4_S 0 - -/* EFUSE_RD_KEY3_DATA5_REG register - * Register 5 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) - -/* EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA5 0xFFFFFFFF -#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) -#define EFUSE_KEY3_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA5_S 0 - -/* EFUSE_RD_KEY3_DATA6_REG register - * Register 6 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) - -/* EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA6 0xFFFFFFFF -#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) -#define EFUSE_KEY3_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA6_S 0 - -/* EFUSE_RD_KEY3_DATA7_REG register - * Register 7 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) - -/* EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA7 0xFFFFFFFF -#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) -#define EFUSE_KEY3_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA7_S 0 - -/* EFUSE_RD_KEY4_DATA0_REG register - * Register 0 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) - -/* EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA0 0xFFFFFFFF -#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) -#define EFUSE_KEY4_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA0_S 0 - -/* EFUSE_RD_KEY4_DATA1_REG register - * Register 1 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) - -/* EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1th 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA1 0xFFFFFFFF -#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) -#define EFUSE_KEY4_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA1_S 0 - -/* EFUSE_RD_KEY4_DATA2_REG register - * Register 2 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) - -/* EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2th 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA2 0xFFFFFFFF -#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) -#define EFUSE_KEY4_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA2_S 0 - -/* EFUSE_RD_KEY4_DATA3_REG register - * Register 3 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) - -/* EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3th 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA3 0xFFFFFFFF -#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) -#define EFUSE_KEY4_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA3_S 0 - -/* EFUSE_RD_KEY4_DATA4_REG register - * Register 4 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) - -/* EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA4 0xFFFFFFFF -#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) -#define EFUSE_KEY4_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA4_S 0 - -/* EFUSE_RD_KEY4_DATA5_REG register - * Register 5 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) - -/* EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA5 0xFFFFFFFF -#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) -#define EFUSE_KEY4_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA5_S 0 - -/* EFUSE_RD_KEY4_DATA6_REG register - * Register 6 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) - -/* EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA6 0xFFFFFFFF -#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) -#define EFUSE_KEY4_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA6_S 0 - -/* EFUSE_RD_KEY4_DATA7_REG register - * Register 7 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) - -/* EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA7 0xFFFFFFFF -#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) -#define EFUSE_KEY4_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA7_S 0 - -/* EFUSE_RD_KEY5_DATA0_REG register - * Register 0 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) - -/* EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA0 0xFFFFFFFF -#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) -#define EFUSE_KEY5_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA0_S 0 - -/* EFUSE_RD_KEY5_DATA1_REG register - * Register 1 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) - -/* EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1th 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA1 0xFFFFFFFF -#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) -#define EFUSE_KEY5_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA1_S 0 - -/* EFUSE_RD_KEY5_DATA2_REG register - * Register 2 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) - -/* EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2th 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA2 0xFFFFFFFF -#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) -#define EFUSE_KEY5_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA2_S 0 - -/* EFUSE_RD_KEY5_DATA3_REG register - * Register 3 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) - -/* EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3th 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA3 0xFFFFFFFF -#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) -#define EFUSE_KEY5_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA3_S 0 - -/* EFUSE_RD_KEY5_DATA4_REG register - * Register 4 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) - -/* EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA4 0xFFFFFFFF -#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) -#define EFUSE_KEY5_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA4_S 0 - -/* EFUSE_RD_KEY5_DATA5_REG register - * Register 5 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) - -/* EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA5 0xFFFFFFFF -#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) -#define EFUSE_KEY5_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA5_S 0 - -/* EFUSE_RD_KEY5_DATA6_REG register - * Register 6 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) - -/* EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA6 0xFFFFFFFF -#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) -#define EFUSE_KEY5_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA6_S 0 - -/* EFUSE_RD_KEY5_DATA7_REG register - * Register 7 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) - -/* EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA7 0xFFFFFFFF -#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) -#define EFUSE_KEY5_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA7_S 0 - -/* EFUSE_RD_SYS_DATA_PART2_0_REG register - * Register 0 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART2_0_REG (DR_REG_EFUSE_BASE + 0x15c) - -/* EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) -#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_0_S 0 - -/* EFUSE_RD_SYS_DATA_PART2_1_REG register - * Register 1 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART2_1_REG (DR_REG_EFUSE_BASE + 0x160) - -/* EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) -#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_1_S 0 - -/* EFUSE_RD_SYS_DATA_PART2_2_REG register - * Register 2 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART2_2_REG (DR_REG_EFUSE_BASE + 0x164) - -/* EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) -#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_2_S 0 - -/* EFUSE_RD_SYS_DATA_PART2_3_REG register - * Register 3 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART2_3_REG (DR_REG_EFUSE_BASE + 0x168) - -/* EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) -#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_3_S 0 - -/* EFUSE_RD_SYS_DATA_PART2_4_REG register - * Register 4 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART2_4_REG (DR_REG_EFUSE_BASE + 0x16c) - -/* EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) -#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_4_S 0 - -/* EFUSE_RD_SYS_DATA_PART2_5_REG register - * Register 5 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART2_5_REG (DR_REG_EFUSE_BASE + 0x170) - -/* EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) -#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_5_S 0 - -/* EFUSE_RD_SYS_DATA_PART2_6_REG register - * Register 6 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART2_6_REG (DR_REG_EFUSE_BASE + 0x174) - -/* EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) -#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_6_S 0 - -/* EFUSE_RD_SYS_DATA_PART2_7_REG register - * Register 7 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART2_7_REG (DR_REG_EFUSE_BASE + 0x178) - -/* EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) -#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_7_S 0 - -/* EFUSE_RD_REPEAT_ERR0_REG register - * Programming error record register 0 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) - -/* EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_RD_DIS. - */ - -#define EFUSE_RD_DIS_ERR 0x0000007F -#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) -#define EFUSE_RD_DIS_ERR_V 0x0000007F -#define EFUSE_RD_DIS_ERR_S 0 - -/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_RTC_RAM_BOOT. - */ - -#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x00000001 -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 - -/* EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_ICACHE. - */ - -#define EFUSE_DIS_ICACHE_ERR (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) -#define EFUSE_DIS_ICACHE_ERR_V 0x00000001 -#define EFUSE_DIS_ICACHE_ERR_S 8 - -/* EFUSE_DIS_DCACHE_ERR : RO; bitpos: [9]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_DCACHE. - */ - -#define EFUSE_DIS_DCACHE_ERR (BIT(9)) -#define EFUSE_DIS_DCACHE_ERR_M (EFUSE_DIS_DCACHE_ERR_V << EFUSE_DIS_DCACHE_ERR_S) -#define EFUSE_DIS_DCACHE_ERR_V 0x00000001 -#define EFUSE_DIS_DCACHE_ERR_S 9 - -/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_DOWNLOAD_ICACHE. - */ - -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 - -/* EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO; bitpos: [11]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_DOWNLOAD_DCACHE. - */ - -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V << EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S) -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11 - -/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_FORCE_DOWNLOAD. - */ - -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001 -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 - -/* EFUSE_DIS_USB_ERR : RO; bitpos: [13]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_USB. - */ - -#define EFUSE_DIS_USB_ERR (BIT(13)) -#define EFUSE_DIS_USB_ERR_M (EFUSE_DIS_USB_ERR_V << EFUSE_DIS_USB_ERR_S) -#define EFUSE_DIS_USB_ERR_V 0x00000001 -#define EFUSE_DIS_USB_ERR_S 13 - -/* EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_CAN. - */ - -#define EFUSE_DIS_CAN_ERR (BIT(14)) -#define EFUSE_DIS_CAN_ERR_M (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S) -#define EFUSE_DIS_CAN_ERR_V 0x00000001 -#define EFUSE_DIS_CAN_ERR_S 14 - -/* EFUSE_DIS_BOOT_REMAP_ERR : RO; bitpos: [15]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_BOOT_REMAP. - */ - -#define EFUSE_DIS_BOOT_REMAP_ERR (BIT(15)) -#define EFUSE_DIS_BOOT_REMAP_ERR_M (EFUSE_DIS_BOOT_REMAP_ERR_V << EFUSE_DIS_BOOT_REMAP_ERR_S) -#define EFUSE_DIS_BOOT_REMAP_ERR_V 0x00000001 -#define EFUSE_DIS_BOOT_REMAP_ERR_S 15 - -/* EFUSE_DIS_EFUSE_ATE_WR_ERR : RO; bitpos: [16]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_EFUSE_ATE_WR. - */ - -#define EFUSE_DIS_EFUSE_ATE_WR_ERR (BIT(16)) -#define EFUSE_DIS_EFUSE_ATE_WR_ERR_M (EFUSE_DIS_EFUSE_ATE_WR_ERR_V << EFUSE_DIS_EFUSE_ATE_WR_ERR_S) -#define EFUSE_DIS_EFUSE_ATE_WR_ERR_V 0x00000001 -#define EFUSE_DIS_EFUSE_ATE_WR_ERR_S 16 - -/* EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [17]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_SOFT_DIS_JTAG. - */ - -#define EFUSE_SOFT_DIS_JTAG_ERR (BIT(17)) -#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) -#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000001 -#define EFUSE_SOFT_DIS_JTAG_ERR_S 17 - -/* EFUSE_HARD_DIS_JTAG_ERR : RO; bitpos: [18]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_HARD_DIS_JTAG. - */ - -#define EFUSE_HARD_DIS_JTAG_ERR (BIT(18)) -#define EFUSE_HARD_DIS_JTAG_ERR_M (EFUSE_HARD_DIS_JTAG_ERR_V << EFUSE_HARD_DIS_JTAG_ERR_S) -#define EFUSE_HARD_DIS_JTAG_ERR_V 0x00000001 -#define EFUSE_HARD_DIS_JTAG_ERR_S 18 - -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [19]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT. - */ - -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(19)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 19 - -/* EFUSE_USB_DREFH_ERR : RO; bitpos: [21:20]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_USB_DREFH. - */ - -#define EFUSE_USB_DREFH_ERR 0x00000003 -#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) -#define EFUSE_USB_DREFH_ERR_V 0x00000003 -#define EFUSE_USB_DREFH_ERR_S 20 - -/* EFUSE_USB_DREFL_ERR : RO; bitpos: [23:22]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_USB_DREFL. - */ - -#define EFUSE_USB_DREFL_ERR 0x00000003 -#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) -#define EFUSE_USB_DREFL_ERR_V 0x00000003 -#define EFUSE_USB_DREFL_ERR_S 22 - -/* EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [24]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_USB_EXCHG_PINS. - */ - -#define EFUSE_USB_EXCHG_PINS_ERR (BIT(24)) -#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) -#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001 -#define EFUSE_USB_EXCHG_PINS_ERR_S 24 - -/* EFUSE_EXT_PHY_ENABLE_ERR : RO; bitpos: [25]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_EXT_PHY_ENABLE. - */ - -#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(25)) -#define EFUSE_EXT_PHY_ENABLE_ERR_M (EFUSE_EXT_PHY_ENABLE_ERR_V << EFUSE_EXT_PHY_ENABLE_ERR_S) -#define EFUSE_EXT_PHY_ENABLE_ERR_V 0x00000001 -#define EFUSE_EXT_PHY_ENABLE_ERR_S 25 - -/* EFUSE_USB_FORCE_NOPERSIST_ERR : RO; bitpos: [26]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_USB_FORCE_NOPERSIST. - */ - -#define EFUSE_USB_FORCE_NOPERSIST_ERR (BIT(26)) -#define EFUSE_USB_FORCE_NOPERSIST_ERR_M (EFUSE_USB_FORCE_NOPERSIST_ERR_V << EFUSE_USB_FORCE_NOPERSIST_ERR_S) -#define EFUSE_USB_FORCE_NOPERSIST_ERR_V 0x00000001 -#define EFUSE_USB_FORCE_NOPERSIST_ERR_S 26 - -/* EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [28:27]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_RPT4_RESERVED0. - */ - -#define EFUSE_RPT4_RESERVED0_ERR 0x00000003 -#define EFUSE_RPT4_RESERVED0_ERR_M (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S) -#define EFUSE_RPT4_RESERVED0_ERR_V 0x00000003 -#define EFUSE_RPT4_RESERVED0_ERR_S 27 - -/* EFUSE_VDD_SPI_MODECURLIM_ERR : RO; bitpos: [29]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_MODECURLIM. - */ - -#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_ERR_M (EFUSE_VDD_SPI_MODECURLIM_ERR_V << EFUSE_VDD_SPI_MODECURLIM_ERR_S) -#define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x00000001 -#define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29 - -/* EFUSE_VDD_SPI_DREFH_ERR : RO; bitpos: [31:30]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_DREFH. - */ - -#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFH_ERR_M (EFUSE_VDD_SPI_DREFH_ERR_V << EFUSE_VDD_SPI_DREFH_ERR_S) -#define EFUSE_VDD_SPI_DREFH_ERR_V 0x00000003 -#define EFUSE_VDD_SPI_DREFH_ERR_S 30 - -/* EFUSE_RD_REPEAT_ERR1_REG register - * Programming error record register 1 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) - -/* EFUSE_VDD_SPI_DREFM_ERR : RO; bitpos: [1:0]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_DREFM. - */ - -#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFM_ERR_M (EFUSE_VDD_SPI_DREFM_ERR_V << EFUSE_VDD_SPI_DREFM_ERR_S) -#define EFUSE_VDD_SPI_DREFM_ERR_V 0x00000003 -#define EFUSE_VDD_SPI_DREFM_ERR_S 0 - -/* EFUSE_VDD_SPI_DREFL_ERR : RO; bitpos: [3:2]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_DREFL. - */ - -#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFL_ERR_M (EFUSE_VDD_SPI_DREFL_ERR_V << EFUSE_VDD_SPI_DREFL_ERR_S) -#define EFUSE_VDD_SPI_DREFL_ERR_V 0x00000003 -#define EFUSE_VDD_SPI_DREFL_ERR_S 2 - -/* EFUSE_VDD_SPI_XPD_ERR : RO; bitpos: [4]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_XPD. - */ - -#define EFUSE_VDD_SPI_XPD_ERR (BIT(4)) -#define EFUSE_VDD_SPI_XPD_ERR_M (EFUSE_VDD_SPI_XPD_ERR_V << EFUSE_VDD_SPI_XPD_ERR_S) -#define EFUSE_VDD_SPI_XPD_ERR_V 0x00000001 -#define EFUSE_VDD_SPI_XPD_ERR_S 4 - -/* EFUSE_VDD_SPI_TIEH_ERR : RO; bitpos: [5]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_TIEH. - */ - -#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_ERR_M (EFUSE_VDD_SPI_TIEH_ERR_V << EFUSE_VDD_SPI_TIEH_ERR_S) -#define EFUSE_VDD_SPI_TIEH_ERR_V 0x00000001 -#define EFUSE_VDD_SPI_TIEH_ERR_S 5 - -/* EFUSE_VDD_SPI_FORCE_ERR : RO; bitpos: [6]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_FORCE. - */ - -#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_ERR_M (EFUSE_VDD_SPI_FORCE_ERR_V << EFUSE_VDD_SPI_FORCE_ERR_S) -#define EFUSE_VDD_SPI_FORCE_ERR_V 0x00000001 -#define EFUSE_VDD_SPI_FORCE_ERR_S 6 - -/* EFUSE_VDD_SPI_EN_INIT_ERR : RO; bitpos: [7]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_EN_INIT. - */ - -#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_ERR_M (EFUSE_VDD_SPI_EN_INIT_ERR_V << EFUSE_VDD_SPI_EN_INIT_ERR_S) -#define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x00000001 -#define EFUSE_VDD_SPI_EN_INIT_ERR_S 7 - -/* EFUSE_VDD_SPI_ENCURLIM_ERR : RO; bitpos: [8]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_ENCURLIM. - */ - -#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_ERR_M (EFUSE_VDD_SPI_ENCURLIM_ERR_V << EFUSE_VDD_SPI_ENCURLIM_ERR_S) -#define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x00000001 -#define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8 - -/* EFUSE_VDD_SPI_DCURLIM_ERR : RO; bitpos: [11:9]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_DCURLIM. - */ - -#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_ERR_M (EFUSE_VDD_SPI_DCURLIM_ERR_V << EFUSE_VDD_SPI_DCURLIM_ERR_S) -#define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_ERR_S 9 - -/* EFUSE_VDD_SPI_INIT_ERR : RO; bitpos: [13:12]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_INIT. - */ - -#define EFUSE_VDD_SPI_INIT_ERR 0x00000003 -#define EFUSE_VDD_SPI_INIT_ERR_M (EFUSE_VDD_SPI_INIT_ERR_V << EFUSE_VDD_SPI_INIT_ERR_S) -#define EFUSE_VDD_SPI_INIT_ERR_V 0x00000003 -#define EFUSE_VDD_SPI_INIT_ERR_S 12 - -/* EFUSE_VDD_SPI_DCAP_ERR : RO; bitpos: [15:14]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_DCAP. - */ - -#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003 -#define EFUSE_VDD_SPI_DCAP_ERR_M (EFUSE_VDD_SPI_DCAP_ERR_V << EFUSE_VDD_SPI_DCAP_ERR_S) -#define EFUSE_VDD_SPI_DCAP_ERR_V 0x00000003 -#define EFUSE_VDD_SPI_DCAP_ERR_S 14 - -/* EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_WDT_DELAY_SEL. - */ - -#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 -#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) -#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003 -#define EFUSE_WDT_DELAY_SEL_ERR_S 16 - -/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_SPI_BOOT_CRYPT_CNT. - */ - -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 - -/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_SECURE_BOOT_KEY_REVOKE0. - */ - -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 - -/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_SECURE_BOOT_KEY_REVOKE1. - */ - -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 - -/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_SECURE_BOOT_KEY_REVOKE2. - */ - -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 - -/* EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_KEY_PURPOSE_0. - */ - -#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) -#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000F -#define EFUSE_KEY_PURPOSE_0_ERR_S 24 - -/* EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_KEY_PURPOSE_1. - */ - -#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) -#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000F -#define EFUSE_KEY_PURPOSE_1_ERR_S 28 - -/* EFUSE_RD_REPEAT_ERR2_REG register - * Programming error record register 2 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) - -/* EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_KEY_PURPOSE_2. - */ - -#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) -#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000F -#define EFUSE_KEY_PURPOSE_2_ERR_S 0 - -/* EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_KEY_PURPOSE_3. - */ - -#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) -#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000F -#define EFUSE_KEY_PURPOSE_3_ERR_S 4 - -/* EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_KEY_PURPOSE_4. - */ - -#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) -#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000F -#define EFUSE_KEY_PURPOSE_4_ERR_S 8 - -/* EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_KEY_PURPOSE_5. - */ - -#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) -#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000F -#define EFUSE_KEY_PURPOSE_5_ERR_S 12 - -/* EFUSE_KEY_PURPOSE_6_ERR : RO; bitpos: [19:16]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_KEY_PURPOSE_6. - */ - -#define EFUSE_KEY_PURPOSE_6_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_6_ERR_M (EFUSE_KEY_PURPOSE_6_ERR_V << EFUSE_KEY_PURPOSE_6_ERR_S) -#define EFUSE_KEY_PURPOSE_6_ERR_V 0x0000000F -#define EFUSE_KEY_PURPOSE_6_ERR_S 16 - -/* EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_SECURE_BOOT_EN. - */ - -#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) -#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001 -#define EFUSE_SECURE_BOOT_EN_ERR_S 20 - -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE. - */ - -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 - -/* EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [27:22]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_RPT4_RESERVED1. - */ - -#define EFUSE_RPT4_RESERVED1_ERR 0x0000003F -#define EFUSE_RPT4_RESERVED1_ERR_M (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S) -#define EFUSE_RPT4_RESERVED1_ERR_V 0x0000003F -#define EFUSE_RPT4_RESERVED1_ERR_S 22 - -/* EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_FLASH_TPUW. - */ - -#define EFUSE_FLASH_TPUW_ERR 0x0000000F -#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) -#define EFUSE_FLASH_TPUW_ERR_V 0x0000000F -#define EFUSE_FLASH_TPUW_ERR_S 28 - -/* EFUSE_RD_REPEAT_ERR3_REG register - * Programming error record register 3 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) - -/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_DOWNLOAD_MODE. - */ - -#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 - -/* EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_LEGACY_SPI_BOOT. - */ - -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S) -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x00000001 -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 - -/* EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_UART_PRINT_CHANNEL. - */ - -#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_ERR_M (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S) -#define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x00000001 -#define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 - -/* EFUSE_RPT4_RESERVED3_ERR : RO; bitpos: [3]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_RPT4_RESERVED3. - */ - -#define EFUSE_RPT4_RESERVED3_ERR (BIT(3)) -#define EFUSE_RPT4_RESERVED3_ERR_M (EFUSE_RPT4_RESERVED3_ERR_V << EFUSE_RPT4_RESERVED3_ERR_S) -#define EFUSE_RPT4_RESERVED3_ERR_V 0x00000001 -#define EFUSE_RPT4_RESERVED3_ERR_S 3 - -/* EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_USB_DOWNLOAD_MODE. - */ - -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x00000001 -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 - -/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_ENABLE_SECURITY_DOWNLOAD. - */ - -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 - -/* EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_UART_PRINT_CONTROL. - */ - -#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) -#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 - -/* EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_PIN_POWER_SELECTION. - */ - -#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_ERR_M (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S) -#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x00000001 -#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 - -/* EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_FLASH_TYPE. - */ - -#define EFUSE_FLASH_TYPE_ERR (BIT(9)) -#define EFUSE_FLASH_TYPE_ERR_M (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S) -#define EFUSE_FLASH_TYPE_ERR_V 0x00000001 -#define EFUSE_FLASH_TYPE_ERR_S 9 - -/* EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [10]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_FORCE_SEND_RESUME. - */ - -#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(10)) -#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) -#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001 -#define EFUSE_FORCE_SEND_RESUME_ERR_S 10 - -/* EFUSE_SECURE_VERSION_ERR : RO; bitpos: [26:11]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_SECURE_VERSION. - */ - -#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF -#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) -#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFF -#define EFUSE_SECURE_VERSION_ERR_S 11 - -/* EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [31:27]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_RPT4_RESERVED2. - */ - -#define EFUSE_RPT4_RESERVED2_ERR 0x0000001F -#define EFUSE_RPT4_RESERVED2_ERR_M (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S) -#define EFUSE_RPT4_RESERVED2_ERR_V 0x0000001F -#define EFUSE_RPT4_RESERVED2_ERR_S 27 - -/* EFUSE_RD_REPEAT_ERR4_REG register - * Programming error record register 4 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) - -/* EFUSE_RPT4_RESERVED4_ERR : RO; bitpos: [23:0]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_RPT4_RESERVED4. - */ - -#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_ERR_M (EFUSE_RPT4_RESERVED4_ERR_V << EFUSE_RPT4_RESERVED4_ERR_S) -#define EFUSE_RPT4_RESERVED4_ERR_V 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_ERR_S 0 - -/* EFUSE_RD_RS_ERR0_REG register - * Programming error record register 0 of BLOCK1-10. - */ - -#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) - -/* EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes in BLOCK1. - */ - -#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007 -#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) -#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007 -#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 - -/* EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of BLOCK1 is reliable; 1: Means - * that programming BLOCK1 data failed and the number of error bytes is over - * 5. - */ - -#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) -#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) -#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001 -#define EFUSE_MAC_SPI_8M_FAIL_S 3 - -/* EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes in BLOCK2. - */ - -#define EFUSE_SYS_PART1_NUM 0x00000007 -#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) -#define EFUSE_SYS_PART1_NUM_V 0x00000007 -#define EFUSE_SYS_PART1_NUM_S 4 - -/* EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of BLOCK2 is reliable; 1: Means - * that programming BLOCK2 data failed and the number of error bytes is over - * 5. - */ - -#define EFUSE_SYS_PART1_FAIL (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) -#define EFUSE_SYS_PART1_FAIL_V 0x00000001 -#define EFUSE_SYS_PART1_FAIL_S 7 - -/* EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; - * The value of this signal means the number of error bytes in BLOCK3. - */ - -#define EFUSE_USR_DATA_ERR_NUM 0x00000007 -#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) -#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007 -#define EFUSE_USR_DATA_ERR_NUM_S 8 - -/* EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; - * 0: Means no failure and that the data of BLOCK3 is reliable; 1: Means - * that programming BLOCK3 data failed and the number of error bytes is over - * 5. - */ - -#define EFUSE_USR_DATA_FAIL (BIT(11)) -#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) -#define EFUSE_USR_DATA_FAIL_V 0x00000001 -#define EFUSE_USR_DATA_FAIL_S 11 - -/* EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; - * The value of this signal means the number of error bytes in KEY0. - */ - -#define EFUSE_KEY0_ERR_NUM 0x00000007 -#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) -#define EFUSE_KEY0_ERR_NUM_V 0x00000007 -#define EFUSE_KEY0_ERR_NUM_S 12 - -/* EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; - * 0: Means no failure and that the data of KEY0 is reliable; 1: Means that - * programming KEY0 failed and the number of error bytes is over 5. - */ - -#define EFUSE_KEY0_FAIL (BIT(15)) -#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) -#define EFUSE_KEY0_FAIL_V 0x00000001 -#define EFUSE_KEY0_FAIL_S 15 - -/* EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; - * The value of this signal means the number of error bytes in KEY1. - */ - -#define EFUSE_KEY1_ERR_NUM 0x00000007 -#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) -#define EFUSE_KEY1_ERR_NUM_V 0x00000007 -#define EFUSE_KEY1_ERR_NUM_S 16 - -/* EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; - * 0: Means no failure and that the data of KEY1 is reliable; 1: Means that - * programming KEY1 failed and the number of error bytes is over 5. - */ - -#define EFUSE_KEY1_FAIL (BIT(19)) -#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) -#define EFUSE_KEY1_FAIL_V 0x00000001 -#define EFUSE_KEY1_FAIL_S 19 - -/* EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; - * The value of this signal means the number of error bytes in KEY2. - */ - -#define EFUSE_KEY2_ERR_NUM 0x00000007 -#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) -#define EFUSE_KEY2_ERR_NUM_V 0x00000007 -#define EFUSE_KEY2_ERR_NUM_S 20 - -/* EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; - * 0: Means no failure and that the data of KEY2 is reliable; 1: Means that - * programming KEY2 failed and the number of error bytes is over 5. - */ - -#define EFUSE_KEY2_FAIL (BIT(23)) -#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) -#define EFUSE_KEY2_FAIL_V 0x00000001 -#define EFUSE_KEY2_FAIL_S 23 - -/* EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; - * The value of this signal means the number of error bytes in KEY3. - */ - -#define EFUSE_KEY3_ERR_NUM 0x00000007 -#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) -#define EFUSE_KEY3_ERR_NUM_V 0x00000007 -#define EFUSE_KEY3_ERR_NUM_S 24 - -/* EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; - * 0: Means no failure and that the data of KEY3 is reliable; 1: Means that - * programming KEY3 failed and the number of error bytes is over 5. - */ - -#define EFUSE_KEY3_FAIL (BIT(27)) -#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) -#define EFUSE_KEY3_FAIL_V 0x00000001 -#define EFUSE_KEY3_FAIL_S 27 - -/* EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; - * The value of this signal means the number of error bytes in KEY4. - */ - -#define EFUSE_KEY4_ERR_NUM 0x00000007 -#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) -#define EFUSE_KEY4_ERR_NUM_V 0x00000007 -#define EFUSE_KEY4_ERR_NUM_S 28 - -/* EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; - * 0: Means no failure and that the data of KEY4 is reliable; 1: Means that - * programming KEY4 failed and the number of error bytes is over 5. - */ - -#define EFUSE_KEY4_FAIL (BIT(31)) -#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) -#define EFUSE_KEY4_FAIL_V 0x00000001 -#define EFUSE_KEY4_FAIL_S 31 - -/* EFUSE_RD_RS_ERR1_REG register - * Programming error record register 1 of BLOCK1-10. - */ - -#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) - -/* EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes in KEY5. - */ - -#define EFUSE_KEY5_ERR_NUM 0x00000007 -#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) -#define EFUSE_KEY5_ERR_NUM_V 0x00000007 -#define EFUSE_KEY5_ERR_NUM_S 0 - -/* EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of KEY5 is reliable; 1: Means that - * programming user data failed and the number of error bytes is over 5. - */ - -#define EFUSE_KEY5_FAIL (BIT(3)) -#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) -#define EFUSE_KEY5_FAIL_V 0x00000001 -#define EFUSE_KEY5_FAIL_S 3 - -/* EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes in BLOCK10. - */ - -#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 -#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) -#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007 -#define EFUSE_SYS_PART2_ERR_NUM_S 4 - -/* EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of BLOCK10 is reliable; 1: Means - * that programming BLOCK10 data failed and the number of error bytes is - * over 5. - */ - -#define EFUSE_SYS_PART2_FAIL (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) -#define EFUSE_SYS_PART2_FAIL_V 0x00000001 -#define EFUSE_SYS_PART2_FAIL_S 7 - -/* EFUSE_CLK_REG register - * eFuse clock configuration register. - */ - -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) - -/* EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; - * If set, forces eFuse SRAM into power-saving mode. - */ - -#define EFUSE_EFUSE_MEM_FORCE_PD (BIT(0)) -#define EFUSE_EFUSE_MEM_FORCE_PD_M (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S) -#define EFUSE_EFUSE_MEM_FORCE_PD_V 0x00000001 -#define EFUSE_EFUSE_MEM_FORCE_PD_S 0 - -/* EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; - * If set, forces to activate clock signal of eFuse SRAM. - */ - -#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) -#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001 -#define EFUSE_MEM_CLK_FORCE_ON_S 1 - -/* EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; - * If set, forces eFuse SRAM into working mode. - */ - -#define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2)) -#define EFUSE_EFUSE_MEM_FORCE_PU_M (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S) -#define EFUSE_EFUSE_MEM_FORCE_PU_V 0x00000001 -#define EFUSE_EFUSE_MEM_FORCE_PU_S 2 - -/* EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; - * If set, forces to enable clock signal of eFuse memory. - */ - -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) -#define EFUSE_CLK_EN_V 0x00000001 -#define EFUSE_CLK_EN_S 16 - -/* EFUSE_CONF_REG register - * eFuse operation mode configuration register. - */ - -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) - -/* EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; - * 0x5A5A: Operate programming command; 0x5AA5: Operate read command. - */ - -#define EFUSE_OP_CODE 0x0000FFFF -#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) -#define EFUSE_OP_CODE_V 0x0000FFFF -#define EFUSE_OP_CODE_S 0 - -/* EFUSE_STATUS_REG register - * eFuse status register. - */ - -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) - -/* EFUSE_STATE : RO; bitpos: [3:0]; default: 0; - * Indicates the state of the eFuse state machine. - */ - -#define EFUSE_STATE 0x0000000F -#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) -#define EFUSE_STATE_V 0x0000000F -#define EFUSE_STATE_S 0 - -/* EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; - * The value of OTP_LOAD_SW. - */ - -#define EFUSE_OTP_LOAD_SW (BIT(4)) -#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) -#define EFUSE_OTP_LOAD_SW_V 0x00000001 -#define EFUSE_OTP_LOAD_SW_S 4 - -/* EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; - * The value of OTP_VDDQ_C_SYNC2. - */ - -#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) -#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001 -#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 - -/* EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; - * The value of OTP_STROBE_SW. - */ - -#define EFUSE_OTP_STROBE_SW (BIT(6)) -#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) -#define EFUSE_OTP_STROBE_SW_V 0x00000001 -#define EFUSE_OTP_STROBE_SW_S 6 - -/* EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; - * The value of OTP_CSB_SW. - */ - -#define EFUSE_OTP_CSB_SW (BIT(7)) -#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) -#define EFUSE_OTP_CSB_SW_V 0x00000001 -#define EFUSE_OTP_CSB_SW_S 7 - -/* EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; - * The value of OTP_PGENB_SW. - */ - -#define EFUSE_OTP_PGENB_SW (BIT(8)) -#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) -#define EFUSE_OTP_PGENB_SW_V 0x00000001 -#define EFUSE_OTP_PGENB_SW_S 8 - -/* EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; - * The value of OTP_VDDQ_IS_SW. - */ - -#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) -#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001 -#define EFUSE_OTP_VDDQ_IS_SW_S 9 - -/* EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0; - * Indicates the number of error bits during programming BLOCK0. - */ - -#define EFUSE_REPEAT_ERR_CNT 0x000000FF -#define EFUSE_REPEAT_ERR_CNT_M (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S) -#define EFUSE_REPEAT_ERR_CNT_V 0x000000FF -#define EFUSE_REPEAT_ERR_CNT_S 10 - -/* EFUSE_CMD_REG register - * eFuse command register. - */ - -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) - -/* EFUSE_READ_CMD : R/W; bitpos: [0]; default: 0; - * Set this bit to send read command. - */ - -#define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) -#define EFUSE_READ_CMD_V 0x00000001 -#define EFUSE_READ_CMD_S 0 - -/* EFUSE_PGM_CMD : R/W; bitpos: [1]; default: 0; - * Set this bit to send programming command. - */ - -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) -#define EFUSE_PGM_CMD_V 0x00000001 -#define EFUSE_PGM_CMD_S 1 - -/* EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; - * The serial number of the block to be programmed. Value 0-10 corresponds - * to block number 0-10, respectively. - */ - -#define EFUSE_BLK_NUM 0x0000000F -#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) -#define EFUSE_BLK_NUM_V 0x0000000F -#define EFUSE_BLK_NUM_S 2 - -/* EFUSE_INT_RAW_REG register - * eFuse raw interrupt register. - */ - -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) - -/* EFUSE_READ_DONE_INT_RAW : RO; bitpos: [0]; default: 0; - * The raw bit signal for read_done interrupt. - */ - -#define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) -#define EFUSE_READ_DONE_INT_RAW_V 0x00000001 -#define EFUSE_READ_DONE_INT_RAW_S 0 - -/* EFUSE_PGM_DONE_INT_RAW : RO; bitpos: [1]; default: 0; - * The raw bit signal for pgm_done interrupt. - */ - -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) -#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001 -#define EFUSE_PGM_DONE_INT_RAW_S 1 - -/* EFUSE_INT_ST_REG register - * eFuse interrupt status register. - */ - -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) - -/* EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; - * The status signal for read_done interrupt. - */ - -#define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) -#define EFUSE_READ_DONE_INT_ST_V 0x00000001 -#define EFUSE_READ_DONE_INT_ST_S 0 - -/* EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; - * The status signal for pgm_done interrupt. - */ - -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) -#define EFUSE_PGM_DONE_INT_ST_V 0x00000001 -#define EFUSE_PGM_DONE_INT_ST_S 1 - -/* EFUSE_INT_ENA_REG register - * eFuse interrupt enable register. - */ - -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) - -/* EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; - * The enable signal for read_done interrupt. - */ - -#define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) -#define EFUSE_READ_DONE_INT_ENA_V 0x00000001 -#define EFUSE_READ_DONE_INT_ENA_S 0 - -/* EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; - * The enable signal for pgm_done interrupt. - */ - -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) -#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001 -#define EFUSE_PGM_DONE_INT_ENA_S 1 - -/* EFUSE_INT_CLR_REG register - * eFuse interrupt clear register. - */ - -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) - -/* EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0; - * The clear signal for read_done interrupt. - */ - -#define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) -#define EFUSE_READ_DONE_INT_CLR_V 0x00000001 -#define EFUSE_READ_DONE_INT_CLR_S 0 - -/* EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0; - * The clear signal for pgm_done interrupt. - */ - -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) -#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001 -#define EFUSE_PGM_DONE_INT_CLR_S 1 - -/* EFUSE_DAC_CONF_REG register - * Controls the eFuse programming voltage. - */ - -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) - -/* EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28; - * Controls the division factor of the rising clock of the programming - * voltage. - */ - -#define EFUSE_DAC_CLK_DIV 0x000000FF -#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) -#define EFUSE_DAC_CLK_DIV_V 0x000000FF -#define EFUSE_DAC_CLK_DIV_S 0 - -/* EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; - * Don't care. - */ - -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001 -#define EFUSE_DAC_CLK_PAD_SEL_S 8 - -/* EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; - * Controls the rising period of the programming voltage. - */ - -#define EFUSE_DAC_NUM 0x000000FF -#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) -#define EFUSE_DAC_NUM_V 0x000000FF -#define EFUSE_DAC_NUM_S 9 - -/* EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; - * Reduces the power supply of the programming voltage. - */ - -#define EFUSE_OE_CLR (BIT(17)) -#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) -#define EFUSE_OE_CLR_V 0x00000001 -#define EFUSE_OE_CLR_S 17 - -/* EFUSE_RD_TIM_CONF_REG register - * Configures read timing parameters. - */ - -#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) - -/* EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; - * Configures the hold time of read operation. - */ - -#define EFUSE_THR_A 0x000000FF -#define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) -#define EFUSE_THR_A_V 0x000000FF -#define EFUSE_THR_A_S 0 - -/* EFUSE_TRD : R/W; bitpos: [15:8]; default: 1; - * Configures the length of pulse of read operation. - */ - -#define EFUSE_TRD 0x000000FF -#define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) -#define EFUSE_TRD_V 0x000000FF -#define EFUSE_TRD_S 8 - -/* EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; - * Configures the setup time of read operation. - */ - -#define EFUSE_TSUR_A 0x000000FF -#define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) -#define EFUSE_TSUR_A_V 0x000000FF -#define EFUSE_TSUR_A_S 16 - -/* EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; - * Configures the initial read time of eFuse. - */ - -#define EFUSE_READ_INIT_NUM 0x000000FF -#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) -#define EFUSE_READ_INIT_NUM_V 0x000000FF -#define EFUSE_READ_INIT_NUM_S 24 - -/* EFUSE_WR_TIM_CONF0_REG register - * Configuration register 0 of eFuse programming timing parameters. - */ - -#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1f0) - -/* EFUSE_THP_A : R/W; bitpos: [7:0]; default: 1; - * Configures the hold time of programming operation. - */ - -#define EFUSE_THP_A 0x000000FF -#define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) -#define EFUSE_THP_A_V 0x000000FF -#define EFUSE_THP_A_S 0 - -/* EFUSE_TPGM_INACTIVE : R/W; bitpos: [15:8]; default: 1; - * Configures the length of pulse during programming 0 to eFuse. - */ - -#define EFUSE_TPGM_INACTIVE 0x000000FF -#define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) -#define EFUSE_TPGM_INACTIVE_V 0x000000FF -#define EFUSE_TPGM_INACTIVE_S 8 - -/* EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200; - * Configures the length of pulse during programming 1 to eFuse. - */ - -#define EFUSE_TPGM 0x0000FFFF -#define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) -#define EFUSE_TPGM_V 0x0000FFFF -#define EFUSE_TPGM_S 16 - -/* EFUSE_WR_TIM_CONF1_REG register - * Configuration register 1 of eFuse programming timing parameters. - */ - -#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f4) - -/* EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; - * Configures the setup time of programming operation. - */ - -#define EFUSE_TSUP_A 0x000000FF -#define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) -#define EFUSE_TSUP_A_V 0x000000FF -#define EFUSE_TSUP_A_S 0 - -/* EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368; - * Configures the power up time for VDDQ. - */ - -#define EFUSE_PWR_ON_NUM 0x0000FFFF -#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) -#define EFUSE_PWR_ON_NUM_V 0x0000FFFF -#define EFUSE_PWR_ON_NUM_S 8 - -/* EFUSE_WR_TIM_CONF2_REG register - * Configuration register 2 of eFuse programming timing parameters. - */ - -#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f8) - -/* EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; - * Configures the power outage time for VDDQ. - */ - -#define EFUSE_PWR_OFF_NUM 0x0000FFFF -#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) -#define EFUSE_PWR_OFF_NUM_V 0x0000FFFF -#define EFUSE_PWR_OFF_NUM_S 0 - -/* EFUSE_DATE_REG register - * eFuse version register. - */ - -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) - -/* EFUSE_EFUSE_DATE : R/W; bitpos: [31:0]; default: 419959040; - * Stores eFuse version. - */ - -#define EFUSE_EFUSE_DATE 0xFFFFFFFF -#define EFUSE_EFUSE_DATE_M (EFUSE_EFUSE_DATE_V << EFUSE_EFUSE_DATE_S) -#define EFUSE_EFUSE_DATE_V 0xFFFFFFFF -#define EFUSE_EFUSE_DATE_S 0 - -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_EFUSE_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h deleted file mode 100644 index 588ed1bd7b475..0000000000000 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h +++ /dev/null @@ -1,5314 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_gpio.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_GPIO_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_GPIO_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32c3_soc.h" - -/**************************************************************************** - * Pre-preprocessor Definitions - ****************************************************************************/ - -#define GPIO_REG(io_num) (GPIO_PIN0_REG + ((io_num) * 0x4)) - -#define GPIO_PIN_INT_ENA 0x0000001f -#define GPIO_PIN_INT_ENA_M ((GPIO_PIN_INT_ENA_V)<<(GPIO_PIN_INT_ENA_S)) -#define GPIO_PIN_INT_ENA_V 0x0000001f -#define GPIO_PIN_INT_ENA_S 13 - -#define GPIO_PIN_CONFIG 0x00000003 -#define GPIO_PIN_CONFIG_M ((GPIO_PIN_CONFIG_V)<<(GPIO_PIN_CONFIG_S)) -#define GPIO_PIN_CONFIG_V 0x00000003 -#define GPIO_PIN_CONFIG_S 11 - -#define GPIO_PIN_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN_WAKEUP_ENABLE_S 10 - -#define GPIO_PIN_INT_TYPE 0x00000007 -#define GPIO_PIN_INT_TYPE_M ((GPIO_PIN_INT_TYPE_V)<<(GPIO_PIN_INT_TYPE_S)) -#define GPIO_PIN_INT_TYPE_V 0x00000007 -#define GPIO_PIN_INT_TYPE_S 7 - -#define GPIO_PIN_CONFIG_MSB 12 -#define GPIO_PIN_CONFIG_LSB 11 -#define GPIO_PIN_CONFIG_MASK 0x00001800 -#define GPIO_PIN_CONFIG_GET(x) (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB) -#define GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK) - -#define GPIO_WAKEUP_ENABLE 1 -#define GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE) -#define GPIO_PIN_WAKEUP_ENABLE_MSB 10 -#define GPIO_PIN_WAKEUP_ENABLE_LSB 10 -#define GPIO_PIN_WAKEUP_ENABLE_MASK 0x00000400 -#define GPIO_PIN_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB) -#define GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK) - -#define GPIO_PIN_INT_TYPE_MASK 0x380 -#define GPIO_PIN_INT_TYPE_MSB 9 -#define GPIO_PIN_INT_TYPE_LSB 7 -#define GPIO_PIN_INT_TYPE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB) -#define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK) - -#define GPIO_PIN_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN_SYNC1_BYPASS_M ((GPIO_PIN0_SYNC1_BYPASS_V)<<(GPIO_PIN0_SYNC1_BYPASS_S)) -#define GPIO_PIN_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN_SYNC1_BYPASS_S 3 - -#define GPIO_PIN_PAD_DRIVER (BIT(2)) -#define GPIO_PIN_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN_PAD_DRIVER_V 0x1 -#define GPIO_PIN_PAD_DRIVER_S 2 - -#define GPIO_PIN_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN_SYNC2_BYPASS_M ((GPIO_PIN0_SYNC2_BYPASS_V)<<(GPIO_PIN0_SYNC2_BYPASS_S)) -#define GPIO_PIN_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN_SYNC2_BYPASS_S 0 - -#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0) - -/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ - -#define GPIO_BT_SEL 0xffffffff -#define GPIO_BT_SEL_M ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S)) -#define GPIO_BT_SEL_V 0xffffffff -#define GPIO_BT_SEL_S 0 - -#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) - -/* GPIO_OUT_DATA : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ - -#define GPIO_OUT_DATA 0x03ffffff -#define GPIO_OUT_DATA_M ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S)) -#define GPIO_OUT_DATA_V 0x3ffffff -#define GPIO_OUT_DATA_S 0 - -#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) - -/* GPIO_OUT_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */ - -#define GPIO_OUT_W1TS 0x03ffffff -#define GPIO_OUT_W1TS_M ((GPIO_OUT_W1TS_V)<<(GPIO_OUT_W1TS_S)) -#define GPIO_OUT_W1TS_V 0x3ffffff -#define GPIO_OUT_W1TS_S 0 - -#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xc) - -/* GPIO_OUT_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */ - -#define GPIO_OUT_W1TC 0x03ffffff -#define GPIO_OUT_W1TC_M ((GPIO_OUT_W1TC_V)<<(GPIO_OUT_W1TC_S)) -#define GPIO_OUT_W1TC_V 0x3ffffff -#define GPIO_OUT_W1TC_S 0 - -#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1c) - -/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ - -#define GPIO_SDIO_SEL 0x000000ff -#define GPIO_SDIO_SEL_M ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S)) -#define GPIO_SDIO_SEL_V 0xff -#define GPIO_SDIO_SEL_S 0 - -#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) - -/* GPIO_ENABLE_DATA : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ - -#define GPIO_ENABLE_DATA 0x03ffffff -#define GPIO_ENABLE_DATA_M ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S)) -#define GPIO_ENABLE_DATA_V 0x3ffffff -#define GPIO_ENABLE_DATA_S 0 - -#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) - -/* GPIO_ENABLE_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */ - -#define GPIO_ENABLE_W1TS 0x03ffffff -#define GPIO_ENABLE_W1TS_M ((GPIO_ENABLE_W1TS_V)<<(GPIO_ENABLE_W1TS_S)) -#define GPIO_ENABLE_W1TS_V 0x3ffffff -#define GPIO_ENABLE_W1TS_S 0 - -#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) - -/* GPIO_ENABLE_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */ - -#define GPIO_ENABLE_W1TC 0x03ffffff -#define GPIO_ENABLE_W1TC_M ((GPIO_ENABLE_W1TC_V)<<(GPIO_ENABLE_W1TC_S)) -#define GPIO_ENABLE_W1TC_V 0x3ffffff -#define GPIO_ENABLE_W1TC_S 0 - -#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38) - -/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default: ; */ - -#define GPIO_STRAPPING 0x0000ffff -#define GPIO_STRAPPING_M ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S)) -#define GPIO_STRAPPING_V 0xffff -#define GPIO_STRAPPING_S 0 - -#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3c) - -/* GPIO_IN_DATA : RO ;bitpos:[25:0] ;default: ; */ - -#define GPIO_IN_DATA 0x03ffffff -#define GPIO_IN_DATA_M ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S)) -#define GPIO_IN_DATA_V 0x3ffffff -#define GPIO_IN_DATA_S 0 - -#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) - -/* GPIO_STATUS_INT : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ - -#define GPIO_STATUS_INT 0x03ffffff -#define GPIO_STATUS_INT_M ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S)) -#define GPIO_STATUS_INT_V 0x3ffffff -#define GPIO_STATUS_INT_S 0 - -#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) - -/* GPIO_STATUS_W1TS : WO ;bitpos:[25:0] ;default: 26'h0 ; */ - -#define GPIO_STATUS_W1TS 0x03ffffff -#define GPIO_STATUS_W1TS_M ((GPIO_STATUS_W1TS_V)<<(GPIO_STATUS_W1TS_S)) -#define GPIO_STATUS_W1TS_V 0x3ffffff -#define GPIO_STATUS_W1TS_S 0 - -#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4c) - -/* GPIO_STATUS_W1TC : WO ;bitpos:[25:0] ;default: 26'h0 ; */ - -#define GPIO_STATUS_W1TC 0x03ffffff -#define GPIO_STATUS_W1TC_M ((GPIO_STATUS_W1TC_V)<<(GPIO_STATUS_W1TC_S)) -#define GPIO_STATUS_W1TC_V 0x3ffffff -#define GPIO_STATUS_W1TC_S 0 - -#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5c) - -/* GPIO_PROCPU_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */ - -#define GPIO_PROCPU_INT 0x03ffffff -#define GPIO_PROCPU_INT_M ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S)) -#define GPIO_PROCPU_INT_V 0x3ffffff -#define GPIO_PROCPU_INT_S 0 - -#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) - -/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */ - -#define GPIO_PROCPU_NMI_INT 0x03ffffff -#define GPIO_PROCPU_NMI_INT_M ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S)) -#define GPIO_PROCPU_NMI_INT_V 0x3ffffff -#define GPIO_PROCPU_NMI_INT_S 0 - -#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) - -/* GPIO_SDIO_INT : RO ;bitpos:[25:0] ;default: 26'h0 ; */ - -#define GPIO_SDIO_INT 0x03ffffff -#define GPIO_SDIO_INT_M ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S)) -#define GPIO_SDIO_INT_V 0x3ffffff -#define GPIO_SDIO_INT_S 0 - -#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) - -/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN0_INT_ENA 0x0000001f -#define GPIO_PIN0_INT_ENA_M ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S)) -#define GPIO_PIN0_INT_ENA_V 0x1f -#define GPIO_PIN0_INT_ENA_S 13 - -/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN0_CONFIG 0x00000003 -#define GPIO_PIN0_CONFIG_M ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S)) -#define GPIO_PIN0_CONFIG_V 0x3 -#define GPIO_PIN0_CONFIG_S 11 - -/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN0_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN0_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN0_INT_TYPE 0x00000007 -#define GPIO_PIN0_INT_TYPE_M ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S)) -#define GPIO_PIN0_INT_TYPE_V 0x7 -#define GPIO_PIN0_INT_TYPE_S 7 - -/* GPIO_PIN0_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN0_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN0_SYNC1_BYPASS_M ((GPIO_PIN0_SYNC1_BYPASS_V)<<(GPIO_PIN0_SYNC1_BYPASS_S)) -#define GPIO_PIN0_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN0_SYNC1_BYPASS_S 3 - -/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN_PAD_DRIVER_S 2 - -#define GPIO_PIN0_PAD_DRIVER (BIT(2)) -#define GPIO_PIN0_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN0_PAD_DRIVER_V 0x1 -#define GPIO_PIN0_PAD_DRIVER_S 2 - -/* GPIO_PIN0_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN0_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN0_SYNC2_BYPASS_M ((GPIO_PIN0_SYNC2_BYPASS_V)<<(GPIO_PIN0_SYNC2_BYPASS_S)) -#define GPIO_PIN0_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN0_SYNC2_BYPASS_S 0 - -#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78) - -/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN1_INT_ENA 0x0000001f -#define GPIO_PIN1_INT_ENA_M ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S)) -#define GPIO_PIN1_INT_ENA_V 0x1f -#define GPIO_PIN1_INT_ENA_S 13 - -/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN1_CONFIG 0x00000003 -#define GPIO_PIN1_CONFIG_M ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S)) -#define GPIO_PIN1_CONFIG_V 0x3 -#define GPIO_PIN1_CONFIG_S 11 - -/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN1_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN1_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN1_INT_TYPE 0x00000007 -#define GPIO_PIN1_INT_TYPE_M ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S)) -#define GPIO_PIN1_INT_TYPE_V 0x7 -#define GPIO_PIN1_INT_TYPE_S 7 - -/* GPIO_PIN1_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN1_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN1_SYNC1_BYPASS_M ((GPIO_PIN1_SYNC1_BYPASS_V)<<(GPIO_PIN1_SYNC1_BYPASS_S)) -#define GPIO_PIN1_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN1_SYNC1_BYPASS_S 3 - -/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN1_PAD_DRIVER (BIT(2)) -#define GPIO_PIN1_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN1_PAD_DRIVER_V 0x1 -#define GPIO_PIN1_PAD_DRIVER_S 2 - -/* GPIO_PIN1_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN1_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN1_SYNC2_BYPASS_M ((GPIO_PIN1_SYNC2_BYPASS_V)<<(GPIO_PIN1_SYNC2_BYPASS_S)) -#define GPIO_PIN1_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN1_SYNC2_BYPASS_S 0 - -#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7c) - -/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN2_INT_ENA 0x0000001f -#define GPIO_PIN2_INT_ENA_M ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S)) -#define GPIO_PIN2_INT_ENA_V 0x1f -#define GPIO_PIN2_INT_ENA_S 13 - -/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN2_CONFIG 0x00000003 -#define GPIO_PIN2_CONFIG_M ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S)) -#define GPIO_PIN2_CONFIG_V 0x3 -#define GPIO_PIN2_CONFIG_S 11 - -/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN2_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN2_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN2_INT_TYPE 0x00000007 -#define GPIO_PIN2_INT_TYPE_M ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S)) -#define GPIO_PIN2_INT_TYPE_V 0x7 -#define GPIO_PIN2_INT_TYPE_S 7 - -/* GPIO_PIN2_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN2_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN2_SYNC1_BYPASS_M ((GPIO_PIN2_SYNC1_BYPASS_V)<<(GPIO_PIN2_SYNC1_BYPASS_S)) -#define GPIO_PIN2_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN2_SYNC1_BYPASS_S 3 - -/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN2_PAD_DRIVER (BIT(2)) -#define GPIO_PIN2_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN2_PAD_DRIVER_V 0x1 -#define GPIO_PIN2_PAD_DRIVER_S 2 - -/* GPIO_PIN2_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN2_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN2_SYNC2_BYPASS_M ((GPIO_PIN2_SYNC2_BYPASS_V)<<(GPIO_PIN2_SYNC2_BYPASS_S)) -#define GPIO_PIN2_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN2_SYNC2_BYPASS_S 0 - -#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80) - -/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN3_INT_ENA 0x0000001f -#define GPIO_PIN3_INT_ENA_M ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S)) -#define GPIO_PIN3_INT_ENA_V 0x1f -#define GPIO_PIN3_INT_ENA_S 13 - -/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN3_CONFIG 0x00000003 -#define GPIO_PIN3_CONFIG_M ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S)) -#define GPIO_PIN3_CONFIG_V 0x3 -#define GPIO_PIN3_CONFIG_S 11 - -/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN3_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN3_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN3_INT_TYPE 0x00000007 -#define GPIO_PIN3_INT_TYPE_M ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S)) -#define GPIO_PIN3_INT_TYPE_V 0x7 -#define GPIO_PIN3_INT_TYPE_S 7 - -/* GPIO_PIN3_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN3_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN3_SYNC1_BYPASS_M ((GPIO_PIN3_SYNC1_BYPASS_V)<<(GPIO_PIN3_SYNC1_BYPASS_S)) -#define GPIO_PIN3_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN3_SYNC1_BYPASS_S 3 - -/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN3_PAD_DRIVER (BIT(2)) -#define GPIO_PIN3_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN3_PAD_DRIVER_V 0x1 -#define GPIO_PIN3_PAD_DRIVER_S 2 - -/* GPIO_PIN3_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN3_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN3_SYNC2_BYPASS_M ((GPIO_PIN3_SYNC2_BYPASS_V)<<(GPIO_PIN3_SYNC2_BYPASS_S)) -#define GPIO_PIN3_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN3_SYNC2_BYPASS_S 0 - -#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84) - -/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN4_INT_ENA 0x0000001f -#define GPIO_PIN4_INT_ENA_M ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S)) -#define GPIO_PIN4_INT_ENA_V 0x1f -#define GPIO_PIN4_INT_ENA_S 13 - -/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN4_CONFIG 0x00000003 -#define GPIO_PIN4_CONFIG_M ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S)) -#define GPIO_PIN4_CONFIG_V 0x3 -#define GPIO_PIN4_CONFIG_S 11 - -/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN4_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN4_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN4_INT_TYPE 0x00000007 -#define GPIO_PIN4_INT_TYPE_M ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S)) -#define GPIO_PIN4_INT_TYPE_V 0x7 -#define GPIO_PIN4_INT_TYPE_S 7 - -/* GPIO_PIN4_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN4_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN4_SYNC1_BYPASS_M ((GPIO_PIN4_SYNC1_BYPASS_V)<<(GPIO_PIN4_SYNC1_BYPASS_S)) -#define GPIO_PIN4_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN4_SYNC1_BYPASS_S 3 - -/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN4_PAD_DRIVER (BIT(2)) -#define GPIO_PIN4_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN4_PAD_DRIVER_V 0x1 -#define GPIO_PIN4_PAD_DRIVER_S 2 - -/* GPIO_PIN4_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN4_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN4_SYNC2_BYPASS_M ((GPIO_PIN4_SYNC2_BYPASS_V)<<(GPIO_PIN4_SYNC2_BYPASS_S)) -#define GPIO_PIN4_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN4_SYNC2_BYPASS_S 0 - -#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88) - -/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN5_INT_ENA 0x0000001f -#define GPIO_PIN5_INT_ENA_M ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S)) -#define GPIO_PIN5_INT_ENA_V 0x1f -#define GPIO_PIN5_INT_ENA_S 13 - -/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN5_CONFIG 0x00000003 -#define GPIO_PIN5_CONFIG_M ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S)) -#define GPIO_PIN5_CONFIG_V 0x3 -#define GPIO_PIN5_CONFIG_S 11 - -/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN5_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN5_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN5_INT_TYPE 0x00000007 -#define GPIO_PIN5_INT_TYPE_M ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S)) -#define GPIO_PIN5_INT_TYPE_V 0x7 -#define GPIO_PIN5_INT_TYPE_S 7 - -/* GPIO_PIN5_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN5_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN5_SYNC1_BYPASS_M ((GPIO_PIN5_SYNC1_BYPASS_V)<<(GPIO_PIN5_SYNC1_BYPASS_S)) -#define GPIO_PIN5_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN5_SYNC1_BYPASS_S 3 - -/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN5_PAD_DRIVER (BIT(2)) -#define GPIO_PIN5_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN5_PAD_DRIVER_V 0x1 -#define GPIO_PIN5_PAD_DRIVER_S 2 - -/* GPIO_PIN5_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN5_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN5_SYNC2_BYPASS_M ((GPIO_PIN5_SYNC2_BYPASS_V)<<(GPIO_PIN5_SYNC2_BYPASS_S)) -#define GPIO_PIN5_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN5_SYNC2_BYPASS_S 0 - -#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8c) - -/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN6_INT_ENA 0x0000001f -#define GPIO_PIN6_INT_ENA_M ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S)) -#define GPIO_PIN6_INT_ENA_V 0x1f -#define GPIO_PIN6_INT_ENA_S 13 - -/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN6_CONFIG 0x00000003 -#define GPIO_PIN6_CONFIG_M ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S)) -#define GPIO_PIN6_CONFIG_V 0x3 -#define GPIO_PIN6_CONFIG_S 11 - -/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN6_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN6_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN6_INT_TYPE 0x00000007 -#define GPIO_PIN6_INT_TYPE_M ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S)) -#define GPIO_PIN6_INT_TYPE_V 0x7 -#define GPIO_PIN6_INT_TYPE_S 7 - -/* GPIO_PIN6_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN6_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN6_SYNC1_BYPASS_M ((GPIO_PIN6_SYNC1_BYPASS_V)<<(GPIO_PIN6_SYNC1_BYPASS_S)) -#define GPIO_PIN6_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN6_SYNC1_BYPASS_S 3 - -/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN6_PAD_DRIVER (BIT(2)) -#define GPIO_PIN6_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN6_PAD_DRIVER_V 0x1 -#define GPIO_PIN6_PAD_DRIVER_S 2 - -/* GPIO_PIN6_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN6_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN6_SYNC2_BYPASS_M ((GPIO_PIN6_SYNC2_BYPASS_V)<<(GPIO_PIN6_SYNC2_BYPASS_S)) -#define GPIO_PIN6_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN6_SYNC2_BYPASS_S 0 - -#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90) - -/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN7_INT_ENA 0x0000001f -#define GPIO_PIN7_INT_ENA_M ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S)) -#define GPIO_PIN7_INT_ENA_V 0x1f -#define GPIO_PIN7_INT_ENA_S 13 - -/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN7_CONFIG 0x00000003 -#define GPIO_PIN7_CONFIG_M ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S)) -#define GPIO_PIN7_CONFIG_V 0x3 -#define GPIO_PIN7_CONFIG_S 11 - -/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN7_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN7_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN7_INT_TYPE 0x00000007 -#define GPIO_PIN7_INT_TYPE_M ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S)) -#define GPIO_PIN7_INT_TYPE_V 0x7 -#define GPIO_PIN7_INT_TYPE_S 7 - -/* GPIO_PIN7_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN7_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN7_SYNC1_BYPASS_M ((GPIO_PIN7_SYNC1_BYPASS_V)<<(GPIO_PIN7_SYNC1_BYPASS_S)) -#define GPIO_PIN7_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN7_SYNC1_BYPASS_S 3 - -/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN7_PAD_DRIVER (BIT(2)) -#define GPIO_PIN7_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN7_PAD_DRIVER_V 0x1 -#define GPIO_PIN7_PAD_DRIVER_S 2 - -/* GPIO_PIN7_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN7_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN7_SYNC2_BYPASS_M ((GPIO_PIN7_SYNC2_BYPASS_V)<<(GPIO_PIN7_SYNC2_BYPASS_S)) -#define GPIO_PIN7_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN7_SYNC2_BYPASS_S 0 - -#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94) - -/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN8_INT_ENA 0x0000001f -#define GPIO_PIN8_INT_ENA_M ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S)) -#define GPIO_PIN8_INT_ENA_V 0x1f -#define GPIO_PIN8_INT_ENA_S 13 - -/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN8_CONFIG 0x00000003 -#define GPIO_PIN8_CONFIG_M ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S)) -#define GPIO_PIN8_CONFIG_V 0x3 -#define GPIO_PIN8_CONFIG_S 11 - -/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN8_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN8_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN8_INT_TYPE 0x00000007 -#define GPIO_PIN8_INT_TYPE_M ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S)) -#define GPIO_PIN8_INT_TYPE_V 0x7 -#define GPIO_PIN8_INT_TYPE_S 7 - -/* GPIO_PIN8_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN8_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN8_SYNC1_BYPASS_M ((GPIO_PIN8_SYNC1_BYPASS_V)<<(GPIO_PIN8_SYNC1_BYPASS_S)) -#define GPIO_PIN8_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN8_SYNC1_BYPASS_S 3 - -/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN8_PAD_DRIVER (BIT(2)) -#define GPIO_PIN8_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN8_PAD_DRIVER_V 0x1 -#define GPIO_PIN8_PAD_DRIVER_S 2 - -/* GPIO_PIN8_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN8_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN8_SYNC2_BYPASS_M ((GPIO_PIN8_SYNC2_BYPASS_V)<<(GPIO_PIN8_SYNC2_BYPASS_S)) -#define GPIO_PIN8_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN8_SYNC2_BYPASS_S 0 - -#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98) - -/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN9_INT_ENA 0x0000001f -#define GPIO_PIN9_INT_ENA_M ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S)) -#define GPIO_PIN9_INT_ENA_V 0x1f -#define GPIO_PIN9_INT_ENA_S 13 - -/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN9_CONFIG 0x00000003 -#define GPIO_PIN9_CONFIG_M ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S)) -#define GPIO_PIN9_CONFIG_V 0x3 -#define GPIO_PIN9_CONFIG_S 11 - -/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN9_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN9_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN9_INT_TYPE 0x00000007 -#define GPIO_PIN9_INT_TYPE_M ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S)) -#define GPIO_PIN9_INT_TYPE_V 0x7 -#define GPIO_PIN9_INT_TYPE_S 7 - -/* GPIO_PIN9_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN9_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN9_SYNC1_BYPASS_M ((GPIO_PIN9_SYNC1_BYPASS_V)<<(GPIO_PIN9_SYNC1_BYPASS_S)) -#define GPIO_PIN9_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN9_SYNC1_BYPASS_S 3 - -/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN9_PAD_DRIVER (BIT(2)) -#define GPIO_PIN9_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN9_PAD_DRIVER_V 0x1 -#define GPIO_PIN9_PAD_DRIVER_S 2 - -/* GPIO_PIN9_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN9_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN9_SYNC2_BYPASS_M ((GPIO_PIN9_SYNC2_BYPASS_V)<<(GPIO_PIN9_SYNC2_BYPASS_S)) -#define GPIO_PIN9_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN9_SYNC2_BYPASS_S 0 - -#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9c) - -/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN10_INT_ENA 0x0000001f -#define GPIO_PIN10_INT_ENA_M ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S)) -#define GPIO_PIN10_INT_ENA_V 0x1f -#define GPIO_PIN10_INT_ENA_S 13 - -/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN10_CONFIG 0x00000003 -#define GPIO_PIN10_CONFIG_M ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S)) -#define GPIO_PIN10_CONFIG_V 0x3 -#define GPIO_PIN10_CONFIG_S 11 - -/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN10_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN10_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN10_INT_TYPE 0x00000007 -#define GPIO_PIN10_INT_TYPE_M ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S)) -#define GPIO_PIN10_INT_TYPE_V 0x7 -#define GPIO_PIN10_INT_TYPE_S 7 - -/* GPIO_PIN10_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN10_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN10_SYNC1_BYPASS_M ((GPIO_PIN10_SYNC1_BYPASS_V)<<(GPIO_PIN10_SYNC1_BYPASS_S)) -#define GPIO_PIN10_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN10_SYNC1_BYPASS_S 3 - -/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN10_PAD_DRIVER (BIT(2)) -#define GPIO_PIN10_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN10_PAD_DRIVER_V 0x1 -#define GPIO_PIN10_PAD_DRIVER_S 2 - -/* GPIO_PIN10_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN10_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN10_SYNC2_BYPASS_M ((GPIO_PIN10_SYNC2_BYPASS_V)<<(GPIO_PIN10_SYNC2_BYPASS_S)) -#define GPIO_PIN10_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN10_SYNC2_BYPASS_S 0 - -#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xa0) - -/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN11_INT_ENA 0x0000001f -#define GPIO_PIN11_INT_ENA_M ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S)) -#define GPIO_PIN11_INT_ENA_V 0x1f -#define GPIO_PIN11_INT_ENA_S 13 - -/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN11_CONFIG 0x00000003 -#define GPIO_PIN11_CONFIG_M ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S)) -#define GPIO_PIN11_CONFIG_V 0x3 -#define GPIO_PIN11_CONFIG_S 11 - -/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN11_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN11_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN11_INT_TYPE 0x00000007 -#define GPIO_PIN11_INT_TYPE_M ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S)) -#define GPIO_PIN11_INT_TYPE_V 0x7 -#define GPIO_PIN11_INT_TYPE_S 7 - -/* GPIO_PIN11_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN11_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN11_SYNC1_BYPASS_M ((GPIO_PIN11_SYNC1_BYPASS_V)<<(GPIO_PIN11_SYNC1_BYPASS_S)) -#define GPIO_PIN11_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN11_SYNC1_BYPASS_S 3 - -/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN11_PAD_DRIVER (BIT(2)) -#define GPIO_PIN11_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN11_PAD_DRIVER_V 0x1 -#define GPIO_PIN11_PAD_DRIVER_S 2 - -/* GPIO_PIN11_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN11_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN11_SYNC2_BYPASS_M ((GPIO_PIN11_SYNC2_BYPASS_V)<<(GPIO_PIN11_SYNC2_BYPASS_S)) -#define GPIO_PIN11_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN11_SYNC2_BYPASS_S 0 - -#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xa4) - -/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN12_INT_ENA 0x0000001f -#define GPIO_PIN12_INT_ENA_M ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S)) -#define GPIO_PIN12_INT_ENA_V 0x1f -#define GPIO_PIN12_INT_ENA_S 13 - -/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN12_CONFIG 0x00000003 -#define GPIO_PIN12_CONFIG_M ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S)) -#define GPIO_PIN12_CONFIG_V 0x3 -#define GPIO_PIN12_CONFIG_S 11 - -/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN12_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN12_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN12_INT_TYPE 0x00000007 -#define GPIO_PIN12_INT_TYPE_M ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S)) -#define GPIO_PIN12_INT_TYPE_V 0x7 -#define GPIO_PIN12_INT_TYPE_S 7 - -/* GPIO_PIN12_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN12_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN12_SYNC1_BYPASS_M ((GPIO_PIN12_SYNC1_BYPASS_V)<<(GPIO_PIN12_SYNC1_BYPASS_S)) -#define GPIO_PIN12_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN12_SYNC1_BYPASS_S 3 - -/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN12_PAD_DRIVER (BIT(2)) -#define GPIO_PIN12_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN12_PAD_DRIVER_V 0x1 -#define GPIO_PIN12_PAD_DRIVER_S 2 - -/* GPIO_PIN12_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN12_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN12_SYNC2_BYPASS_M ((GPIO_PIN12_SYNC2_BYPASS_V)<<(GPIO_PIN12_SYNC2_BYPASS_S)) -#define GPIO_PIN12_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN12_SYNC2_BYPASS_S 0 - -#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xa8) - -/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN13_INT_ENA 0x0000001f -#define GPIO_PIN13_INT_ENA_M ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S)) -#define GPIO_PIN13_INT_ENA_V 0x1f -#define GPIO_PIN13_INT_ENA_S 13 - -/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN13_CONFIG 0x00000003 -#define GPIO_PIN13_CONFIG_M ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S)) -#define GPIO_PIN13_CONFIG_V 0x3 -#define GPIO_PIN13_CONFIG_S 11 - -/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN13_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN13_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN13_INT_TYPE 0x00000007 -#define GPIO_PIN13_INT_TYPE_M ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S)) -#define GPIO_PIN13_INT_TYPE_V 0x7 -#define GPIO_PIN13_INT_TYPE_S 7 - -/* GPIO_PIN13_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN13_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN13_SYNC1_BYPASS_M ((GPIO_PIN13_SYNC1_BYPASS_V)<<(GPIO_PIN13_SYNC1_BYPASS_S)) -#define GPIO_PIN13_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN13_SYNC1_BYPASS_S 3 - -/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN13_PAD_DRIVER (BIT(2)) -#define GPIO_PIN13_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN13_PAD_DRIVER_V 0x1 -#define GPIO_PIN13_PAD_DRIVER_S 2 - -/* GPIO_PIN13_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN13_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN13_SYNC2_BYPASS_M ((GPIO_PIN13_SYNC2_BYPASS_V)<<(GPIO_PIN13_SYNC2_BYPASS_S)) -#define GPIO_PIN13_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN13_SYNC2_BYPASS_S 0 - -#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xac) - -/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN14_INT_ENA 0x0000001f -#define GPIO_PIN14_INT_ENA_M ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S)) -#define GPIO_PIN14_INT_ENA_V 0x1f -#define GPIO_PIN14_INT_ENA_S 13 - -/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN14_CONFIG 0x00000003 -#define GPIO_PIN14_CONFIG_M ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S)) -#define GPIO_PIN14_CONFIG_V 0x3 -#define GPIO_PIN14_CONFIG_S 11 - -/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN14_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN14_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN14_INT_TYPE 0x00000007 -#define GPIO_PIN14_INT_TYPE_M ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S)) -#define GPIO_PIN14_INT_TYPE_V 0x7 -#define GPIO_PIN14_INT_TYPE_S 7 - -/* GPIO_PIN14_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN14_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN14_SYNC1_BYPASS_M ((GPIO_PIN14_SYNC1_BYPASS_V)<<(GPIO_PIN14_SYNC1_BYPASS_S)) -#define GPIO_PIN14_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN14_SYNC1_BYPASS_S 3 - -/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN14_PAD_DRIVER (BIT(2)) -#define GPIO_PIN14_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN14_PAD_DRIVER_V 0x1 -#define GPIO_PIN14_PAD_DRIVER_S 2 - -/* GPIO_PIN14_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN14_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN14_SYNC2_BYPASS_M ((GPIO_PIN14_SYNC2_BYPASS_V)<<(GPIO_PIN14_SYNC2_BYPASS_S)) -#define GPIO_PIN14_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN14_SYNC2_BYPASS_S 0 - -#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xb0) - -/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN15_INT_ENA 0x0000001f -#define GPIO_PIN15_INT_ENA_M ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S)) -#define GPIO_PIN15_INT_ENA_V 0x1f -#define GPIO_PIN15_INT_ENA_S 13 - -/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN15_CONFIG 0x00000003 -#define GPIO_PIN15_CONFIG_M ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S)) -#define GPIO_PIN15_CONFIG_V 0x3 -#define GPIO_PIN15_CONFIG_S 11 - -/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN15_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN15_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN15_INT_TYPE 0x00000007 -#define GPIO_PIN15_INT_TYPE_M ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S)) -#define GPIO_PIN15_INT_TYPE_V 0x7 -#define GPIO_PIN15_INT_TYPE_S 7 - -/* GPIO_PIN15_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN15_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN15_SYNC1_BYPASS_M ((GPIO_PIN15_SYNC1_BYPASS_V)<<(GPIO_PIN15_SYNC1_BYPASS_S)) -#define GPIO_PIN15_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN15_SYNC1_BYPASS_S 3 - -/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN15_PAD_DRIVER (BIT(2)) -#define GPIO_PIN15_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN15_PAD_DRIVER_V 0x1 -#define GPIO_PIN15_PAD_DRIVER_S 2 - -/* GPIO_PIN15_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN15_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN15_SYNC2_BYPASS_M ((GPIO_PIN15_SYNC2_BYPASS_V)<<(GPIO_PIN15_SYNC2_BYPASS_S)) -#define GPIO_PIN15_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN15_SYNC2_BYPASS_S 0 - -#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xb4) - -/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN16_INT_ENA 0x0000001f -#define GPIO_PIN16_INT_ENA_M ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S)) -#define GPIO_PIN16_INT_ENA_V 0x1f -#define GPIO_PIN16_INT_ENA_S 13 - -/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN16_CONFIG 0x00000003 -#define GPIO_PIN16_CONFIG_M ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S)) -#define GPIO_PIN16_CONFIG_V 0x3 -#define GPIO_PIN16_CONFIG_S 11 - -/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN16_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN16_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN16_INT_TYPE 0x00000007 -#define GPIO_PIN16_INT_TYPE_M ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S)) -#define GPIO_PIN16_INT_TYPE_V 0x7 -#define GPIO_PIN16_INT_TYPE_S 7 - -/* GPIO_PIN16_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN16_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN16_SYNC1_BYPASS_M ((GPIO_PIN16_SYNC1_BYPASS_V)<<(GPIO_PIN16_SYNC1_BYPASS_S)) -#define GPIO_PIN16_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN16_SYNC1_BYPASS_S 3 - -/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN16_PAD_DRIVER (BIT(2)) -#define GPIO_PIN16_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN16_PAD_DRIVER_V 0x1 -#define GPIO_PIN16_PAD_DRIVER_S 2 - -/* GPIO_PIN16_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN16_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN16_SYNC2_BYPASS_M ((GPIO_PIN16_SYNC2_BYPASS_V)<<(GPIO_PIN16_SYNC2_BYPASS_S)) -#define GPIO_PIN16_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN16_SYNC2_BYPASS_S 0 - -#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xb8) - -/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN17_INT_ENA 0x0000001f -#define GPIO_PIN17_INT_ENA_M ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S)) -#define GPIO_PIN17_INT_ENA_V 0x1f -#define GPIO_PIN17_INT_ENA_S 13 - -/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN17_CONFIG 0x00000003 -#define GPIO_PIN17_CONFIG_M ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S)) -#define GPIO_PIN17_CONFIG_V 0x3 -#define GPIO_PIN17_CONFIG_S 11 - -/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN17_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN17_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN17_INT_TYPE 0x00000007 -#define GPIO_PIN17_INT_TYPE_M ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S)) -#define GPIO_PIN17_INT_TYPE_V 0x7 -#define GPIO_PIN17_INT_TYPE_S 7 - -/* GPIO_PIN17_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN17_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN17_SYNC1_BYPASS_M ((GPIO_PIN17_SYNC1_BYPASS_V)<<(GPIO_PIN17_SYNC1_BYPASS_S)) -#define GPIO_PIN17_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN17_SYNC1_BYPASS_S 3 - -/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN17_PAD_DRIVER (BIT(2)) -#define GPIO_PIN17_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN17_PAD_DRIVER_V 0x1 -#define GPIO_PIN17_PAD_DRIVER_S 2 - -/* GPIO_PIN17_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN17_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN17_SYNC2_BYPASS_M ((GPIO_PIN17_SYNC2_BYPASS_V)<<(GPIO_PIN17_SYNC2_BYPASS_S)) -#define GPIO_PIN17_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN17_SYNC2_BYPASS_S 0 - -#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xbc) - -/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN18_INT_ENA 0x0000001f -#define GPIO_PIN18_INT_ENA_M ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S)) -#define GPIO_PIN18_INT_ENA_V 0x1f -#define GPIO_PIN18_INT_ENA_S 13 - -/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN18_CONFIG 0x00000003 -#define GPIO_PIN18_CONFIG_M ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S)) -#define GPIO_PIN18_CONFIG_V 0x3 -#define GPIO_PIN18_CONFIG_S 11 - -/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN18_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN18_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN18_INT_TYPE 0x00000007 -#define GPIO_PIN18_INT_TYPE_M ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S)) -#define GPIO_PIN18_INT_TYPE_V 0x7 -#define GPIO_PIN18_INT_TYPE_S 7 - -/* GPIO_PIN18_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN18_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN18_SYNC1_BYPASS_M ((GPIO_PIN18_SYNC1_BYPASS_V)<<(GPIO_PIN18_SYNC1_BYPASS_S)) -#define GPIO_PIN18_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN18_SYNC1_BYPASS_S 3 - -/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN18_PAD_DRIVER (BIT(2)) -#define GPIO_PIN18_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN18_PAD_DRIVER_V 0x1 -#define GPIO_PIN18_PAD_DRIVER_S 2 - -/* GPIO_PIN18_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN18_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN18_SYNC2_BYPASS_M ((GPIO_PIN18_SYNC2_BYPASS_V)<<(GPIO_PIN18_SYNC2_BYPASS_S)) -#define GPIO_PIN18_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN18_SYNC2_BYPASS_S 0 - -#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xc0) - -/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN19_INT_ENA 0x0000001f -#define GPIO_PIN19_INT_ENA_M ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S)) -#define GPIO_PIN19_INT_ENA_V 0x1f -#define GPIO_PIN19_INT_ENA_S 13 - -/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN19_CONFIG 0x00000003 -#define GPIO_PIN19_CONFIG_M ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S)) -#define GPIO_PIN19_CONFIG_V 0x3 -#define GPIO_PIN19_CONFIG_S 11 - -/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN19_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN19_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN19_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN19_INT_TYPE 0x00000007 -#define GPIO_PIN19_INT_TYPE_M ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S)) -#define GPIO_PIN19_INT_TYPE_V 0x7 -#define GPIO_PIN19_INT_TYPE_S 7 - -/* GPIO_PIN19_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN19_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN19_SYNC1_BYPASS_M ((GPIO_PIN19_SYNC1_BYPASS_V)<<(GPIO_PIN19_SYNC1_BYPASS_S)) -#define GPIO_PIN19_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN19_SYNC1_BYPASS_S 3 - -/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN19_PAD_DRIVER (BIT(2)) -#define GPIO_PIN19_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN19_PAD_DRIVER_V 0x1 -#define GPIO_PIN19_PAD_DRIVER_S 2 - -/* GPIO_PIN19_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN19_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN19_SYNC2_BYPASS_M ((GPIO_PIN19_SYNC2_BYPASS_V)<<(GPIO_PIN19_SYNC2_BYPASS_S)) -#define GPIO_PIN19_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN19_SYNC2_BYPASS_S 0 - -#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xc4) - -/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN20_INT_ENA 0x0000001f -#define GPIO_PIN20_INT_ENA_M ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S)) -#define GPIO_PIN20_INT_ENA_V 0x1f -#define GPIO_PIN20_INT_ENA_S 13 - -/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN20_CONFIG 0x00000003 -#define GPIO_PIN20_CONFIG_M ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S)) -#define GPIO_PIN20_CONFIG_V 0x3 -#define GPIO_PIN20_CONFIG_S 11 - -/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN20_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN20_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN20_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN20_INT_TYPE 0x00000007 -#define GPIO_PIN20_INT_TYPE_M ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S)) -#define GPIO_PIN20_INT_TYPE_V 0x7 -#define GPIO_PIN20_INT_TYPE_S 7 - -/* GPIO_PIN20_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN20_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN20_SYNC1_BYPASS_M ((GPIO_PIN20_SYNC1_BYPASS_V)<<(GPIO_PIN20_SYNC1_BYPASS_S)) -#define GPIO_PIN20_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN20_SYNC1_BYPASS_S 3 - -/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN20_PAD_DRIVER (BIT(2)) -#define GPIO_PIN20_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN20_PAD_DRIVER_V 0x1 -#define GPIO_PIN20_PAD_DRIVER_S 2 - -/* GPIO_PIN20_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN20_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN20_SYNC2_BYPASS_M ((GPIO_PIN20_SYNC2_BYPASS_V)<<(GPIO_PIN20_SYNC2_BYPASS_S)) -#define GPIO_PIN20_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN20_SYNC2_BYPASS_S 0 - -#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xc8) - -/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN21_INT_ENA 0x0000001f -#define GPIO_PIN21_INT_ENA_M ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S)) -#define GPIO_PIN21_INT_ENA_V 0x1f -#define GPIO_PIN21_INT_ENA_S 13 - -/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN21_CONFIG 0x00000003 -#define GPIO_PIN21_CONFIG_M ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S)) -#define GPIO_PIN21_CONFIG_V 0x3 -#define GPIO_PIN21_CONFIG_S 11 - -/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN21_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN21_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN21_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN21_INT_TYPE 0x00000007 -#define GPIO_PIN21_INT_TYPE_M ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S)) -#define GPIO_PIN21_INT_TYPE_V 0x7 -#define GPIO_PIN21_INT_TYPE_S 7 - -/* GPIO_PIN21_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN21_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN21_SYNC1_BYPASS_M ((GPIO_PIN21_SYNC1_BYPASS_V)<<(GPIO_PIN21_SYNC1_BYPASS_S)) -#define GPIO_PIN21_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN21_SYNC1_BYPASS_S 3 - -/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN21_PAD_DRIVER (BIT(2)) -#define GPIO_PIN21_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN21_PAD_DRIVER_V 0x1 -#define GPIO_PIN21_PAD_DRIVER_S 2 - -/* GPIO_PIN21_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN21_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN21_SYNC2_BYPASS_M ((GPIO_PIN21_SYNC2_BYPASS_V)<<(GPIO_PIN21_SYNC2_BYPASS_S)) -#define GPIO_PIN21_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN21_SYNC2_BYPASS_S 0 - -#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xcc) - -/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN22_INT_ENA 0x0000001f -#define GPIO_PIN22_INT_ENA_M ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S)) -#define GPIO_PIN22_INT_ENA_V 0x1f -#define GPIO_PIN22_INT_ENA_S 13 - -/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN22_CONFIG 0x00000003 -#define GPIO_PIN22_CONFIG_M ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S)) -#define GPIO_PIN22_CONFIG_V 0x3 -#define GPIO_PIN22_CONFIG_S 11 - -/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN22_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN22_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN22_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN22_INT_TYPE 0x00000007 -#define GPIO_PIN22_INT_TYPE_M ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S)) -#define GPIO_PIN22_INT_TYPE_V 0x7 -#define GPIO_PIN22_INT_TYPE_S 7 - -/* GPIO_PIN22_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN22_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN22_SYNC1_BYPASS_M ((GPIO_PIN22_SYNC1_BYPASS_V)<<(GPIO_PIN22_SYNC1_BYPASS_S)) -#define GPIO_PIN22_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN22_SYNC1_BYPASS_S 3 - -/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN22_PAD_DRIVER (BIT(2)) -#define GPIO_PIN22_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN22_PAD_DRIVER_V 0x1 -#define GPIO_PIN22_PAD_DRIVER_S 2 - -/* GPIO_PIN22_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN22_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN22_SYNC2_BYPASS_M ((GPIO_PIN22_SYNC2_BYPASS_V)<<(GPIO_PIN22_SYNC2_BYPASS_S)) -#define GPIO_PIN22_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN22_SYNC2_BYPASS_S 0 - -#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xd0) - -/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN23_INT_ENA 0x0000001f -#define GPIO_PIN23_INT_ENA_M ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S)) -#define GPIO_PIN23_INT_ENA_V 0x1f -#define GPIO_PIN23_INT_ENA_S 13 - -/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN23_CONFIG 0x00000003 -#define GPIO_PIN23_CONFIG_M ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S)) -#define GPIO_PIN23_CONFIG_V 0x3 -#define GPIO_PIN23_CONFIG_S 11 - -/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN23_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN23_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN23_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN23_INT_TYPE 0x00000007 -#define GPIO_PIN23_INT_TYPE_M ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S)) -#define GPIO_PIN23_INT_TYPE_V 0x7 -#define GPIO_PIN23_INT_TYPE_S 7 - -/* GPIO_PIN23_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN23_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN23_SYNC1_BYPASS_M ((GPIO_PIN23_SYNC1_BYPASS_V)<<(GPIO_PIN23_SYNC1_BYPASS_S)) -#define GPIO_PIN23_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN23_SYNC1_BYPASS_S 3 - -/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN23_PAD_DRIVER (BIT(2)) -#define GPIO_PIN23_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN23_PAD_DRIVER_V 0x1 -#define GPIO_PIN23_PAD_DRIVER_S 2 - -/* GPIO_PIN23_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN23_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN23_SYNC2_BYPASS_M ((GPIO_PIN23_SYNC2_BYPASS_V)<<(GPIO_PIN23_SYNC2_BYPASS_S)) -#define GPIO_PIN23_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN23_SYNC2_BYPASS_S 0 - -#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xd4) - -/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN24_INT_ENA 0x0000001f -#define GPIO_PIN24_INT_ENA_M ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S)) -#define GPIO_PIN24_INT_ENA_V 0x1f -#define GPIO_PIN24_INT_ENA_S 13 - -/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN24_CONFIG 0x00000003 -#define GPIO_PIN24_CONFIG_M ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S)) -#define GPIO_PIN24_CONFIG_V 0x3 -#define GPIO_PIN24_CONFIG_S 11 - -/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN24_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN24_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN24_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN24_INT_TYPE 0x00000007 -#define GPIO_PIN24_INT_TYPE_M ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S)) -#define GPIO_PIN24_INT_TYPE_V 0x7 -#define GPIO_PIN24_INT_TYPE_S 7 - -/* GPIO_PIN24_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN24_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN24_SYNC1_BYPASS_M ((GPIO_PIN24_SYNC1_BYPASS_V)<<(GPIO_PIN24_SYNC1_BYPASS_S)) -#define GPIO_PIN24_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN24_SYNC1_BYPASS_S 3 - -/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN24_PAD_DRIVER (BIT(2)) -#define GPIO_PIN24_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN24_PAD_DRIVER_V 0x1 -#define GPIO_PIN24_PAD_DRIVER_S 2 - -/* GPIO_PIN24_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN24_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN24_SYNC2_BYPASS_M ((GPIO_PIN24_SYNC2_BYPASS_V)<<(GPIO_PIN24_SYNC2_BYPASS_S)) -#define GPIO_PIN24_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN24_SYNC2_BYPASS_S 0 - -#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xd8) - -/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ - -#define GPIO_PIN25_INT_ENA 0x0000001f -#define GPIO_PIN25_INT_ENA_M ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S)) -#define GPIO_PIN25_INT_ENA_V 0x1f -#define GPIO_PIN25_INT_ENA_S 13 - -/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ - -#define GPIO_PIN25_CONFIG 0x00000003 -#define GPIO_PIN25_CONFIG_M ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S)) -#define GPIO_PIN25_CONFIG_V 0x3 -#define GPIO_PIN25_CONFIG_S 11 - -/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) -#define GPIO_PIN25_WAKEUP_ENABLE_M (BIT(10)) -#define GPIO_PIN25_WAKEUP_ENABLE_V 0x1 -#define GPIO_PIN25_WAKEUP_ENABLE_S 10 - -/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ - -#define GPIO_PIN25_INT_TYPE 0x00000007 -#define GPIO_PIN25_INT_TYPE_M ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S)) -#define GPIO_PIN25_INT_TYPE_V 0x7 -#define GPIO_PIN25_INT_TYPE_S 7 - -/* GPIO_PIN25_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ - -#define GPIO_PIN25_SYNC1_BYPASS 0x00000003 -#define GPIO_PIN25_SYNC1_BYPASS_M ((GPIO_PIN25_SYNC1_BYPASS_V)<<(GPIO_PIN25_SYNC1_BYPASS_S)) -#define GPIO_PIN25_SYNC1_BYPASS_V 0x3 -#define GPIO_PIN25_SYNC1_BYPASS_S 3 - -/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -#define GPIO_PIN25_PAD_DRIVER (BIT(2)) -#define GPIO_PIN25_PAD_DRIVER_M (BIT(2)) -#define GPIO_PIN25_PAD_DRIVER_V 0x1 -#define GPIO_PIN25_PAD_DRIVER_S 2 - -/* GPIO_PIN25_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -#define GPIO_PIN25_SYNC2_BYPASS 0x00000003 -#define GPIO_PIN25_SYNC2_BYPASS_M ((GPIO_PIN25_SYNC2_BYPASS_V)<<(GPIO_PIN25_SYNC2_BYPASS_S)) -#define GPIO_PIN25_SYNC2_BYPASS_V 0x3 -#define GPIO_PIN25_SYNC2_BYPASS_S 0 - -#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14c) - -/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[25:0] ;default: 26'h0 ; */ - -#define GPIO_STATUS_INTERRUPT_NEXT 0x03ffffff -#define GPIO_STATUS_INTERRUPT_NEXT_M ((GPIO_STATUS_INTERRUPT_NEXT_V)<<(GPIO_STATUS_INTERRUPT_NEXT_S)) -#define GPIO_STATUS_INTERRUPT_NEXT_V 0x3ffffff -#define GPIO_STATUS_INTERRUPT_NEXT_S 0 - -#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) - -/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG0_IN_SEL (BIT(6)) -#define GPIO_SIG0_IN_SEL_M (BIT(6)) -#define GPIO_SIG0_IN_SEL_V 0x1 -#define GPIO_SIG0_IN_SEL_S 6 - -/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC0_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC0_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC0_IN_INV_SEL_V 0x1 -#define GPIO_FUNC0_IN_INV_SEL_S 5 - -/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC0_IN_SEL 0x0000001f -#define GPIO_FUNC0_IN_SEL_M ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S)) -#define GPIO_FUNC0_IN_SEL_V 0x1f -#define GPIO_FUNC0_IN_SEL_S 0 - -#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x158) - -/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG1_IN_SEL (BIT(6)) -#define GPIO_SIG1_IN_SEL_M (BIT(6)) -#define GPIO_SIG1_IN_SEL_V 0x1 -#define GPIO_SIG1_IN_SEL_S 6 - -/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC1_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC1_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC1_IN_INV_SEL_V 0x1 -#define GPIO_FUNC1_IN_INV_SEL_S 5 - -/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC1_IN_SEL 0x0000001f -#define GPIO_FUNC1_IN_SEL_M ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S)) -#define GPIO_FUNC1_IN_SEL_V 0x1f -#define GPIO_FUNC1_IN_SEL_S 0 - -#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15c) - -/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG2_IN_SEL (BIT(6)) -#define GPIO_SIG2_IN_SEL_M (BIT(6)) -#define GPIO_SIG2_IN_SEL_V 0x1 -#define GPIO_SIG2_IN_SEL_S 6 - -/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC2_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC2_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC2_IN_INV_SEL_V 0x1 -#define GPIO_FUNC2_IN_INV_SEL_S 5 - -/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC2_IN_SEL 0x0000001f -#define GPIO_FUNC2_IN_SEL_M ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S)) -#define GPIO_FUNC2_IN_SEL_V 0x1f -#define GPIO_FUNC2_IN_SEL_S 0 - -#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160) - -/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG3_IN_SEL (BIT(6)) -#define GPIO_SIG3_IN_SEL_M (BIT(6)) -#define GPIO_SIG3_IN_SEL_V 0x1 -#define GPIO_SIG3_IN_SEL_S 6 - -/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC3_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC3_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC3_IN_INV_SEL_V 0x1 -#define GPIO_FUNC3_IN_INV_SEL_S 5 - -/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC3_IN_SEL 0x0000001f -#define GPIO_FUNC3_IN_SEL_M ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S)) -#define GPIO_FUNC3_IN_SEL_V 0x1f -#define GPIO_FUNC3_IN_SEL_S 0 - -#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164) - -/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG4_IN_SEL (BIT(6)) -#define GPIO_SIG4_IN_SEL_M (BIT(6)) -#define GPIO_SIG4_IN_SEL_V 0x1 -#define GPIO_SIG4_IN_SEL_S 6 - -/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC4_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC4_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC4_IN_INV_SEL_V 0x1 -#define GPIO_FUNC4_IN_INV_SEL_S 5 - -/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC4_IN_SEL 0x0000001f -#define GPIO_FUNC4_IN_SEL_M ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S)) -#define GPIO_FUNC4_IN_SEL_V 0x1f -#define GPIO_FUNC4_IN_SEL_S 0 - -#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168) - -/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG5_IN_SEL (BIT(6)) -#define GPIO_SIG5_IN_SEL_M (BIT(6)) -#define GPIO_SIG5_IN_SEL_V 0x1 -#define GPIO_SIG5_IN_SEL_S 6 - -/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC5_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC5_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC5_IN_INV_SEL_V 0x1 -#define GPIO_FUNC5_IN_INV_SEL_S 5 - -/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC5_IN_SEL 0x0000001f -#define GPIO_FUNC5_IN_SEL_M ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S)) -#define GPIO_FUNC5_IN_SEL_V 0x1f -#define GPIO_FUNC5_IN_SEL_S 0 - -#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16c) - -/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG6_IN_SEL (BIT(6)) -#define GPIO_SIG6_IN_SEL_M (BIT(6)) -#define GPIO_SIG6_IN_SEL_V 0x1 -#define GPIO_SIG6_IN_SEL_S 6 - -/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC6_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC6_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC6_IN_INV_SEL_V 0x1 -#define GPIO_FUNC6_IN_INV_SEL_S 5 - -/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC6_IN_SEL 0x0000001f -#define GPIO_FUNC6_IN_SEL_M ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S)) -#define GPIO_FUNC6_IN_SEL_V 0x1f -#define GPIO_FUNC6_IN_SEL_S 0 - -#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) - -/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG7_IN_SEL (BIT(6)) -#define GPIO_SIG7_IN_SEL_M (BIT(6)) -#define GPIO_SIG7_IN_SEL_V 0x1 -#define GPIO_SIG7_IN_SEL_S 6 - -/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC7_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC7_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC7_IN_INV_SEL_V 0x1 -#define GPIO_FUNC7_IN_INV_SEL_S 5 - -/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC7_IN_SEL 0x0000001f -#define GPIO_FUNC7_IN_SEL_M ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S)) -#define GPIO_FUNC7_IN_SEL_V 0x1f -#define GPIO_FUNC7_IN_SEL_S 0 - -#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) - -/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG8_IN_SEL (BIT(6)) -#define GPIO_SIG8_IN_SEL_M (BIT(6)) -#define GPIO_SIG8_IN_SEL_V 0x1 -#define GPIO_SIG8_IN_SEL_S 6 - -/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC8_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC8_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC8_IN_INV_SEL_V 0x1 -#define GPIO_FUNC8_IN_INV_SEL_S 5 - -/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC8_IN_SEL 0x0000001f -#define GPIO_FUNC8_IN_SEL_M ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S)) -#define GPIO_FUNC8_IN_SEL_V 0x1f -#define GPIO_FUNC8_IN_SEL_S 0 - -#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) - -/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG9_IN_SEL (BIT(6)) -#define GPIO_SIG9_IN_SEL_M (BIT(6)) -#define GPIO_SIG9_IN_SEL_V 0x1 -#define GPIO_SIG9_IN_SEL_S 6 - -/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC9_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC9_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC9_IN_INV_SEL_V 0x1 -#define GPIO_FUNC9_IN_INV_SEL_S 5 - -/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC9_IN_SEL 0x0000001f -#define GPIO_FUNC9_IN_SEL_M ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S)) -#define GPIO_FUNC9_IN_SEL_V 0x1f -#define GPIO_FUNC9_IN_SEL_S 0 - -#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17c) - -/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG10_IN_SEL (BIT(6)) -#define GPIO_SIG10_IN_SEL_M (BIT(6)) -#define GPIO_SIG10_IN_SEL_V 0x1 -#define GPIO_SIG10_IN_SEL_S 6 - -/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC10_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC10_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC10_IN_INV_SEL_V 0x1 -#define GPIO_FUNC10_IN_INV_SEL_S 5 - -/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC10_IN_SEL 0x0000001f -#define GPIO_FUNC10_IN_SEL_M ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S)) -#define GPIO_FUNC10_IN_SEL_V 0x1f -#define GPIO_FUNC10_IN_SEL_S 0 - -#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) - -/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG11_IN_SEL (BIT(6)) -#define GPIO_SIG11_IN_SEL_M (BIT(6)) -#define GPIO_SIG11_IN_SEL_V 0x1 -#define GPIO_SIG11_IN_SEL_S 6 - -/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC11_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC11_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC11_IN_INV_SEL_V 0x1 -#define GPIO_FUNC11_IN_INV_SEL_S 5 - -/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC11_IN_SEL 0x0000001f -#define GPIO_FUNC11_IN_SEL_M ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S)) -#define GPIO_FUNC11_IN_SEL_V 0x1f -#define GPIO_FUNC11_IN_SEL_S 0 - -#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) - -/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG12_IN_SEL (BIT(6)) -#define GPIO_SIG12_IN_SEL_M (BIT(6)) -#define GPIO_SIG12_IN_SEL_V 0x1 -#define GPIO_SIG12_IN_SEL_S 6 - -/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC12_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC12_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC12_IN_INV_SEL_V 0x1 -#define GPIO_FUNC12_IN_INV_SEL_S 5 - -/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC12_IN_SEL 0x0000001f -#define GPIO_FUNC12_IN_SEL_M ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S)) -#define GPIO_FUNC12_IN_SEL_V 0x1f -#define GPIO_FUNC12_IN_SEL_S 0 - -#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) - -/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG13_IN_SEL (BIT(6)) -#define GPIO_SIG13_IN_SEL_M (BIT(6)) -#define GPIO_SIG13_IN_SEL_V 0x1 -#define GPIO_SIG13_IN_SEL_S 6 - -/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC13_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC13_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC13_IN_INV_SEL_V 0x1 -#define GPIO_FUNC13_IN_INV_SEL_S 5 - -/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC13_IN_SEL 0x0000001f -#define GPIO_FUNC13_IN_SEL_M ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S)) -#define GPIO_FUNC13_IN_SEL_V 0x1f -#define GPIO_FUNC13_IN_SEL_S 0 - -#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18c) - -/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG14_IN_SEL (BIT(6)) -#define GPIO_SIG14_IN_SEL_M (BIT(6)) -#define GPIO_SIG14_IN_SEL_V 0x1 -#define GPIO_SIG14_IN_SEL_S 6 - -/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC14_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC14_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC14_IN_INV_SEL_V 0x1 -#define GPIO_FUNC14_IN_INV_SEL_S 5 - -/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC14_IN_SEL 0x0000001f -#define GPIO_FUNC14_IN_SEL_M ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S)) -#define GPIO_FUNC14_IN_SEL_V 0x1f -#define GPIO_FUNC14_IN_SEL_S 0 - -#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) - -/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG15_IN_SEL (BIT(6)) -#define GPIO_SIG15_IN_SEL_M (BIT(6)) -#define GPIO_SIG15_IN_SEL_V 0x1 -#define GPIO_SIG15_IN_SEL_S 6 - -/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC15_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC15_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC15_IN_INV_SEL_V 0x1 -#define GPIO_FUNC15_IN_INV_SEL_S 5 - -/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC15_IN_SEL 0x0000001f -#define GPIO_FUNC15_IN_SEL_M ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S)) -#define GPIO_FUNC15_IN_SEL_V 0x1f -#define GPIO_FUNC15_IN_SEL_S 0 - -#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) - -/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG16_IN_SEL (BIT(6)) -#define GPIO_SIG16_IN_SEL_M (BIT(6)) -#define GPIO_SIG16_IN_SEL_V 0x1 -#define GPIO_SIG16_IN_SEL_S 6 - -/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC16_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC16_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC16_IN_INV_SEL_V 0x1 -#define GPIO_FUNC16_IN_INV_SEL_S 5 - -/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC16_IN_SEL 0x0000001f -#define GPIO_FUNC16_IN_SEL_M ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S)) -#define GPIO_FUNC16_IN_SEL_V 0x1f -#define GPIO_FUNC16_IN_SEL_S 0 - -#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) - -/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG17_IN_SEL (BIT(6)) -#define GPIO_SIG17_IN_SEL_M (BIT(6)) -#define GPIO_SIG17_IN_SEL_V 0x1 -#define GPIO_SIG17_IN_SEL_S 6 - -/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC17_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC17_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC17_IN_INV_SEL_V 0x1 -#define GPIO_FUNC17_IN_INV_SEL_S 5 - -/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC17_IN_SEL 0x0000001f - -#define GPIO_FUNC17_IN_SEL_M ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S)) -#define GPIO_FUNC17_IN_SEL_V 0x1f -#define GPIO_FUNC17_IN_SEL_S 0 - -#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19c) - -/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG18_IN_SEL (BIT(6)) -#define GPIO_SIG18_IN_SEL_M (BIT(6)) -#define GPIO_SIG18_IN_SEL_V 0x1 -#define GPIO_SIG18_IN_SEL_S 6 - -/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC18_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC18_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC18_IN_INV_SEL_V 0x1 -#define GPIO_FUNC18_IN_INV_SEL_S 5 - -/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC18_IN_SEL 0x0000001f -#define GPIO_FUNC18_IN_SEL_M ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S)) -#define GPIO_FUNC18_IN_SEL_V 0x1f -#define GPIO_FUNC18_IN_SEL_S 0 - -#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a0) - -/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG19_IN_SEL (BIT(6)) -#define GPIO_SIG19_IN_SEL_M (BIT(6)) -#define GPIO_SIG19_IN_SEL_V 0x1 -#define GPIO_SIG19_IN_SEL_S 6 - -/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC19_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC19_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC19_IN_INV_SEL_V 0x1 -#define GPIO_FUNC19_IN_INV_SEL_S 5 - -/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC19_IN_SEL 0x0000001f -#define GPIO_FUNC19_IN_SEL_M ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S)) -#define GPIO_FUNC19_IN_SEL_V 0x1f -#define GPIO_FUNC19_IN_SEL_S 0 - -#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a4) - -/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG20_IN_SEL (BIT(6)) -#define GPIO_SIG20_IN_SEL_M (BIT(6)) -#define GPIO_SIG20_IN_SEL_V 0x1 -#define GPIO_SIG20_IN_SEL_S 6 - -/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC20_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC20_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC20_IN_INV_SEL_V 0x1 -#define GPIO_FUNC20_IN_INV_SEL_S 5 - -/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC20_IN_SEL 0x0000001f -#define GPIO_FUNC20_IN_SEL_M ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S)) -#define GPIO_FUNC20_IN_SEL_V 0x1f -#define GPIO_FUNC20_IN_SEL_S 0 - -#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1a8) - -/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG21_IN_SEL (BIT(6)) -#define GPIO_SIG21_IN_SEL_M (BIT(6)) -#define GPIO_SIG21_IN_SEL_V 0x1 -#define GPIO_SIG21_IN_SEL_S 6 - -/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC21_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC21_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC21_IN_INV_SEL_V 0x1 -#define GPIO_FUNC21_IN_INV_SEL_S 5 - -/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC21_IN_SEL 0x0000001f -#define GPIO_FUNC21_IN_SEL_M ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S)) -#define GPIO_FUNC21_IN_SEL_V 0x1f -#define GPIO_FUNC21_IN_SEL_S 0 - -#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ac) - -/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG22_IN_SEL (BIT(6)) -#define GPIO_SIG22_IN_SEL_M (BIT(6)) -#define GPIO_SIG22_IN_SEL_V 0x1 -#define GPIO_SIG22_IN_SEL_S 6 - -/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC22_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC22_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC22_IN_INV_SEL_V 0x1 -#define GPIO_FUNC22_IN_INV_SEL_S 5 - -/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC22_IN_SEL 0x0000001f -#define GPIO_FUNC22_IN_SEL_M ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S)) -#define GPIO_FUNC22_IN_SEL_V 0x1f -#define GPIO_FUNC22_IN_SEL_S 0 - -#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b0) - -/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG23_IN_SEL (BIT(6)) -#define GPIO_SIG23_IN_SEL_M (BIT(6)) -#define GPIO_SIG23_IN_SEL_V 0x1 -#define GPIO_SIG23_IN_SEL_S 6 - -/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC23_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC23_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC23_IN_INV_SEL_V 0x1 -#define GPIO_FUNC23_IN_INV_SEL_S 5 - -/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC23_IN_SEL 0x0000001f -#define GPIO_FUNC23_IN_SEL_M ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S)) -#define GPIO_FUNC23_IN_SEL_V 0x1f -#define GPIO_FUNC23_IN_SEL_S 0 - -#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b4) - -/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG24_IN_SEL (BIT(6)) -#define GPIO_SIG24_IN_SEL_M (BIT(6)) -#define GPIO_SIG24_IN_SEL_V 0x1 -#define GPIO_SIG24_IN_SEL_S 6 - -/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC24_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC24_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC24_IN_INV_SEL_V 0x1 -#define GPIO_FUNC24_IN_INV_SEL_S 5 - -/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC24_IN_SEL 0x0000001f -#define GPIO_FUNC24_IN_SEL_M ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S)) -#define GPIO_FUNC24_IN_SEL_V 0x1f -#define GPIO_FUNC24_IN_SEL_S 0 - -#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1b8) - -/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG25_IN_SEL (BIT(6)) -#define GPIO_SIG25_IN_SEL_M (BIT(6)) -#define GPIO_SIG25_IN_SEL_V 0x1 -#define GPIO_SIG25_IN_SEL_S 6 - -/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC25_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC25_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC25_IN_INV_SEL_V 0x1 -#define GPIO_FUNC25_IN_INV_SEL_S 5 - -/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC25_IN_SEL 0x0000001f -#define GPIO_FUNC25_IN_SEL_M ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S)) -#define GPIO_FUNC25_IN_SEL_V 0x1f -#define GPIO_FUNC25_IN_SEL_S 0 - -#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1bc) - -/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG26_IN_SEL (BIT(6)) -#define GPIO_SIG26_IN_SEL_M (BIT(6)) -#define GPIO_SIG26_IN_SEL_V 0x1 -#define GPIO_SIG26_IN_SEL_S 6 - -/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC26_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC26_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC26_IN_INV_SEL_V 0x1 -#define GPIO_FUNC26_IN_INV_SEL_S 5 - -/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC26_IN_SEL 0x0000001f -#define GPIO_FUNC26_IN_SEL_M ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S)) -#define GPIO_FUNC26_IN_SEL_V 0x1f -#define GPIO_FUNC26_IN_SEL_S 0 - -#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c0) - -/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG27_IN_SEL (BIT(6)) -#define GPIO_SIG27_IN_SEL_M (BIT(6)) -#define GPIO_SIG27_IN_SEL_V 0x1 -#define GPIO_SIG27_IN_SEL_S 6 - -/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC27_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC27_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC27_IN_INV_SEL_V 0x1 -#define GPIO_FUNC27_IN_INV_SEL_S 5 - -/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC27_IN_SEL 0x0000001f -#define GPIO_FUNC27_IN_SEL_M ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S)) -#define GPIO_FUNC27_IN_SEL_V 0x1f -#define GPIO_FUNC27_IN_SEL_S 0 - -#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c4) - -/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG28_IN_SEL (BIT(6)) -#define GPIO_SIG28_IN_SEL_M (BIT(6)) -#define GPIO_SIG28_IN_SEL_V 0x1 -#define GPIO_SIG28_IN_SEL_S 6 - -/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC28_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC28_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC28_IN_INV_SEL_V 0x1 -#define GPIO_FUNC28_IN_INV_SEL_S 5 - -/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC28_IN_SEL 0x0000001f -#define GPIO_FUNC28_IN_SEL_M ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S)) -#define GPIO_FUNC28_IN_SEL_V 0x1f -#define GPIO_FUNC28_IN_SEL_S 0 - -#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1c8) - -/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG29_IN_SEL (BIT(6)) -#define GPIO_SIG29_IN_SEL_M (BIT(6)) -#define GPIO_SIG29_IN_SEL_V 0x1 -#define GPIO_SIG29_IN_SEL_S 6 - -/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC29_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC29_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC29_IN_INV_SEL_V 0x1 -#define GPIO_FUNC29_IN_INV_SEL_S 5 - -/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC29_IN_SEL 0x0000001f -#define GPIO_FUNC29_IN_SEL_M ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S)) -#define GPIO_FUNC29_IN_SEL_V 0x1f -#define GPIO_FUNC29_IN_SEL_S 0 - -#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1cc) - -/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG30_IN_SEL (BIT(6)) -#define GPIO_SIG30_IN_SEL_M (BIT(6)) -#define GPIO_SIG30_IN_SEL_V 0x1 -#define GPIO_SIG30_IN_SEL_S 6 - -/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC30_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC30_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC30_IN_INV_SEL_V 0x1 -#define GPIO_FUNC30_IN_INV_SEL_S 5 - -/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC30_IN_SEL 0x0000001f -#define GPIO_FUNC30_IN_SEL_M ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S)) -#define GPIO_FUNC30_IN_SEL_V 0x1f -#define GPIO_FUNC30_IN_SEL_S 0 - -#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d0) - -/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG31_IN_SEL (BIT(6)) -#define GPIO_SIG31_IN_SEL_M (BIT(6)) -#define GPIO_SIG31_IN_SEL_V 0x1 -#define GPIO_SIG31_IN_SEL_S 6 - -/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC31_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC31_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC31_IN_INV_SEL_V 0x1 -#define GPIO_FUNC31_IN_INV_SEL_S 5 - -/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC31_IN_SEL 0x0000001f -#define GPIO_FUNC31_IN_SEL_M ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S)) -#define GPIO_FUNC31_IN_SEL_V 0x1f -#define GPIO_FUNC31_IN_SEL_S 0 - -#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d4) - -/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG32_IN_SEL (BIT(6)) -#define GPIO_SIG32_IN_SEL_M (BIT(6)) -#define GPIO_SIG32_IN_SEL_V 0x1 -#define GPIO_SIG32_IN_SEL_S 6 - -/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC32_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC32_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC32_IN_INV_SEL_V 0x1 -#define GPIO_FUNC32_IN_INV_SEL_S 5 - -/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC32_IN_SEL 0x0000001f -#define GPIO_FUNC32_IN_SEL_M ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S)) -#define GPIO_FUNC32_IN_SEL_V 0x1f -#define GPIO_FUNC32_IN_SEL_S 0 - -#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1d8) - -/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG33_IN_SEL (BIT(6)) -#define GPIO_SIG33_IN_SEL_M (BIT(6)) -#define GPIO_SIG33_IN_SEL_V 0x1 -#define GPIO_SIG33_IN_SEL_S 6 - -/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC33_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC33_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC33_IN_INV_SEL_V 0x1 -#define GPIO_FUNC33_IN_INV_SEL_S 5 - -/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC33_IN_SEL 0x0000001f -#define GPIO_FUNC33_IN_SEL_M ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S)) -#define GPIO_FUNC33_IN_SEL_V 0x1f -#define GPIO_FUNC33_IN_SEL_S 0 - -#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1dc) - -/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG34_IN_SEL (BIT(6)) -#define GPIO_SIG34_IN_SEL_M (BIT(6)) -#define GPIO_SIG34_IN_SEL_V 0x1 -#define GPIO_SIG34_IN_SEL_S 6 - -/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC34_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC34_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC34_IN_INV_SEL_V 0x1 -#define GPIO_FUNC34_IN_INV_SEL_S 5 - -/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC34_IN_SEL 0x0000001f -#define GPIO_FUNC34_IN_SEL_M ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S)) -#define GPIO_FUNC34_IN_SEL_V 0x1f -#define GPIO_FUNC34_IN_SEL_S 0 - -#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e0) - -/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG35_IN_SEL (BIT(6)) -#define GPIO_SIG35_IN_SEL_M (BIT(6)) -#define GPIO_SIG35_IN_SEL_V 0x1 -#define GPIO_SIG35_IN_SEL_S 6 - -/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC35_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC35_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC35_IN_INV_SEL_V 0x1 -#define GPIO_FUNC35_IN_INV_SEL_S 5 - -/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC35_IN_SEL 0x0000001f -#define GPIO_FUNC35_IN_SEL_M ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S)) -#define GPIO_FUNC35_IN_SEL_V 0x1f -#define GPIO_FUNC35_IN_SEL_S 0 - -#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e4) - -/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG36_IN_SEL (BIT(6)) -#define GPIO_SIG36_IN_SEL_M (BIT(6)) -#define GPIO_SIG36_IN_SEL_V 0x1 -#define GPIO_SIG36_IN_SEL_S 6 - -/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC36_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC36_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC36_IN_INV_SEL_V 0x1 -#define GPIO_FUNC36_IN_INV_SEL_S 5 - -/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC36_IN_SEL 0x0000001f -#define GPIO_FUNC36_IN_SEL_M ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S)) -#define GPIO_FUNC36_IN_SEL_V 0x1f -#define GPIO_FUNC36_IN_SEL_S 0 - -#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1e8) - -/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG37_IN_SEL (BIT(6)) -#define GPIO_SIG37_IN_SEL_M (BIT(6)) -#define GPIO_SIG37_IN_SEL_V 0x1 -#define GPIO_SIG37_IN_SEL_S 6 - -/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC37_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC37_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC37_IN_INV_SEL_V 0x1 -#define GPIO_FUNC37_IN_INV_SEL_S 5 - -/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC37_IN_SEL 0x0000001f -#define GPIO_FUNC37_IN_SEL_M ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S)) -#define GPIO_FUNC37_IN_SEL_V 0x1f -#define GPIO_FUNC37_IN_SEL_S 0 - -#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1ec) - -/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG38_IN_SEL (BIT(6)) -#define GPIO_SIG38_IN_SEL_M (BIT(6)) -#define GPIO_SIG38_IN_SEL_V 0x1 -#define GPIO_SIG38_IN_SEL_S 6 - -/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC38_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC38_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC38_IN_INV_SEL_V 0x1 -#define GPIO_FUNC38_IN_INV_SEL_S 5 - -/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC38_IN_SEL 0x0000001f -#define GPIO_FUNC38_IN_SEL_M ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S)) -#define GPIO_FUNC38_IN_SEL_V 0x1f -#define GPIO_FUNC38_IN_SEL_S 0 - -#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f0) - -/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG39_IN_SEL (BIT(6)) -#define GPIO_SIG39_IN_SEL_M (BIT(6)) -#define GPIO_SIG39_IN_SEL_V 0x1 -#define GPIO_SIG39_IN_SEL_S 6 - -/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC39_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC39_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC39_IN_INV_SEL_V 0x1 -#define GPIO_FUNC39_IN_INV_SEL_S 5 - -/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC39_IN_SEL 0x0000001f -#define GPIO_FUNC39_IN_SEL_M ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S)) -#define GPIO_FUNC39_IN_SEL_V 0x1f -#define GPIO_FUNC39_IN_SEL_S 0 - -#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f4) - -/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG40_IN_SEL (BIT(6)) -#define GPIO_SIG40_IN_SEL_M (BIT(6)) -#define GPIO_SIG40_IN_SEL_V 0x1 -#define GPIO_SIG40_IN_SEL_S 6 - -/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC40_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC40_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC40_IN_INV_SEL_V 0x1 -#define GPIO_FUNC40_IN_INV_SEL_S 5 - -/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC40_IN_SEL 0x0000001f -#define GPIO_FUNC40_IN_SEL_M ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S)) -#define GPIO_FUNC40_IN_SEL_V 0x1f -#define GPIO_FUNC40_IN_SEL_S 0 - -#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1f8) - -/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG41_IN_SEL (BIT(6)) -#define GPIO_SIG41_IN_SEL_M (BIT(6)) -#define GPIO_SIG41_IN_SEL_V 0x1 -#define GPIO_SIG41_IN_SEL_S 6 - -/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC41_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC41_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC41_IN_INV_SEL_V 0x1 -#define GPIO_FUNC41_IN_INV_SEL_S 5 - -/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC41_IN_SEL 0x0000001f -#define GPIO_FUNC41_IN_SEL_M ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S)) -#define GPIO_FUNC41_IN_SEL_V 0x1f -#define GPIO_FUNC41_IN_SEL_S 0 - -#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1fc) - -/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG42_IN_SEL (BIT(6)) -#define GPIO_SIG42_IN_SEL_M (BIT(6)) -#define GPIO_SIG42_IN_SEL_V 0x1 -#define GPIO_SIG42_IN_SEL_S 6 - -/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC42_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC42_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC42_IN_INV_SEL_V 0x1 -#define GPIO_FUNC42_IN_INV_SEL_S 5 - -/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC42_IN_SEL 0x0000001f -#define GPIO_FUNC42_IN_SEL_M ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S)) -#define GPIO_FUNC42_IN_SEL_V 0x1f -#define GPIO_FUNC42_IN_SEL_S 0 - -#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200) - -/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG43_IN_SEL (BIT(6)) -#define GPIO_SIG43_IN_SEL_M (BIT(6)) -#define GPIO_SIG43_IN_SEL_V 0x1 -#define GPIO_SIG43_IN_SEL_S 6 - -/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC43_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC43_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC43_IN_INV_SEL_V 0x1 -#define GPIO_FUNC43_IN_INV_SEL_S 5 - -/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC43_IN_SEL 0x0000001f -#define GPIO_FUNC43_IN_SEL_M ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S)) -#define GPIO_FUNC43_IN_SEL_V 0x1f -#define GPIO_FUNC43_IN_SEL_S 0 - -#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204) - -/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG44_IN_SEL (BIT(6)) -#define GPIO_SIG44_IN_SEL_M (BIT(6)) -#define GPIO_SIG44_IN_SEL_V 0x1 -#define GPIO_SIG44_IN_SEL_S 6 - -/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC44_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC44_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC44_IN_INV_SEL_V 0x1 -#define GPIO_FUNC44_IN_INV_SEL_S 5 - -/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC44_IN_SEL 0x0000001f -#define GPIO_FUNC44_IN_SEL_M ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S)) -#define GPIO_FUNC44_IN_SEL_V 0x1f -#define GPIO_FUNC44_IN_SEL_S 0 - -#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) - -/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG45_IN_SEL (BIT(6)) -#define GPIO_SIG45_IN_SEL_M (BIT(6)) -#define GPIO_SIG45_IN_SEL_V 0x1 -#define GPIO_SIG45_IN_SEL_S 6 - -/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC45_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC45_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC45_IN_INV_SEL_V 0x1 -#define GPIO_FUNC45_IN_INV_SEL_S 5 - -/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC45_IN_SEL 0x0000001f -#define GPIO_FUNC45_IN_SEL_M ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S)) -#define GPIO_FUNC45_IN_SEL_V 0x1f -#define GPIO_FUNC45_IN_SEL_S 0 - -#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20c) - -/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG46_IN_SEL (BIT(6)) -#define GPIO_SIG46_IN_SEL_M (BIT(6)) -#define GPIO_SIG46_IN_SEL_V 0x1 -#define GPIO_SIG46_IN_SEL_S 6 - -/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC46_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC46_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC46_IN_INV_SEL_V 0x1 -#define GPIO_FUNC46_IN_INV_SEL_S 5 - -/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC46_IN_SEL 0x0000001f -#define GPIO_FUNC46_IN_SEL_M ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S)) -#define GPIO_FUNC46_IN_SEL_V 0x1f -#define GPIO_FUNC46_IN_SEL_S 0 - -#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) - -/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG47_IN_SEL (BIT(6)) -#define GPIO_SIG47_IN_SEL_M (BIT(6)) -#define GPIO_SIG47_IN_SEL_V 0x1 -#define GPIO_SIG47_IN_SEL_S 6 - -/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC47_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC47_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC47_IN_INV_SEL_V 0x1 -#define GPIO_FUNC47_IN_INV_SEL_S 5 - -/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC47_IN_SEL 0x0000001f -#define GPIO_FUNC47_IN_SEL_M ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S)) -#define GPIO_FUNC47_IN_SEL_V 0x1f -#define GPIO_FUNC47_IN_SEL_S 0 - -#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) - -/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG48_IN_SEL (BIT(6)) -#define GPIO_SIG48_IN_SEL_M (BIT(6)) -#define GPIO_SIG48_IN_SEL_V 0x1 -#define GPIO_SIG48_IN_SEL_S 6 - -/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC48_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC48_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC48_IN_INV_SEL_V 0x1 -#define GPIO_FUNC48_IN_INV_SEL_S 5 - -/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC48_IN_SEL 0x0000001f -#define GPIO_FUNC48_IN_SEL_M ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S)) -#define GPIO_FUNC48_IN_SEL_V 0x1f -#define GPIO_FUNC48_IN_SEL_S 0 - -#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) - -/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG49_IN_SEL (BIT(6)) -#define GPIO_SIG49_IN_SEL_M (BIT(6)) -#define GPIO_SIG49_IN_SEL_V 0x1 -#define GPIO_SIG49_IN_SEL_S 6 - -/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC49_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC49_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC49_IN_INV_SEL_V 0x1 -#define GPIO_FUNC49_IN_INV_SEL_S 5 - -/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC49_IN_SEL 0x0000001f -#define GPIO_FUNC49_IN_SEL_M ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S)) -#define GPIO_FUNC49_IN_SEL_V 0x1f -#define GPIO_FUNC49_IN_SEL_S 0 - -#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21c) - -/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG50_IN_SEL (BIT(6)) -#define GPIO_SIG50_IN_SEL_M (BIT(6)) -#define GPIO_SIG50_IN_SEL_V 0x1 -#define GPIO_SIG50_IN_SEL_S 6 - -/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC50_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC50_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC50_IN_INV_SEL_V 0x1 -#define GPIO_FUNC50_IN_INV_SEL_S 5 - -/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC50_IN_SEL 0x0000001f -#define GPIO_FUNC50_IN_SEL_M ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S)) -#define GPIO_FUNC50_IN_SEL_V 0x1f -#define GPIO_FUNC50_IN_SEL_S 0 - -#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) - -/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG51_IN_SEL (BIT(6)) -#define GPIO_SIG51_IN_SEL_M (BIT(6)) -#define GPIO_SIG51_IN_SEL_V 0x1 -#define GPIO_SIG51_IN_SEL_S 6 - -/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC51_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC51_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC51_IN_INV_SEL_V 0x1 -#define GPIO_FUNC51_IN_INV_SEL_S 5 - -/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC51_IN_SEL 0x0000001f -#define GPIO_FUNC51_IN_SEL_M ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S)) -#define GPIO_FUNC51_IN_SEL_V 0x1f -#define GPIO_FUNC51_IN_SEL_S 0 - -#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) - -/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG52_IN_SEL (BIT(6)) -#define GPIO_SIG52_IN_SEL_M (BIT(6)) -#define GPIO_SIG52_IN_SEL_V 0x1 -#define GPIO_SIG52_IN_SEL_S 6 - -/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC52_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC52_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC52_IN_INV_SEL_V 0x1 -#define GPIO_FUNC52_IN_INV_SEL_S 5 - -/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC52_IN_SEL 0x0000001f -#define GPIO_FUNC52_IN_SEL_M ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S)) -#define GPIO_FUNC52_IN_SEL_V 0x1f -#define GPIO_FUNC52_IN_SEL_S 0 - -#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) - -/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG53_IN_SEL (BIT(6)) -#define GPIO_SIG53_IN_SEL_M (BIT(6)) -#define GPIO_SIG53_IN_SEL_V 0x1 -#define GPIO_SIG53_IN_SEL_S 6 - -/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC53_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC53_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC53_IN_INV_SEL_V 0x1 -#define GPIO_FUNC53_IN_INV_SEL_S 5 - -/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC53_IN_SEL 0x0000001f -#define GPIO_FUNC53_IN_SEL_M ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S)) -#define GPIO_FUNC53_IN_SEL_V 0x1f -#define GPIO_FUNC53_IN_SEL_S 0 - -#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22c) - -/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG54_IN_SEL (BIT(6)) -#define GPIO_SIG54_IN_SEL_M (BIT(6)) -#define GPIO_SIG54_IN_SEL_V 0x1 -#define GPIO_SIG54_IN_SEL_S 6 - -/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC54_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC54_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC54_IN_INV_SEL_V 0x1 -#define GPIO_FUNC54_IN_INV_SEL_S 5 - -/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC54_IN_SEL 0x0000001f -#define GPIO_FUNC54_IN_SEL_M ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S)) -#define GPIO_FUNC54_IN_SEL_V 0x1f -#define GPIO_FUNC54_IN_SEL_S 0 - -#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230) - -/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG55_IN_SEL (BIT(6)) -#define GPIO_SIG55_IN_SEL_M (BIT(6)) -#define GPIO_SIG55_IN_SEL_V 0x1 -#define GPIO_SIG55_IN_SEL_S 6 - -/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC55_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC55_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC55_IN_INV_SEL_V 0x1 -#define GPIO_FUNC55_IN_INV_SEL_S 5 - -/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC55_IN_SEL 0x0000001f -#define GPIO_FUNC55_IN_SEL_M ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S)) -#define GPIO_FUNC55_IN_SEL_V 0x1f -#define GPIO_FUNC55_IN_SEL_S 0 - -#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234) - -/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG56_IN_SEL (BIT(6)) -#define GPIO_SIG56_IN_SEL_M (BIT(6)) -#define GPIO_SIG56_IN_SEL_V 0x1 -#define GPIO_SIG56_IN_SEL_S 6 - -/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC56_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC56_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC56_IN_INV_SEL_V 0x1 -#define GPIO_FUNC56_IN_INV_SEL_S 5 - -/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC56_IN_SEL 0x0000001f -#define GPIO_FUNC56_IN_SEL_M ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S)) -#define GPIO_FUNC56_IN_SEL_V 0x1f -#define GPIO_FUNC56_IN_SEL_S 0 - -#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238) - -/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG57_IN_SEL (BIT(6)) -#define GPIO_SIG57_IN_SEL_M (BIT(6)) -#define GPIO_SIG57_IN_SEL_V 0x1 -#define GPIO_SIG57_IN_SEL_S 6 - -/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC57_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC57_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC57_IN_INV_SEL_V 0x1 -#define GPIO_FUNC57_IN_INV_SEL_S 5 - -/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC57_IN_SEL 0x0000001f -#define GPIO_FUNC57_IN_SEL_M ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S)) -#define GPIO_FUNC57_IN_SEL_V 0x1f -#define GPIO_FUNC57_IN_SEL_S 0 - -#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23c) - -/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG58_IN_SEL (BIT(6)) -#define GPIO_SIG58_IN_SEL_M (BIT(6)) -#define GPIO_SIG58_IN_SEL_V 0x1 -#define GPIO_SIG58_IN_SEL_S 6 - -/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC58_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC58_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC58_IN_INV_SEL_V 0x1 -#define GPIO_FUNC58_IN_INV_SEL_S 5 - -/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC58_IN_SEL 0x0000001f -#define GPIO_FUNC58_IN_SEL_M ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S)) -#define GPIO_FUNC58_IN_SEL_V 0x1f -#define GPIO_FUNC58_IN_SEL_S 0 - -#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240) - -/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG59_IN_SEL (BIT(6)) -#define GPIO_SIG59_IN_SEL_M (BIT(6)) -#define GPIO_SIG59_IN_SEL_V 0x1 -#define GPIO_SIG59_IN_SEL_S 6 - -/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC59_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC59_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC59_IN_INV_SEL_V 0x1 -#define GPIO_FUNC59_IN_INV_SEL_S 5 - -/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC59_IN_SEL 0x0000001f -#define GPIO_FUNC59_IN_SEL_M ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S)) -#define GPIO_FUNC59_IN_SEL_V 0x1f -#define GPIO_FUNC59_IN_SEL_S 0 - -#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244) - -/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG60_IN_SEL (BIT(6)) -#define GPIO_SIG60_IN_SEL_M (BIT(6)) -#define GPIO_SIG60_IN_SEL_V 0x1 -#define GPIO_SIG60_IN_SEL_S 6 - -/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC60_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC60_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC60_IN_INV_SEL_V 0x1 -#define GPIO_FUNC60_IN_INV_SEL_S 5 - -/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC60_IN_SEL 0x0000001f -#define GPIO_FUNC60_IN_SEL_M ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S)) -#define GPIO_FUNC60_IN_SEL_V 0x1f -#define GPIO_FUNC60_IN_SEL_S 0 - -#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248) - -/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG61_IN_SEL (BIT(6)) -#define GPIO_SIG61_IN_SEL_M (BIT(6)) -#define GPIO_SIG61_IN_SEL_V 0x1 -#define GPIO_SIG61_IN_SEL_S 6 - -/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC61_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC61_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC61_IN_INV_SEL_V 0x1 -#define GPIO_FUNC61_IN_INV_SEL_S 5 - -/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC61_IN_SEL 0x0000001f -#define GPIO_FUNC61_IN_SEL_M ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S)) -#define GPIO_FUNC61_IN_SEL_V 0x1f -#define GPIO_FUNC61_IN_SEL_S 0 - -#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24c) - -/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG62_IN_SEL (BIT(6)) -#define GPIO_SIG62_IN_SEL_M (BIT(6)) -#define GPIO_SIG62_IN_SEL_V 0x1 -#define GPIO_SIG62_IN_SEL_S 6 - -/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC62_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC62_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC62_IN_INV_SEL_V 0x1 -#define GPIO_FUNC62_IN_INV_SEL_S 5 - -/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC62_IN_SEL 0x0000001f -#define GPIO_FUNC62_IN_SEL_M ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S)) -#define GPIO_FUNC62_IN_SEL_V 0x1f -#define GPIO_FUNC62_IN_SEL_S 0 - -#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) - -/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG63_IN_SEL (BIT(6)) -#define GPIO_SIG63_IN_SEL_M (BIT(6)) -#define GPIO_SIG63_IN_SEL_V 0x1 -#define GPIO_SIG63_IN_SEL_S 6 - -/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC63_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC63_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC63_IN_INV_SEL_V 0x1 -#define GPIO_FUNC63_IN_INV_SEL_S 5 - -/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC63_IN_SEL 0x0000001f -#define GPIO_FUNC63_IN_SEL_M ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S)) -#define GPIO_FUNC63_IN_SEL_V 0x1f -#define GPIO_FUNC63_IN_SEL_S 0 - -#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) - -/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG64_IN_SEL (BIT(6)) -#define GPIO_SIG64_IN_SEL_M (BIT(6)) -#define GPIO_SIG64_IN_SEL_V 0x1 -#define GPIO_SIG64_IN_SEL_S 6 - -/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC64_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC64_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC64_IN_INV_SEL_V 0x1 -#define GPIO_FUNC64_IN_INV_SEL_S 5 - -/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC64_IN_SEL 0x0000001f -#define GPIO_FUNC64_IN_SEL_M ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S)) -#define GPIO_FUNC64_IN_SEL_V 0x1f -#define GPIO_FUNC64_IN_SEL_S 0 - -#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) - -/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG65_IN_SEL (BIT(6)) -#define GPIO_SIG65_IN_SEL_M (BIT(6)) -#define GPIO_SIG65_IN_SEL_V 0x1 -#define GPIO_SIG65_IN_SEL_S 6 - -/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC65_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC65_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC65_IN_INV_SEL_V 0x1 -#define GPIO_FUNC65_IN_INV_SEL_S 5 - -/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC65_IN_SEL 0x0000001f -#define GPIO_FUNC65_IN_SEL_M ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S)) -#define GPIO_FUNC65_IN_SEL_V 0x1f -#define GPIO_FUNC65_IN_SEL_S 0 - -#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25c) - -/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG66_IN_SEL (BIT(6)) -#define GPIO_SIG66_IN_SEL_M (BIT(6)) -#define GPIO_SIG66_IN_SEL_V 0x1 -#define GPIO_SIG66_IN_SEL_S 6 - -/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC66_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC66_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC66_IN_INV_SEL_V 0x1 -#define GPIO_FUNC66_IN_INV_SEL_S 5 - -/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC66_IN_SEL 0x0000001f -#define GPIO_FUNC66_IN_SEL_M ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S)) -#define GPIO_FUNC66_IN_SEL_V 0x1f -#define GPIO_FUNC66_IN_SEL_S 0 - -#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) - -/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG67_IN_SEL (BIT(6)) -#define GPIO_SIG67_IN_SEL_M (BIT(6)) -#define GPIO_SIG67_IN_SEL_V 0x1 -#define GPIO_SIG67_IN_SEL_S 6 - -/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC67_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC67_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC67_IN_INV_SEL_V 0x1 -#define GPIO_FUNC67_IN_INV_SEL_S 5 - -/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC67_IN_SEL 0x0000001f -#define GPIO_FUNC67_IN_SEL_M ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S)) -#define GPIO_FUNC67_IN_SEL_V 0x1f -#define GPIO_FUNC67_IN_SEL_S 0 - -#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) - -/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG68_IN_SEL (BIT(6)) -#define GPIO_SIG68_IN_SEL_M (BIT(6)) -#define GPIO_SIG68_IN_SEL_V 0x1 -#define GPIO_SIG68_IN_SEL_S 6 - -/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC68_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC68_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC68_IN_INV_SEL_V 0x1 -#define GPIO_FUNC68_IN_INV_SEL_S 5 - -/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC68_IN_SEL 0x0000001f -#define GPIO_FUNC68_IN_SEL_M ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S)) -#define GPIO_FUNC68_IN_SEL_V 0x1f -#define GPIO_FUNC68_IN_SEL_S 0 - -#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) - -/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG69_IN_SEL (BIT(6)) -#define GPIO_SIG69_IN_SEL_M (BIT(6)) -#define GPIO_SIG69_IN_SEL_V 0x1 -#define GPIO_SIG69_IN_SEL_S 6 - -/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC69_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC69_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC69_IN_INV_SEL_V 0x1 -#define GPIO_FUNC69_IN_INV_SEL_S 5 - -/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC69_IN_SEL 0x0000001f -#define GPIO_FUNC69_IN_SEL_M ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S)) -#define GPIO_FUNC69_IN_SEL_V 0x1f -#define GPIO_FUNC69_IN_SEL_S 0 - -#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26c) - -/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG70_IN_SEL (BIT(6)) -#define GPIO_SIG70_IN_SEL_M (BIT(6)) -#define GPIO_SIG70_IN_SEL_V 0x1 -#define GPIO_SIG70_IN_SEL_S 6 - -/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC70_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC70_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC70_IN_INV_SEL_V 0x1 -#define GPIO_FUNC70_IN_INV_SEL_S 5 - -/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC70_IN_SEL 0x0000001f -#define GPIO_FUNC70_IN_SEL_M ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S)) -#define GPIO_FUNC70_IN_SEL_V 0x1f -#define GPIO_FUNC70_IN_SEL_S 0 - -#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) - -/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG71_IN_SEL (BIT(6)) -#define GPIO_SIG71_IN_SEL_M (BIT(6)) -#define GPIO_SIG71_IN_SEL_V 0x1 -#define GPIO_SIG71_IN_SEL_S 6 - -/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC71_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC71_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC71_IN_INV_SEL_V 0x1 -#define GPIO_FUNC71_IN_INV_SEL_S 5 - -/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC71_IN_SEL 0x0000001f -#define GPIO_FUNC71_IN_SEL_M ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S)) -#define GPIO_FUNC71_IN_SEL_V 0x1f -#define GPIO_FUNC71_IN_SEL_S 0 - -#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) - -/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG72_IN_SEL (BIT(6)) -#define GPIO_SIG72_IN_SEL_M (BIT(6)) -#define GPIO_SIG72_IN_SEL_V 0x1 -#define GPIO_SIG72_IN_SEL_S 6 - -/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC72_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC72_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC72_IN_INV_SEL_V 0x1 -#define GPIO_FUNC72_IN_INV_SEL_S 5 - -/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC72_IN_SEL 0x0000001f -#define GPIO_FUNC72_IN_SEL_M ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S)) -#define GPIO_FUNC72_IN_SEL_V 0x1f -#define GPIO_FUNC72_IN_SEL_S 0 - -#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) - -/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG73_IN_SEL (BIT(6)) -#define GPIO_SIG73_IN_SEL_M (BIT(6)) -#define GPIO_SIG73_IN_SEL_V 0x1 -#define GPIO_SIG73_IN_SEL_S 6 - -/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC73_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC73_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC73_IN_INV_SEL_V 0x1 -#define GPIO_FUNC73_IN_INV_SEL_S 5 - -/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC73_IN_SEL 0x0000001f -#define GPIO_FUNC73_IN_SEL_M ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S)) -#define GPIO_FUNC73_IN_SEL_V 0x1f -#define GPIO_FUNC73_IN_SEL_S 0 - -#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x27c) - -/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG74_IN_SEL (BIT(6)) -#define GPIO_SIG74_IN_SEL_M (BIT(6)) -#define GPIO_SIG74_IN_SEL_V 0x1 -#define GPIO_SIG74_IN_SEL_S 6 - -/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC74_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC74_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC74_IN_INV_SEL_V 0x1 -#define GPIO_FUNC74_IN_INV_SEL_S 5 - -/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC74_IN_SEL 0x0000001f -#define GPIO_FUNC74_IN_SEL_M ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S)) -#define GPIO_FUNC74_IN_SEL_V 0x1f -#define GPIO_FUNC74_IN_SEL_S 0 - -#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280) - -/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG75_IN_SEL (BIT(6)) -#define GPIO_SIG75_IN_SEL_M (BIT(6)) -#define GPIO_SIG75_IN_SEL_V 0x1 -#define GPIO_SIG75_IN_SEL_S 6 - -/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC75_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC75_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC75_IN_INV_SEL_V 0x1 -#define GPIO_FUNC75_IN_INV_SEL_S 5 - -/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC75_IN_SEL 0x0000001f -#define GPIO_FUNC75_IN_SEL_M ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S)) -#define GPIO_FUNC75_IN_SEL_V 0x1f -#define GPIO_FUNC75_IN_SEL_S 0 - -#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284) - -/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG76_IN_SEL (BIT(6)) -#define GPIO_SIG76_IN_SEL_M (BIT(6)) -#define GPIO_SIG76_IN_SEL_V 0x1 -#define GPIO_SIG76_IN_SEL_S 6 - -/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC76_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC76_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC76_IN_INV_SEL_V 0x1 -#define GPIO_FUNC76_IN_INV_SEL_S 5 - -/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC76_IN_SEL 0x0000001f -#define GPIO_FUNC76_IN_SEL_M ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S)) -#define GPIO_FUNC76_IN_SEL_V 0x1f -#define GPIO_FUNC76_IN_SEL_S 0 - -#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288) - -/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG77_IN_SEL (BIT(6)) -#define GPIO_SIG77_IN_SEL_M (BIT(6)) -#define GPIO_SIG77_IN_SEL_V 0x1 -#define GPIO_SIG77_IN_SEL_S 6 - -/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC77_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC77_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC77_IN_INV_SEL_V 0x1 -#define GPIO_FUNC77_IN_INV_SEL_S 5 - -/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC77_IN_SEL 0x0000001f -#define GPIO_FUNC77_IN_SEL_M ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S)) -#define GPIO_FUNC77_IN_SEL_V 0x1f -#define GPIO_FUNC77_IN_SEL_S 0 - -#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28c) - -/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG78_IN_SEL (BIT(6)) -#define GPIO_SIG78_IN_SEL_M (BIT(6)) -#define GPIO_SIG78_IN_SEL_V 0x1 -#define GPIO_SIG78_IN_SEL_S 6 - -/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC78_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC78_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC78_IN_INV_SEL_V 0x1 -#define GPIO_FUNC78_IN_INV_SEL_S 5 - -/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC78_IN_SEL 0x0000001f -#define GPIO_FUNC78_IN_SEL_M ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S)) -#define GPIO_FUNC78_IN_SEL_V 0x1f -#define GPIO_FUNC78_IN_SEL_S 0 - -#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290) - -/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG79_IN_SEL (BIT(6)) -#define GPIO_SIG79_IN_SEL_M (BIT(6)) -#define GPIO_SIG79_IN_SEL_V 0x1 -#define GPIO_SIG79_IN_SEL_S 6 - -/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC79_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC79_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC79_IN_INV_SEL_V 0x1 -#define GPIO_FUNC79_IN_INV_SEL_S 5 - -/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC79_IN_SEL 0x0000001f -#define GPIO_FUNC79_IN_SEL_M ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S)) -#define GPIO_FUNC79_IN_SEL_V 0x1f -#define GPIO_FUNC79_IN_SEL_S 0 - -#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x294) - -/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG80_IN_SEL (BIT(6)) -#define GPIO_SIG80_IN_SEL_M (BIT(6)) -#define GPIO_SIG80_IN_SEL_V 0x1 -#define GPIO_SIG80_IN_SEL_S 6 - -/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC80_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC80_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC80_IN_INV_SEL_V 0x1 -#define GPIO_FUNC80_IN_INV_SEL_S 5 - -/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC80_IN_SEL 0x0000001f -#define GPIO_FUNC80_IN_SEL_M ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S)) -#define GPIO_FUNC80_IN_SEL_V 0x1f -#define GPIO_FUNC80_IN_SEL_S 0 - -#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) - -/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG81_IN_SEL (BIT(6)) -#define GPIO_SIG81_IN_SEL_M (BIT(6)) -#define GPIO_SIG81_IN_SEL_V 0x1 -#define GPIO_SIG81_IN_SEL_S 6 - -/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC81_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC81_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC81_IN_INV_SEL_V 0x1 -#define GPIO_FUNC81_IN_INV_SEL_S 5 - -/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC81_IN_SEL 0x0000001f -#define GPIO_FUNC81_IN_SEL_M ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S)) -#define GPIO_FUNC81_IN_SEL_V 0x1f -#define GPIO_FUNC81_IN_SEL_S 0 - -#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29c) - -/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG82_IN_SEL (BIT(6)) -#define GPIO_SIG82_IN_SEL_M (BIT(6)) -#define GPIO_SIG82_IN_SEL_V 0x1 -#define GPIO_SIG82_IN_SEL_S 6 - -/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC82_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC82_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC82_IN_INV_SEL_V 0x1 -#define GPIO_FUNC82_IN_INV_SEL_S 5 - -/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC82_IN_SEL 0x0000001f -#define GPIO_FUNC82_IN_SEL_M ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S)) -#define GPIO_FUNC82_IN_SEL_V 0x1f -#define GPIO_FUNC82_IN_SEL_S 0 - -#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a0) - -/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG83_IN_SEL (BIT(6)) -#define GPIO_SIG83_IN_SEL_M (BIT(6)) -#define GPIO_SIG83_IN_SEL_V 0x1 -#define GPIO_SIG83_IN_SEL_S 6 - -/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC83_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC83_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC83_IN_INV_SEL_V 0x1 -#define GPIO_FUNC83_IN_INV_SEL_S 5 - -/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC83_IN_SEL 0x0000001f -#define GPIO_FUNC83_IN_SEL_M ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S)) -#define GPIO_FUNC83_IN_SEL_V 0x1f -#define GPIO_FUNC83_IN_SEL_S 0 - -#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a4) - -/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG84_IN_SEL (BIT(6)) -#define GPIO_SIG84_IN_SEL_M (BIT(6)) -#define GPIO_SIG84_IN_SEL_V 0x1 -#define GPIO_SIG84_IN_SEL_S 6 - -/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC84_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC84_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC84_IN_INV_SEL_V 0x1 -#define GPIO_FUNC84_IN_INV_SEL_S 5 - -/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC84_IN_SEL 0x0000001f -#define GPIO_FUNC84_IN_SEL_M ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S)) -#define GPIO_FUNC84_IN_SEL_V 0x1f -#define GPIO_FUNC84_IN_SEL_S 0 - -#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2a8) - -/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG85_IN_SEL (BIT(6)) -#define GPIO_SIG85_IN_SEL_M (BIT(6)) -#define GPIO_SIG85_IN_SEL_V 0x1 -#define GPIO_SIG85_IN_SEL_S 6 - -/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC85_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC85_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC85_IN_INV_SEL_V 0x1 -#define GPIO_FUNC85_IN_INV_SEL_S 5 - -/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC85_IN_SEL 0x0000001f -#define GPIO_FUNC85_IN_SEL_M ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S)) -#define GPIO_FUNC85_IN_SEL_V 0x1f -#define GPIO_FUNC85_IN_SEL_S 0 - -#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ac) - -/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG86_IN_SEL (BIT(6)) -#define GPIO_SIG86_IN_SEL_M (BIT(6)) -#define GPIO_SIG86_IN_SEL_V 0x1 -#define GPIO_SIG86_IN_SEL_S 6 - -/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC86_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC86_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC86_IN_INV_SEL_V 0x1 -#define GPIO_FUNC86_IN_INV_SEL_S 5 - -/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC86_IN_SEL 0x0000001f -#define GPIO_FUNC86_IN_SEL_M ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S)) -#define GPIO_FUNC86_IN_SEL_V 0x1f -#define GPIO_FUNC86_IN_SEL_S 0 - -#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b0) - -/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG87_IN_SEL (BIT(6)) -#define GPIO_SIG87_IN_SEL_M (BIT(6)) -#define GPIO_SIG87_IN_SEL_V 0x1 -#define GPIO_SIG87_IN_SEL_S 6 - -/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC87_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC87_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC87_IN_INV_SEL_V 0x1 -#define GPIO_FUNC87_IN_INV_SEL_S 5 - -/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC87_IN_SEL 0x0000001f -#define GPIO_FUNC87_IN_SEL_M ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S)) -#define GPIO_FUNC87_IN_SEL_V 0x1f -#define GPIO_FUNC87_IN_SEL_S 0 - -#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b4) - -/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG88_IN_SEL (BIT(6)) -#define GPIO_SIG88_IN_SEL_M (BIT(6)) -#define GPIO_SIG88_IN_SEL_V 0x1 -#define GPIO_SIG88_IN_SEL_S 6 - -/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC88_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC88_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC88_IN_INV_SEL_V 0x1 -#define GPIO_FUNC88_IN_INV_SEL_S 5 - -/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC88_IN_SEL 0x0000001f -#define GPIO_FUNC88_IN_SEL_M ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S)) -#define GPIO_FUNC88_IN_SEL_V 0x1f -#define GPIO_FUNC88_IN_SEL_S 0 - -#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2b8) - -/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG89_IN_SEL (BIT(6)) -#define GPIO_SIG89_IN_SEL_M (BIT(6)) -#define GPIO_SIG89_IN_SEL_V 0x1 -#define GPIO_SIG89_IN_SEL_S 6 - -/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC89_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC89_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC89_IN_INV_SEL_V 0x1 -#define GPIO_FUNC89_IN_INV_SEL_S 5 - -/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC89_IN_SEL 0x0000001f -#define GPIO_FUNC89_IN_SEL_M ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S)) -#define GPIO_FUNC89_IN_SEL_V 0x1f -#define GPIO_FUNC89_IN_SEL_S 0 - -#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2bc) - -/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG90_IN_SEL (BIT(6)) -#define GPIO_SIG90_IN_SEL_M (BIT(6)) -#define GPIO_SIG90_IN_SEL_V 0x1 -#define GPIO_SIG90_IN_SEL_S 6 - -/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC90_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC90_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC90_IN_INV_SEL_V 0x1 -#define GPIO_FUNC90_IN_INV_SEL_S 5 - -/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC90_IN_SEL 0x0000001f -#define GPIO_FUNC90_IN_SEL_M ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S)) -#define GPIO_FUNC90_IN_SEL_V 0x1f -#define GPIO_FUNC90_IN_SEL_S 0 - -#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c0) - -/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG91_IN_SEL (BIT(6)) -#define GPIO_SIG91_IN_SEL_M (BIT(6)) -#define GPIO_SIG91_IN_SEL_V 0x1 -#define GPIO_SIG91_IN_SEL_S 6 - -/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC91_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC91_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC91_IN_INV_SEL_V 0x1 -#define GPIO_FUNC91_IN_INV_SEL_S 5 - -/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC91_IN_SEL 0x0000001f -#define GPIO_FUNC91_IN_SEL_M ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S)) -#define GPIO_FUNC91_IN_SEL_V 0x1f -#define GPIO_FUNC91_IN_SEL_S 0 - -#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c4) - -/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG92_IN_SEL (BIT(6)) -#define GPIO_SIG92_IN_SEL_M (BIT(6)) -#define GPIO_SIG92_IN_SEL_V 0x1 -#define GPIO_SIG92_IN_SEL_S 6 - -/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC92_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC92_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC92_IN_INV_SEL_V 0x1 -#define GPIO_FUNC92_IN_INV_SEL_S 5 - -/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC92_IN_SEL 0x0000001f -#define GPIO_FUNC92_IN_SEL_M ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S)) -#define GPIO_FUNC92_IN_SEL_V 0x1f -#define GPIO_FUNC92_IN_SEL_S 0 - -#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2c8) - -/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG93_IN_SEL (BIT(6)) -#define GPIO_SIG93_IN_SEL_M (BIT(6)) -#define GPIO_SIG93_IN_SEL_V 0x1 -#define GPIO_SIG93_IN_SEL_S 6 - -/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC93_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC93_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC93_IN_INV_SEL_V 0x1 -#define GPIO_FUNC93_IN_INV_SEL_S 5 - -/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC93_IN_SEL 0x0000001f -#define GPIO_FUNC93_IN_SEL_M ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S)) -#define GPIO_FUNC93_IN_SEL_V 0x1f -#define GPIO_FUNC93_IN_SEL_S 0 - -#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2cc) - -/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG94_IN_SEL (BIT(6)) -#define GPIO_SIG94_IN_SEL_M (BIT(6)) -#define GPIO_SIG94_IN_SEL_V 0x1 -#define GPIO_SIG94_IN_SEL_S 6 - -/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC94_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC94_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC94_IN_INV_SEL_V 0x1 -#define GPIO_FUNC94_IN_INV_SEL_S 5 - -/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC94_IN_SEL 0x0000001f -#define GPIO_FUNC94_IN_SEL_M ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S)) -#define GPIO_FUNC94_IN_SEL_V 0x1f -#define GPIO_FUNC94_IN_SEL_S 0 - -#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d0) - -/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG95_IN_SEL (BIT(6)) -#define GPIO_SIG95_IN_SEL_M (BIT(6)) -#define GPIO_SIG95_IN_SEL_V 0x1 -#define GPIO_SIG95_IN_SEL_S 6 - -/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC95_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC95_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC95_IN_INV_SEL_V 0x1 -#define GPIO_FUNC95_IN_INV_SEL_S 5 - -/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC95_IN_SEL 0x0000001f -#define GPIO_FUNC95_IN_SEL_M ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S)) -#define GPIO_FUNC95_IN_SEL_V 0x1f -#define GPIO_FUNC95_IN_SEL_S 0 - -#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d4) - -/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG96_IN_SEL (BIT(6)) -#define GPIO_SIG96_IN_SEL_M (BIT(6)) -#define GPIO_SIG96_IN_SEL_V 0x1 -#define GPIO_SIG96_IN_SEL_S 6 - -/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC96_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC96_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC96_IN_INV_SEL_V 0x1 -#define GPIO_FUNC96_IN_INV_SEL_S 5 - -/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC96_IN_SEL 0x0000001f -#define GPIO_FUNC96_IN_SEL_M ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S)) -#define GPIO_FUNC96_IN_SEL_V 0x1f -#define GPIO_FUNC96_IN_SEL_S 0 - -#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2d8) - -/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG97_IN_SEL (BIT(6)) -#define GPIO_SIG97_IN_SEL_M (BIT(6)) -#define GPIO_SIG97_IN_SEL_V 0x1 -#define GPIO_SIG97_IN_SEL_S 6 - -/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC97_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC97_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC97_IN_INV_SEL_V 0x1 -#define GPIO_FUNC97_IN_INV_SEL_S 5 - -/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC97_IN_SEL 0x0000001f -#define GPIO_FUNC97_IN_SEL_M ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S)) -#define GPIO_FUNC97_IN_SEL_V 0x1f -#define GPIO_FUNC97_IN_SEL_S 0 - -#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2dc) - -/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG98_IN_SEL (BIT(6)) -#define GPIO_SIG98_IN_SEL_M (BIT(6)) -#define GPIO_SIG98_IN_SEL_V 0x1 -#define GPIO_SIG98_IN_SEL_S 6 - -/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC98_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC98_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC98_IN_INV_SEL_V 0x1 -#define GPIO_FUNC98_IN_INV_SEL_S 5 - -/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC98_IN_SEL 0x0000001f -#define GPIO_FUNC98_IN_SEL_M ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S)) -#define GPIO_FUNC98_IN_SEL_V 0x1f -#define GPIO_FUNC98_IN_SEL_S 0 - -#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e0) - -/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG99_IN_SEL (BIT(6)) -#define GPIO_SIG99_IN_SEL_M (BIT(6)) -#define GPIO_SIG99_IN_SEL_V 0x1 -#define GPIO_SIG99_IN_SEL_S 6 - -/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC99_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC99_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC99_IN_INV_SEL_V 0x1 -#define GPIO_FUNC99_IN_INV_SEL_S 5 - -/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC99_IN_SEL 0x0000001f -#define GPIO_FUNC99_IN_SEL_M ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S)) -#define GPIO_FUNC99_IN_SEL_V 0x1f -#define GPIO_FUNC99_IN_SEL_S 0 - -#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e4) - -/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG100_IN_SEL (BIT(6)) -#define GPIO_SIG100_IN_SEL_M (BIT(6)) -#define GPIO_SIG100_IN_SEL_V 0x1 -#define GPIO_SIG100_IN_SEL_S 6 - -/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC100_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC100_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC100_IN_INV_SEL_V 0x1 -#define GPIO_FUNC100_IN_INV_SEL_S 5 - -/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC100_IN_SEL 0x0000001f -#define GPIO_FUNC100_IN_SEL_M ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S)) -#define GPIO_FUNC100_IN_SEL_V 0x1f -#define GPIO_FUNC100_IN_SEL_S 0 - -#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2e8) - -/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG101_IN_SEL (BIT(6)) -#define GPIO_SIG101_IN_SEL_M (BIT(6)) -#define GPIO_SIG101_IN_SEL_V 0x1 -#define GPIO_SIG101_IN_SEL_S 6 - -/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC101_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC101_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC101_IN_INV_SEL_V 0x1 -#define GPIO_FUNC101_IN_INV_SEL_S 5 - -/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC101_IN_SEL 0x0000001f -#define GPIO_FUNC101_IN_SEL_M ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S)) -#define GPIO_FUNC101_IN_SEL_V 0x1f -#define GPIO_FUNC101_IN_SEL_S 0 - -#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2ec) - -/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG102_IN_SEL (BIT(6)) -#define GPIO_SIG102_IN_SEL_M (BIT(6)) -#define GPIO_SIG102_IN_SEL_V 0x1 -#define GPIO_SIG102_IN_SEL_S 6 - -/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC102_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC102_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC102_IN_INV_SEL_V 0x1 -#define GPIO_FUNC102_IN_INV_SEL_S 5 - -/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC102_IN_SEL 0x0000001f -#define GPIO_FUNC102_IN_SEL_M ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S)) -#define GPIO_FUNC102_IN_SEL_V 0x1f -#define GPIO_FUNC102_IN_SEL_S 0 - -#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f0) - -/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG103_IN_SEL (BIT(6)) -#define GPIO_SIG103_IN_SEL_M (BIT(6)) -#define GPIO_SIG103_IN_SEL_V 0x1 -#define GPIO_SIG103_IN_SEL_S 6 - -/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC103_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC103_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC103_IN_INV_SEL_V 0x1 -#define GPIO_FUNC103_IN_INV_SEL_S 5 - -/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC103_IN_SEL 0x0000001f -#define GPIO_FUNC103_IN_SEL_M ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S)) -#define GPIO_FUNC103_IN_SEL_V 0x1f -#define GPIO_FUNC103_IN_SEL_S 0 - -#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f4) - -/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG104_IN_SEL (BIT(6)) -#define GPIO_SIG104_IN_SEL_M (BIT(6)) -#define GPIO_SIG104_IN_SEL_V 0x1 -#define GPIO_SIG104_IN_SEL_S 6 - -/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC104_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC104_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC104_IN_INV_SEL_V 0x1 -#define GPIO_FUNC104_IN_INV_SEL_S 5 - -/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC104_IN_SEL 0x0000001f -#define GPIO_FUNC104_IN_SEL_M ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S)) -#define GPIO_FUNC104_IN_SEL_V 0x1f -#define GPIO_FUNC104_IN_SEL_S 0 - -#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2f8) - -/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG105_IN_SEL (BIT(6)) -#define GPIO_SIG105_IN_SEL_M (BIT(6)) -#define GPIO_SIG105_IN_SEL_V 0x1 -#define GPIO_SIG105_IN_SEL_S 6 - -/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC105_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC105_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC105_IN_INV_SEL_V 0x1 -#define GPIO_FUNC105_IN_INV_SEL_S 5 - -/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC105_IN_SEL 0x0000001f -#define GPIO_FUNC105_IN_SEL_M ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S)) -#define GPIO_FUNC105_IN_SEL_V 0x1f -#define GPIO_FUNC105_IN_SEL_S 0 - -#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2fc) - -/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG106_IN_SEL (BIT(6)) -#define GPIO_SIG106_IN_SEL_M (BIT(6)) -#define GPIO_SIG106_IN_SEL_V 0x1 -#define GPIO_SIG106_IN_SEL_S 6 - -/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC106_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC106_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC106_IN_INV_SEL_V 0x1 -#define GPIO_FUNC106_IN_INV_SEL_S 5 - -/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC106_IN_SEL 0x0000001f -#define GPIO_FUNC106_IN_SEL_M ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S)) -#define GPIO_FUNC106_IN_SEL_V 0x1f -#define GPIO_FUNC106_IN_SEL_S 0 - -#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) - -/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG107_IN_SEL (BIT(6)) -#define GPIO_SIG107_IN_SEL_M (BIT(6)) -#define GPIO_SIG107_IN_SEL_V 0x1 -#define GPIO_SIG107_IN_SEL_S 6 - -/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC107_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC107_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC107_IN_INV_SEL_V 0x1 -#define GPIO_FUNC107_IN_INV_SEL_S 5 - -/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC107_IN_SEL 0x0000001f -#define GPIO_FUNC107_IN_SEL_M ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S)) -#define GPIO_FUNC107_IN_SEL_V 0x1f -#define GPIO_FUNC107_IN_SEL_S 0 - -#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) - -/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG108_IN_SEL (BIT(6)) -#define GPIO_SIG108_IN_SEL_M (BIT(6)) -#define GPIO_SIG108_IN_SEL_V 0x1 -#define GPIO_SIG108_IN_SEL_S 6 - -/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC108_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC108_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC108_IN_INV_SEL_V 0x1 -#define GPIO_FUNC108_IN_INV_SEL_S 5 - -/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC108_IN_SEL 0x0000001f -#define GPIO_FUNC108_IN_SEL_M ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S)) -#define GPIO_FUNC108_IN_SEL_V 0x1f -#define GPIO_FUNC108_IN_SEL_S 0 - -#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) - -/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG109_IN_SEL (BIT(6)) -#define GPIO_SIG109_IN_SEL_M (BIT(6)) -#define GPIO_SIG109_IN_SEL_V 0x1 -#define GPIO_SIG109_IN_SEL_S 6 - -/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC109_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC109_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC109_IN_INV_SEL_V 0x1 -#define GPIO_FUNC109_IN_INV_SEL_S 5 - -/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC109_IN_SEL 0x0000001f -#define GPIO_FUNC109_IN_SEL_M ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S)) -#define GPIO_FUNC109_IN_SEL_V 0x1f -#define GPIO_FUNC109_IN_SEL_S 0 - -#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30c) - -/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG110_IN_SEL (BIT(6)) -#define GPIO_SIG110_IN_SEL_M (BIT(6)) -#define GPIO_SIG110_IN_SEL_V 0x1 -#define GPIO_SIG110_IN_SEL_S 6 - -/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC110_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC110_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC110_IN_INV_SEL_V 0x1 -#define GPIO_FUNC110_IN_INV_SEL_S 5 - -/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC110_IN_SEL 0x0000001f -#define GPIO_FUNC110_IN_SEL_M ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S)) -#define GPIO_FUNC110_IN_SEL_V 0x1f -#define GPIO_FUNC110_IN_SEL_S 0 - -#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) - -/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG111_IN_SEL (BIT(6)) -#define GPIO_SIG111_IN_SEL_M (BIT(6)) -#define GPIO_SIG111_IN_SEL_V 0x1 -#define GPIO_SIG111_IN_SEL_S 6 - -/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC111_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC111_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC111_IN_INV_SEL_V 0x1 -#define GPIO_FUNC111_IN_INV_SEL_S 5 - -/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC111_IN_SEL 0x0000001f -#define GPIO_FUNC111_IN_SEL_M ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S)) -#define GPIO_FUNC111_IN_SEL_V 0x1f -#define GPIO_FUNC111_IN_SEL_S 0 - -#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) - -/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG112_IN_SEL (BIT(6)) -#define GPIO_SIG112_IN_SEL_M (BIT(6)) -#define GPIO_SIG112_IN_SEL_V 0x1 -#define GPIO_SIG112_IN_SEL_S 6 - -/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC112_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC112_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC112_IN_INV_SEL_V 0x1 -#define GPIO_FUNC112_IN_INV_SEL_S 5 - -/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC112_IN_SEL 0x0000001f -#define GPIO_FUNC112_IN_SEL_M ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S)) -#define GPIO_FUNC112_IN_SEL_V 0x1f -#define GPIO_FUNC112_IN_SEL_S 0 - -#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) - -/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG113_IN_SEL (BIT(6)) -#define GPIO_SIG113_IN_SEL_M (BIT(6)) -#define GPIO_SIG113_IN_SEL_V 0x1 -#define GPIO_SIG113_IN_SEL_S 6 - -/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC113_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC113_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC113_IN_INV_SEL_V 0x1 -#define GPIO_FUNC113_IN_INV_SEL_S 5 - -/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC113_IN_SEL 0x0000001f -#define GPIO_FUNC113_IN_SEL_M ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S)) -#define GPIO_FUNC113_IN_SEL_V 0x1f -#define GPIO_FUNC113_IN_SEL_S 0 - -#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31c) - -/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG114_IN_SEL (BIT(6)) -#define GPIO_SIG114_IN_SEL_M (BIT(6)) -#define GPIO_SIG114_IN_SEL_V 0x1 -#define GPIO_SIG114_IN_SEL_S 6 - -/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC114_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC114_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC114_IN_INV_SEL_V 0x1 -#define GPIO_FUNC114_IN_INV_SEL_S 5 - -/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC114_IN_SEL 0x0000001f -#define GPIO_FUNC114_IN_SEL_M ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S)) -#define GPIO_FUNC114_IN_SEL_V 0x1f -#define GPIO_FUNC114_IN_SEL_S 0 - -#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) - -/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG115_IN_SEL (BIT(6)) -#define GPIO_SIG115_IN_SEL_M (BIT(6)) -#define GPIO_SIG115_IN_SEL_V 0x1 -#define GPIO_SIG115_IN_SEL_S 6 - -/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC115_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC115_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC115_IN_INV_SEL_V 0x1 -#define GPIO_FUNC115_IN_INV_SEL_S 5 - -/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC115_IN_SEL 0x0000001f -#define GPIO_FUNC115_IN_SEL_M ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S)) -#define GPIO_FUNC115_IN_SEL_V 0x1f -#define GPIO_FUNC115_IN_SEL_S 0 - -#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) - -/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG116_IN_SEL (BIT(6)) -#define GPIO_SIG116_IN_SEL_M (BIT(6)) -#define GPIO_SIG116_IN_SEL_V 0x1 -#define GPIO_SIG116_IN_SEL_S 6 - -/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC116_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC116_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC116_IN_INV_SEL_V 0x1 -#define GPIO_FUNC116_IN_INV_SEL_S 5 - -/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC116_IN_SEL 0x0000001f -#define GPIO_FUNC116_IN_SEL_M ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S)) -#define GPIO_FUNC116_IN_SEL_V 0x1f -#define GPIO_FUNC116_IN_SEL_S 0 - -#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) - -/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG117_IN_SEL (BIT(6)) -#define GPIO_SIG117_IN_SEL_M (BIT(6)) -#define GPIO_SIG117_IN_SEL_V 0x1 -#define GPIO_SIG117_IN_SEL_S 6 - -/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC117_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC117_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC117_IN_INV_SEL_V 0x1 -#define GPIO_FUNC117_IN_INV_SEL_S 5 - -/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC117_IN_SEL 0x0000001f -#define GPIO_FUNC117_IN_SEL_M ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S)) -#define GPIO_FUNC117_IN_SEL_V 0x1f -#define GPIO_FUNC117_IN_SEL_S 0 - -#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32c) - -/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG118_IN_SEL (BIT(6)) -#define GPIO_SIG118_IN_SEL_M (BIT(6)) -#define GPIO_SIG118_IN_SEL_V 0x1 -#define GPIO_SIG118_IN_SEL_S 6 - -/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC118_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC118_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC118_IN_INV_SEL_V 0x1 -#define GPIO_FUNC118_IN_INV_SEL_S 5 - -/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC118_IN_SEL 0x0000001f -#define GPIO_FUNC118_IN_SEL_M ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S)) -#define GPIO_FUNC118_IN_SEL_V 0x1f -#define GPIO_FUNC118_IN_SEL_S 0 - -#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) - -/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG119_IN_SEL (BIT(6)) -#define GPIO_SIG119_IN_SEL_M (BIT(6)) -#define GPIO_SIG119_IN_SEL_V 0x1 -#define GPIO_SIG119_IN_SEL_S 6 - -/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC119_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC119_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC119_IN_INV_SEL_V 0x1 -#define GPIO_FUNC119_IN_INV_SEL_S 5 - -/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC119_IN_SEL 0x0000001f -#define GPIO_FUNC119_IN_SEL_M ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S)) -#define GPIO_FUNC119_IN_SEL_V 0x1f -#define GPIO_FUNC119_IN_SEL_S 0 - -#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) - -/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG120_IN_SEL (BIT(6)) -#define GPIO_SIG120_IN_SEL_M (BIT(6)) -#define GPIO_SIG120_IN_SEL_V 0x1 -#define GPIO_SIG120_IN_SEL_S 6 - -/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC120_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC120_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC120_IN_INV_SEL_V 0x1 -#define GPIO_FUNC120_IN_INV_SEL_S 5 - -/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC120_IN_SEL 0x0000001f -#define GPIO_FUNC120_IN_SEL_M ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S)) -#define GPIO_FUNC120_IN_SEL_V 0x1f -#define GPIO_FUNC120_IN_SEL_S 0 - -#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) - -/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG121_IN_SEL (BIT(6)) -#define GPIO_SIG121_IN_SEL_M (BIT(6)) -#define GPIO_SIG121_IN_SEL_V 0x1 -#define GPIO_SIG121_IN_SEL_S 6 - -/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC121_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC121_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC121_IN_INV_SEL_V 0x1 -#define GPIO_FUNC121_IN_INV_SEL_S 5 - -/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC121_IN_SEL 0x0000001f -#define GPIO_FUNC121_IN_SEL_M ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S)) -#define GPIO_FUNC121_IN_SEL_V 0x1f -#define GPIO_FUNC121_IN_SEL_S 0 - -#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33c) - -/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG122_IN_SEL (BIT(6)) -#define GPIO_SIG122_IN_SEL_M (BIT(6)) -#define GPIO_SIG122_IN_SEL_V 0x1 -#define GPIO_SIG122_IN_SEL_S 6 - -/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC122_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC122_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC122_IN_INV_SEL_V 0x1 -#define GPIO_FUNC122_IN_INV_SEL_S 5 - -/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC122_IN_SEL 0x0000001f -#define GPIO_FUNC122_IN_SEL_M ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S)) -#define GPIO_FUNC122_IN_SEL_V 0x1f -#define GPIO_FUNC122_IN_SEL_S 0 - -#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) - -/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG123_IN_SEL (BIT(6)) -#define GPIO_SIG123_IN_SEL_M (BIT(6)) -#define GPIO_SIG123_IN_SEL_V 0x1 -#define GPIO_SIG123_IN_SEL_S 6 - -/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC123_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC123_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC123_IN_INV_SEL_V 0x1 -#define GPIO_FUNC123_IN_INV_SEL_S 5 - -/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC123_IN_SEL 0x0000001f -#define GPIO_FUNC123_IN_SEL_M ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S)) -#define GPIO_FUNC123_IN_SEL_V 0x1f -#define GPIO_FUNC123_IN_SEL_S 0 - -#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) - -/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG124_IN_SEL (BIT(6)) -#define GPIO_SIG124_IN_SEL_M (BIT(6)) -#define GPIO_SIG124_IN_SEL_V 0x1 -#define GPIO_SIG124_IN_SEL_S 6 - -/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC124_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC124_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC124_IN_INV_SEL_V 0x1 -#define GPIO_FUNC124_IN_INV_SEL_S 5 - -/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ -#define GPIO_FUNC124_IN_SEL 0x0000001f -#define GPIO_FUNC124_IN_SEL_M ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S)) -#define GPIO_FUNC124_IN_SEL_V 0x1f -#define GPIO_FUNC124_IN_SEL_S 0 - -#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) - -/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG125_IN_SEL (BIT(6)) -#define GPIO_SIG125_IN_SEL_M (BIT(6)) -#define GPIO_SIG125_IN_SEL_V 0x1 -#define GPIO_SIG125_IN_SEL_S 6 - -/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC125_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC125_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC125_IN_INV_SEL_V 0x1 -#define GPIO_FUNC125_IN_INV_SEL_S 5 - -/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC125_IN_SEL 0x0000001f -#define GPIO_FUNC125_IN_SEL_M ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S)) -#define GPIO_FUNC125_IN_SEL_V 0x1f -#define GPIO_FUNC125_IN_SEL_S 0 - -#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34c) - -/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG126_IN_SEL (BIT(6)) -#define GPIO_SIG126_IN_SEL_M (BIT(6)) -#define GPIO_SIG126_IN_SEL_V 0x1 -#define GPIO_SIG126_IN_SEL_S 6 - -/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC126_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC126_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC126_IN_INV_SEL_V 0x1 -#define GPIO_FUNC126_IN_INV_SEL_S 5 - -/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC126_IN_SEL 0x0000001f -#define GPIO_FUNC126_IN_SEL_M ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S)) -#define GPIO_FUNC126_IN_SEL_V 0x1f -#define GPIO_FUNC126_IN_SEL_S 0 - -#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) - -/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -#define GPIO_SIG127_IN_SEL (BIT(6)) -#define GPIO_SIG127_IN_SEL_M (BIT(6)) -#define GPIO_SIG127_IN_SEL_V 0x1 -#define GPIO_SIG127_IN_SEL_S 6 - -/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -#define GPIO_FUNC127_IN_INV_SEL (BIT(5)) -#define GPIO_FUNC127_IN_INV_SEL_M (BIT(5)) -#define GPIO_FUNC127_IN_INV_SEL_V 0x1 -#define GPIO_FUNC127_IN_INV_SEL_S 5 - -/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[4:0] ;default: 5'h0 ; */ - -#define GPIO_FUNC127_IN_SEL 0x0000001f -#define GPIO_FUNC127_IN_SEL_M ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S)) -#define GPIO_FUNC127_IN_SEL_V 0x1f -#define GPIO_FUNC127_IN_SEL_S 0 - -#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) - -/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC0_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC0_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC0_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC0_OEN_INV_SEL_S 10 - -/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC0_OEN_SEL (BIT(9)) -#define GPIO_FUNC0_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC0_OEN_SEL_V 0x1 -#define GPIO_FUNC0_OEN_SEL_S 9 - -/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC0_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC0_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC0_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC0_OUT_INV_SEL_S 8 - -/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC0_OUT_SEL 0x000000ff -#define GPIO_FUNC0_OUT_SEL_M ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S)) -#define GPIO_FUNC0_OUT_SEL_V 0xff -#define GPIO_FUNC0_OUT_SEL_S 0 - -#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558) - -/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC1_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC1_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC1_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC1_OEN_INV_SEL_S 10 - -/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC1_OEN_SEL (BIT(9)) -#define GPIO_FUNC1_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC1_OEN_SEL_V 0x1 -#define GPIO_FUNC1_OEN_SEL_S 9 - -/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC1_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC1_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC1_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC1_OUT_INV_SEL_S 8 - -/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC1_OUT_SEL 0x000000ff -#define GPIO_FUNC1_OUT_SEL_M ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S)) -#define GPIO_FUNC1_OUT_SEL_V 0xff -#define GPIO_FUNC1_OUT_SEL_S 0 - -#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55c) - -/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC2_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC2_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC2_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC2_OEN_INV_SEL_S 10 - -/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC2_OEN_SEL (BIT(9)) -#define GPIO_FUNC2_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC2_OEN_SEL_V 0x1 -#define GPIO_FUNC2_OEN_SEL_S 9 - -/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC2_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC2_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC2_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC2_OUT_INV_SEL_S 8 - -/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC2_OUT_SEL 0x000000ff -#define GPIO_FUNC2_OUT_SEL_M ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S)) -#define GPIO_FUNC2_OUT_SEL_V 0xff -#define GPIO_FUNC2_OUT_SEL_S 0 - -#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560) - -/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC3_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC3_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC3_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC3_OEN_INV_SEL_S 10 - -/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC3_OEN_SEL (BIT(9)) -#define GPIO_FUNC3_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC3_OEN_SEL_V 0x1 -#define GPIO_FUNC3_OEN_SEL_S 9 - -/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC3_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC3_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC3_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC3_OUT_INV_SEL_S 8 - -/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC3_OUT_SEL 0x000000ff -#define GPIO_FUNC3_OUT_SEL_M ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S)) -#define GPIO_FUNC3_OUT_SEL_V 0xff -#define GPIO_FUNC3_OUT_SEL_S 0 - -#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564) - -/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC4_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC4_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC4_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC4_OEN_INV_SEL_S 10 - -/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC4_OEN_SEL (BIT(9)) -#define GPIO_FUNC4_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC4_OEN_SEL_V 0x1 -#define GPIO_FUNC4_OEN_SEL_S 9 - -/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC4_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC4_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC4_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC4_OUT_INV_SEL_S 8 - -/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC4_OUT_SEL 0x000000ff -#define GPIO_FUNC4_OUT_SEL_M ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S)) -#define GPIO_FUNC4_OUT_SEL_V 0xff -#define GPIO_FUNC4_OUT_SEL_S 0 - -#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568) - -/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC5_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC5_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC5_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC5_OEN_INV_SEL_S 10 - -/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC5_OEN_SEL (BIT(9)) -#define GPIO_FUNC5_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC5_OEN_SEL_V 0x1 -#define GPIO_FUNC5_OEN_SEL_S 9 - -/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC5_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC5_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC5_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC5_OUT_INV_SEL_S 8 - -/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC5_OUT_SEL 0x000000ff -#define GPIO_FUNC5_OUT_SEL_M ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S)) -#define GPIO_FUNC5_OUT_SEL_V 0xff -#define GPIO_FUNC5_OUT_SEL_S 0 - -#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56c) - -/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC6_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC6_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC6_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC6_OEN_INV_SEL_S 10 - -/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC6_OEN_SEL (BIT(9)) -#define GPIO_FUNC6_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC6_OEN_SEL_V 0x1 -#define GPIO_FUNC6_OEN_SEL_S 9 - -/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC6_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC6_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC6_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC6_OUT_INV_SEL_S 8 - -/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC6_OUT_SEL 0x000000ff -#define GPIO_FUNC6_OUT_SEL_M ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S)) -#define GPIO_FUNC6_OUT_SEL_V 0xff -#define GPIO_FUNC6_OUT_SEL_S 0 - -#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570) - -/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC7_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC7_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC7_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC7_OEN_INV_SEL_S 10 - -/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC7_OEN_SEL (BIT(9)) -#define GPIO_FUNC7_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC7_OEN_SEL_V 0x1 -#define GPIO_FUNC7_OEN_SEL_S 9 - -/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC7_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC7_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC7_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC7_OUT_INV_SEL_S 8 - -/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC7_OUT_SEL 0x000000ff -#define GPIO_FUNC7_OUT_SEL_M ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S)) -#define GPIO_FUNC7_OUT_SEL_V 0xff -#define GPIO_FUNC7_OUT_SEL_S 0 - -#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574) - -/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC8_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC8_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC8_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC8_OEN_INV_SEL_S 10 - -/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC8_OEN_SEL (BIT(9)) -#define GPIO_FUNC8_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC8_OEN_SEL_V 0x1 -#define GPIO_FUNC8_OEN_SEL_S 9 - -/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC8_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC8_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC8_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC8_OUT_INV_SEL_S 8 - -/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC8_OUT_SEL 0x000000ff -#define GPIO_FUNC8_OUT_SEL_M ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S)) -#define GPIO_FUNC8_OUT_SEL_V 0xff -#define GPIO_FUNC8_OUT_SEL_S 0 - -#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578) - -/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC9_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC9_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC9_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC9_OEN_INV_SEL_S 10 - -/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC9_OEN_SEL (BIT(9)) -#define GPIO_FUNC9_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC9_OEN_SEL_V 0x1 -#define GPIO_FUNC9_OEN_SEL_S 9 - -/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC9_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC9_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC9_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC9_OUT_INV_SEL_S 8 - -/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC9_OUT_SEL 0x000000ff -#define GPIO_FUNC9_OUT_SEL_M ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S)) -#define GPIO_FUNC9_OUT_SEL_V 0xff -#define GPIO_FUNC9_OUT_SEL_S 0 - -#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57c) - -/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC10_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC10_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC10_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC10_OEN_INV_SEL_S 10 - -/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC10_OEN_SEL (BIT(9)) -#define GPIO_FUNC10_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC10_OEN_SEL_V 0x1 -#define GPIO_FUNC10_OEN_SEL_S 9 - -/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC10_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC10_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC10_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC10_OUT_INV_SEL_S 8 - -/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC10_OUT_SEL 0x000000ff -#define GPIO_FUNC10_OUT_SEL_M ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S)) -#define GPIO_FUNC10_OUT_SEL_V 0xff -#define GPIO_FUNC10_OUT_SEL_S 0 - -#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580) - -/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC11_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC11_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC11_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC11_OEN_INV_SEL_S 10 - -/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC11_OEN_SEL (BIT(9)) -#define GPIO_FUNC11_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC11_OEN_SEL_V 0x1 -#define GPIO_FUNC11_OEN_SEL_S 9 - -/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC11_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC11_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC11_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC11_OUT_INV_SEL_S 8 - -/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC11_OUT_SEL 0x000000ff -#define GPIO_FUNC11_OUT_SEL_M ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S)) -#define GPIO_FUNC11_OUT_SEL_V 0xff -#define GPIO_FUNC11_OUT_SEL_S 0 - -#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584) - -/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC12_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC12_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC12_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC12_OEN_INV_SEL_S 10 - -/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC12_OEN_SEL (BIT(9)) -#define GPIO_FUNC12_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC12_OEN_SEL_V 0x1 -#define GPIO_FUNC12_OEN_SEL_S 9 - -/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC12_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC12_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC12_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC12_OUT_INV_SEL_S 8 - -/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC12_OUT_SEL 0x000000ff -#define GPIO_FUNC12_OUT_SEL_M ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S)) -#define GPIO_FUNC12_OUT_SEL_V 0xff -#define GPIO_FUNC12_OUT_SEL_S 0 - -#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588) - -/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC13_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC13_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC13_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC13_OEN_INV_SEL_S 10 - -/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC13_OEN_SEL (BIT(9)) -#define GPIO_FUNC13_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC13_OEN_SEL_V 0x1 -#define GPIO_FUNC13_OEN_SEL_S 9 - -/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC13_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC13_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC13_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC13_OUT_INV_SEL_S 8 - -/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC13_OUT_SEL 0x000000ff -#define GPIO_FUNC13_OUT_SEL_M ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S)) -#define GPIO_FUNC13_OUT_SEL_V 0xff -#define GPIO_FUNC13_OUT_SEL_S 0 - -#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58c) - -/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC14_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC14_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC14_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC14_OEN_INV_SEL_S 10 - -/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC14_OEN_SEL (BIT(9)) -#define GPIO_FUNC14_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC14_OEN_SEL_V 0x1 -#define GPIO_FUNC14_OEN_SEL_S 9 - -/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC14_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC14_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC14_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC14_OUT_INV_SEL_S 8 - -/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC14_OUT_SEL 0x000000ff -#define GPIO_FUNC14_OUT_SEL_M ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S)) -#define GPIO_FUNC14_OUT_SEL_V 0xff -#define GPIO_FUNC14_OUT_SEL_S 0 - -#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590) - -/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC15_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC15_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC15_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC15_OEN_INV_SEL_S 10 - -/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC15_OEN_SEL (BIT(9)) -#define GPIO_FUNC15_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC15_OEN_SEL_V 0x1 -#define GPIO_FUNC15_OEN_SEL_S 9 - -/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC15_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC15_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC15_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC15_OUT_INV_SEL_S 8 - -/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC15_OUT_SEL 0x000000ff -#define GPIO_FUNC15_OUT_SEL_M ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S)) -#define GPIO_FUNC15_OUT_SEL_V 0xff -#define GPIO_FUNC15_OUT_SEL_S 0 - -#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594) - -/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC16_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC16_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC16_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC16_OEN_INV_SEL_S 10 - -/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC16_OEN_SEL (BIT(9)) -#define GPIO_FUNC16_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC16_OEN_SEL_V 0x1 -#define GPIO_FUNC16_OEN_SEL_S 9 - -/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC16_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC16_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC16_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC16_OUT_INV_SEL_S 8 - -/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC16_OUT_SEL 0x000000ff -#define GPIO_FUNC16_OUT_SEL_M ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S)) -#define GPIO_FUNC16_OUT_SEL_V 0xff -#define GPIO_FUNC16_OUT_SEL_S 0 - -#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598) - -/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC17_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC17_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC17_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC17_OEN_INV_SEL_S 10 - -/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC17_OEN_SEL (BIT(9)) -#define GPIO_FUNC17_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC17_OEN_SEL_V 0x1 -#define GPIO_FUNC17_OEN_SEL_S 9 - -/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC17_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC17_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC17_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC17_OUT_INV_SEL_S 8 - -/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC17_OUT_SEL 0x000000ff -#define GPIO_FUNC17_OUT_SEL_M ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S)) -#define GPIO_FUNC17_OUT_SEL_V 0xff -#define GPIO_FUNC17_OUT_SEL_S 0 - -#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59c) - -/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC18_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC18_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC18_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC18_OEN_INV_SEL_S 10 - -/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC18_OEN_SEL (BIT(9)) -#define GPIO_FUNC18_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC18_OEN_SEL_V 0x1 -#define GPIO_FUNC18_OEN_SEL_S 9 - -/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC18_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC18_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC18_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC18_OUT_INV_SEL_S 8 - -/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC18_OUT_SEL 0x000000ff -#define GPIO_FUNC18_OUT_SEL_M ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S)) -#define GPIO_FUNC18_OUT_SEL_V 0xff -#define GPIO_FUNC18_OUT_SEL_S 0 - -#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a0) - -/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC19_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC19_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC19_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC19_OEN_INV_SEL_S 10 - -/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC19_OEN_SEL (BIT(9)) -#define GPIO_FUNC19_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC19_OEN_SEL_V 0x1 -#define GPIO_FUNC19_OEN_SEL_S 9 - -/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC19_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC19_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC19_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC19_OUT_INV_SEL_S 8 - -/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC19_OUT_SEL 0x000000ff -#define GPIO_FUNC19_OUT_SEL_M ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S)) -#define GPIO_FUNC19_OUT_SEL_V 0xff -#define GPIO_FUNC19_OUT_SEL_S 0 - -#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a4) - -/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC20_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC20_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC20_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC20_OEN_INV_SEL_S 10 - -/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC20_OEN_SEL (BIT(9)) -#define GPIO_FUNC20_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC20_OEN_SEL_V 0x1 -#define GPIO_FUNC20_OEN_SEL_S 9 - -/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC20_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC20_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC20_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC20_OUT_INV_SEL_S 8 - -/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC20_OUT_SEL 0x000000ff -#define GPIO_FUNC20_OUT_SEL_M ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S)) -#define GPIO_FUNC20_OUT_SEL_V 0xff -#define GPIO_FUNC20_OUT_SEL_S 0 - -#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5a8) - -/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC21_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC21_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC21_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC21_OEN_INV_SEL_S 10 - -/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC21_OEN_SEL (BIT(9)) -#define GPIO_FUNC21_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC21_OEN_SEL_V 0x1 -#define GPIO_FUNC21_OEN_SEL_S 9 - -/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC21_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC21_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC21_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC21_OUT_INV_SEL_S 8 - -/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC21_OUT_SEL 0x000000ff -#define GPIO_FUNC21_OUT_SEL_M ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S)) -#define GPIO_FUNC21_OUT_SEL_V 0xff -#define GPIO_FUNC21_OUT_SEL_S 0 - -#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5ac) - -/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC22_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC22_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC22_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC22_OEN_INV_SEL_S 10 - -/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC22_OEN_SEL (BIT(9)) -#define GPIO_FUNC22_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC22_OEN_SEL_V 0x1 -#define GPIO_FUNC22_OEN_SEL_S 9 - -/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC22_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC22_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC22_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC22_OUT_INV_SEL_S 8 - -/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC22_OUT_SEL 0x000000ff -#define GPIO_FUNC22_OUT_SEL_M ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S)) -#define GPIO_FUNC22_OUT_SEL_V 0xff -#define GPIO_FUNC22_OUT_SEL_S 0 - -#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b0) - -/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC23_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC23_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC23_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC23_OEN_INV_SEL_S 10 - -/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC23_OEN_SEL (BIT(9)) -#define GPIO_FUNC23_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC23_OEN_SEL_V 0x1 -#define GPIO_FUNC23_OEN_SEL_S 9 - -/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC23_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC23_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC23_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC23_OUT_INV_SEL_S 8 - -/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC23_OUT_SEL 0x000000ff -#define GPIO_FUNC23_OUT_SEL_M ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S)) -#define GPIO_FUNC23_OUT_SEL_V 0xff -#define GPIO_FUNC23_OUT_SEL_S 0 - -#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b4) - -/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC24_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC24_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC24_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC24_OEN_INV_SEL_S 10 - -/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC24_OEN_SEL (BIT(9)) -#define GPIO_FUNC24_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC24_OEN_SEL_V 0x1 -#define GPIO_FUNC24_OEN_SEL_S 9 - -/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC24_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC24_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC24_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC24_OUT_INV_SEL_S 8 - -/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC24_OUT_SEL 0x000000ff -#define GPIO_FUNC24_OUT_SEL_M ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S)) -#define GPIO_FUNC24_OUT_SEL_V 0xff -#define GPIO_FUNC24_OUT_SEL_S 0 - -#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5b8) - -/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ - -#define GPIO_FUNC25_OEN_INV_SEL (BIT(10)) -#define GPIO_FUNC25_OEN_INV_SEL_M (BIT(10)) -#define GPIO_FUNC25_OEN_INV_SEL_V 0x1 -#define GPIO_FUNC25_OEN_INV_SEL_S 10 - -/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ - -#define GPIO_FUNC25_OEN_SEL (BIT(9)) -#define GPIO_FUNC25_OEN_SEL_M (BIT(9)) -#define GPIO_FUNC25_OEN_SEL_V 0x1 -#define GPIO_FUNC25_OEN_SEL_S 9 - -/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -#define GPIO_FUNC25_OUT_INV_SEL (BIT(8)) -#define GPIO_FUNC25_OUT_INV_SEL_M (BIT(8)) -#define GPIO_FUNC25_OUT_INV_SEL_V 0x1 -#define GPIO_FUNC25_OUT_INV_SEL_S 8 - -/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[7:0] ;default: 8'h80 ; */ - -#define GPIO_FUNC25_OUT_SEL 0x000000ff -#define GPIO_FUNC25_OUT_SEL_M ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S)) -#define GPIO_FUNC25_OUT_SEL_V 0xff -#define GPIO_FUNC25_OUT_SEL_S 0 - -#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62c) - -/* GPIO_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ - -#define GPIO_CLK_EN (BIT(0)) -#define GPIO_CLK_EN_M (BIT(0)) -#define GPIO_CLK_EN_V 0x1 -#define GPIO_CLK_EN_S 0 - -#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x6fc) - -/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006130 ; */ - -#define GPIO_DATE 0x0fffffff -#define GPIO_DATE_M ((GPIO_DATE_V)<<(GPIO_DATE_S)) -#define GPIO_DATE_V 0xfffffff -#define GPIO_DATE_S 0 - -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_GPIO_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_i2c.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_i2c.h deleted file mode 100644 index 2874aaac2eed1..0000000000000 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_i2c.h +++ /dev/null @@ -1,1226 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_i2c.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_I2C_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_I2C_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32c3_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0) - -/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ - -#define I2C_SCL_LOW_PERIOD 0x000001FF -#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S)) -#define I2C_SCL_LOW_PERIOD_V 0x1FF -#define I2C_SCL_LOW_PERIOD_S 0 - -#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x4) - -/* I2C_ADDR_BROADCASTING_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ - -#define I2C_ADDR_BROADCASTING_EN (BIT(14)) -#define I2C_ADDR_BROADCASTING_EN_M (BIT(14)) -#define I2C_ADDR_BROADCASTING_EN_V 0x1 -#define I2C_ADDR_BROADCASTING_EN_S 14 - -/* I2C_ADDR_10BIT_RW_CHECK_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */ - -#define I2C_ADDR_10BIT_RW_CHECK_EN (BIT(13)) -#define I2C_ADDR_10BIT_RW_CHECK_EN_M (BIT(13)) -#define I2C_ADDR_10BIT_RW_CHECK_EN_V 0x1 -#define I2C_ADDR_10BIT_RW_CHECK_EN_S 13 - -/* I2C_SLV_TX_AUTO_START_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ - -#define I2C_SLV_TX_AUTO_START_EN (BIT(12)) -#define I2C_SLV_TX_AUTO_START_EN_M (BIT(12)) -#define I2C_SLV_TX_AUTO_START_EN_V 0x1 -#define I2C_SLV_TX_AUTO_START_EN_S 12 - -/* I2C_CONF_UPGATE : WT ;bitpos:[11] ;default: 1'b0 ; */ - -#define I2C_CONF_UPGATE (BIT(11)) -#define I2C_CONF_UPGATE_M (BIT(11)) -#define I2C_CONF_UPGATE_V 0x1 -#define I2C_CONF_UPGATE_S 11 - -/* I2C_FSM_RST : WT ;bitpos:[10] ;default: 1'b0 ; */ - -#define I2C_FSM_RST (BIT(10)) -#define I2C_FSM_RST_M (BIT(10)) -#define I2C_FSM_RST_V 0x1 -#define I2C_FSM_RST_S 10 - -/* I2C_ARBITRATION_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ - -#define I2C_ARBITRATION_EN (BIT(9)) -#define I2C_ARBITRATION_EN_M (BIT(9)) -#define I2C_ARBITRATION_EN_V 0x1 -#define I2C_ARBITRATION_EN_S 9 - -/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ - -#define I2C_CLK_EN (BIT(8)) -#define I2C_CLK_EN_M (BIT(8)) -#define I2C_CLK_EN_V 0x1 -#define I2C_CLK_EN_S 8 - -/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */ - -#define I2C_RX_LSB_FIRST (BIT(7)) -#define I2C_RX_LSB_FIRST_M (BIT(7)) -#define I2C_RX_LSB_FIRST_V 0x1 -#define I2C_RX_LSB_FIRST_S 7 - -/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ - -#define I2C_TX_LSB_FIRST (BIT(6)) -#define I2C_TX_LSB_FIRST_M (BIT(6)) -#define I2C_TX_LSB_FIRST_V 0x1 -#define I2C_TX_LSB_FIRST_S 6 - -/* I2C_TRANS_START : WT ;bitpos:[5] ;default: 1'b0 ; */ - -#define I2C_TRANS_START (BIT(5)) -#define I2C_TRANS_START_M (BIT(5)) -#define I2C_TRANS_START_V 0x1 -#define I2C_TRANS_START_S 5 - -/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -#define I2C_MS_MODE (BIT(4)) -#define I2C_MS_MODE_M (BIT(4)) -#define I2C_MS_MODE_V 0x1 -#define I2C_MS_MODE_S 4 - -/* I2C_RX_FULL_ACK_LEVEL : R/W ;bitpos:[3] ;default: 1'b1 ; */ - -#define I2C_RX_FULL_ACK_LEVEL (BIT(3)) -#define I2C_RX_FULL_ACK_LEVEL_M (BIT(3)) -#define I2C_RX_FULL_ACK_LEVEL_V 0x1 -#define I2C_RX_FULL_ACK_LEVEL_S 3 - -/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ - -#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) -#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2)) -#define I2C_SAMPLE_SCL_LEVEL_V 0x1 -#define I2C_SAMPLE_SCL_LEVEL_S 2 - -/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */ - -#define I2C_SCL_FORCE_OUT (BIT(1)) -#define I2C_SCL_FORCE_OUT_M (BIT(1)) -#define I2C_SCL_FORCE_OUT_V 0x1 -#define I2C_SCL_FORCE_OUT_S 1 - -/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */ - -#define I2C_SDA_FORCE_OUT (BIT(0)) -#define I2C_SDA_FORCE_OUT_M (BIT(0)) -#define I2C_SDA_FORCE_OUT_V 0x1 -#define I2C_SDA_FORCE_OUT_S 0 - -#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x8) - -/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ - -#define I2C_SCL_STATE_LAST 0x00000007 -#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S)) -#define I2C_SCL_STATE_LAST_V 0x7 -#define I2C_SCL_STATE_LAST_S 28 - -/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ - -#define I2C_SCL_MAIN_STATE_LAST 0x00000007 -#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S)) -#define I2C_SCL_MAIN_STATE_LAST_V 0x7 -#define I2C_SCL_MAIN_STATE_LAST_S 24 - -/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */ - -#define I2C_TXFIFO_CNT 0x0000003F -#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S)) -#define I2C_TXFIFO_CNT_V 0x3F -#define I2C_TXFIFO_CNT_S 18 - -/* I2C_STRETCH_CAUSE : RO ;bitpos:[15:14] ;default: 2'h3 ; */ - -#define I2C_STRETCH_CAUSE 0x00000003 -#define I2C_STRETCH_CAUSE_M ((I2C_STRETCH_CAUSE_V)<<(I2C_STRETCH_CAUSE_S)) -#define I2C_STRETCH_CAUSE_V 0x3 -#define I2C_STRETCH_CAUSE_S 14 - -/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */ - -#define I2C_RXFIFO_CNT 0x0000003F -#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S)) -#define I2C_RXFIFO_CNT_V 0x3F -#define I2C_RXFIFO_CNT_S 8 - -/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */ - -#define I2C_SLAVE_ADDRESSED (BIT(5)) -#define I2C_SLAVE_ADDRESSED_M (BIT(5)) -#define I2C_SLAVE_ADDRESSED_V 0x1 -#define I2C_SLAVE_ADDRESSED_S 5 - -/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */ - -#define I2C_BUS_BUSY (BIT(4)) -#define I2C_BUS_BUSY_M (BIT(4)) -#define I2C_BUS_BUSY_V 0x1 -#define I2C_BUS_BUSY_S 4 - -/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */ - -#define I2C_ARB_LOST (BIT(3)) -#define I2C_ARB_LOST_M (BIT(3)) -#define I2C_ARB_LOST_V 0x1 -#define I2C_ARB_LOST_S 3 - -/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ - -#define I2C_SLAVE_RW (BIT(1)) -#define I2C_SLAVE_RW_M (BIT(1)) -#define I2C_SLAVE_RW_V 0x1 -#define I2C_SLAVE_RW_S 1 - -/* I2C_RESP_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ - -#define I2C_RESP_REC (BIT(0)) -#define I2C_RESP_REC_M (BIT(0)) -#define I2C_RESP_REC_V 0x1 -#define I2C_RESP_REC_S 0 - -#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0xC) - -/* I2C_TIME_OUT_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ - -#define I2C_TIME_OUT_EN (BIT(5)) -#define I2C_TIME_OUT_EN_M (BIT(5)) -#define I2C_TIME_OUT_EN_V 0x1 -#define I2C_TIME_OUT_EN_S 5 - -/* I2C_TIME_OUT_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ - -#define I2C_TIME_OUT_REG 0x0000001F -#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S)) -#define I2C_TIME_OUT_REG_V 0x1F -#define I2C_TIME_OUT_REG_S 0 - -#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x10) - -/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ - -#define I2C_ADDR_10BIT_EN (BIT(31)) -#define I2C_ADDR_10BIT_EN_M (BIT(31)) -#define I2C_ADDR_10BIT_EN_V 0x1 -#define I2C_ADDR_10BIT_EN_S 31 - -/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ - -#define I2C_SLAVE_ADDR 0x00007FFF -#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S)) -#define I2C_SLAVE_ADDR_V 0x7FFF -#define I2C_SLAVE_ADDR_S 0 - -#define I2C_FIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x14) - -/* I2C_SLAVE_RW_POINT : RO ;bitpos:[29:22] ;default: 8'b0 ; */ - -#define I2C_SLAVE_RW_POINT 0x000000FF -#define I2C_SLAVE_RW_POINT_M ((I2C_SLAVE_RW_POINT_V)<<(I2C_SLAVE_RW_POINT_S)) -#define I2C_SLAVE_RW_POINT_V 0xFF -#define I2C_SLAVE_RW_POINT_S 22 - -/* I2C_TXFIFO_WADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */ - -#define I2C_TXFIFO_WADDR 0x0000001F -#define I2C_TXFIFO_WADDR_M ((I2C_TXFIFO_WADDR_V)<<(I2C_TXFIFO_WADDR_S)) -#define I2C_TXFIFO_WADDR_V 0x1F -#define I2C_TXFIFO_WADDR_S 15 - -/* I2C_TXFIFO_RADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */ - -#define I2C_TXFIFO_RADDR 0x0000001F -#define I2C_TXFIFO_RADDR_M ((I2C_TXFIFO_RADDR_V)<<(I2C_TXFIFO_RADDR_S)) -#define I2C_TXFIFO_RADDR_V 0x1F -#define I2C_TXFIFO_RADDR_S 10 - -/* I2C_RXFIFO_WADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */ - -#define I2C_RXFIFO_WADDR 0x0000001F -#define I2C_RXFIFO_WADDR_M ((I2C_RXFIFO_WADDR_V)<<(I2C_RXFIFO_WADDR_S)) -#define I2C_RXFIFO_WADDR_V 0x1F -#define I2C_RXFIFO_WADDR_S 5 - -/* I2C_RXFIFO_RADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */ - -#define I2C_RXFIFO_RADDR 0x0000001F -#define I2C_RXFIFO_RADDR_M ((I2C_RXFIFO_RADDR_V)<<(I2C_RXFIFO_RADDR_S)) -#define I2C_RXFIFO_RADDR_V 0x1F -#define I2C_RXFIFO_RADDR_S 0 - -#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x18) - -/* I2C_FIFO_PRT_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ - -#define I2C_FIFO_PRT_EN (BIT(14)) -#define I2C_FIFO_PRT_EN_M (BIT(14)) -#define I2C_FIFO_PRT_EN_V 0x1 -#define I2C_FIFO_PRT_EN_S 14 - -/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ - -#define I2C_TX_FIFO_RST (BIT(13)) -#define I2C_TX_FIFO_RST_M (BIT(13)) -#define I2C_TX_FIFO_RST_V 0x1 -#define I2C_TX_FIFO_RST_S 13 - -/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ - -#define I2C_RX_FIFO_RST (BIT(12)) -#define I2C_RX_FIFO_RST_M (BIT(12)) -#define I2C_RX_FIFO_RST_V 0x1 -#define I2C_RX_FIFO_RST_S 12 - -/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ - -#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) -#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11)) -#define I2C_FIFO_ADDR_CFG_EN_V 0x1 -#define I2C_FIFO_ADDR_CFG_EN_S 11 - -/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ - -#define I2C_NONFIFO_EN (BIT(10)) -#define I2C_NONFIFO_EN_M (BIT(10)) -#define I2C_NONFIFO_EN_V 0x1 -#define I2C_NONFIFO_EN_S 10 - -/* I2C_TXFIFO_WM_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ - -#define I2C_TXFIFO_WM_THRHD 0x0000001F -#define I2C_TXFIFO_WM_THRHD_M ((I2C_TXFIFO_WM_THRHD_V)<<(I2C_TXFIFO_WM_THRHD_S)) -#define I2C_TXFIFO_WM_THRHD_V 0x1F -#define I2C_TXFIFO_WM_THRHD_S 5 - -/* I2C_RXFIFO_WM_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */ - -#define I2C_RXFIFO_WM_THRHD 0x0000001F -#define I2C_RXFIFO_WM_THRHD_M ((I2C_RXFIFO_WM_THRHD_V)<<(I2C_RXFIFO_WM_THRHD_S)) -#define I2C_RXFIFO_WM_THRHD_V 0x1F -#define I2C_RXFIFO_WM_THRHD_S 0 - -#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x1C) - -/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */ - -#define I2C_FIFO_RDATA 0x000000FF -#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S)) -#define I2C_FIFO_RDATA_V 0xFF -#define I2C_FIFO_RDATA_S 0 - -#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x20) - -/* I2C_GENERAL_CALL_INT_RAW : R/SS/WTC ;bitpos:[17] ;default: 1'b0 ; */ - -#define I2C_GENERAL_CALL_INT_RAW (BIT(17)) -#define I2C_GENERAL_CALL_INT_RAW_M (BIT(17)) -#define I2C_GENERAL_CALL_INT_RAW_V 0x1 -#define I2C_GENERAL_CALL_INT_RAW_S 17 - -/* I2C_SLAVE_STRETCH_INT_RAW : R/SS/WTC ;bitpos:[16] ;default: 1'b0 ; */ - -#define I2C_SLAVE_STRETCH_INT_RAW (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_RAW_M (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_RAW_V 0x1 -#define I2C_SLAVE_STRETCH_INT_RAW_S 16 - -/* I2C_DET_START_INT_RAW : R/SS/WTC ;bitpos:[15] ;default: 1'b0 ; */ - -#define I2C_DET_START_INT_RAW (BIT(15)) -#define I2C_DET_START_INT_RAW_M (BIT(15)) -#define I2C_DET_START_INT_RAW_V 0x1 -#define I2C_DET_START_INT_RAW_S 15 - -/* I2C_SCL_MAIN_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[14] ;default: 1'b0 ; */ - -#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x1 -#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 - -/* I2C_SCL_ST_TO_INT_RAW : R/SS/WTC ;bitpos:[13] ;default: 1'b0 ; */ - -#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) -#define I2C_SCL_ST_TO_INT_RAW_M (BIT(13)) -#define I2C_SCL_ST_TO_INT_RAW_V 0x1 -#define I2C_SCL_ST_TO_INT_RAW_S 13 - -/* I2C_RXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[12] ;default: 1'b0 ; */ - -#define I2C_RXFIFO_UDF_INT_RAW (BIT(12)) -#define I2C_RXFIFO_UDF_INT_RAW_M (BIT(12)) -#define I2C_RXFIFO_UDF_INT_RAW_V 0x1 -#define I2C_RXFIFO_UDF_INT_RAW_S 12 - -/* I2C_TXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[11] ;default: 1'b0 ; */ - -#define I2C_TXFIFO_OVF_INT_RAW (BIT(11)) -#define I2C_TXFIFO_OVF_INT_RAW_M (BIT(11)) -#define I2C_TXFIFO_OVF_INT_RAW_V 0x1 -#define I2C_TXFIFO_OVF_INT_RAW_S 11 - -/* I2C_NACK_INT_RAW : R/SS/WTC ;bitpos:[10] ;default: 1'b0 ; */ - -#define I2C_NACK_INT_RAW (BIT(10)) -#define I2C_NACK_INT_RAW_M (BIT(10)) -#define I2C_NACK_INT_RAW_V 0x1 -#define I2C_NACK_INT_RAW_S 10 - -/* I2C_TRANS_START_INT_RAW : R/SS/WTC ;bitpos:[9] ;default: 1'b0 ; */ - -#define I2C_TRANS_START_INT_RAW (BIT(9)) -#define I2C_TRANS_START_INT_RAW_M (BIT(9)) -#define I2C_TRANS_START_INT_RAW_V 0x1 -#define I2C_TRANS_START_INT_RAW_S 9 - -/* I2C_TIME_OUT_INT_RAW : R/SS/WTC ;bitpos:[8] ;default: 1'b0 ; */ - -#define I2C_TIME_OUT_INT_RAW (BIT(8)) -#define I2C_TIME_OUT_INT_RAW_M (BIT(8)) -#define I2C_TIME_OUT_INT_RAW_V 0x1 -#define I2C_TIME_OUT_INT_RAW_S 8 - -/* I2C_TRANS_COMPLETE_INT_RAW : R/SS/WTC ;bitpos:[7] ;default: 1'b0 ; */ - -#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1 -#define I2C_TRANS_COMPLETE_INT_RAW_S 7 - -/* I2C_MST_TXFIFO_UDF_INT_RAW : R/SS/WTC ;bitpos:[6] ;default: 1'b0 ; */ - -#define I2C_MST_TXFIFO_UDF_INT_RAW (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_RAW_M (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_RAW_V 0x1 -#define I2C_MST_TXFIFO_UDF_INT_RAW_S 6 - -/* I2C_ARBITRATION_LOST_INT_RAW : R/SS/WTC ;bitpos:[5] ;default: 1'b0 ; */ - -#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1 -#define I2C_ARBITRATION_LOST_INT_RAW_S 5 - -/* I2C_BYTE_TRANS_DONE_INT_RAW : R/SS/WTC ;bitpos:[4] ;default: 1'b0 ; */ - -#define I2C_BYTE_TRANS_DONE_INT_RAW (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_RAW_M (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_RAW_V 0x1 -#define I2C_BYTE_TRANS_DONE_INT_RAW_S 4 - -/* I2C_END_DETECT_INT_RAW : R/SS/WTC ;bitpos:[3] ;default: 1'b0 ; */ - -#define I2C_END_DETECT_INT_RAW (BIT(3)) -#define I2C_END_DETECT_INT_RAW_M (BIT(3)) -#define I2C_END_DETECT_INT_RAW_V 0x1 -#define I2C_END_DETECT_INT_RAW_S 3 - -/* I2C_RXFIFO_OVF_INT_RAW : R/SS/WTC ;bitpos:[2] ;default: 1'b0 ; */ - -#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) -#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_RAW_V 0x1 -#define I2C_RXFIFO_OVF_INT_RAW_S 2 - -/* I2C_TXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'b1 ; */ - -#define I2C_TXFIFO_WM_INT_RAW (BIT(1)) -#define I2C_TXFIFO_WM_INT_RAW_M (BIT(1)) -#define I2C_TXFIFO_WM_INT_RAW_V 0x1 -#define I2C_TXFIFO_WM_INT_RAW_S 1 - -/* I2C_RXFIFO_WM_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'b0 ; */ - -#define I2C_RXFIFO_WM_INT_RAW (BIT(0)) -#define I2C_RXFIFO_WM_INT_RAW_M (BIT(0)) -#define I2C_RXFIFO_WM_INT_RAW_V 0x1 -#define I2C_RXFIFO_WM_INT_RAW_S 0 - -#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x24) - -/* I2C_GENERAL_CALL_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */ - -#define I2C_GENERAL_CALL_INT_CLR (BIT(17)) -#define I2C_GENERAL_CALL_INT_CLR_M (BIT(17)) -#define I2C_GENERAL_CALL_INT_CLR_V 0x1 -#define I2C_GENERAL_CALL_INT_CLR_S 17 - -/* I2C_SLAVE_STRETCH_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */ - -#define I2C_SLAVE_STRETCH_INT_CLR (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_CLR_M (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_CLR_V 0x1 -#define I2C_SLAVE_STRETCH_INT_CLR_S 16 - -/* I2C_DET_START_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */ - -#define I2C_DET_START_INT_CLR (BIT(15)) -#define I2C_DET_START_INT_CLR_M (BIT(15)) -#define I2C_DET_START_INT_CLR_V 0x1 -#define I2C_DET_START_INT_CLR_S 15 - -/* I2C_SCL_MAIN_ST_TO_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */ - -#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x1 -#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 - -/* I2C_SCL_ST_TO_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ - -#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) -#define I2C_SCL_ST_TO_INT_CLR_M (BIT(13)) -#define I2C_SCL_ST_TO_INT_CLR_V 0x1 -#define I2C_SCL_ST_TO_INT_CLR_S 13 - -/* I2C_RXFIFO_UDF_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ - -#define I2C_RXFIFO_UDF_INT_CLR (BIT(12)) -#define I2C_RXFIFO_UDF_INT_CLR_M (BIT(12)) -#define I2C_RXFIFO_UDF_INT_CLR_V 0x1 -#define I2C_RXFIFO_UDF_INT_CLR_S 12 - -/* I2C_TXFIFO_OVF_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ - -#define I2C_TXFIFO_OVF_INT_CLR (BIT(11)) -#define I2C_TXFIFO_OVF_INT_CLR_M (BIT(11)) -#define I2C_TXFIFO_OVF_INT_CLR_V 0x1 -#define I2C_TXFIFO_OVF_INT_CLR_S 11 - -/* I2C_NACK_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ - -#define I2C_NACK_INT_CLR (BIT(10)) -#define I2C_NACK_INT_CLR_M (BIT(10)) -#define I2C_NACK_INT_CLR_V 0x1 -#define I2C_NACK_INT_CLR_S 10 - -/* I2C_TRANS_START_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ - -#define I2C_TRANS_START_INT_CLR (BIT(9)) -#define I2C_TRANS_START_INT_CLR_M (BIT(9)) -#define I2C_TRANS_START_INT_CLR_V 0x1 -#define I2C_TRANS_START_INT_CLR_S 9 - -/* I2C_TIME_OUT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ - -#define I2C_TIME_OUT_INT_CLR (BIT(8)) -#define I2C_TIME_OUT_INT_CLR_M (BIT(8)) -#define I2C_TIME_OUT_INT_CLR_V 0x1 -#define I2C_TIME_OUT_INT_CLR_S 8 - -/* I2C_TRANS_COMPLETE_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ - -#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1 -#define I2C_TRANS_COMPLETE_INT_CLR_S 7 - -/* I2C_MST_TXFIFO_UDF_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ - -#define I2C_MST_TXFIFO_UDF_INT_CLR (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_CLR_M (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_CLR_V 0x1 -#define I2C_MST_TXFIFO_UDF_INT_CLR_S 6 - -/* I2C_ARBITRATION_LOST_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ - -#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1 -#define I2C_ARBITRATION_LOST_INT_CLR_S 5 - -/* I2C_BYTE_TRANS_DONE_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ - -#define I2C_BYTE_TRANS_DONE_INT_CLR (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_CLR_M (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_CLR_V 0x1 -#define I2C_BYTE_TRANS_DONE_INT_CLR_S 4 - -/* I2C_END_DETECT_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ - -#define I2C_END_DETECT_INT_CLR (BIT(3)) -#define I2C_END_DETECT_INT_CLR_M (BIT(3)) -#define I2C_END_DETECT_INT_CLR_V 0x1 -#define I2C_END_DETECT_INT_CLR_S 3 - -/* I2C_RXFIFO_OVF_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ - -#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) -#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_CLR_V 0x1 -#define I2C_RXFIFO_OVF_INT_CLR_S 2 - -/* I2C_TXFIFO_WM_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ - -#define I2C_TXFIFO_WM_INT_CLR (BIT(1)) -#define I2C_TXFIFO_WM_INT_CLR_M (BIT(1)) -#define I2C_TXFIFO_WM_INT_CLR_V 0x1 -#define I2C_TXFIFO_WM_INT_CLR_S 1 - -/* I2C_RXFIFO_WM_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ - -#define I2C_RXFIFO_WM_INT_CLR (BIT(0)) -#define I2C_RXFIFO_WM_INT_CLR_M (BIT(0)) -#define I2C_RXFIFO_WM_INT_CLR_V 0x1 -#define I2C_RXFIFO_WM_INT_CLR_S 0 - -#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x28) - -/* I2C_GENERAL_CALL_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ - -#define I2C_GENERAL_CALL_INT_ENA (BIT(17)) -#define I2C_GENERAL_CALL_INT_ENA_M (BIT(17)) -#define I2C_GENERAL_CALL_INT_ENA_V 0x1 -#define I2C_GENERAL_CALL_INT_ENA_S 17 - -/* I2C_SLAVE_STRETCH_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ - -#define I2C_SLAVE_STRETCH_INT_ENA (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_ENA_M (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_ENA_V 0x1 -#define I2C_SLAVE_STRETCH_INT_ENA_S 16 - -/* I2C_DET_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ - -#define I2C_DET_START_INT_ENA (BIT(15)) -#define I2C_DET_START_INT_ENA_M (BIT(15)) -#define I2C_DET_START_INT_ENA_V 0x1 -#define I2C_DET_START_INT_ENA_S 15 - -/* I2C_SCL_MAIN_ST_TO_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ - -#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x1 -#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 - -/* I2C_SCL_ST_TO_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ - -#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) -#define I2C_SCL_ST_TO_INT_ENA_M (BIT(13)) -#define I2C_SCL_ST_TO_INT_ENA_V 0x1 -#define I2C_SCL_ST_TO_INT_ENA_S 13 - -/* I2C_RXFIFO_UDF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ - -#define I2C_RXFIFO_UDF_INT_ENA (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ENA_M (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ENA_V 0x1 -#define I2C_RXFIFO_UDF_INT_ENA_S 12 - -/* I2C_TXFIFO_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ - -#define I2C_TXFIFO_OVF_INT_ENA (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ENA_M (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ENA_V 0x1 -#define I2C_TXFIFO_OVF_INT_ENA_S 11 - -/* I2C_NACK_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ - -#define I2C_NACK_INT_ENA (BIT(10)) -#define I2C_NACK_INT_ENA_M (BIT(10)) -#define I2C_NACK_INT_ENA_V 0x1 -#define I2C_NACK_INT_ENA_S 10 - -/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ - -#define I2C_TRANS_START_INT_ENA (BIT(9)) -#define I2C_TRANS_START_INT_ENA_M (BIT(9)) -#define I2C_TRANS_START_INT_ENA_V 0x1 -#define I2C_TRANS_START_INT_ENA_S 9 - -/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ - -#define I2C_TIME_OUT_INT_ENA (BIT(8)) -#define I2C_TIME_OUT_INT_ENA_M (BIT(8)) -#define I2C_TIME_OUT_INT_ENA_V 0x1 -#define I2C_TIME_OUT_INT_ENA_S 8 - -/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ - -#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1 -#define I2C_TRANS_COMPLETE_INT_ENA_S 7 - -/* I2C_MST_TXFIFO_UDF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ - -#define I2C_MST_TXFIFO_UDF_INT_ENA (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ENA_M (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ENA_V 0x1 -#define I2C_MST_TXFIFO_UDF_INT_ENA_S 6 - -/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ - -#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1 -#define I2C_ARBITRATION_LOST_INT_ENA_S 5 - -/* I2C_BYTE_TRANS_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -#define I2C_BYTE_TRANS_DONE_INT_ENA (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ENA_M (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ENA_V 0x1 -#define I2C_BYTE_TRANS_DONE_INT_ENA_S 4 - -/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -#define I2C_END_DETECT_INT_ENA (BIT(3)) -#define I2C_END_DETECT_INT_ENA_M (BIT(3)) -#define I2C_END_DETECT_INT_ENA_V 0x1 -#define I2C_END_DETECT_INT_ENA_S 3 - -/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ - -#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ENA_V 0x1 -#define I2C_RXFIFO_OVF_INT_ENA_S 2 - -/* I2C_TXFIFO_WM_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -#define I2C_TXFIFO_WM_INT_ENA (BIT(1)) -#define I2C_TXFIFO_WM_INT_ENA_M (BIT(1)) -#define I2C_TXFIFO_WM_INT_ENA_V 0x1 -#define I2C_TXFIFO_WM_INT_ENA_S 1 - -/* I2C_RXFIFO_WM_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -#define I2C_RXFIFO_WM_INT_ENA (BIT(0)) -#define I2C_RXFIFO_WM_INT_ENA_M (BIT(0)) -#define I2C_RXFIFO_WM_INT_ENA_V 0x1 -#define I2C_RXFIFO_WM_INT_ENA_S 0 - -#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x2C) - -/* I2C_GENERAL_CALL_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ - -#define I2C_GENERAL_CALL_INT_ST (BIT(17)) -#define I2C_GENERAL_CALL_INT_ST_M (BIT(17)) -#define I2C_GENERAL_CALL_INT_ST_V 0x1 -#define I2C_GENERAL_CALL_INT_ST_S 17 - -/* I2C_SLAVE_STRETCH_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ - -#define I2C_SLAVE_STRETCH_INT_ST (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_ST_M (BIT(16)) -#define I2C_SLAVE_STRETCH_INT_ST_V 0x1 -#define I2C_SLAVE_STRETCH_INT_ST_S 16 - -/* I2C_DET_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ - -#define I2C_DET_START_INT_ST (BIT(15)) -#define I2C_DET_START_INT_ST_M (BIT(15)) -#define I2C_DET_START_INT_ST_V 0x1 -#define I2C_DET_START_INT_ST_S 15 - -/* I2C_SCL_MAIN_ST_TO_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ - -#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ST_M (BIT(14)) -#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x1 -#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 - -/* I2C_SCL_ST_TO_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ - -#define I2C_SCL_ST_TO_INT_ST (BIT(13)) -#define I2C_SCL_ST_TO_INT_ST_M (BIT(13)) -#define I2C_SCL_ST_TO_INT_ST_V 0x1 -#define I2C_SCL_ST_TO_INT_ST_S 13 - -/* I2C_RXFIFO_UDF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ - -#define I2C_RXFIFO_UDF_INT_ST (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ST_M (BIT(12)) -#define I2C_RXFIFO_UDF_INT_ST_V 0x1 -#define I2C_RXFIFO_UDF_INT_ST_S 12 - -/* I2C_TXFIFO_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ - -#define I2C_TXFIFO_OVF_INT_ST (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ST_M (BIT(11)) -#define I2C_TXFIFO_OVF_INT_ST_V 0x1 -#define I2C_TXFIFO_OVF_INT_ST_S 11 - -/* I2C_NACK_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ - -#define I2C_NACK_INT_ST (BIT(10)) -#define I2C_NACK_INT_ST_M (BIT(10)) -#define I2C_NACK_INT_ST_V 0x1 -#define I2C_NACK_INT_ST_S 10 - -/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ - -#define I2C_TRANS_START_INT_ST (BIT(9)) -#define I2C_TRANS_START_INT_ST_M (BIT(9)) -#define I2C_TRANS_START_INT_ST_V 0x1 -#define I2C_TRANS_START_INT_ST_S 9 - -/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ - -#define I2C_TIME_OUT_INT_ST (BIT(8)) -#define I2C_TIME_OUT_INT_ST_M (BIT(8)) -#define I2C_TIME_OUT_INT_ST_V 0x1 -#define I2C_TIME_OUT_INT_ST_S 8 - -/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ - -#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7)) -#define I2C_TRANS_COMPLETE_INT_ST_V 0x1 -#define I2C_TRANS_COMPLETE_INT_ST_S 7 - -/* I2C_MST_TXFIFO_UDF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ - -#define I2C_MST_TXFIFO_UDF_INT_ST (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ST_M (BIT(6)) -#define I2C_MST_TXFIFO_UDF_INT_ST_V 0x1 -#define I2C_MST_TXFIFO_UDF_INT_ST_S 6 - -/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ - -#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5)) -#define I2C_ARBITRATION_LOST_INT_ST_V 0x1 -#define I2C_ARBITRATION_LOST_INT_ST_S 5 - -/* I2C_BYTE_TRANS_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ - -#define I2C_BYTE_TRANS_DONE_INT_ST (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ST_M (BIT(4)) -#define I2C_BYTE_TRANS_DONE_INT_ST_V 0x1 -#define I2C_BYTE_TRANS_DONE_INT_ST_S 4 - -/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ - -#define I2C_END_DETECT_INT_ST (BIT(3)) -#define I2C_END_DETECT_INT_ST_M (BIT(3)) -#define I2C_END_DETECT_INT_ST_V 0x1 -#define I2C_END_DETECT_INT_ST_S 3 - -/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ - -#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2)) -#define I2C_RXFIFO_OVF_INT_ST_V 0x1 -#define I2C_RXFIFO_OVF_INT_ST_S 2 - -/* I2C_TXFIFO_WM_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ - -#define I2C_TXFIFO_WM_INT_ST (BIT(1)) -#define I2C_TXFIFO_WM_INT_ST_M (BIT(1)) -#define I2C_TXFIFO_WM_INT_ST_V 0x1 -#define I2C_TXFIFO_WM_INT_ST_S 1 - -/* I2C_RXFIFO_WM_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ - -#define I2C_RXFIFO_WM_INT_ST (BIT(0)) -#define I2C_RXFIFO_WM_INT_ST_M (BIT(0)) -#define I2C_RXFIFO_WM_INT_ST_V 0x1 -#define I2C_RXFIFO_WM_INT_ST_S 0 - -#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x30) - -/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ - -#define I2C_SDA_HOLD_TIME 0x000001FF -#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S)) -#define I2C_SDA_HOLD_TIME_V 0x1FF -#define I2C_SDA_HOLD_TIME_S 0 - -#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x34) - -/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ - -#define I2C_SDA_SAMPLE_TIME 0x000001FF -#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S)) -#define I2C_SDA_SAMPLE_TIME_V 0x1FF -#define I2C_SDA_SAMPLE_TIME_S 0 - -#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x38) - -/* I2C_SCL_WAIT_HIGH_PERIOD : R/W ;bitpos:[15:9] ;default: 7'b0 ; */ - -#define I2C_SCL_WAIT_HIGH_PERIOD 0x0000007F -#define I2C_SCL_WAIT_HIGH_PERIOD_M ((I2C_SCL_WAIT_HIGH_PERIOD_V)<<(I2C_SCL_WAIT_HIGH_PERIOD_S)) -#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x7F -#define I2C_SCL_WAIT_HIGH_PERIOD_S 9 - -/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[8:0] ;default: 9'b0 ; */ - -#define I2C_SCL_HIGH_PERIOD 0x000001FF -#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S)) -#define I2C_SCL_HIGH_PERIOD_V 0x1FF -#define I2C_SCL_HIGH_PERIOD_S 0 - -#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x40) - -/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ - -#define I2C_SCL_START_HOLD_TIME 0x000001FF -#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S)) -#define I2C_SCL_START_HOLD_TIME_V 0x1FF -#define I2C_SCL_START_HOLD_TIME_S 0 - -#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x44) - -/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ - -#define I2C_SCL_RSTART_SETUP_TIME 0x000001FF -#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S)) -#define I2C_SCL_RSTART_SETUP_TIME_V 0x1FF -#define I2C_SCL_RSTART_SETUP_TIME_S 0 - -#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x48) - -/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ - -#define I2C_SCL_STOP_HOLD_TIME 0x000001FF -#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S)) -#define I2C_SCL_STOP_HOLD_TIME_V 0x1FF -#define I2C_SCL_STOP_HOLD_TIME_S 0 - -#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x4C) - -/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[8:0] ;default: 9'b1000 ; */ - -#define I2C_SCL_STOP_SETUP_TIME 0x000001FF -#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S)) -#define I2C_SCL_STOP_SETUP_TIME_V 0x1FF -#define I2C_SCL_STOP_SETUP_TIME_S 0 - -#define I2C_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x50) - -/* I2C_SDA_FILTER_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ - -#define I2C_SDA_FILTER_EN (BIT(9)) -#define I2C_SDA_FILTER_EN_M (BIT(9)) -#define I2C_SDA_FILTER_EN_V 0x1 -#define I2C_SDA_FILTER_EN_S 9 - -/* I2C_SCL_FILTER_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */ - -#define I2C_SCL_FILTER_EN (BIT(8)) -#define I2C_SCL_FILTER_EN_M (BIT(8)) -#define I2C_SCL_FILTER_EN_V 0x1 -#define I2C_SCL_FILTER_EN_S 8 - -/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[7:4] ;default: 4'b0 ; */ - -#define I2C_SDA_FILTER_THRES 0x0000000F -#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S)) -#define I2C_SDA_FILTER_THRES_V 0xF -#define I2C_SDA_FILTER_THRES_S 4 - -/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ - -#define I2C_SCL_FILTER_THRES 0x0000000F -#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S)) -#define I2C_SCL_FILTER_THRES_V 0xF -#define I2C_SCL_FILTER_THRES_S 0 - -#define I2C_CLK_CONF_REG(i) (REG_I2C_BASE(i) + 0x54) - -/* I2C_SCLK_ACTIVE : R/W ;bitpos:[21] ;default: 1'b1 ; */ - -#define I2C_SCLK_ACTIVE (BIT(21)) -#define I2C_SCLK_ACTIVE_M (BIT(21)) -#define I2C_SCLK_ACTIVE_V 0x1 -#define I2C_SCLK_ACTIVE_S 21 - -/* I2C_SCLK_SEL : R/W ;bitpos:[20] ;default: 1'b0 ; */ - -#define I2C_SCLK_SEL (BIT(20)) -#define I2C_SCLK_SEL_M (BIT(20)) -#define I2C_SCLK_SEL_V 0x1 -#define I2C_SCLK_SEL_S 20 - -/* I2C_SCLK_DIV_B : R/W ;bitpos:[19:14] ;default: 6'b0 ; */ - -#define I2C_SCLK_DIV_B 0x0000003F -#define I2C_SCLK_DIV_B_M ((I2C_SCLK_DIV_B_V)<<(I2C_SCLK_DIV_B_S)) -#define I2C_SCLK_DIV_B_V 0x3F -#define I2C_SCLK_DIV_B_S 14 - -/* I2C_SCLK_DIV_A : R/W ;bitpos:[13:8] ;default: 6'b0 ; */ - -#define I2C_SCLK_DIV_A 0x0000003F -#define I2C_SCLK_DIV_A_M ((I2C_SCLK_DIV_A_V)<<(I2C_SCLK_DIV_A_S)) -#define I2C_SCLK_DIV_A_V 0x3F -#define I2C_SCLK_DIV_A_S 8 - -/* I2C_SCLK_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ - -#define I2C_SCLK_DIV_NUM 0x000000FF -#define I2C_SCLK_DIV_NUM_M ((I2C_SCLK_DIV_NUM_V)<<(I2C_SCLK_DIV_NUM_S)) -#define I2C_SCLK_DIV_NUM_V 0xFF -#define I2C_SCLK_DIV_NUM_S 0 - -#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x58) - -/* I2C_COMMAND0_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ - -#define I2C_COMMAND0_DONE (BIT(31)) -#define I2C_COMMAND0_DONE_M (BIT(31)) -#define I2C_COMMAND0_DONE_V 0x1 -#define I2C_COMMAND0_DONE_S 31 - -/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ - -#define I2C_COMMAND0 0x00003FFF -#define I2C_COMMAND0_M ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S)) -#define I2C_COMMAND0_V 0x3FFF -#define I2C_COMMAND0_S 0 - -#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x5C) - -/* I2C_COMMAND1_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ - -#define I2C_COMMAND1_DONE (BIT(31)) -#define I2C_COMMAND1_DONE_M (BIT(31)) -#define I2C_COMMAND1_DONE_V 0x1 -#define I2C_COMMAND1_DONE_S 31 - -/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ - -#define I2C_COMMAND1 0x00003FFF -#define I2C_COMMAND1_M ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S)) -#define I2C_COMMAND1_V 0x3FFF -#define I2C_COMMAND1_S 0 - -#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x60) - -/* I2C_COMMAND2_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ - -#define I2C_COMMAND2_DONE (BIT(31)) -#define I2C_COMMAND2_DONE_M (BIT(31)) -#define I2C_COMMAND2_DONE_V 0x1 -#define I2C_COMMAND2_DONE_S 31 - -/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ - -#define I2C_COMMAND2 0x00003FFF -#define I2C_COMMAND2_M ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S)) -#define I2C_COMMAND2_V 0x3FFF -#define I2C_COMMAND2_S 0 - -#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x64) - -/* I2C_COMMAND3_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ - -#define I2C_COMMAND3_DONE (BIT(31)) -#define I2C_COMMAND3_DONE_M (BIT(31)) -#define I2C_COMMAND3_DONE_V 0x1 -#define I2C_COMMAND3_DONE_S 31 - -/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ - -#define I2C_COMMAND3 0x00003FFF -#define I2C_COMMAND3_M ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S)) -#define I2C_COMMAND3_V 0x3FFF -#define I2C_COMMAND3_S 0 - -#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x68) - -/* I2C_COMMAND4_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ - -#define I2C_COMMAND4_DONE (BIT(31)) -#define I2C_COMMAND4_DONE_M (BIT(31)) -#define I2C_COMMAND4_DONE_V 0x1 -#define I2C_COMMAND4_DONE_S 31 - -/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ - -#define I2C_COMMAND4 0x00003FFF -#define I2C_COMMAND4_M ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S)) -#define I2C_COMMAND4_V 0x3FFF -#define I2C_COMMAND4_S 0 - -#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x6C) - -/* I2C_COMMAND5_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ - -#define I2C_COMMAND5_DONE (BIT(31)) -#define I2C_COMMAND5_DONE_M (BIT(31)) -#define I2C_COMMAND5_DONE_V 0x1 -#define I2C_COMMAND5_DONE_S 31 - -/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ - -#define I2C_COMMAND5 0x00003FFF -#define I2C_COMMAND5_M ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S)) -#define I2C_COMMAND5_V 0x3FFF -#define I2C_COMMAND5_S 0 - -#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x70) - -/* I2C_COMMAND6_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ - -#define I2C_COMMAND6_DONE (BIT(31)) -#define I2C_COMMAND6_DONE_M (BIT(31)) -#define I2C_COMMAND6_DONE_V 0x1 -#define I2C_COMMAND6_DONE_S 31 - -/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ - -#define I2C_COMMAND6 0x00003FFF -#define I2C_COMMAND6_M ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S)) -#define I2C_COMMAND6_V 0x3FFF -#define I2C_COMMAND6_S 0 - -#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x74) - -/* I2C_COMMAND7_DONE : R/W/SS ;bitpos:[31] ;default: 1'b0 ; */ - -#define I2C_COMMAND7_DONE (BIT(31)) -#define I2C_COMMAND7_DONE_M (BIT(31)) -#define I2C_COMMAND7_DONE_V 0x1 -#define I2C_COMMAND7_DONE_S 31 - -/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ - -#define I2C_COMMAND7 0x00003FFF -#define I2C_COMMAND7_M ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S)) -#define I2C_COMMAND7_V 0x3FFF -#define I2C_COMMAND7_S 0 - -#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x78) - -/* I2C_SCL_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ - -#define I2C_SCL_ST_TO_REG 0x0000001F -#define I2C_SCL_ST_TO_REG_M ((I2C_SCL_ST_TO_REG_V)<<(I2C_SCL_ST_TO_REG_S)) -#define I2C_SCL_ST_TO_REG_V 0x1F -#define I2C_SCL_ST_TO_REG_S 0 - -#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x7C) - -/* I2C_SCL_MAIN_ST_TO_REG : R/W ;bitpos:[4:0] ;default: 5'h10 ; */ - -#define I2C_SCL_MAIN_ST_TO_REG 0x0000001F -#define I2C_SCL_MAIN_ST_TO_REG_M ((I2C_SCL_MAIN_ST_TO_REG_V)<<(I2C_SCL_MAIN_ST_TO_REG_S)) -#define I2C_SCL_MAIN_ST_TO_REG_V 0x1F -#define I2C_SCL_MAIN_ST_TO_REG_S 0 - -#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x80) - -/* I2C_SDA_PD_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ - -#define I2C_SDA_PD_EN (BIT(7)) -#define I2C_SDA_PD_EN_M (BIT(7)) -#define I2C_SDA_PD_EN_V 0x1 -#define I2C_SDA_PD_EN_S 7 - -/* I2C_SCL_PD_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ - -#define I2C_SCL_PD_EN (BIT(6)) -#define I2C_SCL_PD_EN_M (BIT(6)) -#define I2C_SCL_PD_EN_V 0x1 -#define I2C_SCL_PD_EN_S 6 - -/* I2C_SCL_RST_SLV_NUM : R/W ;bitpos:[5:1] ;default: 5'b0 ; */ - -#define I2C_SCL_RST_SLV_NUM 0x0000001F -#define I2C_SCL_RST_SLV_NUM_M ((I2C_SCL_RST_SLV_NUM_V)<<(I2C_SCL_RST_SLV_NUM_S)) -#define I2C_SCL_RST_SLV_NUM_V 0x1F -#define I2C_SCL_RST_SLV_NUM_S 1 - -/* I2C_SCL_RST_SLV_EN : R/W/SC ;bitpos:[0] ;default: 1'b0 ; */ - -#define I2C_SCL_RST_SLV_EN (BIT(0)) -#define I2C_SCL_RST_SLV_EN_M (BIT(0)) -#define I2C_SCL_RST_SLV_EN_V 0x1 -#define I2C_SCL_RST_SLV_EN_S 0 - -#define I2C_SCL_STRETCH_CONF_REG(i) (REG_I2C_BASE(i) + 0x84) - -/* I2C_SLAVE_BYTE_ACK_LVL : R/W ;bitpos:[13] ;default: 1'b0 ; */ - -#define I2C_SLAVE_BYTE_ACK_LVL (BIT(13)) -#define I2C_SLAVE_BYTE_ACK_LVL_M (BIT(13)) -#define I2C_SLAVE_BYTE_ACK_LVL_V 0x1 -#define I2C_SLAVE_BYTE_ACK_LVL_S 13 - -/* I2C_SLAVE_BYTE_ACK_CTL_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ - -#define I2C_SLAVE_BYTE_ACK_CTL_EN (BIT(12)) -#define I2C_SLAVE_BYTE_ACK_CTL_EN_M (BIT(12)) -#define I2C_SLAVE_BYTE_ACK_CTL_EN_V 0x1 -#define I2C_SLAVE_BYTE_ACK_CTL_EN_S 12 - -/* I2C_SLAVE_SCL_STRETCH_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ - -#define I2C_SLAVE_SCL_STRETCH_CLR (BIT(11)) -#define I2C_SLAVE_SCL_STRETCH_CLR_M (BIT(11)) -#define I2C_SLAVE_SCL_STRETCH_CLR_V 0x1 -#define I2C_SLAVE_SCL_STRETCH_CLR_S 11 - -/* I2C_SLAVE_SCL_STRETCH_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ - -#define I2C_SLAVE_SCL_STRETCH_EN (BIT(10)) -#define I2C_SLAVE_SCL_STRETCH_EN_M (BIT(10)) -#define I2C_SLAVE_SCL_STRETCH_EN_V 0x1 -#define I2C_SLAVE_SCL_STRETCH_EN_S 10 - -/* I2C_STRETCH_PROTECT_NUM : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ - -#define I2C_STRETCH_PROTECT_NUM 0x000003FF -#define I2C_STRETCH_PROTECT_NUM_M ((I2C_STRETCH_PROTECT_NUM_V)<<(I2C_STRETCH_PROTECT_NUM_S)) -#define I2C_STRETCH_PROTECT_NUM_V 0x3FF -#define I2C_STRETCH_PROTECT_NUM_S 0 - -#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0xF8) - -/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h20070201 ; */ - -#define I2C_DATE 0xFFFFFFFF -#define I2C_DATE_M ((I2C_DATE_V)<<(I2C_DATE_S)) -#define I2C_DATE_V 0xFFFFFFFF -#define I2C_DATE_S 0 - -#define I2C_TXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x100) - -#define I2C_RXFIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x180) - -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_I2C_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_ledc.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_ledc.h deleted file mode 100644 index 6b8846b75be75..0000000000000 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_ledc.h +++ /dev/null @@ -1,2742 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_ledc.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_LEDC_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_LEDC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32c3_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* LEDC_CH0_CONF0_REG register - * Configuration register 0 for channel 0 - */ - -#define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0) - -/* LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0; - * This field is used to select one of timers for channel 0. - * - * 0: select timer0 - * - * 1: select timer1 - * - * 2: select timer2 - * - * 3: select timer3 - */ - -#define LEDC_TIMER_SEL_CH0 0x00000003 -#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S) -#define LEDC_TIMER_SEL_CH0_V 0x00000003 -#define LEDC_TIMER_SEL_CH0_S 0 - -/* LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0; - * Set this bit to enable signal output on channel 0. - */ - -#define LEDC_SIG_OUT_EN_CH0 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S) -#define LEDC_SIG_OUT_EN_CH0_V 0x00000001 -#define LEDC_SIG_OUT_EN_CH0_S 2 - -/* LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0; - * This bit is used to control the output value when channel 0 is inactive. - */ - -#define LEDC_IDLE_LV_CH0 (BIT(3)) -#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S) -#define LEDC_IDLE_LV_CH0_V 0x00000001 -#define LEDC_IDLE_LV_CH0_S 3 - -/* LEDC_PARA_UP_CH0 : WO; bitpos: [4]; default: 0; - * This bit is used to update register LEDC_CH0_HPOINT and LEDC_CH0_DUTY for - * channel 0. - */ - -#define LEDC_PARA_UP_CH0 (BIT(4)) -#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S) -#define LEDC_PARA_UP_CH0_V 0x00000001 -#define LEDC_PARA_UP_CH0_S 4 - -/* LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0; - * This register is used to configure the maximum times of overflow minus 1. - * - * The LEDC_OVF_CNT_CH0_INT interrupt will be triggered when channel 0 - * overflows for (LEDC_OVF_NUM_CH0 + 1) times. - */ - -#define LEDC_OVF_NUM_CH0 0x000003FF -#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S) -#define LEDC_OVF_NUM_CH0_V 0x000003FF -#define LEDC_OVF_NUM_CH0_S 5 - -/* LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0; - * This bit is used to enable the ovf_cnt of channel 0. - */ - -#define LEDC_OVF_CNT_EN_CH0 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S) -#define LEDC_OVF_CNT_EN_CH0_V 0x00000001 -#define LEDC_OVF_CNT_EN_CH0_S 15 - -/* LEDC_OVF_CNT_RESET_CH0 : WO; bitpos: [16]; default: 0; - * Set this bit to reset the ovf_cnt of channel 0. - */ - -#define LEDC_OVF_CNT_RESET_CH0 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S) -#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001 -#define LEDC_OVF_CNT_RESET_CH0_S 16 - -/* LEDC_OVF_CNT_RESET_ST_CH0 : RO; bitpos: [17]; default: 0; - * This is the status bit of LEDC_OVF_CNT_RESET_CH0. - */ - -#define LEDC_OVF_CNT_RESET_ST_CH0 (BIT(17)) -#define LEDC_OVF_CNT_RESET_ST_CH0_M (LEDC_OVF_CNT_RESET_ST_CH0_V << LEDC_OVF_CNT_RESET_ST_CH0_S) -#define LEDC_OVF_CNT_RESET_ST_CH0_V 0x00000001 -#define LEDC_OVF_CNT_RESET_ST_CH0_S 17 - -/* LEDC_CH0_HPOINT_REG register - * High point register for channel 0 - */ - -#define LEDC_CH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x4) - -/* LEDC_HPOINT_CH0 : R/W; bitpos: [13:0]; default: 0; - * The output value changes to high when the selected timers has reached the - * value specified by this register. - */ - -#define LEDC_HPOINT_CH0 0x00003FFF -#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S) -#define LEDC_HPOINT_CH0_V 0x00003FFF -#define LEDC_HPOINT_CH0_S 0 - -/* LEDC_CH0_DUTY_REG register - * Initial duty cycle for channel 0 - */ - -#define LEDC_CH0_DUTY_REG (DR_REG_LEDC_BASE + 0x8) - -/* LEDC_DUTY_CH0 : R/W; bitpos: [18:0]; default: 0; - * This register is used to change the output duty by controlling the Lpoint. - * - * The output value turns to low when the selected timers has reached the - * Lpoint. - */ - -#define LEDC_DUTY_CH0 0x0007FFFF -#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S) -#define LEDC_DUTY_CH0_V 0x0007FFFF -#define LEDC_DUTY_CH0_S 0 - -/* LEDC_CH0_CONF1_REG register - * Configuration register 1 for channel 0 - */ - -#define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc) - -/* LEDC_DUTY_SCALE_CH0 : R/W; bitpos: [9:0]; default: 0; - * This register is used to configure the changing step scale of duty on - * channel 0. - */ - -#define LEDC_DUTY_SCALE_CH0 0x000003FF -#define LEDC_DUTY_SCALE_CH0_M (LEDC_DUTY_SCALE_CH0_V << LEDC_DUTY_SCALE_CH0_S) -#define LEDC_DUTY_SCALE_CH0_V 0x000003FF -#define LEDC_DUTY_SCALE_CH0_S 0 - -/* LEDC_DUTY_CYCLE_CH0 : R/W; bitpos: [19:10]; default: 0; - * The duty will change every LEDC_DUTY_CYCLE_CH0 on channel 0. - */ - -#define LEDC_DUTY_CYCLE_CH0 0x000003FF -#define LEDC_DUTY_CYCLE_CH0_M (LEDC_DUTY_CYCLE_CH0_V << LEDC_DUTY_CYCLE_CH0_S) -#define LEDC_DUTY_CYCLE_CH0_V 0x000003FF -#define LEDC_DUTY_CYCLE_CH0_S 10 - -/* LEDC_DUTY_NUM_CH0 : R/W; bitpos: [29:20]; default: 0; - * This register is used to control the number of times the duty cycle will - * be changed. - */ - -#define LEDC_DUTY_NUM_CH0 0x000003FF -#define LEDC_DUTY_NUM_CH0_M (LEDC_DUTY_NUM_CH0_V << LEDC_DUTY_NUM_CH0_S) -#define LEDC_DUTY_NUM_CH0_V 0x000003FF -#define LEDC_DUTY_NUM_CH0_S 20 - -/* LEDC_DUTY_INC_CH0 : R/W; bitpos: [30]; default: 1; - * This register is used to increase or decrease the duty of output signal - * on channel 0. 1: Increase;0: Decrease. - */ - -#define LEDC_DUTY_INC_CH0 (BIT(30)) -#define LEDC_DUTY_INC_CH0_M (LEDC_DUTY_INC_CH0_V << LEDC_DUTY_INC_CH0_S) -#define LEDC_DUTY_INC_CH0_V 0x00000001 -#define LEDC_DUTY_INC_CH0_S 30 - -/* LEDC_DUTY_START_CH0 : R/W; bitpos: [31]; default: 0; - * Other configured fields in LEDC_CH0_CONF1_REG will start to take effect - * when this bit is set to 1. - */ - -#define LEDC_DUTY_START_CH0 (BIT(31)) -#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S) -#define LEDC_DUTY_START_CH0_V 0x00000001 -#define LEDC_DUTY_START_CH0_S 31 - -/* LEDC_CH0_DUTY_R_REG register - * Current duty cycle for channel 0 - */ - -#define LEDC_CH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x10) - -/* LEDC_DUTY_R_CH0 : RO; bitpos: [18:0]; default: 0; - * This register stores the current duty of output signal on channel 0. - */ - -#define LEDC_DUTY_R_CH0 0x0007FFFF -#define LEDC_DUTY_R_CH0_M (LEDC_DUTY_R_CH0_V << LEDC_DUTY_R_CH0_S) -#define LEDC_DUTY_R_CH0_V 0x0007FFFF -#define LEDC_DUTY_R_CH0_S 0 - -/* LEDC_CH1_CONF0_REG register - * Configuration register 0 for channel 1 - */ - -#define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14) - -/* LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0; - * This field is used to select one of timers for channel 1. - * - * 0: select timer0 - * - * 1: select timer1 - * - * 2: select timer2 - * - * 3: select timer3 - */ - -#define LEDC_TIMER_SEL_CH1 0x00000003 -#define LEDC_TIMER_SEL_CH1_M (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S) -#define LEDC_TIMER_SEL_CH1_V 0x00000003 -#define LEDC_TIMER_SEL_CH1_S 0 - -/* LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0; - * Set this bit to enable signal output on channel 1. - */ - -#define LEDC_SIG_OUT_EN_CH1 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH1_M (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S) -#define LEDC_SIG_OUT_EN_CH1_V 0x00000001 -#define LEDC_SIG_OUT_EN_CH1_S 2 - -/* LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0; - * This bit is used to control the output value when channel 1 is inactive. - */ - -#define LEDC_IDLE_LV_CH1 (BIT(3)) -#define LEDC_IDLE_LV_CH1_M (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S) -#define LEDC_IDLE_LV_CH1_V 0x00000001 -#define LEDC_IDLE_LV_CH1_S 3 - -/* LEDC_PARA_UP_CH1 : WO; bitpos: [4]; default: 0; - * This bit is used to update register LEDC_CH1_HPOINT and LEDC_CH1_DUTY for - * channel 1. - */ - -#define LEDC_PARA_UP_CH1 (BIT(4)) -#define LEDC_PARA_UP_CH1_M (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S) -#define LEDC_PARA_UP_CH1_V 0x00000001 -#define LEDC_PARA_UP_CH1_S 4 - -/* LEDC_OVF_NUM_CH1 : R/W; bitpos: [14:5]; default: 0; - * This register is used to configure the maximum times of overflow minus 1. - * - * The LEDC_OVF_CNT_CH1_INT interrupt will be triggered when channel 1 - * overflows for (LEDC_OVF_NUM_CH1 + 1) times. - */ - -#define LEDC_OVF_NUM_CH1 0x000003FF -#define LEDC_OVF_NUM_CH1_M (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S) -#define LEDC_OVF_NUM_CH1_V 0x000003FF -#define LEDC_OVF_NUM_CH1_S 5 - -/* LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0; - * This bit is used to enable the ovf_cnt of channel 1. - */ - -#define LEDC_OVF_CNT_EN_CH1 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH1_M (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S) -#define LEDC_OVF_CNT_EN_CH1_V 0x00000001 -#define LEDC_OVF_CNT_EN_CH1_S 15 - -/* LEDC_OVF_CNT_RESET_CH1 : WO; bitpos: [16]; default: 0; - * Set this bit to reset the ovf_cnt of channel 1. - */ - -#define LEDC_OVF_CNT_RESET_CH1 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH1_M (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S) -#define LEDC_OVF_CNT_RESET_CH1_V 0x00000001 -#define LEDC_OVF_CNT_RESET_CH1_S 16 - -/* LEDC_OVF_CNT_RESET_ST_CH1 : RO; bitpos: [17]; default: 0; - * This is the status bit of LEDC_OVF_CNT_RESET_CH1. - */ - -#define LEDC_OVF_CNT_RESET_ST_CH1 (BIT(17)) -#define LEDC_OVF_CNT_RESET_ST_CH1_M (LEDC_OVF_CNT_RESET_ST_CH1_V << LEDC_OVF_CNT_RESET_ST_CH1_S) -#define LEDC_OVF_CNT_RESET_ST_CH1_V 0x00000001 -#define LEDC_OVF_CNT_RESET_ST_CH1_S 17 - -/* LEDC_CH1_HPOINT_REG register - * High point register for channel 1 - */ - -#define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18) - -/* LEDC_HPOINT_CH1 : R/W; bitpos: [13:0]; default: 0; - * The output value changes to high when the selected timers has reached the - * value specified by this register. - */ - -#define LEDC_HPOINT_CH1 0x00003FFF -#define LEDC_HPOINT_CH1_M (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S) -#define LEDC_HPOINT_CH1_V 0x00003FFF -#define LEDC_HPOINT_CH1_S 0 - -/* LEDC_CH1_DUTY_REG register - * Initial duty cycle for channel 1 - */ - -#define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c) - -/* LEDC_DUTY_CH1 : R/W; bitpos: [18:0]; default: 0; - * This register is used to change the output duty by controlling the Lpoint. - * - * The output value turns to low when the selected timers has reached the - * Lpoint. - */ - -#define LEDC_DUTY_CH1 0x0007FFFF -#define LEDC_DUTY_CH1_M (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S) -#define LEDC_DUTY_CH1_V 0x0007FFFF -#define LEDC_DUTY_CH1_S 0 - -/* LEDC_CH1_CONF1_REG register - * Configuration register 1 for channel 1 - */ - -#define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20) - -/* LEDC_DUTY_SCALE_CH1 : R/W; bitpos: [9:0]; default: 0; - * This register is used to configure the changing step scale of duty on - * channel 1. - */ - -#define LEDC_DUTY_SCALE_CH1 0x000003FF -#define LEDC_DUTY_SCALE_CH1_M (LEDC_DUTY_SCALE_CH1_V << LEDC_DUTY_SCALE_CH1_S) -#define LEDC_DUTY_SCALE_CH1_V 0x000003FF -#define LEDC_DUTY_SCALE_CH1_S 0 - -/* LEDC_DUTY_CYCLE_CH1 : R/W; bitpos: [19:10]; default: 0; - * The duty will change every LEDC_DUTY_CYCLE_CH1 on channel 1. - */ - -#define LEDC_DUTY_CYCLE_CH1 0x000003FF -#define LEDC_DUTY_CYCLE_CH1_M (LEDC_DUTY_CYCLE_CH1_V << LEDC_DUTY_CYCLE_CH1_S) -#define LEDC_DUTY_CYCLE_CH1_V 0x000003FF -#define LEDC_DUTY_CYCLE_CH1_S 10 - -/* LEDC_DUTY_NUM_CH1 : R/W; bitpos: [29:20]; default: 0; - * This register is used to control the number of times the duty cycle will - * be changed. - */ - -#define LEDC_DUTY_NUM_CH1 0x000003FF -#define LEDC_DUTY_NUM_CH1_M (LEDC_DUTY_NUM_CH1_V << LEDC_DUTY_NUM_CH1_S) -#define LEDC_DUTY_NUM_CH1_V 0x000003FF -#define LEDC_DUTY_NUM_CH1_S 20 - -/* LEDC_DUTY_INC_CH1 : R/W; bitpos: [30]; default: 1; - * This register is used to increase or decrease the duty of output signal - * on channel 1. 1: Increase;0: Decrease. - */ - -#define LEDC_DUTY_INC_CH1 (BIT(30)) -#define LEDC_DUTY_INC_CH1_M (LEDC_DUTY_INC_CH1_V << LEDC_DUTY_INC_CH1_S) -#define LEDC_DUTY_INC_CH1_V 0x00000001 -#define LEDC_DUTY_INC_CH1_S 30 - -/* LEDC_DUTY_START_CH1 : R/W; bitpos: [31]; default: 0; - * Other configured fields in LEDC_CH1_CONF1_REG will start to take effect - * when this bit is set to 1. - */ - -#define LEDC_DUTY_START_CH1 (BIT(31)) -#define LEDC_DUTY_START_CH1_M (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S) -#define LEDC_DUTY_START_CH1_V 0x00000001 -#define LEDC_DUTY_START_CH1_S 31 - -/* LEDC_CH1_DUTY_R_REG register - * Current duty cycle for channel 1 - */ - -#define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24) - -/* LEDC_DUTY_R_CH1 : RO; bitpos: [18:0]; default: 0; - * This register stores the current duty of output signal on channel 1. - */ - -#define LEDC_DUTY_R_CH1 0x0007FFFF -#define LEDC_DUTY_R_CH1_M (LEDC_DUTY_R_CH1_V << LEDC_DUTY_R_CH1_S) -#define LEDC_DUTY_R_CH1_V 0x0007FFFF -#define LEDC_DUTY_R_CH1_S 0 - -/* LEDC_CH2_CONF0_REG register - * Configuration register 0 for channel 2 - */ - -#define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28) - -/* LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0; - * This field is used to select one of timers for channel 2. - * - * 0: select timer0 - * - * 1: select timer1 - * - * 2: select timer2 - * - * 3: select timer3 - */ - -#define LEDC_TIMER_SEL_CH2 0x00000003 -#define LEDC_TIMER_SEL_CH2_M (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S) -#define LEDC_TIMER_SEL_CH2_V 0x00000003 -#define LEDC_TIMER_SEL_CH2_S 0 - -/* LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0; - * Set this bit to enable signal output on channel 2. - */ - -#define LEDC_SIG_OUT_EN_CH2 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH2_M (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S) -#define LEDC_SIG_OUT_EN_CH2_V 0x00000001 -#define LEDC_SIG_OUT_EN_CH2_S 2 - -/* LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0; - * This bit is used to control the output value when channel 2 is inactive. - */ - -#define LEDC_IDLE_LV_CH2 (BIT(3)) -#define LEDC_IDLE_LV_CH2_M (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S) -#define LEDC_IDLE_LV_CH2_V 0x00000001 -#define LEDC_IDLE_LV_CH2_S 3 - -/* LEDC_PARA_UP_CH2 : WO; bitpos: [4]; default: 0; - * This bit is used to update register LEDC_CH2_HPOINT and LEDC_CH2_DUTY for - * channel 2. - */ - -#define LEDC_PARA_UP_CH2 (BIT(4)) -#define LEDC_PARA_UP_CH2_M (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S) -#define LEDC_PARA_UP_CH2_V 0x00000001 -#define LEDC_PARA_UP_CH2_S 4 - -/* LEDC_OVF_NUM_CH2 : R/W; bitpos: [14:5]; default: 0; - * This register is used to configure the maximum times of overflow minus 1. - * - * The LEDC_OVF_CNT_CH2_INT interrupt will be triggered when channel 2 - * overflows for (LEDC_OVF_NUM_CH2 + 1) times. - */ - -#define LEDC_OVF_NUM_CH2 0x000003FF -#define LEDC_OVF_NUM_CH2_M (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S) -#define LEDC_OVF_NUM_CH2_V 0x000003FF -#define LEDC_OVF_NUM_CH2_S 5 - -/* LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0; - * This bit is used to enable the ovf_cnt of channel 2. - */ - -#define LEDC_OVF_CNT_EN_CH2 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH2_M (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S) -#define LEDC_OVF_CNT_EN_CH2_V 0x00000001 -#define LEDC_OVF_CNT_EN_CH2_S 15 - -/* LEDC_OVF_CNT_RESET_CH2 : WO; bitpos: [16]; default: 0; - * Set this bit to reset the ovf_cnt of channel 2. - */ - -#define LEDC_OVF_CNT_RESET_CH2 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH2_M (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S) -#define LEDC_OVF_CNT_RESET_CH2_V 0x00000001 -#define LEDC_OVF_CNT_RESET_CH2_S 16 - -/* LEDC_OVF_CNT_RESET_ST_CH2 : RO; bitpos: [17]; default: 0; - * This is the status bit of LEDC_OVF_CNT_RESET_CH2. - */ - -#define LEDC_OVF_CNT_RESET_ST_CH2 (BIT(17)) -#define LEDC_OVF_CNT_RESET_ST_CH2_M (LEDC_OVF_CNT_RESET_ST_CH2_V << LEDC_OVF_CNT_RESET_ST_CH2_S) -#define LEDC_OVF_CNT_RESET_ST_CH2_V 0x00000001 -#define LEDC_OVF_CNT_RESET_ST_CH2_S 17 - -/* LEDC_CH2_HPOINT_REG register - * High point register for channel 2 - */ - -#define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c) - -/* LEDC_HPOINT_CH2 : R/W; bitpos: [13:0]; default: 0; - * The output value changes to high when the selected timers has reached the - * value specified by this register. - */ - -#define LEDC_HPOINT_CH2 0x00003FFF -#define LEDC_HPOINT_CH2_M (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S) -#define LEDC_HPOINT_CH2_V 0x00003FFF -#define LEDC_HPOINT_CH2_S 0 - -/* LEDC_CH2_DUTY_REG register - * Initial duty cycle for channel 2 - */ - -#define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30) - -/* LEDC_DUTY_CH2 : R/W; bitpos: [18:0]; default: 0; - * This register is used to change the output duty by controlling the Lpoint. - * - * The output value turns to low when the selected timers has reached the - * Lpoint. - */ - -#define LEDC_DUTY_CH2 0x0007FFFF -#define LEDC_DUTY_CH2_M (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S) -#define LEDC_DUTY_CH2_V 0x0007FFFF -#define LEDC_DUTY_CH2_S 0 - -/* LEDC_CH2_CONF1_REG register - * Configuration register 1 for channel 2 - */ - -#define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34) - -/* LEDC_DUTY_SCALE_CH2 : R/W; bitpos: [9:0]; default: 0; - * This register is used to configure the changing step scale of duty on - * channel 2. - */ - -#define LEDC_DUTY_SCALE_CH2 0x000003FF -#define LEDC_DUTY_SCALE_CH2_M (LEDC_DUTY_SCALE_CH2_V << LEDC_DUTY_SCALE_CH2_S) -#define LEDC_DUTY_SCALE_CH2_V 0x000003FF -#define LEDC_DUTY_SCALE_CH2_S 0 - -/* LEDC_DUTY_CYCLE_CH2 : R/W; bitpos: [19:10]; default: 0; - * The duty will change every LEDC_DUTY_CYCLE_CH2 on channel 2. - */ - -#define LEDC_DUTY_CYCLE_CH2 0x000003FF -#define LEDC_DUTY_CYCLE_CH2_M (LEDC_DUTY_CYCLE_CH2_V << LEDC_DUTY_CYCLE_CH2_S) -#define LEDC_DUTY_CYCLE_CH2_V 0x000003FF -#define LEDC_DUTY_CYCLE_CH2_S 10 - -/* LEDC_DUTY_NUM_CH2 : R/W; bitpos: [29:20]; default: 0; - * This register is used to control the number of times the duty cycle will - * be changed. - */ - -#define LEDC_DUTY_NUM_CH2 0x000003FF -#define LEDC_DUTY_NUM_CH2_M (LEDC_DUTY_NUM_CH2_V << LEDC_DUTY_NUM_CH2_S) -#define LEDC_DUTY_NUM_CH2_V 0x000003FF -#define LEDC_DUTY_NUM_CH2_S 20 - -/* LEDC_DUTY_INC_CH2 : R/W; bitpos: [30]; default: 1; - * This register is used to increase or decrease the duty of output signal - * on channel 2. 1: Increase;0: Decrease. - */ - -#define LEDC_DUTY_INC_CH2 (BIT(30)) -#define LEDC_DUTY_INC_CH2_M (LEDC_DUTY_INC_CH2_V << LEDC_DUTY_INC_CH2_S) -#define LEDC_DUTY_INC_CH2_V 0x00000001 -#define LEDC_DUTY_INC_CH2_S 30 - -/* LEDC_DUTY_START_CH2 : R/W; bitpos: [31]; default: 0; - * Other configured fields in LEDC_CH2_CONF1_REG will start to take effect - * when this bit is set to 1. - */ - -#define LEDC_DUTY_START_CH2 (BIT(31)) -#define LEDC_DUTY_START_CH2_M (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S) -#define LEDC_DUTY_START_CH2_V 0x00000001 -#define LEDC_DUTY_START_CH2_S 31 - -/* LEDC_CH2_DUTY_R_REG register - * Current duty cycle for channel 2 - */ - -#define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38) - -/* LEDC_DUTY_R_CH2 : RO; bitpos: [18:0]; default: 0; - * This register stores the current duty of output signal on channel 2. - */ - -#define LEDC_DUTY_R_CH2 0x0007FFFF -#define LEDC_DUTY_R_CH2_M (LEDC_DUTY_R_CH2_V << LEDC_DUTY_R_CH2_S) -#define LEDC_DUTY_R_CH2_V 0x0007FFFF -#define LEDC_DUTY_R_CH2_S 0 - -/* LEDC_CH3_CONF0_REG register - * Configuration register 0 for channel 3 - */ - -#define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c) - -/* LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0; - * This field is used to select one of timers for channel 3. - * - * 0: select timer0 - * - * 1: select timer1 - * - * 2: select timer2 - * - * 3: select timer3 - */ - -#define LEDC_TIMER_SEL_CH3 0x00000003 -#define LEDC_TIMER_SEL_CH3_M (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S) -#define LEDC_TIMER_SEL_CH3_V 0x00000003 -#define LEDC_TIMER_SEL_CH3_S 0 - -/* LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0; - * Set this bit to enable signal output on channel 3. - */ - -#define LEDC_SIG_OUT_EN_CH3 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH3_M (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S) -#define LEDC_SIG_OUT_EN_CH3_V 0x00000001 -#define LEDC_SIG_OUT_EN_CH3_S 2 - -/* LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0; - * This bit is used to control the output value when channel 3 is inactive. - */ - -#define LEDC_IDLE_LV_CH3 (BIT(3)) -#define LEDC_IDLE_LV_CH3_M (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S) -#define LEDC_IDLE_LV_CH3_V 0x00000001 -#define LEDC_IDLE_LV_CH3_S 3 - -/* LEDC_PARA_UP_CH3 : WO; bitpos: [4]; default: 0; - * This bit is used to update register LEDC_CH3_HPOINT and LEDC_CH3_DUTY for - * channel 3. - */ - -#define LEDC_PARA_UP_CH3 (BIT(4)) -#define LEDC_PARA_UP_CH3_M (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S) -#define LEDC_PARA_UP_CH3_V 0x00000001 -#define LEDC_PARA_UP_CH3_S 4 - -/* LEDC_OVF_NUM_CH3 : R/W; bitpos: [14:5]; default: 0; - * This register is used to configure the maximum times of overflow minus 1. - * - * The LEDC_OVF_CNT_CH3_INT interrupt will be triggered when channel 3 - * overflows for (LEDC_OVF_NUM_CH3 + 1) times. - */ - -#define LEDC_OVF_NUM_CH3 0x000003FF -#define LEDC_OVF_NUM_CH3_M (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S) -#define LEDC_OVF_NUM_CH3_V 0x000003FF -#define LEDC_OVF_NUM_CH3_S 5 - -/* LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0; - * This bit is used to enable the ovf_cnt of channel 3. - */ - -#define LEDC_OVF_CNT_EN_CH3 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH3_M (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S) -#define LEDC_OVF_CNT_EN_CH3_V 0x00000001 -#define LEDC_OVF_CNT_EN_CH3_S 15 - -/* LEDC_OVF_CNT_RESET_CH3 : WO; bitpos: [16]; default: 0; - * Set this bit to reset the ovf_cnt of channel 3. - */ - -#define LEDC_OVF_CNT_RESET_CH3 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH3_M (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S) -#define LEDC_OVF_CNT_RESET_CH3_V 0x00000001 -#define LEDC_OVF_CNT_RESET_CH3_S 16 - -/* LEDC_OVF_CNT_RESET_ST_CH3 : RO; bitpos: [17]; default: 0; - * This is the status bit of LEDC_OVF_CNT_RESET_CH3. - */ - -#define LEDC_OVF_CNT_RESET_ST_CH3 (BIT(17)) -#define LEDC_OVF_CNT_RESET_ST_CH3_M (LEDC_OVF_CNT_RESET_ST_CH3_V << LEDC_OVF_CNT_RESET_ST_CH3_S) -#define LEDC_OVF_CNT_RESET_ST_CH3_V 0x00000001 -#define LEDC_OVF_CNT_RESET_ST_CH3_S 17 - -/* LEDC_CH3_HPOINT_REG register - * High point register for channel 3 - */ - -#define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40) - -/* LEDC_HPOINT_CH3 : R/W; bitpos: [13:0]; default: 0; - * The output value changes to high when the selected timers has reached the - * value specified by this register. - */ - -#define LEDC_HPOINT_CH3 0x00003FFF -#define LEDC_HPOINT_CH3_M (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S) -#define LEDC_HPOINT_CH3_V 0x00003FFF -#define LEDC_HPOINT_CH3_S 0 - -/* LEDC_CH3_DUTY_REG register - * Initial duty cycle for channel 3 - */ - -#define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44) - -/* LEDC_DUTY_CH3 : R/W; bitpos: [18:0]; default: 0; - * This register is used to change the output duty by controlling the Lpoint. - * - * The output value turns to low when the selected timers has reached the - * Lpoint. - */ - -#define LEDC_DUTY_CH3 0x0007FFFF -#define LEDC_DUTY_CH3_M (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S) -#define LEDC_DUTY_CH3_V 0x0007FFFF -#define LEDC_DUTY_CH3_S 0 - -/* LEDC_CH3_CONF1_REG register - * Configuration register 1 for channel 3 - */ - -#define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48) - -/* LEDC_DUTY_SCALE_CH3 : R/W; bitpos: [9:0]; default: 0; - * This register is used to configure the changing step scale of duty on - * channel 3. - */ - -#define LEDC_DUTY_SCALE_CH3 0x000003FF -#define LEDC_DUTY_SCALE_CH3_M (LEDC_DUTY_SCALE_CH3_V << LEDC_DUTY_SCALE_CH3_S) -#define LEDC_DUTY_SCALE_CH3_V 0x000003FF -#define LEDC_DUTY_SCALE_CH3_S 0 - -/* LEDC_DUTY_CYCLE_CH3 : R/W; bitpos: [19:10]; default: 0; - * The duty will change every LEDC_DUTY_CYCLE_CH3 on channel 3. - */ - -#define LEDC_DUTY_CYCLE_CH3 0x000003FF -#define LEDC_DUTY_CYCLE_CH3_M (LEDC_DUTY_CYCLE_CH3_V << LEDC_DUTY_CYCLE_CH3_S) -#define LEDC_DUTY_CYCLE_CH3_V 0x000003FF -#define LEDC_DUTY_CYCLE_CH3_S 10 - -/* LEDC_DUTY_NUM_CH3 : R/W; bitpos: [29:20]; default: 0; - * This register is used to control the number of times the duty cycle will - * be changed. - */ - -#define LEDC_DUTY_NUM_CH3 0x000003FF -#define LEDC_DUTY_NUM_CH3_M (LEDC_DUTY_NUM_CH3_V << LEDC_DUTY_NUM_CH3_S) -#define LEDC_DUTY_NUM_CH3_V 0x000003FF -#define LEDC_DUTY_NUM_CH3_S 20 - -/* LEDC_DUTY_INC_CH3 : R/W; bitpos: [30]; default: 1; - * This register is used to increase or decrease the duty of output signal - * on channel 3. 1: Increase;0: Decrease. - */ - -#define LEDC_DUTY_INC_CH3 (BIT(30)) -#define LEDC_DUTY_INC_CH3_M (LEDC_DUTY_INC_CH3_V << LEDC_DUTY_INC_CH3_S) -#define LEDC_DUTY_INC_CH3_V 0x00000001 -#define LEDC_DUTY_INC_CH3_S 30 - -/* LEDC_DUTY_START_CH3 : R/W; bitpos: [31]; default: 0; - * Other configured fields in LEDC_CH3_CONF1_REG will start to take effect - * when this bit is set to 1. - */ - -#define LEDC_DUTY_START_CH3 (BIT(31)) -#define LEDC_DUTY_START_CH3_M (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S) -#define LEDC_DUTY_START_CH3_V 0x00000001 -#define LEDC_DUTY_START_CH3_S 31 - -/* LEDC_CH3_DUTY_R_REG register - * Current duty cycle for channel 3 - */ - -#define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c) - -/* LEDC_DUTY_R_CH3 : RO; bitpos: [18:0]; default: 0; - * This register stores the current duty of output signal on channel 3. - */ - -#define LEDC_DUTY_R_CH3 0x0007FFFF -#define LEDC_DUTY_R_CH3_M (LEDC_DUTY_R_CH3_V << LEDC_DUTY_R_CH3_S) -#define LEDC_DUTY_R_CH3_V 0x0007FFFF -#define LEDC_DUTY_R_CH3_S 0 - -/* LEDC_CH4_CONF0_REG register - * Configuration register 0 for channel 4 - */ - -#define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50) - -/* LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0; - * This field is used to select one of timers for channel 4. - * - * 0: select timer0 - * - * 1: select timer1 - * - * 2: select timer2 - * - * 3: select timer3 - */ - -#define LEDC_TIMER_SEL_CH4 0x00000003 -#define LEDC_TIMER_SEL_CH4_M (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S) -#define LEDC_TIMER_SEL_CH4_V 0x00000003 -#define LEDC_TIMER_SEL_CH4_S 0 - -/* LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0; - * Set this bit to enable signal output on channel 4. - */ - -#define LEDC_SIG_OUT_EN_CH4 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH4_M (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S) -#define LEDC_SIG_OUT_EN_CH4_V 0x00000001 -#define LEDC_SIG_OUT_EN_CH4_S 2 - -/* LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0; - * This bit is used to control the output value when channel 4 is inactive. - */ - -#define LEDC_IDLE_LV_CH4 (BIT(3)) -#define LEDC_IDLE_LV_CH4_M (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S) -#define LEDC_IDLE_LV_CH4_V 0x00000001 -#define LEDC_IDLE_LV_CH4_S 3 - -/* LEDC_PARA_UP_CH4 : WO; bitpos: [4]; default: 0; - * This bit is used to update register LEDC_CH4_HPOINT and LEDC_CH4_DUTY for - * channel 4. - */ - -#define LEDC_PARA_UP_CH4 (BIT(4)) -#define LEDC_PARA_UP_CH4_M (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S) -#define LEDC_PARA_UP_CH4_V 0x00000001 -#define LEDC_PARA_UP_CH4_S 4 - -/* LEDC_OVF_NUM_CH4 : R/W; bitpos: [14:5]; default: 0; - * This register is used to configure the maximum times of overflow minus 1. - * - * The LEDC_OVF_CNT_CH4_INT interrupt will be triggered when channel 4 - * overflows for (LEDC_OVF_NUM_CH4 + 1) times. - */ - -#define LEDC_OVF_NUM_CH4 0x000003FF -#define LEDC_OVF_NUM_CH4_M (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S) -#define LEDC_OVF_NUM_CH4_V 0x000003FF -#define LEDC_OVF_NUM_CH4_S 5 - -/* LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0; - * This bit is used to enable the ovf_cnt of channel 4. - */ - -#define LEDC_OVF_CNT_EN_CH4 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH4_M (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S) -#define LEDC_OVF_CNT_EN_CH4_V 0x00000001 -#define LEDC_OVF_CNT_EN_CH4_S 15 - -/* LEDC_OVF_CNT_RESET_CH4 : WO; bitpos: [16]; default: 0; - * Set this bit to reset the ovf_cnt of channel 4. - */ - -#define LEDC_OVF_CNT_RESET_CH4 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH4_M (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S) -#define LEDC_OVF_CNT_RESET_CH4_V 0x00000001 -#define LEDC_OVF_CNT_RESET_CH4_S 16 - -/* LEDC_OVF_CNT_RESET_ST_CH4 : RO; bitpos: [17]; default: 0; - * This is the status bit of LEDC_OVF_CNT_RESET_CH4. - */ - -#define LEDC_OVF_CNT_RESET_ST_CH4 (BIT(17)) -#define LEDC_OVF_CNT_RESET_ST_CH4_M (LEDC_OVF_CNT_RESET_ST_CH4_V << LEDC_OVF_CNT_RESET_ST_CH4_S) -#define LEDC_OVF_CNT_RESET_ST_CH4_V 0x00000001 -#define LEDC_OVF_CNT_RESET_ST_CH4_S 17 - -/* LEDC_CH4_HPOINT_REG register - * High point register for channel 4 - */ - -#define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54) - -/* LEDC_HPOINT_CH4 : R/W; bitpos: [13:0]; default: 0; - * The output value changes to high when the selected timers has reached the - * value specified by this register. - */ - -#define LEDC_HPOINT_CH4 0x00003FFF -#define LEDC_HPOINT_CH4_M (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S) -#define LEDC_HPOINT_CH4_V 0x00003FFF -#define LEDC_HPOINT_CH4_S 0 - -/* LEDC_CH4_DUTY_REG register - * Initial duty cycle for channel 4 - */ - -#define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58) - -/* LEDC_DUTY_CH4 : R/W; bitpos: [18:0]; default: 0; - * This register is used to change the output duty by controlling the Lpoint. - * - * The output value turns to low when the selected timers has reached the - * Lpoint. - */ - -#define LEDC_DUTY_CH4 0x0007FFFF -#define LEDC_DUTY_CH4_M (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S) -#define LEDC_DUTY_CH4_V 0x0007FFFF -#define LEDC_DUTY_CH4_S 0 - -/* LEDC_CH4_CONF1_REG register - * Configuration register 1 for channel 4 - */ - -#define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c) - -/* LEDC_DUTY_SCALE_CH4 : R/W; bitpos: [9:0]; default: 0; - * This register is used to configure the changing step scale of duty on - * channel 4. - */ - -#define LEDC_DUTY_SCALE_CH4 0x000003FF -#define LEDC_DUTY_SCALE_CH4_M (LEDC_DUTY_SCALE_CH4_V << LEDC_DUTY_SCALE_CH4_S) -#define LEDC_DUTY_SCALE_CH4_V 0x000003FF -#define LEDC_DUTY_SCALE_CH4_S 0 - -/* LEDC_DUTY_CYCLE_CH4 : R/W; bitpos: [19:10]; default: 0; - * The duty will change every LEDC_DUTY_CYCLE_CH4 on channel 4. - */ - -#define LEDC_DUTY_CYCLE_CH4 0x000003FF -#define LEDC_DUTY_CYCLE_CH4_M (LEDC_DUTY_CYCLE_CH4_V << LEDC_DUTY_CYCLE_CH4_S) -#define LEDC_DUTY_CYCLE_CH4_V 0x000003FF -#define LEDC_DUTY_CYCLE_CH4_S 10 - -/* LEDC_DUTY_NUM_CH4 : R/W; bitpos: [29:20]; default: 0; - * This register is used to control the number of times the duty cycle will - * be changed. - */ - -#define LEDC_DUTY_NUM_CH4 0x000003FF -#define LEDC_DUTY_NUM_CH4_M (LEDC_DUTY_NUM_CH4_V << LEDC_DUTY_NUM_CH4_S) -#define LEDC_DUTY_NUM_CH4_V 0x000003FF -#define LEDC_DUTY_NUM_CH4_S 20 - -/* LEDC_DUTY_INC_CH4 : R/W; bitpos: [30]; default: 1; - * This register is used to increase or decrease the duty of output signal - * on channel 4. 1: Increase;0: Decrease. - */ - -#define LEDC_DUTY_INC_CH4 (BIT(30)) -#define LEDC_DUTY_INC_CH4_M (LEDC_DUTY_INC_CH4_V << LEDC_DUTY_INC_CH4_S) -#define LEDC_DUTY_INC_CH4_V 0x00000001 -#define LEDC_DUTY_INC_CH4_S 30 - -/* LEDC_DUTY_START_CH4 : R/W; bitpos: [31]; default: 0; - * Other configured fields in LEDC_CH4_CONF1_REG will start to take effect - * when this bit is set to 1. - */ - -#define LEDC_DUTY_START_CH4 (BIT(31)) -#define LEDC_DUTY_START_CH4_M (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S) -#define LEDC_DUTY_START_CH4_V 0x00000001 -#define LEDC_DUTY_START_CH4_S 31 - -/* LEDC_CH4_DUTY_R_REG register - * Current duty cycle for channel 4 - */ - -#define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60) - -/* LEDC_DUTY_R_CH4 : RO; bitpos: [18:0]; default: 0; - * This register stores the current duty of output signal on channel 4. - */ - -#define LEDC_DUTY_R_CH4 0x0007FFFF -#define LEDC_DUTY_R_CH4_M (LEDC_DUTY_R_CH4_V << LEDC_DUTY_R_CH4_S) -#define LEDC_DUTY_R_CH4_V 0x0007FFFF -#define LEDC_DUTY_R_CH4_S 0 - -/* LEDC_CH5_CONF0_REG register - * Configuration register 0 for channel 5 - */ - -#define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64) - -/* LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0; - * This field is used to select one of timers for channel 5. - * - * 0: select timer0 - * - * 1: select timer1 - * - * 2: select timer2 - * - * 3: select timer3 - */ - -#define LEDC_TIMER_SEL_CH5 0x00000003 -#define LEDC_TIMER_SEL_CH5_M (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S) -#define LEDC_TIMER_SEL_CH5_V 0x00000003 -#define LEDC_TIMER_SEL_CH5_S 0 - -/* LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0; - * Set this bit to enable signal output on channel 5. - */ - -#define LEDC_SIG_OUT_EN_CH5 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH5_M (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S) -#define LEDC_SIG_OUT_EN_CH5_V 0x00000001 -#define LEDC_SIG_OUT_EN_CH5_S 2 - -/* LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0; - * This bit is used to control the output value when channel 5 is inactive. - */ - -#define LEDC_IDLE_LV_CH5 (BIT(3)) -#define LEDC_IDLE_LV_CH5_M (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S) -#define LEDC_IDLE_LV_CH5_V 0x00000001 -#define LEDC_IDLE_LV_CH5_S 3 - -/* LEDC_PARA_UP_CH5 : WO; bitpos: [4]; default: 0; - * This bit is used to update register LEDC_CH5_HPOINT and LEDC_CH5_DUTY for - * channel 5. - */ - -#define LEDC_PARA_UP_CH5 (BIT(4)) -#define LEDC_PARA_UP_CH5_M (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S) -#define LEDC_PARA_UP_CH5_V 0x00000001 -#define LEDC_PARA_UP_CH5_S 4 - -/* LEDC_OVF_NUM_CH5 : R/W; bitpos: [14:5]; default: 0; - * This register is used to configure the maximum times of overflow minus 1. - * - * The LEDC_OVF_CNT_CH5_INT interrupt will be triggered when channel 5 - * overflows for (LEDC_OVF_NUM_CH5 + 1) times. - */ - -#define LEDC_OVF_NUM_CH5 0x000003FF -#define LEDC_OVF_NUM_CH5_M (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S) -#define LEDC_OVF_NUM_CH5_V 0x000003FF -#define LEDC_OVF_NUM_CH5_S 5 - -/* LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0; - * This bit is used to enable the ovf_cnt of channel 5. - */ - -#define LEDC_OVF_CNT_EN_CH5 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH5_M (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S) -#define LEDC_OVF_CNT_EN_CH5_V 0x00000001 -#define LEDC_OVF_CNT_EN_CH5_S 15 - -/* LEDC_OVF_CNT_RESET_CH5 : WO; bitpos: [16]; default: 0; - * Set this bit to reset the ovf_cnt of channel 5. - */ - -#define LEDC_OVF_CNT_RESET_CH5 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH5_M (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S) -#define LEDC_OVF_CNT_RESET_CH5_V 0x00000001 -#define LEDC_OVF_CNT_RESET_CH5_S 16 - -/* LEDC_OVF_CNT_RESET_ST_CH5 : RO; bitpos: [17]; default: 0; - * This is the status bit of LEDC_OVF_CNT_RESET_CH5. - */ - -#define LEDC_OVF_CNT_RESET_ST_CH5 (BIT(17)) -#define LEDC_OVF_CNT_RESET_ST_CH5_M (LEDC_OVF_CNT_RESET_ST_CH5_V << LEDC_OVF_CNT_RESET_ST_CH5_S) -#define LEDC_OVF_CNT_RESET_ST_CH5_V 0x00000001 -#define LEDC_OVF_CNT_RESET_ST_CH5_S 17 - -/* LEDC_CH5_HPOINT_REG register - * High point register for channel 5 - */ - -#define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68) - -/* LEDC_HPOINT_CH5 : R/W; bitpos: [13:0]; default: 0; - * The output value changes to high when the selected timers has reached the - * value specified by this register. - */ - -#define LEDC_HPOINT_CH5 0x00003FFF -#define LEDC_HPOINT_CH5_M (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S) -#define LEDC_HPOINT_CH5_V 0x00003FFF -#define LEDC_HPOINT_CH5_S 0 - -/* LEDC_CH5_DUTY_REG register - * Initial duty cycle for channel 5 - */ - -#define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c) - -/* LEDC_DUTY_CH5 : R/W; bitpos: [18:0]; default: 0; - * This register is used to change the output duty by controlling the Lpoint. - * - * The output value turns to low when the selected timers has reached the - * Lpoint. - */ - -#define LEDC_DUTY_CH5 0x0007FFFF -#define LEDC_DUTY_CH5_M (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S) -#define LEDC_DUTY_CH5_V 0x0007FFFF -#define LEDC_DUTY_CH5_S 0 - -/* LEDC_CH5_CONF1_REG register - * Configuration register 1 for channel 5 - */ - -#define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70) - -/* LEDC_DUTY_SCALE_CH5 : R/W; bitpos: [9:0]; default: 0; - * This register is used to configure the changing step scale of duty on - * channel 5. - */ - -#define LEDC_DUTY_SCALE_CH5 0x000003FF -#define LEDC_DUTY_SCALE_CH5_M (LEDC_DUTY_SCALE_CH5_V << LEDC_DUTY_SCALE_CH5_S) -#define LEDC_DUTY_SCALE_CH5_V 0x000003FF -#define LEDC_DUTY_SCALE_CH5_S 0 - -/* LEDC_DUTY_CYCLE_CH5 : R/W; bitpos: [19:10]; default: 0; - * The duty will change every LEDC_DUTY_CYCLE_CH5 on channel 5. - */ - -#define LEDC_DUTY_CYCLE_CH5 0x000003FF -#define LEDC_DUTY_CYCLE_CH5_M (LEDC_DUTY_CYCLE_CH5_V << LEDC_DUTY_CYCLE_CH5_S) -#define LEDC_DUTY_CYCLE_CH5_V 0x000003FF -#define LEDC_DUTY_CYCLE_CH5_S 10 - -/* LEDC_DUTY_NUM_CH5 : R/W; bitpos: [29:20]; default: 0; - * This register is used to control the number of times the duty cycle will - * be changed. - */ - -#define LEDC_DUTY_NUM_CH5 0x000003FF -#define LEDC_DUTY_NUM_CH5_M (LEDC_DUTY_NUM_CH5_V << LEDC_DUTY_NUM_CH5_S) -#define LEDC_DUTY_NUM_CH5_V 0x000003FF -#define LEDC_DUTY_NUM_CH5_S 20 - -/* LEDC_DUTY_INC_CH5 : R/W; bitpos: [30]; default: 1; - * This register is used to increase or decrease the duty of output signal - * on channel 5. 1: Increase;0: Decrease. - */ - -#define LEDC_DUTY_INC_CH5 (BIT(30)) -#define LEDC_DUTY_INC_CH5_M (LEDC_DUTY_INC_CH5_V << LEDC_DUTY_INC_CH5_S) -#define LEDC_DUTY_INC_CH5_V 0x00000001 -#define LEDC_DUTY_INC_CH5_S 30 - -/* LEDC_DUTY_START_CH5 : R/W; bitpos: [31]; default: 0; - * Other configured fields in LEDC_CH5_CONF1_REG will start to take effect - * when this bit is set to 1. - */ - -#define LEDC_DUTY_START_CH5 (BIT(31)) -#define LEDC_DUTY_START_CH5_M (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S) -#define LEDC_DUTY_START_CH5_V 0x00000001 -#define LEDC_DUTY_START_CH5_S 31 - -/* LEDC_CH5_DUTY_R_REG register - * Current duty cycle for channel 5 - */ - -#define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74) - -/* LEDC_DUTY_R_CH5 : RO; bitpos: [18:0]; default: 0; - * This register stores the current duty of output signal on channel 5. - */ - -#define LEDC_DUTY_R_CH5 0x0007FFFF -#define LEDC_DUTY_R_CH5_M (LEDC_DUTY_R_CH5_V << LEDC_DUTY_R_CH5_S) -#define LEDC_DUTY_R_CH5_V 0x0007FFFF -#define LEDC_DUTY_R_CH5_S 0 - -/* LEDC_CH6_CONF0_REG register - * Configuration register 0 for channel 6 - */ - -#define LEDC_CH6_CONF0_REG (DR_REG_LEDC_BASE + 0x78) - -/* LEDC_TIMER_SEL_CH6 : R/W; bitpos: [1:0]; default: 0; - * This field is used to select one of timers for channel 6. - * - * 0: select timer0 - * - * 1: select timer1 - * - * 2: select timer2 - * - * 3: select timer3 - */ - -#define LEDC_TIMER_SEL_CH6 0x00000003 -#define LEDC_TIMER_SEL_CH6_M (LEDC_TIMER_SEL_CH6_V << LEDC_TIMER_SEL_CH6_S) -#define LEDC_TIMER_SEL_CH6_V 0x00000003 -#define LEDC_TIMER_SEL_CH6_S 0 - -/* LEDC_SIG_OUT_EN_CH6 : R/W; bitpos: [2]; default: 0; - * Set this bit to enable signal output on channel 6. - */ - -#define LEDC_SIG_OUT_EN_CH6 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH6_M (LEDC_SIG_OUT_EN_CH6_V << LEDC_SIG_OUT_EN_CH6_S) -#define LEDC_SIG_OUT_EN_CH6_V 0x00000001 -#define LEDC_SIG_OUT_EN_CH6_S 2 - -/* LEDC_IDLE_LV_CH6 : R/W; bitpos: [3]; default: 0; - * This bit is used to control the output value when channel 6 is inactive. - */ - -#define LEDC_IDLE_LV_CH6 (BIT(3)) -#define LEDC_IDLE_LV_CH6_M (LEDC_IDLE_LV_CH6_V << LEDC_IDLE_LV_CH6_S) -#define LEDC_IDLE_LV_CH6_V 0x00000001 -#define LEDC_IDLE_LV_CH6_S 3 - -/* LEDC_PARA_UP_CH6 : WO; bitpos: [4]; default: 0; - * This bit is used to update register LEDC_CH6_HPOINT and LEDC_CH6_DUTY for - * channel 6. - */ - -#define LEDC_PARA_UP_CH6 (BIT(4)) -#define LEDC_PARA_UP_CH6_M (LEDC_PARA_UP_CH6_V << LEDC_PARA_UP_CH6_S) -#define LEDC_PARA_UP_CH6_V 0x00000001 -#define LEDC_PARA_UP_CH6_S 4 - -/* LEDC_OVF_NUM_CH6 : R/W; bitpos: [14:5]; default: 0; - * This register is used to configure the maximum times of overflow minus 1. - * - * The LEDC_OVF_CNT_CH6_INT interrupt will be triggered when channel 6 - * overflows for (LEDC_OVF_NUM_CH6 + 1) times. - */ - -#define LEDC_OVF_NUM_CH6 0x000003FF -#define LEDC_OVF_NUM_CH6_M (LEDC_OVF_NUM_CH6_V << LEDC_OVF_NUM_CH6_S) -#define LEDC_OVF_NUM_CH6_V 0x000003FF -#define LEDC_OVF_NUM_CH6_S 5 - -/* LEDC_OVF_CNT_EN_CH6 : R/W; bitpos: [15]; default: 0; - * This bit is used to enable the ovf_cnt of channel 6. - */ - -#define LEDC_OVF_CNT_EN_CH6 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH6_M (LEDC_OVF_CNT_EN_CH6_V << LEDC_OVF_CNT_EN_CH6_S) -#define LEDC_OVF_CNT_EN_CH6_V 0x00000001 -#define LEDC_OVF_CNT_EN_CH6_S 15 - -/* LEDC_OVF_CNT_RESET_CH6 : WO; bitpos: [16]; default: 0; - * Set this bit to reset the ovf_cnt of channel 6. - */ - -#define LEDC_OVF_CNT_RESET_CH6 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH6_M (LEDC_OVF_CNT_RESET_CH6_V << LEDC_OVF_CNT_RESET_CH6_S) -#define LEDC_OVF_CNT_RESET_CH6_V 0x00000001 -#define LEDC_OVF_CNT_RESET_CH6_S 16 - -/* LEDC_OVF_CNT_RESET_ST_CH6 : RO; bitpos: [17]; default: 0; - * This is the status bit of LEDC_OVF_CNT_RESET_CH6. - */ - -#define LEDC_OVF_CNT_RESET_ST_CH6 (BIT(17)) -#define LEDC_OVF_CNT_RESET_ST_CH6_M (LEDC_OVF_CNT_RESET_ST_CH6_V << LEDC_OVF_CNT_RESET_ST_CH6_S) -#define LEDC_OVF_CNT_RESET_ST_CH6_V 0x00000001 -#define LEDC_OVF_CNT_RESET_ST_CH6_S 17 - -/* LEDC_CH6_HPOINT_REG register - * High point register for channel 6 - */ - -#define LEDC_CH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x7c) - -/* LEDC_HPOINT_CH6 : R/W; bitpos: [13:0]; default: 0; - * The output value changes to high when the selected timers has reached the - * value specified by this register. - */ - -#define LEDC_HPOINT_CH6 0x00003FFF -#define LEDC_HPOINT_CH6_M (LEDC_HPOINT_CH6_V << LEDC_HPOINT_CH6_S) -#define LEDC_HPOINT_CH6_V 0x00003FFF -#define LEDC_HPOINT_CH6_S 0 - -/* LEDC_CH6_DUTY_REG register - * Initial duty cycle for channel 6 - */ - -#define LEDC_CH6_DUTY_REG (DR_REG_LEDC_BASE + 0x80) - -/* LEDC_DUTY_CH6 : R/W; bitpos: [18:0]; default: 0; - * This register is used to change the output duty by controlling the Lpoint. - * - * The output value turns to low when the selected timers has reached the - * Lpoint. - */ - -#define LEDC_DUTY_CH6 0x0007FFFF -#define LEDC_DUTY_CH6_M (LEDC_DUTY_CH6_V << LEDC_DUTY_CH6_S) -#define LEDC_DUTY_CH6_V 0x0007FFFF -#define LEDC_DUTY_CH6_S 0 - -/* LEDC_CH6_CONF1_REG register - * Configuration register 1 for channel 6 - */ - -#define LEDC_CH6_CONF1_REG (DR_REG_LEDC_BASE + 0x84) - -/* LEDC_DUTY_SCALE_CH6 : R/W; bitpos: [9:0]; default: 0; - * This register is used to configure the changing step scale of duty on - * channel 6. - */ - -#define LEDC_DUTY_SCALE_CH6 0x000003FF -#define LEDC_DUTY_SCALE_CH6_M (LEDC_DUTY_SCALE_CH6_V << LEDC_DUTY_SCALE_CH6_S) -#define LEDC_DUTY_SCALE_CH6_V 0x000003FF -#define LEDC_DUTY_SCALE_CH6_S 0 - -/* LEDC_DUTY_CYCLE_CH6 : R/W; bitpos: [19:10]; default: 0; - * The duty will change every LEDC_DUTY_CYCLE_CH6 on channel 6. - */ - -#define LEDC_DUTY_CYCLE_CH6 0x000003FF -#define LEDC_DUTY_CYCLE_CH6_M (LEDC_DUTY_CYCLE_CH6_V << LEDC_DUTY_CYCLE_CH6_S) -#define LEDC_DUTY_CYCLE_CH6_V 0x000003FF -#define LEDC_DUTY_CYCLE_CH6_S 10 - -/* LEDC_DUTY_NUM_CH6 : R/W; bitpos: [29:20]; default: 0; - * This register is used to control the number of times the duty cycle will - * be changed. - */ - -#define LEDC_DUTY_NUM_CH6 0x000003FF -#define LEDC_DUTY_NUM_CH6_M (LEDC_DUTY_NUM_CH6_V << LEDC_DUTY_NUM_CH6_S) -#define LEDC_DUTY_NUM_CH6_V 0x000003FF -#define LEDC_DUTY_NUM_CH6_S 20 - -/* LEDC_DUTY_INC_CH6 : R/W; bitpos: [30]; default: 1; - * This register is used to increase or decrease the duty of output signal - * on channel 6. 1: Increase;0: Decrease. - */ - -#define LEDC_DUTY_INC_CH6 (BIT(30)) -#define LEDC_DUTY_INC_CH6_M (LEDC_DUTY_INC_CH6_V << LEDC_DUTY_INC_CH6_S) -#define LEDC_DUTY_INC_CH6_V 0x00000001 -#define LEDC_DUTY_INC_CH6_S 30 - -/* LEDC_DUTY_START_CH6 : R/W; bitpos: [31]; default: 0; - * Other configured fields in LEDC_CH6_CONF1_REG will start to take effect - * when this bit is set to 1. - */ - -#define LEDC_DUTY_START_CH6 (BIT(31)) -#define LEDC_DUTY_START_CH6_M (LEDC_DUTY_START_CH6_V << LEDC_DUTY_START_CH6_S) -#define LEDC_DUTY_START_CH6_V 0x00000001 -#define LEDC_DUTY_START_CH6_S 31 - -/* LEDC_CH6_DUTY_R_REG register - * Current duty cycle for channel 6 - */ - -#define LEDC_CH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x88) - -/* LEDC_DUTY_R_CH6 : RO; bitpos: [18:0]; default: 0; - * This register stores the current duty of output signal on channel 6. - */ - -#define LEDC_DUTY_R_CH6 0x0007FFFF -#define LEDC_DUTY_R_CH6_M (LEDC_DUTY_R_CH6_V << LEDC_DUTY_R_CH6_S) -#define LEDC_DUTY_R_CH6_V 0x0007FFFF -#define LEDC_DUTY_R_CH6_S 0 - -/* LEDC_CH7_CONF0_REG register - * Configuration register 0 for channel 7 - */ - -#define LEDC_CH7_CONF0_REG (DR_REG_LEDC_BASE + 0x8c) - -/* LEDC_TIMER_SEL_CH7 : R/W; bitpos: [1:0]; default: 0; - * This field is used to select one of timers for channel 7. - * - * 0: select timer0 - * - * 1: select timer1 - * - * 2: select timer2 - * - * 3: select timer3 - */ - -#define LEDC_TIMER_SEL_CH7 0x00000003 -#define LEDC_TIMER_SEL_CH7_M (LEDC_TIMER_SEL_CH7_V << LEDC_TIMER_SEL_CH7_S) -#define LEDC_TIMER_SEL_CH7_V 0x00000003 -#define LEDC_TIMER_SEL_CH7_S 0 - -/* LEDC_SIG_OUT_EN_CH7 : R/W; bitpos: [2]; default: 0; - * Set this bit to enable signal output on channel 7. - */ - -#define LEDC_SIG_OUT_EN_CH7 (BIT(2)) -#define LEDC_SIG_OUT_EN_CH7_M (LEDC_SIG_OUT_EN_CH7_V << LEDC_SIG_OUT_EN_CH7_S) -#define LEDC_SIG_OUT_EN_CH7_V 0x00000001 -#define LEDC_SIG_OUT_EN_CH7_S 2 - -/* LEDC_IDLE_LV_CH7 : R/W; bitpos: [3]; default: 0; - * This bit is used to control the output value when channel 7 is inactive. - */ - -#define LEDC_IDLE_LV_CH7 (BIT(3)) -#define LEDC_IDLE_LV_CH7_M (LEDC_IDLE_LV_CH7_V << LEDC_IDLE_LV_CH7_S) -#define LEDC_IDLE_LV_CH7_V 0x00000001 -#define LEDC_IDLE_LV_CH7_S 3 - -/* LEDC_PARA_UP_CH7 : WO; bitpos: [4]; default: 0; - * This bit is used to update register LEDC_CH7_HPOINT and LEDC_CH7_DUTY for - * channel 7. - */ - -#define LEDC_PARA_UP_CH7 (BIT(4)) -#define LEDC_PARA_UP_CH7_M (LEDC_PARA_UP_CH7_V << LEDC_PARA_UP_CH7_S) -#define LEDC_PARA_UP_CH7_V 0x00000001 -#define LEDC_PARA_UP_CH7_S 4 - -/* LEDC_OVF_NUM_CH7 : R/W; bitpos: [14:5]; default: 0; - * This register is used to configure the maximum times of overflow minus 1. - * - * The LEDC_OVF_CNT_CH7_INT interrupt will be triggered when channel 7 - * overflows for (LEDC_OVF_NUM_CH7 + 1) times. - */ - -#define LEDC_OVF_NUM_CH7 0x000003FF -#define LEDC_OVF_NUM_CH7_M (LEDC_OVF_NUM_CH7_V << LEDC_OVF_NUM_CH7_S) -#define LEDC_OVF_NUM_CH7_V 0x000003FF -#define LEDC_OVF_NUM_CH7_S 5 - -/* LEDC_OVF_CNT_EN_CH7 : R/W; bitpos: [15]; default: 0; - * This bit is used to enable the ovf_cnt of channel 7. - */ - -#define LEDC_OVF_CNT_EN_CH7 (BIT(15)) -#define LEDC_OVF_CNT_EN_CH7_M (LEDC_OVF_CNT_EN_CH7_V << LEDC_OVF_CNT_EN_CH7_S) -#define LEDC_OVF_CNT_EN_CH7_V 0x00000001 -#define LEDC_OVF_CNT_EN_CH7_S 15 - -/* LEDC_OVF_CNT_RESET_CH7 : WO; bitpos: [16]; default: 0; - * Set this bit to reset the ovf_cnt of channel 7. - */ - -#define LEDC_OVF_CNT_RESET_CH7 (BIT(16)) -#define LEDC_OVF_CNT_RESET_CH7_M (LEDC_OVF_CNT_RESET_CH7_V << LEDC_OVF_CNT_RESET_CH7_S) -#define LEDC_OVF_CNT_RESET_CH7_V 0x00000001 -#define LEDC_OVF_CNT_RESET_CH7_S 16 - -/* LEDC_OVF_CNT_RESET_ST_CH7 : RO; bitpos: [17]; default: 0; - * This is the status bit of LEDC_OVF_CNT_RESET_CH7. - */ - -#define LEDC_OVF_CNT_RESET_ST_CH7 (BIT(17)) -#define LEDC_OVF_CNT_RESET_ST_CH7_M (LEDC_OVF_CNT_RESET_ST_CH7_V << LEDC_OVF_CNT_RESET_ST_CH7_S) -#define LEDC_OVF_CNT_RESET_ST_CH7_V 0x00000001 -#define LEDC_OVF_CNT_RESET_ST_CH7_S 17 - -/* LEDC_CH7_HPOINT_REG register - * High point register for channel 7 - */ - -#define LEDC_CH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x90) - -/* LEDC_HPOINT_CH7 : R/W; bitpos: [13:0]; default: 0; - * The output value changes to high when the selected timers has reached the - * value specified by this register. - */ - -#define LEDC_HPOINT_CH7 0x00003FFF -#define LEDC_HPOINT_CH7_M (LEDC_HPOINT_CH7_V << LEDC_HPOINT_CH7_S) -#define LEDC_HPOINT_CH7_V 0x00003FFF -#define LEDC_HPOINT_CH7_S 0 - -/* LEDC_CH7_DUTY_REG register - * Initial duty cycle for channel 7 - */ - -#define LEDC_CH7_DUTY_REG (DR_REG_LEDC_BASE + 0x94) - -/* LEDC_DUTY_CH7 : R/W; bitpos: [18:0]; default: 0; - * This register is used to change the output duty by controlling the Lpoint. - * - * The output value turns to low when the selected timers has reached the - * Lpoint. - */ - -#define LEDC_DUTY_CH7 0x0007FFFF -#define LEDC_DUTY_CH7_M (LEDC_DUTY_CH7_V << LEDC_DUTY_CH7_S) -#define LEDC_DUTY_CH7_V 0x0007FFFF -#define LEDC_DUTY_CH7_S 0 - -/* LEDC_CH7_CONF1_REG register - * Configuration register 1 for channel 7 - */ - -#define LEDC_CH7_CONF1_REG (DR_REG_LEDC_BASE + 0x98) - -/* LEDC_DUTY_SCALE_CH7 : R/W; bitpos: [9:0]; default: 0; - * This register is used to configure the changing step scale of duty on - * channel 7. - */ - -#define LEDC_DUTY_SCALE_CH7 0x000003FF -#define LEDC_DUTY_SCALE_CH7_M (LEDC_DUTY_SCALE_CH7_V << LEDC_DUTY_SCALE_CH7_S) -#define LEDC_DUTY_SCALE_CH7_V 0x000003FF -#define LEDC_DUTY_SCALE_CH7_S 0 - -/* LEDC_DUTY_CYCLE_CH7 : R/W; bitpos: [19:10]; default: 0; - * The duty will change every LEDC_DUTY_CYCLE_CH7 on channel 7. - */ - -#define LEDC_DUTY_CYCLE_CH7 0x000003FF -#define LEDC_DUTY_CYCLE_CH7_M (LEDC_DUTY_CYCLE_CH7_V << LEDC_DUTY_CYCLE_CH7_S) -#define LEDC_DUTY_CYCLE_CH7_V 0x000003FF -#define LEDC_DUTY_CYCLE_CH7_S 10 - -/* LEDC_DUTY_NUM_CH7 : R/W; bitpos: [29:20]; default: 0; - * This register is used to control the number of times the duty cycle will - * be changed. - */ - -#define LEDC_DUTY_NUM_CH7 0x000003FF -#define LEDC_DUTY_NUM_CH7_M (LEDC_DUTY_NUM_CH7_V << LEDC_DUTY_NUM_CH7_S) -#define LEDC_DUTY_NUM_CH7_V 0x000003FF -#define LEDC_DUTY_NUM_CH7_S 20 - -/* LEDC_DUTY_INC_CH7 : R/W; bitpos: [30]; default: 1; - * This register is used to increase or decrease the duty of output signal - * on channel 7. 1: Increase;0: Decrease. - */ - -#define LEDC_DUTY_INC_CH7 (BIT(30)) -#define LEDC_DUTY_INC_CH7_M (LEDC_DUTY_INC_CH7_V << LEDC_DUTY_INC_CH7_S) -#define LEDC_DUTY_INC_CH7_V 0x00000001 -#define LEDC_DUTY_INC_CH7_S 30 - -/* LEDC_DUTY_START_CH7 : R/W; bitpos: [31]; default: 0; - * Other configured fields in LEDC_CH7_CONF1_REG will start to take effect - * when this bit is set to 1. - */ - -#define LEDC_DUTY_START_CH7 (BIT(31)) -#define LEDC_DUTY_START_CH7_M (LEDC_DUTY_START_CH7_V << LEDC_DUTY_START_CH7_S) -#define LEDC_DUTY_START_CH7_V 0x00000001 -#define LEDC_DUTY_START_CH7_S 31 - -/* LEDC_CH7_DUTY_R_REG register - * Current duty cycle for channel 7 - */ - -#define LEDC_CH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x9c) - -/* LEDC_DUTY_R_CH7 : RO; bitpos: [18:0]; default: 0; - * This register stores the current duty of output signal on channel 7. - */ - -#define LEDC_DUTY_R_CH7 0x0007FFFF -#define LEDC_DUTY_R_CH7_M (LEDC_DUTY_R_CH7_V << LEDC_DUTY_R_CH7_S) -#define LEDC_DUTY_R_CH7_V 0x0007FFFF -#define LEDC_DUTY_R_CH7_S 0 - -/* LEDC_TIMER0_CONF_REG register - * Timer 0 configuration - */ - -#define LEDC_TIMER0_CONF_REG (DR_REG_LEDC_BASE + 0xa0) - -/* LEDC_TIMER0_DUTY_RES : R/W; bitpos: [3:0]; default: 0; - * This register is used to control the range of the counter in timer 0. - */ - -#define LEDC_TIMER0_DUTY_RES 0x0000000F -#define LEDC_TIMER0_DUTY_RES_M (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S) -#define LEDC_TIMER0_DUTY_RES_V 0x0000000F -#define LEDC_TIMER0_DUTY_RES_S 0 - -/* LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [21:4]; default: 0; - * This register is used to configure the divisor for the divider in timer 0. - * - * The least significant eight bits represent the fractional part. - */ - -#define LEDC_CLK_DIV_TIMER0 0x0003FFFF -#define LEDC_CLK_DIV_TIMER0_M (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S) -#define LEDC_CLK_DIV_TIMER0_V 0x0003FFFF -#define LEDC_CLK_DIV_TIMER0_S 4 - -/* LEDC_TIMER0_PAUSE : R/W; bitpos: [22]; default: 0; - * This bit is used to suspend the counter in timer 0. - */ - -#define LEDC_TIMER0_PAUSE (BIT(22)) -#define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S) -#define LEDC_TIMER0_PAUSE_V 0x00000001 -#define LEDC_TIMER0_PAUSE_S 22 - -/* LEDC_TIMER0_RST : R/W; bitpos: [23]; default: 1; - * This bit is used to reset timer 0. The counter will show 0 after reset. - */ - -#define LEDC_TIMER0_RST (BIT(23)) -#define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S) -#define LEDC_TIMER0_RST_V 0x00000001 -#define LEDC_TIMER0_RST_S 23 - -/* LEDC_TICK_SEL_TIMER0 : R/W; bitpos: [24]; default: 0; - * This bit is used to select clock for timer 0. When this bit is set to 1 - * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not - * accurate. - * - * 1'h0: SLOW_CLK 1'h1: REF_TICK - */ - -#define LEDC_TICK_SEL_TIMER0 (BIT(24)) -#define LEDC_TICK_SEL_TIMER0_M (LEDC_TICK_SEL_TIMER0_V << LEDC_TICK_SEL_TIMER0_S) -#define LEDC_TICK_SEL_TIMER0_V 0x00000001 -#define LEDC_TICK_SEL_TIMER0_S 24 - -/* LEDC_TIMER0_PARA_UP : WO; bitpos: [25]; default: 0; - * Set this bit to update LEDC_CLK_DIV_TIMER0 and LEDC_TIMER0_DUTY_RES. - */ - -#define LEDC_TIMER0_PARA_UP (BIT(25)) -#define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S) -#define LEDC_TIMER0_PARA_UP_V 0x00000001 -#define LEDC_TIMER0_PARA_UP_S 25 - -/* LEDC_TIMER0_VALUE_REG register - * Timer 0 current counter value - */ - -#define LEDC_TIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0xa4) - -/* LEDC_TIMER0_CNT : RO; bitpos: [13:0]; default: 0; - * This register stores the current counter value of timer 0. - */ - -#define LEDC_TIMER0_CNT 0x00003FFF -#define LEDC_TIMER0_CNT_M (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S) -#define LEDC_TIMER0_CNT_V 0x00003FFF -#define LEDC_TIMER0_CNT_S 0 - -/* LEDC_TIMER1_CONF_REG register - * Timer 1 configuration - */ - -#define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8) - -/* LEDC_TIMER1_DUTY_RES : R/W; bitpos: [3:0]; default: 0; - * This register is used to control the range of the counter in timer 1. - */ - -#define LEDC_TIMER1_DUTY_RES 0x0000000F -#define LEDC_TIMER1_DUTY_RES_M (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S) -#define LEDC_TIMER1_DUTY_RES_V 0x0000000F -#define LEDC_TIMER1_DUTY_RES_S 0 - -/* LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [21:4]; default: 0; - * This register is used to configure the divisor for the divider in timer 1. - * - * The least significant eight bits represent the fractional part. - */ - -#define LEDC_CLK_DIV_TIMER1 0x0003FFFF -#define LEDC_CLK_DIV_TIMER1_M (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S) -#define LEDC_CLK_DIV_TIMER1_V 0x0003FFFF -#define LEDC_CLK_DIV_TIMER1_S 4 - -/* LEDC_TIMER1_PAUSE : R/W; bitpos: [22]; default: 0; - * This bit is used to suspend the counter in timer 1. - */ - -#define LEDC_TIMER1_PAUSE (BIT(22)) -#define LEDC_TIMER1_PAUSE_M (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S) -#define LEDC_TIMER1_PAUSE_V 0x00000001 -#define LEDC_TIMER1_PAUSE_S 22 - -/* LEDC_TIMER1_RST : R/W; bitpos: [23]; default: 1; - * This bit is used to reset timer 1. The counter will show 0 after reset. - */ - -#define LEDC_TIMER1_RST (BIT(23)) -#define LEDC_TIMER1_RST_M (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S) -#define LEDC_TIMER1_RST_V 0x00000001 -#define LEDC_TIMER1_RST_S 23 - -/* LEDC_TICK_SEL_TIMER1 : R/W; bitpos: [24]; default: 0; - * This bit is used to select clock for timer 1. When this bit is set to 1 - * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not - * accurate. - * - * 1'h0: SLOW_CLK 1'h1: REF_TICK - */ - -#define LEDC_TICK_SEL_TIMER1 (BIT(24)) -#define LEDC_TICK_SEL_TIMER1_M (LEDC_TICK_SEL_TIMER1_V << LEDC_TICK_SEL_TIMER1_S) -#define LEDC_TICK_SEL_TIMER1_V 0x00000001 -#define LEDC_TICK_SEL_TIMER1_S 24 - -/* LEDC_TIMER1_PARA_UP : WO; bitpos: [25]; default: 0; - * Set this bit to update LEDC_CLK_DIV_TIMER1 and LEDC_TIMER1_DUTY_RES. - */ - -#define LEDC_TIMER1_PARA_UP (BIT(25)) -#define LEDC_TIMER1_PARA_UP_M (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S) -#define LEDC_TIMER1_PARA_UP_V 0x00000001 -#define LEDC_TIMER1_PARA_UP_S 25 - -/* LEDC_TIMER1_VALUE_REG register - * Timer 1 current counter value - */ - -#define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac) - -/* LEDC_TIMER1_CNT : RO; bitpos: [13:0]; default: 0; - * This register stores the current counter value of timer 1. - */ - -#define LEDC_TIMER1_CNT 0x00003FFF -#define LEDC_TIMER1_CNT_M (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S) -#define LEDC_TIMER1_CNT_V 0x00003FFF -#define LEDC_TIMER1_CNT_S 0 - -/* LEDC_TIMER2_CONF_REG register - * Timer 2 configuration - */ - -#define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0) - -/* LEDC_TIMER2_DUTY_RES : R/W; bitpos: [3:0]; default: 0; - * This register is used to control the range of the counter in timer 2. - */ - -#define LEDC_TIMER2_DUTY_RES 0x0000000F -#define LEDC_TIMER2_DUTY_RES_M (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S) -#define LEDC_TIMER2_DUTY_RES_V 0x0000000F -#define LEDC_TIMER2_DUTY_RES_S 0 - -/* LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [21:4]; default: 0; - * This register is used to configure the divisor for the divider in timer 2. - * - * The least significant eight bits represent the fractional part. - */ - -#define LEDC_CLK_DIV_TIMER2 0x0003FFFF -#define LEDC_CLK_DIV_TIMER2_M (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S) -#define LEDC_CLK_DIV_TIMER2_V 0x0003FFFF -#define LEDC_CLK_DIV_TIMER2_S 4 - -/* LEDC_TIMER2_PAUSE : R/W; bitpos: [22]; default: 0; - * This bit is used to suspend the counter in timer 2. - */ - -#define LEDC_TIMER2_PAUSE (BIT(22)) -#define LEDC_TIMER2_PAUSE_M (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S) -#define LEDC_TIMER2_PAUSE_V 0x00000001 -#define LEDC_TIMER2_PAUSE_S 22 - -/* LEDC_TIMER2_RST : R/W; bitpos: [23]; default: 1; - * This bit is used to reset timer 2. The counter will show 0 after reset. - */ - -#define LEDC_TIMER2_RST (BIT(23)) -#define LEDC_TIMER2_RST_M (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S) -#define LEDC_TIMER2_RST_V 0x00000001 -#define LEDC_TIMER2_RST_S 23 - -/* LEDC_TICK_SEL_TIMER2 : R/W; bitpos: [24]; default: 0; - * This bit is used to select clock for timer 2. When this bit is set to 1 - * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not - * accurate. - * - * 1'h0: SLOW_CLK 1'h1: REF_TICK - */ - -#define LEDC_TICK_SEL_TIMER2 (BIT(24)) -#define LEDC_TICK_SEL_TIMER2_M (LEDC_TICK_SEL_TIMER2_V << LEDC_TICK_SEL_TIMER2_S) -#define LEDC_TICK_SEL_TIMER2_V 0x00000001 -#define LEDC_TICK_SEL_TIMER2_S 24 - -/* LEDC_TIMER2_PARA_UP : WO; bitpos: [25]; default: 0; - * Set this bit to update LEDC_CLK_DIV_TIMER2 and LEDC_TIMER2_DUTY_RES. - */ - -#define LEDC_TIMER2_PARA_UP (BIT(25)) -#define LEDC_TIMER2_PARA_UP_M (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S) -#define LEDC_TIMER2_PARA_UP_V 0x00000001 -#define LEDC_TIMER2_PARA_UP_S 25 - -/* LEDC_TIMER2_VALUE_REG register - * Timer 2 current counter value - */ - -#define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4) - -/* LEDC_TIMER2_CNT : RO; bitpos: [13:0]; default: 0; - * This register stores the current counter value of timer 2. - */ - -#define LEDC_TIMER2_CNT 0x00003FFF -#define LEDC_TIMER2_CNT_M (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S) -#define LEDC_TIMER2_CNT_V 0x00003FFF -#define LEDC_TIMER2_CNT_S 0 - -/* LEDC_TIMER3_CONF_REG register - * Timer 3 configuration - */ - -#define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8) - -/* LEDC_TIMER3_DUTY_RES : R/W; bitpos: [3:0]; default: 0; - * This register is used to control the range of the counter in timer 3. - */ - -#define LEDC_TIMER3_DUTY_RES 0x0000000F -#define LEDC_TIMER3_DUTY_RES_M (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S) -#define LEDC_TIMER3_DUTY_RES_V 0x0000000F -#define LEDC_TIMER3_DUTY_RES_S 0 - -/* LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [21:4]; default: 0; - * This register is used to configure the divisor for the divider in timer 3. - * - * The least significant eight bits represent the fractional part. - */ - -#define LEDC_CLK_DIV_TIMER3 0x0003FFFF -#define LEDC_CLK_DIV_TIMER3_M (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S) -#define LEDC_CLK_DIV_TIMER3_V 0x0003FFFF -#define LEDC_CLK_DIV_TIMER3_S 4 - -/* LEDC_TIMER3_PAUSE : R/W; bitpos: [22]; default: 0; - * This bit is used to suspend the counter in timer 3. - */ - -#define LEDC_TIMER3_PAUSE (BIT(22)) -#define LEDC_TIMER3_PAUSE_M (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S) -#define LEDC_TIMER3_PAUSE_V 0x00000001 -#define LEDC_TIMER3_PAUSE_S 22 - -/* LEDC_TIMER3_RST : R/W; bitpos: [23]; default: 1; - * This bit is used to reset timer 3. The counter will show 0 after reset. - */ - -#define LEDC_TIMER3_RST (BIT(23)) -#define LEDC_TIMER3_RST_M (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S) -#define LEDC_TIMER3_RST_V 0x00000001 -#define LEDC_TIMER3_RST_S 23 - -/* LEDC_TICK_SEL_TIMER3 : R/W; bitpos: [24]; default: 0; - * This bit is used to select clock for timer 3. When this bit is set to 1 - * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not - * accurate. - * - * 1'h0: SLOW_CLK 1'h1: REF_TICK - */ - -#define LEDC_TICK_SEL_TIMER3 (BIT(24)) -#define LEDC_TICK_SEL_TIMER3_M (LEDC_TICK_SEL_TIMER3_V << LEDC_TICK_SEL_TIMER3_S) -#define LEDC_TICK_SEL_TIMER3_V 0x00000001 -#define LEDC_TICK_SEL_TIMER3_S 24 - -/* LEDC_TIMER3_PARA_UP : WO; bitpos: [25]; default: 0; - * Set this bit to update LEDC_CLK_DIV_TIMER3 and LEDC_TIMER3_DUTY_RES. - */ - -#define LEDC_TIMER3_PARA_UP (BIT(25)) -#define LEDC_TIMER3_PARA_UP_M (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S) -#define LEDC_TIMER3_PARA_UP_V 0x00000001 -#define LEDC_TIMER3_PARA_UP_S 25 - -/* LEDC_TIMER3_VALUE_REG register - * Timer 3 current counter value - */ - -#define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc) - -/* LEDC_TIMER3_CNT : RO; bitpos: [13:0]; default: 0; - * This register stores the current counter value of timer 3. - */ - -#define LEDC_TIMER3_CNT 0x00003FFF -#define LEDC_TIMER3_CNT_M (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S) -#define LEDC_TIMER3_CNT_V 0x00003FFF -#define LEDC_TIMER3_CNT_S 0 - -/* LEDC_INT_RAW_REG register - * Raw interrupt status - */ - -#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0xc0) - -/* LEDC_TIMER0_OVF_INT_RAW : RO; bitpos: [0]; default: 0; - * Triggered when the timer0 has reached its maximum counter value. - */ - -#define LEDC_TIMER0_OVF_INT_RAW (BIT(0)) -#define LEDC_TIMER0_OVF_INT_RAW_M (LEDC_TIMER0_OVF_INT_RAW_V << LEDC_TIMER0_OVF_INT_RAW_S) -#define LEDC_TIMER0_OVF_INT_RAW_V 0x00000001 -#define LEDC_TIMER0_OVF_INT_RAW_S 0 - -/* LEDC_TIMER1_OVF_INT_RAW : RO; bitpos: [1]; default: 0; - * Triggered when the timer1 has reached its maximum counter value. - */ - -#define LEDC_TIMER1_OVF_INT_RAW (BIT(1)) -#define LEDC_TIMER1_OVF_INT_RAW_M (LEDC_TIMER1_OVF_INT_RAW_V << LEDC_TIMER1_OVF_INT_RAW_S) -#define LEDC_TIMER1_OVF_INT_RAW_V 0x00000001 -#define LEDC_TIMER1_OVF_INT_RAW_S 1 - -/* LEDC_TIMER2_OVF_INT_RAW : RO; bitpos: [2]; default: 0; - * Triggered when the timer2 has reached its maximum counter value. - */ - -#define LEDC_TIMER2_OVF_INT_RAW (BIT(2)) -#define LEDC_TIMER2_OVF_INT_RAW_M (LEDC_TIMER2_OVF_INT_RAW_V << LEDC_TIMER2_OVF_INT_RAW_S) -#define LEDC_TIMER2_OVF_INT_RAW_V 0x00000001 -#define LEDC_TIMER2_OVF_INT_RAW_S 2 - -/* LEDC_TIMER3_OVF_INT_RAW : RO; bitpos: [3]; default: 0; - * Triggered when the timer3 has reached its maximum counter value. - */ - -#define LEDC_TIMER3_OVF_INT_RAW (BIT(3)) -#define LEDC_TIMER3_OVF_INT_RAW_M (LEDC_TIMER3_OVF_INT_RAW_V << LEDC_TIMER3_OVF_INT_RAW_S) -#define LEDC_TIMER3_OVF_INT_RAW_V 0x00000001 -#define LEDC_TIMER3_OVF_INT_RAW_S 3 - -/* LEDC_DUTY_CHNG_END_CH0_INT_RAW : RO; bitpos: [4]; default: 0; - * Interrupt raw bit for channel 0. Triggered when the gradual change of - * duty has finished. - */ - -#define LEDC_DUTY_CHNG_END_CH0_INT_RAW (BIT(4)) -#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_M (LEDC_DUTY_CHNG_END_CH0_INT_RAW_V << LEDC_DUTY_CHNG_END_CH0_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_S 4 - -/* LEDC_DUTY_CHNG_END_CH1_INT_RAW : RO; bitpos: [5]; default: 0; - * Interrupt raw bit for channel 1. Triggered when the gradual change of - * duty has finished. - */ - -#define LEDC_DUTY_CHNG_END_CH1_INT_RAW (BIT(5)) -#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_M (LEDC_DUTY_CHNG_END_CH1_INT_RAW_V << LEDC_DUTY_CHNG_END_CH1_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_S 5 - -/* LEDC_DUTY_CHNG_END_CH2_INT_RAW : RO; bitpos: [6]; default: 0; - * Interrupt raw bit for channel 2. Triggered when the gradual change of - * duty has finished. - */ - -#define LEDC_DUTY_CHNG_END_CH2_INT_RAW (BIT(6)) -#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_M (LEDC_DUTY_CHNG_END_CH2_INT_RAW_V << LEDC_DUTY_CHNG_END_CH2_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_S 6 - -/* LEDC_DUTY_CHNG_END_CH3_INT_RAW : RO; bitpos: [7]; default: 0; - * Interrupt raw bit for channel 3. Triggered when the gradual change of - * duty has finished. - */ - -#define LEDC_DUTY_CHNG_END_CH3_INT_RAW (BIT(7)) -#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_M (LEDC_DUTY_CHNG_END_CH3_INT_RAW_V << LEDC_DUTY_CHNG_END_CH3_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_S 7 - -/* LEDC_DUTY_CHNG_END_CH4_INT_RAW : RO; bitpos: [8]; default: 0; - * Interrupt raw bit for channel 4. Triggered when the gradual change of - * duty has finished. - */ - -#define LEDC_DUTY_CHNG_END_CH4_INT_RAW (BIT(8)) -#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_M (LEDC_DUTY_CHNG_END_CH4_INT_RAW_V << LEDC_DUTY_CHNG_END_CH4_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_S 8 - -/* LEDC_DUTY_CHNG_END_CH5_INT_RAW : RO; bitpos: [9]; default: 0; - * Interrupt raw bit for channel 5. Triggered when the gradual change of - * duty has finished. - */ - -#define LEDC_DUTY_CHNG_END_CH5_INT_RAW (BIT(9)) -#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_M (LEDC_DUTY_CHNG_END_CH5_INT_RAW_V << LEDC_DUTY_CHNG_END_CH5_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_S 9 - -/* LEDC_DUTY_CHNG_END_CH6_INT_RAW : RO; bitpos: [10]; default: 0; - * Interrupt raw bit for channel 6. Triggered when the gradual change of - * duty has finished. - */ - -#define LEDC_DUTY_CHNG_END_CH6_INT_RAW (BIT(10)) -#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_M (LEDC_DUTY_CHNG_END_CH6_INT_RAW_V << LEDC_DUTY_CHNG_END_CH6_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_S 10 - -/* LEDC_DUTY_CHNG_END_CH7_INT_RAW : RO; bitpos: [11]; default: 0; - * Interrupt raw bit for channel 7. Triggered when the gradual change of - * duty has finished. - */ - -#define LEDC_DUTY_CHNG_END_CH7_INT_RAW (BIT(11)) -#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_M (LEDC_DUTY_CHNG_END_CH7_INT_RAW_V << LEDC_DUTY_CHNG_END_CH7_INT_RAW_S) -#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_S 11 - -/* LEDC_OVF_CNT_CH0_INT_RAW : RO; bitpos: [12]; default: 0; - * Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached - * the value specified by LEDC_OVF_NUM_CH0. - */ - -#define LEDC_OVF_CNT_CH0_INT_RAW (BIT(12)) -#define LEDC_OVF_CNT_CH0_INT_RAW_M (LEDC_OVF_CNT_CH0_INT_RAW_V << LEDC_OVF_CNT_CH0_INT_RAW_S) -#define LEDC_OVF_CNT_CH0_INT_RAW_V 0x00000001 -#define LEDC_OVF_CNT_CH0_INT_RAW_S 12 - -/* LEDC_OVF_CNT_CH1_INT_RAW : RO; bitpos: [13]; default: 0; - * Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached - * the value specified by LEDC_OVF_NUM_CH1. - */ - -#define LEDC_OVF_CNT_CH1_INT_RAW (BIT(13)) -#define LEDC_OVF_CNT_CH1_INT_RAW_M (LEDC_OVF_CNT_CH1_INT_RAW_V << LEDC_OVF_CNT_CH1_INT_RAW_S) -#define LEDC_OVF_CNT_CH1_INT_RAW_V 0x00000001 -#define LEDC_OVF_CNT_CH1_INT_RAW_S 13 - -/* LEDC_OVF_CNT_CH2_INT_RAW : RO; bitpos: [14]; default: 0; - * Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached - * the value specified by LEDC_OVF_NUM_CH2. - */ - -#define LEDC_OVF_CNT_CH2_INT_RAW (BIT(14)) -#define LEDC_OVF_CNT_CH2_INT_RAW_M (LEDC_OVF_CNT_CH2_INT_RAW_V << LEDC_OVF_CNT_CH2_INT_RAW_S) -#define LEDC_OVF_CNT_CH2_INT_RAW_V 0x00000001 -#define LEDC_OVF_CNT_CH2_INT_RAW_S 14 - -/* LEDC_OVF_CNT_CH3_INT_RAW : RO; bitpos: [15]; default: 0; - * Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached - * the value specified by LEDC_OVF_NUM_CH3. - */ - -#define LEDC_OVF_CNT_CH3_INT_RAW (BIT(15)) -#define LEDC_OVF_CNT_CH3_INT_RAW_M (LEDC_OVF_CNT_CH3_INT_RAW_V << LEDC_OVF_CNT_CH3_INT_RAW_S) -#define LEDC_OVF_CNT_CH3_INT_RAW_V 0x00000001 -#define LEDC_OVF_CNT_CH3_INT_RAW_S 15 - -/* LEDC_OVF_CNT_CH4_INT_RAW : RO; bitpos: [16]; default: 0; - * Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached - * the value specified by LEDC_OVF_NUM_CH4. - */ - -#define LEDC_OVF_CNT_CH4_INT_RAW (BIT(16)) -#define LEDC_OVF_CNT_CH4_INT_RAW_M (LEDC_OVF_CNT_CH4_INT_RAW_V << LEDC_OVF_CNT_CH4_INT_RAW_S) -#define LEDC_OVF_CNT_CH4_INT_RAW_V 0x00000001 -#define LEDC_OVF_CNT_CH4_INT_RAW_S 16 - -/* LEDC_OVF_CNT_CH5_INT_RAW : RO; bitpos: [17]; default: 0; - * Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached - * the value specified by LEDC_OVF_NUM_CH5. - */ - -#define LEDC_OVF_CNT_CH5_INT_RAW (BIT(17)) -#define LEDC_OVF_CNT_CH5_INT_RAW_M (LEDC_OVF_CNT_CH5_INT_RAW_V << LEDC_OVF_CNT_CH5_INT_RAW_S) -#define LEDC_OVF_CNT_CH5_INT_RAW_V 0x00000001 -#define LEDC_OVF_CNT_CH5_INT_RAW_S 17 - -/* LEDC_OVF_CNT_CH6_INT_RAW : RO; bitpos: [18]; default: 0; - * Interrupt raw bit for channel 6. Triggered when the ovf_cnt has reached - * the value specified by LEDC_OVF_NUM_CH6. - */ - -#define LEDC_OVF_CNT_CH6_INT_RAW (BIT(18)) -#define LEDC_OVF_CNT_CH6_INT_RAW_M (LEDC_OVF_CNT_CH6_INT_RAW_V << LEDC_OVF_CNT_CH6_INT_RAW_S) -#define LEDC_OVF_CNT_CH6_INT_RAW_V 0x00000001 -#define LEDC_OVF_CNT_CH6_INT_RAW_S 18 - -/* LEDC_OVF_CNT_CH7_INT_RAW : RO; bitpos: [19]; default: 0; - * Interrupt raw bit for channel 7. Triggered when the ovf_cnt has reached - * the value specified by LEDC_OVF_NUM_CH7. - */ - -#define LEDC_OVF_CNT_CH7_INT_RAW (BIT(19)) -#define LEDC_OVF_CNT_CH7_INT_RAW_M (LEDC_OVF_CNT_CH7_INT_RAW_V << LEDC_OVF_CNT_CH7_INT_RAW_S) -#define LEDC_OVF_CNT_CH7_INT_RAW_V 0x00000001 -#define LEDC_OVF_CNT_CH7_INT_RAW_S 19 - -/* LEDC_INT_ST_REG register - * Masked interrupt status - */ - -#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0xc4) - -/* LEDC_TIMER0_OVF_INT_ST : RO; bitpos: [0]; default: 0; - * This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT - * interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1. - */ - -#define LEDC_TIMER0_OVF_INT_ST (BIT(0)) -#define LEDC_TIMER0_OVF_INT_ST_M (LEDC_TIMER0_OVF_INT_ST_V << LEDC_TIMER0_OVF_INT_ST_S) -#define LEDC_TIMER0_OVF_INT_ST_V 0x00000001 -#define LEDC_TIMER0_OVF_INT_ST_S 0 - -/* LEDC_TIMER1_OVF_INT_ST : RO; bitpos: [1]; default: 0; - * This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT - * interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1. - */ - -#define LEDC_TIMER1_OVF_INT_ST (BIT(1)) -#define LEDC_TIMER1_OVF_INT_ST_M (LEDC_TIMER1_OVF_INT_ST_V << LEDC_TIMER1_OVF_INT_ST_S) -#define LEDC_TIMER1_OVF_INT_ST_V 0x00000001 -#define LEDC_TIMER1_OVF_INT_ST_S 1 - -/* LEDC_TIMER2_OVF_INT_ST : RO; bitpos: [2]; default: 0; - * This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT - * interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1. - */ - -#define LEDC_TIMER2_OVF_INT_ST (BIT(2)) -#define LEDC_TIMER2_OVF_INT_ST_M (LEDC_TIMER2_OVF_INT_ST_V << LEDC_TIMER2_OVF_INT_ST_S) -#define LEDC_TIMER2_OVF_INT_ST_V 0x00000001 -#define LEDC_TIMER2_OVF_INT_ST_S 2 - -/* LEDC_TIMER3_OVF_INT_ST : RO; bitpos: [3]; default: 0; - * This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT - * interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1. - */ - -#define LEDC_TIMER3_OVF_INT_ST (BIT(3)) -#define LEDC_TIMER3_OVF_INT_ST_M (LEDC_TIMER3_OVF_INT_ST_V << LEDC_TIMER3_OVF_INT_ST_S) -#define LEDC_TIMER3_OVF_INT_ST_V 0x00000001 -#define LEDC_TIMER3_OVF_INT_ST_S 3 - -/* LEDC_DUTY_CHNG_END_CH0_INT_ST : RO; bitpos: [4]; default: 0; - * This is the masked interrupt status bit for the - * LEDC_DUTY_CHNG_END_CH0_INT interrupt when - * LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1. - */ - -#define LEDC_DUTY_CHNG_END_CH0_INT_ST (BIT(4)) -#define LEDC_DUTY_CHNG_END_CH0_INT_ST_M (LEDC_DUTY_CHNG_END_CH0_INT_ST_V << LEDC_DUTY_CHNG_END_CH0_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH0_INT_ST_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH0_INT_ST_S 4 - -/* LEDC_DUTY_CHNG_END_CH1_INT_ST : RO; bitpos: [5]; default: 0; - * This is the masked interrupt status bit for the - * LEDC_DUTY_CHNG_END_CH1_INT interrupt when - * LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1. - */ - -#define LEDC_DUTY_CHNG_END_CH1_INT_ST (BIT(5)) -#define LEDC_DUTY_CHNG_END_CH1_INT_ST_M (LEDC_DUTY_CHNG_END_CH1_INT_ST_V << LEDC_DUTY_CHNG_END_CH1_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH1_INT_ST_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH1_INT_ST_S 5 - -/* LEDC_DUTY_CHNG_END_CH2_INT_ST : RO; bitpos: [6]; default: 0; - * This is the masked interrupt status bit for the - * LEDC_DUTY_CHNG_END_CH2_INT interrupt when - * LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1. - */ - -#define LEDC_DUTY_CHNG_END_CH2_INT_ST (BIT(6)) -#define LEDC_DUTY_CHNG_END_CH2_INT_ST_M (LEDC_DUTY_CHNG_END_CH2_INT_ST_V << LEDC_DUTY_CHNG_END_CH2_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH2_INT_ST_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH2_INT_ST_S 6 - -/* LEDC_DUTY_CHNG_END_CH3_INT_ST : RO; bitpos: [7]; default: 0; - * This is the masked interrupt status bit for the - * LEDC_DUTY_CHNG_END_CH3_INT interrupt when - * LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1. - */ - -#define LEDC_DUTY_CHNG_END_CH3_INT_ST (BIT(7)) -#define LEDC_DUTY_CHNG_END_CH3_INT_ST_M (LEDC_DUTY_CHNG_END_CH3_INT_ST_V << LEDC_DUTY_CHNG_END_CH3_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH3_INT_ST_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH3_INT_ST_S 7 - -/* LEDC_DUTY_CHNG_END_CH4_INT_ST : RO; bitpos: [8]; default: 0; - * This is the masked interrupt status bit for the - * LEDC_DUTY_CHNG_END_CH4_INT interrupt when - * LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1. - */ - -#define LEDC_DUTY_CHNG_END_CH4_INT_ST (BIT(8)) -#define LEDC_DUTY_CHNG_END_CH4_INT_ST_M (LEDC_DUTY_CHNG_END_CH4_INT_ST_V << LEDC_DUTY_CHNG_END_CH4_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH4_INT_ST_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH4_INT_ST_S 8 - -/* LEDC_DUTY_CHNG_END_CH5_INT_ST : RO; bitpos: [9]; default: 0; - * This is the masked interrupt status bit for the - * LEDC_DUTY_CHNG_END_CH5_INT interrupt when - * LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1. - */ - -#define LEDC_DUTY_CHNG_END_CH5_INT_ST (BIT(9)) -#define LEDC_DUTY_CHNG_END_CH5_INT_ST_M (LEDC_DUTY_CHNG_END_CH5_INT_ST_V << LEDC_DUTY_CHNG_END_CH5_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH5_INT_ST_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH5_INT_ST_S 9 - -/* LEDC_DUTY_CHNG_END_CH6_INT_ST : RO; bitpos: [10]; default: 0; - * This is the masked interrupt status bit for the - * LEDC_DUTY_CHNG_END_CH6_INT interrupt when - * LEDC_DUTY_CHNG_END_CH6_INT_ENAIS set to 1. - */ - -#define LEDC_DUTY_CHNG_END_CH6_INT_ST (BIT(10)) -#define LEDC_DUTY_CHNG_END_CH6_INT_ST_M (LEDC_DUTY_CHNG_END_CH6_INT_ST_V << LEDC_DUTY_CHNG_END_CH6_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH6_INT_ST_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH6_INT_ST_S 10 - -/* LEDC_DUTY_CHNG_END_CH7_INT_ST : RO; bitpos: [11]; default: 0; - * This is the masked interrupt status bit for the - * LEDC_DUTY_CHNG_END_CH7_INT interrupt when - * LEDC_DUTY_CHNG_END_CH7_INT_ENAIS set to 1. - */ - -#define LEDC_DUTY_CHNG_END_CH7_INT_ST (BIT(11)) -#define LEDC_DUTY_CHNG_END_CH7_INT_ST_M (LEDC_DUTY_CHNG_END_CH7_INT_ST_V << LEDC_DUTY_CHNG_END_CH7_INT_ST_S) -#define LEDC_DUTY_CHNG_END_CH7_INT_ST_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH7_INT_ST_S 11 - -/* LEDC_OVF_CNT_CH0_INT_ST : RO; bitpos: [12]; default: 0; - * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT - * interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1. - */ - -#define LEDC_OVF_CNT_CH0_INT_ST (BIT(12)) -#define LEDC_OVF_CNT_CH0_INT_ST_M (LEDC_OVF_CNT_CH0_INT_ST_V << LEDC_OVF_CNT_CH0_INT_ST_S) -#define LEDC_OVF_CNT_CH0_INT_ST_V 0x00000001 -#define LEDC_OVF_CNT_CH0_INT_ST_S 12 - -/* LEDC_OVF_CNT_CH1_INT_ST : RO; bitpos: [13]; default: 0; - * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT - * interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1. - */ - -#define LEDC_OVF_CNT_CH1_INT_ST (BIT(13)) -#define LEDC_OVF_CNT_CH1_INT_ST_M (LEDC_OVF_CNT_CH1_INT_ST_V << LEDC_OVF_CNT_CH1_INT_ST_S) -#define LEDC_OVF_CNT_CH1_INT_ST_V 0x00000001 -#define LEDC_OVF_CNT_CH1_INT_ST_S 13 - -/* LEDC_OVF_CNT_CH2_INT_ST : RO; bitpos: [14]; default: 0; - * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT - * interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1. - */ - -#define LEDC_OVF_CNT_CH2_INT_ST (BIT(14)) -#define LEDC_OVF_CNT_CH2_INT_ST_M (LEDC_OVF_CNT_CH2_INT_ST_V << LEDC_OVF_CNT_CH2_INT_ST_S) -#define LEDC_OVF_CNT_CH2_INT_ST_V 0x00000001 -#define LEDC_OVF_CNT_CH2_INT_ST_S 14 - -/* LEDC_OVF_CNT_CH3_INT_ST : RO; bitpos: [15]; default: 0; - * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT - * interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1. - */ - -#define LEDC_OVF_CNT_CH3_INT_ST (BIT(15)) -#define LEDC_OVF_CNT_CH3_INT_ST_M (LEDC_OVF_CNT_CH3_INT_ST_V << LEDC_OVF_CNT_CH3_INT_ST_S) -#define LEDC_OVF_CNT_CH3_INT_ST_V 0x00000001 -#define LEDC_OVF_CNT_CH3_INT_ST_S 15 - -/* LEDC_OVF_CNT_CH4_INT_ST : RO; bitpos: [16]; default: 0; - * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT - * interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1. - */ - -#define LEDC_OVF_CNT_CH4_INT_ST (BIT(16)) -#define LEDC_OVF_CNT_CH4_INT_ST_M (LEDC_OVF_CNT_CH4_INT_ST_V << LEDC_OVF_CNT_CH4_INT_ST_S) -#define LEDC_OVF_CNT_CH4_INT_ST_V 0x00000001 -#define LEDC_OVF_CNT_CH4_INT_ST_S 16 - -/* LEDC_OVF_CNT_CH5_INT_ST : RO; bitpos: [17]; default: 0; - * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT - * interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1. - */ - -#define LEDC_OVF_CNT_CH5_INT_ST (BIT(17)) -#define LEDC_OVF_CNT_CH5_INT_ST_M (LEDC_OVF_CNT_CH5_INT_ST_V << LEDC_OVF_CNT_CH5_INT_ST_S) -#define LEDC_OVF_CNT_CH5_INT_ST_V 0x00000001 -#define LEDC_OVF_CNT_CH5_INT_ST_S 17 - -/* LEDC_OVF_CNT_CH6_INT_ST : RO; bitpos: [18]; default: 0; - * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH6_INT - * interrupt when LEDC_OVF_CNT_CH6_INT_ENA is set to 1. - */ - -#define LEDC_OVF_CNT_CH6_INT_ST (BIT(18)) -#define LEDC_OVF_CNT_CH6_INT_ST_M (LEDC_OVF_CNT_CH6_INT_ST_V << LEDC_OVF_CNT_CH6_INT_ST_S) -#define LEDC_OVF_CNT_CH6_INT_ST_V 0x00000001 -#define LEDC_OVF_CNT_CH6_INT_ST_S 18 - -/* LEDC_OVF_CNT_CH7_INT_ST : RO; bitpos: [19]; default: 0; - * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH7_INT - * interrupt when LEDC_OVF_CNT_CH7_INT_ENA is set to 1. - */ - -#define LEDC_OVF_CNT_CH7_INT_ST (BIT(19)) -#define LEDC_OVF_CNT_CH7_INT_ST_M (LEDC_OVF_CNT_CH7_INT_ST_V << LEDC_OVF_CNT_CH7_INT_ST_S) -#define LEDC_OVF_CNT_CH7_INT_ST_V 0x00000001 -#define LEDC_OVF_CNT_CH7_INT_ST_S 19 - -/* LEDC_INT_ENA_REG register - * Interrupt enable bits - */ - -#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xc8) - -/* LEDC_TIMER0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0; - * The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt. - */ - -#define LEDC_TIMER0_OVF_INT_ENA (BIT(0)) -#define LEDC_TIMER0_OVF_INT_ENA_M (LEDC_TIMER0_OVF_INT_ENA_V << LEDC_TIMER0_OVF_INT_ENA_S) -#define LEDC_TIMER0_OVF_INT_ENA_V 0x00000001 -#define LEDC_TIMER0_OVF_INT_ENA_S 0 - -/* LEDC_TIMER1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0; - * The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt. - */ - -#define LEDC_TIMER1_OVF_INT_ENA (BIT(1)) -#define LEDC_TIMER1_OVF_INT_ENA_M (LEDC_TIMER1_OVF_INT_ENA_V << LEDC_TIMER1_OVF_INT_ENA_S) -#define LEDC_TIMER1_OVF_INT_ENA_V 0x00000001 -#define LEDC_TIMER1_OVF_INT_ENA_S 1 - -/* LEDC_TIMER2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0; - * The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt. - */ - -#define LEDC_TIMER2_OVF_INT_ENA (BIT(2)) -#define LEDC_TIMER2_OVF_INT_ENA_M (LEDC_TIMER2_OVF_INT_ENA_V << LEDC_TIMER2_OVF_INT_ENA_S) -#define LEDC_TIMER2_OVF_INT_ENA_V 0x00000001 -#define LEDC_TIMER2_OVF_INT_ENA_S 2 - -/* LEDC_TIMER3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0; - * The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt. - */ - -#define LEDC_TIMER3_OVF_INT_ENA (BIT(3)) -#define LEDC_TIMER3_OVF_INT_ENA_M (LEDC_TIMER3_OVF_INT_ENA_V << LEDC_TIMER3_OVF_INT_ENA_S) -#define LEDC_TIMER3_OVF_INT_ENA_V 0x00000001 -#define LEDC_TIMER3_OVF_INT_ENA_S 3 - -/* LEDC_DUTY_CHNG_END_CH0_INT_ENA : R/W; bitpos: [4]; default: 0; - * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt. - */ - -#define LEDC_DUTY_CHNG_END_CH0_INT_ENA (BIT(4)) -#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_M (LEDC_DUTY_CHNG_END_CH0_INT_ENA_V << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_S 4 - -/* LEDC_DUTY_CHNG_END_CH1_INT_ENA : R/W; bitpos: [5]; default: 0; - * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt. - */ - -#define LEDC_DUTY_CHNG_END_CH1_INT_ENA (BIT(5)) -#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_M (LEDC_DUTY_CHNG_END_CH1_INT_ENA_V << LEDC_DUTY_CHNG_END_CH1_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_S 5 - -/* LEDC_DUTY_CHNG_END_CH2_INT_ENA : R/W; bitpos: [6]; default: 0; - * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt. - */ - -#define LEDC_DUTY_CHNG_END_CH2_INT_ENA (BIT(6)) -#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_M (LEDC_DUTY_CHNG_END_CH2_INT_ENA_V << LEDC_DUTY_CHNG_END_CH2_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_S 6 - -/* LEDC_DUTY_CHNG_END_CH3_INT_ENA : R/W; bitpos: [7]; default: 0; - * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt. - */ - -#define LEDC_DUTY_CHNG_END_CH3_INT_ENA (BIT(7)) -#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_M (LEDC_DUTY_CHNG_END_CH3_INT_ENA_V << LEDC_DUTY_CHNG_END_CH3_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_S 7 - -/* LEDC_DUTY_CHNG_END_CH4_INT_ENA : R/W; bitpos: [8]; default: 0; - * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt. - */ - -#define LEDC_DUTY_CHNG_END_CH4_INT_ENA (BIT(8)) -#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_M (LEDC_DUTY_CHNG_END_CH4_INT_ENA_V << LEDC_DUTY_CHNG_END_CH4_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_S 8 - -/* LEDC_DUTY_CHNG_END_CH5_INT_ENA : R/W; bitpos: [9]; default: 0; - * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt. - */ - -#define LEDC_DUTY_CHNG_END_CH5_INT_ENA (BIT(9)) -#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_M (LEDC_DUTY_CHNG_END_CH5_INT_ENA_V << LEDC_DUTY_CHNG_END_CH5_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_S 9 - -/* LEDC_DUTY_CHNG_END_CH6_INT_ENA : R/W; bitpos: [10]; default: 0; - * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt. - */ - -#define LEDC_DUTY_CHNG_END_CH6_INT_ENA (BIT(10)) -#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_M (LEDC_DUTY_CHNG_END_CH6_INT_ENA_V << LEDC_DUTY_CHNG_END_CH6_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_S 10 - -/* LEDC_DUTY_CHNG_END_CH7_INT_ENA : R/W; bitpos: [11]; default: 0; - * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt. - */ - -#define LEDC_DUTY_CHNG_END_CH7_INT_ENA (BIT(11)) -#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_M (LEDC_DUTY_CHNG_END_CH7_INT_ENA_V << LEDC_DUTY_CHNG_END_CH7_INT_ENA_S) -#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_S 11 - -/* LEDC_OVF_CNT_CH0_INT_ENA : R/W; bitpos: [12]; default: 0; - * The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt. - */ - -#define LEDC_OVF_CNT_CH0_INT_ENA (BIT(12)) -#define LEDC_OVF_CNT_CH0_INT_ENA_M (LEDC_OVF_CNT_CH0_INT_ENA_V << LEDC_OVF_CNT_CH0_INT_ENA_S) -#define LEDC_OVF_CNT_CH0_INT_ENA_V 0x00000001 -#define LEDC_OVF_CNT_CH0_INT_ENA_S 12 - -/* LEDC_OVF_CNT_CH1_INT_ENA : R/W; bitpos: [13]; default: 0; - * The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt. - */ - -#define LEDC_OVF_CNT_CH1_INT_ENA (BIT(13)) -#define LEDC_OVF_CNT_CH1_INT_ENA_M (LEDC_OVF_CNT_CH1_INT_ENA_V << LEDC_OVF_CNT_CH1_INT_ENA_S) -#define LEDC_OVF_CNT_CH1_INT_ENA_V 0x00000001 -#define LEDC_OVF_CNT_CH1_INT_ENA_S 13 - -/* LEDC_OVF_CNT_CH2_INT_ENA : R/W; bitpos: [14]; default: 0; - * The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt. - */ - -#define LEDC_OVF_CNT_CH2_INT_ENA (BIT(14)) -#define LEDC_OVF_CNT_CH2_INT_ENA_M (LEDC_OVF_CNT_CH2_INT_ENA_V << LEDC_OVF_CNT_CH2_INT_ENA_S) -#define LEDC_OVF_CNT_CH2_INT_ENA_V 0x00000001 -#define LEDC_OVF_CNT_CH2_INT_ENA_S 14 - -/* LEDC_OVF_CNT_CH3_INT_ENA : R/W; bitpos: [15]; default: 0; - * The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt. - */ - -#define LEDC_OVF_CNT_CH3_INT_ENA (BIT(15)) -#define LEDC_OVF_CNT_CH3_INT_ENA_M (LEDC_OVF_CNT_CH3_INT_ENA_V << LEDC_OVF_CNT_CH3_INT_ENA_S) -#define LEDC_OVF_CNT_CH3_INT_ENA_V 0x00000001 -#define LEDC_OVF_CNT_CH3_INT_ENA_S 15 - -/* LEDC_OVF_CNT_CH4_INT_ENA : R/W; bitpos: [16]; default: 0; - * The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt. - */ - -#define LEDC_OVF_CNT_CH4_INT_ENA (BIT(16)) -#define LEDC_OVF_CNT_CH4_INT_ENA_M (LEDC_OVF_CNT_CH4_INT_ENA_V << LEDC_OVF_CNT_CH4_INT_ENA_S) -#define LEDC_OVF_CNT_CH4_INT_ENA_V 0x00000001 -#define LEDC_OVF_CNT_CH4_INT_ENA_S 16 - -/* LEDC_OVF_CNT_CH5_INT_ENA : R/W; bitpos: [17]; default: 0; - * The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt. - */ - -#define LEDC_OVF_CNT_CH5_INT_ENA (BIT(17)) -#define LEDC_OVF_CNT_CH5_INT_ENA_M (LEDC_OVF_CNT_CH5_INT_ENA_V << LEDC_OVF_CNT_CH5_INT_ENA_S) -#define LEDC_OVF_CNT_CH5_INT_ENA_V 0x00000001 -#define LEDC_OVF_CNT_CH5_INT_ENA_S 17 - -/* LEDC_OVF_CNT_CH6_INT_ENA : R/W; bitpos: [18]; default: 0; - * The interrupt enable bit for the LEDC_OVF_CNT_CH6_INT interrupt. - */ - -#define LEDC_OVF_CNT_CH6_INT_ENA (BIT(18)) -#define LEDC_OVF_CNT_CH6_INT_ENA_M (LEDC_OVF_CNT_CH6_INT_ENA_V << LEDC_OVF_CNT_CH6_INT_ENA_S) -#define LEDC_OVF_CNT_CH6_INT_ENA_V 0x00000001 -#define LEDC_OVF_CNT_CH6_INT_ENA_S 18 - -/* LEDC_OVF_CNT_CH7_INT_ENA : R/W; bitpos: [19]; default: 0; - * The interrupt enable bit for the LEDC_OVF_CNT_CH7_INT interrupt. - */ - -#define LEDC_OVF_CNT_CH7_INT_ENA (BIT(19)) -#define LEDC_OVF_CNT_CH7_INT_ENA_M (LEDC_OVF_CNT_CH7_INT_ENA_V << LEDC_OVF_CNT_CH7_INT_ENA_S) -#define LEDC_OVF_CNT_CH7_INT_ENA_V 0x00000001 -#define LEDC_OVF_CNT_CH7_INT_ENA_S 19 - -/* LEDC_INT_CLR_REG register - * Interrupt clear bits - */ - -#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xcc) - -/* LEDC_TIMER0_OVF_INT_CLR : WO; bitpos: [0]; default: 0; - * Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt. - */ - -#define LEDC_TIMER0_OVF_INT_CLR (BIT(0)) -#define LEDC_TIMER0_OVF_INT_CLR_M (LEDC_TIMER0_OVF_INT_CLR_V << LEDC_TIMER0_OVF_INT_CLR_S) -#define LEDC_TIMER0_OVF_INT_CLR_V 0x00000001 -#define LEDC_TIMER0_OVF_INT_CLR_S 0 - -/* LEDC_TIMER1_OVF_INT_CLR : WO; bitpos: [1]; default: 0; - * Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt. - */ - -#define LEDC_TIMER1_OVF_INT_CLR (BIT(1)) -#define LEDC_TIMER1_OVF_INT_CLR_M (LEDC_TIMER1_OVF_INT_CLR_V << LEDC_TIMER1_OVF_INT_CLR_S) -#define LEDC_TIMER1_OVF_INT_CLR_V 0x00000001 -#define LEDC_TIMER1_OVF_INT_CLR_S 1 - -/* LEDC_TIMER2_OVF_INT_CLR : WO; bitpos: [2]; default: 0; - * Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt. - */ - -#define LEDC_TIMER2_OVF_INT_CLR (BIT(2)) -#define LEDC_TIMER2_OVF_INT_CLR_M (LEDC_TIMER2_OVF_INT_CLR_V << LEDC_TIMER2_OVF_INT_CLR_S) -#define LEDC_TIMER2_OVF_INT_CLR_V 0x00000001 -#define LEDC_TIMER2_OVF_INT_CLR_S 2 - -/* LEDC_TIMER3_OVF_INT_CLR : WO; bitpos: [3]; default: 0; - * Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt. - */ - -#define LEDC_TIMER3_OVF_INT_CLR (BIT(3)) -#define LEDC_TIMER3_OVF_INT_CLR_M (LEDC_TIMER3_OVF_INT_CLR_V << LEDC_TIMER3_OVF_INT_CLR_S) -#define LEDC_TIMER3_OVF_INT_CLR_V 0x00000001 -#define LEDC_TIMER3_OVF_INT_CLR_S 3 - -/* LEDC_DUTY_CHNG_END_CH0_INT_CLR : WO; bitpos: [4]; default: 0; - * Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt. - */ - -#define LEDC_DUTY_CHNG_END_CH0_INT_CLR (BIT(4)) -#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_M (LEDC_DUTY_CHNG_END_CH0_INT_CLR_V << LEDC_DUTY_CHNG_END_CH0_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_S 4 - -/* LEDC_DUTY_CHNG_END_CH1_INT_CLR : WO; bitpos: [5]; default: 0; - * Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt. - */ - -#define LEDC_DUTY_CHNG_END_CH1_INT_CLR (BIT(5)) -#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_M (LEDC_DUTY_CHNG_END_CH1_INT_CLR_V << LEDC_DUTY_CHNG_END_CH1_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_S 5 - -/* LEDC_DUTY_CHNG_END_CH2_INT_CLR : WO; bitpos: [6]; default: 0; - * Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt. - */ - -#define LEDC_DUTY_CHNG_END_CH2_INT_CLR (BIT(6)) -#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_M (LEDC_DUTY_CHNG_END_CH2_INT_CLR_V << LEDC_DUTY_CHNG_END_CH2_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_S 6 - -/* LEDC_DUTY_CHNG_END_CH3_INT_CLR : WO; bitpos: [7]; default: 0; - * Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt. - */ - -#define LEDC_DUTY_CHNG_END_CH3_INT_CLR (BIT(7)) -#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_M (LEDC_DUTY_CHNG_END_CH3_INT_CLR_V << LEDC_DUTY_CHNG_END_CH3_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_S 7 - -/* LEDC_DUTY_CHNG_END_CH4_INT_CLR : WO; bitpos: [8]; default: 0; - * Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt. - */ - -#define LEDC_DUTY_CHNG_END_CH4_INT_CLR (BIT(8)) -#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_M (LEDC_DUTY_CHNG_END_CH4_INT_CLR_V << LEDC_DUTY_CHNG_END_CH4_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_S 8 - -/* LEDC_DUTY_CHNG_END_CH5_INT_CLR : WO; bitpos: [9]; default: 0; - * Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt. - */ - -#define LEDC_DUTY_CHNG_END_CH5_INT_CLR (BIT(9)) -#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_M (LEDC_DUTY_CHNG_END_CH5_INT_CLR_V << LEDC_DUTY_CHNG_END_CH5_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_S 9 - -/* LEDC_DUTY_CHNG_END_CH6_INT_CLR : WO; bitpos: [10]; default: 0; - * Set this bit to clear the LEDC_DUTY_CHNG_END_CH6_INT interrupt. - */ - -#define LEDC_DUTY_CHNG_END_CH6_INT_CLR (BIT(10)) -#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_M (LEDC_DUTY_CHNG_END_CH6_INT_CLR_V << LEDC_DUTY_CHNG_END_CH6_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_S 10 - -/* LEDC_DUTY_CHNG_END_CH7_INT_CLR : WO; bitpos: [11]; default: 0; - * Set this bit to clear the LEDC_DUTY_CHNG_END_CH7_INT interrupt. - */ - -#define LEDC_DUTY_CHNG_END_CH7_INT_CLR (BIT(11)) -#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_M (LEDC_DUTY_CHNG_END_CH7_INT_CLR_V << LEDC_DUTY_CHNG_END_CH7_INT_CLR_S) -#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_V 0x00000001 -#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_S 11 - -/* LEDC_OVF_CNT_CH0_INT_CLR : WO; bitpos: [12]; default: 0; - * Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt. - */ - -#define LEDC_OVF_CNT_CH0_INT_CLR (BIT(12)) -#define LEDC_OVF_CNT_CH0_INT_CLR_M (LEDC_OVF_CNT_CH0_INT_CLR_V << LEDC_OVF_CNT_CH0_INT_CLR_S) -#define LEDC_OVF_CNT_CH0_INT_CLR_V 0x00000001 -#define LEDC_OVF_CNT_CH0_INT_CLR_S 12 - -/* LEDC_OVF_CNT_CH1_INT_CLR : WO; bitpos: [13]; default: 0; - * Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt. - */ - -#define LEDC_OVF_CNT_CH1_INT_CLR (BIT(13)) -#define LEDC_OVF_CNT_CH1_INT_CLR_M (LEDC_OVF_CNT_CH1_INT_CLR_V << LEDC_OVF_CNT_CH1_INT_CLR_S) -#define LEDC_OVF_CNT_CH1_INT_CLR_V 0x00000001 -#define LEDC_OVF_CNT_CH1_INT_CLR_S 13 - -/* LEDC_OVF_CNT_CH2_INT_CLR : WO; bitpos: [14]; default: 0; - * Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt. - */ - -#define LEDC_OVF_CNT_CH2_INT_CLR (BIT(14)) -#define LEDC_OVF_CNT_CH2_INT_CLR_M (LEDC_OVF_CNT_CH2_INT_CLR_V << LEDC_OVF_CNT_CH2_INT_CLR_S) -#define LEDC_OVF_CNT_CH2_INT_CLR_V 0x00000001 -#define LEDC_OVF_CNT_CH2_INT_CLR_S 14 - -/* LEDC_OVF_CNT_CH3_INT_CLR : WO; bitpos: [15]; default: 0; - * Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt. - */ - -#define LEDC_OVF_CNT_CH3_INT_CLR (BIT(15)) -#define LEDC_OVF_CNT_CH3_INT_CLR_M (LEDC_OVF_CNT_CH3_INT_CLR_V << LEDC_OVF_CNT_CH3_INT_CLR_S) -#define LEDC_OVF_CNT_CH3_INT_CLR_V 0x00000001 -#define LEDC_OVF_CNT_CH3_INT_CLR_S 15 - -/* LEDC_OVF_CNT_CH4_INT_CLR : WO; bitpos: [16]; default: 0; - * Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt. - */ - -#define LEDC_OVF_CNT_CH4_INT_CLR (BIT(16)) -#define LEDC_OVF_CNT_CH4_INT_CLR_M (LEDC_OVF_CNT_CH4_INT_CLR_V << LEDC_OVF_CNT_CH4_INT_CLR_S) -#define LEDC_OVF_CNT_CH4_INT_CLR_V 0x00000001 -#define LEDC_OVF_CNT_CH4_INT_CLR_S 16 - -/* LEDC_OVF_CNT_CH5_INT_CLR : WO; bitpos: [17]; default: 0; - * Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt. - */ - -#define LEDC_OVF_CNT_CH5_INT_CLR (BIT(17)) -#define LEDC_OVF_CNT_CH5_INT_CLR_M (LEDC_OVF_CNT_CH5_INT_CLR_V << LEDC_OVF_CNT_CH5_INT_CLR_S) -#define LEDC_OVF_CNT_CH5_INT_CLR_V 0x00000001 -#define LEDC_OVF_CNT_CH5_INT_CLR_S 17 - -/* LEDC_OVF_CNT_CH6_INT_CLR : WO; bitpos: [18]; default: 0; - * Set this bit to clear the LEDC_OVF_CNT_CH6_INT interrupt. - */ - -#define LEDC_OVF_CNT_CH6_INT_CLR (BIT(18)) -#define LEDC_OVF_CNT_CH6_INT_CLR_M (LEDC_OVF_CNT_CH6_INT_CLR_V << LEDC_OVF_CNT_CH6_INT_CLR_S) -#define LEDC_OVF_CNT_CH6_INT_CLR_V 0x00000001 -#define LEDC_OVF_CNT_CH6_INT_CLR_S 18 - -/* LEDC_OVF_CNT_CH7_INT_CLR : WO; bitpos: [19]; default: 0; - * Set this bit to clear the LEDC_OVF_CNT_CH7_INT interrupt. - */ - -#define LEDC_OVF_CNT_CH7_INT_CLR (BIT(19)) -#define LEDC_OVF_CNT_CH7_INT_CLR_M (LEDC_OVF_CNT_CH7_INT_CLR_V << LEDC_OVF_CNT_CH7_INT_CLR_S) -#define LEDC_OVF_CNT_CH7_INT_CLR_V 0x00000001 -#define LEDC_OVF_CNT_CH7_INT_CLR_S 19 - -/* LEDC_CONF_REG register - * Global ledc configuration register - */ - -#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0xd0) - -/* LEDC_APB_CLK_SEL : R/W; bitpos: [1:0]; default: 0; - * This bit is used to select clock source for the 4 timers . - * - * 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK - */ - -#define LEDC_APB_CLK_SEL 0x00000003 -#define LEDC_APB_CLK_SEL_M (LEDC_APB_CLK_SEL_V << LEDC_APB_CLK_SEL_S) -#define LEDC_APB_CLK_SEL_V 0x00000003 -#define LEDC_APB_CLK_SEL_S 0 - -/* LEDC_CLK_EN : R/W; bitpos: [31]; default: 0; - * This bit is used to control clock. - * - * 1'b1: Force clock on for register. 1'h0: Support clock only when - * application writes registers. - */ - -#define LEDC_CLK_EN (BIT(31)) -#define LEDC_CLK_EN_M (LEDC_CLK_EN_V << LEDC_CLK_EN_S) -#define LEDC_CLK_EN_V 0x00000001 -#define LEDC_CLK_EN_S 31 - -/* LEDC_DATE_REG register - * Version control register - */ - -#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0xfc) - -/* LEDC_DATE : R/W; bitpos: [31:0]; default: 419898881; - * This is the version control register. - */ - -#define LEDC_DATE 0xFFFFFFFF -#define LEDC_DATE_M (LEDC_DATE_V << LEDC_DATE_S) -#define LEDC_DATE_V 0xFFFFFFFF -#define LEDC_DATE_S 0 - -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_LEDC_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_memorymap.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_memorymap.h deleted file mode 100644 index c9cf552438a9b..0000000000000 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_memorymap.h +++ /dev/null @@ -1,72 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_memorymap.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_MEMORYMAP_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_MEMORYMAP_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ESP32C3_SYSTEM_BASE 0x600c0000 -#define ESP32C3_SENSITIVE_BASE 0x600c1000 -#define ESP32C3_INTERRUPT_BASE 0x600c2000 -#define ESP32C3_DMA_COPY_BASE 0x600c3000 -#define ESP32C3_EXTMEM_BASE 0x600c4000 -#define ESP32C3_MMU_TABLE 0x600c5000 -#define ESP32C3_AES_BASE 0x6003a000 -#define ESP32C3_SHA_BASE 0x6003b000 -#define ESP32C3_RSA_BASE 0x6003c000 -#define ESP32C3_HMAC_BASE 0x6003e000 -#define ESP32C3_DIGITAL_SIGNATURE_BASE 0x6003d000 -#define ESP32C3_GDMA_BASE 0x6003f000 -#define ESP32C3_ASSIST_DEBUG_BASE 0x600ce000 -#define ESP32C3_DEDICATED_GPIO_BASE 0x600cf000 -#define ESP32C3_WORLD_CNTL_BASE 0x600d0000 -#define ESP32C3_DPORT_END 0x600d3ffc -#define ESP32C3_UART_BASE 0x60000000 -#define ESP32C3_SPI1_BASE 0x60002000 -#define ESP32C3_SPI0_BASE 0x60003000 -#define ESP32C3_GPIO_BASE 0x60004000 -#define ESP32C3_FE2_BASE 0x60005000 -#define ESP32C3_FE_BASE 0x60006000 -#define ESP32C3_RTCCNTL_BASE 0x60008000 -#define ESP32C3_IO_MUX_BASE 0x60009000 -#define ESP32C3_RTC_I2C_BASE 0x6000e000 -#define ESP32C3_UART1_BASE 0x60010000 -#define ESP32C3_I2C_EXT_BASE 0x60013000 -#define ESP32C3_UHCI0_BASE 0x60014000 -#define ESP32C3_RMT_BASE 0x60016000 -#define ESP32C3_LEDC_BASE 0x60019000 -#define ESP32C3_EFUSE_BASE 0x60008800 -#define ESP32C3_NRX_BASE 0x6001cc00 -#define ESP32C3_BB_BASE 0x6001d000 -#define ESP32C3_TIMERGROUP0_BASE 0x6001f000 -#define ESP32C3_TIMERGROUP1_BASE 0x60020000 -#define ESP32C3_SYS_TIMER_BASE 0x60023000 -#define ESP32C3_SPI2_BASE 0x60024000 -#define ESP32C3_SYSCON_BASE 0x60026000 -#define ESP32C3_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON */ -#define ESP32C3_TWAI_BASE 0x6002b000 -#define ESP32C3_I2S0_BASE 0x6002d000 -#define ESP32C3_APB_SARADC_BASE 0x60040000 -#define ESP32C3_AES_XTS_BASE 0x600cc000 - -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_MEMORYMAP_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_rsa.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_rsa.h deleted file mode 100644 index e11582c7f3e38..0000000000000 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_rsa.h +++ /dev/null @@ -1,308 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_rsa.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_RSA_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_RSA_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32c3_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* RSA_MEM_M_BLOCK_REG register - * Memory M - */ - -#define RSA_MEM_M_BLOCK_REG (DR_REG_RSA_BASE + 0x0) - -/* RSA_M_MEMORY : R/W; bitpos: [16:0]; default: 384; - * Memory M - */ - -#define RSA_M_MEMORY 0x0001FFFF -#define RSA_M_MEMORY_M (RSA_M_MEMORY_V << RSA_M_MEMORY_S) -#define RSA_M_MEMORY_V 0x0001FFFF -#define RSA_M_MEMORY_S 0 - -/* RSA_MEM_RB_BLOCK_REG register - * Memory RB - */ - -#define RSA_MEM_RB_BLOCK_REG (DR_REG_RSA_BASE + 0x200) - -/* RSA_RB_MEMORY : R/W; bitpos: [16:0]; default: 384; - * Memory RB - */ - -#define RSA_RB_MEMORY 0x0001FFFF -#define RSA_RB_MEMORY_M (RSA_RB_MEMORY_V << RSA_RB_MEMORY_S) -#define RSA_RB_MEMORY_V 0x0001FFFF -#define RSA_RB_MEMORY_S 0 - -/* RSA_MEM_Z_BLOCK_REG register - * Memory Z - */ - -#define RSA_MEM_Z_BLOCK_REG (DR_REG_RSA_BASE + 0x200) - -/* RSA_Z_MEMORY : R/W; bitpos: [16:0]; default: 384; - * Memory Z - */ - -#define RSA_Z_MEMORY 0x0001FFFF -#define RSA_Z_MEMORY_M (RSA_Z_MEMORY_V << RSA_Z_MEMORY_S) -#define RSA_Z_MEMORY_V 0x0001FFFF -#define RSA_Z_MEMORY_S 0 - -/* RSA_MEM_Y_BLOCK_REG register - * Memory Y - */ - -#define RSA_MEM_Y_BLOCK_REG (DR_REG_RSA_BASE + 0x400) - -/* RSA_Y_MEMORY : R/W; bitpos: [16:0]; default: 384; - * Memory Y - */ - -#define RSA_Y_MEMORY 0x0001FFFF -#define RSA_Y_MEMORY_M (RSA_Y_MEMORY_V << RSA_Y_MEMORY_S) -#define RSA_Y_MEMORY_V 0x0001FFFF -#define RSA_Y_MEMORY_S 0 - -/* RSA_MEM_X_BLOCK_REG register - * Memory X - */ - -#define RSA_MEM_X_BLOCK_REG (DR_REG_RSA_BASE + 0x600) - -/* RSA_X_MEMORY : R/W; bitpos: [16:0]; default: 384; - * Memory X - */ - -#define RSA_X_MEMORY 0x0001FFFF -#define RSA_X_MEMORY_M (RSA_X_MEMORY_V << RSA_X_MEMORY_S) -#define RSA_X_MEMORY_V 0x0001FFFF -#define RSA_X_MEMORY_S 0 - -/* RSA_M_PRIME_REG register - * Register to store M' - */ - -#define RSA_M_PRIME_REG (DR_REG_RSA_BASE + 0x800) - -/* RSA_M_PRIME : R/W; bitpos: [31:0]; default: 0; - * Stores M' - */ - -#define RSA_M_PRIME 0xFFFFFFFF -#define RSA_M_PRIME_M (RSA_M_PRIME_V << RSA_M_PRIME_S) -#define RSA_M_PRIME_V 0xFFFFFFFF -#define RSA_M_PRIME_S 0 - -/* RSA_MODE_REG register - * RSA length mode - */ - -#define RSA_MODE_REG (DR_REG_RSA_BASE + 0x804) - -/* RSA_MODE : R/W; bitpos: [6:0]; default: 0; - * Stores the mode of modular exponentiation. - */ - -#define RSA_MODE 0x0000007F -#define RSA_MODE_M (RSA_MODE_V << RSA_MODE_S) -#define RSA_MODE_V 0x0000007F -#define RSA_MODE_S 0 - -/* RSA_CLEAN_REG register - * RSA clean register - */ - -#define RSA_CLEAN_REG (DR_REG_RSA_BASE + 0x808) - -/* RSA_CLEAN : RO; bitpos: [0]; default: 0; - * The content of this bit is 1 when memories complete initialization. - */ - -#define RSA_CLEAN (BIT(0)) -#define RSA_CLEAN_M (RSA_CLEAN_V << RSA_CLEAN_S) -#define RSA_CLEAN_V 0x00000001 -#define RSA_CLEAN_S 0 - -/* RSA_MODEXP_START_REG register - * Modular exponentiation starting bit - */ - -#define RSA_MODEXP_START_REG (DR_REG_RSA_BASE + 0x80c) - -/* RSA_MODEXP_START : WO; bitpos: [0]; default: 0; - * Set this bit to 1 to start the modular exponentiation. - */ - -#define RSA_MODEXP_START (BIT(0)) -#define RSA_MODEXP_START_M (RSA_MODEXP_START_V << RSA_MODEXP_START_S) -#define RSA_MODEXP_START_V 0x00000001 -#define RSA_MODEXP_START_S 0 - -/* RSA_MODMULT_START_REG register - * Modular multiplication starting bit - */ - -#define RSA_MODMULT_START_REG (DR_REG_RSA_BASE + 0x810) - -/* RSA_MODMULT_START : WO; bitpos: [0]; default: 0; - * Set this bit to 1 to start the modular multiplication. - */ - -#define RSA_MODMULT_START (BIT(0)) -#define RSA_MODMULT_START_M (RSA_MODMULT_START_V << RSA_MODMULT_START_S) -#define RSA_MODMULT_START_V 0x00000001 -#define RSA_MODMULT_START_S 0 - -/* RSA_MULT_START_REG register - * Normal multiplicaiton starting bit - */ - -#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x814) - -/* RSA_MULT_START : WO; bitpos: [0]; default: 0; - * Set this bit to 1 to start the multiplication. - */ - -#define RSA_MULT_START (BIT(0)) -#define RSA_MULT_START_M (RSA_MULT_START_V << RSA_MULT_START_S) -#define RSA_MULT_START_V 0x00000001 -#define RSA_MULT_START_S 0 - -/* RSA_IDLE_REG register - * RSA idle register - */ - -#define RSA_IDLE_REG (DR_REG_RSA_BASE + 0x818) - -/* RSA_IDLE : RO; bitpos: [0]; default: 0; - * The content of this bit is 1 when the RSA accelerator is idle. - */ - -#define RSA_IDLE (BIT(0)) -#define RSA_IDLE_M (RSA_IDLE_V << RSA_IDLE_S) -#define RSA_IDLE_V 0x00000001 -#define RSA_IDLE_S 0 - -/* RSA_CLEAR_INTERRUPT_REG register - * RSA clear interrupt register - */ - -#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81c) - -/* RSA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0; - * Set this bit to 1 to clear the RSA interrupts. - */ - -#define RSA_CLEAR_INTERRUPT (BIT(0)) -#define RSA_CLEAR_INTERRUPT_M (RSA_CLEAR_INTERRUPT_V << RSA_CLEAR_INTERRUPT_S) -#define RSA_CLEAR_INTERRUPT_V 0x00000001 -#define RSA_CLEAR_INTERRUPT_S 0 - -/* RSA_CONSTANT_TIME_REG register - * The constant_time option - */ - -#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820) - -/* RSA_CONSTANT_TIME : R/W; bitpos: [0]; default: 1; - * Set this bit to 0 to enable the acceleration option of constant_time for - * modular exponentiation. Set to 1 to disable the acceleration (by default). - */ - -#define RSA_CONSTANT_TIME (BIT(0)) -#define RSA_CONSTANT_TIME_M (RSA_CONSTANT_TIME_V << RSA_CONSTANT_TIME_S) -#define RSA_CONSTANT_TIME_V 0x00000001 -#define RSA_CONSTANT_TIME_S 0 - -/* RSA_SEARCH_ENABLE_REG register - * The search option - */ - -#define RSA_SEARCH_ENABLE_REG (DR_REG_RSA_BASE + 0x824) - -/* RSA_SEARCH_ENABLE : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable the acceleration option of search for modular - * exponentiation. Set to 0 to disable the acceleration (by default). - */ - -#define RSA_SEARCH_ENABLE (BIT(0)) -#define RSA_SEARCH_ENABLE_M (RSA_SEARCH_ENABLE_V << RSA_SEARCH_ENABLE_S) -#define RSA_SEARCH_ENABLE_V 0x00000001 -#define RSA_SEARCH_ENABLE_S 0 - -/* RSA_SEARCH_POS_REG register - * The search position - */ - -#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828) - -/* RSA_SEARCH_POS : R/W; bitpos: [11:0]; default: 0; - * Is used to configure the starting address when the acceleration option of - * search is used. - */ - -#define RSA_SEARCH_POS 0x00000FFF -#define RSA_SEARCH_POS_M (RSA_SEARCH_POS_V << RSA_SEARCH_POS_S) -#define RSA_SEARCH_POS_V 0x00000FFF -#define RSA_SEARCH_POS_S 0 - -/* RSA_INTERRUPT_ENA_REG register - * RSA interrupt enable register - */ - -#define RSA_INTERRUPT_ENA_REG (DR_REG_RSA_BASE + 0x82c) - -/* RSA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable the RSA interrupt. This option is enabled by - * default. - */ - -#define RSA_INTERRUPT_ENA (BIT(0)) -#define RSA_INTERRUPT_ENA_M (RSA_INTERRUPT_ENA_V << RSA_INTERRUPT_ENA_S) -#define RSA_INTERRUPT_ENA_V 0x00000001 -#define RSA_INTERRUPT_ENA_S 0 - -/* RSA_DATE_REG register - * Version control register - */ - -#define RSA_DATE_REG (DR_REG_RSA_BASE + 0x830) - -/* RSA_DATE : R/W; bitpos: [29:0]; default: 538510373; - * Version control register - */ - -#define RSA_DATE 0x3FFFFFFF -#define RSA_DATE_M (RSA_DATE_V << RSA_DATE_S) -#define RSA_DATE_V 0x3FFFFFFF -#define RSA_DATE_S 0 - -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_RSA_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_sha.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_sha.h deleted file mode 100644 index f4d81898342c1..0000000000000 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_sha.h +++ /dev/null @@ -1,938 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_sha.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SHA_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SHA_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32c3_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* SHA_MODE_REG register - * Defines the algorithm of SHA accelerator - */ - -#define SHA_MODE_REG (DR_REG_SHA_BASE + 0x0) - -/* SHA_MODE : R/W; bitpos: [2:0]; default: 0; - * Defines the SHA algorithm. - */ - -#define SHA_MODE 0x00000007 -#define SHA_MODE_M (SHA_MODE_V << SHA_MODE_S) -#define SHA_MODE_V 0x00000007 -#define SHA_MODE_S 0 - -/* SHA_T_STRING_REG register - * String content register for calculating initial Hash Value (only - * effective for SHA-512/t) - */ - -#define SHA_T_STRING_REG (DR_REG_SHA_BASE + 0x4) - -/* SHA_T_STRING : R/W; bitpos: [31:0]; default: 0; - * Defines t_string for calculating the initial Hash value for SHA-512/t. - */ - -#define SHA_T_STRING 0xFFFFFFFF -#define SHA_T_STRING_M (SHA_T_STRING_V << SHA_T_STRING_S) -#define SHA_T_STRING_V 0xFFFFFFFF -#define SHA_T_STRING_S 0 - -/* SHA_T_LENGTH_REG register - * String length register for calculating initial Hash Value (only effective - * for SHA-512/t) - */ - -#define SHA_T_LENGTH_REG (DR_REG_SHA_BASE + 0x8) - -/* SHA_T_LENGTH : R/W; bitpos: [5:0]; default: 0; - * Defines t_string for calculating the initial Hash value for SHA-512/t. - */ - -#define SHA_T_LENGTH 0x0000003F -#define SHA_T_LENGTH_M (SHA_T_LENGTH_V << SHA_T_LENGTH_S) -#define SHA_T_LENGTH_V 0x0000003F -#define SHA_T_LENGTH_S 0 - -/* SHA_DMA_BLOCK_NUM_REG register - * Block number register (only effective for DMA-SHA) - */ - -#define SHA_DMA_BLOCK_NUM_REG (DR_REG_SHA_BASE + 0xc) - -/* SHA_DMA_BLOCK_NUM : R/W; bitpos: [5:0]; default: 0; - * Defines the DMA-SHA block number. - */ - -#define SHA_DMA_BLOCK_NUM 0x0000003F -#define SHA_DMA_BLOCK_NUM_M (SHA_DMA_BLOCK_NUM_V << SHA_DMA_BLOCK_NUM_S) -#define SHA_DMA_BLOCK_NUM_V 0x0000003F -#define SHA_DMA_BLOCK_NUM_S 0 - -/* SHA_START_REG register - * Starts the SHA accelerator for Typical SHA operation - */ - -#define SHA_START_REG (DR_REG_SHA_BASE + 0x10) - -/* SHA_START : WO; bitpos: [0]; default: 0; - * Write 1 to start Typical SHA calculation. - */ - -#define SHA_START (BIT(0)) -#define SHA_START_M (SHA_START_V << SHA_START_S) -#define SHA_START_V 0x00000001 -#define SHA_START_S 0 - -/* SHA_CONTINUE_REG register - * Continues SHA operation (only effective in Typical SHA mode) - */ - -#define SHA_CONTINUE_REG (DR_REG_SHA_BASE + 0x14) - -/* SHA_CONTINUE : WO; bitpos: [0]; default: 0; - * Write 1 to continue Typical SHA calculation. - */ - -#define SHA_CONTINUE (BIT(0)) -#define SHA_CONTINUE_M (SHA_CONTINUE_V << SHA_CONTINUE_S) -#define SHA_CONTINUE_V 0x00000001 -#define SHA_CONTINUE_S 0 - -/* SHA_BUSY_REG register - * Indicates if SHA Accelerator is busy or not - */ - -#define SHA_BUSY_REG (DR_REG_SHA_BASE + 0x18) - -/* SHA_BUSY_STATE : RO; bitpos: [0]; default: 0; - * Indicates the states of SHA accelerator. - * #1'h0: idle - * #1'h1: busy - */ - -#define SHA_BUSY_STATE (BIT(0)) -#define SHA_BUSY_STATE_M (SHA_BUSY_STATE_V << SHA_BUSY_STATE_S) -#define SHA_BUSY_STATE_V 0x00000001 -#define SHA_BUSY_STATE_S 0 - -/* SHA_DMA_START_REG register - * Starts the SHA accelerator for DMA-SHA operation - */ - -#define SHA_DMA_START_REG (DR_REG_SHA_BASE + 0x1c) - -/* SHA_DMA_START : WO; bitpos: [0]; default: 0; - * Write 1 to start DMA-SHA calculation. - */ - -#define SHA_DMA_START (BIT(0)) -#define SHA_DMA_START_M (SHA_DMA_START_V << SHA_DMA_START_S) -#define SHA_DMA_START_V 0x00000001 -#define SHA_DMA_START_S 0 - -/* SHA_DMA_CONTINUE_REG register - * Continues SHA operation (only effective in DMA-SHA mode) - */ - -#define SHA_DMA_CONTINUE_REG (DR_REG_SHA_BASE + 0x20) - -/* SHA_DMA_CONTINUE : WO; bitpos: [0]; default: 0; - * Write 1 to continue DMA-SHA calculation. - */ - -#define SHA_DMA_CONTINUE (BIT(0)) -#define SHA_DMA_CONTINUE_M (SHA_DMA_CONTINUE_V << SHA_DMA_CONTINUE_S) -#define SHA_DMA_CONTINUE_V 0x00000001 -#define SHA_DMA_CONTINUE_S 0 - -/* SHA_INT_CLEAR_REG register - * DMA-SHA interrupt clear register - */ - -#define SHA_INT_CLEAR_REG (DR_REG_SHA_BASE + 0x24) - -/* SHA_CLEAR_INTERRUPT : WO; bitpos: [0]; default: 0; - * Clears DMA-SHA interrupt. - */ - -#define SHA_CLEAR_INTERRUPT (BIT(0)) -#define SHA_CLEAR_INTERRUPT_M (SHA_CLEAR_INTERRUPT_V << SHA_CLEAR_INTERRUPT_S) -#define SHA_CLEAR_INTERRUPT_V 0x00000001 -#define SHA_CLEAR_INTERRUPT_S 0 - -/* SHA_INT_ENA_REG register - * DMA-SHA interrupt enable register - */ - -#define SHA_INT_ENA_REG (DR_REG_SHA_BASE + 0x28) - -/* SHA_INTERRUPT_ENA : R/W; bitpos: [0]; default: 0; - * Enables DMA-SHA interrupt. - */ - -#define SHA_INTERRUPT_ENA (BIT(0)) -#define SHA_INTERRUPT_ENA_M (SHA_INTERRUPT_ENA_V << SHA_INTERRUPT_ENA_S) -#define SHA_INTERRUPT_ENA_V 0x00000001 -#define SHA_INTERRUPT_ENA_S 0 - -/* SHA_DATE_REG register - * Version control register. - */ - -#define SHA_DATE_REG (DR_REG_SHA_BASE + 0x2c) - -/* SHA_DATE : R/W; bitpos: [29:0]; default: 538510338; - * Version control register - */ - -#define SHA_DATE 0x3FFFFFFF -#define SHA_DATE_M (SHA_DATE_V << SHA_DATE_S) -#define SHA_DATE_V 0x3FFFFFFF -#define SHA_DATE_S 0 - -/* SHA_H_0_REG register - * Hash value - */ - -#define SHA_H_0_REG (DR_REG_SHA_BASE + 0x40) - -/* SHA_H_0 : R/W; bitpos: [31:0]; default: 0; - * Stores the 0th 32-bit piece of the Hash value. - */ - -#define SHA_H_0 0xFFFFFFFF -#define SHA_H_0_M (SHA_H_0_V << SHA_H_0_S) -#define SHA_H_0_V 0xFFFFFFFF -#define SHA_H_0_S 0 - -/* SHA_H_1_REG register - * Hash value - */ - -#define SHA_H_1_REG (DR_REG_SHA_BASE + 0x44) - -/* SHA_H_1 : R/W; bitpos: [31:0]; default: 0; - * Stores the 1th 32-bit piece of the Hash value. - */ - -#define SHA_H_1 0xFFFFFFFF -#define SHA_H_1_M (SHA_H_1_V << SHA_H_1_S) -#define SHA_H_1_V 0xFFFFFFFF -#define SHA_H_1_S 0 - -/* SHA_H_2_REG register - * Hash value - */ - -#define SHA_H_2_REG (DR_REG_SHA_BASE + 0x48) - -/* SHA_H_2 : R/W; bitpos: [31:0]; default: 0; - * Stores the 2th 32-bit piece of the Hash value. - */ - -#define SHA_H_2 0xFFFFFFFF -#define SHA_H_2_M (SHA_H_2_V << SHA_H_2_S) -#define SHA_H_2_V 0xFFFFFFFF -#define SHA_H_2_S 0 - -/* SHA_H_3_REG register - * Hash value - */ - -#define SHA_H_3_REG (DR_REG_SHA_BASE + 0x4c) - -/* SHA_H_3 : R/W; bitpos: [31:0]; default: 0; - * Stores the 3th 32-bit piece of the Hash value. - */ - -#define SHA_H_3 0xFFFFFFFF -#define SHA_H_3_M (SHA_H_3_V << SHA_H_3_S) -#define SHA_H_3_V 0xFFFFFFFF -#define SHA_H_3_S 0 - -/* SHA_H_4_REG register - * Hash value - */ - -#define SHA_H_4_REG (DR_REG_SHA_BASE + 0x50) - -/* SHA_H_4 : R/W; bitpos: [31:0]; default: 0; - * Stores the 4th 32-bit piece of the Hash value. - */ - -#define SHA_H_4 0xFFFFFFFF -#define SHA_H_4_M (SHA_H_4_V << SHA_H_4_S) -#define SHA_H_4_V 0xFFFFFFFF -#define SHA_H_4_S 0 - -/* SHA_H_5_REG register - * Hash value - */ - -#define SHA_H_5_REG (DR_REG_SHA_BASE + 0x54) - -/* SHA_H_5 : R/W; bitpos: [31:0]; default: 0; - * Stores the 5th 32-bit piece of the Hash value. - */ - -#define SHA_H_5 0xFFFFFFFF -#define SHA_H_5_M (SHA_H_5_V << SHA_H_5_S) -#define SHA_H_5_V 0xFFFFFFFF -#define SHA_H_5_S 0 - -/* SHA_H_6_REG register - * Hash value - */ - -#define SHA_H_6_REG (DR_REG_SHA_BASE + 0x58) - -/* SHA_H_6 : R/W; bitpos: [31:0]; default: 0; - * Stores the 6th 32-bit piece of the Hash value. - */ - -#define SHA_H_6 0xFFFFFFFF -#define SHA_H_6_M (SHA_H_6_V << SHA_H_6_S) -#define SHA_H_6_V 0xFFFFFFFF -#define SHA_H_6_S 0 - -/* SHA_H_7_REG register - * Hash value - */ - -#define SHA_H_7_REG (DR_REG_SHA_BASE + 0x5c) - -/* SHA_H_7 : R/W; bitpos: [31:0]; default: 0; - * Stores the 7th 32-bit piece of the Hash value. - */ - -#define SHA_H_7 0xFFFFFFFF -#define SHA_H_7_M (SHA_H_7_V << SHA_H_7_S) -#define SHA_H_7_V 0xFFFFFFFF -#define SHA_H_7_S 0 - -/* SHA_H_8_REG register - * Hash value - */ - -#define SHA_H_8_REG (DR_REG_SHA_BASE + 0x60) - -/* SHA_H_8 : R/W; bitpos: [31:0]; default: 0; - * Stores the 8th 32-bit piece of the Hash value. - */ - -#define SHA_H_8 0xFFFFFFFF -#define SHA_H_8_M (SHA_H_8_V << SHA_H_8_S) -#define SHA_H_8_V 0xFFFFFFFF -#define SHA_H_8_S 0 - -/* SHA_H_9_REG register - * Hash value - */ - -#define SHA_H_9_REG (DR_REG_SHA_BASE + 0x64) - -/* SHA_H_9 : R/W; bitpos: [31:0]; default: 0; - * Stores the 9th 32-bit piece of the Hash value. - */ - -#define SHA_H_9 0xFFFFFFFF -#define SHA_H_9_M (SHA_H_9_V << SHA_H_9_S) -#define SHA_H_9_V 0xFFFFFFFF -#define SHA_H_9_S 0 - -/* SHA_H_10_REG register - * Hash value - */ - -#define SHA_H_10_REG (DR_REG_SHA_BASE + 0x68) - -/* SHA_H_10 : R/W; bitpos: [31:0]; default: 0; - * Stores the 10th 32-bit piece of the Hash value. - */ - -#define SHA_H_10 0xFFFFFFFF -#define SHA_H_10_M (SHA_H_10_V << SHA_H_10_S) -#define SHA_H_10_V 0xFFFFFFFF -#define SHA_H_10_S 0 - -/* SHA_H_11_REG register - * Hash value - */ - -#define SHA_H_11_REG (DR_REG_SHA_BASE + 0x6c) - -/* SHA_H_11 : R/W; bitpos: [31:0]; default: 0; - * Stores the 11th 32-bit piece of the Hash value. - */ - -#define SHA_H_11 0xFFFFFFFF -#define SHA_H_11_M (SHA_H_11_V << SHA_H_11_S) -#define SHA_H_11_V 0xFFFFFFFF -#define SHA_H_11_S 0 - -/* SHA_H_12_REG register - * Hash value - */ - -#define SHA_H_12_REG (DR_REG_SHA_BASE + 0x70) - -/* SHA_H_12 : R/W; bitpos: [31:0]; default: 0; - * Stores the 12th 32-bit piece of the Hash value. - */ - -#define SHA_H_12 0xFFFFFFFF -#define SHA_H_12_M (SHA_H_12_V << SHA_H_12_S) -#define SHA_H_12_V 0xFFFFFFFF -#define SHA_H_12_S 0 - -/* SHA_H_13_REG register - * Hash value - */ - -#define SHA_H_13_REG (DR_REG_SHA_BASE + 0x74) - -/* SHA_H_13 : R/W; bitpos: [31:0]; default: 0; - * Stores the 13th 32-bit piece of the Hash value. - */ - -#define SHA_H_13 0xFFFFFFFF -#define SHA_H_13_M (SHA_H_13_V << SHA_H_13_S) -#define SHA_H_13_V 0xFFFFFFFF -#define SHA_H_13_S 0 - -/* SHA_H_14_REG register - * Hash value - */ - -#define SHA_H_14_REG (DR_REG_SHA_BASE + 0x78) - -/* SHA_H_14 : R/W; bitpos: [31:0]; default: 0; - * Stores the 14th 32-bit piece of the Hash value. - */ - -#define SHA_H_14 0xFFFFFFFF -#define SHA_H_14_M (SHA_H_14_V << SHA_H_14_S) -#define SHA_H_14_V 0xFFFFFFFF -#define SHA_H_14_S 0 - -/* SHA_H_15_REG register - * Hash value - */ - -#define SHA_H_15_REG (DR_REG_SHA_BASE + 0x7c) - -/* SHA_H_15 : R/W; bitpos: [31:0]; default: 0; - * Stores the 15th 32-bit piece of the Hash value. - */ - -#define SHA_H_15 0xFFFFFFFF -#define SHA_H_15_M (SHA_H_15_V << SHA_H_15_S) -#define SHA_H_15_V 0xFFFFFFFF -#define SHA_H_15_S 0 - -/* SHA_M_0_REG register - * Message - */ - -#define SHA_M_0_REG (DR_REG_SHA_BASE + 0x80) - -/* SHA_M_0 : R/W; bitpos: [31:0]; default: 0; - * Stores the 0th 32-bit piece of the message. - */ - -#define SHA_M_0 0xFFFFFFFF -#define SHA_M_0_M (SHA_M_0_V << SHA_M_0_S) -#define SHA_M_0_V 0xFFFFFFFF -#define SHA_M_0_S 0 - -/* SHA_M_1_REG register - * Message - */ - -#define SHA_M_1_REG (DR_REG_SHA_BASE + 0x84) - -/* SHA_M_1 : R/W; bitpos: [31:0]; default: 0; - * Stores the 1th 32-bit piece of the message. - */ - -#define SHA_M_1 0xFFFFFFFF -#define SHA_M_1_M (SHA_M_1_V << SHA_M_1_S) -#define SHA_M_1_V 0xFFFFFFFF -#define SHA_M_1_S 0 - -/* SHA_M_2_REG register - * Message - */ - -#define SHA_M_2_REG (DR_REG_SHA_BASE + 0x88) - -/* SHA_M_2 : R/W; bitpos: [31:0]; default: 0; - * Stores the 2th 32-bit piece of the message. - */ - -#define SHA_M_2 0xFFFFFFFF -#define SHA_M_2_M (SHA_M_2_V << SHA_M_2_S) -#define SHA_M_2_V 0xFFFFFFFF -#define SHA_M_2_S 0 - -/* SHA_M_3_REG register - * Message - */ - -#define SHA_M_3_REG (DR_REG_SHA_BASE + 0x8c) - -/* SHA_M_3 : R/W; bitpos: [31:0]; default: 0; - * Stores the 3th 32-bit piece of the message. - */ - -#define SHA_M_3 0xFFFFFFFF -#define SHA_M_3_M (SHA_M_3_V << SHA_M_3_S) -#define SHA_M_3_V 0xFFFFFFFF -#define SHA_M_3_S 0 - -/* SHA_M_4_REG register - * Message - */ - -#define SHA_M_4_REG (DR_REG_SHA_BASE + 0x90) - -/* SHA_M_4 : R/W; bitpos: [31:0]; default: 0; - * Stores the 4th 32-bit piece of the message. - */ - -#define SHA_M_4 0xFFFFFFFF -#define SHA_M_4_M (SHA_M_4_V << SHA_M_4_S) -#define SHA_M_4_V 0xFFFFFFFF -#define SHA_M_4_S 0 - -/* SHA_M_5_REG register - * Message - */ - -#define SHA_M_5_REG (DR_REG_SHA_BASE + 0x94) - -/* SHA_M_5 : R/W; bitpos: [31:0]; default: 0; - * Stores the 5th 32-bit piece of the message. - */ - -#define SHA_M_5 0xFFFFFFFF -#define SHA_M_5_M (SHA_M_5_V << SHA_M_5_S) -#define SHA_M_5_V 0xFFFFFFFF -#define SHA_M_5_S 0 - -/* SHA_M_6_REG register - * Message - */ - -#define SHA_M_6_REG (DR_REG_SHA_BASE + 0x98) - -/* SHA_M_6 : R/W; bitpos: [31:0]; default: 0; - * Stores the 6th 32-bit piece of the message. - */ - -#define SHA_M_6 0xFFFFFFFF -#define SHA_M_6_M (SHA_M_6_V << SHA_M_6_S) -#define SHA_M_6_V 0xFFFFFFFF -#define SHA_M_6_S 0 - -/* SHA_M_7_REG register - * Message - */ - -#define SHA_M_7_REG (DR_REG_SHA_BASE + 0x9c) - -/* SHA_M_7 : R/W; bitpos: [31:0]; default: 0; - * Stores the 7th 32-bit piece of the message. - */ - -#define SHA_M_7 0xFFFFFFFF -#define SHA_M_7_M (SHA_M_7_V << SHA_M_7_S) -#define SHA_M_7_V 0xFFFFFFFF -#define SHA_M_7_S 0 - -/* SHA_M_8_REG register - * Message - */ - -#define SHA_M_8_REG (DR_REG_SHA_BASE + 0xa0) - -/* SHA_M_8 : R/W; bitpos: [31:0]; default: 0; - * Stores the 8th 32-bit piece of the message. - */ - -#define SHA_M_8 0xFFFFFFFF -#define SHA_M_8_M (SHA_M_8_V << SHA_M_8_S) -#define SHA_M_8_V 0xFFFFFFFF -#define SHA_M_8_S 0 - -/* SHA_M_9_REG register - * Message - */ - -#define SHA_M_9_REG (DR_REG_SHA_BASE + 0xa4) - -/* SHA_M_9 : R/W; bitpos: [31:0]; default: 0; - * Stores the 9th 32-bit piece of the message. - */ - -#define SHA_M_9 0xFFFFFFFF -#define SHA_M_9_M (SHA_M_9_V << SHA_M_9_S) -#define SHA_M_9_V 0xFFFFFFFF -#define SHA_M_9_S 0 - -/* SHA_M_10_REG register - * Message - */ - -#define SHA_M_10_REG (DR_REG_SHA_BASE + 0xa8) - -/* SHA_M_10 : R/W; bitpos: [31:0]; default: 0; - * Stores the 10th 32-bit piece of the message. - */ - -#define SHA_M_10 0xFFFFFFFF -#define SHA_M_10_M (SHA_M_10_V << SHA_M_10_S) -#define SHA_M_10_V 0xFFFFFFFF -#define SHA_M_10_S 0 - -/* SHA_M_11_REG register - * Message - */ - -#define SHA_M_11_REG (DR_REG_SHA_BASE + 0xac) - -/* SHA_M_11 : R/W; bitpos: [31:0]; default: 0; - * Stores the 11th 32-bit piece of the message. - */ - -#define SHA_M_11 0xFFFFFFFF -#define SHA_M_11_M (SHA_M_11_V << SHA_M_11_S) -#define SHA_M_11_V 0xFFFFFFFF -#define SHA_M_11_S 0 - -/* SHA_M_12_REG register - * Message - */ - -#define SHA_M_12_REG (DR_REG_SHA_BASE + 0xb0) - -/* SHA_M_12 : R/W; bitpos: [31:0]; default: 0; - * Stores the 12th 32-bit piece of the message. - */ - -#define SHA_M_12 0xFFFFFFFF -#define SHA_M_12_M (SHA_M_12_V << SHA_M_12_S) -#define SHA_M_12_V 0xFFFFFFFF -#define SHA_M_12_S 0 - -/* SHA_M_13_REG register - * Message - */ - -#define SHA_M_13_REG (DR_REG_SHA_BASE + 0xb4) - -/* SHA_M_13 : R/W; bitpos: [31:0]; default: 0; - * Stores the 13th 32-bit piece of the message. - */ - -#define SHA_M_13 0xFFFFFFFF -#define SHA_M_13_M (SHA_M_13_V << SHA_M_13_S) -#define SHA_M_13_V 0xFFFFFFFF -#define SHA_M_13_S 0 - -/* SHA_M_14_REG register - * Message - */ - -#define SHA_M_14_REG (DR_REG_SHA_BASE + 0xb8) - -/* SHA_M_14 : R/W; bitpos: [31:0]; default: 0; - * Stores the 14th 32-bit piece of the message. - */ - -#define SHA_M_14 0xFFFFFFFF -#define SHA_M_14_M (SHA_M_14_V << SHA_M_14_S) -#define SHA_M_14_V 0xFFFFFFFF -#define SHA_M_14_S 0 - -/* SHA_M_15_REG register - * Message - */ - -#define SHA_M_15_REG (DR_REG_SHA_BASE + 0xbc) - -/* SHA_M_15 : R/W; bitpos: [31:0]; default: 0; - * Stores the 15th 32-bit piece of the message. - */ - -#define SHA_M_15 0xFFFFFFFF -#define SHA_M_15_M (SHA_M_15_V << SHA_M_15_S) -#define SHA_M_15_V 0xFFFFFFFF -#define SHA_M_15_S 0 - -/* SHA_M_16_REG register - * Message - */ - -#define SHA_M_16_REG (DR_REG_SHA_BASE + 0xc0) - -/* SHA_M_16 : R/W; bitpos: [31:0]; default: 0; - * Stores the 16th 32-bit piece of the message. - */ - -#define SHA_M_16 0xFFFFFFFF -#define SHA_M_16_M (SHA_M_16_V << SHA_M_16_S) -#define SHA_M_16_V 0xFFFFFFFF -#define SHA_M_16_S 0 - -/* SHA_M_17_REG register - * Message - */ - -#define SHA_M_17_REG (DR_REG_SHA_BASE + 0xc4) - -/* SHA_M_17 : R/W; bitpos: [31:0]; default: 0; - * Stores the 17th 32-bit piece of the message. - */ - -#define SHA_M_17 0xFFFFFFFF -#define SHA_M_17_M (SHA_M_17_V << SHA_M_17_S) -#define SHA_M_17_V 0xFFFFFFFF -#define SHA_M_17_S 0 - -/* SHA_M_18_REG register - * Message - */ - -#define SHA_M_18_REG (DR_REG_SHA_BASE + 0xc8) - -/* SHA_M_18 : R/W; bitpos: [31:0]; default: 0; - * Stores the 18th 32-bit piece of the message. - */ - -#define SHA_M_18 0xFFFFFFFF -#define SHA_M_18_M (SHA_M_18_V << SHA_M_18_S) -#define SHA_M_18_V 0xFFFFFFFF -#define SHA_M_18_S 0 - -/* SHA_M_19_REG register - * Message - */ - -#define SHA_M_19_REG (DR_REG_SHA_BASE + 0xcc) - -/* SHA_M_19 : R/W; bitpos: [31:0]; default: 0; - * Stores the 19th 32-bit piece of the message. - */ - -#define SHA_M_19 0xFFFFFFFF -#define SHA_M_19_M (SHA_M_19_V << SHA_M_19_S) -#define SHA_M_19_V 0xFFFFFFFF -#define SHA_M_19_S 0 - -/* SHA_M_20_REG register - * Message - */ - -#define SHA_M_20_REG (DR_REG_SHA_BASE + 0xd0) - -/* SHA_M_20 : R/W; bitpos: [31:0]; default: 0; - * Stores the 20th 32-bit piece of the message. - */ - -#define SHA_M_20 0xFFFFFFFF -#define SHA_M_20_M (SHA_M_20_V << SHA_M_20_S) -#define SHA_M_20_V 0xFFFFFFFF -#define SHA_M_20_S 0 - -/* SHA_M_21_REG register - * Message - */ - -#define SHA_M_21_REG (DR_REG_SHA_BASE + 0xd4) - -/* SHA_M_21 : R/W; bitpos: [31:0]; default: 0; - * Stores the 21th 32-bit piece of the message. - */ - -#define SHA_M_21 0xFFFFFFFF -#define SHA_M_21_M (SHA_M_21_V << SHA_M_21_S) -#define SHA_M_21_V 0xFFFFFFFF -#define SHA_M_21_S 0 - -/* SHA_M_22_REG register - * Message - */ - -#define SHA_M_22_REG (DR_REG_SHA_BASE + 0xd8) - -/* SHA_M_22 : R/W; bitpos: [31:0]; default: 0; - * Stores the 22th 32-bit piece of the message. - */ - -#define SHA_M_22 0xFFFFFFFF -#define SHA_M_22_M (SHA_M_22_V << SHA_M_22_S) -#define SHA_M_22_V 0xFFFFFFFF -#define SHA_M_22_S 0 - -/* SHA_M_23_REG register - * Message - */ - -#define SHA_M_23_REG (DR_REG_SHA_BASE + 0xdc) - -/* SHA_M_23 : R/W; bitpos: [31:0]; default: 0; - * Stores the 23th 32-bit piece of the message. - */ - -#define SHA_M_23 0xFFFFFFFF -#define SHA_M_23_M (SHA_M_23_V << SHA_M_23_S) -#define SHA_M_23_V 0xFFFFFFFF -#define SHA_M_23_S 0 - -/* SHA_M_24_REG register - * Message - */ - -#define SHA_M_24_REG (DR_REG_SHA_BASE + 0xe0) - -/* SHA_M_24 : R/W; bitpos: [31:0]; default: 0; - * Stores the 24th 32-bit piece of the message. - */ - -#define SHA_M_24 0xFFFFFFFF -#define SHA_M_24_M (SHA_M_24_V << SHA_M_24_S) -#define SHA_M_24_V 0xFFFFFFFF -#define SHA_M_24_S 0 - -/* SHA_M_25_REG register - * Message - */ - -#define SHA_M_25_REG (DR_REG_SHA_BASE + 0xe4) - -/* SHA_M_25 : R/W; bitpos: [31:0]; default: 0; - * Stores the 25th 32-bit piece of the message. - */ - -#define SHA_M_25 0xFFFFFFFF -#define SHA_M_25_M (SHA_M_25_V << SHA_M_25_S) -#define SHA_M_25_V 0xFFFFFFFF -#define SHA_M_25_S 0 - -/* SHA_M_26_REG register - * Message - */ - -#define SHA_M_26_REG (DR_REG_SHA_BASE + 0xe8) - -/* SHA_M_26 : R/W; bitpos: [31:0]; default: 0; - * Stores the 26th 32-bit piece of the message. - */ - -#define SHA_M_26 0xFFFFFFFF -#define SHA_M_26_M (SHA_M_26_V << SHA_M_26_S) -#define SHA_M_26_V 0xFFFFFFFF -#define SHA_M_26_S 0 - -/* SHA_M_27_REG register - * Message - */ - -#define SHA_M_27_REG (DR_REG_SHA_BASE + 0xec) - -/* SHA_M_27 : R/W; bitpos: [31:0]; default: 0; - * Stores the 27th 32-bit piece of the message. - */ - -#define SHA_M_27 0xFFFFFFFF -#define SHA_M_27_M (SHA_M_27_V << SHA_M_27_S) -#define SHA_M_27_V 0xFFFFFFFF -#define SHA_M_27_S 0 - -/* SHA_M_28_REG register - * Message - */ - -#define SHA_M_28_REG (DR_REG_SHA_BASE + 0xf0) - -/* SHA_M_28 : R/W; bitpos: [31:0]; default: 0; - * Stores the 28th 32-bit piece of the message. - */ - -#define SHA_M_28 0xFFFFFFFF -#define SHA_M_28_M (SHA_M_28_V << SHA_M_28_S) -#define SHA_M_28_V 0xFFFFFFFF -#define SHA_M_28_S 0 - -/* SHA_M_29_REG register - * Message - */ - -#define SHA_M_29_REG (DR_REG_SHA_BASE + 0xf4) - -/* SHA_M_29 : R/W; bitpos: [31:0]; default: 0; - * Stores the 29th 32-bit piece of the message. - */ - -#define SHA_M_29 0xFFFFFFFF -#define SHA_M_29_M (SHA_M_29_V << SHA_M_29_S) -#define SHA_M_29_V 0xFFFFFFFF -#define SHA_M_29_S 0 - -/* SHA_M_30_REG register - * Message - */ - -#define SHA_M_30_REG (DR_REG_SHA_BASE + 0xf8) - -/* SHA_M_30 : R/W; bitpos: [31:0]; default: 0; - * Stores the 30th 32-bit piece of the message. - */ - -#define SHA_M_30 0xFFFFFFFF -#define SHA_M_30_M (SHA_M_30_V << SHA_M_30_S) -#define SHA_M_30_V 0xFFFFFFFF -#define SHA_M_30_S 0 - -/* SHA_M_31_REG register - * Message - */ - -#define SHA_M_31_REG (DR_REG_SHA_BASE + 0xfc) - -/* SHA_M_31 : R/W; bitpos: [31:0]; default: 0; - * Stores the 31th 32-bit piece of the message. - */ - -#define SHA_M_31 0xFFFFFFFF -#define SHA_M_31_M (SHA_M_31_V << SHA_M_31_S) -#define SHA_M_31_V 0xFFFFFFFF -#define SHA_M_31_S 0 - -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SHA_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_spi.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_spi.h deleted file mode 100644 index 9b4a021163b00..0000000000000 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_spi.h +++ /dev/null @@ -1,2214 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_spi.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SPI_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SPI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32c3_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* SPI_CMD_REG register - * Command control register - */ - -#define SPI_CMD_REG (DR_REG_SPI2_BASE + 0x0) - -/* SPI_USR : R/W/SC; bitpos: [24]; default: 0; - * User define command enable. An operation will be triggered when the bit - * is set. The bit will be cleared once the operation done.1: enable 0: - * disable. Can not be changed by CONF_buf. - */ - -#define SPI_USR (BIT(24)) -#define SPI_USR_M (SPI_USR_V << SPI_USR_S) -#define SPI_USR_V 0x00000001 -#define SPI_USR_S 24 - -/* SPI_UPDATE : WT; bitpos: [23]; default: 0; - * Set this bit to synchronize SPI registers from APB clock domain into SPI - * module clock domain, which is only used in SPI master mode. - */ - -#define SPI_UPDATE (BIT(23)) -#define SPI_UPDATE_M (SPI_UPDATE_V << SPI_UPDATE_S) -#define SPI_UPDATE_V 0x00000001 -#define SPI_UPDATE_S 23 - -/* SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0; - * Define the APB cycles of SPI_CONF state. Can be configured in CONF state. - */ - -#define SPI_CONF_BITLEN 0x0003FFFF -#define SPI_CONF_BITLEN_M (SPI_CONF_BITLEN_V << SPI_CONF_BITLEN_S) -#define SPI_CONF_BITLEN_V 0x0003FFFF -#define SPI_CONF_BITLEN_S 0 - -/* SPI_ADDR_REG register - * Address value register - */ - -#define SPI_ADDR_REG (DR_REG_SPI2_BASE + 0x4) - -/* SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0; - * Address to slave. Can be configured in CONF state. - */ - -#define SPI_USR_ADDR_VALUE 0xFFFFFFFF -#define SPI_USR_ADDR_VALUE_M (SPI_USR_ADDR_VALUE_V << SPI_USR_ADDR_VALUE_S) -#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFF -#define SPI_USR_ADDR_VALUE_S 0 - -/* SPI_CTRL_REG register - * SPI control register - */ - -#define SPI_CTRL_REG (DR_REG_SPI2_BASE + 0x8) - -/* SPI_WR_BIT_ORDER : R/W; bitpos: [26]; default: 0; - * In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can - * be configured in CONF state. - */ - -#define SPI_WR_BIT_ORDER (BIT(26)) -#define SPI_WR_BIT_ORDER_M (SPI_WR_BIT_ORDER_V << SPI_WR_BIT_ORDER_S) -#define SPI_WR_BIT_ORDER_V 0x00000001 -#define SPI_WR_BIT_ORDER_S 26 - -/* SPI_RD_BIT_ORDER : R/W; bitpos: [25]; default: 0; - * In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in - * CONF state. - */ - -#define SPI_RD_BIT_ORDER (BIT(25)) -#define SPI_RD_BIT_ORDER_M (SPI_RD_BIT_ORDER_V << SPI_RD_BIT_ORDER_S) -#define SPI_RD_BIT_ORDER_V 0x00000001 -#define SPI_RD_BIT_ORDER_S 25 - -/* SPI_WP_POL : R/W; bitpos: [21]; default: 1; - * Write protect signal output when SPI is idle. 1: output high, 0: output - * low. Can be configured in CONF state. - */ - -#define SPI_WP_POL (BIT(21)) -#define SPI_WP_POL_M (SPI_WP_POL_V << SPI_WP_POL_S) -#define SPI_WP_POL_V 0x00000001 -#define SPI_WP_POL_S 21 - -/* SPI_HOLD_POL : R/W; bitpos: [20]; default: 1; - * SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. - * Can be configured in CONF state. - */ - -#define SPI_HOLD_POL (BIT(20)) -#define SPI_HOLD_POL_M (SPI_HOLD_POL_V << SPI_HOLD_POL_S) -#define SPI_HOLD_POL_V 0x00000001 -#define SPI_HOLD_POL_S 20 - -/* SPI_D_POL : R/W; bitpos: [19]; default: 1; - * The bit is used to set MOSI line polarity, 1: high 0, low. Can be - * configured in CONF state. - */ - -#define SPI_D_POL (BIT(19)) -#define SPI_D_POL_M (SPI_D_POL_V << SPI_D_POL_S) -#define SPI_D_POL_V 0x00000001 -#define SPI_D_POL_S 19 - -/* SPI_Q_POL : R/W; bitpos: [18]; default: 1; - * The bit is used to set MISO line polarity, 1: high 0, low. Can be - * configured in CONF state. - */ - -#define SPI_Q_POL (BIT(18)) -#define SPI_Q_POL_M (SPI_Q_POL_V << SPI_Q_POL_S) -#define SPI_Q_POL_V 0x00000001 -#define SPI_Q_POL_S 18 - -/* SPI_FREAD_QUAD : R/W; bitpos: [15]; default: 0; - * In the read operations read-data phase apply 4 signals. 1: enable 0: - * disable. Can be configured in CONF state. - */ - -#define SPI_FREAD_QUAD (BIT(15)) -#define SPI_FREAD_QUAD_M (SPI_FREAD_QUAD_V << SPI_FREAD_QUAD_S) -#define SPI_FREAD_QUAD_V 0x00000001 -#define SPI_FREAD_QUAD_S 15 - -/* SPI_FREAD_DUAL : R/W; bitpos: [14]; default: 0; - * In the read operations, read-data phase apply 2 signals. 1: enable 0: - * disable. Can be configured in CONF state. - */ - -#define SPI_FREAD_DUAL (BIT(14)) -#define SPI_FREAD_DUAL_M (SPI_FREAD_DUAL_V << SPI_FREAD_DUAL_S) -#define SPI_FREAD_DUAL_V 0x00000001 -#define SPI_FREAD_DUAL_S 14 - -/* SPI_FCMD_QUAD : R/W; bitpos: [9]; default: 0; - * Apply 4 signals during command phase 1:enable 0: disable. Can be - * configured in CONF state. - */ - -#define SPI_FCMD_QUAD (BIT(9)) -#define SPI_FCMD_QUAD_M (SPI_FCMD_QUAD_V << SPI_FCMD_QUAD_S) -#define SPI_FCMD_QUAD_V 0x00000001 -#define SPI_FCMD_QUAD_S 9 - -/* SPI_FCMD_DUAL : R/W; bitpos: [8]; default: 0; - * Apply 2 signals during command phase 1:enable 0: disable. Can be - * configured in CONF state. - */ - -#define SPI_FCMD_DUAL (BIT(8)) -#define SPI_FCMD_DUAL_M (SPI_FCMD_DUAL_V << SPI_FCMD_DUAL_S) -#define SPI_FCMD_DUAL_V 0x00000001 -#define SPI_FCMD_DUAL_S 8 - -/* SPI_FADDR_QUAD : R/W; bitpos: [6]; default: 0; - * Apply 4 signals during addr phase 1:enable 0: disable. Can be configured - * in CONF state. - */ - -#define SPI_FADDR_QUAD (BIT(6)) -#define SPI_FADDR_QUAD_M (SPI_FADDR_QUAD_V << SPI_FADDR_QUAD_S) -#define SPI_FADDR_QUAD_V 0x00000001 -#define SPI_FADDR_QUAD_S 6 - -/* SPI_FADDR_DUAL : R/W; bitpos: [5]; default: 0; - * Apply 2 signals during addr phase 1:enable 0: disable. Can be configured - * in CONF state. - */ - -#define SPI_FADDR_DUAL (BIT(5)) -#define SPI_FADDR_DUAL_M (SPI_FADDR_DUAL_V << SPI_FADDR_DUAL_S) -#define SPI_FADDR_DUAL_V 0x00000001 -#define SPI_FADDR_DUAL_S 5 - -/* SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0; - * In the dummy phase the signal level of spi is output by the spi - * controller. Can be configured in CONF state. - */ - -#define SPI_DUMMY_OUT (BIT(3)) -#define SPI_DUMMY_OUT_M (SPI_DUMMY_OUT_V << SPI_DUMMY_OUT_S) -#define SPI_DUMMY_OUT_V 0x00000001 -#define SPI_DUMMY_OUT_S 3 - -/* SPI_CLOCK_REG register - * SPI clock control register - */ - -#define SPI_CLOCK_REG (DR_REG_SPI2_BASE + 0xc) - -/* SPI_CLK_EQU_SYSCLK : R/W; bitpos: [31]; default: 1; - * In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided - * from system clock. Can be configured in CONF state. - */ - -#define SPI_CLK_EQU_SYSCLK (BIT(31)) -#define SPI_CLK_EQU_SYSCLK_M (SPI_CLK_EQU_SYSCLK_V << SPI_CLK_EQU_SYSCLK_S) -#define SPI_CLK_EQU_SYSCLK_V 0x00000001 -#define SPI_CLK_EQU_SYSCLK_S 31 - -/* SPI_CLKDIV_PRE : R/W; bitpos: [21:18]; default: 0; - * In the master mode it is pre-divider of spi_clk. Can be configured in - * CONF state. - */ - -#define SPI_CLKDIV_PRE 0x0000000F -#define SPI_CLKDIV_PRE_M (SPI_CLKDIV_PRE_V << SPI_CLKDIV_PRE_S) -#define SPI_CLKDIV_PRE_V 0x0000000F -#define SPI_CLKDIV_PRE_S 18 - -/* SPI_CLKCNT_N : R/W; bitpos: [17:12]; default: 3; - * In the master mode it is the divider of spi_clk. So spi_clk frequency is - * system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF - * state. - */ - -#define SPI_CLKCNT_N 0x0000003F -#define SPI_CLKCNT_N_M (SPI_CLKCNT_N_V << SPI_CLKCNT_N_S) -#define SPI_CLKCNT_N_V 0x0000003F -#define SPI_CLKCNT_N_S 12 - -/* SPI_CLKCNT_H : R/W; bitpos: [11:6]; default: 1; - * In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave - * mode it must be 0. Can be configured in CONF state. - */ - -#define SPI_CLKCNT_H 0x0000003F -#define SPI_CLKCNT_H_M (SPI_CLKCNT_H_V << SPI_CLKCNT_H_S) -#define SPI_CLKCNT_H_V 0x0000003F -#define SPI_CLKCNT_H_S 6 - -/* SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3; - * In the master mode it must be equal to spi_clkcnt_N. In the slave mode it - * must be 0. Can be configured in CONF state. - */ - -#define SPI_CLKCNT_L 0x0000003F -#define SPI_CLKCNT_L_M (SPI_CLKCNT_L_V << SPI_CLKCNT_L_S) -#define SPI_CLKCNT_L_V 0x0000003F -#define SPI_CLKCNT_L_S 0 - -/* SPI_USER_REG register - * SPI USER control register - */ - -#define SPI_USER_REG (DR_REG_SPI2_BASE + 0x10) - -/* SPI_USR_COMMAND : R/W; bitpos: [31]; default: 1; - * This bit enable the command phase of an operation. Can be configured in - * CONF state. - */ - -#define SPI_USR_COMMAND (BIT(31)) -#define SPI_USR_COMMAND_M (SPI_USR_COMMAND_V << SPI_USR_COMMAND_S) -#define SPI_USR_COMMAND_V 0x00000001 -#define SPI_USR_COMMAND_S 31 - -/* SPI_USR_ADDR : R/W; bitpos: [30]; default: 0; - * This bit enable the address phase of an operation. Can be configured in - * CONF state. - */ - -#define SPI_USR_ADDR (BIT(30)) -#define SPI_USR_ADDR_M (SPI_USR_ADDR_V << SPI_USR_ADDR_S) -#define SPI_USR_ADDR_V 0x00000001 -#define SPI_USR_ADDR_S 30 - -/* SPI_USR_DUMMY : R/W; bitpos: [29]; default: 0; - * This bit enable the dummy phase of an operation. Can be configured in - * CONF state. - */ - -#define SPI_USR_DUMMY (BIT(29)) -#define SPI_USR_DUMMY_M (SPI_USR_DUMMY_V << SPI_USR_DUMMY_S) -#define SPI_USR_DUMMY_V 0x00000001 -#define SPI_USR_DUMMY_S 29 - -/* SPI_USR_MISO : R/W; bitpos: [28]; default: 0; - * This bit enable the read-data phase of an operation. Can be configured in - * CONF state. - */ - -#define SPI_USR_MISO (BIT(28)) -#define SPI_USR_MISO_M (SPI_USR_MISO_V << SPI_USR_MISO_S) -#define SPI_USR_MISO_V 0x00000001 -#define SPI_USR_MISO_S 28 - -/* SPI_USR_MOSI : R/W; bitpos: [27]; default: 0; - * This bit enable the write-data phase of an operation. Can be configured - * in CONF state. - */ - -#define SPI_USR_MOSI (BIT(27)) -#define SPI_USR_MOSI_M (SPI_USR_MOSI_V << SPI_USR_MOSI_S) -#define SPI_USR_MOSI_V 0x00000001 -#define SPI_USR_MOSI_S 27 - -/* SPI_USR_DUMMY_IDLE : R/W; bitpos: [26]; default: 0; - * spi clock is disable in dummy phase when the bit is enable. Can be - * configured in CONF state. - */ - -#define SPI_USR_DUMMY_IDLE (BIT(26)) -#define SPI_USR_DUMMY_IDLE_M (SPI_USR_DUMMY_IDLE_V << SPI_USR_DUMMY_IDLE_S) -#define SPI_USR_DUMMY_IDLE_V 0x00000001 -#define SPI_USR_DUMMY_IDLE_S 26 - -/* SPI_USR_MOSI_HIGHPART : R/W; bitpos: [25]; default: 0; - * write-data phase only access to high-part of the buffer spi_w8~spi_w15. - * 1: enable 0: disable. Can be configured in CONF state. - */ - -#define SPI_USR_MOSI_HIGHPART (BIT(25)) -#define SPI_USR_MOSI_HIGHPART_M (SPI_USR_MOSI_HIGHPART_V << SPI_USR_MOSI_HIGHPART_S) -#define SPI_USR_MOSI_HIGHPART_V 0x00000001 -#define SPI_USR_MOSI_HIGHPART_S 25 - -/* SPI_USR_MISO_HIGHPART : R/W; bitpos: [24]; default: 0; - * read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: - * enable 0: disable. Can be configured in CONF state. - */ - -#define SPI_USR_MISO_HIGHPART (BIT(24)) -#define SPI_USR_MISO_HIGHPART_M (SPI_USR_MISO_HIGHPART_V << SPI_USR_MISO_HIGHPART_S) -#define SPI_USR_MISO_HIGHPART_V 0x00000001 -#define SPI_USR_MISO_HIGHPART_S 24 - -/* SPI_SIO : R/W; bitpos: [17]; default: 0; - * Set the bit to enable 3-line half duplex communication mosi and miso - * signals share the same pin. 1: enable 0: disable. Can be configured in - * CONF state. - */ - -#define SPI_SIO (BIT(17)) -#define SPI_SIO_M (SPI_SIO_V << SPI_SIO_S) -#define SPI_SIO_V 0x00000001 -#define SPI_SIO_S 17 - -/* SPI_USR_CONF_NXT : R/W; bitpos: [15]; default: 0; - * 1: Enable the DMA CONF phase of next seg-trans operation, which means - * seg-trans will continue. 0: The seg-trans will end after the current SPI - * seg-trans or this is not seg-trans mode. Can be configured in CONF state. - */ - -#define SPI_USR_CONF_NXT (BIT(15)) -#define SPI_USR_CONF_NXT_M (SPI_USR_CONF_NXT_V << SPI_USR_CONF_NXT_S) -#define SPI_USR_CONF_NXT_V 0x00000001 -#define SPI_USR_CONF_NXT_S 15 - -/* SPI_FWRITE_QUAD : R/W; bitpos: [13]; default: 0; - * In the write operations read-data phase apply 4 signals. Can be - * configured in CONF state. - */ - -#define SPI_FWRITE_QUAD (BIT(13)) -#define SPI_FWRITE_QUAD_M (SPI_FWRITE_QUAD_V << SPI_FWRITE_QUAD_S) -#define SPI_FWRITE_QUAD_V 0x00000001 -#define SPI_FWRITE_QUAD_S 13 - -/* SPI_FWRITE_DUAL : R/W; bitpos: [12]; default: 0; - * In the write operations read-data phase apply 2 signals. Can be - * configured in CONF state. - */ - -#define SPI_FWRITE_DUAL (BIT(12)) -#define SPI_FWRITE_DUAL_M (SPI_FWRITE_DUAL_V << SPI_FWRITE_DUAL_S) -#define SPI_FWRITE_DUAL_V 0x00000001 -#define SPI_FWRITE_DUAL_S 12 - -/* SPI_CK_OUT_EDGE : R/W; bitpos: [9]; default: 0; - * the bit combined with spi_mosi_delay_mode bits to set mosi signal delay - * mode. Can be configured in CONF state. - */ - -#define SPI_CK_OUT_EDGE (BIT(9)) -#define SPI_CK_OUT_EDGE_M (SPI_CK_OUT_EDGE_V << SPI_CK_OUT_EDGE_S) -#define SPI_CK_OUT_EDGE_V 0x00000001 -#define SPI_CK_OUT_EDGE_S 9 - -/* SPI_RSCK_I_EDGE : R/W; bitpos: [8]; default: 0; - * In the slave mode, this bit can be used to change the polarity of rsck. - * 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i. - */ - -#define SPI_RSCK_I_EDGE (BIT(8)) -#define SPI_RSCK_I_EDGE_M (SPI_RSCK_I_EDGE_V << SPI_RSCK_I_EDGE_S) -#define SPI_RSCK_I_EDGE_V 0x00000001 -#define SPI_RSCK_I_EDGE_S 8 - -/* SPI_CS_SETUP : R/W; bitpos: [7]; default: 1; - * spi cs is enable when spi is in prepare phase. 1: enable 0: disable. - * Can be configured in CONF state. - */ - -#define SPI_CS_SETUP (BIT(7)) -#define SPI_CS_SETUP_M (SPI_CS_SETUP_V << SPI_CS_SETUP_S) -#define SPI_CS_SETUP_V 0x00000001 -#define SPI_CS_SETUP_S 7 - -/* SPI_CS_HOLD : R/W; bitpos: [6]; default: 1; - * spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be - * configured in CONF state. - */ - -#define SPI_CS_HOLD (BIT(6)) -#define SPI_CS_HOLD_M (SPI_CS_HOLD_V << SPI_CS_HOLD_S) -#define SPI_CS_HOLD_V 0x00000001 -#define SPI_CS_HOLD_S 6 - -/* SPI_TSCK_I_EDGE : R/W; bitpos: [5]; default: 0; - * In the slave mode, this bit can be used to change the polarity of tsck. - * 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i. - */ - -#define SPI_TSCK_I_EDGE (BIT(5)) -#define SPI_TSCK_I_EDGE_M (SPI_TSCK_I_EDGE_V << SPI_TSCK_I_EDGE_S) -#define SPI_TSCK_I_EDGE_V 0x00000001 -#define SPI_TSCK_I_EDGE_S 5 - -/* SPI_QPI_MODE : R/W/SS/SC; bitpos: [3]; default: 0; - * Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: - * others. Can be configured in CONF state. - */ - -#define SPI_QPI_MODE (BIT(3)) -#define SPI_QPI_MODE_M (SPI_QPI_MODE_V << SPI_QPI_MODE_S) -#define SPI_QPI_MODE_V 0x00000001 -#define SPI_QPI_MODE_S 3 - -/* SPI_DOUTDIN : R/W; bitpos: [0]; default: 0; - * Set the bit to enable full duplex communication. 1: enable 0: disable. - * Can be configured in CONF state. - */ - -#define SPI_DOUTDIN (BIT(0)) -#define SPI_DOUTDIN_M (SPI_DOUTDIN_V << SPI_DOUTDIN_S) -#define SPI_DOUTDIN_V 0x00000001 -#define SPI_DOUTDIN_S 0 - -/* SPI_USER1_REG register - * SPI USER control register 1 - */ - -#define SPI_USER1_REG (DR_REG_SPI2_BASE + 0x14) - -/* SPI_USR_ADDR_BITLEN : R/W; bitpos: [31:27]; default: 23; - * The length in bits of address phase. The register value shall be - * (bit_num-1). Can be configured in CONF state. - */ - -#define SPI_USR_ADDR_BITLEN 0x0000001F -#define SPI_USR_ADDR_BITLEN_M (SPI_USR_ADDR_BITLEN_V << SPI_USR_ADDR_BITLEN_S) -#define SPI_USR_ADDR_BITLEN_V 0x0000001F -#define SPI_USR_ADDR_BITLEN_S 27 - -/* SPI_CS_HOLD_TIME : R/W; bitpos: [26:22]; default: 1; - * delay cycles of cs pin by spi clock this bits are combined with - * spi_cs_hold bit. Can be configured in CONF state. - */ - -#define SPI_CS_HOLD_TIME 0x0000001F -#define SPI_CS_HOLD_TIME_M (SPI_CS_HOLD_TIME_V << SPI_CS_HOLD_TIME_S) -#define SPI_CS_HOLD_TIME_V 0x0000001F -#define SPI_CS_HOLD_TIME_S 22 - -/* SPI_CS_SETUP_TIME : R/W; bitpos: [21:17]; default: 0; - * (cycles+1) of prepare phase by spi clock this bits are combined with - * spi_cs_setup bit. Can be configured in CONF state. - */ - -#define SPI_CS_SETUP_TIME 0x0000001F -#define SPI_CS_SETUP_TIME_M (SPI_CS_SETUP_TIME_V << SPI_CS_SETUP_TIME_S) -#define SPI_CS_SETUP_TIME_V 0x0000001F -#define SPI_CS_SETUP_TIME_S 17 - -/* SPI_MST_WFULL_ERR_END_EN : R/W; bitpos: [16]; default: 1; - * 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI - * master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull - * error is valid in GP-SPI master FD/HD-mode. - */ - -#define SPI_MST_WFULL_ERR_END_EN (BIT(16)) -#define SPI_MST_WFULL_ERR_END_EN_M (SPI_MST_WFULL_ERR_END_EN_V << SPI_MST_WFULL_ERR_END_EN_S) -#define SPI_MST_WFULL_ERR_END_EN_V 0x00000001 -#define SPI_MST_WFULL_ERR_END_EN_S 16 - -/* SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7; - * The length in spi_clk cycles of dummy phase. The register value shall be - * (cycle_num-1). Can be configured in CONF state. - */ - -#define SPI_USR_DUMMY_CYCLELEN 0x000000FF -#define SPI_USR_DUMMY_CYCLELEN_M (SPI_USR_DUMMY_CYCLELEN_V << SPI_USR_DUMMY_CYCLELEN_S) -#define SPI_USR_DUMMY_CYCLELEN_V 0x000000FF -#define SPI_USR_DUMMY_CYCLELEN_S 0 - -/* SPI_USER2_REG register - * SPI USER control register 2 - */ - -#define SPI_USER2_REG (DR_REG_SPI2_BASE + 0x18) - -/* SPI_USR_COMMAND_BITLEN : R/W; bitpos: [31:28]; default: 7; - * The length in bits of command phase. The register value shall be - * (bit_num-1). Can be configured in CONF state. - */ - -#define SPI_USR_COMMAND_BITLEN 0x0000000F -#define SPI_USR_COMMAND_BITLEN_M (SPI_USR_COMMAND_BITLEN_V << SPI_USR_COMMAND_BITLEN_S) -#define SPI_USR_COMMAND_BITLEN_V 0x0000000F -#define SPI_USR_COMMAND_BITLEN_S 28 - -/* SPI_MST_REMPTY_ERR_END_EN : R/W; bitpos: [27]; default: 1; - * 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in - * GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO - * read empty error is valid in GP-SPI master FD/HD-mode. - */ - -#define SPI_MST_REMPTY_ERR_END_EN (BIT(27)) -#define SPI_MST_REMPTY_ERR_END_EN_M (SPI_MST_REMPTY_ERR_END_EN_V << SPI_MST_REMPTY_ERR_END_EN_S) -#define SPI_MST_REMPTY_ERR_END_EN_V 0x00000001 -#define SPI_MST_REMPTY_ERR_END_EN_S 27 - -/* SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0; - * The value of command. Can be configured in CONF state. - */ - -#define SPI_USR_COMMAND_VALUE 0x0000FFFF -#define SPI_USR_COMMAND_VALUE_M (SPI_USR_COMMAND_VALUE_V << SPI_USR_COMMAND_VALUE_S) -#define SPI_USR_COMMAND_VALUE_V 0x0000FFFF -#define SPI_USR_COMMAND_VALUE_S 0 - -/* SPI_MS_DLEN_REG register - * SPI data bit length control register - */ - -#define SPI_MS_DLEN_REG (DR_REG_SPI2_BASE + 0x1c) - -/* SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0; - * The value of these bits is the configured SPI transmission data bit - * length in master mode DMA controlled transfer or CPU controlled transfer. - * The value is also the configured bit length in slave mode DMA RX - * controlled transfer. The register value shall be (bit_num-1). Can be - * configured in CONF state. - */ - -#define SPI_MS_DATA_BITLEN 0x0003FFFF -#define SPI_MS_DATA_BITLEN_M (SPI_MS_DATA_BITLEN_V << SPI_MS_DATA_BITLEN_S) -#define SPI_MS_DATA_BITLEN_V 0x0003FFFF -#define SPI_MS_DATA_BITLEN_S 0 - -/* SPI_MISC_REG register - * SPI misc register - */ - -#define SPI_MISC_REG (DR_REG_SPI2_BASE + 0x20) - -/* SPI_QUAD_DIN_PIN_SWAP : R/W; bitpos: [31]; default: 0; - * 1: spi quad input swap enable 0: spi quad input swap disable. Can be - * configured in CONF state. - */ - -#define SPI_QUAD_DIN_PIN_SWAP (BIT(31)) -#define SPI_QUAD_DIN_PIN_SWAP_M (SPI_QUAD_DIN_PIN_SWAP_V << SPI_QUAD_DIN_PIN_SWAP_S) -#define SPI_QUAD_DIN_PIN_SWAP_V 0x00000001 -#define SPI_QUAD_DIN_PIN_SWAP_S 31 - -/* SPI_CS_KEEP_ACTIVE : R/W; bitpos: [30]; default: 0; - * spi cs line keep low when the bit is set. Can be configured in CONF state. - */ - -#define SPI_CS_KEEP_ACTIVE (BIT(30)) -#define SPI_CS_KEEP_ACTIVE_M (SPI_CS_KEEP_ACTIVE_V << SPI_CS_KEEP_ACTIVE_S) -#define SPI_CS_KEEP_ACTIVE_V 0x00000001 -#define SPI_CS_KEEP_ACTIVE_S 30 - -/* SPI_CK_IDLE_EDGE : R/W; bitpos: [29]; default: 0; - * 1: spi clk line is high when idle 0: spi clk line is low when idle. - * Can be configured in CONF state. - */ - -#define SPI_CK_IDLE_EDGE (BIT(29)) -#define SPI_CK_IDLE_EDGE_M (SPI_CK_IDLE_EDGE_V << SPI_CK_IDLE_EDGE_S) -#define SPI_CK_IDLE_EDGE_V 0x00000001 -#define SPI_CK_IDLE_EDGE_S 29 - -/* SPI_SLAVE_CS_POL : R/W; bitpos: [23]; default: 0; - * spi slave input cs polarity select. 1: inv 0: not change. Can be - * configured in CONF state. - */ - -#define SPI_SLAVE_CS_POL (BIT(23)) -#define SPI_SLAVE_CS_POL_M (SPI_SLAVE_CS_POL_V << SPI_SLAVE_CS_POL_S) -#define SPI_SLAVE_CS_POL_V 0x00000001 -#define SPI_SLAVE_CS_POL_S 23 - -/* SPI_MASTER_CS_POL : R/W; bitpos: [12:7]; default: 0; - * In the master mode the bits are the polarity of spi cs line, the value is - * equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state. - */ - -#define SPI_MASTER_CS_POL 0x0000003F -#define SPI_MASTER_CS_POL_M (SPI_MASTER_CS_POL_V << SPI_MASTER_CS_POL_S) -#define SPI_MASTER_CS_POL_V 0x0000003F -#define SPI_MASTER_CS_POL_S 7 - -/* SPI_CK_DIS : R/W; bitpos: [6]; default: 0; - * 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF - * state. - */ - -#define SPI_CK_DIS (BIT(6)) -#define SPI_CK_DIS_M (SPI_CK_DIS_V << SPI_CK_DIS_S) -#define SPI_CK_DIS_V 0x00000001 -#define SPI_CK_DIS_S 6 - -/* SPI_CS5_DIS : R/W; bitpos: [5]; default: 1; - * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n - * pin. Can be configured in CONF state. - */ - -#define SPI_CS5_DIS (BIT(5)) -#define SPI_CS5_DIS_M (SPI_CS5_DIS_V << SPI_CS5_DIS_S) -#define SPI_CS5_DIS_V 0x00000001 -#define SPI_CS5_DIS_S 5 - -/* SPI_CS4_DIS : R/W; bitpos: [4]; default: 1; - * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n - * pin. Can be configured in CONF state. - */ - -#define SPI_CS4_DIS (BIT(4)) -#define SPI_CS4_DIS_M (SPI_CS4_DIS_V << SPI_CS4_DIS_S) -#define SPI_CS4_DIS_V 0x00000001 -#define SPI_CS4_DIS_S 4 - -/* SPI_CS3_DIS : R/W; bitpos: [3]; default: 1; - * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n - * pin. Can be configured in CONF state. - */ - -#define SPI_CS3_DIS (BIT(3)) -#define SPI_CS3_DIS_M (SPI_CS3_DIS_V << SPI_CS3_DIS_S) -#define SPI_CS3_DIS_V 0x00000001 -#define SPI_CS3_DIS_S 3 - -/* SPI_CS2_DIS : R/W; bitpos: [2]; default: 1; - * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n - * pin. Can be configured in CONF state. - */ - -#define SPI_CS2_DIS (BIT(2)) -#define SPI_CS2_DIS_M (SPI_CS2_DIS_V << SPI_CS2_DIS_S) -#define SPI_CS2_DIS_V 0x00000001 -#define SPI_CS2_DIS_S 2 - -/* SPI_CS1_DIS : R/W; bitpos: [1]; default: 1; - * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n - * pin. Can be configured in CONF state. - */ - -#define SPI_CS1_DIS (BIT(1)) -#define SPI_CS1_DIS_M (SPI_CS1_DIS_V << SPI_CS1_DIS_S) -#define SPI_CS1_DIS_V 0x00000001 -#define SPI_CS1_DIS_S 1 - -/* SPI_CS0_DIS : R/W; bitpos: [0]; default: 0; - * SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n - * pin. Can be configured in CONF state. - */ - -#define SPI_CS0_DIS (BIT(0)) -#define SPI_CS0_DIS_M (SPI_CS0_DIS_V << SPI_CS0_DIS_S) -#define SPI_CS0_DIS_V 0x00000001 -#define SPI_CS0_DIS_S 0 - -/* SPI_DIN_MODE_REG register - * SPI input delay mode configuration - */ - -#define SPI_DIN_MODE_REG (DR_REG_SPI2_BASE + 0x24) - -/* SPI_TIMING_HCLK_ACTIVE : R/W; bitpos: [16]; default: 0; - * 1:enable hclk in SPI input timing module. 0: disable it. Can be - * configured in CONF state. - */ - -#define SPI_TIMING_HCLK_ACTIVE (BIT(16)) -#define SPI_TIMING_HCLK_ACTIVE_M (SPI_TIMING_HCLK_ACTIVE_V << SPI_TIMING_HCLK_ACTIVE_S) -#define SPI_TIMING_HCLK_ACTIVE_V 0x00000001 -#define SPI_TIMING_HCLK_ACTIVE_S 16 - -/* SPI_DIN3_MODE : R/W; bitpos: [7:6]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: input - * without delayed, 1: input with the posedge of clk_apb,2 input with the - * negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF - * state. - */ - -#define SPI_DIN3_MODE 0x00000003 -#define SPI_DIN3_MODE_M (SPI_DIN3_MODE_V << SPI_DIN3_MODE_S) -#define SPI_DIN3_MODE_V 0x00000003 -#define SPI_DIN3_MODE_S 6 - -/* SPI_DIN2_MODE : R/W; bitpos: [5:4]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: input - * without delayed, 1: input with the posedge of clk_apb,2 input with the - * negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF - * state. - */ - -#define SPI_DIN2_MODE 0x00000003 -#define SPI_DIN2_MODE_M (SPI_DIN2_MODE_V << SPI_DIN2_MODE_S) -#define SPI_DIN2_MODE_V 0x00000003 -#define SPI_DIN2_MODE_S 4 - -/* SPI_DIN1_MODE : R/W; bitpos: [3:2]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: input - * without delayed, 1: input with the posedge of clk_apb,2 input with the - * negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF - * state. - */ - -#define SPI_DIN1_MODE 0x00000003 -#define SPI_DIN1_MODE_M (SPI_DIN1_MODE_V << SPI_DIN1_MODE_S) -#define SPI_DIN1_MODE_V 0x00000003 -#define SPI_DIN1_MODE_S 2 - -/* SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: input - * without delayed, 1: input with the posedge of clk_apb,2 input with the - * negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF - * state. - */ - -#define SPI_DIN0_MODE 0x00000003 -#define SPI_DIN0_MODE_M (SPI_DIN0_MODE_V << SPI_DIN0_MODE_S) -#define SPI_DIN0_MODE_V 0x00000003 -#define SPI_DIN0_MODE_S 0 - -/* SPI_DIN_NUM_REG register - * SPI input delay number configuration - */ - -#define SPI_DIN_NUM_REG (DR_REG_SPI2_BASE + 0x28) - -/* SPI_DIN3_NUM : R/W; bitpos: [7:6]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 - * cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - */ - -#define SPI_DIN3_NUM 0x00000003 -#define SPI_DIN3_NUM_M (SPI_DIN3_NUM_V << SPI_DIN3_NUM_S) -#define SPI_DIN3_NUM_V 0x00000003 -#define SPI_DIN3_NUM_S 6 - -/* SPI_DIN2_NUM : R/W; bitpos: [5:4]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 - * cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - */ - -#define SPI_DIN2_NUM 0x00000003 -#define SPI_DIN2_NUM_M (SPI_DIN2_NUM_V << SPI_DIN2_NUM_S) -#define SPI_DIN2_NUM_V 0x00000003 -#define SPI_DIN2_NUM_S 4 - -/* SPI_DIN1_NUM : R/W; bitpos: [3:2]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 - * cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - */ - -#define SPI_DIN1_NUM 0x00000003 -#define SPI_DIN1_NUM_M (SPI_DIN1_NUM_V << SPI_DIN1_NUM_S) -#define SPI_DIN1_NUM_V 0x00000003 -#define SPI_DIN1_NUM_S 2 - -/* SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0; - * the input signals are delayed by SPI module clock cycles, 0: delayed by 1 - * cycle, 1: delayed by 2 cycles,... Can be configured in CONF state. - */ - -#define SPI_DIN0_NUM 0x00000003 -#define SPI_DIN0_NUM_M (SPI_DIN0_NUM_V << SPI_DIN0_NUM_S) -#define SPI_DIN0_NUM_V 0x00000003 -#define SPI_DIN0_NUM_S 0 - -/* SPI_DOUT_MODE_REG register - * SPI output delay mode configuration - */ - -#define SPI_DOUT_MODE_REG (DR_REG_SPI2_BASE + 0x2c) - -/* SPI_DOUT3_MODE : R/W; bitpos: [3]; default: 0; - * The output signal $n is delayed by the SPI module clock, 0: output - * without delayed, 1: output delay for a SPI module clock cycle at its - * negative edge. Can be configured in CONF state. - */ - -#define SPI_DOUT3_MODE (BIT(3)) -#define SPI_DOUT3_MODE_M (SPI_DOUT3_MODE_V << SPI_DOUT3_MODE_S) -#define SPI_DOUT3_MODE_V 0x00000001 -#define SPI_DOUT3_MODE_S 3 - -/* SPI_DOUT2_MODE : R/W; bitpos: [2]; default: 0; - * The output signal $n is delayed by the SPI module clock, 0: output - * without delayed, 1: output delay for a SPI module clock cycle at its - * negative edge. Can be configured in CONF state. - */ - -#define SPI_DOUT2_MODE (BIT(2)) -#define SPI_DOUT2_MODE_M (SPI_DOUT2_MODE_V << SPI_DOUT2_MODE_S) -#define SPI_DOUT2_MODE_V 0x00000001 -#define SPI_DOUT2_MODE_S 2 - -/* SPI_DOUT1_MODE : R/W; bitpos: [1]; default: 0; - * The output signal $n is delayed by the SPI module clock, 0: output - * without delayed, 1: output delay for a SPI module clock cycle at its - * negative edge. Can be configured in CONF state. - */ - -#define SPI_DOUT1_MODE (BIT(1)) -#define SPI_DOUT1_MODE_M (SPI_DOUT1_MODE_V << SPI_DOUT1_MODE_S) -#define SPI_DOUT1_MODE_V 0x00000001 -#define SPI_DOUT1_MODE_S 1 - -/* SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0; - * The output signal $n is delayed by the SPI module clock, 0: output - * without delayed, 1: output delay for a SPI module clock cycle at its - * negative edge. Can be configured in CONF state. - */ - -#define SPI_DOUT0_MODE (BIT(0)) -#define SPI_DOUT0_MODE_M (SPI_DOUT0_MODE_V << SPI_DOUT0_MODE_S) -#define SPI_DOUT0_MODE_V 0x00000001 -#define SPI_DOUT0_MODE_S 0 - -/* SPI_DMA_CONF_REG register - * SPI DMA control register - */ - -#define SPI_DMA_CONF_REG (DR_REG_SPI2_BASE + 0x30) - -/* SPI_DMA_AFIFO_RST : WT; bitpos: [31]; default: 0; - * Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI - * slave DMA controlled mode transfer. - */ - -#define SPI_DMA_AFIFO_RST (BIT(31)) -#define SPI_DMA_AFIFO_RST_M (SPI_DMA_AFIFO_RST_V << SPI_DMA_AFIFO_RST_S) -#define SPI_DMA_AFIFO_RST_V 0x00000001 -#define SPI_DMA_AFIFO_RST_S 31 - -/* SPI_BUF_AFIFO_RST : WT; bitpos: [30]; default: 0; - * Set this bit to reset BUF TX AFIFO, which is used send data out in SPI - * slave CPU controlled mode transfer and master mode transfer. - */ - -#define SPI_BUF_AFIFO_RST (BIT(30)) -#define SPI_BUF_AFIFO_RST_M (SPI_BUF_AFIFO_RST_V << SPI_BUF_AFIFO_RST_S) -#define SPI_BUF_AFIFO_RST_V 0x00000001 -#define SPI_BUF_AFIFO_RST_S 30 - -/* SPI_RX_AFIFO_RST : WT; bitpos: [29]; default: 0; - * Set this bit to reset RX AFIFO, which is used to receive data in SPI - * master and slave mode transfer. - */ - -#define SPI_RX_AFIFO_RST (BIT(29)) -#define SPI_RX_AFIFO_RST_M (SPI_RX_AFIFO_RST_V << SPI_RX_AFIFO_RST_S) -#define SPI_RX_AFIFO_RST_V 0x00000001 -#define SPI_RX_AFIFO_RST_S 29 - -/* SPI_DMA_TX_ENA : R/W; bitpos: [28]; default: 0; - * Set this bit to enable SPI DMA controlled send data mode. - */ - -#define SPI_DMA_TX_ENA (BIT(28)) -#define SPI_DMA_TX_ENA_M (SPI_DMA_TX_ENA_V << SPI_DMA_TX_ENA_S) -#define SPI_DMA_TX_ENA_V 0x00000001 -#define SPI_DMA_TX_ENA_S 28 - -/* SPI_DMA_RX_ENA : R/W; bitpos: [27]; default: 0; - * Set this bit to enable SPI DMA controlled receive data mode. - */ - -#define SPI_DMA_RX_ENA (BIT(27)) -#define SPI_DMA_RX_ENA_M (SPI_DMA_RX_ENA_V << SPI_DMA_RX_ENA_S) -#define SPI_DMA_RX_ENA_V 0x00000001 -#define SPI_DMA_RX_ENA_S 27 - -/* SPI_RX_EOF_EN : R/W; bitpos: [21]; default: 0; - * 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is - * equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma - * transition. 0: spi_dma_inlink_eof is set by spi_trans_done in - * non-seg-trans or spi_dma_seg_trans_done in seg-trans. - */ - -#define SPI_RX_EOF_EN (BIT(21)) -#define SPI_RX_EOF_EN_M (SPI_RX_EOF_EN_V << SPI_RX_EOF_EN_S) -#define SPI_RX_EOF_EN_V 0x00000001 -#define SPI_RX_EOF_EN_S 21 - -/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W; bitpos: [20]; default: 0; - * 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: - * spi_dma_outfifo_empty_vld is cleared by spi_trans_done. - */ - -#define SPI_SLV_TX_SEG_TRANS_CLR_EN (BIT(20)) -#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M (SPI_SLV_TX_SEG_TRANS_CLR_EN_V << SPI_SLV_TX_SEG_TRANS_CLR_EN_S) -#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V 0x00000001 -#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S 20 - -/* SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W; bitpos: [19]; default: 0; - * 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: - * spi_dma_infifo_full_vld is cleared by spi_trans_done. - */ - -#define SPI_SLV_RX_SEG_TRANS_CLR_EN (BIT(19)) -#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M (SPI_SLV_RX_SEG_TRANS_CLR_EN_V << SPI_SLV_RX_SEG_TRANS_CLR_EN_S) -#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V 0x00000001 -#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 - -/* SPI_DMA_SLV_SEG_TRANS_EN : R/W; bitpos: [18]; default: 0; - * Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: - * disable. - */ - -#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) -#define SPI_DMA_SLV_SEG_TRANS_EN_M (SPI_DMA_SLV_SEG_TRANS_EN_V << SPI_DMA_SLV_SEG_TRANS_EN_S) -#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x00000001 -#define SPI_DMA_SLV_SEG_TRANS_EN_S 18 - -/* SPI_DMA_INT_ENA_REG register - * SPI DMA interrupt enable register - */ - -#define SPI_DMA_INT_ENA_REG (DR_REG_SPI2_BASE + 0x34) - -/* SPI_APP1_INT_ENA : R/W; bitpos: [20]; default: 0; - * The enable bit for SPI_APP1_INT interrupt. - */ - -#define SPI_APP1_INT_ENA (BIT(20)) -#define SPI_APP1_INT_ENA_M (SPI_APP1_INT_ENA_V << SPI_APP1_INT_ENA_S) -#define SPI_APP1_INT_ENA_V 0x00000001 -#define SPI_APP1_INT_ENA_S 20 - -/* SPI_APP2_INT_ENA : R/W; bitpos: [19]; default: 0; - * The enable bit for SPI_APP2_INT interrupt. - */ - -#define SPI_APP2_INT_ENA (BIT(19)) -#define SPI_APP2_INT_ENA_M (SPI_APP2_INT_ENA_V << SPI_APP2_INT_ENA_S) -#define SPI_APP2_INT_ENA_V 0x00000001 -#define SPI_APP2_INT_ENA_S 19 - -/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA : R/W; bitpos: [18]; default: 0; - * The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - */ - -#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA (BIT(18)) -#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S) -#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_V 0x00000001 -#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ENA_S 18 - -/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W; bitpos: [17]; default: 0; - * The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - */ - -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA (BIT(17)) -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S) -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V 0x00000001 -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S 17 - -/* SPI_SLV_CMD_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; - * The enable bit for SPI_SLV_CMD_ERR_INT interrupt. - */ - -#define SPI_SLV_CMD_ERR_INT_ENA (BIT(16)) -#define SPI_SLV_CMD_ERR_INT_ENA_M (SPI_SLV_CMD_ERR_INT_ENA_V << SPI_SLV_CMD_ERR_INT_ENA_S) -#define SPI_SLV_CMD_ERR_INT_ENA_V 0x00000001 -#define SPI_SLV_CMD_ERR_INT_ENA_S 16 - -/* SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; - * The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. - */ - -#define SPI_SLV_BUF_ADDR_ERR_INT_ENA (BIT(15)) -#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M (SPI_SLV_BUF_ADDR_ERR_INT_ENA_V << SPI_SLV_BUF_ADDR_ERR_INT_ENA_S) -#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V 0x00000001 -#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S 15 - -/* SPI_SEG_MAGIC_ERR_INT_ENA : R/W; bitpos: [14]; default: 0; - * The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt. - */ - -#define SPI_SEG_MAGIC_ERR_INT_ENA (BIT(14)) -#define SPI_SEG_MAGIC_ERR_INT_ENA_M (SPI_SEG_MAGIC_ERR_INT_ENA_V << SPI_SEG_MAGIC_ERR_INT_ENA_S) -#define SPI_SEG_MAGIC_ERR_INT_ENA_V 0x00000001 -#define SPI_SEG_MAGIC_ERR_INT_ENA_S 14 - -/* SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; - * The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. - */ - -#define SPI_DMA_SEG_TRANS_DONE_INT_ENA (BIT(13)) -#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M (SPI_DMA_SEG_TRANS_DONE_INT_ENA_V << SPI_DMA_SEG_TRANS_DONE_INT_ENA_S) -#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V 0x00000001 -#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S 13 - -/* SPI_TRANS_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; - * The enable bit for SPI_TRANS_DONE_INT interrupt. - */ - -#define SPI_TRANS_DONE_INT_ENA (BIT(12)) -#define SPI_TRANS_DONE_INT_ENA_M (SPI_TRANS_DONE_INT_ENA_V << SPI_TRANS_DONE_INT_ENA_S) -#define SPI_TRANS_DONE_INT_ENA_V 0x00000001 -#define SPI_TRANS_DONE_INT_ENA_S 12 - -/* SPI_SLV_WR_BUF_DONE_INT_ENA : R/W; bitpos: [11]; default: 0; - * The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt. - */ - -#define SPI_SLV_WR_BUF_DONE_INT_ENA (BIT(11)) -#define SPI_SLV_WR_BUF_DONE_INT_ENA_M (SPI_SLV_WR_BUF_DONE_INT_ENA_V << SPI_SLV_WR_BUF_DONE_INT_ENA_S) -#define SPI_SLV_WR_BUF_DONE_INT_ENA_V 0x00000001 -#define SPI_SLV_WR_BUF_DONE_INT_ENA_S 11 - -/* SPI_SLV_RD_BUF_DONE_INT_ENA : R/W; bitpos: [10]; default: 0; - * The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt. - */ - -#define SPI_SLV_RD_BUF_DONE_INT_ENA (BIT(10)) -#define SPI_SLV_RD_BUF_DONE_INT_ENA_M (SPI_SLV_RD_BUF_DONE_INT_ENA_V << SPI_SLV_RD_BUF_DONE_INT_ENA_S) -#define SPI_SLV_RD_BUF_DONE_INT_ENA_V 0x00000001 -#define SPI_SLV_RD_BUF_DONE_INT_ENA_S 10 - -/* SPI_SLV_WR_DMA_DONE_INT_ENA : R/W; bitpos: [9]; default: 0; - * The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt. - */ - -#define SPI_SLV_WR_DMA_DONE_INT_ENA (BIT(9)) -#define SPI_SLV_WR_DMA_DONE_INT_ENA_M (SPI_SLV_WR_DMA_DONE_INT_ENA_V << SPI_SLV_WR_DMA_DONE_INT_ENA_S) -#define SPI_SLV_WR_DMA_DONE_INT_ENA_V 0x00000001 -#define SPI_SLV_WR_DMA_DONE_INT_ENA_S 9 - -/* SPI_SLV_RD_DMA_DONE_INT_ENA : R/W; bitpos: [8]; default: 0; - * The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt. - */ - -#define SPI_SLV_RD_DMA_DONE_INT_ENA (BIT(8)) -#define SPI_SLV_RD_DMA_DONE_INT_ENA_M (SPI_SLV_RD_DMA_DONE_INT_ENA_V << SPI_SLV_RD_DMA_DONE_INT_ENA_S) -#define SPI_SLV_RD_DMA_DONE_INT_ENA_V 0x00000001 -#define SPI_SLV_RD_DMA_DONE_INT_ENA_S 8 - -/* SPI_SLV_CMDA_INT_ENA : R/W; bitpos: [7]; default: 0; - * The enable bit for SPI slave CMDA interrupt. - */ - -#define SPI_SLV_CMDA_INT_ENA (BIT(7)) -#define SPI_SLV_CMDA_INT_ENA_M (SPI_SLV_CMDA_INT_ENA_V << SPI_SLV_CMDA_INT_ENA_S) -#define SPI_SLV_CMDA_INT_ENA_V 0x00000001 -#define SPI_SLV_CMDA_INT_ENA_S 7 - -/* SPI_SLV_CMD9_INT_ENA : R/W; bitpos: [6]; default: 0; - * The enable bit for SPI slave CMD9 interrupt. - */ - -#define SPI_SLV_CMD9_INT_ENA (BIT(6)) -#define SPI_SLV_CMD9_INT_ENA_M (SPI_SLV_CMD9_INT_ENA_V << SPI_SLV_CMD9_INT_ENA_S) -#define SPI_SLV_CMD9_INT_ENA_V 0x00000001 -#define SPI_SLV_CMD9_INT_ENA_S 6 - -/* SPI_SLV_CMD8_INT_ENA : R/W; bitpos: [5]; default: 0; - * The enable bit for SPI slave CMD8 interrupt. - */ - -#define SPI_SLV_CMD8_INT_ENA (BIT(5)) -#define SPI_SLV_CMD8_INT_ENA_M (SPI_SLV_CMD8_INT_ENA_V << SPI_SLV_CMD8_INT_ENA_S) -#define SPI_SLV_CMD8_INT_ENA_V 0x00000001 -#define SPI_SLV_CMD8_INT_ENA_S 5 - -/* SPI_SLV_CMD7_INT_ENA : R/W; bitpos: [4]; default: 0; - * The enable bit for SPI slave CMD7 interrupt. - */ - -#define SPI_SLV_CMD7_INT_ENA (BIT(4)) -#define SPI_SLV_CMD7_INT_ENA_M (SPI_SLV_CMD7_INT_ENA_V << SPI_SLV_CMD7_INT_ENA_S) -#define SPI_SLV_CMD7_INT_ENA_V 0x00000001 -#define SPI_SLV_CMD7_INT_ENA_S 4 - -/* SPI_SLV_EN_QPI_INT_ENA : R/W; bitpos: [3]; default: 0; - * The enable bit for SPI slave En_QPI interrupt. - */ - -#define SPI_SLV_EN_QPI_INT_ENA (BIT(3)) -#define SPI_SLV_EN_QPI_INT_ENA_M (SPI_SLV_EN_QPI_INT_ENA_V << SPI_SLV_EN_QPI_INT_ENA_S) -#define SPI_SLV_EN_QPI_INT_ENA_V 0x00000001 -#define SPI_SLV_EN_QPI_INT_ENA_S 3 - -/* SPI_SLV_EX_QPI_INT_ENA : R/W; bitpos: [2]; default: 0; - * The enable bit for SPI slave Ex_QPI interrupt. - */ - -#define SPI_SLV_EX_QPI_INT_ENA (BIT(2)) -#define SPI_SLV_EX_QPI_INT_ENA_M (SPI_SLV_EX_QPI_INT_ENA_V << SPI_SLV_EX_QPI_INT_ENA_S) -#define SPI_SLV_EX_QPI_INT_ENA_V 0x00000001 -#define SPI_SLV_EX_QPI_INT_ENA_S 2 - -/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W; bitpos: [1]; default: 0; - * The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. - */ - -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA (BIT(1)) -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S) -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V 0x00000001 -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S 1 - -/* SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0; - * The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. - */ - -#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA (BIT(0)) -#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M (SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V << SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S) -#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V 0x00000001 -#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S 0 - -/* SPI_DMA_INT_CLR_REG register - * SPI DMA interrupt clear register - */ - -#define SPI_DMA_INT_CLR_REG (DR_REG_SPI2_BASE + 0x38) - -/* SPI_APP1_INT_CLR : WT; bitpos: [20]; default: 0; - * The clear bit for SPI_APP1_INT interrupt. - */ - -#define SPI_APP1_INT_CLR (BIT(20)) -#define SPI_APP1_INT_CLR_M (SPI_APP1_INT_CLR_V << SPI_APP1_INT_CLR_S) -#define SPI_APP1_INT_CLR_V 0x00000001 -#define SPI_APP1_INT_CLR_S 20 - -/* SPI_APP2_INT_CLR : WT; bitpos: [19]; default: 0; - * The clear bit for SPI_APP2_INT interrupt. - */ - -#define SPI_APP2_INT_CLR (BIT(19)) -#define SPI_APP2_INT_CLR_M (SPI_APP2_INT_CLR_V << SPI_APP2_INT_CLR_S) -#define SPI_APP2_INT_CLR_V 0x00000001 -#define SPI_APP2_INT_CLR_S 19 - -/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR : WT; bitpos: [18]; default: 0; - * The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - */ - -#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR (BIT(18)) -#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S) -#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_V 0x00000001 -#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_CLR_S 18 - -/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WT; bitpos: [17]; default: 0; - * The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - */ - -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR (BIT(17)) -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S) -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V 0x00000001 -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S 17 - -/* SPI_SLV_CMD_ERR_INT_CLR : WT; bitpos: [16]; default: 0; - * The clear bit for SPI_SLV_CMD_ERR_INT interrupt. - */ - -#define SPI_SLV_CMD_ERR_INT_CLR (BIT(16)) -#define SPI_SLV_CMD_ERR_INT_CLR_M (SPI_SLV_CMD_ERR_INT_CLR_V << SPI_SLV_CMD_ERR_INT_CLR_S) -#define SPI_SLV_CMD_ERR_INT_CLR_V 0x00000001 -#define SPI_SLV_CMD_ERR_INT_CLR_S 16 - -/* SPI_SLV_BUF_ADDR_ERR_INT_CLR : WT; bitpos: [15]; default: 0; - * The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. - */ - -#define SPI_SLV_BUF_ADDR_ERR_INT_CLR (BIT(15)) -#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M (SPI_SLV_BUF_ADDR_ERR_INT_CLR_V << SPI_SLV_BUF_ADDR_ERR_INT_CLR_S) -#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V 0x00000001 -#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S 15 - -/* SPI_SEG_MAGIC_ERR_INT_CLR : WT; bitpos: [14]; default: 0; - * The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt. - */ - -#define SPI_SEG_MAGIC_ERR_INT_CLR (BIT(14)) -#define SPI_SEG_MAGIC_ERR_INT_CLR_M (SPI_SEG_MAGIC_ERR_INT_CLR_V << SPI_SEG_MAGIC_ERR_INT_CLR_S) -#define SPI_SEG_MAGIC_ERR_INT_CLR_V 0x00000001 -#define SPI_SEG_MAGIC_ERR_INT_CLR_S 14 - -/* SPI_DMA_SEG_TRANS_DONE_INT_CLR : WT; bitpos: [13]; default: 0; - * The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. - */ - -#define SPI_DMA_SEG_TRANS_DONE_INT_CLR (BIT(13)) -#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M (SPI_DMA_SEG_TRANS_DONE_INT_CLR_V << SPI_DMA_SEG_TRANS_DONE_INT_CLR_S) -#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V 0x00000001 -#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S 13 - -/* SPI_TRANS_DONE_INT_CLR : WT; bitpos: [12]; default: 0; - * The clear bit for SPI_TRANS_DONE_INT interrupt. - */ - -#define SPI_TRANS_DONE_INT_CLR (BIT(12)) -#define SPI_TRANS_DONE_INT_CLR_M (SPI_TRANS_DONE_INT_CLR_V << SPI_TRANS_DONE_INT_CLR_S) -#define SPI_TRANS_DONE_INT_CLR_V 0x00000001 -#define SPI_TRANS_DONE_INT_CLR_S 12 - -/* SPI_SLV_WR_BUF_DONE_INT_CLR : WT; bitpos: [11]; default: 0; - * The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt. - */ - -#define SPI_SLV_WR_BUF_DONE_INT_CLR (BIT(11)) -#define SPI_SLV_WR_BUF_DONE_INT_CLR_M (SPI_SLV_WR_BUF_DONE_INT_CLR_V << SPI_SLV_WR_BUF_DONE_INT_CLR_S) -#define SPI_SLV_WR_BUF_DONE_INT_CLR_V 0x00000001 -#define SPI_SLV_WR_BUF_DONE_INT_CLR_S 11 - -/* SPI_SLV_RD_BUF_DONE_INT_CLR : WT; bitpos: [10]; default: 0; - * The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt. - */ - -#define SPI_SLV_RD_BUF_DONE_INT_CLR (BIT(10)) -#define SPI_SLV_RD_BUF_DONE_INT_CLR_M (SPI_SLV_RD_BUF_DONE_INT_CLR_V << SPI_SLV_RD_BUF_DONE_INT_CLR_S) -#define SPI_SLV_RD_BUF_DONE_INT_CLR_V 0x00000001 -#define SPI_SLV_RD_BUF_DONE_INT_CLR_S 10 - -/* SPI_SLV_WR_DMA_DONE_INT_CLR : WT; bitpos: [9]; default: 0; - * The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt. - */ - -#define SPI_SLV_WR_DMA_DONE_INT_CLR (BIT(9)) -#define SPI_SLV_WR_DMA_DONE_INT_CLR_M (SPI_SLV_WR_DMA_DONE_INT_CLR_V << SPI_SLV_WR_DMA_DONE_INT_CLR_S) -#define SPI_SLV_WR_DMA_DONE_INT_CLR_V 0x00000001 -#define SPI_SLV_WR_DMA_DONE_INT_CLR_S 9 - -/* SPI_SLV_RD_DMA_DONE_INT_CLR : WT; bitpos: [8]; default: 0; - * The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt. - */ - -#define SPI_SLV_RD_DMA_DONE_INT_CLR (BIT(8)) -#define SPI_SLV_RD_DMA_DONE_INT_CLR_M (SPI_SLV_RD_DMA_DONE_INT_CLR_V << SPI_SLV_RD_DMA_DONE_INT_CLR_S) -#define SPI_SLV_RD_DMA_DONE_INT_CLR_V 0x00000001 -#define SPI_SLV_RD_DMA_DONE_INT_CLR_S 8 - -/* SPI_SLV_CMDA_INT_CLR : WT; bitpos: [7]; default: 0; - * The clear bit for SPI slave CMDA interrupt. - */ - -#define SPI_SLV_CMDA_INT_CLR (BIT(7)) -#define SPI_SLV_CMDA_INT_CLR_M (SPI_SLV_CMDA_INT_CLR_V << SPI_SLV_CMDA_INT_CLR_S) -#define SPI_SLV_CMDA_INT_CLR_V 0x00000001 -#define SPI_SLV_CMDA_INT_CLR_S 7 - -/* SPI_SLV_CMD9_INT_CLR : WT; bitpos: [6]; default: 0; - * The clear bit for SPI slave CMD9 interrupt. - */ - -#define SPI_SLV_CMD9_INT_CLR (BIT(6)) -#define SPI_SLV_CMD9_INT_CLR_M (SPI_SLV_CMD9_INT_CLR_V << SPI_SLV_CMD9_INT_CLR_S) -#define SPI_SLV_CMD9_INT_CLR_V 0x00000001 -#define SPI_SLV_CMD9_INT_CLR_S 6 - -/* SPI_SLV_CMD8_INT_CLR : WT; bitpos: [5]; default: 0; - * The clear bit for SPI slave CMD8 interrupt. - */ - -#define SPI_SLV_CMD8_INT_CLR (BIT(5)) -#define SPI_SLV_CMD8_INT_CLR_M (SPI_SLV_CMD8_INT_CLR_V << SPI_SLV_CMD8_INT_CLR_S) -#define SPI_SLV_CMD8_INT_CLR_V 0x00000001 -#define SPI_SLV_CMD8_INT_CLR_S 5 - -/* SPI_SLV_CMD7_INT_CLR : WT; bitpos: [4]; default: 0; - * The clear bit for SPI slave CMD7 interrupt. - */ - -#define SPI_SLV_CMD7_INT_CLR (BIT(4)) -#define SPI_SLV_CMD7_INT_CLR_M (SPI_SLV_CMD7_INT_CLR_V << SPI_SLV_CMD7_INT_CLR_S) -#define SPI_SLV_CMD7_INT_CLR_V 0x00000001 -#define SPI_SLV_CMD7_INT_CLR_S 4 - -/* SPI_SLV_EN_QPI_INT_CLR : WT; bitpos: [3]; default: 0; - * The clear bit for SPI slave En_QPI interrupt. - */ - -#define SPI_SLV_EN_QPI_INT_CLR (BIT(3)) -#define SPI_SLV_EN_QPI_INT_CLR_M (SPI_SLV_EN_QPI_INT_CLR_V << SPI_SLV_EN_QPI_INT_CLR_S) -#define SPI_SLV_EN_QPI_INT_CLR_V 0x00000001 -#define SPI_SLV_EN_QPI_INT_CLR_S 3 - -/* SPI_SLV_EX_QPI_INT_CLR : WT; bitpos: [2]; default: 0; - * The clear bit for SPI slave Ex_QPI interrupt. - */ - -#define SPI_SLV_EX_QPI_INT_CLR (BIT(2)) -#define SPI_SLV_EX_QPI_INT_CLR_M (SPI_SLV_EX_QPI_INT_CLR_V << SPI_SLV_EX_QPI_INT_CLR_S) -#define SPI_SLV_EX_QPI_INT_CLR_V 0x00000001 -#define SPI_SLV_EX_QPI_INT_CLR_S 2 - -/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WT; bitpos: [1]; default: 0; - * The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. - */ - -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR (BIT(1)) -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S) -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V 0x00000001 -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S 1 - -/* SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0; - * The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. - */ - -#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR (BIT(0)) -#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M (SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V << SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S) -#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V 0x00000001 -#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S 0 - -/* SPI_DMA_INT_RAW_REG register - * SPI DMA interrupt raw register - */ - -#define SPI_DMA_INT_RAW_REG (DR_REG_SPI2_BASE + 0x3c) - -/* SPI_APP1_INT_RAW : R/W/WTC; bitpos: [20]; default: 0; - * The raw bit for SPI_APP1_INT interrupt. The value is only controlled by - * application. - */ - -#define SPI_APP1_INT_RAW (BIT(20)) -#define SPI_APP1_INT_RAW_M (SPI_APP1_INT_RAW_V << SPI_APP1_INT_RAW_S) -#define SPI_APP1_INT_RAW_V 0x00000001 -#define SPI_APP1_INT_RAW_S 20 - -/* SPI_APP2_INT_RAW : R/W/WTC; bitpos: [19]; default: 0; - * The raw bit for SPI_APP2_INT interrupt. The value is only controlled by - * application. - */ - -#define SPI_APP2_INT_RAW (BIT(19)) -#define SPI_APP2_INT_RAW_M (SPI_APP2_INT_RAW_V << SPI_APP2_INT_RAW_S) -#define SPI_APP2_INT_RAW_V 0x00000001 -#define SPI_APP2_INT_RAW_S 19 - -/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW : R/W/WTC/SS; bitpos: [18]; default: - * 0; - * The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a - * TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: - * Others. - */ - -#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW (BIT(18)) -#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S) -#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_V 0x00000001 -#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_RAW_S 18 - -/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/W/WTC/SS; bitpos: [17]; default: 0; - * The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a - * RX AFIFO write-full error when SPI inputs data in master mode. 0: Others. - */ - -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW (BIT(17)) -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S) -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V 0x00000001 -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S 17 - -/* SPI_SLV_CMD_ERR_INT_RAW : R/W/WTC/SS; bitpos: [16]; default: 0; - * The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value - * in the current SPI slave HD mode transmission is not supported. 0: Others. - */ - -#define SPI_SLV_CMD_ERR_INT_RAW (BIT(16)) -#define SPI_SLV_CMD_ERR_INT_RAW_M (SPI_SLV_CMD_ERR_INT_RAW_V << SPI_SLV_CMD_ERR_INT_RAW_S) -#define SPI_SLV_CMD_ERR_INT_RAW_V 0x00000001 -#define SPI_SLV_CMD_ERR_INT_RAW_S 16 - -/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/W/WTC/SS; bitpos: [15]; default: 0; - * The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data - * address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF - * transmission is bigger than 63. 0: Others. - */ - -#define SPI_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15)) -#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M (SPI_SLV_BUF_ADDR_ERR_INT_RAW_V << SPI_SLV_BUF_ADDR_ERR_INT_RAW_S) -#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V 0x00000001 -#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S 15 - -/* SPI_SEG_MAGIC_ERR_INT_RAW : R/W/WTC/SS; bitpos: [14]; default: 0; - * The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in - * CONF buffer is error in the DMA seg-conf-trans. 0: others. - */ - -#define SPI_SEG_MAGIC_ERR_INT_RAW (BIT(14)) -#define SPI_SEG_MAGIC_ERR_INT_RAW_M (SPI_SEG_MAGIC_ERR_INT_RAW_V << SPI_SEG_MAGIC_ERR_INT_RAW_S) -#define SPI_SEG_MAGIC_ERR_INT_RAW_V 0x00000001 -#define SPI_SEG_MAGIC_ERR_INT_RAW_S 14 - -/* SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/W/WTC/SS; bitpos: [13]; default: 0; - * The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA - * full-duplex/half-duplex seg-conf-trans ends or slave half-duplex - * seg-trans ends. And data has been pushed to corresponding memory. 0: - * seg-conf-trans or seg-trans is not ended or not occurred. - */ - -#define SPI_DMA_SEG_TRANS_DONE_INT_RAW (BIT(13)) -#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M (SPI_DMA_SEG_TRANS_DONE_INT_RAW_V << SPI_DMA_SEG_TRANS_DONE_INT_RAW_S) -#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V 0x00000001 -#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S 13 - -/* SPI_TRANS_DONE_INT_RAW : R/W/WTC/SS; bitpos: [12]; default: 0; - * The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode - * transmission is ended. 0: others. - */ - -#define SPI_TRANS_DONE_INT_RAW (BIT(12)) -#define SPI_TRANS_DONE_INT_RAW_M (SPI_TRANS_DONE_INT_RAW_V << SPI_TRANS_DONE_INT_RAW_S) -#define SPI_TRANS_DONE_INT_RAW_V 0x00000001 -#define SPI_TRANS_DONE_INT_RAW_S 12 - -/* SPI_SLV_WR_BUF_DONE_INT_RAW : R/W/WTC/SS; bitpos: [11]; default: 0; - * The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode - * Wr_BUF transmission is ended. 0: Others. - */ - -#define SPI_SLV_WR_BUF_DONE_INT_RAW (BIT(11)) -#define SPI_SLV_WR_BUF_DONE_INT_RAW_M (SPI_SLV_WR_BUF_DONE_INT_RAW_V << SPI_SLV_WR_BUF_DONE_INT_RAW_S) -#define SPI_SLV_WR_BUF_DONE_INT_RAW_V 0x00000001 -#define SPI_SLV_WR_BUF_DONE_INT_RAW_S 11 - -/* SPI_SLV_RD_BUF_DONE_INT_RAW : R/W/WTC/SS; bitpos: [10]; default: 0; - * The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode - * Rd_BUF transmission is ended. 0: Others. - */ - -#define SPI_SLV_RD_BUF_DONE_INT_RAW (BIT(10)) -#define SPI_SLV_RD_BUF_DONE_INT_RAW_M (SPI_SLV_RD_BUF_DONE_INT_RAW_V << SPI_SLV_RD_BUF_DONE_INT_RAW_S) -#define SPI_SLV_RD_BUF_DONE_INT_RAW_V 0x00000001 -#define SPI_SLV_RD_BUF_DONE_INT_RAW_S 10 - -/* SPI_SLV_WR_DMA_DONE_INT_RAW : R/W/WTC/SS; bitpos: [9]; default: 0; - * The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode - * Wr_DMA transmission is ended. 0: Others. - */ - -#define SPI_SLV_WR_DMA_DONE_INT_RAW (BIT(9)) -#define SPI_SLV_WR_DMA_DONE_INT_RAW_M (SPI_SLV_WR_DMA_DONE_INT_RAW_V << SPI_SLV_WR_DMA_DONE_INT_RAW_S) -#define SPI_SLV_WR_DMA_DONE_INT_RAW_V 0x00000001 -#define SPI_SLV_WR_DMA_DONE_INT_RAW_S 9 - -/* SPI_SLV_RD_DMA_DONE_INT_RAW : R/W/WTC/SS; bitpos: [8]; default: 0; - * The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode - * Rd_DMA transmission is ended. 0: Others. - */ - -#define SPI_SLV_RD_DMA_DONE_INT_RAW (BIT(8)) -#define SPI_SLV_RD_DMA_DONE_INT_RAW_M (SPI_SLV_RD_DMA_DONE_INT_RAW_V << SPI_SLV_RD_DMA_DONE_INT_RAW_S) -#define SPI_SLV_RD_DMA_DONE_INT_RAW_V 0x00000001 -#define SPI_SLV_RD_DMA_DONE_INT_RAW_S 8 - -/* SPI_SLV_CMDA_INT_RAW : R/W/WTC/SS; bitpos: [7]; default: 0; - * The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA - * transmission is ended. 0: Others. - */ - -#define SPI_SLV_CMDA_INT_RAW (BIT(7)) -#define SPI_SLV_CMDA_INT_RAW_M (SPI_SLV_CMDA_INT_RAW_V << SPI_SLV_CMDA_INT_RAW_S) -#define SPI_SLV_CMDA_INT_RAW_V 0x00000001 -#define SPI_SLV_CMDA_INT_RAW_S 7 - -/* SPI_SLV_CMD9_INT_RAW : R/W/WTC/SS; bitpos: [6]; default: 0; - * The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 - * transmission is ended. 0: Others. - */ - -#define SPI_SLV_CMD9_INT_RAW (BIT(6)) -#define SPI_SLV_CMD9_INT_RAW_M (SPI_SLV_CMD9_INT_RAW_V << SPI_SLV_CMD9_INT_RAW_S) -#define SPI_SLV_CMD9_INT_RAW_V 0x00000001 -#define SPI_SLV_CMD9_INT_RAW_S 6 - -/* SPI_SLV_CMD8_INT_RAW : R/W/WTC/SS; bitpos: [5]; default: 0; - * The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 - * transmission is ended. 0: Others. - */ - -#define SPI_SLV_CMD8_INT_RAW (BIT(5)) -#define SPI_SLV_CMD8_INT_RAW_M (SPI_SLV_CMD8_INT_RAW_V << SPI_SLV_CMD8_INT_RAW_S) -#define SPI_SLV_CMD8_INT_RAW_V 0x00000001 -#define SPI_SLV_CMD8_INT_RAW_S 5 - -/* SPI_SLV_CMD7_INT_RAW : R/W/WTC/SS; bitpos: [4]; default: 0; - * The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 - * transmission is ended. 0: Others. - */ - -#define SPI_SLV_CMD7_INT_RAW (BIT(4)) -#define SPI_SLV_CMD7_INT_RAW_M (SPI_SLV_CMD7_INT_RAW_V << SPI_SLV_CMD7_INT_RAW_S) -#define SPI_SLV_CMD7_INT_RAW_V 0x00000001 -#define SPI_SLV_CMD7_INT_RAW_S 4 - -/* SPI_SLV_EN_QPI_INT_RAW : R/W/WTC/SS; bitpos: [3]; default: 0; - * The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI - * transmission is ended. 0: Others. - */ - -#define SPI_SLV_EN_QPI_INT_RAW (BIT(3)) -#define SPI_SLV_EN_QPI_INT_RAW_M (SPI_SLV_EN_QPI_INT_RAW_V << SPI_SLV_EN_QPI_INT_RAW_S) -#define SPI_SLV_EN_QPI_INT_RAW_V 0x00000001 -#define SPI_SLV_EN_QPI_INT_RAW_S 3 - -/* SPI_SLV_EX_QPI_INT_RAW : R/W/WTC/SS; bitpos: [2]; default: 0; - * The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI - * transmission is ended. 0: Others. - */ - -#define SPI_SLV_EX_QPI_INT_RAW (BIT(2)) -#define SPI_SLV_EX_QPI_INT_RAW_M (SPI_SLV_EX_QPI_INT_RAW_V << SPI_SLV_EX_QPI_INT_RAW_S) -#define SPI_SLV_EX_QPI_INT_RAW_V 0x00000001 -#define SPI_SLV_EX_QPI_INT_RAW_S 2 - -/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/W/WTC/SS; bitpos: [1]; default: 0; - * 1: The current data rate of DMA TX is smaller than that of SPI. SPI will - * stop in master mode and send out all 0 in slave mode. 0: Others. - */ - -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW (BIT(1)) -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S) -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V 0x00000001 -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S 1 - -/* SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/W/WTC/SS; bitpos: [0]; default: 0; - * 1: The current data rate of DMA Rx is smaller than that of SPI, which - * will lose the receive data. 0: Others. - */ - -#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW (BIT(0)) -#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M (SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V << SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S) -#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V 0x00000001 -#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S 0 - -/* SPI_DMA_INT_ST_REG register - * SPI DMA interrupt status register - */ - -#define SPI_DMA_INT_ST_REG (DR_REG_SPI2_BASE + 0x40) - -/* SPI_APP1_INT_ST : RO; bitpos: [20]; default: 0; - * The status bit for SPI_APP1_INT interrupt. - */ - -#define SPI_APP1_INT_ST (BIT(20)) -#define SPI_APP1_INT_ST_M (SPI_APP1_INT_ST_V << SPI_APP1_INT_ST_S) -#define SPI_APP1_INT_ST_V 0x00000001 -#define SPI_APP1_INT_ST_S 20 - -/* SPI_APP2_INT_ST : RO; bitpos: [19]; default: 0; - * The status bit for SPI_APP2_INT interrupt. - */ - -#define SPI_APP2_INT_ST (BIT(19)) -#define SPI_APP2_INT_ST_M (SPI_APP2_INT_ST_V << SPI_APP2_INT_ST_S) -#define SPI_APP2_INT_ST_V 0x00000001 -#define SPI_APP2_INT_ST_S 19 - -/* SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST : RO; bitpos: [18]; default: 0; - * The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. - */ - -#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST (BIT(18)) -#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_M (SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V << SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S) -#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_V 0x00000001 -#define SPI_MST_TX_AFIFO_REMPTY_ERR_INT_ST_S 18 - -/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO; bitpos: [17]; default: 0; - * The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. - */ - -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST (BIT(17)) -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M (SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V << SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S) -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V 0x00000001 -#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S 17 - -/* SPI_SLV_CMD_ERR_INT_ST : RO; bitpos: [16]; default: 0; - * The status bit for SPI_SLV_CMD_ERR_INT interrupt. - */ - -#define SPI_SLV_CMD_ERR_INT_ST (BIT(16)) -#define SPI_SLV_CMD_ERR_INT_ST_M (SPI_SLV_CMD_ERR_INT_ST_V << SPI_SLV_CMD_ERR_INT_ST_S) -#define SPI_SLV_CMD_ERR_INT_ST_V 0x00000001 -#define SPI_SLV_CMD_ERR_INT_ST_S 16 - -/* SPI_SLV_BUF_ADDR_ERR_INT_ST : RO; bitpos: [15]; default: 0; - * The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. - */ - -#define SPI_SLV_BUF_ADDR_ERR_INT_ST (BIT(15)) -#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M (SPI_SLV_BUF_ADDR_ERR_INT_ST_V << SPI_SLV_BUF_ADDR_ERR_INT_ST_S) -#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V 0x00000001 -#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S 15 - -/* SPI_SEG_MAGIC_ERR_INT_ST : RO; bitpos: [14]; default: 0; - * The status bit for SPI_SEG_MAGIC_ERR_INT interrupt. - */ - -#define SPI_SEG_MAGIC_ERR_INT_ST (BIT(14)) -#define SPI_SEG_MAGIC_ERR_INT_ST_M (SPI_SEG_MAGIC_ERR_INT_ST_V << SPI_SEG_MAGIC_ERR_INT_ST_S) -#define SPI_SEG_MAGIC_ERR_INT_ST_V 0x00000001 -#define SPI_SEG_MAGIC_ERR_INT_ST_S 14 - -/* SPI_DMA_SEG_TRANS_DONE_INT_ST : RO; bitpos: [13]; default: 0; - * The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. - */ - -#define SPI_DMA_SEG_TRANS_DONE_INT_ST (BIT(13)) -#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M (SPI_DMA_SEG_TRANS_DONE_INT_ST_V << SPI_DMA_SEG_TRANS_DONE_INT_ST_S) -#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V 0x00000001 -#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S 13 - -/* SPI_TRANS_DONE_INT_ST : RO; bitpos: [12]; default: 0; - * The status bit for SPI_TRANS_DONE_INT interrupt. - */ - -#define SPI_TRANS_DONE_INT_ST (BIT(12)) -#define SPI_TRANS_DONE_INT_ST_M (SPI_TRANS_DONE_INT_ST_V << SPI_TRANS_DONE_INT_ST_S) -#define SPI_TRANS_DONE_INT_ST_V 0x00000001 -#define SPI_TRANS_DONE_INT_ST_S 12 - -/* SPI_SLV_WR_BUF_DONE_INT_ST : RO; bitpos: [11]; default: 0; - * The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt. - */ - -#define SPI_SLV_WR_BUF_DONE_INT_ST (BIT(11)) -#define SPI_SLV_WR_BUF_DONE_INT_ST_M (SPI_SLV_WR_BUF_DONE_INT_ST_V << SPI_SLV_WR_BUF_DONE_INT_ST_S) -#define SPI_SLV_WR_BUF_DONE_INT_ST_V 0x00000001 -#define SPI_SLV_WR_BUF_DONE_INT_ST_S 11 - -/* SPI_SLV_RD_BUF_DONE_INT_ST : RO; bitpos: [10]; default: 0; - * The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt. - */ - -#define SPI_SLV_RD_BUF_DONE_INT_ST (BIT(10)) -#define SPI_SLV_RD_BUF_DONE_INT_ST_M (SPI_SLV_RD_BUF_DONE_INT_ST_V << SPI_SLV_RD_BUF_DONE_INT_ST_S) -#define SPI_SLV_RD_BUF_DONE_INT_ST_V 0x00000001 -#define SPI_SLV_RD_BUF_DONE_INT_ST_S 10 - -/* SPI_SLV_WR_DMA_DONE_INT_ST : RO; bitpos: [9]; default: 0; - * The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt. - */ - -#define SPI_SLV_WR_DMA_DONE_INT_ST (BIT(9)) -#define SPI_SLV_WR_DMA_DONE_INT_ST_M (SPI_SLV_WR_DMA_DONE_INT_ST_V << SPI_SLV_WR_DMA_DONE_INT_ST_S) -#define SPI_SLV_WR_DMA_DONE_INT_ST_V 0x00000001 -#define SPI_SLV_WR_DMA_DONE_INT_ST_S 9 - -/* SPI_SLV_RD_DMA_DONE_INT_ST : RO; bitpos: [8]; default: 0; - * The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt. - */ - -#define SPI_SLV_RD_DMA_DONE_INT_ST (BIT(8)) -#define SPI_SLV_RD_DMA_DONE_INT_ST_M (SPI_SLV_RD_DMA_DONE_INT_ST_V << SPI_SLV_RD_DMA_DONE_INT_ST_S) -#define SPI_SLV_RD_DMA_DONE_INT_ST_V 0x00000001 -#define SPI_SLV_RD_DMA_DONE_INT_ST_S 8 - -/* SPI_SLV_CMDA_INT_ST : RO; bitpos: [7]; default: 0; - * The status bit for SPI slave CMDA interrupt. - */ - -#define SPI_SLV_CMDA_INT_ST (BIT(7)) -#define SPI_SLV_CMDA_INT_ST_M (SPI_SLV_CMDA_INT_ST_V << SPI_SLV_CMDA_INT_ST_S) -#define SPI_SLV_CMDA_INT_ST_V 0x00000001 -#define SPI_SLV_CMDA_INT_ST_S 7 - -/* SPI_SLV_CMD9_INT_ST : RO; bitpos: [6]; default: 0; - * The status bit for SPI slave CMD9 interrupt. - */ - -#define SPI_SLV_CMD9_INT_ST (BIT(6)) -#define SPI_SLV_CMD9_INT_ST_M (SPI_SLV_CMD9_INT_ST_V << SPI_SLV_CMD9_INT_ST_S) -#define SPI_SLV_CMD9_INT_ST_V 0x00000001 -#define SPI_SLV_CMD9_INT_ST_S 6 - -/* SPI_SLV_CMD8_INT_ST : RO; bitpos: [5]; default: 0; - * The status bit for SPI slave CMD8 interrupt. - */ - -#define SPI_SLV_CMD8_INT_ST (BIT(5)) -#define SPI_SLV_CMD8_INT_ST_M (SPI_SLV_CMD8_INT_ST_V << SPI_SLV_CMD8_INT_ST_S) -#define SPI_SLV_CMD8_INT_ST_V 0x00000001 -#define SPI_SLV_CMD8_INT_ST_S 5 - -/* SPI_SLV_CMD7_INT_ST : RO; bitpos: [4]; default: 0; - * The status bit for SPI slave CMD7 interrupt. - */ - -#define SPI_SLV_CMD7_INT_ST (BIT(4)) -#define SPI_SLV_CMD7_INT_ST_M (SPI_SLV_CMD7_INT_ST_V << SPI_SLV_CMD7_INT_ST_S) -#define SPI_SLV_CMD7_INT_ST_V 0x00000001 -#define SPI_SLV_CMD7_INT_ST_S 4 - -/* SPI_SLV_EN_QPI_INT_ST : RO; bitpos: [3]; default: 0; - * The status bit for SPI slave En_QPI interrupt. - */ - -#define SPI_SLV_EN_QPI_INT_ST (BIT(3)) -#define SPI_SLV_EN_QPI_INT_ST_M (SPI_SLV_EN_QPI_INT_ST_V << SPI_SLV_EN_QPI_INT_ST_S) -#define SPI_SLV_EN_QPI_INT_ST_V 0x00000001 -#define SPI_SLV_EN_QPI_INT_ST_S 3 - -/* SPI_SLV_EX_QPI_INT_ST : RO; bitpos: [2]; default: 0; - * The status bit for SPI slave Ex_QPI interrupt. - */ - -#define SPI_SLV_EX_QPI_INT_ST (BIT(2)) -#define SPI_SLV_EX_QPI_INT_ST_M (SPI_SLV_EX_QPI_INT_ST_V << SPI_SLV_EX_QPI_INT_ST_S) -#define SPI_SLV_EX_QPI_INT_ST_V 0x00000001 -#define SPI_SLV_EX_QPI_INT_ST_S 2 - -/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO; bitpos: [1]; default: 0; - * The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt. - */ - -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST (BIT(1)) -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M (SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V << SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S) -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V 0x00000001 -#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S 1 - -/* SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0; - * The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt. - */ - -#define SPI_DMA_INFIFO_FULL_ERR_INT_ST (BIT(0)) -#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M (SPI_DMA_INFIFO_FULL_ERR_INT_ST_V << SPI_DMA_INFIFO_FULL_ERR_INT_ST_S) -#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V 0x00000001 -#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S 0 - -/* SPI_W0_REG register - * SPI CPU-controlled buffer0 - */ - -#define SPI_W0_REG (DR_REG_SPI2_BASE + 0x98) - -/* SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - -#define SPI_BUF0 0xFFFFFFFF -#define SPI_BUF0_M (SPI_BUF0_V << SPI_BUF0_S) -#define SPI_BUF0_V 0xFFFFFFFF -#define SPI_BUF0_S 0 - -/* SPI_W1_REG register - * SPI CPU-controlled buffer1 - */ - -#define SPI_W1_REG (DR_REG_SPI2_BASE + 0x9c) - -/* SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - -#define SPI_BUF1 0xFFFFFFFF -#define SPI_BUF1_M (SPI_BUF1_V << SPI_BUF1_S) -#define SPI_BUF1_V 0xFFFFFFFF -#define SPI_BUF1_S 0 - -/* SPI_W2_REG register - * SPI CPU-controlled buffer2 - */ - -#define SPI_W2_REG (DR_REG_SPI2_BASE + 0xa0) - -/* SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - -#define SPI_BUF2 0xFFFFFFFF -#define SPI_BUF2_M (SPI_BUF2_V << SPI_BUF2_S) -#define SPI_BUF2_V 0xFFFFFFFF -#define SPI_BUF2_S 0 - -/* SPI_W3_REG register - * SPI CPU-controlled buffer3 - */ - -#define SPI_W3_REG (DR_REG_SPI2_BASE + 0xa4) - -/* SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - -#define SPI_BUF3 0xFFFFFFFF -#define SPI_BUF3_M (SPI_BUF3_V << SPI_BUF3_S) -#define SPI_BUF3_V 0xFFFFFFFF -#define SPI_BUF3_S 0 - -/* SPI_W4_REG register - * SPI CPU-controlled buffer4 - */ - -#define SPI_W4_REG (DR_REG_SPI2_BASE + 0xa8) - -/* SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - -#define SPI_BUF4 0xFFFFFFFF -#define SPI_BUF4_M (SPI_BUF4_V << SPI_BUF4_S) -#define SPI_BUF4_V 0xFFFFFFFF -#define SPI_BUF4_S 0 - -/* SPI_W5_REG register - * SPI CPU-controlled buffer5 - */ - -#define SPI_W5_REG (DR_REG_SPI2_BASE + 0xac) - -/* SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - -#define SPI_BUF5 0xFFFFFFFF -#define SPI_BUF5_M (SPI_BUF5_V << SPI_BUF5_S) -#define SPI_BUF5_V 0xFFFFFFFF -#define SPI_BUF5_S 0 - -/* SPI_W6_REG register - * SPI CPU-controlled buffer6 - */ - -#define SPI_W6_REG (DR_REG_SPI2_BASE + 0xb0) - -/* SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - -#define SPI_BUF6 0xFFFFFFFF -#define SPI_BUF6_M (SPI_BUF6_V << SPI_BUF6_S) -#define SPI_BUF6_V 0xFFFFFFFF -#define SPI_BUF6_S 0 - -/* SPI_W7_REG register - * SPI CPU-controlled buffer7 - */ - -#define SPI_W7_REG (DR_REG_SPI2_BASE + 0xb4) - -/* SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - -#define SPI_BUF7 0xFFFFFFFF -#define SPI_BUF7_M (SPI_BUF7_V << SPI_BUF7_S) -#define SPI_BUF7_V 0xFFFFFFFF -#define SPI_BUF7_S 0 - -/* SPI_W8_REG register - * SPI CPU-controlled buffer8 - */ - -#define SPI_W8_REG (DR_REG_SPI2_BASE + 0xb8) - -/* SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - -#define SPI_BUF8 0xFFFFFFFF -#define SPI_BUF8_M (SPI_BUF8_V << SPI_BUF8_S) -#define SPI_BUF8_V 0xFFFFFFFF -#define SPI_BUF8_S 0 - -/* SPI_W9_REG register - * SPI CPU-controlled buffer9 - */ - -#define SPI_W9_REG (DR_REG_SPI2_BASE + 0xbc) - -/* SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - -#define SPI_BUF9 0xFFFFFFFF -#define SPI_BUF9_M (SPI_BUF9_V << SPI_BUF9_S) -#define SPI_BUF9_V 0xFFFFFFFF -#define SPI_BUF9_S 0 - -/* SPI_W10_REG register - * SPI CPU-controlled buffer10 - */ - -#define SPI_W10_REG (DR_REG_SPI2_BASE + 0xc0) - -/* SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - -#define SPI_BUF10 0xFFFFFFFF -#define SPI_BUF10_M (SPI_BUF10_V << SPI_BUF10_S) -#define SPI_BUF10_V 0xFFFFFFFF -#define SPI_BUF10_S 0 - -/* SPI_W11_REG register - * SPI CPU-controlled buffer11 - */ - -#define SPI_W11_REG (DR_REG_SPI2_BASE + 0xc4) - -/* SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - -#define SPI_BUF11 0xFFFFFFFF -#define SPI_BUF11_M (SPI_BUF11_V << SPI_BUF11_S) -#define SPI_BUF11_V 0xFFFFFFFF -#define SPI_BUF11_S 0 - -/* SPI_W12_REG register - * SPI CPU-controlled buffer12 - */ - -#define SPI_W12_REG (DR_REG_SPI2_BASE + 0xc8) - -/* SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - -#define SPI_BUF12 0xFFFFFFFF -#define SPI_BUF12_M (SPI_BUF12_V << SPI_BUF12_S) -#define SPI_BUF12_V 0xFFFFFFFF -#define SPI_BUF12_S 0 - -/* SPI_W13_REG register - * SPI CPU-controlled buffer13 - */ - -#define SPI_W13_REG (DR_REG_SPI2_BASE + 0xcc) - -/* SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - -#define SPI_BUF13 0xFFFFFFFF -#define SPI_BUF13_M (SPI_BUF13_V << SPI_BUF13_S) -#define SPI_BUF13_V 0xFFFFFFFF -#define SPI_BUF13_S 0 - -/* SPI_W14_REG register - * SPI CPU-controlled buffer14 - */ - -#define SPI_W14_REG (DR_REG_SPI2_BASE + 0xd0) - -/* SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - -#define SPI_BUF14 0xFFFFFFFF -#define SPI_BUF14_M (SPI_BUF14_V << SPI_BUF14_S) -#define SPI_BUF14_V 0xFFFFFFFF -#define SPI_BUF14_S 0 - -/* SPI_W15_REG register - * SPI CPU-controlled buffer15 - */ - -#define SPI_W15_REG (DR_REG_SPI2_BASE + 0xd4) - -/* SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0; - * data buffer - */ - -#define SPI_BUF15 0xFFFFFFFF -#define SPI_BUF15_M (SPI_BUF15_V << SPI_BUF15_S) -#define SPI_BUF15_V 0xFFFFFFFF -#define SPI_BUF15_S 0 - -/* SPI_SLAVE_REG register - * SPI slave control register - */ - -#define SPI_SLAVE_REG (DR_REG_SPI2_BASE + 0xe0) - -/* SPI_USR_CONF : R/W; bitpos: [28]; default: 0; - * 1: Enable the DMA CONF phase of current seg-trans operation, which means - * seg-trans will start. 0: This is not seg-trans mode. - */ - -#define SPI_USR_CONF (BIT(28)) -#define SPI_USR_CONF_M (SPI_USR_CONF_V << SPI_USR_CONF_S) -#define SPI_USR_CONF_V 0x00000001 -#define SPI_USR_CONF_S 28 - -/* SPI_SOFT_RESET : WT; bitpos: [27]; default: 0; - * Software reset enable, reset the spi clock line cs line and data lines. - * Can be configured in CONF state. - */ - -#define SPI_SOFT_RESET (BIT(27)) -#define SPI_SOFT_RESET_M (SPI_SOFT_RESET_V << SPI_SOFT_RESET_S) -#define SPI_SOFT_RESET_V 0x00000001 -#define SPI_SOFT_RESET_S 27 - -/* SPI_SLAVE_MODE : R/W; bitpos: [26]; default: 0; - * Set SPI work mode. 1: slave mode 0: master mode. - */ - -#define SPI_SLAVE_MODE (BIT(26)) -#define SPI_SLAVE_MODE_M (SPI_SLAVE_MODE_V << SPI_SLAVE_MODE_S) -#define SPI_SLAVE_MODE_V 0x00000001 -#define SPI_SLAVE_MODE_S 26 - -/* SPI_DMA_SEG_MAGIC_VALUE : R/W; bitpos: [25:22]; default: 10; - * The magic value of BM table in master DMA seg-trans. - */ - -#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000F -#define SPI_DMA_SEG_MAGIC_VALUE_M (SPI_DMA_SEG_MAGIC_VALUE_V << SPI_DMA_SEG_MAGIC_VALUE_S) -#define SPI_DMA_SEG_MAGIC_VALUE_V 0x0000000F -#define SPI_DMA_SEG_MAGIC_VALUE_S 22 - -/* SPI_SLV_WRBUF_BITLEN_EN : R/W; bitpos: [11]; default: 0; - * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave - * data length in CPU controlled mode(Wr_BUF). 0: others - */ - -#define SPI_SLV_WRBUF_BITLEN_EN (BIT(11)) -#define SPI_SLV_WRBUF_BITLEN_EN_M (SPI_SLV_WRBUF_BITLEN_EN_V << SPI_SLV_WRBUF_BITLEN_EN_S) -#define SPI_SLV_WRBUF_BITLEN_EN_V 0x00000001 -#define SPI_SLV_WRBUF_BITLEN_EN_S 11 - -/* SPI_SLV_RDBUF_BITLEN_EN : R/W; bitpos: [10]; default: 0; - * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data - * length in CPU controlled mode(Rd_BUF). 0: others - */ - -#define SPI_SLV_RDBUF_BITLEN_EN (BIT(10)) -#define SPI_SLV_RDBUF_BITLEN_EN_M (SPI_SLV_RDBUF_BITLEN_EN_V << SPI_SLV_RDBUF_BITLEN_EN_S) -#define SPI_SLV_RDBUF_BITLEN_EN_V 0x00000001 -#define SPI_SLV_RDBUF_BITLEN_EN_S 10 - -/* SPI_SLV_WRDMA_BITLEN_EN : R/W; bitpos: [9]; default: 0; - * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave - * data length in DMA controlled mode(Wr_DMA). 0: others - */ - -#define SPI_SLV_WRDMA_BITLEN_EN (BIT(9)) -#define SPI_SLV_WRDMA_BITLEN_EN_M (SPI_SLV_WRDMA_BITLEN_EN_V << SPI_SLV_WRDMA_BITLEN_EN_S) -#define SPI_SLV_WRDMA_BITLEN_EN_V 0x00000001 -#define SPI_SLV_WRDMA_BITLEN_EN_S 9 - -/* SPI_SLV_RDDMA_BITLEN_EN : R/W; bitpos: [8]; default: 0; - * 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data - * length in DMA controlled mode(Rd_DMA). 0: others - */ - -#define SPI_SLV_RDDMA_BITLEN_EN (BIT(8)) -#define SPI_SLV_RDDMA_BITLEN_EN_M (SPI_SLV_RDDMA_BITLEN_EN_V << SPI_SLV_RDDMA_BITLEN_EN_S) -#define SPI_SLV_RDDMA_BITLEN_EN_V 0x00000001 -#define SPI_SLV_RDDMA_BITLEN_EN_S 8 - -/* SPI_RSCK_DATA_OUT : R/W; bitpos: [3]; default: 0; - * It saves half a cycle when tsck is the same as rsck. 1: output data at - * rsck posedge 0: output data at tsck posedge - */ - -#define SPI_RSCK_DATA_OUT (BIT(3)) -#define SPI_RSCK_DATA_OUT_M (SPI_RSCK_DATA_OUT_V << SPI_RSCK_DATA_OUT_S) -#define SPI_RSCK_DATA_OUT_V 0x00000001 -#define SPI_RSCK_DATA_OUT_S 3 - -/* SPI_CLK_MODE_13 : R/W; bitpos: [2]; default: 0; - * {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data - * B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data - * B[1]/B[6]. - */ - -#define SPI_CLK_MODE_13 (BIT(2)) -#define SPI_CLK_MODE_13_M (SPI_CLK_MODE_13_V << SPI_CLK_MODE_13_S) -#define SPI_CLK_MODE_13_V 0x00000001 -#define SPI_CLK_MODE_13_S 2 - -/* SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0; - * SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is - * delayed one cycle after CS inactive 2: SPI clock is delayed two cycles - * after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF - * state. - */ - -#define SPI_CLK_MODE 0x00000003 -#define SPI_CLK_MODE_M (SPI_CLK_MODE_V << SPI_CLK_MODE_S) -#define SPI_CLK_MODE_V 0x00000003 -#define SPI_CLK_MODE_S 0 - -/* SPI_SLAVE1_REG register - * SPI slave control register 1 - */ - -#define SPI_SLAVE1_REG (DR_REG_SPI2_BASE + 0xe4) - -/* SPI_SLV_LAST_ADDR : R/W/SS; bitpos: [31:26]; default: 0; - * In the slave mode it is the value of address. - */ - -#define SPI_SLV_LAST_ADDR 0x0000003F -#define SPI_SLV_LAST_ADDR_M (SPI_SLV_LAST_ADDR_V << SPI_SLV_LAST_ADDR_S) -#define SPI_SLV_LAST_ADDR_V 0x0000003F -#define SPI_SLV_LAST_ADDR_S 26 - -/* SPI_SLV_LAST_COMMAND : R/W/SS; bitpos: [25:18]; default: 0; - * In the slave mode it is the value of command. - */ - -#define SPI_SLV_LAST_COMMAND 0x000000FF -#define SPI_SLV_LAST_COMMAND_M (SPI_SLV_LAST_COMMAND_V << SPI_SLV_LAST_COMMAND_S) -#define SPI_SLV_LAST_COMMAND_V 0x000000FF -#define SPI_SLV_LAST_COMMAND_S 18 - -/* SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0; - * The transferred data bit length in SPI slave FD and HD mode. - */ - -#define SPI_SLV_DATA_BITLEN 0x0003FFFF -#define SPI_SLV_DATA_BITLEN_M (SPI_SLV_DATA_BITLEN_V << SPI_SLV_DATA_BITLEN_S) -#define SPI_SLV_DATA_BITLEN_V 0x0003FFFF -#define SPI_SLV_DATA_BITLEN_S 0 - -/* SPI_CLK_GATE_REG register - * SPI module clock and register clock control - */ - -#define SPI_CLK_GATE_REG (DR_REG_SPI2_BASE + 0xe8) - -/* SPI_MST_CLK_SEL : R/W; bitpos: [2]; default: 0; - * This bit is used to select SPI module clock source in master mode. 1: - * PLL_CLK_80M. 0: XTAL CLK. - */ - -#define SPI_MST_CLK_SEL (BIT(2)) -#define SPI_MST_CLK_SEL_M (SPI_MST_CLK_SEL_V << SPI_MST_CLK_SEL_S) -#define SPI_MST_CLK_SEL_V 0x00000001 -#define SPI_MST_CLK_SEL_S 2 - -/* SPI_MST_CLK_ACTIVE : R/W; bitpos: [1]; default: 0; - * Set this bit to power on the SPI module clock. - */ - -#define SPI_MST_CLK_ACTIVE (BIT(1)) -#define SPI_MST_CLK_ACTIVE_M (SPI_MST_CLK_ACTIVE_V << SPI_MST_CLK_ACTIVE_S) -#define SPI_MST_CLK_ACTIVE_V 0x00000001 -#define SPI_MST_CLK_ACTIVE_S 1 - -/* SPI_CLK_EN : R/W; bitpos: [0]; default: 0; - * Set this bit to enable clk gate - */ - -#define SPI_CLK_EN (BIT(0)) -#define SPI_CLK_EN_M (SPI_CLK_EN_V << SPI_CLK_EN_S) -#define SPI_CLK_EN_V 0x00000001 -#define SPI_CLK_EN_S 0 - -/* SPI_DATE_REG register - * Version control - */ - -#define SPI_DATE_REG (DR_REG_SPI2_BASE + 0xf0) - -/* SPI_DATE : R/W; bitpos: [27:0]; default: 33583648; - * SPI register version. - */ - -#define SPI_DATE 0x0FFFFFFF -#define SPI_DATE_M (SPI_DATE_V << SPI_DATE_S) -#define SPI_DATE_V 0x0FFFFFFF -#define SPI_DATE_S 0 - -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_SPI_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_tim.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_tim.h deleted file mode 100644 index 0049bb91378dc..0000000000000 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_tim.h +++ /dev/null @@ -1,537 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_tim.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_TIM_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_TIM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32c3_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Offset relative to each watchdog timer instance memory base */ - -#define MWDT_CONFIG0_OFFSET 0x0048 - -/* MWDT */ - -#define MWDT_CLK_PRESCALE_OFFSET 0x004c -#define MWDT_STAGE0_TIMEOUT_OFFSET 0x0050 -#define MWDT_STAGE1_TIMEOUT_OFFSET 0x0054 -#define MWDT_STAGE2_TIMEOUT_OFFSET 0x0058 -#define MWDT_STAGE3_TIMEOUT_OFFSET 0x005c -#define MWDT_FEED_OFFSET 0x0060 -#define MWDT_WP_REG 0x0064 -#define MWDT_INT_ENA_REG_OFFSET 0x0070 -#define MWDT_INT_CLR_REG_OFFSET 0x007c - -/* The value that needs to be written to TIMG_WDT_WKEY to - * write-enable the WDT registers. - */ - -#define TIMG_WDT_WKEY_VALUE 0x50D83AA1 - -/* Possible values for TIMG_WDT_STGx */ - -#define TIMG_WDT_STG_SEL_OFF 0 -#define TIMG_WDT_STG_SEL_INT 1 -#define TIMG_WDT_STG_SEL_RESET_CPU 2 -#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3 - -#define TIMG_WDT_RESET_LENGTH_100_NS 0 -#define TIMG_WDT_RESET_LENGTH_200_NS 1 -#define TIMG_WDT_RESET_LENGTH_300_NS 2 -#define TIMG_WDT_RESET_LENGTH_400_NS 3 -#define TIMG_WDT_RESET_LENGTH_500_NS 4 -#define TIMG_WDT_RESET_LENGTH_800_NS 5 -#define TIMG_WDT_RESET_LENGTH_1600_NS 6 -#define TIMG_WDT_RESET_LENGTH_3200_NS 7 - -/* Maximum value in the high 22 bits from timer counters */ - -#define LOW_32_MASK 0xffffffff -#define LOW_22_MASK 0x003fffff -#define LOW_20_MASK 0x000fffff -#define LOW_26_MASK 0x03ffffff -#define SHIFT_32 32 - -#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000) - -/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ - -#define TIMG_T0_EN (BIT(31)) -#define TIMG_T0_EN_M (BIT(31)) -#define TIMG_T0_EN_V 0x1 -#define TIMG_T0_EN_S 31 - -/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ - -#define TIMG_T0_INCREASE (BIT(30)) -#define TIMG_T0_INCREASE_M (BIT(30)) -#define TIMG_T0_INCREASE_V 0x1 -#define TIMG_T0_INCREASE_S 30 - -/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ - -#define TIMG_T0_AUTORELOAD (BIT(29)) -#define TIMG_T0_AUTORELOAD_M (BIT(29)) -#define TIMG_T0_AUTORELOAD_V 0x1 -#define TIMG_T0_AUTORELOAD_S 29 - -/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ - -#define TIMG_T0_DIVIDER 0x0000FFFF -#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S)) -#define TIMG_T0_DIVIDER_V 0xFFFF -#define TIMG_T0_DIVIDER_S 13 - -/* TIMG_T0_DIVCNT_RST : WT ;bitpos:[12] ;default: 1'h0 ; */ - -#define TIMG_T0_DIVCNT_RST (BIT(12)) -#define TIMG_T0_DIVCNT_RST_M (BIT(12)) -#define TIMG_T0_DIVCNT_RST_V 0x1 -#define TIMG_T0_DIVCNT_RST_S 12 - -/* TIMG_T0_ALARM_EN : R/W/SC ;bitpos:[10] ;default: 1'h0 ; */ - -#define TIMG_T0_ALARM_EN (BIT(10)) -#define TIMG_T0_ALARM_EN_M (BIT(10)) -#define TIMG_T0_ALARM_EN_V 0x1 -#define TIMG_T0_ALARM_EN_S 10 - -/* TIMG_T0_USE_XTAL : R/W ;bitpos:[9] ;default: 1'd0 ; */ - -#define TIMG_T0_USE_XTAL (BIT(9)) -#define TIMG_T0_USE_XTAL_M (BIT(9)) -#define TIMG_T0_USE_XTAL_V 0x1 -#define TIMG_T0_USE_XTAL_S 9 - -#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004) - -/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ - -#define TIMG_T0_LO 0xFFFFFFFF -#define TIMG_T0_LO_M ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S)) -#define TIMG_T0_LO_V 0xFFFFFFFF -#define TIMG_T0_LO_S 0 - -#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008) - -/* TIMG_T0_HI : RO ;bitpos:[21:0] ;default: 22'h0 ; */ - -#define TIMG_T0_HI 0x003FFFFF -#define TIMG_T0_HI_M ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S)) -#define TIMG_T0_HI_V 0x3FFFFF -#define TIMG_T0_HI_S 0 - -#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c) - -/* TIMG_T0_UPDATE : R/W/SC ;bitpos:[31] ;default: 1'h0 ; */ - -#define TIMG_T0_UPDATE (BIT(31)) -#define TIMG_T0_UPDATE_M (BIT(31)) -#define TIMG_T0_UPDATE_V 0x1 -#define TIMG_T0_UPDATE_S 31 - -#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010) - -/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ - -#define TIMG_T0_ALARM_LO 0xFFFFFFFF -#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S)) -#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF -#define TIMG_T0_ALARM_LO_S 0 - -#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014) - -/* TIMG_T0_ALARM_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ - -#define TIMG_T0_ALARM_HI 0x003FFFFF -#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S)) -#define TIMG_T0_ALARM_HI_V 0x3FFFFF -#define TIMG_T0_ALARM_HI_S 0 - -#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018) - -/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ - -#define TIMG_T0_LOAD_LO 0xFFFFFFFF -#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S)) -#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF -#define TIMG_T0_LOAD_LO_S 0 - -#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c) - -/* TIMG_T0_LOAD_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ - -#define TIMG_T0_LOAD_HI 0x003FFFFF -#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S)) -#define TIMG_T0_LOAD_HI_V 0x3FFFFF -#define TIMG_T0_LOAD_HI_S 0 - -#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020) - -/* TIMG_T0_LOAD : WT ;bitpos:[31:0] ;default: 32'h0 ; */ - -#define TIMG_T0_LOAD 0xFFFFFFFF -#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S)) -#define TIMG_T0_LOAD_V 0xFFFFFFFF -#define TIMG_T0_LOAD_S 0 - -#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048) - -/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ - -#define TIMG_WDT_EN (BIT(31)) -#define TIMG_WDT_EN_M (BIT(31)) -#define TIMG_WDT_EN_V 0x1 -#define TIMG_WDT_EN_S 31 - -/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 2'd0 ; */ - -#define TIMG_WDT_STG0 0x00000003 -#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S)) -#define TIMG_WDT_STG0_V 0x3 -#define TIMG_WDT_STG0_S 29 - -/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ - -#define TIMG_WDT_STG1 0x00000003 -#define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S)) -#define TIMG_WDT_STG1_V 0x3 -#define TIMG_WDT_STG1_S 27 - -/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 2'd0 ; */ - -#define TIMG_WDT_STG2 0x00000003 -#define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S)) -#define TIMG_WDT_STG2_V 0x3 -#define TIMG_WDT_STG2_S 25 - -/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 2'd0 ; */ - -#define TIMG_WDT_STG3 0x00000003 -#define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S)) -#define TIMG_WDT_STG3_V 0x3 -#define TIMG_WDT_STG3_S 23 - -/* TIMG_WDT_CONF_UPDATE_EN : WT ;bitpos:[22] ;default: 1'h0 ; */ - -#define TIMG_WDT_CONF_UPDATE_EN (BIT(22)) -#define TIMG_WDT_CONF_UPDATE_EN_M (BIT(22)) -#define TIMG_WDT_CONF_UPDATE_EN_V 0x1 -#define TIMG_WDT_CONF_UPDATE_EN_S 22 - -/* TIMG_WDT_USE_XTAL : R/W ;bitpos:[21] ;default: 1'h0 ; */ - -#define TIMG_WDT_USE_XTAL (BIT(21)) -#define TIMG_WDT_USE_XTAL_M (BIT(21)) -#define TIMG_WDT_USE_XTAL_V 0x1 -#define TIMG_WDT_USE_XTAL_S 21 - -/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */ - -#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007 -#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S)) -#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7 -#define TIMG_WDT_CPU_RESET_LENGTH_S 18 - -/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */ - -#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007 -#define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S)) -#define TIMG_WDT_SYS_RESET_LENGTH_V 0x7 -#define TIMG_WDT_SYS_RESET_LENGTH_S 15 - -/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ - -#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) -#define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14)) -#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1 -#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 - -/* TIMG_WDT_PROCPU_RESET_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */ - -#define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) -#define TIMG_WDT_PROCPU_RESET_EN_M (BIT(13)) -#define TIMG_WDT_PROCPU_RESET_EN_V 0x1 -#define TIMG_WDT_PROCPU_RESET_EN_S 13 - -/* TIMG_WDT_APPCPU_RESET_EN : R/W ;bitpos:[12] ;default: 1'd0 ; */ - -#define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) -#define TIMG_WDT_APPCPU_RESET_EN_M (BIT(12)) -#define TIMG_WDT_APPCPU_RESET_EN_V 0x1 -#define TIMG_WDT_APPCPU_RESET_EN_S 12 - -#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c) - -/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */ - -#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF -#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S)) -#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF -#define TIMG_WDT_CLK_PRESCALE_S 16 - -/* TIMG_WDT_DIVCNT_RST : WT ;bitpos:[0] ;default: 1'b0 ; */ - -#define TIMG_WDT_DIVCNT_RST (BIT(0)) -#define TIMG_WDT_DIVCNT_RST_M (BIT(0)) -#define TIMG_WDT_DIVCNT_RST_V 0x1 -#define TIMG_WDT_DIVCNT_RST_S 0 - -#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050) - -/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */ - -#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF -#define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S)) -#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF -#define TIMG_WDT_STG0_HOLD_S 0 - -#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054) - -/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */ - -#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF -#define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S)) -#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF -#define TIMG_WDT_STG1_HOLD_S 0 - -#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058) - -/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ - -#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF -#define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S)) -#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF -#define TIMG_WDT_STG2_HOLD_S 0 - -#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c) - -/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ - -#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF -#define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S)) -#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF -#define TIMG_WDT_STG3_HOLD_S 0 - -#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060) - -/* TIMG_WDT_FEED : WT ;bitpos:[31:0] ;default: 32'h0 ; */ - -#define TIMG_WDT_FEED 0xFFFFFFFF -#define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S)) -#define TIMG_WDT_FEED_V 0xFFFFFFFF -#define TIMG_WDT_FEED_S 0 - -#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064) - -/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ - -#define TIMG_WDT_WKEY 0xFFFFFFFF -#define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S)) -#define TIMG_WDT_WKEY_V 0xFFFFFFFF -#define TIMG_WDT_WKEY_S 0 - -#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068) - -/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */ - -#define TIMG_RTC_CALI_START (BIT(31)) -#define TIMG_RTC_CALI_START_M (BIT(31)) -#define TIMG_RTC_CALI_START_V 0x1 -#define TIMG_RTC_CALI_START_S 31 - -/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */ - -#define TIMG_RTC_CALI_MAX 0x00007FFF -#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S)) -#define TIMG_RTC_CALI_MAX_V 0x7FFF -#define TIMG_RTC_CALI_MAX_S 16 - -/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */ - -#define TIMG_RTC_CALI_RDY (BIT(15)) -#define TIMG_RTC_CALI_RDY_M (BIT(15)) -#define TIMG_RTC_CALI_RDY_V 0x1 -#define TIMG_RTC_CALI_RDY_S 15 - -/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */ - -#define TIMG_RTC_CALI_CLK_SEL 0x00000003 -#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S)) -#define TIMG_RTC_CALI_CLK_SEL_V 0x3 -#define TIMG_RTC_CALI_CLK_SEL_S 13 - -/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */ - -#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) -#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12)) -#define TIMG_RTC_CALI_START_CYCLING_V 0x1 -#define TIMG_RTC_CALI_START_CYCLING_S 12 - -#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c) - -/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */ - -#define TIMG_RTC_CALI_VALUE 0x01FFFFFF -#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S)) -#define TIMG_RTC_CALI_VALUE_V 0x1FFFFFF -#define TIMG_RTC_CALI_VALUE_S 7 - -/* TIMG_RTC_CALI_CYCLING_DATA_VLD : RO ;bitpos:[0] ;default: 1'b0 ; */ - -#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) -#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (BIT(0)) -#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x1 -#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 - -#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0070) - -/* TIMG_WDT_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ - -#define TIMG_WDT_INT_ENA (BIT(1)) -#define TIMG_WDT_INT_ENA_M (BIT(1)) -#define TIMG_WDT_INT_ENA_V 0x1 -#define TIMG_WDT_INT_ENA_S 1 - -/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ - -#define TIMG_T0_INT_ENA (BIT(0)) -#define TIMG_T0_INT_ENA_M (BIT(0)) -#define TIMG_T0_INT_ENA_V 0x1 -#define TIMG_T0_INT_ENA_S 0 - -#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0074) - -/* TIMG_WDT_INT_RAW : R/SS/WTC ;bitpos:[1] ;default: 1'h0 ; */ - -#define TIMG_WDT_INT_RAW (BIT(1)) -#define TIMG_WDT_INT_RAW_M (BIT(1)) -#define TIMG_WDT_INT_RAW_V 0x1 -#define TIMG_WDT_INT_RAW_S 1 - -/* TIMG_T0_INT_RAW : R/SS/WTC ;bitpos:[0] ;default: 1'h0 ; */ - -#define TIMG_T0_INT_RAW (BIT(0)) -#define TIMG_T0_INT_RAW_M (BIT(0)) -#define TIMG_T0_INT_RAW_V 0x1 -#define TIMG_T0_INT_RAW_S 0 - -#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0078) - -/* TIMG_WDT_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ - -#define TIMG_WDT_INT_ST (BIT(1)) -#define TIMG_WDT_INT_ST_M (BIT(1)) -#define TIMG_WDT_INT_ST_V 0x1 -#define TIMG_WDT_INT_ST_S 1 - -/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ - -#define TIMG_T0_INT_ST (BIT(0)) -#define TIMG_T0_INT_ST_M (BIT(0)) -#define TIMG_T0_INT_ST_V 0x1 -#define TIMG_T0_INT_ST_S 0 - -#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x007c) - -/* TIMG_WDT_INT_CLR : WT ;bitpos:[1] ;default: 1'h0 ; */ - -#define TIMG_WDT_INT_CLR (BIT(1)) -#define TIMG_WDT_INT_CLR_M (BIT(1)) -#define TIMG_WDT_INT_CLR_V 0x1 -#define TIMG_WDT_INT_CLR_S 1 - -/* TIMG_T0_INT_CLR : WT ;bitpos:[0] ;default: 1'h0 ; */ - -#define TIMG_T0_INT_CLR (BIT(0)) -#define TIMG_T0_INT_CLR_M (BIT(0)) -#define TIMG_T0_INT_CLR_V 0x1 -#define TIMG_T0_INT_CLR_S 0 - -#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x0080) - -/* TIMG_RTC_CALI_TIMEOUT_THRES : R/W ;bitpos:[31:7] ;default: 25'h1ffffff ; */ - -/* description: timeout if cali value counts over threshold */ - -#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFF -#define TIMG_RTC_CALI_TIMEOUT_THRES_M ((TIMG_RTC_CALI_TIMEOUT_THRES_V)<<(TIMG_RTC_CALI_TIMEOUT_THRES_S)) -#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x1FFFFFF -#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 - -/* TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W ;bitpos:[6:3] ;default: 4'd3 ; */ - -/* description: Cycles that release calibration timeout reset */ - -#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000F -#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M ((TIMG_RTC_CALI_TIMEOUT_RST_CNT_V)<<(TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)) -#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0xF -#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 - -/* TIMG_RTC_CALI_TIMEOUT : RO ;bitpos:[0] ;default: 1'h0 ; */ - -/* description: timeout indicator */ - -#define TIMG_RTC_CALI_TIMEOUT (BIT(0)) -#define TIMG_RTC_CALI_TIMEOUT_M (BIT(0)) -#define TIMG_RTC_CALI_TIMEOUT_V 0x1 -#define TIMG_RTC_CALI_TIMEOUT_S 0 - -#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8) - -/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h2006191 ; */ - -#define TIMG_NTIMERS_DATE 0x0FFFFFFF -#define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S)) -#define TIMG_NTIMERS_DATE_V 0xFFFFFFF -#define TIMG_NTIMERS_DATE_S 0 - -#define TIMG_CLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc) - -/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ - -#define TIMG_CLK_EN (BIT(31)) -#define TIMG_CLK_EN_M (BIT(31)) -#define TIMG_CLK_EN_V 0x1 -#define TIMG_CLK_EN_S 31 - -/* TIMG_TIMER_CLK_IS_ACTIVE : R/W ;bitpos:[30] ;default: 1'h1 ; */ - -#define TIMG_TIMER_CLK_IS_ACTIVE (BIT(30)) -#define TIMG_TIMER_CLK_IS_ACTIVE_M (BIT(30)) -#define TIMG_TIMER_CLK_IS_ACTIVE_V 0x1 -#define TIMG_TIMER_CLK_IS_ACTIVE_S 30 - -/* TIMG_WDT_CLK_IS_ACTIVE : R/W ;bitpos:[29] ;default: 1'h1 ; */ - -#define TIMG_WDT_CLK_IS_ACTIVE (BIT(29)) -#define TIMG_WDT_CLK_IS_ACTIVE_M (BIT(29)) -#define TIMG_WDT_CLK_IS_ACTIVE_V 0x1 -#define TIMG_WDT_CLK_IS_ACTIVE_S 29 - -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_TIM_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_twai.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_twai.h deleted file mode 100644 index 2aa56b84dd28a..0000000000000 --- a/arch/risc-v/src/esp32c3/hardware/esp32c3_twai.h +++ /dev/null @@ -1,856 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/esp32c3_twai.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_TWAI_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_TWAI_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32c3_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* TWAI_MODE_REG register - * Mode Register - */ - -#define TWAI_MODE_REG (DR_REG_TWAI_BASE + 0x0) - -/* TWAI_RX_FILTER_MODE : R/W; bitpos: [3]; default: 0; - * This bit is used to configure the filter mode. 0: Dual filter mode; 1: - * Single filter mode. - */ - -#define TWAI_RX_FILTER_MODE (BIT(3)) -#define TWAI_RX_FILTER_MODE_M (TWAI_RX_FILTER_MODE_V << TWAI_RX_FILTER_MODE_S) -#define TWAI_RX_FILTER_MODE_V 0x00000001 -#define TWAI_RX_FILTER_MODE_S 3 - -/* TWAI_SELF_TEST_MODE : R/W; bitpos: [2]; default: 0; - * 1: Self test mode. In this mode the TX nodes can perform a successful - * transmission without receiving the acknowledge signal. This mode is often - * used to test a single node with the self reception request command. - */ - -#define TWAI_SELF_TEST_MODE (BIT(2)) -#define TWAI_SELF_TEST_MODE_M (TWAI_SELF_TEST_MODE_V << TWAI_SELF_TEST_MODE_S) -#define TWAI_SELF_TEST_MODE_V 0x00000001 -#define TWAI_SELF_TEST_MODE_S 2 - -/* TWAI_LISTEN_ONLY_MODE : R/W; bitpos: [1]; default: 0; - * 1: Listen only mode. In this mode the nodes will only receive messages - * from the bus, without generating the acknowledge signal nor updating the - * RX error counter. - */ - -#define TWAI_LISTEN_ONLY_MODE (BIT(1)) -#define TWAI_LISTEN_ONLY_MODE_M (TWAI_LISTEN_ONLY_MODE_V << TWAI_LISTEN_ONLY_MODE_S) -#define TWAI_LISTEN_ONLY_MODE_V 0x00000001 -#define TWAI_LISTEN_ONLY_MODE_S 1 - -/* TWAI_RESET_MODE : R/W; bitpos: [0]; default: 1; - * This bit is used to configure the operating mode of the TWAI Controller. - * 1: Reset mode; 0: Operating mode. - */ - -#define TWAI_RESET_MODE (BIT(0)) -#define TWAI_RESET_MODE_M (TWAI_RESET_MODE_V << TWAI_RESET_MODE_S) -#define TWAI_RESET_MODE_V 0x00000001 -#define TWAI_RESET_MODE_S 0 - -/* TWAI_CMD_REG register - * Command Register - */ - -#define TWAI_CMD_REG (DR_REG_TWAI_BASE + 0x4) - -/* TWAI_SELF_RX_REQ : WO; bitpos: [4]; default: 0; - * Self reception request command. Set the bit to 1 to allow a message be - * transmitted and received simultaneously. - */ - -#define TWAI_SELF_RX_REQ (BIT(4)) -#define TWAI_SELF_RX_REQ_M (TWAI_SELF_RX_REQ_V << TWAI_SELF_RX_REQ_S) -#define TWAI_SELF_RX_REQ_V 0x00000001 -#define TWAI_SELF_RX_REQ_S 4 - -/* TWAI_CLR_OVERRUN : WO; bitpos: [3]; default: 0; - * Set the bit to 1 to clear the data overrun status bit. - */ - -#define TWAI_CLR_OVERRUN (BIT(3)) -#define TWAI_CLR_OVERRUN_M (TWAI_CLR_OVERRUN_V << TWAI_CLR_OVERRUN_S) -#define TWAI_CLR_OVERRUN_V 0x00000001 -#define TWAI_CLR_OVERRUN_S 3 - -/* TWAI_RELEASE_BUF : WO; bitpos: [2]; default: 0; - * Set the bit to 1 to release the RX buffer. - */ - -#define TWAI_RELEASE_BUF (BIT(2)) -#define TWAI_RELEASE_BUF_M (TWAI_RELEASE_BUF_V << TWAI_RELEASE_BUF_S) -#define TWAI_RELEASE_BUF_V 0x00000001 -#define TWAI_RELEASE_BUF_S 2 - -/* TWAI_ABORT_TX : WO; bitpos: [1]; default: 0; - * Set the bit to 1 to cancel a pending transmission request. - */ - -#define TWAI_ABORT_TX (BIT(1)) -#define TWAI_ABORT_TX_M (TWAI_ABORT_TX_V << TWAI_ABORT_TX_S) -#define TWAI_ABORT_TX_V 0x00000001 -#define TWAI_ABORT_TX_S 1 - -/* TWAI_TX_REQ : WO; bitpos: [0]; default: 0; - * Set the bit to 1 to allow the driving nodes start transmission. - */ - -#define TWAI_TX_REQ (BIT(0)) -#define TWAI_TX_REQ_M (TWAI_TX_REQ_V << TWAI_TX_REQ_S) -#define TWAI_TX_REQ_V 0x00000001 -#define TWAI_TX_REQ_S 0 - -/* TWAI_STATUS_REG register - * Status register - */ - -#define TWAI_STATUS_REG (DR_REG_TWAI_BASE + 0x8) - -/* TWAI_MISS_ST : RO; bitpos: [8]; default: 0; - * This bit reflects whether the data packet in the RX FIFO is complete. 1: - * The current packet is missing; 0: The current packet is complete - */ - -#define TWAI_MISS_ST (BIT(8)) -#define TWAI_MISS_ST_M (TWAI_MISS_ST_V << TWAI_MISS_ST_S) -#define TWAI_MISS_ST_V 0x00000001 -#define TWAI_MISS_ST_S 8 - -/* TWAI_BUS_OFF_ST : RO; bitpos: [7]; default: 0; - * 1: In bus-off status, the TWAI Controller is no longer involved in bus - * activities. - */ - -#define TWAI_BUS_OFF_ST (BIT(7)) -#define TWAI_BUS_OFF_ST_M (TWAI_BUS_OFF_ST_V << TWAI_BUS_OFF_ST_S) -#define TWAI_BUS_OFF_ST_V 0x00000001 -#define TWAI_BUS_OFF_ST_S 7 - -/* TWAI_ERR_ST : RO; bitpos: [6]; default: 0; - * 1: At least one of the RX/TX error counter has reached or exceeded the - * value set in register TWAI_ERR_WARNING_LIMIT_REG. - */ - -#define TWAI_ERR_ST (BIT(6)) -#define TWAI_ERR_ST_M (TWAI_ERR_ST_V << TWAI_ERR_ST_S) -#define TWAI_ERR_ST_V 0x00000001 -#define TWAI_ERR_ST_S 6 - -/* TWAI_TX_ST : RO; bitpos: [5]; default: 0; - * 1: The TWAI Controller is transmitting a message to the bus. - */ - -#define TWAI_TX_ST (BIT(5)) -#define TWAI_TX_ST_M (TWAI_TX_ST_V << TWAI_TX_ST_S) -#define TWAI_TX_ST_V 0x00000001 -#define TWAI_TX_ST_S 5 - -/* TWAI_RX_ST : RO; bitpos: [4]; default: 0; - * 1: The TWAI Controller is receiving a message from the bus. - */ - -#define TWAI_RX_ST (BIT(4)) -#define TWAI_RX_ST_M (TWAI_RX_ST_V << TWAI_RX_ST_S) -#define TWAI_RX_ST_V 0x00000001 -#define TWAI_RX_ST_S 4 - -/* TWAI_TX_COMPLETE : RO; bitpos: [3]; default: 0; - * 1: The TWAI controller has successfully received a packet from the bus. - */ - -#define TWAI_TX_COMPLETE (BIT(3)) -#define TWAI_TX_COMPLETE_M (TWAI_TX_COMPLETE_V << TWAI_TX_COMPLETE_S) -#define TWAI_TX_COMPLETE_V 0x00000001 -#define TWAI_TX_COMPLETE_S 3 - -/* TWAI_TX_BUF_ST : RO; bitpos: [2]; default: 0; - * 1: The TX buffer is empty, the CPU may write a message into it. - */ - -#define TWAI_TX_BUF_ST (BIT(2)) -#define TWAI_TX_BUF_ST_M (TWAI_TX_BUF_ST_V << TWAI_TX_BUF_ST_S) -#define TWAI_TX_BUF_ST_V 0x00000001 -#define TWAI_TX_BUF_ST_S 2 - -/* TWAI_OVERRUN_ST : RO; bitpos: [1]; default: 0; - * 1: The RX FIFO is full and data overrun has occurred. - */ - -#define TWAI_OVERRUN_ST (BIT(1)) -#define TWAI_OVERRUN_ST_M (TWAI_OVERRUN_ST_V << TWAI_OVERRUN_ST_S) -#define TWAI_OVERRUN_ST_V 0x00000001 -#define TWAI_OVERRUN_ST_S 1 - -/* TWAI_RX_BUF_ST : RO; bitpos: [0]; default: 0; - * 1: The data in the RX buffer is not empty, with at least one received - * data packet. - */ - -#define TWAI_RX_BUF_ST (BIT(0)) -#define TWAI_RX_BUF_ST_M (TWAI_RX_BUF_ST_V << TWAI_RX_BUF_ST_S) -#define TWAI_RX_BUF_ST_V 0x00000001 -#define TWAI_RX_BUF_ST_S 0 - -/* TWAI_INT_RAW_REG register - * Interrupt Register - */ - -#define TWAI_INT_RAW_REG (DR_REG_TWAI_BASE + 0xc) - -/* TWAI_BUS_ERR_INT_ST : RO; bitpos: [7]; default: 0; - * Error interrupt. If this bit is set to 1, it indicates an error is - * detected on the bus. - */ - -#define TWAI_BUS_ERR_INT_ST (BIT(7)) -#define TWAI_BUS_ERR_INT_ST_M (TWAI_BUS_ERR_INT_ST_V << TWAI_BUS_ERR_INT_ST_S) -#define TWAI_BUS_ERR_INT_ST_V 0x00000001 -#define TWAI_BUS_ERR_INT_ST_S 7 - -/* TWAI_ARB_LOST_INT_ST : RO; bitpos: [6]; default: 0; - * Arbitration lost interrupt. If this bit is set to 1, it indicates an - * arbitration lost interrupt is generated. - */ - -#define TWAI_ARB_LOST_INT_ST (BIT(6)) -#define TWAI_ARB_LOST_INT_ST_M (TWAI_ARB_LOST_INT_ST_V << TWAI_ARB_LOST_INT_ST_S) -#define TWAI_ARB_LOST_INT_ST_V 0x00000001 -#define TWAI_ARB_LOST_INT_ST_S 6 - -/* TWAI_ERR_PASSIVE_INT_ST : RO; bitpos: [5]; default: 0; - * Error passive interrupt. If this bit is set to 1, it indicates the TWAI - * Controller is switched between error active status and error passive - * status due to the change of error counters. - */ - -#define TWAI_ERR_PASSIVE_INT_ST (BIT(5)) -#define TWAI_ERR_PASSIVE_INT_ST_M (TWAI_ERR_PASSIVE_INT_ST_V << TWAI_ERR_PASSIVE_INT_ST_S) -#define TWAI_ERR_PASSIVE_INT_ST_V 0x00000001 -#define TWAI_ERR_PASSIVE_INT_ST_S 5 - -/* TWAI_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0; - * Data overrun interrupt. If this bit is set to 1, it indicates a data - * overrun interrupt is generated in the RX FIFO. - */ - -#define TWAI_OVERRUN_INT_ST (BIT(3)) -#define TWAI_OVERRUN_INT_ST_M (TWAI_OVERRUN_INT_ST_V << TWAI_OVERRUN_INT_ST_S) -#define TWAI_OVERRUN_INT_ST_V 0x00000001 -#define TWAI_OVERRUN_INT_ST_S 3 - -/* TWAI_ERR_WARN_INT_ST : RO; bitpos: [2]; default: 0; - * Error warning interrupt. If this bit is set to 1, it indicates the error - * status signal and the bus-off status signal of Status register have - * changed (e.g., switched from 0 to 1 or from 1 to 0). - */ - -#define TWAI_ERR_WARN_INT_ST (BIT(2)) -#define TWAI_ERR_WARN_INT_ST_M (TWAI_ERR_WARN_INT_ST_V << TWAI_ERR_WARN_INT_ST_S) -#define TWAI_ERR_WARN_INT_ST_V 0x00000001 -#define TWAI_ERR_WARN_INT_ST_S 2 - -/* TWAI_TX_INT_ST : RO; bitpos: [1]; default: 0; - * Transmit interrupt. If this bit is set to 1, it indicates the message - * transmitting mis- sion is finished and a new transmission is able to - * execute. - */ - -#define TWAI_TX_INT_ST (BIT(1)) -#define TWAI_TX_INT_ST_M (TWAI_TX_INT_ST_V << TWAI_TX_INT_ST_S) -#define TWAI_TX_INT_ST_V 0x00000001 -#define TWAI_TX_INT_ST_S 1 - -/* TWAI_RX_INT_ST : RO; bitpos: [0]; default: 0; - * Receive interrupt. If this bit is set to 1, it indicates there are - * messages to be handled in the RX FIFO. - */ - -#define TWAI_RX_INT_ST (BIT(0)) -#define TWAI_RX_INT_ST_M (TWAI_RX_INT_ST_V << TWAI_RX_INT_ST_S) -#define TWAI_RX_INT_ST_V 0x00000001 -#define TWAI_RX_INT_ST_S 0 - -/* TWAI_INT_ENA_REG register - * Interrupt Enable Register - */ - -#define TWAI_INT_ENA_REG (DR_REG_TWAI_BASE + 0x10) - -/* TWAI_BUS_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; - * Set this bit to 1 to enable error interrupt. - */ - -#define TWAI_BUS_ERR_INT_ENA (BIT(7)) -#define TWAI_BUS_ERR_INT_ENA_M (TWAI_BUS_ERR_INT_ENA_V << TWAI_BUS_ERR_INT_ENA_S) -#define TWAI_BUS_ERR_INT_ENA_V 0x00000001 -#define TWAI_BUS_ERR_INT_ENA_S 7 - -/* TWAI_ARB_LOST_INT_ENA : R/W; bitpos: [6]; default: 0; - * Set this bit to 1 to enable arbitration lost interrupt. - */ - -#define TWAI_ARB_LOST_INT_ENA (BIT(6)) -#define TWAI_ARB_LOST_INT_ENA_M (TWAI_ARB_LOST_INT_ENA_V << TWAI_ARB_LOST_INT_ENA_S) -#define TWAI_ARB_LOST_INT_ENA_V 0x00000001 -#define TWAI_ARB_LOST_INT_ENA_S 6 - -/* TWAI_ERR_PASSIVE_INT_ENA : R/W; bitpos: [5]; default: 0; - * Set this bit to 1 to enable error passive interrupt. - */ - -#define TWAI_ERR_PASSIVE_INT_ENA (BIT(5)) -#define TWAI_ERR_PASSIVE_INT_ENA_M (TWAI_ERR_PASSIVE_INT_ENA_V << TWAI_ERR_PASSIVE_INT_ENA_S) -#define TWAI_ERR_PASSIVE_INT_ENA_V 0x00000001 -#define TWAI_ERR_PASSIVE_INT_ENA_S 5 - -/* TWAI_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0; - * Set this bit to 1 to enable data overrun interrupt. - */ - -#define TWAI_OVERRUN_INT_ENA (BIT(3)) -#define TWAI_OVERRUN_INT_ENA_M (TWAI_OVERRUN_INT_ENA_V << TWAI_OVERRUN_INT_ENA_S) -#define TWAI_OVERRUN_INT_ENA_V 0x00000001 -#define TWAI_OVERRUN_INT_ENA_S 3 - -/* TWAI_ERR_WARN_INT_ENA : R/W; bitpos: [2]; default: 0; - * Set this bit to 1 to enable error warning interrupt. - */ - -#define TWAI_ERR_WARN_INT_ENA (BIT(2)) -#define TWAI_ERR_WARN_INT_ENA_M (TWAI_ERR_WARN_INT_ENA_V << TWAI_ERR_WARN_INT_ENA_S) -#define TWAI_ERR_WARN_INT_ENA_V 0x00000001 -#define TWAI_ERR_WARN_INT_ENA_S 2 - -/* TWAI_TX_INT_ENA : R/W; bitpos: [1]; default: 0; - * Set this bit to 1 to enable transmit interrupt. - */ - -#define TWAI_TX_INT_ENA (BIT(1)) -#define TWAI_TX_INT_ENA_M (TWAI_TX_INT_ENA_V << TWAI_TX_INT_ENA_S) -#define TWAI_TX_INT_ENA_V 0x00000001 -#define TWAI_TX_INT_ENA_S 1 - -/* TWAI_RX_INT_ENA : R/W; bitpos: [0]; default: 0; - * Set this bit to 1 to enable receive interrupt. - */ - -#define TWAI_RX_INT_ENA (BIT(0)) -#define TWAI_RX_INT_ENA_M (TWAI_RX_INT_ENA_V << TWAI_RX_INT_ENA_S) -#define TWAI_RX_INT_ENA_V 0x00000001 -#define TWAI_RX_INT_ENA_S 0 - -/* TWAI_BUS_TIMING_0_REG register - * Bus Timing Register 0 - */ - -#define TWAI_BUS_TIMING_0_REG (DR_REG_TWAI_BASE + 0x18) - -/* TWAI_SYNC_JUMP_WIDTH : RO | R/W; bitpos: [15:14]; default: 0; - * Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. - */ - -#define TWAI_SYNC_JUMP_WIDTH 0x00000003 -#define TWAI_SYNC_JUMP_WIDTH_M (TWAI_SYNC_JUMP_WIDTH_V << TWAI_SYNC_JUMP_WIDTH_S) -#define TWAI_SYNC_JUMP_WIDTH_V 0x00000003 -#define TWAI_SYNC_JUMP_WIDTH_S 14 - -/* TWAI_BAUD_PRESC : RO | R/W; bitpos: [13:0]; default: 0; - * Baud Rate Prescaler, determines the frequency dividing ratio. - */ - -#define TWAI_BAUD_PRESC 0x00003FFF -#define TWAI_BAUD_PRESC_M (TWAI_BAUD_PRESC_V << TWAI_BAUD_PRESC_S) -#define TWAI_BAUD_PRESC_V 0x00003FFF -#define TWAI_BAUD_PRESC_S 0 - -/* TWAI_BUS_TIMING_1_REG register - * Bus Timing Register 1 - */ - -#define TWAI_BUS_TIMING_1_REG (DR_REG_TWAI_BASE + 0x1c) - -/* TWAI_TIME_SAMP : RO | R/W; bitpos: [7]; default: 0; - * The number of sample points. 0: the bus is sampled once; 1: the bus is - * sampled three times - */ - -#define TWAI_TIME_SAMP (BIT(7)) -#define TWAI_TIME_SAMP_M (TWAI_TIME_SAMP_V << TWAI_TIME_SAMP_S) -#define TWAI_TIME_SAMP_V 0x00000001 -#define TWAI_TIME_SAMP_S 7 - -/* TWAI_TIME_SEG2 : RO | R/W; bitpos: [6:4]; default: 0; - * The width of PBS2. - */ - -#define TWAI_TIME_SEG2 0x00000007 -#define TWAI_TIME_SEG2_M (TWAI_TIME_SEG2_V << TWAI_TIME_SEG2_S) -#define TWAI_TIME_SEG2_V 0x00000007 -#define TWAI_TIME_SEG2_S 4 - -/* TWAI_TIME_SEG1 : RO | R/W; bitpos: [3:0]; default: 0; - * The width of PBS1. - */ - -#define TWAI_TIME_SEG1 0x0000000F -#define TWAI_TIME_SEG1_M (TWAI_TIME_SEG1_V << TWAI_TIME_SEG1_S) -#define TWAI_TIME_SEG1_V 0x0000000F -#define TWAI_TIME_SEG1_S 0 - -/* TWAI_ARB_LOST_CAP_REG register - * Arbitration Lost Capture Register - */ - -#define TWAI_ARB_LOST_CAP_REG (DR_REG_TWAI_BASE + 0x2c) - -/* TWAI_ARB_LOST_CAP : RO; bitpos: [4:0]; default: 0; - * This register contains information about the bit position of lost - * arbitration. - */ - -#define TWAI_ARB_LOST_CAP 0x0000001F -#define TWAI_ARB_LOST_CAP_M (TWAI_ARB_LOST_CAP_V << TWAI_ARB_LOST_CAP_S) -#define TWAI_ARB_LOST_CAP_V 0x0000001F -#define TWAI_ARB_LOST_CAP_S 0 - -/* TWAI_ERR_CODE_CAP_REG register - * Error Code Capture Register - */ - -#define TWAI_ERR_CODE_CAP_REG (DR_REG_TWAI_BASE + 0x30) - -/* TWAI_ECC_TYPE : RO; bitpos: [7:6]; default: 0; - * This register contains information about error types: 00: bit error; 01: - * form error; 10: stuff error; 11: other type of error - */ - -#define TWAI_ECC_TYPE 0x00000003 -#define TWAI_ECC_TYPE_M (TWAI_ECC_TYPE_V << TWAI_ECC_TYPE_S) -#define TWAI_ECC_TYPE_V 0x00000003 -#define TWAI_ECC_TYPE_S 6 - -/* TWAI_ECC_DIRECTION : RO; bitpos: [5]; default: 0; - * This register contains information about transmission direction of the - * node when error occurs. 1: Error occurs when receiving a message; 0: - * Error occurs when transmitting a message - */ - -#define TWAI_ECC_DIRECTION (BIT(5)) -#define TWAI_ECC_DIRECTION_M (TWAI_ECC_DIRECTION_V << TWAI_ECC_DIRECTION_S) -#define TWAI_ECC_DIRECTION_V 0x00000001 -#define TWAI_ECC_DIRECTION_S 5 - -/* TWAI_ECC_SEGMENT : RO; bitpos: [4:0]; default: 0; - * This register contains information about the location of errors, see - * Table 181 for details. - */ - -#define TWAI_ECC_SEGMENT 0x0000001F -#define TWAI_ECC_SEGMENT_M (TWAI_ECC_SEGMENT_V << TWAI_ECC_SEGMENT_S) -#define TWAI_ECC_SEGMENT_V 0x0000001F -#define TWAI_ECC_SEGMENT_S 0 - -/* TWAI_ERR_WARNING_LIMIT_REG register - * Error Warning Limit Register - */ - -#define TWAI_ERR_WARNING_LIMIT_REG (DR_REG_TWAI_BASE + 0x34) - -/* TWAI_ERR_WARNING_LIMIT : RO | R/W; bitpos: [7:0]; default: 96; - * Error warning threshold. In the case when any of a error counter value - * exceeds the threshold, or all the error counter values are below the - * threshold, an error warning interrupt will be triggered (given the enable - * signal is valid). - */ - -#define TWAI_ERR_WARNING_LIMIT 0x000000FF -#define TWAI_ERR_WARNING_LIMIT_M (TWAI_ERR_WARNING_LIMIT_V << TWAI_ERR_WARNING_LIMIT_S) -#define TWAI_ERR_WARNING_LIMIT_V 0x000000FF -#define TWAI_ERR_WARNING_LIMIT_S 0 - -/* TWAI_RX_ERR_CNT_REG register - * Receive Error Counter Register - */ - -#define TWAI_RX_ERR_CNT_REG (DR_REG_TWAI_BASE + 0x38) - -/* TWAI_RX_ERR_CNT : RO | R/W; bitpos: [7:0]; default: 0; - * The RX error counter register, reflects value changes under reception - * status. - */ - -#define TWAI_RX_ERR_CNT 0x000000FF -#define TWAI_RX_ERR_CNT_M (TWAI_RX_ERR_CNT_V << TWAI_RX_ERR_CNT_S) -#define TWAI_RX_ERR_CNT_V 0x000000FF -#define TWAI_RX_ERR_CNT_S 0 - -/* TWAI_TX_ERR_CNT_REG register - * Transmit Error Counter Register - */ - -#define TWAI_TX_ERR_CNT_REG (DR_REG_TWAI_BASE + 0x3c) - -/* TWAI_TX_ERR_CNT : RO | R/W; bitpos: [7:0]; default: 0; - * The TX error counter register, reflects value changes under transmission - * status. - */ - -#define TWAI_TX_ERR_CNT 0x000000FF -#define TWAI_TX_ERR_CNT_M (TWAI_TX_ERR_CNT_V << TWAI_TX_ERR_CNT_S) -#define TWAI_TX_ERR_CNT_V 0x000000FF -#define TWAI_TX_ERR_CNT_S 0 - -/* TWAI_DATA_0_REG register - * Data register 0 - */ - -#define TWAI_DATA_0_REG (DR_REG_TWAI_BASE + 0x40) - -/* TWAI_TX_BYTE_0 : WO; bitpos: [7:0]; default: 0; - * Stored the 0th byte information of the data to be transmitted under - * operating mode. - */ - -#define TWAI_TX_BYTE_0 0x000000FF -#define TWAI_TX_BYTE_0_M (TWAI_TX_BYTE_0_V << TWAI_TX_BYTE_0_S) -#define TWAI_TX_BYTE_0_V 0x000000FF -#define TWAI_TX_BYTE_0_S 0 - -/* TWAI_ACCEPTANCE_CODE_0 : WO; bitpos: [7:0]; default: 0; - * Stored the 0th byte of the filter code in reset mode. - */ - -#define TWAI_ACCEPTANCE_CODE_0 0x000000FF -#define TWAI_ACCEPTANCE_CODE_0_M (TWAI_ACCEPTANCE_CODE_0_V << TWAI_ACCEPTANCE_CODE_0_S) -#define TWAI_ACCEPTANCE_CODE_0_V 0x000000FF -#define TWAI_ACCEPTANCE_CODE_0_S 0 - -/* TWAI_DATA_1_REG register - * Data register 1 - */ - -#define TWAI_DATA_1_REG (DR_REG_TWAI_BASE + 0x44) - -/* TWAI_TX_BYTE_1 : WO; bitpos: [7:0]; default: 0; - * Stored the 1st byte information of the data to be transmitted under - * operating mode. - */ - -#define TWAI_TX_BYTE_1 0x000000FF -#define TWAI_TX_BYTE_1_M (TWAI_TX_BYTE_1_V << TWAI_TX_BYTE_1_S) -#define TWAI_TX_BYTE_1_V 0x000000FF -#define TWAI_TX_BYTE_1_S 0 - -/* TWAI_ACCEPTANCE_CODE_1 : WO; bitpos: [7:0]; default: 0; - * Stored the 1st byte of the filter code in reset mode. - */ - -#define TWAI_ACCEPTANCE_CODE_1 0x000000FF -#define TWAI_ACCEPTANCE_CODE_1_M (TWAI_ACCEPTANCE_CODE_1_V << TWAI_ACCEPTANCE_CODE_1_S) -#define TWAI_ACCEPTANCE_CODE_1_V 0x000000FF -#define TWAI_ACCEPTANCE_CODE_1_S 0 - -/* TWAI_DATA_2_REG register - * Data register 2 - */ - -#define TWAI_DATA_2_REG (DR_REG_TWAI_BASE + 0x48) - -/* TWAI_TX_BYTE_2 : WO; bitpos: [7:0]; default: 0; - * Stored the 2nd byte information of the data to be transmitted under - * operating mode. - */ - -#define TWAI_TX_BYTE_2 0x000000FF -#define TWAI_TX_BYTE_2_M (TWAI_TX_BYTE_2_V << TWAI_TX_BYTE_2_S) -#define TWAI_TX_BYTE_2_V 0x000000FF -#define TWAI_TX_BYTE_2_S 0 - -/* TWAI_ACCEPTANCE_CODE_2 : WO; bitpos: [7:0]; default: 0; - * Stored the 2nd byte of the filter code in reset mode. - */ - -#define TWAI_ACCEPTANCE_CODE_2 0x000000FF -#define TWAI_ACCEPTANCE_CODE_2_M (TWAI_ACCEPTANCE_CODE_2_V << TWAI_ACCEPTANCE_CODE_2_S) -#define TWAI_ACCEPTANCE_CODE_2_V 0x000000FF -#define TWAI_ACCEPTANCE_CODE_2_S 0 - -/* TWAI_DATA_3_REG register - * Data register 3 - */ - -#define TWAI_DATA_3_REG (DR_REG_TWAI_BASE + 0x4c) - -/* TWAI_TX_BYTE_3 : WO; bitpos: [7:0]; default: 0; - * Stored the 3rd byte information of the data to be transmitted under - * operating mode. - */ - -#define TWAI_TX_BYTE_3 0x000000FF -#define TWAI_TX_BYTE_3_M (TWAI_TX_BYTE_3_V << TWAI_TX_BYTE_3_S) -#define TWAI_TX_BYTE_3_V 0x000000FF -#define TWAI_TX_BYTE_3_S 0 - -/* TWAI_ACCEPTANCE_CODE_3 : WO; bitpos: [7:0]; default: 0; - * Stored the 3rd byte of the filter code in reset mode. - */ - -#define TWAI_ACCEPTANCE_CODE_3 0x000000FF -#define TWAI_ACCEPTANCE_CODE_3_M (TWAI_ACCEPTANCE_CODE_3_V << TWAI_ACCEPTANCE_CODE_3_S) -#define TWAI_ACCEPTANCE_CODE_3_V 0x000000FF -#define TWAI_ACCEPTANCE_CODE_3_S 0 - -/* TWAI_DATA_4_REG register - * Data register 4 - */ - -#define TWAI_DATA_4_REG (DR_REG_TWAI_BASE + 0x50) - -/* TWAI_TX_BYTE_4 : WO; bitpos: [7:0]; default: 0; - * Stored the 4th byte information of the data to be transmitted under - * operating mode. - */ - -#define TWAI_TX_BYTE_4 0x000000FF -#define TWAI_TX_BYTE_4_M (TWAI_TX_BYTE_4_V << TWAI_TX_BYTE_4_S) -#define TWAI_TX_BYTE_4_V 0x000000FF -#define TWAI_TX_BYTE_4_S 0 - -/* TWAI_ACCEPTANCE_MASK_0 : WO; bitpos: [7:0]; default: 0; - * Stored the 0th byte of the filter code in reset mode. - */ - -#define TWAI_ACCEPTANCE_MASK_0 0x000000FF -#define TWAI_ACCEPTANCE_MASK_0_M (TWAI_ACCEPTANCE_MASK_0_V << TWAI_ACCEPTANCE_MASK_0_S) -#define TWAI_ACCEPTANCE_MASK_0_V 0x000000FF -#define TWAI_ACCEPTANCE_MASK_0_S 0 - -/* TWAI_DATA_5_REG register - * Data register 5 - */ - -#define TWAI_DATA_5_REG (DR_REG_TWAI_BASE + 0x54) - -/* TWAI_TX_BYTE_5 : WO; bitpos: [7:0]; default: 0; - * Stored the 5th byte information of the data to be transmitted under - * operating mode. - */ - -#define TWAI_TX_BYTE_5 0x000000FF -#define TWAI_TX_BYTE_5_M (TWAI_TX_BYTE_5_V << TWAI_TX_BYTE_5_S) -#define TWAI_TX_BYTE_5_V 0x000000FF -#define TWAI_TX_BYTE_5_S 0 - -/* TWAI_ACCEPTANCE_MASK_1 : WO; bitpos: [7:0]; default: 0; - * Stored the 1st byte of the filter code in reset mode. - */ - -#define TWAI_ACCEPTANCE_MASK_1 0x000000FF -#define TWAI_ACCEPTANCE_MASK_1_M (TWAI_ACCEPTANCE_MASK_1_V << TWAI_ACCEPTANCE_MASK_1_S) -#define TWAI_ACCEPTANCE_MASK_1_V 0x000000FF -#define TWAI_ACCEPTANCE_MASK_1_S 0 - -/* TWAI_DATA_6_REG register - * Data register 6 - */ - -#define TWAI_DATA_6_REG (DR_REG_TWAI_BASE + 0x58) - -/* TWAI_TX_BYTE_6 : WO; bitpos: [7:0]; default: 0; - * Stored the 6th byte information of the data to be transmitted under - * operating mode. - */ - -#define TWAI_TX_BYTE_6 0x000000FF -#define TWAI_TX_BYTE_6_M (TWAI_TX_BYTE_6_V << TWAI_TX_BYTE_6_S) -#define TWAI_TX_BYTE_6_V 0x000000FF -#define TWAI_TX_BYTE_6_S 0 - -/* TWAI_ACCEPTANCE_MASK_2 : WO; bitpos: [7:0]; default: 0; - * Stored the 2nd byte of the filter code in reset mode. - */ - -#define TWAI_ACCEPTANCE_MASK_2 0x000000FF -#define TWAI_ACCEPTANCE_MASK_2_M (TWAI_ACCEPTANCE_MASK_2_V << TWAI_ACCEPTANCE_MASK_2_S) -#define TWAI_ACCEPTANCE_MASK_2_V 0x000000FF -#define TWAI_ACCEPTANCE_MASK_2_S 0 - -/* TWAI_DATA_7_REG register - * Data register 7 - */ - -#define TWAI_DATA_7_REG (DR_REG_TWAI_BASE + 0x5c) - -/* TWAI_TX_BYTE_7 : WO; bitpos: [7:0]; default: 0; - * Stored the 7th byte information of the data to be transmitted under - * operating mode. - */ - -#define TWAI_TX_BYTE_7 0x000000FF -#define TWAI_TX_BYTE_7_M (TWAI_TX_BYTE_7_V << TWAI_TX_BYTE_7_S) -#define TWAI_TX_BYTE_7_V 0x000000FF -#define TWAI_TX_BYTE_7_S 0 - -/* TWAI_ACCEPTANCE_MASK_3 : WO; bitpos: [7:0]; default: 0; - * Stored the 3th byte of the filter code in reset mode. - */ - -#define TWAI_ACCEPTANCE_MASK_3 0x000000FF -#define TWAI_ACCEPTANCE_MASK_3_M (TWAI_ACCEPTANCE_MASK_3_V << TWAI_ACCEPTANCE_MASK_3_S) -#define TWAI_ACCEPTANCE_MASK_3_V 0x000000FF -#define TWAI_ACCEPTANCE_MASK_3_S 0 - -/* TWAI_DATA_8_REG register - * Data register 8 - */ - -#define TWAI_DATA_8_REG (DR_REG_TWAI_BASE + 0x60) - -/* TWAI_TX_BYTE_8 : WO; bitpos: [7:0]; default: 0; - * Stored the 8th byte information of the data to be transmitted under - * operating mode. - */ - -#define TWAI_TX_BYTE_8 0x000000FF -#define TWAI_TX_BYTE_8_M (TWAI_TX_BYTE_8_V << TWAI_TX_BYTE_8_S) -#define TWAI_TX_BYTE_8_V 0x000000FF -#define TWAI_TX_BYTE_8_S 0 - -/* TWAI_DATA_9_REG register - * Data register 9 - */ - -#define TWAI_DATA_9_REG (DR_REG_TWAI_BASE + 0x64) - -/* TWAI_TX_BYTE_9 : WO; bitpos: [7:0]; default: 0; - * Stored the 9th byte information of the data to be transmitted under - * operating mode. - */ - -#define TWAI_TX_BYTE_9 0x000000FF -#define TWAI_TX_BYTE_9_M (TWAI_TX_BYTE_9_V << TWAI_TX_BYTE_9_S) -#define TWAI_TX_BYTE_9_V 0x000000FF -#define TWAI_TX_BYTE_9_S 0 - -/* TWAI_DATA_10_REG register - * Data register 10 - */ - -#define TWAI_DATA_10_REG (DR_REG_TWAI_BASE + 0x68) - -/* TWAI_TX_BYTE_10 : WO; bitpos: [7:0]; default: 0; - * Stored the 10th byte information of the data to be transmitted under - * operating mode. - */ - -#define TWAI_TX_BYTE_10 0x000000FF -#define TWAI_TX_BYTE_10_M (TWAI_TX_BYTE_10_V << TWAI_TX_BYTE_10_S) -#define TWAI_TX_BYTE_10_V 0x000000FF -#define TWAI_TX_BYTE_10_S 0 - -/* TWAI_DATA_11_REG register - * Data register 11 - */ - -#define TWAI_DATA_11_REG (DR_REG_TWAI_BASE + 0x6c) - -/* TWAI_TX_BYTE_11 : WO; bitpos: [7:0]; default: 0; - * Stored the 11th byte information of the data to be transmitted under - * operating mode. - */ - -#define TWAI_TX_BYTE_11 0x000000FF -#define TWAI_TX_BYTE_11_M (TWAI_TX_BYTE_11_V << TWAI_TX_BYTE_11_S) -#define TWAI_TX_BYTE_11_V 0x000000FF -#define TWAI_TX_BYTE_11_S 0 - -/* TWAI_DATA_12_REG register - * Data register 12 - */ - -#define TWAI_DATA_12_REG (DR_REG_TWAI_BASE + 0x70) - -/* TWAI_TX_BYTE_12 : WO; bitpos: [7:0]; default: 0; - * Stored the 12th byte information of the data to be transmitted under - * operating mode. - */ - -#define TWAI_TX_BYTE_12 0x000000FF -#define TWAI_TX_BYTE_12_M (TWAI_TX_BYTE_12_V << TWAI_TX_BYTE_12_S) -#define TWAI_TX_BYTE_12_V 0x000000FF -#define TWAI_TX_BYTE_12_S 0 - -/* TWAI_RX_MESSAGE_CNT_REG register - * Receive Message Counter Register - */ - -#define TWAI_RX_MESSAGE_CNT_REG (DR_REG_TWAI_BASE + 0x74) - -/* TWAI_RX_MESSAGE_COUNTER : RO; bitpos: [6:0]; default: 0; - * This register reflects the number of messages available within the RX - * FIFO. - */ - -#define TWAI_RX_MESSAGE_COUNTER 0x0000007F -#define TWAI_RX_MESSAGE_COUNTER_M (TWAI_RX_MESSAGE_COUNTER_V << TWAI_RX_MESSAGE_COUNTER_S) -#define TWAI_RX_MESSAGE_COUNTER_V 0x0000007F -#define TWAI_RX_MESSAGE_COUNTER_S 0 - -/* TWAI_CLOCK_DIVIDER_REG register - * Clock Divider register - */ - -#define TWAI_CLOCK_DIVIDER_REG (DR_REG_TWAI_BASE + 0x7c) - -/* TWAI_CLOCK_OFF : RO | R/W; bitpos: [8]; default: 0; - * This bit can be configured under reset mode. 1: Disable the external - * CLKOUT pin; 0: Enable the external CLKOUT pin - */ - -#define TWAI_CLOCK_OFF (BIT(8)) -#define TWAI_CLOCK_OFF_M (TWAI_CLOCK_OFF_V << TWAI_CLOCK_OFF_S) -#define TWAI_CLOCK_OFF_V 0x00000001 -#define TWAI_CLOCK_OFF_S 8 - -/* TWAI_CD : R/W; bitpos: [7:0]; default: 0; - * These bits are used to configure frequency dividing coefficients of the - * external CLKOUT pin. - */ - -#define TWAI_CD 0x000000FF -#define TWAI_CD_M (TWAI_CD_V << TWAI_CD_S) -#define TWAI_CD_V 0x000000FF -#define TWAI_CD_S 0 - -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_TWAI_H */ diff --git a/arch/risc-v/src/esp32c3/hardware/regi2c_saradc.h b/arch/risc-v/src/esp32c3/hardware/regi2c_saradc.h deleted file mode 100644 index f4fe0881ab87c..0000000000000 --- a/arch/risc-v/src/esp32c3/hardware/regi2c_saradc.h +++ /dev/null @@ -1,51 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c3/hardware/regi2c_saradc.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_SARADC_H -#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_SARADC_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Register definitions for analog to calibrate initial code for getting a - * more precise voltage of SAR ADC. - */ - -#define I2C_ADC (0x69) -#define I2C_ADC_HOSTID (0) - -#define I2C_ADC1_ENCAL_GND (0x7) -#define I2C_ADC1_ENCAL_GND_MSB (0x5) -#define I2C_ADC1_ENCAL_GND_LSB (0x5) - -#define I2C_ADC1_INITVAL_L (0x0) -#define I2C_ADC1_INITVAL_L_MSB (0x7) -#define I2C_ADC1_INITVAL_L_LSB (0x0) - -#define I2C_ADC1_INITVAL_H (0x1) -#define I2C_ADC1_INITVAL_H_MSB (0x3) -#define I2C_ADC1_INITVAL_H_LSB (0x0) - -#define I2C_ADC1_DEF (0x2) -#define I2C_ADC1_DEF_MSB (0x6) -#define I2C_ADC1_DEF_LSB (0x4) - -#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_REGI2C_SARADC_H */ diff --git a/arch/risc-v/src/esp32c3/rom/esp32c3_spiflash.h b/arch/risc-v/src/esp32c3/rom/esp32c3_spiflash.h deleted file mode 100644 index 1c1c4fb9cbc1f..0000000000000 --- a/arch/risc-v/src/esp32c3/rom/esp32c3_spiflash.h +++ /dev/null @@ -1,1017 +0,0 @@ -/***************************************************************************** - * arch/risc-v/src/esp32c3/rom/esp32c3_spiflash.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - *****************************************************************************/ - -#ifndef _ROM_SPI_FLASH_H_ -#define _ROM_SPI_FLASH_H_ - -/***************************************************************************** - * Included Files - *****************************************************************************/ - -#include -#include - -#ifdef __cplusplus -extern "C" -{ -#endif - -/***************************************************************************** - * Pre-processor Definitions - *****************************************************************************/ - -#define PERIPHS_SPI_FLASH_CMD SPI_CMD_REG(1) -#define PERIPHS_SPI_FLASH_ADDR SPI_ADDR_REG(1) -#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL_REG(1) -#define PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1_REG(1) -#define PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS_REG(1) -#define PERIPHS_SPI_FLASH_USRREG SPI_USER_REG(1) -#define PERIPHS_SPI_FLASH_USRREG1 SPI_USER1_REG(1) -#define PERIPHS_SPI_FLASH_USRREG2 SPI_USER2_REG(1) -#define PERIPHS_SPI_FLASH_C0 SPI_W0_REG(1) -#define PERIPHS_SPI_FLASH_C1 SPI_W1_REG(1) -#define PERIPHS_SPI_FLASH_C2 SPI_W2_REG(1) -#define PERIPHS_SPI_FLASH_C3 SPI_W3_REG(1) -#define PERIPHS_SPI_FLASH_C4 SPI_W4_REG(1) -#define PERIPHS_SPI_FLASH_C5 SPI_W5_REG(1) -#define PERIPHS_SPI_FLASH_C6 SPI_W6_REG(1) -#define PERIPHS_SPI_FLASH_C7 SPI_W7_REG(1) -#define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC_REG(1) - -#define SPI0_R_QIO_DUMMY_CYCLELEN 3 -#define SPI0_R_QIO_ADDR_BITSLEN 31 -#define SPI0_R_FAST_DUMMY_CYCLELEN 7 -#define SPI0_R_DIO_DUMMY_CYCLELEN 1 -#define SPI0_R_DIO_ADDR_BITSLEN 27 -#define SPI0_R_FAST_ADDR_BITSLEN 23 -#define SPI0_R_SIO_ADDR_BITSLEN 23 - -#define SPI1_R_QIO_DUMMY_CYCLELEN 3 -#define SPI1_R_QIO_ADDR_BITSLEN 31 -#define SPI1_R_FAST_DUMMY_CYCLELEN 7 -#define SPI1_R_DIO_DUMMY_CYCLELEN 3 -#define SPI1_R_DIO_ADDR_BITSLEN 31 -#define SPI1_R_FAST_ADDR_BITSLEN 23 -#define SPI1_R_SIO_ADDR_BITSLEN 23 - -#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 - -#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_WRSR_2B - -/* SPI address register */ - -#define ESP_ROM_SPIFLASH_BYTES_LEN 24 -#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 -#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 64 -#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0x3f - -/* SPI status register */ - -#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 -#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 -#define ESP_ROM_SPIFLASH_BP0 BIT2 -#define ESP_ROM_SPIFLASH_BP1 BIT3 -#define ESP_ROM_SPIFLASH_BP2 BIT4 -#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|\ - ESP_ROM_SPIFLASH_BP1|\ - ESP_ROM_SPIFLASH_BP2) -#define ESP_ROM_SPIFLASH_QE BIT9 - -/* Extra dummy for flash read */ - -#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0 -#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M 1 -#define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M 2 - -#define FLASH_ID_GD25LQ32C 0xC86016 - -/***************************************************************************** - * Public Types - *****************************************************************************/ - -typedef enum -{ - ESP_ROM_SPIFLASH_QIO_MODE = 0, - ESP_ROM_SPIFLASH_QOUT_MODE, - ESP_ROM_SPIFLASH_DIO_MODE, - ESP_ROM_SPIFLASH_DOUT_MODE, - ESP_ROM_SPIFLASH_FASTRD_MODE, - ESP_ROM_SPIFLASH_SLOWRD_MODE -} esp_rom_spiflash_read_mode_t; - -typedef enum -{ - ESP_ROM_SPIFLASH_RESULT_OK, - ESP_ROM_SPIFLASH_RESULT_ERR, - ESP_ROM_SPIFLASH_RESULT_TIMEOUT -} esp_rom_spiflash_result_t; - -typedef struct -{ - uint32_t device_id; - uint32_t chip_size; /* chip size in bytes */ - uint32_t block_size; - uint32_t sector_size; - uint32_t page_size; - uint32_t status_mask; -} esp32c3_spiflash_chip_t; - -typedef struct -{ - uint8_t data_length; - uint8_t read_cmd0; - uint8_t read_cmd1; - uint8_t write_cmd; - uint16_t data_mask; - uint16_t data; -} esp_rom_spiflash_common_cmd_t; - -/* Global ROM spiflash data, as used by legacy SPI flash functions */ - -struct spiflash_legacy_data_s -{ - esp32c3_spiflash_chip_t chip; - uint8_t dummy_len_plus[3]; - uint8_t sig_matrix; -}; - -/* Structure holding SPI flash access critical sections management functions. - * - * Flash API uses two types of functions for flash access management: - * 1) Functions which prepare/restore flash cache and interrupts before - * calling appropriate ROM functions (SPIWrite, SPIRead and - * SPIEraseBlock): - * - 'start' function should disable flash cache and non-IRAM interrupts - * and is invoked before the call to one of ROM functions from - * "struct spiflash_guard_funcs_s". - * - 'end' function should restore state of flash cache and non-IRAM - * interrupts and is invoked after the call to one of ROM - * functions from "struct spiflash_guard_funcs_s". - * These two functions are not reentrant. - * 2) Functions which synchronizes access to internal data used by flash API. - * These functions are mostly intended to synchronize access to flash API - * internal data in multithreaded environment and use OS primitives: - * - 'op_lock' locks access to flash API internal data. - * - 'op_unlock' unlocks access to flash API internal data. - * These two functions are reentrant and can be used around the outside of - * multiple calls to 'start' & 'end', in order to create atomic multi-part - * flash operations. - * - * Different versions of the guarding functions should be used depending on - * the context of execution (with or without functional OS). In normal - * conditions when flash API is called from task the functions use OS - * primitives. - * When there is no OS at all or when it is not guaranteed that OS is - * functional (accessing flash from exception handler) these functions cannot - * use OS primitives or even does not need them (multithreaded access is - * not possible). - * - * Note: Structure and corresponding guard functions should not reside - * in flash. For example structure can be placed in DRAM and functions - * in IRAM sections. - */ - -struct spiflash_guard_funcs -{ - void (*start)(void); /* critical section start function */ - void (*end)(void); /* critical section end function */ - void (*op_lock)(void); /* flash access API lock function */ - void (*op_unlock)(void); /* flash access API unlock function */ - - /* checks flash write addresses */ - - bool (*address_is_safe)(size_t addr, size_t size); - - void (*yield)(void); /* yield to the OS during flash erase */ -}; - -/***************************************************************************** - * Public Function Prototypes - *****************************************************************************/ - -/***************************************************************************** - * Name: esp_rom_spiflash_fix_dummylen - * - * Description: - * Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High - * Speed. - * - * Please do not call this function in SDK. - * - * Input Parameters: - * uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write). - * - * uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, - * 1 for 80M. - * - * Returned Value: - * None - * - *****************************************************************************/ - -void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); - -/***************************************************************************** - * Name: esp_rom_spiflash_select_qiomode - * - * Description: - * Select SPI Flash to QIO mode when WP pad is read from Flash. - * - * Please do not call this function in SDK. - * - * Input Parameters: - * uint8_t wp_gpio_num: WP gpio number. - * - * uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping - * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, - * bit[23:18] spics0, bit[29:24] spihd - * - * Returned Value: - * None - *****************************************************************************/ - -void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, - uint32_t ishspi); - -/***************************************************************************** - * Name: esp_rom_spiflash_set_drvs - * - * Description: - * Set SPI Flash pad drivers. - * - * Please do not call this function in SDK. - * - * Input Parameters: - * uint8_t wp_gpio_num: WP gpio number. - * - * uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping - * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, - * bit[23:18] spics0, bit[29:24] spihd - * - * uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, - * drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid - * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp. - * Values usually read from flash by rom code, function - * usually callde by rom code. - * if value with bit(3) set, the value is valid, bit[2:0] - * is the real value. - * - * Returned Value: - * None - * - *****************************************************************************/ - -void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, - uint32_t ishspi, - uint8_t *drvs); - -/***************************************************************************** - * Name: esp_rom_spiflash_select_padsfunc - * - * Description: - * Select SPI Flash function for pads. - * - * Please do not call this function in SDK. - * - * Input Parameters: - * uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping - * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, - * bit[23:18] spics0, bit[29:24] spihd - * - * Returned Value: - * None - * - *****************************************************************************/ - -void esp_rom_spiflash_select_padsfunc(uint32_t ishspi); - -/***************************************************************************** - * Name: esp_rom_spiflash_attach - * - * Description: - * SPI Flash init, clock divisor is 4, use 1 line Slow read mode. - * - * Please do not call this function in SDK. - * - * Input Parameters: - * uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping - * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, - * bit[23:18] spics0, bit[29:24] spihd - * - * uint8_t legacy: In legacy mode, more SPI command is used in line. - * - * Returned Value: - * None - * - *****************************************************************************/ - -void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); - -/***************************************************************************** - * Name: esp_rom_spiflash_read_status - * - * Description: - * SPI Read Flash status register. We use CMD 0x05 (RDSR). - * - * Please do not call this function in SDK. - * - * Input Parameters: - * esp32c3_spiflash_chip_t *spi : The information for Flash, which is - * exported from ld file. - * - * uint32_t *status : The pointer to which to return the Flash status value. - * - * Returned Value: - * ESP_ROM_SPIFLASH_RESULT_OK : read OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : read error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. - * - *****************************************************************************/ - -esp_rom_spiflash_result_t -esp_rom_spiflash_read_status(esp32c3_spiflash_chip_t *spi, - uint32_t *status); - -/***************************************************************************** - * Name: esp32c3_spiflash_read_statushigh - * - * Description: - * SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). - * - * Please do not call this function in SDK. - * - * Input Parameters: - * esp32c3_spiflash_chip_t *spi : The information for Flash, which is - * exported from ld file. - * - * uint32_t *status : The pointer to which to return the Flash status value. - * - * Returned Value: - * ESP_ROM_SPIFLASH_RESULT_OK : read OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : read error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. - * - *****************************************************************************/ - -esp_rom_spiflash_result_t -esp32c3_spiflash_read_statushigh(esp32c3_spiflash_chip_t *spi, - uint32_t *status); - -/***************************************************************************** - * Name: esp32c3_spiflash_write_status - * - * Description: - * Write status to Falsh status register. - * - * Please do not call this function in SDK. - * - * Input Parameters: - * esp32c3_spiflash_chip_t *spi : The information for Flash, which is - * exported from ld file. - * - * uint32_t status_value : Value to . - * - * Returned Value: - * ESP_ROM_SPIFLASH_RESULT_OK : write OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : write error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. - * - *****************************************************************************/ - -esp_rom_spiflash_result_t -esp32c3_spiflash_write_status(esp32c3_spiflash_chip_t *spi, - uint32_t status_value); - -/***************************************************************************** - * Name: esp_rom_spiflash_read_user_cmd - * - * Description: - * Use a command to Read Flash status register. - * - * Please do not call this function in SDK. - * - * Input Parameters: - * esp32c3_spiflash_chip_t *spi : The information for Flash, which is - * exported from ld file. - * - * uint32_t*status : The pointer to which to return the Flash status value. - * - * Returned Value: - * ESP_ROM_SPIFLASH_RESULT_OK : read OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : read error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. - * - *****************************************************************************/ - -esp_rom_spiflash_result_t -esp_rom_spiflash_read_user_cmd(uint32_t *status, - uint8_t cmd); - -/***************************************************************************** - * Name: esp_rom_spiflash_config_readmode - * - * Description: - * Config SPI Flash read mode when init. - * - * Please do not call this function in SDK. - * - * Input Parameter: - * esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. - * - * This function does not try to set the QIO Enable bit in the status - * register, caller is responsible for this. - * - * Returned Value: - * ESP_ROM_SPIFLASH_RESULT_OK : config OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : config error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. - * - *****************************************************************************/ - -esp_rom_spiflash_result_t -esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode); - -/***************************************************************************** - * Name: esp_rom_spiflash_config_clk - * - * Description: - * Config SPI Flash clock divisor. - * - * Please do not call this function in SDK. - * - * Input Parameters: - * uint8_t freqdiv: clock divisor. - * - * uint8_t spi: 0 for SPI0, 1 for SPI1. - * - * Returned Value: - * ESP_ROM_SPIFLASH_RESULT_OK : config OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : config error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. - * - *****************************************************************************/ - -esp_rom_spiflash_result_t -esp_rom_spiflash_config_clk(uint8_t freqdiv, - uint8_t spi); - -/***************************************************************************** - * Name: esp_rom_spiflash_common_cmd - * - * Description: - * Send CommonCmd to Flash so that is can go into QIO mode, some Flash use - * different CMD. - * - * Please do not call this function in SDK. - * - * Input Paramater: - * esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a - * command. - * - * Returned Value: - * uint16_t 0 : do not send command any more. - * 1 : go to the next command. - * n > 1 : skip (n - 1) commands. - * - *****************************************************************************/ - -uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd); - -/***************************************************************************** - * Name: esp_rom_spiflash_unlock - * - * Description: - * Unlock SPI write protect. - * - * Please do not call this function in SDK. - * - * Input Value: - * None. - * - * Returned Value: - * ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. - * - *****************************************************************************/ - -esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); - -/***************************************************************************** - * Name: esp_rom_spiflash_lock - * - * Description: - * SPI write protect. - * - * Please do not call this function in SDK. - * - * Input Parameter: - * None. - * - * Returned Value: - * ESP_ROM_SPIFLASH_RESULT_OK : Lock OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Lock error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout. - * - *****************************************************************************/ - -esp_rom_spiflash_result_t esp_rom_spiflash_lock(void); - -/***************************************************************************** - * Name: esp_rom_spiflash_config_param - * - * Description: - * Update SPI Flash parameter. - * - * Please do not call this function in SDK. - * - * Input Parameters: - * uint32_t deviceId : Device ID read from SPI, the low 32 bit. - * - * uint32_t chip_size : The Flash size. - * - * uint32_t block_size : The Flash block size. - * - * uint32_t sector_size : The Flash sector size. - * - * uint32_t page_size : The Flash page size. - * - * uint32_t status_mask : The Mask used when read status from Flash - * (use single CMD). - * - * Returned Value: - * ESP_ROM_SPIFLASH_RESULT_OK : Update OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. - * - *****************************************************************************/ - -esp_rom_spiflash_result_t -esp_rom_spiflash_config_param(uint32_t deviceid, - uint32_t chip_size, - uint32_t block_size, - uint32_t sector_size, - uint32_t page_size, - uint32_t status_mask); - -/***************************************************************************** - * Name: esp_rom_spiflash_erase_chip - * - * Description: - * Erase whole flash chip. - * - * Please do not call this function in SDK. - * - * Input Parameter: - * None - * - * Returned Value: - * ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. - * - *****************************************************************************/ - -esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); - -/***************************************************************************** - * Name: esp_rom_spiflash_erase_block - * - * Description: - * Erase a 64KB block of flash - * Uses SPI flash command D8H. - * - * Please do not call this function in SDK. - * - * Input Parameter: - * uint32_t block_num : Which block to erase. - * - * Returned Value: - * ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. - * - *****************************************************************************/ - -esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num); - -/***************************************************************************** - * Name: esp_rom_spiflash_erase_sector - * - * Description: - * Erase a sector of flash. - * Uses SPI flash command 20H. - * - * Please do not call this function in SDK. - * - * Input Parameters: - * uint32_t sector_num : Which sector to erase. - * - * Returned Value: - * ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. - * - *****************************************************************************/ - -esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num); - -/***************************************************************************** - * Name: esp_rom_spiflash_erase_area - * - * Description: - * Erase some sectors. - * - * Please do not call this function in SDK. - * - * Input Parameters: - * uint32_t start_addr : Start addr to erase, should be sector aligned. - * - * uint32_t area_len : Length to erase, should be sector aligned. - * - * Returned Value: - * ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. - * - *****************************************************************************/ - -esp_rom_spiflash_result_t -esp_rom_spiflash_erase_area(uint32_t start_addr, - uint32_t area_len); - -/***************************************************************************** - * Name: esp_rom_spiflash_write - * - * Description: - * Write Data to Flash, you should Erase it yourself if need. - * - * Please do not call this function in SDK. - * - * Input Parameters: - * uint32_t dest_addr : Address to write, should be 4 bytes aligned. - * - * const uint32_t *src : The pointer to data which is to write. - * - * uint32_t len : Length to write, should be 4 bytes aligned. - * - * Returned Value: - * ESP_ROM_SPIFLASH_RESULT_OK : Write OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. - * - *****************************************************************************/ - -esp_rom_spiflash_result_t -esp_rom_spiflash_write(uint32_t dest_addr, - const uint32_t *src, - int32_t len); - -/***************************************************************************** - * Name: esp_rom_spiflash_read - * - * Description: - * Read Data from Flash, you should Erase it yourself if need. - * - * Please do not call this function in SDK. - * - * Input Values: - * uint32_t src_addr : Address to read, should be 4 bytes aligned. - * - * uint32_t *dest : The buf to read the data. - * - * uint32_t len : Length to read, should be 4 bytes aligned. - * - * Returned Value: - * ESP_ROM_SPIFLASH_RESULT_OK : Read OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. - * - *****************************************************************************/ - -esp_rom_spiflash_result_t -esp_rom_spiflash_read(uint32_t src_addr, - uint32_t *dest, - int32_t len); - -/***************************************************************************** - * Name: esp_rom_spiflash_write_encrypted_enable - * - * Description: - * SPI1 go into encrypto mode. - * - * Please do not call this function in SDK. - * - *****************************************************************************/ - -void esp_rom_spiflash_write_encrypted_enable(void); - -/***************************************************************************** - * Name: esp_rom_spiflash_prepare_encrypted_data - * - * Description: - * Prepare 32 Bytes data to encrpto writing, you should Erase it yourself - * if need. - * - * Please do not call this function in SDK. - * - * Input Parameters: - * uint32_t flash_addr : Address to write, should be 32 bytes aligned. - * - * uint32_t *data : The pointer to data which is to write. - * - * Returned Value: - * ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. - * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. - * - *****************************************************************************/ - -esp_rom_spiflash_result_t -esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, - uint32_t *data); - -/***************************************************************************** - * Name: esp_rom_spiflash_write_encrypted_disable - * - * Description: - * SPI1 go out of encrypto mode. - * - * Please do not call this function in SDK. - * - *****************************************************************************/ - -void esp_rom_spiflash_write_encrypted_disable(void); - -/***************************************************************************** - * Name: esp_rom_spiflash_write_encrypted - * - * Description: - * Write data to flash with transparent encryption. - * Sectors to be written should already be erased. - * Please do not call this function in SDK. - * - * Input Parameters: - * uint32_t flash_addr : Address to write, should be 32 byte aligned. - * - * uint32_t *data : The pointer to data to write. Note, this pointer must - * be 32 bit aligned and the content of the data will be - * modified by the encryption function. - * - * uint32_t len : Length to write, should be 32 bytes aligned. - * - * Returned Value: - * ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. - * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. - * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. - * - *****************************************************************************/ - -esp_rom_spiflash_result_t -esp_rom_spiflash_write_encrypted(uint32_t flash_addr, - uint32_t *data, - uint32_t len); - -/***************************************************************************** - * Name: esp_rom_spiflash_wait_idle - * - * Description: - * Wait until SPI flash write operation is complete - * - * Please do not call this function in SDK. - * - * Reads the Write In Progress bit of the SPI flash status register, - * repeats until this bit is zero (indicating write complete). - * - * Returned Value: - * ESP_ROM_SPIFLASH_RESULT_OK : Write is complete - * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. - * - *****************************************************************************/ - -esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp32c3_spiflash_chip_t - *spi); - -/***************************************************************************** - * Name: esp_rom_spiflash_select_qio_pins - * - * Description: - * Enable Quad I/O pin functions - * - * Please do not call this function in SDK. - * - * Sets the HD & WP pin functions for Quad I/O modes, based on the - * efuse SPI pin configuration. - * - * Input Parameters: - * wp_gpio_num - Number of the WP pin to reconfigure for quad I/O. - * spiconfig - Pin configuration, as returned from - * ets_efuse_get_spiconfig(). - * - If this parameter is 0, default SPI pins are used and - * wp_gpio_num parameter is ignored. - * - If this parameter is 1, default HSPI pins are used and - * wp_gpio_num parameter is ignored. - * - For other values, this parameter encodes the HD pin number - * and also the CLK pin number. CLK pin selection is used to - * determine if HSPI or SPI peripheral will be used (use HSPI - * if CLK pin is the HSPI clock pin, otherwise use SPI). - * Both HD & WP pins are configured via GPIO matrix to map to the selected - * peripheral. - * - *****************************************************************************/ - -void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, - uint32_t spiconfig); - -/***************************************************************************** - * Name: spi_flash_guard_set - * - * Description: - * Sets guard functions to access flash. - * - * Input Parameters: - * funcs - funcs pointer to structure holding flash access guard functions - * - * Returned Value: - * None - * - *****************************************************************************/ - -void spi_flash_guard_set(const struct spiflash_guard_funcs *funcs); - -/***************************************************************************** - * Name: spi_flash_write_encrypted - * - * Description: - * Write data encrypted to Flash. - * - * Flash encryption must be enabled for this function to work. - * - * Flash encryption must be enabled when calling this function. - * If flash encryption is disabled, the function returns - * ESP_ERR_INVALID_STATE. Use esp_flash_encryption_enabled() - * function to determine if flash encryption is enabled. - * - * Both dest_addr and size must be multiples of 16 bytes. For - * absolute best performance, both dest_addr and size arguments should - * be multiples of 32 bytes. - * - * Input Parameters: - * dest_addr - Destination address in Flash. Must be a multiple of 16 - * bytes. - * src - Pointer to the source buffer. - * size - Length of data, in bytes. Must be a multiple of 16 bytes. - * - * Returned Values: - * Zero (OK) is returned or a negative error. - * - *****************************************************************************/ - -int spi_flash_write_encrypted(uint32_t dest_addr, const void *src, - uint32_t size); - -/***************************************************************************** - * Name: spi_flash_write - * - * Description: - * - * Write data to Flash. - * - * Note: For fastest write performance, write a 4 byte aligned size at a - * 4 byte aligned offset in flash from a source buffer in DRAM. Varying - * any of these parameters will still work, but will be slower due to - * buffering. - * - * Writing more than 8KB at a time will be split into multiple - * write operations to avoid disrupting other tasks in the system. - * - * Parameters: - * dest_addr - Destination address in Flash. - * src - Pointer to the source buffer. - * size - Length of data, in bytes. - * - * Returned Values: - * Zero (OK) is returned or a negative error. - * - *****************************************************************************/ - -int spi_flash_write(uint32_t dest_addr, const void *src, uint32_t size); - -/***************************************************************************** - * Name: spi_flash_read - * - * Description: - * Read data from Flash. - * - * Note: For fastest read performance, all parameters should be - * 4 byte aligned. If source address and read size are not 4 byte - * aligned, read may be split into multiple flash operations. If - * destination buffer is not 4 byte aligned, a temporary buffer will - * be allocated on the stack. - * - * Reading more than 16KB of data at a time will be split - * into multiple reads to avoid disruption to other tasks in the - * system. Consider using spi_flash_mmap() to read large amounts - * of data. - * - * Parameters: - * src_addr - source address of the data in Flash. - * dest - pointer to the destination buffer - * size - length of data - * - * Returned Values: - * Zero (OK) is returned or a negative error. - * - *****************************************************************************/ - -int spi_flash_read(uint32_t src_addr, void *dest, uint32_t size); - -/***************************************************************************** - * Name: spi_flash_erase_sector - * - * Description: - * Erase the Flash sector. - * - * Parameters: - * sector - Sector number, the count starts at sector 0, 4KB per sector. - * - * Returned Values: esp_err_t - * Zero (OK) is returned or a negative error. - * - *****************************************************************************/ - -int spi_flash_erase_sector(uint32_t sector); - -/***************************************************************************** - * Name: spi_flash_erase_range - * - * Description: - * Erase a range of flash sectors - * - * Parameters: - * start_address - Address where erase operation has to start. - * Must be 4kB-aligned - * size - Size of erased range, in bytes. Must be divisible by - * 4kB. - * - * Returned Values: - * Zero (OK) is returned or a negative error. - * - *****************************************************************************/ - -int spi_flash_erase_range(uint32_t start_address, uint32_t size); - -/***************************************************************************** - * Name: spi_flash_cache_enabled - * - * Description: - * Check at runtime if flash cache is enabled on both CPUs. - * - * Returned Values: - * Return true if both CPUs have flash cache enabled, false otherwise. - * - *****************************************************************************/ - -bool spi_flash_cache_enabled(void); - -/***************************************************************************** - * Name: spi_flash_enable_cache - * - * Description: - * Re-enable cache for the core defined as cpuid parameter. - * - * Parameters: - * cpuid - core number to enable instruction cache for. - * - *****************************************************************************/ - -void spi_flash_enable_cache(uint32_t cpuid); - -/***************************************************************************** - * Public Data - *****************************************************************************/ - -extern const struct spiflash_legacy_data_s *rom_spiflash_legacy_data; - -#ifdef __cplusplus -} -#endif - -#endif /* _ROM_SPI_FLASH_H_ */ diff --git a/arch/risc-v/src/esp32c6/.gitignore b/arch/risc-v/src/esp32c6/.gitignore new file mode 100644 index 0000000000000..d40b86f3a0dce --- /dev/null +++ b/arch/risc-v/src/esp32c6/.gitignore @@ -0,0 +1,4 @@ +/bootloader +/esp-nuttx-bootloader +/*.zip +/esp-hal-3rdparty diff --git a/arch/risc-v/src/esp32c6/Kconfig b/arch/risc-v/src/esp32c6/Kconfig index 29c7298f573a8..e6c218ab0743b 100644 --- a/arch/risc-v/src/esp32c6/Kconfig +++ b/arch/risc-v/src/esp32c6/Kconfig @@ -14,106 +14,29 @@ choice config ARCH_CHIP_ESP32C6X bool "ESP32-C6" - select ESP32C6_ESP32C6XXX ---help--- ESP32 chip with a single RISC-V IMC core, no embedded Flash memory config ARCH_CHIP_ESP32C6FX4 bool "ESP32-C6Fx4" - select ESP32C6_ESP32C6XXX - select ESP32C6_FLASH_4M ---help--- ESP32 chip with a single RISC-V IMC core, 4 MB of in-package Flash memory config ARCH_CHIP_ESP32C6MINI1 bool "ESP32-C6-MINI-1" - select ESP32C6_ESP32C6XXX - select ESP32C6_FLASH_4M ---help--- Generic module with an embedded ESP32-C6Fx4 chip config ARCH_CHIP_ESP32C6WROOM1 bool "ESP32-C6-WROOM-1" - select ESP32C6_ESP32C6XXX - select ESP32C6_FLASH_4M ---help--- - Generic module with an embedded ESP32-C6 chip, 4 MB of Flash memory + Generic module with an embedded ESP32-C6 chip, 4/8 MB of Flash memory endchoice # ESP32-C6 Chip Selection comment "Selected ESP32-C6 chip without embedded Flash, an external Flash memory is required." depends on ARCH_CHIP_ESP32C6X -config ESP32C6_SINGLE_CPU - bool - default n - -config ESP32C6_DUAL_CPU - bool - default n - -config ESP32C6_FLASH_2M - bool - default n - -config ESP32C6_FLASH_4M - bool - default n - -config ESP32C6_FLASH_8M - bool - default n - -config ESP32C6_FLASH_16M - bool - default n - -config ESP32C6_ESP32C6XXX - bool - default n - select ESP32C6_SINGLE_CPU - -choice ESP32C6_CPU_FREQ - prompt "CPU frequency" - default ESP32C6_CPU_FREQ_160 - ---help--- - CPU frequency to be set on application startup. - -config ESP32C6_CPU_FREQ_80 - bool "80 MHz" - -config ESP32C6_CPU_FREQ_120 - bool "120 MHz" - -config ESP32C6_CPU_FREQ_160 - bool "160 MHz" - -endchoice # CPU frequency - -config ESP32C6_CPU_FREQ_MHZ - int - default 80 if ESP32C6_CPU_FREQ_80 - default 120 if ESP32C6_CPU_FREQ_120 - default 160 if ESP32C6_CPU_FREQ_160 - -menu "ESP32-C6 Peripheral Support" - -config ESP32C6_UART - bool - default n - -config ESP32C6_UART0 - bool "UART0" - default y - select ESP32C6_UART - select UART0_SERIALDRIVER - -config ESP32C6_UART1 - bool "UART1" - default n - select ESP32C6_UART - select UART1_SERIALDRIVER - -endmenu +source "arch/risc-v/src/common/espressif/Kconfig" endif # ARCH_CHIP_ESP32C6 diff --git a/arch/risc-v/src/esp32c6/Make.defs b/arch/risc-v/src/esp32c6/Make.defs index 68c6636f4d797..6469f02e57fc4 100644 --- a/arch/risc-v/src/esp32c6/Make.defs +++ b/arch/risc-v/src/esp32c6/Make.defs @@ -19,20 +19,13 @@ ############################################################################ include common/Make.defs +include common/espressif/Make.defs -# Specify our HEAD assembly file. This will be linked as -# the first object file, so it will appear at address 0 +# Wireless interfaces. -HEAD_ASRC = esp32c6_head.S +ifeq ($(CONFIG_ESPRESSIF_WIFI),y) +CHIP_CSRCS += esp_coex_adapter.c esp_wifi_adapter.c +EXTRA_LIBS += -lcore -lnet80211 -lpp +endif -CHIP_ASRCS = esp32c6_vectors.S - -# Specify our general Assembly files - -CMN_ASRCS := $(filter-out riscv_vectors.S,$(CMN_ASRCS)) - -# Specify our C code within this directory to be included - -CHIP_CSRCS = esp32c6_allocateheap.c esp32c6_start.c esp32c6_idle.c -CHIP_CSRCS += esp32c6_irq.c esp32c6_timerisr.c esp32c6_systemreset.c -CHIP_CSRCS += esp32c6_serial.c esp32c6_lowputc.c esp32c6_clockconfig.c +CFLAGS += ${DEFINE_PREFIX}_RETARGETABLE_LOCKING diff --git a/arch/risc-v/src/esp32c6/chip.h b/arch/risc-v/src/esp32c6/chip.h deleted file mode 100644 index 4d7b26c87a904..0000000000000 --- a/arch/risc-v/src/esp32c6/chip.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/chip.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C6_CHIP_H -#define __ARCH_RISCV_SRC_ESP32C6_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include "esp32c6_memorymap.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Section for exception handler. */ - -#define EXCEPTION_SECTION .iram1 - -#endif /* __ARCH_RISCV_SRC_ESP32C6_CHIP_H */ diff --git a/arch/risc-v/src/esp32c6/esp32c6.h b/arch/risc-v/src/esp32c6/esp32c6.h deleted file mode 100644 index 3ec614517ff22..0000000000000 --- a/arch/risc-v/src/esp32c6/esp32c6.h +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/esp32c6.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C6_ESP32C6_H -#define __ARCH_RISCV_SRC_ESP32C6_ESP32C6_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include - -#include - -#include "riscv_internal.h" -#include "chip.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#define setbits(bs, a) modifyreg32(a, 0, bs) -#define resetbits(bs, a) modifyreg32(a, bs, 0) - -#endif - -#endif /* __ARCH_RISCV_SRC_ESP32C6_ESP32C6_H */ diff --git a/arch/risc-v/src/esp32c6/esp32c6_allocateheap.c b/arch/risc-v/src/esp32c6/esp32c6_allocateheap.c deleted file mode 100644 index 222031fc6ee63..0000000000000 --- a/arch/risc-v/src/esp32c6/esp32c6_allocateheap.c +++ /dev/null @@ -1,92 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/esp32c6_allocateheap.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include -#include - -#include "esp32c6.h" -#include "hardware/esp32c6_rom_layout.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_allocate_heap - * - * Description: - * This function will be called to dynamically set aside the heap region. - * - * For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and - * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the - * size of the unprotected, user-space heap. - * - * If a protected kernel-space heap is provided, the kernel heap must be - * allocated (and protected) by an analogous up_allocate_kheap(). - * - ****************************************************************************/ - -void up_allocate_heap(void **heap_start, size_t *heap_size) -{ - /* These values come from the linker scripts (legacy_sections.ld and - * flat_memory.ld). - * Check boards/risc-v/esp32c6. - */ - - extern uint8_t _sheap[]; - extern const struct esp32c6_rom_layout_s *ets_rom_layout_p; - - board_autoled_on(LED_HEAPALLOCATE); - - *heap_start = _sheap; - *heap_size = ets_rom_layout_p->dram0_rtos_reserved_start - - (uintptr_t)_sheap; -} - -/**************************************************************************** - * Name: riscv_addregion - * - * Description: - * RAM may be added in non-contiguous chunks. This routine adds all chunks - * that may be used for heap. - * - ****************************************************************************/ - -#if CONFIG_MM_REGIONS > 1 -void riscv_addregion(void) -{ -} -#endif - diff --git a/arch/risc-v/src/esp32c6/esp32c6_attr.h b/arch/risc-v/src/esp32c6/esp32c6_attr.h deleted file mode 100644 index 27399b5026121..0000000000000 --- a/arch/risc-v/src/esp32c6/esp32c6_attr.h +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/esp32c6_attr.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C6_ESP32C6_ATTR_H -#define __ARCH_RISCV_SRC_ESP32C6_ESP32C6_ATTR_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Forces code into IRAM instead of flash */ - -#define IRAM_ATTR __attribute__((section(".iram1"))) - -/* Forces data into DRAM instead of flash */ - -#define DRAM_ATTR __attribute__((section(".dram1"))) - -/* Forces code into RTC fast memory */ - -#define RTC_IRAM_ATTR __attribute__((section(".rtc.text"))) - -/* Forces data into RTC slow memory - * Any variable marked with this attribute will keep its value - * during a deep sleep / wake cycle. - */ - -#define RTC_DATA_ATTR __attribute__((section(".rtc.data"))) - -/* Forces read-only data into RTC slow memory - * Makes constant data available to RTC wake stubs. - */ - -#define RTC_RODATA_ATTR __attribute__((section(".rtc.rodata"))) - -#endif /* __ARCH_RISCV_SRC_ESP32C6_ESP32C6_ATTR_H */ diff --git a/arch/risc-v/src/esp32c6/esp32c6_clockconfig.c b/arch/risc-v/src/esp32c6/esp32c6_clockconfig.c deleted file mode 100644 index 2dfa981890095..0000000000000 --- a/arch/risc-v/src/esp32c6/esp32c6_clockconfig.c +++ /dev/null @@ -1,281 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/esp32c6_clockconfig.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include "riscv_internal.h" -#include "hardware/esp32c6_soc.h" -#include "hardware/esp32c6_pcr.h" - -#include "esp32c6_attr.h" -#include "esp32c6_clockconfig.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -enum cpu_clksrc_e -{ - XTAL_CLK, - PLL_CLK, - FOSC_CLK -}; - -/**************************************************************************** - * ROM Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: ets_update_cpu_frequency - * - * Description: - * Set the real CPU ticks per us to the ets, so that ets_delay_us will be - * accurate. Call this function when CPU frequency is changed. - * - * Input Parameters: - * ticks_per_us - CPU ticks per us. - * - * Returned Value: - * None - * - ****************************************************************************/ - -extern void ets_update_cpu_frequency(uint32_t ticks_per_us); - -/**************************************************************************** - * Name: ets_get_cpu_frequency - * - * Description: - * Get the real CPU ticks per us to the ets. - * This function do not return real CPU ticks per us, just the record in - * ets. It can be used to check with the real CPU frequency. - * - * Input Parameters: - * None. - * - * Returned Value: - * CPU ticks per us record in ets. - * - ****************************************************************************/ - -extern uint32_t ets_get_cpu_frequency(void); - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c6_cpuclksrc - * - * Description: - * Select a clock source for CPU clock. - * - * Input Parameters: - * src - Any source from cpu_clksrc_e. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void esp32c6_cpuclksrc(enum cpu_clksrc_e src) -{ - uint32_t value; - value = VALUE_TO_FIELD(src, PCR_SOC_CLK_SEL); - modifyreg32(PCR_SYSCLK_CONF_REG, PCR_SOC_CLK_SEL_M, value); -} - -/**************************************************************************** - * Name: esp32c6_cpudiv - * - * Description: - * Select a divider for the CPU clk. - * NOTE: The divider is not necessarily the real divisor. See TRM for the - * equivalences. - * - * Input Parameters: - * divider - A value between 3 to 6. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void esp32c6_cpudiv(uint8_t divider) -{ - uint32_t value = (divider / 3) - 1; - bool force_120m = (divider == 4) ? 1 : 0; - value = VALUE_TO_FIELD(value, PCR_CPU_HS_DIV_NUM); - modifyreg32(PCR_CPU_FREQ_CONF_REG, PCR_CPU_HS_DIV_NUM_M, value); - value = VALUE_TO_FIELD(force_120m, PCR_CPU_HS_120M_FORCE); - modifyreg32(PCR_CPU_FREQ_CONF_REG, PCR_CPU_HS_120M_FORCE_M, value); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c6_update_cpu_freq - * - * Description: - * Set the real CPU ticks per us to the ets, so that ets_delay_us - * will be accurate. Call this function when CPU frequency is changed. - * - * Input Parameters: - * ticks_per_us - CPU ticks per us - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32c6_update_cpu_freq(uint32_t ticks_per_us) -{ - /* Update scale factors used by esp_rom_delay_us */ - - ets_update_cpu_frequency(ticks_per_us); -} - -/**************************************************************************** - * Name: esp32c6_set_cpu_freq - * - * Description: - * Switch to one of PLL-based frequencies. - * - * Input Parameters: - * cpu_freq_mhz - Target CPU frequency - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32c6_set_cpu_freq(int cpu_freq_mhz) -{ - switch (cpu_freq_mhz) - { - case 80: - /* 80 MHz is obtained from the 480 MHz PLL. - * In this case CPU_CLK = PLL_CLK / 6. Config the PLL as 480 MHz - * with a 6 divider and set the source clock as PLL_CLK. - */ - - esp32c6_cpudiv(6); - break; - - case 120: - /* 120 MHz is obtained from the 480 MHz PLL. - * In this case CPU_CLK = PLL_CLK / 4. Config the PLL as 480 MHz - * with a 4 divider and set the source clock as PLL_CLK. - */ - - esp32c6_cpudiv(4); - break; - - case 160: - /* 160 MHz is obtained from the 480 MHz PLL. - * In this case CPU_CLK = PLL_CLK / 3. Config the PLL as 480 MHz - * with a 3 divider and set the source clock as PLL_CLK. - */ - - esp32c6_cpudiv(3); - break; - - default: - - /* Unsupported clock config. */ - - return; - } - - esp32c6_cpuclksrc(PLL_CLK); - esp32c6_update_cpu_freq(cpu_freq_mhz); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c6_clockconfig - * - * Description: - * Called to initialize the ESP32-C6. This does whatever setup is needed to - * put the SoC in a usable state. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c6_clockconfig(void) -{ - /* Configure the CPU frequency */ - - esp32c6_set_cpu_freq(CONFIG_ESP32C6_CPU_FREQ_MHZ); -} - -/**************************************************************************** - * Name: esp_clk_cpu_freq - * - * Description: - * Get CPU frequency - * - * Input Parameters: - * None - * - * Returned Value: - * CPU frequency - * - ****************************************************************************/ - -int IRAM_ATTR esp_clk_cpu_freq(void) -{ - return (int)ets_get_cpu_frequency() * MHZ; -} - -/**************************************************************************** - * Name: esp_clk_apb_freq - * - * Description: - * Return current APB clock frequency. - * - * Input Parameters: - * None - * - * Returned Value: - * APB clock frequency, in Hz - * - ****************************************************************************/ - -int IRAM_ATTR esp_clk_apb_freq(void) -{ - return MIN(ets_get_cpu_frequency(), 80) * MHZ; -} diff --git a/arch/risc-v/src/esp32c6/esp32c6_clockconfig.h b/arch/risc-v/src/esp32c6/esp32c6_clockconfig.h deleted file mode 100644 index fb927e159ced9..0000000000000 --- a/arch/risc-v/src/esp32c6/esp32c6_clockconfig.h +++ /dev/null @@ -1,119 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/esp32c6_clockconfig.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C6_ESP32C6_CLOCKCONFIG_H -#define __ARCH_RISCV_SRC_ESP32C6_ESP32C6_CLOCKCONFIG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c6_update_cpu_freq - * - * Description: - * Set the real CPU ticks per us to the ets, so that ets_delay_us - * will be accurate. Call this function when CPU frequency is changed. - * - * Input Parameters: - * ticks_per_us - CPU ticks per us - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c6_update_cpu_freq(uint32_t ticks_per_us); - -/**************************************************************************** - * Name: esp32c6_set_cpu_freq - * - * Description: - * Switch to one of PLL-based frequencies. - * Current frequency can be XTAL or PLL. - * - * Input Parameters: - * cpu_freq_mhz - new CPU frequency - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c6_set_cpu_freq(int cpu_freq_mhz); - -/**************************************************************************** - * Name: esp32c6_clockconfig - * - * Description: - * Called to initialize the ESP32-C6. This does whatever setup is needed to - * put the SoC in a usable state. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c6_clockconfig(void); - -/**************************************************************************** - * Name: esp_clk_cpu_freq - * - * Description: - * Get the current CPU frequency. - * - * Input Parameters: - * None. - * - * Returned Value: - * CPU frequency in Hz. - * - ****************************************************************************/ - -int esp_clk_cpu_freq(void); - -/**************************************************************************** - * Name: esp_clk_apb_freq - * - * Description: - * Return current APB clock frequency. - * - * Input Parameters: - * None. - * - * Returned Value: - * APB clock frequency in Hz. - * - ****************************************************************************/ - -int esp_clk_apb_freq(void); - -#endif /* __ARCH_RISCV_SRC_ESP32C6_ESP32C6_CLOCKCONFIG_H */ diff --git a/arch/risc-v/src/esp32c6/esp32c6_config.h b/arch/risc-v/src/esp32c6/esp32c6_config.h deleted file mode 100644 index 3524e4f7270f6..0000000000000 --- a/arch/risc-v/src/esp32c6/esp32c6_config.h +++ /dev/null @@ -1,65 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/esp32c6_config.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C6_ESP32C6_CONFIG_H -#define __ARCH_RISCV_SRC_ESP32C6_ESP32C6_CONFIG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* UARTs ********************************************************************/ - -/* Are any UARTs enabled? */ - -#undef HAVE_UART_DEVICE -#if defined(CONFIG_ESP32C6_UART0) || defined(CONFIG_ESP32C6_UART1) -# define HAVE_UART_DEVICE 1 /* Flag to indicate a UART has been selected */ -#endif - -/* Serial Console ***********************************************************/ - -/* Is there a serial console? There should be no more than one defined. It - * could be on any UARTn. n E {0,1} - */ - -#undef HAVE_SERIAL_CONSOLE -#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_ESP32C6_UART0) -# undef CONFIG_UART1_SERIAL_CONSOLE -# define HAVE_SERIAL_CONSOLE 1 -# define CONSOLE_UART 1 -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_ESP32C6_UART1) -# undef CONFIG_UART0_SERIAL_CONSOLE -# define HAVE_SERIAL_CONSOLE 1 -# define CONSOLE_UART 1 -#else -# undef CONFIG_UART0_SERIAL_CONSOLE -# undef CONFIG_UART1_SERIAL_CONSOLE -#endif - -#endif /* __ARCH_XTENSA_SRC_ESP32C6_ESP32C6_CONFIG_H */ diff --git a/arch/risc-v/src/esp32c6/esp32c6_head.S b/arch/risc-v/src/esp32c6/esp32c6_head.S deleted file mode 100644 index c3f61cd052747..0000000000000 --- a/arch/risc-v/src/esp32c6/esp32c6_head.S +++ /dev/null @@ -1,77 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/esp32c6_head.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "chip.h" - -/**************************************************************************** - * Public Symbols - ****************************************************************************/ - - .global __start - -/**************************************************************************** - * Section: .text - ****************************************************************************/ - - .section .text - -/**************************************************************************** - * Name: __start - ****************************************************************************/ - -__start: - .option push - .option norelax - - /* Set stack pointer to the idle thread stack */ - - lui sp, %hi(ESP32C6_IDLESTACK_TOP) - addi sp, sp, %lo(ESP32C6_IDLESTACK_TOP) - - /* Set gp pointer */ - - la gp, __global_pointer$ - - /* Disable all interrupts (i.e. timer, external) in mstatus */ - - csrw mstatus, zero - - .option pop - - /* Initialize the Machine Trap-Vector */ - - lui t0, %hi(_vector_table) - addi t0, t0, %lo(_vector_table) - csrw mtvec, t0 - - /* Jump to __esp32c6_start */ - - jal x1, __esp32c6_start - - /* We shouldn't return from __esp32c6_start */ - - ret diff --git a/arch/risc-v/src/esp32c6/esp32c6_idle.c b/arch/risc-v/src/esp32c6/esp32c6_idle.c deleted file mode 100644 index ce3264b2f342a..0000000000000 --- a/arch/risc-v/src/esp32c6/esp32c6_idle.c +++ /dev/null @@ -1,73 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/esp32c6_idle.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include - -#include "esp32c6.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_idle - * - * Description: - * up_idle() is the logic that will be executed when their is no other - * ready-to-run task. This is processor idle time and will continue until - * some interrupt occurs to cause a context switch from the idle task. - * - * Processing in this state may be processor-specific. e.g., this is where - * power management operations might be performed. - * - ****************************************************************************/ - -void up_idle(void) -{ -#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) - /* If the system is idle and there are no timer interrupts, then process - * "fake" timer interrupts. Hopefully, something will wake up. - */ - - nxsched_process_timer(); -#else - /* This would be an appropriate place to put some MCU-specific logic to - * sleep in a reduced power mode until an interrupt occurs to save power - */ - - asm("WFI"); - -#endif -} diff --git a/arch/risc-v/src/esp32c6/esp32c6_irq.c b/arch/risc-v/src/esp32c6/esp32c6_irq.c deleted file mode 100644 index d02e0becea8a0..0000000000000 --- a/arch/risc-v/src/esp32c6/esp32c6_irq.c +++ /dev/null @@ -1,592 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/esp32c6_irq.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "riscv_internal.h" - -#include "esp32c6.h" -#include "esp32c6_attr.h" - -#include "esp32c6_irq.h" -#include "hardware/esp32c6_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ESP32C6_DEFAULT_INT_THRESHOLD 1 - -#define IRQ_UNMAPPED 0xff - -/* CPU interrupts to peripheral mapping: - * - * Encoding: EPPPPPP - * E: CPU interrupt status (0 = Disabled, 1 = Enabled). - * P: Attached peripheral. - */ - -#define CPUINT_UNASSIGNED 0x7f -#define CPUINT_GETEN(m) (((m) & 0x80) >> 0x07) -#define CPUINT_GETIRQ(m) ((m) & 0x7f) -#define CPUINT_ASSIGN(c) (((c) & 0x7f) | 0x80) -#define CPUINT_DISABLE(m) ((m) & 0x7f) -#define CPUINT_ENABLE(m) ((m) | 0x80) - -/* CPU interrupts can be detached from any peripheral source by setting the - * map register to an internal CPU interrupt (1~31). - */ - -#define NO_CPUINT 0 - -/* Priority range is 1-15 */ - -#define ESP32C6_MIN_PRIORITY 1 -#define ESP32C6_MAX_PRIORITY 15 -#define ESP32C6_PRIO_INDEX(p) ((p) - ESP32C6_MIN_PRIORITY) - -#define ESP32C6_WIFI_RESERVE_INT (BIT(1)) -#define ESP32C6_BLE_RESERVE_INT (BIT(5) | BIT(8)) -#define ESP32C6_DISABLED_INT (BIT(6)) -#define ESP32C6_INVALID_INT (BIT(0) | BIT(3) | BIT(4) | BIT(7)) - -#define ESP32C6_RESERVE_INT (ESP32C6_WIFI_RESERVE_INT | \ - ESP32C6_BLE_RESERVE_INT | \ - ESP32C6_DISABLED_INT | \ - ESP32C6_INVALID_INT) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */ - -static uint8_t g_cpu_intmap[ESP32C6_NCPUINTS]; - -static volatile uint8_t g_irqmap[NR_IRQS]; - -/* Bitsets for free, unallocated CPU interrupts available to peripheral - * devices. - */ - -static uint32_t g_cpu_freeints = ESP32C6_CPUINT_PERIPHSET & - (~ESP32C6_RESERVE_INT); - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c6_getcpuint - * - * Description: - * Get a free CPU interrupt for a peripheral device. This function will - * not ignore all of the pre-allocated CPU interrupts for internal - * devices. - * - * Returned Value: - * On success, a CPU interrupt number is returned. - * A negated errno is returned on failure. - * - ****************************************************************************/ - -static int esp32c6_getcpuint(void) -{ - uint32_t bitmask; - uint32_t intset; - int cpuint = 0; - int ret = -ENOMEM; - - /* Check if there are CPU interrupts with the requested properties - * available. - */ - - intset = g_cpu_freeints; - if (intset != 0) - { - /* Skip over initial unavailable CPU interrupts quickly in groups - * of 8 interrupt. - */ - - for (cpuint = 0, bitmask = 0xff; - cpuint <= ESP32C6_CPUINT_MAX && (intset & bitmask) == 0; - cpuint += 8, bitmask <<= 8); - - /* Search for an unallocated CPU interrupt number in the remaining - * intset. - */ - - for (; cpuint <= ESP32C6_CPUINT_MAX; cpuint++) - { - /* If the bit corresponding to the CPU interrupt is '1', then - * that CPU interrupt is available. - */ - - bitmask = 1ul << cpuint; - if ((intset & bitmask) != 0) - { - /* Got it! */ - - g_cpu_freeints &= ~bitmask; - ret = cpuint; - break; - } - } - } - - /* Enable the CPU interrupt now. The interrupt is still not attached - * to any peripheral and thus has no effect. - */ - - if (ret >= 0) - { - setbits(1 << cpuint, PLIC_MXINT_ENABLE_REG); - } - - return cpuint; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_irqinitialize - ****************************************************************************/ - -void up_irqinitialize(void) -{ - int periphid; - - /* Indicate that no peripheral interrupts are assigned to CPU interrupts */ - - for (int i = 0; i < NR_IRQS; i++) - { - g_irqmap[i] = IRQ_UNMAPPED; - } - - /* Clear all peripheral interrupts from "bootloader" */ - - for (periphid = 0; periphid < ESP32C6_NPERIPHERALS; periphid++) - { - putreg32(0, DR_REG_INTERRUPT_MATRIX_BASE + periphid * 4); - } - - /* Set CPU interrupt threshold level */ - - putreg32(ESP32C6_DEFAULT_INT_THRESHOLD, PLIC_MXINT_THRESH_REG); - - /* Attach the common interrupt handler */ - - riscv_exception_attach(); - -#ifndef CONFIG_SUPPRESS_INTERRUPTS - - /* And finally, enable interrupts */ - - up_irq_enable(); -#endif -} - -/**************************************************************************** - * Name: up_enable_irq - * - * Description: - * Enable the interrupt specified by 'irq' - * - ****************************************************************************/ - -void up_enable_irq(int irq) -{ - int cpuint = g_irqmap[irq]; - irqstate_t irqstate; - - irqinfo("irq=%d | cpuint=%d\n", irq, cpuint); - - DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32C6_CPUINT_MAX); - - irqstate = enter_critical_section(); - setbits(1 << cpuint, PLIC_MXINT_ENABLE_REG); - SET_CSR(mie, 1 << cpuint); - leave_critical_section(irqstate); -} - -/**************************************************************************** - * Name: up_disable_irq - * - * Description: - * Disable the interrupt specified by 'irq' - * - ****************************************************************************/ - -void up_disable_irq(int irq) -{ - int cpuint = g_irqmap[irq]; - - irqinfo("irq=%d | cpuint=%d \n", irq, cpuint); - - DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32C6_CPUINT_MAX); - - if (cpuint == IRQ_UNMAPPED) - { - /* This interrupt is already disabled. */ - - return; - } - else - { - irqstate_t irqstate; - - g_cpu_intmap[cpuint] = CPUINT_DISABLE(g_cpu_intmap[cpuint]); - - irqstate = enter_critical_section(); - CLEAR_CSR(mie, 1 << cpuint); - resetbits(1 << cpuint, PLIC_MXINT_ENABLE_REG); - leave_critical_section(irqstate); - } -} - -/**************************************************************************** - * Name: esp32c6_free_cpuint - * - * Description: - * Free CPU interrupt. - * - * Input Parameters: - * periphid - Peripheral ID. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c6_free_cpuint(uint8_t periphid) -{ - irqstate_t irqstate; - uint8_t cpuint; - - DEBUGASSERT(periphid < ESP32C6_NPERIPHERALS); - - irqstate = enter_critical_section(); - - /* Get the CPU interrupt ID mapped to this peripheral. */ - - cpuint = getreg32(DR_REG_INTERRUPT_MATRIX_BASE + periphid * 4) & 0x1f; - - irqinfo("INFO: irq[%" PRIu8 "]=%" PRIu8 "\n", periphid, cpuint); - - if (cpuint != 0) - { - /* Undo the allocation process: - * 1. Unmap the peripheral from the CPU interrupt ID. - * 2. Reset the interrupt type. - * 3. Reset the interrupt priority. - * 4. Clear the CPU interrupt. - */ - - DEBUGASSERT(g_cpu_intmap[cpuint] != CPUINT_UNASSIGNED); - - g_cpu_intmap[cpuint] = CPUINT_UNASSIGNED; - putreg32(0, DR_REG_INTERRUPT_MATRIX_BASE + periphid * 4); - resetbits(1 << cpuint, PLIC_MXINT_TYPE_REG); - putreg32(0, PLIC_MXINT0_PRI_REG + cpuint * 4); - resetbits(1 << cpuint, PLIC_MXINT_ENABLE_REG); - } - - leave_critical_section(irqstate); -} - -/**************************************************************************** - * Name: esp32c6_cpuint_initialize - * - * Description: - * Initialize CPU interrupts - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. - * - ****************************************************************************/ - -int esp32c6_cpuint_initialize(void) -{ - /* Disable all CPU interrupts on this CPU */ - - for (int i = 0; i < ESP32C6_NCPUINTS; i++) - { - putreg32(0, PLIC_MXINT0_PRI_REG + i * 4); - } - - /* Detach all interrupts from peripheral sources */ - - for (int i = 0; i < ESP32C6_NPERIPHERALS; i++) - { - putreg32(0, DR_REG_INTERRUPT_MATRIX_BASE + i * 4); - } - - /* Indicate that no peripheral interrupts are assigned to CPU interrupts */ - - memset(g_cpu_intmap, CPUINT_UNASSIGNED, ESP32C6_NCPUINTS); - - return OK; -} - -/**************************************************************************** - * Name: esp32c6_bind_irq - * - * Description: - * Bind IRQ and resource with given parameters. - * - * Input Parameters: - * cpuint - CPU interrupt ID - * periphid - Peripheral ID - * prio - Interrupt priority - * flags - Interrupt flags - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c6_bind_irq(uint8_t cpuint, uint8_t periphid, uint8_t prio, - uint32_t flags) -{ - /* Disable the CPU interrupt. */ - - resetbits(1 << cpuint, PLIC_MXINT_ENABLE_REG); - - /* Set the interrupt priority. */ - - putreg32(prio, PLIC_MXINT0_PRI_REG + cpuint * 4); - - /* Set the interrupt type (Edge or Level). */ - - if (flags & ESP32C6_INT_EDGE) - { - setbits(1 << cpuint, PLIC_MXINT_TYPE_REG); - } - else - { - resetbits(1 << cpuint, PLIC_MXINT_TYPE_REG); - } - - /* Map the CPU interrupt ID to the peripheral. */ - - putreg32(cpuint, DR_REG_INTERRUPT_MATRIX_BASE + periphid * 4); -} - -/**************************************************************************** - * Name: esp32c6_setup_irq - * - * Description: - * This function sets up the IRQ. It allocates a CPU interrupt of the given - * priority and type and attaches it to the given peripheral. - * - * Input Parameters: - * periphid - The peripheral number from irq.h to be assigned to - * a CPU interrupt. - * priority - Interrupt's priority (1 - 15). - * type - Interrupt's type (level or edge). - * - * Returned Value: - * The allocated CPU interrupt on success, a negated errno value on - * failure. - * - ****************************************************************************/ - -int esp32c6_setup_irq(int periphid, int priority, int type) -{ - irqstate_t irqstate; - int irq; - int cpuint; - - irqinfo("periphid = %d\n", periphid); - - irqstate = enter_critical_section(); - - /* Setting up an IRQ includes the following steps: - * 1. Allocate a CPU interrupt. - * 2. Attach that CPU interrupt to the peripheral. - * 3. Map the CPU interrupt to the IRQ to ease searching later. - */ - - cpuint = esp32c6_getcpuint(); - if (cpuint < 0) - { - irqerr("Unable to allocate CPU interrupt for priority=%d and type=%d", - priority, type); - leave_critical_section(irqstate); - - return cpuint; - } - - irq = ESP32C6_PERIPH2IRQ(periphid); - - DEBUGASSERT(periphid >= 0 && periphid < ESP32C6_NPERIPHERALS); - DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32C6_CPUINT_MAX); - DEBUGASSERT(g_cpu_intmap[cpuint] == CPUINT_UNASSIGNED); - - g_cpu_intmap[cpuint] = CPUINT_ASSIGN(periphid + ESP32C6_IRQ_FIRSTPERIPH); - g_irqmap[irq] = cpuint; - - esp32c6_bind_irq(cpuint, periphid, priority, type); - - leave_critical_section(irqstate); - - return cpuint; -} - -/**************************************************************************** - * Name: esp32c6_teardown_irq - * - * Description: - * This function undoes the operations done by esp32c6_setup_irq. - * It detaches a peripheral interrupt from a CPU interrupt and frees the - * CPU interrupt. - * - * Input Parameters: - * periphid - The peripheral number from irq.h to be detached from the - * CPU interrupt. - * cpuint - The CPU interrupt from which the peripheral interrupt will - * be detached. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32c6_teardown_irq(int periphid, int cpuint) -{ - irqstate_t irqstate; - uintptr_t regaddr; - int irq; - - irqstate = enter_critical_section(); - - /* Tearing down an IRQ includes the following steps: - * 1. Free the previously allocated CPU interrupt. - * 2. Detach the interrupt from the peripheral. - * 3. Unmap the IRQ from the IRQ-to-cpuint map. - */ - - esp32c6_free_cpuint(cpuint); - - irq = ESP32C6_PERIPH2IRQ(periphid); - - DEBUGASSERT(periphid >= 0 && periphid < ESP32C6_NPERIPHERALS); - - DEBUGASSERT(g_cpu_intmap[cpuint] != CPUINT_UNASSIGNED); - g_cpu_intmap[cpuint] = CPUINT_UNASSIGNED; - g_irqmap[irq] = IRQ_UNMAPPED; - regaddr = CORE_MAP_REGADDR(periphid); - - putreg32(NO_CPUINT, regaddr); - - leave_critical_section(irqstate); -} - -/**************************************************************************** - * Name: riscv_dispatch_irq - * - * Description: - * Process interrupt and its callback function. - * - * Input Parameters: - * mcause - RISC-V "mcause" register. - * regs - Saved registers reference. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -IRAM_ATTR uintptr_t *riscv_dispatch_irq(uintptr_t mcause, uintptr_t *regs) -{ - int irq; - uint8_t cpuint = mcause & RISCV_IRQ_MASK; - bool is_irq = (RISCV_IRQ_BIT & mcause) != 0; - - irqinfo("INFO: mcause=%08" PRIXPTR "\n", mcause); - - DEBUGASSERT(cpuint <= ESP32C6_CPUINT_MAX); - - irqinfo("INFO: cpuint=%" PRIu8 "\n", cpuint); - - if (is_irq) - { - /* Clear edge interrupts. */ - - putreg32(1 << cpuint, PLIC_MXINT_CLEAR_REG); - irq = CPUINT_GETIRQ(g_cpu_intmap[cpuint]); - } - else - { - /* It's exception */ - - irq = mcause; - } - - irqinfo("INFO: IRQ=%d\n", irq); - - regs = riscv_doirq(irq, regs); - - /* Toggle the bit back to zero. */ - - if (is_irq) - { - putreg32(0, PLIC_MXINT_CLEAR_REG); - } - - return regs; -} - -/**************************************************************************** - * Name: up_irq_enable - * - * Description: - * Return the current interrupt state and enable interrupts - * - ****************************************************************************/ - -irqstate_t up_irq_enable(void) -{ - irqstate_t flags; - - /* Read mstatus & set machine interrupt enable (MIE) in mstatus */ - - flags = READ_AND_SET_CSR(mstatus, MSTATUS_MIE); - return flags; -} diff --git a/arch/risc-v/src/esp32c6/esp32c6_irq.h b/arch/risc-v/src/esp32c6/esp32c6_irq.h deleted file mode 100644 index 5a2462aa1b9a7..0000000000000 --- a/arch/risc-v/src/esp32c6/esp32c6_irq.h +++ /dev/null @@ -1,146 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/esp32c6_irq.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C6_ESP32C6_IRQ_H -#define __ARCH_RISCV_SRC_ESP32C6_ESP32C6_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* CPU interrupt types. */ - -#define ESP32C6_INT_LEVEL (0 << 0) -#define ESP32C6_INT_EDGE (1 << 0) - -#define ESP32C6_INT_PRIO_MIN 1 -#define ESP32C6_INT_PRIO_MAX 7 - -#define ESP32C6_INT_PRIO_DEF 1 - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c6_bind_irq - * - * Description: - * Bind IRQ and resource with given parameters. - * - * Input Parameters: - * cpuint - CPU interrupt ID - * periphid - Peripheral ID - * prio - Interrupt priority - * flags - Interrupt flags - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32c6_bind_irq(uint8_t cpuint, uint8_t periphid, uint8_t prio, - uint32_t flags); - -/**************************************************************************** - * Name: esp32c6_cpuint_initialize - * - * Description: - * Initialize CPU interrupts - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. - * - ****************************************************************************/ - -int esp32c6_cpuint_initialize(void); - -/**************************************************************************** - * Name: esp32c6_setup_irq - * - * Description: - * This function sets up the IRQ. It allocates a CPU interrupt of the given - * priority and type and attaches it to the given peripheral. - * - * Input Parameters: - * periphid - The peripheral number from irq.h to be assigned to - * a CPU interrupt. - * priority - Interrupt's priority (1 - 5). - * type - Interrupt's type (level or edge). - * - * Returned Value: - * The allocated CPU interrupt on success, a negated errno value on - * failure. - * - ****************************************************************************/ - -int esp32c6_setup_irq(int periphid, int priority, int type); - -/**************************************************************************** - * Name: esp32c6_teardown_irq - * - * Description: - * This function undoes the operations done by esp32c6_setup_irq. - * It detaches a peripheral interrupt from a CPU interrupt and frees the - * CPU interrupt. - * - * Input Parameters: - * periphid - The peripheral number from irq.h to be detached from the - * CPU interrupt. - * cpuint - The CPU interrupt from which the peripheral interrupt will - * be detached. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32c6_teardown_irq(int periphid, int cpuint); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32C6_ESP32C6_IRQ_H */ diff --git a/arch/risc-v/src/esp32c6/esp32c6_lowputc.c b/arch/risc-v/src/esp32c6/esp32c6_lowputc.c deleted file mode 100644 index 88ca7a56c7910..0000000000000 --- a/arch/risc-v/src/esp32c6/esp32c6_lowputc.c +++ /dev/null @@ -1,510 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/esp32c6_lowputc.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "riscv_internal.h" -#include "chip.h" - -#include "hardware/esp32c6_uart.h" -#include "esp32c6_lowputc.h" -#include "esp32c6_config.h" -#include "hardware/esp32c6_soc.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef HAVE_UART_DEVICE - -#ifdef CONFIG_ESP32C6_UART0 - -struct esp32c6_uart_s g_uart0_config = -{ - .base = REG_UART_BASE(0), - .periph = ESP32C6_UART0_PERIPH, - .id = 0, - .irq = ESP32C6_IRQ_UART0, - .baud = CONFIG_UART0_BAUD, - .bits = CONFIG_UART0_BITS, - .parity = CONFIG_UART0_PARITY, - .stop_b2 = CONFIG_UART0_2STOP, - .int_pri = 1 -}; - -#endif /* CONFIG_ESP32C6_UART0 */ - -#ifdef CONFIG_ESP32C6_UART1 - -struct esp32c6_uart_s g_uart1_config = -{ - .base = REG_UART_BASE(1), - .periph = ESP32C6_UART1_PERIPH, - .id = 1, - .irq = ESP32C6_IRQ_UART1, - .baud = CONFIG_UART1_BAUD, - .bits = CONFIG_UART1_BITS, - .parity = CONFIG_UART1_PARITY, - .stop_b2 = CONFIG_UART1_2STOP, - .int_pri = 1 -}; - -#endif /* CONFIG_ESP32C6_UART1 */ - -#endif /* HAVE_UART_DEVICE */ - -#if 0 -#ifdef HAVE_SERIAL_CONSOLE -# if defined(CONFIG_UART0_SERIAL_CONSOLE) - -static struct esp32c6_uart_s g_console_config = -{ - .base = REG_UART_BASE(0), - .id = 0, - .irq = -1, /* TODO */ - .baud = CONFIG_UART0_BAUD, - .bits = CONFIG_UART0_BITS, - .parity = CONFIG_UART0_PARITY, - .stop_b2 = CONFIG_UART0_2STOP, - .int_pri = 1 -}; - -# elif defined(CONFIG_UART1_SERIAL_CONSOLE) - -static struct esp32c6_uart_s g_uart1_config = -{ - .base = REG_UART_BASE(1), - .id = 1, - .irq = -1, /* TODO */ - .baud = CONFIG_UART1_BAUD, - .bits = CONFIG_UART1_BITS, - .parity = CONFIG_UART1_PARITY, - .stop_b2 = CONFIG_UART1_2STOP, - .int_pri = 1 -}; -# endif /* CONFIG_UART0_SERIAL_CONSOLE */ -#endif /* HAVE_SERIAL_CONSOLE */ -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c6_lowputc_reset_core - * Reset both TX and RX core - ****************************************************************************/ - -void esp32c6_lowputc_reset_core(const struct esp32c6_uart_s *conf) -{ - uint32_t set_bit = 1 << UART_RST_CORE_S; - modifyreg32(UART_CLK_CONF_REG(conf->id), UART_RST_CORE_M, set_bit); - modifyreg32(UART_CLK_CONF_REG(conf->id), UART_RST_CORE_M, 0); -} - -/**************************************************************************** - * Name: esp32c6_lowputc_enable_sclk - * Enable clock for whole core - ****************************************************************************/ - -void esp32c6_lowputc_enable_sclk(const struct esp32c6_uart_s *conf) -{ - modifyreg32(UART_CLK_CONF_REG(conf->id), UART_SCLK_EN_M, - 1 << UART_SCLK_EN_S); - modifyreg32(UART_CLK_CONF_REG(conf->id), UART_RX_SCLK_EN_M, - 1 << UART_RX_SCLK_EN_S); - modifyreg32(UART_CLK_CONF_REG(conf->id), UART_TX_SCLK_EN_M, - 1 << UART_TX_SCLK_EN_S); -} - -/**************************************************************************** - * Name: esp32c6_lowputc_disable_sclk - * Disable clock for whole core - ****************************************************************************/ - -void esp32c6_lowputc_disable_sclk(const struct esp32c6_uart_s *conf) -{ - modifyreg32(UART_CLK_CONF_REG(conf->id), UART_SCLK_EN_M, 0); - modifyreg32(UART_CLK_CONF_REG(conf->id), UART_RX_SCLK_EN_M, 0); - modifyreg32(UART_CLK_CONF_REG(conf->id), UART_TX_SCLK_EN_M, 0); -} - -/**************************************************************************** - * Name: esp32c6_lowputc_set_sclk - * Set a source clock for UART - * APB_CLK = 1 80 MHz - * CLK_8 = 2 8 MHz - * XTAL_CLK = 3 - ****************************************************************************/ - -void esp32c6_lowputc_set_sclk(const struct esp32c6_uart_s *conf, enum - uart_sclk source) -{ - uint32_t clk = (uint32_t)source << UART_SCLK_SEL_S; - modifyreg32(UART_CLK_CONF_REG(conf->id), UART_SCLK_SEL_M, clk); -} - -/**************************************************************************** - * Name: esp32c6_lowputc_get_sclk - * Get the source clock for UART - ****************************************************************************/ - -uint32_t esp32c6_lowputc_get_sclk(const struct esp32c6_uart_s * conf) -{ - uint32_t clk_conf_reg; - uint32_t ret = -ENODATA; - clk_conf_reg = getreg32(UART_CLK_CONF_REG(conf->id)); - clk_conf_reg &= UART_SCLK_SEL_M; - clk_conf_reg >>= UART_SCLK_SEL_S; - switch (clk_conf_reg) - { - case 1: - ret = APB_CLK_FREQ; - break; - case 2: - ret = RTC_CLK_FREQ; - break; - case 3: - ret = XTAL_CLK_FREQ; - break; - } - - return ret; -} - -/**************************************************************************** - * Name: esp32c6_lowputc_baud - * Set the baud rate - ****************************************************************************/ - -void esp32c6_lowputc_baud(const struct esp32c6_uart_s * conf) -{ - const int sclk_div = 1; - uint32_t sclk_freq = esp32c6_lowputc_get_sclk(conf); - uint32_t clk_div = ((sclk_freq) << 4) / conf->baud; - uint32_t int_part = clk_div >> 4; - uint32_t frag_part = clk_div & 0xf; - - /* The baud rate configuration register is divided into - * an integer part and a fractional part. - */ - - modifyreg32(UART_CLKDIV_SYNC_REG(conf->id), UART_CLKDIV_M, int_part); - modifyreg32(UART_CLKDIV_SYNC_REG(conf->id), UART_CLKDIV_FRAG_M, - frag_part << UART_CLKDIV_FRAG_S); - modifyreg32(UART_CLK_CONF_REG(conf->id), UART_SCLK_DIV_NUM_M, - (sclk_div - 1) << UART_SCLK_DIV_NUM_S); -} - -/**************************************************************************** - * Name: esp32c6_lowputc_normal_mode - * Set the UART to operate in normal mode - ****************************************************************************/ - -void esp32c6_lowputc_normal_mode(const struct esp32c6_uart_s * conf) -{ - /* Disable RS485 mode */ - - modifyreg32(UART_RS485_CONF_SYNC_REG(conf->id), UART_RS485_EN_M, 0); - modifyreg32(UART_RS485_CONF_SYNC_REG(conf->id), UART_RS485TX_RX_EN_M, 0); - modifyreg32(UART_RS485_CONF_SYNC_REG(conf->id), UART_RS485RXBY_TX_EN_M, 0); - - /* Disable IRDA mode */ - - modifyreg32(UART_CONF0_SYNC_REG(conf->id), UART_IRDA_EN_M, 0); -} - -/**************************************************************************** - * Name: esp32c6_lowputc_parity - * Set the parity - ****************************************************************************/ - -void esp32c6_lowputc_parity(const struct esp32c6_uart_s * conf) -{ - if (conf->parity == UART_PARITY_DISABLE) - { - modifyreg32(UART_CONF0_SYNC_REG(conf->id), UART_PARITY_EN_M, 0); - } - else - { - modifyreg32(UART_CONF0_SYNC_REG(conf->id), UART_PARITY_M, - ((conf->parity & 0x1) << UART_PARITY_S)); - modifyreg32(UART_CONF0_SYNC_REG(conf->id), UART_PARITY_EN_M, - 1 << UART_PARITY_EN_S); - } -} - -/**************************************************************************** - * Name: esp32c6_lowputc_data_length - * Set the data length - ****************************************************************************/ - -int esp32c6_lowputc_data_length(const struct esp32c6_uart_s * conf) -{ - int ret = OK; - uint32_t length = (conf->bits - 5); - - /* If it is the allowed range */ - - if (length >= UART_DATA_5_BITS && length <= UART_DATA_8_BITS) - { - modifyreg32(UART_CONF0_SYNC_REG(conf->id), UART_BIT_NUM_M, - length << UART_BIT_NUM_S); - } - else - { - ret = -EINVAL; - } - - return ret; -} - -/**************************************************************************** - * Name: esp32c6_lowputc_stop_length - * Set the stop length - ****************************************************************************/ - -void esp32c6_lowputc_stop_length(const struct esp32c6_uart_s * conf) -{ - if (conf->stop_b2 == 0) - { - modifyreg32(UART_CONF0_SYNC_REG(conf->id), UART_STOP_BIT_NUM_M, - UART_STOP_BITS_1 << UART_STOP_BIT_NUM_S); - } - else - { - modifyreg32(UART_CONF0_SYNC_REG(conf->id), UART_STOP_BIT_NUM_M, - UART_STOP_BITS_2 << UART_STOP_BIT_NUM_S); - } -} - -/**************************************************************************** - * Name: esp32c6_lowputc_set_tx_idle_time - * Set the idle time between transfers - ****************************************************************************/ - -void esp32c6_lowputc_set_tx_idle_time(const struct esp32c6_uart_s * - conf, uint32_t time) -{ - time = time << UART_TX_IDLE_NUM_S; - time = time & UART_TX_IDLE_NUM_M; /* Just in case value overloads */ - modifyreg32(UART_IDLE_CONF_SYNC_REG(conf->id), UART_TX_IDLE_NUM_M, - time); -} - -/**************************************************************************** - * Name: esp32c6_lowputc_send_byte - * Send one byte - ****************************************************************************/ - -void esp32c6_lowputc_send_byte(const struct esp32c6_uart_s * conf, - char byte) -{ - putreg32((uint32_t) byte, UART_FIFO_REG(conf->id)); -} - -/**************************************************************************** - * Name: esp32c6_lowputc_is_tx_fifo_full - * Verifies if TX FIFO is full - ****************************************************************************/ - -bool esp32c6_lowputc_is_tx_fifo_full(const struct esp32c6_uart_s * - conf) -{ - uint32_t reg; - reg = getreg32(UART_STATUS_REG(conf->id)); - reg = reg >> UART_TXFIFO_CNT_S; - reg = reg & UART_TXFIFO_CNT_V; - if (reg < (UART_TX_FIFO_SIZE -1)) - { - return false; - } - else - { - return true; - } -} - -/**************************************************************************** - * Name: esp32c6_lowputc_disable_all_uart_int - * - * Description: - * Disable all UART interrupts. - * - * Parameters: - * priv - Pointer to the private driver struct. - * current_status - Pointer to a variable to store the current status of - * the interrupt enable register before disabling - * UART interrupts. - * - ****************************************************************************/ - -void esp32c6_lowputc_disable_all_uart_int(const struct esp32c6_uart_s *priv, - uint32_t *current_status) -{ - irqstate_t flags; - - flags = enter_critical_section(); - - if (current_status != NULL) - { - /* Save current status */ - - *current_status = getreg32(UART_INT_ENA_REG(priv->id)); - } - - /* Disable all UART int */ - - putreg32(0, UART_INT_ENA_REG(priv->id)); - - /* Clear all ints */ - - putreg32(0xffffffff, UART_INT_CLR_REG(priv->id)); - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: esp32c6_lowputc_restore_all_uart_int - * - * Description: - * Restore all UART interrupts. - * - * Parameters: - * priv - Pointer to the private driver struct. - * last_status - Pointer to a variable that stored the last state of the - * interrupt enable register. - * - ****************************************************************************/ - -void esp32c6_lowputc_restore_all_uart_int(const struct esp32c6_uart_s *priv, - uint32_t *last_status) -{ - /* Restore the previous behaviour */ - - putreg32(*last_status, UART_INT_ENA_REG(priv->id)); -} - -/**************************************************************************** - * Name: riscv_lowputc - * - * Description: - * Output one byte on the serial console. - * - * Parameters: - * ch - Byte to be sent. - * - ****************************************************************************/ - -void riscv_lowputc(char ch) -{ -#ifdef CONSOLE_UART - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) - struct esp32c6_uart_s *priv = &g_uart0_config; -#elif defined (CONFIG_UART1_SERIAL_CONSOLE) - struct esp32c6_uart_s *priv = &g_uart1_config; -#endif - - /* Wait until the TX FIFO has space to insert new char */ - - while (esp32c6_lowputc_is_tx_fifo_full(priv)); - - /* Then send the character */ - - esp32c6_lowputc_send_byte(priv, ch); - -#endif /* CONSOLE_UART */ -} - -/**************************************************************************** - * Name: esp32c6_lowsetup - * - * Description: - * This performs basic initialization of the UART used for the serial - * console. Its purpose is to get the console output available as soon - * as possible. - * - ****************************************************************************/ - -void esp32c6_lowsetup(void) -{ - /* Enable and configure the selected console device */ - -#if defined(HAVE_SERIAL_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) - struct esp32c6_uart_s *priv = &g_uart0_config; -#elif defined (CONFIG_UART1_SERIAL_CONSOLE) - struct esp32c6_uart_s *priv = &g_uart1_config; -#endif - - /* Configure Clock */ - - /* esp32c6_lowputc_set_sclk(&g_console_config, APB_CLK); */ - - /* Configure the UART Baud Rate */ - - /* esp32c6_lowputc_baud(&g_console_config); */ - - /* Set a mode */ - - esp32c6_lowputc_normal_mode(priv); - - /* Parity */ - - esp32c6_lowputc_parity(priv); - - /* Data Frame size */ - - esp32c6_lowputc_data_length(priv); - - /* Stop bit */ - - esp32c6_lowputc_stop_length(priv); - - /* No Tx idle interval */ - - esp32c6_lowputc_set_tx_idle_time(priv, 0); - - /* Enable cores */ - - esp32c6_lowputc_enable_sclk(priv); - -#endif /* HAVE_SERIAL_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ -} diff --git a/arch/risc-v/src/esp32c6/esp32c6_lowputc.h b/arch/risc-v/src/esp32c6/esp32c6_lowputc.h deleted file mode 100644 index 48f120d3af868..0000000000000 --- a/arch/risc-v/src/esp32c6/esp32c6_lowputc.h +++ /dev/null @@ -1,252 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/esp32c6_lowputc.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C6_ESP32C6_LOWPUTC_H -#define __ARCH_RISCV_SRC_ESP32C6_ESP32C6_LOWPUTC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "hardware/esp32c6_uart.h" -#include "chip.h" - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -enum uart_sclk -{ - APB_CLK = 1, /* 80 MHz */ - CLK_8, /* 8 MHz */ - XTAL_CLK -}; - -enum uart_parity -{ - UART_PARITY_DISABLE, - UART_PARITY_ODD, - UART_PARITY_EVEN -}; - -enum uart_data_length -{ - UART_DATA_5_BITS, - UART_DATA_6_BITS, - UART_DATA_7_BITS, - UART_DATA_8_BITS -}; - -enum uart_stop_length -{ - UART_STOP_BITS_1 = 0x1, /* stop bit: 1 bit */ - UART_STOP_BITS_2 = 0x3, /* stop bit: 2bits */ -}; - -/* Default FIFOs size */ - -#define UART_TX_FIFO_SIZE 128 -#define UART_RX_FIFO_SIZE 128 - -/* Struct used to store uart driver information and to - * manipulate uart driver - */ - -struct esp32c6_uart_s -{ - uint32_t base; /* Base address of UART registers */ - uint8_t periph; /* UART peripheral ID */ - int cpuint; /* CPU interrupt assigned to this UART */ - uint8_t id; /* UART ID */ - uint8_t irq; /* IRQ associated with this UART */ - uint32_t baud; /* Configured baud rate */ - uint8_t bits; - uint8_t parity; /* 0=no parity, 1=odd parity, 2=even parity */ - uint8_t stop_b2; /* Use 2 stop bits? 0 no, others yes */ - uint8_t int_pri; /* UART Interrupt Priority */ -}; - -#ifdef CONFIG_ESP32C6_UART0 -extern struct esp32c6_uart_s g_uart0_config; -#endif - -#ifdef CONFIG_ESP32C6_UART1 -extern struct esp32c6_uart_s g_uart1_config; -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c6_lowputc_reset_core - * Reset both TX and RX core - ****************************************************************************/ - -void esp32c6_lowputc_reset_core(const struct esp32c6_uart_s *conf); - -/**************************************************************************** - * Name: esp32c6_lowputc_enable_sclk - * Enable clock for whole core - ****************************************************************************/ - -void esp32c6_lowputc_enable_sclk(const struct esp32c6_uart_s *conf); - -/**************************************************************************** - * Name: esp32c6_lowputc_disable_sclk - * Disable clock for whole core - ****************************************************************************/ - -void esp32c6_lowputc_disable_sclk(const struct esp32c6_uart_s *conf); - -/**************************************************************************** - * Name: esp32c6_lowputc_set_sclk - * Set a source clock for UART - * APB_CLK = 1 80 MHz - * CLK_8 = 2 8 MHz - * XTAL_CLK = 3 - ****************************************************************************/ - -void esp32c6_lowputc_set_sclk(const struct esp32c6_uart_s *conf, enum - uart_sclk source); - -/**************************************************************************** - * Name: esp32c6_lowputc_get_sclk - * Get the source clock for UART - ****************************************************************************/ - -uint32_t esp32c6_lowputc_get_sclk(const struct esp32c6_uart_s *conf); - -/**************************************************************************** - * Name: esp32c6_lowputc_baud - * Set the baud rate - ****************************************************************************/ - -void esp32c6_lowputc_baud(const struct esp32c6_uart_s * conf); - -/**************************************************************************** - * Name: esp32c6_lowputc_normal_mode - * Set the UART to operate in normal mode - ****************************************************************************/ - -void esp32c6_lowputc_normal_mode(const struct esp32c6_uart_s * conf); - -/**************************************************************************** - * Name: esp32c6_lowputc_parity - * Set the parity - ****************************************************************************/ - -void esp32c6_lowputc_parity(const struct esp32c6_uart_s * conf); - -/**************************************************************************** - * Name: esp32c6_lowputc_data_length - * Set the data length - ****************************************************************************/ - -int esp32c6_lowputc_data_length(const struct esp32c6_uart_s * conf); - -/**************************************************************************** - * Name: esp32c6_lowputc_stop_length - * Set the stop length - ****************************************************************************/ - -void esp32c6_lowputc_stop_length(const struct esp32c6_uart_s * conf); - -/**************************************************************************** - * Name: esp32c6_lowputc_set_tx_idle_time - * Set the idle time between transfers - ****************************************************************************/ - -void esp32c6_lowputc_set_tx_idle_time(const struct esp32c6_uart_s * - conf, uint32_t time); - -/**************************************************************************** - * Name: esp32c6_lowputc_send_byte - * Send one byte - ****************************************************************************/ - -void esp32c6_lowputc_send_byte(const struct esp32c6_uart_s * conf, - char byte); - -/**************************************************************************** - * Name: esp32c6_lowputc_is_tx_fifo_full - * Send one byte - ****************************************************************************/ - -bool esp32c6_lowputc_is_tx_fifo_full(const struct esp32c6_uart_s *conf); - -/**************************************************************************** - * Name: esp32c6_lowputc_disable_all_uart_int - * - * Description: - * Disable all UART interrupts. - * - * Parameters: - * priv - Pointer to the private driver struct. - * current_status - Pointer to a variable to store the current status of - * the interrupt enable register before disabling - * UART interrupts. - * - ****************************************************************************/ - -void esp32c6_lowputc_disable_all_uart_int(const struct esp32c6_uart_s *priv, - uint32_t *current_status); - -/**************************************************************************** - * Name: esp32c6_lowputc_restore_all_uart_int - * - * Description: - * Restore all UART interrupts. - * - * Parameters: - * priv - Pointer to the private driver struct. - * last_status - Pointer to a variable that stored the last state of the - * interrupt enable register. - * - ****************************************************************************/ - -void esp32c6_lowputc_restore_all_uart_int(const struct esp32c6_uart_s *priv, - uint32_t *last_status); - -/**************************************************************************** - * Name: esp32c6_lowsetup - * - * Description: - * This performs basic initialization of the UART used for the serial - * console. Its purpose is to get the console output available as soon - * as possible. - * - ****************************************************************************/ - -void esp32c6_lowsetup(void); - -#endif /* __ARCH_RISCV_SRC_ESP32C6_ESP32C6_LOWPUTC_H */ \ No newline at end of file diff --git a/arch/risc-v/src/esp32c6/esp32c6_memorymap.h b/arch/risc-v/src/esp32c6/esp32c6_memorymap.h deleted file mode 100644 index 8cdc6a304a329..0000000000000 --- a/arch/risc-v/src/esp32c6/esp32c6_memorymap.h +++ /dev/null @@ -1,43 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/esp32c6_memorymap.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef _ARCH_RISCV_SRC_ESP32C6_ESP32C6_MEMORYMAP_H -#define _ARCH_RISCV_SRC_ESP32C6_ESP32C6_MEMORYMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Idle thread stack starts from _ebss */ - -#ifndef __ASSEMBLY__ -#define ESP32C6_IDLESTACK_BASE (uint32_t)&g_idlestack -#else -#define ESP32C6_IDLESTACK_BASE g_idlestack -#endif - -#define ESP32C6_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3) -#define ESP32C6_IDLESTACK_TOP (ESP32C6_IDLESTACK_BASE + ESP32C6_IDLESTACK_SIZE) - -#endif /* _ARCH_RISCV_SRC_ESP32C6_ESP32C6_MEMORYMAP_H */ diff --git a/arch/risc-v/src/esp32c6/esp32c6_serial.c b/arch/risc-v/src/esp32c6/esp32c6_serial.c deleted file mode 100644 index 70e8f389f0fc8..0000000000000 --- a/arch/risc-v/src/esp32c6/esp32c6_serial.c +++ /dev/null @@ -1,714 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/esp32c6_serial.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "riscv_internal.h" -#include "chip.h" -#include "hardware/esp32c6_uart.h" - -#include "esp32c6_lowputc.h" -#include "esp32c6_config.h" -#include "esp32c6_irq.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The console is enabled, and it's not the syslog device, - * so, it should be a serial device. - */ - -#ifdef USE_SERIALDRIVER - -/* Which UART with be tty0/console and which tty1? */ - -/* First pick the console and ttys0. - * Console can be UART0 or UART1, but will always be ttys0. - */ - -/* In case a UART was assigned to be - * the console and the corresponding peripheral was also selected. - */ - -#ifdef CONSOLE_UART -# if defined(CONFIG_UART0_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart0_dev /* UART0 is console */ -# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */ -# define UART0_ASSIGNED 1 -# elif defined(CONFIG_UART1_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart1_dev /* UART1 is console */ -# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */ -# define UART1_ASSIGNED 1 -# endif /* CONFIG_UART0_SERIAL_CONSOLE */ -#else /* No UART console */ -# undef CONSOLE_DEV -# if defined(CONFIG_ESP32C6_UART0) -# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */ -# define UART0_ASSIGNED 1 -# elif defined(CONFIG_ESP32C6_UART1) -# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */ -# define UART1_ASSIGNED 1 -# endif -#endif /* CONSOLE_UART */ - -/* Pick ttys1 */ - -#if defined(CONFIG_ESP32C6_UART0) && !defined(UART0_ASSIGNED) -# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */ -# define UART0_ASSIGNED 1 -#elif defined(CONFIG_ESP32C5_UART1) && !defined(UART1_ASSIGNED) -# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */ -# define UART1_ASSIGNED 1 -#endif - -#ifdef HAVE_UART_DEVICE - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#ifdef CONFIG_ESP32C6_UART - -/* Serial driver methods */ - -static int esp32c6_setup(struct uart_dev_s *dev); -static void esp32c6_shutdown(struct uart_dev_s *dev); -static int esp32c6_attach(struct uart_dev_s *dev); -static void esp32c6_detach(struct uart_dev_s *dev); -static void esp32c6_txint(struct uart_dev_s *dev, bool enable); -static void esp32c6_rxint(struct uart_dev_s *dev, bool enable); -static bool esp32c6_rxavailable(struct uart_dev_s *dev); -static bool esp32c6_txready(struct uart_dev_s *dev); -static bool esp32c6_txempty(struct uart_dev_s *dev); -static void esp32c6_send(struct uart_dev_s *dev, int ch); -static int esp32c6_receive(struct uart_dev_s *dev, unsigned int *status); -static int esp32c6_ioctl(struct file *filep, int cmd, unsigned long arg); -#ifdef CONFIG_SERIAL_IFLOWCONTROL -static bool esp32c6_rxflowcontrol(struct uart_dev_s *dev, - unsigned int nbuffered, bool upper); -#endif -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_ESP32C6_UART - -/* Operations */ - -static struct uart_ops_s g_uart_ops = -{ - .setup = esp32c6_setup, - .shutdown = esp32c6_shutdown, - .attach = esp32c6_attach, - .detach = esp32c6_detach, - .txint = esp32c6_txint, - .rxint = esp32c6_rxint, - .rxavailable = esp32c6_rxavailable, - .txready = esp32c6_txready, - .txempty = esp32c6_txempty, - .send = esp32c6_send, - .receive = esp32c6_receive, - .ioctl = esp32c6_ioctl, -#ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = esp32c6_rxflowcontrol, -#endif -}; - -/* UART 0 */ - -#ifdef CONFIG_ESP32C6_UART0 - -static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE]; -static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE]; - -/* Fill only the requested fields */ - -static uart_dev_t g_uart0_dev = -{ -#ifdef CONFIG_UART0_SERIAL_CONSOLE - .isconsole = true, -#else - .isconsole = false, -#endif - .xmit = - { - .size = CONFIG_UART0_TXBUFSIZE, - .buffer = g_uart0_txbuffer, - }, - .recv = - { - .size = CONFIG_UART0_RXBUFSIZE, - .buffer = g_uart0_rxbuffer, - }, - - .ops = &g_uart_ops, - .priv = &g_uart0_config -}; - -#endif - -/* UART 1 */ - -#ifdef CONFIG_ESP32C6_UART1 - -static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE]; -static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE]; - -/* Fill only the requested fields */ - -static uart_dev_t g_uart1_dev = -{ -#ifdef CONFIG_UART1_SERIAL_CONSOLE - .isconsole = true, -#else - .isconsole = false, -#endif - .xmit = - { - .size = CONFIG_UART1_TXBUFSIZE, - .buffer = g_uart1_txbuffer, - }, - .recv = - { - .size = CONFIG_UART1_RXBUFSIZE, - .buffer = g_uart1_rxbuffer, - }, - - .ops = &g_uart_ops, - .priv = &g_uart1_config -}; - -#endif - -#endif /* CONFIG_ESP32C6_UART */ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -#ifdef CONFIG_ESP32C6_UART - -/**************************************************************************** - * Name: uart_interrupt - * - * Description: - * This is the UART interrupt handler. It will be invoked when an - * interrupt is received on the 'irq' It should call uart_xmitchars or - * uart_recvchars to perform the appropriate data transfers. The - * interrupt handling logic must be able to map the 'irq' number into the - * appropriate uart_dev_s structure in order to call these functions. - * - ****************************************************************************/ - -static int uart_handler(int irq, void *context, void *arg) -{ - struct uart_dev_s *dev = (struct uart_dev_s *)arg; - struct esp32c6_uart_s *priv = dev->priv; - uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M; - uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M; - uint32_t int_status; - - int_status = getreg32(UART_INT_ST_REG(priv->id)); - - /* Tx fifo empty interrupt or UART tx done int */ - - if (int_status & tx_mask) - { - uart_xmitchars(dev); - modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask); - } - - /* Rx fifo timeout interrupt or rx fifo full interrupt */ - - if (int_status & rx_mask) - { - uart_recvchars(dev); - modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask); - } - - return OK; -} - -/**************************************************************************** - * Name: esp32c6_setup - * - * Description: - * Configure the UART baud, bits, parity, fifos, etc. This method is - * called the first time that the serial port is opened. - * For the serial console, this will occur very early in initialization, - * for other serial ports this will occur when the port is first opened. - * This setup does not include attaching or enabling interrupts. - * That portion of the UART setup is performed when the attach() method - * is called. - * - ****************************************************************************/ - -static int esp32c6_setup(struct uart_dev_s *dev) -{ - return OK; -} - -/**************************************************************************** - * Name: esp32c6_shutdown - * - * Description: - * Disable the UART. This method is called when the serial port is closed. - * This method reverses the operation the setup method. NOTE that the serial - * console is never shutdown. - * - ****************************************************************************/ - -static void esp32c6_shutdown(struct uart_dev_s *dev) -{ - struct esp32c6_uart_s *priv = dev->priv; - - /* Disable ints */ - - esp32c6_lowputc_disable_all_uart_int(priv, NULL); -} - -/**************************************************************************** - * Name: esp32c6_attach - * - * Description: - * Configure the UART to operation in interrupt driven mode. This method - * is called when the serial port is opened. Normally, this is just after - * the the setup() method is called, however, the serial console may - * operate in a non-interrupt driven mode during the boot phase. - * - * RX and TX interrupts are not enabled when by the attach method (unless - * the hardware supports multiple levels of interrupt enabling). The RX - * and TX interrupts are not enabled until the txint() and rxint() methods - * are called. - * - ****************************************************************************/ - -static int esp32c6_attach(struct uart_dev_s *dev) -{ - struct esp32c6_uart_s *priv = dev->priv; - int ret; - - DEBUGASSERT(priv->cpuint == -ENOMEM); - - /* Set up to receive peripheral interrupts */ - - priv->cpuint = esp32c6_setup_irq(priv->periph, priv->int_pri, - ESP32C6_INT_LEVEL); - if (priv->cpuint < 0) - { - return priv->cpuint; - } - - /* Attach and enable the IRQ */ - - ret = irq_attach(priv->irq, uart_handler, dev); - if (ret == OK) - { - up_enable_irq(priv->irq); - } - else - { - up_disable_irq(priv->irq); - } - - return ret; -} - -/**************************************************************************** - * Name: esp32_detach - * - * Description: - * Detach UART interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The - * exception is the serial console which is never shutdown. - * - ****************************************************************************/ - -static void esp32c6_detach(struct uart_dev_s *dev) -{ - struct esp32c6_uart_s *priv = dev->priv; - - DEBUGASSERT(priv->cpuint != -ENOMEM); - - /* Disable and detach the CPU interrupt */ - - up_disable_irq(priv->irq); - irq_detach(priv->irq); - - /* Disassociate the peripheral interrupt from the CPU interrupt */ - - esp32c6_teardown_irq(priv->periph, priv->cpuint); - priv->cpuint = -ENOMEM; -} - -/**************************************************************************** - * Name: esp32c6_txint - * - * Description: - * Call to enable or disable TX interrupts - * - ****************************************************************************/ - -static void esp32c6_txint(struct uart_dev_s *dev, bool enable) -{ - struct esp32c6_uart_s *priv = dev->priv; - uint32_t ints_mask = UART_TXFIFO_EMPTY_INT_ENA_M | UART_TX_DONE_INT_ENA_M; - - if (enable) - { - /* Set to receive an interrupt when the TX holding register register - * is empty - */ - -#ifndef CONFIG_SUPPRESS_SERIAL_INTS - modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask); -#endif - } - else - { - /* Disable the TX interrupt */ - - modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0); - } -} - -/**************************************************************************** - * Name: esp32c6_rxint - * - * Description: - * Call to enable or disable RXRDY interrupts - * - ****************************************************************************/ - -static void esp32c6_rxint(struct uart_dev_s *dev, bool enable) -{ - struct esp32c6_uart_s *priv = dev->priv; - uint32_t ints_mask = UART_RXFIFO_TOUT_INT_ENA_M | - UART_RXFIFO_FULL_INT_ENA_M; - - if (enable) - { - /* Receive an interrupt when their is anything in the Rx data register - * (or an Rx timeout occurs). - */ - -#ifndef CONFIG_SUPPRESS_SERIAL_INTS - modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M, - UART_RX_TOUT_EN_M); - modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask); -#endif - } - else - { - modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M, 0); - - /* Disable the RX interrupts */ - - modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0); - } -} - -/**************************************************************************** - * Name: esp32c6_rxavailable - * - * Description: - * Return true if the receive holding register is not empty - * - ****************************************************************************/ - -static bool esp32c6_rxavailable(struct uart_dev_s *dev) -{ - struct esp32c6_uart_s *priv = dev->priv; - uint32_t status_reg; - uint32_t bytes; - - status_reg = getreg32(UART_STATUS_REG(priv->id)); - bytes = status_reg & UART_RXFIFO_CNT_M; - - return (bytes > 0) ? true : false; -} - -/**************************************************************************** - * Name: esp32c6_txready - * - * Description: - * Return true if the tranmsit hardware is ready to send another byte. This - * is used to determine if send() method can be called. - * - ****************************************************************************/ - -static bool esp32c6_txready(struct uart_dev_s *dev) -{ - return (esp32c6_lowputc_is_tx_fifo_full(dev->priv)) ? false : true; -} - -/**************************************************************************** - * Name: esp32c6_txempty - * - * Description: - * Return true if all characters have been sent. If for example, the UART - * hardware implements FIFOs, then this would mean the transmit FIFO is - * empty. This method is called when the driver needs to make sure that - * all characters are "drained" from the TX hardware. - * - ****************************************************************************/ - -static bool esp32c6_txempty(struct uart_dev_s *dev) -{ - uint32_t reg; - struct esp32c6_uart_s *priv = dev->priv; - - reg = getreg32(UART_INT_RAW_REG(priv->id)); - reg = REG_MASK(reg, UART_TX_DONE_INT_RAW); - - return reg > 0; -} - -/**************************************************************************** - * Name: esp32c6_send - * - * Description: - * Send a unique character - * - * Parameters: - * dev - Pointer to the serial driver struct. - * ch - Byte to be sent. - * - ****************************************************************************/ - -static void esp32c6_send(struct uart_dev_s *dev, int ch) -{ - /* Then send the character */ - - esp32c6_lowputc_send_byte(dev->priv, ch); -} - -/**************************************************************************** - * Name: esp32c6_receive - * - * Description: - * Called (usually) from the interrupt level to receive one - * character from the UART. Error bits associated with the - * receipt are provided in the return 'status'. - * - ****************************************************************************/ - -static int esp32c6_receive(struct uart_dev_s *dev, unsigned int *status) -{ - uint32_t rx_fifo; - struct esp32c6_uart_s *priv = dev->priv; - - rx_fifo = getreg32(UART_FIFO_REG(priv->id)); - rx_fifo = rx_fifo & UART_RXFIFO_RD_BYTE_M; - - /* Since we don't have error bits associated with receipt, we set zero */ - - *status = 0; - - return (int)rx_fifo; -} - -/**************************************************************************** - * Name: esp32c6_ioctl - * - * Description: - * All ioctl calls will be routed through this method. - * Here it's employed to implement the TERMIOS ioctls and TIOCSERGSTRUCT. - * - * Parameters: - * filep Pointer to a file structure instance. - * cmd The ioctl command. - * arg The argument of the ioctl cmd. - * - * Returned Value: - * Returns a non-negative number on success; A negated errno value is - * returned on any failure (see comments ioctl() for a list of appropriate - * errno values). - * - ****************************************************************************/ - -static int esp32c6_ioctl(struct file *filep, int cmd, unsigned long arg) -{ - return OK; -} - -#endif /* CONFIG_ESP32C6_UART */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#ifdef USE_EARLYSERIALINIT - -/**************************************************************************** - * Name: riscv_earlyserialinit - * - * Description: - * Performs the low level UART initialization early in debug so that the - * serial console will be available during bootup. This must be called - * before riscv_serialinit. NOTE: This function depends on GPIO pin - * configuration performed in up_consoleinit() and main clock - * initialization performed in up_clkinitialize(). - * - ****************************************************************************/ - -void riscv_earlyserialinit(void) -{ - /* NOTE: All GPIO configuration for the UARTs was performed in - * esp32c6_lowsetup - */ - - /* Disable all UARTS interrupts */ - -#ifdef TTYS0_DEV - esp32c6_lowputc_disable_all_uart_int(TTYS0_DEV.priv, NULL); -#endif - -#ifdef TTYS1_DEV - esp32c6_lowputc_disable_all_uart_int(TTYS1_DEV.priv, NULL); -#endif - - /* Configure console in early step. - * Setup for other serials will be perfomed when the serial driver is - * open. - */ - -#ifdef CONSOLE_UART - esp32c6_setup(&CONSOLE_DEV); -#endif -} - -#endif /* USE_EARLYSERIALINIT */ - -/**************************************************************************** - * Name: riscv_serialinit - * - * Description: - * Register serial console and serial ports. This assumes - * that riscv_earlyserialinit was called previously. - * - ****************************************************************************/ - -void riscv_serialinit(void) -{ -#ifdef HAVE_SERIAL_CONSOLE - uart_register("/dev/console", &CONSOLE_DEV); -#endif - -#ifdef TTYS0_DEV - uart_register("/dev/ttyS0", &TTYS0_DEV); -#endif - -#ifdef TTYS1_DEV - uart_register("/dev/ttyS1", &TTYS1_DEV); -#endif -} - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug writes - * - ****************************************************************************/ - -int up_putc(int ch) -{ -#ifdef CONSOLE_UART - uint32_t int_status; - - esp32c6_lowputc_disable_all_uart_int(CONSOLE_DEV.priv, &int_status); -#endif - - /* Check for LF */ - - if (ch == '\n') - { - /* Add CR */ - - riscv_lowputc('\r'); - } - - riscv_lowputc(ch); - -#ifdef CONSOLE_UART - esp32c6_lowputc_restore_all_uart_int(CONSOLE_DEV.priv, &int_status); -#endif - return ch; -} - -#endif /* HAVE_UART_DEVICE */ - -#else /* USE_SERIALDRIVER */ - -/**************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug writes - * - ****************************************************************************/ - -int up_putc(int ch) -{ -#ifdef CONSOLE_UART - uint32_t int_status; - - esp32c6_lowputc_disable_all_uart_int(CONSOLE_DEV.priv, &int_status); -#endif - - /* Check for LF */ - - if (ch == '\n') - { - /* Add CR */ - - riscv_lowputc('\r'); - } - - riscv_lowputc(ch); - -#ifdef CONSOLE_UART - esp32c6_lowputc_restore_all_uart_int(CONSOLE_DEV.priv, &int_status); -#endif - return ch; -} - -#endif /* USE_SERIALDRIVER */ diff --git a/arch/risc-v/src/esp32c6/esp32c6_start.c b/arch/risc-v/src/esp32c6/esp32c6_start.c deleted file mode 100644 index 397e33e18711b..0000000000000 --- a/arch/risc-v/src/esp32c6/esp32c6_start.c +++ /dev/null @@ -1,101 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/esp32c6_start.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "chip.h" -#include "esp32c6.h" -#include "esp32c6_irq.h" -#include "esp32c6_lowputc.h" -#include "esp32c6_clockconfig.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_FEATURES -# define showprogress(c) riscv_lowputc(c) -#else -# define showprogress(c) -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Address of the IDLE thread */ - -uint8_t g_idlestack[CONFIG_IDLETHREAD_STACKSIZE] - aligned_data(16) locate_data(".noinit"); -uintptr_t g_idle_topstack = ESP32C6_IDLESTACK_TOP; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: __esp32c6_start - ****************************************************************************/ - -void __esp32c6_start(void) -{ - /* Set CPU frequency */ - - esp32c6_clockconfig(); - - /* Configure the UART so we can get debug output */ - - esp32c6_lowsetup(); - - showprogress('A'); - - /* Clear .bss. We'll do this inline (vs. calling memset) just to be - * certain that there are no issues with the state of global variables. - */ - - for (uint32_t *dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; ) - { - *dest++ = 0; - } - - showprogress('B'); - -#ifndef CONFIG_SUPPRESS_INTERRUPTS - - /* Put the CPU Interrupts in initial state */ - - esp32c6_cpuint_initialize(); -#endif - - /* Call nx_start() */ - - nx_start(); - - for (; ; ); -} diff --git a/arch/risc-v/src/esp32c6/esp32c6_systemreset.c b/arch/risc-v/src/esp32c6/esp32c6_systemreset.c deleted file mode 100644 index 379180fb6bc47..0000000000000 --- a/arch/risc-v/src/esp32c6/esp32c6_systemreset.c +++ /dev/null @@ -1,53 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/esp32c6_systemreset.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "esp32c6.h" -#include "hardware/esp32c6_lp_aon.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_systemreset - * - * Description: - * Internal reset logic. - * - ****************************************************************************/ - -void up_systemreset(void) -{ - putreg32(LP_AON_HPSYS_SW_RESET, LP_AON_SYS_CFG_REG); - - /* Wait for the reset */ - - for (; ; ); -} diff --git a/arch/risc-v/src/esp32c6/esp32c6_timerisr.c b/arch/risc-v/src/esp32c6/esp32c6_timerisr.c deleted file mode 100644 index a488059945ae9..0000000000000 --- a/arch/risc-v/src/esp32c6/esp32c6_timerisr.c +++ /dev/null @@ -1,127 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/esp32c6_timerisr.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "chip.h" -#include "esp32c6.h" -#include "esp32c6_irq.h" -#include "hardware/esp32c6_systimer.h" -#include "hardware/esp32c6_pcr.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ESP32C6_SYSTIMER_TICKS_PER_SEC (16 * 1000 * 1000) - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: systimer_isr - ****************************************************************************/ - -static int systimer_isr(int irq, void *context, void *arg) -{ - setbits(SYSTIMER_TARGET0_INT_CLR, SYSTIMER_INT_CLR_REG); - - /* Process timer interrupt */ - - nxsched_process_timer(); - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_timer_initialize - * - * Description: - * This function is called during start-up to initialize - * the timer interrupt. - * - ****************************************************************************/ - -void up_timer_initialize(void) -{ - uint32_t regval; - - /* Enable timer clock */ - - setbits(PCR_SYSTIMER_CLK_EN, PCR_SYSTIMER_CONF_REG); - resetbits(PCR_SYSTIMER_RST_EN, PCR_SYSTIMER_CONF_REG); - - setbits(SYSTIMER_CLK_EN, SYSTIMER_CONF_REG); - setbits(SYSTIMER_ETM_EN, SYSTIMER_CONF_REG); - - /* Configure alarm0 counter1 */ - - regval = SYSTIMER_TARGET0_PERIOD_MODE | - (1 << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S) | - ((ESP32C6_SYSTIMER_TICKS_PER_SEC / CLOCKS_PER_SEC) << - SYSTIMER_TARGET0_PERIOD_S); - putreg32(regval, SYSTIMER_TARGET0_CONF_REG); - - putreg32(SYSTIMER_TIMER_COMP0_LOAD, SYSTIMER_COMP0_LOAD_REG); - - /* Stall timer when stall CPU, specially when using JTAG to debug */ - - setbits(SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN, SYSTIMER_CONF_REG); - - /* Enable interrupt */ - - setbits(SYSTIMER_TARGET0_INT_CLR, SYSTIMER_INT_CLR_REG); - setbits(SYSTIMER_TARGET0_INT_ENA, SYSTIMER_INT_ENA_REG); - - regval = SYSTIMER_TARGET0_WORK_EN; - setbits(regval, SYSTIMER_CONF_REG); - - /* Start alarm0 counter1 */ - - regval = SYSTIMER_TIMER_UNIT1_WORK_EN; - setbits(regval, SYSTIMER_CONF_REG); - esp32c6_setup_irq(ESP32C6_SYSTIMER_TARGET0_EDGE_PERIPH, - ESP32C6_INT_PRIO_DEF, - ESP32C6_INT_LEVEL); - - /* Attach the timer interrupt. */ - - irq_attach(ESP32C6_IRQ_SYSTIMER_TARGET0_EDGE, (xcpt_t)systimer_isr, NULL); - - /* Enable the allocated CPU interrupt. */ - - up_enable_irq(ESP32C6_IRQ_SYSTIMER_TARGET0_EDGE); -} diff --git a/arch/risc-v/src/esp32c6/esp32c6_vectors.S b/arch/risc-v/src/esp32c6/esp32c6_vectors.S deleted file mode 100644 index 914626dea03e3..0000000000000 --- a/arch/risc-v/src/esp32c6/esp32c6_vectors.S +++ /dev/null @@ -1,56 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/esp32c6_vectors.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include "chip.h" - -/**************************************************************************** - * Public Symbols - ****************************************************************************/ - - .global _vector_table - -/**************************************************************************** - * Section: .exception_vectors.text - ****************************************************************************/ - - .section .exception_vectors.text - -/**************************************************************************** - * Name: _vector_table - ****************************************************************************/ - - .balign 0x100 - .type _vector_table, @function - -_vector_table: - .option push - .option norvc - - .rept (32) - j exception_common - .endr diff --git a/arch/risc-v/src/esp32c6/esp_coex_adapter.c b/arch/risc-v/src/esp32c6/esp_coex_adapter.c new file mode 100644 index 0000000000000..89b6c3067a733 --- /dev/null +++ b/arch/risc-v/src/esp32c6/esp_coex_adapter.c @@ -0,0 +1,578 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c6/esp_coex_adapter.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "esp_hr_timer.h" +#include "esp_wlan.h" + +#include "esp_attr.h" +#include "esp_timer.h" +#include "soc/rtc.h" +#include "esp_private/esp_clk.h" +#include "esp_coexist_adapter.h" +#include "rom/ets_sys.h" +#include "soc/soc_caps.h" +#include "esp_modem_wrapper.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define OSI_FUNCS_TIME_BLOCKING 0xffffffff + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int64_t esp_coex_esp_timer_get_time_wrapper(void); +static int32_t esp_coex_semphr_take_from_isr_wrapper(void *semphr, + void *hptw); +static int32_t esp_coex_semphr_give_from_isr_wrapper(void *semphr, + void *hptw); +static int esp_coex_is_in_isr_wrapper(void); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +coex_adapter_funcs_t g_coex_adapter_funcs = +{ + ._version = COEX_ADAPTER_VERSION, + ._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper, + ._semphr_create = esp_coex_common_semphr_create_wrapper, + ._semphr_delete = esp_coex_common_semphr_delete_wrapper, + ._semphr_take_from_isr = esp_coex_semphr_take_from_isr_wrapper, + ._semphr_give_from_isr = esp_coex_semphr_give_from_isr_wrapper, + ._semphr_take = esp_coex_common_semphr_take_wrapper, + ._semphr_give = esp_coex_common_semphr_give_wrapper, + ._is_in_isr = esp_coex_is_in_isr_wrapper, + ._malloc_internal = esp_coex_common_malloc_internal_wrapper, + ._free = free, + ._esp_timer_get_time = esp_coex_esp_timer_get_time_wrapper, + ._env_is_chip = esp_coex_common_env_is_chip_wrapper, + ._timer_disarm = esp_coex_common_timer_disarm_wrapper, + ._timer_done = esp_coex_common_timer_done_wrapper, + ._timer_setfn = esp_coex_common_timer_setfn_wrapper, + ._timer_arm_us = esp_coex_common_timer_arm_us_wrapper, + ._magic = COEX_ADAPTER_MAGIC, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_coex_esp_timer_get_time_wrapper + * + * Description: + * This function retrieves the current time of the High Resolution Timer + * in microseconds. It is a wrapper around the esp_hr_timer_time_us + * function, providing a consistent interface for the coexistence module. + * + * Input Parameters: + * None. + * + * Returned Value: + * The current time of the High Resolution Timer in microseconds, as a + * 64-bit integer. + * + ****************************************************************************/ + +static IRAM_ATTR int64_t esp_coex_esp_timer_get_time_wrapper(void) +{ + return (int64_t)esp_hr_timer_time_us(); +} + +/**************************************************************************** + * Name: esp_coex_semphr_take_from_isr_wrapper + * + * Description: + * Take a semaphore from an ISR + * + * Input Parameters: + * semphr - Semaphore data pointer. + * hptw - Unused. + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t IRAM_ATTR esp_coex_semphr_take_from_isr_wrapper(void *semphr, + void *hptw) +{ + *(int *)hptw = 0; + + return nuttx_err_to_freertos(nxsem_trywait(semphr)); +} + +/**************************************************************************** + * Name: esp_coex_semphr_give_from_isr_wrapper + * + * Description: + * Post semaphore + * + * Input Parameters: + * semphr - Semaphore data pointer + * hptw - Unused. + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t IRAM_ATTR esp_coex_semphr_give_from_isr_wrapper(void *semphr, + void *hptw) +{ + *(int *)hptw = 0; + + return esp_coex_common_semphr_give_wrapper(semphr); +} + +/**************************************************************************** + * Name: esp_coex_is_in_isr_wrapper + * + * Description: + * This function checks if the current context is an interrupt service + * routine (ISR). It is a wrapper around the NuttX up_interrupt_context + * function. + * + * Input Parameters: + * None + * + * Returned Value: + * Returns 1 if the current context is an ISR, 0 otherwise. + * + ****************************************************************************/ + +static int IRAM_ATTR esp_coex_is_in_isr_wrapper(void) +{ + return (int)up_interrupt_context(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_coex_common_env_is_chip_wrapper + * + * Description: + * This function checks if the environment is a chip or FPGA. + * + * Input Parameters: + * None + * + * Returned Value: + * Returns true if the environment is a chip, false if it's an FPGA. + * + ****************************************************************************/ + +bool IRAM_ATTR esp_coex_common_env_is_chip_wrapper(void) +{ +#ifdef CONFIG_IDF_ENV_FPGA + return false; +#else + return true; +#endif +} + +/**************************************************************************** + * Name: esp_coex_common_spin_lock_create_wrapper + * + * Description: + * Create spin lock in SMP mode + * + * Input Parameters: + * None + * + * Returned Value: + * Spin lock data pointer + * + ****************************************************************************/ + +void *esp_coex_common_spin_lock_create_wrapper(void) +{ + spinlock_t *lock; + int tmp; + + tmp = sizeof(*lock); + lock = kmm_malloc(tmp); + if (!lock) + { + wlerr("Failed to alloc %d memory\n", tmp); + DEBUGPANIC(); + } + + spin_initialize(lock, SP_UNLOCKED); + + return lock; +} + +/**************************************************************************** + * Name: esp_coex_common_int_disable_wrapper + * + * Description: + * Enter critical section by disabling interrupts and taking the spin lock + * if in SMP mode. + * + * Input Parameters: + * wifi_int_mux - Spin lock data pointer + * + * Returned Value: + * CPU PS value. + * + ****************************************************************************/ + +uint32_t IRAM_ATTR esp_coex_common_int_disable_wrapper(void *wifi_int_mux) +{ + irqstate_t flags; + + flags = spin_lock_irqsave((spinlock_t *)wifi_int_mux); + + return (uint32_t)flags; +} + +/**************************************************************************** + * Name: esp_coex_common_int_restore_wrapper + * + * Description: + * Exit from critical section by enabling interrupts and releasing the spin + * lock if in SMP mode. + * + * Input Parameters: + * wifi_int_mux - Spin lock data pointer + * tmp - CPU PS value. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp_coex_common_int_restore_wrapper(void *wifi_int_mux, + uint32_t tmp) +{ + irqstate_t flags = (irqstate_t)tmp; + + spin_unlock_irqrestore((spinlock_t *)wifi_int_mux, flags); +} + +/**************************************************************************** + * Name: esp_task_yield_from_isr + * + * Description: + * Perform a solicited context switch on FreeRTOS. Do nothing in NuttX. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp_coex_common_task_yield_from_isr_wrapper(void) +{ +} + +/**************************************************************************** + * Name: esp_coex_common_semphr_create_wrapper + * + * Description: + * Create and initialize semaphore + * + * Input Parameters: + * max - No meanining for NuttX + * init - semaphore initialization value + * + * Returned Value: + * Semaphore data pointer + * + ****************************************************************************/ + +void *esp_coex_common_semphr_create_wrapper(uint32_t max, uint32_t init) +{ + int ret; + sem_t *sem; + int tmp; + + tmp = sizeof(sem_t); + sem = kmm_malloc(tmp); + if (!sem) + { + wlerr("Failed to alloc %d memory\n", tmp); + return NULL; + } + + ret = nxsem_init(sem, 0, init); + if (ret) + { + wlerr("Failed to initialize sem error=%d\n", ret); + kmm_free(sem); + return NULL; + } + + return sem; +} + +/**************************************************************************** + * Name: esp_coex_common_semphr_delete_wrapper + * + * Description: + * Delete semaphore + * + * Input Parameters: + * semphr - Semaphore data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp_coex_common_semphr_delete_wrapper(void *semphr) +{ + sem_t *sem = (sem_t *)semphr; + + nxsem_destroy(sem); + kmm_free(sem); +} + +/**************************************************************************** + * Name: esp_coex_common_semphr_take_wrapper + * + * Description: + * This function attempts to take (wait for) a semaphore within a certain + * period of time. It is a wrapper around the NuttX nxsem_wait and + * nxsem_tickwait functions, providing error handling and translation + * between NuttX and ESP-IDF error codes. + * + * Input Parameters: + * semphr - Pointer to the semaphore data structure. + * block_time_tick - The maximum number of system ticks to wait. + * + * Returned Value: + * Returns 0 if the semaphore was successfully taken, or a negative error + * code if the operation failed or the timeout expired. + * + ****************************************************************************/ + +int32_t esp_coex_common_semphr_take_wrapper(void *semphr, + uint32_t block_time_tick) +{ + int ret; + sem_t *sem = (sem_t *)semphr; + + if (block_time_tick == OSI_FUNCS_TIME_BLOCKING) + { + ret = nxsem_wait(sem); + } + else + { + if (block_time_tick > 0) + { + ret = nxsem_tickwait(sem, block_time_tick); + } + else + { + ret = nxsem_trywait(sem); + } + } + + if (ret) + { + wlerr("ERROR: Failed to wait sem in %lu ticks. Error=%d\n", + block_time_tick, ret); + } + + return nuttx_err_to_freertos(ret); +} + +/**************************************************************************** + * Name: esp_coex_common_semphr_give_wrapper + * + * Description: + * This function posts (releases) a semaphore. It is a wrapper around the + * NuttX nxsem_post function, providing error handling and translation + * between NuttX and ESP-IDF error codes. + * + * Input Parameters: + * semphr - Pointer to the semaphore data structure. + * + * Returned Value: + * Returns 0 if the semaphore was successfully posted, or a negative error + * code if the operation failed. + * + ****************************************************************************/ + +int32_t esp_coex_common_semphr_give_wrapper(void *semphr) +{ + int ret; + sem_t *sem = (sem_t *)semphr; + + ret = nxsem_post(sem); + if (ret) + { + wlerr("Failed to post sem error=%d\n", ret); + } + + return nuttx_err_to_freertos(ret); +} + +/**************************************************************************** + * Name: esp_coex_common_timer_disarm_wrapper + * + * Description: + * Disable timer + * + * Input Parameters: + * timer - timer data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp_coex_common_timer_disarm_wrapper(void *timer) +{ + ets_timer_disarm(timer); +} + +/**************************************************************************** + * Name: esp_coex_common_timer_done_wrapper + * + * Description: + * Disable and free timer + * + * Input Parameters: + * timer - timer data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp_coex_common_timer_done_wrapper(void *timer) +{ + ets_timer_done(timer); +} + +/**************************************************************************** + * Name: esp_coex_common_timer_setfn_wrapper + * + * Description: + * Set timer callback function and private data + * + * Input Parameters: + * ptimer - Timer data pointer + * pfunction - Callback function + * parg - Callback function private data + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp_coex_common_timer_setfn_wrapper(void *ptimer, + void *pfunction, + void *parg) +{ + ets_timer_setfn(ptimer, pfunction, parg); +} + +/**************************************************************************** + * Name: esp_coex_common_timer_arm_us_wrapper + * + * Description: + * Set timer timeout period and repeat flag + * + * Input Parameters: + * ptimer - timer data pointer + * us - micro seconds + * repeat - true: run cycle, false: run once + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp_coex_common_timer_arm_us_wrapper(void *ptimer, + uint32_t us, + bool repeat) +{ + ets_timer_arm_us(ptimer, us, repeat); +} + +/**************************************************************************** + * Name: esp_coex_common_clk_slowclk_cal_get_wrapper + * + * Description: + * Get the calibration value of RTC slow clock + * + * Input Parameters: + * None + * + * Returned Value: + * The calibration value obtained using rtc_clk_cal + * + ****************************************************************************/ + +uint32_t esp_coex_common_clk_slowclk_cal_get_wrapper(void) +{ + /* The bit width of WiFi light sleep clock calibration is 12 while the one + * of system is 19. It should shift 19 - 12 = 7. + */ + + return (esp_clk_slowclk_cal_get() >> + (RTC_CLK_CAL_FRACT - SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH)); +} + +/**************************************************************************** + * Name: esp_coex_common_malloc_internal_wrapper + * + * Description: + * Drivers allocate a block of memory + * + * Input Parameters: + * size - memory size + * + * Returned Value: + * Memory pointer + * + ****************************************************************************/ + +IRAM_ATTR void *esp_coex_common_malloc_internal_wrapper(size_t size) +{ + return kmm_malloc(size); +} diff --git a/arch/risc-v/src/esp32c6/esp_wifi_adapter.c b/arch/risc-v/src/esp32c6/esp_wifi_adapter.c new file mode 100644 index 0000000000000..4ba19299c59b2 --- /dev/null +++ b/arch/risc-v/src/esp32c6/esp_wifi_adapter.c @@ -0,0 +1,5569 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c6/esp_wifi_adapter.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "esp_irq.h" +#include "esp_hr_timer.h" + +#include "esp_types.h" +#include "esp_random.h" +#include "esp_mac.h" +#include "esp_intr_alloc.h" +#include "esp_attr.h" +#include "esp_log.h" +#include "esp_event.h" +#include "esp_timer.h" +#include "esp_private/esp_modem_clock.h" +#include "esp_private/wifi_os_adapter.h" +#include "esp_private/wifi.h" +#include "esp_phy_init.h" +#include "soc/rtc_cntl_periph.h" +#include "esp_private/periph_ctrl.h" +#include "esp_private/esp_clk.h" +#include "os.h" +#include "esp_smartconfig.h" +#include "esp_coexist_internal.h" +#include "rom/ets_sys.h" +#include "esp_modem_wrapper.h" + +#if SOC_PM_MODEM_RETENTION_BY_REGDMA +#include "esp_private/esp_regdma.h" +#include "esp_private/sleep_retention.h" +#endif + +#include "esp_wlan.h" +#include "esp_wifi_adapter.h" +#include "esp_wifi_utils.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PHY_RF_MASK ((1 << PHY_BT_MODULE) | (1 << PHY_WIFI_MODULE)) + +#define WIFI_CONNECT_TIMEOUT CONFIG_ESPRESSIF_WIFI_CONNECT_TIMEOUT + +#define ESP_WIFI_11B_MAX_BITRATE 11 +#define ESP_WIFI_11G_MAX_BITRATE 54 +#define ESP_WIFI_11N_MCS7_HT20_BITRATE 72 +#define ESP_WIFI_11N_MCS7_HT40_BITRATE 150 + +#ifndef CONFIG_EXAMPLE_WIFI_LISTEN_INTERVAL +#define CONFIG_EXAMPLE_WIFI_LISTEN_INTERVAL 3 +#endif + +#define DEFAULT_LISTEN_INTERVAL CONFIG_EXAMPLE_WIFI_LISTEN_INTERVAL + +#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal + +#define ets_timer _ETSTIMER_ + +/* CONFIG_POWER_SAVE_MODEM */ + +#if defined(CONFIG_ESP_POWER_SAVE_MIN_MODEM) +# define DEFAULT_PS_MODE WIFI_PS_MIN_MODEM +#elif defined(CONFIG_ESP_POWER_SAVE_MAX_MODEM) +# define DEFAULT_PS_MODE WIFI_PS_MAX_MODEM +#elif defined(CONFIG_ESP_POWER_SAVE_NONE) +# define DEFAULT_PS_MODE WIFI_PS_NONE +#else +# define DEFAULT_PS_MODE WIFI_PS_NONE +#endif + +#define ESP_MAX_PRIORITIES (25) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Wi-Fi event ID */ + +enum wifi_adpt_evt_e +{ + WIFI_ADPT_EVT_SCAN_DONE = 0, + WIFI_ADPT_EVT_STA_START, + WIFI_ADPT_EVT_STA_CONNECT, + WIFI_ADPT_EVT_STA_DISCONNECT, + WIFI_ADPT_EVT_STA_AUTHMODE_CHANGE, + WIFI_ADPT_EVT_STA_STOP, + WIFI_ADPT_EVT_AP_START, + WIFI_ADPT_EVT_AP_STOP, + WIFI_ADPT_EVT_AP_STACONNECTED, + WIFI_ADPT_EVT_AP_STADISCONNECTED, + WIFI_ADPT_EVT_MAX, +}; + +/* Wi-Fi Station state */ + +enum wifi_sta_state +{ + WIFI_STA_STATE_NULL, + WIFI_STA_STATE_START, + WIFI_STA_STATE_CONNECT, + WIFI_STA_STATE_DISCONNECT, + WIFI_STA_STATE_STOP +}; + +/* Wi-Fi interrupt adapter private data */ + +struct irq_adpt +{ + void (*func)(void *arg); /* Interrupt callback function */ + void *arg; /* Interrupt private data */ +}; + +/* Wi-Fi message queue private data */ + +struct mq_adpt +{ + struct file mq; /* Message queue handle */ + uint32_t msgsize; /* Message size */ + char name[16]; /* Message queue name */ +}; + +/* Wi-Fi time private data */ + +struct time_adpt +{ + time_t sec; /* Second value */ + suseconds_t usec; /* Micro second value */ +}; + +/* Wi-Fi event private data */ + +struct evt_adpt +{ + sq_entry_t entry; /* Sequence entry */ + int32_t id; /* Event ID */ + uint8_t buf[0]; /* Event private data */ +}; + +/* Wi-Fi event notification private data */ + +struct wifi_notify +{ + bool assigned; /* Flag indicate if it is used */ + pid_t pid; /* Signal's target thread PID */ + struct sigevent event; /* Signal event private data */ + struct sigwork_s work; /* Signal work private data */ +}; + +/* Wi-Fi NVS private data */ + +struct nvs_adpt +{ + char *index_name; +}; + +/* Wi-Fi event callback function */ + +typedef void (*wifi_evt_cb_t)(void *p); + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Private functions order is defined as: + * - A first block containing the functions in the same order as of the + * ESP-IDF' corresponding `esp_adapter.c` to ease comparison; + * - A second block of auxiliary functions block ordered by ascending; + */ + +/* First block of functions */ + +static void *wifi_zalloc_wrapper(size_t size); +static void *wifi_create_queue(int queue_len, int item_size); +static void wifi_delete_queue(wifi_static_queue_t *queue); +static void *wifi_create_queue_wrapper(int queue_len, int item_size); +static void wifi_delete_queue_wrapper(void *queue); +static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, + uint32_t intr_num, int32_t intr_prio); +static void clear_intr_wrapper(uint32_t intr_source, uint32_t intr_num); +static void set_isr_wrapper(int32_t n, void *f, void *arg); +static void enable_intr_wrapper(uint32_t intr_mask); +static void disable_intr_wrapper(uint32_t intr_mask); +static bool is_from_isr_wrapper(void); +static void wifi_thread_semphr_free(void *data); +static void *wifi_thread_semphr_get_wrapper(void); +static void *recursive_mutex_create_wrapper(void); +static void *mutex_create_wrapper(void); +static void mutex_delete_wrapper(void *mutex); +static int32_t mutex_lock_wrapper(void *mutex); +static int32_t mutex_unlock_wrapper(void *mutex); +static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size); +static int32_t queue_send_wrapper(void *queue, + void *item, + uint32_t block_time_tick); +static int32_t queue_send_from_isr_wrapper(void *queue, + void *item, + void *hptw); +static int32_t queue_send_to_back_wrapper(void *queue, + void *item, + uint32_t block_time_tick); +static int32_t queue_send_to_front_wrapper(void *queue, + void *item, + uint32_t block_time_tick); +static int32_t queue_recv_wrapper(void *queue, + void *item, + uint32_t block_time_tick); +static uint32_t event_group_wait_bits_wrapper(void *event, + uint32_t bits_to_wait_for, + int clear_on_exit, + int wait_for_all_bits, + uint32_t block_time_tick); +static int32_t task_create_pinned_to_core_wrapper(void *task_func, + const char *name, + uint32_t stack_depth, + void *param, + uint32_t prio, + void *task_handle, + uint32_t core_id); +static int32_t task_create_wrapper(void *task_func, + const char *name, + uint32_t stack_depth, + void *param, + uint32_t prio, + void *task_handle); +static int32_t task_ms_to_tick_wrapper(uint32_t ms); +static int32_t task_get_max_priority_wrapper(void); +int32_t esp_event_post_wrapper(const char *event_base, + int32_t event_id, + void *event_data, + size_t event_data_size, + uint32_t ticks); +static void wifi_apb80m_request_wrapper(void); +static void wifi_apb80m_release_wrapper(void); +static void timer_arm_wrapper(void *timer, uint32_t tmout, bool repeat); +static void wifi_reset_mac_wrapper(void); +static void wifi_clock_enable_wrapper(void); +static void wifi_clock_disable_wrapper(void); +static int get_time_wrapper(void *t); +static void *realloc_internal_wrapper(void *ptr, size_t size); +static void *calloc_internal_wrapper(size_t n, size_t size); +static void *zalloc_internal_wrapper(size_t size); +static int nvs_open_wrapper(const char *name, unsigned int open_mode, + uint32_t *out_handle); +static void esp_log_writev_wrapper(unsigned int level, + const char *tag, + const char *format, + va_list args); +static void esp_log_write_wrapper(unsigned int level, + const char *tag, + const char *format, ...); +static int esp_read_mac_wrapper(uint8_t *mac, unsigned int type); +static int coex_init_wrapper(void); +static void coex_deinit_wrapper(void); +static int coex_enable_wrapper(void); +static void coex_disable_wrapper(void); +static uint32_t coex_status_get_wrapper(void); +static int coex_wifi_request_wrapper(uint32_t event, + uint32_t latency, + uint32_t duration); +static int coex_wifi_release_wrapper(uint32_t event); +static int coex_wifi_channel_set_wrapper(uint8_t primary, + uint8_t secondary); +static int coex_event_duration_get_wrapper(uint32_t event, + uint32_t *duration); +static int coex_pti_get_wrapper(uint32_t event, uint8_t *pti); +static void coex_schm_status_bit_clear_wrapper(uint32_t type, + uint32_t status); +static void coex_schm_status_bit_set_wrapper(uint32_t type, + uint32_t status); +static int coex_schm_interval_set_wrapper(uint32_t interval); +static uint32_t coex_schm_interval_get_wrapper(void); +static uint8_t coex_schm_curr_period_get_wrapper(void); +static void *coex_schm_curr_phase_get_wrapper(void); +static int coex_register_start_cb_wrapper(int (* cb)(void)); +static int coex_schm_process_restart_wrapper(void); +static int coex_schm_register_cb_wrapper(int type, int(*cb)(int)); +static void esp_empty_wrapper(void); + +/* Second block of functions + * These functions are auxiliary functions that are used by the first block + * of functions or software adapters for the Wi-Fi driver + */ + +static int esp_event_id_map(int event_id); +static void esp_evt_work_cb(void *arg); +static int esp_freq_to_channel(uint16_t freq); +static uint32_t esp_get_free_heap_size(void); +static void *event_group_create_wrapper(void); +static void event_group_delete_wrapper(void *event); +static uint32_t event_group_set_bits_wrapper(void *event, uint32_t bits); +static uint32_t event_group_clear_bits_wrapper(void *event, uint32_t bits); +static int esp_int_adpt_cb(int irq, void *context, void *arg); +static int esp_nvs_commit(uint32_t handle); +static int esp_nvs_erase_key(uint32_t handle, const char *key); +static int esp_nvs_get_blob(uint32_t handle, + const char *key, + void *out_value, + size_t *length); +static int esp_nvs_set_blob(uint32_t handle, + const char *key, + const void *value, + size_t length); +static int esp_nvs_get_i8(uint32_t handle, + const char *key, + int8_t *out_value); +static int esp_nvs_set_i8(uint32_t handle, const char *key, int8_t value); +static int esp_nvs_get_u8(uint32_t handle, + const char *key, + uint8_t *out_value); +static int esp_nvs_set_u8(uint32_t handle, const char *key, uint8_t value); +static int esp_nvs_get_u16(uint32_t handle, + const char *key, + uint16_t *out_value); +static int esp_nvs_set_u16(uint32_t handle, const char *key, uint16_t value); +static void esp_nvs_close(uint32_t handle); +static void esp_update_time(struct timespec *timespec, uint32_t ticks); +static int esp_wifi_auth_trans(uint32_t wifi_auth); +static int esp_wifi_cipher_trans(uint32_t wifi_cipher); +static int esp_wifi_lock(bool lock); +static uint32_t queue_msg_waiting_wrapper(void *queue); +static void task_delay_wrapper(uint32_t tick); +static void task_delete_wrapper(void *task_handle); +static void *task_get_current_task_wrapper(void); +static void vqueue_delete_adapter(void *queue); +static void vsemaphore_delete_adapter(void *semphr); +static void *xqueue_create_adapter(uint32_t queue_len, uint32_t item_size); +static int32_t xqueue_send_adapter(void *queue, + void *item, + uint32_t ticks, + int prio); +void *xsemaphore_create_counting_adapter(uint32_t max, uint32_t init); + +#ifdef CONFIG_PM +extern void wifi_apb80m_request(void); +extern void wifi_apb80m_release(void); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Wi-Fi event private data */ + +static struct work_s g_wifi_evt_work; +static sq_queue_t g_wifi_evt_queue; +static struct wifi_notify g_wifi_notify[WIFI_ADPT_EVT_MAX]; +static mutex_t g_wifiexcl_lock = NXMUTEX_INITIALIZER; + +/* Wi-Fi adapter reference */ + +static int g_wifi_ref; + +#ifdef ESP_WLAN_HAS_STA + +/* If reconnect automatically */ + +static bool g_sta_reconnect; + +/* If Wi-Fi sta starts */ + +static bool g_sta_started; + +/* If Wi-Fi sta connected */ + +static bool g_sta_connected; + +/* Wi-Fi interface configuration */ + +static wifi_config_t g_sta_wifi_cfg; + +#endif /* ESP_WLAN_HAS_STA */ + +#ifdef ESP_WLAN_HAS_SOFTAP + +/* If Wi-Fi SoftAP starts */ + +static bool g_softap_started; + +/* Wi-Fi interface configuration */ + +static wifi_config_t g_softap_wifi_cfg; + +#endif /* ESP_WLAN_HAS_SOFTAP */ + +/* Device specific lock */ + +static spinlock_t g_lock; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Wi-Fi OS adapter data */ + +wifi_osi_funcs_t g_wifi_osi_funcs = +{ + ._version = ESP_WIFI_OS_ADAPTER_VERSION, + ._env_is_chip = esp_coex_common_env_is_chip_wrapper, + ._set_intr = set_intr_wrapper, + ._clear_intr = clear_intr_wrapper, + ._set_isr = set_isr_wrapper, + ._ints_on = enable_intr_wrapper, + ._ints_off = disable_intr_wrapper, + ._is_from_isr = is_from_isr_wrapper, + ._spin_lock_create = esp_coex_common_spin_lock_create_wrapper, + ._spin_lock_delete = free, + ._wifi_int_disable = esp_coex_common_int_disable_wrapper, + ._wifi_int_restore = esp_coex_common_int_restore_wrapper, + ._task_yield_from_isr = esp_coex_common_task_yield_from_isr_wrapper, + ._semphr_create = esp_coex_common_semphr_create_wrapper, + ._semphr_delete = esp_coex_common_semphr_delete_wrapper, + ._semphr_take = esp_coex_common_semphr_take_wrapper, + ._semphr_give = esp_coex_common_semphr_give_wrapper, + ._wifi_thread_semphr_get = wifi_thread_semphr_get_wrapper, + ._mutex_create = mutex_create_wrapper, + ._recursive_mutex_create = recursive_mutex_create_wrapper, + ._mutex_delete = mutex_delete_wrapper, + ._mutex_lock = mutex_lock_wrapper, + ._mutex_unlock = mutex_unlock_wrapper, + ._queue_create = queue_create_wrapper, + ._queue_delete = vqueue_delete_adapter, + ._queue_send = queue_send_wrapper, + ._queue_send_from_isr = queue_send_from_isr_wrapper, + ._queue_send_to_back = queue_send_to_back_wrapper, + ._queue_send_to_front = queue_send_to_front_wrapper, + ._queue_recv = queue_recv_wrapper, + ._queue_msg_waiting = queue_msg_waiting_wrapper, + ._event_group_create = event_group_create_wrapper, + ._event_group_delete = event_group_delete_wrapper, + ._event_group_set_bits = event_group_set_bits_wrapper, + ._event_group_clear_bits = event_group_clear_bits_wrapper, + ._event_group_wait_bits = event_group_wait_bits_wrapper, + ._task_create_pinned_to_core = task_create_pinned_to_core_wrapper, + ._task_create = task_create_wrapper, + ._task_delete = task_delete_wrapper, + ._task_delay = task_delay_wrapper, + ._task_ms_to_tick = task_ms_to_tick_wrapper, + ._task_get_current_task = task_get_current_task_wrapper, + ._task_get_max_priority = task_get_max_priority_wrapper, + ._malloc = malloc, + ._free = free, + ._event_post = esp_event_post_wrapper, + ._get_free_heap_size = esp_get_free_heap_size, + ._rand = esp_random, + ._dport_access_stall_other_cpu_start_wrap = + esp_empty_wrapper, + ._dport_access_stall_other_cpu_end_wrap = + esp_empty_wrapper, + ._wifi_apb80m_request = wifi_apb80m_request_wrapper, + ._wifi_apb80m_release = wifi_apb80m_release_wrapper, + ._phy_disable = esp_phy_disable, + ._phy_enable = esp_phy_enable, + ._phy_update_country_info = esp_phy_update_country_info, + ._read_mac = esp_read_mac_wrapper, + ._timer_arm = timer_arm_wrapper, + ._timer_disarm = esp_coex_common_timer_disarm_wrapper, + ._timer_done = esp_coex_common_timer_done_wrapper, + ._timer_setfn = esp_coex_common_timer_setfn_wrapper, + ._timer_arm_us = esp_coex_common_timer_arm_us_wrapper, + ._wifi_reset_mac = wifi_reset_mac_wrapper, + ._wifi_clock_enable = wifi_clock_enable_wrapper, + ._wifi_clock_disable = wifi_clock_disable_wrapper, + ._wifi_rtc_enable_iso = esp_empty_wrapper, + ._wifi_rtc_disable_iso = esp_empty_wrapper, + ._esp_timer_get_time = (int64_t(*)(void))esp_hr_timer_time_us, + ._nvs_set_i8 = esp_nvs_set_i8, + ._nvs_get_i8 = esp_nvs_get_i8, + ._nvs_set_u8 = esp_nvs_set_u8, + ._nvs_get_u8 = esp_nvs_get_u8, + ._nvs_set_u16 = esp_nvs_set_u16, + ._nvs_get_u16 = esp_nvs_get_u16, + ._nvs_open = nvs_open_wrapper, + ._nvs_close = esp_nvs_close, + ._nvs_commit = esp_nvs_commit, + ._nvs_set_blob = esp_nvs_set_blob, + ._nvs_get_blob = esp_nvs_get_blob, + ._nvs_erase_key = esp_nvs_erase_key, + ._get_random = os_get_random, + ._get_time = get_time_wrapper, + ._random = os_random, + ._slowclk_cal_get = esp_coex_common_clk_slowclk_cal_get_wrapper, + ._log_write = esp_log_write_wrapper, + ._log_writev = esp_log_writev_wrapper, + ._log_timestamp = esp_log_timestamp, + ._malloc_internal = esp_coex_common_malloc_internal_wrapper, + ._realloc_internal = realloc_internal_wrapper, + ._calloc_internal = calloc_internal_wrapper, + ._zalloc_internal = zalloc_internal_wrapper, + ._wifi_malloc = wifi_malloc, + ._wifi_realloc = wifi_realloc, + ._wifi_calloc = wifi_calloc, + ._wifi_zalloc = wifi_zalloc_wrapper, + ._wifi_create_queue = wifi_create_queue_wrapper, + ._wifi_delete_queue = wifi_delete_queue_wrapper, + ._coex_init = coex_init_wrapper, + ._coex_deinit = coex_deinit_wrapper, + ._coex_enable = coex_enable_wrapper, + ._coex_disable = coex_disable_wrapper, + ._coex_status_get = coex_status_get_wrapper, + ._coex_wifi_request = coex_wifi_request_wrapper, + ._coex_wifi_release = coex_wifi_release_wrapper, + ._coex_wifi_channel_set = coex_wifi_channel_set_wrapper, + ._coex_event_duration_get = coex_event_duration_get_wrapper, + ._coex_pti_get = coex_pti_get_wrapper, + ._coex_schm_status_bit_clear = coex_schm_status_bit_clear_wrapper, + ._coex_schm_status_bit_set = coex_schm_status_bit_set_wrapper, + ._coex_schm_interval_set = coex_schm_interval_set_wrapper, + ._coex_schm_interval_get = coex_schm_interval_get_wrapper, + ._coex_schm_curr_period_get = coex_schm_curr_period_get_wrapper, + ._coex_schm_curr_phase_get = coex_schm_curr_phase_get_wrapper, + ._coex_register_start_cb = coex_register_start_cb_wrapper, + ._coex_schm_process_restart = coex_schm_process_restart_wrapper, + ._coex_schm_register_cb = coex_schm_register_cb_wrapper, + ._magic = ESP_WIFI_OS_ADAPTER_MAGIC, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Private functions order is defined as: + * - A first block containing the functions in the same order as of the + * ESP-IDF' corresponding `esp_adapter.c` to ease comparison; + * - A second block of auxiliary functions block ordered by ascending; + */ + +/* First block of functions */ + +/**************************************************************************** + * Name: wifi_zalloc_wrapper + * + * Description: + * Applications allocate a block of memory and clear it with 0 + * + * Input Parameters: + * size - memory size + * + * Returned Value: + * New memory pointer + * + ****************************************************************************/ + +static IRAM_ATTR void *wifi_zalloc_wrapper(size_t size) +{ + return zalloc(size); +} + +/**************************************************************************** + * Name: wifi_create_queue + * + * Description: + * Create Wi-Fi static message queue + * + * Input Parameters: + * queue_len - queue message number + * item_size - message size + * + * Returned Value: + * Wi-Fi static message queue data pointer + * + ****************************************************************************/ + +static void *wifi_create_queue(int queue_len, int item_size) +{ + wifi_static_queue_t *wifi_queue; + + wifi_queue = kmm_malloc(sizeof(wifi_static_queue_t)); + if (!wifi_queue) + { + wlerr("Failed to kmm_malloc\n"); + return NULL; + } + + wifi_queue->handle = xqueue_create_adapter(queue_len, item_size); + if (!wifi_queue->handle) + { + wlerr("Failed to create queue\n"); + kmm_free(wifi_queue); + return NULL; + } + + return wifi_queue; +} + +/**************************************************************************** + * Name: wifi_delete_queue + * + * Description: + * Delete message queue + * + * Input Parameters: + * queue - Message queue data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wifi_delete_queue(wifi_static_queue_t *queue) +{ + if (queue) + { + vqueue_delete_adapter(queue->handle); + kmm_free(queue); + } +} + +/**************************************************************************** + * Name: wifi_create_queue_wrapper + * + * Description: + * This function creates a new queue for Wi-Fi operations. It is a wrapper + * around the wifi_create_queue function, providing a consistent interface + * for the Wi-Fi module. + * + * Input Parameters: + * queue_len - The maximum number of items that the queue can hold. + * item_size - The size of each item in the queue. + * + * Returned Value: + * A pointer to the newly created queue, or NULL if the operation failed. + * + ****************************************************************************/ + +static void *wifi_create_queue_wrapper(int queue_len, int item_size) +{ + return wifi_create_queue(queue_len, item_size); +} + +/**************************************************************************** + * Name: wifi_delete_queue_wrapper + * + * Description: + * Delete Wi-Fi static message queue + * + * Input Parameters: + * queue - Wi-Fi static message queue data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wifi_delete_queue_wrapper(void *queue) +{ + wifi_delete_queue(queue); +} + +/**************************************************************************** + * Name: set_intr_wrapper + * + * Description: + * Do nothing + * + * Input Parameters: + * cpu_no - The CPU which the interrupt number belongs. + * intr_source - The interrupt hardware source number. + * intr_num - The interrupt number CPU. + * intr_prio - The interrupt priority. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, + uint32_t intr_num, int32_t intr_prio) +{ + wlinfo("cpu_no=%" PRId32 ", intr_source=%" PRIu32 + ", intr_num=%" PRIu32 ", intr_prio=%" PRId32 "\n", + cpu_no, intr_source, intr_num, intr_prio); + + esp_route_intr(intr_source, intr_num, intr_prio, ESP_IRQ_TRIGGER_LEVEL); + esp_set_irq(ESP_SOURCE2IRQ(intr_source), intr_num); +} + +/**************************************************************************** + * Name: clear_intr_wrapper + * + * Description: + * This function is intended to clear a specific interrupt. However, this + * functionality is not supported in the current implementation. + * + * Input Parameters: + * intr_source - The source of the interrupt. + * intr_num - The number of the interrupt. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR clear_intr_wrapper(uint32_t intr_source, + uint32_t intr_num) +{ +} + +/**************************************************************************** + * Name: set_isr_wrapper + * + * Description: + * Register interrupt function + * + * Input Parameters: + * n - CPU interrupt number + * f - Interrupt function + * arg - Function private data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void set_isr_wrapper(int32_t n, void *f, void *arg) +{ + int ret; + uint32_t tmp; + struct irq_adpt *adapter; + int irq = esp_get_irq(n); + + wlinfo("n=%ld f=%p arg=%p irq=%d\n", n, f, arg, irq); + + if (g_irqvector[irq].handler && + g_irqvector[irq].handler != irq_unexpected_isr) + { + wlinfo("irq=%d has been set handler=%p\n", irq, + g_irqvector[irq].handler); + return; + } + + tmp = sizeof(struct irq_adpt); + adapter = kmm_malloc(tmp); + if (!adapter) + { + wlerr("Failed to alloc %ld memory\n", tmp); + PANIC(); + return; + } + + adapter->func = f; + adapter->arg = arg; + + ret = irq_attach(irq, esp_int_adpt_cb, adapter); + if (ret) + { + wlerr("Failed to attach IRQ %d\n", irq); + PANIC(); + return; + } +} + +/**************************************************************************** + * Name: enable_intr_wrapper + * + * Description: + * Enable a specific Wi-Fi interrupt. + * + * Input Parameters: + * intr_mask - A mask where the bit corresponding to the interrupt to be + * enabled is set. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void enable_intr_wrapper(uint32_t intr_mask) +{ + int cpuint = __builtin_ffs(intr_mask) - 1; + int irq = esp_get_irq(cpuint); + + wlinfo("intr_mask=%08lx cpuint=%d irq=%d\n", intr_mask, cpuint, irq); + + up_enable_irq(irq); +} + +/**************************************************************************** + * Name: disable_intr_wrapper + * + * Description: + * Disable a specific Wi-Fi interrupt. + * + * Input Parameters: + * intr_mask - A mask where the bit corresponding to the interrupt to be + * disabled is set. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void disable_intr_wrapper(uint32_t intr_mask) +{ + int cpuint = __builtin_ffs(intr_mask) - 1; + int irq = esp_get_irq(cpuint); + + wlinfo("intr_mask=%08lx cpuint=%d irq=%d\n", intr_mask, cpuint, irq); + + up_disable_irq(irq); +} + +/**************************************************************************** + * Name: is_from_isr_wrapper + * + * Description: + * Check current is in interrupt + * + * Input Parameters: + * None + * + * Returned Value: + * true if in interrupt or false if not + * + ****************************************************************************/ + +static bool IRAM_ATTR is_from_isr_wrapper(void) +{ + return up_interrupt_context(); +} + +/**************************************************************************** + * Name: wifi_thread_semphr_free + * + * Description: + * Delete thread self's semaphore + * + * Input Parameters: + * data - Semaphore data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wifi_thread_semphr_free(void *data) +{ + void *sem = (void *)data; + + if (sem) + { + vsemaphore_delete_adapter(sem); + } +} + +/**************************************************************************** + * Name: wifi_thread_semphr_get_wrapper + * + * Description: + * Get thread self's semaphore + * + * Input Parameters: + * None + * + * Returned Value: + * Semaphore data pointer + * + ****************************************************************************/ + +static void *wifi_thread_semphr_get_wrapper(void) +{ + static int wifi_task_key = -1; + int ret; + void *sem; + + if (wifi_task_key < 0) + { + ret = task_tls_alloc(wifi_thread_semphr_free); + if (ret < 0) + { + wlerr("Failed to create task local key\n"); + return NULL; + } + + wifi_task_key = ret; + } + + sem = (void *)task_tls_get_value(wifi_task_key); + if (sem == NULL) + { + sem = xsemaphore_create_counting_adapter(1, 0); + if (!sem) + { + wlerr("Failed to create semaphore\n"); + return NULL; + } + + ret = task_tls_set_value(wifi_task_key, (uintptr_t)sem); + if (ret != OK) + { + wlerr("Failed to save semaphore on task local storage: %d\n", ret); + vsemaphore_delete_adapter(sem); + return NULL; + } + } + + return sem; +} + +/**************************************************************************** + * Name: recursive_mutex_create_wrapper + * + * Description: + * Create recursive mutex + * + * Input Parameters: + * None + * + * Returned Value: + * Recursive mutex data pointer + * + ****************************************************************************/ + +static void *recursive_mutex_create_wrapper(void) +{ + int ret; + pthread_mutex_t *mutex; + pthread_mutexattr_t attr; + int tmp; + + ret = pthread_mutexattr_init(&attr); + if (ret) + { + wlerr("Failed to initialize attr error=%d\n", ret); + return NULL; + } + + ret = pthread_mutexattr_settype(&attr, PTHREAD_MUTEX_RECURSIVE); + if (ret) + { + wlerr("Failed to set attr type error=%d\n", ret); + return NULL; + } + + tmp = sizeof(pthread_mutex_t); + mutex = kmm_malloc(tmp); + if (!mutex) + { + wlerr("Failed to alloc %d memory\n", tmp); + return NULL; + } + + ret = pthread_mutex_init(mutex, &attr); + if (ret) + { + wlerr("Failed to initialize mutex error=%d\n", ret); + kmm_free(mutex); + return NULL; + } + + return mutex; +} + +/**************************************************************************** + * Name: mutex_create_wrapper + * + * Description: + * Create mutex + * + * Input Parameters: + * None + * + * Returned Value: + * Mutex data pointer + * + ****************************************************************************/ + +static void *mutex_create_wrapper(void) +{ + int ret; + pthread_mutex_t *mutex; + int tmp; + + tmp = sizeof(pthread_mutex_t); + mutex = kmm_malloc(tmp); + if (!mutex) + { + wlerr("Failed to alloc %d memory\n", tmp); + return NULL; + } + + ret = pthread_mutex_init(mutex, NULL); + if (ret) + { + wlerr("Failed to initialize mutex error=%d\n", ret); + kmm_free(mutex); + return NULL; + } + + return mutex; +} + +/**************************************************************************** + * Name: mutex_delete_wrapper + * + * Description: + * Delete mutex + * + * Input Parameters: + * mutex - mutex data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void mutex_delete_wrapper(void *mutex) +{ + pthread_mutex_t *mutex_data = (pthread_mutex_t *)mutex; + + pthread_mutex_destroy(mutex_data); + kmm_free(mutex_data); +} + +/**************************************************************************** + * Name: mutex_lock_wrapper + * + * Description: + * Lock mutex + * + * Input Parameters: + * mutex - mutex data pointer + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t IRAM_ATTR mutex_lock_wrapper(void *mutex) +{ + int ret; + pthread_mutex_t *mutex_data = (pthread_mutex_t *)mutex; + + ret = pthread_mutex_lock(mutex_data); + if (ret) + { + wlerr("Failed to lock mutex error=%d\n", ret); + } + + return nuttx_err_to_freertos(ret); +} + +/**************************************************************************** + * Name: mutex_unlock_wrapper + * + * Description: + * Unlock mutex + * + * Input Parameters: + * mutex - mutex data pointer + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t IRAM_ATTR mutex_unlock_wrapper(void *mutex) +{ + int ret; + pthread_mutex_t *mutex_data = (pthread_mutex_t *)mutex; + + ret = pthread_mutex_unlock(mutex_data); + if (ret) + { + wlerr("Failed to unlock mutex error=%d\n", ret); + } + + return nuttx_err_to_freertos(ret); +} + +/**************************************************************************** + * Name: queue_create_wrapper + * + * Description: + * This function creates a new queue adapter with the specified length and + * item size. It is a wrapper around the xqueue_create_adapter function. + * + * Input Parameters: + * queue_len - The maximum number of items that the queue can hold. + * item_size - The size of each item in the queue. + * + * Returned Value: + * A pointer to the newly created queue adapter, or NULL if the operation + * failed. + * + ****************************************************************************/ + +static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size) +{ + return xqueue_create_adapter(queue_len, item_size); +} + +/**************************************************************************** + * Name: queue_send_wrapper + * + * Description: + * Send message of low priority to queue within a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * ticks - Wait ticks + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t queue_send_wrapper(void *queue, void *item, uint32_t ticks) +{ + return xqueue_send_adapter(queue, item, ticks, 0); +} + +/**************************************************************************** + * Name: queue_send_from_isr_wrapper + * + * Description: + * Send message of low priority to queue in ISR within + * a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * hptw - Unused. + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t IRAM_ATTR queue_send_from_isr_wrapper(void *queue, + void *item, + void *hptw) +{ + *(int *)hptw = 0; + + return xqueue_send_adapter(queue, item, 0, 0); +} + +/**************************************************************************** + * Name: queue_send_to_back_wrapper + * + * Description: + * Send message of low priority to queue within a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * ticks - Wait ticks + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t queue_send_to_back_wrapper(void *queue, + void *item, + uint32_t ticks) +{ + return xqueue_send_adapter(queue, item, ticks, 0); +} + +/**************************************************************************** + * Name: queue_send_to_front_wrapper + * + * Description: + * Send message of high priority to queue within a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * ticks - Wait ticks + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t queue_send_to_front_wrapper(void *queue, + void *item, + uint32_t ticks) +{ + return xqueue_send_adapter(queue, item, ticks, 1); +} + +/**************************************************************************** + * Name: queue_recv_wrapper + * + * Description: + * Receive message from queue within a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * ticks - Wait ticks + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t queue_recv_wrapper(void *queue, void *item, uint32_t ticks) +{ + ssize_t ret; + struct timespec timeout; + unsigned int prio; + struct mq_adpt *mq_adpt = (struct mq_adpt *)queue; + + if (ticks == OSI_FUNCS_TIME_BLOCKING) + { + ret = file_mq_receive(&mq_adpt->mq, (char *)item, + mq_adpt->msgsize, &prio); + if (ret < 0) + { + wlerr("Failed to receive from mqueue error=%d\n", ret); + } + } + else + { + ret = clock_gettime(CLOCK_REALTIME, &timeout); + if (ret < 0) + { + wlerr("Failed to get time\n"); + return false; + } + + if (ticks) + { + esp_update_time(&timeout, ticks); + } + + ret = file_mq_timedreceive(&mq_adpt->mq, (char *)item, + mq_adpt->msgsize, &prio, &timeout); + if (ret < 0) + { + wlerr("Failed to timedreceive from mqueue error=%d\n", + ret); + } + } + + return ret > 0 ? true : false; +} + +/**************************************************************************** + * Name: event_group_wait_bits_wrapper + * + * Description: + * Don't support + * + ****************************************************************************/ + +static uint32_t event_group_wait_bits_wrapper(void *event, + uint32_t bits_to_wait_for, + int clear_on_exit, + int wait_for_all_bits, + uint32_t block_time_tick) +{ + DEBUGPANIC(); + + return false; +} + +/**************************************************************************** + * Name: task_create_pinned_to_core_wrapper + * + * Description: + * Create task and bind it to target CPU, the task will run when it + * is created + * + * Input Parameters: + * entry - Task entry + * name - Task name + * stack_depth - Task stack size + * param - Task private data + * prio - Task priority + * task_handle - Task handle pointer which is used to pause, resume + * and delete the task + * core_id - CPU which the task runs in + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t task_create_pinned_to_core_wrapper(void *entry, + const char *name, + uint32_t stack_depth, + void *param, + uint32_t prio, + void *task_handle, + uint32_t core_id) +{ + int pid; +#ifdef CONFIG_SMP + int ret; + cpu_set_t cpuset; +#endif + uint32_t target_prio = prio; + + if (target_prio < ESP_MAX_PRIORITIES) + { + target_prio += task_get_max_priority_wrapper() - ESP_MAX_PRIORITIES; + } + + pid = kthread_create(name, target_prio, stack_depth, entry, + (char * const *)param); + if (pid > 0) + { + if (task_handle != NULL) + { + *((int *)task_handle) = pid; + } + +#ifdef CONFIG_SMP + if (core_id < CONFIG_SMP_NCPUS) + { + CPU_ZERO(&cpuset); + CPU_SET(core_id, &cpuset); + ret = nxsched_set_affinity(pid, sizeof(cpuset), &cpuset); + if (ret) + { + wlerr("Failed to set affinity error=%d\n", ret); + return false; + } + } +#endif + } + else + { + wlerr("Failed to create task\n"); + } + + return pid > 0; +} + +/**************************************************************************** + * Name: task_create_wrapper + * + * Description: + * Create task and the task will run when it is created + * + * Input Parameters: + * entry - Task entry + * name - Task name + * stack_depth - Task stack size + * param - Task private data + * prio - Task priority + * task_handle - Task handle pointer which is used to pause, resume + * and delete the task + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t task_create_wrapper(void *entry, + const char *name, + uint32_t stack_depth, + void *param, + uint32_t prio, + void *task_handle) +{ + return task_create_pinned_to_core_wrapper(entry, + name, + stack_depth, + param, + prio, + task_handle, + UINT32_MAX); +} + +/**************************************************************************** + * Name: task_ms_to_tick_wrapper + * + * Description: + * This function converts a duration from milliseconds to system ticks. + * It is a wrapper around the NuttX MSEC2TICK macro. + * + * Input Parameters: + * ms - The duration in milliseconds. + * + * Returned Value: + * The duration in system ticks. + * + ****************************************************************************/ + +static int32_t task_ms_to_tick_wrapper(uint32_t ms) +{ + return MSEC2TICK(ms); +} + +/**************************************************************************** + * Name: task_get_max_priority_wrapper + * + * Description: + * Get OS task maximum priority + * + * Input Parameters: + * None + * + * Returned Value: + * Task maximum priority + * + ****************************************************************************/ + +static int32_t task_get_max_priority_wrapper(void) +{ + return SCHED_PRIORITY_MAX; +} + +/**************************************************************************** + * Name: esp_event_post_wrapper + * + * Description: + * Active work queue and let the work to process the cached event + * + * Input Parameters: + * event_base - Event set name + * event_id - Event ID + * event_data - Event private data + * event_data_size - Event data size + * ticks - Waiting system ticks + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +int32_t esp_event_post_wrapper(const char *event_base, + int32_t event_id, + void *event_data, + size_t event_data_size, + uint32_t ticks) +{ + size_t size; + int32_t id; + irqstate_t flags; + struct evt_adpt *evt_adpt; + + wlinfo("Event: base=%s id=%ld data=%p data_size=%d ticks=%lu\n", + event_base, event_id, event_data, event_data_size, ticks); + + id = esp_event_id_map(event_id); + if (id < 0) + { + wlinfo("No process event %ld\n", event_id); + return -1; + } + + size = event_data_size + sizeof(struct evt_adpt); + evt_adpt = kmm_malloc(size); + if (!evt_adpt) + { + wlerr("Failed to alloc %d memory\n", size); + return -1; + } + + evt_adpt->id = id; + memcpy(evt_adpt->buf, event_data, event_data_size); + + flags = spin_lock_irqsave(&g_lock); + sq_addlast(&evt_adpt->entry, &g_wifi_evt_queue); + spin_unlock_irqrestore(&g_lock, flags); + + work_queue(LPWORK, &g_wifi_evt_work, esp_evt_work_cb, NULL, 0); + + return 0; +} + +/**************************************************************************** + * Name: wifi_apb80m_request_wrapper + * + * Description: + * This function acquires the Wi-Fi lock in auto-sleep mode. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR wifi_apb80m_request_wrapper(void) +{ +#ifdef CONFIG_PM + wifi_apb80m_request(); +#endif +} + +/**************************************************************************** + * Name: wifi_apb80m_release_wrapper + * + * Description: + * This function releases the Wi-Fi lock in auto-sleep mode. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR wifi_apb80m_release_wrapper(void) +{ +#ifdef CONFIG_PM + wifi_apb80m_release(); +#endif +} + +/**************************************************************************** + * Name: timer_arm_wrapper + * + * Description: + * Set timer timeout period and repeat flag + * + * Input Parameters: + * ptimer - timer data pointer + * ms - millim seconds + * repeat - true: run cycle, false: run once + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR timer_arm_wrapper(void *ptimer, + uint32_t tmout, + bool repeat) +{ + ets_timer_arm(ptimer, tmout, repeat); +} + +/**************************************************************************** + * Name: wifi_reset_mac_wrapper + * + * Description: + * Reset Wi-Fi hardware MAC + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wifi_reset_mac_wrapper(void) +{ + modem_clock_module_mac_reset(PERIPH_WIFI_MODULE); +} + +/**************************************************************************** + * Name: wifi_clock_enable_wrapper + * + * Description: + * Enable Wi-Fi clock + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wifi_clock_enable_wrapper(void) +{ + wifi_module_enable(); +} + +/**************************************************************************** + * Name: wifi_clock_disable_wrapper + * + * Description: + * Disable Wi-Fi clock + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void wifi_clock_disable_wrapper(void) +{ + wifi_module_disable(); +} + +/**************************************************************************** + * Name: get_time_wrapper + * + * Description: + * Get std C time + * + * Input Parameters: + * t - buffer to store time of type timeval + * + * Returned Value: + * Zero (OK) on success; -1 is returned on failure with the errno variable + * set appropriately. + * + ****************************************************************************/ + +static int get_time_wrapper(void *t) +{ + return os_get_time(t); +} + +/**************************************************************************** + * Name: realloc_internal_wrapper + * + * Description: + * Drivers allocate a block of memory by old memory block + * + * Input Parameters: + * ptr - old memory pointer + * size - memory size + * + * Returned Value: + * New memory pointer + * + ****************************************************************************/ + +static IRAM_ATTR void *realloc_internal_wrapper(void *ptr, size_t size) +{ + return kmm_realloc(ptr, size); +} + +/**************************************************************************** + * Name: calloc_internal_wrapper + * + * Description: + * Drivers allocate some continuous blocks of memory + * + * Input Parameters: + * n - memory block number + * size - memory block size + * + * Returned Value: + * New memory pointer + * + ****************************************************************************/ + +static IRAM_ATTR void *calloc_internal_wrapper(size_t n, size_t size) +{ + return kmm_calloc(n, size); +} + +/**************************************************************************** + * Name: zalloc_internal_wrapper + * + * Description: + * Drivers allocate a block of memory and clear it with 0 + * + * Input Parameters: + * size - memory size + * + * Returned Value: + * New memory pointer + * + ****************************************************************************/ + +static IRAM_ATTR void *zalloc_internal_wrapper(size_t size) +{ + return kmm_zalloc(size); +} + +/**************************************************************************** + * Name: nvs_open_wrapper + * + * Description: + * Create a file system storage data object + * + * Input Parameters: + * name - Storage index + * open_mode - Storage mode + * out_handle - Storage handle + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int nvs_open_wrapper(const char *name, + unsigned int open_mode, + uint32_t *out_handle) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_log_writev_wrapper + * + * Description: + * Output log with by format string and its arguments + * + * Input Parameters: + * level - log level, no mean here + * tag - log TAG, no mean here + * format - format string + * args - arguments list + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_log_writev_wrapper(unsigned int level, + const char *tag, + const char *format, + va_list args) +{ + esp_log_level_t max_level; + +#if defined (CONFIG_DEBUG_WIRELESS_INFO) + max_level = ESP_LOG_VERBOSE; +#elif defined (CONFIG_DEBUG_WIRELESS_WARN) + max_level = ESP_LOG_WARN; +#elif defined (CONFIG_DEBUG_WIRELESS_ERROR) + max_level = ESP_LOG_ERROR; +#else + max_level = ESP_LOG_NONE; +#endif + + if (level <= max_level) + { + esp_log_writev(level, tag, format, args); + } +} + +/**************************************************************************** + * Name: esp_log_write_wrapper + * + * Description: + * Output log with by format string and its arguments + * + * Input Parameters: + * level - log level, no mean here + * tag - log TAG, no mean here + * format - format string + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_log_write_wrapper(unsigned int level, + const char *tag, + const char *format, ...) +{ + esp_log_level_t max_level; + +#if defined (CONFIG_DEBUG_WIRELESS_INFO) + max_level = ESP_LOG_VERBOSE; +#elif defined (CONFIG_DEBUG_WIRELESS_WARN) + max_level = ESP_LOG_WARN; +#elif defined (CONFIG_DEBUG_WIRELESS_ERROR) + max_level = ESP_LOG_ERROR; +#else + max_level = ESP_LOG_NONE; +#endif + + if (level <= max_level) + { + va_list list; + va_start(list, format); + esp_log_writev(level, tag, format, list); + va_end(list); + } +} + +/**************************************************************************** + * Name: esp_read_mac_wrapper + * + * Description: + * Read MAC address from efuse + * + * Input Parameters: + * mac - MAC address buffer pointer + * type - MAC address type + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_read_mac_wrapper(uint8_t *mac, unsigned int type) +{ + return esp_read_mac(mac, type); +} + +/**************************************************************************** + * Name: coex_init_wrapper + * + * Description: + * Init software coexist + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int coex_init_wrapper(void) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_init(); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_deinit_wrapper + * + * Description: + * De-init software coexist + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void coex_deinit_wrapper(void) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + coex_deinit(); +#endif +} + +/**************************************************************************** + * Name: coex_enable_wrapper + * + * Description: + * Enable software coexist + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int coex_enable_wrapper(void) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_enable(); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_disable_wrapper + * + * Description: + * Disable software coexist + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void coex_disable_wrapper(void) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + coex_disable(); +#endif +} + +/**************************************************************************** + * Name: coex_status_get_wrapper + * + * Description: + * Get software coexist status. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static IRAM_ATTR uint32_t coex_status_get_wrapper(void) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_status_get(); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_wifi_request_wrapper + * + * Description: + * Request Wi-Fi coexistence. + * + * Input Parameters: + * event - WiFi event + * latency - WiFi will request coexistence after latency + * duration - duration for WiFi to request coexistence + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int coex_wifi_request_wrapper(uint32_t event, + uint32_t latency, + uint32_t duration) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_wifi_request(event, latency, duration); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_wifi_release_wrapper + * + * Description: + * Release Wi-Fi coexistence. + * + * Input Parameters: + * event - WiFi event + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static IRAM_ATTR int coex_wifi_release_wrapper(uint32_t event) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_wifi_release(event); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_wifi_channel_set_wrapper + * + * Description: + * Set Wi-Fi channel to coexistence module. + * + * Input Parameters: + * primary - WiFi primary channel + * secondary - WiFi secondary channel + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int coex_wifi_channel_set_wrapper(uint8_t primary, uint8_t secondary) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_wifi_channel_set(primary, secondary); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_event_duration_get_wrapper + * + * Description: + * Get coexistence event duration. + * + * Input Parameters: + * event - Coexistence event + * duration - Coexistence event duration + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static IRAM_ATTR int coex_event_duration_get_wrapper(uint32_t event, + uint32_t *duration) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_event_duration_get(event, duration); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_pti_get_wrapper + * + * Description: + * Get coexistence event priority. + * + * Input Parameters: + * event - Coexistence event + * pti - Coexistence event priority + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int coex_pti_get_wrapper(uint32_t event, uint8_t *pti) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_pti_get(event, pti); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_schm_status_bit_clear_wrapper + * + * Description: + * Clear coexistence status. + * + * Input Parameters: + * type - Coexistence status type + * status - Coexistence status + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void coex_schm_status_bit_clear_wrapper(uint32_t type, + uint32_t status) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + coex_schm_status_bit_clear(type, status); +#endif +} + +/**************************************************************************** + * Name: coex_schm_status_bit_set_wrapper + * + * Description: + * Set coexistence status. + * + * Input Parameters: + * type - Coexistence status type + * status - Coexistence status + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + coex_schm_status_bit_set(type, status); +#endif +} + +/**************************************************************************** + * Name: coex_schm_interval_set_wrapper + * + * Description: + * Set coexistence scheme interval. + * + * Input Parameters: + * interval - Coexistence scheme interval + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static IRAM_ATTR int coex_schm_interval_set_wrapper(uint32_t interval) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_schm_interval_set(interval); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_schm_interval_get_wrapper + * + * Description: + * Get coexistence scheme interval. + * + * Input Parameters: + * None + * + * Returned Value: + * Coexistence scheme interval + * + ****************************************************************************/ + +static uint32_t coex_schm_interval_get_wrapper(void) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_schm_interval_get(); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_schm_curr_period_get_wrapper + * + * Description: + * Get current coexistence scheme period. + * + * Input Parameters: + * None + * + * Returned Value: + * Coexistence scheme period + * + ****************************************************************************/ + +static uint8_t coex_schm_curr_period_get_wrapper(void) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_schm_curr_period_get(); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_schm_curr_phase_get_wrapper + * + * Description: + * Get current coexistence scheme phase. + * + * Input Parameters: + * None + * + * Returned Value: + * Coexistence scheme phase + * + ****************************************************************************/ + +static void *coex_schm_curr_phase_get_wrapper(void) +{ +#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE + return coex_schm_curr_phase_get(); +#else + return NULL; +#endif +} + +/**************************************************************************** + * Name: coex_register_start_cb_wrapper + * + * Description: + * Register Wi-Fi callback for coexistence starts. + * + * Input Parameters: + * cb - WiFi callback + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int coex_register_start_cb_wrapper(int (* cb)(void)) +{ +#if CONFIG_SW_COEXIST_ENABLE + return coex_register_start_cb(cb); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_schm_process_restart_wrapper + * + * Description: + * Restart current coexistence scheme. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int coex_schm_process_restart_wrapper(void) +{ +#if CONFIG_SW_COEXIST_ENABLE + return coex_schm_process_restart(); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_schm_register_cb_wrapper + * + * Description: + * Register callback for coexistence scheme. + * + * Input Parameters: + * type - callback type + * cb - callback + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int coex_schm_register_cb_wrapper(int type, int(*cb)(int)) +{ +#if CONFIG_SW_COEXIST_ENABLE + return coex_schm_register_callback(type, cb); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: esp_empty_wrapper + * + * Description: + * This function is an empty wrapper, designed to be used where a function + * pointer is required but no operation is needed. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp_empty_wrapper(void) +{ +} + +/* Second block of functions + * These functions are auxiliary functions that are used by the first block + * of functions or software adapters for the Wi-Fi driver + */ + +/**************************************************************************** + * Name: esp_event_id_map + * + * Description: + * Transform from esp-idf event ID to Wi-Fi adapter event ID + * + * Input Parameters: + * event_id - esp-idf event ID + * + * Returned Value: + * Wi-Fi adapter event ID + * + ****************************************************************************/ + +static int esp_event_id_map(int event_id) +{ + int id; + + switch (event_id) + { + case WIFI_EVENT_SCAN_DONE: + id = WIFI_ADPT_EVT_SCAN_DONE; + break; + +#ifdef ESP_WLAN_HAS_STA + case WIFI_EVENT_STA_START: + id = WIFI_ADPT_EVT_STA_START; + break; + + case WIFI_EVENT_STA_CONNECTED: + id = WIFI_ADPT_EVT_STA_CONNECT; + break; + + case WIFI_EVENT_STA_DISCONNECTED: + id = WIFI_ADPT_EVT_STA_DISCONNECT; + break; + + case WIFI_EVENT_STA_AUTHMODE_CHANGE: + id = WIFI_ADPT_EVT_STA_AUTHMODE_CHANGE; + break; + + case WIFI_EVENT_STA_STOP: + id = WIFI_ADPT_EVT_STA_STOP; + break; +#endif /* ESP_WLAN_HAS_STA */ + +#ifdef ESP_WLAN_HAS_SOFTAP + case WIFI_EVENT_AP_START: + id = WIFI_ADPT_EVT_AP_START; + break; + + case WIFI_EVENT_AP_STOP: + id = WIFI_ADPT_EVT_AP_STOP; + break; + + case WIFI_EVENT_AP_STACONNECTED: + id = WIFI_ADPT_EVT_AP_STACONNECTED; + break; + + case WIFI_EVENT_AP_STADISCONNECTED: + id = WIFI_ADPT_EVT_AP_STADISCONNECTED; + break; +#endif /* ESP_WLAN_HAS_SOFTAP */ + + default: + return -1; + } + + return id; +} + +/**************************************************************************** + * Name: esp_evt_work_cb + * + * Description: + * Process the cached event + * + * Input Parameters: + * arg - No mean + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_evt_work_cb(void *arg) +{ + int ret; + irqstate_t flags; + struct evt_adpt *evt_adpt; + struct wifi_notify *notify; + wifi_ps_type_t ps_type = DEFAULT_PS_MODE; + + while (1) + { + flags = spin_lock_irqsave(&g_lock); + evt_adpt = (struct evt_adpt *)sq_remfirst(&g_wifi_evt_queue); + spin_unlock_irqrestore(&g_lock, flags); + if (!evt_adpt) + { + break; + } + + esp_wifi_lock(true); + + switch (evt_adpt->id) + { + case WIFI_ADPT_EVT_SCAN_DONE: + esp_wifi_scan_event_parse(); + break; + +#ifdef ESP_WLAN_HAS_STA + case WIFI_ADPT_EVT_STA_START: + wlinfo("Wi-Fi sta start\n"); + + g_sta_connected = false; + + ret = esp_wifi_set_ps(ps_type); + if (ret) + { + wlerr("Failed to set power save type\n"); + break; + } + else + { + wlinfo("INFO: Set ps type=%d\n", ps_type); + } + + ret = esp_wifi_get_config(WIFI_IF_STA, &g_sta_wifi_cfg); + if (ret) + { + wlerr("Failed to get Wi-Fi config data ret=%d\n", ret); + } + break; + + case WIFI_ADPT_EVT_STA_CONNECT: + wlinfo("Wi-Fi sta connect\n"); + g_sta_connected = true; + ret = esp_wlan_sta_set_linkstatus(true); + if (ret < 0) + { + wlerr("ERROR: Failed to set Wi-Fi station link status\n"); + } + + break; + + case WIFI_ADPT_EVT_STA_DISCONNECT: + wlinfo("Wi-Fi sta disconnect\n"); + g_sta_connected = false; + ret = esp_wlan_sta_set_linkstatus(false); + if (ret < 0) + { + wlerr("ERROR: Failed to set Wi-Fi station link status\n"); + } + + if (g_sta_reconnect) + { + ret = esp_wifi_connect(); + if (ret) + { + wlerr("Failed to connect AP error=%d\n", ret); + } + } + break; + + case WIFI_ADPT_EVT_STA_STOP: + wlinfo("Wi-Fi sta stop\n"); + g_sta_connected = false; + break; +#endif /* ESP_WLAN_HAS_STA */ + +#ifdef ESP_WLAN_HAS_SOFTAP + case WIFI_ADPT_EVT_AP_START: + wlinfo("INFO: Wi-Fi softap start\n"); + + ret = esp_wifi_set_ps(ps_type); + if (ret) + { + wlerr("Failed to set power save type\n"); + break; + } + else + { + wlinfo("INFO: Set ps type=%d\n", ps_type); + } + + ret = esp_wifi_get_config(WIFI_IF_AP, &g_softap_wifi_cfg); + if (ret) + { + wlerr("Failed to get Wi-Fi config data ret=%d\n", ret); + } + break; + + case WIFI_ADPT_EVT_AP_STOP: + wlinfo("INFO: Wi-Fi softap stop\n"); + break; + + case WIFI_ADPT_EVT_AP_STACONNECTED: + wlinfo("INFO: Wi-Fi station join\n"); + break; + + case WIFI_ADPT_EVT_AP_STADISCONNECTED: + wlinfo("INFO: Wi-Fi station leave\n"); + break; +#endif /* ESP_WLAN_HAS_SOFTAP */ + default: + break; + } + + notify = &g_wifi_notify[evt_adpt->id]; + if (notify->assigned) + { + notify->event.sigev_value.sival_ptr = evt_adpt->buf; + + ret = nxsig_notification(notify->pid, ¬ify->event, + SI_QUEUE, ¬ify->work); + if (ret < 0) + { + wlwarn("nxsig_notification event ID=%ld failed: %d\n", + evt_adpt->id, ret); + } + } + + esp_wifi_lock(false); + + kmm_free(evt_adpt); + } +} + +/**************************************************************************** + * Name: esp_freq_to_channel + * + * Description: + * Converts Wi-Fi frequency to channel. + * + * Input Parameters: + * freq - Wi-Fi frequency + * + * Returned Value: + * Wi-Fi channel + * + ****************************************************************************/ + +static int esp_freq_to_channel(uint16_t freq) +{ + int channel = 0; + if (freq >= 2412 && freq <= 2484) + { + if (freq == 2484) + { + channel = 14; + } + else + { + channel = freq - 2407; + if (channel % 5) + { + return 0; + } + + channel /= 5; + } + + return channel; + } + + if (freq >= 5005 && freq < 5900) + { + if (freq % 5) + { + return 0; + } + + channel = (freq - 5000) / 5; + return channel; + } + + if (freq >= 4905 && freq < 5000) + { + if (freq % 5) + { + return 0; + } + + channel = (freq - 4000) / 5; + return channel; + } + + return 0; +} + +/**************************************************************************** + * Name: esp_get_free_heap_size + * + * Description: + * Get free heap size by byte + * + * Input Parameters: + * None + * + * Returned Value: + * Free heap size + * + ****************************************************************************/ + +static uint32_t esp_get_free_heap_size(void) +{ + struct mallinfo info; + + info = kmm_mallinfo(); + return info.fordblks; +} + +/**************************************************************************** + * Name: event_group_create_wrapper + * + * Description: + * Don't support + * + ****************************************************************************/ + +static void *event_group_create_wrapper(void) +{ + DEBUGPANIC(); + + return NULL; +} + +/**************************************************************************** + * Name: event_group_delete_wrapper + * + * Description: + * Don't support + * + ****************************************************************************/ + +static void event_group_delete_wrapper(void *event) +{ + DEBUGPANIC(); +} + +/**************************************************************************** + * Name: event_group_set_bits_wrapper + * + * Description: + * Don't support + * + ****************************************************************************/ + +static uint32_t event_group_set_bits_wrapper(void *event, uint32_t bits) +{ + DEBUGPANIC(); + + return false; +} + +/**************************************************************************** + * Name: event_group_clear_bits_wrapper + * + * Description: + * Don't support + * + ****************************************************************************/ + +static uint32_t event_group_clear_bits_wrapper(void *event, uint32_t bits) +{ + DEBUGPANIC(); + + return false; +} + +/**************************************************************************** + * Name: esp_int_adpt_cb + * + * Description: + * This is the callback function for the Wi-Fi interrupt adapter. It + * retrieves the adapter from the argument, then calls the function + * stored in the adapter with its argument. + * + * Input Parameters: + * irq - The IRQ number that caused this interrupt. + * context - The register context at the time of the interrupt. + * arg - A pointer to the interrupt adapter's private data. + * + * Returned Value: + * Always returns 0. + * + ****************************************************************************/ + +static int esp_int_adpt_cb(int irq, void *context, void *arg) +{ + struct irq_adpt *adapter = (struct irq_adpt *)arg; + + adapter->func(adapter->arg); + + return 0; +} + +/**************************************************************************** + * Name: esp_nvs_commit + * + * Description: + * This function has no practical effect + * + ****************************************************************************/ + +static int esp_nvs_commit(uint32_t handle) +{ + return 0; +} + +/**************************************************************************** + * Name: esp_nvs_erase_key + * + * Description: + * Read a block of data from file system + * + * Input Parameters: + * handle - NVS handle + * key - Data index + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_nvs_erase_key(uint32_t handle, const char *key) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_nvs_get_blob + * + * Description: + * Read a block of data from file system + * + * Input Parameters: + * handle - NVS handle + * key - Data index + * out_value - Read buffer pointer + * length - Buffer length + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_nvs_get_blob(uint32_t handle, + const char *key, + void *out_value, + size_t *length) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_nvs_set_blob + * + * Description: + * Save a block of data into file system + * + * Input Parameters: + * handle - NVS handle + * key - Data index + * value - Stored buffer pointer + * length - Buffer length + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_nvs_set_blob(uint32_t handle, + const char *key, + const void *value, + size_t length) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_nvs_get_i8 + * + * Description: + * Read data of type int8_t from file system + * + * Input Parameters: + * handle - NVS handle + * key - Data index + * out_value - Read buffer pointer + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_nvs_get_i8(uint32_t handle, + const char *key, + int8_t *out_value) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_nvs_set_i8 + * + * Description: + * Save data of type int8_t into file system + * + * Input Parameters: + * handle - NVS handle + * key - Data index + * value - Stored data + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_nvs_set_i8(uint32_t handle, + const char *key, + int8_t value) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_nvs_get_u8 + * + * Description: + * Read data of type uint8_t from file system + * + * Input Parameters: + * handle - NVS handle + * key - Data index + * out_value - Read buffer pointer + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_nvs_get_u8(uint32_t handle, + const char *key, + uint8_t *out_value) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_nvs_set_u8 + * + * Description: + * Save data of type uint8_t into file system + * + * Input Parameters: + * handle - NVS handle + * key - Data index + * value - Stored data + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_nvs_set_u8(uint32_t handle, + const char *key, + uint8_t value) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_nvs_get_u16 + * + * Description: + * Read data of type uint16_t from file system + * + * Input Parameters: + * handle - NVS handle + * key - Data index + * out_value - Read buffer pointer + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_nvs_get_u16(uint32_t handle, + const char *key, + uint16_t *out_value) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_nvs_set_u16 + * + * Description: + * Save data of type uint16_t into file system + * + * Input Parameters: + * handle - NVS handle + * key - Data index + * value - Stored data + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static int esp_nvs_set_u16(uint32_t handle, + const char *key, + uint16_t value) +{ + DEBUGPANIC(); + + return -1; +} + +/**************************************************************************** + * Name: esp_nvs_close + * + * Description: + * Close storage data object and free resource + * + * Input Parameters: + * handle - NVS handle + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +static void esp_nvs_close(uint32_t handle) +{ + DEBUGPANIC(); +} + +/**************************************************************************** + * Name: esp_update_time + * + * Description: + * Transform ticks to time and add this time to timespec value + * + * Input Parameters: + * timespec - Input timespec data pointer + * ticks - System ticks + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_update_time(struct timespec *timespec, uint32_t ticks) +{ + uint32_t tmp; + + tmp = TICK2SEC(ticks); + timespec->tv_sec += tmp; + + ticks -= SEC2TICK(tmp); + tmp = TICK2NSEC(ticks); + + timespec->tv_nsec += tmp; +} + +#ifdef ESP_WLAN_HAS_STA + +/**************************************************************************** + * Name: esp_wifi_auth_trans + * + * Description: + * Converts a ESP32-C6 authenticate mode values to WEXT authenticate mode. + * + * Input Parameters: + * wifi_auth - ESP32-C6 authenticate mode + * + * Returned Value: + * authenticate mode + * + ****************************************************************************/ + +static int esp_wifi_auth_trans(uint32_t wifi_auth) +{ + int auth_mode = IW_AUTH_WPA_VERSION_DISABLED; + + switch (wifi_auth) + { + case WIFI_AUTH_OPEN: + auth_mode = IW_AUTH_WPA_VERSION_DISABLED; + break; + + case WIFI_AUTH_WPA_PSK: + auth_mode = IW_AUTH_WPA_VERSION_WPA; + break; + + case WIFI_AUTH_WPA2_PSK: + case WIFI_AUTH_WPA_WPA2_PSK: + auth_mode = IW_AUTH_WPA_VERSION_WPA2; + break; + + case WIFI_AUTH_WPA3_PSK: + case WIFI_AUTH_WPA2_WPA3_PSK: + auth_mode = IW_AUTH_WPA_VERSION_WPA3; + break; + + default: + wlerr("Failed to transfer wireless authmode: %ld", wifi_auth); + break; + } + + return auth_mode; +} + +/**************************************************************************** + * Name: esp_wifi_cipher_trans + * + * Description: + * Converts a ESP32-C6 cipher type values to WEXT cipher type values. + * + * Input Parameters: + * wifi_cipher - ESP32-C6 cipher type + * + * Returned Value: + * cipher type + * + ****************************************************************************/ + +static int esp_wifi_cipher_trans(uint32_t wifi_cipher) +{ + int cipher_mode = IW_AUTH_CIPHER_NONE; + + switch (wifi_cipher) + { + case WIFI_CIPHER_TYPE_NONE: + cipher_mode = IW_AUTH_CIPHER_NONE; + break; + + case WIFI_CIPHER_TYPE_WEP40: + cipher_mode = IW_AUTH_CIPHER_WEP40; + break; + + case WIFI_CIPHER_TYPE_WEP104: + cipher_mode = IW_AUTH_CIPHER_WEP104; + break; + + case WIFI_CIPHER_TYPE_TKIP: + cipher_mode = IW_AUTH_CIPHER_TKIP; + break; + + case WIFI_CIPHER_TYPE_CCMP: + case WIFI_CIPHER_TYPE_TKIP_CCMP: + cipher_mode = IW_AUTH_CIPHER_CCMP; + break; + + case WIFI_CIPHER_TYPE_AES_CMAC128: + cipher_mode = IW_AUTH_CIPHER_AES_CMAC; + break; + + default: + wlerr("Failed to transfer wireless authmode: %ld", + wifi_cipher); + break; + } + + return cipher_mode; +} + +#endif /* ESP_WLAN_HAS_STA */ + +/**************************************************************************** + * Name: esp_wifi_lock + * + * Description: + * Lock or unlock the event process + * + * Input Parameters: + * lock - true: Lock event process, false: unlock event process + * + * Returned Value: + * The result of lock or unlock the event process + * + ****************************************************************************/ + +static int esp_wifi_lock(bool lock) +{ + int ret; + + if (lock) + { + ret = nxmutex_lock(&g_wifiexcl_lock); + if (ret < 0) + { + wlinfo("Failed to lock Wi-Fi ret=%d\n", ret); + } + } + else + { + ret = nxmutex_unlock(&g_wifiexcl_lock); + if (ret < 0) + { + wlinfo("Failed to unlock Wi-Fi ret=%d\n", ret); + } + } + + return ret; +} + +/**************************************************************************** + * Name: queue_msg_waiting_wrapper + * + * Description: + * Get message number in the message queue + * + * Input Parameters: + * queue - Message queue data pointer + * + * Returned Value: + * Message number + * + ****************************************************************************/ + +static uint32_t queue_msg_waiting_wrapper(void *queue) +{ + int ret; + struct mq_attr attr; + struct mq_adpt *mq_adpt = (struct mq_adpt *)queue; + + ret = file_mq_getattr(&mq_adpt->mq, &attr); + if (ret < 0) + { + wlerr("Failed to get attr from mqueue error=%d\n", ret); + return 0; + } + + return attr.mq_curmsgs; +} + +/**************************************************************************** + * Name: task_delay_wrapper + * + * Description: + * Current task wait for some ticks + * + * Input Parameters: + * tick - Waiting ticks + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void task_delay_wrapper(uint32_t tick) +{ + useconds_t us = TICK2USEC(tick); + + nxsig_usleep(us); +} + +/**************************************************************************** + * Name: task_delete_wrapper + * + * Description: + * Delete the target task + * + * Input Parameters: + * task_handle - Task handle pointer which is used to pause, resume + * and delete the task + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void task_delete_wrapper(void *task_handle) +{ + pid_t pid = (pid_t)((uintptr_t)task_handle); + + kthread_delete(pid); +} + +/**************************************************************************** + * Name: task_get_current_task_wrapper + * + * Description: + * This function gets the current task's PID and returns it as a void + * pointer. This is a wrapper around the NuttX function nxsched_getpid. + * + * Input Parameters: + * None + * + * Returned Value: + * The current task's PID as a void pointer. + * + ****************************************************************************/ + +static void *task_get_current_task_wrapper(void) +{ + pid_t pid = nxsched_getpid(); + + return (void *)((uintptr_t)pid); +} + +/**************************************************************************** + * Name: vqueue_delete_adapter + * + * Description: + * This function deletes a queue adapter. It closes the message queue, + * unlinks it, and then frees the memory allocated for the queue adapter. + * + * Input Parameters: + * queue - A pointer to the queue adapter to be deleted. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void vqueue_delete_adapter(void *queue) +{ + struct mq_adpt *mq_adpt = (struct mq_adpt *)queue; + + file_mq_close(&mq_adpt->mq); + file_mq_unlink(mq_adpt->name); + kmm_free(mq_adpt); +} + +/**************************************************************************** + * Name: vsemaphore_delete_adapter + * + * Description: + * Delete semaphore + * + * Input Parameters: + * semphr - Semaphore data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void vsemaphore_delete_adapter(void *semphr) +{ + sem_t *sem = (sem_t *)semphr; + + nxsem_destroy(sem); + kmm_free(sem); +} + +/**************************************************************************** + * Name: xqueue_create_adapter + * + * Description: + * Create message queue + * + * Input Parameters: + * queue_len - queue message number + * item_size - message size + * + * Returned Value: + * Message queue data pointer + * + ****************************************************************************/ + +static void *xqueue_create_adapter(uint32_t queue_len, uint32_t item_size) +{ + struct mq_attr attr; + struct mq_adpt *mq_adpt; + int ret; + + mq_adpt = kmm_malloc(sizeof(struct mq_adpt)); + if (!mq_adpt) + { + wlerr("Failed to kmm_malloc\n"); + return NULL; + } + + snprintf(mq_adpt->name, sizeof(mq_adpt->name), + "/tmp/%p", mq_adpt); + + attr.mq_maxmsg = queue_len; + attr.mq_msgsize = item_size; + attr.mq_curmsgs = 0; + attr.mq_flags = 0; + + ret = file_mq_open(&mq_adpt->mq, mq_adpt->name, + O_RDWR | O_CREAT, 0644, &attr); + if (ret < 0) + { + wlerr("Failed to create mqueue\n"); + kmm_free(mq_adpt); + return NULL; + } + + mq_adpt->msgsize = item_size; + + return (void *)mq_adpt; +} + +/**************************************************************************** + * Name: xqueue_send_adapter + * + * Description: + * Generic send message to queue within a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * ticks - Wait ticks + * prio - Message priority + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t xqueue_send_adapter(void *queue, + void *item, + uint32_t ticks, + int prio) +{ + int ret; + struct timespec timeout; + struct mq_adpt *mq_adpt = (struct mq_adpt *)queue; + + if (ticks == OSI_FUNCS_TIME_BLOCKING || ticks == 0) + { + /* Wi-Fi interrupt function will call this adapter function to send + * message to message queue, so here we should call kernel API + * instead of application API + */ + + ret = file_mq_send(&mq_adpt->mq, (const char *)item, + mq_adpt->msgsize, prio); + if (ret < 0) + { + wlerr("Failed to send message to mqueue error=%d\n", + ret); + } + } + else + { + ret = clock_gettime(CLOCK_REALTIME, &timeout); + if (ret < 0) + { + wlerr("Failed to get time\n"); + return false; + } + + if (ticks) + { + esp_update_time(&timeout, ticks); + } + + ret = file_mq_timedsend(&mq_adpt->mq, (const char *)item, + mq_adpt->msgsize, prio, &timeout); + if (ret < 0) + { + wlerr("Failed to timedsend message to mqueue error=%d\n", + ret); + } + } + + return nuttx_err_to_freertos(ret); +} + +/**************************************************************************** + * Name: xsemaphore_create_counting_adapter + * + * Description: + * Create and initialize semaphore + * + * Input Parameters: + * max - No meanining for NuttX + * init - semaphore initialization value + * + * Returned Value: + * Semaphore data pointer + * + ****************************************************************************/ + +void *xsemaphore_create_counting_adapter(uint32_t max, uint32_t init) +{ + int ret; + sem_t *sem; + int tmp; + + tmp = sizeof(sem_t); + sem = kmm_malloc(tmp); + if (!sem) + { + wlerr("Failed to alloc %d memory\n", tmp); + return NULL; + } + + ret = nxsem_init(sem, 0, init); + if (ret) + { + wlerr("Failed to initialize sem error=%d\n", ret); + kmm_free(sem); + return NULL; + } + + return sem; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: wifi_malloc + * + * Description: + * Applications allocate a block of memory + * + * Input Parameters: + * size - memory size + * + * Returned Value: + * Memory pointer + * + ****************************************************************************/ + +IRAM_ATTR void *wifi_malloc(size_t size) +{ + return malloc(size); +} + +/**************************************************************************** + * Name: wifi_realloc + * + * Description: + * Applications allocate a block of memory by old memory block + * + * Input Parameters: + * ptr - old memory pointer + * size - memory size + * + * Returned Value: + * New memory pointer + * + ****************************************************************************/ + +IRAM_ATTR void *wifi_realloc(void *ptr, size_t size) +{ + return realloc(ptr, size); +} + +/**************************************************************************** + * Name: wifi_calloc + * + * Description: + * Applications allocate some continuous blocks of memory + * + * Input Parameters: + * n - memory block number + * size - memory block size + * + * Returned Value: + * New memory pointer + * + ****************************************************************************/ + +IRAM_ATTR void *wifi_calloc(size_t n, size_t size) +{ + return calloc(n, size); +} + +/**************************************************************************** + * Name: esp_wifi_notify_subscribe + * + * Description: + * Enable event notification + * + * Input Parameters: + * pid - Task PID + * event - Signal event data pointer + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +int esp_wifi_notify_subscribe(pid_t pid, struct sigevent *event) +{ + int id; + struct wifi_notify *notify; + int ret = -1; + + wlinfo("PID=%d event=%p\n", pid, event); + + esp_wifi_lock(true); + + if (event->sigev_notify == SIGEV_SIGNAL) + { + id = esp_event_id_map(event->sigev_signo); + if (id < 0) + { + wlerr("No process event %d\n", event->sigev_signo); + } + else + { + notify = &g_wifi_notify[id]; + + if (notify->assigned) + { + wlerr("sigev_signo %d has subscribed\n", + event->sigev_signo); + } + else + { + if (pid == 0) + { + pid = nxsched_getpid(); + wlinfo("Actual PID=%d\n", pid); + } + + notify->pid = pid; + notify->event = *event; + notify->assigned = true; + + ret = 0; + } + } + } + else if (event->sigev_notify == SIGEV_NONE) + { + id = esp_event_id_map(event->sigev_signo); + if (id < 0) + { + wlerr("No process event %d\n", event->sigev_signo); + } + else + { + notify = &g_wifi_notify[id]; + + if (!notify->assigned) + { + wlerr("sigev_signo %d has not subscribed\n", + event->sigev_signo); + } + else + { + notify->assigned = false; + + ret = 0; + } + } + } + else + { + wlerr("sigev_notify %d is invalid\n", event->sigev_signo); + } + + esp_wifi_lock(false); + + return ret; +} + +/**************************************************************************** + * Name: esp_wifi_adapter_init + * + * Description: + * Initialize ESP32-C6 Wi-Fi adapter + * + * Input Parameters: + * None + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +int esp_wifi_adapter_init(void) +{ + int ret; + wifi_init_config_t wifi_cfg = WIFI_INIT_CONFIG_DEFAULT(); + + esp_wifi_lock(true); + + if (g_wifi_ref) + { + wlinfo("Wi-Fi adapter is already initialized\n"); + g_wifi_ref++; + esp_wifi_lock(false); + return OK; + } + + sq_init(&g_wifi_evt_queue); + + wifi_cfg.nvs_enable = 0; + +#ifdef CONFIG_ESPRESSIF_WIFI_AMPDU_TX_ENABLED + wifi_cfg.ampdu_tx_enable = 1; +#else + wifi_cfg.ampdu_tx_enable = 0; +#endif + +#ifdef CONFIG_ESPRESSIF_WIFI_AMPDU_RX_ENABLED + wifi_cfg.ampdu_rx_enable = 1; +#else + wifi_cfg.ampdu_rx_enable = 0; +#endif + +#ifdef CONFIG_ESPRESSIF_WIFI_STA_DISCONNECT_PM + wifi_cfg.sta_disconnected_pm = true; +#else + wifi_cfg.sta_disconnected_pm = false; +#endif + + wifi_cfg.rx_ba_win = CONFIG_ESPRESSIF_WIFI_TX_BA_WIN; + wifi_cfg.static_rx_buf_num = CONFIG_ESPRESSIF_WIFI_STATIC_RX_BUFFER_NUM; + wifi_cfg.dynamic_rx_buf_num = CONFIG_ESPRESSIF_WIFI_DYNAMIC_RX_BUFFER_NUM; + wifi_cfg.dynamic_tx_buf_num = CONFIG_ESPRESSIF_WIFI_DYNAMIC_TX_BUFFER_NUM; + + ret = esp_wifi_init(&wifi_cfg); + if (ret) + { + wlerr("Failed to initialize Wi-Fi error=%d\n", ret); + ret = esp_wifi_to_errno(ret); + goto errout_init_wifi; + } + + ret = esp_wifi_set_tx_done_cb(esp_wifi_tx_done_cb); + if (ret) + { + wlerr("Failed to register TX done callback ret=%d\n", ret); + ret = esp_wifi_to_errno(ret); + goto errout_init_txdone; + } + + g_wifi_ref++; + + wlinfo("OK to initialize Wi-Fi adapter\n"); + + esp_wifi_lock(false); + + return OK; + +errout_init_txdone: + esp_wifi_deinit(); +errout_init_wifi: + esp_wifi_lock(false); + + return ret; +} + +/**************************************************************************** + * Station functions + ****************************************************************************/ + +#ifdef ESP_WLAN_HAS_STA + +/**************************************************************************** + * Name: esp_wifi_sta_start + * + * Description: + * Start Wi-Fi station. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_start(void) +{ + int ret; + wifi_mode_t mode; + + esp_wifi_lock(true); + + ret = esp_wifi_stop(); + if (ret) + { + wlinfo("Failed to stop Wi-Fi ret=%d\n", ret); + } + +#ifdef ESP_WLAN_HAS_SOFTAP + if (g_softap_started) + { + mode = WIFI_MODE_APSTA; + } + else +#endif /* ESP_WLAN_HAS_SOFTAP */ + { + mode = WIFI_MODE_STA; + } + + ret = esp_wifi_set_mode(mode); + if (ret) + { + wlerr("Failed to set Wi-Fi mode=%d ret=%d\n", mode, ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + + ret = esp_wifi_start(); + if (ret) + { + wlerr("Failed to start Wi-Fi with mode=%d ret=%d\n", mode, ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + + g_sta_started = true; + + wlinfo("OK to start Wi-Fi station\n"); + +errout: + esp_wifi_lock(false); + return ret; +} + +/**************************************************************************** + * Name: esp_wifi_sta_stop + * + * Description: + * Stop Wi-Fi station. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_stop(void) +{ + int ret; + + esp_wifi_lock(true); + + ret = esp_wifi_stop(); + if (ret) + { + wlinfo("Failed to stop Wi-Fi ret=%d\n", ret); + } + + g_sta_started = false; + +#ifdef ESP_WLAN_HAS_SOFTAP + if (g_softap_started) + { + ret = esp_wifi_set_mode(WIFI_MODE_AP); + if (ret) + { + wlerr("Failed to set Wi-Fi AP mode ret=%d\n", ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + + ret = esp_wifi_start(); + if (ret) + { + wlerr("Failed to start Wi-Fi AP ret=%d\n", ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + } +#endif /* ESP_WLAN_HAS_SOFTAP */ + + wlinfo("OK to stop Wi-Fi station\n"); + +#ifdef ESP_WLAN_HAS_SOFTAP +errout: +#endif /* ESP_WLAN_HAS_SOFTAP */ + + esp_wifi_lock(false); + return ret; +} + +/**************************************************************************** + * Name: esp_wifi_sta_send_data + * + * Description: + * Use Wi-Fi station interface to send 802.3 frame + * + * Input Parameters: + * pbuf - Packet buffer pointer + * len - Packet length + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_send_data(void *pbuf, size_t len) +{ + int ret; + + ret = esp_wifi_internal_tx(WIFI_IF_STA, pbuf, len); + + return esp_wifi_to_errno(ret); +} + +/**************************************************************************** + * Name: esp_wifi_set_password + * + * Description: + * Set/Get Wi-Fi station password + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_password(struct iwreq *iwr, bool set) +{ + int ret; + int size; + wifi_config_t wifi_cfg; + struct iw_encode_ext *ext = iwr->u.encoding.pointer; + uint8_t *pdata; + uint8_t len; +#ifdef CONFIG_DEBUG_WIRELESS_INFO + char buf[PWD_MAX_LEN + 1]; +#endif + + DEBUGASSERT(ext != NULL); + + pdata = ext->key; + + wifi_cfg = g_sta_wifi_cfg; + + if (set) + { + len = ext->key_len; + if (len > PWD_MAX_LEN) + { + return -EINVAL; + } + + memset(wifi_cfg.sta.password, 0x0, PWD_MAX_LEN); + + if (ext->alg != IW_ENCODE_ALG_NONE) + { + memcpy(wifi_cfg.sta.password, pdata, len); + } + + wifi_cfg.sta.pmf_cfg.capable = true; + + if (g_sta_connected) + { + ret = esp_wifi_sta_disconnect(); + if (ret) + { + wlerr("Failed to disconnect from Wi-Fi AP ret=%d\n", ret); + return ret; + } + + ret = esp_wifi_set_config(WIFI_IF_STA, &wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + ret = esp_wifi_sta_connect(); + if (ret) + { + wlerr("Failed to connect to Wi-Fi AP ret=%d\n", ret); + return ret; + } + } + + g_sta_wifi_cfg = wifi_cfg; + } + else + { + len = iwr->u.encoding.length - sizeof(*ext); + size = strnlen((char *)wifi_cfg.sta.password, PWD_MAX_LEN); + if (len < size) + { + return -EINVAL; + } + else + { + ext->key_len = size; + memcpy(pdata, wifi_cfg.sta.password, ext->key_len); + } + + if (g_sta_connected) + { + wifi_ap_record_t ap_info; + + ret = esp_wifi_sta_get_ap_info(&ap_info); + if (ret) + { + wlerr("Failed to get AP record ret=%d", ret); + return esp_wifi_to_errno(ret); + } + + switch (ap_info.pairwise_cipher) + { + case WIFI_CIPHER_TYPE_NONE: + ext->alg = IW_ENCODE_ALG_NONE; + break; + + case WIFI_CIPHER_TYPE_WEP40: + case WIFI_CIPHER_TYPE_WEP104: + ext->alg = IW_ENCODE_ALG_WEP; + break; + + case WIFI_CIPHER_TYPE_TKIP: + ext->alg = IW_ENCODE_ALG_TKIP; + break; + + case WIFI_CIPHER_TYPE_CCMP: + case WIFI_CIPHER_TYPE_TKIP_CCMP: + ext->alg = IW_ENCODE_ALG_CCMP; + break; + + case WIFI_CIPHER_TYPE_AES_CMAC128: + ext->alg = IW_ENCODE_ALG_AES_CMAC; + break; + + default: + wlerr("Failed to transfer wireless authmode: %d", + ap_info.pairwise_cipher); + return -EIO; + } + } + } + +#ifdef CONFIG_DEBUG_WIRELESS_INFO + memcpy(buf, pdata, len); + buf[len] = 0; + wlinfo("Wi-Fi station password=%s len=%d\n", buf, len); +#endif + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_sta_essid + * + * Description: + * Set/Get Wi-Fi station ESSID + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_essid(struct iwreq *iwr, bool set) +{ + int ret; + int size; + wifi_config_t wifi_cfg; + struct iw_point *essid = &iwr->u.essid; + uint8_t *pdata; + uint8_t len; +#ifdef CONFIG_DEBUG_WIRELESS_INFO + char buf[SSID_MAX_LEN + 1]; +#endif + + DEBUGASSERT(essid != NULL); + + pdata = essid->pointer; + len = essid->length; + + if (set && len > SSID_MAX_LEN) + { + return -EINVAL; + } + + wifi_cfg = g_sta_wifi_cfg; + + if (set) + { + memset(wifi_cfg.sta.ssid, 0x0, SSID_MAX_LEN); + memcpy(wifi_cfg.sta.ssid, pdata, len); + memset(wifi_cfg.sta.sae_h2e_identifier, 0x0, SAE_H2E_IDENTIFIER_LEN); + wifi_cfg.sta.sae_pwe_h2e = WPA3_SAE_PWE_BOTH; + + if (g_sta_connected) + { + ret = esp_wifi_sta_disconnect(); + if (ret) + { + wlerr("Failed to disconnect from Wi-Fi AP ret=%d\n", ret); + return ret; + } + + ret = esp_wifi_set_config(WIFI_IF_STA, &wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + ret = esp_wifi_sta_connect(); + if (ret) + { + wlerr("Failed to connect to Wi-Fi AP ret=%d\n", ret); + return ret; + } + } + + g_sta_wifi_cfg = wifi_cfg; + } + else + { + size = strnlen((char *)wifi_cfg.sta.ssid, SSID_MAX_LEN); + if (len < size) + { + return -EINVAL; + } + else + { + len = size; + memcpy(pdata, wifi_cfg.sta.ssid, len); + } + + if (g_sta_connected) + { + essid->flags = IW_ESSID_ON; + } + else + { + essid->flags = IW_ESSID_OFF; + } + } + +#ifdef CONFIG_DEBUG_WIRELESS_INFO + memcpy(buf, pdata, len); + buf[len] = 0; + wlinfo("Wi-Fi station ssid=%s len=%d\n", buf, len); +#endif + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_sta_bssid + * + * Description: + * Set/Get Wi-Fi station BSSID + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_bssid(struct iwreq *iwr, bool set) +{ + int ret; + wifi_config_t wifi_cfg; + struct sockaddr *sockaddr; + char *pdata; + + sockaddr = &iwr->u.ap_addr; + pdata = sockaddr->sa_data; + + wifi_cfg = g_sta_wifi_cfg; + + if (set) + { + wifi_cfg.sta.bssid_set = true; + memcpy(wifi_cfg.sta.bssid, pdata, MAC_LEN); + + if (g_sta_connected) + { + ret = esp_wifi_sta_disconnect(); + if (ret) + { + wlerr("Failed to disconnect from Wi-Fi AP ret=%d\n", ret); + return ret; + } + + ret = esp_wifi_set_config(WIFI_IF_STA, &wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + ret = esp_wifi_sta_connect(); + if (ret) + { + wlerr("Failed to connect to Wi-Fi AP ret=%d\n", ret); + return ret; + } + } + + g_sta_wifi_cfg = wifi_cfg; + } + else + { + memcpy(pdata, wifi_cfg.sta.bssid, MAC_LEN); + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_sta_connect + * + * Description: + * Trigger Wi-Fi station connection action + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_connect(void) +{ + int ret; + uint32_t ticks; + + esp_wifi_lock(true); + + if (g_sta_connected) + { + wlinfo("Wi-Fi has connected AP\n"); + esp_wifi_lock(false); + return OK; + } + + g_sta_reconnect = true; + + ret = esp_wifi_set_config(WIFI_IF_STA, &g_sta_wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + ret = esp_wifi_connect(); + if (ret) + { + wlerr("Failed to connect ret=%d\n", ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + + esp_wifi_lock(false); + + ticks = SEC2TICK(WIFI_CONNECT_TIMEOUT); + do + { + if (g_sta_connected) + { + break; + } + + task_delay_wrapper(1); + } + while (ticks--); + + if (!g_sta_connected) + { + g_sta_reconnect = false; + wlinfo("Failed to connect to AP\n"); + return -1; + } + + return OK; + +errout: + g_sta_reconnect = false; + esp_wifi_lock(false); + return ret; +} + +/**************************************************************************** + * Name: esp_wifi_sta_disconnect + * + * Description: + * Trigger Wi-Fi station disconnection action + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_disconnect(void) +{ + int ret; + + esp_wifi_lock(true); + + g_sta_reconnect = false; + + ret = esp_wifi_disconnect(); + if (ret) + { + wlerr("Failed to disconnect ret=%d\n", ret); + ret = esp_wifi_to_errno(ret); + } + else + { + wlinfo("OK to disconnect Wi-Fi station\n"); + } + + esp_wifi_lock(false); + return ret; +} + +/**************************************************************************** + * Name: esp_wifi_sta_mode + * + * Description: + * Set/Get Wi-Fi Station mode code. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_mode(struct iwreq *iwr, bool set) +{ + if (set == false) + { + iwr->u.mode = IW_MODE_INFRA; + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_sta_auth + * + * Description: + * Set/Get station authentication mode params. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_auth(struct iwreq *iwr, bool set) +{ + int ret; + int cmd; + wifi_config_t wifi_cfg; + wifi_ap_record_t ap_info; + + wifi_cfg = g_sta_wifi_cfg; + + if (set) + { + cmd = iwr->u.param.flags & IW_AUTH_INDEX; + switch (cmd) + { + case IW_AUTH_WPA_VERSION: + { + switch (iwr->u.param.value) + { + case IW_AUTH_WPA_VERSION_DISABLED: + wifi_cfg.sta.threshold.authmode = WIFI_AUTH_OPEN; + break; + + case IW_AUTH_WPA_VERSION_WPA: + wifi_cfg.sta.threshold.authmode = WIFI_AUTH_WPA_PSK; + break; + + case IW_AUTH_WPA_VERSION_WPA2: + wifi_cfg.sta.threshold.authmode = WIFI_AUTH_WPA2_PSK; + break; + + case IW_AUTH_WPA_VERSION_WPA3: + wifi_cfg.sta.threshold.authmode = WIFI_AUTH_WPA3_PSK; + break; + + default: + wlerr("Invalid wpa version %" PRId32 "\n", + iwr->u.param.value); + return -EINVAL; + } + } + + break; + case IW_AUTH_CIPHER_PAIRWISE: + case IW_AUTH_CIPHER_GROUP: + { + switch (iwr->u.param.value) + { + case IW_AUTH_CIPHER_NONE: + wifi_cfg.sta.threshold.authmode = WIFI_AUTH_OPEN; + break; + + case IW_AUTH_CIPHER_WEP40: + case IW_AUTH_CIPHER_WEP104: + wifi_cfg.sta.threshold.authmode = WIFI_AUTH_WEP; + break; + + case IW_AUTH_CIPHER_TKIP: + case IW_AUTH_CIPHER_CCMP: + case IW_AUTH_CIPHER_AES_CMAC: + break; + + default: + wlerr("Invalid cipher mode %" PRId32 "\n", + iwr->u.param.value); + return -EINVAL; + } + } + + break; + case IW_AUTH_KEY_MGMT: + case IW_AUTH_TKIP_COUNTERMEASURES: + case IW_AUTH_DROP_UNENCRYPTED: + case IW_AUTH_80211_AUTH_ALG: + case IW_AUTH_WPA_ENABLED: + case IW_AUTH_RX_UNENCRYPTED_EAPOL: + case IW_AUTH_ROAMING_CONTROL: + case IW_AUTH_PRIVACY_INVOKED: + default: + wlerr("Unknown cmd %d\n", cmd); + return -EINVAL; + } + + size_t password_len = strlen((const char *)wifi_cfg.sta.password); + wifi_auth_mode_t authmode = wifi_cfg.sta.threshold.authmode; + + if (g_sta_connected && + ((password_len > 0 && authmode != WIFI_AUTH_OPEN) || + (password_len == 0 && authmode == WIFI_AUTH_OPEN))) + { + ret = esp_wifi_sta_disconnect(); + if (ret) + { + wlerr("Failed to disconnect from Wi-Fi AP ret=%d\n", ret); + return ret; + } + + ret = esp_wifi_set_config(WIFI_IF_STA, &wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + ret = esp_wifi_sta_connect(); + if (ret) + { + wlerr("Failed to connect to Wi-Fi AP ret=%d\n", ret); + return ret; + } + } + + g_sta_wifi_cfg = wifi_cfg; + } + else + { + if (g_sta_connected == false) + { + return -ENOTCONN; + } + + ret = esp_wifi_sta_get_ap_info(&ap_info); + if (ret) + { + wlerr("Failed to get AP record ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + cmd = iwr->u.param.flags & IW_AUTH_INDEX; + switch (cmd) + { + case IW_AUTH_WPA_VERSION: + iwr->u.param.value = esp_wifi_auth_trans(ap_info.authmode); + break; + + case IW_AUTH_CIPHER_PAIRWISE: + iwr->u.param.value = + esp_wifi_cipher_trans(ap_info.pairwise_cipher); + break; + + case IW_AUTH_CIPHER_GROUP: + iwr->u.param.value = esp_wifi_cipher_trans(ap_info.group_cipher); + break; + + case IW_AUTH_KEY_MGMT: + case IW_AUTH_TKIP_COUNTERMEASURES: + case IW_AUTH_DROP_UNENCRYPTED: + case IW_AUTH_80211_AUTH_ALG: + case IW_AUTH_WPA_ENABLED: + case IW_AUTH_RX_UNENCRYPTED_EAPOL: + case IW_AUTH_ROAMING_CONTROL: + case IW_AUTH_PRIVACY_INVOKED: + default: + wlerr("Unknown cmd %d\n", cmd); + return -ENOSYS; + } + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_sta_freq + * + * Description: + * Set/Get station frequency. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_freq(struct iwreq *iwr, bool set) +{ + int ret; + + if (set && (iwr->u.freq.flags == IW_FREQ_FIXED)) + { + wifi_config_t wifi_cfg = g_sta_wifi_cfg; + + wifi_cfg.sta.channel = esp_freq_to_channel(iwr->u.freq.m); + + if (g_sta_connected) + { + ret = esp_wifi_sta_disconnect(); + if (ret) + { + wlerr("Failed to disconnect from Wi-Fi AP ret=%d\n", ret); + return ret; + } + + ret = esp_wifi_set_config(WIFI_IF_STA, &wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + ret = esp_wifi_sta_connect(); + if (ret) + { + wlerr("Failed to connect to Wi-Fi AP ret=%d\n", ret); + return ret; + } + } + + g_sta_wifi_cfg = wifi_cfg; + } + else + { + if (g_sta_connected) + { + wifi_ap_record_t ap_info; + + ret = esp_wifi_sta_get_ap_info(&ap_info); + if (ret) + { + wlerr("Failed to get AP record ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + iwr->u.freq.flags = IW_FREQ_FIXED; + iwr->u.freq.e = 0; + iwr->u.freq.m = 2407 + 5 * ap_info.primary; + } + else + { + iwr->u.freq.flags = IW_FREQ_AUTO; + iwr->u.freq.e = 0; + iwr->u.freq.m = 2412; + } + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_sta_bitrate + * + * Description: + * Get station default bit rate (Mbps). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_bitrate(struct iwreq *iwr, bool set) +{ + int ret; + wifi_ap_record_t ap_info; + + if (set) + { + return -ENOSYS; + } + else + { + if (g_sta_connected == false) + { + iwr->u.bitrate.fixed = IW_FREQ_AUTO; + return OK; + } + + ret = esp_wifi_sta_get_ap_info(&ap_info); + if (ret) + { + wlerr("Failed to get AP record ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + iwr->u.bitrate.fixed = IW_FREQ_FIXED; + if (ap_info.phy_11n) + { + if (ap_info.second) + { + iwr->u.bitrate.value = ESP_WIFI_11N_MCS7_HT40_BITRATE; + } + else + { + iwr->u.bitrate.value = ESP_WIFI_11N_MCS7_HT20_BITRATE; + } + } + else if (ap_info.phy_11g) + { + iwr->u.bitrate.value = ESP_WIFI_11G_MAX_BITRATE; + } + else if (ap_info.phy_11b) + { + iwr->u.bitrate.value = ESP_WIFI_11B_MAX_BITRATE; + } + else + { + return -EIO; + } + } + + return OK; +} + +#endif /* ESP_WLAN_HAS_STA */ + +/**************************************************************************** + * Name: esp_wifi_sta_get_txpower + * + * Description: + * Get station transmit power (dBm). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_txpower(struct iwreq *iwr, bool set) +{ + int ret; + int8_t power; + double power_dbm; + + if (set) + { + if (iwr->u.txpower.flags == IW_TXPOW_RELATIVE) + { + power = (int8_t)iwr->u.txpower.value; + } + else + { + if (iwr->u.txpower.flags == IW_TXPOW_MWATT) + { + power_dbm = ceil(10 * log10(iwr->u.txpower.value)); + } + else + { + power_dbm = iwr->u.txpower.value; + } + + power = (int8_t)(power_dbm * 4); + } + + /* The value set by this API will be mapped to the max_tx_power + * of the structure wifi_country_t variable. Param power unit is + * 0.25dBm, range is [8, 84] corresponding to 2dBm - 20dBm. + * Relationship between set value and actual value. + * As follows: {set value range, actual value} = + * {{[8, 19],8}, {[20, 27],20}, {[28, 33],28}, + * {[34, 43],34}, {[44, 51],44}, {[52, 55],52}, + * {[56, 59],56}, {[60, 65],60}, {[66, 71],66}, + * {[72, 79],72}, {[80, 84],80}}. + */ + + if (power < 8 || power > 84) + { + wlerr("Failed to set transmit power =%d\n", power); + return -ENOSYS; + } + + esp_wifi_set_max_tx_power(power); + return OK; + } + else + { + ret = esp_wifi_get_max_tx_power(&power); + if (ret) + { + wlerr("Failed to get transmit power ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + iwr->u.txpower.disabled = 0; + iwr->u.txpower.flags = IW_TXPOW_DBM; + iwr->u.txpower.value = power / 4; + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_sta_channel + * + * Description: + * Get station range of channel parameters. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_channel(struct iwreq *iwr, bool set) +{ + int ret; + int k; + wifi_country_t country; + struct iw_range *range; + + if (set) + { + return -ENOSYS; + } + else + { + ret = esp_wifi_get_country(&country); + if (ret) + { + wlerr("Failed to get country info ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + range = (struct iw_range *)iwr->u.data.pointer; + range->num_frequency = country.nchan; + for (k = 1; k <= range->num_frequency; k++) + { + range->freq[k - 1].i = k; + range->freq[k - 1].e = 0; + range->freq[k - 1].m = 2407 + 5 * k; + } + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_sta_country + * + * Description: + * Configure country info. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_country(struct iwreq *iwr, bool set) +{ + int ret; + char *country_code; + wifi_country_t country; + + if (set) + { + memset(&country, 0x00, sizeof(wifi_country_t)); + country.schan = 1; + country.policy = 0; + + country_code = (char *)iwr->u.data.pointer; + if (strlen(country_code) != 2) + { + wlerr("Invalid input arguments\n"); + return -EINVAL; + } + + if (strncmp(country_code, "US", 3) == 0 || + strncmp(country_code, "CA", 3) == 0) + { + country.nchan = 11; + } + else if(strncmp(country_code, "JP", 3) == 0) + { + country.nchan = 14; + } + else + { + country.nchan = 13; + } + + memcpy(country.cc, country_code, 2); + ret = esp_wifi_set_country(&country); + if (ret) + { + wlerr("Failed to Configure country ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + } + else + { + return -ENOSYS; + } + + return OK; +} + +#ifdef ESP_WLAN_HAS_STA + +/**************************************************************************** + * Name: esp_wifi_sta_rssi + * + * Description: + * Get Wi-Fi sensitivity (dBm). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_rssi(struct iwreq *iwr, bool set) +{ + int ret; + wifi_ap_record_t ap_info; + + if (set) + { + return -ENOSYS; + } + else + { + if (g_sta_connected == false) + { + iwr->u.sens.value = 128; + return OK; + } + + ret = esp_wifi_sta_get_ap_info(&ap_info); + if (ret) + { + wlerr("Failed to get AP record ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + iwr->u.sens.value = -(ap_info.rssi); + } + + return OK; +} +#endif /* ESP_WLAN_HAS_STA */ + +/**************************************************************************** + * SoftAP functions + ****************************************************************************/ + +#ifdef ESP_WLAN_HAS_SOFTAP + +/**************************************************************************** + * Name: esp_wifi_softap_start + * + * Description: + * Start Wi-Fi SoftAP. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_start(void) +{ + int ret; + wifi_mode_t mode; + + esp_wifi_lock(true); + + ret = esp_wifi_stop(); + if (ret) + { + wlinfo("Failed to stop Wi-Fi ret=%d\n", ret); + } + +#ifdef ESP_WLAN_HAS_STA + if (g_sta_started) + { + mode = WIFI_MODE_APSTA; + } + else +#endif /* ESP_WLAN_HAS_STA */ + { + mode = WIFI_MODE_AP; + } + + ret = esp_wifi_set_mode(mode); + if (ret) + { + wlerr("Failed to set Wi-Fi mode=%d ret=%d\n", mode, ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + + ret = esp_wifi_start(); + if (ret) + { + wlerr("Failed to start Wi-Fi with mode=%d ret=%d\n", mode, ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + + g_softap_started = true; + + wlinfo("OK to start Wi-Fi SoftAP\n"); + +errout: + esp_wifi_lock(false); + return ret; +} + +/**************************************************************************** + * Name: esp_wifi_softap_stop + * + * Description: + * Stop Wi-Fi SoftAP. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_stop(void) +{ + int ret; + + esp_wifi_lock(true); + + ret = esp_wifi_stop(); + if (ret) + { + wlinfo("Failed to stop Wi-Fi ret=%d\n", ret); + } + + g_softap_started = false; + +#ifdef ESP_WLAN_HAS_STA + if (g_sta_started) + { + ret = esp_wifi_set_mode(WIFI_MODE_STA); + if (ret) + { + wlerr("Failed to set Wi-Fi AP mode ret=%d\n", ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + + ret = esp_wifi_start(); + if (ret) + { + wlerr("Failed to start Wi-Fi STA ret=%d\n", ret); + ret = esp_wifi_to_errno(ret); + goto errout; + } + } +#endif /* ESP_WLAN_HAS_STA */ + + wlinfo("OK to stop Wi-Fi SoftAP\n"); + +#ifdef ESP_WLAN_HAS_STA +errout: +#endif /* ESP_WLAN_HAS_STA */ + + esp_wifi_lock(false); + return ret; +} + +/**************************************************************************** + * Name: esp_wifi_softap_send_data + * + * Description: + * Use Wi-Fi SoftAP interface to send 802.3 frame + * + * Input Parameters: + * pbuf - Packet buffer pointer + * len - Packet length + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_send_data(void *pbuf, size_t len) +{ + int ret; + + ret = esp_wifi_internal_tx(WIFI_IF_AP, pbuf, len); + + return esp_wifi_to_errno(ret); +} + +/**************************************************************************** + * Name: esp_wifi_softap_password + * + * Description: + * Set/Get Wi-Fi SoftAP password + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_password(struct iwreq *iwr, bool set) +{ + int ret; + int size; + wifi_config_t wifi_cfg; + struct iw_encode_ext *ext = iwr->u.encoding.pointer; + uint8_t *pdata; + uint8_t len; +#ifdef CONFIG_DEBUG_WIRELESS_INFO + char buf[PWD_MAX_LEN + 1]; +#endif + + DEBUGASSERT(ext != NULL); + + pdata = ext->key; + len = ext->key_len; + + if (set && len > PWD_MAX_LEN) + { + return -EINVAL; + } + + pdata = ext->key; + len = ext->key_len; + + wifi_cfg = g_softap_wifi_cfg; + + if (set) + { + /* Clear the password field and copy the user password to it */ + + memset(wifi_cfg.ap.password, 0x0, PWD_MAX_LEN); + + if (ext->alg != IW_ENCODE_ALG_NONE) + { + memcpy(wifi_cfg.sta.password, pdata, len); + } + + if (g_softap_started) + { + ret = esp_wifi_set_config(WIFI_IF_AP, &wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + } + + g_softap_wifi_cfg = wifi_cfg; + } + else + { + size = strnlen((char *)wifi_cfg.ap.password, PWD_MAX_LEN); + if (len < size) + { + return -EINVAL; + } + else + { + len = size; + memcpy(pdata, wifi_cfg.ap.password, len); + } + } + +#ifdef CONFIG_DEBUG_WIRELESS_INFO + memcpy(buf, pdata, len); + buf[len] = 0; + wlinfo("Wi-Fi SoftAP password=%s len=%d\n", buf, len); +#endif + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_softap_essid + * + * Description: + * Set/Get Wi-Fi SoftAP ESSID + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_essid(struct iwreq *iwr, bool set) +{ + int ret; + int size; + wifi_config_t wifi_cfg; + struct iw_point *essid = &iwr->u.essid; + uint8_t *pdata; + uint8_t len; +#ifdef CONFIG_DEBUG_WIRELESS_INFO + char buf[SSID_MAX_LEN + 1]; +#endif + + DEBUGASSERT(essid != NULL); + + pdata = essid->pointer; + len = essid->length; + + if (set && len > SSID_MAX_LEN) + { + return -EINVAL; + } + + wifi_cfg = g_softap_wifi_cfg; + + if (set) + { + memset(wifi_cfg.ap.ssid, 0x0, SSID_MAX_LEN); + memcpy(wifi_cfg.ap.ssid, pdata, len); + wifi_cfg.ap.ssid_len = len; + if (g_softap_started) + { + ret = esp_wifi_set_config(WIFI_IF_AP, &wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + } + + g_softap_wifi_cfg = wifi_cfg; + } + else + { + size = strnlen((char *)wifi_cfg.ap.ssid, SSID_MAX_LEN); + if (len < size) + { + return -EINVAL; + } + else + { + len = size; + memcpy(pdata, wifi_cfg.ap.ssid, len); + } + } + +#ifdef CONFIG_DEBUG_WIRELESS_INFO + memcpy(buf, pdata, len); + buf[len] = 0; + wlinfo("Wi-Fi SoftAP ssid=%s len=%d\n", buf, len); +#endif + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_softap_bssid + * + * Description: + * Set/Get Wi-Fi softAP BSSID + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_bssid(struct iwreq *iwr, bool set) +{ + return -ENOSYS; +} + +/**************************************************************************** + * Name: esp_wifi_softap_connect + * + * Description: + * Trigger Wi-Fi SoftAP accept connection action + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_connect(void) +{ + int ret; + + ret = esp_wifi_set_config(WIFI_IF_AP, &g_softap_wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_softap_disconnect + * + * Description: + * Trigger Wi-Fi SoftAP drop connection action + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_disconnect(void) +{ + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_softap_mode + * + * Description: + * Set/Get Wi-Fi SoftAP mode code. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_mode(struct iwreq *iwr, bool set) +{ + if (set == false) + { + iwr->u.mode = IW_MODE_MASTER; + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_softap_auth + * + * Description: + * Set/get authentication mode params. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_auth(struct iwreq *iwr, bool set) +{ + int ret; + int cmd; + wifi_config_t wifi_cfg; + + wifi_cfg = g_softap_wifi_cfg; + + if (set) + { + cmd = iwr->u.param.flags & IW_AUTH_INDEX; + switch (cmd) + { + case IW_AUTH_WPA_VERSION: + { + switch (iwr->u.param.value) + { + case IW_AUTH_WPA_VERSION_DISABLED: + wifi_cfg.ap.authmode = WIFI_AUTH_OPEN; + break; + + case IW_AUTH_WPA_VERSION_WPA: + wifi_cfg.ap.authmode = WIFI_AUTH_WPA_PSK; + break; + + case IW_AUTH_WPA_VERSION_WPA2: + wifi_cfg.ap.authmode = WIFI_AUTH_WPA2_PSK; + break; + + case IW_AUTH_WPA_VERSION_WPA3: + wifi_cfg.ap.pmf_cfg.required = true; + wifi_cfg.ap.pmf_cfg.capable = false; + wifi_cfg.ap.sae_pwe_h2e = WPA3_SAE_PWE_BOTH; + wifi_cfg.ap.authmode = WIFI_AUTH_WPA3_PSK; + break; + + default: + wlerr("Invalid wpa version %" PRId32 "\n", + iwr->u.param.value); + return -EINVAL; + } + } + + break; + case IW_AUTH_CIPHER_PAIRWISE: + case IW_AUTH_CIPHER_GROUP: + { + switch (iwr->u.param.value) + { + case IW_AUTH_CIPHER_NONE: + wifi_cfg.ap.authmode = WIFI_AUTH_OPEN; + break; + + case IW_AUTH_CIPHER_WEP40: + case IW_AUTH_CIPHER_WEP104: + wifi_cfg.ap.authmode = WIFI_AUTH_WEP; + break; + + case IW_AUTH_CIPHER_TKIP: + case IW_AUTH_CIPHER_CCMP: + case IW_AUTH_CIPHER_AES_CMAC: + break; + + default: + wlerr("Invalid cipher mode %" PRId32 "\n", + iwr->u.param.value); + return -EINVAL; + } + } + + break; + case IW_AUTH_KEY_MGMT: + case IW_AUTH_TKIP_COUNTERMEASURES: + case IW_AUTH_DROP_UNENCRYPTED: + case IW_AUTH_80211_AUTH_ALG: + case IW_AUTH_WPA_ENABLED: + case IW_AUTH_RX_UNENCRYPTED_EAPOL: + case IW_AUTH_ROAMING_CONTROL: + case IW_AUTH_PRIVACY_INVOKED: + default: + wlerr("Unknown cmd %d\n", cmd); + return -EINVAL; + } + + size_t password_len = strlen((const char *)wifi_cfg.ap.password); + + if (g_softap_started && + ((password_len > 0 && wifi_cfg.ap.authmode != WIFI_AUTH_OPEN) || + (password_len == 0 && wifi_cfg.ap.authmode == WIFI_AUTH_OPEN))) + { + ret = esp_wifi_set_config(WIFI_IF_AP, &wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + } + + g_softap_wifi_cfg = wifi_cfg; + } + else + { + return -ENOSYS; + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_softap_freq + * + * Description: + * Set/Get SoftAP frequency. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_freq(struct iwreq *iwr, bool set) +{ + int ret; + wifi_config_t wifi_cfg; + + wifi_cfg = g_softap_wifi_cfg; + + if (set) + { + int channel = esp_freq_to_channel(iwr->u.freq.m); + + wifi_cfg.ap.channel = channel; + + if (g_softap_started) + { + ret = esp_wifi_set_config(WIFI_IF_AP, &wifi_cfg); + if (ret) + { + wlerr("Failed to set Wi-Fi config data ret=%d\n", ret); + return esp_wifi_to_errno(ret); + } + } + + g_softap_wifi_cfg = wifi_cfg; + } + else + { + iwr->u.freq.flags = IW_FREQ_FIXED; + iwr->u.freq.e = 0; + iwr->u.freq.m = 2407 + 5 * wifi_cfg.ap.channel; + } + + return OK; +} + +/**************************************************************************** + * Name: esp_wifi_softap_get_bitrate + * + * Description: + * Get SoftAP default bit rate (Mbps). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_bitrate(struct iwreq *iwr, bool set) +{ + return -ENOSYS; +} + +/**************************************************************************** + * Name: esp_wifi_softap_txpower + * + * Description: + * Get SoftAP transmit power (dBm). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_txpower(struct iwreq *iwr, bool set) +{ + return esp_wifi_sta_txpower(iwr, set); +} + +/**************************************************************************** + * Name: esp_wifi_softap_channel + * + * Description: + * Get SoftAP range of channel parameters. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_channel(struct iwreq *iwr, bool set) +{ + return esp_wifi_sta_channel(iwr, set); +} + +/**************************************************************************** + * Name: esp_wifi_softap_country + * + * Description: + * Configure country info. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_country(struct iwreq *iwr, bool set) +{ + return esp_wifi_sta_country(iwr, set); +} + +/**************************************************************************** + * Name: esp_wifi_softap_rssi + * + * Description: + * Get Wi-Fi sensitivity (dBm). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_rssi(struct iwreq *iwr, bool set) +{ + return -ENOSYS; +} + +#endif /* ESP_WLAN_HAS_SOFTAP */ diff --git a/arch/risc-v/src/esp32c6/esp_wifi_adapter.h b/arch/risc-v/src/esp32c6/esp_wifi_adapter.h new file mode 100644 index 0000000000000..9852b0921cb67 --- /dev/null +++ b/arch/risc-v/src/esp32c6/esp_wifi_adapter.h @@ -0,0 +1,672 @@ +/**************************************************************************** + * arch/risc-v/src/esp32c6/esp_wifi_adapter.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_ESP32C6_ESP_WIFI_ADAPTER_H +#define __ARCH_RISCV_SRC_ESP32C6_ESP_WIFI_ADAPTER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "esp_wlan.h" + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SSID_MAX_LEN (32) +#define PWD_MAX_LEN (64) + +#define CONFIG_IDF_TARGET_ESP32C6 1 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_wifi_adapter_init + * + * Description: + * Initialize ESP32C6 Wi-Fi adapter + * + * Input Parameters: + * None + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +int esp_wifi_adapter_init(void); + +/**************************************************************************** + * Name: esp_wifi_notify_subscribe + * + * Description: + * Enable event notification + * + * Input Parameters: + * pid - Task PID + * event - Signal event data pointer + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +int esp_wifi_notify_subscribe(pid_t pid, struct sigevent *event); + +#ifdef ESP_WLAN_HAS_STA + +/**************************************************************************** + * Name: esp_wifi_sta_start + * + * Description: + * Start Wi-Fi station. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_start(void); + +/**************************************************************************** + * Name: esp_wifi_sta_stop + * + * Description: + * Stop Wi-Fi station. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_stop(void); + +/**************************************************************************** + * Name: esp_wifi_sta_send_data + * + * Description: + * Use Wi-Fi station interface to send 802.3 frame + * + * Input Parameters: + * pbuf - Packet buffer pointer + * len - Packet length + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_send_data(void *pbuf, size_t len); + +/**************************************************************************** + * Name: esp_wifi_set_password + * + * Description: + * Set/Get Wi-Fi station password + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_password(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_essid + * + * Description: + * Set/Get Wi-Fi station ESSID + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_essid(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_bssid + * + * Description: + * Set/Get Wi-Fi station BSSID + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_bssid(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_connect + * + * Description: + * Trigger Wi-Fi station connection action + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_connect(void); + +/**************************************************************************** + * Name: esp_wifi_sta_disconnect + * + * Description: + * Trigger Wi-Fi station disconnection action + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_disconnect(void); + +/**************************************************************************** + * Name: esp_wifi_sta_mode + * + * Description: + * Set/Get Wi-Fi Station mode code. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_mode(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_auth + * + * Description: + * Set/Get station authentication mode params. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_auth(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_freq + * + * Description: + * Get station frequency. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_freq(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_bitrate + * + * Description: + * Get station default bit rate (Mbps). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_bitrate(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_get_txpower + * + * Description: + * Get station transmit power (dBm). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_txpower(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_get_channel_range + * + * Description: + * Get station range of channel parameters. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_channel(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_country + * + * Description: + * Configure country info. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_country(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_sta_rssi + * + * Description: + * Get Wi-Fi sensitivity (dBm). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_sta_rssi(struct iwreq *iwr, bool set); +#endif /* ESP_WLAN_HAS_STA */ + +#ifdef ESP_WLAN_HAS_SOFTAP + +/**************************************************************************** + * Name: esp_wifi_softap_start + * + * Description: + * Start Wi-Fi softAP. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_start(void); + +/**************************************************************************** + * Name: esp_wifi_softap_stop + * + * Description: + * Stop Wi-Fi softAP. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_stop(void); + +/**************************************************************************** + * Name: esp_wifi_softap_send_data + * + * Description: + * Use Wi-Fi softAP interface to send 802.3 frame + * + * Input Parameters: + * pbuf - Packet buffer pointer + * len - Packet length + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_send_data(void *pbuf, size_t len); + +/**************************************************************************** + * Name: esp_wifi_softap_password + * + * Description: + * Set/Get Wi-Fi SoftAP password + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_password(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_essid + * + * Description: + * Set/Get Wi-Fi SoftAP ESSID + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_essid(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_bssid + * + * Description: + * Set/Get Wi-Fi softAP BSSID + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_bssid(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_connect + * + * Description: + * Trigger Wi-Fi softAP accept connection action + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_connect(void); + +/**************************************************************************** + * Name: esp_wifi_softap_disconnect + * + * Description: + * Trigger Wi-Fi softAP drop connection action + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_disconnect(void); + +/**************************************************************************** + * Name: esp_wifi_softap_mode + * + * Description: + * Set/Get Wi-Fi SoftAP mode code. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_mode(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_auth + * + * Description: + * Set/Get authentication mode params. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_auth(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_freq + * + * Description: + * Set/Get SoftAP frequency. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_freq(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_get_bitrate + * + * Description: + * Get SoftAP default bit rate (Mbps). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_bitrate(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_txpower + * + * Description: + * Get SoftAP transmit power (dBm). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_txpower(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_channel + * + * Description: + * Get SoftAP range of channel parameters. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_channel(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_country + * + * Description: + * Configure country info. + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_country(struct iwreq *iwr, bool set); + +/**************************************************************************** + * Name: esp_wifi_softap_rssi + * + * Description: + * Get Wi-Fi sensitivity (dBm). + * + * Input Parameters: + * iwr - The argument of the ioctl cmd + * set - true: set data; false: get data + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +int esp_wifi_softap_rssi(struct iwreq *iwr, bool set); +#endif /* ESP_WLAN_HAS_SOFTAP */ + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32C6_ESP_WIFI_ADAPTER_H */ diff --git a/arch/risc-v/src/esp32c6/hal_esp32c6.mk b/arch/risc-v/src/esp32c6/hal_esp32c6.mk new file mode 100644 index 0000000000000..d66e16acb358e --- /dev/null +++ b/arch/risc-v/src/esp32c6/hal_esp32c6.mk @@ -0,0 +1,175 @@ +############################################################################ +# arch/risc-v/src/esp32c6/esp32c6.mk +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Include header paths + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)driver$(DELIM)twai$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_event$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)esp_private +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include$(DELIM)private +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)public_compat +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)platform_port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash + +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)private_include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)include +endif + +# Linker scripts + +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.api.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.coexist.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.net80211.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.phy.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.pp.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.spiflash.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.version.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.wdt.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).peripherals.ld + +# Source files + +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_api.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_utility.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_fields.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_table.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_utility.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)src$(DELIM)esp_err_to_name.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)cpu.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)hw_random.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mac_addr.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)modem_clock.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)periph_ctrl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modem.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)ocode_init.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_init.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_param.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)pmu_sleep.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk_init.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_time.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)sar_periph_ctrl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)systimer.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)lib_printf.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_regi2c_$(CHIP_SERIES).c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_systimer.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_wdt.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)brownout.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)brownout_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)efuse_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gpio_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)lp_timer_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)twai_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)twai_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mpu_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mmu_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)wdt_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)efuse_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)modem_clock_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log_noos.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)riscv$(DELIM)interrupt.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gpio_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c + +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)bootloader_banner_wrap.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_console.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_console_loader.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_${CHIP_SERIES}.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_init.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common_loader.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash_config_${CHIP_SERIES}.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_init.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_loader.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_efuse.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_mem.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random_${CHIP_SERIES}.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)esp_image_format.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_sha.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)flash_encrypt.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_fields.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)efuse_controller$(DELIM)keys$(DELIM)with_key_purposes$(DELIM)esp_efuse_api_key.c + + LDFLAGS += --wrap=bootloader_print_banner +endif diff --git a/arch/risc-v/src/esp32c6/hardware/esp32c6_lp_aon.h b/arch/risc-v/src/esp32c6/hardware/esp32c6_lp_aon.h deleted file mode 100644 index 9367b229a1d6e..0000000000000 --- a/arch/risc-v/src/esp32c6/hardware/esp32c6_lp_aon.h +++ /dev/null @@ -1,541 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/hardware/esp32c6_lp_aon.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_LP_AON_H -#define __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_LP_AON_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32c6_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* LP_AON_STORE0_REG register - * need_des - */ - -#define LP_AON_STORE0_REG (DR_REG_LP_AON_BASE + 0x0) - -/* LP_AON_LP_AON_STORE0 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - -#define LP_AON_LP_AON_STORE0 0xffffffff -#define LP_AON_LP_AON_STORE0_M (LP_AON_LP_AON_STORE0_V << LP_AON_LP_AON_STORE0_S) -#define LP_AON_LP_AON_STORE0_V 0xffffffff -#define LP_AON_LP_AON_STORE0_S 0 - -/* LP_AON_STORE1_REG register - * need_des - */ - -#define LP_AON_STORE1_REG (DR_REG_LP_AON_BASE + 0x4) - -/* LP_AON_LP_AON_STORE1 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - -#define LP_AON_LP_AON_STORE1 0xffffffff -#define LP_AON_LP_AON_STORE1_M (LP_AON_LP_AON_STORE1_V << LP_AON_LP_AON_STORE1_S) -#define LP_AON_LP_AON_STORE1_V 0xffffffff -#define LP_AON_LP_AON_STORE1_S 0 - -/* LP_AON_STORE2_REG register - * need_des - */ - -#define LP_AON_STORE2_REG (DR_REG_LP_AON_BASE + 0x8) - -/* LP_AON_LP_AON_STORE2 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - -#define LP_AON_LP_AON_STORE2 0xffffffff -#define LP_AON_LP_AON_STORE2_M (LP_AON_LP_AON_STORE2_V << LP_AON_LP_AON_STORE2_S) -#define LP_AON_LP_AON_STORE2_V 0xffffffff -#define LP_AON_LP_AON_STORE2_S 0 - -/* LP_AON_STORE3_REG register - * need_des - */ - -#define LP_AON_STORE3_REG (DR_REG_LP_AON_BASE + 0xc) - -/* LP_AON_LP_AON_STORE3 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - -#define LP_AON_LP_AON_STORE3 0xffffffff -#define LP_AON_LP_AON_STORE3_M (LP_AON_LP_AON_STORE3_V << LP_AON_LP_AON_STORE3_S) -#define LP_AON_LP_AON_STORE3_V 0xffffffff -#define LP_AON_LP_AON_STORE3_S 0 - -/* LP_AON_STORE4_REG register - * need_des - */ - -#define LP_AON_STORE4_REG (DR_REG_LP_AON_BASE + 0x10) - -/* LP_AON_LP_AON_STORE4 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - -#define LP_AON_LP_AON_STORE4 0xffffffff -#define LP_AON_LP_AON_STORE4_M (LP_AON_LP_AON_STORE4_V << LP_AON_LP_AON_STORE4_S) -#define LP_AON_LP_AON_STORE4_V 0xffffffff -#define LP_AON_LP_AON_STORE4_S 0 - -/* LP_AON_STORE5_REG register - * need_des - */ - -#define LP_AON_STORE5_REG (DR_REG_LP_AON_BASE + 0x14) - -/* LP_AON_LP_AON_STORE5 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - -#define LP_AON_LP_AON_STORE5 0xffffffff -#define LP_AON_LP_AON_STORE5_M (LP_AON_LP_AON_STORE5_V << LP_AON_LP_AON_STORE5_S) -#define LP_AON_LP_AON_STORE5_V 0xffffffff -#define LP_AON_LP_AON_STORE5_S 0 - -/* LP_AON_STORE6_REG register - * need_des - */ - -#define LP_AON_STORE6_REG (DR_REG_LP_AON_BASE + 0x18) - -/* LP_AON_LP_AON_STORE6 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - -#define LP_AON_LP_AON_STORE6 0xffffffff -#define LP_AON_LP_AON_STORE6_M (LP_AON_LP_AON_STORE6_V << LP_AON_LP_AON_STORE6_S) -#define LP_AON_LP_AON_STORE6_V 0xffffffff -#define LP_AON_LP_AON_STORE6_S 0 - -/* LP_AON_STORE7_REG register - * need_des - */ - -#define LP_AON_STORE7_REG (DR_REG_LP_AON_BASE + 0x1c) - -/* LP_AON_LP_AON_STORE7 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - -#define LP_AON_LP_AON_STORE7 0xffffffff -#define LP_AON_LP_AON_STORE7_M (LP_AON_LP_AON_STORE7_V << LP_AON_LP_AON_STORE7_S) -#define LP_AON_LP_AON_STORE7_V 0xffffffff -#define LP_AON_LP_AON_STORE7_S 0 - -/* LP_AON_STORE8_REG register - * need_des - */ - -#define LP_AON_STORE8_REG (DR_REG_LP_AON_BASE + 0x20) - -/* LP_AON_LP_AON_STORE8 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - -#define LP_AON_LP_AON_STORE8 0xffffffff -#define LP_AON_LP_AON_STORE8_M (LP_AON_LP_AON_STORE8_V << LP_AON_LP_AON_STORE8_S) -#define LP_AON_LP_AON_STORE8_V 0xffffffff -#define LP_AON_LP_AON_STORE8_S 0 - -/* LP_AON_STORE9_REG register - * need_des - */ - -#define LP_AON_STORE9_REG (DR_REG_LP_AON_BASE + 0x24) - -/* LP_AON_LP_AON_STORE9 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - -#define LP_AON_LP_AON_STORE9 0xffffffff -#define LP_AON_LP_AON_STORE9_M (LP_AON_LP_AON_STORE9_V << LP_AON_LP_AON_STORE9_S) -#define LP_AON_LP_AON_STORE9_V 0xffffffff -#define LP_AON_LP_AON_STORE9_S 0 - -/* LP_AON_GPIO_MUX_REG register - * need_des - */ - -#define LP_AON_GPIO_MUX_REG (DR_REG_LP_AON_BASE + 0x28) - -/* LP_AON_GPIO_MUX_SEL : R/W; bitpos: [7:0]; default: 0; - * need_des - */ - -#define LP_AON_GPIO_MUX_SEL 0x000000ff -#define LP_AON_GPIO_MUX_SEL_M (LP_AON_GPIO_MUX_SEL_V << LP_AON_GPIO_MUX_SEL_S) -#define LP_AON_GPIO_MUX_SEL_V 0x000000ff -#define LP_AON_GPIO_MUX_SEL_S 0 - -/* LP_AON_GPIO_HOLD0_REG register - * need_des - */ - -#define LP_AON_GPIO_HOLD0_REG (DR_REG_LP_AON_BASE + 0x2c) - -/* LP_AON_GPIO_HOLD0 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - -#define LP_AON_GPIO_HOLD0 0xffffffff -#define LP_AON_GPIO_HOLD0_M (LP_AON_GPIO_HOLD0_V << LP_AON_GPIO_HOLD0_S) -#define LP_AON_GPIO_HOLD0_V 0xffffffff -#define LP_AON_GPIO_HOLD0_S 0 - -/* LP_AON_GPIO_HOLD1_REG register - * need_des - */ - -#define LP_AON_GPIO_HOLD1_REG (DR_REG_LP_AON_BASE + 0x30) - -/* LP_AON_GPIO_HOLD1 : R/W; bitpos: [31:0]; default: 0; - * need_des - */ - -#define LP_AON_GPIO_HOLD1 0xffffffff -#define LP_AON_GPIO_HOLD1_M (LP_AON_GPIO_HOLD1_V << LP_AON_GPIO_HOLD1_S) -#define LP_AON_GPIO_HOLD1_V 0xffffffff -#define LP_AON_GPIO_HOLD1_S 0 - -/* LP_AON_SYS_CFG_REG register - * need_des - */ - -#define LP_AON_SYS_CFG_REG (DR_REG_LP_AON_BASE + 0x34) - -/* LP_AON_HPSYS_SW_RESET : WT; bitpos: [31]; default: 0; - * need_des - */ - -#define LP_AON_HPSYS_SW_RESET (BIT(31)) -#define LP_AON_HPSYS_SW_RESET_M (LP_AON_HPSYS_SW_RESET_V << LP_AON_HPSYS_SW_RESET_S) -#define LP_AON_HPSYS_SW_RESET_V 0x00000001 -#define LP_AON_HPSYS_SW_RESET_S 31 - -/* LP_AON_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [30]; default: 0; - * need_des - */ - -#define LP_AON_FORCE_DOWNLOAD_BOOT (BIT(30)) -#define LP_AON_FORCE_DOWNLOAD_BOOT_M (LP_AON_FORCE_DOWNLOAD_BOOT_V << LP_AON_FORCE_DOWNLOAD_BOOT_S) -#define LP_AON_FORCE_DOWNLOAD_BOOT_V 0x00000001 -#define LP_AON_FORCE_DOWNLOAD_BOOT_S 30 - -/* LP_AON_CPUCORE0_CFG_REG register - * need_des - */ - -#define LP_AON_CPUCORE0_CFG_REG (DR_REG_LP_AON_BASE + 0x38) - -/* LP_AON_CPU_CORE0_DRESET_MASK : R/W; bitpos: [31]; default: 0; - * need_des - */ - -#define LP_AON_CPU_CORE0_DRESET_MASK (BIT(31)) -#define LP_AON_CPU_CORE0_DRESET_MASK_M (LP_AON_CPU_CORE0_DRESET_MASK_V << LP_AON_CPU_CORE0_DRESET_MASK_S) -#define LP_AON_CPU_CORE0_DRESET_MASK_V 0x00000001 -#define LP_AON_CPU_CORE0_DRESET_MASK_S 31 - -/* LP_AON_CPU_CORE0_STAT_VECTOR_SEL : R/W; bitpos: [30]; default: 1; - * need_des - */ - -#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL (BIT(30)) -#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_M (LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V << LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S) -#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_V 0x00000001 -#define LP_AON_CPU_CORE0_STAT_VECTOR_SEL_S 30 - -/* LP_AON_CPU_CORE0_OCD_HALT_ON_RESET : R/W; bitpos: [29]; default: 0; - * need_des - */ - -#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET (BIT(29)) -#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_M (LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V << LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S) -#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_V 0x00000001 -#define LP_AON_CPU_CORE0_OCD_HALT_ON_RESET_S 29 - -/* LP_AON_CPU_CORE0_SW_RESET : WT; bitpos: [28]; default: 0; - * need_des - */ - -#define LP_AON_CPU_CORE0_SW_RESET (BIT(28)) -#define LP_AON_CPU_CORE0_SW_RESET_M (LP_AON_CPU_CORE0_SW_RESET_V << LP_AON_CPU_CORE0_SW_RESET_S) -#define LP_AON_CPU_CORE0_SW_RESET_V 0x00000001 -#define LP_AON_CPU_CORE0_SW_RESET_S 28 - -/* LP_AON_CPU_CORE0_SW_STALL : R/W; bitpos: [7:0]; default: 0; - * need_des - */ - -#define LP_AON_CPU_CORE0_SW_STALL 0x000000ff -#define LP_AON_CPU_CORE0_SW_STALL_M (LP_AON_CPU_CORE0_SW_STALL_V << LP_AON_CPU_CORE0_SW_STALL_S) -#define LP_AON_CPU_CORE0_SW_STALL_V 0x000000ff -#define LP_AON_CPU_CORE0_SW_STALL_S 0 - -/* LP_AON_IO_MUX_REG register - * need_des - */ - -#define LP_AON_IO_MUX_REG (DR_REG_LP_AON_BASE + 0x3c) - -/* LP_AON_IO_MUX_RESET_DISABLE : R/W; bitpos: [31]; default: 0; - * need_des - */ - -#define LP_AON_IO_MUX_RESET_DISABLE (BIT(31)) -#define LP_AON_IO_MUX_RESET_DISABLE_M (LP_AON_IO_MUX_RESET_DISABLE_V << LP_AON_IO_MUX_RESET_DISABLE_S) -#define LP_AON_IO_MUX_RESET_DISABLE_V 0x00000001 -#define LP_AON_IO_MUX_RESET_DISABLE_S 31 - -/* LP_AON_EXT_WAKEUP_CNTL_REG register - * need_des - */ - -#define LP_AON_EXT_WAKEUP_CNTL_REG (DR_REG_LP_AON_BASE + 0x40) - -/* LP_AON_EXT_WAKEUP_FILTER : R/W; bitpos: [31]; default: 0; - * need_des - */ - -#define LP_AON_EXT_WAKEUP_FILTER (BIT(31)) -#define LP_AON_EXT_WAKEUP_FILTER_M (LP_AON_EXT_WAKEUP_FILTER_V << LP_AON_EXT_WAKEUP_FILTER_S) -#define LP_AON_EXT_WAKEUP_FILTER_V 0x00000001 -#define LP_AON_EXT_WAKEUP_FILTER_S 31 - -/* LP_AON_EXT_WAKEUP_LV : R/W; bitpos: [30:23]; default: 0; - * need_des - */ - -#define LP_AON_EXT_WAKEUP_LV 0x000000ff -#define LP_AON_EXT_WAKEUP_LV_M (LP_AON_EXT_WAKEUP_LV_V << LP_AON_EXT_WAKEUP_LV_S) -#define LP_AON_EXT_WAKEUP_LV_V 0x000000ff -#define LP_AON_EXT_WAKEUP_LV_S 23 - -/* LP_AON_EXT_WAKEUP_SEL : R/W; bitpos: [22:15]; default: 0; - * need_des - */ - -#define LP_AON_EXT_WAKEUP_SEL 0x000000ff -#define LP_AON_EXT_WAKEUP_SEL_M (LP_AON_EXT_WAKEUP_SEL_V << LP_AON_EXT_WAKEUP_SEL_S) -#define LP_AON_EXT_WAKEUP_SEL_V 0x000000ff -#define LP_AON_EXT_WAKEUP_SEL_S 15 - -/* LP_AON_EXT_WAKEUP_STATUS_CLR : WT; bitpos: [14]; default: 0; - * need_des - */ - -#define LP_AON_EXT_WAKEUP_STATUS_CLR (BIT(14)) -#define LP_AON_EXT_WAKEUP_STATUS_CLR_M (LP_AON_EXT_WAKEUP_STATUS_CLR_V << LP_AON_EXT_WAKEUP_STATUS_CLR_S) -#define LP_AON_EXT_WAKEUP_STATUS_CLR_V 0x00000001 -#define LP_AON_EXT_WAKEUP_STATUS_CLR_S 14 - -/* LP_AON_EXT_WAKEUP_STATUS : RO; bitpos: [7:0]; default: 0; - * need_des - */ - -#define LP_AON_EXT_WAKEUP_STATUS 0x000000ff -#define LP_AON_EXT_WAKEUP_STATUS_M (LP_AON_EXT_WAKEUP_STATUS_V << LP_AON_EXT_WAKEUP_STATUS_S) -#define LP_AON_EXT_WAKEUP_STATUS_V 0x000000ff -#define LP_AON_EXT_WAKEUP_STATUS_S 0 - -/* LP_AON_USB_REG register - * need_des - */ - -#define LP_AON_USB_REG (DR_REG_LP_AON_BASE + 0x44) - -/* LP_AON_USB_RESET_DISABLE : R/W; bitpos: [31]; default: 0; - * need_des - */ - -#define LP_AON_USB_RESET_DISABLE (BIT(31)) -#define LP_AON_USB_RESET_DISABLE_M (LP_AON_USB_RESET_DISABLE_V << LP_AON_USB_RESET_DISABLE_S) -#define LP_AON_USB_RESET_DISABLE_V 0x00000001 -#define LP_AON_USB_RESET_DISABLE_S 31 - -/* LP_AON_LPBUS_REG register - * need_des - */ - -#define LP_AON_LPBUS_REG (DR_REG_LP_AON_BASE + 0x48) - -/* LP_AON_FAST_MEM_MUX_SEL : R/W; bitpos: [31]; default: 1; - * need_des - */ - -#define LP_AON_FAST_MEM_MUX_SEL (BIT(31)) -#define LP_AON_FAST_MEM_MUX_SEL_M (LP_AON_FAST_MEM_MUX_SEL_V << LP_AON_FAST_MEM_MUX_SEL_S) -#define LP_AON_FAST_MEM_MUX_SEL_V 0x00000001 -#define LP_AON_FAST_MEM_MUX_SEL_S 31 - -/* LP_AON_FAST_MEM_MUX_SEL_UPDATE : WT; bitpos: [30]; default: 0; - * need_des - */ - -#define LP_AON_FAST_MEM_MUX_SEL_UPDATE (BIT(30)) -#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_M (LP_AON_FAST_MEM_MUX_SEL_UPDATE_V << LP_AON_FAST_MEM_MUX_SEL_UPDATE_S) -#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_V 0x00000001 -#define LP_AON_FAST_MEM_MUX_SEL_UPDATE_S 30 - -/* LP_AON_FAST_MEM_MUX_SEL_STATUS : RO; bitpos: [29]; default: 1; - * need_des - */ - -#define LP_AON_FAST_MEM_MUX_SEL_STATUS (BIT(29)) -#define LP_AON_FAST_MEM_MUX_SEL_STATUS_M (LP_AON_FAST_MEM_MUX_SEL_STATUS_V << LP_AON_FAST_MEM_MUX_SEL_STATUS_S) -#define LP_AON_FAST_MEM_MUX_SEL_STATUS_V 0x00000001 -#define LP_AON_FAST_MEM_MUX_SEL_STATUS_S 29 - -/* LP_AON_FAST_MEM_MUX_FSM_IDLE : RO; bitpos: [28]; default: 1; - * need_des - */ - -#define LP_AON_FAST_MEM_MUX_FSM_IDLE (BIT(28)) -#define LP_AON_FAST_MEM_MUX_FSM_IDLE_M (LP_AON_FAST_MEM_MUX_FSM_IDLE_V << LP_AON_FAST_MEM_MUX_FSM_IDLE_S) -#define LP_AON_FAST_MEM_MUX_FSM_IDLE_V 0x00000001 -#define LP_AON_FAST_MEM_MUX_FSM_IDLE_S 28 - -/* LP_AON_FAST_MEM_RA : R/W; bitpos: [23:22]; default: 0; - * This field controls fast memory RA parameter. - */ - -#define LP_AON_FAST_MEM_RA 0x00000003 -#define LP_AON_FAST_MEM_RA_M (LP_AON_FAST_MEM_RA_V << LP_AON_FAST_MEM_RA_S) -#define LP_AON_FAST_MEM_RA_V 0x00000003 -#define LP_AON_FAST_MEM_RA_S 22 - -/* LP_AON_FAST_MEM_WA : R/W; bitpos: [21:19]; default: 4; - * This field controls fast memory WA parameter. - */ - -#define LP_AON_FAST_MEM_WA 0x00000007 -#define LP_AON_FAST_MEM_WA_M (LP_AON_FAST_MEM_WA_V << LP_AON_FAST_MEM_WA_S) -#define LP_AON_FAST_MEM_WA_V 0x00000007 -#define LP_AON_FAST_MEM_WA_S 19 - -/* LP_AON_FAST_MEM_WPULSE : R/W; bitpos: [18:16]; default: 0; - * This field controls fast memory WPULSE parameter. - */ - -#define LP_AON_FAST_MEM_WPULSE 0x00000007 -#define LP_AON_FAST_MEM_WPULSE_M (LP_AON_FAST_MEM_WPULSE_V << LP_AON_FAST_MEM_WPULSE_S) -#define LP_AON_FAST_MEM_WPULSE_V 0x00000007 -#define LP_AON_FAST_MEM_WPULSE_S 16 - -/* LP_AON_SDIO_ACTIVE_REG register - * need_des - */ - -#define LP_AON_SDIO_ACTIVE_REG (DR_REG_LP_AON_BASE + 0x4c) - -/* LP_AON_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 10; - * need_des - */ - -#define LP_AON_SDIO_ACT_DNUM 0x000003ff -#define LP_AON_SDIO_ACT_DNUM_M (LP_AON_SDIO_ACT_DNUM_V << LP_AON_SDIO_ACT_DNUM_S) -#define LP_AON_SDIO_ACT_DNUM_V 0x000003ff -#define LP_AON_SDIO_ACT_DNUM_S 22 - -/* LP_AON_LPCORE_REG register - * need_des - */ - -#define LP_AON_LPCORE_REG (DR_REG_LP_AON_BASE + 0x50) - -/* LP_AON_LPCORE_DISABLE : R/W; bitpos: [31]; default: 0; - * need_des - */ - -#define LP_AON_LPCORE_DISABLE (BIT(31)) -#define LP_AON_LPCORE_DISABLE_M (LP_AON_LPCORE_DISABLE_V << LP_AON_LPCORE_DISABLE_S) -#define LP_AON_LPCORE_DISABLE_V 0x00000001 -#define LP_AON_LPCORE_DISABLE_S 31 - -/* LP_AON_LPCORE_ETM_WAKEUP_FLAG : R/WTC/SS; bitpos: [1]; default: 0; - * need_des - */ - -#define LP_AON_LPCORE_ETM_WAKEUP_FLAG (BIT(1)) -#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_S) -#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_V 0x00000001 -#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_S 1 - -/* LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR : WT; bitpos: [0]; default: 0; - * need_des - */ - -#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR (BIT(0)) -#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_M (LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V << LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S) -#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_V 0x00000001 -#define LP_AON_LPCORE_ETM_WAKEUP_FLAG_CLR_S 0 - -/* LP_AON_SAR_CCT_REG register - * need_des - */ - -#define LP_AON_SAR_CCT_REG (DR_REG_LP_AON_BASE + 0x54) - -/* LP_AON_SAR2_PWDET_CCT : R/W; bitpos: [31:29]; default: 0; - * need_des - */ - -#define LP_AON_SAR2_PWDET_CCT 0x00000007 -#define LP_AON_SAR2_PWDET_CCT_M (LP_AON_SAR2_PWDET_CCT_V << LP_AON_SAR2_PWDET_CCT_S) -#define LP_AON_SAR2_PWDET_CCT_V 0x00000007 -#define LP_AON_SAR2_PWDET_CCT_S 29 - -/* LP_AON_DATE_REG register - * need_des - */ - -#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc) - -/* LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0; - * need_des - */ - -#define LP_AON_CLK_EN (BIT(31)) -#define LP_AON_CLK_EN_M (LP_AON_CLK_EN_V << LP_AON_CLK_EN_S) -#define LP_AON_CLK_EN_V 0x00000001 -#define LP_AON_CLK_EN_S 31 - -/* LP_AON_DATE : R/W; bitpos: [30:0]; default: 35672704; - * need_des - */ - -#define LP_AON_DATE 0x7fffffff -#define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S) -#define LP_AON_DATE_V 0x7fffffff -#define LP_AON_DATE_S 0 - -#endif /* __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_LP_AON_H */ diff --git a/arch/risc-v/src/esp32c6/hardware/esp32c6_pcr.h b/arch/risc-v/src/esp32c6/hardware/esp32c6_pcr.h deleted file mode 100644 index f5c87af89aa1d..0000000000000 --- a/arch/risc-v/src/esp32c6/hardware/esp32c6_pcr.h +++ /dev/null @@ -1,2645 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/hardware/esp32c6_pcr.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_PCR_H -#define __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_PCR_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32c6_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* PCR_UART0_CONF_REG register - * UART0 configuration register - */ - -#define PCR_UART0_CONF_REG (DR_REG_PCR_BASE + 0x0) - -/* PCR_UART0_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart0 module - */ - -#define PCR_UART0_RST_EN (BIT(1)) -#define PCR_UART0_RST_EN_M (PCR_UART0_RST_EN_V << PCR_UART0_RST_EN_S) -#define PCR_UART0_RST_EN_V 0x00000001 -#define PCR_UART0_RST_EN_S 1 - -/* PCR_UART0_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable uart0 apb clock - */ - -#define PCR_UART0_CLK_EN (BIT(0)) -#define PCR_UART0_CLK_EN_M (PCR_UART0_CLK_EN_V << PCR_UART0_CLK_EN_S) -#define PCR_UART0_CLK_EN_V 0x00000001 -#define PCR_UART0_CLK_EN_S 0 - -/* PCR_UART0_SCLK_CONF_REG register - * UART0_SCLK configuration register - */ - -#define PCR_UART0_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x4) - -/* PCR_UART0_SCLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable uart0 function clock - */ - -#define PCR_UART0_SCLK_EN (BIT(22)) -#define PCR_UART0_SCLK_EN_M (PCR_UART0_SCLK_EN_V << PCR_UART0_SCLK_EN_S) -#define PCR_UART0_SCLK_EN_V 0x00000001 -#define PCR_UART0_SCLK_EN_S 22 - -/* PCR_UART0_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; - * set this field to select clock-source. 0: do not select anyone clock, 1: - * 80MHz, 2: FOSC, 3(default): XTAL. - */ - -#define PCR_UART0_SCLK_SEL 0x00000003 -#define PCR_UART0_SCLK_SEL_M (PCR_UART0_SCLK_SEL_V << PCR_UART0_SCLK_SEL_S) -#define PCR_UART0_SCLK_SEL_V 0x00000003 -#define PCR_UART0_SCLK_SEL_S 20 - -/* PCR_UART0_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; - * The integral part of the frequency divider factor of the uart0 function - * clock. - */ - -#define PCR_UART0_SCLK_DIV_NUM 0x000000ff -#define PCR_UART0_SCLK_DIV_NUM_M (PCR_UART0_SCLK_DIV_NUM_V << PCR_UART0_SCLK_DIV_NUM_S) -#define PCR_UART0_SCLK_DIV_NUM_V 0x000000ff -#define PCR_UART0_SCLK_DIV_NUM_S 12 - -/* PCR_UART0_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor of the uart0 function clock. - */ - -#define PCR_UART0_SCLK_DIV_B 0x0000003f -#define PCR_UART0_SCLK_DIV_B_M (PCR_UART0_SCLK_DIV_B_V << PCR_UART0_SCLK_DIV_B_S) -#define PCR_UART0_SCLK_DIV_B_V 0x0000003f -#define PCR_UART0_SCLK_DIV_B_S 6 - -/* PCR_UART0_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor of the uart0 function - * clock. - */ - -#define PCR_UART0_SCLK_DIV_A 0x0000003f -#define PCR_UART0_SCLK_DIV_A_M (PCR_UART0_SCLK_DIV_A_V << PCR_UART0_SCLK_DIV_A_S) -#define PCR_UART0_SCLK_DIV_A_V 0x0000003f -#define PCR_UART0_SCLK_DIV_A_S 0 - -/* PCR_UART0_PD_CTRL_REG register - * UART0 power control register - */ - -#define PCR_UART0_PD_CTRL_REG (DR_REG_PCR_BASE + 0x8) - -/* PCR_UART0_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; - * Set this bit to force power up UART0 memory. - */ - -#define PCR_UART0_MEM_FORCE_PD (BIT(2)) -#define PCR_UART0_MEM_FORCE_PD_M (PCR_UART0_MEM_FORCE_PD_V << PCR_UART0_MEM_FORCE_PD_S) -#define PCR_UART0_MEM_FORCE_PD_V 0x00000001 -#define PCR_UART0_MEM_FORCE_PD_S 2 - -/* PCR_UART0_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; - * Set this bit to force power down UART0 memory. - */ - -#define PCR_UART0_MEM_FORCE_PU (BIT(1)) -#define PCR_UART0_MEM_FORCE_PU_M (PCR_UART0_MEM_FORCE_PU_V << PCR_UART0_MEM_FORCE_PU_S) -#define PCR_UART0_MEM_FORCE_PU_V 0x00000001 -#define PCR_UART0_MEM_FORCE_PU_S 1 - -/* PCR_UART1_CONF_REG register - * UART1 configuration register - */ - -#define PCR_UART1_CONF_REG (DR_REG_PCR_BASE + 0xc) - -/* PCR_UART1_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uart1 module - */ - -#define PCR_UART1_RST_EN (BIT(1)) -#define PCR_UART1_RST_EN_M (PCR_UART1_RST_EN_V << PCR_UART1_RST_EN_S) -#define PCR_UART1_RST_EN_V 0x00000001 -#define PCR_UART1_RST_EN_S 1 - -/* PCR_UART1_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable uart1 apb clock - */ - -#define PCR_UART1_CLK_EN (BIT(0)) -#define PCR_UART1_CLK_EN_M (PCR_UART1_CLK_EN_V << PCR_UART1_CLK_EN_S) -#define PCR_UART1_CLK_EN_V 0x00000001 -#define PCR_UART1_CLK_EN_S 0 - -/* PCR_UART1_SCLK_CONF_REG register - * UART1_SCLK configuration register - */ - -#define PCR_UART1_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x10) - -/* PCR_UART1_SCLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable uart0 function clock - */ - -#define PCR_UART1_SCLK_EN (BIT(22)) -#define PCR_UART1_SCLK_EN_M (PCR_UART1_SCLK_EN_V << PCR_UART1_SCLK_EN_S) -#define PCR_UART1_SCLK_EN_V 0x00000001 -#define PCR_UART1_SCLK_EN_S 22 - -/* PCR_UART1_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; - * set this field to select clock-source. 0: do not select anyone clock, 1: - * 80MHz, 2: FOSC, 3(default): XTAL. - */ - -#define PCR_UART1_SCLK_SEL 0x00000003 -#define PCR_UART1_SCLK_SEL_M (PCR_UART1_SCLK_SEL_V << PCR_UART1_SCLK_SEL_S) -#define PCR_UART1_SCLK_SEL_V 0x00000003 -#define PCR_UART1_SCLK_SEL_S 20 - -/* PCR_UART1_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; - * The integral part of the frequency divider factor of the uart1 function - * clock. - */ - -#define PCR_UART1_SCLK_DIV_NUM 0x000000ff -#define PCR_UART1_SCLK_DIV_NUM_M (PCR_UART1_SCLK_DIV_NUM_V << PCR_UART1_SCLK_DIV_NUM_S) -#define PCR_UART1_SCLK_DIV_NUM_V 0x000000ff -#define PCR_UART1_SCLK_DIV_NUM_S 12 - -/* PCR_UART1_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor of the uart1 function clock. - */ - -#define PCR_UART1_SCLK_DIV_B 0x0000003f -#define PCR_UART1_SCLK_DIV_B_M (PCR_UART1_SCLK_DIV_B_V << PCR_UART1_SCLK_DIV_B_S) -#define PCR_UART1_SCLK_DIV_B_V 0x0000003f -#define PCR_UART1_SCLK_DIV_B_S 6 - -/* PCR_UART1_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor of the uart1 function - * clock. - */ - -#define PCR_UART1_SCLK_DIV_A 0x0000003f -#define PCR_UART1_SCLK_DIV_A_M (PCR_UART1_SCLK_DIV_A_V << PCR_UART1_SCLK_DIV_A_S) -#define PCR_UART1_SCLK_DIV_A_V 0x0000003f -#define PCR_UART1_SCLK_DIV_A_S 0 - -/* PCR_UART1_PD_CTRL_REG register - * UART1 power control register - */ - -#define PCR_UART1_PD_CTRL_REG (DR_REG_PCR_BASE + 0x14) - -/* PCR_UART1_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; - * Set this bit to force power up UART1 memory. - */ - -#define PCR_UART1_MEM_FORCE_PD (BIT(2)) -#define PCR_UART1_MEM_FORCE_PD_M (PCR_UART1_MEM_FORCE_PD_V << PCR_UART1_MEM_FORCE_PD_S) -#define PCR_UART1_MEM_FORCE_PD_V 0x00000001 -#define PCR_UART1_MEM_FORCE_PD_S 2 - -/* PCR_UART1_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; - * Set this bit to force power down UART1 memory. - */ - -#define PCR_UART1_MEM_FORCE_PU (BIT(1)) -#define PCR_UART1_MEM_FORCE_PU_M (PCR_UART1_MEM_FORCE_PU_V << PCR_UART1_MEM_FORCE_PU_S) -#define PCR_UART1_MEM_FORCE_PU_V 0x00000001 -#define PCR_UART1_MEM_FORCE_PU_S 1 - -/* PCR_MSPI_CONF_REG register - * MSPI configuration register - */ - -#define PCR_MSPI_CONF_REG (DR_REG_PCR_BASE + 0x18) - -/* PCR_MSPI_PLL_CLK_EN : R/W; bitpos: [2]; default: 1; - * Set 1 to enable mspi pll clock - */ - -#define PCR_MSPI_PLL_CLK_EN (BIT(2)) -#define PCR_MSPI_PLL_CLK_EN_M (PCR_MSPI_PLL_CLK_EN_V << PCR_MSPI_PLL_CLK_EN_S) -#define PCR_MSPI_PLL_CLK_EN_V 0x00000001 -#define PCR_MSPI_PLL_CLK_EN_S 2 - -/* PCR_MSPI_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset mspi module - */ - -#define PCR_MSPI_RST_EN (BIT(1)) -#define PCR_MSPI_RST_EN_M (PCR_MSPI_RST_EN_V << PCR_MSPI_RST_EN_S) -#define PCR_MSPI_RST_EN_V 0x00000001 -#define PCR_MSPI_RST_EN_S 1 - -/* PCR_MSPI_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable mspi clock, include mspi pll clock - */ - -#define PCR_MSPI_CLK_EN (BIT(0)) -#define PCR_MSPI_CLK_EN_M (PCR_MSPI_CLK_EN_V << PCR_MSPI_CLK_EN_S) -#define PCR_MSPI_CLK_EN_V 0x00000001 -#define PCR_MSPI_CLK_EN_S 0 - -/* PCR_MSPI_CLK_CONF_REG register - * MSPI_CLK configuration register - */ - -#define PCR_MSPI_CLK_CONF_REG (DR_REG_PCR_BASE + 0x1c) - -/* PCR_MSPI_FAST_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3; - * Set as one within (3,4,5) to generate div4(default)/div5/div6 of - * high-speed clock-source to drive clk_mspi_fast. Only avaiable whe the - * clck-source is a high-speed clock-source such as SPLL. - */ - -#define PCR_MSPI_FAST_HS_DIV_NUM 0x000000ff -#define PCR_MSPI_FAST_HS_DIV_NUM_M (PCR_MSPI_FAST_HS_DIV_NUM_V << PCR_MSPI_FAST_HS_DIV_NUM_S) -#define PCR_MSPI_FAST_HS_DIV_NUM_V 0x000000ff -#define PCR_MSPI_FAST_HS_DIV_NUM_S 8 - -/* PCR_MSPI_FAST_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set as one within (0,1,2) to generate div1(default)/div2/div4 of - * low-speed clock-source to drive clk_mspi_fast. Only avaiable whe the - * clck-source is a low-speed clock-source such as XTAL/FOSC. - */ - -#define PCR_MSPI_FAST_LS_DIV_NUM 0x000000ff -#define PCR_MSPI_FAST_LS_DIV_NUM_M (PCR_MSPI_FAST_LS_DIV_NUM_V << PCR_MSPI_FAST_LS_DIV_NUM_S) -#define PCR_MSPI_FAST_LS_DIV_NUM_V 0x000000ff -#define PCR_MSPI_FAST_LS_DIV_NUM_S 0 - -/* PCR_I2C_CONF_REG register - * I2C configuration register - */ - -#define PCR_I2C_CONF_REG (DR_REG_PCR_BASE + 0x20) - -/* PCR_I2C_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2c module - */ - -#define PCR_I2C_RST_EN (BIT(1)) -#define PCR_I2C_RST_EN_M (PCR_I2C_RST_EN_V << PCR_I2C_RST_EN_S) -#define PCR_I2C_RST_EN_V 0x00000001 -#define PCR_I2C_RST_EN_S 1 - -/* PCR_I2C_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable i2c apb clock - */ - -#define PCR_I2C_CLK_EN (BIT(0)) -#define PCR_I2C_CLK_EN_M (PCR_I2C_CLK_EN_V << PCR_I2C_CLK_EN_S) -#define PCR_I2C_CLK_EN_V 0x00000001 -#define PCR_I2C_CLK_EN_S 0 - -/* PCR_I2C_SCLK_CONF_REG register - * I2C_SCLK configuration register - */ - -#define PCR_I2C_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x24) - -/* PCR_I2C_SCLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable i2c function clock - */ - -#define PCR_I2C_SCLK_EN (BIT(22)) -#define PCR_I2C_SCLK_EN_M (PCR_I2C_SCLK_EN_V << PCR_I2C_SCLK_EN_S) -#define PCR_I2C_SCLK_EN_V 0x00000001 -#define PCR_I2C_SCLK_EN_S 22 - -/* PCR_I2C_SCLK_SEL : R/W; bitpos: [20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: FOSC. - */ - -#define PCR_I2C_SCLK_SEL (BIT(20)) -#define PCR_I2C_SCLK_SEL_M (PCR_I2C_SCLK_SEL_V << PCR_I2C_SCLK_SEL_S) -#define PCR_I2C_SCLK_SEL_V 0x00000001 -#define PCR_I2C_SCLK_SEL_S 20 - -/* PCR_I2C_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 0; - * The integral part of the frequency divider factor of the i2c function - * clock. - */ - -#define PCR_I2C_SCLK_DIV_NUM 0x000000ff -#define PCR_I2C_SCLK_DIV_NUM_M (PCR_I2C_SCLK_DIV_NUM_V << PCR_I2C_SCLK_DIV_NUM_S) -#define PCR_I2C_SCLK_DIV_NUM_V 0x000000ff -#define PCR_I2C_SCLK_DIV_NUM_S 12 - -/* PCR_I2C_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor of the i2c function clock. - */ - -#define PCR_I2C_SCLK_DIV_B 0x0000003f -#define PCR_I2C_SCLK_DIV_B_M (PCR_I2C_SCLK_DIV_B_V << PCR_I2C_SCLK_DIV_B_S) -#define PCR_I2C_SCLK_DIV_B_V 0x0000003f -#define PCR_I2C_SCLK_DIV_B_S 6 - -/* PCR_I2C_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor of the i2c function - * clock. - */ - -#define PCR_I2C_SCLK_DIV_A 0x0000003f -#define PCR_I2C_SCLK_DIV_A_M (PCR_I2C_SCLK_DIV_A_V << PCR_I2C_SCLK_DIV_A_S) -#define PCR_I2C_SCLK_DIV_A_V 0x0000003f -#define PCR_I2C_SCLK_DIV_A_S 0 - -/* PCR_UHCI_CONF_REG register - * UHCI configuration register - */ - -#define PCR_UHCI_CONF_REG (DR_REG_PCR_BASE + 0x28) - -/* PCR_UHCI_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset uhci module - */ - -#define PCR_UHCI_RST_EN (BIT(1)) -#define PCR_UHCI_RST_EN_M (PCR_UHCI_RST_EN_V << PCR_UHCI_RST_EN_S) -#define PCR_UHCI_RST_EN_V 0x00000001 -#define PCR_UHCI_RST_EN_S 1 - -/* PCR_UHCI_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable uhci clock - */ - -#define PCR_UHCI_CLK_EN (BIT(0)) -#define PCR_UHCI_CLK_EN_M (PCR_UHCI_CLK_EN_V << PCR_UHCI_CLK_EN_S) -#define PCR_UHCI_CLK_EN_V 0x00000001 -#define PCR_UHCI_CLK_EN_S 0 - -/* PCR_RMT_CONF_REG register - * RMT configuration register - */ - -#define PCR_RMT_CONF_REG (DR_REG_PCR_BASE + 0x2c) - -/* PCR_RMT_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset rmt module - */ - -#define PCR_RMT_RST_EN (BIT(1)) -#define PCR_RMT_RST_EN_M (PCR_RMT_RST_EN_V << PCR_RMT_RST_EN_S) -#define PCR_RMT_RST_EN_V 0x00000001 -#define PCR_RMT_RST_EN_S 1 - -/* PCR_RMT_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable rmt apb clock - */ - -#define PCR_RMT_CLK_EN (BIT(0)) -#define PCR_RMT_CLK_EN_M (PCR_RMT_CLK_EN_V << PCR_RMT_CLK_EN_S) -#define PCR_RMT_CLK_EN_V 0x00000001 -#define PCR_RMT_CLK_EN_S 0 - -/* PCR_RMT_SCLK_CONF_REG register - * RMT_SCLK configuration register - */ - -#define PCR_RMT_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x30) - -/* PCR_RMT_SCLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable rmt function clock - */ - -#define PCR_RMT_SCLK_EN (BIT(22)) -#define PCR_RMT_SCLK_EN_M (PCR_RMT_SCLK_EN_V << PCR_RMT_SCLK_EN_S) -#define PCR_RMT_SCLK_EN_V 0x00000001 -#define PCR_RMT_SCLK_EN_S 22 - -/* PCR_RMT_SCLK_SEL : R/W; bitpos: [21:20]; default: 1; - * set this field to select clock-source. 0: do not select anyone clock, - * 1(default): 80MHz, 2: FOSC, 3: XTAL. - */ - -#define PCR_RMT_SCLK_SEL 0x00000003 -#define PCR_RMT_SCLK_SEL_M (PCR_RMT_SCLK_SEL_V << PCR_RMT_SCLK_SEL_S) -#define PCR_RMT_SCLK_SEL_V 0x00000003 -#define PCR_RMT_SCLK_SEL_S 20 - -/* PCR_RMT_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; - * The integral part of the frequency divider factor of the rmt function - * clock. - */ - -#define PCR_RMT_SCLK_DIV_NUM 0x000000ff -#define PCR_RMT_SCLK_DIV_NUM_M (PCR_RMT_SCLK_DIV_NUM_V << PCR_RMT_SCLK_DIV_NUM_S) -#define PCR_RMT_SCLK_DIV_NUM_V 0x000000ff -#define PCR_RMT_SCLK_DIV_NUM_S 12 - -/* PCR_RMT_SCLK_DIV_B : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor of the rmt function clock. - */ - -#define PCR_RMT_SCLK_DIV_B 0x0000003f -#define PCR_RMT_SCLK_DIV_B_M (PCR_RMT_SCLK_DIV_B_V << PCR_RMT_SCLK_DIV_B_S) -#define PCR_RMT_SCLK_DIV_B_V 0x0000003f -#define PCR_RMT_SCLK_DIV_B_S 6 - -/* PCR_RMT_SCLK_DIV_A : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor of the rmt function - * clock. - */ - -#define PCR_RMT_SCLK_DIV_A 0x0000003f -#define PCR_RMT_SCLK_DIV_A_M (PCR_RMT_SCLK_DIV_A_V << PCR_RMT_SCLK_DIV_A_S) -#define PCR_RMT_SCLK_DIV_A_V 0x0000003f -#define PCR_RMT_SCLK_DIV_A_S 0 - -/* PCR_LEDC_CONF_REG register - * LEDC configuration register - */ - -#define PCR_LEDC_CONF_REG (DR_REG_PCR_BASE + 0x34) - -/* PCR_LEDC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ledc module - */ - -#define PCR_LEDC_RST_EN (BIT(1)) -#define PCR_LEDC_RST_EN_M (PCR_LEDC_RST_EN_V << PCR_LEDC_RST_EN_S) -#define PCR_LEDC_RST_EN_V 0x00000001 -#define PCR_LEDC_RST_EN_S 1 - -/* PCR_LEDC_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable ledc apb clock - */ - -#define PCR_LEDC_CLK_EN (BIT(0)) -#define PCR_LEDC_CLK_EN_M (PCR_LEDC_CLK_EN_V << PCR_LEDC_CLK_EN_S) -#define PCR_LEDC_CLK_EN_V 0x00000001 -#define PCR_LEDC_CLK_EN_S 0 - -/* PCR_LEDC_SCLK_CONF_REG register - * LEDC_SCLK configuration register - */ - -#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x38) - -/* PCR_LEDC_SCLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable ledc function clock - */ - -#define PCR_LEDC_SCLK_EN (BIT(22)) -#define PCR_LEDC_SCLK_EN_M (PCR_LEDC_SCLK_EN_V << PCR_LEDC_SCLK_EN_S) -#define PCR_LEDC_SCLK_EN_V 0x00000001 -#define PCR_LEDC_SCLK_EN_S 22 - -/* PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0; - * set this field to select clock-source. 0(default): do not select anyone - * clock, 1: 80MHz, 2: FOSC, 3: XTAL. - */ - -#define PCR_LEDC_SCLK_SEL 0x00000003 -#define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S) -#define PCR_LEDC_SCLK_SEL_V 0x00000003 -#define PCR_LEDC_SCLK_SEL_S 20 - -/* PCR_TIMERGROUP0_CONF_REG register - * TIMERGROUP0 configuration register - */ - -#define PCR_TIMERGROUP0_CONF_REG (DR_REG_PCR_BASE + 0x3c) - -/* PCR_TG0_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group0 module - */ - -#define PCR_TG0_RST_EN (BIT(1)) -#define PCR_TG0_RST_EN_M (PCR_TG0_RST_EN_V << PCR_TG0_RST_EN_S) -#define PCR_TG0_RST_EN_V 0x00000001 -#define PCR_TG0_RST_EN_S 1 - -/* PCR_TG0_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable timer_group0 apb clock - */ - -#define PCR_TG0_CLK_EN (BIT(0)) -#define PCR_TG0_CLK_EN_M (PCR_TG0_CLK_EN_V << PCR_TG0_CLK_EN_S) -#define PCR_TG0_CLK_EN_V 0x00000001 -#define PCR_TG0_CLK_EN_S 0 - -/* PCR_TIMERGROUP0_TIMER_CLK_CONF_REG register - * TIMERGROUP0_TIMER_CLK configuration register - */ - -#define PCR_TIMERGROUP0_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x40) - -/* PCR_TG0_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable timer_group0 timer clock - */ - -#define PCR_TG0_TIMER_CLK_EN (BIT(22)) -#define PCR_TG0_TIMER_CLK_EN_M (PCR_TG0_TIMER_CLK_EN_V << PCR_TG0_TIMER_CLK_EN_S) -#define PCR_TG0_TIMER_CLK_EN_V 0x00000001 -#define PCR_TG0_TIMER_CLK_EN_S 22 - -/* PCR_TG0_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: - * FOSC, 3: reserved. - */ - -#define PCR_TG0_TIMER_CLK_SEL 0x00000003 -#define PCR_TG0_TIMER_CLK_SEL_M (PCR_TG0_TIMER_CLK_SEL_V << PCR_TG0_TIMER_CLK_SEL_S) -#define PCR_TG0_TIMER_CLK_SEL_V 0x00000003 -#define PCR_TG0_TIMER_CLK_SEL_S 20 - -/* PCR_TIMERGROUP0_WDT_CLK_CONF_REG register - * TIMERGROUP0_WDT_CLK configuration register - */ - -#define PCR_TIMERGROUP0_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x44) - -/* PCR_TG0_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable timer_group0 wdt clock - */ - -#define PCR_TG0_WDT_CLK_EN (BIT(22)) -#define PCR_TG0_WDT_CLK_EN_M (PCR_TG0_WDT_CLK_EN_V << PCR_TG0_WDT_CLK_EN_S) -#define PCR_TG0_WDT_CLK_EN_V 0x00000001 -#define PCR_TG0_WDT_CLK_EN_S 22 - -/* PCR_TG0_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: - * FOSC, 3: reserved. - */ - -#define PCR_TG0_WDT_CLK_SEL 0x00000003 -#define PCR_TG0_WDT_CLK_SEL_M (PCR_TG0_WDT_CLK_SEL_V << PCR_TG0_WDT_CLK_SEL_S) -#define PCR_TG0_WDT_CLK_SEL_V 0x00000003 -#define PCR_TG0_WDT_CLK_SEL_S 20 - -/* PCR_TIMERGROUP1_CONF_REG register - * TIMERGROUP1 configuration register - */ - -#define PCR_TIMERGROUP1_CONF_REG (DR_REG_PCR_BASE + 0x48) - -/* PCR_TG1_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset timer_group1 module - */ - -#define PCR_TG1_RST_EN (BIT(1)) -#define PCR_TG1_RST_EN_M (PCR_TG1_RST_EN_V << PCR_TG1_RST_EN_S) -#define PCR_TG1_RST_EN_V 0x00000001 -#define PCR_TG1_RST_EN_S 1 - -/* PCR_TG1_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable timer_group1 apb clock - */ - -#define PCR_TG1_CLK_EN (BIT(0)) -#define PCR_TG1_CLK_EN_M (PCR_TG1_CLK_EN_V << PCR_TG1_CLK_EN_S) -#define PCR_TG1_CLK_EN_V 0x00000001 -#define PCR_TG1_CLK_EN_S 0 - -/* PCR_TIMERGROUP1_TIMER_CLK_CONF_REG register - * TIMERGROUP1_TIMER_CLK configuration register - */ - -#define PCR_TIMERGROUP1_TIMER_CLK_CONF_REG (DR_REG_PCR_BASE + 0x4c) - -/* PCR_TG1_TIMER_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable timer_group1 timer clock - */ - -#define PCR_TG1_TIMER_CLK_EN (BIT(22)) -#define PCR_TG1_TIMER_CLK_EN_M (PCR_TG1_TIMER_CLK_EN_V << PCR_TG1_TIMER_CLK_EN_S) -#define PCR_TG1_TIMER_CLK_EN_V 0x00000001 -#define PCR_TG1_TIMER_CLK_EN_S 22 - -/* PCR_TG1_TIMER_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: - * FOSC, 3: reserved. - */ - -#define PCR_TG1_TIMER_CLK_SEL 0x00000003 -#define PCR_TG1_TIMER_CLK_SEL_M (PCR_TG1_TIMER_CLK_SEL_V << PCR_TG1_TIMER_CLK_SEL_S) -#define PCR_TG1_TIMER_CLK_SEL_V 0x00000003 -#define PCR_TG1_TIMER_CLK_SEL_S 20 - -/* PCR_TIMERGROUP1_WDT_CLK_CONF_REG register - * TIMERGROUP1_WDT_CLK configuration register - */ - -#define PCR_TIMERGROUP1_WDT_CLK_CONF_REG (DR_REG_PCR_BASE + 0x50) - -/* PCR_TG1_WDT_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable timer_group0 wdt clock - */ - -#define PCR_TG1_WDT_CLK_EN (BIT(22)) -#define PCR_TG1_WDT_CLK_EN_M (PCR_TG1_WDT_CLK_EN_V << PCR_TG1_WDT_CLK_EN_S) -#define PCR_TG1_WDT_CLK_EN_V 0x00000001 -#define PCR_TG1_WDT_CLK_EN_S 22 - -/* PCR_TG1_WDT_CLK_SEL : R/W; bitpos: [21:20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: - * FOSC, 3: reserved. - */ - -#define PCR_TG1_WDT_CLK_SEL 0x00000003 -#define PCR_TG1_WDT_CLK_SEL_M (PCR_TG1_WDT_CLK_SEL_V << PCR_TG1_WDT_CLK_SEL_S) -#define PCR_TG1_WDT_CLK_SEL_V 0x00000003 -#define PCR_TG1_WDT_CLK_SEL_S 20 - -/* PCR_SYSTIMER_CONF_REG register - * SYSTIMER configuration register - */ - -#define PCR_SYSTIMER_CONF_REG (DR_REG_PCR_BASE + 0x54) - -/* PCR_SYSTIMER_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset systimer module - */ - -#define PCR_SYSTIMER_RST_EN (BIT(1)) -#define PCR_SYSTIMER_RST_EN_M (PCR_SYSTIMER_RST_EN_V << PCR_SYSTIMER_RST_EN_S) -#define PCR_SYSTIMER_RST_EN_V 0x00000001 -#define PCR_SYSTIMER_RST_EN_S 1 - -/* PCR_SYSTIMER_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable systimer apb clock - */ - -#define PCR_SYSTIMER_CLK_EN (BIT(0)) -#define PCR_SYSTIMER_CLK_EN_M (PCR_SYSTIMER_CLK_EN_V << PCR_SYSTIMER_CLK_EN_S) -#define PCR_SYSTIMER_CLK_EN_V 0x00000001 -#define PCR_SYSTIMER_CLK_EN_S 0 - -/* PCR_SYSTIMER_FUNC_CLK_CONF_REG register - * SYSTIMER_FUNC_CLK configuration register - */ - -#define PCR_SYSTIMER_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x58) - -/* PCR_SYSTIMER_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable systimer function clock - */ - -#define PCR_SYSTIMER_FUNC_CLK_EN (BIT(22)) -#define PCR_SYSTIMER_FUNC_CLK_EN_M (PCR_SYSTIMER_FUNC_CLK_EN_V << PCR_SYSTIMER_FUNC_CLK_EN_S) -#define PCR_SYSTIMER_FUNC_CLK_EN_V 0x00000001 -#define PCR_SYSTIMER_FUNC_CLK_EN_S 22 - -/* PCR_SYSTIMER_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: FOSC. - */ - -#define PCR_SYSTIMER_FUNC_CLK_SEL (BIT(20)) -#define PCR_SYSTIMER_FUNC_CLK_SEL_M (PCR_SYSTIMER_FUNC_CLK_SEL_V << PCR_SYSTIMER_FUNC_CLK_SEL_S) -#define PCR_SYSTIMER_FUNC_CLK_SEL_V 0x00000001 -#define PCR_SYSTIMER_FUNC_CLK_SEL_S 20 - -/* PCR_TWAI0_CONF_REG register - * TWAI0 configuration register - */ - -#define PCR_TWAI0_CONF_REG (DR_REG_PCR_BASE + 0x5c) - -/* PCR_TWAI0_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset twai0 module - */ - -#define PCR_TWAI0_RST_EN (BIT(1)) -#define PCR_TWAI0_RST_EN_M (PCR_TWAI0_RST_EN_V << PCR_TWAI0_RST_EN_S) -#define PCR_TWAI0_RST_EN_V 0x00000001 -#define PCR_TWAI0_RST_EN_S 1 - -/* PCR_TWAI0_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable twai0 apb clock - */ - -#define PCR_TWAI0_CLK_EN (BIT(0)) -#define PCR_TWAI0_CLK_EN_M (PCR_TWAI0_CLK_EN_V << PCR_TWAI0_CLK_EN_S) -#define PCR_TWAI0_CLK_EN_V 0x00000001 -#define PCR_TWAI0_CLK_EN_S 0 - -/* PCR_TWAI0_FUNC_CLK_CONF_REG register - * TWAI0_FUNC_CLK configuration register - */ - -#define PCR_TWAI0_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x60) - -/* PCR_TWAI0_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable twai0 function clock - */ - -#define PCR_TWAI0_FUNC_CLK_EN (BIT(22)) -#define PCR_TWAI0_FUNC_CLK_EN_M (PCR_TWAI0_FUNC_CLK_EN_V << PCR_TWAI0_FUNC_CLK_EN_S) -#define PCR_TWAI0_FUNC_CLK_EN_V 0x00000001 -#define PCR_TWAI0_FUNC_CLK_EN_S 22 - -/* PCR_TWAI0_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: FOSC. - */ - -#define PCR_TWAI0_FUNC_CLK_SEL (BIT(20)) -#define PCR_TWAI0_FUNC_CLK_SEL_M (PCR_TWAI0_FUNC_CLK_SEL_V << PCR_TWAI0_FUNC_CLK_SEL_S) -#define PCR_TWAI0_FUNC_CLK_SEL_V 0x00000001 -#define PCR_TWAI0_FUNC_CLK_SEL_S 20 - -/* PCR_TWAI1_CONF_REG register - * TWAI1 configuration register - */ - -#define PCR_TWAI1_CONF_REG (DR_REG_PCR_BASE + 0x64) - -/* PCR_TWAI1_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset twai1 module - */ - -#define PCR_TWAI1_RST_EN (BIT(1)) -#define PCR_TWAI1_RST_EN_M (PCR_TWAI1_RST_EN_V << PCR_TWAI1_RST_EN_S) -#define PCR_TWAI1_RST_EN_V 0x00000001 -#define PCR_TWAI1_RST_EN_S 1 - -/* PCR_TWAI1_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable twai1 apb clock - */ - -#define PCR_TWAI1_CLK_EN (BIT(0)) -#define PCR_TWAI1_CLK_EN_M (PCR_TWAI1_CLK_EN_V << PCR_TWAI1_CLK_EN_S) -#define PCR_TWAI1_CLK_EN_V 0x00000001 -#define PCR_TWAI1_CLK_EN_S 0 - -/* PCR_TWAI1_FUNC_CLK_CONF_REG register - * TWAI1_FUNC_CLK configuration register - */ - -#define PCR_TWAI1_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0x68) - -/* PCR_TWAI1_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable twai1 function clock - */ - -#define PCR_TWAI1_FUNC_CLK_EN (BIT(22)) -#define PCR_TWAI1_FUNC_CLK_EN_M (PCR_TWAI1_FUNC_CLK_EN_V << PCR_TWAI1_FUNC_CLK_EN_S) -#define PCR_TWAI1_FUNC_CLK_EN_V 0x00000001 -#define PCR_TWAI1_FUNC_CLK_EN_S 22 - -/* PCR_TWAI1_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: FOSC. - */ - -#define PCR_TWAI1_FUNC_CLK_SEL (BIT(20)) -#define PCR_TWAI1_FUNC_CLK_SEL_M (PCR_TWAI1_FUNC_CLK_SEL_V << PCR_TWAI1_FUNC_CLK_SEL_S) -#define PCR_TWAI1_FUNC_CLK_SEL_V 0x00000001 -#define PCR_TWAI1_FUNC_CLK_SEL_S 20 - -/* PCR_I2S_CONF_REG register - * I2S configuration register - */ - -#define PCR_I2S_CONF_REG (DR_REG_PCR_BASE + 0x6c) - -/* PCR_I2S_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset i2s module - */ - -#define PCR_I2S_RST_EN (BIT(1)) -#define PCR_I2S_RST_EN_M (PCR_I2S_RST_EN_V << PCR_I2S_RST_EN_S) -#define PCR_I2S_RST_EN_V 0x00000001 -#define PCR_I2S_RST_EN_S 1 - -/* PCR_I2S_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable i2s apb clock - */ - -#define PCR_I2S_CLK_EN (BIT(0)) -#define PCR_I2S_CLK_EN_M (PCR_I2S_CLK_EN_V << PCR_I2S_CLK_EN_S) -#define PCR_I2S_CLK_EN_V 0x00000001 -#define PCR_I2S_CLK_EN_S 0 - -/* PCR_I2S_TX_CLKM_CONF_REG register - * I2S_TX_CLKM configuration register - */ - -#define PCR_I2S_TX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x70) - -/* PCR_I2S_TX_CLKM_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable i2s_tx function clock - */ - -#define PCR_I2S_TX_CLKM_EN (BIT(22)) -#define PCR_I2S_TX_CLKM_EN_M (PCR_I2S_TX_CLKM_EN_V << PCR_I2S_TX_CLKM_EN_S) -#define PCR_I2S_TX_CLKM_EN_V 0x00000001 -#define PCR_I2S_TX_CLKM_EN_S 22 - -/* PCR_I2S_TX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: - * I2S_MCLK_in. - */ - -#define PCR_I2S_TX_CLKM_SEL 0x00000003 -#define PCR_I2S_TX_CLKM_SEL_M (PCR_I2S_TX_CLKM_SEL_V << PCR_I2S_TX_CLKM_SEL_S) -#define PCR_I2S_TX_CLKM_SEL_V 0x00000003 -#define PCR_I2S_TX_CLKM_SEL_S 20 - -/* PCR_I2S_TX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; - * Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). - * There will be (a-b) * n-div and b * (n+1)-div. So the average - * combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * - * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div. - */ - -#define PCR_I2S_TX_CLKM_DIV_NUM 0x000000ff -#define PCR_I2S_TX_CLKM_DIV_NUM_M (PCR_I2S_TX_CLKM_DIV_NUM_V << PCR_I2S_TX_CLKM_DIV_NUM_S) -#define PCR_I2S_TX_CLKM_DIV_NUM_V 0x000000ff -#define PCR_I2S_TX_CLKM_DIV_NUM_S 12 - -/* PCR_I2S_TX_CLKM_DIV_CONF_REG register - * I2S_TX_CLKM_DIV configuration register - */ - -#define PCR_I2S_TX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x74) - -/* PCR_I2S_TX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; - * For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the - * value of I2S_TX_CLKM_DIV_YN1 is 1. - */ - -#define PCR_I2S_TX_CLKM_DIV_YN1 (BIT(27)) -#define PCR_I2S_TX_CLKM_DIV_YN1_M (PCR_I2S_TX_CLKM_DIV_YN1_V << PCR_I2S_TX_CLKM_DIV_YN1_S) -#define PCR_I2S_TX_CLKM_DIV_YN1_V 0x00000001 -#define PCR_I2S_TX_CLKM_DIV_YN1_S 27 - -/* PCR_I2S_TX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; - * For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, - * the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1. - */ - -#define PCR_I2S_TX_CLKM_DIV_X 0x000001ff -#define PCR_I2S_TX_CLKM_DIV_X_M (PCR_I2S_TX_CLKM_DIV_X_V << PCR_I2S_TX_CLKM_DIV_X_S) -#define PCR_I2S_TX_CLKM_DIV_X_V 0x000001ff -#define PCR_I2S_TX_CLKM_DIV_X_S 18 - -/* PCR_I2S_TX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; - * For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the - * value of I2S_TX_CLKM_DIV_Y is (a%(a-b)). - */ - -#define PCR_I2S_TX_CLKM_DIV_Y 0x000001ff -#define PCR_I2S_TX_CLKM_DIV_Y_M (PCR_I2S_TX_CLKM_DIV_Y_V << PCR_I2S_TX_CLKM_DIV_Y_S) -#define PCR_I2S_TX_CLKM_DIV_Y_V 0x000001ff -#define PCR_I2S_TX_CLKM_DIV_Y_S 9 - -/* PCR_I2S_TX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; - * For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value - * of I2S_TX_CLKM_DIV_Z is (a-b). - */ - -#define PCR_I2S_TX_CLKM_DIV_Z 0x000001ff -#define PCR_I2S_TX_CLKM_DIV_Z_M (PCR_I2S_TX_CLKM_DIV_Z_V << PCR_I2S_TX_CLKM_DIV_Z_S) -#define PCR_I2S_TX_CLKM_DIV_Z_V 0x000001ff -#define PCR_I2S_TX_CLKM_DIV_Z_S 0 - -/* PCR_I2S_RX_CLKM_CONF_REG register - * I2S_RX_CLKM configuration register - */ - -#define PCR_I2S_RX_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x78) - -/* PCR_I2S_MCLK_SEL : R/W; bitpos: [23]; default: 0; - * This field is used to select master-clock. 0(default): clk_i2s_rx, 1: - * clk_i2s_tx - */ - -#define PCR_I2S_MCLK_SEL (BIT(23)) -#define PCR_I2S_MCLK_SEL_M (PCR_I2S_MCLK_SEL_V << PCR_I2S_MCLK_SEL_S) -#define PCR_I2S_MCLK_SEL_V 0x00000001 -#define PCR_I2S_MCLK_SEL_S 23 - -/* PCR_I2S_RX_CLKM_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable i2s_rx function clock - */ - -#define PCR_I2S_RX_CLKM_EN (BIT(22)) -#define PCR_I2S_RX_CLKM_EN_M (PCR_I2S_RX_CLKM_EN_V << PCR_I2S_RX_CLKM_EN_S) -#define PCR_I2S_RX_CLKM_EN_V 0x00000001 -#define PCR_I2S_RX_CLKM_EN_S 22 - -/* PCR_I2S_RX_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: - * I2S_MCLK_in. - */ - -#define PCR_I2S_RX_CLKM_SEL 0x00000003 -#define PCR_I2S_RX_CLKM_SEL_M (PCR_I2S_RX_CLKM_SEL_V << PCR_I2S_RX_CLKM_SEL_S) -#define PCR_I2S_RX_CLKM_SEL_V 0x00000003 -#define PCR_I2S_RX_CLKM_SEL_S 20 - -/* PCR_I2S_RX_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 2; - * Integral I2S clock divider value - */ - -#define PCR_I2S_RX_CLKM_DIV_NUM 0x000000ff -#define PCR_I2S_RX_CLKM_DIV_NUM_M (PCR_I2S_RX_CLKM_DIV_NUM_V << PCR_I2S_RX_CLKM_DIV_NUM_S) -#define PCR_I2S_RX_CLKM_DIV_NUM_V 0x000000ff -#define PCR_I2S_RX_CLKM_DIV_NUM_S 12 - -/* PCR_I2S_RX_CLKM_DIV_CONF_REG register - * I2S_RX_CLKM_DIV configuration register - */ - -#define PCR_I2S_RX_CLKM_DIV_CONF_REG (DR_REG_PCR_BASE + 0x7c) - -/* PCR_I2S_RX_CLKM_DIV_YN1 : R/W; bitpos: [27]; default: 0; - * For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the - * value of I2S_RX_CLKM_DIV_YN1 is 1. - */ - -#define PCR_I2S_RX_CLKM_DIV_YN1 (BIT(27)) -#define PCR_I2S_RX_CLKM_DIV_YN1_M (PCR_I2S_RX_CLKM_DIV_YN1_V << PCR_I2S_RX_CLKM_DIV_YN1_S) -#define PCR_I2S_RX_CLKM_DIV_YN1_V 0x00000001 -#define PCR_I2S_RX_CLKM_DIV_YN1_S 27 - -/* PCR_I2S_RX_CLKM_DIV_X : R/W; bitpos: [26:18]; default: 0; - * For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, - * the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1. - */ - -#define PCR_I2S_RX_CLKM_DIV_X 0x000001ff -#define PCR_I2S_RX_CLKM_DIV_X_M (PCR_I2S_RX_CLKM_DIV_X_V << PCR_I2S_RX_CLKM_DIV_X_S) -#define PCR_I2S_RX_CLKM_DIV_X_V 0x000001ff -#define PCR_I2S_RX_CLKM_DIV_X_S 18 - -/* PCR_I2S_RX_CLKM_DIV_Y : R/W; bitpos: [17:9]; default: 1; - * For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the - * value of I2S_RX_CLKM_DIV_Y is (a%(a-b)). - */ - -#define PCR_I2S_RX_CLKM_DIV_Y 0x000001ff -#define PCR_I2S_RX_CLKM_DIV_Y_M (PCR_I2S_RX_CLKM_DIV_Y_V << PCR_I2S_RX_CLKM_DIV_Y_S) -#define PCR_I2S_RX_CLKM_DIV_Y_V 0x000001ff -#define PCR_I2S_RX_CLKM_DIV_Y_S 9 - -/* PCR_I2S_RX_CLKM_DIV_Z : R/W; bitpos: [8:0]; default: 0; - * For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value - * of I2S_RX_CLKM_DIV_Z is (a-b). - */ - -#define PCR_I2S_RX_CLKM_DIV_Z 0x000001ff -#define PCR_I2S_RX_CLKM_DIV_Z_M (PCR_I2S_RX_CLKM_DIV_Z_V << PCR_I2S_RX_CLKM_DIV_Z_S) -#define PCR_I2S_RX_CLKM_DIV_Z_V 0x000001ff -#define PCR_I2S_RX_CLKM_DIV_Z_S 0 - -/* PCR_SARADC_CONF_REG register - * SARADC configuration register - */ - -#define PCR_SARADC_CONF_REG (DR_REG_PCR_BASE + 0x80) - -/* PCR_SARADC_REG_RST_EN : R/W; bitpos: [3]; default: 0; - * Set 0 to reset apb_register of saradc module - */ - -#define PCR_SARADC_REG_RST_EN (BIT(3)) -#define PCR_SARADC_REG_RST_EN_M (PCR_SARADC_REG_RST_EN_V << PCR_SARADC_REG_RST_EN_S) -#define PCR_SARADC_REG_RST_EN_V 0x00000001 -#define PCR_SARADC_REG_RST_EN_S 3 - -/* PCR_SARADC_REG_CLK_EN : R/W; bitpos: [2]; default: 1; - * Set 1 to enable saradc apb clock - */ - -#define PCR_SARADC_REG_CLK_EN (BIT(2)) -#define PCR_SARADC_REG_CLK_EN_M (PCR_SARADC_REG_CLK_EN_V << PCR_SARADC_REG_CLK_EN_S) -#define PCR_SARADC_REG_CLK_EN_V 0x00000001 -#define PCR_SARADC_REG_CLK_EN_S 2 - -/* PCR_SARADC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset function_register of saradc module - */ - -#define PCR_SARADC_RST_EN (BIT(1)) -#define PCR_SARADC_RST_EN_M (PCR_SARADC_RST_EN_V << PCR_SARADC_RST_EN_S) -#define PCR_SARADC_RST_EN_V 0x00000001 -#define PCR_SARADC_RST_EN_S 1 - -/* PCR_SARADC_CLK_EN : R/W; bitpos: [0]; default: 1; - * no use - */ - -#define PCR_SARADC_CLK_EN (BIT(0)) -#define PCR_SARADC_CLK_EN_M (PCR_SARADC_CLK_EN_V << PCR_SARADC_CLK_EN_S) -#define PCR_SARADC_CLK_EN_V 0x00000001 -#define PCR_SARADC_CLK_EN_S 0 - -/* PCR_SARADC_CLKM_CONF_REG register - * SARADC_CLKM configuration register - */ - -#define PCR_SARADC_CLKM_CONF_REG (DR_REG_PCR_BASE + 0x84) - -/* PCR_SARADC_CLKM_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable saradc function clock - */ - -#define PCR_SARADC_CLKM_EN (BIT(22)) -#define PCR_SARADC_CLKM_EN_M (PCR_SARADC_CLKM_EN_V << PCR_SARADC_CLKM_EN_S) -#define PCR_SARADC_CLKM_EN_V 0x00000001 -#define PCR_SARADC_CLKM_EN_S 22 - -/* PCR_SARADC_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: - * FOSC, 3: reserved. - */ - -#define PCR_SARADC_CLKM_SEL 0x00000003 -#define PCR_SARADC_CLKM_SEL_M (PCR_SARADC_CLKM_SEL_V << PCR_SARADC_CLKM_SEL_S) -#define PCR_SARADC_CLKM_SEL_V 0x00000003 -#define PCR_SARADC_CLKM_SEL_S 20 - -/* PCR_SARADC_CLKM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; - * The integral part of the frequency divider factor of the saradc function - * clock. - */ - -#define PCR_SARADC_CLKM_DIV_NUM 0x000000ff -#define PCR_SARADC_CLKM_DIV_NUM_M (PCR_SARADC_CLKM_DIV_NUM_V << PCR_SARADC_CLKM_DIV_NUM_S) -#define PCR_SARADC_CLKM_DIV_NUM_V 0x000000ff -#define PCR_SARADC_CLKM_DIV_NUM_S 12 - -/* PCR_SARADC_CLKM_DIV_B : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor of the saradc function - * clock. - */ - -#define PCR_SARADC_CLKM_DIV_B 0x0000003f -#define PCR_SARADC_CLKM_DIV_B_M (PCR_SARADC_CLKM_DIV_B_V << PCR_SARADC_CLKM_DIV_B_S) -#define PCR_SARADC_CLKM_DIV_B_V 0x0000003f -#define PCR_SARADC_CLKM_DIV_B_S 6 - -/* PCR_SARADC_CLKM_DIV_A : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor of the saradc function - * clock. - */ - -#define PCR_SARADC_CLKM_DIV_A 0x0000003f -#define PCR_SARADC_CLKM_DIV_A_M (PCR_SARADC_CLKM_DIV_A_V << PCR_SARADC_CLKM_DIV_A_S) -#define PCR_SARADC_CLKM_DIV_A_V 0x0000003f -#define PCR_SARADC_CLKM_DIV_A_S 0 - -/* PCR_TSENS_CLK_CONF_REG register - * TSENS_CLK configuration register - */ - -#define PCR_TSENS_CLK_CONF_REG (DR_REG_PCR_BASE + 0x88) - -/* PCR_TSENS_RST_EN : R/W; bitpos: [23]; default: 0; - * Set 0 to reset tsens module - */ - -#define PCR_TSENS_RST_EN (BIT(23)) -#define PCR_TSENS_RST_EN_M (PCR_TSENS_RST_EN_V << PCR_TSENS_RST_EN_S) -#define PCR_TSENS_RST_EN_V 0x00000001 -#define PCR_TSENS_RST_EN_S 23 - -/* PCR_TSENS_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable tsens clock - */ - -#define PCR_TSENS_CLK_EN (BIT(22)) -#define PCR_TSENS_CLK_EN_M (PCR_TSENS_CLK_EN_V << PCR_TSENS_CLK_EN_S) -#define PCR_TSENS_CLK_EN_V 0x00000001 -#define PCR_TSENS_CLK_EN_S 22 - -/* PCR_TSENS_CLK_SEL : R/W; bitpos: [20]; default: 0; - * set this field to select clock-source. 0(default): FOSC, 1: XTAL. - */ - -#define PCR_TSENS_CLK_SEL (BIT(20)) -#define PCR_TSENS_CLK_SEL_M (PCR_TSENS_CLK_SEL_V << PCR_TSENS_CLK_SEL_S) -#define PCR_TSENS_CLK_SEL_V 0x00000001 -#define PCR_TSENS_CLK_SEL_S 20 - -/* PCR_USB_DEVICE_CONF_REG register - * USB_DEVICE configuration register - */ - -#define PCR_USB_DEVICE_CONF_REG (DR_REG_PCR_BASE + 0x8c) - -/* PCR_USB_DEVICE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset usb_device module - */ - -#define PCR_USB_DEVICE_RST_EN (BIT(1)) -#define PCR_USB_DEVICE_RST_EN_M (PCR_USB_DEVICE_RST_EN_V << PCR_USB_DEVICE_RST_EN_S) -#define PCR_USB_DEVICE_RST_EN_V 0x00000001 -#define PCR_USB_DEVICE_RST_EN_S 1 - -/* PCR_USB_DEVICE_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable usb_device clock - */ - -#define PCR_USB_DEVICE_CLK_EN (BIT(0)) -#define PCR_USB_DEVICE_CLK_EN_M (PCR_USB_DEVICE_CLK_EN_V << PCR_USB_DEVICE_CLK_EN_S) -#define PCR_USB_DEVICE_CLK_EN_V 0x00000001 -#define PCR_USB_DEVICE_CLK_EN_S 0 - -/* PCR_INTMTX_CONF_REG register - * INTMTX configuration register - */ - -#define PCR_INTMTX_CONF_REG (DR_REG_PCR_BASE + 0x90) - -/* PCR_INTMTX_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset intmtx module - */ - -#define PCR_INTMTX_RST_EN (BIT(1)) -#define PCR_INTMTX_RST_EN_M (PCR_INTMTX_RST_EN_V << PCR_INTMTX_RST_EN_S) -#define PCR_INTMTX_RST_EN_V 0x00000001 -#define PCR_INTMTX_RST_EN_S 1 - -/* PCR_INTMTX_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable intmtx clock - */ - -#define PCR_INTMTX_CLK_EN (BIT(0)) -#define PCR_INTMTX_CLK_EN_M (PCR_INTMTX_CLK_EN_V << PCR_INTMTX_CLK_EN_S) -#define PCR_INTMTX_CLK_EN_V 0x00000001 -#define PCR_INTMTX_CLK_EN_S 0 - -/* PCR_PCNT_CONF_REG register - * PCNT configuration register - */ - -#define PCR_PCNT_CONF_REG (DR_REG_PCR_BASE + 0x94) - -/* PCR_PCNT_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset pcnt module - */ - -#define PCR_PCNT_RST_EN (BIT(1)) -#define PCR_PCNT_RST_EN_M (PCR_PCNT_RST_EN_V << PCR_PCNT_RST_EN_S) -#define PCR_PCNT_RST_EN_V 0x00000001 -#define PCR_PCNT_RST_EN_S 1 - -/* PCR_PCNT_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable pcnt clock - */ - -#define PCR_PCNT_CLK_EN (BIT(0)) -#define PCR_PCNT_CLK_EN_M (PCR_PCNT_CLK_EN_V << PCR_PCNT_CLK_EN_S) -#define PCR_PCNT_CLK_EN_V 0x00000001 -#define PCR_PCNT_CLK_EN_S 0 - -/* PCR_ETM_CONF_REG register - * ETM configuration register - */ - -#define PCR_ETM_CONF_REG (DR_REG_PCR_BASE + 0x98) - -/* PCR_ETM_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset etm module - */ - -#define PCR_ETM_RST_EN (BIT(1)) -#define PCR_ETM_RST_EN_M (PCR_ETM_RST_EN_V << PCR_ETM_RST_EN_S) -#define PCR_ETM_RST_EN_V 0x00000001 -#define PCR_ETM_RST_EN_S 1 - -/* PCR_ETM_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable etm clock - */ - -#define PCR_ETM_CLK_EN (BIT(0)) -#define PCR_ETM_CLK_EN_M (PCR_ETM_CLK_EN_V << PCR_ETM_CLK_EN_S) -#define PCR_ETM_CLK_EN_V 0x00000001 -#define PCR_ETM_CLK_EN_S 0 - -/* PCR_PWM_CONF_REG register - * PWM configuration register - */ - -#define PCR_PWM_CONF_REG (DR_REG_PCR_BASE + 0x9c) - -/* PCR_PWM_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset pwm module - */ - -#define PCR_PWM_RST_EN (BIT(1)) -#define PCR_PWM_RST_EN_M (PCR_PWM_RST_EN_V << PCR_PWM_RST_EN_S) -#define PCR_PWM_RST_EN_V 0x00000001 -#define PCR_PWM_RST_EN_S 1 - -/* PCR_PWM_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable pwm clock - */ - -#define PCR_PWM_CLK_EN (BIT(0)) -#define PCR_PWM_CLK_EN_M (PCR_PWM_CLK_EN_V << PCR_PWM_CLK_EN_S) -#define PCR_PWM_CLK_EN_V 0x00000001 -#define PCR_PWM_CLK_EN_S 0 - -/* PCR_PWM_CLK_CONF_REG register - * PWM_CLK configuration register - */ - -#define PCR_PWM_CLK_CONF_REG (DR_REG_PCR_BASE + 0xa0) - -/* PCR_PWM_CLKM_EN : R/W; bitpos: [22]; default: 1; - * set this field as 1 to activate pwm clkm. - */ - -#define PCR_PWM_CLKM_EN (BIT(22)) -#define PCR_PWM_CLKM_EN_M (PCR_PWM_CLKM_EN_V << PCR_PWM_CLKM_EN_S) -#define PCR_PWM_CLKM_EN_V 0x00000001 -#define PCR_PWM_CLKM_EN_S 22 - -/* PCR_PWM_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * set this field to select clock-source. 0(default): do not select anyone - * clock, 1: 160MHz, 2: XTAL, 3: FOSC. - */ - -#define PCR_PWM_CLKM_SEL 0x00000003 -#define PCR_PWM_CLKM_SEL_M (PCR_PWM_CLKM_SEL_V << PCR_PWM_CLKM_SEL_S) -#define PCR_PWM_CLKM_SEL_V 0x00000003 -#define PCR_PWM_CLKM_SEL_S 20 - -/* PCR_PWM_DIV_NUM : R/W; bitpos: [19:12]; default: 4; - * The integral part of the frequency divider factor of the pwm function - * clock. - */ - -#define PCR_PWM_DIV_NUM 0x000000ff -#define PCR_PWM_DIV_NUM_M (PCR_PWM_DIV_NUM_V << PCR_PWM_DIV_NUM_S) -#define PCR_PWM_DIV_NUM_V 0x000000ff -#define PCR_PWM_DIV_NUM_S 12 - -/* PCR_PARL_IO_CONF_REG register - * PARL_IO configuration register - */ - -#define PCR_PARL_IO_CONF_REG (DR_REG_PCR_BASE + 0xa4) - -/* PCR_PARL_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset parl apb reg - */ - -#define PCR_PARL_RST_EN (BIT(1)) -#define PCR_PARL_RST_EN_M (PCR_PARL_RST_EN_V << PCR_PARL_RST_EN_S) -#define PCR_PARL_RST_EN_V 0x00000001 -#define PCR_PARL_RST_EN_S 1 - -/* PCR_PARL_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable parl apb clock - */ - -#define PCR_PARL_CLK_EN (BIT(0)) -#define PCR_PARL_CLK_EN_M (PCR_PARL_CLK_EN_V << PCR_PARL_CLK_EN_S) -#define PCR_PARL_CLK_EN_V 0x00000001 -#define PCR_PARL_CLK_EN_S 0 - -/* PCR_PARL_CLK_RX_CONF_REG register - * PARL_CLK_RX configuration register - */ - -#define PCR_PARL_CLK_RX_CONF_REG (DR_REG_PCR_BASE + 0xa8) - -/* PCR_PARL_RX_RST_EN : R/W; bitpos: [19]; default: 0; - * Set 0 to reset parl rx module - */ - -#define PCR_PARL_RX_RST_EN (BIT(19)) -#define PCR_PARL_RX_RST_EN_M (PCR_PARL_RX_RST_EN_V << PCR_PARL_RX_RST_EN_S) -#define PCR_PARL_RX_RST_EN_V 0x00000001 -#define PCR_PARL_RX_RST_EN_S 19 - -/* PCR_PARL_CLK_RX_EN : R/W; bitpos: [18]; default: 1; - * Set 1 to enable parl rx clock - */ - -#define PCR_PARL_CLK_RX_EN (BIT(18)) -#define PCR_PARL_CLK_RX_EN_M (PCR_PARL_CLK_RX_EN_V << PCR_PARL_CLK_RX_EN_S) -#define PCR_PARL_CLK_RX_EN_V 0x00000001 -#define PCR_PARL_CLK_RX_EN_S 18 - -/* PCR_PARL_CLK_RX_SEL : R/W; bitpos: [17:16]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: - * FOSC, 3: user clock from pad. - */ - -#define PCR_PARL_CLK_RX_SEL 0x00000003 -#define PCR_PARL_CLK_RX_SEL_M (PCR_PARL_CLK_RX_SEL_V << PCR_PARL_CLK_RX_SEL_S) -#define PCR_PARL_CLK_RX_SEL_V 0x00000003 -#define PCR_PARL_CLK_RX_SEL_S 16 - -/* PCR_PARL_CLK_RX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; - * The integral part of the frequency divider factor of the parl rx clock. - */ - -#define PCR_PARL_CLK_RX_DIV_NUM 0x0000ffff -#define PCR_PARL_CLK_RX_DIV_NUM_M (PCR_PARL_CLK_RX_DIV_NUM_V << PCR_PARL_CLK_RX_DIV_NUM_S) -#define PCR_PARL_CLK_RX_DIV_NUM_V 0x0000ffff -#define PCR_PARL_CLK_RX_DIV_NUM_S 0 - -/* PCR_PARL_CLK_TX_CONF_REG register - * PARL_CLK_TX configuration register - */ - -#define PCR_PARL_CLK_TX_CONF_REG (DR_REG_PCR_BASE + 0xac) - -/* PCR_PARL_TX_RST_EN : R/W; bitpos: [19]; default: 0; - * Set 0 to reset parl tx module - */ - -#define PCR_PARL_TX_RST_EN (BIT(19)) -#define PCR_PARL_TX_RST_EN_M (PCR_PARL_TX_RST_EN_V << PCR_PARL_TX_RST_EN_S) -#define PCR_PARL_TX_RST_EN_V 0x00000001 -#define PCR_PARL_TX_RST_EN_S 19 - -/* PCR_PARL_CLK_TX_EN : R/W; bitpos: [18]; default: 1; - * Set 1 to enable parl tx clock - */ - -#define PCR_PARL_CLK_TX_EN (BIT(18)) -#define PCR_PARL_CLK_TX_EN_M (PCR_PARL_CLK_TX_EN_V << PCR_PARL_CLK_TX_EN_S) -#define PCR_PARL_CLK_TX_EN_V 0x00000001 -#define PCR_PARL_CLK_TX_EN_S 18 - -/* PCR_PARL_CLK_TX_SEL : R/W; bitpos: [17:16]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: 240MHz, 2: - * FOSC, 3: user clock from pad. - */ - -#define PCR_PARL_CLK_TX_SEL 0x00000003 -#define PCR_PARL_CLK_TX_SEL_M (PCR_PARL_CLK_TX_SEL_V << PCR_PARL_CLK_TX_SEL_S) -#define PCR_PARL_CLK_TX_SEL_V 0x00000003 -#define PCR_PARL_CLK_TX_SEL_S 16 - -/* PCR_PARL_CLK_TX_DIV_NUM : R/W; bitpos: [15:0]; default: 0; - * The integral part of the frequency divider factor of the parl tx clock. - */ - -#define PCR_PARL_CLK_TX_DIV_NUM 0x0000ffff -#define PCR_PARL_CLK_TX_DIV_NUM_M (PCR_PARL_CLK_TX_DIV_NUM_V << PCR_PARL_CLK_TX_DIV_NUM_S) -#define PCR_PARL_CLK_TX_DIV_NUM_V 0x0000ffff -#define PCR_PARL_CLK_TX_DIV_NUM_S 0 - -/* PCR_SDIO_SLAVE_CONF_REG register - * SDIO_SLAVE configuration register - */ - -#define PCR_SDIO_SLAVE_CONF_REG (DR_REG_PCR_BASE + 0xb0) - -/* PCR_SDIO_SLAVE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset sdio_slave module - */ - -#define PCR_SDIO_SLAVE_RST_EN (BIT(1)) -#define PCR_SDIO_SLAVE_RST_EN_M (PCR_SDIO_SLAVE_RST_EN_V << PCR_SDIO_SLAVE_RST_EN_S) -#define PCR_SDIO_SLAVE_RST_EN_V 0x00000001 -#define PCR_SDIO_SLAVE_RST_EN_S 1 - -/* PCR_SDIO_SLAVE_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable sdio_slave clock - */ - -#define PCR_SDIO_SLAVE_CLK_EN (BIT(0)) -#define PCR_SDIO_SLAVE_CLK_EN_M (PCR_SDIO_SLAVE_CLK_EN_V << PCR_SDIO_SLAVE_CLK_EN_S) -#define PCR_SDIO_SLAVE_CLK_EN_V 0x00000001 -#define PCR_SDIO_SLAVE_CLK_EN_S 0 - -/* PCR_PVT_MONITOR_CONF_REG register - * PVT_MONITOR configuration register - */ - -#define PCR_PVT_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xb4) - -/* PCR_PVT_MONITOR_SITE3_CLK_EN : R/W; bitpos: [4]; default: 1; - * Set 1 to enable function clock of hp_peri pvt module - */ - -#define PCR_PVT_MONITOR_SITE3_CLK_EN (BIT(4)) -#define PCR_PVT_MONITOR_SITE3_CLK_EN_M (PCR_PVT_MONITOR_SITE3_CLK_EN_V << PCR_PVT_MONITOR_SITE3_CLK_EN_S) -#define PCR_PVT_MONITOR_SITE3_CLK_EN_V 0x00000001 -#define PCR_PVT_MONITOR_SITE3_CLK_EN_S 4 - -/* PCR_PVT_MONITOR_SITE2_CLK_EN : R/W; bitpos: [3]; default: 1; - * Set 1 to enable function clock of cpu pvt module - */ - -#define PCR_PVT_MONITOR_SITE2_CLK_EN (BIT(3)) -#define PCR_PVT_MONITOR_SITE2_CLK_EN_M (PCR_PVT_MONITOR_SITE2_CLK_EN_V << PCR_PVT_MONITOR_SITE2_CLK_EN_S) -#define PCR_PVT_MONITOR_SITE2_CLK_EN_V 0x00000001 -#define PCR_PVT_MONITOR_SITE2_CLK_EN_S 3 - -/* PCR_PVT_MONITOR_SITE1_CLK_EN : R/W; bitpos: [2]; default: 1; - * Set 1 to enable function clock of modem pvt module - */ - -#define PCR_PVT_MONITOR_SITE1_CLK_EN (BIT(2)) -#define PCR_PVT_MONITOR_SITE1_CLK_EN_M (PCR_PVT_MONITOR_SITE1_CLK_EN_V << PCR_PVT_MONITOR_SITE1_CLK_EN_S) -#define PCR_PVT_MONITOR_SITE1_CLK_EN_V 0x00000001 -#define PCR_PVT_MONITOR_SITE1_CLK_EN_S 2 - -/* PCR_PVT_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset all pvt monitor module - */ - -#define PCR_PVT_MONITOR_RST_EN (BIT(1)) -#define PCR_PVT_MONITOR_RST_EN_M (PCR_PVT_MONITOR_RST_EN_V << PCR_PVT_MONITOR_RST_EN_S) -#define PCR_PVT_MONITOR_RST_EN_V 0x00000001 -#define PCR_PVT_MONITOR_RST_EN_S 1 - -/* PCR_PVT_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable apb clock of pvt module - */ - -#define PCR_PVT_MONITOR_CLK_EN (BIT(0)) -#define PCR_PVT_MONITOR_CLK_EN_M (PCR_PVT_MONITOR_CLK_EN_V << PCR_PVT_MONITOR_CLK_EN_S) -#define PCR_PVT_MONITOR_CLK_EN_V 0x00000001 -#define PCR_PVT_MONITOR_CLK_EN_S 0 - -/* PCR_PVT_MONITOR_FUNC_CLK_CONF_REG register - * PVT_MONITOR function clock configuration register - */ - -#define PCR_PVT_MONITOR_FUNC_CLK_CONF_REG (DR_REG_PCR_BASE + 0xb8) - -/* PCR_PVT_MONITOR_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable source clock of pvt sitex - */ - -#define PCR_PVT_MONITOR_FUNC_CLK_EN (BIT(22)) -#define PCR_PVT_MONITOR_FUNC_CLK_EN_M (PCR_PVT_MONITOR_FUNC_CLK_EN_V << PCR_PVT_MONITOR_FUNC_CLK_EN_S) -#define PCR_PVT_MONITOR_FUNC_CLK_EN_V 0x00000001 -#define PCR_PVT_MONITOR_FUNC_CLK_EN_S 22 - -/* PCR_PVT_MONITOR_FUNC_CLK_SEL : R/W; bitpos: [20]; default: 0; - * set this field to select clock-source. 0: XTAL, 1(default): 160MHz drived - * by SPLL divided by 3. - */ - -#define PCR_PVT_MONITOR_FUNC_CLK_SEL (BIT(20)) -#define PCR_PVT_MONITOR_FUNC_CLK_SEL_M (PCR_PVT_MONITOR_FUNC_CLK_SEL_V << PCR_PVT_MONITOR_FUNC_CLK_SEL_S) -#define PCR_PVT_MONITOR_FUNC_CLK_SEL_V 0x00000001 -#define PCR_PVT_MONITOR_FUNC_CLK_SEL_S 20 - -/* PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM : R/W; bitpos: [3:0]; default: 0; - * The integral part of the frequency divider factor of the pvt_monitor - * function clock. - */ - -#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM 0x0000000f -#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_M (PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V << PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S) -#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_V 0x0000000f -#define PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S 0 - -/* PCR_GDMA_CONF_REG register - * GDMA configuration register - */ - -#define PCR_GDMA_CONF_REG (DR_REG_PCR_BASE + 0xbc) - -/* PCR_GDMA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset gdma module - */ - -#define PCR_GDMA_RST_EN (BIT(1)) -#define PCR_GDMA_RST_EN_M (PCR_GDMA_RST_EN_V << PCR_GDMA_RST_EN_S) -#define PCR_GDMA_RST_EN_V 0x00000001 -#define PCR_GDMA_RST_EN_S 1 - -/* PCR_GDMA_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable gdma clock - */ - -#define PCR_GDMA_CLK_EN (BIT(0)) -#define PCR_GDMA_CLK_EN_M (PCR_GDMA_CLK_EN_V << PCR_GDMA_CLK_EN_S) -#define PCR_GDMA_CLK_EN_V 0x00000001 -#define PCR_GDMA_CLK_EN_S 0 - -/* PCR_SPI2_CONF_REG register - * SPI2 configuration register - */ - -#define PCR_SPI2_CONF_REG (DR_REG_PCR_BASE + 0xc0) - -/* PCR_SPI2_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset spi2 module - */ - -#define PCR_SPI2_RST_EN (BIT(1)) -#define PCR_SPI2_RST_EN_M (PCR_SPI2_RST_EN_V << PCR_SPI2_RST_EN_S) -#define PCR_SPI2_RST_EN_V 0x00000001 -#define PCR_SPI2_RST_EN_S 1 - -/* PCR_SPI2_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable spi2 apb clock - */ - -#define PCR_SPI2_CLK_EN (BIT(0)) -#define PCR_SPI2_CLK_EN_M (PCR_SPI2_CLK_EN_V << PCR_SPI2_CLK_EN_S) -#define PCR_SPI2_CLK_EN_V 0x00000001 -#define PCR_SPI2_CLK_EN_S 0 - -/* PCR_SPI2_CLKM_CONF_REG register - * SPI2_CLKM configuration register - */ - -#define PCR_SPI2_CLKM_CONF_REG (DR_REG_PCR_BASE + 0xc4) - -/* PCR_SPI2_CLKM_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable spi2 function clock - */ - -#define PCR_SPI2_CLKM_EN (BIT(22)) -#define PCR_SPI2_CLKM_EN_M (PCR_SPI2_CLKM_EN_V << PCR_SPI2_CLKM_EN_S) -#define PCR_SPI2_CLKM_EN_V 0x00000001 -#define PCR_SPI2_CLKM_EN_S 22 - -/* PCR_SPI2_CLKM_SEL : R/W; bitpos: [21:20]; default: 0; - * set this field to select clock-source. 0(default): XTAL, 1: 80MHz, 2: - * FOSC, 3: reserved. - */ - -#define PCR_SPI2_CLKM_SEL 0x00000003 -#define PCR_SPI2_CLKM_SEL_M (PCR_SPI2_CLKM_SEL_V << PCR_SPI2_CLKM_SEL_S) -#define PCR_SPI2_CLKM_SEL_V 0x00000003 -#define PCR_SPI2_CLKM_SEL_S 20 - -/* PCR_AES_CONF_REG register - * AES configuration register - */ - -#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0xc8) - -/* PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset aes module - */ - -#define PCR_AES_RST_EN (BIT(1)) -#define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S) -#define PCR_AES_RST_EN_V 0x00000001 -#define PCR_AES_RST_EN_S 1 - -/* PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable aes clock - */ - -#define PCR_AES_CLK_EN (BIT(0)) -#define PCR_AES_CLK_EN_M (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S) -#define PCR_AES_CLK_EN_V 0x00000001 -#define PCR_AES_CLK_EN_S 0 - -/* PCR_SHA_CONF_REG register - * SHA configuration register - */ - -#define PCR_SHA_CONF_REG (DR_REG_PCR_BASE + 0xcc) - -/* PCR_SHA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset sha module - */ - -#define PCR_SHA_RST_EN (BIT(1)) -#define PCR_SHA_RST_EN_M (PCR_SHA_RST_EN_V << PCR_SHA_RST_EN_S) -#define PCR_SHA_RST_EN_V 0x00000001 -#define PCR_SHA_RST_EN_S 1 - -/* PCR_SHA_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable sha clock - */ - -#define PCR_SHA_CLK_EN (BIT(0)) -#define PCR_SHA_CLK_EN_M (PCR_SHA_CLK_EN_V << PCR_SHA_CLK_EN_S) -#define PCR_SHA_CLK_EN_V 0x00000001 -#define PCR_SHA_CLK_EN_S 0 - -/* PCR_RSA_CONF_REG register - * RSA configuration register - */ - -#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xd0) - -/* PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset rsa module - */ - -#define PCR_RSA_RST_EN (BIT(1)) -#define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S) -#define PCR_RSA_RST_EN_V 0x00000001 -#define PCR_RSA_RST_EN_S 1 - -/* PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable rsa clock - */ - -#define PCR_RSA_CLK_EN (BIT(0)) -#define PCR_RSA_CLK_EN_M (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S) -#define PCR_RSA_CLK_EN_V 0x00000001 -#define PCR_RSA_CLK_EN_S 0 - -/* PCR_RSA_PD_CTRL_REG register - * RSA power control register - */ - -#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xd4) - -/* PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; - * Set this bit to force power down rsa internal memory. - */ - -#define PCR_RSA_MEM_FORCE_PD (BIT(2)) -#define PCR_RSA_MEM_FORCE_PD_M (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S) -#define PCR_RSA_MEM_FORCE_PD_V 0x00000001 -#define PCR_RSA_MEM_FORCE_PD_S 2 - -/* PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; - * Set this bit to force power up rsa internal memory - */ - -#define PCR_RSA_MEM_FORCE_PU (BIT(1)) -#define PCR_RSA_MEM_FORCE_PU_M (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S) -#define PCR_RSA_MEM_FORCE_PU_V 0x00000001 -#define PCR_RSA_MEM_FORCE_PU_S 1 - -/* PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0; - * Set this bit to power down rsa internal memory. - */ - -#define PCR_RSA_MEM_PD (BIT(0)) -#define PCR_RSA_MEM_PD_M (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S) -#define PCR_RSA_MEM_PD_V 0x00000001 -#define PCR_RSA_MEM_PD_S 0 - -/* PCR_ECC_CONF_REG register - * ECC configuration register - */ - -#define PCR_ECC_CONF_REG (DR_REG_PCR_BASE + 0xd8) - -/* PCR_ECC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ecc module - */ - -#define PCR_ECC_RST_EN (BIT(1)) -#define PCR_ECC_RST_EN_M (PCR_ECC_RST_EN_V << PCR_ECC_RST_EN_S) -#define PCR_ECC_RST_EN_V 0x00000001 -#define PCR_ECC_RST_EN_S 1 - -/* PCR_ECC_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable ecc clock - */ - -#define PCR_ECC_CLK_EN (BIT(0)) -#define PCR_ECC_CLK_EN_M (PCR_ECC_CLK_EN_V << PCR_ECC_CLK_EN_S) -#define PCR_ECC_CLK_EN_V 0x00000001 -#define PCR_ECC_CLK_EN_S 0 - -/* PCR_ECC_PD_CTRL_REG register - * ECC power control register - */ - -#define PCR_ECC_PD_CTRL_REG (DR_REG_PCR_BASE + 0xdc) - -/* PCR_ECC_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; - * Set this bit to force power down ecc internal memory. - */ - -#define PCR_ECC_MEM_FORCE_PD (BIT(2)) -#define PCR_ECC_MEM_FORCE_PD_M (PCR_ECC_MEM_FORCE_PD_V << PCR_ECC_MEM_FORCE_PD_S) -#define PCR_ECC_MEM_FORCE_PD_V 0x00000001 -#define PCR_ECC_MEM_FORCE_PD_S 2 - -/* PCR_ECC_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1; - * Set this bit to force power up ecc internal memory - */ - -#define PCR_ECC_MEM_FORCE_PU (BIT(1)) -#define PCR_ECC_MEM_FORCE_PU_M (PCR_ECC_MEM_FORCE_PU_V << PCR_ECC_MEM_FORCE_PU_S) -#define PCR_ECC_MEM_FORCE_PU_V 0x00000001 -#define PCR_ECC_MEM_FORCE_PU_S 1 - -/* PCR_ECC_MEM_PD : R/W; bitpos: [0]; default: 0; - * Set this bit to power down ecc internal memory. - */ - -#define PCR_ECC_MEM_PD (BIT(0)) -#define PCR_ECC_MEM_PD_M (PCR_ECC_MEM_PD_V << PCR_ECC_MEM_PD_S) -#define PCR_ECC_MEM_PD_V 0x00000001 -#define PCR_ECC_MEM_PD_S 0 - -/* PCR_DS_CONF_REG register - * DS configuration register - */ - -#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xe0) - -/* PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset ds module - */ - -#define PCR_DS_RST_EN (BIT(1)) -#define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S) -#define PCR_DS_RST_EN_V 0x00000001 -#define PCR_DS_RST_EN_S 1 - -/* PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable ds clock - */ - -#define PCR_DS_CLK_EN (BIT(0)) -#define PCR_DS_CLK_EN_M (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S) -#define PCR_DS_CLK_EN_V 0x00000001 -#define PCR_DS_CLK_EN_S 0 - -/* PCR_HMAC_CONF_REG register - * HMAC configuration register - */ - -#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xe4) - -/* PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset hmac module - */ - -#define PCR_HMAC_RST_EN (BIT(1)) -#define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S) -#define PCR_HMAC_RST_EN_V 0x00000001 -#define PCR_HMAC_RST_EN_S 1 - -/* PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable hmac clock - */ - -#define PCR_HMAC_CLK_EN (BIT(0)) -#define PCR_HMAC_CLK_EN_M (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S) -#define PCR_HMAC_CLK_EN_V 0x00000001 -#define PCR_HMAC_CLK_EN_S 0 - -/* PCR_IOMUX_CONF_REG register - * IOMUX configuration register - */ - -#define PCR_IOMUX_CONF_REG (DR_REG_PCR_BASE + 0xe8) - -/* PCR_IOMUX_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset iomux module - */ - -#define PCR_IOMUX_RST_EN (BIT(1)) -#define PCR_IOMUX_RST_EN_M (PCR_IOMUX_RST_EN_V << PCR_IOMUX_RST_EN_S) -#define PCR_IOMUX_RST_EN_V 0x00000001 -#define PCR_IOMUX_RST_EN_S 1 - -/* PCR_IOMUX_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable iomux apb clock - */ - -#define PCR_IOMUX_CLK_EN (BIT(0)) -#define PCR_IOMUX_CLK_EN_M (PCR_IOMUX_CLK_EN_V << PCR_IOMUX_CLK_EN_S) -#define PCR_IOMUX_CLK_EN_V 0x00000001 -#define PCR_IOMUX_CLK_EN_S 0 - -/* PCR_IOMUX_CLK_CONF_REG register - * IOMUX_CLK configuration register - */ - -#define PCR_IOMUX_CLK_CONF_REG (DR_REG_PCR_BASE + 0xec) - -/* PCR_IOMUX_FUNC_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable iomux function clock - */ - -#define PCR_IOMUX_FUNC_CLK_EN (BIT(22)) -#define PCR_IOMUX_FUNC_CLK_EN_M (PCR_IOMUX_FUNC_CLK_EN_V << PCR_IOMUX_FUNC_CLK_EN_S) -#define PCR_IOMUX_FUNC_CLK_EN_V 0x00000001 -#define PCR_IOMUX_FUNC_CLK_EN_S 22 - -/* PCR_IOMUX_FUNC_CLK_SEL : R/W; bitpos: [21:20]; default: 3; - * set this field to select clock-source. 0: do not select anyone clock, 1: - * 80MHz, 2: FOSC, 3(default): XTAL. - */ - -#define PCR_IOMUX_FUNC_CLK_SEL 0x00000003 -#define PCR_IOMUX_FUNC_CLK_SEL_M (PCR_IOMUX_FUNC_CLK_SEL_V << PCR_IOMUX_FUNC_CLK_SEL_S) -#define PCR_IOMUX_FUNC_CLK_SEL_V 0x00000003 -#define PCR_IOMUX_FUNC_CLK_SEL_S 20 - -/* PCR_MEM_MONITOR_CONF_REG register - * MEM_MONITOR configuration register - */ - -#define PCR_MEM_MONITOR_CONF_REG (DR_REG_PCR_BASE + 0xf0) - -/* PCR_MEM_MONITOR_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset mem_monitor module - */ - -#define PCR_MEM_MONITOR_RST_EN (BIT(1)) -#define PCR_MEM_MONITOR_RST_EN_M (PCR_MEM_MONITOR_RST_EN_V << PCR_MEM_MONITOR_RST_EN_S) -#define PCR_MEM_MONITOR_RST_EN_V 0x00000001 -#define PCR_MEM_MONITOR_RST_EN_S 1 - -/* PCR_MEM_MONITOR_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable mem_monitor clock - */ - -#define PCR_MEM_MONITOR_CLK_EN (BIT(0)) -#define PCR_MEM_MONITOR_CLK_EN_M (PCR_MEM_MONITOR_CLK_EN_V << PCR_MEM_MONITOR_CLK_EN_S) -#define PCR_MEM_MONITOR_CLK_EN_V 0x00000001 -#define PCR_MEM_MONITOR_CLK_EN_S 0 - -/* PCR_REGDMA_CONF_REG register - * REGDMA configuration register - */ - -#define PCR_REGDMA_CONF_REG (DR_REG_PCR_BASE + 0xf4) - -/* PCR_REGDMA_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset regdma module - */ - -#define PCR_REGDMA_RST_EN (BIT(1)) -#define PCR_REGDMA_RST_EN_M (PCR_REGDMA_RST_EN_V << PCR_REGDMA_RST_EN_S) -#define PCR_REGDMA_RST_EN_V 0x00000001 -#define PCR_REGDMA_RST_EN_S 1 - -/* PCR_REGDMA_CLK_EN : R/W; bitpos: [0]; default: 0; - * Set 1 to enable regdma clock - */ - -#define PCR_REGDMA_CLK_EN (BIT(0)) -#define PCR_REGDMA_CLK_EN_M (PCR_REGDMA_CLK_EN_V << PCR_REGDMA_CLK_EN_S) -#define PCR_REGDMA_CLK_EN_V 0x00000001 -#define PCR_REGDMA_CLK_EN_S 0 - -/* PCR_RETENTION_CONF_REG register - * retention configuration register - */ - -#define PCR_RETENTION_CONF_REG (DR_REG_PCR_BASE + 0xf8) - -/* PCR_RETENTION_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset retention module - */ - -#define PCR_RETENTION_RST_EN (BIT(1)) -#define PCR_RETENTION_RST_EN_M (PCR_RETENTION_RST_EN_V << PCR_RETENTION_RST_EN_S) -#define PCR_RETENTION_RST_EN_V 0x00000001 -#define PCR_RETENTION_RST_EN_S 1 - -/* PCR_RETENTION_CLK_EN : R/W; bitpos: [0]; default: 0; - * Set 1 to enable retention clock - */ - -#define PCR_RETENTION_CLK_EN (BIT(0)) -#define PCR_RETENTION_CLK_EN_M (PCR_RETENTION_CLK_EN_V << PCR_RETENTION_CLK_EN_S) -#define PCR_RETENTION_CLK_EN_V 0x00000001 -#define PCR_RETENTION_CLK_EN_S 0 - -/* PCR_TRACE_CONF_REG register - * TRACE configuration register - */ - -#define PCR_TRACE_CONF_REG (DR_REG_PCR_BASE + 0xfc) - -/* PCR_TRACE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset trace module - */ - -#define PCR_TRACE_RST_EN (BIT(1)) -#define PCR_TRACE_RST_EN_M (PCR_TRACE_RST_EN_V << PCR_TRACE_RST_EN_S) -#define PCR_TRACE_RST_EN_V 0x00000001 -#define PCR_TRACE_RST_EN_S 1 - -/* PCR_TRACE_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable trace clock - */ - -#define PCR_TRACE_CLK_EN (BIT(0)) -#define PCR_TRACE_CLK_EN_M (PCR_TRACE_CLK_EN_V << PCR_TRACE_CLK_EN_S) -#define PCR_TRACE_CLK_EN_V 0x00000001 -#define PCR_TRACE_CLK_EN_S 0 - -/* PCR_ASSIST_CONF_REG register - * ASSIST configuration register - */ - -#define PCR_ASSIST_CONF_REG (DR_REG_PCR_BASE + 0x100) - -/* PCR_ASSIST_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset assist module - */ - -#define PCR_ASSIST_RST_EN (BIT(1)) -#define PCR_ASSIST_RST_EN_M (PCR_ASSIST_RST_EN_V << PCR_ASSIST_RST_EN_S) -#define PCR_ASSIST_RST_EN_V 0x00000001 -#define PCR_ASSIST_RST_EN_S 1 - -/* PCR_ASSIST_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable assist clock - */ - -#define PCR_ASSIST_CLK_EN (BIT(0)) -#define PCR_ASSIST_CLK_EN_M (PCR_ASSIST_CLK_EN_V << PCR_ASSIST_CLK_EN_S) -#define PCR_ASSIST_CLK_EN_V 0x00000001 -#define PCR_ASSIST_CLK_EN_S 0 - -/* PCR_CACHE_CONF_REG register - * CACHE configuration register - */ - -#define PCR_CACHE_CONF_REG (DR_REG_PCR_BASE + 0x104) - -/* PCR_CACHE_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cache module - */ - -#define PCR_CACHE_RST_EN (BIT(1)) -#define PCR_CACHE_RST_EN_M (PCR_CACHE_RST_EN_V << PCR_CACHE_RST_EN_S) -#define PCR_CACHE_RST_EN_V 0x00000001 -#define PCR_CACHE_RST_EN_S 1 - -/* PCR_CACHE_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable cache clock - */ - -#define PCR_CACHE_CLK_EN (BIT(0)) -#define PCR_CACHE_CLK_EN_M (PCR_CACHE_CLK_EN_V << PCR_CACHE_CLK_EN_S) -#define PCR_CACHE_CLK_EN_V 0x00000001 -#define PCR_CACHE_CLK_EN_S 0 - -/* PCR_MODEM_APB_CONF_REG register - * MODEM_APB configuration register - */ - -#define PCR_MODEM_APB_CONF_REG (DR_REG_PCR_BASE + 0x108) - -/* PCR_MODEM_RST_EN : R/W; bitpos: [1]; default: 0; - * Set this file as 1 to reset modem-subsystem. - */ - -#define PCR_MODEM_RST_EN (BIT(1)) -#define PCR_MODEM_RST_EN_M (PCR_MODEM_RST_EN_V << PCR_MODEM_RST_EN_S) -#define PCR_MODEM_RST_EN_V 0x00000001 -#define PCR_MODEM_RST_EN_S 1 - -/* PCR_MODEM_APB_CLK_EN : R/W; bitpos: [0]; default: 1; - * This field indicates if modem_apb clock is enable. 0: disable, 1: - * enable(default). - */ - -#define PCR_MODEM_APB_CLK_EN (BIT(0)) -#define PCR_MODEM_APB_CLK_EN_M (PCR_MODEM_APB_CLK_EN_V << PCR_MODEM_APB_CLK_EN_S) -#define PCR_MODEM_APB_CLK_EN_V 0x00000001 -#define PCR_MODEM_APB_CLK_EN_S 0 - -/* PCR_TIMEOUT_CONF_REG register - * TIMEOUT configuration register - */ - -#define PCR_TIMEOUT_CONF_REG (DR_REG_PCR_BASE + 0x10c) - -/* PCR_HP_TIMEOUT_RST_EN : R/W; bitpos: [2]; default: 0; - * Set 0 to reset hp_peri timeout module and hp_modem timeout module - */ - -#define PCR_HP_TIMEOUT_RST_EN (BIT(2)) -#define PCR_HP_TIMEOUT_RST_EN_M (PCR_HP_TIMEOUT_RST_EN_V << PCR_HP_TIMEOUT_RST_EN_S) -#define PCR_HP_TIMEOUT_RST_EN_V 0x00000001 -#define PCR_HP_TIMEOUT_RST_EN_S 2 - -/* PCR_CPU_TIMEOUT_RST_EN : R/W; bitpos: [1]; default: 0; - * Set 0 to reset cpu_peri timeout module - */ - -#define PCR_CPU_TIMEOUT_RST_EN (BIT(1)) -#define PCR_CPU_TIMEOUT_RST_EN_M (PCR_CPU_TIMEOUT_RST_EN_V << PCR_CPU_TIMEOUT_RST_EN_S) -#define PCR_CPU_TIMEOUT_RST_EN_V 0x00000001 -#define PCR_CPU_TIMEOUT_RST_EN_S 1 - -/* PCR_SYSCLK_CONF_REG register - * SYSCLK configuration register - */ - -#define PCR_SYSCLK_CONF_REG (DR_REG_PCR_BASE + 0x110) - -/* PCR_CLK_XTAL_FREQ : RO; bitpos: [30:24]; default: 40; - * This field indicates the frequency(MHz) of XTAL. - */ - -#define PCR_CLK_XTAL_FREQ 0x0000007f -#define PCR_CLK_XTAL_FREQ_M (PCR_CLK_XTAL_FREQ_V << PCR_CLK_XTAL_FREQ_S) -#define PCR_CLK_XTAL_FREQ_V 0x0000007f -#define PCR_CLK_XTAL_FREQ_S 24 - -/* PCR_SOC_CLK_SEL : R/W; bitpos: [17:16]; default: 0; - * This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: - * reserved. - */ - -#define PCR_SOC_CLK_SEL 0x00000003 -#define PCR_SOC_CLK_SEL_M (PCR_SOC_CLK_SEL_V << PCR_SOC_CLK_SEL_S) -#define PCR_SOC_CLK_SEL_V 0x00000003 -#define PCR_SOC_CLK_SEL_S 16 - -/* PCR_HS_DIV_NUM : HRO; bitpos: [15:8]; default: 2; - * clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL. - */ - -#define PCR_HS_DIV_NUM 0x000000ff -#define PCR_HS_DIV_NUM_M (PCR_HS_DIV_NUM_V << PCR_HS_DIV_NUM_S) -#define PCR_HS_DIV_NUM_V 0x000000ff -#define PCR_HS_DIV_NUM_S 8 - -/* PCR_LS_DIV_NUM : HRO; bitpos: [7:0]; default: 0; - * clk_hproot is div1 of low-speed clock-source if clck-source is a - * low-speed clock-source such as XTAL/FOSC. - */ - -#define PCR_LS_DIV_NUM 0x000000ff -#define PCR_LS_DIV_NUM_M (PCR_LS_DIV_NUM_V << PCR_LS_DIV_NUM_S) -#define PCR_LS_DIV_NUM_V 0x000000ff -#define PCR_LS_DIV_NUM_S 0 - -/* PCR_CPU_WAITI_CONF_REG register - * CPU_WAITI configuration register - */ - -#define PCR_CPU_WAITI_CONF_REG (DR_REG_PCR_BASE + 0x114) - -/* PCR_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; - * This field used to set delay cycle when cpu enter waiti mode, after delay - * waiti_clk will close - */ - -#define PCR_CPU_WAITI_DELAY_NUM 0x0000000f -#define PCR_CPU_WAITI_DELAY_NUM_M (PCR_CPU_WAITI_DELAY_NUM_V << PCR_CPU_WAITI_DELAY_NUM_S) -#define PCR_CPU_WAITI_DELAY_NUM_V 0x0000000f -#define PCR_CPU_WAITI_DELAY_NUM_S 4 - -/* PCR_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; - * Set 1 to force cpu_waiti_clk enable. - */ - -#define PCR_CPU_WAIT_MODE_FORCE_ON (BIT(3)) -#define PCR_CPU_WAIT_MODE_FORCE_ON_M (PCR_CPU_WAIT_MODE_FORCE_ON_V << PCR_CPU_WAIT_MODE_FORCE_ON_S) -#define PCR_CPU_WAIT_MODE_FORCE_ON_V 0x00000001 -#define PCR_CPU_WAIT_MODE_FORCE_ON_S 3 - -/* PCR_PLL_FREQ_SEL : HRO; bitpos: [2]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and - * PCR_CPU_LS_DIV_NUM - */ - -#define PCR_PLL_FREQ_SEL (BIT(2)) -#define PCR_PLL_FREQ_SEL_M (PCR_PLL_FREQ_SEL_V << PCR_PLL_FREQ_SEL_S) -#define PCR_PLL_FREQ_SEL_V 0x00000001 -#define PCR_PLL_FREQ_SEL_S 2 - -/* PCR_CPUPERIOD_SEL : HRO; bitpos: [1:0]; default: 1; - * Reserved. This filed has been replaced by PCR_CPU_HS_DIV_NUM and - * PCR_CPU_LS_DIV_NUM - */ - -#define PCR_CPUPERIOD_SEL 0x00000003 -#define PCR_CPUPERIOD_SEL_M (PCR_CPUPERIOD_SEL_V << PCR_CPUPERIOD_SEL_S) -#define PCR_CPUPERIOD_SEL_V 0x00000003 -#define PCR_CPUPERIOD_SEL_S 0 - -/* PCR_CPU_FREQ_CONF_REG register - * CPU_FREQ configuration register - */ - -#define PCR_CPU_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x118) - -/* PCR_CPU_HS_120M_FORCE : R/W; bitpos: [16]; default: 0; - * Given that PCR_CPU_HS_DIV_NUM is 0, set this field as 1 to force clk_cpu - * at 120MHz. Only avaliable when PCR_CPU_HS_DIV_NUM is 0 and clk_cpu is - * driven by SPLL. - */ - -#define PCR_CPU_HS_120M_FORCE (BIT(16)) -#define PCR_CPU_HS_120M_FORCE_M (PCR_CPU_HS_120M_FORCE_V << PCR_CPU_HS_120M_FORCE_S) -#define PCR_CPU_HS_120M_FORCE_V 0x00000001 -#define PCR_CPU_HS_120M_FORCE_S 16 - -/* PCR_CPU_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 0; - * Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The - * clk_cpu is div1(default)/div2/div4 of clk_hproot. This field is only - * avaliable for high-speed clock-source such as SPLL, and should be used - * together with PCR_AHB_HS_DIV_NUM. - */ - -#define PCR_CPU_HS_DIV_NUM 0x000000ff -#define PCR_CPU_HS_DIV_NUM_M (PCR_CPU_HS_DIV_NUM_V << PCR_CPU_HS_DIV_NUM_S) -#define PCR_CPU_HS_DIV_NUM_V 0x000000ff -#define PCR_CPU_HS_DIV_NUM_S 8 - -/* PCR_CPU_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set as one within (0,1,3) to generate clk_cpu drived by clk_hproot. The - * clk_cpu is div1(default)/div2/div4 of clk_hproot. This field is only - * avaliable for low-speed clock-source such as XTAL/FOSC, and should be - * used together with PCR_AHB_LS_DIV_NUM. - */ - -#define PCR_CPU_LS_DIV_NUM 0x000000ff -#define PCR_CPU_LS_DIV_NUM_M (PCR_CPU_LS_DIV_NUM_V << PCR_CPU_LS_DIV_NUM_S) -#define PCR_CPU_LS_DIV_NUM_V 0x000000ff -#define PCR_CPU_LS_DIV_NUM_S 0 - -/* PCR_AHB_FREQ_CONF_REG register - * AHB_FREQ configuration register - */ - -#define PCR_AHB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x11c) - -/* PCR_AHB_HS_DIV_NUM : R/W; bitpos: [15:8]; default: 3; - * Set as one within (3,7,15) to generate clk_ahb drived by clk_hproot. The - * clk_ahb is div4(default)/div8/div16 of clk_hproot. This field is only - * avaliable for high-speed clock-source such as SPLL, and should be used - * together with PCR_CPU_HS_DIV_NUM. - */ - -#define PCR_AHB_HS_DIV_NUM 0x000000ff -#define PCR_AHB_HS_DIV_NUM_M (PCR_AHB_HS_DIV_NUM_V << PCR_AHB_HS_DIV_NUM_S) -#define PCR_AHB_HS_DIV_NUM_V 0x000000ff -#define PCR_AHB_HS_DIV_NUM_S 8 - -/* PCR_AHB_LS_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * Set as one within (0,1,3,7) to generate clk_ahb drived by clk_hproot. The - * clk_ahb is div1(default)/div2/div4/div8 of clk_hproot. This field is only - * avaliable for low-speed clock-source such as XTAL/FOSC, and should be - * used together with PCR_CPU_LS_DIV_NUM. - */ - -#define PCR_AHB_LS_DIV_NUM 0x000000ff -#define PCR_AHB_LS_DIV_NUM_M (PCR_AHB_LS_DIV_NUM_V << PCR_AHB_LS_DIV_NUM_S) -#define PCR_AHB_LS_DIV_NUM_V 0x000000ff -#define PCR_AHB_LS_DIV_NUM_S 0 - -/* PCR_APB_FREQ_CONF_REG register - * APB_FREQ configuration register - */ - -#define PCR_APB_FREQ_CONF_REG (DR_REG_PCR_BASE + 0x120) - -/* PCR_APB_DIV_NUM : R/W; bitpos: [15:8]; default: 0; - * Set as one within (0,1,3) to generate clk_apb drived by clk_ahb. The - * clk_apb is div1(default)/div2/div4 of clk_ahb. - */ - -#define PCR_APB_DIV_NUM 0x000000ff -#define PCR_APB_DIV_NUM_M (PCR_APB_DIV_NUM_V << PCR_APB_DIV_NUM_S) -#define PCR_APB_DIV_NUM_V 0x000000ff -#define PCR_APB_DIV_NUM_S 8 - -/* PCR_APB_DECREASE_DIV_NUM : R/W; bitpos: [7:0]; default: 0; - * If this field's value is grater than PCR_APB_DIV_NUM, the clk_apb will be - * automatically down to clk_apb_decrease only when no access is on apb-bus, - * and will recover to the previous frequency when a new access appears on - * apb-bus. Set as one within (0,1,3) to set clk_apb_decrease as - * div1/div2/div4(default) of clk_ahb. Note that enable this function will - * reduce performance. Users can set this field as zero to disable the - * auto-decrease-apb-freq function. By default, this function is disable. - */ - -#define PCR_APB_DECREASE_DIV_NUM 0x000000ff -#define PCR_APB_DECREASE_DIV_NUM_M (PCR_APB_DECREASE_DIV_NUM_V << PCR_APB_DECREASE_DIV_NUM_S) -#define PCR_APB_DECREASE_DIV_NUM_V 0x000000ff -#define PCR_APB_DECREASE_DIV_NUM_S 0 - -/* PCR_SYSCLK_FREQ_QUERY_0_REG register - * SYSCLK frequency query 0 register - */ - -#define PCR_SYSCLK_FREQ_QUERY_0_REG (DR_REG_PCR_BASE + 0x124) - -/* PCR_PLL_FREQ : HRO; bitpos: [17:8]; default: 480; - * This field indicates the frequency(MHz) of SPLL. - */ - -#define PCR_PLL_FREQ 0x000003ff -#define PCR_PLL_FREQ_M (PCR_PLL_FREQ_V << PCR_PLL_FREQ_S) -#define PCR_PLL_FREQ_V 0x000003ff -#define PCR_PLL_FREQ_S 8 - -/* PCR_FOSC_FREQ : HRO; bitpos: [7:0]; default: 20; - * This field indicates the frequency(MHz) of FOSC. - */ - -#define PCR_FOSC_FREQ 0x000000ff -#define PCR_FOSC_FREQ_M (PCR_FOSC_FREQ_V << PCR_FOSC_FREQ_S) -#define PCR_FOSC_FREQ_V 0x000000ff -#define PCR_FOSC_FREQ_S 0 - -/* PCR_PLL_DIV_CLK_EN_REG register - * SPLL DIV clock-gating configuration register - */ - -#define PCR_PLL_DIV_CLK_EN_REG (DR_REG_PCR_BASE + 0x128) - -/* PCR_PLL_20M_CLK_EN : R/W; bitpos: [6]; default: 1; - * This field is used to open 20 MHz clock (div24 of SPLL) drived from SPLL. - * 0: close, 1: open(default). Only avaliable when high-speed clock-source - * SPLL is active. - */ - -#define PCR_PLL_20M_CLK_EN (BIT(6)) -#define PCR_PLL_20M_CLK_EN_M (PCR_PLL_20M_CLK_EN_V << PCR_PLL_20M_CLK_EN_S) -#define PCR_PLL_20M_CLK_EN_V 0x00000001 -#define PCR_PLL_20M_CLK_EN_S 6 - -/* PCR_PLL_40M_CLK_EN : R/W; bitpos: [5]; default: 1; - * This field is used to open 40 MHz clock (div12 of SPLL) drived from SPLL. - * 0: close, 1: open(default). Only avaliable when high-speed clock-source - * SPLL is active. - */ - -#define PCR_PLL_40M_CLK_EN (BIT(5)) -#define PCR_PLL_40M_CLK_EN_M (PCR_PLL_40M_CLK_EN_V << PCR_PLL_40M_CLK_EN_S) -#define PCR_PLL_40M_CLK_EN_V 0x00000001 -#define PCR_PLL_40M_CLK_EN_S 5 - -/* PCR_PLL_48M_CLK_EN : R/W; bitpos: [4]; default: 1; - * This field is used to open 48 MHz clock (div10 of SPLL) drived from SPLL. - * 0: close, 1: open(default). Only avaliable when high-speed clock-source - * SPLL is active. - */ - -#define PCR_PLL_48M_CLK_EN (BIT(4)) -#define PCR_PLL_48M_CLK_EN_M (PCR_PLL_48M_CLK_EN_V << PCR_PLL_48M_CLK_EN_S) -#define PCR_PLL_48M_CLK_EN_V 0x00000001 -#define PCR_PLL_48M_CLK_EN_S 4 - -/* PCR_PLL_80M_CLK_EN : R/W; bitpos: [3]; default: 1; - * This field is used to open 80 MHz clock (div6 of SPLL) drived from SPLL. - * 0: close, 1: open(default). Only avaliable when high-speed clock-source - * SPLL is active. - */ - -#define PCR_PLL_80M_CLK_EN (BIT(3)) -#define PCR_PLL_80M_CLK_EN_M (PCR_PLL_80M_CLK_EN_V << PCR_PLL_80M_CLK_EN_S) -#define PCR_PLL_80M_CLK_EN_V 0x00000001 -#define PCR_PLL_80M_CLK_EN_S 3 - -/* PCR_PLL_120M_CLK_EN : R/W; bitpos: [2]; default: 1; - * This field is used to open 120 MHz clock (div4 of SPLL) drived from SPLL. - * 0: close, 1: open(default). Only avaliable when high-speed clock-source - * SPLL is active. - */ - -#define PCR_PLL_120M_CLK_EN (BIT(2)) -#define PCR_PLL_120M_CLK_EN_M (PCR_PLL_120M_CLK_EN_V << PCR_PLL_120M_CLK_EN_S) -#define PCR_PLL_120M_CLK_EN_V 0x00000001 -#define PCR_PLL_120M_CLK_EN_S 2 - -/* PCR_PLL_160M_CLK_EN : R/W; bitpos: [1]; default: 1; - * This field is used to open 160 MHz clock (div3 of SPLL) drived from SPLL. - * 0: close, 1: open(default). Only avaliable when high-speed clock-source - * SPLL is active. - */ - -#define PCR_PLL_160M_CLK_EN (BIT(1)) -#define PCR_PLL_160M_CLK_EN_M (PCR_PLL_160M_CLK_EN_V << PCR_PLL_160M_CLK_EN_S) -#define PCR_PLL_160M_CLK_EN_V 0x00000001 -#define PCR_PLL_160M_CLK_EN_S 1 - -/* PCR_PLL_240M_CLK_EN : R/W; bitpos: [0]; default: 1; - * This field is used to open 240 MHz clock (div2 of SPLL) drived from SPLL. - * 0: close, 1: open(default). Only avaliable when high-speed clock-source - * SPLL is active. - */ - -#define PCR_PLL_240M_CLK_EN (BIT(0)) -#define PCR_PLL_240M_CLK_EN_M (PCR_PLL_240M_CLK_EN_V << PCR_PLL_240M_CLK_EN_S) -#define PCR_PLL_240M_CLK_EN_V 0x00000001 -#define PCR_PLL_240M_CLK_EN_S 0 - -/* PCR_CTRL_CLK_OUT_EN_REG register - * CLK_OUT_EN configuration register - */ - -#define PCR_CTRL_CLK_OUT_EN_REG (DR_REG_PCR_BASE + 0x12c) - -/* PCR_CLK_XTAL_OEN : R/W; bitpos: [10]; default: 1; - * Set 1 to enable xtal clock - */ - -#define PCR_CLK_XTAL_OEN (BIT(10)) -#define PCR_CLK_XTAL_OEN_M (PCR_CLK_XTAL_OEN_V << PCR_CLK_XTAL_OEN_S) -#define PCR_CLK_XTAL_OEN_V 0x00000001 -#define PCR_CLK_XTAL_OEN_S 10 - -/* PCR_CLK40X_BB_OEN : R/W; bitpos: [9]; default: 1; - * Set 1 to enable 40x_bb clock - */ - -#define PCR_CLK40X_BB_OEN (BIT(9)) -#define PCR_CLK40X_BB_OEN_M (PCR_CLK40X_BB_OEN_V << PCR_CLK40X_BB_OEN_S) -#define PCR_CLK40X_BB_OEN_V 0x00000001 -#define PCR_CLK40X_BB_OEN_S 9 - -/* PCR_CLK_DAC_CPU_OEN : R/W; bitpos: [8]; default: 1; - * Reserved - */ - -#define PCR_CLK_DAC_CPU_OEN (BIT(8)) -#define PCR_CLK_DAC_CPU_OEN_M (PCR_CLK_DAC_CPU_OEN_V << PCR_CLK_DAC_CPU_OEN_S) -#define PCR_CLK_DAC_CPU_OEN_V 0x00000001 -#define PCR_CLK_DAC_CPU_OEN_S 8 - -/* PCR_CLK_ADC_INF_OEN : R/W; bitpos: [7]; default: 1; - * Reserved - */ - -#define PCR_CLK_ADC_INF_OEN (BIT(7)) -#define PCR_CLK_ADC_INF_OEN_M (PCR_CLK_ADC_INF_OEN_V << PCR_CLK_ADC_INF_OEN_S) -#define PCR_CLK_ADC_INF_OEN_V 0x00000001 -#define PCR_CLK_ADC_INF_OEN_S 7 - -/* PCR_CLK_320M_OEN : R/W; bitpos: [6]; default: 1; - * Set 1 to enable 320m clock - */ - -#define PCR_CLK_320M_OEN (BIT(6)) -#define PCR_CLK_320M_OEN_M (PCR_CLK_320M_OEN_V << PCR_CLK_320M_OEN_S) -#define PCR_CLK_320M_OEN_V 0x00000001 -#define PCR_CLK_320M_OEN_S 6 - -/* PCR_CLK160_OEN : R/W; bitpos: [5]; default: 1; - * Set 1 to enable 160m clock - */ - -#define PCR_CLK160_OEN (BIT(5)) -#define PCR_CLK160_OEN_M (PCR_CLK160_OEN_V << PCR_CLK160_OEN_S) -#define PCR_CLK160_OEN_V 0x00000001 -#define PCR_CLK160_OEN_S 5 - -/* PCR_CLK80_OEN : R/W; bitpos: [4]; default: 1; - * Set 1 to enable 80m clock - */ - -#define PCR_CLK80_OEN (BIT(4)) -#define PCR_CLK80_OEN_M (PCR_CLK80_OEN_V << PCR_CLK80_OEN_S) -#define PCR_CLK80_OEN_V 0x00000001 -#define PCR_CLK80_OEN_S 4 - -/* PCR_CLK_BB_OEN : R/W; bitpos: [3]; default: 1; - * Set 1 to enable bb clock - */ - -#define PCR_CLK_BB_OEN (BIT(3)) -#define PCR_CLK_BB_OEN_M (PCR_CLK_BB_OEN_V << PCR_CLK_BB_OEN_S) -#define PCR_CLK_BB_OEN_V 0x00000001 -#define PCR_CLK_BB_OEN_S 3 - -/* PCR_CLK44_OEN : R/W; bitpos: [2]; default: 1; - * Set 1 to enable 44m clock - */ - -#define PCR_CLK44_OEN (BIT(2)) -#define PCR_CLK44_OEN_M (PCR_CLK44_OEN_V << PCR_CLK44_OEN_S) -#define PCR_CLK44_OEN_V 0x00000001 -#define PCR_CLK44_OEN_S 2 - -/* PCR_CLK22_OEN : R/W; bitpos: [1]; default: 1; - * Set 1 to enable 22m clock - */ - -#define PCR_CLK22_OEN (BIT(1)) -#define PCR_CLK22_OEN_M (PCR_CLK22_OEN_V << PCR_CLK22_OEN_S) -#define PCR_CLK22_OEN_V 0x00000001 -#define PCR_CLK22_OEN_S 1 - -/* PCR_CLK20_OEN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable 20m clock - */ - -#define PCR_CLK20_OEN (BIT(0)) -#define PCR_CLK20_OEN_M (PCR_CLK20_OEN_V << PCR_CLK20_OEN_S) -#define PCR_CLK20_OEN_V 0x00000001 -#define PCR_CLK20_OEN_S 0 - -/* PCR_CTRL_TICK_CONF_REG register - * TICK configuration register - */ - -#define PCR_CTRL_TICK_CONF_REG (DR_REG_PCR_BASE + 0x130) - -/* PCR_RST_TICK_CNT : R/W; bitpos: [17]; default: 0; - * ******* Description *********** - */ - -#define PCR_RST_TICK_CNT (BIT(17)) -#define PCR_RST_TICK_CNT_M (PCR_RST_TICK_CNT_V << PCR_RST_TICK_CNT_S) -#define PCR_RST_TICK_CNT_V 0x00000001 -#define PCR_RST_TICK_CNT_S 17 - -/* PCR_TICK_ENABLE : R/W; bitpos: [16]; default: 1; - * ******* Description *********** - */ - -#define PCR_TICK_ENABLE (BIT(16)) -#define PCR_TICK_ENABLE_M (PCR_TICK_ENABLE_V << PCR_TICK_ENABLE_S) -#define PCR_TICK_ENABLE_V 0x00000001 -#define PCR_TICK_ENABLE_S 16 - -/* PCR_FOSC_TICK_NUM : R/W; bitpos: [15:8]; default: 7; - * ******* Description *********** - */ - -#define PCR_FOSC_TICK_NUM 0x000000ff -#define PCR_FOSC_TICK_NUM_M (PCR_FOSC_TICK_NUM_V << PCR_FOSC_TICK_NUM_S) -#define PCR_FOSC_TICK_NUM_V 0x000000ff -#define PCR_FOSC_TICK_NUM_S 8 - -/* PCR_XTAL_TICK_NUM : R/W; bitpos: [7:0]; default: 39; - * ******* Description *********** - */ - -#define PCR_XTAL_TICK_NUM 0x000000ff -#define PCR_XTAL_TICK_NUM_M (PCR_XTAL_TICK_NUM_V << PCR_XTAL_TICK_NUM_S) -#define PCR_XTAL_TICK_NUM_V 0x000000ff -#define PCR_XTAL_TICK_NUM_S 0 - -/* PCR_CTRL_32K_CONF_REG register - * 32KHz clock configuration register - */ - -#define PCR_CTRL_32K_CONF_REG (DR_REG_PCR_BASE + 0x134) - -/* PCR_32K_SEL : R/W; bitpos: [1:0]; default: 0; - * This field indicates which one 32KHz clock will be used by MODEM_SYSTEM - * and timergroup. 0: OSC32K(default), 1: XTAL32K, 2/3: 32KHz from pad GPIO0. - */ - -#define PCR_32K_SEL 0x00000003 -#define PCR_32K_SEL_M (PCR_32K_SEL_V << PCR_32K_SEL_S) -#define PCR_32K_SEL_V 0x00000003 -#define PCR_32K_SEL_S 0 - -/* PCR_SRAM_POWER_CONF_REG register - * HP SRAM/ROM configuration register - */ - -#define PCR_SRAM_POWER_CONF_REG (DR_REG_PCR_BASE + 0x138) - -/* PCR_ROM_CLKGATE_FORCE_ON : R/W; bitpos: [20:18]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the - * ROM. 0: A gate-clock will be used when accessing the ROM. - */ - -#define PCR_ROM_CLKGATE_FORCE_ON 0x00000007 -#define PCR_ROM_CLKGATE_FORCE_ON_M (PCR_ROM_CLKGATE_FORCE_ON_V << PCR_ROM_CLKGATE_FORCE_ON_S) -#define PCR_ROM_CLKGATE_FORCE_ON_V 0x00000007 -#define PCR_ROM_CLKGATE_FORCE_ON_S 18 - -/* PCR_ROM_FORCE_PD : R/W; bitpos: [17:15]; default: 0; - * Set this bit to force power down ROM. - */ - -#define PCR_ROM_FORCE_PD 0x00000007 -#define PCR_ROM_FORCE_PD_M (PCR_ROM_FORCE_PD_V << PCR_ROM_FORCE_PD_S) -#define PCR_ROM_FORCE_PD_V 0x00000007 -#define PCR_ROM_FORCE_PD_S 15 - -/* PCR_ROM_FORCE_PU : R/W; bitpos: [14:12]; default: 7; - * Set this bit to force power up ROM - */ - -#define PCR_ROM_FORCE_PU 0x00000007 -#define PCR_ROM_FORCE_PU_M (PCR_ROM_FORCE_PU_V << PCR_ROM_FORCE_PU_S) -#define PCR_ROM_FORCE_PU_V 0x00000007 -#define PCR_ROM_FORCE_PU_S 12 - -/* PCR_SRAM_CLKGATE_FORCE_ON : R/W; bitpos: [11:8]; default: 0; - * 1: Force to open the clock and bypass the gate-clock when accessing the - * SRAM. 0: A gate-clock will be used when accessing the SRAM. - */ - -#define PCR_SRAM_CLKGATE_FORCE_ON 0x0000000f -#define PCR_SRAM_CLKGATE_FORCE_ON_M (PCR_SRAM_CLKGATE_FORCE_ON_V << PCR_SRAM_CLKGATE_FORCE_ON_S) -#define PCR_SRAM_CLKGATE_FORCE_ON_V 0x0000000f -#define PCR_SRAM_CLKGATE_FORCE_ON_S 8 - -/* PCR_SRAM_FORCE_PD : R/W; bitpos: [7:4]; default: 0; - * Set this bit to force power down SRAM. - */ - -#define PCR_SRAM_FORCE_PD 0x0000000f -#define PCR_SRAM_FORCE_PD_M (PCR_SRAM_FORCE_PD_V << PCR_SRAM_FORCE_PD_S) -#define PCR_SRAM_FORCE_PD_V 0x0000000f -#define PCR_SRAM_FORCE_PD_S 4 - -/* PCR_SRAM_FORCE_PU : R/W; bitpos: [3:0]; default: 15; - * Set this bit to force power up SRAM - */ - -#define PCR_SRAM_FORCE_PU 0x0000000f -#define PCR_SRAM_FORCE_PU_M (PCR_SRAM_FORCE_PU_V << PCR_SRAM_FORCE_PU_S) -#define PCR_SRAM_FORCE_PU_V 0x0000000f -#define PCR_SRAM_FORCE_PU_S 0 - -/* PCR_RESET_EVENT_BYPASS_REG register - * reset event bypass backdoor configuration register - */ - -#define PCR_RESET_EVENT_BYPASS_REG (DR_REG_PCR_BASE + 0xff0) - -/* PCR_RESET_EVENT_BYPASS : R/W; bitpos: [1]; default: 1; - * This field is used to control reset event relationship for system-bus. 1: - * system bus (including arbiter/router) will only be reset by power-reset. - * some reset event will be bypass. 0: system bus (including arbiter/router) - * will not only be reset by power-reset, but also some reset event. - */ - -#define PCR_RESET_EVENT_BYPASS (BIT(1)) -#define PCR_RESET_EVENT_BYPASS_M (PCR_RESET_EVENT_BYPASS_V << PCR_RESET_EVENT_BYPASS_S) -#define PCR_RESET_EVENT_BYPASS_V 0x00000001 -#define PCR_RESET_EVENT_BYPASS_S 1 - -/* PCR_RESET_EVENT_BYPASS_APM : R/W; bitpos: [0]; default: 0; - * This field is used to control reset event relationship for - * tee_reg/apm_reg/hp_system_reg. 1: tee_reg/apm_reg/hp_system_reg will only - * be reset by power-reset. some reset event will be bypass. 0: - * tee_reg/apm_reg/hp_system_reg will not only be reset by power-reset, but - * also some reset event. - */ - -#define PCR_RESET_EVENT_BYPASS_APM (BIT(0)) -#define PCR_RESET_EVENT_BYPASS_APM_M (PCR_RESET_EVENT_BYPASS_APM_V << PCR_RESET_EVENT_BYPASS_APM_S) -#define PCR_RESET_EVENT_BYPASS_APM_V 0x00000001 -#define PCR_RESET_EVENT_BYPASS_APM_S 0 - -/* PCR_FPGA_DEBUG_REG register - * fpga debug register - */ - -#define PCR_FPGA_DEBUG_REG (DR_REG_PCR_BASE + 0xff4) - -/* PCR_FPGA_DEBUG : R/W; bitpos: [31:0]; default: 4294967295; - * Only used in fpga debug. - */ - -#define PCR_FPGA_DEBUG 0xffffffff -#define PCR_FPGA_DEBUG_M (PCR_FPGA_DEBUG_V << PCR_FPGA_DEBUG_S) -#define PCR_FPGA_DEBUG_V 0xffffffff -#define PCR_FPGA_DEBUG_S 0 - -/* PCR_CLOCK_GATE_REG register - * PCR clock gating configure register - */ - -#define PCR_CLOCK_GATE_REG (DR_REG_PCR_BASE + 0xff8) - -/* PCR_CLK_EN : R/W; bitpos: [0]; default: 0; - * Set this bit as 1 to force on clock gating. - */ - -#define PCR_CLK_EN (BIT(0)) -#define PCR_CLK_EN_M (PCR_CLK_EN_V << PCR_CLK_EN_S) -#define PCR_CLK_EN_V 0x00000001 -#define PCR_CLK_EN_S 0 - -/* PCR_DATE_REG register - * Date register. - */ - -#define PCR_DATE_REG (DR_REG_PCR_BASE + 0xffc) - -/* PCR_DATE : R/W; bitpos: [27:0]; default: 35676496; - * PCR version information. - */ - -#define PCR_DATE 0x0fffffff -#define PCR_DATE_M (PCR_DATE_V << PCR_DATE_S) -#define PCR_DATE_V 0x0fffffff -#define PCR_DATE_S 0 - -#endif /* __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_PCR_H */ diff --git a/arch/risc-v/src/esp32c6/hardware/esp32c6_rom_layout.h b/arch/risc-v/src/esp32c6/hardware/esp32c6_rom_layout.h deleted file mode 100644 index 36ef8c3e0e17b..0000000000000 --- a/arch/risc-v/src/esp32c6/hardware/esp32c6_rom_layout.h +++ /dev/null @@ -1,102 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/hardware/esp32c6_rom_layout.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_ROM_LAYOUT_H -#define __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_ROM_LAYOUT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Structure and functions for returning ROM global layout - * - * This is for address symbols defined in the linker script, - * which may change during ECOs. - */ - -struct esp32c6_rom_layout_s -{ - uintptr_t dram0_stack_shared_mem_start; - uintptr_t dram0_rtos_reserved_start; - uintptr_t stack_sentry; - uintptr_t stack; - - /* BTDM data */ - - uintptr_t data_start_btdm; - uintptr_t data_end_btdm; - uintptr_t bss_start_btdm; - uintptr_t bss_end_btdm; - uintptr_t data_start_btdm_rom; - uintptr_t data_start_interface_btdm; - uintptr_t data_end_interface_btdm; - uintptr_t bss_start_interface_btdm; - uintptr_t bss_end_interface_btdm; - - /* BTBB data */ - - uintptr_t dram_start_btbbrom; - uintptr_t dram_end_btbbrom; - - /* PHY data */ - - uintptr_t dram_start_phyrom; - uintptr_t dram_end_phyrom; - - /* Wi-Fi data */ - - uintptr_t dram_start_net80211; - uintptr_t dram_end_net80211; - uintptr_t data_start_interface_net80211; - uintptr_t data_end_interface_net80211; - uintptr_t bss_start_interface_net80211; - uintptr_t bss_end_interface_net80211; - uintptr_t dram_start_pp; - uintptr_t dram_end_pp; - uintptr_t data_start_interface_pp; - uintptr_t data_end_interface_pp; - uintptr_t bss_start_interface_pp; - uintptr_t bss_end_interface_pp; - - /* Coexist data */ - - uintptr_t dram_start_coexist; - uintptr_t dram_end_coexist; - uintptr_t data_start_interface_coexist; - uintptr_t data_end_interface_coexist; - uintptr_t bss_start_interface_coexist; - uintptr_t bss_end_interface_coexist; - - /* USB device data */ - - uintptr_t dram_start_usbdev_rom; - uintptr_t dram_end_usbdev_rom; - uintptr_t dram_start_uart_rom; - uintptr_t dram_end_uart_rom; -}; - -#endif /* __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_ROM_LAYOUT_H */ - diff --git a/arch/risc-v/src/esp32c6/hardware/esp32c6_soc.h b/arch/risc-v/src/esp32c6/hardware/esp32c6_soc.h deleted file mode 100644 index 6b0bd3d76dd0f..0000000000000 --- a/arch/risc-v/src/esp32c6/hardware/esp32c6_soc.h +++ /dev/null @@ -1,161 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/hardware/esp32c6_soc.h - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_SOC_H -#define __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_SOC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define DR_REG_PLIC_MX_BASE 0x20001000 -#define DR_REG_PLIC_UX_BASE 0x20001400 -#define DR_REG_CLINT_M_BASE 0x20001800 -#define DR_REG_CLINT_U_BASE 0x20001C00 - -#define DR_REG_UART_BASE 0x60000000 -#define DR_REG_UART1_BASE 0x60001000 -#define DR_REG_SPI0_BASE 0x60002000 -#define DR_REG_SPI1_BASE 0x60003000 -#define DR_REG_I2C_EXT_BASE 0x60004000 -#define DR_REG_UHCI0_BASE 0x60005000 -#define DR_REG_RMT_BASE 0x60006000 -#define DR_REG_LEDC_BASE 0x60007000 -#define DR_REG_TIMERGROUP0_BASE 0x60008000 -#define DR_REG_TIMERGROUP1_BASE 0x60009000 -#define DR_REG_SYSTIMER_BASE 0x6000A000 -#define DR_REG_TWAI0_BASE 0x6000B000 -#define DR_REG_I2S_BASE 0x6000C000 -#define DR_REG_TWAI1_BASE 0x6000D000 -#define DR_REG_APB_SARADC_BASE 0x6000E000 -#define DR_REG_USB_SERIAL_JTAG_BASE 0x6000F000 -#define DR_REG_INTERRUPT_MATRIX_BASE 0x60010000 -#define DR_REG_ATOMIC_BASE 0x60011000 -#define DR_REG_PCNT_BASE 0x60012000 -#define DR_REG_SOC_ETM_BASE 0x60013000 -#define DR_REG_MCPWM_BASE 0x60014000 -#define DR_REG_PARL_IO_BASE 0x60015000 -#define DR_REG_HINF_BASE 0x60016000 -#define DR_REG_SLC_BASE 0x60017000 -#define DR_REG_SLCHOST_BASE 0x60018000 -#define DR_REG_PVT_MONITOR_BASE 0x60019000 -#define DR_REG_GDMA_BASE 0x60080000 -#define DR_REG_SPI2_BASE 0x60081000 -#define DR_REG_AES_BASE 0x60088000 -#define DR_REG_SHA_BASE 0x60089000 -#define DR_REG_RSA_BASE 0x6008A000 -#define DR_REG_ECC_MULT_BASE 0x6008B000 -#define DR_REG_DS_BASE 0x6008C000 -#define DR_REG_HMAC_BASE 0x6008D000 -#define DR_REG_IO_MUX_BASE 0x60090000 -#define DR_REG_GPIO_BASE 0x60091000 -#define DR_REG_GPIO_EXT_BASE 0x60091f00 //ESP32C6-TODO -#define DR_REG_MEM_MONITOR_BASE 0x60092000 -#define DR_REG_PAU_BASE 0x60093000 -#define DR_REG_HP_SYSTEM_BASE 0x60095000 -#define DR_REG_PCR_BASE 0x60096000 -#define DR_REG_TEE_BASE 0x60098000 -#define DR_REG_HP_APM_BASE 0x60099000 -#define DR_REG_LP_APM0_BASE 0x60099800 -#define DR_REG_MISC_BASE 0x6009F000 - -#define DR_REG_PMU_BASE 0x600B0000 -#define DR_REG_LP_CLKRST_BASE 0x600B0400 -#define DR_REG_EFUSE_BASE 0x600B0800 -#define DR_REG_LP_TIMER_BASE 0x600B0C00 -#define DR_REG_LP_AON_BASE 0x600B1000 -#define DR_REG_LP_UART_BASE 0x600B1400 -#define DR_REG_LP_I2C_BASE 0x600B1800 -#define DR_REG_LP_WDT_BASE 0x600B1C00 -#define DR_REG_LP_IO_BASE 0x600B2000 -#define DR_REG_LP_I2C_ANA_MST_BASE 0x600B2400 -#define DR_REG_LPPERI_BASE 0x600B2800 -#define DR_REG_LP_ANALOG_PERI_BASE 0x600B2C00 -#define DR_REG_LP_TEE_BASE 0x600B3400 -#define DR_REG_LP_APM_BASE 0x600B3800 -#define DR_REG_OPT_DEBUG_BASE 0x600B3C00 - -#define DR_REG_TRACE_BASE 0x600C0000 -#define DR_REG_ASSIST_DEBUG_BASE 0x600C2000 -#define DR_REG_CPU_BUS_MONITOR_BASE 0x600C2000 -#define DR_REG_INTPRI_BASE 0x600C5000 -#define DR_REG_EXTMEM_BASE 0x600C8000 - -/* Registers Operation */ - -#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) -#define REG_UART_BASE(i) (DR_REG_UART_BASE + (i) * 0x1000) -#define REG_UART_AHB_BASE(i) (DR_REG_UART_BASE + (i) * 0x10000) -#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) -#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) -#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) -#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE) -#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) -#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) -#define REG_TWAI_BASE(i) (DR_REG_TWAI_BASE + (i) * 0x2000) - -/* Peripheral Clock */ - -#define APB_CLK_FREQ_ROM (40 * 1000000) -#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM -#define UART_CLK_FREQ_ROM (40 * 1000000) -#define EFUSE_CLK_FREQ_ROM (20 * 1000000) -#define CPU_CLK_FREQ APB_CLK_FREQ -#define APB_CLK_FREQ (80 * 1000000) -#define REF_CLK_FREQ (1000000) -#define RTC_CLK_FREQ (20 * 1000000) -#define XTAL_CLK_FREQ (40 * 1000000) -#define UART_CLK_FREQ APB_CLK_FREQ -#define WDT_CLK_FREQ APB_CLK_FREQ -#define TIMER_CLK_FREQ (80000000 >> 4) /* 80MHz divided by 16 */ -#define SPI_CLK_DIV 4 -#define TICKS_PER_US_ROM 40 /* CPU is 80MHz */ -#define GPIO_MATRIX_DELAY_NS 0 - -#define PLIC_MXINT_ENABLE_REG (DR_REG_PLIC_MX_BASE + 0x0) -#define PLIC_MXINT_TYPE_REG (DR_REG_PLIC_MX_BASE + 0x4) -#define PLIC_MXINT_CLEAR_REG (DR_REG_PLIC_MX_BASE + 0x8) -#define PLIC_MXINT_THRESH_REG (DR_REG_PLIC_MX_BASE + 0x90) -#define PLIC_MXINT0_PRI_REG (DR_REG_PLIC_MX_BASE + 0x10) - -#define INTC_INT_PRIO_REG(n) (PLIC_MXINT0_PRI_REG + (n)*4) - -/* Mapping Peripheral IDs to map register addresses. */ - -#define CORE_MAP_REGADDR(n) (DR_REG_INTERRUPT_MATRIX_BASE + ((n) << 2)) - -#define BIT(nr) (1UL << (nr)) - -/* Extract the field from the register and shift it to avoid wrong reading */ - -#define REG_MASK(_reg, _field) (((_reg) & (_field##_M)) >> (_field##_S)) - -/* Helper to place a value in a field */ - -#define VALUE_TO_FIELD(_value, _field) (((_value) << (_field##_S)) & (_field##_M)) - -#define MHZ (1000000) - -#endif /* __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_SOC_H */ diff --git a/arch/risc-v/src/esp32c6/hardware/esp32c6_systimer.h b/arch/risc-v/src/esp32c6/hardware/esp32c6_systimer.h deleted file mode 100644 index 60363d0e253f4..0000000000000 --- a/arch/risc-v/src/esp32c6/hardware/esp32c6_systimer.h +++ /dev/null @@ -1,817 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/hardware/esp32c6_systimer.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_SYSTIMER_H -#define __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_SYSTIMER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32c6_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* SYSTIMER_CONF_REG register - * Configure system timer clock - */ - -#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0) - -/* SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0; - * register file clk gating - */ - -#define SYSTIMER_CLK_EN (BIT(31)) -#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S) -#define SYSTIMER_CLK_EN_V 0x00000001 -#define SYSTIMER_CLK_EN_S 31 - -/* SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1; - * timer unit0 work enable - */ - -#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30)) -#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S) -#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001 -#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30 - -/* SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0; - * timer unit1 work enable - */ - -#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29)) -#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S) -#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001 -#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29 - -/* SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0; - * If timer unit0 is stalled when core0 stalled - */ - -#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) -#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S) -#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001 -#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 - -/* SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0; - * If timer unit0 is stalled when core1 stalled - */ - -#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) -#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S) -#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001 -#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 - -/* SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1; - * If timer unit1 is stalled when core0 stalled - */ - -#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) -#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S) -#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001 -#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 - -/* SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1; - * If timer unit1 is stalled when core1 stalled - */ - -#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) -#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S) -#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001 -#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 - -/* SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0; - * target0 work enable - */ - -#define SYSTIMER_TARGET0_WORK_EN (BIT(24)) -#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S) -#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001 -#define SYSTIMER_TARGET0_WORK_EN_S 24 - -/* SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0; - * target1 work enable - */ - -#define SYSTIMER_TARGET1_WORK_EN (BIT(23)) -#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S) -#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001 -#define SYSTIMER_TARGET1_WORK_EN_S 23 - -/* SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0; - * target2 work enable - */ - -#define SYSTIMER_TARGET2_WORK_EN (BIT(22)) -#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S) -#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001 -#define SYSTIMER_TARGET2_WORK_EN_S 22 - -/* SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0; - * enable systimer's etm task and event - */ - -#define SYSTIMER_ETM_EN (BIT(1)) -#define SYSTIMER_ETM_EN_M (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S) -#define SYSTIMER_ETM_EN_V 0x00000001 -#define SYSTIMER_ETM_EN_S 1 - -/* SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0; - * systimer clock force on - */ - -#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0)) -#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S) -#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001 -#define SYSTIMER_SYSTIMER_CLK_FO_S 0 - -/* SYSTIMER_UNIT0_OP_REG register - * system timer unit0 value update register - */ - -#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4) - -/* SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0; - * update timer_unit0 - */ - -#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30)) -#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S) -#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001 -#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30 - -/* SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; - * timer value is sync and valid - */ - -#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) -#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S) -#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001 -#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29 - -/* SYSTIMER_UNIT1_OP_REG register - * system timer unit1 value update register - */ - -#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8) - -/* SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0; - * update timer unit1 - */ - -#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30)) -#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S) -#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001 -#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30 - -/* SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0; - * timer value is sync and valid - */ - -#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) -#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S) -#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001 -#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29 - -/* SYSTIMER_UNIT0_LOAD_HI_REG register - * system timer unit0 value high load register - */ - -#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc) - -/* SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0; - * timer unit0 load high 20 bits - */ - -#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000fffff -#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S) -#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000fffff -#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0 - -/* SYSTIMER_UNIT0_LOAD_LO_REG register - * system timer unit0 value low load register - */ - -#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10) - -/* SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0; - * timer unit0 load low 32 bits - */ - -#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xffffffff -#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S) -#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xffffffff -#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0 - -/* SYSTIMER_UNIT1_LOAD_HI_REG register - * system timer unit1 value high load register - */ - -#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14) - -/* SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0; - * timer unit1 load high 20 bits - */ - -#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000fffff -#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S) -#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000fffff -#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0 - -/* SYSTIMER_UNIT1_LOAD_LO_REG register - * system timer unit1 value low load register - */ - -#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18) - -/* SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0; - * timer unit1 load low 32 bits - */ - -#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xffffffff -#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S) -#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xffffffff -#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0 - -/* SYSTIMER_TARGET0_HI_REG register - * system timer comp0 value high register - */ - -#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c) - -/* SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0; - * timer taget0 high 20 bits - */ - -#define SYSTIMER_TIMER_TARGET0_HI 0x000fffff -#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S) -#define SYSTIMER_TIMER_TARGET0_HI_V 0x000fffff -#define SYSTIMER_TIMER_TARGET0_HI_S 0 - -/* SYSTIMER_TARGET0_LO_REG register - * system timer comp0 value low register - */ - -#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20) - -/* SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0; - * timer taget0 low 32 bits - */ - -#define SYSTIMER_TIMER_TARGET0_LO 0xffffffff -#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S) -#define SYSTIMER_TIMER_TARGET0_LO_V 0xffffffff -#define SYSTIMER_TIMER_TARGET0_LO_S 0 - -/* SYSTIMER_TARGET1_HI_REG register - * system timer comp1 value high register - */ - -#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24) - -/* SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0; - * timer taget1 high 20 bits - */ - -#define SYSTIMER_TIMER_TARGET1_HI 0x000fffff -#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S) -#define SYSTIMER_TIMER_TARGET1_HI_V 0x000fffff -#define SYSTIMER_TIMER_TARGET1_HI_S 0 - -/* SYSTIMER_TARGET1_LO_REG register - * system timer comp1 value low register - */ - -#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28) - -/* SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0; - * timer taget1 low 32 bits - */ - -#define SYSTIMER_TIMER_TARGET1_LO 0xffffffff -#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S) -#define SYSTIMER_TIMER_TARGET1_LO_V 0xffffffff -#define SYSTIMER_TIMER_TARGET1_LO_S 0 - -/* SYSTIMER_TARGET2_HI_REG register - * system timer comp2 value high register - */ - -#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c) - -/* SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0; - * timer taget2 high 20 bits - */ - -#define SYSTIMER_TIMER_TARGET2_HI 0x000fffff -#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S) -#define SYSTIMER_TIMER_TARGET2_HI_V 0x000fffff -#define SYSTIMER_TIMER_TARGET2_HI_S 0 - -/* SYSTIMER_TARGET2_LO_REG register - * system timer comp2 value low register - */ - -#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30) - -/* SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0; - * timer taget2 low 32 bits - */ - -#define SYSTIMER_TIMER_TARGET2_LO 0xffffffff -#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S) -#define SYSTIMER_TIMER_TARGET2_LO_V 0xffffffff -#define SYSTIMER_TIMER_TARGET2_LO_S 0 - -/* SYSTIMER_TARGET0_CONF_REG register - * system timer comp0 target mode register - */ - -#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34) - -/* SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; - * select which unit to compare - */ - -#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) -#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S) -#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001 -#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31 - -/* SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0; - * Set target0 to period mode - */ - -#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30)) -#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S) -#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001 -#define SYSTIMER_TARGET0_PERIOD_MODE_S 30 - -/* SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0; - * target0 period - */ - -#define SYSTIMER_TARGET0_PERIOD 0x03ffffff -#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S) -#define SYSTIMER_TARGET0_PERIOD_V 0x03ffffff -#define SYSTIMER_TARGET0_PERIOD_S 0 - -/* SYSTIMER_TARGET1_CONF_REG register - * system timer comp1 target mode register - */ - -#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38) - -/* SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; - * select which unit to compare - */ - -#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) -#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S) -#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001 -#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31 - -/* SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0; - * Set target1 to period mode - */ - -#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30)) -#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S) -#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001 -#define SYSTIMER_TARGET1_PERIOD_MODE_S 30 - -/* SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0; - * target1 period - */ - -#define SYSTIMER_TARGET1_PERIOD 0x03ffffff -#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S) -#define SYSTIMER_TARGET1_PERIOD_V 0x03ffffff -#define SYSTIMER_TARGET1_PERIOD_S 0 - -/* SYSTIMER_TARGET2_CONF_REG register - * system timer comp2 target mode register - */ - -#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c) - -/* SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0; - * select which unit to compare - */ - -#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) -#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S) -#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001 -#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31 - -/* SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0; - * Set target2 to period mode - */ - -#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30)) -#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S) -#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001 -#define SYSTIMER_TARGET2_PERIOD_MODE_S 30 - -/* SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0; - * target2 period - */ - -#define SYSTIMER_TARGET2_PERIOD 0x03ffffff -#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S) -#define SYSTIMER_TARGET2_PERIOD_V 0x03ffffff -#define SYSTIMER_TARGET2_PERIOD_S 0 - -/* SYSTIMER_UNIT0_VALUE_HI_REG register - * system timer unit0 value high register - */ - -#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40) - -/* SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0; - * timer read value high 20bits - */ - -#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000fffff -#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S) -#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000fffff -#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0 - -/* SYSTIMER_UNIT0_VALUE_LO_REG register - * system timer unit0 value low register - */ - -#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44) - -/* SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0; - * timer read value low 32bits - */ - -#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xffffffff -#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S) -#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xffffffff -#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0 - -/* SYSTIMER_UNIT1_VALUE_HI_REG register - * system timer unit1 value high register - */ - -#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48) - -/* SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0; - * timer read value high 20bits - */ - -#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000fffff -#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S) -#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000fffff -#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0 - -/* SYSTIMER_UNIT1_VALUE_LO_REG register - * system timer unit1 value low register - */ - -#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c) - -/* SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0; - * timer read value low 32bits - */ - -#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xffffffff -#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S) -#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xffffffff -#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0 - -/* SYSTIMER_COMP0_LOAD_REG register - * system timer comp0 conf sync register - */ - -#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50) - -/* SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0; - * timer comp0 sync enable signal - */ - -#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0)) -#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S) -#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001 -#define SYSTIMER_TIMER_COMP0_LOAD_S 0 - -/* SYSTIMER_COMP1_LOAD_REG register - * system timer comp1 conf sync register - */ - -#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54) - -/* SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0; - * timer comp1 sync enable signal - */ - -#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0)) -#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S) -#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001 -#define SYSTIMER_TIMER_COMP1_LOAD_S 0 - -/* SYSTIMER_COMP2_LOAD_REG register - * system timer comp2 conf sync register - */ - -#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58) - -/* SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0; - * timer comp2 sync enable signal - */ - -#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0)) -#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S) -#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001 -#define SYSTIMER_TIMER_COMP2_LOAD_S 0 - -/* SYSTIMER_UNIT0_LOAD_REG register - * system timer unit0 conf sync register - */ - -#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c) - -/* SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0; - * timer unit0 sync enable signal - */ - -#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0)) -#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S) -#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001 -#define SYSTIMER_TIMER_UNIT0_LOAD_S 0 - -/* SYSTIMER_UNIT1_LOAD_REG register - * system timer unit1 conf sync register - */ - -#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60) - -/* SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0; - * timer unit1 sync enable signal - */ - -#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0)) -#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S) -#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001 -#define SYSTIMER_TIMER_UNIT1_LOAD_S 0 - -/* SYSTIMER_INT_ENA_REG register - * systimer interrupt enable register - */ - -#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64) - -/* SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0; - * interupt2 enable - */ - -#define SYSTIMER_TARGET2_INT_ENA (BIT(2)) -#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S) -#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001 -#define SYSTIMER_TARGET2_INT_ENA_S 2 - -/* SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0; - * interupt1 enable - */ - -#define SYSTIMER_TARGET1_INT_ENA (BIT(1)) -#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S) -#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001 -#define SYSTIMER_TARGET1_INT_ENA_S 1 - -/* SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0; - * interupt0 enable - */ - -#define SYSTIMER_TARGET0_INT_ENA (BIT(0)) -#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S) -#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001 -#define SYSTIMER_TARGET0_INT_ENA_S 0 - -/* SYSTIMER_INT_RAW_REG register - * systimer interrupt raw register - */ - -#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68) - -/* SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * interupt2 raw - */ - -#define SYSTIMER_TARGET2_INT_RAW (BIT(2)) -#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S) -#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001 -#define SYSTIMER_TARGET2_INT_RAW_S 2 - -/* SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; - * interupt1 raw - */ - -#define SYSTIMER_TARGET1_INT_RAW (BIT(1)) -#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S) -#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001 -#define SYSTIMER_TARGET1_INT_RAW_S 1 - -/* SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * interupt0 raw - */ - -#define SYSTIMER_TARGET0_INT_RAW (BIT(0)) -#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S) -#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001 -#define SYSTIMER_TARGET0_INT_RAW_S 0 - -/* SYSTIMER_INT_CLR_REG register - * systimer interrupt clear register - */ - -#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c) - -/* SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0; - * interupt2 clear - */ - -#define SYSTIMER_TARGET2_INT_CLR (BIT(2)) -#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S) -#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001 -#define SYSTIMER_TARGET2_INT_CLR_S 2 - -/* SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0; - * interupt1 clear - */ - -#define SYSTIMER_TARGET1_INT_CLR (BIT(1)) -#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S) -#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001 -#define SYSTIMER_TARGET1_INT_CLR_S 1 - -/* SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0; - * interupt0 clear - */ - -#define SYSTIMER_TARGET0_INT_CLR (BIT(0)) -#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S) -#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001 -#define SYSTIMER_TARGET0_INT_CLR_S 0 - -/* SYSTIMER_INT_ST_REG register - * systimer interrupt status register - */ - -#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70) - -/* SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0; - * interupt2 status - */ - -#define SYSTIMER_TARGET2_INT_ST (BIT(2)) -#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S) -#define SYSTIMER_TARGET2_INT_ST_V 0x00000001 -#define SYSTIMER_TARGET2_INT_ST_S 2 - -/* SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0; - * interupt1 status - */ - -#define SYSTIMER_TARGET1_INT_ST (BIT(1)) -#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S) -#define SYSTIMER_TARGET1_INT_ST_V 0x00000001 -#define SYSTIMER_TARGET1_INT_ST_S 1 - -/* SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0; - * interupt0 status - */ - -#define SYSTIMER_TARGET0_INT_ST (BIT(0)) -#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S) -#define SYSTIMER_TARGET0_INT_ST_V 0x00000001 -#define SYSTIMER_TARGET0_INT_ST_S 0 - -/* SYSTIMER_REAL_TARGET0_LO_REG register - * system timer comp0 actual target value low register - */ - -#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74) - -/* SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0; - * actual target value value low 32bits - */ - -#define SYSTIMER_TARGET0_LO_RO 0xffffffff -#define SYSTIMER_TARGET0_LO_RO_M (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S) -#define SYSTIMER_TARGET0_LO_RO_V 0xffffffff -#define SYSTIMER_TARGET0_LO_RO_S 0 - -/* SYSTIMER_REAL_TARGET0_HI_REG register - * system timer comp0 actual target value high register - */ - -#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78) - -/* SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0; - * actual target value value high 20bits - */ - -#define SYSTIMER_TARGET0_HI_RO 0x000fffff -#define SYSTIMER_TARGET0_HI_RO_M (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S) -#define SYSTIMER_TARGET0_HI_RO_V 0x000fffff -#define SYSTIMER_TARGET0_HI_RO_S 0 - -/* SYSTIMER_REAL_TARGET1_LO_REG register - * system timer comp1 actual target value low register - */ - -#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c) - -/* SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0; - * actual target value value low 32bits - */ - -#define SYSTIMER_TARGET1_LO_RO 0xffffffff -#define SYSTIMER_TARGET1_LO_RO_M (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S) -#define SYSTIMER_TARGET1_LO_RO_V 0xffffffff -#define SYSTIMER_TARGET1_LO_RO_S 0 - -/* SYSTIMER_REAL_TARGET1_HI_REG register - * system timer comp1 actual target value high register - */ - -#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80) - -/* SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0; - * actual target value value high 20bits - */ - -#define SYSTIMER_TARGET1_HI_RO 0x000fffff -#define SYSTIMER_TARGET1_HI_RO_M (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S) -#define SYSTIMER_TARGET1_HI_RO_V 0x000fffff -#define SYSTIMER_TARGET1_HI_RO_S 0 - -/* SYSTIMER_REAL_TARGET2_LO_REG register - * system timer comp2 actual target value low register - */ - -#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84) - -/* SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0; - * actual target value value low 32bits - */ - -#define SYSTIMER_TARGET2_LO_RO 0xffffffff -#define SYSTIMER_TARGET2_LO_RO_M (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S) -#define SYSTIMER_TARGET2_LO_RO_V 0xffffffff -#define SYSTIMER_TARGET2_LO_RO_S 0 - -/* SYSTIMER_REAL_TARGET2_HI_REG register - * system timer comp2 actual target value high register - */ - -#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88) - -/* SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0; - * actual target value value high 20bits - */ - -#define SYSTIMER_TARGET2_HI_RO 0x000fffff -#define SYSTIMER_TARGET2_HI_RO_M (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S) -#define SYSTIMER_TARGET2_HI_RO_V 0x000fffff -#define SYSTIMER_TARGET2_HI_RO_S 0 - -/* SYSTIMER_DATE_REG register - * system timer version control register - */ - -#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc) - -/* SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 35655795; - * systimer register version - */ - -#define SYSTIMER_DATE 0xffffffff -#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S) -#define SYSTIMER_DATE_V 0xffffffff -#define SYSTIMER_DATE_S 0 - -#endif /* __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_SYSTIMER_H */ diff --git a/arch/risc-v/src/esp32c6/hardware/esp32c6_uart.h b/arch/risc-v/src/esp32c6/hardware/esp32c6_uart.h deleted file mode 100644 index dedb15ec31e06..0000000000000 --- a/arch/risc-v/src/esp32c6/hardware/esp32c6_uart.h +++ /dev/null @@ -1,2083 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/esp32c6/hardware/esp32c6_uart.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_UART_H -#define __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_UART_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32c6_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* UART_FIFO_REG register - * FIFO data register - */ - -#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) - -/* UART_RXFIFO_RD_BYTE : RO; bitpos: [7:0]; default: 0; - * UART $n accesses FIFO via this register. - */ - -#define UART_RXFIFO_RD_BYTE 0x000000ff -#define UART_RXFIFO_RD_BYTE_M (UART_RXFIFO_RD_BYTE_V << UART_RXFIFO_RD_BYTE_S) -#define UART_RXFIFO_RD_BYTE_V 0x000000ff -#define UART_RXFIFO_RD_BYTE_S 0 - -/* UART_INT_RAW_REG register - * Raw interrupt status - */ - -#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) - -/* UART_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; - * This interrupt raw bit turns to high level when input rxd edge changes - * more times than what reg_active_threshold specifies in light sleeping - * mode. - */ - -#define UART_WAKEUP_INT_RAW (BIT(19)) -#define UART_WAKEUP_INT_RAW_M (UART_WAKEUP_INT_RAW_V << UART_WAKEUP_INT_RAW_S) -#define UART_WAKEUP_INT_RAW_V 0x00000001 -#define UART_WAKEUP_INT_RAW_S 19 - -/* UART_AT_CMD_CHAR_DET_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; - * This interrupt raw bit turns to high level when receiver detects the - * configured at_cmd char. - */ - -#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_RAW_M (UART_AT_CMD_CHAR_DET_INT_RAW_V << UART_AT_CMD_CHAR_DET_INT_RAW_S) -#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x00000001 -#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 - -/* UART_RS485_CLASH_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; - * This interrupt raw bit turns to high level when detects a clash between - * transmitter and receiver in rs485 mode. - */ - -#define UART_RS485_CLASH_INT_RAW (BIT(17)) -#define UART_RS485_CLASH_INT_RAW_M (UART_RS485_CLASH_INT_RAW_V << UART_RS485_CLASH_INT_RAW_S) -#define UART_RS485_CLASH_INT_RAW_V 0x00000001 -#define UART_RS485_CLASH_INT_RAW_S 17 - -/* UART_RS485_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a data - * frame error from the echo of transmitter in rs485 mode. - */ - -#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) -#define UART_RS485_FRM_ERR_INT_RAW_M (UART_RS485_FRM_ERR_INT_RAW_V << UART_RS485_FRM_ERR_INT_RAW_S) -#define UART_RS485_FRM_ERR_INT_RAW_V 0x00000001 -#define UART_RS485_FRM_ERR_INT_RAW_S 16 - -/* UART_RS485_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a parity - * error from the echo of transmitter in rs485 mode. - */ - -#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_RAW_M (UART_RS485_PARITY_ERR_INT_RAW_V << UART_RS485_PARITY_ERR_INT_RAW_S) -#define UART_RS485_PARITY_ERR_INT_RAW_V 0x00000001 -#define UART_RS485_PARITY_ERR_INT_RAW_S 15 - -/* UART_TX_DONE_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; - * This interrupt raw bit turns to high level when transmitter has send out - * all data in FIFO. - */ - -#define UART_TX_DONE_INT_RAW (BIT(14)) -#define UART_TX_DONE_INT_RAW_M (UART_TX_DONE_INT_RAW_V << UART_TX_DONE_INT_RAW_S) -#define UART_TX_DONE_INT_RAW_V 0x00000001 -#define UART_TX_DONE_INT_RAW_S 14 - -/* UART_TX_BRK_IDLE_DONE_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; - * This interrupt raw bit turns to high level when transmitter has kept the - * shortest duration after sending the last data. - */ - -#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (UART_TX_BRK_IDLE_DONE_INT_RAW_V << UART_TX_BRK_IDLE_DONE_INT_RAW_S) -#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x00000001 -#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 - -/* UART_TX_BRK_DONE_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; - * This interrupt raw bit turns to high level when transmitter completes - * sending NULL characters after all data in Tx-FIFO are sent. - */ - -#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) -#define UART_TX_BRK_DONE_INT_RAW_M (UART_TX_BRK_DONE_INT_RAW_V << UART_TX_BRK_DONE_INT_RAW_S) -#define UART_TX_BRK_DONE_INT_RAW_V 0x00000001 -#define UART_TX_BRK_DONE_INT_RAW_S 12 - -/* UART_GLITCH_DET_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a glitch - * in the middle of a start bit. - */ - -#define UART_GLITCH_DET_INT_RAW (BIT(11)) -#define UART_GLITCH_DET_INT_RAW_M (UART_GLITCH_DET_INT_RAW_V << UART_GLITCH_DET_INT_RAW_S) -#define UART_GLITCH_DET_INT_RAW_V 0x00000001 -#define UART_GLITCH_DET_INT_RAW_S 11 - -/* UART_SW_XOFF_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; - * This interrupt raw bit turns to high level when receiver receives Xoff - * char when uart_sw_flow_con_en is set to 1. - */ - -#define UART_SW_XOFF_INT_RAW (BIT(10)) -#define UART_SW_XOFF_INT_RAW_M (UART_SW_XOFF_INT_RAW_V << UART_SW_XOFF_INT_RAW_S) -#define UART_SW_XOFF_INT_RAW_V 0x00000001 -#define UART_SW_XOFF_INT_RAW_S 10 - -/* UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; - * This interrupt raw bit turns to high level when receiver recevies Xon - * char when uart_sw_flow_con_en is set to 1. - */ - -#define UART_SW_XON_INT_RAW (BIT(9)) -#define UART_SW_XON_INT_RAW_M (UART_SW_XON_INT_RAW_V << UART_SW_XON_INT_RAW_S) -#define UART_SW_XON_INT_RAW_V 0x00000001 -#define UART_SW_XON_INT_RAW_S 9 - -/* UART_RXFIFO_TOUT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; - * This interrupt raw bit turns to high level when receiver takes more time - * than rx_tout_thrhd to receive a byte. - */ - -#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) -#define UART_RXFIFO_TOUT_INT_RAW_M (UART_RXFIFO_TOUT_INT_RAW_V << UART_RXFIFO_TOUT_INT_RAW_S) -#define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001 -#define UART_RXFIFO_TOUT_INT_RAW_S 8 - -/* UART_BRK_DET_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a 0 - * after the stop bit. - */ - -#define UART_BRK_DET_INT_RAW (BIT(7)) -#define UART_BRK_DET_INT_RAW_M (UART_BRK_DET_INT_RAW_V << UART_BRK_DET_INT_RAW_S) -#define UART_BRK_DET_INT_RAW_V 0x00000001 -#define UART_BRK_DET_INT_RAW_S 7 - -/* UART_CTS_CHG_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; - * This interrupt raw bit turns to high level when receiver detects the edge - * change of CTSn signal. - */ - -#define UART_CTS_CHG_INT_RAW (BIT(6)) -#define UART_CTS_CHG_INT_RAW_M (UART_CTS_CHG_INT_RAW_V << UART_CTS_CHG_INT_RAW_S) -#define UART_CTS_CHG_INT_RAW_V 0x00000001 -#define UART_CTS_CHG_INT_RAW_S 6 - -/* UART_DSR_CHG_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; - * This interrupt raw bit turns to high level when receiver detects the edge - * change of DSRn signal. - */ - -#define UART_DSR_CHG_INT_RAW (BIT(5)) -#define UART_DSR_CHG_INT_RAW_M (UART_DSR_CHG_INT_RAW_V << UART_DSR_CHG_INT_RAW_S) -#define UART_DSR_CHG_INT_RAW_V 0x00000001 -#define UART_DSR_CHG_INT_RAW_S 5 - -/* UART_RXFIFO_OVF_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; - * This interrupt raw bit turns to high level when receiver receives more - * data than the FIFO can store. - */ - -#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) -#define UART_RXFIFO_OVF_INT_RAW_M (UART_RXFIFO_OVF_INT_RAW_V << UART_RXFIFO_OVF_INT_RAW_S) -#define UART_RXFIFO_OVF_INT_RAW_V 0x00000001 -#define UART_RXFIFO_OVF_INT_RAW_S 4 - -/* UART_FRM_ERR_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a data - * frame error . - */ - -#define UART_FRM_ERR_INT_RAW (BIT(3)) -#define UART_FRM_ERR_INT_RAW_M (UART_FRM_ERR_INT_RAW_V << UART_FRM_ERR_INT_RAW_S) -#define UART_FRM_ERR_INT_RAW_V 0x00000001 -#define UART_FRM_ERR_INT_RAW_S 3 - -/* UART_PARITY_ERR_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; - * This interrupt raw bit turns to high level when receiver detects a parity - * error in the data. - */ - -#define UART_PARITY_ERR_INT_RAW (BIT(2)) -#define UART_PARITY_ERR_INT_RAW_M (UART_PARITY_ERR_INT_RAW_V << UART_PARITY_ERR_INT_RAW_S) -#define UART_PARITY_ERR_INT_RAW_V 0x00000001 -#define UART_PARITY_ERR_INT_RAW_S 2 - -/* UART_TXFIFO_EMPTY_INT_RAW : R/WTC/SS; bitpos: [1]; default: 1; - * This interrupt raw bit turns to high level when the amount of data in - * Tx-FIFO is less than what txfifo_empty_thrhd specifies . - */ - -#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_RAW_M (UART_TXFIFO_EMPTY_INT_RAW_V << UART_TXFIFO_EMPTY_INT_RAW_S) -#define UART_TXFIFO_EMPTY_INT_RAW_V 0x00000001 -#define UART_TXFIFO_EMPTY_INT_RAW_S 1 - -/* UART_RXFIFO_FULL_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; - * This interrupt raw bit turns to high level when receiver receives more - * data than what rxfifo_full_thrhd specifies. - */ - -#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) -#define UART_RXFIFO_FULL_INT_RAW_M (UART_RXFIFO_FULL_INT_RAW_V << UART_RXFIFO_FULL_INT_RAW_S) -#define UART_RXFIFO_FULL_INT_RAW_V 0x00000001 -#define UART_RXFIFO_FULL_INT_RAW_S 0 - -/* UART_INT_ST_REG register - * Masked interrupt status - */ - -#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) - -/* UART_WAKEUP_INT_ST : RO; bitpos: [19]; default: 0; - * This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena - * is set to 1. - */ - -#define UART_WAKEUP_INT_ST (BIT(19)) -#define UART_WAKEUP_INT_ST_M (UART_WAKEUP_INT_ST_V << UART_WAKEUP_INT_ST_S) -#define UART_WAKEUP_INT_ST_V 0x00000001 -#define UART_WAKEUP_INT_ST_S 19 - -/* UART_AT_CMD_CHAR_DET_INT_ST : RO; bitpos: [18]; default: 0; - * This is the status bit for at_cmd_det_int_raw when - * at_cmd_char_det_int_ena is set to 1. - */ - -#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ST_M (UART_AT_CMD_CHAR_DET_INT_ST_V << UART_AT_CMD_CHAR_DET_INT_ST_S) -#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x00000001 -#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 - -/* UART_RS485_CLASH_INT_ST : RO; bitpos: [17]; default: 0; - * This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena - * is set to 1. - */ - -#define UART_RS485_CLASH_INT_ST (BIT(17)) -#define UART_RS485_CLASH_INT_ST_M (UART_RS485_CLASH_INT_ST_V << UART_RS485_CLASH_INT_ST_S) -#define UART_RS485_CLASH_INT_ST_V 0x00000001 -#define UART_RS485_CLASH_INT_ST_S 17 - -/* UART_RS485_FRM_ERR_INT_ST : RO; bitpos: [16]; default: 0; - * This is the status bit for rs485_frm_err_int_raw when - * rs485_fm_err_int_ena is set to 1. - */ - -#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ST_M (UART_RS485_FRM_ERR_INT_ST_V << UART_RS485_FRM_ERR_INT_ST_S) -#define UART_RS485_FRM_ERR_INT_ST_V 0x00000001 -#define UART_RS485_FRM_ERR_INT_ST_S 16 - -/* UART_RS485_PARITY_ERR_INT_ST : RO; bitpos: [15]; default: 0; - * This is the status bit for rs485_parity_err_int_raw when - * rs485_parity_int_ena is set to 1. - */ - -#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ST_M (UART_RS485_PARITY_ERR_INT_ST_V << UART_RS485_PARITY_ERR_INT_ST_S) -#define UART_RS485_PARITY_ERR_INT_ST_V 0x00000001 -#define UART_RS485_PARITY_ERR_INT_ST_S 15 - -/* UART_TX_DONE_INT_ST : RO; bitpos: [14]; default: 0; - * This is the status bit for tx_done_int_raw when tx_done_int_ena is set to - * 1. - */ - -#define UART_TX_DONE_INT_ST (BIT(14)) -#define UART_TX_DONE_INT_ST_M (UART_TX_DONE_INT_ST_V << UART_TX_DONE_INT_ST_S) -#define UART_TX_DONE_INT_ST_V 0x00000001 -#define UART_TX_DONE_INT_ST_S 14 - -/* UART_TX_BRK_IDLE_DONE_INT_ST : RO; bitpos: [13]; default: 0; - * This is the stauts bit for tx_brk_idle_done_int_raw when - * tx_brk_idle_done_int_ena is set to 1. - */ - -#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ST_M (UART_TX_BRK_IDLE_DONE_INT_ST_V << UART_TX_BRK_IDLE_DONE_INT_ST_S) -#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x00000001 -#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 - -/* UART_TX_BRK_DONE_INT_ST : RO; bitpos: [12]; default: 0; - * This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena - * is set to 1. - */ - -#define UART_TX_BRK_DONE_INT_ST (BIT(12)) -#define UART_TX_BRK_DONE_INT_ST_M (UART_TX_BRK_DONE_INT_ST_V << UART_TX_BRK_DONE_INT_ST_S) -#define UART_TX_BRK_DONE_INT_ST_V 0x00000001 -#define UART_TX_BRK_DONE_INT_ST_S 12 - -/* UART_GLITCH_DET_INT_ST : RO; bitpos: [11]; default: 0; - * This is the status bit for glitch_det_int_raw when glitch_det_int_ena is - * set to 1. - */ - -#define UART_GLITCH_DET_INT_ST (BIT(11)) -#define UART_GLITCH_DET_INT_ST_M (UART_GLITCH_DET_INT_ST_V << UART_GLITCH_DET_INT_ST_S) -#define UART_GLITCH_DET_INT_ST_V 0x00000001 -#define UART_GLITCH_DET_INT_ST_S 11 - -/* UART_SW_XOFF_INT_ST : RO; bitpos: [10]; default: 0; - * This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to - * 1. - */ - -#define UART_SW_XOFF_INT_ST (BIT(10)) -#define UART_SW_XOFF_INT_ST_M (UART_SW_XOFF_INT_ST_V << UART_SW_XOFF_INT_ST_S) -#define UART_SW_XOFF_INT_ST_V 0x00000001 -#define UART_SW_XOFF_INT_ST_S 10 - -/* UART_SW_XON_INT_ST : RO; bitpos: [9]; default: 0; - * This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1. - */ - -#define UART_SW_XON_INT_ST (BIT(9)) -#define UART_SW_XON_INT_ST_M (UART_SW_XON_INT_ST_V << UART_SW_XON_INT_ST_S) -#define UART_SW_XON_INT_ST_V 0x00000001 -#define UART_SW_XON_INT_ST_S 9 - -/* UART_RXFIFO_TOUT_INT_ST : RO; bitpos: [8]; default: 0; - * This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena - * is set to 1. - */ - -#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ST_M (UART_RXFIFO_TOUT_INT_ST_V << UART_RXFIFO_TOUT_INT_ST_S) -#define UART_RXFIFO_TOUT_INT_ST_V 0x00000001 -#define UART_RXFIFO_TOUT_INT_ST_S 8 - -/* UART_BRK_DET_INT_ST : RO; bitpos: [7]; default: 0; - * This is the status bit for brk_det_int_raw when brk_det_int_ena is set to - * 1. - */ - -#define UART_BRK_DET_INT_ST (BIT(7)) -#define UART_BRK_DET_INT_ST_M (UART_BRK_DET_INT_ST_V << UART_BRK_DET_INT_ST_S) -#define UART_BRK_DET_INT_ST_V 0x00000001 -#define UART_BRK_DET_INT_ST_S 7 - -/* UART_CTS_CHG_INT_ST : RO; bitpos: [6]; default: 0; - * This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to - * 1. - */ - -#define UART_CTS_CHG_INT_ST (BIT(6)) -#define UART_CTS_CHG_INT_ST_M (UART_CTS_CHG_INT_ST_V << UART_CTS_CHG_INT_ST_S) -#define UART_CTS_CHG_INT_ST_V 0x00000001 -#define UART_CTS_CHG_INT_ST_S 6 - -/* UART_DSR_CHG_INT_ST : RO; bitpos: [5]; default: 0; - * This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to - * 1. - */ - -#define UART_DSR_CHG_INT_ST (BIT(5)) -#define UART_DSR_CHG_INT_ST_M (UART_DSR_CHG_INT_ST_V << UART_DSR_CHG_INT_ST_S) -#define UART_DSR_CHG_INT_ST_V 0x00000001 -#define UART_DSR_CHG_INT_ST_S 5 - -/* UART_RXFIFO_OVF_INT_ST : RO; bitpos: [4]; default: 0; - * This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is - * set to 1. - */ - -#define UART_RXFIFO_OVF_INT_ST (BIT(4)) -#define UART_RXFIFO_OVF_INT_ST_M (UART_RXFIFO_OVF_INT_ST_V << UART_RXFIFO_OVF_INT_ST_S) -#define UART_RXFIFO_OVF_INT_ST_V 0x00000001 -#define UART_RXFIFO_OVF_INT_ST_S 4 - -/* UART_FRM_ERR_INT_ST : RO; bitpos: [3]; default: 0; - * This is the status bit for frm_err_int_raw when frm_err_int_ena is set to - * 1. - */ - -#define UART_FRM_ERR_INT_ST (BIT(3)) -#define UART_FRM_ERR_INT_ST_M (UART_FRM_ERR_INT_ST_V << UART_FRM_ERR_INT_ST_S) -#define UART_FRM_ERR_INT_ST_V 0x00000001 -#define UART_FRM_ERR_INT_ST_S 3 - -/* UART_PARITY_ERR_INT_ST : RO; bitpos: [2]; default: 0; - * This is the status bit for parity_err_int_raw when parity_err_int_ena is - * set to 1. - */ - -#define UART_PARITY_ERR_INT_ST (BIT(2)) -#define UART_PARITY_ERR_INT_ST_M (UART_PARITY_ERR_INT_ST_V << UART_PARITY_ERR_INT_ST_S) -#define UART_PARITY_ERR_INT_ST_V 0x00000001 -#define UART_PARITY_ERR_INT_ST_S 2 - -/* UART_TXFIFO_EMPTY_INT_ST : RO; bitpos: [1]; default: 0; - * This is the status bit for txfifo_empty_int_raw when - * txfifo_empty_int_ena is set to 1. - */ - -#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ST_M (UART_TXFIFO_EMPTY_INT_ST_V << UART_TXFIFO_EMPTY_INT_ST_S) -#define UART_TXFIFO_EMPTY_INT_ST_V 0x00000001 -#define UART_TXFIFO_EMPTY_INT_ST_S 1 - -/* UART_RXFIFO_FULL_INT_ST : RO; bitpos: [0]; default: 0; - * This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena - * is set to 1. - */ - -#define UART_RXFIFO_FULL_INT_ST (BIT(0)) -#define UART_RXFIFO_FULL_INT_ST_M (UART_RXFIFO_FULL_INT_ST_V << UART_RXFIFO_FULL_INT_ST_S) -#define UART_RXFIFO_FULL_INT_ST_V 0x00000001 -#define UART_RXFIFO_FULL_INT_ST_S 0 - -/* UART_INT_ENA_REG register - * Interrupt enable bits - */ - -#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xc) - -/* UART_WAKEUP_INT_ENA : R/W; bitpos: [19]; default: 0; - * This is the enable bit for uart_wakeup_int_st register. - */ - -#define UART_WAKEUP_INT_ENA (BIT(19)) -#define UART_WAKEUP_INT_ENA_M (UART_WAKEUP_INT_ENA_V << UART_WAKEUP_INT_ENA_S) -#define UART_WAKEUP_INT_ENA_V 0x00000001 -#define UART_WAKEUP_INT_ENA_S 19 - -/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W; bitpos: [18]; default: 0; - * This is the enable bit for at_cmd_char_det_int_st register. - */ - -#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_ENA_M (UART_AT_CMD_CHAR_DET_INT_ENA_V << UART_AT_CMD_CHAR_DET_INT_ENA_S) -#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x00000001 -#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 - -/* UART_RS485_CLASH_INT_ENA : R/W; bitpos: [17]; default: 0; - * This is the enable bit for rs485_clash_int_st register. - */ - -#define UART_RS485_CLASH_INT_ENA (BIT(17)) -#define UART_RS485_CLASH_INT_ENA_M (UART_RS485_CLASH_INT_ENA_V << UART_RS485_CLASH_INT_ENA_S) -#define UART_RS485_CLASH_INT_ENA_V 0x00000001 -#define UART_RS485_CLASH_INT_ENA_S 17 - -/* UART_RS485_FRM_ERR_INT_ENA : R/W; bitpos: [16]; default: 0; - * This is the enable bit for rs485_parity_err_int_st register. - */ - -#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) -#define UART_RS485_FRM_ERR_INT_ENA_M (UART_RS485_FRM_ERR_INT_ENA_V << UART_RS485_FRM_ERR_INT_ENA_S) -#define UART_RS485_FRM_ERR_INT_ENA_V 0x00000001 -#define UART_RS485_FRM_ERR_INT_ENA_S 16 - -/* UART_RS485_PARITY_ERR_INT_ENA : R/W; bitpos: [15]; default: 0; - * This is the enable bit for rs485_parity_err_int_st register. - */ - -#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_ENA_M (UART_RS485_PARITY_ERR_INT_ENA_V << UART_RS485_PARITY_ERR_INT_ENA_S) -#define UART_RS485_PARITY_ERR_INT_ENA_V 0x00000001 -#define UART_RS485_PARITY_ERR_INT_ENA_S 15 - -/* UART_TX_DONE_INT_ENA : R/W; bitpos: [14]; default: 0; - * This is the enable bit for tx_done_int_st register. - */ - -#define UART_TX_DONE_INT_ENA (BIT(14)) -#define UART_TX_DONE_INT_ENA_M (UART_TX_DONE_INT_ENA_V << UART_TX_DONE_INT_ENA_S) -#define UART_TX_DONE_INT_ENA_V 0x00000001 -#define UART_TX_DONE_INT_ENA_S 14 - -/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W; bitpos: [13]; default: 0; - * This is the enable bit for tx_brk_idle_done_int_st register. - */ - -#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (UART_TX_BRK_IDLE_DONE_INT_ENA_V << UART_TX_BRK_IDLE_DONE_INT_ENA_S) -#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x00000001 -#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 - -/* UART_TX_BRK_DONE_INT_ENA : R/W; bitpos: [12]; default: 0; - * This is the enable bit for tx_brk_done_int_st register. - */ - -#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) -#define UART_TX_BRK_DONE_INT_ENA_M (UART_TX_BRK_DONE_INT_ENA_V << UART_TX_BRK_DONE_INT_ENA_S) -#define UART_TX_BRK_DONE_INT_ENA_V 0x00000001 -#define UART_TX_BRK_DONE_INT_ENA_S 12 - -/* UART_GLITCH_DET_INT_ENA : R/W; bitpos: [11]; default: 0; - * This is the enable bit for glitch_det_int_st register. - */ - -#define UART_GLITCH_DET_INT_ENA (BIT(11)) -#define UART_GLITCH_DET_INT_ENA_M (UART_GLITCH_DET_INT_ENA_V << UART_GLITCH_DET_INT_ENA_S) -#define UART_GLITCH_DET_INT_ENA_V 0x00000001 -#define UART_GLITCH_DET_INT_ENA_S 11 - -/* UART_SW_XOFF_INT_ENA : R/W; bitpos: [10]; default: 0; - * This is the enable bit for sw_xoff_int_st register. - */ - -#define UART_SW_XOFF_INT_ENA (BIT(10)) -#define UART_SW_XOFF_INT_ENA_M (UART_SW_XOFF_INT_ENA_V << UART_SW_XOFF_INT_ENA_S) -#define UART_SW_XOFF_INT_ENA_V 0x00000001 -#define UART_SW_XOFF_INT_ENA_S 10 - -/* UART_SW_XON_INT_ENA : R/W; bitpos: [9]; default: 0; - * This is the enable bit for sw_xon_int_st register. - */ - -#define UART_SW_XON_INT_ENA (BIT(9)) -#define UART_SW_XON_INT_ENA_M (UART_SW_XON_INT_ENA_V << UART_SW_XON_INT_ENA_S) -#define UART_SW_XON_INT_ENA_V 0x00000001 -#define UART_SW_XON_INT_ENA_S 9 - -/* UART_RXFIFO_TOUT_INT_ENA : R/W; bitpos: [8]; default: 0; - * This is the enable bit for rxfifo_tout_int_st register. - */ - -#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) -#define UART_RXFIFO_TOUT_INT_ENA_M (UART_RXFIFO_TOUT_INT_ENA_V << UART_RXFIFO_TOUT_INT_ENA_S) -#define UART_RXFIFO_TOUT_INT_ENA_V 0x00000001 -#define UART_RXFIFO_TOUT_INT_ENA_S 8 - -/* UART_BRK_DET_INT_ENA : R/W; bitpos: [7]; default: 0; - * This is the enable bit for brk_det_int_st register. - */ - -#define UART_BRK_DET_INT_ENA (BIT(7)) -#define UART_BRK_DET_INT_ENA_M (UART_BRK_DET_INT_ENA_V << UART_BRK_DET_INT_ENA_S) -#define UART_BRK_DET_INT_ENA_V 0x00000001 -#define UART_BRK_DET_INT_ENA_S 7 - -/* UART_CTS_CHG_INT_ENA : R/W; bitpos: [6]; default: 0; - * This is the enable bit for cts_chg_int_st register. - */ - -#define UART_CTS_CHG_INT_ENA (BIT(6)) -#define UART_CTS_CHG_INT_ENA_M (UART_CTS_CHG_INT_ENA_V << UART_CTS_CHG_INT_ENA_S) -#define UART_CTS_CHG_INT_ENA_V 0x00000001 -#define UART_CTS_CHG_INT_ENA_S 6 - -/* UART_DSR_CHG_INT_ENA : R/W; bitpos: [5]; default: 0; - * This is the enable bit for dsr_chg_int_st register. - */ - -#define UART_DSR_CHG_INT_ENA (BIT(5)) -#define UART_DSR_CHG_INT_ENA_M (UART_DSR_CHG_INT_ENA_V << UART_DSR_CHG_INT_ENA_S) -#define UART_DSR_CHG_INT_ENA_V 0x00000001 -#define UART_DSR_CHG_INT_ENA_S 5 - -/* UART_RXFIFO_OVF_INT_ENA : R/W; bitpos: [4]; default: 0; - * This is the enable bit for rxfifo_ovf_int_st register. - */ - -#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) -#define UART_RXFIFO_OVF_INT_ENA_M (UART_RXFIFO_OVF_INT_ENA_V << UART_RXFIFO_OVF_INT_ENA_S) -#define UART_RXFIFO_OVF_INT_ENA_V 0x00000001 -#define UART_RXFIFO_OVF_INT_ENA_S 4 - -/* UART_FRM_ERR_INT_ENA : R/W; bitpos: [3]; default: 0; - * This is the enable bit for frm_err_int_st register. - */ - -#define UART_FRM_ERR_INT_ENA (BIT(3)) -#define UART_FRM_ERR_INT_ENA_M (UART_FRM_ERR_INT_ENA_V << UART_FRM_ERR_INT_ENA_S) -#define UART_FRM_ERR_INT_ENA_V 0x00000001 -#define UART_FRM_ERR_INT_ENA_S 3 - -/* UART_PARITY_ERR_INT_ENA : R/W; bitpos: [2]; default: 0; - * This is the enable bit for parity_err_int_st register. - */ - -#define UART_PARITY_ERR_INT_ENA (BIT(2)) -#define UART_PARITY_ERR_INT_ENA_M (UART_PARITY_ERR_INT_ENA_V << UART_PARITY_ERR_INT_ENA_S) -#define UART_PARITY_ERR_INT_ENA_V 0x00000001 -#define UART_PARITY_ERR_INT_ENA_S 2 - -/* UART_TXFIFO_EMPTY_INT_ENA : R/W; bitpos: [1]; default: 0; - * This is the enable bit for txfifo_empty_int_st register. - */ - -#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_ENA_M (UART_TXFIFO_EMPTY_INT_ENA_V << UART_TXFIFO_EMPTY_INT_ENA_S) -#define UART_TXFIFO_EMPTY_INT_ENA_V 0x00000001 -#define UART_TXFIFO_EMPTY_INT_ENA_S 1 - -/* UART_RXFIFO_FULL_INT_ENA : R/W; bitpos: [0]; default: 0; - * This is the enable bit for rxfifo_full_int_st register. - */ - -#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) -#define UART_RXFIFO_FULL_INT_ENA_M (UART_RXFIFO_FULL_INT_ENA_V << UART_RXFIFO_FULL_INT_ENA_S) -#define UART_RXFIFO_FULL_INT_ENA_V 0x00000001 -#define UART_RXFIFO_FULL_INT_ENA_S 0 - -/* UART_INT_CLR_REG register - * Interrupt clear bits - */ - -#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) - -/* UART_WAKEUP_INT_CLR : WT; bitpos: [19]; default: 0; - * Set this bit to clear the uart_wakeup_int_raw interrupt. - */ - -#define UART_WAKEUP_INT_CLR (BIT(19)) -#define UART_WAKEUP_INT_CLR_M (UART_WAKEUP_INT_CLR_V << UART_WAKEUP_INT_CLR_S) -#define UART_WAKEUP_INT_CLR_V 0x00000001 -#define UART_WAKEUP_INT_CLR_S 19 - -/* UART_AT_CMD_CHAR_DET_INT_CLR : WT; bitpos: [18]; default: 0; - * Set this bit to clear the at_cmd_char_det_int_raw interrupt. - */ - -#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) -#define UART_AT_CMD_CHAR_DET_INT_CLR_M (UART_AT_CMD_CHAR_DET_INT_CLR_V << UART_AT_CMD_CHAR_DET_INT_CLR_S) -#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x00000001 -#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 - -/* UART_RS485_CLASH_INT_CLR : WT; bitpos: [17]; default: 0; - * Set this bit to clear the rs485_clash_int_raw interrupt. - */ - -#define UART_RS485_CLASH_INT_CLR (BIT(17)) -#define UART_RS485_CLASH_INT_CLR_M (UART_RS485_CLASH_INT_CLR_V << UART_RS485_CLASH_INT_CLR_S) -#define UART_RS485_CLASH_INT_CLR_V 0x00000001 -#define UART_RS485_CLASH_INT_CLR_S 17 - -/* UART_RS485_FRM_ERR_INT_CLR : WT; bitpos: [16]; default: 0; - * Set this bit to clear the rs485_frm_err_int_raw interrupt. - */ - -#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) -#define UART_RS485_FRM_ERR_INT_CLR_M (UART_RS485_FRM_ERR_INT_CLR_V << UART_RS485_FRM_ERR_INT_CLR_S) -#define UART_RS485_FRM_ERR_INT_CLR_V 0x00000001 -#define UART_RS485_FRM_ERR_INT_CLR_S 16 - -/* UART_RS485_PARITY_ERR_INT_CLR : WT; bitpos: [15]; default: 0; - * Set this bit to clear the rs485_parity_err_int_raw interrupt. - */ - -#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) -#define UART_RS485_PARITY_ERR_INT_CLR_M (UART_RS485_PARITY_ERR_INT_CLR_V << UART_RS485_PARITY_ERR_INT_CLR_S) -#define UART_RS485_PARITY_ERR_INT_CLR_V 0x00000001 -#define UART_RS485_PARITY_ERR_INT_CLR_S 15 - -/* UART_TX_DONE_INT_CLR : WT; bitpos: [14]; default: 0; - * Set this bit to clear the tx_done_int_raw interrupt. - */ - -#define UART_TX_DONE_INT_CLR (BIT(14)) -#define UART_TX_DONE_INT_CLR_M (UART_TX_DONE_INT_CLR_V << UART_TX_DONE_INT_CLR_S) -#define UART_TX_DONE_INT_CLR_V 0x00000001 -#define UART_TX_DONE_INT_CLR_S 14 - -/* UART_TX_BRK_IDLE_DONE_INT_CLR : WT; bitpos: [13]; default: 0; - * Set this bit to clear the tx_brk_idle_done_int_raw interrupt. - */ - -#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) -#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (UART_TX_BRK_IDLE_DONE_INT_CLR_V << UART_TX_BRK_IDLE_DONE_INT_CLR_S) -#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x00000001 -#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 - -/* UART_TX_BRK_DONE_INT_CLR : WT; bitpos: [12]; default: 0; - * Set this bit to clear the tx_brk_done_int_raw interrupt.. - */ - -#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) -#define UART_TX_BRK_DONE_INT_CLR_M (UART_TX_BRK_DONE_INT_CLR_V << UART_TX_BRK_DONE_INT_CLR_S) -#define UART_TX_BRK_DONE_INT_CLR_V 0x00000001 -#define UART_TX_BRK_DONE_INT_CLR_S 12 - -/* UART_GLITCH_DET_INT_CLR : WT; bitpos: [11]; default: 0; - * Set this bit to clear the glitch_det_int_raw interrupt. - */ - -#define UART_GLITCH_DET_INT_CLR (BIT(11)) -#define UART_GLITCH_DET_INT_CLR_M (UART_GLITCH_DET_INT_CLR_V << UART_GLITCH_DET_INT_CLR_S) -#define UART_GLITCH_DET_INT_CLR_V 0x00000001 -#define UART_GLITCH_DET_INT_CLR_S 11 - -/* UART_SW_XOFF_INT_CLR : WT; bitpos: [10]; default: 0; - * Set this bit to clear the sw_xoff_int_raw interrupt. - */ - -#define UART_SW_XOFF_INT_CLR (BIT(10)) -#define UART_SW_XOFF_INT_CLR_M (UART_SW_XOFF_INT_CLR_V << UART_SW_XOFF_INT_CLR_S) -#define UART_SW_XOFF_INT_CLR_V 0x00000001 -#define UART_SW_XOFF_INT_CLR_S 10 - -/* UART_SW_XON_INT_CLR : WT; bitpos: [9]; default: 0; - * Set this bit to clear the sw_xon_int_raw interrupt. - */ - -#define UART_SW_XON_INT_CLR (BIT(9)) -#define UART_SW_XON_INT_CLR_M (UART_SW_XON_INT_CLR_V << UART_SW_XON_INT_CLR_S) -#define UART_SW_XON_INT_CLR_V 0x00000001 -#define UART_SW_XON_INT_CLR_S 9 - -/* UART_RXFIFO_TOUT_INT_CLR : WT; bitpos: [8]; default: 0; - * Set this bit to clear the rxfifo_tout_int_raw interrupt. - */ - -#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) -#define UART_RXFIFO_TOUT_INT_CLR_M (UART_RXFIFO_TOUT_INT_CLR_V << UART_RXFIFO_TOUT_INT_CLR_S) -#define UART_RXFIFO_TOUT_INT_CLR_V 0x00000001 -#define UART_RXFIFO_TOUT_INT_CLR_S 8 - -/* UART_BRK_DET_INT_CLR : WT; bitpos: [7]; default: 0; - * Set this bit to clear the brk_det_int_raw interrupt. - */ - -#define UART_BRK_DET_INT_CLR (BIT(7)) -#define UART_BRK_DET_INT_CLR_M (UART_BRK_DET_INT_CLR_V << UART_BRK_DET_INT_CLR_S) -#define UART_BRK_DET_INT_CLR_V 0x00000001 -#define UART_BRK_DET_INT_CLR_S 7 - -/* UART_CTS_CHG_INT_CLR : WT; bitpos: [6]; default: 0; - * Set this bit to clear the cts_chg_int_raw interrupt. - */ - -#define UART_CTS_CHG_INT_CLR (BIT(6)) -#define UART_CTS_CHG_INT_CLR_M (UART_CTS_CHG_INT_CLR_V << UART_CTS_CHG_INT_CLR_S) -#define UART_CTS_CHG_INT_CLR_V 0x00000001 -#define UART_CTS_CHG_INT_CLR_S 6 - -/* UART_DSR_CHG_INT_CLR : WT; bitpos: [5]; default: 0; - * Set this bit to clear the dsr_chg_int_raw interrupt. - */ - -#define UART_DSR_CHG_INT_CLR (BIT(5)) -#define UART_DSR_CHG_INT_CLR_M (UART_DSR_CHG_INT_CLR_V << UART_DSR_CHG_INT_CLR_S) -#define UART_DSR_CHG_INT_CLR_V 0x00000001 -#define UART_DSR_CHG_INT_CLR_S 5 - -/* UART_RXFIFO_OVF_INT_CLR : WT; bitpos: [4]; default: 0; - * Set this bit to clear rxfifo_ovf_int_raw interrupt. - */ - -#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) -#define UART_RXFIFO_OVF_INT_CLR_M (UART_RXFIFO_OVF_INT_CLR_V << UART_RXFIFO_OVF_INT_CLR_S) -#define UART_RXFIFO_OVF_INT_CLR_V 0x00000001 -#define UART_RXFIFO_OVF_INT_CLR_S 4 - -/* UART_FRM_ERR_INT_CLR : WT; bitpos: [3]; default: 0; - * Set this bit to clear frm_err_int_raw interrupt. - */ - -#define UART_FRM_ERR_INT_CLR (BIT(3)) -#define UART_FRM_ERR_INT_CLR_M (UART_FRM_ERR_INT_CLR_V << UART_FRM_ERR_INT_CLR_S) -#define UART_FRM_ERR_INT_CLR_V 0x00000001 -#define UART_FRM_ERR_INT_CLR_S 3 - -/* UART_PARITY_ERR_INT_CLR : WT; bitpos: [2]; default: 0; - * Set this bit to clear parity_err_int_raw interrupt. - */ - -#define UART_PARITY_ERR_INT_CLR (BIT(2)) -#define UART_PARITY_ERR_INT_CLR_M (UART_PARITY_ERR_INT_CLR_V << UART_PARITY_ERR_INT_CLR_S) -#define UART_PARITY_ERR_INT_CLR_V 0x00000001 -#define UART_PARITY_ERR_INT_CLR_S 2 - -/* UART_TXFIFO_EMPTY_INT_CLR : WT; bitpos: [1]; default: 0; - * Set this bit to clear txfifo_empty_int_raw interrupt. - */ - -#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) -#define UART_TXFIFO_EMPTY_INT_CLR_M (UART_TXFIFO_EMPTY_INT_CLR_V << UART_TXFIFO_EMPTY_INT_CLR_S) -#define UART_TXFIFO_EMPTY_INT_CLR_V 0x00000001 -#define UART_TXFIFO_EMPTY_INT_CLR_S 1 - -/* UART_RXFIFO_FULL_INT_CLR : WT; bitpos: [0]; default: 0; - * Set this bit to clear the rxfifo_full_int_raw interrupt. - */ - -#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) -#define UART_RXFIFO_FULL_INT_CLR_M (UART_RXFIFO_FULL_INT_CLR_V << UART_RXFIFO_FULL_INT_CLR_S) -#define UART_RXFIFO_FULL_INT_CLR_V 0x00000001 -#define UART_RXFIFO_FULL_INT_CLR_S 0 - -/* UART_CLKDIV_SYNC_REG register - * Clock divider configuration - */ - -#define UART_CLKDIV_SYNC_REG(i) (REG_UART_BASE(i) + 0x14) - -/* UART_CLKDIV_FRAG : R/W; bitpos: [23:20]; default: 0; - * The decimal part of the frequency divider factor. - */ - -#define UART_CLKDIV_FRAG 0x0000000f -#define UART_CLKDIV_FRAG_M (UART_CLKDIV_FRAG_V << UART_CLKDIV_FRAG_S) -#define UART_CLKDIV_FRAG_V 0x0000000f -#define UART_CLKDIV_FRAG_S 20 - -/* UART_CLKDIV : R/W; bitpos: [11:0]; default: 694; - * The integral part of the frequency divider factor. - */ - -#define UART_CLKDIV 0x00000fff -#define UART_CLKDIV_M (UART_CLKDIV_V << UART_CLKDIV_S) -#define UART_CLKDIV_V 0x00000fff -#define UART_CLKDIV_S 0 - -/* UART_RX_FILT_REG register - * Rx Filter configuration - */ - -#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18) - -/* UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0; - * Set this bit to enable Rx signal filter. - */ - -#define UART_GLITCH_FILT_EN (BIT(8)) -#define UART_GLITCH_FILT_EN_M (UART_GLITCH_FILT_EN_V << UART_GLITCH_FILT_EN_S) -#define UART_GLITCH_FILT_EN_V 0x00000001 -#define UART_GLITCH_FILT_EN_S 8 - -/* UART_GLITCH_FILT : R/W; bitpos: [7:0]; default: 8; - * when input pulse width is lower than this value the pulse is ignored. - */ - -#define UART_GLITCH_FILT 0x000000ff -#define UART_GLITCH_FILT_M (UART_GLITCH_FILT_V << UART_GLITCH_FILT_S) -#define UART_GLITCH_FILT_V 0x000000ff -#define UART_GLITCH_FILT_S 0 - -/* UART_STATUS_REG register - * UART status register - */ - -#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1c) - -/* UART_TXD : RO; bitpos: [31]; default: 1; - * This bit represents the level of the internal uart txd signal. - */ - -#define UART_TXD (BIT(31)) -#define UART_TXD_M (UART_TXD_V << UART_TXD_S) -#define UART_TXD_V 0x00000001 -#define UART_TXD_S 31 - -/* UART_RTSN : RO; bitpos: [30]; default: 1; - * This bit represents the level of the internal uart rts signal. - */ - -#define UART_RTSN (BIT(30)) -#define UART_RTSN_M (UART_RTSN_V << UART_RTSN_S) -#define UART_RTSN_V 0x00000001 -#define UART_RTSN_S 30 - -/* UART_DTRN : RO; bitpos: [29]; default: 1; - * This bit represents the level of the internal uart dtr signal. - */ - -#define UART_DTRN (BIT(29)) -#define UART_DTRN_M (UART_DTRN_V << UART_DTRN_S) -#define UART_DTRN_V 0x00000001 -#define UART_DTRN_S 29 - -/* UART_TXFIFO_CNT : RO; bitpos: [23:16]; default: 0; - * Stores the byte number of data in Tx-FIFO. - */ - -#define UART_TXFIFO_CNT 0x000000ff -#define UART_TXFIFO_CNT_M (UART_TXFIFO_CNT_V << UART_TXFIFO_CNT_S) -#define UART_TXFIFO_CNT_V 0x000000ff -#define UART_TXFIFO_CNT_S 16 - -/* UART_RXD : RO; bitpos: [15]; default: 1; - * This register represent the level value of the internal uart rxd signal. - */ - -#define UART_RXD (BIT(15)) -#define UART_RXD_M (UART_RXD_V << UART_RXD_S) -#define UART_RXD_V 0x00000001 -#define UART_RXD_S 15 - -/* UART_CTSN : RO; bitpos: [14]; default: 1; - * This register represent the level value of the internal uart cts signal. - */ - -#define UART_CTSN (BIT(14)) -#define UART_CTSN_M (UART_CTSN_V << UART_CTSN_S) -#define UART_CTSN_V 0x00000001 -#define UART_CTSN_S 14 - -/* UART_DSRN : RO; bitpos: [13]; default: 0; - * The register represent the level value of the internal uart dsr signal. - */ - -#define UART_DSRN (BIT(13)) -#define UART_DSRN_M (UART_DSRN_V << UART_DSRN_S) -#define UART_DSRN_V 0x00000001 -#define UART_DSRN_S 13 - -/* UART_RXFIFO_CNT : RO; bitpos: [7:0]; default: 0; - * Stores the byte number of valid data in Rx-FIFO. - */ - -#define UART_RXFIFO_CNT 0x000000ff -#define UART_RXFIFO_CNT_M (UART_RXFIFO_CNT_V << UART_RXFIFO_CNT_S) -#define UART_RXFIFO_CNT_V 0x000000ff -#define UART_RXFIFO_CNT_S 0 - -/* UART_CONF0_SYNC_REG register - * a - */ - -#define UART_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x20) - -/* UART_TXFIFO_RST : R/W; bitpos: [23]; default: 0; - * Set this bit to reset the uart transmit-FIFO. - */ - -#define UART_TXFIFO_RST (BIT(23)) -#define UART_TXFIFO_RST_M (UART_TXFIFO_RST_V << UART_TXFIFO_RST_S) -#define UART_TXFIFO_RST_V 0x00000001 -#define UART_TXFIFO_RST_S 23 - -/* UART_RXFIFO_RST : R/W; bitpos: [22]; default: 0; - * Set this bit to reset the uart receive-FIFO. - */ - -#define UART_RXFIFO_RST (BIT(22)) -#define UART_RXFIFO_RST_M (UART_RXFIFO_RST_V << UART_RXFIFO_RST_S) -#define UART_RXFIFO_RST_V 0x00000001 -#define UART_RXFIFO_RST_S 22 - -/* UART_SW_RTS : R/W; bitpos: [21]; default: 0; - * This register is used to configure the software rts signal which is used - * in software flow control. - */ - -#define UART_SW_RTS (BIT(21)) -#define UART_SW_RTS_M (UART_SW_RTS_V << UART_SW_RTS_S) -#define UART_SW_RTS_V 0x00000001 -#define UART_SW_RTS_S 21 - -/* UART_MEM_CLK_EN : R/W; bitpos: [20]; default: 1; - * UART memory clock gate enable signal. - */ - -#define UART_MEM_CLK_EN (BIT(20)) -#define UART_MEM_CLK_EN_M (UART_MEM_CLK_EN_V << UART_MEM_CLK_EN_S) -#define UART_MEM_CLK_EN_V 0x00000001 -#define UART_MEM_CLK_EN_S 20 - -/* UART_AUTOBAUD_EN : R/W; bitpos: [19]; default: 0; - * This is the enable bit for detecting baudrate. - */ - -#define UART_AUTOBAUD_EN (BIT(19)) -#define UART_AUTOBAUD_EN_M (UART_AUTOBAUD_EN_V << UART_AUTOBAUD_EN_S) -#define UART_AUTOBAUD_EN_V 0x00000001 -#define UART_AUTOBAUD_EN_S 19 - -/* UART_ERR_WR_MASK : R/W; bitpos: [18]; default: 0; - * 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: - * Receiver stores the data even if the received data is wrong. - */ - -#define UART_ERR_WR_MASK (BIT(18)) -#define UART_ERR_WR_MASK_M (UART_ERR_WR_MASK_V << UART_ERR_WR_MASK_S) -#define UART_ERR_WR_MASK_V 0x00000001 -#define UART_ERR_WR_MASK_S 18 - -/* UART_DIS_RX_DAT_OVF : R/W; bitpos: [17]; default: 0; - * Disable UART Rx data overflow detect. - */ - -#define UART_DIS_RX_DAT_OVF (BIT(17)) -#define UART_DIS_RX_DAT_OVF_M (UART_DIS_RX_DAT_OVF_V << UART_DIS_RX_DAT_OVF_S) -#define UART_DIS_RX_DAT_OVF_V 0x00000001 -#define UART_DIS_RX_DAT_OVF_S 17 - -/* UART_TXD_INV : R/W; bitpos: [16]; default: 0; - * Set this bit to inverse the level value of uart txd signal. - */ - -#define UART_TXD_INV (BIT(16)) -#define UART_TXD_INV_M (UART_TXD_INV_V << UART_TXD_INV_S) -#define UART_TXD_INV_V 0x00000001 -#define UART_TXD_INV_S 16 - -/* UART_RXD_INV : R/W; bitpos: [15]; default: 0; - * Set this bit to inverse the level value of uart rxd signal. - */ - -#define UART_RXD_INV (BIT(15)) -#define UART_RXD_INV_M (UART_RXD_INV_V << UART_RXD_INV_S) -#define UART_RXD_INV_V 0x00000001 -#define UART_RXD_INV_S 15 - -/* UART_IRDA_EN : R/W; bitpos: [14]; default: 0; - * Set this bit to enable IrDA protocol. - */ - -#define UART_IRDA_EN (BIT(14)) -#define UART_IRDA_EN_M (UART_IRDA_EN_V << UART_IRDA_EN_S) -#define UART_IRDA_EN_V 0x00000001 -#define UART_IRDA_EN_S 14 - -/* UART_TX_FLOW_EN : R/W; bitpos: [13]; default: 0; - * Set this bit to enable flow control function for transmitter. - */ - -#define UART_TX_FLOW_EN (BIT(13)) -#define UART_TX_FLOW_EN_M (UART_TX_FLOW_EN_V << UART_TX_FLOW_EN_S) -#define UART_TX_FLOW_EN_V 0x00000001 -#define UART_TX_FLOW_EN_S 13 - -/* UART_LOOPBACK : R/W; bitpos: [12]; default: 0; - * Set this bit to enable uart loopback test mode. - */ - -#define UART_LOOPBACK (BIT(12)) -#define UART_LOOPBACK_M (UART_LOOPBACK_V << UART_LOOPBACK_S) -#define UART_LOOPBACK_V 0x00000001 -#define UART_LOOPBACK_S 12 - -/* UART_IRDA_RX_INV : R/W; bitpos: [11]; default: 0; - * Set this bit to invert the level of IrDA receiver. - */ - -#define UART_IRDA_RX_INV (BIT(11)) -#define UART_IRDA_RX_INV_M (UART_IRDA_RX_INV_V << UART_IRDA_RX_INV_S) -#define UART_IRDA_RX_INV_V 0x00000001 -#define UART_IRDA_RX_INV_S 11 - -/* UART_IRDA_TX_INV : R/W; bitpos: [10]; default: 0; - * Set this bit to invert the level of IrDA transmitter. - */ - -#define UART_IRDA_TX_INV (BIT(10)) -#define UART_IRDA_TX_INV_M (UART_IRDA_TX_INV_V << UART_IRDA_TX_INV_S) -#define UART_IRDA_TX_INV_V 0x00000001 -#define UART_IRDA_TX_INV_S 10 - -/* UART_IRDA_WCTL : R/W; bitpos: [9]; default: 0; - * 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set - * IrDA transmitter's 11th bit to 0. - */ - -#define UART_IRDA_WCTL (BIT(9)) -#define UART_IRDA_WCTL_M (UART_IRDA_WCTL_V << UART_IRDA_WCTL_S) -#define UART_IRDA_WCTL_V 0x00000001 -#define UART_IRDA_WCTL_S 9 - -/* UART_IRDA_TX_EN : R/W; bitpos: [8]; default: 0; - * This is the start enable bit for IrDA transmitter. - */ - -#define UART_IRDA_TX_EN (BIT(8)) -#define UART_IRDA_TX_EN_M (UART_IRDA_TX_EN_V << UART_IRDA_TX_EN_S) -#define UART_IRDA_TX_EN_V 0x00000001 -#define UART_IRDA_TX_EN_S 8 - -/* UART_IRDA_DPLX : R/W; bitpos: [7]; default: 0; - * Set this bit to enable IrDA loopback mode. - */ - -#define UART_IRDA_DPLX (BIT(7)) -#define UART_IRDA_DPLX_M (UART_IRDA_DPLX_V << UART_IRDA_DPLX_S) -#define UART_IRDA_DPLX_V 0x00000001 -#define UART_IRDA_DPLX_S 7 - -/* UART_TXD_BRK : R/W; bitpos: [6]; default: 0; - * Set this bit to enbale transmitter to send NULL when the process of - * sending data is done. - */ - -#define UART_TXD_BRK (BIT(6)) -#define UART_TXD_BRK_M (UART_TXD_BRK_V << UART_TXD_BRK_S) -#define UART_TXD_BRK_V 0x00000001 -#define UART_TXD_BRK_S 6 - -/* UART_STOP_BIT_NUM : R/W; bitpos: [5:4]; default: 1; - * This register is used to set the length of stop bit. - */ - -#define UART_STOP_BIT_NUM 0x00000003 -#define UART_STOP_BIT_NUM_M (UART_STOP_BIT_NUM_V << UART_STOP_BIT_NUM_S) -#define UART_STOP_BIT_NUM_V 0x00000003 -#define UART_STOP_BIT_NUM_S 4 - -/* UART_BIT_NUM : R/W; bitpos: [3:2]; default: 3; - * This register is used to set the length of data. - */ - -#define UART_BIT_NUM 0x00000003 -#define UART_BIT_NUM_M (UART_BIT_NUM_V << UART_BIT_NUM_S) -#define UART_BIT_NUM_V 0x00000003 -#define UART_BIT_NUM_S 2 - -/* UART_PARITY_EN : R/W; bitpos: [1]; default: 0; - * Set this bit to enable uart parity check. - */ - -#define UART_PARITY_EN (BIT(1)) -#define UART_PARITY_EN_M (UART_PARITY_EN_V << UART_PARITY_EN_S) -#define UART_PARITY_EN_V 0x00000001 -#define UART_PARITY_EN_S 1 - -/* UART_PARITY : R/W; bitpos: [0]; default: 0; - * This register is used to configure the parity check mode. - */ - -#define UART_PARITY (BIT(0)) -#define UART_PARITY_M (UART_PARITY_V << UART_PARITY_S) -#define UART_PARITY_V 0x00000001 -#define UART_PARITY_S 0 - -/* UART_CONF1_REG register - * Configuration register 1 - */ - -#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) - -/* UART_CLK_EN : R/W; bitpos: [21]; default: 0; - * 1'h1: Force clock on for register. 1'h0: Support clock only when - * application writes registers. - */ - -#define UART_CLK_EN (BIT(21)) -#define UART_CLK_EN_M (UART_CLK_EN_V << UART_CLK_EN_S) -#define UART_CLK_EN_V 0x00000001 -#define UART_CLK_EN_S 21 - -/* UART_SW_DTR : R/W; bitpos: [20]; default: 0; - * This register is used to configure the software dtr signal which is used - * in software flow control. - */ - -#define UART_SW_DTR (BIT(20)) -#define UART_SW_DTR_M (UART_SW_DTR_V << UART_SW_DTR_S) -#define UART_SW_DTR_V 0x00000001 -#define UART_SW_DTR_S 20 - -/* UART_DTR_INV : R/W; bitpos: [19]; default: 0; - * Set this bit to inverse the level value of uart dtr signal. - */ - -#define UART_DTR_INV (BIT(19)) -#define UART_DTR_INV_M (UART_DTR_INV_V << UART_DTR_INV_S) -#define UART_DTR_INV_V 0x00000001 -#define UART_DTR_INV_S 19 - -/* UART_RTS_INV : R/W; bitpos: [18]; default: 0; - * Set this bit to inverse the level value of uart rts signal. - */ - -#define UART_RTS_INV (BIT(18)) -#define UART_RTS_INV_M (UART_RTS_INV_V << UART_RTS_INV_S) -#define UART_RTS_INV_V 0x00000001 -#define UART_RTS_INV_S 18 - -/* UART_DSR_INV : R/W; bitpos: [17]; default: 0; - * Set this bit to inverse the level value of uart dsr signal. - */ - -#define UART_DSR_INV (BIT(17)) -#define UART_DSR_INV_M (UART_DSR_INV_V << UART_DSR_INV_S) -#define UART_DSR_INV_V 0x00000001 -#define UART_DSR_INV_S 17 - -/* UART_CTS_INV : R/W; bitpos: [16]; default: 0; - * Set this bit to inverse the level value of uart cts signal. - */ - -#define UART_CTS_INV (BIT(16)) -#define UART_CTS_INV_M (UART_CTS_INV_V << UART_CTS_INV_S) -#define UART_CTS_INV_V 0x00000001 -#define UART_CTS_INV_S 16 - -/* UART_TXFIFO_EMPTY_THRHD : R/W; bitpos: [15:8]; default: 96; - * It will produce txfifo_empty_int interrupt when the data amount in - * Tx-FIFO is less than this register value. - */ - -#define UART_TXFIFO_EMPTY_THRHD 0x000000ff -#define UART_TXFIFO_EMPTY_THRHD_M (UART_TXFIFO_EMPTY_THRHD_V << UART_TXFIFO_EMPTY_THRHD_S) -#define UART_TXFIFO_EMPTY_THRHD_V 0x000000ff -#define UART_TXFIFO_EMPTY_THRHD_S 8 - -/* UART_RXFIFO_FULL_THRHD : R/W; bitpos: [7:0]; default: 96; - * It will produce rxfifo_full_int interrupt when receiver receives more - * data than this register value. - */ - -#define UART_RXFIFO_FULL_THRHD 0x000000ff -#define UART_RXFIFO_FULL_THRHD_M (UART_RXFIFO_FULL_THRHD_V << UART_RXFIFO_FULL_THRHD_S) -#define UART_RXFIFO_FULL_THRHD_V 0x000000ff -#define UART_RXFIFO_FULL_THRHD_S 0 - -/* UART_HWFC_CONF_SYNC_REG register - * Hardware flow-control configuration - */ - -#define UART_HWFC_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x2c) - -/* UART_RX_FLOW_EN : R/W; bitpos: [8]; default: 0; - * This is the flow enable bit for UART receiver. - */ - -#define UART_RX_FLOW_EN (BIT(8)) -#define UART_RX_FLOW_EN_M (UART_RX_FLOW_EN_V << UART_RX_FLOW_EN_S) -#define UART_RX_FLOW_EN_V 0x00000001 -#define UART_RX_FLOW_EN_S 8 - -/* UART_RX_FLOW_THRHD : R/W; bitpos: [7:0]; default: 0; - * This register is used to configure the maximum amount of data that can be - * received when hardware flow control works. - */ - -#define UART_RX_FLOW_THRHD 0x000000ff -#define UART_RX_FLOW_THRHD_M (UART_RX_FLOW_THRHD_V << UART_RX_FLOW_THRHD_S) -#define UART_RX_FLOW_THRHD_V 0x000000ff -#define UART_RX_FLOW_THRHD_S 0 - -/* UART_SLEEP_CONF0_REG register - * UART sleep configure register 0 - */ - -#define UART_SLEEP_CONF0_REG(i) (REG_UART_BASE(i) + 0x30) - -/* UART_WK_CHAR4 : R/W; bitpos: [31:24]; default: 0; - * This register restores the specified wake up char4 to wake up - */ - -#define UART_WK_CHAR4 0x000000ff -#define UART_WK_CHAR4_M (UART_WK_CHAR4_V << UART_WK_CHAR4_S) -#define UART_WK_CHAR4_V 0x000000ff -#define UART_WK_CHAR4_S 24 - -/* UART_WK_CHAR3 : R/W; bitpos: [23:16]; default: 0; - * This register restores the specified wake up char3 to wake up - */ - -#define UART_WK_CHAR3 0x000000ff -#define UART_WK_CHAR3_M (UART_WK_CHAR3_V << UART_WK_CHAR3_S) -#define UART_WK_CHAR3_V 0x000000ff -#define UART_WK_CHAR3_S 16 - -/* UART_WK_CHAR2 : R/W; bitpos: [15:8]; default: 0; - * This register restores the specified wake up char2 to wake up - */ - -#define UART_WK_CHAR2 0x000000ff -#define UART_WK_CHAR2_M (UART_WK_CHAR2_V << UART_WK_CHAR2_S) -#define UART_WK_CHAR2_V 0x000000ff -#define UART_WK_CHAR2_S 8 - -/* UART_WK_CHAR1 : R/W; bitpos: [7:0]; default: 0; - * This register restores the specified wake up char1 to wake up - */ - -#define UART_WK_CHAR1 0x000000ff -#define UART_WK_CHAR1_M (UART_WK_CHAR1_V << UART_WK_CHAR1_S) -#define UART_WK_CHAR1_V 0x000000ff -#define UART_WK_CHAR1_S 0 - -/* UART_SLEEP_CONF1_REG register - * UART sleep configure register 1 - */ - -#define UART_SLEEP_CONF1_REG(i) (REG_UART_BASE(i) + 0x34) - -/* UART_WK_CHAR0 : R/W; bitpos: [7:0]; default: 0; - * This register restores the specified char0 to wake up - */ - -#define UART_WK_CHAR0 0x000000ff -#define UART_WK_CHAR0_M (UART_WK_CHAR0_V << UART_WK_CHAR0_S) -#define UART_WK_CHAR0_V 0x000000ff -#define UART_WK_CHAR0_S 0 - -/* UART_SLEEP_CONF2_REG register - * UART sleep configure register 2 - */ - -#define UART_SLEEP_CONF2_REG(i) (REG_UART_BASE(i) + 0x38) - -/* UART_WK_MODE_SEL : R/W; bitpos: [27:26]; default: 0; - * This register is used to select wake up mode. 0: RXD toggling to wake up. - * 1: received data number larger than - */ - -#define UART_WK_MODE_SEL 0x00000003 -#define UART_WK_MODE_SEL_M (UART_WK_MODE_SEL_V << UART_WK_MODE_SEL_S) -#define UART_WK_MODE_SEL_V 0x00000003 -#define UART_WK_MODE_SEL_S 26 - -/* UART_WK_CHAR_MASK : R/W; bitpos: [25:21]; default: 0; - * This register is used to mask wake up char. - */ - -#define UART_WK_CHAR_MASK 0x0000001f -#define UART_WK_CHAR_MASK_M (UART_WK_CHAR_MASK_V << UART_WK_CHAR_MASK_S) -#define UART_WK_CHAR_MASK_V 0x0000001f -#define UART_WK_CHAR_MASK_S 21 - -/* UART_WK_CHAR_NUM : R/W; bitpos: [20:18]; default: 5; - * This register is used to select number of wake up char. - */ - -#define UART_WK_CHAR_NUM 0x00000007 -#define UART_WK_CHAR_NUM_M (UART_WK_CHAR_NUM_V << UART_WK_CHAR_NUM_S) -#define UART_WK_CHAR_NUM_V 0x00000007 -#define UART_WK_CHAR_NUM_S 18 - -/* UART_RX_WAKE_UP_THRHD : R/W; bitpos: [17:10]; default: 1; - * In wake up mode 1 this field is used to set the received data number - * threshold to wake up chip. - */ - -#define UART_RX_WAKE_UP_THRHD 0x000000ff -#define UART_RX_WAKE_UP_THRHD_M (UART_RX_WAKE_UP_THRHD_V << UART_RX_WAKE_UP_THRHD_S) -#define UART_RX_WAKE_UP_THRHD_V 0x000000ff -#define UART_RX_WAKE_UP_THRHD_S 10 - -/* UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; - * The uart is activated from light sleeping mode when the input rxd edge - * changes more times than this register value. - */ - -#define UART_ACTIVE_THRESHOLD 0x000003ff -#define UART_ACTIVE_THRESHOLD_M (UART_ACTIVE_THRESHOLD_V << UART_ACTIVE_THRESHOLD_S) -#define UART_ACTIVE_THRESHOLD_V 0x000003ff -#define UART_ACTIVE_THRESHOLD_S 0 - -/* UART_SWFC_CONF0_SYNC_REG register - * Software flow-control character configuration - */ - -#define UART_SWFC_CONF0_SYNC_REG(i) (REG_UART_BASE(i) + 0x3c) - -/* UART_SEND_XOFF : R/W/SS/SC; bitpos: [22]; default: 0; - * Set this bit to send Xoff char. It is cleared by hardware automatically. - */ - -#define UART_SEND_XOFF (BIT(22)) -#define UART_SEND_XOFF_M (UART_SEND_XOFF_V << UART_SEND_XOFF_S) -#define UART_SEND_XOFF_V 0x00000001 -#define UART_SEND_XOFF_S 22 - -/* UART_SEND_XON : R/W/SS/SC; bitpos: [21]; default: 0; - * Set this bit to send Xon char. It is cleared by hardware automatically. - */ - -#define UART_SEND_XON (BIT(21)) -#define UART_SEND_XON_M (UART_SEND_XON_V << UART_SEND_XON_S) -#define UART_SEND_XON_V 0x00000001 -#define UART_SEND_XON_S 21 - -/* UART_FORCE_XOFF : R/W; bitpos: [20]; default: 0; - * Set this bit to stop the transmitter from sending data. - */ - -#define UART_FORCE_XOFF (BIT(20)) -#define UART_FORCE_XOFF_M (UART_FORCE_XOFF_V << UART_FORCE_XOFF_S) -#define UART_FORCE_XOFF_V 0x00000001 -#define UART_FORCE_XOFF_S 20 - -/* UART_FORCE_XON : R/W; bitpos: [19]; default: 0; - * Set this bit to enable the transmitter to go on sending data. - */ - -#define UART_FORCE_XON (BIT(19)) -#define UART_FORCE_XON_M (UART_FORCE_XON_V << UART_FORCE_XON_S) -#define UART_FORCE_XON_V 0x00000001 -#define UART_FORCE_XON_S 19 - -/* UART_XONOFF_DEL : R/W; bitpos: [18]; default: 0; - * Set this bit to remove flow control char from the received data. - */ - -#define UART_XONOFF_DEL (BIT(18)) -#define UART_XONOFF_DEL_M (UART_XONOFF_DEL_V << UART_XONOFF_DEL_S) -#define UART_XONOFF_DEL_V 0x00000001 -#define UART_XONOFF_DEL_S 18 - -/* UART_SW_FLOW_CON_EN : R/W; bitpos: [17]; default: 0; - * Set this bit to enable software flow control. It is used with register - * sw_xon or sw_xoff. - */ - -#define UART_SW_FLOW_CON_EN (BIT(17)) -#define UART_SW_FLOW_CON_EN_M (UART_SW_FLOW_CON_EN_V << UART_SW_FLOW_CON_EN_S) -#define UART_SW_FLOW_CON_EN_V 0x00000001 -#define UART_SW_FLOW_CON_EN_S 17 - -/* UART_XON_XOFF_STILL_SEND : R/W; bitpos: [16]; default: 0; - * In software flow control mode, UART Tx is disabled once UART Rx receives - * XOFF. In this status, UART Tx can not transmit XOFF even the received - * data number is larger than UART_XOFF_THRESHOLD. Set this bit to enable - * UART Tx can transmit XON/XOFF when UART Tx is disabled. - */ - -#define UART_XON_XOFF_STILL_SEND (BIT(16)) -#define UART_XON_XOFF_STILL_SEND_M (UART_XON_XOFF_STILL_SEND_V << UART_XON_XOFF_STILL_SEND_S) -#define UART_XON_XOFF_STILL_SEND_V 0x00000001 -#define UART_XON_XOFF_STILL_SEND_S 16 - -/* UART_XOFF_CHAR : R/W; bitpos: [15:8]; default: 19; - * This register stores the Xoff flow control char. - */ - -#define UART_XOFF_CHAR 0x000000ff -#define UART_XOFF_CHAR_M (UART_XOFF_CHAR_V << UART_XOFF_CHAR_S) -#define UART_XOFF_CHAR_V 0x000000ff -#define UART_XOFF_CHAR_S 8 - -/* UART_XON_CHAR : R/W; bitpos: [7:0]; default: 17; - * This register stores the Xon flow control char. - */ - -#define UART_XON_CHAR 0x000000ff -#define UART_XON_CHAR_M (UART_XON_CHAR_V << UART_XON_CHAR_S) -#define UART_XON_CHAR_V 0x000000ff -#define UART_XON_CHAR_S 0 - -/* UART_SWFC_CONF1_REG register - * Software flow-control character configuration - */ - -#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) - -/* UART_XOFF_THRESHOLD : R/W; bitpos: [15:8]; default: 224; - * When the data amount in Rx-FIFO is more than this register value with - * uart_sw_flow_con_en set to 1 it will send a Xoff char. - */ - -#define UART_XOFF_THRESHOLD 0x000000ff -#define UART_XOFF_THRESHOLD_M (UART_XOFF_THRESHOLD_V << UART_XOFF_THRESHOLD_S) -#define UART_XOFF_THRESHOLD_V 0x000000ff -#define UART_XOFF_THRESHOLD_S 8 - -/* UART_XON_THRESHOLD : R/W; bitpos: [7:0]; default: 0; - * When the data amount in Rx-FIFO is less than this register value with - * uart_sw_flow_con_en set to 1 it will send a Xon char. - */ - -#define UART_XON_THRESHOLD 0x000000ff -#define UART_XON_THRESHOLD_M (UART_XON_THRESHOLD_V << UART_XON_THRESHOLD_S) -#define UART_XON_THRESHOLD_V 0x000000ff -#define UART_XON_THRESHOLD_S 0 - -/* UART_TXBRK_CONF_SYNC_REG register - * Tx Break character configuration - */ - -#define UART_TXBRK_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x44) - -/* UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; - * This register is used to configure the number of 0 to be sent after the - * process of sending data is done. It is active when txd_brk is set to 1. - */ - -#define UART_TX_BRK_NUM 0x000000ff -#define UART_TX_BRK_NUM_M (UART_TX_BRK_NUM_V << UART_TX_BRK_NUM_S) -#define UART_TX_BRK_NUM_V 0x000000ff -#define UART_TX_BRK_NUM_S 0 - -/* UART_IDLE_CONF_SYNC_REG register - * Frame-end idle configuration - */ - -#define UART_IDLE_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x48) - -/* UART_TX_IDLE_NUM : R/W; bitpos: [19:10]; default: 256; - * This register is used to configure the duration time between transfers. - */ - -#define UART_TX_IDLE_NUM 0x000003ff -#define UART_TX_IDLE_NUM_M (UART_TX_IDLE_NUM_V << UART_TX_IDLE_NUM_S) -#define UART_TX_IDLE_NUM_V 0x000003ff -#define UART_TX_IDLE_NUM_S 10 - -/* UART_RX_IDLE_THRHD : R/W; bitpos: [9:0]; default: 256; - * It will produce frame end signal when receiver takes more time to receive - * one byte data than this register value. - */ - -#define UART_RX_IDLE_THRHD 0x000003ff -#define UART_RX_IDLE_THRHD_M (UART_RX_IDLE_THRHD_V << UART_RX_IDLE_THRHD_S) -#define UART_RX_IDLE_THRHD_V 0x000003ff -#define UART_RX_IDLE_THRHD_S 0 - -/* UART_RS485_CONF_SYNC_REG register - * RS485 mode configuration - */ - -#define UART_RS485_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x4c) - -/* UART_RS485_TX_DLY_NUM : R/W; bitpos: [9:6]; default: 0; - * This register is used to delay the transmitter's internal data signal. - */ - -#define UART_RS485_TX_DLY_NUM 0x0000000f -#define UART_RS485_TX_DLY_NUM_M (UART_RS485_TX_DLY_NUM_V << UART_RS485_TX_DLY_NUM_S) -#define UART_RS485_TX_DLY_NUM_V 0x0000000f -#define UART_RS485_TX_DLY_NUM_S 6 - -/* UART_RS485_RX_DLY_NUM : R/W; bitpos: [5]; default: 0; - * This register is used to delay the receiver's internal data signal. - */ - -#define UART_RS485_RX_DLY_NUM (BIT(5)) -#define UART_RS485_RX_DLY_NUM_M (UART_RS485_RX_DLY_NUM_V << UART_RS485_RX_DLY_NUM_S) -#define UART_RS485_RX_DLY_NUM_V 0x00000001 -#define UART_RS485_RX_DLY_NUM_S 5 - -/* UART_RS485RXBY_TX_EN : R/W; bitpos: [4]; default: 0; - * 1'h1: enable rs485 transmitter to send data when rs485 receiver line is - * busy. - */ - -#define UART_RS485RXBY_TX_EN (BIT(4)) -#define UART_RS485RXBY_TX_EN_M (UART_RS485RXBY_TX_EN_V << UART_RS485RXBY_TX_EN_S) -#define UART_RS485RXBY_TX_EN_V 0x00000001 -#define UART_RS485RXBY_TX_EN_S 4 - -/* UART_RS485TX_RX_EN : R/W; bitpos: [3]; default: 0; - * Set this bit to enable receiver could receive data when the transmitter - * is transmitting data in rs485 mode. - */ - -#define UART_RS485TX_RX_EN (BIT(3)) -#define UART_RS485TX_RX_EN_M (UART_RS485TX_RX_EN_V << UART_RS485TX_RX_EN_S) -#define UART_RS485TX_RX_EN_V 0x00000001 -#define UART_RS485TX_RX_EN_S 3 - -/* UART_DL1_EN : R/W; bitpos: [2]; default: 0; - * Set this bit to delay the stop bit by 1 bit. - */ - -#define UART_DL1_EN (BIT(2)) -#define UART_DL1_EN_M (UART_DL1_EN_V << UART_DL1_EN_S) -#define UART_DL1_EN_V 0x00000001 -#define UART_DL1_EN_S 2 - -/* UART_DL0_EN : R/W; bitpos: [1]; default: 0; - * Set this bit to delay the stop bit by 1 bit. - */ - -#define UART_DL0_EN (BIT(1)) -#define UART_DL0_EN_M (UART_DL0_EN_V << UART_DL0_EN_S) -#define UART_DL0_EN_V 0x00000001 -#define UART_DL0_EN_S 1 - -/* UART_RS485_EN : R/W; bitpos: [0]; default: 0; - * Set this bit to choose the rs485 mode. - */ - -#define UART_RS485_EN (BIT(0)) -#define UART_RS485_EN_M (UART_RS485_EN_V << UART_RS485_EN_S) -#define UART_RS485_EN_V 0x00000001 -#define UART_RS485_EN_S 0 - -/* UART_AT_CMD_PRECNT_SYNC_REG register - * Pre-sequence timing configuration - */ - -#define UART_AT_CMD_PRECNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x50) - -/* UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; - * This register is used to configure the idle duration time before the - * first at_cmd is received by receiver. - */ - -#define UART_PRE_IDLE_NUM 0x0000ffff -#define UART_PRE_IDLE_NUM_M (UART_PRE_IDLE_NUM_V << UART_PRE_IDLE_NUM_S) -#define UART_PRE_IDLE_NUM_V 0x0000ffff -#define UART_PRE_IDLE_NUM_S 0 - -/* UART_AT_CMD_POSTCNT_SYNC_REG register - * Post-sequence timing configuration - */ - -#define UART_AT_CMD_POSTCNT_SYNC_REG(i) (REG_UART_BASE(i) + 0x54) - -/* UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; - * This register is used to configure the duration time between the last - * at_cmd and the next data. - */ - -#define UART_POST_IDLE_NUM 0x0000ffff -#define UART_POST_IDLE_NUM_M (UART_POST_IDLE_NUM_V << UART_POST_IDLE_NUM_S) -#define UART_POST_IDLE_NUM_V 0x0000ffff -#define UART_POST_IDLE_NUM_S 0 - -/* UART_AT_CMD_GAPTOUT_SYNC_REG register - * Timeout configuration - */ - -#define UART_AT_CMD_GAPTOUT_SYNC_REG(i) (REG_UART_BASE(i) + 0x58) - -/* UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; - * This register is used to configure the duration time between the at_cmd - * chars. - */ - -#define UART_RX_GAP_TOUT 0x0000ffff -#define UART_RX_GAP_TOUT_M (UART_RX_GAP_TOUT_V << UART_RX_GAP_TOUT_S) -#define UART_RX_GAP_TOUT_V 0x0000ffff -#define UART_RX_GAP_TOUT_S 0 - -/* UART_AT_CMD_CHAR_SYNC_REG register - * AT escape sequence detection configuration - */ - -#define UART_AT_CMD_CHAR_SYNC_REG(i) (REG_UART_BASE(i) + 0x5c) - -/* UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3; - * This register is used to configure the num of continuous at_cmd chars - * received by receiver. - */ - -#define UART_CHAR_NUM 0x000000ff -#define UART_CHAR_NUM_M (UART_CHAR_NUM_V << UART_CHAR_NUM_S) -#define UART_CHAR_NUM_V 0x000000ff -#define UART_CHAR_NUM_S 8 - -/* UART_AT_CMD_CHAR : R/W; bitpos: [7:0]; default: 43; - * This register is used to configure the content of at_cmd char. - */ - -#define UART_AT_CMD_CHAR 0x000000ff -#define UART_AT_CMD_CHAR_M (UART_AT_CMD_CHAR_V << UART_AT_CMD_CHAR_S) -#define UART_AT_CMD_CHAR_V 0x000000ff -#define UART_AT_CMD_CHAR_S 0 - -/* UART_MEM_CONF_REG register - * UART memory power configuration - */ - -#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60) - -/* UART_MEM_FORCE_PU : R/W; bitpos: [26]; default: 0; - * Set this bit to force power up UART memory. - */ - -#define UART_MEM_FORCE_PU (BIT(26)) -#define UART_MEM_FORCE_PU_M (UART_MEM_FORCE_PU_V << UART_MEM_FORCE_PU_S) -#define UART_MEM_FORCE_PU_V 0x00000001 -#define UART_MEM_FORCE_PU_S 26 - -/* UART_MEM_FORCE_PD : R/W; bitpos: [25]; default: 0; - * Set this bit to force power down UART memory. - */ - -#define UART_MEM_FORCE_PD (BIT(25)) -#define UART_MEM_FORCE_PD_M (UART_MEM_FORCE_PD_V << UART_MEM_FORCE_PD_S) -#define UART_MEM_FORCE_PD_V 0x00000001 -#define UART_MEM_FORCE_PD_S 25 - -/* UART_TOUT_CONF_SYNC_REG register - * UART threshold and allocation configuration - */ - -#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64) - -/* UART_RX_TOUT_THRHD : R/W; bitpos: [11:2]; default: 10; - * This register is used to configure the threshold time that receiver takes - * to receive one byte. The rxfifo_tout_int interrupt will be trigger when - * the receiver takes more time to receive one byte with rx_tout_en set to 1. - */ - -#define UART_RX_TOUT_THRHD 0x000003ff -#define UART_RX_TOUT_THRHD_M (UART_RX_TOUT_THRHD_V << UART_RX_TOUT_THRHD_S) -#define UART_RX_TOUT_THRHD_V 0x000003ff -#define UART_RX_TOUT_THRHD_S 2 - -/* UART_RX_TOUT_FLOW_DIS : R/W; bitpos: [1]; default: 0; - * Set this bit to stop accumulating idle_cnt when hardware flow control - * works. - */ - -#define UART_RX_TOUT_FLOW_DIS (BIT(1)) -#define UART_RX_TOUT_FLOW_DIS_M (UART_RX_TOUT_FLOW_DIS_V << UART_RX_TOUT_FLOW_DIS_S) -#define UART_RX_TOUT_FLOW_DIS_V 0x00000001 -#define UART_RX_TOUT_FLOW_DIS_S 1 - -/* UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0; - * This is the enble bit for uart receiver's timeout function. - */ - -#define UART_RX_TOUT_EN (BIT(0)) -#define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S) -#define UART_RX_TOUT_EN_V 0x00000001 -#define UART_RX_TOUT_EN_S 0 - -/* UART_MEM_TX_STATUS_REG register - * Tx-SRAM write and read offset address. - */ - -#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68) - -/* UART_TX_SRAM_RADDR : RO; bitpos: [16:9]; default: 0; - * This register stores the offset read address in Tx-SRAM. - */ - -#define UART_TX_SRAM_RADDR 0x000000ff -#define UART_TX_SRAM_RADDR_M (UART_TX_SRAM_RADDR_V << UART_TX_SRAM_RADDR_S) -#define UART_TX_SRAM_RADDR_V 0x000000ff -#define UART_TX_SRAM_RADDR_S 9 - -/* UART_TX_SRAM_WADDR : RO; bitpos: [7:0]; default: 0; - * This register stores the offset write address in Tx-SRAM. - */ - -#define UART_TX_SRAM_WADDR 0x000000ff -#define UART_TX_SRAM_WADDR_M (UART_TX_SRAM_WADDR_V << UART_TX_SRAM_WADDR_S) -#define UART_TX_SRAM_WADDR_V 0x000000ff -#define UART_TX_SRAM_WADDR_S 0 - -/* UART_MEM_RX_STATUS_REG register - * Rx-SRAM write and read offset address. - */ - -#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c) - -/* UART_RX_SRAM_WADDR : RO; bitpos: [16:9]; default: 128; - * This register stores the offset write address in Rx-SRAM. - */ - -#define UART_RX_SRAM_WADDR 0x000000ff -#define UART_RX_SRAM_WADDR_M (UART_RX_SRAM_WADDR_V << UART_RX_SRAM_WADDR_S) -#define UART_RX_SRAM_WADDR_V 0x000000ff -#define UART_RX_SRAM_WADDR_S 9 - -/* UART_RX_SRAM_RADDR : RO; bitpos: [7:0]; default: 128; - * This register stores the offset read address in RX-SRAM. - */ - -#define UART_RX_SRAM_RADDR 0x000000ff -#define UART_RX_SRAM_RADDR_M (UART_RX_SRAM_RADDR_V << UART_RX_SRAM_RADDR_S) -#define UART_RX_SRAM_RADDR_V 0x000000ff -#define UART_RX_SRAM_RADDR_S 0 - -/* UART_FSM_STATUS_REG register - * UART transmit and receive status. - */ - -#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x70) - -/* UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0; - * This is the status register of transmitter. - */ - -#define UART_ST_UTX_OUT 0x0000000f -#define UART_ST_UTX_OUT_M (UART_ST_UTX_OUT_V << UART_ST_UTX_OUT_S) -#define UART_ST_UTX_OUT_V 0x0000000f -#define UART_ST_UTX_OUT_S 4 - -/* UART_ST_URX_OUT : RO; bitpos: [3:0]; default: 0; - * This is the status register of receiver. - */ - -#define UART_ST_URX_OUT 0x0000000f -#define UART_ST_URX_OUT_M (UART_ST_URX_OUT_V << UART_ST_URX_OUT_S) -#define UART_ST_URX_OUT_V 0x0000000f -#define UART_ST_URX_OUT_S 0 - -/* UART_POSPULSE_REG register - * Autobaud high pulse register - */ - -#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x74) - -/* UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; - * This register stores the minimal input clock count between two positive - * edges. It is used in boudrate-detect process. - */ - -#define UART_POSEDGE_MIN_CNT 0x00000fff -#define UART_POSEDGE_MIN_CNT_M (UART_POSEDGE_MIN_CNT_V << UART_POSEDGE_MIN_CNT_S) -#define UART_POSEDGE_MIN_CNT_V 0x00000fff -#define UART_POSEDGE_MIN_CNT_S 0 - -/* UART_NEGPULSE_REG register - * Autobaud low pulse register - */ - -#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x78) - -/* UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; - * This register stores the minimal input clock count between two negative - * edges. It is used in boudrate-detect process. - */ - -#define UART_NEGEDGE_MIN_CNT 0x00000fff -#define UART_NEGEDGE_MIN_CNT_M (UART_NEGEDGE_MIN_CNT_V << UART_NEGEDGE_MIN_CNT_S) -#define UART_NEGEDGE_MIN_CNT_V 0x00000fff -#define UART_NEGEDGE_MIN_CNT_S 0 - -/* UART_LOWPULSE_REG register - * Autobaud minimum low pulse duration register - */ - -#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x7c) - -/* UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the minimum duration time of the low - * level pulse. It is used in baud rate-detect process. - */ - -#define UART_LOWPULSE_MIN_CNT 0x00000fff -#define UART_LOWPULSE_MIN_CNT_M (UART_LOWPULSE_MIN_CNT_V << UART_LOWPULSE_MIN_CNT_S) -#define UART_LOWPULSE_MIN_CNT_V 0x00000fff -#define UART_LOWPULSE_MIN_CNT_S 0 - -/* UART_HIGHPULSE_REG register - * Autobaud minimum high pulse duration register - */ - -#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80) - -/* UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; - * This register stores the value of the maxinum duration time for the high - * level pulse. It is used in baud rate-detect process. - */ - -#define UART_HIGHPULSE_MIN_CNT 0x00000fff -#define UART_HIGHPULSE_MIN_CNT_M (UART_HIGHPULSE_MIN_CNT_V << UART_HIGHPULSE_MIN_CNT_S) -#define UART_HIGHPULSE_MIN_CNT_V 0x00000fff -#define UART_HIGHPULSE_MIN_CNT_S 0 - -/* UART_RXD_CNT_REG register - * Autobaud edge change count register - */ - -#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x84) - -/* UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0; - * This register stores the count of rxd edge change. It is used in baud - * rate-detect process. - */ - -#define UART_RXD_EDGE_CNT 0x000003ff -#define UART_RXD_EDGE_CNT_M (UART_RXD_EDGE_CNT_V << UART_RXD_EDGE_CNT_S) -#define UART_RXD_EDGE_CNT_V 0x000003ff -#define UART_RXD_EDGE_CNT_S 0 - -/* UART_CLK_CONF_REG register - * UART core clock configuration - */ - -#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88) - -/* UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0; - * Write 1 then write 0 to this bit to reset UART Rx. - */ - -#define UART_RX_RST_CORE (BIT(27)) -#define UART_RX_RST_CORE_M (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S) -#define UART_RX_RST_CORE_V 0x00000001 -#define UART_RX_RST_CORE_S 27 - -/* UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0; - * Write 1 then write 0 to this bit to reset UART Tx. - */ - -#define UART_TX_RST_CORE (BIT(26)) -#define UART_TX_RST_CORE_M (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S) -#define UART_TX_RST_CORE_V 0x00000001 -#define UART_TX_RST_CORE_S 26 - -/* UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1; - * Set this bit to enable UART Rx clock. - */ - -#define UART_RX_SCLK_EN (BIT(25)) -#define UART_RX_SCLK_EN_M (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S) -#define UART_RX_SCLK_EN_V 0x00000001 -#define UART_RX_SCLK_EN_S 25 - -/* UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1; - * Set this bit to enable UART Tx clock. - */ - -#define UART_TX_SCLK_EN (BIT(24)) -#define UART_TX_SCLK_EN_M (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S) -#define UART_TX_SCLK_EN_V 0x00000001 -#define UART_TX_SCLK_EN_S 24 - -/* UART_RST_CORE : R/W; bitpos: [23]; default: 0; - * Write 1 then write 0 to this bit to reset UART Tx/Rx. - */ - -#define UART_RST_CORE (BIT(23)) -#define UART_RST_CORE_M (UART_RST_CORE_V << UART_RST_CORE_S) -#define UART_RST_CORE_V 0x00000001 -#define UART_RST_CORE_S 23 - -/* UART_SCLK_EN : R/W; bitpos: [22]; default: 1; - * Set this bit to enable UART Tx/Rx clock. - */ - -#define UART_SCLK_EN (BIT(22)) -#define UART_SCLK_EN_M (UART_SCLK_EN_V << UART_SCLK_EN_S) -#define UART_SCLK_EN_V 0x00000001 -#define UART_SCLK_EN_S 22 - -/* UART_SCLK_SEL : R/W; bitpos: [21:20]; default: 3; - * UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL. - */ - -#define UART_SCLK_SEL 0x00000003 -#define UART_SCLK_SEL_M (UART_SCLK_SEL_V << UART_SCLK_SEL_S) -#define UART_SCLK_SEL_V 0x00000003 -#define UART_SCLK_SEL_S 20 - -/* UART_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1; - * The integral part of the frequency divider factor. - */ - -#define UART_SCLK_DIV_NUM 0x000000ff -#define UART_SCLK_DIV_NUM_M (UART_SCLK_DIV_NUM_V << UART_SCLK_DIV_NUM_S) -#define UART_SCLK_DIV_NUM_V 0x000000ff -#define UART_SCLK_DIV_NUM_S 12 - -/* UART_SCLK_DIV_A : R/W; bitpos: [11:6]; default: 0; - * The numerator of the frequency divider factor. - */ - -#define UART_SCLK_DIV_A 0x0000003f -#define UART_SCLK_DIV_A_M (UART_SCLK_DIV_A_V << UART_SCLK_DIV_A_S) -#define UART_SCLK_DIV_A_V 0x0000003f -#define UART_SCLK_DIV_A_S 6 - -/* UART_SCLK_DIV_B : R/W; bitpos: [5:0]; default: 0; - * The denominator of the frequency divider factor. - */ - -#define UART_SCLK_DIV_B 0x0000003f -#define UART_SCLK_DIV_B_M (UART_SCLK_DIV_B_V << UART_SCLK_DIV_B_S) -#define UART_SCLK_DIV_B_V 0x0000003f -#define UART_SCLK_DIV_B_S 0 - -/* UART_DATE_REG register - * UART Version register - */ - -#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x8c) - -/* UART_DATE : R/W; bitpos: [31:0]; default: 35656288; - * This is the version register. - */ - -#define UART_DATE 0xffffffff -#define UART_DATE_M (UART_DATE_V << UART_DATE_S) -#define UART_DATE_V 0xffffffff -#define UART_DATE_S 0 - -/* UART_AFIFO_STATUS_REG register - * UART AFIFO Status - */ - -#define UART_AFIFO_STATUS_REG(i) (REG_UART_BASE(i) + 0x90) - -/* UART_RX_AFIFO_EMPTY : RO; bitpos: [3]; default: 1; - * Empty signal of APB RX AFIFO. - */ - -#define UART_RX_AFIFO_EMPTY (BIT(3)) -#define UART_RX_AFIFO_EMPTY_M (UART_RX_AFIFO_EMPTY_V << UART_RX_AFIFO_EMPTY_S) -#define UART_RX_AFIFO_EMPTY_V 0x00000001 -#define UART_RX_AFIFO_EMPTY_S 3 - -/* UART_RX_AFIFO_FULL : RO; bitpos: [2]; default: 0; - * Full signal of APB RX AFIFO. - */ - -#define UART_RX_AFIFO_FULL (BIT(2)) -#define UART_RX_AFIFO_FULL_M (UART_RX_AFIFO_FULL_V << UART_RX_AFIFO_FULL_S) -#define UART_RX_AFIFO_FULL_V 0x00000001 -#define UART_RX_AFIFO_FULL_S 2 - -/* UART_TX_AFIFO_EMPTY : RO; bitpos: [1]; default: 1; - * Empty signal of APB TX AFIFO. - */ - -#define UART_TX_AFIFO_EMPTY (BIT(1)) -#define UART_TX_AFIFO_EMPTY_M (UART_TX_AFIFO_EMPTY_V << UART_TX_AFIFO_EMPTY_S) -#define UART_TX_AFIFO_EMPTY_V 0x00000001 -#define UART_TX_AFIFO_EMPTY_S 1 - -/* UART_TX_AFIFO_FULL : RO; bitpos: [0]; default: 0; - * Full signal of APB TX AFIFO. - */ - -#define UART_TX_AFIFO_FULL (BIT(0)) -#define UART_TX_AFIFO_FULL_M (UART_TX_AFIFO_FULL_V << UART_TX_AFIFO_FULL_S) -#define UART_TX_AFIFO_FULL_V 0x00000001 -#define UART_TX_AFIFO_FULL_S 0 - -/* UART_REG_UPDATE_REG register - * UART Registers Configuration Update register - */ - -#define UART_REG_UPDATE_REG(i) (REG_UART_BASE(i) + 0x98) - -/* UART_REG_UPDATE : R/W/SC; bitpos: [0]; default: 0; - * Software write 1 would synchronize registers into UART Core clock domain - * and would be cleared by hardware after synchronization is done. - */ - -#define UART_REG_UPDATE (BIT(0)) -#define UART_REG_UPDATE_M (UART_REG_UPDATE_V << UART_REG_UPDATE_S) -#define UART_REG_UPDATE_V 0x00000001 -#define UART_REG_UPDATE_S 0 - -/* UART_ID_REG register - * UART ID register - */ - -#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x9c) - -/* UART_ID : R/W; bitpos: [31:0]; default: 1280; - * This register is used to configure the uart_id. - */ - -#define UART_ID 0xffffffff -#define UART_ID_M (UART_ID_V << UART_ID_S) -#define UART_ID_V 0xffffffff -#define UART_ID_S 0 - -#endif /* __ARCH_RISCV_SRC_ESP32C6_HARDWARE_ESP32C6_UART_H */ diff --git a/arch/risc-v/src/esp32h2/.gitignore b/arch/risc-v/src/esp32h2/.gitignore new file mode 100644 index 0000000000000..d40b86f3a0dce --- /dev/null +++ b/arch/risc-v/src/esp32h2/.gitignore @@ -0,0 +1,4 @@ +/bootloader +/esp-nuttx-bootloader +/*.zip +/esp-hal-3rdparty diff --git a/arch/risc-v/src/esp32h2/Kconfig b/arch/risc-v/src/esp32h2/Kconfig new file mode 100644 index 0000000000000..cd7f3510ddd8b --- /dev/null +++ b/arch/risc-v/src/esp32h2/Kconfig @@ -0,0 +1,10 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_ESP32H2 + +source "arch/risc-v/src/common/espressif/Kconfig" + +endif # ARCH_CHIP_ESP32H2 diff --git a/arch/risc-v/src/esp32h2/Make.defs b/arch/risc-v/src/esp32h2/Make.defs new file mode 100644 index 0000000000000..98a16698f1fe7 --- /dev/null +++ b/arch/risc-v/src/esp32h2/Make.defs @@ -0,0 +1,24 @@ +############################################################################ +# arch/risc-v/src/esp32h2/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include common/Make.defs +include common/espressif/Make.defs + +CFLAGS += ${DEFINE_PREFIX}_RETARGETABLE_LOCKING diff --git a/arch/risc-v/src/esp32h2/hal_esp32h2.mk b/arch/risc-v/src/esp32h2/hal_esp32h2.mk new file mode 100644 index 0000000000000..12190c1e718e5 --- /dev/null +++ b/arch/risc-v/src/esp32h2/hal_esp32h2.mk @@ -0,0 +1,160 @@ +############################################################################ +# arch/risc-v/src/esp32c6/esp32h2.mk +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Include header paths + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/nuttx/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/nuttx/$(CHIP_SERIES)/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_common/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/include/esp_private +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/include/soc +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/include/$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/include/private +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/public_compat +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_timer/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/platform_port/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/log +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/log/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/riscv/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/spi_flash/include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/spi_flash/include/spi_flash +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/driver/twai/include + +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/private_include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/bootloader_flash/include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/spi_flash/include + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/spi_flash/include/spi_flash + INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_app_format/include +endif + +# Linker scripts + +ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.ld +ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.api.ld +ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.newlib.ld +ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.spiflash.ld +ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.version.ld +ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.wdt.ld +ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/ld/$(CHIP_SERIES).peripherals.ld + +# Source files + +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/src/esp_efuse_api.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/src/esp_efuse_utility.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/esp_efuse_fields.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/esp_efuse_table.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/esp_efuse_utility.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/clk_ctrl_os.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/cpu.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/esp_clk.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/hw_random.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/modem_clock.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/periph_ctrl.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/regi2c_ctrl.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/esp_clk_tree_common.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/esp_clk_tree.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/cpu_region_protect.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/pmu_init.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/pmu_param.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_clk.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_clk_init.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_time.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/sar_periph_ctrl.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/systimer.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_regi2c_$(CHIP_SERIES).c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_systimer.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_wdt.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/brownout.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/soc/$(CHIP_SERIES)/clk.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/soc/$(CHIP_SERIES)/system_internal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/brownout_hal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/cache_hal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/efuse_hal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/gpio_hal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/ledc_hal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/ledc_hal_iram.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/lp_timer_hal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/rmt_hal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/timer_hal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/timer_hal_iram.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/mpu_hal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/mmu_hal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/uart_hal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/uart_hal_iram.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/wdt_hal_iram.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/clk_tree_hal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/efuse_hal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/modem_clock_hal.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/log/log.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/log/log_noos.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/riscv/interrupt.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/gpio_periph.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/ledc_periph.c +CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/rmt_periph.c + +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/nuttx/src/bootloader_banner_wrap.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_console.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_console_loader.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/${CHIP_SERIES}/bootloader_${CHIP_SERIES}.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_init.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_common.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_common_loader.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/bootloader_flash/src/bootloader_flash.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_${CHIP_SERIES}.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_clock_init.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_clock_loader.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_efuse.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_mem.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_random.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/bootloader_random_${CHIP_SERIES}.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/esp_image_format.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/${CHIP_SERIES}/bootloader_soc.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/${CHIP_SERIES}/bootloader_sha.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/bootloader_support/src/flash_encrypt.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/${CHIP_SERIES}/uart_periph.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_uart.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_sys.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_spiflash.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/src/esp_efuse_fields.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/twai_hal.c + CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/twai_hal_iram.c + + LDFLAGS += --wrap=bootloader_print_banner +endif diff --git a/arch/risc-v/src/espressif/Bootloader.mk b/arch/risc-v/src/espressif/Bootloader.mk deleted file mode 100644 index 15621de18f26c..0000000000000 --- a/arch/risc-v/src/espressif/Bootloader.mk +++ /dev/null @@ -1,125 +0,0 @@ -############################################################################ -# arch/risc-v/src/espressif/Bootloader.mk -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -# Remove quotes from CONFIG_ESPRESSIF_CHIP_SERIES configuration - -CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES)) - -TOOLSDIR = $(TOPDIR)/tools/espressif -CHIPDIR = $(TOPDIR)/arch/risc-v/src/chip -HALDIR = $(CHIPDIR)/esp-hal-3rdparty -BOOTLOADER_SRCDIR = $(CHIPDIR)/bootloader -BOOTLOADER_OUTDIR = $(BOOTLOADER_SRCDIR)/out -BOOTLOADER_CONFIG = $(BOOTLOADER_SRCDIR)/bootloader.conf - -# MCUboot - -MCUBOOT_SRCDIR = $(BOOTLOADER_SRCDIR)/mcuboot -MCUBOOT_ESPDIR = $(MCUBOOT_SRCDIR)/boot/espressif -MCUBOOT_URL = https://github.com/mcu-tools/mcuboot - -# IDFboot - -BLBIN_VERSION = latest -BLBIN_URL = https://github.com/espressif/esp-nuttx-bootloader/releases/download/$(BLBIN_VERSION) - -# Helpers for creating the configuration file - -cfg_en = echo "$(1)=$(if $(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT),1,y)"; -cfg_dis = echo "$(1)=$(if $(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT),0,n)"; -cfg_val = echo "$(1)=$(2)"; - -$(BOOTLOADER_SRCDIR): - $(Q) mkdir -p $(BOOTLOADER_SRCDIR) &>/dev/null - -$(BOOTLOADER_CONFIG): $(TOPDIR)/.config $(BOOTLOADER_SRCDIR) - $(Q) echo "Creating Bootloader configuration" - $(Q) { \ - $(if $(CONFIG_ESPRESSIF_FLASH_2M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_2MB)) \ - $(if $(CONFIG_ESPRESSIF_FLASH_4M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_4MB)) \ - $(if $(CONFIG_ESPRESSIF_FLASH_MODE_DIO),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_DIO)) \ - $(if $(CONFIG_ESPRESSIF_FLASH_MODE_DOUT),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_DOUT)) \ - $(if $(CONFIG_ESPRESSIF_FLASH_MODE_QIO),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_QIO)) \ - $(if $(CONFIG_ESPRESSIF_FLASH_MODE_QOUT),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_QOUT)) \ - $(if $(CONFIG_ESPRESSIF_FLASH_FREQ_80M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_80M)) \ - $(if $(CONFIG_ESPRESSIF_FLASH_FREQ_48M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_48M)) \ - $(if $(CONFIG_ESPRESSIF_FLASH_FREQ_40M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_40M)) \ - $(if $(CONFIG_ESPRESSIF_FLASH_FREQ_26M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_26M)) \ - $(if $(CONFIG_ESPRESSIF_FLASH_FREQ_20M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_20M)) \ - } > $(BOOTLOADER_CONFIG) -ifeq ($(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT),y) - $(Q) { \ - $(call cfg_val,CONFIG_ESP_BOOTLOADER_OFFSET,0x0000) \ - $(call cfg_val,CONFIG_ESP_BOOTLOADER_SIZE,0xF000) \ - $(call cfg_val,CONFIG_ESP_IMAGE0_PRIMARY_START_ADDRESS,$(CONFIG_ESPRESSIF_OTA_PRIMARY_SLOT_OFFSET)) \ - $(call cfg_val,CONFIG_ESP_APPLICATION_SIZE,$(CONFIG_ESPRESSIF_OTA_SLOT_SIZE)) \ - $(call cfg_val,CONFIG_ESP_IMAGE0_SECONDARY_START_ADDRESS,$(CONFIG_ESPRESSIF_OTA_SECONDARY_SLOT_OFFSET)) \ - $(call cfg_en,CONFIG_ESP_MCUBOOT_WDT_ENABLE) \ - $(call cfg_val,CONFIG_ESP_SCRATCH_OFFSET,$(CONFIG_ESPRESSIF_OTA_SCRATCH_OFFSET)) \ - $(call cfg_val,CONFIG_ESP_SCRATCH_SIZE,$(CONFIG_ESPRESSIF_OTA_SCRATCH_SIZE)) \ - $(call cfg_en,CONFIG_ESP_CONSOLE_UART) \ - $(if $(CONFIG_UART0_SERIAL_CONSOLE),$(call cfg_val,CONFIG_ESP_CONSOLE_UART_NUM,0)) \ - $(if $(CONFIG_UART1_SERIAL_CONSOLE),$(call cfg_val,CONFIG_ESP_CONSOLE_UART_NUM,1)) \ - } >> $(BOOTLOADER_CONFIG) -else - $(Q) { \ - $(call cfg_en,CONFIG_PARTITION_TABLE_CUSTOM) \ - $(call cfg_val,CONFIG_PARTITION_TABLE_CUSTOM_FILENAME,\"partitions.csv\") \ - $(call cfg_val,CONFIG_PARTITION_TABLE_OFFSET,$(CONFIG_ESPRESSIF_PARTITION_TABLE_OFFSET)) \ - } >> $(BOOTLOADER_CONFIG) -endif - -ifeq ($(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT),y) - -BOOTLOADER_BIN = $(TOPDIR)/mcuboot-$(CHIP_SERIES).bin - -$(MCUBOOT_SRCDIR): $(BOOTLOADER_SRCDIR) - $(Q) echo "Cloning MCUboot" - $(Q) git clone --quiet $(MCUBOOT_URL) $(MCUBOOT_SRCDIR) - $(Q) git -C "$(MCUBOOT_SRCDIR)" checkout --quiet $(CONFIG_ESPRESSIF_MCUBOOT_VERSION) - $(Q) git -C "$(MCUBOOT_SRCDIR)" submodule --quiet update --init --recursive ext/mbedtls - -$(BOOTLOADER_BIN): chip/$(ESP_HAL_3RDPARTY_REPO) $(MCUBOOT_SRCDIR) $(BOOTLOADER_CONFIG) - $(Q) echo "Building MCUboot" - $(Q) $(TOOLSDIR)/build_mcuboot.sh \ - -c $(CHIP_SERIES) \ - -f $(BOOTLOADER_CONFIG) \ - -p $(BOOTLOADER_SRCDIR) \ - -e $(HALDIR) - $(call COPYFILE, $(BOOTLOADER_OUTDIR)/mcuboot-$(CHIP_SERIES).bin, $(TOPDIR)) - -bootloader: $(BOOTLOADER_CONFIG) $(BOOTLOADER_BIN) - -clean_bootloader: - $(call DELDIR,$(BOOTLOADER_SRCDIR)) - $(call DELFILE,$(BOOTLOADER_BIN)) - -else - -bootloader: - $(Q) echo "Downloading Bootloader binaries" - $(call DOWNLOAD,$(BLBIN_URL),bootloader-$(CHIP_SERIES).bin,$(TOPDIR)/bootloader-$(CHIP_SERIES).bin) - $(call DOWNLOAD,$(BLBIN_URL),partition-table-$(CHIP_SERIES).bin,$(TOPDIR)/partition-table-$(CHIP_SERIES).bin) - -clean_bootloader: - $(call DELFILE,$(TOPDIR)/bootloader-$(CHIP_SERIES).bin) - $(call DELFILE,$(TOPDIR)/partition-table-$(CHIP_SERIES).bin) - -endif diff --git a/arch/risc-v/src/espressif/Kconfig b/arch/risc-v/src/espressif/Kconfig deleted file mode 100644 index 9f2c060b4df1c..0000000000000 --- a/arch/risc-v/src/espressif/Kconfig +++ /dev/null @@ -1,690 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -if ARCH_CHIP_ESPRESSIF - -choice ESPRESSIF_CHIP_SERIES - prompt "Chip Series" - default ESPRESSIF_ESP32C3 - -config ESPRESSIF_ESP32C3 - bool "ESP32-C3" - select ARCH_RV32 - select ARCH_RV_ISA_M - select ARCH_RV_ISA_C - select ARCH_VECNOTIRQ - select ARCH_HAVE_BOOTLOADER - select ARCH_HAVE_MPU - select ARCH_HAVE_RESET - select ARCH_HAVE_RNG - select ARCH_HAVE_TICKLESS - select LIBC_ARCH_ATOMIC - select LIBC_ARCH_MEMCPY - select LIBC_ARCH_MEMCHR - select LIBC_ARCH_MEMCMP - select LIBC_ARCH_MEMMOVE - select LIBC_ARCH_MEMSET - select LIBC_ARCH_STRCHR - select LIBC_ARCH_STRCMP - select LIBC_ARCH_STRCPY - select LIBC_ARCH_STRLCPY - select LIBC_ARCH_STRNCPY - select LIBC_ARCH_STRLEN - select LIBC_ARCH_STRNLEN - select ESPRESSIF_SOC_RTC_MEM_SUPPORTED - ---help--- - ESP32-C3 chip with a single RISC-V IMC core, no embedded Flash memory - -config ESPRESSIF_ESP32C6 - bool "ESP32-C6" - select ARCH_RV32 - select ARCH_RV_ISA_M - select ARCH_RV_ISA_A - select ARCH_RV_ISA_C - select ARCH_VECNOTIRQ - select ARCH_HAVE_BOOTLOADER - select ARCH_HAVE_MPU - select ARCH_HAVE_RESET - select ARCH_HAVE_RNG - select ARCH_HAVE_TICKLESS - select LIBC_ARCH_MEMCPY - select LIBC_ARCH_MEMCHR - select LIBC_ARCH_MEMCMP - select LIBC_ARCH_MEMMOVE - select LIBC_ARCH_MEMSET - select LIBC_ARCH_STRCHR - select LIBC_ARCH_STRCMP - select LIBC_ARCH_STRCPY - select LIBC_ARCH_STRLCPY - select LIBC_ARCH_STRNCPY - select LIBC_ARCH_STRLEN - select LIBC_ARCH_STRNLEN - select ESPRESSIF_SOC_RTC_MEM_SUPPORTED - ---help--- - Espressif ESP32-C6 (RV32IMAC). - -config ESPRESSIF_ESP32H2 - bool "ESP32-H2" - select ARCH_RV32 - select ARCH_RV_ISA_M - select ARCH_RV_ISA_C - select ARCH_VECNOTIRQ - select ARCH_HAVE_BOOTLOADER - select ARCH_HAVE_MPU - select ARCH_HAVE_RESET - select ARCH_HAVE_RNG - select ARCH_HAVE_TICKLESS - select LIBC_ARCH_ATOMIC - select LIBC_ARCH_MEMCPY - select LIBC_ARCH_MEMCHR - select LIBC_ARCH_MEMCMP - select LIBC_ARCH_MEMMOVE - select LIBC_ARCH_MEMSET - select LIBC_ARCH_STRCHR - select LIBC_ARCH_STRCMP - select LIBC_ARCH_STRCPY - select LIBC_ARCH_STRLCPY - select LIBC_ARCH_STRNCPY - select LIBC_ARCH_STRLEN - select LIBC_ARCH_STRNLEN - select ESPRESSIF_ESPTOOLPY_NO_STUB - select ESPRESSIF_SOC_RTC_MEM_SUPPORTED - ---help--- - Espressif ESP32-H2 (RV32IMC). - -endchoice # ESPRESSIF_CHIP_SERIES - -config ESPRESSIF_CHIP_SERIES - string - default "esp32c3" if ESPRESSIF_ESP32C3 - default "esp32c6" if ESPRESSIF_ESP32C6 - default "esp32h2" if ESPRESSIF_ESP32H2 - default "unknown" - -choice ESPRESSIF_FLASH - prompt "Flash Size" - default ESPRESSIF_FLASH_4M if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2 - -config ESPRESSIF_FLASH_2M - bool "2 MB" - -config ESPRESSIF_FLASH_4M - bool "4 MB" - -endchoice # ESPRESSIF_FLASH - -config ESPRESSIF_FLASH_DETECT - bool "Auto-detect FLASH size" - default n - ---help--- - Auto detect flash size when flashing. - -choice ESPRESSIF_CPU_FREQ - prompt "CPU frequency" - default ESPRESSIF_CPU_FREQ_160 if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 - default ESPRESSIF_CPU_FREQ_96 if ESPRESSIF_ESP32H2 - ---help--- - CPU frequency to be set on application startup. - -config ESPRESSIF_CPU_FREQ_40 - bool "40 MHz" - depends on ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 - ---help--- - Set the CPU frequency to 40 MHz. - -config ESPRESSIF_CPU_FREQ_48 - bool "48 MHz" - depends on ESPRESSIF_ESP32H2 - ---help--- - Set the CPU frequency to 48 MHz. - -config ESPRESSIF_CPU_FREQ_64 - bool "64 MHz" - depends on ESPRESSIF_ESP32H2 - ---help--- - Set the CPU frequency to 64 MHz. - -config ESPRESSIF_CPU_FREQ_80 - bool "80 MHz" - depends on ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 - ---help--- - Set the CPU frequency to 80 MHz. - -config ESPRESSIF_CPU_FREQ_96 - bool "96 MHz" - depends on ESPRESSIF_ESP32H2 - ---help--- - Set the CPU frequency to 96 MHz. - -config ESPRESSIF_CPU_FREQ_160 - bool "160 MHz" - depends on ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 - ---help--- - Set the CPU frequency to 160 MHz. - -endchoice # ESPRESSIF_CPU_FREQ - -config ESPRESSIF_CPU_FREQ_MHZ - int - default 40 if ESPRESSIF_CPU_FREQ_40 - default 48 if ESPRESSIF_CPU_FREQ_48 - default 64 if ESPRESSIF_CPU_FREQ_64 - default 80 if ESPRESSIF_CPU_FREQ_80 - default 96 if ESPRESSIF_CPU_FREQ_96 - default 160 if ESPRESSIF_CPU_FREQ_160 - -config ESPRESSIF_REGION_PROTECTION - bool "Enable region protection" - default y - select ARCH_USE_MPU - ---help--- - Configure the MPU to disable access to invalid memory regions. - -config ESPRESSIF_RUN_IRAM - bool "Run from IRAM" - default n - ---help--- - This loads all of NuttX inside IRAM. Used to test somewhat small - images that can fit entirely in IRAM. - -config ESPRESSIF_ESPTOOLPY_NO_STUB - bool "Disable download stub" - default n - ---help--- - The flasher tool sends a precompiled download stub first by default. - That stub allows things like compressed downloads and more. - Usually you should not need to disable that feature. - It is only required to be disabled in certain scenarios when either - Secure Boot V2 or Flash Encryption is enabled. - -config ESPRESSIF_HAL_ASSERTIONS - bool "Enable HAL assertions" - depends on DEBUG_ASSERTIONS - default y - ---help--- - Enable the assertions implemented in the HAL. Otherwise, the assertions - are replaced by empty macros. - -config ESPRESSIF_SOC_RTC_MEM_SUPPORTED - bool - default n - -menu "Bootloader and Image Configuration" - -config ESPRESSIF_BOOTLOADER_MCUBOOT - bool "Enable Native MCUboot" - select ESPRESSIF_HAVE_OTA_PARTITION - depends on ESPRESSIF_ESP32C3 - default n - ---help--- - Enables the Espressif port of MCUboot bootloader. - -config ESPRESSIF_MCUBOOT_VERSION - string "MCUboot version" - depends on ESPRESSIF_BOOTLOADER_MCUBOOT - default "aa7e2b1faae623dbe01bbc6094e71ab44ec9d80a" - -choice - prompt "Target slot for image flashing" - default ESPRESSIF_ESPTOOL_TARGET_PRIMARY - depends on ESPRESSIF_HAVE_OTA_PARTITION - ---help--- - Slot to which ESPTOOL will flash the generated binary image. - -config ESPRESSIF_ESPTOOL_TARGET_PRIMARY - bool "Application image primary slot" - ---help--- - This assumes that the generated image is already pre-validated. - This is the recommended option for the initial stages of the - application firmware image development. - -config ESPRESSIF_ESPTOOL_TARGET_SECONDARY - bool "Application image secondary slot" - ---help--- - The application needs to confirm the generated image as valid, - otherwise the bootloader may consider it invalid and perform the - rollback of the update after a reset. - This is the choice most suitable for the development and verification - of a secure firmware update workflow. - -endchoice - -config ESPRESSIF_APP_MCUBOOT_HEADER_SIZE - int "Application image header size (in bytes)" - default 32 - depends on ESPRESSIF_BOOTLOADER_MCUBOOT - -config ESPRESSIF_PARTITION_TABLE_OFFSET - hex "Partition Table offset" - default 0x8000 - depends on !ESPRESSIF_BOOTLOADER_MCUBOOT - -config ESPRESSIF_HAVE_OTA_PARTITION - bool - default n - -if ESPRESSIF_HAVE_OTA_PARTITION - -comment "Application Image OTA Update support" - -config ESPRESSIF_OTA_PRIMARY_SLOT_OFFSET - hex "Application image primary slot offset" - default 0x10000 - -config ESPRESSIF_OTA_PRIMARY_SLOT_DEVPATH - string "Application image primary slot device path" - default "/dev/ota0" - -config ESPRESSIF_OTA_SECONDARY_SLOT_OFFSET - hex "Application image secondary slot offset" - default 0x110000 - -config ESPRESSIF_OTA_SECONDARY_SLOT_DEVPATH - string "Application image secondary slot device path" - default "/dev/ota1" - -config ESPRESSIF_OTA_SLOT_SIZE - hex "Application image slot size (in bytes)" - default 0x100000 - -config ESPRESSIF_OTA_SCRATCH_OFFSET - hex "Scratch partition offset" - default 0x210000 - -config ESPRESSIF_OTA_SCRATCH_SIZE - hex "Scratch partition size" - default 0x40000 - -config ESPRESSIF_OTA_SCRATCH_DEVPATH - string "Scratch partition device path" - default "/dev/otascratch" - -endif # ESPRESSIF_HAVE_OTA_PARTITION - -endmenu # Bootloader and Image Configuration - -menu "Peripheral Support" - -config ESPRESSIF_UART - bool - default n - -config ESPRESSIF_UART0 - bool "UART0" - default y - select ESPRESSIF_UART - select UART0_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - -config ESPRESSIF_UART1 - bool "UART1" - default n - select ESPRESSIF_UART - select UART1_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - -config ESPRESSIF_USBSERIAL - bool "USB-Serial-JTAG Driver" - default n - select OTHER_UART_SERIALDRIVER - select ARCH_HAVE_SERIAL_TERMIOS - -config ESPRESSIF_GPIO_IRQ - bool "GPIO pin interrupts" - default n - ---help--- - Enable support for interrupting GPIO pins - -config ESPRESSIF_LEDC - bool "LEDC (PWM)" - default n - select PWM - select ARCH_HAVE_PWM_MULTICHAN - -config ESPRESSIF_HR_TIMER - bool - default RTC_DRIVER - ---help--- - A high-resolution hardware timer for supporting the management of - kernel events. - The HR Timer is built on top of the System Timer (SYSTIMER) peripheral. - Timer callbacks are dispatched from a high-priority kernel task. - -config ESPRESSIF_BROWNOUT_DET - bool "Brownout Detector" - default y - ---help--- - A built-in brownout detector which can detect if the voltage is lower - than a specific value. If this happens, it will reset the chip in - order to prevent unintended behaviour. - -endmenu # Peripheral Support - -menu "UART Configuration" - depends on ESPRESSIF_UART - -if ESPRESSIF_UART0 - -config ESPRESSIF_UART0_TXPIN - int "UART0 TX Pin" - default 21 if ESPRESSIF_ESP32C3 - default 16 if ESPRESSIF_ESP32C6 - default 24 if ESPRESSIF_ESP32H2 - range 0 21 if ESPRESSIF_ESP32C3 - range 0 30 if ESPRESSIF_ESP32C6 - range 0 27 if ESPRESSIF_ESP32H2 - -config ESPRESSIF_UART0_RXPIN - int "UART0 RX Pin" - default 20 if ESPRESSIF_ESP32C3 - default 17 if ESPRESSIF_ESP32C6 - default 23 if ESPRESSIF_ESP32H2 - range 0 21 if ESPRESSIF_ESP32C3 - range 0 30 if ESPRESSIF_ESP32C6 - range 0 27 if ESPRESSIF_ESP32H2 - -config ESPRESSIF_UART0_RTSPIN - int "UART0 RTS Pin" - depends on SERIAL_IFLOWCONTROL - default 16 if ESPRESSIF_ESP32C3 - default 15 if ESPRESSIF_ESP32C6 - default 22 if ESPRESSIF_ESP32H2 - range 0 21 if ESPRESSIF_ESP32C3 - range 0 30 if ESPRESSIF_ESP32C6 - range 0 27 if ESPRESSIF_ESP32H2 - -config ESPRESSIF_UART0_CTSPIN - int "UART0 CTS Pin" - depends on SERIAL_OFLOWCONTROL - default 15 if ESPRESSIF_ESP32C3 - default 14 if ESPRESSIF_ESP32C6 - default 21 if ESPRESSIF_ESP32H2 - range 0 21 if ESPRESSIF_ESP32C3 - range 0 30 if ESPRESSIF_ESP32C6 - range 0 27 if ESPRESSIF_ESP32H2 - -endif # ESPRESSIF_UART0 - -if ESPRESSIF_UART1 - -config ESPRESSIF_UART1_TXPIN - int "UART1 TX Pin" - default 8 if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2 - -config ESPRESSIF_UART1_RXPIN - int "UART1 RX Pin" - default 9 if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2 - -config ESPRESSIF_UART1_RTSPIN - int "UART1 RTS Pin" - depends on SERIAL_IFLOWCONTROL - default 1 if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2 - range 0 21 if ESPRESSIF_ESP32C3 - range 0 30 if ESPRESSIF_ESP32C6 - range 0 27 if ESPRESSIF_ESP32H2 - -config ESPRESSIF_UART1_CTSPIN - int "UART1 CTS Pin" - depends on SERIAL_OFLOWCONTROL - default 2 if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2 - range 0 21 if ESPRESSIF_ESP32C3 - range 0 30 if ESPRESSIF_ESP32C6 - range 0 27 if ESPRESSIF_ESP32H2 - -endif # ESPRESSIF_UART1 - -endmenu # UART Configuration - -menu "SPI Flash Configuration" - -choice ESPRESSIF_FLASH_MODE - prompt "SPI Flash mode" - default ESPRESSIF_FLASH_MODE_DIO - ---help--- - These options control how many I/O pins are used for communication with the attached SPI Flash chip. - The option selected here is then used by esptool when flashing. - -config ESPRESSIF_FLASH_MODE_DIO - bool "Dual IO (DIO)" - -config ESPRESSIF_FLASH_MODE_DOUT - bool "Dual Output (DOUT)" - -config ESPRESSIF_FLASH_MODE_QIO - bool "Quad IO (QIO)" - -config ESPRESSIF_FLASH_MODE_QOUT - bool "Quad Output (QOUT)" - -endchoice # ESPRESSIF_FLASH_MODE - -choice ESPRESSIF_FLASH_FREQ - prompt "SPI Flash frequency" - default ESPRESSIF_FLASH_FREQ_80M if ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 - default ESPRESSIF_FLASH_FREQ_48M if ESPRESSIF_ESP32H2 - ---help--- - SPI Flash frequency. - -config ESPRESSIF_FLASH_FREQ_80M - bool "80 MHz" - depends on ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 - -config ESPRESSIF_FLASH_FREQ_48M - bool "48 MHz" - depends on ESPRESSIF_ESP32H2 - -config ESPRESSIF_FLASH_FREQ_40M - bool "40 MHz" - depends on ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 - -config ESPRESSIF_FLASH_FREQ_26M - bool "26 MHz" - depends on ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 - -config ESPRESSIF_FLASH_FREQ_20M - bool "20 MHz" - depends on ESPRESSIF_ESP32C3 || ESPRESSIF_ESP32C6 - -endchoice # ESPRESSIF_FLASH_FREQ - -endmenu # SPI Flash Configuration - -menu "LEDC configuration" - depends on ESPRESSIF_LEDC - -config ESPRESSIF_LEDC_HPOINT - hex "LEDC hpoint value" - default 0x0000 - range 0x0 0xfffff - -menuconfig ESPRESSIF_LEDC_TIMER0 - bool "Timer 0" - default n - -if ESPRESSIF_LEDC_TIMER0 - -config ESPRESSIF_LEDC_TIMER0_CHANNELS - int "Number of Timer 0 channels" - default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1 - default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1 - range 0 6 - -config ESPRESSIF_LEDC_TIMER0_RESOLUTION - int "Timer 0 resolution" - default 13 - range 1 14 if ESPRESSIF_ESP32C3 && !(ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2) - range 1 20 if !ESPRESSIF_ESP32C3 && (ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2) - ---help--- - Timer resolution in bits. The resolution is the number of bits used to by the timer - counter to generate the PWM signal. The duty cycle provided by the upper layers - will be scaled to fit the resolution. - -endif # ESPRESSIF_LEDC_TIMER0 - -menuconfig ESPRESSIF_LEDC_TIMER1 - bool "Timer 1" - default n - -if ESPRESSIF_LEDC_TIMER1 - -config ESPRESSIF_LEDC_TIMER1_CHANNELS - int "Number of Timer 1 channels" - default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1 - default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1 - range 0 6 - -config ESPRESSIF_LEDC_TIMER1_RESOLUTION - int "Timer 1 resolution" - default 13 - range 1 14 if ESPRESSIF_ESP32C3 && !(ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2) - range 1 20 if !ESPRESSIF_ESP32C3 && (ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2) - ---help--- - Timer resolution in bits. The resolution is the number of bits used to by the timer - counter to generate the PWM signal. The duty cycle provided by the upper layers - will be scaled to fit the resolution. - -endif # ESPRESSIF_LEDC_TIMER1 - -menuconfig ESPRESSIF_LEDC_TIMER2 - bool "Timer 2" - default n - -if ESPRESSIF_LEDC_TIMER2 - -config ESPRESSIF_LEDC_TIMER2_CHANNELS - int "Number of Timer 2 channels" - default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1 - default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1 - range 0 6 - -config ESPRESSIF_LEDC_TIMER2_RESOLUTION - int "Timer 2 resolution" - default 13 - range 1 14 if ESPRESSIF_ESP32C3 && !(ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2) - range 1 20 if !ESPRESSIF_ESP32C3 && (ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2) - ---help--- - Timer resolution in bits. The resolution is the number of bits used to by the timer - counter to generate the PWM signal. The duty cycle provided by the upper layers - will be scaled to fit the resolution. - -endif # ESPRESSIF_LEDC_TIMER2 - -menuconfig ESPRESSIF_LEDC_TIMER3 - bool "Timer 3" - default n - -if ESPRESSIF_LEDC_TIMER3 - -config ESPRESSIF_LEDC_TIMER3_CHANNELS - int "Number of Timer 3 channels" - default 2 if PWM_MULTICHAN && PWM_NCHANNELS > 1 - default 1 if !PWM_MULTICHAN || PWM_NCHANNELS = 1 - range 0 6 - -config ESPRESSIF_LEDC_TIMER3_RESOLUTION - int "Timer 3 resolution" - default 13 - range 1 14 if ESPRESSIF_ESP32C3 && !(ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2) - range 1 20 if !ESPRESSIF_ESP32C3 && (ESPRESSIF_ESP32C6 || ESPRESSIF_ESP32H2) - ---help--- - Timer resolution in bits. The resolution is the number of bits used to by the timer - counter to generate the PWM signal. The duty cycle provided by the upper layers - will be scaled to fit the resolution. - -endif # ESPRESSIF_LEDC_TIMER3 - -config ESPRESSIF_LEDC_CHANNEL0_PIN - int "Channel 0 pin" - default 2 - -config ESPRESSIF_LEDC_CHANNEL1_PIN - int "Channel 1 pin" - default 3 - -config ESPRESSIF_LEDC_CHANNEL2_PIN - int "Channel 2 pin" - default 4 - -config ESPRESSIF_LEDC_CHANNEL3_PIN - int "Channel 3 pin" - default 5 - -if PWM_MULTICHAN && PWM_NCHANNELS > 1 - -config ESPRESSIF_LEDC_CHANNEL4_PIN - int "Channel 4 pin" - default 6 - -config ESPRESSIF_LEDC_CHANNEL5_PIN - int "Channel 5 pin" - default 7 - -endif # PWM_MULTICHAN && PWM_NCHANNELS > 1 - -endmenu # LEDC configuration - -menu "High Resolution Timer" - depends on ESPRESSIF_HR_TIMER - -config ESPRESSIF_HR_TIMER_TASK_NAME - string "High Resolution Timer task name" - default "hr_timer" - -config ESPRESSIF_HR_TIMER_TASK_PRIORITY - int "High Resolution Timer task priority" - default 223 - ---help--- - Priority level of the High Resolution Timer task. - Must be lower than the SCHED_HPWORKPRIORITY. - -config ESPRESSIF_HR_TIMER_TASK_STACK_SIZE - int "High Resolution Timer task stack size" - default 2048 - -endmenu # High Resolution Timer - -menu "Brownout Detector Configuration" - depends on ESPRESSIF_BROWNOUT_DET - -choice ESPRESSIF_BROWNOUT_DET_LVL_SEL - prompt "Brownout voltage level" - default ESPRESSIF_BROWNOUT_DET_LVL_SEL_7 - ---help--- - The brownout detector will reset the chip when the supply voltage is - approximately below this level. Note that there may be some variation - of brownout voltage level between each chip. - -config ESPRESSIF_BROWNOUT_DET_LVL_SEL_7 - bool "2.51V" - -config ESPRESSIF_BROWNOUT_DET_LVL_SEL_6 - bool "2.64V" - -config ESPRESSIF_BROWNOUT_DET_LVL_SEL_5 - bool "2.76V" - -config ESPRESSIF_BROWNOUT_DET_LVL_SEL_4 - bool "2.92V" - -config ESPRESSIF_BROWNOUT_DET_LVL_SEL_3 - bool "3.10V" - -config ESPRESSIF_BROWNOUT_DET_LVL_SEL_2 - bool "3.27V" - -endchoice # ESPRESSIF_BROWNOUT_DET_LVL_SEL - -config ESPRESSIF_BROWNOUT_DET_LVL - int - default 2 if ESPRESSIF_BROWNOUT_DET_LVL_SEL_2 - default 3 if ESPRESSIF_BROWNOUT_DET_LVL_SEL_3 - default 4 if ESPRESSIF_BROWNOUT_DET_LVL_SEL_4 - default 5 if ESPRESSIF_BROWNOUT_DET_LVL_SEL_5 - default 6 if ESPRESSIF_BROWNOUT_DET_LVL_SEL_6 - default 7 if ESPRESSIF_BROWNOUT_DET_LVL_SEL_7 - -endmenu # ESPRESSIF_BROWNOUT_DET - -endif # ARCH_CHIP_ESPRESSIF diff --git a/arch/risc-v/src/espressif/Make.defs b/arch/risc-v/src/espressif/Make.defs deleted file mode 100644 index f0bcfc8f90062..0000000000000 --- a/arch/risc-v/src/espressif/Make.defs +++ /dev/null @@ -1,118 +0,0 @@ -############################################################################ -# arch/risc-v/src/espressif/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include common/Make.defs - -# The start-up, "head", file. May be either a .S or a .c file. - -HEAD_ASRC = esp_head.S - -# Skip common RISC-V vector table in favor of Espressif's custom vector -# table. - -CMN_ASRCS := $(filter-out riscv_vectors.S,$(CMN_ASRCS)) -CHIP_ASRCS = esp_vectors.S - -# Required Espressif chip's files (arch/risc-v/src/espressif) - -CHIP_CSRCS = esp_allocateheap.c esp_start.c esp_idle.c -CHIP_CSRCS += esp_irq.c esp_gpio.c esp_libc_stubs.c -CHIP_CSRCS += esp_lowputc.c esp_serial.c -CHIP_CSRCS += esp_systemreset.c - -ifeq ($(CONFIG_SCHED_TICKLESS),y) - CHIP_CSRCS += esp_tickless.c -else - CHIP_CSRCS += esp_timerisr.c -endif - -ifeq ($(CONFIG_WATCHDOG),y) - CHIP_CSRCS += esp_wdt.c -endif - -ifneq ($(CONFIG_DEV_RANDOM)$(CONFIG_DEV_URANDOM_ARCH),) - CHIP_CSRCS += esp_random.c -endif - -ifeq ($(CONFIG_TIMER),y) - CHIP_CSRCS += esp_timer.c -endif - -ifeq ($(CONFIG_ONESHOT),y) - CHIP_CSRCS += esp_oneshot.c -endif - -ifeq ($(CONFIG_RTC),y) - CHIP_CSRCS += esp_rtc.c -endif - -ifeq ($(CONFIG_ESPRESSIF_HR_TIMER),y) - CHIP_CSRCS += esp_hr_timer.c -endif - -ifeq ($(CONFIG_ESPRESSIF_LEDC),y) - CHIP_CSRCS += esp_ledc.c -endif - -ifeq ($(CONFIG_ESPRESSIF_USBSERIAL),y) - CHIP_CSRCS += esp_usbserial.c -endif - -############################################################################# -# Espressif HAL for 3rd Party Platforms -############################################################################# - -# Fetch source files and add them to build - -ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty -ifndef ESP_HAL_3RDPARTY_VERSION - ESP_HAL_3RDPARTY_VERSION = 22804823777dbbb7f43925b7729b3a32331aa7cd -endif - -ifndef ESP_HAL_3RDPARTY_URL - ESP_HAL_3RDPARTY_URL = https://github.com/espressif/esp-hal-3rdparty.git -endif - -chip/$(ESP_HAL_3RDPARTY_REPO): - $(Q) echo "Cloning Espressif HAL for 3rd Party Platforms" - $(Q) git clone --quiet $(ESP_HAL_3RDPARTY_URL) chip/$(ESP_HAL_3RDPARTY_REPO) - $(Q) echo "Espressif HAL for 3rd Party Platforms: ${ESP_HAL_3RDPARTY_VERSION}" - $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) checkout --quiet $(ESP_HAL_3RDPARTY_VERSION) - -# Silent preprocessor warnings - -CFLAGS += -Wno-undef -Wno-unused-variable - -# Remove quotes from CONFIG_ESPRESSIF_CHIP_SERIES configuration - -CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES)) - -include chip/hal_${CHIP_SERIES}.mk - -context:: chip/$(ESP_HAL_3RDPARTY_REPO) - $(call COPYFILE,chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/include/soc/gpio_sig_map.h,../include/chip/) - $(call COPYFILE,chip/$(ESP_HAL_3RDPARTY_REPO)/nuttx/$(CHIP_SERIES)/include/irq.h,../include/chip/) - -distclean:: - $(call DELFILE,../include/chip/gpio_sig_map.h) - $(call DELFILE,../include/chip/irq.h) - $(call DELDIR,chip/$(ESP_HAL_3RDPARTY_REPO)) - -include chip/Bootloader.mk diff --git a/arch/risc-v/src/espressif/chip.h b/arch/risc-v/src/espressif/chip.h deleted file mode 100644 index 67b4071ed57b6..0000000000000 --- a/arch/risc-v/src/espressif/chip.h +++ /dev/null @@ -1,40 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/espressif/chip.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESPRESSIF_CHIP_H -#define __ARCH_RISCV_SRC_ESPRESSIF_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "esp_memorymap.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Section for exception handler. */ - -#define EXCEPTION_SECTION .iram1 - -#endif /* __ARCH_RISCV_SRC_ESPRESSIF_CHIP_H */ diff --git a/arch/risc-v/src/espressif/esp_irq.h b/arch/risc-v/src/espressif/esp_irq.h deleted file mode 100644 index 6c7a47c146281..0000000000000 --- a/arch/risc-v/src/espressif/esp_irq.h +++ /dev/null @@ -1,151 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/espressif/esp_irq.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESPRESSIF_ESP_IRQ_H -#define __ARCH_RISCV_SRC_ESPRESSIF_ESP_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* CPU interrupt trigger types */ - -typedef enum irq_trigger_e -{ - ESP_IRQ_TRIGGER_LEVEL = 0, /* Level-triggered interrupts */ - ESP_IRQ_TRIGGER_EDGE = 1, /* Edge-triggered interrupts */ -} irq_trigger_t; - -/* CPU interrupt priority levels */ - -typedef enum irq_priority_e -{ - ESP_IRQ_PRIORITY_1 = 1, /* Priority Level 1 */ - ESP_IRQ_PRIORITY_2 = 2, /* Priority Level 2 */ - ESP_IRQ_PRIORITY_3 = 3, /* Priority Level 3 */ - ESP_IRQ_PRIORITY_4 = 4, /* Priority Level 4 */ - ESP_IRQ_PRIORITY_5 = 5, /* Priority Level 5 */ - ESP_IRQ_PRIORITY_6 = 6, /* Priority Level 6 */ - ESP_IRQ_PRIORITY_7 = 7, /* Priority Level 7 */ - ESP_IRQ_PRIORITY_8 = 8, /* Priority Level 8 */ - ESP_IRQ_PRIORITY_9 = 9, /* Priority Level 9 */ - ESP_IRQ_PRIORITY_10 = 10, /* Priority Level 10 */ - ESP_IRQ_PRIORITY_11 = 11, /* Priority Level 11 */ - ESP_IRQ_PRIORITY_12 = 12, /* Priority Level 12 */ - ESP_IRQ_PRIORITY_13 = 13, /* Priority Level 13 */ - ESP_IRQ_PRIORITY_14 = 14, /* Priority Level 14 */ - ESP_IRQ_PRIORITY_15 = 15, /* Priority Level 15 */ - ESP_IRQ_PRIORITY_DEFAULT = ESP_IRQ_PRIORITY_1 /* Default Priority */ -} irq_priority_t; - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_route_intr - * - * Description: - * Assign an interrupt source to a pre-allocated CPU interrupt. - * - * Input Parameters: - * source - Interrupt source (see irq.h) to be assigned to a CPU - * interrupt. - * cpuint - Pre-allocated CPU interrupt to which the interrupt - * source will be assigned. - * priority - Interrupt priority. - * type - Interrupt trigger type. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_route_intr(int source, int cpuint, irq_priority_t priority, - irq_trigger_t type); - -/**************************************************************************** - * Name: esp_setup_irq - * - * Description: - * This function sets up the IRQ. It allocates a CPU interrupt of the given - * priority and type and attaches it to a given interrupt source. - * - * Input Parameters: - * source - The interrupt source from irq.h to be assigned to - * a CPU interrupt. - * priority - Interrupt priority. - * type - Interrupt trigger type. - * - * Returned Value: - * Allocated CPU interrupt. - * - ****************************************************************************/ - -int esp_setup_irq(int source, irq_priority_t priority, irq_trigger_t type); - -/**************************************************************************** - * Name: esp_teardown_irq - * - * Description: - * This function undoes the operations done by esp_setup_irq. - * It detaches an interrupt source from a CPU interrupt and frees the - * CPU interrupt. - * - * Input Parameters: - * source - The interrupt source from irq.h to be detached from the - * CPU interrupt. - * cpuint - The CPU interrupt from which the interrupt source will - * be detached. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_teardown_irq(int source, int cpuint); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESPRESSIF_ESP_IRQ_H */ diff --git a/arch/risc-v/src/espressif/esp_start.c b/arch/risc-v/src/espressif/esp_start.c deleted file mode 100644 index 8265f4cb6d9db..0000000000000 --- a/arch/risc-v/src/espressif/esp_start.c +++ /dev/null @@ -1,321 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/espressif/esp_start.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "riscv_internal.h" - -#include "esp_irq.h" -#include "esp_libc_stubs.h" -#include "esp_lowputc.h" -#include "esp_start.h" - -#include "esp_clk_internal.h" -#include "esp_cpu.h" -#include "esp_private/brownout.h" -#include "hal/wdt_hal.h" -#include "soc/ext_mem_defs.h" -#include "soc/extmem_reg.h" -#include "soc/mmu.h" -#include "soc/reg_base.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_FEATURES -# define showprogress(c) riscv_lowputc(c) -#else -# define showprogress(c) -#endif - -#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT -# define PRIMARY_SLOT_OFFSET CONFIG_ESPRESSIF_OTA_PRIMARY_SLOT_OFFSET -# define HDR_ATTR __attribute__((section(".entry_addr"))) \ - __attribute__((used)) -# define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE) -# define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t)) -# define MMU_BLOCK_SIZE 0x00010000 /* 64 KB */ -# define MMU_FLASH_MASK (~(MMU_BLOCK_SIZE - 1)) -# define CACHE_REG EXTMEM_ICACHE_CTRL1_REG -# define CACHE_MASK (EXTMEM_ICACHE_SHUT_IBUS_M | \ - EXTMEM_ICACHE_SHUT_DBUS_M) -#endif - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT -extern uint8_t _image_irom_vma[]; -extern uint8_t _image_irom_lma[]; -extern uint8_t _image_irom_size[]; - -extern uint8_t _image_drom_vma[]; -extern uint8_t _image_drom_lma[]; -extern uint8_t _image_drom_size[]; -#endif - -/**************************************************************************** - * ROM Function Prototypes - ****************************************************************************/ - -#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT -extern int ets_printf(const char *fmt, ...) printf_like(1, 2); -extern uint32_t cache_suspend_icache(void); -extern void cache_resume_icache(uint32_t val); -extern void cache_invalidate_icache_all(void); - -#ifdef CONFIG_ESPRESSIF_ESP32C3 -extern int cache_dbus_mmu_set(uint32_t ext_ram, uint32_t vaddr, - uint32_t paddr, uint32_t psize, uint32_t num, - uint32_t fixed); -extern int cache_ibus_mmu_set(uint32_t ext_ram, uint32_t vaddr, - uint32_t paddr, uint32_t psize, uint32_t num, - uint32_t fixed); -#elif defined(CONFIG_ESPRESSIF_ESP32C6) -extern bool ets_efuse_cache_encryption_enabled(void); -extern int cache_mspi_mmu_set(uint32_t sensitive, uint32_t ext_ram, - uint32_t vaddr, uint32_t paddr, uint32_t psize, - uint32_t num, uint32_t fixed); -#endif - -#endif - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT -IRAM_ATTR noreturn_function void __start(void); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT -HDR_ATTR static void (*_entry_point)(void) = __start; -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Address of the IDLE thread */ - -uint8_t g_idlestack[CONFIG_IDLETHREAD_STACKSIZE] - aligned_data(16) locate_data(".noinit"); -uintptr_t g_idle_topstack = ESP_IDLESTACK_TOP; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: calc_mmu_pages - * - * Description: - * Calculate the number of cache pages to map. - * - * Input Parameters: - * size - Size of data to map - * vaddr - Virtual address where data will be mapped - * - * Returned Value: - * Number of cache MMU pages required to do the mapping. - * - ****************************************************************************/ - -#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT -static inline uint32_t calc_mmu_pages(uint32_t size, uint32_t vaddr) -{ - return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_BLOCK_SIZE - 1) / - MMU_BLOCK_SIZE; -} -#endif - -/**************************************************************************** - * Name: map_rom_segments - * - * Description: - * Configure the MMU and Cache peripherals for accessing ROM code and data. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT -static int map_rom_segments(void) -{ - uint32_t rc = 0; - uint32_t regval; - uint32_t drom_lma_aligned; - uint32_t drom_vma_aligned; - uint32_t drom_page_count; - uint32_t irom_lma_aligned; - uint32_t irom_vma_aligned; - uint32_t irom_page_count; - - size_t partition_offset = PRIMARY_SLOT_OFFSET; - uint32_t app_irom_lma = partition_offset + (uint32_t)_image_irom_lma; - uint32_t app_irom_size = (uint32_t)_image_irom_size; - uint32_t app_irom_vma = (uint32_t)_image_irom_vma; - uint32_t app_drom_lma = partition_offset + (uint32_t)_image_drom_lma; - uint32_t app_drom_size = (uint32_t)_image_drom_size; - uint32_t app_drom_vma = (uint32_t)_image_drom_vma; - - uint32_t autoload = cache_suspend_icache(); - cache_invalidate_icache_all(); - - /* Clear the MMU entries that are already set up, so the new app only has - * the mappings it creates. - */ - - for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) - { - FLASH_MMU_TABLE[i] = MMU_INVALID; - } - - drom_lma_aligned = app_drom_lma & MMU_FLASH_MASK; - drom_vma_aligned = app_drom_vma & MMU_FLASH_MASK; - drom_page_count = calc_mmu_pages(app_drom_size, app_drom_vma); - rc = cache_dbus_mmu_set(MMU_ACCESS_FLASH, drom_vma_aligned, - drom_lma_aligned, 64, (int)drom_page_count, 0); - - irom_lma_aligned = app_irom_lma & MMU_FLASH_MASK; - irom_vma_aligned = app_irom_vma & MMU_FLASH_MASK; - irom_page_count = calc_mmu_pages(app_irom_size, app_irom_vma); - rc |= cache_ibus_mmu_set(MMU_ACCESS_FLASH, irom_vma_aligned, - irom_lma_aligned, 64, (int)irom_page_count, 0); - - regval = getreg32(CACHE_REG); - regval &= ~(CACHE_MASK); - putreg32(regval, CACHE_REG); - - cache_resume_icache(autoload); - - return (int)rc; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: __esp_start - ****************************************************************************/ - -void __esp_start(void) -{ -#ifdef CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT - if (map_rom_segments() != 0) - { - ets_printf("Failed to setup XIP, aborting\n"); - while (true); - } - -#endif - -#ifdef CONFIG_ESPRESSIF_REGION_PROTECTION - /* Configure region protection */ - - esp_cpu_configure_region_protection(); -#endif - - /* Configures the CPU clock, RTC slow and fast clocks, and performs - * RTC slow clock calibration. - */ - - esp_clk_init(); - - /* Disable clock of unused peripherals */ - - esp_perip_clk_init(); - -#ifdef CONFIG_ESPRESSIF_BROWNOUT_DET - /* Initialize hardware brownout check and reset */ - - esp_brownout_init(); -#endif - - /* Configure the UART so we can get debug output */ - - esp_lowsetup(); - -#ifdef USE_EARLYSERIALINIT - /* Perform early serial initialization */ - - riscv_earlyserialinit(); -#endif - - showprogress('A'); - - /* Clear .bss. We'll do this inline (vs. calling memset) just to be - * certain that there are no issues with the state of global variables. - */ - - for (uint32_t *dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; ) - { - *dest++ = 0; - } - - /* Setup the syscall table needed by the ROM code */ - - esp_setup_syscall_table(); - - showprogress('B'); - - /* The 2nd stage bootloader enables RTC WDT to monitor any issues that may - * prevent the startup sequence from finishing correctly. Hence disable it - * as NuttX is about to start. - */ - - wdt_hal_context_t rwdt_ctx = RWDT_HAL_CONTEXT_DEFAULT(); - wdt_hal_write_protect_disable(&rwdt_ctx); - wdt_hal_disable(&rwdt_ctx); - wdt_hal_write_protect_enable(&rwdt_ctx); - - /* Initialize onboard resources */ - - esp_board_initialize(); - - showprogress('C'); - - /* Bring up NuttX */ - - nx_start(); - - for (; ; ); -} diff --git a/arch/risc-v/src/espressif/esp_wdt.c b/arch/risc-v/src/espressif/esp_wdt.c deleted file mode 100644 index 9688f943d6723..0000000000000 --- a/arch/risc-v/src/espressif/esp_wdt.c +++ /dev/null @@ -1,587 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/espressif/esp_wdt.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "esp_irq.h" -#include "esp_wdt.h" - -#include "hal/mwdt_ll.h" -#include "hal/wdt_hal.h" -#include "periph_ctrl.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* MWDT clock period in microseconds */ - -#define MWDT_CLK_PERIOD_US (500) - -/* Number of MWDT cycles per microseconds */ - -#define MWDT_CYCLES_PER_MS (USEC_PER_MSEC / MWDT_CLK_PERIOD_US) - -/* Convert MWDT timeout cycles to milliseconds */ - -#define MWDT_TIMEOUT_MS(t) ((t) * MWDT_CYCLES_PER_MS) - -/* Maximum number of MWDT cycles supported for timeout */ - -#define MWDT_MAX_TIMEOUT_MS (UINT32_MAX / MWDT_CYCLES_PER_MS) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* This structure provides the private representation of the "lower-half" - * driver state structure. This structure must be cast-compatible with the - * well-known watchdog_lowerhalf_s structure. - */ - -struct esp_wdt_lowerhalf_s -{ - const struct watchdog_ops_s *ops; /* Lower half operations */ - uint32_t timeout; /* The current timeout */ - wdt_stage_action_t action; /* The current action */ - uint32_t lastreset; /* The last reset time */ - bool started; /* True: Timer has been started */ - xcpt_t handler; /* User Handler */ - void *upper; /* Pointer to watchdog_upperhalf_s */ -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Interrupt handling *******************************************************/ - -static int wdt_handler(int irq, void *context, void *arg); - -/* "Lower half" driver methods **********************************************/ - -static int wdt_start(struct watchdog_lowerhalf_s *lower); -static int wdt_stop(struct watchdog_lowerhalf_s *lower); -static int wdt_keepalive(struct watchdog_lowerhalf_s *lower); -static int wdt_getstatus(struct watchdog_lowerhalf_s *lower, - struct watchdog_status_s *status); -static int wdt_settimeout(struct watchdog_lowerhalf_s *lower, - uint32_t timeout); -static xcpt_t wdt_capture(struct watchdog_lowerhalf_s *lower, - xcpt_t handler); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* "Lower half" driver methods */ - -static const struct watchdog_ops_s g_esp_wdg_ops = -{ - .start = wdt_start, - .stop = wdt_stop, - .keepalive = wdt_keepalive, - .getstatus = wdt_getstatus, - .settimeout = wdt_settimeout, - .capture = wdt_capture, - .ioctl = NULL -}; - -/* MWDT0 lower-half */ - -static struct esp_wdt_lowerhalf_s g_esp_wdt_lowerhalf = -{ - .ops = &g_esp_wdg_ops, - .timeout = MWDT_MAX_TIMEOUT_MS -}; - -/* Watchdog HAL context */ - -static wdt_hal_context_t wdt_hal_ctx; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: wdt_start - * - * Description: - * Start the watchdog timer, register a callback if there is one and - * enables interrupt, otherwise, configure it to reset system on - * expiration. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Values: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int wdt_start(struct watchdog_lowerhalf_s *lower) -{ - struct esp_wdt_lowerhalf_s *priv = (struct esp_wdt_lowerhalf_s *)lower; - int ret = OK; - irqstate_t flags; - - wdinfo("Entry: started\n"); - - DEBUGASSERT(priv != NULL); - - if (priv->started) - { - /* Return EBUSY to indicate that the timer was already running */ - - return -EBUSY; - } - - priv->started = true; - - wdt_hal_write_protect_disable(&wdt_hal_ctx); - - if (priv->handler == NULL) - { - /* No user handler, so configure WDT to reset on timeout */ - - priv->action = WDT_STAGE_ACTION_RESET_SYSTEM; - - wdt_hal_config_stage(&wdt_hal_ctx, WDT_STAGE0, - MWDT_TIMEOUT_MS(priv->timeout), - priv->action); - } - else - { - /* Configure WDT to call the user handler on timeout */ - - priv->action = WDT_STAGE_ACTION_INT; - - wdt_hal_config_stage(&wdt_hal_ctx, WDT_STAGE0, - MWDT_TIMEOUT_MS(priv->timeout), - priv->action); - - /* Enable interrupt */ - - mwdt_ll_set_intr_enable(wdt_hal_ctx.mwdt_dev, true); - } - - flags = enter_critical_section(); - priv->lastreset = clock_systime_ticks(); - wdt_hal_enable(&wdt_hal_ctx); - leave_critical_section(flags); - - wdt_hal_write_protect_enable(&wdt_hal_ctx); - - return ret; -} - -/**************************************************************************** - * Name: wdt_stop - * - * Description: - * Stop the watchdog timer. In case a callback was previously configured, - * unregister and deallocate it. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Values: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int wdt_stop(struct watchdog_lowerhalf_s *lower) -{ - struct esp_wdt_lowerhalf_s *priv = (struct esp_wdt_lowerhalf_s *)lower; - - wdt_hal_write_protect_disable(&wdt_hal_ctx); - - /* Disable the WDT */ - - wdt_hal_disable(&wdt_hal_ctx); - - /* In case there is a callback registered, ensure WDT interrupts are - * disabled. - */ - - if (priv->handler != NULL) - { - mwdt_ll_set_intr_enable(wdt_hal_ctx.mwdt_dev, false); - } - - wdt_hal_write_protect_enable(&wdt_hal_ctx); - - priv->started = false; - - return OK; -} - -/**************************************************************************** - * Name: wdt_keepalive - * - * Description: - * Reset the watchdog timer, prevent any - * imminent watchdog timeouts. This is sometimes referred as "pinging" - * the watchdog timer or "petting the dog". - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * - * Returned Values: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int wdt_keepalive(struct watchdog_lowerhalf_s *lower) -{ - struct esp_wdt_lowerhalf_s *priv = (struct esp_wdt_lowerhalf_s *)lower; - irqstate_t flags; - - wdt_hal_write_protect_disable(&wdt_hal_ctx); - - /* Feed the dog and update the time of last reset */ - - flags = enter_critical_section(); - priv->lastreset = clock_systime_ticks(); - wdt_hal_feed(&wdt_hal_ctx); - leave_critical_section(flags); - - wdt_hal_write_protect_enable(&wdt_hal_ctx); - - return OK; -} - -/**************************************************************************** - * Name: wdt_getstatus - * - * Description: - * Get the current watchdog timer status - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * status - The location to return the watchdog status information. - * - * Returned Values: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int wdt_getstatus(struct watchdog_lowerhalf_s *lower, - struct watchdog_status_s *status) -{ - struct esp_wdt_lowerhalf_s *priv = (struct esp_wdt_lowerhalf_s *)lower; - uint32_t ticks; - uint32_t elapsed; - - DEBUGASSERT(priv != NULL); - - status->flags = 0; - - /* If no handler was settled, then RESET on expiration. - * Otherwise, call the user handler. - */ - - if (priv->handler == NULL) - { - status->flags |= WDFLAGS_RESET; - } - else - { - status->flags |= WDFLAGS_CAPTURE; - } - - if (priv->started) - { - status->flags |= WDFLAGS_ACTIVE; - } - - /* Return the current timeout in milliseconds */ - - status->timeout = priv->timeout; - - /* Get the elapsed time since the last ping */ - - ticks = clock_systime_ticks() - priv->lastreset; - elapsed = (uint32_t)TICK2MSEC(ticks); - - if (elapsed < priv->timeout) - { - /* Return the approximate time until the watchdog timer expiration */ - - status->timeleft = priv->timeout - elapsed; - } - else - { - status->timeleft = 0; - } - - return OK; -} - -/**************************************************************************** - * Name: wdt_settimeout - * - * Description: - * Set a new timeout value (and reset the watchdog timer) - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * timeout - The new timeout value in milliseconds. - * - * Returned Values: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int wdt_settimeout(struct watchdog_lowerhalf_s *lower, - uint32_t timeout) -{ - struct esp_wdt_lowerhalf_s *priv = (struct esp_wdt_lowerhalf_s *)lower; - uint16_t rtc_cycles = 0; - uint32_t rtc_ms_max = 0; - - wdinfo("Entry: timeout=%" PRIu32 "\n", timeout); - - DEBUGASSERT(priv != NULL); - - wdt_hal_write_protect_disable(&wdt_hal_ctx); - - priv->timeout = timeout; - - if (timeout == 0 || timeout > MWDT_MAX_TIMEOUT_MS) - { - wderr("ERROR: Cannot represent timeout=%" PRIu32 " > %" PRIu32 "\n", - timeout, MWDT_MAX_TIMEOUT_MS); - return -ERANGE; - } - - wdt_hal_config_stage(&wdt_hal_ctx, WDT_STAGE0, - MWDT_TIMEOUT_MS(priv->timeout), - priv->action); - - wdt_hal_feed(&wdt_hal_ctx); - - wdt_hal_write_protect_enable(&wdt_hal_ctx); - - return OK; -} - -/**************************************************************************** - * Name: wdt_capture - * - * Description: - * Don't reset on watchdog timer timeout; instead, call this user provider - * timeout handler. NOTE: Providing handler==NULL will restore the reset - * behavior. - * - * Input Parameters: - * lower - A pointer the publicly visible representation of the - * "lower-half" driver state structure. - * handler - The new watchdog expiration function pointer. If this - * function pointer is NULL, then the reset-on-expiration - * behavior is restored. - * - * Returned Value: - * The previous watchdog expiration function pointer or NULL if there was - * no previous function pointer, i.e., if the previous behavior was - * reset-on-expiration (NULL is also returned if an error occurs). - * - ****************************************************************************/ - -static xcpt_t wdt_capture(struct watchdog_lowerhalf_s *lower, xcpt_t handler) -{ - struct esp_wdt_lowerhalf_s *priv = (struct esp_wdt_lowerhalf_s *)lower; - irqstate_t flags; - xcpt_t oldhandler; - - DEBUGASSERT(priv != NULL); - - wdinfo("Entry: handler=0x%" PRIxPTR "\n", (uintptr_t)handler); - - oldhandler = priv->handler; - - wdt_hal_write_protect_disable(&wdt_hal_ctx); - - flags = enter_critical_section(); - - /* Save the new user handler */ - - priv->handler = handler; - - /* There is a user callback and the timer has already been started. - * The user wants to set a callback after starting the WDT or wants to - * change the callback function once a callback has already been settled. - */ - - if (priv->handler != NULL && priv->started) - { - if (oldhandler == NULL) - { - /* If it was previous configured to reset on timeout - * then change to interrupt. - */ - - priv->action = WDT_STAGE_ACTION_INT; - - wdt_hal_config_stage(&wdt_hal_ctx, WDT_STAGE0, - MWDT_TIMEOUT_MS(priv->timeout), - priv->action); - } - - mwdt_ll_set_intr_enable(wdt_hal_ctx.mwdt_dev, true); - } - - /* In case the user wants to disable the callback */ - - else - { - mwdt_ll_set_intr_enable(wdt_hal_ctx.mwdt_dev, false); - - /* Then configure it to reset on WDT expiration */ - - priv->action = WDT_STAGE_ACTION_RESET_SYSTEM; - - wdt_hal_config_stage(&wdt_hal_ctx, WDT_STAGE0, - MWDT_TIMEOUT_MS(priv->timeout), - priv->action); - } - - leave_critical_section(flags); - - wdt_hal_write_protect_enable(&wdt_hal_ctx); - - return oldhandler; -} - -/**************************************************************************** - * Name: wdt_handler - * - * Description: - * This is the WDT interrupt handler. It will be invoked when an - * interrupt is received on the device. - * - * Input Parameters: - * irq - IRQ associated to that interrupt. - * context - Interrupt register state save info. - * arg - A pointer to the argument provided when the interrupt - * was registered. - * - * Returned Value: - * Zero on success; a negated errno value on failure. - * - ****************************************************************************/ - -static int wdt_handler(int irq, void *context, void *arg) -{ - struct esp_wdt_lowerhalf_s *priv = (struct esp_wdt_lowerhalf_s *)arg; - - /* Run the user callback */ - - priv->handler(irq, context, priv->upper); - - /* Clear the Interrupt */ - - wdt_hal_write_protect_disable(&wdt_hal_ctx); - wdt_hal_handle_intr(&wdt_hal_ctx); - wdt_hal_write_protect_enable(&wdt_hal_ctx); - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_wdt_initialize - * - * Description: - * Initialize the watchdog timer. - * - * Input Parameters: - * None. - * - * Returned Values: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure. - * - ****************************************************************************/ - -int esp_wdt_initialize(void) -{ - periph_module_enable(PERIPH_TIMG0_MODULE); - wdt_hal_init(&wdt_hal_ctx, WDT_MWDT0, MWDT_LL_DEFAULT_CLK_PRESCALER, true); - - struct esp_wdt_lowerhalf_s *lower = &g_esp_wdt_lowerhalf; - - /* Initialize the elements of lower half state structure */ - - lower->handler = NULL; - lower->timeout = 0; - lower->started = wdt_hal_is_enabled(&wdt_hal_ctx); - - /* Register the watchdog driver as /dev/watchdogX. If the registration goes - * right the returned value from watchdog_register is a pointer to - * watchdog_upperhalf_s that can be either used with watchdog_unregister() - * or with the handler's arg. - */ - - lower->upper = watchdog_register(CONFIG_WATCHDOG_DEVPATH, - (struct watchdog_lowerhalf_s *)lower); - if (lower->upper == NULL) - { - /* The actual cause of the failure may have been a failure to allocate - * perhaps a failure to register the watchdog driver (such as if the - * 'devpath' were not unique). We know here but we return EEXIST to - * indicate the failure (implying the non-unique devpath). - */ - - return -EEXIST; - } - - esp_setup_irq(TG0_WDT_LEVEL_INTR_SOURCE, - ESP_IRQ_PRIORITY_DEFAULT, - ESP_IRQ_TRIGGER_LEVEL); - - /* Attach the handler for the timer IRQ */ - - irq_attach(ESP_IRQ_TG0_WDT_LEVEL, (xcpt_t)wdt_handler, lower); - - /* Enable the allocated CPU interrupt */ - - up_enable_irq(ESP_IRQ_TG0_WDT_LEVEL); - - return OK; -} diff --git a/arch/risc-v/src/espressif/esp_wdt.h b/arch/risc-v/src/espressif/esp_wdt.h deleted file mode 100644 index d6910e06a8ed8..0000000000000 --- a/arch/risc-v/src/espressif/esp_wdt.h +++ /dev/null @@ -1,51 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/espressif/esp_wdt.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_RISCV_SRC_ESPRESSIF_ESP_WDT_H -#define __ARCH_RISCV_SRC_ESPRESSIF_ESP_WDT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_wdt_initialize - * - * Description: - * Initialize the watchdog timer. - * - * Input Parameters: - * None. - * - * Returned Values: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure. - * - ****************************************************************************/ - -int esp_wdt_initialize(void); - -#endif /* __ARCH_RISCV_SRC_ESPRESSIF_ESP_WDT_H */ diff --git a/arch/risc-v/src/espressif/hal_esp32c3.mk b/arch/risc-v/src/espressif/hal_esp32c3.mk deleted file mode 100644 index e0ac44ba84615..0000000000000 --- a/arch/risc-v/src/espressif/hal_esp32c3.mk +++ /dev/null @@ -1,104 +0,0 @@ -############################################################################ -# arch/risc-v/src/espressif/esp32c3.mk -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -# Include header paths - -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/nuttx/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/nuttx/$(CHIP_SERIES)/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/private_include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/private_include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_common/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/include/esp_private -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/include/soc -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES) -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/private_include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/include/$(CHIP_SERIES) -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES) -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/include/private -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/public_compat -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_timer/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/platform_port/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/log -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/log/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/riscv/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/include - -# Linker scripts - -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.ld -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.eco3.ld -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.api.ld -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.newlib.ld -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.version.ld -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/ld/$(CHIP_SERIES).peripherals.ld - -# Source files - -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/src/esp_efuse_api.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/src/esp_efuse_utility.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/esp_efuse_fields.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/esp_efuse_table.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/esp_efuse_utility.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/clk_ctrl_os.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/cpu.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/esp_clk.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/hw_random.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/periph_ctrl.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/regi2c_ctrl.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/esp_clk_tree_common.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/esp_clk_tree.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/cpu_region_protect.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_clk.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_init.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_sleep.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_time.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/sar_periph_ctrl.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/systimer.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/brownout.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/soc/$(CHIP_SERIES)/clk.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/soc/$(CHIP_SERIES)/system_internal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/brownout_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/efuse_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/gpio_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/ledc_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/ledc_hal_iram.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/systimer_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/timer_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/timer_hal_iram.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/uart_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/uart_hal_iram.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/wdt_hal_iram.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/clk_tree_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/efuse_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/log/log.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/log/log_noos.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/riscv/interrupt.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/gpio_periph.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/ledc_periph.c diff --git a/arch/risc-v/src/espressif/hal_esp32c6.mk b/arch/risc-v/src/espressif/hal_esp32c6.mk deleted file mode 100644 index 2267222968b76..0000000000000 --- a/arch/risc-v/src/espressif/hal_esp32c6.mk +++ /dev/null @@ -1,111 +0,0 @@ -############################################################################ -# arch/risc-v/src/espressif/esp32c6.mk -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -# Include header paths - -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/nuttx/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/nuttx/$(CHIP_SERIES)/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/private_include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/private_include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_common/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/include/esp_private -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/include/soc -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES) -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/private_include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/include/$(CHIP_SERIES) -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES) -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/include/private -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/public_compat -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_timer/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/platform_port/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/log -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/log/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/riscv/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/include - -# Linker scripts - -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.ld -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.api.ld -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.newlib.ld -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.spiflash.ld -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.version.ld -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.wdt.ld -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/ld/$(CHIP_SERIES).peripherals.ld - -# Source files - -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/src/esp_efuse_api.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/src/esp_efuse_utility.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/esp_efuse_fields.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/esp_efuse_table.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/esp_efuse_utility.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/clk_ctrl_os.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/cpu.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/esp_clk.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/hw_random.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/modem_clock.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/periph_ctrl.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/regi2c_ctrl.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/esp_clk_tree_common.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/esp_clk_tree.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/cpu_region_protect.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/ocode_init.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/pmu_init.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/pmu_param.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/pmu_sleep.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_clk.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_time.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/sar_periph_ctrl.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/systimer.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_regi2c_$(CHIP_SERIES).c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_systimer.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_wdt.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/brownout.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/soc/$(CHIP_SERIES)/clk.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/soc/$(CHIP_SERIES)/system_internal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/brownout_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/efuse_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/gpio_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/ledc_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/ledc_hal_iram.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/lp_timer_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/timer_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/timer_hal_iram.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/uart_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/uart_hal_iram.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/clk_tree_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/efuse_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/modem_clock_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/log/log.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/log/log_noos.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/riscv/interrupt.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/gpio_periph.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/ledc_periph.c diff --git a/arch/risc-v/src/espressif/hal_esp32h2.mk b/arch/risc-v/src/espressif/hal_esp32h2.mk deleted file mode 100644 index c96f37719b046..0000000000000 --- a/arch/risc-v/src/espressif/hal_esp32h2.mk +++ /dev/null @@ -1,110 +0,0 @@ -############################################################################ -# arch/risc-v/src/espressif/esp32h2.mk -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -# Include header paths - -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/nuttx/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/nuttx/$(CHIP_SERIES)/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/private_include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/private_include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_common/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/include/esp_private -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/include/soc -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES) -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/private_include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/include/$(CHIP_SERIES) -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES) -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/include/private -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/public_compat -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_timer/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/platform_port/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/log -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/log/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/riscv/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/include - -# Linker scripts - -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.ld -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.api.ld -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.newlib.ld -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.spiflash.ld -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.version.ld -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/$(CHIP_SERIES)/ld/$(CHIP_SERIES).rom.wdt.ld -ARCHSCRIPT += $(ARCH_SRCDIR)/chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/ld/$(CHIP_SERIES).peripherals.ld - -# Source files - -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/src/esp_efuse_api.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/src/esp_efuse_utility.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/esp_efuse_fields.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/esp_efuse_table.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/efuse/$(CHIP_SERIES)/esp_efuse_utility.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/clk_ctrl_os.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/cpu.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/esp_clk.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/hw_random.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/modem_clock.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/periph_ctrl.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/regi2c_ctrl.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/esp_clk_tree_common.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/esp_clk_tree.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/cpu_region_protect.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/pmu_init.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/pmu_param.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_clk.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/rtc_time.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/sar_periph_ctrl.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_hw_support/port/$(CHIP_SERIES)/systimer.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_regi2c_$(CHIP_SERIES).c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_systimer.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_rom/patches/esp_rom_wdt.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/brownout.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/soc/$(CHIP_SERIES)/clk.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/esp_system/port/soc/$(CHIP_SERIES)/system_internal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/brownout_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/cache_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/efuse_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/gpio_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/ledc_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/ledc_hal_iram.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/lp_timer_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/timer_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/timer_hal_iram.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/uart_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/uart_hal_iram.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/clk_tree_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/efuse_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/hal/$(CHIP_SERIES)/modem_clock_hal.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/log/log.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/log/log_noos.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/riscv/interrupt.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/gpio_periph.c -CHIP_CSRCS += chip/$(ESP_HAL_3RDPARTY_REPO)/components/soc/$(CHIP_SERIES)/ledc_periph.c diff --git a/arch/risc-v/src/fe310/fe310_head.S b/arch/risc-v/src/fe310/fe310_head.S index 7c307ac54aed0..8e91221ef0aac 100644 --- a/arch/risc-v/src/fe310/fe310_head.S +++ b/arch/risc-v/src/fe310/fe310_head.S @@ -48,12 +48,12 @@ __start: /* Disable all interrupts (i.e. timer, external) in mie */ - csrw mie, zero + csrw CSR_MIE, zero /* Initialize the Machine Trap Vector */ la t0, __trap_vec - csrw mtvec, t0 + csrw CSR_MTVEC, t0 /* Jump to __fe310_start */ diff --git a/arch/risc-v/src/fe310/fe310_irq.c b/arch/risc-v/src/fe310/fe310_irq.c index 1ab7ab4d22e19..f7244f9387ac4 100644 --- a/arch/risc-v/src/fe310/fe310_irq.c +++ b/arch/risc-v/src/fe310/fe310_irq.c @@ -104,7 +104,7 @@ void up_disable_irq(int irq) { /* Read mstatus & clear machine timer interrupt enable in mie */ - CLEAR_CSR(mie, MIE_MTIE); + CLEAR_CSR(CSR_MIE, MIE_MTIE); } else if (irq > RISCV_IRQ_MEXT) { @@ -140,7 +140,7 @@ void up_enable_irq(int irq) { /* Read mstatus & set machine timer interrupt enable in mie */ - SET_CSR(mie, MIE_MTIE); + SET_CSR(CSR_MIE, MIE_MTIE); } else if (irq > RISCV_IRQ_MEXT) { @@ -190,11 +190,11 @@ irqstate_t up_irq_enable(void) /* TODO: should move to up_enable_irq() */ - SET_CSR(mie, MIE_MEIE); + SET_CSR(CSR_MIE, MIE_MEIE); #endif /* Read mstatus & set machine interrupt enable (MIE) in mstatus */ - oldstat = READ_AND_SET_CSR(mstatus, MSTATUS_MIE); + oldstat = READ_AND_SET_CSR(CSR_MSTATUS, MSTATUS_MIE); return oldstat; } diff --git a/arch/risc-v/src/fe310/fe310_memorymap.h b/arch/risc-v/src/fe310/fe310_memorymap.h index f7495cf03d732..6bf30e63643ca 100644 --- a/arch/risc-v/src/fe310/fe310_memorymap.h +++ b/arch/risc-v/src/fe310/fe310_memorymap.h @@ -45,6 +45,6 @@ #define FE310_IDLESTACK_BASE _ebss #endif -#define FE310_IDLESTACK_TOP (FE310_IDLESTACK_BASE + CONFIG_IDLETHREAD_STACKSIZE) +#define FE310_IDLESTACK_TOP (FE310_IDLESTACK_BASE + SMP_STACK_SIZE) #endif /* __ARCH_RISCV_SRC_FE310_FE310_MEMORYMAP_H */ diff --git a/arch/risc-v/src/fe310/fe310_serial.c b/arch/risc-v/src/fe310/fe310_serial.c index 5e04afabefd34..9250ce3098d03 100644 --- a/arch/risc-v/src/fe310/fe310_serial.c +++ b/arch/risc-v/src/fe310/fe310_serial.c @@ -214,12 +214,12 @@ static void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) { - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(NULL); priv->im = im; up_serialout(priv, UART_IE_OFFSET, im); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -228,7 +228,7 @@ static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) { - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(NULL); /* Return the current interrupt mask value */ @@ -241,7 +241,7 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) priv->im = 0; up_serialout(priv, UART_IE_OFFSET, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/risc-v/src/fe310/fe310_start.c b/arch/risc-v/src/fe310/fe310_start.c index d22be0f97f713..885ea5b3d00d6 100644 --- a/arch/risc-v/src/fe310/fe310_start.c +++ b/arch/risc-v/src/fe310/fe310_start.c @@ -47,18 +47,6 @@ * Public Data ****************************************************************************/ -/* g_idle_topstack: _sbss is the start of the BSS region as defined by the - * linker script. _ebss lies at the end of the BSS region. The idle task - * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. - * The IDLE thread is the thread that the system boots on and, eventually, - * becomes the IDLE, do nothing task that runs only when there is nothing - * else to run. The heap continues from there until the end of memory. - * g_idle_topstack is a read-only variable the provides this computed - * address. - */ - -uintptr_t g_idle_topstack = FE310_IDLESTACK_TOP; - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/risc-v/src/hpm6000/CMakeLists.txt b/arch/risc-v/src/hpm6000/CMakeLists.txt new file mode 100644 index 0000000000000..849dfa2bb7932 --- /dev/null +++ b/arch/risc-v/src/hpm6000/CMakeLists.txt @@ -0,0 +1,36 @@ +# ############################################################################## +# arch/risc-v/src/hpm6000/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS hpm_head.S) + +list( + APPEND + SRCS + hpm_clockconfig.c + hpm_gpio.c + hpm_ioc.c + hpm_irq.c + hpm_irq_dispatch.c + hpm_lowputc.c + hpm_serial.c + hpm_start.c + hpm_timerisr.c) + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/risc-v/src/hpm6000/Kconfig b/arch/risc-v/src/hpm6000/Kconfig new file mode 100644 index 0000000000000..eb912fce4ce06 --- /dev/null +++ b/arch/risc-v/src/hpm6000/Kconfig @@ -0,0 +1,116 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "HPM6000 Configuration Options" + +choice + prompt "HPM6000 Chip Selection" + default ARCH_CHIP_HPM6360IPA + depends on ARCH_CHIP_HPM6000 + +config ARCH_CHIP_HPM6360IPA + bool "HPM6360IPA" + select ARCH_FAMILY_HPM6360 + +endchoice # HPM6000 Chip Selection + +# HPM6000 Families + +config ARCH_FAMILY_HPM6360 + bool + default n + select ARCH_FAMILY_HPM6300 + +# Peripheral support + +menu "HPM6000 Peripheral Selection" + +config HPM_ENET + bool "Ethernet" + default n + +menu "Watchdog" + +config HPM_WDOG0 + bool "WathDog" + default n + +config HPM_WDOG1 + bool "WathDog" + default n + +config HPM_WDOG2 + bool "WathDog" + default n + +endmenu # Watchdog + +menu "UART Peripherals" + +config HPM_UART0 + bool "UART0" + default n + select UART0_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select HPM_HAVE_UART + +config HPM_UART1 + bool "UART1" + default n + select UART1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select HPM_HAVE_UART + +config HPM_UART2 + bool "UART2" + default n + select UART2_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select HPM_HAVE_UART + +config HPM_UART3 + bool "UART3" + default n + select UART3_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select HPM_HAVE_UART + +config HPM_UART4 + bool "UART4" + default n + select UART4_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select HPM_HAVE_UART + +config HPM_UART5 + bool "UART5" + default n + select UART5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select HPM_HAVE_UART + +config HPM_UART6 + bool "UART6" + default n + select UART6_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select HPM_HAVE_UART + +config HPM_UART7 + bool "UART7" + default n + select UART7_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select HPM_HAVE_UART + +config HPM_PUART + bool "PUART" + default n + select PUART_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + select HPM_HAVE_UART + +endmenu # UART Peripherals +endmenu # HPM6000 Peripheral Selection diff --git a/arch/risc-v/src/hpm6000/Make.defs b/arch/risc-v/src/hpm6000/Make.defs new file mode 100644 index 0000000000000..e2ae1024f8ac1 --- /dev/null +++ b/arch/risc-v/src/hpm6000/Make.defs @@ -0,0 +1,32 @@ +############################################################################ +# arch/risc-v/src/hpm6000/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include common/Make.defs + +# Specify our HEAD assembly file. This will be linked as +# the first object file, so it will appear at address 0 +HEAD_ASRC = hpm_head.S + +# Specify our C code within this directory to be included +CHIP_CSRCS = hpm_clockconfig.c +CHIP_CSRCS += hpm_irq.c hpm_irq_dispatch.c +CHIP_CSRCS += hpm_lowputc.c hpm_serial.c +CHIP_CSRCS += hpm_start.c hpm_timerisr.c +CHIP_CSRCS += hpm_ioc.c hpm_gpio.c diff --git a/arch/risc-v/src/hpm6000/chip.h b/arch/risc-v/src/hpm6000/chip.h new file mode 100644 index 0000000000000..8ed81c4eea226 --- /dev/null +++ b/arch/risc-v/src/hpm6000/chip.h @@ -0,0 +1,32 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_CHIP_H +#define __ARCH_RISCV_SRC_HPM6000_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "hpm_memorymap.h" + +#endif /* __ARCH_RISCV_SRC_HPM6000_CHIP_H */ diff --git a/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_gpio.h b/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_gpio.h new file mode 100644 index 0000000000000..9aade3e58e375 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_gpio.h @@ -0,0 +1,489 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_GPIO_H +#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/hpm_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define HPM_GPIOA_OFFSET 0x0000 /* GPIOA Register Offset */ +#define HPM_GPIOB_OFFSET 0x0010 /* GPIOB Register Offset */ +#define HPM_GPIOC_OFFSET 0x0020 /* GPIOC Register Offset */ +#define HPM_GPIOX_OFFSET 0x00d0 /* GPIOX Register Offset */ +#define HPM_GPIOY_OFFSET 0x00e0 /* GPIOY Register Offset */ +#define HPM_GPIOZ_OFFSET 0x00f0 /* GPIOZ Register Offset */ + +#define HPM_GPIO_VAL_OFFSET 0x0000 /* GPIO Value Register Offset */ +#define HPM_GPIO_SET_OFFSET 0x0004 /* GPIO Set Register Offset */ +#define HPM_GPIO_CLR_OFFSET 0x0008 /* GPIO Clear Register Offset */ +#define HPM_GPIO_TGL_OFFSET 0x000c /* GPIO Toggle Register Offset */ + +#define HPM_GPIO_DI_OFFSET 0x0000 /* GPIO Data Input Register Offset */ +#define HPM_GPIO_DO_OFFSET 0x0100 /* GPIO Data Output Register Offset */ +#define HPM_GPIO_OE_OFFSET 0x0200 /* GPIO Output Enable Register Offset */ +#define HPM_GPIO_IF_OFFSET 0x0300 /* GPIO Interrupt Flag Register Offset */ +#define HPM_GPIO_IE_OFFSET 0x0400 /* GPIO Interrupt Enable Register Offset */ +#define HPM_GPIO_PL_OFFSET 0x0500 /* GPIO Interrupt Edge Register Offset */ +#define HPM_GPIO_TP_OFFSET 0x0600 /* GPIO Interrupt Type Offset */ +#define HPM_GPIO_AS_OFFSET 0x0700 /* GPIO Async Interrupt Offset */ + +#define HPM_GPIO_DI_VAL_OFFSET (HPM_GPIO_DI_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIO_DI_SET_OFFSET (HPM_GPIO_DI_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIO_DI_CLR_OFFSET (HPM_GPIO_DI_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIO_DI_TGL_OFFSET (HPM_GPIO_DI_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIO_DO_VAL_OFFSET (HPM_GPIO_DO_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIO_DO_SET_OFFSET (HPM_GPIO_DO_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIO_DO_CLR_OFFSET (HPM_GPIO_DO_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIO_DO_TGL_OFFSET (HPM_GPIO_DO_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIO_OE_VAL_OFFSET (HPM_GPIO_OE_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIO_OE_SET_OFFSET (HPM_GPIO_OE_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIO_OE_CLR_OFFSET (HPM_GPIO_OE_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIO_OE_TGL_OFFSET (HPM_GPIO_OE_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIO_IF_VAL_OFFSET (HPM_GPIO_IF_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIO_IF_SET_OFFSET (HPM_GPIO_IF_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIO_IF_CLR_OFFSET (HPM_GPIO_IF_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIO_IF_TGL_OFFSET (HPM_GPIO_IF_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIO_IE_VAL_OFFSET (HPM_GPIO_IE_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIO_IE_SET_OFFSET (HPM_GPIO_IE_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIO_IE_CLR_OFFSET (HPM_GPIO_IE_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIO_IE_TGL_OFFSET (HPM_GPIO_IE_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIO_PL_VAL_OFFSET (HPM_GPIO_PL_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIO_PL_SET_OFFSET (HPM_GPIO_PL_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIO_PL_CLR_OFFSET (HPM_GPIO_PL_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIO_PL_TGL_OFFSET (HPM_GPIO_PL_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIO_TP_VAL_OFFSET (HPM_GPIO_TP_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIO_TP_SET_OFFSET (HPM_GPIO_TP_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIO_TP_CLR_OFFSET (HPM_GPIO_TP_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIO_TP_TGL_OFFSET (HPM_GPIO_TP_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIO_AS_VAL_OFFSET (HPM_GPIO_AS_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIO_AS_SET_OFFSET (HPM_GPIO_AS_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIO_AS_CLR_OFFSET (HPM_GPIO_AS_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIO_AS_TGL_OFFSET (HPM_GPIO_AS_OFFSET + HPM_GPIO_TGL_OFFSET) + +#define HPM_GPIOA_DI_VAL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOA_DI_SET_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOA_DI_CLR_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOA_DI_TGL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOA_DO_VAL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOA_DO_SET_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOA_DO_CLR_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOA_DO_TGL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOA_OE_VAL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOA_OE_SET_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOA_OE_CLR_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOA_OE_TGL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOA_IF_VAL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOA_IF_SET_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOA_IF_CLR_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOA_IF_TGL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOA_IE_VAL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOA_IE_SET_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOA_IE_CLR_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOA_IE_TGL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOA_PL_VAL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOA_PL_SET_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOA_PL_CLR_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOA_PL_TGL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOA_TP_VAL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOA_TP_SET_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOA_TP_CLR_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOA_TP_TGL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOA_AS_VAL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOA_AS_SET_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOA_AS_CLR_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOA_AS_TGL_OFFSET (HPM_GPIOA_OFFSET + HPM_GPIO_TGL_OFFSET) + +#define HPM_GPIOB_DI_VAL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOB_DI_SET_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOB_DI_CLR_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOB_DI_TGL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOB_DO_VAL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOB_DO_SET_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOB_DO_CLR_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOB_DO_TGL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOB_OE_VAL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOB_OE_SET_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOB_OE_CLR_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOB_OE_TGL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOB_IF_VAL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOB_IF_SET_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOB_IF_CLR_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOB_IF_TGL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOB_IE_VAL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOB_IE_SET_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOB_IE_CLR_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOB_IE_TGL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOB_PL_VAL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOB_PL_SET_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOB_PL_CLR_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOB_PL_TGL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOB_TP_VAL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOB_TP_SET_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOB_TP_CLR_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOB_TP_TGL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOB_AS_VAL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOB_AS_SET_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOB_AS_CLR_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOB_AS_TGL_OFFSET (HPM_GPIOB_OFFSET + HPM_GPIO_TGL_OFFSET) + +#define HPM_GPIOC_DI_VAL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOC_DI_SET_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOC_DI_CLR_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOC_DI_TGL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOC_DO_VAL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOC_DO_SET_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOC_DO_CLR_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOC_DO_TGL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOC_OE_VAL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOC_OE_SET_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOC_OE_CLR_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOC_OE_TGL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOC_IF_VAL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOC_IF_SET_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOC_IF_CLR_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOC_IF_TGL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOC_IE_VAL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOC_IE_SET_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOC_IE_CLR_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOC_IE_TGL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOC_PL_VAL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOC_PL_SET_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOC_PL_CLR_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOC_PL_TGL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOC_TP_VAL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOC_TP_SET_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOC_TP_CLR_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOC_TP_TGL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOC_AS_VAL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOC_AS_SET_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOC_AS_CLR_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOC_AS_TGL_OFFSET (HPM_GPIOC_OFFSET + HPM_GPIO_TGL_OFFSET) + +#define HPM_GPIOX_DI_VAL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOX_DI_SET_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOX_DI_CLR_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOX_DI_TGL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOX_DO_VAL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOX_DO_SET_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOX_DO_CLR_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOX_DO_TGL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOX_OE_VAL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOX_OE_SET_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOX_OE_CLR_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOX_OE_TGL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOX_IF_VAL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOX_IF_SET_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOX_IF_CLR_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOX_IF_TGL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOX_IE_VAL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOX_IE_SET_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOX_IE_CLR_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOX_IE_TGL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOX_PL_VAL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOX_PL_SET_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOX_PL_CLR_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOX_PL_TGL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOX_TP_VAL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOX_TP_SET_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOX_TP_CLR_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOX_TP_TGL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOX_AS_VAL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOX_AS_SET_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOX_AS_CLR_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOX_AS_TGL_OFFSET (HPM_GPIOX_OFFSET + HPM_GPIO_TGL_OFFSET) + +#define HPM_GPIOY_DI_VAL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOY_DI_SET_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOY_DI_CLR_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOY_DI_TGL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOY_DO_VAL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOY_DO_SET_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOY_DO_CLR_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOY_DO_TGL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOY_OE_VAL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOY_OE_SET_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOY_OE_CLR_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOY_OE_TGL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOY_IF_VAL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOY_IF_SET_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOY_IF_CLR_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOY_IF_TGL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOY_IE_VAL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOY_IE_SET_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOY_IE_CLR_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOY_IE_TGL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOY_PL_VAL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOY_PL_SET_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOY_PL_CLR_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOY_PL_TGL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOY_TP_VAL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOY_TP_SET_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOY_TP_CLR_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOY_TP_TGL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOY_AS_VAL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOY_AS_SET_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOY_AS_CLR_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOY_AS_TGL_OFFSET (HPM_GPIOY_OFFSET + HPM_GPIO_TGL_OFFSET) + +#define HPM_GPIOZ_DI_VAL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOZ_DI_SET_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOZ_DI_CLR_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOZ_DI_TGL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOZ_DO_VAL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOZ_DO_SET_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOZ_DO_CLR_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOZ_DO_TGL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOZ_OE_VAL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOZ_OE_SET_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOZ_OE_CLR_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOZ_OE_TGL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOZ_IF_VAL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOZ_IF_SET_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOZ_IF_CLR_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOZ_IF_TGL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOZ_IE_VAL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOZ_IE_SET_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOZ_IE_CLR_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOZ_IE_TGL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOZ_PL_VAL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOZ_PL_SET_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOZ_PL_CLR_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOZ_PL_TGL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOZ_TP_VAL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOZ_TP_SET_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOZ_TP_CLR_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOZ_TP_TGL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_TGL_OFFSET) +#define HPM_GPIOZ_AS_VAL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_VAL_OFFSET) +#define HPM_GPIOZ_AS_SET_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_SET_OFFSET) +#define HPM_GPIOZ_AS_CLR_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_CLR_OFFSET) +#define HPM_GPIOZ_AS_TGL_OFFSET (HPM_GPIOZ_OFFSET + HPM_GPIO_TGL_OFFSET) + +/* Register addresses *******************************************************/ + +#define HPM_GPIOA_DI_VAL (HPM_GPIO0_BASE + HPM_GPIOA_DI_VAL_OFFSET) +#define HPM_GPIOA_DI_SET (HPM_GPIO0_BASE + HPM_GPIOA_DI_SET_OFFSET) +#define HPM_GPIOA_DI_CLR (HPM_GPIO0_BASE + HPM_GPIOA_DI_CLR_OFFSET) +#define HPM_GPIOA_DI_TGL (HPM_GPIO0_BASE + HPM_GPIOA_DI_TGL_OFFSET) +#define HPM_GPIOA_DO_VAL (HPM_GPIO0_BASE + HPM_GPIOA_DO_VAL_OFFSET) +#define HPM_GPIOA_DO_SET (HPM_GPIO0_BASE + HPM_GPIOA_DO_SET_OFFSET) +#define HPM_GPIOA_DO_CLR (HPM_GPIO0_BASE + HPM_GPIOA_DO_CLR_OFFSET) +#define HPM_GPIOA_DO_TGL (HPM_GPIO0_BASE + HPM_GPIOA_DO_TGL_OFFSET) +#define HPM_GPIOA_OE_VAL (HPM_GPIO0_BASE + HPM_GPIOA_OE_VAL_OFFSET) +#define HPM_GPIOA_OE_SET (HPM_GPIO0_BASE + HPM_GPIOA_OE_SET_OFFSET) +#define HPM_GPIOA_OE_CLR (HPM_GPIO0_BASE + HPM_GPIOA_OE_CLR_OFFSET) +#define HPM_GPIOA_OE_TGL (HPM_GPIO0_BASE + HPM_GPIOA_OE_TGL_OFFSET) +#define HPM_GPIOA_IF_VAL (HPM_GPIO0_BASE + HPM_GPIOA_IF_VAL_OFFSET) +#define HPM_GPIOA_IF_SET (HPM_GPIO0_BASE + HPM_GPIOA_IF_SET_OFFSET) +#define HPM_GPIOA_IF_CLR (HPM_GPIO0_BASE + HPM_GPIOA_IF_CLR_OFFSET) +#define HPM_GPIOA_IF_TGL (HPM_GPIO0_BASE + HPM_GPIOA_IF_TGL_OFFSET) +#define HPM_GPIOA_IE_VAL (HPM_GPIO0_BASE + HPM_GPIOA_IE_VAL_OFFSET) +#define HPM_GPIOA_IE_SET (HPM_GPIO0_BASE + HPM_GPIOA_IE_SET_OFFSET) +#define HPM_GPIOA_IE_CLR (HPM_GPIO0_BASE + HPM_GPIOA_IE_CLR_OFFSET) +#define HPM_GPIOA_IE_TGL (HPM_GPIO0_BASE + HPM_GPIOA_IE_TGL_OFFSET) +#define HPM_GPIOA_PL_VAL (HPM_GPIO0_BASE + HPM_GPIOA_PL_VAL_OFFSET) +#define HPM_GPIOA_PL_SET (HPM_GPIO0_BASE + HPM_GPIOA_PL_SET_OFFSET) +#define HPM_GPIOA_PL_CLR (HPM_GPIO0_BASE + HPM_GPIOA_PL_CLR_OFFSET) +#define HPM_GPIOA_PL_TGL (HPM_GPIO0_BASE + HPM_GPIOA_PL_TGL_OFFSET) +#define HPM_GPIOA_TP_VAL (HPM_GPIO0_BASE + HPM_GPIOA_TP_VAL_OFFSET) +#define HPM_GPIOA_TP_SET (HPM_GPIO0_BASE + HPM_GPIOA_TP_SET_OFFSET) +#define HPM_GPIOA_TP_CLR (HPM_GPIO0_BASE + HPM_GPIOA_TP_CLR_OFFSET) +#define HPM_GPIOA_TP_TGL (HPM_GPIO0_BASE + HPM_GPIOA_TP_TGL_OFFSET) +#define HPM_GPIOA_AS_VAL (HPM_GPIO0_BASE + HPM_GPIOA_AS_VAL_OFFSET) +#define HPM_GPIOA_AS_SET (HPM_GPIO0_BASE + HPM_GPIOA_AS_SET_OFFSET) +#define HPM_GPIOA_AS_CLR (HPM_GPIO0_BASE + HPM_GPIOA_AS_CLR_OFFSET) +#define HPM_GPIOA_AS_TGL (HPM_GPIO0_BASE + HPM_GPIOA_AS_TGL_OFFSET) + +#define HPM_GPIOB_DI_VAL (HPM_GPIO0_BASE + HPM_GPIOB_DI_VAL_OFFSET) +#define HPM_GPIOB_DI_SET (HPM_GPIO0_BASE + HPM_GPIOB_DI_SET_OFFSET) +#define HPM_GPIOB_DI_CLR (HPM_GPIO0_BASE + HPM_GPIOB_DI_CLR_OFFSET) +#define HPM_GPIOB_DI_TGL (HPM_GPIO0_BASE + HPM_GPIOB_DI_TGL_OFFSET) +#define HPM_GPIOB_DO_VAL (HPM_GPIO0_BASE + HPM_GPIOB_DO_VAL_OFFSET) +#define HPM_GPIOB_DO_SET (HPM_GPIO0_BASE + HPM_GPIOB_DO_SET_OFFSET) +#define HPM_GPIOB_DO_CLR (HPM_GPIO0_BASE + HPM_GPIOB_DO_CLR_OFFSET) +#define HPM_GPIOB_DO_TGL (HPM_GPIO0_BASE + HPM_GPIOB_DO_TGL_OFFSET) +#define HPM_GPIOB_OE_VAL (HPM_GPIO0_BASE + HPM_GPIOB_OE_VAL_OFFSET) +#define HPM_GPIOB_OE_SET (HPM_GPIO0_BASE + HPM_GPIOB_OE_SET_OFFSET) +#define HPM_GPIOB_OE_CLR (HPM_GPIO0_BASE + HPM_GPIOB_OE_CLR_OFFSET) +#define HPM_GPIOB_OE_TGL (HPM_GPIO0_BASE + HPM_GPIOB_OE_TGL_OFFSET) +#define HPM_GPIOB_IF_VAL (HPM_GPIO0_BASE + HPM_GPIOB_IF_VAL_OFFSET) +#define HPM_GPIOB_IF_SET (HPM_GPIO0_BASE + HPM_GPIOB_IF_SET_OFFSET) +#define HPM_GPIOB_IF_CLR (HPM_GPIO0_BASE + HPM_GPIOB_IF_CLR_OFFSET) +#define HPM_GPIOB_IF_TGL (HPM_GPIO0_BASE + HPM_GPIOB_IF_TGL_OFFSET) +#define HPM_GPIOB_IE_VAL (HPM_GPIO0_BASE + HPM_GPIOB_IE_VAL_OFFSET) +#define HPM_GPIOB_IE_SET (HPM_GPIO0_BASE + HPM_GPIOB_IE_SET_OFFSET) +#define HPM_GPIOB_IE_CLR (HPM_GPIO0_BASE + HPM_GPIOB_IE_CLR_OFFSET) +#define HPM_GPIOB_IE_TGL (HPM_GPIO0_BASE + HPM_GPIOB_IE_TGL_OFFSET) +#define HPM_GPIOB_PL_VAL (HPM_GPIO0_BASE + HPM_GPIOB_PL_VAL_OFFSET) +#define HPM_GPIOB_PL_SET (HPM_GPIO0_BASE + HPM_GPIOB_PL_SET_OFFSET) +#define HPM_GPIOB_PL_CLR (HPM_GPIO0_BASE + HPM_GPIOB_PL_CLR_OFFSET) +#define HPM_GPIOB_PL_TGL (HPM_GPIO0_BASE + HPM_GPIOB_PL_TGL_OFFSET) +#define HPM_GPIOB_TP_VAL (HPM_GPIO0_BASE + HPM_GPIOB_TP_VAL_OFFSET) +#define HPM_GPIOB_TP_SET (HPM_GPIO0_BASE + HPM_GPIOB_TP_SET_OFFSET) +#define HPM_GPIOB_TP_CLR (HPM_GPIO0_BASE + HPM_GPIOB_TP_CLR_OFFSET) +#define HPM_GPIOB_TP_TGL (HPM_GPIO0_BASE + HPM_GPIOB_TP_TGL_OFFSET) +#define HPM_GPIOB_AS_VAL (HPM_GPIO0_BASE + HPM_GPIOB_AS_VAL_OFFSET) +#define HPM_GPIOB_AS_SET (HPM_GPIO0_BASE + HPM_GPIOB_AS_SET_OFFSET) +#define HPM_GPIOB_AS_CLR (HPM_GPIO0_BASE + HPM_GPIOB_AS_CLR_OFFSET) +#define HPM_GPIOB_AS_TGL (HPM_GPIO0_BASE + HPM_GPIOB_AS_TGL_OFFSET) + +#define HPM_GPIOC_DI_VAL (HPM_GPIO0_BASE + HPM_GPIOC_DI_VAL_OFFSET) +#define HPM_GPIOC_DI_SET (HPM_GPIO0_BASE + HPM_GPIOC_DI_SET_OFFSET) +#define HPM_GPIOC_DI_CLR (HPM_GPIO0_BASE + HPM_GPIOC_DI_CLR_OFFSET) +#define HPM_GPIOC_DI_TGL (HPM_GPIO0_BASE + HPM_GPIOC_DI_TGL_OFFSET) +#define HPM_GPIOC_DO_VAL (HPM_GPIO0_BASE + HPM_GPIOC_DO_VAL_OFFSET) +#define HPM_GPIOC_DO_SET (HPM_GPIO0_BASE + HPM_GPIOC_DO_SET_OFFSET) +#define HPM_GPIOC_DO_CLR (HPM_GPIO0_BASE + HPM_GPIOC_DO_CLR_OFFSET) +#define HPM_GPIOC_DO_TGL (HPM_GPIO0_BASE + HPM_GPIOC_DO_TGL_OFFSET) +#define HPM_GPIOC_OE_VAL (HPM_GPIO0_BASE + HPM_GPIOC_OE_VAL_OFFSET) +#define HPM_GPIOC_OE_SET (HPM_GPIO0_BASE + HPM_GPIOC_OE_SET_OFFSET) +#define HPM_GPIOC_OE_CLR (HPM_GPIO0_BASE + HPM_GPIOC_OE_CLR_OFFSET) +#define HPM_GPIOC_OE_TGL (HPM_GPIO0_BASE + HPM_GPIOC_OE_TGL_OFFSET) +#define HPM_GPIOC_IF_VAL (HPM_GPIO0_BASE + HPM_GPIOC_IF_VAL_OFFSET) +#define HPM_GPIOC_IF_SET (HPM_GPIO0_BASE + HPM_GPIOC_IF_SET_OFFSET) +#define HPM_GPIOC_IF_CLR (HPM_GPIO0_BASE + HPM_GPIOC_IF_CLR_OFFSET) +#define HPM_GPIOC_IF_TGL (HPM_GPIO0_BASE + HPM_GPIOC_IF_TGL_OFFSET) +#define HPM_GPIOC_IE_VAL (HPM_GPIO0_BASE + HPM_GPIOC_IE_VAL_OFFSET) +#define HPM_GPIOC_IE_SET (HPM_GPIO0_BASE + HPM_GPIOC_IE_SET_OFFSET) +#define HPM_GPIOC_IE_CLR (HPM_GPIO0_BASE + HPM_GPIOC_IE_CLR_OFFSET) +#define HPM_GPIOC_IE_TGL (HPM_GPIO0_BASE + HPM_GPIOC_IE_TGL_OFFSET) +#define HPM_GPIOC_PL_VAL (HPM_GPIO0_BASE + HPM_GPIOC_PL_VAL_OFFSET) +#define HPM_GPIOC_PL_SET (HPM_GPIO0_BASE + HPM_GPIOC_PL_SET_OFFSET) +#define HPM_GPIOC_PL_CLR (HPM_GPIO0_BASE + HPM_GPIOC_PL_CLR_OFFSET) +#define HPM_GPIOC_PL_TGL (HPM_GPIO0_BASE + HPM_GPIOC_PL_TGL_OFFSET) +#define HPM_GPIOC_TP_VAL (HPM_GPIO0_BASE + HPM_GPIOC_TP_VAL_OFFSET) +#define HPM_GPIOC_TP_SET (HPM_GPIO0_BASE + HPM_GPIOC_TP_SET_OFFSET) +#define HPM_GPIOC_TP_CLR (HPM_GPIO0_BASE + HPM_GPIOC_TP_CLR_OFFSET) +#define HPM_GPIOC_TP_TGL (HPM_GPIO0_BASE + HPM_GPIOC_TP_TGL_OFFSET) +#define HPM_GPIOC_AS_VAL (HPM_GPIO0_BASE + HPM_GPIOC_AS_VAL_OFFSET) +#define HPM_GPIOC_AS_SET (HPM_GPIO0_BASE + HPM_GPIOC_AS_SET_OFFSET) +#define HPM_GPIOC_AS_CLR (HPM_GPIO0_BASE + HPM_GPIOC_AS_CLR_OFFSET) +#define HPM_GPIOC_AS_TGL (HPM_GPIO0_BASE + HPM_GPIOC_AS_TGL_OFFSET) + +#define HPM_GPIOX_DI_VAL (HPM_GPIO0_BASE + HPM_GPIOX_DI_VAL_OFFSET) +#define HPM_GPIOX_DI_SET (HPM_GPIO0_BASE + HPM_GPIOX_DI_SET_OFFSET) +#define HPM_GPIOX_DI_CLR (HPM_GPIO0_BASE + HPM_GPIOX_DI_CLR_OFFSET) +#define HPM_GPIOX_DI_TGL (HPM_GPIO0_BASE + HPM_GPIOX_DI_TGL_OFFSET) +#define HPM_GPIOX_DO_VAL (HPM_GPIO0_BASE + HPM_GPIOX_DO_VAL_OFFSET) +#define HPM_GPIOX_DO_SET (HPM_GPIO0_BASE + HPM_GPIOX_DO_SET_OFFSET) +#define HPM_GPIOX_DO_CLR (HPM_GPIO0_BASE + HPM_GPIOX_DO_CLR_OFFSET) +#define HPM_GPIOX_DO_TGL (HPM_GPIO0_BASE + HPM_GPIOX_DO_TGL_OFFSET) +#define HPM_GPIOX_OE_VAL (HPM_GPIO0_BASE + HPM_GPIOX_OE_VAL_OFFSET) +#define HPM_GPIOX_OE_SET (HPM_GPIO0_BASE + HPM_GPIOX_OE_SET_OFFSET) +#define HPM_GPIOX_OE_CLR (HPM_GPIO0_BASE + HPM_GPIOX_OE_CLR_OFFSET) +#define HPM_GPIOX_OE_TGL (HPM_GPIO0_BASE + HPM_GPIOX_OE_TGL_OFFSET) +#define HPM_GPIOX_IF_VAL (HPM_GPIO0_BASE + HPM_GPIOX_IF_VAL_OFFSET) +#define HPM_GPIOX_IF_SET (HPM_GPIO0_BASE + HPM_GPIOX_IF_SET_OFFSET) +#define HPM_GPIOX_IF_CLR (HPM_GPIO0_BASE + HPM_GPIOX_IF_CLR_OFFSET) +#define HPM_GPIOX_IF_TGL (HPM_GPIO0_BASE + HPM_GPIOX_IF_TGL_OFFSET) +#define HPM_GPIOX_IE_VAL (HPM_GPIO0_BASE + HPM_GPIOX_IE_VAL_OFFSET) +#define HPM_GPIOX_IE_SET (HPM_GPIO0_BASE + HPM_GPIOX_IE_SET_OFFSET) +#define HPM_GPIOX_IE_CLR (HPM_GPIO0_BASE + HPM_GPIOX_IE_CLR_OFFSET) +#define HPM_GPIOX_IE_TGL (HPM_GPIO0_BASE + HPM_GPIOX_IE_TGL_OFFSET) +#define HPM_GPIOX_PL_VAL (HPM_GPIO0_BASE + HPM_GPIOX_PL_VAL_OFFSET) +#define HPM_GPIOX_PL_SET (HPM_GPIO0_BASE + HPM_GPIOX_PL_SET_OFFSET) +#define HPM_GPIOX_PL_CLR (HPM_GPIO0_BASE + HPM_GPIOX_PL_CLR_OFFSET) +#define HPM_GPIOX_PL_TGL (HPM_GPIO0_BASE + HPM_GPIOX_PL_TGL_OFFSET) +#define HPM_GPIOX_TP_VAL (HPM_GPIO0_BASE + HPM_GPIOX_TP_VAL_OFFSET) +#define HPM_GPIOX_TP_SET (HPM_GPIO0_BASE + HPM_GPIOX_TP_SET_OFFSET) +#define HPM_GPIOX_TP_CLR (HPM_GPIO0_BASE + HPM_GPIOX_TP_CLR_OFFSET) +#define HPM_GPIOX_TP_TGL (HPM_GPIO0_BASE + HPM_GPIOX_TP_TGL_OFFSET) +#define HPM_GPIOX_AS_VAL (HPM_GPIO0_BASE + HPM_GPIOX_AS_VAL_OFFSET) +#define HPM_GPIOX_AS_SET (HPM_GPIO0_BASE + HPM_GPIOX_AS_SET_OFFSET) +#define HPM_GPIOX_AS_CLR (HPM_GPIO0_BASE + HPM_GPIOX_AS_CLR_OFFSET) +#define HPM_GPIOX_AS_TGL (HPM_GPIO0_BASE + HPM_GPIOX_AS_TGL_OFFSET) + +#define HPM_GPIOY_DI_VAL (HPM_GPIO0_BASE + HPM_GPIOY_DI_VAL_OFFSET) +#define HPM_GPIOY_DI_SET (HPM_GPIO0_BASE + HPM_GPIOY_DI_SET_OFFSET) +#define HPM_GPIOY_DI_CLR (HPM_GPIO0_BASE + HPM_GPIOY_DI_CLR_OFFSET) +#define HPM_GPIOY_DI_TGL (HPM_GPIO0_BASE + HPM_GPIOY_DI_TGL_OFFSET) +#define HPM_GPIOY_DO_VAL (HPM_GPIO0_BASE + HPM_GPIOY_DO_VAL_OFFSET) +#define HPM_GPIOY_DO_SET (HPM_GPIO0_BASE + HPM_GPIOY_DO_SET_OFFSET) +#define HPM_GPIOY_DO_CLR (HPM_GPIO0_BASE + HPM_GPIOY_DO_CLR_OFFSET) +#define HPM_GPIOY_DO_TGL (HPM_GPIO0_BASE + HPM_GPIOY_DO_TGL_OFFSET) +#define HPM_GPIOY_OE_VAL (HPM_GPIO0_BASE + HPM_GPIOY_OE_VAL_OFFSET) +#define HPM_GPIOY_OE_SET (HPM_GPIO0_BASE + HPM_GPIOY_OE_SET_OFFSET) +#define HPM_GPIOY_OE_CLR (HPM_GPIO0_BASE + HPM_GPIOY_OE_CLR_OFFSET) +#define HPM_GPIOY_OE_TGL (HPM_GPIO0_BASE + HPM_GPIOY_OE_TGL_OFFSET) +#define HPM_GPIOY_IF_VAL (HPM_GPIO0_BASE + HPM_GPIOY_IF_VAL_OFFSET) +#define HPM_GPIOY_IF_SET (HPM_GPIO0_BASE + HPM_GPIOY_IF_SET_OFFSET) +#define HPM_GPIOY_IF_CLR (HPM_GPIO0_BASE + HPM_GPIOY_IF_CLR_OFFSET) +#define HPM_GPIOY_IF_TGL (HPM_GPIO0_BASE + HPM_GPIOY_IF_TGL_OFFSET) +#define HPM_GPIOY_IE_VAL (HPM_GPIO0_BASE + HPM_GPIOY_IE_VAL_OFFSET) +#define HPM_GPIOY_IE_SET (HPM_GPIO0_BASE + HPM_GPIOY_IE_SET_OFFSET) +#define HPM_GPIOY_IE_CLR (HPM_GPIO0_BASE + HPM_GPIOY_IE_CLR_OFFSET) +#define HPM_GPIOY_IE_TGL (HPM_GPIO0_BASE + HPM_GPIOY_IE_TGL_OFFSET) +#define HPM_GPIOY_PL_VAL (HPM_GPIO0_BASE + HPM_GPIOY_PL_VAL_OFFSET) +#define HPM_GPIOY_PL_SET (HPM_GPIO0_BASE + HPM_GPIOY_PL_SET_OFFSET) +#define HPM_GPIOY_PL_CLR (HPM_GPIO0_BASE + HPM_GPIOY_PL_CLR_OFFSET) +#define HPM_GPIOY_PL_TGL (HPM_GPIO0_BASE + HPM_GPIOY_PL_TGL_OFFSET) +#define HPM_GPIOY_TP_VAL (HPM_GPIO0_BASE + HPM_GPIOY_TP_VAL_OFFSET) +#define HPM_GPIOY_TP_SET (HPM_GPIO0_BASE + HPM_GPIOY_TP_SET_OFFSET) +#define HPM_GPIOY_TP_CLR (HPM_GPIO0_BASE + HPM_GPIOY_TP_CLR_OFFSET) +#define HPM_GPIOY_TP_TGL (HPM_GPIO0_BASE + HPM_GPIOY_TP_TGL_OFFSET) +#define HPM_GPIOY_AS_VAL (HPM_GPIO0_BASE + HPM_GPIOY_AS_VAL_OFFSET) +#define HPM_GPIOY_AS_SET (HPM_GPIO0_BASE + HPM_GPIOY_AS_SET_OFFSET) +#define HPM_GPIOY_AS_CLR (HPM_GPIO0_BASE + HPM_GPIOY_AS_CLR_OFFSET) +#define HPM_GPIOY_AS_TGL (HPM_GPIO0_BASE + HPM_GPIOY_AS_TGL_OFFSET) + +#define HPM_GPIOZ_DI_VAL (HPM_GPIO0_BASE + HPM_GPIOZ_DI_VAL_OFFSET) +#define HPM_GPIOZ_DI_SET (HPM_GPIO0_BASE + HPM_GPIOZ_DI_SET_OFFSET) +#define HPM_GPIOZ_DI_CLR (HPM_GPIO0_BASE + HPM_GPIOZ_DI_CLR_OFFSET) +#define HPM_GPIOZ_DI_TGL (HPM_GPIO0_BASE + HPM_GPIOZ_DI_TGL_OFFSET) +#define HPM_GPIOZ_DO_VAL (HPM_GPIO0_BASE + HPM_GPIOZ_DO_VAL_OFFSET) +#define HPM_GPIOZ_DO_SET (HPM_GPIO0_BASE + HPM_GPIOZ_DO_SET_OFFSET) +#define HPM_GPIOZ_DO_CLR (HPM_GPIO0_BASE + HPM_GPIOZ_DO_CLR_OFFSET) +#define HPM_GPIOZ_DO_TGL (HPM_GPIO0_BASE + HPM_GPIOZ_DO_TGL_OFFSET) +#define HPM_GPIOZ_OE_VAL (HPM_GPIO0_BASE + HPM_GPIOZ_OE_VAL_OFFSET) +#define HPM_GPIOZ_OE_SET (HPM_GPIO0_BASE + HPM_GPIOZ_OE_SET_OFFSET) +#define HPM_GPIOZ_OE_CLR (HPM_GPIO0_BASE + HPM_GPIOZ_OE_CLR_OFFSET) +#define HPM_GPIOZ_OE_TGL (HPM_GPIO0_BASE + HPM_GPIOZ_OE_TGL_OFFSET) +#define HPM_GPIOZ_IF_VAL (HPM_GPIO0_BASE + HPM_GPIOZ_IF_VAL_OFFSET) +#define HPM_GPIOZ_IF_SET (HPM_GPIO0_BASE + HPM_GPIOZ_IF_SET_OFFSET) +#define HPM_GPIOZ_IF_CLR (HPM_GPIO0_BASE + HPM_GPIOZ_IF_CLR_OFFSET) +#define HPM_GPIOZ_IF_TGL (HPM_GPIO0_BASE + HPM_GPIOZ_IF_TGL_OFFSET) +#define HPM_GPIOZ_IE_VAL (HPM_GPIO0_BASE + HPM_GPIOZ_IE_VAL_OFFSET) +#define HPM_GPIOZ_IE_SET (HPM_GPIO0_BASE + HPM_GPIOZ_IE_SET_OFFSET) +#define HPM_GPIOZ_IE_CLR (HPM_GPIO0_BASE + HPM_GPIOZ_IE_CLR_OFFSET) +#define HPM_GPIOZ_IE_TGL (HPM_GPIO0_BASE + HPM_GPIOZ_IE_TGL_OFFSET) +#define HPM_GPIOZ_PL_VAL (HPM_GPIO0_BASE + HPM_GPIOZ_PL_VAL_OFFSET) +#define HPM_GPIOZ_PL_SET (HPM_GPIO0_BASE + HPM_GPIOZ_PL_SET_OFFSET) +#define HPM_GPIOZ_PL_CLR (HPM_GPIO0_BASE + HPM_GPIOZ_PL_CLR_OFFSET) +#define HPM_GPIOZ_PL_TGL (HPM_GPIO0_BASE + HPM_GPIOZ_PL_TGL_OFFSET) +#define HPM_GPIOZ_TP_VAL (HPM_GPIO0_BASE + HPM_GPIOZ_TP_VAL_OFFSET) +#define HPM_GPIOZ_TP_SET (HPM_GPIO0_BASE + HPM_GPIOZ_TP_SET_OFFSET) +#define HPM_GPIOZ_TP_CLR (HPM_GPIO0_BASE + HPM_GPIOZ_TP_CLR_OFFSET) +#define HPM_GPIOZ_TP_TGL (HPM_GPIO0_BASE + HPM_GPIOZ_TP_TGL_OFFSET) +#define HPM_GPIOZ_AS_VAL (HPM_GPIO0_BASE + HPM_GPIOZ_AS_VAL_OFFSET) +#define HPM_GPIOZ_AS_SET (HPM_GPIO0_BASE + HPM_GPIOZ_AS_SET_OFFSET) +#define HPM_GPIOZ_AS_CLR (HPM_GPIO0_BASE + HPM_GPIOZ_AS_CLR_OFFSET) +#define HPM_GPIOZ_AS_TGL (HPM_GPIO0_BASE + HPM_GPIOZ_AS_TGL_OFFSET) + +#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_GPIO_H */ \ No newline at end of file diff --git a/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_ioc.h b/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_ioc.h new file mode 100644 index 0000000000000..196ede0e42c0c --- /dev/null +++ b/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_ioc.h @@ -0,0 +1,641 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_ioc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_IOC_H +#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_IOC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/hpm_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* PAD register group index macro definition */ +#define HPM_IOC_PAD_PA00_INDEX (0UL) +#define HPM_IOC_PAD_PA01_INDEX (1UL) +#define HPM_IOC_PAD_PA02_INDEX (2UL) +#define HPM_IOC_PAD_PA03_INDEX (3UL) +#define HPM_IOC_PAD_PA04_INDEX (4UL) +#define HPM_IOC_PAD_PA05_INDEX (5UL) +#define HPM_IOC_PAD_PA06_INDEX (6UL) +#define HPM_IOC_PAD_PA07_INDEX (7UL) +#define HPM_IOC_PAD_PA08_INDEX (8UL) +#define HPM_IOC_PAD_PA09_INDEX (9UL) +#define HPM_IOC_PAD_PA10_INDEX (10UL) +#define HPM_IOC_PAD_PA11_INDEX (11UL) +#define HPM_IOC_PAD_PA12_INDEX (12UL) +#define HPM_IOC_PAD_PA13_INDEX (13UL) +#define HPM_IOC_PAD_PA14_INDEX (14UL) +#define HPM_IOC_PAD_PA15_INDEX (15UL) +#define HPM_IOC_PAD_PA16_INDEX (16UL) +#define HPM_IOC_PAD_PA17_INDEX (17UL) +#define HPM_IOC_PAD_PA18_INDEX (18UL) +#define HPM_IOC_PAD_PA19_INDEX (19UL) +#define HPM_IOC_PAD_PA20_INDEX (20UL) +#define HPM_IOC_PAD_PA21_INDEX (21UL) +#define HPM_IOC_PAD_PA22_INDEX (22UL) +#define HPM_IOC_PAD_PA23_INDEX (23UL) +#define HPM_IOC_PAD_PA24_INDEX (24UL) +#define HPM_IOC_PAD_PA25_INDEX (25UL) +#define HPM_IOC_PAD_PA26_INDEX (26UL) +#define HPM_IOC_PAD_PA27_INDEX (27UL) +#define HPM_IOC_PAD_PA28_INDEX (28UL) +#define HPM_IOC_PAD_PA29_INDEX (29UL) +#define HPM_IOC_PAD_PA30_INDEX (30UL) +#define HPM_IOC_PAD_PA31_INDEX (31UL) +#define HPM_IOC_PAD_PB00_INDEX (32UL) +#define HPM_IOC_PAD_PB01_INDEX (33UL) +#define HPM_IOC_PAD_PB02_INDEX (34UL) +#define HPM_IOC_PAD_PB03_INDEX (35UL) +#define HPM_IOC_PAD_PB04_INDEX (36UL) +#define HPM_IOC_PAD_PB05_INDEX (37UL) +#define HPM_IOC_PAD_PB06_INDEX (38UL) +#define HPM_IOC_PAD_PB07_INDEX (39UL) +#define HPM_IOC_PAD_PB08_INDEX (40UL) +#define HPM_IOC_PAD_PB09_INDEX (41UL) +#define HPM_IOC_PAD_PB10_INDEX (42UL) +#define HPM_IOC_PAD_PB11_INDEX (43UL) +#define HPM_IOC_PAD_PB12_INDEX (44UL) +#define HPM_IOC_PAD_PB13_INDEX (45UL) +#define HPM_IOC_PAD_PB14_INDEX (46UL) +#define HPM_IOC_PAD_PB15_INDEX (47UL) +#define HPM_IOC_PAD_PB16_INDEX (48UL) +#define HPM_IOC_PAD_PB17_INDEX (49UL) +#define HPM_IOC_PAD_PB18_INDEX (50UL) +#define HPM_IOC_PAD_PB19_INDEX (51UL) +#define HPM_IOC_PAD_PB20_INDEX (52UL) +#define HPM_IOC_PAD_PB21_INDEX (53UL) +#define HPM_IOC_PAD_PB22_INDEX (54UL) +#define HPM_IOC_PAD_PB23_INDEX (55UL) +#define HPM_IOC_PAD_PB24_INDEX (56UL) +#define HPM_IOC_PAD_PB25_INDEX (57UL) +#define HPM_IOC_PAD_PB26_INDEX (58UL) +#define HPM_IOC_PAD_PB27_INDEX (59UL) +#define HPM_IOC_PAD_PB28_INDEX (60UL) +#define HPM_IOC_PAD_PB29_INDEX (61UL) +#define HPM_IOC_PAD_PB30_INDEX (62UL) +#define HPM_IOC_PAD_PB31_INDEX (63UL) +#define HPM_IOC_PAD_PC00_INDEX (64UL) +#define HPM_IOC_PAD_PC01_INDEX (65UL) +#define HPM_IOC_PAD_PC02_INDEX (66UL) +#define HPM_IOC_PAD_PC03_INDEX (67UL) +#define HPM_IOC_PAD_PC04_INDEX (68UL) +#define HPM_IOC_PAD_PC05_INDEX (69UL) +#define HPM_IOC_PAD_PC06_INDEX (70UL) +#define HPM_IOC_PAD_PC07_INDEX (71UL) +#define HPM_IOC_PAD_PC08_INDEX (72UL) +#define HPM_IOC_PAD_PC09_INDEX (73UL) +#define HPM_IOC_PAD_PC10_INDEX (74UL) +#define HPM_IOC_PAD_PC11_INDEX (75UL) +#define HPM_IOC_PAD_PC12_INDEX (76UL) +#define HPM_IOC_PAD_PC13_INDEX (77UL) +#define HPM_IOC_PAD_PC14_INDEX (78UL) +#define HPM_IOC_PAD_PC15_INDEX (79UL) +#define HPM_IOC_PAD_PC16_INDEX (80UL) +#define HPM_IOC_PAD_PC17_INDEX (81UL) +#define HPM_IOC_PAD_PC18_INDEX (82UL) +#define HPM_IOC_PAD_PC19_INDEX (83UL) +#define HPM_IOC_PAD_PC20_INDEX (84UL) +#define HPM_IOC_PAD_PC21_INDEX (85UL) +#define HPM_IOC_PAD_PC22_INDEX (86UL) +#define HPM_IOC_PAD_PC23_INDEX (87UL) +#define HPM_IOC_PAD_PC24_INDEX (88UL) +#define HPM_IOC_PAD_PC25_INDEX (89UL) +#define HPM_IOC_PAD_PC26_INDEX (90UL) +#define HPM_IOC_PAD_PC27_INDEX (91UL) +#define HPM_IOC_PAD_PX00_INDEX (416UL) +#define HPM_IOC_PAD_PX01_INDEX (417UL) +#define HPM_IOC_PAD_PX02_INDEX (418UL) +#define HPM_IOC_PAD_PX03_INDEX (419UL) +#define HPM_IOC_PAD_PX04_INDEX (420UL) +#define HPM_IOC_PAD_PX05_INDEX (421UL) +#define HPM_IOC_PAD_PX06_INDEX (422UL) +#define HPM_IOC_PAD_PX07_INDEX (423UL) +#define HPM_IOC_PAD_PY00_INDEX (448UL) +#define HPM_IOC_PAD_PY01_INDEX (449UL) +#define HPM_IOC_PAD_PY02_INDEX (450UL) +#define HPM_IOC_PAD_PY03_INDEX (451UL) +#define HPM_IOC_PAD_PY04_INDEX (452UL) +#define HPM_IOC_PAD_PY05_INDEX (453UL) +#define HPM_IOC_PAD_PY06_INDEX (454UL) +#define HPM_IOC_PAD_PY07_INDEX (455UL) +#define HPM_IOC_PAD_PZ00_INDEX (480UL) +#define HPM_IOC_PAD_PZ01_INDEX (481UL) +#define HPM_IOC_PAD_PZ02_INDEX (482UL) +#define HPM_IOC_PAD_PZ03_INDEX (483UL) +#define HPM_IOC_PAD_PZ04_INDEX (484UL) +#define HPM_IOC_PAD_PZ05_INDEX (485UL) +#define HPM_IOC_PAD_PZ06_INDEX (486UL) +#define HPM_IOC_PAD_PZ07_INDEX (487UL) + +#define HPM_IOC_PAD_NREGISTERS 116 + +/* Register offsets *********************************************************/ + +#define HPM_IOC_PAD_FUNC_CTL_OFFSET(n) (0x0000 + ((unsigned int)(n) * 0x0008)) +#define HPM_IOC_PAD_PAD_CTL_OFFSET(n) (0x0004 + ((unsigned int)(n) * 0x0008)) + +#define HPM_IOC_PAD_PA00_FUNC_CTL_OFFSET 0x0000 +#define HPM_IOC_PAD_PA00_PAD_CTL_OFFSET 0x0004 +#define HPM_IOC_PAD_PA01_FUNC_CTL_OFFSET 0x0008 +#define HPM_IOC_PAD_PA01_PAD_CTL_OFFSET 0x000c +#define HPM_IOC_PAD_PA02_FUNC_CTL_OFFSET 0x0010 +#define HPM_IOC_PAD_PA02_PAD_CTL_OFFSET 0x0014 +#define HPM_IOC_PAD_PA03_FUNC_CTL_OFFSET 0x0018 +#define HPM_IOC_PAD_PA03_PAD_CTL_OFFSET 0x001c +#define HPM_IOC_PAD_PA04_FUNC_CTL_OFFSET 0x0020 +#define HPM_IOC_PAD_PA04_PAD_CTL_OFFSET 0x0024 +#define HPM_IOC_PAD_PA05_FUNC_CTL_OFFSET 0x0028 +#define HPM_IOC_PAD_PA05_PAD_CTL_OFFSET 0x002c +#define HPM_IOC_PAD_PA06_FUNC_CTL_OFFSET 0x0030 +#define HPM_IOC_PAD_PA06_PAD_CTL_OFFSET 0x0034 +#define HPM_IOC_PAD_PA07_FUNC_CTL_OFFSET 0x0038 +#define HPM_IOC_PAD_PA07_PAD_CTL_OFFSET 0x003c +#define HPM_IOC_PAD_PA08_FUNC_CTL_OFFSET 0x0040 +#define HPM_IOC_PAD_PA08_PAD_CTL_OFFSET 0x0044 +#define HPM_IOC_PAD_PA09_FUNC_CTL_OFFSET 0x0048 +#define HPM_IOC_PAD_PA09_PAD_CTL_OFFSET 0x004c +#define HPM_IOC_PAD_PA10_FUNC_CTL_OFFSET 0x0050 +#define HPM_IOC_PAD_PA10_PAD_CTL_OFFSET 0x0054 +#define HPM_IOC_PAD_PA11_FUNC_CTL_OFFSET 0x0058 +#define HPM_IOC_PAD_PA11_PAD_CTL_OFFSET 0x005c +#define HPM_IOC_PAD_PA12_FUNC_CTL_OFFSET 0x0060 +#define HPM_IOC_PAD_PA12_PAD_CTL_OFFSET 0x0064 +#define HPM_IOC_PAD_PA13_FUNC_CTL_OFFSET 0x0068 +#define HPM_IOC_PAD_PA13_PAD_CTL_OFFSET 0x006c +#define HPM_IOC_PAD_PA14_FUNC_CTL_OFFSET 0x0070 +#define HPM_IOC_PAD_PA14_PAD_CTL_OFFSET 0x0074 +#define HPM_IOC_PAD_PA15_FUNC_CTL_OFFSET 0x0078 +#define HPM_IOC_PAD_PA15_PAD_CTL_OFFSET 0x007c +#define HPM_IOC_PAD_PA16_FUNC_CTL_OFFSET 0x0080 +#define HPM_IOC_PAD_PA16_PAD_CTL_OFFSET 0x0084 +#define HPM_IOC_PAD_PA17_FUNC_CTL_OFFSET 0x0088 +#define HPM_IOC_PAD_PA17_PAD_CTL_OFFSET 0x008c +#define HPM_IOC_PAD_PA18_FUNC_CTL_OFFSET 0x0090 +#define HPM_IOC_PAD_PA18_PAD_CTL_OFFSET 0x0094 +#define HPM_IOC_PAD_PA19_FUNC_CTL_OFFSET 0x0098 +#define HPM_IOC_PAD_PA19_PAD_CTL_OFFSET 0x009c +#define HPM_IOC_PAD_PA20_FUNC_CTL_OFFSET 0x00a0 +#define HPM_IOC_PAD_PA20_PAD_CTL_OFFSET 0x00a4 +#define HPM_IOC_PAD_PA21_FUNC_CTL_OFFSET 0x00a8 +#define HPM_IOC_PAD_PA21_PAD_CTL_OFFSET 0x00ac +#define HPM_IOC_PAD_PA22_FUNC_CTL_OFFSET 0x00b0 +#define HPM_IOC_PAD_PA22_PAD_CTL_OFFSET 0x00b4 +#define HPM_IOC_PAD_PA23_FUNC_CTL_OFFSET 0x00b8 +#define HPM_IOC_PAD_PA23_PAD_CTL_OFFSET 0x00bc +#define HPM_IOC_PAD_PA24_FUNC_CTL_OFFSET 0x00c0 +#define HPM_IOC_PAD_PA24_PAD_CTL_OFFSET 0x00c4 +#define HPM_IOC_PAD_PA25_FUNC_CTL_OFFSET 0x00c8 +#define HPM_IOC_PAD_PA25_PAD_CTL_OFFSET 0x00cc +#define HPM_IOC_PAD_PA26_FUNC_CTL_OFFSET 0x00d0 +#define HPM_IOC_PAD_PA26_PAD_CTL_OFFSET 0x00d4 +#define HPM_IOC_PAD_PA27_FUNC_CTL_OFFSET 0x00d8 +#define HPM_IOC_PAD_PA27_PAD_CTL_OFFSET 0x00dc +#define HPM_IOC_PAD_PA28_FUNC_CTL_OFFSET 0x00e0 +#define HPM_IOC_PAD_PA28_PAD_CTL_OFFSET 0x00e4 +#define HPM_IOC_PAD_PA29_FUNC_CTL_OFFSET 0x00e8 +#define HPM_IOC_PAD_PA29_PAD_CTL_OFFSET 0x00ec +#define HPM_IOC_PAD_PA30_FUNC_CTL_OFFSET 0x00f0 +#define HPM_IOC_PAD_PA30_PAD_CTL_OFFSET 0x00f4 +#define HPM_IOC_PAD_PA31_FUNC_CTL_OFFSET 0x00f8 +#define HPM_IOC_PAD_PA31_PAD_CTL_OFFSET 0x00fc +#define HPM_IOC_PAD_PB00_FUNC_CTL_OFFSET 0x0100 +#define HPM_IOC_PAD_PB00_PAD_CTL_OFFSET 0x0104 +#define HPM_IOC_PAD_PB01_FUNC_CTL_OFFSET 0x0108 +#define HPM_IOC_PAD_PB01_PAD_CTL_OFFSET 0x010c +#define HPM_IOC_PAD_PB02_FUNC_CTL_OFFSET 0x0110 +#define HPM_IOC_PAD_PB02_PAD_CTL_OFFSET 0x0114 +#define HPM_IOC_PAD_PB03_FUNC_CTL_OFFSET 0x0118 +#define HPM_IOC_PAD_PB03_PAD_CTL_OFFSET 0x011c +#define HPM_IOC_PAD_PB04_FUNC_CTL_OFFSET 0x0120 +#define HPM_IOC_PAD_PB04_PAD_CTL_OFFSET 0x0124 +#define HPM_IOC_PAD_PB05_FUNC_CTL_OFFSET 0x0128 +#define HPM_IOC_PAD_PB05_PAD_CTL_OFFSET 0x012c +#define HPM_IOC_PAD_PB06_FUNC_CTL_OFFSET 0x0130 +#define HPM_IOC_PAD_PB06_PAD_CTL_OFFSET 0x0134 +#define HPM_IOC_PAD_PB07_FUNC_CTL_OFFSET 0x0138 +#define HPM_IOC_PAD_PB07_PAD_CTL_OFFSET 0x013c +#define HPM_IOC_PAD_PB08_FUNC_CTL_OFFSET 0x0140 +#define HPM_IOC_PAD_PB08_PAD_CTL_OFFSET 0x0144 +#define HPM_IOC_PAD_PB09_FUNC_CTL_OFFSET 0x0148 +#define HPM_IOC_PAD_PB09_PAD_CTL_OFFSET 0x014c +#define HPM_IOC_PAD_PB10_FUNC_CTL_OFFSET 0x0150 +#define HPM_IOC_PAD_PB10_PAD_CTL_OFFSET 0x0154 +#define HPM_IOC_PAD_PB11_FUNC_CTL_OFFSET 0x0158 +#define HPM_IOC_PAD_PB11_PAD_CTL_OFFSET 0x015c +#define HPM_IOC_PAD_PB12_FUNC_CTL_OFFSET 0x0160 +#define HPM_IOC_PAD_PB12_PAD_CTL_OFFSET 0x0164 +#define HPM_IOC_PAD_PB13_FUNC_CTL_OFFSET 0x0168 +#define HPM_IOC_PAD_PB13_PAD_CTL_OFFSET 0x016c +#define HPM_IOC_PAD_PB14_FUNC_CTL_OFFSET 0x0170 +#define HPM_IOC_PAD_PB14_PAD_CTL_OFFSET 0x0174 +#define HPM_IOC_PAD_PB15_FUNC_CTL_OFFSET 0x0178 +#define HPM_IOC_PAD_PB15_PAD_CTL_OFFSET 0x017c +#define HPM_IOC_PAD_PB16_FUNC_CTL_OFFSET 0x0180 +#define HPM_IOC_PAD_PB16_PAD_CTL_OFFSET 0x0184 +#define HPM_IOC_PAD_PB17_FUNC_CTL_OFFSET 0x0188 +#define HPM_IOC_PAD_PB17_PAD_CTL_OFFSET 0x018c +#define HPM_IOC_PAD_PB18_FUNC_CTL_OFFSET 0x0190 +#define HPM_IOC_PAD_PB18_PAD_CTL_OFFSET 0x0194 +#define HPM_IOC_PAD_PB19_FUNC_CTL_OFFSET 0x0198 +#define HPM_IOC_PAD_PB19_PAD_CTL_OFFSET 0x019c +#define HPM_IOC_PAD_PB20_FUNC_CTL_OFFSET 0x01a0 +#define HPM_IOC_PAD_PB20_PAD_CTL_OFFSET 0x01a4 +#define HPM_IOC_PAD_PB21_FUNC_CTL_OFFSET 0x01a8 +#define HPM_IOC_PAD_PB21_PAD_CTL_OFFSET 0x01ac +#define HPM_IOC_PAD_PB22_FUNC_CTL_OFFSET 0x01b0 +#define HPM_IOC_PAD_PB22_PAD_CTL_OFFSET 0x01b4 +#define HPM_IOC_PAD_PB23_FUNC_CTL_OFFSET 0x01b8 +#define HPM_IOC_PAD_PB23_PAD_CTL_OFFSET 0x01bc +#define HPM_IOC_PAD_PB24_FUNC_CTL_OFFSET 0x01c0 +#define HPM_IOC_PAD_PB24_PAD_CTL_OFFSET 0x01c4 +#define HPM_IOC_PAD_PB25_FUNC_CTL_OFFSET 0x01c8 +#define HPM_IOC_PAD_PB25_PAD_CTL_OFFSET 0x01cc +#define HPM_IOC_PAD_PB26_FUNC_CTL_OFFSET 0x01d0 +#define HPM_IOC_PAD_PB26_PAD_CTL_OFFSET 0x01d4 +#define HPM_IOC_PAD_PB27_FUNC_CTL_OFFSET 0x01d8 +#define HPM_IOC_PAD_PB27_PAD_CTL_OFFSET 0x01dc +#define HPM_IOC_PAD_PB28_FUNC_CTL_OFFSET 0x01e0 +#define HPM_IOC_PAD_PB28_PAD_CTL_OFFSET 0x01e4 +#define HPM_IOC_PAD_PB29_FUNC_CTL_OFFSET 0x01e8 +#define HPM_IOC_PAD_PB29_PAD_CTL_OFFSET 0x01ec +#define HPM_IOC_PAD_PB30_FUNC_CTL_OFFSET 0x01f0 +#define HPM_IOC_PAD_PB30_PAD_CTL_OFFSET 0x01f4 +#define HPM_IOC_PAD_PB31_FUNC_CTL_OFFSET 0x01f8 +#define HPM_IOC_PAD_PB31_PAD_CTL_OFFSET 0x01fc +#define HPM_IOC_PAD_PC00_FUNC_CTL_OFFSET 0x0200 +#define HPM_IOC_PAD_PC00_PAD_CTL_OFFSET 0x0204 +#define HPM_IOC_PAD_PC01_FUNC_CTL_OFFSET 0x0208 +#define HPM_IOC_PAD_PC01_PAD_CTL_OFFSET 0x020c +#define HPM_IOC_PAD_PC02_FUNC_CTL_OFFSET 0x0210 +#define HPM_IOC_PAD_PC02_PAD_CTL_OFFSET 0x0214 +#define HPM_IOC_PAD_PC03_FUNC_CTL_OFFSET 0x0218 +#define HPM_IOC_PAD_PC03_PAD_CTL_OFFSET 0x021c +#define HPM_IOC_PAD_PC04_FUNC_CTL_OFFSET 0x0220 +#define HPM_IOC_PAD_PC04_PAD_CTL_OFFSET 0x0224 +#define HPM_IOC_PAD_PC05_FUNC_CTL_OFFSET 0x0228 +#define HPM_IOC_PAD_PC05_PAD_CTL_OFFSET 0x022c +#define HPM_IOC_PAD_PC06_FUNC_CTL_OFFSET 0x0230 +#define HPM_IOC_PAD_PC06_PAD_CTL_OFFSET 0x0234 +#define HPM_IOC_PAD_PC07_FUNC_CTL_OFFSET 0x0238 +#define HPM_IOC_PAD_PC07_PAD_CTL_OFFSET 0x023c +#define HPM_IOC_PAD_PC08_FUNC_CTL_OFFSET 0x0240 +#define HPM_IOC_PAD_PC08_PAD_CTL_OFFSET 0x0244 +#define HPM_IOC_PAD_PC09_FUNC_CTL_OFFSET 0x0248 +#define HPM_IOC_PAD_PC09_PAD_CTL_OFFSET 0x024c +#define HPM_IOC_PAD_PC10_FUNC_CTL_OFFSET 0x0250 +#define HPM_IOC_PAD_PC10_PAD_CTL_OFFSET 0x0254 +#define HPM_IOC_PAD_PC11_FUNC_CTL_OFFSET 0x0258 +#define HPM_IOC_PAD_PC11_PAD_CTL_OFFSET 0x025c +#define HPM_IOC_PAD_PC12_FUNC_CTL_OFFSET 0x0260 +#define HPM_IOC_PAD_PC12_PAD_CTL_OFFSET 0x0264 +#define HPM_IOC_PAD_PC13_FUNC_CTL_OFFSET 0x0268 +#define HPM_IOC_PAD_PC13_PAD_CTL_OFFSET 0x026c +#define HPM_IOC_PAD_PC14_FUNC_CTL_OFFSET 0x0270 +#define HPM_IOC_PAD_PC14_PAD_CTL_OFFSET 0x0274 +#define HPM_IOC_PAD_PC15_FUNC_CTL_OFFSET 0x0278 +#define HPM_IOC_PAD_PC15_PAD_CTL_OFFSET 0x027c +#define HPM_IOC_PAD_PC16_FUNC_CTL_OFFSET 0x0280 +#define HPM_IOC_PAD_PC16_PAD_CTL_OFFSET 0x0284 +#define HPM_IOC_PAD_PC17_FUNC_CTL_OFFSET 0x0288 +#define HPM_IOC_PAD_PC17_PAD_CTL_OFFSET 0x028c +#define HPM_IOC_PAD_PC18_FUNC_CTL_OFFSET 0x0290 +#define HPM_IOC_PAD_PC18_PAD_CTL_OFFSET 0x0294 +#define HPM_IOC_PAD_PC19_FUNC_CTL_OFFSET 0x0298 +#define HPM_IOC_PAD_PC19_PAD_CTL_OFFSET 0x029c +#define HPM_IOC_PAD_PC20_FUNC_CTL_OFFSET 0x02a0 +#define HPM_IOC_PAD_PC20_PAD_CTL_OFFSET 0x02a4 +#define HPM_IOC_PAD_PC21_FUNC_CTL_OFFSET 0x02a8 +#define HPM_IOC_PAD_PC21_PAD_CTL_OFFSET 0x02ac +#define HPM_IOC_PAD_PC22_FUNC_CTL_OFFSET 0x02b0 +#define HPM_IOC_PAD_PC22_PAD_CTL_OFFSET 0x02b4 +#define HPM_IOC_PAD_PC23_FUNC_CTL_OFFSET 0x02b8 +#define HPM_IOC_PAD_PC23_PAD_CTL_OFFSET 0x02bc +#define HPM_IOC_PAD_PC24_FUNC_CTL_OFFSET 0x02c0 +#define HPM_IOC_PAD_PC24_PAD_CTL_OFFSET 0x02c4 +#define HPM_IOC_PAD_PC25_FUNC_CTL_OFFSET 0x02c8 +#define HPM_IOC_PAD_PC25_PAD_CTL_OFFSET 0x02cc +#define HPM_IOC_PAD_PC26_FUNC_CTL_OFFSET 0x02d0 +#define HPM_IOC_PAD_PC26_PAD_CTL_OFFSET 0x02d4 +#define HPM_IOC_PAD_PC27_FUNC_CTL_OFFSET 0x02d8 +#define HPM_IOC_PAD_PC27_PAD_CTL_OFFSET 0x02dc +#define HPM_IOC_PAD_PX00_FUNC_CTL_OFFSET 0x0d00 +#define HPM_IOC_PAD_PX00_PAD_CTL_OFFSET 0x0d04 +#define HPM_IOC_PAD_PX01_FUNC_CTL_OFFSET 0x0d08 +#define HPM_IOC_PAD_PX01_PAD_CTL_OFFSET 0x0d0c +#define HPM_IOC_PAD_PX02_FUNC_CTL_OFFSET 0x0d10 +#define HPM_IOC_PAD_PX02_PAD_CTL_OFFSET 0x0d14 +#define HPM_IOC_PAD_PX03_FUNC_CTL_OFFSET 0x0d18 +#define HPM_IOC_PAD_PX03_PAD_CTL_OFFSET 0x0d1c +#define HPM_IOC_PAD_PX04_FUNC_CTL_OFFSET 0x0d20 +#define HPM_IOC_PAD_PX04_PAD_CTL_OFFSET 0x0d24 +#define HPM_IOC_PAD_PX05_FUNC_CTL_OFFSET 0x0d28 +#define HPM_IOC_PAD_PX05_PAD_CTL_OFFSET 0x0d2c +#define HPM_IOC_PAD_PX06_FUNC_CTL_OFFSET 0x0d30 +#define HPM_IOC_PAD_PX06_PAD_CTL_OFFSET 0x0d34 +#define HPM_IOC_PAD_PX07_FUNC_CTL_OFFSET 0x0d38 +#define HPM_IOC_PAD_PX07_PAD_CTL_OFFSET 0x0d3c +#define HPM_IOC_PAD_PY00_FUNC_CTL_OFFSET 0x0e00 +#define HPM_IOC_PAD_PY00_PAD_CTL_OFFSET 0x0e04 +#define HPM_IOC_PAD_PY01_FUNC_CTL_OFFSET 0x0e08 +#define HPM_IOC_PAD_PY01_PAD_CTL_OFFSET 0x0e0c +#define HPM_IOC_PAD_PY02_FUNC_CTL_OFFSET 0x0e10 +#define HPM_IOC_PAD_PY02_PAD_CTL_OFFSET 0x0e14 +#define HPM_IOC_PAD_PY03_FUNC_CTL_OFFSET 0x0e18 +#define HPM_IOC_PAD_PY03_PAD_CTL_OFFSET 0x0e1c +#define HPM_IOC_PAD_PY04_FUNC_CTL_OFFSET 0x0e20 +#define HPM_IOC_PAD_PY04_PAD_CTL_OFFSET 0x0e24 +#define HPM_IOC_PAD_PY05_FUNC_CTL_OFFSET 0x0e28 +#define HPM_IOC_PAD_PY05_PAD_CTL_OFFSET 0x0e2c +#define HPM_IOC_PAD_PY06_FUNC_CTL_OFFSET 0x0e30 +#define HPM_IOC_PAD_PY06_PAD_CTL_OFFSET 0x0e34 +#define HPM_IOC_PAD_PY07_FUNC_CTL_OFFSET 0x0e38 +#define HPM_IOC_PAD_PY07_PAD_CTL_OFFSET 0x0e3c +#define HPM_IOC_PAD_PZ00_FUNC_CTL_OFFSET 0x0f00 +#define HPM_IOC_PAD_PZ00_PAD_CTL_OFFSET 0x0f04 +#define HPM_IOC_PAD_PZ01_FUNC_CTL_OFFSET 0x0f08 +#define HPM_IOC_PAD_PZ01_PAD_CTL_OFFSET 0x0f0c +#define HPM_IOC_PAD_PZ02_FUNC_CTL_OFFSET 0x0f10 +#define HPM_IOC_PAD_PZ02_PAD_CTL_OFFSET 0x0f14 +#define HPM_IOC_PAD_PZ03_FUNC_CTL_OFFSET 0x0f18 +#define HPM_IOC_PAD_PZ03_PAD_CTL_OFFSET 0x0f1c +#define HPM_IOC_PAD_PZ04_FUNC_CTL_OFFSET 0x0f20 +#define HPM_IOC_PAD_PZ04_PAD_CTL_OFFSET 0x0f24 +#define HPM_IOC_PAD_PZ05_FUNC_CTL_OFFSET 0x0f28 +#define HPM_IOC_PAD_PZ05_PAD_CTL_OFFSET 0x0f2c +#define HPM_IOC_PAD_PZ06_FUNC_CTL_OFFSET 0x0f30 +#define HPM_IOC_PAD_PZ06_PAD_CTL_OFFSET 0x0f34 +#define HPM_IOC_PAD_PZ07_FUNC_CTL_OFFSET 0x0f38 +#define HPM_IOC_PAD_PZ07_PAD_CTL_OFFSET 0x0f3c + +#define HPM_IOC_PAD_FUNC_CTL_ADDRESS(n) (HPM_IOC_BASE + HPM_IOC_PAD_FUNC_CTL_OFFSET(n)) +#define HPM_IOC_PAD_PAD_CTL_ADDRESS(n) (HPM_IOC_BASE + HPM_IOC_PAD_PAD_CTL_OFFSET(n)) + +#define HPM_IOC_PAD_PA00_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA00_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA00_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA00_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA01_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA01_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA01_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA01_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA02_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA02_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA02_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA02_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA03_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA03_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA03_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA03_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA04_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA04_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA04_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA04_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA05_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA05_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA05_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA05_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA06_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA06_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA06_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA06_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA07_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA07_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA07_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA07_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA08_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA08_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA08_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA08_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA09_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA09_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA09_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA09_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA10_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA10_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA10_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA10_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA11_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA11_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA11_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA11_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA12_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA12_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA12_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA12_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA13_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA13_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA13_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA13_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA14_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA14_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA14_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA14_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA15_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA15_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA15_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA15_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA16_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA16_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA16_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA16_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA17_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA17_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA17_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA17_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA18_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA18_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA18_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA18_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA19_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA19_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA19_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA19_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA20_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA20_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA20_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA20_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA21_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA21_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA21_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA21_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA22_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA22_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA22_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA22_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA23_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA23_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA23_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA23_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA24_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA24_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA24_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA24_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA25_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA25_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA25_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA25_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA26_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA26_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA26_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA26_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA27_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA27_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA27_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA27_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA28_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA28_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA28_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA28_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA29_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA29_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA29_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA29_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA30_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA30_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA30_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA30_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PA31_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA31_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PA31_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PA31_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB00_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB00_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB00_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB00_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB01_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB01_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB01_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB01_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB02_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB02_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB02_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB02_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB03_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB03_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB03_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB03_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB04_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB04_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB04_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB04_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB05_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB05_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB05_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB05_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB06_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB06_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB06_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB06_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB07_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB07_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB07_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB07_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB08_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB08_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB08_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB08_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB09_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB09_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB09_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB09_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB10_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB10_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB10_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB10_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB11_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB11_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB11_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB11_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB12_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB12_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB12_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB12_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB13_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB13_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB13_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB13_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB14_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB14_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB14_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB14_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB15_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB15_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB15_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB15_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB16_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB16_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB16_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB16_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB17_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB17_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB17_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB17_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB18_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB18_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB18_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB18_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB19_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB19_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB19_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB19_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB20_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB20_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB20_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB20_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB21_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB21_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB21_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB21_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB22_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB22_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB22_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB22_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB23_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB23_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB23_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB23_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB24_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB24_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB24_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB24_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB25_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB25_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB25_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB25_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB26_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB26_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB26_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB26_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB27_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB27_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB27_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB27_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB28_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB28_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB28_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB28_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB29_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB29_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB29_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB29_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB30_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB30_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB30_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB30_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PB31_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB31_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PB31_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PB31_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC00_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC00_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC00_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC00_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC01_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC01_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC01_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC01_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC02_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC02_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC02_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC02_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC03_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC03_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC03_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC03_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC04_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC04_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC04_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC04_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC05_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC05_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC05_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC05_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC06_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC06_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC06_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC06_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC07_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC07_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC07_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC07_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC08_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC08_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC08_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC08_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC09_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC09_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC09_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC09_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC10_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC10_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC10_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC10_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC11_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC11_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC11_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC11_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC12_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC12_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC12_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC12_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC13_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC13_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC13_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC13_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC14_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC14_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC14_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC14_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC15_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC15_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC15_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC15_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC16_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC16_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC16_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC16_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC17_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC17_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC17_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC17_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC18_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC18_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC18_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC18_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC19_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC19_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC19_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC19_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC20_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC20_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC20_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC20_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC21_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC21_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC21_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC21_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC22_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC22_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC22_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC22_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC23_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC23_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC23_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC23_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC24_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC24_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC24_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC24_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC25_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC25_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC25_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC25_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC26_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC26_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC26_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC26_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PC27_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC27_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PC27_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PC27_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PX00_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX00_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PX00_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX00_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PX01_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX01_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PX01_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX01_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PX02_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX02_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PX02_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX02_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PX03_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX03_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PX03_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX03_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PX04_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX04_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PX04_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX04_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PX05_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX05_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PX05_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX05_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PX06_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX06_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PX06_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX06_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PX07_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX07_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PX07_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PX07_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PY00_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY00_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PY00_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY00_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PY01_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY01_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PY01_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY01_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PY02_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY02_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PY02_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY02_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PY03_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY03_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PY03_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY03_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PY04_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY04_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PY04_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY04_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PY05_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY05_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PY05_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY05_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PY06_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY06_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PY06_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY06_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PY07_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY07_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PY07_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PY07_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PZ00_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ00_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PZ00_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ00_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PZ01_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ01_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PZ01_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ01_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PZ02_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ02_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PZ02_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ02_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PZ03_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ03_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PZ03_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ03_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PZ04_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ04_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PZ04_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ04_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PZ05_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ05_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PZ05_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ05_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PZ06_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ06_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PZ06_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ06_PAD_CTL_OFFSET ) +#define HPM_IOC_PAD_PZ07_FUNC_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ07_FUNC_CTL_OFFSET) +#define HPM_IOC_PAD_PZ07_PAD_CTL (HPM_IOC_BASE + HPM_IOC_PAD_PZ07_PAD_CTL_OFFSET ) + +#define HPM_PIOC_PAD_FUNC_CTL_ADDRESS(n) (HPM_PIOC_BASE + HPM_IOC_PAD_FUNC_CTL_OFFSET(n)) +#define HPM_PIOC_PAD_PAD_CTL_ADDRESS(n) (HPM_PIOC_BASE + HPM_IOC_PAD_PAD_CTL_OFFSET(n)) + +#define HPM_PIOC_PAD_PY00_FUNC_CTL (HPM_PIOC_BASE + HPM_IOC_PAD_PY00_FUNC_CTL_OFFSET) +#define HPM_PIOC_PAD_PY01_FUNC_CTL (HPM_PIOC_BASE + HPM_IOC_PAD_PY01_FUNC_CTL_OFFSET) +#define HPM_PIOC_PAD_PY02_FUNC_CTL (HPM_PIOC_BASE + HPM_IOC_PAD_PY02_FUNC_CTL_OFFSET) +#define HPM_PIOC_PAD_PY03_FUNC_CTL (HPM_PIOC_BASE + HPM_IOC_PAD_PY03_FUNC_CTL_OFFSET) +#define HPM_PIOC_PAD_PY04_FUNC_CTL (HPM_PIOC_BASE + HPM_IOC_PAD_PY04_FUNC_CTL_OFFSET) +#define HPM_PIOC_PAD_PY05_FUNC_CTL (HPM_PIOC_BASE + HPM_IOC_PAD_PY05_FUNC_CTL_OFFSET) +#define HPM_PIOC_PAD_PY06_FUNC_CTL (HPM_PIOC_BASE + HPM_IOC_PAD_PY06_FUNC_CTL_OFFSET) +#define HPM_PIOC_PAD_PY07_FUNC_CTL (HPM_PIOC_BASE + HPM_IOC_PAD_PY07_FUNC_CTL_OFFSET) + +#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_IOC_H */ \ No newline at end of file diff --git a/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_memorymap.h b/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_memorymap.h new file mode 100644 index 0000000000000..715291c46f4bc --- /dev/null +++ b/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_memorymap.h @@ -0,0 +1,141 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_MEMORYMAP_H +#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_MEMORYMAP_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Base Address ****************************************************/ + +#define HPM_PLIC_BASE 0xE4000000 +#define HPM_MCHTMR_BASE 0xE6000000 +#define HPM_GPIO0_BASE 0xF0000000 + +#define HPM_GPIOM_BASE 0xF0008000 +#define HPM_ADC0_BASE 0xF0010000 +#define HPM_ADC1_BASE 0xF0014000 +#define HPM_ADC2_BASE 0xF0018000 + +#define HPM_ACMP_BASE 0xF0020000 +#define HPM_DAC_BASE 0Xf0024000 +#define HPM_SPI0_BASE 0xF0030000 +#define HPM_SPI1_BASE 0xF0034000 +#define HPM_SPI2_BASE 0xF0038000 +#define HPM_SPI3_BASE 0xF003c000 +#define HPM_UART0_BASE 0xF0040000 +#define HPM_UART1_BASE 0xF0044000 +#define HPM_UART2_BASE 0xF0048000 +#define HPM_UART3_BASE 0xF004C000 +#define HPM_UART4_BASE 0xF0050000 +#define HPM_UART5_BASE 0xF0054000 +#define HPM_UART6_BASE 0xF0058000 +#define HPM_UART7_BASE 0xF005C000 + +#define HPM_CAN0_BASE 0xF0080000 +#define HPM_CAN1_BASE 0xF0084000 + +#define HPM_WDG0_BASE 0xF0090000 +#define HPM_WDG1_BASE 0xF0094000 + +#define HPM_MBX0A_BASE 0xF00A0000 +#define HPM_MBX0B_BASE 0xF00A4000 + +#define HPM_PTPC_BASE 0xF00B0000 +#define HPM_DMAMUX_BASE 0xF00C0000 +#define HPM_HDMA_BASE 0xF00C4000 +#define HPM_RNG_BASE 0xF00C8000 +#define HPM_KEYM_BASE 0xF00CC000 +#define HPM_I2S0_BASE 0xF0100000 +#define HPM_I2S1_BASE 0xF0104000 + +#define HPM_DAO_BASE 0xF0110000 +#define HPM_PDM_BASE 0xF0114000 +#define HPM_PWM0_BASE 0xF0200000 +#define HPM_HALL0_BASE 0xF0204000 +#define HPM_QEI0_BASE 0xF0208000 +#define HPM_TRGM0_BASE 0xF020C000 +#define HPM_PWM1_BASE 0xF0210000 +#define HPM_HALL1_BASE 0xF0214000 +#define HPM_QEI1_BASE 0xF0218000 +#define HPM_TRGM1_BASE 0xF021C000 + +#define HPM_SYNT_BASE 0xF0240000 + +#define HPM_ENET0_BASE 0xF2000000 + +#define HPM_NTMR0_BASE 0xF2010000 + +#define HPM_USB0_BASE 0xF2020000 + +#define HPM_SDXC0_BASE 0xF2030000 + +#define HPM_CONCTL_BASE 0xF2040000 +#define HPM_GPTMR0_BASE 0xF3000000 +#define HPM_GPTMR1_BASE 0xF3004000 +#define HPM_GPTMR2_BASE 0xF3008000 +#define HPM_GPTMR3_BASE 0xF300C000 + +#define HPM_I2C0_BASE 0xF3020000 +#define HPM_I2C1_BASE 0xF3020000 +#define HPM_I2C2_BASE 0xF3020000 +#define HPM_I2C3_BASE 0xF3020000 +#define HPM_XPI0_BASE 0xF3040000 +#define HPM_XPI1_BASE 0xF3044000 +#define HPM_XDMA_BASE 0xF3048000 +#define HPM_SDP_BASE 0xF304C000 +#define HPM_FEMC_BASE 0xF3050000 +#define HPM_ROMC_BASE 0xF3054000 +#define HPM_FFA_BASE 0xF3058000 +#define HPM_SYSCTL_BASE 0xF4000000 +#define HPM_IOC_BASE 0xF4040000 +#define HPM_OTPSHW_BASE 0xF4080000 +#define HPM_PPOR_BASE 0xF40C0000 +#define HPM_PCFG_BASE 0xF40C4000 +#define HPM_OTP_BASE 0xF40C8000 +#define HPM_PSEC_BASE 0xF40CC000 +#define HPM_PMON_BASE 0xF40D0000 +#define HPM_PGPR_BASE 0xF40D4000 +#define HPM_PIOC_BASE 0xF40D8000 +#define HPM_PGPIO_BASE 0xF40DC000 +#define HPM_PTMR_BASE 0xF40E0000 +#define HPM_PUART_BASE 0xF40E4000 +#define HPM_PWDG_BASE 0xF40E8000 + +#define HPM_PLLCTL_BASE 0xF4100000 +#define HPM_TSNS_BASE 0xF4104000 +#define HPM_BACC_BASE 0xF5000000 +#define HPM_BPOR_BASE 0xF5004000 +#define HPM_BCFG_BASE 0xF5008000 +#define HPM_BUTN_BASE 0xF500C000 +#define HPM_BIOC_BASE 0xF5010000 +#define HPM_BGPIO_BASE 0xF5014000 +#define HPM_BGPR_BASE 0xF5018000 +#define HPM_RTCSHW_BASE 0xF501C000 +#define HPM_BSEC_BASE 0xF5040000 +#define HPM_RTC_BASE 0xF5044000 +#define HPM_BKEY_BASE 0xF5048000 +#define HPM_BMON_BASE 0xF504C000 +#define HPM_TAMP_BASE 0xF5050000 +#define HPM_MONO_BASE 0xF5054000 + +#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_MEMORYMAP_H */ diff --git a/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pcfg.h b/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pcfg.h new file mode 100644 index 0000000000000..91b99d891ae33 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pcfg.h @@ -0,0 +1,118 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pcfg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PCFG_H +#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PCFG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hpm_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define HPM_PCFG_BANDGAP (HPM_PCFG_BASE + 0x0000) +#define HPM_PCFG_LDO1P1 (HPM_PCFG_BASE + 0x0004) +#define HPM_PCFG_LDO2P5 (HPM_PCFG_BASE + 0x0008) +#define HPM_PCFG_DCDC_MODE (HPM_PCFG_BASE + 0x0010) +#define HPM_PCFG_DCDC_LPMODE (HPM_PCFG_BASE + 0x0014) +#define HPM_PCFG_DCDC_PROT (HPM_PCFG_BASE + 0x0018) +#define HPM_PCFG_DCDC_CURRENT (HPM_PCFG_BASE + 0x001C) +#define HPM_PCFG_DCDC_ADVMODE (HPM_PCFG_BASE + 0x0020) +#define HPM_PCFG_DCDC_ADVPARAM (HPM_PCFG_BASE + 0x0024) +#define HPM_PCFG_DCDC_MISC (HPM_PCFG_BASE + 0x0028) +#define HPM_PCFG_DCDC_DEBUG (HPM_PCFG_BASE + 0x002C) +#define HPM_PCFG_DCDC_START_TIME (HPM_PCFG_BASE + 0x0030) +#define HPM_PCFG_DCDC_RESUME_TIME (HPM_PCFG_BASE + 0x0034) +#define HPM_PCFG_POWER_TRAP (HPM_PCFG_BASE + 0x0040) +#define HPM_PCFG_WAKE_CAUSE (HPM_PCFG_BASE + 0x0044) +#define HPM_PCFG_WAK_MASK (HPM_PCFG_BASE + 0x0048) +#define HPM_PCFG_SCG_CTRL (HPM_PCFG_BASE + 0x004C) +#define HPM_PCFG_DEBUG_STOP (HPM_PCFG_BASE + 0x0050) +#define HPM_PCFG_RC24M (HPM_PCFG_BASE + 0x0060) +#define HPM_PCFG_RC24M_TRACK (HPM_PCFG_BASE + 0x0064) +#define HPM_PCFG_TRACK_TARGET (HPM_PCFG_BASE + 0x0068) +#define HPM_PCFG_STATUS (HPM_PCFG_BASE + 0x006C) + +#define HPM_PCFG_BANDGAP_VBG_P50_TRIM_SHIFT (0) +#define HPM_PCFG_BANDGAP_VBG_P50_TRIM_MASK (0x1F << HPM_PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) +#define HPM_PCFG_BANDGAP_VBG_P50_TRIM(n) ((n) << HPM_PCFG_BANDGAP_VBG_P50_TRIM_SHIFT) + +#define HPM_PCFG_BANDGAP_VBG_P65_TRIM_SHIFT (8) +#define HPM_PCFG_BANDGAP_VBG_P65_TRIM_MASK (0x1F << HPM_PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) +#define HPM_PCFG_BANDGAP_VBG_P65_TRIM(n) ((n) << HPM_PCFG_BANDGAP_VBG_P65_TRIM_SHIFT) + +#define HPM_PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT (16) +#define HPM_PCFG_BANDGAP_VBG_1P0_TRIM_MASK (0x1F << HPM_PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) +#define HPM_PCFG_BANDGAP_VBG_1P0_TRIM(n) ((n) << HPM_PCFG_BANDGAP_VBG_1P0_TRIM_SHIFT) + +#define HPM_PCFG_BANDGAP_POWER_SAVE_SHIFT (24) +#define HPM_PCFG_BANDGAP_POWER_SAVE_NORMAL (0 << HPM_PCFG_BANDGAP_POWER_SAVE_SHIFT) +#define HPM_PCFG_BANDGAP_POWER_SAVE_LOW (1 << HPM_PCFG_BANDGAP_POWER_SAVE_SHIFT) + +#define HPM_PCFG_BANDGAP_LOWPOWER_MODE_SHIFT (25) +#define HPM_PCFG_BANDGAP_LOWPOWER_MODE_NORMAL (0 << HPM_PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) +#define HPM_PCFG_BANDGAP_LOWPOWER_MODE_LOW (1 << HPM_PCFG_BANDGAP_LOWPOWER_MODE_SHIFT) + +#define HPM_PCFG_BANDGAP_VBG_TRIMMED_SHIFT (31) +#define HPM_PCFG_BANDGAP_VBG_TRIMMED_UNCALIBRATED (0 << HPM_PCFG_BANDGAP_VBG_TRIMMED_SHIFT) +#define HPM_PCFG_BANDGAP_VBG_TRIMMED_CALIBRATED (1 << HPM_PCFG_BANDGAP_VBG_TRIMMED_SHIFT) + +#define HPM_PCFG_LDO1P1_VOLT_SHIFT (0) +#define HPM_PCFG_LDO1P1_VOLT_MASK (0x7FF << HPM_PCFG_LDO1P1_VOLT_SHIFT) +#define HPM_PCFG_LDO1P1_VOLT(n) ((n) << HPM_PCFG_LDO1P1_VOLT_SHIFT) + +#define HPM_PCFG_LDO2P5_VOLT_SHIFT (0) +#define HPM_PCFG_LDO2P5_VOLT_MASK (0x7FF << HPM_PCFG_LDO2P5_VOLT_SHIFT) +#define HPM_PCFG_LDO2P5_VOLT(n) ((n) << HPM_PCFG_LDO2P5_VOLT_SHIFT) + +#define HPM_PCFG_LDO2P5_ENABLE_SHIFT (16) +#define HPM_PCFG_LDO2P5_ENABLE_DISABL (0 << HPM_PCFG_LDO2P5_ENABLE_SHIFT) +#define HPM_PCFG_LDO2P5_ENABLE_ENABLE (1 << HPM_PCFG_LDO2P5_ENABLE_SHIFT) + +#define HPM_PCFG_LDO2P5_READY_SHIFT (28) +#define HPM_PCFG_LDO2P5_READY_NOT_RE (0 << HPM_PCFG_LDO2P5_READY_SHIFT) +#define HPM_PCFG_LDO2P5_READY_READY (1 << HPM_PCFG_LDO2P5_READY_SHIFT) + +#define HPM_PCFG_DCDC_MODE_VOLT_SHIFT (0) +#define HPM_PCFG_DCDC_MODE_VOLT_MASK (0x7FF << HPM_PCFG_DCDC_MODE_VOLT_SHIFT) +#define HPM_PCFG_DCDC_MODE_VOLT(n) ((n) << HPM_PCFG_DCDC_MODE_VOLT_SHIFT) + +#define HPM_PCFG_DCDC_MODE_MODE_SHIFT (16) +#define HPM_PCFG_DCDC_MODE_MODE_MASK (0x07 << HPM_PCFG_DCDC_MODE_MODE_SHIFT) +#define HPM_PCFG_DCDC_MODE_MODE(n) ((n) << HPM_PCFG_DCDC_MODE_MODE_SHIFT) +#define HPM_PCFG_DCDC_MODE_CLOSE (0 << HPM_PCFG_DCDC_MODE_MODE_SHIFT) +#define HPM_PCFG_DCDC_MODE_NORMAL (1 << HPM_PCFG_DCDC_MODE_MODE_SHIFT) +#define HPM_PCFG_DCDC_MODE_UNIVERSAL (3 << HPM_PCFG_DCDC_MODE_MODE_SHIFT) +#define HPM_PCFG_DCDC_MODE_PRO (7 << HPM_PCFG_DCDC_MODE_MODE_SHIFT) + +#define HPM_PCFG_DCDC_MODE_READY_SHIFT (28) +#define HPM_PCFG_DCDC_MODE_READY_NOT_READY (0 << HPM_PCFG_DCDC_MODE_READY_SHIFT) +#define HPM_PCFG_DCDC_MODE_READY_READY (1 << HPM_PCFG_DCDC_MODE_READY_SHIFT) + +#define HPM_PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT (0) +#define HPM_PCFG_DCDC_LPMODE_STBY_VOLT_MASK (0x7FF << HPM_PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) +#define HPM_PCFG_DCDC_LPMODE_STBY_VOLT(n) ((n) << HPM_PCFG_DCDC_LPMODE_STBY_VOLT_SHIFT) + +#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PCFG_H */ diff --git a/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pinmux.h b/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pinmux.h new file mode 100644 index 0000000000000..e2b4d55743664 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pinmux.h @@ -0,0 +1,112 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_pinmux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PINMUX_H +#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PINMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hpm_ioc.h" +#include "hpm_gpio.h" + +#define GPIO_UART0_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA30_INDEX)) +#define GPIO_UART0_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB22_INDEX)) +#define GPIO_UART0_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC22_INDEX)) +#define GPIO_UART0_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PY06_INDEX)) + +#define GPIO_UART0_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA31_INDEX)) +#define GPIO_UART0_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB23_INDEX)) +#define GPIO_UART0_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC23_INDEX)) +#define GPIO_UART0_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PY07_INDEX)) + +#define GPIO_UART1_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA00_INDEX)) +#define GPIO_UART1_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB00_INDEX)) +#define GPIO_UART1_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB24_INDEX)) +#define GPIO_UART1_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC24_INDEX)) + +#define GPIO_UART1_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA01_INDEX)) +#define GPIO_UART1_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB01_INDEX)) +#define GPIO_UART1_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB25_INDEX)) +#define GPIO_UART1_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC25_INDEX)) + +#define GPIO_UART2_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA02_INDEX)) +#define GPIO_UART2_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB02_INDEX)) +#define GPIO_UART2_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB26_INDEX)) +#define GPIO_UART2_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC26_INDEX)) + +#define GPIO_UART2_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA03_INDEX)) +#define GPIO_UART2_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB03_INDEX)) +#define GPIO_UART2_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB27_INDEX)) +#define GPIO_UART2_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC27_INDEX)) + +#define GPIO_UART3_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA04_INDEX)) +#define GPIO_UART3_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB04_INDEX)) +#define GPIO_UART3_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB28_INDEX)) +#define GPIO_UART3_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ00_INDEX)) + +#define GPIO_UART3_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA05_INDEX)) +#define GPIO_UART3_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB05_INDEX)) +#define GPIO_UART3_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB28_INDEX)) +#define GPIO_UART3_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ01_INDEX)) + +#define GPIO_UART4_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA14_INDEX)) +#define GPIO_UART4_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB06_INDEX)) +#define GPIO_UART4_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC06_INDEX)) +#define GPIO_UART4_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ02_INDEX)) + +#define GPIO_UART4_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA15_INDEX)) +#define GPIO_UART4_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB07_INDEX)) +#define GPIO_UART4_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC07_INDEX)) +#define GPIO_UART4_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ03_INDEX)) + +#define GPIO_UART5_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA16_INDEX)) +#define GPIO_UART5_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB08_INDEX)) +#define GPIO_UART5_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC08_INDEX)) +#define GPIO_UART5_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ04_INDEX)) + +#define GPIO_UART5_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA17_INDEX)) +#define GPIO_UART5_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB09_INDEX)) +#define GPIO_UART5_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC09_INDEX)) +#define GPIO_UART5_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ05_INDEX)) + +#define GPIO_UART6_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA18_INDEX)) +#define GPIO_UART6_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB10_INDEX)) +#define GPIO_UART6_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC10_INDEX)) +#define GPIO_UART6_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ06_INDEX)) + +#define GPIO_UART6_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA19_INDEX)) +#define GPIO_UART6_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB11_INDEX)) +#define GPIO_UART6_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC11_INDEX)) +#define GPIO_UART6_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PZ07_INDEX)) + +#define GPIO_UART7_TXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA20_INDEX)) +#define GPIO_UART7_TXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB12_INDEX)) +#define GPIO_UART7_TXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC12_INDEX)) +#define GPIO_UART7_TXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PY04_INDEX)) + +#define GPIO_UART7_RXD1 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PA21_INDEX)) +#define GPIO_UART7_RXD2 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PB13_INDEX)) +#define GPIO_UART7_RXD3 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PC13_INDEX)) +#define GPIO_UART7_RXD4 (GPIO_PERIPH | PAD_ALT2 | GPIO_PADMUX(HPM_IOC_PAD_PY05_INDEX)) + +#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_PINMUX_H */ diff --git a/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_sysctl.h b/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_sysctl.h new file mode 100644 index 0000000000000..489dedb0525c0 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_sysctl.h @@ -0,0 +1,693 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hardware/hpm6300/hpm6300_sysctl.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_SYSCTL_H +#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_SYSCTL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hpm6300_memorymap.h" + +#define HPM_SYSCTL_RESOURCE_CPU0 (HPM_SYSCTL_BASE + 0x0000) +#define HPM_SYSCTL_RESOURCE_CPX0 (HPM_SYSCTL_BASE + 0x0004) +#define HPM_SYSCTL_RESOURCE_POW_CPU0 (HPM_SYSCTL_BASE + 0x0054) +#define HPM_SYSCTL_RESOURCE_RST_SOC (HPM_SYSCTL_BASE + 0x0058) +#define HPM_SYSCTL_RESOURCE_RST_CPU0 (HPM_SYSCTL_BASE + 0x005c) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_XTAL (HPM_SYSCTL_BASE + 0x0080) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_PLL0 (HPM_SYSCTL_BASE + 0x0084) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (HPM_SYSCTL_BASE + 0x0088) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (HPM_SYSCTL_BASE + 0x008c) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0 (HPM_SYSCTL_BASE + 0x0090) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_PLL1 (HPM_SYSCTL_BASE + 0x0094) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (HPM_SYSCTL_BASE + 0x0098) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (HPM_SYSCTL_BASE + 0x009c) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_PLL2 (HPM_SYSCTL_BASE + 0x00a0) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2 (HPM_SYSCTL_BASE + 0x00a4) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2 (HPM_SYSCTL_BASE + 0x00a8) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (HPM_SYSCTL_BASE + 0x00ac) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (HPM_SYSCTL_BASE + 0x00b0) +#define HPM_SYSCTL_RESOURCE_CLK_SRC_PLL2_REF (HPM_SYSCTL_BASE + 0x00b4) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_CPU0 (HPM_SYSCTL_BASE + 0x0100) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_MCT0 (HPM_SYSCTL_BASE + 0x0104) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_FEMC (HPM_SYSCTL_BASE + 0x0108) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_XPI0 (HPM_SYSCTL_BASE + 0x010c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_XPI1 (HPM_SYSCTL_BASE + 0x0110) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_TMR0 (HPM_SYSCTL_BASE + 0x0114) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_TMR1 (HPM_SYSCTL_BASE + 0x0118) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_TMR2 (HPM_SYSCTL_BASE + 0x011c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_TMR3 (HPM_SYSCTL_BASE + 0x0120) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART0 (HPM_SYSCTL_BASE + 0x0124) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART1 (HPM_SYSCTL_BASE + 0x0128) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART2 (HPM_SYSCTL_BASE + 0x012c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART3 (HPM_SYSCTL_BASE + 0x0130) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART4 (HPM_SYSCTL_BASE + 0x0134) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART5 (HPM_SYSCTL_BASE + 0x0138) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART6 (HPM_SYSCTL_BASE + 0x013c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_UART7 (HPM_SYSCTL_BASE + 0x0140) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_I2C0 (HPM_SYSCTL_BASE + 0x0144) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_IC21 (HPM_SYSCTL_BASE + 0x0148) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_IC22 (HPM_SYSCTL_BASE + 0x014c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_IC23 (HPM_SYSCTL_BASE + 0x0150) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_SPI0 (HPM_SYSCTL_BASE + 0x0154) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_SPI1 (HPM_SYSCTL_BASE + 0x0158) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_SPI2 (HPM_SYSCTL_BASE + 0x015c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_SPI3 (HPM_SYSCTL_BASE + 0x0160) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_CAN0 (HPM_SYSCTL_BASE + 0x0164) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_CAN1 (HPM_SYSCTL_BASE + 0x0168) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_PTPC (HPM_SYSCTL_BASE + 0x016c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_ANA0 (HPM_SYSCTL_BASE + 0x0170) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_ANA1 (HPM_SYSCTL_BASE + 0x0174) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_ANA2 (HPM_SYSCTL_BASE + 0x0178) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_ANA3 (HPM_SYSCTL_BASE + 0x017c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_AUD0 (HPM_SYSCTL_BASE + 0x0180) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_AUD1 (HPM_SYSCTL_BASE + 0x0184) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_ETH0 (HPM_SYSCTL_BASE + 0x0188) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_PTP0 (HPM_SYSCTL_BASE + 0x018c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_REF0 (HPM_SYSCTL_BASE + 0x0190) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_REF1 (HPM_SYSCTL_BASE + 0x0194) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_NTM0 (HPM_SYSCTL_BASE + 0x0198) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_SDC0 (HPM_SYSCTL_BASE + 0x019c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_ADC0 (HPM_SYSCTL_BASE + 0x0200) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_ADC1 (HPM_SYSCTL_BASE + 0x0204) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_ADC2 (HPM_SYSCTL_BASE + 0x0208) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_DAC0 (HPM_SYSCTL_BASE + 0x020c) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_I2S0 (HPM_SYSCTL_BASE + 0x0210) +#define HPM_SYSCTL_RESOURCE_CLK_TOP_I2S1 (HPM_SYSCTL_BASE + 0x0214) +#define HPM_SYSCTL_RESOURCE_AHBP (HPM_SYSCTL_BASE + 0x0400) +#define HPM_SYSCTL_RESOURCE_AXIS (HPM_SYSCTL_BASE + 0x0404) +#define HPM_SYSCTL_RESOURCE_AXIC (HPM_SYSCTL_BASE + 0x0408) +#define HPM_SYSCTL_RESOURCE_FEMC (HPM_SYSCTL_BASE + 0x040c) +#define HPM_SYSCTL_RESOURCE_ROM0 (HPM_SYSCTL_BASE + 0x0410) +#define HPM_SYSCTL_RESOURCE_LMM0 (HPM_SYSCTL_BASE + 0x0414) +#define HPM_SYSCTL_RESOURCE_RAM0 (HPM_SYSCTL_BASE + 0x0418) +#define HPM_SYSCTL_RESOURCE_MCT0 (HPM_SYSCTL_BASE + 0x041c) +#define HPM_SYSCTL_RESOURCE_XPI0 (HPM_SYSCTL_BASE + 0x0420) +#define HPM_SYSCTL_RESOURCE_XPI1 (HPM_SYSCTL_BASE + 0x0424) +#define HPM_SYSCTL_RESOURCE_SDP0 (HPM_SYSCTL_BASE + 0x0428) +#define HPM_SYSCTL_RESOURCE_RNG0 (HPM_SYSCTL_BASE + 0x042c) +#define HPM_SYSCTL_RESOURCE_KMAN (HPM_SYSCTL_BASE + 0x0430) +#define HPM_SYSCTL_RESOURCE_DMA0 (HPM_SYSCTL_BASE + 0x0434) +#define HPM_SYSCTL_RESOURCE_DMA1 (HPM_SYSCTL_BASE + 0x0438) +#define HPM_SYSCTL_RESOURCE_FFA0 (HPM_SYSCTL_BASE + 0x043c) +#define HPM_SYSCTL_RESOURCE_GPIO (HPM_SYSCTL_BASE + 0x0440) +#define HPM_SYSCTL_RESOURCE_MBX0 (HPM_SYSCTL_BASE + 0x0444) +#define HPM_SYSCTL_RESOURCE_WDG0 (HPM_SYSCTL_BASE + 0x0448) +#define HPM_SYSCTL_RESOURCE_WDG1 (HPM_SYSCTL_BASE + 0x044c) +#define HPM_SYSCTL_RESOURCE_TSNS (HPM_SYSCTL_BASE + 0x0450) +#define HPM_SYSCTL_RESOURCE_TMR0 (HPM_SYSCTL_BASE + 0x0454) +#define HPM_SYSCTL_RESOURCE_TMR1 (HPM_SYSCTL_BASE + 0x0458) +#define HPM_SYSCTL_RESOURCE_RMR2 (HPM_SYSCTL_BASE + 0x045c) +#define HPM_SYSCTL_RESOURCE_TMR3 (HPM_SYSCTL_BASE + 0x0460) +#define HPM_SYSCTL_RESOURCE_URT0 (HPM_SYSCTL_BASE + 0x0464) +#define HPM_SYSCTL_RESOURCE_URT1 (HPM_SYSCTL_BASE + 0x0468) +#define HPM_SYSCTL_RESOURCE_URT2 (HPM_SYSCTL_BASE + 0x046c) +#define HPM_SYSCTL_RESOURCE_URT3 (HPM_SYSCTL_BASE + 0x0470) +#define HPM_SYSCTL_RESOURCE_URT4 (HPM_SYSCTL_BASE + 0x0474) +#define HPM_SYSCTL_RESOURCE_URT5 (HPM_SYSCTL_BASE + 0x0478) +#define HPM_SYSCTL_RESOURCE_URT6 (HPM_SYSCTL_BASE + 0x047c) +#define HPM_SYSCTL_RESOURCE_URT7 (HPM_SYSCTL_BASE + 0x0480) +#define HPM_SYSCTL_RESOURCE_I2C0 (HPM_SYSCTL_BASE + 0x0484) +#define HPM_SYSCTL_RESOURCE_I2C1 (HPM_SYSCTL_BASE + 0x0488) +#define HPM_SYSCTL_RESOURCE_I2C2 (HPM_SYSCTL_BASE + 0x048c) +#define HPM_SYSCTL_RESOURCE_I2C3 (HPM_SYSCTL_BASE + 0x0490) +#define HPM_SYSCTL_RESOURCE_SPI0 (HPM_SYSCTL_BASE + 0x0494) +#define HPM_SYSCTL_RESOURCE_SPI1 (HPM_SYSCTL_BASE + 0x0498) +#define HPM_SYSCTL_RESOURCE_SPI2 (HPM_SYSCTL_BASE + 0x049c) +#define HPM_SYSCTL_RESOURCE_SPI3 (HPM_SYSCTL_BASE + 0x04a0) +#define HPM_SYSCTL_RESOURCE_CAN0 (HPM_SYSCTL_BASE + 0x04a4) +#define HPM_SYSCTL_RESOURCE_CAN1 (HPM_SYSCTL_BASE + 0x04a8) +#define HPM_SYSCTL_RESOURCE_PTPC (HPM_SYSCTL_BASE + 0x04ac) +#define HPM_SYSCTL_RESOURCE_ADC0 (HPM_SYSCTL_BASE + 0x04b0) +#define HPM_SYSCTL_RESOURCE_ADC1 (HPM_SYSCTL_BASE + 0x04b4) +#define HPM_SYSCTL_RESOURCE_ADC2 (HPM_SYSCTL_BASE + 0x04b8) +#define HPM_SYSCTL_RESOURCE_DAC0 (HPM_SYSCTL_BASE + 0x04bc) +#define HPM_SYSCTL_RESOURCE_ACMP (HPM_SYSCTL_BASE + 0x04c0) +#define HPM_SYSCTL_RESOURCE_I2S0 (HPM_SYSCTL_BASE + 0x04c4) +#define HPM_SYSCTL_RESOURCE_I2S1 (HPM_SYSCTL_BASE + 0x04c8) +#define HPM_SYSCTL_RESOURCE_PDM0 (HPM_SYSCTL_BASE + 0x04cc) +#define HPM_SYSCTL_RESOURCE_DAO (HPM_SYSCTL_BASE + 0x04d0) +#define HPM_SYSCTL_RESOURCE_MSYN (HPM_SYSCTL_BASE + 0x04d4) +#define HPM_SYSCTL_RESOURCE_MOT0 (HPM_SYSCTL_BASE + 0x04d8) +#define HPM_SYSCTL_RESOURCE_MOT1 (HPM_SYSCTL_BASE + 0x04dc) +#define HPM_SYSCTL_RESOURCE_ETH0 (HPM_SYSCTL_BASE + 0x04e0) +#define HPM_SYSCTL_RESOURCE_NTM0 (HPM_SYSCTL_BASE + 0x04e4) +#define HPM_SYSCTL_RESOURCE_SDC0 (HPM_SYSCTL_BASE + 0x04e8) +#define HPM_SYSCTL_RESOURCE_USB0 (HPM_SYSCTL_BASE + 0x04ec) +#define HPM_SYSCTL_RESOURCE_REF0 (HPM_SYSCTL_BASE + 0x04f0) +#define HPM_SYSCTL_RESOURCE_REF1 (HPM_SYSCTL_BASE + 0x04f4) +#define HPM_SYSCTL_GROUP0_LINK0_VALUE (HPM_SYSCTL_BASE + 0x0800) +#define HPM_SYSCTL_GROUP0_LINK0_SET (HPM_SYSCTL_BASE + 0x0804) +#define HPM_SYSCTL_GROUP0_LINK0_CLEAR (HPM_SYSCTL_BASE + 0x0808) +#define HPM_SYSCTL_GROUP0_LINK0_TOGGLE (HPM_SYSCTL_BASE + 0x080c) +#define HPM_SYSCTL_GROUP0_LINK1_VALUE (HPM_SYSCTL_BASE + 0x0810) +#define HPM_SYSCTL_GROUP0_LINK1_SET (HPM_SYSCTL_BASE + 0x0814) +#define HPM_SYSCTL_GROUP0_LINK1_CLEAR (HPM_SYSCTL_BASE + 0x0818) +#define HPM_SYSCTL_GROUP0_LINK1_TOGGLE (HPM_SYSCTL_BASE + 0x081c) +#define HPM_SYSCTL_AFFILIATE_CPU0_VALUE (HPM_SYSCTL_BASE + 0x0900) +#define HPM_SYSCTL_AFFILIATE_CPU0_SET (HPM_SYSCTL_BASE + 0x0904) +#define HPM_SYSCTL_AFFILIATE_CPU0_CLEAR (HPM_SYSCTL_BASE + 0x0908) +#define HPM_SYSCTL_AFFILIATE_CPU0_TOGGLE (HPM_SYSCTL_BASE + 0x090c) +#define HPM_SYSCTL_RETENTION_CPU0_VALUE (HPM_SYSCTL_BASE + 0x0920) +#define HPM_SYSCTL_RETENTION_CPU0_SET (HPM_SYSCTL_BASE + 0x0924) +#define HPM_SYSCTL_RETENTION_CPU0_CLEAR (HPM_SYSCTL_BASE + 0x0928) +#define HPM_SYSCTL_RETENTION_CPU0_TOGGLE (HPM_SYSCTL_BASE + 0x092c) +#define HPM_SYSCTL_POWER_CPU0_STATUS (HPM_SYSCTL_BASE + 0x1000) +#define HPM_SYSCTL_POWER_CPU0_LF_WAIT (HPM_SYSCTL_BASE + 0x1004) +#define HPM_SYSCTL_POWER_CPU0_OFF_WAIT (HPM_SYSCTL_BASE + 0x100c) +#define HPM_SYSCTL_RESET_SOC_CONTROL (HPM_SYSCTL_BASE + 0x1400) +#define HPM_SYSCTL_RESET_SOC_CONFIG (HPM_SYSCTL_BASE + 0x1404) +#define HPM_SYSCTL_RESET_SOC_COUNTER (HPM_SYSCTL_BASE + 0x140c) +#define HPM_SYSCTL_RESET_CPU0_CONTROL (HPM_SYSCTL_BASE + 0x1410) +#define HPM_SYSCTL_RESET_CPU0_CONFIG (HPM_SYSCTL_BASE + 0x1414) +#define HPM_SYSCTL_RESET_CPU0_COUNTER (HPM_SYSCTL_BASE + 0x141c) +#define HPM_SYSCTL_CLOCK_CPU_CLK_TOP_CPU0 (HPM_SYSCTL_BASE + 0x1800) +#define HPM_SYSCTL_CLOCK_CLK_TOP_MCT0 (HPM_SYSCTL_BASE + 0x1804) +#define HPM_SYSCTL_CLOCK_CLK_TOP_FEMC (HPM_SYSCTL_BASE + 0x1808) +#define HPM_SYSCTL_CLOCK_CLK_TOP_XPI0 (HPM_SYSCTL_BASE + 0x180c) +#define HPM_SYSCTL_CLOCK_CLK_TOP_XPI1 (HPM_SYSCTL_BASE + 0x1810) +#define HPM_SYSCTL_CLOCK_CLK_TOP_TMR0 (HPM_SYSCTL_BASE + 0x1814) +#define HPM_SYSCTL_CLOCK_CLK_TOP_TMR1 (HPM_SYSCTL_BASE + 0x1818) +#define HPM_SYSCTL_CLOCK_CLK_TOP_TMR2 (HPM_SYSCTL_BASE + 0x181c) +#define HPM_SYSCTL_CLOCK_CLK_TOP_TMR3 (HPM_SYSCTL_BASE + 0x1820) +#define HPM_SYSCTL_CLOCK_CLK_TOP_UART0 (HPM_SYSCTL_BASE + 0x1824) +#define HPM_SYSCTL_CLOCK_CLK_TOP_UART1 (HPM_SYSCTL_BASE + 0x1828) +#define HPM_SYSCTL_CLOCK_CLK_TOP_UART2 (HPM_SYSCTL_BASE + 0x182c) +#define HPM_SYSCTL_CLOCK_CLK_TOP_UART3 (HPM_SYSCTL_BASE + 0x1830) +#define HPM_SYSCTL_CLOCK_CLK_TOP_UART4 (HPM_SYSCTL_BASE + 0x1834) +#define HPM_SYSCTL_CLOCK_CLK_TOP_UART5 (HPM_SYSCTL_BASE + 0x1838) +#define HPM_SYSCTL_CLOCK_CLK_TOP_UART6 (HPM_SYSCTL_BASE + 0x183c) +#define HPM_SYSCTL_CLOCK_CLK_TOP_UART7 (HPM_SYSCTL_BASE + 0x1840) +#define HPM_SYSCTL_CLOCK_CLK_TOP_I2C0 (HPM_SYSCTL_BASE + 0x1844) +#define HPM_SYSCTL_CLOCK_CLK_TOP_IC21 (HPM_SYSCTL_BASE + 0x1848) +#define HPM_SYSCTL_CLOCK_CLK_TOP_IC22 (HPM_SYSCTL_BASE + 0x184c) +#define HPM_SYSCTL_CLOCK_CLK_TOP_IC23 (HPM_SYSCTL_BASE + 0x1850) +#define HPM_SYSCTL_CLOCK_CLK_TOP_SPI0 (HPM_SYSCTL_BASE + 0x1854) +#define HPM_SYSCTL_CLOCK_CLK_TOP_SPI1 (HPM_SYSCTL_BASE + 0x1858) +#define HPM_SYSCTL_CLOCK_CLK_TOP_SPI2 (HPM_SYSCTL_BASE + 0x185c) +#define HPM_SYSCTL_CLOCK_CLK_TOP_SPI3 (HPM_SYSCTL_BASE + 0x1860) +#define HPM_SYSCTL_CLOCK_CLK_TOP_CAN0 (HPM_SYSCTL_BASE + 0x1864) +#define HPM_SYSCTL_CLOCK_CLK_TOP_CAN1 (HPM_SYSCTL_BASE + 0x1868) +#define HPM_SYSCTL_CLOCK_CLK_TOP_PTPC (HPM_SYSCTL_BASE + 0x186c) +#define HPM_SYSCTL_CLOCK_CLK_TOP_ANA0 (HPM_SYSCTL_BASE + 0x1870) +#define HPM_SYSCTL_CLOCK_CLK_TOP_ANA1 (HPM_SYSCTL_BASE + 0x1874) +#define HPM_SYSCTL_CLOCK_CLK_TOP_ANA2 (HPM_SYSCTL_BASE + 0x1878) +#define HPM_SYSCTL_CLOCK_CLK_TOP_ANA3 (HPM_SYSCTL_BASE + 0x187c) +#define HPM_SYSCTL_CLOCK_CLK_TOP_AUD0 (HPM_SYSCTL_BASE + 0x1880) +#define HPM_SYSCTL_CLOCK_CLK_TOP_AUD1 (HPM_SYSCTL_BASE + 0x1884) +#define HPM_SYSCTL_CLOCK_CLK_TOP_ETH0 (HPM_SYSCTL_BASE + 0x1888) +#define HPM_SYSCTL_CLOCK_CLK_TOP_PTP0 (HPM_SYSCTL_BASE + 0x188c) +#define HPM_SYSCTL_CLOCK_CLK_TOP_REF0 (HPM_SYSCTL_BASE + 0x1890) +#define HPM_SYSCTL_CLOCK_CLK_TOP_REF1 (HPM_SYSCTL_BASE + 0x1894) +#define HPM_SYSCTL_CLOCK_CLK_TOP_NTM0 (HPM_SYSCTL_BASE + 0x1898) +#define HPM_SYSCTL_CLOCK_CLK_TOP_SDC0 (HPM_SYSCTL_BASE + 0x189c) +#define HPM_SYSCTL_ADCCLK_CLK_TOP_ADC0 (HPM_SYSCTL_BASE + 0x1c00) +#define HPM_SYSCTL_ADCCLK_CLK_TOP_ADC1 (HPM_SYSCTL_BASE + 0x1c04) +#define HPM_SYSCTL_ADCCLK_CLK_TOP_ADC2 (HPM_SYSCTL_BASE + 0x1c08) +#define HPM_SYSCTL_ADCCLK_CLK_TOP_DAC0 (HPM_SYSCTL_BASE + 0x1c0c) +#define HPM_SYSCTL_I2SCLK_CLK_TOP_I2S0 (HPM_SYSCTL_BASE + 0x1c10) +#define HPM_SYSCTL_I2SCLK_CLK_TOP_I2S1 (HPM_SYSCTL_BASE + 0x1c14) +#define HPM_SYSCTL_GLOBAL00 (HPM_SYSCTL_BASE + 0x2000) +#define HPM_SYSCTL_MONITOR_SLICE0_CONTROL (HPM_SYSCTL_BASE + 0x2400) +#define HPM_SYSCTL_MONITOR_SLICE0_CURRENT (HPM_SYSCTL_BASE + 0x2404) +#define HPM_SYSCTL_MONITOR_SLICE0_LOW_LIMIT (HPM_SYSCTL_BASE + 0x2408) +#define HPM_SYSCTL_MONITOR_SLICE0_HIGH_LIMIT (HPM_SYSCTL_BASE + 0x240c) +#define HPM_SYSCTL_MONITOR_SLICE1_CONTROL (HPM_SYSCTL_BASE + 0x2420) +#define HPM_SYSCTL_MONITOR_SLICE1_CURRENT (HPM_SYSCTL_BASE + 0x2424) +#define HPM_SYSCTL_MONITOR_SLICE1_LOW_LIMIT (HPM_SYSCTL_BASE + 0x2428) +#define HPM_SYSCTL_MONITOR_SLICE1_HIGH_LIMIT (HPM_SYSCTL_BASE + 0x242c) +#define HPM_SYSCTL_MONITOR_SLICE2_CONTROL (HPM_SYSCTL_BASE + 0x2440) +#define HPM_SYSCTL_MONITOR_SLICE2_CURRENT (HPM_SYSCTL_BASE + 0x2444) +#define HPM_SYSCTL_MONITOR_SLICE2_LOW_LIMIT (HPM_SYSCTL_BASE + 0x2448) +#define HPM_SYSCTL_MONITOR_SLICE2_HIGH_LIMIT (HPM_SYSCTL_BASE + 0x244c) +#define HPM_SYSCTL_MONITOR_SLICE3_CONTROL (HPM_SYSCTL_BASE + 0x2460) +#define HPM_SYSCTL_MONITOR_SLICE3_CURRENT (HPM_SYSCTL_BASE + 0x2464) +#define HPM_SYSCTL_MONITOR_SLICE3_LOW_LIMIT (HPM_SYSCTL_BASE + 0x2468) +#define HPM_SYSCTL_MONITOR_SLICE3_HIGH_LIMIT (HPM_SYSCTL_BASE + 0x246c) +#define HPM_SYSCTL_CPU_CPU0_LP (HPM_SYSCTL_BASE + 0x2800) +#define HPM_SYSCTL_CPU_CPU0_LOCK (HPM_SYSCTL_BASE + 0x2804) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR0 (HPM_SYSCTL_BASE + 0x2808) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR1 (HPM_SYSCTL_BASE + 0x280c) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR2 (HPM_SYSCTL_BASE + 0x2810) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR3 (HPM_SYSCTL_BASE + 0x2814) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR4 (HPM_SYSCTL_BASE + 0x2818) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR5 (HPM_SYSCTL_BASE + 0x281c) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR6 (HPM_SYSCTL_BASE + 0x2820) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR7 (HPM_SYSCTL_BASE + 0x2824) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR8 (HPM_SYSCTL_BASE + 0x2828) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR9 (HPM_SYSCTL_BASE + 0x282c) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR10 (HPM_SYSCTL_BASE + 0x2830) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR11 (HPM_SYSCTL_BASE + 0x2834) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR12 (HPM_SYSCTL_BASE + 0x2838) +#define HPM_SYSCTL_CPU_CPU0_GPR_GPR13 (HPM_SYSCTL_BASE + 0x283c) +#define HPM_SYSCTL_CPU_CPU0_WAKEUP_STATUS_STATUS0 (HPM_SYSCTL_BASE + 0x2840) +#define HPM_SYSCTL_CPU_CPU0_WAKEUP_STATUS_STATUS1 (HPM_SYSCTL_BASE + 0x2844) +#define HPM_SYSCTL_CPU_CPU0_WAKEUP_STATUS_STATUS2 (HPM_SYSCTL_BASE + 0x2848) +#define HPM_SYSCTL_CPU_CPU0_WAKEUP_STATUS_STATUS3 (HPM_SYSCTL_BASE + 0x284c) +#define HPM_SYSCTL_CPU_CPU0_WAKEUP_ENABLE_ENABLE0 (HPM_SYSCTL_BASE + 0x2880) +#define HPM_SYSCTL_CPU_CPU0_WAKEUP_ENABLE_ENABLE1 (HPM_SYSCTL_BASE + 0x2884) +#define HPM_SYSCTL_CPU_CPU0_WAKEUP_ENABLE_ENABLE2 (HPM_SYSCTL_BASE + 0x2888) +#define HPM_SYSCTL_CPU_CPU0_WAKEUP_ENABLE_ENABLE3 (HPM_SYSCTL_BASE + 0x288c) + +#define SYSCTL_RESOURCE_GLB_BUSY (1 << 31) +#define SYSCTL_RESOURCE_LOC_BUSY (1 << 30) +#define SYSCTL_RESOURCE_MODE_SHIFT (0U) +#define SYSCTL_RESOURCE_MODE_MASK (0x3U << SYSCTL_RESOURCE_MODE_SHIFT) +# define SYSCTL_RESOURCE_MODE_AUTO (0 << SYSCTL_RESOURCE_MODE_SHIFT) +# define SYSCTL_RESOURCE_MODE_ON (1 << SYSCTL_RESOURCE_MODE_SHIFT) +# define SYSCTL_RESOURCE_MODE_OFF (2 << SYSCTL_RESOURCE_MODE_SHIFT) +# define SYSCTL_RESOURCE_MODE_RESV (3 << SYSCTL_RESOURCE_MODE_SHIFT) + +#define SYSCTL_GROUP0(n) (1U << (n)) + +#define SYSCTL_AFFILIATE(n) (1U << (n)) + +#define SYSCTL_RETENTION_LINK_SHIFT (0) +#define SYSCTL_RETENTION_LINK_MASK (0xffU << SYSCTL_RETENTION_LINK_SHIFT) +# define SYSCTL_RETENTION_LINK_SOC_RAM (0 << SYSCTL_RETENTION_LINK_SHIFT) +# define SYSCTL_RETENTION_LINK_PERIPH_REG (1 << SYSCTL_RETENTION_LINK_SHIFT) +# define SYSCTL_RETENTION_LINK_CPU0_RAM (2 << SYSCTL_RETENTION_LINK_SHIFT) +# define SYSCTL_RETENTION_LINK_CPU0_REG (3 << SYSCTL_RETENTION_LINK_SHIFT) +# define SYSCTL_RETENTION_LINK_XTAL (4 << SYSCTL_RETENTION_LINK_SHIFT) +# define SYSCTL_RETENTION_LINK_PLL0 (5 << SYSCTL_RETENTION_LINK_SHIFT) +# define SYSCTL_RETENTION_LINK_PLL1 (6 << SYSCTL_RETENTION_LINK_SHIFT) +# define SYSCTL_RETENTION_LINK_PLL2 (7 << SYSCTL_RETENTION_LINK_SHIFT) + +#define SYSCTL_POWER_STATUS_FLAG (1 << 31) +#define SYSCTL_POWER_STATUS_FLAG_WAKE (1 << 30) +#define SYSCTL_POWER_LF_DISABLE (1 << 12) +#define SYSCTL_POWER_LF_ACK (1 << 8) + +#define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0) +#define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xfffffU << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) +#define SYSCTL_POWER_LF_WAIT_WAIT(n) ((n) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) + +#define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0) +#define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xfffffU << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) +#define SYSCTL_POWER_OFF_WAIT_WAIT(n) ((n) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) + +#define SYSCTL_RESET_CONTROL_FLAG (1 << 31) +#define SYSCTL_RESET_CONTROL_FLAG_WAKE (1 << 30) +#define SYSCTL_RESET_CONTROL_HOLD (1 << 4) +#define SYSCTL_RESET_CONTROL_RESET (1 << 0) + +#define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16) +#define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xffU << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) +#define SYSCTL_RESET_CONFIG_PRE_WAIT(n) ((n) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xffU << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) +#define SYSCTL_RESET_CONFIG_RSTCLK_NUM(n) ((n) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) +#define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0) +#define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xffU << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) +#define SYSCTL_RESET_CONFIG_POST_WAIT(n) ((n) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) + +#define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0) +#define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xfffffU << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) +#define SYSCTL_RESET_COUNTER_COUNTER(n) ((n) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) + +#define SYSCTL_CLOCK_CPU_GLB_BUSY (1 << 31) +#define SYSCTL_CLOCK_CPU_LOC_BUSY (1 << 30) +#define SYSCTL_CLOCK_CPU_PRESERVE (1 << 28) +#define SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT (20) +#define SYSCTL_CLOCK_CPU_SUB1_DIV_MASK (0xfU << SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT) +#define SYSCTL_CLOCK_CPU_SUB1_DIV(n) ((n) << SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT (16) +#define SYSCTL_CLOCK_CPU_SUB0_DIV_MASK (0xfU << SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) +#define SYSCTL_CLOCK_CPU_SUB0_DIV(n) ((n) << SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) +#define SYSCTL_CLOCK_CPU_MUX_SHIFT (8) +#define SYSCTL_CLOCK_CPU_MUX_MASK (0xfU << SYSCTL_CLOCK_CPU_MUX_SHIFT) +# define SYSCTL_CLOCK_CPU_MUX_OSC0_CLK0 (0 << SYSCTL_CLOCK_CPU_MUX_SHIFT) +# define SYSCTL_CLOCK_CPU_MUX_PLL0_CLK0 (1 << SYSCTL_CLOCK_CPU_MUX_SHIFT) +# define SYSCTL_CLOCK_CPU_MUX_PLL0_CLK1 (2 << SYSCTL_CLOCK_CPU_MUX_SHIFT) +# define SYSCTL_CLOCK_CPU_MUX_PLL0_CLK2 (3 << SYSCTL_CLOCK_CPU_MUX_SHIFT) +# define SYSCTL_CLOCK_CPU_MUX_PLL1_CLK0 (4 << SYSCTL_CLOCK_CPU_MUX_SHIFT) +# define SYSCTL_CLOCK_CPU_MUX_PLL1_CLK1 (5 << SYSCTL_CLOCK_CPU_MUX_SHIFT) +# define SYSCTL_CLOCK_CPU_MUX_PLL2_CLK0 (6 << SYSCTL_CLOCK_CPU_MUX_SHIFT) +# define SYSCTL_CLOCK_CPU_MUX_PLL2_CLK1 (7 << SYSCTL_CLOCK_CPU_MUX_SHIFT) +#define SYSCTL_CLOCK_CPU_DIV_SHIFT (0) +#define SYSCTL_CLOCK_CPU_DIV_MASK (0xffU << SYSCTL_CLOCK_CPU_DIV_SHIFT) +#define SYSCTL_CLOCK_CPU_DIV(n) ((n) << SYSCTL_CLOCK_CPU_DIV_SHIFT) + +#define SYSCTL_CLOCK_GLB_BUSY (1 << 31) +#define SYSCTL_CLOCK_LOC_BUSY (1 << 30) +#define SYSCTL_CLOCK_PRESERVE (1 << 28) +#define SYSCTL_CLOCK_SUB1_DIV_SHIFT (20) +#define SYSCTL_CLOCK_SUB1_DIV_MASK (0xfU << SYSCTL_CLOCK_SUB1_DIV_SHIFT) +#define SYSCTL_CLOCK_SUB1_DIV(n) ((n) << SYSCTL_CLOCK_SUB1_DIV_SHIFT) +#define SYSCTL_CLOCK_SUB0_DIV_SHIFT (16) +#define SYSCTL_CLOCK_SUB0_DIV_MASK (0xfU << SYSCTL_CLOCK_SUB0_DIV_SHIFT) +#define SYSCTL_CLOCK_SUB0_DIV(n) ((n) << SYSCTL_CLOCK_SUB0_DIV_SHIFT) +#define SYSCTL_CLOCK_MUX_SHIFT (8) +#define SYSCTL_CLOCK_MUX_MASK (0xfU << SYSCTL_CLOCK_MUX_SHIFT) +# define SYSCTL_CLOCK_MUX_OSC0_CLK0 (0 << SYSCTL_CLOCK_MUX_SHIFT) +# define SYSCTL_CLOCK_MUX_PLL0_CLK0 (1 << SYSCTL_CLOCK_MUX_SHIFT) +# define SYSCTL_CLOCK_MUX_PLL0_CLK1 (2 << SYSCTL_CLOCK_MUX_SHIFT) +# define SYSCTL_CLOCK_MUX_PLL0_CLK2 (3 << SYSCTL_CLOCK_MUX_SHIFT) +# define SYSCTL_CLOCK_MUX_PLL1_CLK0 (4 << SYSCTL_CLOCK_MUX_SHIFT) +# define SYSCTL_CLOCK_MUX_PLL1_CLK1 (5 << SYSCTL_CLOCK_MUX_SHIFT) +# define SYSCTL_CLOCK_MUX_PLL2_CLK0 (6 << SYSCTL_CLOCK_MUX_SHIFT) +# define SYSCTL_CLOCK_MUX_PLL2_CLK1 (7 << SYSCTL_CLOCK_MUX_SHIFT) +#define SYSCTL_CLOCK_DIV_SHIFT (0) +#define SYSCTL_CLOCK_DIV_MASK (0xffU << SYSCTL_CLOCK_DIV_SHIFT) +#define SYSCTL_CLOCK_DIV(n) ((n-1) << SYSCTL_CLOCK_DIV_SHIFT) + +#define SYSCTL_ADCCLK_GLB_BUSY (1 << 31) +#define SYSCTL_ADCCLK_LOC_BUSY (1 << 30) +#define SYSCTL_ADCCLK_PRESERVE (1 << 28) +#define SYSCTL_ADCCLK_MUX_ANA_CLOCK (0) +#define SYSCTL_ADCCLK_MUX_AHB_CLOCK (1 << 8) + +#define SYSCTL_DACCLK_GLB_BUSY (1 << 31) +#define SYSCTL_DACCLK_LOC_BUSY (1 << 30) +#define SYSCTL_DACCLK_PRESERVE (1 << 28) +#define SYSCTL_DACCLK_MUX_ANA_CLOCK (0) +#define SYSCTL_DACCLK_MUX_AHB_CLOCK (1 << 8) + +#define SYSCTL_DACCLK_GLB_BUSY (1 << 31) +#define SYSCTL_DACCLK_LOC_BUSY (1 << 30) +#define SYSCTL_DACCLK_PRESERVE (1 << 28) +#define SYSCTL_DACCLK_MUX_AUD_CLOCK0 (0) +#define SYSCTL_DACCLK_MUX_AUD_CLOCK1 (1 << 8) + +#define SYSCTL_GLOBAL00_MUX_SHIFT (0) +#define SYSCTL_GLOBAL00_MUX_MASK (3 << SYSCTL_GLOBAL00_MUX_SHIFT) +#define SYSCTL_GLOBAL00_MUX(n) ((n) << SYSCTL_GLOBAL00_MUX_SHIFT) +#define SYSCTL_GLOBAL00_MUX_24M (0) +#define SYSCTL_GLOBAL00_MUX_SUG (1 << 1) + +#define SYSCTL_MONITOR_CONTROL_VALID (1 << 31) +#define SYSCTL_MONITOR_CONTROL_DIV_BUSY (1 << 27) +#define SYSCTL_MONITOR_CONTROL_OUTEN (1 << 24) +#define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16) +#define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xffU << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) +#define SYSCTL_MONITOR_CONTROL_DIV(n) ((n) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) +#define SYSCTL_MONITOR_CONTROL_HIGH (1 << 15) +#define SYSCTL_MONITOR_CONTROL_LOW (1 << 14) +#define SYSCTL_MONITOR_CONTROL_START (1 << 12) +#define SYSCTL_MONITOR_CONTROL_MODE (1 << 10) +#define SYSCTL_MONITOR_CONTROL_ACCURACY (1 << 9) +#define SYSCTL_MONITOR_CONTROL_REFERENCE (1 << 8) +#define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0) +#define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xffU << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) +#define SYSCTL_MONITOR_CONTROL_SELECTION(n) ((n) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) + +#define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24) +#define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xffU << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) +#define SYSCTL_CPU_LP_WAKE_CNT_CLEAR (0) +#define SYSCTL_CPU_LP_HALT (1 << 16) +#define SYSCTL_CPU_LP_WAKE (1 << 13) +#define SYSCTL_CPU_LP_EXEC (1 << 12) +#define SYSCTL_CPU_LP_WAKE_FLAG (1 << 10) +#define SYSCTL_CPU_LP_SLEEP_FLAG (1 << 9) +#define SYSCTL_CPU_LP_RESET_FLAG (1 << 8) +#define SYSCTL_CPU_LP_MODE_SHIFT (0) +#define SYSCTL_CPU_LP_MODE_MASK (0x3 << SYSCTL_CPU_LP_MODE_SHIFT) +#define SYSCTL_CPU_LP_MODE_WAIT (0 << SYSCTL_CPU_LP_MODE_SHIFT) +#define SYSCTL_CPU_LP_MODE_HALT (1 << SYSCTL_CPU_LP_MODE_SHIFT) +#define SYSCTL_CPU_LP_MODE_RUN (2 << SYSCTL_CPU_LP_MODE_SHIFT) + +#define SYSCTL_CPU_LOCK_GPR_SHIFT (2) +#define SYSCTL_CPU_LOCK_GPR_MASK (0x3f << SYSCTL_CPU_LOCK_GPR_SHIFT) +#define SYSCTL_CPU_LOCK_LOCK (1 << 1) + +#define SYSCTL_CPU_GPR_GPR_MASK (0xffff) + +#define SYSCTL_CPU_WAKEUP_STATUS_MASK (0xffff) + +#define SYSCTL_CPU_WAKEUP_ENABLE_MASK (0xffff) + +#define SYSCTL_GROUP0_LINK0_AHBP (1 << 0) +#define SYSCTL_GROUP0_LINK0_AXIS (1 << 1) +#define SYSCTL_GROUP0_LINK0_AXIC (1 << 2) +#define SYSCTL_GROUP0_LINK0_FEMC (1 << 3) +#define SYSCTL_GROUP0_LINK0_ROM0 (1 << 4) +#define SYSCTL_GROUP0_LINK0_LMM0 (1 << 5) +#define SYSCTL_GROUP0_LINK0_RAM0 (1 << 6) +#define SYSCTL_GROUP0_LINK0_MCHTMR0 (1 << 7) +#define SYSCTL_GROUP0_LINK0_XPI0 (1 << 8) +#define SYSCTL_GROUP0_LINK0_XPI1 (1 << 9) +#define SYSCTL_GROUP0_LINK0_SDP0 (1 << 10) +#define SYSCTL_GROUP0_LINK0_RNG0 (1 << 11) +#define SYSCTL_GROUP0_LINK0_KMAN (1 << 12) +#define SYSCTL_GROUP0_LINK0_DMA0 (1 << 13) +#define SYSCTL_GROUP0_LINK0_DMA1 (1 << 14) +#define SYSCTL_GROUP0_LINK0_FFA0 (1 << 15) +#define SYSCTL_GROUP0_LINK0_GPIO (1 << 16) +#define SYSCTL_GROUP0_LINK0_MBX0 (1 << 17) +#define SYSCTL_GROUP0_LINK0_WDG0 (1 << 18) +#define SYSCTL_GROUP0_LINK0_WDG1 (1 << 19) +#define SYSCTL_GROUP0_LINK0_TSNS (1 << 20) +#define SYSCTL_GROUP0_LINK0_GPTMR0 (1 << 21) +#define SYSCTL_GROUP0_LINK0_GPTMR1 (1 << 22) +#define SYSCTL_GROUP0_LINK0_GPRMR2 (1 << 23) +#define SYSCTL_GROUP0_LINK0_GPTMR3 (1 << 24) +#define SYSCTL_GROUP0_LINK0_UART0 (1 << 25) +#define SYSCTL_GROUP0_LINK0_UART1 (1 << 26) +#define SYSCTL_GROUP0_LINK0_UART2 (1 << 27) +#define SYSCTL_GROUP0_LINK0_UART3 (1 << 28) +#define SYSCTL_GROUP0_LINK0_UART4 (1 << 29) +#define SYSCTL_GROUP0_LINK0_UART5 (1 << 30) +#define SYSCTL_GROUP0_LINK0_UART6 (1 << 11) +#define SYSCTL_GROUP0_LINK1_UART7 (1 << 0) +#define SYSCTL_GROUP0_LINK1_I2C0 (1 << 1) +#define SYSCTL_GROUP0_LINK1_I2C1 (1 << 2) +#define SYSCTL_GROUP0_LINK1_I2C2 (1 << 3) +#define SYSCTL_GROUP0_LINK1_I2C3 (1 << 4) +#define SYSCTL_GROUP0_LINK1_SPI0 (1 << 5) +#define SYSCTL_GROUP0_LINK1_SPI1 (1 << 6) +#define SYSCTL_GROUP0_LINK1_SPI2 (1 << 7) +#define SYSCTL_GROUP0_LINK1_SPI3 (1 << 8) +#define SYSCTL_GROUP0_LINK1_CAN0 (1 << 9) +#define SYSCTL_GROUP0_LINK1_CAN1 (1 << 10) +#define SYSCTL_GROUP0_LINK1_PTPC (1 << 11) +#define SYSCTL_GROUP0_LINK1_ADC0 (1 << 12) +#define SYSCTL_GROUP0_LINK1_ADC1 (1 << 13) +#define SYSCTL_GROUP0_LINK1_ADC2 (1 << 14) +#define SYSCTL_GROUP0_LINK1_DAC0 (1 << 15) +#define SYSCTL_GROUP0_LINK1_ACMP (1 << 16) +#define SYSCTL_GROUP0_LINK1_I2S0 (1 << 17) +#define SYSCTL_GROUP0_LINK1_I2S1 (1 << 18) +#define SYSCTL_GROUP0_LINK1_I2SPDM0 (1 << 19) +#define SYSCTL_GROUP0_LINK1_I2SDAO (1 << 20) +#define SYSCTL_GROUP0_LINK1_MSYN (1 << 21) +#define SYSCTL_GROUP0_LINK1_MOT0 (1 << 22) +#define SYSCTL_GROUP0_LINK1_MOT1 (1 << 23) +#define SYSCTL_GROUP0_LINK1_ETH0 (1 << 24) +#define SYSCTL_GROUP0_LINK1_NTMR0 (1 << 25) +#define SYSCTL_GROUP0_LINK1_SDXC0 (1 << 26) +#define SYSCTL_GROUP0_LINK1_USB0 (1 << 27) +#define SYSCTL_GROUP0_LINK1_REF0 (1 << 28) +#define SYSCTL_GROUP0_LINK1_REF1 (1 << 29) + +#define SYSCTL_RESOURCE_CPU0 (0) +#define SYSCTL_RESOURCE_CPX1 (1) +#define SYSCTL_RESOURCE_EXE0 (2) +#define SYSCTL_RESOURCE_WAK0 (3) +#define SYSCTL_RESOURCE_CPU0_PER (4) +#define SYSCTL_RESOURCE_LOGIC0 (16) +#define SYSCTL_RESOURCE_LOGIC1 (17) +#define SYSCTL_RESOURCE_LOGIC2 (18) +#define SYSCTL_RESOURCE_LOGIC3 (19) +#define SYSCTL_RESOURCE_PMIC (20) +#define SYSCTL_RESOURCE_POW_CPU0 (21) +#define SYSCTL_RESOURCE_RST_SOC (22) +#define SYSCTL_RESOURCE_RST_CPU0 (23) +#define SYSCTL_RESOURCE_XTAL (32) +#define SYSCTL_RESOURCE_PLL0 (33) +#define SYSCTL_RESOURCE_CLK0_PLL0 (34) +#define SYSCTL_RESOURCE_CLK1_PLL0 (35) +#define SYSCTL_RESOURCE_CLK2_PLL0 (36) +#define SYSCTL_RESOURCE_PLL1 (37) +#define SYSCTL_RESOURCE_CLK0_PLL1 (38) +#define SYSCTL_RESOURCE_CLK1_PLL1 (39) +#define SYSCTL_RESOURCE_PLL2 (40) +#define SYSCTL_RESOURCE_CLK0_PLL2 (41) +#define SYSCTL_RESOURCE_CLK1_PLL2 (42) +#define SYSCTL_RESOURCE_PLL0_REF (43) +#define SYSCTL_RESOURCE_PLL1_REF (44) +#define SYSCTL_RESOURCE_PLL2_REF (45) +#define SYSCTL_RESOURCE_MBIST_SOC (48) +#define SYSCTL_RESOURCE_MBIST_CPU (49) +#define SSYCTL_RESOURCE_MBIST_CON (50) +#define SYSCTL_RESOURCE_DFT_START_BUS (51) +#define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64) +#define SYSCTL_RESOURCE_CLK_TOP_MCHTMR0 (65) +#define SYSCTL_RESOURCE_CLK_TOP_FEMC (66) +#define SYSCTL_RESOURCE_CLK_TOP_XPI0 (67) +#define SYSCTL_RESOURCE_CLK_TOP_XPI1 (68) +#define SYSCTL_RESOURCE_CLK_TOP_ANA1 (93) +#define SYSCTL_RESOURCE_CLK_TOP_ANA2 (94) +#define SYSCTL_RESOURCE_CLK_TOP_ANA3 (95) +#define SYSCTL_RESOURCE_CLK_TOP_AUD0 (96) +#define SYSCTL_RESOURCE_CLK_TOP_AUD1 (97) +#define SYSCTL_RESOURCE_CLK_TOP_ETH0 (98) +#define SYSCTL_RESOURCE_CLK_TOP_PTP0 (99) +#define SYSCTL_RESOURCE_CLK_TOP_REF0 (100) +#define SYSCTL_RESOURCE_CLK_TOP_REF1 (101) +#define SYSCTL_RESOURCE_CLK_TOP_NTMR0 (102) +#define SYSCTL_RESOURCE_CLK_TOP_SDXC0 (103) +#define SYSCTL_RESOURCE_CLK_TOP_ADC0 (128) +#define SYSCTL_RESOURCE_CLK_TOP_ADC1 (129) +#define SYSCTL_RESOURCE_CLK_TOP_ADC2 (130) +#define SYSCTL_RESOURCE_CLK_TOP_DAC0 (131) +#define SYSCTL_RESOURCE_CLK_TOP_I2S0 (132) +#define SYSCTL_RESOURCE_CLK_TOP_I2S1 (133) + +#define SYSCTL_RESOURCE_ETH0_MEM (192) +#define SYSCTL_RESOURCE_SDXC0_MEM (193) +#define SYSCTL_RESOURCE_USB0_MEM (194) +#define SYSCTL_RESOURCE_RAM0_MEM (195) +#define SYSCTL_RESOURCE_AHBP_MEM (196) +#define SYSCTL_RESOURCE_FEMC_MEM (197) +#define SYSCTL_RESOURCE_ROM0_MEM (198) +#define SYSCTL_RESOURCE_XPI0_MEM (199) +#define SYSCTL_RESOURCE_XPI1_MEM (200) +#define SYSCTL_RESOURCE_CAN0_MEM (201) +#define SYSCTL_RESOURCE_CAN1_MEM (202) +#define SYSCTL_RESOURCE_I2S0_MEM (203) +#define SYSCTL_RESOURCE_I2S1_MEM (204) +#define SYSCTL_RESOURCE_PDM0_MEM (205) +#define SYSCTL_RESOURCE_SDP0_MEM (206) +#define SYSCTL_RESOURCE_FFA0_MEM (207) +#define SYSCTL_RESOURCE_CPX_MEM (208) +#define SYSCTL_RESOURCE_CORE_MEM (209) +#define SYSCTL_RESOURCE_LMM0_MEM (210) + +#define SYSCTL_RESOURCE_LINKABLE_START (256) +#define SYSCTL_RESOURCE_AHBP (256) +#define SYSCTL_RESOURCE_AXIS (257) +#define SYSCTL_RESOURCE_AXIC (258) +#define SYSCTL_RESOURCE_FEMC (259) +#define SYSCTL_RESOURCE_ROM0 (260) +#define SYSCTL_RESOURCE_LMM0 (261) +#define SYSCTL_RESOURCE_RAM0 (262) +#define SYSCTL_RESOURCE_MCHTMR0 (263) +#define SYSCTL_RESOURCE_XPI0 (264) +#define SYSCTL_RESOURCE_XPI1 (265) +#define SYSCTL_RESOURCE_SDP0 (266) +#define SYSCTL_RESOURCE_RNG0 (267) +#define SYSCTL_RESOURCE_KMAN (268) +#define SYSCTL_RESOURCE_DMA0 (269) +#define SYSCTL_RESOURCE_DMA1 (270) +#define SYSCTL_RESOURCE_FFA0 (271) +#define SYSCTL_RESOURCE_GPIO (272) +#define SYSCTL_RESOURCE_MBX0 (273) +#define SYSCTL_RESOURCE_WDG0 (274) +#define SYSCTL_RESOURCE_WDG1 (275) +#define SYSCTL_RESOURCE_TSNS (276) +#define SYSCTL_RESOURCE_GPTMR0 (277) +#define SYSCTL_RESOURCE_GPTMR1 (278) +#define SYSCTL_RESOURCE_GPRMR2 (279) +#define SYSCTL_RESOURCE_GPTMR3 (280) +#define SYSCTL_RESOURCE_UART0 (281) +#define SYSCTL_RESOURCE_UART1 (282) +#define SYSCTL_RESOURCE_UART2 (283) +#define SYSCTL_RESOURCE_UART3 (284) +#define SYSCTL_RESOURCE_UART4 (285) +#define SYSCTL_RESOURCE_UART5 (286) +#define SYSCTL_RESOURCE_UART6 (287) +#define SYSCTL_RESOURCE_UART7 (288) +#define SYSCTL_RESOURCE_I2C0 (289) +#define SYSCTL_RESOURCE_I2C1 (290) +#define SYSCTL_RESOURCE_I2C2 (291) +#define SYSCTL_RESOURCE_I2C3 (292) +#define SYSCTL_RESOURCE_SPI0 (293) +#define SYSCTL_RESOURCE_SPI1 (294) +#define SYSCTL_RESOURCE_SPI2 (295) +#define SYSCTL_RESOURCE_SPI3 (296) +#define SYSCTL_RESOURCE_CAN0 (297) +#define SYSCTL_RESOURCE_CAN1 (298) +#define SYSCTL_RESOURCE_PTPC (299) +#define SYSCTL_RESOURCE_ADC0 (300) +#define SYSCTL_RESOURCE_ADC1 (301) +#define SYSCTL_RESOURCE_ADC2 (302) +#define SYSCTL_RESOURCE_DAC0 (303) +#define SYSCTL_RESOURCE_ACMP (304) +#define SYSCTL_RESOURCE_I2S0 (305) +#define SYSCTL_RESOURCE_I2S1 (306) +#define SYSCTL_RESOURCE_I2SPDM0 (307) +#define SYSCTL_RESOURCE_I2SDAO (308) +#define SYSCTL_RESOURCE_MSYN (309) +#define SYSCTL_RESOURCE_MOT0 (310) +#define SYSCTL_RESOURCE_MOT1 (311) +#define SYSCTL_RESOURCE_ETH0 (312) +#define SYSCTL_RESOURCE_NTMR0 (313) +#define SYSCTL_RESOURCE_SDXC0 (314) +#define SYSCTL_RESOURCE_USB0 (315) +#define SYSCTL_RESOURCE_REF0 (316) +#define SYSCTL_RESOURCE_REF1 (317) +#define SYSCTL_RESOURCE_LINKABLE_END (317) + +#define CLOCK_NODE_MCHTMR0 (0) +#define CLOCK_NODE_FEMC (1) +#define CLOCK_NODE_XPI0 (2) +#define CLOCK_NODE_XPI1 (3) +#define CLOCK_NODE_GPTMR0 (4) +#define CLOCK_NODE_GPTMR1 (5) +#define CLOCK_NODE_GPTMR2 (6) +#define CLOCK_NODE_GPTMR3 (7) +#define CLOCK_NODE_UART0 (8) +#define CLOCK_NODE_UART1 (9) +#define CLOCK_NODE_UART2 (10) +#define CLOCK_NODE_UART3 (11) +#define CLOCK_NODE_UART4 (12) +#define CLOCK_NODE_UART5 (13) +#define CLOCK_NODE_UART6 (14) +#define CLOCK_NODE_UART7 (15) +#define CLOCK_NODE_I2C0 (16) +#define CLOCK_NODE_I2C1 (17) +#define CLOCK_NODE_I2C2 (18) +#define CLOCK_NODE_I2C3 (19) +#define CLOCK_NODE_SPI0 (20) +#define CLOCK_NODE_SPI1 (21) +#define CLOCK_NODE_SPI2 (22) +#define CLOCK_NODE_SPI3 (23) +#define CLOCK_NODE_CAN0 (24) +#define CLOCK_NODE_CAN1 (25) +#define CLOCK_NODE_PTPC (26) +#define CLOCK_NODE_ANA0 (27) +#define CLOCK_NODE_ANA1 (28) +#define CLOCK_NODE_ANA2 (29) +#define CLOCK_NODE_ANA3 (30) +#define CLOCK_NODE_AUD0 (31) +#define CLOCK_NODE_AUD1 (32) +#define CLOCK_NODE_ETH0 (33) +#define CLOCK_NODE_PTP0 (34) +#define CLOCK_NODE_REF0 (35) +#define CLOCK_NODE_REF1 (36) +#define CLOCK_NODE_NTMR0 (37) +#define CLOCK_NODE_SDXC0 (38) + +#define CLOCK_NODE_ADC0 (0) +#define CLOCK_NODE_ADC1 (1) +#define CLOCK_NODE_ADC2 (2) + +#define CLOCK_NODE_DAC0 (1) + +#define CLOCK_NODE_I2S0 (0) +#define CLOCK_NODE_I2S1 (1) + +#define CLOCK_NODE_CORE_START (252) +#define CLOCK_NODE_CPU0 (252) +#define CLOCK_NODE_AXI (253) +#define CLOCK_NODE_AHB (254) + +#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM6300_HPM6300_SYSCTL_H */ diff --git a/arch/risc-v/src/hpm6000/hardware/hpm_gpio.h b/arch/risc-v/src/hpm6000/hardware/hpm_gpio.h new file mode 100644 index 0000000000000..b9db47b3e7ccf --- /dev/null +++ b/arch/risc-v/src/hpm6000/hardware/hpm_gpio.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hardware/hpm_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_GPIO_H +#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hardware/hpm_memorymap.h" + +#if defined(CONFIG_ARCH_CHIP_HPM6360IPA) +#include "hpm6300/hpm6300_ioc.h" +#include "hpm6300/hpm6300_pinmux.h" +#else +#error The selected HPM variant is not impelemented +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define GPIOA 0 +#define GPIOB 1 +#define GPIOC 2 +#define GPIOD 3 +#define GPIOE 4 +#define GPIOF 5 +#define GPIOX 6 +#define GPIOY 7 +#define GPIOZ 8 +#define HPM_GPIO_NPINS 32 + +/* Most registers are laid out simply with one bit per pin */ + +#define GPIO_PIN(n) (1 << (n)) /* Bit n: Pin n, n=0-31 */ + +/* Register offsets *********************************************************/ + +#endif /* __ARCH_RISCV_SRC_MPFS_HARDWARE_MPFS_GPIO_H */ diff --git a/arch/risc-v/src/hpm6000/hardware/hpm_ioc.h b/arch/risc-v/src/hpm6000/hardware/hpm_ioc.h new file mode 100644 index 0000000000000..bd8b391c04712 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hardware/hpm_ioc.h @@ -0,0 +1,160 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hardware/hpm_ioc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_IOC_H +#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_IOC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "hpm_ioc.h" + +#define CONFIG_ARCH_FAMILY_HPM6300 + +#if defined (CONFIG_ARCH_FAMILY_HPM6300) +# include "hardware/hpm6300/hpm6300_ioc.h" +#else +# error Unrecognized HPM chip +#endif + +#define DRIVE_260OHM (1) +#define DRIVE_130OHM (2) +#define DRIVE_88OHM (3) +#define DRIVE_65OHM (4) +#define DRIVE_52OHM (5) +#define DRIVE_43OHM (6) +#define DRIVE_37OHM (7) + +#define SPEED_SLOW (0) +#define SPEED_MEDIUM (1) +#define SPEED_FAST (2) +#define SPEED_MAX (3) + +#define PULL_DOWN_100K (0) +#define PULL_UP_100K (1) +#define PULL_UP_47K (2) +#define PULL_UP_22K (3) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Pad Alt Registers */ + +#define IOC_PAD_FUNC_ALT_SELECT_SHIFT (0) +#define IOC_PAD_FUNC_ALT_SELECT_MASK (1f << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT(n) ((uint32_t)(n) << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT0 (0 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT1 (1 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT2 (2 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT3 (3 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT4 (4 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT5 (5 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT6 (6 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT7 (7 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT8 (8 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT9 (9 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT10 (10 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT11 (11 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT12 (12 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT13 (13 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT14 (14 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT15 (15 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT16 (16 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT17 (17 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT18 (18 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT19 (19 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT20 (20 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT21 (21 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT22 (22 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT23 (23 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT24 (24 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT25 (25 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT26 (26 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT27 (27 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT28 (28 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT29 (29 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT30 (30 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) +# define IOC_PAD_FUNC_ALT_SELECT_ALT31 (31 << IOC_PAD_FUNC_ALT_SELECT_SHIFT) + +/* Pad Analog Registers */ + +#define IOC_PAD_FUNC_ANALOG (1 << 8) + +/* Pad Loop Back Registers */ + +#define IOC_PAD_FUNC_LOOP_BACK (1 << 16) + +/* Pad Drive strength Registers */ + +#define IOC_PAD_PAD_DS_SHIFT (0) +#define IOC_PAD_PAD_DS_MASK (0x7 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS(n) ((uint32_t)(n) << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_1V8_260OHM (1 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_1V8_130OHM (2 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_1V8_88OHM (3 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_1V8_65OHM (4 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_1V8_52OHM (5 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_1V8_43OHM (6 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_1V8_37OHM (7 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_3V3_157OHM (1 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_3V3_78OHM (2 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_3V3_53OHM (3 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_3V3_39OHM (4 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_3V3_32OHM (5 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_3V3_26OHM (6 << IOC_PAD_PAD_DS_SHIFT) +# define IOC_PAD_PAD_DS_3V3_23OHM (7 << IOC_PAD_PAD_DS_SHIFT) + +#define IOC_PAD_PAD_SPD_SHIFT (4) +#define IOC_PAD_PAD_SPD_MASK (0x3 << IOC_PAD_PAD_SPD_SHIFT) +# define IOC_PAD_PAD_SPD(n) ((uint32_t)(n) << IOC_PAD_PAD_SPD_SHIFT) +# define IOC_PAD_PAD_SPD_SLOW (0 << IOC_PAD_PAD_SPD_SHIFT) +# define IOC_PAD_PAD_SPD_MEDIUM (1 << IOC_PAD_PAD_SPD_SHIFT) +# define IOC_PAD_PAD_SPD_FAST (2 << IOC_PAD_PAD_SPD_SHIFT) +# define IOC_PAD_PAD_SPD_MAX (3 << IOC_PAD_PAD_SPD_SHIFT) + +#define IOC_PAD_PAD_SR (1 << 6) +#define IOC_PAD_PAD_OD (1 << 8) +#define IOC_PAD_PAD_KE (1 << 16) +#define IOC_PAD_PAD_PE (1 << 17) +#define IOC_PAD_PAD_PS (1 << 18) + +#define IOC_PAD_PAD_PRS_SHIFT (20) /* Bit 20-21: Pull up/down internal resistance strength */ +#define IOC_PAD_PAD_PRS_MASK (0x3 << IOC_PAD_PAD_PRS_SHIFT) +# define IOC_PAD_PAD_PRS(n) ((uint32_t)(n) << IOC_PAD_PAD_PRS_SHIFT) +# define IOC_PAD_PAD_PRS_DOWN_100K (0 << IOC_PAD_PAD_PRS_SHIFT) +# define IOC_PAD_PAD_PRS_UP_100K (0 << IOC_PAD_PAD_PRS_SHIFT) +# define IOC_PAD_PAD_PRS_UP_47K (1 << IOC_PAD_PAD_PRS_SHIFT) +# define IOC_PAD_PAD_PRS_UP_22K (2 << IOC_PAD_PAD_PRS_SHIFT) + +#define IOC_PAD_PAD_HYS (1 << 24) /* Bit 24: Schmitt Trigger Enable Field */ + +/* Defaults for drive conditions for each set of pins. These are a good + * starting point but should be updated once you've got real hardware + * to measure. + */ + +#define IOC_PAD_UART_DEFAULT (PAD_PULL_UP_22K | PAD_DRIVE_43OHM | \ + PAD_SLEW_SLOW | PAD_SPEED_SLOW | PAD_SCHMITT_TRIGGER) + +#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_IOC_H */ diff --git a/arch/risc-v/src/hpm6000/hardware/hpm_mchtmr.h b/arch/risc-v/src/hpm6000/hardware/hpm_mchtmr.h new file mode 100644 index 0000000000000..03dd20292ebe3 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hardware/hpm_mchtmr.h @@ -0,0 +1,31 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hardware/hpm_mchtmr.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_MCHTMR_H +#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_MCHTMR_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define HPM_MCHTMR_MTIME (HPM_MCHTMR_BASE + 0x0000) +#define HPM_MCHTMR_MTIMECMP (HPM_MCHTMR_BASE + 0x0008) + +#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_MCHTMR_H */ diff --git a/arch/risc-v/src/hpm6000/hardware/hpm_memorymap.h b/arch/risc-v/src/hpm6000/hardware/hpm_memorymap.h new file mode 100644 index 0000000000000..b23eaa516e6ed --- /dev/null +++ b/arch/risc-v/src/hpm6000/hardware/hpm_memorymap.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hardware/hpm_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_MEMORYMAP_H +#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#define CONFIG_ARCH_FAMILY_HPM6300 + +#if defined(CONFIG_ARCH_FAMILY_HPM6300) +# include "hpm6300/hpm6300_memorymap.h" +#else +# error Unrecognized HPM architecture +#endif + +#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_MEMORYMAP_H */ diff --git a/arch/risc-v/src/hpm6000/hardware/hpm_plic.h b/arch/risc-v/src/hpm6000/hardware/hpm_plic.h new file mode 100644 index 0000000000000..37dd160435ed2 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hardware/hpm_plic.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hardware/hpm_plic.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_PLIC_H +#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_PLIC_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define HPM_PLIC_PRIORITY (HPM_PLIC_BASE + 0x000000) +#define HPM_PLIC_PENDING0 (HPM_PLIC_BASE + 0x001000) +#define HPM_PLIC_PENDING1 (HPM_PLIC_BASE + 0x001004) +#define HPM_PLIC_PENDING2 (HPM_PLIC_BASE + 0x001008) +#define HPM_PLIC_PENDING3 (HPM_PLIC_BASE + 0x00100C) +#define HPM_PLIC_INTEN0 (HPM_PLIC_BASE + 0x002000) +#define HPM_PLIC_INTEN1 (HPM_PLIC_BASE + 0x002004) +#define HPM_PLIC_INTEN2 (HPM_PLIC_BASE + 0x002008) +#define HPM_PLIC_INTEN3 (HPM_PLIC_BASE + 0x00200C) +#define HPM_PLIC_THRESHOLD (HPM_PLIC_BASE + 0x200000) +#define HPM_PLIC_CLAIM (HPM_PLIC_BASE + 0x200004) + +#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_PLIC_H */ diff --git a/arch/risc-v/src/hpm6000/hardware/hpm_pllctl.h b/arch/risc-v/src/hpm6000/hardware/hpm_pllctl.h new file mode 100644 index 0000000000000..5d50024e98124 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hardware/hpm_pllctl.h @@ -0,0 +1,131 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hardware/hpm_pllctl.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_PLLCTL_H +#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_PLLCTL_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define HPM_PLLCTLV2_XTAL (HPM_PLLCTL_BASE + 0x0000) +#define HPM_PLLCTLV2_PLL0_MFI (HPM_PLLCTL_BASE + 0x0080) +#define HPM_PLLCTLV2_PLL0_MFN (HPM_PLLCTL_BASE + 0x0084) +#define HPM_PLLCTLV2_PLL0_MFD (HPM_PLLCTL_BASE + 0x0088) +#define HPM_PLLCTLV2_PLL0_SS_STEP (HPM_PLLCTL_BASE + 0x008c) +#define HPM_PLLCTLV2_PLL0_SS_STOP (HPM_PLLCTL_BASE + 0x0090) +#define HPM_PLLCTLV2_PLL0_CONFIG (HPM_PLLCTL_BASE + 0x0094) +#define HPM_PLLCTLV2_PLL0_LOCKTIME (HPM_PLLCTL_BASE + 0x0098) +#define HPM_PLLCTLV2_PLL0_STEPTIME (HPM_PLLCTL_BASE + 0x009c) +#define HPM_PLLCTLV2_PLL0_ADVANCED (HPM_PLLCTL_BASE + 0x00a0) +#define HPM_PLLCTLV2_PLL0_DIV0 (HPM_PLLCTL_BASE + 0x00c0) +#define HPM_PLLCTLV2_PLL0_DIV1 (HPM_PLLCTL_BASE + 0x00c4) +#define HPM_PLLCTLV2_PLL0_DIV2 (HPM_PLLCTL_BASE + 0x00c8) + +#define HPM_PLLCTLV2_PLL1_MFI (HPM_PLLCTL_BASE + 0x0100) +#define HPM_PLLCTLV2_PLL1_MFN (HPM_PLLCTL_BASE + 0x0104) +#define HPM_PLLCTLV2_PLL1_MFD (HPM_PLLCTL_BASE + 0x0108) +#define HPM_PLLCTLV2_PLL1_SS_STEP (HPM_PLLCTL_BASE + 0x010c) +#define HPM_PLLCTLV2_PLL1_SS_STOP (HPM_PLLCTL_BASE + 0x0110) +#define HPM_PLLCTLV2_PLL1_CONFIG (HPM_PLLCTL_BASE + 0x0114) +#define HPM_PLLCTLV2_PLL1_LOCKTIME (HPM_PLLCTL_BASE + 0x0118) +#define HPM_PLLCTLV2_PLL1_STEPTIME (HPM_PLLCTL_BASE + 0x011c) +#define HPM_PLLCTLV2_PLL1_ADVANCED (HPM_PLLCTL_BASE + 0x0120) +#define HPM_PLLCTLV2_PLL1_DIV0 (HPM_PLLCTL_BASE + 0x0140) +#define HPM_PLLCTLV2_PLL1_DIV1 (HPM_PLLCTL_BASE + 0x0144) +#define HPM_PLLCTLV2_PLL1_DIV2 (HPM_PLLCTL_BASE + 0x0148) + +#define HPM_PLLCTLV2_PLL2_MFI (HPM_PLLCTL_BASE + 0x0180) +#define HPM_PLLCTLV2_PLL2_MFN (HPM_PLLCTL_BASE + 0x0184) +#define HPM_PLLCTLV2_PLL2_MFD (HPM_PLLCTL_BASE + 0x0188) +#define HPM_PLLCTLV2_PLL2_SS_STEP (HPM_PLLCTL_BASE + 0x018c) +#define HPM_PLLCTLV2_PLL2_SS_STOP (HPM_PLLCTL_BASE + 0x0190) +#define HPM_PLLCTLV2_PLL2_CONFIG (HPM_PLLCTL_BASE + 0x0194) +#define HPM_PLLCTLV2_PLL2_LOCKTIME (HPM_PLLCTL_BASE + 0x0198) +#define HPM_PLLCTLV2_PLL2_STEPTIME (HPM_PLLCTL_BASE + 0x019c) +#define HPM_PLLCTLV2_PLL2_ADVANCED (HPM_PLLCTL_BASE + 0x01a0) +#define HPM_PLLCTLV2_PLL2_DIV(n) (HPM_PLLCTL_BASE + 0x01c0 + n * 0x04) + +#define HPM_PLLCTLV2_XTAL_BUSY (0x80000000UL) +#define HPM_PLLCTLV2_XTAL_RESPONSE (0x20000000UL) +#define HPM_PLLCTLV2_XTAL_ENABLE (0x10000000UL) +#define HPM_PLLCTLV2_XTAL_RAMP_TIME_SHIFT (0U) +#define HPM_PLLCTLV2_XTAL_RAMP_TIME_MASK (0xFFFFFUL) +#define HPM_PLLCTLV2_XTAL_RAMP_TIME(n) \ + ((uint32_t)(n) << HPM_PLLCTLV2_XTAL_RAMP_TIME_SHIFT) + +#define HPM_PLLCTLV2_PLL_MFI_BUSY (0x80000000UL) +#define HPM_PLLCTLV2_PLL_MFI_RESPONSE (0x20000000UL) +#define HPM_PLLCTLV2_PLL_MFI_ENABLE (0x10000000UL) +#define HPM_PLLCTLV2_PLL_MFI_MFI_MASK (0x7FU) +#define HPM_PLLCTLV2_PLL_MFI_MFI_SHIFT (0U) +#define HPM_PLLCTLV2_PLL_MFI_MFI(n) \ + ((uint32_t)(n) << HPM_PLLCTLV2_PLL_MFI_MFI_SHIFT) + +#define HPM_PLLCTLV2_PLL_MFN_MFN_MASK (0x3FFFFFFFUL) +#define HPM_PLLCTLV2_PLL_MFN_MFN_SHIFT (0U) +#define HPM_PLLCTLV2_PLL_MFN_MFN(x) \ + ((uint32_t)(x) << PLLCTLV2_PLL_MFN_MFN_SHIFT) +#define HPM_PLLCTLV2_PLL_MFD_MFD_MASK (0x3FFFFFFFUL) +#define HPM_PLLCTLV2_PLL_MFD_MFD_SHIFT (0U) +#define HPM_PLLCTLV2_PLL_MFD_MFD(n) \ + ((uint32_t)(n) << PLLCTLV2_PLL_MFD_MFD_SHIFT) + +#define HPM_PLLCTLV2_PLL_SS_STEP_STEP_MASK (0x3FFFFFFFUL) +#define HPM_PLLCTLV2_PLL_SS_STEP_STEP_SHIFT (0U) +#define HPM_PLLCTLV2_PLL_SS_STEP_STEP(n) \ + ((uint32_t)(n) << HPM_PLLCTLV2_PLL_SS_STEP_STEP_SHIFT) +#define HPM_PLLCTLV2_PLL_SS_STOP_STOP_MASK (0x3FFFFFFFUL) +#define HPM_PLLCTLV2_PLL_SS_STOP_STOP_SHIFT (0U) +#define HPM_PLLCTLV2_PLL_SS_STOP_STOP(n) \ + ((uint32_t)(n) << PLLCTLV2_PLL_SS_STOP_STOP_SHIFT) + +#define HPM_PLLCTLV2_PLL_CONFIG_SPREAD (0x100U) +#define HPM_PLLCTLV2_PLL_CONFIG_REFSEL (0x1U) + +#define HPM_PLLCTLV2_PLL_LOCKTIME_LOCKTIME_MASK (0xFFFFU) +#define HPM_PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT (0U) +#define HPM_PLLCTLV2_PLL_LOCKTIME_LOCKTIME(x) \ + ((uint32_t)(x) << PLLCTLV2_PLL_LOCKTIME_LOCKTIME_SHIFT) + +#define HPM_PLLCTLV2_PLL_STEPTIME_STEPTIME_MASK (0xFFFFU) +#define HPM_PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT (0U) +#define HPM_PLLCTLV2_PLL_STEPTIME_STEPTIME(x) \ + ((uint32_t)(x) << PLLCTLV2_PLL_STEPTIME_STEPTIME_SHIFT) + +#define HPM_PLLCTLV2_PLL_ADVANCED_SLOW (0x10000000UL) +#define HPM_PLLCTLV2_PLL_ADVANCED_DITHER (0x1000000UL) + +#define HPM_PLLCTLV2_PLL_DIV_BUSY (0x80000000UL) +#define HPM_PLLCTLV2_PLL_DIV_RESPONSE (0x20000000UL) +#define HPM_PLLCTLV2_PLL_DIV_ENABLE (0x10000000UL) +#define HPM_PLLCTLV2_PLL_DIV_DIV_MASK (0x3FU) +#define HPM_PLLCTLV2_PLL_DIV_DIV_SHIFT (0U) +#define HPM_PLLCTLV2_PLL_DIV_DIV(x) \ + ((uint32_t)(x) << HPM_PLLCTLV2_PLL_DIV_DIV_SHIFT) +# define HPM_PLLCTLV2_PLL_DIV_DIV0 (0UL) +# define HPM_PLLCTLV2_PLL_DIV_DIV1 (1UL) +# define HPM_PLLCTLV2_PLL_DIV_DIV2 (2UL) + +#define HPM_PLLCTLV2_PLL_PLL0 (0UL) +#define HPM_PLLCTLV2_PLL_PLL1 (1UL) +#define HPM_PLLCTLV2_PLL_PLL2 (2UL) + +#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_PLLCTL_H */ diff --git a/arch/risc-v/src/hpm6000/hardware/hpm_sysctl.h b/arch/risc-v/src/hpm6000/hardware/hpm_sysctl.h new file mode 100644 index 0000000000000..5f82664bda372 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hardware/hpm_sysctl.h @@ -0,0 +1,42 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hardware/hpm_sysctl.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_SYSCTL_H +#define __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_SYSCTL_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#define CONFIG_ARCH_FAMILY_HPM6300 + +#if defined(CONFIG_ARCH_FAMILY_HPM6300) +# include "hpm6300/hpm6300_sysctl.h" +#else +# error Unrecognized HPM architecture +#endif + +#endif /* __ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_SYSCTL_H */ \ No newline at end of file diff --git a/arch/risc-v/src/hpm6000/hardware/hpm_uart.h b/arch/risc-v/src/hpm6000/hardware/hpm_uart.h new file mode 100644 index 0000000000000..2c34ee8d11264 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hardware/hpm_uart.h @@ -0,0 +1,238 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hardware/hpm_uart.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_UART_H +#define ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_UART_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define HPM_UART_MINIMUM_BAUDRATE (200U) +#define HPM_UART_BAUDRATE_TOLERANCE (3) +#define HPM_UART_OSC_MAX (32U) +#define HPM_UART_OSC_MIN (8U) +#define HPM_UART_BAUDRATE_DIV_MAX (0xFFFFU) +#define HPM_UART_BAUDRATE_DIV_MIN (1U) +#define HPM_UART_FREQ 2400000 + +#define HPM_UART_OSCR_OFFSET 0x14 +#define HPM_UART_RBR_OFFSET 0x20 +#define HPM_UART_THR_OFFSET 0x20 +#define HPM_UART_DLL_OFFSET 0x20 +#define HPM_UART_IER_OFFSET 0x24 +#define HPM_UART_DLM_OFFSET 0x24 +#define HPM_UART_IIR_OFFSET 0x28 +#define HPM_UART_FCR_OFFSET 0x28 +#define HPM_UART_LCR_OFFSET 0x2C +#define HPM_UART_MCR_OFFSET 0x30 +#define HPM_UART_LSR_OFFSET 0x34 +#define HPM_UART_MSR_OFFSET 0x38 + +/* Register addresses *******************************************************/ + +#define HPM_UART0_OSC (HPM_UART0_BASE + HPM_UART_OSCR_OFFSET) +#define HPM_UART0_RBR (HPM_UART0_BASE + HPM_UART_RBR_OFFSET) +#define HPM_UART0_THR (HPM_UART0_BASE + HPM_UART_THR_OFFSET) +#define HPM_UART0_DLL (HPM_UART0_BASE + HPM_UART_DLL_OFFSET) +#define HPM_UART0_IER (HPM_UART0_BASE + HPM_UART_IER_OFFSET) +#define HPM_UART0_DLM (HPM_UART0_BASE + HPM_UART_DLM_OFFSET) +#define HPM_UART0_IIR (HPM_UART0_BASE + HPM_UART_IIR_OFFSET) +#define HPM_UART0_FCR (HPM_UART0_BASE + HPM_UART_FCR_OFFSET) +#define HPM_UART0_LCR (HPM_UART0_BASE + HPM_UART_LCR_OFFSET) +#define HPM_UART0_MCR (HPM_UART0_BASE + HPM_UART_MCR_OFFSET) +#define HPM_UART0_LSR (HPM_UART0_BASE + HPM_UART_LSR_OFFSET) +#define HPM_UART0_MSR (HPM_UART0_BASE + HPM_UART_MSR_OFFSET) + +#define HPM_UART1_OSC (HPM_UART1_BASE + HPM_UART_OSCR_OFFSET) +#define HPM_UART1_RBR (HPM_UART1_BASE + HPM_UART_RBR_OFFSET) +#define HPM_UART1_THR (HPM_UART1_BASE + HPM_UART_THR_OFFSET) +#define HPM_UART1_DLL (HPM_UART1_BASE + HPM_UART_DLL_OFFSET) +#define HPM_UART1_IER (HPM_UART1_BASE + HPM_UART_IER_OFFSET) +#define HPM_UART1_DLM (HPM_UART1_BASE + HPM_UART_DLM_OFFSET) +#define HPM_UART1_IIR (HPM_UART1_BASE + HPM_UART_IIR_OFFSET) +#define HPM_UART1_FCR (HPM_UART1_BASE + HPM_UART_FCR_OFFSET) +#define HPM_UART1_LCR (HPM_UART1_BASE + HPM_UART_LCR_OFFSET) +#define HPM_UART1_MCR (HPM_UART1_BASE + HPM_UART_MCR_OFFSET) +#define HPM_UART1_LSR (HPM_UART1_BASE + HPM_UART_LSR_OFFSET) +#define HPM_UART1_MSR (HPM_UART1_BASE + HPM_UART_MSR_OFFSET) + +#define HPM_UART2_OSC (HPM_UART2_BASE + HPM_UART_OSCR_OFFSET) +#define HPM_UART2_RBR (HPM_UART2_BASE + HPM_UART_RBR_OFFSET) +#define HPM_UART2_THR (HPM_UART2_BASE + HPM_UART_THR_OFFSET) +#define HPM_UART2_DLL (HPM_UART2_BASE + HPM_UART_DLL_OFFSET) +#define HPM_UART2_IER (HPM_UART2_BASE + HPM_UART_IER_OFFSET) +#define HPM_UART2_DLM (HPM_UART2_BASE + HPM_UART_DLM_OFFSET) +#define HPM_UART2_IIR (HPM_UART2_BASE + HPM_UART_IIR_OFFSET) +#define HPM_UART2_FCR (HPM_UART2_BASE + HPM_UART_FCR_OFFSET) +#define HPM_UART2_LCR (HPM_UART2_BASE + HPM_UART_LCR_OFFSET) +#define HPM_UART2_MCR (HPM_UART2_BASE + HPM_UART_MCR_OFFSET) +#define HPM_UART2_LSR (HPM_UART2_BASE + HPM_UART_LSR_OFFSET) +#define HPM_UART2_MSR (HPM_UART2_BASE + HPM_UART_MSR_OFFSET) + +#define HPM_UART3_OSC (HPM_UART3_BASE + HPM_UART_OSCR_OFFSET) +#define HPM_UART3_RBR (HPM_UART3_BASE + HPM_UART_RBR_OFFSET) +#define HPM_UART3_THR (HPM_UART3_BASE + HPM_UART_THR_OFFSET) +#define HPM_UART3_DLL (HPM_UART3_BASE + HPM_UART_DLL_OFFSET) +#define HPM_UART3_IER (HPM_UART3_BASE + HPM_UART_IER_OFFSET) +#define HPM_UART3_DLM (HPM_UART3_BASE + HPM_UART_DLM_OFFSET) +#define HPM_UART3_IIR (HPM_UART3_BASE + HPM_UART_IIR_OFFSET) +#define HPM_UART3_FCR (HPM_UART3_BASE + HPM_UART_FCR_OFFSET) +#define HPM_UART3_LCR (HPM_UART3_BASE + HPM_UART_LCR_OFFSET) +#define HPM_UART3_MCR (HPM_UART3_BASE + HPM_UART_MCR_OFFSET) +#define HPM_UART3_LSR (HPM_UART3_BASE + HPM_UART_LSR_OFFSET) +#define HPM_UART3_MSR (HPM_UART3_BASE + HPM_UART_MSR_OFFSET) + +#define HPM_UART4_OSC (HPM_UART4_BASE + HPM_UART_OSCR_OFFSET) +#define HPM_UART4_RBR (HPM_UART4_BASE + HPM_UART_RBR_OFFSET) +#define HPM_UART4_THR (HPM_UART4_BASE + HPM_UART_THR_OFFSET) +#define HPM_UART4_DLL (HPM_UART4_BASE + HPM_UART_DLL_OFFSET) +#define HPM_UART4_IER (HPM_UART4_BASE + HPM_UART_IER_OFFSET) +#define HPM_UART4_DLM (HPM_UART4_BASE + HPM_UART_DLM_OFFSET) +#define HPM_UART4_IIR (HPM_UART4_BASE + HPM_UART_IIR_OFFSET) +#define HPM_UART4_FCR (HPM_UART4_BASE + HPM_UART_FCR_OFFSET) +#define HPM_UART4_LCR (HPM_UART4_BASE + HPM_UART_LCR_OFFSET) +#define HPM_UART4_MCR (HPM_UART4_BASE + HPM_UART_MCR_OFFSET) +#define HPM_UART4_LSR (HPM_UART4_BASE + HPM_UART_LSR_OFFSET) +#define HPM_UART4_MSR (HPM_UART4_BASE + HPM_UART_MSR_OFFSET) + +#define HPM_UART5_OSC (HPM_UART5_BASE + HPM_UART_OSCR_OFFSET) +#define HPM_UART5_RBR (HPM_UART5_BASE + HPM_UART_RBR_OFFSET) +#define HPM_UART5_THR (HPM_UART5_BASE + HPM_UART_THR_OFFSET) +#define HPM_UART5_DLL (HPM_UART5_BASE + HPM_UART_DLL_OFFSET) +#define HPM_UART5_IER (HPM_UART5_BASE + HPM_UART_IER_OFFSET) +#define HPM_UART5_DLM (HPM_UART5_BASE + HPM_UART_DLM_OFFSET) +#define HPM_UART5_IIR (HPM_UART5_BASE + HPM_UART_IIR_OFFSET) +#define HPM_UART5_FCR (HPM_UART5_BASE + HPM_UART_FCR_OFFSET) +#define HPM_UART5_LCR (HPM_UART5_BASE + HPM_UART_LCR_OFFSET) +#define HPM_UART5_MCR (HPM_UART5_BASE + HPM_UART_MCR_OFFSET) +#define HPM_UART5_LSR (HPM_UART5_BASE + HPM_UART_LSR_OFFSET) +#define HPM_UART5_MSR (HPM_UART5_BASE + HPM_UART_MSR_OFFSET) + +#define HPM_UART6_OSC (HPM_UART6_BASE + HPM_UART_OSCR_OFFSET) +#define HPM_UART6_RBR (HPM_UART6_BASE + HPM_UART_RBR_OFFSET) +#define HPM_UART6_THR (HPM_UART6_BASE + HPM_UART_THR_OFFSET) +#define HPM_UART6_DLL (HPM_UART6_BASE + HPM_UART_DLL_OFFSET) +#define HPM_UART6_IER (HPM_UART6_BASE + HPM_UART_IER_OFFSET) +#define HPM_UART6_DLM (HPM_UART6_BASE + HPM_UART_DLM_OFFSET) +#define HPM_UART6_IIR (HPM_UART6_BASE + HPM_UART_IIR_OFFSET) +#define HPM_UART6_FCR (HPM_UART6_BASE + HPM_UART_FCR_OFFSET) +#define HPM_UART6_LCR (HPM_UART6_BASE + HPM_UART_LCR_OFFSET) +#define HPM_UART6_MCR (HPM_UART6_BASE + HPM_UART_MCR_OFFSET) +#define HPM_UART6_LSR (HPM_UART6_BASE + HPM_UART_LSR_OFFSET) +#define HPM_UART6_MSR (HPM_UART6_BASE + HPM_UART_MSR_OFFSET) + +#define HPM_UART7_OSC (HPM_UART7_BASE + HPM_UART_OSCR_OFFSET) +#define HPM_UART7_RBR (HPM_UART7_BASE + HPM_UART_RBR_OFFSET) +#define HPM_UART7_THR (HPM_UART7_BASE + HPM_UART_THR_OFFSET) +#define HPM_UART7_DLL (HPM_UART7_BASE + HPM_UART_DLL_OFFSET) +#define HPM_UART7_IER (HPM_UART7_BASE + HPM_UART_IER_OFFSET) +#define HPM_UART7_DLM (HPM_UART7_BASE + HPM_UART_DLM_OFFSET) +#define HPM_UART7_IIR (HPM_UART7_BASE + HPM_UART_IIR_OFFSET) +#define HPM_UART7_FCR (HPM_UART7_BASE + HPM_UART_FCR_OFFSET) +#define HPM_UART7_LCR (HPM_UART7_BASE + HPM_UART_LCR_OFFSET) +#define HPM_UART7_MCR (HPM_UART7_BASE + HPM_UART_MCR_OFFSET) +#define HPM_UART7_LSR (HPM_UART7_BASE + HPM_UART_LSR_OFFSET) +#define HPM_UART7_MSR (HPM_UART7_BASE + HPM_UART_MSR_OFFSET) + +/* Register bit definitions *************************************************/ + +#define UART_RXIDLE_CFG_DETECT_COND (1U << 9) +#define UART_RXIDLE_CFG_DETECT_EN (1U << 8) +#define UART_RXIDLE_CFG_THR_SHIFT (0U) +#define UART_RXIDLE_CFG_THR_MASK (0xff << UART_RXIDLE_CFG_THR_SHIFT) +#define UART_RXIDLE_CFG_THR(n) ((uint32_t)(n) << UART_RXIDLE_CFG_THR_SHIFT) + +#define UART_CFG_FIFOSIZE_SHIFT (0U) +#define UART_CFG_FIFOSIZE_MASK (2 << UART_CFG_FIFOSIZE_SHIFT) +# define UART_CFG_FIFOSIZE_16B (0 << UART_CFG_FIFOSIZE_SHIFT) +# define UART_CFG_FIFOSIZE_32B (1 << UART_CFG_FIFOSIZE_SHIFT) +# define UART_CFG_FIFOSIZE_64B (2 << UART_CFG_FIFOSIZE_SHIFT) +# define UART_CFG_FIFOSIZE_128B (3 << UART_CFG_FIFOSIZE_SHIFT) + +#define UART_OSCR_OSC_SHIFT (0U) +#define UART_OSCR_OSC_MASK (0x1f << UART_OSCR_OSC_SHIFT) +# define UART_OSCR_OSC(n) ((uint32_t)(n) << UART_OSCR_OSC_SHIFT) + +#define UART_RBR_RBR_MASK (0xffff) + +#define UART_IER_ERBI (1 << 0) +#define UART_IER_ETHEI (1 << 1) +#define UART_IER_ELSI (1 << 2) +#define UART_IER_EMSI (1 << 3) +#define UART_IER_ERXIDLE (1 << 31) +#define UART_ALL_INTS (UART_IER_ERBI | UART_IER_ETHEI | UART_IER_ELSI | UART_IER_EMSI | UART_IER_ERXIDLE) + +#define UART_IIR_INTRID_SHIFT (0U) +#define UART_IIR_INTRID_MASK (0xf << UART_IIR_INTRID_SHIFT) +#define UART_IIR_INTRID_MODEM_STATE (0x1 << UART_IIR_INTRID_SHIFT) +#define UART_IIR_INTRID_TX_AVAILE (0x2 << UART_IIR_INTRID_SHIFT) +#define UART_IIR_INTRID_RX_AVAILE (0x4 << UART_IIR_INTRID_SHIFT) +#define UART_IIR_INTRID_RX_STATE (0x6 << UART_IIR_INTRID_SHIFT) +#define UART_IIR_INTRID_RX_TIMEOUT (0xc << UART_IIR_INTRID_SHIFT) +#define UART_IIR_FIFOED_SHIFT (6U) +#define UART_IIR_FIFOED_MASK (3 << UART_IIR_FIFOED_SHIFT) +#define UART_IIR_DATA_LOST (1 << 27) +#define UART_IIR_ADDR_MATCH_IDLE (1 << 28) +#define UART_IIR_ADDR_MATCH (1 << 29) +#define UART_IIR_TXIDLE_FLAG (1 << 30) +#define UART_IIR_RXIDLE_FLAG (1 << 31) + +#define UART_FCR_FIFOE (1 << 0) +#define UART_FCR_RXFIFORST (1 << 1) +#define UART_FCR_TXFIFORST (1 << 2) +#define UART_FCR_DMAE (1 << 3) +#define UART_FCR_TFIFOT_SHIFT (4U) +#define UART_FCR_TFIFOT_MASK (0x3U << UART_FCR_TFIFO_SHIFT) +#define UART_FCR_TFIFOT(n) ((uint32_t)(n) << UART_FCR_TFIFO_SHIFT) +#define UART_FCR_RFIFOT_SHIFT (6U) +#define UART_FCR_RFIFOT_MASK (0x3U << UART_FCR_RFIFO_SHIFT) +#define UART_FCR_RFIFOT(n) ((uint32_t)(n) << UART_FCR_RFIFO_SHIFT) + +#define UART_LCR_WLS_SHIFT (0U) +#define UART_LCR_WLS_MASK (0x3U << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_5BITS (0 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_6BITS (1 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_7BITS (2 << UART_LCR_WLS_SHIFT) +# define UART_LCR_WLS_8BITS (3 << UART_LCR_WLS_SHIFT) +#define UART_LCR_STB (1 << 2) +#define UART_LCR_PEN (1 << 3) +#define UART_LCR_EPS (1 << 4) +#define UART_LCR_SPS (1 << 5) +#define UART_LCR_BC (1 << 6) +#define UART_LCR_DLAB (1 << 7) + +#define UART_MCR_RTS (1 << 0) +#define UART_MCR_LOOP (1 << 1) +#define UART_MCR_AFE (1 << 5) + +#define UART_LSR_DR (1 << 0) +#define UART_LSR_OE (1 << 1) +#define UART_LSR_PE (1 << 2) +#define UART_LSR_FE (1 << 3) +#define UART_LSR_LBREAK (1 << 4) +#define UART_LSR_THRE (1 << 5) +#define UART_LSR_TEMT (1 << 6) +#define UART_LSR_ERRF (1 << 7) + +#define UART_MSR_DCTS (1 << 0) +#define UART_MSR_CTS (1 << 4) + +#endif /* ARCH_RISCV_SRC_HPM6000_HARDWARE_HPM_UART_H */ diff --git a/arch/risc-v/src/hpm6000/hpm.h b/arch/risc-v/src/hpm6000/hpm.h new file mode 100644 index 0000000000000..23ca06346ef27 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm.h @@ -0,0 +1,37 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_H +#define __ARCH_RISCV_SRC_HPM6000_HPM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include +#include "riscv_internal.h" +#include "chip.h" + +#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_H */ diff --git a/arch/risc-v/src/hpm6000/hpm_clockconfig.c b/arch/risc-v/src/hpm6000/hpm_clockconfig.c new file mode 100644 index 0000000000000..75f055e94f6fb --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_clockconfig.c @@ -0,0 +1,210 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_clockconfig.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "hardware/hpm6300/hpm6300_sysctl.h" +#include "hardware/hpm_memorymap.h" +#include "hardware/hpm_pllctl.h" +#include "riscv_internal.h" +#include "chip.h" +#include "hpm.h" +#include "hpm_clockconfig.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define EXT_OSC 24000000 + +#define PLLCTLV2_PLL_MFN_FACTOR (10U) /* PLLCTLV2 PLL MFN Factor */ +#define PLLCTLV2_PLL_MFD_DEFAULT (240UL * 1000000UL) /* PLLCTLV2 PLL Default MFD value */ + +#define PLLCTLV2_PLL_MFI_MIN (16U) +#define PLLCTLV2_PLL_MFI_MAX (42U) +#define PLLCTLV2_PLL_XTAL_FREQ (24000000UL) + +#define PLLCTLV2_PLL_FREQ_MIN (PLLCTLV2_PLL_MFI_MIN * PLLCTLV2_PLL_XTAL_FREQ) +#define PLLCTLV2_PLL_FREQ_MAX ((PLLCTLV2_PLL_MFI_MAX + 1U) * PLLCTLV2_PLL_XTAL_FREQ) + +#define BUS_FREQ_MAX (166000000UL) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: hpm6750_get_osc_freq + ****************************************************************************/ + +uint32_t hpm_get_osc_freq(void) +{ + return EXT_OSC; +} + +/**************************************************************************** + * Name: hpm6750_clockconfig + ****************************************************************************/ + +void hpm_clockconfig(void) +{ + uint32_t value; + + value = getreg32(0xf40c4010); + value &= ~0xfff; + value |= 0x1044c; + putreg32(value, 0xf40c4010); + + /* uart should configure pin function before opening clock */ + + value = 0xffffffff & + ~(SYSCTL_GROUP0_LINK0_UART0 | SYSCTL_GROUP0_LINK0_UART1 | + SYSCTL_GROUP0_LINK0_UART2 | SYSCTL_GROUP0_LINK0_UART3 | + SYSCTL_GROUP0_LINK0_UART4 | SYSCTL_GROUP0_LINK0_UART5 | + SYSCTL_GROUP0_LINK0_UART6); + putreg32(0x01f7ffff, HPM_SYSCTL_GROUP0_LINK0_VALUE); + + value = 0xffffffff & ~SYSCTL_GROUP0_LINK1_UART7; + putreg32(0x3dfffffe, HPM_SYSCTL_GROUP0_LINK1_VALUE); + + /* Connect Group0 to CPU0 */ + + putreg32(1, HPM_SYSCTL_AFFILIATE_CPU0_SET); + + value = getreg32(HPM_SYSCTL_CLOCK_CPU_CLK_TOP_CPU0); + if ((value & 0xff) == 1) + { + value = SYSCTL_CLOCK_CPU_MUX_PLL1_CLK0 | + SYSCTL_CLOCK_CPU_DIV(CPU_DIV) | + SYSCTL_CLOCK_CPU_SUB0_DIV(AXI_SUB_DIV - 1) | + SYSCTL_CLOCK_CPU_SUB1_DIV(AHB_SUB_DIV - 1); + putreg32(value, HPM_SYSCTL_CLOCK_CPU_CLK_TOP_CPU0); + while (getreg32(HPM_SYSCTL_CLOCK_CPU_CLK_TOP_CPU0) & 0x80000000); + } + + /* Configure CPU0 clock & AXI Sub-clock & AHB Sub-clock */ + + value = SYSCTL_CLOCK_CPU_MUX_PLL1_CLK0 | + SYSCTL_CLOCK_CPU_DIV(CPU_DIV - 1) | + SYSCTL_CLOCK_CPU_SUB0_DIV(AXI_SUB_DIV - 1) | + SYSCTL_CLOCK_CPU_SUB1_DIV(AHB_SUB_DIV - 1); + putreg32(value, HPM_SYSCTL_CLOCK_CPU_CLK_TOP_CPU0); + while (getreg32(HPM_SYSCTL_CLOCK_CPU_CLK_TOP_CPU0) & 0x80000000); + +#if defined (CONFIG_ARCH_FAMILY_HPM6300) + /* Configure PLL1_CLK0 Post Divider */ + + value = (getreg32(HPM_PLLCTLV2_PLL1_DIV0) & + ~HPM_PLLCTLV2_PLL_DIV_DIV_MASK) | + HPM_PLLCTLV2_PLL_DIV_DIV(PLL1_DIV) | + HPM_PLLCTLV2_PLL_DIV_ENABLE; + putreg32(value, HPM_PLLCTLV2_PLL1_DIV0); + while (getreg32(HPM_PLLCTLV2_PLL1_DIV0) & 0x80000000); +#endif + /* Configure PLL1 clock frequencey */ + + value = PLL1_FREQ / PLLCTLV2_PLL_XTAL_FREQ - 1; + putreg32(value, HPM_PLLCTLV2_PLL1_MFI); + while (getreg32(HPM_PLLCTLV2_PLL1_MFI) & 0x80000000); + putreg32(value + 1, HPM_PLLCTLV2_PLL1_MFI); + while (getreg32(HPM_PLLCTLV2_PLL1_MFI) & 0x80000000); + + value = PLL1_FREQ % PLLCTLV2_PLL_XTAL_FREQ * PLLCTLV2_PLL_MFN_FACTOR; + putreg32(value, HPM_PLLCTLV2_PLL1_MFN); + while (getreg32(HPM_PLLCTLV2_PLL1_MFN) & 0x80000000); + + value = (getreg32(HPM_SYSCTL_CLOCK_CLK_TOP_MCT0) & + ~(SYSCTL_CLOCK_MUX_MASK | SYSCTL_CLOCK_DIV_MASK)) | + (SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1)); + putreg32(value, HPM_SYSCTL_CLOCK_CLK_TOP_MCT0); + while (getreg32(HPM_SYSCTL_CLOCK_CLK_TOP_MCT0) & 0x40000000); +} + +void hpm_uart_clockconfig(void) +{ + uint32_t value; + + value = getreg32(HPM_SYSCTL_GROUP0_LINK0_VALUE); + +#ifdef CONFIG_HPM_UART0 + putreg32(SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1), + HPM_SYSCTL_CLOCK_CLK_TOP_UART0); + while (getreg32(HPM_SYSCTL_CLOCK_CLK_TOP_UART0) & 0x40000000); + value |= SYSCTL_GROUP0_LINK0_UART0; +#endif + +#ifdef CONFIG_HPM_UART1 + putreg32(SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1), + HPM_SYSCTL_CLOCK_CLK_TOP_UART1); + value |= SYSCTL_GROUP0_LINK0_UART1; +#endif + +#if defined CONFIG_HPM_UART2 + putreg32(SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1), + HPM_SYSCTL_CLOCK_CLK_TOP_UART2); + value |= SYSCTL_GROUP0_LINK0_UART2; +#endif + +#if defined CONFIG_HPM_UART3 + putreg32(SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1), + HPM_SYSCTL_CLOCK_CLK_TOP_UART3); + value |= SYSCTL_GROUP0_LINK0_UART3; +#endif + +#if defined CONFIG_HPM_UART4 + putreg32(SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1), + HPM_SYSCTL_CLOCK_CLK_TOP_UART4); + value |= SYSCTL_GROUP0_LINK0_UART4; +#endif + +#if defined CONFIG_HPM_UART5 + putreg32(SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1), + HPM_SYSCTL_CLOCK_CLK_TOP_UART5); + value |= SYSCTL_GROUP0_LINK0_UART5; +#endif + +#if defined CONFIG_HPM_UART6 + putreg32(SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1), + HPM_SYSCTL_CLOCK_CLK_TOP_UART6); + value |= SYSCTL_GROUP0_LINK0_UART6; +#endif + + putreg32(value, HPM_SYSCTL_GROUP0_LINK0_SET); + +#ifdef CONFIG_HPM_UART7 + putreg32(SYSCTL_CLOCK_MUX_OSC0_CLK0 | SYSCTL_CLOCK_DIV(1), + HPM_SYSCTL_CLOCK_CLK_TOP_UART7); + value = getreg32(HPM_SYSCTL_GROUP0_LINK1_VALUE); + value |= SYSCTL_GROUP0_LINK1_UART7; + putreg32(value, HPM_SYSCTL_GROUP0_LINK1_SET); +#endif +} diff --git a/arch/risc-v/src/hpm6000/hpm_clockconfig.h b/arch/risc-v/src/hpm6000/hpm_clockconfig.h new file mode 100644 index 0000000000000..58210967b29cd --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_clockconfig.h @@ -0,0 +1,152 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_clockconfig.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_CLOCKCONFIG_H +#define __ARCH_RISCV_SRC_HPM6000_HPM_CLOCKCONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hpm_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CPU_DIV 1 +#define AXI_SUB_DIV 3 +#define AHB_SUB_DIV 3 +#define PLL1_DIV 1 +#define PLL1_FREQ 576000000 +#define AUD_DIV 46 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/** + * @brief Clock nodes + */ + +typedef enum +{ + clock_node_mchtmr0 = 0, + clock_node_femc = 1, + clock_node_xpi0 = 2, + clock_node_xpi1 = 3, + clock_node_gptmr0 = 4, + clock_node_gptmr1 = 5, + clock_node_gptmr2 = 6, + clock_node_gptmr3 = 7, + clock_node_uart0 = 8, + clock_node_uart1 = 9, + clock_node_uart2 = 10, + clock_node_uart3 = 11, + clock_node_uart4 = 12, + clock_node_uart5 = 13, + clock_node_uart6 = 14, + clock_node_uart7 = 15, + clock_node_i2c0 = 16, + clock_node_i2c1 = 17, + clock_node_i2c2 = 18, + clock_node_i2c3 = 19, + clock_node_spi0 = 20, + clock_node_spi1 = 21, + clock_node_spi2 = 22, + clock_node_spi3 = 23, + clock_node_can0 = 24, + clock_node_can1 = 25, + clock_node_ptpc = 26, + clock_node_ana0 = 27, + clock_node_ana1 = 28, + clock_node_ana2 = 29, + clock_node_ana3 = 30, + clock_node_aud0 = 31, + clock_node_aud1 = 32, + clock_node_eth0 = 33, + clock_node_ptp0 = 34, + clock_node_ref0 = 35, + clock_node_ref1 = 36, + clock_node_ntmr0 = 37, + clock_node_sdxc0 = 38, + + clock_node_adc_i2s_start, + clock_node_adc0 = clock_node_adc_i2s_start, + clock_node_adc1, + clock_node_adc2, + + clock_node_i2s0, + clock_node_i2s1, + + clock_node_end, + + clock_node_core_start = 0xfc, + clock_node_cpu0 = clock_node_core_start, + clock_node_axi, + clock_node_ahb, +} clock_node_t; + +/** + * @brief General clock sources + */ + +typedef enum +{ + clock_source_osc0_clk0 = 0, + clock_source_pll0_clk0 = 1, + clock_source_pll0_clk1 = 2, + clock_source_pll0_clk2 = 3, + clock_source_pll1_clk0 = 4, + clock_source_pll1_clk1 = 5, + clock_source_pll2_clk0 = 6, + clock_source_pll2_clk1 = 7, + clock_source_general_source_end, +} clock_source_t; + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +EXTERN uint32_t hpm_get_osc_freq(void); +EXTERN void hpm_clockconfig(void); +void hpm_uart_clockconfig(void); + +#if defined(__cplusplus) +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_CLOCKCONFIG_H */ diff --git a/arch/risc-v/src/hpm6000/hpm_config.h b/arch/risc-v/src/hpm6000/hpm_config.h new file mode 100644 index 0000000000000..6c671ecd3360e --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_config.h @@ -0,0 +1,131 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_config.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_CONFIG_H +#define __ARCH_RISCV_SRC_HPM6000_HPM_CONFIG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#undef HAVE_UART_DEVICE +#if defined(CONFIG_HPM_UART0) || defined(CONFIG_HPM_UART1) || \ + defined(CONFIG_HPM_UART2) || defined(CONFIG_HPM_UART3) || \ + defined(CONFIG_HPM_UART4) || defined(CONFIG_HPM_UART5) || \ + defined(CONFIG_HPM_UART6) || defined(CONFIG_HPM_UART7) +# define HAVE_UART_DEVICE 1 +#endif + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_HPM_UART0) +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_UART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_HPM_UART1) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_UART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_HPM_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_UART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_HPM_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_UART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_HPM_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_UART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_HPM_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART6_SERIAL_CONSOLE) && defined(CONFIG_HPM_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#elif defined(CONFIG_UART7_SERIAL_CONSOLE) && defined(CONFIG_HPM_UART2) +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_UART6_SERIAL_CONSOLE +# define HAVE_UART_CONSOLE 1 +#else +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_UART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# undef HAVE_UART_CONSOLE +#endif + +#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_CONFIG_H */ diff --git a/arch/risc-v/src/hpm6000/hpm_gpio.c b/arch/risc-v/src/hpm6000/hpm_gpio.c new file mode 100644 index 0000000000000..7b3172a910289 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_gpio.c @@ -0,0 +1,294 @@ +/*************************************************************************** + * arch/risc-v/src/hpm6000/hpm_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ***************************************************************************/ + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include + +#include "hardware/hpm_memorymap.h" +#include "hardware/hpm_ioc.h" +#include "hardware/hpm_gpio.h" +#include "hpm_gpio.h" +#include "riscv_internal.h" +#include "hpm_gpio.h" +#include "hpm_ioc.h" + +/*************************************************************************** + * Pre-processor Definitions + ***************************************************************************/ + +#define HPM_GPIO_NPORTS 6 + +/*************************************************************************** + * Private Functions + ***************************************************************************/ + +/*************************************************************************** + * Public Data + ***************************************************************************/ + +/*************************************************************************** + * Name: hpm_gpio_dirout + ***************************************************************************/ + +static inline void hpm_gpio_dirout(int port, int pin) +{ + uint32_t regval = getreg32(HPM_GPIO_OE_SET(port)); + regval |= GPIO_PIN(pin); + putreg32(regval, HPM_GPIO_OE_SET(port)); +} + +/*************************************************************************** + * Name: hpm_gpio_diin + ***************************************************************************/ + +static inline void hpm_gpio_dirin(int port, int pin) +{ + uint32_t regval = getreg32(HPM_GPIO_OE_CLR(port)); + regval |= GPIO_PIN(pin); + putreg32(regval, HPM_GPIO_OE_CLR(port)); +} + +/*************************************************************************** + * Name: hpm_gpio_setoutput + ***************************************************************************/ + +static void hpm_gpio_setoutput(int port, int pin, bool value) +{ + uint32_t regval = 0; + + if (value) + { + regval = getreg32(HPM_GPIO_DO_SET(port)); + regval |= GPIO_PIN(pin); + putreg32(regval, HPM_GPIO_DO_SET(port)); + } + else + { + regval = getreg32(HPM_GPIO_DO_CLR(port)); + regval |= GPIO_PIN(pin); + putreg32(regval, HPM_GPIO_DO_CLR(port)); + } +} + +/*************************************************************************** + * Name: hpm_gpio_getinput + ***************************************************************************/ + +static inline bool hpm_gpio_getinput(int port, int pin) +{ + uint32_t regval = getreg32(HPM_GPIO_DI_VAL(port)); + + return ((regval & GPIO_PIN(pin)) != 0); +} + +/*************************************************************************** + * Name: hpm_gpio_configinput + ***************************************************************************/ + +static int hpm_gpio_configinput(gpio_pinset_t pinset) +{ + int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + ioc_pinset_t ioset; + uintptr_t padctl; + + /* Configure pin as */ + + hpm_gpio_dirin(port, pin); + + /* Configure pin as a GPIO */ + + putreg32(IOC_PAD_FUNC_ALT_SELECT_ALT0, IOC_FUNC_CTL_(port, pin)); + + /* Configure pin pad settings */ + + padctl = IOC_PAD_CTL_(port, pin); + + ioset = (ioc_pinset_t)(pinset & GPIO_IOCPAD_MASK) >> GPIO_IOCPAD_SHIFT; + + return hpm_iocpad_configure(padctl, ioset); +} + +/*************************************************************************** + * Name: hpm_gpio_configoutput + ***************************************************************************/ + +static inline int hpm_gpio_configoutput(gpio_pinset_t pinset) +{ + int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + bool value = ((pinset & GPIO_OUTPUT_ONE) != 0); + + /* Set the output value */ + + hpm_gpio_setoutput(port, pin, value); + + /* Convert the configured input GPIO to an poutput */ + + hpm_gpio_dirout(port, pin); + + return OK; +} + +/*************************************************************************** + * Name: hpm_gpio_configperiph + ***************************************************************************/ + +static inline int hpm_gpio_configperiph(gpio_pinset_t pinset) +{ + unsigned int index; + ioc_pinset_t ioset; + uintptr_t regaddr; + + index = ((pinset & GPIO_PADMUX_MASK) >> GPIO_PADMUX_SHIFT); + ioset = (ioc_pinset_t)(pinset & GPIO_IOCPAD_MASK) >> GPIO_IOCPAD_SHIFT; + + regaddr = HPM_IOC_PAD_PAD_CTL_ADDRESS(index); + + hpm_iocpad_configure(regaddr, ioset); + + if (index >= HPM_IOC_PAD_PY00_INDEX) + { + regaddr = HPM_PIOC_PAD_PAD_CTL_ADDRESS(index); + hpm_iocpad_configure(regaddr, PAD_ALT3); + } + + return OK; +} + +/*************************************************************************** + * Public Functions + ***************************************************************************/ + +/*************************************************************************** + * Name: hpm_gpio_config + * + * Description: + * Configure a GPIO pin based on pin-encoded description of the pin. + * + ***************************************************************************/ + +int hpm_gpio_config(gpio_pinset_t pinset) +{ + irqstate_t flags; + int ret; + + /* Configure the pin as an input initially to avoid any spurious outputs */ + + flags = enter_critical_section(); + + /* Configure based upon the pin mode */ + + switch (pinset & GPIO_MODE_MASK) + { + case GPIO_INPUT: + { + /* Configure the pin as a GPIO input */ + + ret = hpm_gpio_configinput(pinset); + } + break; + + case GPIO_OUTPUT: + { + ret = hpm_gpio_configoutput(pinset); + } + break; + + case GPIO_PERIPH: + { + ret = hpm_gpio_configperiph(pinset); + } + break; + +#ifdef CONFIG_HPM_GPIO_IRQ + /* TODO: irq configure */ +#endif + default: + ret = -EINVAL; + break; + } + + leave_critical_section(flags); + return ret; +} + +/*************************************************************************** + * Name: hpm_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ***************************************************************************/ + +void hpm_gpio_write(gpio_pinset_t pinset, bool value) +{ + irqstate_t flags; + int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + flags = enter_critical_section(); + hpm_gpio_setoutput(port, pin, value); + leave_critical_section(flags); +} + +/*************************************************************************** + * Name: hpm_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ***************************************************************************/ + +bool hpm_gpio_read(gpio_pinset_t pinset) +{ + irqstate_t flags; + int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + bool value; + + flags = enter_critical_section(); + if ((pinset &(GPIO_OUTPUT | GPIO_LOOP_ENABLE)) == + (GPIO_OUTPUT | GPIO_LOOP_ENABLE)) + { + /* TODO: read input state */ + } + else + { + value = hpm_gpio_getinput(port, pin); + } + + leave_critical_section(flags); + + return value; +} diff --git a/arch/risc-v/src/hpm6000/hpm_gpio.h b/arch/risc-v/src/hpm6000/hpm_gpio.h new file mode 100644 index 0000000000000..ea3d9af2df854 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_gpio.h @@ -0,0 +1,357 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_GPIO_H +#define __ARCH_RISCV_SRC_HPM6000_HPM_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +#include +#include +#endif + +#include +#include + +#include "chip.h" +#include "hardware/hpm_gpio.h" + +/**************************************************************************** + * Pre-Processor Declarations + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* 32-bit Encoding: + * + * 3322 2222 2222 1111 1111 1100 0000 0000 + * 1098 7654 3210 9876 5432 1098 7654 3210 + * ENCODING IIXX XXXX XXXX XXXX MMMM MMMM MMMM MMMM + * GPIO INPUT 00.. BEEG GGGP PPPP MMMM MMMM MMMM MMMM + * INT INPUT 11.. BEEG GGGP PPPP MMMM MMMM MMMM MMMM + * GPIO OUTPUT 01V. ..SG GGGP PPPP MMMM MMMM MMMM MMMM + * PERIPHERAL 10AA AAS. IIII IIII MMMM MMMM MMMM MMMM + */ + +/* Input/Output Selection: + * + * 3322 2222 2222 1111 1111 1100 0000 0000 + * 1098 7654 3210 9876 5432 1098 7654 3210 + * ENCODING II.. .... .... .... .... .... .... .... + */ + +#define GPIO_MODE_SHIFT (30) /* Bits 30-31: Pin mode */ +#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT) +# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* GPIO input */ +# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* GPIO output */ +# define GPIO_PERIPH (2 << GPIO_MODE_SHIFT) /* Peripheral */ +# define GPIO_INTERRUPT (3 << GPIO_MODE_SHIFT) /* Interrupt input */ + +/* Initial Output Value: + * + * GPIO OUTPUT 01V. .... .... .... .... .... .... .... + */ + +#define GPIO_OUTPUT_ZERO (0) /* Bit 29: 0=Initial output is low */ +#define GPIO_OUTPUT_ONE (1 << 29) /* Bit 29: 1=Initial output is high */ + +/* Loopback On Field: + * + * 3322 2222 2222 1111 1111 1100 0000 0000 + * 1098 7654 3210 9876 5432 1098 7654 3210 + * PERIPHERAL .... ..S. .... .... .... .... .... .... + */ + +#define GPIO_LOOP_SHIFT (24) /* Bits 24: Peripheral SION function */ +#define GPIO_LOOP_MASK (1 << GPIO_LOOP_SHIFT) +# define GPIO_LOOP_ENABLE (1 << GPIO_LOOP_SHIFT) /* enable SION */ + +/* Interrupt edge/level configuration + * + * 3322 2222 2222 1111 1111 1100 0000 0000 + * 1098 7654 3210 9876 5432 1098 7654 3210 + * INT INPUT 11.. .EE. .... .... .... .... .... .... + */ + +#define GPIO_INTCFG_SHIFT (24) /* Bits 24-25: Interrupt edge/level configuration */ +#define GPIO_INTCFG_MASK (3 << GPIO_INTCFG_SHIFT) +# define GPIO_INT_LOWLEVEL (GPIO_ICR_LOWLEVEL << GPIO_INTCFG_SHIFT) +# define GPIO_INT_HIGHLEVEL (GPIO_ICR_HIGHLEVEL << GPIO_INTCFG_SHIFT) +# define GPIO_INT_RISINGEDGE (GPIO_ICR_RISINGEDGE << GPIO_INTCFG_SHIFT) +# define GPIO_INT_FALLINGEDGE (GPIO_ICR_FALLINGEDGE << GPIO_INTCFG_SHIFT) + +/* GPIO Port Number + * + * 3322 2222 2222 1111 1111 1100 0000 0000 + * 1098 7654 3210 9876 5432 1098 7654 3210 + * GPIO INPUT 00.. ...G GGG. .... .... .... .... .... + * GPIO OUTPUT 01.. ...G GGG. .... .... .... .... .... + */ + +#define GPIO_PORT_SHIFT (21) /* Bits 21-23: GPIO port index */ +#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT) +# define GPIO_PORTA (GPIOA << GPIO_PORT_SHIFT) /* GPIO1 */ +# define GPIO_PORTB (GPIOB << GPIO_PORT_SHIFT) /* GPIO2 */ +# define GPIO_PORTC (GPIOC << GPIO_PORT_SHIFT) /* GPIO3 */ +# define GPIO_PORTD (GPIOD << GPIO_PORT_SHIFT) /* GPIO3 */ +# define GPIO_PORTE (GPIOE << GPIO_PORT_SHIFT) /* GPIO3 */ +# define GPIO_PORTF (GPIOF << GPIO_PORT_SHIFT) /* GPIO3 */ +# define GPIO_PORTX (GPIOX << GPIO_PORT_SHIFT) /* GPIO4 */ +# define GPIO_PORTY (GPIOY << GPIO_PORT_SHIFT) /* GPIO5 */ +# define GPIO_PORTZ (GPIOZ << GPIO_PORT_SHIFT) /* GPIOZ */ + +/* GPIO Pin Number: + * + * 3322 2222 2222 1111 1111 1100 0000 0000 + * 1098 7654 3210 9876 5432 1098 7654 3210 + * GPIO INPUT 00.. .... ...P PPPP .... .... .... .... + * GPIO OUTPUT 01.. .... ...P PPPP .... .... .... .... + */ + +#define GPIO_PIN_SHIFT (16) /* Bits 0-4: GPIO number: 0-31 */ +#define GPIO_PIN_MASK (0x1f << GPIO_PIN_SHIFT) +#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) +#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) +#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) +#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) +#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) +#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) +#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) +#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) +#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) +#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) +#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) +#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) +#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) +#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) +#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) +#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) +#define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) +#define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) +#define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) +#define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) +#define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) +#define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) +#define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) +#define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) +#define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) +#define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) +#define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) +#define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) +#define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) +#define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) +#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) +#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) + +/* Pad Mux Register Index: + * + * 3322 2222 2222 1111 1111 1100 0000 0000 + * 1098 7654 3210 9876 5432 1098 7654 3210 + * PERIPHERAL .... .... IIII IIII .... .... .... .... + */ + +#define GPIO_PADMUX_SHIFT (16) +#define GPIO_PADMUX_MASK (0xfff << GPIO_PADMUX_SHIFT) +# define GPIO_PADMUX(n) ((uint32_t)(n) << GPIO_PADMUX_SHIFT) +#define GPIO_PADMUX_GET(n) ((n&GPIO_PADMUX_MASK) >> GPIO_PADMUX_SHIFT) + +/* IOC PAD CTL Configuration + * + * 3322 2222 2222 1111 1111 1100 0000 0000 + * 1098 7654 3210 9876 5432 1098 7654 3210 + * ENCODING .... .... .... .... MMMM MMMM MMMM MMMM + * + */ + +#define GPIO_IOCPAD_SHIFT (0) +#define GPIO_IOCPAD_MASK (0xffff << GPIO_IOCPAD_SHIFT) + +#define HPM_GPIO_GPIOA (0) +#define HPM_GPIO_GPIOB (1) +#define HPM_GPIO_GPIOC (2) +#define HPM_GPIO_GPIOX (3) +#define HPM_GPIO_GPIOY (4) +#define HPM_GPIO_GPIOZ (5) + +#define HPM_GPIO_DI_VAL(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0000) +#define HPM_GPIO_DI_SET(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0004) +#define HPM_GPIO_DI_CLR(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0008) +#define HPM_GPIO_DI_TOG(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x000c) + +#define HPM_GPIO_DO_VAL(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0100) +#define HPM_GPIO_DO_SET(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0104) +#define HPM_GPIO_DO_CLR(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0108) +#define HPM_GPIO_DO_TOG(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x010c) + +#define HPM_GPIO_OE_VAL(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0200) +#define HPM_GPIO_OE_SET(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0204) +#define HPM_GPIO_OE_CLR(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0208) +#define HPM_GPIO_OE_TOG(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x020c) + +#define HPM_GPIO_IF_VAL(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0300) +#define HPM_GPIO_IF_SET(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0304) +#define HPM_GPIO_IF_CLR(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0308) +#define HPM_GPIO_IF_TOG(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x030c) + +#define HPM_GPIO_IE_VAL(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0400) +#define HPM_GPIO_IE_SET(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0404) +#define HPM_GPIO_IE_CLR(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0408) +#define HPM_GPIO_IE_TOG(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x040c) + +#define HPM_GPIO_PL_VAL(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0500) +#define HPM_GPIO_PL_SET(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0504) +#define HPM_GPIO_PL_CLR(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0508) +#define HPM_GPIO_PL_TOG(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x050c) + +#define HPM_GPIO_TP_VAL(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0600) +#define HPM_GPIO_TP_SET(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0604) +#define HPM_GPIO_TP_CLR(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0608) +#define HPM_GPIO_TP_TOG(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x060c) + +#define HPM_GPIO_AS_VAL(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0700) +#define HPM_GPIO_AS_SET(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0704) +#define HPM_GPIO_AS_CLR(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x0708) +#define HPM_GPIO_AS_TOG(n) (HPM_GPIO0_BASE + (n) * 0x10 + 0x070c) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* The smallest integer type that can hold the GPIO encoding */ + +typedef uint32_t gpio_pinset_t; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: mpfs_configgpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + * Returned Value: + * OK on success + * ERROR on invalid port. + * + ****************************************************************************/ + +int hpm_gpio_config(gpio_pinset_t pinset); + +/**************************************************************************** + * Name: mpfs_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void hpm_gpio_write(gpio_pinset_t pinset, bool value); + +/**************************************************************************** + * Name: mpfs_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool hpm_gpio_read(gpio_pinset_t pinset); + +/**************************************************************************** + * Name: mpfs_gpiosetevent + * + * Description: + * Sets/clears GPIO based event and interrupt triggers. + * + * Input Parameters: + * - pinset: GPIO pin configuration + * - risingedge: Enables interrupt on rising edges + * - fallingedge: Enables interrupt on falling edges + * - high: Enables interrupt on level high + * - low: Enables interrupt on level low + * - event: Generate event when set + * - func: When non-NULL, generate interrupt + * - arg: Argument passed to the interrupt callback + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure indicating the + * nature of the failure. + * + ****************************************************************************/ + +int hpm_gpiosetevent(gpio_pinset_t pinset, bool risingedge, + bool fallingedge, bool high, bool low, bool event, + xcpt_t func, void *arg); + +/**************************************************************************** + * Name: mpfs_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int hpm_gpio_initialize(void); + +/**************************************************************************** + * Function: mpfs_dumpgpio + * + * Description: + * Dump all GPIO registers associated with the provided base address + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_GPIO_INFO +int hpm_dumpgpio(gpio_pinset_t pinset, const char *msg); +#else +#define hpm_dumpgpio(p, m) +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_GPIO_H */ diff --git a/arch/risc-v/src/hpm6000/hpm_head.S b/arch/risc-v/src/hpm6000/hpm_head.S new file mode 100644 index 0000000000000..300512b2bbc18 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_head.S @@ -0,0 +1,77 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_head.S + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "chip.h" +#include "hpm_memorymap.h" +#include "riscv_internal.h" + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + /* Imported symbols */ + + .extern __trap_vec + + .section .text + .global __start + +__start: + /* reset mstatus to 0*/ + + csrrw x0, CSR_MSTATUS, x0 + + /* Set stack pointer to the idle thread stack */ + + la sp, HPM_IDLESTACK_TOP + + /* Disable all interrupts (i.e. timer, external) in mie */ + + csrw CSR_MIE, zero + csrw CSR_MIP, zero + + /* Initialize the Machine Trap Vector */ + + la t0, __trap_vec + csrw CSR_MTVEC, t0 + + /* Jump to __hpm_start */ + + jal x1, __hpm_start + + /* We shouldn't return from __hpm_start */ + + .global _init + .global _fini + +_init: +_fini: + + /* These don't have to do anything since we use init_array/fini_array. */ + + ret + diff --git a/arch/risc-v/src/hpm6000/hpm_ioc.c b/arch/risc-v/src/hpm6000/hpm_ioc.c new file mode 100644 index 0000000000000..0c2f674adfc6e --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_ioc.c @@ -0,0 +1,281 @@ +/*************************************************************************** + * arch/risc-v/src/hpm6000/hpm_ioc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ***************************************************************************/ + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "hardware/hpm_ioc.h" +#include "riscv_internal.h" +#include "hpm_ioc.h" + +/*************************************************************************** + * Private Data + ***************************************************************************/ + +/* This table is indexed by the Pad Mux register index and provides the + * index to the corresponding Pad Control register. + * + * REVISIT: This could be greatly simplified: The Pad Control registers + * map 1-to-1 with the Pad Mux registers except for two regions where + * there are no corresponding Pad Mux registers. The entire table could be + * replaced to two range checks and the appropriate offset added to the Pad + * Mux Register index. + */ + +#if defined (CONFIG_ARCH_FAMILY_HPM6300) +static const uint16_t g_iocctl_map[HPM_IOC_PAD_NREGISTERS] = +{ + HPM_IOC_PAD_PA00_INDEX, + HPM_IOC_PAD_PA01_INDEX, + HPM_IOC_PAD_PA02_INDEX, + HPM_IOC_PAD_PA03_INDEX, + HPM_IOC_PAD_PA04_INDEX, + HPM_IOC_PAD_PA05_INDEX, + HPM_IOC_PAD_PA06_INDEX, + HPM_IOC_PAD_PA07_INDEX, + HPM_IOC_PAD_PA08_INDEX, + HPM_IOC_PAD_PA09_INDEX, + HPM_IOC_PAD_PA10_INDEX, + HPM_IOC_PAD_PA11_INDEX, + HPM_IOC_PAD_PA12_INDEX, + HPM_IOC_PAD_PA13_INDEX, + HPM_IOC_PAD_PA14_INDEX, + HPM_IOC_PAD_PA15_INDEX, + HPM_IOC_PAD_PA16_INDEX, + HPM_IOC_PAD_PA17_INDEX, + HPM_IOC_PAD_PA18_INDEX, + HPM_IOC_PAD_PA19_INDEX, + HPM_IOC_PAD_PA20_INDEX, + HPM_IOC_PAD_PA21_INDEX, + HPM_IOC_PAD_PA22_INDEX, + HPM_IOC_PAD_PA23_INDEX, + HPM_IOC_PAD_PA24_INDEX, + HPM_IOC_PAD_PA25_INDEX, + HPM_IOC_PAD_PA26_INDEX, + HPM_IOC_PAD_PA27_INDEX, + HPM_IOC_PAD_PA28_INDEX, + HPM_IOC_PAD_PA29_INDEX, + HPM_IOC_PAD_PA30_INDEX, + HPM_IOC_PAD_PA31_INDEX, + HPM_IOC_PAD_PB00_INDEX, + HPM_IOC_PAD_PB01_INDEX, + HPM_IOC_PAD_PB02_INDEX, + HPM_IOC_PAD_PB03_INDEX, + HPM_IOC_PAD_PB04_INDEX, + HPM_IOC_PAD_PB05_INDEX, + HPM_IOC_PAD_PB06_INDEX, + HPM_IOC_PAD_PB07_INDEX, + HPM_IOC_PAD_PB08_INDEX, + HPM_IOC_PAD_PB09_INDEX, + HPM_IOC_PAD_PB10_INDEX, + HPM_IOC_PAD_PB11_INDEX, + HPM_IOC_PAD_PB12_INDEX, + HPM_IOC_PAD_PB13_INDEX, + HPM_IOC_PAD_PB14_INDEX, + HPM_IOC_PAD_PB15_INDEX, + HPM_IOC_PAD_PB16_INDEX, + HPM_IOC_PAD_PB17_INDEX, + HPM_IOC_PAD_PB18_INDEX, + HPM_IOC_PAD_PB19_INDEX, + HPM_IOC_PAD_PB20_INDEX, + HPM_IOC_PAD_PB21_INDEX, + HPM_IOC_PAD_PB22_INDEX, + HPM_IOC_PAD_PB23_INDEX, + HPM_IOC_PAD_PB24_INDEX, + HPM_IOC_PAD_PB25_INDEX, + HPM_IOC_PAD_PB26_INDEX, + HPM_IOC_PAD_PB27_INDEX, + HPM_IOC_PAD_PB28_INDEX, + HPM_IOC_PAD_PB29_INDEX, + HPM_IOC_PAD_PB30_INDEX, + HPM_IOC_PAD_PB31_INDEX, + HPM_IOC_PAD_PC00_INDEX, + HPM_IOC_PAD_PC01_INDEX, + HPM_IOC_PAD_PC02_INDEX, + HPM_IOC_PAD_PC03_INDEX, + HPM_IOC_PAD_PC04_INDEX, + HPM_IOC_PAD_PC05_INDEX, + HPM_IOC_PAD_PC06_INDEX, + HPM_IOC_PAD_PC07_INDEX, + HPM_IOC_PAD_PC08_INDEX, + HPM_IOC_PAD_PC09_INDEX, + HPM_IOC_PAD_PC10_INDEX, + HPM_IOC_PAD_PC11_INDEX, + HPM_IOC_PAD_PC12_INDEX, + HPM_IOC_PAD_PC13_INDEX, + HPM_IOC_PAD_PC14_INDEX, + HPM_IOC_PAD_PC15_INDEX, + HPM_IOC_PAD_PC16_INDEX, + HPM_IOC_PAD_PC17_INDEX, + HPM_IOC_PAD_PC18_INDEX, + HPM_IOC_PAD_PC19_INDEX, + HPM_IOC_PAD_PC20_INDEX, + HPM_IOC_PAD_PC21_INDEX, + HPM_IOC_PAD_PC22_INDEX, + HPM_IOC_PAD_PC23_INDEX, + HPM_IOC_PAD_PC24_INDEX, + HPM_IOC_PAD_PC25_INDEX, + HPM_IOC_PAD_PC26_INDEX, + HPM_IOC_PAD_PC27_INDEX, + HPM_IOC_PAD_PX00_INDEX, + HPM_IOC_PAD_PX01_INDEX, + HPM_IOC_PAD_PX02_INDEX, + HPM_IOC_PAD_PX03_INDEX, + HPM_IOC_PAD_PX04_INDEX, + HPM_IOC_PAD_PX05_INDEX, + HPM_IOC_PAD_PX06_INDEX, + HPM_IOC_PAD_PX07_INDEX, + HPM_IOC_PAD_PY00_INDEX, + HPM_IOC_PAD_PY01_INDEX, + HPM_IOC_PAD_PY02_INDEX, + HPM_IOC_PAD_PY03_INDEX, + HPM_IOC_PAD_PY04_INDEX, + HPM_IOC_PAD_PY05_INDEX, + HPM_IOC_PAD_PY06_INDEX, + HPM_IOC_PAD_PY07_INDEX, + HPM_IOC_PAD_PZ00_INDEX, + HPM_IOC_PAD_PZ01_INDEX, + HPM_IOC_PAD_PZ02_INDEX, + HPM_IOC_PAD_PZ03_INDEX, + HPM_IOC_PAD_PZ04_INDEX, + HPM_IOC_PAD_PZ05_INDEX, + HPM_IOC_PAD_PZ06_INDEX, + HPM_IOC_PAD_PZ07_INDEX, +}; +#endif + +/*************************************************************************** + * Public Functions + ***************************************************************************/ + +unsigned int hpm_iocpad_map(unsigned int iocpad) +{ + return (unsigned int)g_iocctl_map[iocpad]; +} + +int hpm_iocpad_configure(uintptr_t padctl, ioc_pinset_t ioset) +{ + uint32_t regval = 0; + uint32_t value; + uint32_t alt; + uintptr_t funcctl; + + /* Select CMOS input or Schmitt Trigger input */ + + if ((ioset & PAD_SCHMITT_TRIGGER) != 0) + { + regval |= IOC_PAD_PAD_HYS; + } + + /* Select drive strength */ + + value = (ioset & PAD_DRIVE_MASK) >> PAD_DRIVE_SHIFT; + regval |= IOC_PAD_PAD_DS(value); + + /* Select speed */ + + value = (ioset & PAD_SPEED_MASK) >> PAD_SPEED_SHIFT; + regval |= IOC_PAD_PAD_SPD(value); + + /* Select CMOS output or Open Drain output */ + + if ((ioset & PAD_OPENDRAIN) != 0) + { + regval |= IOC_PAD_PAD_OD; + } + + /* Handle pull/keep selection */ + + switch (ioset & _PAD_PULLTYPE_MASK) + { + default: + break; + + case _PAD_PULL_KEEP: + { + regval |= IOC_PAD_PAD_KE; + } + break; + + case _PAD_PULL_ENABLE: + { + regval |= (IOC_PAD_PAD_KE | IOC_PAD_PAD_PE); + if ((ioset & _PAD_PULLTYPE_MASK) != _PAD_PULL_DOWN_100K) + { + regval |= IOC_PAD_PAD_PS; + } + + value = (ioset & _PAD_PULLDESC_MASK) >> _PAD_PULLDESC_SHIFT; + regval |= IOC_PAD_PAD_PRS(value); + } + break; + } + + /* Select slow/fast slew rate */ + + if ((ioset & PAD_SLEW_FAST) != 0) + { + regval |= IOC_PAD_PAD_SR; + } + + /* Write the result to the specified Pad Control register */ + + putreg32(regval, padctl); + + /* Configure IOC FUNCTL Register */ + + funcctl = padctl - 0x0004; + regval = 0; + + /* Configure analog */ + + if ((ioset & FUNC_ANALOG_MASK) == FUNC_ANALOG) + { + regval |= IOC_PAD_FUNC_ANALOG; + putreg32(regval, funcctl); + + return OK; + } + + if ((ioset & PAD_ALT_MASK) == PAD_ALT0) + { + regval |= IOC_PAD_FUNC_LOOP_BACK; + putreg32(regval, funcctl); + + return OK; + } + + alt = (ioset & PAD_ALT_MASK) >> PAD_ALT_SHIFT; + regval |= IOC_PAD_FUNC_ALT_SELECT(alt); + + putreg32(regval, funcctl); + + return OK; +} diff --git a/arch/risc-v/src/hpm6000/hpm_ioc.h b/arch/risc-v/src/hpm6000/hpm_ioc.h new file mode 100644 index 0000000000000..d878315ddbad9 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_ioc.h @@ -0,0 +1,185 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_ioc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + + #ifndef __ARCH_RISCV_SRC_HPM6000_HPM_IOC_H + #define __ARCH_RISCV_SRC_HPM6000_HPM_IOC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "hardware/hpm_memorymap.h" +#include "hardware/hpm_ioc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* 16-bit Encoding: + * + * AAAA ARRR ODDD LSST + */ + +/* Peripheral Alternate Function: + * AAAA A... .... .... + */ + +#define PAD_ALT_SHIFT (11) /* Bits 11-15: Peripheral alternate function */ +#define PAD_ALT_MASK (0x1f << PAD_ALT_SHIFT) +# define PAD_ALT0 (0 << PAD_ALT_SHIFT) +# define PAD_ALT1 (1 << PAD_ALT_SHIFT) +# define PAD_ALT2 (2 << PAD_ALT_SHIFT) +# define PAD_ALT3 (3 << PAD_ALT_SHIFT) +# define PAD_ALT4 (4 << PAD_ALT_SHIFT) +# define PAD_ALT5 (5 << PAD_ALT_SHIFT) +# define PAD_ALT6 (6 << PAD_ALT_SHIFT) +# define PAD_ALT7 (7 << PAD_ALT_SHIFT) +# define PAD_ALT8 (8 << PAD_ALT_SHIFT) +# define PAD_ALT9 (9 << PAD_ALT_SHIFT) +# define PAD_ALT10 (10 << PAD_ALT_SHIFT) +# define PAD_ALT11 (11 << PAD_ALT_SHIFT) +# define PAD_ALT12 (12 << PAD_ALT_SHIFT) +# define PAD_ALT13 (13 << PAD_ALT_SHIFT) +# define PAD_ALT14 (14 << PAD_ALT_SHIFT) +# define PAD_ALT15 (15 << PAD_ALT_SHIFT) +# define PAD_ALT16 (16 << PAD_ALT_SHIFT) +# define PAD_ALT17 (17 << PAD_ALT_SHIFT) +# define PAD_ALT18 (18 << PAD_ALT_SHIFT) +# define PAD_ALT19 (19 << PAD_ALT_SHIFT) +# define PAD_ALT20 (20 << PAD_ALT_SHIFT) +# define PAD_ALT21 (21 << PAD_ALT_SHIFT) +# define PAD_ALT22 (22 << PAD_ALT_SHIFT) +# define PAD_ALT23 (23 << PAD_ALT_SHIFT) +# define PAD_ALT24 (24 << PAD_ALT_SHIFT) +# define PAD_ALT25 (25 << PAD_ALT_SHIFT) +# define PAD_ALT26 (26 << PAD_ALT_SHIFT) +# define PAD_ALT27 (27 << PAD_ALT_SHIFT) +# define PAD_ALT28 (28 << PAD_ALT_SHIFT) +# define PAD_ALT29 (29 << PAD_ALT_SHIFT) +# define PAD_ALT30 (30 << PAD_ALT_SHIFT) +# define PAD_ALT31 (31 << PAD_ALT_SHIFT) + +/* Output Pull Up/Down: + * + * .... RRRR .... .... + */ + +#define _PAD_PULLTYPE_SHIFT (8) /* Bits 8: Pull up/down type */ +#define _PAD_PULLTYPE_MASK (1 << _PAD_PULLTYPE_SHIFT) +# define _PAD_PULL_KEEP (0 << _PAD_PULLTYPE_SHIFT) /* Output determined by keeper */ +# define _PAD_PULL_ENABLE (1 << _PAD_PULLTYPE_SHIFT) /* Output pulled up or down */ + +#define _PAD_PULLDESC_SHIFT (9) /* Bits 9-10: Pull up/down description */ +#define _PAD_PULLDESC_MASK (3 << _PAD_PULLDESC_SHIFT) +# define _PAD_PULL_UP_22K (PULL_UP_22K << _PAD_PULLDESC_SHIFT) /* Pull up with 22 KOhm resister */ +# define _PAD_PULL_UP_47K (PULL_UP_47K << _PAD_PULLDESC_SHIFT) /* Pull up with 47 KOhm resister */ +# define _PAD_PULL_UP_100K (PULL_UP_100K << _PAD_PULLDESC_SHIFT) /* Pull up with 100 KOhm resister */ +# define _PAD_PULL_DOWN_100K (PULL_DOWN_100K << _PAD_PULLDESC_SHIFT) /* Pull down with 100 KOhm resister */ + +#define PAD_PULL_SHIFT (8) /* Bits 8-10: Pull up/down selection */ +#define PAD_PULL_MASK (15 << PAD_PULL_SHIFT) +# define PAD_PULL_KEEP _PAD_PULL_KEEP +# define PAD_PULL_UP_22K (_PAD_PULL_ENABLE | _PAD_PULL_UP_22K) +# define PAD_PULL_UP_47K (_PAD_PULL_ENABLE | _PAD_PULL_UP_47K) +# define PAD_PULL_UP_100K (_PAD_PULL_ENABLE | _PAD_PULL_UP_100K) +# define PAD_PULL_DOWN_100K (_PAD_PULL_ENABLE | _PAD_PULL_DOWN_100K) + +/* Open Drain Output: + * + * .... .... O... .... + */ + +#define PAD_CMOS_OUTPUT (0) /* Bit 7: 0=CMOS output */ +#define PAD_OPENDRAIN (1 << 7) /* Bit 7: 1=Enable open-drain output */ + +/* Output Drive Strength: + * + * .... .... .DDD .... + */ + +#define PAD_DRIVE_SHIFT (4) /* Bits 4-6: Output Drive Strength */ +#define PAD_DRIVE_MASK (7 << PAD_DRIVE_SHIFT) +# define PAD_DRIVE_260OHM (DRIVE_260OHM << PAD_DRIVE_SHIFT) /* 150 Ohm @3.3V, 260 Ohm @1.8V */ +# define PAD_DRIVE_130OHM (DRIVE_130OHM << PAD_DRIVE_SHIFT) /* 75 Ohm @3.3V, 130 Ohm @1.8V */ +# define PAD_DRIVE_88OHM (DRIVE_88OHM << PAD_DRIVE_SHIFT) /* 50 Ohm @3.3V, 90 Ohm @1.8V */ +# define PAD_DRIVE_65OHM (DRIVE_65OHM << PAD_DRIVE_SHIFT) /* 37 Ohm @3.3V, 60 Ohm @1.8V */ +# define PAD_DRIVE_52OHM (DRIVE_52OHM << PAD_DRIVE_SHIFT) /* 30 Ohm @3.3V, 50 Ohm @1.8V */ +# define PAD_DRIVE_43OHM (DRIVE_43OHM << PAD_DRIVE_SHIFT) /* 25 Ohm @3.3V, 40 Ohm @1.8V */ +# define PAD_DRIVE_37OHM (DRIVE_37OHM << PAD_DRIVE_SHIFT) /* 20 Ohm @3.3V, 33 Ohm @1.8V */ + +/* Analog pin + * + * .... .... .DDD .... + */ +#define FUNC_ANALOG_SHIFT (4) +#define FUNC_ANALOG_MASK (7 << FUNC_ANALOG_SHIFT) +#define FUNC_ANALOG (1 << FUNC_ANALOG_SHIFT) + +/* Output Slew Rate: + * + * .... .... .... L... + */ + +#define PAD_SLEW_SLOW (0) /* Bit 3: 0=Slow Slew Rate */ +#define PAD_SLEW_FAST (1 << 3) /* Bit 3: 1=Fast Slew Rate */ + +/* Output Speed: + * + * .... .... .... .SS. + */ + +#define PAD_SPEED_SHIFT (1) /* Bits 1-2: Speed */ +#define PAD_SPEED_MASK (3 << PAD_SPEED_SHIFT) +# define PAD_SPEED_SLOW (SPEED_SLOW << PAD_SPEED_SHIFT) /* Low frequency (50 MHz) */ +# define PAD_SPEED_MEDIUM (SPEED_MEDIUM << PAD_SPEED_SHIFT) /* Medium frequency (100, 150 MHz) */ +# define PAD_SPEED_FAST (SPEED_FAST << PAD_SPEED_SHIFT) /* Fast frequency */ +# define PAD_SPEED_MAX (SPEED_MAX << PAD_SPEED_SHIFT) /* Maximum frequency (100, 150, 200 MHz) */ + +/* Input Schmitt Trigger: + * + * .... .... .... ...T + */ + +#define PAD_CMOS_INPUT (0) /* Bit 0: 0=CMOS input */ +#define PAD_SCHMITT_TRIGGER (1 << 0) /* Bit 0: 1=Enable Schmitt trigger if input */ + +#define IOC_FUNC_CTL_(port, pin) (HPM_IOC_BASE + port * 0x0100 + pin * 0x0008 + 0x0000) +#define IOC_PAD_CTL_(port, pin) (HPM_IOC_BASE + port * 0x0100 + pin * 0x0008 + 0x0004) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* The smallest integer type that can hold the IOMUX encoding */ + +typedef uint16_t ioc_pinset_t; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +unsigned int hpm_iocpad_map(unsigned int iocpad); +int hpm_iocpad_configure(uintptr_t padctl, ioc_pinset_t ioset); + +#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_IOC_H */ diff --git a/arch/risc-v/src/hpm6000/hpm_iomux.h b/arch/risc-v/src/hpm6000/hpm_iomux.h new file mode 100644 index 0000000000000..1d17d0a44093a --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_iomux.h @@ -0,0 +1,976 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_iomux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_IOMUX_H +#define __ARCH_RISCV_SRC_HPM6000_HPM_IOMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/hpm_ioc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IOC_PA00_FUNC_CTL function mux definitions */ +#define IOC_PA00_FUNC_CTL_GPIO_A_00 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA00_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA00_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA00_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PA00_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_ALT_SELECT(17) + +/* IOC_PA01_FUNC_CTL function mux definitions */ +#define IOC_PA01_FUNC_CTL_GPIO_A_01 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA01_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PA01_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_ALT_SELECT(17) + +/* IOC_PA02_FUNC_CTL function mux definitions */ +#define IOC_PA02_FUNC_CTL_GPIO_A_02 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA02_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA02_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PA02_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_ALT_SELECT(17) + +/* IOC_PA03_FUNC_CTL function mux definitions */ +#define IOC_PA03_FUNC_CTL_GPIO_A_03 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA03_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA03_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA03_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PA03_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_ALT_SELECT(17) + +/* IOC_PA04_FUNC_CTL function mux definitions */ +#define IOC_PA04_FUNC_CTL_GPIO_A_04 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA04_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA04_FUNC_CTL_SPI3_DAT3 IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA04_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PA04_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PA04_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_ALT_SELECT(17) + +/* IOC_PA05_FUNC_CTL function mux definitions */ +#define IOC_PA05_FUNC_CTL_GPIO_A_05 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA05_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA05_FUNC_CTL_SPI3_DAT2 IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA05_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PA05_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PA05_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_ALT_SELECT(17) + +/* IOC_PA06_FUNC_CTL function mux definitions */ +#define IOC_PA06_FUNC_CTL_GPIO_A_06 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA06_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PA06_FUNC_CTL_UART2_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA06_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PA06_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PA06_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA06_FUNC_CTL_XPI0_CA_CS1 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PA06_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_ALT_SELECT(18) + +/* IOC_PA07_FUNC_CTL function mux definitions */ +#define IOC_PA07_FUNC_CTL_GPIO_A_07 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA07_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PA07_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PA07_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PA07_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA07_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PA07_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_ALT_SELECT(18) + +/* IOC_PA08_FUNC_CTL function mux definitions */ +#define IOC_PA08_FUNC_CTL_GPIO_A_08 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA08_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PA08_FUNC_CTL_UART3_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA08_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PA08_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PA08_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA08_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PA08_FUNC_CTL_XPI0_CB_D_0 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PA08_FUNC_CTL_SDC0_DATA_2 IOC_PAD_FUNC_ALT_SELECT(17) +#define IOC_PA08_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_ALT_SELECT(18) + +/* IOC_PA09_FUNC_CTL function mux definitions */ +#define IOC_PA09_FUNC_CTL_GPIO_A_09 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA09_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PA09_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PA09_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PA09_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA09_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PA09_FUNC_CTL_XPI0_CB_D_2 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PA09_FUNC_CTL_SDC0_DATA_3 IOC_PAD_FUNC_ALT_SELECT(17) +#define IOC_PA09_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_ALT_SELECT(18) + +/* IOC_PA10_FUNC_CTL function mux definitions */ +#define IOC_PA10_FUNC_CTL_GPIO_A_10 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA10_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PA10_FUNC_CTL_UART4_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA10_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PA10_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA10_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PA10_FUNC_CTL_XPI0_CB_D_1 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PA10_FUNC_CTL_SDC0_CMD IOC_PAD_FUNC_ALT_SELECT(17) +#define IOC_PA10_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_ALT_SELECT(18) + +/* IOC_PA11_FUNC_CTL function mux definitions */ +#define IOC_PA11_FUNC_CTL_GPIO_A_11 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA11_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PA11_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PA11_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA11_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PA11_FUNC_CTL_XPI0_CB_SCLK IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PA11_FUNC_CTL_SDC0_CLK IOC_PAD_FUNC_ALT_SELECT(17) +#define IOC_PA11_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_ALT_SELECT(18) + +/* IOC_PA12_FUNC_CTL function mux definitions */ +#define IOC_PA12_FUNC_CTL_GPIO_A_12 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA12_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PA12_FUNC_CTL_UART5_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA12_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PA12_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA12_FUNC_CTL_XPI0_CB_D_3 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PA12_FUNC_CTL_SDC0_DATA_0 IOC_PAD_FUNC_ALT_SELECT(17) +#define IOC_PA12_FUNC_CTL_ETH0_REFCLK IOC_PAD_FUNC_ALT_SELECT(18) + +/* IOC_PA13_FUNC_CTL function mux definitions */ +#define IOC_PA13_FUNC_CTL_GPIO_A_13 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA13_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PA13_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PA13_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA13_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PA13_FUNC_CTL_XPI0_CB_DQS IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PA13_FUNC_CTL_SDC0_DATA_1 IOC_PAD_FUNC_ALT_SELECT(17) +#define IOC_PA13_FUNC_CTL_ETH0_RXER IOC_PAD_FUNC_ALT_SELECT(18) +#define IOC_PA13_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_ALT_SELECT(19) +#define IOC_PA13_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PA14_FUNC_CTL function mux definitions */ +#define IOC_PA14_FUNC_CTL_GPIO_A_14 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA14_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA14_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA14_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PA14_FUNC_CTL_XPI0_CB_CS1 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PA14_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PA14_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_ALT_SELECT(17) +#define IOC_PA14_FUNC_CTL_ETH0_RXD_3 IOC_PAD_FUNC_ALT_SELECT(18) +#define IOC_PA14_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_ALT_SELECT(19) +#define IOC_PA14_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PA15_FUNC_CTL function mux definitions */ +#define IOC_PA15_FUNC_CTL_GPIO_A_15 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA15_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA15_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA15_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PA15_FUNC_CTL_XPI0_CB_CS0 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PA15_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PA15_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_ALT_SELECT(17) +#define IOC_PA15_FUNC_CTL_ETH0_RXD_2 IOC_PAD_FUNC_ALT_SELECT(18) +#define IOC_PA15_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_ALT_SELECT(19) +#define IOC_PA15_FUNC_CTL_SYSCTL_CLK_OBS_3 IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PA16_FUNC_CTL function mux definitions */ +#define IOC_PA16_FUNC_CTL_GPIO_A_16 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA16_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA16_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA16_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PA16_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PA16_FUNC_CTL_SDC0_VSEL IOC_PAD_FUNC_ALT_SELECT(17) +#define IOC_PA16_FUNC_CTL_ETH0_RXCK IOC_PAD_FUNC_ALT_SELECT(18) +#define IOC_PA16_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_ALT_SELECT(19) +#define IOC_PA16_FUNC_CTL_SYSCTL_CLK_OBS_2 IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PA17_FUNC_CTL function mux definitions */ +#define IOC_PA17_FUNC_CTL_GPIO_A_17 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA17_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA17_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA17_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PA17_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PA17_FUNC_CTL_ETH0_RXD_1 IOC_PAD_FUNC_ALT_SELECT(18) +#define IOC_PA17_FUNC_CTL_SYSCTL_CLK_OBS_1 IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PA18_FUNC_CTL function mux definitions */ +#define IOC_PA18_FUNC_CTL_GPIO_A_18 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA18_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA18_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA18_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PA18_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PA18_FUNC_CTL_ETH0_RXD_0 IOC_PAD_FUNC_ALT_SELECT(18) +#define IOC_PA18_FUNC_CTL_SYSCTL_CLK_OBS_0 IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PA19_FUNC_CTL function mux definitions */ +#define IOC_PA19_FUNC_CTL_GPIO_A_19 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA19_FUNC_CTL_GPTMR0_CAPT_0 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PA19_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA19_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PA19_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA19_FUNC_CTL_DAOR_P IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PA19_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PA19_FUNC_CTL_ETH0_RXDV IOC_PAD_FUNC_ALT_SELECT(18) + +/* IOC_PA20_FUNC_CTL function mux definitions */ +#define IOC_PA20_FUNC_CTL_GPIO_A_20 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA20_FUNC_CTL_GPTMR0_CAPT_1 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PA20_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA20_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PA20_FUNC_CTL_DAOR_N IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PA20_FUNC_CTL_TRGM1_P_00 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PA20_FUNC_CTL_ETH0_TXD_0 IOC_PAD_FUNC_ALT_SELECT(18) + +/* IOC_PA21_FUNC_CTL function mux definitions */ +#define IOC_PA21_FUNC_CTL_GPIO_A_21 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA21_FUNC_CTL_GPTMR0_COMP_0 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PA21_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA21_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PA21_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PA21_FUNC_CTL_DAOL_P IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PA21_FUNC_CTL_TRGM1_P_01 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PA21_FUNC_CTL_ETH0_TXD_1 IOC_PAD_FUNC_ALT_SELECT(18) + +/* IOC_PA22_FUNC_CTL function mux definitions */ +#define IOC_PA22_FUNC_CTL_GPIO_A_22 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA22_FUNC_CTL_GPTMR0_COMP_1 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PA22_FUNC_CTL_UART6_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA22_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PA22_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PA22_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PA22_FUNC_CTL_DAOL_N IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PA22_FUNC_CTL_TRGM1_P_02 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PA22_FUNC_CTL_ETH0_REFCLK IOC_PAD_FUNC_ALT_SELECT(18) + +/* IOC_PA23_FUNC_CTL function mux definitions */ +#define IOC_PA23_FUNC_CTL_GPIO_A_23 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA23_FUNC_CTL_GPTMR1_CAPT_0 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PA23_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PA23_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PA23_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PA23_FUNC_CTL_FEMC_CS_1 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PA23_FUNC_CTL_TRGM1_P_03 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PA23_FUNC_CTL_ETH0_TXEN IOC_PAD_FUNC_ALT_SELECT(18) + +/* IOC_PA24_FUNC_CTL function mux definitions */ +#define IOC_PA24_FUNC_CTL_GPIO_A_24 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA24_FUNC_CTL_GPTMR1_CAPT_1 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PA24_FUNC_CTL_UART7_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA24_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PA24_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PA24_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PA24_FUNC_CTL_FEMC_SCLK IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PA24_FUNC_CTL_TRGM1_P_04 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PA24_FUNC_CTL_ETH0_TXD_2 IOC_PAD_FUNC_ALT_SELECT(18) + +/* IOC_PA25_FUNC_CTL function mux definitions */ +#define IOC_PA25_FUNC_CTL_GPIO_A_25 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA25_FUNC_CTL_GPTMR1_COMP_0 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PA25_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PA25_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PA25_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PA25_FUNC_CTL_FEMC_DQ_07 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PA25_FUNC_CTL_TRGM1_P_05 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PA25_FUNC_CTL_ETH0_TXD_3 IOC_PAD_FUNC_ALT_SELECT(18) +#define IOC_PA25_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_ALT_SELECT(19) + +/* IOC_PA26_FUNC_CTL function mux definitions */ +#define IOC_PA26_FUNC_CTL_GPIO_A_26 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA26_FUNC_CTL_GPTMR1_COMP_1 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PA26_FUNC_CTL_UART0_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA26_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PA26_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PA26_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PA26_FUNC_CTL_FEMC_DQ_06 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PA26_FUNC_CTL_TRGM1_P_06 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PA26_FUNC_CTL_ETH0_CRS IOC_PAD_FUNC_ALT_SELECT(18) +#define IOC_PA26_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_ALT_SELECT(19) + +/* IOC_PA27_FUNC_CTL function mux definitions */ +#define IOC_PA27_FUNC_CTL_GPIO_A_27 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA27_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PA27_FUNC_CTL_FEMC_DQ_05 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PA27_FUNC_CTL_TRGM1_P_07 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PA27_FUNC_CTL_ETH0_COL IOC_PAD_FUNC_ALT_SELECT(18) + +/* IOC_PA28_FUNC_CTL function mux definitions */ +#define IOC_PA28_FUNC_CTL_GPIO_A_28 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA28_FUNC_CTL_UART1_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA28_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PA28_FUNC_CTL_SPI0_CSN IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA28_FUNC_CTL_FEMC_DQ_04 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PA28_FUNC_CTL_TRGM1_P_08 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PA29_FUNC_CTL function mux definitions */ +#define IOC_PA29_FUNC_CTL_GPIO_A_29 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA29_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PA29_FUNC_CTL_SPI0_MISO IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA29_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PA29_FUNC_CTL_FEMC_DQ_03 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PA29_FUNC_CTL_TRGM1_P_09 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PA30_FUNC_CTL function mux definitions */ +#define IOC_PA30_FUNC_CTL_GPIO_A_30 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA30_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA30_FUNC_CTL_SPI0_SCLK IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA30_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PA30_FUNC_CTL_FEMC_DQ_02 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PA30_FUNC_CTL_TRGM1_P_10 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PA31_FUNC_CTL function mux definitions */ +#define IOC_PA31_FUNC_CTL_GPIO_A_31 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PA31_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PA31_FUNC_CTL_SPI0_MOSI IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PA31_FUNC_CTL_FEMC_DQ_01 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PA31_FUNC_CTL_TRGM1_P_11 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB00_FUNC_CTL function mux definitions */ +#define IOC_PB00_FUNC_CTL_GPIO_B_00 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB00_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB00_FUNC_CTL_SPI0_DAT2 IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB00_FUNC_CTL_FEMC_DQ_00 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB00_FUNC_CTL_PWM1_P_0 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB01_FUNC_CTL function mux definitions */ +#define IOC_PB01_FUNC_CTL_GPIO_B_01 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB01_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB01_FUNC_CTL_SPI0_DAT3 IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB01_FUNC_CTL_FEMC_DM_0 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB01_FUNC_CTL_PWM1_P_1 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB02_FUNC_CTL function mux definitions */ +#define IOC_PB02_FUNC_CTL_GPIO_B_02 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB02_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB02_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB02_FUNC_CTL_FEMC_DQ_08 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB02_FUNC_CTL_PWM1_P_2 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB03_FUNC_CTL function mux definitions */ +#define IOC_PB03_FUNC_CTL_GPIO_B_03 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB03_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB03_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB03_FUNC_CTL_FEMC_DQ_09 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB03_FUNC_CTL_XPI1_CB_CS0 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PB03_FUNC_CTL_PWM1_P_3 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB04_FUNC_CTL function mux definitions */ +#define IOC_PB04_FUNC_CTL_GPIO_B_04 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB04_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB04_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB04_FUNC_CTL_FEMC_DQ_10 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB04_FUNC_CTL_XPI1_CB_CS1 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PB04_FUNC_CTL_PWM1_P_4 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB05_FUNC_CTL function mux definitions */ +#define IOC_PB05_FUNC_CTL_GPIO_B_05 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB05_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB05_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB05_FUNC_CTL_FEMC_DQ_11 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB05_FUNC_CTL_XPI1_CB_DQS IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PB05_FUNC_CTL_PWM1_P_5 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB06_FUNC_CTL function mux definitions */ +#define IOC_PB06_FUNC_CTL_GPIO_B_06 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB06_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB06_FUNC_CTL_FEMC_DQ_12 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB06_FUNC_CTL_XPI1_CB_D_3 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PB06_FUNC_CTL_PWM1_P_6 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB07_FUNC_CTL function mux definitions */ +#define IOC_PB07_FUNC_CTL_GPIO_B_07 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB07_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB07_FUNC_CTL_SPI1_DAT2 IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB07_FUNC_CTL_FEMC_DQ_13 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB07_FUNC_CTL_XPI1_CB_D_1 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PB07_FUNC_CTL_PWM1_P_7 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB08_FUNC_CTL function mux definitions */ +#define IOC_PB08_FUNC_CTL_GPIO_B_08 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB08_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB08_FUNC_CTL_SPI1_DAT3 IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB08_FUNC_CTL_FEMC_DQ_14 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB08_FUNC_CTL_XPI1_CB_SCLK IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PB08_FUNC_CTL_PWM1_FAULT_0 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB09_FUNC_CTL function mux definitions */ +#define IOC_PB09_FUNC_CTL_GPIO_B_09 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB09_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB09_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB09_FUNC_CTL_FEMC_DQ_15 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB09_FUNC_CTL_XPI1_CB_D_2 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PB09_FUNC_CTL_PWM1_FAULT_1 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB10_FUNC_CTL function mux definitions */ +#define IOC_PB10_FUNC_CTL_GPIO_B_10 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB10_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB10_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB10_FUNC_CTL_FEMC_DM_1 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB10_FUNC_CTL_XPI1_CB_D_0 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PB10_FUNC_CTL_PWM0_FAULT_1 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB11_FUNC_CTL function mux definitions */ +#define IOC_PB11_FUNC_CTL_GPIO_B_11 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB11_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB11_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB11_FUNC_CTL_FEMC_WE IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB11_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PB11_FUNC_CTL_PWM0_FAULT_0 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB12_FUNC_CTL function mux definitions */ +#define IOC_PB12_FUNC_CTL_GPIO_B_12 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB12_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB12_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB12_FUNC_CTL_FEMC_CAS IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB12_FUNC_CTL_XPI1_CA_D_0 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PB12_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB13_FUNC_CTL function mux definitions */ +#define IOC_PB13_FUNC_CTL_GPIO_B_13 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB13_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB13_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB13_FUNC_CTL_FEMC_RAS IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB13_FUNC_CTL_XPI1_CA_D_2 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PB13_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB14_FUNC_CTL function mux definitions */ +#define IOC_PB14_FUNC_CTL_GPIO_B_14 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB14_FUNC_CTL_UART6_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB14_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PB14_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB14_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PB14_FUNC_CTL_FEMC_CS_0 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB14_FUNC_CTL_XPI1_CA_SCLK IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PB14_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB15_FUNC_CTL function mux definitions */ +#define IOC_PB15_FUNC_CTL_GPIO_B_15 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB15_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PB15_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB15_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PB15_FUNC_CTL_FEMC_BA0 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB15_FUNC_CTL_XPI1_CA_D_1 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PB15_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB16_FUNC_CTL function mux definitions */ +#define IOC_PB16_FUNC_CTL_GPIO_B_16 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB16_FUNC_CTL_UART7_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB16_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PB16_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB16_FUNC_CTL_FEMC_BA1 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB16_FUNC_CTL_XPI1_CA_D_3 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PB16_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB17_FUNC_CTL function mux definitions */ +#define IOC_PB17_FUNC_CTL_GPIO_B_17 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB17_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PB17_FUNC_CTL_FEMC_A_10 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB17_FUNC_CTL_XPI1_CA_CS0 IOC_PAD_FUNC_ALT_SELECT(14) +#define IOC_PB17_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB18_FUNC_CTL function mux definitions */ +#define IOC_PB18_FUNC_CTL_GPIO_B_18 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB18_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PB18_FUNC_CTL_UART0_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB18_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PB18_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PB18_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PB18_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PB18_FUNC_CTL_FEMC_A_00 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB18_FUNC_CTL_PWM0_P_6 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB19_FUNC_CTL function mux definitions */ +#define IOC_PB19_FUNC_CTL_GPIO_B_19 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB19_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PB19_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PB19_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PB19_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PB19_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PB19_FUNC_CTL_FEMC_A_01 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB19_FUNC_CTL_PWM0_P_7 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB20_FUNC_CTL function mux definitions */ +#define IOC_PB20_FUNC_CTL_GPIO_B_20 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB20_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PB20_FUNC_CTL_UART1_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB20_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PB20_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PB20_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PB20_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PB20_FUNC_CTL_FEMC_A_02 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB20_FUNC_CTL_TRGM0_P_00 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB21_FUNC_CTL function mux definitions */ +#define IOC_PB21_FUNC_CTL_GPIO_B_21 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB21_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PB21_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PB21_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PB21_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PB21_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PB21_FUNC_CTL_FEMC_A_03 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB21_FUNC_CTL_TRGM0_P_01 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB22_FUNC_CTL function mux definitions */ +#define IOC_PB22_FUNC_CTL_GPIO_B_22 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB22_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PB22_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB22_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PB22_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PB22_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PB22_FUNC_CTL_FEMC_CLK IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB22_FUNC_CTL_TRGM0_P_02 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PB22_FUNC_CTL_SOC_REF0 IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PB23_FUNC_CTL function mux definitions */ +#define IOC_PB23_FUNC_CTL_GPIO_B_23 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB23_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PB23_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB23_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PB23_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PB23_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PB23_FUNC_CTL_FEMC_CKE IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB23_FUNC_CTL_TRGM0_P_03 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PB23_FUNC_CTL_SOC_REF1 IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PB24_FUNC_CTL function mux definitions */ +#define IOC_PB24_FUNC_CTL_GPIO_B_24 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB24_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PB24_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB24_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PB24_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PB24_FUNC_CTL_FEMC_A_12 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB24_FUNC_CTL_TRGM0_P_04 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB25_FUNC_CTL function mux definitions */ +#define IOC_PB25_FUNC_CTL_GPIO_B_25 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB25_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PB25_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB25_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PB25_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PB25_FUNC_CTL_FEMC_A_11 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB25_FUNC_CTL_TRGM0_P_05 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB26_FUNC_CTL function mux definitions */ +#define IOC_PB26_FUNC_CTL_GPIO_B_26 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB26_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB26_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PB26_FUNC_CTL_FEMC_A_09 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB26_FUNC_CTL_TRGM0_P_06 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB27_FUNC_CTL function mux definitions */ +#define IOC_PB27_FUNC_CTL_GPIO_B_27 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB27_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB27_FUNC_CTL_SPI1_CSN IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB27_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PB27_FUNC_CTL_FEMC_A_08 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB27_FUNC_CTL_TRGM0_P_07 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB28_FUNC_CTL function mux definitions */ +#define IOC_PB28_FUNC_CTL_GPIO_B_28 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB28_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB28_FUNC_CTL_SPI1_MISO IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB28_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PB28_FUNC_CTL_FEMC_A_07 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB28_FUNC_CTL_TRGM0_P_08 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB29_FUNC_CTL function mux definitions */ +#define IOC_PB29_FUNC_CTL_GPIO_B_29 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB29_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB29_FUNC_CTL_SPI1_SCLK IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB29_FUNC_CTL_I2S0_TXD_3 IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PB29_FUNC_CTL_FEMC_A_06 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB29_FUNC_CTL_TRGM0_P_09 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB30_FUNC_CTL function mux definitions */ +#define IOC_PB30_FUNC_CTL_GPIO_B_30 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB30_FUNC_CTL_UART2_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PB30_FUNC_CTL_UART2_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PB30_FUNC_CTL_SPI1_MOSI IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB30_FUNC_CTL_I2S0_TXD_2 IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PB30_FUNC_CTL_FEMC_A_05 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB30_FUNC_CTL_TRGM0_P_10 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PB31_FUNC_CTL function mux definitions */ +#define IOC_PB31_FUNC_CTL_GPIO_B_31 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PB31_FUNC_CTL_UART2_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PB31_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PB31_FUNC_CTL_I2S0_TXD_1 IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PB31_FUNC_CTL_FEMC_A_04 IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PB31_FUNC_CTL_TRGM0_P_11 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PC00_FUNC_CTL function mux definitions */ +#define IOC_PC00_FUNC_CTL_GPIO_C_00 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC00_FUNC_CTL_UART3_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC00_FUNC_CTL_UART3_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PC00_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC00_FUNC_CTL_I2S0_TXD_0 IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PC00_FUNC_CTL_FEMC_SRDY IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PC00_FUNC_CTL_PWM0_P_0 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PC00_FUNC_CTL_USB0_ID IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PC01_FUNC_CTL function mux definitions */ +#define IOC_PC01_FUNC_CTL_GPIO_C_01 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC01_FUNC_CTL_UART3_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PC01_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC01_FUNC_CTL_I2S0_BCLK IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PC01_FUNC_CTL_FEMC_DQS IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PC01_FUNC_CTL_PWM0_P_1 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PC01_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PC02_FUNC_CTL function mux definitions */ +#define IOC_PC02_FUNC_CTL_GPIO_C_02 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC02_FUNC_CTL_UART4_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC02_FUNC_CTL_UART4_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PC02_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC02_FUNC_CTL_I2S0_FCLK IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PC02_FUNC_CTL_PWM0_P_2 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PC02_FUNC_CTL_USB0_OC IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PC03_FUNC_CTL function mux definitions */ +#define IOC_PC03_FUNC_CTL_GPIO_C_03 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC03_FUNC_CTL_UART4_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PC03_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC03_FUNC_CTL_I2S0_MCLK IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PC03_FUNC_CTL_I2S1_TXD_3 IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC03_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PC03_FUNC_CTL_PWM0_P_3 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PC04_FUNC_CTL function mux definitions */ +#define IOC_PC04_FUNC_CTL_GPIO_C_04 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC04_FUNC_CTL_UART5_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC04_FUNC_CTL_UART5_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PC04_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC04_FUNC_CTL_I2S0_RXD_0 IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PC04_FUNC_CTL_I2S1_TXD_2 IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC04_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PC04_FUNC_CTL_PWM0_P_4 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PC05_FUNC_CTL function mux definitions */ +#define IOC_PC05_FUNC_CTL_GPIO_C_05 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC05_FUNC_CTL_UART5_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PC05_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC05_FUNC_CTL_I2S0_RXD_1 IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PC05_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC05_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PC05_FUNC_CTL_PWM0_P_5 IOC_PAD_FUNC_ALT_SELECT(16) +#define IOC_PC05_FUNC_CTL_USB0_OC IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PC06_FUNC_CTL function mux definitions */ +#define IOC_PC06_FUNC_CTL_GPIO_C_06 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC06_FUNC_CTL_GPTMR2_CAPT_0 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PC06_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC06_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC06_FUNC_CTL_I2S0_RXD_2 IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PC06_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC06_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PC06_FUNC_CTL_USB0_ID IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PC07_FUNC_CTL function mux definitions */ +#define IOC_PC07_FUNC_CTL_GPIO_C_07 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC07_FUNC_CTL_GPTMR2_CAPT_1 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PC07_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC07_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC07_FUNC_CTL_I2S0_RXD_3 IOC_PAD_FUNC_ALT_SELECT(8) +#define IOC_PC07_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC07_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PC07_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_ALT_SELECT(19) +#define IOC_PC07_FUNC_CTL_USB0_OC IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PC08_FUNC_CTL function mux definitions */ +#define IOC_PC08_FUNC_CTL_GPIO_C_08 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC08_FUNC_CTL_GPTMR2_COMP_0 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PC08_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC08_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC08_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC08_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PC08_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_ALT_SELECT(19) +#define IOC_PC08_FUNC_CTL_USB0_PWR IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PC09_FUNC_CTL function mux definitions */ +#define IOC_PC09_FUNC_CTL_GPIO_C_09 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC09_FUNC_CTL_GPTMR2_COMP_1 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PC09_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC09_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PC09_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PC09_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC09_FUNC_CTL_DAOR_N IOC_PAD_FUNC_ALT_SELECT(10) + +/* IOC_PC10_FUNC_CTL function mux definitions */ +#define IOC_PC10_FUNC_CTL_GPIO_C_10 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC10_FUNC_CTL_GPTMR3_CAPT_0 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PC10_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC10_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PC10_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PC10_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC10_FUNC_CTL_DAOR_P IOC_PAD_FUNC_ALT_SELECT(10) + +/* IOC_PC11_FUNC_CTL function mux definitions */ +#define IOC_PC11_FUNC_CTL_GPIO_C_11 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC11_FUNC_CTL_GPTMR3_CAPT_1 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PC11_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC11_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PC11_FUNC_CTL_CAN0_STBY IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PC11_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC11_FUNC_CTL_DAOL_N IOC_PAD_FUNC_ALT_SELECT(10) + +/* IOC_PC12_FUNC_CTL function mux definitions */ +#define IOC_PC12_FUNC_CTL_GPIO_C_12 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC12_FUNC_CTL_GPTMR3_COMP_0 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PC12_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC12_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PC12_FUNC_CTL_CAN1_STBY IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PC12_FUNC_CTL_I2S1_RXD_2 IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC12_FUNC_CTL_DAOL_P IOC_PAD_FUNC_ALT_SELECT(10) + +/* IOC_PC13_FUNC_CTL function mux definitions */ +#define IOC_PC13_FUNC_CTL_GPIO_C_13 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC13_FUNC_CTL_GPTMR3_COMP_1 IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PC13_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC13_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PC13_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PC13_FUNC_CTL_I2S1_RXD_3 IOC_PAD_FUNC_ALT_SELECT(9) + +/* IOC_PC14_FUNC_CTL function mux definitions */ +#define IOC_PC14_FUNC_CTL_GPIO_C_14 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC14_FUNC_CTL_UART6_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC14_FUNC_CTL_UART6_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PC14_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PC14_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PC14_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC14_FUNC_CTL_ACMP_COMP_0 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PC15_FUNC_CTL function mux definitions */ +#define IOC_PC15_FUNC_CTL_GPIO_C_15 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC15_FUNC_CTL_UART6_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PC15_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PC15_FUNC_CTL_ACMP_COMP_1 IOC_PAD_FUNC_ALT_SELECT(16) + +/* IOC_PC16_FUNC_CTL function mux definitions */ +#define IOC_PC16_FUNC_CTL_GPIO_C_16 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC16_FUNC_CTL_UART7_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC16_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PC16_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PC16_FUNC_CTL_I2S1_TXD_3 IOC_PAD_FUNC_ALT_SELECT(9) + +/* IOC_PC17_FUNC_CTL function mux definitions */ +#define IOC_PC17_FUNC_CTL_GPIO_C_17 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC17_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PC17_FUNC_CTL_I2S1_TXD_2 IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC17_FUNC_CTL_PDM0_D_1 IOC_PAD_FUNC_ALT_SELECT(10) + +/* IOC_PC18_FUNC_CTL function mux definitions */ +#define IOC_PC18_FUNC_CTL_GPIO_C_18 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC18_FUNC_CTL_UART0_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC18_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PC18_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC18_FUNC_CTL_I2S1_TXD_1 IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC18_FUNC_CTL_PDM0_D_0 IOC_PAD_FUNC_ALT_SELECT(10) + +/* IOC_PC19_FUNC_CTL function mux definitions */ +#define IOC_PC19_FUNC_CTL_GPIO_C_19 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC19_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PC19_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC19_FUNC_CTL_I2S1_TXD_0 IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC19_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_ALT_SELECT(10) + +/* IOC_PC20_FUNC_CTL function mux definitions */ +#define IOC_PC20_FUNC_CTL_GPIO_C_20 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC20_FUNC_CTL_UART1_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC20_FUNC_CTL_UART1_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PC20_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC20_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC20_FUNC_CTL_PDM0_D_3 IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PC20_FUNC_CTL_ETH0_EVTO_1 IOC_PAD_FUNC_ALT_SELECT(19) +#define IOC_PC20_FUNC_CTL_WDG0_RST IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PC21_FUNC_CTL function mux definitions */ +#define IOC_PC21_FUNC_CTL_GPIO_C_21 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC21_FUNC_CTL_UART1_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PC21_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC21_FUNC_CTL_I2S1_FCLK IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC21_FUNC_CTL_PDM0_D_2 IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PC21_FUNC_CTL_ETH0_EVTO_0 IOC_PAD_FUNC_ALT_SELECT(19) +#define IOC_PC21_FUNC_CTL_WDG1_RST IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PC22_FUNC_CTL function mux definitions */ +#define IOC_PC22_FUNC_CTL_GPIO_C_22 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC22_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC22_FUNC_CTL_SPI2_CSN IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC22_FUNC_CTL_I2S1_BCLK IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC22_FUNC_CTL_PDM0_CLK IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PC22_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_ALT_SELECT(17) +#define IOC_PC22_FUNC_CTL_ETH0_MDIO IOC_PAD_FUNC_ALT_SELECT(19) + +/* IOC_PC23_FUNC_CTL function mux definitions */ +#define IOC_PC23_FUNC_CTL_GPIO_C_23 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC23_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC23_FUNC_CTL_SPI2_MOSI IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC23_FUNC_CTL_I2S1_MCLK IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC23_FUNC_CTL_SDC0_VSEL IOC_PAD_FUNC_ALT_SELECT(17) +#define IOC_PC23_FUNC_CTL_ETH0_MDC IOC_PAD_FUNC_ALT_SELECT(19) + +/* IOC_PC24_FUNC_CTL function mux definitions */ +#define IOC_PC24_FUNC_CTL_GPIO_C_24 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC24_FUNC_CTL_UART1_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC24_FUNC_CTL_SPI2_MISO IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC24_FUNC_CTL_I2S1_RXD_0 IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC24_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_ALT_SELECT(17) + +/* IOC_PC25_FUNC_CTL function mux definitions */ +#define IOC_PC25_FUNC_CTL_GPIO_C_25 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC25_FUNC_CTL_UART1_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC25_FUNC_CTL_SPI2_SCLK IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC25_FUNC_CTL_I2S1_RXD_1 IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC25_FUNC_CTL_SDC0_WP IOC_PAD_FUNC_ALT_SELECT(17) + +/* IOC_PC26_FUNC_CTL function mux definitions */ +#define IOC_PC26_FUNC_CTL_GPIO_C_26 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC26_FUNC_CTL_UART2_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC26_FUNC_CTL_SPI2_DAT3 IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC26_FUNC_CTL_I2S1_RXD_2 IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC26_FUNC_CTL_SDC0_VSEL IOC_PAD_FUNC_ALT_SELECT(17) +#define IOC_PC26_FUNC_CTL_ETH0_EVTI_1 IOC_PAD_FUNC_ALT_SELECT(19) + +/* IOC_PC27_FUNC_CTL function mux definitions */ +#define IOC_PC27_FUNC_CTL_GPIO_C_27 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PC27_FUNC_CTL_UART2_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PC27_FUNC_CTL_SPI2_DAT2 IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PC27_FUNC_CTL_I2S1_RXD_3 IOC_PAD_FUNC_ALT_SELECT(9) +#define IOC_PC27_FUNC_CTL_SDC0_CDN IOC_PAD_FUNC_ALT_SELECT(17) +#define IOC_PC27_FUNC_CTL_ETH0_EVTI_0 IOC_PAD_FUNC_ALT_SELECT(19) + +/* IOC_PX00_FUNC_CTL function mux definitions */ +#define IOC_PX00_FUNC_CTL_GPIO_X_00 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PX00_FUNC_CTL_XPI0_CA_D_2 IOC_PAD_FUNC_ALT_SELECT(14) + +/* IOC_PX01_FUNC_CTL function mux definitions */ +#define IOC_PX01_FUNC_CTL_GPIO_X_01 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PX01_FUNC_CTL_XPI0_CA_D_1 IOC_PAD_FUNC_ALT_SELECT(14) + +/* IOC_PX02_FUNC_CTL function mux definitions */ +#define IOC_PX02_FUNC_CTL_GPIO_X_02 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PX02_FUNC_CTL_XPI0_CA_CS0 IOC_PAD_FUNC_ALT_SELECT(14) + +/* IOC_PX03_FUNC_CTL function mux definitions */ +#define IOC_PX03_FUNC_CTL_GPIO_X_03 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PX03_FUNC_CTL_XPI0_CA_D_0 IOC_PAD_FUNC_ALT_SELECT(14) + +/* IOC_PX04_FUNC_CTL function mux definitions */ +#define IOC_PX04_FUNC_CTL_GPIO_X_04 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PX04_FUNC_CTL_XPI0_CA_SCLK IOC_PAD_FUNC_ALT_SELECT(14) + +/* IOC_PX05_FUNC_CTL function mux definitions */ +#define IOC_PX05_FUNC_CTL_GPIO_X_05 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PX05_FUNC_CTL_XPI0_CA_D_3 IOC_PAD_FUNC_ALT_SELECT(14) + +/* IOC_PX06_FUNC_CTL function mux definitions */ +#define IOC_PX06_FUNC_CTL_GPIO_X_06 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PX06_FUNC_CTL_XPI0_CA_DQS IOC_PAD_FUNC_ALT_SELECT(14) + +/* IOC_PX07_FUNC_CTL function mux definitions */ +#define IOC_PX07_FUNC_CTL_GPIO_X_07 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PX07_FUNC_CTL_FEMC_DQS IOC_PAD_FUNC_ALT_SELECT(12) +#define IOC_PX07_FUNC_CTL_XPI1_CA_DQS IOC_PAD_FUNC_ALT_SELECT(14) + +/* IOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_GPIO_Y_00 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PY00_FUNC_CTL_UART7_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PY00_FUNC_CTL_UART7_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PY00_FUNC_CTL_SPI3_CSN IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PY00_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_ALT_SELECT(7) + +/* IOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_GPIO_Y_01 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PY01_FUNC_CTL_UART7_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PY01_FUNC_CTL_SPI3_MISO IOC_PAD_FUNC_ALT_SELECT(5) +#define IOC_PY01_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_ALT_SELECT(7) + +/* IOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_GPIO_Y_02 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PY02_FUNC_CTL_UART0_DE IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PY02_FUNC_CTL_UART0_RTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PY02_FUNC_CTL_SPI3_SCLK IOC_PAD_FUNC_ALT_SELECT(5) + +/* IOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_GPIO_Y_03 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PY03_FUNC_CTL_UART0_CTS IOC_PAD_FUNC_ALT_SELECT(3) +#define IOC_PY03_FUNC_CTL_SPI3_MOSI IOC_PAD_FUNC_ALT_SELECT(5) + +/* IOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_GPIO_Y_04 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PY04_FUNC_CTL_UART7_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PY04_FUNC_CTL_I2C0_SCL IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PY04_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PY04_FUNC_CTL_DAOR_P IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PY04_FUNC_CTL_WDG0_RST IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_GPIO_Y_05 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PY05_FUNC_CTL_UART7_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PY05_FUNC_CTL_I2C0_SDA IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PY05_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_ALT_SELECT(7) +#define IOC_PY05_FUNC_CTL_DAOR_N IOC_PAD_FUNC_ALT_SELECT(10) +#define IOC_PY05_FUNC_CTL_WDG1_RST IOC_PAD_FUNC_ALT_SELECT(24) + +/* IOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_GPIO_Y_06 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PY06_FUNC_CTL_UART0_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PY06_FUNC_CTL_I2C1_SCL IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PY06_FUNC_CTL_DAOL_P IOC_PAD_FUNC_ALT_SELECT(10) + +/* IOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_GPIO_Y_07 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PY07_FUNC_CTL_UART0_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PY07_FUNC_CTL_I2C1_SDA IOC_PAD_FUNC_ALT_SELECT(4) +#define IOC_PY07_FUNC_CTL_DAOL_N IOC_PAD_FUNC_ALT_SELECT(10) + +/* IOC_PZ00_FUNC_CTL function mux definitions */ +#define IOC_PZ00_FUNC_CTL_GPIO_Z_00 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PZ00_FUNC_CTL_UART3_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PZ00_FUNC_CTL_CAN0_TXD IOC_PAD_FUNC_ALT_SELECT(7) + +/* IOC_PZ01_FUNC_CTL function mux definitions */ +#define IOC_PZ01_FUNC_CTL_GPIO_Z_01 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PZ01_FUNC_CTL_UART3_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PZ01_FUNC_CTL_CAN0_RXD IOC_PAD_FUNC_ALT_SELECT(7) + +/* IOC_PZ02_FUNC_CTL function mux definitions */ +#define IOC_PZ02_FUNC_CTL_GPIO_Z_02 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PZ02_FUNC_CTL_UART4_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PZ02_FUNC_CTL_I2C2_SCL IOC_PAD_FUNC_ALT_SELECT(4) + +/* IOC_PZ03_FUNC_CTL function mux definitions */ +#define IOC_PZ03_FUNC_CTL_GPIO_Z_03 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PZ03_FUNC_CTL_UART4_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PZ03_FUNC_CTL_I2C2_SDA IOC_PAD_FUNC_ALT_SELECT(4) + +/* IOC_PZ04_FUNC_CTL function mux definitions */ +#define IOC_PZ04_FUNC_CTL_GPIO_Z_04 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PZ04_FUNC_CTL_UART5_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PZ04_FUNC_CTL_CAN1_TXD IOC_PAD_FUNC_ALT_SELECT(7) + +/* IOC_PZ05_FUNC_CTL function mux definitions */ +#define IOC_PZ05_FUNC_CTL_GPIO_Z_05 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PZ05_FUNC_CTL_UART5_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PZ05_FUNC_CTL_CAN1_RXD IOC_PAD_FUNC_ALT_SELECT(7) + +/* IOC_PZ06_FUNC_CTL function mux definitions */ +#define IOC_PZ06_FUNC_CTL_GPIO_Z_06 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PZ06_FUNC_CTL_UART6_TXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PZ06_FUNC_CTL_I2C3_SCL IOC_PAD_FUNC_ALT_SELECT(4) + +/* IOC_PZ07_FUNC_CTL function mux definitions */ +#define IOC_PZ07_FUNC_CTL_GPIO_Z_07 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PZ07_FUNC_CTL_UART6_RXD IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PZ07_FUNC_CTL_I2C3_SDA IOC_PAD_FUNC_ALT_SELECT(4) +#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_IOMUX_H */ \ No newline at end of file diff --git a/arch/risc-v/src/hpm6000/hpm_irq.c b/arch/risc-v/src/hpm6000/hpm_irq.c new file mode 100644 index 0000000000000..73de263464730 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_irq.c @@ -0,0 +1,213 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_irq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "riscv_internal.h" +#include "chip.h" +#include "hpm.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + /* Disable Machine interrupts */ + + up_irq_save(); + + /* Disable all global interrupts */ + + putreg32(0x0, HPM_PLIC_INTEN0); + putreg32(0x0, HPM_PLIC_INTEN1); + putreg32(0x0, HPM_PLIC_INTEN2); + putreg32(0x0, HPM_PLIC_INTEN3); + + /* Clear pendings in PLIC */ + + uint32_t val = getreg32(HPM_PLIC_CLAIM); + putreg32(val, HPM_PLIC_CLAIM); + + /* Colorize the interrupt stack for debug purposes */ + +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 15 + size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~15); + riscv_stack_color(g_intstackalloc, intstack_size); +#endif + + /* Set priority for all global interrupts to 1 (lowest) */ + + for (int id = 1; id <= 78; id++) + { + putreg32(1, HPM_PLIC_PRIORITY + (4 * id)); + } + + /* Set irq threshold to 0 (permits all global interrupts) */ + + putreg32(0, HPM_PLIC_THRESHOLD); + + /* Attach the common interrupt handler */ + + riscv_exception_attach(); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + + /* And finally, enable interrupts */ + + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + int extirq = 0; + + if (irq == RISCV_IRQ_MSOFT) + { + /* Read mstatus & clear machine software interrupt enable in mie */ + + CLEAR_CSR(CSR_MIE, MIE_MSIE); + } + else if (irq == RISCV_IRQ_MTIMER) + { + /* Read mstatus & clear machine timer interrupt enable in mie */ + + CLEAR_CSR(CSR_MIE, MIE_MTIE); + } + else if (irq >= HPM_IRQ_PERI_START) + { + extirq = irq - HPM_IRQ_PERI_START; + + /* Clear enable bit for the irq */ + + if (1 <= extirq && extirq <= 127) + { + modifyreg32(HPM_PLIC_INTEN0 + (4 * (extirq / 32)), + 1 << (extirq % 32), 0); + } + else + { + ASSERT(false); + } + } +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + int extirq; + + if (irq == RISCV_IRQ_MSOFT) + { + /* Read mstatus & set machine software interrupt enable in mie */ + + SET_CSR(CSR_MIE, MIE_MSIE); + } + else if (irq == RISCV_IRQ_MTIMER) + { + /* Read mstatus & set machine timer interrupt enable in mie */ + + SET_CSR(CSR_MIE, MIE_MTIE); + } + else if (irq >= HPM_IRQ_PERI_START) + { + extirq = irq - HPM_IRQ_PERI_START; + + /* Set enable bit for the irq */ + + if (1 <= extirq && extirq <= 127) + { + modifyreg32(HPM_PLIC_INTEN0 + (4 * (extirq / 32)), + 0, 1 << (extirq % 32)); + } + else + { + ASSERT(false); + } + } +} + +/**************************************************************************** + * Name: riscv_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void riscv_ack_irq(int irq) +{ +} + +/**************************************************************************** + * Name: up_irq_enable + * + * Description: + * Return the current interrupt state and enable interrupts + * + ****************************************************************************/ + +irqstate_t up_irq_enable(void) +{ + irqstate_t oldstat; + + /* Enable MEIE (machine external interrupt enable) */ + + /* TODO: should move to up_enable_irq() */ + + SET_CSR(CSR_MIE, MIE_MEIE); + + /* Read mstatus & set machine interrupt enable (MIE) in mstatus */ + + oldstat = READ_AND_SET_CSR(CSR_MSTATUS, MSTATUS_MIE); + return oldstat; +} diff --git a/arch/risc-v/src/hpm6000/hpm_irq_dispatch.c b/arch/risc-v/src/hpm6000/hpm_irq_dispatch.c new file mode 100644 index 0000000000000..5b103fc26eb21 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_irq_dispatch.c @@ -0,0 +1,87 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_irq_dispatch.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "riscv_internal.h" +#include "chip.h" +#include "hpm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RV_IRQ_MASK 27 + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * riscv_dispatch_irq + ****************************************************************************/ + +void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs) +{ + int irq = (vector >> RV_IRQ_MASK) | (vector & 0xf); + + /* Firstly, check if the irq is machine external interrupt */ + + if (RISCV_IRQ_MEXT == irq) + { + uint32_t val = getreg32(HPM_PLIC_CLAIM); + + /* Add the value to nuttx irq which is offset to the mext */ + + irq = val + HPM_IRQ_PERI_START; + } + + /* Acknowledge the interrupt */ + + riscv_ack_irq(irq); + + /* claim_irq was zero means no interrupt */ + + if (HPM_IRQ_PERI_START != irq) + { + /* Deliver the IRQ */ + + regs = riscv_doirq(irq, regs); + } + + if (HPM_IRQ_PERI_START <= irq) + { + /* Then write PLIC_CLAIM to clear pending in PLIC */ + + putreg32(irq - HPM_IRQ_PERI_START, HPM_PLIC_CLAIM); + } + + return regs; +} diff --git a/arch/risc-v/src/hpm6000/hpm_lowputc.c b/arch/risc-v/src/hpm6000/hpm_lowputc.c new file mode 100644 index 0000000000000..f9d06d6467058 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_lowputc.c @@ -0,0 +1,474 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_lowputc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "riscv_internal.h" +#include "chip.h" +#include "hpm.h" +#include "hpm_config.h" +#include "hpm_clockconfig.h" +#include "hpm_iomux.h" +#include "hardware/hpm_uart.h" +#include "hpm_gpio.h" +#include "hpm_lowputc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Select UART parameters for the selected console */ + +#ifdef HAVE_UART_CONSOLE +# if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define HPM_CONSOLE_BASE HPM_UART0_BASE +# define HPM_CONSOLE_BAUD CONFIG_UART0_BAUD +# define HPM_CONSOLE_BITS CONFIG_UART0_BITS +# define HPM_CONSOLE_PARITY CONFIG_UART0_PARITY +# define HPM_CONSOLE_2STOP CONFIG_UART0_2STOP +# define HPM_CONSOLE_CLOCKBIT SYSREG_SUBBLK_CLOCK_CR_MMUART0 +# define HPM_CONSOLE_RESETBIT SYSREG_SOFT_RESET_CR_MMUART0 +# define HAVE_UART +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define HPM_CONSOLE_BASE HPM_UART1_BASE +# define HPM_CONSOLE_BAUD CONFIG_UART1_BAUD +# define HPM_CONSOLE_BITS CONFIG_UART1_BITS +# define HPM_CONSOLE_PARITY CONFIG_UART1_PARITY +# define HPM_CONSOLE_2STOP CONFIG_UART1_2STOP +# define HPM_CONSOLE_CLOCKBIT SYSREG_SUBBLK_CLOCK_CR_MMUART1 +# define HPM_CONSOLE_RESETBIT SYSREG_SOFT_RESET_CR_MMUART1 +# define HAVE_UART +# elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define HPM_CONSOLE_BASE HPM_UART2_BASE +# define HPM_CONSOLE_BAUD CONFIG_UART2_BAUD +# define HPM_CONSOLE_BITS CONFIG_UART2_BITS +# define HPM_CONSOLE_PARITY CONFIG_UART2_PARITY +# define HPM_CONSOLE_2STOP CONFIG_UART2_2STOP +# define HPM_CONSOLE_CLOCKBIT SYSREG_SUBBLK_CLOCK_CR_MMUART2 +# define HPM_CONSOLE_RESETBIT SYSREG_SOFT_RESET_CR_MMUART2 +# define HAVE_UART +# elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define HPM_CONSOLE_BASE HPM_UART3_BASE +# define HPM_CONSOLE_BAUD CONFIG_UART3_BAUD +# define HPM_CONSOLE_BITS CONFIG_UART3_BITS +# define HPM_CONSOLE_PARITY CONFIG_UART3_PARITY +# define HPM_CONSOLE_2STOP CONFIG_UART3_2STOP +# define HPM_CONSOLE_CLOCKBIT SYSREG_SUBBLK_CLOCK_CR_MMUART3 +# define HPM_CONSOLE_RESETBIT SYSREG_SOFT_RESET_CR_MMUART3 +# define HAVE_UART +# elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define HPM_CONSOLE_BASE HPM_UART4_BASE +# define HPM_CONSOLE_BAUD CONFIG_UART4_BAUD +# define HPM_CONSOLE_BITS CONFIG_UART4_BITS +# define HPM_CONSOLE_PARITY CONFIG_UART4_PARITY +# define HPM_CONSOLE_2STOP CONFIG_UART4_2STOP +# define HPM_CONSOLE_CLOCKBIT SYSREG_SUBBLK_CLOCK_CR_MMUART4 +# define HPM_CONSOLE_RESETBIT SYSREG_SOFT_RESET_CR_MMUART4 +# define HAVE_UART +# elif defined(CONFIG_UART5_SERIAL_CONSOLE) +# define HPM_CONSOLE_BASE HPM_UART5_BASE +# define HPM_CONSOLE_BAUD CONFIG_UART5_BAUD +# define HPM_CONSOLE_BITS CONFIG_UART5_BITS +# define HPM_CONSOLE_PARITY CONFIG_UART5_PARITY +# define HPM_CONSOLE_2STOP CONFIG_UART5_2STOP +# define HPM_CONSOLE_CLOCKBIT SYSREG_SUBBLK_CLOCK_CR_MMUART5 +# define HPM_CONSOLE_RESETBIT SYSREG_SOFT_RESET_CR_MMUART5 +# define HAVE_UART +# elif defined(CONFIG_UART6_SERIAL_CONSOLE) +# define HPM_CONSOLE_BASE HPM_UART6_BASE +# define HPM_CONSOLE_BAUD CONFIG_UART6_BAUD +# define HPM_CONSOLE_BITS CONFIG_UART6_BITS +# define HPM_CONSOLE_PARITY CONFIG_UART6_PARITY +# define HPM_CONSOLE_2STOP CONFIG_UART6_2STOP +# define HPM_CONSOLE_CLOCKBIT SYSREG_SUBBLK_CLOCK_CR_MMUART6 +# define HPM_CONSOLE_RESETBIT SYSREG_SOFT_RESET_CR_MMUART6 +# define HAVE_UART +# elif defined(CONFIG_UART7_SERIAL_CONSOLE) +# define HPM_CONSOLE_BASE HPM_UART7_BASE +# define HPM_CONSOLE_BAUD CONFIG_UART7_BAUD +# define HPM_CONSOLE_BITS CONFIG_UART7_BITS +# define HPM_CONSOLE_PARITY CONFIG_UART7_PARITY +# define HPM_CONSOLE_2STOP CONFIG_UART7_2STOP +# define HPM_CONSOLE_CLOCKBIT SYSREG_SUBBLK_CLOCK_CR_MMUART7 +# define HPM_CONSOLE_RESETBIT SYSREG_SOFT_RESET_CR_MMUART7 +# define HAVE_UART +# elif defined(HAVE_UART) +# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting" +# endif +#endif /* HAVE_UART_CONSOLE */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#if !defined(CONFIG_SUPPRESS_UART_CONFIG) + +/**************************************************************************** + * Name: config_baud_divisors + * + * Description: + * Configure the UART baudrate divisors. + * + ****************************************************************************/ + +static bool hpm_uart_calculate_baudrate(uint32_t freq, uint32_t baudrate, + uint16_t *div_out, uint8_t *osc_out) +{ + uint16_t div; + uint16_t osc; + uint16_t delta; + float tmp; + + if ((div_out == NULL) || (!freq) || (!baudrate) + || (baudrate < HPM_UART_MINIMUM_BAUDRATE) + || (freq / HPM_UART_BAUDRATE_DIV_MIN < baudrate * HPM_UART_OSC_MIN) + || (freq / HPM_UART_BAUDRATE_DIV_MAX > (baudrate * HPM_UART_OSC_MAX))) + { + return 0; + } + + tmp = (float) freq / baudrate; + for (uint8_t i = 0; i < HPM_UART_OSC_MAX; i += 2) + { + /* osc range: 0 - 32, even number */ + + if (i == 0) + { + /* osc == 0 in bitfield, oversample rate is 32 */ + + osc = HPM_UART_OSC_MAX; + } + else if (i <= 8) + { + /* osc <= 8 in bitfield, oversample rate is 8 */ + + osc = HPM_UART_OSC_MIN; + } + else + { + /* osc > 8 && osc < 32 in bitfield, oversample rate is osc */ + + osc = i; + } + + delta = 0; + div = (uint16_t)(tmp / osc); + if (div < HPM_UART_BAUDRATE_DIV_MIN) + { + /* invalid div */ + + continue; + } + + if (div * osc > tmp) + { + delta = div * osc - tmp; + } + else if (div * osc < tmp) + { + delta = tmp - div * osc; + } + else + { + /* Do Nothing */ + } + + if (delta && ((delta * 100 / tmp) > HPM_UART_BAUDRATE_TOLERANCE)) + { + continue; + } + else + { + *div_out = div; + *osc_out = (i <= 8 && i) ? osc : i; + return true; + } + } + + return false; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: riscv_lowputc + * + * Description: + * Output one byte on the serial console + * + ****************************************************************************/ + +void riscv_lowputc(char ch) +{ +#if defined HAVE_UART_CONSOLE && defined HAVE_UART + + /* Wait until the TX data register is empty */ + + while ((getreg32(HPM_CONSOLE_BASE + HPM_UART_LSR_OFFSET) + & UART_LSR_THRE) == 0) + ; + + /* Then send the character */ + + putreg32(ch, HPM_CONSOLE_BASE + HPM_UART_THR_OFFSET); + +#endif +} + +/**************************************************************************** + * Name: hpm6750_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output available as soon + * as possible. + * + ****************************************************************************/ + +void hpm_lowsetup(void) +{ +#if defined(HAVE_UART_DEVICE) + + /* Enable and configure the selected console device */ + +#if defined(HAVE_UART_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG) + +#ifdef CONFIG_HPM_UART0 + hpm_gpio_config(GPIO_UART0_RXD); + hpm_gpio_config(GPIO_UART0_TXD); +#ifdef CONFIG_UART0_OFLOWCONTROL + hpm_gpio_config(GPIO_UART0_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_UART0_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART0_IFLOWCONTROL))) + hpm_config_gpio(GPIO_UART0_RTS); +#endif +#endif + +#ifdef CONFIG_HPM_UART1 + hpm_gpio_config(GPIO_UART1_RXD); + hpm_gpio_config(GPIO_UART1_TXD) +#ifdef CONFIG_UART1_OFLOWCONTROL + hpm_gpio_config(GPIO_UART1_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_UART1_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART1_IFLOWCONTROL))) + hpm_config_gpio(GPIO_UART1_RTS); +#endif +#endif + +#ifdef CONFIG_HPM_UART2 + hpm_gpio_config(GPIO_UART2_RXD); + hpm_gpio_config(GPIO_UART2_TXD) +#ifdef CONFIG_UART2_OFLOWCONTROL + hpm_gpio_config(GPIO_UART2_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_UART2_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART2_IFLOWCONTROL))) + hpm_config_gpio(GPIO_UART2_RTS); +#endif +#endif + +#ifdef CONFIG_HPM_UART3 + hpm_gpio_config(GPIO_UART3_RXD); + hpm_gpio_config(GPIO_UART3_TXD) +#ifdef CONFIG_UART3_OFLOWCONTROL + hpm_gpio_config(GPIO_UART3_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_UART3_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART3_IFLOWCONTROL))) + hpm_config_gpio(GPIO_UART3_RTS); +#endif +#endif + +#ifdef CONFIG_HPM_UART4 + hpm_gpio_config(GPIO_UART4_RXD); + hpm_gpio_config(GPIO_UART4_TXD) +#ifdef CONFIG_UART4_OFLOWCONTROL + hpm_gpio_config(GPIO_UART4_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_UART4_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART4_IFLOWCONTROL))) + hpm_config_gpio(GPIO_UART4_RTS); +#endif +#endif + +#ifdef CONFIG_HPM_UART5 + hpm_gpio_config(GPIO_UART5_RXD); + hpm_gpio_config(GPIO_UART5_TXD) +#ifdef CONFIG_UART5_OFLOWCONTROL + hpm_gpio_config(GPIO_UART5_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_UART5_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART5_IFLOWCONTROL))) + hpm_config_gpio(GPIO_UART5_RTS); +#endif +#endif + +#ifdef CONFIG_HPM_UART6 + hpm_gpio_config(GPIO_UART6_RXD); + hpm_gpio_config(GPIO_UART6_TXD) +#ifdef CONFIG_UART6_OFLOWCONTROL + hpm_gpio_config(GPIO_UART6_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_UART6_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART6_IFLOWCONTROL))) + hpm_config_gpio(GPIO_UART6_RTS); +#endif +#endif + +#ifdef CONFIG_HPM_UART7 + hpm_gpio_config(GPIO_UART7_RXD); + hpm_gpio_config(GPIO_UART7_TXD) +#ifdef CONFIG_UART7_OFLOWCONTROL + hpm_gpio_config(GPIO_UART7_CTS); +#endif +#if ((defined(CONFIG_SERIAL_RS485CONTROL) && defined(CONFIG_UART7_RS485RTSCONTROL)) || \ + (defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_UART7_IFLOWCONTROL))) + hpm_config_gpio(GPIO_UART7_RTS); +#endif +#endif + + hpm_uart_clockconfig(); + +#endif /* HAVE_UART_CONSOLE && !CONFIG_SUPPRESS_UART_CONFIG */ +#endif /* HAVE_UART */ +} + +/**************************************************************************** + * Name: hpm_uart_configure + * + * Description: + * Configure a UART for non-interrupt driven operation + * + ****************************************************************************/ + +#ifdef HAVE_UART_DEVICE +int hpm_uart_configure(uint32_t base, const struct uart_config_s *config) +{ + uint8_t osc = 0; + uint16_t div = 0; + uint8_t lcr = 0; + + /* disable all interrupts */ + + putreg32(0, base + HPM_UART_IER_OFFSET); + + /* set DLAB to 1 */ + + lcr = getreg32(base + HPM_UART_LCR_OFFSET) | UART_LCR_DLAB; + while ((getreg32(base + HPM_UART_LCR_OFFSET) & UART_LCR_DLAB) + != UART_LCR_DLAB) + { + putreg32(lcr, base + HPM_UART_LCR_OFFSET); + } + + hpm_uart_calculate_baudrate(24000000, config->baud, &div, &osc); + putreg32(osc, base + HPM_UART_OSCR_OFFSET); + putreg32(div & 0xff, base + HPM_UART_DLL_OFFSET); + putreg32(div >> 8, base + HPM_UART_DLM_OFFSET); + + /* DLAB bit needs to be cleared once baudrate is configured */ + + while ((getreg32(base + HPM_UART_LCR_OFFSET) & UART_LCR_DLAB) + == UART_LCR_DLAB) + { + lcr &= ~UART_LCR_DLAB; + putreg32(lcr, base + HPM_UART_LCR_OFFSET); + } + + lcr = 0; + switch (config->bits) + { + case 5: + lcr |= UART_LCR_WLS_5BITS; + break; + + case 6: + lcr |= UART_LCR_WLS_6BITS; + break; + + case 7: + lcr |= UART_LCR_WLS_7BITS; + break; + + case 8: + default: + lcr |= UART_LCR_WLS_8BITS; + break; + } + + if (config->stopbits2) + { + lcr |= UART_LCR_STB; + } + + if (config->parity == 1) + { + lcr |= UART_LCR_PEN; + } + else if (config->parity == 2) + { + lcr |= (UART_LCR_PEN | UART_LCR_EPS); + } + + putreg32(lcr, base + HPM_UART_LCR_OFFSET); + + return OK; +} + +#if defined (HAVE_UART_DEVICE) +void hpm_lowputc(int ch) +{ +#ifdef HAVE_UART_CONSOLE + while ((getreg32(HPM_CONSOLE_BASE + HPM_UART_LSR_OFFSET) & + UART_LSR_THRE) == 0) + { + } + + if (ch == '\n') + { + putreg32((uint32_t)'\r', HPM_CONSOLE_BASE + HPM_UART_THR_OFFSET); + while ((getreg32(HPM_CONSOLE_BASE + HPM_UART_LSR_OFFSET) & + UART_LSR_THRE) == 0) + { + } + } + + putreg32((uint32_t)ch, HPM_CONSOLE_BASE + HPM_UART_THR_OFFSET); +#endif +} +#endif +#endif /* HAVE_UART_DEVICE */ \ No newline at end of file diff --git a/arch/risc-v/src/hpm6000/hpm_lowputc.h b/arch/risc-v/src/hpm6000/hpm_lowputc.h new file mode 100644 index 0000000000000..a9a608e0adff3 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_lowputc.h @@ -0,0 +1,84 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_lowputc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_LOWPUTC_H +#define __ARCH_RISCV_SRC_HPM6000_HPM_LOWPUTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#ifdef HAVE_UART_DEVICE +/* This structure describes the configuration of an UART */ + +struct uart_config_s +{ + uint32_t baud; /* Configured baud */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (5-9) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ + bool userts; /* True: Assert RTS when there are data to be sent */ + bool invrts; /* True: Invert sense of RTS pin (true=active high) */ + bool usects; /* True: Condition transmission on CTS asserted */ + bool users485; /* True: Assert RTS while transmission progresses */ +}; +#endif + +/**************************************************************************** + * Name: hpm_lowsetup + ****************************************************************************/ + +EXTERN void hpm_lowsetup(void); + +#ifdef HAVE_UART_DEVICE +int hpm_uart_configure(uint32_t base, const struct uart_config_s *config); +#endif + +#ifdef HAVE_UART_DEVICE +void hpm_lowputc(int ch); +#else +# define hpm_lowputc(ch) +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_LOWPUTC_H */ diff --git a/arch/risc-v/src/hpm6000/hpm_memorymap.h b/arch/risc-v/src/hpm6000/hpm_memorymap.h new file mode 100644 index 0000000000000..9d42acaad848d --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_memorymap.h @@ -0,0 +1,50 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_MEMORYMAP_H +#define __ARCH_RISCV_SRC_HPM6000_HPM_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "riscv_common_memorymap.h" +#include "hardware/hpm_memorymap.h" +#include "hardware/hpm_uart.h" +#include "hardware/hpm_mchtmr.h" +#include "hardware/hpm_ioc.h" +#include "hardware/hpm_plic.h" +#include "hardware/hpm_sysctl.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Idle thread stack starts from _ebss */ + +#ifndef __ASSEMBLY__ +#define HPM_IDLESTACK_BASE (uintptr_t)_ebss +#else +#define HPM_IDLESTACK_BASE _ebss +#endif + +#define HPM_IDLESTACK_TOP (HPM_IDLESTACK_BASE + SMP_STACK_SIZE) + +#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_MEMORYMAP_H */ diff --git a/arch/risc-v/src/hpm6000/hpm_pmic_iomux.h b/arch/risc-v/src/hpm6000/hpm_pmic_iomux.h new file mode 100644 index 0000000000000..4aeec54366365 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_pmic_iomux.h @@ -0,0 +1,82 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_pmic_iomux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_PMIC_IOMUX_H +#define __ARCH_RISCV_SRC_HPM6000_HPM_PMIC_IOMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "hardware/hpm_ioc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* IOC_PY00_FUNC_CTL function mux definitions */ +#define IOC_PY00_FUNC_CTL_PGPIO_Y_00 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PY00_FUNC_CTL_JTAG_TDO IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PY00_FUNC_CTL_PTMR_COMP_0 IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PY00_FUNC_CTL_SOC_PY_00 IOC_PAD_FUNC_ALT_SELECT(3) + +/* IOC_PY01_FUNC_CTL function mux definitions */ +#define IOC_PY01_FUNC_CTL_PGPIO_Y_01 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PY01_FUNC_CTL_JTAG_TDI IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PY01_FUNC_CTL_PTMR_CAPT_0 IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PY01_FUNC_CTL_SOC_PY_01 IOC_PAD_FUNC_ALT_SELECT(3) + +/* IOC_PY02_FUNC_CTL function mux definitions */ +#define IOC_PY02_FUNC_CTL_PGPIO_Y_02 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PY02_FUNC_CTL_JTAG_TCK IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PY02_FUNC_CTL_PTMR_COMP_1 IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PY02_FUNC_CTL_SOC_PY_02 IOC_PAD_FUNC_ALT_SELECT(3) + +/* IOC_PY03_FUNC_CTL function mux definitions */ +#define IOC_PY03_FUNC_CTL_PGPIO_Y_03 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PY03_FUNC_CTL_JTAG_TMS IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PY03_FUNC_CTL_PTMR_CAPT_1 IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PY03_FUNC_CTL_SOC_PY_03 IOC_PAD_FUNC_ALT_SELECT(3) + +/* IOC_PY04_FUNC_CTL function mux definitions */ +#define IOC_PY04_FUNC_CTL_PGPIO_Y_04 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PY04_FUNC_CTL_JTAG_TRST IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PY04_FUNC_CTL_PTMR_COMP_2 IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PY04_FUNC_CTL_SOC_PY_04 IOC_PAD_FUNC_ALT_SELECT(3) + +/* IOC_PY05_FUNC_CTL function mux definitions */ +#define IOC_PY05_FUNC_CTL_PGPIO_Y_05 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PY05_FUNC_CTL_PWDG_RST IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PY05_FUNC_CTL_PTMR_CAPT_2 IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PY05_FUNC_CTL_SOC_PY_05 IOC_PAD_FUNC_ALT_SELECT(3) + +/* IOC_PY06_FUNC_CTL function mux definitions */ +#define IOC_PY06_FUNC_CTL_PGPIO_Y_06 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PY06_FUNC_CTL_PUART_TXD IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PY06_FUNC_CTL_PTMR_COMP_3 IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PY06_FUNC_CTL_SOC_PY_06 IOC_PAD_FUNC_ALT_SELECT(3) + +/* IOC_PY07_FUNC_CTL function mux definitions */ +#define IOC_PY07_FUNC_CTL_PGPIO_Y_07 IOC_PAD_FUNC_ALT_SELECT(0) +#define IOC_PY07_FUNC_CTL_PUART_RXD IOC_PAD_FUNC_ALT_SELECT(1) +#define IOC_PY07_FUNC_CTL_PTMR_CAPT_3 IOC_PAD_FUNC_ALT_SELECT(2) +#define IOC_PY07_FUNC_CTL_SOC_PY_07 IOC_PAD_FUNC_ALT_SELECT(3) + +#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_PMIC_IOMUX_H */ diff --git a/arch/risc-v/src/hpm6000/hpm_serial.c b/arch/risc-v/src/hpm6000/hpm_serial.c new file mode 100644 index 0000000000000..7db6c330499a0 --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_serial.c @@ -0,0 +1,1345 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_serial.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include + +#include "chip.h" +#include "riscv_internal.h" +#include "hardware/hpm_uart.h" +#include "hpm_gpio.h" +#include "hpm_config.h" +#include "hpm_lowputc.h" +#include "hpm_serial.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If we are not using the serial driver for the console, then we still must + * provide some minimal implementation of up_putc. + */ +#ifdef USE_SERIALDRIVER +/* Which UART with be tty0/console and which tty1? The console will always + * be ttyS0. If there is no console then will use the lowest numbered UART. + */ + +#ifdef HAVE_UART_CONSOLE +# if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0priv /* UART0 is console */ +# define TTYS0_DEV g_uart0priv /* UART0 is ttyS0 */ +# define SERIAL_CONSOLE 1 +# elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1priv /* UART1 is console */ +# define TTYS0_DEV g_uart1priv /* UART1 is ttyS0 */ +# define SERIAL_CONSOLE 2 +# elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart2priv /* UART2 is console */ +# define TTYS0_DEV g_uart2priv /* UART2 is ttyS0 */ +# define SERIAL_CONSOLE 3 +# elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart3priv /* UART3 is console */ +# define TTYS0_DEV g_uart3priv /* UART3 is ttyS0 */ +# define SERIAL_CONSOLE 4 +# elif defined(CONFIG_UART4_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart4priv /* UART4 is console */ +# define TTYS0_DEV g_uart4priv /* UART4 is ttyS0 */ +# define SERIAL_CONSOLE 5 +# elif defined(CONFIG_UART5_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart5priv /* UART5 is console */ +# define TTYS0_DEV g_uart5priv /* UART5 is ttyS0 */ +# define SERIAL_CONSOLE 6 +# elif defined(CONFIG_UART6_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart6priv /* UART6 is console */ +# define TTYS0_DEV g_uart6priv /* UART6 is ttyS0 */ +# define SERIAL_CONSOLE 7 +# elif defined(CONFIG_UART7_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart7priv /* UART7 is console */ +# define TTYS0_DEV g_uart7priv /* UART7 is ttyS0 */ +# define SERIAL_CONSOLE 8 +# else +# error "I'm confused... Do we have a serial console or not?" +# endif +#else +# undef CONSOLE_DEV /* No console */ +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef CONFIG_UART1_SERIAL_CONSOLE +# undef CONFIG_UART2_SERIAL_CONSOLE +# undef CONFIG_UART3_SERIAL_CONSOLE +# undef CONFIG_UART4_SERIAL_CONSOLE +# undef CONFIG_UART5_SERIAL_CONSOLE +# undef CONFIG_UART6_SERIAL_CONSOLE +# undef CONFIG_UART7_SERIAL_CONSOLE +# if defined(CONFIG_HPM_UART0) +# define TTYS0_DEV g_uart0priv /* UART0 is ttyS0 */ +# define SERIAL_CONSOLE 1 +# elif defined(CONFIG_HPM_UART1) +# define TTYS0_DEV g_uart1priv /* UART1 is ttyS0 */ +# define SERIAL_CONSOLE 2 +# elif defined(CONFIG_HPM_UART2) +# define TTYS0_DEV g_uart2priv /* UART2 is ttyS0 */ +# define SERIAL_CONSOLE 3 +# elif defined(CONFIG_HPM_UART3) +# define TTYS0_DEV g_uart3priv /* UART3 is ttyS0 */ +# define SERIAL_CONSOLE 4 +# elif defined(CONFIG_HPM_UART4) +# define TTYS0_DEV g_uart4priv /* UART4 is ttyS0 */ +# define SERIAL_CONSOLE 5 +# elif defined(CONFIG_HPM_UART5) +# define TTYS0_DEV g_uart5priv /* UART5 is ttyS0 */ +# define SERIAL_CONSOLE 6 +# elif defined(CONFIG_HPM_UART6) +# define TTYS0_DEV g_uart6priv /* UART6 is ttyS0 */ +# define SERIAL_CONSOLE 7 +# elif defined(CONFIG_HPM_UART7) +# define TTYS0_DEV g_uart7priv /* UART7 is ttyS0 */ +# define SERIAL_CONSOLE 8 +# else +# undef TTYS0_DEV +# endif +#endif + +/* Pick ttys1. This could be any of UART1-8 excluding the console UART. + * One of UART1-8 could be the console; one of UART1-8 has already been + * assigned to ttys0. + */ +#if defined(CONFIG_HPM_UART0) && (SERIAL_CONSOLE != 1) +# define TTYS1_DEV g_uart0priv /* UART0 is ttyS1 */ +# define SERIAL_CONSOLE 1 +#elif defined(CONFIG_HPM_UART1) && (SERIAL_CONSOLE != 2) +# define TTYS1_DEV g_uart1priv /* LPUART1 is ttyS1 */ +# define SERIAL_CONSOLE 2 +#elif defined(CONFIG_HPM_UART2) && (SERIAL_CONSOLE != 3) +# define TTYS1_DEV g_uart2priv /* LPUART2 is ttyS1 */ +# define SERIAL_CONSOLE 3 +#elif defined(CONFIG_HPM_UART3) && (SERIAL_CONSOLE != 4) +# define TTYS1_DEV g_uart3priv /* LPUART3 is ttyS1 */ +# define SERIAL_CONSOLE 4 +#elif defined(CONFIG_HPM_UART4) && (SERIAL_CONSOLE != 5) +# define TTYS1_DEV g_uart4priv /* LPUART4 is ttyS1 */ +# define SERIAL_CONSOLE 5 +#elif defined(CONFIG_HPM_UART5) && (SERIAL_CONSOLE != 6) +# define TTYS1_DEV g_uart5priv /* LPUART5 is ttyS1 */ +# define SERIAL_CONSOLE 6 +#elif defined(CONFIG_HPM_UART6) && (SERIAL_CONSOLE != 7) +# define TTYS1_DEV g_uart6priv /* LPUART6 is ttyS1 */ +# define SERIAL_CONSOLE 7 +#elif defined(CONFIG_HPM_UART7) && (SERIAL_CONSOLE != 8) +# define TTYS1_DEV g_uart7priv /* LPUART7 is ttyS1 */ +# define SERIAL_CONSOLE 8 +#endif + +#if defined(CONFIG_HPM_UART1) && (SERIAL_CONSOLE != 2) +# define TTYS2_DEV g_uart1priv /* LPUART1 is ttyS1 */ +# define SERIAL_CONSOLE 2 +#elif defined(CONFIG_HPM_UART2) && (SERIAL_CONSOLE != 3) +# define TTYS2_DEV g_uart2priv /* LPUART2 is ttyS1 */ +# define SERIAL_CONSOLE 3 +#elif defined(CONFIG_HPM_UART3) && (SERIAL_CONSOLE != 4) +# define TTYS2_DEV g_uart3priv /* LPUART3 is ttyS1 */ +# define SERIAL_CONSOLE 4 +#elif defined(CONFIG_HPM_UART4) && (SERIAL_CONSOLE != 5) +# define TTYS2_DEV g_uart4priv /* LPUART4 is ttyS1 */ +# define SERIAL_CONSOLE 5 +#elif defined(CONFIG_HPM_UART5) && (SERIAL_CONSOLE != 6) +# define TTYS2_DEV g_uart5priv /* LPUART5 is ttyS1 */ +# define SERIAL_CONSOLE 6 +#elif defined(CONFIG_HPM_UART6) && (SERIAL_CONSOLE != 7) +# define TTYS2_DEV g_uart6priv /* LPUART6 is ttyS1 */ +# define SERIAL_CONSOLE 7 +#elif defined(CONFIG_HPM_UART7) && (SERIAL_CONSOLE != 8) +# define TTYS2_DEV g_uart7priv /* LPUART7 is ttyS1 */ +# define SERIAL_CONSOLE 8 +#endif + +#if defined(CONFIG_HPM_UART2) && (SERIAL_CONSOLE != 3) +# define TTYS3_DEV g_uart2priv /* LPUART2 is ttyS1 */ +# define SERIAL_CONSOLE 3 +#elif defined(CONFIG_HPM_UART3) && (SERIAL_CONSOLE != 4) +# define TTYS3_DEV g_uart3priv /* LPUART3 is ttyS1 */ +# define SERIAL_CONSOLE 4 +#elif defined(CONFIG_HPM_UART4) && (SERIAL_CONSOLE != 5) +# define TTYS3_DEV g_uart4priv /* LPUART4 is ttyS1 */ +# define SERIAL_CONSOLE 5 +#elif defined(CONFIG_HPM_UART5) && (SERIAL_CONSOLE != 6) +# define TTYS3_DEV g_uart5priv /* LPUART5 is ttyS1 */ +# define SERIAL_CONSOLE 6 +#elif defined(CONFIG_HPM_UART6) && (SERIAL_CONSOLE != 7) +# define TTYS3_DEV g_uart6priv /* LPUART6 is ttyS1 */ +# define SERIAL_CONSOLE 7 +#elif defined(CONFIG_HPM_UART7) && (SERIAL_CONSOLE != 8) +# define TTYS3_DEV g_uart7priv /* LPUART7 is ttyS1 */ +# define SERIAL_CONSOLE 8 +#endif + +#if defined(CONFIG_HPM_UART3) && (SERIAL_CONSOLE != 4) +# define TTYS4_DEV g_uart3priv /* LPUART3 is ttyS1 */ +# define SERIAL_CONSOLE 4 +#elif defined(CONFIG_HPM_UART4) && (SERIAL_CONSOLE != 5) +# define TTYS4_DEV g_uart4priv /* LPUART4 is ttyS1 */ +# define SERIAL_CONSOLE 5 +#elif defined(CONFIG_HPM_UART5) && (SERIAL_CONSOLE != 6) +# define TTYS4_DEV g_uart5priv /* LPUART5 is ttyS1 */ +# define SERIAL_CONSOLE 6 +#elif defined(CONFIG_HPM_UART6) && (SERIAL_CONSOLE != 7) +# define TTYS4_DEV g_uart6priv /* LPUART6 is ttyS1 */ +# define SERIAL_CONSOLE 7 +#elif defined(CONFIG_HPM_UART7) && (SERIAL_CONSOLE != 8) +# define TTYS4_DEV g_uart7priv /* LPUART7 is ttyS1 */ +# define SERIAL_CONSOLE 8 +#endif + +#if defined(CONFIG_HPM_UART4) && (SERIAL_CONSOLE != 5) +# define TTYS5_DEV g_uart4priv /* LPUART4 is ttyS1 */ +# define SERIAL_CONSOLE 5 +#elif defined(CONFIG_HPM_UART5) && (SERIAL_CONSOLE != 6) +# define TTYS5_DEV g_uart5priv /* LPUART5 is ttyS1 */ +# define SERIAL_CONSOLE 6 +#elif defined(CONFIG_HPM_UART6) && (SERIAL_CONSOLE != 7) +# define TTYS5_DEV g_uart6priv /* LPUART6 is ttyS1 */ +# define SERIAL_CONSOLE 7 +#elif defined(CONFIG_HPM_UART7) && (SERIAL_CONSOLE != 8) +# define TTYS5_DEV g_uart7priv /* LPUART7 is ttyS1 */ +# define SERIAL_CONSOLE 8 +#endif + +#if defined(CONFIG_HPM_UART5) && (SERIAL_CONSOLE != 6) +# define TTYS6_DEV g_uart5priv /* LPUART5 is ttyS1 */ +# define SERIAL_CONSOLE 6 +#elif defined(CONFIG_HPM_UART6) && (SERIAL_CONSOLE != 7) +# define TTYS6_DEV g_uart6priv /* LPUART6 is ttyS1 */ +# define SERIAL_CONSOLE 7 +#elif defined(CONFIG_HPM_UART7) && (SERIAL_CONSOLE != 8) +# define TTYS6_DEV g_uart7priv /* LPUART7 is ttyS1 */ +# define SERIAL_CONSOLE 8 +#endif + +#if defined(CONFIG_HPM_UART6) && (SERIAL_CONSOLE != 7) +# define TTYS7_DEV g_uart6priv /* LPUART6 is ttyS1 */ +# define SERIAL_CONSOLE 7 +#elif defined(CONFIG_HPM_UART7) && (SERIAL_CONSOLE != 8) +# define TTYS7_DEV g_uart7priv /* LPUART7 is ttyS1 */ +# define SERIAL_CONSOLE 8 +#endif + +/* Common initialization logic will not not know that the all of the UARTs + * have been disabled. So, as a result, we may still have to provide + * stub implementations of riscv_earlyserialinit(), riscv_serialinit(), and + * up_putc(). + */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct hpm_uart_s +{ + struct uart_dev_s dev; + uint32_t uartbase; /* Base address of UART registers */ + uint32_t baud; /* Configured baud */ + uint32_t irq; /* IRQ associated with this UART */ + uint32_t im; /* Interrupt mask state */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +#if defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL) + uint8_t inviflow:1; /* Invert RTS sense */ + const uint32_t rts_gpio; /* UART RTS GPIO pin configuration */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + const uint32_t cts_gpio; /* UART CTS GPIO pin configuration */ +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + uint8_t iflow:1; /* input flow control (RTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_OFLOWCONTROL + uint8_t oflow:1; /* output flow control (CTS) enabled */ +#endif +#ifdef CONFIG_SERIAL_RS485CONTROL + uint8_t rs485mode:1; /* We are in RS485 (RTS on TX) mode */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline +uint32_t hpm_serialin(struct hpm_uart_s *priv, uint32_t offset); +static inline +void hpm_serialout(struct hpm_uart_s *priv, uint32_t offset, uint32_t value); +#if defined (CONFIG_SERIAL_TERMIOS) || defined (CONSOLE_DEV) +static inline void hpm_disableuartint(struct hpm_uart_s *priv, uint32_t *ie); +static inline void hpm_restoreuartint(struct hpm_uart_s *priv, uint32_t ie); +#endif + +/* Serial driver methods */ + +static int hpm_setup(struct uart_dev_s *dev); +static void hpm_shutdown(struct uart_dev_s *dev); +static int hpm_attach(struct uart_dev_s *dev); +static void hpm_detach(struct uart_dev_s *dev); +static int hpm_interrupt(int irq, void *context, void *arg); +static int hpm_ioctl(struct file *filep, int cmd, unsigned long arg); +static int hpm_receive(struct uart_dev_s *dev, unsigned int *status); +static void hpm_rxint(struct uart_dev_s *dev, bool enable); +static bool hpm_rxavailable(struct uart_dev_s *dev); +static void hpm_txint(struct uart_dev_s *dev, bool enable); +#ifdef CONFIG_SERIAL_IFLOWCONTROL +static bool hpm_rxflowcontrol(struct uart_dev_s *dev, + unsigned int nbuffered, bool upper); +#endif +static void hpm_send(struct uart_dev_s *dev, int ch); +static bool hpm_txready(struct uart_dev_s *dev); +static bool hpm_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = hpm_setup, + .shutdown = hpm_shutdown, + .attach = hpm_attach, + .detach = hpm_detach, + .ioctl = hpm_ioctl, + .receive = hpm_receive, + .rxint = hpm_rxint, + .rxavailable = hpm_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = hpm_rxflowcontrol, +#endif + .send = hpm_send, + .txint = hpm_txint, + .txready = hpm_txready, + .txempty = hpm_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_HPM_UART0 +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif + +#ifdef CONFIG_HPM_UART1 +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; +#endif + +#ifdef CONFIG_HPM_UART2 +static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; +#endif + +#ifdef CONFIG_HPM_UART3 +static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE]; +static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE]; +#endif + +#ifdef CONFIG_HPM_UART4 +static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE]; +static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE]; +#endif + +#ifdef CONFIG_HPM_UART5 +static char g_uart5rxbuffer[CONFIG_UART5_RXBUFSIZE]; +static char g_uart5txbuffer[CONFIG_UART5_TXBUFSIZE]; +#endif + +#ifdef CONFIG_HPM_UART6 +static char g_uart6rxbuffer[CONFIG_UART6_RXBUFSIZE]; +static char g_uart6txbuffer[CONFIG_UART6_TXBUFSIZE]; +#endif + +#ifdef CONFIG_HPM_UART7 +static char g_uart7rxbuffer[CONFIG_UART7_RXBUFSIZE]; +static char g_uart7txbuffer[CONFIG_UART7_TXBUFSIZE]; +#endif + +#ifdef CONFIG_HPM_UART0 +static struct hpm_uart_s g_uart0priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + }, + .uartbase = HPM_UART0_BASE, + .irq = HPM_IRQ_UART0, + .im = 0, + .baud = CONFIG_UART0_BAUD, + .parity = CONFIG_UART0_PARITY, + .bits = CONFIG_UART0_BITS, + .stopbits2 = CONFIG_UART0_2STOP, +}; +#endif + +#ifdef CONFIG_HPM_UART1 +static struct hpm_uart_s g_uart1priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + }, + .uartbase = HPM_UART1_BASE, + .irq = HPM_IRQ_UART1, + .im = 0, + .baud = CONFIG_UART1_BAUD, + .parity = CONFIG_UART1_PARITY, + .bits = CONFIG_UART1_BITS, + .stopbits2 = CONFIG_UART1_2STOP, +}; +#endif + +#ifdef CONFIG_HPM_UART2 +static struct hpm_uart_s g_uart2priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_UART2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + }, + .uartbase = HPM_UART2_BASE, + .irq = HPM_IRQ_UART2, + .im = 0, + .baud = CONFIG_UART2_BAUD, + .parity = CONFIG_UART2_PARITY, + .bits = CONFIG_UART2_BITS, + .stopbits2 = CONFIG_UART2_2STOP, +}; +#endif + +#ifdef CONFIG_HPM_UART3 +static struct hpm_uart_s g_uart3priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_UART3_RXBUFSIZE, + .buffer = g_uart3rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART3_TXBUFSIZE, + .buffer = g_uart3txbuffer, + }, + .ops = &g_uart_ops, + }, + .uartbase = HPM_UART3_BASE, + .irq = HPM_IRQ_UART3, + .im = 0, + .baud = CONFIG_UART3_BAUD, + .parity = CONFIG_UART3_PARITY, + .bits = CONFIG_UART3_BITS, + .stopbits2 = CONFIG_UART3_2STOP, +}; +#endif + +#ifdef CONFIG_HPM_UART4 +static struct hpm_uart_s g_uart4priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_UART4_RXBUFSIZE, + .buffer = g_uart4rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART4_TXBUFSIZE, + .buffer = g_uart4txbuffer, + }, + .ops = &g_uart_ops, + }, + .uartbase = HPM_UART4_BASE, + .irq = HPM_IRQ_UART4, + .im = 0, + .baud = CONFIG_UART4_BAUD, + .parity = CONFIG_UART4_PARITY, + .bits = CONFIG_UART4_BITS, + .stopbits2 = CONFIG_UART4_2STOP, +}; +#endif + +#ifdef CONFIG_HPM_UART5 +static struct hpm_uart_s g_uart5priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_UART5_RXBUFSIZE, + .buffer = g_uart5rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART5_TXBUFSIZE, + .buffer = g_uart5txbuffer, + }, + .ops = &g_uart_ops, + }, + .uartbase = HPM_UART5_BASE, + .irq = HPM_IRQ_UART5, + .im = 0, + .baud = CONFIG_UART5_BAUD, + .parity = CONFIG_UART5_PARITY, + .bits = CONFIG_UART5_BITS, + .stopbits2 = CONFIG_UART5_2STOP, +}; +#endif + +#ifdef CONFIG_HPM_UART6 +static struct hpm_uart_s g_uart6priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_UART6_RXBUFSIZE, + .buffer = g_uart6rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART6_TXBUFSIZE, + .buffer = g_uart6txbuffer, + }, + .ops = &g_uart_ops, + }, + .uartbase = HPM_UART6_BASE, + .irq = HPM_IRQ_UART6, + .im = 0, + .baud = CONFIG_UART6_BAUD, + .parity = CONFIG_UART6_PARITY, + .bits = CONFIG_UART6_BITS, + .stopbits2 = CONFIG_UART6_2STOP, +}; +#endif + +#ifdef CONFIG_HPM_UART7 +static struct hpm_uart_s g_uart7priv = +{ + .dev = + { + .recv = + { + .size = CONFIG_UART7_RXBUFSIZE, + .buffer = g_uart7rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART7_TXBUFSIZE, + .buffer = g_uart7txbuffer, + }, + .ops = &g_uart_ops, + }, + .uartbase = HPM_UART7_BASE, + .irq = HPM_IRQ_UART7, + .im = 0, + .baud = CONFIG_UART7_BAUD, + .parity = CONFIG_UART7_PARITY, + .bits = CONFIG_UART7_BITS, + .stopbits2 = CONFIG_UART7_2STOP, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: hpm_serialin + ****************************************************************************/ + +static inline uint32_t hpm_serialin(struct hpm_uart_s *priv, uint32_t offset) +{ + return getreg32(priv->uartbase + offset); +} + +/**************************************************************************** + * Name: hpm_serialout + ****************************************************************************/ + +static inline +void hpm_serialout(struct hpm_uart_s *priv, uint32_t offset, uint32_t value) +{ + putreg32(value, priv->uartbase + offset); +} + +/**************************************************************************** + * Name: hpm_disableuartint + ****************************************************************************/ + +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONSOLE_DEV) +static inline void hpm_disableuartint(struct hpm_uart_s *priv, uint32_t *ie) +{ + irqstate_t flags; + uint32_t regval; + + flags = enter_critical_section(); + regval = hpm_serialin(priv, HPM_UART_IER_OFFSET); + + /* Return the current Rx and Tx interrupt state */ + + if (ie != NULL) + { + *ie = regval & UART_ALL_INTS; + } + + regval &= ~UART_ALL_INTS; + + hpm_serialout(priv, HPM_UART_IER_OFFSET, regval); + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: hpm_restoreuartint + ****************************************************************************/ + +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONSOLE_DEV) +static inline void hpm_restoreuartint(struct hpm_uart_s *priv, uint32_t im) +{ + uint32_t regval; + irqstate_t flags; + + /* Enable/disable any interrupts that are currently disabled but should be + * enabled/disabled. + */ + + flags = enter_critical_section(); + regval = hpm_serialin(priv, HPM_UART_IER_OFFSET); + regval &= ~UART_ALL_INTS; + regval |= im; + hpm_serialout(priv, HPM_UART_IER_OFFSET, regval); + + leave_critical_section(flags); +} +#endif + +/**************************************************************************** + * Name: hpm_setup + * + * Description: + * Configure the UART baud, bits, parity, fifos, etc. This + * method is called the first time that the serial port is + * opened. + * + ****************************************************************************/ + +static int hpm_setup(struct uart_dev_s *dev) +{ + struct hpm_uart_s *priv = (struct hpm_uart_s *)dev; +#ifndef CONFIG_SUPPRESS_UART_CONFIG + int ret; + struct uart_config_s config = + { + 0 + }; + + /* Configure the UART */ + + config.baud = priv->baud; /* Configured baud */ + config.parity = priv->parity; /* 0=none, 1=odd, 2=even */ + config.bits = priv->bits; /* Number of bits (5-9) */ + config.stopbits2 = priv->stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +#ifdef CONFIG_SERIAL_OFLOWCONTROL + config.usects = priv->oflow; /* Flow control on outbound side */ +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + /* Flow control on inbound side if not GPIO based */ + + if ((priv->rts_gpio & GPIO_MODE_MASK) == GPIO_PERIPH) + { + config.userts = priv->iflow; + } + +#endif +#ifdef CONFIG_SERIAL_RS485CONTROL + config.users485 = priv->rs485mode; /* Switch into RS485 mode */ +#endif +#if defined(CONFIG_SERIAL_RS485CONTROL) || defined(CONFIG_SERIAL_IFLOWCONTROL) + config.invrts = priv->inviflow; /* Inversion of outbound flow control */ +#endif + + ret = hpm_uart_configure(priv->uartbase, &config); + + priv->im = hpm_serialin(priv, HPM_UART_IER_OFFSET) & UART_ALL_INTS; + return ret; + +#else + priv->im = hpm_serialin(priv, HPM_UART_IER_OFFSET) & UART_ALL_INTS; + + return OK; +#endif /* CONFIG_SUPPRESS_UART_CONFIG */ +} + +/**************************************************************************** + * Name: hpm_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void hpm_shutdown(struct uart_dev_s *dev) +{ + struct hpm_uart_s *priv = (struct hpm_uart_s *)dev; + + /* Disable interrupts */ + + hpm_disableuartint(priv, NULL); +} + +/**************************************************************************** + * Name: hpm_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() are called. + * + ****************************************************************************/ + +static int hpm_attach(struct uart_dev_s *dev) +{ + struct hpm_uart_s *priv = (struct hpm_uart_s *)dev; + int ret; + + ret = irq_attach(priv->irq, hpm_interrupt, dev); + + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ + + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: hpm_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void hpm_detach(struct uart_dev_s *dev) +{ + struct hpm_uart_s *priv = (struct hpm_uart_s *)dev; + + /* Disable interrupts */ + + up_disable_irq(priv->irq); + + /* Detach from the interrupt */ + + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: hpm_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked when an + * interrupt is received on the 'irq'. It should call uart_xmitchars or + * uart_recvchars to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'arg' into the + * appropriate uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int hpm_interrupt(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev = (struct uart_dev_s *)arg; + struct hpm_uart_s *priv = (struct hpm_uart_s *)dev; + uint32_t irq_id; + + irq_id = hpm_serialin(priv, HPM_UART_IIR_OFFSET) & UART_IIR_INTRID_MASK; + + if ((irq_id & UART_IIR_INTRID_RX_AVAILE) == UART_IIR_INTRID_RX_AVAILE) + { + uart_recvchars(dev); + } + + if ((irq_id & UART_IIR_INTRID_TX_AVAILE) == UART_IIR_INTRID_TX_AVAILE) + { + uart_xmitchars(dev); + } + + if ((irq_id & UART_IIR_INTRID_RX_TIMEOUT) == UART_IIR_INTRID_RX_TIMEOUT) + { + /* TODO: timeout logic */ + } + + if ((irq_id & UART_IIR_INTRID_RX_STATE) == UART_IIR_INTRID_RX_STATE) + { + /* TODO: line break */ + } + + if ((irq_id & UART_IIR_INTRID_MODEM_STATE) == UART_IIR_INTRID_MODEM_STATE) + { + /* TODO: modem state */ + } + + return OK; +} + +/**************************************************************************** + * Name: hpm_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int hpm_ioctl(struct file *filep, int cmd, unsigned long arg) +{ +#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT) + struct inode *inode = filep->f_inode; + struct uart_dev_s *dev = inode->i_private; + struct hpm_uart_s *priv = (struct hpm_uart_s *)dev; + irqstate_t flags; +#endif + + int ret = OK; + + switch (cmd) + { +#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT + case TIOCSERGSTRUCT: + { + struct hpm_uart_s *user = (struct hpm_uart_s *)arg; + if (!user) + { + ret = -EINVAL; + } + else + { + memcpy(user, dev, sizeof(struct hpm_uart_s)); + } + } + break; +#endif + +#ifdef CONFIG_SERIAL_TERMIOS + case TCGETS: + { + struct termios *termiosp = (struct termios *)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + termiosp->c_cflag = + ((priv->parity != 0) ? PARENB : 0) | + ((priv->parity == 1) ? PARODD : 0) | + ((priv->stopbits2) ? CSTOPB : 0) | + ((priv->bits == 5) ? CS5 : 0) | + ((priv->bits == 6) ? CS6 : 0) | + ((priv->bits == 7) ? CS7 : 0) | + ((priv->bits == 8) ? CS8 : 0); + + /* Return flow control */ + +#ifdef CONFIG_SERIAL_OFLOWCONTROL + termiosp->c_cflag |= ((priv->oflow) ? CCTS_OFLOW : 0); +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + termiosp->c_cflag |= ((priv->iflow) ? CRTS_IFLOW : 0); +#endif + + cfsetispeed(termiosp, priv->baud); + } + break; + + case TCSETS: + { + struct termios *termiosp = (struct termios *)arg; + uint32_t baud; + uint32_t im; + uint8_t parity; + uint8_t nbits; + bool stop2; + + if ((!termiosp) +#ifdef CONFIG_SERIAL_OFLOWCONTROL + || ((termiosp->c_cflag & CCTS_OFLOW) && (priv->cts_gpio == 0)) +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + || ((termiosp->c_cflag & CRTS_IFLOW) && (priv->rts_gpio == 0)) +#endif + ) + { + ret = -EINVAL; + break; + } + + baud = cfgetispeed(termiosp); + + if (termiosp->c_cflag & PARENB) + { + parity = (termiosp->c_cflag & PARODD) ? 1 : 2; + } + else + { + parity = 0; + } + + stop2 = (termiosp->c_cflag & CSTOPB) != 0; + + switch (termiosp->c_cflag & CSIZE) + { + case CS5: + nbits = 5; + break; + + case CS6: + nbits = 6; + break; + + case CS7: + nbits = 7; + break; + + case CS8: + nbits = 8; + break; + + default: + nbits = 0; + ret = -EINVAL; + break; + } + + if (ret == OK) + { + priv->baud = baud; + priv->parity = parity; + priv->bits = nbits; + priv->stopbits2 = stop2; +#ifdef CONFIG_SERIAL_OFLOWCONTROL + priv->oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0; +#endif +#ifdef CONFIG_SERIAL_IFLOWCONTROL + priv->iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0; +#endif + + /* Effect the changes immediately - note that we do not implement + * TCSADRAIN / TCSAFLUSH + */ + + flags = enter_critical_section(); + hpm_disableuartint(priv, &im); + ret = dev->ops->setup(dev); + + /* Restore the interrupt state */ + + hpm_restoreuartint(priv, im); + priv->im = im; + leave_critical_section(flags); + } + } + break; +#endif /* CONFIG_SERIAL_TERMIOS */ + +#ifdef CONFIG_IMXRT_LPUART_SINGLEWIRE + case TIOCSSINGLEWIRE: + break; +#endif +#ifdef CONFIG_IMXRT_LPUART_INVERT + case TIOCSINVERT: + break; +#endif + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: hpm_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int hpm_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct hpm_uart_s *priv = (struct hpm_uart_s *)dev; + uint32_t rxdata = 0; + + if ((hpm_serialin(priv, HPM_UART_LSR_OFFSET) & UART_LSR_DR) == UART_LSR_DR) + { + rxdata = hpm_serialin(priv, HPM_UART_RBR_OFFSET) & UART_RBR_RBR_MASK; + *status = 0; + } + else + { + *status = -1; + } + + return (int)rxdata; +} + +/**************************************************************************** + * Name: hpm_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void hpm_rxint(struct uart_dev_s *dev, bool enable) +{ + struct hpm_uart_s *priv = (struct hpm_uart_s *)dev; + irqstate_t flags = enter_critical_section(); + + if (enable) + { +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->im |= UART_IER_ERBI; +#endif + } + else + { + priv->im &= ~UART_IER_ERBI; + } + + hpm_serialout(priv, HPM_UART_IER_OFFSET, priv->im); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: hpm_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +static bool hpm_rxavailable(struct uart_dev_s *dev) +{ + struct hpm_uart_s *priv = (struct hpm_uart_s *)dev; + + return ((hpm_serialin(priv, HPM_UART_LSR_OFFSET) & UART_LSR_DR) != 0) + ? true : false; +} + +/**************************************************************************** + * Name: hpm_send + * + * Description: + * This method will send one byte on the UART. + * + ****************************************************************************/ + +static void hpm_send(struct uart_dev_s *dev, int ch) +{ + struct hpm_uart_s *priv = (struct hpm_uart_s *)dev; + + while ((hpm_serialin(priv, HPM_UART_LSR_OFFSET) + & UART_LSR_THRE) == 0) + { + } + + hpm_serialout(priv, HPM_UART_THR_OFFSET, (uint32_t)ch); +} + +/**************************************************************************** + * Name: hpm_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void hpm_txint(struct uart_dev_s *dev, bool enable) +{ + struct hpm_uart_s *priv = (struct hpm_uart_s *)dev; + irqstate_t flags; + + flags = enter_critical_section(); + if (enable) + { + /* Enable the TX interrupt */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + priv->im |= UART_IER_ETHEI; +#endif + } + else + { + /* Disable the TX interrupt */ + + priv->im &= ~UART_IER_ETHEI; + } + + hpm_serialout(priv, HPM_UART_IER_OFFSET, priv->im); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: hpm_txready + * + * Description: + * Return true if the tranmsit data register is not full + * + ****************************************************************************/ + +static bool hpm_txready(struct uart_dev_s *dev) +{ + struct hpm_uart_s *priv = (struct hpm_uart_s *)dev; + + /* Return TRUE if the TX FIFO is not full */ + + return (hpm_serialin(priv, HPM_UART_LSR_OFFSET) & UART_LSR_THRE) + ? true : false; +} + +/**************************************************************************** + * Name: hpm_txempty + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool hpm_txempty(struct uart_dev_s *dev) +{ + struct hpm_uart_s *priv = (struct hpm_uart_s *)dev; + + /* Return TRUE if the TX wartermak is pending */ + + return (hpm_serialin(priv, HPM_UART_LSR_OFFSET) & UART_LSR_TEMT) + ? true : false; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT + +/**************************************************************************** + * Name: riscv_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before riscv_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in up_consoleinit() and main clock iniialization + * performed in up_clkinitialize(). + * + ****************************************************************************/ + +void riscv_earlyserialinit(void) +{ + /* Configuration whichever one is the console */ + +#ifdef CONSOLE_DEV + CONSOLE_DEV.dev.isconsole = true; + hpm_setup(&CONSOLE_DEV.dev); +#endif +} +#endif + +/**************************************************************************** + * Name: riscv_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that riscv_earlyserialinit was called previously. + * + ****************************************************************************/ + +void riscv_serialinit(void) +{ + /* Register the console */ + +#ifdef CONSOLE_DEV + uart_register("/dev/console", &CONSOLE_DEV.dev); +#endif + + /* Register all UARTs NOTE: we don't reorganize the numbering */ + +#ifdef TTYS0_DEV + uart_register("/dev/ttyS0", &TTYS0_DEV.dev); +#endif +#ifdef TTYS1_DEV + uart_register("/dev/ttyS1", &TTYS1_DEV.dev); +#endif +#ifdef TTYS2_DEV + uart_register("/dev/ttyS2", &TTYS2_DEV.dev); +#endif +#ifdef TTYS3_DEV + uart_register("/dev/ttyS3", &TTYS3_DEV.dev); +#endif +#ifdef TTYS4_DEV + uart_register("/dev/ttyS4", &TTYS4_DEV.dev); +#endif +#ifdef TTYS5_DEV + uart_register("/dev/ttyS5", &TTYS5_DEV.dev); +#endif +#ifdef TTYS6_DEV + uart_register("/dev/ttyS6", &TTYS6_DEV.dev); +#endif +#ifdef TTYS7_DEV + uart_register("/dev/ttyS7", &TTYS7_DEV.dev); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef CONSOLE_DEV + struct hpm_uart_s *priv = (struct hpm_uart_s *)CONSOLE_DEV.dev.priv; + uint32_t im; + + hpm_disableuartint(priv, &im); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + hpm_lowputc('\r'); + } + + hpm_lowputc(ch); + hpm_restoreuartint(priv, im); +#endif + return ch; +} + +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_UART_CONSOLE + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + riscv_lowputc('\r'); + } + + riscv_lowputc(ch); +#endif + return ch; +} + +#endif /* USE_SERIALDRIVER */ diff --git a/arch/risc-v/src/hpm6000/hpm_serial.h b/arch/risc-v/src/hpm6000/hpm_serial.h new file mode 100644 index 0000000000000..e3c8406d27a3d --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_serial.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_serial.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_HPM6000_HPM_SERIAL_H +#define __ARCH_RISCV_SRC_HPM6000_HPM_SERIAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_HPM6000_HPM_SERIAL_H */ diff --git a/arch/risc-v/src/hpm6000/hpm_start.c b/arch/risc-v/src/hpm6000/hpm_start.c new file mode 100644 index 0000000000000..051249c0669cc --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_start.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_start.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "chip.h" +#include "hpm.h" +#include "hpm_clockconfig.h" +#include "hpm_lowputc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __hpm6750_start + ****************************************************************************/ + +void __hpm_start(void) +{ + const uint32_t *src; + uint32_t *dest; + + /* Clear .bss. We'll do this inline (vs. calling memset) just to be + * certain that there are no issues with the state of global variables. + */ + + for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; ) + { + *dest++ = 0; + } + + /* Move the initialized data section from his temporary holding spot in + * FLASH into the correct place in SRAM. The correct place in SRAM is + * give by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. + */ + + for (src = (const uint32_t *)_eronly, + dest = (uint32_t *)_sdata; dest < (uint32_t *)_edata; + ) + { + *dest++ = *src++; + } + + /* Setup PLL */ + + hpm_clockconfig(); + + /* Configure the UART so we can get debug output */ + + hpm_lowsetup(); + +#ifdef USE_EARLYSERIALINIT + riscv_earlyserialinit(); +#endif + + /* Do board initialization */ + + hpm6360_boardinitialize(); + + /* Call nx_start() */ + + nx_start(); + + /* Shouldn't get here */ + + for (; ; ); +} diff --git a/arch/risc-v/src/hpm6000/hpm_timerisr.c b/arch/risc-v/src/hpm6000/hpm_timerisr.c new file mode 100644 index 0000000000000..65d74a32a915d --- /dev/null +++ b/arch/risc-v/src/hpm6000/hpm_timerisr.c @@ -0,0 +1,70 @@ +/**************************************************************************** + * arch/risc-v/src/hpm6000/hpm_timerisr.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "riscv_internal.h" +#include "riscv_mtimer.h" +#include "chip.h" +#include "hpm.h" +#include "hpm_clockconfig.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + struct oneshot_lowerhalf_s *lower = riscv_mtimer_initialize( + HPM_MCHTMR_MTIME, HPM_MCHTMR_MTIMECMP, + RISCV_IRQ_MTIMER, hpm_get_osc_freq()); + + DEBUGASSERT(lower); + + up_alarm_set_lowerhalf(lower); +} diff --git a/arch/risc-v/src/hpm6750/hpm6750_head.S b/arch/risc-v/src/hpm6750/hpm6750_head.S index d8c3750b0f37b..f696c2360af0a 100644 --- a/arch/risc-v/src/hpm6750/hpm6750_head.S +++ b/arch/risc-v/src/hpm6750/hpm6750_head.S @@ -43,7 +43,7 @@ __start: /* reset mstatus to 0*/ - csrrw x0, mstatus, x0 + csrrw x0, CSR_MSTATUS, x0 /* Set stack pointer to the idle thread stack */ @@ -51,13 +51,13 @@ __start: /* Disable all interrupts (i.e. timer, external) in mie */ - csrw mie, zero - csrw mip, zero + csrw CSR_MIE, zero + csrw CSR_MIP, zero /* Initialize the Machine Trap Vector */ la t0, __trap_vec - csrw mtvec, t0 + csrw CSR_MTVEC, t0 /* Jump to __hpm6750_start */ diff --git a/arch/risc-v/src/hpm6750/hpm6750_irq.c b/arch/risc-v/src/hpm6750/hpm6750_irq.c index 27034bfe14ba8..25d614d406769 100644 --- a/arch/risc-v/src/hpm6750/hpm6750_irq.c +++ b/arch/risc-v/src/hpm6750/hpm6750_irq.c @@ -108,13 +108,13 @@ void up_disable_irq(int irq) { /* Read mstatus & clear machine software interrupt enable in mie */ - CLEAR_CSR(mie, MIE_MSIE); + CLEAR_CSR(CSR_MIE, MIE_MSIE); } else if (irq == RISCV_IRQ_MTIMER) { /* Read mstatus & clear machine timer interrupt enable in mie */ - CLEAR_CSR(mie, MIE_MTIE); + CLEAR_CSR(CSR_MIE, MIE_MTIE); } else if (irq >= HPM6750_IRQ_PERI_START) { @@ -150,13 +150,13 @@ void up_enable_irq(int irq) { /* Read mstatus & set machine software interrupt enable in mie */ - SET_CSR(mie, MIE_MSIE); + SET_CSR(CSR_MIE, MIE_MSIE); } else if (irq == RISCV_IRQ_MTIMER) { /* Read mstatus & set machine timer interrupt enable in mie */ - SET_CSR(mie, MIE_MTIE); + SET_CSR(CSR_MIE, MIE_MTIE); } else if (irq >= HPM6750_IRQ_PERI_START) { @@ -204,10 +204,10 @@ irqstate_t up_irq_enable(void) /* TODO: should move to up_enable_irq() */ - SET_CSR(mie, MIE_MEIE); + SET_CSR(CSR_MIE, MIE_MEIE); /* Read mstatus & set machine interrupt enable (MIE) in mstatus */ - oldstat = READ_AND_SET_CSR(mstatus, MSTATUS_MIE); + oldstat = READ_AND_SET_CSR(CSR_MSTATUS, MSTATUS_MIE); return oldstat; } diff --git a/arch/risc-v/src/hpm6750/hpm6750_memorymap.h b/arch/risc-v/src/hpm6750/hpm6750_memorymap.h index 56ecf64388073..b9c960589c084 100644 --- a/arch/risc-v/src/hpm6750/hpm6750_memorymap.h +++ b/arch/risc-v/src/hpm6750/hpm6750_memorymap.h @@ -45,6 +45,6 @@ #define HPM6750_IDLESTACK_BASE _ebss #endif -#define HPM6750_IDLESTACK_TOP (HPM6750_IDLESTACK_BASE + CONFIG_IDLETHREAD_STACKSIZE) +#define HPM6750_IDLESTACK_TOP (HPM6750_IDLESTACK_BASE + SMP_STACK_SIZE) #endif /* __ARCH_RISCV_SRC_HPM6750_HPM6750_MEMORYMAP_H */ diff --git a/arch/risc-v/src/hpm6750/hpm6750_serial.c b/arch/risc-v/src/hpm6750/hpm6750_serial.c index 5ea38e7754dd3..c18dafd44ce33 100644 --- a/arch/risc-v/src/hpm6750/hpm6750_serial.c +++ b/arch/risc-v/src/hpm6750/hpm6750_serial.c @@ -233,12 +233,12 @@ static void up_serialmodfiy(struct up_dev_s *priv, int offset, static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) { - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(NULL); priv->im = im; up_serialout(priv, UART_IER_OFFSET, im); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -247,7 +247,7 @@ static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) { - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(NULL); /* Return the current interrupt mask value */ @@ -260,7 +260,7 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) priv->im = 0; up_serialout(priv, UART_IER_OFFSET, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/risc-v/src/hpm6750/hpm6750_start.c b/arch/risc-v/src/hpm6750/hpm6750_start.c index 1a7f530a4f206..7afdaed2fe440 100644 --- a/arch/risc-v/src/hpm6750/hpm6750_start.c +++ b/arch/risc-v/src/hpm6750/hpm6750_start.c @@ -42,18 +42,6 @@ * Public Data ****************************************************************************/ -/* g_idle_topstack: _sbss is the start of the BSS region as defined by the - * linker script. _ebss lies at the end of the BSS region. The idle task - * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. - * The IDLE thread is the thread that the system boots on and, eventually, - * becomes the IDLE, do nothing task that runs only when there is nothing - * else to run. The heap continues from there until the end of memory. - * g_idle_topstack is a read-only variable the provides this computed - * address. - */ - -uintptr_t g_idle_topstack = HPM6750_IDLESTACK_TOP; - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/risc-v/src/jh7110/jh7110_head.S b/arch/risc-v/src/jh7110/jh7110_head.S index ace118541e12f..151195c2001a9 100644 --- a/arch/risc-v/src/jh7110/jh7110_head.S +++ b/arch/risc-v/src/jh7110/jh7110_head.S @@ -29,6 +29,7 @@ #include "chip.h" #include "riscv_internal.h" +#include "riscv_macros.S" /**************************************************************************** * Public Symbols @@ -74,13 +75,6 @@ real_start: addi a0, a0, -1 - /* Set stack pointer to the idle thread stack */ - - bnez a0, 1f - la sp, JH7110_IDLESTACK_TOP - j 2f -1: - /* Load the number of CPUs that the kernel supports */ #ifdef CONFIG_SMP @@ -92,45 +86,19 @@ real_start: /* If a0 (hartid) >= t1 (the number of CPUs), stop here */ blt a0, t1, 3f - csrw sie, zero + csrw CSR_SIE, zero wfi 3: - /* To get g_cpu_basestack[hartid], must get g_cpu_basestack first */ - - la t0, g_cpu_basestack - - /* Offset = pointer width * hart id */ - -#ifdef CONFIG_ARCH_RV32 - slli t1, a0, 2 -#else - slli t1, a0, 3 -#endif - add t0, t0, t1 - - /* Load idle stack base to sp */ - - REGLOAD sp, 0(t0) - - /* - * sp (stack top) = sp + idle stack size - XCPTCONTEXT_SIZE - * - * Note: Reserve some space used by up_initial_state since we are already - * running and using the per CPU idle stack. - */ - - li t0, STACK_ALIGN_UP(CONFIG_IDLETHREAD_STACKSIZE - XCPTCONTEXT_SIZE) - add sp, sp, t0 - -2: + /* Set stack pointer to the idle thread stack */ + riscv_set_inital_sp JH7110_IDLESTACK_BASE, SMP_STACK_SIZE, a0 /* Disable all interrupts (i.e. timer, external) in sie */ - csrw sie, zero + csrw CSR_SIE, zero la t0, __trap_vec - csrw stvec, t0 + csrw CSR_STVEC, t0 /* Jump to jh7110_start */ diff --git a/arch/risc-v/src/jh7110/jh7110_irq.c b/arch/risc-v/src/jh7110/jh7110_irq.c index 6bb4fe3f8a78d..ec30dbf417883 100644 --- a/arch/risc-v/src/jh7110/jh7110_irq.c +++ b/arch/risc-v/src/jh7110/jh7110_irq.c @@ -33,6 +33,7 @@ #include #include "riscv_internal.h" +#include "riscv_ipi.h" #include "chip.h" /**************************************************************************** @@ -79,9 +80,9 @@ void up_irqinitialize(void) riscv_exception_attach(); #ifdef CONFIG_SMP - /* Clear RISCV_IPI for CPU0 */ + /* Clear IPI for CPU0 */ - putreg32(0, RISCV_IPI); + riscv_ipi_clear(0); up_enable_irq(RISCV_IRQ_SOFT); #endif diff --git a/arch/risc-v/src/jh7110/jh7110_memorymap.h b/arch/risc-v/src/jh7110/jh7110_memorymap.h index d922e3c4a8da3..02724605e5f5b 100644 --- a/arch/risc-v/src/jh7110/jh7110_memorymap.h +++ b/arch/risc-v/src/jh7110/jh7110_memorymap.h @@ -39,7 +39,4 @@ #define JH7110_IDLESTACK_BASE _ebss #endif -#define JH7110_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3) -#define JH7110_IDLESTACK_TOP (JH7110_IDLESTACK_BASE + JH7110_IDLESTACK_SIZE) - #endif /* __ARCH_RISCV_SRC_JH7110_JH7110_MEMORYMAP_H */ diff --git a/arch/risc-v/src/jh7110/jh7110_start.c b/arch/risc-v/src/jh7110/jh7110_start.c index d27fbf2676652..a55844ffa1043 100644 --- a/arch/risc-v/src/jh7110/jh7110_start.c +++ b/arch/risc-v/src/jh7110/jh7110_start.c @@ -52,12 +52,6 @@ extern void __trap_vec(void); * Public Data ****************************************************************************/ -/* NOTE: g_idle_topstack needs to point the top of the idle stack - * for CPU0 and this value is used in up_initial_state() - */ - -uintptr_t g_idle_topstack = JH7110_IDLESTACK_TOP; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -146,11 +140,11 @@ void jh7110_start(int mhartid) /* Disable MMU */ - WRITE_CSR(satp, 0x0); + WRITE_CSR(CSR_SATP, 0x0); /* Set the trap vector for S-mode */ - WRITE_CSR(stvec, (uintptr_t)__trap_vec); + WRITE_CSR(CSR_STVEC, (uintptr_t)__trap_vec); /* Start S-mode */ diff --git a/arch/risc-v/src/jh7110/jh7110_timerisr.c b/arch/risc-v/src/jh7110/jh7110_timerisr.c index 751cb0910c546..920361fff6161 100644 --- a/arch/risc-v/src/jh7110/jh7110_timerisr.c +++ b/arch/risc-v/src/jh7110/jh7110_timerisr.c @@ -64,7 +64,7 @@ static int jh7110_ssoft_interrupt(int irq, void *context, void *arg) { /* Cleaer Supervisor Software Interrupt */ - CLEAR_CSR(sip, SIP_SSIP); + CLEAR_CSR(CSR_SIP, SIP_SSIP); if (g_stimer_pending) { diff --git a/arch/risc-v/src/k210/chip.h b/arch/risc-v/src/k210/chip.h index 9592bb54ce619..50548c09f995a 100644 --- a/arch/risc-v/src/k210/chip.h +++ b/arch/risc-v/src/k210/chip.h @@ -48,7 +48,7 @@ #if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 .macro setintstack tmp0, tmp1 - csrr \tmp0, mhartid + csrr \tmp0, CSR_MHARTID li \tmp1, STACK_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK) mul \tmp1, \tmp0, \tmp1 la \tmp0, g_intstacktop diff --git a/arch/risc-v/src/k210/k210_head.S b/arch/risc-v/src/k210/k210_head.S index 77f618d4f35db..53101c079b7d4 100644 --- a/arch/risc-v/src/k210/k210_head.S +++ b/arch/risc-v/src/k210/k210_head.S @@ -28,6 +28,7 @@ #include "chip.h" #include "k210_memorymap.h" #include "riscv_internal.h" +#include "riscv_macros.S" /**************************************************************************** * Public Symbols @@ -44,55 +45,28 @@ __start: /* Load mhartid (cpuid) */ - csrr a0, mhartid - - /* Set stack pointer to the idle thread stack */ - - bnez a0, 1f - la sp, K210_IDLESTACK0_TOP - j 2f -1: + csrr a0, CSR_MHARTID /* In case of single CPU config, stop here */ #if !defined(CONFIG_SMP) || (CONFIG_SMP_NCPUS == 1) - csrw mie, zero + beqz a0, 2f + csrw CSR_MIE, zero wfi #endif - /* To get g_cpu_basestack[mhartid], must get g_cpu_basestack first */ - - la t0, g_cpu_basestack - - /* Offset = pointer width * hart id */ - - slli t1, a0, 3 - add t0, t0, t1 - - /* Load idle stack base to sp */ - - ld sp, 0(t0) - - /* - * sp (stack top) = sp + idle stack size - XCPTCONTEXT_SIZE - * - * Note: Reserve some space used by up_initial_state since we are already - * running and using the per CPU idle stack. - */ - - li t0, STACK_ALIGN_UP(CONFIG_IDLETHREAD_STACKSIZE - XCPTCONTEXT_SIZE) - add sp, sp, t0 - 2: + /* Set stack pointer to the idle thread stack */ + riscv_set_inital_sp K210_IDLESTACK_BASE, SMP_STACK_SIZE, a0 /* Disable all interrupts (i.e. timer, external) in mie */ - csrw mie, zero + csrw CSR_MIE, zero /* Initialize the Machine Trap Vector */ la t0, __trap_vec - csrw mtvec, t0 + csrw CSR_MTVEC, t0 /* Jump to __k210_start with mhartid */ diff --git a/arch/risc-v/src/k210/k210_irq.c b/arch/risc-v/src/k210/k210_irq.c index c29c1dfc8fb02..2a4e8f3f1c514 100644 --- a/arch/risc-v/src/k210/k210_irq.c +++ b/arch/risc-v/src/k210/k210_irq.c @@ -33,6 +33,7 @@ #include #include "riscv_internal.h" +#include "riscv_ipi.h" #include "k210.h" /**************************************************************************** @@ -85,9 +86,9 @@ void up_irqinitialize(void) riscv_exception_attach(); #ifdef CONFIG_SMP - /* Clear RISCV_IPI for CPU0 */ + /* Clear IPI for CPU0 */ - putreg32(0, RISCV_IPI); + riscv_ipi_clear(0); up_enable_irq(RISCV_IRQ_SOFT); #endif @@ -116,13 +117,13 @@ void up_disable_irq(int irq) { /* Read mstatus & clear machine software interrupt enable in mie */ - CLEAR_CSR(mie, MIE_MSIE); + CLEAR_CSR(CSR_MIE, MIE_MSIE); } else if (irq == RISCV_IRQ_MTIMER) { /* Read mstatus & clear machine timer interrupt enable in mie */ - CLEAR_CSR(mie, MIE_MTIE); + CLEAR_CSR(CSR_MIE, MIE_MTIE); } else if (irq > RISCV_IRQ_MEXT) { @@ -158,13 +159,13 @@ void up_enable_irq(int irq) { /* Read mstatus & set machine software interrupt enable in mie */ - SET_CSR(mie, MIE_MSIE); + SET_CSR(CSR_MIE, MIE_MSIE); } else if (irq == RISCV_IRQ_MTIMER) { /* Read mstatus & set machine timer interrupt enable in mie */ - SET_CSR(mie, MIE_MTIE); + SET_CSR(CSR_MIE, MIE_MTIE); } else if (irq > RISCV_IRQ_MEXT) { @@ -213,11 +214,11 @@ irqstate_t up_irq_enable(void) /* TODO: should move to up_enable_irq() */ - SET_CSR(mie, MIE_MEIE); + SET_CSR(CSR_MIE, MIE_MEIE); #endif /* Read mstatus & set machine interrupt enable (MIE) in mstatus */ - oldstat = READ_AND_SET_CSR(mstatus, MSTATUS_MIE); + oldstat = READ_AND_SET_CSR(CSR_MSTATUS, MSTATUS_MIE); return oldstat; } diff --git a/arch/risc-v/src/k210/k210_memorymap.h b/arch/risc-v/src/k210/k210_memorymap.h index 9027742f48224..68f73bf8c2042 100644 --- a/arch/risc-v/src/k210/k210_memorymap.h +++ b/arch/risc-v/src/k210/k210_memorymap.h @@ -45,6 +45,5 @@ #endif #define K210_IDLESTACK0_BASE (K210_IDLESTACK_BASE) -#define K210_IDLESTACK0_TOP (K210_IDLESTACK0_BASE + CONFIG_IDLETHREAD_STACKSIZE) #endif /* __ARCH_RISCV_SRC_K210_K210_MEMORYMAP_H */ diff --git a/arch/risc-v/src/k210/k210_serial.c b/arch/risc-v/src/k210/k210_serial.c index 16cd880d9af27..4179c7fe7aad5 100644 --- a/arch/risc-v/src/k210/k210_serial.c +++ b/arch/risc-v/src/k210/k210_serial.c @@ -214,12 +214,12 @@ static void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) { - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(NULL); priv->im = im; up_serialout(priv, UART_IE_OFFSET, im); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -228,7 +228,7 @@ static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) { - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(NULL); /* Return the current interrupt mask value */ @@ -241,7 +241,7 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) priv->im = 0; up_serialout(priv, UART_IE_OFFSET, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/risc-v/src/k210/k210_start.c b/arch/risc-v/src/k210/k210_start.c index c52eb6b4aa8c5..65855c55a5604 100644 --- a/arch/risc-v/src/k210/k210_start.c +++ b/arch/risc-v/src/k210/k210_start.c @@ -48,12 +48,6 @@ * Public Data ****************************************************************************/ -/* NOTE: g_idle_topstack needs to point the top of the idle stack - * for CPU0 and this value is used in up_initial_state() - */ - -uintptr_t g_idle_topstack = K210_IDLESTACK0_TOP; - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/risc-v/src/k230/CMakeLists.txt b/arch/risc-v/src/k230/CMakeLists.txt new file mode 100644 index 0000000000000..b66ff3650f4df --- /dev/null +++ b/arch/risc-v/src/k230/CMakeLists.txt @@ -0,0 +1,43 @@ +# ############################################################################## +# arch/risc-v/src/k230/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS k230_head.S k230_start.c k230_irq.c k230_irq_dispatch.c) + +list(APPEND SRCS k230_timerisr.c k230_allocateheap.c k230_hart.c) + +if(CONFIG_BUILD_KERNEL) + list(APPEND SRCS k230_mm_init.c) +elseif(CONFIG_BUILD_PROTECTED) + list(APPEND SRCS k230_userspace.c) +endif() + +if(CONFIG_MM_PGALLOC) + list(APPEND SRCS k230_pgalloc.c) +endif() + +if(CONFIG_K230_IPI) + list(APPEND SRCS k230_ipi.c) +endif() + +if(CONFIG_RPTUN) + list(APPEND SRCS k230_rptun.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/risc-v/src/k230/Kconfig b/arch/risc-v/src/k230/Kconfig index e69de29bb2d1d..39f8011ff5559 100644 --- a/arch/risc-v/src/k230/Kconfig +++ b/arch/risc-v/src/k230/Kconfig @@ -0,0 +1,46 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if RPTUN + +config K230_RPTUN_MASTER + bool "RPTUN master node" + default y if RPTUN_LOADER + default n + +config K230_RPTUN_SHM_ADDR + hex "RPTUN share memory address" + default 0x80200000 + ---help--- + RPTUN shared memory start address. + +config K230_RPTUN_SHM_SIZE + int "RPTUN share memory size" + default 32768 + ---help--- + RPTUN shared memory size in bytes. + +config K230_RPTUN_IPI_DEV + int "IPI device num for RPTUN purpose" + default 0 + ---help--- + Choose the IPI device for RPTUN purpose, should be within 0..3 + +endif # RPTUN + +config K230_IPI + bool "Enable K230 IPI driver" + default y if RPTUN + default n + +if K230_IPI + +config K230_IPI_RESET_UPON_INIT + bool "Reset K230 mailbox device upon initialization" + default n + ---help--- + Reset whole K230 mailbox device upon k230_ipi_init. + +endif # K230_IPI diff --git a/arch/risc-v/src/k230/Make.defs b/arch/risc-v/src/k230/Make.defs index d481c48d3ccbd..5783d63cc662a 100644 --- a/arch/risc-v/src/k230/Make.defs +++ b/arch/risc-v/src/k230/Make.defs @@ -20,19 +20,24 @@ include common/Make.defs -# Specify our HEAD assembly file. This will be linked as -# the first object file, so it will appear at address 0 -HEAD_ASRC = k230_head.S +CHIP_ASRCS += k230_head.S # Specify our C code within this directory to be included CHIP_CSRCS = k230_start.c k230_irq_dispatch.c k230_irq.c -CHIP_CSRCS += k230_timerisr.c k230_allocateheap.c +CHIP_CSRCS += k230_timerisr.c k230_allocateheap.c k230_hart.c ifeq ($(CONFIG_BUILD_KERNEL),y) CHIP_CSRCS += k230_mm_init.c -CMN_ASRCS += k230_exception_m.S endif ifeq ($(CONFIG_MM_PGALLOC),y) CHIP_CSRCS += k230_pgalloc.c endif + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +CHIP_CSRCS += k230_userspace.c +endif + +ifeq ($(CONFIG_RPTUN),y) +CHIP_CSRCS += k230_rptun.c k230_ipi.c +endif diff --git a/arch/risc-v/src/k230/chip.h b/arch/risc-v/src/k230/chip.h index cd863e38bf4e2..2bd8768798752 100644 --- a/arch/risc-v/src/k230/chip.h +++ b/arch/risc-v/src/k230/chip.h @@ -30,9 +30,11 @@ #include #include "k230_memorymap.h" +#include "k230_hart.h" #include "hardware/k230_memorymap.h" #include "hardware/k230_plic.h" +#include "hardware/k230_clint.h" #include "riscv_internal.h" #include "riscv_percpu.h" @@ -71,5 +73,11 @@ #endif /* !defined(CONFIG_SMP) && defined(CONFIG_ARCH_USE_S_MODE) */ #endif /* CONFIG_ARCH_INTERRUPTSTACK > 15 */ -#endif /* __ASSEMBLY__ */ +#else /* ! __ASSEMBLY__ */ + +/* always show on uart0 */ + +#define k230_putc(c) (*(volatile uint32_t*)0x91400000 = c) + +#endif /* __ASSEMBLY__ */ #endif /* __ARCH_RISCV_SRC_K230_CHIP_H */ diff --git a/arch/risc-v/src/k230/hardware/k230_clint.h b/arch/risc-v/src/k230/hardware/k230_clint.h index 7bf4435007290..179e8934200ee 100644 --- a/arch/risc-v/src/k230/hardware/k230_clint.h +++ b/arch/risc-v/src/k230/hardware/k230_clint.h @@ -27,14 +27,23 @@ #define K230_CLINT_MSIP (K230_CLINT_BASE + 0x0000) #define K230_CLINT_MTIMECMP (K230_CLINT_BASE + 0x4000) +#define K230_CLINT_SSIP (K230_CLINT_BASE + 0xC000) +#define K230_CLINT_STIMECMP (K230_CLINT_BASE + 0xD000) #define K230_CLINT_MTIME (K230_CLINT_BASE + 0xBFF8) +#define K230_CLINT_STIME (K230_CLINT_BASE + 0xBFF8) -#define RISCV_CLINT_MSIP K230_CLINT_MSIP +#define K230_CLINT_FREQ (27000000) #ifdef CONFIG_ARCH_USE_S_MODE -# define RISCV_IPI +# define K230_IPI K230_CLINT_SSIP +# define K230_TIME K230_CLINT_STIME +# define K230_TIMECMP K230_CLINT_STIMECMP #else -# define RISCV_IPI RISCV_CLINT_MSIP +# define K230_IPI K230_CLINT_MSIP +# define K230_TIME K230_CLINT_MTIME +# define K230_TIMECMP K230_CLINT_MTIMECMP #endif +#define RISCV_IPI K230_IPI + #endif /* __ARCH_RISCV_SRC_K230_HARDWARE_K230_CLINT_H */ diff --git a/arch/risc-v/src/k230/hardware/k230_memorymap.h b/arch/risc-v/src/k230/hardware/k230_memorymap.h index d928f15aa0c11..5cd6c7aee66cb 100644 --- a/arch/risc-v/src/k230/hardware/k230_memorymap.h +++ b/arch/risc-v/src/k230/hardware/k230_memorymap.h @@ -25,9 +25,26 @@ * Pre-processor Definitions ****************************************************************************/ -/* Register Base Address ****************************************************/ +/* Devices Base Address */ -#define K230_PLIC_BASE 0xF00000000 +#define K230_PLIC_BASE 0xF00000000UL #define K230_CLINT_BASE (K230_PLIC_BASE + 0x04000000) +#define K230_CPU1_BOOTA 0x91102104UL +#define K230_CPU1_RESET 0x9110100cUL +/* T-Head c908 specific CSR */ + +#define CSR_MENVCFG 0x30a +#define CSR_MXSTATUS 0x7c0 +#define CSR_MHCR 0x7c1 +#define CSR_MCOR 0x7c2 +#define CSR_MCCR2 0x7c3 +#define CSR_MHINT 0x7c5 +#define CSR_MSMPR 0x7f3 +#define CSR_PLIC_BASE 0xfc1 +#define CSR_MAGIC 0x7d9 + +/* Enable RV PBMT */ + +#define MENVCFG_PBMT (1ul << 62) #endif /* __ARCH_RISCV_SRC_K230_HARDWARE_K230_MEMORYMAP_H */ diff --git a/arch/risc-v/src/k230/hardware/k230_plic.h b/arch/risc-v/src/k230/hardware/k230_plic.h index 910facbc66e29..2acb8f47c0cd6 100644 --- a/arch/risc-v/src/k230/hardware/k230_plic.h +++ b/arch/risc-v/src/k230/hardware/k230_plic.h @@ -46,4 +46,8 @@ # define K230_PLIC_CLAIM (K230_PLIC_BASE + 0x200004) #endif +/* use in M-mode to enable PLIC delegation to S-mode */ + +#define K230_PLIC_CTRL (K230_PLIC_BASE + 0x01ffffc) + #endif /* __ARCH_RISCV_SRC_K230_HARDWARE_K230_PLIC_H */ diff --git a/arch/risc-v/src/k230/k230_exception_m.S b/arch/risc-v/src/k230/k230_exception_m.S deleted file mode 100644 index a4ca925afc8e6..0000000000000 --- a/arch/risc-v/src/k230/k230_exception_m.S +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/qemu-rv/k230_exception_m.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" - -#include "riscv_macros.S" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Provide a default section for the exeception handler. */ - -#ifndef EXCEPTION_SECTION -# define EXCEPTION_SECTION .text -#endif - -/**************************************************************************** - * Public Symbols - ****************************************************************************/ - -.section .text -.balign 8 -.global __trap_vec_m - -/**************************************************************************** - * Name: __trap_vec_m - * - * Description: - * All M-mode exceptions and interrupts will be handled from here. If - * kernel is in S-mode delegated exceptions and interrupts are handled. - * - ****************************************************************************/ - -__trap_vec_m: - j exception_m - -/**************************************************************************** - * Name: exception_m - * - * Description: - * Handles interrupts for m-mode - * - ****************************************************************************/ - -.section EXCEPTION_SECTION -.global exception_m -.align 8 - -exception_m: - - /* Swap mscratch with sp */ - /* NOTE: mscratch has been set in up_mtimer_initialize() */ - - csrrw sp, mscratch, sp - - /* Save the context */ - - save_ctx sp - - /* Handle the mtimer interrupt */ - /* NOTE: we assume exception/interrupt only happens for mtimer */ - - jal ra, k230_mtimer_interrupt - - /* Restore the context */ - - load_ctx sp - - /* Swap mscratch with sp */ - - csrrw sp, mscratch, sp - - /* Return from exception */ - - mret diff --git a/arch/risc-v/src/k230/k230_hart.c b/arch/risc-v/src/k230/k230_hart.c new file mode 100644 index 0000000000000..a6aa9dd4b6dad --- /dev/null +++ b/arch/risc-v/src/k230/k230_hart.c @@ -0,0 +1,221 @@ +/**************************************************************************** + * arch/risc-v/src/k230/k230_hart.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "riscv_internal.h" +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_K230_PBMT_THEAD +#define THEAD_PBMT 0x638000 +#define XSTATUS THEAD_PBMT +#else +#define RISCV_PBMT 0x438000 +#define XSTATUS RISCV_PBMT +#endif +#define XSTATE_MSK ((1 << 30) - 1) + +#define MCOR 0x70013 +#define MHCR 0x11ff +#define MHINT 0x6e30c +#define MCCR2 0xe0000009 +#define MHINT_BIG 0x16e30c +#define MCCR2_BIG 0xe0410009 +#define MSMPR 1 + +#define MHCR_IE_MSK (1 << 0) +#define MHCR_DE_MSK (1 << 1) + +#define RISCV_PMBT_EN (1 << 62) + +/* K230 cache flush instructions */ + +#define K230_DAT_SYNC_B ".long 0x0ff0000f\n" +#define K230_INS_SYNC_B ".long 0x0000100f\n .long 0x0220000f\n" +#define K230_I_IALL ".long 0x0100000b\n" +#define K230_D_CIALL ".long 0x0030000b\n" +#define K230_L2_IALL ".long 0x0170000b\n" +#define K230_SYNC_IS ".long 0x01b0000b\n" + +#define ASM __asm__ __volatile__ + +/* Hart reset control bits and delays */ + +#define RESET_DONE_BIT (1 << 12) +#define RESET_RQST_BIT (1 << 0) +#define RESET_DONE_ENW (1 << (12 + 16)) +#define RESET_RQST_ENW (1 << (0 + 16)) + +#define RESET_WAIT_USEC 100 + +/**************************************************************************** + * Private Variables + ****************************************************************************/ + +#if !defined(CONFIG_BUILD_KERNEL) || defined(CONFIG_NUTTSBI) + +static volatile uint64_t g_misa locate_data(".data"); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: hart_cleanup + * Description: from cleanup_before_linux() in K230 U-Boot + ****************************************************************************/ + +static void k230_hart_cleanup(void) +{ + uintptr_t reg = READ_CSR(CSR_MHCR); + + ASM(K230_DAT_SYNC_B); + ASM(K230_INS_SYNC_B); + ASM(K230_I_IALL); /* icache.iall */ + ASM(K230_D_CIALL); /* dcache.ciall */ + ASM(K230_DAT_SYNC_B); + ASM(K230_INS_SYNC_B); + reg &= ~MHCR_IE_MSK; /* icache.disable */ + reg &= ~MHCR_DE_MSK; /* dcache.disable */ + WRITE_CSR(CSR_MHCR, reg); + ASM(K230_L2_IALL); /* l2.iall */ + ASM(K230_DAT_SYNC_B); + ASM(K230_INS_SYNC_B); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: k230_hart_init() + * Description: K230 M-mode HART setup following K230 SDK + ****************************************************************************/ + +void k230_hart_init(void) +{ + bool big; + + while (!(g_misa = READ_CSR(CSR_MISA))); + big = g_misa & (1 << 21); + + k230_hart_cleanup(); + + WRITE_CSR(CSR_MXSTATUS, XSTATUS); + WRITE_CSR(CSR_MHCR, MHCR); + WRITE_CSR(CSR_MCOR, MCOR); + WRITE_CSR(CSR_MSMPR, MSMPR); + WRITE_CSR(CSR_MCCR2, big ? MCCR2_BIG : MCCR2); + WRITE_CSR(CSR_MHINT, big ? MHINT_BIG : MHINT); + +#ifdef RISCV_PBMT + SET_CSR(CSR_MENVCFG, MENVCFG_PBMT); +#endif +} + +/**************************************************************************** + * Name: k230_hart_is_big() + * Description: returns true if running on big core. + ****************************************************************************/ + +bool k230_hart_is_big(void) +{ + return g_misa & (1 << 21); +} + +/**************************************************************************** + * Name: k230_hart_big_stop() + * Description: stop big core, can run in S-mode + ****************************************************************************/ + +void k230_hart_big_stop(void) +{ + if (k230_hart_is_big()) return; + + /* 0x10001 set RESET */ + + putreg32(RESET_RQST_BIT | RESET_RQST_ENW, K230_CPU1_RESET); + up_udelay(RESET_WAIT_USEC); + sinfo("reg: %x\n", getreg32(K230_CPU1_RESET)); +} + +/**************************************************************************** + * Name: k230_hart_big_boot() + * Description: start big core from given address, can run in S-mode + ****************************************************************************/ + +void k230_hart_big_boot(uintptr_t addr) +{ + if (k230_hart_is_big()) return; + + /* learned from U-Boot baremetal and RTT sysctl_reset_cpu */ + + if (addr) putreg32(addr, K230_CPU1_BOOTA); + sinfo("addr=%lx\n", addr); + + /* 0x10001000 clear DONE bit */ + + putreg32(RESET_DONE_BIT | RESET_DONE_ENW, K230_CPU1_RESET); + up_udelay(RESET_WAIT_USEC); + + /* 0x10001 set RQST bit */ + + putreg32(RESET_RQST_BIT | RESET_RQST_ENW, K230_CPU1_RESET); + up_udelay(RESET_WAIT_USEC); + + /* 0x10000 clear RQST bit */ + + putreg32(RESET_RQST_ENW, K230_CPU1_RESET); + up_udelay(RESET_WAIT_USEC); +} + +#endif /* !defined(CONFIG_BUILD_KERNEL) || defined(CONFIG_NUTTSBI) */ + +#ifdef CONFIG_NUTTSBI_LATE_INIT + +/**************************************************************************** + * Name: sbi_late_initialize + * Description: K230 specific setup in M-mode. + ****************************************************************************/ + +void sbi_late_initialize(void) +{ + /* delegate K230 plic enable to S-mode */ + + putreg32(1, K230_PLIC_CTRL); + k230_hart_init(); +} +#endif diff --git a/arch/risc-v/src/k230/k230_hart.h b/arch/risc-v/src/k230/k230_hart.h new file mode 100644 index 0000000000000..cd5a5cf9a11a4 --- /dev/null +++ b/arch/risc-v/src/k230/k230_hart.h @@ -0,0 +1,48 @@ +/**************************************************************************** + * arch/risc-v/src/k230/k230_hart.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_K230_K230_HART_H +#define __ARCH_RISCV_SRC_K230_K230_HART_H + +/**************************************************************************** + * Preprocessor Macros + ****************************************************************************/ + +#define CSR_MSECCFG 0x747 +#define CSR_MSECCFGH 0x757 + +#define MSECCFG_MML (1 << 0) +#define MSECCFG_RLB (1 << 2) + +/**************************************************************************** + * Public functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#if !defined(CONFIG_BUILD_KERNEL) || defined(CONFIG_NUTTSBI) + +void k230_hart_init(void); /* M-mode initialization */ +bool k230_hart_is_big(void); /* true if on big core */ +void k230_hart_big_boot(uintptr_t addr); /* turn on big core w/ boot addr */ +void k230_hart_big_stop(void); /* turn off big core */ + +#endif /* !defined(CONFIG_BUILD_KERNEL) || defined(CONFIG_NUTTSBI) */ +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_K230_K230_HART_H */ diff --git a/arch/risc-v/src/k230/k230_head.S b/arch/risc-v/src/k230/k230_head.S index 1509a41b67038..2673779ceb2c0 100644 --- a/arch/risc-v/src/k230/k230_head.S +++ b/arch/risc-v/src/k230/k230_head.S @@ -26,32 +26,44 @@ #include #include +#include #include "chip.h" #include "riscv_internal.h" +#include "riscv_macros.S" /**************************************************************************** * Public Symbols ****************************************************************************/ + /* Imported symbols */ + + .extern __trap_vec /* Exported Symbols */ .section .text + +#ifdef CONFIG_NUTTSBI + + .global __start_s + +__start_s: + +#else + .global __start __start: - /* Preserve a1 as it contains the pointer to DTB */ - /* Load mhartid (cpuid) */ +#endif - csrr a0, mhartid + /* Preserve a1 by not using it here as it contains DTB */ - /* Set stack pointer to the idle thread stack */ +#ifndef CONFIG_BUILD_KERNEL + /* Load mhartid (cpuid) */ - bnez a0, 1f - la sp, K230_IDLESTACK_TOP - j 2f -1: + csrr a0, CSR_MHARTID +#endif /* Load the number of CPUs that the kernel supports */ @@ -64,47 +76,21 @@ __start: /* If a0 (mhartid) >= t1 (the number of CPUs), stop here */ blt a0, t1, 3f - csrw mie, zero + csrw CSR_IE, zero wfi 3: - /* To get g_cpu_basestack[mhartid], must get g_cpu_basestack first */ - - la t0, g_cpu_basestack - - /* Offset = pointer width * hart id */ - -#ifdef CONFIG_ARCH_RV32 - slli t1, a0, 2 -#else - slli t1, a0, 3 -#endif - add t0, t0, t1 - - /* Load idle stack base to sp */ - - REGLOAD sp, 0(t0) - - /* - * sp (stack top) = sp + idle stack size - XCPTCONTEXT_SIZE - * - * Note: Reserve some space used by up_initial_state since we are already - * running and using the per CPU idle stack. - */ - - li t0, STACK_ALIGN_UP(CONFIG_IDLETHREAD_STACKSIZE - XCPTCONTEXT_SIZE) - add sp, sp, t0 - -2: + /* Set stack pointer to the idle thread stack */ + riscv_set_inital_sp K230_IDLESTACK_BASE, SMP_STACK_SIZE, a0 - /* Disable all interrupts (i.e. timer, external) in mie */ + /* Disable all interrupts (i.e. timer, external) */ - csrw mie, zero + csrw CSR_IE, zero - la t0, __trap_vec - csrw mtvec, t0 + la t0, __trap_vec /* __trap_dump */ + csrw CSR_TVEC, t0 - /* Jump to k230_start */ + /* Jump to k230_start, a0=mhartid, a1=dtb */ jal x1, k230_start diff --git a/arch/risc-v/src/k230/k230_ipi.c b/arch/risc-v/src/k230/k230_ipi.c new file mode 100644 index 0000000000000..9a4e9492d1296 --- /dev/null +++ b/arch/risc-v/src/k230/k230_ipi.c @@ -0,0 +1,207 @@ +/**************************************************************************** + * arch/risc-v/src/k230/k230_ipi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#if !defined(CONFIG_BUILD_KERNEL) || defined(CONFIG_NUTTSBI) + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "riscv_internal.h" +#include "chip.h" +#include "k230_ipi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define K230_IPI_IRQ(n) (K230_IRQ_IPI0 + n) +#define K230_SOC_RESET_ADDR 0x91101020ul +#define K230_MBOX_RESET_BIT 17 +#define K230_RESET_DELAY_US 100 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct k230_ipi_entry_s +{ + uint16_t role; /* role of this node */ + uint16_t mask; /* allowed line masks */ + ipi_callback_t cbfn; /* the callback function */ + void *args; /* argument for callback */ +}; + +/**************************************************************************** + * Private Variables + ****************************************************************************/ + +static mutex_t g_ipi_lock = NXMUTEX_INITIALIZER; + +static struct k230_ipi_entry_s g_ipi_confs[K230_IPI_DEVN_MAX + 1] = +{ + 0 +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int k230_ipi_isr(int irq, void *context, void *args) +{ + uint32_t devn = (uintptr_t)args; + bool remote = (g_ipi_confs[devn].role == IPI_ROLE_REMOTE); + uintptr_t regc = remote ? K230_IPI_M2R_INTCLR(devn): + K230_IPI_R2M_INTCLR(devn); + uintptr_t regs = remote ? K230_IPI_M2R_INTSTS(devn): + K230_IPI_R2M_INTSTS(devn); + uint32_t stat = getreg32(regs); + for (uint32_t i = 0; i <= K230_IPI_LINE_MAX; i++) + { + if (stat & (3 << (i << 1))) + { + g_ipi_confs[devn].cbfn(IPI_COMB(devn, i), g_ipi_confs[devn].args); + putreg32(i, regc); + } + } + + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int k230_ipi_init(uintptr_t devn, uint16_t mask, uint16_t role, + ipi_callback_t ipcb, void *args) +{ + int ret = -EBUSY; + bool master = (role == IPI_ROLE_MASTER); +#ifdef CONFIG_K230_IPI_RESET_ON_INIT + static bool mbox_reset = false; +#endif + + DEBUGASSERT(devn <= K230_IPI_DEVN_MAX); + DEBUGASSERT(mask); + DEBUGASSERT(ipcb); + DEBUGASSERT(role == IPI_ROLE_MASTER || role == IPI_ROLE_REMOTE); + + nxmutex_lock(&g_ipi_lock); + if (0 == g_ipi_confs[devn].role) + { + g_ipi_confs[devn].mask = mask; + g_ipi_confs[devn].cbfn = ipcb; + g_ipi_confs[devn].args = args; + g_ipi_confs[devn].role = role; + ret = 0; + } + + nxmutex_unlock(&g_ipi_lock); + + if (0 == ret) + { +#ifdef CONFIG_K230_IPI_RESET_UPON_INIT + /* Reset whole mailbox device */ + + if (master && !mbox_reset) + { + uint32_t val = getreg32(K230_SOC_RESET_ADDR); + val &= ~(1 << K230_MBOX_RESET_BIT); + putreg32(val, K230_SOC_RESET_ADDR); + up_udelay(K230_RESET_DELAY_US); + val |= (1 << K230_MBOX_RESET_BIT); + putreg32(val, K230_SOC_RESET_ADDR); + up_udelay(K230_RESET_DELAY_US); + mbox_reset = true; + sinfo("mbox reset @ %lx\n", K230_SOC_RESET_ADDR); + } + +#endif + /* Attach and enable the IRQ */ + + ret = irq_attach(K230_IPI_IRQ(devn), k230_ipi_isr, (void *)devn); + up_enable_irq(K230_IPI_IRQ(devn)); + + /* enable IPI device like RTT/Linux does */ + + uint32_t v = (master ? 3u : 1u) | (mask << 16); + putreg32(v, K230_IPI_R2M_INTEN(devn)); + putreg32(v, K230_IPI_M2R_INTEN(devn)); + } + + sinfo("devn=%ld,lmsk=%x,role=%c,r2me=%x,m2re=%x,ret=%d\n", + devn, mask, master ? 'M' : 'R', + getreg32(K230_IPI_R2M_INTEN(devn)), + getreg32(K230_IPI_M2R_INTEN(devn)), ret); + + return ret; +} + +void k230_ipi_notify(uint8_t devn, uint8_t line) +{ + DEBUGASSERT(devn <= K230_IPI_DEVN_MAX); + DEBUGASSERT(line <= K230_IPI_LINE_MAX); + + nxmutex_lock(&g_ipi_lock); + uint16_t role = g_ipi_confs[devn].role; + uint16_t mask = g_ipi_confs[devn].mask; + nxmutex_unlock(&g_ipi_lock); + + if ((1 << line) & mask) + { + bool master = (role == IPI_ROLE_MASTER); + uintptr_t regs = master ? K230_IPI_M2R_INTSET(devn): + K230_IPI_R2M_INTSET(devn); + putreg32(line, regs); + } +} + +void k230_ipi_finish(uint8_t devn, uint16_t mask) +{ + DEBUGASSERT(devn <= K230_IPI_DEVN_MAX); + DEBUGASSERT(g_ipi_confs[devn].mask == mask); + uint16_t role = g_ipi_confs[devn].role; + DEBUGASSERT(role == IPI_ROLE_MASTER || role == IPI_ROLE_MASTER); + + /* reset device and disable interrupts */ + + bool remote = (role == IPI_ROLE_REMOTE); + putreg32(2u | mask << 16, remote ? K230_IPI_M2R_INTEN(devn): + K230_IPI_R2M_INTEN(devn)); + up_disable_irq(K230_IPI_IRQ(devn)); + irq_detach(K230_IPI_IRQ(devn)); + + nxmutex_lock(&g_ipi_lock); + memset(g_ipi_confs + devn, 0, sizeof(g_ipi_confs[0])); + nxmutex_unlock(&g_ipi_lock); + sinfo("devn=%d,mask=%x\n", devn, mask); +} + +#endif /* !defined(CONFIG_BUILD_KERNEL) || defined(CONFIG_NUTTSBI) */ diff --git a/arch/risc-v/src/k230/k230_ipi.h b/arch/risc-v/src/k230/k230_ipi.h new file mode 100644 index 0000000000000..a159539e47f2e --- /dev/null +++ b/arch/risc-v/src/k230/k230_ipi.h @@ -0,0 +1,155 @@ +/**************************************************************************** + * arch/risc-v/src/k230/k230_ipi.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_K230_K230_IPI_H +#define __ARCH_RISCV_SRC_K230_K230_IPI_H + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* K230 has 4 IPI devices, each has 10 registers with 32 bit width. */ + +#define K230_IPI_DEVN_MAX 3 +#define K230_IPI_LINE_MAX 15 +#define K230_IPI_BASE(n) (0x91104000ul + n * 0x28) + +/* The IPI registers are organized in two directions (M2R or R2M), there are + * 5 registers for each direction, with 16 IPI lines for each node. Though + * K230 names the two directions as CPU2DSP or DSP2CPU, we use M2R or R2M. + * + * The Status register has 2-bit counter for each IPI line. + * The Set/Clear registers accepts values from 0..15 for 16 IPI lines. + * Setting a line increases its counter by 1, clearing the line decreases it + * by 1. The Error register further uses the high/low 16 bits to flag the + * over/under-run situations of counters. + * + * The Enable register's bit 16..31 are for line enable, bit 0 is for device + * interrupt enable, bit 1 for resetting line counters to zero. + * + * Also note the directions M2R/R2M are tied to the CPU cores: little core is + * M and big core is R. So we can also select the direction based on current + * core, but due to that we can't read correct MISA register value with NSBI + * booting environment, that method is not used and the role is passed in. + */ + +#define K230_IPI_M2R_INTEN(n) (K230_IPI_BASE(n) + 0) +#define K230_IPI_M2R_INTSET(n) (K230_IPI_BASE(n) + 4) +#define K230_IPI_M2R_INTCLR(n) (K230_IPI_BASE(n) + 8) +#define K230_IPI_M2R_INTSTS(n) (K230_IPI_BASE(n) + 12) +#define K230_IPI_M2R_INTERR(n) (K230_IPI_BASE(n) + 16) +#define K230_IPI_R2M_INTEN(n) (K230_IPI_BASE(n) + 20) +#define K230_IPI_R2M_INTSET(n) (K230_IPI_BASE(n) + 24) +#define K230_IPI_R2M_INTCLR(n) (K230_IPI_BASE(n) + 28) +#define K230_IPI_R2M_INTSTS(n) (K230_IPI_BASE(n) + 32) +#define K230_IPI_R2M_INTERR(n) (K230_IPI_BASE(n) + 36) + +#define IPI_ROLE_MASTER 1 /* master role, for little core */ +#define IPI_ROLE_REMOTE 2 /* remote role, for big core */ + +/* Tools for handling uint16_t device and line id combo */ + +#define IPI_DEVN(x) ((x & 0xFF00) >> 8) +#define IPI_LINE(x) (x & 0xFF) +#define IPI_COMB(d,l) ((d << 8) | (l & 0xFF)) + +/**************************************************************************** + * Public types + ****************************************************************************/ + +/**************************************************************************** + * Name: ipi_callback_t + * Description: + * Callback for a particular IPI line. Should be brief as maybe running in + * ISR context. + * Params; + * comb: combined IPI dev and line ids, see IPI_COMB above + * args: the args used in subscription + ****************************************************************************/ + +typedef void (*ipi_callback_t)(uint16_t comb, void *args); + +/**************************************************************************** + * Public functions + ****************************************************************************/ + +/**************************************************************************** + * Name: k230_ipi_init + * Description: + * Initialzie IPI device with receiving and sending line masks. + * Params: + * devn: IPI device number in 0..K230_IPI_DEVN_MAX + * mask: allowed lines mask for notifying peers or receiving notifications + * role: IPI role of this node (IPI_ROLE_MASTER or IPI_ROLE_REMOTE) + * ipcb: callback for incoming IPI notifications + * args: last parameter for the callback. + * Returns: + * 0 on success, or negative value on errors + ****************************************************************************/ + +int k230_ipi_init(uintptr_t devn, uint16_t mask, uint16_t role, + ipi_callback_t ipcb, void *args); + +/**************************************************************************** + * Name: k230_ipi_notify + * Description: + * Notify peers via IPI. + * Params: + * devn: device id in 0..K230_IPI_DEVN_MAX + * line: line id in 0..K230_IPI_LINE_MAX + ****************************************************************************/ + +void k230_ipi_notify(uint8_t devn, uint8_t line); + +/**************************************************************************** + * Name: k230_ipi_finish + * Description: + * Deinitializes IPI device + * Params: + * devn: IPI device number initialized previously. + * mask: line masks iniitialied previously. + ****************************************************************************/ + +void k230_ipi_finish(uint8_t devn, uint16_t mask); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_K230_K230_IPI_H */ diff --git a/arch/risc-v/src/k230/k230_irq.c b/arch/risc-v/src/k230/k230_irq.c index 1acfbc98e4079..0a6ea357d01b2 100644 --- a/arch/risc-v/src/k230/k230_irq.c +++ b/arch/risc-v/src/k230/k230_irq.c @@ -33,8 +33,11 @@ #include #include "riscv_internal.h" +#include "riscv_ipi.h" #include "chip.h" +#define STATUS_LOW (READ_CSR(CSR_STATUS) & 0xffffffff) /* STATUS low part */ + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -70,6 +73,8 @@ void up_irqinitialize(void) putreg32(1, (uintptr_t)(K230_PLIC_PRIORITY + 4 * id)); } + sinfo("prioritized %d irqs\n", NR_IRQS); + /* Set irq threshold to 0 (permits all global interrupts) */ putreg32(0, K230_PLIC_THRESHOLD); @@ -79,9 +84,9 @@ void up_irqinitialize(void) riscv_exception_attach(); #ifdef CONFIG_SMP - /* Clear RISCV_IPI for CPU0 */ + /* Clear IPI for CPU0 */ - putreg32(0, RISCV_IPI); + riscv_ipi_clear(0); up_enable_irq(RISCV_IRQ_SOFT); #endif @@ -114,7 +119,7 @@ void up_disable_irq(int irq) } else if (irq == RISCV_IRQ_TIMER) { - /* Read m/sstatus & clear timer interrupt enable in m/sie */ + /* Disable timer interrupt in m/sie */ CLEAR_CSR(CSR_IE, IE_TIE); } @@ -124,7 +129,7 @@ void up_disable_irq(int irq) /* Clear enable bit for the irq */ - if (0 <= extirq && extirq <= 63) + if (0 <= extirq && extirq <= K230_PLIC_IRQS) { modifyreg32(K230_PLIC_ENABLE1 + (4 * (extirq / 32)), 1 << (extirq % 32), 0); @@ -134,6 +139,8 @@ void up_disable_irq(int irq) PANIC(); } } + + sinfo("ie=%lx sts=%lx irq=%d\n", READ_CSR(CSR_IE), STATUS_LOW, irq); } /**************************************************************************** @@ -156,25 +163,17 @@ void up_enable_irq(int irq) } else if (irq == RISCV_IRQ_TIMER) { - /* Read m/sstatus & set timer interrupt enable in m/sie */ + /* Enable timer interrupt in m/sie */ SET_CSR(CSR_IE, IE_TIE); } -#ifdef CONFIG_BUILD_KERNEL - else if (irq == RISCV_IRQ_MTIMER) - { - /* Read m/sstatus & set timer interrupt enable in m/sie */ - - SET_CSR(mie, MIE_MTIE); - } -#endif else if (irq > RISCV_IRQ_EXT) { extirq = irq - RISCV_IRQ_EXT; - /* Set enable bit for the irq */ + /* Enable the irq in PLIC */ - if (0 <= extirq && extirq <= 63) + if (0 <= extirq && extirq < K230_PLIC_IRQS) { modifyreg32(K230_PLIC_ENABLE1 + (4 * (extirq / 32)), 0, 1 << (extirq % 32)); @@ -184,6 +183,8 @@ void up_enable_irq(int irq) PANIC(); } } + + sinfo("ie=%lx sts=%lx irq=%d\n", READ_CSR(CSR_IE), STATUS_LOW, irq); } irqstate_t up_irq_enable(void) @@ -197,6 +198,8 @@ irqstate_t up_irq_enable(void) /* Read and enable global interrupts (M/SIE) in m/sstatus */ oldstat = READ_AND_SET_CSR(CSR_STATUS, STATUS_IE); + sinfo("ie=%lx sts=%lx ctx=%d\n", READ_CSR(CSR_IE), STATUS_LOW, + XCPTCONTEXT_SIZE); return oldstat; } diff --git a/arch/risc-v/src/k230/k230_memorymap.h b/arch/risc-v/src/k230/k230_memorymap.h index 2932691b613dd..a8701d8616d11 100644 --- a/arch/risc-v/src/k230/k230_memorymap.h +++ b/arch/risc-v/src/k230/k230_memorymap.h @@ -39,7 +39,4 @@ #define K230_IDLESTACK_BASE _ebss #endif -#define K230_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3) -#define K230_IDLESTACK_TOP (K230_IDLESTACK_BASE + K230_IDLESTACK_SIZE) - #endif /* __ARCH_RISCV_SRC_K230_K230_MEMORYMAP_H */ diff --git a/arch/risc-v/src/k230/k230_mm_init.c b/arch/risc-v/src/k230/k230_mm_init.c index c3bbf154d7c1a..721d8e0b7285b 100644 --- a/arch/risc-v/src/k230/k230_mm_init.c +++ b/arch/risc-v/src/k230/k230_mm_init.c @@ -40,192 +40,124 @@ * Pre-processor Definitions ****************************************************************************/ -/* Map the whole I/O memory with vaddr = paddr mappings */ +#ifdef CONFIG_K230_PBMT_THEAD +/* T-Head Memory Type PTE definitions */ -#define MMU_IO_BASE (0x80400000) // KPU config -#define MMU_IO_SIZE (0x19c00000) // DDR config +# define _PAGE_SEC (1UL << 59) /* Security */ +# define _PAGE_SHARE (1UL << 60) /* Shareable */ +# define _PAGE_BUF (1UL << 61) /* Bufferable */ +# define _PAGE_CACHE (1UL << 62) /* Cacheable */ +# define _PAGE_SO (1UL << 63) /* Strong Order */ -#ifdef CONFIG_ARCH_MMU_TYPE_SV32 +# define _THEAD_PMA (_PAGE_SHARE | _PAGE_BUF | _PAGE_CACHE) +# define _THEAD_IO (_PAGE_BUF | _PAGE_SO) +# define _THEAD_NC (_PAGE_SHARE | _PAGE_BUF) -/* Physical and virtual addresses to page tables (vaddr = paddr mapping) */ +# define K230_DEV_FLAGS (_THEAD_IO | MMU_IO_FLAGS) +# define K230_TXT_FLAGS (_THEAD_PMA | MMU_KTEXT_FLAGS) +# define K230_DAT_FLAGS (_THEAD_PMA | MMU_KDATA_FLAGS) +# define K230_SHM_FLAGS (_THEAD_NC | MMU_KDATA_FLAGS) -#define PGT_L1_PBASE (uintptr_t)&m_l1_pgtable -#define PGT_L2_PBASE (uintptr_t)&m_l2_pgtable -#define PGT_L1_VBASE PGT_L1_PBASE -#define PGT_L2_VBASE PGT_L2_PBASE +#else +/* Svpbmt Memory Type PTE definitions */ -#define PGT_L1_SIZE (1024) /* Enough to map 4 GiB */ -#define PGT_L2_SIZE (3072) /* Enough to map 12 MiB */ +# define _PAGE_NC (1UL << 61) +# define _PAGE_IO (1UL << 62) -#define SLAB_COUNT (sizeof(m_l2_pgtable) / RV_MMU_PAGE_SIZE) +# define SVPBMT_PMA (0) +# define SVPBMT_IO (_PAGE_IO) +# define SVPBMT_NC (_PAGE_NC) -#define KMM_PAGE_SIZE RV_MMU_L2_PAGE_SIZE -#define KMM_PBASE PGT_L2_PBASE -#define KMM_PBASE_IDX 2 -#define KMM_SPBASE PGT_L1_PBASE -#define KMM_SPBASE_IDX 1 +# define K230_DEV_FLAGS (SVPBMT_IO | MMU_IO_FLAGS) +# define K230_SHM_FLAGS (SVPBMT_NC | MMU_KDATA_FLAGS) +# define K230_TXT_FLAGS (SVPBMT_PMA | MMU_KTEXT_FLAGS) +# define K230_DAT_FLAGS (SVPBMT_PMA | MMU_KDATA_FLAGS) +#endif -#elif CONFIG_ARCH_MMU_TYPE_SV39 +/* for PTE dump purposes, covers Svpbmt or MAEE w/o bit-59 */ -/* Physical and virtual addresses to page tables (vaddr = paddr mapping) */ +#define MMU_PBMT_MASK (0xful << 60) +#define MMU_PBMT_VAL(x) (((x) & MMU_PBMT_MASK) >> 60) -#define PGT_L1_PBASE (uintptr_t)&m_l1_pgtable -#define PGT_L2_PBASE (uintptr_t)&m_l2_pgtable -#define PGT_L3_PBASE (uintptr_t)&m_l3_pgtable -#define PGT_L1_VBASE PGT_L1_PBASE -#define PGT_L2_VBASE PGT_L2_PBASE -#define PGT_L3_VBASE PGT_L3_PBASE - -#define PGT_L1_SIZE (512) /* Enough to map 512 GiB */ -#define PGT_L2_SIZE (512) /* Enough to map 1 GiB */ -#define PGT_L3_SIZE (1024) /* Enough to map 4 MiB (2MiB x 2) */ +#define MMUFD(x) (uint16_t)(((x) & 0xff) | (MMU_PBMT_VAL(x) << 8)) -#define SLAB_COUNT (sizeof(m_l3_pgtable) / RV_MMU_PAGE_SIZE) +/* Map the whole I/O & PLIC memory with vaddr = paddr mappings */ -#define KMM_PAGE_SIZE RV_MMU_L3_PAGE_SIZE -#define KMM_PBASE PGT_L3_PBASE -#define KMM_PBASE_IDX 3 -#define KMM_SPBASE PGT_L2_PBASE -#define KMM_SPBASE_IDX 2 +#define MMU_DEV_BASE (0x80400000ul) /* KPU config */ +#define MMU_DEV_SIZE (0x11200000ul) /* 274MB till Hi-sys end */ +#define MMU_INT_BASE (0xF00000000ul) /* PLIC base */ +#define MMU_INT_SIZE (0x400000ul) /* 4MB for PLIC */ -#else -#error No valid MMU defined. +#ifdef CONFIG_RPTUN +#define MMU_SHM_BASE (uintptr_t)CONFIG_K230_RPTUN_SHM_ADDR +#define MMU_SHM_SIZE CONFIG_K230_RPTUN_SHM_SIZE #endif -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct pgalloc_slab_s -{ - sq_entry_t *next; - void *memory; -}; -typedef struct pgalloc_slab_s pgalloc_slab_t; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Kernel mappings simply here, mapping is vaddr=paddr */ - -static size_t m_l1_pgtable[PGT_L1_SIZE] locate_data(".pgtables"); -static size_t m_l2_pgtable[PGT_L2_SIZE] locate_data(".pgtables"); -#ifdef CONFIG_ARCH_MMU_TYPE_SV39 -static size_t m_l3_pgtable[PGT_L3_SIZE] locate_data(".pgtables"); +#ifndef CONFIG_ARCH_MMU_TYPE_SV39 +#error "No valid MMU type defined" #endif -/* Kernel mappings (L1 base) */ +/* Physical and virtual addresses to page tables (vaddr = paddr mapping) + * Note NUTTSBI kernel can live in small flash+ram regions thus needs L3. + * We also assume KFLASH and KSRAM can be held by one L3 table (4MB). + */ -uintptr_t g_kernel_mappings = PGT_L1_VBASE; -uintptr_t g_kernel_pgt_pbase = PGT_L1_PBASE; +#define PGT_L1_PBASE (uintptr_t)&m_l1_pgtable +#define PGT_L2_PBDDR (uintptr_t)&m_l2_pgt_ddr +#define PGT_L2_PBINT (uintptr_t)&m_l2_pgt_int +#define PGT_L2_PBDEV (uintptr_t)&m_l2_pgt_dev +#define PGT_L3_PBDDR (uintptr_t)&m_l3_pgt_ddr -/* L3 page table allocator */ +#define PGT_L1_VBASE PGT_L1_PBASE +#define PGT_L2_VBDDR PGT_L2_PBDDR +#define PGT_L2_VBINT PGT_L2_PBINT +#define PGT_L2_VBDEV PGT_L2_PBDEV +#define PGT_L3_VBDDR PGT_L3_PBDDR -static sq_queue_t g_free_slabs; -static pgalloc_slab_t g_slabs[SLAB_COUNT]; +#define PGT_L1_SIZE (512) /* Enough for 512 GiB */ +#define PGT_L2_SIZE (512) /* Enough for 1 GiB */ +#define PGT_L3_SIZE (1024) /* Enough for 4 MiB */ /**************************************************************************** - * Private Functions + * Private Types ****************************************************************************/ /**************************************************************************** - * Name: slab_init - * - * Description: - * Initialize slab allocator for L2 or L3 page table entries - * - * L2 Page table is used for SV32. L3 used for SV39 - * - * Input Parameters: - * start - Beginning of the L2 or L3 page table pool - * + * Private Data ****************************************************************************/ -static void slab_init(uintptr_t start) -{ - int i; +/* Kernel mapping use simple identical mapping (i.e. vaddr==paddr). */ - sq_init(&g_free_slabs); +static size_t m_l1_pgtable[PGT_L1_SIZE] locate_data(".pgtables"); +static size_t m_l2_pgt_dev[PGT_L2_SIZE] locate_data(".pgtables"); +static size_t m_l2_pgt_int[PGT_L2_SIZE] locate_data(".pgtables"); +static size_t m_l2_pgt_ddr[PGT_L2_SIZE] locate_data(".pgtables"); +static size_t m_l3_pgt_ddr[PGT_L3_SIZE] locate_data(".pgtables"); - for (i = 0; i < SLAB_COUNT; i++) - { - g_slabs[i].memory = (void *)start; - sq_addlast((sq_entry_t *)&g_slabs[i], (sq_queue_t *)&g_free_slabs); - start += RV_MMU_PAGE_SIZE; - } -} +/* Kernel mappings (L1 base) required by riscv_addrenv */ + +uintptr_t g_kernel_mappings = PGT_L1_VBASE; +uintptr_t g_kernel_pgt_pbase = PGT_L1_PBASE; /**************************************************************************** - * Name: slab_alloc - * - * Description: - * Allocate single slab for L2/L3 page table entry - * - * L2 Page table is used for SV32. L3 used for SV39 - * + * Private Functions ****************************************************************************/ -static uintptr_t slab_alloc(void) -{ - pgalloc_slab_t *slab = (pgalloc_slab_t *)sq_remfirst(&g_free_slabs); - return slab ? (uintptr_t)slab->memory : 0; -} - /**************************************************************************** - * Name: map_region - * - * Description: - * Map a region of physical memory to the L3 page table - * - * Input Parameters: - * paddr - Beginning of the physical address mapping - * vaddr - Beginning of the virtual address mapping - * size - Size of the region in bytes - * mmuflags - The MMU flags to use in the mapping - * + * Name: dump_pgtable dump one pagetable ****************************************************************************/ -static void map_region(uintptr_t paddr, uintptr_t vaddr, size_t size, - uint32_t mmuflags) +static void dump_pgtable(const size_t * pgt, uint32_t len, const char * name) { - uintptr_t endaddr; - uintptr_t pbase; - int npages; - int i; - int j; - - /* How many pages */ - - npages = (size + RV_MMU_PAGE_MASK) >> RV_MMU_PAGE_SHIFT; - endaddr = vaddr + size; - - for (i = 0; i < npages; i += RV_MMU_PAGE_ENTRIES) + minfo("%s at %lx\n", name, (size_t)pgt); + for (uint32_t i = 0; i < len ; i++) { - /* See if a mapping exists ? */ - - pbase = mmu_pte_to_paddr(mmu_ln_getentry( - KMM_SPBASE_IDX, KMM_SPBASE, vaddr)); - if (!pbase) - { - /* No, allocate 1 page, this must not fail */ - - pbase = slab_alloc(); - DEBUGASSERT(pbase); - - /* Map it to the new table */ - - mmu_ln_setentry( - KMM_SPBASE_IDX, KMM_SPBASE, pbase, vaddr, MMU_UPGT_FLAGS); - } - - /* Then add the mappings */ - - for (j = 0; j < RV_MMU_PAGE_ENTRIES && vaddr < endaddr; j++) + uintptr_t pte = (uintptr_t)pgt[i]; + if (pte & PTE_VALID) { - mmu_ln_setentry(KMM_PBASE_IDX, pbase, paddr, vaddr, mmuflags); - paddr += KMM_PAGE_SIZE; - vaddr += KMM_PAGE_SIZE; + minfo("#%03d paddr:%09lx flags:%03x %s\n", i, + mmu_pte_to_paddr(pte), MMUFD(pte), + (pte & PTE_LEAF_MASK)? "" : ">>>"); } } } @@ -245,45 +177,66 @@ static void map_region(uintptr_t paddr, uintptr_t vaddr, size_t size, void k230_kernel_mappings(void) { - /* Initialize slab allocator for the L2/L3 page tables */ + /* Map I/O region in L2 page table. */ - slab_init(KMM_PBASE); + minfo("\nflags: dev=%03x shm=%03x dat=%03x txt=%03x\n", + MMUFD(K230_DEV_FLAGS | PTE_VALID), MMUFD(K230_SHM_FLAGS | PTE_VALID), + MMUFD(K230_DAT_FLAGS | PTE_VALID), MMUFD(K230_TXT_FLAGS | PTE_VALID)); - /* Begin mapping memory to MMU; note that at this point the MMU is not yet - * active, so the page table virtual addresses are actually physical - * addresses and so forth. M-mode does not perform translations anyhow, so - * this mapping is quite simple to do - */ + minfo("map DEV L2(%ldMB)\n", MMU_DEV_SIZE >> 20); + mmu_ln_map_region(2, PGT_L2_VBDEV, MMU_DEV_BASE, MMU_DEV_BASE, + MMU_DEV_SIZE, K230_DEV_FLAGS); - /* Map I/O region, use enough large page tables for the IO region. */ + /* Map INT region using L2 page table */ - binfo("map I/O regions\n"); - mmu_ln_map_region(1, PGT_L1_VBASE, MMU_IO_BASE, MMU_IO_BASE, - MMU_IO_SIZE, MMU_IO_FLAGS); + minfo("map INT L2(%ldMB)\n", MMU_INT_SIZE >> 20); + mmu_ln_map_region(2, PGT_L2_VBINT, MMU_INT_BASE, MMU_INT_BASE, + MMU_INT_SIZE, K230_DEV_FLAGS); - /* Map the kernel text and data for L2/L3 */ + /* Map kernel area use L3 */ - binfo("map kernel text\n"); - map_region(KFLASH_START, KFLASH_START, KFLASH_SIZE, MMU_KTEXT_FLAGS); + minfo("map kernel L2/L3(%ldKB)\n", (KFLASH_SIZE + KSRAM_SIZE) >> 10); + mmu_ln_map_region(3, PGT_L3_VBDDR, KFLASH_START, KFLASH_START, + KFLASH_SIZE, K230_TXT_FLAGS); + mmu_ln_map_region(3, PGT_L3_VBDDR, KSRAM_START, KSRAM_START, + KSRAM_SIZE, K230_DAT_FLAGS); - binfo("map kernel data\n"); - map_region(KSRAM_START, KSRAM_START, KSRAM_SIZE, MMU_KDATA_FLAGS); + /* Map the page pool */ -#ifdef CONFIG_ARCH_MMU_TYPE_SV39 + minfo("map pgpool L2(%ldMB)\n", PGPOOL_SIZE >> 20); + mmu_ln_map_region(2, PGT_L2_VBDDR, PGPOOL_START, PGPOOL_START, + PGPOOL_SIZE, K230_DAT_FLAGS); - /* Connect the L1 and L2 page tables for the kernel text and data */ +#ifdef CONFIG_RPTUN + uintptr_t base; - binfo("connect the L1 and L2 page tables\n"); - mmu_ln_setentry(1, PGT_L1_VBASE, PGT_L2_PBASE, KFLASH_START, PTE_G); + /* map shared memory, 2MB aligned in either DDR or DEV/SRAM zone */ - /* Map the page pool */ + minfo("map shmem L2(%dKB)\n", (MMU_SHM_SIZE) >> 10); + base = (CONFIG_K230_RPTUN_SHM_ADDR >= 0x80000000) ? PGT_L2_VBDEV + : PGT_L2_VBDDR; + mmu_ln_map_region(2, base, MMU_SHM_BASE, MMU_SHM_BASE, + MMU_SHM_SIZE, K230_SHM_FLAGS); +#endif + + /* Connect page tables, two tables can only connect once. */ - binfo("map the page pool\n"); - mmu_ln_map_region(2, PGT_L2_VBASE, PGPOOL_START, PGPOOL_START, PGPOOL_SIZE, - MMU_KDATA_FLAGS); -#elif CONFIG_ARCH_MMU_TYPE_SV32 - binfo("map the page pool\n"); - map_region(PGPOOL_START, PGPOOL_START, PGPOOL_SIZE, MMU_KDATA_FLAGS); + minfo("connect L1, L2 and L3\n"); + mmu_ln_setentry(1, PGT_L1_VBASE, PGT_L2_PBDDR, KFLASH_START, 0); + mmu_ln_setentry(1, PGT_L1_VBASE, PGT_L2_PBDEV, MMU_DEV_BASE, 0); + mmu_ln_setentry(1, PGT_L1_VBASE, PGT_L2_PBINT, MMU_INT_BASE, 0); + mmu_ln_setentry(2, PGT_L2_VBDDR, PGT_L3_PBDDR, KFLASH_START, 0); + + /* dump page tables */ + +#ifdef DEBUG_MM + dump_pgtable(m_l1_pgtable, PGT_L1_SIZE, "L1"); + dump_pgtable(m_l2_pgt_dev, PGT_L2_SIZE, "L2_DEV"); + dump_pgtable(m_l2_pgt_int, PGT_L2_SIZE, "L2_INT"); + dump_pgtable(m_l2_pgt_ddr, PGT_L2_SIZE, "L2_DDR"); + dump_pgtable(m_l3_pgt_ddr, PGT_L3_SIZE, "L3_DDR"); +#else + UNUSED(dump_pgtable); #endif } @@ -302,8 +255,6 @@ void k230_mm_init(void) k230_kernel_mappings(); - /* Enable MMU (note: system is still in M-mode) */ - - binfo("mmu_enable: satp=%" PRIuPTR "\n", g_kernel_pgt_pbase); + minfo("mmu_enable: satp=%lx\n", g_kernel_pgt_pbase); mmu_enable(g_kernel_pgt_pbase, 0); } diff --git a/arch/risc-v/src/k230/k230_rptun.c b/arch/risc-v/src/k230/k230_rptun.c new file mode 100644 index 0000000000000..f511d0d4a2c6a --- /dev/null +++ b/arch/risc-v/src/k230/k230_rptun.c @@ -0,0 +1,339 @@ +/**************************************************************************** + * arch/risc-v/src/k230/k230_rptun.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include +#include "hardware/k230_memorymap.h" +#include "riscv_internal.h" +#include "k230_hart.h" +#include "k230_ipi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define rpinfo rpmsginfo +#define rpwarn rpmsgwarn +#define rperr rpmsgerr + +/* Vring config parameters taken from nrf53_rptun */ + +#define VRINGS 2 /* Number of vrings */ +#define VRING_ALIGN 8 /* Vring alignment */ +#define VRING_NR 8 /* Number of descriptors */ +#define VRING_SIZE 512 /* Size of one descriptor */ + +/* The RPMSG default channel used with only one RPMSG channel */ + +#define VRING_SHMEM (CONFIG_K230_RPTUN_SHM_ADDR) /* Vring addr */ +#define VRING0_NOTIFYID (RSC_NOTIFY_ID_ANY) /* Vring0 id */ +#define VRING1_NOTIFYID (RSC_NOTIFY_ID_ANY) /* Vring1 id */ + +#define VRING_SHMEM_END (VRING_SHMEM + CONFIG_K230_RPTUN_SHM_SIZE) + +/* Design notes: + * + * Though there are 16 IPI lines per K230 IPI device, we use only 1 IPI + * line for each core to notify the peer. Later we will see if more lines + * are really needed. + * + * For configurations, master and remote builds should use same IPI device + * defined by CONFIG_K230_RPTUN_IPI_DEVN otherwise the IPI notifications + * won't reach each other. + */ + +#define RPTUN_IPI_DEVN CONFIG_K230_RPTUN_IPI_DEV +#define RPTUN_IPI_LINE 0 +#define RPTUN_IPI_LINE_MASK (1 << RPTUN_IPI_LINE) + +#if RPTUN_IPI_DEVN < 0 || RPTUN_IPI_DEVN > K230_IPI_DEVN_MAX +#error Invalid K230_RPTUN_IPI_DEV number +#endif + +#ifdef CONFIG_K230_RPTUN_MASTER +#define RPTUN_IPI_ROLE IPI_ROLE_MASTER +#else +#define RPTUN_IPI_ROLE IPI_ROLE_REMOTE +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct k230_rptun_shmem_s +{ + volatile uintptr_t base; + struct rptun_rsc_s rsc; +}; + +struct k230_rptun_dev_s +{ + struct rptun_dev_s rptun; + rptun_callback_t callback; + void *arg; + bool master; + struct k230_rptun_shmem_s *shmem; + struct simple_addrenv_s addrenv[VRINGS]; + char peername[RPMSG_NAME_SIZE + 1]; +}; + +#define as_k230_rptun_dev(d) container_of(d, struct k230_rptun_dev_s, rptun) + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static const char *rp_get_cpuname(struct rptun_dev_s *dev); +static struct rptun_rsc_s *rp_get_resource(struct rptun_dev_s *dev); +static bool rp_is_autostart(struct rptun_dev_s *dev); +static bool rp_is_master(struct rptun_dev_s *dev); +static int rp_start(struct rptun_dev_s *dev); +static int rp_stop(struct rptun_dev_s *dev); +static int rp_notify(struct rptun_dev_s *dev, uint32_t notifyid); +static int rp_set_callback(struct rptun_dev_s *, rptun_callback_t, void *); +static void k230_rptun_callback(uint16_t comb, void *args); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct rptun_ops_s g_k230_rptun_ops = +{ + .get_cpuname = rp_get_cpuname, + .get_resource = rp_get_resource, + .is_autostart = rp_is_autostart, + .is_master = rp_is_master, + .start = rp_start, + .stop = rp_stop, + .notify = rp_notify, + .register_callback = rp_set_callback, +}; + +#define SHMEM (struct k230_rptun_shmem_s*)VRING_SHMEM +#define SHMEM_SIZE sizeof(struct k230_rptun_shmem_s) +#define SHMEM_END (VRING_SHMEM + SHMEM_SIZE) + +static struct k230_rptun_dev_s g_rptun_dev; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static const char *rp_get_cpuname(struct rptun_dev_s *dev) +{ + struct k230_rptun_dev_s *priv = as_k230_rptun_dev(dev); + return priv->peername; +} + +static struct rptun_rsc_s *rp_get_resource(struct rptun_dev_s *dev) +{ + struct k230_rptun_dev_s *priv = as_k230_rptun_dev(dev); + struct rptun_rsc_s *rsc; + + if (priv->shmem != NULL) + { + return &priv->shmem->rsc; + } + + priv->shmem = SHMEM; + + if (priv->master) + { + /* Perform initial setup */ + + rsc = &priv->shmem->rsc; + + rsc->rsc_tbl_hdr.ver = 1; + rsc->rsc_tbl_hdr.num = 1; + rsc->rsc_tbl_hdr.reserved[0] = 0; + rsc->rsc_tbl_hdr.reserved[1] = 0; + rsc->offset[0] = offsetof(struct rptun_rsc_s, + rpmsg_vdev); + + rsc->rpmsg_vdev.type = RSC_VDEV; + rsc->rpmsg_vdev.id = VIRTIO_ID_RPMSG; + rsc->rpmsg_vdev.dfeatures = 1 << VIRTIO_RPMSG_F_NS + | 1 << VIRTIO_RPMSG_F_ACK + | 1 << VIRTIO_RPMSG_F_BUFSZ; + rsc->rpmsg_vdev.config_len = sizeof(struct fw_rsc_config); + rsc->rpmsg_vdev.num_of_vrings = VRINGS; + + rsc->rpmsg_vring0.align = VRING_ALIGN; + rsc->rpmsg_vring0.num = VRING_NR; + rsc->rpmsg_vring0.notifyid = VRING0_NOTIFYID; + rsc->rpmsg_vring1.align = VRING_ALIGN; + rsc->rpmsg_vring1.num = VRING_NR; + rsc->rpmsg_vring1.notifyid = VRING1_NOTIFYID; + rsc->config.r2h_buf_size = VRING_SIZE; + rsc->config.h2r_buf_size = VRING_SIZE; + + priv->shmem->base = (uintptr_t)priv->shmem; + + rpinfo("shmem:%lx, dev:%p\n", priv->shmem->base, dev); + } + else + { + /* TODO: use IPI later, polling now. */ + + rpinfo("wait for shmem %p...\n", priv->shmem); + while (priv->shmem->base == 0) + { + nxsig_usleep(100); + } + + rpinfo("shmem:%lx, dev:%p\n", priv->shmem->base, dev); + } + + return &priv->shmem->rsc; +} + +static bool rp_is_autostart(struct rptun_dev_s *dev) +{ + return true; +} + +static bool rp_is_master(struct rptun_dev_s *dev) +{ + struct k230_rptun_dev_s *priv = as_k230_rptun_dev(dev); + return priv->master; +} + +static int rp_start(struct rptun_dev_s *dev) +{ + rpinfo("%p\n", dev); +#ifdef CONFIG_K230_RPTUN_MASTER + k230_hart_big_boot(0x7000000); +#endif + return 0; +} + +static int rp_stop(struct rptun_dev_s *dev) +{ + rpinfo("%p\n", dev); +#ifdef CONFIG_K230_RPTUN_MASTER + k230_hart_big_stop(); +#endif + return 0; +} + +static int rp_notify(struct rptun_dev_s *dev, uint32_t vqid) +{ + UNUSED(dev); + UNUSED(vqid); + k230_ipi_notify(RPTUN_IPI_DEVN, RPTUN_IPI_LINE); + return 0; +} + +static int rp_set_callback(struct rptun_dev_s *dev, rptun_callback_t cb, + void *arg) +{ + struct k230_rptun_dev_s *priv = as_k230_rptun_dev(dev); + + priv->callback = cb; + priv->arg = arg; + return 0; +} + +static void k230_rptun_callback(uint16_t comb, void *args) +{ + UNUSED(comb); + struct k230_rptun_dev_s *dev = args; + if (dev->callback) dev->callback(dev->arg, RPTUN_NOTIFY_ALL); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int k230_rptun_init(const char *peername) +{ + struct k230_rptun_dev_s *dev = &g_rptun_dev; + int ret = OK; + + memset(dev, 0, sizeof(*dev)); + +#ifdef CONFIG_K230_RPTUN_MASTER + /* master is responsible for initializing shmem */ + + memset((void *)SHMEM, 0, SHMEM_SIZE); + rpinfo("cleared %ld @ %p\n", SHMEM_SIZE, SHMEM); + dev->master = true; +#else + dev->master = false; +#endif + + ret = k230_ipi_init(RPTUN_IPI_DEVN, RPTUN_IPI_LINE_MASK, RPTUN_IPI_ROLE, + k230_rptun_callback, dev); + if (ret < 0) + { + rperr("k230_ipi_init failed %d\n", ret); + goto ipierr; + } + + /* Configure device */ + + dev->rptun.ops = &g_k230_rptun_ops; + strncpy(dev->peername, peername, RPMSG_NAME_SIZE); + + ret = rptun_initialize(&dev->rptun); + if (ret < 0) + { + rperr("rptun_initialize failed %d!\n", ret); + goto errout; + } + + return 0; + +errout: + k230_ipi_finish(RPTUN_IPI_DEVN, RPTUN_IPI_LINE_MASK); + +ipierr: + return ret; +} diff --git a/arch/risc-v/src/k230/k230_rptun.h b/arch/risc-v/src/k230/k230_rptun.h new file mode 100644 index 0000000000000..835a8108b5ac8 --- /dev/null +++ b/arch/risc-v/src/k230/k230_rptun.h @@ -0,0 +1,62 @@ +/**************************************************************************** + * arch/risc-v/src/k230/k230_rptun.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_K230_K230_RPTUN_H +#define __ARCH_RISCV_SRC_K230_K230_RPTUN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: k230_rptun_init + * Description: initializes a K230 RPTUN device. + * Parameters: + * peername: the name of the peer that this RPTUN links to + * Returns: OK on success, or negated number on error + ****************************************************************************/ + +int k230_rptun_init(const char *peername); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_K230_K230_RPTUN_H */ diff --git a/arch/risc-v/src/k230/k230_start.c b/arch/risc-v/src/k230/k230_start.c index cf46c685f9c05..abc378188cb28 100644 --- a/arch/risc-v/src/k230/k230_start.c +++ b/arch/risc-v/src/k230/k230_start.c @@ -24,20 +24,22 @@ #include +#include #include #include #include +#include #include #include "riscv_internal.h" #include "chip.h" -#ifdef CONFIG_BUILD_KERNEL -# include "k230_mm_init.h" +#ifdef CONFIG_BUILD_PROTECTED +# include "k230_userspace.h" #endif -#ifdef CONFIG_DEVICE_TREE -# include +#ifdef CONFIG_BUILD_KERNEL +# include "k230_mm_init.h" #endif /**************************************************************************** @@ -55,43 +57,50 @@ #endif /**************************************************************************** - * Extern Function Declarations + * Name: k230_clear_bss ****************************************************************************/ -#ifdef CONFIG_BUILD_KERNEL -extern void __trap_vec(void); -extern void __trap_vec_m(void); -extern void up_mtimer_initialize(void); -#endif +static void k230_clear_bss(void) +{ + uint32_t *dest; + + /* Doing this inline just to be sure on the state of global variables. */ + + for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; ) + { + *dest++ = 0; + } +} +#ifndef CONFIG_BUILD_KERNEL /**************************************************************************** - * Name: k230_clear_bss + * Name: k230_copy_init_data ****************************************************************************/ -void k230_clear_bss(void) +static void k230_copy_init_data(void) { + const uint32_t *src; uint32_t *dest; - /* Clear .bss. We'll do this inline (vs. calling memset) just to be - * certain that there are no issues with the state of global variables. + /* Move the initialized data from their temporary holding spot at FLASH + * into the correct place in SRAM. The correct place in SRAM is given + * by _sdata and _edata. The temporary location is in FLASH at the + * end of all of the other read-only data (.text, .rodata) at _eronly. */ - for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; ) + for (src = (const uint32_t *)_eronly, + dest = (uint32_t *)_sdata; dest < (uint32_t *)_edata; + ) { - *dest++ = 0; + *dest++ = *src++; } } +#endif /**************************************************************************** * Public Data ****************************************************************************/ -/* NOTE: g_idle_topstack needs to point the top of the idle stack - * for CPU0 and this value is used in up_initial_state() - */ - -uintptr_t g_idle_topstack = K230_IDLESTACK_TOP; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -100,12 +109,27 @@ uintptr_t g_idle_topstack = K230_IDLESTACK_TOP; * Name: k230_start ****************************************************************************/ -#ifdef CONFIG_BUILD_KERNEL -void k230_start_s(int mhartid, const char *dtb) -#else void k230_start(int mhartid, const char *dtb) -#endif { + if (0 == mhartid) + { + k230_clear_bss(); + +#ifdef CONFIG_RISCV_PERCPU_SCRATCH + riscv_percpu_add_hart(mhartid); +#else + k230_copy_init_data(); +#endif + } + +#ifndef CONFIG_BUILD_KERNEL + k230_hart_init(); +#endif + + /* Disable MMU */ + + WRITE_CSR(CSR_SATP, 0x0); + /* Configure FPU */ riscv_fpuconfig(); @@ -115,14 +139,6 @@ void k230_start(int mhartid, const char *dtb) goto cpux; } -#ifndef CONFIG_BUILD_KERNEL - k230_clear_bss(); -#endif - -#ifdef CONFIG_DEVICE_TREE - fdt_register(dtb); -#endif - showprogress('A'); #ifdef USE_EARLYSERIALINIT @@ -133,9 +149,11 @@ void k230_start(int mhartid, const char *dtb) /* Do board initialization */ -#ifdef CONFIG_BUILD_KERNEL - /* Setup page tables for kernel and enable MMU */ +#ifdef CONFIG_BUILD_PROTECTED + k230_userspace(); +#endif +#ifdef CONFIG_BUILD_KERNEL k230_mm_init(); #endif @@ -157,83 +175,25 @@ void k230_start(int mhartid, const char *dtb) } } -#ifdef CONFIG_BUILD_KERNEL - -/**************************************************************************** - * Name: k230_start - ****************************************************************************/ - -void k230_start(int mhartid, const char *dtb) -{ - /* NOTE: still in M-mode */ - - if (0 == mhartid) - { - k230_clear_bss(); - - /* Initialize the per CPU areas */ - - riscv_percpu_add_hart(mhartid); - } - - /* Disable MMU and enable PMP */ - - WRITE_CSR(satp, 0x0); - WRITE_CSR(pmpaddr0, 0x3fffffffffffffull); - WRITE_CSR(pmpcfg0, 0xf); - - /* Set exception and interrupt delegation for S-mode */ - - WRITE_CSR(medeleg, 0xffff); - WRITE_CSR(mideleg, 0xffff); - - /* Allow to write satp from S-mode */ - - CLEAR_CSR(mstatus, MSTATUS_TVM); - - /* Set mstatus to S-mode and enable SUM */ - - CLEAR_CSR(mstatus, ~MSTATUS_MPP_MASK); - SET_CSR(mstatus, MSTATUS_MPPS | SSTATUS_SUM); - - /* Set the trap vector for S-mode */ - - WRITE_CSR(stvec, (uintptr_t)__trap_vec); - - /* Set the trap vector for M-mode */ - - WRITE_CSR(mtvec, (uintptr_t)__trap_vec_m); - - if (0 == mhartid) - { - /* Only the primary CPU needs to initialize mtimer - * before entering to S-mode - */ - - up_mtimer_initialize(); - } - - /* Set mepc to the entry */ - - WRITE_CSR(mepc, (uintptr_t)k230_start_s); - - /* Set a0 to mhartid and a1 to dtb explicitly and enter to S-mode */ - - asm volatile ( - "mv a0, %0 \n" - "mv a1, %1 \n" - "mret \n" - :: "r" (mhartid), "r" (dtb) - ); -} -#endif - void riscv_earlyserialinit(void) { +#ifdef CONFIG_16550_UART u16550_earlyserialinit(); +#endif } void riscv_serialinit(void) { +#ifdef CONFIG_16550_UART u16550_serialinit(); +#endif } + +#ifdef CONFIG_RPMSG_UART_CONSOLE +int up_putc(int ch) +{ + /* place holder for now */ + + return ch; +} +#endif diff --git a/arch/risc-v/src/k230/k230_timerisr.c b/arch/risc-v/src/k230/k230_timerisr.c index 1b82f98909eb5..ff97e1cf3e518 100644 --- a/arch/risc-v/src/k230/k230_timerisr.c +++ b/arch/risc-v/src/k230/k230_timerisr.c @@ -38,7 +38,6 @@ #include "riscv_internal.h" #include "riscv_mtimer.h" -#include "riscv_percpu.h" #include "hardware/k230_memorymap.h" #include "hardware/k230_clint.h" @@ -46,78 +45,14 @@ * Pre-processor Definitions ****************************************************************************/ -#define MTIMER_FREQ 10000000 -#define TICK_COUNT (10000000 / TICK_PER_SEC) - -#ifdef CONFIG_BUILD_KERNEL - /**************************************************************************** * Private Data ****************************************************************************/ -static uint32_t g_mtimer_cnt = 0; -static uint32_t g_stimer_pending = false; - /**************************************************************************** * Private Functions for S-mode ****************************************************************************/ -/**************************************************************************** - * Name: k230_ssoft_interrupt - * - * Description: - * This function is S-mode software interrupt handler to proceed - * the OS timer - * - ****************************************************************************/ - -static int k230_ssoft_interrupt(int irq, void *context, void *arg) -{ - /* Cleaer Supervisor Software Interrupt */ - - CLEAR_CSR(sip, SIP_SSIP); - - if (g_stimer_pending) - { - g_stimer_pending = false; - - /* Proceed the OS timer */ - - nxsched_process_timer(); - } -#ifdef CONFIG_SMP - else - { - /* We assume IPI has been issued */ - - riscv_pause_handler(irq, context, arg); - } -#endif - - return 0; -} - -/**************************************************************************** - * Name: k230_reload_mtimecmp - * - * Description: - * This function is called during start-up to initialize mtimecmp - * for CONFIG_BUILD_KERNEL=y - * - ****************************************************************************/ - -static void k230_reload_mtimecmp(void) -{ - uint64_t current; - uint64_t next; - - current = READ_CSR(time); - next = current + TICK_COUNT; - putreg64(next, K230_CLINT_MTIMECMP); -} - -#endif /* CONFIG_BUILD_KERNEL */ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -126,86 +61,16 @@ static void k230_reload_mtimecmp(void) * Name: up_timer_initialize * * Description: - * This function is called during start-up to initialize - * the timer interrupt. - * + * This function is called during start-up to initialize timer interrupt ****************************************************************************/ void up_timer_initialize(void) { -#ifndef CONFIG_BUILD_KERNEL + /* KERNEL mode ignores CLINT addresses and use SBI timer. */ struct oneshot_lowerhalf_s *lower = riscv_mtimer_initialize( - K230_CLINT_MTIME, K230_CLINT_MTIMECMP, - RISCV_IRQ_MTIMER, MTIMER_FREQ); + K230_TIME, K230_TIMECMP, K230_IRQ_TIMER, K230_CLINT_FREQ); DEBUGASSERT(lower); - up_alarm_set_lowerhalf(lower); -#else - /* NOTE: This function is called in S-mode */ - - irq_attach(RISCV_IRQ_SSOFT, k230_ssoft_interrupt, NULL); - up_enable_irq(RISCV_IRQ_SSOFT); -#endif -} - -#ifdef CONFIG_BUILD_KERNEL - -/**************************************************************************** - * Name: up_mtimer_initialize - * - * Description: - * This function is called during start-up to initialize the M-mode timer - * - ****************************************************************************/ - -void up_mtimer_initialize(void) -{ - uintptr_t irqstacktop = riscv_percpu_get_irqstack(); - - /* Set the irq stack base to mscratch */ - - WRITE_CSR(mscratch, - irqstacktop - STACK_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK)); - - /* NOTE: we do not attach a handler for mtimer, - * because it is handled in the exception_m directly - */ - - up_enable_irq(RISCV_IRQ_MTIMER); - k230_reload_mtimecmp(); } - -/**************************************************************************** - * Name: k230_mtimer_interrupt - * - * Description: - * In RISC-V with S-mode, M-mode timer must be handled in M-mode - * This function is called from exception_m in M-mode directly - * - ****************************************************************************/ - -void k230_mtimer_interrupt(void) -{ - uint64_t current; - uint64_t next; - - /* Update mtimercmp */ - - current = getreg64(K230_CLINT_MTIMECMP); - next = current + TICK_COUNT; - putreg64(next, K230_CLINT_MTIMECMP); - - g_mtimer_cnt++; - g_stimer_pending = true; - - if (OSINIT_HW_READY()) - { - /* Post Supervisor Software Interrupt */ - - SET_CSR(sip, SIP_SSIP); - } -} - -#endif /* CONFIG_BUILD_KERNEL */ diff --git a/arch/risc-v/src/k230/k230_userspace.c b/arch/risc-v/src/k230/k230_userspace.c new file mode 100644 index 0000000000000..c1e1135a90ec7 --- /dev/null +++ b/arch/risc-v/src/k230/k230_userspace.c @@ -0,0 +1,134 @@ +/**************************************************************************** + * arch/risc-v/src/k230/k230_userspace.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "k230_userspace.h" +#include "riscv_internal.h" + +#ifdef CONFIG_BUILD_PROTECTED + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define UFLASH_F (PMPCFG_A_NAPOT | PMPCFG_X | PMPCFG_R) +#define USRAM_F (PMPCFG_A_NAPOT | PMPCFG_W | PMPCFG_R) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: configure_mpu + * + * Description: + * This function configures the MPU for for kernel- / userspace separation. + * It will also grant access to the page table memory for the supervisor. + * + ****************************************************************************/ + +static void configure_mpu(void); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: k230_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + ****************************************************************************/ + +void k230_userspace(void) +{ + uint8_t *src; + uint8_t *dest; + uint8_t *end; + + /* Clear all of user-space .bss */ + + DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 && + USERSPACE->us_bssstart <= USERSPACE->us_bssend); + + dest = (uint8_t *)USERSPACE->us_bssstart; + end = (uint8_t *)USERSPACE->us_bssend; + + while (dest != end) + { + *dest++ = 0; + } + + /* Initialize all of user-space .data */ + + DEBUGASSERT(USERSPACE->us_datasource != 0 && + USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 && + USERSPACE->us_datastart <= USERSPACE->us_dataend); + + src = (uint8_t *)USERSPACE->us_datasource; + dest = (uint8_t *)USERSPACE->us_datastart; + end = (uint8_t *)USERSPACE->us_dataend; + + while (dest != end) + { + *dest++ = *src++; + } + + /* Configure MPU / PMP to grant access to the userspace */ + + configure_mpu(); +} + +/**************************************************************************** + * Name: configure_mpu + * + * Description: + * This function configures the MPU for for kernel- / userspace separation. + * + ****************************************************************************/ + +static void configure_mpu(void) +{ + riscv_append_pmp_region(UFLASH_F, UFLASH_START, UFLASH_SIZE); + riscv_append_pmp_region(USRAM_F, USRAM_START, USRAM_SIZE); +} + +#endif /* CONFIG_BUILD_PROTECTED */ diff --git a/arch/risc-v/src/k230/k230_userspace.h b/arch/risc-v/src/k230/k230_userspace.h new file mode 100644 index 0000000000000..0e6f82625bbf2 --- /dev/null +++ b/arch/risc-v/src/k230/k230_userspace.h @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/risc-v/src/k230/k230_userspace.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_k230_k230_USERSPACE_H +#define __ARCH_RISCV_SRC_k230_k230_USERSPACE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: k230_userspace + * + * Description: + * For the case of the separate user-/kernel-space build, perform whatever + * platform specific initialization of the user memory is required. + * Normally this just means initializing the user space .data and .bss + * segments. + * + ****************************************************************************/ + +#ifdef CONFIG_BUILD_PROTECTED +void k230_userspace(void); +#endif + +#endif /* __ARCH_RISCV_SRC_k230_k230_USERSPACE_H */ diff --git a/arch/risc-v/src/litex/Kconfig b/arch/risc-v/src/litex/Kconfig index 83b4fbd6d5b71..ac4f36985ba71 100644 --- a/arch/risc-v/src/litex/Kconfig +++ b/arch/risc-v/src/litex/Kconfig @@ -18,6 +18,10 @@ config LITEX_COHERENT_DMA Select this option if the soft core was build with coherent DMA. When selected, dcache is considered coherent and not invalidated before DMA transfers. +config LITEX_FDT_MEMORY_ADDRESS + hex "Location of the FDT in memory" + default 0x41ec0000 + menu "LITEX Peripheral Support" # These "hidden" settings determine whether a peripheral option is available diff --git a/arch/risc-v/src/litex/litex_head.S b/arch/risc-v/src/litex/litex_head.S index 9c1563c14ab92..37c59c54bdcc8 100644 --- a/arch/risc-v/src/litex/litex_head.S +++ b/arch/risc-v/src/litex/litex_head.S @@ -47,13 +47,13 @@ __start: /* Disable all interrupts (i.e. timer, external) in mie */ - csrw mie, zero + csrw CSR_MIE, zero /* Initialize the Machine Trap Vector */ lui t0, %hi(__trap_vec) addi t0, t0, %lo(__trap_vec) - csrw mtvec, t0 + csrw CSR_MTVEC, t0 /* Jump to __litex_start */ diff --git a/arch/risc-v/src/litex/litex_irq.c b/arch/risc-v/src/litex/litex_irq.c index af59cdd15711c..f73472b015edd 100644 --- a/arch/risc-v/src/litex/litex_irq.c +++ b/arch/risc-v/src/litex/litex_irq.c @@ -53,7 +53,7 @@ void up_irqinitialize(void) #ifdef CONFIG_ARCH_USE_S_MODE putreg32(0x0, LITEX_PLIC_ENABLE1); -#else +#else asm volatile ("csrw %0, %1" :: "i"(LITEX_MMASK_CSR), "r"(0)); #endif @@ -147,13 +147,13 @@ void up_disable_irq(int irq) { /* Read mstatus & clear machine software interrupt enable in mie */ - CLEAR_CSR(mie, MIE_MSIE); + CLEAR_CSR(CSR_MIE, MIE_MSIE); } else if (irq == RISCV_IRQ_MTIMER) { /* Read mstatus & clear machine timer interrupt enable in mie */ - CLEAR_CSR(mie, MIE_MTIE); + CLEAR_CSR(CSR_MIE, MIE_MTIE); } else if (irq > RISCV_IRQ_MEXT) { @@ -228,13 +228,13 @@ void up_enable_irq(int irq) { /* Read mstatus & set machine software interrupt enable in mie */ - SET_CSR(mie, MIE_MSIE); + SET_CSR(CSR_MIE, MIE_MSIE); } else if (irq == RISCV_IRQ_MTIMER) { /* Read mstatus & set machine timer interrupt enable in mie */ - SET_CSR(mie, MIE_MTIE); + SET_CSR(CSR_MIE, MIE_MTIE); } else if (irq > RISCV_IRQ_MEXT) { diff --git a/arch/risc-v/src/litex/litex_memorymap.h b/arch/risc-v/src/litex/litex_memorymap.h index bd1a8b230746e..3ef63e03c5db6 100644 --- a/arch/risc-v/src/litex/litex_memorymap.h +++ b/arch/risc-v/src/litex/litex_memorymap.h @@ -25,6 +25,7 @@ * Included Files ****************************************************************************/ +#include "riscv_common_memorymap.h" #include "hardware/litex_memorymap.h" #include "hardware/litex_uart.h" #include "hardware/litex_clint.h" @@ -42,6 +43,6 @@ #define LITEX_IDLESTACK_BASE _ebss #endif -#define LITEX_IDLESTACK_TOP (LITEX_IDLESTACK_BASE + CONFIG_IDLETHREAD_STACKSIZE) +#define LITEX_IDLESTACK_TOP (LITEX_IDLESTACK_BASE + SMP_STACK_SIZE) #endif /* __ARCH_RISCV_SRC_LITEX_LITEX_MEMORYMAP_H */ diff --git a/arch/risc-v/src/litex/litex_serial.c b/arch/risc-v/src/litex/litex_serial.c index 21fc262a26243..919ed9faa9955 100644 --- a/arch/risc-v/src/litex/litex_serial.c +++ b/arch/risc-v/src/litex/litex_serial.c @@ -237,7 +237,7 @@ static void up_serialout(struct up_dev_s *priv, int offset, uint32_t value) static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) { - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(NULL); priv->im = im; @@ -245,7 +245,7 @@ static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) LITEX_CONSOLE_BASE + UART_EV_PENDING_OFFSET); up_serialout(priv, UART_EV_ENABLE_OFFSET, im); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -254,7 +254,7 @@ static void up_restoreuartint(struct up_dev_s *priv, uint8_t im) static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) { - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(NULL); /* Return the current interrupt mask value */ @@ -271,7 +271,7 @@ static void up_disableuartint(struct up_dev_s *priv, uint8_t *im) LITEX_CONSOLE_BASE + UART_EV_PENDING_OFFSET); up_serialout(priv, UART_EV_ENABLE_OFFSET, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/risc-v/src/litex/litex_shead.S b/arch/risc-v/src/litex/litex_shead.S index 03b4809d0f75e..6899171ba3bc1 100644 --- a/arch/risc-v/src/litex/litex_shead.S +++ b/arch/risc-v/src/litex/litex_shead.S @@ -56,25 +56,23 @@ __start: /* Disable all interrupts in sie */ - - csrw sie, zero - csrw sip, zero - + csrw CSR_SIE, zero + csrw CSR_SIP, zero /* Set the S-mode trap vector */ la t0, __trap_vec - csrw stvec, t0 + csrw CSR_STVEC, t0 /* Clear sscratch */ - csrw sscratch, zero - csrw scause, zero - csrw sepc, zero + csrw CSR_SSCRATCH, zero + csrw CSR_SCAUSE, zero + csrw CSR_SEPC, zero /* initialize global pointer, global data */ - + .option push .option norelax la gp, __global_pointer$ diff --git a/arch/risc-v/src/litex/litex_start.c b/arch/risc-v/src/litex/litex_start.c index 751111caf514d..a3107a40a7d77 100644 --- a/arch/risc-v/src/litex/litex_start.c +++ b/arch/risc-v/src/litex/litex_start.c @@ -26,6 +26,7 @@ #include +#include #include #include @@ -55,18 +56,6 @@ * Public Data ****************************************************************************/ -/* g_idle_topstack: _sbss is the start of the BSS region as defined by the - * linker script. _ebss lies at the end of the BSS region. The idle task - * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. - * The IDLE thread is the thread that the system boots on and, eventually, - * becomes the IDLE, do nothing task that runs only when there is nothing - * else to run. The heap continues from there until the end of memory. - * g_idle_topstack is a read-only variable the provides this computed - * address. - */ - -uintptr_t g_idle_topstack = LITEX_IDLESTACK_TOP; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -75,8 +64,11 @@ uintptr_t g_idle_topstack = LITEX_IDLESTACK_TOP; * Name: __litex_start ****************************************************************************/ -void __litex_start(void) +void __litex_start(int hart_index, const void * fdt, int arg) { + (void)hart_index; + (void)arg; + const uint32_t *src; uint32_t *dest; @@ -104,7 +96,18 @@ void __litex_start(void) *dest++ = *src++; } -#ifdef CONFIG_LITEX_CORE_VEXRISCV_SMP + /* Assume the FDT address was passed in if not NULL */ + + if (fdt) + { + fdt_register(fdt); + } + else + { + fdt_register((const char *)CONFIG_LITEX_FDT_MEMORY_ADDRESS); + } + +#ifdef CONFIG_RISCV_PERCPU_SCRATCH riscv_percpu_add_hart(0); #endif diff --git a/arch/risc-v/src/mpfs/Kconfig b/arch/risc-v/src/mpfs/Kconfig index 9ba677b2acf52..c84284c533dbc 100644 --- a/arch/risc-v/src/mpfs/Kconfig +++ b/arch/risc-v/src/mpfs/Kconfig @@ -791,6 +791,12 @@ config MPFS_ETHMAC_REGDEBUG endmenu +config MPFS_MPUCFG + bool "Enable MPUCFG driver" + default n + ---help--- + Enable driver to set MPUCFG entries. + config MPFS_HAVE_CORERMII bool "CoreRMII FPGA IP block configured" default n diff --git a/arch/risc-v/src/mpfs/Make.defs b/arch/risc-v/src/mpfs/Make.defs index 6e060cef60e07..1f4403ca43b52 100644 --- a/arch/risc-v/src/mpfs/Make.defs +++ b/arch/risc-v/src/mpfs/Make.defs @@ -58,6 +58,10 @@ ifeq ($(CONFIG_I2C),y) CHIP_CSRCS += mpfs_i2c.c endif +ifneq ($(filter y,$(CONFIG_MPFS_EMMCSD) $(CONFIG_MPFS_COREMMC)),) +CHIP_CSRCS += mpfs_sdio.c +endif + ifeq ($(CONFIG_MPFS_EMMCSD),y) CHIP_CSRCS += mpfs_emmcsd.c endif @@ -108,3 +112,7 @@ ifeq ($(CONFIG_MPFS_CORESPI),y) CHIP_CSRCS += mpfs_corespi.c endif +ifeq ($(CONFIG_MPFS_MPUCFG),y) +CHIP_CSRCS += mpfs_mpu.c +endif + diff --git a/arch/risc-v/src/mpfs/mpfs_coremmc.c b/arch/risc-v/src/mpfs/mpfs_coremmc.c index 02d8bd7499ad6..ebc836afd645e 100644 --- a/arch/risc-v/src/mpfs/mpfs_coremmc.c +++ b/arch/risc-v/src/mpfs/mpfs_coremmc.c @@ -45,10 +45,12 @@ #include -#include "mpfs_emmcsd.h" +#include "mpfs_coremmc.h" #include "riscv_internal.h" #include "hardware/mpfs_coremmc.h" +#include "mpfs_sdio_dev.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -158,54 +160,6 @@ * Private Types ****************************************************************************/ -/* This structure defines the state of the MPFS eMMCSD interface */ - -struct mpfs_dev_s -{ - struct sdio_dev_s dev; /* Standard, base SDIO interface */ - - const uintptr_t hw_base; /* Base address */ - const int plic_irq; /* PLIC interrupt */ - bool clk_enabled; /* Clk state */ - - /* Event support */ - - sem_t waitsem; /* Implements event waiting */ - sdio_eventset_t waitevents; /* Set of events to be waited for */ - uint32_t waitmask; /* Interrupt enables for event waiting */ - volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */ - struct wdog_s waitwdog; /* Watchdog that handles event timeouts */ - - /* Callback support */ - - sdio_statset_t cdstatus; /* Card status */ - sdio_eventset_t cbevents; /* Set of events to be cause callbacks */ - worker_t callback; /* Registered callback function */ - void *cbarg; /* Registered callback argument */ - struct work_s cbwork; /* Callback work queue structure */ - - /* Interrupt mode data transfer support */ - - uint32_t *buffer; /* Address of current R/W buffer */ - size_t remaining; /* Number of bytes remaining in the transfer */ - size_t receivecnt; /* Real count to receive */ - uint32_t xfrmask; /* Interrupt enables for data transfer */ - uint32_t xfr_blkmask; /* Interrupt enables for SB/MB data transfer */ - - bool widebus; /* Required for DMA support */ - bool onebit; /* true: Only 1-bit transfers are supported */ - - /* Data transfer support */ - - bool polltransfer; /* Indicate a poll transfer, no DMA */ - bool multiblock; /* Indicate a multi-block transfer */ - - /* Misc */ - - uint32_t blocksize; /* Current block size */ - uint32_t fifo_depth; /* Fifo size, read from the register */ -}; - union { uint32_t w; @@ -1951,7 +1905,7 @@ static int mpfs_recvlong(struct sdio_dev_s *dev, uint32_t cmd, getreg8(MPFS_COREMMC_RR14) << 8 | getreg8(MPFS_COREMMC_RR15); - mcinfo("recv: %08" PRIx32 " %08" PRIx32 " %08" PRIx32 " %08" \ + mcinfo("recv: %08" PRIx32 " %08" PRIx32 " %08" PRIx32 " %08" PRIx32"\n", rlong[0], rlong[1], rlong[2], rlong[3]); } @@ -2277,7 +2231,7 @@ static void mpfs_callback(void *arg) ****************************************************************************/ /**************************************************************************** - * Name: sdio_initialize + * Name: mpfs_coremmc_sdio_initialize * * Description: * Initialize SDIO for operation. @@ -2291,7 +2245,7 @@ static void mpfs_callback(void *arg) * ****************************************************************************/ -struct sdio_dev_s *sdio_initialize(int slotno) +struct sdio_dev_s *mpfs_coremmc_sdio_initialize(int slotno) { struct mpfs_dev_s *priv = &g_coremmc_dev; @@ -2308,7 +2262,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) } /**************************************************************************** - * Name: sdio_mediachange + * Name: mpfs_coremmc_sdio_mediachange * * Description: * Called by board-specific logic -- possible from an interrupt handler -- @@ -2326,7 +2280,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) * ****************************************************************************/ -void sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot) +void mpfs_coremmc_sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot) { struct mpfs_dev_s *priv = (struct mpfs_dev_s *)dev; sdio_statset_t cdstatus; @@ -2359,7 +2313,7 @@ void sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot) } /**************************************************************************** - * Name: sdio_wrprotect + * Name: mpfs_coremmc_sdio_wrprotect * * Description: * Called by board-specific logic to report if the card in the slot is @@ -2374,7 +2328,7 @@ void sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot) * ****************************************************************************/ -void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect) +void mpfs_coremmc_sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect) { struct mpfs_dev_s *priv = (struct mpfs_dev_s *)dev; irqstate_t flags; diff --git a/arch/risc-v/src/mpfs/mpfs_coremmc.h b/arch/risc-v/src/mpfs/mpfs_coremmc.h index 86cc90dca2ff3..95bf79b4d3b9b 100644 --- a/arch/risc-v/src/mpfs/mpfs_coremmc.h +++ b/arch/risc-v/src/mpfs/mpfs_coremmc.h @@ -48,7 +48,7 @@ extern "C" #endif /**************************************************************************** - * Name: sdio_initialize + * Name: mpfs_coremmc_sdio_initialize * * Description: * Initialize SDIO for operation. @@ -63,10 +63,10 @@ extern "C" ****************************************************************************/ struct sdio_dev_s; /* See include/nuttx/sdio.h */ -struct sdio_dev_s *sdio_initialize(int slotno); +struct sdio_dev_s *mpfs_coremmc_sdio_initialize(int slotno); /**************************************************************************** - * Name: sdio_mediachange + * Name: mpfs_coremmc_sdio_mediachange * * Description: * Called by board-specific logic -- possibly from an interrupt handler -- @@ -84,10 +84,10 @@ struct sdio_dev_s *sdio_initialize(int slotno); * ****************************************************************************/ -void sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot); +void mpfs_coremmc_sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot); /**************************************************************************** - * Name: sdio_wrprotect + * Name: mpfs_coremmc_sdio_wrprotect * * Description: * Called by board-specific logic to report if the card in the slot is @@ -102,7 +102,7 @@ void sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot); * ****************************************************************************/ -void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect); +void mpfs_coremmc_sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/risc-v/src/mpfs/mpfs_corespi.c b/arch/risc-v/src/mpfs/mpfs_corespi.c index f92ed0123c8e1..e4931f86f7508 100644 --- a/arch/risc-v/src/mpfs/mpfs_corespi.c +++ b/arch/risc-v/src/mpfs/mpfs_corespi.c @@ -1435,6 +1435,22 @@ static void mpfs_spi_init(struct spi_dev_s *dev) mpfs_spi_set_master_mode(priv, 1); mpfs_spi_enable(priv, 1); + /* Disable all interrupt sources */ + + modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_INTTXTURUN | + MPFS_SPI_INTRXOVRFLOW | + MPFS_SPI_INTTXDONE, + 0); + + /* Clear all interrupt sources */ + + putreg32(MPFS_SPI_TXCHUNDRUN | + MPFS_SPI_RXCHOVRFLW | + MPFS_SPI_DATA_RX | + MPFS_SPI_TXDONE, MPFS_SPI_INT_CLEAR); + + /* Then enable the interrupt */ + up_enable_irq(priv->plic_irq); } diff --git a/arch/risc-v/src/mpfs/mpfs_emmcsd.c b/arch/risc-v/src/mpfs/mpfs_emmcsd.c index 267894dc81c1e..249b4c5ca264e 100644 --- a/arch/risc-v/src/mpfs/mpfs_emmcsd.c +++ b/arch/risc-v/src/mpfs/mpfs_emmcsd.c @@ -50,6 +50,8 @@ #include "hardware/mpfs_emmcsd.h" #include "hardware/mpfs_mpucfg.h" +#include "mpfs_sdio_dev.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -291,58 +293,6 @@ * Private Types ****************************************************************************/ -/* This structure defines the state of the MPFS eMMCSD interface */ - -struct mpfs_dev_s -{ - struct sdio_dev_s dev; /* Standard, base SDIO interface */ - - const uintptr_t hw_base; /* Base address */ - const int plic_irq; /* PLIC interrupt */ - bool clk_enabled; /* Clk state */ - - /* eMMC / SD and HW parameters */ - - const bool emmc; /* eMMC or SD */ - int bus_voltage; /* Bus voltage */ - int bus_mode; /* eMMC Bus mode */ - bool jumpers_3v3; /* Jumper settings: 1v8 or 3v3 */ - - /* Event support */ - - sem_t waitsem; /* Implements event waiting */ - sdio_eventset_t waitevents; /* Set of events to be waited for */ - uint32_t waitmask; /* Interrupt enables for event waiting */ - volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */ - struct wdog_s waitwdog; /* Watchdog that handles event timeouts */ - - /* Callback support */ - - sdio_statset_t cdstatus; /* Card status */ - sdio_eventset_t cbevents; /* Set of events to be cause callbacks */ - worker_t callback; /* Registered callback function */ - void *cbarg; /* Registered callback argument */ - struct work_s cbwork; /* Callback work queue structure */ - - /* Interrupt mode data transfer support */ - - uint32_t *buffer; /* Address of current R/W buffer */ - size_t remaining; /* Number of bytes remaining in the transfer */ - size_t receivecnt; /* Real count to receive */ - uint32_t xfrmask; /* Interrupt enables for data transfer */ - - bool widebus; /* Required for DMA support */ - bool onebit; /* true: Only 1-bit transfers are supported */ - - /* DMA data transfer support */ - - bool polltransfer; /* Indicate a poll transfer, no DMA */ - - /* Misc */ - - uint32_t blocksize; /* Current block size */ -}; - /**************************************************************************** * Private Function Prototypes ****************************************************************************/ @@ -1135,14 +1085,14 @@ static int mpfs_emmcsd_interrupt(int irq, void *context, void *arg) { mcinfo("Card inserted!\n"); - sdio_mediachange((struct sdio_dev_s *)priv, true); + mpfs_emmcsd_sdio_mediachange((struct sdio_dev_s *)priv, true); putreg32(MPFS_EMMCSD_SRS12_CIN, MPFS_EMMCSD_SRS12); } else if (status & MPFS_EMMCSD_SRS12_CR) { mcinfo("Card removed!\n"); - sdio_mediachange((struct sdio_dev_s *)priv, false); + mpfs_emmcsd_sdio_mediachange((struct sdio_dev_s *)priv, false); putreg32(MPFS_EMMCSD_SRS12_CR, MPFS_EMMCSD_SRS12); } else @@ -2604,7 +2554,7 @@ static int mpfs_recvlong(struct sdio_dev_s *dev, uint32_t cmd, rlong[3] = tmp << 8; - mcinfo("recv: %08" PRIx32 " %08" PRIx32 " %08" PRIx32 " %08" \ + mcinfo("recv: %08" PRIx32 " %08" PRIx32 " %08" PRIx32 " %08" PRIx32"\n", rlong[0], rlong[1], rlong[2], rlong[3]); } @@ -2948,7 +2898,7 @@ static void mpfs_callback(void *arg) ****************************************************************************/ /**************************************************************************** - * Name: sdio_initialize + * Name: mpfs_emmcsd_sdio_initialize * * Description: * Initialize SDIO for operation. @@ -2962,7 +2912,7 @@ static void mpfs_callback(void *arg) * ****************************************************************************/ -struct sdio_dev_s *sdio_initialize(int slotno) +struct sdio_dev_s *mpfs_emmcsd_sdio_initialize(int slotno) { struct mpfs_dev_s *priv = NULL; priv = &g_emmcsd_dev; @@ -2973,14 +2923,14 @@ struct sdio_dev_s *sdio_initialize(int slotno) if (!mpfs_device_reset(&priv->dev)) { - return NULL; + return (struct sdio_dev_s *)NULL; } - return &priv->dev; + return (struct sdio_dev_s *) &priv->dev; } /**************************************************************************** - * Name: sdio_mediachange + * Name: mpfs_emmcsd_sdio_mediachange * * Description: * Called by board-specific logic -- possible from an interrupt handler -- @@ -2998,7 +2948,7 @@ struct sdio_dev_s *sdio_initialize(int slotno) * ****************************************************************************/ -void sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot) +void mpfs_emmcsd_sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot) { struct mpfs_dev_s *priv = (struct mpfs_dev_s *)dev; sdio_statset_t cdstatus; @@ -3031,7 +2981,7 @@ void sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot) } /**************************************************************************** - * Name: sdio_wrprotect + * Name: mpfs_emmcsd_sdio_wrprotect * * Description: * Called by board-specific logic to report if the card in the slot is @@ -3046,7 +2996,7 @@ void sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot) * ****************************************************************************/ -void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect) +void mpfs_emmcsd_sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect) { struct mpfs_dev_s *priv = (struct mpfs_dev_s *)dev; irqstate_t flags; diff --git a/arch/risc-v/src/mpfs/mpfs_emmcsd.h b/arch/risc-v/src/mpfs/mpfs_emmcsd.h index 3f1e0f562453d..40e90a91dccd9 100644 --- a/arch/risc-v/src/mpfs/mpfs_emmcsd.h +++ b/arch/risc-v/src/mpfs/mpfs_emmcsd.h @@ -48,7 +48,7 @@ extern "C" #endif /**************************************************************************** - * Name: sdio_initialize + * Name: mpfs_emmcsd_sdio_initialize * * Description: * Initialize SDIO for operation. @@ -63,10 +63,10 @@ extern "C" ****************************************************************************/ struct sdio_dev_s; /* See include/nuttx/sdio.h */ -struct sdio_dev_s *sdio_initialize(int slotno); +struct sdio_dev_s *mpfs_emmcsd_sdio_initialize(int slotno); /**************************************************************************** - * Name: sdio_mediachange + * Name: mpfs_emmcsd_sdio_mediachange * * Description: * Called by board-specific logic -- possibly from an interrupt handler -- @@ -84,10 +84,10 @@ struct sdio_dev_s *sdio_initialize(int slotno); * ****************************************************************************/ -void sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot); +void mpfs_emmcsd_sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot); /**************************************************************************** - * Name: sdio_wrprotect + * Name: mpfs_emmcsd_sdio_wrprotect * * Description: * Called by board-specific logic to report if the card in the slot is @@ -102,7 +102,7 @@ void sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot); * ****************************************************************************/ -void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect); +void mpfs_emmcsd_sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/risc-v/src/mpfs/mpfs_head.S b/arch/risc-v/src/mpfs/mpfs_head.S index ec2c3d3a04cf2..b223c84ec7605 100644 --- a/arch/risc-v/src/mpfs/mpfs_head.S +++ b/arch/risc-v/src/mpfs/mpfs_head.S @@ -45,25 +45,25 @@ __start: /* Disable all interrupts (i.e. timer, external) in mie */ - csrw mie, zero - csrw mip, zero + csrw CSR_MIE, zero + csrw CSR_MIP, zero /* Initialize the Machine Trap Vector */ la t0, __trap_vec - csrw mtvec, t0 + csrw CSR_MTVEC, t0 /* Make sure that mtvec is updated before continuing */ 1: - csrr t1, mtvec + csrr t1, CSR_MTVEC bne t0, t1, 1b /* mscratch must be init to zero- we are not using scratch memory */ - csrw mscratch, zero - csrw mcause, zero - csrw mepc, zero + csrw CSR_MSCRATCH, zero + csrw CSR_MCAUSE, zero + csrw CSR_MEPC, zero li x1, 0 li x2, 0 li x3, 0 @@ -97,17 +97,17 @@ __start: li x31, 0 /* Skip delegation register, mmu and floating point initializations if E51 */ - csrr a0, mhartid + csrr a0, CSR_MHARTID beqz a0, .skip_e51 /* Delegation registers must be explicitly reset */ - csrw mideleg, 0 - csrw medeleg, 0 + csrw CSR_MIDELEG, 0 + csrw CSR_MEDELEG, 0 /* Remove MMU mappings (if any) */ - csrw satp, zero + csrw CSR_SATP, zero fence /* Flush TLB (does not make a difference really) */ @@ -131,8 +131,8 @@ __start: #ifdef CONFIG_MPFS_BOOTLOADER /* Clear PMP */ - csrw pmpcfg0, zero - csrw pmpcfg2, zero + csrw CSR_PMPCFG0, zero + csrw CSR_PMPCFG2, zero /* Set all but the boot hart into wfi */ @@ -142,7 +142,7 @@ __start: /* Enable IRQ_M_SOFT */ li a2, (1U << 3) - csrw mie, a2 /* Set MSIE bit to receive IPI */ + csrw CSR_MIE, a2 /* Set MSIE bit to receive IPI */ /* flush the instruction cache */ fence.i @@ -155,15 +155,15 @@ __start: * interrupt */ - csrr a2, mip + csrr a2, CSR_MIP andi a2, a2, (1U << 3) /* MIP_MSIP */ beqz a2, .wait_boot /* Disable and clear all interrupts (the sw interrupt) */ li a2, 0x00000008 /* MSTATUS_MIE */ - csrc mstatus, a2 - csrw mie, zero - csrw mip, zero + csrc CSR_MSTATUS, a2 + csrw CSR_MIE, zero + csrw CSR_MIP, zero /* Jump to application */ tail mpfs_jump_to_app diff --git a/arch/risc-v/src/mpfs/mpfs_i2c.c b/arch/risc-v/src/mpfs/mpfs_i2c.c index 26fa4408eb14e..63ffe6006de52 100644 --- a/arch/risc-v/src/mpfs/mpfs_i2c.c +++ b/arch/risc-v/src/mpfs/mpfs_i2c.c @@ -83,7 +83,10 @@ typedef enum mpfs_i2c_status MPFS_I2C_SUCCESS = 0u, MPFS_I2C_IN_PROGRESS, MPFS_I2C_FAILED, - MPFS_I2C_TIMED_OUT + MPFS_I2C_FAILED_SLAW_NACK, + MPFS_I2C_FAILED_SLAR_NACK, + MPFS_I2C_FAILED_TX_DATA_NACK, + MPFS_I2C_FAILED_BUS_ERROR, } mpfs_i2c_status_t; typedef enum mpfs_i2c_clock_divider @@ -123,6 +126,8 @@ static const uint32_t mpfs_i2c_freqs_fpga[MPFS_I2C_NUMBER_OF_DIVIDERS] = MPFS_FPGA_BCLK / 8 }; +static int mpfs_i2c_irq(int cpuint, void *context, void *arg); + static int mpfs_i2c_transfer(struct i2c_master_s *dev, struct i2c_msg_s *msgs, int count); @@ -298,8 +303,67 @@ static uint32_t mpfs_i2c_timeout(int msgc, struct i2c_msg_s *msgv); static int mpfs_i2c_init(struct mpfs_i2c_priv_s *priv) { + int ret = OK; + uint32_t ctrl; + uint32_t status; + if (!priv->initialized) { + /* In case of warm boot, or after reset, check that the IP block is + * not already active and try to recover from any pending data + * transfer if it is. + */ + + ctrl = getreg32(MPFS_I2C_CTRL); + if (ctrl != 0) + { + /* Check if the IP is enabled */ + + status = getreg32(MPFS_I2C_STATUS); + if (ctrl & MPFS_I2C_CTRL_ENS1_MASK) + { + if (status == MPFS_I2C_ST_RX_DATA_ACK) + { + /* In case the machine was in the middle of data RX, try to + * receive one byte and nack it + */ + + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_AA_MASK, 0); + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_SI_MASK, 0); + usleep(100); + status = getreg32(MPFS_I2C_STATUS); + } + + if (status != MPFS_I2C_ST_IDLE) + { + /* If the bus is not idle, send STOP */ + + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_SI_MASK, 0); + modifyreg32(MPFS_I2C_CTRL, 0, MPFS_I2C_CTRL_STO_MASK); + usleep(100); + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_SI_MASK, 0); + status = getreg32(MPFS_I2C_STATUS); + } + } + + if (status != MPFS_I2C_ST_IDLE) + { + i2cerr("Bus not idle before init\n"); + } + + /* Disable IP and continue initialization */ + + putreg32(0, MPFS_I2C_CTRL); + } + + /* Attach interrupt */ + + ret = irq_attach(priv->plic_irq, mpfs_i2c_irq, priv); + if (ret != OK) + { + return ret; + } + if (priv->fpga) { /* FIC3 is used by many, don't reset it here, or many @@ -358,10 +422,9 @@ static int mpfs_i2c_init(struct mpfs_i2c_priv_s *priv) putreg32(priv->ser_address, MPFS_I2C_ADDR); - /* Enable i2c bus */ + /* Enable i2c bus, clear all other bits */ - modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_ENS1_MASK, - MPFS_I2C_CTRL_ENS1_MASK); + putreg32(MPFS_I2C_CTRL_ENS1_MASK, MPFS_I2C_CTRL); priv->initialized = true; } @@ -385,8 +448,7 @@ static void mpfs_i2c_deinit(struct mpfs_i2c_priv_s *priv) up_disable_irq(priv->plic_irq); irq_detach(priv->plic_irq); - modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_ENS1_MASK, - ~MPFS_I2C_CTRL_ENS1_MASK); + putreg32(0, MPFS_I2C_CTRL); priv->initialized = false; } @@ -437,8 +499,6 @@ static int mpfs_i2c_irq(int cpuint, void *context, void *arg) volatile uint32_t status; uint8_t clear_irq = 1u; - DEBUGASSERT(msg != NULL); - status = getreg32(MPFS_I2C_STATUS); switch (status) @@ -472,14 +532,23 @@ static int mpfs_i2c_irq(int cpuint, void *context, void *arg) case MPFS_I2C_ST_SLAW_NACK: modifyreg32(MPFS_I2C_CTRL, 0, MPFS_I2C_CTRL_STO_MASK); - priv->status = MPFS_I2C_FAILED; + priv->status = MPFS_I2C_FAILED_SLAW_NACK; break; case MPFS_I2C_ST_SLAW_ACK: case MPFS_I2C_ST_TX_DATA_ACK: if (priv->tx_idx < priv->tx_size) { - DEBUGASSERT(priv->tx_buffer != NULL); + if (priv->tx_buffer == NULL) + { + i2cerr("ERROR: tx_buffer is NULL!\n"); + + /* Clear the serial interrupt flag and exit */ + + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_SI_MASK, 0); + return 0; + } + putreg32(priv->tx_buffer[priv->tx_idx], MPFS_I2C_DATA); priv->tx_idx++; } @@ -493,7 +562,10 @@ static int mpfs_i2c_irq(int cpuint, void *context, void *arg) /* Jump to the next message */ - priv->msgid++; + if (priv->msgid < (priv->msgc - 1)) + { + priv->msgid++; + } } else { @@ -512,7 +584,10 @@ static int mpfs_i2c_irq(int cpuint, void *context, void *arg) /* Jump to the next message */ - priv->msgid++; + if (priv->msgid < (priv->msgc - 1)) + { + priv->msgid++; + } } else { @@ -525,7 +600,7 @@ static int mpfs_i2c_irq(int cpuint, void *context, void *arg) case MPFS_I2C_ST_TX_DATA_NACK: modifyreg32(MPFS_I2C_CTRL, 0, MPFS_I2C_CTRL_STO_MASK); - priv->status = MPFS_I2C_FAILED; + priv->status = MPFS_I2C_FAILED_TX_DATA_NACK; break; case MPFS_I2C_ST_SLAR_ACK: /* SLA+R tx'ed. */ @@ -547,14 +622,22 @@ static int mpfs_i2c_irq(int cpuint, void *context, void *arg) case MPFS_I2C_ST_SLAR_NACK: /* SLA+R tx'ed; send a stop condition */ modifyreg32(MPFS_I2C_CTRL, 0, MPFS_I2C_CTRL_STO_MASK); - priv->status = MPFS_I2C_FAILED; + priv->status = MPFS_I2C_FAILED_SLAR_NACK; break; case MPFS_I2C_ST_RX_DATA_ACK: + if (priv->rx_buffer == NULL) + { + i2cerr("ERROR: rx_buffer is NULL!\n"); + + /* Clear the serial interrupt flag and exit */ + + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_SI_MASK, 0); + return 0; + } /* Data byte received, ACK returned */ - DEBUGASSERT(priv->rx_buffer != NULL); priv->rx_buffer[priv->rx_idx] = (uint8_t)getreg32(MPFS_I2C_DATA); priv->rx_idx++; @@ -566,13 +649,31 @@ static int mpfs_i2c_irq(int cpuint, void *context, void *arg) case MPFS_I2C_ST_RX_DATA_NACK: + /* Some sanity checks */ + + if (priv->rx_buffer == NULL) + { + i2cerr("ERROR: rx_buffer is NULL!\n"); + + /* Clear the serial interrupt flag and exit */ + + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_SI_MASK, 0); + return 0; + } + else if (priv->rx_idx >= priv->rx_size) + { + i2cerr("ERROR: rx_idx is out of bounds!\n"); + + /* Clear the serial interrupt flag and exit */ + + modifyreg32(MPFS_I2C_CTRL, MPFS_I2C_CTRL_SI_MASK, 0); + return 0; + } + /* Data byte received, NACK returned */ - DEBUGASSERT(priv->rx_buffer != NULL); - DEBUGASSERT(priv->rx_idx < priv->rx_size); priv->rx_buffer[priv->rx_idx] = (uint8_t)getreg32(MPFS_I2C_DATA); priv->rx_idx++; - priv->status = MPFS_I2C_SUCCESS; modifyreg32(MPFS_I2C_CTRL, 0, MPFS_I2C_CTRL_STO_MASK); break; @@ -613,7 +714,7 @@ static int mpfs_i2c_irq(int cpuint, void *context, void *arg) if (priv->status == MPFS_I2C_IN_PROGRESS) { - priv->status = MPFS_I2C_FAILED; + priv->status = MPFS_I2C_FAILED_BUS_ERROR; } break; @@ -665,9 +766,17 @@ static int mpfs_i2c_transfer(struct i2c_master_s *dev, { struct mpfs_i2c_priv_s *priv = (struct mpfs_i2c_priv_s *)dev; int ret = OK; +#ifdef CONFIG_DEBUG_I2C_ERROR + int sval; + uint32_t status; +#endif i2cinfo("Starting transfer request of %d message(s):\n", count); - DEBUGASSERT(count > 0); + + if (count <= 0) + { + return -EINVAL; + } ret = nxmutex_lock(&priv->lock); if (ret < 0) @@ -675,6 +784,24 @@ static int mpfs_i2c_transfer(struct i2c_master_s *dev, return ret; } +#ifdef CONFIG_DEBUG_I2C_ERROR + /* We should never start at transfer with semaphore already signalled */ + + sem_getvalue(&priv->sem_isr, &sval); + if (sval != 0) + { + i2cerr("Already signalled at start? %d\n", sval); + } + + /* We should always be idle before transfer */ + + status = getreg32(MPFS_I2C_STATUS); + if (status != MPFS_I2C_ST_IDLE) + { + i2cerr("I2C bus not idle before transfer! Status: 0x%x\n", status); + } +#endif + priv->msgv = msgs; priv->msgc = count; @@ -709,9 +836,17 @@ static int mpfs_i2c_transfer(struct i2c_master_s *dev, if (msgs[i].flags & I2C_M_NOSTOP) { - /* Support only write + read combinations */ + /* Support only write + read combinations. No write + write, + * nor read + write without stop condition between supported + * yet. + */ - DEBUGASSERT(!(msgs[i].flags & I2C_M_READ)); + if (msgs[i].flags & I2C_M_READ) + { + i2cerr("No read before write supported!\n"); + nxmutex_unlock(&priv->lock); + return -EINVAL; + } /* Combine write + read transaction into one */ @@ -759,6 +894,20 @@ static int mpfs_i2c_transfer(struct i2c_master_s *dev, i2cinfo("Message %" PRIu8 " transfer complete.\n", priv->msgid); } +#ifdef CONFIG_DEBUG_I2C_ERROR + /* We should always be idle after the transfers */ + + status = getreg32(MPFS_I2C_STATUS); + if (status != MPFS_I2C_ST_IDLE) + { + i2cerr("I2C bus not idle after transfer! Status: 0x%x\n", status); + } +#endif + + /* Irq was enabled at mpfs_i2c_sendstart() */ + + up_disable_irq(priv->plic_irq); + nxmutex_unlock(&priv->lock); return ret; } @@ -782,26 +931,15 @@ static int mpfs_i2c_reset(struct i2c_master_s *dev) { struct mpfs_i2c_priv_s *priv = (struct mpfs_i2c_priv_s *)dev; int ret; - irqstate_t flags; - DEBUGASSERT(priv != NULL); - - flags = enter_critical_section(); - - /* Disabling I2C interrupts. - * NOTE: up_enable_irq() will be called at mpfs_i2c_sendstart() - */ - - up_disable_irq(priv->plic_irq); + nxmutex_lock(&priv->lock); - priv->inflight = false; - priv->status = MPFS_I2C_SUCCESS; - priv->initialized = false; + mpfs_i2c_deinit(priv); ret = mpfs_i2c_init(priv); if (ret != OK) { - leave_critical_section(flags); + nxmutex_unlock(&priv->lock); return ret; } @@ -809,8 +947,10 @@ static int mpfs_i2c_reset(struct i2c_master_s *dev) priv->tx_idx = 0; priv->rx_size = 0; priv->rx_idx = 0; + priv->inflight = false; + priv->status = MPFS_I2C_SUCCESS; - leave_critical_section(flags); + nxmutex_unlock(&priv->lock); return OK; } @@ -988,7 +1128,7 @@ struct i2c_master_s *mpfs_i2cbus_initialize(int port) nxmutex_unlock(&priv->lock); i2cinfo("Returning previously initialized I2C bus. " - "Handler: %" PRIxPTR "\n", (uintptr_t)priv); + "Handler: %p\n", priv); return (struct i2c_master_s *)priv; } @@ -1004,14 +1144,6 @@ struct i2c_master_s *mpfs_i2cbus_initialize(int port) priv->fpga = true; #endif - ret = irq_attach(priv->plic_irq, mpfs_i2c_irq, priv); - if (ret != OK) - { - priv->refs--; - nxmutex_unlock(&priv->lock); - return NULL; - } - ret = mpfs_i2c_init(priv); if (ret != OK) { @@ -1022,7 +1154,7 @@ struct i2c_master_s *mpfs_i2cbus_initialize(int port) nxmutex_unlock(&priv->lock); - i2cinfo("I2C bus initialized! Handler: %" PRIxPTR "\n", (uintptr_t)priv); + i2cinfo("I2C bus initialized! Handler: %p\n", priv); return (struct i2c_master_s *)priv; } diff --git a/arch/risc-v/src/mpfs/mpfs_ihc.c b/arch/risc-v/src/mpfs/mpfs_ihc.c index e1823b2ab5354..736571a6ee6c4 100644 --- a/arch/risc-v/src/mpfs/mpfs_ihc.c +++ b/arch/risc-v/src/mpfs/mpfs_ihc.c @@ -34,6 +34,7 @@ #include #include +#include #include #include #include @@ -80,7 +81,6 @@ /* rptun initialization names */ #define MPFS_RPTUN_CPU_NAME "mpfs-ihc" -#define MPFS_RPTUN_SHMEM_NAME "mpfs-shmem" /* Vring configuration parameters */ @@ -114,8 +114,6 @@ struct mpfs_rptun_shmem_s { volatile uintptr_t base; - volatile unsigned int seqs; - volatile unsigned int seqm; struct rptun_rsc_s rsc; bool master_up; }; @@ -127,11 +125,9 @@ struct mpfs_rptun_dev_s rptun_callback_t callback; void *arg; bool master; - unsigned int seq; struct mpfs_rptun_shmem_s *shmem; struct simple_addrenv_s addrenv[VRINGS]; char cpuname[RPMSG_NAME_SIZE + 1]; - char shmemname[RPMSG_NAME_SIZE + 1]; }; struct mpfs_queue_table_s @@ -150,9 +146,6 @@ struct mpfs_ihc_work_arg_s ****************************************************************************/ static const char *mpfs_rptun_get_cpuname(struct rptun_dev_s *dev); -static const char *mpfs_rptun_get_firmware(struct rptun_dev_s *dev); -static const struct rptun_addrenv_s -*mpfs_rptun_get_addrenv(struct rptun_dev_s *dev); static struct rptun_rsc_s *mpfs_rptun_get_resource(struct rptun_dev_s *dev); static bool mpfs_rptun_is_autostart(struct rptun_dev_s *dev); static bool mpfs_rptun_is_master(struct rptun_dev_s *dev); @@ -226,8 +219,6 @@ const uint32_t ihcia_remote_hart_ints[MPFS_NUM_HARTS] = static const struct rptun_ops_s g_mpfs_rptun_ops = { .get_cpuname = mpfs_rptun_get_cpuname, - .get_firmware = mpfs_rptun_get_firmware, - .get_addrenv = mpfs_rptun_get_addrenv, .get_resource = mpfs_rptun_get_resource, .is_autostart = mpfs_rptun_is_autostart, .is_master = mpfs_rptun_is_master, @@ -839,45 +830,6 @@ static const char *mpfs_rptun_get_cpuname(struct rptun_dev_s *dev) return priv->cpuname; } -/**************************************************************************** - * Name: mpfs_rptun_get_firmware - * - * Description: - * Gets the mpfs rptun firmware. - * - * Input Parameters: - * dev - Rptun device. - * - * Returned Value: - * Always null, no associated firmware present - * - ****************************************************************************/ - -static const char *mpfs_rptun_get_firmware(struct rptun_dev_s *dev) -{ - return NULL; -} - -/**************************************************************************** - * Name: mpfs_rptun_get_addrenv - * - * Description: - * Gets the mpfs rptun addrenv. - * - * Input Parameters: - * dev - Rptun device. - * - * Returned Value: - * Always null, no associated addrenv present. - * - ****************************************************************************/ - -static const struct rptun_addrenv_s * -mpfs_rptun_get_addrenv(struct rptun_dev_s *dev) -{ - return NULL; -} - /**************************************************************************** * Name: mpfs_rptun_get_resource * @@ -914,8 +866,6 @@ mpfs_rptun_get_resource(struct rptun_dev_s *dev) rsc = &priv->shmem->rsc; g_shmem.base = VRING_SHMEM; - g_shmem.seqm = 0; - g_shmem.seqs = 0; rsc->rsc_tbl_hdr.ver = 1; rsc->rsc_tbl_hdr.num = 1; @@ -1129,7 +1079,6 @@ static int mpfs_rptun_register_callback(struct rptun_dev_s *dev, * Initializes the rptun device. * * Input Parameters: - * shmemname - Shared mempory name * cpuname - Local CPU name * * Returned Value: @@ -1137,7 +1086,7 @@ static int mpfs_rptun_register_callback(struct rptun_dev_s *dev, * ****************************************************************************/ -static int mpfs_rptun_init(const char *shmemname, const char *cpuname) +static int mpfs_rptun_init(const char *cpuname) { struct mpfs_rptun_dev_s *dev; int ret; @@ -1156,7 +1105,6 @@ static int mpfs_rptun_init(const char *shmemname, const char *cpuname) dev->rptun.ops = &g_mpfs_rptun_ops; strlcpy(dev->cpuname, cpuname, sizeof(dev->cpuname)); - strlcpy(dev->shmemname, shmemname, sizeof(dev->shmemname)); list_add_tail(&g_dev_list, &dev->node); ret = rptun_initialize(&dev->rptun); @@ -1421,7 +1369,7 @@ int mpfs_ihc_init(void) g_shmem.rsc.rpmsg_vdev.status |= VIRTIO_CONFIG_STATUS_DRIVER_OK; } - ret = mpfs_rptun_init(MPFS_RPTUN_SHMEM_NAME, MPFS_RPTUN_CPU_NAME); + ret = mpfs_rptun_init(MPFS_RPTUN_CPU_NAME); if (ret < 0) { ihcerr("ERROR: Not able to init RPTUN\n"); @@ -1467,43 +1415,3 @@ int mpfs_ihc_init(void) up_disable_irq(g_plic_irq); return ret; } - -/**************************************************************************** - * Name: up_addrenv_va_to_pa - * - * Description: - * This is needed by openamp/libmetal/lib/system/nuttx/io.c:78. The - * physical memory is mapped as virtual. - * - * Input Parameters: - * va_ - * - * Returned Value: - * va - * - ****************************************************************************/ - -uintptr_t up_addrenv_va_to_pa(void *va) -{ - return (uintptr_t)va; -} - -/**************************************************************************** - * Name: up_addrenv_pa_to_va - * - * Description: - * This is needed by openamp/libmetal/lib/system/nuttx/io.c. The - * physical memory is mapped as virtual. - * - * Input Parameters: - * pa - * - * Returned Value: - * pa - * - ****************************************************************************/ - -void *up_addrenv_pa_to_va(uintptr_t pa) -{ - return (void *)pa; -} diff --git a/arch/risc-v/src/mpfs/mpfs_irq.c b/arch/risc-v/src/mpfs/mpfs_irq.c index a7550c5d7317d..5ee1a744ed8b6 100644 --- a/arch/risc-v/src/mpfs/mpfs_irq.c +++ b/arch/risc-v/src/mpfs/mpfs_irq.c @@ -50,6 +50,18 @@ void up_irqinitialize(void) up_irq_save(); + /* Complete possibly claimed IRQs in PLIC (for current hart) in case + * of warm reboot, e.g. after a crash in the middle of IRQ handler. + * This has no effect on non-claimed or disabled interrupts. + */ + + uintptr_t claim_address = mpfs_plic_get_claimbase(); + + for (int irq = MPFS_IRQ_EXT_START; irq < NR_IRQS; irq++) + { + putreg32(irq - MPFS_IRQ_EXT_START, claim_address); + } + /* Disable all global interrupts for current hart */ uintptr_t iebase = mpfs_plic_get_iebase(); @@ -61,12 +73,6 @@ void up_irqinitialize(void) putreg32(0x0, iebase + 16); putreg32(0x0, iebase + 20); - /* Clear pendings in PLIC (for current hart) */ - - uintptr_t claim_address = mpfs_plic_get_claimbase(); - uint32_t val = getreg32(claim_address); - putreg32(val, claim_address); - /* Colorize the interrupt stack for debug purposes */ #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 15 @@ -76,9 +82,7 @@ void up_irqinitialize(void) /* Set priority for all global interrupts to 1 (lowest) */ - int id; - - for (id = 1; id <= NR_IRQS; id++) + for (int id = 1; id <= NR_IRQS; id++) { putreg32(1, (uintptr_t)(MPFS_PLIC_PRIORITY + (4 * id))); } diff --git a/arch/risc-v/src/mpfs/mpfs_memorymap.h b/arch/risc-v/src/mpfs/mpfs_memorymap.h index 75aa5c0bd752a..b937b50c2b1fd 100644 --- a/arch/risc-v/src/mpfs/mpfs_memorymap.h +++ b/arch/risc-v/src/mpfs/mpfs_memorymap.h @@ -44,7 +44,7 @@ #define MPFS_IDLESTACK_BASE _ebss #endif -#define MPFS_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~15) +#define MPFS_IDLESTACK_SIZE SMP_STACK_SIZE #define MPFS_IDLESTACK0_TOP (MPFS_IDLESTACK_BASE + MPFS_IDLESTACK_SIZE) diff --git a/arch/risc-v/src/mpfs/mpfs_mpu.c b/arch/risc-v/src/mpfs/mpfs_mpu.c new file mode 100644 index 0000000000000..2adaf3d911c58 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_mpu.c @@ -0,0 +1,285 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_mpu.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#include "riscv_internal.h" +#include "mpfs_memorymap.h" + +#include "hardware/mpfs_mpucfg.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* MPUCFG entry is 64-bits */ + +#define MPFS_MPUCFG_WIDTH 64 + +/* Mode bits [63:56] */ + +#define MPFS_MPUCFG_MODE_SHIFT 56 +#define MPFS_MPUCFG_MODE_WIDTH 8 +#define MPFS_MPUCFG_MODE_MASK \ + (((1ul << MPFS_MPUCFG_MODE_WIDTH) - 1) << MPFS_MPUCFG_MODE_SHIFT) + +/* PMP entry bits [35:0] */ + +#define MPFS_MPUCFG_PMP_SHIFT 0 +#define MPFS_MPUCFG_PMP_WIDTH 36 +#define MPFS_MPUCFG_PMP_MASK \ + (((1ul << MPFS_MPUCFG_PMP_WIDTH) - 1) << MPFS_MPUCFG_PMP_SHIFT) + +/* Encode the MPUCFG register value */ + +#define MPFS_MPUCFG_ENCODE(mode, napot) \ + ((((mode) << MPFS_MPUCFG_MODE_SHIFT) & MPFS_MPUCFG_MODE_MASK) | \ + (((napot) << MPFS_MPUCFG_PMP_SHIFT) & MPFS_MPUCFG_PMP_MASK)) + +/* Decode the MPUCFG register value */ + +#define MPFS_MPUCFG_DECODE(reg, mode, napot) \ + do \ + { \ + uintptr_t val = getreg64(reg); \ + *(mode) = (val & MPFS_MPUCFG_MODE_MASK) >> MPFS_MPUCFG_MODE_SHIFT; \ + *(napot) = (val & MPFS_MPUCFG_PMP_MASK) >> MPFS_MPUCFG_PMP_SHIFT; \ + } \ + while(0) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: napot_decode + * + * Description: + * Decode base and size from NAPOT value + * + * Input Parameters: + * val - Value to decode. + * size - Size out. + * + * Returned Value: + * Base address. + * + ****************************************************************************/ + +static void napot_decode(uintptr_t val, uintptr_t *base, uintptr_t *size) +{ + uintptr_t mask = (uintptr_t)(-1) >> 1; + uintptr_t pot = MPFS_MPUCFG_WIDTH + 2; + + while (mask) + { + if ((val & mask) == mask) + { + break; + } + + pot--; + mask >>= 1; + } + + *size = UINT64_C(1) << pot; + *base = (val & ~mask) << 2; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mpfs_mpu_set + * + * Description: + * Set value to MPFS MPUCFG register. + * + * Input Parameters: + * reg - The MPUCFG register to write. + * perm - The region permissions. + * base - The base address of the region. + * size - The length of the region. + * + * Note: + * Only NAPOT encoded regions are supported, thus the base address and + * size must align with each other. + * + * Returned Value: + * 0 on success; negated error on failure. + * + ****************************************************************************/ + +int mpfs_mpu_set(uintptr_t reg, uintptr_t perm, uintptr_t base, + uintptr_t size) +{ + uintptr_t mode; + uintptr_t napot; + + /* Read the the permission and napot fields */ + + MPFS_MPUCFG_DECODE(reg, &mode, &napot); + + /* First, check that the register is not already configured */ + + if ((mode & PMPCFG_L) != 0) + { + /* The entry is locked, get out */ + + return -EACCES; + } + + /* Base must be word aligned, + * minimum size is 4K and it has to be power-of-two + */ + + if ((base & 0x07) != 0 || size < 0x1000 || (size & (size - 1)) != 0) + { + return -EINVAL; + } + + /* Make sure the base + size are NAPOT encodable */ + + if ((base & ((UINT64_C(1) << log2ceil(size)) - 1)) != 0) + { + /* The start address is not properly aligned with size */ + + return -EINVAL; + } + + /* Sanity check the register */ + + if (reg < MPFS_MPUCFG_BASE || reg >= MPFS_MPUCFG_END) + { + return -EINVAL; + } + + /* Calculate mode (RWX), only NAPOT encoding is supported */ + + mode = (perm & (PMPCFG_RWX_MASK | PMPCFG_L)) | PMPCFG_A_NAPOT; + + /* Do the NAPOT encoding */ + + napot = (base >> 2) | ((size - 1) >> 3); + + /* Then set the value */ + + putreg64(MPFS_MPUCFG_ENCODE(mode, napot), reg); + + return OK; +} + +/**************************************************************************** + * Name: mpfs_mpu_access_ok + * + * Description: + * Check if MPFS MPUCFG access is OK for register. + * + * Input Parameters: + * reg - The MPUCFG register to check. + * perm - The region permissions. + * base - The base address of the region. + * size - The length of the region. + * + * Returned Value: + * true if access OK; false if not. + * + ****************************************************************************/ + +bool mpfs_mpu_access_ok(uintptr_t reg, uintptr_t perm, uintptr_t base, + uintptr_t size) +{ + uintptr_t mode; + uintptr_t napot; + uintptr_t reg_base; + uintptr_t reg_size; + + /* Read the the permission and napot fields */ + + MPFS_MPUCFG_DECODE(reg, &mode, &napot); + + /* Check for permission match */ + + if ((mode & PMPCFG_RWX_MASK) != perm) + { + return false; + } + + /* Decode the napot field */ + + napot_decode(napot, ®_base, ®_size); + + /* Then check if the area fits */ + + return (base >= reg_base && (base + size) <= (reg_base + reg_size)); +} + +/**************************************************************************** + * Name: mpfs_mpu_lock + * + * Description: + * Lock an MPUCFG register from further modifications. + * + * Input Parameters: + * reg - The MPUCFG register to lock. + * + * Returned Value: + * 0 on success; negated error on failure. + * + ****************************************************************************/ + +int mpfs_mpu_lock(uintptr_t reg) +{ + uintptr_t mode; + uintptr_t napot; + + /* Sanity check the register */ + + if (reg < MPFS_MPUCFG_BASE || reg >= MPFS_MPUCFG_END) + { + return -EINVAL; + } + + MPFS_MPUCFG_DECODE(reg, &mode, &napot); + + /* If the entry is already locked, everything is fine */ + + if ((mode & PMPCFG_L) == 0) + { + /* Set the lock bit and write the value back */ + + putreg64(MPFS_MPUCFG_ENCODE(mode | PMPCFG_L, napot), reg); + } + + return OK; +} diff --git a/arch/risc-v/src/mpfs/mpfs_mpu.h b/arch/risc-v/src/mpfs/mpfs_mpu.h new file mode 100644 index 0000000000000..d934cd64044ef --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_mpu.h @@ -0,0 +1,95 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_mpu.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISC_V_SRC_MPFS_MPFS_MPU_H +#define __ARCH_RISC_V_SRC_MPFS_MPFS_MPU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: mpfs_mpu_set + * + * Description: + * Set value to MPFS MPUCFG register. + * + * Input Parameters: + * reg - The MPUCFG register to write. + * perm - The region permissions. + * base - The base address of the region. + * size - The length of the region. + * + * Note: + * Only NAPOT encoded regions are supported, thus the base address and + * size must align with each other. + * + * Returned Value: + * 0 on success; negated error on failure. + * + ****************************************************************************/ + +int mpfs_mpu_set(uintptr_t reg, uintptr_t perm, uintptr_t base, + uintptr_t size); + +/**************************************************************************** + * Name: mpfs_mpu_access_ok + * + * Description: + * Check if MPFS MPUCFG access is OK for register. + * + * Input Parameters: + * reg - The MPUCFG register to check. + * perm - The region permissions. + * base - The base address of the region. + * size - The length of the region. + * + * Returned Value: + * true if access OK; false if not. + * + ****************************************************************************/ + +bool mpfs_mpu_access_ok(uintptr_t reg, uintptr_t perm, uintptr_t base, + uintptr_t size); + +/**************************************************************************** + * Name: mpfs_mpu_lock + * + * Description: + * Lock an MPUCFG register from further modifications. + * + * Input Parameters: + * reg - The MPUCFG register to lock. + * + * Returned Value: + * 0 on success; negated error on failure. + * + ****************************************************************************/ + +int mpfs_mpu_lock(uintptr_t reg); + +#endif /* __ARCH_RISC_V_SRC_MPFS_MPFS_MPU_H */ diff --git a/arch/risc-v/src/mpfs/mpfs_opensbi.c b/arch/risc-v/src/mpfs/mpfs_opensbi.c index ad9e835c346c5..d0d277ba05f72 100644 --- a/arch/risc-v/src/mpfs/mpfs_opensbi.c +++ b/arch/risc-v/src/mpfs/mpfs_opensbi.c @@ -84,8 +84,8 @@ typedef struct sbi_scratch_holder_s sbi_scratch_holder_t; extern const uint8_t __mpfs_nuttx_start[]; extern const uint8_t __mpfs_nuttx_end[]; -extern const uint8_t _ssbi_ddr[]; -extern const uint8_t _esbi_ddr[]; +extern const uint8_t _ssbi_ram[]; +extern const uint8_t _esbi_ram[]; /**************************************************************************** * Private Function Prototypes @@ -479,9 +479,9 @@ static void mpfs_opensbi_scratch_setup(uint32_t hartid) * them so that OpenSBI has no chance override then. */ - g_scratches[hartid].scratch.fw_start = (unsigned long)_ssbi_ddr; - g_scratches[hartid].scratch.fw_size = (unsigned long)_esbi_ddr - - (unsigned long)_ssbi_ddr; + g_scratches[hartid].scratch.fw_start = (unsigned long)_ssbi_ram; + g_scratches[hartid].scratch.fw_size = (unsigned long)_esbi_ram - + (unsigned long)_ssbi_ram; g_scratches[hartid].scratch.fw_rw_offset = (unsigned long)g_scratches[hartid].scratch.fw_size; diff --git a/arch/risc-v/src/mpfs/mpfs_opensbi_utils.S b/arch/risc-v/src/mpfs/mpfs_opensbi_utils.S index db8f8fff7f738..f3b687c404ec7 100644 --- a/arch/risc-v/src/mpfs/mpfs_opensbi_utils.S +++ b/arch/risc-v/src/mpfs/mpfs_opensbi_utils.S @@ -74,7 +74,7 @@ mpfs_opensbi_prepare_hart: /* Setup OpenSBI exception handler */ la t0, mpfs_exception_opensbi - csrw mtvec, t0 + csrw CSR_MTVEC, t0 /* la gp, __global_pointer$ will not work. We want to have the gp as seen * in the .map file exactly. We need to restore gp in the trap handler. @@ -85,7 +85,7 @@ mpfs_opensbi_prepare_hart: /* Setup stacks per hart, the stack top is the end of the hart's scratch */ - csrr a0, mhartid + csrr a0, CSR_MHARTID li t1, SBI_SCRATCH_SIZE mul t0, a0, t1 la sp, g_scratches diff --git a/arch/risc-v/src/mpfs/mpfs_sdio.c b/arch/risc-v/src/mpfs/mpfs_sdio.c new file mode 100644 index 0000000000000..ae6f4a3d93217 --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_sdio.c @@ -0,0 +1,176 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_sdio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "mpfs_coremmc.h" +#include "mpfs_emmcsd.h" +#include "mpfs_sdio_dev.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sdio_initialize + * + * Description: + * Initialize SDIO for operation. + * + * Input Parameters: + * slotno - Not used. + * + * Returned Values: + * A reference to an SDIO interface structure. NULL is returned on + * failures. + * + ****************************************************************************/ + +struct sdio_dev_s *sdio_initialize(int slotno) +{ + switch (slotno) + { + case 0: +#ifdef CONFIG_MPFS_EMMCSD + return mpfs_emmcsd_sdio_initialize(slotno); +#endif + + case 1: +#ifdef CONFIG_MPFS_COREMMC + return mpfs_coremmc_sdio_initialize(slotno); +#endif + + default: + break; + } + + mcerr("sdio slot number %d not supported!\n", slotno); + return NULL; +} + +/**************************************************************************** + * Name: sdio_mediachange + * + * Description: + * Called by board-specific logic -- possible from an interrupt handler -- + * in order to signal to the driver that a card has been inserted or + * removed from the slot + * + * Input Parameters: + * dev - An instance of the SDIO driver device state structure. + * cardinslot - true is a card has been detected in the slot; false if a + * card has been removed from the slot. Only transitions + * (inserted->removed or removed->inserted should be reported) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot) +{ + struct mpfs_dev_s *priv = (struct mpfs_dev_s *)dev; + + if (!dev) + { + mcerr("sdio device not found\n"); + return; + } + + switch (priv->hw_base) + { +#ifdef CONFIG_MPFS_EMMCSD + case MPFS_EMMC_SD_BASE: + mpfs_emmcsd_sdio_mediachange(dev, cardinslot); + return; +#endif + +#ifdef CONFIG_MPFS_COREMMC + case CONFIG_MPFS_COREMMC_BASE: + mpfs_coremmc_sdio_mediachange(dev, cardinslot); + return; +#endif + + default: + break; + } + + mcerr("Invalid sdio base address\n"); +} + +/**************************************************************************** + * Name: sdio_wrprotect + * + * Description: + * Called by board-specific logic to report if the card in the slot is + * mechanically write protected. + * + * Input Parameters: + * dev - An instance of the SDIO driver device state structure. + * wrprotect - true is a card is writeprotected. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect) +{ + struct mpfs_dev_s *priv = (struct mpfs_dev_s *)dev; + + if (!dev) + { + mcerr("sdio device not found\n"); + return; + } + + switch (priv->hw_base) + { +#ifdef CONFIG_MPFS_EMMCSD + case MPFS_EMMC_SD_BASE: + mpfs_emmcsd_sdio_wrprotect(dev, wrprotect); + return; +#endif + +#ifdef CONFIG_MPFS_COREMMC + case CONFIG_MPFS_COREMMC_BASE: + mpfs_coremmc_sdio_wrprotect(dev, wrprotect); + return; +#endif + + default: + mcerr("Invalid sdio base address\n"); + break; + } +} diff --git a/arch/risc-v/src/mpfs/mpfs_sdio.h b/arch/risc-v/src/mpfs/mpfs_sdio.h new file mode 100644 index 0000000000000..ec63db76e7c3c --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_sdio.h @@ -0,0 +1,112 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_sdio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_MPFS_SDIO_H +#define __ARCH_RISCV_SRC_MPFS_MPFS_SDIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "chip.h" + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: sdio_initialize + * + * Description: + * Initialize SDIO for operation. + * + * Input Parameters: + * slotno - Not used. + * + * Returned Values: + * A reference to an SDIO interface structure. NULL is returned on + * failures. + * + ****************************************************************************/ + +struct sdio_dev_s; /* See include/nuttx/sdio.h */ +struct sdio_dev_s *sdio_initialize(int slotno); + +/**************************************************************************** + * Name: sdio_mediachange + * + * Description: + * Called by board-specific logic -- possibly from an interrupt handler -- + * in order to signal to the driver that a card has been inserted or + * removed from the slot. + * + * Input Parameters: + * dev - An instance of the SDIO driver device state structure. + * cardinslot - true is a card has been detected in the slot; false if a + * card has been removed from the slot. Only transitions + * (inserted->removed or removed->inserted should be reported) + * + * Returned Values: + * None + * + ****************************************************************************/ + +void sdio_mediachange(struct sdio_dev_s *dev, bool cardinslot); + +/**************************************************************************** + * Name: sdio_wrprotect + * + * Description: + * Called by board-specific logic to report if the card in the slot is + * mechanically write protected. + * + * Input Parameters: + * dev - An instance of the SDIO driver device state structure. + * wrprotect - true is a card is writeprotected. + * + * Returned Values: + * None + * + ****************************************************************************/ + +void sdio_wrprotect(struct sdio_dev_s *dev, bool wrprotect); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_MPFS_MPFS_SDIO_H */ diff --git a/arch/risc-v/src/mpfs/mpfs_sdio_dev.h b/arch/risc-v/src/mpfs/mpfs_sdio_dev.h new file mode 100644 index 0000000000000..688a6c462756d --- /dev/null +++ b/arch/risc-v/src/mpfs/mpfs_sdio_dev.h @@ -0,0 +1,92 @@ +/**************************************************************************** + * arch/risc-v/src/mpfs/mpfs_sdio_dev.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_MPFS_MPFS_SDIO_DEV_H +#define __ARCH_RISCV_SRC_MPFS_MPFS_SDIO_DEV_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* This structure defines the state of the MPFS eMMCSD interface */ + +struct mpfs_dev_s +{ + struct sdio_dev_s dev; /* Standard, base SDIO interface */ + + const uintptr_t hw_base; /* Base address */ + const int plic_irq; /* PLIC interrupt */ + bool clk_enabled; /* Clk state */ + + /* eMMC / SD and HW parameters */ + + const bool emmc; /* eMMC or SD */ + int bus_voltage; /* Bus voltage */ + int bus_mode; /* eMMC Bus mode */ + bool jumpers_3v3; /* Jumper settings: 1v8 or 3v3 */ + + /* Event support */ + + sem_t waitsem; /* Implements event waiting */ + sdio_eventset_t waitevents; /* Set of events to be waited for */ + uint32_t waitmask; /* Interrupt enables for event waiting */ + volatile sdio_eventset_t wkupevent; /* The event that caused the wakeup */ + struct wdog_s waitwdog; /* Watchdog that handles event timeouts */ + + /* Callback support */ + + sdio_statset_t cdstatus; /* Card status */ + sdio_eventset_t cbevents; /* Set of events to be cause callbacks */ + worker_t callback; /* Registered callback function */ + void *cbarg; /* Registered callback argument */ + struct work_s cbwork; /* Callback work queue structure */ + + /* Interrupt mode data transfer support */ + + uint32_t *buffer; /* Address of current R/W buffer */ + size_t remaining; /* Number of bytes remaining in the transfer */ + size_t receivecnt; /* Real count to receive */ + uint32_t xfrmask; /* Interrupt enables for data transfer */ + uint32_t xfr_blkmask; /* Interrupt enables for SB/MB data transfer */ + + bool widebus; /* Required for DMA support */ + bool onebit; /* true: Only 1-bit transfers are supported */ + + /* DMA data transfer support */ + + bool polltransfer; /* Indicate a poll transfer, no DMA */ + bool multiblock; /* Indicate a multi-block transfer */ + + /* Misc */ + + uint32_t blocksize; /* Current block size */ + uint32_t fifo_depth; /* Fifo size, read from the register */ +}; + +#endif /* __ARCH_RISCV_SRC_MPFS_MPFS_SDIO_DEV_H */ diff --git a/arch/risc-v/src/mpfs/mpfs_serial.c b/arch/risc-v/src/mpfs/mpfs_serial.c index ec9ab908cf712..ab262dc2a590a 100644 --- a/arch/risc-v/src/mpfs/mpfs_serial.c +++ b/arch/risc-v/src/mpfs/mpfs_serial.c @@ -1027,6 +1027,13 @@ static void up_send(struct uart_dev_s *dev, int ch) { struct up_dev_s *priv = (struct up_dev_s *)dev->priv; +#ifdef HAVE_SERIAL_CONSOLE + if (dev == &CONSOLE_DEV && !dev->isconsole) + { + return; + } +#endif + while ((up_serialin(priv, MPFS_UART_LSR_OFFSET) & UART_LSR_THRE) == 0); @@ -1198,6 +1205,12 @@ int up_putc(int ch) #ifdef HAVE_SERIAL_CONSOLE struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv; uint32_t ier; + + if (!CONSOLE_DEV.isconsole) + { + return ch; + } + up_disableuartint(priv, &ier); #endif diff --git a/arch/risc-v/src/mpfs/mpfs_shead.S b/arch/risc-v/src/mpfs/mpfs_shead.S index 9c124c4011a70..b73127f4373f8 100644 --- a/arch/risc-v/src/mpfs/mpfs_shead.S +++ b/arch/risc-v/src/mpfs/mpfs_shead.S @@ -63,19 +63,19 @@ __start: #endif /* Disable all interrupts in sie */ - csrw sie, zero - csrw sip, zero + csrw CSR_SIE, zero + csrw CSR_SIP, zero /* Set the S-mode trap vector */ la t0, __trap_vec - csrw stvec, t0 + csrw CSR_STVEC, t0 /* Clear sscratch */ - csrw sscratch, zero - csrw scause, zero - csrw sepc, zero + csrw CSR_SSCRATCH, zero + csrw CSR_SCAUSE, zero + csrw CSR_SEPC, zero /* initialize global pointer, global data */ @@ -86,7 +86,7 @@ __start: /* Remove MMU mappings (if any) and flush TLB */ - csrw satp, zero + csrw CSR_SATP, zero sfence.vma x0, x0 /* Make sure the writes to CSR stick before continuing */ diff --git a/arch/risc-v/src/mpfs/mpfs_start.c b/arch/risc-v/src/mpfs/mpfs_start.c index 52fd3162fd848..1b9282247212d 100644 --- a/arch/risc-v/src/mpfs/mpfs_start.c +++ b/arch/risc-v/src/mpfs/mpfs_start.c @@ -57,18 +57,6 @@ * Public Data ****************************************************************************/ -/* g_idle_topstack: _sbss is the start of the BSS region as defined by the - * linker script. _ebss lies at the end of the BSS region. The idle task - * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. - * The IDLE thread is the thread that the system boots on and, eventually, - * becomes the IDLE, do nothing task that runs only when there is nothing - * else to run. The heap continues from there until the end of memory. - * g_idle_topstack is a read-only variable the provides this computed - * address. - */ - -uintptr_t g_idle_topstack = MPFS_IDLESTACK_TOP; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -149,14 +137,14 @@ void __mpfs_start(uint64_t mhartid) mpfs_boardinitialize(); -#ifdef CONFIG_ARCH_USE_S_MODE +#ifdef CONFIG_RISCV_PERCPU_SCRATCH /* Initialize the per CPU areas */ if (mhartid != 0) { riscv_percpu_add_hart(mhartid); } -#endif /* CONFIG_ARCH_USE_S_MODE */ +#endif /* CONFIG_RISCV_PERCPU_SCRATCH */ /* Initialize the caches. Should only be executed from E51 (hart 0) to be * functional. Consider the caches already configured if running without diff --git a/arch/risc-v/src/mpfs/mpfs_usb.c b/arch/risc-v/src/mpfs/mpfs_usb.c index fec9deb8fd823..f30d5fc457753 100644 --- a/arch/risc-v/src/mpfs/mpfs_usb.c +++ b/arch/risc-v/src/mpfs/mpfs_usb.c @@ -3613,7 +3613,7 @@ static void mpfs_usb_iomux(void) #ifdef CONFIG_USBDEV_DMA /* DMA operations need to open the USB PMP registers for proper - * operation. If not configured, apply default settings. + * operation. */ uint64_t pmpcfg_usb_x; @@ -3622,28 +3622,24 @@ static void mpfs_usb_iomux(void) if ((pmpcfg_usb_x & 0x1ffffff000000000llu) != 0x1f00000000000000llu) { uerr("Please check the MPFS_PMPCFG_USB_0 register.\n"); - putreg64(0x1f00000fffffffffllu, MPFS_PMPCFG_USB_0); } pmpcfg_usb_x = getreg64(MPFS_PMPCFG_USB_1); if ((pmpcfg_usb_x & 0x1ffffff000000000llu) != 0x1f00000000000000llu) { uerr("Please check the MPFS_PMPCFG_USB_1 register.\n"); - putreg64(0x1f00000fffffffffllu, MPFS_PMPCFG_USB_1); } pmpcfg_usb_x = getreg64(MPFS_PMPCFG_USB_2); if ((pmpcfg_usb_x & 0x1ffffff000000000llu) != 0x1f00000000000000llu) { uerr("Please check the MPFS_PMPCFG_USB_2 register.\n"); - putreg64(0x1f00000fffffffffllu, MPFS_PMPCFG_USB_2); } pmpcfg_usb_x = getreg64(MPFS_PMPCFG_USB_3); if ((pmpcfg_usb_x & 0x1ffffff000000000llu) != 0x1f00000000000000llu) { uerr("Please check the MPFS_PMPCFG_USB_3 register.\n"); - putreg64(0x1f00000fffffffffllu, MPFS_PMPCFG_USB_3); } #endif } diff --git a/arch/risc-v/src/mpfs/mpfs_userspace.c b/arch/risc-v/src/mpfs/mpfs_userspace.c index a4409e2dcb088..de4d7e155b708 100644 --- a/arch/risc-v/src/mpfs/mpfs_userspace.c +++ b/arch/risc-v/src/mpfs/mpfs_userspace.c @@ -224,8 +224,8 @@ static void configure_mpu(void) { /* Open everything for PMP */ - WRITE_CSR(pmpaddr0, UINT64_C(~0)); - WRITE_CSR(pmpcfg0, (PMPCFG_A_NAPOT | PMPCFG_R | PMPCFG_W | PMPCFG_X)); + WRITE_CSR(CSR_PMPADDR0, UINT64_C(~0)); + WRITE_CSR(CSR_PMPCFG0, (PMPCFG_A_NAPOT | PMPCFG_R | PMPCFG_W | PMPCFG_X)); } /**************************************************************************** diff --git a/arch/risc-v/src/nuttsbi/CMakeLists.txt b/arch/risc-v/src/nuttsbi/CMakeLists.txt new file mode 100644 index 0000000000000..740cf8d1d573e --- /dev/null +++ b/arch/risc-v/src/nuttsbi/CMakeLists.txt @@ -0,0 +1,31 @@ +# ############################################################################## +# arch/risc-v/src/nuttsbi/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +if(CONFIG_NUTTSBI) + + set(SRCS sbi_head.S sbi_mtrap.S sbi_vectors.S sbi_start.c) + + list(APPEND SRCS sbi_mtimer.c sbi_mexception.c sbi_mcall.c sbi_mscratch.c) + + list(APPEND SRCS sbi_ipi.c) + + target_sources(arch PRIVATE ${SRCS}) + +endif() diff --git a/arch/risc-v/src/nuttsbi/Kconfig b/arch/risc-v/src/nuttsbi/Kconfig index 004ef2745a174..94ac9dd44a1dc 100644 --- a/arch/risc-v/src/nuttsbi/Kconfig +++ b/arch/risc-v/src/nuttsbi/Kconfig @@ -15,6 +15,12 @@ config NUTTSBI_HART_CNT int "Amount of harts in SoC" default 1 +config NUTTSBI_IPI_BASE + hex "MSWI base address" + default 0 + ---help--- + Sets the address of mtimecmp memory mapped register + config NUTTSBI_MTIME_BASE hex "MTIME base address" default 0 @@ -27,4 +33,8 @@ config NUTTSBI_MTIMECMP_BASE ---help--- Sets the address of mtimecmp memory mapped register +config NUTTSBI_LATE_INIT + bool "Target has sbi_late_init() implementation" + default n + endif diff --git a/arch/risc-v/src/nuttsbi/Make.defs b/arch/risc-v/src/nuttsbi/Make.defs index b580ca11a446e..7a17f583daf49 100644 --- a/arch/risc-v/src/nuttsbi/Make.defs +++ b/arch/risc-v/src/nuttsbi/Make.defs @@ -24,7 +24,7 @@ ifeq ($(CONFIG_NUTTSBI),y) SBI_ASRCS += sbi_mtrap.S sbi_vectors.S sbi_head.S SBI_CSRCS += sbi_mscratch.c sbi_mcall.c sbi_start.c -SBI_CSRCS += sbi_mexception.c sbi_mtimer.c +SBI_CSRCS += sbi_mexception.c sbi_mtimer.c sbi_ipi.c INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)nuttsbi diff --git a/arch/risc-v/src/nuttsbi/sbi_head.S b/arch/risc-v/src/nuttsbi/sbi_head.S index 745565d29a0d0..66e2d005ff96f 100644 --- a/arch/risc-v/src/nuttsbi/sbi_head.S +++ b/arch/risc-v/src/nuttsbi/sbi_head.S @@ -42,25 +42,25 @@ __start: /* Disable all interrupts (i.e. timer, external) in mie */ - csrw mie, zero - csrw mip, zero + csrw CSR_MIE, zero + csrw CSR_MIP, zero /* Initialize the Machine Trap Vector */ la t0, __mtrap_vec - csrw mtvec, t0 + csrw CSR_MTVEC, t0 /* Make sure that mtvec is updated before continuing */ 1: - csrr t1, mtvec + csrr t1, CSR_MTVEC bne t0, t1, 1b /* mscratch must be init to zero- we are not using scratch memory */ - csrw mscratch, zero - csrw mcause, zero - csrw mepc, zero + csrw CSR_MSCRATCH, zero + csrw CSR_MCAUSE, zero + csrw CSR_MEPC, zero li x1, 0 li x2, 0 li x3, 0 @@ -95,12 +95,12 @@ __start: /* Delegation registers must be explicitly reset */ - csrw mideleg, 0 - csrw medeleg, 0 + csrw CSR_MIDELEG, 0 + csrw CSR_MEDELEG, 0 /* Remove MMU mappings (if any) */ - csrw satp, zero + csrw CSR_SATP, zero fence /* Flush TLB (does not make a difference really) */ @@ -109,8 +109,8 @@ __start: /* Clear PMP */ - csrw pmpcfg0, 0 - csrw pmpcfg2, 0 + csrw CSR_PMPCFG0, zero + csrw CSR_PMPCFG2, zero /* Set up a temporary stack */ diff --git a/arch/risc-v/src/nuttsbi/sbi_internal.h b/arch/risc-v/src/nuttsbi/sbi_internal.h index 79e4690135ab6..2d4eda1107b81 100644 --- a/arch/risc-v/src/nuttsbi/sbi_internal.h +++ b/arch/risc-v/src/nuttsbi/sbi_internal.h @@ -43,7 +43,15 @@ #define MMODE_IRQSTACK (1024) -/* Timer interrupt is the only one we handle, others are discarded */ +/* IPI memory mapped registers */ + +#define IPI_IRQ (3) + +/* IPI memory mapped registers */ + +#define IPI_BASE (CONFIG_NUTTSBI_IPI_BASE) + +/* Timer interrupt */ #define MTIMER_IRQ (7) @@ -97,6 +105,20 @@ void sbi_mscratch_assign(uintptr_t hartid); void sbi_start(void) noreturn_function; +/**************************************************************************** + * Name: sbi_send_ipi + * + * Description: + * Send an inter-processor interrupt to all the harts defined + * + * Input Parameters: + * hmask - Mask fo CPU to send IPI + * hbase - The firset CPU id to send + * + ****************************************************************************/ + +void sbi_send_ipi(uintptr_t hmask, uintptr_t hbase); + /**************************************************************************** * Name: sbi_init_mtimer * @@ -140,5 +162,19 @@ uint64_t sbi_get_mtime(void); void sbi_set_mtimecmp(uint64_t value); +#ifdef CONFIG_NUTTSBI_LATE_INIT +/**************************************************************************** + * Name: sbi_late_initialize + * + * Description: + * Conduct any device specific initialization before entering S-mode from + * NUTTSBI as some chips need such preparations. This function still runs + * in M-mode. + * + ****************************************************************************/ + +void sbi_late_initialize(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __ARCH_RISC_V_SRC_NUTTSBI_SBI_INTERNAL_H */ diff --git a/arch/risc-v/src/nuttsbi/sbi_ipi.c b/arch/risc-v/src/nuttsbi/sbi_ipi.c new file mode 100644 index 0000000000000..0396d2a1f2eb6 --- /dev/null +++ b/arch/risc-v/src/nuttsbi/sbi_ipi.c @@ -0,0 +1,56 @@ +/**************************************************************************** + * arch/risc-v/src/nuttsbi/sbi_ipi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include + +#include + +#include "riscv_internal.h" + +#include "sbi_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void sbi_send_ipi(uintptr_t hmask, uintptr_t hbase) +{ + uintptr_t i; + + for (i = hbase; hmask; i++, hmask >>= 1) + { + if (hmask & 1) + { + putreg32(1, IPI_BASE + 4 * i); + } + } +} diff --git a/arch/risc-v/src/nuttsbi/sbi_mcall.c b/arch/risc-v/src/nuttsbi/sbi_mcall.c index 1f8596b3f5714..02f0eeb2a9c1d 100644 --- a/arch/risc-v/src/nuttsbi/sbi_mcall.c +++ b/arch/risc-v/src/nuttsbi/sbi_mcall.c @@ -51,9 +51,28 @@ void sbi_mcall_handle(uintptr_t *regs) { /* Check the environment call number */ - switch (regs[REG_A0]) + switch (regs[REG_A7]) { - case MCALL_GET_TIMER: + case SBI_EXT_IPI: + sbi_send_ipi(regs[REG_A0], regs[REG_A1]); + break; + case SBI_EXT_TIME: + switch (regs[REG_A6]) + { + case SBI_EXT_TIME_SET_TIMER: +#ifdef CONFIG_ARCH_RV64 + sbi_set_mtimecmp(regs[REG_A0]); +#else + sbi_set_mtimecmp(regs[REG_A0] + ((uint64_t)regs[REG_A1] << 32)); +#endif + CLEAR_CSR(CSR_MIP, MIP_STIP); + SET_CSR(CSR_MIE, MIE_MTIE); + break; + default: + break; + } + break; + case SBI_EXT_FIRMWARE: #ifdef CONFIG_ARCH_RV64 regs[REG_A0] = sbi_get_mtime(); #else @@ -65,16 +84,6 @@ void sbi_mcall_handle(uintptr_t *regs) #endif break; - case MCALL_SET_TIMER: -#ifdef CONFIG_ARCH_RV64 - sbi_set_mtimecmp(regs[REG_A1]); -#else - sbi_set_mtimecmp(regs[REG_A1] + ((uint64_t)regs[REG_A2] << 32)); -#endif - CLEAR_CSR(mip, MIP_STIP); - SET_CSR(mie, MIE_MTIE); - break; - default: break; } diff --git a/arch/risc-v/src/nuttsbi/sbi_mcall.h b/arch/risc-v/src/nuttsbi/sbi_mcall.h index 95154a2eacb71..f6412339473fe 100644 --- a/arch/risc-v/src/nuttsbi/sbi_mcall.h +++ b/arch/risc-v/src/nuttsbi/sbi_mcall.h @@ -30,105 +30,10 @@ #include /**************************************************************************** - * Public Types + * Pre-processor Definitions ****************************************************************************/ -enum mcall_num_e -{ - MCALL_INVALID, - MCALL_GET_TIMER, - MCALL_SET_TIMER, - MCALL_LAST -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: mcall0 - * - * Description: - * Generate an environment call to machine mode - * - * Input Parameters: - * nbr - Environment call number - * - ****************************************************************************/ - -static inline uintptr_t mcall0(unsigned int nbr) -{ - register long r0 asm("a0") = (long)(nbr); - - asm volatile - ( - "ecall" - :: "r"(r0) - : "memory" - ); - - asm volatile("nop" : "=r"(r0)); - - return r0; -} - -/**************************************************************************** - * Name: mcall1 - * - * Description: - * Generate an environment call to machine mode - * - * Input Parameters: - * nbr - Environment call number - * parm1 - Argument for ecall - * - ****************************************************************************/ - -static inline uintptr_t mcall1(unsigned int nbr, uintptr_t parm1) -{ - register long r0 asm("a0") = (long)(nbr); - register long r1 asm("a1") = (long)(parm1); - - asm volatile - ( - "ecall" - :: "r"(r0), "r"(r1) - : "memory" - ); - - asm volatile("nop" : "=r"(r0)); - - return r0; -} - -/**************************************************************************** - * Name: sbi_mcall_get_time - * - * Description: - * Read the current system time (mtime) - * - * Returned Value: - * time - Value of mtime - * - ****************************************************************************/ - -#define sbi_mcall_get_time() \ - mcall0(MCALL_GET_TIMER) - -/**************************************************************************** - * Name: sbi_mcall_set_timer - * - * Description: - * Set new compare match value for timer. Time is in absolute time, so - * user must either obtain system time and calculate the offset, or keep - * the old compare match value in memory - * - * Input Parameters: - * stime_value - Absolute time for next compare match event - * - ****************************************************************************/ - -#define sbi_mcall_set_timer(stime_value) \ - (void)mcall1(MCALL_SET_TIMER, stime_value) +#define SBI_EXT_FIRMWARE 0x0A000000 +#define SBI_EXT_FIRMWARE_GET_MTIME 0x0 #endif /* __ARCH_RISC_V_SRC_NUTTSBI_SBI_MCALL_H */ diff --git a/arch/risc-v/src/nuttsbi/sbi_mscratch.c b/arch/risc-v/src/nuttsbi/sbi_mscratch.c index 21913c21b8945..e1c48417c36c4 100644 --- a/arch/risc-v/src/nuttsbi/sbi_mscratch.c +++ b/arch/risc-v/src/nuttsbi/sbi_mscratch.c @@ -77,7 +77,7 @@ void sbi_mscratch_assign(uintptr_t hartid) stack_top = (uintptr_t)&g_mintstacktop; #endif - WRITE_CSR(mscratch, stack_top); + WRITE_CSR(CSR_MSCRATCH, stack_top); /* Make sure mscratch is updated before continuing */ diff --git a/arch/risc-v/src/nuttsbi/sbi_mtimer.c b/arch/risc-v/src/nuttsbi/sbi_mtimer.c index 4fae0db2b2e61..9534f791d56bf 100644 --- a/arch/risc-v/src/nuttsbi/sbi_mtimer.c +++ b/arch/risc-v/src/nuttsbi/sbi_mtimer.c @@ -66,7 +66,7 @@ void sbi_init_mtimer(uintptr_t mtime, uintptr_t mtimecmp) uint64_t sbi_get_mtime(void) { -#ifdef CONFIG_ARCH_RV64 +#if CONFIG_ARCH_RV_MMIO_BITS == 64 return getreg64(g_mtime); #else uint32_t hi; @@ -85,8 +85,9 @@ uint64_t sbi_get_mtime(void) void sbi_set_mtimecmp(uint64_t value) { - uintptr_t mtimecmp = g_mtimecmp + READ_CSR(mhartid) * sizeof(uintptr_t); -#ifdef CONFIG_ARCH_RV64 + uintptr_t mtimecmp = g_mtimecmp + + READ_CSR(CSR_MHARTID) * sizeof(uintptr_t); +#if CONFIG_ARCH_RV_MMIO_BITS == 64 putreg64(value, mtimecmp); #else putreg32(UINT32_MAX, mtimecmp + 4); diff --git a/arch/risc-v/src/nuttsbi/sbi_mtrap.S b/arch/risc-v/src/nuttsbi/sbi_mtrap.S index 52809cae0a018..2f2925433f1ed 100644 --- a/arch/risc-v/src/nuttsbi/sbi_mtrap.S +++ b/arch/risc-v/src/nuttsbi/sbi_mtrap.S @@ -51,15 +51,15 @@ machine_trap: /* Switch to M-mode IRQ stack */ - csrrw sp, mscratch, sp /* mscratch has user stack */ + csrrw sp, CSR_MSCRATCH, sp /* mscratch has user stack */ beqz sp, .Lmtrap /* Detect recursive traps */ addi sp, sp, -XCPTCONTEXT_SIZE save_ctx sp - csrr a0, mcause /* exception cause */ + csrr a0, CSR_MCAUSE /* exception cause */ - csrrw s0, mscratch, x0 /* read user stack */ + csrrw s0, CSR_MSCRATCH, x0 /* read user stack */ REGSTORE s0, REG_X2(sp) /* original SP */ /* Check if this is an exception */ @@ -70,20 +70,29 @@ machine_trap: sll a0, a0, 1 /* Shift msbit out */ li a1, MTIMER_IRQ * 2 /* Machine timer irq ? (shifted left) */ + beq a0, a1, 2f + li a1, IPI_IRQ * 2 /* Machine IPI irq ? (shifted left) */ bne a0, a1, 1f /* Delegate interrupt to S-mode handler */ + li a0, MIP_MSIP + csrc CSR_MIE, a0 + li a0, MIP_SSIP + csrs CSR_MIP, a0 + j 1f + +2: li a0, MIP_MTIP - csrc mie, a0 + csrc CSR_MIE, a0 li a0, MIP_STIP - csrs mip, a0 + csrs CSR_MIP, a0 1: /* Restore mscratch */ addi s0, sp, XCPTCONTEXT_SIZE - csrw mscratch, s0 /* original mscratch */ + csrw CSR_MSCRATCH, s0 /* original mscratch */ /* Restore original context */ @@ -107,17 +116,17 @@ machine_trap: mv a0, sp jal x1, sbi_mcall_handle - csrr a0, mepc + csrr a0, CSR_MEPC addi a0, a0, 4 - csrw mepc, a0 + csrw CSR_MEPC, a0 j 1b /* An unhandled trap to M-mode: this is an error and we cannot proceed */ .Lmtrap: - csrr a0, mcause /* Interrupt cause [arg0] */ - csrr a1, mepc /* Interrupt PC (instruction) [arg1] */ + csrr a0, CSR_MCAUSE /* Interrupt cause [arg0] */ + csrr a1, CSR_MEPC /* Interrupt PC (instruction) [arg1] */ jal x1, sbi_mexception j __start diff --git a/arch/risc-v/src/nuttsbi/sbi_start.c b/arch/risc-v/src/nuttsbi/sbi_start.c index b968302d03dd0..7bc9e0a530bc4 100644 --- a/arch/risc-v/src/nuttsbi/sbi_start.c +++ b/arch/risc-v/src/nuttsbi/sbi_start.c @@ -62,7 +62,7 @@ void sbi_start(void) /* Read hart ID */ - hartid = READ_CSR(mhartid); + hartid = READ_CSR(CSR_MHARTID); /* Set mscratch, mtimer */ @@ -71,7 +71,7 @@ void sbi_start(void) /* Setup system to enter S-mode */ - reg = READ_CSR(mstatus); + reg = READ_CSR(CSR_MSTATUS); reg &= ~MSTATUS_MPPM; /* Clear MPP */ reg &= ~MSTATUS_MPIE; /* Clear MPIE */ reg &= ~MSTATUS_TW; /* Do not trap WFI */ @@ -82,16 +82,16 @@ void sbi_start(void) /* Setup next context */ - WRITE_CSR(mstatus, reg); + WRITE_CSR(CSR_MSTATUS, reg); /* Setup a temporary S-mode interrupt vector */ - WRITE_CSR(stvec, __trap_vec_tmp); + WRITE_CSR(CSR_STVEC, __trap_vec_tmp); /* Delegate interrupts */ reg = (MIP_SSIP | MIP_STIP | MIP_SEIP); - WRITE_CSR(mideleg, reg); + WRITE_CSR(CSR_MIDELEG, reg); /* Delegate exceptions (all of them) */ @@ -100,21 +100,26 @@ void sbi_start(void) (1 << RISCV_IRQ_LOADPF) | (1 << RISCV_IRQ_STOREPF) | (1 << RISCV_IRQ_ECALLU)); - WRITE_CSR(medeleg, reg); + WRITE_CSR(CSR_MEDELEG, reg); /* Enable access to all counters for S- and U-mode */ - WRITE_CSR(mcounteren, UINT32_C(~0)); - WRITE_CSR(scounteren, UINT32_C(~0)); + WRITE_CSR(CSR_MCOUNTEREN, UINT32_C(~0)); + WRITE_CSR(CSR_SCOUNTEREN, UINT32_C(~0)); + +#ifdef CONFIG_NUTTSBI_LATE_INIT + /* Do device specific initialization as needed */ + + sbi_late_initialize(); +#endif /* Set program counter to __start_s */ - WRITE_CSR(mepc, __start_s); + WRITE_CSR(CSR_MEPC, __start_s); /* Open everything for PMP */ - WRITE_CSR(pmpaddr0, -1); - WRITE_CSR(pmpcfg0, (PMPCFG_A_NAPOT | PMPCFG_R | PMPCFG_W | PMPCFG_X)); + riscv_append_pmp_region(PMPCFG_A_NAPOT | PMPCFG_RWX_MASK, 0, -1); /* Then jump to the S-mode start function */ diff --git a/arch/risc-v/src/qemu-rv/CMakeLists.txt b/arch/risc-v/src/qemu-rv/CMakeLists.txt index b9c14e6413e38..d397f1b21464f 100644 --- a/arch/risc-v/src/qemu-rv/CMakeLists.txt +++ b/arch/risc-v/src/qemu-rv/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# arch/arm/src/qemu-rv/CMakeLists.txt +# arch/risc-v/src/qemu-rv/CMakeLists.txt # # Licensed to the Apache Software Foundation (ASF) under one or more contributor # license agreements. See the NOTICE file distributed with this work for @@ -30,7 +30,7 @@ list( qemu_rv_allocateheap.c) if(CONFIG_BUILD_KERNEL) - list(APPEND SRCS qemu_rv_mm_init.c qemu_rv_exception_m.S) + list(APPEND SRCS qemu_rv_mm_init.c) endif() if(CONFIG_MM_PGALLOC) diff --git a/arch/risc-v/src/qemu-rv/Kconfig b/arch/risc-v/src/qemu-rv/Kconfig index 00ce77171c691..5d5b8b2dd41ec 100644 --- a/arch/risc-v/src/qemu-rv/Kconfig +++ b/arch/risc-v/src/qemu-rv/Kconfig @@ -35,4 +35,9 @@ config ARCH_CHIP_QEMU_RV_ISA_C default n select ARCH_RV_ISA_C +config ARCH_CHIP_QEMU_RV_ISA_V + bool "Standard Extension for Vector Instructions" + default n + select ARCH_RV_ISA_V + endif diff --git a/arch/risc-v/src/qemu-rv/Make.defs b/arch/risc-v/src/qemu-rv/Make.defs index 3c5982a8b0a33..3033111cc38a0 100644 --- a/arch/risc-v/src/qemu-rv/Make.defs +++ b/arch/risc-v/src/qemu-rv/Make.defs @@ -30,7 +30,6 @@ CHIP_CSRCS += qemu_rv_timerisr.c qemu_rv_allocateheap.c ifeq ($(CONFIG_BUILD_KERNEL),y) CHIP_CSRCS += qemu_rv_mm_init.c -CMN_ASRCS += qemu_rv_exception_m.S endif ifeq ($(CONFIG_MM_PGALLOC),y) diff --git a/arch/risc-v/src/qemu-rv/hardware/qemu_rv_memorymap.h b/arch/risc-v/src/qemu-rv/hardware/qemu_rv_memorymap.h index 868f3d698a9db..ce821fe32cbf4 100644 --- a/arch/risc-v/src/qemu-rv/hardware/qemu_rv_memorymap.h +++ b/arch/risc-v/src/qemu-rv/hardware/qemu_rv_memorymap.h @@ -31,4 +31,6 @@ #define QEMU_RV_ACLINT_BASE 0x02f00000 #define QEMU_RV_PLIC_BASE 0x0c000000 +#define QEMU_RV_RESET_BASE 0x100000 + #endif /* __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_MEMORYMAP_H */ diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_exception_m.S b/arch/risc-v/src/qemu-rv/qemu_rv_exception_m.S deleted file mode 100644 index 3d6a0fcc75ac5..0000000000000 --- a/arch/risc-v/src/qemu-rv/qemu_rv_exception_m.S +++ /dev/null @@ -1,105 +0,0 @@ -/**************************************************************************** - * arch/risc-v/src/qemu-rv/qemu_rv_exception_m.S - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#include "chip.h" - -#include "riscv_macros.S" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Provide a default section for the exeception handler. */ - -#ifndef EXCEPTION_SECTION -# define EXCEPTION_SECTION .text -#endif - -/**************************************************************************** - * Public Symbols - ****************************************************************************/ - -.section .text -.balign 8 -.global __trap_vec_m - -/**************************************************************************** - * Name: __trap_vec_m - * - * Description: - * All M-mode exceptions and interrupts will be handled from here. If - * kernel is in S-mode delegated exceptions and interrupts are handled. - * - ****************************************************************************/ - -__trap_vec_m: - j exception_m - -/**************************************************************************** - * Name: exception_m - * - * Description: - * Handles interrupts for m-mode - * - ****************************************************************************/ - -.section EXCEPTION_SECTION -.global exception_m -.align 8 - -exception_m: - - /* Swap mscratch with sp */ - /* NOTE: mscratch has been set in up_mtimer_initialize() */ - - csrrw sp, mscratch, sp - - /* Save the context */ - - save_ctx sp - - /* Handle the mtimer interrupt */ - /* NOTE: we assume exception/interrupt only happens for mtimer */ - - jal ra, qemu_rv_mtimer_interrupt - - /* Restore the context */ - - load_ctx sp - - /* Swap mscratch with sp */ - - csrrw sp, mscratch, sp - - /* Return from exception */ - - mret diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_head.S b/arch/risc-v/src/qemu-rv/qemu_rv_head.S index 9e321bb62a6f0..9be1ed225ffe8 100644 --- a/arch/risc-v/src/qemu-rv/qemu_rv_head.S +++ b/arch/risc-v/src/qemu-rv/qemu_rv_head.S @@ -29,6 +29,7 @@ #include "chip.h" #include "riscv_internal.h" +#include "riscv_macros.S" /**************************************************************************** * Public Symbols @@ -44,65 +45,29 @@ __start: /* Preserve a1 as it contains the pointer to DTB */ /* Load mhartid (cpuid) */ - csrr a0, mhartid - - /* Set stack pointer to the idle thread stack */ - - bnez a0, 1f - la sp, QEMU_RV_IDLESTACK_TOP - j 2f -1: +#ifndef CONFIG_BUILD_KERNEL + csrr a0, CSR_MHARTID +#endif /* Load the number of CPUs that the kernel supports */ - -#ifdef CONFIG_SMP li t1, CONFIG_SMP_NCPUS -#else - li t1, 1 -#endif /* If a0 (mhartid) >= t1 (the number of CPUs), stop here */ - blt a0, t1, 3f - csrw mie, zero + blt a0, t1, 2f + csrw CSR_IE, zero wfi -3: - /* To get g_cpu_basestack[mhartid], must get g_cpu_basestack first */ - - la t0, g_cpu_basestack - - /* Offset = pointer width * hart id */ - -#ifdef CONFIG_ARCH_RV32 - slli t1, a0, 2 -#else - slli t1, a0, 3 -#endif - add t0, t0, t1 - - /* Load idle stack base to sp */ - - REGLOAD sp, 0(t0) - - /* - * sp (stack top) = sp + idle stack size - XCPTCONTEXT_SIZE - * - * Note: Reserve some space used by up_initial_state since we are already - * running and using the per CPU idle stack. - */ - - li t0, STACK_ALIGN_UP(CONFIG_IDLETHREAD_STACKSIZE - XCPTCONTEXT_SIZE) - add sp, sp, t0 - 2: + /* Set stack pointer to the idle thread stack */ + riscv_set_inital_sp QEMU_RV_IDLESTACK_BASE, SMP_STACK_SIZE, a0 /* Disable all interrupts (i.e. timer, external) in mie */ - csrw mie, zero + csrw CSR_IE, zero la t0, __trap_vec - csrw mtvec, t0 + csrw CSR_TVEC, t0 /* Jump to qemu_rv_start */ diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_irq.c b/arch/risc-v/src/qemu-rv/qemu_rv_irq.c index 5c0badb1f7563..202cedab444eb 100644 --- a/arch/risc-v/src/qemu-rv/qemu_rv_irq.c +++ b/arch/risc-v/src/qemu-rv/qemu_rv_irq.c @@ -33,6 +33,7 @@ #include #include "riscv_internal.h" +#include "riscv_ipi.h" #include "chip.h" /**************************************************************************** @@ -79,9 +80,9 @@ void up_irqinitialize(void) riscv_exception_attach(); #ifdef CONFIG_SMP - /* Clear RISCV_IPI for CPU0 */ + /* Clear IPI for CPU0 */ - putreg32(0, RISCV_IPI); + riscv_ipi_clear(0); up_enable_irq(RISCV_IRQ_SOFT); #endif @@ -160,14 +161,6 @@ void up_enable_irq(int irq) SET_CSR(CSR_IE, IE_TIE); } -#ifdef CONFIG_BUILD_KERNEL - else if (irq == RISCV_IRQ_MTIMER) - { - /* Read m/sstatus & set timer interrupt enable in m/sie */ - - SET_CSR(mie, MIE_MTIE); - } -#endif else if (irq > RISCV_IRQ_EXT) { extirq = irq - RISCV_IRQ_EXT; diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_memorymap.h b/arch/risc-v/src/qemu-rv/qemu_rv_memorymap.h index 9be4569ab6865..c8deb5dd22605 100644 --- a/arch/risc-v/src/qemu-rv/qemu_rv_memorymap.h +++ b/arch/risc-v/src/qemu-rv/qemu_rv_memorymap.h @@ -39,7 +39,12 @@ #define QEMU_RV_IDLESTACK_BASE _ebss #endif -#define QEMU_RV_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3) -#define QEMU_RV_IDLESTACK_TOP (QEMU_RV_IDLESTACK_BASE + QEMU_RV_IDLESTACK_SIZE) +#ifndef CONFIG_BUILD_KERNEL +/* QEMU reset chocies */ + +#define QEMU_RV_RESET_DONE 0x5555 +#define QEMU_RV_RESET_FAIL 0x3333 +#define QEMU_RV_RESET_REBOOT 0x7777 +#endif #endif /* __ARCH_RISCV_SRC_QEMU_RV_QEMU_RV_MEMORYMAP_H */ diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_start.c b/arch/risc-v/src/qemu-rv/qemu_rv_start.c index e3465bcac53a2..c9d9bf736bb8c 100644 --- a/arch/risc-v/src/qemu-rv/qemu_rv_start.c +++ b/arch/risc-v/src/qemu-rv/qemu_rv_start.c @@ -59,16 +59,14 @@ ****************************************************************************/ #ifdef CONFIG_BUILD_KERNEL -extern void __trap_vec(void); -extern void __trap_vec_m(void); -extern void up_mtimer_initialize(void); +extern void __start(void); #endif /**************************************************************************** * Name: qemu_rv_clear_bss ****************************************************************************/ -void qemu_rv_clear_bss(void) +static void qemu_rv_clear_bss(void) { uint32_t *dest; @@ -82,15 +80,34 @@ void qemu_rv_clear_bss(void) } } +#ifdef CONFIG_BUILD_KERNEL +static void qemu_boot_secondary(int mhartid, uintptr_t dtb) +{ + int i; + + for (i = 0; i < CONFIG_SMP_NCPUS; i++) + { + if (i == mhartid) + { + continue; + } + + riscv_sbi_boot_secondary(i, (uintptr_t)&__start, dtb); + } +} +#endif + /**************************************************************************** - * Public Data + * Private Data ****************************************************************************/ -/* NOTE: g_idle_topstack needs to point the top of the idle stack - * for CPU0 and this value is used in up_initial_state() - */ +#ifdef CONFIG_BUILD_KERNEL +static bool boot_secondary = false; +#endif -uintptr_t g_idle_topstack = QEMU_RV_IDLESTACK_TOP; +/**************************************************************************** + * Public Data + ****************************************************************************/ /**************************************************************************** * Public Functions @@ -100,12 +117,18 @@ uintptr_t g_idle_topstack = QEMU_RV_IDLESTACK_TOP; * Name: qemu_rv_start ****************************************************************************/ -#ifdef CONFIG_BUILD_KERNEL -void qemu_rv_start_s(int mhartid, const char *dtb) -#else void qemu_rv_start(int mhartid, const char *dtb) -#endif { +#ifdef CONFIG_BUILD_KERNEL + /* Boot other cores */ + + if (!boot_secondary) + { + boot_secondary = true; + qemu_boot_secondary(mhartid, (uintptr_t)dtb); + } +#endif + /* Configure FPU */ riscv_fpuconfig(); @@ -115,8 +138,10 @@ void qemu_rv_start(int mhartid, const char *dtb) goto cpux; } -#ifndef CONFIG_BUILD_KERNEL qemu_rv_clear_bss(); + +#ifdef CONFIG_RISCV_PERCPU_SCRATCH + riscv_percpu_add_hart(mhartid); #endif #ifdef CONFIG_DEVICE_TREE @@ -157,77 +182,6 @@ void qemu_rv_start(int mhartid, const char *dtb) } } -#ifdef CONFIG_BUILD_KERNEL - -/**************************************************************************** - * Name: qemu_rv_start - ****************************************************************************/ - -void qemu_rv_start(int mhartid, const char *dtb) -{ - /* NOTE: still in M-mode */ - - if (0 == mhartid) - { - qemu_rv_clear_bss(); - - /* Initialize the per CPU areas */ - - riscv_percpu_add_hart(mhartid); - } - - /* Disable MMU and enable PMP */ - - WRITE_CSR(satp, 0x0); - WRITE_CSR(pmpaddr0, 0x3fffffffffffffull); - WRITE_CSR(pmpcfg0, 0xf); - - /* Set exception and interrupt delegation for S-mode */ - - WRITE_CSR(medeleg, 0xffff); - WRITE_CSR(mideleg, 0xffff); - - /* Allow to write satp from S-mode */ - - CLEAR_CSR(mstatus, MSTATUS_TVM); - - /* Set mstatus to S-mode and enable SUM */ - - CLEAR_CSR(mstatus, ~MSTATUS_MPP_MASK); - SET_CSR(mstatus, MSTATUS_MPPS | SSTATUS_SUM); - - /* Set the trap vector for S-mode */ - - WRITE_CSR(stvec, (uintptr_t)__trap_vec); - - /* Set the trap vector for M-mode */ - - WRITE_CSR(mtvec, (uintptr_t)__trap_vec_m); - - if (0 == mhartid) - { - /* Only the primary CPU needs to initialize mtimer - * before entering to S-mode - */ - - up_mtimer_initialize(); - } - - /* Set mepc to the entry */ - - WRITE_CSR(mepc, (uintptr_t)qemu_rv_start_s); - - /* Set a0 to mhartid and a1 to dtb explicitly and enter to S-mode */ - - asm volatile ( - "mv a0, %0 \n" - "mv a1, %1 \n" - "mret \n" - :: "r" (mhartid), "r" (dtb) - ); -} -#endif - void riscv_earlyserialinit(void) { u16550_earlyserialinit(); diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_timerisr.c b/arch/risc-v/src/qemu-rv/qemu_rv_timerisr.c index 92363ee7bad95..ad6769f5a6313 100644 --- a/arch/risc-v/src/qemu-rv/qemu_rv_timerisr.c +++ b/arch/risc-v/src/qemu-rv/qemu_rv_timerisr.c @@ -49,75 +49,6 @@ #define MTIMER_FREQ 10000000 #define TICK_COUNT (10000000 / TICK_PER_SEC) -#ifdef CONFIG_BUILD_KERNEL - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static uint32_t g_mtimer_cnt = 0; -static uint32_t g_stimer_pending = false; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: qemu_rv_ssoft_interrupt - * - * Description: - * This function is S-mode software interrupt handler to proceed - * the OS timer - * - ****************************************************************************/ - -static int qemu_rv_ssoft_interrupt(int irq, void *context, void *arg) -{ - /* Cleaer Supervisor Software Interrupt */ - - CLEAR_CSR(sip, SIP_SSIP); - - if (g_stimer_pending) - { - g_stimer_pending = false; - - /* Proceed the OS timer */ - - nxsched_process_timer(); - } -#ifdef CONFIG_SMP - else - { - /* We assume IPI has been issued */ - - riscv_pause_handler(irq, context, arg); - } -#endif - - return 0; -} - -/**************************************************************************** - * Name: qemu_rv_reload_mtimecmp - * - * Description: - * This function is called during start-up to initialize mtimecmp - * for CONFIG_BUILD_KERNEL=y - * - ****************************************************************************/ - -static void qemu_rv_reload_mtimecmp(void) -{ - uint64_t current; - uint64_t next; - - current = READ_CSR(time); - next = current + TICK_COUNT; - putreg64(next, QEMU_RV_CLINT_MTIMECMP); -} - -#endif /* CONFIG_BUILD_KERNEL */ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -133,78 +64,11 @@ static void qemu_rv_reload_mtimecmp(void) void up_timer_initialize(void) { -#ifndef CONFIG_BUILD_KERNEL struct oneshot_lowerhalf_s *lower = riscv_mtimer_initialize( QEMU_RV_CLINT_MTIME, QEMU_RV_CLINT_MTIMECMP, - RISCV_IRQ_MTIMER, MTIMER_FREQ); + RISCV_IRQ_TIMER, MTIMER_FREQ); DEBUGASSERT(lower); up_alarm_set_lowerhalf(lower); -#else - /* NOTE: This function is called in S-mode */ - - irq_attach(RISCV_IRQ_SSOFT, qemu_rv_ssoft_interrupt, NULL); - up_enable_irq(RISCV_IRQ_SSOFT); -#endif -} - -#ifdef CONFIG_BUILD_KERNEL - -/**************************************************************************** - * Name: up_mtimer_initialize - * - * Description: - * This function is called during start-up to initialize the M-mode timer - * - ****************************************************************************/ - -void up_mtimer_initialize(void) -{ - uintptr_t irqstacktop = riscv_percpu_get_irqstack(); - - /* Set the irq stack base to mscratch */ - - WRITE_CSR(mscratch, - irqstacktop - STACK_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK)); - - /* NOTE: we do not attach a handler for mtimer, - * because it is handled in the exception_m directly - */ - - up_enable_irq(RISCV_IRQ_MTIMER); - qemu_rv_reload_mtimecmp(); -} - -/**************************************************************************** - * Name: qemu_rv_mtimer_interrupt - * - * Description: - * In RISC-V with S-mode, M-mode timer must be handled in M-mode - * This function is called from exception_m in M-mode directly - * - ****************************************************************************/ - -void qemu_rv_mtimer_interrupt(void) -{ - uint64_t current; - uint64_t next; - - /* Update mtimercmp */ - - current = getreg64(QEMU_RV_CLINT_MTIMECMP); - next = current + TICK_COUNT; - putreg64(next, QEMU_RV_CLINT_MTIMECMP); - - g_mtimer_cnt++; - g_stimer_pending = true; - - if (OSINIT_HW_READY()) - { - /* Post Supervisor Software Interrupt */ - - SET_CSR(sip, SIP_SSIP); - } } - -#endif /* CONFIG_BUILD_KERNEL */ diff --git a/arch/risc-v/src/rv32m1/rv32m1_gpio.c b/arch/risc-v/src/rv32m1/rv32m1_gpio.c index 2b5d4ba18a256..bdfa832325c98 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_gpio.c +++ b/arch/risc-v/src/rv32m1/rv32m1_gpio.c @@ -32,6 +32,7 @@ #include #include +#include #include #include diff --git a/arch/risc-v/src/rv32m1/rv32m1_head.S b/arch/risc-v/src/rv32m1/rv32m1_head.S index 8853d23c017d7..879936103e89d 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_head.S +++ b/arch/risc-v/src/rv32m1/rv32m1_head.S @@ -47,14 +47,14 @@ __start: /* Disable all interrupts (i.e. timer, external) in mie */ - csrci mstatus, 0x8 - csrw mie, zero + csrci CSR_MSTATUS, 0x8 + csrw CSR_MIE, zero /* Initialize the Machine Trap Vector */ lui t0, %hi(_svector) addi t0, t0, %lo(_svector) - csrw mtvec, t0 + csrw CSR_MTVEC, t0 /* Jump to __rv32m1_start */ @@ -130,7 +130,7 @@ exception_common: sw x30, 38*4(sp) #endif - csrr s0, mstatus + csrr s0, CSR_MSTATUS sw s0, 32*4(sp) /* mstatus */ addi s0, sp, XCPTCONTEXT_SIZE @@ -138,8 +138,8 @@ exception_common: /* Setup arg0(exception cause), arg1(context) */ - csrr a0, mcause /* exception cause */ - csrr s0, mepc + csrr a0, CSR_MCAUSE /* exception cause */ + csrr s0, CSR_MEPC sw s0, 0(sp) /* exception PC */ mv a1, sp /* context = sp */ @@ -159,10 +159,10 @@ exception_common: mv sp, a0 lw s0, 0(sp) /* restore mepc */ - csrw mepc, s0 + csrw CSR_MEPC, s0 lw s0, 32*4(sp) /* restore mstatus */ - csrw mstatus, s0 + csrw CSR_MSTATUS, s0 #if defined(INT_XCPT_REGS) && INT_XCPT_REGS >= 39 lw x28, 36*4(sp) diff --git a/arch/risc-v/src/rv32m1/rv32m1_irq.c b/arch/risc-v/src/rv32m1/rv32m1_irq.c index 3f21f49721237..ead570961f8e6 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_irq.c +++ b/arch/risc-v/src/rv32m1/rv32m1_irq.c @@ -237,11 +237,11 @@ irqstate_t up_irq_enable(void) /* TODO: should move to up_enable_irq() */ - SET_CSR(mie, MIE_MEIE); + SET_CSR(CSR_MIE, MIE_MEIE); #endif /* Read mstatus & set machine interrupt enable (MIE) in mstatus */ - oldstat = READ_AND_SET_CSR(mstatus, MSTATUS_MIE); + oldstat = READ_AND_SET_CSR(CSR_MSTATUS, MSTATUS_MIE); return oldstat; } diff --git a/arch/risc-v/src/rv32m1/rv32m1_memorymap.h b/arch/risc-v/src/rv32m1/rv32m1_memorymap.h index 28e2b6d89ba6a..1f8612e3340e3 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_memorymap.h +++ b/arch/risc-v/src/rv32m1/rv32m1_memorymap.h @@ -25,6 +25,8 @@ * Included Files ****************************************************************************/ +#include "riscv_internal.h" + #include "hardware/rv32m1_memorymap.h" /**************************************************************************** @@ -39,7 +41,7 @@ #define RV32M1_IDLESTACK_BASE _ebss #endif -#define RV32M1_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3) +#define RV32M1_IDLESTACK_SIZE SMP_STACK_SIZE #define RV32M1_IDLESTACK_TOP (RV32M1_IDLESTACK_BASE + RV32M1_IDLESTACK_SIZE) #endif /* __ARCH_RISCV_SRC_RV32M1_RV32M1_MEMORYMAP_H */ diff --git a/arch/risc-v/src/rv32m1/rv32m1_serial.c b/arch/risc-v/src/rv32m1/rv32m1_serial.c index cbc2a1be36d44..093f3eccc73ff 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_serial.c +++ b/arch/risc-v/src/rv32m1/rv32m1_serial.c @@ -343,11 +343,11 @@ static void up_putreg(struct up_dev_s *priv, int offset, uint32_t value) static void up_restoreuartint(struct up_dev_s *priv, uint32_t im) { - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(NULL); up_putreg(priv, RV32M1_LPUART_CTRL_OFFSET, im); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -356,7 +356,7 @@ static void up_restoreuartint(struct up_dev_s *priv, uint32_t im) static void up_disableuartint(struct up_dev_s *priv, uint32_t *im) { - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(NULL); uint32_t regval = up_getreg(priv, RV32M1_LPUART_CTRL_OFFSET); /* Return the current interrupt mask value */ @@ -371,7 +371,7 @@ static void up_disableuartint(struct up_dev_s *priv, uint32_t *im) regval &= ~(LPUART_CTRL_TCIE | LPUART_CTRL_TIE | LPUART_CTRL_RIE); up_putreg(priv, RV32M1_LPUART_CTRL_OFFSET, regval); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/risc-v/src/rv32m1/rv32m1_start.c b/arch/risc-v/src/rv32m1/rv32m1_start.c index 895290e247077..c6ae0926d5279 100644 --- a/arch/risc-v/src/rv32m1/rv32m1_start.c +++ b/arch/risc-v/src/rv32m1/rv32m1_start.c @@ -50,18 +50,6 @@ * Public Data ****************************************************************************/ -/* g_idle_topstack: _sbss is the start of the BSS region as defined by the - * linker script. _ebss lies at the end of the BSS region. The idle task - * stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. - * The IDLE thread is the thread that the system boots on and, eventually, - * becomes the IDLE, do nothing task that runs only when there is nothing - * else to run. The heap continues from there until the end of memory. - * g_idle_topstack is a read-only variable the provides this computed - * address. - */ - -uintptr_t g_idle_topstack = RV32M1_IDLESTACK_TOP; - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/arch/sim/Kconfig b/arch/sim/Kconfig index ed410099dbbad..a3099ab9c46f2 100644 --- a/arch/sim/Kconfig +++ b/arch/sim/Kconfig @@ -15,18 +15,22 @@ config HOST_X86_64 select ARCH_HAVE_STACKCHECK select LIBC_ARCH_ELF_64BIT if LIBC_ARCH_ELF && !SIM_M32 select ARCH_HAVE_MATH_H + select ARCH_TOOLCHAIN_GNU config HOST_X86 bool "x86" select ARCH_HAVE_STACKCHECK + select ARCH_TOOLCHAIN_GNU config HOST_ARM bool "arm" select ARCH_HAVE_STACKCHECK + select ARCH_TOOLCHAIN_GNU config HOST_ARM64 bool "arm64" select ARCH_HAVE_STACKCHECK + select ARCH_TOOLCHAIN_GNU endchoice # Host CPU Type @@ -327,6 +331,30 @@ config SIM_CAMERA_DEV_PATH endif +menu "Simulated v4l2m2m support" + +config SIM_VIDEO_DECODER + bool "Video decoder support on sim" + depends on VIDEO + default n + +config SIM_VIDEO_DECODER_DEV_PATH + string "Video decoder device path" + depends on SIM_VIDEO_DECODER + default "/dev/video1" + +config SIM_VIDEO_ENCODER + bool "Video encoder support on sim" + depends on VIDEO + default n + +config SIM_VIDEO_ENCODER_DEV_PATH + string "Video encoder device path" + depends on SIM_VIDEO_ENCODER + default "/dev/video2" + +endmenu + menu "Simulated Graphics/Input" config SIM_X11FB diff --git a/arch/sim/include/irq.h b/arch/sim/include/irq.h index e5474e15fa0a3..86bbe794094b0 100644 --- a/arch/sim/include/irq.h +++ b/arch/sim/include/irq.h @@ -68,7 +68,7 @@ extern "C" ****************************************************************************/ /* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt + * register storage structure. It is non-NULL only during interrupt * processing. Access to g_current_regs[] must be through the macro * CURRENT_REGS for portability. */ diff --git a/arch/sim/src/Makefile b/arch/sim/src/Makefile index 5750fd5fe7208..60cf7b8a4ea16 100644 --- a/arch/sim/src/Makefile +++ b/arch/sim/src/Makefile @@ -18,7 +18,7 @@ # ############################################################################ --include $(TOPDIR)/Make.defs +include $(TOPDIR)/tools/apps-or-nuttx-Make.defs ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src @@ -65,6 +65,7 @@ CSRCS += sim_createstack.c sim_usestack.c sim_releasestack.c sim_stackframe.c CSRCS += sim_exit.c sim_schedulesigaction.c sim_switchcontext.c sim_heap.c CSRCS += sim_uart.c sim_copyfullstate.c sim_sigdeliver.c sim_tcbinfo.c sim_cpuinfo.c CSRCS += sim_registerdump.c sim_saveusercontext.c sim_textheap.c +CSRCS += sim_checkhostfstypes.c ifeq ($(CONFIG_SCHED_BACKTRACE),y) CSRCS += sim_backtrace.c @@ -249,6 +250,18 @@ ifeq ($(CONFIG_SIM_CAMERA_V4L2),y) STDLIBS += -lv4l2 endif +ifeq ($(CONFIG_SIM_VIDEO_DECODER),y) + HOSTSRCS += sim_hostdecoder.c + CSRCS += sim_decoder.c + STDLIBS += -lopenh264 +endif + +ifeq ($(CONFIG_SIM_VIDEO_ENCODER),y) + HOSTSRCS += sim_hostencoder.c + CSRCS += sim_encoder.c + STDLIBS += -lx264 +endif + COBJS = $(CSRCS:.c=$(OBJEXT)) NUTTXOBJS = $(AOBJS) $(COBJS) @@ -350,17 +363,32 @@ board/libboard$(LIBEXT): nuttx-names.dat: nuttx-names.in $(call PREPROCESS, nuttx-names.in, nuttx-names.dat) -define LINK_ALLSYMS - $(if $(CONFIG_HOST_MACOS), \ - $(Q) $(TOPDIR)/tools/mkallsyms.sh noconst $(NUTTX) $(CROSSDEV) > allsyms.tmp, \ - $(Q) $(TOPDIR)/tools/mkallsyms.py $(NUTTX) allsyms.tmp) - $(Q) $(call COMPILE, allsyms.tmp, allsyms$(OBJEXT), -x c) +# When multiple linking, these two additional linking objects will be included + +ifeq ($(CONFIG_MM_KASAN_GLOBAL),y) +EXTRALD_OBJ += kasan_globals$(OBJEXT) +endif +ifeq ($(CONFIG_ALLSYMS),y) +EXTRALD_OBJ += allsyms$(OBJEXT) +endif + +define LINK_ALLSYMS_KASAN + $(if $(CONFIG_ALLSYMS), \ + $(if $(CONFIG_HOST_MACOS), \ + $(Q) $(TOPDIR)/tools/mkallsyms.sh noconst $(NUTTX) $(CROSSDEV) > allsyms.tmp, \ + $(Q) $(TOPDIR)/tools/mkallsyms.py $(NUTTX) allsyms.tmp --orderbyname $(CONFIG_SYMTAB_ORDEREDBYNAME))) + $(if $(CONFIG_ALLSYMS), \ + $(Q) $(call COMPILE, allsyms.tmp, allsyms$(OBJEXT), -x c) + $(Q) $(call DELFILE, allsyms.tmp)) + $(if $(CONFIG_MM_KASAN_GLOBAL), + $(Q) $(TOPDIR)/tools/kasan_global.py -e $(NUTTX) -o kasan_globals.tmp + $(Q) $(call COMPILE, kasan_globals.tmp, kasan_globals$(OBJEXT) -fno-sanitize=kernel-address, -x c) + $(Q) $(call DELFILE, kasan_globals.tmp)) $(if $(CONFIG_HAVE_CXX),\ $(Q) "$(CXX)" $(CFLAGS) $(LDFLAGS) -o $(NUTTX) \ - $(HEADOBJ) nuttx.rel $(HOSTOBJS) $(STDLIBS) allsyms$(OBJEXT),\ + $(HEADOBJ) nuttx.rel $(HOSTOBJS) $(STDLIBS) $(EXTRALD_OBJ),\ $(Q) "$(CC)" $(CFLAGS) $(LDFLAGS) -o $(NUTTX) \ - $(HEADOBJ) nuttx.rel $(HOSTOBJS) $(STDLIBS) allsyms$(OBJEXT)) - $(Q) $(call DELFILE, allsyms.tmp allsyms$(OBJEXT)) + $(HEADOBJ) nuttx.rel $(HOSTOBJS) $(STDLIBS) $(EXTRALD_OBJ)) endef # Note: Use objcopy for Linux because for some reasons visibility=hidden @@ -381,17 +409,20 @@ ifneq ($(CONFIG_HOST_MACOS),y) -e 's/__fini_array_start/_sfini/g' -e 's/__fini_array_end/_efini/g' >nuttx.ld $(Q) echo "__init_array_start = .; __init_array_end = .; __fini_array_start = .; __fini_array_end = .;" >>nuttx.ld endif -ifneq ($(CONFIG_ALLSYMS),y) +ifeq ($(CONFIG_MM_KASAN_GLOBAL),y) + $(Q) sed -i 's/\s*\.interp\s*:\s*{\s*\*(\.interp)\s*}/ \ + .kasan.global : {KEEP(*(.data..LASAN0)) KEEP (*(.data.rel.local..LASAN0)) }\n \ + .interp : {*(.interp)}/g' nuttx.ld +endif +ifeq ($(CONFIG_ALLSYMS)$(CONFIG_MM_KASAN_GLOBAL),) $(if $(CONFIG_HAVE_CXX),\ $(Q) "$(CXX)" $(CFLAGS) $(LDFLAGS) -o $(TOPDIR)/$@ $(HEADOBJ) nuttx.rel $(HOSTOBJS) $(STDLIBS),\ $(Q) "$(CC)" $(CFLAGS) $(LDFLAGS) -o $(TOPDIR)/$@ $(HEADOBJ) nuttx.rel $(HOSTOBJS) $(STDLIBS)) else - $(Q) # Link and generate default table - $(Q) $(if $(wildcard $(shell echo $(NUTTX))),,$(call LINK_ALLSYMS, $@)) - $(Q) # Extract all symbols - $(Q) $(call LINK_ALLSYMS, $^) - $(Q) # Extract again since the table offset may changed - $(Q) $(call LINK_ALLSYMS, $^) + $(Q) $(call LINK_ALLSYMS_KASAN) + $(Q) $(call LINK_ALLSYMS_KASAN) + $(Q) $(call LINK_ALLSYMS_KASAN) + $(Q) $(call LINK_ALLSYMS_KASAN) endif $(Q) $(NM) $(TOPDIR)/$@ | \ grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ diff --git a/arch/sim/src/cmake/Toolchain.cmake b/arch/sim/src/cmake/Toolchain.cmake index 47ef9e5f0224d..3f7611f9ee0ac 100644 --- a/arch/sim/src/cmake/Toolchain.cmake +++ b/arch/sim/src/cmake/Toolchain.cmake @@ -1,5 +1,5 @@ # ############################################################################## -# arch/sim/cmake/Toolchain.cmake +# arch/sim/src/cmake/Toolchain.cmake # # Licensed to the Apache Software Foundation (ASF) under one or more contributor # license agreements. See the NOTICE file distributed with this work for @@ -99,13 +99,16 @@ if(CONFIG_CXX_STANDARD) endif() set(ARCHCFLAGS "-Wstrict-prototypes") -set(ARCHCXXFLAGS "-nostdinc++") -if(CONFIG_CXX_EXCEPTION) +if(NOT CONFIG_LIBCXXTOOLCHAIN) + set(ARCHCXXFLAGS "${ARCHCXXFLAGS} -nostdinc++") +endif() + +if(NOT CONFIG_CXX_EXCEPTION) string(APPEND ARCHCXXFLAGS " -fno-exceptions -fcheck-new") endif() -if(CONFIG_CXX_RTTI) +if(NOT CONFIG_CXX_RTTI) string(APPEND ARCHCXXFLAGS " -fno-rtti") endif() diff --git a/arch/sim/src/sim/CMakeLists.txt b/arch/sim/src/sim/CMakeLists.txt index 21ab50b6a83c9..4118093f1051d 100644 --- a/arch/sim/src/sim/CMakeLists.txt +++ b/arch/sim/src/sim/CMakeLists.txt @@ -57,7 +57,8 @@ list( sim_registerdump.c sim_saveusercontext.c sim_tcbinfo.c - sim_textheap.c) + sim_textheap.c + sim_checkhostfstypes.c) if(CONFIG_HOST_X86_64) if(CONFIG_SIM_M32) @@ -139,12 +140,33 @@ list( sim_hosttime.c sim_hostuart.c) +# Note: sim_macho_init.c is picky about the place in the object list for +# linking. Namely, its constructor should be the first one in the executable. +# For now, we are just assuming no other files in HOSTSRCS provide constructors. +if(CONFIG_HOST_MACOS) + if(CONFIG_HAVE_CXXINITIALIZE) + list(APPEND HOSTSRCS sim_macho_init.c) + endif() +endif() + if(CONFIG_SIM_CAMERA_V4L2) list(APPEND HOSTSRCS sim_host_v4l2.c) list(APPEND SRCS sim_camera.c) list(APPEND STDLIBS v4l2) endif() +if(CONFIG_SIM_VIDEO_DECODER) + list(APPEND HOSTSRCS sim_hostdecoder.c) + list(APPEND SRCS sim_decoder.c) + list(APPEND STDLIBS openh264) +endif() + +if(CONFIG_SIM_VIDEO_ENCODER) + list(APPEND HOSTSRCS sim_hostencoder.c) + list(APPEND SRCS sim_encoder.c) + list(APPEND STDLIBS x264) +endif() + if(CONFIG_SPINLOCK) list(APPEND HOSTSRCS sim_testset.c) endif() @@ -156,7 +178,12 @@ endif() if(CONFIG_SIM_X11FB) list(APPEND HOSTSRCS sim_x11framebuffer.c) - list(APPEND STDLIBS X11 Xext) + + find_package(X11 REQUIRED) + if(X11_FOUND) + target_include_directories(nuttx PRIVATE ${X11_INCLUDE_DIR}) + target_link_libraries(nuttx PRIVATE ${X11_LIBRARIES}) + endif() if(CONFIG_SIM_TOUCHSCREEN) list(APPEND SRCS sim_touchscreen.c) @@ -187,7 +214,8 @@ elseif(CONFIG_SIM_NETDEV_VPNKIT) list(APPEND SRCS sim_netdriver.c) list(APPEND HOST_DEFINITIONS CONFIG_SIM_NETDEV_VPNKIT_PATH=\"${CONFIG_SIM_NETDEV_VPNKIT_PATH}\") - list(APPEND HOSTSRCS sim_vpnkit.c vpnkit/protocol.c vpnkit/negotiate.c) + list(APPEND HOSTSRCS sim_vpnkit.c vpnkit/sim_protocol.c + vpnkit/sim_negotiate.c) endif() if(CONFIG_SIM_NETUSRSOCK) @@ -228,14 +256,18 @@ list(APPEND HOST_DEFINITIONS CONFIG_NAME_MAX=${CONFIG_NAME_MAX}) configure_file(${NUTTX_DIR}/include/nuttx/fs/hostfs.h ${CMAKE_CURRENT_BINARY_DIR}/hostfs.h COPYONLY) +configure_file(${CMAKE_BINARY_DIR}/include/nuttx/config.h + ${CMAKE_CURRENT_BINARY_DIR}/config.h COPYONLY) target_include_directories(nuttx PRIVATE ${CMAKE_CURRENT_BINARY_DIR}) -target_include_directories(nuttx PRIVATE ${CMAKE_BINARY_DIR}/include/nuttx) target_include_directories(nuttx PRIVATE ${CMAKE_CURRENT_LIST_DIR}) target_include_directories(sim_head PUBLIC ${NUTTX_DIR}/sched) target_sources(sim_head PUBLIC sim_head.c sim_doirq.c) + +target_include_directories(arch PRIVATE ${CMAKE_CURRENT_BINARY_DIR}) target_sources(arch PRIVATE ${SRCS}) +target_compile_options(arch PRIVATE -fvisibility=default) if(WIN32) set(HOSTDIR win) diff --git a/arch/sim/src/sim/posix/sim_alsa.c b/arch/sim/src/sim/posix/sim_alsa.c index bf6fc06e7529c..ad36ea4031ad3 100644 --- a/arch/sim/src/sim/posix/sim_alsa.c +++ b/arch/sim/src/sim/posix/sim_alsa.c @@ -23,6 +23,7 @@ ****************************************************************************/ #include +#include #include #include #include diff --git a/arch/sim/src/sim/sim_checkhostfstypes.c b/arch/sim/src/sim/sim_checkhostfstypes.c new file mode 100644 index 0000000000000..49145ab34643b --- /dev/null +++ b/arch/sim/src/sim/sim_checkhostfstypes.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * arch/sim/src/sim/sim_checkhostfstypes.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* include headers for NuttX types + * eg. struct stat + * + * Note: This file is not HOSTSRCS. Thus, these files are not + * the host OS version of them. + */ + +#include +#include +#include + +/* include nuttx/fs/hostfs.h for hostfs types + * eg. struct nuttx_stat_s + * + * define __SIM__ to make them visible. + * + * Note: For HOSTSRCS, __SIM__ is automatically defined by make files. + * However, this file is not HOSTSRCS. Thus we need to define it + * by ourselves here. + */ + +#define __SIM__ +#include +#undef __SIM__ + +/* Here we make static assertions to ensure NuttX types (eg. struct stat) + * match the corresponding hostfs types. (eg. struct nuttx_stat_s) + * + * TODO: check the alignment as well. (_Alignof) + */ + +#define STATIC_ASSERT(c) static_assert(c, #c) +#define STATIC_ASSERT_FILED(a, b, f) \ + STATIC_ASSERT(offsetof(struct a, f) == offsetof(struct b, f)); \ + STATIC_ASSERT(sizeof(((struct a *)0)->f) == sizeof(((struct b *)0)->f)) + +/* dirent */ + +STATIC_ASSERT_FILED(nuttx_dirent_s, dirent, d_type); +STATIC_ASSERT_FILED(nuttx_dirent_s, dirent, d_name); + +STATIC_ASSERT(sizeof(struct nuttx_dirent_s) == sizeof(struct dirent)); + +/* stat */ + +STATIC_ASSERT_FILED(nuttx_stat_s, stat, st_dev); +STATIC_ASSERT_FILED(nuttx_stat_s, stat, st_ino); +STATIC_ASSERT_FILED(nuttx_stat_s, stat, st_mode); +STATIC_ASSERT_FILED(nuttx_stat_s, stat, st_nlink); +STATIC_ASSERT_FILED(nuttx_stat_s, stat, st_uid); +STATIC_ASSERT_FILED(nuttx_stat_s, stat, st_gid); +STATIC_ASSERT_FILED(nuttx_stat_s, stat, st_rdev); +STATIC_ASSERT_FILED(nuttx_stat_s, stat, st_size); +STATIC_ASSERT_FILED(nuttx_stat_s, stat, st_atim); +STATIC_ASSERT_FILED(nuttx_stat_s, stat, st_mtim); +STATIC_ASSERT_FILED(nuttx_stat_s, stat, st_ctim); +STATIC_ASSERT_FILED(nuttx_stat_s, stat, st_blksize); +STATIC_ASSERT_FILED(nuttx_stat_s, stat, st_blocks); +STATIC_ASSERT_FILED(nuttx_stat_s, stat, st_size); + +STATIC_ASSERT(sizeof(struct nuttx_stat_s) == sizeof(struct stat)); + +/* statfs */ + +STATIC_ASSERT_FILED(nuttx_statfs_s, statfs, f_type); +STATIC_ASSERT_FILED(nuttx_statfs_s, statfs, f_namelen); +STATIC_ASSERT_FILED(nuttx_statfs_s, statfs, f_bsize); +STATIC_ASSERT_FILED(nuttx_statfs_s, statfs, f_blocks); +STATIC_ASSERT_FILED(nuttx_statfs_s, statfs, f_bfree); +STATIC_ASSERT_FILED(nuttx_statfs_s, statfs, f_bavail); +STATIC_ASSERT_FILED(nuttx_statfs_s, statfs, f_files); +STATIC_ASSERT_FILED(nuttx_statfs_s, statfs, f_ffree); +STATIC_ASSERT_FILED(nuttx_statfs_s, statfs, f_fsid); + +STATIC_ASSERT(sizeof(struct nuttx_statfs_s) == sizeof(struct statfs)); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* dummy function to suppress nxstyle and compiler warnings */ + +void check_hostfs_types_dummy(void); + +void check_hostfs_types_dummy(void) +{ +} diff --git a/arch/sim/src/sim/sim_decoder.c b/arch/sim/src/sim/sim_decoder.c new file mode 100644 index 0000000000000..c9f4f7592a0fa --- /dev/null +++ b/arch/sim/src/sim/sim_decoder.c @@ -0,0 +1,478 @@ +/**************************************************************************** + * arch/sim/src/sim/sim_decoder.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include "sim_hostdecoder.h" +#include "sim_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SIM_DECODER_NAME "sim-h264" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct sim_decoder_s +{ + struct host_decoder_s *decoder; + struct v4l2_format output_fmt; + struct v4l2_format capture_fmt; + struct work_s work; + void *cookie; + bool capture_on; + bool flushing; +}; + +typedef struct sim_decoder_s sim_decoder_t; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int sim_decoder_open(void *cookie, void **priv); +static int sim_decoder_close(void *priv); +static int sim_decoder_capture_streamon(void *priv); +static int sim_decoder_output_streamon(void *priv); +static int sim_decoder_capture_streamoff(void *priv); +static int sim_decoder_output_streamoff(void *priv); +static int sim_decoder_output_available(void *priv); +static int sim_decoder_capture_available(void *priv); +static int sim_decoder_querycap(void *priv, + struct v4l2_capability *cap); +static int sim_decoder_capture_enum_fmt(void *priv, + struct v4l2_fmtdesc *fmt); +static int sim_decoder_output_enum_fmt(void *priv, + struct v4l2_fmtdesc *fmt); +static int sim_decoder_capture_g_fmt(void *priv, + struct v4l2_format *fmt); +static int sim_decoder_output_g_fmt(void *priv, + struct v4l2_format *fmt); +static int sim_decoder_capture_s_fmt(void *priv, + struct v4l2_format *fmt); +static int sim_decoder_output_s_fmt(void *priv, + struct v4l2_format *fmt); +static int sim_decoder_capture_try_fmt(void *priv, + struct v4l2_format *fmt); +static int sim_decoder_output_try_fmt(void *priv, + struct v4l2_format *fmt); +static int sim_decoder_subscribe_event(void *priv, + struct v4l2_event_subscription *sub); +static size_t sim_decoder_capture_g_bufsize(void *priv); +static size_t sim_decoder_output_g_bufsize(void *priv); +static int sim_decoder_process(sim_decoder_t *sim_decoder, + struct v4l2_buffer *dst_buf, + struct v4l2_buffer *src_buf); +static void sim_decoder_work(void *cookie); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct codec_ops_s g_sim_decoder_ops = +{ + .open = sim_decoder_open, + .close = sim_decoder_close, + .capture_streamon = sim_decoder_capture_streamon, + .output_streamon = sim_decoder_output_streamon, + .capture_streamoff = sim_decoder_capture_streamoff, + .output_streamoff = sim_decoder_output_streamoff, + .output_available = sim_decoder_output_available, + .capture_available = sim_decoder_capture_available, + .querycap = sim_decoder_querycap, + .capture_enum_fmt = sim_decoder_capture_enum_fmt, + .output_enum_fmt = sim_decoder_output_enum_fmt, + .capture_g_fmt = sim_decoder_capture_g_fmt, + .output_g_fmt = sim_decoder_output_g_fmt, + .capture_s_fmt = sim_decoder_capture_s_fmt, + .output_s_fmt = sim_decoder_output_s_fmt, + .capture_try_fmt = sim_decoder_capture_try_fmt, + .output_try_fmt = sim_decoder_output_try_fmt, + .subscribe_event = sim_decoder_subscribe_event, + .capture_g_bufsize = sim_decoder_capture_g_bufsize, + .output_g_bufsize = sim_decoder_output_g_bufsize, +}; + +static struct codec_s g_sim_codec_decoder = +{ + .ops = &g_sim_decoder_ops, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int sim_decoder_open(void *cookie, void **priv) +{ + sim_decoder_t *sim_decoder; + struct host_decoder_s *decoder; + + sim_decoder = kmm_zalloc(sizeof(sim_decoder_t)); + if (sim_decoder == NULL) + { + return -ENOMEM; + } + + decoder = host_decoder_open(); + if (decoder == NULL) + { + kmm_free(sim_decoder); + return -ENOMEM; + } + + sim_decoder->decoder = decoder; + sim_decoder->cookie = cookie; + *priv = sim_decoder; + + return 0; +} + +static int sim_decoder_close(void *priv) +{ + sim_decoder_t *sim_decoder = priv; + + host_decoder_close(sim_decoder->decoder); + kmm_free(sim_decoder); + + return 0; +} + +static int sim_decoder_capture_streamon(void *priv) +{ + sim_decoder_t *sim_decoder = priv; + + sim_decoder->capture_on = true; + work_queue(HPWORK, &sim_decoder->work, + sim_decoder_work, sim_decoder, 0); + + return 0; +} + +static int sim_decoder_output_streamon(void *priv) +{ + sim_decoder_t *sim_decoder = priv; + + return host_decoder_streamon(sim_decoder->decoder); +} + +static int sim_decoder_capture_streamoff(void *priv) +{ + sim_decoder_t *sim_decoder = priv; + + sim_decoder->capture_on = false; + return host_decoder_streamoff(sim_decoder->decoder); +} + +static int sim_decoder_output_streamoff(void *priv) +{ + sim_decoder_t *sim_decoder = priv; + + if (!sim_decoder->capture_on) + { + return 0; + } + + sim_decoder->flushing = true; + work_queue(HPWORK, &sim_decoder->work, + sim_decoder_work, sim_decoder, 0); + + return 0; +} + +static int sim_decoder_output_available(void *priv) +{ + sim_decoder_t *sim_decoder = priv; + + if (sim_decoder->capture_on == false) + { + return 0; + } + + work_queue(HPWORK, &sim_decoder->work, + sim_decoder_work, sim_decoder, 0); + + return 0; +} + +static int sim_decoder_capture_available(void *priv) +{ + sim_decoder_t *sim_decoder = priv; + + if (sim_decoder->capture_on == false) + { + return 0; + } + + work_queue(HPWORK, &sim_decoder->work, + sim_decoder_work, sim_decoder, 0); + + return 0; +} + +static int sim_decoder_querycap(void *priv, + struct v4l2_capability *cap) +{ + strlcpy((char *)cap->driver, SIM_DECODER_NAME, sizeof(cap->driver)); + strlcpy((char *)cap->card, SIM_DECODER_NAME, sizeof(cap->card)); + cap->capabilities = V4L2_CAP_VIDEO_M2M; + + return 0; +} + +static int sim_decoder_capture_enum_fmt(void *priv, + struct v4l2_fmtdesc *f) +{ + if (f->index >= 1) + { + return -EINVAL; + } + + f->pixelformat = V4L2_PIX_FMT_YUV420; + return 0; +} + +static int sim_decoder_output_enum_fmt(void *priv, + struct v4l2_fmtdesc *fmt) +{ + if (fmt->index >= 1) + { + return -EINVAL; + } + + fmt->pixelformat = V4L2_PIX_FMT_H264; + return 0; +} + +static int sim_decoder_capture_g_fmt(void *priv, + struct v4l2_format *fmt) +{ + sim_decoder_t *sim_decoder = priv; + + *fmt = sim_decoder->capture_fmt; + return 0; +} + +static int sim_decoder_output_g_fmt(void *priv, + struct v4l2_format *fmt) +{ + sim_decoder_t *sim_decoder = priv; + + *fmt = sim_decoder->output_fmt; + return 0; +} + +static int sim_decoder_capture_s_fmt(void *priv, + struct v4l2_format *fmt) +{ + sim_decoder_t *sim_decoder = priv; + size_t sizeimage; + + if (fmt->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) + { + sim_decoder->capture_fmt = *fmt; + + sizeimage = fmt->fmt.pix.width * fmt->fmt.pix.height * 3 / 2; + sim_decoder->capture_fmt.fmt.pix.sizeimage = sizeimage; + sim_decoder->capture_fmt.fmt.pix.bytesperline = fmt->fmt.pix.width; + + return 0; + } + + return -EINVAL; +} + +static int sim_decoder_output_s_fmt(void *priv, + struct v4l2_format *fmt) +{ + sim_decoder_t *sim_decoder = priv; + size_t sizeimage; + + if (fmt->fmt.pix.pixelformat == V4L2_PIX_FMT_H264) + { + sim_decoder->output_fmt = *fmt; + + sizeimage = fmt->fmt.pix.width * fmt->fmt.pix.height; + sizeimage = (sizeimage * 3 / 2) / 2 + 128; + sim_decoder->output_fmt.fmt.pix.sizeimage = sizeimage; + + return 0; + } + + return -EINVAL; +} + +static int sim_decoder_capture_try_fmt(void *priv, + struct v4l2_format *fmt) +{ + if (fmt->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) + { + return 0; + } + + return -EINVAL; +} + +static int sim_decoder_output_try_fmt(void *priv, + struct v4l2_format *fmt) +{ + if (fmt->fmt.pix.pixelformat == V4L2_PIX_FMT_H264) + { + return 0; + } + + return -EINVAL; +} + +static int sim_decoder_subscribe_event(void *priv, + struct v4l2_event_subscription *sub) +{ + switch (sub->type) + { + case V4L2_EVENT_EOS: + return OK; + + default: + return -EINVAL; + } +} + +static size_t sim_decoder_capture_g_bufsize(void *priv) +{ + sim_decoder_t *sim_decoder = priv; + + if (sim_decoder->capture_fmt.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) + { + return sim_decoder->capture_fmt.fmt.pix.sizeimage; + } + + return 0; +} + +static size_t sim_decoder_output_g_bufsize(void *priv) +{ + sim_decoder_t *sim_decoder = priv; + + if (sim_decoder->output_fmt.fmt.pix.pixelformat == V4L2_PIX_FMT_H264) + { + return sim_decoder->output_fmt.fmt.pix.sizeimage; + } + + return 0; +} + +static int sim_decoder_process(sim_decoder_t *sim_decoder, + struct v4l2_buffer *dst_buf, + struct v4l2_buffer *src_buf) +{ + struct v4l2_event event; + uint8_t *src_data = NULL; + uint32_t src_size = 0; + int64_t src_pts = 0; + int64_t dst_pts = 0; + int ret; + + if (src_buf != NULL) + { + src_data = (uint8_t *)src_buf->m.userptr; + src_size = src_buf->bytesused; + src_pts = src_buf->timestamp.tv_sec * 1000000 + + src_buf->timestamp.tv_usec; + } + + ret = host_decoder_enqueue(sim_decoder->decoder, + src_data, src_pts, src_size); + if (ret >= 0 && src_buf != NULL) + { + codec_output_put_buf(sim_decoder->cookie, src_buf); + } + + if (ret < 1) + { + return ret; + } + + ret = host_decoder_dequeue(sim_decoder->decoder, + (uint8_t *)dst_buf->m.userptr, + &dst_pts, + &dst_buf->bytesused); + if (ret == 0 && src_buf == NULL) + { + sim_decoder->flushing = false; + dst_buf->flags |= V4L2_BUF_FLAG_LAST; + + memset(&event, 0, sizeof(event)); + event.type = V4L2_EVENT_EOS; + codec_queue_event(sim_decoder->cookie, &event); + } + + dst_buf->timestamp.tv_usec = dst_pts % 1000000; + dst_buf->timestamp.tv_sec = dst_pts / 1000000; + + codec_capture_put_buf(sim_decoder->cookie, dst_buf); + return ret; +} + +static void sim_decoder_work(void *decoder) +{ + sim_decoder_t *sim_decoder = decoder; + struct v4l2_buffer *src_buf; + struct v4l2_buffer *dst_buf; + int ret; + + src_buf = codec_output_get_buf(sim_decoder->cookie); + if (src_buf == NULL && !sim_decoder->flushing) + { + return; + } + + dst_buf = codec_capture_get_buf(sim_decoder->cookie); + if (dst_buf == NULL) + { + return; + } + + ret = sim_decoder_process(decoder, dst_buf, src_buf); + if (ret > 0) + { + work_queue(HPWORK, &sim_decoder->work, + sim_decoder_work, sim_decoder, 0); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int sim_decoder_initialize() +{ + return codec_register(CONFIG_SIM_VIDEO_DECODER_DEV_PATH, + &g_sim_codec_decoder); +} diff --git a/arch/sim/src/sim/sim_encoder.c b/arch/sim/src/sim/sim_encoder.c new file mode 100644 index 0000000000000..bf3b41763736e --- /dev/null +++ b/arch/sim/src/sim/sim_encoder.c @@ -0,0 +1,547 @@ +/**************************************************************************** + * arch/sim/src/sim/sim_encoder.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "sim_hostencoder.h" +#include "sim_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SIM_ENCODER_NAME "sim-x264" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct sim_encoder_s +{ + struct host_encoder_s *encoder; + struct v4l2_format output_fmt; + struct v4l2_format capture_fmt; + struct work_s work; + void *cookie; + int bframe; + int fps; + bool capture_on; + bool flushing; +}; + +typedef struct sim_encoder_s sim_encoder_t; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int sim_encoder_open(void *cookie, void **priv); +static int sim_encoder_close(void *priv); +static int sim_encoder_capture_streamon(void *priv); +static int sim_encoder_output_streamon(void *priv); +static int sim_encoder_capture_streamoff(void *priv); +static int sim_encoder_output_streamoff(void *priv); +static int sim_encoder_capture_available(void *priv); +static int sim_encoder_output_available(void *priv); +static int sim_encoder_querycap(void *priv, + struct v4l2_capability *cap); +static int sim_encoder_capture_enum_fmt(void *priv, + struct v4l2_fmtdesc *fmt); +static int sim_encoder_output_enum_fmt(void *priv, + struct v4l2_fmtdesc *fmt); +static int sim_encoder_capture_g_fmt(void *priv, + struct v4l2_format *fmt); +static int sim_encoder_output_g_fmt(void *priv, + struct v4l2_format *fmt); +static int sim_encoder_capture_s_fmt(void *priv, + struct v4l2_format *fmt); +static int sim_encoder_output_s_fmt(void *priv, + struct v4l2_format *fmt); +static int sim_encoder_capture_try_fmt(void *priv, + struct v4l2_format *fmt); +static int sim_encoder_output_try_fmt(void *priv, + struct v4l2_format *fmt); +static size_t sim_encoder_capture_g_bufsize(void *priv); +static size_t sim_encoder_output_g_bufsize(void *priv); +static int sim_encoder_capture_s_parm(void *priv, + struct v4l2_streamparm *parm); +static int sim_encoder_capture_g_ext_ctrls(void *priv, + struct v4l2_ext_controls *ctrls); +static int sim_encoder_capture_s_ext_ctrls(void *priv, + struct v4l2_ext_controls *ctrls); +static int sim_encoder_subscribe_event(void *priv, + struct v4l2_event_subscription *sub); +static void sim_encoder_work(void *cookie); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct codec_ops_s g_sim_encoder_ops = +{ + .open = sim_encoder_open, + .close = sim_encoder_close, + .capture_streamon = sim_encoder_capture_streamon, + .output_streamon = sim_encoder_output_streamon, + .capture_streamoff = sim_encoder_capture_streamoff, + .output_streamoff = sim_encoder_output_streamoff, + .capture_available = sim_encoder_capture_available, + .output_available = sim_encoder_output_available, + .querycap = sim_encoder_querycap, + .capture_enum_fmt = sim_encoder_capture_enum_fmt, + .output_enum_fmt = sim_encoder_output_enum_fmt, + .capture_g_fmt = sim_encoder_capture_g_fmt, + .output_g_fmt = sim_encoder_output_g_fmt, + .capture_s_fmt = sim_encoder_capture_s_fmt, + .output_s_fmt = sim_encoder_output_s_fmt, + .capture_try_fmt = sim_encoder_capture_try_fmt, + .output_try_fmt = sim_encoder_output_try_fmt, + .capture_g_bufsize = sim_encoder_capture_g_bufsize, + .output_g_bufsize = sim_encoder_output_g_bufsize, + .capture_s_parm = sim_encoder_capture_s_parm, + .g_ext_ctrls = sim_encoder_capture_g_ext_ctrls, + .s_ext_ctrls = sim_encoder_capture_s_ext_ctrls, + .subscribe_event = sim_encoder_subscribe_event, +}; + +static struct codec_s g_sim_codec_encoder = +{ + .ops = &g_sim_encoder_ops, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int sim_encoder_open(void *cookie, void **priv) +{ + sim_encoder_t *sim_encoder; + struct host_encoder_s *encoder; + + sim_encoder = kmm_zalloc(sizeof(struct sim_encoder_s)); + if (sim_encoder == NULL) + { + return -ENOMEM; + } + + encoder = host_encoder_open(); + if (encoder == NULL) + { + kmm_free(sim_encoder); + return -ENOMEM; + } + + sim_encoder->encoder = encoder; + sim_encoder->cookie = cookie; + *priv = sim_encoder; + + return 0; +} + +static int sim_encoder_close(void *priv) +{ + sim_encoder_t *sim_encoder = priv; + + host_encoder_close(sim_encoder->encoder); + kmm_free(sim_encoder); + + return 0; +} + +static int sim_encoder_capture_streamon(void *priv) +{ + sim_encoder_t *sim_encoder = priv; + + sim_encoder->capture_on = true; + work_queue(HPWORK, &sim_encoder->work, + sim_encoder_work, sim_encoder, 0); + + return 0; +} + +static int sim_encoder_output_streamon(void *priv) +{ + sim_encoder_t *sim_encoder = priv; + + return host_encoder_streamon(sim_encoder->encoder, + sim_encoder->output_fmt.fmt.pix.width, + sim_encoder->output_fmt.fmt.pix.height, + sim_encoder->fps ? sim_encoder->fps : 30, + sim_encoder->bframe); +} + +static int sim_encoder_capture_available(void *priv) +{ + sim_encoder_t *sim_encoder = priv; + + if (sim_encoder->capture_on == false) + { + return 0; + } + + work_queue(HPWORK, &sim_encoder->work, + sim_encoder_work, sim_encoder, 0); + return 0; +} + +static int sim_encoder_output_available(void *priv) +{ + sim_encoder_t *sim_encoder = priv; + + if (sim_encoder->capture_on == false) + { + return 0; + } + + work_queue(HPWORK, &sim_encoder->work, + sim_encoder_work, sim_encoder, 0); + return 0; +} + +static int sim_encoder_capture_streamoff(void *priv) +{ + sim_encoder_t *sim_encoder = priv; + + sim_encoder->capture_on = false; + return host_encoder_streamoff(sim_encoder->encoder); +} + +static int sim_encoder_output_streamoff(void *priv) +{ + sim_encoder_t *sim_encoder = priv; + + if (!sim_encoder->capture_on) + { + return 0; + } + + sim_encoder->flushing = true; + work_queue(HPWORK, &sim_encoder->work, + sim_encoder_work, sim_encoder, 0); + + return 0; +} + +static int sim_encoder_querycap(void *priv, + struct v4l2_capability *cap) +{ + strncpy((char *)cap->driver, SIM_ENCODER_NAME, sizeof(cap->driver)); + strncpy((char *)cap->card, SIM_ENCODER_NAME, sizeof(cap->card)); + cap->capabilities = V4L2_CAP_VIDEO_M2M; + + return 0; +} + +static int sim_encoder_capture_enum_fmt(void *priv, + struct v4l2_fmtdesc *fmt) +{ + if (fmt->index >= 1) + { + return -EINVAL; + } + + fmt->pixelformat = V4L2_PIX_FMT_H264; + return 0; +} + +static int sim_encoder_output_enum_fmt(void *priv, + struct v4l2_fmtdesc *fmt) +{ + if (fmt->index >= 1) + { + return -EINVAL; + } + + fmt->pixelformat = V4L2_PIX_FMT_YUV420; + return 0; +} + +static int sim_encoder_capture_g_fmt(void *priv, + struct v4l2_format *fmt) +{ + fmt->fmt.pix.field = V4L2_FIELD_NONE; + fmt->fmt.pix.pixelformat = V4L2_PIX_FMT_H264; + + return 0; +} + +static int sim_encoder_output_g_fmt(void *priv, + struct v4l2_format *fmt) +{ + fmt->fmt.pix.field = V4L2_FIELD_NONE; + fmt->fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420; + + return 0; +} + +static int sim_encoder_capture_try_fmt(void *priv, + struct v4l2_format *fmt) +{ + if (fmt->fmt.pix.pixelformat == V4L2_PIX_FMT_H264) + { + return 0; + } + + return -EINVAL; +} + +static int sim_encoder_output_try_fmt(void *priv, + struct v4l2_format *fmt) +{ + if (fmt->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) + { + return 0; + } + + return -EINVAL; +} + +static int sim_encoder_capture_s_fmt(void *priv, + struct v4l2_format *fmt) +{ + sim_encoder_t *sim_encoder = priv; + size_t sizeimage; + + if (fmt->fmt.pix.pixelformat == V4L2_PIX_FMT_H264) + { + sim_encoder->capture_fmt = *fmt; + + sizeimage = fmt->fmt.pix.width * fmt->fmt.pix.height; + sizeimage = (sizeimage * 3 / 2) / 2 + 128; + sim_encoder->capture_fmt.fmt.pix.sizeimage = sizeimage; + + return 0; + } + + return -EINVAL; +} + +static int sim_encoder_output_s_fmt(void *priv, + struct v4l2_format *fmt) +{ + sim_encoder_t *sim_encoder = priv; + size_t sizeimage; + + if (fmt->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) + { + sim_encoder->output_fmt = *fmt; + sizeimage = fmt->fmt.pix.width * fmt->fmt.pix.height * 3 / 2; + sim_encoder->output_fmt.fmt.pix.sizeimage = sizeimage; + + return 0; + } + + return -EINVAL; +} + +static size_t sim_encoder_capture_g_bufsize(void *priv) +{ + sim_encoder_t *sim_encoder = priv; + + if (sim_encoder->capture_fmt.fmt.pix.pixelformat == V4L2_PIX_FMT_H264) + { + return sim_encoder->capture_fmt.fmt.pix.sizeimage; + } + + return 0; +} + +static size_t sim_encoder_output_g_bufsize(void *priv) +{ + sim_encoder_t *sim_encoder = priv; + + if (sim_encoder->output_fmt.fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) + { + return sim_encoder->output_fmt.fmt.pix.sizeimage; + } + + return 0; +} + +static int sim_encoder_capture_s_parm(void *priv, + struct v4l2_streamparm *parm) +{ + sim_encoder_t *sim_encoder = priv; + struct v4l2_fract fract; + + fract = parm->parm.capture.timeperframe; + if (fract.numerator > 0 && fract.denominator > 0) + { + sim_encoder->fps = fract.denominator / fract.numerator; + } + + return 0; +} + +static int sim_encoder_capture_s_ext_ctrls(void *priv, + struct v4l2_ext_controls *ctrls) +{ + sim_encoder_t *sim_encoder = priv; + struct v4l2_ext_control *ctrl; + + if (ctrls->count != 1) + { + return -EINVAL; + } + + ctrl = ctrls->controls; + switch (ctrl->id) + { + case V4L2_CID_MPEG_VIDEO_B_FRAMES: + sim_encoder->bframe = ctrl->value; + return 0; + + default: + return -EINVAL; + } +} + +static int sim_encoder_capture_g_ext_ctrls(void *priv, + struct v4l2_ext_controls *ctrls) +{ + sim_encoder_t *sim_encoder = priv; + struct v4l2_ext_control *ctrl; + + if (ctrls->count != 1) + { + return -EINVAL; + } + + ctrl = ctrls->controls; + switch (ctrl->id) + { + case V4L2_CID_MPEG_VIDEO_B_FRAMES: + ctrl->value = sim_encoder->bframe; + return 0; + + default: + return -EINVAL; + } +} + +static int sim_encoder_subscribe_event(void *priv, + struct v4l2_event_subscription *sub) +{ + switch (sub->type) + { + case V4L2_EVENT_EOS: + return OK; + + default: + return -EINVAL; + } +} + +static int sim_encoder_process(sim_encoder_t *sim_encoder, + struct v4l2_buffer *dst_buf, + struct v4l2_buffer *src_buf) +{ + struct v4l2_event event; + uint8_t *src_data = NULL; + uint32_t src_size = 0; + int64_t src_pts = 0; + int64_t dst_pts = 0; + int ret; + + if (src_buf != NULL) + { + src_data = (uint8_t *)src_buf->m.userptr; + src_size = src_buf->bytesused; + src_pts = src_buf->timestamp.tv_sec * 1000000 + + src_buf->timestamp.tv_usec; + } + + ret = host_encoder_enqueue(sim_encoder->encoder, + src_data, src_size, src_pts); + if (ret >= 0 && src_buf != NULL) + { + codec_output_put_buf(sim_encoder->cookie, src_buf); + } + + if (ret < 1) + { + return ret; + } + + ret = host_encoder_dequeue(sim_encoder->encoder, + (uint8_t *)dst_buf->m.userptr, + &dst_buf->bytesused, + &dst_pts, + &dst_buf->flags); + if (ret == 0 && src_buf == NULL) + { + sim_encoder->flushing = false; + dst_buf->flags |= V4L2_BUF_FLAG_LAST; + + memset(&event, 0, sizeof(event)); + event.type = V4L2_EVENT_EOS; + codec_queue_event(sim_encoder->cookie, &event); + } + + dst_buf->timestamp.tv_usec = dst_pts % 1000000; + dst_buf->timestamp.tv_sec = dst_pts / 1000000; + + codec_capture_put_buf(sim_encoder->cookie, dst_buf); + return ret; +} + +static void sim_encoder_work(void *encoder) +{ + sim_encoder_t *sim_encoder = encoder; + struct v4l2_buffer *src_buf; + struct v4l2_buffer *dst_buf; + int ret; + + src_buf = codec_output_get_buf(sim_encoder->cookie); + if (src_buf == NULL && !sim_encoder->flushing) + { + return; + } + + dst_buf = codec_capture_get_buf(sim_encoder->cookie); + if (dst_buf == NULL) + { + return; + } + + ret = sim_encoder_process(encoder, dst_buf, src_buf); + if (ret > 0) + { + work_queue(HPWORK, &sim_encoder->work, + sim_encoder_work, sim_encoder, 0); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int sim_encoder_initialize() +{ + return codec_register(CONFIG_SIM_VIDEO_ENCODER_DEV_PATH, + &g_sim_codec_encoder); +} diff --git a/arch/sim/src/sim/sim_exit.c b/arch/sim/src/sim/sim_exit.c index fe4be9fa14b73..53a2221d51e87 100644 --- a/arch/sim/src/sim/sim_exit.c +++ b/arch/sim/src/sim/sim_exit.c @@ -58,8 +58,6 @@ void up_exit(int status) enter_critical_section(); - sinfo("TCB=%p exiting\n", this_task()); - /* Destroy the task at the head of the ready to run list. */ nxtask_exit(); diff --git a/arch/sim/src/sim/sim_hostdecoder.c b/arch/sim/src/sim/sim_hostdecoder.c new file mode 100644 index 0000000000000..5d2c2fcec4a20 --- /dev/null +++ b/arch/sim/src/sim/sim_hostdecoder.c @@ -0,0 +1,205 @@ +/**************************************************************************** + * arch/sim/src/sim/sim_hostdecoder.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include +#include + +#include "sim_hostdecoder.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct host_decoder_s +{ + ISVCDecoder *dec; + SBufferInfo bufinfo; + uint8_t *pdst[4]; + int remaining_frames; +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +struct host_decoder_s *host_decoder_open(void) +{ + struct host_decoder_s *decoder; + + decoder = calloc(1, sizeof(struct host_decoder_s)); + if (decoder == NULL) + { + syslog(LOG_ERR, "Init host decoder failed\n"); + } + + return decoder; +} + +int host_decoder_close(struct host_decoder_s *decoder) +{ + free(decoder); + return 0; +} + +int host_decoder_streamon(struct host_decoder_s *decoder) +{ + SDecodingParam param; + int level = WELS_LOG_RESV; + int ret; + + memset(¶m, 0, sizeof(SDecodingParam)); + param.eEcActiveIdc = ERROR_CON_DISABLE; + param.sVideoProperty.eVideoBsType = VIDEO_BITSTREAM_DEFAULT; + + ret = WelsCreateDecoder(&decoder->dec); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to create decoder\n"); + return ret; + } + + (*decoder->dec)->SetOption(decoder->dec, + DECODER_OPTION_TRACE_LEVEL, + &level); + + ret = (*decoder->dec)->Initialize(decoder->dec, ¶m); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize decoder\n"); + WelsDestroyDecoder(decoder->dec); + } + + return ret; +} + +int host_decoder_streamoff(struct host_decoder_s *decoder) +{ + (*decoder->dec)->Uninitialize(decoder->dec); + WelsDestroyDecoder(decoder->dec); + + decoder->remaining_frames = 0; + return 0; +} + +int host_decoder_enqueue(struct host_decoder_s *decoder, + void *data, int64_t pts, int size) +{ + DECODING_STATE state; + + memset(&decoder->bufinfo, 0, sizeof(SBufferInfo)); + memset(decoder->pdst, 0, sizeof(decoder->pdst)); + + if (decoder->remaining_frames == 0) + { + /* When data is NULL and remaining_frames has + * not been assigned, call DecodeFrame2 to obtain + * the pending buffer. + */ + + decoder->bufinfo.uiInBsTimeStamp = pts; + state = (*decoder->dec)->DecodeFrame2(decoder->dec, + data, + size, + decoder->pdst, + &decoder->bufinfo); + if (state != dsErrorFree) + { + syslog(LOG_ERR, "hostdec - decode failed 0x%04x\n", state); + return -EINVAL; + } + + if (data == NULL) + { + (*decoder->dec)->GetOption(decoder->dec, + DECODER_OPTION_NUM_OF_FRAMES_REMAINING_IN_BUFFER, + &decoder->remaining_frames); + } + } + else + { + /* When remaining_frames is assigned and greater than + * zero, call FlushFrame to get the last buffers. + */ + + state = (*decoder->dec)->FlushFrame(decoder->dec, + decoder->pdst, + &decoder->bufinfo); + if (state != dsErrorFree) + { + syslog(LOG_ERR, "hostdec - flush failed 0x%04x\n", state); + return -EINVAL; + } + + decoder->remaining_frames--; + } + + return decoder->bufinfo.iBufferStatus; +} + +int host_decoder_dequeue(struct host_decoder_s *decoder, + void *data, int64_t *pts, uint32_t *size) +{ + uint8_t *dst_addr = data; + int plane; + + for (plane = 0; plane < 3; plane++) + { + uint8_t *src_addr = decoder->pdst[plane]; + int width = decoder->bufinfo.UsrData.sSystemBuffer.iWidth; + int height = decoder->bufinfo.UsrData.sSystemBuffer.iHeight; + int stride = decoder->bufinfo.UsrData.sSystemBuffer.iStride[0]; + int row; + + if (plane > 0) + { + /* UV plane stride is iStride[1] */ + + width = width / 2; + height = height / 2; + stride = decoder->bufinfo.UsrData.sSystemBuffer.iStride[1]; + } + + for (row = 0; row < height; row++) + { + memcpy(dst_addr, src_addr, width); + src_addr += stride; + dst_addr += width; + } + } + + *pts = decoder->bufinfo.uiOutYuvTimeStamp; + *size = decoder->bufinfo.UsrData.sSystemBuffer.iWidth * + decoder->bufinfo.UsrData.sSystemBuffer.iHeight * 3 / 2; + + return decoder->remaining_frames; +} diff --git a/arch/sim/src/sim/sim_hostdecoder.h b/arch/sim/src/sim/sim_hostdecoder.h new file mode 100644 index 0000000000000..a15412ad849f8 --- /dev/null +++ b/arch/sim/src/sim/sim_hostdecoder.h @@ -0,0 +1,50 @@ +/**************************************************************************** + * arch/sim/src/sim/sim_hostdecoder.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_SIM_SRC_SIM_SIM_HOSTDECODER_H +#define __ARCH_SIM_SRC_SIM_SIM_HOSTDECODER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct host_decoder_s; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +struct host_decoder_s *host_decoder_open(void); +int host_decoder_close(struct host_decoder_s *decoder); +int host_decoder_streamon(struct host_decoder_s *decoder); +int host_decoder_streamoff(struct host_decoder_s *decoder); +int host_decoder_enqueue(struct host_decoder_s *decoder, + void *data, int64_t pts, int size); +int host_decoder_dequeue(struct host_decoder_s *decoder, + void *data, int64_t *pts, uint32_t *size); + +#endif /* __ARCH_SIM_SRC_SIM_SIM_HOSTDECODER_H */ + diff --git a/arch/sim/src/sim/sim_hostencoder.c b/arch/sim/src/sim/sim_hostencoder.c new file mode 100644 index 0000000000000..a7810f456e6ed --- /dev/null +++ b/arch/sim/src/sim/sim_hostencoder.c @@ -0,0 +1,197 @@ +/**************************************************************************** + * arch/sim/src/sim/sim_hostencoder.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include +#include + +#include "sim_hostencoder.h" +#include "sim_internal.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct host_encoder_s +{ + x264_t *enc_ctx; + x264_picture_t pic_in; + x264_picture_t pic_out; + x264_nal_t *nal; + x264_param_t param; + int i_nal; + int remaining_frames; +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +struct host_encoder_s *host_encoder_open(void) +{ + return calloc(1, sizeof(struct host_encoder_s)); +} + +int host_encoder_close(struct host_encoder_s *encoder) +{ + free(encoder); + return 0; +} + +int host_encoder_streamon(struct host_encoder_s *encoder, + int width, int height, int fps, int bframe) +{ + int ret; + + memset(&encoder->param, 0, sizeof(x264_param_t)); + + ret = host_uninterruptible(x264_param_default_preset, + &encoder->param, + "fast", + "zerolatency"); + if (ret < 0) + { + return ret; + } + + encoder->param.i_width = width; + encoder->param.i_height = height; + encoder->param.i_fps_num = fps; + encoder->param.i_fps_den = 1; + encoder->param.b_annexb = 1; + encoder->param.i_csp = X264_CSP_I420; + encoder->param.i_keyint_max = 50; + encoder->param.i_keyint_min = 25; + encoder->param.i_bframe = bframe; + + ret = host_uninterruptible(x264_picture_alloc, + &encoder->pic_in, + X264_CSP_I420, + width, + height); + if (ret < 0) + { + return ret; + } + + encoder->enc_ctx = host_uninterruptible(x264_encoder_open, + &encoder->param); + if (!encoder->enc_ctx) + { + host_uninterruptible_no_return(x264_picture_clean, &encoder->pic_in); + return -EINVAL; + } + + return 0; +} + +int host_encoder_streamoff(struct host_encoder_s *encoder) +{ + host_uninterruptible_no_return(x264_encoder_close, encoder->enc_ctx); + host_uninterruptible_no_return(x264_picture_clean, &encoder->pic_in); + encoder->remaining_frames = 0; + + return 0; +} + +int host_encoder_enqueue(struct host_encoder_s *encoder, + uint8_t *data, uint32_t size, int64_t pts) +{ + int ret; + + if (data != NULL) + { + int width = encoder->param.i_width; + int height = encoder->param.i_height; + + encoder->pic_in.i_pts = pts; + memcpy(encoder->pic_in.img.plane[0], data, width * height); + memcpy(encoder->pic_in.img.plane[1], data + width * height, + width * height / 4); + memcpy(encoder->pic_in.img.plane[2], data + width * height * 5 / 4, + width * height / 4); + } + + ret = host_uninterruptible(x264_encoder_encode, + encoder->enc_ctx, + &encoder->nal, + &encoder->i_nal, + (data != NULL ? &encoder->pic_in : NULL), + &encoder->pic_out); + + if (data == NULL) + { + encoder->remaining_frames = + host_uninterruptible(x264_encoder_delayed_frames, + encoder->enc_ctx); + } + + if (ret >= 0) + { + return 1; + } + + return ret; +} + +int host_encoder_dequeue(struct host_encoder_s *encoder, + uint8_t *data, uint32_t *size, + int64_t *pts, uint32_t *flags) +{ + int total_size = 0; + int i; + + for (i = 0; i < encoder->i_nal; i++) + { + memcpy(data + total_size, + encoder->nal[i].p_payload, encoder->nal[i].i_payload); + total_size += encoder->nal[i].i_payload; + } + + *size = total_size; + *pts = encoder->pic_out.i_pts; + + switch (encoder->pic_out.i_type) + { + case X264_TYPE_IDR: + case X264_TYPE_I: + *flags = V4L2_BUF_FLAG_KEYFRAME; + break; + + case X264_TYPE_P: + *flags = V4L2_BUF_FLAG_PFRAME; + break; + + case X264_TYPE_B: + case X264_TYPE_BREF: + *flags = V4L2_BUF_FLAG_BFRAME; + break; + } + + return encoder->remaining_frames; +} diff --git a/arch/sim/src/sim/sim_hostencoder.h b/arch/sim/src/sim/sim_hostencoder.h new file mode 100644 index 0000000000000..fa02da422695d --- /dev/null +++ b/arch/sim/src/sim/sim_hostencoder.h @@ -0,0 +1,51 @@ +/**************************************************************************** + * arch/sim/src/sim/sim_hostencoder.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_SIM_SRC_SIM_SIM_HOSTENCODER_H +#define __ARCH_SIM_SRC_SIM_SIM_HOSTENCODER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct host_encoder_s; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +struct host_encoder_s *host_encoder_open(void); +int host_encoder_close(struct host_encoder_s *encoder); +int host_encoder_streamon(struct host_encoder_s *encoder, + int width, int height, int fps, int bframe); +int host_encoder_streamoff(struct host_encoder_s *encoder); +int host_encoder_enqueue(struct host_encoder_s *encoder, + uint8_t *data, uint32_t size, int64_t pts); +int host_encoder_dequeue(struct host_encoder_s *encoder, + uint8_t *data, uint32_t *size, + int64_t *pts, uint32_t *flags); + +#endif /* __ARCH_SIM_SRC_SIM_SIM_HOSTENCODER_H */ diff --git a/arch/sim/src/sim/sim_initialize.c b/arch/sim/src/sim/sim_initialize.c index d5b194cbff677..bd8b459e6a7d0 100644 --- a/arch/sim/src/sim/sim_initialize.c +++ b/arch/sim/src/sim/sim_initialize.c @@ -306,6 +306,14 @@ void up_initialize(void) sim_usbhost_initialize(); #endif +#ifdef CONFIG_SIM_VIDEO_DECODER + sim_decoder_initialize(); +#endif + +#ifdef CONFIG_SIM_VIDEO_ENCODER + sim_encoder_initialize(); +#endif + kthread_create("loop_task", CONFIG_SIM_LOOPTASK_PRIORITY, CONFIG_DEFAULT_TASK_STACKSIZE, sim_loop_task, NULL); diff --git a/arch/sim/src/sim/sim_internal.h b/arch/sim/src/sim/sim_internal.h index 7b18ed4c32d40..5b41814796d65 100644 --- a/arch/sim/src/sim/sim_internal.h +++ b/arch/sim/src/sim/sim_internal.h @@ -435,6 +435,14 @@ int sim_camera_initialize(void); void sim_camera_loop(void); #endif +#ifdef CONFIG_SIM_VIDEO_DECODER +int sim_decoder_initialize(void); +#endif + +#ifdef CONFIG_SIM_VIDEO_ENCODER +int sim_encoder_initialize(void); +#endif + /* sim_usbdev.c *************************************************************/ #ifdef CONFIG_SIM_USB_DEV diff --git a/arch/sim/src/sim/sim_rptun.c b/arch/sim/src/sim/sim_rptun.c index 7416222da64d8..2a1e21a3ddf3b 100644 --- a/arch/sim/src/sim/sim_rptun.c +++ b/arch/sim/src/sim/sim_rptun.c @@ -22,6 +22,7 @@ * Included Files ****************************************************************************/ +#include #include #include #include @@ -84,17 +85,6 @@ static const char *sim_rptun_get_cpuname(struct rptun_dev_s *dev) return priv->cpuname; } -static const char *sim_rptun_get_firmware(struct rptun_dev_s *dev) -{ - return NULL; -} - -static const struct rptun_addrenv_s * -sim_rptun_get_addrenv(struct rptun_dev_s *dev) -{ - return NULL; -} - static struct rptun_rsc_s * sim_rptun_get_resource(struct rptun_dev_s *dev) { @@ -315,8 +305,6 @@ static void sim_rptun_work(void *arg) static const struct rptun_ops_s g_sim_rptun_ops = { .get_cpuname = sim_rptun_get_cpuname, - .get_firmware = sim_rptun_get_firmware, - .get_addrenv = sim_rptun_get_addrenv, .get_resource = sim_rptun_get_resource, .is_autostart = sim_rptun_is_autostart, .is_master = sim_rptun_is_master, diff --git a/arch/sim/src/sim/sim_smpsignal.c b/arch/sim/src/sim/sim_smpsignal.c index 0f9ba526da38f..aef103b19426e 100644 --- a/arch/sim/src/sim/sim_smpsignal.c +++ b/arch/sim/src/sim/sim_smpsignal.c @@ -128,7 +128,7 @@ bool up_cpu_pausereq(int cpu) } /**************************************************************************** - * Name: up_cpu_paused + * Name: up_cpu_paused_save * * Description: * Handle a pause request from another CPU. Normally, this logic is @@ -137,16 +137,8 @@ bool up_cpu_pausereq(int cpu) * pause operation in other contexts where the interrupt cannot be taken * in order to avoid deadlocks. * - * This function performs the following operations: - * - * 1. It saves the current task state at the head of the current assigned - * task list. - * 2. It waits on a spinlock, then - * 3. Returns from interrupt, restoring the state of the new task at the - * head of the ready to run list. - * * Input Parameters: - * cpu - The index of the CPU to be paused + * None * * Returned Value: * On success, OK is returned. Otherwise, a negated errno value indicating @@ -154,9 +146,9 @@ bool up_cpu_pausereq(int cpu) * ****************************************************************************/ -int up_cpu_paused(int cpu) +int up_cpu_paused_save(void) { - struct tcb_s *tcb = current_task(cpu); + struct tcb_s *tcb = this_task(); /* Update scheduler parameters */ @@ -174,6 +166,38 @@ int up_cpu_paused(int cpu) sim_savestate(tcb->xcp.regs); + return OK; +} + +/**************************************************************************** + * Name: up_cpu_paused + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. + * + * This function performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. + * + * Input Parameters: + * cpu - The index of the CPU to be paused + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused(int cpu) +{ /* Wait for the spinlock to be released */ spin_unlock(&g_cpu_paused[cpu]); @@ -184,16 +208,31 @@ int up_cpu_paused(int cpu) spin_lock(&g_cpu_wait[cpu]); - /* Restore the exception context of the tcb at the (new) head of the - * assigned task list. - */ + spin_unlock(&g_cpu_wait[cpu]); + spin_unlock(&g_cpu_resumed[cpu]); - tcb = current_task(cpu); + return OK; +} - /* The way that we handle signals in the simulation is kind of a - * kludge. This would be unsafe in a truly multi-threaded, - * interrupt driven environment. - */ +/**************************************************************************** + * Name: up_cpu_paused_restore + * + * Description: + * Restore the state of the CPU after it was paused via up_cpu_pause(), + * and resume normal tasking. + * + * Input Parameters: + * None + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused_restore(void) +{ + struct tcb_s *tcb = this_task(); #ifdef CONFIG_SCHED_INSTRUMENTATION /* Notify that we have resumed */ @@ -214,8 +253,6 @@ int up_cpu_paused(int cpu) */ sim_restorestate(tcb->xcp.regs); - spin_unlock(&g_cpu_wait[cpu]); - spin_unlock(&g_cpu_resumed[cpu]); return OK; } diff --git a/arch/sim/src/sim/sim_wifidriver.c b/arch/sim/src/sim/sim_wifidriver.c index e391e5807c97e..1261d22d5a5e9 100644 --- a/arch/sim/src/sim/sim_wifidriver.c +++ b/arch/sim/src/sim/sim_wifidriver.c @@ -56,7 +56,7 @@ #define HOSTAPD_CTRL_PATH " -p /var/run/simwifi/hostapd " #define HOSTAPD_CLI "/usr/bin/sudo /usr/sbin/hostapd_cli " -#define SIMWIFI_FILE "tools/simwifi/sim_wifi.sh " +#define SIMWIFI_FILE "/usr/bin/sim_wifi.sh " #define WPA_SET_NETWORK(wifidev, fmt, args...) \ set_cmd(wifidev,"set_network %d "fmt, (wifidev)->network_id, ##args) @@ -1360,8 +1360,8 @@ static int wifidriver_set_mode(struct sim_netdev_s *wifidev, /* Start the sta config, including wpa_supplicant and udhcpc. */ ret = host_system(NULL, 0, - "/usr/bin/sudo %s/"SIMWIFI_FILE" start_sta %s", - TOPDIR, wifidev->host_ifname); + "/usr/bin/sudo "SIMWIFI_FILE" start_sta %s", + wifidev->host_ifname); if (ret == 0) { /* Check the network number, if no network, should add new network. @@ -1389,8 +1389,8 @@ static int wifidriver_set_mode(struct sim_netdev_s *wifidev, /* Start the hostapd. */ ret = host_system(NULL, 0, - "/usr/bin/sudo %s/"SIMWIFI_FILE" start_ap %s", - TOPDIR, wifidev->host_ifname); + "/usr/bin/sudo "SIMWIFI_FILE" start_ap %s", + wifidev->host_ifname); break; default: diff --git a/arch/sparc/include/irq.h b/arch/sparc/include/irq.h index 2378b657ecf44..b4f2eb8a61c97 100644 --- a/arch/sparc/include/irq.h +++ b/arch/sparc/include/irq.h @@ -93,7 +93,7 @@ static inline uint32_t up_getsp(void) ****************************************************************************/ /* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt + * register storage structure. It is non-NULL only during interrupt * processing. Access to g_current_regs[] must be through the macro * CURRENT_REGS for portability. */ diff --git a/arch/sparc/src/Makefile b/arch/sparc/src/Makefile index 6bb3050ce72a0..a6af15bc32774 100644 --- a/arch/sparc/src/Makefile +++ b/arch/sparc/src/Makefile @@ -18,7 +18,7 @@ # ############################################################################ --include $(TOPDIR)/Make.defs +include $(TOPDIR)/tools/apps-or-nuttx-Make.defs -include chip/Make.defs ARCH_SUBDIR = sparc_v8 diff --git a/arch/sparc/src/bm3803/bm3803-serial.c b/arch/sparc/src/bm3803/bm3803-serial.c index 3d41b64465a29..b6911025f53b2 100644 --- a/arch/sparc/src/bm3803/bm3803-serial.c +++ b/arch/sparc/src/bm3803/bm3803-serial.c @@ -359,10 +359,10 @@ static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im) * in im */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); up_rxint(dev, RX_ENABLED(im)); up_txint(dev, TX_ENABLED(im)); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -374,14 +374,14 @@ static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (im) { *im = priv->im; } up_restoreuartint(dev, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/sparc/src/bm3823/bm3823-serial.c b/arch/sparc/src/bm3823/bm3823-serial.c index 6d5aa07c0efde..12ccba4b04063 100644 --- a/arch/sparc/src/bm3823/bm3823-serial.c +++ b/arch/sparc/src/bm3823/bm3823-serial.c @@ -361,10 +361,10 @@ static void up_restoreuartint(struct uart_dev_s *dev, uint8_t im) * im */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); up_rxint(dev, RX_ENABLED(im)); up_txint(dev, TX_ENABLED(im)); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** @@ -376,14 +376,14 @@ static void up_disableuartint(struct uart_dev_s *dev, uint8_t *im) struct up_dev_s *priv = (struct up_dev_s *)dev->priv; irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (im) { *im = priv->im; } up_restoreuartint(dev, 0); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/sparc/src/common/Make.defs b/arch/sparc/src/common/Make.defs index b79fd5d56e353..5144b50d45054 100644 --- a/arch/sparc/src/common/Make.defs +++ b/arch/sparc/src/common/Make.defs @@ -21,7 +21,7 @@ # Common Sparc files (arch/sparc/src/common) CMN_CSRCS += sparc_allocateheap.c sparc_createstack.c sparc_exit.c -CMN_CSRCS += sparc_getintstack.c sparc_idle.c sparc_initialize.c +CMN_CSRCS += sparc_idle.c sparc_initialize.c CMN_CSRCS += sparc_lowputs.c sparc_mdelay.c sparc_modifyreg8.c CMN_CSRCS += sparc_modifyreg16.c sparc_modifyreg32.c sparc_nputs.c CMN_CSRCS += sparc_releasestack.c sparc_stackframe.c diff --git a/arch/sparc/src/common/sparc_checkstack.c b/arch/sparc/src/common/sparc_checkstack.c index 1a710984344cd..c199409877ed1 100644 --- a/arch/sparc/src/common/sparc_checkstack.c +++ b/arch/sparc/src/common/sparc_checkstack.c @@ -204,9 +204,9 @@ size_t up_check_tcbstack(struct tcb_s *tcb) } #if CONFIG_ARCH_INTERRUPTSTACK > 7 -size_t up_check_intstack(void) +size_t up_check_intstack(int cpu) { - return sparc_stack_check((void *)sparc_intstack_alloc(), + return sparc_stack_check((void *)up_get_intstackbase(cpu), STACK_ALIGN_DOWN(CONFIG_ARCH_INTERRUPTSTACK)); } #endif diff --git a/arch/sparc/src/common/sparc_exit.c b/arch/sparc/src/common/sparc_exit.c index 17dc6842e0233..c81a5a381e984 100644 --- a/arch/sparc/src/common/sparc_exit.c +++ b/arch/sparc/src/common/sparc_exit.c @@ -62,8 +62,6 @@ void up_exit(int status) (void)enter_critical_section(); - sinfo("TCB=%p exiting\n", tcb); - nxsched_dumponexit(); /* Update scheduler parameters */ diff --git a/arch/sparc/src/common/sparc_getintstack.c b/arch/sparc/src/common/sparc_getintstack.c deleted file mode 100644 index 55c258b6f2f2f..0000000000000 --- a/arch/sparc/src/common/sparc_getintstack.c +++ /dev/null @@ -1,44 +0,0 @@ -/**************************************************************************** - * arch/sparc/src/common/sparc_getintstack.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "sparc_internal.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_get_intstackbase - ****************************************************************************/ - -#if CONFIG_ARCH_INTERRUPTSTACK > 3 -uintptr_t up_get_intstackbase(void) -{ - return (uintptr_t)sparc_intstack_alloc(); -} -#endif diff --git a/arch/sparc/src/common/sparc_initialize.c b/arch/sparc/src/common/sparc_initialize.c index a23a138020234..4c4e35b74df4c 100644 --- a/arch/sparc/src/common/sparc_initialize.c +++ b/arch/sparc/src/common/sparc_initialize.c @@ -103,14 +103,11 @@ volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 7 static inline void up_color_intstack(void) { - uint32_t *ptr = (uint32_t *)sparc_intstack_alloc(); - ssize_t size; + int cpu; - for (size = ((CONFIG_ARCH_INTERRUPTSTACK & ~7) * CONFIG_SMP_NCPUS); - size > 0; - size -= sizeof(uint32_t)) + for (cpu = 0; cpu < CONFIG_SMP_NCPUS; cpu++) { - *ptr++ = INTSTACK_COLOR; + sparc_stack_color((void *)up_get_intstackbase(cpu), INTSTACK_SIZE); } } #else diff --git a/arch/sparc/src/common/sparc_internal.h b/arch/sparc/src/common/sparc_internal.h index 6762176956ab6..b2ba78e806ebc 100644 --- a/arch/sparc/src/common/sparc_internal.h +++ b/arch/sparc/src/common/sparc_internal.h @@ -195,13 +195,6 @@ int sparc_swint1(int irq, void *context, void *arg); void sparc_sigdeliver(void); -/* Interrupt handling *******************************************************/ - -#if CONFIG_ARCH_INTERRUPTSTACK > 7 -uintptr_t sparc_intstack_alloc(void); -uintptr_t sparc_intstack_top(void); -#endif - /* Chip-specific functions **************************************************/ /* Chip specific functions defined in arch/sparc/src/ */ diff --git a/arch/sparc/src/s698pm/s698pm-irq.c b/arch/sparc/src/s698pm/s698pm-irq.c index 21b6694309e13..c904de8121cc4 100644 --- a/arch/sparc/src/s698pm/s698pm-irq.c +++ b/arch/sparc/src/s698pm/s698pm-irq.c @@ -499,27 +499,7 @@ int up_prioritize_irq(int irq, int priority) } /**************************************************************************** - * Name: sparc_intstack_top - * - * Description: - * Return a pointer to the top the correct interrupt stack allocation - * for the current CPU. - * - ****************************************************************************/ - -#if CONFIG_ARCH_INTERRUPTSTACK > 7 -uintptr_t sparc_intstack_top(void) -{ -#if defined(CONFIG_SMP) - return g_cpu_intstack_top[up_cpu_index()]; -#else - return g_cpu_intstack_top[0]; -#endif -} -#endif - -/**************************************************************************** - * Name: sparc_intstack_alloc + * Name: up_get_intstackbase * * Description: * Return a pointer to the "alloc" the correct interrupt stack allocation @@ -528,10 +508,10 @@ uintptr_t sparc_intstack_top(void) ****************************************************************************/ #if CONFIG_ARCH_INTERRUPTSTACK > 7 -uintptr_t sparc_intstack_alloc(void) +uintptr_t up_get_intstackbase(int cpu) { #if defined(CONFIG_SMP) - return g_cpu_intstack_top[up_cpu_index()] - INTSTACK_SIZE; + return g_cpu_intstack_top[cpu] - INTSTACK_SIZE; #else return g_cpu_intstack_top[0] - INTSTACK_SIZE; #endif diff --git a/arch/sparc/src/s698pm/s698pm_cpupause.c b/arch/sparc/src/s698pm/s698pm_cpupause.c index 16449cabf8a2b..3e7101a66dfaf 100644 --- a/arch/sparc/src/s698pm/s698pm_cpupause.c +++ b/arch/sparc/src/s698pm/s698pm_cpupause.c @@ -85,7 +85,7 @@ bool up_cpu_pausereq(int cpu) } /**************************************************************************** - * Name: up_cpu_paused + * Name: up_cpu_paused_save * * Description: * Handle a pause request from another CPU. Normally, this logic is @@ -94,16 +94,8 @@ bool up_cpu_pausereq(int cpu) * pause operation in other contexts where the interrupt cannot be taken * in order to avoid deadlocks. * - * This function performs the following operations: - * - * 1. It saves the current task state at the head of the current assigned - * task list. - * 2. It waits on a spinlock, then - * 3. Returns from interrupt, restoring the state of the new task at the - * head of the ready to run list. - * * Input Parameters: - * cpu - The index of the CPU to be paused + * None * * Returned Value: * On success, OK is returned. Otherwise, a negated errno value indicating @@ -111,7 +103,7 @@ bool up_cpu_pausereq(int cpu) * ****************************************************************************/ -int up_cpu_paused(int cpu) +int up_cpu_paused_save(void) { struct tcb_s *tcb = this_task(); @@ -131,6 +123,38 @@ int up_cpu_paused(int cpu) sparc_savestate(tcb->xcp.regs); + return OK; +} + +/**************************************************************************** + * Name: up_cpu_paused + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. + * + * This function performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. + * + * Input Parameters: + * cpu - The index of the CPU to be paused + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused(int cpu) +{ /* Wait for the spinlock to be released */ spin_unlock(&g_cpu_paused[cpu]); @@ -141,11 +165,31 @@ int up_cpu_paused(int cpu) spin_lock(&g_cpu_wait[cpu]); - /* Restore the exception context of the tcb at the (new) head of the - * assigned task list. - */ + spin_unlock(&g_cpu_wait[cpu]); + spin_unlock(&g_cpu_resumed[cpu]); + + return OK; +} + +/**************************************************************************** + * Name: up_cpu_paused_restore + * + * Description: + * Restore the state of the CPU after it was paused via up_cpu_pause(), + * and resume normal tasking. + * + * Input Parameters: + * None + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ - tcb = this_task(); +int up_cpu_paused_restore(void) +{ + struct tcb_s *tcb = this_task(); #ifdef CONFIG_SCHED_INSTRUMENTATION /* Notify that we have resumed */ @@ -163,9 +207,6 @@ int up_cpu_paused(int cpu) sparc_restorestate(tcb->xcp.regs); - spin_unlock(&g_cpu_wait[cpu]); - spin_unlock(&g_cpu_resumed[cpu]); - return OK; } @@ -283,7 +324,7 @@ int up_cpu_pause(int cpu) * called. g_cpu_paused will be unlocked in any case. */ - return 0; + return OK; } /**************************************************************************** @@ -333,5 +374,5 @@ int up_cpu_resume(int cpu) spin_unlock(&g_cpu_resumed[cpu]); - return 0; + return OK; } diff --git a/arch/sparc/src/s698pm/s698pm_cpustart.c b/arch/sparc/src/s698pm/s698pm_cpustart.c index df58abff83266..24ce75feeb35d 100644 --- a/arch/sparc/src/s698pm/s698pm_cpustart.c +++ b/arch/sparc/src/s698pm/s698pm_cpustart.c @@ -71,8 +71,6 @@ volatile static spinlock_t g_cpu_boot; void s698pm_cpu_boot(void) { - struct tcb_s *tcb = this_task(); - _info("CPU%d Started\n", this_cpu()); /* Initialize CPU interrupts */ @@ -84,12 +82,12 @@ void s698pm_cpu_boot(void) #ifdef CONFIG_SCHED_INSTRUMENTATION /* Notify that this CPU has started */ - sched_note_cpu_started(tcb); + sched_note_cpu_started(this_task()); #endif /* Reset scheduler parameters */ - nxsched_resume_scheduler(tcb); + nxsched_resume_scheduler(this_task()); /* And finally, enable cpu interrupts */ diff --git a/arch/sparc/src/sparc_v8/Toolchain.defs b/arch/sparc/src/sparc_v8/Toolchain.defs index b6c199e8d0631..42f5dbdf82e97 100644 --- a/arch/sparc/src/sparc_v8/Toolchain.defs +++ b/arch/sparc/src/sparc_v8/Toolchain.defs @@ -77,11 +77,15 @@ ifeq ($(CONFIG_DEBUG_SYMBOLS),y) endif ARCHCFLAGS += -fno-common -ARCHCXXFLAGS += -fno-common -nostdinc++ +ARCHCXXFLAGS += -fno-common ARCHCFLAGS += -Wall -Wstrict-prototypes -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas ARCHCXXFLAGS += -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas +ifneq ($(CONFIG_LIBCXXTOOLCHAIN),y) + ARCHCXXFLAGS += -nostdinc++ +endif + ifneq ($(CONFIG_CXX_STANDARD),) ARCHCXXFLAGS += -std=$(CONFIG_CXX_STANDARD) endif diff --git a/arch/tricore/Kconfig b/arch/tricore/Kconfig new file mode 100644 index 0000000000000..e9b545458859b --- /dev/null +++ b/arch/tricore/Kconfig @@ -0,0 +1,43 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_TRICORE +comment "Tricore Options" + +choice + prompt "Tricore Toolchain Selection" + default TRICORE_TOOLCHAIN_TASKING + +config TRICORE_TOOLCHAIN_TASKING + bool "AURIX Tasking C/C++ toolchain" + select ARCH_TOOLCHAIN_TASKING + +endchoice # Tricore Toolchain Selection + +config ARCH_TC3XX + bool + select ARCH_HAVE_TESTSET + default n + +config ARCH_FAMILY + string + default "tc3xx" if ARCH_TC3XX + +config ARCH_CHIP + string + default "tc3xx" if ARCH_CHIP_TC397 + +config ARCH_CHIP_TC397 + bool "AURIX Family TC397" + select ARCH_TC3XX + select ALARM_ARCH + select ONESHOT + ---help--- + AURIX TC39x family: TC397 + +if ARCH_TC3XX +source "arch/tricore/src/tc3xx/Kconfig" +endif +endif # ARCH_TRICORE diff --git a/arch/tricore/include/.gitignore b/arch/tricore/include/.gitignore new file mode 100644 index 0000000000000..af8911db06172 --- /dev/null +++ b/arch/tricore/include/.gitignore @@ -0,0 +1,2 @@ +/board +/chip diff --git a/arch/tricore/include/arch.h b/arch/tricore/include/arch.h new file mode 100644 index 0000000000000..f44a3976d1630 --- /dev/null +++ b/arch/tricore/include/arch.h @@ -0,0 +1,64 @@ +/**************************************************************************** + * arch/tricore/include/arch.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/arch.h + */ + +#ifndef __ARCH_TRICORE_INCLUDE_ARCH_H +#define __ARCH_TRICORE_INCLUDE_ARCH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_TRICORE_INCLUDE_ARCH_H */ diff --git a/arch/tricore/include/inttypes.h b/arch/tricore/include/inttypes.h new file mode 100644 index 0000000000000..dc15bff5b6878 --- /dev/null +++ b/arch/tricore/include/inttypes.h @@ -0,0 +1,120 @@ +/**************************************************************************** + * arch/tricore/include/inttypes.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_INCLUDE_INTTYPES_H +#define __ARCH_TRICORE_INCLUDE_INTTYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define INT32_C(x) x ## l +#define INT64_C(x) x ## ll +#define UINT32_C(x) x ## ul +#define UINT64_C(x) x ## ull + +#define PRId8 "d" +#define PRId16 "d" +#define PRId32 "ld" +#define PRId64 "lld" + +#define PRIdPTR "d" + +#define PRIi8 "i" +#define PRIi16 "i" +#define PRIi32 "li" +#define PRIi64 "lli" + +#define PRIiPTR "i" + +#define PRIo8 "o" +#define PRIo16 "o" +#define PRIo32 "lo" +#define PRIo64 "llo" + +#define PRIoPTR "o" + +#define PRIu8 "u" +#define PRIu16 "u" +#define PRIu32 "lu" +#define PRIu64 "llu" + +#define PRIuPTR "u" + +#define PRIx8 "x" +#define PRIx16 "x" +#define PRIx32 "lx" +#define PRIx64 "llx" + +#define PRIxPTR "x" + +#define PRIX8 "X" +#define PRIX16 "X" +#define PRIX32 "lX" +#define PRIX64 "llX" + +#define PRIXPTR "X" + +#define SCNd8 "hhd" +#define SCNd16 "hd" +#define SCNd32 "ld" +#define SCNd64 "lld" + +#define SCNdPTR "d" + +#define SCNi8 "hhi" +#define SCNi16 "hi" +#define SCNi32 "li" +#define SCNi64 "lli" + +#define SCNiPTR "i" + +#define SCNo8 "hho" +#define SCNo16 "ho" +#define SCNo32 "lo" +#define SCNo64 "llo" + +#define SCNoPTR "o" + +#define SCNu8 "hhu" +#define SCNu16 "hu" +#define SCNu32 "lu" +#define SCNu64 "llu" + +#define SCNuPTR "u" + +#define SCNx8 "hhx" +#define SCNx16 "hx" +#define SCNx32 "lx" +#define SCNx64 "llx" + +#define SCNxPTR "x" + +#define INT8_C(x) x +#define INT16_C(x) x + +#define UINT8_C(x) x +#define UINT16_C(x) x + +#endif /* __ARCH_TRICORE_INCLUDE_INTTYPES_H */ diff --git a/arch/tricore/include/irq.h b/arch/tricore/include/irq.h new file mode 100644 index 0000000000000..e8fa9b7786607 --- /dev/null +++ b/arch/tricore/include/irq.h @@ -0,0 +1,178 @@ +/**************************************************************************** + * arch/tricore/include/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_TRICORE_INCLUDE_IRQ_H +#define __ARCH_TRICORE_INCLUDE_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/* Include NuttX-specific IRQ definitions */ + +#include + +/* Include chip-specific IRQ definitions (including IRQ numbers) */ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_current_regs[] holds a references to the current interrupt level + * register storage structure. It is non-NULL only during interrupt + * processing. Access to g_current_regs[] must be through the macro + * CURRENT_REGS for portability. + */ + +/* For the case of architectures with multiple CPUs, then there must be one + * such value for each processor that can receive an interrupt. + */ + +EXTERN volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS]; +#define CURRENT_REGS (g_current_regs[up_cpu_index()]) + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: up_cpu_index + * + * Description: + * Return an index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + * Input Parameters: + * None + * + * Returned Value: + * An integer index in the range of 0 through (CONFIG_SMP_NCPUS-1) that + * corresponds to the currently executing CPU. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +int up_cpu_index(void) noinstrument_function; +#else +# define up_cpu_index() (0) +#endif + +/**************************************************************************** + * Name: up_irq_enable + * + * Description: + * Enable interrupts globally. + * + ****************************************************************************/ + +void up_irq_enable(void); + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +noinstrument_function static inline uintptr_t up_getsp(void) +{ + return (uintptr_t)__get_sp(); +} + +/**************************************************************************** + * Name: up_irq_save + * + * Description: + * Disable interrupts and return the previous value of the mstatus register + * + ****************************************************************************/ + +noinstrument_function static inline irqstate_t up_irq_save(void) +{ + return __disable_and_save(); +} + +/**************************************************************************** + * Name: up_irq_restore + * + * Description: + * Restore the value of the mstatus register + * + ****************************************************************************/ + +noinstrument_function static inline void up_irq_restore(irqstate_t flags) +{ + __restore(flags); +} + +/**************************************************************************** + * Name: up_interrupt_context + * + * Description: + * Return true is we are currently executing in the interrupt + * handler context. + * + ****************************************************************************/ + +noinstrument_function +static inline bool up_interrupt_context(void) +{ +#ifdef CONFIG_SMP + irqstate_t flags = up_irq_save(); +#endif + + bool ret = CURRENT_REGS != NULL; + +#ifdef CONFIG_SMP + up_irq_restore(flags); +#endif + + return ret; +} +#endif /* __ASSEMBLY__ */ + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ARCH_TRICORE_INCLUDE_IRQ_H */ diff --git a/arch/tricore/include/limits.h b/arch/tricore/include/limits.h new file mode 100644 index 0000000000000..3a68941f7fa25 --- /dev/null +++ b/arch/tricore/include/limits.h @@ -0,0 +1,82 @@ +/**************************************************************************** + * arch/tricore/include/limits.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_INCLUDE_LIMITS_H +#define __ARCH_TRICORE_INCLUDE_LIMITS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CHAR_BIT 8 +#define SCHAR_MIN (-SCHAR_MAX - 1) +#define SCHAR_MAX 127 +#define UCHAR_MAX 255 + +/* These could be different on machines where char is unsigned */ + +#ifdef __CHAR_UNSIGNED__ +# define CHAR_MIN 0 +# define CHAR_MAX UCHAR_MAX +#else +# define CHAR_MIN SCHAR_MIN +# define CHAR_MAX SCHAR_MAX +#endif + +#define SHRT_MIN (-SHRT_MAX - 1) +#define SHRT_MAX 32767 +#define USHRT_MAX 65535U + +#define INT_MIN (-INT_MAX - 1) +#define INT_MAX 2147483647 +#define UINT_MAX 4294967295U + +/* These change on 32-bit and 64-bit platforms */ + +# define LONG_MIN (-LONG_MAX - 1) +# define LONG_MAX 2147483647L +# define ULONG_MAX 4294967295UL + +# define LLONG_MIN (-LLONG_MAX - 1) +# define LLONG_MAX 9223372036854775807LL +# define ULLONG_MAX 18446744073709551615ULL + +/* A pointer is 4 bytes */ + +# define PTR_MIN (-PTR_MAX - 1) +# define PTR_MAX 2147483647 +# define UPTR_MAX 4294967295U + +#if !defined(__WCHAR_TYPE__) +# define WCHAR_MIN INT_MIN +# define WCHAR_MAX INT_MAX +#elif defined(__WCHAR_UNSIGNED__) +# define WCHAR_MIN 0 +# define WCHAR_MAX __WCHAR_MAX__ +#else +# define WCHAR_MIN (-__WCHAR_MAX__ - 1) +# define WCHAR_MAX __WCHAR_MAX__ +#endif + +#endif /* __ARCH_TRICORE_INCLUDE_LIMITS_H */ diff --git a/arch/tricore/include/spinlock.h b/arch/tricore/include/spinlock.h new file mode 100644 index 0000000000000..6f75e8fd5b0e9 --- /dev/null +++ b/arch/tricore/include/spinlock.h @@ -0,0 +1,88 @@ +/**************************************************************************** + * arch/tricore/include/spinlock.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_INCLUDE_SPINLOCK_H +#define __ARCH_TRICORE_INCLUDE_SPINLOCK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Spinlock states */ + +#define SP_UNLOCKED 0 /* The Un-locked state */ +#define SP_LOCKED 1 /* The Locked state */ + +/* Memory barriers for use with NuttX spinlock logic + * + * Data Memory Barrier (DMB) acts as a memory barrier. + * Data Synchronization Barrier (DSB) acts as a special kind of memory + * barrier. + */ + +#define SP_DSB() __dsync() +#define SP_DMB() __asm("":::"memory") + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* The Type of a spinlock. */ + +typedef long spinlock_t; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: up_testset + * + * Description: + * Perform an atomic test and set operation on the provided spinlock. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * lock - The address of spinlock object. + * + * Returned Value: + * The spinlock is always locked upon return. The value of previous value + * of the spinlock variable is returned, either SP_LOCKED if the spinlock + * as previously locked (meaning that the test-and-set operation failed to + * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked + * (meaning that we successfully obtained the lock) + * + ****************************************************************************/ + +/* See prototype in nuttx/include/nuttx/spinlock.h */ + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_TRICORE_INCLUDE_SPINLOCK_H */ diff --git a/arch/tricore/include/syscall.h b/arch/tricore/include/syscall.h new file mode 100644 index 0000000000000..5b1e9eccb4fed --- /dev/null +++ b/arch/tricore/include/syscall.h @@ -0,0 +1,350 @@ +/**************************************************************************** + * arch/tricore/include/syscall.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through include/syscall.h or include/sys/sycall.h + */ + +#ifndef __ARCH_TRICORE_INCLUDE_SYSCALL_H +#define __ARCH_TRICORE_INCLUDE_SYSCALL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +#define SYS_syscall 0x00 + +/* Configuration ************************************************************/ + +/* This logic uses three system calls {0,1,2} for context switching and one + * for the syscall return. + * So a minimum of four syscall values must be reserved. + * If CONFIG_BUILD_FLAT isn't defined, then four more syscall values must + * be reserved. + */ + +#ifndef CONFIG_BUILD_FLAT +# define CONFIG_SYS_RESERVED 8 +#else +# define CONFIG_SYS_RESERVED 4 +#endif + +/* Cortex-M system calls ****************************************************/ + +/* SYS call 1: + * + * void tricore_fullcontextrestore(uint32_t *restoreregs) noreturn_function; + */ + +#define SYS_restore_context (1) + +/* SYS call 2: + * + * void tricore_switchcontext(uint32_t **saveregs, uint32_t *restoreregs); + */ + +#define SYS_switch_context (2) + +#ifdef CONFIG_LIB_SYSCALL +/* SYS call 3: + * + * void tricore_syscall_return(void); + */ + +#define SYS_syscall_return (3) +#endif /* CONFIG_LIB_SYSCALL */ + +#ifndef CONFIG_BUILD_FLAT +/* SYS call 4: + * + * void up_task_start(main_t taskentry, int argc, char *argv[]) + * noreturn_function; + */ + +#define SYS_task_start (4) + +/* SYS call 5: + * + * void up_pthread_start((pthread_startroutine_t startup, + * pthread_startroutine_t entrypt, pthread_addr_t arg) + * noreturn_function + */ + +#define SYS_pthread_start (5) + +/* SYS call 6: + * + * void signal_handler(_sa_sigaction_t sighand, + * int signo, siginfo_t *info, + * void *ucontext); + */ + +#define SYS_signal_handler (6) + +/* SYS call 7: + * + * void signal_handler_return(void); + */ + +#define SYS_signal_handler_return (7) +#endif /* !CONFIG_BUILD_FLAT */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* SVC with SYS_ call number and no parameters */ + +static inline uintptr_t sys_call0(unsigned int nbr) +{ + register long reg0; + + __asm volatile + ( + "mov d8, %0 \n\t" + : + : "d"(nbr) + : "d8" + ); + __asm volatile + ( + "syscall %1" + : "=d"(reg0) + : "i"(SYS_syscall), "d"(nbr) + : "memory", "a11" + ); + + return reg0; +} + +/* SVC with SYS_ call number and one parameter */ + +static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1) +{ + register long reg0; + + __asm volatile + ( + "mov d8, %0 \n\t" + "mov d9, %1 \n\t" + : + : "d"(nbr), "d"(parm1) + : "d8", "d9" + ); + __asm volatile + ( + "syscall %1" + : "=d"(reg0) + : "i"(SYS_syscall) + : "memory", "a11" + ); + + return reg0; +} + +/* SVC with SYS_ call number and two parameters */ + +static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2) +{ + register long reg0; + + __asm volatile + ( + "mov d8, %0 \n\t" + "mov d9, %1 \n\t" + "mov d10, %2 \n\t" + : + : "d"(nbr), "d"(parm1), "d"(parm2) + : "d8", "d9", "d10" + ); + __asm volatile + ( + "syscall %1" + : "=d"(reg0) + : "i"(SYS_syscall) + : "memory", "a11" + ); + + return reg0; +} + +/* SVC with SYS_ call number and three parameters */ + +static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2, uintptr_t parm3) +{ + register long reg0; + + __asm volatile + ( + "mov d8, %0 \n\t" + "mov d9, %1 \n\t" + "mov d10, %2 \n\t" + "mov d11, %3 \n\t" + : + : "d"(nbr), "d"(parm1), "d"(parm2), "d"(parm3) + : "d8", "d9", "d10", "d11" + ); + __asm volatile + ( + "syscall %1" + : "=d"(reg0) + : "i"(SYS_syscall) + : "memory", "a11" + ); + + return reg0; +} + +/* SVC with SYS_ call number and four parameters */ + +static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2, uintptr_t parm3, + uintptr_t parm4) +{ + register long reg0; + + __asm volatile + ( + "mov d8, %0 \n\t" + "mov d9, %1 \n\t" + "mov d10, %2 \n\t" + "mov d11, %3 \n\t" + "mov d12, %4 \n\t" + : + : "d"(nbr), "d"(parm1), "d"(parm2), "d"(parm3), "d"(parm4) + : "d8", "d9", "d10", "d11", "d12" + ); + __asm volatile + ( + "syscall %1" + : "=d"(reg0) + : "i"(SYS_syscall) + : "memory", "a11" + ); + + return reg0; +} + +/* SVC with SYS_ call number and five parameters */ + +static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2, uintptr_t parm3, + uintptr_t parm4, uintptr_t parm5) +{ + register long reg0; + + __asm volatile + ( + "mov d8, %0 \n\t" + "mov d9, %1 \n\t" + "mov d10, %2 \n\t" + "mov d11, %3 \n\t" + "mov d12, %4 \n\t" + "mov d13, %5 \n\t" + : + : "d"(nbr), "d"(parm1), "d"(parm2), "d"(parm3), "d"(parm4), "d"(parm5) + : "d8", "d9", "d10", "d11", "d12", "d13" + ); + __asm volatile + ( + "syscall %1" + : "=d"(reg0) + : "i"(SYS_syscall) + : "memory", "a11" + ); + + return reg0; +} + +/* SVC with SYS_ call number and six parameters */ + +static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1, + uintptr_t parm2, uintptr_t parm3, + uintptr_t parm4, uintptr_t parm5, + uintptr_t parm6) +{ + register long reg0; + + __asm volatile + ( + "mov d8, %0 \n\t" + "mov d9, %1 \n\t" + "mov d10, %2 \n\t" + "mov d11, %3 \n\t" + "mov d12, %4 \n\t" + "mov d13, %5 \n\t" + "mov d14, %6 \n\t" + : + : "d"(nbr), "d"(parm1), "d"(parm2), + "d"(parm3), "d"(parm4), "d"(parm5), "d"(parm6) + : "d8", "d9", "d10", "d11", "d12", "d13", "d14" + ); + __asm volatile + ( + "syscall %1" + : "=d"(reg0) + : "i"(SYS_syscall) + : "memory", "a11" + ); + + return reg0; +} + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_TRICORE_INCLUDE_SYSCALL_H */ diff --git a/arch/tricore/include/tc3xx/irq.h b/arch/tricore/include/tc3xx/irq.h new file mode 100644 index 0000000000000..72ddfb2e48d99 --- /dev/null +++ b/arch/tricore/include/tc3xx/irq.h @@ -0,0 +1,140 @@ +/**************************************************************************** + * arch/tricore/include/tc3xx/irq.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, + * only indirectly through nuttx/irq.h + */ + +#ifndef __ARCH_TRICORE_INCLUDE_TC3XX_IRQ_H +#define __ARCH_TRICORE_INCLUDE_TC3XX_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Prototypes + ****************************************************************************/ + +/* Upper CSA */ + +#define REG_UPCXI 0 +#define REG_PSW 1 +#define REG_A10 2 +#define REG_UA11 3 +#define REG_D8 4 +#define REG_D9 5 +#define REG_D10 6 +#define REG_D11 7 +#define REG_A12 8 +#define REG_A13 9 +#define REG_A14 10 +#define REG_A15 11 +#define REG_D12 12 +#define REG_D13 13 +#define REG_D14 14 +#define REG_D15 15 + +/* Lower CSA */ + +#define REG_LPCXI 0 +#define REG_LA11 1 +#define REG_A2 2 +#define REG_A3 3 +#define REG_D0 4 +#define REG_D1 5 +#define REG_D2 6 +#define REG_D3 7 +#define REG_A4 8 +#define REG_A5 9 +#define REG_A6 10 +#define REG_A7 11 +#define REG_D4 12 +#define REG_D5 13 +#define REG_D6 14 +#define REG_D7 15 + +#define REG_RA REG_UA11 +#define REG_SP REG_A10 +#define REG_UPC REG_UA11 + +#define REG_LPC REG_LA11 + +#define TC_CONTEXT_REGS (16) + +#define XCPTCONTEXT_REGS (TC_CONTEXT_REGS) +#define XCPTCONTEXT_SIZE (sizeof(void *) * TC_CONTEXT_REGS) + +#define NR_IRQS (255) + +/* PSW: Program Status Word Register */ + +#define PSW_CDE (1 << 7) /* Bits 7: Call Depth Count Enable */ +#define PSW_IS (1 << 9) /* Bits 9: Interrupt Stack Control */ +#define PSW_IO (10) /* Bits 10-11: Access Privilege Level Control (I/O Privilege) */ +# define PSW_IO_USER0 (0 << PSW_IO) +# define PSW_IO_USER1 (1 << PSW_IO) +# define PSW_IO_SUPERVISOR (2 << PSW_IO) + +/* PCXI: Previous Context Information and Pointer Register */ + +#define PCXI_UL (1 << 20) /* Bits 20: Upper or Lower Context Tag */ +#define PCXI_PIE (1 << 21) /* Bits 21: Previous Interrupt Enable */ + +/* FCX: Free CSA List Head Pointer Register */ + +#define FCX_FCXO (0) /* Bits 0-15: FCX Offset Address */ +#define FCX_FCXS (16) /* Bits 16-19: FCX Segment Address */ +#define FCX_FCXO_MASK (0xffff << FCX_FCXO) +#define FCX_FCXS_MASK (0xf << FCX_FCXS) +#define FCX_FREE (FCX_FCXS_MASK | FCX_FCXO_MASK) /* Free CSA manipulation */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +struct xcptcontext +{ + /* The following function pointer is non-zero if there are pending signals + * to be processed. + */ + + void *sigdeliver; /* Actual type is sig_deliver_t */ + + /* These are saved copies of the context used during + * signal processing. + */ + + uintptr_t *saved_regs; + + /* Register save area with XCPTCONTEXT_SIZE, only valid when: + * 1.The task isn't running or + * 2.The task is interrupted + * otherwise task is running, and regs contain the stale value. + */ + + uintptr_t *regs; +}; +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_TRICORE_INCLUDE_TC3XX_IRQ_H */ diff --git a/arch/tricore/include/types.h b/arch/tricore/include/types.h new file mode 100644 index 0000000000000..0daba0000627e --- /dev/null +++ b/arch/tricore/include/types.h @@ -0,0 +1,103 @@ +/**************************************************************************** + * arch/tricore/include/types.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through sys/types.h + */ + +#ifndef __ARCH_TRICORE_INCLUDE_TYPES_H +#define __ARCH_TRICORE_INCLUDE_TYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Declarations + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* These are the sizes of the standard integer types. NOTE that these type + * names have a leading underscore character. This file will be included + * (indirectly) by include/stdint.h and typedef'ed to the final name without + * the underscore character. This roundabout way of doings things allows + * the stdint.h to be removed from the include/ directory in the event that + * the user prefers to use the definitions provided by their toolchain header + * files + */ + +typedef signed char _int8_t; +typedef unsigned char _uint8_t; + +typedef signed short _int16_t; +typedef unsigned short _uint16_t; + +typedef signed long _int32_t; +typedef unsigned long _uint32_t; + +typedef signed long long _int64_t; +typedef unsigned long long _uint64_t; +#define __INT64_DEFINED + +typedef _int64_t _intmax_t; +typedef _uint64_t _uintmax_t; + +#if defined(__WCHAR_TYPE__) +typedef __WCHAR_TYPE__ _wchar_t; +#else +typedef int _wchar_t; +#endif + +/* A size is 4 bytes */ + +#if defined(__SIZE_TYPE__) +/* If __SIZE_TYPE__ is defined we define ssize_t based on size_t. + * We simply change "unsigned" to "signed" for this single definition + * to make sure ssize_t and size_t only differ by their signedness. + */ + +#define unsigned signed +typedef __SIZE_TYPE__ _ssize_t; +#undef unsigned +typedef __SIZE_TYPE__ _size_t; +#elif defined(CONFIG_ARCH_SIZET_LONG) +typedef signed long _ssize_t; +typedef unsigned long _size_t; +#else +typedef signed int _ssize_t; +typedef unsigned int _size_t; +#endif + +/* This is the size of the interrupt state save returned by irqsave(). */ + +typedef unsigned int irqstate_t; + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Global Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_TRICORE_INCLUDE_TYPES_H */ diff --git a/arch/tricore/src/.gitignore b/arch/tricore/src/.gitignore new file mode 100644 index 0000000000000..b7393142a4834 --- /dev/null +++ b/arch/tricore/src/.gitignore @@ -0,0 +1,3 @@ +/board +/chip +/*.S diff --git a/arch/tricore/src/Makefile b/arch/tricore/src/Makefile new file mode 100644 index 0000000000000..2b460ed7fc690 --- /dev/null +++ b/arch/tricore/src/Makefile @@ -0,0 +1,217 @@ +############################################################################ +# arch/tricore/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs +include chip/Make.defs + +ifeq ($(CONFIG_ARCH_TC3XX),y) +ARCH_SUBDIR = tc3xx +endif + +ARCH_SRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src + +INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip +INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)common +INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)$(ARCH_SUBDIR) +INCLUDES += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)sched + +CPPFLAGS += $(INCLUDES) +CFLAGS += $(INCLUDES) +CXXFLAGS += $(INCLUDES) +AFLAGS += $(INCLUDES) + +NUTTX = $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx$(EXEEXT)) + +# Additional rules for system call wrapper + +ifeq ($(CONFIG_SCHED_INSTRUMENTATION_SYSCALL),y) + EXTRALINKCMDS += @$(TOPDIR)/syscall/syscall_wraps.ldcmd +endif + +# The "head" object + +HEAD_COBJ = $(HEAD_CSRC:.c=$(OBJEXT)) +STARTUP_OBJS ?= $(HEAD_COBJ) + +# Flat build or kernel-mode objects + +ASRCS = $(CHIP_ASRCS) $(CMN_ASRCS) +AOBJS = $(ASRCS:.S=$(OBJEXT)) + +CSRCS = $(CHIP_CSRCS) $(CMN_CSRCS) +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +# User-mode objects + +UASRCS = $(CHIP_UASRCS) $(CMN_UASRCS) +UAOBJS = $(UASRCS:.S=$(OBJEXT)) + +UCSRCS = $(CHIP_UCSRCS) $(CMN_UCSRCS) +UCOBJS = $(UCSRCS:.c=$(OBJEXT)) + +USRCS = $(UASRCS) $(UCSRCS) +UOBJS = $(UAOBJS) $(UCOBJS) + +KBIN = libkarch$(LIBEXT) +BIN = libarch$(LIBEXT) + +$(foreach lib,$(notdir $(wildcard $(APPDIR)$(DELIM)staging$(DELIM)*$(LIBEXT))), \ + $(foreach elib,$(EXTRA_LIBS), \ + $(if $(filter $(notdir $(elib)),$(lib)), \ + $(eval NAMEFULL_LIBS+=$(elib)), \ + $(if $(filter $(notdir $(elib)),$(patsubst lib%$(LIBEXT),-l%,$(lib))), \ + $(eval NAMESPEC_LIBS+=$(elib)) \ + ) \ + ) \ + ) \ + ) + +EXTRA_LIBS := $(filter-out $(NAMEFULL_LIBS) $(NAMESPEC_LIBS),$(EXTRA_LIBS)) +EXTRA_LIBS += $(wildcard $(APPDIR)$(DELIM)staging$(DELIM)*$(LIBEXT)) + +LIBPATH_OPT = --library-directory= +SCRIPT_OPT = --lsl-file= +LIBRARY_OPT = -l + +LDFLAGS += $(addprefix $(SCRIPT_OPT),$(call CONVERT_PATH,$(ARCHSCRIPT))) $(EXTRALINKCMDS) +LIBPATHS += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)staging) + +BOARDMAKE = $(if $(wildcard board$(DELIM)Makefile),y,) +ifeq ($(BOARDMAKE),y) + LIBPATHS += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board) +endif + +LIBPATHS := $(addprefix $(LIBPATH_OPT),$(LIBPATHS)) + +LDLIBS = $(patsubst %.a,%,$(patsubst lib%,$(LIBRARY_OPT)%,$(LINKLIBS))) +ifeq ($(BOARDMAKE),y) + LDLIBS += $(LIBRARY_OPT)board +endif + +VPATH += chip +VPATH += common +VPATH += $(ARCH_SUBDIR) + +all: $(HEAD_COBJ) $(BIN) + +.PHONY: board$(DELIM)libboard$(LIBEXT) + +$(AOBJS) $(UAOBJS): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS) $(UCOBJS) $(HEAD_COBJ): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +ifeq ($(CONFIG_BUILD_FLAT),y) +$(BIN): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) +else +$(BIN): $(UOBJS) + $(call ARCHIVE, $@, $(UOBJS)) +endif + +$(KBIN): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + +board$(DELIM)libboard$(LIBEXT): + $(Q) $(MAKE) -C board libboard$(LIBEXT) EXTRAFLAGS="$(EXTRAFLAGS)" + +define LINK_ALLSYMS + $(Q) $(TOPDIR)/tools/mkallsyms.py $(NUTTX) allsyms.tmp --orderbyname $(CONFIG_SYMTAB_ORDEREDBYNAME) + $(Q) $(call COMPILE, allsyms.tmp, allsyms$(OBJEXT), -x c) + $(Q) $(LD) $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ + -o $(NUTTX) $(HEAD_COBJ) allsyms$(OBJEXT) $(EXTRA_OBJS) \ + $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) + $(Q) $(call DELFILE, allsyms.tmp allsyms$(OBJEXT)) +endef + +nuttx$(EXEEXT): $(HEAD_COBJ) board$(DELIM)libboard$(LIBEXT) $(ARCHSCRIPT) $(EXTRA_LIBS) + $(Q) echo "LD: nuttx" +ifneq ($(CONFIG_ALLSYMS),y) + $(Q) $(LD) $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ + -o $(NUTTX) $(HEAD_COBJ) $(EXTRA_OBJS) \ + $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LDENDGROUP) +else + $(Q) # Link and generate default table + $(Q) $(if $(wildcard $(shell echo $(NUTTX))),,$(call LINK_ALLSYMS,$^)) + $(Q) # Extract all symbols + $(Q) $(call LINK_ALLSYMS, $^) + $(Q) # Extract again since the table offset may changed + $(Q) $(call LINK_ALLSYMS, $^) +endif +ifneq ($(CONFIG_WINDOWS_NATIVE),y) + $(Q) $(NM) $(NUTTX) | \ + grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ + sort > $(TOPDIR)$(DELIM)System.map +endif + +# This is part of the top-level export target +# Note that there may not be a head object if layout is handled +# by the linker configuration. + +export_startup: $(STARTUP_OBJS) +ifneq ($(STARTUP_OBJS),) + $(Q) if [ -d "$(EXPORT_DIR)$(DELIM)startup" ]; then \ + cp -f $(STARTUP_OBJS) "$(EXPORT_DIR)$(DELIM)startup$(DELIM)."; \ + else \ + echo "$(EXPORT_DIR)$(DELIM)startup does not exist"; \ + exit 1; \ + fi +endif + +# Dependencies + +makedepfile: $(CSRCS:.c=.ddc) $(ASRCS:.S=.dds) + $(call CATFILE, Make.dep, $^) + $(call DELFILE, $^) + +.depend: Makefile chip$(DELIM)Make.defs $(SRCS) $(TOPDIR)$(DELIM).config +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board depend +endif + $(Q) $(MAKE) makedepfile DEPPATH="$(patsubst %,--dep-path %,$(subst :, ,$(VPATH)))" + $(Q) touch $@ + +depend: .depend + +context:: + +clean: +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board clean +endif + $(call DELFILE, $(KBIN)) + $(call DELFILE, $(BIN)) +ifneq ($(EXTRADELFILE),) + $(call DELFILE, $(EXTRADELFILE)) +endif + $(call CLEAN) + +distclean:: clean +ifeq ($(BOARDMAKE),y) + $(Q) $(MAKE) -C board distclean +endif + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +-include Make.dep diff --git a/arch/tricore/src/common/Ifx_Cfg_Trap.h b/arch/tricore/src/common/Ifx_Cfg_Trap.h new file mode 100644 index 0000000000000..4a6e702c7f0bc --- /dev/null +++ b/arch/tricore/src/common/Ifx_Cfg_Trap.h @@ -0,0 +1,60 @@ +/**************************************************************************** + * arch/tricore/src/common/Ifx_Cfg_Trap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_COMMON_IFX_CFG_TRAP_H +#define __ARCH_TRICORE_SRC_COMMON_IFX_CFG_TRAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "tricore_internal.h" + +#if (IFX_CFG_EXTEND_TRAP_HOOKS == 1) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Trap Hook defination */ + +/* Trap Call */ + +#define IFX_CFG_CPU_TRAP_TSR_HOOK(trapInfo) tricore_trapcall(&trapInfo) +#define IFX_CFG_CPU_TRAP_NMI_HOOK(trapInfo) tricore_trapcall(&trapInfo) +#define IFX_CFG_CPU_TRAP_MME_HOOK(trapInfo) tricore_trapcall(&trapInfo) +#define IFX_CFG_CPU_TRAP_IPE_HOOK(trapInfo) tricore_trapcall(&trapInfo) +#define IFX_CFG_CPU_TRAP_IE_HOOK(trapInfo) tricore_trapcall(&trapInfo) +#define IFX_CFG_CPU_TRAP_CME_HOOK(trapInfo) tricore_trapcall(&trapInfo) +#define IFX_CFG_CPU_TRAP_BE_HOOK(trapInfo) tricore_trapcall(&trapInfo) +#define IFX_CFG_CPU_TRAP_ASSERT_HOOK(trapInfo) tricore_trapcall(&trapInfo) + +#define IFX_CFG_CPU_TRAP_SYSCALL_CPU0_HOOK(trapWatch) tricore_svcall(&trapWatch) +#define IFX_CFG_CPU_TRAP_SYSCALL_CPU1_HOOK(trapWatch) tricore_svcall(&trapWatch) +#define IFX_CFG_CPU_TRAP_SYSCALL_CPU2_HOOK(trapWatch) tricore_svcall(&trapWatch) +#define IFX_CFG_CPU_TRAP_SYSCALL_CPU3_HOOK(trapWatch) tricore_svcall(&trapWatch) +#define IFX_CFG_CPU_TRAP_SYSCALL_CPU4_HOOK(trapWatch) tricore_svcall(&trapWatch) +#define IFX_CFG_CPU_TRAP_SYSCALL_CPU5_HOOK(trapWatch) tricore_svcall(&trapWatch) + +#endif /* IFX_CFG_EXTEND_TRAP_HOOKS */ + +#endif /* __ARCH_TRICORE_SRC_COMMON_IFX_CFG_TRAP_H */ diff --git a/arch/tricore/src/common/Make.defs b/arch/tricore/src/common/Make.defs new file mode 100644 index 0000000000000..ebb666ac171ce --- /dev/null +++ b/arch/tricore/src/common/Make.defs @@ -0,0 +1,54 @@ +############################################################################ +# arch/tricore/src/common/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +HEAD_CSRC += tricore_doirq.c + +CMN_CSRCS += tricore_allocateheap.c +CMN_CSRCS += tricore_checkstack.c +CMN_CSRCS += tricore_createstack.c +CMN_CSRCS += tricore_csa.c +CMN_CSRCS += tricore_exit.c +CMN_CSRCS += tricore_getintstack.c +CMN_CSRCS += tricore_idle.c +CMN_CSRCS += tricore_initialize.c +CMN_CSRCS += tricore_initialstate.c +CMN_CSRCS += tricore_irq.c +CMN_CSRCS += tricore_main.c +CMN_CSRCS += tricore_mdelay.c +CMN_CSRCS += tricore_nputs.c +CMN_CSRCS += tricore_registerdump.c +CMN_CSRCS += tricore_releasestack.c +CMN_CSRCS += tricore_saveusercontext.c +CMN_CSRCS += tricore_schedulesigaction.c +CMN_CSRCS += tricore_sigdeliver.c +CMN_CSRCS += tricore_stackframe.c +CMN_CSRCS += tricore_svcall.c +CMN_CSRCS += tricore_switchcontext.c +CMN_CSRCS += tricore_tcbinfo.c +CMN_CSRCS += tricore_trapcall.c +CMN_CSRCS += tricore_systimer.c +CMN_CSRCS += tricore_usestack.c + +ifeq ($(CONFIG_SPINLOCK),y) + CMN_CSRCS += tricore_testset.c +endif + +CFLAGS += -DIFX_CFG_EXTEND_TRAP_HOOKS +CFLAGS += -DIFX_USE_SW_MANAGED_INT diff --git a/arch/tricore/src/common/Toolchain.defs b/arch/tricore/src/common/Toolchain.defs new file mode 100644 index 0000000000000..895a8df48cbad --- /dev/null +++ b/arch/tricore/src/common/Toolchain.defs @@ -0,0 +1,127 @@ +############################################################################ +# arch/tricore/src/common/Toolchain.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# +# Supported toolchains +# +# Each toolchain definition should set: +# +# CROSSDEV The GNU toolchain triple (command prefix) +# ARCHCPUFLAGS CPU-specific flags selecting the instruction set +# FPU options, etc. +# ARCHOPTIMIZATION The optimization level that results in +# reliable code generation. +# + +ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) + ARCHOPTIMIZATION += $(CONFIG_DEBUG_OPTLEVEL) +else ifeq ($(CONFIG_DEBUG_FULLOPT),y) + ifeq ($(CONFIG_ARCH_TOOLCHAIN_CLANG),y) + ARCHOPTIMIZATION += -Oz + else + ARCHOPTIMIZATION += -Os + endif +endif + +# Tasking toolchain + +CC = cctc +CXX = cctc +CPP = cctc $(ARCHOPTIMIZATION) +LD = cctc +STRIP = strip --strip-unneeded +AR = artc -r +NM = nm +OBJCOPY = echo +OBJDUMP = elfdump + +ARCHOPTIMIZATION += --lsl-core=vtc +LDFLAGS += --lsl-core=vtc +ARCHOPTIMIZATION += --iso=99 +ARCHOPTIMIZATION += --language=+gcc,+volatile,-strings,-kanji + +# pragma align <4> (default: 0) + +ARCHOPTIMIZATION += --align=4 + +# Always use 32-bit integers for enumeration + +ARCHOPTIMIZATION += --integer-enumeration + +# tradeoff between speed (-t0) and size (-t4) (default: 4) + +ARCHOPTIMIZATION += --tradeoff=2 + +# enable symbolic debug information + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION += --debug-info=default + ARCHOPTIMIZATION += --keep-temporary-files + LDFLAGS += -g +endif + +# merge source code with assembly output + +ARCHOPTIMIZATION += --source + +# generate alignment depending on assume_if hints + +ARCHOPTIMIZATION += --branch-target-align + + +# Since nuttx uses too many of GNU extensions in the implementation of +# FPU-related library functions, which is not supported in tasking, +# so currently we cannot use FPU-related configurations to manage it. +# +# Just set fp-model to Double Precision: +# --fp-model[=,...] floating-point model (default: cFlnrSTz) +# 0 alias for --fp-model=CFLNRStZ (strict) +# 1 alias for --fp-model=cFLNRSTZ (precise) +# 2 alias for --fp-model=cFlnrSTz (fast-dp) +# 3 alias for --fp-model=cflnrSTz (fast-sp) + +ARCHOPTIMIZATION += --fp-model=2 +LDFLAGS += --fp-model=2 +LDFLAGS += -lfp_fpu + +LDFLAGS += --hex-format=s -Wl-OtxYcL -Wl-mcrfiklsmnoduq +LDFLAGS += -lrt + +# ctc W500: ["stdio/lib_libvsprintf.c" 884/29] expression without effect +# ctc W507: ["mm_heap/mm_malloc.c" 238/64] variable "nodesize" is possibly uninitialized +# ctc W508: ["misc/lib_impure.c" 1/1] empty source file +# ctc W525: ["getopt.c" 678/3] discarded 'const' qualifier at assignment: conversion from char const * to char * +# ctc W527: ["stdlib/lib_strtold.c" 565/23] constant of type "double" saturated +# ctc W526: ["include/sys/epoll.h" 87/5] enumeration constant shall be representable as 'int' +# ctc W529: ["wchar/lib_mbrtowc.c" 88/35] overflow in constant expression of type "unsigned long int" +# ctc W544: ["wqueue/kwork_thread.c" 210/32] unreachable code +# ctc W549: ["unistd/lib_getopt_common.c" 544/15] condition is always true +# ctc W553: ["vfs/fs_fcntl.c" 231/7] no 'break' or comment before case label +# ctc W557: ["common/tricore_main.c" 58/11] possible infinite loop +# ctc W560: ["tmpfs/fs_tmpfs.c" 232/25] possible truncation at implicit conversion to type "unsigned short int" +# ctc W562: ["mm_heap/mm_memalign.c" 70/20] unary minus applied to unsigned value +# ctc W558: ["include/nuttx/power/regulator.h" 224/36] struct/union/enum definition in parameter declaration +# ctc W587: ["stdlib/lib_strtold.c" 571/23] underflow on constant of type "double" +# ctc W588: ["misc/lib_glob.c" 150/13] dead assignment to "i" eliminated +# ctc W589: ["inode/fs_inodesearch.c" 72/8] pointer assumed to be nonzero - test removed + +TASKING_WARNINGS = 500,507,508,525,526,527,529,544,549,553,560,562,557,558,587,588,589 + +ARCHOPTIMIZATION += --pass-c=--no-warnings=$(TASKING_WARNINGS) diff --git a/arch/tricore/src/common/tricore_allocateheap.c b/arch/tricore/src/common/tricore_allocateheap.c new file mode 100644 index 0000000000000..c57de7d524d34 --- /dev/null +++ b/arch/tricore/src/common/tricore_allocateheap.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_allocateheap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "tricore_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_allocate_heap + * + * Description: + * This function will be called to dynamically set aside the heap region. + * + * For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and + * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the + * size of the unprotected, user-space heap. + * + * If a protected kernel-space heap is provided, the kernel heap must be + * allocated (and protected) by an analogous up_allocate_kheap(). + * + ****************************************************************************/ + +void up_allocate_heap(void **heap_start, size_t *heap_size) +{ + *heap_start = _edata; + *heap_size = (size_t)((uintptr_t)_eheap - (uintptr_t)_edata); +} diff --git a/arch/tricore/src/common/tricore_checkstack.c b/arch/tricore/src/common/tricore_checkstack.c new file mode 100644 index 0000000000000..f12fd84e4abbd --- /dev/null +++ b/arch/tricore/src/common/tricore_checkstack.c @@ -0,0 +1,152 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_checkstack.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "tricore_internal.h" + +#ifdef CONFIG_STACK_COLORATION + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tricore_stack_check + * + * Description: + * Determine (approximately) how much stack has been used be searching the + * stack memory for a high water mark. That is, the deepest level of the + * stack that clobbered some recognizable marker in the stack memory. + * + * Input Parameters: + * alloc - Allocation base address of the stack + * size - The size of the stack in bytes + * + * Returned Value: + * The estimated amount of stack space used. + * + ****************************************************************************/ + +size_t tricore_stack_check(uintptr_t alloc, size_t size) +{ + uintptr_t start; + uintptr_t end; + uint32_t *ptr; + size_t mark; + + if (size == 0) + { + return 0; + } + + /* Get aligned addresses of the top and bottom of the stack */ + + start = (alloc + 3) & ~3; + end = (alloc + size) & ~3; + + /* Get the adjusted size based on the top and bottom of the stack */ + + size = end - start; + + /* RISC-V uses a push-down stack: the stack grows toward lower addresses + * in memory. We need to start at the lowest address in the stack memory + * allocation and search to higher addresses. The first word we encounter + * that does not have the magic value is the high water mark. + */ + + for (ptr = (uint32_t *)start, mark = (size >> 2); + *ptr == STACK_COLOR && mark > 0; + ptr++, mark--); + + /* Return our guess about how much stack space was used */ + + return mark << 2; +} + +/**************************************************************************** + * Name: up_check_tcbstack and friends + * + * Description: + * Determine (approximately) how much stack has been used be searching the + * stack memory for a high water mark. That is, the deepest level of the + * stack that clobbered some recognizable marker in the stack memory. + * + * Input Parameters: + * None + * + * Returned Value: + * The estimated amount of stack space used. + * + ****************************************************************************/ + +size_t up_check_tcbstack(struct tcb_s *tcb) +{ + size_t size; + +#ifdef CONFIG_ARCH_ADDRENV + struct addrenv_s *oldenv; + + if (tcb->addrenv_own != NULL) + { + addrenv_select(tcb->addrenv_own, &oldenv); + } +#endif + + size = tricore_stack_check((uintptr_t)tcb->stack_base_ptr, + tcb->adj_stack_size); + +#ifdef CONFIG_ARCH_ADDRENV + if (tcb->addrenv_own != NULL) + { + addrenv_restore(oldenv); + } +#endif + + return size; +} + +#if CONFIG_ARCH_INTERRUPTSTACK > 15 +size_t up_check_intstack(void) +{ + return tricore_stack_check((uintptr_t)g_intstackalloc, + (CONFIG_ARCH_INTERRUPTSTACK & ~15)); +} +#endif + +#endif /* CONFIG_STACK_COLORATION */ diff --git a/arch/tricore/src/common/tricore_createstack.c b/arch/tricore/src/common/tricore_createstack.c new file mode 100644 index 0000000000000..f485c548a692b --- /dev/null +++ b/arch/tricore/src/common/tricore_createstack.c @@ -0,0 +1,247 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_createstack.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_create_stack + * + * Description: + * Allocate a stack for a new thread and setup up stack-related information + * in the TCB. + * + * The following TCB fields must be initialized by this function: + * + * - adj_stack_size: Stack size after adjustment for hardware, processor, + * etc. This value is retained only for debug purposes. + * - stack_alloc_ptr: Pointer to allocated stack + * - stack_base_ptr: Adjusted stack base pointer after the TLS Data and + * Arguments has been removed from the stack allocation. + * + * Input Parameters: + * - tcb: The TCB of new task + * - stack_size: The requested stack size. At least this much + * must be allocated. + * - ttype: The thread type. This may be one of following (defined in + * include/nuttx/sched.h): + * + * TCB_FLAG_TTYPE_TASK Normal user task + * TCB_FLAG_TTYPE_PTHREAD User pthread + * TCB_FLAG_TTYPE_KERNEL Kernel thread + * + * This thread type is normally available in the flags field of the TCB, + * however, there are certain contexts where the TCB may not be fully + * initialized when up_create_stack is called. + * + * If CONFIG_BUILD_KERNEL is defined, then this thread type may affect + * how the stack is allocated. For example, kernel thread stacks should + * be allocated from protected kernel memory. Stacks for user tasks and + * threads must come from memory that is accessible to user code. + * + ****************************************************************************/ + +int up_create_stack(struct tcb_s *tcb, size_t stack_size, uint8_t ttype) +{ +#ifdef CONFIG_TLS_ALIGNED + /* The allocated stack size must not exceed the maximum possible for the + * TLS feature. + */ + + DEBUGASSERT(stack_size <= TLS_MAXSTACK); + if (stack_size >= TLS_MAXSTACK) + { + stack_size = TLS_MAXSTACK; + } +#endif + + /* Is there already a stack allocated of a different size? Because of + * alignment issues, stack_size might erroneously appear to be of a + * different size. Fortunately, this is not a critical operation. + */ + + if (tcb->stack_alloc_ptr && tcb->adj_stack_size != stack_size) + { + /* Yes.. Release the old stack */ + + up_release_stack(tcb, ttype); + } + + /* Do we need to allocate a new stack? */ + + if (!tcb->stack_alloc_ptr) + { + /* Allocate the stack. If DEBUG is enabled (but not stack debug), + * then create a zeroed stack to make stack dumps easier to trace. + * If TLS is enabled, then we must allocate aligned stacks. + */ + +#ifdef CONFIG_TLS_ALIGNED +#ifdef CONFIG_MM_KERNEL_HEAP + /* Use the kernel allocator if this is a kernel thread */ + + if (ttype == TCB_FLAG_TTYPE_KERNEL) + { + tcb->stack_alloc_ptr = kmm_memalign(TLS_STACK_ALIGN, stack_size); + } + else +#endif + { + /* Use the user-space allocator if this is a task or pthread */ + + tcb->stack_alloc_ptr = kumm_memalign(TLS_STACK_ALIGN, stack_size); + } + +#else /* CONFIG_TLS_ALIGNED */ +#ifdef CONFIG_MM_KERNEL_HEAP + /* Use the kernel allocator if this is a kernel thread */ + + if (ttype == TCB_FLAG_TTYPE_KERNEL) + { + tcb->stack_alloc_ptr = kmm_malloc(stack_size); + } + else +#endif + { + /* Use the user-space allocator if this is a task or pthread */ + + tcb->stack_alloc_ptr = kumm_malloc(stack_size); + } +#endif /* CONFIG_TLS_ALIGNED */ + +#ifdef CONFIG_DEBUG_FEATURES + /* Was the allocation successful? */ + + if (!tcb->stack_alloc_ptr) + { + serr("ERROR: Failed to allocate stack, size %zu\n", stack_size); + } +#endif + } + + /* Did we successfully allocate a stack? */ + + if (tcb->stack_alloc_ptr) + { + uintptr_t top_of_stack; + size_t size_of_stack; + + /* RISC-V uses a push-down stack: the stack grows toward lower + * addresses in memory. The stack pointer register points to the + * lowest, valid working address (the "top" of the stack). Items on + * the stack are referenced as positive word offsets from SP. + */ + + top_of_stack = (uintptr_t)tcb->stack_alloc_ptr + stack_size; + + /* The RISC-V stack must be aligned at 128-bit (16-byte) boundaries. + * If necessary top_of_stack must be rounded down to the next boundary. + */ + + top_of_stack = STACK_ALIGN_DOWN(top_of_stack); + size_of_stack = top_of_stack - (uintptr_t)tcb->stack_alloc_ptr; + + /* Save the adjusted stack values in the struct tcb_s */ + + tcb->stack_base_ptr = tcb->stack_alloc_ptr; + tcb->adj_stack_size = size_of_stack; + +#ifdef CONFIG_STACK_COLORATION + /* If stack debug is enabled, then fill the stack with a + * recognizable value that we can use later to test for high + * water marks. + */ + + tricore_stack_color(tcb->stack_base_ptr, tcb->adj_stack_size); + +#endif /* CONFIG_STACK_COLORATION */ + tcb->flags |= TCB_FLAG_FREE_STACK; + + return OK; + } + + return ERROR; +} + +/**************************************************************************** + * Name: tricore_stack_color + * + * Description: + * Write a well know value into the stack + * + ****************************************************************************/ + +#ifdef CONFIG_STACK_COLORATION +void tricore_stack_color(void *stackbase, size_t nbytes) +{ + uint32_t *stkptr; + uintptr_t stkend; + size_t nwords; + uintptr_t sp; + + /* Take extra care that we do not write outside the stack boundaries */ + + stkptr = (uint32_t *)STACK_ALIGN_UP((uintptr_t)stackbase); + + if (nbytes == 0) /* 0: colorize the running stack */ + { + stkend = up_getsp(); + if (stkend > (uintptr_t)&sp) + { + stkend = (uintptr_t)&sp; + } + } + else + { + stkend = (uintptr_t)stackbase + nbytes; + } + + stkend = STACK_ALIGN_DOWN(stkend); + nwords = (stkend - (uintptr_t)stkptr) >> 2; + + /* Set the entire stack to the coloration value */ + + while (nwords-- > 0) + { + *stkptr++ = STACK_COLOR; + } +} +#endif diff --git a/arch/tricore/src/common/tricore_csa.c b/arch/tricore/src/common/tricore_csa.c new file mode 100644 index 0000000000000..cec39ccb8a1af --- /dev/null +++ b/arch/tricore/src/common/tricore_csa.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_csa.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "tricore_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tricore_alloc_csa + ****************************************************************************/ + +uintptr_t *tricore_alloc_csa(uintptr_t pc, uintptr_t sp, + uintptr_t psw, bool irqsave) +{ + uintptr_t *plcsa; + uintptr_t *pucsa; + + plcsa = (uintptr_t *)tricore_csa2addr(__mfcr(CPU_FCX)); + + pucsa = (uintptr_t *)tricore_csa2addr(plcsa[REG_UPCXI]); + + __mtcr(CPU_FCX, pucsa[REG_UPCXI]); + + memset(pucsa, 0, XCPTCONTEXT_SIZE); + memset(plcsa, 0, XCPTCONTEXT_SIZE); + + pucsa[REG_SP] = sp; + pucsa[REG_PSW] = psw; + + /* Save the task entry point */ + + pucsa[REG_UPC] = pc; + plcsa[REG_LPC] = pc; + + plcsa[REG_LPCXI] = (PCXI_UL | tricore_addr2csa(pucsa)); + + if (!irqsave) + { + plcsa[REG_LPCXI] |= PCXI_PIE; + } + + return (uintptr_t *)tricore_addr2csa(plcsa); +} + +/**************************************************************************** + * Name: tricore_reclaim_csa + ****************************************************************************/ + +void tricore_reclaim_csa(uintptr_t pcxi) +{ + uintptr_t head, tail, free; + uintptr_t *next; + + /* A pointer to the first CSA in the list of CSAs consumed by the task is + * stored in the first element of the tasks TCB structure (where the stack + * pointer would be on a traditional stack based architecture). + */ + + head = pcxi & FCX_FREE; + + /* Mask off everything in the CSA link field other than the address. If + * the address is NULL, then the CSA is not linking anywhere and there is + * nothing to do. + */ + + tail = head; + + /* Convert the link value to contain just a raw address and store this + * in a local variable. + */ + + next = tricore_csa2addr(tail); + + /* Iterate over the CSAs that were consumed as part of the task. The + * first field in the CSA is the pointer to then next CSA. Mask off + * everything in the pointer to the next CSA, other than the link address. + * If this is NULL, then the CSA currently being pointed to is the last in + * the chain. + */ + + while ((next[0] & FCX_FREE) != 0) + { + /* Clear all bits of the pointer to the next in the chain, other + * than the address bits themselves. + */ + + next[0] = next[0] & FCX_FREE; + + /* Move the pointer to point to the next CSA in the list. */ + + tail = next[0]; + + /* Update the local pointer to the CSA. */ + + next = tricore_csa2addr(tail); + } + + /* Look up the current free CSA head. */ + + free = __mfcr(CPU_FCX); + + /* Join the current Free onto the Tail of what is being reclaimed. */ + + tricore_csa2addr(tail)[0] = free; + + /* Move the head of the reclaimed into the Free. */ + + __mtcr(CPU_FCX, head); +} diff --git a/arch/tricore/src/common/tricore_doirq.c b/arch/tricore/src/common/tricore_doirq.c new file mode 100644 index 0000000000000..79224336a5f71 --- /dev/null +++ b/arch/tricore/src/common/tricore_doirq.c @@ -0,0 +1,110 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_doirq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include + +#include + +#include "tricore_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +IFX_INTERRUPT_INTERNAL(tricore_doirq, 0, 255) +{ +#ifdef CONFIG_SUPPRESS_INTERRUPTS + PANIC(); +#else + Ifx_CPU_ICR icr; + uintptr_t *regs; + + icr.U = __mfcr(CPU_ICR); + regs = (uintptr_t *)__mfcr(CPU_PCXI); + + board_autoled_on(LED_INIRQ); + + /* Nested interrupts are not supported */ + + DEBUGASSERT(CURRENT_REGS == NULL); + + /* Current regs non-zero indicates that we are processing an interrupt; + * CURRENT_REGS is also used to manage interrupt level context switches. + */ + + CURRENT_REGS = regs; + + /* Deliver the IRQ */ + + irq_dispatch(icr.B.CCPN, regs); + + /* Check for a context switch. If a context switch occurred, then + * CURRENT_REGS will have a different value than it did on entry. If an + * interrupt level context switch has occurred, then restore the floating + * point state and the establish the correct address environment before + * returning from the interrupt. + */ + + if (regs != CURRENT_REGS) + { +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + addrenv_switch(NULL); +#endif + + /* Record the new "running" task when context switch occurred. + * g_running_tasks[] is only used by assertion logic for reporting + * crashes. + */ + + g_running_tasks[this_cpu()] = this_task(); + + __mtcr(CPU_PCXI, (uintptr_t)CURRENT_REGS); + __isync(); + } + + /* Set CURRENT_REGS to NULL to indicate that we are no longer in an + * interrupt handler. + */ + + CURRENT_REGS = NULL; + + board_autoled_off(LED_INIRQ); +#endif +} diff --git a/arch/tricore/src/common/tricore_exit.c b/arch/tricore/src/common/tricore_exit.c new file mode 100644 index 0000000000000..9243021ba8442 --- /dev/null +++ b/arch/tricore/src/common/tricore_exit.c @@ -0,0 +1,92 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_exit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "task/task.h" +#include "sched/sched.h" +#include "group/group.h" +#include "tricore_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_exit + * + * Description: + * This function causes the currently executing task to cease + * to exist. This is a special case of task_delete() where the task to + * be deleted is the currently executing task. It is more complex because + * a context switch must be perform to the next ready to run task. + * + ****************************************************************************/ + +void up_exit(int status) +{ + struct tcb_s *tcb = this_task(); + + /* Make sure that we are in a critical section with local interrupts. + * The IRQ state will be restored when the next task is started. + */ + + enter_critical_section(); + + nxsched_dumponexit(); + + /* Destroy the task at the head of the ready to run list. */ + + nxtask_exit(); + + /* Now, perform the context switch to the new ready-to-run task at the + * head of the list. + */ + + tcb = this_task(); + + /* Adjusts time slice for SCHED_RR & SCHED_SPORADIC cases + * NOTE: the API also adjusts the global IRQ control for SMP + */ + + nxsched_resume_scheduler(tcb); + + /* Then switch contexts */ + + tricore_fullcontextrestore(tcb->xcp.regs); + + /* tricore_fullcontextrestore() should not return but could if the software + * interrupts are disabled. + */ + + PANIC(); +} diff --git a/arch/tricore/src/common/tricore_getintstack.c b/arch/tricore/src/common/tricore_getintstack.c new file mode 100644 index 0000000000000..9fca8b9eaa664 --- /dev/null +++ b/arch/tricore/src/common/tricore_getintstack.c @@ -0,0 +1,44 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_getintstack.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "tricore_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_get_intstackbase + ****************************************************************************/ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 +uintptr_t up_get_intstackbase(void) +{ + return (uintptr_t)g_intstackalloc; +} +#endif diff --git a/arch/tricore/src/common/tricore_idle.c b/arch/tricore/src/common/tricore_idle.c new file mode 100644 index 0000000000000..0ec6062c5c8bf --- /dev/null +++ b/arch/tricore/src/common/tricore_idle.c @@ -0,0 +1,74 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_idle.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +#include "tricore_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_idle + * + * Description: + * up_idle() is the logic that will be executed when there is no other + * ready-to-run task. This is processor idle time and will continue until + * some interrupt occurs to cause a context switch from the idle task. + * + * Processing in this state may be processor-specific. e.g., this is where + * power management operations might be performed. + * + ****************************************************************************/ + +void up_idle(void) +{ +#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS) + /* If the system is idle and there are no timer interrupts, then process + * "fake" timer interrupts. Hopefully, something will wake up. + */ + + nxsched_process_timer(); +#else + + /* Does the board support an IDLE LED to indicate that the board is in the + * IDLE state? + */ + +#ifdef CONFIG_ARCH_LEDS_CPU_ACTIVITY + board_autoled_off(LED_CPU); +#endif + + /* This would be an appropriate place to put some MCU-specific logic to + * sleep in a reduced power mode until an interrupt occurs to save power + */ + + Ifx_Ssw_infiniteLoop(); +#endif +} diff --git a/arch/tricore/src/common/tricore_initialize.c b/arch/tricore/src/common/tricore_initialize.c new file mode 100644 index 0000000000000..1ee4f419dce8d --- /dev/null +++ b/arch/tricore/src/common/tricore_initialize.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_initialize.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "tricore_internal.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile uintptr_t *g_current_regs[CONFIG_SMP_NCPUS]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_color_intstack + * + * Description: + * Set the interrupt stack to a value so that later we can determine how + * much stack space was used by interrupt handling logic + * + ****************************************************************************/ + +#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 15 +static inline void up_color_intstack(void) +{ + uint32_t *ptr = (uint32_t *)g_intstackalloc; + ssize_t size; + + for (size = (CONFIG_ARCH_INTERRUPTSTACK & ~15); + size > 0; + size -= sizeof(uint32_t)) + { + *ptr++ = INTSTACK_COLOR; + } +} +#else +# define up_color_intstack() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_initialize + * + * Description: + * up_initialize will be called once during OS initialization after the + * basic OS services have been initialized. The architecture specific + * details of initializing the OS will be handled here. Such things as + * setting up interrupt service routines, starting the clock, and + * registering device drivers are some of the things that are different + * for each processor and hardware platform. + * + * up_initialize is called after the OS initialized but before the user + * initialization logic has been started and before the libraries have + * been initialized. OS services and driver services are available. + * + ****************************************************************************/ + +void up_initialize(void) +{ + /* Colorize the interrupt stack */ + + up_color_intstack(); + + /* Initialize the serial device driver */ + +#ifdef USE_SERIALDRIVER + tricore_serialinit(); +#endif +} diff --git a/arch/tricore/src/common/tricore_initialstate.c b/arch/tricore/src/common/tricore_initialstate.c new file mode 100644 index 0000000000000..f7d394c24f016 --- /dev/null +++ b/arch/tricore/src/common/tricore_initialstate.c @@ -0,0 +1,87 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_initialstate.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "tricore_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_initial_state + * + * Description: + * A new thread is being started and a new TCB + * has been created. This function is called to initialize + * the processor specific portions of the new TCB. + * + * This function must setup the initial architecture registers + * and/or stack so that execution will begin at tcb->start + * on the next context switch. + * + ****************************************************************************/ + +void up_initial_state(struct tcb_s *tcb) +{ + struct xcptcontext *xcp = &tcb->xcp; + + /* Initialize the initial exception register context structure */ + + memset(xcp, 0, sizeof(struct xcptcontext)); + + /* Initialize the idle thread stack */ + + if (tcb->pid == IDLE_PROCESS_ID) + { + tcb->stack_alloc_ptr = (void *)((uintptr_t)g_idle_topstack - + CONFIG_IDLETHREAD_STACKSIZE); + tcb->stack_base_ptr = tcb->stack_alloc_ptr; + tcb->adj_stack_size = CONFIG_IDLETHREAD_STACKSIZE; + +#ifdef CONFIG_STACK_COLORATION + /* If stack debug is enabled, then fill the stack with a + * recognizable value that we can use later to test for high + * water marks. + */ + + tricore_stack_color(tcb->stack_alloc_ptr, 0); +#endif /* CONFIG_STACK_COLORATION */ + return; + } + + xcp->regs = tricore_alloc_csa((uintptr_t)tcb->start, + (uintptr_t)tcb->stack_base_ptr + + tcb->adj_stack_size, + PSW_IO_SUPERVISOR | PSW_CDE, false); +} diff --git a/arch/tricore/src/common/tricore_internal.h b/arch/tricore/src/common/tricore_internal.h new file mode 100644 index 0000000000000..e306f787a73a0 --- /dev/null +++ b/arch/tricore/src/common/tricore_internal.h @@ -0,0 +1,252 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_internal.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_COMMON_TRICORE_INTERNAL_H +#define __ARCH_TRICORE_SRC_COMMON_TRICORE_INTERNAL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +# include +# include +# include + +# include +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Determine which (if any) console driver to use. If a console is enabled + * and no other console device is specified, then a serial console is + * assumed. + */ + +#ifndef CONFIG_DEV_CONSOLE +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +#else +# if defined(CONFIG_LWL_CONSOLE) +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# elif defined(CONFIG_CONSOLE_SYSLOG) +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# elif defined(CONFIG_SERIAL_RTT_CONSOLE) +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# elif defined(CONFIG_RPMSG_UART_CONSOLE) +# undef USE_SERIALDRIVER +# undef USE_EARLYSERIALINIT +# else +# define USE_SERIALDRIVER 1 +# define USE_EARLYSERIALINIT 1 +# endif +#endif + +/* If some other device is used as the console, then the serial driver may + * still be needed. Let's assume that if the upper half serial driver is + * built, then the lower half will also be needed. There is no need for + * the early serial initialization in this case. + */ + +#if !defined(USE_SERIALDRIVER) && defined(CONFIG_STANDARD_SERIAL) +# define USE_SERIALDRIVER 1 +#endif + +/* For use with EABI and floating point, the stack must be aligned to 8-byte + * addresses. + */ + +#define STACK_ALIGNMENT 8 + +/* Stack alignment macros */ + +#define STACK_ALIGN_MASK (STACK_ALIGNMENT - 1) +#define STACK_ALIGN_DOWN(a) ((a) & ~STACK_ALIGN_MASK) +#define STACK_ALIGN_UP(a) (((a) + STACK_ALIGN_MASK) & ~STACK_ALIGN_MASK) + +/* Check if an interrupt stack size is configured */ + +#ifndef CONFIG_ARCH_INTERRUPTSTACK +# define CONFIG_ARCH_INTERRUPTSTACK 0 +#endif + +#define INTSTACK_SIZE (CONFIG_ARCH_INTERRUPTSTACK & ~STACK_ALIGN_MASK) + +/* This is the value used to mark the stack for subsequent stack monitoring + * logic. + */ + +#define STACK_COLOR 0xdeadbeef +#define INTSTACK_COLOR 0xdeadbeef +#define HEAP_COLOR 'h' + +#define getreg8(a) (*(volatile uint8_t *)(a)) +#define putreg8(v,a) (*(volatile uint8_t *)(a) = (v)) +#define getreg16(a) (*(volatile uint16_t *)(a)) +#define putreg16(v,a) (*(volatile uint16_t *)(a) = (v)) +#define getreg32(a) (*(volatile uint32_t *)(a)) +#define putreg32(v,a) (*(volatile uint32_t *)(a) = (v)) +#define getreg64(a) (*(volatile uint64_t *)(a)) +#define putreg64(v,a) (*(volatile uint64_t *)(a) = (v)) + +/* Non-atomic, but more effective modification of registers */ + +#define modreg8(v,m,a) putreg8((getreg8(a) & ~(m)) | ((v) & (m)), (a)) +#define modreg16(v,m,a) putreg16((getreg16(a) & ~(m)) | ((v) & (m)), (a)) +#define modreg32(v,m,a) putreg32((getreg32(a) & ~(m)) | ((v) & (m)), (a)) +#define modreg64(v,m,a) putreg64((getreg64(a) & ~(m)) | ((v) & (m)), (a)) + +/* Context switching */ + +#ifndef tricore_fullcontextrestore +# define tricore_fullcontextrestore(restoreregs) \ + sys_call1(SYS_restore_context, (uintptr_t)restoreregs); +#else +extern void tricore_fullcontextrestore(uintptr_t *restoreregs); +#endif + +#ifndef tricore_switchcontext +# define tricore_switchcontext(saveregs, restoreregs) \ + sys_call2(SYS_switch_context, (uintptr_t)saveregs, (uintptr_t)restoreregs); +#else +extern void tricore_switchcontext(uintptr_t **saveregs, + uintptr_t *restoreregs); +#endif + +/* Address <--> Context Save Areas */ + +#define tricore_csa2addr(csa) ((uintptr_t *)((((csa) & 0x000F0000) << 12) \ + | (((csa) & 0x0000FFFF) << 6))) +#define tricore_addr2csa(addr) ((uintptr_t)(((((uintptr_t)(addr)) & 0xF0000000) >> 12) \ + | (((uintptr_t)(addr) & 0x003FFFC0) >> 6))) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +typedef void (*up_vector_t)(void); +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* This is the beginning of heap as provided from up_head.S. This is the + * first address in DRAM after the loaded program+bss+idle stack. The + * end of the heap is CONFIG_RAM_END + */ + +extern uintptr_t __USTACK0_END[]; +extern uintptr_t __USTACK0[]; +#define g_idle_topstack __USTACK0 + +/* Address of the saved user stack pointer */ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 +extern uintptr_t __ISTACK0_END[]; +extern uintptr_t __ISTACK0[]; +#define g_intstackalloc __ISTACK0_END +#define g_intstacktop __ISTACK0 +#endif + +/* These symbols are setup by the linker script. */ + +extern uintptr_t _lc_gb_data[]; /* Start of .data */ +extern uintptr_t _lc_ge_data[]; /* End+1 of .data */ +#define _sdata _lc_gb_data +#define _edata _lc_ge_data +#define _eheap __USTACK0_END +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#define tricore_savecontext(regs) (regs = (uintptr_t *)CURRENT_REGS) +#define tricore_restorecontext(regs) (CURRENT_REGS = regs) + +/* Macros to handle saving and restoring interrupt state. */ + +#define tricore_savestate(regs) (regs = (uintptr_t *)CURRENT_REGS) +#define tricore_restorestate(regs) (CURRENT_REGS = regs) + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/* Signal handling **********************************************************/ + +void tricore_sigdeliver(void); + +/* Exception Handler ********************************************************/ + +void tricore_svcall(volatile void *trap); +void tricore_trapcall(volatile void *trap); + +/* Context Save Areas *******************************************************/ + +uintptr_t *tricore_alloc_csa(uintptr_t pc, uintptr_t sp, + uintptr_t psw, bool irqsave); +void tricore_reclaim_csa(uintptr_t pcxi); + +/* Low level serial output **************************************************/ + +void tricore_lowputc(char ch); +void tricore_lowputs(const char *str); + +#ifdef USE_SERIALDRIVER +void tricore_serialinit(void); +#endif + +#ifdef USE_EARLYSERIALINIT +void tricore_earlyserialinit(void); +#endif + +/* System Timer *************************************************************/ + +struct oneshot_lowerhalf_s * +tricore_systimer_initialize(void *tbase, int irq, uint64_t freq); + +/* Debug ********************************************************************/ + +#ifdef CONFIG_STACK_COLORATION +size_t tricore_stack_check(uintptr_t alloc, size_t size); +void tricore_stack_color(void *stackbase, size_t nbytes); +#endif + +#endif /* __ARCH_TRICORE_SRC_COMMON_TRICORE_INTERNAL_H */ diff --git a/arch/tricore/src/common/tricore_irq.c b/arch/tricore/src/common/tricore_irq.c new file mode 100644 index 0000000000000..6c87de493ba14 --- /dev/null +++ b/arch/tricore/src/common/tricore_irq.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_irq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "tricore_internal.h" + +#include "IfxSrc.h" +#include "IfxCpu.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irq_enable + * + * Description: + * Enable interrupts globally. + * + ****************************************************************************/ + +void up_irq_enable(void) +{ + IfxCpu_enableInterrupts(); +} + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + up_irq_enable(); +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + volatile Ifx_SRC_SRCR *src = &SRC_CPU_CPU0_SB + irq; + + IfxSrc_disable(src); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + volatile Ifx_SRC_SRCR *src = &SRC_CPU_CPU0_SB + irq; + + IfxSrc_init(src, IfxSrc_Tos_cpu0, irq); + IfxSrc_enable(src); +} + +/**************************************************************************** + * Name: tricore_ack_irq + * + * Description: + * Acknowledge the IRQ + * + ****************************************************************************/ + +void tricore_ack_irq(int irq) +{ +} diff --git a/arch/tricore/src/common/tricore_main.c b/arch/tricore/src/common/tricore_main.c new file mode 100644 index 0000000000000..b62107cd0509f --- /dev/null +++ b/arch/tricore/src/common/tricore_main.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_main.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "Ifx_Types.h" +#include "IfxScuWdt.h" +#include "IfxCpu.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void core_main(void) +{ + static IfxCpu_syncEvent g_sync_event = 0; + + /* !!WATCHDOG0 AND SAFETY WATCHDOG ARE DISABLED HERE!! + * Enable the watchdogs and service them periodically if it is required + */ + + IfxScuWdt_disableCpuWatchdog(IfxScuWdt_getCpuWatchdogPassword()); + IfxScuWdt_disableSafetyWatchdog(IfxScuWdt_getSafetyWatchdogPassword()); + + /* Wait for CPU sync event */ + + IfxCpu_emitEvent(&g_sync_event); + IfxCpu_waitEvent(&g_sync_event, 1); + + if (IfxCpu_getCoreIndex() == 0) + { + tricore_earlyserialinit(); + nx_start(); + } + + while (1); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void core0_main(void) +{ + core_main(); +} + +void core1_main(void) +{ + core_main(); +} + +void core2_main(void) +{ + core_main(); +} + +void core3_main(void) +{ + core_main(); +} + +void core4_main(void) +{ + core_main(); +} + +void core5_main(void) +{ + core_main(); +} diff --git a/arch/tricore/src/common/tricore_mdelay.c b/arch/tricore/src/common/tricore_mdelay.c new file mode 100644 index 0000000000000..57c5f4c3822de --- /dev/null +++ b/arch/tricore/src/common/tricore_mdelay.c @@ -0,0 +1,55 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_mdelay.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_mdelay + * + * Description: + * Delay inline for the requested number of milliseconds. + * *** NOT multi-tasking friendly *** + * + * ASSUMPTIONS: + * The setting CONFIG_BOARD_LOOPSPERMSEC has been calibrated + * + ****************************************************************************/ + +void up_mdelay(unsigned int milliseconds) +{ + volatile unsigned int i; + volatile unsigned int j; + + for (i = 0; i < milliseconds; i++) + { + for (j = 0; j < CONFIG_BOARD_LOOPSPERMSEC; j++) + { + } + } +} diff --git a/arch/tricore/src/common/tricore_nputs.c b/arch/tricore/src/common/tricore_nputs.c new file mode 100644 index 0000000000000..421e2b9f893b3 --- /dev/null +++ b/arch/tricore/src/common/tricore_nputs.c @@ -0,0 +1,46 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_nputs.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_nputs + * + * Description: + * This is a low-level helper function used to support debug. + * + ****************************************************************************/ + +void up_nputs(const char *str, size_t len) +{ + while (len-- > 0 && *str) + { + up_putc(*str++); + } +} diff --git a/arch/tricore/src/common/tricore_registerdump.c b/arch/tricore/src/common/tricore_registerdump.c new file mode 100644 index 0000000000000..e1dcddfe1e1d0 --- /dev/null +++ b/arch/tricore/src/common/tricore_registerdump.c @@ -0,0 +1,65 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_registerdump.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "tricore_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_getusrsp + ****************************************************************************/ + +uintptr_t up_getusrsp(void *regs) +{ + uintptr_t *csa = regs; + + while (((uintptr_t)csa & PCXI_UL) == 0) + { + csa = tricore_csa2addr((uintptr_t)csa); + csa = (uintptr_t *)csa[0]; + } + + csa = tricore_csa2addr((uintptr_t)csa); + + return csa[REG_SP]; +} + +/**************************************************************************** + * Name: up_dump_register + ****************************************************************************/ + +void up_dump_register(void *dumpregs) +{ +} diff --git a/arch/tricore/src/common/tricore_releasestack.c b/arch/tricore/src/common/tricore_releasestack.c new file mode 100644 index 0000000000000..28f4da8cb0745 --- /dev/null +++ b/arch/tricore/src/common/tricore_releasestack.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_releasestack.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "tricore_internal.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_release_stack + * + * Description: + * A task has been stopped. Free all stack related resources retained in + * the defunct TCB. + * + * Input Parameters: + * - dtcb: The TCB containing information about the stack to be released + * - ttype: The thread type. This may be one of following (defined in + * include/nuttx/sched.h): + * + * TCB_FLAG_TTYPE_TASK Normal user task + * TCB_FLAG_TTYPE_PTHREAD User pthread + * TCB_FLAG_TTYPE_KERNEL Kernel thread + * + * This thread type is normally available in the flags field of the TCB, + * however, there are certain error recovery contexts where the TCB may + * not be fully initialized when up_release_stack is called. + * + * If CONFIG_BUILD_KERNEL is defined, then this thread type may affect + * how the stack is freed. For example, kernel thread stacks may have + * been allocated from protected kernel memory. Stacks for user tasks + * and threads must have come from memory that is accessible to user + * code. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_release_stack(struct tcb_s *dtcb, uint8_t ttype) +{ + /* Is there a stack allocated? */ + + if (dtcb->stack_alloc_ptr && (dtcb->flags & TCB_FLAG_FREE_STACK)) + { +#ifdef CONFIG_MM_KERNEL_HEAP + /* Use the kernel allocator if this is a kernel thread */ + + if (ttype == TCB_FLAG_TTYPE_KERNEL) + { + kmm_free(dtcb->stack_alloc_ptr); + } + else +#endif + { + /* Use the user-space allocator if this is a task or pthread */ + + kumm_free(dtcb->stack_alloc_ptr); + } + } + + /* Mark the stack freed */ + + dtcb->flags &= ~TCB_FLAG_FREE_STACK; + dtcb->stack_alloc_ptr = NULL; + dtcb->stack_base_ptr = NULL; + dtcb->adj_stack_size = 0; +} diff --git a/arch/tricore/src/common/tricore_saveusercontext.c b/arch/tricore/src/common/tricore_saveusercontext.c new file mode 100644 index 0000000000000..6b9d6b0853b1d --- /dev/null +++ b/arch/tricore/src/common/tricore_saveusercontext.c @@ -0,0 +1,50 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_saveusercontext.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "tricore_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_saveusercontext + * + * Description: + * Save the current thread context + * + ****************************************************************************/ + +int up_saveusercontext(void *saveregs) +{ + uintptr_t *regs = tricore_csa2addr(__mfcr(CPU_PCXI)); + memcpy(saveregs, regs, XCPTCONTEXT_SIZE); + return 0; +} diff --git a/arch/tricore/src/common/tricore_schedulesigaction.c b/arch/tricore/src/common/tricore_schedulesigaction.c new file mode 100644 index 0000000000000..cde5214005b89 --- /dev/null +++ b/arch/tricore/src/common/tricore_schedulesigaction.c @@ -0,0 +1,162 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_schedulesigaction.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "tricore_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_schedule_sigaction + * + * Description: + * This function is called by the OS when one or more + * signal handling actions have been queued for execution. + * The architecture specific code must configure things so + * that the 'sigdeliver' callback is executed on the thread + * specified by 'tcb' as soon as possible. + * + * This function may be called from interrupt handling logic. + * + * This operation should not cause the task to be unblocked + * nor should it cause any immediate execution of sigdeliver. + * Typically, a few cases need to be considered: + * + * (1) This function may be called from an interrupt handler + * During interrupt processing, all xcptcontext structures + * should be valid for all tasks. That structure should + * be modified to invoke sigdeliver() either on return + * from (this) interrupt or on some subsequent context + * switch to the recipient task. + * (2) If not in an interrupt handler and the tcb is NOT + * the currently executing task, then again just modify + * the saved xcptcontext structure for the recipient + * task so it will invoke sigdeliver when that task is + * later resumed. + * (3) If not in an interrupt handler and the tcb IS the + * currently executing task -- just call the signal + * handler now. + * + * Assumptions: + * Called from critical section + * + ****************************************************************************/ + +void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) +{ + /* Refuse to handle nested signal actions */ + + if (tcb->xcp.sigdeliver == NULL) + { + tcb->xcp.sigdeliver = sigdeliver; + + /* First, handle some special cases when the signal is + * being delivered to the currently executing task. + */ + + if (tcb == this_task()) + { + /* CASE 1: We are not in an interrupt handler and + * a task is signalling itself for some reason. + */ + + if (CURRENT_REGS == NULL) + { + /* In this case just deliver the signal now. */ + + sigdeliver(tcb); + tcb->xcp.sigdeliver = NULL; + } + + /* CASE 2: We are in an interrupt handler AND the + * interrupted task is the same as the one that + * must receive the signal, then we will have to modify + * the return state as well as the state in the TCB. + * + * Hmmm... there looks like a latent bug here: The following + * logic would fail in the strange case where we are in an + * interrupt handler, the thread is signalling itself, but + * a context switch to another task has occurred so that + * CURRENT_REGS does not refer to the thread of this_task()! + */ + + else + { + /* Save the context registers. These will be + * restored by the signal trampoline after the signals have + * been delivered. + */ + + tricore_savestate(tcb->xcp.saved_regs); + + /* Create a new CSA for signal delivery. The new context + * will borrow the process stack of the current tcb. + */ + + CURRENT_REGS = tricore_alloc_csa((uintptr_t)tricore_sigdeliver, + STACK_ALIGN_DOWN(up_getusrsp(tcb->xcp.regs)), + PSW_IO_SUPERVISOR | PSW_CDE, true); + } + } + + /* Otherwise, we are (1) signaling a task is not running + * from an interrupt handler or (2) we are not in an + * interrupt handler and the running task is signalling + * some non-running task. + */ + + else + { + /* Save the return EPC and STATUS registers. These will be + * restored by the signal trampoline after the signals have + * been delivered. + */ + + /* Save the current register context location */ + + tcb->xcp.saved_regs = tcb->xcp.regs; + + /* Create a new CSA for signal delivery. The new context + * will borrow the process stack of the current tcb. + */ + + tcb->xcp.regs = tricore_alloc_csa((uintptr_t)tricore_sigdeliver, + STACK_ALIGN_DOWN(up_getusrsp(tcb->xcp.regs)), + PSW_IO_SUPERVISOR | PSW_CDE, true); + } + } +} diff --git a/arch/tricore/src/common/tricore_sigdeliver.c b/arch/tricore/src/common/tricore_sigdeliver.c new file mode 100644 index 0000000000000..9888597b9b7c1 --- /dev/null +++ b/arch/tricore/src/common/tricore_sigdeliver.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_sigdeliver.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "sched/sched.h" +#include "tricore_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tricore_sigdeliver + * + * Description: + * This is the a signal handling trampoline. When a signal action was + * posted. The task context was mucked with and forced to branch to this + * location with interrupts disabled. + * + ****************************************************************************/ + +void tricore_sigdeliver(void) +{ + struct tcb_s *rtcb = this_task(); + uintptr_t *regs = rtcb->xcp.saved_regs; + + board_autoled_on(LED_SIGNAL); + + sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", + rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); + DEBUGASSERT(rtcb->xcp.sigdeliver != NULL); + +retry: + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + /* Then make sure that interrupts are enabled. Signal handlers must always + * run with interrupts enabled. + */ + + up_irq_enable(); +#endif + + /* Deliver the signal */ + + ((sig_deliver_t)rtcb->xcp.sigdeliver)(rtcb); + + /* Output any debug messages BEFORE restoring errno (because they may + * alter errno), then disable interrupts again and restore the original + * errno that is needed by the user logic (it is probably EINTR). + * + * I would prefer that all interrupts are disabled when + * tricore_fullcontextrestore() is called, but that may not be necessary. + */ + + sinfo("Resuming\n"); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + up_irq_save(); +#endif + + if (!sq_empty(&rtcb->sigpendactionq) && + (rtcb->flags & TCB_FLAG_SIGNAL_ACTION) == 0) + { + goto retry; + } + + /* Modify the saved return state with the actual saved values in the + * TCB. This depends on the fact that nested signal handling is + * not supported. Therefore, these values will persist throughout the + * signal handling action. + * + * Keeping this data in the TCB resolves a security problem in protected + * and kernel mode: The regs[] array is visible on the user stack and + * could be modified by a hostile program. + */ + + rtcb->xcp.sigdeliver = NULL; /* Allows next handler to be scheduled */ + + /* Then restore the correct state for this thread of + * execution. + */ + + board_autoled_off(LED_SIGNAL); + + tricore_fullcontextrestore(regs); +} diff --git a/arch/tricore/src/common/tricore_stackframe.c b/arch/tricore/src/common/tricore_stackframe.c new file mode 100644 index 0000000000000..93a1a512834ce --- /dev/null +++ b/arch/tricore/src/common/tricore_stackframe.c @@ -0,0 +1,97 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_stackframe.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "tricore_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_stack_frame + * + * Description: + * Allocate a stack frame in the TCB's stack to hold thread-specific data. + * This function may be called anytime after up_create_stack() or + * up_use_stack() have been called but before the task has been started. + * + * Thread data may be kept in the stack (instead of in the TCB) if it is + * accessed by the user code directly. This includes such things as + * argv[]. The stack memory is guaranteed to be in the same protection + * domain as the thread. + * + * The following TCB fields will be re-initialized: + * + * - adj_stack_size: Stack size after removal of the stack frame from + * the stack + * - stack_base_ptr: Adjusted stack base pointer after the TLS Data and + * Arguments has been removed from the stack allocation. + * + * Input Parameters: + * - tcb: The TCB of new task + * - frame_size: The size of the stack frame to allocate. + * + * Returned Value: + * - A pointer to bottom of the allocated stack frame. NULL will be + * returned on any failures. The alignment of the returned value is + * the same as the alignment of the stack itself. + * + ****************************************************************************/ + +void *up_stack_frame(struct tcb_s *tcb, size_t frame_size) +{ + void *ret; + + /* Align the frame_size */ + + frame_size = STACK_ALIGN_UP(frame_size); + + /* Is there already a stack allocated? Is it big enough? */ + + if (!tcb->stack_alloc_ptr || tcb->adj_stack_size <= frame_size) + { + return NULL; + } + + ret = tcb->stack_base_ptr; + memset(ret, 0, frame_size); + + /* Save the adjusted stack values in the struct tcb_s */ + + tcb->stack_base_ptr = (uint8_t *)tcb->stack_base_ptr + frame_size; + tcb->adj_stack_size -= frame_size; + + /* And return the pointer to the allocated region */ + + return ret; +} diff --git a/arch/tricore/src/common/tricore_svcall.c b/arch/tricore/src/common/tricore_svcall.c new file mode 100644 index 0000000000000..6628e89a51a62 --- /dev/null +++ b/arch/tricore/src/common/tricore_svcall.c @@ -0,0 +1,123 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_svcall.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "tricore_internal.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tricore_svcall + * + * Description: + * This is SVCall exception handler that performs context switching + * + ****************************************************************************/ + +void tricore_svcall(volatile void *trap) +{ + uintptr_t *regs; + uint32_t cmd; + + regs = tricore_csa2addr(__mfcr(CPU_PCXI)); + + CURRENT_REGS = regs; + + cmd = regs[REG_D8]; + + /* Handle the SVCall according to the command in R0 */ + + switch (cmd) + { + /* R0=SYS_restore_context: This a restore context command: + * + * void tricore_fullcontextrestore(uint32_t *restoreregs) + * noreturn_function; + * + * At this point, the following values are saved in context: + * + * R0 = SYS_restore_context + * R1 = restoreregs + * + * In this case, we simply need to set CURRENT_REGS to restore + * register area referenced in the saved R1. context == CURRENT_REGS + * is the normal exception return. By setting CURRENT_REGS = + * context[R1], we force the return to the saved context referenced + * in R1. + */ + + case SYS_restore_context: + { + tricore_reclaim_csa(regs[REG_UPCXI]); + CURRENT_REGS = (uintptr_t *)regs[REG_D9]; + } + break; + + case SYS_switch_context: + { + *(uintptr_t **)regs[REG_D9] = (uintptr_t *)regs[REG_UPCXI]; + CURRENT_REGS = (uintptr_t *)regs[REG_D10]; + } + break; + + default: + { + svcerr("ERROR: Bad SYS call: %d\n", (int)regs[REG_D0]); + } + break; + } + + if (regs != CURRENT_REGS) + { + /* Record the new "running" task when context switch occurred. + * g_running_tasks[] is only used by assertion logic for reporting + * crashes. + */ + + g_running_tasks[this_cpu()] = this_task(); + + regs[REG_UPCXI] = (uintptr_t)CURRENT_REGS; + + __isync(); + } + + CURRENT_REGS = NULL; +} diff --git a/arch/tricore/src/common/tricore_switchcontext.c b/arch/tricore/src/common/tricore_switchcontext.c new file mode 100644 index 0000000000000..1f195bda72743 --- /dev/null +++ b/arch/tricore/src/common/tricore_switchcontext.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_switchcontext.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "clock/clock.h" +#include "tricore_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_switch_context + * + * Description: + * A task is currently in the ready-to-run list but has been prepped + * to execute. Restore its context, and start execution. + * + * Input Parameters: + * tcb: Refers to the head task of the ready-to-run list + * which will be executed. + * rtcb: Refers to the running task which will be blocked. + * + ****************************************************************************/ + +void up_switch_context(struct tcb_s *tcb, struct tcb_s *rtcb) +{ + /* Update scheduler parameters */ + + nxsched_suspend_scheduler(rtcb); + + /* Are we in an interrupt handler? */ + + if (CURRENT_REGS) + { + /* Yes, then we have to do things differently. + * Just copy the CURRENT_REGS into the OLD rtcb. + */ + + tricore_savecontext(rtcb->xcp.regs); + + /* Update scheduler parameters */ + + nxsched_resume_scheduler(tcb); + + /* Then switch contexts. Any necessary address environment + * changes will be made when the interrupt returns. + */ + + tricore_restorecontext(tcb->xcp.regs); + } + + /* No, then we will need to perform the user context switch */ + + else + { + /* Update scheduler parameters */ + + nxsched_resume_scheduler(tcb); + + /* Then switch contexts */ + + tricore_switchcontext(&rtcb->xcp.regs, tcb->xcp.regs); + + /* tricore_switchcontext forces a context switch to the task at the + * head of the ready-to-run list. It does not 'return' in the + * normal sense. When it does return, it is because the blocked + * task is again ready to run and has execution priority. + */ + } +} diff --git a/arch/tricore/src/common/tricore_systimer.c b/arch/tricore/src/common/tricore_systimer.c new file mode 100644 index 0000000000000..5547a84f5e17c --- /dev/null +++ b/arch/tricore/src/common/tricore_systimer.c @@ -0,0 +1,331 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_systimer.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include "tricore_internal.h" + +#include "IfxStm.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure provides the private representation of the "lower-half" + * driver state structure. This structure must be cast-compatible with the + * oneshot_lowerhalf_s structure. + */ + +struct tricore_systimer_lowerhalf_s +{ + struct oneshot_lowerhalf_s lower; + void *tbase; + uint64_t freq; + uint64_t alarm; + oneshot_callback_t callback; + void *arg; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int tricore_systimer_max_delay(struct oneshot_lowerhalf_s *lower, + struct timespec *ts); +static int tricore_systimer_start(struct oneshot_lowerhalf_s *lower, + oneshot_callback_t callback, void *arg, + const struct timespec *ts); +static int tricore_systimer_cancel(struct oneshot_lowerhalf_s *lower, + struct timespec *ts); +static int tricore_systimer_current(struct oneshot_lowerhalf_s *lower, + struct timespec *ts); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct oneshot_operations_s g_tricore_systimer_ops = +{ + .max_delay = tricore_systimer_max_delay, + .start = tricore_systimer_start, + .cancel = tricore_systimer_cancel, + .current = tricore_systimer_current, +}; + +static struct tricore_systimer_lowerhalf_s g_systimer_lower = +{ + .lower.ops = &g_tricore_systimer_ops, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static uint64_t +tricore_systimer_get_time(struct tricore_systimer_lowerhalf_s *priv) +{ + irqstate_t flags; + uint64_t ticks; + + flags = enter_critical_section(); + + ticks = IfxStm_get(priv->tbase); + + leave_critical_section(flags); + + return ticks; +} + +static void +tricore_systimer_set_timecmp(struct tricore_systimer_lowerhalf_s *priv, + uint64_t value) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + IfxStm_updateCompare(priv->tbase, IfxStm_Comparator_0, value); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: tricore_systimer_max_delay + * + * Description: + * Determine the maximum delay of the one-shot timer + * + * Input Parameters: + * lower An instance of the lower-half oneshot state structure. This + * structure must have been previously initialized via a call to + * oneshot_initialize(); + * ts The location in which to return the maximum delay. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int tricore_systimer_max_delay(struct oneshot_lowerhalf_s *lower, + struct timespec *ts) +{ + ts->tv_sec = UINT32_MAX; + ts->tv_nsec = NSEC_PER_SEC - 1; + + return 0; +} + +/**************************************************************************** + * Name: tricore_systimer_start + * + * Description: + * Start the oneshot timer + * + * Input Parameters: + * lower An instance of the lower-half oneshot state structure. This + * structure must have been previously initialized via a call to + * oneshot_initialize(); + * handler The function to call when when the oneshot timer expires. + * arg An opaque argument that will accompany the callback. + * ts Provides the duration of the one shot timer. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int tricore_systimer_start(struct oneshot_lowerhalf_s *lower, + oneshot_callback_t callback, void *arg, + const struct timespec *ts) +{ + struct tricore_systimer_lowerhalf_s *priv = + (struct tricore_systimer_lowerhalf_s *)lower; + uint64_t mtime = tricore_systimer_get_time(priv); + + priv->alarm = mtime + ts->tv_sec * priv->freq + + ts->tv_nsec * priv->freq / NSEC_PER_SEC; + if (priv->alarm < mtime) + { + priv->alarm = UINT64_MAX; + } + + priv->callback = callback; + priv->arg = arg; + + tricore_systimer_set_timecmp(priv, priv->alarm); + return 0; +} + +/**************************************************************************** + * Name: tricore_systimer_cancel + * + * Description: + * Cancel the oneshot timer and return the time remaining on the timer. + * + * NOTE: This function may execute at a high rate with no timer running (as + * when pre-emption is enabled and disabled). + * + * Input Parameters: + * lower Caller allocated instance of the oneshot state structure. This + * structure must have been previously initialized via a call to + * oneshot_initialize(); + * ts The location in which to return the time remaining on the + * oneshot timer. A time of zero is returned if the timer is + * not running. + * + * Returned Value: + * Zero (OK) is returned on success. A call to up_timer_cancel() when + * the timer is not active should also return success; a negated errno + * value is returned on any failure. + * + ****************************************************************************/ + +static int tricore_systimer_cancel(struct oneshot_lowerhalf_s *lower, + struct timespec *ts) +{ + struct tricore_systimer_lowerhalf_s *priv = + (struct tricore_systimer_lowerhalf_s *)lower; + uint64_t mtime; + + tricore_systimer_set_timecmp(priv, UINT64_MAX); + + mtime = tricore_systimer_get_time(priv); + if (priv->alarm > mtime) + { + uint64_t nsec = (priv->alarm - mtime) * + NSEC_PER_SEC / priv->freq; + + ts->tv_sec = nsec / NSEC_PER_SEC; + ts->tv_nsec = nsec % NSEC_PER_SEC; + } + else + { + ts->tv_sec = 0; + ts->tv_nsec = 0; + } + + priv->alarm = 0; + priv->callback = NULL; + priv->arg = NULL; + + return 0; +} + +/**************************************************************************** + * Name: tricore_systimer_current + * + * Description: + * Get the current time. + * + * Input Parameters: + * lower Caller allocated instance of the oneshot state structure. This + * structure must have been previously initialized via a call to + * oneshot_initialize(); + * ts The location in which to return the current time. A time of zero + * is returned for the initialization moment. + * + * Returned Value: + * Zero (OK) is returned on success, a negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +static int tricore_systimer_current(struct oneshot_lowerhalf_s *lower, + struct timespec *ts) +{ + struct tricore_systimer_lowerhalf_s *priv = + (struct tricore_systimer_lowerhalf_s *)lower; + uint64_t mtime = tricore_systimer_get_time(priv); + uint64_t nsec = mtime / (priv->freq / USEC_PER_SEC) * NSEC_PER_USEC; + + ts->tv_sec = nsec / NSEC_PER_SEC; + ts->tv_nsec = nsec % NSEC_PER_SEC; + + return 0; +} + +/**************************************************************************** + * Name: tricore_systimer_interrupt + * + * Description: + * This function is software interrupt handler to proceed + * the system timer interrupt. + * + ****************************************************************************/ + +static int tricore_systimer_interrupt(int irq, void *context, void *arg) +{ + struct tricore_systimer_lowerhalf_s *priv = arg; + + tricore_systimer_set_timecmp(priv, UINT64_MAX); + if (priv->callback != NULL) + { + priv->callback(&priv->lower, priv->arg); + } + + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tricore_systimer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +struct oneshot_lowerhalf_s * +tricore_systimer_initialize(void *tbase, int irq, uint64_t freq) +{ + struct tricore_systimer_lowerhalf_s *priv = &g_systimer_lower; + + priv->tbase = tbase; + priv->freq = freq; + + IfxStm_setCompareControl(tbase, + IfxStm_Comparator_0, + IfxStm_ComparatorOffset_0, + IfxStm_ComparatorSize_32Bits, + IfxStm_ComparatorInterrupt_ir0); + + IfxStm_clearCompareFlag(tbase, IfxStm_Comparator_0); + tricore_systimer_set_timecmp(priv, UINT64_MAX); + IfxStm_enableComparatorInterrupt(tbase, IfxStm_Comparator_0); + + irq_attach(irq, tricore_systimer_interrupt, priv); + up_enable_irq(irq); + + return (struct oneshot_lowerhalf_s *)priv; +} diff --git a/arch/tricore/src/common/tricore_tcbinfo.c b/arch/tricore/src/common/tricore_tcbinfo.c new file mode 100644 index 0000000000000..15d9fd6e767fc --- /dev/null +++ b/arch/tricore/src/common/tricore_tcbinfo.c @@ -0,0 +1,58 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_tcbinfo.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint16_t g_reg_offs[1]; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +const struct tcbinfo_s g_tcbinfo used_data = +{ + .pid_off = TCB_PID_OFF, + .state_off = TCB_STATE_OFF, + .pri_off = TCB_PRI_OFF, + .name_off = TCB_NAME_OFF, + .stack_off = TCB_STACK_OFF, + .stack_size_off = TCB_STACK_SIZE_OFF, + .regs_off = TCB_REGS_OFF, + .regs_num = nitems(g_reg_offs), + { + .p = g_reg_offs, + }, +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/tricore/src/common/tricore_testset.c b/arch/tricore/src/common/tricore_testset.c new file mode 100644 index 0000000000000..cc4242de58f5b --- /dev/null +++ b/arch/tricore/src/common/tricore_testset.c @@ -0,0 +1,61 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_testset.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "tricore_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_testset + * + * Description: + * Perform an atomic test and set operation on the provided spinlock. + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * lock - A reference to the spinlock object. + * + * Returned Value: + * The spinlock is always locked upon return. The previous value of the + * spinlock variable is returned, either SP_LOCKED if the spinlock was + * previously locked (meaning that the test-and-set operation failed to + * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked + * (meaning that we successfully obtained the lock). + * + ****************************************************************************/ + +spinlock_t up_testset(volatile spinlock_t *lock) +{ + /* Perform the compare and set operation */ + + return __cmpswapw((volatile void *)lock, SP_LOCKED, SP_UNLOCKED); +} + diff --git a/arch/tricore/src/common/tricore_trapcall.c b/arch/tricore/src/common/tricore_trapcall.c new file mode 100644 index 0000000000000..88fa318543f37 --- /dev/null +++ b/arch/tricore/src/common/tricore_trapcall.c @@ -0,0 +1,67 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_trapcall.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "tricore_internal.h" + +#include "IfxCpu_Trap.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tricore_trapcall + * + * Description: + * This is Trap exception handler + * + ****************************************************************************/ + +void tricore_trapcall(volatile void *trap) +{ + uintptr_t *regs; + + regs = tricore_csa2addr(__mfcr(CPU_PCXI)); + + CURRENT_REGS = regs; + + up_irq_save(); + PANIC_WITH_REGS("Trap", CURRENT_REGS); +} diff --git a/arch/tricore/src/common/tricore_usestack.c b/arch/tricore/src/common/tricore_usestack.c new file mode 100644 index 0000000000000..5952fbf611a77 --- /dev/null +++ b/arch/tricore/src/common/tricore_usestack.c @@ -0,0 +1,125 @@ +/**************************************************************************** + * arch/tricore/src/common/tricore_usestack.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "tricore_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_use_stack + * + * Description: + * Setup up stack-related information in the TCB using pre-allocated stack + * memory. This function is called only from nxtask_init() when a task or + * kernel thread is started (never for pthreads). + * + * The following TCB fields must be initialized: + * + * - adj_stack_size: Stack size after adjustment for hardware, + * processor, etc. This value is retained only for debug + * purposes. + * - stack_alloc_ptr: Pointer to allocated stack + * - stack_base_ptr: Adjusted stack base pointer after the TLS Data and + * Arguments has been removed from the stack allocation. + * + * Input Parameters: + * - tcb: The TCB of new task + * - stack_size: The allocated stack size. + * + * NOTE: Unlike up_stack_create() and up_stack_release, this function + * does not require the task type (ttype) parameter. The TCB flags will + * always be set to provide the task type to up_use_stack() if it needs + * that information. + * + ****************************************************************************/ + +int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size) +{ + uintptr_t top_of_stack; + size_t size_of_stack; + +#ifdef CONFIG_TLS_ALIGNED + /* Make certain that the user provided stack is properly aligned */ + + DEBUGASSERT(((uintptr_t)stack & TLS_STACK_MASK) == 0); +#endif + + /* Is there already a stack allocated? */ + + if (tcb->stack_alloc_ptr) + { + /* Yes.. Release the old stack allocation */ + + up_release_stack(tcb, tcb->flags & TCB_FLAG_TTYPE_MASK); + } + + /* Save the new stack allocation */ + + tcb->stack_alloc_ptr = stack; + + /* RISC-V uses a push-down stack: the stack grows toward lower addresses in + * memory. The stack pointer register, points to the lowest, valid work + * address (the "top" of the stack). Items on the stack are referenced + * as positive word offsets from SP. + */ + + top_of_stack = (uintptr_t)tcb->stack_alloc_ptr + stack_size; + + /* The RISC-V stack must be aligned at 128-bit (16-byte) boundaries. + * If necessary top_of_stack must be rounded down to the next boundary. + */ + + top_of_stack = STACK_ALIGN_DOWN(top_of_stack); + size_of_stack = top_of_stack - (uintptr_t)tcb->stack_alloc_ptr; + + /* Save the adjusted stack values in the struct tcb_s */ + + tcb->stack_base_ptr = tcb->stack_alloc_ptr; + tcb->adj_stack_size = size_of_stack; + +#if defined(CONFIG_STACK_COLORATION) + /* If stack debug is enabled, then fill the stack with a + * recognizable value that we can use later to test for high + * water marks. + */ + + tricore_stack_color(tcb->stack_base_ptr, tcb->adj_stack_size); +#endif + + return OK; +} diff --git a/arch/tricore/src/tc3xx/.gitignore b/arch/tricore/src/tc3xx/.gitignore new file mode 100644 index 0000000000000..6e279e3dd9ae5 --- /dev/null +++ b/arch/tricore/src/tc3xx/.gitignore @@ -0,0 +1,3 @@ +/*_unpack +/tc397 +/*tar.gz diff --git a/arch/tricore/src/tc3xx/Kconfig b/arch/tricore/src/tc3xx/Kconfig new file mode 100644 index 0000000000000..1c3f45744d0af --- /dev/null +++ b/arch/tricore/src/tc3xx/Kconfig @@ -0,0 +1,18 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +comment "TC3XX Configuration Options" + +menu "TC3XX Peripheral Support" + +# These are the peripheral selections proper + +config TC3XX_UART0 + bool "TC3XX UART0" + default y + select UART0_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +endmenu diff --git a/arch/tricore/src/tc3xx/Make.defs b/arch/tricore/src/tc3xx/Make.defs new file mode 100644 index 0000000000000..81ae83f6df71a --- /dev/null +++ b/arch/tricore/src/tc3xx/Make.defs @@ -0,0 +1,62 @@ +############################################################################ +# arch/tricore/src/tc3xx/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +ifeq ($(CONFIG_ARCH_CHIP_TC397),y) + -include tc3xx/tc397/Make.defs +endif + +CHIP_CSRCS += tc3xx_timerisr.c +CHIP_CSRCS += tc3xx_serial.c + +VPATH += tc3xx + +tc3xx_libc$(OBJEXT): tc3xx_libc.c + $(call COMPILE, $<, $@) + +libc_fpu$(LIBEXT): tc3xx_libc$(OBJEXT) + $(call ARCHIVE, $@, $<) + +EXTRA_LIBS += libc_fpu$(LIBEXT) +LIBPATHS += $(CURDIR) + +TC397_UNPACK = tc397 +TC397_COMMIT = master +TC397_URL = https://github.com/anchao/tc397_sdk/archive/refs/heads +TC397_TARBALL = tc3xx/$(TC397_UNPACK).tar.gz +TC397_DIR = tc397_sdk-master + +$(TC397_TARBALL): + $(call DOWNLOAD,$(TC397_URL),$(TC397_COMMIT).tar.gz,$(TC397_TARBALL)) + +tc3xx/.tc397_unpack: $(TC397_TARBALL) + $(Q) echo "Unpacking: TC397" + $(Q) tar xzf $(TC397_TARBALL) -C tc3xx + $(Q) mv tc3xx/$(TC397_DIR) tc3xx/$(TC397_UNPACK) + $(Q) touch tc3xx/.tc397_unpack + + +ifeq ($(wildcard tc3xx/$(TC397_UNPACK)/.git),) +context:: .tc397_unpack + +distclean:: + $(call DELFILE, tc3xx/.tc397_unpack) + $(call DELFILE, $(TC397_TARBALL)) + $(call DELDIR, tc3xx/$(TC397_UNPACK)) +endif diff --git a/arch/tricore/src/tc3xx/Toolchain.defs b/arch/tricore/src/tc3xx/Toolchain.defs new file mode 100644 index 0000000000000..6b709b738f9f0 --- /dev/null +++ b/arch/tricore/src/tc3xx/Toolchain.defs @@ -0,0 +1,26 @@ +############################################################################ +# arch/tricore/src/tc3xx/Toolchain.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +ifeq ($(CONFIG_ARCH_CHIP_TC397),y) + ARCHOPTIMIZATION += --cpu=tc39xb + LDFLAGS += -Ctc39xb +endif + +include $(TOPDIR)/arch/tricore/src/common/Toolchain.defs diff --git a/arch/tricore/src/tc3xx/chip.h b/arch/tricore/src/tc3xx/chip.h new file mode 100644 index 0000000000000..b190de4512adc --- /dev/null +++ b/arch/tricore/src/tc3xx/chip.h @@ -0,0 +1,28 @@ +/**************************************************************************** + * arch/tricore/src/tc3xx/chip.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_TRICORE_SRC_TC3XX_CHIP_H +#define __ARCH_TRICORE_SRC_TC3XX_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#endif /* __ARCH_TRICORE_SRC_TC3XX_CHIP_H */ diff --git a/arch/tricore/src/tc3xx/tc3xx_libc.c b/arch/tricore/src/tc3xx/tc3xx_libc.c new file mode 100644 index 0000000000000..177f8ab474223 --- /dev/null +++ b/arch/tricore/src/tc3xx/tc3xx_libc.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * arch/tricore/src/tc3xx/tc3xx_libc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "tricore_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/* TODO: + * The data copy from flash to ram reuses the implementation in tricore sdk. + * The next update will reimplement _c_init() to abandon the copy code. + * + * Usage: ltc [options] files + * -i --user-provided-initialization-code + * + * the user provides his own initialization + * routine, do not emit the copytable + * + * void _c_init(void) + * { + * } + */ + +/* The implementation of libc is introduced by default in the Tricore + * toolchain, in nuttx we made a fake libc_fpu.a library to bypass + * this issue, but the linker will still generate markup code, + * add a few definitions to fool the linker. + */ + +void __printf_float(void) +{ +} + +void __printf_int(void) +{ +} + +void __printf_llong(void) +{ +} + +void _main(void) +{ +} + +void _doexit(void) +{ +} + +/* BUG, Workaroud for tasking compiler: + * + * ltc E106: unresolved external: regulator_gpio_init - + * (drivers_initialize.o) + * ltc F019: unrecoverable error: fatal link error + * + */ + +int regulator_gpio_init(void *iodev, void *desc) +{ + return 0; +} diff --git a/arch/tricore/src/tc3xx/tc3xx_serial.c b/arch/tricore/src/tc3xx/tc3xx_serial.c new file mode 100644 index 0000000000000..cf6e87bbfcddf --- /dev/null +++ b/arch/tricore/src/tc3xx/tc3xx_serial.c @@ -0,0 +1,741 @@ +/**************************************************************************** + * arch/tricore/src/tc3xx/tc3xx_serial.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "tricore_internal.h" + +#include "Asclin/Asc/IfxAsclin_Asc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If we are not using the serial driver for the console, then we still must + * provide some minimal implementation of up_putc. + */ + +#ifdef USE_SERIALDRIVER + +/* Which UART with be tty0/console and which tty1? The console will always + * be ttyS0. If there is no console then will use the lowest numbered UART. + */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_TC3XX_UART0) +# define HAVE_SERIAL_CONSOLE 1 +#else +# undef CONFIG_UART0_SERIAL_CONSOLE +# undef HAVE_SERIAL_CONSOLE +#endif + +#ifdef HAVE_SERIAL_CONSOLE +# if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* UART0 is console */ +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# define SERIAL_CONSOLE 1 +# else +# error "I'm confused... Do we have a serial console or not?" +# endif +#else +# undef CONSOLE_DEV /* No console */ +# undef CONFIG_UART0_SERIAL_CONSOLE +# if defined(CONFIG_TC3XX_UART0) +# define TTYS0_DEV g_uart0port /* UART0 is ttyS0 */ +# define SERIAL_CONSOLE 1 +# else +# undef TTYS0_DEV +# endif +#endif + +#undef HAVE_UART_DEVICE +#if defined(CONFIG_TC3XX_UART0) +# define HAVE_UART_DEVICE 1 +#endif + +/* Common initialization logic will not not know that the all of the UARTs + * have been disabled. So, as a result, we may still have to provide + * stub implementations of tricore_earlyserialinit(), + * tricore_serialinit(), and up_putc(). + */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct up_dev_s +{ + void *uartbase; /* Base address of UART registers */ + void *pins; /* Pin configuration */ + uint32_t baud; /* Configured baud */ + uint8_t irq; /* IRQ associated with this UART */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Serial driver methods */ + +static int up_setup(struct uart_dev_s *dev); +static void up_shutdown(struct uart_dev_s *dev); +static int up_attach(struct uart_dev_s *dev); +static void up_detach(struct uart_dev_s *dev); +static int up_interrupt(int irq, void *context, void *arg); +static int up_ioctl(struct file *filep, int cmd, unsigned long arg); +static int up_receive(struct uart_dev_s *dev, unsigned int *status); +static void up_rxint(struct uart_dev_s *dev, bool enable); +static bool up_rxavailable(struct uart_dev_s *dev); +static void up_send(struct uart_dev_s *dev, int ch); +static void up_txint(struct uart_dev_s *dev, bool enable); +static bool up_txready(struct uart_dev_s *dev); +static bool up_txempty(struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = up_setup, + .shutdown = up_shutdown, + .attach = up_attach, + .detach = up_detach, + .ioctl = up_ioctl, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_TC3XX_UART0 +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif + +#ifdef CONFIG_TC3XX_UART0 + +#define UART_PIN_RX IfxAsclin0_RXA_P14_1_IN /* UART receive port pin */ +#define UART_PIN_TX IfxAsclin0_TX_P14_0_OUT /* UART transmit port pin */ + +/* Pin configuration */ + +static const IfxAsclin_Asc_Pins g_uart0_pins = +{ + NULL, IfxPort_InputMode_pullUp, /* CTS pin not used */ + &UART_PIN_RX, IfxPort_InputMode_pullUp, /* RX pin */ + NULL, IfxPort_OutputMode_pushPull, /* RTS pin not used */ + &UART_PIN_TX, IfxPort_OutputMode_pushPull, /* TX pin */ + IfxPort_PadDriver_cmosAutomotiveSpeed1 +}; + +static struct up_dev_s g_uart0priv = +{ + .uartbase = &MODULE_ASCLIN0, + .pins = &g_uart0_pins, + .baud = CONFIG_UART0_BAUD, + .irq = 21, +}; + +static uart_dev_t g_uart0port = +{ +#if SERIAL_CONSOLE == 1 + .isconsole = 1, +#endif + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: asclin_init + * + * Description: + * Configure the UART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static void asclin_init(struct up_dev_s *priv) +{ + Ifx_ASCLIN *asclin = priv->uartbase; + const IfxAsclin_Asc_Pins *pins = priv->pins; + + /* enabling the module */ + + IfxAsclin_enableModule(asclin); + + /* disabling the clock */ + + IfxAsclin_setClockSource(asclin, IfxAsclin_ClockSource_noClock); + + /* setting the module in Initialise mode */ + + IfxAsclin_setFrameMode(asclin, IfxAsclin_FrameMode_initialise); + + /* sets the prescaler */ + + IfxAsclin_setPrescaler(asclin, 1); + + /* temporary set the clock source for baudrate configuration */ + + IfxAsclin_setClockSource(asclin, IfxAsclin_ClockSource_ascFastClock); + + /* setting the baudrate bit fields to generate the required baudrate */ + + IfxAsclin_setBitTiming(asclin, priv->baud, + IfxAsclin_OversamplingFactor_16, + IfxAsclin_SamplePointPosition_8, + IfxAsclin_SamplesPerBit_three); + + /* disabling the clock again */ + + IfxAsclin_setClockSource(asclin, IfxAsclin_ClockSource_noClock); + + /* selecting the loopback mode */ + + IfxAsclin_enableLoopBackMode(asclin, false); + + /* setting parity enable */ + + IfxAsclin_enableParity(asclin, false); + + /* setting parity type (odd/even) */ + + IfxAsclin_setParityType(asclin, IfxAsclin_ParityType_even); + + /* setting the stop bit */ + + IfxAsclin_setStopBit(asclin, IfxAsclin_StopBit_1); + + /* setting the shift direction */ + + IfxAsclin_setShiftDirection(asclin, + IfxAsclin_ShiftDirection_lsbFirst); + + /* setting the data length */ + + IfxAsclin_setDataLength(asclin, IfxAsclin_DataLength_8); + + /* setting Tx FIFO inlet width */ + + IfxAsclin_setTxFifoInletWidth(asclin, + IfxAsclin_TxFifoInletWidth_1); + + /* setting Rx FIFO outlet width */ + + IfxAsclin_setRxFifoOutletWidth(asclin, + IfxAsclin_RxFifoOutletWidth_1); + + /* setting idle delay */ + + IfxAsclin_setIdleDelay(asclin, IfxAsclin_IdleDelay_0); + + /* setting Tx FIFO level at which a Tx interrupt will be triggered */ + + IfxAsclin_setTxFifoInterruptLevel(asclin, + IfxAsclin_TxFifoInterruptLevel_0); + + /* setting Rx FIFO interrupt level at which a Rx + * interrupt will be triggered + */ + + IfxAsclin_setRxFifoInterruptLevel(asclin, + IfxAsclin_RxFifoInterruptLevel_1); + + /* setting Tx FIFO interrupt generation mode */ + + IfxAsclin_setTxFifoInterruptMode(asclin, + IfxAsclin_FifoInterruptMode_combined); + + /* setting Rx FIFO interrupt generation mode */ + + IfxAsclin_setRxFifoInterruptMode(asclin, + IfxAsclin_FifoInterruptMode_combined); + + /* selecting the frame mode */ + + IfxAsclin_setFrameMode(asclin, IfxAsclin_FrameMode_asc); + + /* Pin mapping */ + + if (pins != NULL) + { + IfxAsclin_Cts_In *cts = pins->cts; + + if (cts != NULL) + { + IfxAsclin_initCtsPin(cts, pins->ctsMode, pins->pinDriver); + } + + IfxAsclin_Rx_In *rx = pins->rx; + + if (rx != NULL) + { + IfxAsclin_initRxPin(rx, pins->rxMode, pins->pinDriver); + } + + IfxAsclin_Rts_Out *rts = pins->rts; + + if (rts != NULL) + { + IfxAsclin_initRtsPin(rts, pins->rtsMode, pins->pinDriver); + } + + IfxAsclin_Tx_Out *tx = pins->tx; + + if (tx != NULL) + { + IfxAsclin_initTxPin(tx, pins->txMode, pins->pinDriver); + } + } + + /* select the clock source */ + + IfxAsclin_setClockSource(asclin, IfxAsclin_ClockSource_ascFastClock); + + /* disable all flags */ + + IfxAsclin_disableAllFlags(asclin); + + /* clear all flags */ + + IfxAsclin_clearAllFlags(asclin); + + /* HW error flags */ + + IfxAsclin_enableParityErrorFlag(asclin, true); + IfxAsclin_enableFrameErrorFlag(asclin, true); + IfxAsclin_enableRxFifoOverflowFlag(asclin, true); + IfxAsclin_enableRxFifoUnderflowFlag(asclin, true); + IfxAsclin_enableTxFifoOverflowFlag(asclin, true); + + /* enable transfers */ + + IfxAsclin_enableRxFifoInlet(asclin, true); + IfxAsclin_enableTxFifoOutlet(asclin, true); + + IfxAsclin_flushRxFifo(asclin); + IfxAsclin_flushTxFifo(asclin); +} + +/**************************************************************************** + * Name: up_setup + * + * Description: + * Configure the UART baud, bits, parity, etc. This method is called the + * first time that the serial port is opened. + * + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev) +{ + asclin_init(dev->priv); + + return OK; +} + +/**************************************************************************** + * Name: up_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void up_shutdown(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = dev->priv; + + /* Disable interrupts */ + + up_disable_irq(priv->irq); +} + +/**************************************************************************** + * Name: up_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled by the attach method (unless the + * hardware supports multiple levels of interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() are called. + * + ****************************************************************************/ + +static int up_attach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = dev->priv; + int ret; + + /* Initialize interrupt generation on the peripheral */ + + ret = irq_attach(priv->irq, up_interrupt, dev); + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ + + up_enable_irq(priv->irq); + } + + return ret; +} + +/**************************************************************************** + * Name: up_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The exception + * is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void up_detach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = dev->priv; + + /* Disable interrupts */ + + up_disable_irq(priv->irq); + + /* Detach from the interrupt */ + + irq_detach(priv->irq); +} + +/**************************************************************************** + * Name: up_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked when an + * interrupt is received on the 'irq'. It should call uart_xmitchars or + * uart_recvchars to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'arg' to the + * appropriate uart_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int up_interrupt(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev = arg; + + if (up_rxavailable(dev)) + { + uart_recvchars(dev); + } + + if (up_txready(dev)) + { + uart_xmitchars(dev); + } + + return OK; +} + +/**************************************************************************** + * Name: up_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int up_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + return -ENOTTY; +} + +/**************************************************************************** + * Name: up_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int up_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct up_dev_s *priv = dev->priv; + + return IfxAsclin_readRxData(priv->uartbase); +} + +/**************************************************************************** + * Name: up_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void up_rxint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv = dev->priv; + irqstate_t flags = enter_critical_section(); + + IfxAsclin_enableRxFifoFillLevelFlag(priv->uartbase, enable); + IfxAsclin_enableRxFifoInlet(priv->uartbase, enable); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_rxavailable + * + * Description: + * Return true if the receive register is not empty + * + ****************************************************************************/ + +static bool up_rxavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = dev->priv; + + return IfxAsclin_getRxFifoFillLevel(priv->uartbase) > 0; +} + +/**************************************************************************** + * Name: up_send + * + * Description: + * This method will send one byte on the UART. + * + ****************************************************************************/ + +static void up_send(struct uart_dev_s *dev, int ch) +{ + struct up_dev_s *priv = dev->priv; + + /* Wait for FIFO */ + + if (dev == &CONSOLE_DEV) + { + up_putc(ch); + return; + } + + while (IfxAsclin_getTxFifoFillLevel(priv->uartbase) != 0); + + IfxAsclin_clearAllFlags(priv->uartbase); + IfxAsclin_writeTxData(priv->uartbase, ch); +} + +/**************************************************************************** + * Name: up_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void up_txint(struct uart_dev_s *dev, bool enable) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + if (enable) + { + /* Enable the TX interrupt */ + + uart_xmitchars(dev); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return true if the tranmsit data register is not full + * + ****************************************************************************/ + +static bool up_txready(struct uart_dev_s *dev) +{ + return true; +} + +/**************************************************************************** + * Name: up_txempty + * + * Description: + * Return true if the tranmsit data register is empty + * + ****************************************************************************/ + +static bool up_txempty(struct uart_dev_s *dev) +{ + struct up_dev_s *priv = dev->priv; + + /* Return true if the TX wartermak is pending */ + + return IfxAsclin_getTxFifoFillLevel(priv->uartbase) != 0; +} + +/**************************************************************************** + * Name: tricore_lowputc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +void tricore_lowputc(char ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + struct up_dev_s *priv = CONSOLE_DEV.priv; + + /* Wait for FIFO */ + + while (IfxAsclin_getTxFifoFillLevel(priv->uartbase) != 0); + + IfxAsclin_clearAllFlags(priv->uartbase); + IfxAsclin_writeTxData(priv->uartbase, ch); +#endif /* HAVE_CONSOLE */ +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef USE_EARLYSERIALINIT + +/**************************************************************************** + * Name: tricore_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before tricore_serialinit. NOTE: This function depends on GPIO pin + * configuration performed in up_consoleinit() and main clock + * initialization performed in up_clkinitialize(). + * + ****************************************************************************/ + +void tricore_earlyserialinit(void) +{ + /* Configuration whichever one is the console */ + +#ifdef HAVE_SERIAL_CONSOLE + CONSOLE_DEV.isconsole = true; + up_setup(&CONSOLE_DEV); +#endif +} +#endif + +/**************************************************************************** + * Name: tricore_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that tricore_earlyserialinit was called previously. + * + ****************************************************************************/ + +void tricore_serialinit(void) +{ + /* Register the console */ + +#ifdef HAVE_SERIAL_CONSOLE + uart_register("/dev/console", &CONSOLE_DEV); +#endif + + /* Register all UARTs */ + + uart_register("/dev/ttyS0", &TTYS0_DEV); +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_SERIAL_CONSOLE + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + tricore_lowputc('\r'); + } + + tricore_lowputc(ch); +#endif + return ch; +} +#endif /* USE_SERIALDRIVER */ diff --git a/arch/tricore/src/tc3xx/tc3xx_timerisr.c b/arch/tricore/src/tc3xx/tc3xx_timerisr.c new file mode 100644 index 0000000000000..4fcab8b5b2dca --- /dev/null +++ b/arch/tricore/src/tc3xx/tc3xx_timerisr.c @@ -0,0 +1,63 @@ +/**************************************************************************** + * arch/tricore/src/tc3xx/tc3xx_timerisr.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include "tricore_internal.h" + +#include "IfxStm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SCU_FREQUENCY 100000000UL + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + struct oneshot_lowerhalf_s *lower; + + lower = tricore_systimer_initialize(&MODULE_STM0, 192, SCU_FREQUENCY); + + DEBUGASSERT(lower != NULL); + + up_alarm_set_lowerhalf(lower); +} diff --git a/arch/x86/include/irq.h b/arch/x86/include/irq.h index a29002974fcb0..e38787a8dc00f 100644 --- a/arch/x86/include/irq.h +++ b/arch/x86/include/irq.h @@ -76,7 +76,7 @@ extern "C" #ifndef __ASSEMBLY__ /* This holds a references to the current interrupt level register storage - * structure. If is non-NULL only during interrupt processing. + * structure. It is non-NULL only during interrupt processing. */ EXTERN volatile uint32_t *g_current_regs; diff --git a/arch/x86/src/Makefile b/arch/x86/src/Makefile index 176bf7ceb79df..76e5b1abfbfa8 100644 --- a/arch/x86/src/Makefile +++ b/arch/x86/src/Makefile @@ -18,7 +18,7 @@ # ############################################################################ -include $(TOPDIR)/Make.defs +include $(TOPDIR)/tools/apps-or-nuttx-Make.defs include chip/Make.defs ifeq ($(CONFIG_ARCH_I486),y) diff --git a/arch/x86/src/common/x86_exit.c b/arch/x86/src/common/x86_exit.c index 8b0c2a42313ba..a26e3914af228 100644 --- a/arch/x86/src/common/x86_exit.c +++ b/arch/x86/src/common/x86_exit.c @@ -61,8 +61,6 @@ void up_exit(int status) enter_critical_section(); - sinfo("TCB=%p exiting\n", tcb); - nxsched_dumponexit(); /* Destroy the task at the head of the ready to run list. */ diff --git a/arch/x86/src/common/x86_getintstack.c b/arch/x86/src/common/x86_getintstack.c index 03167b6b348a0..355e013c720b5 100644 --- a/arch/x86/src/common/x86_getintstack.c +++ b/arch/x86/src/common/x86_getintstack.c @@ -37,7 +37,7 @@ ****************************************************************************/ #if CONFIG_ARCH_INTERRUPTSTACK > 3 -uintptr_t up_get_intstackbase(void) +uintptr_t up_get_intstackbase(int cpu) { return (uintptr_t)g_intstackalloc; } diff --git a/arch/x86_64/CMakeLists.txt b/arch/x86_64/CMakeLists.txt new file mode 100644 index 0000000000000..9aef319f33c6e --- /dev/null +++ b/arch/x86_64/CMakeLists.txt @@ -0,0 +1,21 @@ +# ############################################################################## +# arch/x86_64/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +nuttx_add_subdirectory() diff --git a/arch/x86_64/Kconfig b/arch/x86_64/Kconfig index fac4bb7d61c72..d67475dffd617 100644 --- a/arch/x86_64/Kconfig +++ b/arch/x86_64/Kconfig @@ -21,6 +21,17 @@ config ARCH_INTEL64 select ARCH_HAVE_TICKLESS select ARCH_HAVE_STACKCHECK select ARCH_HAVE_RNG + select ARCH_HAVE_RESET + select ARCH_HAVE_MMX + select ARCH_HAVE_SSE + select ARCH_HAVE_SSE2 + select ARCH_HAVE_SSE3 + select ARCH_HAVE_SSSE3 + select ARCH_HAVE_SSE41 + select ARCH_HAVE_SSE42 + select ARCH_HAVE_SSE4A + select ARCH_ICACHE + select ARCH_DCACHE ---help--- Intel x86_64 architecture @@ -32,16 +43,47 @@ config ARCH_CHIP_X86_64_CUSTOM endchoice -choice - prompt "x86_64 system selection" - default ARCH_BOARD_QEMU +# CPU features -config ARCH_BOARD_QEMU - bool "Qemu environment" - ---help--- - Targeting virtualized qemu environment +config ARCH_HAVE_MMX + bool + default n -endchoice +config ARCH_HAVE_SSE + bool + default y + +config ARCH_HAVE_SSE2 + bool + default y + +config ARCH_HAVE_SSE3 + bool + default n + +config ARCH_HAVE_SSSE3 + bool + default n + +config ARCH_HAVE_SSE41 + bool + default n + +config ARCH_HAVE_SSE42 + bool + default n + +config ARCH_HAVE_SSE4A + bool + default n + +config ARCH_HAVE_AVX + bool + default n + +config ARCH_HAVE_AVX512 + bool + default n source "arch/x86_64/src/common/Kconfig" @@ -54,19 +96,22 @@ config ARCH_CHIP endif # ARCH_INTEL64 -if ARCH_BOARD_QEMU -source "arch/x86_64/src/qemu/Kconfig" - -config ARCH_BOARD - string - default "qemu-intel64" +config ARCH_MULTIBOOT2 + bool "Append multiboot2 header" + default y + ---help--- + Include a multiboot2 header. This also provides information to the + system to enable certain features like the low level framebuffer. -endif # ARCH_CHIP_QEMU +if ARCH_MULTIBOOT2 -config ARCH_EXCLUDE_MULTIBOOT - bool "Don't append multiboot2 header" +config MULTBOOT2_FB_TERM + bool "Multiboot2 framebuffer terminal" default n + depends on NXFONTS ---help--- - Some platforms, e.g. jailhouse, do not like to have a multiboot header + Enable a framebuffer terminal for early debug printing + +endif # ARCH_MULTIBOOT2 endif # ARCH_X86_64 diff --git a/arch/x86_64/include/acpi.h b/arch/x86_64/include/acpi.h new file mode 100644 index 0000000000000..d1f5f89e85773 --- /dev/null +++ b/arch/x86_64/include/acpi.h @@ -0,0 +1,304 @@ +/**************************************************************************** + * arch/x86_64/include/acpi.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_X86_64_INCLUDE_ACPI_H +#define __ARCH_X86_64_INCLUDE_ACPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ACPI_SIG_RSDP "RSD PTR " /* Root System Description Pointer */ + +/* Tables defined by ACPI spec */ + +#define ACPI_SIG_APIC "APIC" /* Multiple APIC Description Table (MADT) */ +#define ACPI_SIG_BERT "BERT" +#define ACPI_SIG_BGRT "BGRT" +#define ACPI_SIG_CCEL "CCEL" +#define ACPI_SIG_CPEP "CPEP" +#define ACPI_SIG_DSDT "DSDT" +#define ACPI_SIG_ECDT "ECDT" +#define ACPI_SIG_EINJ "EINJ" +#define ACPI_SIG_ERST "ERST" +#define ACPI_SIG_FACP "FACP" +#define ACPI_SIG_FACS "FACS" +#define ACPI_SIG_FPDT "FPDT" +#define ACPI_SIG_GTDT "GTDT" +#define ACPI_SIG_HEST "HEST" +#define ACPI_SIG_MISC "MISC" +#define ACPI_SIG_MSCT "MSCT" +#define ACPI_SIG_MPST "MPST" +#define ACPI_SIG_NFIT "NFIT" +#define ACPI_SIG_OEMx "OEMx" +#define ACPI_SIG_PCCT "PCCT" +#define ACPI_SIG_PHAT "PHAT" +#define ACPI_SIG_PMTT "PMTT" +#define ACPI_SIG_PPTT "PPTT" +#define ACPI_SIG_PSDT "PSDT" +#define ACPI_SIG_RASF "RASF" +#define ACPI_SIG_RAS2 "RAS2" +#define ACPI_SIG_RSDT "RSDT" +#define ACPI_SIG_SBST "SBST" +#define ACPI_SIG_SDEV "SDEV" +#define ACPI_SIG_SLIT "SLIT" +#define ACPI_SIG_SRAT "SRAT" +#define ACPI_SIG_SSDT "SSDT" +#define ACPI_SIG_SVKL "SVKL" +#define ACPI_SIG_XSDT "XSDT" + +/* Tables not defined by ACPI spec */ + +#define ACPI_SIG_AEST "AEST" +#define ACPI_SIG_AGDI "AGDI" +#define ACPI_SIG_APMT "APMT" +#define ACPI_SIG_BDAT "BDAT" +#define ACPI_SIG_BOOT "BOOT" +#define ACPI_SIG_CEDT "CEDT" +#define ACPI_SIG_CSRT "CSRT" +#define ACPI_SIG_DBGT "DBGT" +#define ACPI_SIG_DBG2 "DBG2" +#define ACPI_SIG_DMAR "DMAR" +#define ACPI_SIG_DRTM "DRTM" +#define ACPI_SIG_DTPR "DTPR" +#define ACPI_SIG_ETDT "ETDT" +#define ACPI_SIG_HPET "HPET" +#define ACPI_SIG_IBFT "IBFT" +#define ACPI_SIG_IERS "IERS" +#define ACPI_SIG_IORT "IORT" +#define ACPI_SIG_IVRS "IVRS" +#define ACPI_SIG_KEYP "KEYP" +#define ACPI_SIG_LPIT "LPIT" +#define ACPI_SIG_MCFG "MCFG" /* PCI Express Memory-mapped Configuration table */ +#define ACPI_SIG_MCHI "MCHI" +#define ACPI_SIG_MHSP "MHSP" +#define ACPI_SIG_MPAM "MPAM" +#define ACPI_SIG_MSDM "MSDM" +#define ACPI_SIG_NBFT "NBFT" +#define ACPI_SIG_PRMT "PRMT" +#define ACPI_SIG_RGRT "RGRT" +#define ACPI_SIG_SDEI "SDEI" +#define ACPI_SIG_SLIC "SLIC" +#define ACPI_SIG_SPCR "SPCR" +#define ACPI_SIG_SPMI "SPMI" +#define ACPI_SIG_STAO "STAO" +#define ACPI_SIG_SWFT "SWFT" +#define ACPI_SIG_TCPA "TCPA" +#define ACPI_SIG_TPM2 "TPM2" +#define ACPI_SIG_UEFI "UEFI" +#define ACPI_SIG_WAET "WAET" +#define ACPI_SIG_WDAT "WDAT" +#define ACPI_SIG_WDDT "WDDT" +#define ACPI_SIG_WDRT "WDRT" +#define ACPI_SIG_WPBT "WPBT" +#define ACPI_SIG_WSMT "WSMT" +#define ACPI_SIG_XENV "XENV" + +/* MADT Interrupt Controller Structure types */ + +#define ACPI_MADT_TYPE_LOCAL_APIC (0) +#define ACPI_MADT_TYPE_IO_APIC (1) +#define ACPI_MADT_TYPE_LOCAL_APIC64 (5) +#define ACPI_MADT_TYPE_LOCAL_X2APIC (9) + +/* Local APIC Flags */ + +#define ACPI_LAPIC_FLAGS_ENABLED (1 << 0) +#define ACPI_LAPIC_FLAGS_ONLINECAP (1 << 1) +#define ACPI_LAPIC_FLAGS_RESERVED (0xfffffffc) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Root System Description Pointer (RSDP) Structure */ + +begin_packed_struct struct acpi_rsdp_s +{ + char signature[8]; /* "RSD PTR " sugnature */ + uint8_t checksum; /* ACPI 1.0 checksum */ + char oem_id[6]; /* An OEM-supplied string */ + uint8_t revision; /* The revision of this structure */ + uint32_t rsdt_addr; /* 32 bit physical address of the RSDT */ + uint32_t length; /* The length of the table */ + uint64_t xsdt_addr; /* 64 bit physical address of the XSDT */ + uint8_t ext_checksum; /* Extended checksum */ + uint8_t reserved[3]; /* Reserved field */ +} end_packed_struct; + +/* System Description Table Header */ + +begin_packed_struct struct acpi_sdt_s +{ + char signature[4]; /* Table ASCII identifier */ + uint32_t length; /* The length of the table in bytes */ + uint8_t revision; /* The revision of the structure */ + uint8_t checksum; /* The entire table checksum */ + char oem_id[6]; /* An OEM identification string */ + char oem_table_id[8]; /* An OEM data table string */ + uint32_t oem_revision; /* An OEM revision number */ + uint32_t creator_id; /* Vendor ID */ + uint32_t creator_revision; /* Vendor revision */ +} end_packed_struct; + +/* Root System Description Table */ + +begin_packed_struct struct acpi_rsdt_s +{ + struct acpi_sdt_s sdt; + uint32_t table_ptrs; +} end_packed_struct; + +/* Extended System Descriptior Table */ + +begin_packed_struct struct acpi_xsdt_s +{ + struct acpi_sdt_s sdt; + uint64_t table_ptrs; +} end_packed_struct; + +/* Common structure for tables entry */ + +begin_packed_struct struct acpi_entry_s +{ + uint8_t type; + uint8_t length; +} end_packed_struct; + +/* Multiple APIC Description Table */ + +begin_packed_struct struct acpi_madt_s +{ + struct acpi_sdt_s sdt; + uint32_t loapic; + uint32_t flags; + struct acpi_entry_s entries; +} end_packed_struct; + +/* Multiple APIC Description Table */ + +begin_packed_struct struct acpi_lapic_s +{ + struct acpi_entry_s entry; + uint8_t acpi_id; + uint8_t apic_id; + uint8_t flags; +} end_packed_struct; + +/* Configuration space base address allocation structure */ + +begin_packed_struct struct acpi_pciseg_s +{ + uint64_t base_addr; /* Base address */ + uint16_t seg_group_num; /* PCI Segment Group Number */ + uint8_t start_bus; /* Strt PCI bus number */ + uint8_t end_bus; /* End PCI bus number */ + uint32_t reserved; /* Reserved */ +} end_packed_struct; + +/* PCI Express Memory-mapped Configuration Table */ + +begin_packed_struct struct acpi_mcfg_s +{ + struct acpi_sdt_s sdt; /* Header */ + uint64_t reserved; /* Reserved */ + struct acpi_pciseg_s segs; /* Configuration space base addresses */ +} end_packed_struct; + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: acpi_init + * + * Description: + * Initialize ACPI parser. + * + ****************************************************************************/ + +int acpi_init(uintptr_t rsdp); + +/**************************************************************************** + * Name: acpi_madt_get + * + * Description: + * Find the n'th occurence of a MADT entry with a given type. + * + ****************************************************************************/ + +int acpi_madt_get(int type, int n, struct acpi_entry_s **entry); + +/**************************************************************************** + * Name: acpi_lapi_get + * + * Description: + * Get Local APIC entry for a given CPU. + * + ****************************************************************************/ + +int acpi_lapic_get(int cpu, struct acpi_lapic_s **lapic); + +#ifdef CONFIG_ARCH_X86_64_ACPI_DUMP +/**************************************************************************** + * Name: acpi_dump + * + * Description: + * Dump ACPI tables. + * + ****************************************************************************/ + +void acpi_dump(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_X86_64_INCLUDE_ACPI_H */ diff --git a/arch/x86_64/include/hpet.h b/arch/x86_64/include/hpet.h new file mode 100644 index 0000000000000..40627c82efcc6 --- /dev/null +++ b/arch/x86_64/include/hpet.h @@ -0,0 +1,96 @@ +/**************************************************************************** + * arch/x86_64/include/hpet.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_X86_64_INCLUDE_HPET_H +#define __ARCH_X86_64_INCLUDE_HPET_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register definitions */ + +#define HPET_GCAPID_OFFSET (0x00) +#define HPET_GCONF_OFFSET (0x10) +#define HPET_GISR_OFFSET (0x20) +#define HPET_MCNTR_OFFSET (0xf0) +#define HPET_TCONF_OFFSET(n) (0x100 + (0x20 * (n))) +#define HPET_TCOMP_OFFSET(n) (0x108 + (0x20 * (n))) +#define HPET_TFSB_OFFSET(n) (0x110 + (0x20 * (n))) + +/* General Capabilities and ID Register */ + +#define HPET_GCAPID_REVID_SHIFT (0ul) /* Bits 0-7: Revistion */ +# define HPET_GCAPID_REVID_MASK (0xfful << HPET_GCAPID_REVID_SHIFT) +#define HPET_GCAPID_NUMTIM_SHIFT (8ul) /* Bits 8-12: Number of Timers */ +#define HPET_GCAPID_NUMTIM_MASK (0x1ful << HPET_GCAPID_NUMTIM_SHIFT) +#define HPET_GCAPID_COUNTSIZE (1 << 13) /* Bit 13: Counter size, 0: 32 bit, 1: 64 bit */ + /* Bit 14: Reserved */ +#define HPET_GCAPID_LEGROUTE (1 << 15) /* Bit 15: LegacyReplacement Route Capable */ +#define HPET_GCAPID_VENDORID_SHIFT (16ul) /* Bits 16-31: Vendor ID */ +# define HPET_GCAPID_VENDORID_MASK (0x7ffful << HPET_GCAPID_VENDORID_SHIFT) +#define HPET_GCAPID_CLKPER_SHIFT (32ul) /* Bits 32-63: Main Counter Tick Period in ps */ +# define HPET_GCAPID_CLKPER_MASK (0x7ffffffful << HPET_GCAPID_CLKPER_SHIFT) + +/* General Configuration Register */ + +#define HPET_GCONF_LEGERT (1 << 0) /* Bit 0: LegacyReplacement Route */ +#define HPET_GCONF_ENABLE (1 << 1) /* Bit 1: Overall Enable */ + +/* General Interrupt Status Register */ + +#define HPET_GISR_TINT(n) (1 << (n)) /* Timer n Interrupt Active */ + +/* Timer N Configuration and Capabilities Register */ + + /* Bit 0: Reserved */ +#define HPET_TCONF_INTTYPE (1 << 1) /* Bit 1: Timer n Interrupt Type (0: edge, 1: level) */ +#define HPET_TCONF_INTEN (1 << 2) /* Bit 2: Timer n Interrupt Enable */ +#define HPET_TCONF_TYPE (1 << 3) /* Bit 3: Timer n Type (0: non-periodic, 1: periodic) */ +#define HPET_TCONF_PERCAP (1 << 4) /* Bit 4: Timer n Periodic Interrupt Capable */ +#define HPET_TCONF_SIZECAP (1 << 5) /* Bit 5: Timer n Size */ +#define HPET_TCONF_VALSET (1 << 6) /* Bit 6: Timer n Value Set */ + /* Bit 7: Reserved */ +#define HPET_TCONF_32MODE (1 << 8) /* Bit 8: Timer n 32-bit mode */ +#define HPET_TCONF_INTROUTE_SHIFT (9) /* Bits 9-13: Timer n Interrupt Route */ +# define HPET_TCONF_INTROUTE_MASK (0x7f << HPET_TCONF_INTROUTE_SHIFT) +# define HPET_TCONF_INTROUTE(n) (((n) << HPET_TCONF_INTROUTE_SHIFT) & HPET_TCONF_INTROUTE_MASK) +#define HPET_TCONF_FSBEN (1 << 14) /* Bit 14: Timer n FSB Interrupt Enable */ +#define HPET_TCONF_FSBCAP (1 << 15) /* Bit 15: Timer n FSB Interrupt Delivery */ + /* Bits 16-31: Reserved */ +#define HPET_TCONF_ROUTECAP_SHIFT (32) /* Bits 32-63: Timer n Interrupt Routing Capability */ +# define HPET_TCONF_ROUTECAP_MASK (0x7ffffffful << HPET_TCONF_ROUTECAP_SHIFT) + +/* Timer N FSB Interrupt Route Register */ + +#define HPET_TFSB_INT_VAL_SHIFT (0) +#define HPET_TFSB_INT_VAL_MASK (0x00000000ffffffff) +#define HPET_TFSB_INT_ADDR_SHIFT (31) +#define HPET_TFSB_INT_ADDR_MASK (0xffffffff00000000) + +/* HPET register space */ + +#define HPET_REGION_SIZE (1024) + +#endif /* __ARCH_X86_64_INCLUDE_HPET_H */ diff --git a/arch/x86_64/include/intel64/arch.h b/arch/x86_64/include/intel64/arch.h index e6855518223c0..fd85fcc4377b7 100644 --- a/arch/x86_64/include/intel64/arch.h +++ b/arch/x86_64/include/intel64/arch.h @@ -135,14 +135,31 @@ /* CPUID Leaf Definitions */ -#define X86_64_CPUID_CAP 0x01 -# define X86_64_CPUID_01_SSE3 (1 << 0) -# define X86_64_CPUID_01_PCID (1 << 17) -# define X86_64_CPUID_01_X2APIC (1 << 21) -# define X86_64_CPUID_01_TSCDEA (1 << 24) -# define X86_64_CPUID_01_XSAVE (1 << 26) -# define X86_64_CPUID_01_RDRAND (1 << 30) -#define X86_64_CPUID_TSC 0x15 +#define X86_64_CPUID_VENDOR 0x00 +#define X86_64_CPUID_CAP 0x01 +# define X86_64_CPUID_01_SSE3 (1 << 0) +# define X86_64_CPUID_01_SSSE3 (1 << 9) +# define X86_64_CPUID_01_PCID (1 << 17) +# define X86_64_CPUID_01_SSE41 (1 << 19) +# define X86_64_CPUID_01_SSE42 (1 << 20) +# define X86_64_CPUID_01_X2APIC (1 << 21) +# define X86_64_CPUID_01_TSCDEA (1 << 24) +# define X86_64_CPUID_01_XSAVE (1 << 26) +# define X86_64_CPUID_01_RDRAND (1 << 30) +# define X86_64_CPUID_01_APICID(ebx) ((ebx) >> 24) +#define X86_64_CPUID_EXTCAP 0x07 +# define X86_64_CPUID_07_AVX2 (1 << 5) +# define X86_64_CPUID_07_AVX512F (1 << 16) +# define X86_64_CPUID_07_AVX512DQ (1 << 17) +# define X86_64_CPUID_07_SMAP (1 << 20) +# define X86_64_CPUID_07_AVX512IFMA (1 << 21) +# define X86_64_CPUID_07_CLWB (1 << 24) +# define X86_64_CPUID_07_AVX512PF (1 << 26) +# define X86_64_CPUID_07_AVX512ER (1 << 27) +# define X86_64_CPUID_07_AVX512CD (1 << 28) +# define X86_64_CPUID_07_AVX512BW (1 << 30) +# define X86_64_CPUID_07_AVX512VL (1 << 31) +#define X86_64_CPUID_TSC 0x15 /* MSR Definitions */ @@ -248,6 +265,13 @@ #define BITS_PER_LONG 64 +/* Reset Control Register (RST_CNT) */ + +#define X86_RST_CNT_REG 0xcf9 +# define X86_RST_CNT_SYS_RST 0x02 +# define X86_RST_CNT_CPU_RST 0x04 +# define X86_RST_CNT_FULL_RST 0x08 + #ifndef __ASSEMBLY__ /**************************************************************************** @@ -342,8 +366,7 @@ begin_packed_struct struct ist_s uint64_t IST6; /* Interrupt Stack 6 */ uint64_t IST7; /* Interrupt Stack 7 */ uint64_t reserved3; /* reserved */ - uint64_t reserved4; /* reserved */ - uint16_t reserved5; /* reserved */ + uint16_t reserved4; /* reserved */ uint16_t IOPB_OFFSET; /* IOPB_offset */ } end_packed_struct; @@ -357,25 +380,25 @@ begin_packed_struct struct ist_s /* These are defined in intel64_head.S */ -extern volatile uint8_t pdpt_low; -extern volatile uint8_t pd_low; -extern volatile uint8_t pt_low; +extern volatile uint8_t g_pdpt_low; +extern volatile uint8_t g_pd_low; +extern volatile uint8_t g_pt_low; -extern volatile uint8_t ist64_low; -extern volatile uint8_t gdt64_low; -extern volatile uint8_t gdt64_ist_low; -extern volatile uint8_t gdt64_low_end; +extern volatile uint8_t g_ist64_low; +extern volatile uint8_t g_gdt64_low; +extern volatile uint8_t g_gdt64_ist_low; +extern volatile uint8_t g_gdt64_low_end; /* The actual address of the page table and gdt/ist after mapping the kernel * in high address */ -extern volatile uint64_t *pdpt; -extern volatile uint64_t *pd; -extern volatile uint64_t *pt; +extern volatile uint64_t *g_pdpt; +extern volatile uint64_t *g_pd; +extern volatile uint64_t *g_pt; -extern volatile struct ist_s *ist64; -extern volatile struct gdt_entry_s *gdt64; +extern volatile struct ist_s *g_ist64; +extern volatile struct gdt_entry_s *g_gdt64; /**************************************************************************** * Public Function Prototypes diff --git a/arch/x86_64/include/intel64/irq.h b/arch/x86_64/include/intel64/irq.h index 55786caa5095d..f91ce9772f9eb 100644 --- a/arch/x86_64/include/intel64/irq.h +++ b/arch/x86_64/include/intel64/irq.h @@ -93,18 +93,264 @@ #define IRQ13 45 /* Math coprocessor */ #define IRQ14 46 /* Primary ATA channel */ #define IRQ15 47 /* Secondary ATA channel */ +#define IRQ16 48 +#define IRQ17 49 +#define IRQ18 50 +#define IRQ19 51 +#define IRQ20 52 +#define IRQ21 53 +#define IRQ22 54 +#define IRQ23 55 +#define IRQ24 56 +#define IRQ25 57 +#define IRQ26 58 +#define IRQ27 59 +#define IRQ28 60 +#define IRQ29 61 +#define IRQ30 62 +#define IRQ31 63 +#define IRQ32 64 +#define IRQ33 65 +#define IRQ34 66 +#define IRQ35 67 +#define IRQ36 68 +#define IRQ37 69 +#define IRQ38 70 +#define IRQ39 71 +#define IRQ40 72 +#define IRQ41 73 +#define IRQ42 74 +#define IRQ43 75 +#define IRQ44 76 +#define IRQ45 77 +#define IRQ46 78 +#define IRQ47 79 +#define IRQ48 80 +#define IRQ49 81 +#define IRQ50 82 +#define IRQ51 83 +#define IRQ52 84 +#define IRQ53 85 +#define IRQ54 86 +#define IRQ55 87 +#define IRQ56 88 +#define IRQ57 89 +#define IRQ58 90 +#define IRQ59 91 +#define IRQ60 92 +#define IRQ61 93 +#define IRQ62 94 +#define IRQ63 95 +#define IRQ64 96 +#define IRQ65 97 +#define IRQ66 98 +#define IRQ67 99 +#define IRQ68 100 +#define IRQ69 101 +#define IRQ70 102 +#define IRQ71 103 +#define IRQ72 104 +#define IRQ73 105 +#define IRQ74 106 +#define IRQ75 107 +#define IRQ76 108 +#define IRQ77 109 +#define IRQ78 110 +#define IRQ79 111 +#define IRQ80 112 +#define IRQ81 113 +#define IRQ82 114 +#define IRQ83 115 +#define IRQ84 116 +#define IRQ85 117 +#define IRQ86 118 +#define IRQ87 119 +#define IRQ88 120 +#define IRQ89 121 +#define IRQ90 122 +#define IRQ91 123 +#define IRQ92 124 +#define IRQ93 125 +#define IRQ94 126 +#define IRQ95 127 +#define IRQ96 128 +#define IRQ97 129 +#define IRQ98 130 +#define IRQ99 131 +#define IRQ100 132 +#define IRQ101 133 +#define IRQ102 134 +#define IRQ103 135 +#define IRQ104 136 +#define IRQ105 137 +#define IRQ106 138 +#define IRQ107 139 +#define IRQ108 140 +#define IRQ109 141 +#define IRQ110 142 +#define IRQ111 143 +#define IRQ112 144 +#define IRQ113 145 +#define IRQ114 146 +#define IRQ115 147 +#define IRQ116 148 +#define IRQ117 149 +#define IRQ118 150 +#define IRQ119 151 +#define IRQ120 152 +#define IRQ121 153 +#define IRQ122 154 +#define IRQ123 155 +#define IRQ124 156 +#define IRQ125 157 +#define IRQ126 158 +#define IRQ127 159 +#define IRQ128 160 +#define IRQ129 161 +#define IRQ130 162 +#define IRQ131 163 +#define IRQ132 164 +#define IRQ133 165 +#define IRQ134 166 +#define IRQ135 167 +#define IRQ136 168 +#define IRQ137 169 +#define IRQ138 170 +#define IRQ139 171 +#define IRQ140 172 +#define IRQ141 173 +#define IRQ142 174 +#define IRQ143 175 +#define IRQ144 176 +#define IRQ145 177 +#define IRQ146 178 +#define IRQ147 179 +#define IRQ148 180 +#define IRQ149 181 +#define IRQ150 182 +#define IRQ151 183 +#define IRQ152 184 +#define IRQ153 185 +#define IRQ154 186 +#define IRQ155 187 +#define IRQ156 188 +#define IRQ157 189 +#define IRQ158 190 +#define IRQ159 191 +#define IRQ160 192 +#define IRQ161 193 +#define IRQ162 194 +#define IRQ163 195 +#define IRQ164 196 +#define IRQ165 197 +#define IRQ166 198 +#define IRQ167 199 +#define IRQ168 200 +#define IRQ169 201 +#define IRQ170 202 +#define IRQ171 203 +#define IRQ172 204 +#define IRQ173 205 +#define IRQ174 206 +#define IRQ175 207 +#define IRQ176 208 +#define IRQ177 209 +#define IRQ178 210 +#define IRQ179 211 +#define IRQ180 212 +#define IRQ181 213 +#define IRQ182 214 +#define IRQ183 215 +#define IRQ184 216 +#define IRQ185 217 +#define IRQ186 218 +#define IRQ187 219 +#define IRQ188 220 +#define IRQ189 221 +#define IRQ190 222 +#define IRQ191 223 +#define IRQ192 224 +#define IRQ193 225 +#define IRQ194 226 +#define IRQ195 227 +#define IRQ196 228 +#define IRQ197 229 +#define IRQ198 230 +#define IRQ199 231 +#define IRQ200 232 +#define IRQ201 233 +#define IRQ202 234 +#define IRQ203 235 +#define IRQ204 236 +#define IRQ205 237 +#define IRQ206 238 +#define IRQ207 239 +#define IRQ208 240 +#define IRQ209 241 +#define IRQ210 242 +#define IRQ211 243 +#define IRQ212 244 +#define IRQ213 245 +#define IRQ214 246 +#define IRQ215 247 +#define IRQ216 248 +#define IRQ217 249 +#define IRQ218 250 +#define IRQ219 251 +#define IRQ220 252 +#define IRQ221 253 +#define IRQ222 254 +#define IRQ223 255 +#define IRQ224 256 +#define IRQ225 257 +#define IRQ226 258 +#define IRQ227 259 +#define IRQ228 260 +#define IRQ229 261 +#define IRQ230 262 +#define IRQ231 263 +#define IRQ232 264 +#define IRQ233 265 +#define IRQ234 266 +#define IRQ235 267 +#define IRQ236 268 +#define IRQ237 269 +#define IRQ238 270 +#define IRQ239 271 +#define IRQ240 272 +#define IRQ241 273 +#define IRQ242 274 +#define IRQ243 275 +#define IRQ244 276 +#define IRQ245 277 +#define IRQ246 278 +#define IRQ247 279 +#define IRQ248 280 +#define IRQ249 281 +#define IRQ250 282 +#define IRQ251 283 +#define IRQ252 284 +#define IRQ253 285 +#define IRQ254 286 +#define IRQ255 287 + +#define NR_IRQS 288 +#define MAX_NR_IRQS 255 #define IRQ_ERROR 51 /* APIC Error */ #define IRQ_SPURIOUS 0xff /* Spurious Interrupts */ -#define NR_IRQS 48 +/* Use legacy routing for HPET */ + +#define HPET0_IRQ IRQ2 +#define HPET1_IRQ IRQ8 /* Common register save structure created by up_saveusercontext() and by * ISR/IRQ interrupt processing. */ #define XCPTCONTEXT_XMM_AREA_SIZE 512 -#define XMMAREA_OFFSET XCPTCONTEXT_XMM_AREA_SIZE / 8 +#define XMMAREA_OFFSET (XCPTCONTEXT_XMM_AREA_SIZE / 8) /* Data segments */ diff --git a/arch/x86_64/include/irq.h b/arch/x86_64/include/irq.h index 80994301bed0c..2e1e81fe5cd3d 100644 --- a/arch/x86_64/include/irq.h +++ b/arch/x86_64/include/irq.h @@ -59,7 +59,7 @@ #ifndef __ASSEMBLY__ /* This holds a references to the current interrupt level register storage - * structure. If is non-NULL only during interrupt processing. + * structure. It is non-NULL only during interrupt processing. */ extern volatile uint64_t *g_current_regs; diff --git a/arch/x86_64/include/spinlock.h b/arch/x86_64/include/spinlock.h new file mode 100644 index 0000000000000..ac5b7d8b4f500 --- /dev/null +++ b/arch/x86_64/include/spinlock.h @@ -0,0 +1,98 @@ +/**************************************************************************** + * arch/x86_64/include/spinlock.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_X86_64_INCLUDE_SPINLOCK_H +#define __ARCH_X86_64_INCLUDE_SPINLOCK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Spinlock states */ + +#define SP_UNLOCKED 0 /* The Un-locked state */ +#define SP_LOCKED 1 /* The Locked state */ + +/* Memory barriers for use with NuttX spinlock logic + * + * Data Memory Barrier (DMB) acts as a memory barrier. It ensures that all + * explicit memory accesses that appear in program order before the DMB + * instruction are observed before any explicit memory accesses that appear + * in program order after the DMB instruction. It does not affect the + * ordering of any other instructions executing on the processor + * + * Data Synchronization Barrier (DSB) acts as a special kind of memory + * barrier. No instruction in program order after this instruction executes + * until this instruction completes. This instruction completes when: (1) All + * explicit memory accesses before this instruction complete, and (2) all + * Cache, Branch predictor and TLB maintenance operations before this + * instruction complete. + * + */ + +#define SP_DSB(n) __asm__ __volatile__ ("mfence") +#define SP_DMB(n) __asm__ __volatile__ ("mfence") + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* The Type of a spinlock */ + +typedef uintptr_t spinlock_t; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: up_testset + * + * Description: + * Perform an atomic test and set operation on the provided spinlock. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * lock - The address of spinlock object. + * + * Returned Value: + * The spinlock is always locked upon return. The value of previous value + * of the spinlock variable is returned, either SP_LOCKED if the spinlock + * as previously locked (meaning that the test-and-set operation failed to + * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked + * (meaning that we successfully obtained the lock) + * + ****************************************************************************/ + +/* See prototype in nuttx/include/nuttx/spinlock.h */ + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_X86_64_INCLUDE_SPINLOCK_H */ diff --git a/arch/x86_64/src/CMakeLists.txt b/arch/x86_64/src/CMakeLists.txt new file mode 100644 index 0000000000000..a485b1ac7cce7 --- /dev/null +++ b/arch/x86_64/src/CMakeLists.txt @@ -0,0 +1,33 @@ +# ############################################################################## +# arch/x86_64/src/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(${ARCH_SUBDIR}) +add_subdirectory(${NUTTX_CHIP_ABS_DIR} EXCLUDE_FROM_ALL exclude_chip) +add_subdirectory(common) + +# Include directories (before system ones) as PUBLIC so that it can be exposed +# to libboard +target_include_directories(arch BEFORE PUBLIC ${NUTTX_CHIP_ABS_DIR} common + ${ARCH_SUBDIR}) + +if(NOT CONFIG_BUILD_FLAT) + target_include_directories(arch_interface BEFORE PUBLIC ${NUTTX_CHIP_ABS_DIR} + common ${ARCH_SUBDIR}) +endif() diff --git a/arch/x86_64/src/Makefile b/arch/x86_64/src/Makefile index b37f96f679d02..0c97c4bc6bfdc 100644 --- a/arch/x86_64/src/Makefile +++ b/arch/x86_64/src/Makefile @@ -18,7 +18,7 @@ # ############################################################################ -include $(TOPDIR)/Make.defs +include $(TOPDIR)/tools/apps-or-nuttx-Make.defs include chip/Make.defs ifeq ($(CONFIG_ARCH_INTEL64),y) diff --git a/arch/x86_64/src/cmake/Toolchain.cmake b/arch/x86_64/src/cmake/Toolchain.cmake new file mode 100644 index 0000000000000..1bd11bca4b466 --- /dev/null +++ b/arch/x86_64/src/cmake/Toolchain.cmake @@ -0,0 +1,144 @@ +# ############################################################################## +# arch/x86_64/src/cmake/Toolchain.cmake +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +# Toolchain + +set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_VERSION 1) + +set(ARCH_SUBDIR intel64) + +# override the ARCHIVE command + +set(CMAKE_C_ARCHIVE_CREATE " rcs ") +set(CMAKE_CXX_ARCHIVE_CREATE " rcs ") +set(CMAKE_ASM_ARCHIVE_CREATE " rcs ") + +if(CONFIG_DEBUG_CUSTOMOPT) + add_compile_options(${CONFIG_DEBUG_OPTLEVEL}) +elseif(CONFIG_DEBUG_FULLOPT) + add_compile_options(-Os) +endif() + +if(NOT CONFIG_DEBUG_NOOPT) + add_compile_options(-fno-strict-aliasing) +endif() + +# NOTE: don't set -fomit-frame-pointer - it breaks debugging with gdb. The +# addresses of local variables are shifted in gdb if this option is enabled + +if(CONFIG_FRAME_POINTER) + add_compile_options(-fno-omit-frame-pointer -fno-optimize-sibling-calls) +endif() + +if(CONFIG_STACK_CANARIES) + add_compile_options(-fstack-protector-all) +else() + add_compile_options(-fno-stack-protector) +endif() + +if(CONFIG_STACK_USAGE) + add_compile_options(-fstack-usage) +endif() + +if(${CONFIG_STACK_USAGE_WARNING}) + if(NOT ${CONFIG_STACK_USAGE_WARNING} STREQUAL 0) + add_compile_options(-Wstack-usage=${CONFIG_STACK_USAGE_WARNING}) + endif() +endif() + +if(CONFIG_ARCH_COVERAGE) + add_compile_options(-fprofile-generate -ftest-coverage) +endif() + +if(CONFIG_DEBUG_SYMBOLS) + add_compile_options(-g) +endif() + +# Architecture flags + +add_link_options(-Wl,--entry=__pmode_entry) +add_link_options(-z max-page-size=0x1000) +add_link_options(-no-pie -nostdlib) +add_link_options(-Wl,--no-relax) +add_compile_options(-fPIC) +add_compile_options(-mno-red-zone) + +if(CONFIG_DEBUG_LINK_MAP) + add_link_options(-Wl,--cref -Wl,-Map=nuttx.map) +endif() + +set(ARCHCFLAGS + "-Wstrict-prototypes -fno-common -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas" +) +set(ARCHCXXFLAGS + "-fno-common -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas") + +if(NOT CONFIG_LIBCXXTOOLCHAIN) + set(ARCHCXXFLAGS "${ARCHCXXFLAGS} -nostdinc++") +endif() + +if(NOT CONFIG_CXX_EXCEPTION) + string(APPEND ARCHCXXFLAGS " -fno-exceptions -fcheck-new") +endif() + +if(NOT CONFIG_CXX_RTTI) + string(APPEND ARCHCXXFLAGS " -fno-rtti") +endif() + +if(NOT "${CMAKE_C_FLAGS}" STREQUAL "") + string(REGEX MATCH "${ARCHCFLAGS}" EXISTS_FLAGS "${CMAKE_C_FLAGS}") +endif() + +if(NOT EXISTS_FLAGS) + set(CMAKE_ASM_FLAGS + "${CMAKE_ASM_FLAGS} ${ARCHCFLAGS}" + CACHE STRING "" FORCE) + set(CMAKE_C_FLAGS + "${CMAKE_C_FLAGS} ${ARCHCFLAGS}" + CACHE STRING "" FORCE) + set(CMAKE_CXX_FLAGS + "${CMAKE_CXX_FLAGS} ${ARCHCXXFLAGS}" + CACHE STRING "" FORCE) +endif() + +if(CONFIG_ARCH_INTEL64_HAVE_RDRAND) + add_compile_options(-mrdrnd) +endif() + +if(CONFIG_ARCH_X86_64_SSE3) + add_compile_options(-msse3) +endif() + +if(CONFIG_ARCH_X86_64_SSSE3) + add_compile_options(-mssse3) +endif() + +if(CONFIG_ARCH_X86_64_SSE41) + add_compile_options(-msse4.1) +endif() + +if(CONFIG_ARCH_X86_64_SSE42) + add_compile_options(-msse4.2) +endif() + +if(CONFIG_ARCH_X86_64_SSE4A) + add_compile_options(-msse4a) +endif() diff --git a/arch/x86_64/src/cmake/platform.cmake b/arch/x86_64/src/cmake/platform.cmake new file mode 100644 index 0000000000000..5e53d971d08d1 --- /dev/null +++ b/arch/x86_64/src/cmake/platform.cmake @@ -0,0 +1,62 @@ +# ############################################################################## +# arch/x86_64/src/cmake/platform.cmake +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +get_directory_property(NUTTX_EXTRA_FLAGS DIRECTORY ${CMAKE_SOURCE_DIR} + COMPILE_OPTIONS) + +execute_process( + COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} ${NUTTX_EXTRA_FLAGS} + --print-libgcc-file-name + OUTPUT_STRIP_TRAILING_WHITESPACE + OUTPUT_VARIABLE extra_library) + +list(APPEND EXTRA_LIB ${extra_library}) + +if(CONFIG_LIBM_TOOLCHAIN) + execute_process( + COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} ${NUTTX_EXTRA_FLAGS} + --print-file-name=libm.a + OUTPUT_STRIP_TRAILING_WHITESPACE + OUTPUT_VARIABLE extra_library) + list(APPEND EXTRA_LIB ${extra_library}) +endif() + +if(CONFIG_LIBSUPCXX) + execute_process( + COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} ${NUTTX_EXTRA_FLAGS} + --print-file-name=libsupc++.a + OUTPUT_STRIP_TRAILING_WHITESPACE + OUTPUT_VARIABLE extra_library) + list(APPEND EXTRA_LIB ${extra_library}) +endif() + +if(CONFIG_ARCH_COVERAGE) + execute_process( + COMMAND ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} ${NUTTX_EXTRA_FLAGS} + --print-file-name=libgcov.a + OUTPUT_STRIP_TRAILING_WHITESPACE + OUTPUT_VARIABLE extra_library) + list(APPEND EXTRA_LIB ${extra_library}) +endif() + +nuttx_add_extra_library(${EXTRA_LIB}) + +separate_arguments(CMAKE_C_FLAG_ARGS NATIVE_COMMAND ${CMAKE_C_FLAGS}) +set(PREPROCES ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} -E -P -x c) diff --git a/arch/x86_64/src/common/CMakeLists.txt b/arch/x86_64/src/common/CMakeLists.txt new file mode 100644 index 0000000000000..f50ff808e309a --- /dev/null +++ b/arch/x86_64/src/common/CMakeLists.txt @@ -0,0 +1,44 @@ +# ############################################################################## +# arch/x86_64/src/common/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS + x86_64_allocateheap.c + x86_64_copystate.c + x86_64_exit.c + x86_64_getintstack.c + x86_64_mdelay.c + x86_64_initialize.c + x86_64_modifyreg8.c + x86_64_modifyreg16.c + x86_64_modifyreg32.c + x86_64_nputs.c + x86_64_switchcontext.c + x86_64_udelay.c + x86_64_tcbinfo.c) + +if(CONFIG_PCI) + list(APPEND SRCS x86_64_pci.c) +endif() + +if(CONFIG_ARCH_X86_64_ACPI) + list(APPEND SRCS x86_64_acpi.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/x86_64/src/common/Kconfig b/arch/x86_64/src/common/Kconfig index 6dcd0d64f9695..fc4235a69b0e0 100644 --- a/arch/x86_64/src/common/Kconfig +++ b/arch/x86_64/src/common/Kconfig @@ -6,4 +6,76 @@ if ARCH_X86_64 comment "Common Configuration Options" +config ARCH_X86_64_ACPI + bool "ACPI support" + default y + ---help--- + Select to enable ACPI parser. + +if ARCH_X86_64_ACPI + +config ARCH_X86_64_ACPI_DUMP + bool "ACPI dump" + default DEBUG_FEATURES + ---help--- + Select to dump ACPI tables. + +config ARCH_X86_64_ACPI_BIOS + bool "Look for ACPI RSDP in BIOS legacy region" + default y + ---help--- + Look for RSDP in BIOS legacy region (0x000e0000-0x000fffff). + +endif # ARCH_X86_64_ACPI + +config ARCH_X86_64_MMX + bool "MMX support" + depends on ARCH_HAVE_MMX + default y + +config ARCH_X86_64_SSE + bool "SSE support" + depends on ARCH_HAVE_SSE + default y + +config ARCH_X86_64_SSE2 + bool "SSE2 support" + depends on ARCH_HAVE_SSE2 + default y + +config ARCH_X86_64_SSE3 + bool "SSE3 support" + depends on ARCH_HAVE_SSE3 + default n + +config ARCH_X86_64_SSSE3 + bool "SSSE3 support" + depends on ARCH_HAVE_SSSE3 + default n + +config ARCH_X86_64_SSE41 + bool "SSE41 support" + depends on ARCH_HAVE_SSE41 + default n + +config ARCH_X86_64_SSE42 + bool "SSE42 support" + depends on ARCH_HAVE_SSE42 + default n + +config ARCH_X86_64_SSE4A + bool "SSE4A support" + depends on ARCH_HAVE_SSE4A + default n + +config ARCH_X86_64_AVX + bool "AVX support" + depends on ARCH_HAVE_AVX + default n + +config ARCH_X86_64_AVX512 + bool "AVX512 support" + depends on ARCH_HAVE_AVX512 + default n + endif diff --git a/arch/x86_64/src/common/Make.defs b/arch/x86_64/src/common/Make.defs new file mode 100644 index 0000000000000..12db901b99fc6 --- /dev/null +++ b/arch/x86_64/src/common/Make.defs @@ -0,0 +1,34 @@ +############################################################################ +# arch/x86_64/src/common/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Common x86_64 files + +CMN_CSRCS += x86_64_allocateheap.c x86_64_copystate.c x86_64_exit.c +CMN_CSRCS += x86_64_getintstack.c x86_64_mdelay.c x86_64_initialize.c +CMN_CSRCS += x86_64_modifyreg8.c x86_64_modifyreg16.c x86_64_modifyreg32.c +CMN_CSRCS += x86_64_nputs.c x86_64_switchcontext.c x86_64_udelay.c + +ifeq ($(CONFIG_PCI),y) +CMN_CSRCS += x86_64_pci.c +endif + +ifeq ($(CONFIG_ARCH_X86_64_ACPI),y) +CMN_CSRCS += x86_64_acpi.c +endif diff --git a/arch/x86_64/src/common/Toolchain.defs b/arch/x86_64/src/common/Toolchain.defs new file mode 100644 index 0000000000000..68ef67cf5fc89 --- /dev/null +++ b/arch/x86_64/src/common/Toolchain.defs @@ -0,0 +1,83 @@ +############################################################################ +# arch/x86_64/src/common/Toolchain.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifeq ($(CONFIG_DEBUG_CUSTOMOPT),y) + ARCHOPTIMIZATION += $(CONFIG_DEBUG_OPTLEVEL) +else ifeq ($(CONFIG_DEBUG_FULLOPT),y) + ARCHOPTIMIZATION += -Os +endif + +ARCHCPUFLAGS = -fPIC -fno-stack-protector -mno-red-zone -mrdrnd +ARCHPICFLAGS = -fPIC +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef + +# We have to use a cross-development toolchain under Cygwin because the native +# Cygwin toolchains don't generate ELF binaries. + +ifeq ($(CONFIG_WINDOWS_CYGWIN),y) +CROSSDEV = i486-nuttx-elf- +endif + +ifeq ($(CONFIG_HOST_MACOS),y) +CROSSDEV = x86_64-elf- +endif + +CC = $(CROSSDEV)gcc +CPP = $(CROSSDEV)gcc -E -x c +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +CFLAGS := $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +ifeq ($(CONFIG_HOST_MACOS),y) +AFLAGS += -Wa,--divide +endif + +EXEEXT = .elf + +ifeq ($(CONFIG_ARCH_X86_64_SSE3),y) + ARCHCPUFLAGS += -msse3 +endif + +ifeq ($(CONFIG_ARCH_X86_64_SSSE3),y) + ARCHCPUFLAGS += -mssse3 +endif + +ifeq ($(CONFIG_ARCH_X86_64_SSE41),y) + ARCHCPUFLAGS += -msse41 +endif + +ifeq ($(CONFIG_ARCH_X86_64_SSE42),y) + ARCHCPUFLAGS += -msse42 +endif + +ifeq ($(CONFIG_ARCH_X86_64_SSE4a),y) + ARCHCPUFLAGS += -msse4a +endif diff --git a/arch/x86_64/src/common/x86_64_acpi.c b/arch/x86_64/src/common/x86_64_acpi.c new file mode 100644 index 0000000000000..aff0d797b1570 --- /dev/null +++ b/arch/x86_64/src/common/x86_64_acpi.c @@ -0,0 +1,660 @@ +/**************************************************************************** + * arch/x86_64/src/common/x86_64_acpi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "x86_64_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ACPI_BIOS_MEM_START (0x000e0000) +#define ACPI_BIOS_MEM_END (0x000fffff) +#define ACPI_BIOS_MEM_SIZE (ACPI_BIOS_MEM_END - ACPI_BIOS_MEM_START) +#define ACPI_PAGE_FLAGS (X86_PAGE_PRESENT | X86_PAGE_WR | X86_PAGE_NOCACHE) + +/* Debug macros */ + +#define acpi_info _info +#define acpi_err _err +#define acpi_warn _warn + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct acpi_s +{ + struct acpi_rsdp_s *rsdp; + struct acpi_rsdt_s *rsdt; + struct acpi_xsdt_s *xsdt; + struct acpi_madt_s *madt; + struct acpi_mcfg_s *mcfg; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct acpi_s g_acpi; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: acpi_map_region + * + * Description: + * Map ACPI region. + * + ****************************************************************************/ + +static void acpi_map_region(uintptr_t addr, size_t size) +{ + /* Map region */ + + up_map_region((void *)addr, size, ACPI_PAGE_FLAGS); +} + +/**************************************************************************** + * Name: acpi_map_rsdt + * + * Description: + * Map all ACPI tables. + * + ****************************************************************************/ + +static void acpi_map_rsdt(void) +{ + void *tps = NULL; + uint32_t *tp32 = NULL; + uint32_t *end32 = NULL; + + tps = &g_acpi.rsdt->table_ptrs; + tp32 = (uint32_t *)tps; + end32 = (uint32_t *)((uintptr_t)g_acpi.rsdt + g_acpi.rsdt->sdt.length); + + while (tp32 < end32) + { + acpi_map_region((uintptr_t)*tp32, + sizeof(struct acpi_sdt_s)); + + /* Next table */ + + tp32 += 1; + } +} + +/**************************************************************************** + * Name: acpi_map_xsdt + * + * Description: + * Map all ACPI tables. + * + ****************************************************************************/ + +static void acpi_map_xsdt(void) +{ + void *tps = NULL; + uint64_t *tp64 = NULL; + uint64_t *end64 = NULL; + + tps = &g_acpi.rsdt->table_ptrs; + tp64 = (uint64_t *)tps; + end64 = (uint64_t *)((uintptr_t)g_acpi.xsdt + g_acpi.xsdt->sdt.length); + + while (tp64 < end64) + { + acpi_map_region((uintptr_t)*tp64, + sizeof(struct acpi_sdt_s)); + + /* Next table */ + + tp64 += 1; + } +} + +/**************************************************************************** + * Name: acpi_sdt_checksum + * + * Description: + * Verify checksum. + * + ****************************************************************************/ + +static bool acpi_sdt_checksum(struct acpi_sdt_s *sdt) +{ + uint8_t *ptr = (uint8_t *)sdt; + uint8_t sum = 0; + uint32_t i = 0; + + for (i = 0; i < sdt->length; i++) + { + sum += ptr[i]; + } + + return sum == 0; +} + +/**************************************************************************** + * Name: acpi_rsdp_parse + * + * Description: + * Parse RSDP. + * + ****************************************************************************/ + +static int acpi_rsdp_parse(struct acpi_rsdp_s *rsdp) +{ + uint8_t *ptr = (uint8_t *)rsdp; + uint8_t sum = 0; + uint32_t len = 0; + uint32_t i = 0; + + /* Checksum */ + + len = rsdp->revision < 2 ? 20 : rsdp->length; + for (i = 0; i < len; i++) + { + sum += ptr[i]; + } + + if (sum != 0) + { + return -EINVAL; + } + + /* Parse RSDT table */ + + if (rsdp->rsdt_addr != 0) + { + struct acpi_rsdt_s *rsdt = NULL; + + acpi_map_region((uintptr_t)rsdp->rsdt_addr, + sizeof(struct acpi_rsdt_s)); + + rsdt = (struct acpi_rsdt_s *)(uintptr_t)rsdp->rsdt_addr; + + /* Verify checksum */ + + if (!acpi_sdt_checksum(&rsdt->sdt)) + { + return -EINVAL; + } + + /* Store pointer */ + + g_acpi.rsdt = rsdt; + + /* Map all tables */ + + acpi_map_rsdt(); + } + + /* Parse XSDT table if RSDT not available */ + + else if (rsdp->xsdt_addr != 0) + { + struct acpi_xsdt_s *xsdt = NULL; + + acpi_map_region((uintptr_t)rsdp->xsdt_addr, + sizeof(struct acpi_xsdt_s)); + + xsdt = (struct acpi_xsdt_s *)rsdp->xsdt_addr; + + /* Verify checksum */ + + if (!acpi_sdt_checksum(&xsdt->sdt)) + { + return -EINVAL; + } + + /* Store pointer */ + + g_acpi.xsdt = xsdt; + + /* Map all talbes */ + + acpi_map_xsdt(); + } + + return OK; +} + +#ifdef CONFIG_ARCH_X86_64_ACPI_BIOS +/**************************************************************************** + * Name: acpi_rsdp_find_bios + * + * Description: + * Find RSDP in BIOS region. + * + ****************************************************************************/ + +static bool acpi_rsdp_find_bios(struct acpi_s *acpi) +{ + char *now = (char *)ACPI_BIOS_MEM_START; + char *end = (char *)ACPI_BIOS_MEM_END; + + /* Map BIOS region */ + + acpi_map_region((uintptr_t)ACPI_BIOS_MEM_START, + ACPI_BIOS_MEM_SIZE); + + acpi->rsdp = NULL; + + while (now < end) + { + if (strncmp(now, ACPI_SIG_RSDP, sizeof(ACPI_SIG_RSDP) - 1) == 0) + { + acpi->rsdp = (struct acpi_rsdp_s *)now; + break; + } + + now += 16; + } + + return acpi->rsdp != NULL; +} +#endif + +/**************************************************************************** + * Name: acpi_rsdp_find + * + * Description: + * Find RSDP. + * + ****************************************************************************/ + +static bool acpi_rsdp_find(struct acpi_s *acpi) +{ + /* For now ony ACPI from BIOS region us supported */ + +#ifdef CONFIG_ARCH_X86_64_ACPI_BIOS + return acpi_rsdp_find_bios(acpi); +#else +# error For now ony ACPI from BIOS region is supported +#endif +} + +/**************************************************************************** + * Name: acpi_table64_find + ****************************************************************************/ + +static int acpi_table64_find(const char *sig, struct acpi_sdt_s **sdt) +{ + static struct acpi_s *acpi = &g_acpi; + struct acpi_sdt_s *tmp = NULL; + void *tps = NULL; + uint64_t *tp = NULL; + uint64_t *end = NULL; + + tps = &acpi->xsdt->table_ptrs; + tp = (uint64_t *)((uintptr_t)tps); + end = (uint64_t *)((uintptr_t)acpi->xsdt + acpi->xsdt->sdt.length); + + while (tp < end) + { + /* Compare signature */ + + tmp = (struct acpi_sdt_s *)(uintptr_t)*tp; + if (strncmp(tmp->signature, sig, 4) == 0) + { + *sdt = tmp; + return OK; + } + + /* Next table */ + + tp += 1; + } + + /* Not found */ + + return -ENOENT; +} + +/**************************************************************************** + * Name: acpi_table32_find + ****************************************************************************/ + +static int acpi_table32_find(const char *sig, struct acpi_sdt_s **sdt) +{ + struct acpi_s *acpi = &g_acpi; + struct acpi_sdt_s *tmp = NULL; + void *tps = NULL; + uint32_t *tp = NULL; + uint32_t *end = NULL; + + tps = &acpi->rsdt->table_ptrs; + tp = (uint32_t *)((uintptr_t)tps); + end = (uint32_t *)((uintptr_t)acpi->rsdt + acpi->rsdt->sdt.length); + + while (tp < end) + { + /* Compare signature */ + + tmp = (struct acpi_sdt_s *)(uintptr_t)*tp; + if (strncmp(tmp->signature, sig, 4) == 0) + { + *sdt = tmp; + return OK; + } + + /* Next table */ + + tp += 1; + } + + /* Not found */ + + return -ENOENT; +} + +/**************************************************************************** + * Name: acpi_table_find + * + * Description: + * Find and return table with a given signature + * + ****************************************************************************/ + +static int acpi_table_find(const char *sig, struct acpi_sdt_s **sdt) +{ + struct acpi_s *acpi = &g_acpi; + + /* 64 bit pointers or 32 bit pointers */ + + if (acpi->xsdt != 0) + { + return acpi_table64_find(sig, sdt); + } + else + { + return acpi_table32_find(sig, sdt); + } +} + +#ifdef CONFIG_ARCH_X86_64_ACPI_DUMP +/**************************************************************************** + * Name: acpi_sdt_dump + * + * Description: + * Dump SDT entry + * + ****************************************************************************/ + +static void acpi_sdt_dump(struct acpi_sdt_s *sdt) +{ + acpi_info("ptr = %p sig = %.4s", sdt, sdt->signature); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: acpi_init + * + * Description: + * Initialize ACPI parser. + * + ****************************************************************************/ + +int acpi_init(uintptr_t rsdp) +{ + struct acpi_s *acpi = &g_acpi; + int ret = OK; + + if (rsdp == 0) + { + /* Find RSP */ + + if (!acpi_rsdp_find(acpi)) + { + return -EINVAL; + } + } + else + { + acpi->rsdp = (struct acpi_rsdp_s *)rsdp; + } + + /* Make sure that RSDP is mapped */ + + acpi_map_region((uintptr_t)acpi->rsdp, sizeof(struct acpi_rsdp_s)); + + /* Parse RSDP */ + + ret = acpi_rsdp_parse(acpi->rsdp); + if (ret < 0) + { + return ret; + } + + /* Cache some useful tables */ + + /* Get MADT table */ + + acpi_table_find(ACPI_SIG_APIC, (struct acpi_sdt_s **)&acpi->madt); + + /* Get MCFG */ + + acpi_table_find(ACPI_SIG_MCFG, (struct acpi_sdt_s **)&acpi->mcfg); + + return OK; +} + +/**************************************************************************** + * Name: acpi_madt_get + * + * Description: + * Find the n'th occurence of a MADT entry with a given type. + * + ****************************************************************************/ + +int acpi_madt_get(int type, int n, struct acpi_entry_s **entry) +{ + struct acpi_s *acpi = &g_acpi; + struct acpi_entry_s *tmp = NULL; + uint8_t *ptr = NULL; + uint8_t *end = NULL; + + if (acpi->madt == NULL) + { + return -EINVAL; + } + + ptr = (uint8_t *)&g_acpi.madt->entries; + end = (uint8_t *)((uintptr_t)g_acpi.madt + g_acpi.madt->sdt.length); + + while (ptr < end) + { + tmp = (struct acpi_entry_s *)ptr; + + if (tmp->type == type) + { + if (n-- == 0) + { + *entry = tmp; + return OK; + } + } + + ptr += tmp->length; + } + + /* Not found */ + + return -ENOENT; +} + +/**************************************************************************** + * Name: acpi_lapi_get + * + * Description: + * Get Local APIC entry for a given CPU. + * + ****************************************************************************/ + +int acpi_lapic_get(int cpu, struct acpi_lapic_s **lapic) +{ + return acpi_madt_get(ACPI_MADT_TYPE_LOCAL_APIC, cpu, + (struct acpi_entry_s **)lapic); +} + +#ifdef CONFIG_ARCH_X86_64_ACPI_DUMP +/**************************************************************************** + * Name: acpi_dump + * + * Description: + * Dump ACPI tables. + * + ****************************************************************************/ + +void acpi_dump(void) +{ + struct acpi_entry_s *entry = NULL; + struct acpi_lapic_s *lapic = NULL; + uint8_t *ptr8 = NULL; + uint8_t *end8 = NULL; + struct acpi_entry_s *tmp = NULL; + void *tps = NULL; + uint64_t *tp64 = NULL; + uint64_t *end64 = NULL; + uint32_t *tp32 = NULL; + uint32_t *end32 = NULL; + int i = 0; + int ret = 0; + + /* Dump entires */ + + if (g_acpi.xsdt != 0) + { + tps = &g_acpi.rsdt->table_ptrs; + tp64 = (uint64_t *)tps; + end64 = (uint64_t *)((uintptr_t)g_acpi.xsdt + g_acpi.xsdt->sdt.length); + + acpi_info("XSDT = %p", g_acpi.xsdt); + acpi_info(" tp64 = %p", tp64); + acpi_info(" end64 = %p", end64); + + while (tp64 < end64) + { + acpi_sdt_dump((struct acpi_sdt_s *)(uintptr_t)*tp64); + + /* Next table */ + + tp64 += 1; + } + } + else + { + tps = &g_acpi.rsdt->table_ptrs; + tp32 = (uint32_t *)tps; + end32 = (uint32_t *)((uintptr_t)g_acpi.rsdt + g_acpi.rsdt->sdt.length); + + acpi_info("RSDT = %p", g_acpi.rsdt); + acpi_info(" tp32 = %p", tp32); + acpi_info(" end32 = %p", end32); + + while (tp32 < end32) + { + acpi_sdt_dump((struct acpi_sdt_s *)(uintptr_t)*tp32); + + /* Next table */ + + tp32 += 1; + } + } + + /* Dump MADT */ + + ptr8 = (uint8_t *)&g_acpi.madt->entries; + end8 = (uint8_t *)((uint64_t)g_acpi.madt + g_acpi.madt->sdt.length); + + while (ptr8 < end8) + { + tmp = (struct acpi_entry_s *)ptr8; + acpi_info("Found MADT type %d %p", tmp->type, tmp); + ptr8 += tmp->length; + } + + /* Print all CPU */ + + while (true) + { + ret = acpi_lapic_get(i, &lapic); + if (ret < 0) + { + break; + } + + acpi_info("Found LAPIC for CPU %d %p", i, lapic); + acpi_info(" ACPI ID %d", lapic->acpi_id); + acpi_info(" APIC ID %d", lapic->apic_id); + acpi_info(" flags %d", lapic->flags); + + /* IO_APIC */ + + ret = acpi_madt_get(ACPI_MADT_TYPE_IO_APIC, i, &entry); + if (ret == OK) + { + acpi_info("Found IOAPIC %p", entry); + } + + /* APIC64 */ + + ret = acpi_madt_get(ACPI_MADT_TYPE_LOCAL_APIC64, i, &entry); + if (ret == OK) + { + acpi_info("Found 64 bit APIC %p", entry); + } + + /* X2APIC */ + + ret = acpi_madt_get(ACPI_MADT_TYPE_LOCAL_X2APIC, i, &entry); + if (ret == OK) + { + acpi_info("Found X2APIC %p", entry); + } + + /* Try next core */ + + i += 1; + } +} +#endif diff --git a/arch/x86_64/src/common/x86_64_exit.c b/arch/x86_64/src/common/x86_64_exit.c index 916e30fd4be02..43f0dcc66d6bf 100644 --- a/arch/x86_64/src/common/x86_64_exit.c +++ b/arch/x86_64/src/common/x86_64_exit.c @@ -60,8 +60,6 @@ void up_exit(int status) enter_critical_section(); - sinfo("TCB=%p exiting\n", this_task()); - nxsched_dumponexit(); /* Destroy the task at the head of the ready to run list. */ diff --git a/arch/x86_64/src/common/x86_64_getintstack.c b/arch/x86_64/src/common/x86_64_getintstack.c index 85469a72c81d5..12e646893eae0 100644 --- a/arch/x86_64/src/common/x86_64_getintstack.c +++ b/arch/x86_64/src/common/x86_64_getintstack.c @@ -37,7 +37,7 @@ ****************************************************************************/ #if CONFIG_ARCH_INTERRUPTSTACK > 3 -uintptr_t up_get_intstackbase(void) +uintptr_t up_get_intstackbase(int cpu) { return (uintptr_t)g_intstackalloc; } diff --git a/arch/x86_64/src/common/x86_64_initialize.c b/arch/x86_64/src/common/x86_64_initialize.c index b9f32c2d2530d..381c2b0aa408f 100644 --- a/arch/x86_64/src/common/x86_64_initialize.c +++ b/arch/x86_64/src/common/x86_64_initialize.c @@ -26,38 +26,47 @@ #include #include +#ifdef CONFIG_DEV_SIMPLE_ADDRENV +# include +#endif + +#include + #include "x86_64_internal.h" +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_DEV_SIMPLE_ADDRENV +/* Map 1:1 with 0x100000000 offset */ + +struct simple_addrenv_s g_addrenv = +{ + .va = X86_64_LOAD_OFFSET, + .pa = 0, + .size = 0xffffffffffffffff +}; +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: up_calibratedelay + * Name: up_addrenv_init * * Description: - * Delay loops are provided for short timing loops. This function, if - * enabled, will just wait for 100 seconds. Using a stopwatch, you can - * can then determine if the timing loops are properly calibrated. + * Initialize addrenv. * ****************************************************************************/ -#if defined(CONFIG_ARCH_CALIBRATION) && defined(CONFIG_DEBUG_FEATURES) -static void up_calibratedelay(void) +static void x86_64_addrenv_init(void) { - int i; - - _warn("Beginning 100s delay\n"); - for (i = 0; i < 100; i++) - { - up_mdelay(1000); - } - - _warn("End 100s delay\n"); -} -#else -# define up_calibratedelay() +#ifdef CONFIG_DEV_SIMPLE_ADDRENV + simple_addrenv_initialize(&g_addrenv); #endif +} /**************************************************************************** * Public Functions @@ -86,6 +95,10 @@ void up_initialize(void) x86_64_addregion(); + /* Initialzie addrenv */ + + x86_64_addrenv_init(); + #ifdef CONFIG_PM /* Initialize the power management subsystem. This MCU-specific function * must be called *very* early in the initialization sequence *before* any @@ -117,10 +130,19 @@ void up_initialize(void) /* Initialize the network */ +#ifndef CONFIG_NETDEV_LATEINIT x86_64_netinitialize(); +#endif /* Initialize USB -- device and/or host */ x86_64_usbinitialize(); + +#ifdef CONFIG_ARCH_X86_64_ACPI_DUMP + /* Dump ACPI tables */ + + acpi_dump(); +#endif + board_autoled_on(LED_IRQSENABLED); } diff --git a/arch/x86_64/src/common/x86_64_internal.h b/arch/x86_64/src/common/x86_64_internal.h index da5a5a451e9b7..8ec08f845d13a 100644 --- a/arch/x86_64/src/common/x86_64_internal.h +++ b/arch/x86_64/src/common/x86_64_internal.h @@ -32,6 +32,7 @@ # include # include # include +# include #endif /**************************************************************************** @@ -63,7 +64,7 @@ # undef USE_SERIALDRIVER # undef USE_EARLYSERIALINIT # undef CONFIG_DEV_LOWCONSOLE -# else +# elif defined(CONFIG_16550_UART) # define USE_SERIALDRIVER 1 # define USE_EARLYSERIALINIT 1 # endif @@ -195,6 +196,11 @@ void x86_64_checktasks(void); void x86_64_syscall(uint64_t *regs); +#ifdef CONFIG_ARCH_MULTIBOOT2 +void x86_64_mb2_fbinitialize(struct multiboot_tag_framebuffer *tag); +void fb_putc(char ch); +#endif + /* Defined in up_allocateheap.c */ #if CONFIG_MM_REGIONS > 1 @@ -215,7 +221,7 @@ void x86_64_timer_initialize(void); /* Defined in board/x86_64_network.c */ -#ifdef CONFIG_NET +#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) void x86_64_netinitialize(void); #else # define x86_64_netinitialize() @@ -229,6 +235,12 @@ void x86_64_usbuninitialize(void); # define x86_64_usbuninitialize() #endif +/* Defined in x86_64_pci.c */ + +#ifdef CONFIG_PCI +void x86_64_pci_init(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __ARCH_X86_64_SRC_COMMON_UP_INTERNAL_H */ diff --git a/arch/x86_64/src/common/x86_64_pci.c b/arch/x86_64/src/common/x86_64_pci.c new file mode 100644 index 0000000000000..d603d8999b0cf --- /dev/null +++ b/arch/x86_64/src/common/x86_64_pci.c @@ -0,0 +1,225 @@ +/**************************************************************************** + * arch/x86_64/src/common/x86_64_pci.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "x86_64_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PCI_CFG_ADDR 0xcf8 +#define PCI_DATA_ADDR 0xcfc +#define PCI_CFG_EN (1 << 31) + +/**************************************************************************** + * Private Functions Definitions + ****************************************************************************/ + +static void x86_64_pci_cfg_write(struct pci_dev_s *dev, int reg, + uint32_t val, int width); +static uint32_t x86_64_pci_cfg_read(struct pci_dev_s *dev, int reg, + int width); +static int x86_64_pci_map_bar(uint64_t addr, uint64_t len); +static uint32_t x86_64_pci_io_read(const volatile void *addr, int width); +static void x86_64_pci_io_write(const volatile void *addr, uint32_t val, + int width); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct pci_bus_ops_s g_x86_64_pci_bus_ops = +{ + .pci_cfg_write = x86_64_pci_cfg_write, + .pci_cfg_read = x86_64_pci_cfg_read, + .pci_map_bar = x86_64_pci_map_bar, + .pci_io_read = x86_64_pci_io_read, + .pci_io_write = x86_64_pci_io_write, +}; + +static struct pci_bus_s g_x86_64_pci_bus = +{ + .ops = &g_x86_64_pci_bus_ops, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: x86_64_pci_cfg_write + * + * Description: + * Write 8, 16, 32, 64 bits data to PCI-E configuration space of device + * specified by dev + * + * Input Parameters: + * bdf - Device private data + * reg - A pointer to the read-only buffer of data to be written + * size - The number of bytes to send from the buffer + * + * Returned Value: + * 0: success, <0: A negated errno + * + ****************************************************************************/ + +static void x86_64_pci_cfg_write(struct pci_dev_s *dev, int reg, + uint32_t val, int width) +{ + uint8_t offset_mask = (4 - width); + + outl(PCI_CFG_EN | (dev->bdf << 8) | reg, PCI_CFG_ADDR); + switch (width) + { + case 1: + outb(val, PCI_DATA_ADDR + (reg & offset_mask)); + return; + case 2: + outw(val, PCI_DATA_ADDR + (reg & offset_mask)); + return; + case 4: + outl(val, PCI_DATA_ADDR); + return; + default: + pcierr("Invalid cfg write width %d\n", width); + } +} + +/**************************************************************************** + * Name: x86_64_pci_cfg_read + * + * Description: + * Read 8, 16, 32, 64 bits data from PCI-E configuration space of device + * specified by dev + * + * Input Parameters: + * dev - Device private data + * buffer - A pointer to a buffer to receive the data from the device + * size - The requested number of bytes to be read + * + * Returned Value: + * 0: success, <0: A negated errno + * + ****************************************************************************/ + +static uint32_t x86_64_pci_cfg_read(struct pci_dev_s *dev, int reg, + int width) +{ + uint32_t ret; + uint8_t offset_mask = 4 - width; + + outl(PCI_CFG_EN | (dev->bdf << 8) | reg, PCI_CFG_ADDR); + + switch (width) + { + case 1: + ret = inb(PCI_DATA_ADDR + (reg & offset_mask)); + return ret; + + case 2: + ret = inw(PCI_DATA_ADDR + (reg & offset_mask)); + return ret; + case 4: + ret = inl(PCI_DATA_ADDR); + return ret; + default: + pcierr("Invalid cfg read width %d\n", width); + } + + return 0; +} + +static uint32_t x86_64_pci_io_read(const volatile void *addr, int width) +{ + uint16_t portaddr = (uint16_t)(intptr_t)addr; + + switch (width) + { + case 1: + return (uint32_t)inb(portaddr); + case 2: + return (uint32_t)inw(portaddr); + case 4: + return (uint32_t)inl(portaddr); + default: + pcierr("Invalid read width %d\n", width); + DEBUGPANIC(); + } + + return 0; +} + +static void x86_64_pci_io_write(const volatile void *addr, uint32_t val, + int width) +{ + uint16_t portaddr = (uint16_t)(intptr_t)addr; + + switch (width) + { + case 1: + outb((uint8_t)val, portaddr); + return; + case 2: + outw((uint16_t)val, portaddr); + return; + case 4: + outl((uint32_t)val, portaddr); + return; + default: + pcierr("Invalid write width %d\n", width); + DEBUGPANIC(); + } +} + +static int x86_64_pci_map_bar(uint64_t addr, uint64_t len) +{ + up_map_region((void *)(uintptr_t)addr, len, + X86_PAGE_WR | X86_PAGE_PRESENT | X86_PAGE_NOCACHE | X86_PAGE_GLOBAL); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: x86_64_pci_init + * + * Description: + * Initialize the PCI-E bus + * + ****************************************************************************/ + +void x86_64_pci_init(void) +{ + pciinfo("Initializing PCI Bus\n"); + pci_initialize(&g_x86_64_pci_bus); +} diff --git a/arch/x86_64/src/intel64/CMakeLists.txt b/arch/x86_64/src/intel64/CMakeLists.txt new file mode 100644 index 0000000000000..4525a4d78533c --- /dev/null +++ b/arch/x86_64/src/intel64/CMakeLists.txt @@ -0,0 +1,78 @@ +# ############################################################################## +# arch/x86_64/src/intel64/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS + intel64_saveusercontext.S + intel64_fullcontextrestore.S + intel64_vectors.S + intel64_head.S + intel64_createstack.c + intel64_initialstate.c + intel64_irq.c + intel64_map_region.c + intel64_regdump.c + intel64_releasestack.c + intel64_rtc.c + intel64_restore_auxstate.c + intel64_savestate.c + intel64_stackframe.c + intel64_schedulesigaction.c + intel64_sigdeliver.c + intel64_usestack.c + intel64_systemreset.c + intel64_freq.c + intel64_cache.c + intel64_start.c + intel64_handlers.c + intel64_idle.c + intel64_lowsetup.c + intel64_serial.c + intel64_rng.c + intel64_check_capability.c) + +if(CONFIG_ARCH_HAVE_TESTSET) + list(APPEND SRCS intel64_testset.S) +endif() + +if(CONFIG_MULTBOOT2_FB_TERM) + list(APPEND SRCS intel64_mbfb.c) +endif() + +if(CONFIG_ARCH_INTEL64_HAVE_TSC) + if(CONFIG_SCHED_TICKLESS) + list(APPEND SRCS intel64_tsc_tickless.c) + else() + list(APPEND SRCS intel64_tsc_timerisr.c) + endif() +endif() + +if(CONFIG_INTEL64_HPET) + list(APPEND SRCS intel64_hpet.c) +endif() + +if(CONFIG_INTEL64_ONESHOT) + list(APPEND SRCS intel64_oneshot.c intel64_oneshot_lower.c) +endif() + +if(CONFIG_ARCH_FPU) + list(APPEND SRCS intel64_fpucmp.c) +endif() + +target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/x86_64/src/intel64/Kconfig b/arch/x86_64/src/intel64/Kconfig index 902e887341423..f0b5722ec3cba 100644 --- a/arch/x86_64/src/intel64/Kconfig +++ b/arch/x86_64/src/intel64/Kconfig @@ -6,13 +6,71 @@ if ARCH_INTEL64 comment "intel64 Configuration Options" -config ARCH_INTEL64_HAVE_TSC_DEADLINE +choice + prompt "Intel64 Chip Selection" + default ARCH_CHIP_INTEL64_QEMU + +config ARCH_CHIP_INTEL64_QEMU + bool "Intel64 QEMU" + +config ARCH_CHIP_INTEL64_CUSTOM + bool "Custom Intel64 chip" + +endchoice # "Intel64 Chip Selection" + +config ARCH_INTEL64_HAVE_TSC + bool + +config ARCH_INTEL64_CACHE_LINESIZE + int "Cache line size (hardcoded)" + depends on ARCH_DCACHE || ARCH_ICACHE + default 64 + ---help--- + Cache line size. If set to 0, we read the value from CPUID, + (Probably) all new Intel CPUs have this value equal to 64. + +config ARCH_INTEL64_DCACHE_SIZE + int "Data cache line size (L1d)" + depends on ARCH_DCACHE + default 0 + ---help--- + Data cache line size (L1d). If set to 0, we read the value from CPUID. + +config ARCH_INTEL64_ICACHE_SIZE + int "Instruction cache line size (L1i)" + depends on ARCH_ICACHE + default 0 + ---help--- + Instruction cache line size (L1i). If set to 0, we read the value from CPUID. + +config ARCH_INTEL64_HAVE_CLWB + bool "CLWB support" + default n + ---help--- + Select to enable the use of CLWB to write back cache line + +choice + prompt "System Timer Source" + default ARCH_INTEL64_TSC_DEADLINE + ---help--- + Choose which hardware resource will drive NuttX + system time + +config ARCH_INTEL64_TSC_DEADLINE bool "TSC DEADLINE timer support" - default y + select ARCH_INTEL64_HAVE_TSC ---help--- Select to enable the use of TSC DEADLINE timer of x86_64 -if ARCH_INTEL64_HAVE_TSC_DEADLINE +config ARCH_INTEL64_TSC + bool "TSC APIC timer support" + select ARCH_INTEL64_HAVE_TSC + ---help--- + Select to enable the use of TSC APIC timer of x86_64 + +endchoice # System Timer Source + +if ARCH_INTEL64_TSC_DEADLINE config ARCH_INTEL64_CORE_FREQ_KHZ int "CPU Core frequency in kHz" @@ -23,7 +81,7 @@ config ARCH_INTEL64_CORE_FREQ_KHZ endif -if !ARCH_INTEL64_HAVE_TSC_DEADLINE +if ARCH_INTEL64_TSC config ARCH_INTEL64_APIC_FREQ_KHZ int "APIC timer frequency in kHz" @@ -34,6 +92,63 @@ config ARCH_INTEL64_APIC_FREQ_KHZ endif +config INTEL64_HPET + bool "HPET timer support" + default n + ---help--- + Select to enable the HPET timer support + +if INTEL64_HPET + +config INTEL64_HPET_BASE + hex "HPET timer base address" + default 0xfed00000 + ---help--- + Configure base address for HPET. In the future, we can get this address from + the ACPI table if ACPI support is enabled. + +config INTEL64_HPET_CHANNELS + int "HPET timer supported channels" + default 2 + range 1 3 + ---help--- + Configure the number of supported HPET channles (called HPET timers + in HPET spec). We use HPET legacy replacement for interrupts which + means that Timer 0 and Timer 1 interrupts are hardcoded, but Timer 2 + needs additional attention to configure interrupt routing. + Timer 2 will most likely not work with QEMU. + +config INTEL64_HPET_MIN_DELAY + int "HPET minimum supported delay in micro-seconds" + default 1000 + ---help--- + HPET use free runnin up-counter and a comparators which generate events + only on a equal event. This can results in event miss if we set too small + delay. In that case we must set a minimum value for delay that always work. + For the QEMU target this value should be as high as 1000, but for real + hardware it may go much lower (for i7-1255U CPU it works with values <10). + +endif # INTEL64_HPET + +config INTEL64_ONESHOT + bool "Oneshot timer support" + select INTEL64_HPET + default n + ---help--- + Select to enable the oneshot timer support + +if INTEL64_ONESHOT + +config INTEL64_ONESHOT_MAXTIMERS + int "Maximum number of oneshot timers" + default 1 + range 1 3 + ---help--- + Determines the maximum number of oneshot timers that can be + supported. + +endif + config ARCH_INTEL64_HAVE_XSAVE bool "XSAVE support" default y diff --git a/arch/x86_64/src/intel64/Make.defs b/arch/x86_64/src/intel64/Make.defs index 010b56acd6e70..082812f1f6744 100644 --- a/arch/x86_64/src/intel64/Make.defs +++ b/arch/x86_64/src/intel64/Make.defs @@ -18,31 +18,47 @@ # ############################################################################ -# Common x86_64 and intel64 files +include common/Make.defs -CMN_CSRCS += x86_64_allocateheap.c x86_64_copystate.c x86_64_exit.c -CMN_CSRCS += x86_64_getintstack.c x86_64_mdelay.c x86_64_initialize.c -CMN_CSRCS += x86_64_modifyreg8.c x86_64_modifyreg16.c x86_64_modifyreg32.c -CMN_CSRCS += x86_64_nputs.c x86_64_switchcontext.c x86_64_udelay.c CMN_CSRCS += intel64_createstack.c intel64_initialstate.c intel64_irq.c CMN_CSRCS += intel64_map_region.c intel64_regdump.c intel64_releasestack.c CMN_CSRCS += intel64_rtc.c intel64_restore_auxstate.c intel64_savestate.c CMN_CSRCS += intel64_stackframe.c intel64_schedulesigaction.c CMN_CSRCS += intel64_sigdeliver.c intel64_usestack.c x86_64_tcbinfo.c +CMN_CSRCS += intel64_systemreset.c intel64_freq.c intel64_cache.c # Required Intel64 files CHIP_ASRCS = intel64_saveusercontext.S intel64_fullcontextrestore.S intel64_vectors.S intel64_head.S -CHIP_CSRCS = intel64_handlers.c intel64_idle.c intel64_lowsetup.c +CHIP_CSRCS = intel64_start.c intel64_handlers.c intel64_idle.c intel64_lowsetup.c CHIP_CSRCS += intel64_serial.c intel64_rng.c intel64_check_capability.c +ifeq ($(CONFIG_ARCH_HAVE_TESTSET), y) +CHIP_ASRCS += intel64_testset.S +endif + # Configuration-dependent intel64 files -ifneq ($(CONFIG_SCHED_TICKLESS),y) -CHIP_CSRCS += intel64_timerisr.c +ifeq ($(CONFIG_MULTBOOT2_FB_TERM),y) +CHIP_CSRCS += intel64_mbfb.c endif +ifeq ($(CONFIG_ARCH_INTEL64_HAVE_TSC),y) ifeq ($(CONFIG_SCHED_TICKLESS),y) -CHIP_CSRCS += intel64_tickless.c +CHIP_CSRCS += intel64_tsc_tickless.c +else +CHIP_CSRCS += intel64_tsc_timerisr.c +endif +endif + +ifeq ($(CONFIG_INTEL64_HPET),y) +CHIP_CSRCS += intel64_hpet.c +endif + +ifeq ($(CONFIG_INTEL64_ONESHOT),y) +CHIP_CSRCS += intel64_oneshot.c intel64_oneshot_lower.c endif +ifeq ($(CONFIG_ARCH_FPU),y) +CHIP_CSRCS += intel64_fpucmp.c +endif \ No newline at end of file diff --git a/arch/x86_64/src/intel64/Toolchain.defs b/arch/x86_64/src/intel64/Toolchain.defs new file mode 100644 index 0000000000000..6d0392aaa3e4e --- /dev/null +++ b/arch/x86_64/src/intel64/Toolchain.defs @@ -0,0 +1,21 @@ +############################################################################ +# arch/x86_64/src/intel64/Toolchain.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/arch/x86_64/src/common/Toolchain.defs diff --git a/arch/x86_64/src/intel64/intel64.h b/arch/x86_64/src/intel64/intel64.h index b8d644038e935..40220d4c78d17 100644 --- a/arch/x86_64/src/intel64/intel64.h +++ b/arch/x86_64/src/intel64/intel64.h @@ -68,19 +68,6 @@ extern "C" * Public Function Prototypes ****************************************************************************/ -/**************************************************************************** - * Name: intel64_lowsetup - * - * Description: - * Called at the very beginning of _start. - * Performs low level initializationincluding setup of the console UART. - * This UART done early so that the serial console is available for - * debugging very early in the boot sequence. - * - ****************************************************************************/ - -void intel64_lowsetup(void); - /**************************************************************************** * Name: vector_* * @@ -140,6 +127,246 @@ void vector_irq12(void); void vector_irq13(void); void vector_irq14(void); void vector_irq15(void); +void vector_irq16(void); +void vector_irq17(void); +void vector_irq18(void); +void vector_irq19(void); +void vector_irq20(void); +void vector_irq21(void); +void vector_irq22(void); +void vector_irq23(void); +void vector_irq24(void); +void vector_irq25(void); +void vector_irq26(void); +void vector_irq27(void); +void vector_irq28(void); +void vector_irq29(void); +void vector_irq30(void); +void vector_irq31(void); +void vector_irq32(void); +void vector_irq33(void); +void vector_irq34(void); +void vector_irq35(void); +void vector_irq36(void); +void vector_irq37(void); +void vector_irq38(void); +void vector_irq39(void); +void vector_irq40(void); +void vector_irq41(void); +void vector_irq42(void); +void vector_irq43(void); +void vector_irq44(void); +void vector_irq45(void); +void vector_irq46(void); +void vector_irq47(void); +void vector_irq48(void); +void vector_irq49(void); +void vector_irq50(void); +void vector_irq51(void); +void vector_irq52(void); +void vector_irq53(void); +void vector_irq54(void); +void vector_irq55(void); +void vector_irq56(void); +void vector_irq57(void); +void vector_irq58(void); +void vector_irq59(void); +void vector_irq60(void); +void vector_irq61(void); +void vector_irq62(void); +void vector_irq63(void); +void vector_irq64(void); +void vector_irq65(void); +void vector_irq66(void); +void vector_irq67(void); +void vector_irq68(void); +void vector_irq69(void); +void vector_irq70(void); +void vector_irq71(void); +void vector_irq72(void); +void vector_irq73(void); +void vector_irq74(void); +void vector_irq75(void); +void vector_irq76(void); +void vector_irq77(void); +void vector_irq78(void); +void vector_irq79(void); +void vector_irq80(void); +void vector_irq81(void); +void vector_irq82(void); +void vector_irq83(void); +void vector_irq84(void); +void vector_irq85(void); +void vector_irq86(void); +void vector_irq87(void); +void vector_irq88(void); +void vector_irq89(void); +void vector_irq90(void); +void vector_irq91(void); +void vector_irq92(void); +void vector_irq93(void); +void vector_irq94(void); +void vector_irq95(void); +void vector_irq96(void); +void vector_irq97(void); +void vector_irq98(void); +void vector_irq99(void); +void vector_irq100(void); +void vector_irq101(void); +void vector_irq102(void); +void vector_irq103(void); +void vector_irq104(void); +void vector_irq105(void); +void vector_irq106(void); +void vector_irq107(void); +void vector_irq108(void); +void vector_irq109(void); +void vector_irq110(void); +void vector_irq111(void); +void vector_irq112(void); +void vector_irq113(void); +void vector_irq114(void); +void vector_irq115(void); +void vector_irq116(void); +void vector_irq117(void); +void vector_irq118(void); +void vector_irq119(void); +void vector_irq120(void); +void vector_irq121(void); +void vector_irq122(void); +void vector_irq123(void); +void vector_irq124(void); +void vector_irq125(void); +void vector_irq126(void); +void vector_irq127(void); +void vector_irq128(void); +void vector_irq129(void); +void vector_irq130(void); +void vector_irq131(void); +void vector_irq132(void); +void vector_irq133(void); +void vector_irq134(void); +void vector_irq135(void); +void vector_irq136(void); +void vector_irq137(void); +void vector_irq138(void); +void vector_irq139(void); +void vector_irq140(void); +void vector_irq141(void); +void vector_irq142(void); +void vector_irq143(void); +void vector_irq144(void); +void vector_irq145(void); +void vector_irq146(void); +void vector_irq147(void); +void vector_irq148(void); +void vector_irq149(void); +void vector_irq150(void); +void vector_irq151(void); +void vector_irq152(void); +void vector_irq153(void); +void vector_irq154(void); +void vector_irq155(void); +void vector_irq156(void); +void vector_irq157(void); +void vector_irq158(void); +void vector_irq159(void); +void vector_irq160(void); +void vector_irq161(void); +void vector_irq162(void); +void vector_irq163(void); +void vector_irq164(void); +void vector_irq165(void); +void vector_irq166(void); +void vector_irq167(void); +void vector_irq168(void); +void vector_irq169(void); +void vector_irq170(void); +void vector_irq171(void); +void vector_irq172(void); +void vector_irq173(void); +void vector_irq174(void); +void vector_irq175(void); +void vector_irq176(void); +void vector_irq177(void); +void vector_irq178(void); +void vector_irq179(void); +void vector_irq180(void); +void vector_irq181(void); +void vector_irq182(void); +void vector_irq183(void); +void vector_irq184(void); +void vector_irq185(void); +void vector_irq186(void); +void vector_irq187(void); +void vector_irq188(void); +void vector_irq189(void); +void vector_irq190(void); +void vector_irq191(void); +void vector_irq192(void); +void vector_irq193(void); +void vector_irq194(void); +void vector_irq195(void); +void vector_irq196(void); +void vector_irq197(void); +void vector_irq198(void); +void vector_irq199(void); +void vector_irq200(void); +void vector_irq201(void); +void vector_irq202(void); +void vector_irq203(void); +void vector_irq204(void); +void vector_irq205(void); +void vector_irq206(void); +void vector_irq207(void); +void vector_irq208(void); +void vector_irq209(void); +void vector_irq210(void); +void vector_irq211(void); +void vector_irq212(void); +void vector_irq213(void); +void vector_irq214(void); +void vector_irq215(void); +void vector_irq216(void); +void vector_irq217(void); +void vector_irq218(void); +void vector_irq219(void); +void vector_irq220(void); +void vector_irq221(void); +void vector_irq222(void); +void vector_irq223(void); +void vector_irq224(void); +void vector_irq225(void); +void vector_irq226(void); +void vector_irq227(void); +void vector_irq228(void); +void vector_irq229(void); +void vector_irq230(void); +void vector_irq231(void); +void vector_irq232(void); +void vector_irq233(void); +void vector_irq234(void); +void vector_irq235(void); +void vector_irq236(void); +void vector_irq237(void); +void vector_irq238(void); +void vector_irq239(void); +void vector_irq240(void); +void vector_irq241(void); +void vector_irq242(void); +void vector_irq243(void); +void vector_irq244(void); +void vector_irq245(void); +void vector_irq246(void); +void vector_irq247(void); +void vector_irq248(void); +void vector_irq249(void); +void vector_irq250(void); +void vector_irq251(void); +void vector_irq252(void); +void vector_irq253(void); +void vector_irq254(void); +void vector_irq255(void); #undef EXTERN #if defined(__cplusplus) diff --git a/arch/x86_64/src/intel64/intel64_cache.c b/arch/x86_64/src/intel64/intel64_cache.c new file mode 100644 index 0000000000000..924afcd4aa05e --- /dev/null +++ b/arch/x86_64/src/intel64/intel64_cache.c @@ -0,0 +1,591 @@ +/**************************************************************************** + * arch/x86_64/src/intel64/intel64_cache.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "x86_64_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: x86_64_wbindv + ****************************************************************************/ + +static inline void x86_64_wbindv(void) +{ + asm volatile("wbinvd" : : : "memory"); +} + +/**************************************************************************** + * Name: x86_64_wbnoinvd + ****************************************************************************/ + +static inline void x86_64_wbnoinvd(void) +{ + asm volatile("wbnoinvd" : : : "memory"); +} + +/**************************************************************************** + * Name: x86_64_invd + ****************************************************************************/ + +static inline void x86_64_invd(void) +{ + asm volatile("invd" : : : "memory"); +} + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: x86_64_cache_linesize + ****************************************************************************/ + +static size_t x86_64_cache_linesize(void) +{ +#if CONFIG_ARCH_INTEL64_CACHE_LINESIZE == 0 + unsigned long eax = 0; + unsigned long ebx = 0; + + eax = 1; + asm volatile("cpuid\n\t" + : "=b" (ebx) + : "a" (eax)); + + return ((ebx >> 8) & 0xff) * 8; +#else + return CONFIG_ARCH_INTEL64_CACHE_LINESIZE; +#endif +} + +/**************************************************************************** + * Name: x86_64_cache_size + ****************************************************************************/ + +static size_t x86_64_cache_size(int leaf) +{ + unsigned long eax; + unsigned long ebx; + unsigned long ecx; + unsigned long edx; + + /* The leaf 0 is Data cache */ + + eax = 4; + ecx = leaf; + asm volatile("cpuid" + : "=a"(eax), "=b"(ebx), "=c"(ecx), "=d"(edx) + : "a"(eax), "c"(ecx)); + + /* (Ways + 1) * (Partitions + 1) * (Line_Size + 1) * (Sets + 1) */ + + return ((((ebx >> 22) & 0x3ff) + 1) * + (((ebx >> 12) & 0x3ff) + 1) * + ((ebx & 0x7ff) + 1) * + (ecx + 1)); +} + +/**************************************************************************** + * Name: x86_64_cache_enable + ****************************************************************************/ + +static void x86_64_cache_enable(void) +{ + /* Clear "Not-write through" (NW) and "Cache disable" (CD) bits */ + + asm volatile("\t mov %%cr0, %%rax\n" + "\t mov $0x9fffffff, %%rbx\n" + "\t and %%rbx, %%rax\n" + "\t mov %%rax, %%cr0\n" + ::: "memory", "rax", "rbx"); +} + +/**************************************************************************** + * Name: x86_64_cache_disable + ****************************************************************************/ + +static void x86_64_cache_disable(void) +{ + /* Set "Not-write through" (NW) and "Cache disable" (CD) bits */ + + asm volatile("\t mov %%cr0, %%rax\n" + "\t mov $0x9fffffff, %%rbx \n" + "\t and %%rbx, %%rax \n" + "\t mov $0x60000000, %%rbx\n" + "\t or %%rbx, %%rax\n" + "\t mov %%rax, %%cr0\n" + :::"memory", "rax", "rbx"); + + /* And flush all caches */ + + up_flush_dcache_all(); + + /* Disable MTRR */ + + write_msr(MSR_MTRR_DEF_TYPE, 0); + + /* And flush once again */ + + up_flush_dcache_all(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_get_icache_linesize + * + * Description: + * Get icache linesize + * + * Input Parameters: + * None + * + * Returned Value: + * Cache line size + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_ICACHE +size_t up_get_icache_linesize(void) +{ + return x86_64_cache_linesize(); +} + +/**************************************************************************** + * Name: up_get_icache_size + * + * Description: + * Get icache size + * + * Input Parameters: + * None + * + * Returned Value: + * Cache size + * + ****************************************************************************/ + +size_t up_get_icache_size(void) +{ +#if CONFIG_ARCH_INTEL64_ICACHE_SIZE == 0 + return x86_64_cache_size(1); +#else + return CONFIG_ARCH_INTEL64_ICACHE_SIZE; +#endif +} +#endif + +/**************************************************************************** + * Name: up_enable_icache + * + * Description: + * Enable the I-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_ICACHE +void up_enable_icache(void) +{ + x86_64_cache_enable(); +} +#endif + +/**************************************************************************** + * Name: up_disable_icache + * + * Description: + * Disable the I-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_ICACHE +void up_disable_icache(void) +{ + x86_64_cache_disable(); +} +#endif + +/**************************************************************************** + * Name: up_invalidate_icache + * + * Description: + * Invalidate the instruction cache within the specified region. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_ICACHE +void up_invalidate_icache(uintptr_t start, uintptr_t end) +{ + /* NOTE: x86 doesn't have separate instructions for I-cache */ + + up_invalidate_dcache(start, end); +} +#endif /* CONFIG_ARCH_ICACHE */ + +/**************************************************************************** + * Name: up_invalidate_icache_all + * + * Description: + * Invalidate the entire contents of I cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_ICACHE +void up_invalidate_icache_all(void) +{ + /* NOTE: x86 doesn't have separate instructions for I-cache */ + + up_invalidate_dcache_all(); +} +#endif + +/**************************************************************************** + * Name: up_get_dcache_linesize + * + * Description: + * Get dcache linesize + * + * Input Parameters: + * None + * + * Returned Value: + * Cache line size + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_DCACHE +size_t up_get_dcache_linesize(void) +{ + return x86_64_cache_linesize(); +} + +/**************************************************************************** + * Name: up_get_dcache_size + * + * Description: + * Get icache size + * + * Input Parameters: + * None + * + * Returned Value: + * Cache size + * + ****************************************************************************/ + +size_t up_get_dcache_size(void) +{ +#if CONFIG_ARCH_INTEL64_DCACHE_SIZE == 0 + return x86_64_cache_size(0); +#else + return CONFIG_ARCH_INTEL64_DCACHE_SIZE; +#endif +} +#endif + +/**************************************************************************** + * Name: up_enable_dcache + * + * Description: + * Enable the D-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_DCACHE +void up_enable_dcache(void) +{ + x86_64_cache_enable(); +} +#endif /* CONFIG_ARCH_DCACHE */ + +/**************************************************************************** + * Name: up_disable_dcache + * + * Description: + * Disable the D-Cache + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_DCACHE +void up_disable_dcache(void) +{ + x86_64_cache_disable(); +} +#endif /* CONFIG_ARCH_DCACHE */ + +/**************************************************************************** + * Name: up_invalidae_dcache + * + * Description: + * Invalidate the data cache within the specified region; we will be + * performing a DMA operation in this region and we want to purge old data + * in the cache. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_DCACHE +void up_invalidate_dcache(uintptr_t start, uintptr_t end) +{ + up_flush_dcache(start, end); +} +#endif /* CONFIG_ARCH_DCACHE */ + +/**************************************************************************** + * Name: up_invalidate_dcache_all + * + * Description: + * Invalidate the entire contents of D cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_DCACHE +void up_invalidate_dcache_all(void) +{ + x86_64_invd(); +} +#endif /* CONFIG_ARCH_DCACHE */ + +/**************************************************************************** + * Name: up_clean_dcache + * + * Description: + * Clean the data cache within the specified region by flushing the + * contents of the data cache to memory. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_DCACHE +void up_clean_dcache(uintptr_t start, uintptr_t end) +{ +#ifdef CONFIG_ARCH_INTEL64_HAVE_CLWB + size_t lsize = up_get_dcache_linesize(); + + start &= ~(lsize - 1); + + asm volatile("mfence" : : : "memory"); + + do + { + asm volatile("\tclwb %0;\n" : "+m" (start)); + + /* Increment the address by the size of one cache line. */ + + start += lsize; + } + while (start < end); + + asm volatile("mfence" : : : "memory"); +#else + x86_64_wbnoinvd(); +#endif +} +#endif /* CONFIG_ARCH_DCACHE */ + +/**************************************************************************** + * Name: up_clean_dcache_all + * + * Description: + * Clean the entire data cache within the specified region by flushing the + * contents of the data cache to memory. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_DCACHE +void up_clean_dcache_all(void) +{ + x86_64_wbnoinvd(); +} +#endif /* CONFIG_ARCH_DCACHE */ + +/**************************************************************************** + * Name: up_flush_dcache + * + * Description: + * Flush the data cache within the specified region by cleaning and + * invalidating the D cache. + * + * Input Parameters: + * start - virtual start address of region + * end - virtual end address of region + 1 + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_DCACHE +void up_flush_dcache(uintptr_t start, uintptr_t end) +{ + size_t lsize = up_get_dcache_linesize(); + + start &= ~(lsize - 1); + + asm volatile("mfence" : : : "memory"); + + do + { + asm volatile("\tclflush %0;\n" : "+m" (start)); + + /* Increment the address by the size of one cache line. */ + + start += lsize; + } + while (start < end); + + asm volatile("mfence" : : : "memory"); +} +#endif /* CONFIG_ARCH_DCACHE */ + +/**************************************************************************** + * Name: up_flush_dcache_all + * + * Description: + * Flush the entire data cache by cleaning and invalidating the D cache. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_DCACHE +void up_flush_dcache_all(void) +{ + x86_64_wbindv(); +} +#endif /* CONFIG_ARCH_DCACHE */ + +/**************************************************************************** + * Name: up_coherent_dcache + * + * Description: + * Ensure that the I and D caches are coherent within specified region + * by cleaning the D cache (i.e., flushing the D cache contents to memory + * and invalidating the I cache. This is typically used when code has been + * written to a memory region, and will be executed. + * + * Input Parameters: + * addr - virtual start address of region + * len - Size of the address region in bytes + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_ARCH_ICACHE) && defined(CONFIG_ARCH_DCACHE) +void up_coherent_dcache(uintptr_t addr, size_t len) +{ + uintptr_t end; + + if (len > 0) + { + /* Flush any dirtcy D-Cache lines to memory */ + + end = addr + len; + up_clean_dcache(addr, end); + + /* Invalidate I-Cache lines */ + + up_invalidate_icache(addr, end); + } +} +#endif diff --git a/arch/x86_64/src/intel64/intel64_check_capability.c b/arch/x86_64/src/intel64/intel64_check_capability.c index 533a77566a26a..e777b8554b27d 100644 --- a/arch/x86_64/src/intel64/intel64_check_capability.c +++ b/arch/x86_64/src/intel64/intel64_check_capability.c @@ -56,6 +56,7 @@ void x86_64_check_and_enable_capability(void) { + unsigned long ebx; unsigned long ecx; unsigned long require; @@ -63,7 +64,7 @@ void x86_64_check_and_enable_capability(void) /* Check timer availability */ -#ifdef CONFIG_ARCH_INTEL64_HAVE_TSC_DEADLINE +#ifdef CONFIG_ARCH_INTEL64_TSC_DEADLINE require |= X86_64_CPUID_01_TSCDEA; #endif @@ -80,15 +81,33 @@ void x86_64_check_and_enable_capability(void) #endif asm volatile("cpuid" : "=c" (ecx) : "a" (X86_64_CPUID_CAP) - : "rbx", "rdx", "memory"); + : "rdx", "memory"); - /* Check x2APIC availability */ + /* Check features availability from ECX */ if ((ecx & require) != require) { goto err; } + /* Extended features */ + + require = 0; + +#ifdef CONFIG_ARCH_INTEL64_HAVE_CLWB + require |= X86_64_CPUID_07_CLWB; +#endif + + asm volatile("cpuid" : "=b" (ebx) : "a" (X86_64_CPUID_EXTCAP), "c" (0) + : "rdx", "memory"); + + /* Check features availability */ + + if ((ebx & require) != require) + { + goto err; + } + #ifdef CONFIG_ARCH_INTEL64_HAVE_XSAVE __enable_sse_avx(); #endif @@ -97,6 +116,11 @@ void x86_64_check_and_enable_capability(void) __enable_pcid(); #endif + /* Enable I- and D-Caches */ + + up_enable_icache(); + up_enable_dcache(); + return; err: diff --git a/arch/x86_64/src/intel64/intel64_createstack.c b/arch/x86_64/src/intel64/intel64_createstack.c index 6649cb06c8209..f1c05da1fd162 100644 --- a/arch/x86_64/src/intel64/intel64_createstack.c +++ b/arch/x86_64/src/intel64/intel64_createstack.c @@ -161,7 +161,7 @@ int up_create_stack(struct tcb_s *tcb, size_t stack_size, uint8_t ttype) if (!tcb->stack_alloc_ptr) { - serr("ERROR: Failed to allocate stack, size %d\n", stack_size); + serr("ERROR: Failed to allocate stack, size %zu\n", stack_size); } #endif } @@ -192,8 +192,9 @@ int up_create_stack(struct tcb_s *tcb, size_t stack_size, uint8_t ttype) /* The intel64 stack must be aligned at word (16 byte) boundaries. If * necessary top_of_stack must be rounded down to the next boundary. - * We intentionally align at 8 byte boundary, because at task_start, - * only frame pointer will be pushed, not instruction pointer. + * We intentionally align at 8 byte boundary (look at up_stack_frame()) + * , because at task_start, only frame pointer will be pushed, not + * instruction pointer. */ top_of_stack &= ~0x0f; diff --git a/arch/x86_64/src/intel64/intel64_fpucmp.c b/arch/x86_64/src/intel64/intel64_fpucmp.c new file mode 100644 index 0000000000000..3159284dacc4e --- /dev/null +++ b/arch/x86_64/src/intel64/intel64_fpucmp.c @@ -0,0 +1,76 @@ +/**************************************************************************** + * arch/x86_64/src/intel64/intel64_fpucmp.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "x86_64_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_ARCH_FPU + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_fpucmp + * + * Description: + * Compare FPU areas from thread context. + * + * Input Parameters: + * saveregs1 - Pointer to the saved FPU registers. + * saveregs2 - Pointer to the saved FPU registers. + * + * Returned Value: + * True if FPU areas compare equal, False otherwise. + * + ****************************************************************************/ + +bool up_fpucmp(const void *saveregs1, const void *saveregs2) +{ + const uint32_t *regs1 = saveregs1; + const uint32_t *regs2 = saveregs2; + + /* IMPORTANT: + * + * With aggresive optimization enabled (-O2/-O3), ostest FPU test will + * fail. This is because the compiler will generate additional vector + * instructions between subsequent up_fpucmp() calls (loop vectorization + * somewhere in usleep() call), which will consequently overwrite + * the expected FPU context (XMM registers). + */ + + /* XMM area starts from offset 0 */ + + return memcmp(®s1[0], ®s2[0], XCPTCONTEXT_XMM_AREA_SIZE) == 0; +} +#endif /* CONFIG_ARCH_FPU */ diff --git a/arch/x86_64/src/intel64/intel64_freq.c b/arch/x86_64/src/intel64/intel64_freq.c new file mode 100644 index 0000000000000..421daaa6ea836 --- /dev/null +++ b/arch/x86_64/src/intel64/intel64_freq.c @@ -0,0 +1,97 @@ +/**************************************************************************** + * arch/x86_64/src/intel64/intel64_freq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include +#include + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +extern unsigned long g_x86_64_timer_freq; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: x86_64_timer_initialize + * + * Description: + * Initializes all platform-specific timer facilities. This function is + * called early in the initialization sequence by up_initialize(). + * On return, the current up-time should be available from + * up_timer_gettime() and the interval timer is ready for use (but not + * actively timing. + * + * Provided by platform-specific code and called from the architecture- + * specific logic. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Assumptions: + * Called early in the initialization sequence before any special + * concurrency protections are required. + * + ****************************************************************************/ + +void x86_64_timer_calibrate_freq(void) +{ +#ifdef CONFIG_ARCH_INTEL64_TSC_DEADLINE + + unsigned long crystal_freq; + unsigned long numerator; + unsigned long denominator; + + asm volatile("cpuid" + : "=c" (crystal_freq), "=b" (numerator), "=a" (denominator) + : "a" (X86_64_CPUID_TSC) + : "rdx", "memory"); + + if (numerator == 0 || denominator == 0 || crystal_freq == 0) + { + g_x86_64_timer_freq = CONFIG_ARCH_INTEL64_CORE_FREQ_KHZ * 1000L; + } + else + { + g_x86_64_timer_freq = crystal_freq / denominator * numerator; + } + +#elif defined(CONFIG_ARCH_INTEL64_TSC) + g_x86_64_timer_freq = CONFIG_ARCH_INTEL64_APIC_FREQ_KHZ * 1000L; +#endif +} diff --git a/arch/x86_64/src/intel64/intel64_fullcontextrestore.S b/arch/x86_64/src/intel64/intel64_fullcontextrestore.S index 03c73797f77bd..545bb3bdd00af 100644 --- a/arch/x86_64/src/intel64/intel64_fullcontextrestore.S +++ b/arch/x86_64/src/intel64/intel64_fullcontextrestore.S @@ -26,45 +26,13 @@ #include #include "x86_64_internal.h" - .file "intel64_fullcontextrestore.S" - -/************************************************************************** - * Pre-processor Definitions - **************************************************************************/ - -/************************************************************************** - * Public Data - **************************************************************************/ - -/**************************************************************************** - * Macros - ****************************************************************************/ - -/* Trace macros, use like trace 'i' to print char to serial port. */ - - .macro chout, addr, ch -#ifdef CONFIG_DEBUG_FEATURES - mov $\addr, %dx - mov $\ch, %al - out %al, %dx -#endif - .endm - - .macro trace, ch -#ifdef CONFIG_DEBUG_FEATURES - push %eax - push %edx - chout 0x3f8, \ch - pop %edx - pop %eax -#endif - .endm + .file "intel64_fullcontextrestore.S" /************************************************************************** * Public Functions **************************************************************************/ - .text + .text /************************************************************************** * Name: x86_64_fullcontextrestore @@ -74,84 +42,85 @@ * **************************************************************************/ - .globl x86_64_fullcontextrestore - .type x86_64_fullcontextrestore, @function + .globl x86_64_fullcontextrestore + .type x86_64_fullcontextrestore, @function x86_64_fullcontextrestore: - /* The pointer to the register save array in RDI. */ - - /* Disable interrupts now (the correct RFLAGS will be restored before we - * return - */ - - cli - - /* Create an interrupt stack frame for the final iret. - * - * - * IRET STACK - * --------------- - * RSP Before -> - * SS - * RSP - * RFLAGS - * CS - * RSP After -> RIP - * - */ - - movq (8*REG_SS)(%rdi), %rbx - push %rbx - movq (8*REG_RSP)(%rdi), %rbx - push %rbx - - movq (8*REG_RFLAGS)(%rdi), %rbx - push %rbx - movq (8*REG_CS)(%rdi), %rbx - push %rbx - movq (8*REG_RIP)(%rdi), %rbx - push %rbx - - /* Save the value of RDI on the stack too */ - - movq (8*REG_RDI)(%rdi), %rbx - push %rbx - - /* Now restore the remaining registers */ - movq (8*REG_RSI)(%rdi), %rsi - movq (8*REG_RDX)(%rdi), %rdx - movq (8*REG_RCX)(%rdi), %rcx - movq (8*REG_R8 )(%rdi), %r8 - movq (8*REG_R9 )(%rdi), %r9 - - movq (8*REG_R15)(%rdi), %r15 - movq (8*REG_R14)(%rdi), %r14 - movq (8*REG_R13)(%rdi), %r13 - movq (8*REG_R12)(%rdi), %r12 - movq (8*REG_R11)(%rdi), %r11 - movq (8*REG_R10)(%rdi), %r10 - movq (8*REG_RBP)(%rdi), %rbp - movq (8*REG_RBX)(%rdi), %rbx - movq (8*REG_RAX)(%rdi), %rax - - /* Restore the data segment register. I think there is an issue that will - * need to be address here at some time: If the register save area is in - * one data segment and the stack is in another, then the above would not - * work (and, conversely, if they are in the same data segment, the - * following is unnecessary and redundant). - */ - - mov (8*REG_DS)(%rdi), %ds - // mov (8*REG_ES)(%rdi), %es // Not used in 64 bit - // mov (8*REG_GS)(%rdi), %gs // Disabled, otherwise we will destroy MSR_GS_BASE - // mov (8*REG_FS)(%rdi), %fs // Disabled, otherwise we will destroy MSR_FS_BASE - // XXX: Should use wrgsbase and wrfsbase to restore the gs and fs register - - /* restore xmm registers */ - fxrstorq (%rdi) - - /* Restore the correct value of EAX and then return */ - - popq %rdi - iretq - .size x86_64_fullcontextrestore, . - x86_64_fullcontextrestore - .end + /* The pointer to the register save array in RDI. */ + + /* Disable interrupts now (the correct RFLAGS will be restored before we + * return + */ + + cli + + /* Create an interrupt stack frame for the final iret. + * + * + * IRET STACK + * --------------- + * RSP Before -> + * SS + * RSP + * RFLAGS + * CS + * RSP After -> RIP + * + */ + + movq (8*REG_SS)(%rdi), %rbx + push %rbx + movq (8*REG_RSP)(%rdi), %rbx + push %rbx + + movq (8*REG_RFLAGS)(%rdi), %rbx + push %rbx + movq (8*REG_CS)(%rdi), %rbx + push %rbx + movq (8*REG_RIP)(%rdi), %rbx + push %rbx + + /* Save the value of RDI on the stack too */ + + movq (8*REG_RDI)(%rdi), %rbx + push %rbx + + /* Now restore the remaining registers */ + movq (8*REG_RSI)(%rdi), %rsi + movq (8*REG_RDX)(%rdi), %rdx + movq (8*REG_RCX)(%rdi), %rcx + movq (8*REG_R8 )(%rdi), %r8 + movq (8*REG_R9 )(%rdi), %r9 + + movq (8*REG_R15)(%rdi), %r15 + movq (8*REG_R14)(%rdi), %r14 + movq (8*REG_R13)(%rdi), %r13 + movq (8*REG_R12)(%rdi), %r12 + movq (8*REG_R11)(%rdi), %r11 + movq (8*REG_R10)(%rdi), %r10 + movq (8*REG_RBP)(%rdi), %rbp + movq (8*REG_RBX)(%rdi), %rbx + movq (8*REG_RAX)(%rdi), %rax + + /* Restore the data segment register. I think there is an issue that will + * need to be address here at some time: If the register save area is in + * one data segment and the stack is in another, then the above would not + * work (and, conversely, if they are in the same data segment, the + * following is unnecessary and redundant). + */ + + mov (8*REG_DS)(%rdi), %ds + /* mov (8*REG_ES)(%rdi), %es // Not used in 64 bit + * mov (8*REG_GS)(%rdi), %gs // Disabled, otherwise we will destroy MSR_GS_BASE + * mov (8*REG_FS)(%rdi), %fs // Disabled, otherwise we will destroy MSR_FS_BASE + * XXX: Should use wrgsbase and wrfsbase to restore the gs and fs register + */ + + /* restore xmm registers */ + fxrstorq (%rdi) + + /* Restore the correct value of EAX and then return */ + + popq %rdi + iretq + .size x86_64_fullcontextrestore, . - x86_64_fullcontextrestore + .end diff --git a/arch/x86_64/src/intel64/intel64_handlers.c b/arch/x86_64/src/intel64/intel64_handlers.c index 3c9b175d228de..87d1e4c74d638 100644 --- a/arch/x86_64/src/intel64/intel64_handlers.c +++ b/arch/x86_64/src/intel64/intel64_handlers.c @@ -62,8 +62,6 @@ #ifndef CONFIG_SUPPRESS_INTERRUPTS static uint64_t *common_handler(int irq, uint64_t *regs) { - board_autoled_on(LED_INIRQ); - /* Current regs non-zero indicates that we are processing an interrupt; * g_current_regs is also used to manage interrupt level context switches. * @@ -86,12 +84,6 @@ static uint64_t *common_handler(int irq, uint64_t *regs) if (regs != g_current_regs) { -#ifdef CONFIG_ARCH_FPU - /* Restore floating point registers */ - - up_restorefpu((uint64_t *)g_current_regs); -#endif - #ifdef CONFIG_ARCH_ADDRENV /* Make sure that the address environment for the previously * running task is closed down gracefully (data caches dump, @@ -141,9 +133,9 @@ static uint64_t *common_handler(int irq, uint64_t *regs) uint64_t *isr_handler(uint64_t *regs, uint64_t irq) { -#ifdef CONFIG_SUPPRESS_INTERRUPTS board_autoled_on(LED_INIRQ); +#ifdef CONFIG_SUPPRESS_INTERRUPTS /* Doesn't return */ PANIC(); @@ -194,7 +186,7 @@ uint64_t *isr_handler(uint64_t *regs, uint64_t irq) } /**************************************************************************** - * Name: isr_handler + * Name: irq_handler * * Description: * This gets called from IRQ vector handling logic in intel64_vectors.S @@ -203,9 +195,9 @@ uint64_t *isr_handler(uint64_t *regs, uint64_t irq) uint64_t *irq_handler(uint64_t *regs, uint64_t irq_no) { -#ifdef CONFIG_SUPPRESS_INTERRUPTS board_autoled_on(LED_INIRQ); +#ifdef CONFIG_SUPPRESS_INTERRUPTS /* Doesn't return */ PANIC(); @@ -217,8 +209,6 @@ uint64_t *irq_handler(uint64_t *regs, uint64_t irq_no) uint64_t *ret; int irq; - board_autoled_on(LED_INIRQ); - /* Get the IRQ number */ irq = (int)irq_no; diff --git a/arch/x86_64/src/intel64/intel64_head.S b/arch/x86_64/src/intel64/intel64_head.S index 34c7bdf8dacff..47a5401880202 100644 --- a/arch/x86_64/src/intel64/intel64_head.S +++ b/arch/x86_64/src/intel64/intel64_head.S @@ -26,7 +26,7 @@ #include #include - .file "intel64_head.S" + .file "intel64_head.S" /**************************************************************************** * Pre-processor definitions @@ -41,106 +41,114 @@ */ /**************************************************************************** - * Macros + * Public Symbols ****************************************************************************/ -/* Trace macros, use like trace 'i' to print char to serial port. */ + .global __pmode_entry /* The 32bit protected mode entry */ + .global __enable_sse_avx + .global __enable_pcid + .global __revoke_low_memory + .global __nxstart /* __nxstart is defined elsewhere */ + .global nx_start /* nx_start is defined elsewhere */ + .global g_idle_topstack /* The end of the idle stack, the start of the heap */ + .global g_mb_info_struct + .global g_mb_magic - .macro trace, ch -#ifdef CONFIG_DEBUG_FEATURES - mov $0x3f8, %dx - mov $\ch, %al - out %al, %dx -#endif - .endm + /* These are the page tables */ + .global g_pdpt_low + .global g_pd_low + .global g_pt_low -/**************************************************************************** - * Public Symbols - ****************************************************************************/ - .global __pmode_entry /* The 32bit protected mode entry */ - .global __nxstart - .global __enable_sse_avx - .global __enable_pcid - .global __revoke_low_memory - .global nx_start /* nx_start is defined elsewhere */ - .global up_lowsetup /* up_lowsetup is defined elsewhere */ - .global g_idle_topstack /* The end of the idle stack, the start of the heap */ - - /* These are the page tables */ - .global pdpt_low - .global pd_low - .global pt_low - - /* These are the GDT */ - .global gdt64_low - .global gdt64_ist_low - .global gdt64_low_end - - .global ist64_low + /* These are the GDT */ + .global g_gdt64_low + .global g_gdt64_ist_low + .global g_gdt64_low_end + + .global g_ist64_low /**************************************************************************** * The multiboot2 header ****************************************************************************/ - .set HEADER_LENGTH, header_end - header_start - .set CHECKSUM, -(MULTIBOOT2_HEADER_MAGIC + MULTIBOOT_ARCHITECTURE_I386 + HEADER_LENGTH) + .set HEADER_LENGTH, header_end - header_start + .set CHECKSUM, -(MULTIBOOT2_HEADER_MAGIC + MULTIBOOT_ARCHITECTURE_I386 + HEADER_LENGTH) - .section ".multiboot", "a" - .align 8 + .section ".multiboot", "a" + .align 8 header_start: -#ifndef CONFIG_ARCH_EXCLUDE_MULTIBOOT - .long MULTIBOOT2_HEADER_MAGIC - .long MULTIBOOT_ARCHITECTURE_I386 - .long HEADER_LENGTH - .long CHECKSUM - - // multiboot tags go here - - .short MULTIBOOT_HEADER_TAG_END - .short 0 // flags, none set - .long 8 // size, including itself (short + short + long) +#ifdef CONFIG_ARCH_MULTIBOOT2 + .long MULTIBOOT2_HEADER_MAGIC + .long MULTIBOOT_ARCHITECTURE_I386 + .long HEADER_LENGTH + .long CHECKSUM + + /* multiboot tags go here */ + + .short MULTIBOOT_HEADER_TAG_INFORMATION_REQUEST + .short 0 /* flags, none set */ + .long 24 /* size, including itself (short + short + long) */ + .long MULTIBOOT_TAG_TYPE_EFI64 + .long MULTIBOOT_TAG_TYPE_FRAMEBUFFER + .long MULTIBOOT_TAG_TYPE_ACPI_OLD + .long MULTIBOOT_TAG_TYPE_ACPI_NEW + + .short MULTIBOOT_HEADER_TAG_END + .short 0 /* flags, none set */ + .long 8 /* size, including itself (short + short + long) */ #endif header_end: .code16 .section ".realmode", "ax" - .type __reset_entry, @function +/**************************************************************************** + * Name: __reset_entry + * + * Description: + * Real mode entry point. + * + ****************************************************************************/ + + .type __reset_entry, @function + __reset_entry: - // Load a GDT for protected mode - movl $loader_gdt_ptr, %ebx - lgdtl (%ebx) + /* Load a GDT for protected mode */ + movl $loader_gdt_ptr, %ebx + lgdtl (%ebx) - // enable protected mode in CR0 - mov %cr0,%eax - or $X86_CR0_PE,%al - mov %eax,%cr0 + /* enable protected mode in CR0 */ + mov %cr0, %eax + or $X86_CR0_PE, %al + mov %eax, %cr0 - // Long jump into protected mode - // Hardcode the address - ljmpl $0x8,$0x100000 + /* Long jump into protected mode. Hardcode the address. */ + ljmpl $0x8, $0x100000 - // Loader GDT and GDTR + /* Loader GDT and GDTR */ .align(16) .global loader_gdt loader_gdt: - .quad 0 - .quad 0x00cf9a000000ffff - .quad 0x00cf92000000ffff - + .quad 0 + .quad 0x00cf9a000000ffff + .quad 0x00cf92000000ffff loader_gdt_ptr: .short loader_gdt_ptr - loader_gdt - 1 - .long loader_gdt + .long loader_gdt - .size __reset_entry, . - __reset_entry + .size __reset_entry, . - __reset_entry /**************************************************************************** * .text ****************************************************************************/ - .code32 - .section ".loader.text", "ax" + .code32 + .section ".loader.text", "ax" + +start32_0: + mov $0x10, %ax + mov %ax, %ss + mov %ax, %ds /**************************************************************************** * Name: __pmode_entry @@ -151,107 +159,108 @@ loader_gdt_ptr: * ****************************************************************************/ -start32_0: - mov $0x10, %ax - mov %ax, %ss - mov %ax, %ds + .type __pmode_entry, @function - .type __pmode_entry, @function __pmode_entry: start32: +#ifdef CONFIG_ARCH_MULTIBOOT2 + movl %ebx, g_mb_info_struct + movl %eax, g_mb_magic +#endif - // initialize rest of the page directory - lea pd_low, %edi - lea pt_low, %esi + /* initialize rest of the page directory */ + lea g_pd_low, %edi + lea g_pt_low, %esi - // Popluate the lower 4GB as non-present - // for ecx = 0...512 * 4 : Loop and setup the page directories - mov $0x800, %ecx // 512 * 4 + /* Popluate the lower 4GB as non-present + * for ecx = 0...512 * 4 : Loop and setup the page directories + */ + mov $0x800, %ecx /* 512 * 4 */ epd_loop: - mov %esi, %edx - or $(X86_PAGE_WR | X86_PAGE_PRESENT), %edx - mov %edx, 0(%edi) - add $(X86_PAGE_ENTRY_SIZE), %edi + mov %esi, %edx + or $(X86_PAGE_WR | X86_PAGE_PRESENT), %edx + mov %edx, 0(%edi) + add $(X86_PAGE_ENTRY_SIZE), %edi - // for ebx = 0...1024: Loop and clear the page table of each page directory - mov $1024, %ebx + /* for ebx = 0...1024: Loop and clear the page table of each page directory */ + mov $1024, %ebx ept_loop: - movl $0x0, 0(%esi) - add $4, %esi + movl $0x0, 0(%esi) + add $4, %esi - // end for ebx - dec %ebx - jnz ept_loop + /* end for ebx */ + dec %ebx + jnz ept_loop - // end for ecx - dec %ecx - jnz epd_loop + /* end for ecx */ + dec %ecx + jnz epd_loop - // Temporary populate the lower 128MB on 1:1 mapping - lea pd_low, %edi - mov $(X86_PAGE_GLOBAL | X86_PAGE_WR | X86_PAGE_PRESENT | X86_PAGE_HUGE), %eax + /* Temporary populate the lower 128MB on 1:1 mapping */ + lea g_pd_low, %edi + mov $(X86_PAGE_GLOBAL | X86_PAGE_WR | X86_PAGE_PRESENT | X86_PAGE_HUGE), %eax - // for ecx = 0...64 : Loop and setup 64x 2MB page directories - mov $64, %ecx + /* for ecx = 0...64 : Loop and setup 64x 2MB page directories */ + mov $64, %ecx pd_loop: - mov %eax, 0(%edi) - add $(HUGE_PAGE_SIZE), %eax - add $(X86_PAGE_ENTRY_SIZE), %edi - - // end for ecx - dec %ecx - jnz pd_loop - - // Populate the 1GB after 4GB boundary with Global mapping to kernel code - // This creates maps the lower 1GB to 4GB~5GB - lea pdpt_low, %edi - mov $(X86_PAGE_GLOBAL | X86_PAGE_WR | X86_PAGE_PRESENT | X86_PAGE_HUGE), %eax - - mov $0x4, %ecx - mov %eax, 0(%edi, %ecx, X86_PAGE_ENTRY_SIZE) - - // Enable PAE - mov %cr4, %eax - or $(X86_CR4_PAE | X86_CR4_PGE), %eax - mov %eax, %cr4 - - // Load the 4 level page table - // Level 1 and 2 were preset at build time in assembly for this loading - // process - // 4KiB page table is used - // Kernel mapped to 1GB HiMem - lea pml4, %eax - mov %eax, %cr3 - - movl $MSR_MTRR_DEF_TYPE, %ecx - rdmsr - or $MTRR_ENABLE, %eax - wrmsr - - movl $MSR_EFER, %ecx - rdmsr - or $EFER_LME, %eax - wrmsr - - // Enable paging related bits in CR0 - mov $(X86_CR0_PG | X86_CR0_WP | X86_CR0_PE), %eax - mov %eax, %cr0 - - // Enable FGSBASE - mov %cr4, %eax - or $X86_CR4_FGSBASE, %eax - mov %eax, %cr4 - - // Load a GDT with 64bits mode set - lgdt gdt64_ptr - - // Long jump into 64 bit mode, updating cs to new GDT - ljmpl $(X86_GDT_CODE_SEL), $start64 - - .code64 + mov %eax, 0(%edi) + add $(HUGE_PAGE_SIZE), %eax + add $(X86_PAGE_ENTRY_SIZE), %edi + + /* end for ecx */ + dec %ecx + jnz pd_loop + + /* Populate the 1GB after 4GB boundary with Global mapping to kernel code. + * This creates maps the lower 1GB to 4GB~5GB + */ + lea g_pdpt_low, %edi + mov $(X86_PAGE_GLOBAL | X86_PAGE_WR | X86_PAGE_PRESENT | X86_PAGE_HUGE), %eax + + mov $0x4, %ecx + mov %eax, 0(%edi, %ecx, X86_PAGE_ENTRY_SIZE) + + /* Enable PAE */ + mov %cr4, %eax + or $(X86_CR4_PAE | X86_CR4_PGE), %eax + mov %eax, %cr4 + + /* Load the 4 level page table. + * Level 1 and 2 were preset at build time in assembly for this loading process. + * 4KiB page table is used. + * Kernel mapped to 1GB HiMem + */ + lea pml4, %eax + mov %eax, %cr3 + + movl $MSR_MTRR_DEF_TYPE, %ecx + rdmsr + or $MTRR_ENABLE, %eax + wrmsr + + movl $MSR_EFER, %ecx + rdmsr + or $EFER_LME, %eax + wrmsr + + /* Enable paging related bits in CR0 */ + mov $(X86_CR0_PG | X86_CR0_WP | X86_CR0_PE), %eax + mov %eax, %cr0 + + /* Enable FGSBASE */ + mov %cr4, %eax + or $X86_CR4_FGSBASE, %eax + mov %eax, %cr4 + + /* Load a GDT with 64bits mode set */ + lgdt gdt64_ptr + + /* Long jump into 64 bit mode, updating cs to new GDT */ + ljmpl $(X86_GDT_CODE_SEL), $start64 + + .code64 start64: - - // Set Segement Registers for proper iret, etc. operation + /* Set Segement Registers for proper iret, etc. operation */ mov $(X86_GDT_DATA_SEL), %ax mov %ax, %ss mov %ax, %ds @@ -259,76 +268,53 @@ start64: mov %ax, %fs mov %ax, %gs - // Finally, we can start the OS + /* Properly setup RSP to idle stack */ + movabs $g_idle_topstack, %rbx + mov (%rbx), %rsp + + /* We use jmp instruction below which doesn't push 1 byte on stack, so we + * have to push a dummy value here, otherwise SSE instructions calledd + * during initialization will fail. + */ + pushq $0 + + /* Finally, we can start the OS */ movabs $__nxstart, %rbx jmp *%rbx .size __pmode_entry, . - __pmode_entry /**************************************************************************** - * Name: __nxstart + * Name: __revoke_low_memory * * Description: - * Do low-level initialization and call nx_start + * Revoke the lower 128MB memory mapping * ****************************************************************************/ - .section .text, "ax" - .type __nxstart, @function - -__nxstart: - /* We are now in high memory, will revoke the lower 128MB memory mapping in lowsetup*/ - - //clear out bss section - movabs $_sbss, %rbx - movabs $_ebss, %rdx -clear_bss: - movb $0, (%rbx) - inc %rbx - cmp %rbx, %rdx - jne clear_bss - - // Properly setup RSP to idle stack - movabs $g_idle_topstack, %rbx - mov (%rbx), %rsp - - /* Initialize and start NuttX */ - call up_lowsetup /* Low-level, pre-OS initialization */ - - call nx_start /* Start NuttX */ - - /* NuttX will not return */ - /* We should never end up here */ - /* If we really do, then we are doomed, halting the processor for ever */ + .section .text, "ax" + .type __revoke_low_memory, @function - cli -hang: - hlt /* Halt machine should NuttX return */ - jmp hang - .size __nxstart, . - __nxstart - - .type __revoke_low_memory, @function __revoke_low_memory: + /* Revoke the lower 128MB memory mapping */ + lea g_pd_low, %edi + lea g_pt_low, %esi - /* Revoke the lower 128MB memory mapping */ - lea pd_low, %edi - lea pt_low, %esi - - // for ecx = 0...64 : Loop and setup 64x 2MB page directories - mov $64, %ecx + /* for ecx = 0...64 : Loop and setup 64x 2MB page directories */ + mov $64, %ecx npd_loop: - mov %esi, %edx - or $(X86_PAGE_WR | X86_PAGE_PRESENT), %edx - mov %edx, 0(%edi) - add $(PAGE_SIZE), %esi - add $(X86_PAGE_ENTRY_SIZE), %edi + mov %esi, %edx + or $(X86_PAGE_WR | X86_PAGE_PRESENT), %edx + mov %edx, 0(%edi) + add $(PAGE_SIZE), %esi + add $(X86_PAGE_ENTRY_SIZE), %edi - // end for ecx - dec %ecx - jnz npd_loop + /* end for ecx */ + dec %ecx + jnz npd_loop - ret + ret - .size __revoke_low_memory, . - __revoke_low_memory + .size __revoke_low_memory, . - __revoke_low_memory /**************************************************************************** * Name: __enable_sse_avx @@ -338,28 +324,28 @@ npd_loop: * ****************************************************************************/ - .type __enable_sse_avx, @function + .type __enable_sse_avx, @function __enable_sse_avx: - // Enable SSE - mov %cr0, %rax - mov $(X86_CR0_EM), %rbx - not %rbx - and %rbx, %rax - or $(X86_CR0_MP), %rax - mov %rax, %cr0 + /* Enable SSE */ + mov %cr0, %rax + mov $(X86_CR0_EM), %rbx + not %rbx + and %rbx, %rax + or $(X86_CR0_MP), %rax + mov %rax, %cr0 - // Enable Saving XMM context - mov %cr4, %rax - or $(X86_CR4_OSXFSR | X86_CR4_XMMEXCPT), %rax - mov %rax, %cr4 + /* Enable Saving XMM context */ + mov %cr4, %rax + or $(X86_CR4_OSXFSR | X86_CR4_XMMEXCPT), %rax + mov %rax, %cr4 - // Setup MXCSR, masking all SSE precision exception - ldmxcsr mxcsr_mem + /* Setup MXCSR, masking all SSE precision exception */ + ldmxcsr mxcsr_mem - ret + ret - .size __enable_sse_avx, . - __enable_sse_avx + .size __enable_sse_avx, . - __enable_sse_avx /**************************************************************************** * Name: __enable_pcid @@ -369,97 +355,95 @@ __enable_sse_avx: * ****************************************************************************/ - .type __enable_pcid, @function + .type __enable_pcid, @function __enable_pcid: - // Enable PCID and FGSBASE - mov %cr4, %rax - or $X86_CR4_PCIDE, %rax - mov %rax, %cr4 + /* Enable PCID and FGSBASE */ + mov %cr4, %rax + or $X86_CR4_PCIDE, %rax + mov %rax, %cr4 - ret + ret - .size __enable_pcid, . - __enable_pcid + .size __enable_pcid, . - __enable_pcid /**************************************************************************** * .data ****************************************************************************/ - .section ".loader.data", "ax" - - // IST for 64 bit long mode - // will be filled in up_irq - .align(16) -ist64_low: - .long 0 - .quad 0xdeadbeefdeadbee0 - .quad 0xdeadbeefdeadbee1 - .quad 0xdeadbeefdeadbee2 - .quad 0 - .quad 0 - .quad 0 - .quad 0 - .quad 0 - .quad 0 - .quad 0 - .quad 0 - .quad 0 - .word 0 - - // GDT for 64 bit long mode - .align(16) -gdt64_low: - .quad 0 - .quad X86_GDT_CODE64_ENTRY - .quad X86_GDT_DATA_ENTRY - .quad X86_GDT_CODE32_ENTRY - .quad X86_GDT_DATA_ENTRY - .quad X86_GDT_CODE64_ENTRY -gdt64_ist_low: - .quad 0x0 // TSS segment low - .quad 0x0 // TSS segment high -gdt64_low_end: + .section ".loader.data", "ax" + + /* IST for 64 bit long mode will be filled in up_irq */ + .align(16) +g_ist64_low: + .long 0 + .quad 0xdeadbeefdeadbee0 + .quad 0xdeadbeefdeadbee1 + .quad 0xdeadbeefdeadbee2 + .quad 0 + .quad 0 + .quad 0 + .quad 0 + .quad 0 + .quad 0 + .quad 0 + .quad 0 + .quad 0 + .word 0 + + /* GDT for 64 bit long mode */ + .align(16) +g_gdt64_low: + .quad 0 + .quad X86_GDT_CODE64_ENTRY + .quad X86_GDT_DATA_ENTRY + .quad X86_GDT_CODE32_ENTRY + .quad X86_GDT_DATA_ENTRY + .quad X86_GDT_CODE64_ENTRY +g_gdt64_ist_low: + .quad 0x0 /* TSS segment low */ + .quad 0x0 /* TSS segment high */ +g_gdt64_low_end: gdt64_ptr: - .short gdt64_low_end - gdt64_low - 1 - .long gdt64_low + .short g_gdt64_low_end - g_gdt64_low - 1 + .long g_gdt64_low mxcsr_mem: - .long 0x00001f80 + .long 0x00001f80 - .align(PAGE_SIZE) + .align(PAGE_SIZE) pml4: - .quad pdpt_low + X86_PAGE_PRESENT + X86_PAGE_WR + .quad g_pdpt_low + X86_PAGE_PRESENT + X86_PAGE_WR - .align(PAGE_SIZE) -pdpt_low: - .quad pd_low + X86_PAGE_PRESENT + X86_PAGE_WR - .quad pd_2_low + X86_PAGE_PRESENT + X86_PAGE_WR - .quad pd_3_low + X86_PAGE_PRESENT + X86_PAGE_WR - .quad pd_4_low + X86_PAGE_PRESENT + X86_PAGE_WR + .align(PAGE_SIZE) +g_pdpt_low: + .quad g_pd_low + X86_PAGE_PRESENT + X86_PAGE_WR + .quad pd_2_low + X86_PAGE_PRESENT + X86_PAGE_WR + .quad pd_3_low + X86_PAGE_PRESENT + X86_PAGE_WR + .quad pd_4_low + X86_PAGE_PRESENT + X86_PAGE_WR - .fill X86_NUM_PAGE_ENTRY - 4, X86_PAGE_ENTRY_SIZE, 0 + .fill X86_NUM_PAGE_ENTRY - 4, X86_PAGE_ENTRY_SIZE, 0 - .align(PAGE_SIZE) -pd_low: - .fill X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0 + .align(PAGE_SIZE) +g_pd_low: + .fill X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0 - .align(PAGE_SIZE) + .align(PAGE_SIZE) pd_2_low: - .fill X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0 + .fill X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0 - .align(PAGE_SIZE) + .align(PAGE_SIZE) pd_3_low: - .fill X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0 + .fill X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0 - .align(PAGE_SIZE) + .align(PAGE_SIZE) pd_4_low: - .fill X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0 - - .align(PAGE_SIZE) -pt_low: - .fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0 - .fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0 - .fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0 - .fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0 - + .fill X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0 + + .align(PAGE_SIZE) +g_pt_low: + .fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0 + .fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0 + .fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0 + .fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0 diff --git a/arch/x86_64/src/intel64/intel64_hpet.c b/arch/x86_64/src/intel64/intel64_hpet.c new file mode 100644 index 0000000000000..c906fa3b86998 --- /dev/null +++ b/arch/x86_64/src/intel64/intel64_hpet.c @@ -0,0 +1,496 @@ +/**************************************************************************** + * arch/x86_64/src/intel64/intel64_hpet.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include +#include +#include +#include + +#include "intel64_hpet.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* HPET timer channel */ + +struct intel64_hpet_chan_s +{ + uint8_t irq; +}; + +/* HPET timer driver */ + +struct intel64_hpet_s +{ + struct intel64_tim_ops_s *ops; + uint64_t base; + uint32_t clk_per_fs; + uint8_t timers; + bool initialized; + struct intel64_hpet_chan_s chans[CONFIG_INTEL64_HPET_CHANNELS]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Helpers */ + +static void intel64_hpet_putreg(struct intel64_hpet_s *hpet, uint32_t offset, + uint64_t value); +static uint64_t intel64_hpet_getreg(struct intel64_hpet_s *hpet, + uint32_t offset); + +/* Ops */ + +static void intel64_hpet_enable(struct intel64_tim_dev_s *dev, bool en); +static void intel64_hpet_cmpset(struct intel64_tim_dev_s *dev, uint8_t timer, + uint64_t cmp); +static uint64_t intel64_hpet_cmpget(struct intel64_tim_dev_s *dev, + uint8_t timer); +static uint64_t intel64_hpet_cntget(struct intel64_tim_dev_s *dev); +static uint64_t intel64_hpet_intget(struct intel64_tim_dev_s *dev, + uint8_t timer); +static void intel64_hpet_intack(struct intel64_tim_dev_s *dev, + uint8_t timer); +static void intel64_hpet_cntset(struct intel64_tim_dev_s *dev, + uint64_t cntr); +static uint32_t intel64_hpet_perget(struct intel64_tim_dev_s *dev); +static int intel64_hpet_setisr(struct intel64_tim_dev_s *dev, uint8_t timer, + xcpt_t handler, void *arg, bool periodic); +static void intel64_hpet_enint(struct intel64_tim_dev_s *dev, uint8_t tim); +static void intel64_hpet_disint(struct intel64_tim_dev_s *dev, uint8_t tim); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* HPET ops */ + +static struct intel64_tim_ops_s g_intel64_hpet_ops = +{ + .enable = intel64_hpet_enable, + .getperiod = intel64_hpet_perget, + .getcounter = intel64_hpet_cntget, + .setcounter = intel64_hpet_cntset, + .setcompare = intel64_hpet_cmpset, + .getcompare = intel64_hpet_cmpget, + .getint = intel64_hpet_intget, + .ackint = intel64_hpet_intack, + .setisr = intel64_hpet_setisr, + .enableint = intel64_hpet_enint, + .disableint = intel64_hpet_disint +}; + +/* HPET driver instance */ + +static struct intel64_hpet_s g_intel64_hpet = +{ + .ops = &g_intel64_hpet_ops, + .initialized = false, + .chans = + { + /* Channel 0 (Timer 0) */ + + { + .irq = HPET0_IRQ, + }, + +#if CONFIG_INTEL64_HPET_CHANNELS > 1 + /* Channel 1 (Timer 1) */ + + { + .irq = HPET1_IRQ, + }, +#endif + +#if CONFIG_INTEL64_HPET_CHANNELS > 2 + /* Channel 2 (Timer 2) */ + + { + .irq = HPET2_IRQ + }, +#endif + } +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: intel64_hpet_putreg + * + * Description: + * Put a 64-bit register value by offset + * + ****************************************************************************/ + +static void intel64_hpet_putreg(struct intel64_hpet_s *hpet, uint32_t offset, + uint64_t value) +{ + return mmio_write64((void *)(hpet->base + offset), value); +} + +/**************************************************************************** + * Name: intel64_hpet_getreg + * + * Description: + * Get a 64-bit register value by offset + * + ****************************************************************************/ + +static uint64_t intel64_hpet_getreg(struct intel64_hpet_s *hpet, + uint32_t offset) +{ + return mmio_read64((void *)(hpet->base + offset)); +} + +/**************************************************************************** + * Name: intel64_hpet_enable + * + * Description: + * Allow main counter to run and allow timer interrupts + * + ****************************************************************************/ + +static void intel64_hpet_enable(struct intel64_tim_dev_s *dev, bool en) +{ + struct intel64_hpet_s *hpet = (struct intel64_hpet_s *)dev; + uint64_t regval = 0; + + regval = intel64_hpet_getreg(hpet, HPET_GCONF_OFFSET); + + if (en) + { + regval |= HPET_GCONF_ENABLE; + } + else + { + regval &= ~HPET_GCONF_ENABLE; + } + + intel64_hpet_putreg(hpet, HPET_GCONF_OFFSET, regval); +} + +/**************************************************************************** + * Name: intel64_hpet_cmpset + * + * Description: + * Set a compare register to a given value. + * + ****************************************************************************/ + +static void intel64_hpet_cmpset(struct intel64_tim_dev_s *dev, uint8_t timer, + uint64_t cmp) +{ + struct intel64_hpet_s *hpet = (struct intel64_hpet_s *)dev; + DEBUGASSERT(timer < hpet->timers); + intel64_hpet_putreg(hpet, HPET_TCOMP_OFFSET(timer), cmp); +} + +/**************************************************************************** + * Name: intel64_hpet_cmpget + * + * Description: + * Get a compare register to a given value. + * + ****************************************************************************/ + +static uint64_t intel64_hpet_cmpget(struct intel64_tim_dev_s *dev, + uint8_t timer) +{ + struct intel64_hpet_s *hpet = (struct intel64_hpet_s *)dev; + DEBUGASSERT(timer < hpet->timers); + return intel64_hpet_getreg(hpet, HPET_TCOMP_OFFSET(timer)); +} + +/**************************************************************************** + * Name: intel64_hpet_intget + * + * Description: + * Get a interrupt status register. + * + ****************************************************************************/ + +static uint64_t intel64_hpet_intget(struct intel64_tim_dev_s *dev, + uint8_t timer) +{ + struct intel64_hpet_s *hpet = (struct intel64_hpet_s *)dev; + return (intel64_hpet_getreg(hpet, HPET_GISR_OFFSET) & + HPET_GISR_TINT(timer)); +} + +/**************************************************************************** + * Name: intel64_hpet_intack + * + * Description: + * ACK interrupt. + * + ****************************************************************************/ + +static void intel64_hpet_intack(struct intel64_tim_dev_s *dev, + uint8_t timer) +{ + struct intel64_hpet_s *hpet = (struct intel64_hpet_s *)dev; + intel64_hpet_putreg(hpet, HPET_GISR_OFFSET, HPET_GISR_TINT(timer)); +} + +/**************************************************************************** + * Name: intel64_hpet_cntget + * + * Description: + * Get the main counter. + * + ****************************************************************************/ + +static uint64_t intel64_hpet_cntget(struct intel64_tim_dev_s *dev) +{ + struct intel64_hpet_s *hpet = (struct intel64_hpet_s *)dev; + return intel64_hpet_getreg(hpet, HPET_MCNTR_OFFSET); +} + +/**************************************************************************** + * Name: intel64_hpet_cntset + * + * Description: + * Set the main counter. + * + ****************************************************************************/ + +static void intel64_hpet_cntset(struct intel64_tim_dev_s *dev, + uint64_t cntr) +{ + struct intel64_hpet_s *hpet = (struct intel64_hpet_s *)dev; + return intel64_hpet_putreg(hpet, HPET_MCNTR_OFFSET, cntr); +} + +/**************************************************************************** + * Name: intel64_hpet_perget + * + * Description: + * Get the main counter period in femtosecounds (1e-15 sec). + * + ****************************************************************************/ + +static uint32_t intel64_hpet_perget(struct intel64_tim_dev_s *dev) +{ + struct intel64_hpet_s *hpet = (struct intel64_hpet_s *)dev; + return hpet->clk_per_fs; +} + +/**************************************************************************** + * Name: intel64_hpet_setisr + * + * Description: + * Configure interrupt handler for a given timer + * + ****************************************************************************/ + +static int intel64_hpet_setisr(struct intel64_tim_dev_s *dev, uint8_t timer, + xcpt_t handler, void *arg, bool periodic) +{ + struct intel64_hpet_s *hpet = (struct intel64_hpet_s *)dev; + uint64_t regval = 0; + uint8_t irq = hpet->chans[timer].irq; + + DEBUGASSERT(timer < hpet->timers); + + regval = intel64_hpet_getreg(hpet, HPET_TCONF_OFFSET(timer)); + + if (periodic) + { + if ((regval & HPET_TCONF_PERCAP) == 0) + { + tmrerr("Periodic not supported"); + return -EPERM; + } + + regval |= HPET_TCONF_PERCAP; + } + else + { + regval &= ~HPET_TCONF_PERCAP; + } + + /* Route interrupts */ + + regval |= HPET_TCONF_INTROUTE(irq - IRQ0); + + /* Set level triggered mode. + * + * Edge triggered mode seems to work well on QEMU, but for real hardware, + * unwanted interrupt is generated when we enable timer interrupts. + */ + + regval |= HPET_TCONF_INTTYPE; + + /* Set 64-bit mode */ + + regval &= ~HPET_TCONF_32MODE; + + /* Write Timer configuration */ + + intel64_hpet_putreg(hpet, HPET_TCONF_OFFSET(timer), regval); + + if (handler == NULL) + { + /* Disable interrupt */ + + irq_attach(irq, handler, arg); + up_disable_irq(irq); + } + else + { + /* Set callback and enable interrupt */ + + irq_attach(irq, handler, arg); + up_enable_irq(irq); + } + + return OK; +} + +/**************************************************************************** + * Name: intel64_hpet_enint + * + * Description: + * Enable interrupt + * + ****************************************************************************/ + +static void intel64_hpet_enint(struct intel64_tim_dev_s *dev, uint8_t tim) +{ + struct intel64_hpet_s *hpet = (struct intel64_hpet_s *)dev; + uint64_t regval = 0; + + DEBUGASSERT(tim < hpet->timers); + + regval = intel64_hpet_getreg(hpet, HPET_TCONF_OFFSET(tim)); + regval |= HPET_TCONF_INTEN; + intel64_hpet_putreg(hpet, HPET_TCONF_OFFSET(tim), regval); +} + +/**************************************************************************** + * Name: intel64_hpet_disint + * + * Description: + * Disable interrupt + * + ****************************************************************************/ + +static void intel64_hpet_disint(struct intel64_tim_dev_s *dev, uint8_t tim) +{ + struct intel64_hpet_s *hpet = (struct intel64_hpet_s *)dev; + uint64_t regval = 0; + + DEBUGASSERT(tim < hpet->timers); + + regval = intel64_hpet_getreg(hpet, HPET_TCONF_OFFSET(tim)); + regval &= ~HPET_TCONF_INTEN; + intel64_hpet_putreg(hpet, HPET_TCONF_OFFSET(tim), regval); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: intel64_hpet_init + * + * Description: + * Initialize HPET timer with a given base address + * + ****************************************************************************/ + +struct intel64_tim_dev_s *intel64_hpet_init(uint64_t base) +{ + struct intel64_hpet_s *hpet = &g_intel64_hpet; + uint64_t regval = 0; + + if (hpet->initialized == false) + { + /* Store HPET base */ + + hpet->base = base; + + /* Map HPET region */ + + up_map_region((void *)hpet->base, HPET_REGION_SIZE, + (X86_PAGE_PRESENT | X86_PAGE_WR | X86_PAGE_NOCACHE)); + + /* Get capabilities */ + + regval = intel64_hpet_getreg(hpet, HPET_GCAPID_OFFSET); + hpet->clk_per_fs = ((regval & HPET_GCAPID_CLKPER_MASK) >> + HPET_GCAPID_CLKPER_SHIFT); + hpet->timers = ((regval & HPET_GCAPID_NUMTIM_MASK) >> + HPET_GCAPID_NUMTIM_SHIFT); + + hpet->timers = (hpet->timers > CONFIG_INTEL64_HPET_CHANNELS ? + CONFIG_INTEL64_HPET_CHANNELS : hpet->timers); + + /* Connect ops */ + + hpet->ops = &g_intel64_hpet_ops; + + if (regval & HPET_GCAPID_LEGROUTE) + { + /* Configure legacy mode. + * + * There is no way to disable PIT interrupts (?) other than enable + * legacy mode for HPET. Otherwise unwanted PIT interupts will + * interfere with HPET interrupts, making them useless. + */ + + intel64_hpet_putreg(hpet, HPET_GCONF_OFFSET, HPET_GCONF_LEGERT); + } + else + { + /* Not supported */ + + ASSERT(0); + } + + /* Enable HPET */ + + intel64_hpet_enable((struct intel64_tim_dev_s *)hpet, true); + + tmrinfo("clk_per_fs = %" PRId32 " timers = %d\n", + hpet->clk_per_fs, hpet->timers); + + /* Initialization done */ + + hpet->initialized = true; + } + + return (struct intel64_tim_dev_s *)hpet; +} diff --git a/arch/x86_64/src/intel64/intel64_hpet.h b/arch/x86_64/src/intel64/intel64_hpet.h new file mode 100644 index 0000000000000..9eddb865e458c --- /dev/null +++ b/arch/x86_64/src/intel64/intel64_hpet.h @@ -0,0 +1,118 @@ +/**************************************************************************** + * arch/x86_64/src/intel64/intel64_hpet.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_X86_64_SRC_INTEL64_INTEL64_HPET_H +#define __ARCH_X86_64_SRC_INTEL64_INTEL64_HPET_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Helpers ******************************************************************/ + +#define INTEL64_TIM_ENABLE(d, e) ((d)->ops->enable(d, e)) +#define INTEL64_TIM_GETPERIOD(d) ((d)->ops->getperiod(d)) +#define INTEL64_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) +#define INTEL64_TIM_SETCOUNTER(d, c) ((d)->ops->setcounter(d, c)) +#define INTEL64_TIM_SETCOMPARE(d, t, c) ((d)->ops->setcompare(d, t, c)) +#define INTEL64_TIM_GETCOMPARE(d, t) ((d)->ops->getcompare(d, t)) +#define INTEL64_TIM_GETINT(d, t) ((d)->ops->getint(d, t)) +#define INTEL64_TIM_ACKINT(d, t) ((d)->ops->ackint(d, t)) +#define INTEL64_TIM_SETISR(d, t, h, a, p) ((d)->ops->setisr(d, t, h, a, p)) +#define INTEL64_TIM_ENABLEINT(d, t) ((d)->ops->enableint(d, t)) +#define INTEL64_TIM_DISABLEINT(d, t) ((d)->ops->disableint(d, t)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* TIM Device Structure */ + +struct intel64_tim_ops_s; +struct intel64_tim_dev_s +{ + struct intel64_tim_ops_s *ops; +}; + +/* TIM Operations */ + +struct intel64_tim_ops_s +{ + void (*enable)(struct intel64_tim_dev_s *dev, bool en); + uint32_t (*getperiod)(struct intel64_tim_dev_s *dev); + uint64_t (*getcounter)(struct intel64_tim_dev_s *dev); + void (*setcounter)(struct intel64_tim_dev_s *dev, uint64_t count); + void (*setcompare)(struct intel64_tim_dev_s *dev, uint8_t timer, + uint64_t compare); + uint64_t (*getcompare)(struct intel64_tim_dev_s *dev, uint8_t timer); + uint64_t (*getint)(struct intel64_tim_dev_s *dev, uint8_t timer); + void (*ackint)(struct intel64_tim_dev_s *dev, uint8_t timer); + int (*setisr)(struct intel64_tim_dev_s *dev, uint8_t timer, + xcpt_t handler, void * arg, bool periodic); + void (*enableint)(struct intel64_tim_dev_s *dev, uint8_t tim); + void (*disableint)(struct intel64_tim_dev_s *dev, uint8_t tim); +}; + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: intel64_hpet_init + * + * Description: + * Initialize HPET timer with a given base address + * + ****************************************************************************/ + +struct intel64_tim_dev_s *intel64_hpet_init(uint64_t base); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_X86_64_SRC_INTEL64_INTEL64_HPET_H */ diff --git a/arch/x86_64/src/intel64/intel64_irq.c b/arch/x86_64/src/intel64/intel64_irq.c index 3e9494e5f8ded..cc82c00deb4d5 100644 --- a/arch/x86_64/src/intel64/intel64_irq.c +++ b/arch/x86_64/src/intel64/intel64_irq.c @@ -36,6 +36,8 @@ #include #include +#include + #include "x86_64_internal.h" #include "intel64.h" @@ -47,6 +49,15 @@ #define IRQ_STACK_SIZE 0x2000 +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct intel64_irq_priv_s +{ + uint8_t busy; +}; + /**************************************************************************** * Private Function Prototypes ****************************************************************************/ @@ -72,7 +83,9 @@ uint8_t *g_isr_stack_end = g_isr_stack + IRQ_STACK_SIZE - 16; * Private Data ****************************************************************************/ -static struct idt_entry_s idt_entries[256]; +static struct idt_entry_s g_idt_entries[NR_IRQS]; +static struct intel64_irq_priv_s g_irq_priv[NR_IRQS]; +static spinlock_t g_irq_spin; /**************************************************************************** * Private Functions @@ -176,8 +189,8 @@ static void up_ist_init(void) tss_l.limit_low = (((104 - 1) & 0xffff)); /* Segment limit = TSS size - 1 */ - tss_l.base_low = ((uintptr_t)ist64 & 0x00ffffff); /* Low address 1 */ - tss_l.base_high = (((uintptr_t)ist64 & 0xff000000) >> 24); /* Low address 2 */ + tss_l.base_low = ((uintptr_t)g_ist64 & 0x00ffffff); /* Low address 1 */ + tss_l.base_high = (((uintptr_t)g_ist64 & 0xff000000) >> 24); /* Low address 2 */ tss_l.P = 1; @@ -186,17 +199,17 @@ static void up_ist_init(void) tss_l.AC = 1; tss_l.EX = 1; - tss_h = (((uintptr_t)ist64 >> 32) & 0xffffffff); /* High address */ + tss_h = (((uintptr_t)g_ist64 >> 32) & 0xffffffff); /* High address */ - gdt64[X86_GDT_ISTL_SEL_NUM] = tss_l; + g_gdt64[X86_GDT_ISTL_SEL_NUM] = tss_l; /* memcpy used to handle type punning compiler warning */ - memcpy((void *)&gdt64[X86_GDT_ISTH_SEL_NUM], - (void *)&tss_h, sizeof(gdt64[0])); + memcpy((void *)&g_gdt64[X86_GDT_ISTH_SEL_NUM], + (void *)&tss_h, sizeof(g_gdt64[0])); - ist64->IST1 = (uintptr_t)g_interrupt_stack_end; - ist64->IST2 = (uintptr_t)g_isr_stack_end; + g_ist64->IST1 = (uintptr_t)g_interrupt_stack_end; + g_ist64->IST2 = (uintptr_t)g_isr_stack_end; asm volatile ("mov $0x30, %%ax; ltr %%ax":::"memory", "rax"); } @@ -345,6 +358,7 @@ legacy_pic_irq_handler(int irq, uint32_t *regs, void *arg) #ifndef CONFIG_ARCH_INTEL64_DISABLE_INT_INIT static void up_ioapic_init(void) { + uint32_t maxintr; int i; up_map_region((void *)IOAPIC_BASE, HUGE_PAGE_SIZE, @@ -352,7 +366,7 @@ static void up_ioapic_init(void) /* Setup the IO-APIC, remap the interrupt to 32~ */ - uint32_t maxintr = (up_ioapic_read(IOAPIC_REG_VER) >> 16) & 0xff; + maxintr = (up_ioapic_read(IOAPIC_REG_VER) >> 16) & 0xff; for (i = 0; i < maxintr; i++) { @@ -373,7 +387,7 @@ static void up_ioapic_init(void) static void up_idtentry(unsigned int index, uint64_t base, uint16_t sel, uint8_t flags, uint8_t ist) { - struct idt_entry_s *entry = &idt_entries[index]; + struct idt_entry_s *entry = &g_idt_entries[index]; entry->lobase = base & 0xffff; entry->hibase = (base >> 16) & 0xffff; @@ -400,11 +414,13 @@ static void up_idtentry(unsigned int index, uint64_t base, uint16_t sel, * ****************************************************************************/ -struct idt_ptr_s idt_ptr; - static inline void up_idtinit(void) { - memset(&idt_entries, 0, sizeof(struct idt_entry_s)*256); + size_t offset = 0; + uint64_t vector = 0; + int irq = 0; + + memset(&g_idt_entries, 0, sizeof(g_idt_entries)); /* Set each ISR/IRQ to the appropriate vector with selector=8 and with * 32-bit interrupt gate. Interrupt gate (vs. trap gate) will leave @@ -444,26 +460,20 @@ static inline void up_idtinit(void) up_idtentry(ISR30, (uint64_t)vector_isr30, 0x08, 0x8e, 0x2); up_idtentry(ISR31, (uint64_t)vector_isr31, 0x08, 0x8e, 0x2); - up_idtentry(IRQ0, (uint64_t)vector_irq0, 0x08, 0x8e, 0x1); - up_idtentry(IRQ1, (uint64_t)vector_irq1, 0x08, 0x8e, 0x1); - up_idtentry(IRQ2, (uint64_t)vector_irq2, 0x08, 0x8e, 0x1); - up_idtentry(IRQ3, (uint64_t)vector_irq3, 0x08, 0x8e, 0x1); - up_idtentry(IRQ4, (uint64_t)vector_irq4, 0x08, 0x8e, 0x1); - up_idtentry(IRQ5, (uint64_t)vector_irq5, 0x08, 0x8e, 0x1); - up_idtentry(IRQ6, (uint64_t)vector_irq6, 0x08, 0x8e, 0x1); - up_idtentry(IRQ7, (uint64_t)vector_irq7, 0x08, 0x8e, 0x1); - up_idtentry(IRQ8, (uint64_t)vector_irq8, 0x08, 0x8e, 0x1); - up_idtentry(IRQ9, (uint64_t)vector_irq9, 0x08, 0x8e, 0x1); - up_idtentry(IRQ10, (uint64_t)vector_irq10, 0x08, 0x8e, 0x1); - up_idtentry(IRQ11, (uint64_t)vector_irq11, 0x08, 0x8e, 0x1); - up_idtentry(IRQ12, (uint64_t)vector_irq12, 0x08, 0x8e, 0x1); - up_idtentry(IRQ13, (uint64_t)vector_irq13, 0x08, 0x8e, 0x1); - up_idtentry(IRQ14, (uint64_t)vector_irq14, 0x08, 0x8e, 0x1); - up_idtentry(IRQ15, (uint64_t)vector_irq15, 0x08, 0x8e, 0x1); + /* Set all IRQ vectors */ + + offset = (uint64_t)vector_irq1 - (uint64_t)vector_irq0; + + for (irq = IRQ0, vector = (uint64_t)vector_irq0; + irq <= IRQ255; + irq += 1, vector += offset) + { + up_idtentry(irq, (uint64_t)vector, 0x08, 0x8e, 0x1); + } /* Then program the IDT */ - setidt(&idt_entries, sizeof(struct idt_entry_s) * NR_IRQS - 1); + setidt(&g_idt_entries, sizeof(struct idt_entry_s) * NR_IRQS - 1); } /**************************************************************************** @@ -518,10 +528,31 @@ void up_irqinitialize(void) void up_disable_irq(int irq) { #ifndef CONFIG_ARCH_INTEL64_DISABLE_INT_INIT - if (irq >= IRQ0) + irqstate_t flags = spin_lock_irqsave(&g_irq_spin); + + if (irq > IRQ255) + { + /* Not supported yet */ + + ASSERT(0); + } + + if (g_irq_priv[irq].busy > 0) { - up_ioapic_mask_pin(irq - IRQ0); + g_irq_priv[irq].busy -= 1; } + + if (g_irq_priv[irq].busy == 0) + { + /* One time disable */ + + if (irq >= IRQ0) + { + up_ioapic_mask_pin(irq - IRQ0); + } + } + + spin_unlock_irqrestore(&g_irq_spin, flags); #endif } @@ -536,10 +567,37 @@ void up_disable_irq(int irq) void up_enable_irq(int irq) { #ifndef CONFIG_ARCH_INTEL64_DISABLE_INT_INIT - if (irq >= IRQ0) + irqstate_t flags = spin_lock_irqsave(&g_irq_spin); + +# ifndef CONFIG_IRQCHAIN + /* Check if IRQ is free if we don't support IRQ chains */ + + if (g_irq_priv[irq].busy) { - up_ioapic_unmask_pin(irq - IRQ0); + ASSERT(0); } +# endif + + if (irq > IRQ255) + { + /* Not supported yet */ + + ASSERT(0); + } + + if (g_irq_priv[irq].busy == 0) + { + /* One time enable */ + + if (irq >= IRQ0) + { + up_ioapic_unmask_pin(irq - IRQ0); + } + } + + g_irq_priv[irq].busy += 1; + + spin_unlock_irqrestore(&g_irq_spin, flags); #endif } diff --git a/arch/x86_64/src/intel64/intel64_lowsetup.c b/arch/x86_64/src/intel64/intel64_lowsetup.c index 51f04e2009e6b..ac544e970d616 100644 --- a/arch/x86_64/src/intel64/intel64_lowsetup.c +++ b/arch/x86_64/src/intel64/intel64_lowsetup.c @@ -25,7 +25,6 @@ #include #include -#include #include "x86_64_internal.h" @@ -45,12 +44,12 @@ * in high address. */ -volatile uint64_t *pdpt; -volatile uint64_t *pd; -volatile uint64_t *pt; +volatile uint64_t *g_pdpt; +volatile uint64_t *g_pd; +volatile uint64_t *g_pt; -volatile struct ist_s *ist64; -volatile struct gdt_entry_s *gdt64; +volatile struct ist_s *g_ist64; +volatile struct gdt_entry_s *g_gdt64; /**************************************************************************** * Private Functions @@ -61,15 +60,15 @@ volatile struct gdt_entry_s *gdt64; ****************************************************************************/ /**************************************************************************** - * Name: up_lowsetup + * Name: intel64_lowsetup * * Description: - * Called from intel64_head BEFORE starting the operating system in order + * Called from __nxstart BEFORE starting the operating system in order * perform any necessary, early initialization. * ****************************************************************************/ -void up_lowsetup(void) +void intel64_lowsetup(void) { /* we should be in long mode at this point */ @@ -79,37 +78,20 @@ void up_lowsetup(void) /* Setup pointers for accessing Page table and GDT in high address */ - pdpt = (uint64_t *)((uintptr_t)&pdpt_low + X86_64_LOAD_OFFSET); - pd = (uint64_t *)((uintptr_t)&pd_low + X86_64_LOAD_OFFSET); - pt = (uint64_t *)((uintptr_t)&pt_low + X86_64_LOAD_OFFSET); + g_pdpt = (uint64_t *)((uintptr_t)&g_pdpt_low + X86_64_LOAD_OFFSET); + g_pd = (uint64_t *)((uintptr_t)&g_pd_low + X86_64_LOAD_OFFSET); + g_pt = (uint64_t *)((uintptr_t)&g_pt_low + X86_64_LOAD_OFFSET); - ist64 = (struct ist_s *)((uintptr_t)&ist64_low + X86_64_LOAD_OFFSET); - gdt64 = (struct gdt_entry_s *)((uintptr_t)&gdt64_low + X86_64_LOAD_OFFSET); + g_ist64 = (struct ist_s *)((uintptr_t)&g_ist64_low + + X86_64_LOAD_OFFSET); + g_gdt64 = (struct gdt_entry_s *)((uintptr_t)&g_gdt64_low + + X86_64_LOAD_OFFSET); /* reload the GDTR with mapped high memory address */ - setgdt((void *)gdt64, (uintptr_t)(&gdt64_low_end - &gdt64_low) - 1); - - /* Do some checking on CPU compatibilities */ - - x86_64_check_and_enable_capability(); + setgdt((void *)g_gdt64, (uintptr_t)(&g_gdt64_low_end - &g_gdt64_low) - 1); /* Revoke the lower memory */ __revoke_low_memory(); - - /* perform board-specific initializations */ - - x86_64_boardinitialize(); - - /* Early serial driver initialization */ - - x86_64_earlyserialinit(); - - x86_64_timer_calibrate_freq(); - -#ifdef CONFIG_LIB_SYSCALL - enable_syscall(); -#endif } - diff --git a/arch/x86_64/src/intel64/intel64_lowsetup.h b/arch/x86_64/src/intel64/intel64_lowsetup.h new file mode 100644 index 0000000000000..a50602a74b128 --- /dev/null +++ b/arch/x86_64/src/intel64/intel64_lowsetup.h @@ -0,0 +1,64 @@ +/**************************************************************************** + * arch/x86_64/src/intel64/intel64_lowsetup.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_X86_64_SRC_INTEL64_INTEL64_LOWSETUP_H +#define __ARCH_X86_64_SRC_INTEL64_INTEL64_LOWSETUP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: intel64_lowsetup + * + * Description: + * Called at the very beginning of _nxstart or up_ap_boot. + * Performs low level initializationincluding setup of the console UART. + * This UART done early so that the serial console is available for + * debugging very early in the boot sequence. + * + ****************************************************************************/ + +void intel64_lowsetup(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_X86_64_SRC_INTEL64_INTEL64_LOWSETUP_H */ diff --git a/arch/x86_64/src/intel64/intel64_map_region.c b/arch/x86_64/src/intel64/intel64_map_region.c index 789f382da7f68..69fd2ce8b8fbd 100644 --- a/arch/x86_64/src/intel64/intel64_map_region.c +++ b/arch/x86_64/src/intel64/intel64_map_region.c @@ -68,7 +68,7 @@ int up_map_region(void *base, int size, int flags) { entry = (curr >> 12) & 0x7ffffff; - pt[entry] = curr | flags; + g_pt[entry] = curr | flags; curr += PAGE_SIZE; } diff --git a/arch/x86_64/src/intel64/intel64_mbfb.c b/arch/x86_64/src/intel64/intel64_mbfb.c new file mode 100644 index 0000000000000..665e79a57a38c --- /dev/null +++ b/arch/x86_64/src/intel64/intel64_mbfb.c @@ -0,0 +1,350 @@ +/**************************************************************************** + * arch/x86_64/src/intel64/intel64_mbfb.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#ifdef CONFIG_MULTBOOT2_FB_TERM +#include +#endif + +#include "x86_64_internal.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct multiboot_fb_s +{ + void *baseaddr; + uint32_t height; + uint32_t width; + uint32_t pitch; + uint8_t bpp; + uint8_t type; +}; + +#ifdef CONFIG_MULTBOOT2_FB_TERM +struct fb_term_s +{ + const struct nx_fontpackage_s *font; + uint32_t cursor_x; + uint32_t cursor_y; +}; +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_MULTBOOT2_FB_TERM +static void fb_term_initialize(void); +static void fb_scroll(void); +#endif +static void fb_clear(void); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct multiboot_fb_s g_fb = +{ + .baseaddr = NULL +}; + +#ifdef CONFIG_MULTBOOT2_FB_TERM +static struct fb_term_s g_fb_term; +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: fb_draw_pixel + * + * Description: + * Draw a pixel on the framebuffer. Note that the color paramter must + * be in the format specified by the bpp of the framebuffer. + * + ****************************************************************************/ + +static void fb_draw_pixel(uint32_t color, uint32_t x, uint32_t y) +{ + /* Check if we support this type of framebuffer */ + + if (g_fb.type != MULTIBOOT_FRAMEBUFFER_TYPE_RGB) + { + return; + } + + /* Make sure we are within the bounds */ + + if (x >= g_fb.width || y >= g_fb.height) + { + return; + } + + switch (g_fb.bpp) + { + case 8: + { + uint8_t *pixel = (uint8_t *)( + (uintptr_t)g_fb.baseaddr + (g_fb.pitch * y) + x); + *pixel = (uint8_t)color; + break; + } + + case 15: + case 16: + { + uint16_t *pixel = (uint16_t *)( + (uintptr_t)g_fb.baseaddr + (g_fb.pitch * y) + x * 2); + *pixel = (uint16_t)color; + break; + } + + case 24: + { + /* We have to be careful here to not overwrite the lower 8bits + * of the next pixel in the buffer. + */ + + uint32_t *pixel = (uint32_t *)( + (uintptr_t)g_fb.baseaddr + (g_fb.pitch * y) + x * 3); + *pixel = (color & 0xffffff) | (*pixel & 0xff000000); + break; + } + + case 32: + { + uint32_t *pixel = (uint32_t *)( + (uintptr_t)g_fb.baseaddr + (g_fb.pitch * y) + x * 4); + *pixel = color; + break; + } + } +} + +#if 0 +/**************************************************************************** + * Name: fb_test_line + * + * Description: + * This is a simple test function that can be used to draw a 45deg + * line across the screen. + * + ****************************************************************************/ + +static void fb_test_line(void) +{ + size_t idx; + uint32_t color; + + switch (fb.bpp) + { + case 8: + color = 0xff; + break; + case 15: + case 16: + color = 0x7fff; + break; + case 24: + color = 0xffffff; + break; + case 32: + color = 0xffffffff; + break; + default: + return; + } + + for (idx = 0; (idx < fb.height) && (idx < fb.width); idx++) + { + fb_draw_pixel(color, idx, idx); + } +} +#endif + +#ifdef CONFIG_MULTBOOT2_FB_TERM +/**************************************************************************** + * Name: fb_term_initialize + ****************************************************************************/ + +static void fb_term_initialize(void) +{ + g_fb_term.font = nxf_getfonthandle(FONTID_DEFAULT); + g_fb_term.cursor_x = 0; + g_fb_term.cursor_y = 0; +} + +/**************************************************************************** + * Name: fb_scroll + ****************************************************************************/ + +static void fb_scroll(void) +{ + void *destp = g_fb.baseaddr; + uint32_t save_rows = 0; + size_t row_size = 0; + uint32_t pxl_row = 0; + + save_rows = ((g_fb.height / g_fb_term.font->metrics.mxheight) - 1); + row_size = g_fb.pitch * g_fb_term.font->metrics.mxheight; + + for (; pxl_row < save_rows * g_fb_term.font->metrics.mxheight; pxl_row++) + { + memcpy(destp, destp + row_size, g_fb.pitch); + destp += g_fb.pitch; + } + + memset(destp, 0, g_fb.pitch * (g_fb.height - pxl_row)); + + g_fb_term.cursor_y -= g_fb_term.font->metrics.mxheight; +} +#endif + +/**************************************************************************** + * Name: fb_clear + ****************************************************************************/ + +static void fb_clear(void) +{ + if (g_fb.baseaddr == NULL) + { + return; + } + + memset(g_fb.baseaddr, 0, g_fb.pitch * g_fb.height); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: x86_64_mb2_fbinitialize + ****************************************************************************/ + +void x86_64_mb2_fbinitialize(struct multiboot_tag_framebuffer *fbt) +{ + g_fb.baseaddr = (void *)(uintptr_t)fbt->common.framebuffer_addr; + g_fb.width = fbt->common.framebuffer_width; + g_fb.height = fbt->common.framebuffer_height; + g_fb.pitch = fbt->common.framebuffer_pitch; + g_fb.bpp = fbt->common.framebuffer_bpp; + g_fb.type = fbt->common.framebuffer_type; + + up_map_region(g_fb.baseaddr, g_fb.pitch * g_fb.height, + X86_PAGE_WR | X86_PAGE_PRESENT | + X86_PAGE_NOCACHE | X86_PAGE_GLOBAL); + + fb_clear(); + +#ifdef CONFIG_MULTBOOT2_FB_TERM + fb_term_initialize(); +#endif +} + +#ifdef CONFIG_MULTBOOT2_FB_TERM +/**************************************************************************** + * Name: fb_putc + ****************************************************************************/ + +void fb_putc(char ch) +{ + const struct nx_fontbitmap_s *fbm; + uint8_t gly_x; + uint8_t gly_y; + + if (g_fb.baseaddr == NULL) + { + return; + } + + if (ch == '\n') + { + g_fb_term.cursor_y += g_fb_term.font->metrics.mxheight; + return; + } + + if (ch == '\r') + { + g_fb_term.cursor_x = 0; + return; + } + + fbm = nxf_getbitmap((NXHANDLE)g_fb_term.font, ch); + if (fbm == NULL) + { + fb_putc('.'); + return; + } + + for (gly_y = 0; gly_y < fbm->metric.height; gly_y++) + { + if (g_fb_term.cursor_y + gly_y >= g_fb.height) + { + fb_scroll(); + fb_putc(ch); + return; + } + + for (gly_x = 0; gly_x < fbm->metric.width; gly_x++) + { + if (g_fb_term.cursor_x + gly_x >= g_fb.width) + { + break; + } + + uint8_t stride = (fbm->metric.width + 7) >> 3; + uint8_t gly_byte = stride * gly_y + (gly_x >> 3); + uint8_t gly_bit = gly_x & 0x7; + uint32_t color = 0; + + if ((fbm->bitmap[gly_byte] >> (7 - gly_bit)) & 0x01) + { + /* White no matter the color depth */ + + color = 0xffffffff; + } + + fb_draw_pixel( + color, g_fb_term.cursor_x + gly_x, g_fb_term.cursor_y + gly_y); + } + } + + g_fb_term.cursor_x += fbm->metric.width; +} +#endif /* CONFIG_MULTBOOT2_FB_TERM */ diff --git a/arch/x86_64/src/intel64/intel64_oneshot.c b/arch/x86_64/src/intel64/intel64_oneshot.c new file mode 100644 index 0000000000000..2822c4100cbd7 --- /dev/null +++ b/arch/x86_64/src/intel64/intel64_oneshot.c @@ -0,0 +1,425 @@ +/**************************************************************************** + * arch/x86_64/src/intel64/intel64_oneshot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "intel64_hpet.h" +#include "intel64_oneshot.h" + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int intel64_oneshot_handler(int irg_num, void * context, void *arg); +static int intel64_allocate_handler(struct intel64_oneshot_s *oneshot); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct intel64_oneshot_s *g_oneshot[CONFIG_INTEL64_ONESHOT_MAXTIMERS]; +static spinlock_t g_oneshot_spin; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: intel64_oneshot_handler + * + * Description: + * Common timer interrupt callback. When any oneshot timer interrupt + * expires, this function will be called. It will forward the call to + * the next level up. + * + * Input Parameters: + * oneshot - The state associated with the expired timer + * + * Returned Value: + * Always returns OK + * + ****************************************************************************/ + +static int intel64_oneshot_handler(int irg_num, void * context, void *arg) +{ + struct intel64_oneshot_s *oneshot = (struct intel64_oneshot_s *)arg; + void *oneshot_arg; + oneshot_handler_t oneshot_handler; + + tmrinfo("Expired...\n"); + DEBUGASSERT(oneshot != NULL && oneshot->handler); + + if (INTEL64_TIM_GETINT(oneshot->tch, oneshot->chan)) + { + /* Disable any further interrupts. */ + + INTEL64_TIM_DISABLEINT(oneshot->tch, oneshot->chan); + INTEL64_TIM_SETISR(oneshot->tch, oneshot->chan, NULL, NULL, false); + INTEL64_TIM_ACKINT(oneshot->tch, oneshot->chan); + + /* The timer is no longer running */ + + oneshot->running = false; + + /* Forward the event, clearing out any vestiges */ + + oneshot_handler = (oneshot_handler_t)oneshot->handler; + oneshot->handler = NULL; + oneshot_arg = (void *)oneshot->arg; + oneshot->arg = NULL; + + oneshot_handler(oneshot_arg); + } + + return OK; +} + +/**************************************************************************** + * Name: intel64_allocate_handler + * + * Description: + * Allocate a timer callback handler for the oneshot instance. + * + * Input Parameters: + * oneshot - The state instance the new oneshot timer + * + * Returned Value: + * Returns zero (OK) on success. This can only fail if the number of + * timers exceeds CONFIG_INTEL64_ONESHOT_MAXTIMERS. + * + ****************************************************************************/ + +static int intel64_allocate_handler(struct intel64_oneshot_s *oneshot) +{ + int ret = -EBUSY; + int i; + + /* Search for an unused handler */ + + for (i = 0; i < CONFIG_INTEL64_ONESHOT_MAXTIMERS; i++) + { + /* Is this handler available? */ + + if (g_oneshot[i] == NULL) + { + /* Yes... assign it to this oneshot */ + + g_oneshot[i] = oneshot; + oneshot->cbndx = i; + ret = OK; + break; + } + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: intel64_oneshot_initialize + * + * Description: + * Initialize the oneshot timer wrapper + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure + * chan Timer counter channel to be used. + * resolution The required resolution of the timer in units of + * microseconds. NOTE that the range is restricted to the + * range of uint16_t (excluding zero). + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int intel64_oneshot_initialize(struct intel64_oneshot_s *oneshot, int chan, + uint16_t resolution) +{ + /* HPET resolution can't be changed, but it is always in terms of ns */ + + UNUSED(resolution); + + /* Get timer */ + + oneshot->tch = intel64_hpet_init(CONFIG_INTEL64_HPET_BASE); + if (oneshot->tch == NULL) + { + tmrerr("ERROR: Failed to allocate HPET timer %d\n", chan); + return -EBUSY; + } + + /* Get the timer period */ + + oneshot->period = INTEL64_TIM_GETPERIOD(oneshot->tch); + oneshot->frequency = 1e15 / oneshot->period; + + /* Initialize the remaining fields in the state structure. */ + + oneshot->chan = chan; + oneshot->running = false; + oneshot->handler = NULL; + oneshot->arg = NULL; + + /* Assign a callback handler to the oneshot */ + + return intel64_allocate_handler(oneshot); +} + +/**************************************************************************** + * Name: intel64_oneshot_max_delay + * + * Description: + * Determine the maximum delay of the one-shot timer (in microseconds) + * + ****************************************************************************/ + +int intel64_oneshot_max_delay(struct intel64_oneshot_s *oneshot, + uint64_t *usec) +{ + DEBUGASSERT(oneshot != NULL && usec != NULL); + + *usec = ((uint64_t)(UINT32_MAX / oneshot->frequency) * + (uint64_t)USEC_PER_SEC); + return OK; +} + +/**************************************************************************** + * Name: intel64_oneshot_start + * + * Description: + * Start the oneshot timer + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure. This + * structure must have been previously initialized via a call to + * intel64_oneshot_initialize(); + * handler The function to call when when the oneshot timer expires. + * arg An opaque argument that will accompany the callback. + * ts Provides the duration of the one shot timer. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int intel64_oneshot_start(struct intel64_oneshot_s *oneshot, + oneshot_handler_t handler, void *arg, + const struct timespec *ts) +{ + uint64_t usec = 0; + uint64_t compare = 0; + irqstate_t flags; + + tmrinfo("handler=%p arg=%p, ts=(%lu, %lu)\n", + handler, arg, (unsigned long)ts->tv_sec, + (unsigned long)ts->tv_nsec); + + DEBUGASSERT(oneshot && handler && ts); + DEBUGASSERT(oneshot->tch); + + /* Was the oneshot already running? */ + + flags = spin_lock_irqsave(&g_oneshot_spin); + if (oneshot->running) + { + /* Yes.. then cancel it */ + + tmrinfo("Already running... cancelling\n"); + intel64_oneshot_cancel(oneshot, NULL); + } + + /* Save the new handler and its argument */ + + oneshot->handler = handler; + oneshot->arg = arg; + + /* Express the delay in microseconds */ + + usec = (uint64_t)ts->tv_sec * USEC_PER_SEC + + (uint64_t)(ts->tv_nsec / NSEC_PER_USEC); + + /* HPET use free runnin up-counter and a comparators which generate events + * only on a equal event. This can results in event miss if we set too + * small delay. In that case we just set a minimum value for delay that + * seem to work. + */ + + if (usec < CONFIG_INTEL64_HPET_MIN_DELAY) + { + usec = CONFIG_INTEL64_HPET_MIN_DELAY; + } + + /* Get the timer counter frequency and determine the number of counts need + * to achieve the requested delay. + * + * frequency = ticks / second + * ticks = seconds * frequency + * = (usecs * frequency) / USEC_PER_SEC; + */ + + compare = (usec * (uint64_t)oneshot->frequency) / USEC_PER_SEC; + + /* Set up to receive the callback when the interrupt occurs */ + + INTEL64_TIM_SETISR(oneshot->tch, oneshot->chan, intel64_oneshot_handler, + oneshot, false); + + /* Set comparator ahed of the current counter */ + + compare += INTEL64_TIM_GETCOUNTER(oneshot->tch); + INTEL64_TIM_SETCOMPARE(oneshot->tch, oneshot->chan, compare); + + /* Enable interrupts. We should get the callback when the interrupt + * occurs. + */ + + INTEL64_TIM_ENABLEINT(oneshot->tch, oneshot->chan); + + oneshot->running = true; + spin_unlock_irqrestore(&g_oneshot_spin, flags); + return OK; +} + +/**************************************************************************** + * Name: intel64_oneshot_cancel + * + * Description: + * Cancel the oneshot timer and return the time remaining on the timer. + * + * NOTE: This function may execute at a high rate with no timer running (as + * when pre-emption is enabled and disabled). + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure. This + * structure must have been previously initialized via a call to + * intel64_oneshot_initialize(); + * ts The location in which to return the time remaining on the + * oneshot timer. A time of zero is returned if the timer is + * not running. + * + * Returned Value: + * Zero (OK) is returned on success. A call to up_timer_cancel() when + * the timer is not active should also return success; a negated errno + * value is returned on any failure. + * + ****************************************************************************/ + +int intel64_oneshot_cancel(struct intel64_oneshot_s *oneshot, + struct timespec *ts) +{ + irqstate_t flags; + uint64_t usec; + uint64_t sec; + uint64_t nsec; + uint64_t counter; + uint64_t compare; + + /* Was the timer running? */ + + flags = spin_lock_irqsave(&g_oneshot_spin); + if (!oneshot->running) + { + /* No.. Just return zero timer remaining and successful cancellation. + * This function may execute at a high rate with no timer running + * (as when pre-emption is enabled and disabled). + */ + + ts->tv_sec = 0; + ts->tv_nsec = 0; + spin_unlock_irqrestore(&g_oneshot_spin, flags); + return OK; + } + + /* Yes.. Get the timer counter and compare registers and stop the + * counter. + */ + + tmrinfo("Cancelling...\n"); + + counter = INTEL64_TIM_GETCOUNTER(oneshot->tch); + compare = INTEL64_TIM_GETCOMPARE(oneshot->tch, oneshot->chan); + + /* Now we can disable the interrupt and stop the timer. */ + + INTEL64_TIM_DISABLEINT(oneshot->tch, oneshot->chan); + INTEL64_TIM_SETISR(oneshot->tch, oneshot->chan, NULL, NULL, false); + + oneshot->running = false; + oneshot->handler = NULL; + oneshot->arg = NULL; + spin_unlock_irqrestore(&g_oneshot_spin, flags); + + /* Did the caller provide us with a location to return the time + * remaining? + */ + + if (ts) + { + /* Yes.. then calculate and return the time remaining on the + * oneshot timer. + */ + + /* The total time remaining is the difference. Convert that + * to units of microseconds. + * + * frequency = ticks / second + * seconds = ticks * frequency + * usecs = (ticks * USEC_PER_SEC) / frequency; + */ + + usec = ((compare - counter) * USEC_PER_SEC) / + oneshot->frequency; + + /* Return the time remaining in the correct form */ + + sec = usec / USEC_PER_SEC; + nsec = ((usec) - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; + + ts->tv_sec = (time_t)sec; + ts->tv_nsec = (unsigned long)nsec; + + tmrinfo("remaining (%lu, %lu)\n", + (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + } + + return OK; +} diff --git a/arch/x86_64/src/intel64/intel64_oneshot.h b/arch/x86_64/src/intel64/intel64_oneshot.h new file mode 100644 index 0000000000000..fd9a024f66a59 --- /dev/null +++ b/arch/x86_64/src/intel64/intel64_oneshot.h @@ -0,0 +1,177 @@ +/**************************************************************************** + * arch/x86_64/src/intel64/intel64_oneshot.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_X86_64_SRC_INTEL64_INTEL64_ONESHOT_H +#define __ARCH_X86_64_SRC_INTEL64_INTEL64_ONESHOT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* This describes the callback function that will be invoked when the oneshot + * timer expires. The oneshot fires, the client will receive: + * + * arg - The opaque argument provided when the interrupt was registered + */ + +typedef void (*oneshot_handler_t)(void *arg); + +/* The oneshot client must allocate an instance of this structure and called + * intel64_oneshot_initialize() before using the oneshot facilities. The + * client should not access the contents of this structure directly since + * the contents are subject to change. + */ + +struct intel64_oneshot_s +{ + uint8_t chan; + uint8_t cbndx; + volatile bool running; + struct intel64_tim_dev_s *tch; + volatile oneshot_handler_t handler; + volatile void *arg; + uint32_t frequency; + uint32_t period; +}; + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: intel64_oneshot_initialize + * + * Description: + * Initialize the oneshot timer wrapper + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure + * chan Timer counter channel to be used. + * resolution The required resolution of the timer in units of + * microseconds. NOTE that the range is restricted to the + * range of uint16_t (excluding zero). + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int intel64_oneshot_initialize(struct intel64_oneshot_s *oneshot, int chan, + uint16_t resolution); + +/**************************************************************************** + * Name: intel64_oneshot_max_delay + * + * Description: + * Determine the maximum delay of the one-shot timer (in microseconds) + * + ****************************************************************************/ + +int intel64_oneshot_max_delay(struct intel64_oneshot_s *oneshot, + uint64_t *usec); + +/**************************************************************************** + * Name: intel64_oneshot_start + * + * Description: + * Start the oneshot timer + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure. This + * structure must have been previously initialized via a call to + * intel64_oneshot_initialize(); + * handler The function to call when when the oneshot timer expires. + * arg An opaque argument that will accompany the callback. + * ts Provides the duration of the one shot timer. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int intel64_oneshot_start(struct intel64_oneshot_s *oneshot, + oneshot_handler_t handler, void *arg, + const struct timespec *ts); + +/**************************************************************************** + * Name: intel64_oneshot_cancel + * + * Description: + * Cancel the oneshot timer and return the time remaining on the timer. + * + * NOTE: This function may execute at a high rate with no timer running (as + * when pre-emption is enabled and disabled). + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure. This + * structure must have been previously initialized via a call to + * intel64_oneshot_initialize(); + * ts The location in which to return the time remaining on the + * oneshot timer. A time of zero is returned if the timer is + * not running. + * + * Returned Value: + * Zero (OK) is returned on success. A call to up_timer_cancel() when + * the timer is not active should also return success; a negated errno + * value is returned on any failure. + * + ****************************************************************************/ + +int intel64_oneshot_cancel(struct intel64_oneshot_s *oneshot, + struct timespec *ts); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_X86_64_SRC_INTEL64_INTEL64_ONESHOT_H */ diff --git a/arch/x86_64/src/intel64/intel64_oneshot_lower.c b/arch/x86_64/src/intel64/intel64_oneshot_lower.c new file mode 100644 index 0000000000000..3e6f324b51abb --- /dev/null +++ b/arch/x86_64/src/intel64/intel64_oneshot_lower.c @@ -0,0 +1,324 @@ +/**************************************************************************** + * arch/x86_64/src/intel64/intel64_oneshot_lower.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "intel64_oneshot.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure describes the state of the oneshot timer lower-half driver + */ + +struct intel64_oneshot_lowerhalf_s +{ + struct oneshot_lowerhalf_s lh; + struct intel64_oneshot_s oneshot; + oneshot_callback_t callback; + void *arg; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void intel64_oneshot_handler(void *arg); + +static int intel64_max_delay(struct oneshot_lowerhalf_s *lower, + struct timespec *ts); +static int intel64_start(struct oneshot_lowerhalf_s *lower, + oneshot_callback_t callback, void *arg, + const struct timespec *ts); +static int intel64_cancel(struct oneshot_lowerhalf_s *lower, + struct timespec *ts); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Lower half operations */ + +static const struct oneshot_operations_s g_oneshot_ops = +{ + .max_delay = intel64_max_delay, + .start = intel64_start, + .cancel = intel64_cancel, +}; + +static spinlock_t g_oneshotlow_spin; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: intel64_oneshot_handler + * + * Description: + * Timer expiration handler + * + * Input Parameters: + * arg - Should be the same argument provided when intel64_oneshot_start() + * was called. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void intel64_oneshot_handler(void *arg) +{ + struct intel64_oneshot_lowerhalf_s *priv = arg; + oneshot_callback_t callback; + void *cbarg; + + DEBUGASSERT(priv != NULL); + + /* Perhaps the callback was nullified in a race condition with + * intel64_cancel? + */ + + if (priv->callback) + { + /* Sample and nullify BEFORE executing callback (in case the callback + * restarts the oneshot). + */ + + callback = priv->callback; + cbarg = priv->arg; + priv->callback = NULL; + priv->arg = NULL; + + /* Then perform the callback */ + + callback(&priv->lh, cbarg); + } +} + +/**************************************************************************** + * Name: intel64_max_delay + * + * Description: + * Determine the maximum delay of the one-shot timer (in microseconds) + * + * Input Parameters: + * lower An instance of the lower-half oneshot state structure. This + * structure must have been previously initialized via a call to + * oneshot_initialize(); + * ts The location in which to return the maximum delay. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int intel64_max_delay(struct oneshot_lowerhalf_s *lower, + struct timespec *ts) +{ + struct intel64_oneshot_lowerhalf_s *priv = + (struct intel64_oneshot_lowerhalf_s *)lower; + uint64_t usecs; + uint64_t sec; + int ret; + + DEBUGASSERT(priv != NULL && ts != NULL); + ret = intel64_oneshot_max_delay(&priv->oneshot, &usecs); + if (ret >= 0) + { + sec = usecs / 1000000; + usecs -= 1000000 * sec; + + ts->tv_sec = (time_t)sec; + ts->tv_nsec = (long)(usecs * 1000); + } + + return ret; +} + +/**************************************************************************** + * Name: intel64_start + * + * Description: + * Start the oneshot timer + * + * Input Parameters: + * lower An instance of the lower-half oneshot state structure. This + * structure must have been previously initialized via a call to + * oneshot_initialize(); + * handler The function to call when when the oneshot timer expires. + * arg An opaque argument that will accompany the callback. + * ts Provides the duration of the one shot timer. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int intel64_start(struct oneshot_lowerhalf_s *lower, + oneshot_callback_t callback, void *arg, + const struct timespec *ts) +{ + struct intel64_oneshot_lowerhalf_s *priv = + (struct intel64_oneshot_lowerhalf_s *)lower; + irqstate_t flags; + int ret; + + DEBUGASSERT(priv != NULL && callback != NULL && ts != NULL); + + /* Save the callback information and start the timer */ + + flags = spin_lock_irqsave(&g_oneshotlow_spin); + priv->callback = callback; + priv->arg = arg; + ret = intel64_oneshot_start(&priv->oneshot, + intel64_oneshot_handler, + priv, ts); + spin_unlock_irqrestore(&g_oneshotlow_spin, flags); + + if (ret < 0) + { + tmrerr("ERROR: intel64_oneshot_start failed\n"); + } + + return ret; +} + +/**************************************************************************** + * Name: intel64_cancel + * + * Description: + * Cancel the oneshot timer and return the time remaining on the timer. + * + * NOTE: This function may execute at a high rate with no timer running (as + * when pre-emption is enabled and disabled). + * + * Input Parameters: + * lower Caller allocated instance of the oneshot state structure. This + * structure must have been previously initialized via a call to + * oneshot_initialize(); + * ts The location in which to return the time remaining on the + * oneshot timer. A time of zero is returned if the timer is + * not running. + * + * Returned Value: + * Zero (OK) is returned on success. A call to up_timer_cancel() when + * the timer is not active should also return success; a negated errno + * value is returned on any failure. + * + ****************************************************************************/ + +static int intel64_cancel(struct oneshot_lowerhalf_s *lower, + struct timespec *ts) +{ + struct intel64_oneshot_lowerhalf_s *priv = + (struct intel64_oneshot_lowerhalf_s *)lower; + irqstate_t flags; + int ret; + + DEBUGASSERT(priv != NULL); + + /* Cancel the timer */ + + flags = spin_lock_irqsave(&g_oneshotlow_spin); + ret = intel64_oneshot_cancel(&priv->oneshot, ts); + priv->callback = NULL; + priv->arg = NULL; + spin_unlock_irqrestore(&g_oneshotlow_spin, flags); + + if (ret < 0) + { + tmrerr("ERROR: intel64_oneshot_cancel failed\n"); + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: oneshot_initialize + * + * Description: + * Initialize the oneshot timer and return a oneshot lower half driver + * instance. + * + * Input Parameters: + * chan Timer counter channel to be used. + * resolution The required resolution of the timer in units of + * microseconds. NOTE that the range is restricted to the + * range of uint16_t (excluding zero). + * + * Returned Value: + * On success, a non-NULL instance of the oneshot lower-half driver is + * returned. NULL is return on any failure. + * + ****************************************************************************/ + +struct oneshot_lowerhalf_s *oneshot_initialize(int chan, uint16_t resolution) +{ + struct intel64_oneshot_lowerhalf_s *priv; + int ret; + + /* Allocate an instance of the lower half driver */ + + priv = (struct intel64_oneshot_lowerhalf_s *) + kmm_zalloc(sizeof(struct intel64_oneshot_lowerhalf_s)); + if (priv == NULL) + { + tmrerr("ERROR: Failed to initialized state structure\n"); + return NULL; + } + + /* Initialize the lower-half driver structure */ + + priv->lh.ops = &g_oneshot_ops; + + /* Initialize the contained INTEL64 oneshot timer */ + + ret = intel64_oneshot_initialize(&priv->oneshot, chan, resolution); + if (ret < 0) + { + tmrerr("ERROR: intel64_oneshot_initialize failed: %d\n", ret); + kmm_free(priv); + return NULL; + } + + return &priv->lh; +} diff --git a/arch/x86_64/src/intel64/intel64_saveusercontext.S b/arch/x86_64/src/intel64/intel64_saveusercontext.S index 17d2d2733f71e..1c5a14a9f5ee6 100644 --- a/arch/x86_64/src/intel64/intel64_saveusercontext.S +++ b/arch/x86_64/src/intel64/intel64_saveusercontext.S @@ -26,42 +26,15 @@ #include #include "x86_64_internal.h" - .file "intel64_saveusercontext.S" - -/************************************************************************** - * Pre-processor Definitions - **************************************************************************/ - -/**************************************************************************** - * Macros - ****************************************************************************/ - -/* Trace macros, use like trace 'i' to print char to serial port. */ - - .macro chout, addr, ch -#ifdef CONFIG_DEBUG_FEATURES - mov $\addr, %dx - mov $\ch, %al - out %al, %dx -#endif - .endm - - .macro trace, ch -#ifdef CONFIG_DEBUG_FEATURES - push %eax - push %edx - chout 0x3f8, \ch - pop %edx - pop %eax -#endif - .endm + .file "intel64_saveusercontext.S" /************************************************************************** * .text **************************************************************************/ - .text -.code64 + .text + .code64 + /************************************************************************** * Name: up_saveusercontext * @@ -84,66 +57,66 @@ * **************************************************************************/ - .globl up_saveusercontext - .type up_saveusercontext, @function + .globl up_saveusercontext + .type up_saveusercontext, @function up_saveusercontext: - // callee saved regs - movq %rbx, (8*REG_RBX)(%rdi) - movq %r12, (8*REG_R12)(%rdi) - movq %r13, (8*REG_R13)(%rdi) - movq %r14, (8*REG_R14)(%rdi) - movq %r15, (8*REG_R15)(%rdi) - - // save xmm registers - fxsaveq (%rdi) - - /* Save the value of SP as will be at the time of the IRET that will - * appear to be the return from this function. - * - * CURRENT STACK IRET STACK - * ------------------------------ ----------------- - * RIP - * CS - * RFLAGS - * RSP - * ESP->Return address SS - * Argument Alignment (16bytes) - * - */ - - leaq 8(%rsp), %rcx - movq %rcx, (8*REG_RSP)(%rdi) - - /* Fetch the PC from the stack and save it in the save block */ - - movq 0(%rsp), %rcx - movq %rcx, (8*REG_RIP)(%rdi) - - /* Save the framepointer */ - - movq %rbp, (8*REG_RBP)(%rdi) - - /* Save EAX=1. This will be the "apparent" return value from this - * function when context is switch back to this thread. The non-zero - * return value is the indication that we have been resumed. - */ - - movq $1, (8*REG_RAX)(%rdi) - - /* Get and save the interrupt state */ - - pushf - pop %rcx - movq %rcx, (8*REG_RFLAGS)(%rdi) - - /* And return 0 -- The zero return value is the indication that that - * this is the original, "true" return from the function. - * - * 'ret' will remove the RIP from the top of the stack. - */ - - xor %rax, %rax - ret - .size up_saveusercontext, . - up_saveusercontext - .end + /* callee saved regs */ + movq %rbx, (8*REG_RBX)(%rdi) + movq %r12, (8*REG_R12)(%rdi) + movq %r13, (8*REG_R13)(%rdi) + movq %r14, (8*REG_R14)(%rdi) + movq %r15, (8*REG_R15)(%rdi) + + /* save xmm registers */ + fxsaveq (%rdi) + + /* Save the value of SP as will be at the time of the IRET that will + * appear to be the return from this function. + * + * CURRENT STACK IRET STACK + * ------------------------------ ----------------- + * RIP + * CS + * RFLAGS + * RSP + * ESP->Return address SS + * Argument Alignment (16bytes) + * + */ + + leaq 8(%rsp), %rcx + movq %rcx, (8*REG_RSP)(%rdi) + + /* Fetch the PC from the stack and save it in the save block */ + + movq 0(%rsp), %rcx + movq %rcx, (8*REG_RIP)(%rdi) + + /* Save the framepointer */ + + movq %rbp, (8*REG_RBP)(%rdi) + + /* Save EAX=1. This will be the "apparent" return value from this + * function when context is switch back to this thread. The non-zero + * return value is the indication that we have been resumed. + */ + + movq $1, (8*REG_RAX)(%rdi) + + /* Get and save the interrupt state */ + + pushf + pop %rcx + movq %rcx, (8*REG_RFLAGS)(%rdi) + + /* And return 0 -- The zero return value is the indication that that + * this is the original, "true" return from the function. + * + * 'ret' will remove the RIP from the top of the stack. + */ + + xor %rax, %rax + ret + .size up_saveusercontext, . - up_saveusercontext + .end diff --git a/arch/x86_64/src/intel64/intel64_serial.c b/arch/x86_64/src/intel64/intel64_serial.c index 00896fc1f8dd8..d8fe7e81eede2 100644 --- a/arch/x86_64/src/intel64/intel64_serial.c +++ b/arch/x86_64/src/intel64/intel64_serial.c @@ -82,6 +82,11 @@ void uart_putreg(uart_addrwidth_t base, unsigned int offset, * ****************************************************************************/ +void up_lowputc(char ch) +{ + fb_putc(ch); +} + int up_putc(int ch) { /* Check for LF */ @@ -90,15 +95,16 @@ int up_putc(int ch) { /* Add CR */ - x86_64_lowputc('\r'); + up_lowputc('\r'); } - x86_64_lowputc(ch); + up_lowputc(ch); return ch; } - #endif /* USE_SERIALDRIVER */ +#ifdef USE_EARLYSERIALINIT + void x86_64_earlyserialinit(void) { u16550_earlyserialinit(); @@ -108,3 +114,4 @@ void x86_64_serialinit(void) { u16550_serialinit(); } +#endif diff --git a/arch/x86_64/src/intel64/intel64_stackframe.c b/arch/x86_64/src/intel64/intel64_stackframe.c index 4ebc9c40665b5..a0c690979954d 100644 --- a/arch/x86_64/src/intel64/intel64_stackframe.c +++ b/arch/x86_64/src/intel64/intel64_stackframe.c @@ -85,12 +85,12 @@ void *up_stack_frame(struct tcb_s *tcb, size_t frame_size) } ret = tcb->stack_base_ptr; - memset(ret, 0, tcb->adj_stack_size); + memset(ret, 0, frame_size); /* Save the adjusted stack values in the struct tcb_s */ tcb->stack_base_ptr = (uint8_t *)tcb->stack_base_ptr + frame_size; - tcb->adj_stack_size -= frame_size; + tcb->adj_stack_size -= frame_size + 8; /* And return the pointer to the allocated region */ diff --git a/arch/x86_64/src/intel64/intel64_start.c b/arch/x86_64/src/intel64/intel64_start.c new file mode 100644 index 0000000000000..c1e02a6ddaa71 --- /dev/null +++ b/arch/x86_64/src/intel64/intel64_start.c @@ -0,0 +1,187 @@ +/**************************************************************************** + * arch/x86_64/src/intel64/intel64_start.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include + +#include "x86_64_internal.h" + +#include "intel64_lowsetup.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* This holds information passed by the multiboot2 bootloader */ + +uint32_t g_mb_magic __attribute__((section(".loader.bss"))); +uint32_t g_mb_info_struct __attribute__((section(".loader.bss"))); +uintptr_t g_acpi_rsdp = 0; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifdef CONFIG_ARCH_MULTIBOOT2 +/**************************************************************************** + * Name: x86_64_mb2_config + * + * Description: + * Parse multiboot2 info. + * + ****************************************************************************/ + +static void x86_64_mb2_config(void) +{ + struct multiboot_tag *tag; + + /* Check that we were actually booted by a multiboot2 bootloader */ + + if (g_mb_magic != MULTIBOOT2_BOOTLOADER_MAGIC) + { + return; + } + + for (tag = (struct multiboot_tag *)(uintptr_t)(g_mb_info_struct + 8); + tag->type != MULTIBOOT_TAG_TYPE_END; + tag = (struct multiboot_tag *)((uint8_t *)tag + + ((tag->size + 7) & ~7))) + { + switch (tag->type) + { + case MULTIBOOT_TAG_TYPE_EFI64: + { + break; + } + + case MULTIBOOT_TAG_TYPE_ACPI_OLD: + { + struct multiboot_tag_old_acpi *acpi + = (struct multiboot_tag_old_acpi *)tag; + g_acpi_rsdp = (uintptr_t)acpi->rsdp; + break; + } + + case MULTIBOOT_TAG_TYPE_ACPI_NEW: + { + struct multiboot_tag_new_acpi *acpi = + (struct multiboot_tag_new_acpi *)tag; + g_acpi_rsdp = (uintptr_t)acpi->rsdp; + break; + } + +#ifdef CONFIG_MULTBOOT2_FB_TERM + case MULTIBOOT_TAG_TYPE_FRAMEBUFFER: + { + x86_64_mb2_fbinitialize( + (struct multiboot_tag_framebuffer *)tag); + break; + } +#endif + + default: + break; + } + } +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __nxstart + * + * Description: + * Do low-level initialization and call nx_start. + * + ****************************************************************************/ + +void __nxstart(void) +{ + uint64_t *dest = NULL; + + /* Do some checking on CPU compatibilities at the top of this function. + * BSS cleanup can be optimized with vector instructions, so we need to + * enable SSE at this point. + */ + + x86_64_check_and_enable_capability(); + + /* Clear .bss. The compiler can optimize this with vector instructions, + * so this *must be* called after enabling SSE instructions. + */ + + for (dest = (uint64_t *)_sbss; dest < (uint64_t *)_ebss; ) + { + *dest++ = 0; + } + +#ifdef CONFIG_ARCH_MULTIBOOT2 + /* Handle multiboot2 info */ + + x86_64_mb2_config(); +#endif + + /* Low-level, pre-OS initialization */ + + intel64_lowsetup(); + +#ifdef CONFIG_ARCH_X86_64_ACPI + /* Initialize ACPI */ + + acpi_init(g_acpi_rsdp); +#endif + + /* perform board-specific initializations */ + + x86_64_boardinitialize(); + +#ifdef USE_EARLYSERIALINIT + /* Early serial driver initialization */ + + x86_64_earlyserialinit(); +#endif + + x86_64_timer_calibrate_freq(); + +#ifdef CONFIG_LIB_SYSCALL + enable_syscall(); +#endif + + /* Start NuttX */ + + nx_start(); + + /* Shouldn't get here */ + + for (; ; ); +} diff --git a/arch/x86_64/src/intel64/intel64_systemreset.c b/arch/x86_64/src/intel64/intel64_systemreset.c new file mode 100644 index 0000000000000..e3309f191bdad --- /dev/null +++ b/arch/x86_64/src/intel64/intel64_systemreset.c @@ -0,0 +1,62 @@ +/**************************************************************************** + * arch/x86_64/src/intel64/intel64_systemreset.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_systemreset + * + * Description: + * Internal, intel64 reset logic. + * + ****************************************************************************/ + +void up_systemreset(void) +{ + uint8_t regval = (X86_RST_CNT_CPU_RST | + X86_RST_CNT_SYS_RST | + X86_RST_CNT_FULL_RST); + + /* Write to Reset Control Register */ + + outb(regval, X86_RST_CNT_REG); + + while (1) + { + asm volatile("hlt"); + } +} diff --git a/arch/x86_64/src/intel64/intel64_testset.S b/arch/x86_64/src/intel64/intel64_testset.S new file mode 100644 index 0000000000000..77dde153a3f94 --- /dev/null +++ b/arch/x86_64/src/intel64/intel64_testset.S @@ -0,0 +1,71 @@ +/**************************************************************************** + * arch/x86/src/intel64/intel64_testset.S + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + + .file "intel64_head.S" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/************************************************************************** + * .text + **************************************************************************/ + + .text + .code64 + +/**************************************************************************** + * Name: up_testset + * + * Description: + * Perform an atomic test and set operation on the provided spinlock. + * + * This function must be provided via the architecture-specific logic. + * + * Input Parameters: + * lock - A reference to the spinlock object. + * + * Returned Value: + * The spinlock is always locked upon return. The previous value of the + * spinlock variable is returned, either SP_LOCKED if the spinlock was + * previously locked (meaning that the test-and-set operation failed to + * obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked + * (meaning that we successfully obtained the lock). + * + ****************************************************************************/ + + .globl up_testset + .type up_testset, @function +up_testset: + /* Set the value to be written (SP_LOCKED for test-and-set) */ + + movq $SP_LOCKED, %rax + + /* Atomic exchange, the old value is returned in rax */ + + xchg %rax, (%rdi) + ret diff --git a/arch/x86_64/src/intel64/intel64_tickless.c b/arch/x86_64/src/intel64/intel64_tickless.c deleted file mode 100644 index 6524e97056cb0..0000000000000 --- a/arch/x86_64/src/intel64/intel64_tickless.c +++ /dev/null @@ -1,472 +0,0 @@ -/**************************************************************************** - * arch/x86_64/src/intel64/intel64_tickless.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Tickless OS Support. - * - * When CONFIG_SCHED_TICKLESS is enabled, all support for timer interrupts - * is suppressed and the platform specific code is expected to provide the - * following custom functions. - * - * void sim_timer_initialize(void): Initializes the timer facilities. - * Called early in the initialization sequence (by up_initialize()). - * int up_timer_gettime(struct timespec *ts): Returns the current - * time from the platform specific time source. - * int up_timer_cancel(void): Cancels the interval timer. - * int up_timer_start(const struct timespec *ts): Start (or re-starts) - * the interval timer. - * - * The RTOS will provide the following interfaces for use by the platform- - * specific interval timer implementation: - * - * void sched_timer_expiration(void): Called by the platform-specific - * logic when the interval timer expires. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include - -#ifdef CONFIG_SCHED_TICKLESS - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define NS_PER_USEC 1000UL -#define NS_PER_MSEC 1000000UL -#define NS_PER_SEC 1000000000UL - -#define TMR_IRQ IRQ14 - -#define ROUND_INT_DIV(s, d) (s + (d >> 1)) / d - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -unsigned long x86_64_timer_freq; - -static struct timespec g_goal_time_ts; -static uint64_t g_last_stop_time; -static uint64_t g_start_tsc; -static uint32_t g_timer_active; - -static irqstate_t g_tmr_sync_count; -static irqstate_t g_tmr_flags; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -void up_mask_tmr(void) -{ - /* Disable TSC Deadline interrupt */ - -#ifdef CONFIG_ARCH_INTEL64_HAVE_TSC_DEADLINE - write_msr(MSR_X2APIC_LVTT, TMR_IRQ | MSR_X2APIC_LVTT_TSC_DEADLINE | - (1 << 16)); -#else - write_msr(MSR_X2APIC_LVTT, TMR_IRQ | (1 << 16)); -#endif - - /* Required when using TSC deadline mode. */ - - asm volatile("mfence" : : : "memory"); -} - -void up_unmask_tmr(void) -{ - /* Enable TSC Deadline interrupt */ - -#ifdef CONFIG_ARCH_INTEL64_HAVE_TSC_DEADLINE - write_msr(MSR_X2APIC_LVTT, TMR_IRQ | MSR_X2APIC_LVTT_TSC_DEADLINE); -#else - write_msr(MSR_X2APIC_LVTT, TMR_IRQ); -#endif - - /* Required when using TSC deadline mode. */ - - asm volatile("mfence" : : : "memory"); -} - -#ifndef CONFIG_SCHED_TICKLESS_ALARM -void up_timer_expire(void); -#else -void up_alarm_expire(void); -#endif - -void up_timer_initialize(void) -{ - g_last_stop_time = g_start_tsc = rdtsc(); - -#ifndef CONFIG_SCHED_TICKLESS_ALARM - irq_attach(TMR_IRQ, (xcpt_t)up_timer_expire, NULL); -#else - irq_attach(TMR_IRQ, (xcpt_t)up_alarm_expire, NULL); -#endif -} - -static inline uint64_t up_ts2tick(const struct timespec *ts) -{ - return ROUND_INT_DIV((uint64_t)ts->tv_nsec * x86_64_timer_freq, - NS_PER_SEC) + - (uint64_t)ts->tv_sec * x86_64_timer_freq; -} - -static inline void up_tick2ts(uint64_t tick, struct timespec *ts) -{ - ts->tv_sec = (tick / x86_64_timer_freq); - ts->tv_nsec = (uint64_t)(ROUND_INT_DIV((tick % x86_64_timer_freq) * - NSEC_PER_SEC, x86_64_timer_freq)); -} - -static inline void up_tmr_sync_up(void) -{ - if (!g_tmr_sync_count) - { - g_tmr_flags = enter_critical_section(); - } - - g_tmr_sync_count++; -} - -static inline void up_tmr_sync_down(void) -{ - if (g_tmr_sync_count == 1) - { - leave_critical_section(g_tmr_flags); - } - - if (g_tmr_sync_count > 0) - { - g_tmr_sync_count--; - } -} - -/**************************************************************************** - * Name: up_timer_gettime - * - * Description: - * Return the elapsed time since power-up (or, more correctly, since - * sim_timer_initialize() was called). This function is functionally - * equivalent to: - * - * int clock_gettime(clockid_t clockid, struct timespec *ts); - * - * when clockid is CLOCK_MONOTONIC. - * - * This function provides the basis for reporting the current time and - * also is used to eliminate error build-up from small erros in interval - * time calculations. - * - * Provided by platform-specific code and called from the RTOS base code. - * - * Input Parameters: - * ts - Provides the location in which to return the up-time. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure. - * - * Assumptions: - * Called from the normal tasking context. The implementation must - * provide whatever mutual exclusion is necessary for correct operation. - * This can include disabling interrupts in order to assure atomic register - * operations. - * - ****************************************************************************/ - -int up_timer_gettime(struct timespec *ts) -{ - uint64_t diff = (rdtsc() - g_start_tsc); - up_tick2ts(diff, ts); - return OK; -} - -#ifndef CONFIG_SCHED_TICKLESS_ALARM - -/**************************************************************************** - * Name: up_timer_cancel - * - * Description: - * Cancel the interval timer and return the time remaining on the timer. - * These two steps need to be as nearly atomic as possible. - * sched_timer_expiration() will not be called unless the timer is - * restarted with up_timer_start(). - * - * If, as a race condition, the timer has already expired when this - * function is called, then that pending interrupt must be cleared so - * that up_timer_start() and the remaining time of zero should be - * returned. - * - * Provided by platform-specific code and called from the RTOS base code. - * - * Input Parameters: - * ts - Location to return the remaining time. Zero should be returned - * if the timer is not active. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure. - * - * Assumptions: - * May be called from interrupt level handling or from the normal tasking - * level. Interrupts may need to be disabled internally to assure - * non-reentrancy. - * - ****************************************************************************/ - -int up_timer_cancel(struct timespec *ts) -{ - up_tmr_sync_up(); - - up_mask_tmr(); - - if (ts != NULL) - { - if (g_timer_active) - { - up_tick2ts(g_goal_time - rdtsc(), ts); - } - else - { - ts->tv_sec = 0; - ts->tv_nsec = 0; - } - } - - g_timer_active = 0; - - up_tmr_sync_down(); - - return OK; -} - -/**************************************************************************** - * Name: up_timer_start - * - * Description: - * Start the interval timer. sched_timer_expiration() will be - * called at the completion of the timeout (unless up_timer_cancel - * is called to stop the timing. - * - * Provided by platform-specific code and called from the RTOS base code. - * - * Input Parameters: - * ts - Provides the time interval until sched_timer_expiration() is - * called. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure. - * - * Assumptions: - * May be called from interrupt level handling or from the normal tasking - * level. Interrupts may need to be disabled internally to assure - * non-reentrancy. - * - ****************************************************************************/ - -int up_timer_start(const struct timespec *ts) -{ - uint64_t ticks; - - up_tmr_sync_up(); - - ticks = up_ts2tick(ts) + rdtsc(); - - g_timer_active = 1; - - write_msr(MSR_IA32_TSC_DEADLINE, ticks); - - g_goal_time = ticks; - - up_unmask_tmr(); - - up_tmr_sync_down(); - return OK; -} - -/**************************************************************************** - * Name: up_timer_expire - * - * Description: - * Called as the IRQ handler for alarm expiration. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_timer_expire(void) -{ - g_timer_active = 0; - - up_mask_tmr(); - sched_timer_expiration(); -} - -#else /* CONFIG_SCHED_TICKLESS_ALARM */ - -/**************************************************************************** - * Name: up_timer_cancel - * - * Description: - * Cancel the interval timer and return the time remaining on the timer. - * These two steps need to be as nearly atomic as possible. - * sched_timer_expiration() will not be called unless the timer is - * restarted with up_timer_start(). - * - * If, as a race condition, the timer has already expired when this - * function is called, then that pending interrupt must be cleared so - * that up_timer_start() and the remaining time of zero should be - * returned. - * - * Provided by platform-specific code and called from the RTOS base code. - * - * Input Parameters: - * ts - Location to return the remaining time. Zero should be returned - * if the timer is not active. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure. - * - * Assumptions: - * May be called from interrupt level handling or from the normal tasking - * level. Interrupts may need to be disabled internally to assure - * non-reentrancy. - * - ****************************************************************************/ - -int up_alarm_cancel(struct timespec *ts) -{ - up_tmr_sync_up(); - - up_mask_tmr(); - - if (ts != NULL) - { - up_timer_gettime(ts); - } - - g_timer_active = 0; - - up_tmr_sync_down(); - - return OK; -} - -/**************************************************************************** - * Name: up_timer_start - * - * Description: - * Start the interval timer. sched_timer_expiration() will be - * called at the completion of the timeout (unless up_timer_cancel - * is called to stop the timing. - * - * Provided by platform-specific code and called from the RTOS base code. - * - * Input Parameters: - * ts - Provides the time interval until sched_timer_expiration() is - * called. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure. - * - * Assumptions: - * May be called from interrupt level handling or from the normal tasking - * level. Interrupts may need to be disabled internally to assure - * non-reentrancy. - * - ****************************************************************************/ - -int up_alarm_start(const struct timespec *ts) -{ - uint64_t ticks; - - up_tmr_sync_up(); - - up_unmask_tmr(); - - ticks = up_ts2tick(ts) + g_start_tsc; - - write_msr(MSR_IA32_TSC_DEADLINE, ticks); - - g_timer_active = 1; - - g_goal_time_ts.tv_sec = ts->tv_sec; - g_goal_time_ts.tv_nsec = ts->tv_nsec; - - up_tmr_sync_down(); - - tmrinfo("%" PRIdMAX ".%09ld\n", (uintmax_t)ts->tv_sec, ts->tv_nsec); - tmrinfo("start\n"); - - return OK; -} - -/**************************************************************************** - * Name: up_timer_update - * - * Description: - * Called as the IRQ handler for alarm expiration. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void up_alarm_expire(void) -{ - struct timespec now; - - up_mask_tmr(); - tmrinfo("expire\n"); - - g_timer_active = 0; - - up_timer_gettime(&now); - - nxsched_alarm_expiration(&now); -} - -#endif /* CONFIG_SCHED_TICKLESS_ALARM */ -#endif /* CONFIG_SCHED_TICKLESS */ diff --git a/arch/x86_64/src/intel64/intel64_timerisr.c b/arch/x86_64/src/intel64/intel64_timerisr.c deleted file mode 100644 index 2cf7dab15db8a..0000000000000 --- a/arch/x86_64/src/intel64/intel64_timerisr.c +++ /dev/null @@ -1,132 +0,0 @@ -/**************************************************************************** - * arch/x86_64/src/intel64/intel64_timerisr.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include -#include -#include - -#include "clock/clock.h" -#include "x86_64_internal.h" - -#include - -#include "chip.h" -#include "intel64.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define NS_PER_USEC 1000UL -#define NS_PER_MSEC 1000000UL -#define NS_PER_SEC 1000000000UL - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -unsigned long x86_64_timer_freq; - -static unsigned long tsc_overflow; -static unsigned long tsc_last; -static unsigned long tsc_overflows; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: apic_timer_set - * - * Description: - * Set a time for APIC timer to fire - * - ****************************************************************************/ - -void apic_timer_set(unsigned long timeout_ns) -{ - unsigned long long ticks = - (unsigned long long)timeout_ns * x86_64_timer_freq / NS_PER_SEC; -#ifdef CONFIG_ARCH_INTEL64_HAVE_TSC_DEADLINE - write_msr(MSR_IA32_TSC_DEADLINE, rdtsc() + ticks); -#else - write_msr(MSR_X2APIC_TMICT, ticks); -#endif -} - -/**************************************************************************** - * Function: intel64_timerisr - * - * Description: - * The timer ISR will perform a variety of services for various portions - * of the systems. - * - ****************************************************************************/ - -static int intel64_timerisr(int irq, uint32_t *regs, void *arg) -{ - /* Process timer interrupt */ - - nxsched_process_timer(); - apic_timer_set(CONFIG_USEC_PER_TICK * NS_PER_USEC); - return 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Function: up_timer_initialize - * - * Description: - * This function is called during start-up to initialize - * the timer interrupt. - * - ****************************************************************************/ - -void up_timer_initialize(void) -{ - unsigned long ecx; - uint32_t vector = IRQ0; - - irq_attach(IRQ0, (xcpt_t)intel64_timerisr, NULL); - -#ifdef CONFIG_ARCH_INTEL64_HAVE_TSC_DEADLINE - vector |= MSR_X2APIC_LVTT_TSC_DEADLINE; -#endif - - write_msr(MSR_X2APIC_LVTT, vector); - - asm volatile("mfence" : : : "memory"); - - apic_timer_set(NS_PER_MSEC); -} diff --git a/arch/x86_64/src/intel64/intel64_tsc_tickless.c b/arch/x86_64/src/intel64/intel64_tsc_tickless.c new file mode 100644 index 0000000000000..13c643d1873db --- /dev/null +++ b/arch/x86_64/src/intel64/intel64_tsc_tickless.c @@ -0,0 +1,472 @@ +/**************************************************************************** + * arch/x86_64/src/intel64/intel64_tsc_tickless.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Tickless OS Support. + * + * When CONFIG_SCHED_TICKLESS is enabled, all support for timer interrupts + * is suppressed and the platform specific code is expected to provide the + * following custom functions. + * + * void sim_timer_initialize(void): Initializes the timer facilities. + * Called early in the initialization sequence (by up_initialize()). + * int up_timer_gettime(struct timespec *ts): Returns the current + * time from the platform specific time source. + * int up_timer_cancel(void): Cancels the interval timer. + * int up_timer_start(const struct timespec *ts): Start (or re-starts) + * the interval timer. + * + * The RTOS will provide the following interfaces for use by the platform- + * specific interval timer implementation: + * + * void sched_timer_expiration(void): Called by the platform-specific + * logic when the interval timer expires. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#ifdef CONFIG_SCHED_TICKLESS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NS_PER_USEC 1000UL +#define NS_PER_MSEC 1000000UL +#define NS_PER_SEC 1000000000UL + +#define TMR_IRQ IRQ14 + +#define ROUND_INT_DIV(s, d) (s + (d >> 1)) / d + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +unsigned long g_x86_64_timer_freq; + +static struct timespec g_goal_time_ts; +static uint64_t g_last_stop_time; +static uint64_t g_start_tsc; +static uint32_t g_timer_active; + +static irqstate_t g_tmr_sync_count; +static irqstate_t g_tmr_flags; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +void up_mask_tmr(void) +{ + /* Disable TSC Deadline interrupt */ + +#ifdef CONFIG_ARCH_INTEL64_TSC_DEADLINE + write_msr(MSR_X2APIC_LVTT, TMR_IRQ | MSR_X2APIC_LVTT_TSC_DEADLINE | + (1 << 16)); +#else + write_msr(MSR_X2APIC_LVTT, TMR_IRQ | (1 << 16)); +#endif + + /* Required when using TSC deadline mode. */ + + asm volatile("mfence" : : : "memory"); +} + +void up_unmask_tmr(void) +{ + /* Enable TSC Deadline interrupt */ + +#ifdef CONFIG_ARCH_INTEL64_TSC_DEADLINE + write_msr(MSR_X2APIC_LVTT, TMR_IRQ | MSR_X2APIC_LVTT_TSC_DEADLINE); +#else + write_msr(MSR_X2APIC_LVTT, TMR_IRQ); +#endif + + /* Required when using TSC deadline mode. */ + + asm volatile("mfence" : : : "memory"); +} + +#ifndef CONFIG_SCHED_TICKLESS_ALARM +void up_timer_expire(void); +#else +void up_alarm_expire(void); +#endif + +void up_timer_initialize(void) +{ + g_last_stop_time = g_start_tsc = rdtsc(); + +#ifndef CONFIG_SCHED_TICKLESS_ALARM + irq_attach(TMR_IRQ, (xcpt_t)up_timer_expire, NULL); +#else + irq_attach(TMR_IRQ, (xcpt_t)up_alarm_expire, NULL); +#endif +} + +static inline uint64_t up_ts2tick(const struct timespec *ts) +{ + return ROUND_INT_DIV((uint64_t)ts->tv_nsec * g_x86_64_timer_freq, + NS_PER_SEC) + + (uint64_t)ts->tv_sec * g_x86_64_timer_freq; +} + +static inline void up_tick2ts(uint64_t tick, struct timespec *ts) +{ + ts->tv_sec = (tick / g_x86_64_timer_freq); + ts->tv_nsec = (uint64_t)(ROUND_INT_DIV((tick % g_x86_64_timer_freq) * + NSEC_PER_SEC, g_x86_64_timer_freq)); +} + +static inline void up_tmr_sync_up(void) +{ + if (!g_tmr_sync_count) + { + g_tmr_flags = enter_critical_section(); + } + + g_tmr_sync_count++; +} + +static inline void up_tmr_sync_down(void) +{ + if (g_tmr_sync_count == 1) + { + leave_critical_section(g_tmr_flags); + } + + if (g_tmr_sync_count > 0) + { + g_tmr_sync_count--; + } +} + +/**************************************************************************** + * Name: up_timer_gettime + * + * Description: + * Return the elapsed time since power-up (or, more correctly, since + * sim_timer_initialize() was called). This function is functionally + * equivalent to: + * + * int clock_gettime(clockid_t clockid, struct timespec *ts); + * + * when clockid is CLOCK_MONOTONIC. + * + * This function provides the basis for reporting the current time and + * also is used to eliminate error build-up from small erros in interval + * time calculations. + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Provides the location in which to return the up-time. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * Called from the normal tasking context. The implementation must + * provide whatever mutual exclusion is necessary for correct operation. + * This can include disabling interrupts in order to assure atomic register + * operations. + * + ****************************************************************************/ + +int up_timer_gettime(struct timespec *ts) +{ + uint64_t diff = (rdtsc() - g_start_tsc); + up_tick2ts(diff, ts); + return OK; +} + +#ifndef CONFIG_SCHED_TICKLESS_ALARM + +/**************************************************************************** + * Name: up_timer_cancel + * + * Description: + * Cancel the interval timer and return the time remaining on the timer. + * These two steps need to be as nearly atomic as possible. + * sched_timer_expiration() will not be called unless the timer is + * restarted with up_timer_start(). + * + * If, as a race condition, the timer has already expired when this + * function is called, then that pending interrupt must be cleared so + * that up_timer_start() and the remaining time of zero should be + * returned. + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Location to return the remaining time. Zero should be returned + * if the timer is not active. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * May be called from interrupt level handling or from the normal tasking + * level. Interrupts may need to be disabled internally to assure + * non-reentrancy. + * + ****************************************************************************/ + +int up_timer_cancel(struct timespec *ts) +{ + up_tmr_sync_up(); + + up_mask_tmr(); + + if (ts != NULL) + { + if (g_timer_active) + { + up_tick2ts(g_goal_time - rdtsc(), ts); + } + else + { + ts->tv_sec = 0; + ts->tv_nsec = 0; + } + } + + g_timer_active = 0; + + up_tmr_sync_down(); + + return OK; +} + +/**************************************************************************** + * Name: up_timer_start + * + * Description: + * Start the interval timer. sched_timer_expiration() will be + * called at the completion of the timeout (unless up_timer_cancel + * is called to stop the timing. + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Provides the time interval until sched_timer_expiration() is + * called. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * May be called from interrupt level handling or from the normal tasking + * level. Interrupts may need to be disabled internally to assure + * non-reentrancy. + * + ****************************************************************************/ + +int up_timer_start(const struct timespec *ts) +{ + uint64_t ticks; + + up_tmr_sync_up(); + + ticks = up_ts2tick(ts) + rdtsc(); + + g_timer_active = 1; + + write_msr(MSR_IA32_TSC_DEADLINE, ticks); + + g_goal_time = ticks; + + up_unmask_tmr(); + + up_tmr_sync_down(); + return OK; +} + +/**************************************************************************** + * Name: up_timer_expire + * + * Description: + * Called as the IRQ handler for alarm expiration. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_timer_expire(void) +{ + g_timer_active = 0; + + up_mask_tmr(); + sched_timer_expiration(); +} + +#else /* CONFIG_SCHED_TICKLESS_ALARM */ + +/**************************************************************************** + * Name: up_timer_cancel + * + * Description: + * Cancel the interval timer and return the time remaining on the timer. + * These two steps need to be as nearly atomic as possible. + * sched_timer_expiration() will not be called unless the timer is + * restarted with up_timer_start(). + * + * If, as a race condition, the timer has already expired when this + * function is called, then that pending interrupt must be cleared so + * that up_timer_start() and the remaining time of zero should be + * returned. + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Location to return the remaining time. Zero should be returned + * if the timer is not active. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * May be called from interrupt level handling or from the normal tasking + * level. Interrupts may need to be disabled internally to assure + * non-reentrancy. + * + ****************************************************************************/ + +int up_alarm_cancel(struct timespec *ts) +{ + up_tmr_sync_up(); + + up_mask_tmr(); + + if (ts != NULL) + { + up_timer_gettime(ts); + } + + g_timer_active = 0; + + up_tmr_sync_down(); + + return OK; +} + +/**************************************************************************** + * Name: up_timer_start + * + * Description: + * Start the interval timer. sched_timer_expiration() will be + * called at the completion of the timeout (unless up_timer_cancel + * is called to stop the timing. + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Provides the time interval until sched_timer_expiration() is + * called. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * May be called from interrupt level handling or from the normal tasking + * level. Interrupts may need to be disabled internally to assure + * non-reentrancy. + * + ****************************************************************************/ + +int up_alarm_start(const struct timespec *ts) +{ + uint64_t ticks; + + up_tmr_sync_up(); + + up_unmask_tmr(); + + ticks = up_ts2tick(ts) + g_start_tsc; + + write_msr(MSR_IA32_TSC_DEADLINE, ticks); + + g_timer_active = 1; + + g_goal_time_ts.tv_sec = ts->tv_sec; + g_goal_time_ts.tv_nsec = ts->tv_nsec; + + up_tmr_sync_down(); + + tmrinfo("%" PRIdMAX ".%09ld\n", (uintmax_t)ts->tv_sec, ts->tv_nsec); + tmrinfo("start\n"); + + return OK; +} + +/**************************************************************************** + * Name: up_timer_update + * + * Description: + * Called as the IRQ handler for alarm expiration. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void up_alarm_expire(void) +{ + struct timespec now; + + up_mask_tmr(); + tmrinfo("expire\n"); + + g_timer_active = 0; + + up_timer_gettime(&now); + + nxsched_alarm_expiration(&now); +} + +#endif /* CONFIG_SCHED_TICKLESS_ALARM */ +#endif /* CONFIG_SCHED_TICKLESS */ diff --git a/arch/x86_64/src/intel64/intel64_tsc_timerisr.c b/arch/x86_64/src/intel64/intel64_tsc_timerisr.c new file mode 100644 index 0000000000000..9fe54174ea79a --- /dev/null +++ b/arch/x86_64/src/intel64/intel64_tsc_timerisr.c @@ -0,0 +1,128 @@ +/**************************************************************************** + * arch/x86_64/src/intel64/intel64_tsc_timerisr.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "clock/clock.h" +#include "x86_64_internal.h" + +#include + +#include "chip.h" +#include "intel64.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NS_PER_USEC 1000UL +#define NS_PER_MSEC 1000000UL +#define NS_PER_SEC 1000000000UL + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +unsigned long g_x86_64_timer_freq; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: apic_timer_set + * + * Description: + * Set a time for APIC timer to fire + * + ****************************************************************************/ + +void apic_timer_set(unsigned long timeout_ns) +{ + unsigned long long ticks = + (unsigned long long)timeout_ns * g_x86_64_timer_freq / NS_PER_SEC; + +#ifdef CONFIG_ARCH_INTEL64_TSC_DEADLINE + write_msr(MSR_IA32_TSC_DEADLINE, rdtsc() + ticks); +#else + write_msr(MSR_X2APIC_TMICT, ticks); +#endif +} + +/**************************************************************************** + * Function: intel64_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +static int intel64_timerisr(int irq, uint32_t *regs, void *arg) +{ + /* Process timer interrupt */ + + nxsched_process_timer(); + apic_timer_set(CONFIG_USEC_PER_TICK * NS_PER_USEC); + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + uint32_t vector = IRQ0; + + irq_attach(IRQ0, (xcpt_t)intel64_timerisr, NULL); + +#ifdef CONFIG_ARCH_INTEL64_TSC_DEADLINE + vector |= MSR_X2APIC_LVTT_TSC_DEADLINE; +#endif + + write_msr(MSR_X2APIC_LVTT, vector); + + asm volatile("mfence" : : : "memory"); + + apic_timer_set(NS_PER_MSEC); +} diff --git a/arch/x86_64/src/intel64/intel64_usestack.c b/arch/x86_64/src/intel64/intel64_usestack.c index d05d89d1fd6e2..386d7c77cdba5 100644 --- a/arch/x86_64/src/intel64/intel64_usestack.c +++ b/arch/x86_64/src/intel64/intel64_usestack.c @@ -110,8 +110,9 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size) /* The intel64 stack must be aligned at word (16 byte) boundaries. If * necessary top_of_stack must be rounded down to the next boundary. - * We intentionally align at 8 byte boundary, because at task_start, only - * frame pointer will be pushed, not instruction pointer. + * We intentionally align at 8 byte boundary (look at up_stack_frame()), + * because at task_start, only frame pointer will be pushed, not + * instruction pointer. */ top_of_stack &= ~0x0f; diff --git a/arch/x86_64/src/intel64/intel64_vectors.S b/arch/x86_64/src/intel64/intel64_vectors.S index efcf6dd783450..7abaa88bfe731 100644 --- a/arch/x86_64/src/intel64/intel64_vectors.S +++ b/arch/x86_64/src/intel64/intel64_vectors.S @@ -25,200 +25,668 @@ #include #include - .file "broadwell_vectors.S" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ + .file "intel64_vectors.S" /**************************************************************************** * .text ****************************************************************************/ .text - .code64 + .code64 /**************************************************************************** * Public Symbols ****************************************************************************/ - .globl irq_handler - .globl isr_handler - .globl g_interrupt_stack - .globl g_interrupt_stack_end - .globl g_isr_stack - .globl g_isr_stack_end + .globl irq_handler + .globl isr_handler + .globl g_interrupt_stack + .globl g_interrupt_stack_end + .globl g_isr_stack + .globl g_isr_stack_end /**************************************************************************** * Macros ****************************************************************************/ -/* Trace macros, use like trace 'i' to print char to serial port. */ - - .macro trace, ch - mov $0x3f8, %dx - mov $\ch, %al - out %al, %dx - .endm - -/* This macro creates a stub for an ISR which does NOT pass it's own - * error code (adds a dummy errcode byte). - */ + /* This macro creates a stub for an ISR which does NOT pass it's own + * error code (adds a dummy errcode byte). + */ .macro ISR_NOERRCODE, intno - .globl vector_isr\intno + .globl vector_isr\intno vector_isr\intno: - cli /* Disable interrupts firstly. */ + cli /* Disable interrupts firstly. */ - // CPU has sawitched to the ISR stack using IST + /* CPU has sawitched to the ISR stack using IST */ - pushq $0 /* Push a dummy error code. */ + pushq $0 /* Push a dummy error code. */ - // Save rdi, rsi - pushq %rdi - pushq %rsi - movq $\intno, %rsi /* INT Number is saved to 2nd parameter of function call */ - jmp isr_common /* Go to the common ISR handler code. */ + /* Save rdi, rsi */ + pushq %rdi + pushq %rsi + movq $\intno, %rsi /* INT Number is saved to 2nd parameter of function call */ + jmp isr_common /* Go to the common ISR handler code. */ .endm -/* This macro creates a stub for an ISR which passes it's own - * error code. - */ + /* This macro creates a stub for an ISR which passes it's own + * error code. + */ - .macro ISR_ERRCODE, intno - .globl vector_isr\intno + .macro ISR_ERRCODE, intno + .globl vector_isr\intno vector_isr\intno: - cli /* Disable interrupts firstly. */ + cli /* Disable interrupts firstly. */ - // CPU has sawitched to the ISR stack using IST + /* CPU has sawitched to the ISR stack using IST */ - // Save rdi, rsi - pushq %rdi - pushq %rsi - movq $\intno, %rsi /* INT Number is saved to 2nd parameter of function call */ - jmp isr_common /* Go to the common ISR handler code. */ + /* Save rdi, rsi */ + pushq %rdi + pushq %rsi + movq $\intno, %rsi /* INT Number is saved to 2nd parameter of function call */ + jmp isr_common /* Go to the common ISR handler code. */ .endm -/* This macro creates a stub for an IRQ - the first parameter is - * the IRQ number, the second is the ISR number it is remapped to. - */ + /* This macro creates a stub for an IRQ - the first parameter is + * the IRQ number, the second is the ISR number it is remapped to. + */ - .macro IRQ, irqno, intno - .globl vector_irq\irqno -vector_irq\irqno: - cli /* Disable interrupts firstly. */ + .macro IRQ, irqno, intno + .globl vector_irq\irqno + vector_irq\irqno: + cli /* Disable interrupts firstly. */ - // CPU has switched to the IRQ stack using IST + /* CPU has switched to the IRQ stack using IST */ - pushq $0 /* Push a dummy error code. */ + pushq $0 /* Push a dummy error code. */ - // Save rdi, rsi - pushq %rdi - pushq %rsi - movq $\intno, %rsi /* INT Number is saved to 2nd parameter of function call */ - jmp irq_common /* Go to the common IRQ handler code. */ + /* Save rdi, rsi */ + pushq %rdi + pushq %rsi + movq $\intno, %rsi /* INT Number is saved to 2nd parameter of function call */ + jmp irq_common /* Go to the common IRQ handler code. */ .endm /**************************************************************************** * IDT Vectors ****************************************************************************/ -/* The following will be the vector addresses programmed into the IDT */ + /* The following will be the vector addresses programmed into the IDT */ - ISR_NOERRCODE ISR0 + ISR_NOERRCODE ISR0 + .balign 16 + ISR_NOERRCODE ISR1 + .balign 16 + ISR_NOERRCODE ISR2 + .balign 16 + ISR_NOERRCODE ISR3 + .balign 16 + ISR_NOERRCODE ISR4 + .balign 16 + ISR_NOERRCODE ISR5 + .balign 16 + ISR_NOERRCODE ISR6 + .balign 16 + ISR_NOERRCODE ISR7 + .balign 16 + ISR_ERRCODE ISR8 + .balign 16 + ISR_NOERRCODE ISR9 + .balign 16 + ISR_ERRCODE ISR10 + .balign 16 + ISR_ERRCODE ISR11 + .balign 16 + ISR_ERRCODE ISR12 + .balign 16 + ISR_ERRCODE ISR13 + .balign 16 + ISR_ERRCODE ISR14 + .balign 16 + ISR_NOERRCODE ISR15 + .balign 16 + ISR_NOERRCODE ISR16 + .balign 16 + ISR_NOERRCODE ISR17 + .balign 16 + ISR_NOERRCODE ISR18 + .balign 16 + ISR_NOERRCODE ISR19 + .balign 16 + ISR_NOERRCODE ISR20 + .balign 16 + ISR_NOERRCODE ISR21 + .balign 16 + ISR_NOERRCODE ISR22 + .balign 16 + ISR_NOERRCODE ISR23 + .balign 16 + ISR_NOERRCODE ISR24 + .balign 16 + ISR_NOERRCODE ISR25 + .balign 16 + ISR_NOERRCODE ISR26 + .balign 16 + ISR_NOERRCODE ISR27 + .balign 16 + ISR_NOERRCODE ISR28 + .balign 16 + ISR_NOERRCODE ISR29 + .balign 16 + ISR_NOERRCODE ISR30 + .balign 16 + ISR_NOERRCODE ISR31 + .balign 16 + IRQ 0, IRQ0 + .balign 16 + IRQ 1, IRQ1 + .balign 16 + IRQ 2, IRQ2 + .balign 16 + IRQ 3, IRQ3 + .balign 16 + IRQ 4, IRQ4 + .balign 16 + IRQ 5, IRQ5 + .balign 16 + IRQ 6, IRQ6 + .balign 16 + IRQ 7, IRQ7 + .balign 16 + IRQ 8, IRQ8 + .balign 16 + IRQ 9, IRQ9 + .balign 16 + IRQ 10, IRQ10 + .balign 16 + IRQ 11, IRQ11 + .balign 16 + IRQ 12, IRQ12 + .balign 16 + IRQ 13, IRQ13 + .balign 16 + IRQ 14, IRQ14 + .balign 16 + IRQ 15, IRQ15 + .balign 16 + IRQ 16, IRQ16 + .balign 16 + IRQ 17, IRQ17 + .balign 16 + IRQ 18, IRQ18 + .balign 16 + IRQ 19, IRQ19 + .balign 16 + IRQ 20, IRQ20 + .balign 16 + IRQ 21, IRQ21 + .balign 16 + IRQ 22, IRQ22 + .balign 16 + IRQ 23, IRQ23 + .balign 16 + IRQ 24, IRQ24 + .balign 16 + IRQ 25, IRQ25 + .balign 16 + IRQ 26, IRQ26 + .balign 16 + IRQ 27, IRQ27 + .balign 16 + IRQ 28, IRQ28 + .balign 16 + IRQ 29, IRQ29 + .balign 16 + IRQ 30, IRQ30 + .balign 16 + IRQ 31, IRQ31 + .balign 16 + IRQ 32, IRQ32 + .balign 16 + IRQ 33, IRQ33 + .balign 16 + IRQ 34, IRQ34 + .balign 16 + IRQ 35, IRQ35 + .balign 16 + IRQ 36, IRQ36 + .balign 16 + IRQ 37, IRQ37 + .balign 16 + IRQ 38, IRQ38 + .balign 16 + IRQ 39, IRQ39 + .balign 16 + IRQ 40, IRQ40 + .balign 16 + IRQ 41, IRQ41 + .balign 16 + IRQ 42, IRQ42 + .balign 16 + IRQ 43, IRQ43 + .balign 16 + IRQ 44, IRQ44 + .balign 16 + IRQ 45, IRQ45 + .balign 16 + IRQ 46, IRQ46 + .balign 16 + IRQ 47, IRQ47 + .balign 16 + IRQ 48, IRQ48 + .balign 16 + IRQ 49, IRQ49 + .balign 16 + IRQ 50, IRQ50 + .balign 16 + IRQ 51, IRQ51 + .balign 16 + IRQ 52, IRQ52 + .balign 16 + IRQ 53, IRQ53 + .balign 16 + IRQ 54, IRQ54 + .balign 16 + IRQ 55, IRQ55 + .balign 16 + IRQ 56, IRQ56 + .balign 16 + IRQ 57, IRQ57 + .balign 16 + IRQ 58, IRQ58 + .balign 16 + IRQ 59, IRQ59 + .balign 16 + IRQ 60, IRQ60 + .balign 16 + IRQ 61, IRQ61 + .balign 16 + IRQ 62, IRQ62 + .balign 16 + IRQ 63, IRQ63 + .balign 16 + IRQ 64, IRQ64 + .balign 16 + IRQ 65, IRQ65 + .balign 16 + IRQ 66, IRQ66 + .balign 16 + IRQ 67, IRQ67 + .balign 16 + IRQ 68, IRQ68 + .balign 16 + IRQ 69, IRQ69 + .balign 16 + IRQ 70, IRQ70 + .balign 16 + IRQ 71, IRQ71 + .balign 16 + IRQ 72, IRQ72 + .balign 16 + IRQ 73, IRQ73 + .balign 16 + IRQ 74, IRQ74 + .balign 16 + IRQ 75, IRQ75 + .balign 16 + IRQ 76, IRQ76 + .balign 16 + IRQ 77, IRQ77 + .balign 16 + IRQ 78, IRQ78 + .balign 16 + IRQ 79, IRQ79 + .balign 16 + IRQ 80, IRQ80 + .balign 16 + IRQ 81, IRQ81 + .balign 16 + IRQ 82, IRQ82 + .balign 16 + IRQ 83, IRQ83 + .balign 16 + IRQ 84, IRQ84 .balign 16 - ISR_NOERRCODE ISR1 + IRQ 85, IRQ85 .balign 16 - ISR_NOERRCODE ISR2 + IRQ 86, IRQ86 .balign 16 - ISR_NOERRCODE ISR3 + IRQ 87, IRQ87 .balign 16 - ISR_NOERRCODE ISR4 + IRQ 88, IRQ88 .balign 16 - ISR_NOERRCODE ISR5 + IRQ 89, IRQ89 .balign 16 - ISR_NOERRCODE ISR6 + IRQ 90, IRQ90 .balign 16 - ISR_NOERRCODE ISR7 + IRQ 91, IRQ91 .balign 16 - ISR_ERRCODE ISR8 + IRQ 92, IRQ92 .balign 16 - ISR_NOERRCODE ISR9 + IRQ 93, IRQ93 .balign 16 - ISR_ERRCODE ISR10 + IRQ 94, IRQ94 .balign 16 - ISR_ERRCODE ISR11 + IRQ 95, IRQ95 .balign 16 - ISR_ERRCODE ISR12 + IRQ 96, IRQ96 .balign 16 - ISR_ERRCODE ISR13 + IRQ 97, IRQ97 .balign 16 - ISR_ERRCODE ISR14 + IRQ 98, IRQ98 .balign 16 - ISR_NOERRCODE ISR15 + IRQ 99, IRQ99 .balign 16 - ISR_NOERRCODE ISR16 + IRQ 100, IRQ100 .balign 16 - ISR_NOERRCODE ISR17 + IRQ 101, IRQ101 .balign 16 - ISR_NOERRCODE ISR18 + IRQ 102, IRQ102 .balign 16 - ISR_NOERRCODE ISR19 + IRQ 103, IRQ103 .balign 16 - ISR_NOERRCODE ISR20 + IRQ 104, IRQ104 .balign 16 - ISR_NOERRCODE ISR21 + IRQ 105, IRQ105 .balign 16 - ISR_NOERRCODE ISR22 + IRQ 106, IRQ106 .balign 16 - ISR_NOERRCODE ISR23 + IRQ 107, IRQ107 .balign 16 - ISR_NOERRCODE ISR24 + IRQ 108, IRQ108 .balign 16 - ISR_NOERRCODE ISR25 + IRQ 109, IRQ109 .balign 16 - ISR_NOERRCODE ISR26 + IRQ 110, IRQ110 .balign 16 - ISR_NOERRCODE ISR27 + IRQ 111, IRQ111 .balign 16 - ISR_NOERRCODE ISR28 + IRQ 112, IRQ112 .balign 16 - ISR_NOERRCODE ISR29 + IRQ 113, IRQ113 .balign 16 - ISR_NOERRCODE ISR30 + IRQ 114, IRQ114 .balign 16 - ISR_NOERRCODE ISR31 + IRQ 115, IRQ115 .balign 16 - IRQ 0, IRQ0 + IRQ 116, IRQ116 .balign 16 - IRQ 1, IRQ1 + IRQ 117, IRQ117 .balign 16 - IRQ 2, IRQ2 + IRQ 118, IRQ118 .balign 16 - IRQ 3, IRQ3 + IRQ 119, IRQ119 .balign 16 - IRQ 4, IRQ4 + IRQ 120, IRQ120 .balign 16 - IRQ 5, IRQ5 + IRQ 121, IRQ121 .balign 16 - IRQ 6, IRQ6 + IRQ 122, IRQ122 .balign 16 - IRQ 7, IRQ7 + IRQ 123, IRQ123 .balign 16 - IRQ 8, IRQ8 + IRQ 124, IRQ124 .balign 16 - IRQ 9, IRQ9 + IRQ 125, IRQ125 .balign 16 - IRQ 10, IRQ10 + IRQ 126, IRQ126 .balign 16 - IRQ 11, IRQ11 + IRQ 127, IRQ127 .balign 16 - IRQ 12, IRQ12 + IRQ 128, IRQ128 .balign 16 - IRQ 13, IRQ13 + IRQ 129, IRQ129 .balign 16 - IRQ 14, IRQ14 + IRQ 130, IRQ130 .balign 16 - IRQ 15, IRQ15 + IRQ 131, IRQ131 + .balign 16 + IRQ 132, IRQ132 + .balign 16 + IRQ 133, IRQ133 + .balign 16 + IRQ 134, IRQ134 + .balign 16 + IRQ 135, IRQ135 + .balign 16 + IRQ 136, IRQ136 + .balign 16 + IRQ 137, IRQ137 + .balign 16 + IRQ 138, IRQ138 + .balign 16 + IRQ 139, IRQ139 + .balign 16 + IRQ 140, IRQ140 + .balign 16 + IRQ 141, IRQ141 + .balign 16 + IRQ 142, IRQ142 + .balign 16 + IRQ 143, IRQ143 + .balign 16 + IRQ 144, IRQ144 + .balign 16 + IRQ 145, IRQ145 + .balign 16 + IRQ 146, IRQ146 + .balign 16 + IRQ 147, IRQ147 + .balign 16 + IRQ 148, IRQ148 + .balign 16 + IRQ 149, IRQ149 + .balign 16 + IRQ 150, IRQ150 + .balign 16 + IRQ 151, IRQ151 + .balign 16 + IRQ 152, IRQ152 + .balign 16 + IRQ 153, IRQ153 + .balign 16 + IRQ 154, IRQ154 + .balign 16 + IRQ 155, IRQ155 + .balign 16 + IRQ 156, IRQ156 + .balign 16 + IRQ 157, IRQ157 + .balign 16 + IRQ 158, IRQ158 + .balign 16 + IRQ 159, IRQ159 + .balign 16 + IRQ 160, IRQ160 + .balign 16 + IRQ 161, IRQ161 + .balign 16 + IRQ 162, IRQ162 + .balign 16 + IRQ 163, IRQ163 + .balign 16 + IRQ 164, IRQ164 + .balign 16 + IRQ 165, IRQ165 + .balign 16 + IRQ 166, IRQ166 + .balign 16 + IRQ 167, IRQ167 + .balign 16 + IRQ 168, IRQ168 + .balign 16 + IRQ 169, IRQ169 + .balign 16 + IRQ 170, IRQ170 + .balign 16 + IRQ 171, IRQ171 + .balign 16 + IRQ 172, IRQ172 + .balign 16 + IRQ 173, IRQ173 + .balign 16 + IRQ 174, IRQ174 + .balign 16 + IRQ 175, IRQ175 + .balign 16 + IRQ 176, IRQ176 + .balign 16 + IRQ 177, IRQ177 + .balign 16 + IRQ 178, IRQ178 + .balign 16 + IRQ 179, IRQ179 + .balign 16 + IRQ 180, IRQ180 + .balign 16 + IRQ 181, IRQ181 + .balign 16 + IRQ 182, IRQ182 + .balign 16 + IRQ 183, IRQ183 + .balign 16 + IRQ 184, IRQ184 + .balign 16 + IRQ 185, IRQ185 + .balign 16 + IRQ 186, IRQ186 + .balign 16 + IRQ 187, IRQ187 + .balign 16 + IRQ 188, IRQ188 + .balign 16 + IRQ 189, IRQ189 + .balign 16 + IRQ 190, IRQ190 + .balign 16 + IRQ 191, IRQ191 + .balign 16 + IRQ 192, IRQ192 + .balign 16 + IRQ 193, IRQ193 + .balign 16 + IRQ 194, IRQ194 + .balign 16 + IRQ 195, IRQ195 + .balign 16 + IRQ 196, IRQ196 + .balign 16 + IRQ 197, IRQ197 + .balign 16 + IRQ 198, IRQ198 + .balign 16 + IRQ 199, IRQ199 + .balign 16 + IRQ 200, IRQ200 + .balign 16 + IRQ 201, IRQ201 + .balign 16 + IRQ 202, IRQ202 + .balign 16 + IRQ 203, IRQ203 + .balign 16 + IRQ 204, IRQ204 + .balign 16 + IRQ 205, IRQ205 + .balign 16 + IRQ 206, IRQ206 + .balign 16 + IRQ 207, IRQ207 + .balign 16 + IRQ 208, IRQ208 + .balign 16 + IRQ 209, IRQ209 + .balign 16 + IRQ 210, IRQ210 + .balign 16 + IRQ 211, IRQ211 + .balign 16 + IRQ 212, IRQ212 + .balign 16 + IRQ 213, IRQ213 + .balign 16 + IRQ 214, IRQ214 + .balign 16 + IRQ 215, IRQ215 + .balign 16 + IRQ 216, IRQ216 + .balign 16 + IRQ 217, IRQ217 + .balign 16 + IRQ 218, IRQ218 + .balign 16 + IRQ 219, IRQ219 + .balign 16 + IRQ 220, IRQ220 + .balign 16 + IRQ 221, IRQ221 + .balign 16 + IRQ 222, IRQ222 + .balign 16 + IRQ 223, IRQ223 + .balign 16 + IRQ 224, IRQ224 + .balign 16 + IRQ 225, IRQ225 + .balign 16 + IRQ 226, IRQ226 + .balign 16 + IRQ 227, IRQ227 + .balign 16 + IRQ 228, IRQ228 + .balign 16 + IRQ 229, IRQ229 + .balign 16 + IRQ 230, IRQ230 + .balign 16 + IRQ 231, IRQ231 + .balign 16 + IRQ 232, IRQ232 + .balign 16 + IRQ 233, IRQ233 + .balign 16 + IRQ 234, IRQ234 + .balign 16 + IRQ 235, IRQ235 + .balign 16 + IRQ 236, IRQ236 + .balign 16 + IRQ 237, IRQ237 + .balign 16 + IRQ 238, IRQ238 + .balign 16 + IRQ 239, IRQ239 + .balign 16 + IRQ 240, IRQ240 + .balign 16 + IRQ 241, IRQ241 + .balign 16 + IRQ 242, IRQ242 + .balign 16 + IRQ 243, IRQ243 + .balign 16 + IRQ 244, IRQ244 + .balign 16 + IRQ 245, IRQ245 + .balign 16 + IRQ 246, IRQ246 + .balign 16 + IRQ 247, IRQ247 + .balign 16 + IRQ 248, IRQ248 + .balign 16 + IRQ 249, IRQ249 + .balign 16 + IRQ 250, IRQ250 + .balign 16 + IRQ 251, IRQ251 + .balign 16 + IRQ 252, IRQ252 + .balign 16 + IRQ 253, IRQ253 + .balign 16 + IRQ 254, IRQ254 + .balign 16 + IRQ 255, IRQ255 .balign 16 /**************************************************************************** @@ -232,51 +700,50 @@ vector_irq\irqno: ****************************************************************************/ isr_common: -/* trace 'S' */ - /* Already swap to the interrupt stack */ - /* stack is automatically recovered by iretq using task state */ - - /* x86_64 don't have pusha, we have to do things manually */ - /* RDI and RSI are pushed above for handling IRQ no */ - pushq %rdx - pushq %rcx - pushq %r8 - pushq %r9 - - pushq %r15 - pushq %r14 - pushq %r13 - pushq %r12 - pushq %r11 - pushq %r10 - pushq %rbp - pushq %rbx - pushq %rax - - mov %ds, %ax /* Lower 16-bits of rax. */ - pushq %rax /* Save the data segment descriptor */ - mov %es, %ax /* Lower 16-bits of rax. */ - pushq %rax /* Save the data segment descriptor */ - mov %gs, %ax /* Lower 16-bits of rax. */ - pushq %rax /* Save the data segment descriptor */ - mov %fs, %ax /* Lower 16-bits of rax. */ - pushq %rax /* Save the data segment descriptor */ - - /* align to 16-bytes boundary */ - leaq -8(%rsp), %rsp - - /* save xmm registers */ - leaq -512(%rsp), %rsp - fxsaveq (%rsp) + /* Already swap to the interrupt stack */ + /* stack is automatically recovered by iretq using task state */ + + /* x86_64 don't have pusha, we have to do things manually */ + /* RDI and RSI are pushed above for handling IRQ no */ + pushq %rdx + pushq %rcx + pushq %r8 + pushq %r9 + + pushq %r15 + pushq %r14 + pushq %r13 + pushq %r12 + pushq %r11 + pushq %r10 + pushq %rbp + pushq %rbx + pushq %rax + + mov %ds, %ax /* Lower 16-bits of rax. */ + pushq %rax /* Save the data segment descriptor */ + mov %es, %ax /* Lower 16-bits of rax. */ + pushq %rax /* Save the data segment descriptor */ + mov %gs, %ax /* Lower 16-bits of rax. */ + pushq %rax /* Save the data segment descriptor */ + mov %fs, %ax /* Lower 16-bits of rax. */ + pushq %rax /* Save the data segment descriptor */ + + /* align to 16-bytes boundary */ + leaq -8(%rsp), %rsp + + /* save xmm registers */ + leaq -512(%rsp), %rsp + fxsaveq (%rsp) /* The current value of the SP points to the beginning of the state save * structure. Save that in RDI as the input parameter to isr_handler. */ - mov %rsp, %rdi - call isr_handler - jmp .Lreturn - .size isr_common, . - isr_common + mov %rsp, %rdi + call isr_handler + jmp .Lreturn + .size isr_common, . - isr_common /**************************************************************************** * Name: irq_common @@ -288,51 +755,50 @@ isr_common: * ****************************************************************************/ - .type irq_common, @function + .type irq_common, @function irq_common: -/* trace 'R' */ - /* Already swap to the interrupt stack */ - /* stack is automatically recovered by iretq using task state */ - - /* x86_64 don't have pusha, we have to do things manually */ - /* RDI and RSI are pushed above for handling IRQ no */ - pushq %rdx - pushq %rcx - pushq %r8 - pushq %r9 - - pushq %r15 - pushq %r14 - pushq %r13 - pushq %r12 - pushq %r11 - pushq %r10 - pushq %rbp - pushq %rbx - pushq %rax - - mov %ds, %ax /* Lower 16-bits of rax. */ - pushq %rax /* Save the data segment descriptor */ - mov %es, %ax /* Lower 16-bits of rax. */ - pushq %rax /* Save the data segment descriptor */ - mov %gs, %ax /* Lower 16-bits of rax. */ - pushq %rax /* Save the data segment descriptor */ - mov %fs, %ax /* Lower 16-bits of rax. */ - pushq %rax /* Save the data segment descriptor */ - - /* align to 16-bytes boundary */ - leaq -8(%rsp), %rsp - - /* save xmm registers */ - leaq -512(%rsp), %rsp - fxsaveq (%rsp) + /* Already swap to the interrupt stack */ + /* stack is automatically recovered by iretq using task state */ + + /* x86_64 don't have pusha, we have to do things manually */ + /* RDI and RSI are pushed above for handling IRQ no */ + pushq %rdx + pushq %rcx + pushq %r8 + pushq %r9 + + pushq %r15 + pushq %r14 + pushq %r13 + pushq %r12 + pushq %r11 + pushq %r10 + pushq %rbp + pushq %rbx + pushq %rax + + mov %ds, %ax /* Lower 16-bits of rax. */ + pushq %rax /* Save the data segment descriptor */ + mov %es, %ax /* Lower 16-bits of rax. */ + pushq %rax /* Save the data segment descriptor */ + mov %gs, %ax /* Lower 16-bits of rax. */ + pushq %rax /* Save the data segment descriptor */ + mov %fs, %ax /* Lower 16-bits of rax. */ + pushq %rax /* Save the data segment descriptor */ + + /* align to 16-bytes boundary */ + leaq -8(%rsp), %rsp + + /* save xmm registers */ + leaq -512(%rsp), %rsp + fxsaveq (%rsp) /* The current value of the SP points to the beginning of the state save * structure. Save that in RDI as the input parameter to irq_handler. */ - mov %rsp, %rdi - call irq_handler + mov %rsp, %rdi + call irq_handler /* The common return point for both isr_handler and irq_handler */ @@ -341,55 +807,55 @@ irq_common: * return. Are we switching to a new context? */ - cmp %rax, %rsp - je .Lnoswitch + cmp %rax, %rsp + je .Lnoswitch /* A context swith will be performed. EAX holds the address of the new - * register save structure. + * register save structure. * * Jump to x86_64_fullcontextrestore(). We perform a call here, but that function * never returns. The address of the new register save block is the argument * to the x86_64_fullcontextrestore(). - */ + */ mov %rax, %rdi - call x86_64_fullcontextrestore + call x86_64_fullcontextrestore .Lnoswitch: - fxrstorq (%rsp) - leaq 512(%rsp), %rsp - leaq 8(%rsp), %rsp - - popq %rax - mov %fs, %ax - popq %rax - mov %gs, %ax - popq %rax - mov %es, %ax - popq %rax - mov %ds, %ax - - popq %rax - popq %rbx - popq %rbp - popq %r10 - popq %r11 - popq %r12 - popq %r13 - popq %r14 - popq %r15 - - popq %r9 - popq %r8 - popq %rcx - popq %rdx - - popq %rsi - popq %rdi - - add $8, %rsp /* Cleans up the pushed error code */ - - iretq /* Pops 5 things at once: CS, RIP, RFLAGS and SS and RSP */ + fxrstorq (%rsp) + leaq 512(%rsp), %rsp + leaq 8(%rsp), %rsp + + popq %rax + mov %fs, %ax + popq %rax + mov %gs, %ax + popq %rax + mov %es, %ax + popq %rax + mov %ds, %ax + + popq %rax + popq %rbx + popq %rbp + popq %r10 + popq %r11 + popq %r12 + popq %r13 + popq %r14 + popq %r15 + + popq %r9 + popq %r8 + popq %rcx + popq %rdx + + popq %rsi + popq %rdi + + add $8, %rsp /* Cleans up the pushed error code */ + + iretq /* Pops 5 things at once: CS, RIP, RFLAGS and SS and RSP */ .size irq_common, . - irq_common .end diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 0c7f1f60ab92d..120f766465361 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -78,12 +78,14 @@ config ARCH_CHIP_ESP32S3 bool "Espressif ESP32-S3" select ARCH_FAMILY_LX7 select XTENSA_HAVE_INTERRUPTS - select ARCH_HAVE_BOOTLOADER + select ARCH_HAVE_BOOTLOADER if !ESPRESSIF_SIMPLE_BOOT select ARCH_HAVE_FPU select ARCH_HAVE_MPU select ARCH_HAVE_MULTICPU select ARCH_HAVE_RESET select ARCH_HAVE_TEXT_HEAP + select ARCH_HAVE_TEXT_HEAP_SEPARATE_DATA_ADDRESS + select ARCH_HAVE_TEXT_HEAP_WORD_ALIGNED_READ select ARCH_HAVE_TESTSET select ARCH_VECNOTIRQ select LIBC_PREVENT_STRING_KERNEL diff --git a/arch/xtensa/include/esp32s3/.gitignore b/arch/xtensa/include/esp32s3/.gitignore new file mode 100644 index 0000000000000..9dd4b4aea86e7 --- /dev/null +++ b/arch/xtensa/include/esp32s3/.gitignore @@ -0,0 +1,6 @@ +/soc.h +/reg_base.h +/esp_attr.h +/esp_assert.h +/esp_bit_defs.h +/sdkconfig.h diff --git a/arch/xtensa/include/esp32s3/irq.h b/arch/xtensa/include/esp32s3/irq.h index 25a248f422e13..82acc3e12a831 100644 --- a/arch/xtensa/include/esp32s3/irq.h +++ b/arch/xtensa/include/esp32s3/irq.h @@ -137,17 +137,19 @@ #define ESP32S3_PERIPH_DCACHE_SYNC 63 #define ESP32S3_PERIPH_ICACHE_SYNC 64 #define ESP32S3_PERIPH_APB_ADC 65 + #define ESP32S3_PERIPH_DMA_IN_CH0 66 #define ESP32S3_PERIPH_DMA_IN_CH1 67 #define ESP32S3_PERIPH_DMA_IN_CH2 68 #define ESP32S3_PERIPH_DMA_IN_CH3 69 - #define ESP32S3_PERIPH_DMA_IN_CH4 70 + #define ESP32S3_PERIPH_DMA_OUT_CH0 71 #define ESP32S3_PERIPH_DMA_OUT_CH1 72 #define ESP32S3_PERIPH_DMA_OUT_CH2 73 #define ESP32S3_PERIPH_DMA_OUT_CH3 74 #define ESP32S3_PERIPH_DMA_OUT_CH4 75 + #define ESP32S3_PERIPH_RSA 76 #define ESP32S3_PERIPH_AES 77 #define ESP32S3_PERIPH_SHA 78 diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index ece60779f7f97..f5c71856b6236 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -367,7 +367,7 @@ extern "C" #ifndef __ASSEMBLY__ /* g_current_regs[] holds a references to the current interrupt level - * register storage structure. If is non-NULL only during interrupt + * register storage structure. It is non-NULL only during interrupt * processing. Access to g_current_regs[] must be through the macro * CURRENT_REGS for portability. */ diff --git a/arch/xtensa/src/Makefile b/arch/xtensa/src/Makefile index 2a6f450609c77..ec83edd9b8943 100644 --- a/arch/xtensa/src/Makefile +++ b/arch/xtensa/src/Makefile @@ -18,7 +18,7 @@ # ############################################################################ -include $(TOPDIR)/Make.defs +include $(TOPDIR)/tools/apps-or-nuttx-Make.defs include chip/Make.defs ifeq ($(CONFIG_ARCH_FAMILY_LX6),y) @@ -158,7 +158,7 @@ board/libboard$(LIBEXT): $(Q) $(MAKE) -C board libboard$(LIBEXT) EXTRAFLAGS="$(EXTRAFLAGS)" define LINK_ALLSYMS - $(Q) $(TOPDIR)/tools/mkallsyms.py $(NUTTX) allsyms.tmp + $(Q) $(TOPDIR)/tools/mkallsyms.py $(NUTTX) allsyms.tmp --orderbyname $(CONFIG_SYMTAB_ORDEREDBYNAME) $(Q) $(call COMPILE, allsyms.tmp, allsyms$(OBJEXT), -x c) $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \ -o $(NUTTX) $(STARTUP_OBJS) allsyms$(OBJEXT) $(EXTRA_OBJS) \ diff --git a/arch/xtensa/src/common/espressif/Kconfig b/arch/xtensa/src/common/espressif/Kconfig index 6bc8c13f71a57..c6cfce8c7fff0 100644 --- a/arch/xtensa/src/common/espressif/Kconfig +++ b/arch/xtensa/src/common/espressif/Kconfig @@ -3,5 +3,7 @@ config ESP_RMT default n depends on RMT ---help--- - Remote Control Module is currently used to control WS2812 - RGB LED normally used on LED strips. \ No newline at end of file + The RMT (Remote Control Transceiver) peripheral was designed to act as + an infrared transceiver. However, due to the flexibility of its data + format, RMT can be extended to a versatile and general-purpose + transceiver, transmitting or receiving many other types of signals. diff --git a/arch/xtensa/src/common/espressif/Make.defs b/arch/xtensa/src/common/espressif/Make.defs index 3a48c6b4a7dfd..2034dbeebf84a 100644 --- a/arch/xtensa/src/common/espressif/Make.defs +++ b/arch/xtensa/src/common/espressif/Make.defs @@ -24,3 +24,5 @@ ifeq ($(CONFIG_WS2812_NON_SPI_DRIVER),y) CHIP_CSRCS += esp_ws2812.c endif endif + +INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)common$(DELIM)espressif$(DELIM)platform_include diff --git a/arch/xtensa/src/common/espressif/esp_rmt.c b/arch/xtensa/src/common/espressif/esp_rmt.c index 5d7ac7fef3083..2b15c313c20f1 100644 --- a/arch/xtensa/src/common/espressif/esp_rmt.c +++ b/arch/xtensa/src/common/espressif/esp_rmt.c @@ -174,10 +174,12 @@ enum rmt_channel_e RMT_CHANNEL_1, /* RMT channel number 1 */ RMT_CHANNEL_2, /* RMT channel number 2 */ RMT_CHANNEL_3, /* RMT channel number 3 */ +#if SOC_RMT_CHANNELS_PER_GROUP > 4 RMT_CHANNEL_4, /* RMT channel number 4 */ RMT_CHANNEL_5, /* RMT channel number 5 */ RMT_CHANNEL_6, /* RMT channel number 6 */ RMT_CHANNEL_7, /* RMT channel number 7 */ +#endif RMT_CHANNEL_MAX /* Number of RMT channels */ }; @@ -266,7 +268,7 @@ struct rmt_dev_common_s struct rmt_dev_lowerhalf_s { - /* The following block is part of the upper-hald device struct */ + /* The following block is part of the upper-half device struct */ FAR const struct rmt_ops_s *ops; FAR struct circbuf_s *circbuf; @@ -285,18 +287,18 @@ struct rmt_obj_s size_t tx_len_rem; size_t tx_sub_len; bool wait_done; /* Mark whether wait tx done */ - bool loop_autostop; /* mark whether loop auto-stop is enabled */ + bool loop_autostop; /* Mark whether loop auto-stop is enabled */ rmt_channel_t channel; const rmt_item32_t *tx_data; sem_t tx_sem; -#if CONFIG_SPIRAM_USE_MALLOC +#ifdef CONFIG_SPIRAM_USE_MALLOC int intr_alloc_flags; sem_t tx_sem_buffer; #endif rmt_item32_t *tx_buf; struct circbuf_s rx_buf; sem_t rx_sem; -#if SOC_RMT_SUPPORT_RX_PINGPONG +#ifdef SOC_RMT_SUPPORT_RX_PINGPONG rmt_item32_t *rx_item_buf; uint32_t rx_item_buf_size; uint32_t rx_item_len; @@ -415,9 +417,9 @@ static rmt_channel_t g_rx_channel = RMT_CHANNEL_MAX; #endif #if SOC_RMT_CHANNEL_CLK_INDEPENDENT -static uint32_t s_rmt_source_clock_hz[RMT_CHANNEL_MAX]; +uint32_t g_rmt_source_clock_hz[RMT_CHANNEL_MAX]; #else -static uint32_t s_rmt_source_clock_hz; +uint32_t g_rmt_source_clock_hz; #endif /* RMTMEM address is declared in .peripherals.ld */ @@ -477,7 +479,7 @@ static void rmt_module_enable(void) * ****************************************************************************/ -#if SOC_RMT_SUPPORT_RX_PINGPONG +#ifdef SOC_RMT_SUPPORT_RX_PINGPONG static int rmt_set_rx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_thresh) { @@ -541,7 +543,7 @@ static int rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst) { irqstate_t flags; rmt_channel_t ch = RMT_DECODE_RX_CHANNEL(channel); -#if SOC_RMT_SUPPORT_RX_PINGPONG +#ifdef SOC_RMT_SUPPORT_RX_PINGPONG const uint32_t item_block_len = rmt_ll_rx_get_mem_blocks(g_rmtdev_common.hal.regs, ch) * RMT_MEM_ITEM_NUM; @@ -562,7 +564,7 @@ static int rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst) rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, RMT_LL_EVENT_RX_DONE(ch), true); -#if SOC_RMT_SUPPORT_RX_PINGPONG +#ifdef SOC_RMT_SUPPORT_RX_PINGPONG p_rmt_obj[channel]->rx_item_start_idx = 0; p_rmt_obj[channel]->rx_item_len = 0; rmt_set_rx_thr_intr_en(channel, true, item_block_len / 2); @@ -605,7 +607,7 @@ static int rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst) rmt_ll_clear_interrupt_status(g_rmtdev_common.hal.regs, RMT_LL_EVENT_TX_DONE(channel)); - /* enable tx end interrupt in non-loop mode */ + /* Enable tx end interrupt in non-loop mode */ if (!rmt_ll_tx_is_loop_enabled(g_rmtdev_common.hal.regs, channel)) { @@ -891,16 +893,16 @@ static int rmt_internal_config(rmt_dev_t *dev, spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); #if SOC_RMT_CHANNEL_CLK_INDEPENDENT - s_rmt_source_clock_hz[channel] = rmt_source_clk_hz; + g_rmt_source_clock_hz[channel] = rmt_source_clk_hz; #else - if (s_rmt_source_clock_hz && rmt_source_clk_hz != s_rmt_source_clock_hz) + if (g_rmt_source_clock_hz && rmt_source_clk_hz != g_rmt_source_clock_hz) { rmterr("RMT clock source has been configured to %"PRIu32" by other " "channel, now reconfigure it to %"PRIu32"", - s_rmt_source_clock_hz, rmt_source_clk_hz); + g_rmt_source_clock_hz, rmt_source_clk_hz); } - s_rmt_source_clock_hz = rmt_source_clk_hz; + g_rmt_source_clock_hz = rmt_source_clk_hz; #endif rmtinfo("rmt_source_clk_hz: %"PRIu32, rmt_source_clk_hz); @@ -983,7 +985,7 @@ static int rmt_internal_config(rmt_dev_t *dev, rmt_ll_rx_enable_filter(dev, RMT_DECODE_RX_CHANNEL(channel), rmt_param->rx_config.filter_en); -#if SOC_RMT_SUPPORT_RX_PINGPONG +#ifdef SOC_RMT_SUPPORT_RX_PINGPONG /* always enable rx ping-pong */ @@ -1281,7 +1283,7 @@ static int IRAM_ATTR rmt_driver_isr_default(int irq, void *context, addr = (rmt_item32_t *) RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32; -#if SOC_RMT_SUPPORT_RX_PINGPONG +#ifdef SOC_RMT_SUPPORT_RX_PINGPONG if (item_len > p_rmt->rx_item_start_idx) { item_len = item_len - p_rmt->rx_item_start_idx; @@ -1321,7 +1323,7 @@ static int IRAM_ATTR rmt_driver_isr_default(int irq, void *context, rmterr("RMT RX BUFFER ERROR"); } -#if SOC_RMT_SUPPORT_RX_PINGPONG +#ifdef SOC_RMT_SUPPORT_RX_PINGPONG p_rmt->rx_item_start_idx = 0; p_rmt->rx_item_len = 0; memset((void *)p_rmt->rx_item_buf, 0, p_rmt->rx_item_buf_size); @@ -1336,7 +1338,7 @@ static int IRAM_ATTR rmt_driver_isr_default(int irq, void *context, RMT_LL_EVENT_RX_DONE(channel)); } -#if SOC_RMT_SUPPORT_RX_PINGPONG +#ifdef SOC_RMT_SUPPORT_RX_PINGPONG /* Rx thres interrupt */ @@ -1512,8 +1514,8 @@ static int rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, } #endif -#if !CONFIG_SPIRAM_USE_MALLOC - p_rmt_obj[channel] = calloc(1, sizeof(rmt_obj_t)); +#ifndef CONFIG_SPIRAM_USE_MALLOC + p_rmt_obj[channel] = kmm_calloc(1, sizeof(rmt_obj_t)); #else if (!(intr_alloc_flags & ESP_INTR_FLAG_IRAM)) { @@ -1521,9 +1523,7 @@ static int rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, } else { - p_rmt_obj[channel] = heap_caps_calloc(1, sizeof(rmt_obj_t), - MALLOC_CAP_INTERNAL | \ - MALLOC_CAP_8BIT); + p_rmt_obj[channel] = kmm_calloc(1, sizeof(rmt_obj_t)); } #endif @@ -1541,7 +1541,7 @@ static int rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, p_rmt_obj[channel]->wait_done = false; p_rmt_obj[channel]->loop_autostop = false; -#if !CONFIG_SPIRAM_USE_MALLOC +#ifndef CONFIG_SPIRAM_USE_MALLOC nxsem_init(&p_rmt_obj[channel]->tx_sem, 0, 0); nxsem_init(&p_rmt_obj[channel]->rx_sem, 0, 0); #endif @@ -1553,24 +1553,22 @@ static int rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, circbuf_init(&p_rmt_obj[channel]->rx_buf, NULL, rx_buf_size); } -#if SOC_RMT_SUPPORT_RX_PINGPONG +#ifdef SOC_RMT_SUPPORT_RX_PINGPONG if (p_rmt_obj[channel]->rx_item_buf == NULL && rx_buf_size > 0) { -#if !CONFIG_SPIRAM_USE_MALLOC - p_rmt_obj[channel]->rx_item_buf = calloc(1, rx_buf_size); -#else +# ifndef CONFIG_SPIRAM_USE_MALLOC + p_rmt_obj[channel]->rx_item_buf = kmm_calloc(1, rx_buf_size); +# else if (!(p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM)) { p_rmt_obj[channel]->rx_item_buf = calloc(1, rx_buf_size); } else { - p_rmt_obj[channel]->rx_item_buf = - heap_caps_calloc(1, rx_buf_size, - MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT); + p_rmt_obj[channel]->rx_item_buf = kmm_calloc(1, rx_buf_size); } -#endif +# endif if (p_rmt_obj[channel]->rx_item_buf == NULL) { rmterr("RMT malloc fail"); @@ -1654,12 +1652,12 @@ static int rmt_write_items(rmt_channel_t channel, channel); DEBUGASSERT(mem_blocks + channel <= SOC_RMT_CHANNELS_PER_GROUP); -#if CONFIG_SPIRAM_USE_MALLOC +#ifdef CONFIG_SPIRAM_USE_MALLOC if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) { if (!esp_ptr_internal(rmt_item)) { - remterr(RMT_PSRAM_BUFFER_WARN_STR); + rmterr(RMT_PSRAM_BUFFER_WARN_STR); return ESP_ERR_INVALID_ARG; } } @@ -1953,7 +1951,7 @@ static struct rmt_dev_s * Initialize the selected RMT device in TX mode * * Input Parameters: - * ch - the RMT's channel that will be used + * ch - The RMT's channel that will be used * pin - The pin used for the TX channel * * Returned Value: @@ -1975,7 +1973,7 @@ struct rmt_dev_s *esp_rmt_tx_init(int ch, int pin) * Initialize the selected RMT device in RC mode * * Input Parameters: - * ch - the RMT's channel that will be used + * ch - The RMT's channel that will be used * pin - The pin used for the RX channel * * Returned Value: diff --git a/arch/xtensa/src/common/espressif/esp_rmt.h b/arch/xtensa/src/common/espressif/esp_rmt.h index 336725bf3f3d5..b1b1d03f8a471 100644 --- a/arch/xtensa/src/common/espressif/esp_rmt.h +++ b/arch/xtensa/src/common/espressif/esp_rmt.h @@ -72,7 +72,7 @@ extern "C" * Initialize the selected RMT device in TX mode * * Input Parameters: - * ch - the RMT's channel that will be used + * ch - The RMT's channel that will be used * pin - The pin used for the TX channel * * Returned Value: @@ -89,7 +89,7 @@ struct rmt_dev_s *esp_rmt_tx_init(int ch, int pin); * Initialize the selected RMT device in RC mode * * Input Parameters: - * ch - the RMT's channel that will be used + * ch - The RMT's channel that will be used * pin - The pin used for the RX channel * * Returned Value: diff --git a/arch/xtensa/src/common/espressif/esp_ws2812.c b/arch/xtensa/src/common/espressif/esp_ws2812.c index 7604b9aab7d30..1baf01fa62d26 100644 --- a/arch/xtensa/src/common/espressif/esp_ws2812.c +++ b/arch/xtensa/src/common/espressif/esp_ws2812.c @@ -45,15 +45,6 @@ * Pre-processor Definitions ****************************************************************************/ -#define APB_PERIOD_PS (1000000000000 / APB_CLK_FREQ) -#define RMT_PERIOD_PS (APB_PERIOD_PS / RMT_DEFAULT_CLK_DIV) // ps - -#define T0H ((uint16_t)(350000 / RMT_PERIOD_PS)) // cyles -#define T0L ((uint16_t)(900000 / RMT_PERIOD_PS)) // cyles -#define T1H ((uint16_t)(900000 / RMT_PERIOD_PS)) // cyles -#define T1L ((uint16_t)(350000 / RMT_PERIOD_PS)) // cyles -#define RES ((uint16_t)(60000000 / RMT_PERIOD_PS)) // cyles - #define rmt_item32_t rmt_symbol_word_t /**************************************************************************** @@ -83,12 +74,32 @@ struct esp_ws2812_dev_s size_t open_count; /* Number of opens on this instance. */ }; +/* RMT channel ID */ + +enum rmt_channel_e +{ + RMT_CHANNEL_0, /* RMT channel number 0 */ + RMT_CHANNEL_1, /* RMT channel number 1 */ + RMT_CHANNEL_2, /* RMT channel number 2 */ + RMT_CHANNEL_3, /* RMT channel number 3 */ +#if SOC_RMT_CHANNELS_PER_GROUP > 4 + RMT_CHANNEL_4, /* RMT channel number 4 */ + RMT_CHANNEL_5, /* RMT channel number 5 */ + RMT_CHANNEL_6, /* RMT channel number 6 */ + RMT_CHANNEL_7, /* RMT channel number 7 */ +#endif + RMT_CHANNEL_MAX /* Number of RMT channels */ +}; + /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -static uint32_t map_byte_to_words(uint8_t byte, uint32_t *dst); -static int map_leds_to_words(struct rgbw_led_s *leds, +static uint32_t map_byte_to_words(struct esp_ws2812_dev_s *dev, + uint8_t byte, + uint32_t *dst); +static int map_leds_to_words(struct esp_ws2812_dev_s *dev, + struct rgbw_led_s *leds, uint32_t n_leds, uint32_t *dst, bool has_white); @@ -100,6 +111,12 @@ static int esp_write(struct file *filep, const char *data, size_t len); * Private Data ****************************************************************************/ +#if SOC_RMT_CHANNEL_CLK_INDEPENDENT +extern uint32_t g_rmt_source_clock_hz[RMT_CHANNEL_MAX]; +#else +extern uint32_t g_rmt_source_clock_hz; +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -109,11 +126,12 @@ static int esp_write(struct file *filep, const char *data, size_t len); * * Description: * Maps a byte to a sequence of RMT items. Each bit in the byte is - * represented by an RMT item (32-bit value). Iterates over each bit in - * the byte, creating an RMT item for each bit, set or not. The created - * RMT items are stored in the destination array. + * represented by an RMT item (32-bit value). The function iterates over + * each bit in the byte, creating an RMT item for each bit, HIGH or LOW. + * The created RMT items are stored in the destination array. * * Input Parameters: + * dev - Pointer to the RMT-based WS2812 device structure. * byte - The byte to be mapped. * dst - Destination array for the RMT items. * @@ -122,10 +140,32 @@ static int esp_write(struct file *filep, const char *data, size_t len); * ****************************************************************************/ -static uint32_t map_byte_to_words(uint8_t byte, uint32_t *dst) +static uint32_t map_byte_to_words(struct esp_ws2812_dev_s *dev, + uint8_t byte, + uint32_t *dst) { uint32_t mapped; uint8_t mask; + uint16_t t0h; + uint16_t t0l; + uint16_t t1h; + uint16_t t1l; + uint32_t clock_period_ps; + uint32_t rmt_period_ps; + +#if SOC_RMT_CHANNEL_CLK_INDEPENDENT + clock_period_ps = 1000000000000 / g_rmt_source_clock_hz[dev->rmt->minor]; +#else + clock_period_ps = 1000000000000 / g_rmt_source_clock_hz; +#endif + rmt_period_ps = clock_period_ps / RMT_DEFAULT_CLK_DIV; + + /* Calculate the RMT period to encode WS2812 frames */ + + t0h = ((uint16_t)(350000 / rmt_period_ps)); + t0l = ((uint16_t)(900000 / rmt_period_ps)); + t1h = ((uint16_t)(900000 / rmt_period_ps)); + t1l = ((uint16_t)(350000 / rmt_period_ps)); mapped = 0; mask = 0x80; @@ -138,11 +178,11 @@ static uint32_t map_byte_to_words(uint8_t byte, uint32_t *dst) if (bit) { - word = (T1L << 16) | (0x8000 | T1H); + word = (t1l << 16) | (0x8000 | t1h); } else { - word = (T0L << 16) | (0x8000 | T0H); + word = (t0l << 16) | (0x8000 | t0h); } *dst = word; @@ -165,6 +205,7 @@ static uint32_t map_byte_to_words(uint8_t byte, uint32_t *dst) * array. * * Input Parameters: + * dev - Pointer to the RMT-based WS2812 device structure. * leds - Pointer to the array of LEDs. * n_leds - Number of LEDs in the array. * dst - Destination array for the RMT items. @@ -176,7 +217,8 @@ static uint32_t map_byte_to_words(uint8_t byte, uint32_t *dst) * ****************************************************************************/ -static int map_leds_to_words(struct rgbw_led_s *leds, +static int map_leds_to_words(struct esp_ws2812_dev_s *dev, + struct rgbw_led_s *leds, uint32_t n_leds, uint32_t *dst, bool has_white) @@ -191,12 +233,20 @@ static int map_leds_to_words(struct rgbw_led_s *leds, dst_offset = 0; for (uint32_t led_idx = 0; led_idx < n_leds; led_idx++) { - dst_offset += map_byte_to_words(leds[led_idx].g, dst + dst_offset); - dst_offset += map_byte_to_words(leds[led_idx].r, dst + dst_offset); - dst_offset += map_byte_to_words(leds[led_idx].b, dst + dst_offset); + dst_offset += map_byte_to_words(dev, + leds[led_idx].g, + dst + dst_offset); + dst_offset += map_byte_to_words(dev, + leds[led_idx].r, + dst + dst_offset); + dst_offset += map_byte_to_words(dev, + leds[led_idx].b, + dst + dst_offset); if (has_white) { - dst_offset += map_byte_to_words(leds[led_idx].w, dst + dst_offset); + dst_offset += map_byte_to_words(dev, + leds[led_idx].w, + dst + dst_offset); } } @@ -290,7 +340,9 @@ static int esp_open(struct file *filep) for (i = 0; i < dev_data->nleds; i++) { - map_leds_to_words(led, 1, + map_leds_to_words(priv, + led, + 1, ((uint32_t *)priv->buf + i * colors * 8), dev_data->has_white); } @@ -428,7 +480,8 @@ static ssize_t esp_write(struct file *filep, const char *data, size_t len) n_leds = dev->nleds - (position / WS2812_RW_PIXEL_SIZE); } - ret = map_leds_to_words((struct rgbw_led_s *)data, + ret = map_leds_to_words(priv, + (struct rgbw_led_s *)data, n_leds, (uint32_t *)bp, dev->has_white); @@ -505,10 +558,10 @@ static ssize_t esp_write(struct file *filep, const char *data, size_t len) * ****************************************************************************/ -struct ws2812_dev_s *esp_ws2812_setup(const char *path, - struct rmt_dev_s *rmt, - uint16_t pixel_count, - bool has_white) +struct ws2812_dev_s *esp_ws2812_setup(const char *path, + struct rmt_dev_s *rmt, + uint16_t pixel_count, + bool has_white) { struct ws2812_dev_s *dev; struct esp_ws2812_dev_s *priv; diff --git a/arch/xtensa/src/common/espressif/esp_ws2812.h b/arch/xtensa/src/common/espressif/esp_ws2812.h index e81c7a6f4aba1..3da5d58f36a03 100644 --- a/arch/xtensa/src/common/espressif/esp_ws2812.h +++ b/arch/xtensa/src/common/espressif/esp_ws2812.h @@ -65,9 +65,9 @@ extern "C" ****************************************************************************/ struct ws2812_dev_s *esp_ws2812_setup(const char *path, - struct rmt_dev_s *rmt, - uint16_t pixel_count, - bool has_white); + struct rmt_dev_s *rmt, + uint16_t pixel_count, + bool has_white); /**************************************************************************** * Name: esp_ws2812_release diff --git a/arch/xtensa/src/common/espressif/platform_include/sys/lock.h b/arch/xtensa/src/common/espressif/platform_include/sys/lock.h new file mode 100644 index 0000000000000..94e4809034087 --- /dev/null +++ b/arch/xtensa/src/common/espressif/platform_include/sys/lock.h @@ -0,0 +1,213 @@ +/**************************************************************************** + * arch/xtensa/src/common/espressif/platform_include/sys/lock.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#pragma once + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include_next + +#ifdef _RETARGETABLE_LOCKING + +/**************************************************************************** + * Public Type Definitions + ****************************************************************************/ + +/* Actual platfrom-specific definition of struct __lock. + * The size here should be sufficient for a NuttX mutex and recursive mutex. + * This is checked by a static assertion in _libc_stubs.c + */ + +struct __lock +{ + int reserved[4]; +}; + +typedef _LOCK_T _lock_t; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: _lock_init + * + * Description: + * Allocate lock related resources. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * None + * + ****************************************************************************/ + +void _lock_init(_lock_t *plock); + +/**************************************************************************** + * Name: _lock_init_recursive + * + * Description: + * Allocate recursive lock related resources. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * None + * + ****************************************************************************/ + +void _lock_init_recursive(_lock_t *plock); + +/**************************************************************************** + * Name: _lock_close + * + * Description: + * Free lock related resources. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * None + * + ****************************************************************************/ + +void _lock_close(_lock_t *plock); + +/**************************************************************************** + * Name: _lock_close_recursive + * + * Description: + * Free recursive lock related resources. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * None + * + ****************************************************************************/ + +void _lock_close_recursive(_lock_t *plock); + +/**************************************************************************** + * Name: _lock_acquire + * + * Description: + * Acquire lock immediately after the lock object is available. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * None + * + ****************************************************************************/ + +void _lock_acquire(_lock_t *plock); + +/**************************************************************************** + * Name: _lock_acquire_recursive + * + * Description: + * Acquire recursive lock immediately after the lock object is available. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * None + * + ****************************************************************************/ + +void _lock_acquire_recursive(_lock_t *plock); + +/**************************************************************************** + * Name: _lock_try_acquire + * + * Description: + * Acquire lock if the lock object is available. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * Zero for success and non-zero to indicate that the lock cannot be + * acquired + * + ****************************************************************************/ + +int _lock_try_acquire(_lock_t *plock); + +/**************************************************************************** + * Name: _lock_try_acquire_recursive + * + * Description: + * Acquire recursive lock if the lock object is available. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * Zero for success and non-zero to indicate that the lock cannot be + * acquired + * + ****************************************************************************/ + +int _lock_try_acquire_recursive(_lock_t *plock); + +/**************************************************************************** + * Name: _lock_release + * + * Description: + * Relinquish the lock ownership. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * None + * + ****************************************************************************/ + +void _lock_release(_lock_t *plock); + +/**************************************************************************** + * Name: _lock_release_recursive + * + * Description: + * Relinquish the recursive lock ownership. + * + * Input Parameters: + * plock - pointer to user defined lock object + * + * Returned Value: + * None + * + ****************************************************************************/ + +void _lock_release_recursive(_lock_t *plock); + +#endif // _RETARGETABLE_LOCKING diff --git a/arch/xtensa/src/common/espressif/utils/memory_reserve.h b/arch/xtensa/src/common/espressif/utils/memory_reserve.h new file mode 100644 index 0000000000000..a2214059a6ee9 --- /dev/null +++ b/arch/xtensa/src/common/espressif/utils/memory_reserve.h @@ -0,0 +1,85 @@ +/**************************************************************************** + * arch/xtensa/src/common/espressif/utils/memory_reserve.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#pragma once + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include "sdkconfig.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Region descriptor holds a description for a particular region of + * memory reserved on this SoC for a particular use (ie not available + * for stack/heap usage.) + */ + +typedef struct +{ + intptr_t start; + intptr_t end; +} soc_reserved_region_t; + +/**************************************************************************** + * Helper Macros/Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: SOC_RESERVE_MEMORY_REGION + * + * Description: + * Macro to reserve a fixed region of RAM (hardcoded addresses) for a + * particular purpose. Usually used to mark out memory addresses needed + * for hardware or ROM code purposes. Not intended for user code which + * can use normal C static allocation instead. + * + * Input Parameters: + * START - Start address to be reserved. + * END - One memory address after the address of the last byte to be + * reserved. + * (ie length of the reserved region is (END - START) in bytes.) + * NAME - Name for the reserved region. Must be a valid variable name, + * unique to this source file. + * + * Returned Value: + * None + * + ****************************************************************************/ + +#define SOC_RESERVE_MEMORY_REGION(START, END, NAME) \ + __attribute__((section(".reserved_memory_address"))) \ + __attribute__((used)) \ + static soc_reserved_region_t reserved_region_##NAME = { START, END }; + +#ifdef __cplusplus +} +#endif diff --git a/arch/xtensa/src/common/xtensa.h b/arch/xtensa/src/common/xtensa.h index f1e3babd1f911..4a59b6bc19d65 100644 --- a/arch/xtensa/src/common/xtensa.h +++ b/arch/xtensa/src/common/xtensa.h @@ -229,11 +229,6 @@ void xtensa_window_spill(void); /* IRQs */ -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 -uintptr_t xtensa_intstack_alloc(void); -uintptr_t xtensa_intstack_top(void); -#endif - uint32_t *xtensa_int_decode(uint32_t cpuints, uint32_t *regs); uint32_t *xtensa_irq_dispatch(int irq, uint32_t *regs); uint32_t xtensa_enable_cpuint(uint32_t *shadow, uint32_t intmask); diff --git a/arch/xtensa/src/common/xtensa_backtrace.c b/arch/xtensa/src/common/xtensa_backtrace.c index 9de290b61a6c0..a68016cdb628f 100644 --- a/arch/xtensa/src/common/xtensa_backtrace.c +++ b/arch/xtensa/src/common/xtensa_backtrace.c @@ -235,16 +235,11 @@ int up_backtrace(struct tcb_s *tcb, void **buffer, int size, int skip) if (up_interrupt_context()) { #if CONFIG_ARCH_INTERRUPTSTACK > 15 - void *istackbase; -#ifdef CONFIG_SMP - istackbase = xtensa_intstack_alloc(); -#else - istackbase = g_intstackalloc; -#endif - xtensa_window_spill(); + void *istackbase = (void *)up_get_intstackbase(up_cpu_index()); + xtensa_window_spill(); ret = backtrace_stack(istackbase, - (istackbase + CONFIG_ARCH_INTERRUPTSTACK), + istackbase + CONFIG_ARCH_INTERRUPTSTACK, (void *)up_getsp(), NULL, buffer, size, &skip); #else diff --git a/arch/xtensa/src/common/xtensa_checkstack.c b/arch/xtensa/src/common/xtensa_checkstack.c index e50b3b6219a9c..6bdc76157c0d3 100644 --- a/arch/xtensa/src/common/xtensa_checkstack.c +++ b/arch/xtensa/src/common/xtensa_checkstack.c @@ -163,9 +163,9 @@ size_t up_check_tcbstack(struct tcb_s *tcb) } #if CONFIG_ARCH_INTERRUPTSTACK > 15 -size_t up_check_intstack(void) +size_t up_check_intstack(int cpu) { - return xtensa_stack_check(up_get_intstackbase(), INTSTACK_SIZE); + return xtensa_stack_check(up_get_intstackbase(cpu), INTSTACK_SIZE); } #endif diff --git a/arch/xtensa/src/common/xtensa_cpupause.c b/arch/xtensa/src/common/xtensa_cpupause.c index 9a8697f3cf5af..12cfcfa5498d5 100644 --- a/arch/xtensa/src/common/xtensa_cpupause.c +++ b/arch/xtensa/src/common/xtensa_cpupause.c @@ -70,25 +70,17 @@ bool up_cpu_pausereq(int cpu) } /**************************************************************************** - * Name: up_cpu_paused + * Name: up_cpu_paused_save * * Description: * Handle a pause request from another CPU. Normally, this logic is * executed from interrupt handling logic within the architecture-specific - * However, it is sometimes necessary to perform the pending pause - * operation in other contexts where the interrupt cannot be taken in - * order to avoid deadlocks. - * - * This function performs the following operations: - * - * 1. It saves the current task state at the head of the current assigned - * task list. - * 2. It waits on a spinlock, then - * 3. Returns from interrupt, restoring the state of the new task at the - * head of the ready to run list. + * However, it is sometimes necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. * * Input Parameters: - * cpu - The index of the CPU to be paused + * None * * Returned Value: * On success, OK is returned. Otherwise, a negated errno value indicating @@ -96,7 +88,7 @@ bool up_cpu_pausereq(int cpu) * ****************************************************************************/ -int up_cpu_paused(int cpu) +int up_cpu_paused_save(void) { struct tcb_s *tcb = this_task(); @@ -116,6 +108,38 @@ int up_cpu_paused(int cpu) xtensa_savestate(tcb->xcp.regs); + return OK; +} + +/**************************************************************************** + * Name: up_cpu_paused + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary to perform the pending pause + * operation in other contexts where the interrupt cannot be taken in + * order to avoid deadlocks. + * + * This function performs the following operations: + * + * 1. It saves the current task state at the head of the current assigned + * task list. + * 2. It waits on a spinlock, then + * 3. Returns from interrupt, restoring the state of the new task at the + * head of the ready to run list. + * + * Input Parameters: + * cpu - The index of the CPU to be paused + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused(int cpu) +{ /* Wait for the spinlock to be released */ spin_unlock(&g_cpu_paused[cpu]); @@ -126,11 +150,31 @@ int up_cpu_paused(int cpu) spin_lock(&g_cpu_wait[cpu]); - /* Restore the exception context of the tcb at the (new) head of the - * assigned task list. - */ + spin_unlock(&g_cpu_wait[cpu]); + spin_unlock(&g_cpu_resumed[cpu]); - tcb = this_task(); + return OK; +} + +/**************************************************************************** + * Name: up_cpu_paused_restore + * + * Description: + * Restore the state of the CPU after it was paused via up_cpu_pause(), + * and resume normal tasking. + * + * Input Parameters: + * None + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +int up_cpu_paused_restore(void) +{ + struct tcb_s *tcb = this_task(); #ifdef CONFIG_SCHED_INSTRUMENTATION /* Notify that we have resumed */ @@ -148,9 +192,6 @@ int up_cpu_paused(int cpu) xtensa_restorestate(tcb->xcp.regs); - spin_unlock(&g_cpu_wait[cpu]); - spin_unlock(&g_cpu_resumed[cpu]); - return OK; } diff --git a/arch/xtensa/src/common/xtensa_exit.c b/arch/xtensa/src/common/xtensa_exit.c index 83ddcc8d641d5..47f7024aa0623 100644 --- a/arch/xtensa/src/common/xtensa_exit.c +++ b/arch/xtensa/src/common/xtensa_exit.c @@ -62,8 +62,6 @@ void up_exit(int status) enter_critical_section(); - sinfo("TCB=%p exiting\n", tcb); - nxsched_dumponexit(); /* Destroy the task at the head of the ready to run list. */ diff --git a/arch/xtensa/src/common/xtensa_getintstack.c b/arch/xtensa/src/common/xtensa_getintstack.c index eb64149ddd70d..3a5a6f54d0fb7 100644 --- a/arch/xtensa/src/common/xtensa_getintstack.c +++ b/arch/xtensa/src/common/xtensa_getintstack.c @@ -36,13 +36,9 @@ * Name: up_get_intstackbase ****************************************************************************/ -#if CONFIG_ARCH_INTERRUPTSTACK > 3 -uintptr_t up_get_intstackbase(void) +#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 3 +uintptr_t up_get_intstackbase(int cpu) { -#ifdef CONFIG_SMP - return (uintptr_t)xtensa_intstack_alloc(); -#else return (uintptr_t)g_intstackalloc; -#endif } #endif diff --git a/arch/xtensa/src/common/xtensa_initialize.c b/arch/xtensa/src/common/xtensa_initialize.c index c645005f9b75f..92c5f28b1f111 100644 --- a/arch/xtensa/src/common/xtensa_initialize.c +++ b/arch/xtensa/src/common/xtensa_initialize.c @@ -60,17 +60,11 @@ volatile uint32_t *g_current_regs[CONFIG_SMP_NCPUS]; #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 15 static inline void xtensa_color_intstack(void) { -#ifdef CONFIG_SMP - uint32_t *ptr = (uint32_t *)xtensa_intstack_alloc(); -#else - uint32_t *ptr = (uint32_t *)g_intstackalloc; -#endif - ssize_t size; + int cpu; - for (size = INTSTACK_SIZE * CONFIG_SMP_NCPUS; - size > 0; size -= sizeof(uint32_t)) + for (cpu = 0; cpu < CONFIG_SMP_NCPUS; cpu++) { - *ptr++ = INTSTACK_COLOR; + xtensa_stack_color((void *)up_get_intstackbase(cpu), INTSTACK_SIZE); } } #else diff --git a/arch/xtensa/src/esp32/Bootloader.mk b/arch/xtensa/src/esp32/Bootloader.mk index 0c2be5fde081e..3041f370a0fcd 100644 --- a/arch/xtensa/src/esp32/Bootloader.mk +++ b/arch/xtensa/src/esp32/Bootloader.mk @@ -192,15 +192,7 @@ else ifeq ($(CONFIG_ESP32_BOOTLOADER_DOWNLOAD_PREBUILT),y) BOOTLOADER_VERSION = latest BOOTLOADER_URL = https://github.com/espressif/esp-nuttx-bootloader/releases/download/$(BOOTLOADER_VERSION) -ifeq ($(CONFIG_ESP32_APP_FORMAT_MCUBOOT),y) - -bootloader: - $(call DOWNLOAD,$(BOOTLOADER_URL),mcuboot-esp32.bin,$(TOPDIR)/mcuboot-esp32.bin) - -clean_bootloader: - $(call DELFILE,$(TOPDIR)/mcuboot-esp32.bin) - -else ifeq ($(CONFIG_ESP32_APP_FORMAT_LEGACY),y) +ifeq ($(CONFIG_ESP32_APP_FORMAT_LEGACY),y) bootloader: $(call DOWNLOAD,$(BOOTLOADER_URL),bootloader-esp32.bin,$(TOPDIR)/bootloader-esp32.bin) diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig index 0e374b24d9fb9..be4846b3c80cf 100644 --- a/arch/xtensa/src/esp32/Kconfig +++ b/arch/xtensa/src/esp32/Kconfig @@ -99,6 +99,10 @@ config ARCH_CHIP_ESP32PICOD4 endchoice # ESP32 Chip Selection +config ESPRESSIF_CHIP_SERIES + string + default "esp32" + config ESP32_SINGLE_CPU bool default n @@ -209,6 +213,8 @@ config ESP32_EXCEPTION_ENABLE_CACHE menu "ESP32 Peripheral Selection" +source "arch/xtensa/src/common/espressif/Kconfig" + config ESP32_UART bool default n @@ -241,6 +247,33 @@ config ESP32_EMAC ---help--- Enable ESP32 ethernet support. +config ESP32_OPENETH + bool "Opencores Ethernet MAC" + default n + depends on !ESP32_EMAC + select NET + select SCHED_WORKQUEUE + ---help--- + Enable ESP32 ethernet opencores support for use with QEMU. + Disable this if you are using the real device. + +if ESP32_OPENETH +config ESP32_OPENETH_DMA_RX_BUFFER_NUM + int "Number of Ethernet DMA Rx buffers" + range 1 64 + default 4 + ---help--- + Number of DMA receive buffers, each buffer is 1600 bytes. + +config ESP32_OPENETH_DMA_TX_BUFFER_NUM + int "Number of Ethernet DMA Tx buffers" + range 1 64 + default 1 + ---help--- + Number of DMA transmit buffers, each buffer is 1600 bytes. + +endif # ESP32_OPENETH + config ESP32_I2C bool default n @@ -265,14 +298,6 @@ config ESP32_PCNT Pulse Counter is currently used to implement Quadracture Encoder. -config ESP32_RMT - bool "Remote Control Module (RMT)" - default n - depends on EXPERIMENTAL - ---help--- - Remote Control Module is currently used to control WS2812 - RGB LED normally used on LED strips. - config ESP32_RNG bool "Random Number Generator (RNG)" default n @@ -764,8 +789,10 @@ endmenu # ESP32 Peripheral Selection config ESP32_WIFI_BT_COEXIST bool "Wi-Fi and BT coexist" + default y if ESP32_WIFI && ESP32_BLE default n depends on ESP32_WIFI && ESP32_BLE + select ESP32_WIFI_STA_DISCONNECT_PM menu "Interrupt Configuration" @@ -1870,6 +1897,7 @@ comment "Partition Table Configuration" config ESP32_PARTITION_TABLE bool "Create MTD partitions from Partition Table" default n + select ESP32_BOOTLOADER_BUILD_FROM_SOURCE ---help--- Decode partition table and initialize partitions as MTD. @@ -2354,6 +2382,35 @@ config ESP32_RTC_CLK_SRC_INT_8MD256 endchoice endmenu # "RTC Configuration" +menu "DAC Configuration" + depends on ANALOG && DAC + +config ESP32_DAC_DEVPATH + string "DAC device path" + default "/dev/dac0" + +choice ESP32_DAC_MODE + prompt "DAC mode of operation" + default ESP32_DAC_MODE_ONE_SHOT + ---help--- + One-shot mode requires to write every single value with a write call while + retaining the last value on output. + + Following modes are not implemented yet. + Timer mode utilizes timer IRQs to call handler which can manage the write. + DMA is using a ring buffer accessed directly by the driver. + Cosine Wave Generator can output preset wave without the need to generate + the data and write in memory. + +config ESP32_DAC_MODE_ONE_SHOT + bool "One-shot mode" + ---help--- + One-shot mode requires to write every single value with a write call while + retaining the last value on output. + +endchoice # "DAC mode of operation" +endmenu # "DAC Configuration" + menu "LEDC Configuration" depends on ESP32_LEDC @@ -2443,42 +2500,28 @@ config ESP32_HAVE_OTA_PARTITION bool default n -menu "Application Image Configuration" - -choice - prompt "Application Image Format" - default ESP32_APP_FORMAT_LEGACY - ---help--- - Depending on the chosen 2nd stage bootloader, the application may - be required to be perform a specific startup routine. Furthermore, - the image binary must be formatted according to the definition from - the 2nd stage bootloader. +menu "Bootloader and Image Configuration" config ESP32_APP_FORMAT_LEGACY - bool "Legacy format" + bool + default y if !ESP32_APP_FORMAT_MCUBOOT + depends on !ESP32_APP_FORMAT_MCUBOOT ---help--- This is the legacy application image format, as supported by the ESP-IDF 2nd stage bootloader. config ESP32_APP_FORMAT_MCUBOOT - bool "MCUboot-bootable format" + bool "Enable MCUboot-bootable format" depends on !MCUBOOT_BOOTLOADER select ESP32_HAVE_OTA_PARTITION + select ESP32_BOOTLOADER_BUILD_FROM_SOURCE ---help--- - The ESP32 port of MCUboot supports the loading of unsegmented firmware - images. - -endchoice # Application Image Format - -choice - prompt "Source for bootloader binaries" - default ESP32_BOOTLOADER_DOWNLOAD_PREBUILT - ---help--- - Select the action to be taken by the build system for the - "make bootloader" target. + Enables the Espressif port of MCUboot to be used as 2nd stage bootloader. config ESP32_BOOTLOADER_DOWNLOAD_PREBUILT - bool "Download prebuilt binaries" + bool + default y if !ESP32_BOOTLOADER_BUILD_FROM_SOURCE + depends on !ESP32_BOOTLOADER_BUILD_FROM_SOURCE ---help--- The build system will download the prebuilt binaries from https://github.com/espressif/esp-nuttx-bootloader according to the chosen @@ -2492,8 +2535,6 @@ config ESP32_BOOTLOADER_BUILD_FROM_SOURCE custom bootloader according to the chosen Application Image Format (ESP32_APP_FORMAT_LEGACY or ESP32_APP_FORMAT_MCUBOOT) and partition information. -endchoice - choice prompt "Target slot for image flashing" default ESP32_ESPTOOL_TARGET_PRIMARY @@ -2529,11 +2570,37 @@ config ESP32_APP_MCUBOOT_HEADER_SIZE default 32 depends on ESP32_APP_FORMAT_MCUBOOT +config ESP32_PARTITION_TABLE_OFFSET_DEFAULT + hex + default 0x8000 + depends on ESP32_APP_FORMAT_LEGACY + +config ESP32_CUSTOM_PARTITION_TABLE_OFFSET + bool "Customize partition table offset" + default n + depends on ESP32_APP_FORMAT_LEGACY + select ESP32_BOOTLOADER_BUILD_FROM_SOURCE + ---help--- + Enable to select the offset of the partition table in the flash. + +if ESP32_CUSTOM_PARTITION_TABLE_OFFSET + config ESP32_PARTITION_TABLE_OFFSET hex "Partition Table offset" - default 0x8000 + default ESP32_PARTITION_TABLE_OFFSET_DEFAULT depends on ESP32_APP_FORMAT_LEGACY +endif # ESP32_CUSTOM_PARTITION_TABLE_OFFSET + +if !ESP32_CUSTOM_PARTITION_TABLE_OFFSET + +config ESP32_PARTITION_TABLE_OFFSET + hex + default ESP32_PARTITION_TABLE_OFFSET_DEFAULT + depends on ESP32_APP_FORMAT_LEGACY + +endif # !ESP32_CUSTOM_PARTITION_TABLE_OFFSET + if BUILD_PROTECTED config ESP32_USER_IMAGE_OFFSET diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index b71e77879eecb..a7a604e7548af 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -61,6 +61,10 @@ ifeq ($(CONFIG_XTENSA_IMEM_USE_SEPARATE_HEAP),y) CHIP_CSRCS += esp32_imm.c endif +ifeq ($(CONFIG_DAC),y) +CHIP_CSRCS += esp32_dac.c +endif + ifeq ($(CONFIG_ESP32_LEDC),y) CHIP_CSRCS += esp32_ledc.c endif @@ -81,10 +85,6 @@ ifeq ($(CONFIG_ESP32_PCNT_AS_QE),y) CHIP_CSRCS += esp32_qencoder.c endif -ifeq ($(CONFIG_ESP32_RMT),y) -CHIP_CSRCS += esp32_rmt.c -endif - ifeq ($(CONFIG_ESP32_SPI),y) CHIP_CSRCS += esp32_spi.c ifeq ($(CONFIG_SPI_SLAVE),y) @@ -111,9 +111,8 @@ CHIP_CSRCS += esp32_himem.c CHIP_CSRCS += esp32_himem_chardev.c endif -ifeq ($(CONFIG_ESP32_EFUSE),y) CHIP_CSRCS += esp32_efuse.c -CHIP_CSRCS += esp32_efuse_table.c +ifeq ($(CONFIG_ESP32_EFUSE),y) CHIP_CSRCS += esp32_efuse_lowerhalf.c endif @@ -197,58 +196,8 @@ CHIP_CSRCS += esp32_rtc_lowerhalf.c endif endif -ifeq ($(CONFIG_ESP32_WIRELESS),y) -WIRELESS_DRV_UNPACK = esp-wireless-drivers-3rdparty -WIRELESS_DRV_ID = 45701c0 -WIRELESS_DRV_ZIP = $(WIRELESS_DRV_ID).zip -WIRELESS_DRV_URL = https://github.com/espressif/esp-wireless-drivers-3rdparty/archive - -$(WIRELESS_DRV_ZIP): - $(call DOWNLOAD,$(WIRELESS_DRV_URL),$(WIRELESS_DRV_ZIP),chip/$(WIRELESS_DRV_ZIP)) - -chip/$(WIRELESS_DRV_UNPACK): $(WIRELESS_DRV_ZIP) - $(Q) echo "Unpacking: ESP Wireless Drivers" - $(Q) unzip -oqq chip/$(WIRELESS_DRV_ZIP) -d chip/ - $(Q) mv chip/$(WIRELESS_DRV_UNPACK)-$(WIRELESS_DRV_ID)* chip/$(WIRELESS_DRV_UNPACK) - $(Q) touch chip/$(WIRELESS_DRV_UNPACK) - -ifeq ($(wildcard chip/$(WIRELESS_DRV_UNPACK)/.git),) -context:: chip/$(WIRELESS_DRV_UNPACK) - -distclean:: - $(call DELFILE, chip/$(WIRELESS_DRV_ZIP)) - $(call DELDIR, chip/$(WIRELESS_DRV_UNPACK)) -endif - -INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)esp-wireless-drivers-3rdparty$(DELIM)include -INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)esp-wireless-drivers-3rdparty$(DELIM)include$(DELIM)esp32 - -EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)esp-wireless-drivers-3rdparty$(DELIM)libs$(DELIM)esp32 -EXTRA_LIBS += -lphy -lrtc - -# Wireless interfaces. - -CHIP_CSRCS += esp32_wireless.c -endif - -ifeq ($(CONFIG_ESP32_WIFI),y) -CHIP_CSRCS += esp32_wlan.c esp32_wifi_utils.c esp32_wifi_adapter.c -EXTRA_LIBS += -lcore -lnet80211 -lpp -lsmartconfig -lespnow -lwpa_supplicant - -ifeq ($(GCCVER),) - export GCCVER := $(shell $(CC) --version | grep gcc | sed -E 's/.* ([0-9]+\.[0-9]+).*/\1/' | cut -d'.' -f1) -endif -ifeq ($(GCCVER),12) - chip/esp32_wifi_adapter.c_CFLAGS += -Wno-maybe-uninitialized -endif -endif - -ifeq ($(CONFIG_ESP32_BLE),y) -CHIP_CSRCS += esp32_ble_adapter.c esp32_ble.c -EXTRA_LIBS += -lbtdm_app - ifeq ($(CONFIG_ESP32_WIFI_BT_COEXIST),y) - EXTRA_LIBS += -lcoexist - endif +ifeq ($(CONFIG_ESP32_OPENETH),y) +CHIP_CSRCS += esp32_openeth.c endif ############################################################################# @@ -259,11 +208,18 @@ endif ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty ifndef ESP_HAL_3RDPARTY_VERSION - ESP_HAL_3RDPARTY_VERSION = 2fbc8a025275d68833cdfef490377048538de57a + ESP_HAL_3RDPARTY_VERSION = 966f1bbf7d80d3fac9a43f414e864985cbcfd680 endif ifndef ESP_HAL_3RDPARTY_URL - ESP_HAL_3RDPARTY_URL = https://github.com/espressif/esp-hal-3rdparty.git + ESP_HAL_3RDPARTY_URL = https://github.com/espressif/esp-hal-3rdparty.git +endif + +ifndef DISABLE_GIT_DEPTH +ifndef GIT_DEPTH + GIT_DEPTH=1 +endif + GIT_DEPTH_PARAMETER = --depth=$(GIT_DEPTH) endif chip/$(ESP_HAL_3RDPARTY_REPO): @@ -276,7 +232,33 @@ chip/$(ESP_HAL_3RDPARTY_REPO): CFLAGS += -Wno-undef -Wno-unused-variable +# Files that require the HAL recipe + +CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES)) + include chip/Bootloader.mk +include chip/hal.mk + +include common/espressif/Make.defs + +context:: chip/$(ESP_HAL_3RDPARTY_REPO) +ifeq ($(CONFIG_ESP32_WIRELESS),y) + $(Q) echo "Espressif HAL for 3rd Party Platforms: initializing submodules..." + $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) submodule --quiet update --init $(GIT_DEPTH_PARAMETER) components/mbedtls/mbedtls components/esp_phy/lib components/esp_wifi/lib components/bt/controller/lib_esp32 components/esp_coex/lib + $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls reset --quiet --hard + $(Q) echo "Applying patches..." + $(Q) cd chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls && git apply ../../../nuttx/patches/components/mbedtls/mbedtls/*.patch +endif + +distclean:: + $(call DELDIR, chip/$(ESP_HAL_3RDPARTY_REPO)) + +ifeq ($(CONFIG_ESP32_WIRELESS),y) +include chip/Wireless.mk +endif + distclean:: $(call DELDIR,chip/$(ESP_HAL_3RDPARTY_REPO)) + +INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)common$(DELIM)espressif diff --git a/arch/xtensa/src/esp32/Wireless.mk b/arch/xtensa/src/esp32/Wireless.mk new file mode 100644 index 0000000000000..93ef1b810bb13 --- /dev/null +++ b/arch/xtensa/src/esp32/Wireless.mk @@ -0,0 +1,253 @@ +############################################################################ +# arch/xtensa/src/esp32/Wireless.mk +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)include$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_coex$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)esp_wifi + +EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)controller$(DELIM)lib_esp32$(DELIM)$(CHIP_SERIES) +EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_coex$(DELIM)lib$(DELIM)$(CHIP_SERIES) +EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)lib$(DELIM)$(CHIP_SERIES) +EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)lib$(DELIM)$(CHIP_SERIES) + +EXTRA_LIBS += -lrtc -lphy -lcoexist + +# Wireless interfaces. + +CHIP_CSRCS += esp32_wireless.c + +ifeq ($(CONFIG_ESP32_BLE),y) +CHIP_CSRCS += esp32_ble_adapter.c esp32_ble.c +EXTRA_LIBS += -lbtdm_app +endif + +ifeq ($(CONFIG_ESP32_WIFI),y) +CHIP_CSRCS += esp32_wlan.c esp32_wifi_utils.c esp32_wifi_adapter.c +EXTRA_LIBS += -lcore -lnet80211 -lpp + +ifeq ($(CONFIG_WPA_WAPI_PSK),y) +EXTRA_LIBS += -lwapi +endif + +## ESP-IDF's mbedTLS + +VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)library + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)library +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls + +### Define Espressif's configs for mbedTLS + +CFLAGS += $(DEFINE_PREFIX)MBEDTLS_CONFIG_FILE="" + +CHIP_CSRCS += aes.c +CHIP_CSRCS += aria.c +CHIP_CSRCS += bignum_core.c +CHIP_CSRCS += bignum.c +CHIP_CSRCS += ccm.c +CHIP_CSRCS += cipher_wrap.c +CHIP_CSRCS += cipher.c +CHIP_CSRCS += cmac.c +CHIP_CSRCS += constant_time.c +CHIP_CSRCS += ctr_drbg.c +CHIP_CSRCS += ecp_curves.c +CHIP_CSRCS += ecp.c +CHIP_CSRCS += entropy.c +CHIP_CSRCS += gcm.c +CHIP_CSRCS += md.c +CHIP_CSRCS += pkcs5.c +CHIP_CSRCS += platform_util.c +CHIP_CSRCS += platform.c +CHIP_CSRCS += sha1.c +CHIP_CSRCS += sha256.c +CHIP_CSRCS += sha512.c +CHIP_CSRCS += pk.c +CHIP_CSRCS += pk_wrap.c +CHIP_CSRCS += pkparse.c +CHIP_CSRCS += ecdsa.c +CHIP_CSRCS += asn1parse.c +CHIP_CSRCS += asn1write.c +CHIP_CSRCS += rsa.c +CHIP_CSRCS += md5.c +CHIP_CSRCS += oid.c +CHIP_CSRCS += pem.c +CHIP_CSRCS += hmac_drbg.c +CHIP_CSRCS += hash_info.c +CHIP_CSRCS += rsa_alt_helpers.c +CHIP_CSRCS += ecdh.c + +VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port + +CHIP_CSRCS += esp_hardware.c +CHIP_CSRCS += esp_mem.c +CHIP_CSRCS += esp_timing.c + +VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)md + +CHIP_CSRCS += esp_md.c + +## WPA Supplicant + +WIFI_WPA_SUPPLICANT = chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)wpa_supplicant + +CFLAGS += $(DEFINE_PREFIX)__ets__ +CFLAGS += $(DEFINE_PREFIX)CONFIG_CRYPTO_MBEDTLS +CFLAGS += $(DEFINE_PREFIX)CONFIG_ECC +CFLAGS += $(DEFINE_PREFIX)CONFIG_IEEE80211W +CFLAGS += $(DEFINE_PREFIX)CONFIG_WPA3_SAE +CFLAGS += $(DEFINE_PREFIX)EAP_PEER_METHOD +CFLAGS += $(DEFINE_PREFIX)ESP_PLATFORM=1 +CFLAGS += $(DEFINE_PREFIX)ESP_SUPPLICANT +CFLAGS += $(DEFINE_PREFIX)ESPRESSIF_USE +CFLAGS += $(DEFINE_PREFIX)IEEE8021X_EAPOL +CFLAGS += $(DEFINE_PREFIX)USE_WPA2_TASK +CFLAGS += $(DEFINE_PREFIX)CONFIG_SHA256 +CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE + +ifeq ($(CONFIG_ESP_WIFI_ENABLE_SAE_PK),y) +CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE_PK +endif + +ifeq ($(CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA),y) +CFLAGS += $(DEFINE_PREFIX)CONFIG_OWE_STA +endif + +ifeq ($(CONFIG_ESP_WIFI_GCMP_SUPPORT),y) +CFLAGS += $(DEFINE_PREFIX)CONFIG_GCMP +endif + +ifeq ($(CONFIG_ESP_WIFI_GMAC_SUPPORT),y) +CFLAGS += $(DEFINE_PREFIX)CONFIG_GMAC +endif + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src + +VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)ap + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)ap + +CHIP_CSRCS += ap_config.c +CHIP_CSRCS += ieee802_11.c +CHIP_CSRCS += comeback_token.c +CHIP_CSRCS += pmksa_cache_auth.c +CHIP_CSRCS += sta_info.c +CHIP_CSRCS += wpa_auth_ie.c +CHIP_CSRCS += wpa_auth.c + +VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)common + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)common + +CHIP_CSRCS += dragonfly.c +CHIP_CSRCS += sae.c +CHIP_CSRCS += wpa_common.c +CHIP_CSRCS += sae_pk.c +CHIP_CSRCS += bss.c +CHIP_CSRCS += scan.c +CHIP_CSRCS += ieee802_11_common.c + +VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)crypto + +CHIP_CSRCS += aes-ccm.c +CHIP_CSRCS += aes-gcm.c +CHIP_CSRCS += aes-omac1.c +CHIP_CSRCS += aes-unwrap.c +CHIP_CSRCS += aes-wrap.c +CHIP_CSRCS += ccmp.c +CHIP_CSRCS += crypto_ops.c +CHIP_CSRCS += des-internal.c +CHIP_CSRCS += dh_groups.c +CHIP_CSRCS += rc4.c +CHIP_CSRCS += sha1-prf.c +CHIP_CSRCS += sha256-kdf.c +CHIP_CSRCS += sha256-prf.c + +VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)eap_peer + +CHIP_CSRCS += chap.c +CHIP_CSRCS += eap_common.c +CHIP_CSRCS += eap_mschapv2.c +CHIP_CSRCS += eap_peap_common.c +CHIP_CSRCS += eap_peap.c +CHIP_CSRCS += eap_tls_common.c +CHIP_CSRCS += eap_tls.c +CHIP_CSRCS += eap_ttls.c +CHIP_CSRCS += eap.c +CHIP_CSRCS += mschapv2.c + +VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)rsn_supp + +CHIP_CSRCS += pmksa_cache.c +CHIP_CSRCS += wpa_ie.c +CHIP_CSRCS += wpa.c + +VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)utils + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)utils + +CHIP_CSRCS += base64.c +CHIP_CSRCS += bitfield.c +CHIP_CSRCS += common.c +CHIP_CSRCS += ext_password.c +CHIP_CSRCS += json.c +CHIP_CSRCS += uuid.c +CHIP_CSRCS += wpa_debug.c +CHIP_CSRCS += wpabuf.c + +VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)port + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)port$(DELIM)include + +CHIP_CSRCS += eloop.c +CHIP_CSRCS += os_xtensa.c + +## ESP Supplicant (Espressif's WPA supplicant extension) + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)include + +VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src + +CHIP_CSRCS += esp_common.c +CHIP_CSRCS += esp_hostap.c +CHIP_CSRCS += esp_wpa_main.c +CHIP_CSRCS += esp_wpa2.c +CHIP_CSRCS += esp_wpa3.c +CHIP_CSRCS += esp_wpas_glue.c +CHIP_CSRCS += esp_owe.c +CHIP_CSRCS += esp_scan.c + +VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src$(DELIM)crypto + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)crypto + +CHIP_CSRCS += crypto_mbedtls-bignum.c +CHIP_CSRCS += crypto_mbedtls-ec.c +CHIP_CSRCS += crypto_mbedtls-rsa.c +CHIP_CSRCS += crypto_mbedtls.c +CHIP_CSRCS += tls_mbedtls.c +CHIP_CSRCS += aes-siv.c + +endif diff --git a/arch/xtensa/src/esp32/esp32_ble_adapter.c b/arch/xtensa/src/esp32/esp32_ble_adapter.c index 6c414936e257f..f0650665179f5 100644 --- a/arch/xtensa/src/esp32/esp32_ble_adapter.c +++ b/arch/xtensa/src/esp32/esp32_ble_adapter.c @@ -51,65 +51,79 @@ #include "hardware/esp32_dport.h" #include "hardware/wdev_reg.h" -#include "espidf_wifi.h" #include "xtensa.h" #include "xtensa_attr.h" +#include "utils/memory_reserve.h" #include "esp32_rt_timer.h" -#include "esp32_ble_adapter.h" #include "esp32_wireless.h" #include "esp32_irq.h" #include "esp32_spicache.h" -#ifdef CONFIG_ESP32_WIFI_BT_COEXIST -# include "esp_coexist_internal.h" -#endif +#include "esp_bt.h" +#include "esp_log.h" +#include "esp_mac.h" +#include "esp_private/phy.h" +#include "esp_private/wifi.h" +#include "esp_random.h" +#include "esp_timer.h" +#include "periph_ctrl.h" +#include "rom/ets_sys.h" +#include "soc/soc_caps.h" +#include "xtensa/core-macros.h" +#include "xtensa/xtensa_api.h" +#include "esp_coexist_internal.h" + +#include "esp32_ble_adapter.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -typedef void (*xt_handler)(void *); -typedef void (*coex_func_cb_t)(uint32_t event, int sched_cnt); - -#define XTHAL_SET_INTSET(v) \ -do {\ - int __interrupt = (int)(v);\ - __asm__ __volatile__("wsr.intset %0" :: "a"(__interrupt):"memory");\ -} while(0) +/* Bluetooth system and controller config */ -#define MSG_QUEUE_NAME_SIZE 16 +#define BTDM_CFG_BT_DATA_RELEASE (1<<0) +#define BTDM_CFG_HCI_UART (1<<1) +#define BTDM_CFG_CONTROLLER_RUN_APP_CPU (1<<2) +#define BTDM_CFG_SCAN_DUPLICATE_OPTIONS (1<<3) +#define BTDM_CFG_SEND_ADV_RESERVED_SIZE (1<<4) +#define BTDM_CFG_BLE_FULL_SCAN_SUPPORTED (1<<5) -#define OSI_FUNCS_TIME_BLOCKING 0xffffffff -#define OSI_VERSION 0x00010002 -#define OSI_MAGIC_VALUE 0xfadebead +/* Sleep mode */ -#define BTDM_ASYNC_WAKEUP_REQ_HCI 0 -#define BTDM_ASYNC_WAKEUP_REQ_COEX 1 -#define BTDM_ASYNC_WAKEUP_REQMAX 2 - -#ifdef CONFIG_PM -#define BTDM_MIN_TIMER_UNCERTAINTY_US (1800) +#define BTDM_MODEM_SLEEP_MODE_NONE (0) +#define BTDM_MODEM_SLEEP_MODE_ORIG (1) +#define BTDM_MODEM_SLEEP_MODE_EVED (2) /* sleep mode for BLE controller, used only for internal test. */ /* Low Power Clock Selection */ -#define BTDM_LPCLK_SEL_XTAL (0) -#define BTDM_LPCLK_SEL_XTAL32K (1) -#define BTDM_LPCLK_SEL_RTC_SLOW (2) -#define BTDM_LPCLK_SEL_8M (3) +#define BTDM_LPCLK_SEL_XTAL (0) +#define BTDM_LPCLK_SEL_XTAL32K (1) +#define BTDM_LPCLK_SEL_RTC_SLOW (2) +#define BTDM_LPCLK_SEL_8M (3) /* Sleep and wakeup interval control */ -#define BTDM_MIN_SLEEP_DURATION (24) /* Threshold of interval in half slots to allow to fall into sleep mode */ -#define BTDM_MODEM_WAKE_UP_DELAY (8) /* delay in half slots of modem wake up procedure, including re-enable PHY/RF */ +#define BTDM_MIN_SLEEP_DURATION (12) /* threshold of interval in slots to allow to fall into modem sleep */ +#define BTDM_MODEM_WAKE_UP_DELAY (4) /* delay in slots of modem wake up procedure, including re-enable PHY/RF */ + +#define OSI_FUNCS_TIME_BLOCKING 0xffffffff +#define OSI_VERSION 0x00010004 +#define OSI_MAGIC_VALUE 0xfadebead + +#ifdef CONFIG_PM +# define BTDM_MIN_TIMER_UNCERTAINTY_US (500) #endif -#define BTDM_MODEM_SLEEP_MODE_NONE 0 +#define BTDM_ASYNC_WAKEUP_REQ_HCI 0 +#define BTDM_ASYNC_WAKEUP_REQ_COEX 1 +#define BTDM_ASYNC_WAKEUP_REQ_CTRL_DISA 2 +#define BTDM_ASYNC_WAKEUP_REQMAX 3 -#define ESP_BT_CONTROLLER_CONFIG_MAGIC_VAL 0x20200622 +#define MSG_QUEUE_NAME_SIZE 16 #ifdef CONFIG_ESP32_SPIFLASH -# define BLE_TASK_EVENT_QUEUE_ITEM_SIZE 8 -# define BLE_TASK_EVENT_QUEUE_LEN 8 +# define BLE_TASK_EVENT_QUEUE_ITEM_SIZE 8 +# define BLE_TASK_EVENT_QUEUE_LEN 8 #endif #ifdef CONFIG_ESP32_BLE_INTERRUPT_SAVE_STATUS @@ -118,13 +132,106 @@ do {\ # define NR_IRQSTATE_FLAGS 3 #endif +#define RTC_CLK_CAL_FRACT 19 /* Number of fractional bits in values returned by rtc_clk_cal */ + /**************************************************************************** * Private Types ****************************************************************************/ -/* Number of fractional bits in values returned by rtc_clk_cal */ +/* VHCI function interface */ + +typedef struct vhci_host_callback_s +{ + void (*notify_host_send_available)(void); /* callback used to notify that the host can send packet to controller */ + int (*notify_host_recv)(uint8_t *data, uint16_t len); /* callback used to notify that the controller has a packet to send to the host */ +} vhci_host_callback_t; + +/* Dram region */ + +typedef struct +{ + esp_bt_mode_t mode; + intptr_t start; + intptr_t end; +} btdm_dram_available_region_t; + +struct osi_funcs_s +{ + uint32_t _version; + xt_handler (*_set_isr)(int n, xt_handler f, void *arg); + void (*_ints_on)(unsigned int mask); + void (*_interrupt_disable)(void); + void (*_interrupt_restore)(void); + void (*_task_yield)(void); + void (*_task_yield_from_isr)(void); + void *(*_semphr_create)(uint32_t max, uint32_t init); + void (*_semphr_delete)(void *semphr); + int32_t (*_semphr_take_from_isr)(void *semphr, void *hptw); + int32_t (*_semphr_give_from_isr)(void *semphr, void *hptw); + int32_t (*_semphr_take)(void *semphr, uint32_t block_time_ms); + int32_t (*_semphr_give)(void *semphr); + void *(*_mutex_create)(void); + void (*_mutex_delete)(void *mutex); + int32_t (*_mutex_lock)(void *mutex); + int32_t (*_mutex_unlock)(void *mutex); + void *(* _queue_create)(uint32_t queue_len, uint32_t item_size); + void (* _queue_delete)(void *queue); + int32_t (* _queue_send)(void *queue, void *item, uint32_t block_time_ms); + int32_t (* _queue_send_from_isr)(void *queue, void *item, void *hptw); + int32_t (* _queue_recv)(void *queue, void *item, uint32_t block_time_ms); + int32_t (* _queue_recv_from_isr)(void *queue, void *item, void *hptw); + int32_t (* _task_create)(void *task_func, + const char *name, + uint32_t stack_depth, + void *param, + uint32_t prio, + void *task_handle, + uint32_t core_id); + void (* _task_delete)(void *task_handle); + bool (* _is_in_isr)(void); + int (* _cause_sw_intr_to_core)(int core_id, int intr_no); + void *(* _malloc)(size_t size); + void *(* _malloc_internal)(size_t size); + void (* _free)(void *p); + int32_t (* _read_efuse_mac)(uint8_t mac[6]); + void (* _srand)(unsigned int seed); + int (* _rand)(void); + uint32_t (* _btdm_lpcycles_2_us)(uint32_t cycles); + uint32_t (* _btdm_us_2_lpcycles)(uint32_t us); + bool (* _btdm_sleep_check_duration)(uint32_t *slot_cnt); + void (* _btdm_sleep_enter_phase1)(uint32_t lpcycles); /* called when interrupt is disabled */ + void (* _btdm_sleep_enter_phase2)(void); + void (* _btdm_sleep_exit_phase1)(void); /* called from ISR */ + void (* _btdm_sleep_exit_phase2)(void); /* called from ISR */ + void (* _btdm_sleep_exit_phase3)(void); /* called from task */ + bool (* _coex_bt_wakeup_request)(void); + void (* _coex_bt_wakeup_request_end)(void); + int (* _coex_bt_request)(uint32_t event, + uint32_t latency, + uint32_t duration); + int (* _coex_bt_release)(uint32_t event); + int (* _coex_register_bt_cb)(coex_func_cb_t cb); + uint32_t (* _coex_bb_reset_lock)(void); + void (* _coex_bb_reset_unlock)(uint32_t restore); + int (* _coex_schm_register_btdm_callback)(void *callback); + void (* _coex_schm_status_bit_clear)(uint32_t type, uint32_t status); + void (* _coex_schm_status_bit_set)(uint32_t type, uint32_t status); + uint32_t (* _coex_schm_interval_get)(void); + uint8_t (* _coex_schm_curr_period_get)(void); + void *(* _coex_schm_curr_phase_get)(void); + int (* _coex_wifi_channel_get)(uint8_t *primary, uint8_t *secondary); + int (* _coex_register_wifi_channel_change_callback)(void *cb); + xt_handler (*_set_isr_l3)(int n, xt_handler f, void *arg); + void (*_interrupt_l3_disable)(void); + void (*_interrupt_l3_restore)(void); + void *(* _customer_queue_create)(uint32_t queue_len, uint32_t item_size); + int (* _coex_version_get)(unsigned int *major, + unsigned int *minor, + unsigned int *patch); + uint32_t _magic; +}; -#define RTC_CLK_CAL_FRACT 19 +typedef void (*workitem_handler_t)(void *arg); /* BLE message queue private data */ @@ -143,27 +250,6 @@ struct irq_adpt_s void *arg; /* Interrupt private data */ }; -/* BLE low power control struct */ - -typedef struct btdm_lpcntl_s -{ - bool enable; /* whether low power mode is required */ - bool lpclk_sel; /* low power clock source */ - bool mac_bb_pd; /* whether hardware(MAC, BB) force-power-down is required during sleep */ - bool wakeup_timer_required; /* whether system timer is needed */ - bool no_light_sleep; /* do not allow system to enter light sleep after bluetooth is enabled */ -} btdm_lpcntl_t; - -/* low power control status */ - -typedef struct btdm_lpstat_s -{ - bool pm_lock_released; /* whether power management lock is released */ - bool mac_bb_pd; /* whether hardware(MAC, BB) is powered down */ - bool phy_enabled; /* whether phy is switched on */ - bool wakeup_timer_started; /* whether wakeup timer is started */ -} btdm_lpstat_t; - /* vendor dependent signals to be posted to controller task */ typedef enum @@ -194,139 +280,12 @@ struct bt_sem_s #endif }; -typedef enum -{ - PERIPH_LEDC_MODULE = 0, - PERIPH_UART0_MODULE, - PERIPH_UART1_MODULE, - PERIPH_UART2_MODULE, - PERIPH_I2C0_MODULE, - PERIPH_I2C1_MODULE, - PERIPH_I2S0_MODULE, - PERIPH_I2S1_MODULE, - PERIPH_TIMG0_MODULE, - PERIPH_TIMG1_MODULE, - PERIPH_PWM0_MODULE, - PERIPH_PWM1_MODULE, - PERIPH_PWM2_MODULE, - PERIPH_PWM3_MODULE, - PERIPH_UHCI0_MODULE, - PERIPH_UHCI1_MODULE, - PERIPH_RMT_MODULE, - PERIPH_PCNT_MODULE, - PERIPH_SPI_MODULE, - PERIPH_HSPI_MODULE, - PERIPH_VSPI_MODULE, - PERIPH_SPI_DMA_MODULE, - PERIPH_SDMMC_MODULE, - PERIPH_SDIO_SLAVE_MODULE, - PERIPH_CAN_MODULE, - PERIPH_EMAC_MODULE, - PERIPH_RNG_MODULE, - PERIPH_WIFI_MODULE, - PERIPH_BT_MODULE, - PERIPH_WIFI_BT_COMMON_MODULE, - PERIPH_BT_BASEBAND_MODULE, - PERIPH_BT_LC_MODULE, - PERIPH_AES_MODULE, - PERIPH_SHA_MODULE, - PERIPH_RSA_MODULE, -} periph_module_e; - /* prototype of function to handle vendor dependent signals */ typedef void (*btdm_vnd_ol_task_func_t)(void *param); -/* VHCI function interface */ - -typedef struct vhci_host_callback_s -{ - void (*notify_host_send_available)(void); /* callback used to notify that the host can send packet to controller */ - int (*notify_host_recv)(uint8_t *data, uint16_t len); /* callback used to notify that the controller has a packet to send to the host */ -} vhci_host_callback_t; - -/* DRAM region */ - -typedef struct btdm_dram_available_region_s -{ - esp_bt_mode_t mode; - intptr_t start; - intptr_t end; -} btdm_dram_available_region_t; - typedef void (*osi_intr_handler)(void); -/* BLE OS function */ - -struct osi_funcs_s -{ - uint32_t _version; - xt_handler (*_set_isr)(int n, xt_handler f, void *arg); - void (*_ints_on)(unsigned int mask); - void (*_interrupt_disable)(void); - void (*_interrupt_restore)(void); - void (*_task_yield)(void); - void (*_task_yield_from_isr)(void); - void *(*_semphr_create)(uint32_t max, uint32_t init); - void (*_semphr_delete)(void *semphr); - int32_t (*_semphr_take_from_isr)(void *semphr, void *hptw); - int32_t (*_semphr_give_from_isr)(void *semphr, void *hptw); - int32_t (*_semphr_take)(void *semphr, uint32_t block_time_ms); - int32_t (*_semphr_give)(void *semphr); - void *(*_mutex_create)(void); - void (*_mutex_delete)(void *mutex); - int32_t (*_mutex_lock)(void *mutex); - int32_t (*_mutex_unlock)(void *mutex); - void *(* _queue_create)(uint32_t queue_len, uint32_t item_size); - void (* _queue_delete)(void *queue); - int32_t (* _queue_send)(void *queue, void *item, uint32_t block_time_ms); - int32_t (* _queue_send_from_isr)(void *queue, void *item, void *hptw); - int32_t (* _queue_recv)(void *queue, void *item, uint32_t block_time_ms); - int32_t (* _queue_recv_from_isr)(void *queue, void *item, void *hptw); - int32_t (* _task_create)(void *task_func, - const char *name, - uint32_t stack_depth, - void *param, - uint32_t prio, - void *task_handle, - uint32_t core_id); - void (* _task_delete)(void *task_handle); - bool (* _is_in_isr)(void); - int (* _cause_sw_intr_to_core)(int core_id, int intr_no); - void *(* _malloc)(uint32_t size); - void *(* _malloc_internal)(uint32_t size); - void (* _free)(void *p); - int32_t (* _read_efuse_mac)(uint8_t mac[6]); - void (* _srand)(unsigned int seed); - int (* _rand)(void); - uint32_t (* _btdm_lpcycles_2_us)(uint32_t cycles); - uint32_t (* _btdm_us_2_lpcycles)(uint32_t us); - bool (* _btdm_sleep_check_duration)(uint32_t *slot_cnt); - void (* _btdm_sleep_enter_phase1)(uint32_t lpcycles); /* called when interrupt is disabled */ - void (* _btdm_sleep_enter_phase2)(void); - void (* _btdm_sleep_exit_phase1)(void); /* called from ISR */ - void (* _btdm_sleep_exit_phase2)(void); /* called from ISR */ - void (* _btdm_sleep_exit_phase3)(void); /* called from task */ - bool (* _coex_bt_wakeup_request)(void); - void (* _coex_bt_wakeup_request_end)(void); - int (* _coex_bt_request)(uint32_t event, - uint32_t latency, - uint32_t duration); - int (* _coex_bt_release)(uint32_t event); - int (* _coex_register_bt_cb)(coex_func_cb_t cb); - uint32_t (* _coex_bb_reset_lock)(void); - void (* _coex_bb_reset_unlock)(uint32_t restore); - int (* _coex_schm_register_btdm_callback)(void *callback); - void (* _coex_schm_status_bit_clear)(uint32_t type, uint32_t status); - void (* _coex_schm_status_bit_set)(uint32_t type, uint32_t status); - uint32_t (* _coex_schm_interval_get)(void); - uint8_t (* _coex_schm_curr_period_get)(void); - void *(* _coex_schm_curr_phase_get)(void); - int (* _coex_wifi_channel_get)(uint8_t *primary, uint8_t *secondary); - int (* _coex_register_wifi_channel_change_callback)(void *cb); - uint32_t _magic; -}; - /* List of nested IRQ status flags */ struct irqstate_list_s @@ -336,10 +295,22 @@ struct irqstate_list_s }; /**************************************************************************** - * Private Function + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Functions to be registered to struct osi_funcs_s ****************************************************************************/ -static xt_handler esp_ble_set_isr(int n, xt_handler f, void *arg); +/* Note: Functions name prefixed with `esp_` usually refers to the common + * source code shared between different devices. Avoid creating functions + * with the same prefix. Adding a different prefix, however, would differ + * this source from other devices. So, it's recommended to not use any kind + * of prefix to refer to the SoC. + */ + +static xt_handler ble_set_isr(int n, xt_handler f, void *arg); +static void ints_on(uint32_t mask); static void IRAM_ATTR interrupt_disable(void); static void IRAM_ATTR interrupt_restore(void); static void IRAM_ATTR task_yield_from_isr(void); @@ -347,68 +318,108 @@ static void *semphr_create_wrapper(uint32_t max, uint32_t init); static void semphr_delete_wrapper(void *semphr); static int IRAM_ATTR semphr_take_from_isr_wrapper(void *semphr, void *hptw); static int IRAM_ATTR semphr_give_from_isr_wrapper(void *semphr, void *hptw); -static int semphr_take_wrapper(void *semphr, uint32_t block_time_ms); -static int semphr_give_wrapper(void *semphr); +static int semphr_take_wrapper(void *semphr, uint32_t block_time_ms); +static int semphr_give_wrapper(void *semphr); static void *mutex_create_wrapper(void); static void mutex_delete_wrapper(void *mutex); -static int mutex_lock_wrapper(void *mutex); -static int mutex_unlock_wrapper(void *mutex); -static int IRAM_ATTR queue_send_from_isr_wrapper(void *queue, void *item, +static int mutex_lock_wrapper(void *mutex); +static int mutex_unlock_wrapper(void *mutex); +static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size); +static void queue_delete_wrapper(void *queue); +static int queue_send_wrapper(void *queue, + void *item, + uint32_t block_time_ms); +static int IRAM_ATTR queue_send_from_isr_wrapper(void *queue, + void *item, void *hptw); -static int IRAM_ATTR queue_recv_from_isr_wrapper(void *queue, void *item, +static int queue_recv_wrapper(void *queue, + void *item, + uint32_t block_time_ms); +static int IRAM_ATTR queue_recv_from_isr_wrapper(void *queue, + void *item, void *hptw); -static int task_create_wrapper(void *task_func, const char *name, - uint32_t stack_depth, void *param, - uint32_t prio, void *task_handle, +static int task_create_wrapper(void *task_func, + const char *name, + uint32_t stack_depth, + void *param, + uint32_t prio, + void *task_handle, uint32_t core_id); static void task_delete_wrapper(void *task_handle); static bool IRAM_ATTR is_in_isr_wrapper(void); -static void *malloc_wrapper(size_t size); -static void IRAM_ATTR cause_sw_intr(void *arg); static int IRAM_ATTR cause_sw_intr_to_core_wrapper(int core_id, int intr_no); +static void *malloc_wrapper(size_t size); static void *malloc_internal_wrapper(size_t size); static int IRAM_ATTR read_mac_wrapper(uint8_t mac[6]); static void IRAM_ATTR srand_wrapper(unsigned int seed); static int IRAM_ATTR rand_wrapper(void); static uint32_t IRAM_ATTR btdm_lpcycles_2_us(uint32_t cycles); static uint32_t IRAM_ATTR btdm_us_2_lpcycles(uint32_t us); -static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size); -static int queue_send_wrapper(void *queue, void *item, - uint32_t block_time_ms); -static int queue_recv_wrapper(void *queue, void *item, - uint32_t block_time_ms); -static void queue_delete_wrapper(void *queue); -static void esp32_ints_on(uint32_t mask); -static int adapter_coex_register_bt_cb_wrapper(coex_func_cb_t cb); -static int adapter_coex_schm_register_btdm_callback(void *callback); -static int adapter_coex_register_wifi_channel_change_callback(void *cb); -static int adapter_coex_wifi_channel_get(uint8_t *primary, - uint8_t *secondary); -static void adapter_coex_schm_status_bit_clear(uint32_t type, - uint32_t status); -static void adapter_coex_schm_status_bit_set(uint32_t type, uint32_t status); -static uint32_t adapter_coex_schm_interval_get(void); -static uint8_t adapter_coex_schm_curr_period_get(void); -static void *adapter_coex_schm_curr_phase_get(void); - -#ifdef CONFIG_PM -static bool IRAM_ATTR btdm_sleep_check_duration(int32_t *half_slot_cnt); +static bool IRAM_ATTR btdm_sleep_check_duration(uint32_t *slot_cnt); static void btdm_sleep_enter_phase1_wrapper(uint32_t lpcycles); static void btdm_sleep_enter_phase2_wrapper(void); static void btdm_sleep_exit_phase3_wrapper(void); -#endif - static bool coex_bt_wakeup_request(void); static void coex_bt_wakeup_request_end(void); -static int esp_int_adpt_cb(int irq, void *context, void *arg); +static int coex_bt_request_wrapper(uint32_t event, + uint32_t latency, + uint32_t duration); +static int coex_bt_release_wrapper(uint32_t event); +static int adapter_coex_register_bt_cb_wrapper(coex_func_cb_t cb); +static uint32_t coex_bb_reset_lock_wrapper(void); +static void coex_bb_reset_unlock_wrapper(uint32_t restore); +static int coex_schm_register_btdm_callback_wrapper(void *callback); +static void coex_schm_status_bit_clear_wrapper(uint32_t type, + uint32_t status); +static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status); +static uint32_t coex_schm_interval_get_wrapper(void); +static uint8_t coex_schm_curr_period_get_wrapper(void); +static void *coex_schm_curr_phase_get_wrapper(void); +static int coex_wifi_channel_get_wrapper(uint8_t *primary, + uint8_t *secondary); +static int coex_register_wifi_channel_change_callback_wrapper(void *cb); +static int coex_version_get_wrapper(unsigned int *major, + unsigned int *minor, + unsigned int *patch); + +/**************************************************************************** + * Other functions + ****************************************************************************/ + +static int32_t esp_task_create_pinned_to_core(void *entry, + const char *name, + uint32_t stack_depth, + void *param, + uint32_t prio, + void *task_handle, + uint32_t core_id); +static IRAM_ATTR int32_t esp_queue_send_generic(void *queue, + void *item, + uint32_t ticks, + int prio); +static void esp_update_time(struct timespec *timespec, uint32_t ticks); +static void IRAM_ATTR cause_sw_intr(void *arg); +#ifdef CONFIG_PM +static void btdm_slp_tmr_customer_callback(void * arg); +static void IRAM_ATTR btdm_slp_tmr_callback(void *arg); +#endif +static int IRAM_ATTR esp_int_adpt_cb(int irq, void *context, void *arg); +static void btdm_wakeup_request_callback(void * arg); +static void btdm_controller_mem_init(void); +static uint32_t btdm_config_mask_load(void); +static void bt_controller_deinit_internal(void); +static bool async_wakeup_request(int event); +static void async_wakeup_request_end(int event); /**************************************************************************** * Extern Functions declaration and value ****************************************************************************/ +/* Not for user call, so don't put to include file */ + +/* OSI */ + extern int btdm_osi_funcs_register(void *osi_funcs); -extern void btdm_controller_rom_data_init(void); -extern void coex_bt_high_prio(void); /* Initialise and De-initialise */ @@ -420,6 +431,9 @@ extern void btdm_controller_disable(void); extern uint8_t btdm_controller_get_mode(void); extern const char *btdm_controller_get_compile_version(void); extern void btdm_rf_bb_init_phase2(void); /* shall be called after PHY/RF is enabled */ +extern int btdm_dispatch_work_to_controller(workitem_handler_t callback, + void *arg, + bool blocking); /* Sleep */ @@ -427,14 +441,13 @@ extern void btdm_controller_enable_sleep(bool enable); extern void btdm_controller_set_sleep_mode(uint8_t mode); extern uint8_t btdm_controller_get_sleep_mode(void); extern bool btdm_power_state_active(void); -extern void btdm_wakeup_request(bool request_lock); -extern void btdm_wakeup_request_end(void); +extern void btdm_wakeup_request(void); +extern void btdm_in_wakeup_requesting_set(bool in_wakeup_requesting); /* Low Power Clock */ extern bool btdm_lpclk_select_src(uint32_t sel); extern bool btdm_lpclk_set_div(uint32_t div); -extern int btdm_hci_tl_io_event_post(int event); /* VHCI */ @@ -452,112 +465,41 @@ extern int bredr_txpwr_get(int *min_power_level, int *max_power_level); extern void bredr_sco_datapath_set(uint8_t data_path); extern void btdm_controller_scan_duplicate_list_clear(void); -/* Coexistence */ +/* Shutdown */ -int coex_bt_request_wrapper(uint32_t event, - uint32_t latency, - uint32_t duration); -int coex_bt_release_wrapper(uint32_t event); -uint32_t coex_bb_reset_lock_wrapper(void); -void coex_bb_reset_unlock_wrapper(uint32_t restore); -extern void coex_ble_adv_priority_high_set(bool high); -extern int coex_bt_request(uint32_t event, - uint32_t latency, - uint32_t duration); -extern int coex_bt_release(uint32_t event); -extern int coex_enable(void); -extern int coex_register_bt_cb(coex_func_cb_t cb); -extern int coex_schm_register_btdm_callback(void *callback); -extern int coex_register_wifi_channel_change_callback(void *cb); -extern int coex_wifi_channel_get(uint8_t *primary, - uint8_t *secondary); -extern int coex_register_bt_cb(coex_func_cb_t cb); -extern void coex_bb_reset_unlock(uint32_t restore); -extern uint32_t coex_bb_reset_lock(void); +extern void esp_bt_controller_shutdown(void); extern uint8_t _bss_start_btdm[]; extern uint8_t _bss_end_btdm[]; extern uint8_t _data_start_btdm[]; extern uint8_t _data_end_btdm[]; -extern const uint32_t _data_start_btdm_rom; -extern const uint32_t _data_end_btdm_rom; - -extern uint8_t _bt_bss_start[]; -extern uint8_t _bt_bss_end[]; -extern uint8_t _btdm_bss_start[]; -extern uint8_t _btdm_bss_end[]; -extern uint8_t _bt_data_start[]; -extern uint8_t _bt_data_end[]; -extern uint8_t _btdm_data_start[]; -extern uint8_t _btdm_data_end[]; - -extern uint8_t _bt_tmp_bss_start[]; -extern uint8_t _bt_tmp_bss_end[]; - -void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); +extern uint32_t _data_start_btdm_rom; +extern uint32_t _data_end_btdm_rom; + +extern uint32_t _bt_bss_start; +extern uint32_t _bt_bss_end; +extern uint32_t _nimble_bss_start; +extern uint32_t _nimble_bss_end; +extern uint32_t _btdm_bss_start; +extern uint32_t _btdm_bss_end; +extern uint32_t _bt_data_start; +extern uint32_t _bt_data_end; +extern uint32_t _nimble_data_start; +extern uint32_t _nimble_data_end; +extern uint32_t _btdm_data_start; +extern uint32_t _btdm_data_end; /**************************************************************************** * Private Data ****************************************************************************/ -/* Controller status */ - -static DRAM_ATTR esp_bt_controller_status_t btdm_controller_status = - ESP_BT_CONTROLLER_STATUS_IDLE; - -/* low power control struct */ - -static DRAM_ATTR btdm_lpcntl_t g_lp_cntl; - -/* low power status struct */ - -static DRAM_ATTR btdm_lpstat_t g_lp_stat; - -/* measured average low power clock period in micro seconds */ - -static DRAM_ATTR uint32_t g_btdm_lpcycle_us = 0; - -/* number of fractional bit for g_btdm_lpcycle_us */ - -static DRAM_ATTR uint8_t g_btdm_lpcycle_us_frac = 0; - -#ifdef CONFIG_PM -/* semaphore used for blocking VHCI API to wait for controller to wake up */ - -static DRAM_ATTR void * g_wakeup_req_sem = NULL; - -/* wakeup timer */ - -static DRAM_ATTR esp_timer_handle_t g_btdm_slp_tmr; -#endif - -/* BT interrupt private data */ - -static sq_queue_t g_int_flags_free; - -static sq_queue_t g_int_flags_used; - -static struct irqstate_list_s g_int_flags[NR_IRQSTATE_FLAGS]; - -/* Cached queue control variables */ - -#ifdef CONFIG_ESP32_SPIFLASH -static struct esp_queuecache_s g_esp_queuecache[BLE_TASK_EVENT_QUEUE_LEN]; -static uint8_t g_esp_queuecache_buffer[BLE_TASK_EVENT_QUEUE_ITEM_SIZE]; -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* BLE OS adapter data */ +/* OSI funcs */ -static struct osi_funcs_s g_osi_funcs = +static struct osi_funcs_s g_osi_funcs_ro = { - ._magic = OSI_MAGIC_VALUE, ._version = OSI_VERSION, - ._set_isr = esp_ble_set_isr, - ._ints_on = esp32_ints_on, + ._set_isr = ble_set_isr, + ._ints_on = ints_on, ._interrupt_disable = interrupt_disable, ._interrupt_restore = interrupt_restore, ._task_yield = task_yield_from_isr, @@ -590,38 +532,44 @@ static struct osi_funcs_s g_osi_funcs = ._rand = rand_wrapper, ._btdm_lpcycles_2_us = btdm_lpcycles_2_us, ._btdm_us_2_lpcycles = btdm_us_2_lpcycles, -#ifdef CONFIG_PM ._btdm_sleep_check_duration = btdm_sleep_check_duration, ._btdm_sleep_enter_phase1 = btdm_sleep_enter_phase1_wrapper, ._btdm_sleep_enter_phase2 = btdm_sleep_enter_phase2_wrapper, + ._btdm_sleep_exit_phase1 = NULL, + ._btdm_sleep_exit_phase2 = NULL, ._btdm_sleep_exit_phase3 = btdm_sleep_exit_phase3_wrapper, -#endif ._coex_bt_wakeup_request = coex_bt_wakeup_request, ._coex_bt_wakeup_request_end = coex_bt_wakeup_request_end, ._coex_bt_request = coex_bt_request_wrapper, ._coex_bt_release = coex_bt_release_wrapper, ._coex_register_bt_cb = adapter_coex_register_bt_cb_wrapper, - ._coex_register_wifi_channel_change_callback = - adapter_coex_register_wifi_channel_change_callback, - ._coex_wifi_channel_get = adapter_coex_wifi_channel_get, - ._coex_schm_status_bit_clear = adapter_coex_schm_status_bit_clear, - ._coex_schm_status_bit_set = adapter_coex_schm_status_bit_set, - ._coex_schm_interval_get = adapter_coex_schm_interval_get, - ._coex_schm_curr_period_get = adapter_coex_schm_curr_period_get, - ._coex_schm_curr_phase_get = adapter_coex_schm_curr_phase_get, - ._coex_schm_register_btdm_callback = - adapter_coex_schm_register_btdm_callback, ._coex_bb_reset_lock = coex_bb_reset_lock_wrapper, ._coex_bb_reset_unlock = coex_bb_reset_unlock_wrapper, + ._coex_schm_register_btdm_callback = + coex_schm_register_btdm_callback_wrapper, + ._coex_schm_status_bit_clear = coex_schm_status_bit_clear_wrapper, + ._coex_schm_status_bit_set = coex_schm_status_bit_set_wrapper, + ._coex_schm_interval_get = coex_schm_interval_get_wrapper, + ._coex_schm_curr_period_get = coex_schm_curr_period_get_wrapper, + ._coex_schm_curr_phase_get = coex_schm_curr_phase_get_wrapper, + ._coex_wifi_channel_get = coex_wifi_channel_get_wrapper, + ._coex_register_wifi_channel_change_callback = + coex_register_wifi_channel_change_callback_wrapper, + ._set_isr_l3 = ble_set_isr, + ._interrupt_l3_disable = interrupt_disable, + ._interrupt_l3_restore = interrupt_restore, + ._customer_queue_create = NULL, + ._coex_version_get = coex_version_get_wrapper, + ._magic = OSI_MAGIC_VALUE, }; -/* The mode column will be modified by release function to indicate the - * available region +/* The mode column will be modified by release function to indicate + * the available region. */ -static btdm_dram_available_region_t btdm_dram_available_region[] = +static btdm_dram_available_region_t g_btdm_dram_available_region[] = { - /* following is .data */ + /* The following is .data */ { ESP_BT_MODE_BTDM, @@ -629,7 +577,7 @@ static btdm_dram_available_region_t btdm_dram_available_region[] = SOC_MEM_BT_DATA_END }, - /* following is memory which HW will use */ + /* The following is memory which HW will use */ { ESP_BT_MODE_BTDM, @@ -652,7 +600,7 @@ static btdm_dram_available_region_t btdm_dram_available_region[] = SOC_MEM_BT_EM_BREDR_REAL_END }, - /* following is .bss */ + /* The following is .bss */ { ESP_BT_MODE_BTDM, @@ -666,212 +614,199 @@ static btdm_dram_available_region_t btdm_dram_available_region[] = }, }; -extern void btdm_controller_set_sleep_mode(uint8_t mode); +/* Reserve the full memory region used by Bluetooth Controller. + * Some may be released later at runtime. + */ -/**************************************************************************** - * Private Functions and Public Functions only used by libraries - ****************************************************************************/ +SOC_RESERVE_MEMORY_REGION(SOC_MEM_BT_EM_START, + SOC_MEM_BT_EM_BREDR_REAL_END, + rom_bt_em); +SOC_RESERVE_MEMORY_REGION(SOC_MEM_BT_BSS_START, + SOC_MEM_BT_BSS_END, + rom_bt_bss); +SOC_RESERVE_MEMORY_REGION(SOC_MEM_BT_MISC_START, + SOC_MEM_BT_MISC_END, + rom_bt_misc); +SOC_RESERVE_MEMORY_REGION(SOC_MEM_BT_DATA_START, + SOC_MEM_BT_DATA_END, + rom_bt_data); -static int adapter_coex_register_bt_cb_wrapper(coex_func_cb_t cb) -{ -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) - return coex_register_bt_cb(cb); -#else - return 0; -#endif -} +static DRAM_ATTR struct osi_funcs_s *g_osi_funcs_p; -static int adapter_coex_schm_register_btdm_callback(void *callback) -{ -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) - return coex_schm_register_btdm_callback(callback); -#else - return 0; -#endif -} +/* timestamp when PHY/RF was switched on */ -static int adapter_coex_register_wifi_channel_change_callback(void *cb) -{ -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) - return coex_register_wifi_channel_change_callback(cb); -#else - return -1; -#endif -} +static DRAM_ATTR int64_t g_time_phy_rf_just_enabled = 0; -static int adapter_coex_wifi_channel_get(uint8_t *primary, - uint8_t *secondary) -{ -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) - return coex_wifi_channel_get(primary, secondary); -#else - return -1; -#endif -} +static DRAM_ATTR esp_bt_controller_status_t g_btdm_controller_status = + ESP_BT_CONTROLLER_STATUS_IDLE; -static void adapter_coex_schm_status_bit_clear(uint32_t type, - uint32_t status) -{ -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) - coex_schm_status_bit_clear(type, status); -#endif -} +/* measured average low power clock period in micro seconds */ -static void adapter_coex_schm_status_bit_set(uint32_t type, uint32_t status) -{ -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) - coex_schm_status_bit_set(type, status); -#endif -} +static DRAM_ATTR uint32_t g_btdm_lpcycle_us = 0; -static uint32_t adapter_coex_schm_interval_get(void) -{ -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) - return coex_schm_interval_get(); -#else - return 0; -#endif -} +/* number of fractional bit for g_btdm_lpcycle_us */ + +static DRAM_ATTR uint8_t g_btdm_lpcycle_us_frac = 0; + +#ifdef CONFIG_BTDM_CTRL_MODEM_SLEEP_MODE_ORIG + +/* used low power clock */ + +static DRAM_ATTR uint8_t g_btdm_lpclk_sel; + +#endif /* CONFIG_BTDM_CTRL_MODEM_SLEEP_MODE_ORIG */ + +/* semaphore used for blocking VHCI API to wait for controller to wake up */ + +static DRAM_ATTR struct bt_sem_s * g_wakeup_req_sem = NULL; + +#ifdef CONFIG_PM + +/* wakeup timer */ + +static DRAM_ATTR esp_timer_handle_t g_btdm_slp_tmr; + +static bool g_pm_lock_acquired = true; + +static DRAM_ATTR bool g_btdm_allow_light_sleep; -static uint8_t adapter_coex_schm_curr_period_get(void) -{ -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) - return coex_schm_interval_get(); -#else - return 0; #endif -} -static void *adapter_coex_schm_curr_phase_get(void) -{ -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) - return coex_schm_curr_phase_get(); -#else - return NULL; +/* BT interrupt private data */ + +static sq_queue_t g_ble_int_flags_free; + +static sq_queue_t g_ble_int_flags_used; + +static struct irqstate_list_s g_ble_int_flags[NR_IRQSTATE_FLAGS]; + +/* Cached queue control variables */ + +#ifdef CONFIG_ESP32_SPIFLASH +static struct esp_queuecache_s g_esp_queuecache[BLE_TASK_EVENT_QUEUE_LEN]; +static uint8_t g_esp_queuecache_buffer[BLE_TASK_EVENT_QUEUE_ITEM_SIZE]; #endif -} + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ /**************************************************************************** * Name: esp_errno_trans * * Description: - * Transform from nuttx error code to Wi-Fi adapter error code + * Transform NuttX error code to a boolean value. Returns true if the + * input error code is 0 (no error), and false otherwise. * * Input Parameters: * ret - NuttX error code * * Returned Value: - * Wi-Fi adapter error code + * Boolean value indicating the absence (true) or presence (false) of an + * error * ****************************************************************************/ static inline int32_t esp_errno_trans(int ret) { if (!ret) - { - return true; - } + { + return true; + } else - { - return false; - } + { + return false; + } } /**************************************************************************** - * Name: esp_task_create_pinned_to_core + * Name: esp_bt_power_domain_on * * Description: - * Create task and bind it to target CPU, the task will run when it - * is created + * Power up the Bluetooth module. This function is a wrapper for the + * esp_wifi_bt_power_domain_on function. * * Input Parameters: - * entry - Task entry - * name - Task name - * stack_depth - Task stack size - * param - Task private data - * prio - Task priority - * task_handle - Task handle pointer which is used to pause, resume - * and delete the task - * core_id - CPU which the task runs in + * None * * Returned Value: - * True if success or false if fail + * None * ****************************************************************************/ -static int32_t esp_task_create_pinned_to_core(void *entry, - const char *name, - uint32_t stack_depth, - void *param, - uint32_t prio, - void *task_handle, - uint32_t core_id) +static inline void esp_bt_power_domain_on(void) { - int pid; -#ifdef CONFIG_SMP - int ret; - cpu_set_t cpuset; -#endif + esp_wifi_bt_power_domain_on(); +} - DEBUGASSERT(task_handle != NULL); +/**************************************************************************** + * Name: esp_bt_power_domain_off + * + * Description: + * Power down the Bluetooth module. This function is a wrapper for the + * esp_wifi_bt_power_domain_off function. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ -#ifdef CONFIG_SMP - ret = sched_lock(); - if (ret) - { - wlerr("Failed to lock scheduler before creating pinned thread\n"); - return false; - } -#endif +static inline void esp_bt_power_domain_off(void) +{ + esp_wifi_bt_power_domain_off(); +} - pid = kthread_create(name, prio, stack_depth, entry, - (char * const *)param); - if (pid > 0) - { - if (task_handle) - { - *((int *)task_handle) = pid; - } +/**************************************************************************** + * Name: btdm_check_and_init_bb + * + * Description: + * Check and initialize the Bluetooth baseband (BB). If the PHY/RF has + * been switched off since the last Bluetooth baseband initialization, it + * re-initializes the baseband. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ -#ifdef CONFIG_SMP - if (core_id < CONFIG_SMP_NCPUS) - { - CPU_ZERO(&cpuset); - CPU_SET(core_id, &cpuset); - ret = nxsched_set_affinity(pid, sizeof(cpuset), &cpuset); - if (ret) - { - wlerr("Failed to set affinity error=%d\n", ret); - return false; - } - } -#endif - } - else - { - wlerr("Failed to create task, error %d\n", pid); - } +static inline void btdm_check_and_init_bb(void) +{ + int64_t latest_ts = esp_phy_rf_get_on_ts(); -#ifdef CONFIG_SMP - ret = sched_unlock(); - if (ret) + if (latest_ts != g_time_phy_rf_just_enabled || + g_time_phy_rf_just_enabled == 0) { - wlerr("Failed to unlock scheduler after creating pinned thread\n"); - return false; + btdm_rf_bb_init_phase2(); + g_time_phy_rf_just_enabled = latest_ts; } -#endif - - return pid > 0; } /**************************************************************************** - * Name: esp_set_isr + * Functions to be registered to struct osi_funcs_s + ****************************************************************************/ + +/**************************************************************************** + * Name: ble_set_isr * * Description: * Register interrupt function * * Input Parameters: - * n - Interrupt ID + * n - CPU Interrupt ID * f - Interrupt function * arg - Function private data * @@ -880,7 +815,7 @@ static int32_t esp_task_create_pinned_to_core(void *entry, * ****************************************************************************/ -static xt_handler esp_ble_set_isr(int n, xt_handler f, void *arg) +static xt_handler ble_set_isr(int n, xt_handler f, void *arg) { int ret; uint32_t tmp; @@ -921,7 +856,7 @@ static xt_handler esp_ble_set_isr(int n, xt_handler f, void *arg) } /**************************************************************************** - * Name: esp32_ints_on + * Name: ints_on * * Description: * Enable BLE interrupt @@ -934,7 +869,7 @@ static xt_handler esp_ble_set_isr(int n, xt_handler f, void *arg) * ****************************************************************************/ -static void esp32_ints_on(uint32_t mask) +static void ints_on(uint32_t mask) { uint32_t bit; int irq; @@ -943,182 +878,17 @@ static void esp32_ints_on(uint32_t mask) { bit = 1 << i; if (bit & mask) - { - irq = esp32_getirq(0, i); - DEBUGVERIFY(esp32_irq_set_iram_isr(irq)); - up_enable_irq(irq); - wlinfo("Enabled bit %d\n", irq); - } + { + irq = esp32_getirq(0, i); + DEBUGVERIFY(esp32_irq_set_iram_isr(irq)); + up_enable_irq(irq); + wlinfo("Enabled bit %d\n", irq); + } } UNUSED(irq); } -/**************************************************************************** - * Name: is_wifi_clk_peripheral - * - * Description: - * Checks if the peripheral module needs Wi-Fi Clock. - * - * Input Parameters: - * periph - The peripheral module - * - * Returned Value: - * true if it depends on Wi-Fi clock or false otherwise. - * - ****************************************************************************/ - -static bool is_wifi_clk_peripheral(periph_module_e periph) -{ - /* A small subset of peripherals use WIFI_CLK_EN_REG and - * CORE_RST_EN_REG for their clock & reset registers - */ - - switch (periph) - { - case PERIPH_SDMMC_MODULE: - case PERIPH_SDIO_SLAVE_MODULE: - case PERIPH_EMAC_MODULE: - case PERIPH_RNG_MODULE: - case PERIPH_WIFI_MODULE: - case PERIPH_BT_MODULE: - case PERIPH_WIFI_BT_COMMON_MODULE: - case PERIPH_BT_BASEBAND_MODULE: - case PERIPH_BT_LC_MODULE: - return true; - default: - return false; - } -} - -/**************************************************************************** - * Name: get_clk_en_mask - * - * Description: - * Returns the WIFI_BT clock mask case it is BLE peripheral. - * - * Input Parameters: - * periph - The peripheral module - * - * Returned Value: - * The clock peripheral mask. - * - ****************************************************************************/ - -static uint32_t get_clk_en_mask(periph_module_e periph) -{ - switch (periph) - { - case PERIPH_BT_MODULE: - return DPORT_WIFI_CLK_BT_EN_M; - default: - return 0; - } -} - -/**************************************************************************** - * Name: get_rst_en_mask - * - * Description: - * Returns the WIFI_BT reset mask - * - * Input Parameters: - * periph - The peripheral module - * enable - Enable/Disable - * - * Returned Value: - * The reset peripheral mask. - * - ****************************************************************************/ - -static uint32_t get_rst_en_mask(periph_module_e periph, bool enable) -{ - return 0; -} - -/**************************************************************************** - * Name: get_clk_en_reg - * - * Description: - * Returns the WIFI_BT clock register - * - * Input Parameters: - * periph - The peripheral module - * - * Returned Value: - * The clock peripheral register. - * - ****************************************************************************/ - -static uint32_t get_clk_en_reg(periph_module_e periph) -{ - return is_wifi_clk_peripheral(periph) ? DPORT_WIFI_CLK_EN_REG : - DPORT_PERIP_CLK_EN_REG; -} - -/**************************************************************************** - * Name: get_rst_en_reg - * - * Description: - * Returns the WIFI_BT reset register - * - * Input Parameters: - * periph - The peripheral module - * - * Returned Value: - * The reset peripheral register. - * - ****************************************************************************/ - -static uint32_t get_rst_en_reg(periph_module_e periph) -{ - return is_wifi_clk_peripheral(periph) ? DPORT_CORE_RST_EN_REG : - DPORT_PERIP_RST_EN_REG; -} - -/**************************************************************************** - * Name: bt_periph_module_enable - * - * Description: - * Enable the bluetooth module - * - * Input Parameters: - * periph - The peripheral module - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void bt_periph_module_enable(periph_module_e periph) -{ - modifyreg32(get_clk_en_reg(periph), 0, get_clk_en_mask(periph)); - modifyreg32(get_rst_en_reg(periph), get_rst_en_mask(periph, true), 0); -} - -/**************************************************************************** - * Name: esp_int_adpt_cb - * - * Description: - * BT interrupt adapter callback function - * - * Input Parameters: - * arg - interrupt adapter private data - * - * Returned Value: - * NuttX error code - * - ****************************************************************************/ - -static int IRAM_ATTR esp_int_adpt_cb(int irq, void *context, void *arg) -{ - struct irq_adpt_s *adapter = (struct irq_adpt_s *)arg; - - adapter->func(adapter->arg); - - return OK; -} - /**************************************************************************** * Name: interrupt_disable * @@ -1138,13 +908,13 @@ static void IRAM_ATTR interrupt_disable(void) { struct irqstate_list_s *irqstate; - irqstate = (struct irqstate_list_s *)sq_remlast(&g_int_flags_free); + irqstate = (struct irqstate_list_s *)sq_remlast(&g_ble_int_flags_free); - DEBUGASSERT(irqstate != NULL); + ASSERT(irqstate != NULL); irqstate->flags = enter_critical_section(); - sq_addlast((sq_entry_t *)irqstate, &g_int_flags_used); + sq_addlast((sq_entry_t *)irqstate, &g_ble_int_flags_used); } /**************************************************************************** @@ -1166,13 +936,13 @@ static void IRAM_ATTR interrupt_restore(void) { struct irqstate_list_s *irqstate; - irqstate = (struct irqstate_list_s *)sq_remlast(&g_int_flags_used); + irqstate = (struct irqstate_list_s *)sq_remlast(&g_ble_int_flags_used); - DEBUGASSERT(irqstate != NULL); + ASSERT(irqstate != NULL); leave_critical_section(irqstate->flags); - sq_addlast((sq_entry_t *)irqstate, &g_int_flags_free); + sq_addlast((sq_entry_t *)irqstate, &g_ble_int_flags_free); } /**************************************************************************** @@ -1291,6 +1061,7 @@ static int IRAM_ATTR semphr_take_from_isr_wrapper(void *semphr, void *hptw) * * Input Parameters: * semphr - Semaphore data pointer + * hptw - Unused. * * Returned Value: * True if success or false if fail @@ -1319,36 +1090,6 @@ static int IRAM_ATTR semphr_give_from_isr_wrapper(void *semphr, void *hptw) return esp_errno_trans(ret); } -/**************************************************************************** - * Name: esp_update_time - * - * Description: - * Transform ticks to time and add this time to timespec value - * - * Input Parameters: - * ticks - System ticks - * - * Output Parameters: - * timespec - Input timespec data pointer - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp_update_time(struct timespec *timespec, uint32_t ticks) -{ - uint32_t tmp; - - tmp = TICK2SEC(ticks); - timespec->tv_sec += tmp; - - ticks -= SEC2TICK(tmp); - tmp = TICK2NSEC(ticks); - - timespec->tv_nsec += tmp; -} - /**************************************************************************** * Name: semphr_take_wrapper * @@ -1532,74 +1273,113 @@ static int mutex_unlock_wrapper(void *mutex) } /**************************************************************************** - * Name: esp_queue_send_generic + * Name: queue_create_wrapper * * Description: - * Generic send message to queue within a certain period of time + * Create message queue * * Input Parameters: - * queue - Message queue data pointer - * item - Message data pointer - * ticks - Wait ticks - * prio - Message priority + * queue_len - queue message number + * item_size - message size * * Returned Value: - * True if success or false if fail + * Message queue data pointer * ****************************************************************************/ -static IRAM_ATTR int32_t esp_queue_send_generic(void *queue, void *item, - uint32_t ticks, int prio) +static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size) { - int ret; - struct timespec timeout; - struct mq_adpt_s *mq_adpt = (struct mq_adpt_s *)queue; + struct mq_attr attr; + struct mq_adpt_s *mq_adpt; + int ret; -#ifdef CONFIG_ESP32_SPIFLASH - if (!spi_flash_cache_enabled()) + mq_adpt = kmm_malloc(sizeof(struct mq_adpt_s)); + DEBUGASSERT(mq_adpt); + + snprintf(mq_adpt->name, sizeof(mq_adpt->name), "/tmp/%p", mq_adpt); + + attr.mq_maxmsg = queue_len; + attr.mq_msgsize = item_size; + attr.mq_curmsgs = 0; + attr.mq_flags = 0; + + ret = file_mq_open(&mq_adpt->mq, mq_adpt->name, + O_RDWR | O_CREAT, 0644, &attr); + + if (ret < 0) { - esp_send_queuecache(queue, item, mq_adpt->msgsize); - return esp_errno_trans(OK); + wlerr("Failed to create mqueue %d\n", ret); + kmm_free(mq_adpt); + return NULL; } -#endif - if (ticks == OSI_FUNCS_TIME_BLOCKING || ticks == 0) - { - /* BLE interrupt function will call this adapter function to send - * message to message queue, so here we should call kernel API - * instead of application API - */ + mq_adpt->msgsize = item_size; - ret = file_mq_send(&mq_adpt->mq, (const char *)item, - mq_adpt->msgsize, prio); - if (ret < 0) - { - wlerr("Failed to send message to mqueue error=%d\n", ret); - } +#ifdef CONFIG_ESP32_SPIFLASH + if (queue_len <= BLE_TASK_EVENT_QUEUE_LEN && + item_size == BLE_TASK_EVENT_QUEUE_ITEM_SIZE) + { + esp_init_queuecache(g_esp_queuecache, + &mq_adpt->mq, + g_esp_queuecache_buffer, + BLE_TASK_EVENT_QUEUE_LEN, + BLE_TASK_EVENT_QUEUE_ITEM_SIZE); } else { - ret = clock_gettime(CLOCK_REALTIME, &timeout); - if (ret < 0) - { - wlerr("Failed to get time %d\n", ret); - return esp_errno_trans(ret); - } + wlerr("Failed to create queue cache." + " Please incresase BLE_TASK_EVENT_QUEUE_LEN to, at least, %d", + queue_len); + return NULL; + } +#endif - if (ticks) - { - esp_update_time(&timeout, ticks); - } + return (void *)mq_adpt; +} - ret = file_mq_timedsend(&mq_adpt->mq, (const char *)item, - mq_adpt->msgsize, prio, &timeout); - if (ret < 0) - { - wlerr("Failed to timedsend message to mqueue error=%d\n", ret); - } - } +/**************************************************************************** + * Name: queue_delete_wrapper + * + * Description: + * Delete message queue + * + * Input Parameters: + * queue - Message queue data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ - return esp_errno_trans(ret); +static void queue_delete_wrapper(void *queue) +{ + struct mq_adpt_s *mq_adpt = (struct mq_adpt_s *)queue; + + file_mq_close(&mq_adpt->mq); + file_mq_unlink(mq_adpt->name); + kmm_free(mq_adpt); +} + +/**************************************************************************** + * Name: queue_send_wrapper + * + * Description: + * Generic send message to queue within a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Item to be sent. + * block_time_ms - Wait time + * + * Returned Value:uint32_t + * True if success or false if fail + * + ****************************************************************************/ + +static int queue_send_wrapper(void *queue, void *item, + uint32_t block_time_ms) +{ + return esp_queue_send_generic(queue, item, block_time_ms, 0); } /**************************************************************************** @@ -1627,6 +1407,67 @@ static int IRAM_ATTR queue_send_from_isr_wrapper(void *queue, return esp_queue_send_generic(queue, item, 0, 0); } +/**************************************************************************** + * Name: queue_recv_wrapper + * + * Description: + * Receive message from queue within a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * block_time_ms - Wait time + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int queue_recv_wrapper(void *queue, void *item, + uint32_t block_time_ms) +{ + ssize_t ret; + struct timespec timeout; + unsigned int prio; + struct mq_adpt_s *mq_adpt = (struct mq_adpt_s *)queue; + + if (block_time_ms == OSI_FUNCS_TIME_BLOCKING) + { + ret = file_mq_receive(&mq_adpt->mq, (char *)item, + mq_adpt->msgsize, &prio); + + if (ret < 0) + { + wlerr("Failed to receive from mqueue error=%d\n", ret); + } + } + else + { + ret = clock_gettime(CLOCK_REALTIME, &timeout); + + if (ret < 0) + { + wlerr("Failed to get time %d\n", ret); + return false; + } + + if (block_time_ms) + { + esp_update_time(&timeout, MSEC2TICK(block_time_ms)); + } + + ret = file_mq_timedreceive(&mq_adpt->mq, (char *)item, + mq_adpt->msgsize, &prio, &timeout); + + if (ret < 0) + { + wlerr("Failed to timedreceive from mqueue error=%d\n", ret); + } + } + + return ret > 0 ? true : false; +} + /**************************************************************************** * Name: queue_recv_from_isr_wrapper * @@ -1636,7 +1477,7 @@ static int IRAM_ATTR queue_send_from_isr_wrapper(void *queue, * Input Parameters: * queue - Message queue data pointer * item - Message data pointer - * hptw - Unused + * hptw - Unused * * Returned Value: * True if success or false if fail @@ -1706,85 +1547,64 @@ static void task_delete_wrapper(void *task_handle) * Name: is_in_isr_wrapper * * Description: + * Check current is in interrupt * * Input Parameters: - * None + * None * * Returned Value: - * None + * true if in interrupt or false if not * ****************************************************************************/ static bool IRAM_ATTR is_in_isr_wrapper(void) { - return false; + return up_interrupt_context(); } /**************************************************************************** - * Name: malloc_wrapper + * Name: cause_sw_intr_to_core_wrapper * * Description: - * Malloc buffer + * Just a wrapper to cause_sw_intr * * Input Parameters: - * size - buffer size + * core_id - ID of the CPU core, not used. + * intr_no - Number of the software interrupt * * Returned Value: - * None + * Always return OK. * ****************************************************************************/ -static void *malloc_wrapper(size_t size) +static int IRAM_ATTR cause_sw_intr_to_core_wrapper(int core_id, int intr_no) { - void * p = NULL; - - p = kmm_malloc(size); - DEBUGASSERT(p); - - return p; + cause_sw_intr((void *)intr_no); + return ESP_OK; } /**************************************************************************** - * Name: cause_sw_intr + * Name: malloc_wrapper * * Description: - * Set a software interrupt bit + * Malloc buffer * * Input Parameters: - * arg - number of the bit as void pointer + * size - buffer size * * Returned Value: * None * ****************************************************************************/ -static void IRAM_ATTR cause_sw_intr(void *arg) +static void *malloc_wrapper(size_t size) { - /* just convert void * to int, because the width is the same */ - - uint32_t intr_no = (uint32_t)arg; - XTHAL_SET_INTSET((1 << intr_no)); -} + void * p = NULL; -/**************************************************************************** - * Name: cause_sw_intr_to_core_wrapper - * - * Description: - * Just a wrapper to cause_sw_intr - * - * Input Parameters: - * core_id - ID of the CPU core, not used. - * intr_no - Number of the software interrupt - * - * Returned Value: - * Always return OK. - * - ****************************************************************************/ + p = kmm_malloc(size); + DEBUGASSERT(p); -static int IRAM_ATTR cause_sw_intr_to_core_wrapper(int core_id, int intr_no) -{ - cause_sw_intr((void *)intr_no); - return ESP_OK; + return p; } /**************************************************************************** @@ -1818,10 +1638,10 @@ static void *malloc_internal_wrapper(size_t size) * Get Mac Address * * Input Parameters: - * mac - mac address + * mac - mac address * * Returned Value: - * None + * Zero (OK) is returned on success. Otherwise, -1 (ERROR) is returned. * ****************************************************************************/ @@ -1834,9 +1654,10 @@ static int IRAM_ATTR read_mac_wrapper(uint8_t mac[6]) * Name: srand_wrapper * * Description: + * Get random value with seed input. Not implemented. * * Input Parameters: - * None + * seed - Value to be used as seed. * * Returned Value: * None @@ -1852,10 +1673,10 @@ static void IRAM_ATTR srand_wrapper(unsigned int seed) * Name: rand_wrapper * * Description: - * Get random value. + * Get random value. * * Input Parameters: - * None + * None * * Returned Value: * Random value @@ -1864,7 +1685,7 @@ static void IRAM_ATTR srand_wrapper(unsigned int seed) static int IRAM_ATTR rand_wrapper(void) { - return getreg32(WDEV_RND_REG); + return esp_random(); } /**************************************************************************** @@ -1877,12 +1698,16 @@ static int IRAM_ATTR rand_wrapper(void) * cycles - number of CPU cycles * * Returned Value: - * us - value equivalent to the CPU cycles + * us - value equivalent to the CPU cycles in us * ****************************************************************************/ static uint32_t IRAM_ATTR btdm_lpcycles_2_us(uint32_t cycles) { + /* The number of lp cycles should not lead to overflow. Thrs: 100s + * clock measurement is conducted + */ + uint64_t us = (uint64_t)g_btdm_lpcycle_us * cycles; us = (us + (1 << (g_btdm_lpcycle_us_frac - 1))) >> g_btdm_lpcycle_us_frac; return (uint32_t)us; @@ -1892,10 +1717,10 @@ static uint32_t IRAM_ATTR btdm_lpcycles_2_us(uint32_t cycles) * Name: btdm_us_2_lpcycles * * Description: - * Converts a duration in half us into a number of low power clock cycles. + * Converts a duration in slots into a number of low power clock cycles. * * Input Parameters: - * us + * us - duration in us * * Returned Value: * cycles @@ -1904,101 +1729,40 @@ static uint32_t IRAM_ATTR btdm_lpcycles_2_us(uint32_t cycles) static uint32_t IRAM_ATTR btdm_us_2_lpcycles(uint32_t us) { + /* The number of sleep duration(us) should not lead to overflow. Thrs: 100s + * Compute the sleep duration in us to low power clock cycles, with + * calibration result applied clock measurement is conducted + */ + uint64_t cycles; cycles = ((uint64_t)(us) << g_btdm_lpcycle_us_frac) / g_btdm_lpcycle_us; return (uint32_t)cycles; } -#ifdef CONFIG_PM /**************************************************************************** - * Name: btdm_sleep_exit_phase0 + * Name: btdm_sleep_check_duration * * Description: - * Acquire PM lock and stop esp timer. + * Wake up in advance considering the delay in enabling PHY/RF. * * Input Parameters: - * param - wakeup event + * half_slot_cnt - half slots to allow to fall into modem sleep * * Returned Value: * None * ****************************************************************************/ -static void IRAM_ATTR btdm_sleep_exit_phase0(void *param) +static bool IRAM_ATTR btdm_sleep_check_duration(uint32_t *slot_cnt) { - int event = (int)param; - - DEBUGASSERT(g_lp_cntl.enable == true); - - if (g_lp_stat.pm_lock_released) + if (*slot_cnt < BTDM_MIN_SLEEP_DURATION) { - esp32_pm_lockacquire(); - g_lp_stat.pm_lock_released = false; + return false; } - if (event == BTDM_ASYNC_WAKEUP_SRC_VHCI || - event == BTDM_ASYNC_WAKEUP_SRC_DISA) - { - btdm_wakeup_request(); - } - - if (g_lp_cntl.wakeup_timer_required && g_lp_stat.wakeup_timer_started) - { - esp_timer_stop(g_btdm_slp_tmr); - g_lp_stat.wakeup_timer_started = false; - } - - if (event == BTDM_ASYNC_WAKEUP_SRC_VHCI || - event == BTDM_ASYNC_WAKEUP_SRC_DISA) - { - semphr_give_wrapper(g_wakeup_req_sem); - } -} - -/**************************************************************************** - * Name: btdm_slp_tmr_callback - * - * Description: - * ESP BLE sleep callback function. - * - * Input Parameters: - * arg - Unused - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR btdm_slp_tmr_callback(void *arg) -{ - btdm_vnd_offload_post(BTDM_VND_OL_SIG_WAKEUP_TMR, - (void *)BTDM_ASYNC_WAKEUP_SRC_TMR); -} - -/**************************************************************************** - * Name: btdm_sleep_check_duration - * - * Description: - * Wake up in advance considering the delay in enabling PHY/RF. - * - * Input Parameters: - * half_slot_cnt - half slots to allow to fall into modem sleep - * - * Returned Value: - * None - * - ****************************************************************************/ - -static bool IRAM_ATTR btdm_sleep_check_duration(int32_t *half_slot_cnt) -{ - if (*half_slot_cnt < BTDM_MIN_SLEEP_DURATION) - { - return false; - } - - *half_slot_cnt -= BTDM_MODEM_WAKE_UP_DELAY; - return true; -} + *slot_cnt -= BTDM_MODEM_WAKE_UP_DELAY; + return true; +} /**************************************************************************** * Name: btdm_sleep_enter_phase1_wrapper @@ -2016,6 +1780,7 @@ static bool IRAM_ATTR btdm_sleep_check_duration(int32_t *half_slot_cnt) static void btdm_sleep_enter_phase1_wrapper(uint32_t lpcycles) { +#ifdef CONFIG_PM uint32_t us_to_sleep; uint32_t uncertainty; @@ -2048,6 +1813,7 @@ static void btdm_sleep_enter_phase1_wrapper(uint32_t lpcycles) wlerr("timer start failed"); DEBUGPANIC(); } +#endif } /**************************************************************************** @@ -2066,23 +1832,24 @@ static void btdm_sleep_enter_phase1_wrapper(uint32_t lpcycles) static void btdm_sleep_enter_phase2_wrapper(void) { - if (btdm_controller_get_sleep_mode() == ESP_BT_SLEEP_MODE_1) + if (btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_ORIG) { - if (g_lp_stat.phy_enabled) - { - bt_phy_disable(); - g_lp_stat.phy_enabled = false; - } - else - { - DEBUGPANIC(); - } - - if (g_lp_stat.pm_lock_released == false) + esp_phy_disable(); +#ifdef CONFIG_PM + if (g_pm_lock_acquired) { esp32_pm_lockrelease(); - g_lp_stat.pm_lock_released = true; + g_pm_lock_acquired = false; } +#endif + } + else if (btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_EVED) + { + esp_phy_disable(); + + /* pause bluetooth baseband */ + + periph_module_disable(PERIPH_BT_BASEBAND_MODULE); } } @@ -2100,328 +1867,803 @@ static void btdm_sleep_enter_phase2_wrapper(void) * ****************************************************************************/ -static void btdm_sleep_exit_phase3_wrapper(void) +void btdm_sleep_exit_phase3_wrapper(void) { - if (g_lp_stat.pm_lock_released) +#ifdef CONFIG_PM + if (g_pm_lock_acquired == false) { + g_pm_lock_acquired = true; esp32_pm_lockacquire(); - g_lp_stat.pm_lock_released = false; } +#endif - if (btdm_sleep_clock_sync()) + if (btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_ORIG) { - wlerr("sleep eco state err\n"); - DEBUGPANIC(); + esp_phy_enable(); + btdm_check_and_init_bb(); +#ifdef CONFIG_PM + esp_timer_stop(g_btdm_slp_tmr); +#endif } - - if (btdm_controller_get_sleep_mode() == ESP_BT_SLEEP_MODE_1) + else if (btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_EVED) { - if (g_lp_stat.phy_enabled == false) - { - bt_phy_enable(); - g_lp_stat.phy_enabled = true; - } - } + /* resume bluetooth baseband */ - if (g_lp_cntl.wakeup_timer_required && g_lp_stat.wakeup_timer_started) - { - esp_timer_stop(g_btdm_slp_tmr); - g_lp_stat.wakeup_timer_started = false; + periph_module_enable(PERIPH_BT_BASEBAND_MODULE); + esp_phy_enable(); } } -#endif /**************************************************************************** - * Name: btdm_controller_mem_init + * Name: coex_bt_wakeup_request * * Description: - * Initialize BT controller to allocate task and other resource. + * Request a Wi-Fi/BLE Coex wakeup request + * * Input Parameters: - * None + * none * * Returned Value: - * None + * true if request lock is needed, false otherwise * ****************************************************************************/ -static void btdm_controller_mem_init(void) +static bool coex_bt_wakeup_request(void) { - int btdm_dram_regions; - - /* initialise .data section */ - - memcpy(_data_start_btdm, (void *)_data_start_btdm_rom, - _data_end_btdm - _data_start_btdm); - - wlinfo(".data initialise [0x%08x] <== [0x%08x]\n", - (uint32_t)_data_start_btdm, _data_start_btdm_rom); - - /* initial em, .bss section */ - - btdm_dram_regions = sizeof(btdm_dram_available_region) - / sizeof(btdm_dram_available_region_t); - - for (int i = 1; i < btdm_dram_regions; i++) - { - if (btdm_dram_available_region[i].mode != ESP_BT_MODE_IDLE) - { - memset((void *)btdm_dram_available_region[i].start, 0x0, - btdm_dram_available_region[i].end - \ - btdm_dram_available_region[i].start); - wlinfo(".bss initialise [0x%08x] - [0x%08x]\n", - btdm_dram_available_region[i].start, - btdm_dram_available_region[i].end); - } - } + return async_wakeup_request(BTDM_ASYNC_WAKEUP_REQ_COEX); } /**************************************************************************** - * Name: phy_printf_ble + * Name: coex_bt_wakeup_request_end * * Description: - * Output format string and its arguments + * Finish Wi-Fi/BLE Coex wakeup request * * Input Parameters: - * format - format string + * none * * Returned Value: - * 0 + * none * ****************************************************************************/ -int phy_printf_ble(const char *format, ...) +static void coex_bt_wakeup_request_end(void) { -#ifdef CONFIG_DEBUG_WIRELESS_INFO - va_list arg; + async_wakeup_request_end(BTDM_ASYNC_WAKEUP_REQ_COEX); +} - va_start(arg, format); - vsyslog(LOG_INFO, format, arg); - va_end(arg); -#endif +/**************************************************************************** + * Name: coex_bt_request_wrapper + * + * Description: + * Bluetooth requests coexistence. + * + * Input Parameters: + * event - Bluetooth event + * latency - Bluetooth will request coexistence after latency + * duration - duration for Bluetooth to request coexistence + * + * Returned Value: + * 0 on success, other values indicate failure + * + ****************************************************************************/ +static int IRAM_ATTR coex_bt_request_wrapper(uint32_t event, + uint32_t latency, + uint32_t duration) +{ +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + return coex_bt_request(event, latency, duration); +#else return 0; +#endif } -int coexist_printf(const char *format, ...) -{ -#ifdef CONFIG_DEBUG_WIRELESS_INFO - va_list arg; - - va_start(arg, format); - vsyslog(LOG_INFO, format, arg); - va_end(arg); -#endif +/**************************************************************************** + * Name: coex_bt_release_wrapper + * + * Description: + * Bluetooth releases coexistence. + * + * Input Parameters: + * event - Bluetooth event + * + * Returned Value: + * 0 on success, other values indicate failure + * + ****************************************************************************/ +static int IRAM_ATTR coex_bt_release_wrapper(uint32_t event) +{ +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + return coex_bt_release(event); +#else return 0; +#endif } /**************************************************************************** - * Name: bt_phy_disable + * Name: adapter_coex_register_bt_cb_wrapper * * Description: - * Disable BT phy. + * Bluetooth registers callback function to coexistence module. + * This function is only used on ESP32. * * Input Parameters: - * None + * cb - callback function registered to coexistence module * * Returned Value: - * None + * 0 on success, other values indicate failure * ****************************************************************************/ -static void bt_phy_disable(void) +static int adapter_coex_register_bt_cb_wrapper(coex_func_cb_t cb) { - esp32_phy_disable(); +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + return coex_register_bt_cb(cb); +#else + return 0; +#endif } /**************************************************************************** - * Name: bt_phy_enable + * Name: coex_bb_reset_lock_wrapper * * Description: - * Enable BT phy. + * To acquire the spin-lock used in resetting Bluetooth baseband. + * This function is only used to workaround ESP32 hardware issue. * * Input Parameters: - * None + * None * * Returned Value: - * None + * Value of the spinlock to be restored * ****************************************************************************/ -static void bt_phy_enable(void) +static uint32_t IRAM_ATTR coex_bb_reset_lock_wrapper(void) { - esp32_phy_enable(); +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + return coex_bb_reset_lock(); +#else + return 0; +#endif } /**************************************************************************** - * Name: queue_create_wrapper + * Name: coex_bb_reset_unlock_wrapper * * Description: - * Create message queue + * To release the spin-lock used in resetting Bluetooth baseband. + * This function is only used to workaround ESP32 hardware issue. * * Input Parameters: - * queue_len - queue message number - * item_size - message size + * restore - value of the spinlock returned from previous call of + * coex_bb_rest_lock * * Returned Value: - * Message queue data pointer + * None * ****************************************************************************/ -static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size) +static void IRAM_ATTR coex_bb_reset_unlock_wrapper(uint32_t restore) { - struct mq_attr attr; - struct mq_adpt_s *mq_adpt; - int ret; - - mq_adpt = kmm_malloc(sizeof(struct mq_adpt_s)); - DEBUGASSERT(mq_adpt); - - snprintf(mq_adpt->name, sizeof(mq_adpt->name), "/tmp/%p", mq_adpt); - - attr.mq_maxmsg = queue_len; - attr.mq_msgsize = item_size; - attr.mq_curmsgs = 0; - attr.mq_flags = 0; - - ret = file_mq_open(&mq_adpt->mq, mq_adpt->name, - O_RDWR | O_CREAT, 0644, &attr); - - if (ret < 0) - { - wlerr("Failed to create mqueue %d\n", ret); - kmm_free(mq_adpt); - return NULL; - } +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + coex_bb_reset_unlock(restore); +#endif +} - mq_adpt->msgsize = item_size; +/**************************************************************************** + * Name: coex_schm_register_btdm_callback_wrapper + * + * Description: + * Register callback for coexistence scheme. + * + * Input Parameters: + * callback - callback function to be registered + * + * Returned Value: + * 0 on success, other values indicate failure + * + ****************************************************************************/ -#ifdef CONFIG_ESP32_SPIFLASH - if (queue_len <= BLE_TASK_EVENT_QUEUE_LEN && - item_size == BLE_TASK_EVENT_QUEUE_ITEM_SIZE) - { - esp_init_queuecache(g_esp_queuecache, - &mq_adpt->mq, - g_esp_queuecache_buffer, - BLE_TASK_EVENT_QUEUE_LEN, - BLE_TASK_EVENT_QUEUE_ITEM_SIZE); - } - else - { - wlerr("Failed to create queue cache." - " Please incresase BLE_TASK_EVENT_QUEUE_LEN to, at least, %d", - queue_len); - return NULL; - } +static int coex_schm_register_btdm_callback_wrapper(void *callback) +{ +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + return coex_schm_register_callback(COEX_SCHM_CALLBACK_TYPE_BT, callback); +#else + return 0; #endif - - return (void *)mq_adpt; } /**************************************************************************** - * Name: queue_send_wrapper + * Name: coex_schm_status_bit_clear_wrapper * * Description: - * Generic send message to queue within a certain period of time + * Clear coexistence status. * * Input Parameters: - * queue - Message queue data pointer - * item - Item to be sent. - * block_time_ms - Wait time + * type - Coexistence status type + * status - Coexistence status * - * Returned Value:uint32_t - * True if success or false if fail + * Returned Value: + * None * ****************************************************************************/ -static int queue_send_wrapper(void *queue, void *item, - uint32_t block_time_ms) +static void coex_schm_status_bit_clear_wrapper(uint32_t type, + uint32_t status) { - return esp_queue_send_generic(queue, item, block_time_ms, 0); +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + coex_schm_status_bit_clear(type, status); +#endif } /**************************************************************************** - * Name: queue_recv_wrapper + * Name: coex_schm_status_bit_set_wrapper * * Description: - * Receive message from queue within a certain period of time + * Set coexistence status. * * Input Parameters: - * queue - Message queue data pointer - * item - Message data pointer - * block_time_ms - Wait time + * type - Coexistence status type + * status - Coexistence status * * Returned Value: - * True if success or false if fail + * None * ****************************************************************************/ -static int queue_recv_wrapper(void *queue, void *item, - uint32_t block_time_ms) +static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status) { - ssize_t ret; - struct timespec timeout; - unsigned int prio; - struct mq_adpt_s *mq_adpt = (struct mq_adpt_s *)queue; +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + coex_schm_status_bit_set(type, status); +#endif +} - if (block_time_ms == OSI_FUNCS_TIME_BLOCKING) +/**************************************************************************** + * Name: coex_schm_interval_get_wrapper + * + * Description: + * Get coexistence scheme interval. + * + * Input Parameters: + * None + * + * Returned Value: + * Coexistence scheme interval + * + ****************************************************************************/ + +static uint32_t coex_schm_interval_get_wrapper(void) +{ +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + return coex_schm_interval_get(); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_schm_curr_period_get_wrapper + * + * Description: + * Get current coexistence scheme period. + * + * Input Parameters: + * None + * + * Returned Value: + * Coexistence scheme period + * + ****************************************************************************/ + +static uint8_t coex_schm_curr_period_get_wrapper(void) +{ +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + return coex_schm_interval_get(); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_schm_curr_phase_get_wrapper + * + * Description: + * Get current coexistence scheme phase. + * + * Input Parameters: + * None + * + * Returned Value: + * Coexistence scheme phase + * + ****************************************************************************/ + +static void *coex_schm_curr_phase_get_wrapper(void) +{ +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + return coex_schm_curr_phase_get(); +#else + return NULL; +#endif +} + +/**************************************************************************** + * Name: coex_wifi_channel_get_wrapper + * + * Description: + * Get WiFi channel from coexistence module. + * + * Input Parameters: + * primary - pointer to value of WiFi primary channel + * secondary - pointer to value of WiFi secondary channel + * + * Returned Value: + * 0 on success, other values indicate failure + * + ****************************************************************************/ + +static int coex_wifi_channel_get_wrapper(uint8_t *primary, + uint8_t *secondary) +{ +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + return coex_wifi_channel_get(primary, secondary); +#else + return -1; +#endif +} + +/**************************************************************************** + * Name: coex_register_wifi_channel_change_callback_wrapper + * + * Description: + * Bluetooth registers callback function to receive notification when Wi-Fi + * channel changes. + * + * Input Parameters: + * cb - callback function registered to coexistence module + * + * Returned Value: + * 0 on success, other values indicate failure + * + ****************************************************************************/ + +static int coex_register_wifi_channel_change_callback_wrapper(void *cb) +{ +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + return coex_register_wifi_channel_change_callback(cb); +#else + return -1; +#endif +} + +/**************************************************************************** + * Name: coex_version_get_wrapper + * + * Description: + * Get the version of the coexistence module. + * + * Input Parameters: + * major - pointer to store the major version number + * minor - pointer to store the minor version number + * patch - pointer to store the patch version number + * + * Returned Value: + * 0 on success, -1 on failure + * + ****************************************************************************/ + +static int coex_version_get_wrapper(unsigned int *major, + unsigned int *minor, + unsigned int *patch) +{ +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + const char *ver_str = coex_version_get(); + + if (ver_str != NULL) { - ret = file_mq_receive(&mq_adpt->mq, (char *)item, - mq_adpt->msgsize, &prio); + unsigned int _major = 0; + unsigned int _minor = 0; + unsigned int _patch = 0; + + if (sscanf(ver_str, "%u.%u.%u", &_major, &_minor, &_patch) != 3) + { + return -1; + } + + if (major != NULL) + { + *major = _major; + } + + if (minor != NULL) + { + *minor = _minor; + } + + if (patch != NULL) + { + *patch = _patch; + } + + return 0; + } +#endif + + return -1; +} + +/**************************************************************************** + * Other functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_task_create_pinned_to_core + * + * Description: + * Create task and bind it to target CPU, the task will run when it + * is created + * + * Input Parameters: + * entry - Task entry + * name - Task name + * stack_depth - Task stack size + * param - Task private data + * prio - Task priority + * task_handle - Task handle pointer which is used to pause, resume + * and delete the task + * core_id - CPU which the task runs in + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t esp_task_create_pinned_to_core(void *entry, + const char *name, + uint32_t stack_depth, + void *param, + uint32_t prio, + void *task_handle, + uint32_t core_id) +{ + int pid; +#ifdef CONFIG_SMP + int ret; + cpu_set_t cpuset; +#endif + + DEBUGASSERT(task_handle != NULL); + +#ifdef CONFIG_SMP + ret = sched_lock(); + if (ret) + { + wlerr("Failed to lock scheduler before creating pinned thread\n"); + return false; + } +#endif + + pid = kthread_create(name, prio, stack_depth, entry, + (char * const *)param); + if (pid > 0) + { + if (task_handle) + { + *((int *)task_handle) = pid; + } + +#ifdef CONFIG_SMP + if (core_id < CONFIG_SMP_NCPUS) + { + CPU_ZERO(&cpuset); + CPU_SET(core_id, &cpuset); + ret = nxsched_set_affinity(pid, sizeof(cpuset), &cpuset); + if (ret) + { + wlerr("Failed to set affinity error=%d\n", ret); + return false; + } + } +#endif + } + else + { + wlerr("Failed to create task, error %d\n", pid); + } + +#ifdef CONFIG_SMP + ret = sched_unlock(); + if (ret) + { + wlerr("Failed to unlock scheduler after creating pinned thread\n"); + return false; + } +#endif + + return pid > 0; +} + +/**************************************************************************** + * Name: esp_queue_send_generic + * + * Description: + * Generic send message to queue within a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * ticks - Wait ticks + * prio - Message priority + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static IRAM_ATTR int32_t esp_queue_send_generic(void *queue, void *item, + uint32_t ticks, int prio) +{ + int ret; + struct timespec timeout; + struct mq_adpt_s *mq_adpt = (struct mq_adpt_s *)queue; +#ifdef CONFIG_ESP32_SPIFLASH + if (!spi_flash_cache_enabled()) + { + esp_send_queuecache(queue, item, mq_adpt->msgsize); + return esp_errno_trans(OK); + } +#endif + + if (ticks == OSI_FUNCS_TIME_BLOCKING || ticks == 0) + { + /* BLE interrupt function will call this adapter function to send + * message to message queue, so here we should call kernel API + * instead of application API + */ + + ret = file_mq_send(&mq_adpt->mq, (const char *)item, + mq_adpt->msgsize, prio); if (ret < 0) { - wlerr("Failed to receive from mqueue error=%d\n", ret); + wlerr("Failed to send message to mqueue error=%d\n", ret); } } else { ret = clock_gettime(CLOCK_REALTIME, &timeout); + if (ret < 0) + { + wlerr("Failed to get time %d\n", ret); + return esp_errno_trans(ret); + } + + if (ticks) + { + esp_update_time(&timeout, ticks); + } + + ret = file_mq_timedsend(&mq_adpt->mq, (const char *)item, + mq_adpt->msgsize, prio, &timeout); + if (ret < 0) + { + wlerr("Failed to timedsend message to mqueue error=%d\n", ret); + } + } + + return esp_errno_trans(ret); +} + +/**************************************************************************** + * Name: esp_update_time + * + * Description: + * Transform ticks to time and add this time to timespec value + * + * Input Parameters: + * ticks - System ticks + * + * Output Parameters: + * timespec - Input timespec data pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_update_time(struct timespec *timespec, uint32_t ticks) +{ + uint32_t tmp; + + tmp = TICK2SEC(ticks); + timespec->tv_sec += tmp; + + ticks -= SEC2TICK(tmp); + tmp = TICK2NSEC(ticks); + + timespec->tv_nsec += tmp; +} + +/**************************************************************************** + * Name: cause_sw_intr + * + * Description: + * Set a software interrupt bit + * + * Input Parameters: + * arg - number of the bit as void pointer + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR cause_sw_intr(void *arg) +{ + /* just convert void * to int, because the width is the same */ + + uint32_t intr_no = (uint32_t)arg; + XTHAL_SET_INTSET((1 << intr_no)); +} + +#ifdef CONFIG_PM + +/**************************************************************************** + * Name: btdm_slp_tmr_customer_callback + * + * Description: + * Callback function for ESP BLE sleep timer. This function is dispatched + * to the controller from `btdm_slp_tmr_callback`. If the power management + * lock has been released, it acquires the lock again. + * + * Input Parameters: + * arg - Unused + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void btdm_slp_tmr_customer_callback(void * arg) +{ + (void)(arg); + + if (g_pm_lock_acquired == false) + { + g_pm_lock_acquired = true; + esp32_pm_lockacquire(); + } +} + +/**************************************************************************** + * Name: btdm_slp_tmr_callback + * + * Description: + * ESP BLE sleep callback function. + * + * Input Parameters: + * arg - Unused + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR btdm_slp_tmr_callback(void *arg) +{ + (void)(arg); + btdm_dispatch_work_to_controller(btdm_slp_tmr_customer_callback, + NULL, + true); +} +#endif + +/**************************************************************************** + * Name: esp_int_adpt_cb + * + * Description: + * BT interrupt adapter callback function + * + * Input Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (not used) + * arg - Argument passed to the interrupt callback + * + * Returned Value: + * OK + * + ****************************************************************************/ + +static int IRAM_ATTR esp_int_adpt_cb(int irq, void *context, void *arg) +{ + struct irq_adpt_s *adapter = (struct irq_adpt_s *)arg; + + adapter->func(adapter->arg); - if (ret < 0) - { - wlerr("Failed to get time %d\n", ret); - return false; - } + return OK; +} - if (block_time_ms) - { - esp_update_time(&timeout, MSEC2TICK(block_time_ms)); - } +/**************************************************************************** + * Name: btdm_wakeup_request_callback + * + * Description: + * Callback function for ESP BLE wakeup request. This function is + * dispatched when a wakeup request is received. If the power management + * lock has not been acquired, it acquires the lock. It also stops the + * sleep timer and gives the wakeup request semaphore. + * + * Input Parameters: + * arg - Unused + * + * Returned Value: + * None + * + ****************************************************************************/ - ret = file_mq_timedreceive(&mq_adpt->mq, (char *)item, - mq_adpt->msgsize, &prio, &timeout); +static void btdm_wakeup_request_callback(void * arg) +{ + (void)(arg); - if (ret < 0) - { - wlerr("Failed to timedreceive from mqueue error=%d\n", ret); - } +#if CONFIG_PM + if (g_pm_lock_acquired == false) + { + g_pm_lock_acquired = true; + esp32_pm_lockacquire(); } - return ret > 0 ? true : false; + esp_timer_stop(g_btdm_slp_tmr); +#endif + btdm_wakeup_request(); + + semphr_give_wrapper(g_wakeup_req_sem); } /**************************************************************************** - * Name: queue_delete_wrapper + * Name: btdm_controller_mem_init * * Description: - * Delete message queue + * Initialize BT controller to allocate task and other resource. * * Input Parameters: - * queue - Message queue data pointer + * None * * Returned Value: - * None + * None * ****************************************************************************/ -static void queue_delete_wrapper(void *queue) +static void btdm_controller_mem_init(void) { - struct mq_adpt_s *mq_adpt = (struct mq_adpt_s *)queue; + int btdm_dram_regions; - file_mq_close(&mq_adpt->mq); - file_mq_unlink(mq_adpt->name); - kmm_free(mq_adpt); + /* initialise .data section */ + + memcpy(_data_start_btdm, (void *)_data_start_btdm_rom, + _data_end_btdm - _data_start_btdm); + + wlinfo(".data initialise [0x%08x] <== [0x%08x]\n", + (uint32_t)_data_start_btdm, _data_start_btdm_rom); + + /* initial em, .bss section */ + + btdm_dram_regions = sizeof(g_btdm_dram_available_region) + / sizeof(btdm_dram_available_region_t); + + for (int i = 1; i < btdm_dram_regions; i++) + { + if (g_btdm_dram_available_region[i].mode != ESP_BT_MODE_IDLE) + { + memset((void *)g_btdm_dram_available_region[i].start, 0x0, + g_btdm_dram_available_region[i].end - \ + g_btdm_dram_available_region[i].start); + wlinfo(".bss initialise [0x%08x] - [0x%08x]\n", + g_btdm_dram_available_region[i].start, + g_btdm_dram_available_region[i].end); + } + } } /**************************************************************************** @@ -2440,25 +2682,174 @@ static void queue_delete_wrapper(void *queue) static uint32_t btdm_config_mask_load(void) { - uint32_t mask = 0x0; + uint32_t mask = 0x0; #ifdef CONFIG_UART_BTH4 - mask |= BTDM_CFG_HCI_UART; + mask |= BTDM_CFG_HCI_UART; +#endif + +#ifdef CONFIG_BTDM_CTRL_PINNED_TO_CORE_1 + mask |= BTDM_CFG_CONTROLLER_RUN_APP_CPU; +#endif + +#ifdef CONFIG_BTDM_CTRL_FULL_SCAN_SUPPORTED + mask |= BTDM_CFG_BLE_FULL_SCAN_SUPPORTED; #endif -#ifdef CONFIG_ESP32_BLE_RUN_APP_CPU - mask |= BTDM_CFG_CONTROLLER_RUN_APP_CPU; + mask |= BTDM_CFG_SCAN_DUPLICATE_OPTIONS; + + mask |= BTDM_CFG_SEND_ADV_RESERVED_SIZE; + + return mask; +} + +/**************************************************************************** + * Name: bt_controller_deinit_internal + * + * Description: + * Deinitialize the internal structures of the Bluetooth controller. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void bt_controller_deinit_internal(void) +{ + periph_module_disable(PERIPH_BT_MODULE); + +#ifdef CONFIG_PM + + if (g_btdm_slp_tmr != NULL) + { + esp_timer_stop(g_btdm_slp_tmr); + esp_timer_delete(g_btdm_slp_tmr); + g_btdm_slp_tmr = NULL; + } + + g_pm_lock_acquired = false; #endif -#ifdef CONFIG_ESP32_BLE_FULL_SCAN - mask |= BTDM_CFG_BLE_FULL_SCAN_SUPPORTED; + if (g_wakeup_req_sem) + { + semphr_delete_wrapper(g_wakeup_req_sem); + g_wakeup_req_sem = NULL; + } + + if (g_osi_funcs_p) + { + free(g_osi_funcs_p); + g_osi_funcs_p = NULL; + } + + g_btdm_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE; + + g_btdm_lpcycle_us = 0; + btdm_controller_set_sleep_mode(BTDM_MODEM_SLEEP_MODE_NONE); + + esp_bt_power_domain_off(); + + esp_phy_modem_deinit(); +} + +/**************************************************************************** + * Name: async_wakeup_request + * + * Description: + * Request the BLE Controller to wakeup + * + * Input Parameters: + * event - the event that triggered the wakeup + * + * Returned Value: + * true if request lock is needed, false otherwise + * + ****************************************************************************/ + +static bool async_wakeup_request(int event) +{ + bool request_lock = false; + bool do_wakeup_request = false; + + switch (event) + { + case BTDM_ASYNC_WAKEUP_REQ_HCI: + btdm_in_wakeup_requesting_set(true); + + /* No break */ + + case BTDM_ASYNC_WAKEUP_REQ_CTRL_DISA: + if (!btdm_power_state_active()) + { + do_wakeup_request = true; + + btdm_dispatch_work_to_controller(btdm_wakeup_request_callback, + NULL, + true); + semphr_take_wrapper(g_wakeup_req_sem, OSI_FUNCS_TIME_BLOCKING); + } + break; + case BTDM_ASYNC_WAKEUP_REQ_COEX: + if (!btdm_power_state_active()) + { + do_wakeup_request = true; +#if CONFIG_PM + if (g_pm_lock_acquired == false) + { + g_pm_lock_acquired = true; + esp32_pm_lockacquire(); + } + + esp_timer_stop(g_btdm_slp_tmr); #endif + btdm_wakeup_request(); + } + break; + default: + return false; + } + + return do_wakeup_request; +} + +/**************************************************************************** + * Name: async_wakeup_request_end + * + * Description: + * Finish a wakeup request + * + * Input Parameters: + * event - the event that triggered the wakeup + * + * Returned Value: + * true if request lock is needed, false otherwise + * + ****************************************************************************/ - mask |= BTDM_CFG_SCAN_DUPLICATE_OPTIONS; +static void async_wakeup_request_end(int event) +{ + bool request_lock = false; - mask |= BTDM_CFG_SEND_ADV_RESERVED_SIZE; + switch (event) + { + case BTDM_ASYNC_WAKEUP_REQ_HCI: + request_lock = true; + break; + case BTDM_ASYNC_WAKEUP_REQ_COEX: + case BTDM_ASYNC_WAKEUP_REQ_CTRL_DISA: + request_lock = false; + break; + default: + return; + } - return mask; + if (request_lock) + { + btdm_in_wakeup_requesting_set(false); + } } /**************************************************************************** @@ -2475,233 +2866,248 @@ static uint32_t btdm_config_mask_load(void) * None * * Returned Value: - * None + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. * ****************************************************************************/ int esp32_bt_controller_init(void) { - esp_bt_controller_config_t bt_cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT(); - esp_bt_controller_config_t *cfg = &bt_cfg; - int err; + esp_bt_controller_config_t cfg = BT_CONTROLLER_INIT_CONFIG_DEFAULT(); uint32_t btdm_cfg_mask = 0; + int err; int i; + bool select_src_ret; + bool set_div_ret; +#ifdef CONFIG_PM + esp_timer_create_args_t create_args = + { + .callback = btdm_slp_tmr_callback, + .arg = NULL, + .name = "btSlp" + }; +#endif - sq_init(&g_int_flags_free); - sq_init(&g_int_flags_used); + /* If all the bt available memory was already released, + * cannot initialize bluetooth controller + */ - for (i = 0; i < NR_IRQSTATE_FLAGS; i++) + if (g_btdm_dram_available_region[0].mode == ESP_BT_MODE_IDLE) { - sq_addlast((sq_entry_t *)&g_int_flags[i], &g_int_flags_free); + wlerr("Error, bt available memory was released\n"); + return -EIO; } - if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) + /* Initialize list of interrupt flags to enable chained critical sections + * to return sucessfully. + */ + + sq_init(&g_ble_int_flags_free); + sq_init(&g_ble_int_flags_used); + + for (i = 0; i < NR_IRQSTATE_FLAGS; i++) { - wlerr("Invalid controller status"); - return ERROR; + sq_addlast((sq_entry_t *)&g_ble_int_flags[i], &g_ble_int_flags_free); } #ifdef CONFIG_ESP32_SPIFLASH + + /* Initialize interfaces that enable BLE ISRs to run during a + * SPI flash operation. + */ + if (esp_wireless_init() != OK) { return -EIO; } #endif - if (btdm_osi_funcs_register(&g_osi_funcs) != 0) + g_osi_funcs_p = + (struct osi_funcs_s *)kmm_malloc(sizeof(struct osi_funcs_s)); + + if (g_osi_funcs_p == NULL) { - wlerr("Error, probably invalid OSI Functions\n"); - return -EINVAL; + return -ENOMEM; } - wlinfo("BT controller compile version [%s]\n", - btdm_controller_get_compile_version()); - - /* If all the bt available memory was already released, - * cannot initialize bluetooth controller - */ - - if (btdm_dram_available_region[0].mode == ESP_BT_MODE_IDLE) + memcpy(g_osi_funcs_p, &g_osi_funcs_ro, sizeof(struct osi_funcs_s)); + if (btdm_osi_funcs_register(g_osi_funcs_p) != 0) { - wlerr("Error, bt available memory was released\n"); - return -EIO; + wlerr("Invalid OSI Functions\n"); + return -EINVAL; } - if (cfg == NULL) + if (g_btdm_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) { - wlerr("%s %d\n", __func__, __LINE__); - return -EINVAL; + return ESP_ERR_INVALID_STATE; } - cfg->controller_task_stack_size = CONFIG_ESP32_BLE_TASK_STACK_SIZE; - cfg->controller_task_prio = CONFIG_ESP32_BLE_TASK_PRIORITY; + /* overwrite some parameters */ - cfg->bt_max_sync_conn = CONFIG_ESP32_BLE_MAX_CONN; - cfg->magic = ESP_BT_CONTROLLER_CONFIG_MAGIC_VAL; + cfg.controller_task_stack_size = CONFIG_ESP32_BLE_TASK_STACK_SIZE; + cfg.controller_task_prio = CONFIG_ESP32_BLE_TASK_PRIORITY; + cfg.bt_max_sync_conn = CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF; + cfg.magic = ESP_BT_CONTROLLER_CONFIG_MAGIC_VAL; - if (((cfg->mode & ESP_BT_MODE_BLE) && (cfg->ble_max_conn <= 0 || - cfg->ble_max_conn > BTDM_CONTROLLER_BLE_MAX_CONN_LIMIT)) || - ((cfg->mode & ESP_BT_MODE_CLASSIC_BT) && (cfg->bt_max_acl_conn <= 0 || - cfg->bt_max_acl_conn > BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_LIMIT)) || - ((cfg->mode & ESP_BT_MODE_CLASSIC_BT) && - (cfg->bt_max_sync_conn > BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_LIMIT))) + if (((cfg.mode & ESP_BT_MODE_BLE) && (cfg.ble_max_conn <= 0 || + cfg.ble_max_conn > BTDM_CONTROLLER_BLE_MAX_CONN_LIMIT)) || + ((cfg.mode & ESP_BT_MODE_CLASSIC_BT) && (cfg.bt_max_acl_conn <= 0 || + cfg.bt_max_acl_conn > BTDM_CONTROLLER_BR_EDR_MAX_ACL_CONN_LIMIT)) || + ((cfg.mode & ESP_BT_MODE_CLASSIC_BT) && + (cfg.bt_max_sync_conn > BTDM_CONTROLLER_BR_EDR_MAX_SYNC_CONN_LIMIT))) { wlerr("%s %d\n", __func__, __LINE__); return -EINVAL; } wlinfo("BT controller compile version [%s]", - btdm_controller_get_compile_version()); + btdm_controller_get_compile_version()); + + g_wakeup_req_sem = semphr_create_wrapper(1, 0); + if (g_wakeup_req_sem == NULL) + { + err = -ENOMEM; + goto error; + } + + esp_phy_modem_init(); + + esp_bt_power_domain_on(); btdm_controller_mem_init(); - wlinfo("Memory initialized!\n"); + periph_module_enable(PERIPH_BT_MODULE); - bt_periph_module_enable(PERIPH_BT_MODULE); +#ifdef CONFIG_PM + g_btdm_allow_light_sleep = false; +#endif /* set default sleep clock cycle and its fractional bits */ g_btdm_lpcycle_us_frac = RTC_CLK_CAL_FRACT; g_btdm_lpcycle_us = 2 << (g_btdm_lpcycle_us_frac); - btdm_controller_set_sleep_mode(BTDM_MODEM_SLEEP_MODE_NONE); - - btdm_cfg_mask = btdm_config_mask_load(); +#ifdef CONFIG_BTDM_CTRL_MODEM_SLEEP_MODE_ORIG + g_btdm_lpclk_sel = BTDM_LPCLK_SEL_XTAL; /* set default value */ +#ifdef CONFIG_BTDM_CTRL_LPCLK_SEL_EXT_32K_XTAL - wlinfo("Going to call btdm_controller_init\n"); + /* check whether or not EXT_CRYS is working */ - if (btdm_controller_init(btdm_cfg_mask, cfg) != 0) + if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { - wlerr("Failed to initialize the BLE Controller\n"); - err = -ENOMEM; - goto error; - } - - wlinfo("The btdm_controller_init was initialized\n"); - -#ifdef CONFIG_BTDM_COEX_BLE_ADV_HIGH_PRIORITY - coex_ble_adv_priority_high_set(true); -#else - coex_ble_adv_priority_high_set(false); + g_btdm_lpclk_sel = BTDM_LPCLK_SEL_XTAL32K; /* External 32kHz XTAL */ +#ifdef CONFIG_PM + g_btdm_allow_light_sleep = true; #endif - - btdm_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; - - return OK; - -error: - return err; -} - -/**************************************************************************** - * Name: esp32_bt_controller_deinit - * - * Description: - * Deinit BT controller. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -int esp32_bt_controller_deinit(void) -{ - if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_INITED) + } + else { - return ERROR; + wlwarn("32.768kHz XTAL not detected, fall back to main XTAL as " + "Bluetooth sleep clock\n" + "light sleep mode will not be able to apply when bluetooth " + "is enabled"); + g_btdm_lpclk_sel = BTDM_LPCLK_SEL_XTAL; /* set default value */ } +#else + g_btdm_lpclk_sel = BTDM_LPCLK_SEL_XTAL; /* set default value */ +#endif - btdm_controller_deinit(); - - if (g_lp_stat.phy_enabled) + if (g_btdm_lpclk_sel == BTDM_LPCLK_SEL_XTAL) { - bt_phy_disable(); - g_lp_stat.phy_enabled = false; + select_src_ret = btdm_lpclk_select_src(BTDM_LPCLK_SEL_XTAL); + set_div_ret = btdm_lpclk_set_div(esp_clk_xtal_freq() * 2 / MHZ - 1); + assert(select_src_ret && set_div_ret); + g_btdm_lpcycle_us_frac = RTC_CLK_CAL_FRACT; + g_btdm_lpcycle_us = 2 << (g_btdm_lpcycle_us_frac); } else { - DEBUGPANIC(); + /* g_btdm_lpclk_sel == BTDM_LPCLK_SEL_XTAL32K */ + + select_src_ret = btdm_lpclk_select_src(BTDM_LPCLK_SEL_XTAL32K); + set_div_ret = btdm_lpclk_set_div(0); + assert(select_src_ret && set_div_ret); + g_btdm_lpcycle_us_frac = RTC_CLK_CAL_FRACT; + g_btdm_lpcycle_us = (RTC_CLK_CAL_FRACT > 15) ? + (1000000 << (RTC_CLK_CAL_FRACT - 15)) : + (1000000 >> (15 - RTC_CLK_CAL_FRACT)); + assert(g_btdm_lpcycle_us != 0); } -#ifdef CONFIG_PM - /* deinit low power control resources */ + btdm_controller_set_sleep_mode(BTDM_MODEM_SLEEP_MODE_ORIG); - g_lp_stat.pm_lock_released = false; +#elif CONFIG_BTDM_CTRL_MODEM_SLEEP_MODE_EVED + btdm_controller_set_sleep_mode(BTDM_MODEM_SLEEP_MODE_EVED); + UNUSED(select_src_ret); + UNUSED(set_div_ret); +#else + btdm_controller_set_sleep_mode(BTDM_MODEM_SLEEP_MODE_NONE); + UNUSED(select_src_ret); + UNUSED(set_div_ret); +#endif - if (g_lp_cntl.wakeup_timer_required) +#ifdef CONFIG_PM + if ((err = esp_timer_create(&create_args, &g_btdm_slp_tmr) != OK)) { - if (g_lp_stat.wakeup_timer_started) - { - esp_timer_stop(g_btdm_slp_tmr); - } - - g_lp_stat.wakeup_timer_started = false; - esp_timer_delete(g_btdm_slp_tmr); - g_btdm_slp_tmr = NULL; + wlerr("Failed to create timer"); + goto error; } - if (g_lp_cntl.enable) + g_pm_lock_acquired = true; +#endif + +#if CONFIG_ESP32_WIFI_BT_COEXIST + coex_init(); +#endif + + btdm_cfg_mask = btdm_config_mask_load(); + + wlinfo("Going to call btdm_controller_init\n"); + + if (btdm_controller_init(btdm_cfg_mask, &cfg) != 0) { - btdm_vnd_offload_task_deregister(BTDM_VND_OL_SIG_WAKEUP_TMR); - semphr_delete_wrapper(g_wakeup_req_sem); - g_wakeup_req_sem = NULL; + wlerr("Failed to initialize the BLE Controller\n"); + err = -ENOMEM; + goto error; } -#endif - btdm_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE; - g_btdm_lpcycle_us = 0; + wlinfo("The btdm_controller_init was initialized\n"); + + g_btdm_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; + return OK; + +error: + + bt_controller_deinit_internal(); + + return err; } /**************************************************************************** - * Name: esp32_bt_controller_disable + * Name: esp32_bt_controller_deinit * * Description: - * Disable BT controller. + * Deinit BT controller. + * * Input Parameters: - * None + * None * * Returned Value: - * None + * Zero (OK) is returned on success. Otherwise, -1 (ERROR) is returned. * ****************************************************************************/ -int esp32_bt_controller_disable(void) +int esp32_bt_controller_deinit(void) { - if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) + if (g_btdm_controller_status != ESP_BT_CONTROLLER_STATUS_INITED) { return ERROR; } - while (!btdm_power_state_active()) - { - nxsig_usleep(1000); /* wait */ - } - - btdm_controller_disable(); - -#ifdef CONFIG_ESP32_WIFI_BT_COEXIST - coex_disable(); -#endif - - btdm_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; - -#ifdef CONFIG_PM - /* disable low power mode */ + btdm_controller_deinit(); - if (g_lp_stat.pm_lock_released == false) - { - esp32_pm_lockrelease(); - g_lp_stat.pm_lock_released = true; - } - else - { - DEBUGPANIC(); - } -#endif + bt_controller_deinit_internal(); return OK; } @@ -2710,12 +3116,16 @@ int esp32_bt_controller_disable(void) * Name: esp32_bt_controller_enable * * Description: - * Enable BT controller. + * Enable BT controller. + * * Input Parameters: - * None + * mode - the mode(BLE/BT/BTDM) to enable. For compatible of API, retain + * this argument. This mode must be equal as the mode in "cfg" of + * esp_bt_controller_init(). * * Returned Value: - * None + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. * ****************************************************************************/ @@ -2723,7 +3133,7 @@ int esp32_bt_controller_enable(esp_bt_mode_t mode) { int ret = OK; - if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_INITED) + if (g_btdm_controller_status != ESP_BT_CONTROLLER_STATUS_INITED) { return ERROR; } @@ -2731,195 +3141,129 @@ int esp32_bt_controller_enable(esp_bt_mode_t mode) if (mode != btdm_controller_get_mode()) { wlerr("invalid mode %d, controller support mode is %d", - mode, btdm_controller_get_mode()); + mode, btdm_controller_get_mode()); return ERROR; } - bt_phy_enable(); +#ifdef CONFIG_PM + if (g_btdm_allow_light_sleep == false) + { + esp32_pm_lockacquire(); + } - btdm_rf_bb_init_phase2(); + esp32_pm_lockacquire(); +#endif - coex_bt_high_prio(); + esp_phy_enable(); #ifdef CONFIG_ESP32_WIFI_BT_COEXIST coex_enable(); #endif -#ifdef CONFIG_PM - /* enable low power mode */ - - esp32_pm_lockacquire(); - g_lp_stat.pm_lock_released = false; - - if (g_lp_cntl.enable) + if (btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_ORIG) { btdm_controller_enable_sleep(true); } -#endif - - if (g_lp_cntl.enable) - { - btdm_controller_enable_sleep(true); - } - - if (btdm_controller_enable(mode) != 0) - { - ret = ERROR; - goto error; - } - - btdm_controller_status = ESP_BT_CONTROLLER_STATUS_ENABLED; - - return ret; - -error: - /* disable low power mode */ + /* inititalize bluetooth baseband */ - btdm_controller_enable_sleep(false); + btdm_check_and_init_bb(); -#ifdef CONFIG_PM - if (g_lp_stat.pm_lock_released == false) + ret = btdm_controller_enable(mode); + if (ret != 0) { - esp32_pm_lockrelease(); - g_lp_stat.pm_lock_released = true; - } +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + coex_disable(); #endif + esp_phy_disable(); +#ifdef CONFIG_PM + if (g_btdm_allow_light_sleep == false) + { + esp32_pm_lockrelease(); + } - return ret; -} + esp32_pm_lockrelease(); +#endif + return ERROR; + } -/**************************************************************************** - * Name: esp32_bt_controller_get_status - * - * Description: - * Returns the status of the BT Controller - * - * Input Parameters: - * None - * - * Returned Value: - * The current status (type esp_bt_controller_status_t) - * - ****************************************************************************/ + g_btdm_controller_status = ESP_BT_CONTROLLER_STATUS_ENABLED; -esp_bt_controller_status_t esp32_bt_controller_get_status(void) -{ - return btdm_controller_status; + return OK; } /**************************************************************************** - * Name: async_wakeup_request + * Name: esp32_bt_controller_disable * * Description: - * Request the BLE Controller to wakeup + * Disable BT controller. * * Input Parameters: - * event - the event that triggered the wakeup + * None * * Returned Value: - * true if request lock is needed, false otherwise + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. * ****************************************************************************/ -static bool async_wakeup_request(int event) +int esp32_bt_controller_disable(void) { - bool request_lock = false; - bool do_wakeup_request = false; - - switch (event) + if (g_btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) { - case BTDM_ASYNC_WAKEUP_REQ_HCI: - request_lock = true; - break; - case BTDM_ASYNC_WAKEUP_REQ_COEX: - request_lock = false; - break; - default: - return false; + return ERROR; } - if (!btdm_power_state_active()) + /* disable modem sleep and wake up from sleep mode */ + + if (btdm_controller_get_sleep_mode() == BTDM_MODEM_SLEEP_MODE_ORIG) { - do_wakeup_request = true; - btdm_wakeup_request(request_lock); + btdm_controller_enable_sleep(false); + async_wakeup_request(BTDM_ASYNC_WAKEUP_REQ_CTRL_DISA); + while (btdm_power_state_active() == false) + { + nxsig_usleep(1000); + } } - return do_wakeup_request; -} - -/**************************************************************************** - * Name: async_wakeup_request_end - * - * Description: - * Finish a wakeup request - * - * Input Parameters: - * event - the event that triggered the wakeup - * - * Returned Value: - * true if request lock is needed, false otherwise - * - ****************************************************************************/ + btdm_controller_disable(); -static void async_wakeup_request_end(int event) -{ - bool request_lock = false; +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + coex_disable(); +#endif - switch (event) - { - case BTDM_ASYNC_WAKEUP_REQ_HCI: - request_lock = true; - break; - case BTDM_ASYNC_WAKEUP_REQ_COEX: - request_lock = false; - break; - default: - return; - } + esp_phy_disable(); + g_btdm_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; - if (request_lock) +#ifdef CONFIG_PM + if (g_btdm_allow_light_sleep == false) { - btdm_wakeup_request_end(); + esp32_pm_lockrelease(); } -} -/**************************************************************************** - * Name: coex_bt_wakeup_request - * - * Description: - * Request a Wi-Fi/BLE Coex wakeup request - * - * Input Parameters: - * none - * - * Returned Value: - * true if request lock is needed, false otherwise - * - ****************************************************************************/ + esp32_pm_lockrelease(); +#endif -static bool coex_bt_wakeup_request(void) -{ - return async_wakeup_request(BTDM_ASYNC_WAKEUP_REQ_COEX); + return OK; } /**************************************************************************** - * Name: coex_bt_wakeup_request_end + * Name: esp32_bt_controller_get_status * * Description: - * Finish Wi-Fi/BLE Coex wakeup request + * Returns the status of the BT Controller * * Input Parameters: - * none + * None * * Returned Value: - * none + * The current status (type esp_bt_controller_status_t) * ****************************************************************************/ -static void coex_bt_wakeup_request_end(void) +esp_bt_controller_status_t esp32_bt_controller_get_status(void) { - async_wakeup_request_end(BTDM_ASYNC_WAKEUP_REQ_COEX); + return g_btdm_controller_status; } /**************************************************************************** @@ -2938,11 +3282,6 @@ static void coex_bt_wakeup_request_end(void) bool esp32_vhci_host_check_send_available(void) { - if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) - { - return false; - } - return api_vhci_host_check_send_available(); } @@ -2950,10 +3289,11 @@ bool esp32_vhci_host_check_send_available(void) * Name: esp32_vhci_host_send_packet * * Description: - * Host send packet to controller. + * Host send packet to controller. + * * Input Parameters: - * data - the packet pointer - * len - the packet length + * data - the packet pointer + * len - the packet length * * Returned Value: * None @@ -2962,18 +3302,11 @@ bool esp32_vhci_host_check_send_available(void) void esp32_vhci_host_send_packet(uint8_t *data, uint16_t len) { - wlinfo("len: %d\n", len); - for (uint16_t i = 0; i < len; i++) - { - wlinfo("%02x\n", data[i]); - } - - if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) - { - return; - } + async_wakeup_request(BTDM_ASYNC_WAKEUP_REQ_HCI); api_vhci_host_send_packet(data, len); + + async_wakeup_request_end(BTDM_ASYNC_WAKEUP_REQ_HCI); } /**************************************************************************** @@ -2993,48 +3326,8 @@ void esp32_vhci_host_send_packet(uint8_t *data, uint16_t len) int esp32_vhci_register_callback(const esp_vhci_host_callback_t *callback) { int ret = ERROR; - if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) - { - return ret; - } ret = api_vhci_host_register_callback( (const vhci_host_callback_t *)callback) == 0 ? 0 : -1; return ret; } - -int IRAM_ATTR coex_bt_request_wrapper(uint32_t event, - uint32_t latency, - uint32_t duration) -{ -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) - return coex_bt_request(event, latency, duration); -#else - return 0; -#endif -} - -int IRAM_ATTR coex_bt_release_wrapper(uint32_t event) -{ -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) - return coex_bt_release(event); -#else - return 0; -#endif -} - -uint32_t IRAM_ATTR coex_bb_reset_lock_wrapper(void) -{ -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) - return coex_bb_reset_lock(); -#else - return 0; -#endif -} - -void IRAM_ATTR coex_bb_reset_unlock_wrapper(uint32_t restore) -{ -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) - coex_bb_reset_unlock(restore); -#endif -} diff --git a/arch/xtensa/src/esp32/esp32_ble_adapter.h b/arch/xtensa/src/esp32/esp32_ble_adapter.h index 447b1113037ce..522e75f463571 100644 --- a/arch/xtensa/src/esp32/esp32_ble_adapter.h +++ b/arch/xtensa/src/esp32/esp32_ble_adapter.h @@ -31,45 +31,6 @@ #include "esp_bt.h" -/* Bluetooth system and controller config */ - -#define BTDM_CFG_BT_DATA_RELEASE (1 << 0) -#define BTDM_CFG_HCI_UART (1 << 1) -#define BTDM_CFG_CONTROLLER_RUN_APP_CPU (1 << 2) -#define BTDM_CFG_SCAN_DUPLICATE_OPTIONS (1 << 3) -#define BTDM_CFG_SEND_ADV_RESERVED_SIZE (1 << 4) -#define BTDM_CFG_BLE_FULL_SCAN_SUPPORTED (1 << 5) - -/* Bluetooth memory regions */ - -#define SOC_MEM_BT_DATA_START 0x3ffae6e0 -#define SOC_MEM_BT_DATA_END 0x3ffaff10 -#define SOC_MEM_BT_EM_START 0x3ffb0000 -#define SOC_MEM_BT_EM_END 0x3ffb7cd8 -#define SOC_MEM_BT_EM_BTDM0_START 0x3ffb0000 -#define SOC_MEM_BT_EM_BTDM0_END 0x3ffb09a8 -#define SOC_MEM_BT_EM_BLE_START 0x3ffb09a8 -#define SOC_MEM_BT_EM_BLE_END 0x3ffb1ddc -#define SOC_MEM_BT_EM_BTDM1_START 0x3ffb1ddc -#define SOC_MEM_BT_EM_BTDM1_END 0x3ffb2730 -#define SOC_MEM_BT_EM_BREDR_START 0x3ffb2730 -#define SOC_MEM_BT_EM_BREDR_NO_SYNC_END 0x3ffb6388 /* Not calculate with synchronize connection support */ -#define SOC_MEM_BT_EM_BREDR_END 0x3ffb7cd8 /* Calculate with synchronize connection support */ -#define SOC_MEM_BT_EM_SYNC0_START 0x3ffb6388 -#define SOC_MEM_BT_EM_SYNC0_END 0x3ffb6bf8 -#define SOC_MEM_BT_EM_SYNC1_START 0x3ffb6bf8 -#define SOC_MEM_BT_EM_SYNC1_END 0x3ffb7468 -#define SOC_MEM_BT_EM_SYNC2_START 0x3ffb7468 -#define SOC_MEM_BT_EM_SYNC2_END 0x3ffb7cd8 -#define SOC_MEM_BT_BSS_START 0x3ffb8000 -#define SOC_MEM_BT_BSS_END 0x3ffb9a20 -#define SOC_MEM_BT_MISC_START 0x3ffbdb28 -#define SOC_MEM_BT_MISC_END 0x3ffbdb5c - -#define SOC_MEM_BT_EM_PER_SYNC_SIZE 0x870 - -#define SOC_MEM_BT_EM_BREDR_REAL_END (SOC_MEM_BT_EM_BREDR_NO_SYNC_END + CONFIG_BTDM_CTRL_BR_EDR_MAX_SYNC_CONN_EFF * SOC_MEM_BT_EM_PER_SYNC_SIZE) - /**************************************************************************** * Public Function Prototypes ****************************************************************************/ diff --git a/arch/xtensa/src/esp32/esp32_clockconfig.c b/arch/xtensa/src/esp32/esp32_clockconfig.c index cadddb76d697f..54675e151e003 100644 --- a/arch/xtensa/src/esp32/esp32_clockconfig.c +++ b/arch/xtensa/src/esp32/esp32_clockconfig.c @@ -216,42 +216,3 @@ void esp32_clockconfig(void) esp32_rtc_bbpll_configure(xtal_freq, source_freq_mhz); esp32_set_cpu_freq(freq_mhz); } - -/**************************************************************************** - * Name: esp_clk_cpu_freq - * - * Description: - * Get CPU frequency - * - * Input Parameters: - * None - * - * Returned Value: - * CPU frequency - * - ****************************************************************************/ - -int IRAM_ATTR esp_clk_cpu_freq(void) -{ - return g_ticks_per_us_pro * MHZ; -} - -/**************************************************************************** - * Name: esp_clk_apb_freq - * - * Description: - * Return current APB clock frequency. - * - * Input Parameters: - * None - * - * Returned Value: - * APB clock frequency, in Hz - * - ****************************************************************************/ - -int IRAM_ATTR esp_clk_apb_freq(void) -{ - return MIN(g_ticks_per_us_pro, 80) * MHZ; -} - diff --git a/arch/xtensa/src/esp32/esp32_clockconfig.h b/arch/xtensa/src/esp32/esp32_clockconfig.h index 4393210b55afc..39b6490b04bc6 100644 --- a/arch/xtensa/src/esp32/esp32_clockconfig.h +++ b/arch/xtensa/src/esp32/esp32_clockconfig.h @@ -27,6 +27,8 @@ #include +#include "esp_private/esp_clk.h" + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ @@ -77,36 +79,4 @@ void esp32_set_cpu_freq(int cpu_freq_mhz); void esp32_clockconfig(void); -/**************************************************************************** - * Name: esp_clk_cpu_freq - * - * Description: - * Get CPU frequency - * - * Input Parameters: - * None - * - * Returned Value: - * CPU frequency - * - ****************************************************************************/ - -int esp_clk_cpu_freq(void); - -/**************************************************************************** - * Name: esp_clk_apb_freq - * - * Description: - * Return current APB clock frequency. - * - * Input Parameters: - * None - * - * Returned Value: - * APB clock frequency, in Hz - * - ****************************************************************************/ - -int esp_clk_apb_freq(void); - #endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CLOCKCONFIG_H */ diff --git a/arch/xtensa/src/esp32/esp32_dac.c b/arch/xtensa/src/esp32/esp32_dac.c new file mode 100644 index 0000000000000..5f3b84540ae37 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_dac.c @@ -0,0 +1,400 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_dac.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "xtensa.h" +#include +#include +#include +#include +#include "esp32_dac.h" +#include "esp32_rtc_gpio.h" +#include "hardware/esp32_rtc_io.h" +#include "hardware/esp32_dport.h" +#include "hardware/esp32_sens.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ESP32_DAC0_RTC_IO_CHANNEL RTCIO_GPIO25_CHANNEL +#define ESP32_DAC1_RTC_IO_CHANNEL RTCIO_GPIO26_CHANNEL + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct esp32_dac_priv_s +{ + spinlock_t slock; /* Device specific lock. */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* DAC methods */ + +static void dac_reset(struct dac_dev_s *dev); +static int dac_setup(struct dac_dev_s *dev); +static void dac_shutdown(struct dac_dev_s *dev); +static void dac_txint(struct dac_dev_s *dev, bool enable); +static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg); +static int dac_ioctl(struct dac_dev_s *dev, int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct esp32_dac_priv_s esp32_dac_priv; + +static const struct dac_ops_s g_dacops = +{ + .ao_reset = dac_reset, + .ao_setup = dac_setup, + .ao_shutdown = dac_shutdown, + .ao_txint = dac_txint, + .ao_send = dac_send, + .ao_ioctl = dac_ioctl, +}; + +static struct dac_dev_s g_dac = +{ + .ad_ops = &g_dacops, /* Arch-specific operations */ + .ad_nchannel = 2, /* Available number of DAC channels */ + .ad_priv = (void *) (&esp32_dac_priv), /* Used by the arch-specific logic */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: dac_power + * + * Description: + * Power ON or OFF both DAC channels + * + * Input Parameters: + * bool on - true : turn DAC ON; false : turn DAC OFF + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void dac_power(bool on) +{ + if (on) + { + modifyreg32(RTC_IO_PAD_DAC1_REG, 0, RTC_IO_PDAC1_DAC_XPD_FORCE | + RTC_IO_PDAC1_XPD_DAC); + modifyreg32(RTC_IO_PAD_DAC2_REG, 0, RTC_IO_PDAC2_DAC_XPD_FORCE | + RTC_IO_PDAC2_XPD_DAC); + } + else + { + modifyreg32(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_DAC_XPD_FORCE | + RTC_IO_PDAC1_XPD_DAC, 0); + modifyreg32(RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_DAC_XPD_FORCE | + RTC_IO_PDAC2_XPD_DAC, 0); + } +} + +/**************************************************************************** + * Name: dac_reset + * + * Description: + * Reset the DAC channel. Called early to initialize the hardware. This + * is called, before dac_setup() and on error conditions. + * + * NOTE: DAC reset will reset both DAC channels! + * + * Input Parameters: + * dev - A pointer to the DAC device structure. This structure contains + * information about the DAC device. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void dac_reset(struct dac_dev_s *dev) +{ + dac_shutdown(dev); + dac_setup(dev); +} + +/**************************************************************************** + * Name: dac_setup + * + * Description: + * Configure the DAC. This method is called the first time that the DAC + * device is opened. This will occur when the port is first opened. + * This setup includes configuring and attaching DAC interrupts. + * Interrupts are all disabled upon return. + * + * Input Parameters: + * dev - A pointer to the DAC device structure. This structure contains + * information about the DAC device. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int dac_setup(struct dac_dev_s *dev) +{ + irqstate_t flags; + struct esp32_dac_priv_s *priv = (struct esp32_dac_priv_s *) dev->ad_priv; + ainfo("DAC starting setup (for both channels)"); + + flags = spin_lock_irqsave(&priv->slock); + + /* Initialize RTC GPIO set to RTC Disabled and disable both pull resistors + * set RTC_IO_PDACn_MUX_SEL to route the pad to RTC block + * set RTC_IO_PDACn_DRV to 0x2 (which is default anyway) + * Note: Drive strength _DRV (you won't find this in TRM) + * 0: ~5 mA; 1: ~10 mA; 2: ~20 mA; 3: ~40 mA; the default value is 2. + * Keep other bits 0, especially: + * RTC_IO_PDACn_FUN_SEL (2 bits) = mode 0 to choose RTC_GPIO function. + * RTC_IO_PDACn_FUN_IE to disable Input + * RTC_IO_PDACn_RUE to disable pull up resistor + * RTC_IO_PDACn_RDE to disable pull down resistor + * + * Note: the following 2 bits are setup separately in dac_power as a last + * operation. + * set RTC_IO_PDACn_DAC_XPD_FORCE to power up DAC + * set RTC_IO_PDACn_XPD_DAC to power on DAC + */ + + uint32_t reg_val = RTC_IO_PDAC1_MUX_SEL | + 0x2 << RTC_IO_PDAC1_DRV_S; + + /* Write the same value to both registers for DAC 1 and DAC 2 */ + + putreg32(reg_val, RTC_IO_PAD_DAC1_REG); + putreg32(reg_val, RTC_IO_PAD_DAC2_REG); + + /* Disable GPIO output by setting bits in "write 1 to clear" reg */ + + modifyreg32(RTC_GPIO_ENABLE_W1TC_REG, 0 , + (UINT32_C(1) << (ESP32_DAC0_RTC_IO_CHANNEL + + RTC_GPIO_ENABLE_W1TC_S)) | + (UINT32_C(1) << (ESP32_DAC1_RTC_IO_CHANNEL + + RTC_GPIO_ENABLE_W1TC_S))); + + /* Clear bit of PAD_DRIVER to setup "normal" output mode for the + * corresponding pads + */ + + modifyreg32(RTC_GPIO_PIN6_REG, RTC_GPIO_PIN6_PAD_DRIVER, 0); + modifyreg32(RTC_GPIO_PIN7_REG, RTC_GPIO_PIN7_PAD_DRIVER, 0); + + dac_power(true); + + dev->ad_ocount += 1; + + spin_unlock_irqrestore(&priv->slock, flags); + + return OK; +} + +/**************************************************************************** + * Name: dac_shutdown + * + * Description: + * Disable the DAC. This method is called when the DAC device is closed. + * This method reverses the operation the setup method. + * + * Input Parameters: + * dev - A pointer to the DAC device structure. This structure contains + * information about the DAC device. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void dac_shutdown(struct dac_dev_s *dev) +{ + esp32_configrtcio(ESP32_DAC0_RTC_IO_CHANNEL, RTC_FUNCTION_DIGITAL); + esp32_configrtcio(ESP32_DAC1_RTC_IO_CHANNEL, RTC_FUNCTION_DIGITAL); + dac_power(false); +} + +/**************************************************************************** + * Name: dac_txint + * + * Description: + * Call to enable or disable TX (transmit) interrupts for the DAC device. + * This function is intended to control interrupt-driven data transfers. + * Enabling TX interrupts allows the DAC device to generate + * an interrupt when it is ready to accept new data for transmission. + * Disabling TX interrupts would prevent the DAC from generating these + * interrupts. + * + * Input Parameters: + * dev - A pointer to the DAC device structure. This structure contains + * information about the DAC device. + * enable - Set true to enable TX interrupts. set false to disable + * TX interrupts. + * + * Returned Value: + * None + * + * Note: + * The actual logic for enabling or disabling TX interrupts is not + * implemented in this function! + * + ****************************************************************************/ + +static void dac_txint(struct dac_dev_s *dev, bool enable) +{ +} + +/**************************************************************************** + * Name: dac_send + * + * Description: + * Set the DAC (Digital-to-Analog Converter) output. + * + * Input Parameters: + * dev - A pointer to the DAC device structure. This structure contains + * information about the DAC device. + * msg - A pointer to the DAC message structure. This structure includes + * the data to be sent to the DAC and the target DAC channel. + * The 'am_data' field of this structure is the actual data to be + * written to the DAC, and 'am_channel' determines which DAC channel + * (0 or 1) to use. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. -EINVAL is + * returned if an invalid channel is specified. + * + * Note: The dac_msg_s.am_data is treated as 8 bit value i.e. in range + * from 0-255 and corresponds to the analog voltage 0~Vref. + * The reference voltage 'Vref' here is input from the pin VDD3P3_RTC + * which ideally equals to the power supply VDD (3.3V). + * The output voltage can be calculated as the following: + * out_voltage = 3.3 * digi_val / 255 + * + ****************************************************************************/ + +static int dac_send(struct dac_dev_s *dev, struct dac_msg_s *msg) +{ + irqstate_t flags; + uint8_t value = (uint8_t)(msg->am_data & 0xff); + uint32_t reg_val; + struct esp32_dac_priv_s *priv = (struct esp32_dac_priv_s *) dev->ad_priv; + + flags = spin_lock_irqsave(&priv->slock); + + switch (msg->am_channel) + { + case 0: + modifyreg32(SENS_SAR_DAC_CTRL2_REG, SENS_DAC_CW_EN1, 0); + reg_val = getreg32(RTC_IO_PAD_DAC1_REG); + reg_val &= ~RTC_IO_PDAC1_DAC_M; + reg_val |= value << RTC_IO_PDAC1_DAC_S; + putreg32(reg_val, RTC_IO_PAD_DAC1_REG); + break; + + case 1: + modifyreg32(SENS_SAR_DAC_CTRL2_REG, SENS_DAC_CW_EN2, 0); + reg_val = getreg32(RTC_IO_PAD_DAC2_REG); + reg_val &= ~RTC_IO_PDAC2_DAC_M; + reg_val |= value << RTC_IO_PDAC2_DAC_S; + putreg32(reg_val, RTC_IO_PAD_DAC2_REG); + break; + + default: + spin_unlock_irqrestore(&priv->slock, flags); + return -EINVAL; + } + + spin_unlock_irqrestore(&priv->slock, flags); + + /* One shot mode does not support interrupts for DAC. The TX Done is + * signaled to upper half driver directly from this function because the + * value is used right away. + */ + + dac_txdone(dev); + + return OK; +} + +/**************************************************************************** + * Name: dac_ioctl + * + * Description: + * All ioctl (input/output control) calls for the DAC device are routed + * through this method. This function handles various control commands + * for the DAC device. Currently, it returns -ENOTTY for all commands, + * indicating that no command is implemented. + * + * Input Parameters: + * dev - A pointer to the DAC device structure. This structure contains + * information about the DAC device, required for handling the ioctl + * commands. + * cmd - An integer value representing the ioctl command. These commands + * are used to perform various control operations on the DAC device. + * arg - An unsigned long value representing additional information or + * arguments that are relevant to the ioctl command. + * The interpretation of this parameter + * depends on the specific command. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. Currently, it + * always returns -ENOTTY, indicating that no ioctl commands are supported. + * + ****************************************************************************/ + +static int dac_ioctl(struct dac_dev_s *dev, int cmd, unsigned long arg) +{ + return -ENOTTY; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_dac_initialize + * + * Description: + * Initialize the DAC. + * + * Input Parameters: + * None + * + * Returned Value: + * Valid dac device structure reference on success; a NULL on failure. + * + ****************************************************************************/ + +struct dac_dev_s *esp32_dac_initialize(void) +{ + return &g_dac; +} diff --git a/arch/xtensa/src/esp32/esp32_dac.h b/arch/xtensa/src/esp32/esp32_dac.h new file mode 100644 index 0000000000000..52782d756d4c3 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_dac.h @@ -0,0 +1,63 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_dac.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_DAC_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_DAC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_dac_initialize + * + * Description: + * Initialize the DAC. + * + * Input Parameters: + * None + * + * Returned Value: + * Valid dac device structure reference on success; a NULL on failure. + * + ****************************************************************************/ + +struct dac_dev_s *esp32_dac_initialize(void); + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_DAC_H */ diff --git a/arch/xtensa/src/esp32/esp32_efuse.c b/arch/xtensa/src/esp32/esp32_efuse.c index 27815ac045139..df7518520c5bf 100644 --- a/arch/xtensa/src/esp32/esp32_efuse.c +++ b/arch/xtensa/src/esp32/esp32_efuse.c @@ -32,7 +32,8 @@ #include "xtensa.h" #include "esp32_efuse.h" #include "esp32_clockconfig.h" -#include "hardware/efuse_reg.h" +#include "hardware/esp32_apb_ctrl.h" +#include "hardware/esp32_efuse.h" /**************************************************************************** * Pre-processor Definitions @@ -67,6 +68,7 @@ uint32_t g_start_efuse_wrreg[4] = * Private Prototypes ****************************************************************************/ +#ifdef CONFIG_ESP32_EFUSE static int esp_efuse_set_timing(void); void esp_efuse_burn_efuses(void); static uint32_t get_mask(uint32_t bit_count, uint32_t shift); @@ -89,11 +91,17 @@ static int esp_efuse_fill_buff(uint32_t num_reg, int bit_offset, int *bits_counter); static void esp_efuse_write_reg(uint32_t blk, uint32_t num_reg, uint32_t value); +#endif /* CONFIG_ESP32_EFUSE */ + +static uint32_t efuse_hal_get_major_chip_version(void); +static uint32_t efuse_hal_get_minor_chip_version(void); /**************************************************************************** * Private Functions ****************************************************************************/ +#ifdef CONFIG_ESP32_EFUSE + static int esp_efuse_set_timing(void) { uint32_t apb_freq_mhz = esp_clk_apb_freq() / 1000000; @@ -428,10 +436,105 @@ static void esp_efuse_write_reg(uint32_t blk, uint32_t num_reg, putreg32(reg_to_write, addr_wr_reg); } +#endif /* CONFIG_ESP32_EFUSE */ + +/**************************************************************************** + * Name: efuse_hal_get_major_chip_version + * + * Description: + * Retrieves the major version of the chip. It reads the version + * information from specific registers and combines them to determine + * the major version. + * + * Input Parameters: + * None + * + * Returned Value: + * The major version of the chip as an unsigned 32-bit integer. + * + ****************************************************************************/ + +IRAM_ATTR static uint32_t efuse_hal_get_major_chip_version(void) +{ + uint8_t eco_bit0; + uint8_t eco_bit1; + uint8_t eco_bit2; + uint32_t combine_value; + uint32_t chip_ver = 0; + + eco_bit0 = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_REV1); + eco_bit1 = REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_CHIP_VER_REV2); + eco_bit2 = (getreg32(APB_CTRL_DATE_REG) & 0x80000000) >> 31; + combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0; + + switch (combine_value) + { + case 0: + chip_ver = 0; + break; + case 1: + chip_ver = 1; + break; + case 3: + chip_ver = 2; + break; + case 7: + chip_ver = 3; + break; + default: + chip_ver = 0; + break; + } + + return chip_ver; +} + +/**************************************************************************** + * Name: efuse_hal_get_minor_chip_version + * + * Description: + * Retrieves the minor version of the chip. It reads the version + * information from a specific register. + * + * Input Parameters: + * None + * + * Returned Value: + * The minor version of the chip as an unsigned 32-bit integer. + * + ****************************************************************************/ + +IRAM_ATTR static uint32_t efuse_hal_get_minor_chip_version(void) +{ + return REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_WAFER_VERSION_MINOR); +} + /**************************************************************************** * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: esp_efuse_hal_chip_revision + * + * Description: + * Returns the chip version in the format: Major * 100 + Minor. + * + * Input Parameters: + * None + * + * Returned Value: + * The chip version as an unsigned 32-bit integer. + * + ****************************************************************************/ + +IRAM_ATTR uint32_t esp_efuse_hal_chip_revision(void) +{ + return (efuse_hal_get_major_chip_version() * 100) + + efuse_hal_get_minor_chip_version(); +} + +#ifdef CONFIG_ESP32_EFUSE + /* Read value from EFUSE, writing it into an array */ int esp_efuse_read_field(const efuse_desc_t *field[], void *dst, @@ -498,3 +601,4 @@ void esp_efuse_burn_efuses(void) }; } +#endif /* CONFIG_ESP32_EFUSE */ diff --git a/arch/xtensa/src/esp32/esp32_efuse.h b/arch/xtensa/src/esp32/esp32_efuse.h index 51497ba3187bf..904693d3fc86a 100644 --- a/arch/xtensa/src/esp32/esp32_efuse.h +++ b/arch/xtensa/src/esp32/esp32_efuse.h @@ -18,6 +18,16 @@ * ****************************************************************************/ +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + /* Type of eFuse blocks for ESP32 */ typedef enum @@ -52,6 +62,24 @@ typedef int (*efuse_func_proc_t) (unsigned int num_reg, * Public Functions Prototypes ****************************************************************************/ +/**************************************************************************** + * Name: esp_efuse_hal_chip_revision + * + * Description: + * Returns the chip version in the format: Major * 100 + Minor. + * + * Input Parameters: + * None + * + * Returned Value: + * The chip version as an unsigned 32-bit integer. + * + ****************************************************************************/ + +uint32_t esp_efuse_hal_chip_revision(void); + +#ifdef CONFIG_ESP32_EFUSE + int esp_efuse_read_field(const efuse_desc_t *field[], void *dst, size_t dst_size_bits); @@ -61,3 +89,5 @@ int esp_efuse_write_field(const efuse_desc_t *field[], void esp_efuse_burn_efuses(void); int esp32_efuse_initialize(const char *devpath); + +#endif /* CONFIG_ESP32_EFUSE */ diff --git a/arch/xtensa/src/esp32/esp32_efuse_table.c b/arch/xtensa/src/esp32/esp32_efuse_table.c deleted file mode 100644 index b923099f4e157..0000000000000 --- a/arch/xtensa/src/esp32/esp32_efuse_table.c +++ /dev/null @@ -1,641 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_efuse_table.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include "esp32_efuse.h" - -#define MAX_BLK_LEN 256 - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* The last free bit in the block is counted over the entire file */ - -#define LAST_FREE_BIT_BLK1 MAX_BLK_LEN -#define LAST_FREE_BIT_BLK2 MAX_BLK_LEN -#define LAST_FREE_BIT_BLK3 192 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -static const efuse_desc_t MAC_FACTORY[] = -{ - { - 72, 8 /* Factory MAC addr [0], */ - }, - { - 64, 8 /* Factory MAC addr [1], */ - }, - { - 56, 8 /* Factory MAC addr [2], */ - }, - { - 48, 8 /* Factory MAC addr [3], */ - }, - { - 40, 8 /* Factory MAC addr [4], */ - }, - { - 32, 8 /* Factory MAC addr [5], */ - }, -}; - -static const efuse_desc_t MAC_FACTORY_CRC[] = -{ - { - 80, 8 /* CRC8 for factory MAC address */ - }, -}; - -static const efuse_desc_t MAC_CUSTOM_CRC[] = -{ - { - 768, 8 /* CRC8 for custom MAC address */ - }, -}; - -static const efuse_desc_t MAC_CUSTOM[] = -{ - { - 776, 48 /* Custom MAC */ - }, -}; - -static const efuse_desc_t MAC_CUSTOM_VER[] = -{ - { - 952, 8 /* Custom MAC version */ - }, -}; - -static const efuse_desc_t SECURE_BOOT_KEY[] = -{ - { - 512, MAX_BLK_LEN /* Security boot key */ - }, -}; - -static const efuse_desc_t ABS_DONE_0[] = -{ - { - 196, 1 /* Secure boot is enabled for bootloader image. - * EFUSE_RD_ABS_DONE_0 - */ - }, -}; - -static const efuse_desc_t ENCRYPT_FLASH_KEY[] = -{ - { - 256, MAX_BLK_LEN /* Flash encrypt key */ - }, -}; - -static const efuse_desc_t ENCRYPT_CONFIG[] = -{ - { - 188, 4 /* Flash encrypt. EFUSE_FLASH_CRYPT_CONFIG_M */ - }, -}; - -static const efuse_desc_t DISABLE_DL_ENCRYPT[] = -{ - { - 199, 1 /* Flash encrypt. Disable UART bootloader - * encryption. EFUSE_DISABLE_DL_ENCRYPT - */ - }, -}; - -static const efuse_desc_t DISABLE_DL_DECRYPT[] = -{ - { - 200, 1 /* Flash encrypt. Disable UART bootloader - * decryption. EFUSE_DISABLE_DL_DECRYPT - */ - }, -}; - -static const efuse_desc_t DISABLE_DL_CACHE[] = -{ - { - 201, 1 /* Flash encrypt. Disable UART bootloader MMU - * cache. EFUSE_DISABLE_DL_CACHE - */ - }, -}; - -static const efuse_desc_t FLASH_CRYPT_CNT[] = -{ - { - 20, 7 /* Flash encrypt. Flash encryption is enabled - * if this field has an odd number of bits set. - * EFUSE_FLASH_CRYPT_CNT - */ - }, -}; - -static const efuse_desc_t DISABLE_JTAG[] = -{ - { - 198, 1 /* Disable JTAG. EFUSE_RD_DISABLE_JTAG */ - }, -}; - -static const efuse_desc_t CONSOLE_DEBUG_DISABLE[] = -{ - { - 194, 1 /* Disable ROM BASIC interpreter fallback. - * EFUSE_RD_CONSOLE_DEBUG_DISABLE - */ - }, -}; - -static const efuse_desc_t UART_DOWNLOAD_DIS[] = -{ - { - 27, 1 /* Disable UART download mode. - * Valid for ESP32 V3 and newer - */ - }, -}; - -static const efuse_desc_t WR_DIS_FLASH_CRYPT_CNT[] = -{ - { - 2, 1 /* Flash encrypt. Write protection - * FLASH_CRYPT_CNT - */ - }, -}; - -static const efuse_desc_t WR_DIS_BLK1[] = -{ - { - 7, 1 /* Flash encrypt. Write protection encryption key. - * EFUSE_WR_DIS_BLK1 - */ - }, -}; - -static const efuse_desc_t WR_DIS_BLK2[] = -{ - { - 8, 1 /* Security boot. Write protection security key. - * EFUSE_WR_DIS_BLK2 - */ - }, -}; - -static const efuse_desc_t WR_DIS_BLK3[] = -{ - { - 9, 1 /* Write protection for EFUSE_BLK3. - * EFUSE_WR_DIS_BLK3 - */ - }, -}; - -static const efuse_desc_t RD_DIS_BLK1[] = -{ - { - 16, 1 /* Flash encrypt. efuse_key_read_protected. - * EFUSE_RD_DIS_BLK1 - */ - }, -}; - -static const efuse_desc_t RD_DIS_BLK2[] = -{ - { - 17, 1 /* Security boot. efuse_key_read_protected. - * EFUSE_RD_DIS_BLK2 - */ - }, -}; - -static const efuse_desc_t RD_DIS_BLK3[] = -{ - { - 18, 1 /* Read protection for EFUSE_BLK3. - * EFUSE_RD_DIS_BLK3 - */ - }, -}; - -static const efuse_desc_t CHIP_VER_DIS_APP_CPU[] = -{ - { - 96, 1 /* EFUSE_RD_CHIP_VER_DIS_APP_CPU */ - }, -}; - -static const efuse_desc_t CHIP_VER_DIS_BT[] = -{ - { - 97, 1 /* EFUSE_RD_CHIP_VER_DIS_BT */ - }, -}; - -static const efuse_desc_t CHIP_VER_PKG[] = -{ - { - 105, 3 /* EFUSE_RD_CHIP_VER_PKG */ - }, -}; - -static const efuse_desc_t CHIP_CPU_FREQ_LOW[] = -{ - { - 108, 1 /* EFUSE_RD_CHIP_CPU_FREQ_LOW */ - }, -}; - -static const efuse_desc_t CHIP_CPU_FREQ_RATED[] = -{ - { - 109, 1 /* EFUSE_RD_CHIP_CPU_FREQ_RATED */ - }, -}; - -static const efuse_desc_t CHIP_VER_REV1[] = -{ - { - 111, 1 /* EFUSE_RD_CHIP_VER_REV1 */ - }, -}; - -static const efuse_desc_t CHIP_VER_REV2[] = -{ - { - 180, 1 /* EFUSE_RD_CHIP_VER_REV2 */ - }, -}; - -static const efuse_desc_t XPD_SDIO_REG[] = -{ - { - 142, 1 /* EFUSE_RD_XPD_SDIO_REG */ - }, -}; - -static const efuse_desc_t SDIO_TIEH[] = -{ - { - 143, 1 /* EFUSE_RD_SDIO_TIEH */ - }, -}; - -static const efuse_desc_t SDIO_FORCE[] = -{ - { - 144, 1 /* EFUSE_RD_SDIO_FORCE */ - }, -}; - -static const efuse_desc_t ADC_VREF_AND_SDIO_DREF[] = -{ - { - 136, 6 /* EFUSE_RD_ADC_VREF[0..4] or SDIO_DREFH[0 1] */ - }, -}; - -static const efuse_desc_t ADC1_TP_LOW[] = -{ - { - 864, 7 /* TP_REG EFUSE_RD_ADC1_TP_LOW */ - }, -}; - -static const efuse_desc_t ADC2_TP_LOW[] = -{ - { - 880, 7 /* TP_REG EFUSE_RD_ADC2_TP_LOW */ - }, -}; - -static const efuse_desc_t ADC1_TP_HIGH[] = -{ - { - 871, 9 /* TP_REG EFUSE_RD_ADC1_TP_HIGH */ - }, -}; - -static const efuse_desc_t ADC2_TP_HIGH[] = -{ - { - 887, 9 /* TP_REG EFUSE_RD_ADC2_TP_HIGH */ - }, -}; - -static const efuse_desc_t SECURE_VERSION[] = -{ - { - 896, 32 /* Secure version for anti-rollback */ - }, -}; - -/* */ - -const efuse_desc_t *ESP_EFUSE_MAC_FACTORY[] = -{ - &MAC_FACTORY[0], /* Factory MAC addr [0] */ - &MAC_FACTORY[1], /* Factory MAC addr [1] */ - &MAC_FACTORY[2], /* Factory MAC addr [2] */ - &MAC_FACTORY[3], /* Factory MAC addr [3] */ - &MAC_FACTORY[4], /* Factory MAC addr [4] */ - &MAC_FACTORY[5], /* Factory MAC addr [5] */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_MAC_FACTORY_CRC[] = -{ - &MAC_FACTORY_CRC[0], /* CRC8 for factory MAC address */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_MAC_CUSTOM_CRC[] = -{ - &MAC_CUSTOM_CRC[0], /* CRC8 for custom MAC address. */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_MAC_CUSTOM[] = -{ - &MAC_CUSTOM[0], /* Custom MAC */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_MAC_CUSTOM_VER[] = -{ - &MAC_CUSTOM_VER[0], /* Custom MAC version */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_SECURE_BOOT_KEY[] = -{ - &SECURE_BOOT_KEY[0], /* Security boot. Key. - * (length = "None" - 256. - * "3/4" - 192. "REPEAT" - 128) - */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_ABS_DONE_0[] = -{ - &ABS_DONE_0[0], /* Secure boot is enabled for bootloader image. - * EFUSE_RD_ABS_DONE_0 - */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_ENCRYPT_FLASH_KEY[] = -{ - &ENCRYPT_FLASH_KEY[0], /* Flash encrypt. Key. - * (length = "None" - 256. - * "3/4" - 192. "REPEAT" - 128) - */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_ENCRYPT_CONFIG[] = -{ - &ENCRYPT_CONFIG[0], /* Flash encrypt. EFUSE_FLASH_CRYPT_CONFIG_M */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_DISABLE_DL_ENCRYPT[] = -{ - &DISABLE_DL_ENCRYPT[0], /* Flash encrypt. Disable UART bootloader - * encryption. EFUSE_DISABLE_DL_ENCRYPT. - */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_DISABLE_DL_DECRYPT[] = -{ - &DISABLE_DL_DECRYPT[0], /* Flash encrypt. Disable UART bootloader - * decryption. EFUSE_DISABLE_DL_DECRYPT. - */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_DISABLE_DL_CACHE[] = -{ - &DISABLE_DL_CACHE[0], /* Flash encrypt. Disable UART bootloader - * MMU cache. EFUSE_DISABLE_DL_CACHE. - */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_FLASH_CRYPT_CNT[] = -{ - &FLASH_CRYPT_CNT[0], /* Flash encrypt. Flash encryption is enabled - * if this field has an odd number of bits set. - * EFUSE_FLASH_CRYPT_CNT. - */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_DISABLE_JTAG[] = -{ - &DISABLE_JTAG[0], /* Disable JTAG. EFUSE_RD_DISABLE_JTAG. */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_CONSOLE_DEBUG_DISABLE[] = -{ - &CONSOLE_DEBUG_DISABLE[0], /* Disable ROM BASIC interpreter fallback. - * EFUSE_RD_CONSOLE_DEBUG_DISABLE. - */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_UART_DOWNLOAD_DIS[] = -{ - &UART_DOWNLOAD_DIS[0], /* Disable UART download mode. Valid for - * ESP32 V3 and newer - */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_WR_DIS_FLASH_CRYPT_CNT[] = -{ - &WR_DIS_FLASH_CRYPT_CNT[0], /* Flash encrypt. Write protection - * FLASH_CRYPT_CNT - */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_WR_DIS_BLK1[] = -{ - &WR_DIS_BLK1[0], /* Flash encrypt. Write protection - * encryption key. EFUSE_WR_DIS_BLK1 */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_WR_DIS_BLK2[] = -{ - &WR_DIS_BLK2[0], /* Security boot. Write protection security - * key. EFUSE_WR_DIS_BLK2 */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_WR_DIS_BLK3[] = -{ - &WR_DIS_BLK3[0], /* Write protection for EFUSE_BLK3. - * EFUSE_WR_DIS_BLK3 - */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_RD_DIS_BLK1[] = -{ - &RD_DIS_BLK1[0], /* Flash encrypt. efuse_key_read_protected. - * EFUSE_RD_DIS_BLK1 - */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_RD_DIS_BLK2[] = -{ - &RD_DIS_BLK2[0], /* Security boot. efuse_key_read_protected. - * EFUSE_RD_DIS_BLK2 - */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_RD_DIS_BLK3[] = -{ - &RD_DIS_BLK3[0], /* Read protection for EFUSE_BLK3. - * EFUSE_RD_DIS_BLK3 - */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_CHIP_VER_DIS_APP_CPU[] = -{ - &CHIP_VER_DIS_APP_CPU[0], /* EFUSE_RD_CHIP_VER_DIS_APP_CPU */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_CHIP_VER_DIS_BT[] = -{ - &CHIP_VER_DIS_BT[0], /* EFUSE_RD_CHIP_VER_DIS_BT */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_CHIP_VER_PKG[] = -{ - &CHIP_VER_PKG[0], /* EFUSE_RD_CHIP_VER_PKG */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_CHIP_CPU_FREQ_LOW[] = -{ - &CHIP_CPU_FREQ_LOW[0], /* EFUSE_RD_CHIP_CPU_FREQ_LOW */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_CHIP_CPU_FREQ_RATED[] = -{ - &CHIP_CPU_FREQ_RATED[0], /* EFUSE_RD_CHIP_CPU_FREQ_RATED */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_CHIP_VER_REV1[] = -{ - &CHIP_VER_REV1[0], /* EFUSE_RD_CHIP_VER_REV1 */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_CHIP_VER_REV2[] = -{ - &CHIP_VER_REV2[0], /* EFUSE_RD_CHIP_VER_REV2 */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_XPD_SDIO_REG[] = -{ - &XPD_SDIO_REG[0], /* EFUSE_RD_XPD_SDIO_REG */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_SDIO_TIEH[] = -{ - &SDIO_TIEH[0], /* EFUSE_RD_SDIO_TIEH */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_SDIO_FORCE[] = -{ - &SDIO_FORCE[0], /* EFUSE_RD_SDIO_FORCE */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_ADC_VREF_AND_SDIO_DREF[] = -{ - &ADC_VREF_AND_SDIO_DREF[0], /* EFUSE_RD_ADC_VREF[0..4] or - * SDIO_DREFH[0 1] - */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_ADC1_TP_LOW[] = -{ - &ADC1_TP_LOW[0], /* TP_REG EFUSE_RD_ADC1_TP_LOW */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_ADC2_TP_LOW[] = -{ - &ADC2_TP_LOW[0], /* TP_REG EFUSE_RD_ADC2_TP_LOW */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_ADC1_TP_HIGH[] = -{ - &ADC1_TP_HIGH[0], /* TP_REG EFUSE_RD_ADC1_TP_HIGH */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_ADC2_TP_HIGH[] = -{ - &ADC2_TP_HIGH[0], /* TP_REG EFUSE_RD_ADC2_TP_HIGH */ - NULL -}; - -const efuse_desc_t *ESP_EFUSE_SECURE_VERSION[] = -{ - &SECURE_VERSION[0], /* Secure version for anti-rollback */ - NULL -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ diff --git a/arch/xtensa/src/esp32/esp32_emac.c b/arch/xtensa/src/esp32/esp32_emac.c index a0b9787e1cd8e..6be2f45fb5d73 100644 --- a/arch/xtensa/src/esp32/esp32_emac.c +++ b/arch/xtensa/src/esp32/esp32_emac.c @@ -1793,7 +1793,9 @@ static int emac_ifdown(struct net_driver_s *dev) emac_reset_regbits(EMAC_CR_OFFSET, EMAC_TX_E | EMAC_RX_E); - up_disable_irq(priv->cpuint); + /* Disable the Ethernet interrupt */ + + up_disable_irq(ESP32_IRQ_EMAC); /* Cancel the TX timeout timers */ diff --git a/arch/xtensa/src/esp32/esp32_gpio.c b/arch/xtensa/src/esp32/esp32_gpio.c index e6af92aba9b2f..7f36eb7fb33a6 100644 --- a/arch/xtensa/src/esp32/esp32_gpio.c +++ b/arch/xtensa/src/esp32/esp32_gpio.c @@ -35,6 +35,8 @@ #include "xtensa.h" +#include "soc/soc_caps.h" + #include "hardware/esp32_iomux.h" #include "hardware/esp32_gpio.h" diff --git a/arch/xtensa/src/esp32/esp32_gpio.h b/arch/xtensa/src/esp32/esp32_gpio.h index 5d7cc8518e991..a581bbac76973 100644 --- a/arch/xtensa/src/esp32/esp32_gpio.h +++ b/arch/xtensa/src/esp32/esp32_gpio.h @@ -102,6 +102,24 @@ #define ONLOW_WE 0x0c #define ONHIGH_WE 0x0d +/* Check whether it is a valid GPIO number */ + +#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num >= 0) && \ + (((1ULL << (gpio_num)) & \ + SOC_GPIO_VALID_GPIO_MASK) != 0)) + +/* Check whether it can be a valid GPIO number of output mode */ + +#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) \ + ((gpio_num >= 0) && \ + (((1ULL << (gpio_num)) & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) != 0)) + +/* Check whether it can be a valid digital I/O pad */ + +#define GPIO_IS_VALID_DIGITAL_IO_PAD(gpio_num) \ + ((gpio_num >= 0) && \ + (((1ULL << (gpio_num)) & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK) != 0)) + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/arch/xtensa/src/esp32/esp32_himem.c b/arch/xtensa/src/esp32/esp32_himem.c index 5ede3dead3d80..8dd1c0adb01e4 100644 --- a/arch/xtensa/src/esp32/esp32_himem.c +++ b/arch/xtensa/src/esp32/esp32_himem.c @@ -31,6 +31,7 @@ #include "esp32_spiram.h" #include "esp32_himem.h" +#include "esp32_spiflash.h" #include "hardware/esp32_soc.h" /**************************************************************************** @@ -79,8 +80,6 @@ # define SPIRAM_BANKSWITCH_RESERVE 0 #endif -#define CACHE_BLOCKSIZE (32*1024) - /* Start of the virtual address range reserved for himem use */ #define VIRT_HIMEM_RANGE_START (SOC_EXTRAM_DATA_LOW + \ @@ -164,20 +163,6 @@ static inline int rangeblock_idx_valid(int rangeblock_idx) return (rangeblock_idx >= 0 && rangeblock_idx < g_rangeblockcnt); } -static void set_bank(int virt_bank, int phys_bank, int ct) -{ - int r; - - r = cache_sram_mmu_set(0, 0, SOC_EXTRAM_DATA_LOW + CACHE_BLOCKSIZE * - virt_bank, phys_bank * CACHE_BLOCKSIZE, 32, ct); - DEBUGASSERT(r == 0); - r = cache_sram_mmu_set(1, 0, SOC_EXTRAM_DATA_LOW + CACHE_BLOCKSIZE * - virt_bank, phys_bank * CACHE_BLOCKSIZE, 32, ct); - DEBUGASSERT(r == 0); - - UNUSED(r); -} - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -567,9 +552,9 @@ int esp_himem_map(esp_himem_handle_t handle, for (i = 0; i < blockcount; i++) { - set_bank(VIRT_HIMEM_RANGE_BLOCKSTART + range->block_start + i + - range_block, handle->block[i + ram_block] + - PHYS_HIMEM_BLOCKSTART, 1); + esp32_set_bank(VIRT_HIMEM_RANGE_BLOCKSTART + range->block_start + i + + range_block, handle->block[i + ram_block] + + PHYS_HIMEM_BLOCKSTART, 1); } /* Set out pointer */ diff --git a/arch/xtensa/src/esp32/esp32_i2s.c b/arch/xtensa/src/esp32/esp32_i2s.c index 856aafe260f50..fabf4a0c1af28 100644 --- a/arch/xtensa/src/esp32/esp32_i2s.c +++ b/arch/xtensa/src/esp32/esp32_i2s.c @@ -361,6 +361,7 @@ static void i2s_rx_channel_stop(struct esp32_i2s_s *priv); static int i2s_rxchannels(struct i2s_dev_s *dev, uint8_t channels); static uint32_t i2s_rxsamplerate(struct i2s_dev_s *dev, uint32_t rate); static uint32_t i2s_rxdatawidth(struct i2s_dev_s *dev, int bits); +static void i2s_cleanup_queues(struct esp32_i2s_s *priv); static int i2s_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, i2s_callback_t callback, void *arg, uint32_t timeout); @@ -1304,6 +1305,7 @@ static void i2s_rx_worker(void *arg) apb_samp_t samp_size; uint32_t data_copied; + uint8_t carry_bytes; uint8_t padding; uint8_t *buf; uint8_t *samp; @@ -1322,23 +1324,48 @@ static void i2s_rx_worker(void *arg) samp = &bfcontainer->apb->samp[bfcontainer->apb->curbyte]; samp_size = (bfcontainer->apb->nbytes - bfcontainer->apb->curbyte); + data_copied = 0; + buf = bfcontainer->buf; + + /* Copy the remaining bytes from previous transfer and + * complete the sample so that the next memcpy is aligned + * with the sample size. + */ + + if (priv->rx.carry.bytes) + { + memcpy(samp, &priv->rx.carry.value, priv->rx.carry.bytes); + samp += priv->rx.carry.bytes; + data_copied += priv->rx.carry.bytes; + + memcpy(samp, buf, (bytes_per_sample - priv->rx.carry.bytes)); + buf += (bytes_per_sample - priv->rx.carry.bytes); + samp += (bytes_per_sample - priv->rx.carry.bytes); + data_copied += (bytes_per_sample - priv->rx.carry.bytes); + } + /* If there is no need to add padding bytes, the memcpy may be done at * once. Otherwise, the operation must add the padding bytes to each * sample in the internal buffer. */ - data_copied = 0; - buf = bfcontainer->buf + padding; + buf += padding; if (padding) { - while (data_copied < samp_size) + while (data_copied + bytes_per_sample <= samp_size) { memcpy(samp, buf, bytes_per_sample); buf += (bytes_per_sample + padding); samp += bytes_per_sample; data_copied += bytes_per_sample; } + + /* Store the carry bytes, if any */ + + carry_bytes = samp_size - data_copied; + memcpy(&priv->rx.carry.value, buf, carry_bytes); + priv->rx.carry.bytes = carry_bytes; } else { @@ -2815,6 +2842,56 @@ static int i2s_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, } #endif /* I2S_HAVE_RX */ +/**************************************************************************** + * Name: i2s_cleanup_queues + * + * Description: + * Wait for all buffers to be processed and free them after + * + ****************************************************************************/ + +#ifdef I2S_HAVE_RX +static void i2s_cleanup_queues(struct esp32_i2s_s *priv) +{ + irqstate_t flags; + struct esp32_buffer_s *bfcontainer; + + while (sq_peek(&priv->rx.done) != NULL) + { + flags = enter_critical_section(); + bfcontainer = (struct esp32_buffer_s *)sq_remfirst(&priv->rx.done); + leave_critical_section(flags); + bfcontainer->callback(&priv->dev, bfcontainer->apb, + bfcontainer->arg, OK); + apb_free(bfcontainer->apb); + i2s_buf_free(priv, bfcontainer); + } + + while (sq_peek(&priv->rx.act) != NULL) + { + flags = enter_critical_section(); + bfcontainer = (struct esp32_buffer_s *)sq_remfirst(&priv->rx.act); + leave_critical_section(flags); + bfcontainer->callback(&priv->dev, bfcontainer->apb, + bfcontainer->arg, OK); + apb_free(bfcontainer->apb); + i2s_buf_free(priv, bfcontainer); + } + + while (sq_peek(&priv->rx.pend) != NULL) + { + flags = enter_critical_section(); + bfcontainer = (struct esp32_buffer_s *)sq_remfirst(&priv->rx.pend); + leave_critical_section(flags); + bfcontainer->apb->flags |= AUDIO_APB_FINAL; + bfcontainer->callback(&priv->dev, bfcontainer->apb, + bfcontainer->arg, OK); + apb_free(bfcontainer->apb); + i2s_buf_free(priv, bfcontainer); + } +} +#endif /* I2S_HAVE_RX */ + /**************************************************************************** * Name: i2s_ioctl * @@ -2843,6 +2920,25 @@ static int i2s_ioctl(struct i2s_dev_s *dev, int cmd, unsigned long arg) } break; + /* AUDIOIOC_STOP - Stop the audio stream. + * + * ioctl argument: Audio session + */ + + case AUDIOIOC_STOP: + { + i2sinfo("AUDIOIOC_STOP\n"); + +#ifdef I2S_HAVE_RX + struct esp32_i2s_s *priv = (struct esp32_i2s_s *)dev; + + i2s_cleanup_queues(priv); +#endif /* I2S_HAVE_RX */ + + ret = OK; + } + break; + /* AUDIOIOC_ALLOCBUFFER - Allocate an audio buffer * * ioctl argument: pointer to an audio_buf_desc_s structure diff --git a/arch/xtensa/src/esp32/esp32_idle.c b/arch/xtensa/src/esp32/esp32_idle.c index 02cda6119cf34..d5e85f7f430d3 100644 --- a/arch/xtensa/src/esp32/esp32_idle.c +++ b/arch/xtensa/src/esp32/esp32_idle.c @@ -219,7 +219,6 @@ static void esp32_idlepm(void) esp32_pmsleep(CONFIG_PM_SLEEP_WAKEUP_SEC * 1000000 + CONFIG_PM_SLEEP_WAKEUP_NSEC / 1000); } - break; default: break; @@ -227,13 +226,6 @@ static void esp32_idlepm(void) } else { - if (oldstate == PM_NORMAL) - { - /* Relax normal operation */ - - pm_relax(PM_IDLE_DOMAIN, PM_NORMAL); - } - #ifdef CONFIG_WATCHDOG /* Announce the power management state change to feed watchdog */ diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c index 9dae25e49575b..b1d2e00b38098 100644 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ b/arch/xtensa/src/esp32/esp32_irq.c @@ -178,8 +178,9 @@ static bool g_non_iram_int_disabled_flag[CONFIG_SMP_NCPUS]; */ static uint32_t g_cpu0_freeints = ESP32_CPUINT_PERIPHSET & - (~ESP32_WIFI_RESERVE_INT & - ~ESP32_BLE_RESERVE_INT); + ~(ESP32_WIFI_RESERVE_INT | + ESP32_BLE_RESERVE_INT); + #ifdef CONFIG_SMP static uint32_t g_cpu1_freeints = ESP32_CPUINT_PERIPHSET; #endif @@ -517,6 +518,8 @@ void up_irqinitialize(void) /* Hard code special cases. */ g_irqmap[XTENSA_IRQ_TIMER0] = IRQ_MKMAP(0, ESP32_CPUINT_TIMER0); + g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(0, ESP32_CPUINT_SOFTWARE1); + g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(1, ESP32_CPUINT_SOFTWARE1); #ifdef CONFIG_ESP32_WIFI g_irqmap[ESP32_IRQ_MAC] = IRQ_MKMAP(0, ESP32_CPUINT_MAC); @@ -528,9 +531,6 @@ void up_irqinitialize(void) g_irqmap[ESP32_IRQ_RWBLE_IRQ] = IRQ_MKMAP(0, ESP32_PERIPH_RWBLE_IRQ); #endif - g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(0, ESP32_CPUINT_SOFTWARE1); - g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(1, ESP32_CPUINT_SOFTWARE1); - /* Initialize CPU interrupts */ esp32_cpuint_initialize(); @@ -681,7 +681,7 @@ void up_enable_irq(int irq) /* Enable the CPU interrupt now for internal CPU. */ - xtensa_enable_cpuint(&g_intenable[cpu], 1ul << cpuint); + xtensa_enable_cpuint(&g_intenable[cpu], (1ul << cpuint)); } else { @@ -711,8 +711,8 @@ void up_enable_irq(int irq) DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); - /* Attach the interrupt to the peripheral; the CPU interrupt was - * already enabled when allocated. + /* For peripheral interrupts, attach the interrupt to the peripheral; + * the CPU interrupt was already enabled when allocated. */ int periph = ESP32_IRQ2PERIPH(irq); @@ -740,22 +740,7 @@ void up_enable_irq(int irq) } /**************************************************************************** - * Name: xtensa_intstack_top - * - * Description: - * Return a pointer to the top of the correct interrupt stack for the - * given CPU. - * - ****************************************************************************/ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 -uintptr_t xtensa_intstack_top(void) -{ - return g_cpu_intstack_top[up_cpu_index()]; -} - -/**************************************************************************** - * Name: xtensa_intstack_alloc + * Name: up_get_intstackbase * * Description: * Return a pointer to the "alloc" the correct interrupt stack allocation @@ -763,9 +748,10 @@ uintptr_t xtensa_intstack_top(void) * ****************************************************************************/ -uintptr_t xtensa_intstack_alloc(void) +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 +uintptr_t up_get_intstackbase(int cpu) { - return g_cpu_intstack_top[up_cpu_index()] - INTSTACK_SIZE; + return g_cpu_intstack_top[cpu] - INTSTACK_SIZE; } #endif diff --git a/arch/xtensa/src/esp32/esp32_libc_stubs.c b/arch/xtensa/src/esp32/esp32_libc_stubs.c index 66f80472305e2..2cd2bf069591f 100644 --- a/arch/xtensa/src/esp32/esp32_libc_stubs.c +++ b/arch/xtensa/src/esp32/esp32_libc_stubs.c @@ -38,18 +38,12 @@ #include "rom/esp32_libc_stubs.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define _lock_t int - /**************************************************************************** * Private Types ****************************************************************************/ -static mutex_t g_nxlock_common; -static mutex_t g_nxlock_recursive; +static mutex_t g_nxlock_common = NXMUTEX_INITIALIZER; +static mutex_t g_nxlock_recursive = NXMUTEX_INITIALIZER; /* Forward declaration */ @@ -171,64 +165,112 @@ void _raise_r(struct _reent *r) void _lock_init(_lock_t *lock) { - nxmutex_init(&g_nxlock_common); - nxsem_get_value(&g_nxlock_common.sem, lock); + *lock = 0; + + mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t)); + + nxmutex_init(mutex); + + *lock = (_lock_t)mutex; } void _lock_init_recursive(_lock_t *lock) { - nxmutex_init(&g_nxlock_recursive); - nxsem_get_value(&g_nxlock_recursive.sem, lock); + *lock = 0; + + rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t)); + + nxrmutex_init(rmutex); + + *lock = (_lock_t)rmutex; } void _lock_close(_lock_t *lock) { - nxmutex_destroy(&g_nxlock_common); + mutex_t *mutex = (mutex_t *)(*lock); + + nxmutex_destroy(mutex); + kmm_free((void *)(*lock)); *lock = 0; } void _lock_close_recursive(_lock_t *lock) { - nxmutex_destroy(&g_nxlock_recursive); + rmutex_t *rmutex = (rmutex_t *)(*lock); + + nxrmutex_destroy(rmutex); + kmm_free((void *)(*lock)); *lock = 0; } void _lock_acquire(_lock_t *lock) { - nxmutex_lock(&g_nxlock_common); - nxsem_get_value(&g_nxlock_common.sem, lock); + if ((*lock) == 0) + { + mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t)); + + nxmutex_init(mutex); + + *lock = (_lock_t)mutex; + } + + nxmutex_lock((mutex_t *)(*lock)); } void _lock_acquire_recursive(_lock_t *lock) { - nxmutex_lock(&g_nxlock_recursive); - nxsem_get_value(&g_nxlock_recursive.sem, lock); + if ((*lock) == 0) + { + rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t)); + + nxrmutex_init(rmutex); + + *lock = (_lock_t)rmutex; + } + + nxrmutex_lock((rmutex_t *)(*lock)); } int _lock_try_acquire(_lock_t *lock) { - nxmutex_trylock(&g_nxlock_common); - nxsem_get_value(&g_nxlock_common.sem, lock); - return 0; + if ((*lock) == 0) + { + mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t)); + + nxmutex_init(mutex); + + *lock = (_lock_t)mutex; + } + + return nxmutex_trylock((mutex_t *)(*lock)); } int _lock_try_acquire_recursive(_lock_t *lock) { - nxmutex_trylock(&g_nxlock_recursive); - nxsem_get_value(&g_nxlock_recursive.sem, lock); - return 0; + if ((*lock) == 0) + { + rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t)); + + nxrmutex_init(rmutex); + + *lock = (_lock_t)rmutex; + } + + return nxrmutex_trylock((rmutex_t *)(*lock)); } void _lock_release(_lock_t *lock) { - nxmutex_unlock(&g_nxlock_common); - nxsem_get_value(&g_nxlock_common.sem, lock); + mutex_t *mutex = (mutex_t *)(*lock); + + nxmutex_unlock(mutex); } void _lock_release_recursive(_lock_t *lock) { - nxmutex_unlock(&g_nxlock_recursive); - nxsem_get_value(&g_nxlock_recursive.sem, lock); + rmutex_t *rmutex = (rmutex_t *)(*lock); + + nxrmutex_unlock(rmutex); } struct _reent *__getreent(void) diff --git a/arch/xtensa/src/esp32/esp32_openeth.c b/arch/xtensa/src/esp32/esp32_openeth.c new file mode 100644 index 0000000000000..442c0af874a59 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_openeth.c @@ -0,0 +1,863 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_openeth.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_NET_PKT +#include +#endif + +#include "hardware/esp32_soc.h" +#include "esp32_irq.h" + +#ifdef CONFIG_ESP32_OPENETH + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* We need to have the work queue to handle interrupts */ + +#if !defined(CONFIG_SCHED_WORKQUEUE) +#error Worker thread support is required (CONFIG_SCHED_WORKQUEUE) +#endif + +/* These are the register definitions for the OpenCores Ethernet MAC. */ + +/* DMA buffers configuration */ +#define DMA_BUF_SIZE 1600 +#define RX_BUF_COUNT CONFIG_ESP32_OPENETH_DMA_RX_BUFFER_NUM +#define TX_BUF_COUNT CONFIG_ESP32_OPENETH_DMA_TX_BUFFER_NUM + +/* This driver uses the interrupt source number of the internal EMAC + * of the ESP32 chip, and uses the same register address base. This of + * course only works in QEMU, where the OpenCores MAC is mapped to the + * same register base and to the same interrupt source. This driver does + * a sanity check that it is not running on the real ESP32 chip, using + * the EMAC date register. + */ +#define OPENETH_BASE DR_REG_EMAC_BASE + +/* OpenCores ethmac registers */ +#define OPENETH_MODER_REG (OPENETH_BASE + 0x00) +#define OPENETH_MODER_DEFAULT 0xa000 +/* OPENETH_RST: reset the MAC */ +#define OPENETH_RST BIT(11) +/* OPENETH_PRO: enable promiscuous mode */ +#define OPENETH_PRO BIT(5) +/* OPENETH_TXEN: enable transmit */ +#define OPENETH_TXEN BIT(1) +/* OPENETH_RXEN: enable receive */ +#define OPENETH_RXEN BIT(0) + +#define OPENETH_INT_SOURCE_REG (OPENETH_BASE + 0x04) +#define OPENETH_INT_MASK_REG (OPENETH_BASE + 0x08) +/* These bits apply to INT_SOURCE and INT_MASK registers: */ + +/* OPENETH_INT_BUSY: Buffer was received and discarded due + * to lack of buffers + */ +#define OPENETH_INT_BUSY BIT(4) +/* OPENETH_INT_RXB: Frame received */ +#define OPENETH_INT_RXB BIT(2) +/* OPENETH_INT_TXB: Frame transmitted */ +#define OPENETH_INT_TXB BIT(0) + +/* IPGT, IPGR1, IPGR2 registers are not implemented in QEMU, + * hence not used here + */ +#define OPENETH_PACKETLEN_REG (OPENETH_BASE + 0x18) +/* OPENETH_MINFL: minimum frame length */ +#define OPENETH_MINFL_S 16 +#define OPENETH_MINFL_V 0xffff +#define OPENETH_MINFL_M (OPENETH_MINFL_V << OPENETH_MINFL_S) +/* OPENETH_MAXFL: maximum frame length */ +#define OPENETH_MAXFL_S 0 +#define OPENETH_MAXFL_V 0xffff +#define OPENETH_MAXFL_M (OPENETH_MAXFL_V << OPENETH_MAXFL_S) + +/* COLLCONF is not implemented in QEMU */ +#define OPENETH_TX_BD_NUM_REG (OPENETH_BASE + 0x20) +/* CTRLMODER, MIIMODER are not implemented in QEMU */ +#define OPENETH_MIICOMMAND_REG (OPENETH_BASE + 0x2c) +/* OPENETH_WCTRLDATA: write control data */ +#define OPENETH_WCTRLDATA BIT(2) +/* OPENETH_RSTAT: read status */ +#define OPENETH_RSTAT BIT(1) +/* OPENETH_SCANSTAT: scan status */ +#define OPENETH_SCANSTAT BIT(0) + +#define OPENETH_MIIADDRESS_REG (OPENETH_BASE + 0x30) +/* OPENETH_RGAD: register address */ +#define OPENETH_RGAD_S 8 +#define OPENETH_RGAD_V 0x1f +#define OPENETH_RGAD_M (OPENETH_RGAD_V << OPENETH_RGAD_S) +/* OPENETH_FIAD: PHY address */ +#define OPENETH_FIAD_S 0 +#define OPENETH_FIAD_V 0x1f +#define OPENETH_FIAD_N (OPENETH_FIAD_V << OPENETH_FIAD_S) + +#define OPENETH_MIITX_DATA_REG (OPENETH_BASE + 0x34) +#define OPENETH_MIIRX_DATA_REG (OPENETH_BASE + 0x38) +#define OPENETH_MII_DATA_MASK 0xffff + +#define OPENETH_MIISTATUS_REG (OPENETH_BASE + 0x3c) +/* OPENETH_LINKFAIL: link is down */ +#define OPENETH_LINKFAIL BIT(0) + +/* OPENETH_MAC_ADDR0_REG: bytes 2-5 of the MAC address (byte 5 in LSB) */ +#define OPENETH_MAC_ADDR0_REG (OPENETH_BASE + 0x40) +/* OPENETH_MAC_ADDR1_REG: bytes 0-1 of the MAC address (byte 1 in LSB) */ +#define OPENETH_MAC_ADDR1_REG (OPENETH_BASE + 0x44) + +#define OPENETH_HASH0_ADR_REG (OPENETH_BASE + 0x48) +#define OPENETH_HASH1_ADR_REG (OPENETH_BASE + 0x4c) + +/* Location of the DMA descriptors */ +#define OPENETH_DESC_BASE (OPENETH_BASE + 0x400) +/* Total number of (TX + RX) DMA descriptors */ +#define OPENETH_DESC_CNT 128 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* The lo_driver_s encapsulates all state information for a single hardware + * interface + */ + +struct openeth_driver_s +{ + struct work_s openeth_work; /* For deferring poll work to the work queue */ + + int cpuint; /* EMAC interrupt ID */ + + int cur_rx_desc; + int cur_tx_desc; + uint8_t addr[6]; + uint8_t *rx_buf[RX_BUF_COUNT]; + uint8_t *tx_buf[TX_BUF_COUNT]; + + struct work_s rxwork; /* For deferring RX work to the work queue */ + + /* This holds the information visible to the NuttX network */ + + struct net_driver_s dev; /* Interface understood by the network */ +}; + +/* Structures describing TX and RX descriptors. */ + +/* The field names are same as in the OpenCores ethmac documentation. */ + +typedef struct +{ + uint16_t cs : 1; /* !< Carrier sense lost (flag set by HW) */ + uint16_t df : 1; /* !< Defer indication (flag set by HW) */ + uint16_t lc : 1; /* !< Late collision occured (flag set by HW) */ + uint16_t rl : 1; /* !< TX failed due to retransmission limit (flag set by HW) */ + uint16_t rtry : 4; /* !< Number of retries before the frame was sent (set by HW) */ + uint16_t ur : 1; /* !< Underrun status (flag set by HW) */ + uint16_t rsv : 2; /* !< Reserved */ + uint16_t crc : 1; /* !< Add CRC at the end of the packet */ + uint16_t pad : 1; /* !< Add padding to the end of short packets */ + uint16_t wr : 1; /* !< Wrap-around. 0: not the last descriptor in the table, 1: last descriptor. */ + uint16_t irq : 1; /* !< Generate interrupt after this descriptor is transmitted */ + uint16_t rd : 1; /* !< Descriptor ready. 0: descriptor owned by SW, 1: descriptor owned by HW. Cleared by HW. */ + + uint16_t len; /* !< Number of bytes to be transmitted */ + void *txpnt; /* !< Pointer to the data to transmit */ +} openeth_tx_desc_t; + +static_assert(sizeof(openeth_tx_desc_t) == 8, + "incorrect size of openeth_tx_desc_t"); + +typedef struct +{ + uint16_t lc : 1; /* !< Late collision flag */ + uint16_t crc : 1; /* !< RX CRC error flag */ + uint16_t sf : 1; /* !< Frame shorter than set in PACKETLEN register */ + uint16_t tl : 1; /* !< Frame longer than set in PACKETLEN register */ + uint16_t dn : 1; /* !< Dribble nibble (frame length not divisible by 8 bits) flag */ + uint16_t is : 1; /* !< Invalid symbol flag */ + uint16_t or : 1; /* !< Overrun flag */ + uint16_t m : 1; /* !< Frame received because of the promiscuous mode */ + uint16_t rsv : 5; /* !< Reserved */ + uint16_t wr : 1; /* !< Wrap-around. 0: not the last descriptor in the table, 1: last descriptor. */ + uint16_t irq : 1; /* !< Generate interrupt after this descriptor is transmitted */ + uint16_t e : 1; /* !< The buffer is empty. 0: descriptor owned by SW, 1: descriptor owned by HW. */ + + uint16_t len; /* !< Number of bytes received (filled by HW) */ + void *rxpnt; /* !< Pointer to the receive buffer */ +} openeth_rx_desc_t; + +static_assert(sizeof(openeth_rx_desc_t) == 8, + "incorrect size of openeth_rx_desc_t"); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct openeth_driver_s g_openeth; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* NuttX callback functions */ + +static int openeth_ifup(FAR struct net_driver_s *dev); +static int openeth_ifdown(FAR struct net_driver_s *dev); +static int openeth_txavail(FAR struct net_driver_s *dev); +#ifdef CONFIG_NET_MCASTGROUP +static int openeth_addmac(FAR struct net_driver_s *dev, + FAR const uint8_t *mac); +static int openeth_rmmac(FAR struct net_driver_s *dev, + FAR const uint8_t *mac); +#endif +static int openeth_transmit(FAR struct net_driver_s *dev); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline openeth_tx_desc_t *openeth_tx_desc(int idx) +{ + assert(idx < TX_BUF_COUNT); + return &((openeth_tx_desc_t *)OPENETH_DESC_BASE)[idx]; +} + +static inline openeth_rx_desc_t *openeth_rx_desc(int idx) +{ + assert(idx < OPENETH_DESC_CNT - TX_BUF_COUNT); + return &((openeth_rx_desc_t *)OPENETH_DESC_BASE)[idx + TX_BUF_COUNT]; +} + +static inline void openeth_enable(void) +{ + REG_SET_BIT(OPENETH_MODER_REG, OPENETH_TXEN | OPENETH_RXEN | OPENETH_PRO); + REG_SET_BIT(OPENETH_INT_MASK_REG, OPENETH_INT_RXB); +} + +static inline void openeth_disable(void) +{ + REG_CLR_BIT(OPENETH_INT_MASK_REG, OPENETH_INT_RXB); + REG_CLR_BIT(OPENETH_MODER_REG, OPENETH_TXEN | OPENETH_RXEN | OPENETH_PRO); +} + +static inline void openeth_reset(void) +{ + REG_SET_BIT(OPENETH_MODER_REG, OPENETH_RST); + REG_CLR_BIT(OPENETH_MODER_REG, OPENETH_RST); +} + +static inline void openeth_init_tx_desc(openeth_tx_desc_t *desc, void *buf) +{ + *desc = (openeth_tx_desc_t) + { + .rd = 0, + .txpnt = buf, + }; +} + +static inline void openeth_init_rx_desc(openeth_rx_desc_t *desc, void *buf) +{ + *desc = (openeth_rx_desc_t) + { + .e = 1, + .irq = 1, + .rxpnt = buf, + }; +} + +static inline void openeth_set_tx_desc_cnt(int tx_desc_cnt) +{ + assert(tx_desc_cnt <= OPENETH_DESC_CNT); + REG_WRITE(OPENETH_TX_BD_NUM_REG, tx_desc_cnt); +} + +/**************************************************************************** + * Function: openeth_rx_interrupt_work + * + * Description: + * Perform interrupt related work from the worker thread + * + * Input Parameters: + * arg - The argument passed when work_queue() was called. + * + * Returned Value: + * 0 on success + * + * Assumptions: + * Ethernet interrupts are disabled + * + ****************************************************************************/ + +static void openeth_rx_interrupt_work(void *arg) +{ + struct openeth_driver_s *priv = (struct openeth_driver_s *)arg; + struct net_driver_s *dev = &priv->dev; + + net_lock(); + + uint8_t *buffer = NULL; + uint32_t length = 0; + + while (1) + { + openeth_rx_desc_t *desc_ptr = openeth_rx_desc(priv->cur_rx_desc); + openeth_rx_desc_t desc_val = *desc_ptr; + + if (!desc_val.len) + break; + ninfo("desc %d (%p) e=%d len=%d wr=%d", + priv->cur_rx_desc, desc_ptr, desc_val.e, desc_val.len, desc_val.wr); + if (desc_val.e) + { + nerr("ERROR %d", desc_val.e); + goto err; + } + + /* We don't need to copy this anywere. We can just feed it + * to the stack from where it is + */ + + priv->dev.d_buf = desc_val.rxpnt; + priv->dev.d_len = desc_val.len; + struct eth_hdr_s *eth_hdr = (struct eth_hdr_s *)desc_val.rxpnt; + + #ifdef CONFIG_NET_PKT + /* When packet sockets are enabled, feed the frame into the packet tap + */ + + pkt_input(&priv->dev); + #endif + + /* We only accept IP packets of the configured type and ARP packets + */ + + #ifdef CONFIG_NET_IPv4 + if (eth_hdr->type == HTONS(ETHTYPE_IP)) + { + /* Receive an IPv4 packet from the network device */ + + ipv4_input(&priv->dev); + + /* If the above function invocation resulted in data that should be + * sent out on the network, the field d_len will set to a value > 0 + */ + + if (priv->dev.d_len > 0) + { + /* And send the packet */ + + openeth_transmit(&priv->dev); + } + } + else + #endif + #ifdef CONFIG_NET_IPv6 + if (eth_hdr->type == HTONS(ETHTYPE_IP6)) + { + /* Give the IPv6 packet to the network layer */ + + ipv6_input(&priv->dev); + + /* If the above function invocation resulted in data that should be + * sent out on the network, the field d_len will set to a value > 0 + */ + + if (priv->dev.d_len > 0) + { + /* And send the packet */ + + openeth_transmit(&priv->dev); + } + } + else + #endif + #ifdef CONFIG_NET_ARP + if (eth_hdr->type == HTONS(ETHTYPE_ARP)) + { + /* Handle ARP packet */ + + arp_input(&priv->dev); + + /* If the above function invocation resulted in data that should be + * sent out on the network, the field d_len will set to a value > 0 + */ + + if (priv->dev.d_len > 0) + { + /* And send the packet */ + + openeth_transmit(&priv->dev); + } + } + else + #endif + { + nerr("ERROR: Dropped, Unknown type: %04x\n", eth_hdr->type); + } + + desc_val.e = 1; + desc_val.len = 0; + *desc_ptr = desc_val; + + priv->cur_rx_desc = (priv->cur_rx_desc + 1) % RX_BUF_COUNT; + } + +err: + + net_unlock(); +} + +static IRAM_ATTR int openeth_isr_handler(int irq, void *context, void *arg) +{ + struct openeth_driver_s *priv = (struct openeth_driver_s *)arg; + + uint32_t status = REG_READ(OPENETH_INT_SOURCE_REG); + + if (status & OPENETH_INT_RXB) + { + work_queue(LPWORK, &priv->rxwork, openeth_rx_interrupt_work, priv, 0); + } + + if (status & OPENETH_INT_BUSY) + { + ninfo("RX frame dropped (0x%x)", status); + } + + /* Clear interrupt */ + + REG_WRITE(OPENETH_INT_SOURCE_REG, status); + + return 0; +} + +/**************************************************************************** + * Name: openeth_ifup + * + * Description: + * NuttX Callback: Bring up the Ethernet interface when an IP address is + * provided + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int openeth_ifup(FAR struct net_driver_s *dev) +{ + irqstate_t flags; + FAR struct openeth_driver_s *priv = + (FAR struct openeth_driver_s *)dev->d_private; + + /* Disable the Ethernet interrupt */ + + flags = enter_critical_section(); + + /* Enable TX and RX */ + + openeth_enable(); + + leave_critical_section(flags); + + netdev_carrier_on(dev); + + return OK; +} + +/**************************************************************************** + * Name: openeth_ifdown + * + * Description: + * NuttX Callback: Stop the interface. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int openeth_ifdown(FAR struct net_driver_s *dev) +{ + irqstate_t flags; + FAR struct openeth_driver_s *priv = + (FAR struct openeth_driver_s *)dev->d_private; + + /* Disable the Ethernet interrupt */ + + flags = enter_critical_section(); + + /* Disable TX and RX */ + + openeth_enable(); + + leave_critical_section(flags); + + netdev_carrier_off(dev); + + return OK; +} + +static int openeth_transmit(FAR struct net_driver_s *dev) +{ + FAR struct openeth_driver_s *priv = + (FAR struct openeth_driver_s *)dev->d_private; + + int ret = 0; + uint8_t *buf = priv->dev.d_buf; + uint16_t length = priv->dev.d_len; + + if (!buf) + { + nerr("can't set buf to null"); + goto err; + } + + if (!length) + { + nerr("buf length can't be zero"); + goto err; + } + + if (length >= DMA_BUF_SIZE * TX_BUF_COUNT) + { + nerr("insufficient TX buffer size"); + goto err; + } + + uint32_t bytes_remaining = length; + + /* In QEMU, there never is a TX operation in progress, + * so start with descriptor 0. + */ + + while (bytes_remaining > 0) + { + uint32_t will_write = MIN(bytes_remaining, DMA_BUF_SIZE); + + memcpy(priv->tx_buf[priv->cur_tx_desc], buf, will_write); + openeth_tx_desc_t *desc_ptr = openeth_tx_desc(priv->cur_tx_desc); + openeth_tx_desc_t desc_val = *desc_ptr; + desc_val.wr = (priv->cur_tx_desc == TX_BUF_COUNT - 1); + desc_val.len = will_write; + desc_val.rd = 1; + + /* TXEN is already set, and this triggers a TX operation + * for the descriptor + */ + + ninfo("desc %d (%p) len=%d wr=%d", + priv->cur_tx_desc, desc_ptr, will_write, desc_val.wr); + *desc_ptr = desc_val; + bytes_remaining -= will_write; + buf += will_write; + priv->cur_tx_desc = (priv->cur_tx_desc + 1) % TX_BUF_COUNT; + } + + priv->dev.d_buf = NULL; + priv->dev.d_len = 0; + return OK; + +err: + return ERROR; +} + +/**************************************************************************** + * Name: openeth_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int openeth_txavail(FAR struct net_driver_s *dev) +{ + if (IFF_IS_UP(dev->d_flags)) + { + /* In QEMU, the MAC is always available */ + + net_lock(); + + /* poll the network for new XMIT data */ + + devif_poll(dev, openeth_transmit); + + net_unlock(); + } + + return 0; +} + +/**************************************************************************** + * Name: openeth_addmac + * + * Description: + * NuttX Callback: Add the specified MAC address to the hardware multicast + * address filtering + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be added + * + * Returned Value: + * None + * + * Assumptions: + * The default option can allow EMAC receive all multicast frame. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_MCASTGROUP +static int openeth_addmac(FAR struct net_driver_s *dev, + FAR const uint8_t *mac) +{ + ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + + return 0; +} +#endif + +/**************************************************************************** + * Name: openeth_rmmac + * + * Description: + * NuttX Callback: Remove the specified MAC address from the hardware + * multicast address filtering + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be removed + * + * Returned Value: + * None + * + * Assumptions: + * The default option can allow EMAC receive all multicast frame. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_MCASTGROUP +static int openeth_rmmac(FAR struct net_driver_s *dev, + FAR const uint8_t *mac) +{ + ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + + return 0; +} +#endif + +static int openeth_set_addr(uint8_t *addr) +{ + ninfo("set mac\n"); + if (!addr) + { + nerr("can't set mac addr to null"); + goto err; + } + + const uint8_t mac0[4] = { + addr[5], addr[4], addr[3], addr[2] + }; + + const uint8_t mac1[4] = { + addr[1], addr[0] + }; + + uint32_t mac0_u32; + uint32_t mac1_u32; + memcpy(&mac0_u32, &mac0, 4); + memcpy(&mac1_u32, &mac1, 4); + REG_WRITE(OPENETH_MAC_ADDR0_REG, mac0_u32); + REG_WRITE(OPENETH_MAC_ADDR1_REG, mac1_u32); + return 0; +err: + return -1; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: openeth_initialize + * + * Description: + * Initialize the openeth driver + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success; Negated errno on failure. + * + ****************************************************************************/ + +int esp32_openeth_initialize(void) +{ + int ret; + FAR struct openeth_driver_s *priv; + + /* Sanity check */ + + if (REG_READ(OPENETH_MODER_REG) != OPENETH_MODER_DEFAULT) + { + nerr("CONFIG_ESP32_OPENETH should only be used when running in QEMU."); + nerr("When running the app on the ESP32, use ESP32 EMAC instead."); + abort(); + } + + /* Get the interface structure associated with this interface number. */ + + priv = &g_openeth; + + /* Initialize the driver structure */ + + memset(priv, 0, sizeof(struct openeth_driver_s)); + priv->dev.d_ifup = openeth_ifup; /* I/F up (new IP address) callback */ + priv->dev.d_ifdown = openeth_ifdown; /* I/F down callback */ + priv->dev.d_txavail = openeth_txavail; /* New TX data callback */ +#ifdef CONFIG_NET_MCASTGROUP + priv->dev.d_addmac = openeth_addmac; /* Add multicast MAC address */ + priv->dev.d_rmmac = openeth_rmmac; /* Remove multicast MAC address */ +#endif + priv->dev.d_private = priv; /* Used to recover private state from dev */ + + /* Allocate DMA buffers */ + + for (int i = 0; i < RX_BUF_COUNT; i++) + { + priv->rx_buf[i] = calloc(1, DMA_BUF_SIZE); + if (!(priv->rx_buf[i])) + { + nerr("ERROR: Failed allocate RX descriptors\n"); + ret = -ENOMEM; + goto err; + } + + openeth_init_rx_desc(openeth_rx_desc(i), priv->rx_buf[i]); + } + + openeth_rx_desc(RX_BUF_COUNT - 1)->wr = 1; + priv->cur_rx_desc = 0; + + for (int i = 0; i < TX_BUF_COUNT; i++) + { + priv->tx_buf[i] = calloc(1, DMA_BUF_SIZE); + if (!(priv->tx_buf[i])) + { + nerr("ERROR: Failed allocate TX descriptors\n"); + ret = -ENOMEM; + goto err; + } + + openeth_init_tx_desc(openeth_tx_desc(i), priv->tx_buf[i]); + } + + openeth_tx_desc(TX_BUF_COUNT - 1)->wr = 1; + priv->cur_tx_desc = 0; + + /* Setup interrupts */ + + priv->cpuint = esp32_setup_irq(0, ESP32_PERIPH_EMAC, + 1, ESP32_CPUINT_LEVEL); + if (priv->cpuint < 0) + { + nerr("ERROR: Failed allocate interrupt\n"); + ret = -ENOMEM; + goto err; + } + + /* Initialize the MAC */ + + openeth_reset(); + openeth_set_tx_desc_cnt(TX_BUF_COUNT); + memcpy(priv->dev.d_mac.ether.ether_addr_octet, + "\x00\x02\x03\x04\x05\x06\x07\x08", ETH_ALEN); + openeth_set_addr(priv->dev.d_mac.ether.ether_addr_octet); + + /* Attach the interrupt */ + + ret = irq_attach(ESP32_IRQ_EMAC, openeth_isr_handler, priv); + + /* Register the device with the OS so that socket IOCTLs can be + * performed. + */ + + netdev_register(&priv->dev, NET_LL_ETHERNET); + + /* Put the network in the UP state */ + + IFF_SET_UP(priv->dev.d_flags); + return openeth_ifup(&priv->dev); + +err: + nerr("Failed initializing ret = %d", ret); + abort(); +} + +#endif /* CONFIG_ESP32_OPENETH */ diff --git a/arch/xtensa/src/esp32/esp32_pm.c b/arch/xtensa/src/esp32/esp32_pm.c index 28abfcd2207bb..025ae954f430a 100644 --- a/arch/xtensa/src/esp32/esp32_pm.c +++ b/arch/xtensa/src/esp32/esp32_pm.c @@ -502,25 +502,22 @@ static int IRAM_ATTR esp32_get_vddsdio_config( efuse_reg = getreg32(EFUSE_BLK0_RDATA4_REG); - if (efuse_reg & EFUSE_RD_SDIO_FORCE) + if (efuse_reg & EFUSE_RD_XPD_SDIO_FORCE) { /* Get configuration from EFUSE */ result->force = 0; result->enable = (efuse_reg & EFUSE_RD_XPD_SDIO_REG_M) >> EFUSE_RD_XPD_SDIO_REG_S; - result->tieh = (efuse_reg & EFUSE_RD_SDIO_TIEH_M) - >> EFUSE_RD_SDIO_TIEH_S; + result->tieh = (efuse_reg & EFUSE_RD_XPD_SDIO_TIEH_M) + >> EFUSE_RD_XPD_SDIO_TIEH_S; if (REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_BLK3_PART_RESERVE) == 0) { - result->drefh = (efuse_reg & EFUSE_RD_SDIO_DREFH_M) - >> EFUSE_RD_SDIO_DREFH_S; - result->drefm = (efuse_reg & EFUSE_RD_SDIO_DREFM_M) - >> EFUSE_RD_SDIO_DREFM_S; - result->drefl = (efuse_reg & EFUSE_RD_SDIO_DREFL_M) - >> EFUSE_RD_SDIO_DREFL_S; + result->drefh = (efuse_reg >> 8) & 0x3; + result->drefm = (efuse_reg >> 10) & 0x3; + result->drefl = (efuse_reg >> 12) & 0x3; } return OK; diff --git a/arch/xtensa/src/esp32/esp32_psram.c b/arch/xtensa/src/esp32/esp32_psram.c index fb87e0ed8e832..c42c8456fe8bf 100644 --- a/arch/xtensa/src/esp32/esp32_psram.c +++ b/arch/xtensa/src/esp32/esp32_psram.c @@ -44,7 +44,7 @@ #include "rom/esp32_efuse.h" #include "rom/esp32_spiflash.h" -#include "hardware/efuse_reg.h" +#include "hardware/esp32_efuse.h" #ifdef CONFIG_ESP32_SPIRAM @@ -381,25 +381,22 @@ static int IRAM_ATTR esp32_get_vddsdio_config( efuse_reg = getreg32(EFUSE_BLK0_RDATA4_REG); - if (efuse_reg & EFUSE_RD_SDIO_FORCE) + if (efuse_reg & EFUSE_RD_XPD_SDIO_FORCE) { /* Get configuration from EFUSE */ result->force = 0; result->enable = (efuse_reg & EFUSE_RD_XPD_SDIO_REG_M) >> EFUSE_RD_XPD_SDIO_REG_S; - result->tieh = (efuse_reg & EFUSE_RD_SDIO_TIEH_M) - >> EFUSE_RD_SDIO_TIEH_S; + result->tieh = (efuse_reg & EFUSE_RD_XPD_SDIO_TIEH_M) + >> EFUSE_RD_XPD_SDIO_TIEH_S; if (REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_BLK3_PART_RESERVE) == 0) { - result->drefh = (efuse_reg & EFUSE_RD_SDIO_DREFH_M) - >> EFUSE_RD_SDIO_DREFH_S; - result->drefm = (efuse_reg & EFUSE_RD_SDIO_DREFM_M) - >> EFUSE_RD_SDIO_DREFM_S; - result->drefl = (efuse_reg & EFUSE_RD_SDIO_DREFL_M) - >> EFUSE_RD_SDIO_DREFL_S; + result->drefh = (efuse_reg >> 8) & 0x3; + result->drefm = (efuse_reg >> 10) & 0x3; + result->drefl = (efuse_reg >> 12) & 0x3; } return OK; @@ -1514,8 +1511,10 @@ psram_enable(int mode, int vaddrmode) /* psram init */ 0 }; - uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, - EFUSE_RD_CHIP_VER_PKG); + uint32_t chip_ver = (REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, + EFUSE_RD_CHIP_PACKAGE_4BIT) << 3) | + REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, + EFUSE_RD_CHIP_PACKAGE); uint32_t pkg_ver = chip_ver & 0x7; uint32_t spiconfig; @@ -1613,7 +1612,7 @@ psram_enable(int mode, int vaddrmode) /* psram init */ } } - assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode."); + ASSERT(mode < PSRAM_CACHE_MAX && "we don't support any other mode."); s_psram_mode = mode; putreg32(0x1, SPI_EXT3_REG(0)); diff --git a/arch/xtensa/src/esp32/esp32_rmt.c b/arch/xtensa/src/esp32/esp32_rmt.c deleted file mode 100644 index 71d9489691391..0000000000000 --- a/arch/xtensa/src/esp32/esp32_rmt.c +++ /dev/null @@ -1,433 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_rmt.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "xtensa.h" - -#include "esp32_gpio.h" -#include "esp32_rmt.h" -#include "esp32_irq.h" -#include "esp32_clockconfig.h" - -#include "hardware/esp32_dport.h" -#include "hardware/esp32_gpio_sigmap.h" - -#ifdef CONFIG_ESP32_RMT - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* RMT methods */ - -static void rmt_reset(struct rmt_dev_s *dev); -static int rmt_setup(struct rmt_dev_s *dev); -IRAM_ATTR static int rmt_interrupt(int irq, void *context, void *arg); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -struct rmt_dev_s g_rmt_dev = -{ - .periph = ESP32_PERIPH_RMT, - .irq = ESP32_IRQ_RMT, - .cpu = 0, - .cpuint = -ENOMEM, - .lock = 0 -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: rmt_reset - * - * Description: - * Reset the RMT device. Called early to initialize the hardware. This - * function is called, before esp32_rmt_setup(). - * - * Input Parameters: - * dev - An instance of the "upper half" RMT driver state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void rmt_reset(struct rmt_dev_s *dev) -{ - irqstate_t flags; - - flags = spin_lock_irqsave(&dev->lock); - - modifyreg32(DPORT_PERIP_RST_EN_REG, 0, DPORT_RMT_RST); - modifyreg32(DPORT_PERIP_RST_EN_REG, DPORT_RMT_RST, 0); - - /* Clear any spurious IRQ Flag */ - - putreg32(0xffffffff, RMT_INT_CLR_REG); - - /* Enable memory wrap-around */ - - modifyreg32(RMT_APB_CONF_REG, 0 , BIT(1)); - - spin_unlock_irqrestore(&dev->lock, flags); -} - -/**************************************************************************** - * Name: rmt_setup - * - * Description: - * Configure the RMT. This method is called the first time that the RMT - * device is opened. This will occur when the port is first opened. - * This setup includes configuring and attaching RMT interrupts. - * - * Input Parameters: - * dev - An instance of the "upper half" RMT driver state structure. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -static int rmt_setup(struct rmt_dev_s *dev) -{ - irqstate_t flags; - int ret = OK; - - flags = spin_lock_irqsave(&dev->lock); - - if (dev->cpuint != -ENOMEM) - { - /* Disable the provided CPU Interrupt to configure it. */ - - up_disable_irq(dev->cpuint); - } - - dev->cpu = up_cpu_index(); - dev->cpuint = esp32_setup_irq(dev->cpu, dev->periph, - 1, ESP32_CPUINT_LEVEL); - if (dev->cpuint < 0) - { - /* Failed to allocate a CPU interrupt of this type. */ - - ret = dev->cpuint; - spin_unlock_irqrestore(&dev->lock, flags); - - return ret; - } - - ret = irq_attach(dev->irq, rmt_interrupt, dev); - - if (ret != OK) - { - /* Failed to attach IRQ, so CPU interrupt must be freed. */ - - esp32_teardown_irq(dev->cpu, dev->periph, dev->cpuint); - dev->cpuint = -ENOMEM; - spin_unlock_irqrestore(&dev->lock, flags); - - return ret; - } - - /* Enable the CPU interrupt that is linked to the RMT device. */ - - up_enable_irq(dev->irq); - - spin_unlock_irqrestore(&dev->lock, flags); - - return ret; -} - -/**************************************************************************** - * Name: rmt_load_tx_buffer - * - * Description: - * Copies chunks of data from the buffer to the RMT device memory - * This function can also be called on the first transmission data chunk - * - * Input Parameters: - * channel - Pointer to the channel to be reloaded - * - * Returned Value: - * None - * - ****************************************************************************/ - -IRAM_ATTR void rmt_load_tx_buffer(struct rmt_dev_channel_s *channel) -{ - uint32_t *src = channel->src; - uint32_t dst_mem; - uint32_t buffer_size; - - if (channel->src_offset == 0) - { - buffer_size = channel->available_words; - dst_mem = channel->start_address; - channel->next_buffer = 0; - } - else - { - buffer_size = channel->reload_thresh; - dst_mem = channel->start_address + - 4*channel->next_buffer*channel->reload_thresh; - - /* only swap buffers after the first call */ - - if (channel->next_buffer == 0) - { - channel->next_buffer = 1; - } - else - { - channel->next_buffer = 0; - } - } - - while (channel->src_offset < channel->words_to_send && buffer_size > 0) - { - uint32_t word_to_send = *(src + channel->src_offset); - putreg32(word_to_send, dst_mem); - - channel->src_offset++; - dst_mem += 4; - buffer_size--; - } - - /* Adding 0x00 on RMT's buffer marks the EOT */ - - if (channel->src_offset == channel->words_to_send && buffer_size > 0) - { - putreg32(0x00, dst_mem); - } -} - -/**************************************************************************** - * Name: rmt_interrupt - * - * Description: - * RMT TX interrupt handler - * - * Input Parameters: - * irq - The IRQ number of the interrupt. - * context - The register state save array at the time of the interrupt. - * arg - The pointer to driver structure. - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -IRAM_ATTR static int rmt_interrupt(int irq, void *context, void *arg) -{ - struct rmt_dev_s *dev = (struct rmt_dev_s *)arg; - uint32_t regval = getreg32(RMT_INT_ST_REG); - - uint8_t error_flag = 0; - - int flags = spin_lock_irqsave(&dev->lock); - - for (int ch_idx = 0; ch_idx < RMT_NUMBER_OF_CHANNELS; ch_idx++) - { - struct rmt_dev_channel_s *channel_data = - (struct rmt_dev_channel_s *) &(dev->channels[ch_idx]); - - /* IRQs from channels with no pins, should be ignored */ - - if (channel_data->output_pin < 0) - { - putreg32(RMT_CHN_TX_THR_EVENT_INT_CLR(ch_idx), RMT_INT_CLR_REG); - putreg32(RMT_CHN_TX_END_INT_CLR(ch_idx), RMT_INT_CLR_REG); - continue; - } - - if (regval & RMT_CHN_TX_THR_EVENT_INT_ST(ch_idx)) - { - putreg32(RMT_CHN_TX_THR_EVENT_INT_CLR(ch_idx), RMT_INT_CLR_REG); - - /* buffer refill */ - - rmt_load_tx_buffer(channel_data); - } - else if (regval & RMT_CHN_TX_END_INT_ST(ch_idx)) - { - /* end of transmission */ - - modifyreg32(RMT_INT_ENA_REG, - RMT_CHN_TX_END_INT_ENA(ch_idx) | - RMT_CHN_TX_THR_EVENT_INT_ENA(ch_idx), - 0 - ); - - putreg32(RMT_CHN_TX_END_INT_CLR(ch_idx), RMT_INT_CLR_REG); - putreg32(RMT_CHN_TX_THR_EVENT_INT_CLR(ch_idx), RMT_INT_CLR_REG); - - /* release the lock so the write function can return */ - - nxsem_post(&channel_data->tx_sem); - } - } - - if (error_flag) - { - /* clear any spurious IRQ flag */ - - putreg32(0xffffffff, RMT_INT_CLR_REG); - } - - spin_unlock_irqrestore(&dev->lock, flags); - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32_rmtinitialize - * - * Description: - * Initialize the selected RMT device - * - * Input Parameters: - * - * Returned Value: - * Valid RMT device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct rmt_dev_s *esp32_rmtinitialize(void) -{ - struct rmt_dev_s *rmtdev = &g_rmt_dev; - irqstate_t flags; - - flags = spin_lock_irqsave(&rmtdev->lock); - - modifyreg32(DPORT_PERIP_CLK_EN_REG, 0, DPORT_RMT_CLK_EN); - modifyreg32(DPORT_PERIP_RST_EN_REG, DPORT_RMT_RST, 0); - - spin_unlock_irqrestore(&rmtdev->lock, flags); - - rmt_reset(rmtdev); - rmt_setup(rmtdev); - - rmtdev->channels = kmm_zalloc(sizeof(struct rmt_dev_channel_s) * - RMT_NUMBER_OF_CHANNELS); - if (!rmtdev->channels) - { - rmterr("Failed to allocate memory for RMT Channels"); - return NULL; - } - - for (int ch_idx = 0; ch_idx < RMT_NUMBER_OF_CHANNELS; ch_idx++) - { - struct rmt_dev_channel_s *channel_data = - (struct rmt_dev_channel_s *) &(rmtdev->channels[ch_idx]); - - channel_data->open_count = 0; - channel_data->ch_idx = ch_idx; - channel_data->output_pin = -1; - - channel_data->available_words = 64; - uint32_t start_addr_chn = RMT_DATA_BASE_ADDR + - RMT_DATA_MEMORY_BLOCK_WORDS * 4 * ch_idx; - - channel_data->start_address = start_addr_chn; - channel_data->reload_thresh = channel_data->available_words / 2; - channel_data->parent_dev = rmtdev; - } - - return rmtdev; -} - -/**************************************************************************** - * Name: rmt_attach_pin_to_channel - * - * Description: - * Binds a gpio pin to a RMT channel - * - * Input Parameters: - * rmtdev - pointer the rmt device, needed for the locks - * output_pin - the pin used for output - * channel - the RMT's channel that will be used - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -int rmt_attach_pin_to_channel(struct rmt_dev_s *rmtdev, int ch_idx, int pin) -{ - irqstate_t flags; - - if (ch_idx >= RMT_NUMBER_OF_CHANNELS || pin < 0) - { - return -EINVAL; - } - - flags = spin_lock_irqsave(&rmtdev->lock); - - struct rmt_dev_channel_s *channel_data = - (struct rmt_dev_channel_s *) &(rmtdev->channels[ch_idx]); - - channel_data->output_pin = pin; - nxsem_init(&channel_data->tx_sem, 0, 1); - - /* Configure RMT GPIO pin */ - - esp32_gpio_matrix_out(pin, RMT_SIG_OUT0_IDX + ch_idx, 0, 0); - esp32_configgpio(pin, OUTPUT_FUNCTION_1); - - spin_unlock_irqrestore(&rmtdev->lock, flags); - - return OK; -} - -#endif diff --git a/arch/xtensa/src/esp32/esp32_rmt.h b/arch/xtensa/src/esp32/esp32_rmt.h deleted file mode 100644 index a7625339578a1..0000000000000 --- a/arch/xtensa/src/esp32/esp32_rmt.h +++ /dev/null @@ -1,164 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_rmt.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_RMT_H -#define __ARCH_XTENSA_SRC_ESP32_ESP32_RMT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include "hardware/esp32_rmt.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -struct rmt_dev_channel_s -{ - /* Parameters for each RMT channel */ - - int open_count; /* Unused */ - int ch_idx; /* RMT channel number (0-7) */ - int output_pin; /* GPIO pin number attached to the RMT */ - int next_buffer; /* Tracking buffer (0 or 1) used next reload */ - sem_t tx_sem; /* Semaphore structure */ - - uint32_t *src; /* Data to be copied to the internal buffer */ - uint32_t src_offset; /* Offset pointer to the src */ - size_t words_to_send; /* Number of 32-bit words to be sent */ - uint32_t available_words; /* Counter of available words in the src */ - uint32_t start_address; /* Current RMT register buffer address */ - uint32_t reload_thresh; /* Threshold for reloading the internal buffer */ - void *parent_dev; /* Pointer to the parent RMT device structure */ -}; - -struct rmt_dev_s -{ - /* Device configuration */ - - uint8_t periph; /* Peripheral ID */ - uint8_t irq; /* IRQ associated with this RMT */ - uint8_t cpu; /* CPU ID */ - int cpuint; /* CPU interrupt assigned to this RMT */ - spinlock_t lock; - - struct rmt_dev_channel_s *channels; -}; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ -#ifdef __cplusplus -extern "C" -{ -#endif - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -#if defined(CONFIG_ESP32_RMT) - -/**************************************************************************** - * Name: rmt_load_tx_buffer - * - * Description: - * Copies chunks of data from the buffer to the RMT device memory - * This function can also be called on the first transmission data chunk - * - * Input Parameters: - * channel - Pointer to the channel to be reloaded - * - * Returned Value: - * None - * - ****************************************************************************/ - -IRAM_ATTR void rmt_load_tx_buffer(struct rmt_dev_channel_s *channel); - -/**************************************************************************** - * Name: esp32_rmtinitialize - * - * Description: - * Initialize the selected RMT device - * - * Input Parameters: - * - * Returned Value: - * Valid RMT device structure reference on success; a NULL on failure - * - ****************************************************************************/ - -struct rmt_dev_s *esp32_rmtinitialize(void); - -/**************************************************************************** - * Name: rmt_attach_pin_to_channel - * - * Description: - * Binds a gpio pin to a RMT channel - * - * Input Parameters: - * rmtdev - pointer the rmt device, needed for the locks - * output_pin - the pin used for output - * channel - the RMT's channel that will be used - * - * Returned Value: - * Zero on success; a negated errno on failure - * - ****************************************************************************/ - -int rmt_attach_pin_to_channel(struct rmt_dev_s *rmtdev, int ch_idx, int pin); - -/**************************************************************************** - * Name: board_rmt_initialize - * - * Description: - * Initialize RMT driver and register the channel/pin pair at /dev/rtm0 - * - * Input Parameters: - * output_pin - the output pin to assing to the channel - * channel - the channel that will be initialized - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int board_rmt_initialize(int output_pin, int channel); - -#endif - -#ifdef __cplusplus -} -#endif -#endif /* __ASSEMBLY__ */ - -#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_RMT_H */ diff --git a/arch/xtensa/src/esp32/esp32_rng.c b/arch/xtensa/src/esp32/esp32_rng.c index cfecced69c9a0..4d83b6a5b3d78 100644 --- a/arch/xtensa/src/esp32/esp32_rng.c +++ b/arch/xtensa/src/esp32/esp32_rng.c @@ -44,6 +44,8 @@ #include "hardware/wdev_reg.h" #include "esp32_clockconfig.h" +#include "esp_random.h" + #if defined(CONFIG_ESP32_RNG) #if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) @@ -81,42 +83,6 @@ static const struct file_operations g_rngops = * Private functions ****************************************************************************/ -/**************************************************************************** - * Name: esp32_random - ****************************************************************************/ - -uint32_t IRAM_ATTR esp_random(void) -{ - /* The PRNG which implements WDEV_RANDOM register gets 2 bits - * of extra entropy from a hardware randomness source every APB clock cycle - * (provided Wi-Fi or BT are enabled). To make sure entropy is not drained - * faster than it is added, this function needs to wait for at least 16 APB - * clock cycles after reading previous word. This implementation may - * actually wait a bit longer due to extra time spent in arithmetic and - * branch statements. - * - * As a (probably unnecessary) precaution to avoid returning the - * RNG state as-is, the result is XORed with additional - * WDEV_RND_REG reads while waiting. - */ - - uint32_t cpu_to_apb_freq_ratio = esp_clk_cpu_freq() / esp_clk_apb_freq(); - - static uint32_t last_ccount = 0; - uint32_t ccount; - uint32_t result = 0; - - do - { - ccount = XTHAL_GET_CCOUNT(); - result ^= getreg32(WDEV_RND_REG); - } - while (ccount - last_ccount < cpu_to_apb_freq_ratio * 16); - - last_ccount = ccount; - return result ^ getreg32(WDEV_RND_REG); -} - /**************************************************************************** * Name: esp32_rng_read ****************************************************************************/ diff --git a/arch/xtensa/src/esp32/esp32_rt_timer.c b/arch/xtensa/src/esp32/esp32_rt_timer.c index 27c1771506ba7..88f2ecc0184a9 100644 --- a/arch/xtensa/src/esp32/esp32_rt_timer.c +++ b/arch/xtensa/src/esp32/esp32_rt_timer.c @@ -33,6 +33,7 @@ #include #include +#include #include #include #include @@ -316,7 +317,7 @@ static int rt_timer_thread(int argc, char *argv[]) if (ret) { tmrerr("ERROR: Wait priv->toutsem error=%d\n", ret); - assert(0); + ASSERT(0); } flags = spin_lock_irqsave(&priv->lock); diff --git a/arch/xtensa/src/esp32/esp32_rtc.c b/arch/xtensa/src/esp32/esp32_rtc.c index 35e87861a9c6c..779ced3df327a 100644 --- a/arch/xtensa/src/esp32/esp32_rtc.c +++ b/arch/xtensa/src/esp32/esp32_rtc.c @@ -34,6 +34,7 @@ #include "esp32_clockconfig.h" #include "esp32_rt_timer.h" +#include "hardware/esp32_apb_ctrl.h" #include "hardware/esp32_rtccntl.h" #include "hardware/esp32_rtc_io.h" #include "hardware/esp32_dport.h" @@ -864,9 +865,6 @@ uint32_t IRAM_ATTR esp32_rtc_clk_cal(enum esp32_rtc_cal_sel_e cal_clk, return period; } -enum esp32_rtc_xtal_freq_e rtc_get_xtal(void) - __attribute__((alias("esp32_rtc_clk_xtal_freq_get"))); - /**************************************************************************** * Name: esp32_rtc_clk_xtal_freq_get * diff --git a/arch/xtensa/src/esp32/esp32_spiflash.c b/arch/xtensa/src/esp32/esp32_spiflash.c index 241679f0ab447..6b19153720ec8 100644 --- a/arch/xtensa/src/esp32/esp32_spiflash.c +++ b/arch/xtensa/src/esp32/esp32_spiflash.c @@ -51,7 +51,7 @@ #include "hardware/esp32_soc.h" #include "hardware/esp32_spi.h" #include "hardware/esp32_dport.h" -#include "hardware/efuse_reg.h" +#include "hardware/esp32_efuse.h" #include "esp32_spicache.h" #ifdef CONFIG_ESP32_SPIRAM @@ -113,6 +113,7 @@ enum spiflash_op_code_e SPIFLASH_OP_CODE_WRITE = 0, SPIFLASH_OP_CODE_READ, SPIFLASH_OP_CODE_ERASE, + SPIFLASH_OP_CODE_SET_BANK, SPIFLASH_OP_CODE_ENCRYPT_READ, SPIFLASH_OP_CODE_ENCRYPT_WRITE }; @@ -188,6 +189,7 @@ struct spiflash_work_arg uint32_t addr; uint8_t *buffer; uint32_t size; + uint32_t paddr; } op_arg; volatile int ret; @@ -290,6 +292,9 @@ static int esp32_ioctl(struct mtd_dev_s *dev, int cmd, unsigned long arg); static int esp32_ioctl_encrypt(struct mtd_dev_s *dev, int cmd, unsigned long arg); +#ifdef CONFIG_ESP32_SPIRAM +static int esp32_set_mmu_map(int vaddr, int paddr, int num); +#endif /**************************************************************************** * Private Data @@ -458,18 +463,22 @@ static inline void spi_reset_regbits(struct esp32_spiflash_s *priv, static void esp32_spiflash_opstart(void) { struct tcb_s *tcb = this_task(); - int cpu = up_cpu_index(); int saved_priority = tcb->sched_priority; + int cpu; #ifdef CONFIG_SMP - int other_cpu = cpu ? 0 : 1; + int other_cpu; #endif - - DEBUGASSERT(cpu == 0 || cpu == 1); - /* Temporary raise schedule priority */ nxsched_set_priority(tcb, SCHED_PRIORITY_MAX); + cpu = up_cpu_index(); +#ifdef CONFIG_SMP + other_cpu = cpu == 1 ? 0 : 1; +#endif + + DEBUGASSERT(cpu == 0 || cpu == 1); + #ifdef CONFIG_SMP DEBUGASSERT(other_cpu == 0 || other_cpu == 1); DEBUGASSERT(other_cpu != cpu); @@ -1640,6 +1649,14 @@ static void esp32_spiflash_work(void *p) work_arg->op_arg.addr, work_arg->op_arg.size); } +#ifdef CONFIG_ESP32_SPIRAM + else if (work_arg->op_code == SPIFLASH_OP_CODE_SET_BANK) + { + work_arg->ret = esp32_set_mmu_map(work_arg->op_arg.addr, + work_arg->op_arg.paddr, + work_arg->op_arg.size); + } +#endif else if (work_arg->op_code == SPIFLASH_OP_CODE_ENCRYPT_READ) { esp32_set_read_opt(work_arg->op_arg.priv); @@ -1682,7 +1699,8 @@ static int esp32_async_op(enum spiflash_op_code_e opcode, struct esp32_spiflash_s *priv, uint32_t addr, const uint8_t *buffer, - uint32_t size) + uint32_t size, + uint32_t paddr) { int ret; struct spiflash_work_arg work_arg = @@ -1694,6 +1712,7 @@ static int esp32_async_op(enum spiflash_op_code_e opcode, .addr = addr, .buffer = (uint8_t *)buffer, .size = size, + .paddr = paddr, }, .sem = NXSEM_INITIALIZER(0, 0) }; @@ -1751,7 +1770,8 @@ static int esp32_erase(struct mtd_dev_s *dev, off_t startblock, #ifdef CONFIG_ESP32_SPI_FLASH_SUPPORT_PSRAM_STACK if (stack_is_psram()) { - ret = esp32_async_op(SPIFLASH_OP_CODE_ERASE, priv, addr, NULL, size); + ret = esp32_async_op(SPIFLASH_OP_CODE_ERASE, priv, addr, NULL, + size, 0); } else { @@ -1813,7 +1833,7 @@ static ssize_t esp32_read(struct mtd_dev_s *dev, off_t offset, if (stack_is_psram()) { ret = esp32_async_op(SPIFLASH_OP_CODE_READ, priv, - offset, buffer, nbytes); + offset, buffer, nbytes, 0); } else { @@ -1925,7 +1945,7 @@ static ssize_t esp32_read_decrypt(struct mtd_dev_s *dev, if (stack_is_psram()) { ret = esp32_async_op(SPIFLASH_OP_CODE_ENCRYPT_READ, priv, - offset, buffer, nbytes); + offset, buffer, nbytes, 0); } else { @@ -2040,7 +2060,7 @@ static ssize_t esp32_write(struct mtd_dev_s *dev, off_t offset, if (stack_is_psram()) { ret = esp32_async_op(SPIFLASH_OP_CODE_WRITE, priv, - offset, buffer, nbytes); + offset, buffer, nbytes, 0); } else { @@ -2157,7 +2177,7 @@ static ssize_t esp32_bwrite_encrypt(struct mtd_dev_s *dev, if (stack_is_psram()) { ret = esp32_async_op(SPIFLASH_OP_CODE_ENCRYPT_WRITE, priv, - offset, buffer, nbytes); + offset, buffer, nbytes, 0); } else { @@ -2463,10 +2483,78 @@ int spiflash_init_spi_flash_op_block_task(int cpu) } #endif /* CONFIG_SMP */ +#ifdef CONFIG_ESP32_SPIRAM + +/**************************************************************************** + * Name: esp32_set_mmu_map + * + * Description: + * Set Ext-SRAM-Cache mmu mapping. + * + * Input Parameters: + * vaddr - Virtual address in CPU address space + * paddr - Physical address in Ext-SRAM + * num - Pages to be set + * + * Returned Value: + * 0 if success or a negative value if fail. + * + ****************************************************************************/ + +static int esp32_set_mmu_map(int vaddr, int paddr, int num) +{ + int ret; + ret = cache_sram_mmu_set(0, 0, vaddr, paddr, 32, num); + DEBUGASSERT(ret == 0); + ret = cache_sram_mmu_set(1, 0, vaddr, paddr, 32, num); + return ret; +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ +#ifdef CONFIG_ESP32_SPIRAM + +/**************************************************************************** + * Name: esp32_set_bank + * + * Description: + * Set Ext-SRAM-Cache mmu mapping. + * + * Input Parameters: + * virt_bank - Beginning of the virtual bank + * phys_bank - Beginning of the physical bank + * ct - Number of banks + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32_set_bank(int virt_bank, int phys_bank, int ct) +{ + int ret; + uint32_t vaddr = SOC_EXTRAM_DATA_LOW + CACHE_BLOCKSIZE * virt_bank; + uint32_t paddr = phys_bank * CACHE_BLOCKSIZE; +#ifdef CONFIG_ESP32_SPI_FLASH_SUPPORT_PSRAM_STACK + if (stack_is_psram()) + { + ret = esp32_async_op(SPIFLASH_OP_CODE_SET_BANK, NULL, vaddr, NULL, + ct, paddr); + } + else +#endif + { + ret = esp32_set_mmu_map(vaddr, paddr, ct); + } + + DEBUGASSERT(ret == 0); + UNUSED(ret); +} +#endif + /**************************************************************************** * Name: esp32_spiflash_init * diff --git a/arch/xtensa/src/esp32/esp32_spiflash.h b/arch/xtensa/src/esp32/esp32_spiflash.h index be8c452639936..a885294a8d4e7 100644 --- a/arch/xtensa/src/esp32/esp32_spiflash.h +++ b/arch/xtensa/src/esp32/esp32_spiflash.h @@ -44,10 +44,38 @@ extern "C" #define EXTERN extern #endif +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CACHE_BLOCKSIZE (32*1024) + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ +#ifdef CONFIG_ESP32_SPIRAM + +/**************************************************************************** + * Name: esp32_set_bank + * + * Description: + * Set Ext-SRAM-Cache mmu mapping. + * + * Input Parameters: + * virt_bank - Beginning of the virtual bank + * phys_bank - Beginning of the physical bank + * ct - Number of banks + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32_set_bank(int virt_bank, int phys_bank, int ct); + +#endif + /**************************************************************************** * Name: esp32_spiflash_init * diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c index 0422dd7a3e532..30679d7840c04 100644 --- a/arch/xtensa/src/esp32/esp32_start.c +++ b/arch/xtensa/src/esp32/esp32_start.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -35,6 +36,7 @@ #include "xtensa_attr.h" #include "esp32_clockconfig.h" +#include "esp32_efuse.h" #include "esp32_region.h" #include "esp32_start.h" #include "esp32_spiram.h" @@ -91,8 +93,9 @@ extern uint8_t _image_drom_size[]; * ROM Function Prototypes ****************************************************************************/ -#ifdef CONFIG_ESP32_APP_FORMAT_MCUBOOT extern int ets_printf(const char *fmt, ...) printf_like(1, 2); + +#ifdef CONFIG_ESP32_APP_FORMAT_MCUBOOT extern void cache_read_enable(int cpu); extern void cache_read_disable(int cpu); extern void cache_flush(int cpu); @@ -143,6 +146,7 @@ static noreturn_function void __esp32_start(void) { uint32_t sp; uint32_t regval unused_data; + uint32_t chip_rev; /* Make sure that normal interrupts are disabled. This is really only an * issue when we are started in un-usual ways (such as from IRAM). In this @@ -222,6 +226,26 @@ static noreturn_function void __esp32_start(void) showprogress('A'); + chip_rev = esp_efuse_hal_chip_revision(); + + _info("ESP32 chip revision is v%d.%01d\n", chip_rev / 100, chip_rev % 100); + + if (chip_rev < 300) + { +#ifndef ESP32_IGNORE_CHIP_REVISION_CHECK + ets_printf("ERROR: NuttX supports ESP32 chip revision >= v3.0" + " (chip revision is v%d.%01d)\n", + chip_rev / 100, chip_rev % 100); + PANIC(); +#endif + ets_printf("WARNING: NuttX supports ESP32 chip revision >= v3.0" + " (chip is v%d.%01d).\n" + "Ignoring this error and continuing because " + "`ESP32_IGNORE_CHIP_REVISION_CHECK` is set...\n" + "THIS MAY NOT WORK! DON'T USE THIS CHIP IN PRODUCTION!\n", + chip_rev / 100, chip_rev % 100); + } + #if defined(CONFIG_ESP32_SPIRAM_BOOT_INIT) if (esp_spiram_init() != OK) { diff --git a/arch/xtensa/src/esp32/esp32_tim_lowerhalf.c b/arch/xtensa/src/esp32/esp32_tim_lowerhalf.c index d6c0296fef87e..819091bbe413a 100644 --- a/arch/xtensa/src/esp32/esp32_tim_lowerhalf.c +++ b/arch/xtensa/src/esp32/esp32_tim_lowerhalf.c @@ -490,7 +490,7 @@ static void esp32_timer_setcallback(struct timer_lowerhalf_s *lower, } spin_unlock_irqrestore(&priv->lock, flags); - assert(ret == OK); + ASSERT(ret == OK); } /**************************************************************************** diff --git a/arch/xtensa/src/esp32/esp32_touch.h b/arch/xtensa/src/esp32/esp32_touch.h index 1f126b88ccfa2..d48d3b4c61f4c 100644 --- a/arch/xtensa/src/esp32/esp32_touch.h +++ b/arch/xtensa/src/esp32/esp32_touch.h @@ -29,7 +29,7 @@ #include #include -#include "esp32_touch_lowerhalf.h" +#include "hardware/esp32_touch.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/xtensa/src/esp32/esp32_twai.c b/arch/xtensa/src/esp32/esp32_twai.c index 154f6ede5f822..afa4e4b0919e5 100644 --- a/arch/xtensa/src/esp32/esp32_twai.c +++ b/arch/xtensa/src/esp32/esp32_twai.c @@ -48,6 +48,9 @@ #include "hardware/esp32_dport.h" #include "hardware/esp32_gpio_sigmap.h" +#include "hardware/esp32_twai.h" + +#include "soc/soc.h" #if defined(CONFIG_ESP32_TWAI) diff --git a/arch/xtensa/src/esp32/esp32_twai.h b/arch/xtensa/src/esp32/esp32_twai.h index d1478906806b3..9ecf0e5304042 100644 --- a/arch/xtensa/src/esp32/esp32_twai.h +++ b/arch/xtensa/src/esp32/esp32_twai.h @@ -26,7 +26,6 @@ ****************************************************************************/ #include -#include "hardware/esp32_twai.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/xtensa/src/esp32/esp32_wifi_adapter.c b/arch/xtensa/src/esp32/esp32_wifi_adapter.c index 0d2e5066e30c4..79b7a8e35eb88 100644 --- a/arch/xtensa/src/esp32/esp32_wifi_adapter.c +++ b/arch/xtensa/src/esp32/esp32_wifi_adapter.c @@ -57,7 +57,6 @@ #include "xtensa_attr.h" #include "hardware/esp32_dport.h" #include "hardware/esp32_emac.h" -#include "hardware/esp32_soc.h" #include "esp32_irq.h" #include "esp32_wireless.h" #include "esp32_wifi_adapter.h" @@ -69,11 +68,23 @@ # include "esp32_pm.h" #endif -#ifdef CONFIG_ESP32_WIFI_BT_COEXIST -# include "esp_coexist_internal.h" +#ifdef CONFIG_ESP32_BLE +# include "esp32_ble_adapter.h" +# ifdef CONFIG_ESP32_WIFI_BT_COEXIST +# include "esp_coexist_internal.h" +# endif #endif -#include "espidf_wifi.h" +#include "esp_log.h" +#include "esp_mac.h" +#include "esp_private/phy.h" +#include "esp_private/wifi.h" +#include "esp_random.h" +#include "esp_timer.h" +#include "esp_wpa.h" +#include "periph_ctrl.h" +#include "rom/ets_sys.h" +#include "soc/soc_caps.h" /**************************************************************************** * Pre-processor Definitions @@ -90,27 +101,28 @@ #define ESP_WIFI_11N_MCS7_HT20_BITRATE 72 #define ESP_WIFI_11N_MCS7_HT40_BITRATE 150 -#define SSID_MAX_LEN (32) -#define PWD_MAX_LEN (64) - #ifndef CONFIG_EXAMPLE_WIFI_LISTEN_INTERVAL #define CONFIG_EXAMPLE_WIFI_LISTEN_INTERVAL 3 #endif #define DEFAULT_LISTEN_INTERVAL CONFIG_EXAMPLE_WIFI_LISTEN_INTERVAL +#define ets_timer _ETSTIMER_ + /* CONFIG_POWER_SAVE_MODEM */ -#if defined(CONFIG_EXAMPLE_POWER_SAVE_MIN_MODEM) +#if defined(CONFIG_ESP32_POWER_SAVE_MIN_MODEM) # define DEFAULT_PS_MODE WIFI_PS_MIN_MODEM -#elif defined(CONFIG_EXAMPLE_POWER_SAVE_MAX_MODEM) +#elif defined(CONFIG_ESP32_POWER_SAVE_MAX_MODEM) # define DEFAULT_PS_MODE WIFI_PS_MAX_MODEM -#elif defined(CONFIG_EXAMPLE_POWER_SAVE_NONE) +#elif defined(CONFIG_ESP32_POWER_SAVE_NONE) # define DEFAULT_PS_MODE WIFI_PS_NONE #else # define DEFAULT_PS_MODE WIFI_PS_NONE #endif +#define ESP_MAX_PRIORITIES (25) + /**************************************************************************** * Private Types ****************************************************************************/ @@ -126,15 +138,6 @@ enum wifi_sta_state WIFI_STA_STATE_STOP }; -/* Wi-Fi SoftAP state */ - -enum wifi_softap_state -{ - WIFI_SOFTAP_STATE_NULL, - WIFI_SOFTAP_STATE_START, - WIFI_SOFTAP_STATE_STOP -}; - /* Wi-Fi interrupt adapter private data */ struct irq_adpt @@ -160,21 +163,6 @@ struct time_adpt suseconds_t usec; /* Micro second value */ }; -/* Wi-Fi timer private data */ - -struct timer_adpt -{ - struct wdog_s wdog; /* Timer handle */ - struct work_s work; /* Work private data */ - bool repeat; /* Flags indicate if it is cycle */ - uint32_t delay; /* Timeout ticks */ - - /* Timer callback function */ - - void (*func)(void *priv); - void *priv; /* Timer private data */ -}; - /* Wi-Fi event private data */ struct evt_adpt @@ -205,6 +193,12 @@ struct nvs_adpt * Private Function Prototypes ****************************************************************************/ +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST +static int semphr_take_from_isr_wrapper(void *semphr, void *hptw); +static int semphr_give_from_isr_wrapper(void *semphr, void *hptw); +static int is_in_isr_wrapper(void); +#endif /* CONFIG_ESP32_WIFI_BT_COEXIST */ + static bool wifi_env_is_chip(void); static void wifi_set_intr(int32_t cpu_no, uint32_t intr_source, uint32_t intr_num, int32_t intr_prio); @@ -222,13 +216,6 @@ static void *esp_semphr_create(uint32_t max, uint32_t init); static void esp_semphr_delete(void *semphr); static int32_t esp_semphr_take(void *semphr, uint32_t block_time_tick); static int32_t esp_semphr_give(void *semphr); - -#ifdef CONFIG_ESP32_WIFI_BT_COEXIST -static int32_t esp_semphr_take_from_isr(void *semphr, void *hptw); -static int32_t esp_semphr_give_from_isr(void *semphr, void *hptw); -static int wifi_is_in_isr(void); -#endif - static void *esp_thread_semphr_get(void); static void *esp_mutex_create(void); static void *esp_recursive_mutex_create(void); @@ -273,6 +260,7 @@ static void *esp_task_get_current_task(void); static int32_t esp_task_get_max_priority(void); static void *esp_malloc(uint32_t size); static void esp_free(void *ptr); +static uint32_t esp_get_free_heap_size(void); static uint32_t esp_rand(void); static void esp_dport_access_stall_other_cpu_start(void); static void esp_dport_access_stall_other_cpu_end(void); @@ -289,6 +277,7 @@ static void wifi_clock_enable(void); static void wifi_clock_disable(void); static void wifi_rtc_enable_iso(void); static void wifi_rtc_disable_iso(void); +static int64_t esp32_timer_get_time(void); static int32_t esp_nvs_set_i8(uint32_t handle, const char *key, int8_t value); static int32_t esp_nvs_get_i8(uint32_t handle, const char *key, @@ -312,9 +301,11 @@ static int32_t esp_nvs_get_blob(uint32_t handle, const char *key, static int32_t esp_nvs_erase_key(uint32_t handle, const char *key); static int32_t esp_get_random(uint8_t *buf, size_t len); static int32_t esp_get_time(void *t); -static void esp_log_writev(uint32_t level, const char *tag, - const char *format, va_list args) - printf_like(3, 0); +static void esp_log_writev_wrapper(uint32_t level, const char *tag, + const char *format, va_list args); +static void esp_log_write_wrapper(uint32_t level, + const char *tag, + const char *format, ...); static void *esp_malloc_internal(size_t size); static void *esp_realloc_internal(void *ptr, size_t size); static void *esp_calloc_internal(size_t n, size_t size); @@ -325,44 +316,30 @@ static void *esp_wifi_calloc(size_t n, size_t size); static void *esp_wifi_zalloc(size_t size); static void *esp_wifi_create_queue(int32_t queue_len, int32_t item_size); static void esp_wifi_delete_queue(void *queue); -static int wifi_coex_init(void); -static void wifi_coex_deinit(void); -static int wifi_coex_enable(void); -static void wifi_coex_disable(void); -static uint32_t esp_coex_status_get(void); -static void esp_coex_condition_set(uint32_t type, bool dissatisfy); -static int32_t esp_coex_wifi_request(uint32_t event, uint32_t latency, - uint32_t duration); -static int32_t esp_coex_wifi_release(uint32_t event); +static int coex_init_wrapper(void); +static void coex_deinit_wrapper(void); +static int coex_enable_wrapper(void); +static void coex_disable_wrapper(void); +static uint32_t coex_status_get_wrapper(void); +static int32_t coex_wifi_request_wrapper(uint32_t event, uint32_t latency, + uint32_t duration); +static int32_t coex_wifi_release_wrapper(uint32_t event); static unsigned long esp_random_ulong(void); -static int wifi_coex_wifi_set_channel(uint8_t primary, uint8_t secondary); -static int wifi_coex_get_event_duration(uint32_t event, - uint32_t *duration); -static int wifi_coex_get_pti(uint32_t event, uint8_t *pti); -static void wifi_coex_clear_schm_status_bit(uint32_t type, - uint32_t status); -static void wifi_coex_set_schm_status_bit(uint32_t type, - uint32_t status); -static int wifi_coex_set_schm_interval(uint32_t interval); -static uint32_t wifi_coex_get_schm_interval(void); -static uint8_t wifi_coex_get_schm_curr_period(void); -static void *wifi_coex_get_schm_curr_phase(void); -static int wifi_coex_set_schm_curr_phase_idx(int idx); -static int wifi_coex_get_schm_curr_phase_idx(void); - -extern void coex_bt_high_prio(void); - -/**************************************************************************** - * Public Functions declaration - ****************************************************************************/ - -int64_t esp_timer_get_time(void); -void esp_fill_random(void *buf, size_t len); -void esp_log_write(uint32_t level, const char *tag, const char *format, ...) - printf_like(3, 4); -uint32_t esp_log_timestamp(void); -uint8_t esp_crc8(const uint8_t *p, uint32_t len); -void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num); +static int coex_wifi_channel_set_wrapper(uint8_t primary, uint8_t secondary); +static int coex_event_duration_get_wrapper(uint32_t event, + uint32_t *duration); +static int coex_pti_get_wrapper(uint32_t event, uint8_t *pti); +static void coex_schm_status_bit_clear_wrapper(uint32_t type, + uint32_t status); +static void coex_schm_status_bit_set_wrapper(uint32_t type, + uint32_t status); +static int coex_schm_interval_set_wrapper(uint32_t interval); +static uint32_t coex_schm_interval_get_wrapper(void); +static uint8_t coex_schm_curr_period_get_wrapper(void); +static void *coex_schm_curr_phase_get_wrapper(void); +static int coex_register_start_cb_wrapper(int (* cb)(void)); +static int coex_schm_process_restart_wrapper(void); +static int coex_schm_register_cb_wrapper(int type, int(*cb)(int)); /**************************************************************************** * Private Data @@ -375,10 +352,6 @@ static sq_queue_t g_wifi_evt_queue; static struct wifi_notify g_wifi_notify[WIFI_ADPT_EVT_MAX]; static mutex_t g_wifiexcl_lock = NXMUTEX_INITIALIZER; -/* Callback function to update Wi-Fi MAC time */ - -wifi_mac_time_update_cb_t g_wifi_mac_time_update_cb; - /* Wi-Fi adapter reference */ static int g_wifi_ref; @@ -427,6 +400,10 @@ static wifi_config_t g_softap_wifi_cfg; static spinlock_t g_lock; +/**************************************************************************** + * Public Data + ****************************************************************************/ + /* Wi-Fi and BT coexistence OS adapter data */ #ifdef CONFIG_ESP32_WIFI_BT_COEXIST @@ -435,30 +412,26 @@ coex_adapter_funcs_t g_coex_adapter_funcs = ._version = COEX_ADAPTER_VERSION, ._spin_lock_create = esp_spin_lock_create, ._spin_lock_delete = esp_spin_lock_delete, - ._int_enable = esp_wifi_int_restore, ._int_disable = esp_wifi_int_disable, + ._int_enable = esp_wifi_int_restore, ._task_yield_from_isr = esp_task_yield_from_isr, ._semphr_create = esp_semphr_create, ._semphr_delete = esp_semphr_delete, - ._semphr_take_from_isr = esp_semphr_take_from_isr, - ._semphr_give_from_isr = esp_semphr_give_from_isr, + ._semphr_take_from_isr = semphr_take_from_isr_wrapper, + ._semphr_give_from_isr = semphr_give_from_isr_wrapper, ._semphr_take = esp_semphr_take, ._semphr_give = esp_semphr_give, - ._is_in_isr = wifi_is_in_isr, + ._is_in_isr = is_in_isr_wrapper, ._malloc_internal = esp_malloc_internal, ._free = esp_free, + ._esp_timer_get_time = esp32_timer_get_time, ._timer_disarm = esp_timer_disarm, ._timer_done = esp32_timer_done, ._timer_setfn = esp_timer_setfn, ._timer_arm_us = esp_timer_arm_us, - ._esp_timer_get_time = esp_timer_get_time, ._magic = COEX_ADAPTER_MAGIC, }; -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ +#endif /* CONFIG_ESP32_WIFI_BT_COEXIST */ /* Wi-Fi OS adapter data */ @@ -518,10 +491,10 @@ wifi_osi_funcs_t g_wifi_osi_funcs = esp_dport_access_stall_other_cpu_end, ._wifi_apb80m_request = wifi_apb80m_request, ._wifi_apb80m_release = wifi_apb80m_release, - ._phy_disable = esp32_phy_disable, - ._phy_enable = esp32_phy_enable, - ._phy_common_clock_enable = esp32_phy_enable_clock, - ._phy_common_clock_disable = esp32_phy_disable_clock, + ._phy_disable = esp_phy_disable, + ._phy_enable = esp_phy_enable, + ._phy_common_clock_enable = esp_phy_common_clock_enable, + ._phy_common_clock_disable = esp_phy_common_clock_disable, ._phy_update_country_info = esp32_phy_update_country_info, ._read_mac = esp_wifi_read_mac, ._timer_arm = esp_timer_arm, @@ -534,7 +507,7 @@ wifi_osi_funcs_t g_wifi_osi_funcs = ._wifi_clock_disable = wifi_clock_disable, ._wifi_rtc_enable_iso = wifi_rtc_enable_iso, ._wifi_rtc_disable_iso = wifi_rtc_disable_iso, - ._esp_timer_get_time = esp_timer_get_time, + ._esp_timer_get_time = esp32_timer_get_time, ._nvs_set_i8 = esp_nvs_set_i8, ._nvs_get_i8 = esp_nvs_get_i8, ._nvs_set_u8 = esp_nvs_set_u8, @@ -550,8 +523,8 @@ wifi_osi_funcs_t g_wifi_osi_funcs = ._get_random = esp_get_random, ._get_time = esp_get_time, ._random = esp_random_ulong, - ._log_write = esp_log_write, - ._log_writev = esp_log_writev, + ._log_write = esp_log_write_wrapper, + ._log_writev = esp_log_writev_wrapper, ._log_timestamp = esp_log_timestamp, ._malloc_internal = esp_malloc_internal, ._realloc_internal = esp_realloc_internal, @@ -563,25 +536,25 @@ wifi_osi_funcs_t g_wifi_osi_funcs = ._wifi_zalloc = esp_wifi_zalloc, ._wifi_create_queue = esp_wifi_create_queue, ._wifi_delete_queue = esp_wifi_delete_queue, - ._coex_init = wifi_coex_init, - ._coex_deinit = wifi_coex_deinit, - ._coex_enable = wifi_coex_enable, - ._coex_disable = wifi_coex_disable, - ._coex_status_get = esp_coex_status_get, - ._coex_condition_set = esp_coex_condition_set, - ._coex_wifi_request = esp_coex_wifi_request, - ._coex_wifi_release = esp_coex_wifi_release, - ._coex_wifi_channel_set = wifi_coex_wifi_set_channel, - ._coex_event_duration_get = wifi_coex_get_event_duration, - ._coex_pti_get = wifi_coex_get_pti, - ._coex_schm_status_bit_clear = wifi_coex_clear_schm_status_bit, - ._coex_schm_status_bit_set = wifi_coex_set_schm_status_bit, - ._coex_schm_interval_set = wifi_coex_set_schm_interval, - ._coex_schm_interval_get = wifi_coex_get_schm_interval, - ._coex_schm_curr_period_get = wifi_coex_get_schm_curr_period, - ._coex_schm_curr_phase_get = wifi_coex_get_schm_curr_phase, - ._coex_schm_curr_phase_idx_set = wifi_coex_set_schm_curr_phase_idx, - ._coex_schm_curr_phase_idx_get = wifi_coex_get_schm_curr_phase_idx, + ._coex_init = coex_init_wrapper, + ._coex_deinit = coex_deinit_wrapper, + ._coex_enable = coex_enable_wrapper, + ._coex_disable = coex_disable_wrapper, + ._coex_status_get = coex_status_get_wrapper, + ._coex_wifi_request = coex_wifi_request_wrapper, + ._coex_wifi_release = coex_wifi_release_wrapper, + ._coex_wifi_channel_set = coex_wifi_channel_set_wrapper, + ._coex_event_duration_get = coex_event_duration_get_wrapper, + ._coex_pti_get = coex_pti_get_wrapper, + ._coex_schm_status_bit_clear = coex_schm_status_bit_clear_wrapper, + ._coex_schm_status_bit_set = coex_schm_status_bit_set_wrapper, + ._coex_schm_interval_set = coex_schm_interval_set_wrapper, + ._coex_schm_interval_get = coex_schm_interval_get_wrapper, + ._coex_schm_curr_period_get = coex_schm_curr_period_get_wrapper, + ._coex_schm_curr_phase_get = coex_schm_curr_phase_get_wrapper, + ._coex_register_start_cb = coex_register_start_cb_wrapper, + ._coex_schm_process_restart = coex_schm_process_restart_wrapper, + ._coex_schm_register_cb = coex_schm_register_cb_wrapper, ._magic = ESP_WIFI_OS_ADAPTER_MAGIC, }; @@ -624,7 +597,7 @@ static inline int32_t osi_errno_trans(int ret) } /**************************************************************************** - * Name: osi_errno_trans + * Name: wifi_errno_trans * * Description: * Transform from ESP Wi-Fi error code to NuttX error code @@ -694,10 +667,12 @@ static int32_t wifi_errno_trans(int ret) * Wi-Fi interrupt adapter callback function * * Input Parameters: - * arg - interrupt adapter private data + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (not used) + * arg - Argument passed to the interrupt callback * * Returned Value: - * 0 on success + * OK * ****************************************************************************/ @@ -828,7 +803,7 @@ static void esp_set_isr(int32_t n, void *f, void *arg) { wlinfo("irq=%d has been set handler=%p\n", irq, g_irqvector[irq].handler); - return ; + return; } tmp = sizeof(struct irq_adpt); @@ -836,8 +811,8 @@ static void esp_set_isr(int32_t n, void *f, void *arg) if (!adapter) { wlerr("Failed to alloc %d memory\n", tmp); - assert(0); - return ; + PANIC(); + return; } adapter->func = f; @@ -847,8 +822,8 @@ static void esp_set_isr(int32_t n, void *f, void *arg) if (ret) { wlerr("Failed to attach IRQ %d\n", irq); - assert(0); - return ; + PANIC(); + return; } } @@ -933,7 +908,6 @@ static bool IRAM_ATTR wifi_is_from_isr(void) static void *esp_spin_lock_create(void) { -#ifdef CONFIG_SMP spinlock_t *lock; int tmp; @@ -948,11 +922,6 @@ static void *esp_spin_lock_create(void) spin_initialize(lock, SP_UNLOCKED); return lock; -#else - /* If return NULL, code may check fail */ - - return (void *)1; -#endif } /**************************************************************************** @@ -971,11 +940,7 @@ static void *esp_spin_lock_create(void) static void esp_spin_lock_delete(void *lock) { -#ifdef CONFIG_SMP kmm_free(lock); -#else - DEBUGASSERT((int)lock == 1); -#endif } /**************************************************************************** @@ -1029,7 +994,7 @@ static void IRAM_ATTR esp_wifi_int_restore(void *wifi_int_mux, uint32_t tmp) * Name: esp_task_yield_from_isr * * Description: - * Do nothing in NuttX + * Perform a solicited context switch on FreeRTOS. Do nothing in NuttX. * * Input Parameters: * None @@ -1041,7 +1006,6 @@ static void IRAM_ATTR esp_wifi_int_restore(void *wifi_int_mux, uint32_t tmp) static void IRAM_ATTR esp_task_yield_from_isr(void) { - /* Do nothing */ } /**************************************************************************** @@ -1178,70 +1142,6 @@ static int32_t esp_semphr_give(void *semphr) return osi_errno_trans(ret); } -#ifdef CONFIG_ESP32_WIFI_BT_COEXIST - -/**************************************************************************** - * Name: esp_semphr_take_from_isr - * - * Description: - * Try to take semaphore from within an interrupt service routine. - * - * Input Parameters: - * semphr - Semaphore data pointer - * - * Returned Value: - * True if success or false if fail - * - ****************************************************************************/ - -static int32_t IRAM_ATTR esp_semphr_take_from_isr(void *semphr, void *hptw) -{ - *(int *)hptw = 0; - - return osi_errno_trans(nxsem_trywait(semphr)); -} - -/**************************************************************************** - * Name: esp_semphr_give_from_isr - * - * Description: - * Post semaphore from within an interrupt service routine. - * - * Input Parameters: - * semphr - Semaphore data pointer - * - * Returned Value: - * True if success or false if fail - * - ****************************************************************************/ - -static int32_t IRAM_ATTR esp_semphr_give_from_isr(void *semphr, void *hptw) -{ - *(int *)hptw = 0; - - return osi_errno_trans(nxsem_post(semphr)); -} - -/**************************************************************************** - * Name: wifi_is_in_isr - * - * Description: - * Check whether current execution context is of an interrupt service - * routine. - * - * Input Parameters: - * None - * - * Returned Value: - * true if in interrupt or false if not - * - ****************************************************************************/ - -static int IRAM_ATTR wifi_is_in_isr(void) -{ - return up_interrupt_context(); -} -#endif /**************************************************************************** * Name: esp_thread_semphr_get @@ -1637,7 +1537,7 @@ static int32_t esp_queue_send(void *queue, void *item, uint32_t ticks) * Input Parameters: * queue - Message queue data pointer * item - Message data pointer - * hptw - No mean + * hptw - Unused. * * Returned Value: * True if success or false if fail @@ -1646,9 +1546,7 @@ static int32_t esp_queue_send(void *queue, void *item, uint32_t ticks) static int32_t esp_queue_send_from_isr(void *queue, void *item, void *hptw) { - /* Force to set the value to be false */ - - *((int *)hptw) = false; + *(int *)hptw = 0; return esp_queue_send_generic(queue, item, 0, 0); } @@ -1897,9 +1795,15 @@ static int32_t esp_task_create_pinned_to_core(void *entry, int ret; cpu_set_t cpuset; #endif + uint32_t target_prio = prio; + + if (target_prio < ESP_MAX_PRIORITIES) + { + target_prio += esp_task_get_max_priority() - ESP_MAX_PRIORITIES; + } - pid = kthread_create(name, prio, stack_depth, entry, - (char * const *)param); + pid = kthread_create(name, target_prio, stack_depth, entry, + (char * const *)param); if (pid > 0) { if (task_handle != NULL) @@ -2177,6 +2081,7 @@ static int esp_event_id_map(int event_id) id = WIFI_ADPT_EVT_AP_STADISCONNECTED; break; #endif /* ESP32_WLAN_HAS_SOFTAP */ + default: return -1; } @@ -2204,6 +2109,7 @@ static void esp_evt_work_cb(void *arg) irqstate_t flags; struct evt_adpt *evt_adpt; struct wifi_notify *notify; + wifi_ps_type_t ps_type = DEFAULT_PS_MODE; while (1) { @@ -2226,13 +2132,30 @@ static void esp_evt_work_cb(void *arg) #ifdef ESP32_WLAN_HAS_STA case WIFI_ADPT_EVT_STA_START: wlinfo("Wi-Fi sta start\n"); + g_sta_connected = false; - ret = esp_wifi_set_ps(DEFAULT_PS_MODE); + +#ifdef CONFIG_ESP32_BLE + if (esp32_bt_controller_get_status() != + ESP_BT_CONTROLLER_STATUS_IDLE) + { + if (ps_type == WIFI_PS_NONE) + { + ps_type = WIFI_PS_MIN_MODEM; + } + } +#endif + ret = esp_wifi_set_ps(ps_type); + if (ret) { - wlerr("Failed to close PS\n"); + wlerr("Failed to set power save type\n"); break; } + else + { + wlinfo("INFO: Set ps type=%d\n", ps_type); + } ret = esp_wifi_get_config(WIFI_IF_STA, &g_sta_wifi_cfg); if (ret) @@ -2280,6 +2203,29 @@ static void esp_evt_work_cb(void *arg) #ifdef ESP32_WLAN_HAS_SOFTAP case WIFI_ADPT_EVT_AP_START: wlinfo("INFO: Wi-Fi softap start\n"); + +#ifdef CONFIG_ESP32_BLE + if (esp32_bt_controller_get_status() != + ESP_BT_CONTROLLER_STATUS_IDLE) + { + if (ps_type == WIFI_PS_NONE) + { + ps_type = WIFI_PS_MIN_MODEM; + } + } +#endif + ret = esp_wifi_set_ps(ps_type); + + if (ret) + { + wlerr("Failed to set power save type\n"); + break; + } + else + { + wlinfo("INFO: Set ps type=%d\n", ps_type); + } + ret = esp_wifi_get_config(WIFI_IF_AP, &g_softap_wifi_cfg); if (ret) { @@ -2323,6 +2269,73 @@ static void esp_evt_work_cb(void *arg) } } +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + +/**************************************************************************** + * Name: semphr_take_from_isr_wrapper + * + * Description: + * Take a semaphore from an ISR + * + * Input Parameters: + * semphr - Semaphore data pointer. + * hptw - Unused. + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int IRAM_ATTR semphr_take_from_isr_wrapper(void *semphr, void *hptw) +{ + *(int *)hptw = 0; + + return osi_errno_trans(nxsem_trywait(semphr)); +} + +/**************************************************************************** + * Name: semphr_give_from_isr_wrapper + * + * Description: + * Post semaphore + * + * Input Parameters: + * semphr - Semaphore data pointer + * hptw - Unused. + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int IRAM_ATTR semphr_give_from_isr_wrapper(void *semphr, void *hptw) +{ + *(int *)hptw = 0; + + return esp_semphr_give(semphr); +} + +/**************************************************************************** + * Name: is_in_isr_wrapper + * + * Description: + * Check current is in interrupt + * + * Input Parameters: + * None + * + * Returned Value: + * true if in interrupt or false if not + * + ****************************************************************************/ + +static int IRAM_ATTR is_in_isr_wrapper(void) +{ + return up_interrupt_context(); +} + +#endif /* CONFIG_ESP32_WIFI_BT_COEXIST */ + /**************************************************************************** * Name: wifi_env_is_chip * @@ -2362,10 +2375,6 @@ static void wifi_set_intr(int32_t cpu_no, uint32_t intr_source, wlinfo("cpu_no=%" PRId32 ", intr_source=%" PRIu32 ", intr_num=%" PRIu32 ", intr_prio=%" PRId32 "\n", cpu_no, intr_source, intr_num, intr_prio); - - /* Force to bind Wi-Fi interrupt to CPU0 */ - - intr_matrix_set(0, intr_source, intr_num); } /**************************************************************************** @@ -2454,7 +2463,7 @@ int32_t esp_event_post(esp_event_base_t event_base, * ****************************************************************************/ -uint32_t esp_get_free_heap_size(void) +static uint32_t esp_get_free_heap_size(void) { struct mallinfo info; @@ -2580,9 +2589,9 @@ static void esp_timer_arm(void *ptimer, uint32_t ms, bool repeat) static void esp_timer_disarm(void *ptimer) { struct ets_timer *ets_timer = (struct ets_timer *)ptimer; - esp_timer_handle_t esp_timer = (esp_timer_handle_t)ets_timer->priv; + esp_timer_handle_t esp_timer = (esp_timer_handle_t)ets_timer->timer_arg; - if (ets_timer->expire == TIMER_INITIALIZED_VAL) + if (ets_timer->timer_expire == TIMER_INITIALIZED_VAL) { esp_timer_stop(esp_timer); } @@ -2605,13 +2614,13 @@ static void esp_timer_disarm(void *ptimer) static void esp32_timer_done(void *ptimer) { struct ets_timer *ets_timer = (struct ets_timer *)ptimer; - esp_timer_handle_t esp_timer = (esp_timer_handle_t)ets_timer->priv; + esp_timer_handle_t esp_timer = (esp_timer_handle_t)ets_timer->timer_arg; - if (ets_timer->expire == TIMER_INITIALIZED_VAL) + if (ets_timer->timer_expire == TIMER_INITIALIZED_VAL) { - ets_timer->expire = 0; + ets_timer->timer_expire = 0; esp_timer_delete(esp_timer); - ets_timer->priv = NULL; + ets_timer->timer_arg = NULL; } } @@ -2637,12 +2646,12 @@ static void esp_timer_setfn(void *ptimer, void *pfunction, void *parg) esp_timer_handle_t esp_timer; struct ets_timer *ets_timer = (struct ets_timer *)ptimer; - if (ets_timer->expire != TIMER_INITIALIZED_VAL) + if (ets_timer->timer_expire != TIMER_INITIALIZED_VAL) { - ets_timer->priv = NULL; + ets_timer->timer_arg = NULL; } - if (ets_timer->priv == NULL) + if (ets_timer->timer_arg == NULL) { const esp_timer_create_args_t create_args = { @@ -2659,8 +2668,8 @@ static void esp_timer_setfn(void *ptimer, void *pfunction, void *parg) } else { - ets_timer->priv = esp_timer; - ets_timer->expire = TIMER_INITIALIZED_VAL; + ets_timer->timer_arg = esp_timer; + ets_timer->timer_expire = TIMER_INITIALIZED_VAL; } } } @@ -2685,9 +2694,9 @@ static void esp_timer_arm_us(void *ptimer, uint32_t us, bool repeat) { int ret; struct ets_timer *ets_timer = (struct ets_timer *)ptimer; - esp_timer_handle_t esp_timer = (esp_timer_handle_t)ets_timer->priv; + esp_timer_handle_t esp_timer = (esp_timer_handle_t)ets_timer->timer_arg; - if (ets_timer->expire == TIMER_INITIALIZED_VAL) + if (ets_timer->timer_expire == TIMER_INITIALIZED_VAL) { esp_timer_stop(esp_timer); if (!repeat) @@ -2724,8 +2733,7 @@ static void esp_timer_arm_us(void *ptimer, uint32_t us, bool repeat) static void wifi_reset_mac(void) { - modifyreg32(DPORT_WIFI_RST_EN_REG, 0, DPORT_MAC_RST_EN); - modifyreg32(DPORT_WIFI_RST_EN_REG, DPORT_MAC_RST_EN, 0); + periph_module_reset(PERIPH_WIFI_MODULE); } /**************************************************************************** @@ -2744,7 +2752,7 @@ static void wifi_reset_mac(void) static void wifi_clock_enable(void) { - modifyreg32(DPORT_WIFI_CLK_EN_REG, 0, DPORT_WIFI_CLK_WIFI_EN_M); + wifi_module_enable(); } /**************************************************************************** @@ -2763,7 +2771,7 @@ static void wifi_clock_enable(void) static void wifi_clock_disable(void) { - modifyreg32(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN_M, 0); + wifi_module_disable(); } /**************************************************************************** @@ -2791,7 +2799,7 @@ static void wifi_rtc_disable_iso(void) } /**************************************************************************** - * Name: esp_timer_get_time + * Name: esp32_timer_get_time * * Description: * Get system time of type int64_t @@ -2804,7 +2812,7 @@ static void wifi_rtc_disable_iso(void) * ****************************************************************************/ -int64_t esp_timer_get_time(void) +int64_t esp32_timer_get_time(void) { return (int64_t)rt_timer_time_us(); } @@ -3092,38 +3100,6 @@ static int32_t esp_nvs_erase_key(uint32_t handle, const char *key) return -1; } -/**************************************************************************** - * Name: esp_fill_random - * - * Description: - * Fill random data int given buffer of given length - * - * Input Parameters: - * buf - buffer pointer - * len - buffer length - * - * Returned Value: - * - ****************************************************************************/ - -void esp_fill_random(void *buf, size_t len) -{ - uint8_t *p = (uint8_t *)buf; - uint32_t tmp; - uint32_t n; - - while (len > 0) - { - tmp = esp_random(); - n = len < 4 ? len : 4; - - memcpy(p, &tmp, n); - - p += n; - len -= n; - } -} - /**************************************************************************** * Name: esp_get_random * @@ -3200,7 +3176,7 @@ static uint32_t esp_rand(void) } /**************************************************************************** - * Name: esp_log_writev + * Name: esp_log_writev_wrapper * * Description: * Output log with by format string and its arguments @@ -3216,34 +3192,29 @@ static uint32_t esp_rand(void) * ****************************************************************************/ -static void esp_log_writev(uint32_t level, const char *tag, - const char *format, va_list args) +static void esp_log_writev_wrapper(uint32_t level, const char *tag, + const char *format, va_list args) { - switch (level) - { -#ifdef CONFIG_DEBUG_WIRELESS_ERROR - case ESP_LOG_ERROR: - vsyslog(LOG_ERR, format, args); - break; -#endif -#ifdef CONFIG_DEBUG_WIRELESS_WARN - case ESP_LOG_WARN: - vsyslog(LOG_WARNING, format, args); - break; -#endif -#ifdef CONFIG_DEBUG_WIRELESS_INFO - case ESP_LOG_INFO: - vsyslog(LOG_INFO, format, args); - break; - default: - vsyslog(LOG_DEBUG, format, args); - break; + esp_log_level_t max_level; + +#if defined (CONFIG_DEBUG_WIRELESS_INFO) + max_level = ESP_LOG_VERBOSE; +#elif defined (CONFIG_DEBUG_WIRELESS_WARN) + max_level = ESP_LOG_WARN; +#elif defined (CONFIG_DEBUG_WIRELESS_ERROR) + max_level = ESP_LOG_ERROR; +#else + max_level = ESP_LOG_NONE; #endif + + if (level <= max_level) + { + esp_log_writev(level, tag, format, args); } } /**************************************************************************** - * Name: esp_log_write + * Name: esp_log_write_wrapper * * Description: * Output log with by format string and its arguments @@ -3258,33 +3229,29 @@ static void esp_log_writev(uint32_t level, const char *tag, * ****************************************************************************/ -void esp_log_write(uint32_t level, - const char *tag, - const char *format, ...) +static void esp_log_write_wrapper(uint32_t level, + const char *tag, + const char *format, ...) { - va_list list; - va_start(list, format); - esp_log_writev(level, tag, format, list); - va_end(list); -} + esp_log_level_t max_level; -/**************************************************************************** - * Name: esp_log_timestamp - * - * Description: - * Get system time by millim second - * - * Input Parameters: - * None - * - * Returned Value: - * System time - * - ****************************************************************************/ +#if defined (CONFIG_DEBUG_WIRELESS_INFO) + max_level = ESP_LOG_VERBOSE; +#elif defined (CONFIG_DEBUG_WIRELESS_WARN) + max_level = ESP_LOG_WARN; +#elif defined (CONFIG_DEBUG_WIRELESS_ERROR) + max_level = ESP_LOG_ERROR; +#else + max_level = ESP_LOG_NONE; +#endif -uint32_t esp_log_timestamp(void) -{ - return (uint32_t)(esp_timer_get_time() / 1000); + if (level <= max_level) + { + va_list list; + va_start(list, format); + esp_log_writev(level, tag, format, list); + va_end(list); + } } /**************************************************************************** @@ -3583,16 +3550,23 @@ static void esp_wifi_delete_queue(void *queue) } /**************************************************************************** - * Name: wifi_coex_init + * Name: coex_init_wrapper * * Description: - * Don't support + * Init software coexist + * + * Input Parameters: + * none + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. * ****************************************************************************/ -static int wifi_coex_init(void) +static int coex_init_wrapper(void) { -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST return coex_init(); #else return 0; @@ -3600,31 +3574,44 @@ static int wifi_coex_init(void) } /**************************************************************************** - * Name: wifi_coex_deinit + * Name: coex_deinit_wrapper * * Description: - * Don't support + * De-init software coexist + * + * Input Parameters: + * none + * + * Returned Value: + * none * ****************************************************************************/ -static void wifi_coex_deinit(void) +static void coex_deinit_wrapper(void) { -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST coex_deinit(); #endif } /**************************************************************************** - * Name: wifi_coex_enable + * Name: coex_enable_wrapper * * Description: - * Don't support + * Enable software coexist + * + * Input Parameters: + * none + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. * ****************************************************************************/ -static int wifi_coex_enable(void) +static int coex_enable_wrapper(void) { -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST return coex_enable(); #else return 0; @@ -3632,31 +3619,44 @@ static int wifi_coex_enable(void) } /**************************************************************************** - * Name: wifi_coex_disable + * Name: coex_disable_wrapper * * Description: - * Don't support + * Disable software coexist + * + * Input Parameters: + * none + * + * Returned Value: + * none * ****************************************************************************/ -static void wifi_coex_disable(void) +static void coex_disable_wrapper(void) { -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST coex_disable(); #endif } /**************************************************************************** - * Name: esp_coex_status_get + * Name: coex_status_get_wrapper * * Description: - * Don't support + * Get software coexist status. + * + * Input Parameters: + * none + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. * ****************************************************************************/ -static uint32_t esp_coex_status_get(void) +static IRAM_ATTR uint32_t coex_status_get_wrapper(void) { -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST return coex_status_get(); #else return 0; @@ -3664,32 +3664,26 @@ static uint32_t esp_coex_status_get(void) } /**************************************************************************** - * Name: esp_coex_condition_set + * Name: coex_wifi_request_wrapper * * Description: - * Don't support + * Request Wi-Fi coexistence. * - ****************************************************************************/ - -static void esp_coex_condition_set(uint32_t type, bool dissatisfy) -{ -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) - coex_condition_set(type, dissatisfy); -#endif -} - -/**************************************************************************** - * Name: esp_coex_wifi_request + * Input Parameters: + * event - WiFi event + * latency - WiFi will request coexistence after latency + * duration - duration for WiFi to request coexistence * - * Description: - * Don't support + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. * ****************************************************************************/ -static int32_t esp_coex_wifi_request(uint32_t event, uint32_t latency, - uint32_t duration) +static int32_t coex_wifi_request_wrapper(uint32_t event, uint32_t latency, + uint32_t duration) { -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST return coex_wifi_request(event, latency, duration); #else return 0; @@ -3697,33 +3691,48 @@ static int32_t esp_coex_wifi_request(uint32_t event, uint32_t latency, } /**************************************************************************** - * Name: esp_coex_wifi_release + * Name: coex_wifi_release_wrapper * * Description: - * Don't support + * Release Wi-Fi coexistence. + * + * Input Parameters: + * event - WiFi event + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. * ****************************************************************************/ -static int32_t esp_coex_wifi_release(uint32_t event) +static IRAM_ATTR int32_t coex_wifi_release_wrapper(uint32_t event) { -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) - return coex_wifi_release(event); +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + return coex_wifi_release(event); #else - return 0; + return 0; #endif } /**************************************************************************** - * Name: wifi_coex_wifi_set_channel + * Name: coex_wifi_channel_set_wrapper * * Description: - * Don't support + * Set Wi-Fi channel to coexistence module. + * + * Input Parameters: + * primary - WiFi primary channel + * secondary - WiFi secondary channel + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. * ****************************************************************************/ -static int wifi_coex_wifi_set_channel(uint8_t primary, uint8_t secondary) +static int coex_wifi_channel_set_wrapper(uint8_t primary, uint8_t secondary) { -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST return coex_wifi_channel_set(primary, secondary); #else return 0; @@ -3731,16 +3740,25 @@ static int wifi_coex_wifi_set_channel(uint8_t primary, uint8_t secondary) } /**************************************************************************** - * Name: wifi_coex_get_event_duration + * Name: coex_event_duration_get_wrapper * * Description: - * Don't support + * Get coexistence event duration. + * + * Input Parameters: + * event - Coexistence event + * duration - Coexistence event duration + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. * ****************************************************************************/ -static int wifi_coex_get_event_duration(uint32_t event, uint32_t *duration) +static int coex_event_duration_get_wrapper(uint32_t event, + uint32_t *duration) { -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST return coex_event_duration_get(event, duration); #else return 0; @@ -3748,59 +3766,89 @@ static int wifi_coex_get_event_duration(uint32_t event, uint32_t *duration) } /**************************************************************************** - * Name: wifi_coex_get_pti + * Name: coex_pti_get_wrapper * * Description: - * Don't support + * Get coexistence event priority. + * + * Input Parameters: + * event - Coexistence event + * pti - Coexistence event priority + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. * ****************************************************************************/ -static int wifi_coex_get_pti(uint32_t event, uint8_t *pti) +static int coex_pti_get_wrapper(uint32_t event, uint8_t *pti) { return 0; } /**************************************************************************** - * Name: wifi_coex_clear_schm_status_bit + * Name: coex_schm_status_bit_clear_wrapper * * Description: - * Don't support + * Clear coexistence status. + * + * Input Parameters: + * type - Coexistence status type + * status - Coexistence status + * + * Returned Value: + * none * ****************************************************************************/ -static void wifi_coex_clear_schm_status_bit(uint32_t type, uint32_t status) +static void coex_schm_status_bit_clear_wrapper(uint32_t type, + uint32_t status) { -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST coex_schm_status_bit_clear(type, status); #endif } /**************************************************************************** - * Name: wifi_coex_set_schm_status_bit + * Name: coex_schm_status_bit_set_wrapper * * Description: - * Don't support + * Set coexistence status. + * + * Input Parameters: + * type - Coexistence status type + * status - Coexistence status + * + * Returned Value: + * none * ****************************************************************************/ -static void wifi_coex_set_schm_status_bit(uint32_t type, uint32_t status) +static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status) { -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST coex_schm_status_bit_set(type, status); #endif } /**************************************************************************** - * Name: wifi_coex_set_schm_interval + * Name: coex_schm_interval_set_wrapper * * Description: - * Don't support + * Set coexistence scheme interval. + * + * Input Parameters: + * interval - Coexistence scheme interval + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. * ****************************************************************************/ -static int wifi_coex_set_schm_interval(uint32_t interval) +static IRAM_ATTR int coex_schm_interval_set_wrapper(uint32_t interval) { -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST return coex_schm_interval_set(interval); #else return 0; @@ -3808,16 +3856,22 @@ static int wifi_coex_set_schm_interval(uint32_t interval) } /**************************************************************************** - * Name: wifi_coex_get_schm_interval + * Name: coex_schm_interval_get_wrapper * * Description: - * Don't support + * Get coexistence scheme interval. + * + * Input Parameters: + * none + * + * Returned Value: + * Coexistence scheme interval * ****************************************************************************/ -static uint32_t wifi_coex_get_schm_interval(void) +static uint32_t coex_schm_interval_get_wrapper(void) { -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST return coex_schm_interval_get(); #else return 0; @@ -3825,16 +3879,22 @@ static uint32_t wifi_coex_get_schm_interval(void) } /**************************************************************************** - * Name: wifi_coex_get_schm_curr_period + * Name: coex_schm_curr_period_get_wrapper * * Description: - * Don't support + * Get current coexistence scheme period. + * + * Input Parameters: + * none + * + * Returned Value: + * Coexistence scheme period * ****************************************************************************/ -static uint8_t wifi_coex_get_schm_curr_period(void) +static uint8_t coex_schm_curr_period_get_wrapper(void) { -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST return coex_schm_curr_period_get(); #else return 0; @@ -3842,16 +3902,22 @@ static uint8_t wifi_coex_get_schm_curr_period(void) } /**************************************************************************** - * Name: wifi_coex_get_schm_curr_phase + * Name: coex_schm_curr_phase_get_wrapper * * Description: - * Don't support + * Get current coexistence scheme phase. + * + * Input Parameters: + * none + * + * Returned Value: + * Coexistence scheme phase * ****************************************************************************/ -static void *wifi_coex_get_schm_curr_phase(void) +static void *coex_schm_curr_phase_get_wrapper(void) { -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST return coex_schm_curr_phase_get(); #else return NULL; @@ -3859,34 +3925,73 @@ static void *wifi_coex_get_schm_curr_phase(void) } /**************************************************************************** - * Name: wifi_coex_set_schm_curr_phase_idx + * Name: coex_register_start_cb_wrapper * * Description: - * Don't support + * Register Wi-Fi callback for coexistence starts. + * + * Input Parameters: + * cb - WiFi callback + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. * ****************************************************************************/ -static int wifi_coex_set_schm_curr_phase_idx(int idx) +static int coex_register_start_cb_wrapper(int (* cb)(void)) { -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) - return coex_schm_curr_phase_idx_set(idx); +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + return coex_register_start_cb(cb); #else return 0; #endif } /**************************************************************************** - * Name: wifi_coex_get_schm_curr_phase_idx + * Name: coex_schm_process_restart_wrapper * * Description: - * Don't support + * Restart current coexistence scheme. + * + * Input Parameters: + * none + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. + * + ****************************************************************************/ + +static int coex_schm_process_restart_wrapper(void) +{ +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + return coex_schm_process_restart(); +#else + return 0; +#endif +} + +/**************************************************************************** + * Name: coex_schm_register_cb_wrapper + * + * Description: + * Register callback for coexistence scheme. + * + * Input Parameters: + * type - callback type + * cb - callback + * + * Returned Value: + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. * ****************************************************************************/ -static int wifi_coex_get_schm_curr_phase_idx(void) +static int coex_schm_register_cb_wrapper(int type, int(*cb)(int)) { -#if defined(CONFIG_ESP32_WIFI_BT_COEXIST) - return coex_schm_curr_phase_idx_get(); +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + return coex_schm_register_callback(type, cb); #else return 0; #endif @@ -3896,8 +4001,13 @@ static int wifi_coex_get_schm_curr_phase_idx(void) * Name: esp_random_ulong * * Description: - * A simpler wrapper of esp_random. - * Just convert the return value from uint32_t to unsigned long. + * Get random value and convert to unsigned long. + * + * Input Parameters: + * None + * + * Returned Value: + * Random value * ****************************************************************************/ @@ -3912,6 +4022,16 @@ static unsigned long esp_random_ulong(void) * Description: * Wi-Fi TX done callback function. * + * Input Parameters: + * ifidx - The interface id that the tx callback has been triggered from + * data - Pointer to the data transmitted + * data_len - Length of the data transmitted + * txstatus - True:if the data was transmitted sucessfully False: if data + * transmission failed + * + * Returned Value: + * none + * ****************************************************************************/ static IRAM_ATTR void esp_wifi_tx_done_cb(uint8_t ifidx, uint8_t *data, @@ -3944,6 +4064,7 @@ static IRAM_ATTR void esp_wifi_tx_done_cb(uint8_t ifidx, uint8_t *data, } #ifdef ESP32_WLAN_HAS_STA + /**************************************************************************** * Name: esp_wifi_auth_trans * @@ -4043,6 +4164,7 @@ static int esp_wifi_cipher_trans(uint32_t wifi_cipher) return cipher_mode; } + #endif /* ESP32_WLAN_HAS_STA */ /**************************************************************************** @@ -4108,11 +4230,11 @@ static int esp_freq_to_channel(uint16_t freq) } /**************************************************************************** - * Functions needed by libnet80211.a + * Functions needed by libpp.a ****************************************************************************/ /**************************************************************************** - * Name: net80211_printf + * Name: pp_printf * * Description: * Output format string and its arguments @@ -4121,11 +4243,11 @@ static int esp_freq_to_channel(uint16_t freq) * format - format string * * Returned Value: - * 0 + * Zero (OK) * ****************************************************************************/ -int net80211_printf(const char *format, ...) +int pp_printf(const char *format, ...) { #ifdef CONFIG_DEBUG_WIRELESS_INFO va_list arg; @@ -4139,168 +4261,63 @@ int net80211_printf(const char *format, ...) } /**************************************************************************** - * Functions needed by libmesh.a - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_mesh_send_event_internal - * - * Description: - * Don't support - * - ****************************************************************************/ - -int esp_mesh_send_event_internal(int32_t event_id, - void *event_data, - size_t event_data_size) -{ - return -1; -} - -/**************************************************************************** - * Name: esp_mesh_get_topology - * - * Description: - * Don't support - * - ****************************************************************************/ - -void *esp_mesh_get_topology(void) -{ - return NULL; -} - -/**************************************************************************** - * Functions needed by libwpa_supplicant.a - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_timer_create - * - * Description: - * Create timer with given arguments - * - * Input Parameters: - * create_args - Timer arguments data pointer - * out_handle - Timer handle pointer - * - * Returned Value: - * 0 if success or -1 if fail - * - ****************************************************************************/ - -int32_t esp_timer_create(const esp_timer_create_args_t *create_args, - esp_timer_handle_t *out_handle) -{ - int ret; - struct rt_timer_args_s rt_timer_args; - struct rt_timer_s *rt_timer; - - rt_timer_args.arg = create_args->arg; - rt_timer_args.callback = create_args->callback; - - ret = rt_timer_create(&rt_timer_args, &rt_timer); - if (ret) - { - wlerr("Failed to create rt_timer error=%d\n", ret); - return ret; - } - - *out_handle = (esp_timer_handle_t)rt_timer; - - return 0; -} - -/**************************************************************************** - * Name: esp_timer_start_once - * - * Description: - * Start timer with one shot mode - * - * Input Parameters: - * timer - Timer handle pointer - * timeout_us - Timeout value by micro second - * - * Returned Value: - * 0 if success or -1 if fail - * + * Functions needed by libnet80211.a ****************************************************************************/ -int32_t esp_timer_start_once(esp_timer_handle_t timer, uint64_t timeout_us) -{ - struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer; - - rt_timer_start(rt_timer, timeout_us, false); - - return 0; -} - /**************************************************************************** - * Name: esp_timer_start_periodic + * Name: net80211_printf * * Description: - * Start timer with periodic mode + * Output format string and its arguments * * Input Parameters: - * timer - Timer handle pointer - * period - Timeout value by micro second + * format - format string * * Returned Value: - * 0 if success or -1 if fail + * Zero (OK) * ****************************************************************************/ -int32_t esp_timer_start_periodic(esp_timer_handle_t timer, uint64_t period) +int net80211_printf(const char *format, ...) { - struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer; +#ifdef CONFIG_DEBUG_WIRELESS_INFO + va_list arg; - rt_timer_start(rt_timer, period, true); + va_start(arg, format); + vsyslog(LOG_INFO, format, arg); + va_end(arg); +#endif return 0; } /**************************************************************************** - * Name: esp_timer_stop - * - * Description: - * Stop timer - * - * Input Parameters: - * timer - Timer handle pointer - * - * Returned Value: - * 0 if success or -1 if fail - * + * Functions needed by libcoexist.a ****************************************************************************/ -int32_t esp_timer_stop(esp_timer_handle_t timer) -{ - struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer; - - rt_timer_stop(rt_timer); - - return 0; -} - /**************************************************************************** - * Name: esp_timer_delete + * Name: coexist_printf * * Description: - * Delete timer and free resource + * Output format string and its arguments * * Input Parameters: - * timer - Timer handle pointer + * format - format string * * Returned Value: - * 0 if success or -1 if fail + * Zero (OK) * ****************************************************************************/ -int32_t esp_timer_delete(esp_timer_handle_t timer) +int coexist_printf(const char *format, ...) { - struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer; +#ifdef CONFIG_DEBUG_WIRELESS_INFO + va_list arg; - rt_timer_delete(rt_timer); + va_start(arg, format); + vsyslog(LOG_INFO, format, arg); + va_end(arg); +#endif return 0; } @@ -4309,32 +4326,6 @@ int32_t esp_timer_delete(esp_timer_handle_t timer) * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: esp32_wifi_bt_coexist_init - * - * Description: - * Initialize ESP32 Wi-Fi and BT coexistence module. - * - * Input Parameters: - * None - * - * Returned Value: - * OK on success (positive non-zero values are cmd-specific) - * Negated errno returned on failure. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32_WIFI_BT_COEXIST -int esp32_wifi_bt_coexist_init(void) -{ - coex_dbg_set_log_level(COEX_LOG_INFO); - esp_coex_adapter_register(&g_coex_adapter_funcs); - coex_pre_init(); - - return 0; -} -#endif - /**************************************************************************** * Name: esp_event_send_internal * @@ -4367,77 +4358,6 @@ int32_t esp_event_send_internal(esp_event_base_t event_base, return ret; } -/**************************************************************************** - * Name: esp_wifi_init - * - * Description: - * Initialize Wi-Fi - * - * Input Parameters: - * config - Initialization config parameters - * - * Returned Value: - * 0 if success or others if fail - * - ****************************************************************************/ - -int32_t esp_wifi_init(const wifi_init_config_t *config) -{ - int32_t ret; - - ret = esp_wifi_init_internal(config); - if (ret) - { - wlerr("Failed to initialize Wi-Fi error=%d\n", ret); - return ret; - } - - ret = esp_supplicant_init(); - if (ret) - { - wlerr("Failed to initialize WPA supplicant error=%d\n", ret); - esp_wifi_deinit_internal(); - return ret; - } - - return 0; -} - -/**************************************************************************** - * Name: esp_wifi_deinit - * - * Description: - * Deinitialize Wi-Fi and free resource - * - * Input Parameters: - * None - * - * Returned Value: - * 0 if success or others if fail - * - ****************************************************************************/ - -int32_t esp_wifi_deinit(void) -{ - int ret; - - ret = esp_supplicant_deinit(); - if (ret) - { - wlerr("Failed to deinitialize supplicant\n"); - return ret; - } - - ret = esp_wifi_deinit_internal(); - if (ret != 0) - { - wlerr("Failed to deinitialize Wi-Fi\n"); - return ret; - } - - return ret; -} - /**************************************************************************** * Name: esp_wifi_free_eb * @@ -5043,6 +4963,8 @@ int esp_wifi_sta_essid(struct iwreq *iwr, bool set) { memset(wifi_cfg.sta.ssid, 0x0, SSID_MAX_LEN); memcpy(wifi_cfg.sta.ssid, pdata, len); + memset(wifi_cfg.sta.sae_h2e_identifier, 0x0, SAE_H2E_IDENTIFIER_LEN); + wifi_cfg.sta.sae_pwe_h2e = WPA3_SAE_PWE_BOTH; if (g_sta_connected) { @@ -5632,7 +5554,8 @@ int esp_wifi_sta_bitrate(struct iwreq *iwr, bool set) return OK; } -#endif //ESP32_WLAN_HAS_STA + +#endif /* ESP32_WLAN_HAS_STA */ /**************************************************************************** * Name: esp_wifi_sta_get_txpower @@ -5714,7 +5637,7 @@ int esp_wifi_sta_txpower(struct iwreq *iwr, bool set) } /**************************************************************************** - * Name: esp_wifi_sta_get_channel_range + * Name: esp_wifi_sta_channel * * Description: * Get station range of channel parameters. @@ -5828,6 +5751,7 @@ int esp_wifi_sta_country(struct iwreq *iwr, bool set) } #ifdef ESP32_WLAN_HAS_STA + /**************************************************************************** * Name: esp_wifi_sta_rssi * @@ -6021,7 +5945,7 @@ int esp_wifi_softap_stop(void) * ****************************************************************************/ -int esp_wifi_softap_send_data(void *pbuf, uint32_t len) +int esp_wifi_softap_send_data(void *pbuf, size_t len) { int ret; @@ -6125,7 +6049,7 @@ int esp_wifi_softap_password(struct iwreq *iwr, bool set) DEBUGASSERT(ext != NULL); pdata = ext->key; - len = ext->key_len; + len = ext->key_len; if (set && len > PWD_MAX_LEN) { @@ -6142,6 +6066,7 @@ int esp_wifi_softap_password(struct iwreq *iwr, bool set) /* Clear the password field and copy the user password to it */ memset(wifi_cfg.ap.password, 0x0, PWD_MAX_LEN); + if (ext->alg != IW_ENCODE_ALG_NONE) { memcpy(wifi_cfg.sta.password, pdata, len); @@ -6227,7 +6152,6 @@ int esp_wifi_softap_essid(struct iwreq *iwr, bool set) memset(wifi_cfg.ap.ssid, 0x0, SSID_MAX_LEN); memcpy(wifi_cfg.ap.ssid, pdata, len); wifi_cfg.ap.ssid_len = len; - if (g_softap_started) { ret = esp_wifi_set_config(WIFI_IF_AP, &wifi_cfg); @@ -6403,6 +6327,13 @@ int esp_wifi_softap_auth(struct iwreq *iwr, bool set) wifi_cfg.ap.authmode = WIFI_AUTH_WPA2_PSK; break; + case IW_AUTH_WPA_VERSION_WPA3: + wifi_cfg.ap.pmf_cfg.required = true; + wifi_cfg.ap.pmf_cfg.capable = false; + wifi_cfg.ap.sae_pwe_h2e = WPA3_SAE_PWE_BOTH; + wifi_cfg.ap.authmode = WIFI_AUTH_WPA3_PSK; + break; + default: wlerr("Invalid wpa version %" PRId32 "\n", iwr->u.param.value); @@ -6631,7 +6562,32 @@ int esp_wifi_softap_rssi(struct iwreq *iwr, bool set) return -ENOSYS; } -#endif +#endif /* ESP32_WLAN_HAS_SOFTAP */ + +/**************************************************************************** + * Name: esp32_wifi_bt_coexist_init + * + * Description: + * Initialize ESP32 Wi-Fi and BT coexistance module. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success (positive non-zero values are cmd-specific) + * Negated errno returned on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST +int esp32_wifi_bt_coexist_init(void) +{ + esp_coex_adapter_register(&g_coex_adapter_funcs); + coex_pre_init(); + + return 0; +} +#endif /* CONFIG_ESP32_WIFI_BT_COEXIST */ /**************************************************************************** * Name: esp_wifi_stop_callback diff --git a/arch/xtensa/src/esp32/esp32_wifi_adapter.h b/arch/xtensa/src/esp32/esp32_wifi_adapter.h index 5c0b251196c09..309cf3ae288d9 100644 --- a/arch/xtensa/src/esp32/esp32_wifi_adapter.h +++ b/arch/xtensa/src/esp32/esp32_wifi_adapter.h @@ -61,7 +61,8 @@ extern "C" # define ESP32_WLAN_DEVS 2 #endif -/* Needed to fix coex_adapter_funcs_t definition */ +#define SSID_MAX_LEN (32) +#define PWD_MAX_LEN (64) #define CONFIG_IDF_TARGET_ESP32 1 diff --git a/arch/xtensa/src/esp32/esp32_wifi_utils.c b/arch/xtensa/src/esp32/esp32_wifi_utils.c index 7f10e1c6fe4d3..d6ae1317e1898 100644 --- a/arch/xtensa/src/esp32/esp32_wifi_utils.c +++ b/arch/xtensa/src/esp32/esp32_wifi_utils.c @@ -35,7 +35,15 @@ #include "esp32_wifi_adapter.h" #include "esp32_wifi_utils.h" #include "esp32_wireless.h" -#include "espidf_wifi.h" + +#include "esp_log.h" +#include "esp_mac.h" +#include "esp_private/phy.h" +#include "esp_private/wifi.h" +#include "esp_random.h" +#include "esp_timer.h" +#include "rom/ets_sys.h" +#include "soc/soc_caps.h" /**************************************************************************** * Pre-processor Definitions @@ -53,7 +61,6 @@ #endif #define SCAN_TIME_SEC (5) -#define SSID_LEN (33) /* Maximum number of channels for Wi-Fi 2.4Ghz */ @@ -88,7 +95,7 @@ static struct wifi_scan_result g_scan_priv = { .scan_signal = SEM_INITIALIZER(0), }; -static uint8_t g_channel_num = 0; +static uint8_t g_channel_num; static uint8_t g_channel_list[CHANNEL_MAX_NUM]; /**************************************************************************** @@ -114,13 +121,13 @@ int esp_wifi_start_scan(struct iwreq *iwr) { struct wifi_scan_result *priv = &g_scan_priv; wifi_scan_config_t *config = NULL; - uint8_t target_ssid[SSID_LEN]; struct iw_scan_req *req; int ret = 0; int i; uint8_t target_mac[MAC_LEN]; + uint8_t target_ssid[SSID_MAX_LEN + 1]; + memset(target_ssid, 0x0, sizeof(SSID_MAX_LEN + 1)); - memset(target_ssid, 0x0, sizeof(SSID_LEN)); if (iwr == NULL) { wlerr("ERROR: Invalid ioctl cmd.\n"); @@ -132,7 +139,7 @@ int esp_wifi_start_scan(struct iwreq *iwr) return OK; } - config = kmm_malloc(sizeof(wifi_scan_config_t)); + config = kmm_calloc(1, sizeof(wifi_scan_config_t)); if (config == NULL) { wlerr("ERROR: Cannot allocate result buffer\n"); @@ -141,7 +148,7 @@ int esp_wifi_start_scan(struct iwreq *iwr) g_channel_num = 0; memset(g_channel_list, 0x0, CHANNEL_MAX_NUM); - memset(config, 0x0, sizeof(wifi_scan_config_t)); + if (iwr->u.data.pointer && iwr->u.data.length >= sizeof(struct iw_scan_req)) { @@ -153,6 +160,8 @@ int esp_wifi_start_scan(struct iwreq *iwr) { /* Scan specific ESSID */ + config->show_hidden = true; + config->bssid = NULL; memcpy(&target_ssid[0], req->essid, req->essid_len); config->ssid = &target_ssid[0]; config->ssid[req->essid_len] = '\0'; @@ -196,12 +205,11 @@ int esp_wifi_start_scan(struct iwreq *iwr) } esp_wifi_start(); - - esp_wifi_scan_stop(); ret = esp_wifi_scan_start(config, false); if (ret != OK) { wlerr("ERROR: Scan error, ret: %d\n", ret); + ret = ERROR; } else { @@ -226,10 +234,13 @@ int esp_wifi_start_scan(struct iwreq *iwr) { kmm_free(config); config = NULL; - wlinfo("INFO: start scan\n"); } - g_scan_priv.scan_status = ESP_SCAN_RUN; + if (ret == OK) + { + wlinfo("INFO: start scan\n"); + g_scan_priv.scan_status = ESP_SCAN_RUN; + } return ret; } @@ -257,18 +268,26 @@ int esp_wifi_get_scan_results(struct iwreq *iwr) if (g_scan_priv.scan_status == ESP_SCAN_RUN) { - if (scan_block == false) + irqstate_t irqstate = enter_critical_section(); + if (!scan_block) { scan_block = true; + leave_critical_section(irqstate); nxsem_tickwait(&priv->scan_signal, SEC2TICK(SCAN_TIME_SEC)); scan_block = false; } else { + leave_critical_section(irqstate); ret = -EINVAL; goto exit_failed; } } + else if (g_scan_priv.scan_status == ESP_SCAN_DISABLED) + { + ret = -EINVAL; + goto exit_failed; + } if ((iwr == NULL) || (g_scan_priv.scan_status != ESP_SCAN_DONE)) { @@ -276,7 +295,7 @@ int esp_wifi_get_scan_results(struct iwreq *iwr) goto exit_failed; } - if (!priv->scan_result) + if (priv->scan_result == NULL) { /* Result have already been requested */ @@ -285,6 +304,13 @@ int esp_wifi_get_scan_results(struct iwreq *iwr) goto exit_failed; } + if (priv->scan_result_size <= 0) + { + ret = OK; + iwr->u.data.length = 0; + goto exit_free_buffer; + } + if (iwr->u.data.pointer == NULL || iwr->u.data.length < priv->scan_result_size) { @@ -293,14 +319,7 @@ int esp_wifi_get_scan_results(struct iwreq *iwr) ret = -E2BIG; iwr->u.data.pointer = NULL; iwr->u.data.length = priv->scan_result_size; - goto exit_failed; - } - - if (priv->scan_result_size <= 0) - { - ret = OK; - iwr->u.data.length = 0; - goto exit_free_buffer; + return ret; } /* Copy result to user buffer */ @@ -352,19 +371,26 @@ void esp_wifi_scan_event_parse(void) uint8_t bss_count = 0; bool parse_done = false; + if (priv->scan_status != ESP_SCAN_RUN) + { + return; + } + esp_wifi_scan_get_ap_num(&bss_total); if (bss_total == 0) { priv->scan_status = ESP_SCAN_DONE; wlinfo("INFO: None AP is scanned\n"); + nxsem_post(&priv->scan_signal); return; } - ap_list_buffer = kmm_zalloc(bss_total * sizeof(wifi_ap_record_t)); + ap_list_buffer = kmm_calloc(bss_total, sizeof(wifi_ap_record_t)); if (ap_list_buffer == NULL) { priv->scan_status = ESP_SCAN_DONE; - wlerr("ERROR: Failed to malloc buffer to print scan results"); + wlerr("ERROR: Failed to calloc buffer to print scan results"); + nxsem_post(&priv->scan_signal); return; } @@ -377,6 +403,7 @@ void esp_wifi_scan_event_parse(void) size_t essid_len_aligned; bool is_target_channel = true; int i; + for (bss_count = 0; bss_count < bss_total; bss_count++) { if (g_channel_num > 1) @@ -396,7 +423,7 @@ void esp_wifi_scan_event_parse(void) is_target_channel = true; } - if (is_target_channel == true) + if (is_target_channel) { result_size = WIFI_SCAN_RESULT_SIZE - priv->scan_result_size; @@ -421,16 +448,16 @@ void esp_wifi_scan_event_parse(void) /* Copy ESSID */ essid_len = MIN(strlen((const char *) - ap_list_buffer[bss_count].ssid), 32); + ap_list_buffer[bss_count].ssid), SSID_MAX_LEN); essid_len_aligned = (essid_len + 3) & -4; - if (result_size < ESP_IW_EVENT_SIZE(essid)+essid_len_aligned) + if (result_size < ESP_IW_EVENT_SIZE(essid) + essid_len_aligned) { goto scan_result_full; } iwe = (struct iw_event *) &priv->scan_result[priv->scan_result_size]; - iwe->len = ESP_IW_EVENT_SIZE(essid)+essid_len_aligned; + iwe->len = ESP_IW_EVENT_SIZE(essid) + essid_len_aligned; iwe->cmd = SIOCGIWESSID; iwe->u.essid.flags = 0; iwe->u.essid.length = essid_len; @@ -442,10 +469,12 @@ void esp_wifi_scan_event_parse(void) iwe->u.essid.pointer = (void *)sizeof(iwe->u.essid); memcpy(&iwe->u.essid + 1, ap_list_buffer[bss_count].ssid, essid_len); + wlinfo("INFO: ssid %s\n", ap_list_buffer[bss_count].ssid); + priv->scan_result_size += - ESP_IW_EVENT_SIZE(essid)+essid_len_aligned; - result_size -= ESP_IW_EVENT_SIZE(essid)+essid_len_aligned; + ESP_IW_EVENT_SIZE(essid) + essid_len_aligned; + result_size -= ESP_IW_EVENT_SIZE(essid) + essid_len_aligned; /* Copy link quality info */ @@ -459,7 +488,9 @@ void esp_wifi_scan_event_parse(void) iwe->len = ESP_IW_EVENT_SIZE(qual); iwe->cmd = IWEVQUAL; iwe->u.qual.qual = 0x00; + wlinfo("INFO: signal %d\n", ap_list_buffer[bss_count].rssi); + iwe->u.qual.level = ap_list_buffer[bss_count].rssi; iwe->u.qual.noise = 0x00; iwe->u.qual.updated = IW_QUAL_DBM | IW_QUAL_ALL_UPDATED; @@ -526,7 +557,7 @@ void esp_wifi_scan_event_parse(void) /* Continue instead of break to log dropped AP results */ - if (parse_done == false) + if (!parse_done) { wlerr("ERROR: No more space in scan_result buffer\n"); } diff --git a/arch/xtensa/src/esp32/esp32_wireless.c b/arch/xtensa/src/esp32/esp32_wireless.c index 109e61aa9a575..ad9cc4201b708 100644 --- a/arch/xtensa/src/esp32/esp32_wireless.c +++ b/arch/xtensa/src/esp32/esp32_wireless.c @@ -26,10 +26,10 @@ #include #include -#include -#include #include #include +#include +#include #include "xtensa.h" #include "hardware/esp32_dport.h" @@ -38,6 +38,13 @@ #include "esp32_irq.h" #include "esp32_partition.h" +#include "esp_private/phy.h" +#ifdef CONFIG_ESP32_WIFI +# include "esp_private/wifi.h" +# include "esp_wpa.h" +#endif +#include "esp_coexist_internal.h" +#include "periph_ctrl.h" #include "esp_phy_init.h" #include "phy_init_data.h" @@ -47,12 +54,6 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES_FOUR -# define MAC_ADDR_UNIVERSE_BT_OFFSET 2 -#else -# define MAC_ADDR_UNIVERSE_BT_OFFSET 1 -#endif - /* Software Interrupt */ #define SWI_IRQ ESP32_IRQ_CPU_CPU2 @@ -81,13 +82,16 @@ struct esp_wireless_priv_s static inline void phy_digital_regs_store(void); static inline void phy_digital_regs_load(void); +static int esp_swi_irq(int irq, void *context, void *arg); +#ifdef CONFIG_ESP32_WIFI +static void esp_wifi_set_log_level(void); +#endif /**************************************************************************** * Extern Functions declaration ****************************************************************************/ extern uint8_t esp_crc8(const uint8_t *p, uint32_t len); -extern void coex_bt_high_prio(void); extern void phy_wakeup_init(void); extern void phy_close_rf(void); extern uint8_t phy_dig_reg_backup(bool init, uint32_t *regs); @@ -116,6 +120,10 @@ static uint32_t *g_phy_digital_regs_mem = NULL; static bool g_is_phy_calibrated = false; +/* Private data of the wireless common interface */ + +static struct esp_wireless_priv_s g_esp_wireless_priv; + #ifdef CONFIG_ESP32_PHY_INIT_DATA_IN_PARTITION static const char *phy_partion_label = "phy_init"; #endif @@ -144,6 +152,7 @@ static const char *g_phy_type[ESP_PHY_INIT_DATA_TYPE_NUMBER] = static phy_country_to_bin_type_t g_country_code_map_type_table[] = { + {"01", ESP_PHY_INIT_DATA_TYPE_DEFAULT}, {"AT", ESP_PHY_INIT_DATA_TYPE_CE}, {"AU", ESP_PHY_INIT_DATA_TYPE_ACMA}, {"BE", ESP_PHY_INIT_DATA_TYPE_CE}, @@ -192,9 +201,13 @@ static phy_country_to_bin_type_t g_country_code_map_type_table[] = #endif -/* Private data of the wireless common interface */ +/**************************************************************************** + * Public Data + ****************************************************************************/ -static struct esp_wireless_priv_s g_esp_wireless_priv; +/* Callback function to update WiFi MAC time */ + +wifi_mac_time_update_cb_t g_wifi_mac_time_update_cb = NULL; /**************************************************************************** * Private Functions @@ -299,73 +312,66 @@ static int esp_swi_irq(int irq, void *context, void *arg) return OK; } -/**************************************************************************** - * Public Functions - ****************************************************************************/ +#ifdef CONFIG_ESP32_WIFI /**************************************************************************** - * Functions needed by libphy.a - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_dport_access_reg_read + * Name: esp_wifi_set_log_level * * Description: - * Read register value safely in SMP + * Sets the log level for the ESP32 WiFi module based on preprocessor + * definitions. The log level can be verbose, warning, or error. * * Input Parameters: - * reg - Register address + * None * * Returned Value: - * Register value + * None * ****************************************************************************/ -uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg) +static void esp_wifi_set_log_level(void) { - return getreg32(reg); + wifi_log_level_t wifi_log_level = WIFI_LOG_NONE; + + /* set WiFi log level */ + +#if defined(CONFIG_DEBUG_WIRELESS_INFO) + wifi_log_level = WIFI_LOG_VERBOSE; +#elif defined(CONFIG_DEBUG_WIRELESS_WARN) + wifi_log_level = WIFI_LOG_WARNING; +#elif defined(CONFIG_LOG_MAXIMUM_LEVEL) + wifi_log_level = WIFI_LOG_ERROR; +#endif + + esp_wifi_internal_set_log_level(wifi_log_level); } +#endif /* CONFIG_ESP32_WIFI */ /**************************************************************************** - * Name: phy_enter_critical - * - * Description: - * Enter critical state - * - * Input Parameters: - * None - * - * Returned Value: - * CPU PS value - * + * Public Functions ****************************************************************************/ -uint32_t IRAM_ATTR phy_enter_critical(void) -{ - irqstate_t flags; - - flags = enter_critical_section(); - - return flags; -} +/**************************************************************************** + * Functions needed by libphy.a + ****************************************************************************/ /**************************************************************************** - * Name: phy_exit_critical + * Name: esp_dport_access_reg_read * * Description: - * Exit from critical state + * Read register value safely in SMP * * Input Parameters: - * level - CPU PS value + * reg - Register address * * Returned Value: - * None + * Register value * ****************************************************************************/ -void IRAM_ATTR phy_exit_critical(uint32_t level) +uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg) { - leave_critical_section(level); + return getreg32(reg); } /**************************************************************************** @@ -395,71 +401,6 @@ int phy_printf(const char *format, ...) return 0; } -/**************************************************************************** - * Name: esp32_phy_enable_clock - * - * Description: - * Enable PHY hardware clock - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_phy_enable_clock(void) -{ - irqstate_t flags; - - flags = enter_critical_section(); - - if (g_phy_clk_en_cnt == 0) - { - modifyreg32(DPORT_WIFI_CLK_EN_REG, 0, - DPORT_WIFI_CLK_WIFI_BT_COMMON_M); - } - - g_phy_clk_en_cnt++; - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: esp32_phy_disable_clock - * - * Description: - * Disable PHY hardware clock - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_phy_disable_clock(void) -{ - irqstate_t flags; - - flags = enter_critical_section(); - - if (g_phy_clk_en_cnt > 0) - { - g_phy_clk_en_cnt--; - if (g_phy_clk_en_cnt == 0) - { - modifyreg32(DPORT_WIFI_CLK_EN_REG, - DPORT_WIFI_CLK_WIFI_BT_COMMON_M, - 0); - } - } - - leave_critical_section(flags); -} - #ifdef CONFIG_ESP32_SUPPORT_MULTIPLE_PHY_INIT_DATA /**************************************************************************** @@ -515,7 +456,7 @@ static uint8_t phy_find_bin_type_according_country(const char *country) for (i = 0; i < num; i++) { if (memcmp(country, g_country_code_map_type_table[i].cc, - PHY_COUNTRY_CODE_LEN) == 0) + sizeof(g_phy_current_country)) == 0) { phy_init_data_type = g_country_code_map_type_table[i].type; wlinfo("Current country is %c%c, PHY init data type is %s\n", @@ -606,8 +547,10 @@ static int phy_get_multiple_init_data(uint8_t *data, size_t length, return -ENOMEM; } - int ret = esp32_partition_read(phy_partion_label, length, - control_info, sizeof(phy_control_info_data_t)); + int ret = esp32_partition_read(phy_partion_label, + length, + control_info, + sizeof(phy_control_info_data_t)); if (ret != OK) { kmm_free(control_info); @@ -618,8 +561,9 @@ static int phy_get_multiple_init_data(uint8_t *data, size_t length, if ((control_info->check_algorithm) == PHY_CRC_ALGORITHM) { ret = phy_crc_check(control_info->multiple_bin_checksum, - control_info->control_info_checksum, sizeof(phy_control_info_data_t) - - sizeof(control_info->control_info_checksum)); + control_info->control_info_checksum, + sizeof(phy_control_info_data_t) - + sizeof(control_info->control_info_checksum)); if (ret != OK) { kmm_free(control_info); @@ -762,7 +706,7 @@ static int phy_update_init_data(phy_init_data_type_t init_data_type) if (g_current_apply_phy_init_data != g_phy_init_data_type) { ret = esp_phy_apply_phy_init_data(init_data_store + - sizeof(phy_init_magic_pre)); + sizeof(phy_init_magic_pre)); if (ret != OK) { wlerr("ERROR: PHY init data failed to load\n"); @@ -802,7 +746,7 @@ const esp_phy_init_data_t *esp_phy_get_init_data(void) { int ret; size_t length = sizeof(phy_init_magic_pre) + - sizeof(esp_phy_init_data_t) + sizeof(phy_init_magic_post); + sizeof(esp_phy_init_data_t) + sizeof(phy_init_magic_post); uint8_t *init_data_store = kmm_malloc(length); if (init_data_store == NULL) { @@ -867,6 +811,7 @@ const esp_phy_init_data_t *esp_phy_get_init_data(void) } #endif + wlinfo("PHY data partition validated\n"); return (const esp_phy_init_data_t *) (init_data_store + sizeof(phy_init_magic_pre)); } @@ -931,84 +876,6 @@ void esp_phy_release_init_data(const esp_phy_init_data_t *init_data) } #endif -/**************************************************************************** - * Name: esp_read_mac - * - * Description: - * Read MAC address from efuse - * - * Input Parameters: - * mac - MAC address buffer pointer - * type - MAC address type - * - * Returned Value: - * 0 if success or -1 if fail - * - ****************************************************************************/ - -int32_t esp_read_mac(uint8_t *mac, esp_mac_type_t type) -{ - uint32_t regval[2]; - uint8_t *data = (uint8_t *)regval; - uint8_t crc; - int i; - - if (type > ESP_MAC_BT) - { - wlerr("Input type is error=%d\n", type); - return -1; - } - - regval[0] = getreg32(MAC_ADDR0_REG); - regval[1] = getreg32(MAC_ADDR1_REG); - - crc = data[6]; - for (i = 0; i < MAC_LEN; i++) - { - mac[i] = data[5 - i]; - } - - if (crc != esp_crc8(mac, MAC_LEN)) - { - wlerr("Failed to check MAC address CRC\n"); - return -1; - } - - if (type == ESP_MAC_WIFI_SOFTAP) - { -#ifdef CONFIG_ESP_MAC_ADDR_UNIVERSE_WIFI_AP - mac[5] += 1; -#else - uint8_t tmp = mac[0]; - for (i = 0; i < 64; i++) - { - mac[0] = tmp | 0x02; - mac[0] ^= i << 2; - - if (mac[0] != tmp) - { - break; - } - } - - if (i >= 64) - { - wlerr("Failed to generate SoftAP MAC\n"); - return -1; - } -#endif - } - - if (type == ESP_MAC_BT) - { -#ifdef CONFIG_ESP_MAC_ADDR_UNIVERSE_BT - mac[5] += MAC_ADDR_UNIVERSE_BT_OFFSET; -#endif - } - - return 0; -} - /**************************************************************************** * Name: esp32_phy_update_country_info * @@ -1058,107 +925,134 @@ int esp32_phy_update_country_info(const char *country) } /**************************************************************************** - * Name: esp32_phy_disable + * Name: esp_timer_create * * Description: - * Deinitialize PHY hardware + * Create timer with given arguments * * Input Parameters: - * None + * create_args - Timer arguments data pointer + * out_handle - Timer handle pointer * * Returned Value: - * None + * 0 if success or -1 if fail * ****************************************************************************/ -void esp32_phy_disable(void) +int32_t esp_timer_create(const esp_timer_create_args_t *create_args, + esp_timer_handle_t *out_handle) { - irqstate_t flags; - flags = enter_critical_section(); + int ret; + struct rt_timer_args_s rt_timer_args; + struct rt_timer_s *rt_timer; - g_phy_access_ref--; + rt_timer_args.arg = create_args->arg; + rt_timer_args.callback = create_args->callback; - if (g_phy_access_ref == 0) + ret = rt_timer_create(&rt_timer_args, &rt_timer); + if (ret) { - /* Disable PHY and RF. */ + wlerr("Failed to create rt_timer error=%d\n", ret); + return ret; + } - phy_close_rf(); + *out_handle = (esp_timer_handle_t)rt_timer; - /* Disable Wi-Fi/BT common peripheral clock. - * Do not disable clock for hardware RNG. - */ + return 0; +} - esp32_phy_disable_clock(); - } +/**************************************************************************** + * Name: esp_timer_start_once + * + * Description: + * Start timer with one shot mode + * + * Input Parameters: + * timer - Timer handle pointer + * timeout_us - Timeout value by micro second + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ - leave_critical_section(flags); +int32_t esp_timer_start_once(esp_timer_handle_t timer, uint64_t timeout_us) +{ + struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer; + + rt_timer_start(rt_timer, timeout_us, false); + + return 0; } /**************************************************************************** - * Name: esp32_phy_enable + * Name: esp_timer_start_periodic * * Description: - * Initialize PHY hardware + * Start timer with periodic mode * * Input Parameters: - * None + * timer - Timer handle pointer + * period - Timeout value by micro second * * Returned Value: - * None + * 0 if success or -1 if fail * ****************************************************************************/ -void esp32_phy_enable(void) +int32_t esp_timer_start_periodic(esp_timer_handle_t timer, uint64_t period) { - static bool debug = false; - irqstate_t flags; - esp_phy_calibration_data_t *cal_data; - if (debug == false) - { - char *phy_version = get_phy_version_str(); - wlinfo("phy_version %s\n", phy_version); - debug = true; - } + struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer; - cal_data = kmm_zalloc(sizeof(esp_phy_calibration_data_t)); - if (!cal_data) - { - wlerr("ERROR: Failed to allocate PHY calibration data buffer."); - abort(); - } + rt_timer_start(rt_timer, period, true); - flags = enter_critical_section(); + return 0; +} - if (g_phy_access_ref == 0) - { - esp32_phy_enable_clock(); - if (g_is_phy_calibrated == false) - { - const esp_phy_init_data_t *init_data = esp_phy_get_init_data(); - if (init_data == NULL) - { - wlerr("ERROR: Failed to obtain PHY init data"); - abort(); - } +/**************************************************************************** + * Name: esp_timer_stop + * + * Description: + * Stop timer + * + * Input Parameters: + * timer - Timer handle pointer + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ - register_chipv7_phy(init_data, cal_data, PHY_RF_CAL_FULL); - esp_phy_release_init_data(init_data); - g_is_phy_calibrated = true; - } - else - { - phy_wakeup_init(); - phy_digital_regs_load(); - } +int32_t esp_timer_stop(esp_timer_handle_t timer) +{ + struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer; -#ifdef CONFIG_ESP32_BLE - coex_bt_high_prio(); -#endif - } + rt_timer_stop(rt_timer); - g_phy_access_ref++; - leave_critical_section(flags); - kmm_free(cal_data); + return 0; +} + +/**************************************************************************** + * Name: esp_timer_delete + * + * Description: + * Delete timer and free resource + * + * Input Parameters: + * timer - Timer handle pointer + * + * Returned Value: + * 0 if success or -1 if fail + * + ****************************************************************************/ + +int32_t esp_timer_delete(esp_timer_handle_t timer) +{ + struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer; + + rt_timer_delete(rt_timer); + + return 0; } /**************************************************************************** @@ -1397,3 +1291,99 @@ int esp_wireless_deinit(void) return OK; } + +#ifdef CONFIG_ESP32_WIFI + +/**************************************************************************** + * Name: esp_wifi_init + * + * Description: + * Initialize Wi-Fi + * + * Input Parameters: + * config - Initialization config parameters + * + * Returned Value: + * 0 if success or others if fail + * + ****************************************************************************/ + +int32_t esp_wifi_init(const wifi_init_config_t *config) +{ + int32_t ret; + + esp_wifi_power_domain_on(); + +#ifdef CONFIG_ESP32_WIFI_BT_COEXIST + ret = coex_init(); + if (ret) + { + wlerr("ERROR: Failed to initialize coex error=%d\n", ret); + return ret; + } +#endif /* CONFIG_ESP32_WIFI_BT_COEXIST */ + + esp_wifi_set_log_level(); + + ret = esp_wifi_init_internal(config); + if (ret) + { + wlerr("Failed to initialize Wi-Fi error=%d\n", ret); + return ret; + } + +#if CONFIG_MAC_BB_PD + esp_mac_bb_pd_mem_init(); + esp_wifi_internal_set_mac_sleep(true); +#endif + + esp_phy_modem_init(); + + g_wifi_mac_time_update_cb = esp_wifi_internal_update_mac_time; + + ret = esp_supplicant_init(); + if (ret) + { + wlerr("Failed to initialize WPA supplicant error=%d\n", ret); + esp_wifi_deinit_internal(); + return ret; + } + + return 0; +} + +/**************************************************************************** + * Name: esp_wifi_deinit + * + * Description: + * Deinitialize Wi-Fi and free resource + * + * Input Parameters: + * None + * + * Returned Value: + * 0 if success or others if fail + * + ****************************************************************************/ + +int32_t esp_wifi_deinit(void) +{ + int ret; + + ret = esp_supplicant_deinit(); + if (ret) + { + wlerr("Failed to deinitialize supplicant\n"); + return ret; + } + + ret = esp_wifi_deinit_internal(); + if (ret != 0) + { + wlerr("Failed to deinitialize Wi-Fi\n"); + return ret; + } + + return ret; +} +#endif /* CONFIG_ESP32_WIFI */ diff --git a/arch/xtensa/src/esp32/esp32_wireless.h b/arch/xtensa/src/esp32/esp32_wireless.h index 6b7e328cfa73e..6c183792682de 100644 --- a/arch/xtensa/src/esp32/esp32_wireless.h +++ b/arch/xtensa/src/esp32/esp32_wireless.h @@ -32,8 +32,16 @@ #include #include "xtensa_attr.h" +#include "esp32_rt_timer.h" -#include "espidf_wifi.h" +#include "esp_log.h" +#include "esp_mac.h" +#include "esp_private/phy.h" +#include "esp_private/wifi.h" +#include "esp_random.h" +#include "esp_timer.h" +#include "rom/ets_sys.h" +#include "soc/soc_caps.h" /**************************************************************************** * Pre-processor Definitions @@ -82,153 +90,124 @@ struct esp_queuecache_s ****************************************************************************/ /**************************************************************************** - * Name: esp_read_mac - * - * Description: - * Read MAC address from efuse - * - * Input Parameters: - * mac - MAC address buffer pointer - * type - MAC address type - * - * Returned Value: - * 0 if success or -1 if fail - * - ****************************************************************************/ - -int32_t esp_read_mac(uint8_t *mac, esp_mac_type_t type); - -/**************************************************************************** - * Name: esp32_phy_enable - * - * Description: - * Initialize PHY hardware - * - * Input Parameters: - * None - * - * Returned Value: - * None - * + * Functions needed by libphy.a ****************************************************************************/ -void esp32_phy_enable(void); - /**************************************************************************** - * Name: esp32_phy_disable + * Name: esp_dport_access_reg_read * * Description: - * Deinitialize PHY hardware + * Read register value safely in SMP * * Input Parameters: - * None + * reg - Register address * * Returned Value: - * None + * Register value * ****************************************************************************/ -void esp32_phy_disable(void); +uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg); /**************************************************************************** - * Name: esp32_phy_enable_clock + * Name: phy_printf * * Description: - * Enable PHY clock + * Output format string and its arguments * * Input Parameters: - * None + * format - format string * * Returned Value: - * None + * 0 * ****************************************************************************/ -void esp32_phy_enable_clock(void); +int phy_printf(const char *format, ...) printf_like(1, 2); /**************************************************************************** - * Name: esp32_phy_disable_clock + * Name: esp_timer_create * * Description: - * Disable PHY clock + * Create timer with given arguments * * Input Parameters: - * None + * create_args - Timer arguments data pointer + * out_handle - Timer handle pointer * * Returned Value: - * None + * 0 if success or -1 if fail * ****************************************************************************/ -void esp32_phy_disable_clock(void); +int32_t esp_timer_create(const esp_timer_create_args_t *create_args, + esp_timer_handle_t *out_handle); /**************************************************************************** - * Functions needed by libphy.a - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_dport_access_reg_read + * Name: esp_timer_start_once * * Description: - * Read register value safely in SMP + * Start timer with one shot mode * * Input Parameters: - * reg - Register address + * timer - Timer handle pointer + * timeout_us - Timeout value by micro second * * Returned Value: - * Register value + * 0 if success or -1 if fail * ****************************************************************************/ -uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg); +int32_t esp_timer_start_once(esp_timer_handle_t timer, uint64_t timeout_us); /**************************************************************************** - * Name: phy_enter_critical + * Name: esp_timer_start_periodic * * Description: - * Enter critical state + * Start timer with periodic mode * * Input Parameters: - * None + * timer - Timer handle pointer + * period - Timeout value by micro second * * Returned Value: - * CPU PS value + * 0 if success or -1 if fail * ****************************************************************************/ -uint32_t IRAM_ATTR phy_enter_critical(void); +int32_t esp_timer_start_periodic(esp_timer_handle_t timer, uint64_t period); /**************************************************************************** - * Name: phy_exit_critical + * Name: esp_timer_stop * * Description: - * Exit from critical state + * Stop timer * * Input Parameters: - * level - CPU PS value + * timer - Timer handle pointer * * Returned Value: - * None + * 0 if success or -1 if fail * ****************************************************************************/ -void IRAM_ATTR phy_exit_critical(uint32_t level); +int32_t esp_timer_stop(esp_timer_handle_t timer); /**************************************************************************** - * Name: phy_printf + * Name: esp_timer_delete * * Description: - * Output format string and its arguments + * Delete timer and free resource * * Input Parameters: - * format - format string + * timer - Timer handle pointer * * Returned Value: - * 0 + * 0 if success or -1 if fail * ****************************************************************************/ -int phy_printf(const char *format, ...) printf_like(1, 2); +int32_t esp_timer_delete(esp_timer_handle_t timer); /**************************************************************************** * Name: esp32_phy_update_country_info diff --git a/arch/xtensa/src/esp32/esp32_wlan.c b/arch/xtensa/src/esp32/esp32_wlan.c index f66a429aec9b3..c242db1906cff 100644 --- a/arch/xtensa/src/esp32/esp32_wlan.c +++ b/arch/xtensa/src/esp32/esp32_wlan.c @@ -31,6 +31,7 @@ #include #include +#include #include #include #include @@ -200,7 +201,7 @@ struct wlan_priv_s /* Reference count of register Wi-Fi handler */ -static uint8_t g_callback_register_ref = 0; +static uint8_t g_callback_register_ref; static struct wlan_priv_s g_wlan_priv[ESP32_WLAN_DEVS]; diff --git a/arch/xtensa/src/esp32/hal.mk b/arch/xtensa/src/esp32/hal.mk new file mode 100644 index 0000000000000..3257f81a46804 --- /dev/null +++ b/arch/xtensa/src/esp32/hal.mk @@ -0,0 +1,110 @@ +############################################################################ +# arch/xtensa/src/esp32/hal.mk +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Include header paths + +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_event$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)esp_private +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include$(DELIM)private +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)public_compat +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)platform_port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include + +# Linker scripts + +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.api.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).peripherals.ld + +# Source files + +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_api.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_utility.c + +# Please note that the following source file depends on `CONFIG_SOC_EFUSE_KEY_PURPOSE_FIELD` and `CONFIG_SOC_EFUSE_CONSISTS_OF_ONE_KEY_BLOCK` +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)efuse_controller$(DELIM)keys$(DELIM)without_key_purposes$(DELIM)three_key_blocks$(DELIM)esp_efuse_api_key.c + +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_fields.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_table.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_utility.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)cpu.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)hw_random.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mac_addr.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)periph_ctrl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_time.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_wdt.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)efuse_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)brownout_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)efuse_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gpio_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log_noos.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gpio_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c + +CFLAGS += ${DEFINE_PREFIX}ESP_PLATFORM=1 diff --git a/arch/xtensa/src/esp32/hardware/efuse_reg.h b/arch/xtensa/src/esp32/hardware/efuse_reg.h deleted file mode 100644 index 8ec7b6ea21a09..0000000000000 --- a/arch/xtensa/src/esp32/hardware/efuse_reg.h +++ /dev/null @@ -1,1827 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/hardware/efuse_reg.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_EFUSE_REG_H -#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_EFUSE_REG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32_soc.h" - -#define EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x000) - -/* EFUSE_RD_FLASH_CRYPT_CNT : RO ;bitpos:[26:20] ;default: 7'b0 ; - * Description: read for flash_crypt_cnt - */ - -#define EFUSE_RD_FLASH_CRYPT_CNT 0x0000007f -#define EFUSE_RD_FLASH_CRYPT_CNT_M ((EFUSE_RD_FLASH_CRYPT_CNT_V) << \ - (EFUSE_RD_FLASH_CRYPT_CNT_S)) -#define EFUSE_RD_FLASH_CRYPT_CNT_V 0x7f -#define EFUSE_RD_FLASH_CRYPT_CNT_S 20 - -/* EFUSE_RD_EFUSE_RD_DIS : RO ;bitpos:[19:16] ;default: 4'b0 ; - * Description: read for efuse_rd_disable - */ - -#define EFUSE_RD_EFUSE_RD_DIS 0x0000000f -#define EFUSE_RD_EFUSE_RD_DIS_M ((EFUSE_RD_EFUSE_RD_DIS_V) << \ - (EFUSE_RD_EFUSE_RD_DIS_S)) -#define EFUSE_RD_EFUSE_RD_DIS_V 0xf -#define EFUSE_RD_EFUSE_RD_DIS_S 16 - -/* Read disable bits for efuse blocks 1-3 */ - -#define EFUSE_RD_DIS_BLK1 (1 << 16) -#define EFUSE_RD_DIS_BLK2 (1 << 17) -#define EFUSE_RD_DIS_BLK3 (1 << 18) - -/* Read disable FLASH_CRYPT_CONFIG, CODING_SCHEME & KEY_STATUS - * in efuse block 0 - */ - -#define EFUSE_RD_DIS_BLK0_PARTIAL (1 << 19) - -/* EFUSE_RD_EFUSE_WR_DIS : RO ;bitpos:[15:0] ;default: 16'b0 ; - * Description: read for efuse_wr_disable - */ - -#define EFUSE_RD_EFUSE_WR_DIS 0x0000ffff -#define EFUSE_RD_EFUSE_WR_DIS_M ((EFUSE_RD_EFUSE_WR_DIS_V) << \ - (EFUSE_RD_EFUSE_WR_DIS_S)) -#define EFUSE_RD_EFUSE_WR_DIS_V 0xffff -#define EFUSE_RD_EFUSE_WR_DIS_S 0 - -/* Write disable bits */ - -#define EFUSE_WR_DIS_RD_DIS (1 << 0) /* disable writing read disable reg */ -#define EFUSE_WR_DIS_WR_DIS (1 << 1) /* disable writing write disable reg */ -#define EFUSE_WR_DIS_FLASH_CRYPT_CNT (1 << 2) -#define EFUSE_WR_DIS_MAC_SPI_CONFIG_HD (1 << 3) /* disable writing MAC & SPI config hd efuses */ -#define EFUSE_WR_DIS_XPD_SDIO (1 << 5) /* disable writing SDIO config efuses */ -#define EFUSE_WR_DIS_SPI_PAD_CONFIG (1 << 6) /* disable writing SPI_PAD_CONFIG efuses */ -#define EFUSE_WR_DIS_BLK1 (1 << 7) /* disable writing BLK1 efuses */ -#define EFUSE_WR_DIS_BLK2 (1 << 8) /* disable writing BLK2 efuses */ -#define EFUSE_WR_DIS_BLK3 (1 << 9) /* disable writing BLK3 efuses */ -#define EFUSE_WR_DIS_FL_CRYPT_COD_SCH (1 << 10) /* disable writing FLASH_CRYPT_CONFIG and CODING_SCHEME efuses */ -#define EFUSE_WR_DIS_ABS_DONE_0 (1 << 12) /* disable writing ABS_DONE_0 efuse */ -#define EFUSE_WR_DIS_ABS_DONE_1 (1 << 13) /* disable writing ABS_DONE_1 efuse */ -#define EFUSE_WR_DIS_JTAG_DISABLE (1 << 14) /* disable writing JTAG_DISABLE efuse */ -#define EFUSE_WR_DIS_CONSOLE_DL_DISABLE (1 << 15) /* disable writing CONSOLE_DEBUG_DISABLE, DISABLE_DL_ENCRYPT, DISABLE_DL_DECRYPT and DISABLE_DL_CACHE efuses */ - -#define EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x004) - -/* EFUSE_RD_WIFI_MAC_CRC_LOW : RO ;bitpos:[31:0] ;default: 32'b0 ; - * Description: read for low 32bit WIFI_MAC_Address - */ - -#define EFUSE_RD_WIFI_MAC_CRC_LOW 0xffffffff -#define EFUSE_RD_WIFI_MAC_CRC_LOW_M ((EFUSE_RD_WIFI_MAC_CRC_LOW_V) << \ - (EFUSE_RD_WIFI_MAC_CRC_LOW_S)) -#define EFUSE_RD_WIFI_MAC_CRC_LOW_V 0xffffffff -#define EFUSE_RD_WIFI_MAC_CRC_LOW_S 0 - -#define EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x008) - -/* EFUSE_RD_WIFI_MAC_CRC_HIGH : RO ;bitpos:[23:0] ;default: 24'b0 ; - * Description: read for high 24bit WIFI_MAC_Address - */ - -#define EFUSE_RD_WIFI_MAC_CRC_HIGH 0x00ffffff -#define EFUSE_RD_WIFI_MAC_CRC_HIGH_M ((EFUSE_RD_WIFI_MAC_CRC_HIGH_V) << \ - (EFUSE_RD_WIFI_MAC_CRC_HIGH_S)) -#define EFUSE_RD_WIFI_MAC_CRC_HIGH_V 0xffffff -#define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0 - -#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c) - -/* EFUSE_RD_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; - * Description: bit is set to 1 for rev1 silicon - */ - -#define EFUSE_RD_CHIP_VER_REV1 (BIT(15)) -#define EFUSE_RD_CHIP_VER_REV1_M ((EFUSE_RD_CHIP_VER_REV1_V) << \ - (EFUSE_RD_CHIP_VER_REV1_S)) -#define EFUSE_RD_CHIP_VER_REV1_V 0x1 -#define EFUSE_RD_CHIP_VER_REV1_S 15 - -/* EFUSE_RD_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; - * Description: If set, this bit indicates that BLOCK3[143:96] is reserved - * for internal use - */ - -#define EFUSE_RD_BLK3_PART_RESERVE (BIT(14)) -#define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V) << \ - (EFUSE_RD_BLK3_PART_RESERVE_S)) -#define EFUSE_RD_BLK3_PART_RESERVE_V 0x1 -#define EFUSE_RD_BLK3_PART_RESERVE_S 14 - -/* EFUSE_RD_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; - * Description: If set, the ESP32's maximum CPU frequency has been rated - */ - -#define EFUSE_RD_CHIP_CPU_FREQ_RATED (BIT(13)) -#define EFUSE_RD_CHIP_CPU_FREQ_RATED_M ((EFUSE_RD_CHIP_CPU_FREQ_RATED_V) << \ - (EFUSE_RD_CHIP_CPU_FREQ_RATED_S)) -#define EFUSE_RD_CHIP_CPU_FREQ_RATED_V 0x1 -#define EFUSE_RD_CHIP_CPU_FREQ_RATED_S 13 - -/* EFUSE_RD_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; - * Description: If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's - * max CPU frequency is rated for 160MHz. 240MHz otherwise - */ - -#define EFUSE_RD_CHIP_CPU_FREQ_LOW (BIT(12)) -#define EFUSE_RD_CHIP_CPU_FREQ_LOW_M ((EFUSE_RD_CHIP_CPU_FREQ_LOW_V) << \ - (EFUSE_RD_CHIP_CPU_FREQ_LOW_S)) -#define EFUSE_RD_CHIP_CPU_FREQ_LOW_V 0x1 -#define EFUSE_RD_CHIP_CPU_FREQ_LOW_S 12 - -/* EFUSE_RD_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; - * Description: chip package - */ - -#define EFUSE_RD_CHIP_VER_PKG 0x00000007 -#define EFUSE_RD_CHIP_VER_PKG_M ((EFUSE_RD_CHIP_VER_PKG_V) << \ - (EFUSE_RD_CHIP_VER_PKG_S)) -#define EFUSE_RD_CHIP_VER_PKG_V 0x7 -#define EFUSE_RD_CHIP_VER_PKG_S 9 -#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0 -#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1 -#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2 -#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 -#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5 - -/* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; - * Description: read for SPI_pad_config_hd - */ - -#define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001f -#define EFUSE_RD_SPI_PAD_CONFIG_HD_M ((EFUSE_RD_SPI_PAD_CONFIG_HD_V) << \ - (EFUSE_RD_SPI_PAD_CONFIG_HD_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_HD_V 0x1f -#define EFUSE_RD_SPI_PAD_CONFIG_HD_S 4 - -/* EFUSE_RD_CHIP_VER_DIS_CACHE : RO ;bitpos:[3] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_RD_CHIP_VER_DIS_CACHE (BIT(3)) -#define EFUSE_RD_CHIP_VER_DIS_CACHE_M (BIT(3)) -#define EFUSE_RD_CHIP_VER_DIS_CACHE_V 0x1 -#define EFUSE_RD_CHIP_VER_DIS_CACHE_S 3 - -/* EFUSE_RD_CHIP_VER_32PAD : RO ;bitpos:[2] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_RD_CHIP_VER_32PAD (BIT(2)) -#define EFUSE_RD_CHIP_VER_32PAD_M (BIT(2)) -#define EFUSE_RD_CHIP_VER_32PAD_V 0x1 -#define EFUSE_RD_CHIP_VER_32PAD_S 2 - -/* EFUSE_RD_CHIP_VER_DIS_BT : RO ;bitpos:[1] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_RD_CHIP_VER_DIS_BT (BIT(1)) -#define EFUSE_RD_CHIP_VER_DIS_BT_M (BIT(1)) -#define EFUSE_RD_CHIP_VER_DIS_BT_V 0x1 -#define EFUSE_RD_CHIP_VER_DIS_BT_S 1 - -/* EFUSE_RD_CHIP_VER_DIS_APP_CPU : RO ;bitpos:[0] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_RD_CHIP_VER_DIS_APP_CPU (BIT(0)) -#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_M (BIT(0)) -#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_V 0x1 -#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_S 0 - -#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010) - -/* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; - * Description: read for sdio_force - */ - -#define EFUSE_RD_SDIO_FORCE (BIT(16)) -#define EFUSE_RD_SDIO_FORCE_M (BIT(16)) -#define EFUSE_RD_SDIO_FORCE_V 0x1 -#define EFUSE_RD_SDIO_FORCE_S 16 - -/* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; - * Description: read for SDIO_TIEH - */ - -#define EFUSE_RD_SDIO_TIEH (BIT(15)) -#define EFUSE_RD_SDIO_TIEH_M (BIT(15)) -#define EFUSE_RD_SDIO_TIEH_V 0x1 -#define EFUSE_RD_SDIO_TIEH_S 15 - -/* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; - * Description: read for XPD_SDIO_REG - */ - -#define EFUSE_RD_XPD_SDIO_REG (BIT(14)) -#define EFUSE_RD_XPD_SDIO_REG_M (BIT(14)) -#define EFUSE_RD_XPD_SDIO_REG_V 0x1 -#define EFUSE_RD_XPD_SDIO_REG_S 14 - -/* EFUSE_RD_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; - * Description: True ADC reference voltage - */ - -#define EFUSE_RD_ADC_VREF 0x0000001f -#define EFUSE_RD_ADC_VREF_M ((EFUSE_RD_ADC_VREF_V) << \ - (EFUSE_RD_ADC_VREF_S)) -#define EFUSE_RD_ADC_VREF_V 0x1f -#define EFUSE_RD_ADC_VREF_S 8 - -/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. - * Newer versions of ESP32 come with EFUSE_ADC_VREF already burned, - * therefore SDIO_DREFH/M/L is only available in older versions of ESP32 - */ - -/* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; - * Description: - */ - -#define EFUSE_RD_SDIO_DREFL 0x00000003 -#define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V) << \ - (EFUSE_RD_SDIO_DREFL_S)) -#define EFUSE_RD_SDIO_DREFL_V 0x3 -#define EFUSE_RD_SDIO_DREFL_S 12 - -/* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; - * Description: - */ - -#define EFUSE_RD_SDIO_DREFM 0x00000003 -#define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V) << \ - (EFUSE_RD_SDIO_DREFM_S)) -#define EFUSE_RD_SDIO_DREFM_V 0x3 -#define EFUSE_RD_SDIO_DREFM_S 10 - -/* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; - * Description: - */ - -#define EFUSE_RD_SDIO_DREFH 0x00000003 -#define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V) << \ - (EFUSE_RD_SDIO_DREFH_S)) -#define EFUSE_RD_SDIO_DREFH_V 0x3 -#define EFUSE_RD_SDIO_DREFH_S 8 - -/* EFUSE_RD_CK8M_FREQ : RO ;bitpos:[7:0] ;default: 8'b0 ; - * Description: - */ - -#define EFUSE_RD_CK8M_FREQ 0x000000ff -#define EFUSE_RD_CK8M_FREQ_M ((EFUSE_RD_CK8M_FREQ_V) << \ - (EFUSE_RD_CK8M_FREQ_S)) -#define EFUSE_RD_CK8M_FREQ_V 0xff -#define EFUSE_RD_CK8M_FREQ_S 0 - -#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014) - -/* EFUSE_RD_FLASH_CRYPT_CONFIG : RO ;bitpos:[31:28] ;default: 4'b0 ; - * Description: read for flash_crypt_config - */ - -#define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000f -#define EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V) << \ - (EFUSE_RD_FLASH_CRYPT_CONFIG_S)) -#define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xf -#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28 - -/* EFUSE_RD_DIG_VOL_L6: RO; bitpos:[27:24]; - * Description: This field stores the difference between the digital - * regulator voltage at level6 and 1.2 V. (RO) - * BIT[27] is the sign bit, 0: + , 1: - - * BIT[26:24] is the difference value, unit: 0.017V - * volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + - * BIT[26:24] * 0.017 - */ - -#define EFUSE_RD_DIG_VOL_L6 0x0f -#define EFUSE_RD_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V) << \ - (EFUSE_RD_DIG_VOL_L6_S)) -#define EFUSE_RD_DIG_VOL_L6_V 0x0f -#define EFUSE_RD_DIG_VOL_L6_S 24 - -/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] - * Description: This field stores the voltage level for CPU to run at 240 MHz - * or for flash/PSRAM to run at 80 MHz. - * 0x0: level 7; - * 0x1: level 6; - * 0x2: level 5; - * 0x3: level 4. (RO) - */ - -#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03 -#define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V) << \ - (EFUSE_RD_VOL_LEVEL_HP_INV_S)) -#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03 -#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 - -/* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; - * Deprecated - */ - -#define EFUSE_RD_INST_CONFIG 0x000000ff /* Deprecated */ -#define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V) << \ - (EFUSE_RD_INST_CONFIG_S)) -#define EFUSE_RD_INST_CONFIG_V 0xff /* Deprecated */ -#define EFUSE_RD_INST_CONFIG_S 20 /* Deprecated */ - -/* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; - * Description: read for SPI_pad_config_cs0 - */ - -#define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001f -#define EFUSE_RD_SPI_PAD_CONFIG_CS0_M ((EFUSE_RD_SPI_PAD_CONFIG_CS0_V) << \ - (EFUSE_RD_SPI_PAD_CONFIG_CS0_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_CS0_V 0x1f -#define EFUSE_RD_SPI_PAD_CONFIG_CS0_S 15 - -/* EFUSE_RD_SPI_PAD_CONFIG_D : RO ;bitpos:[14:10] ;default: 5'b0 ; - * Description: read for SPI_pad_config_d - */ - -#define EFUSE_RD_SPI_PAD_CONFIG_D 0x0000001f -#define EFUSE_RD_SPI_PAD_CONFIG_D_M ((EFUSE_RD_SPI_PAD_CONFIG_D_V) << \ - (EFUSE_RD_SPI_PAD_CONFIG_D_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_D_V 0x1f -#define EFUSE_RD_SPI_PAD_CONFIG_D_S 10 - -/* EFUSE_RD_SPI_PAD_CONFIG_Q : RO ;bitpos:[9:5] ;default: 5'b0 ; - * Description: read for SPI_pad_config_q - */ - -#define EFUSE_RD_SPI_PAD_CONFIG_Q 0x0000001f -#define EFUSE_RD_SPI_PAD_CONFIG_Q_M ((EFUSE_RD_SPI_PAD_CONFIG_Q_V) << \ - (EFUSE_RD_SPI_PAD_CONFIG_Q_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_Q_V 0x1f -#define EFUSE_RD_SPI_PAD_CONFIG_Q_S 5 - -/* EFUSE_RD_SPI_PAD_CONFIG_CLK : RO ;bitpos:[4:0] ;default: 5'b0 ; - * Description: read for SPI_pad_config_clk - */ - -#define EFUSE_RD_SPI_PAD_CONFIG_CLK 0x0000001f -#define EFUSE_RD_SPI_PAD_CONFIG_CLK_M ((EFUSE_RD_SPI_PAD_CONFIG_CLK_V) << \ - (EFUSE_RD_SPI_PAD_CONFIG_CLK_S)) -#define EFUSE_RD_SPI_PAD_CONFIG_CLK_V 0x1f -#define EFUSE_RD_SPI_PAD_CONFIG_CLK_S 0 - -#define EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x018) - -/* EFUSE_RD_KEY_STATUS : RO ;bitpos:[10] ;default: 1'b0 ; - * Description: read for key_status - */ - -#define EFUSE_RD_KEY_STATUS (BIT(10)) -#define EFUSE_RD_KEY_STATUS_M (BIT(10)) -#define EFUSE_RD_KEY_STATUS_V 0x1 -#define EFUSE_RD_KEY_STATUS_S 10 - -/* EFUSE_RD_DISABLE_DL_CACHE : RO ;bitpos:[9] ;default: 1'b0 ; - * Description: read for download_dis_cache - */ - -#define EFUSE_RD_DISABLE_DL_CACHE (BIT(9)) -#define EFUSE_RD_DISABLE_DL_CACHE_M (BIT(9)) -#define EFUSE_RD_DISABLE_DL_CACHE_V 0x1 -#define EFUSE_RD_DISABLE_DL_CACHE_S 9 - -/* EFUSE_RD_DISABLE_DL_DECRYPT : RO ;bitpos:[8] ;default: 1'b0 ; - * Description: read for download_dis_decrypt - */ - -#define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8)) -#define EFUSE_RD_DISABLE_DL_DECRYPT_M (BIT(8)) -#define EFUSE_RD_DISABLE_DL_DECRYPT_V 0x1 -#define EFUSE_RD_DISABLE_DL_DECRYPT_S 8 - -/* EFUSE_RD_DISABLE_DL_ENCRYPT : RO ;bitpos:[7] ;default: 1'b0 ; - * Description: read for download_dis_encrypt - */ - -#define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7)) -#define EFUSE_RD_DISABLE_DL_ENCRYPT_M (BIT(7)) -#define EFUSE_RD_DISABLE_DL_ENCRYPT_V 0x1 -#define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7 - -/* EFUSE_RD_DISABLE_JTAG : RO ;bitpos:[6] ;default: 1'b0 ; - * Description: read for JTAG_disable - */ - -#define EFUSE_RD_DISABLE_JTAG (BIT(6)) -#define EFUSE_RD_DISABLE_JTAG_M (BIT(6)) -#define EFUSE_RD_DISABLE_JTAG_V 0x1 -#define EFUSE_RD_DISABLE_JTAG_S 6 - -/* EFUSE_RD_ABS_DONE_1 : RO ;bitpos:[5] ;default: 1'b0 ; - * Description: read for abstract_done_1 - */ - -#define EFUSE_RD_ABS_DONE_1 (BIT(5)) -#define EFUSE_RD_ABS_DONE_1_M (BIT(5)) -#define EFUSE_RD_ABS_DONE_1_V 0x1 -#define EFUSE_RD_ABS_DONE_1_S 5 - -/* EFUSE_RD_ABS_DONE_0 : RO ;bitpos:[4] ;default: 1'b0 ; - * Description: read for abstract_done_0 - */ - -#define EFUSE_RD_ABS_DONE_0 (BIT(4)) -#define EFUSE_RD_ABS_DONE_0_M (BIT(4)) -#define EFUSE_RD_ABS_DONE_0_V 0x1 -#define EFUSE_RD_ABS_DONE_0_S 4 - -/* EFUSE_RD_DISABLE_SDIO_HOST : RO ;bitpos:[3] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3)) -#define EFUSE_RD_DISABLE_SDIO_HOST_M (BIT(3)) -#define EFUSE_RD_DISABLE_SDIO_HOST_V 0x1 -#define EFUSE_RD_DISABLE_SDIO_HOST_S 3 - -/* EFUSE_RD_CONSOLE_DEBUG_DISABLE : RO ;bitpos:[2] ;default: 1'b0 ; - * Description: read for console_debug_disable - */ - -#define EFUSE_RD_CONSOLE_DEBUG_DISABLE (BIT(2)) -#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_M (BIT(2)) -#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_V 0x1 -#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_S 2 - -/* EFUSE_RD_CODING_SCHEME : RO ;bitpos:[1:0] ;default: 2'b0 ; - * Description: read for coding_scheme - */ - -#define EFUSE_RD_CODING_SCHEME 0x00000003 -#define EFUSE_RD_CODING_SCHEME_M ((EFUSE_RD_CODING_SCHEME_V) << \ - (EFUSE_RD_CODING_SCHEME_S)) -#define EFUSE_RD_CODING_SCHEME_V 0x3 -#define EFUSE_RD_CODING_SCHEME_S 0 - -#define EFUSE_CODING_SCHEME_VAL_NONE 0x0 -#define EFUSE_CODING_SCHEME_VAL_34 0x1 -#define EFUSE_CODING_SCHEME_VAL_REPEAT 0x2 - -#define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x01c) - -/* EFUSE_FLASH_CRYPT_CNT : R/W ;bitpos:[26:20] ;default: 7'b0 ; - * Description: program for flash_crypt_cnt - */ - -#define EFUSE_FLASH_CRYPT_CNT 0x0000007f -#define EFUSE_FLASH_CRYPT_CNT_M ((EFUSE_FLASH_CRYPT_CNT_V) << \ - (EFUSE_FLASH_CRYPT_CNT_S)) -#define EFUSE_FLASH_CRYPT_CNT_V 0x7f -#define EFUSE_FLASH_CRYPT_CNT_S 20 - -/* EFUSE_RD_DIS : R/W ;bitpos:[19:16] ;default: 4'b0 ; - * Description: program for efuse_rd_disable - */ - -#define EFUSE_RD_DIS 0x0000000f -#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V) << \ - (EFUSE_RD_DIS_S)) -#define EFUSE_RD_DIS_V 0xf -#define EFUSE_RD_DIS_S 16 - -/* EFUSE_WR_DIS : R/W ;bitpos:[15:0] ;default: 16'b0 ; - * Description: program for efuse_wr_disable - */ - -#define EFUSE_WR_DIS 0x0000ffff -#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V) << \ - (EFUSE_WR_DIS_S)) -#define EFUSE_WR_DIS_V 0xffff -#define EFUSE_WR_DIS_S 0 - -#define EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x020) - -/* EFUSE_WIFI_MAC_CRC_LOW : R/W ;bitpos:[31:0] ;default: 32'b0 ; - * Description: program for low 32bit WIFI_MAC_Address - */ - -#define EFUSE_WIFI_MAC_CRC_LOW 0xffffffff -#define EFUSE_WIFI_MAC_CRC_LOW_M ((EFUSE_WIFI_MAC_CRC_LOW_V) << \ - (EFUSE_WIFI_MAC_CRC_LOW_S)) -#define EFUSE_WIFI_MAC_CRC_LOW_V 0xffffffff -#define EFUSE_WIFI_MAC_CRC_LOW_S 0 - -#define EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x024) - -/* EFUSE_WIFI_MAC_CRC_HIGH : R/W ;bitpos:[23:0] ;default: 24'b0 ; - * Description: program for high 24bit WIFI_MAC_Address - */ - -#define EFUSE_WIFI_MAC_CRC_HIGH 0x00ffffff -#define EFUSE_WIFI_MAC_CRC_HIGH_M ((EFUSE_WIFI_MAC_CRC_HIGH_V) << \ - (EFUSE_WIFI_MAC_CRC_HIGH_S)) -#define EFUSE_WIFI_MAC_CRC_HIGH_V 0xffffff -#define EFUSE_WIFI_MAC_CRC_HIGH_S 0 - -#define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x028) - -/* EFUSE_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_CHIP_VER_REV1 (BIT(15)) -#define EFUSE_CHIP_VER_REV1_M ((EFUSE_CHIP_VER_REV1_V) << \ - (EFUSE_CHIP_VER_REV1_S)) -#define EFUSE_CHIP_VER_REV1_V 0x1 -#define EFUSE_CHIP_VER_REV1_S 15 - -/* EFUSE_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; - * Description: If set, this bit indicates that BLOCK3[143:96] is reserved - * for internal use - */ - -#define EFUSE_BLK3_PART_RESERVE (BIT(14)) -#define EFUSE_BLK3_PART_RESERVE_M ((EFUSE_BLK3_PART_RESERVE_V) << \ - (EFUSE_BLK3_PART_RESERVE_S)) -#define EFUSE_BLK3_PART_RESERVE_V 0x1 -#define EFUSE_BLK3_PART_RESERVE_S 14 - -/* EFUSE_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; - * Description: If set, the ESP32's maximum CPU frequency has been rated - */ - -#define EFUSE_CHIP_CPU_FREQ_RATED (BIT(13)) -#define EFUSE_CHIP_CPU_FREQ_RATED_M ((EFUSE_CHIP_CPU_FREQ_RATED_V) << \ - (EFUSE_CHIP_CPU_FREQ_RATED_S)) -#define EFUSE_CHIP_CPU_FREQ_RATED_V 0x1 -#define EFUSE_CHIP_CPU_FREQ_RATED_S 13 - -/* EFUSE_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; - * Description: If set alongside EFUSE_CHIP_CPU_FREQ_RATED, the ESP32's max - * CPU frequency is rated for 160MHz. 240MHz otherwise - */ - -#define EFUSE_CHIP_CPU_FREQ_LOW (BIT(12)) -#define EFUSE_CHIP_CPU_FREQ_LOW_M ((EFUSE_CHIP_CPU_FREQ_LOW_V) << \ - (EFUSE_CHIP_CPU_FREQ_LOW_S)) -#define EFUSE_CHIP_CPU_FREQ_LOW_V 0x1 -#define EFUSE_CHIP_CPU_FREQ_LOW_S 12 - -/* EFUSE_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; - * Description: - */ - -#define EFUSE_CHIP_VER_PKG 0x00000007 -#define EFUSE_CHIP_VER_PKG_M ((EFUSE_CHIP_VER_PKG_V) << \ - (EFUSE_CHIP_VER_PKG_S)) -#define EFUSE_CHIP_VER_PKG_V 0x7 -#define EFUSE_CHIP_VER_PKG_S 9 -#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ6 0 -#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ5 1 -#define EFUSE_CHIP_VER_PKG_ESP32D2WDQ5 2 -#define EFUSE_CHIP_VER_PKG_ESP32PICOD2 4 -#define EFUSE_CHIP_VER_PKG_ESP32PICOD4 5 - -/* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; - * Description: program for SPI_pad_config_hd - */ - -#define EFUSE_SPI_PAD_CONFIG_HD 0x0000001f -#define EFUSE_SPI_PAD_CONFIG_HD_M ((EFUSE_SPI_PAD_CONFIG_HD_V) << \ - (EFUSE_SPI_PAD_CONFIG_HD_S)) -#define EFUSE_SPI_PAD_CONFIG_HD_V 0x1f -#define EFUSE_SPI_PAD_CONFIG_HD_S 4 - -/* EFUSE_CHIP_VER_DIS_CACHE : R/W ;bitpos:[3] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_CHIP_VER_DIS_CACHE (BIT(3)) -#define EFUSE_CHIP_VER_DIS_CACHE_M (BIT(3)) -#define EFUSE_CHIP_VER_DIS_CACHE_V 0x1 -#define EFUSE_CHIP_VER_DIS_CACHE_S 3 - -/* EFUSE_CHIP_VER_32PAD : R/W ;bitpos:[2] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_CHIP_VER_32PAD (BIT(2)) -#define EFUSE_CHIP_VER_32PAD_M (BIT(2)) -#define EFUSE_CHIP_VER_32PAD_V 0x1 -#define EFUSE_CHIP_VER_32PAD_S 2 - -/* EFUSE_CHIP_VER_DIS_BT : R/W ;bitpos:[1] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_CHIP_VER_DIS_BT (BIT(1)) -#define EFUSE_CHIP_VER_DIS_BT_M (BIT(1)) -#define EFUSE_CHIP_VER_DIS_BT_V 0x1 -#define EFUSE_CHIP_VER_DIS_BT_S 1 - -/* EFUSE_CHIP_VER_DIS_APP_CPU : R/W ;bitpos:[0] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_CHIP_VER_DIS_APP_CPU (BIT(0)) -#define EFUSE_CHIP_VER_DIS_APP_CPU_M (BIT(0)) -#define EFUSE_CHIP_VER_DIS_APP_CPU_V 0x1 -#define EFUSE_CHIP_VER_DIS_APP_CPU_S 0 - -#define EFUSE_BLK0_WDATA4_REG (DR_REG_EFUSE_BASE + 0x02c) - -/* EFUSE_SDIO_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; - * Description: program for sdio_force - */ - -#define EFUSE_SDIO_FORCE (BIT(16)) -#define EFUSE_SDIO_FORCE_M (BIT(16)) -#define EFUSE_SDIO_FORCE_V 0x1 -#define EFUSE_SDIO_FORCE_S 16 - -/* EFUSE_SDIO_TIEH : R/W ;bitpos:[15] ;default: 1'b0 ; - * Description: program for SDIO_TIEH - */ - -#define EFUSE_SDIO_TIEH (BIT(15)) -#define EFUSE_SDIO_TIEH_M (BIT(15)) -#define EFUSE_SDIO_TIEH_V 0x1 -#define EFUSE_SDIO_TIEH_S 15 - -/* EFUSE_XPD_SDIO_REG : R/W ;bitpos:[14] ;default: 1'b0 ; - * Description: program for XPD_SDIO_REG - */ - -#define EFUSE_XPD_SDIO_REG (BIT(14)) -#define EFUSE_XPD_SDIO_REG_M (BIT(14)) -#define EFUSE_XPD_SDIO_REG_V 0x1 -#define EFUSE_XPD_SDIO_REG_S 14 - -/* EFUSE_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; - * Description: True ADC reference voltage - */ - -#define EFUSE_ADC_VREF 0x0000001f -#define EFUSE_ADC_VREF_M ((EFUSE_ADC_VREF_V) << \ - (EFUSE_ADC_VREF_S)) -#define EFUSE_ADC_VREF_V 0x1f -#define EFUSE_ADC_VREF_S 8 - -/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. - * Newer versions of ESP32 come with EFUSE_ADC_VREF already burned, - * therefore SDIO_DREFH/M/L is only available in older versions of ESP32 - */ - -/* EFUSE_SDIO_DREFL : R/W ;bitpos:[13:12] ;default: 2'b0 ; - * Description: - */ - -#define EFUSE_SDIO_DREFL 0x00000003 -#define EFUSE_SDIO_DREFL_M ((EFUSE_SDIO_DREFL_V) << \ - (EFUSE_SDIO_DREFL_S)) -#define EFUSE_SDIO_DREFL_V 0x3 -#define EFUSE_SDIO_DREFL_S 12 - -/* EFUSE_SDIO_DREFM : R/W ;bitpos:[11:10] ;default: 2'b0 ; - * Description: - */ - -#define EFUSE_SDIO_DREFM 0x00000003 -#define EFUSE_SDIO_DREFM_M ((EFUSE_SDIO_DREFM_V) << \ - (EFUSE_SDIO_DREFM_S)) -#define EFUSE_SDIO_DREFM_V 0x3 -#define EFUSE_SDIO_DREFM_S 10 - -/* EFUSE_SDIO_DREFH : R/W ;bitpos:[9:8] ;default: 2'b0 ; - * Description: - */ - -#define EFUSE_SDIO_DREFH 0x00000003 -#define EFUSE_SDIO_DREFH_M ((EFUSE_SDIO_DREFH_V) << \ - (EFUSE_SDIO_DREFH_S)) -#define EFUSE_SDIO_DREFH_V 0x3 -#define EFUSE_SDIO_DREFH_S 8 - -/* EFUSE_CK8M_FREQ : R/W ;bitpos:[7:0] ;default: 8'b0 ; - * Description: - */ - -#define EFUSE_CK8M_FREQ 0x000000ff -#define EFUSE_CK8M_FREQ_M ((EFUSE_CK8M_FREQ_V) << \ - (EFUSE_CK8M_FREQ_S)) -#define EFUSE_CK8M_FREQ_V 0xff -#define EFUSE_CK8M_FREQ_S 0 - -#define EFUSE_BLK0_WDATA5_REG (DR_REG_EFUSE_BASE + 0x030) - -/* EFUSE_FLASH_CRYPT_CONFIG : R/W ;bitpos:[31:28] ;default: 4'b0 ; - * Description: program for flash_crypt_config - */ - -#define EFUSE_FLASH_CRYPT_CONFIG 0x0000000f -#define EFUSE_FLASH_CRYPT_CONFIG_M ((EFUSE_FLASH_CRYPT_CONFIG_V) << \ - (EFUSE_FLASH_CRYPT_CONFIG_S)) -#define EFUSE_FLASH_CRYPT_CONFIG_V 0xf -#define EFUSE_FLASH_CRYPT_CONFIG_S 28 - -/* EFUSE_DIG_VOL_L6: R/W; bitpos:[27:24]; - * Description: This field stores the difference between the digital - * regulator voltage at level6 and 1.2 V. (R/W) - * BIT[27] is the sign bit, 0: + , 1: - - * BIT[26:24] is the difference value, unit: 0.017V - * volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + - * BIT[26:24] * 0.017 - */ - -#define EFUSE_DIG_VOL_L6 0x0f -#define EFUSE_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V) << \ - (EFUSE_RD_DIG_VOL_L6_S)) -#define EFUSE_DIG_VOL_L6_V 0x0f -#define EFUSE_DIG_VOL_L6_S 24 - -/* EFUSE_VOL_LEVEL_HP_INV: R/W; bitpos:[23:22] - * Description: This field stores the voltage level for CPU to run at - * 240 MHz, or for flash/PSRAM to run at 80 MHz. - * 0x0: level 7; - * 0x1: level 6; - * 0x2: level 5; - * 0x3: level 4. (R/W) - */ - -#define EFUSE_VOL_LEVEL_HP_INV 0x03 -#define EFUSE_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V) << \ - (EFUSE_RD_VOL_LEVEL_HP_INV_S)) -#define EFUSE_VOL_LEVEL_HP_INV_V 0x03 -#define EFUSE_VOL_LEVEL_HP_INV_S 22 - -/* EFUSE_INST_CONFIG : R/W ;bitpos:[27:20] ;default: 8'b0 ; - * Deprecated - */ - -#define EFUSE_INST_CONFIG 0x000000ff /* Deprecated */ -#define EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V) << \ - (EFUSE_INST_CONFIG_S)) /* Deprecated */ -#define EFUSE_INST_CONFIG_V 0xff /* Deprecated */ -#define EFUSE_INST_CONFIG_S 20 /* Deprecated */ - -/* EFUSE_SPI_PAD_CONFIG_CS0 : R/W ;bitpos:[19:15] ;default: 5'b0 ; - * Description: program for SPI_pad_config_cs0 - */ - -#define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001f -#define EFUSE_SPI_PAD_CONFIG_CS0_M ((EFUSE_SPI_PAD_CONFIG_CS0_V) << \ - (EFUSE_SPI_PAD_CONFIG_CS0_S)) -#define EFUSE_SPI_PAD_CONFIG_CS0_V 0x1f -#define EFUSE_SPI_PAD_CONFIG_CS0_S 15 - -/* EFUSE_SPI_PAD_CONFIG_D : R/W ;bitpos:[14:10] ;default: 5'b0 ; - * Description: program for SPI_pad_config_d - */ - -#define EFUSE_SPI_PAD_CONFIG_D 0x0000001f -#define EFUSE_SPI_PAD_CONFIG_D_M ((EFUSE_SPI_PAD_CONFIG_D_V) << \ - (EFUSE_SPI_PAD_CONFIG_D_S)) -#define EFUSE_SPI_PAD_CONFIG_D_V 0x1f -#define EFUSE_SPI_PAD_CONFIG_D_S 10 - -/* EFUSE_SPI_PAD_CONFIG_Q : R/W ;bitpos:[9:5] ;default: 5'b0 ; - * Description: program for SPI_pad_config_q - */ - -#define EFUSE_SPI_PAD_CONFIG_Q 0x0000001f -#define EFUSE_SPI_PAD_CONFIG_Q_M ((EFUSE_SPI_PAD_CONFIG_Q_V) << \ - (EFUSE_SPI_PAD_CONFIG_Q_S)) -#define EFUSE_SPI_PAD_CONFIG_Q_V 0x1f -#define EFUSE_SPI_PAD_CONFIG_Q_S 5 - -/* EFUSE_SPI_PAD_CONFIG_CLK : R/W ;bitpos:[4:0] ;default: 5'b0 ; - * Description: program for SPI_pad_config_clk - */ - -#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000001f -#define EFUSE_SPI_PAD_CONFIG_CLK_M ((EFUSE_SPI_PAD_CONFIG_CLK_V) << \ - (EFUSE_SPI_PAD_CONFIG_CLK_S)) -#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x1f -#define EFUSE_SPI_PAD_CONFIG_CLK_S 0 - -#define EFUSE_BLK0_WDATA6_REG (DR_REG_EFUSE_BASE + 0x034) - -/* EFUSE_KEY_STATUS : R/W ;bitpos:[10] ;default: 1'b0 ; - * Description: program for key_status - */ - -#define EFUSE_KEY_STATUS (BIT(10)) -#define EFUSE_KEY_STATUS_M (BIT(10)) -#define EFUSE_KEY_STATUS_V 0x1 -#define EFUSE_KEY_STATUS_S 10 - -/* EFUSE_DISABLE_DL_CACHE : R/W ;bitpos:[9] ;default: 1'b0 ; - * Description: program for download_dis_cache - */ - -#define EFUSE_DISABLE_DL_CACHE (BIT(9)) -#define EFUSE_DISABLE_DL_CACHE_M (BIT(9)) -#define EFUSE_DISABLE_DL_CACHE_V 0x1 -#define EFUSE_DISABLE_DL_CACHE_S 9 - -/* EFUSE_DISABLE_DL_DECRYPT : R/W ;bitpos:[8] ;default: 1'b0 ; - * Description: program for download_dis_decrypt - */ - -#define EFUSE_DISABLE_DL_DECRYPT (BIT(8)) -#define EFUSE_DISABLE_DL_DECRYPT_M (BIT(8)) -#define EFUSE_DISABLE_DL_DECRYPT_V 0x1 -#define EFUSE_DISABLE_DL_DECRYPT_S 8 - -/* EFUSE_DISABLE_DL_ENCRYPT : R/W ;bitpos:[7] ;default: 1'b0 ; - * Description: program for download_dis_encrypt - */ - -#define EFUSE_DISABLE_DL_ENCRYPT (BIT(7)) -#define EFUSE_DISABLE_DL_ENCRYPT_M (BIT(7)) -#define EFUSE_DISABLE_DL_ENCRYPT_V 0x1 -#define EFUSE_DISABLE_DL_ENCRYPT_S 7 - -/* EFUSE_DISABLE_JTAG : R/W ;bitpos:[6] ;default: 1'b0 ; - * Description: program for JTAG_disable - */ - -#define EFUSE_DISABLE_JTAG (BIT(6)) -#define EFUSE_DISABLE_JTAG_M (BIT(6)) -#define EFUSE_DISABLE_JTAG_V 0x1 -#define EFUSE_DISABLE_JTAG_S 6 - -/* EFUSE_ABS_DONE_1 : R/W ;bitpos:[5] ;default: 1'b0 ; - * Description: program for abstract_done_1 - */ - -#define EFUSE_ABS_DONE_1 (BIT(5)) -#define EFUSE_ABS_DONE_1_M (BIT(5)) -#define EFUSE_ABS_DONE_1_V 0x1 -#define EFUSE_ABS_DONE_1_S 5 - -/* EFUSE_ABS_DONE_0 : R/W ;bitpos:[4] ;default: 1'b0 ; - * Description: program for abstract_done_0 - */ - -#define EFUSE_ABS_DONE_0 (BIT(4)) -#define EFUSE_ABS_DONE_0_M (BIT(4)) -#define EFUSE_ABS_DONE_0_V 0x1 -#define EFUSE_ABS_DONE_0_S 4 - -/* EFUSE_DISABLE_SDIO_HOST : R/W ;bitpos:[3] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_DISABLE_SDIO_HOST (BIT(3)) -#define EFUSE_DISABLE_SDIO_HOST_M (BIT(3)) -#define EFUSE_DISABLE_SDIO_HOST_V 0x1 -#define EFUSE_DISABLE_SDIO_HOST_S 3 - -/* EFUSE_CONSOLE_DEBUG_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; - * Description: program for console_debug_disable - */ - -#define EFUSE_CONSOLE_DEBUG_DISABLE (BIT(2)) -#define EFUSE_CONSOLE_DEBUG_DISABLE_M (BIT(2)) -#define EFUSE_CONSOLE_DEBUG_DISABLE_V 0x1 -#define EFUSE_CONSOLE_DEBUG_DISABLE_S 2 - -/* EFUSE_CODING_SCHEME : R/W ;bitpos:[1:0] ;default: 2'b0 ; - * Description: program for coding_scheme - */ - -#define EFUSE_CODING_SCHEME 0x00000003 -#define EFUSE_CODING_SCHEME_M ((EFUSE_CODING_SCHEME_V) << \ - (EFUSE_CODING_SCHEME_S)) -#define EFUSE_CODING_SCHEME_V 0x3 -#define EFUSE_CODING_SCHEME_S 0 - -#define EFUSE_BLK1_RDATA0_REG (DR_REG_EFUSE_BASE + 0x038) - -/* EFUSE_BLK1_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK1 - */ - -#define EFUSE_BLK1_DOUT0 0xffffffff -#define EFUSE_BLK1_DOUT0_M ((EFUSE_BLK1_DOUT0_V) << \ - (EFUSE_BLK1_DOUT0_S)) -#define EFUSE_BLK1_DOUT0_V 0xffffffff -#define EFUSE_BLK1_DOUT0_S 0 - -#define EFUSE_BLK1_RDATA1_REG (DR_REG_EFUSE_BASE + 0x03c) - -/* EFUSE_BLK1_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK1 - */ - -#define EFUSE_BLK1_DOUT1 0xffffffff -#define EFUSE_BLK1_DOUT1_M ((EFUSE_BLK1_DOUT1_V) << \ - (EFUSE_BLK1_DOUT1_S)) -#define EFUSE_BLK1_DOUT1_V 0xffffffff -#define EFUSE_BLK1_DOUT1_S 0 - -#define EFUSE_BLK1_RDATA2_REG (DR_REG_EFUSE_BASE + 0x040) - -/* EFUSE_BLK1_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK1 - */ - -#define EFUSE_BLK1_DOUT2 0xffffffff -#define EFUSE_BLK1_DOUT2_M ((EFUSE_BLK1_DOUT2_V) << \ - (EFUSE_BLK1_DOUT2_S)) -#define EFUSE_BLK1_DOUT2_V 0xffffffff -#define EFUSE_BLK1_DOUT2_S 0 - -#define EFUSE_BLK1_RDATA3_REG (DR_REG_EFUSE_BASE + 0x044) - -/* EFUSE_BLK1_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK1 - */ - -#define EFUSE_BLK1_DOUT3 0xffffffff -#define EFUSE_BLK1_DOUT3_M ((EFUSE_BLK1_DOUT3_V) << \ - (EFUSE_BLK1_DOUT3_S)) -#define EFUSE_BLK1_DOUT3_V 0xffffffff -#define EFUSE_BLK1_DOUT3_S 0 - -#define EFUSE_BLK1_RDATA4_REG (DR_REG_EFUSE_BASE + 0x048) - -/* EFUSE_BLK1_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK1 - */ - -#define EFUSE_BLK1_DOUT4 0xffffffff -#define EFUSE_BLK1_DOUT4_M ((EFUSE_BLK1_DOUT4_V) << \ - (EFUSE_BLK1_DOUT4_S)) -#define EFUSE_BLK1_DOUT4_V 0xffffffff -#define EFUSE_BLK1_DOUT4_S 0 - -#define EFUSE_BLK1_RDATA5_REG (DR_REG_EFUSE_BASE + 0x04c) - -/* EFUSE_BLK1_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK1 - */ - -#define EFUSE_BLK1_DOUT5 0xffffffff -#define EFUSE_BLK1_DOUT5_M ((EFUSE_BLK1_DOUT5_V) << \ - (EFUSE_BLK1_DOUT5_S)) -#define EFUSE_BLK1_DOUT5_V 0xffffffff -#define EFUSE_BLK1_DOUT5_S 0 - -#define EFUSE_BLK1_RDATA6_REG (DR_REG_EFUSE_BASE + 0x050) - -/* EFUSE_BLK1_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK1 - */ - -#define EFUSE_BLK1_DOUT6 0xffffffff -#define EFUSE_BLK1_DOUT6_M ((EFUSE_BLK1_DOUT6_V) << \ - (EFUSE_BLK1_DOUT6_S)) -#define EFUSE_BLK1_DOUT6_V 0xffffffff -#define EFUSE_BLK1_DOUT6_S 0 - -#define EFUSE_BLK1_RDATA7_REG (DR_REG_EFUSE_BASE + 0x054) - -/* EFUSE_BLK1_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK1 - */ - -#define EFUSE_BLK1_DOUT7 0xffffffff -#define EFUSE_BLK1_DOUT7_M ((EFUSE_BLK1_DOUT7_V) << \ - (EFUSE_BLK1_DOUT7_S)) -#define EFUSE_BLK1_DOUT7_V 0xffffffff -#define EFUSE_BLK1_DOUT7_S 0 - -#define EFUSE_BLK2_RDATA0_REG (DR_REG_EFUSE_BASE + 0x058) - -/* EFUSE_BLK2_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK2 - */ - -#define EFUSE_BLK2_DOUT0 0xffffffff -#define EFUSE_BLK2_DOUT0_M ((EFUSE_BLK2_DOUT0_V) << \ - (EFUSE_BLK2_DOUT0_S)) -#define EFUSE_BLK2_DOUT0_V 0xffffffff -#define EFUSE_BLK2_DOUT0_S 0 - -#define EFUSE_BLK2_RDATA1_REG (DR_REG_EFUSE_BASE + 0x05c) - -/* EFUSE_BLK2_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK2 - */ - -#define EFUSE_BLK2_DOUT1 0xffffffff -#define EFUSE_BLK2_DOUT1_M ((EFUSE_BLK2_DOUT1_V) << \ - (EFUSE_BLK2_DOUT1_S)) -#define EFUSE_BLK2_DOUT1_V 0xffffffff -#define EFUSE_BLK2_DOUT1_S 0 - -#define EFUSE_BLK2_RDATA2_REG (DR_REG_EFUSE_BASE + 0x060) - -/* EFUSE_BLK2_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK2 - */ - -#define EFUSE_BLK2_DOUT2 0xffffffff -#define EFUSE_BLK2_DOUT2_M ((EFUSE_BLK2_DOUT2_V) << \ - (EFUSE_BLK2_DOUT2_S)) -#define EFUSE_BLK2_DOUT2_V 0xffffffff -#define EFUSE_BLK2_DOUT2_S 0 - -#define EFUSE_BLK2_RDATA3_REG (DR_REG_EFUSE_BASE + 0x064) - -/* EFUSE_BLK2_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK2 - */ - -#define EFUSE_BLK2_DOUT3 0xffffffff -#define EFUSE_BLK2_DOUT3_M ((EFUSE_BLK2_DOUT3_V) << \ - (EFUSE_BLK2_DOUT3_S)) -#define EFUSE_BLK2_DOUT3_V 0xffffffff -#define EFUSE_BLK2_DOUT3_S 0 - -#define EFUSE_BLK2_RDATA4_REG (DR_REG_EFUSE_BASE + 0x068) - -/* EFUSE_BLK2_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK2 - */ - -#define EFUSE_BLK2_DOUT4 0xffffffff -#define EFUSE_BLK2_DOUT4_M ((EFUSE_BLK2_DOUT4_V) << \ - (EFUSE_BLK2_DOUT4_S)) -#define EFUSE_BLK2_DOUT4_V 0xffffffff -#define EFUSE_BLK2_DOUT4_S 0 - -#define EFUSE_BLK2_RDATA5_REG (DR_REG_EFUSE_BASE + 0x06c) - -/* EFUSE_BLK2_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK2 - */ - -#define EFUSE_BLK2_DOUT5 0xffffffff -#define EFUSE_BLK2_DOUT5_M ((EFUSE_BLK2_DOUT5_V) << \ - (EFUSE_BLK2_DOUT5_S)) -#define EFUSE_BLK2_DOUT5_V 0xffffffff -#define EFUSE_BLK2_DOUT5_S 0 - -#define EFUSE_BLK2_RDATA6_REG (DR_REG_EFUSE_BASE + 0x070) - -/* EFUSE_BLK2_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK2 - */ - -#define EFUSE_BLK2_DOUT6 0xffffffff -#define EFUSE_BLK2_DOUT6_M ((EFUSE_BLK2_DOUT6_V) << \ - (EFUSE_BLK2_DOUT6_S)) -#define EFUSE_BLK2_DOUT6_V 0xffffffff -#define EFUSE_BLK2_DOUT6_S 0 - -#define EFUSE_BLK2_RDATA7_REG (DR_REG_EFUSE_BASE + 0x074) - -/* EFUSE_BLK2_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK2 - */ - -#define EFUSE_BLK2_DOUT7 0xffffffff -#define EFUSE_BLK2_DOUT7_M ((EFUSE_BLK2_DOUT7_V) << \ - (EFUSE_BLK2_DOUT7_S)) -#define EFUSE_BLK2_DOUT7_V 0xffffffff -#define EFUSE_BLK2_DOUT7_S 0 - -#define EFUSE_BLK3_RDATA0_REG (DR_REG_EFUSE_BASE + 0x078) - -/* EFUSE_BLK3_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK3 - */ - -#define EFUSE_BLK3_DOUT0 0xffffffff -#define EFUSE_BLK3_DOUT0_M ((EFUSE_BLK3_DOUT0_V) << \ - (EFUSE_BLK3_DOUT0_S)) -#define EFUSE_BLK3_DOUT0_V 0xffffffff -#define EFUSE_BLK3_DOUT0_S 0 - -#define EFUSE_BLK3_RDATA1_REG (DR_REG_EFUSE_BASE + 0x07c) - -/* EFUSE_BLK3_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK3 - */ - -#define EFUSE_BLK3_DOUT1 0xffffffff -#define EFUSE_BLK3_DOUT1_M ((EFUSE_BLK3_DOUT1_V) << \ - (EFUSE_BLK3_DOUT1_S)) -#define EFUSE_BLK3_DOUT1_V 0xffffffff -#define EFUSE_BLK3_DOUT1_S 0 - -#define EFUSE_BLK3_RDATA2_REG (DR_REG_EFUSE_BASE + 0x080) - -/* EFUSE_BLK3_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK3 - */ - -#define EFUSE_BLK3_DOUT2 0xffffffff -#define EFUSE_BLK3_DOUT2_M ((EFUSE_BLK3_DOUT2_V) << \ - (EFUSE_BLK3_DOUT2_S)) -#define EFUSE_BLK3_DOUT2_V 0xffffffff -#define EFUSE_BLK3_DOUT2_S 0 - -/* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for - * calibration purposes. This usage is indicated by the - * EFUSE_RD_BLK3_PART_RESERVE bit. - */ - -#define EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x084) - -/* EFUSE_BLK3_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK3 - */ - -#define EFUSE_BLK3_DOUT3 0xffffffff -#define EFUSE_BLK3_DOUT3_M ((EFUSE_BLK3_DOUT3_V) << \ - (EFUSE_BLK3_DOUT3_S)) -#define EFUSE_BLK3_DOUT3_V 0xffffffff -#define EFUSE_BLK3_DOUT3_S 0 - -/* EFUSE_RD_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; - * Description: ADC2 Two Point calibration high point. Only valid if - * EFUSE_RD_BLK3_PART_RESERVE - */ - -#define EFUSE_RD_ADC2_TP_HIGH 0x1ff -#define EFUSE_RD_ADC2_TP_HIGH_M ((EFUSE_RD_ADC2_TP_HIGH_V) << \ - (EFUSE_RD_ADC2_TP_HIGH_S)) -#define EFUSE_RD_ADC2_TP_HIGH_V 0x1ff -#define EFUSE_RD_ADC2_TP_HIGH_S 23 - -/* EFUSE_RD_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; - * Description: ADC2 Two Point calibration low point. Only valid if - * EFUSE_RD_BLK3_PART_RESERVE - */ - -#define EFUSE_RD_ADC2_TP_LOW 0x7f -#define EFUSE_RD_ADC2_TP_LOW_M ((EFUSE_RD_ADC2_TP_LOW_V) << \ - (EFUSE_RD_ADC2_TP_LOW_S)) -#define EFUSE_RD_ADC2_TP_LOW_V 0x7f -#define EFUSE_RD_ADC2_TP_LOW_S 16 - -/* EFUSE_RD_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; - * Description: ADC1 Two Point calibration high point. Only valid if - * EFUSE_RD_BLK3_PART_RESERVE - */ - -#define EFUSE_RD_ADC1_TP_HIGH 0x1ff -#define EFUSE_RD_ADC1_TP_HIGH_M ((EFUSE_RD_ADC1_TP_HIGH_V) << \ - (EFUSE_RD_ADC1_TP_HIGH_S)) -#define EFUSE_RD_ADC1_TP_HIGH_V 0x1ff -#define EFUSE_RD_ADC1_TP_HIGH_S 7 - -/* EFUSE_RD_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; - * Description: ADC1 Two Point calibration low point. Only valid if - * EFUSE_RD_BLK3_PART_RESERVE - */ - -#define EFUSE_RD_ADC1_TP_LOW 0x7f -#define EFUSE_RD_ADC1_TP_LOW_M ((EFUSE_RD_ADC1_TP_LOW_V) << \ - (EFUSE_RD_ADC1_TP_LOW_S)) -#define EFUSE_RD_ADC1_TP_LOW_V 0x7f -#define EFUSE_RD_ADC1_TP_LOW_S 0 - -#define EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x088) - -/* EFUSE_BLK3_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK3 - */ - -#define EFUSE_BLK3_DOUT4 0xffffffff -#define EFUSE_BLK3_DOUT4_M ((EFUSE_BLK3_DOUT4_V) << \ - (EFUSE_BLK3_DOUT4_S)) -#define EFUSE_BLK3_DOUT4_V 0xffffffff -#define EFUSE_BLK3_DOUT4_S 0 - -/* EFUSE_RD_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; - * Description: Reserved for future calibration use. Indicated by - * EFUSE_RD_BLK3_PART_RESERVE - */ - -#define EFUSE_RD_CAL_RESERVED 0x0000ffff -#define EFUSE_RD_CAL_RESERVED_M ((EFUSE_RD_CAL_RESERVED_V) << \ - (EFUSE_RD_CAL_RESERVED_S)) -#define EFUSE_RD_CAL_RESERVED_V 0xffff -#define EFUSE_RD_CAL_RESERVED_S 0 - -#define EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x08c) - -/* EFUSE_BLK3_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK3 - */ - -#define EFUSE_BLK3_DOUT5 0xffffffff -#define EFUSE_BLK3_DOUT5_M ((EFUSE_BLK3_DOUT5_V) << \ - (EFUSE_BLK3_DOUT5_S)) -#define EFUSE_BLK3_DOUT5_V 0xffffffff -#define EFUSE_BLK3_DOUT5_S 0 - -#define EFUSE_BLK3_RDATA6_REG (DR_REG_EFUSE_BASE + 0x090) - -/* EFUSE_BLK3_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK3 - */ - -#define EFUSE_BLK3_DOUT6 0xffffffff -#define EFUSE_BLK3_DOUT6_M ((EFUSE_BLK3_DOUT6_V) << (EFUSE_BLK3_DOUT6_S)) -#define EFUSE_BLK3_DOUT6_V 0xffffffff -#define EFUSE_BLK3_DOUT6_S 0 - -#define EFUSE_BLK3_RDATA7_REG (DR_REG_EFUSE_BASE + 0x094) - -/* EFUSE_BLK3_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: read for BLOCK3 - */ - -#define EFUSE_BLK3_DOUT7 0xffffffff -#define EFUSE_BLK3_DOUT7_M ((EFUSE_BLK3_DOUT7_V) << \ - (EFUSE_BLK3_DOUT7_S)) -#define EFUSE_BLK3_DOUT7_V 0xffffffff -#define EFUSE_BLK3_DOUT7_S 0 - -#define EFUSE_BLK1_WDATA0_REG (DR_REG_EFUSE_BASE + 0x098) - -/* EFUSE_BLK1_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK1 - */ - -#define EFUSE_BLK1_DIN0 0xffffffff -#define EFUSE_BLK1_DIN0_M ((EFUSE_BLK1_DIN0_V) << \ - (EFUSE_BLK1_DIN0_S)) -#define EFUSE_BLK1_DIN0_V 0xffffffff -#define EFUSE_BLK1_DIN0_S 0 - -#define EFUSE_BLK1_WDATA1_REG (DR_REG_EFUSE_BASE + 0x09c) - -/* EFUSE_BLK1_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK1 - */ - -#define EFUSE_BLK1_DIN1 0xffffffff -#define EFUSE_BLK1_DIN1_M ((EFUSE_BLK1_DIN1_V) << \ - (EFUSE_BLK1_DIN1_S)) -#define EFUSE_BLK1_DIN1_V 0xffffffff -#define EFUSE_BLK1_DIN1_S 0 - -#define EFUSE_BLK1_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0a0) - -/* EFUSE_BLK1_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK1 - */ - -#define EFUSE_BLK1_DIN2 0xffffffff -#define EFUSE_BLK1_DIN2_M ((EFUSE_BLK1_DIN2_V) << \ - (EFUSE_BLK1_DIN2_S)) -#define EFUSE_BLK1_DIN2_V 0xffffffff -#define EFUSE_BLK1_DIN2_S 0 - -#define EFUSE_BLK1_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0a4) - -/* EFUSE_BLK1_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK1 - */ - -#define EFUSE_BLK1_DIN3 0xffffffff -#define EFUSE_BLK1_DIN3_M ((EFUSE_BLK1_DIN3_V) << \ - (EFUSE_BLK1_DIN3_S)) -#define EFUSE_BLK1_DIN3_V 0xffffffff -#define EFUSE_BLK1_DIN3_S 0 - -#define EFUSE_BLK1_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0a8) - -/* EFUSE_BLK1_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK1 - */ - -#define EFUSE_BLK1_DIN4 0xffffffff -#define EFUSE_BLK1_DIN4_M ((EFUSE_BLK1_DIN4_V) << \ - (EFUSE_BLK1_DIN4_S)) -#define EFUSE_BLK1_DIN4_V 0xffffffff -#define EFUSE_BLK1_DIN4_S 0 - -#define EFUSE_BLK1_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ac) - -/* EFUSE_BLK1_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK1 - */ - -#define EFUSE_BLK1_DIN5 0xffffffff -#define EFUSE_BLK1_DIN5_M ((EFUSE_BLK1_DIN5_V) << \ - (EFUSE_BLK1_DIN5_S)) -#define EFUSE_BLK1_DIN5_V 0xffffffff -#define EFUSE_BLK1_DIN5_S 0 - -#define EFUSE_BLK1_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0b0) - -/* EFUSE_BLK1_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK1 - */ - -#define EFUSE_BLK1_DIN6 0xffffffff -#define EFUSE_BLK1_DIN6_M ((EFUSE_BLK1_DIN6_V) << \ - (EFUSE_BLK1_DIN6_S)) -#define EFUSE_BLK1_DIN6_V 0xffffffff -#define EFUSE_BLK1_DIN6_S 0 - -#define EFUSE_BLK1_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0b4) - -/* EFUSE_BLK1_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK1 - */ - -#define EFUSE_BLK1_DIN7 0xffffffff -#define EFUSE_BLK1_DIN7_M ((EFUSE_BLK1_DIN7_V) << \ - (EFUSE_BLK1_DIN7_S)) -#define EFUSE_BLK1_DIN7_V 0xffffffff -#define EFUSE_BLK1_DIN7_S 0 - -#define EFUSE_BLK2_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0b8) - -/* EFUSE_BLK2_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK2 - */ - -#define EFUSE_BLK2_DIN0 0xffffffff -#define EFUSE_BLK2_DIN0_M ((EFUSE_BLK2_DIN0_V) << \ - (EFUSE_BLK2_DIN0_S)) -#define EFUSE_BLK2_DIN0_V 0xffffffff -#define EFUSE_BLK2_DIN0_S 0 - -#define EFUSE_BLK2_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0bc) - -/* EFUSE_BLK2_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK2 - */ - -#define EFUSE_BLK2_DIN1 0xffffffff -#define EFUSE_BLK2_DIN1_M ((EFUSE_BLK2_DIN1_V) << \ - (EFUSE_BLK2_DIN1_S)) -#define EFUSE_BLK2_DIN1_V 0xffffffff -#define EFUSE_BLK2_DIN1_S 0 - -#define EFUSE_BLK2_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0c0) - -/* EFUSE_BLK2_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK2 - */ - -#define EFUSE_BLK2_DIN2 0xffffffff -#define EFUSE_BLK2_DIN2_M ((EFUSE_BLK2_DIN2_V) << \ - (EFUSE_BLK2_DIN2_S)) -#define EFUSE_BLK2_DIN2_V 0xffffffff -#define EFUSE_BLK2_DIN2_S 0 - -#define EFUSE_BLK2_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0c4) - -/* EFUSE_BLK2_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK2 - */ - -#define EFUSE_BLK2_DIN3 0xffffffff -#define EFUSE_BLK2_DIN3_M ((EFUSE_BLK2_DIN3_V) << \ - (EFUSE_BLK2_DIN3_S)) -#define EFUSE_BLK2_DIN3_V 0xffffffff -#define EFUSE_BLK2_DIN3_S 0 - -#define EFUSE_BLK2_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0c8) - -/* EFUSE_BLK2_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK2 - */ - -#define EFUSE_BLK2_DIN4 0xffffffff -#define EFUSE_BLK2_DIN4_M ((EFUSE_BLK2_DIN4_V) << \ - (EFUSE_BLK2_DIN4_S)) -#define EFUSE_BLK2_DIN4_V 0xffffffff -#define EFUSE_BLK2_DIN4_S 0 - -#define EFUSE_BLK2_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0cc) - -/* EFUSE_BLK2_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK2 - */ - -#define EFUSE_BLK2_DIN5 0xffffffff -#define EFUSE_BLK2_DIN5_M ((EFUSE_BLK2_DIN5_V) << \ - (EFUSE_BLK2_DIN5_S)) -#define EFUSE_BLK2_DIN5_V 0xffffffff -#define EFUSE_BLK2_DIN5_S 0 - -#define EFUSE_BLK2_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0d0) - -/* EFUSE_BLK2_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK2 - */ - -#define EFUSE_BLK2_DIN6 0xffffffff -#define EFUSE_BLK2_DIN6_M ((EFUSE_BLK2_DIN6_V) << \ - (EFUSE_BLK2_DIN6_S)) -#define EFUSE_BLK2_DIN6_V 0xffffffff -#define EFUSE_BLK2_DIN6_S 0 - -#define EFUSE_BLK2_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0d4) - -/* EFUSE_BLK2_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK2 - */ - -#define EFUSE_BLK2_DIN7 0xffffffff -#define EFUSE_BLK2_DIN7_M ((EFUSE_BLK2_DIN7_V) << \ - (EFUSE_BLK2_DIN7_S)) -#define EFUSE_BLK2_DIN7_V 0xffffffff -#define EFUSE_BLK2_DIN7_S 0 - -#define EFUSE_BLK3_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0d8) - -/* EFUSE_BLK3_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK3 - */ - -#define EFUSE_BLK3_DIN0 0xffffffff -#define EFUSE_BLK3_DIN0_M ((EFUSE_BLK3_DIN0_V) << \ - (EFUSE_BLK3_DIN0_S)) -#define EFUSE_BLK3_DIN0_V 0xffffffff -#define EFUSE_BLK3_DIN0_S 0 - -#define EFUSE_BLK3_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0dc) - -/* EFUSE_BLK3_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK3 - */ - -#define EFUSE_BLK3_DIN1 0xffffffff -#define EFUSE_BLK3_DIN1_M ((EFUSE_BLK3_DIN1_V) << \ - (EFUSE_BLK3_DIN1_S)) -#define EFUSE_BLK3_DIN1_V 0xffffffff -#define EFUSE_BLK3_DIN1_S 0 - -#define EFUSE_BLK3_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0e0) - -/* EFUSE_BLK3_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK3 - */ - -#define EFUSE_BLK3_DIN2 0xffffffff -#define EFUSE_BLK3_DIN2_M ((EFUSE_BLK3_DIN2_V) << \ - (EFUSE_BLK3_DIN2_S)) -#define EFUSE_BLK3_DIN2_V 0xffffffff -#define EFUSE_BLK3_DIN2_S 0 - -/* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for - * calibration purposes. This usage is indicated by the - * EFUSE_RD_BLK3_PART_RESERVE bit. - */ - -#define EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0e4) - -/* EFUSE_BLK3_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK3 - */ - -#define EFUSE_BLK3_DIN3 0xffffffff -#define EFUSE_BLK3_DIN3_M ((EFUSE_BLK3_DIN3_V) << \ - (EFUSE_BLK3_DIN3_S)) -#define EFUSE_BLK3_DIN3_V 0xffffffff -#define EFUSE_BLK3_DIN3_S 0 - -/* EFUSE_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; - * Description: ADC2 Two Point calibration high point. Only valid if - * EFUSE_RD_BLK3_PART_RESERVE - */ - -#define EFUSE_ADC2_TP_HIGH 0x1ff -#define EFUSE_ADC2_TP_HIGH_M ((EFUSE_ADC2_TP_HIGH_V) << \ - (EFUSE_ADC2_TP_HIGH_S)) -#define EFUSE_ADC2_TP_HIGH_V 0x1ff -#define EFUSE_ADC2_TP_HIGH_S 23 - -/* EFUSE_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; - * Description: ADC2 Two Point calibration low point. Only valid if - * EFUSE_RD_BLK3_PART_RESERVE - */ - -#define EFUSE_ADC2_TP_LOW 0x7f -#define EFUSE_ADC2_TP_LOW_M ((EFUSE_ADC2_TP_LOW_V) << \ - (EFUSE_ADC2_TP_LOW_S)) -#define EFUSE_ADC2_TP_LOW_V 0x7f -#define EFUSE_ADC2_TP_LOW_S 16 - -/* EFUSE_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; - * Description: ADC1 Two Point calibration high point. Only valid if - * EFUSE_RD_BLK3_PART_RESERVE - */ - -#define EFUSE_ADC1_TP_HIGH 0x1ff -#define EFUSE_ADC1_TP_HIGH_M ((EFUSE_ADC1_TP_HIGH_V) << \ - (EFUSE_ADC1_TP_HIGH_S)) -#define EFUSE_ADC1_TP_HIGH_V 0x1ff -#define EFUSE_ADC1_TP_HIGH_S 7 - -/* EFUSE_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; - * Description: ADC1 Two Point calibration low point. Only valid if - * EFUSE_RD_BLK3_PART_RESERVE - */ - -#define EFUSE_ADC1_TP_LOW 0x7f -#define EFUSE_ADC1_TP_LOW_M ((EFUSE_ADC1_TP_LOW_V) << \ - (EFUSE_ADC1_TP_LOW_S)) -#define EFUSE_ADC1_TP_LOW_V 0x7f -#define EFUSE_ADC1_TP_LOW_S 0 - -#define EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0e8) - -/* EFUSE_BLK3_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK3 - */ - -#define EFUSE_BLK3_DIN4 0xffffffff -#define EFUSE_BLK3_DIN4_M ((EFUSE_BLK3_DIN4_V) << \ - (EFUSE_BLK3_DIN4_S)) -#define EFUSE_BLK3_DIN4_V 0xffffffff -#define EFUSE_BLK3_DIN4_S 0 - -/* EFUSE_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; - * Description: Reserved for future calibration use. Indicated by - * EFUSE_BLK3_PART_RESERVE - */ - -#define EFUSE_CAL_RESERVED 0x0000ffff -#define EFUSE_CAL_RESERVED_M ((EFUSE_CAL_RESERVED_V) << \ - (EFUSE_CAL_RESERVED_S)) -#define EFUSE_CAL_RESERVED_V 0xffff -#define EFUSE_CAL_RESERVED_S 0 - -#define EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ec) - -/* EFUSE_BLK3_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK3 - */ - -#define EFUSE_BLK3_DIN5 0xffffffff -#define EFUSE_BLK3_DIN5_M ((EFUSE_BLK3_DIN5_V) << \ - (EFUSE_BLK3_DIN5_S)) -#define EFUSE_BLK3_DIN5_V 0xffffffff -#define EFUSE_BLK3_DIN5_S 0 - -#define EFUSE_BLK3_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0f0) - -/* EFUSE_BLK3_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK3 - */ - -#define EFUSE_BLK3_DIN6 0xffffffff -#define EFUSE_BLK3_DIN6_M ((EFUSE_BLK3_DIN6_V) << \ - (EFUSE_BLK3_DIN6_S)) -#define EFUSE_BLK3_DIN6_V 0xffffffff -#define EFUSE_BLK3_DIN6_S 0 - -#define EFUSE_BLK3_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0f4) - -/* EFUSE_BLK3_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; - * Description: program for BLOCK3 - */ - -#define EFUSE_BLK3_DIN7 0xffffffff -#define EFUSE_BLK3_DIN7_M ((EFUSE_BLK3_DIN7_V) << \ - (EFUSE_BLK3_DIN7_S)) -#define EFUSE_BLK3_DIN7_V 0xffffffff -#define EFUSE_BLK3_DIN7_S 0 - -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x0f8) - -/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (BIT(16)) -#define EFUSE_CLK_EN_V 0x1 -#define EFUSE_CLK_EN_S 16 - -/* EFUSE_CLK_SEL1 : R/W ;bitpos:[15:8] ;default: 8'h40 ; - * Description: efuse timing configure - */ - -#define EFUSE_CLK_SEL1 0x000000ff -#define EFUSE_CLK_SEL1_M ((EFUSE_CLK_SEL1_V) << \ - (EFUSE_CLK_SEL1_S)) -#define EFUSE_CLK_SEL1_V 0xff -#define EFUSE_CLK_SEL1_S 8 - -/* EFUSE_CLK_SEL0 : R/W ;bitpos:[7:0] ;default: 8'h52 ; - * Description: efuse timing configure - */ - -#define EFUSE_CLK_SEL0 0x000000ff -#define EFUSE_CLK_SEL0_M ((EFUSE_CLK_SEL0_V) << \ - (EFUSE_CLK_SEL0_S)) -#define EFUSE_CLK_SEL0_V 0xff -#define EFUSE_CLK_SEL0_S 0 - -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x0fc) - -/* EFUSE_FORCE_NO_WR_RD_DIS : R/W ;bitpos:[16] ;default: 1'h1 ; - * Description: - */ - -#define EFUSE_FORCE_NO_WR_RD_DIS (BIT(16)) -#define EFUSE_FORCE_NO_WR_RD_DIS_M (BIT(16)) -#define EFUSE_FORCE_NO_WR_RD_DIS_V 0x1 -#define EFUSE_FORCE_NO_WR_RD_DIS_S 16 - -/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; - * Description: efuse operation code - */ - -#define EFUSE_OP_CODE 0x0000ffff -#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V) << \ - (EFUSE_OP_CODE_S)) -#define EFUSE_OP_CODE_V 0xffff -#define EFUSE_OP_CODE_S 0 - -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x100) - -/* EFUSE_DEBUG : RO ;bitpos:[31:0] ;default: 32'h0 ; - * Description: - */ - -#define EFUSE_DEBUG 0xffffffff -#define EFUSE_DEBUG_M ((EFUSE_DEBUG_V) << \ - (EFUSE_DEBUG_S)) -#define EFUSE_DEBUG_V 0xffffffff -#define EFUSE_DEBUG_S 0 - -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x104) - -/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; - * Description: command for program - */ - -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (BIT(1)) -#define EFUSE_PGM_CMD_V 0x1 -#define EFUSE_PGM_CMD_S 1 - -/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; - * Description: command for read - */ - -#define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (BIT(0)) -#define EFUSE_READ_CMD_V 0x1 -#define EFUSE_READ_CMD_S 0 - -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x108) - -/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; - * Description: program done interrupt raw status - */ - -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_V 0x1 -#define EFUSE_PGM_DONE_INT_RAW_S 1 - -/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; - * Description: read done interrupt raw status - */ - -#define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_V 0x1 -#define EFUSE_READ_DONE_INT_RAW_S 0 - -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x10c) - -/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; - * Description: program done interrupt status - */ - -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_V 0x1 -#define EFUSE_PGM_DONE_INT_ST_S 1 - -/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; - * Description: read done interrupt status - */ - -#define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_V 0x1 -#define EFUSE_READ_DONE_INT_ST_S 0 - -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x110) - -/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; - * Description: program done interrupt enable - */ - -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_V 0x1 -#define EFUSE_PGM_DONE_INT_ENA_S 1 - -/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; - * Description: read done interrupt enable - */ - -#define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_V 0x1 -#define EFUSE_READ_DONE_INT_ENA_S 0 - -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x114) - -/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; - * Description: program done interrupt clear - */ - -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_V 0x1 -#define EFUSE_PGM_DONE_INT_CLR_S 1 - -/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; - * Description: read done interrupt clear - */ - -#define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_V 0x1 -#define EFUSE_READ_DONE_INT_CLR_S 0 - -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x118) - -/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; - * Description: - */ - -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x1 -#define EFUSE_DAC_CLK_PAD_SEL_S 8 - -/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd40 ; - * Description: efuse timing configure - */ - -#define EFUSE_DAC_CLK_DIV 0x000000ff -#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V) << \ - (EFUSE_DAC_CLK_DIV_S)) -#define EFUSE_DAC_CLK_DIV_V 0xff -#define EFUSE_DAC_CLK_DIV_S 0 - -#define EFUSE_DEC_STATUS_REG (DR_REG_EFUSE_BASE + 0x11c) - -/* EFUSE_DEC_WARNINGS : RO ;bitpos:[11:0] ;default: 12'b0 ; - * Description: the decode result of 3/4 coding scheme has warning - */ - -#define EFUSE_DEC_WARNINGS 0x00000fff -#define EFUSE_DEC_WARNINGS_M ((EFUSE_DEC_WARNINGS_V) << \ - (EFUSE_DEC_WARNINGS_S)) -#define EFUSE_DEC_WARNINGS_V 0xfff -#define EFUSE_DEC_WARNINGS_S 0 - -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) - -/* EFUSE_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042600 ; - * Description: - */ - -#define EFUSE_DATE 0xffffffff -#define EFUSE_DATE_M ((EFUSE_DATE_V) << \ - (EFUSE_DATE_S)) -#define EFUSE_DATE_V 0xffffffff -#define EFUSE_DATE_S 0 - -#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_EFUSE_REG_H */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_aes.h b/arch/xtensa/src/esp32/hardware/esp32_aes.h index e2ed92d93af4a..af2714597beca 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_aes.h +++ b/arch/xtensa/src/esp32/hardware/esp32_aes.h @@ -23,8 +23,6 @@ /* AES acceleration registers */ -#define DR_REG_AES_BASE (0x3ff01000) - #define AES_START_REG ((DR_REG_AES_BASE) + 0x00) #define AES_IDLE_REG ((DR_REG_AES_BASE) + 0x04) #define AES_MODE_REG ((DR_REG_AES_BASE) + 0x08) diff --git a/arch/xtensa/src/esp32/hardware/esp32_apb_ctrl.h b/arch/xtensa/src/esp32/hardware/esp32_apb_ctrl.h new file mode 100644 index 0000000000000..83ca590a322e9 --- /dev/null +++ b/arch/xtensa/src/esp32/hardware/esp32_apb_ctrl.h @@ -0,0 +1,422 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/hardware/esp32_apb_ctrl.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_APB_CTRL_H +#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_APB_CTRL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* APB_CTRL_SYSCLK_CONF_REG register */ + +#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0) + +/* APB_CTRL_QUICK_CLK_CHNG : RW; bitpos: [13]; default: 1; */ + +#define APB_CTRL_QUICK_CLK_CHNG (BIT(13)) +#define APB_CTRL_QUICK_CLK_CHNG_M (APB_CTRL_QUICK_CLK_CHNG_V << APB_CTRL_QUICK_CLK_CHNG_S) +#define APB_CTRL_QUICK_CLK_CHNG_V 0x00000001 +#define APB_CTRL_QUICK_CLK_CHNG_S 13 + +/* APB_CTRL_RST_TICK_CNT : RW; bitpos: [12]; default: 0; */ + +#define APB_CTRL_RST_TICK_CNT (BIT(12)) +#define APB_CTRL_RST_TICK_CNT_M (APB_CTRL_RST_TICK_CNT_V << APB_CTRL_RST_TICK_CNT_S) +#define APB_CTRL_RST_TICK_CNT_V 0x00000001 +#define APB_CTRL_RST_TICK_CNT_S 12 + +/* APB_CTRL_CLK_EN : RW; bitpos: [11]; default: 0; */ + +#define APB_CTRL_CLK_EN (BIT(11)) +#define APB_CTRL_CLK_EN_M (APB_CTRL_CLK_EN_V << APB_CTRL_CLK_EN_S) +#define APB_CTRL_CLK_EN_V 0x00000001 +#define APB_CTRL_CLK_EN_S 11 + +/* APB_CTRL_CLK_320M_EN : RW; bitpos: [10]; default: 0; */ + +#define APB_CTRL_CLK_320M_EN (BIT(10)) +#define APB_CTRL_CLK_320M_EN_M (APB_CTRL_CLK_320M_EN_V << APB_CTRL_CLK_320M_EN_S) +#define APB_CTRL_CLK_320M_EN_V 0x00000001 +#define APB_CTRL_CLK_320M_EN_S 10 + +/* APB_CTRL_PRE_DIV_CNT : RW; bitpos: [9:0]; default: 0; */ + +#define APB_CTRL_PRE_DIV_CNT 0x000003ff +#define APB_CTRL_PRE_DIV_CNT_M (APB_CTRL_PRE_DIV_CNT_V << APB_CTRL_PRE_DIV_CNT_S) +#define APB_CTRL_PRE_DIV_CNT_V 0x000003ff +#define APB_CTRL_PRE_DIV_CNT_S 0 + +/* APB_CTRL_XTAL_TICK_CONF_REG register */ + +#define APB_CTRL_XTAL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4) + +/* APB_CTRL_XTAL_TICK_NUM : RW; bitpos: [7:0]; default: 39; */ + +#define APB_CTRL_XTAL_TICK_NUM 0x000000ff +#define APB_CTRL_XTAL_TICK_NUM_M (APB_CTRL_XTAL_TICK_NUM_V << APB_CTRL_XTAL_TICK_NUM_S) +#define APB_CTRL_XTAL_TICK_NUM_V 0x000000ff +#define APB_CTRL_XTAL_TICK_NUM_S 0 + +/* APB_CTRL_PLL_TICK_CONF_REG register */ + +#define APB_CTRL_PLL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x8) + +/* APB_CTRL_PLL_TICK_NUM : RW; bitpos: [7:0]; default: 79; */ + +#define APB_CTRL_PLL_TICK_NUM 0x000000ff +#define APB_CTRL_PLL_TICK_NUM_M (APB_CTRL_PLL_TICK_NUM_V << APB_CTRL_PLL_TICK_NUM_S) +#define APB_CTRL_PLL_TICK_NUM_V 0x000000ff +#define APB_CTRL_PLL_TICK_NUM_S 0 + +/* APB_CTRL_CK8M_TICK_CONF_REG register */ + +#define APB_CTRL_CK8M_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0xc) + +/* APB_CTRL_CK8M_TICK_NUM : RW; bitpos: [7:0]; default: 11; */ + +#define APB_CTRL_CK8M_TICK_NUM 0x000000ff +#define APB_CTRL_CK8M_TICK_NUM_M (APB_CTRL_CK8M_TICK_NUM_V << APB_CTRL_CK8M_TICK_NUM_S) +#define APB_CTRL_CK8M_TICK_NUM_V 0x000000ff +#define APB_CTRL_CK8M_TICK_NUM_S 0 + +/* APB_CTRL_APB_SARADC_CTRL_REG register */ + +#define APB_CTRL_APB_SARADC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x10) + +/* APB_CTRL_SARADC_DATA_TO_I2S : RW; bitpos: [26]; default: 0; + * 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from + * GPIO matrix + */ + +#define APB_CTRL_SARADC_DATA_TO_I2S (BIT(26)) +#define APB_CTRL_SARADC_DATA_TO_I2S_M (APB_CTRL_SARADC_DATA_TO_I2S_V << APB_CTRL_SARADC_DATA_TO_I2S_S) +#define APB_CTRL_SARADC_DATA_TO_I2S_V 0x00000001 +#define APB_CTRL_SARADC_DATA_TO_I2S_S 26 + +/* APB_CTRL_SARADC_DATA_SAR_SEL : RW; bitpos: [25]; default: 0; + * 1: sar_sel will be coded by the MSB of the 16-bit output data in this + * case the resolution should not be larger than 11 bits. + */ + +#define APB_CTRL_SARADC_DATA_SAR_SEL (BIT(25)) +#define APB_CTRL_SARADC_DATA_SAR_SEL_M (APB_CTRL_SARADC_DATA_SAR_SEL_V << APB_CTRL_SARADC_DATA_SAR_SEL_S) +#define APB_CTRL_SARADC_DATA_SAR_SEL_V 0x00000001 +#define APB_CTRL_SARADC_DATA_SAR_SEL_S 25 + +/* APB_CTRL_SARADC_SAR2_PATT_P_CLEAR : RW; bitpos: [24]; default: 0; + * clear the pointer of pattern table for DIG ADC2 CTRL + */ + +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR (BIT(24)) +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_M (APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_V << APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_S) +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_V 0x00000001 +#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_S 24 + +/* APB_CTRL_SARADC_SAR1_PATT_P_CLEAR : RW; bitpos: [23]; default: 0; + * clear the pointer of pattern table for DIG ADC1 CTRL + */ + +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR (BIT(23)) +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_M (APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_V << APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_S) +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_V 0x00000001 +#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_S 23 + +/* APB_CTRL_SARADC_SAR2_PATT_LEN : RW; bitpos: [22:19]; default: 15; + * 0 ~ 15 means length 1 ~ 16 + */ + +#define APB_CTRL_SARADC_SAR2_PATT_LEN 0x0000000f +#define APB_CTRL_SARADC_SAR2_PATT_LEN_M (APB_CTRL_SARADC_SAR2_PATT_LEN_V << APB_CTRL_SARADC_SAR2_PATT_LEN_S) +#define APB_CTRL_SARADC_SAR2_PATT_LEN_V 0x0000000f +#define APB_CTRL_SARADC_SAR2_PATT_LEN_S 19 + +/* APB_CTRL_SARADC_SAR1_PATT_LEN : RW; bitpos: [18:15]; default: 15; + * 0 ~ 15 means length 1 ~ 16 + */ + +#define APB_CTRL_SARADC_SAR1_PATT_LEN 0x0000000f +#define APB_CTRL_SARADC_SAR1_PATT_LEN_M (APB_CTRL_SARADC_SAR1_PATT_LEN_V << APB_CTRL_SARADC_SAR1_PATT_LEN_S) +#define APB_CTRL_SARADC_SAR1_PATT_LEN_V 0x0000000f +#define APB_CTRL_SARADC_SAR1_PATT_LEN_S 15 + +/* APB_CTRL_SARADC_SAR_CLK_DIV : RW; bitpos: [14:7]; default: 4; + * SAR clock divider + */ + +#define APB_CTRL_SARADC_SAR_CLK_DIV 0x000000ff +#define APB_CTRL_SARADC_SAR_CLK_DIV_M (APB_CTRL_SARADC_SAR_CLK_DIV_V << APB_CTRL_SARADC_SAR_CLK_DIV_S) +#define APB_CTRL_SARADC_SAR_CLK_DIV_V 0x000000ff +#define APB_CTRL_SARADC_SAR_CLK_DIV_S 7 + +/* APB_CTRL_SARADC_SAR_CLK_GATED : RW; bitpos: [6]; default: 1; */ + +#define APB_CTRL_SARADC_SAR_CLK_GATED (BIT(6)) +#define APB_CTRL_SARADC_SAR_CLK_GATED_M (APB_CTRL_SARADC_SAR_CLK_GATED_V << APB_CTRL_SARADC_SAR_CLK_GATED_S) +#define APB_CTRL_SARADC_SAR_CLK_GATED_V 0x00000001 +#define APB_CTRL_SARADC_SAR_CLK_GATED_S 6 + +/* APB_CTRL_SARADC_SAR_SEL : RW; bitpos: [5]; default: 0; + * 0: SAR1 1: SAR2 only work for single SAR mode + */ + +#define APB_CTRL_SARADC_SAR_SEL (BIT(5)) +#define APB_CTRL_SARADC_SAR_SEL_M (APB_CTRL_SARADC_SAR_SEL_V << APB_CTRL_SARADC_SAR_SEL_S) +#define APB_CTRL_SARADC_SAR_SEL_V 0x00000001 +#define APB_CTRL_SARADC_SAR_SEL_S 5 + +/* APB_CTRL_SARADC_WORK_MODE : RW; bitpos: [4:3]; default: 0; + * 0: single mode 1: double mode 2: alternate mode + */ + +#define APB_CTRL_SARADC_WORK_MODE 0x00000003 +#define APB_CTRL_SARADC_WORK_MODE_M (APB_CTRL_SARADC_WORK_MODE_V << APB_CTRL_SARADC_WORK_MODE_S) +#define APB_CTRL_SARADC_WORK_MODE_V 0x00000003 +#define APB_CTRL_SARADC_WORK_MODE_S 3 + +/* APB_CTRL_SARADC_SAR2_MUX : RW; bitpos: [2]; default: 0; + * 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by + * PWDET CTRL + */ + +#define APB_CTRL_SARADC_SAR2_MUX (BIT(2)) +#define APB_CTRL_SARADC_SAR2_MUX_M (APB_CTRL_SARADC_SAR2_MUX_V << APB_CTRL_SARADC_SAR2_MUX_S) +#define APB_CTRL_SARADC_SAR2_MUX_V 0x00000001 +#define APB_CTRL_SARADC_SAR2_MUX_S 2 + +/* APB_CTRL_SARADC_START : RW; bitpos: [1]; default: 0; */ + +#define APB_CTRL_SARADC_START (BIT(1)) +#define APB_CTRL_SARADC_START_M (APB_CTRL_SARADC_START_V << APB_CTRL_SARADC_START_S) +#define APB_CTRL_SARADC_START_V 0x00000001 +#define APB_CTRL_SARADC_START_S 1 + +/* APB_CTRL_SARADC_START_FORCE : RW; bitpos: [0]; default: 0; */ + +#define APB_CTRL_SARADC_START_FORCE (BIT(0)) +#define APB_CTRL_SARADC_START_FORCE_M (APB_CTRL_SARADC_START_FORCE_V << APB_CTRL_SARADC_START_FORCE_S) +#define APB_CTRL_SARADC_START_FORCE_V 0x00000001 +#define APB_CTRL_SARADC_START_FORCE_S 0 + +/* APB_CTRL_APB_SARADC_CTRL2_REG register */ + +#define APB_CTRL_APB_SARADC_CTRL2_REG (DR_REG_APB_CTRL_BASE + 0x14) + +/* APB_CTRL_SARADC_SAR2_INV : RW; bitpos: [10]; default: 0; + * 1: data to DIG ADC2 CTRL is inverted otherwise not + */ + +#define APB_CTRL_SARADC_SAR2_INV (BIT(10)) +#define APB_CTRL_SARADC_SAR2_INV_M (APB_CTRL_SARADC_SAR2_INV_V << APB_CTRL_SARADC_SAR2_INV_S) +#define APB_CTRL_SARADC_SAR2_INV_V 0x00000001 +#define APB_CTRL_SARADC_SAR2_INV_S 10 + +/* APB_CTRL_SARADC_SAR1_INV : RW; bitpos: [9]; default: 0; + * 1: data to DIG ADC1 CTRL is inverted otherwise not + */ + +#define APB_CTRL_SARADC_SAR1_INV (BIT(9)) +#define APB_CTRL_SARADC_SAR1_INV_M (APB_CTRL_SARADC_SAR1_INV_V << APB_CTRL_SARADC_SAR1_INV_S) +#define APB_CTRL_SARADC_SAR1_INV_V 0x00000001 +#define APB_CTRL_SARADC_SAR1_INV_S 9 + +/* APB_CTRL_SARADC_MAX_MEAS_NUM : RW; bitpos: [8:1]; default: 255; + * max conversion number + */ + +#define APB_CTRL_SARADC_MAX_MEAS_NUM 0x000000ff +#define APB_CTRL_SARADC_MAX_MEAS_NUM_M (APB_CTRL_SARADC_MAX_MEAS_NUM_V << APB_CTRL_SARADC_MAX_MEAS_NUM_S) +#define APB_CTRL_SARADC_MAX_MEAS_NUM_V 0x000000ff +#define APB_CTRL_SARADC_MAX_MEAS_NUM_S 1 + +/* APB_CTRL_SARADC_MEAS_NUM_LIMIT : RW; bitpos: [0]; default: 0; */ + +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_M (APB_CTRL_SARADC_MEAS_NUM_LIMIT_V << APB_CTRL_SARADC_MEAS_NUM_LIMIT_S) +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_V 0x00000001 +#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_S 0 + +/* APB_CTRL_APB_SARADC_FSM_REG register */ + +#define APB_CTRL_APB_SARADC_FSM_REG (DR_REG_APB_CTRL_BASE + 0x18) + +/* APB_CTRL_SARADC_SAMPLE_CYCLE : RW; bitpos: [31:24]; default: 2; + * sample cycles + */ + +#define APB_CTRL_SARADC_SAMPLE_CYCLE 0x000000ff +#define APB_CTRL_SARADC_SAMPLE_CYCLE_M (APB_CTRL_SARADC_SAMPLE_CYCLE_V << APB_CTRL_SARADC_SAMPLE_CYCLE_S) +#define APB_CTRL_SARADC_SAMPLE_CYCLE_V 0x000000ff +#define APB_CTRL_SARADC_SAMPLE_CYCLE_S 24 + +/* APB_CTRL_SARADC_START_WAIT : RW; bitpos: [23:16]; default: 8; */ + +#define APB_CTRL_SARADC_START_WAIT 0x000000ff +#define APB_CTRL_SARADC_START_WAIT_M (APB_CTRL_SARADC_START_WAIT_V << APB_CTRL_SARADC_START_WAIT_S) +#define APB_CTRL_SARADC_START_WAIT_V 0x000000ff +#define APB_CTRL_SARADC_START_WAIT_S 16 + +/* APB_CTRL_SARADC_STANDBY_WAIT : RW; bitpos: [15:8]; default: 255; */ + +#define APB_CTRL_SARADC_STANDBY_WAIT 0x000000ff +#define APB_CTRL_SARADC_STANDBY_WAIT_M (APB_CTRL_SARADC_STANDBY_WAIT_V << APB_CTRL_SARADC_STANDBY_WAIT_S) +#define APB_CTRL_SARADC_STANDBY_WAIT_V 0x000000ff +#define APB_CTRL_SARADC_STANDBY_WAIT_S 8 + +/* APB_CTRL_SARADC_RSTB_WAIT : RW; bitpos: [7:0]; default: 8; */ + +#define APB_CTRL_SARADC_RSTB_WAIT 0x000000ff +#define APB_CTRL_SARADC_RSTB_WAIT_M (APB_CTRL_SARADC_RSTB_WAIT_V << APB_CTRL_SARADC_RSTB_WAIT_S) +#define APB_CTRL_SARADC_RSTB_WAIT_V 0x000000ff +#define APB_CTRL_SARADC_RSTB_WAIT_S 0 + +/* APB_CTRL_APB_SARADC_SAR1_PATT_TAB1_REG register */ + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x1c) + +/* APB_CTRL_SARADC_SAR1_PATT_TAB1 : RW; bitpos: [31:0]; default: 252645135; + * item 0 ~ 3 for pattern table 1 (each item one byte) + */ + +#define APB_CTRL_SARADC_SAR1_PATT_TAB1 0xffffffff +#define APB_CTRL_SARADC_SAR1_PATT_TAB1_M (APB_CTRL_SARADC_SAR1_PATT_TAB1_V << APB_CTRL_SARADC_SAR1_PATT_TAB1_S) +#define APB_CTRL_SARADC_SAR1_PATT_TAB1_V 0xffffffff +#define APB_CTRL_SARADC_SAR1_PATT_TAB1_S 0 + +/* APB_CTRL_APB_SARADC_SAR1_PATT_TAB2_REG register */ + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x20) + +/* APB_CTRL_SARADC_SAR1_PATT_TAB2 : RW; bitpos: [31:0]; default: 252645135; + * Item 4 ~ 7 for pattern table 1 (each item one byte) + */ + +#define APB_CTRL_SARADC_SAR1_PATT_TAB2 0xffffffff +#define APB_CTRL_SARADC_SAR1_PATT_TAB2_M (APB_CTRL_SARADC_SAR1_PATT_TAB2_V << APB_CTRL_SARADC_SAR1_PATT_TAB2_S) +#define APB_CTRL_SARADC_SAR1_PATT_TAB2_V 0xffffffff +#define APB_CTRL_SARADC_SAR1_PATT_TAB2_S 0 + +/* APB_CTRL_APB_SARADC_SAR1_PATT_TAB3_REG register */ + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x24) + +/* APB_CTRL_SARADC_SAR1_PATT_TAB3 : RW; bitpos: [31:0]; default: 252645135; + * Item 8 ~ 11 for pattern table 1 (each item one byte) + */ + +#define APB_CTRL_SARADC_SAR1_PATT_TAB3 0xffffffff +#define APB_CTRL_SARADC_SAR1_PATT_TAB3_M (APB_CTRL_SARADC_SAR1_PATT_TAB3_V << APB_CTRL_SARADC_SAR1_PATT_TAB3_S) +#define APB_CTRL_SARADC_SAR1_PATT_TAB3_V 0xffffffff +#define APB_CTRL_SARADC_SAR1_PATT_TAB3_S 0 + +/* APB_CTRL_APB_SARADC_SAR1_PATT_TAB4_REG register */ + +#define APB_CTRL_APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x28) + +/* APB_CTRL_SARADC_SAR1_PATT_TAB4 : RW; bitpos: [31:0]; default: 252645135; + * Item 12 ~ 15 for pattern table 1 (each item one byte) + */ + +#define APB_CTRL_SARADC_SAR1_PATT_TAB4 0xffffffff +#define APB_CTRL_SARADC_SAR1_PATT_TAB4_M (APB_CTRL_SARADC_SAR1_PATT_TAB4_V << APB_CTRL_SARADC_SAR1_PATT_TAB4_S) +#define APB_CTRL_SARADC_SAR1_PATT_TAB4_V 0xffffffff +#define APB_CTRL_SARADC_SAR1_PATT_TAB4_S 0 + +/* APB_CTRL_APB_SARADC_SAR2_PATT_TAB1_REG register */ + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_CTRL_BASE + 0x2c) + +/* APB_CTRL_SARADC_SAR2_PATT_TAB1 : RW; bitpos: [31:0]; default: 252645135; + * item 0 ~ 3 for pattern table 2 (each item one byte) + */ + +#define APB_CTRL_SARADC_SAR2_PATT_TAB1 0xffffffff +#define APB_CTRL_SARADC_SAR2_PATT_TAB1_M (APB_CTRL_SARADC_SAR2_PATT_TAB1_V << APB_CTRL_SARADC_SAR2_PATT_TAB1_S) +#define APB_CTRL_SARADC_SAR2_PATT_TAB1_V 0xffffffff +#define APB_CTRL_SARADC_SAR2_PATT_TAB1_S 0 + +/* APB_CTRL_APB_SARADC_SAR2_PATT_TAB2_REG register */ + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_CTRL_BASE + 0x30) + +/* APB_CTRL_SARADC_SAR2_PATT_TAB2 : RW; bitpos: [31:0]; default: 252645135; + * Item 4 ~ 7 for pattern table 2 (each item one byte) + */ + +#define APB_CTRL_SARADC_SAR2_PATT_TAB2 0xffffffff +#define APB_CTRL_SARADC_SAR2_PATT_TAB2_M (APB_CTRL_SARADC_SAR2_PATT_TAB2_V << APB_CTRL_SARADC_SAR2_PATT_TAB2_S) +#define APB_CTRL_SARADC_SAR2_PATT_TAB2_V 0xffffffff +#define APB_CTRL_SARADC_SAR2_PATT_TAB2_S 0 + +/* APB_CTRL_APB_SARADC_SAR2_PATT_TAB3_REG register */ + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_CTRL_BASE + 0x34) + +/* APB_CTRL_SARADC_SAR2_PATT_TAB3 : RW; bitpos: [31:0]; default: 252645135; + * Item 8 ~ 11 for pattern table 2 (each item one byte) + */ + +#define APB_CTRL_SARADC_SAR2_PATT_TAB3 0xffffffff +#define APB_CTRL_SARADC_SAR2_PATT_TAB3_M (APB_CTRL_SARADC_SAR2_PATT_TAB3_V << APB_CTRL_SARADC_SAR2_PATT_TAB3_S) +#define APB_CTRL_SARADC_SAR2_PATT_TAB3_V 0xffffffff +#define APB_CTRL_SARADC_SAR2_PATT_TAB3_S 0 + +/* APB_CTRL_APB_SARADC_SAR2_PATT_TAB4_REG register */ + +#define APB_CTRL_APB_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_CTRL_BASE + 0x38) + +/* APB_CTRL_SARADC_SAR2_PATT_TAB4 : RW; bitpos: [31:0]; default: 252645135; + * Item 12 ~ 15 for pattern table 2 (each item one byte) + */ + +#define APB_CTRL_SARADC_SAR2_PATT_TAB4 0xffffffff +#define APB_CTRL_SARADC_SAR2_PATT_TAB4_M (APB_CTRL_SARADC_SAR2_PATT_TAB4_V << APB_CTRL_SARADC_SAR2_PATT_TAB4_S) +#define APB_CTRL_SARADC_SAR2_PATT_TAB4_V 0xffffffff +#define APB_CTRL_SARADC_SAR2_PATT_TAB4_S 0 + +/* APB_CTRL_APLL_TICK_CONF_REG register */ + +#define APB_CTRL_APLL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x3c) + +/* APB_CTRL_APLL_TICK_NUM : RW; bitpos: [7:0]; default: 99; */ + +#define APB_CTRL_APLL_TICK_NUM 0x000000ff +#define APB_CTRL_APLL_TICK_NUM_M (APB_CTRL_APLL_TICK_NUM_V << APB_CTRL_APLL_TICK_NUM_S) +#define APB_CTRL_APLL_TICK_NUM_V 0x000000ff +#define APB_CTRL_APLL_TICK_NUM_S 0 + +/* APB_CTRL_DATE_REG register */ + +#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x7c) + +/* APB_CTRL_DATE : RW; bitpos: [31:0]; default: 369369088; */ + +#define APB_CTRL_DATE 0xffffffff +#define APB_CTRL_DATE_M (APB_CTRL_DATE_V << APB_CTRL_DATE_S) +#define APB_CTRL_DATE_V 0xffffffff +#define APB_CTRL_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_APB_CTRL_H */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_efuse.h b/arch/xtensa/src/esp32/hardware/esp32_efuse.h new file mode 100644 index 0000000000000..81d28597849e1 --- /dev/null +++ b/arch/xtensa/src/esp32/hardware/esp32_efuse.h @@ -0,0 +1,1503 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/hardware/esp32_efuse.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_EFUSE_H +#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_EFUSE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32_soc.h" +#include "esp32_efuse_defs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* EFUSE_BLK0_RDATA0_REG register */ + +#define EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x0) + +/* EFUSE_RESERVED_0_28 : R; bitpos: [31:28]; default: 0; */ + +#define EFUSE_RESERVED_0_28 0x0000000f +#define EFUSE_RESERVED_0_28_M (EFUSE_RESERVED_0_28_V << EFUSE_RESERVED_0_28_S) +#define EFUSE_RESERVED_0_28_V 0x0000000f +#define EFUSE_RESERVED_0_28_S 28 + +/* EFUSE_RD_UART_DOWNLOAD_DIS : R; bitpos: [27]; default: 0; */ + +#define EFUSE_RD_UART_DOWNLOAD_DIS (BIT(27)) +#define EFUSE_RD_UART_DOWNLOAD_DIS_M (EFUSE_RD_UART_DOWNLOAD_DIS_V << EFUSE_RD_UART_DOWNLOAD_DIS_S) +#define EFUSE_RD_UART_DOWNLOAD_DIS_V 0x00000001 +#define EFUSE_RD_UART_DOWNLOAD_DIS_S 27 + +/* EFUSE_RD_FLASH_CRYPT_CNT : R; bitpos: [26:20]; default: 0; */ + +#define EFUSE_RD_FLASH_CRYPT_CNT 0x0000007f +#define EFUSE_RD_FLASH_CRYPT_CNT_M (EFUSE_RD_FLASH_CRYPT_CNT_V << EFUSE_RD_FLASH_CRYPT_CNT_S) +#define EFUSE_RD_FLASH_CRYPT_CNT_V 0x0000007f +#define EFUSE_RD_FLASH_CRYPT_CNT_S 20 + +/* EFUSE_RD_EFUSE_RD_DIS : R; bitpos: [19:16]; default: 0; */ + +#define EFUSE_RD_EFUSE_RD_DIS 0x0000000f +#define EFUSE_RD_EFUSE_RD_DIS_M (EFUSE_RD_EFUSE_RD_DIS_V << EFUSE_RD_EFUSE_RD_DIS_S) +#define EFUSE_RD_EFUSE_RD_DIS_V 0x0000000f +#define EFUSE_RD_EFUSE_RD_DIS_S 16 + +/* EFUSE_RD_EFUSE_WR_DIS : R; bitpos: [15:0]; default: 0; */ + +#define EFUSE_RD_EFUSE_WR_DIS 0x0000ffff +#define EFUSE_RD_EFUSE_WR_DIS_M (EFUSE_RD_EFUSE_WR_DIS_V << EFUSE_RD_EFUSE_WR_DIS_S) +#define EFUSE_RD_EFUSE_WR_DIS_V 0x0000ffff +#define EFUSE_RD_EFUSE_WR_DIS_S 0 + +/* EFUSE_BLK0_RDATA1_REG register */ + +#define EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x4) + +/* EFUSE_RD_MAC : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_MAC 0xffffffff +#define EFUSE_RD_MAC_M (EFUSE_RD_MAC_V << EFUSE_RD_MAC_S) +#define EFUSE_RD_MAC_V 0xffffffff +#define EFUSE_RD_MAC_S 0 + +/* EFUSE_BLK0_RDATA2_REG register */ + +#define EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x8) + +/* EFUSE_RD_RESERVE_0_88 : RW; bitpos: [31:24]; default: 0; */ + +#define EFUSE_RD_RESERVE_0_88 0x000000ff +#define EFUSE_RD_RESERVE_0_88_M (EFUSE_RD_RESERVE_0_88_V << EFUSE_RD_RESERVE_0_88_S) +#define EFUSE_RD_RESERVE_0_88_V 0x000000ff +#define EFUSE_RD_RESERVE_0_88_S 24 + +/* EFUSE_RD_MAC_CRC : R; bitpos: [23:16]; default: 0; */ + +#define EFUSE_RD_MAC_CRC 0x000000ff +#define EFUSE_RD_MAC_CRC_M (EFUSE_RD_MAC_CRC_V << EFUSE_RD_MAC_CRC_S) +#define EFUSE_RD_MAC_CRC_V 0x000000ff +#define EFUSE_RD_MAC_CRC_S 16 + +/* EFUSE_RD_MAC_1 : R; bitpos: [15:0]; default: 0; */ + +#define EFUSE_RD_MAC_1 0x0000ffff +#define EFUSE_RD_MAC_1_M (EFUSE_RD_MAC_1_V << EFUSE_RD_MAC_1_S) +#define EFUSE_RD_MAC_1_V 0x0000ffff +#define EFUSE_RD_MAC_1_S 0 + +/* EFUSE_BLK0_RDATA3_REG register */ + +#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0xc) + +/* EFUSE_RD_RESERVE_0_112 : RW; bitpos: [31:16]; default: 0; */ + +#define EFUSE_RD_RESERVE_0_112 0x0000ffff +#define EFUSE_RD_RESERVE_0_112_M (EFUSE_RD_RESERVE_0_112_V << EFUSE_RD_RESERVE_0_112_S) +#define EFUSE_RD_RESERVE_0_112_V 0x0000ffff +#define EFUSE_RD_RESERVE_0_112_S 16 + +/* EFUSE_RD_CHIP_VER_REV1 : RW; bitpos: [15]; default: 0; */ + +#define EFUSE_RD_CHIP_VER_REV1 (BIT(15)) +#define EFUSE_RD_CHIP_VER_REV1_M (EFUSE_RD_CHIP_VER_REV1_V << EFUSE_RD_CHIP_VER_REV1_S) +#define EFUSE_RD_CHIP_VER_REV1_V 0x00000001 +#define EFUSE_RD_CHIP_VER_REV1_S 15 + +/* EFUSE_RD_BLK3_PART_RESERVE : RW; bitpos: [14]; default: 0; */ + +#define EFUSE_RD_BLK3_PART_RESERVE (BIT(14)) +#define EFUSE_RD_BLK3_PART_RESERVE_M (EFUSE_RD_BLK3_PART_RESERVE_V << EFUSE_RD_BLK3_PART_RESERVE_S) +#define EFUSE_RD_BLK3_PART_RESERVE_V 0x00000001 +#define EFUSE_RD_BLK3_PART_RESERVE_S 14 + +/* EFUSE_RD_CHIP_CPU_FREQ_RATED : RW; bitpos: [13]; default: 0; */ + +#define EFUSE_RD_CHIP_CPU_FREQ_RATED (BIT(13)) +#define EFUSE_RD_CHIP_CPU_FREQ_RATED_M (EFUSE_RD_CHIP_CPU_FREQ_RATED_V << EFUSE_RD_CHIP_CPU_FREQ_RATED_S) +#define EFUSE_RD_CHIP_CPU_FREQ_RATED_V 0x00000001 +#define EFUSE_RD_CHIP_CPU_FREQ_RATED_S 13 + +/* EFUSE_RD_CHIP_CPU_FREQ_LOW : RW; bitpos: [12]; default: 0; */ + +#define EFUSE_RD_CHIP_CPU_FREQ_LOW (BIT(12)) +#define EFUSE_RD_CHIP_CPU_FREQ_LOW_M (EFUSE_RD_CHIP_CPU_FREQ_LOW_V << EFUSE_RD_CHIP_CPU_FREQ_LOW_S) +#define EFUSE_RD_CHIP_CPU_FREQ_LOW_V 0x00000001 +#define EFUSE_RD_CHIP_CPU_FREQ_LOW_S 12 + +/* EFUSE_RD_CHIP_PACKAGE : RW; bitpos: [11:9]; default: 0; */ + +#define EFUSE_RD_CHIP_PACKAGE 0x00000007 +#define EFUSE_RD_CHIP_PACKAGE_M (EFUSE_RD_CHIP_PACKAGE_V << EFUSE_RD_CHIP_PACKAGE_S) +#define EFUSE_RD_CHIP_PACKAGE_V 0x00000007 +#define EFUSE_RD_CHIP_PACKAGE_S 9 + +/* EFUSE_RD_SPI_PAD_CONFIG_HD : R; bitpos: [8:4]; default: 0; */ + +#define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_HD_M (EFUSE_RD_SPI_PAD_CONFIG_HD_V << EFUSE_RD_SPI_PAD_CONFIG_HD_S) +#define EFUSE_RD_SPI_PAD_CONFIG_HD_V 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_HD_S 4 + +/* EFUSE_RD_DIS_CACHE : R; bitpos: [3]; default: 0; */ + +#define EFUSE_RD_DIS_CACHE (BIT(3)) +#define EFUSE_RD_DIS_CACHE_M (EFUSE_RD_DIS_CACHE_V << EFUSE_RD_DIS_CACHE_S) +#define EFUSE_RD_DIS_CACHE_V 0x00000001 +#define EFUSE_RD_DIS_CACHE_S 3 + +/* EFUSE_RD_CHIP_PACKAGE_4BIT : R; bitpos: [2]; default: 0; */ + +#define EFUSE_RD_CHIP_PACKAGE_4BIT (BIT(2)) +#define EFUSE_RD_CHIP_PACKAGE_4BIT_M (EFUSE_RD_CHIP_PACKAGE_4BIT_V << EFUSE_RD_CHIP_PACKAGE_4BIT_S) +#define EFUSE_RD_CHIP_PACKAGE_4BIT_V 0x00000001 +#define EFUSE_RD_CHIP_PACKAGE_4BIT_S 2 + +/* EFUSE_RD_DISABLE_BT : R; bitpos: [1]; default: 0; */ + +#define EFUSE_RD_DISABLE_BT (BIT(1)) +#define EFUSE_RD_DISABLE_BT_M (EFUSE_RD_DISABLE_BT_V << EFUSE_RD_DISABLE_BT_S) +#define EFUSE_RD_DISABLE_BT_V 0x00000001 +#define EFUSE_RD_DISABLE_BT_S 1 + +/* EFUSE_RD_DISABLE_APP_CPU : R; bitpos: [0]; default: 0; */ + +#define EFUSE_RD_DISABLE_APP_CPU (BIT(0)) +#define EFUSE_RD_DISABLE_APP_CPU_M (EFUSE_RD_DISABLE_APP_CPU_V << EFUSE_RD_DISABLE_APP_CPU_S) +#define EFUSE_RD_DISABLE_APP_CPU_V 0x00000001 +#define EFUSE_RD_DISABLE_APP_CPU_S 0 + +/* EFUSE_BLK0_RDATA4_REG register */ + +#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x10) + +/* EFUSE_RD_RESERVE_0_145 : RW; bitpos: [31:17]; default: 0; */ + +#define EFUSE_RD_RESERVE_0_145 0x00007fff +#define EFUSE_RD_RESERVE_0_145_M (EFUSE_RD_RESERVE_0_145_V << EFUSE_RD_RESERVE_0_145_S) +#define EFUSE_RD_RESERVE_0_145_V 0x00007fff +#define EFUSE_RD_RESERVE_0_145_S 17 + +/* EFUSE_RD_XPD_SDIO_FORCE : R; bitpos: [16]; default: 0; */ + +#define EFUSE_RD_XPD_SDIO_FORCE (BIT(16)) +#define EFUSE_RD_XPD_SDIO_FORCE_M (EFUSE_RD_XPD_SDIO_FORCE_V << EFUSE_RD_XPD_SDIO_FORCE_S) +#define EFUSE_RD_XPD_SDIO_FORCE_V 0x00000001 +#define EFUSE_RD_XPD_SDIO_FORCE_S 16 + +/* EFUSE_RD_XPD_SDIO_TIEH : R; bitpos: [15]; default: 0; */ + +#define EFUSE_RD_XPD_SDIO_TIEH (BIT(15)) +#define EFUSE_RD_XPD_SDIO_TIEH_M (EFUSE_RD_XPD_SDIO_TIEH_V << EFUSE_RD_XPD_SDIO_TIEH_S) +#define EFUSE_RD_XPD_SDIO_TIEH_V 0x00000001 +#define EFUSE_RD_XPD_SDIO_TIEH_S 15 + +/* EFUSE_RD_XPD_SDIO_REG : R; bitpos: [14]; default: 0; */ + +#define EFUSE_RD_XPD_SDIO_REG (BIT(14)) +#define EFUSE_RD_XPD_SDIO_REG_M (EFUSE_RD_XPD_SDIO_REG_V << EFUSE_RD_XPD_SDIO_REG_S) +#define EFUSE_RD_XPD_SDIO_REG_V 0x00000001 +#define EFUSE_RD_XPD_SDIO_REG_S 14 + +/* EFUSE_RD_RESERVE_0_141 : RW; bitpos: [13]; default: 0; */ + +#define EFUSE_RD_RESERVE_0_141 (BIT(13)) +#define EFUSE_RD_RESERVE_0_141_M (EFUSE_RD_RESERVE_0_141_V << EFUSE_RD_RESERVE_0_141_S) +#define EFUSE_RD_RESERVE_0_141_V 0x00000001 +#define EFUSE_RD_RESERVE_0_141_S 13 + +/* EFUSE_RD_ADC_VREF : RW; bitpos: [12:8]; default: 0; */ + +#define EFUSE_RD_ADC_VREF 0x0000001f +#define EFUSE_RD_ADC_VREF_M (EFUSE_RD_ADC_VREF_V << EFUSE_RD_ADC_VREF_S) +#define EFUSE_RD_ADC_VREF_V 0x0000001f +#define EFUSE_RD_ADC_VREF_S 8 + +/* EFUSE_RD_CLK8M_FREQ : R; bitpos: [7:0]; default: 0; */ + +#define EFUSE_RD_CLK8M_FREQ 0x000000ff +#define EFUSE_RD_CLK8M_FREQ_M (EFUSE_RD_CLK8M_FREQ_V << EFUSE_RD_CLK8M_FREQ_S) +#define EFUSE_RD_CLK8M_FREQ_V 0x000000ff +#define EFUSE_RD_CLK8M_FREQ_S 0 + +/* EFUSE_BLK0_RDATA5_REG register */ + +#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x14) + +/* EFUSE_RD_FLASH_CRYPT_CONFIG : R; bitpos: [31:28]; default: 0; */ + +#define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000f +#define EFUSE_RD_FLASH_CRYPT_CONFIG_M (EFUSE_RD_FLASH_CRYPT_CONFIG_V << EFUSE_RD_FLASH_CRYPT_CONFIG_S) +#define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0x0000000f +#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28 + +/* EFUSE_RD_RESERVE_0_186 : RW; bitpos: [27:26]; default: 0; */ + +#define EFUSE_RD_RESERVE_0_186 0x00000003 +#define EFUSE_RD_RESERVE_0_186_M (EFUSE_RD_RESERVE_0_186_V << EFUSE_RD_RESERVE_0_186_S) +#define EFUSE_RD_RESERVE_0_186_V 0x00000003 +#define EFUSE_RD_RESERVE_0_186_S 26 + +/* EFUSE_RD_WAFER_VERSION_MINOR : R; bitpos: [25:24]; default: 0; */ + +#define EFUSE_RD_WAFER_VERSION_MINOR 0x00000003 +#define EFUSE_RD_WAFER_VERSION_MINOR_M (EFUSE_RD_WAFER_VERSION_MINOR_V << EFUSE_RD_WAFER_VERSION_MINOR_S) +#define EFUSE_RD_WAFER_VERSION_MINOR_V 0x00000003 +#define EFUSE_RD_WAFER_VERSION_MINOR_S 24 + +/* EFUSE_RD_VOL_LEVEL_HP_INV : R; bitpos: [23:22]; default: 0; */ + +#define EFUSE_RD_VOL_LEVEL_HP_INV 0x00000003 +#define EFUSE_RD_VOL_LEVEL_HP_INV_M (EFUSE_RD_VOL_LEVEL_HP_INV_V << EFUSE_RD_VOL_LEVEL_HP_INV_S) +#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x00000003 +#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 + +/* EFUSE_RD_RESERVE_0_181 : RW; bitpos: [21]; default: 0; */ + +#define EFUSE_RD_RESERVE_0_181 (BIT(21)) +#define EFUSE_RD_RESERVE_0_181_M (EFUSE_RD_RESERVE_0_181_V << EFUSE_RD_RESERVE_0_181_S) +#define EFUSE_RD_RESERVE_0_181_V 0x00000001 +#define EFUSE_RD_RESERVE_0_181_S 21 + +/* EFUSE_RD_CHIP_VER_REV2 : R; bitpos: [20]; default: 0; */ + +#define EFUSE_RD_CHIP_VER_REV2 (BIT(20)) +#define EFUSE_RD_CHIP_VER_REV2_M (EFUSE_RD_CHIP_VER_REV2_V << EFUSE_RD_CHIP_VER_REV2_S) +#define EFUSE_RD_CHIP_VER_REV2_V 0x00000001 +#define EFUSE_RD_CHIP_VER_REV2_S 20 + +/* EFUSE_RD_SPI_PAD_CONFIG_CS0 : R; bitpos: [19:15]; default: 0; */ + +#define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_M (EFUSE_RD_SPI_PAD_CONFIG_CS0_V << EFUSE_RD_SPI_PAD_CONFIG_CS0_S) +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_V 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_S 15 + +/* EFUSE_RD_SPI_PAD_CONFIG_D : R; bitpos: [14:10]; default: 0; */ + +#define EFUSE_RD_SPI_PAD_CONFIG_D 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_D_M (EFUSE_RD_SPI_PAD_CONFIG_D_V << EFUSE_RD_SPI_PAD_CONFIG_D_S) +#define EFUSE_RD_SPI_PAD_CONFIG_D_V 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_D_S 10 + +/* EFUSE_RD_SPI_PAD_CONFIG_Q : R; bitpos: [9:5]; default: 0; */ + +#define EFUSE_RD_SPI_PAD_CONFIG_Q 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_Q_M (EFUSE_RD_SPI_PAD_CONFIG_Q_V << EFUSE_RD_SPI_PAD_CONFIG_Q_S) +#define EFUSE_RD_SPI_PAD_CONFIG_Q_V 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_Q_S 5 + +/* EFUSE_RD_SPI_PAD_CONFIG_CLK : R; bitpos: [4:0]; default: 0; */ + +#define EFUSE_RD_SPI_PAD_CONFIG_CLK 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_CLK_M (EFUSE_RD_SPI_PAD_CONFIG_CLK_V << EFUSE_RD_SPI_PAD_CONFIG_CLK_S) +#define EFUSE_RD_SPI_PAD_CONFIG_CLK_V 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_CLK_S 0 + +/* EFUSE_BLK0_RDATA6_REG register */ + +#define EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x18) + +/* EFUSE_RD_RESERVE_0_203 : RW; bitpos: [31:11]; default: 0; */ + +#define EFUSE_RD_RESERVE_0_203 0x001fffff +#define EFUSE_RD_RESERVE_0_203_M (EFUSE_RD_RESERVE_0_203_V << EFUSE_RD_RESERVE_0_203_S) +#define EFUSE_RD_RESERVE_0_203_V 0x001fffff +#define EFUSE_RD_RESERVE_0_203_S 11 + +/* EFUSE_RD_KEY_STATUS : R; bitpos: [10]; default: 0; */ + +#define EFUSE_RD_KEY_STATUS (BIT(10)) +#define EFUSE_RD_KEY_STATUS_M (EFUSE_RD_KEY_STATUS_V << EFUSE_RD_KEY_STATUS_S) +#define EFUSE_RD_KEY_STATUS_V 0x00000001 +#define EFUSE_RD_KEY_STATUS_S 10 + +/* EFUSE_RD_DISABLE_DL_CACHE : R; bitpos: [9]; default: 0; */ + +#define EFUSE_RD_DISABLE_DL_CACHE (BIT(9)) +#define EFUSE_RD_DISABLE_DL_CACHE_M (EFUSE_RD_DISABLE_DL_CACHE_V << EFUSE_RD_DISABLE_DL_CACHE_S) +#define EFUSE_RD_DISABLE_DL_CACHE_V 0x00000001 +#define EFUSE_RD_DISABLE_DL_CACHE_S 9 + +/* EFUSE_RD_DISABLE_DL_DECRYPT : R; bitpos: [8]; default: 0; */ + +#define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8)) +#define EFUSE_RD_DISABLE_DL_DECRYPT_M (EFUSE_RD_DISABLE_DL_DECRYPT_V << EFUSE_RD_DISABLE_DL_DECRYPT_S) +#define EFUSE_RD_DISABLE_DL_DECRYPT_V 0x00000001 +#define EFUSE_RD_DISABLE_DL_DECRYPT_S 8 + +/* EFUSE_RD_DISABLE_DL_ENCRYPT : R; bitpos: [7]; default: 0; */ + +#define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7)) +#define EFUSE_RD_DISABLE_DL_ENCRYPT_M (EFUSE_RD_DISABLE_DL_ENCRYPT_V << EFUSE_RD_DISABLE_DL_ENCRYPT_S) +#define EFUSE_RD_DISABLE_DL_ENCRYPT_V 0x00000001 +#define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7 + +/* EFUSE_RD_JTAG_DISABLE : R; bitpos: [6]; default: 0; */ + +#define EFUSE_RD_JTAG_DISABLE (BIT(6)) +#define EFUSE_RD_JTAG_DISABLE_M (EFUSE_RD_JTAG_DISABLE_V << EFUSE_RD_JTAG_DISABLE_S) +#define EFUSE_RD_JTAG_DISABLE_V 0x00000001 +#define EFUSE_RD_JTAG_DISABLE_S 6 + +/* EFUSE_RD_ABS_DONE_1 : R; bitpos: [5]; default: 0; */ + +#define EFUSE_RD_ABS_DONE_1 (BIT(5)) +#define EFUSE_RD_ABS_DONE_1_M (EFUSE_RD_ABS_DONE_1_V << EFUSE_RD_ABS_DONE_1_S) +#define EFUSE_RD_ABS_DONE_1_V 0x00000001 +#define EFUSE_RD_ABS_DONE_1_S 5 + +/* EFUSE_RD_ABS_DONE_0 : R; bitpos: [4]; default: 0; */ + +#define EFUSE_RD_ABS_DONE_0 (BIT(4)) +#define EFUSE_RD_ABS_DONE_0_M (EFUSE_RD_ABS_DONE_0_V << EFUSE_RD_ABS_DONE_0_S) +#define EFUSE_RD_ABS_DONE_0_V 0x00000001 +#define EFUSE_RD_ABS_DONE_0_S 4 + +/* EFUSE_RD_DISABLE_SDIO_HOST : R; bitpos: [3]; default: 0; */ + +#define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3)) +#define EFUSE_RD_DISABLE_SDIO_HOST_M (EFUSE_RD_DISABLE_SDIO_HOST_V << EFUSE_RD_DISABLE_SDIO_HOST_S) +#define EFUSE_RD_DISABLE_SDIO_HOST_V 0x00000001 +#define EFUSE_RD_DISABLE_SDIO_HOST_S 3 + +/* EFUSE_RD_CONSOLE_DEBUG_DISABLE : R; bitpos: [2]; default: 0; */ + +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE (BIT(2)) +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_M (EFUSE_RD_CONSOLE_DEBUG_DISABLE_V << EFUSE_RD_CONSOLE_DEBUG_DISABLE_S) +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_V 0x00000001 +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_S 2 + +/* EFUSE_RD_CODING_SCHEME : R; bitpos: [1:0]; default: 0; */ + +#define EFUSE_RD_CODING_SCHEME 0x00000003 +#define EFUSE_RD_CODING_SCHEME_M (EFUSE_RD_CODING_SCHEME_V << EFUSE_RD_CODING_SCHEME_S) +#define EFUSE_RD_CODING_SCHEME_V 0x00000003 +#define EFUSE_RD_CODING_SCHEME_S 0 + +/* EFUSE_BLK0_WDATA0_REG register */ + +#define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x1c) + +/* EFUSE_FLASH_CRYPT_CNT : RW; bitpos: [26:20]; default: 0; */ + +#define EFUSE_FLASH_CRYPT_CNT 0x0000007f +#define EFUSE_FLASH_CRYPT_CNT_M (EFUSE_FLASH_CRYPT_CNT_V << EFUSE_FLASH_CRYPT_CNT_S) +#define EFUSE_FLASH_CRYPT_CNT_V 0x0000007f +#define EFUSE_FLASH_CRYPT_CNT_S 20 + +/* EFUSE_RD_DIS : RW; bitpos: [19:16]; default: 0; */ + +#define EFUSE_RD_DIS 0x0000000f +#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) +#define EFUSE_RD_DIS_V 0x0000000f +#define EFUSE_RD_DIS_S 16 + +/* EFUSE_WR_DIS : RW; bitpos: [15:0]; default: 0; */ + +#define EFUSE_WR_DIS 0x0000ffff +#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) +#define EFUSE_WR_DIS_V 0x0000ffff +#define EFUSE_WR_DIS_S 0 + +/* EFUSE_BLK0_WDATA1_REG register */ + +#define EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x20) + +/* EFUSE_WIFI_MAC_CRC_LOW : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_WIFI_MAC_CRC_LOW 0xffffffff +#define EFUSE_WIFI_MAC_CRC_LOW_M (EFUSE_WIFI_MAC_CRC_LOW_V << EFUSE_WIFI_MAC_CRC_LOW_S) +#define EFUSE_WIFI_MAC_CRC_LOW_V 0xffffffff +#define EFUSE_WIFI_MAC_CRC_LOW_S 0 + +/* EFUSE_BLK0_WDATA2_REG register */ + +#define EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x24) + +/* EFUSE_WIFI_MAC_CRC_HIGH : RW; bitpos: [23:0]; default: 0; */ + +#define EFUSE_WIFI_MAC_CRC_HIGH 0x00ffffff +#define EFUSE_WIFI_MAC_CRC_HIGH_M (EFUSE_WIFI_MAC_CRC_HIGH_V << EFUSE_WIFI_MAC_CRC_HIGH_S) +#define EFUSE_WIFI_MAC_CRC_HIGH_V 0x00ffffff +#define EFUSE_WIFI_MAC_CRC_HIGH_S 0 + +/* EFUSE_BLK0_WDATA3_REG register */ + +#define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x28) + +/* EFUSE_RESERVE_0_112 : RW; bitpos: [31:16]; default: 0; */ + +#define EFUSE_RESERVE_0_112 0x0000ffff +#define EFUSE_RESERVE_0_112_M (EFUSE_RESERVE_0_112_V << EFUSE_RESERVE_0_112_S) +#define EFUSE_RESERVE_0_112_V 0x0000ffff +#define EFUSE_RESERVE_0_112_S 16 + +/* EFUSE_CHIP_VER_REV1 : RW; bitpos: [15]; default: 0; */ + +#define EFUSE_CHIP_VER_REV1 (BIT(15)) +#define EFUSE_CHIP_VER_REV1_M (EFUSE_CHIP_VER_REV1_V << EFUSE_CHIP_VER_REV1_S) +#define EFUSE_CHIP_VER_REV1_V 0x00000001 +#define EFUSE_CHIP_VER_REV1_S 15 + +/* EFUSE_BLK3_PART_RESERVE : RW; bitpos: [14]; default: 0; */ + +#define EFUSE_BLK3_PART_RESERVE (BIT(14)) +#define EFUSE_BLK3_PART_RESERVE_M (EFUSE_BLK3_PART_RESERVE_V << EFUSE_BLK3_PART_RESERVE_S) +#define EFUSE_BLK3_PART_RESERVE_V 0x00000001 +#define EFUSE_BLK3_PART_RESERVE_S 14 + +/* EFUSE_CHIP_CPU_FREQ_RATED : RW; bitpos: [13]; default: 0; */ + +#define EFUSE_CHIP_CPU_FREQ_RATED (BIT(13)) +#define EFUSE_CHIP_CPU_FREQ_RATED_M (EFUSE_CHIP_CPU_FREQ_RATED_V << EFUSE_CHIP_CPU_FREQ_RATED_S) +#define EFUSE_CHIP_CPU_FREQ_RATED_V 0x00000001 +#define EFUSE_CHIP_CPU_FREQ_RATED_S 13 + +/* EFUSE_CHIP_CPU_FREQ_LOW : RW; bitpos: [12]; default: 0; */ + +#define EFUSE_CHIP_CPU_FREQ_LOW (BIT(12)) +#define EFUSE_CHIP_CPU_FREQ_LOW_M (EFUSE_CHIP_CPU_FREQ_LOW_V << EFUSE_CHIP_CPU_FREQ_LOW_S) +#define EFUSE_CHIP_CPU_FREQ_LOW_V 0x00000001 +#define EFUSE_CHIP_CPU_FREQ_LOW_S 12 + +/* EFUSE_CHIP_PACKAGE : RW; bitpos: [11:9]; default: 0; */ + +#define EFUSE_CHIP_PACKAGE 0x00000007 +#define EFUSE_CHIP_PACKAGE_M (EFUSE_CHIP_PACKAGE_V << EFUSE_CHIP_PACKAGE_S) +#define EFUSE_CHIP_PACKAGE_V 0x00000007 +#define EFUSE_CHIP_PACKAGE_S 9 + +/* EFUSE_SPI_PAD_CONFIG_HD : R; bitpos: [8:4]; default: 0; */ + +#define EFUSE_SPI_PAD_CONFIG_HD 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_HD_M (EFUSE_SPI_PAD_CONFIG_HD_V << EFUSE_SPI_PAD_CONFIG_HD_S) +#define EFUSE_SPI_PAD_CONFIG_HD_V 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_HD_S 4 + +/* EFUSE_DIS_CACHE : R; bitpos: [3]; default: 0; */ + +#define EFUSE_DIS_CACHE (BIT(3)) +#define EFUSE_DIS_CACHE_M (EFUSE_DIS_CACHE_V << EFUSE_DIS_CACHE_S) +#define EFUSE_DIS_CACHE_V 0x00000001 +#define EFUSE_DIS_CACHE_S 3 + +/* EFUSE_CHIP_PACKAGE_4BIT : R; bitpos: [2]; default: 0; */ + +#define EFUSE_CHIP_PACKAGE_4BIT (BIT(2)) +#define EFUSE_CHIP_PACKAGE_4BIT_M (EFUSE_CHIP_PACKAGE_4BIT_V << EFUSE_CHIP_PACKAGE_4BIT_S) +#define EFUSE_CHIP_PACKAGE_4BIT_V 0x00000001 +#define EFUSE_CHIP_PACKAGE_4BIT_S 2 + +/* EFUSE_DISABLE_BT : R; bitpos: [1]; default: 0; */ + +#define EFUSE_DISABLE_BT (BIT(1)) +#define EFUSE_DISABLE_BT_M (EFUSE_DISABLE_BT_V << EFUSE_DISABLE_BT_S) +#define EFUSE_DISABLE_BT_V 0x00000001 +#define EFUSE_DISABLE_BT_S 1 + +/* EFUSE_DISABLE_APP_CPU : R; bitpos: [0]; default: 0; */ + +#define EFUSE_DISABLE_APP_CPU (BIT(0)) +#define EFUSE_DISABLE_APP_CPU_M (EFUSE_DISABLE_APP_CPU_V << EFUSE_DISABLE_APP_CPU_S) +#define EFUSE_DISABLE_APP_CPU_V 0x00000001 +#define EFUSE_DISABLE_APP_CPU_S 0 + +/* EFUSE_BLK0_WDATA4_REG register */ + +#define EFUSE_BLK0_WDATA4_REG (DR_REG_EFUSE_BASE + 0x2c) + +/* EFUSE_RESERVE_0_145 : RW; bitpos: [31:17]; default: 0; */ + +#define EFUSE_RESERVE_0_145 0x00007fff +#define EFUSE_RESERVE_0_145_M (EFUSE_RESERVE_0_145_V << EFUSE_RESERVE_0_145_S) +#define EFUSE_RESERVE_0_145_V 0x00007fff +#define EFUSE_RESERVE_0_145_S 17 + +/* EFUSE_XPD_SDIO_FORCE : R; bitpos: [16]; default: 0; */ + +#define EFUSE_XPD_SDIO_FORCE (BIT(16)) +#define EFUSE_XPD_SDIO_FORCE_M (EFUSE_XPD_SDIO_FORCE_V << EFUSE_XPD_SDIO_FORCE_S) +#define EFUSE_XPD_SDIO_FORCE_V 0x00000001 +#define EFUSE_XPD_SDIO_FORCE_S 16 + +/* EFUSE_XPD_SDIO_TIEH : R; bitpos: [15]; default: 0; */ + +#define EFUSE_XPD_SDIO_TIEH (BIT(15)) +#define EFUSE_XPD_SDIO_TIEH_M (EFUSE_XPD_SDIO_TIEH_V << EFUSE_XPD_SDIO_TIEH_S) +#define EFUSE_XPD_SDIO_TIEH_V 0x00000001 +#define EFUSE_XPD_SDIO_TIEH_S 15 + +/* EFUSE_XPD_SDIO_REG : R; bitpos: [14]; default: 0; */ + +#define EFUSE_XPD_SDIO_REG (BIT(14)) +#define EFUSE_XPD_SDIO_REG_M (EFUSE_XPD_SDIO_REG_V << EFUSE_XPD_SDIO_REG_S) +#define EFUSE_XPD_SDIO_REG_V 0x00000001 +#define EFUSE_XPD_SDIO_REG_S 14 + +/* EFUSE_RESERVE_0_141 : RW; bitpos: [13]; default: 0; */ + +#define EFUSE_RESERVE_0_141 (BIT(13)) +#define EFUSE_RESERVE_0_141_M (EFUSE_RESERVE_0_141_V << EFUSE_RESERVE_0_141_S) +#define EFUSE_RESERVE_0_141_V 0x00000001 +#define EFUSE_RESERVE_0_141_S 13 + +/* EFUSE_ADC_VREF : RW; bitpos: [12:8]; default: 0; */ + +#define EFUSE_ADC_VREF 0x0000001f +#define EFUSE_ADC_VREF_M (EFUSE_ADC_VREF_V << EFUSE_ADC_VREF_S) +#define EFUSE_ADC_VREF_V 0x0000001f +#define EFUSE_ADC_VREF_S 8 + +/* EFUSE_CLK8M_FREQ : R; bitpos: [7:0]; default: 0; */ + +#define EFUSE_CLK8M_FREQ 0x000000ff +#define EFUSE_CLK8M_FREQ_M (EFUSE_CLK8M_FREQ_V << EFUSE_CLK8M_FREQ_S) +#define EFUSE_CLK8M_FREQ_V 0x000000ff +#define EFUSE_CLK8M_FREQ_S 0 + +/* EFUSE_BLK0_WDATA5_REG register */ + +#define EFUSE_BLK0_WDATA5_REG (DR_REG_EFUSE_BASE + 0x30) + +/* EFUSE_FLASH_CRYPT_CONFIG : R; bitpos: [31:28]; default: 0; */ + +#define EFUSE_FLASH_CRYPT_CONFIG 0x0000000f +#define EFUSE_FLASH_CRYPT_CONFIG_M (EFUSE_FLASH_CRYPT_CONFIG_V << EFUSE_FLASH_CRYPT_CONFIG_S) +#define EFUSE_FLASH_CRYPT_CONFIG_V 0x0000000f +#define EFUSE_FLASH_CRYPT_CONFIG_S 28 + +/* EFUSE_RESERVE_0_186 : RW; bitpos: [27:26]; default: 0; */ + +#define EFUSE_RESERVE_0_186 0x00000003 +#define EFUSE_RESERVE_0_186_M (EFUSE_RESERVE_0_186_V << EFUSE_RESERVE_0_186_S) +#define EFUSE_RESERVE_0_186_V 0x00000003 +#define EFUSE_RESERVE_0_186_S 26 + +/* EFUSE_WAFER_VERSION_MINOR : R; bitpos: [25:24]; default: 0; */ + +#define EFUSE_WAFER_VERSION_MINOR 0x00000003 +#define EFUSE_WAFER_VERSION_MINOR_M (EFUSE_WAFER_VERSION_MINOR_V << EFUSE_WAFER_VERSION_MINOR_S) +#define EFUSE_WAFER_VERSION_MINOR_V 0x00000003 +#define EFUSE_WAFER_VERSION_MINOR_S 24 + +/* EFUSE_VOL_LEVEL_HP_INV : R; bitpos: [23:22]; default: 0; */ + +#define EFUSE_VOL_LEVEL_HP_INV 0x00000003 +#define EFUSE_VOL_LEVEL_HP_INV_M (EFUSE_VOL_LEVEL_HP_INV_V << EFUSE_VOL_LEVEL_HP_INV_S) +#define EFUSE_VOL_LEVEL_HP_INV_V 0x00000003 +#define EFUSE_VOL_LEVEL_HP_INV_S 22 + +/* EFUSE_RESERVE_0_181 : RW; bitpos: [21]; default: 0; */ + +#define EFUSE_RESERVE_0_181 (BIT(21)) +#define EFUSE_RESERVE_0_181_M (EFUSE_RESERVE_0_181_V << EFUSE_RESERVE_0_181_S) +#define EFUSE_RESERVE_0_181_V 0x00000001 +#define EFUSE_RESERVE_0_181_S 21 + +/* EFUSE_CHIP_VER_REV2 : R; bitpos: [20]; default: 0; */ + +#define EFUSE_CHIP_VER_REV2 (BIT(20)) +#define EFUSE_CHIP_VER_REV2_M (EFUSE_CHIP_VER_REV2_V << EFUSE_CHIP_VER_REV2_S) +#define EFUSE_CHIP_VER_REV2_V 0x00000001 +#define EFUSE_CHIP_VER_REV2_S 20 + +/* EFUSE_SPI_PAD_CONFIG_CS0 : R; bitpos: [19:15]; default: 0; */ + +#define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_CS0_M (EFUSE_SPI_PAD_CONFIG_CS0_V << EFUSE_SPI_PAD_CONFIG_CS0_S) +#define EFUSE_SPI_PAD_CONFIG_CS0_V 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_CS0_S 15 + +/* EFUSE_SPI_PAD_CONFIG_D : R; bitpos: [14:10]; default: 0; */ + +#define EFUSE_SPI_PAD_CONFIG_D 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_D_M (EFUSE_SPI_PAD_CONFIG_D_V << EFUSE_SPI_PAD_CONFIG_D_S) +#define EFUSE_SPI_PAD_CONFIG_D_V 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_D_S 10 + +/* EFUSE_SPI_PAD_CONFIG_Q : R; bitpos: [9:5]; default: 0; */ + +#define EFUSE_SPI_PAD_CONFIG_Q 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_Q_M (EFUSE_SPI_PAD_CONFIG_Q_V << EFUSE_SPI_PAD_CONFIG_Q_S) +#define EFUSE_SPI_PAD_CONFIG_Q_V 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_Q_S 5 + +/* EFUSE_SPI_PAD_CONFIG_CLK : R; bitpos: [4:0]; default: 0; */ + +#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_CLK_M (EFUSE_SPI_PAD_CONFIG_CLK_V << EFUSE_SPI_PAD_CONFIG_CLK_S) +#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_CLK_S 0 + +/* EFUSE_BLK0_WDATA6_REG register */ + +#define EFUSE_BLK0_WDATA6_REG (DR_REG_EFUSE_BASE + 0x34) + +/* EFUSE_KEY_STATUS : RW; bitpos: [10]; default: 0; */ + +#define EFUSE_KEY_STATUS (BIT(10)) +#define EFUSE_KEY_STATUS_M (EFUSE_KEY_STATUS_V << EFUSE_KEY_STATUS_S) +#define EFUSE_KEY_STATUS_V 0x00000001 +#define EFUSE_KEY_STATUS_S 10 + +/* EFUSE_DISABLE_DL_CACHE : RW; bitpos: [9]; default: 0; */ + +#define EFUSE_DISABLE_DL_CACHE (BIT(9)) +#define EFUSE_DISABLE_DL_CACHE_M (EFUSE_DISABLE_DL_CACHE_V << EFUSE_DISABLE_DL_CACHE_S) +#define EFUSE_DISABLE_DL_CACHE_V 0x00000001 +#define EFUSE_DISABLE_DL_CACHE_S 9 + +/* EFUSE_DISABLE_DL_DECRYPT : RW; bitpos: [8]; default: 0; */ + +#define EFUSE_DISABLE_DL_DECRYPT (BIT(8)) +#define EFUSE_DISABLE_DL_DECRYPT_M (EFUSE_DISABLE_DL_DECRYPT_V << EFUSE_DISABLE_DL_DECRYPT_S) +#define EFUSE_DISABLE_DL_DECRYPT_V 0x00000001 +#define EFUSE_DISABLE_DL_DECRYPT_S 8 + +/* EFUSE_DISABLE_DL_ENCRYPT : RW; bitpos: [7]; default: 0; */ + +#define EFUSE_DISABLE_DL_ENCRYPT (BIT(7)) +#define EFUSE_DISABLE_DL_ENCRYPT_M (EFUSE_DISABLE_DL_ENCRYPT_V << EFUSE_DISABLE_DL_ENCRYPT_S) +#define EFUSE_DISABLE_DL_ENCRYPT_V 0x00000001 +#define EFUSE_DISABLE_DL_ENCRYPT_S 7 + +/* EFUSE_DISABLE_JTAG : RW; bitpos: [6]; default: 0; */ + +#define EFUSE_DISABLE_JTAG (BIT(6)) +#define EFUSE_DISABLE_JTAG_M (EFUSE_DISABLE_JTAG_V << EFUSE_DISABLE_JTAG_S) +#define EFUSE_DISABLE_JTAG_V 0x00000001 +#define EFUSE_DISABLE_JTAG_S 6 + +/* EFUSE_ABS_DONE_1 : RW; bitpos: [5]; default: 0; */ + +#define EFUSE_ABS_DONE_1 (BIT(5)) +#define EFUSE_ABS_DONE_1_M (EFUSE_ABS_DONE_1_V << EFUSE_ABS_DONE_1_S) +#define EFUSE_ABS_DONE_1_V 0x00000001 +#define EFUSE_ABS_DONE_1_S 5 + +/* EFUSE_ABS_DONE_0 : RW; bitpos: [4]; default: 0; */ + +#define EFUSE_ABS_DONE_0 (BIT(4)) +#define EFUSE_ABS_DONE_0_M (EFUSE_ABS_DONE_0_V << EFUSE_ABS_DONE_0_S) +#define EFUSE_ABS_DONE_0_V 0x00000001 +#define EFUSE_ABS_DONE_0_S 4 + +/* EFUSE_DISABLE_SDIO_HOST : RW; bitpos: [3]; default: 0; */ + +#define EFUSE_DISABLE_SDIO_HOST (BIT(3)) +#define EFUSE_DISABLE_SDIO_HOST_M (EFUSE_DISABLE_SDIO_HOST_V << EFUSE_DISABLE_SDIO_HOST_S) +#define EFUSE_DISABLE_SDIO_HOST_V 0x00000001 +#define EFUSE_DISABLE_SDIO_HOST_S 3 + +/* EFUSE_CONSOLE_DEBUG_DISABLE : RW; bitpos: [2]; default: 0; */ + +#define EFUSE_CONSOLE_DEBUG_DISABLE (BIT(2)) +#define EFUSE_CONSOLE_DEBUG_DISABLE_M (EFUSE_CONSOLE_DEBUG_DISABLE_V << EFUSE_CONSOLE_DEBUG_DISABLE_S) +#define EFUSE_CONSOLE_DEBUG_DISABLE_V 0x00000001 +#define EFUSE_CONSOLE_DEBUG_DISABLE_S 2 + +/* EFUSE_CODING_SCHEME : RW; bitpos: [1:0]; default: 0; */ + +#define EFUSE_CODING_SCHEME 0x00000003 +#define EFUSE_CODING_SCHEME_M (EFUSE_CODING_SCHEME_V << EFUSE_CODING_SCHEME_S) +#define EFUSE_CODING_SCHEME_V 0x00000003 +#define EFUSE_CODING_SCHEME_S 0 + +/* EFUSE_BLK1_RDATA0_REG register */ + +#define EFUSE_BLK1_RDATA0_REG (DR_REG_EFUSE_BASE + 0x38) + +/* EFUSE_RD_BLOCK1 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLOCK1 0xffffffff +#define EFUSE_RD_BLOCK1_M (EFUSE_RD_BLOCK1_V << EFUSE_RD_BLOCK1_S) +#define EFUSE_RD_BLOCK1_V 0xffffffff +#define EFUSE_RD_BLOCK1_S 0 + +/* EFUSE_BLK1_RDATA1_REG register */ + +#define EFUSE_BLK1_RDATA1_REG (DR_REG_EFUSE_BASE + 0x3c) + +/* EFUSE_RD_BLOCK1_1 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLOCK1_1 0xffffffff +#define EFUSE_RD_BLOCK1_1_M (EFUSE_RD_BLOCK1_1_V << EFUSE_RD_BLOCK1_1_S) +#define EFUSE_RD_BLOCK1_1_V 0xffffffff +#define EFUSE_RD_BLOCK1_1_S 0 + +/* EFUSE_BLK1_RDATA2_REG register */ + +#define EFUSE_BLK1_RDATA2_REG (DR_REG_EFUSE_BASE + 0x40) + +/* EFUSE_RD_BLOCK1_2 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLOCK1_2 0xffffffff +#define EFUSE_RD_BLOCK1_2_M (EFUSE_RD_BLOCK1_2_V << EFUSE_RD_BLOCK1_2_S) +#define EFUSE_RD_BLOCK1_2_V 0xffffffff +#define EFUSE_RD_BLOCK1_2_S 0 + +/* EFUSE_BLK1_RDATA3_REG register */ + +#define EFUSE_BLK1_RDATA3_REG (DR_REG_EFUSE_BASE + 0x44) + +/* EFUSE_RD_BLOCK1_3 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLOCK1_3 0xffffffff +#define EFUSE_RD_BLOCK1_3_M (EFUSE_RD_BLOCK1_3_V << EFUSE_RD_BLOCK1_3_S) +#define EFUSE_RD_BLOCK1_3_V 0xffffffff +#define EFUSE_RD_BLOCK1_3_S 0 + +/* EFUSE_BLK1_RDATA4_REG register */ + +#define EFUSE_BLK1_RDATA4_REG (DR_REG_EFUSE_BASE + 0x48) + +/* EFUSE_RD_BLOCK1_4 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLOCK1_4 0xffffffff +#define EFUSE_RD_BLOCK1_4_M (EFUSE_RD_BLOCK1_4_V << EFUSE_RD_BLOCK1_4_S) +#define EFUSE_RD_BLOCK1_4_V 0xffffffff +#define EFUSE_RD_BLOCK1_4_S 0 + +/* EFUSE_BLK1_RDATA5_REG register */ + +#define EFUSE_BLK1_RDATA5_REG (DR_REG_EFUSE_BASE + 0x4c) + +/* EFUSE_RD_BLOCK1_5 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLOCK1_5 0xffffffff +#define EFUSE_RD_BLOCK1_5_M (EFUSE_RD_BLOCK1_5_V << EFUSE_RD_BLOCK1_5_S) +#define EFUSE_RD_BLOCK1_5_V 0xffffffff +#define EFUSE_RD_BLOCK1_5_S 0 + +/* EFUSE_BLK1_RDATA6_REG register */ + +#define EFUSE_BLK1_RDATA6_REG (DR_REG_EFUSE_BASE + 0x50) + +/* EFUSE_RD_BLOCK1_6 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLOCK1_6 0xffffffff +#define EFUSE_RD_BLOCK1_6_M (EFUSE_RD_BLOCK1_6_V << EFUSE_RD_BLOCK1_6_S) +#define EFUSE_RD_BLOCK1_6_V 0xffffffff +#define EFUSE_RD_BLOCK1_6_S 0 + +/* EFUSE_BLK1_RDATA7_REG register */ + +#define EFUSE_BLK1_RDATA7_REG (DR_REG_EFUSE_BASE + 0x54) + +/* EFUSE_RD_BLOCK1_7 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLOCK1_7 0xffffffff +#define EFUSE_RD_BLOCK1_7_M (EFUSE_RD_BLOCK1_7_V << EFUSE_RD_BLOCK1_7_S) +#define EFUSE_RD_BLOCK1_7_V 0xffffffff +#define EFUSE_RD_BLOCK1_7_S 0 + +/* EFUSE_BLK2_RDATA0_REG register */ + +#define EFUSE_BLK2_RDATA0_REG (DR_REG_EFUSE_BASE + 0x58) + +/* EFUSE_RD_BLOCK2 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLOCK2 0xffffffff +#define EFUSE_RD_BLOCK2_M (EFUSE_RD_BLOCK2_V << EFUSE_RD_BLOCK2_S) +#define EFUSE_RD_BLOCK2_V 0xffffffff +#define EFUSE_RD_BLOCK2_S 0 + +/* EFUSE_BLK2_RDATA1_REG register */ + +#define EFUSE_BLK2_RDATA1_REG (DR_REG_EFUSE_BASE + 0x5c) + +/* EFUSE_RD_BLOCK2_1 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLOCK2_1 0xffffffff +#define EFUSE_RD_BLOCK2_1_M (EFUSE_RD_BLOCK2_1_V << EFUSE_RD_BLOCK2_1_S) +#define EFUSE_RD_BLOCK2_1_V 0xffffffff +#define EFUSE_RD_BLOCK2_1_S 0 + +/* EFUSE_BLK2_RDATA2_REG register */ + +#define EFUSE_BLK2_RDATA2_REG (DR_REG_EFUSE_BASE + 0x60) + +/* EFUSE_RD_BLOCK2_2 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLOCK2_2 0xffffffff +#define EFUSE_RD_BLOCK2_2_M (EFUSE_RD_BLOCK2_2_V << EFUSE_RD_BLOCK2_2_S) +#define EFUSE_RD_BLOCK2_2_V 0xffffffff +#define EFUSE_RD_BLOCK2_2_S 0 + +/* EFUSE_BLK2_RDATA3_REG register */ + +#define EFUSE_BLK2_RDATA3_REG (DR_REG_EFUSE_BASE + 0x64) + +/* EFUSE_RD_BLOCK2_3 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLOCK2_3 0xffffffff +#define EFUSE_RD_BLOCK2_3_M (EFUSE_RD_BLOCK2_3_V << EFUSE_RD_BLOCK2_3_S) +#define EFUSE_RD_BLOCK2_3_V 0xffffffff +#define EFUSE_RD_BLOCK2_3_S 0 + +/* EFUSE_BLK2_RDATA4_REG register */ + +#define EFUSE_BLK2_RDATA4_REG (DR_REG_EFUSE_BASE + 0x68) + +/* EFUSE_RD_BLOCK2_4 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLOCK2_4 0xffffffff +#define EFUSE_RD_BLOCK2_4_M (EFUSE_RD_BLOCK2_4_V << EFUSE_RD_BLOCK2_4_S) +#define EFUSE_RD_BLOCK2_4_V 0xffffffff +#define EFUSE_RD_BLOCK2_4_S 0 + +/* EFUSE_BLK2_RDATA5_REG register */ + +#define EFUSE_BLK2_RDATA5_REG (DR_REG_EFUSE_BASE + 0x6c) + +/* EFUSE_RD_BLOCK2_5 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLOCK2_5 0xffffffff +#define EFUSE_RD_BLOCK2_5_M (EFUSE_RD_BLOCK2_5_V << EFUSE_RD_BLOCK2_5_S) +#define EFUSE_RD_BLOCK2_5_V 0xffffffff +#define EFUSE_RD_BLOCK2_5_S 0 + +/* EFUSE_BLK2_RDATA6_REG register */ + +#define EFUSE_BLK2_RDATA6_REG (DR_REG_EFUSE_BASE + 0x70) + +/* EFUSE_RD_BLOCK2_6 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLOCK2_6 0xffffffff +#define EFUSE_RD_BLOCK2_6_M (EFUSE_RD_BLOCK2_6_V << EFUSE_RD_BLOCK2_6_S) +#define EFUSE_RD_BLOCK2_6_V 0xffffffff +#define EFUSE_RD_BLOCK2_6_S 0 + +/* EFUSE_BLK2_RDATA7_REG register */ + +#define EFUSE_BLK2_RDATA7_REG (DR_REG_EFUSE_BASE + 0x74) + +/* EFUSE_RD_BLOCK2_7 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLOCK2_7 0xffffffff +#define EFUSE_RD_BLOCK2_7_M (EFUSE_RD_BLOCK2_7_V << EFUSE_RD_BLOCK2_7_S) +#define EFUSE_RD_BLOCK2_7_V 0xffffffff +#define EFUSE_RD_BLOCK2_7_S 0 + +/* EFUSE_BLK3_RDATA0_REG register */ + +#define EFUSE_BLK3_RDATA0_REG (DR_REG_EFUSE_BASE + 0x78) + +/* EFUSE_RD_CUSTOM_MAC : R; bitpos: [31:8]; default: 0; */ + +#define EFUSE_RD_CUSTOM_MAC 0x00ffffff +#define EFUSE_RD_CUSTOM_MAC_M (EFUSE_RD_CUSTOM_MAC_V << EFUSE_RD_CUSTOM_MAC_S) +#define EFUSE_RD_CUSTOM_MAC_V 0x00ffffff +#define EFUSE_RD_CUSTOM_MAC_S 8 + +/* EFUSE_RD_CUSTOM_MAC_CRC : R; bitpos: [7:0]; default: 0; */ + +#define EFUSE_RD_CUSTOM_MAC_CRC 0x000000ff +#define EFUSE_RD_CUSTOM_MAC_CRC_M (EFUSE_RD_CUSTOM_MAC_CRC_V << EFUSE_RD_CUSTOM_MAC_CRC_S) +#define EFUSE_RD_CUSTOM_MAC_CRC_V 0x000000ff +#define EFUSE_RD_CUSTOM_MAC_CRC_S 0 + +/* EFUSE_BLK3_RDATA1_REG register */ + +#define EFUSE_BLK3_RDATA1_REG (DR_REG_EFUSE_BASE + 0x7c) + +/* EFUSE_RESERVED_3_56 : R; bitpos: [31:24]; default: 0; */ + +#define EFUSE_RESERVED_3_56 0x000000ff +#define EFUSE_RESERVED_3_56_M (EFUSE_RESERVED_3_56_V << EFUSE_RESERVED_3_56_S) +#define EFUSE_RESERVED_3_56_V 0x000000ff +#define EFUSE_RESERVED_3_56_S 24 + +/* EFUSE_RD_CUSTOM_MAC_1 : R; bitpos: [23:0]; default: 0; */ + +#define EFUSE_RD_CUSTOM_MAC_1 0x00ffffff +#define EFUSE_RD_CUSTOM_MAC_1_M (EFUSE_RD_CUSTOM_MAC_1_V << EFUSE_RD_CUSTOM_MAC_1_S) +#define EFUSE_RD_CUSTOM_MAC_1_V 0x00ffffff +#define EFUSE_RD_CUSTOM_MAC_1_S 0 + +/* EFUSE_BLK3_RDATA2_REG register */ + +#define EFUSE_BLK3_RDATA2_REG (DR_REG_EFUSE_BASE + 0x80) + +/* EFUSE_RD_BLK3_RESERVED_2 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLK3_RESERVED_2 0xffffffff +#define EFUSE_RD_BLK3_RESERVED_2_M (EFUSE_RD_BLK3_RESERVED_2_V << EFUSE_RD_BLK3_RESERVED_2_S) +#define EFUSE_RD_BLK3_RESERVED_2_V 0xffffffff +#define EFUSE_RD_BLK3_RESERVED_2_S 0 + +/* EFUSE_BLK3_RDATA3_REG register */ + +#define EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x84) + +/* EFUSE_RD_ADC2_TP_HIGH : RW; bitpos: [31:23]; default: 0; */ + +#define EFUSE_RD_ADC2_TP_HIGH 0x000001ff +#define EFUSE_RD_ADC2_TP_HIGH_M (EFUSE_RD_ADC2_TP_HIGH_V << EFUSE_RD_ADC2_TP_HIGH_S) +#define EFUSE_RD_ADC2_TP_HIGH_V 0x000001ff +#define EFUSE_RD_ADC2_TP_HIGH_S 23 + +/* EFUSE_RD_ADC2_TP_LOW : RW; bitpos: [22:16]; default: 0; */ + +#define EFUSE_RD_ADC2_TP_LOW 0x0000007f +#define EFUSE_RD_ADC2_TP_LOW_M (EFUSE_RD_ADC2_TP_LOW_V << EFUSE_RD_ADC2_TP_LOW_S) +#define EFUSE_RD_ADC2_TP_LOW_V 0x0000007f +#define EFUSE_RD_ADC2_TP_LOW_S 16 + +/* EFUSE_RD_ADC1_TP_HIGH : RW; bitpos: [15:7]; default: 0; */ + +#define EFUSE_RD_ADC1_TP_HIGH 0x000001ff +#define EFUSE_RD_ADC1_TP_HIGH_M (EFUSE_RD_ADC1_TP_HIGH_V << EFUSE_RD_ADC1_TP_HIGH_S) +#define EFUSE_RD_ADC1_TP_HIGH_V 0x000001ff +#define EFUSE_RD_ADC1_TP_HIGH_S 7 + +/* EFUSE_RD_ADC1_TP_LOW : RW; bitpos: [6:0]; default: 0; */ + +#define EFUSE_RD_ADC1_TP_LOW 0x0000007f +#define EFUSE_RD_ADC1_TP_LOW_M (EFUSE_RD_ADC1_TP_LOW_V << EFUSE_RD_ADC1_TP_LOW_S) +#define EFUSE_RD_ADC1_TP_LOW_V 0x0000007f +#define EFUSE_RD_ADC1_TP_LOW_S 0 + +/* EFUSE_BLK3_RDATA4_REG register */ + +#define EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x88) + +/* EFUSE_RD_SECURE_VERSION : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_SECURE_VERSION 0xffffffff +#define EFUSE_RD_SECURE_VERSION_M (EFUSE_RD_SECURE_VERSION_V << EFUSE_RD_SECURE_VERSION_S) +#define EFUSE_RD_SECURE_VERSION_V 0xffffffff +#define EFUSE_RD_SECURE_VERSION_S 0 + +/* EFUSE_BLK3_RDATA5_REG register */ + +#define EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x8c) + +/* EFUSE_RD_MAC_VERSION : R; bitpos: [31:24]; default: 0; */ + +#define EFUSE_RD_MAC_VERSION 0x000000ff +#define EFUSE_RD_MAC_VERSION_M (EFUSE_RD_MAC_VERSION_V << EFUSE_RD_MAC_VERSION_S) +#define EFUSE_RD_MAC_VERSION_V 0x000000ff +#define EFUSE_RD_MAC_VERSION_S 24 + +/* EFUSE_RESERVED_3_160 : R; bitpos: [23:0]; default: 0; */ + +#define EFUSE_RESERVED_3_160 0x00ffffff +#define EFUSE_RESERVED_3_160_M (EFUSE_RESERVED_3_160_V << EFUSE_RESERVED_3_160_S) +#define EFUSE_RESERVED_3_160_V 0x00ffffff +#define EFUSE_RESERVED_3_160_S 0 + +/* EFUSE_BLK3_RDATA6_REG register */ + +#define EFUSE_BLK3_RDATA6_REG (DR_REG_EFUSE_BASE + 0x90) + +/* EFUSE_RD_BLK3_RESERVED_6 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLK3_RESERVED_6 0xffffffff +#define EFUSE_RD_BLK3_RESERVED_6_M (EFUSE_RD_BLK3_RESERVED_6_V << EFUSE_RD_BLK3_RESERVED_6_S) +#define EFUSE_RD_BLK3_RESERVED_6_V 0xffffffff +#define EFUSE_RD_BLK3_RESERVED_6_S 0 + +/* EFUSE_BLK3_RDATA7_REG register */ + +#define EFUSE_BLK3_RDATA7_REG (DR_REG_EFUSE_BASE + 0x94) + +/* EFUSE_RD_BLK3_RESERVED_7 : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_RD_BLK3_RESERVED_7 0xffffffff +#define EFUSE_RD_BLK3_RESERVED_7_M (EFUSE_RD_BLK3_RESERVED_7_V << EFUSE_RD_BLK3_RESERVED_7_S) +#define EFUSE_RD_BLK3_RESERVED_7_V 0xffffffff +#define EFUSE_RD_BLK3_RESERVED_7_S 0 + +/* EFUSE_BLK1_WDATA0_REG register */ + +#define EFUSE_BLK1_WDATA0_REG (DR_REG_EFUSE_BASE + 0x98) + +/* EFUSE_BLK1_DIN0 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK1_DIN0 0xffffffff +#define EFUSE_BLK1_DIN0_M (EFUSE_BLK1_DIN0_V << EFUSE_BLK1_DIN0_S) +#define EFUSE_BLK1_DIN0_V 0xffffffff +#define EFUSE_BLK1_DIN0_S 0 + +/* EFUSE_BLK1_WDATA1_REG register */ + +#define EFUSE_BLK1_WDATA1_REG (DR_REG_EFUSE_BASE + 0x9c) + +/* EFUSE_BLK1_DIN1 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK1_DIN1 0xffffffff +#define EFUSE_BLK1_DIN1_M (EFUSE_BLK1_DIN1_V << EFUSE_BLK1_DIN1_S) +#define EFUSE_BLK1_DIN1_V 0xffffffff +#define EFUSE_BLK1_DIN1_S 0 + +/* EFUSE_BLK1_WDATA2_REG register */ + +#define EFUSE_BLK1_WDATA2_REG (DR_REG_EFUSE_BASE + 0xa0) + +/* EFUSE_BLK1_DIN2 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK1_DIN2 0xffffffff +#define EFUSE_BLK1_DIN2_M (EFUSE_BLK1_DIN2_V << EFUSE_BLK1_DIN2_S) +#define EFUSE_BLK1_DIN2_V 0xffffffff +#define EFUSE_BLK1_DIN2_S 0 + +/* EFUSE_BLK1_WDATA3_REG register */ + +#define EFUSE_BLK1_WDATA3_REG (DR_REG_EFUSE_BASE + 0xa4) + +/* EFUSE_BLK1_DIN3 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK1_DIN3 0xffffffff +#define EFUSE_BLK1_DIN3_M (EFUSE_BLK1_DIN3_V << EFUSE_BLK1_DIN3_S) +#define EFUSE_BLK1_DIN3_V 0xffffffff +#define EFUSE_BLK1_DIN3_S 0 + +/* EFUSE_BLK1_WDATA4_REG register */ + +#define EFUSE_BLK1_WDATA4_REG (DR_REG_EFUSE_BASE + 0xa8) + +/* EFUSE_BLK1_DIN4 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK1_DIN4 0xffffffff +#define EFUSE_BLK1_DIN4_M (EFUSE_BLK1_DIN4_V << EFUSE_BLK1_DIN4_S) +#define EFUSE_BLK1_DIN4_V 0xffffffff +#define EFUSE_BLK1_DIN4_S 0 + +/* EFUSE_BLK1_WDATA5_REG register */ + +#define EFUSE_BLK1_WDATA5_REG (DR_REG_EFUSE_BASE + 0xac) + +/* EFUSE_BLK1_DIN5 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK1_DIN5 0xffffffff +#define EFUSE_BLK1_DIN5_M (EFUSE_BLK1_DIN5_V << EFUSE_BLK1_DIN5_S) +#define EFUSE_BLK1_DIN5_V 0xffffffff +#define EFUSE_BLK1_DIN5_S 0 + +/* EFUSE_BLK1_WDATA6_REG register */ + +#define EFUSE_BLK1_WDATA6_REG (DR_REG_EFUSE_BASE + 0xb0) + +/* EFUSE_BLK1_DIN6 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK1_DIN6 0xffffffff +#define EFUSE_BLK1_DIN6_M (EFUSE_BLK1_DIN6_V << EFUSE_BLK1_DIN6_S) +#define EFUSE_BLK1_DIN6_V 0xffffffff +#define EFUSE_BLK1_DIN6_S 0 + +/* EFUSE_BLK1_WDATA7_REG register */ + +#define EFUSE_BLK1_WDATA7_REG (DR_REG_EFUSE_BASE + 0xb4) + +/* EFUSE_BLK1_DIN7 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK1_DIN7 0xffffffff +#define EFUSE_BLK1_DIN7_M (EFUSE_BLK1_DIN7_V << EFUSE_BLK1_DIN7_S) +#define EFUSE_BLK1_DIN7_V 0xffffffff +#define EFUSE_BLK1_DIN7_S 0 + +/* EFUSE_BLK2_WDATA0_REG register */ + +#define EFUSE_BLK2_WDATA0_REG (DR_REG_EFUSE_BASE + 0xb8) + +/* EFUSE_BLK2_DIN0 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK2_DIN0 0xffffffff +#define EFUSE_BLK2_DIN0_M (EFUSE_BLK2_DIN0_V << EFUSE_BLK2_DIN0_S) +#define EFUSE_BLK2_DIN0_V 0xffffffff +#define EFUSE_BLK2_DIN0_S 0 + +/* EFUSE_BLK2_WDATA1_REG register */ + +#define EFUSE_BLK2_WDATA1_REG (DR_REG_EFUSE_BASE + 0xbc) + +/* EFUSE_BLK2_DIN1 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK2_DIN1 0xffffffff +#define EFUSE_BLK2_DIN1_M (EFUSE_BLK2_DIN1_V << EFUSE_BLK2_DIN1_S) +#define EFUSE_BLK2_DIN1_V 0xffffffff +#define EFUSE_BLK2_DIN1_S 0 + +/* EFUSE_BLK2_WDATA2_REG register */ + +#define EFUSE_BLK2_WDATA2_REG (DR_REG_EFUSE_BASE + 0xc0) + +/* EFUSE_BLK2_DIN2 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK2_DIN2 0xffffffff +#define EFUSE_BLK2_DIN2_M (EFUSE_BLK2_DIN2_V << EFUSE_BLK2_DIN2_S) +#define EFUSE_BLK2_DIN2_V 0xffffffff +#define EFUSE_BLK2_DIN2_S 0 + +/* EFUSE_BLK2_WDATA3_REG register */ + +#define EFUSE_BLK2_WDATA3_REG (DR_REG_EFUSE_BASE + 0xc4) + +/* EFUSE_BLK2_DIN3 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK2_DIN3 0xffffffff +#define EFUSE_BLK2_DIN3_M (EFUSE_BLK2_DIN3_V << EFUSE_BLK2_DIN3_S) +#define EFUSE_BLK2_DIN3_V 0xffffffff +#define EFUSE_BLK2_DIN3_S 0 + +/* EFUSE_BLK2_WDATA4_REG register */ + +#define EFUSE_BLK2_WDATA4_REG (DR_REG_EFUSE_BASE + 0xc8) + +/* EFUSE_BLK2_DIN4 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK2_DIN4 0xffffffff +#define EFUSE_BLK2_DIN4_M (EFUSE_BLK2_DIN4_V << EFUSE_BLK2_DIN4_S) +#define EFUSE_BLK2_DIN4_V 0xffffffff +#define EFUSE_BLK2_DIN4_S 0 + +/* EFUSE_BLK2_WDATA5_REG register */ + +#define EFUSE_BLK2_WDATA5_REG (DR_REG_EFUSE_BASE + 0xcc) + +/* EFUSE_BLK2_DIN5 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK2_DIN5 0xffffffff +#define EFUSE_BLK2_DIN5_M (EFUSE_BLK2_DIN5_V << EFUSE_BLK2_DIN5_S) +#define EFUSE_BLK2_DIN5_V 0xffffffff +#define EFUSE_BLK2_DIN5_S 0 + +/* EFUSE_BLK2_WDATA6_REG register */ + +#define EFUSE_BLK2_WDATA6_REG (DR_REG_EFUSE_BASE + 0xd0) + +/* EFUSE_BLK2_DIN6 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK2_DIN6 0xffffffff +#define EFUSE_BLK2_DIN6_M (EFUSE_BLK2_DIN6_V << EFUSE_BLK2_DIN6_S) +#define EFUSE_BLK2_DIN6_V 0xffffffff +#define EFUSE_BLK2_DIN6_S 0 + +/* EFUSE_BLK2_WDATA7_REG register */ + +#define EFUSE_BLK2_WDATA7_REG (DR_REG_EFUSE_BASE + 0xd4) + +/* EFUSE_BLK2_DIN7 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK2_DIN7 0xffffffff +#define EFUSE_BLK2_DIN7_M (EFUSE_BLK2_DIN7_V << EFUSE_BLK2_DIN7_S) +#define EFUSE_BLK2_DIN7_V 0xffffffff +#define EFUSE_BLK2_DIN7_S 0 + +/* EFUSE_BLK3_WDATA0_REG register */ + +#define EFUSE_BLK3_WDATA0_REG (DR_REG_EFUSE_BASE + 0xd8) + +/* EFUSE_BLK3_DIN0 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK3_DIN0 0xffffffff +#define EFUSE_BLK3_DIN0_M (EFUSE_BLK3_DIN0_V << EFUSE_BLK3_DIN0_S) +#define EFUSE_BLK3_DIN0_V 0xffffffff +#define EFUSE_BLK3_DIN0_S 0 + +/* EFUSE_BLK3_WDATA1_REG register */ + +#define EFUSE_BLK3_WDATA1_REG (DR_REG_EFUSE_BASE + 0xdc) + +/* EFUSE_BLK3_DIN1 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK3_DIN1 0xffffffff +#define EFUSE_BLK3_DIN1_M (EFUSE_BLK3_DIN1_V << EFUSE_BLK3_DIN1_S) +#define EFUSE_BLK3_DIN1_V 0xffffffff +#define EFUSE_BLK3_DIN1_S 0 + +/* EFUSE_BLK3_WDATA2_REG register */ + +#define EFUSE_BLK3_WDATA2_REG (DR_REG_EFUSE_BASE + 0xe0) + +/* EFUSE_BLK3_DIN2 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK3_DIN2 0xffffffff +#define EFUSE_BLK3_DIN2_M (EFUSE_BLK3_DIN2_V << EFUSE_BLK3_DIN2_S) +#define EFUSE_BLK3_DIN2_V 0xffffffff +#define EFUSE_BLK3_DIN2_S 0 + +/* EFUSE_BLK3_WDATA3_REG register */ + +#define EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0xe4) + +/* EFUSE_ADC2_TP_HIGH : RW; bitpos: [31:23]; default: 0; */ + +#define EFUSE_ADC2_TP_HIGH 0x000001ff +#define EFUSE_ADC2_TP_HIGH_M (EFUSE_ADC2_TP_HIGH_V << EFUSE_ADC2_TP_HIGH_S) +#define EFUSE_ADC2_TP_HIGH_V 0x000001ff +#define EFUSE_ADC2_TP_HIGH_S 23 + +/* EFUSE_ADC2_TP_LOW : RW; bitpos: [22:16]; default: 0; */ + +#define EFUSE_ADC2_TP_LOW 0x0000007f +#define EFUSE_ADC2_TP_LOW_M (EFUSE_ADC2_TP_LOW_V << EFUSE_ADC2_TP_LOW_S) +#define EFUSE_ADC2_TP_LOW_V 0x0000007f +#define EFUSE_ADC2_TP_LOW_S 16 + +/* EFUSE_ADC1_TP_HIGH : RW; bitpos: [15:7]; default: 0; */ + +#define EFUSE_ADC1_TP_HIGH 0x000001ff +#define EFUSE_ADC1_TP_HIGH_M (EFUSE_ADC1_TP_HIGH_V << EFUSE_ADC1_TP_HIGH_S) +#define EFUSE_ADC1_TP_HIGH_V 0x000001ff +#define EFUSE_ADC1_TP_HIGH_S 7 + +/* EFUSE_ADC1_TP_LOW : RW; bitpos: [6:0]; default: 0; */ + +#define EFUSE_ADC1_TP_LOW 0x0000007f +#define EFUSE_ADC1_TP_LOW_M (EFUSE_ADC1_TP_LOW_V << EFUSE_ADC1_TP_LOW_S) +#define EFUSE_ADC1_TP_LOW_V 0x0000007f +#define EFUSE_ADC1_TP_LOW_S 0 + +/* EFUSE_BLK3_WDATA4_REG register */ + +#define EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0xe8) + +/* EFUSE_SECURE_VERSION : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_SECURE_VERSION 0xffffffff +#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) +#define EFUSE_SECURE_VERSION_V 0xffffffff +#define EFUSE_SECURE_VERSION_S 0 + +/* EFUSE_BLK3_WDATA5_REG register */ + +#define EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0xec) + +/* EFUSE_BLK3_DIN5 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK3_DIN5 0xffffffff +#define EFUSE_BLK3_DIN5_M (EFUSE_BLK3_DIN5_V << EFUSE_BLK3_DIN5_S) +#define EFUSE_BLK3_DIN5_V 0xffffffff +#define EFUSE_BLK3_DIN5_S 0 + +/* EFUSE_BLK3_WDATA6_REG register */ + +#define EFUSE_BLK3_WDATA6_REG (DR_REG_EFUSE_BASE + 0xf0) + +/* EFUSE_BLK3_DIN6 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK3_DIN6 0xffffffff +#define EFUSE_BLK3_DIN6_M (EFUSE_BLK3_DIN6_V << EFUSE_BLK3_DIN6_S) +#define EFUSE_BLK3_DIN6_V 0xffffffff +#define EFUSE_BLK3_DIN6_S 0 + +/* EFUSE_BLK3_WDATA7_REG register */ + +#define EFUSE_BLK3_WDATA7_REG (DR_REG_EFUSE_BASE + 0xf4) + +/* EFUSE_BLK3_DIN7 : RW; bitpos: [31:0]; default: 0; */ + +#define EFUSE_BLK3_DIN7 0xffffffff +#define EFUSE_BLK3_DIN7_M (EFUSE_BLK3_DIN7_V << EFUSE_BLK3_DIN7_S) +#define EFUSE_BLK3_DIN7_V 0xffffffff +#define EFUSE_BLK3_DIN7_S 0 + +/* EFUSE_CLK_REG register */ + +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0xf8) + +/* EFUSE_CLK_EN : RW; bitpos: [16]; default: 0; */ + +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) +#define EFUSE_CLK_EN_V 0x00000001 +#define EFUSE_CLK_EN_S 16 + +/* EFUSE_CLK_SEL1 : RW; bitpos: [15:8]; default: 64; */ + +#define EFUSE_CLK_SEL1 0x000000ff +#define EFUSE_CLK_SEL1_M (EFUSE_CLK_SEL1_V << EFUSE_CLK_SEL1_S) +#define EFUSE_CLK_SEL1_V 0x000000ff +#define EFUSE_CLK_SEL1_S 8 + +/* EFUSE_CLK_SEL0 : RW; bitpos: [7:0]; default: 82; */ + +#define EFUSE_CLK_SEL0 0x000000ff +#define EFUSE_CLK_SEL0_M (EFUSE_CLK_SEL0_V << EFUSE_CLK_SEL0_S) +#define EFUSE_CLK_SEL0_V 0x000000ff +#define EFUSE_CLK_SEL0_S 0 + +/* EFUSE_CONF_REG register */ + +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0xfc) + +/* EFUSE_FORCE_NO_WR_RD_DIS : RW; bitpos: [16]; default: 1; */ + +#define EFUSE_FORCE_NO_WR_RD_DIS (BIT(16)) +#define EFUSE_FORCE_NO_WR_RD_DIS_M (EFUSE_FORCE_NO_WR_RD_DIS_V << EFUSE_FORCE_NO_WR_RD_DIS_S) +#define EFUSE_FORCE_NO_WR_RD_DIS_V 0x00000001 +#define EFUSE_FORCE_NO_WR_RD_DIS_S 16 + +/* EFUSE_OP_CODE : RW; bitpos: [15:0]; default: 0; */ + +#define EFUSE_OP_CODE 0x0000ffff +#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) +#define EFUSE_OP_CODE_V 0x0000ffff +#define EFUSE_OP_CODE_S 0 + +/* EFUSE_STATUS_REG register */ + +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x100) + +/* EFUSE_DEBUG : R; bitpos: [31:0]; default: 0; */ + +#define EFUSE_DEBUG 0xffffffff +#define EFUSE_DEBUG_M (EFUSE_DEBUG_V << EFUSE_DEBUG_S) +#define EFUSE_DEBUG_V 0xffffffff +#define EFUSE_DEBUG_S 0 + +/* EFUSE_CMD_REG register */ + +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x104) + +/* EFUSE_PGM_CMD : RW; bitpos: [1]; default: 0; */ + +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) +#define EFUSE_PGM_CMD_V 0x00000001 +#define EFUSE_PGM_CMD_S 1 + +/* EFUSE_READ_CMD : RW; bitpos: [0]; default: 0; */ + +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) +#define EFUSE_READ_CMD_V 0x00000001 +#define EFUSE_READ_CMD_S 0 + +/* EFUSE_INT_RAW_REG register */ + +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x108) + +/* EFUSE_PGM_DONE_INT_RAW : R; bitpos: [1]; default: 0; */ + +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) +#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001 +#define EFUSE_PGM_DONE_INT_RAW_S 1 + +/* EFUSE_READ_DONE_INT_RAW : R; bitpos: [0]; default: 0; */ + +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) +#define EFUSE_READ_DONE_INT_RAW_V 0x00000001 +#define EFUSE_READ_DONE_INT_RAW_S 0 + +/* EFUSE_INT_ST_REG register */ + +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x10c) + +/* EFUSE_PGM_DONE_INT_ST : R; bitpos: [1]; default: 0; */ + +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) +#define EFUSE_PGM_DONE_INT_ST_V 0x00000001 +#define EFUSE_PGM_DONE_INT_ST_S 1 + +/* EFUSE_READ_DONE_INT_ST : R; bitpos: [0]; default: 0; */ + +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) +#define EFUSE_READ_DONE_INT_ST_V 0x00000001 +#define EFUSE_READ_DONE_INT_ST_S 0 + +/* EFUSE_INT_ENA_REG register */ + +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x110) + +/* EFUSE_PGM_DONE_INT_ENA : RW; bitpos: [1]; default: 0; */ + +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) +#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001 +#define EFUSE_PGM_DONE_INT_ENA_S 1 + +/* EFUSE_READ_DONE_INT_ENA : RW; bitpos: [0]; default: 0; */ + +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) +#define EFUSE_READ_DONE_INT_ENA_V 0x00000001 +#define EFUSE_READ_DONE_INT_ENA_S 0 + +/* EFUSE_INT_CLR_REG register */ + +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x114) + +/* EFUSE_PGM_DONE_INT_CLR : W; bitpos: [1]; default: 0; */ + +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) +#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001 +#define EFUSE_PGM_DONE_INT_CLR_S 1 + +/* EFUSE_READ_DONE_INT_CLR : W; bitpos: [0]; default: 0; */ + +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) +#define EFUSE_READ_DONE_INT_CLR_V 0x00000001 +#define EFUSE_READ_DONE_INT_CLR_S 0 + +/* EFUSE_DAC_CONF_REG register */ + +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x118) + +/* EFUSE_DAC_CLK_PAD_SEL : RW; bitpos: [8]; default: 0; */ + +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001 +#define EFUSE_DAC_CLK_PAD_SEL_S 8 + +/* EFUSE_DAC_CLK_DIV : RW; bitpos: [7:0]; default: 40; */ + +#define EFUSE_DAC_CLK_DIV 0x000000ff +#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) +#define EFUSE_DAC_CLK_DIV_V 0x000000ff +#define EFUSE_DAC_CLK_DIV_S 0 + +/* EFUSE_DEC_STATUS_REG register */ + +#define EFUSE_DEC_STATUS_REG (DR_REG_EFUSE_BASE + 0x11c) + +/* EFUSE_DEC_WARNINGS : R; bitpos: [11:0]; default: 0; */ + +#define EFUSE_DEC_WARNINGS 0x00000fff +#define EFUSE_DEC_WARNINGS_M (EFUSE_DEC_WARNINGS_V << EFUSE_DEC_WARNINGS_S) +#define EFUSE_DEC_WARNINGS_V 0x00000fff +#define EFUSE_DEC_WARNINGS_S 0 + +/* EFUSE_DATE_REG register */ + +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) + +/* EFUSE_DATE : RW; bitpos: [31:0]; default: 369370624; */ + +#define EFUSE_DATE 0xffffffff +#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) +#define EFUSE_DATE_V 0xffffffff +#define EFUSE_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_EFUSE_H */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_efuse_defs.h b/arch/xtensa/src/esp32/hardware/esp32_efuse_defs.h new file mode 100644 index 0000000000000..7b4025cba8743 --- /dev/null +++ b/arch/xtensa/src/esp32/hardware/esp32_efuse_defs.h @@ -0,0 +1,73 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/hardware/esp32_efuse_defs.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_EFUSE_DEFS_H +#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_EFUSE_DEFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define EFUSE_WRITE_OP_CODE 0x5a5a +#define EFUSE_READ_OP_CODE 0x5aa5 + +/* Write disable bits */ + +#define EFUSE_WR_DIS_RD_DIS (1 << 0) /* disable writing read disable reg */ +#define EFUSE_WR_DIS_WR_DIS (1 << 1) /* disable writing write disable reg */ +#define EFUSE_WR_DIS_FLASH_CRYPT_CNT (1 << 2) +#define EFUSE_WR_DIS_MAC_SPI_CONFIG_HD (1 << 3) /* disable writing MAC & SPI config hd efuses */ +#define EFUSE_WR_DIS_XPD_SDIO (1 << 5) /* disable writing SDIO config efuses */ +#define EFUSE_WR_DIS_SPI_PAD_CONFIG (1 << 6) /* disable writing SPI_PAD_CONFIG efuses */ +#define EFUSE_WR_DIS_BLK1 (1 << 7) /* disable writing BLK1 efuses */ +#define EFUSE_WR_DIS_BLK2 (1 << 8) /* disable writing BLK2 efuses */ +#define EFUSE_WR_DIS_BLK3 (1 << 9) /* disable writing BLK3 efuses */ +#define EFUSE_WR_DIS_FLASH_CRYPT_CODING_SCHEME (1 << 10) /* disable writing FLASH_CRYPT_CONFIG and CODING_SCHEME efuses */ +#define EFUSE_WR_DIS_ABS_DONE_0 (1 << 12) /* disable writing ABS_DONE_0 efuse */ +#define EFUSE_WR_DIS_ABS_DONE_1 (1 << 13) /* disable writing ABS_DONE_1 efuse */ +#define EFUSE_WR_DIS_JTAG_DISABLE (1 << 14) /* disable writing JTAG_DISABLE efuse */ +#define EFUSE_WR_DIS_CONSOLE_DL_DISABLE (1 << 15) /* disable writing CONSOLE_DEBUG_DISABLE, DISABLE_DL_ENCRYPT, DISABLE_DL_DECRYPT and DISABLE_DL_CACHE efuses */ + +/* Read disable bits for efuse blocks 1-3 */ + +#define EFUSE_RD_DIS_BLK1 (1 << 16) +#define EFUSE_RD_DIS_BLK2 (1 << 17) +#define EFUSE_RD_DIS_BLK3 (1 << 18) + +#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2 +#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 /* Deprecated: this chip was never mass produced */ +#define EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH 4 +#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5 +#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302 6 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDR2V3 7 + +#define EFUSE_CODING_SCHEME_VAL_NONE 0x0 +#define EFUSE_CODING_SCHEME_VAL_34 0x1 +#define EFUSE_CODING_SCHEME_VAL_REPEAT 0x2 + +#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_EFUSE_DEFS_H */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_rmt.h b/arch/xtensa/src/esp32/hardware/esp32_rmt.h deleted file mode 100644 index 7f3c097269a05..0000000000000 --- a/arch/xtensa/src/esp32/hardware/esp32_rmt.h +++ /dev/null @@ -1,266 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/hardware/esp32_rmt.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_RMT_H -#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_RMT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* RMT Peripheral constants */ -#define RMT_NUMBER_OF_CHANNELS 8 -#define RMT_DATA_BASE_ADDR 0x3ff56800 -#define RMT_DATA_MEMORY_BLOCK_WORDS 64 - -/* RMT Channel configuration registers */ - -#define RMT_CHNCONF_REG_BASE (DR_REG_RMT_BASE+0x20) -#define RMT_CHNCONF0_REG(n) (RMT_CHNCONF_REG_BASE + 8*n) -#define RMT_CHNCONF1_REG(n) (RMT_CHNCONF0_REG(n) + 4) - -#define RMT_INT_RAW_REG (DR_REG_RMT_BASE+0x00A0) -#define RMT_INT_ST_REG (DR_REG_RMT_BASE+0x00A4) -#define RMT_INT_ENA_REG (DR_REG_RMT_BASE+0x00A8) -#define RMT_INT_CLR_REG (DR_REG_RMT_BASE+0x00AC) - -#define RMT_CHNCARRIER_DUTY_REG(n) (DR_REG_RMT_BASE + 0x00B0+4*n) -#define RMT_CHN_TX_LIM_REG(n) (DR_REG_RMT_BASE + 0x00D0+4*n) - -#define RMT_APB_CONF_REG (DR_REG_RMT_BASE + 0x00F0) - -/* RMT_CHNCONF0_REG Bits */ - -/* RMT_MEM_PD: This bit is used to power down the entire RMT RAM block. - * (It only exists in RMT_CH0CONF0). - * 1: power down memory; 0: power up memory. (R/W) - */ - -#define RMT_MEM_PD BIT(30) -#define RMT_MEM_PD_M (RMT_MEM_PD_V << RMT_MEM_PD_S) -#define RMT_MEM_PD_V 0x00000001 -#define RMT_MEM_PD_S 30 - -/* RMT_CARRIER_OUT_LV_CHN This bit is used for configuration when the - * carrier wave is being transmitted. Transmit on low output level with 0, - * and transmit on high output level with 1. (R/W) - */ - -#define RMT_CARRIER_OUT_LV_CHN BIT(29) -#define RMT_CARRIER_OUT_LV_CHN_M (RMT_CARRIER_OUT_LV_CHN_V << RMT_CARRIER_OUT_LV_CHN_S) -#define RMT_CARRIER_OUT_LV_CHN_V 0x00000001 -#define RMT_CARRIER_OUT_LV_CHN_S 29 - -/* RMT_CARRIER_EN_CHN This is the carrier modulation enable-control bit - * for channel n. Carrier modulation is enabled with 1, while carrier - * modulation is disabled with 0. (R/W) - */ - -#define RMT_CARRIER_EN_CHN BIT(28) -#define RMT_CARRIER_EN_CHN_M (RMT_CARRIER_EN_CHN_V << RMT_CARRIER_EN_CHN_S) -#define RMT_CARRIER_EN_CHN_V 0x00000001 -#define RMT_CARRIER_EN_CHN_S 28 - -/* RMT_MEM_SIZE_CHN This register is used to configure the amount of - * memory blocks allocated to channel n. (R/W) - */ - -#define RMT_MEM_SIZE_CHN BIT(24) -#define RMT_MEM_SIZE_CHN_M (RMT_MEM_SIZE_CHN_V << RMT_MEM_SIZE_CHN_S) -#define RMT_MEM_SIZE_CHN_V 0x00000001 -#define RMT_MEM_SIZE_CHN_S 24 - -/* RMT_IDLE_THRES_CHN In receive mode, when no edge is detected on - * the input signal for longer than REG_IDLE_THRES_CHN channel clock cycles, - * the receive process is finished. (R/W) - */ - -#define RMT_IDLE_THRES_CHN BIT(8) -#define RMT_IDLE_THRES_CHN_M (RMT_IDLE_THRES_CHN_V << RMT_IDLE_THRES_CHN_S) -#define RMT_IDLE_THRES_CHN_V 0x00000001 -#define RMT_IDLE_THRES_CHN_S 8 - -/* RMT_DIV_CNT_CHN This register is used to set the divider for the channel - * clock of channel n. (R/W) - */ - -#define RMT_DIV_CNT_CHN BIT(0) -#define RMT_DIV_CNT_CHN_M (RMT_DIV_CNT_CHN_V << RMT_DIV_CNT_CHN_S) -#define RMT_DIV_CNT_CHN_V 0x00000001 -#define RMT_DIV_CNT_CHN_S 0 - -/* RMT_CHNCONF1_REG Bits */ - -/* RMT_IDLE_OUT_EN_CHN This is the output enable-control bit for channel n - * in IDLE state. (R/W) - */ - -#define RMT_IDLE_OUT_EN_CHN BIT(19) -#define RMT_IDLE_OUT_EN_CHN_M (RMT_IDLE_OUT_EN_CHN_V << RMT_IDLE_OUT_EN_CHN_S) -#define RMT_IDLE_OUT_EN_CHN_V 0x00000001 -#define RMT_IDLE_OUT_EN_CHN_S 19 - -/* RMT_IDLE_OUT_LV_CHN This bit configures the level of output signals - * in channel n when the latter is in IDLE state. (R/W) - */ - -#define RMT_IDLE_OUT_LV_CHN BIT(18) -#define RMT_IDLE_OUT_LV_CHN_M (RMT_IDLE_OUT_LV_CHN_V << RMT_IDLE_OUT_LV_CHN_S) -#define RMT_IDLE_OUT_LV_CHN_V 0x00000001 -#define RMT_IDLE_OUT_LV_CHN_S 18 - -/* RMT_REF_ALWAYS_ON_CHN This bit is used to select the channel's base - * clock. 1:clk_apb; 0:clk_ref. (R/W) - */ - -#define RMT_REF_ALWAYS_ON_CHN BIT(17) -#define RMT_REF_ALWAYS_ON_CHN_M (RMT_REF_ALWAYS_ON_CHN_V << RMT_REF_ALWAYS_ON_CHN_S) -#define RMT_REF_ALWAYS_ON_CHN_V 0x00000001 -#define RMT_REF_ALWAYS_ON_CHN_S 17 - -/* RMT_REF_CNT_RST_CHN Setting this bit resets the clock divider of channel - * n. (R/W) - */ - -#define RMT_REF_CNT_RST_CHN BIT(16) -#define RMT_REF_CNT_RST_CHN_M (RMT_REF_CNT_RST_CHN_V << RMT_REF_CNT_RST_CHN_S) -#define RMT_REF_CNT_RST_CHN_V 0x00000001 -#define RMT_REF_CNT_RST_CHN_S 16 - -/* RMT_RX_FILTER_THRES_CHN In receive mode, channel n ignores input - * pulse when the pulse width is smaller than this value in APB clock - * periods. (R/W) - */ - -#define RMT_RX_FILTER_THRES_CHN BIT(8) -#define RMT_RX_FILTER_THRES_CHN_M (RMT_RX_FILTER_THRES_CHN_V << RMT_RX_FILTER_THRES_CHN_S) -#define RMT_RX_FILTER_THRES_CHN_V 0x00000001 -#define RMT_RX_FILTER_THRES_CHN_S 8 - -/* RMT_RX_FILTER_EN_CHN This is the receive filter's enable-bit for channel - * n. (R/W) - */ - -#define RMT_RX_FILTER_EN_CHN BIT(7) -#define RMT_RX_FILTER_EN_CHN_M (RMT_RX_FILTER_EN_CHN_V << RMT_RX_FILTER_EN_CHN_S) -#define RMT_RX_FILTER_EN_CHN_V 0x00000001 -#define RMT_RX_FILTER_EN_CHN_S 7 - -/* RMT_TX_CONTI_MODE_CHN If this bit is set, instead of going to an idle - * state when transmission ends, the transmitter will restart transmission. - * This results in a repeating output signal. (R/W) - */ - -#define RMT_TX_CONTI_MODE_CHN BIT(6) -#define RMT_TX_CONTI_MODE_CHN_M (RMT_TX_CONTI_MODE_CHN_V << RMT_TX_CONTI_MODE_CHN_S) -#define RMT_TX_CONTI_MODE_CHN_V 0x00000001 -#define RMT_TX_CONTI_MODE_CHN_S 6 - -/* RMT_MEM_OWNER_CHN This bit marks channel n's RAM block ownership. - * Number 1 indicates that the receiver is using the RAM, while 0 indicates - * that the transmitter is using the RAM. (R/W) - */ - -#define RMT_MEM_OWNER_CHN BIT(5) -#define RMT_MEM_OWNER_CHN_M (RMT_MEM_OWNER_CHN_V << RMT_MEM_OWNER_CHN_S) -#define RMT_MEM_OWNER_CHN_V 0x00000001 -#define RMT_MEM_OWNER_CHN_S 5 - -/* RMT_MEM_RD_RST_CHN Set this bit to reset the read-RAM address for channel - * n by accessing the transmitter. (R/W) - */ - -#define RMT_MEM_RD_RST_CHN BIT(3) -#define RMT_MEM_RD_RST_CHN_M (RMT_MEM_RD_RST_CHN_V << RMT_MEM_RD_RST_CHN_S) -#define RMT_MEM_RD_RST_CHN_V 0x00000001 -#define RMT_MEM_RD_RST_CHN_S 3 - -/* RMT_MEM_WR_RST_CHN Set this bit to reset the write-RAM address for - * channel n by accessing the receiver. (R/W) - */ - -#define RMT_MEM_WR_RST_CHN BIT(2) -#define RMT_MEM_WR_RST_CHN_M (RMT_MEM_WR_RST_CHN_V << RMT_MEM_WR_RST_CHN_S) -#define RMT_MEM_WR_RST_CHN_V 0x00000001 -#define RMT_MEM_WR_RST_CHN_S 2 - -/* RMT_RX_EN_CHN Set this bit to enable receiving data on channel n. (R/W) */ - -#define RMT_RX_EN_CHN BIT(1) -#define RMT_RX_EN_CHN_M (RMT_RX_EN_CHN_V << RMT_RX_EN_CHN_S) -#define RMT_RX_EN_CHN_V 0x00000001 -#define RMT_RX_EN_CHN_S 1 - -/* RMT_TX_START_CHN Set this bit to start sending data on channel n. (R/W) */ - -#define RMT_TX_START_CHN(n) BIT(n) -#define RMT_TX_START_CHN_M (RMT_TX_START_CHN_V << RMT_TX_START_CHN_S) -#define RMT_TX_START_CHN_V 0x00000001 -#define RMT_TX_START_CHN_S 0 - -/* RMT_INT_RAW_REG Bits */ - -/* RMT_CHN_TX_THR_EVENT_INT_RAW The raw interrupt status bit for the - * RMT_CHN_TX_THR_EVENT_INT interrupt. (RO) - */ - -#define RMT_CHN_TX_THR_EVENT_INT_RAW(n) BIT(24+n) - -/* RMT_CHN_ERR_INT_RAW The raw interrupt status bit for the RMT_CHN_ERR_INT - * interrupt. (RO) - */ - -#define RMT_CHN_ERR_INT_RAW(n) BIT(3*n+2) - -/* RMT_CHN_RX_END_INT_RAW The raw interrupt status bit for - * the RMT_CHN_RX_END_INT interrupt. (RO) - */ -#define RMT_CHN_RX_END_INT_RAW(n) BIT(3*n+1) - -/* RMT_CHN_TX_END_INT_RAW The raw interrupt status bit for the - * RMT_CHN_TX_END_INT interrupt. (RO) - */ -#define RMT_CHN_TX_END_INT_RAW(n) BIT(3*n) - -/* RMT_INT_ST_REG Bits */ -#define RMT_CHN_TX_THR_EVENT_INT_ST(n) BIT(24+n) -#define RMT_CHN_ERR_INT_ST(n) BIT(3*n+2) -#define RMT_CHN_RX_END_INT_ST(n) BIT(3*n+1) -#define RMT_CHN_TX_END_INT_ST(n) BIT(3*n) - -/* RMT_INT_ENA_REG Bits */ -#define RMT_CHN_TX_THR_EVENT_INT_ENA(n) BIT(24+n) -#define RMT_CHN_ERR_INT_ENA(n) BIT(3*n+2) -#define RMT_CHN_RX_END_INT_ENA(n) BIT(3*n+1) -#define RMT_CHN_TX_END_INT_ENA(n) BIT(3*n) - -/* RMT_INT_CLR_REG Bits */ -#define RMT_CHN_TX_THR_EVENT_INT_CLR(n) BIT(24+n) -#define RMT_CHN_ERR_INT_CLR(n) BIT(3*n+2) -#define RMT_CHN_RX_END_INT_CLR(n) BIT(3*n+1) -#define RMT_CHN_TX_END_INT_CLR(n) BIT(3*n) - -#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_RMT_H */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_sens.h b/arch/xtensa/src/esp32/hardware/esp32_sens.h index a172147c6c498..a89bd6065439e 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_sens.h +++ b/arch/xtensa/src/esp32/hardware/esp32_sens.h @@ -35,727 +35,1464 @@ #define SENS_SAR_READ_CTRL_REG (DR_REG_SENS_BASE + 0x0) -/* SENS_SAR1_DATA_INV : R/W; bitpos: [28]; default: 0; */ +/* SENS_SAR1_DATA_INV : RW; bitpos: [28]; default: 0; + * Invert SAR ADC1 data + */ #define SENS_SAR1_DATA_INV (BIT(28)) #define SENS_SAR1_DATA_INV_M (SENS_SAR1_DATA_INV_V << SENS_SAR1_DATA_INV_S) -#define SENS_SAR1_DATA_INV_V 0x1 +#define SENS_SAR1_DATA_INV_V 0x00000001 #define SENS_SAR1_DATA_INV_S 28 -/* SENS_SAR1_DIG_FORCE : R/W; bitpos: [27]; default: 0; */ +/* SENS_SAR1_DIG_FORCE : RW; bitpos: [27]; default: 0; + * 1: SAR ADC1 controlled by DIG ADC1 CTRL 0: SAR ADC1 controlled by RTC + * ADC1 CTRL + */ #define SENS_SAR1_DIG_FORCE (BIT(27)) -#define SENS_SAR1_DIG_FORCE_M (SENS_SAR1_DIG_FORCE_V << \ - SENS_SAR1_DIG_FORCE_S) -#define SENS_SAR1_DIG_FORCE_V 0x1 +#define SENS_SAR1_DIG_FORCE_M (SENS_SAR1_DIG_FORCE_V << SENS_SAR1_DIG_FORCE_S) +#define SENS_SAR1_DIG_FORCE_V 0x00000001 #define SENS_SAR1_DIG_FORCE_S 27 -/* SENS_SAR1_SAMPLE_BIT : R/W; bitpos: [17:16]; default: 3; */ +/* SENS_SAR1_SAMPLE_NUM : RW; bitpos: [26:19]; default: 0; */ + +#define SENS_SAR1_SAMPLE_NUM 0x000000ff +#define SENS_SAR1_SAMPLE_NUM_M (SENS_SAR1_SAMPLE_NUM_V << SENS_SAR1_SAMPLE_NUM_S) +#define SENS_SAR1_SAMPLE_NUM_V 0x000000ff +#define SENS_SAR1_SAMPLE_NUM_S 19 + +/* SENS_SAR1_CLK_GATED : RW; bitpos: [18]; default: 1; */ + +#define SENS_SAR1_CLK_GATED (BIT(18)) +#define SENS_SAR1_CLK_GATED_M (SENS_SAR1_CLK_GATED_V << SENS_SAR1_CLK_GATED_S) +#define SENS_SAR1_CLK_GATED_V 0x00000001 +#define SENS_SAR1_CLK_GATED_S 18 + +/* SENS_SAR1_SAMPLE_BIT : RW; bitpos: [17:16]; default: 3; + * 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for + * 12-bit width + */ #define SENS_SAR1_SAMPLE_BIT 0x00000003 -#define SENS_SAR1_SAMPLE_BIT_M (SENS_SAR1_SAMPLE_BIT_V << \ - SENS_SAR1_SAMPLE_BIT_S) -#define SENS_SAR1_SAMPLE_BIT_V 0x3 +#define SENS_SAR1_SAMPLE_BIT_M (SENS_SAR1_SAMPLE_BIT_V << SENS_SAR1_SAMPLE_BIT_S) +#define SENS_SAR1_SAMPLE_BIT_V 0x00000003 #define SENS_SAR1_SAMPLE_BIT_S 16 -/* SENS_SAR1_SAMPLE_CYCLE : R/W; bitpos: [15:8]; default: 9; */ +/* SENS_SAR1_SAMPLE_CYCLE : RW; bitpos: [15:8]; default: 9; + * sample cycles for SAR ADC1 + */ #define SENS_SAR1_SAMPLE_CYCLE 0x000000ff -#define SENS_SAR1_SAMPLE_CYCLE_M (SENS_SAR1_SAMPLE_CYCLE_V << \ - SENS_SAR1_SAMPLE_CYCLE_S) -#define SENS_SAR1_SAMPLE_CYCLE_V 0xff +#define SENS_SAR1_SAMPLE_CYCLE_M (SENS_SAR1_SAMPLE_CYCLE_V << SENS_SAR1_SAMPLE_CYCLE_S) +#define SENS_SAR1_SAMPLE_CYCLE_V 0x000000ff #define SENS_SAR1_SAMPLE_CYCLE_S 8 -/* SENS_SAR1_CLK_DIV : R/W; bitpos: [7:0]; default: 2; */ +/* SENS_SAR1_CLK_DIV : RW; bitpos: [7:0]; default: 2; + * clock divider + */ #define SENS_SAR1_CLK_DIV 0x000000ff #define SENS_SAR1_CLK_DIV_M (SENS_SAR1_CLK_DIV_V << SENS_SAR1_CLK_DIV_S) -#define SENS_SAR1_CLK_DIV_V 0xff +#define SENS_SAR1_CLK_DIV_V 0x000000ff #define SENS_SAR1_CLK_DIV_S 0 +/* SENS_SAR_READ_STATUS1_REG register */ + +#define SENS_SAR_READ_STATUS1_REG (DR_REG_SENS_BASE + 0x4) + +/* SENS_SAR1_READER_STATUS : R; bitpos: [31:0]; default: 0; */ + +#define SENS_SAR1_READER_STATUS 0xffffffff +#define SENS_SAR1_READER_STATUS_M (SENS_SAR1_READER_STATUS_V << SENS_SAR1_READER_STATUS_S) +#define SENS_SAR1_READER_STATUS_V 0xffffffff +#define SENS_SAR1_READER_STATUS_S 0 + +/* SENS_SAR_MEAS_WAIT1_REG register */ + +#define SENS_SAR_MEAS_WAIT1_REG (DR_REG_SENS_BASE + 0x8) + +/* SENS_SAR_AMP_WAIT2 : RW; bitpos: [31:16]; default: 10; */ + +#define SENS_SAR_AMP_WAIT2 0x0000ffff +#define SENS_SAR_AMP_WAIT2_M (SENS_SAR_AMP_WAIT2_V << SENS_SAR_AMP_WAIT2_S) +#define SENS_SAR_AMP_WAIT2_V 0x0000ffff +#define SENS_SAR_AMP_WAIT2_S 16 + +/* SENS_SAR_AMP_WAIT1 : RW; bitpos: [15:0]; default: 10; */ + +#define SENS_SAR_AMP_WAIT1 0x0000ffff +#define SENS_SAR_AMP_WAIT1_M (SENS_SAR_AMP_WAIT1_V << SENS_SAR_AMP_WAIT1_S) +#define SENS_SAR_AMP_WAIT1_V 0x0000ffff +#define SENS_SAR_AMP_WAIT1_S 0 + +/* SENS_SAR_MEAS_WAIT2_REG register */ + +#define SENS_SAR_MEAS_WAIT2_REG (DR_REG_SENS_BASE + 0xc) + +/* SENS_SAR2_RSTB_WAIT : RW; bitpos: [27:20]; default: 2; */ + +#define SENS_SAR2_RSTB_WAIT 0x000000ff +#define SENS_SAR2_RSTB_WAIT_M (SENS_SAR2_RSTB_WAIT_V << SENS_SAR2_RSTB_WAIT_S) +#define SENS_SAR2_RSTB_WAIT_V 0x000000ff +#define SENS_SAR2_RSTB_WAIT_S 20 + +/* SENS_FORCE_XPD_SAR : RW; bitpos: [19:18]; default: 0; */ + +#define SENS_FORCE_XPD_SAR 0x00000003 +#define SENS_FORCE_XPD_SAR_M (SENS_FORCE_XPD_SAR_V << SENS_FORCE_XPD_SAR_S) +#define SENS_FORCE_XPD_SAR_V 0x00000003 +#define SENS_FORCE_XPD_SAR_S 18 + +/* SENS_FORCE_XPD_AMP : RW; bitpos: [17:16]; default: 0; */ + +#define SENS_FORCE_XPD_AMP 0x00000003 +#define SENS_FORCE_XPD_AMP_M (SENS_FORCE_XPD_AMP_V << SENS_FORCE_XPD_AMP_S) +#define SENS_FORCE_XPD_AMP_V 0x00000003 +#define SENS_FORCE_XPD_AMP_S 16 + +/* SENS_SAR_AMP_WAIT3 : RW; bitpos: [15:0]; default: 10; */ + +#define SENS_SAR_AMP_WAIT3 0x0000ffff +#define SENS_SAR_AMP_WAIT3_M (SENS_SAR_AMP_WAIT3_V << SENS_SAR_AMP_WAIT3_S) +#define SENS_SAR_AMP_WAIT3_V 0x0000ffff +#define SENS_SAR_AMP_WAIT3_S 0 + +/* SENS_FORCE_XPD_SAR_SW : RW; bitpos: [-1:0]; default: 0; */ + +#define SENS_FORCE_XPD_SAR_SW 0x00000000 +#define SENS_FORCE_XPD_SAR_SW_M (SENS_FORCE_XPD_SAR_SW_V << SENS_FORCE_XPD_SAR_SW_S) +#define SENS_FORCE_XPD_SAR_SW_V 0x00000000 +#define SENS_FORCE_XPD_SAR_SW_S 0 + +/* SENS_SAR_MEAS_CTRL_REG register */ + +#define SENS_SAR_MEAS_CTRL_REG (DR_REG_SENS_BASE + 0x10) + +/* SENS_SAR2_XPD_WAIT : RW; bitpos: [31:24]; default: 7; */ + +#define SENS_SAR2_XPD_WAIT 0x000000ff +#define SENS_SAR2_XPD_WAIT_M (SENS_SAR2_XPD_WAIT_V << SENS_SAR2_XPD_WAIT_S) +#define SENS_SAR2_XPD_WAIT_V 0x000000ff +#define SENS_SAR2_XPD_WAIT_S 24 + +/* SENS_SAR_RSTB_FSM : RW; bitpos: [23:20]; default: 0; */ + +#define SENS_SAR_RSTB_FSM 0x0000000f +#define SENS_SAR_RSTB_FSM_M (SENS_SAR_RSTB_FSM_V << SENS_SAR_RSTB_FSM_S) +#define SENS_SAR_RSTB_FSM_V 0x0000000f +#define SENS_SAR_RSTB_FSM_S 20 + +/* SENS_XPD_SAR_FSM : RW; bitpos: [19:16]; default: 7; */ + +#define SENS_XPD_SAR_FSM 0x0000000f +#define SENS_XPD_SAR_FSM_M (SENS_XPD_SAR_FSM_V << SENS_XPD_SAR_FSM_S) +#define SENS_XPD_SAR_FSM_V 0x0000000f +#define SENS_XPD_SAR_FSM_S 16 + +/* SENS_AMP_SHORT_REF_GND_FSM : RW; bitpos: [15:12]; default: 3; */ + +#define SENS_AMP_SHORT_REF_GND_FSM 0x0000000f +#define SENS_AMP_SHORT_REF_GND_FSM_M (SENS_AMP_SHORT_REF_GND_FSM_V << SENS_AMP_SHORT_REF_GND_FSM_S) +#define SENS_AMP_SHORT_REF_GND_FSM_V 0x0000000f +#define SENS_AMP_SHORT_REF_GND_FSM_S 12 + +/* SENS_AMP_SHORT_REF_FSM : RW; bitpos: [11:8]; default: 3; */ + +#define SENS_AMP_SHORT_REF_FSM 0x0000000f +#define SENS_AMP_SHORT_REF_FSM_M (SENS_AMP_SHORT_REF_FSM_V << SENS_AMP_SHORT_REF_FSM_S) +#define SENS_AMP_SHORT_REF_FSM_V 0x0000000f +#define SENS_AMP_SHORT_REF_FSM_S 8 + +/* SENS_AMP_RST_FB_FSM : RW; bitpos: [7:4]; default: 8; */ + +#define SENS_AMP_RST_FB_FSM 0x0000000f +#define SENS_AMP_RST_FB_FSM_M (SENS_AMP_RST_FB_FSM_V << SENS_AMP_RST_FB_FSM_S) +#define SENS_AMP_RST_FB_FSM_V 0x0000000f +#define SENS_AMP_RST_FB_FSM_S 4 + +/* SENS_XPD_SAR_AMP_FSM : RW; bitpos: [3:0]; default: 15; */ + +#define SENS_XPD_SAR_AMP_FSM 0x0000000f +#define SENS_XPD_SAR_AMP_FSM_M (SENS_XPD_SAR_AMP_FSM_V << SENS_XPD_SAR_AMP_FSM_S) +#define SENS_XPD_SAR_AMP_FSM_V 0x0000000f +#define SENS_XPD_SAR_AMP_FSM_S 0 + +/* SENS_SAR_READ_STATUS2_REG register */ + +#define SENS_SAR_READ_STATUS2_REG (DR_REG_SENS_BASE + 0x14) + +/* SENS_SAR2_READER_STATUS : R; bitpos: [31:0]; default: 0; */ + +#define SENS_SAR2_READER_STATUS 0xffffffff +#define SENS_SAR2_READER_STATUS_M (SENS_SAR2_READER_STATUS_V << SENS_SAR2_READER_STATUS_S) +#define SENS_SAR2_READER_STATUS_V 0xffffffff +#define SENS_SAR2_READER_STATUS_S 0 + /* SENS_ULP_CP_SLEEP_CYC0_REG register */ #define SENS_ULP_CP_SLEEP_CYC0_REG (DR_REG_SENS_BASE + 0x18) -/* SENS_ULP_CP_SLEEP_CYC0 : R/W; bitpos: [31:0]; default: 200; */ +/* SENS_SLEEP_CYCLES_S0 : RW; bitpos: [31:0]; default: 200; + * sleep cycles for ULP-coprocessor timer + */ + +#define SENS_SLEEP_CYCLES_S0 0xffffffff +#define SENS_SLEEP_CYCLES_S0_M (SENS_SLEEP_CYCLES_S0_V << SENS_SLEEP_CYCLES_S0_S) +#define SENS_SLEEP_CYCLES_S0_V 0xffffffff +#define SENS_SLEEP_CYCLES_S0_S 0 + +/* SENS_ULP_CP_SLEEP_CYC1_REG register */ + +#define SENS_ULP_CP_SLEEP_CYC1_REG (DR_REG_SENS_BASE + 0x1c) + +/* SENS_SLEEP_CYCLES_S1 : RW; bitpos: [31:0]; default: 100; */ + +#define SENS_SLEEP_CYCLES_S1 0xffffffff +#define SENS_SLEEP_CYCLES_S1_M (SENS_SLEEP_CYCLES_S1_V << SENS_SLEEP_CYCLES_S1_S) +#define SENS_SLEEP_CYCLES_S1_V 0xffffffff +#define SENS_SLEEP_CYCLES_S1_S 0 + +/* SENS_ULP_CP_SLEEP_CYC2_REG register */ + +#define SENS_ULP_CP_SLEEP_CYC2_REG (DR_REG_SENS_BASE + 0x20) + +/* SENS_SLEEP_CYCLES_S2 : RW; bitpos: [31:0]; default: 50; */ + +#define SENS_SLEEP_CYCLES_S2 0xffffffff +#define SENS_SLEEP_CYCLES_S2_M (SENS_SLEEP_CYCLES_S2_V << SENS_SLEEP_CYCLES_S2_S) +#define SENS_SLEEP_CYCLES_S2_V 0xffffffff +#define SENS_SLEEP_CYCLES_S2_S 0 + +/* SENS_ULP_CP_SLEEP_CYC3_REG register */ -#define SENS_ULP_CP_SLEEP_CYC0 0xffffffff -#define SENS_ULP_CP_SLEEP_CYC0_M (SENS_ULP_CP_SLEEP_CYC0_V << \ - SENS_ULP_CP_SLEEP_CYC0_S) -#define SENS_ULP_CP_SLEEP_CYC0_V 0xffffffff -#define SENS_ULP_CP_SLEEP_CYC0_S 0 +#define SENS_ULP_CP_SLEEP_CYC3_REG (DR_REG_SENS_BASE + 0x24) + +/* SENS_SLEEP_CYCLES_S3 : RW; bitpos: [31:0]; default: 40; */ + +#define SENS_SLEEP_CYCLES_S3 0xffffffff +#define SENS_SLEEP_CYCLES_S3_M (SENS_SLEEP_CYCLES_S3_V << SENS_SLEEP_CYCLES_S3_S) +#define SENS_SLEEP_CYCLES_S3_V 0xffffffff +#define SENS_SLEEP_CYCLES_S3_S 0 + +/* SENS_ULP_CP_SLEEP_CYC4_REG register */ + +#define SENS_ULP_CP_SLEEP_CYC4_REG (DR_REG_SENS_BASE + 0x28) + +/* SENS_SLEEP_CYCLES_S4 : RW; bitpos: [31:0]; default: 20; */ + +#define SENS_SLEEP_CYCLES_S4 0xffffffff +#define SENS_SLEEP_CYCLES_S4_M (SENS_SLEEP_CYCLES_S4_V << SENS_SLEEP_CYCLES_S4_S) +#define SENS_SLEEP_CYCLES_S4_V 0xffffffff +#define SENS_SLEEP_CYCLES_S4_S 0 /* SENS_SAR_START_FORCE_REG register */ #define SENS_SAR_START_FORCE_REG (DR_REG_SENS_BASE + 0x2c) -/* SENS_SAR1_STOP : R/W; bitpos: [23]; default: 0; */ +/* SENS_SAR2_PWDET_EN : RW; bitpos: [24]; default: 0; + * N/A + */ + +#define SENS_SAR2_PWDET_EN (BIT(24)) +#define SENS_SAR2_PWDET_EN_M (SENS_SAR2_PWDET_EN_V << SENS_SAR2_PWDET_EN_S) +#define SENS_SAR2_PWDET_EN_V 0x00000001 +#define SENS_SAR2_PWDET_EN_S 24 + +/* SENS_SAR1_STOP : RW; bitpos: [23]; default: 0; + * stop SAR ADC1 conversion + */ #define SENS_SAR1_STOP (BIT(23)) #define SENS_SAR1_STOP_M (SENS_SAR1_STOP_V << SENS_SAR1_STOP_S) -#define SENS_SAR1_STOP_V 0x1 +#define SENS_SAR1_STOP_V 0x00000001 #define SENS_SAR1_STOP_S 23 -/* SENS_SAR2_STOP : R/W; bitpos: [22]; default: 0; */ +/* SENS_SAR2_STOP : RW; bitpos: [22]; default: 0; + * stop SAR ADC2 conversion + */ #define SENS_SAR2_STOP (BIT(22)) #define SENS_SAR2_STOP_M (SENS_SAR2_STOP_V << SENS_SAR2_STOP_S) -#define SENS_SAR2_STOP_V 0x1 +#define SENS_SAR2_STOP_V 0x00000001 #define SENS_SAR2_STOP_S 22 -/* SENS_PC_INIT : R/W; bitpos: [21:11]; default: 0; */ +/* SENS_PC_INIT : RW; bitpos: [21:11]; default: 0; + * initialized PC for ULP-coprocessor + */ #define SENS_PC_INIT 0x000007ff #define SENS_PC_INIT_M (SENS_PC_INIT_V << SENS_PC_INIT_S) -#define SENS_PC_INIT_V 0x7ff +#define SENS_PC_INIT_V 0x000007ff #define SENS_PC_INIT_S 11 -/* SENS_ULP_CP_START_TOP : R/W; bitpos: [9]; default: 0; */ +/* SENS_SARCLK_EN : RW; bitpos: [10]; default: 0; */ + +#define SENS_SARCLK_EN (BIT(10)) +#define SENS_SARCLK_EN_M (SENS_SARCLK_EN_V << SENS_SARCLK_EN_S) +#define SENS_SARCLK_EN_V 0x00000001 +#define SENS_SARCLK_EN_S 10 + +/* SENS_ULP_CP_START_TOP : RW; bitpos: [9]; default: 0; + * Write 1 to start ULP-coprocessor only active when + * reg_ulp_cp_force_start_top = 1 + */ #define SENS_ULP_CP_START_TOP (BIT(9)) -#define SENS_ULP_CP_START_TOP_M (SENS_ULP_CP_START_TOP_V << \ - SENS_ULP_CP_START_TOP_S) -#define SENS_ULP_CP_START_TOP_V 0x1 +#define SENS_ULP_CP_START_TOP_M (SENS_ULP_CP_START_TOP_V << SENS_ULP_CP_START_TOP_S) +#define SENS_ULP_CP_START_TOP_V 0x00000001 #define SENS_ULP_CP_START_TOP_S 9 -/* SENS_ULP_CP_FORCE_START_TOP : R/W; bitpos: [8]; default: 0; */ +/* SENS_ULP_CP_FORCE_START_TOP : RW; bitpos: [8]; default: 0; + * 1: ULP-coprocessor is started by SW 0: ULP-coprocessor is started by + * timer + */ #define SENS_ULP_CP_FORCE_START_TOP (BIT(8)) -#define SENS_ULP_CP_FORCE_START_TOP_M (SENS_ULP_CP_FORCE_START_TOP_V << \ - SENS_ULP_CP_FORCE_START_TOP_S) -#define SENS_ULP_CP_FORCE_START_TOP_V 0x1 +#define SENS_ULP_CP_FORCE_START_TOP_M (SENS_ULP_CP_FORCE_START_TOP_V << SENS_ULP_CP_FORCE_START_TOP_S) +#define SENS_ULP_CP_FORCE_START_TOP_V 0x00000001 #define SENS_ULP_CP_FORCE_START_TOP_S 8 -/* SENS_SAR2_PWDET_CCT : R/W; bitpos: [7:5]; default: 0; */ +/* SENS_SAR2_PWDET_CCT : RW; bitpos: [7:5]; default: 0; + * SAR2_PWDET_CCT PA power detector capacitance tuning. + */ #define SENS_SAR2_PWDET_CCT 0x00000007 -#define SENS_SAR2_PWDET_CCT_M (SENS_SAR2_PWDET_CCT_V << \ - SENS_SAR2_PWDET_CCT_S) -#define SENS_SAR2_PWDET_CCT_V 0x7 +#define SENS_SAR2_PWDET_CCT_M (SENS_SAR2_PWDET_CCT_V << SENS_SAR2_PWDET_CCT_S) +#define SENS_SAR2_PWDET_CCT_V 0x00000007 #define SENS_SAR2_PWDET_CCT_S 5 -/* SENS_SAR2_EN_TEST : R/W; bitpos: [4]; default: 0; */ +/* SENS_SAR2_EN_TEST : RW; bitpos: [4]; default: 0; + * SAR2_EN_TEST only active when reg_sar2_dig_force = 0 + */ #define SENS_SAR2_EN_TEST (BIT(4)) #define SENS_SAR2_EN_TEST_M (SENS_SAR2_EN_TEST_V << SENS_SAR2_EN_TEST_S) -#define SENS_SAR2_EN_TEST_V 0x1 +#define SENS_SAR2_EN_TEST_V 0x00000001 #define SENS_SAR2_EN_TEST_S 4 -/* SENS_SAR2_BIT_WIDTH : R/W; bitpos: [3:2]; default: 3; */ +/* SENS_SAR2_BIT_WIDTH : RW; bitpos: [3:2]; default: 3; + * 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits + */ #define SENS_SAR2_BIT_WIDTH 0x00000003 -#define SENS_SAR2_BIT_WIDTH_M (SENS_SAR2_BIT_WIDTH_V << \ - SENS_SAR2_BIT_WIDTH_S) -#define SENS_SAR2_BIT_WIDTH_V 0x3 +#define SENS_SAR2_BIT_WIDTH_M (SENS_SAR2_BIT_WIDTH_V << SENS_SAR2_BIT_WIDTH_S) +#define SENS_SAR2_BIT_WIDTH_V 0x00000003 #define SENS_SAR2_BIT_WIDTH_S 2 -/* SENS_SAR1_BIT_WIDTH : R/W; bitpos: [1:0]; default: 3; */ +/* SENS_SAR1_BIT_WIDTH : RW; bitpos: [1:0]; default: 3; + * 00: 9 bit 01: 10 bits 10: 11bits 11: 12bits + */ #define SENS_SAR1_BIT_WIDTH 0x00000003 -#define SENS_SAR1_BIT_WIDTH_M (SENS_SAR1_BIT_WIDTH_V << \ - SENS_SAR1_BIT_WIDTH_S) -#define SENS_SAR1_BIT_WIDTH_V 0x3 +#define SENS_SAR1_BIT_WIDTH_M (SENS_SAR1_BIT_WIDTH_V << SENS_SAR1_BIT_WIDTH_S) +#define SENS_SAR1_BIT_WIDTH_V 0x00000003 #define SENS_SAR1_BIT_WIDTH_S 0 +/* SENS_SAR_MEM_WR_CTRL_REG register */ + +#define SENS_SAR_MEM_WR_CTRL_REG (DR_REG_SENS_BASE + 0x30) + +/* SENS_RTC_MEM_WR_OFFST_CLR : W; bitpos: [22]; default: 0; */ + +#define SENS_RTC_MEM_WR_OFFST_CLR (BIT(22)) +#define SENS_RTC_MEM_WR_OFFST_CLR_M (SENS_RTC_MEM_WR_OFFST_CLR_V << SENS_RTC_MEM_WR_OFFST_CLR_S) +#define SENS_RTC_MEM_WR_OFFST_CLR_V 0x00000001 +#define SENS_RTC_MEM_WR_OFFST_CLR_S 22 + +/* SENS_MEM_WR_ADDR_SIZE : RW; bitpos: [21:11]; default: 512; */ + +#define SENS_MEM_WR_ADDR_SIZE 0x000007ff +#define SENS_MEM_WR_ADDR_SIZE_M (SENS_MEM_WR_ADDR_SIZE_V << SENS_MEM_WR_ADDR_SIZE_S) +#define SENS_MEM_WR_ADDR_SIZE_V 0x000007ff +#define SENS_MEM_WR_ADDR_SIZE_S 11 + +/* SENS_MEM_WR_ADDR_INIT : RW; bitpos: [10:0]; default: 512; */ + +#define SENS_MEM_WR_ADDR_INIT 0x000007ff +#define SENS_MEM_WR_ADDR_INIT_M (SENS_MEM_WR_ADDR_INIT_V << SENS_MEM_WR_ADDR_INIT_S) +#define SENS_MEM_WR_ADDR_INIT_V 0x000007ff +#define SENS_MEM_WR_ADDR_INIT_S 0 + /* SENS_SAR_ATTEN1_REG register */ #define SENS_SAR_ATTEN1_REG (DR_REG_SENS_BASE + 0x34) -/* SENS_SAR_ATTEN1 : R/W; bitpos: [31:0]; default: 0xffffffff; */ +/* SENS_SAR1_ATTEN : RW; bitpos: [31:0]; default: 4294967295; + * 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB + */ -#define SENS_SAR_ATTEN1 0xffffffff -#define SENS_SAR_ATTEN1_M (SENS_SAR_ATTEN1_V << SENS_SAR_ATTEN1_S) -#define SENS_SAR_ATTEN1_V 0xffffffff -#define SENS_SAR_ATTEN1_S 0 +#define SENS_SAR1_ATTEN 0xffffffff +#define SENS_SAR1_ATTEN_M (SENS_SAR1_ATTEN_V << SENS_SAR1_ATTEN_S) +#define SENS_SAR1_ATTEN_V 0xffffffff +#define SENS_SAR1_ATTEN_S 0 /* SENS_SAR_ATTEN2_REG register */ #define SENS_SAR_ATTEN2_REG (DR_REG_SENS_BASE + 0x38) -/* SENS_SAR_ATTEN2 : R/W; bitpos: [31:0]; default: 0xffffffff; */ +/* SENS_SAR2_ATTEN : RW; bitpos: [31:0]; default: 4294967295; + * 2-bit attenuation for each pad 11:1dB 10:6dB 01:3dB 00:0dB + */ + +#define SENS_SAR2_ATTEN 0xffffffff +#define SENS_SAR2_ATTEN_M (SENS_SAR2_ATTEN_V << SENS_SAR2_ATTEN_S) +#define SENS_SAR2_ATTEN_V 0xffffffff +#define SENS_SAR2_ATTEN_S 0 + +/* SENS_SAR_SLAVE_ADDR1_REG register */ + +#define SENS_SAR_SLAVE_ADDR1_REG (DR_REG_SENS_BASE + 0x3c) + +/* SENS_MEAS_STATUS : R; bitpos: [29:22]; default: 0; */ + +#define SENS_MEAS_STATUS 0x000000ff +#define SENS_MEAS_STATUS_M (SENS_MEAS_STATUS_V << SENS_MEAS_STATUS_S) +#define SENS_MEAS_STATUS_V 0x000000ff +#define SENS_MEAS_STATUS_S 22 + +/* SENS_I2C_SLAVE_ADDR0 : RW; bitpos: [21:11]; default: 0; */ + +#define SENS_I2C_SLAVE_ADDR0 0x000007ff +#define SENS_I2C_SLAVE_ADDR0_M (SENS_I2C_SLAVE_ADDR0_V << SENS_I2C_SLAVE_ADDR0_S) +#define SENS_I2C_SLAVE_ADDR0_V 0x000007ff +#define SENS_I2C_SLAVE_ADDR0_S 11 + +/* SENS_I2C_SLAVE_ADDR1 : RW; bitpos: [10:0]; default: 0; */ + +#define SENS_I2C_SLAVE_ADDR1 0x000007ff +#define SENS_I2C_SLAVE_ADDR1_M (SENS_I2C_SLAVE_ADDR1_V << SENS_I2C_SLAVE_ADDR1_S) +#define SENS_I2C_SLAVE_ADDR1_V 0x000007ff +#define SENS_I2C_SLAVE_ADDR1_S 0 + +/* SENS_SAR_SLAVE_ADDR2_REG register */ + +#define SENS_SAR_SLAVE_ADDR2_REG (DR_REG_SENS_BASE + 0x40) + +/* SENS_I2C_SLAVE_ADDR2 : RW; bitpos: [21:11]; default: 0; */ + +#define SENS_I2C_SLAVE_ADDR2 0x000007ff +#define SENS_I2C_SLAVE_ADDR2_M (SENS_I2C_SLAVE_ADDR2_V << SENS_I2C_SLAVE_ADDR2_S) +#define SENS_I2C_SLAVE_ADDR2_V 0x000007ff +#define SENS_I2C_SLAVE_ADDR2_S 11 + +/* SENS_I2C_SLAVE_ADDR3 : RW; bitpos: [10:0]; default: 0; */ + +#define SENS_I2C_SLAVE_ADDR3 0x000007ff +#define SENS_I2C_SLAVE_ADDR3_M (SENS_I2C_SLAVE_ADDR3_V << SENS_I2C_SLAVE_ADDR3_S) +#define SENS_I2C_SLAVE_ADDR3_V 0x000007ff +#define SENS_I2C_SLAVE_ADDR3_S 0 -#define SENS_SAR_ATTEN2 0xffffffff -#define SENS_SAR_ATTEN2_M (SENS_SAR_ATTEN2_V << SENS_SAR_ATTEN2_S) -#define SENS_SAR_ATTEN2_V 0xffffffff -#define SENS_SAR_ATTEN2_S 0 +/* SENS_SAR_SLAVE_ADDR3_REG register */ + +#define SENS_SAR_SLAVE_ADDR3_REG (DR_REG_SENS_BASE + 0x44) + +/* SENS_TSENS_RDY_OUT : R; bitpos: [30]; default: 0; + * indicate temperature sensor out ready + */ + +#define SENS_TSENS_RDY_OUT (BIT(30)) +#define SENS_TSENS_RDY_OUT_M (SENS_TSENS_RDY_OUT_V << SENS_TSENS_RDY_OUT_S) +#define SENS_TSENS_RDY_OUT_V 0x00000001 +#define SENS_TSENS_RDY_OUT_S 30 + +/* SENS_TSENS_OUT : R; bitpos: [29:22]; default: 0; + * temperature sensor data out + */ + +#define SENS_TSENS_OUT 0x000000ff +#define SENS_TSENS_OUT_M (SENS_TSENS_OUT_V << SENS_TSENS_OUT_S) +#define SENS_TSENS_OUT_V 0x000000ff +#define SENS_TSENS_OUT_S 22 + +/* SENS_I2C_SLAVE_ADDR4 : RW; bitpos: [21:11]; default: 0; */ + +#define SENS_I2C_SLAVE_ADDR4 0x000007ff +#define SENS_I2C_SLAVE_ADDR4_M (SENS_I2C_SLAVE_ADDR4_V << SENS_I2C_SLAVE_ADDR4_S) +#define SENS_I2C_SLAVE_ADDR4_V 0x000007ff +#define SENS_I2C_SLAVE_ADDR4_S 11 + +/* SENS_I2C_SLAVE_ADDR5 : RW; bitpos: [10:0]; default: 0; */ + +#define SENS_I2C_SLAVE_ADDR5 0x000007ff +#define SENS_I2C_SLAVE_ADDR5_M (SENS_I2C_SLAVE_ADDR5_V << SENS_I2C_SLAVE_ADDR5_S) +#define SENS_I2C_SLAVE_ADDR5_V 0x000007ff +#define SENS_I2C_SLAVE_ADDR5_S 0 + +/* SENS_SAR_SLAVE_ADDR4_REG register */ + +#define SENS_SAR_SLAVE_ADDR4_REG (DR_REG_SENS_BASE + 0x48) + +/* SENS_I2C_DONE : R; bitpos: [30]; default: 0; + * indicate I2C done + */ + +#define SENS_I2C_DONE (BIT(30)) +#define SENS_I2C_DONE_M (SENS_I2C_DONE_V << SENS_I2C_DONE_S) +#define SENS_I2C_DONE_V 0x00000001 +#define SENS_I2C_DONE_S 30 + +/* SENS_I2C_RDATA : R; bitpos: [29:22]; default: 0; + * I2C read data + */ + +#define SENS_I2C_RDATA 0x000000ff +#define SENS_I2C_RDATA_M (SENS_I2C_RDATA_V << SENS_I2C_RDATA_S) +#define SENS_I2C_RDATA_V 0x000000ff +#define SENS_I2C_RDATA_S 22 + +/* SENS_I2C_SLAVE_ADDR6 : RW; bitpos: [21:11]; default: 0; */ + +#define SENS_I2C_SLAVE_ADDR6 0x000007ff +#define SENS_I2C_SLAVE_ADDR6_M (SENS_I2C_SLAVE_ADDR6_V << SENS_I2C_SLAVE_ADDR6_S) +#define SENS_I2C_SLAVE_ADDR6_V 0x000007ff +#define SENS_I2C_SLAVE_ADDR6_S 11 + +/* SENS_I2C_SLAVE_ADDR7 : RW; bitpos: [10:0]; default: 0; */ + +#define SENS_I2C_SLAVE_ADDR7 0x000007ff +#define SENS_I2C_SLAVE_ADDR7_M (SENS_I2C_SLAVE_ADDR7_V << SENS_I2C_SLAVE_ADDR7_S) +#define SENS_I2C_SLAVE_ADDR7_V 0x000007ff +#define SENS_I2C_SLAVE_ADDR7_S 0 + +/* SENS_SAR_TSENS_CTRL_REG register */ + +#define SENS_SAR_TSENS_CTRL_REG (DR_REG_SENS_BASE + 0x4c) + +/* SENS_TSENS_DUMP_OUT : RW; bitpos: [26]; default: 0; + * temperature sensor dump out only active when reg_tsens_power_up_force = 1 + */ + +#define SENS_TSENS_DUMP_OUT (BIT(26)) +#define SENS_TSENS_DUMP_OUT_M (SENS_TSENS_DUMP_OUT_V << SENS_TSENS_DUMP_OUT_S) +#define SENS_TSENS_DUMP_OUT_V 0x00000001 +#define SENS_TSENS_DUMP_OUT_S 26 + +/* SENS_TSENS_POWER_UP_FORCE : RW; bitpos: [25]; default: 0; + * 1: dump out & power up controlled by SW 0: by FSM + */ + +#define SENS_TSENS_POWER_UP_FORCE (BIT(25)) +#define SENS_TSENS_POWER_UP_FORCE_M (SENS_TSENS_POWER_UP_FORCE_V << SENS_TSENS_POWER_UP_FORCE_S) +#define SENS_TSENS_POWER_UP_FORCE_V 0x00000001 +#define SENS_TSENS_POWER_UP_FORCE_S 25 + +/* SENS_TSENS_POWER_UP : RW; bitpos: [24]; default: 0; + * temperature sensor power up + */ + +#define SENS_TSENS_POWER_UP (BIT(24)) +#define SENS_TSENS_POWER_UP_M (SENS_TSENS_POWER_UP_V << SENS_TSENS_POWER_UP_S) +#define SENS_TSENS_POWER_UP_V 0x00000001 +#define SENS_TSENS_POWER_UP_S 24 + +/* SENS_TSENS_CLK_DIV : RW; bitpos: [23:16]; default: 6; + * temperature sensor clock divider + */ + +#define SENS_TSENS_CLK_DIV 0x000000ff +#define SENS_TSENS_CLK_DIV_M (SENS_TSENS_CLK_DIV_V << SENS_TSENS_CLK_DIV_S) +#define SENS_TSENS_CLK_DIV_V 0x000000ff +#define SENS_TSENS_CLK_DIV_S 16 + +/* SENS_TSENS_IN_INV : RW; bitpos: [15]; default: 0; + * invert temperature sensor data + */ + +#define SENS_TSENS_IN_INV (BIT(15)) +#define SENS_TSENS_IN_INV_M (SENS_TSENS_IN_INV_V << SENS_TSENS_IN_INV_S) +#define SENS_TSENS_IN_INV_V 0x00000001 +#define SENS_TSENS_IN_INV_S 15 + +/* SENS_TSENS_CLK_GATED : RW; bitpos: [14]; default: 1; */ + +#define SENS_TSENS_CLK_GATED (BIT(14)) +#define SENS_TSENS_CLK_GATED_M (SENS_TSENS_CLK_GATED_V << SENS_TSENS_CLK_GATED_S) +#define SENS_TSENS_CLK_GATED_V 0x00000001 +#define SENS_TSENS_CLK_GATED_S 14 + +/* SENS_TSENS_CLK_INV : RW; bitpos: [13]; default: 1; */ + +#define SENS_TSENS_CLK_INV (BIT(13)) +#define SENS_TSENS_CLK_INV_M (SENS_TSENS_CLK_INV_V << SENS_TSENS_CLK_INV_S) +#define SENS_TSENS_CLK_INV_V 0x00000001 +#define SENS_TSENS_CLK_INV_S 13 + +/* SENS_TSENS_XPD_FORCE : RW; bitpos: [12]; default: 0; */ + +#define SENS_TSENS_XPD_FORCE (BIT(12)) +#define SENS_TSENS_XPD_FORCE_M (SENS_TSENS_XPD_FORCE_V << SENS_TSENS_XPD_FORCE_S) +#define SENS_TSENS_XPD_FORCE_V 0x00000001 +#define SENS_TSENS_XPD_FORCE_S 12 + +/* SENS_TSENS_XPD_WAIT : RW; bitpos: [11:0]; default: 2; */ + +#define SENS_TSENS_XPD_WAIT 0x00000fff +#define SENS_TSENS_XPD_WAIT_M (SENS_TSENS_XPD_WAIT_V << SENS_TSENS_XPD_WAIT_S) +#define SENS_TSENS_XPD_WAIT_V 0x00000fff +#define SENS_TSENS_XPD_WAIT_S 0 + +/* SENS_SAR_I2C_CTRL_REG register */ + +#define SENS_SAR_I2C_CTRL_REG (DR_REG_SENS_BASE + 0x50) + +/* SENS_SAR_I2C_START_FORCE : RW; bitpos: [29]; default: 0; + * 1: I2C started by SW 0: I2C started by FSM + */ + +#define SENS_SAR_I2C_START_FORCE (BIT(29)) +#define SENS_SAR_I2C_START_FORCE_M (SENS_SAR_I2C_START_FORCE_V << SENS_SAR_I2C_START_FORCE_S) +#define SENS_SAR_I2C_START_FORCE_V 0x00000001 +#define SENS_SAR_I2C_START_FORCE_S 29 + +/* SENS_SAR_I2C_START : RW; bitpos: [28]; default: 0; + * start I2C only active when reg_sar_i2c_start_force = 1 + */ + +#define SENS_SAR_I2C_START (BIT(28)) +#define SENS_SAR_I2C_START_M (SENS_SAR_I2C_START_V << SENS_SAR_I2C_START_S) +#define SENS_SAR_I2C_START_V 0x00000001 +#define SENS_SAR_I2C_START_S 28 + +/* SENS_SAR_I2C_CTRL : RW; bitpos: [27:0]; default: 0; + * I2C control data only active when reg_sar_i2c_start_force = 1 + */ + +#define SENS_SAR_I2C_CTRL 0x0fffffff +#define SENS_SAR_I2C_CTRL_M (SENS_SAR_I2C_CTRL_V << SENS_SAR_I2C_CTRL_S) +#define SENS_SAR_I2C_CTRL_V 0x0fffffff +#define SENS_SAR_I2C_CTRL_S 0 /* SENS_SAR_MEAS_START1_REG register */ #define SENS_SAR_MEAS_START1_REG (DR_REG_SENS_BASE + 0x54) -/* SENS_SAR1_EN_PAD_FORCE : R/W; bitpos: [31]; default: 0; */ +/* SENS_SAR1_EN_PAD_FORCE : RW; bitpos: [31]; default: 0; + * 1: SAR ADC1 pad enable bitmap is controlled by SW 0: SAR ADC1 pad enable + * bitmap is controlled by ULP-coprocessor + */ #define SENS_SAR1_EN_PAD_FORCE (BIT(31)) -#define SENS_SAR1_EN_PAD_FORCE_M (SENS_SAR1_EN_PAD_FORCE_V << \ - SENS_SAR1_EN_PAD_FORCE_S) -#define SENS_SAR1_EN_PAD_FORCE_V 0x1 +#define SENS_SAR1_EN_PAD_FORCE_M (SENS_SAR1_EN_PAD_FORCE_V << SENS_SAR1_EN_PAD_FORCE_S) +#define SENS_SAR1_EN_PAD_FORCE_V 0x00000001 #define SENS_SAR1_EN_PAD_FORCE_S 31 -/* SENS_SAR1_EN_PAD : R/W; bitpos: [30:19]; default: 0; */ +/* SENS_SAR1_EN_PAD : RW; bitpos: [30:19]; default: 0; + * SAR ADC1 pad enable bitmap only active when reg_sar1_en_pad_force = 1 + */ -#define SENS_SAR1_EN_PAD 0x000003ff +#define SENS_SAR1_EN_PAD 0x00000fff #define SENS_SAR1_EN_PAD_M (SENS_SAR1_EN_PAD_V << SENS_SAR1_EN_PAD_S) -#define SENS_SAR1_EN_PAD_V 0x3ff +#define SENS_SAR1_EN_PAD_V 0x00000fff #define SENS_SAR1_EN_PAD_S 19 -/* SENS_MEAS1_START_FORCE : R/W; bitpos: [18]; default: 0; */ +/* SENS_MEAS1_START_FORCE : RW; bitpos: [18]; default: 0; + * 1: SAR ADC1 controller (in RTC) is started by SW 0: SAR ADC1 controller + * is started by ULP-coprocessor + */ #define SENS_MEAS1_START_FORCE (BIT(18)) -#define SENS_MEAS1_START_FORCE_M (SENS_MEAS1_START_FORCE_V << \ - SENS_MEAS1_START_FORCE_S) -#define SENS_MEAS1_START_FORCE_V 0x1 +#define SENS_MEAS1_START_FORCE_M (SENS_MEAS1_START_FORCE_V << SENS_MEAS1_START_FORCE_S) +#define SENS_MEAS1_START_FORCE_V 0x00000001 #define SENS_MEAS1_START_FORCE_S 18 -/* SENS_MEAS1_START_SAR : R/W; bitpos: [17]; default: 0; */ +/* SENS_MEAS1_START_SAR : RW; bitpos: [17]; default: 0; + * SAR ADC1 controller (in RTC) starts conversion only active when + * reg_meas1_start_force = 1 + */ #define SENS_MEAS1_START_SAR (BIT(17)) -#define SENS_MEAS1_START_SAR_M (SENS_MEAS1_START_SAR_V << \ - SENS_MEAS1_START_SAR_S) -#define SENS_MEAS1_START_SAR_V 0x1 +#define SENS_MEAS1_START_SAR_M (SENS_MEAS1_START_SAR_V << SENS_MEAS1_START_SAR_S) +#define SENS_MEAS1_START_SAR_V 0x00000001 #define SENS_MEAS1_START_SAR_S 17 -/* SENS_MEAS1_DONE_SAR : RO; bitpos: [16]; default: 0; */ +/* SENS_MEAS1_DONE_SAR : R; bitpos: [16]; default: 0; + * SAR ADC1 conversion done indication + */ #define SENS_MEAS1_DONE_SAR (BIT(16)) -#define SENS_MEAS1_DONE_SAR_M (SENS_MEAS1_DONE_SAR_V << \ - SENS_MEAS1_DONE_SAR_S) -#define SENS_MEAS1_DONE_SAR_V 0x1 +#define SENS_MEAS1_DONE_SAR_M (SENS_MEAS1_DONE_SAR_V << SENS_MEAS1_DONE_SAR_S) +#define SENS_MEAS1_DONE_SAR_V 0x00000001 #define SENS_MEAS1_DONE_SAR_S 16 -/* SENS_MEAS1_DATA_SAR : RO; bitpos: [15:0]; default: 0; */ +/* SENS_MEAS1_DATA_SAR : R; bitpos: [15:0]; default: 0; + * SAR ADC1 data + */ #define SENS_MEAS1_DATA_SAR 0x0000ffff -#define SENS_MEAS1_DATA_SAR_M (SENS_MEAS1_DATA_SAR_V << \ - SENS_MEAS1_DATA_SAR_S) -#define SENS_MEAS1_DATA_SAR_V 0xffff +#define SENS_MEAS1_DATA_SAR_M (SENS_MEAS1_DATA_SAR_V << SENS_MEAS1_DATA_SAR_S) +#define SENS_MEAS1_DATA_SAR_V 0x0000ffff #define SENS_MEAS1_DATA_SAR_S 0 /* SENS_SAR_TOUCH_CTRL1_REG register */ #define SENS_SAR_TOUCH_CTRL1_REG (DR_REG_SENS_BASE + 0x58) -/* SENS_HALL_PHASE_FORCE : R/W; bitpos: [27]; default: 0; */ +/* SENS_HALL_PHASE_FORCE : RW; bitpos: [27]; default: 0; + * 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in + * ULP-coprocessor + */ #define SENS_HALL_PHASE_FORCE (BIT(27)) -#define SENS_HALL_PHASE_FORCE_M (SENS_HALL_PHASE_FORCE_V << \ - SENS_HALL_PHASE_FORCE_S) -#define SENS_HALL_PHASE_FORCE_V 0x1 +#define SENS_HALL_PHASE_FORCE_M (SENS_HALL_PHASE_FORCE_V << SENS_HALL_PHASE_FORCE_S) +#define SENS_HALL_PHASE_FORCE_V 0x00000001 #define SENS_HALL_PHASE_FORCE_S 27 -/* SENS_XPD_HALL_FORCE : R/W; bitpos: [26]; default: 0; */ +/* SENS_XPD_HALL_FORCE : RW; bitpos: [26]; default: 0; + * 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in + * ULP-coprocessor + */ #define SENS_XPD_HALL_FORCE (BIT(26)) -#define SENS_XPD_HALL_FORCE_M (SENS_XPD_HALL_FORCE_V << \ - SENS_XPD_HALL_FORCE_S) -#define SENS_XPD_HALL_FORCE_V 0x1 +#define SENS_XPD_HALL_FORCE_M (SENS_XPD_HALL_FORCE_V << SENS_XPD_HALL_FORCE_S) +#define SENS_XPD_HALL_FORCE_V 0x00000001 #define SENS_XPD_HALL_FORCE_S 26 -/* SENS_TOUCH_OUT_1EN : R/W; bitpos: [25]; default: 1; */ +/* SENS_TOUCH_OUT_1EN : RW; bitpos: [25]; default: 1; + * 1: wakeup interrupt is generated if SET1 is "touched" 0: wakeup + * interrupt is generated only if SET1 & SET2 is both "touched" + */ #define SENS_TOUCH_OUT_1EN (BIT(25)) #define SENS_TOUCH_OUT_1EN_M (SENS_TOUCH_OUT_1EN_V << SENS_TOUCH_OUT_1EN_S) -#define SENS_TOUCH_OUT_1EN_V 0x1 +#define SENS_TOUCH_OUT_1EN_V 0x00000001 #define SENS_TOUCH_OUT_1EN_S 25 -/* SENS_TOUCH_OUT_SEL : R/W; bitpos: [24]; default: 0; */ +/* SENS_TOUCH_OUT_SEL : RW; bitpos: [24]; default: 0; + * 1: when the counter is greater then the threshold the touch pad is + * considered as "touched" 0: when the counter is less than the threshold + * the touch pad is considered as "touched" + */ #define SENS_TOUCH_OUT_SEL (BIT(24)) #define SENS_TOUCH_OUT_SEL_M (SENS_TOUCH_OUT_SEL_V << SENS_TOUCH_OUT_SEL_S) -#define SENS_TOUCH_OUT_SEL_V 0x1 +#define SENS_TOUCH_OUT_SEL_V 0x00000001 #define SENS_TOUCH_OUT_SEL_S 24 -/* SENS_TOUCH_XPD_WAIT : R/W; bitpos: [23:16]; default: 4; */ +/* SENS_TOUCH_XPD_WAIT : RW; bitpos: [23:16]; default: 4; + * the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD + */ #define SENS_TOUCH_XPD_WAIT 0x000000ff -#define SENS_TOUCH_XPD_WAIT_M (SENS_TOUCH_XPD_WAIT_V << \ - SENS_TOUCH_XPD_WAIT_S) -#define SENS_TOUCH_XPD_WAIT_V 0xff +#define SENS_TOUCH_XPD_WAIT_M (SENS_TOUCH_XPD_WAIT_V << SENS_TOUCH_XPD_WAIT_S) +#define SENS_TOUCH_XPD_WAIT_V 0x000000ff #define SENS_TOUCH_XPD_WAIT_S 16 -/* SENS_TOUCH_MEAS_DELAY : R/W; bitpos: [15:0]; default: 0x1000; */ +/* SENS_TOUCH_MEAS_DELAY : RW; bitpos: [15:0]; default: 4096; + * the meas length (in 8MHz) + */ #define SENS_TOUCH_MEAS_DELAY 0x0000ffff -#define SENS_TOUCH_MEAS_DELAY_M (SENS_TOUCH_MEAS_DELAY_V << \ - SENS_TOUCH_MEAS_DELAY_S) -#define SENS_TOUCH_MEAS_DELAY_V 0xffff +#define SENS_TOUCH_MEAS_DELAY_M (SENS_TOUCH_MEAS_DELAY_V << SENS_TOUCH_MEAS_DELAY_S) +#define SENS_TOUCH_MEAS_DELAY_V 0x0000ffff #define SENS_TOUCH_MEAS_DELAY_S 0 /* SENS_SAR_TOUCH_THRES1_REG register */ #define SENS_SAR_TOUCH_THRES1_REG (DR_REG_SENS_BASE + 0x5c) -/* SENS_TOUCH_OUT_TH0 : R/W; bitpos: [31:16]; default: 0; */ +/* SENS_TOUCH_OUT_TH0 : RW; bitpos: [31:16]; default: 0; + * the threshold for touch pad 0 + */ #define SENS_TOUCH_OUT_TH0 0x0000ffff #define SENS_TOUCH_OUT_TH0_M (SENS_TOUCH_OUT_TH0_V << SENS_TOUCH_OUT_TH0_S) -#define SENS_TOUCH_OUT_TH0_V 0xffff +#define SENS_TOUCH_OUT_TH0_V 0x0000ffff #define SENS_TOUCH_OUT_TH0_S 16 -/* SENS_TOUCH_OUT_TH1 : R/W; bitpos: [15:0]; default: 0; */ +/* SENS_TOUCH_OUT_TH1 : RW; bitpos: [15:0]; default: 0; + * the threshold for touch pad 1 + */ #define SENS_TOUCH_OUT_TH1 0x0000ffff #define SENS_TOUCH_OUT_TH1_M (SENS_TOUCH_OUT_TH1_V << SENS_TOUCH_OUT_TH1_S) -#define SENS_TOUCH_OUT_TH1_V 0xffff +#define SENS_TOUCH_OUT_TH1_V 0x0000ffff #define SENS_TOUCH_OUT_TH1_S 0 /* SENS_SAR_TOUCH_THRES2_REG register */ #define SENS_SAR_TOUCH_THRES2_REG (DR_REG_SENS_BASE + 0x60) -/* SENS_TOUCH_OUT_TH2 : R/W; bitpos: [31:16]; default: 0; */ +/* SENS_TOUCH_OUT_TH2 : RW; bitpos: [31:16]; default: 0; + * the threshold for touch pad 2 + */ #define SENS_TOUCH_OUT_TH2 0x0000ffff #define SENS_TOUCH_OUT_TH2_M (SENS_TOUCH_OUT_TH2_V << SENS_TOUCH_OUT_TH2_S) -#define SENS_TOUCH_OUT_TH2_V 0xffff +#define SENS_TOUCH_OUT_TH2_V 0x0000ffff #define SENS_TOUCH_OUT_TH2_S 16 -/* SENS_TOUCH_OUT_TH3 : R/W; bitpos: [15:0]; default: 0; */ +/* SENS_TOUCH_OUT_TH3 : RW; bitpos: [15:0]; default: 0; + * the threshold for touch pad 3 + */ #define SENS_TOUCH_OUT_TH3 0x0000ffff #define SENS_TOUCH_OUT_TH3_M (SENS_TOUCH_OUT_TH3_V << SENS_TOUCH_OUT_TH3_S) -#define SENS_TOUCH_OUT_TH3_V 0xffff +#define SENS_TOUCH_OUT_TH3_V 0x0000ffff #define SENS_TOUCH_OUT_TH3_S 0 /* SENS_SAR_TOUCH_THRES3_REG register */ #define SENS_SAR_TOUCH_THRES3_REG (DR_REG_SENS_BASE + 0x64) -/* SENS_TOUCH_OUT_TH4 : R/W; bitpos: [31:16]; default: 0; */ +/* SENS_TOUCH_OUT_TH4 : RW; bitpos: [31:16]; default: 0; + * the threshold for touch pad 4 + */ #define SENS_TOUCH_OUT_TH4 0x0000ffff #define SENS_TOUCH_OUT_TH4_M (SENS_TOUCH_OUT_TH4_V << SENS_TOUCH_OUT_TH4_S) -#define SENS_TOUCH_OUT_TH4_V 0xffff +#define SENS_TOUCH_OUT_TH4_V 0x0000ffff #define SENS_TOUCH_OUT_TH4_S 16 -/* SENS_TOUCH_OUT_TH5 : R/W; bitpos: [15:0]; default: 0; */ +/* SENS_TOUCH_OUT_TH5 : RW; bitpos: [15:0]; default: 0; + * the threshold for touch pad 5 + */ #define SENS_TOUCH_OUT_TH5 0x0000ffff #define SENS_TOUCH_OUT_TH5_M (SENS_TOUCH_OUT_TH5_V << SENS_TOUCH_OUT_TH5_S) -#define SENS_TOUCH_OUT_TH5_V 0xffff +#define SENS_TOUCH_OUT_TH5_V 0x0000ffff #define SENS_TOUCH_OUT_TH5_S 0 /* SENS_SAR_TOUCH_THRES4_REG register */ #define SENS_SAR_TOUCH_THRES4_REG (DR_REG_SENS_BASE + 0x68) -/* SENS_TOUCH_OUT_TH6 : R/W; bitpos: [31:16]; default: 0; */ +/* SENS_TOUCH_OUT_TH6 : RW; bitpos: [31:16]; default: 0; + * the threshold for touch pad 6 + */ #define SENS_TOUCH_OUT_TH6 0x0000ffff #define SENS_TOUCH_OUT_TH6_M (SENS_TOUCH_OUT_TH6_V << SENS_TOUCH_OUT_TH6_S) -#define SENS_TOUCH_OUT_TH6_V 0xffff +#define SENS_TOUCH_OUT_TH6_V 0x0000ffff #define SENS_TOUCH_OUT_TH6_S 16 -/* SENS_TOUCH_OUT_TH7 : R/W; bitpos: [15:0]; default: 0; */ +/* SENS_TOUCH_OUT_TH7 : RW; bitpos: [15:0]; default: 0; + * the threshold for touch pad 7 + */ #define SENS_TOUCH_OUT_TH7 0x0000ffff #define SENS_TOUCH_OUT_TH7_M (SENS_TOUCH_OUT_TH7_V << SENS_TOUCH_OUT_TH7_S) -#define SENS_TOUCH_OUT_TH7_V 0xffff +#define SENS_TOUCH_OUT_TH7_V 0x0000ffff #define SENS_TOUCH_OUT_TH7_S 0 /* SENS_SAR_TOUCH_THRES5_REG register */ #define SENS_SAR_TOUCH_THRES5_REG (DR_REG_SENS_BASE + 0x6c) -/* SENS_TOUCH_OUT_TH8 : R/W; bitpos: [31:16]; default: 0; */ +/* SENS_TOUCH_OUT_TH8 : RW; bitpos: [31:16]; default: 0; + * the threshold for touch pad 8 + */ #define SENS_TOUCH_OUT_TH8 0x0000ffff #define SENS_TOUCH_OUT_TH8_M (SENS_TOUCH_OUT_TH8_V << SENS_TOUCH_OUT_TH8_S) -#define SENS_TOUCH_OUT_TH8_V 0xffff +#define SENS_TOUCH_OUT_TH8_V 0x0000ffff #define SENS_TOUCH_OUT_TH8_S 16 -/* SENS_TOUCH_OUT_TH9 : R/W; bitpos: [15:0]; default: 0; */ +/* SENS_TOUCH_OUT_TH9 : RW; bitpos: [15:0]; default: 0; + * the threshold for touch pad 9 + */ #define SENS_TOUCH_OUT_TH9 0x0000ffff #define SENS_TOUCH_OUT_TH9_M (SENS_TOUCH_OUT_TH9_V << SENS_TOUCH_OUT_TH9_S) -#define SENS_TOUCH_OUT_TH9_V 0xffff +#define SENS_TOUCH_OUT_TH9_V 0x0000ffff #define SENS_TOUCH_OUT_TH9_S 0 /* SENS_SAR_TOUCH_OUT1_REG register */ #define SENS_SAR_TOUCH_OUT1_REG (DR_REG_SENS_BASE + 0x70) -/* SENS_TOUCH_MEAS_OUT0 : RO; bitpos: [31:16]; default: 0; */ +/* SENS_TOUCH_MEAS_OUT0 : R; bitpos: [31:16]; default: 0; + * the counter for touch pad 0 + */ #define SENS_TOUCH_MEAS_OUT0 0x0000ffff -#define SENS_TOUCH_MEAS_OUT0_M (SENS_TOUCH_MEAS_OUT0_V << \ - SENS_TOUCH_MEAS_OUT0_S) -#define SENS_TOUCH_MEAS_OUT0_V 0xffff +#define SENS_TOUCH_MEAS_OUT0_M (SENS_TOUCH_MEAS_OUT0_V << SENS_TOUCH_MEAS_OUT0_S) +#define SENS_TOUCH_MEAS_OUT0_V 0x0000ffff #define SENS_TOUCH_MEAS_OUT0_S 16 -/* SENS_TOUCH_MEAS_OUT1 : RO; bitpos: [15:0]; default: 0; */ +/* SENS_TOUCH_MEAS_OUT1 : R; bitpos: [15:0]; default: 0; + * the counter for touch pad 1 + */ #define SENS_TOUCH_MEAS_OUT1 0x0000ffff -#define SENS_TOUCH_MEAS_OUT1_M (SENS_TOUCH_MEAS_OUT1_V << \ - SENS_TOUCH_MEAS_OUT1_S) -#define SENS_TOUCH_MEAS_OUT1_V 0xffff +#define SENS_TOUCH_MEAS_OUT1_M (SENS_TOUCH_MEAS_OUT1_V << SENS_TOUCH_MEAS_OUT1_S) +#define SENS_TOUCH_MEAS_OUT1_V 0x0000ffff #define SENS_TOUCH_MEAS_OUT1_S 0 /* SENS_SAR_TOUCH_OUT2_REG register */ #define SENS_SAR_TOUCH_OUT2_REG (DR_REG_SENS_BASE + 0x74) -/* SENS_TOUCH_MEAS_OUT2 : RO; bitpos: [31:16]; default: 0; */ +/* SENS_TOUCH_MEAS_OUT2 : R; bitpos: [31:16]; default: 0; + * the counter for touch pad 2 + */ #define SENS_TOUCH_MEAS_OUT2 0x0000ffff -#define SENS_TOUCH_MEAS_OUT2_M (SENS_TOUCH_MEAS_OUT2_V << \ - SENS_TOUCH_MEAS_OUT2_S) -#define SENS_TOUCH_MEAS_OUT2_V 0xffff +#define SENS_TOUCH_MEAS_OUT2_M (SENS_TOUCH_MEAS_OUT2_V << SENS_TOUCH_MEAS_OUT2_S) +#define SENS_TOUCH_MEAS_OUT2_V 0x0000ffff #define SENS_TOUCH_MEAS_OUT2_S 16 -/* SENS_TOUCH_MEAS_OUT3 : RO; bitpos: [15:0]; default: 0; */ +/* SENS_TOUCH_MEAS_OUT3 : R; bitpos: [15:0]; default: 0; + * the counter for touch pad 3 + */ #define SENS_TOUCH_MEAS_OUT3 0x0000ffff -#define SENS_TOUCH_MEAS_OUT3_M (SENS_TOUCH_MEAS_OUT3_V << \ - SENS_TOUCH_MEAS_OUT3_S) -#define SENS_TOUCH_MEAS_OUT3_V 0xffff +#define SENS_TOUCH_MEAS_OUT3_M (SENS_TOUCH_MEAS_OUT3_V << SENS_TOUCH_MEAS_OUT3_S) +#define SENS_TOUCH_MEAS_OUT3_V 0x0000ffff #define SENS_TOUCH_MEAS_OUT3_S 0 /* SENS_SAR_TOUCH_OUT3_REG register */ #define SENS_SAR_TOUCH_OUT3_REG (DR_REG_SENS_BASE + 0x78) -/* SENS_TOUCH_MEAS_OUT4 : RO; bitpos: [31:16]; default: 0; */ +/* SENS_TOUCH_MEAS_OUT4 : R; bitpos: [31:16]; default: 0; + * the counter for touch pad 4 + */ #define SENS_TOUCH_MEAS_OUT4 0x0000ffff -#define SENS_TOUCH_MEAS_OUT4_M (SENS_TOUCH_MEAS_OUT4_V << \ - SENS_TOUCH_MEAS_OUT4_S) -#define SENS_TOUCH_MEAS_OUT4_V 0xffff +#define SENS_TOUCH_MEAS_OUT4_M (SENS_TOUCH_MEAS_OUT4_V << SENS_TOUCH_MEAS_OUT4_S) +#define SENS_TOUCH_MEAS_OUT4_V 0x0000ffff #define SENS_TOUCH_MEAS_OUT4_S 16 -/* SENS_TOUCH_MEAS_OUT5 : RO; bitpos: [15:0]; default: 0; */ +/* SENS_TOUCH_MEAS_OUT5 : R; bitpos: [15:0]; default: 0; + * the counter for touch pad 5 + */ #define SENS_TOUCH_MEAS_OUT5 0x0000ffff -#define SENS_TOUCH_MEAS_OUT5_M (SENS_TOUCH_MEAS_OUT5_V << \ - SENS_TOUCH_MEAS_OUT5_S) -#define SENS_TOUCH_MEAS_OUT5_V 0xffff +#define SENS_TOUCH_MEAS_OUT5_M (SENS_TOUCH_MEAS_OUT5_V << SENS_TOUCH_MEAS_OUT5_S) +#define SENS_TOUCH_MEAS_OUT5_V 0x0000ffff #define SENS_TOUCH_MEAS_OUT5_S 0 /* SENS_SAR_TOUCH_OUT4_REG register */ #define SENS_SAR_TOUCH_OUT4_REG (DR_REG_SENS_BASE + 0x7c) -/* SENS_TOUCH_MEAS_OUT6 : RO; bitpos: [31:16]; default: 0; */ +/* SENS_TOUCH_MEAS_OUT6 : R; bitpos: [31:16]; default: 0; + * the counter for touch pad 6 + */ #define SENS_TOUCH_MEAS_OUT6 0x0000ffff -#define SENS_TOUCH_MEAS_OUT6_M (SENS_TOUCH_MEAS_OUT6_V << \ - SENS_TOUCH_MEAS_OUT6_S) -#define SENS_TOUCH_MEAS_OUT6_V 0xffff +#define SENS_TOUCH_MEAS_OUT6_M (SENS_TOUCH_MEAS_OUT6_V << SENS_TOUCH_MEAS_OUT6_S) +#define SENS_TOUCH_MEAS_OUT6_V 0x0000ffff #define SENS_TOUCH_MEAS_OUT6_S 16 -/* SENS_TOUCH_MEAS_OUT7 : RO; bitpos: [15:0]; default: 0; */ +/* SENS_TOUCH_MEAS_OUT7 : R; bitpos: [15:0]; default: 0; + * the counter for touch pad 7 + */ #define SENS_TOUCH_MEAS_OUT7 0x0000ffff -#define SENS_TOUCH_MEAS_OUT7_M (SENS_TOUCH_MEAS_OUT7_V << \ - SENS_TOUCH_MEAS_OUT7_S) -#define SENS_TOUCH_MEAS_OUT7_V 0xffff +#define SENS_TOUCH_MEAS_OUT7_M (SENS_TOUCH_MEAS_OUT7_V << SENS_TOUCH_MEAS_OUT7_S) +#define SENS_TOUCH_MEAS_OUT7_V 0x0000ffff #define SENS_TOUCH_MEAS_OUT7_S 0 /* SENS_SAR_TOUCH_OUT5_REG register */ #define SENS_SAR_TOUCH_OUT5_REG (DR_REG_SENS_BASE + 0x80) -/* SENS_TOUCH_MEAS_OUT8 : RO; bitpos: [31:16]; default: 0; */ +/* SENS_TOUCH_MEAS_OUT8 : R; bitpos: [31:16]; default: 0; + * the counter for touch pad 8 + */ #define SENS_TOUCH_MEAS_OUT8 0x0000ffff -#define SENS_TOUCH_MEAS_OUT8_M (SENS_TOUCH_MEAS_OUT8_V << \ - SENS_TOUCH_MEAS_OUT8_S) -#define SENS_TOUCH_MEAS_OUT8_V 0xffff +#define SENS_TOUCH_MEAS_OUT8_M (SENS_TOUCH_MEAS_OUT8_V << SENS_TOUCH_MEAS_OUT8_S) +#define SENS_TOUCH_MEAS_OUT8_V 0x0000ffff #define SENS_TOUCH_MEAS_OUT8_S 16 -/* SENS_TOUCH_MEAS_OUT9 : RO; bitpos: [15:0]; default: 0; */ +/* SENS_TOUCH_MEAS_OUT9 : R; bitpos: [15:0]; default: 0; + * the counter for touch pad 9 + */ #define SENS_TOUCH_MEAS_OUT9 0x0000ffff -#define SENS_TOUCH_MEAS_OUT9_M (SENS_TOUCH_MEAS_OUT9_V << \ - SENS_TOUCH_MEAS_OUT9_S) -#define SENS_TOUCH_MEAS_OUT9_V 0xffff +#define SENS_TOUCH_MEAS_OUT9_M (SENS_TOUCH_MEAS_OUT9_V << SENS_TOUCH_MEAS_OUT9_S) +#define SENS_TOUCH_MEAS_OUT9_V 0x0000ffff #define SENS_TOUCH_MEAS_OUT9_S 0 /* SENS_SAR_TOUCH_CTRL2_REG register */ #define SENS_SAR_TOUCH_CTRL2_REG (DR_REG_SENS_BASE + 0x84) -/* SENS_TOUCH_MEAS_EN_CLR : WO; bitpos: [30]; default: 0; */ +/* SENS_TOUCH_MEAS_EN_CLR : W; bitpos: [30]; default: 0; + * to clear reg_touch_meas_en + */ #define SENS_TOUCH_MEAS_EN_CLR (BIT(30)) -#define SENS_TOUCH_MEAS_EN_CLR_M (SENS_TOUCH_MEAS_EN_CLR_V << \ - SENS_TOUCH_MEAS_EN_CLR_S) -#define SENS_TOUCH_MEAS_EN_CLR_V 0x1 +#define SENS_TOUCH_MEAS_EN_CLR_M (SENS_TOUCH_MEAS_EN_CLR_V << SENS_TOUCH_MEAS_EN_CLR_S) +#define SENS_TOUCH_MEAS_EN_CLR_V 0x00000001 #define SENS_TOUCH_MEAS_EN_CLR_S 30 -/* SENS_TOUCH_SLEEP_CYCLES : R/W; bitpos: [29:14]; default: 0x100; */ +/* SENS_TOUCH_SLEEP_CYCLES : RW; bitpos: [29:14]; default: 256; + * sleep cycles for timer + */ #define SENS_TOUCH_SLEEP_CYCLES 0x0000ffff -#define SENS_TOUCH_SLEEP_CYCLES_M (SENS_TOUCH_SLEEP_CYCLES_V << \ - SENS_TOUCH_SLEEP_CYCLES_S) -#define SENS_TOUCH_SLEEP_CYCLES_V 0xffff +#define SENS_TOUCH_SLEEP_CYCLES_M (SENS_TOUCH_SLEEP_CYCLES_V << SENS_TOUCH_SLEEP_CYCLES_S) +#define SENS_TOUCH_SLEEP_CYCLES_V 0x0000ffff #define SENS_TOUCH_SLEEP_CYCLES_S 14 -/* SENS_TOUCH_START_FORCE : R/W; bitpos: [13]; default: 0; */ +/* SENS_TOUCH_START_FORCE : RW; bitpos: [13]; default: 0; + * 1: to start touch fsm by SW 0: to start touch fsm by timer + */ #define SENS_TOUCH_START_FORCE (BIT(13)) -#define SENS_TOUCH_START_FORCE_M (SENS_TOUCH_START_FORCE_V << \ - SENS_TOUCH_START_FORCE_S) -#define SENS_TOUCH_START_FORCE_V 0x1 +#define SENS_TOUCH_START_FORCE_M (SENS_TOUCH_START_FORCE_V << SENS_TOUCH_START_FORCE_S) +#define SENS_TOUCH_START_FORCE_V 0x00000001 #define SENS_TOUCH_START_FORCE_S 13 -/* SENS_TOUCH_START_EN : R/W; bitpos: [12]; default: 0; */ +/* SENS_TOUCH_START_EN : RW; bitpos: [12]; default: 0; + * 1: start touch fsm valid when reg_touch_start_force is set + */ #define SENS_TOUCH_START_EN (BIT(12)) -#define SENS_TOUCH_START_EN_M (SENS_TOUCH_START_EN_V << \ - SENS_TOUCH_START_EN_S) -#define SENS_TOUCH_START_EN_V 0x1 +#define SENS_TOUCH_START_EN_M (SENS_TOUCH_START_EN_V << SENS_TOUCH_START_EN_S) +#define SENS_TOUCH_START_EN_V 0x00000001 #define SENS_TOUCH_START_EN_S 12 -/* SENS_TOUCH_START_FSM_EN : R/W; bitpos: [11]; default: 1; */ +/* SENS_TOUCH_START_FSM_EN : RW; bitpos: [11]; default: 1; + * 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm 0: TOUCH_START & + * TOUCH_XPD is controlled by registers + */ #define SENS_TOUCH_START_FSM_EN (BIT(11)) -#define SENS_TOUCH_START_FSM_EN_M (SENS_TOUCH_START_FSM_EN_V << \ - SENS_TOUCH_START_FSM_EN_S) -#define SENS_TOUCH_START_FSM_EN_V 0x1 +#define SENS_TOUCH_START_FSM_EN_M (SENS_TOUCH_START_FSM_EN_V << SENS_TOUCH_START_FSM_EN_S) +#define SENS_TOUCH_START_FSM_EN_V 0x00000001 #define SENS_TOUCH_START_FSM_EN_S 11 -/* SENS_TOUCH_MEAS_DONE : RO; bitpos: [10]; default: 0; */ +/* SENS_TOUCH_MEAS_DONE : R; bitpos: [10]; default: 0; + * fsm set 1 to indicate touch touch meas is done + */ #define SENS_TOUCH_MEAS_DONE (BIT(10)) -#define SENS_TOUCH_MEAS_DONE_M (SENS_TOUCH_MEAS_DONE_V << \ - SENS_TOUCH_MEAS_DONE_S) -#define SENS_TOUCH_MEAS_DONE_V 0x1 +#define SENS_TOUCH_MEAS_DONE_M (SENS_TOUCH_MEAS_DONE_V << SENS_TOUCH_MEAS_DONE_S) +#define SENS_TOUCH_MEAS_DONE_V 0x00000001 #define SENS_TOUCH_MEAS_DONE_S 10 -/* SENS_TOUCH_MEAS_EN : RO; bitpos: [9:0]; default: 0; */ +/* SENS_TOUCH_MEAS_EN : R; bitpos: [9:0]; default: 0; + * 10-bit register to indicate which pads are "touched" + */ #define SENS_TOUCH_MEAS_EN 0x000003ff #define SENS_TOUCH_MEAS_EN_M (SENS_TOUCH_MEAS_EN_V << SENS_TOUCH_MEAS_EN_S) -#define SENS_TOUCH_MEAS_EN_V 0x3ff +#define SENS_TOUCH_MEAS_EN_V 0x000003ff #define SENS_TOUCH_MEAS_EN_S 0 /* SENS_SAR_TOUCH_ENABLE_REG register */ #define SENS_SAR_TOUCH_ENABLE_REG (DR_REG_SENS_BASE + 0x8c) -/* SENS_TOUCH_PAD_OUTEN1 : R/W; bitpos: [29:20]; default: 0x3ff; */ +/* SENS_TOUCH_PAD_OUTEN1 : RW; bitpos: [29:20]; default: 1023; + * Bitmap defining SET1 for generating wakeup interrupt. SET1 is "touched" + * only if at least one of touch pad in SET1 is "touched". + */ #define SENS_TOUCH_PAD_OUTEN1 0x000003ff -#define SENS_TOUCH_PAD_OUTEN1_M (SENS_TOUCH_PAD_OUTEN1_V << \ - SENS_TOUCH_PAD_OUTEN1_S) -#define SENS_TOUCH_PAD_OUTEN1_V 0x3ff +#define SENS_TOUCH_PAD_OUTEN1_M (SENS_TOUCH_PAD_OUTEN1_V << SENS_TOUCH_PAD_OUTEN1_S) +#define SENS_TOUCH_PAD_OUTEN1_V 0x000003ff #define SENS_TOUCH_PAD_OUTEN1_S 20 -/* SENS_TOUCH_PAD_OUTEN2 : R/W; bitpos: [19:10]; default: 0x3ff; */ +/* SENS_TOUCH_PAD_OUTEN2 : RW; bitpos: [19:10]; default: 1023; + * Bitmap defining SET2 for generating wakeup interrupt. SET2 is "touched" + * only if at least one of touch pad in SET2 is "touched". + */ #define SENS_TOUCH_PAD_OUTEN2 0x000003ff -#define SENS_TOUCH_PAD_OUTEN2_M (SENS_TOUCH_PAD_OUTEN2_V << \ - SENS_TOUCH_PAD_OUTEN2_S) -#define SENS_TOUCH_PAD_OUTEN2_V 0x3ff +#define SENS_TOUCH_PAD_OUTEN2_M (SENS_TOUCH_PAD_OUTEN2_V << SENS_TOUCH_PAD_OUTEN2_S) +#define SENS_TOUCH_PAD_OUTEN2_V 0x000003ff #define SENS_TOUCH_PAD_OUTEN2_S 10 -/* SENS_TOUCH_PAD_WORKEN : R/W; bitpos: [9:0]; default: 0x3ff; */ +/* SENS_TOUCH_PAD_WORKEN : RW; bitpos: [9:0]; default: 1023; + * Bitmap defining the working set during the measurement. + */ #define SENS_TOUCH_PAD_WORKEN 0x000003ff -#define SENS_TOUCH_PAD_WORKEN_M (SENS_TOUCH_PAD_WORKEN_V << \ - SENS_TOUCH_PAD_WORKEN_S) -#define SENS_TOUCH_PAD_WORKEN_V 0x3ff +#define SENS_TOUCH_PAD_WORKEN_M (SENS_TOUCH_PAD_WORKEN_V << SENS_TOUCH_PAD_WORKEN_S) +#define SENS_TOUCH_PAD_WORKEN_V 0x000003ff #define SENS_TOUCH_PAD_WORKEN_S 0 /* SENS_SAR_READ_CTRL2_REG register */ #define SENS_SAR_READ_CTRL2_REG (DR_REG_SENS_BASE + 0x90) -/* SENS_SAR2_DATA_INV : R/W; bitpos: [29]; default: 0; */ +/* SENS_SAR2_DATA_INV : RW; bitpos: [29]; default: 0; + * Invert SAR ADC2 data + */ #define SENS_SAR2_DATA_INV (BIT(29)) #define SENS_SAR2_DATA_INV_M (SENS_SAR2_DATA_INV_V << SENS_SAR2_DATA_INV_S) -#define SENS_SAR2_DATA_INV_V 0x1 +#define SENS_SAR2_DATA_INV_V 0x00000001 #define SENS_SAR2_DATA_INV_S 29 -/* SENS_SAR2_DIG_FORCE : R/W; bitpos: [28]; default: 0; */ +/* SENS_SAR2_DIG_FORCE : RW; bitpos: [28]; default: 0; + * 1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL 0: SAR ADC2 + * controlled by RTC ADC2 CTRL + */ #define SENS_SAR2_DIG_FORCE (BIT(28)) -#define SENS_SAR2_DIG_FORCE_M (SENS_SAR2_DIG_FORCE_V << \ - SENS_SAR2_DIG_FORCE_S) -#define SENS_SAR2_DIG_FORCE_V 0x1 +#define SENS_SAR2_DIG_FORCE_M (SENS_SAR2_DIG_FORCE_V << SENS_SAR2_DIG_FORCE_S) +#define SENS_SAR2_DIG_FORCE_V 0x00000001 #define SENS_SAR2_DIG_FORCE_S 28 -/* SENS_SAR2_SAMPLE_BIT : R/W; bitpos: [17:16]; default: 3; */ +/* SENS_SAR2_PWDET_FORCE : RW; bitpos: [27]; default: 0; */ + +#define SENS_SAR2_PWDET_FORCE (BIT(27)) +#define SENS_SAR2_PWDET_FORCE_M (SENS_SAR2_PWDET_FORCE_V << SENS_SAR2_PWDET_FORCE_S) +#define SENS_SAR2_PWDET_FORCE_V 0x00000001 +#define SENS_SAR2_PWDET_FORCE_S 27 + +/* SENS_SAR2_SAMPLE_NUM : RW; bitpos: [26:19]; default: 0; */ + +#define SENS_SAR2_SAMPLE_NUM 0x000000ff +#define SENS_SAR2_SAMPLE_NUM_M (SENS_SAR2_SAMPLE_NUM_V << SENS_SAR2_SAMPLE_NUM_S) +#define SENS_SAR2_SAMPLE_NUM_V 0x000000ff +#define SENS_SAR2_SAMPLE_NUM_S 19 + +/* SENS_SAR2_CLK_GATED : RW; bitpos: [18]; default: 1; */ + +#define SENS_SAR2_CLK_GATED (BIT(18)) +#define SENS_SAR2_CLK_GATED_M (SENS_SAR2_CLK_GATED_V << SENS_SAR2_CLK_GATED_S) +#define SENS_SAR2_CLK_GATED_V 0x00000001 +#define SENS_SAR2_CLK_GATED_S 18 + +/* SENS_SAR2_SAMPLE_BIT : RW; bitpos: [17:16]; default: 3; + * 00: for 9-bit width 01: for 10-bit width 10: for 11-bit width 11: for + * 12-bit width + */ #define SENS_SAR2_SAMPLE_BIT 0x00000003 -#define SENS_SAR2_SAMPLE_BIT_M (SENS_SAR2_SAMPLE_BIT_V << \ - SENS_SAR2_SAMPLE_BIT_S) -#define SENS_SAR2_SAMPLE_BIT_V 0x3 +#define SENS_SAR2_SAMPLE_BIT_M (SENS_SAR2_SAMPLE_BIT_V << SENS_SAR2_SAMPLE_BIT_S) +#define SENS_SAR2_SAMPLE_BIT_V 0x00000003 #define SENS_SAR2_SAMPLE_BIT_S 16 -/* SENS_SAR2_SAMPLE_CYCLE : R/W; bitpos: [15:8]; default: 9; */ +/* SENS_SAR2_SAMPLE_CYCLE : RW; bitpos: [15:8]; default: 9; + * sample cycles for SAR ADC2 + */ #define SENS_SAR2_SAMPLE_CYCLE 0x000000ff -#define SENS_SAR2_SAMPLE_CYCLE_M (SENS_SAR2_SAMPLE_CYCLE_V << \ - SENS_SAR2_SAMPLE_CYCLE_S) -#define SENS_SAR2_SAMPLE_CYCLE_V 0xff +#define SENS_SAR2_SAMPLE_CYCLE_M (SENS_SAR2_SAMPLE_CYCLE_V << SENS_SAR2_SAMPLE_CYCLE_S) +#define SENS_SAR2_SAMPLE_CYCLE_V 0x000000ff #define SENS_SAR2_SAMPLE_CYCLE_S 8 -/* SENS_SAR2_CLK_DIV : R/W; bitpos: [7:0]; default: 2; */ +/* SENS_SAR2_CLK_DIV : RW; bitpos: [7:0]; default: 2; + * clock divider + */ #define SENS_SAR2_CLK_DIV 0x000000ff #define SENS_SAR2_CLK_DIV_M (SENS_SAR2_CLK_DIV_V << SENS_SAR2_CLK_DIV_S) -#define SENS_SAR2_CLK_DIV_V 0xff +#define SENS_SAR2_CLK_DIV_V 0x000000ff #define SENS_SAR2_CLK_DIV_S 0 /* SENS_SAR_MEAS_START2_REG register */ #define SENS_SAR_MEAS_START2_REG (DR_REG_SENS_BASE + 0x94) -/* SENS_SAR2_EN_PAD_FORCE : R/W; bitpos: [31]; default: 0; */ +/* SENS_SAR2_EN_PAD_FORCE : RW; bitpos: [31]; default: 0; + * 1: SAR ADC2 pad enable bitmap is controlled by SW 0: SAR ADC2 pad enable + * bitmap is controlled by ULP-coprocessor + */ #define SENS_SAR2_EN_PAD_FORCE (BIT(31)) -#define SENS_SAR2_EN_PAD_FORCE_M (SENS_SAR2_EN_PAD_FORCE_V << \ - SENS_SAR2_EN_PAD_FORCE_S) -#define SENS_SAR2_EN_PAD_FORCE_V 0x1 +#define SENS_SAR2_EN_PAD_FORCE_M (SENS_SAR2_EN_PAD_FORCE_V << SENS_SAR2_EN_PAD_FORCE_S) +#define SENS_SAR2_EN_PAD_FORCE_V 0x00000001 #define SENS_SAR2_EN_PAD_FORCE_S 31 -/* SENS_SAR2_EN_PAD : R/W; bitpos: [30:19]; default: 0; */ +/* SENS_SAR2_EN_PAD : RW; bitpos: [30:19]; default: 0; + * SAR ADC2 pad enable bitmap only active when reg_sar2_en_pad_force = 1 + */ -#define SENS_SAR2_EN_PAD 0x000003ff +#define SENS_SAR2_EN_PAD 0x00000fff #define SENS_SAR2_EN_PAD_M (SENS_SAR2_EN_PAD_V << SENS_SAR2_EN_PAD_S) -#define SENS_SAR2_EN_PAD_V 0x3ff +#define SENS_SAR2_EN_PAD_V 0x00000fff #define SENS_SAR2_EN_PAD_S 19 -/* SENS_MEAS2_START_FORCE : R/W; bitpos: [18]; default: 0; */ +/* SENS_MEAS2_START_FORCE : RW; bitpos: [18]; default: 0; + * 1: SAR ADC2 controller (in RTC) is started by SW 0: SAR ADC2 controller + * is started by ULP-coprocessor + */ #define SENS_MEAS2_START_FORCE (BIT(18)) -#define SENS_MEAS2_START_FORCE_M (SENS_MEAS2_START_FORCE_V << \ - SENS_MEAS2_START_FORCE_S) -#define SENS_MEAS2_START_FORCE_V 0x1 +#define SENS_MEAS2_START_FORCE_M (SENS_MEAS2_START_FORCE_V << SENS_MEAS2_START_FORCE_S) +#define SENS_MEAS2_START_FORCE_V 0x00000001 #define SENS_MEAS2_START_FORCE_S 18 -/* SENS_MEAS2_START_SAR : R/W; bitpos: [17]; default: 0; */ +/* SENS_MEAS2_START_SAR : RW; bitpos: [17]; default: 0; + * SAR ADC2 controller (in RTC) starts conversion only active when + * reg_meas2_start_force = 1 + */ #define SENS_MEAS2_START_SAR (BIT(17)) -#define SENS_MEAS2_START_SAR_M (SENS_MEAS2_START_SAR_V << \ - SENS_MEAS2_START_SAR_S) -#define SENS_MEAS2_START_SAR_V 0x1 +#define SENS_MEAS2_START_SAR_M (SENS_MEAS2_START_SAR_V << SENS_MEAS2_START_SAR_S) +#define SENS_MEAS2_START_SAR_V 0x00000001 #define SENS_MEAS2_START_SAR_S 17 -/* SENS_MEAS2_DONE_SAR : RO; bitpos: [16]; default: 0; */ +/* SENS_MEAS2_DONE_SAR : R; bitpos: [16]; default: 0; + * SAR ADC2 conversion done indication + */ #define SENS_MEAS2_DONE_SAR (BIT(16)) -#define SENS_MEAS2_DONE_SAR_M (SENS_MEAS2_DONE_SAR_V << \ - SENS_MEAS2_DONE_SAR_S) -#define SENS_MEAS2_DONE_SAR_V 0x1 +#define SENS_MEAS2_DONE_SAR_M (SENS_MEAS2_DONE_SAR_V << SENS_MEAS2_DONE_SAR_S) +#define SENS_MEAS2_DONE_SAR_V 0x00000001 #define SENS_MEAS2_DONE_SAR_S 16 -/* SENS_MEAS2_DATA_SAR : RO; bitpos: [15:0]; default: 0; */ +/* SENS_MEAS2_DATA_SAR : R; bitpos: [15:0]; default: 0; + * SAR ADC2 data + */ #define SENS_MEAS2_DATA_SAR 0x0000ffff -#define SENS_MEAS2_DATA_SAR_M (SENS_MEAS2_DATA_SAR_V << \ - SENS_MEAS2_DATA_SAR_S) -#define SENS_MEAS2_DATA_SAR_V 0xffff +#define SENS_MEAS2_DATA_SAR_M (SENS_MEAS2_DATA_SAR_V << SENS_MEAS2_DATA_SAR_S) +#define SENS_MEAS2_DATA_SAR_V 0x0000ffff #define SENS_MEAS2_DATA_SAR_S 0 /* SENS_SAR_DAC_CTRL1_REG register */ #define SENS_SAR_DAC_CTRL1_REG (DR_REG_SENS_BASE + 0x98) -/* SENS_DAC_CLK_INV : R/W; bitpos: [25]; default: 0; */ +/* SENS_DAC_CLK_INV : RW; bitpos: [25]; default: 0; + * 1: invert PDAC_CLK + */ #define SENS_DAC_CLK_INV (BIT(25)) #define SENS_DAC_CLK_INV_M (SENS_DAC_CLK_INV_V << SENS_DAC_CLK_INV_S) -#define SENS_DAC_CLK_INV_V 0x1 +#define SENS_DAC_CLK_INV_V 0x00000001 #define SENS_DAC_CLK_INV_S 25 -/* SENS_DAC_CLK_FORCE_HIGH : R/W; bitpos: [24]; default: 0; */ +/* SENS_DAC_CLK_FORCE_HIGH : RW; bitpos: [24]; default: 0; + * 1: force PDAC_CLK to high + */ #define SENS_DAC_CLK_FORCE_HIGH (BIT(24)) -#define SENS_DAC_CLK_FORCE_HIGH_M (SENS_DAC_CLK_FORCE_HIGH_V << \ - SENS_DAC_CLK_FORCE_HIGH_S) -#define SENS_DAC_CLK_FORCE_HIGH_V 0x1 +#define SENS_DAC_CLK_FORCE_HIGH_M (SENS_DAC_CLK_FORCE_HIGH_V << SENS_DAC_CLK_FORCE_HIGH_S) +#define SENS_DAC_CLK_FORCE_HIGH_V 0x00000001 #define SENS_DAC_CLK_FORCE_HIGH_S 24 -/* SENS_DAC_CLK_FORCE_LOW : R/W; bitpos: [23]; default: 0; */ +/* SENS_DAC_CLK_FORCE_LOW : RW; bitpos: [23]; default: 0; + * 1: force PDAC_CLK to low + */ #define SENS_DAC_CLK_FORCE_LOW (BIT(23)) -#define SENS_DAC_CLK_FORCE_LOW_M (SENS_DAC_CLK_FORCE_LOW_V << \ - SENS_DAC_CLK_FORCE_LOW_S) -#define SENS_DAC_CLK_FORCE_LOW_V 0x1 +#define SENS_DAC_CLK_FORCE_LOW_M (SENS_DAC_CLK_FORCE_LOW_V << SENS_DAC_CLK_FORCE_LOW_S) +#define SENS_DAC_CLK_FORCE_LOW_V 0x00000001 #define SENS_DAC_CLK_FORCE_LOW_S 23 -/* SENS_DAC_DIG_FORCE : R/W; bitpos: [22]; default: 0; */ +/* SENS_DAC_DIG_FORCE : RW; bitpos: [22]; default: 0; + * 1: DAC1 & DAC2 use DMA 0: DAC1 & DAC2 do not use DMA + */ #define SENS_DAC_DIG_FORCE (BIT(22)) #define SENS_DAC_DIG_FORCE_M (SENS_DAC_DIG_FORCE_V << SENS_DAC_DIG_FORCE_S) -#define SENS_DAC_DIG_FORCE_V 0x1 +#define SENS_DAC_DIG_FORCE_V 0x00000001 #define SENS_DAC_DIG_FORCE_S 22 -/* SENS_SW_TONE_EN : R/W; bitpos: [16]; default: 0; */ +/* SENS_DEBUG_BIT_SEL : RW; bitpos: [21:17]; default: 0; */ + +#define SENS_DEBUG_BIT_SEL 0x0000001f +#define SENS_DEBUG_BIT_SEL_M (SENS_DEBUG_BIT_SEL_V << SENS_DEBUG_BIT_SEL_S) +#define SENS_DEBUG_BIT_SEL_V 0x0000001f +#define SENS_DEBUG_BIT_SEL_S 17 + +/* SENS_SW_TONE_EN : RW; bitpos: [16]; default: 0; + * 1: enable CW generator 0: disable CW generator + */ #define SENS_SW_TONE_EN (BIT(16)) #define SENS_SW_TONE_EN_M (SENS_SW_TONE_EN_V << SENS_SW_TONE_EN_S) -#define SENS_SW_TONE_EN_V 0x1 +#define SENS_SW_TONE_EN_V 0x00000001 #define SENS_SW_TONE_EN_S 16 -/* SENS_SW_FSTEP : R/W; bitpos: [15:0]; default: 0; */ +/* SENS_SW_FSTEP : RW; bitpos: [15:0]; default: 0; + * frequency step for CW generator can be used to adjust the frequency + */ #define SENS_SW_FSTEP 0x0000ffff #define SENS_SW_FSTEP_M (SENS_SW_FSTEP_V << SENS_SW_FSTEP_S) -#define SENS_SW_FSTEP_V 0xffff +#define SENS_SW_FSTEP_V 0x0000ffff #define SENS_SW_FSTEP_S 0 /* SENS_SAR_DAC_CTRL2_REG register */ #define SENS_SAR_DAC_CTRL2_REG (DR_REG_SENS_BASE + 0x9c) -/* SENS_DAC_CW_EN2 : R/W; bitpos: [25]; default: 1; */ +/* SENS_DAC_CW_EN2 : RW; bitpos: [25]; default: 1; + * 1: to select CW generator as source to PDAC2_DAC[7:0] 0: to select + * register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0] + */ #define SENS_DAC_CW_EN2 (BIT(25)) #define SENS_DAC_CW_EN2_M (SENS_DAC_CW_EN2_V << SENS_DAC_CW_EN2_S) -#define SENS_DAC_CW_EN2_V 0x1 +#define SENS_DAC_CW_EN2_V 0x00000001 #define SENS_DAC_CW_EN2_S 25 -/* SENS_DAC_CW_EN1 : R/W; bitpos: [24]; default: 1; */ +/* SENS_DAC_CW_EN1 : RW; bitpos: [24]; default: 1; + * 1: to select CW generator as source to PDAC1_DAC[7:0] 0: to select + * register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0] + */ #define SENS_DAC_CW_EN1 (BIT(24)) #define SENS_DAC_CW_EN1_M (SENS_DAC_CW_EN1_V << SENS_DAC_CW_EN1_S) -#define SENS_DAC_CW_EN1_V 0x1 +#define SENS_DAC_CW_EN1_V 0x00000001 #define SENS_DAC_CW_EN1_S 24 -/* SENS_DAC_INV2 : R/W; bitpos: [23:22]; default: 0; */ +/* SENS_DAC_INV2 : RW; bitpos: [23:22]; default: 0; + * 00: do not invert any bits 01: invert all bits 10: invert MSB 11: + * invert all bits except MSB + */ #define SENS_DAC_INV2 0x00000003 #define SENS_DAC_INV2_M (SENS_DAC_INV2_V << SENS_DAC_INV2_S) -#define SENS_DAC_INV2_V 0x3 +#define SENS_DAC_INV2_V 0x00000003 #define SENS_DAC_INV2_S 22 -/* SENS_DAC_INV1 : R/W; bitpos: [21:20]; default: 0; */ +/* SENS_DAC_INV1 : RW; bitpos: [21:20]; default: 0; + * 00: do not invert any bits 01: invert all bits 10: invert MSB 11: + * invert all bits except MSB + */ #define SENS_DAC_INV1 0x00000003 #define SENS_DAC_INV1_M (SENS_DAC_INV1_V << SENS_DAC_INV1_S) -#define SENS_DAC_INV1_V 0x3 +#define SENS_DAC_INV1_V 0x00000003 #define SENS_DAC_INV1_S 20 -/* SENS_DAC_SCALE2 : R/W; bitpos: [19:18]; default: 0; */ +/* SENS_DAC_SCALE2 : RW; bitpos: [19:18]; default: 0; + * 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8 + */ #define SENS_DAC_SCALE2 0x00000003 #define SENS_DAC_SCALE2_M (SENS_DAC_SCALE2_V << SENS_DAC_SCALE2_S) -#define SENS_DAC_SCALE2_V 0x3 +#define SENS_DAC_SCALE2_V 0x00000003 #define SENS_DAC_SCALE2_S 18 -/* SENS_DAC_SCALE1 : R/W; bitpos: [17:16]; default: 0; */ +/* SENS_DAC_SCALE1 : RW; bitpos: [17:16]; default: 0; + * 00: no scale 01: scale to 1/2 10: scale to 1/4 scale to 1/8 + */ #define SENS_DAC_SCALE1 0x00000003 #define SENS_DAC_SCALE1_M (SENS_DAC_SCALE1_V << SENS_DAC_SCALE1_S) -#define SENS_DAC_SCALE1_V 0x3 +#define SENS_DAC_SCALE1_V 0x00000003 #define SENS_DAC_SCALE1_S 16 -/* SENS_DAC_DC2 : R/W; bitpos: [15:8]; default: 0; */ +/* SENS_DAC_DC2 : RW; bitpos: [15:8]; default: 0; + * DC offset for DAC2 CW generator + */ #define SENS_DAC_DC2 0x000000ff #define SENS_DAC_DC2_M (SENS_DAC_DC2_V << SENS_DAC_DC2_S) -#define SENS_DAC_DC2_V 0xff +#define SENS_DAC_DC2_V 0x000000ff #define SENS_DAC_DC2_S 8 -/* SENS_DAC_DC1 : R/W; bitpos: [7:0]; default: 0; */ +/* SENS_DAC_DC1 : RW; bitpos: [7:0]; default: 0; + * DC offset for DAC1 CW generator + */ #define SENS_DAC_DC1 0x000000ff #define SENS_DAC_DC1_M (SENS_DAC_DC1_V << SENS_DAC_DC1_S) -#define SENS_DAC_DC1_V 0xff +#define SENS_DAC_DC1_V 0x000000ff #define SENS_DAC_DC1_S 0 +/* SENS_SAR_MEAS_CTRL2_REG register */ + +#define SENS_SAR_MEAS_CTRL2_REG (DR_REG_SENS_BASE + 0xa0) + +/* SENS_AMP_SHORT_REF_GND_FORCE : RW; bitpos: [18:17]; default: 0; */ + +#define SENS_AMP_SHORT_REF_GND_FORCE 0x00000003 +#define SENS_AMP_SHORT_REF_GND_FORCE_M (SENS_AMP_SHORT_REF_GND_FORCE_V << SENS_AMP_SHORT_REF_GND_FORCE_S) +#define SENS_AMP_SHORT_REF_GND_FORCE_V 0x00000003 +#define SENS_AMP_SHORT_REF_GND_FORCE_S 17 + +/* SENS_AMP_SHORT_REF_FORCE : RW; bitpos: [16:15]; default: 0; */ + +#define SENS_AMP_SHORT_REF_FORCE 0x00000003 +#define SENS_AMP_SHORT_REF_FORCE_M (SENS_AMP_SHORT_REF_FORCE_V << SENS_AMP_SHORT_REF_FORCE_S) +#define SENS_AMP_SHORT_REF_FORCE_V 0x00000003 +#define SENS_AMP_SHORT_REF_FORCE_S 15 + +/* SENS_AMP_RST_FB_FORCE : RW; bitpos: [14:13]; default: 0; */ + +#define SENS_AMP_RST_FB_FORCE 0x00000003 +#define SENS_AMP_RST_FB_FORCE_M (SENS_AMP_RST_FB_FORCE_V << SENS_AMP_RST_FB_FORCE_S) +#define SENS_AMP_RST_FB_FORCE_V 0x00000003 +#define SENS_AMP_RST_FB_FORCE_S 13 + +/* SENS_SAR2_RSTB_FORCE : RW; bitpos: [12:11]; default: 0; */ + +#define SENS_SAR2_RSTB_FORCE 0x00000003 +#define SENS_SAR2_RSTB_FORCE_M (SENS_SAR2_RSTB_FORCE_V << SENS_SAR2_RSTB_FORCE_S) +#define SENS_SAR2_RSTB_FORCE_V 0x00000003 +#define SENS_SAR2_RSTB_FORCE_S 11 + +/* SENS_SAR_RSTB_FSM_IDLE : RW; bitpos: [10]; default: 0; */ + +#define SENS_SAR_RSTB_FSM_IDLE (BIT(10)) +#define SENS_SAR_RSTB_FSM_IDLE_M (SENS_SAR_RSTB_FSM_IDLE_V << SENS_SAR_RSTB_FSM_IDLE_S) +#define SENS_SAR_RSTB_FSM_IDLE_V 0x00000001 +#define SENS_SAR_RSTB_FSM_IDLE_S 10 + +/* SENS_XPD_SAR_FSM_IDLE : RW; bitpos: [9]; default: 0; */ + +#define SENS_XPD_SAR_FSM_IDLE (BIT(9)) +#define SENS_XPD_SAR_FSM_IDLE_M (SENS_XPD_SAR_FSM_IDLE_V << SENS_XPD_SAR_FSM_IDLE_S) +#define SENS_XPD_SAR_FSM_IDLE_V 0x00000001 +#define SENS_XPD_SAR_FSM_IDLE_S 9 + +/* SENS_AMP_SHORT_REF_GND_FSM_IDLE : RW; bitpos: [8]; default: 0; */ + +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE (BIT(8)) +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_M (SENS_AMP_SHORT_REF_GND_FSM_IDLE_V << SENS_AMP_SHORT_REF_GND_FSM_IDLE_S) +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_V 0x00000001 +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_S 8 + +/* SENS_AMP_SHORT_REF_FSM_IDLE : RW; bitpos: [7]; default: 0; */ + +#define SENS_AMP_SHORT_REF_FSM_IDLE (BIT(7)) +#define SENS_AMP_SHORT_REF_FSM_IDLE_M (SENS_AMP_SHORT_REF_FSM_IDLE_V << SENS_AMP_SHORT_REF_FSM_IDLE_S) +#define SENS_AMP_SHORT_REF_FSM_IDLE_V 0x00000001 +#define SENS_AMP_SHORT_REF_FSM_IDLE_S 7 + +/* SENS_AMP_RST_FB_FSM_IDLE : RW; bitpos: [6]; default: 0; */ + +#define SENS_AMP_RST_FB_FSM_IDLE (BIT(6)) +#define SENS_AMP_RST_FB_FSM_IDLE_M (SENS_AMP_RST_FB_FSM_IDLE_V << SENS_AMP_RST_FB_FSM_IDLE_S) +#define SENS_AMP_RST_FB_FSM_IDLE_V 0x00000001 +#define SENS_AMP_RST_FB_FSM_IDLE_S 6 + +/* SENS_XPD_SAR_AMP_FSM_IDLE : RW; bitpos: [5]; default: 0; */ + +#define SENS_XPD_SAR_AMP_FSM_IDLE (BIT(5)) +#define SENS_XPD_SAR_AMP_FSM_IDLE_M (SENS_XPD_SAR_AMP_FSM_IDLE_V << SENS_XPD_SAR_AMP_FSM_IDLE_S) +#define SENS_XPD_SAR_AMP_FSM_IDLE_V 0x00000001 +#define SENS_XPD_SAR_AMP_FSM_IDLE_S 5 + +/* SENS_SAR1_DAC_XPD_FSM_IDLE : RW; bitpos: [4]; default: 0; */ + +#define SENS_SAR1_DAC_XPD_FSM_IDLE (BIT(4)) +#define SENS_SAR1_DAC_XPD_FSM_IDLE_M (SENS_SAR1_DAC_XPD_FSM_IDLE_V << SENS_SAR1_DAC_XPD_FSM_IDLE_S) +#define SENS_SAR1_DAC_XPD_FSM_IDLE_V 0x00000001 +#define SENS_SAR1_DAC_XPD_FSM_IDLE_S 4 + +/* SENS_SAR1_DAC_XPD_FSM : RW; bitpos: [3:0]; default: 3; */ + +#define SENS_SAR1_DAC_XPD_FSM 0x0000000f +#define SENS_SAR1_DAC_XPD_FSM_M (SENS_SAR1_DAC_XPD_FSM_V << SENS_SAR1_DAC_XPD_FSM_S) +#define SENS_SAR1_DAC_XPD_FSM_V 0x0000000f +#define SENS_SAR1_DAC_XPD_FSM_S 0 + +/* SENS_SAR_NOUSE_REG register */ + +#define SENS_SAR_NOUSE_REG (DR_REG_SENS_BASE + 0xf8) + +/* SENS_SAR_NOUSE : RW; bitpos: [31:0]; default: 0; */ + +#define SENS_SAR_NOUSE 0xffffffff +#define SENS_SAR_NOUSE_M (SENS_SAR_NOUSE_V << SENS_SAR_NOUSE_S) +#define SENS_SAR_NOUSE_V 0xffffffff +#define SENS_SAR_NOUSE_S 0 + +/* SENS_SARDATE_REG register */ + +#define SENS_SARDATE_REG (DR_REG_SENS_BASE + 0xfc) + +/* SENS_SAR_DATE : RW; bitpos: [27:0]; default: 23089536; */ + +#define SENS_SAR_DATE 0x0fffffff +#define SENS_SAR_DATE_M (SENS_SAR_DATE_V << SENS_SAR_DATE_S) +#define SENS_SAR_DATE_V 0x0fffffff +#define SENS_SAR_DATE_S 0 + #endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SENS_H */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_soc.h b/arch/xtensa/src/esp32/hardware/esp32_soc.h index 1128e4a49cbd7..a1f1ad67a5f81 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_soc.h +++ b/arch/xtensa/src/esp32/hardware/esp32_soc.h @@ -29,8 +29,12 @@ #include #include "xtensa_attr.h" +#include "hardware/esp32_efuse.h" + #include +#include "soc/soc.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -75,113 +79,6 @@ /* Registers Operation */ -#define ETS_UNCACHED_ADDR(addr) (addr) -#define ETS_CACHED_ADDR(addr) (addr) - -/* Write value to register */ - -#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) - -/* Read value from register */ - -#define REG_READ(_r) (*(volatile uint32_t *)(_r)) - -/* Get bit or get bits from register */ - -#define REG_GET_BIT(_r, _b) (*(volatile uint32_t*)(_r) & (_b)) - -/* Set bit or set bits to register */ - -#define REG_SET_BIT(_r, _b) (*(volatile uint32_t*)(_r) |= (_b)) - -/* Clear bit or clear bits of register */ - -#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t*)(_r) &= ~(_b)) - -/* Set bits of register controlled by mask */ - -#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))) - -/* Get field from register, - * used when _f is not left shifted by _f##_S - */ - -#define REG_GET_FIELD(addr, field) ((getreg32(addr) >> (field##_S)) & (field##_V)) - -/* Set field to register, - * used when _f is not left shifted by _f##_S - */ - -#define REG_SET_FIELD(addr, field, val) (modifyreg32((addr), (field##_M), (((uint32_t) val) & (field##_V)) << (field##_S))) - -/* Set field value from a variable, - * used when _f is not left shifted by _f##_S - */ - -#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) - -/* Get field value from a variable, - * used when _f is left shifted by _f##_S - */ - -#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) - -/* Set field value to a variable, - * used when _f is not left shifted by _f##_S - */ - -#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) - -/* Set field value to a variable, - * used when _f is left shifted by _f##_S - */ - -#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) - -/* Generate a value from a field value, - * used when _f is not left shifted by _f##_S - */ - -#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) - -/* Generate a value from a field value, - * used when _f is left shifted by _f##_S - */ - -#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) - -/* Read value from register */ - -#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) - -/* Write value to register */ - -#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val) - -/* Clear bits of register controlled by mask */ - -#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))) - -/* Set bits of register controlled by mask */ - -#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))) - -/* Get bits of register controlled by mask */ - -#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask)) - -/* Get bits of register controlled by highest bit and lowest bit */ - -#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) - -/* Set bits of register controlled by mask and shift */ - -#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )) - -/* Get field of register */ - -#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask)) - /* Extract the field from the register and shift it to avoid wrong reading */ #define REG_MASK(_reg, _field) (((_reg) & (_field##_M)) >> (_field##_S)) @@ -192,65 +89,15 @@ /* Periheral Clock */ -#define APB_CLK_FREQ_ROM 26 * 1000000 #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM #define CPU_CLK_FREQ APB_CLK_FREQ -#define APB_CLK_FREQ 80 * 1000000 /* Unit: Hz */ -#define REF_CLK_FREQ (1000000) #define UART_CLK_FREQ APB_CLK_FREQ #define MWDT_CLK_FREQ APB_CLK_FREQ -#define TIMER_CLK_FREQ (80000000 >> 4) /* 80MHz divided by 16 */ #define SPI_CLK_DIV 4 #define TICKS_PER_US_ROM 26 /* CPU is 80MHz */ -#define DR_REG_DPORT_BASE 0x3ff00000 -#define DR_REG_UART_BASE 0x3ff40000 -#define DR_REG_SPI1_BASE 0x3ff42000 -#define DR_REG_SPI0_BASE 0x3ff43000 -#define DR_REG_GPIO_BASE 0x3ff44000 -#define DR_REG_GPIO_SD_BASE 0x3ff44f00 -#define DR_REG_FE2_BASE 0x3ff45000 -#define DR_REG_FE_BASE 0x3ff46000 -#define DR_REG_FRC_TIMER_BASE 0x3ff47000 -#define DR_REG_RTCCNTL_BASE 0x3ff48000 -#define DR_REG_RTCIO_BASE 0x3ff48400 -#define DR_REG_SENS_BASE 0x3ff48800 -#define DR_REG_IO_MUX_BASE 0x3ff49000 -#define DR_REG_EFUSE_BASE 0x3ff5a000 -#define DR_REG_RTCMEM0_BASE 0x3ff61000 -#define DR_REG_RTCMEM1_BASE 0x3ff62000 -#define DR_REG_RTCMEM2_BASE 0x3ff63000 -#define DR_REG_HINF_BASE 0x3ff4b000 -#define DR_REG_UHCI1_BASE 0x3ff4c000 -#define DR_REG_I2S_BASE 0x3ff4f000 -#define DR_REG_UART1_BASE 0x3ff50000 -#define DR_REG_BT_BASE 0x3ff51000 -#define DR_REG_I2C_EXT_BASE 0x3ff53000 -#define DR_REG_UHCI0_BASE 0x3ff54000 -#define DR_REG_SLCHOST_BASE 0x3ff55000 -#define DR_REG_RMT_BASE 0x3ff56000 -#define DR_REG_PCNT_BASE 0x3ff57000 -#define DR_REG_SLC_BASE 0x3ff58000 -#define DR_REG_LEDC_BASE 0x3ff59000 -#define DR_REG_EFUSE_BASE 0x3ff5a000 -#define DR_REG_SPI_ENCRYPT_BASE 0x3ff5b000 -#define DR_REG_NRX_BASE 0x3ff5cc00 -#define DR_REG_BB_BASE 0x3ff5d000 -#define DR_REG_PWM_BASE 0x3ff5e000 -#define DR_REG_TIMERGROUP0_BASE 0x3ff5f000 -#define DR_REG_TIMERGROUP1_BASE 0x3ff60000 -#define DR_REG_SPI2_BASE 0x3ff64000 -#define DR_REG_SPI3_BASE 0x3ff65000 -#define DR_REG_I2C1_EXT_BASE 0x3ff67000 -#define DR_REG_SDMMC_BASE 0x3ff68000 -#define DR_REG_EMAC_BASE 0x3ff69000 -#define DR_REG_TWAI_BASE 0x3ff6b000 -#define DR_REG_CAN_BASE DR_REG_TWAI_BASE -#define DR_REG_PWM1_BASE 0x3ff6c000 -#define DR_REG_I2S1_BASE 0x3ff6d000 -#define DR_REG_UART2_BASE 0x3ff6e000 -#define DR_REG_PWM2_BASE 0x3ff6f000 -#define DR_REG_PWM3_BASE 0x3ff70000 +#define DR_REG_TWAI_BASE DR_REG_CAN_BASE + #define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE /* Some AHB addresses can be used instead of DPORT addresses @@ -264,110 +111,14 @@ /* Overall memory map */ -#define SOC_DROM_LOW 0x3f400000 -#define SOC_DROM_HIGH 0x3f800000 -#define SOC_DRAM_LOW 0x3ffae000 -#define SOC_DRAM_HIGH 0x40000000 -#define SOC_IROM_LOW 0x400d0000 -#define SOC_IROM_HIGH 0x40400000 -#define SOC_IROM_MASK_LOW 0x40000000 -#define SOC_IROM_MASK_HIGH 0x40064f00 -#define SOC_CACHE_PRO_LOW 0x40070000 -#define SOC_CACHE_PRO_HIGH 0x40078000 -#define SOC_CACHE_APP_LOW 0x40078000 -#define SOC_CACHE_APP_HIGH 0x40080000 -#define SOC_IRAM_LOW 0x40080000 -#define SOC_IRAM_HIGH 0x400a0000 -#define SOC_RTC_IRAM_LOW 0x400c0000 -#define SOC_RTC_IRAM_HIGH 0x400c2000 -#define SOC_RTC_DRAM_LOW 0x3ff80000 -#define SOC_RTC_DRAM_HIGH 0x3ff82000 -#define SOC_RTC_SLOW_LOW 0x50000000 -#define SOC_RTC_SLOW_HIGH 0x50002000 -#define SOC_EXTRAM_DATA_LOW 0x3f800000 -#define SOC_EXTRAM_DATA_HIGH 0x3fc00000 +#define SOC_RTC_SLOW_LOW SOC_RTC_DATA_LOW +#define SOC_RTC_SLOW_HIGH SOC_RTC_DATA_HIGH /* Virtual address 0 */ #define VADDR0_START_ADDR SOC_DROM_LOW #define VADDR0_END_ADDR (SOC_DROM_HIGH - 1) -/* Interrupt hardware source table - * This table is decided by hardware, don't touch this. - */ - -#define ETS_WIFI_MAC_INTR_SOURCE 0 /* Interrupt of Wi-Fi MAC, level */ -#define ETS_WIFI_MAC_NMI_SOURCE 1 /* Interrupt of Wi-Fi MAC, NMI, use if MAC have bug to fix in NMI */ -#define ETS_WIFI_BB_INTR_SOURCE 2 /* Interrupt of Wi-Fi BB, level, we can do some calibartion */ -#define ETS_BT_MAC_INTR_SOURCE 3 /* will be cancelled */ -#define ETS_BT_BB_INTR_SOURCE 4 /* Interrupt of BT BB, level */ -#define ETS_BT_BB_NMI_SOURCE 5 /* Interrupt of BT BB, NMI, use if BB have bug to fix in NMI */ -#define ETS_RWBT_INTR_SOURCE 6 /* Interrupt of RWBT, level */ -#define ETS_RWBLE_INTR_SOURCE 7 /* Interrupt of RWBLE, level */ -#define ETS_RWBT_NMI_SOURCE 8 /* Interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI */ -#define ETS_RWBLE_NMI_SOURCE 9 /* Interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI */ -#define ETS_SLC0_INTR_SOURCE 10 /* Interrupt of SLC0, level */ -#define ETS_SLC1_INTR_SOURCE 11 /* Interrupt of SLC1, level */ -#define ETS_UHCI0_INTR_SOURCE 12 /* Interrupt of UHCI0, level */ -#define ETS_UHCI1_INTR_SOURCE 13 /* Interrupt of UHCI1, level */ -#define ETS_TG0_T0_LEVEL_INTR_SOURCE 14 /* Interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission */ -#define ETS_TG0_T1_LEVEL_INTR_SOURCE 15 /* Interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission */ -#define ETS_TG0_WDT_LEVEL_INTR_SOURCE 16 /* Interrupt of TIMER_GROUP0, WATCHDOG, level */ -#define ETS_TG0_LACT_LEVEL_INTR_SOURCE 17 /* Interrupt of TIMER_GROUP0, LACT, level */ -#define ETS_TG1_T0_LEVEL_INTR_SOURCE 18 /* Interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission */ -#define ETS_TG1_T1_LEVEL_INTR_SOURCE 19 /* Interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission */ -#define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20 /* Interrupt of TIMER_GROUP1, WATCHDOG, level */ -#define ETS_TG1_LACT_LEVEL_INTR_SOURCE 21 /* Interrupt of TIMER_GROUP1, LACT, level */ -#define ETS_GPIO_INTR_SOURCE 22 /* Interrupt of GPIO, level */ -#define ETS_GPIO_NMI_SOURCE 23 /* Interrupt of GPIO, NMI */ -#define ETS_FROM_CPU_INTR0_SOURCE 24 /* Interrupt0 generated from a CPU, level */ -#define ETS_FROM_CPU_INTR1_SOURCE 25 /* Interrupt1 generated from a CPU, level */ -#define ETS_FROM_CPU_INTR2_SOURCE 26 /* Interrupt2 generated from a CPU, level */ -#define ETS_FROM_CPU_INTR3_SOURCE 27 /* Interrupt3 generated from a CPU, level */ -#define ETS_SPI0_INTR_SOURCE 28 /* Interrupt of SPI0, level, SPI0 is for Cache Access, do not use this */ -#define ETS_SPI1_INTR_SOURCE 29 /* Interrupt of SPI1, level, SPI1 is for flash read/write, do not use this */ -#define ETS_SPI2_INTR_SOURCE 30 /* Interrupt of SPI2, level */ -#define ETS_SPI3_INTR_SOURCE 31 /* Interrupt of SPI3, level */ -#define ETS_I2S0_INTR_SOURCE 32 /* Interrupt of I2S0, level */ -#define ETS_I2S1_INTR_SOURCE 33 /* Interrupt of I2S1, level */ -#define ETS_UART0_INTR_SOURCE 34 /* Interrupt of UART0, level */ -#define ETS_UART1_INTR_SOURCE 35 /* Interrupt of UART1, level */ -#define ETS_UART2_INTR_SOURCE 36 /* Interrupt of UART2, level */ -#define ETS_SDIO_HOST_INTR_SOURCE 37 /* Interrupt of SD/SDIO/MMC HOST, level */ -#define ETS_ETH_MAC_INTR_SOURCE 38 /* Interrupt of ethernet mac, level */ -#define ETS_PWM0_INTR_SOURCE 39 /* Interrupt of PWM0, level, Reserved */ -#define ETS_PWM1_INTR_SOURCE 40 /* Interrupt of PWM1, level, Reserved */ -#define ETS_PWM2_INTR_SOURCE 41 /* Interrupt of PWM2, level */ -#define ETS_PWM3_INTR_SOURCE 42 /* Interruot of PWM3, level */ -#define ETS_LEDC_INTR_SOURCE 43 /* Interrupt of LED PWM, level */ -#define ETS_EFUSE_INTR_SOURCE 44 /* Interrupt of efuse, level, not likely to use */ -#define ETS_CAN_INTR_SOURCE 45 /* Interrupt of can, level */ -#define ETS_RTC_CORE_INTR_SOURCE 46 /* Interrupt of rtc core, level, include rtc watchdog */ -#define ETS_RMT_INTR_SOURCE 47 /* Interrupt of remote controller, level */ -#define ETS_PCNT_INTR_SOURCE 48 /* Interrupt of pulse count, level */ -#define ETS_I2C_EXT0_INTR_SOURCE 49 /* Interrupt of I2C controller1, level */ -#define ETS_I2C_EXT1_INTR_SOURCE 50 /* Interrupt of I2C controller0, level */ -#define ETS_RSA_INTR_SOURCE 51 /* Interrupt of RSA accelerator, level */ -#define ETS_SPI1_DMA_INTR_SOURCE 52 /* Interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this */ -#define ETS_SPI2_DMA_INTR_SOURCE 53 /* Interrupt of SPI2 DMA, level */ -#define ETS_SPI3_DMA_INTR_SOURCE 54 /* Interrupt of SPI3 DMA, level */ -#define ETS_WDT_INTR_SOURCE 55 /* will be cancelled */ -#define ETS_TIMER1_INTR_SOURCE 56 /* will be cancelled */ -#define ETS_TIMER2_INTR_SOURCE 57 /* will be cancelled */ -#define ETS_TG0_T0_EDGE_INTR_SOURCE 58 /* Interrupt of TIMER_GROUP0, TIMER0, EDGE */ -#define ETS_TG0_T1_EDGE_INTR_SOURCE 59 /* Interrupt of TIMER_GROUP0, TIMER1, EDGE */ -#define ETS_TG0_WDT_EDGE_INTR_SOURCE 60 /* Interrupt of TIMER_GROUP0, WATCH DOG, EDGE */ -#define ETS_TG0_LACT_EDGE_INTR_SOURCE 61 /* Interrupt of TIMER_GROUP0, LACT, EDGE */ -#define ETS_TG1_T0_EDGE_INTR_SOURCE 62 /* Interrupt of TIMER_GROUP1, TIMER0, EDGE */ -#define ETS_TG1_T1_EDGE_INTR_SOURCE 63 /* Interrupt of TIMER_GROUP1, TIMER1, EDGE */ -#define ETS_TG1_WDT_EDGE_INTR_SOURCE 64 /* Interrupt of TIMER_GROUP1, WATCHDOG, EDGE */ -#define ETS_TG1_LACT_EDGE_INTR_SOURCE 65 /* Interrupt of TIMER_GROUP0, LACT, EDGE */ -#define ETS_MMU_IA_INTR_SOURCE 66 /* Interrupt of MMU Invalid Access, LEVEL */ -#define ETS_MPU_IA_INTR_SOURCE 67 /* Interrupt of MPU Invalid Access, LEVEL */ -#define ETS_CACHE_IA_INTR_SOURCE 68 /* Interrupt of Cache Invalied Access, LEVEL */ - -#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010) -#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c) #define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x0038) /* Interrupt cpu using table */ @@ -430,14 +181,6 @@ #define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x0) #define APB_CTRL_XTAL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x4) -/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ - -#define APB_CTRL_PRE_DIV_CNT 0x000003ff -#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V) << \ - (APB_CTRL_PRE_DIV_CNT_S)) -#define APB_CTRL_PRE_DIV_CNT_V 0x3ff -#define APB_CTRL_PRE_DIV_CNT_S 0 - #define I2C_BBPLL_IR_CAL_DELAY 0 #define I2C_BBPLL_IR_CAL_EXT_CAP 1 #define I2C_BBPLL_OC_ENB_FCAL 4 @@ -487,84 +230,6 @@ extern int rom_i2c_writereg(int block, int block_id, int reg_add, #define BBPLL_OC_ENB_VCON_VAL 0x00 #define BBPLL_BBADC_CAL_7_0_VAL 0x00 -#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014) - -/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] */ - -/* description: This field stores the voltage level for - * CPU to run at 240 MHz, or for flash/PSRAM to run at 80 MHz. - * 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO) - */ - -#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03 -#define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V) << (EFUSE_RD_VOL_LEVEL_HP_INV_S)) -#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03 -#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 - -/* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; */ - -/* description: read for sdio_force */ - -#define EFUSE_RD_SDIO_FORCE (BIT(16)) -#define EFUSE_RD_SDIO_FORCE_M (BIT(16)) -#define EFUSE_RD_SDIO_FORCE_V 0x1 -#define EFUSE_RD_SDIO_FORCE_S 16 - -/* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; */ - -/* description: read for XPD_SDIO_REG */ - -#define EFUSE_RD_XPD_SDIO_REG (BIT(14)) -#define EFUSE_RD_XPD_SDIO_REG_M (BIT(14)) -#define EFUSE_RD_XPD_SDIO_REG_V 0x1 -#define EFUSE_RD_XPD_SDIO_REG_S 14 - -/* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; */ - -/* description: read for SDIO_TIEH */ - -#define EFUSE_RD_SDIO_TIEH (BIT(15)) -#define EFUSE_RD_SDIO_TIEH_M (BIT(15)) -#define EFUSE_RD_SDIO_TIEH_V 0x1 -#define EFUSE_RD_SDIO_TIEH_S 15 - -/* EFUSE_RD_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; */ - -/* description: If set, this bit indicates that - * BLOCK3[143:96] is reserved for internal use - */ - -#define EFUSE_RD_BLK3_PART_RESERVE (BIT(14)) -#define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V) << (EFUSE_RD_BLK3_PART_RESERVE_S)) -#define EFUSE_RD_BLK3_PART_RESERVE_V 0x1 -#define EFUSE_RD_BLK3_PART_RESERVE_S 14 - -/* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; */ - -#define EFUSE_RD_SDIO_DREFH 0x00000003 -#define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V) << (EFUSE_RD_SDIO_DREFH_S)) -#define EFUSE_RD_SDIO_DREFH_V 0x3 -#define EFUSE_RD_SDIO_DREFH_S 8 - -/* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; */ - -#define EFUSE_RD_SDIO_DREFM 0x00000003 -#define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V) << (EFUSE_RD_SDIO_DREFM_S)) -#define EFUSE_RD_SDIO_DREFM_V 0x3 -#define EFUSE_RD_SDIO_DREFM_S 10 - -/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. - * Newer versions of ESP32 come with EFUSE_ADC_VREF already burned, - * therefore SDIO_DREFH/M/L is only available in older versions of ESP32 - */ - -/* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; */ - -#define EFUSE_RD_SDIO_DREFL 0x00000003 -#define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V) << (EFUSE_RD_SDIO_DREFL_S)) -#define EFUSE_RD_SDIO_DREFL_V 0x3 -#define EFUSE_RD_SDIO_DREFL_S 12 - #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + i*0x1000) #define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068) diff --git a/arch/xtensa/src/esp32s2/Bootloader.mk b/arch/xtensa/src/esp32s2/Bootloader.mk index 54940e551d989..3a75b427210a0 100644 --- a/arch/xtensa/src/esp32s2/Bootloader.mk +++ b/arch/xtensa/src/esp32s2/Bootloader.mk @@ -187,15 +187,7 @@ else ifeq ($(CONFIG_ESP32S2_BOOTLOADER_DOWNLOAD_PREBUILT),y) BOOTLOADER_VERSION = latest BOOTLOADER_URL = https://github.com/espressif/esp-nuttx-bootloader/releases/download/$(BOOTLOADER_VERSION) -ifeq ($(CONFIG_ESP32S2_APP_FORMAT_MCUBOOT),y) - -bootloader: - $(call DOWNLOAD,$(BOOTLOADER_URL),mcuboot-esp32s2.bin,$(TOPDIR)/mcuboot-esp32s2.bin) - -clean_bootloader: - $(call DELFILE,$(TOPDIR)/mcuboot-esp32s2.bin) - -else ifeq ($(CONFIG_ESP32S2_APP_FORMAT_LEGACY),y) +ifeq ($(CONFIG_ESP32S2_APP_FORMAT_LEGACY),y) bootloader: $(call DOWNLOAD,$(BOOTLOADER_URL),bootloader-esp32s2.bin,$(TOPDIR)/bootloader-esp32s2.bin) diff --git a/arch/xtensa/src/esp32s2/Kconfig b/arch/xtensa/src/esp32s2/Kconfig index 2f37780fda4ac..16e5a62e843aa 100644 --- a/arch/xtensa/src/esp32s2/Kconfig +++ b/arch/xtensa/src/esp32s2/Kconfig @@ -1220,42 +1220,28 @@ config ESP32S2_HAVE_OTA_PARTITION bool default n -menu "Application Image Configuration" - -choice - prompt "Application Image Format" - default ESP32S2_APP_FORMAT_LEGACY - ---help--- - Depending on the chosen 2nd stage bootloader, the application may - be required to be perform a specific startup routine. Furthermore, - the image binary must be formatted according to the definition from - the 2nd stage bootloader. +menu "Bootloader and Image Configuration" config ESP32S2_APP_FORMAT_LEGACY - bool "Legacy format" + bool + default y if !ESP32S2_APP_FORMAT_MCUBOOT + depends on !ESP32S2_APP_FORMAT_MCUBOOT ---help--- This is the legacy application image format, as supported by the ESP-IDF 2nd stage bootloader. config ESP32S2_APP_FORMAT_MCUBOOT - bool "MCUboot-bootable format" + bool "Enable MCUboot-bootable format" depends on !MCUBOOT_BOOTLOADER select ESP32S2_HAVE_OTA_PARTITION + select ESP32S2_BOOTLOADER_BUILD_FROM_SOURCE ---help--- - The Espressif port of MCUboot supports the loading of unsegmented firmware - images. - -endchoice # Application Image Format - -choice - prompt "Source for bootloader binaries" - default ESP32S2_BOOTLOADER_DOWNLOAD_PREBUILT - ---help--- - Select the action to be taken by the build system for the - "make bootloader" target. + Enables the Espressif port of MCUboot to be used as 2nd stage bootloader. config ESP32S2_BOOTLOADER_DOWNLOAD_PREBUILT - bool "Download prebuilt binaries" + bool + default y if !ESP32S2_BOOTLOADER_BUILD_FROM_SOURCE + depends on !ESP32S2_BOOTLOADER_BUILD_FROM_SOURCE ---help--- The build system will download the prebuilt binaries from https://github.com/espressif/esp-nuttx-bootloader according to the chosen @@ -1269,8 +1255,6 @@ config ESP32S2_BOOTLOADER_BUILD_FROM_SOURCE custom bootloader according to the chosen Application Image Format (ESP32S2_APP_FORMAT_LEGACY or ESP32S2_APP_FORMAT_MCUBOOT) and partition information. -endchoice - choice prompt "Target slot for image flashing" default ESP32S2_ESPTOOL_TARGET_PRIMARY @@ -1306,13 +1290,39 @@ config ESP32S2_APP_MCUBOOT_HEADER_SIZE default 32 depends on ESP32S2_APP_FORMAT_MCUBOOT +config ESP32S2_PARTITION_TABLE_OFFSET_DEFAULT + hex + default 0x8000 + depends on ESP32S2_APP_FORMAT_LEGACY + +config ESP32S2_CUSTOM_PARTITION_TABLE_OFFSET + bool "Customize partition table offset" + default n + depends on ESP32S2_APP_FORMAT_LEGACY + select ESP32S2_BOOTLOADER_BUILD_FROM_SOURCE + ---help--- + Enable to select the offset of the partition table in the flash. + +if ESP32S2_CUSTOM_PARTITION_TABLE_OFFSET + config ESP32S2_PARTITION_TABLE_OFFSET hex "Partition Table offset" - default 0x8000 + default ESP32S2_PARTITION_TABLE_OFFSET_DEFAULT depends on ESP32S2_APP_FORMAT_LEGACY +endif # ESP32S2_CUSTOM_PARTITION_TABLE_OFFSET + +if !ESP32S2_CUSTOM_PARTITION_TABLE_OFFSET + +config ESP32S2_PARTITION_TABLE_OFFSET + hex + default ESP32S2_PARTITION_TABLE_OFFSET_DEFAULT + depends on ESP32S2_APP_FORMAT_LEGACY + +endif # !ESP32S2_CUSTOM_PARTITION_TABLE_OFFSET + source "arch/xtensa/src/esp32s2/Kconfig.security" -endmenu # Application Image Configuration +endmenu # Bootloader and Image Configuration endif # ARCH_CHIP_ESP32S2 diff --git a/arch/xtensa/src/esp32s2/esp32s2_libc_stubs.c b/arch/xtensa/src/esp32s2/esp32s2_libc_stubs.c index 2415d83109f4a..49e353fc4bf28 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_libc_stubs.c +++ b/arch/xtensa/src/esp32s2/esp32s2_libc_stubs.c @@ -38,18 +38,12 @@ #include "rom/esp32s2_libc_stubs.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define _lock_t int - /**************************************************************************** * Private Types ****************************************************************************/ -static mutex_t g_nxlock_common; -static mutex_t g_nxlock_recursive; +static mutex_t g_nxlock_common = NXMUTEX_INITIALIZER; +static mutex_t g_nxlock_recursive = NXMUTEX_INITIALIZER; /* Forward declaration */ @@ -171,64 +165,112 @@ void _raise_r(struct _reent *r) void _lock_init(_lock_t *lock) { - nxmutex_init(&g_nxlock_common); - nxsem_get_value(&g_nxlock_common.sem, lock); + *lock = 0; + + mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t)); + + nxmutex_init(mutex); + + *lock = (_lock_t)mutex; } void _lock_init_recursive(_lock_t *lock) { - nxmutex_init(&g_nxlock_recursive); - nxsem_get_value(&g_nxlock_recursive.sem, lock); + *lock = 0; + + rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t)); + + nxrmutex_init(rmutex); + + *lock = (_lock_t)rmutex; } void _lock_close(_lock_t *lock) { - nxmutex_destroy(&g_nxlock_common); + mutex_t *mutex = (mutex_t *)(*lock); + + nxmutex_destroy(mutex); + kmm_free((void *)(*lock)); *lock = 0; } void _lock_close_recursive(_lock_t *lock) { - nxmutex_destroy(&g_nxlock_recursive); + rmutex_t *rmutex = (rmutex_t *)(*lock); + + nxrmutex_destroy(rmutex); + kmm_free((void *)(*lock)); *lock = 0; } void _lock_acquire(_lock_t *lock) { - nxmutex_lock(&g_nxlock_common); - nxsem_get_value(&g_nxlock_common.sem, lock); + if ((*lock) == 0) + { + mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t)); + + nxmutex_init(mutex); + + *lock = (_lock_t)mutex; + } + + nxmutex_lock((mutex_t *)(*lock)); } void _lock_acquire_recursive(_lock_t *lock) { - nxmutex_lock(&g_nxlock_recursive); - nxsem_get_value(&g_nxlock_recursive.sem, lock); + if ((*lock) == 0) + { + rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t)); + + nxrmutex_init(rmutex); + + *lock = (_lock_t)rmutex; + } + + nxrmutex_lock((rmutex_t *)(*lock)); } int _lock_try_acquire(_lock_t *lock) { - nxmutex_trylock(&g_nxlock_common); - nxsem_get_value(&g_nxlock_common.sem, lock); - return 0; + if ((*lock) == 0) + { + mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t)); + + nxmutex_init(mutex); + + *lock = (_lock_t)mutex; + } + + return nxmutex_trylock((mutex_t *)(*lock)); } int _lock_try_acquire_recursive(_lock_t *lock) { - nxmutex_trylock(&g_nxlock_recursive); - nxsem_get_value(&g_nxlock_recursive.sem, lock); - return 0; + if ((*lock) == 0) + { + rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t)); + + nxrmutex_init(rmutex); + + *lock = (_lock_t)rmutex; + } + + return nxrmutex_trylock((rmutex_t *)(*lock)); } void _lock_release(_lock_t *lock) { - nxmutex_unlock(&g_nxlock_common); - nxsem_get_value(&g_nxlock_common.sem, lock); + mutex_t *mutex = (mutex_t *)(*lock); + + nxmutex_unlock(mutex); } void _lock_release_recursive(_lock_t *lock) { - nxmutex_unlock(&g_nxlock_recursive); - nxsem_get_value(&g_nxlock_recursive.sem, lock); + rmutex_t *rmutex = (rmutex_t *)(*lock); + + nxrmutex_unlock(rmutex); } struct _reent *__getreent(void) diff --git a/arch/xtensa/src/esp32s2/esp32s2_lowputc.c b/arch/xtensa/src/esp32s2/esp32s2_lowputc.c index a5bb7b01c6b65..423b5907ebf8f 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_lowputc.c +++ b/arch/xtensa/src/esp32s2/esp32s2_lowputc.c @@ -653,7 +653,7 @@ void esp32s2_lowputc_disable_all_uart_int(const struct esp32s2_uart_s *priv, { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (current_status != NULL) { @@ -670,7 +670,7 @@ void esp32s2_lowputc_disable_all_uart_int(const struct esp32s2_uart_s *priv, putreg32(UINT32_MAX, UART_INT_CLR_REG(priv->id)); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c b/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c index b0b3d7a189f9c..7b0e387da67d3 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c +++ b/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c @@ -33,6 +33,7 @@ #include #include +#include #include #include #include @@ -350,7 +351,7 @@ static int rt_timer_thread(int argc, char *argv[]) if (ret) { tmrerr("ERROR: Wait priv->toutsem error=%d\n", ret); - assert(0); + ASSERT(0); } flags = enter_critical_section(); diff --git a/arch/xtensa/src/esp32s2/esp32s2_spi_slave.c b/arch/xtensa/src/esp32s2/esp32s2_spi_slave.c index 2af5df88be9f1..aa8fac1ccb110 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_spi_slave.c +++ b/arch/xtensa/src/esp32s2/esp32s2_spi_slave.c @@ -1203,7 +1203,7 @@ static void spislave_initialize(struct spi_slave_ctrlr_s *ctrlr) spislave_dma_init(priv); #endif - esp32s2_gpioirqenable(ESP32S2_PIN2IRQ(config->cs_pin), GPIO_INTR_POSEDGE); + esp32s2_gpioirqenable(ESP32S2_PIN2IRQ(config->cs_pin), RISING); /* Force a transaction done interrupt. * This interrupt won't fire yet because we initialized the SPI interrupt diff --git a/arch/xtensa/src/esp32s2/esp32s2_spiram.c b/arch/xtensa/src/esp32s2/esp32s2_spiram.c index 5c5f5e86fbef9..d356529f5a9f0 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_spiram.c +++ b/arch/xtensa/src/esp32s2/esp32s2_spiram.c @@ -144,7 +144,7 @@ int mmu_map_psram(uint32_t start_paddr, uint32_t end_paddr, /* should be MMU page aligned */ - assert((start_paddr % MMU_PAGE_SIZE) == 0); + ASSERT((start_paddr % MMU_PAGE_SIZE) == 0); uint32_t start_vaddr = DPORT_CACHE_ADDRESS_LOW; uint32_t end_vaddr = start_vaddr + map_length; @@ -156,7 +156,7 @@ int mmu_map_psram(uint32_t start_paddr, uint32_t end_paddr, cache_bus_mask |= (end_vaddr >= DRAM1_ADDRESS_HIGH) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0; - assert(end_vaddr <= DRAM0_CACHE_ADDRESS_HIGH); + ASSERT(end_vaddr <= DRAM0_CACHE_ADDRESS_HIGH); minfo("start_paddr is %x, map_length is %xB, %d pages", start_paddr, map_length, BYTES_TO_MMU_PAGE(map_length)); diff --git a/arch/xtensa/src/esp32s2/esp32s2_textheap.c b/arch/xtensa/src/esp32s2/esp32s2_textheap.c index d98e4c06a773d..e46b9916adcd5 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_textheap.c +++ b/arch/xtensa/src/esp32s2/esp32s2_textheap.c @@ -41,11 +41,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_ESP32S2_RTC_HEAP -#error "No suitable heap available. Enable ESP32S2_RTC_HEAP." -#endif - -#define D_I_BUS_OFFSET 0x700000 +#define D_I_BUS_OFFSET 0x70000 /**************************************************************************** * Public Functions diff --git a/arch/xtensa/src/esp32s2/esp32s2_wdt.c b/arch/xtensa/src/esp32s2/esp32s2_wdt.c index 06ac7c13e9d37..449f512b48560 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_wdt.c +++ b/arch/xtensa/src/esp32s2/esp32s2_wdt.c @@ -852,6 +852,10 @@ static void wdt_enableint(struct esp32s2_wdt_dev_s *dev) } else if (IS_MWDT(dev)) { + /* Level Interrupt */ + + wdt_modifyreg32(dev, MWDT_CONFIG0_OFFSET, 0, TIMG_WDT_LEVEL_INT_EN); + wdt_modifyreg32(dev, MWDT_INT_ENA_REG_OFFSET, 0, TIMG_WDT_INT_ENA); } else @@ -882,6 +886,10 @@ static void wdt_disableint(struct esp32s2_wdt_dev_s *dev) } else if (IS_MWDT(dev)) { + /* Level Interrupt */ + + wdt_modifyreg32(dev, MWDT_CONFIG0_OFFSET, TIMG_WDT_LEVEL_INT_EN, 0); + wdt_modifyreg32(dev, MWDT_INT_ENA_REG_OFFSET, TIMG_WDT_INT_ENA, 0); } else diff --git a/arch/xtensa/src/esp32s2/esp32s2_wdt_lowerhalf.c b/arch/xtensa/src/esp32s2/esp32s2_wdt_lowerhalf.c index 308d92e018de8..018baf7f4d446 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_wdt_lowerhalf.c +++ b/arch/xtensa/src/esp32s2/esp32s2_wdt_lowerhalf.c @@ -588,7 +588,7 @@ static xcpt_t wdt_lh_capture(struct watchdog_lowerhalf_s *lower, DEBUGASSERT(priv); - wdinfo("Entry: handler=0x%" PRIxPTR "\n", (uintptr_t) handler); + wdinfo("Entry: handler=%p\n", handler); /* Get the old handler to return it */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_tim.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_tim.h index 8b8a75b91df17..ee270b946b6c0 100644 --- a/arch/xtensa/src/esp32s2/hardware/esp32s2_tim.h +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_tim.h @@ -45,7 +45,7 @@ #define MWDT_FEED_OFFSET 0x0060 #define MWDT_WP_REG 0x0064 #define MWDT_INT_ENA_REG_OFFSET 0x0098 -#define MWDT_INT_CLR_REG_OFFSET 0x00a0 +#define MWDT_INT_CLR_REG_OFFSET 0x00a4 /* The value that needs to be written to TIMG_WDT_WKEY to * write-enable the WDT registers. diff --git a/arch/xtensa/src/esp32s3/Bootloader.mk b/arch/xtensa/src/esp32s3/Bootloader.mk index 0b3d1a6678b5d..9d6c704c86659 100644 --- a/arch/xtensa/src/esp32s3/Bootloader.mk +++ b/arch/xtensa/src/esp32s3/Bootloader.mk @@ -20,7 +20,7 @@ .PHONY: bootloader clean_bootloader -ifeq ($(CONFIG_ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE),y) +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),) TOOLSDIR = $(TOPDIR)/tools/espressif CHIPDIR = $(TOPDIR)/arch/xtensa/src/chip @@ -51,6 +51,7 @@ $(BOOTLOADER_CONFIG): $(TOPDIR)/.config $(BOOTLOADER_DIR) $(if $(CONFIG_ESP32S3_FLASH_4M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_4MB)) \ $(if $(CONFIG_ESP32S3_FLASH_8M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_8MB)) \ $(if $(CONFIG_ESP32S3_FLASH_16M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_16MB)) \ + $(if $(CONFIG_ESP32S3_FLASH_32M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_32MB)) \ $(if $(CONFIG_ESP32S3_FLASH_MODE_DIO),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_DIO)) \ $(if $(CONFIG_ESP32S3_FLASH_MODE_DOUT),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_DOUT)) \ $(if $(CONFIG_ESP32S3_FLASH_MODE_QIO),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_QIO)) \ @@ -82,8 +83,13 @@ else ifeq ($(CONFIG_ESP32S3_APP_FORMAT_LEGACY),y) $(call cfg_val,CONFIG_PARTITION_TABLE_OFFSET,$(CONFIG_ESP32S3_PARTITION_TABLE_OFFSET)) \ } >> $(BOOTLOADER_CONFIG) endif +endif -ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) +bootloader: + $(Q) echo "Using direct bootloader to boot NuttX." + +else ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) BOOTLOADER_BIN = $(TOPDIR)/mcuboot-esp32s3.bin @@ -125,30 +131,3 @@ clean_bootloader: $(call DELFILE,$(TOPDIR)/partition-table-esp32s3.bin) endif - -else ifeq ($(CONFIG_ESP32S3_BOOTLOADER_DOWNLOAD_PREBUILT),y) - -BOOTLOADER_VERSION = latest -BOOTLOADER_URL = https://github.com/espressif/esp-nuttx-bootloader/releases/download/$(BOOTLOADER_VERSION) - -ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) - -bootloader: - $(call DOWNLOAD,$(BOOTLOADER_URL),mcuboot-esp32s3.bin,$(TOPDIR)/mcuboot-esp32s3.bin) - -clean_bootloader: - $(call DELFILE,$(TOPDIR)/mcuboot-esp32s3.bin) - -else ifeq ($(CONFIG_ESP32S3_APP_FORMAT_LEGACY),y) - -bootloader: - $(call DOWNLOAD,$(BOOTLOADER_URL),bootloader-esp32s3.bin,$(TOPDIR)/bootloader-esp32s3.bin) - $(call DOWNLOAD,$(BOOTLOADER_URL),partition-table-esp32s3.bin,$(TOPDIR)/partition-table-esp32s3.bin) - -clean_bootloader: - $(call DELFILE,$(TOPDIR)/bootloader-esp32s3.bin) - $(call DELFILE,$(TOPDIR)/partition-table-esp32s3.bin) - -endif - -endif diff --git a/arch/xtensa/src/esp32s3/Kconfig b/arch/xtensa/src/esp32s3/Kconfig index 0568c64e74c33..ecf696b7e4e6b 100644 --- a/arch/xtensa/src/esp32s3/Kconfig +++ b/arch/xtensa/src/esp32s3/Kconfig @@ -19,13 +19,27 @@ config ARCH_CHIP_ESP32S3WROOM1 Generic module with an embedded ESP32-S3. config ARCH_CHIP_ESP32S3WROOM2 - bool "ESP32-S3-WROOM-2" + bool "ESP32-S3-WROOM-2 with 16MB Flash" select ESP32S3_FLASH_16M select ESP32S3_PSRAM_8M select ARCH_HAVE_I2CRESET ---help--- Generic module with an embedded ESP32-S3. + Note: depending on the modules, WROOM2 has 16MB flash + (ESP32-S3-WROOM-2-N16R8V) or 32MB flash. (ESP32-S3-WROOM-2-N32R8V) + +config ARCH_CHIP_ESP32S3WROOM2_32M + bool "ESP32-S3-WROOM-2 with 32MB Flash" + select ESP32S3_FLASH_32M + select ESP32S3_PSRAM_8M + select ARCH_HAVE_I2CRESET + ---help--- + Generic module with an embedded ESP32-S3. + + Note: depending on the modules, WROOM2 has 16MB flash + (ESP32-S3-WROOM-2-N16R8V) or 32MB flash. (ESP32-S3-WROOM-2-N32R8V) + config ARCH_CHIP_ESP32S3MINI1 bool "ESP32-S3-MINI-1" select ESP32S3_FLASH_8M @@ -39,6 +53,10 @@ config ESPRESSIF_CHIP_SERIES string default "esp32s3" +config ESPRESSIF_NUM_CPUS + int + default 2 + choice ESP32S3_DEFAULT_CPU_FREQ prompt "CPU frequency" default ESP32S3_DEFAULT_CPU_FREQ_240 @@ -270,6 +288,12 @@ menu "ESP32-S3 Peripheral Selection" source "arch/xtensa/src/common/espressif/Kconfig" +config ESP32S3_ADC + bool "ADC" + default n + select ANALOG + select ADC + config ESP32S3_UART bool default n @@ -366,26 +390,24 @@ config ESP32S3_I2S0_SAMPLE_RATE config ESP32S3_I2S0_BCLKPIN int "I2S0 BCLK pin" default 4 - range 0 33 if ESP32S3_I2S0_ROLE_MASTER - range 0 39 if ESP32S3_I2S0_ROLE_SLAVE + range 0 48 config ESP32S3_I2S0_WSPIN int "I2S0 WS pin" default 5 - range 0 33 if ESP32S3_I2S0_ROLE_MASTER - range 0 39 if ESP32S3_I2S0_ROLE_SLAVE + range 0 48 config ESP32S3_I2S0_DINPIN int "I2S0 DIN pin" depends on ESP32S3_I2S0_RX default 19 - range 0 39 + range 0 48 config ESP32S3_I2S0_DOUTPIN int "I2S0 DOUT pin" depends on ESP32S3_I2S0_TX default 18 - range 0 33 + range 0 48 config ESP32S3_I2S0_MCLK bool "Enable I2S Master Clock" @@ -398,7 +420,7 @@ config ESP32S3_I2S0_MCLKPIN int "I2S MCLK pin" depends on ESP32S3_I2S0_MCLK default 0 - range 0 39 + range 0 48 endif #ESP32S3_I2S0 @@ -478,26 +500,24 @@ config ESP32S3_I2S1_SAMPLE_RATE config ESP32S3_I2S1_BCLKPIN int "I2S1 BCLK pin" default 22 - range 0 33 if ESP32S3_I2S1_ROLE_MASTER - range 0 39 if ESP32S3_I2S1_ROLE_SLAVE + range 0 48 config ESP32S3_I2S1_WSPIN int "I2S1 WS pin" default 23 - range 0 33 if ESP32S3_I2S1_ROLE_MASTER - range 0 39 if ESP32S3_I2S1_ROLE_SLAVE + range 0 48 config ESP32S3_I2S1_DINPIN int "I2S1 DIN pin" depends on ESP32S3_I2S1_RX default 26 - range 0 39 + range 0 48 config ESP32S3_I2S1_DOUTPIN int "I2S1 DOUT pin" depends on ESP32S3_I2S1_TX default 25 - range 0 33 + range 0 48 config ESP32S3_I2S1_MCLK bool "Enable I2S Master Clock" @@ -510,7 +530,7 @@ config ESP32S3_I2S1_MCLKPIN int "I2S MCLK pin" depends on ESP32S3_I2S1_MCLK default 1 - range 0 39 + range 0 48 endif #ESP32S3_I2S1 @@ -534,6 +554,7 @@ config ESP32S3_WDT config ESP32S3_EFUSE bool "EFUSE support" + select EFUSE default n ---help--- Enable ESP32-S3 efuse support. @@ -727,7 +748,7 @@ config ESP32S3_XTWDT_BACKUP_CLK_ENABLE bool "Automatically switch to BACKUP32K_CLK when timer expires" depends on ESP32S3_XTWDT default y - help + ---help--- Enable this to automatically switch to BACKUP32K_CLK as the source of RTC_SLOW_CLK when the watchdog timer expires. @@ -749,10 +770,13 @@ config ESP32S3_LCD select DRIVERS_VIDEO select VIDEO_FB select FB_UPDATE - help ---help--- LCD controller that outputs parallel data and supports RGB interface. +config ESP32S3_AES_ACCELERATOR + bool "AES Accelerator" + default n + endmenu # ESP32-S3 Peripheral Selection menuconfig ESP32S3_WIFI_BT_COEXIST @@ -1266,6 +1290,73 @@ endif # ESP32S3_UART2 endmenu # UART Configuration +menu "ADC Configuration" + depends on ESP32S3_ADC + +if ESP32S3_ADC + +choice ESP32S3_ADC_VOL_RANGES + prompt "ADC voltage ranges" + default ESP32S3_ADC_VOL_3100 + +config ESP32S3_ADC_VOL_950 + bool "0~950mV" + +config ESP32S3_ADC_VOL_1250 + bool "0~1250mV" + +config ESP32S3_ADC_VOL_1750 + bool "0~1750mV" + +config ESP32S3_ADC_VOL_3100 + bool "0~3100mV" + +endchoice # ADC voltage ranges + +config ESP32S3_ADC1_CHANNEL0 + bool "ADC1 channel 0" + default n + +config ESP32S3_ADC1_CHANNEL1 + bool "ADC1 channel 1" + default n + +config ESP32S3_ADC1_CHANNEL2 + bool "ADC1 channel 2" + default n + +config ESP32S3_ADC1_CHANNEL3 + bool "ADC1 channel 3" + default n + +config ESP32S3_ADC1_CHANNEL4 + bool "ADC1 channel 4" + default n + +config ESP32S3_ADC1_CHANNEL5 + bool "ADC1 channel 5" + default n + +config ESP32S3_ADC1_CHANNEL6 + bool "ADC1 channel 6" + default n + +config ESP32S3_ADC1_CHANNEL7 + bool "ADC1 channel 7" + default n + +config ESP32S3_ADC1_CHANNEL8 + bool "ADC1 channel 8" + default n + +config ESP32S3_ADC1_CHANNEL9 + bool "ADC1 channel 9" + default n + +endif # ESP32S3_ADC + +endmenu # ADC Configuration + menu "I2C Configuration" depends on ESP32S3_I2C @@ -1407,6 +1498,20 @@ config ESP32S3_WIFI_STATION_SOFTAP endchoice # ESP32S3 Wi-Fi mode +config ESP_WIFI_ENABLE_SAE_PK + bool "Enable SAE-PK" + default y + ---help--- + Select this option to enable SAE-PK + +config ESP_WIFI_ENABLE_WPA3_OWE_STA + bool "Enable OWE STA" + default y + ---help--- + Select this option to allow the device to establish OWE connection with eligible AP's. + PMF (Protected Management Frames) is a prerequisite feature for a WPA3 connection, it needs to be + explicitly configured before attempting connection. Please refer to the Wi-Fi Driver API Guide for details. + config ESP32S3_WIFI_STATIC_RXBUF_NUM int "Wi-Fi static RX buffer number" default 10 @@ -1866,21 +1971,20 @@ config ESP32S3_SPI_FLASH_SUPPORT_PSRAM_STACK can do SPI Flash read/write/erase/map/unmap. Otherwise, it may cause exception, the root cause is as following: 1. When operating SPI flash, cache is also disable, - then software can't access PSRAM by data cache. + then software can't access PSRAM by data cache. 2. SPI flash read/write/erase functions have instruction like stack-pop and stack-push which may use stack buffer which is - PSRAM space or load/store temp variables which locate in PSRAM space too. + PSRAM space or load/store temp variables which locate in PSRAM space too. 3. Once operation in step 2 triggers, CPU will trigger exception. So related SPI flash functions should be sent and run in tasks which use SRAM as task stack. -if ESP32S3_APP_FORMAT_LEGACY - comment "Partition Table configuration" config ESP32S3_PARTITION_TABLE bool "Create MTD partitions from Partition Table" default n - depends on ESP32S3_MTD && ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE + depends on ESP32S3_MTD + select ESP32S3_APP_FORMAT_LEGACY ---help--- Decode partition table and initialize partitions as MTD. @@ -1889,8 +1993,6 @@ config ESP32S3_PARTITION_MOUNTPT default "/dev/esp/partition/" depends on ESP32S3_PARTITION_TABLE -endif # ESP32S3_APP_FORMAT_LEGACY - endif # ESP32S3_SPIFLASH endmenu # SPI Flash configuration @@ -2156,56 +2258,28 @@ config ESP32S3_LCD_REGDEBUG endmenu -menu "Application Image Configuration" +menu "Bootloader and Image Configuration" -choice - prompt "Application Image Format" - default ESP32S3_APP_FORMAT_LEGACY - ---help--- - Depending on the chosen 2nd stage bootloader, the application may - be required to be perform a specific startup routine. Furthermore, - the image binary must be formatted according to the definition from - the 2nd stage bootloader. - -config ESP32S3_APP_FORMAT_LEGACY - bool "Legacy format" - ---help--- - This is the legacy application image format, as supported by the ESP-IDF - 2nd stage bootloader. +config ESPRESSIF_SIMPLE_BOOT + bool + depends on !ESP32S3_APP_FORMAT_MCUBOOT + depends on !ESP32S3_APP_FORMAT_LEGACY + default y config ESP32S3_APP_FORMAT_MCUBOOT - bool "MCUboot-bootable format" + bool "Enable MCUboot-bootable format" depends on !MCUBOOT_BOOTLOADER + default n select ESP32S3_HAVE_OTA_PARTITION ---help--- - The Espressif port of MCUboot supports the loading of unsegmented firmware - images. - -endchoice # Application Image Format + Enables the Espressif port of MCUboot to be used as 2nd stage bootloader. -choice - prompt "Source for bootloader binaries" - default ESP32S3_BOOTLOADER_DOWNLOAD_PREBUILT - ---help--- - Select the action to be taken by the build system for the - "make bootloader" target. - -config ESP32S3_BOOTLOADER_DOWNLOAD_PREBUILT - bool "Download prebuilt binaries" - ---help--- - The build system will download the prebuilt binaries from - https://github.com/espressif/esp-nuttx-bootloader according to the chosen - Application Image Format (ESP32S3_APP_FORMAT_LEGACY or ESP32S3_APP_FORMAT_MCUBOOT) - -config ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE - bool "Build binaries from source" +config ESP32S3_APP_FORMAT_LEGACY + bool + default y if BUILD_PROTECTED ---help--- - The build system will build all the required binaries from source. It will clone - the https://github.com/espressif/esp-nuttx-bootloader repository and build a - custom bootloader according to the chosen Application Image Format - (ESP32S3_APP_FORMAT_LEGACY or ESP32S3_APP_FORMAT_MCUBOOT) and partition information. - -endchoice + This is the legacy application image format, as supported by the ESP-IDF + 2nd stage bootloader. choice prompt "Target slot for image flashing" @@ -2242,11 +2316,36 @@ config ESP32S3_APP_MCUBOOT_HEADER_SIZE default 32 depends on ESP32S3_APP_FORMAT_MCUBOOT +config ESP32S3_PARTITION_TABLE_OFFSET_DEFAULT + hex + default 0x8000 + depends on ESP32S3_APP_FORMAT_LEGACY + +config ESP32S3_CUSTOM_PARTITION_TABLE_OFFSET + bool "Customize partition table offset" + default n + depends on ESP32S3_APP_FORMAT_LEGACY + ---help--- + Enable to select the offset of the partition table in the flash. + +if ESP32S3_CUSTOM_PARTITION_TABLE_OFFSET + config ESP32S3_PARTITION_TABLE_OFFSET hex "Partition Table offset" - default 0x8000 + default ESP32S3_PARTITION_TABLE_OFFSET_DEFAULT depends on ESP32S3_APP_FORMAT_LEGACY +endif # ESP32S3_CUSTOM_PARTITION_TABLE_OFFSET + +if !ESP32S3_CUSTOM_PARTITION_TABLE_OFFSET + +config ESP32S3_PARTITION_TABLE_OFFSET + hex + default ESP32S3_PARTITION_TABLE_OFFSET_DEFAULT + depends on ESP32S3_APP_FORMAT_LEGACY + +endif # !ESP32S3_CUSTOM_PARTITION_TABLE_OFFSET + config ESP32S3_KERNEL_OFFSET hex default 0x10000 @@ -2280,6 +2379,15 @@ config ESP32S3_KERNEL_RAM_SIZE endif # BUILD_PROTECTED -endmenu # Application Image Configuration +endmenu # Bootloader and Image Configuration + +menu "AES accelerate" + depends on ESP32S3_AES_ACCELERATOR + +config ESP32S3_AES_ACCELERATOR_TEST + bool "AES driver test" + default n + +endmenu # ESP32S3_AES_ACCELERATOR endif # ARCH_CHIP_ESP32S3 diff --git a/arch/xtensa/src/esp32s3/Make.defs b/arch/xtensa/src/esp32s3/Make.defs index 3dd91698233b5..2e87e8af2f1f0 100644 --- a/arch/xtensa/src/esp32s3/Make.defs +++ b/arch/xtensa/src/esp32s3/Make.defs @@ -30,7 +30,6 @@ CHIP_CSRCS = esp32s3_irq.c esp32s3_clockconfig.c esp32s3_region.c CHIP_CSRCS += esp32s3_systemreset.c esp32s3_user.c esp32s3_allocateheap.c CHIP_CSRCS += esp32s3_wdt.c esp32s3_gpio.c esp32s3_lowputc.c esp32s3_serial.c CHIP_CSRCS += esp32s3_rtc_gpio.c esp32s3_libc_stubs.c esp32s3_spi_timing.c -CHIP_CSRCS += esp32s3_periph.c # Configuration-dependent ESP32-S3 files @@ -105,6 +104,10 @@ ifeq ($(CONFIG_ESP32S3_RT_TIMER),y) CHIP_CSRCS += esp32s3_rt_timer.c endif +ifeq ($(CONFIG_ESP32S3_ADC),y) +CHIP_CSRCS += esp32s3_adc.c +endif + ifeq ($(CONFIG_ESP32S3_I2C),y) CHIP_CSRCS += esp32s3_i2c.c endif @@ -183,6 +186,17 @@ ifeq ($(CONFIG_ESP32S3_LCD),y) CHIP_CSRCS += esp32s3_lcd.c endif +ifeq ($(CONFIG_ESP32S3_AES_ACCELERATOR),y) +CHIP_CSRCS += esp32s3_aes.c +endif + +ifeq ($(CONFIG_PM),y) +ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) +CHIP_CSRCS += esp32s3_pminitialize.c +endif +CHIP_CSRCS += esp32s3_pm.c +endif + ############################################################################# # Espressif HAL for 3rd Party Platforms ############################################################################# @@ -191,13 +205,20 @@ endif ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty ifndef ESP_HAL_3RDPARTY_VERSION - ESP_HAL_3RDPARTY_VERSION = 22804823777dbbb7f43925b7729b3a32331aa7cd + ESP_HAL_3RDPARTY_VERSION = 7c4fae7ebc5342b19cab03511bfa277176bba377 endif ifndef ESP_HAL_3RDPARTY_URL ESP_HAL_3RDPARTY_URL = https://github.com/espressif/esp-hal-3rdparty.git endif +ifndef DISABLE_GIT_DEPTH +ifndef GIT_DEPTH + GIT_DEPTH=1 +endif + GIT_DEPTH_PARAMETER = --depth=$(GIT_DEPTH) +endif + chip/$(ESP_HAL_3RDPARTY_REPO): $(Q) echo "Cloning Espressif HAL for 3rd Party Platforms" $(Q) git clone --quiet $(ESP_HAL_3RDPARTY_URL) chip/$(ESP_HAL_3RDPARTY_REPO) @@ -207,6 +228,9 @@ chip/$(ESP_HAL_3RDPARTY_REPO): # Silent preprocessor warnings CFLAGS += -Wno-undef -Wno-unused-variable +CFLAGS += ${DEFINE_PREFIX}_RETARGETABLE_LOCKING + +AFLAGS += $(CFLAGS) # Files that require the HAL recipe @@ -221,15 +245,12 @@ include common/espressif/Make.defs context:: chip/$(ESP_HAL_3RDPARTY_REPO) ifeq ($(CONFIG_ESP32S3_WIRELESS),y) $(Q) echo "Espressif HAL for 3rd Party Platforms: initializing submodules..." - $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) submodule --quiet update --init --depth=1 components/mbedtls/mbedtls components/esp_phy/lib components/esp_wifi/lib components/bt/controller/lib_esp32c3_family components/esp_coex/lib + $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) submodule --quiet update --init $(GIT_DEPTH_PARAMETER) components/mbedtls/mbedtls components/esp_phy/lib components/esp_wifi/lib components/bt/controller/lib_esp32c3_family components/esp_coex/lib $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls reset --quiet --hard $(Q) echo "Applying patches..." $(Q) cd chip/$(ESP_HAL_3RDPARTY_REPO)/components/mbedtls/mbedtls && git apply ../../../nuttx/patches/components/mbedtls/mbedtls/*.patch endif -distclean:: - $(call DELDIR, chip/$(ESP_HAL_3RDPARTY_REPO)) - ifeq ($(CONFIG_ESP32S3_WIRELESS),y) include chip/Wireless.mk endif diff --git a/arch/xtensa/src/esp32s3/Wireless.mk b/arch/xtensa/src/esp32s3/Wireless.mk index 9ca8d91fa8ec1..6a4023b77b57c 100644 --- a/arch/xtensa/src/esp32s3/Wireless.mk +++ b/arch/xtensa/src/esp32s3/Wireless.mk @@ -20,19 +20,14 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)include$(DELIM)esp32c3$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_coex$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_event$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)esp32s3$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include$(DELIM)esp32s3 -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)esp32s3$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)esp32s3$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)esp_wifi -EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)controller$(DELIM)lib_esp32c3_family$(DELIM)esp32s3 -EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_coex$(DELIM)lib$(DELIM)esp32s3 -EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)lib$(DELIM)esp32s3 -EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)lib$(DELIM)esp32s3 +EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)controller$(DELIM)lib_esp32c3_family$(DELIM)$(CHIP_SERIES) +EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_coex$(DELIM)lib$(DELIM)$(CHIP_SERIES) +EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)lib$(DELIM)$(CHIP_SERIES) +EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)lib$(DELIM)$(CHIP_SERIES) EXTRA_LIBS += -lphy -lcoexist @@ -87,6 +82,20 @@ CHIP_CSRCS += platform.c CHIP_CSRCS += sha1.c CHIP_CSRCS += sha256.c CHIP_CSRCS += sha512.c +CHIP_CSRCS += pk.c +CHIP_CSRCS += pk_wrap.c +CHIP_CSRCS += pkparse.c +CHIP_CSRCS += ecdsa.c +CHIP_CSRCS += asn1parse.c +CHIP_CSRCS += asn1write.c +CHIP_CSRCS += rsa.c +CHIP_CSRCS += md5.c +CHIP_CSRCS += oid.c +CHIP_CSRCS += pem.c +CHIP_CSRCS += hmac_drbg.c +CHIP_CSRCS += hash_info.c +CHIP_CSRCS += rsa_alt_helpers.c +CHIP_CSRCS += ecdh.c VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port @@ -113,6 +122,16 @@ CFLAGS += $(DEFINE_PREFIX)ESP_SUPPLICANT CFLAGS += $(DEFINE_PREFIX)ESPRESSIF_USE CFLAGS += $(DEFINE_PREFIX)IEEE8021X_EAPOL CFLAGS += $(DEFINE_PREFIX)USE_WPA2_TASK +CFLAGS += $(DEFINE_PREFIX)CONFIG_SHA256 +CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE + +ifeq ($(CONFIG_ESP_WIFI_ENABLE_SAE_PK),y) +CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE_PK +endif + +ifeq ($(CONFIG_ESP_WIFI_ENABLE_WPA3_OWE_STA),y) +CFLAGS += $(DEFINE_PREFIX)CONFIG_OWE_STA +endif ifeq ($(CONFIG_ESP_WIFI_GCMP_SUPPORT),y) CFLAGS += $(DEFINE_PREFIX)CONFIG_GCMP @@ -131,6 +150,7 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM) CHIP_CSRCS += ap_config.c CHIP_CSRCS += ieee802_11.c +CHIP_CSRCS += comeback_token.c CHIP_CSRCS += pmksa_cache_auth.c CHIP_CSRCS += sta_info.c CHIP_CSRCS += wpa_auth_ie.c @@ -143,6 +163,10 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM) CHIP_CSRCS += dragonfly.c CHIP_CSRCS += sae.c CHIP_CSRCS += wpa_common.c +CHIP_CSRCS += sae_pk.c +CHIP_CSRCS += bss.c +CHIP_CSRCS += scan.c +CHIP_CSRCS += ieee802_11_common.c VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)crypto @@ -213,6 +237,8 @@ CHIP_CSRCS += esp_wpa_main.c CHIP_CSRCS += esp_wpa2.c CHIP_CSRCS += esp_wpa3.c CHIP_CSRCS += esp_wpas_glue.c +CHIP_CSRCS += esp_owe.c +CHIP_CSRCS += esp_scan.c VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src$(DELIM)crypto @@ -223,5 +249,6 @@ CHIP_CSRCS += crypto_mbedtls-ec.c CHIP_CSRCS += crypto_mbedtls-rsa.c CHIP_CSRCS += crypto_mbedtls.c CHIP_CSRCS += tls_mbedtls.c +CHIP_CSRCS += aes-siv.c endif diff --git a/arch/xtensa/src/esp32s3/esp32s3_adc.c b/arch/xtensa/src/esp32s3/esp32s3_adc.c new file mode 100644 index 0000000000000..ce87f13ff4076 --- /dev/null +++ b/arch/xtensa/src/esp32s3/esp32s3_adc.c @@ -0,0 +1,944 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/esp32s3_adc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include "esp32s3_gpio.h" +#include "esp32s3_dma.h" +#include "esp32s3_irq.h" +#include "esp32s3_adc.h" + +#include "xtensa.h" +#include "hardware/esp32s3_system.h" +#include "hardware/esp32s3_efuse.h" +#include "hardware/esp32s3_sens.h" +#include "hardware/esp32s3_gpio_sigmap.h" +#include "hardware/regi2c_ctrl.h" +#include "hardware/regi2c_saradc.h" +#include "hardware/esp32s3_rtc_io.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* ADC calibration max count */ + +#define ADC_CAL_CNT_MAX (32) + +/* ADC calibration max value */ + +#define ADC_CAL_VAL_MAX (4096 - 1) + +/* ADC calibration sampling channel */ + +#define ADC_CAL_CHANNEL (0xf) + +/* ADC max value mask */ + +#define ADC_VAL_MASK (0xfff) + +#define ADC_CAL_BASE_REG EFUSE_RD_SYS_PART1_DATA0_REG + +#define ADC_CAL_VER_OFF (128) +#define ADC_CAL_VER_LEN (2) + +#define ADC_CAL_DATA_COMP (1550) + +#define ADC_CAL_VOL_LEN (8) + +/* ADC input voltage attenuation, this affects measuring range */ + +#define ADC_ATTEN_DB_0 (0) /* Vmax = 950 mV */ +#define ADC_ATTEN_DB_2_5 (1) /* Vmax = 1250 mV */ +#define ADC_ATTEN_DB_6 (2) /* Vmax = 1750 mV */ +#define ADC_ATTEN_DB_12 (3) /* Vmax = 3100 mV */ + +/* ADC attenuation */ + +#if defined(CONFIG_ESP32S3_ADC_VOL_950) +# define ADC_ATTEN_DEF ADC_ATTEN_DB_0 +# define ADC_CAL_DATA_LEN (8) + +# define ADC_CAL_DATA_OFF (149) +# define ADC_CAL_VOL_OFF (201) + +# define ADC_CAL_VOL_DEF (488) +#elif defined(CONFIG_ESP32S3_ADC_VOL_1250) +# define ADC_ATTEN_DEF ADC_ATTEN_DB_2_5 +# define ADC_CAL_DATA_LEN (6) + +# define ADC_CAL_DATA_OFF (157) +# define ADC_CAL_VOL_OFF (209) + +# define ADC_CAL_VOL_DEF (641) +#elif defined(CONFIG_ESP32S3_ADC_VOL_1750) +# define ADC_ATTEN_DEF ADC_ATTEN_DB_6 +# define ADC_CAL_DATA_LEN (6) + +# define ADC_CAL_DATA_OFF (163) +# define ADC_CAL_VOL_OFF (217) + +# define ADC_CAL_VOL_DEF (892) +#elif defined(CONFIG_ESP32S3_ADC_VOL_3100) +# define ADC_ATTEN_DEF ADC_ATTEN_DB_12 +# define ADC_CAL_DATA_LEN (6) + +# define ADC_CAL_DATA_OFF (169) +# define ADC_CAL_VOL_OFF (225) + +# define ADC_CAL_VOL_DEF (1592) +#endif + +#define setbits(bs, a) modifyreg32(a, 0, bs) +#define resetbits(bs, a) modifyreg32(a, bs, 0) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* ADC Private Data */ + +struct adc_chan_s +{ + uint32_t ref; /* Reference count */ + + const uint8_t channel; /* Channel number */ + const uint8_t pin; /* GPIO pin number */ + + const struct adc_callback_s *cb; /* Upper driver callback */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int adc_bind(struct adc_dev_s *dev, + const struct adc_callback_s *callback); +static void adc_reset(struct adc_dev_s *dev); +static int adc_setup(struct adc_dev_s *dev); +static void adc_shutdown(struct adc_dev_s *dev); +static void adc_rxint(struct adc_dev_s *dev, bool enable); +static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* ADC interface operations */ + +static const struct adc_ops_s g_adcops = +{ + .ao_bind = adc_bind, + .ao_reset = adc_reset, + .ao_setup = adc_setup, + .ao_shutdown = adc_shutdown, + .ao_rxint = adc_rxint, + .ao_ioctl = adc_ioctl, +}; + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL0 +static struct adc_chan_s g_adc1_chan0 = +{ + .channel = 0, + .pin = 1 +}; +#endif + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL1 +static struct adc_chan_s g_adc1_chan1 = +{ + .channel = 1, + .pin = 2 +}; +#endif + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL2 +static struct adc_chan_s g_adc1_chan2 = +{ + .channel = 2, + .pin = 3 +}; +#endif + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL3 +static struct adc_chan_s g_adc1_chan3 = +{ + .channel = 3, + .pin = 4 +}; +#endif + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL4 +static struct adc_chan_s g_adc1_chan4 = +{ + .channel = 4, + .pin = 5 +}; +#endif + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL5 +static struct adc_chan_s g_adc1_chan5 = +{ + .channel = 5, + .pin = 6 +}; +#endif + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL6 +static struct adc_chan_s g_adc1_chan6 = +{ + .channel = 6, + .pin = 7 +}; +#endif + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL7 +static struct adc_chan_s g_adc1_chan7 = +{ + .channel = 7, + .pin = 8 +}; +#endif + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL8 +static struct adc_chan_s g_adc1_chan8 = +{ + .channel = 8, + .pin = 9 +}; +#endif + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL9 +static struct adc_chan_s g_adc1_chan9 = +{ + .channel = 9, + .pin = 10 +}; +#endif + +/* ADC calibration mark */ + +static bool g_adc_switch; + +/* ADC calibration mark */ + +static bool g_calibrated; + +/* ADC calibration digital parameter */ + +static uint16_t g_cal_digit; + +/* ADC clock reference */ + +static uint32_t g_clk_ref; + +static mutex_t g_lock = NXMUTEX_INITIALIZER; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: read_efuse + * + * Description: + * Read Efuse data. + * + * Input Parameters: + * addr - register address + * b_off - bit offset + * b_size - bit size + * + * Returned Value: + * Efuse data. + * + ****************************************************************************/ + +static uint32_t read_efuse(uint32_t addr, uint32_t b_off, uint32_t b_size) +{ + uint32_t data; + uint32_t regval; + uint32_t shift = 32 - b_size; + uint32_t mask = UINT32_MAX >> shift; + uint32_t res = b_off % 32; + uint32_t regaddr = addr + (b_off / 32 * 4); + + regval = getreg32(regaddr); + data = regval >> res; + if (res <= shift) + { + data &= mask; + } + else + { + shift = 32 - res; + + regval = getreg32(regaddr + 4); + data |= (regval & (mask >> shift)) << shift; + } + + return data; +} + +/**************************************************************************** + * Name: adc_enable_clk + * + * Description: + * Enable ADC clock. + * + * Input Parameters: + * NOne + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void adc_enable_clk(void) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + if (!g_clk_ref) + { + setbits(SENS_SARADC_CLK_EN, SENS_SAR_PERI_CLK_GATE_CONF_REG); + } + + g_clk_ref++; + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: adc_disable_clk + * + * Description: + * Disable ADC clock. + * + * Input Parameters: + * NOne + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void adc_disable_clk(void) +{ + irqstate_t flags; + + flags = enter_critical_section(); + + g_clk_ref--; + + if (!g_clk_ref) + { + resetbits(SENS_SARADC_CLK_EN, SENS_SAR_PERI_CLK_GATE_CONF_REG); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: adc_set_calibration + * + * Description: + * Set calibration parameter to ADC hardware. + * + * Input Parameters: + * data - Calibration parameter + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void adc_set_calibration(uint16_t data) +{ + uint8_t h_data = data >> 8; + uint8_t l_data = data & 0xff; + + esp_rom_regi2c_write_mask(I2C_ADC, I2C_ADC_HOSTID, + I2C_ADC1_INITVAL_H, + I2C_ADC1_INITVAL_H_MSB, + I2C_ADC1_INITVAL_H_LSB, h_data); + + esp_rom_regi2c_write_mask(I2C_ADC, I2C_ADC_HOSTID, + I2C_ADC1_INITVAL_L, + I2C_ADC1_INITVAL_L_MSB, + I2C_ADC1_INITVAL_L_LSB, l_data); +} + +/**************************************************************************** + * Name: adc_samplecfg + * + * Description: + * Set ADC sampling with given channel. + * + * Input Parameters: + * channel - Sampling channel number + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static inline void adc_samplecfg(int channel) +{ + uint32_t regval; + + /* set (Frequency division) (inversion adc) */ + + regval = getreg32(SENS_SAR_READER1_CTRL_REG); + regval &= ~(SENS_SAR1_CLK_DIV_M); + regval |= (1 << SENS_SAR1_CLK_DIV_S); + putreg32(regval, SENS_SAR_READER1_CTRL_REG); + + /* Enable ADC1, its sampling attenuation */ + + regval = getreg32(SENS_SAR_ATTEN1_REG); + regval &= ~(ADC_ATTEN_DEF << (channel * 2)); + regval |= ADC_ATTEN_DEF << (channel * 2); + putreg32(regval, SENS_SAR_ATTEN1_REG); + + /* Enable ADC1, its sampling channel and attenuation */ + + regval = getreg32(SENS_SAR_MEAS1_CTRL2_REG); + regval &= ~(SENS_SAR1_EN_PAD_M | SENS_SAR1_EN_PAD_FORCE_M | + SENS_MEAS1_START_FORCE_M); + regval |= ((1 << channel) << SENS_SAR1_EN_PAD_S) | + SENS_SAR1_EN_PAD_FORCE | SENS_MEAS1_START_FORCE; + putreg32(regval, SENS_SAR_MEAS1_CTRL2_REG); +} + +/**************************************************************************** + * Name: adc_read + * + * Description: + * Start ADC sampling and read ADC value. + * + * Input Parameters: + * None + * + * Returned Value: + * Read ADC value. + * + ****************************************************************************/ + +static uint16_t adc_read(void) +{ + uint16_t adc; + uint32_t regval; + + /* Trigger ADC1 sampling */ + + setbits(SENS_MEAS1_START_SAR, SENS_SAR_MEAS1_CTRL2_REG); + + /* Wait until ADC1 sampling is done */ + + do + { + regval = getreg32(SENS_SAR_MEAS1_CTRL2_REG); + } + while (!(regval & SENS_MEAS1_DONE_SAR_M)); + + regval = getreg32(SENS_SAR_MEAS1_CTRL2_REG) & ADC_VAL_MASK; + ainfo("SENS_MEAS1_DATA_SAR adc_read: %d\n", regval); + + /* Disable ADC sampling */ + + resetbits(SENS_MEAS1_START_SAR, SENS_SAR_MEAS1_CTRL2_REG); + + return regval; +} + +/**************************************************************************** + * Name: adc_calibrate + * + * Description: + * ADC calibration. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void adc_calibrate(void) +{ + uint16_t cali_val; + uint16_t adc; + uint16_t adc_max = 0; + uint16_t adc_min = UINT16_MAX; + uint32_t adc_sum = 0; + uint32_t regval; + + regval = read_efuse(ADC_CAL_BASE_REG, ADC_CAL_VER_OFF, ADC_CAL_VER_LEN); + if (regval == 1) + { + ainfo("Calibrate based on efuse data\n"); + + regval = read_efuse(ADC_CAL_BASE_REG, ADC_CAL_DATA_OFF, + ADC_CAL_DATA_LEN); + cali_val = regval + ADC_CAL_DATA_COMP; + } + else + { + ainfo("Calibrate based on GND voltage\n"); + + /* Enable Vdef */ + + esp_rom_regi2c_write_mask(I2C_ADC, I2C_ADC_HOSTID, + I2C_ADC1_DEF, I2C_ADC1_DEF_MSB, + I2C_ADC1_DEF_LSB, 1); + + /* Start sampling */ + + adc_samplecfg(ADC_CAL_CHANNEL); + + /* Enable internal connect GND (for calibration). */ + + esp_rom_regi2c_write_mask(I2C_ADC, I2C_ADC_HOSTID, + I2C_ADC1_ENCAL_GND, I2C_ADC1_ENCAL_GND_MSB, + I2C_ADC1_ENCAL_GND_LSB, 1); + + for (int i = 1; i < ADC_CAL_CNT_MAX ; i++) + { + adc_set_calibration(0); + adc = adc_read(); + + adc_sum += adc; + adc_max = MAX(adc, adc_max); + adc_min = MIN(adc, adc_min); + } + + cali_val = (adc_sum - adc_max - adc_min) / (ADC_CAL_CNT_MAX - 2); + + /* Disable internal connect GND (for calibration). */ + + esp_rom_regi2c_write_mask(I2C_ADC, I2C_ADC_HOSTID, + I2C_ADC1_ENCAL_GND, + I2C_ADC1_ENCAL_GND_MSB, + I2C_ADC1_ENCAL_GND_LSB, 0); + } + + ainfo("calibration value: %" PRIu16 "\n", cali_val); + + /* Set final calibration parameters */ + + adc_set_calibration(cali_val); + + /* Set calibration digital parameters */ + + regval = read_efuse(ADC_CAL_BASE_REG, ADC_CAL_VOL_OFF, ADC_CAL_VOL_LEN); + if (regval & BIT(ADC_CAL_VOL_LEN - 1)) + { + g_cal_digit = 2000 - (regval & ~(BIT(ADC_CAL_VOL_LEN - 1))); + } + else + { + g_cal_digit = 2000 + regval; + } + + ainfo("calibration read_efuse g_cal_digit: %" PRIu16 "\n", g_cal_digit); +} + +/**************************************************************************** + * Name: adc_read_work + * + * Description: + * Read ADC value and pass it to up. + * + * Input Parameters: + * dev - ADC device pointer + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void adc_read_work(struct adc_dev_s *dev) +{ + int ret; + uint32_t value; + int32_t adc; + struct adc_chan_s *priv = (struct adc_chan_s *)dev->ad_priv; + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + aerr("Failed to lock ret=%d\n", ret); + return; + } + + adc_samplecfg(priv->channel); + value = adc_read(); + + adc = (int32_t)(value * (UINT16_MAX * ADC_CAL_VOL_DEF / g_cal_digit) / + UINT16_MAX); + + priv->cb->au_receive(dev, priv->channel, adc); + + ainfo("channel: %" PRIu8 ", voltage: %" PRIu32 " mV\n", priv->channel, + adc); + + nxmutex_unlock(&g_lock); +} + +/**************************************************************************** + * Name: adc_bind + * + * Description: + * Bind the upper-half driver callbacks to the lower-half implementation. + * This must be called early in order to receive ADC event notifications. + * + ****************************************************************************/ + +static int adc_bind(struct adc_dev_s *dev, + const struct adc_callback_s *callback) +{ + struct adc_chan_s *priv = (struct adc_chan_s *)dev->ad_priv; + + DEBUGASSERT(priv != NULL); + + ainfo("channel: %" PRIu8 "\n", priv->channel); + + priv->cb = callback; + + return OK; +} + +/**************************************************************************** + * Name: adc_reset + * + * Description: + * Reset the ADC device. Called early to initialize the hardware. + * This is called, before adc_setup() and on error conditions. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_reset(struct adc_dev_s *dev) +{ + irqstate_t flags; + struct adc_chan_s *priv = (struct adc_chan_s *)dev->ad_priv; + + ainfo("channel: %" PRIu8 "\n", priv->channel); + + flags = enter_critical_section(); + + /* Do nothing if ADC instance is currently in use */ + + if (priv->ref > 0) + { + goto out; + } + + /* Reset ADC hardware */ + + adc_enable_clk(); + + adc_disable_clk(); + +out: + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: adc_setup + * + * Description: + * Configure the ADC. This method is called the first time that the ADC + * device is opened. This will occur when the port is first opened. + * This setup includes configuring. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static int adc_setup(struct adc_dev_s *dev) +{ + int ret; + uint32_t regval; + struct adc_chan_s *priv = (struct adc_chan_s *)dev->ad_priv; + + ainfo("channel: %" PRIu8 "\n", priv->channel); + + /* Do nothing when the ADC device is already set up */ + + if (priv->ref > 0) + { + priv->ref++; + return OK; + } + + /* Enable ADC clock */ + + adc_enable_clk(); + + /* Disable GPIO input and output */ + + ainfo("pin: %" PRIu8 "\n", priv->pin); + + esp32s3_configgpio(priv->pin, INPUT | FUNCTION_1); + + /* Start calibration only once */ + + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + adc_disable_clk(); + aerr("Failed to lock ret=%d\n", ret); + return ret; + } + + if (!g_calibrated) + { + adc_calibrate(); + g_calibrated = true; + } + + nxmutex_unlock(&g_lock); + + /* The ADC device is ready */ + + priv->ref++; + + return OK; +} + +/**************************************************************************** + * Name: adc_rxint + * + * Description: + * Call to enable or disable RX interrupts. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_rxint(struct adc_dev_s *dev, bool enable) +{ +} + +/**************************************************************************** + * Name: adc_ioctl + * + * Description: + * All ioctl calls will be routed through this method. + * + * Input Parameters: + * dev - pointer to device structure used by the driver + * cmd - command + * arg - arguments passed with command + * + * Returned Value: + * + ****************************************************************************/ + +static int adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg) +{ + int ret; + struct adc_chan_s *priv = (struct adc_chan_s *)dev->ad_priv; + + ainfo("channel: %" PRIu8 " cmd=%d\n", priv->channel, cmd); + + switch (cmd) + { + case ANIOC_TRIGGER: + { + /* Start sampling and read ADC value here */ + + adc_read_work(dev); + ret = OK; + } + break; + + case ANIOC_GET_NCHANNELS: + { + /* Return the number of configured channels */ + + ret = priv->channel; + } + break; + + default: + { + aerr("ERROR: Unknown cmd: %d\n", cmd); + ret = -ENOTTY; + } + break; + } + + return ret; +} + +/**************************************************************************** + * Name: adc_shutdown + * + * Description: + * Disable the ADC. This method is called when the ADC device is closed. + * This method reverses the operation the setup method. + * + * Input Parameters: + * + * Returned Value: + * + ****************************************************************************/ + +static void adc_shutdown(struct adc_dev_s *dev) +{ + struct adc_chan_s *priv = (struct adc_chan_s *)dev->ad_priv; + + ainfo("channel: %" PRIu8 "\n", priv->channel); + + /* Decrement count only when ADC device is in use */ + + if (priv->ref > 0) + { + priv->ref--; + + /* Shutdown the ADC device only when not in use */ + + if (!priv->ref) + { + adc_rxint(dev, false); + + /* Disable ADC clock */ + + adc_disable_clk(); + } + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s3_adc_init + * + * Description: + * Initialize the ADC. + * + * Input Parameters: + * adc_index - ADC channel number + * dev - pointer to device structure used by the driver + * + * Returned Value: + * + ****************************************************************************/ + +void esp32s3_adc_init(int adc_index, struct adc_dev_s *dev) +{ + ainfo("ADC index: %" PRIu8 "\n", adc_index); + + dev->ad_ops = &g_adcops; + + switch (adc_index) + { +#if defined(CONFIG_ESP32S3_ADC1_CHANNEL0) + case 0: + dev->ad_priv = &g_adc1_chan0; + break; +#endif + +#if defined(CONFIG_ESP32S3_ADC1_CHANNEL1) + case 1: + dev->ad_priv = &g_adc1_chan1; + break; +#endif + +#if defined(CONFIG_ESP32S3_ADC1_CHANNEL2) + case 2: + dev->ad_priv = &g_adc1_chan2; + break; +#endif + +#if defined(CONFIG_ESP32S3_ADC1_CHANNEL3) + case 3: + dev->ad_priv = &g_adc1_chan3; + break; +#endif + +#if defined(CONFIG_ESP32S3_ADC1_CHANNEL4) + case 4: + dev->ad_priv = &g_adc1_chan4; + break; +#endif + +#if defined(CONFIG_ESP32S3_ADC1_CHANNEL5) + case 5: + dev->ad_priv = &g_adc1_chan5; + break; +#endif + +#if defined(CONFIG_ESP32S3_ADC1_CHANNEL6) + case 6: + dev->ad_priv = &g_adc1_chan6; + break; +#endif + +#if defined(CONFIG_ESP32S3_ADC1_CHANNEL7) + case 7: + dev->ad_priv = &g_adc1_chan7; + break; +#endif + +#if defined(CONFIG_ESP32S3_ADC1_CHANNEL8) + case 8: + dev->ad_priv = &g_adc1_chan8; + break; +#endif + +#if defined(CONFIG_ESP32S3_ADC1_CHANNEL9) + case 9: + dev->ad_priv = &g_adc1_chan9; + break; +#endif + + default: + { + aerr("ERROR: No ADC interface defined\n"); + } + } +} diff --git a/arch/xtensa/src/esp32s3/esp32s3_adc.h b/arch/xtensa/src/esp32s3/esp32s3_adc.h new file mode 100644 index 0000000000000..a64bc4a3e53fb --- /dev/null +++ b/arch/xtensa/src/esp32s3/esp32s3_adc.h @@ -0,0 +1,93 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/esp32s3_adc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_ADC_H +#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_ADC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#ifdef CONFIG_ESP32S3_ADC +# define ESP32S3_ADC1 1 +# define ESP32S3_ADC1_CHANNEL0 0 +# define ESP32S3_ADC1_CHANNEL1 1 +# define ESP32S3_ADC1_CHANNEL2 2 +# define ESP32S3_ADC1_CHANNEL3 3 +# define ESP32S3_ADC1_CHANNEL4 4 +# define ESP32S3_ADC1_CHANNEL5 5 +# define ESP32S3_ADC1_CHANNEL6 6 +# define ESP32S3_ADC1_CHANNEL7 7 +# define ESP32S3_ADC1_CHANNEL8 8 +# define ESP32S3_ADC1_CHANNEL9 9 +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: esp32s3_adc_init + * + * Description: + * Initialize the ADC. + * + * Input Parameters: + * channel - ADC channel number + * + * Returned Value: + * ADC device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +void esp32s3_adc_init(int adc_index, struct adc_dev_s *dev); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_ADC_H */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_aes.c b/arch/xtensa/src/esp32s3/esp32s3_aes.c new file mode 100644 index 0000000000000..3530c7e5f037d --- /dev/null +++ b/arch/xtensa/src/esp32s3/esp32s3_aes.c @@ -0,0 +1,1080 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/esp32s3_aes.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "xtensa.h" +#include "esp32s3_aes.h" + +#include "hardware/esp32s3_aes.h" +#include "hardware/esp32s3_system.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define AES_BLK_SIZE (16) + +#define AES_MODE_DECRYPT (BIT(2)) + +#define AES_IDLE_STATE (0) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static bool g_aes_inited; +static mutex_t g_aes_lock = NXMUTEX_INITIALIZER; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: aes_hw_setkey + * + * Description: + * Set AES hardware key and encryption/decryption mode + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void aes_hw_setkey(struct esp32s3_aes_s *aes, bool encrypt) +{ + int i; + uint32_t cryptbits = encrypt ? 0 : AES_MODE_DECRYPT; + uint32_t keybits = (aes->keybits / 64) - 2; + uint32_t keywords = aes->keybits / 32; + + putreg32(cryptbits | keybits, AES_MODE_REG); + + for (i = 0; i < keywords; ++i) + { + putreg32(aes->key[i], AES_KEY_0_REG + i * 4); + } +} + +/**************************************************************************** + * Name: aes_hw_cypher + * + * Description: + * Process AES hardware encryption/decryption. + * + * Input Parameters: + * s - Input data pointer + * d - Output buffer pointer + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void aes_hw_cypher(const uint8_t *s, uint8_t *d) +{ + uint32_t buffer[AES_BLK_SIZE / 4]; + + memcpy(buffer, s, AES_BLK_SIZE); + + putreg32(buffer[0], AES_TEXT_IN_0_REG + 0); + putreg32(buffer[1], AES_TEXT_IN_0_REG + 4); + putreg32(buffer[2], AES_TEXT_IN_0_REG + 8); + putreg32(buffer[3], AES_TEXT_IN_0_REG + 12); + + putreg32(AES_TRIGGER_M, AES_TRIGGER_REG); + + while (getreg32(AES_STATE_REG) != AES_IDLE_STATE) + { + } + + buffer[0] = getreg32(AES_TEXT_OUT_0_REG + 0); + buffer[1] = getreg32(AES_TEXT_OUT_0_REG + 4); + buffer[2] = getreg32(AES_TEXT_OUT_0_REG + 8); + buffer[3] = getreg32(AES_TEXT_OUT_0_REG + 12); + + memcpy(d, buffer, AES_BLK_SIZE); +} + +/**************************************************************************** + * Name: gf128mul_x_ble + * + * Description: + * GF(2^128) multiplication function. + * + * Input Parameters: + * d - Result buffer + * s - Input data buffer + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void gf128mul_x_ble(uint8_t *d, const uint8_t *s) +{ + uint64_t a, b, ra, rb; + + memcpy(&a, s, 8); + memcpy(&b, s + 8, 8); + + ra = (a << 1) ^ (0x0087 >> (8 - ((b >> 63) << 3))); + rb = (a >> 63) | (b << 1); + + memcpy(d, &ra, 8); + memcpy(d + 8, &rb, 8); +} + +#ifdef CONFIG_ESP32S3_AES_ACCELERATOR_TEST + +/**************************************************************************** + * Name: esp32s3_aes_ecb_test + * + * Description: + * ESP32-S3 AES-ECB test. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32s3_aes_ecb_test(void) +{ + int ret; + int i; + int keybits; + uint8_t encrypt_buf[16]; + uint8_t decrypt_buf[16]; + struct esp32s3_aes_s aes; + const int size = 16; + + const uint32_t input[8] = + { + 0x740fdb34, 0x002defca, 0xb042437b, 0xc2f42cf9, + 0xc64444be, 0x32365bc1, 0xb613cfa2, 0x15ce0d23 + }; + + const uint32_t key[16] = + { + 0x8ffdc2c5, 0x14d6c69d, 0x9cb7608f, 0x899b2472, + 0xbf9e4372, 0x855290d0, 0xc62753da, 0xdeedeab7 + }; + + const uint32_t result[2][4] = + { + /* keybits = 128 */ + + { + 0xc810df2a, 0x8ae67e6e, 0x50c5e32c, 0xd535f3e4 + }, + + /* keybits = 256 */ + + { + 0xa0714c2b, 0x356adb1f, 0xe905c243, 0x35195a7c + } + }; + + for (i = 0; i < 2; i++) + { + keybits = i * 128 + 128; + + ret = esp32s3_aes_setkey(&aes, key, keybits); + DEBUGASSERT(ret == 0); + + ret = esp32s3_aes_ecb_cypher(&aes, 1, input, encrypt_buf, size); + DEBUGASSERT(ret == 0); + + if (memcmp(encrypt_buf, result[i], size)) + { + DEBUGASSERT(0); + } + + ret = esp32s3_aes_ecb_cypher(&aes, 0, encrypt_buf, decrypt_buf, size); + DEBUGASSERT(ret == 0); + + if (memcmp(decrypt_buf, input, size)) + { + DEBUGASSERT(0); + } + + syslog(LOG_INFO, "AES ECB key=%d bits test: PASS\n", keybits); + } +} + +/**************************************************************************** + * Name: esp32s3_aes_cbc_test + * + * Description: + * ESP32-S3 AES-CBC test. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32s3_aes_cbc_test(void) +{ + int ret; + int i; + int keybits; + uint8_t encrypt_buf[32]; + uint8_t decrypt_buf[32]; + uint8_t iv_buf[16]; + struct esp32s3_aes_s aes; + const int size = 32; + + const uint32_t input[8] = + { + 0x740fdb34, 0x002defca, 0xb042437b, 0xc2f42cf9, + 0xc64444be, 0x32365bc1, 0xb613cfa2, 0x15ce0d23 + }; + + const uint32_t key[16] = + { + 0x8ffdc2c5, 0x14d6c69d, 0x9cb7608f, 0x899b2472, + 0xbf9e4372, 0x855290d0, 0xc62753da, 0xdeedeab7 + }; + + const uint32_t iv[4] = + { + 0xf53a50f2, 0x8aaf711d, 0x953bbbfa, 0x228d53cb + }; + + const uint32_t result[2][8] = + { + /* keybits = 128 */ + + { + 0x04e27d12, 0x1a91e508, 0x01092431, 0x9d572184, + 0xa39979e1, 0x5543e1bc, 0x7173b71d, 0x4e3be064 + }, + + /* keybits = 256 */ + + { + 0x6f36b8fe, 0x33bc1f37, 0x24fe659c, 0x0370def0, + 0xb9a852f8, 0x64a79ae2, 0xd59f5045, 0x648a0f44 + } + }; + + for (i = 0; i < 2; i++) + { + keybits = i * 128 + 128; + + ret = esp32s3_aes_setkey(&aes, key, keybits); + DEBUGASSERT(ret == 0); + + memcpy(iv_buf, iv, 16); + ret = esp32s3_aes_cbc_cypher(&aes, 1, iv_buf, input, + encrypt_buf, size); + DEBUGASSERT(ret == 0); + + if (memcmp(encrypt_buf, result[i], size)) + { + DEBUGASSERT(0); + } + + memcpy(iv_buf, iv, 16); + ret = esp32s3_aes_cbc_cypher(&aes, 0, iv_buf, encrypt_buf, + decrypt_buf, size); + DEBUGASSERT(ret == 0); + + if (memcmp(decrypt_buf, input, size)) + { + DEBUGASSERT(0); + } + + syslog(LOG_INFO, "AES CBC key=%d bits test: PASS\n", keybits); + } +} + +/**************************************************************************** + * Name: esp32s3_aes_ctr_test + * + * Description: + * ESP32-S3 AES-CTR test. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32s3_aes_ctr_test(void) +{ + int ret; + int i; + int keybits; + uint8_t encrypt_buf[32]; + uint8_t decrypt_buf[32]; + uint8_t cnt_buf[16]; + uint8_t cache_buf[16]; + uint32_t nc_off; + struct esp32s3_aes_s aes; + const int size = 32; + + const uint32_t input[8] = + { + 0x740fdb34, 0x002defca, 0xb042437b, 0xc2f42cf9, + 0xc64444be, 0x32365bc1, 0xb613cfa2, 0x15ce0d23 + }; + + const uint32_t key[16] = + { + 0x8ffdc2c5, 0x14d6c69d, 0x9cb7608f, 0x899b2472, + 0xbf9e4372, 0x855290d0, 0xc62753da, 0xdeedeab7 + }; + + const uint32_t cnt[4] = + { + 0xf53a50f2, 0x8aaf711d, 0x953bbbfa, 0x228d53cb + }; + + const uint32_t result[2][8] = + { + /* keybits = 128 */ + + { + 0x5f922338, 0x5aff403d, 0x45fede3f, 0x616568c6, + 0x3cd0ffc7, 0xa26cb704, 0x0aaa8b6a, 0x1d0b5e1c + }, + + /* keybits = 256 */ + + { + 0x70af4473, 0x597d2126, 0xd598ed09, 0x3fea540c, + 0xfb5c743c, 0x0c1a39ca, 0xcbcf2d17, 0x341a7a0c + } + }; + + for (i = 0; i < 2; i++) + { + keybits = i * 128 + 128; + + ret = esp32s3_aes_setkey(&aes, key, keybits); + DEBUGASSERT(ret == 0); + + nc_off = 0; + memcpy(cnt_buf, cnt, 16); + ret = esp32s3_aes_ctr_cypher(&aes, &nc_off, cnt_buf, cache_buf, + input, encrypt_buf, size); + DEBUGASSERT(ret == 0); + + if (memcmp(encrypt_buf, result[i], size)) + { + DEBUGASSERT(0); + } + + nc_off = 0; + memcpy(cnt_buf, cnt, 16); + ret = esp32s3_aes_ctr_cypher(&aes, &nc_off, cnt_buf, cache_buf, + encrypt_buf, decrypt_buf, size); + DEBUGASSERT(ret == 0); + + if (memcmp(decrypt_buf, input, size)) + { + DEBUGASSERT(0); + } + + syslog(LOG_INFO, "AES CTR key=%d bits test: PASS\n", keybits); + } +} + +/**************************************************************************** + * Name: esp32s3_aes_xts_test + * + * Description: + * ESP32-S3 AES-XTS test. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32s3_aes_xts_test(void) +{ + int ret; + int i; + int keybits; + uint8_t encrypt_buf[32]; + uint8_t decrypt_buf[32]; + uint8_t unit_buf[16]; + struct esp32s3_aes_xts_s aes; + int size; + + const uint32_t input[8] = + { + 0x740fdb34, 0x002defca, 0xb042437b, 0xc2f42cf9, + 0xc64444be, 0x32365bc1, 0xb613cfa2, 0x15ce0d23 + }; + + const uint32_t key[16] = + { + 0x8ffdc2c5, 0x14d6c69d, 0x9cb7608f, 0x899b2472, + 0xbf9e4372, 0x855290d0, 0xc62753da, 0xdeedeab7, + 0x7ac6c53b, 0xc94f0b81, 0xdd673fc9, 0x8c1b71a6, + 0x1f99b728, 0x5e7af2eb, 0xcc7274a3, 0xf0005b23 + }; + + const uint32_t unit[4] = + { + 0xf53a50f2, 0x8aaf711d, 0x953bbbfa, 0x228d53cb + }; + + const uint32_t result_in32[2][8] = + { + /* keybits = 256 */ + + { + 0xf70e05fd, 0x2791be41, 0x926ec006, 0xc76068f4, + 0x01fd0843, 0xdf5e576a, 0xa4b1833d, 0x90502608 + }, + + /* keybits = 512 */ + + { + 0x164b4185, 0x4cb1cce7, 0xf285e523, 0x06a5923a, + 0xae4fcb7b, 0x59ce9dc6, 0xed64546f, 0x5889cb17 + } + }; + + const uint32_t result_in30[2][8] = + { + /* keybits = 256 */ + + { + 0x26991fb6, 0x72e4a7bc, 0x97041d61, 0x9ec889af, + 0xf70e05fd, 0x2791be41, 0x926ec006, 0x000068f4 + }, + + /* keybits = 512 */ + + { + 0x4b42dd86, 0xeee792c0, 0x1516ff95, 0x1f5fd9e6, + 0x164b4185, 0x4cb1cce7, 0xf285e523, 0x0000923a + } + }; + + for (i = 0; i < 2; i++) + { + keybits = i * 256 + 256; + + ret = esp32s3_aes_xts_setkey(&aes, key, keybits); + DEBUGASSERT(ret == 0); + + /* Encrypt/Decrypt 32 bytes */ + + size = 32; + + memcpy(unit_buf, unit, 16); + ret = esp32s3_aes_xts_cypher(&aes, true, unit_buf, input, + encrypt_buf, size); + DEBUGASSERT(ret == 0); + + if (memcmp(encrypt_buf, result_in32[i], size)) + { + DEBUGASSERT(0); + } + + memcpy(unit_buf, unit, 16); + ret = esp32s3_aes_xts_cypher(&aes, false, unit_buf, encrypt_buf, + decrypt_buf, size); + DEBUGASSERT(ret == 0); + + if (memcmp(decrypt_buf, input, size)) + { + DEBUGASSERT(0); + } + + /* Encrypt/Decrypt 30 bytes */ + + size = 30; + + memcpy(unit_buf, unit, 16); + ret = esp32s3_aes_xts_cypher(&aes, true, unit_buf, input, + encrypt_buf, size); + DEBUGASSERT(ret == 0); + + if (memcmp(encrypt_buf, result_in30[i], size)) + { + DEBUGASSERT(0); + } + + memcpy(unit_buf, unit, 16); + ret = esp32s3_aes_xts_cypher(&aes, false, unit_buf, encrypt_buf, + decrypt_buf, size); + DEBUGASSERT(ret == 0); + + if (memcmp(decrypt_buf, input, size)) + { + DEBUGASSERT(0); + } + + syslog(LOG_INFO, "AES XTS key=%d bits test: PASS\n", keybits); + } +} + +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s3_aes_ecb_cypher + * + * Description: + * Process AES ECB encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32s3_aes_ecb_cypher(struct esp32s3_aes_s *aes, bool encrypt, + const void *input, void *output, uint32_t size) +{ + int ret; + uint32_t i; + const uint8_t *s = (const uint8_t *)input; + uint8_t *d = (uint8_t *)output; + + DEBUGASSERT(aes && input && output); + DEBUGASSERT(size && ((size % AES_BLK_SIZE) == 0)); + + ret = nxmutex_lock(&g_aes_lock); + if (ret < 0) + { + return ret; + } + + aes_hw_setkey(aes, encrypt); + + for (i = 0; i < size; i += AES_BLK_SIZE) + { + aes_hw_cypher(s, d); + + s += AES_BLK_SIZE; + d += AES_BLK_SIZE; + } + + ret = nxmutex_unlock(&g_aes_lock); + if (ret < 0) + { + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: esp32s3_aes_cbc_cypher + * + * Description: + * Process AES CBC encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * ivptr - Initialization vector pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32s3_aes_cbc_cypher(struct esp32s3_aes_s *aes, bool encrypt, + void *ivptr, const void *input, void *output, + uint32_t size) +{ + int ret; + uint32_t i; + uint32_t j; + const uint8_t *s = (const uint8_t *)input; + uint8_t *d = (uint8_t *)output; + uint8_t *iv = (uint8_t *)ivptr; + + DEBUGASSERT(aes && input && output && ivptr); + DEBUGASSERT(size && ((size % AES_BLK_SIZE) == 0)); + + ret = nxmutex_lock(&g_aes_lock); + if (ret < 0) + { + return ret; + } + + aes_hw_setkey(aes, encrypt); + + for (i = 0; i < size; i += AES_BLK_SIZE) + { + if (encrypt) + { + for (j = 0; j < AES_BLK_SIZE; j++) + { + d[j] = s[j] ^ iv[j]; + } + + aes_hw_cypher(d, d); + + memcpy(iv, d, AES_BLK_SIZE); + } + else + { + aes_hw_cypher(s, d); + + for (j = 0; j < AES_BLK_SIZE; j++) + { + d[j] = d[j] ^ iv[j]; + } + + memcpy(iv, s, AES_BLK_SIZE); + } + + s += AES_BLK_SIZE; + d += AES_BLK_SIZE; + } + + ret = nxmutex_unlock(&g_aes_lock); + if (ret < 0) + { + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: esp32s3_aes_ctr_cypher + * + * Description: + * Process AES CTR encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * offptr - Offset buffer pointer + * cntptr - Counter buffer pointer + * cacheptr - Counter calculation buffer pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32s3_aes_ctr_cypher(struct esp32s3_aes_s *aes, uint32_t *offptr, + void *cntptr, void *cacheptr, const void *input, + void *output, uint32_t size) +{ + int ret; + uint32_t i; + uint32_t j; + uint32_t n; + uint8_t *cnt = (uint8_t *)cntptr; + uint8_t *cache = (uint8_t *)cacheptr; + const uint8_t *s = (const uint8_t *)input; + uint8_t *d = (uint8_t *)output; + + DEBUGASSERT(aes && offptr && cntptr && cacheptr && input && output); + DEBUGASSERT(size); + + ret = nxmutex_lock(&g_aes_lock); + if (ret < 0) + { + return ret; + } + + aes_hw_setkey(aes, true); + + n = *offptr; + for (i = 0; i < size; i++) + { + if (n == 0) + { + aes_hw_cypher(cnt, cache); + for (j = AES_BLK_SIZE - 1; j > 0; j--) + { + cnt[j]++; + if (cnt[j] != 0) + { + break; + } + } + } + + d[i] = s[i] ^ cache[n]; + + n = (n + 1) & (AES_BLK_SIZE - 1); + } + + *offptr = n; + + ret = nxmutex_unlock(&g_aes_lock); + if (ret < 0) + { + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: esp32s3_aes_xts_cypher + * + * Description: + * Process AES XTS encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * unitptr - Unit data buffer pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32s3_aes_xts_cypher(struct esp32s3_aes_xts_s *aes, bool encrypt, + void *unitptr, const void *input, void *output, + uint32_t size) +{ + int ret; + uint32_t i; + uint32_t j; + uint32_t blks; + uint32_t rst; + uint8_t *t; + uint8_t *prev_output; + uint8_t tweak[AES_BLK_SIZE]; + uint8_t prev_tweak[AES_BLK_SIZE]; + uint8_t tmp[AES_BLK_SIZE]; + uint8_t *unit = (uint8_t *)unitptr; + const uint8_t *s = (const uint8_t *)input; + uint8_t *d = (uint8_t *)output; + + DEBUGASSERT(aes && unitptr && input && output); + + /* NIST SP 80-38E disallows data units larger than 2**20 blocks. */ + + DEBUGASSERT((size >= AES_BLK_SIZE) && + (size <= ((1 << 20) * AES_BLK_SIZE))); + + ret = nxmutex_lock(&g_aes_lock); + if (ret < 0) + { + return ret; + } + + blks = size / AES_BLK_SIZE; + rst = size % AES_BLK_SIZE; + + aes_hw_setkey(&aes->tweak, true); + aes_hw_cypher(unit, tweak); + + for (i = 0; i < blks; i++) + { + if (rst && (encrypt == false) && (blks == 1)) + { + memcpy(prev_tweak, tweak, AES_BLK_SIZE); + gf128mul_x_ble(tweak, tweak); + } + + for (j = 0; j < AES_BLK_SIZE; j++) + { + tmp[j] = s[j] ^ tweak[j]; + } + + aes_hw_setkey(&aes->crypt, encrypt); + aes_hw_cypher(tmp, tmp); + + for (j = 0; j < AES_BLK_SIZE; j++) + { + d[j] = tmp[j] ^ tweak[j]; + } + + gf128mul_x_ble(tweak, tweak); + + s += AES_BLK_SIZE; + d += AES_BLK_SIZE; + } + + if (rst) + { + t = encrypt ? tweak : prev_tweak; + prev_output = d - AES_BLK_SIZE; + + for (i = 0; i < rst; i++) + { + d[i] = prev_output[i]; + tmp[i] = s[i] ^ t[i]; + } + + for (; i < AES_BLK_SIZE; i++) + { + tmp[i] = prev_output[i] ^ t[i]; + } + + aes_hw_setkey(&aes->crypt, encrypt); + aes_hw_cypher(tmp, tmp); + + for (i = 0; i < AES_BLK_SIZE; i++) + { + prev_output[i] = tmp[i] ^ t[i]; + } + } + + ret = nxmutex_unlock(&g_aes_lock); + if (ret < 0) + { + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: esp32s3_aes_setkey + * + * Description: + * Configurate AES key. + * + * Input Parameters: + * aes - AES object data pointer + * keyptr - Key data pointer + * keybits - Key data bits + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32s3_aes_setkey(struct esp32s3_aes_s *aes, const void *keyptr, + uint16_t keybits) +{ + DEBUGASSERT(aes && keyptr); + + if ((keybits != 128) && (keybits != 256)) + { + return -EINVAL; + } + + aes->keybits = keybits; + memcpy(aes->key, keyptr, keybits / 8); + + return OK; +} + +/**************************************************************************** + * Name: esp32s3_aes_xts_setkey + * + * Description: + * Configurate AES XTS key. + * + * Input Parameters: + * aes - AES object data pointer + * keyptr - Key data pointer + * keybits - Key data bits + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32s3_aes_xts_setkey(struct esp32s3_aes_xts_s *aes, const void *keyptr, + uint16_t keybits) +{ + const uint8_t *key = (const uint8_t *)keyptr; + uint16_t half_keybits = keybits / 2; + + DEBUGASSERT(aes && keyptr); + + if ((keybits != 256) && (keybits != 512)) + { + return -EINVAL; + } + + aes->crypt.keybits = half_keybits; + memcpy(aes->crypt.key, key, half_keybits / 8); + + aes->tweak.keybits = half_keybits; + memcpy(aes->tweak.key, key + half_keybits / 8, half_keybits / 8); + + return OK; +} + +/**************************************************************************** + * Name: esp32s3_aes_init + * + * Description: + * Initialize ESP32-S3 AES hardware. + * + * Input Parameters: + * None + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32s3_aes_init(void) +{ + if (g_aes_inited == false) + { + modifyreg32(SYSTEM_PERIP_CLK_EN1_REG, 0, SYSTEM_CRYPTO_AES_CLK_EN); + modifyreg32(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_CRYPTO_AES_RST, 0); + g_aes_inited = true; + } + + return OK; +} + +/**************************************************************************** + * Name: aes_cypher + ****************************************************************************/ + +#ifdef CONFIG_CRYPTO_AES + +int aes_cypher(void *out, const void *in, size_t size, + const void *iv, const void *key, size_t keysize, + int mode, int encrypt) +{ + int ret; + uint8_t iv_buf[AES_BLK_SIZE]; + uint8_t cache_buf[AES_BLK_SIZE]; + uint32_t nc_off; + struct esp32s3_aes_s aes; + + if ((size & (AES_BLK_SIZE - 1)) != 0) + { + return -EINVAL; + } + + if (mode == AES_MODE_CTR) + { + keysize -= 4; + } + + if (keysize != 16 && keysize != 32) + { + return -EINVAL; + } + + if ((mode != AES_MODE_ECB) && + (mode != AES_MODE_CBC) && + (mode != AES_MODE_CTR)) + { + return -EINVAL; + } + + ret = esp32s3_aes_init(); + if (ret < 0) + { + return ret; + } + + ret = esp32s3_aes_setkey(&aes, key, keysize * 8); + if (ret < 0) + { + return ret; + } + + switch (mode) + { + case AES_MODE_ECB: + ret = esp32s3_aes_ecb_cypher(&aes, encrypt, in, out, size); + break; + case AES_MODE_CBC: + memcpy(iv_buf, iv, AES_BLK_SIZE); + ret = esp32s3_aes_cbc_cypher(&aes, encrypt, iv_buf, in, out, size); + break; + case AES_MODE_CTR: + nc_off = 0; + memcpy(iv_buf, iv, AES_BLK_SIZE); + ret = esp32s3_aes_ctr_cypher(&aes, &nc_off, iv_buf, cache_buf, + in, out, size); + break; + default : + ret = -EINVAL; + break; + } + + return ret; +} + +#endif + +#ifdef CONFIG_ESP32S3_AES_ACCELERATOR_TEST + +/**************************************************************************** + * Name: esp32s3_aes_test + ****************************************************************************/ + +void esp32s3_aes_test(void) +{ + esp32s3_aes_ecb_test(); + esp32s3_aes_cbc_test(); + esp32s3_aes_ctr_test(); + esp32s3_aes_xts_test(); + syslog(LOG_INFO, "\nAES hardware accelerate test done.\n"); +} + +#endif diff --git a/arch/xtensa/src/esp32s3/esp32s3_aes.h b/arch/xtensa/src/esp32s3/esp32s3_aes.h new file mode 100644 index 0000000000000..5b6e8c9aaadfd --- /dev/null +++ b/arch/xtensa/src/esp32s3/esp32s3_aes.h @@ -0,0 +1,227 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/esp32s3_aes.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_AES_H +#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_AES_H + +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* AES private description */ + +struct esp32s3_aes_s +{ + uint32_t key[8]; /* Key data value */ + uint16_t keybits; /* Key data bits */ +}; + +/* AES XTS private description */ + +struct esp32s3_aes_xts_s +{ + struct esp32s3_aes_s crypt; /* AES block encryption/decryption */ + struct esp32s3_aes_s tweak; /* AES tweak encryption/decryption */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s3_aes_ecb_cypher + * + * Description: + * Process AES ECB encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32s3_aes_ecb_cypher(struct esp32s3_aes_s *aes, bool encrypt, + const void *input, void *output, uint32_t size); + +/**************************************************************************** + * Name: esp32s3_aes_cbc_cypher + * + * Description: + * Process AES CBC encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * ivptr - Initialization vector pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32s3_aes_cbc_cypher(struct esp32s3_aes_s *aes, bool encrypt, + void *ivptr, const void *input, void *output, + uint32_t size); + +/**************************************************************************** + * Name: esp32s3_aes_ctr_cypher + * + * Description: + * Process AES CTR encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * offptr - Offset buffer pointer + * cntptr - Counter buffer pointer + * cacheptr - Counter calculation buffer pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32s3_aes_ctr_cypher(struct esp32s3_aes_s *aes, uint32_t *offptr, + void *cntptr, void *cacheptr, const void *input, + void *output, uint32_t size); + +/**************************************************************************** + * Name: esp32s3_aes_xts_cypher + * + * Description: + * Process AES XTS encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * unitptr - Unit data buffer pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32s3_aes_xts_cypher(struct esp32s3_aes_xts_s *aes, bool encrypt, + void *unitptr, const void *input, void *output, + uint32_t size); + +/**************************************************************************** + * Name: esp32s3_aes_setkey + * + * Description: + * Configurate AES key. + * + * Input Parameters: + * aes - AES object data pointer + * keyptr - Key data pointer + * keybits - Key data bits + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32s3_aes_setkey(struct esp32s3_aes_s *aes, const void *keyptr, + uint16_t keybits); + +/**************************************************************************** + * Name: esp32s3_aes_xts_setkey + * + * Description: + * Configurate AES XTS key. + * + * Input Parameters: + * aes - AES object data pointer + * keyptr - Key data pointer + * keybits - Key data bits + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32s3_aes_xts_setkey(struct esp32s3_aes_xts_s *aes, const void *keyptr, + uint16_t keybits); + +/**************************************************************************** + * Name: esp32s3_aes_init + * + * Description: + * Initialize ESP32-S3 AES hardware driver. + * + * Input Parameters: + * None + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp32s3_aes_init(void); + +#ifdef CONFIG_ESP32S3_AES_ACCELERATOR_TEST + +/**************************************************************************** + * Name: esp32s3_aes_test + ****************************************************************************/ + +void esp32s3_aes_test(void); + +#endif + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_ESP32S3_LEGACY_ESP32S3_AES_H */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c b/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c index 6684e8af1c189..5f5b537d16e7c 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c +++ b/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c @@ -53,28 +53,31 @@ #include "hardware/wdev_reg.h" #include "rom/esp32s3_spiflash.h" #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "esp32s3_irq.h" -#include "esp32s3_periph.h" #include "esp32s3_rt_timer.h" #include "esp32s3_rtc.h" #include "esp32s3_spiflash.h" #include "esp32s3_wireless.h" -#include "esp32s3_ble_adapter.h" +#include "esp_bt.h" +#include "esp_log.h" +#include "esp_mac.h" +#include "esp_private/phy.h" +#include "esp_private/wifi.h" +#include "esp_random.h" +#include "esp_timer.h" +#include "periph_ctrl.h" +#include "rom/ets_sys.h" +#include "soc/soc_caps.h" +#include "esp_coexist_internal.h" -#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST -# include "esp_coexist_internal.h" -#endif +#include "esp32s3_ble_adapter.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define OSI_FUNCS_TIME_BLOCKING 0xffffffff -#define OSI_VERSION 0x00010006 -#define OSI_MAGIC_VALUE 0xfadebead - #define BTDM_MIN_TIMER_UNCERTAINTY_US (1800) /* Sleep and wakeup interval control */ @@ -89,9 +92,13 @@ #define BTDM_LPCLK_SEL_RTC_SLOW (2) #define BTDM_LPCLK_SEL_8M (3) +#define OSI_FUNCS_TIME_BLOCKING 0xffffffff +#define OSI_VERSION 0x00010006 +#define OSI_MAGIC_VALUE 0xfadebead + #ifdef CONFIG_ESP32S3_SPIFLASH # define BLE_TASK_EVENT_QUEUE_ITEM_SIZE 8 -# define BLE_TASK_EVENT_QUEUE_LEN 1 +# define BLE_TASK_EVENT_QUEUE_LEN 8 #endif #ifdef CONFIG_ESP32S3_BLE_INTERRUPT_SAVE_STATUS @@ -104,6 +111,77 @@ * Private Types ****************************************************************************/ +/* VHCI function interface */ + +typedef struct vhci_host_callback_s +{ + void (*notify_host_send_available)(void); /* callback used to notify that the host can send packet to controller */ + int (*notify_host_recv)(uint8_t *data, uint16_t len); /* callback used to notify that the controller has a packet to send to the host */ +} vhci_host_callback_t; + +/* BLE OS function */ + +struct osi_funcs_s +{ + uint32_t _magic; + uint32_t _version; + void (*_interrupt_set)(int cpu_no, int intr_source, + int interrupt_no, int interrpt_prio); + void (*_interrupt_clear)(int interrupt_source, int interrupt_no); + void (*_interrupt_handler_set)(int interrupt_no, void * fn, void *arg); + void (*_interrupt_disable)(void); + void (*_interrupt_restore)(void); + void (*_task_yield)(void); + void (*_task_yield_from_isr)(void); + void *(*_semphr_create)(uint32_t max, uint32_t init); + void (*_semphr_delete)(void *semphr); + int (*_semphr_take_from_isr)(void *semphr, void *hptw); + int (*_semphr_give_from_isr)(void *semphr, void *hptw); + int (*_semphr_take)(void *semphr, uint32_t block_time_ms); + int (*_semphr_give)(void *semphr); + void *(*_mutex_create)(void); + void (*_mutex_delete)(void *mutex); + int (*_mutex_lock)(void *mutex); + int (*_mutex_unlock)(void *mutex); + void *(* _queue_create)(uint32_t queue_len, uint32_t item_size); + void (* _queue_delete)(void *queue); + int (* _queue_send)(void *queue, void *item, uint32_t block_time_ms); + int (* _queue_send_from_isr)(void *queue, void *item, void *hptw); + int (* _queue_recv)(void *queue, void *item, uint32_t block_time_ms); + int (* _queue_recv_from_isr)(void *queue, void *item, void *hptw); + int (* _task_create)(void *task_func, const char *name, + uint32_t stack_depth, void *param, uint32_t prio, + void *task_handle, uint32_t core_id); + void (* _task_delete)(void *task_handle); + bool (* _is_in_isr)(void); + int (* _cause_sw_intr_to_core)(int core_id, int intr_no); + void *(* _malloc)(size_t size); + void *(* _malloc_internal)(size_t size); + void (* _free)(void *p); + int (* _read_efuse_mac)(uint8_t mac[6]); + void (* _srand)(unsigned int seed); + int (* _rand)(void); + uint32_t (* _btdm_lpcycles_2_hus)(uint32_t cycles, uint32_t *error_corr); + uint32_t (* _btdm_hus_2_lpcycles)(uint32_t us); + bool (* _btdm_sleep_check_duration)(int32_t *slot_cnt); + void (* _btdm_sleep_enter_phase1)(uint32_t lpcycles); /* called when interrupt is disabled */ + void (* _btdm_sleep_enter_phase2)(void); + void (* _btdm_sleep_exit_phase1)(void); /* called from ISR */ + void (* _btdm_sleep_exit_phase2)(void); /* called from ISR */ + void (* _btdm_sleep_exit_phase3)(void); /* called from task */ + void (* _coex_wifi_sleep_set)(bool sleep); + int (* _coex_core_ble_conn_dyn_prio_get)(bool *low, bool *high); + void (* _coex_schm_status_bit_set)(uint32_t type, uint32_t status); + void (* _coex_schm_status_bit_clear)(uint32_t type, uint32_t status); + void (* _interrupt_on)(int intr_num); + void (* _interrupt_off)(int intr_num); + void (* _esp_hw_power_down)(void); + void (* _esp_hw_power_up)(void); + void (* _ets_backup_dma_copy)(uint32_t reg, + uint32_t mem_addr, uint32_t num, + bool to_rem); +}; + /* BLE message queue private data */ struct mq_adpt_s @@ -179,91 +257,26 @@ struct bt_sem_s #endif }; -struct irqstate_list_s -{ - struct irqstate_list_s *flink; - irqstate_t flags; -}; - /* prototype of function to handle vendor dependent signals */ typedef void (*btdm_vnd_ol_task_func_t)(void *param); -/* VHCI function interface */ - -typedef struct vhci_host_callback_s -{ - void (*notify_host_send_available)(void); /* callback used to notify that the host can send packet to controller */ - int (*notify_host_recv)(uint8_t *data, uint16_t len); /* callback used to notify that the controller has a packet to send to the host */ -} vhci_host_callback_t; - typedef void (*osi_intr_handler)(void); -/* BLE OS function */ +/* List of nested IRQ status flags */ -struct osi_funcs_s +struct irqstate_list_s { - uint32_t _magic; - uint32_t _version; - void (*_interrupt_set)(int cpu_no, int intr_source, - int interrupt_no, int interrpt_prio); - void (*_interrupt_clear)(int interrupt_source, int interrupt_no); - void (*_interrupt_handler_set)(int interrupt_no, void * fn, void *arg); - void (*_interrupt_disable)(void); - void (*_interrupt_restore)(void); - void (*_task_yield)(void); - void (*_task_yield_from_isr)(void); - void *(*_semphr_create)(uint32_t max, uint32_t init); - void (*_semphr_delete)(void *semphr); - int (*_semphr_take_from_isr)(void *semphr, void *hptw); - int (*_semphr_give_from_isr)(void *semphr, void *hptw); - int (*_semphr_take)(void *semphr, uint32_t block_time_ms); - int (*_semphr_give)(void *semphr); - void *(*_mutex_create)(void); - void (*_mutex_delete)(void *mutex); - int (*_mutex_lock)(void *mutex); - int (*_mutex_unlock)(void *mutex); - void *(* _queue_create)(uint32_t queue_len, uint32_t item_size); - void (* _queue_delete)(void *queue); - int (* _queue_send)(void *queue, void *item, uint32_t block_time_ms); - int (* _queue_send_from_isr)(void *queue, void *item, void *hptw); - int (* _queue_recv)(void *queue, void *item, uint32_t block_time_ms); - int (* _queue_recv_from_isr)(void *queue, void *item, void *hptw); - int (* _task_create)(void *task_func, const char *name, - uint32_t stack_depth, void *param, uint32_t prio, - void *task_handle, uint32_t core_id); - void (* _task_delete)(void *task_handle); - bool (* _is_in_isr)(void); - int (* _cause_sw_intr_to_core)(int core_id, int intr_no); - void *(* _malloc)(size_t size); - void *(* _malloc_internal)(size_t size); - void (* _free)(void *p); - int (* _read_efuse_mac)(uint8_t mac[6]); - void (* _srand)(unsigned int seed); - int (* _rand)(void); - uint32_t (* _btdm_lpcycles_2_hus)(uint32_t cycles, uint32_t *error_corr); - uint32_t (* _btdm_hus_2_lpcycles)(uint32_t us); - bool (* _btdm_sleep_check_duration)(int32_t *slot_cnt); - void (* _btdm_sleep_enter_phase1)(uint32_t lpcycles); /* called when interrupt is disabled */ - void (* _btdm_sleep_enter_phase2)(void); - void (* _btdm_sleep_exit_phase1)(void); /* called from ISR */ - void (* _btdm_sleep_exit_phase2)(void); /* called from ISR */ - void (* _btdm_sleep_exit_phase3)(void); /* called from task */ - void (* _coex_wifi_sleep_set)(bool sleep); - int (* _coex_core_ble_conn_dyn_prio_get)(bool *low, bool *high); - void (* _coex_schm_status_bit_set)(uint32_t type, uint32_t status); - void (* _coex_schm_status_bit_clear)(uint32_t type, uint32_t status); - void (* _interrupt_on)(int intr_num); - void (* _interrupt_off)(int intr_num); - void (* _esp_hw_power_down)(void); - void (* _esp_hw_power_up)(void); - void (* _ets_backup_dma_copy)(uint32_t reg, - uint32_t mem_addr, uint32_t num, - bool to_rem); + struct irqstate_list_s *flink; + irqstate_t flags; }; /**************************************************************************** - * Private Function + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Functions to be registered to struct osi_funcs_s ****************************************************************************/ static void interrupt_set_wrapper(int cpu_no, int intr_source, @@ -283,13 +296,22 @@ static void *mutex_create_wrapper(void); static void mutex_delete_wrapper(void *mutex); static int mutex_lock_wrapper(void *mutex); static int mutex_unlock_wrapper(void *mutex); +static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size); +static void queue_delete_wrapper(void *queue); +static int queue_send_wrapper(void *queue, void *item, + uint32_t block_time_ms); static int IRAM_ATTR queue_send_from_isr_wrapper(void *queue, void *item, void *hptw); +static int queue_recv_wrapper(void *queue, void *item, + uint32_t block_time_ms); static int IRAM_ATTR queue_recv_from_isr_wrapper(void *queue, void *item, void *hptw); -static int task_create_wrapper(void *task_func, const char *name, - uint32_t stack_depth, void *param, - uint32_t prio, void *task_handle, +static int task_create_wrapper(void *task_func, + const char *name, + uint32_t stack_depth, + void *param, + uint32_t prio, + void *task_handle, uint32_t core_id); static void task_delete_wrapper(void *task_handle); static bool IRAM_ATTR is_in_isr_wrapper(void); @@ -301,31 +323,49 @@ static int IRAM_ATTR rand_wrapper(void); static uint32_t IRAM_ATTR btdm_lpcycles_2_hus(uint32_t cycles, uint32_t *error_corr); static uint32_t IRAM_ATTR btdm_hus_2_lpcycles(uint32_t us); +static bool IRAM_ATTR btdm_sleep_check_duration(int32_t *half_slot_cnt); +static void btdm_sleep_enter_phase1_wrapper(uint32_t lpcycles); +static void btdm_sleep_enter_phase2_wrapper(void); +static void btdm_sleep_exit_phase3_wrapper(void); static void coex_wifi_sleep_set_hook(bool sleep); static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status); static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status); + static void interrupt_on_wrapper(int intr_num); static void interrupt_off_wrapper(int intr_num); -static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size); -static int queue_send_wrapper(void *queue, void *item, - uint32_t block_time_ms); -static int queue_recv_wrapper(void *queue, void *item, - uint32_t block_time_ms); -static void queue_delete_wrapper(void *queue); - -static bool IRAM_ATTR btdm_sleep_check_duration(int32_t *half_slot_cnt); -static void btdm_sleep_enter_phase1_wrapper(uint32_t lpcycles); -static void btdm_sleep_enter_phase2_wrapper(void); -static void btdm_sleep_exit_phase3_wrapper(void); - -void IRAM_ATTR esp_wifi_bt_power_domain_on(void); void IRAM_ATTR btdm_hw_mac_power_down_wrapper(void); void IRAM_ATTR btdm_hw_mac_power_up_wrapper(void); void IRAM_ATTR btdm_backup_dma_copy_wrapper(uint32_t reg, uint32_t mem_addr, uint32_t num, bool to_mem); -static void esp32s3_bt_controller_deinit_internal(void); +/**************************************************************************** + * Other functions + ****************************************************************************/ + +static int32_t esp_task_create_pinned_to_core(void *entry, + const char *name, + uint32_t stack_depth, + void *param, + uint32_t prio, + void *task_handle, + uint32_t core_id); +static IRAM_ATTR int32_t esp_queue_send_generic(void *queue, + void *item, + uint32_t ticks, + int prio); +static void esp_update_time(struct timespec *timespec, uint32_t ticks); +static void IRAM_ATTR btdm_slp_tmr_callback(void *arg); +static int IRAM_ATTR esp_int_adpt_cb(int irq, void *context, void *arg); +static void IRAM_ATTR btdm_sleep_exit_phase0(void *param); +#if CONFIG_MAC_BB_PD +static void IRAM_ATTR btdm_mac_bb_power_down_cb(void); +static void IRAM_ATTR btdm_mac_bb_power_up_cb(void); +#endif +static void btdm_controller_mem_init(void); +static void bt_controller_deinit_internal(void); +static bool async_wakeup_request(int event); +static void async_wakeup_request_end(int event); /**************************************************************************** * Extern Functions declaration and value @@ -407,64 +447,6 @@ extern uint8_t _btdm_data_end[]; * Private Data ****************************************************************************/ -static DRAM_ATTR struct osi_funcs_s *osi_funcs_p; - -/* Controller status */ - -static DRAM_ATTR esp_bt_controller_status_t btdm_controller_status = - ESP_BT_CONTROLLER_STATUS_IDLE; - -/* low power control struct */ - -static DRAM_ATTR btdm_lpcntl_t g_lp_cntl; - -/* low power status struct */ - -static DRAM_ATTR btdm_lpstat_t g_lp_stat; - -/* measured average low power clock period in micro seconds */ - -static DRAM_ATTR uint32_t g_btdm_lpcycle_us = 0; - -/* number of fractional bit for g_btdm_lpcycle_us */ - -static DRAM_ATTR uint8_t g_btdm_lpcycle_us_frac = 0; - -/* semaphore used for blocking VHCI API to wait for controller to wake up */ - -static DRAM_ATTR void * g_wakeup_req_sem = NULL; - -/* wakeup timer */ - -static DRAM_ATTR esp_timer_handle_t g_btdm_slp_tmr; - -#ifdef CONFIG_PM -static DRAM_ATTR void * g_pm_lock; - -/* pm_lock to prevent light sleep due to incompatibility currently */ - -static DRAM_ATTR void * g_light_sleep_pm_lock; -#endif - -/* BT interrupt private data */ - -static sq_queue_t g_int_flags_free; - -static sq_queue_t g_int_flags_used; - -static struct irqstate_list_s g_int_flags[NR_IRQSTATE_FLAGS]; - -/* Cached queue control variables */ - -#ifdef CONFIG_ESP32S3_SPIFLASH -static struct esp_queuecache_s g_esp_queuecache; -static uint8_t g_esp_queuecache_buffer[BLE_TASK_EVENT_QUEUE_ITEM_SIZE]; -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - /* BLE OS adapter data */ static struct osi_funcs_s g_osi_funcs = @@ -523,67 +505,94 @@ static struct osi_funcs_s g_osi_funcs = ._ets_backup_dma_copy = btdm_backup_dma_copy_wrapper, }; -/**************************************************************************** - * Private Functions and Public Functions only used by libraries - ****************************************************************************/ +static DRAM_ATTR struct osi_funcs_s *osi_funcs_p; -/**************************************************************************** - * Name: btdm_hw_mac_power_down_wrapper - * - * Description: - * Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled - * - * Input Parameters: - * none - * - * Returned Value: - * none - * - ****************************************************************************/ +/* Controller status */ -void IRAM_ATTR btdm_hw_mac_power_down_wrapper(void) -{ -} +static DRAM_ATTR esp_bt_controller_status_t g_btdm_controller_status = + ESP_BT_CONTROLLER_STATUS_IDLE; -/**************************************************************************** - * Name: btdm_hw_mac_power_up_wrapper +/* measured average low power clock period in micro seconds */ - * - * Description: - * Power up MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled - * - * Input Parameters: - * none - * - * Returned Value: - * none - * +static DRAM_ATTR uint32_t g_btdm_lpcycle_us = 0; + +/* number of fractional bit for g_btdm_lpcycle_us */ + +static DRAM_ATTR uint8_t g_btdm_lpcycle_us_frac = 0; + +/* low power status struct */ + +static DRAM_ATTR btdm_lpstat_t g_lp_stat; + +/* low power control struct */ + +static DRAM_ATTR btdm_lpcntl_t g_lp_cntl; + +/* semaphore used for blocking VHCI API to wait for controller to wake up */ + +static DRAM_ATTR void * g_wakeup_req_sem = NULL; + +/* wakeup timer */ + +static DRAM_ATTR esp_timer_handle_t g_btdm_slp_tmr; + +#ifdef CONFIG_PM + +/* pm_lock to prevent light sleep due to incompatibility currently */ + +static DRAM_ATTR void * g_light_sleep_pm_lock; +#endif + +/* BT interrupt private data */ + +static sq_queue_t g_ble_int_flags_free; + +static sq_queue_t g_ble_int_flags_used; + +static struct irqstate_list_s g_ble_int_flags[NR_IRQSTATE_FLAGS]; + +/* Cached queue control variables */ + +#ifdef CONFIG_ESP32S3_SPIFLASH +static struct esp_queuecache_s g_esp_queuecache; +static uint8_t g_esp_queuecache_buffer[BLE_TASK_EVENT_QUEUE_ITEM_SIZE]; +#endif + +/**************************************************************************** + * Public Data ****************************************************************************/ -void IRAM_ATTR btdm_hw_mac_power_up_wrapper(void) -{ -} +/**************************************************************************** + * Private Functions + ****************************************************************************/ /**************************************************************************** - * Name: btdm_backup_dma_copy_wrapper + * Inline Functions + ****************************************************************************/ +/**************************************************************************** + * Name: esp_errno_trans * * Description: - * Copy btdm backup DMA when PHY is disabled + * Transform from nuttx error code to Wi-Fi adapter error code * * Input Parameters: - * none + * ret - NuttX error code * * Returned Value: - * none + * Wi-Fi adapter error code * ****************************************************************************/ -void IRAM_ATTR btdm_backup_dma_copy_wrapper(uint32_t reg, uint32_t mem_addr, - uint32_t num, bool to_mem) +static inline int32_t esp_errno_trans(int ret) { + return ret == 0; } +/**************************************************************************** + * Functions to be registered to struct osi_funcs_s + ****************************************************************************/ + /**************************************************************************** * Name: esp_bt_power_domain_on * @@ -630,25 +639,6 @@ static IRAM_ATTR void esp_bt_power_domain_off(void) esp_wifi_bt_power_domain_off(); } -/**************************************************************************** - * Name: esp_errno_trans - * - * Description: - * Transform from nuttx error code to Wi-Fi adapter error code - * - * Input Parameters: - * ret - NuttX error code - * - * Returned Value: - * Wi-Fi adapter error code - * - ****************************************************************************/ - -static inline int32_t esp_errno_trans(int ret) -{ - return ret == 0; -} - /**************************************************************************** * Name: interrupt_set_wrapper * @@ -700,29 +690,6 @@ static void IRAM_ATTR interrupt_clear_wrapper(int intr_source, int intr_num) { } -/**************************************************************************** - * Name: esp_int_adpt_cb - * - * Description: - * BT interrupt adapter callback function - * - * Input Parameters: - * arg - interrupt adapter private data - * - * Returned Value: - * NuttX error code - * - ****************************************************************************/ - -static int IRAM_ATTR esp_int_adpt_cb(int irq, void *context, void *arg) -{ - struct irq_adpt_s *adapter = (struct irq_adpt_s *)arg; - - adapter->func(adapter->arg); - - return OK; -} - /**************************************************************************** * Name: interrupt_handler_set_wrapper * @@ -755,49 +722,6 @@ static void interrupt_handler_set_wrapper(int intr_num, void *fn, void *arg) DEBUGVERIFY(irq_attach(irq, esp_int_adpt_cb, adapter)); } -/**************************************************************************** - * Name: interrupt_on_wrapper - * - * Description: - * Enable Wi-Fi interrupt - * - * Input Parameters: - * intr_num - The interrupt CPU number. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void interrupt_on_wrapper(int intr_num) -{ - int cpuint = intr_num; - int irq = esp32s3_getirq(0, cpuint); - - DEBUGVERIFY(esp32s3_irq_set_iram_isr(irq)); - - up_enable_irq(irq); -} - -/**************************************************************************** - * Name: interrupt_off_wrapper - * - * Description: - * Disable Wi-Fi interrupt - * - * Input Parameters: - * intr_num - No mean - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void interrupt_off_wrapper(int intr_num) -{ - up_disable_irq(intr_num + XTENSA_IRQ_FIRSTPERIPH); -} - /**************************************************************************** * Name: interrupt_disable * @@ -817,13 +741,13 @@ static void IRAM_ATTR interrupt_disable(void) { struct irqstate_list_s *irqstate; - irqstate = (struct irqstate_list_s *)sq_remlast(&g_int_flags_free); + irqstate = (struct irqstate_list_s *)sq_remlast(&g_ble_int_flags_free); - DEBUGASSERT(irqstate != NULL); + ASSERT(irqstate != NULL); irqstate->flags = enter_critical_section(); - sq_addlast((sq_entry_t *)irqstate, &g_int_flags_used); + sq_addlast((sq_entry_t *)irqstate, &g_ble_int_flags_used); } /**************************************************************************** @@ -845,13 +769,13 @@ static void IRAM_ATTR interrupt_restore(void) { struct irqstate_list_s *irqstate; - irqstate = (struct irqstate_list_s *)sq_remlast(&g_int_flags_used); + irqstate = (struct irqstate_list_s *)sq_remlast(&g_ble_int_flags_used); - DEBUGASSERT(irqstate != NULL); + ASSERT(irqstate != NULL); leave_critical_section(irqstate->flags); - sq_addlast((sq_entry_t *)irqstate, &g_int_flags_free); + sq_addlast((sq_entry_t *)irqstate, &g_ble_int_flags_free); } /**************************************************************************** @@ -999,36 +923,6 @@ static int IRAM_ATTR semphr_give_from_isr_wrapper(void *semphr, void *hptw) return esp_errno_trans(ret); } -/**************************************************************************** - * Name: esp_update_time - * - * Description: - * Transform ticks to time and add this time to timespec value - * - * Input Parameters: - * ticks - System ticks - * - * Output Parameters: - * timespec - Input timespec data pointer - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp_update_time(struct timespec *timespec, uint32_t ticks) -{ - uint32_t tmp; - - tmp = TICK2SEC(ticks); - timespec->tv_sec += tmp; - - ticks -= SEC2TICK(tmp); - tmp = TICK2NSEC(ticks); - - timespec->tv_nsec += tmp; -} - /**************************************************************************** * Name: semphr_take_wrapper * @@ -1212,121 +1106,50 @@ static int mutex_unlock_wrapper(void *mutex) } /**************************************************************************** - * Name: esp_queue_send_generic + * Name: queue_create_wrapper * * Description: - * Generic send message to queue within a certain period of time + * Create message queue * * Input Parameters: - * queue - Message queue data pointer - * item - Message data pointer - * ticks - Wait ticks - * prio - Message priority + * queue_len - queue message number + * item_size - message size * * Returned Value: - * True if success or false if fail + * Message queue data pointer * ****************************************************************************/ -static IRAM_ATTR int32_t esp_queue_send_generic(void *queue, void *item, - uint32_t ticks, int prio) +static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size) { + struct mq_attr attr; + struct mq_adpt_s *mq_adpt; int ret; - struct timespec timeout; - struct mq_adpt_s *mq_adpt = (struct mq_adpt_s *)queue; -#ifdef CONFIG_ESP32S3_SPIFLASH - if (!spi_flash_cache_enabled()) + mq_adpt = kmm_malloc(sizeof(struct mq_adpt_s)); + DEBUGASSERT(mq_adpt); + + snprintf(mq_adpt->name, sizeof(mq_adpt->name), "/tmp/%p", mq_adpt); + + attr.mq_maxmsg = queue_len; + attr.mq_msgsize = item_size; + attr.mq_curmsgs = 0; + attr.mq_flags = 0; + + ret = file_mq_open(&mq_adpt->mq, mq_adpt->name, + O_RDWR | O_CREAT, 0644, &attr); + + if (ret < 0) { - esp_send_queuecache(&g_esp_queuecache, item, mq_adpt->msgsize); - return esp_errno_trans(OK); + wlerr("Failed to create mqueue %d\n", ret); + kmm_free(mq_adpt); + return NULL; } -#endif - if (ticks == OSI_FUNCS_TIME_BLOCKING || ticks == 0) - { - /* BLE interrupt function will call this adapter function to send - * message to message queue, so here we should call kernel API - * instead of application API - */ - - ret = file_mq_send(&mq_adpt->mq, (const char *)item, - mq_adpt->msgsize, prio); - if (ret < 0) - { - wlerr("Failed to send message to mqueue error=%d\n", ret); - } - } - else - { - ret = clock_gettime(CLOCK_REALTIME, &timeout); - if (ret < 0) - { - wlerr("Failed to get time %d\n", ret); - return esp_errno_trans(ret); - } - - if (ticks) - { - esp_update_time(&timeout, ticks); - } - - ret = file_mq_timedsend(&mq_adpt->mq, (const char *)item, - mq_adpt->msgsize, prio, &timeout); - if (ret < 0) - { - wlerr("Failed to timedsend message to mqueue error=%d\n", ret); - } - } - - return esp_errno_trans(ret); -} - -/**************************************************************************** - * Name: queue_create_wrapper - * - * Description: - * Create message queue - * - * Input Parameters: - * queue_len - queue message number - * item_size - message size - * - * Returned Value: - * Message queue data pointer - * - ****************************************************************************/ - -static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size) -{ - struct mq_attr attr; - struct mq_adpt_s *mq_adpt; - int ret; - - mq_adpt = kmm_malloc(sizeof(struct mq_adpt_s)); - DEBUGASSERT(mq_adpt); - - snprintf(mq_adpt->name, sizeof(mq_adpt->name), "/tmp/%p", mq_adpt); - - attr.mq_maxmsg = queue_len; - attr.mq_msgsize = item_size; - attr.mq_curmsgs = 0; - attr.mq_flags = 0; - - ret = file_mq_open(&mq_adpt->mq, mq_adpt->name, - O_RDWR | O_CREAT, 0644, &attr); - - if (ret < 0) - { - wlerr("Failed to create mqueue %d\n", ret); - kmm_free(mq_adpt); - return NULL; - } - - mq_adpt->msgsize = item_size; + mq_adpt->msgsize = item_size; #ifdef CONFIG_ESP32S3_SPIFLASH - if (queue_len == BLE_TASK_EVENT_QUEUE_LEN && + if (queue_len <= BLE_TASK_EVENT_QUEUE_LEN && item_size == BLE_TASK_EVENT_QUEUE_ITEM_SIZE) { esp_init_queuecache(&g_esp_queuecache, @@ -1334,6 +1157,13 @@ static void *queue_create_wrapper(uint32_t queue_len, uint32_t item_size) g_esp_queuecache_buffer, BLE_TASK_EVENT_QUEUE_ITEM_SIZE); } + else + { + wlerr("Failed to create queue cache." + " Please incresase BLE_TASK_EVENT_QUEUE_LEN to, at least, %d", + queue_len); + return NULL; + } #endif return (void *)mq_adpt; @@ -1493,75 +1323,6 @@ static int IRAM_ATTR queue_recv_from_isr_wrapper(void *queue, return 0; } -/**************************************************************************** - * Name: esp_task_create_pinned_to_core - * - * Description: - * Create task and bind it to target CPU, the task will run when it - * is created - * - * Input Parameters: - * entry - Task entry - * name - Task name - * stack_depth - Task stack size - * param - Task private data - * prio - Task priority - * task_handle - Task handle pointer which is used to pause, resume - * and delete the task - * core_id - CPU which the task runs in - * - * Returned Value: - * True if success or false if fail - * - ****************************************************************************/ - -static int32_t esp_task_create_pinned_to_core(void *entry, - const char *name, - uint32_t stack_depth, - void *param, - uint32_t prio, - void *task_handle, - uint32_t core_id) -{ - int pid; -#ifdef CONFIG_SMP - int ret; - cpu_set_t cpuset; -#endif - - DEBUGASSERT(task_handle != NULL); - - pid = kthread_create(name, prio, stack_depth, entry, - (char * const *)param); - if (pid > 0) - { - if (task_handle) - { - *((int *)task_handle) = pid; - } - -#ifdef CONFIG_SMP - if (core_id < CONFIG_SMP_NCPUS) - { - CPU_ZERO(&cpuset); - CPU_SET(core_id, &cpuset); - ret = nxsched_set_affinity(pid, sizeof(cpuset), &cpuset); - if (ret) - { - wlerr("Failed to set affinity error=%d\n", ret); - return false; - } - } -#endif - } - else - { - wlerr("Failed to create task, error %d\n", pid); - } - - return pid > 0; -} - /**************************************************************************** * Name: task_create_wrapper * @@ -1771,6 +1532,7 @@ static uint32_t IRAM_ATTR btdm_lpcycles_2_hus(uint32_t cycles, { *error_corr = (uint32_t)local_error_corr; } + return (uint32_t)res; } @@ -1847,7 +1609,7 @@ static void btdm_sleep_enter_phase1_wrapper(uint32_t lpcycles) uint32_t us_to_sleep; uint32_t uncertainty; - if (!g_lp_cntl.wakeup_timer_required) + if (g_lp_cntl.wakeup_timer_required == 0) { return; } @@ -1864,7 +1626,7 @@ static void btdm_sleep_enter_phase1_wrapper(uint32_t lpcycles) uncertainty = BTDM_MIN_TIMER_UNCERTAINTY_US; } - DEBUGASSERT(g_lp_stat.wakeup_timer_started == false); + DEBUGASSERT(g_lp_stat.wakeup_timer_started == 0); if (esp_timer_start_once(g_btdm_slp_tmr, us_to_sleep - uncertainty) == ESP_OK) @@ -1898,20 +1660,20 @@ static void btdm_sleep_enter_phase2_wrapper(void) { if (g_lp_stat.phy_enabled) { - esp32s3_phy_disable(); - g_lp_stat.phy_enabled = false; + esp_phy_disable(); + g_lp_stat.phy_enabled = 0; } else { DEBUGPANIC(); } - if (!g_lp_stat.pm_lock_released) + if (g_lp_stat.pm_lock_released == 0) { #ifdef CONFIG_PM_ENABLE esp32s3_pm_lockrelease(); #endif - g_lp_stat.pm_lock_released = true; + g_lp_stat.pm_lock_released = 1; } } } @@ -1936,95 +1698,44 @@ static void btdm_sleep_exit_phase3_wrapper(void) if (g_lp_stat.pm_lock_released) { esp32s3_pm_lockacquire(); - g_lp_stat.pm_lock_released = false; + g_lp_stat.pm_lock_released = 0; } #endif if (btdm_controller_get_sleep_mode() == ESP_BT_SLEEP_MODE_1) { - if (!g_lp_stat.phy_enabled) + if (g_lp_stat.phy_enabled == 0) { - esp32s3_phy_enable(); - g_lp_stat.phy_enabled = true; + esp_phy_enable(); + g_lp_stat.phy_enabled = 1; } } if (g_lp_cntl.wakeup_timer_required && g_lp_stat.wakeup_timer_started) { esp_timer_stop(g_btdm_slp_tmr); - g_lp_stat.wakeup_timer_started = false; - } - - while (btdm_sleep_clock_sync()); -} - -/**************************************************************************** - * Name: btdm_sleep_exit_phase0 - * - * Description: - * Acquire PM lock and stop esp timer. - * - * Input Parameters: - * param - wakeup event - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR btdm_sleep_exit_phase0(void *param) -{ - DEBUGASSERT(g_lp_cntl.enable); - -#ifdef CONFIG_PM - if (g_lp_stat.pm_lock_released) - { - esp32s3_pm_lockacquire(); - g_lp_stat.pm_lock_released = false; - } -#endif - - int event = (int)param; - - if (event == BTDM_ASYNC_WAKEUP_SRC_VHCI || - event == BTDM_ASYNC_WAKEUP_SRC_DISA) - { - btdm_wakeup_request(); - } - - if (g_lp_cntl.wakeup_timer_required && g_lp_stat.wakeup_timer_started) - { - esp_timer_stop(g_btdm_slp_tmr); - g_lp_stat.wakeup_timer_started = false; + g_lp_stat.wakeup_timer_started = 0; } - if (event == BTDM_ASYNC_WAKEUP_SRC_VHCI || - event == BTDM_ASYNC_WAKEUP_SRC_DISA) - { - semphr_give_wrapper(g_wakeup_req_sem); - } + while (btdm_sleep_clock_sync()); } /**************************************************************************** - * Name: btdm_slp_tmr_callback + * Name: coex_wifi_sleep_set_hook * * Description: - * ESP-S3 BLE sleep callback function. + * Set Wi-Fi/BT coexistence sleep. * * Input Parameters: - * arg - Unused + * sleep - True to set sleep, false otherwise. * * Returned Value: * None * ****************************************************************************/ -static void IRAM_ATTR btdm_slp_tmr_callback(void *arg) +static void coex_wifi_sleep_set_hook(bool sleep) { -#ifdef CONFIG_PM - btdm_vnd_offload_post(BTDM_VND_OL_SIG_WAKEUP_TMR, - (void *)BTDM_ASYNC_WAKEUP_SRC_TMR); -#endif } /**************************************************************************** @@ -2073,102 +1784,407 @@ static void coex_schm_status_bit_clear_wrapper(uint32_t type, } /**************************************************************************** - * Name: esp32s3_vhci_host_check_send_available + * Name: interrupt_on_wrapper * * Description: - * Check if the host can send packet to controller or not. + * Enable Wi-Fi interrupt * * Input Parameters: - * None + * intr_num - The interrupt CPU number. * * Returned Value: - * bool - true or false + * None * ****************************************************************************/ -bool esp32s3_vhci_host_check_send_available(void) +static void interrupt_on_wrapper(int intr_num) { - if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) - { - return false; - } + int cpuint = intr_num; + int irq = esp32s3_getirq(0, cpuint); - return api_vhci_host_check_send_available(); + DEBUGVERIFY(esp32s3_irq_set_iram_isr(irq)); + + up_enable_irq(irq); } /**************************************************************************** - * Name: esp32s3_vhci_host_send_packet + * Name: interrupt_off_wrapper * * Description: - * Host send packet to controller. + * Disable Wi-Fi interrupt * * Input Parameters: - * data - the packet pointer - * len - the packet length + * intr_num - No mean * * Returned Value: * None * ****************************************************************************/ -void esp32s3_vhci_host_send_packet(uint8_t *data, uint16_t len) +static void interrupt_off_wrapper(int intr_num) { - if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) - { - return; - } - - api_vhci_host_send_packet(data, len); + up_disable_irq(intr_num + XTENSA_IRQ_FIRSTPERIPH); } /**************************************************************************** - * Name: esp32s3_vhci_register_callback + * Name: btdm_hw_mac_power_down_wrapper * * Description: - * Register the vhci reference callback. + * Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled * * Input Parameters: - * callback - struct defined by vhci_host_callback structure. + * none * * Returned Value: - * status - success or fail + * none * ****************************************************************************/ -int esp32s3_vhci_register_callback(const esp_vhci_host_callback_t *callback) +void IRAM_ATTR btdm_hw_mac_power_down_wrapper(void) { - int ret = ERROR; - if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) - { - return ret; - } +} - ret = api_vhci_host_register_callback( - (const vhci_host_callback_t *)callback) == 0 ? 0 : -1; - return ret; +/**************************************************************************** + * Name: btdm_hw_mac_power_up_wrapper + * + * Description: + * Power up MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled + * + * Input Parameters: + * none + * + * Returned Value: + * none + * + ****************************************************************************/ + +void IRAM_ATTR btdm_hw_mac_power_up_wrapper(void) +{ } /**************************************************************************** - * Name: btdm_controller_mem_init + * Name: btdm_backup_dma_copy_wrapper * * Description: - * Initialize BT controller to allocate task and other resource. + * Copy btdm backup DMA when PHY is disabled * * Input Parameters: + * none + * + * Returned Value: + * none + * + ****************************************************************************/ + +void IRAM_ATTR btdm_backup_dma_copy_wrapper(uint32_t reg, uint32_t mem_addr, + uint32_t num, bool to_mem) +{ +} + +/**************************************************************************** + * Other functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_task_create_pinned_to_core + * + * Description: + * Create task and bind it to target CPU, the task will run when it + * is created + * + * Input Parameters: + * entry - Task entry + * name - Task name + * stack_depth - Task stack size + * param - Task private data + * prio - Task priority + * task_handle - Task handle pointer which is used to pause, resume + * and delete the task + * core_id - CPU which the task runs in + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static int32_t esp_task_create_pinned_to_core(void *entry, + const char *name, + uint32_t stack_depth, + void *param, + uint32_t prio, + void *task_handle, + uint32_t core_id) +{ + int pid; +#ifdef CONFIG_SMP + int ret; + cpu_set_t cpuset; +#endif + + DEBUGASSERT(task_handle != NULL); + +#ifdef CONFIG_SMP + ret = sched_lock(); + if (ret) + { + wlerr("Failed to lock scheduler before creating pinned thread\n"); + return false; + } +#endif + + pid = kthread_create(name, prio, stack_depth, entry, + (char * const *)param); + if (pid > 0) + { + if (task_handle) + { + *((int *)task_handle) = pid; + } + +#ifdef CONFIG_SMP + if (core_id < CONFIG_SMP_NCPUS) + { + CPU_ZERO(&cpuset); + CPU_SET(core_id, &cpuset); + ret = nxsched_set_affinity(pid, sizeof(cpuset), &cpuset); + if (ret) + { + wlerr("Failed to set affinity error=%d\n", ret); + return false; + } + } +#endif + } + else + { + wlerr("Failed to create task, error %d\n", pid); + } + +#ifdef CONFIG_SMP + ret = sched_unlock(); + if (ret) + { + wlerr("Failed to unlock scheduler after creating pinned thread\n"); + return false; + } +#endif + + return pid > 0; +} + +/**************************************************************************** + * Name: esp_queue_send_generic + * + * Description: + * Generic send message to queue within a certain period of time + * + * Input Parameters: + * queue - Message queue data pointer + * item - Message data pointer + * ticks - Wait ticks + * prio - Message priority + * + * Returned Value: + * True if success or false if fail + * + ****************************************************************************/ + +static IRAM_ATTR int32_t esp_queue_send_generic(void *queue, void *item, + uint32_t ticks, int prio) +{ + int ret; + struct timespec timeout; + struct mq_adpt_s *mq_adpt = (struct mq_adpt_s *)queue; + +#ifdef CONFIG_ESP32S3_SPIFLASH + if (!spi_flash_cache_enabled()) + { + esp_send_queuecache(&g_esp_queuecache, item, mq_adpt->msgsize); + return esp_errno_trans(OK); + } +#endif + + if (ticks == OSI_FUNCS_TIME_BLOCKING || ticks == 0) + { + /* BLE interrupt function will call this adapter function to send + * message to message queue, so here we should call kernel API + * instead of application API + */ + + ret = file_mq_send(&mq_adpt->mq, (const char *)item, + mq_adpt->msgsize, prio); + if (ret < 0) + { + wlerr("Failed to send message to mqueue error=%d\n", ret); + } + } + else + { + ret = clock_gettime(CLOCK_REALTIME, &timeout); + if (ret < 0) + { + wlerr("Failed to get time %d\n", ret); + return esp_errno_trans(ret); + } + + if (ticks) + { + esp_update_time(&timeout, ticks); + } + + ret = file_mq_timedsend(&mq_adpt->mq, (const char *)item, + mq_adpt->msgsize, prio, &timeout); + if (ret < 0) + { + wlerr("Failed to timedsend message to mqueue error=%d\n", ret); + } + } + + return esp_errno_trans(ret); +} + +/**************************************************************************** + * Name: esp_update_time + * + * Description: + * Transform ticks to time and add this time to timespec value + * + * Input Parameters: + * ticks - System ticks + * + * Output Parameters: + * timespec - Input timespec data pointer + * + * Returned Value: * None * + ****************************************************************************/ + +static void esp_update_time(struct timespec *timespec, uint32_t ticks) +{ + uint32_t tmp; + + tmp = TICK2SEC(ticks); + timespec->tv_sec += tmp; + + ticks -= SEC2TICK(tmp); + tmp = TICK2NSEC(ticks); + + timespec->tv_nsec += tmp; +} + +/**************************************************************************** + * Name: btdm_slp_tmr_callback + * + * Description: + * ESP-S3 BLE sleep callback function. + * + * Input Parameters: + * arg - Unused + * * Returned Value: * None * ****************************************************************************/ -static void btdm_controller_mem_init(void) +static void IRAM_ATTR btdm_slp_tmr_callback(void *arg) { - extern void btdm_controller_rom_data_init(void); - btdm_controller_rom_data_init(); +#ifdef CONFIG_PM + btdm_vnd_offload_post(BTDM_VND_OL_SIG_WAKEUP_TMR, + (void *)BTDM_ASYNC_WAKEUP_SRC_TMR); +#endif +} + +/**************************************************************************** + * Name: esp_int_adpt_cb + * + * Description: + * BT interrupt adapter callback function + * + * Input Parameters: + * arg - interrupt adapter private data + * + * Returned Value: + * NuttX error code + * + ****************************************************************************/ + +static int IRAM_ATTR esp_int_adpt_cb(int irq, void *context, void *arg) +{ + struct irq_adpt_s *adapter = (struct irq_adpt_s *)arg; + + adapter->func(adapter->arg); + + return OK; +} + +/**************************************************************************** + * Name: btdm_sleep_exit_phase0 + * + * Description: + * Acquire PM lock and stop esp timer. + * + * Input Parameters: + * param - wakeup event + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR btdm_sleep_exit_phase0(void *param) +{ + DEBUGASSERT(g_lp_cntl.enable); + +#ifdef CONFIG_PM + if (g_lp_stat.pm_lock_released) + { + esp32s3_pm_lockacquire(); + g_lp_stat.pm_lock_released = 0; + } +#endif + + int event = (int)param; + + if (event == BTDM_ASYNC_WAKEUP_SRC_VHCI || + event == BTDM_ASYNC_WAKEUP_SRC_DISA) + { + btdm_wakeup_request(); + } + + if (g_lp_cntl.wakeup_timer_required && g_lp_stat.wakeup_timer_started) + { + esp_timer_stop(g_btdm_slp_tmr); + g_lp_stat.wakeup_timer_started = 0; + } + + if (event == BTDM_ASYNC_WAKEUP_SRC_VHCI || + event == BTDM_ASYNC_WAKEUP_SRC_DISA) + { + semphr_give_wrapper(g_wakeup_req_sem); + } } #if CONFIG_MAC_BB_PD + +/**************************************************************************** + * Name: btdm_mac_bb_power_down_cb + * + * Description: + * This function is a callback that powers down the MAC and baseband (BB) + * of the Bluetooth module. It first checks if the power down control for + * the MAC and BB is enabled and if they are not already powered down. If + * these conditions are met, it powers down the DMA and sets the MAC and BB + * as powered down. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + static void IRAM_ATTR btdm_mac_bb_power_down_cb(void) { if (g_lp_cntl.mac_bb_pd && g_lp_stat.mac_bb_pd == 0) @@ -2178,6 +2194,24 @@ static void IRAM_ATTR btdm_mac_bb_power_down_cb(void) } } +/**************************************************************************** + * Name: btdm_mac_bb_power_up_cb + * + * Description: + * This function is a callback that powers up the MAC and baseband (BB) + * of the Bluetooth module. It first checks if the power down control for + * the MAC and BB is enabled and if they are currently powered down. If + * these conditions are met, it powers up the DMA and sets the MAC and BB + * as powered up. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + static void IRAM_ATTR btdm_mac_bb_power_up_cb(void) { if (g_lp_cntl.mac_bb_pd && g_lp_stat.mac_bb_pd) @@ -2186,24 +2220,209 @@ static void IRAM_ATTR btdm_mac_bb_power_up_cb(void) g_lp_stat.mac_bb_pd = 0; } } -#endif +#endif + +/**************************************************************************** + * Name: btdm_controller_mem_init + * + * Description: + * Initialize BT controller to allocate task and other resource. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void btdm_controller_mem_init(void) +{ + extern void btdm_controller_rom_data_init(void); + btdm_controller_rom_data_init(); +} + +/**************************************************************************** + * Name: bt_controller_deinit_internal + * + * Description: + * Deinit BT internal controller. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void bt_controller_deinit_internal(void) +{ + periph_module_disable(PERIPH_BT_MODULE); + + if (g_lp_stat.phy_enabled) + { + esp_phy_disable(); + g_lp_stat.phy_enabled = 0; + } + + /* deinit low power control resources */ + +#if CONFIG_MAC_BB_PD + if (g_lp_cntl.mac_bb_pd) + { + btdm_deep_sleep_mem_deinit(); + g_lp_cntl.mac_bb_pd = 0; + } +#endif + +#ifdef CONFIG_PM + g_lp_stat.pm_lock_released = 0; +#endif + + if (g_lp_cntl.wakeup_timer_required) + { + if (g_lp_stat.wakeup_timer_started) + { + esp_timer_stop(g_btdm_slp_tmr); + } + + g_lp_stat.wakeup_timer_started = 0; + esp_timer_delete(g_btdm_slp_tmr); + g_btdm_slp_tmr = NULL; + } + + if (g_lp_cntl.enable) + { + btdm_vnd_offload_task_deregister(BTDM_VND_OL_SIG_WAKEUP_TMR); + if (g_wakeup_req_sem != NULL) + { + semphr_delete_wrapper(g_wakeup_req_sem); + g_wakeup_req_sem = NULL; + } + } + + if (g_lp_cntl.lpclk_sel == BTDM_LPCLK_SEL_XTAL) + { +#ifdef CONFIG_BT_CTRL_MAIN_XTAL_PU_DURING_LIGHT_SLEEP + if (g_lp_cntl.main_xtal_pu) + { + esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_OFF); + g_lp_cntl.main_xtal_pu = 0; + } +#endif + + btdm_lpclk_select_src(BTDM_LPCLK_SEL_RTC_SLOW); + btdm_lpclk_set_div(0); +#if CONFIG_ESP32S3_WIFI_BT_COEXIST + coex_update_lpclk_interval(); +#endif + } + + g_btdm_lpcycle_us = 0; + +#if CONFIG_MAC_BB_PD + esp_unregister_mac_bb_pd_callback(btdm_mac_bb_power_down_cb); + esp_unregister_mac_bb_pu_callback(btdm_mac_bb_power_up_cb); +#endif + + esp_bt_power_domain_off(); +#if CONFIG_MAC_BB_PD + esp_mac_bb_pd_mem_deinit(); +#endif + esp_phy_modem_deinit(); + + if (osi_funcs_p != NULL) + { + kmm_free(osi_funcs_p); + osi_funcs_p = NULL; + } + + g_btdm_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE; +} + +/**************************************************************************** + * Name: async_wakeup_request + * + * Description: + * Request the BLE Controller to wakeup + * + * Input Parameters: + * event - the event that triggered the wakeup + * + * Returned Value: + * true if request lock is needed, false otherwise + * + ****************************************************************************/ + +static bool async_wakeup_request(int event) +{ + bool do_wakeup_request = false; + + if (g_lp_cntl.enable == 0) + { + return false; + } + + switch (event) + { + case BTDM_ASYNC_WAKEUP_SRC_VHCI: + case BTDM_ASYNC_WAKEUP_SRC_DISA: + btdm_in_wakeup_requesting_set(true); + + if (btdm_power_state_active() == false) + { + r_btdm_vnd_offload_post(BTDM_VND_OL_SIG_WAKEUP_TMR, + (void *)event); + do_wakeup_request = true; + semphr_take_wrapper(g_wakeup_req_sem, OSI_FUNCS_TIME_BLOCKING); + } + break; + default: + return false; + } + + return do_wakeup_request; +} /**************************************************************************** - * Name: coex_wifi_sleep_set_hook + * Name: async_wakeup_request_end * * Description: - * Set Wi-Fi/BT coexistence sleep. + * Finish a wakeup request * * Input Parameters: - * sleep - True to set sleep, false otherwise. + * event - the event that triggered the wakeup * * Returned Value: - * None + * true if request lock is needed, false otherwise * ****************************************************************************/ -static void coex_wifi_sleep_set_hook(bool sleep) +static void async_wakeup_request_end(int event) { + bool allow_to_sleep; + + if (g_lp_cntl.enable == 0) + { + return; + } + + switch (event) + { + case BTDM_ASYNC_WAKEUP_SRC_VHCI: + case BTDM_ASYNC_WAKEUP_SRC_DISA: + allow_to_sleep = true; + break; + default: + allow_to_sleep = true; + break; + } + + if (allow_to_sleep) + { + btdm_in_wakeup_requesting_set(false); + } } /**************************************************************************** @@ -2232,16 +2451,17 @@ int esp32s3_bt_controller_init(void) bool select_src_ret; bool set_div_ret; int i; + int err; - sq_init(&g_int_flags_free); - sq_init(&g_int_flags_used); + sq_init(&g_ble_int_flags_free); + sq_init(&g_ble_int_flags_used); for (i = 0; i < NR_IRQSTATE_FLAGS; i++) { - sq_addlast((sq_entry_t *)&g_int_flags[i], &g_int_flags_free); + sq_addlast((sq_entry_t *)&g_ble_int_flags[i], &g_ble_int_flags_free); } - if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) + if (g_btdm_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) { wlerr("Invalid controller status"); return ERROR; @@ -2249,7 +2469,7 @@ int esp32s3_bt_controller_init(void) if (cfg == NULL) { - return ESP_ERR_INVALID_ARG; + return -EINVAL; } if (cfg->controller_task_prio != ESP_TASK_BT_CONTROLLER_PRIO || @@ -2289,10 +2509,30 @@ int esp32s3_bt_controller_init(void) cfg->controller_task_run_cpu = CONFIG_BT_CTRL_PINNED_TO_CORE; cfg->magic = ESP_BT_CTRL_CONFIG_MAGIC_VAL; +#if CONFIG_MAC_BB_PD + esp_mac_bb_pd_mem_init(); +#endif + + esp_phy_modem_init(); + esp_bt_power_domain_on(); btdm_controller_mem_init(); +#if CONFIG_MAC_BB_PD + if (esp_register_mac_bb_pd_callback(btdm_mac_bb_power_down_cb) != 0) + { + err = -EINVAL; + goto error; + } + + if (esp_register_mac_bb_pu_callback(btdm_mac_bb_power_up_cb) != 0) + { + err = -EINVAL; + goto error; + } +#endif + osi_funcs_p = kmm_malloc(sizeof(struct osi_funcs_s)); if (osi_funcs_p == NULL) { @@ -2300,7 +2540,6 @@ int esp32s3_bt_controller_init(void) } memcpy(osi_funcs_p, &g_osi_funcs, sizeof(struct osi_funcs_s)); - if (btdm_osi_funcs_register(osi_funcs_p) != 0) { wlerr("Error, probably invalid OSI Functions\n"); @@ -2331,6 +2570,7 @@ int esp32s3_bt_controller_init(void) #if CONFIG_MAC_BB_PD if (!btdm_deep_sleep_mem_init()) { + err = -ENOMEM; goto error; } @@ -2367,6 +2607,8 @@ int esp32s3_bt_controller_init(void) } } + /* set default bluetooth sleep clock cycle and its fractional bits */ + g_btdm_lpcycle_us_frac = RTC_CLK_CAL_FRACT; g_btdm_lpcycle_us = 2 << (g_btdm_lpcycle_us_frac); @@ -2375,7 +2617,9 @@ int esp32s3_bt_controller_init(void) g_lp_cntl.lpclk_sel = BTDM_LPCLK_SEL_XTAL; /* set default value */ #if CONFIG_BT_CTRL_LPCLK_SEL_EXT_32K_XTAL - if (esp32s3_rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_32K_XTAL) + /* check whether or not EXT_CRYS is working */ + + if (esp32s3_rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_32K_XTAL) /* External 32 kHz XTAL */ { g_lp_cntl.lpclk_sel = BTDM_LPCLK_SEL_XTAL32K; } @@ -2383,7 +2627,7 @@ int esp32s3_bt_controller_init(void) { wlwarn("32.768kHz XTAL not detected"); #if !CONFIG_BT_CTRL_MAIN_XTAL_PU_DURING_LIGHT_SLEEP - g_lp_cntl.lpclk_sel = BTDM_LPCLK_SEL_XTAL; + g_lp_cntl.no_light_sleep = 1; #endif } #elif (CONFIG_BT_CTRL_LPCLK_SEL_MAIN_XTAL) @@ -2413,7 +2657,8 @@ int esp32s3_bt_controller_init(void) { uint32_t rtc_clk_xtal_freq = 0; #ifdef CONFIG_BT_CTRL_MAIN_XTAL_PU_DURING_LIGHT_SLEEP - s_lp_cntl.main_xtal_pu = 1; + ASSERT(esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON)); + g_lp_cntl.main_xtal_pu = 1; #endif select_src_ret = btdm_lpclk_select_src(BTDM_LPCLK_SEL_XTAL); rtc_clk_xtal_freq = esp32s3_rtc_clk_xtal_freq_get(); @@ -2443,6 +2688,8 @@ int esp32s3_bt_controller_init(void) } else { + UNUSED(select_src_ret); + UNUSED(set_div_ret); goto error; } @@ -2460,22 +2707,22 @@ int esp32s3_bt_controller_init(void) coex_init(); #endif - esp32s3_periph_module_enable(PERIPH_BT_MODULE); - esp32s3_periph_module_reset(PERIPH_BT_MODULE); + periph_module_enable(PERIPH_BT_MODULE); + periph_module_reset(PERIPH_BT_MODULE); - esp32s3_phy_enable(); - g_lp_stat.phy_enabled = true; + esp_phy_enable(); + g_lp_stat.phy_enabled = 1; if (btdm_controller_init(cfg) != 0) { - esp32s3_phy_disable(); - g_lp_stat.phy_enabled = false; + esp_phy_disable(); + g_lp_stat.phy_enabled = 0; return -EIO; } coex_pti_v2(); - btdm_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; + g_btdm_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; #ifdef CONFIG_ESP32S3_SPIFLASH if (esp_wireless_init() != OK) @@ -2488,7 +2735,7 @@ int esp32s3_bt_controller_init(void) error: - esp32s3_bt_controller_deinit_internal (); + bt_controller_deinit_internal (); return -ENOMEM; } @@ -2509,128 +2756,106 @@ int esp32s3_bt_controller_init(void) int esp32s3_bt_controller_deinit(void) { - if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_INITED) + if (g_btdm_controller_status != ESP_BT_CONTROLLER_STATUS_INITED) { return ERROR; } btdm_controller_deinit(); - esp32s3_bt_controller_deinit_internal(); + bt_controller_deinit_internal(); return OK; } /**************************************************************************** - * Name: esp32s3_bt_controller_deinit_internal + * Name: esp32s3_bt_controller_enable * * Description: - * Deinit BT internal controller. + * Enable BT controller. * * Input Parameters: - * None + * mode - the mode(BLE/BT/BTDM) to enable. For compatible of API, retain + * this argument. This mode must be equal as the mode in "cfg" of + * esp_bt_controller_init(). * * Returned Value: - * None + * Zero (OK) is returned on success. A negated errno value is returned + * on failure. * ****************************************************************************/ -static void esp32s3_bt_controller_deinit_internal(void) +int esp32s3_bt_controller_enable(esp_bt_mode_t mode) { - esp32s3_periph_module_disable(PERIPH_BT_MODULE); + int ret = OK; - if (g_lp_stat.phy_enabled) + if (g_btdm_controller_status != ESP_BT_CONTROLLER_STATUS_INITED) { - esp32s3_phy_disable(); - g_lp_stat.phy_enabled = 0; + return ERROR; } - /* deinit low power control resources */ - -#if CONFIG_MAC_BB_PD - if (g_lp_cntl.mac_bb_pd) + if (mode != btdm_controller_get_mode()) { - btdm_deep_sleep_mem_deinit(); - g_lp_cntl.mac_bb_pd = 0; + wlerr("invalid mode %d, controller support mode is %d", + mode, btdm_controller_get_mode()); + return ERROR; } + +#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST + coex_enable(); #endif #ifdef CONFIG_PM + /* enable low power mode */ + if (g_lp_cntl.no_light_sleep) { - if (g_light_sleep_pm_lock != NULL) - { - esp_pm_lock_delete(g_light_sleep_pm_lock); - g_light_sleep_pm_lock = NULL; - } + esp32s3_pm_lockacquire(); } - if (g_pm_lock != NULL) - { - esp_pm_lock_delete(g_pm_lock); - g_pm_lock = NULL; - g_lp_stat.pm_lock_released = 0; - } + esp32s3_pm_lockacquire(); + g_lp_stat.pm_lock_released = 0; #endif - if (g_lp_cntl.wakeup_timer_required) + if (g_lp_cntl.enable) { - if (g_lp_stat.wakeup_timer_started) - { - esp_timer_stop(g_btdm_slp_tmr); - } - - g_lp_stat.wakeup_timer_started = 0; - esp_timer_delete(g_btdm_slp_tmr); - g_btdm_slp_tmr = NULL; + btdm_controller_enable_sleep(true); } - if (g_lp_cntl.enable) + if (btdm_controller_enable(mode) != 0) { - btdm_vnd_offload_task_deregister(BTDM_VND_OL_SIG_WAKEUP_TMR); - if (g_wakeup_req_sem != NULL) - { - semphr_delete_wrapper(g_wakeup_req_sem); - g_wakeup_req_sem = NULL; - } + ret = ERROR; + goto error; } - if (g_lp_cntl.lpclk_sel == BTDM_LPCLK_SEL_XTAL) - { -#ifdef CONFIG_BT_CTRL_MAIN_XTAL_PU_DURING_LIGHT_SLEEP - if (g_lp_cntl.main_xtal_pu) - { - esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_OFF); - g_lp_cntl.main_xtal_pu = 0; - } -#endif + g_btdm_controller_status = ESP_BT_CONTROLLER_STATUS_ENABLED; - btdm_lpclk_select_src(BTDM_LPCLK_SEL_RTC_SLOW); - btdm_lpclk_set_div(0); -#if CONFIG_ESP32S3_WIFI_BT_COEXIST - coex_update_lpclk_interval(); -#endif - } + return ret; - g_btdm_lpcycle_us = 0; +error: -#if CONFIG_MAC_BB_PD - esp_unregister_mac_bb_pd_callback(btdm_mac_bb_power_down_cb); - esp_unregister_mac_bb_pu_callback(btdm_mac_bb_power_up_cb); -#endif + /* disable low power mode */ - esp_bt_power_domain_off(); -#if CONFIG_MAC_BB_PD - esp_mac_bb_pd_mem_deinit(); -#endif + btdm_controller_enable_sleep(false); - if (osi_funcs_p != NULL) +#ifdef CONFIG_PM + if (g_lp_cntl.no_light_sleep) { - kmm_free(osi_funcs_p); - osi_funcs_p = NULL; + esp32s3_pm_lockrelease(); + } + + if (g_lp_stat.pm_lock_released == 0) + { + esp32s3_pm_lockrelease(); + g_lp_stat.pm_lock_released = 1; } +#endif + +#if CONFIG_ESP32S3_WIFI_BT_COEXIST + coex_disable(); +#endif - btdm_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE; + return ret; } /**************************************************************************** @@ -2650,11 +2875,12 @@ static void esp32s3_bt_controller_deinit_internal(void) int esp32s3_bt_controller_disable(void) { - if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) + if (g_btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) { return ERROR; } + async_wakeup_request(BTDM_ASYNC_WAKEUP_SRC_DISA); while (!btdm_power_state_active()) { nxsig_usleep(1000); /* wait */ @@ -2662,19 +2888,26 @@ int esp32s3_bt_controller_disable(void) btdm_controller_disable(); + async_wakeup_request_end(BTDM_ASYNC_WAKEUP_SRC_DISA); + #ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST coex_disable(); #endif - btdm_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; + g_btdm_controller_status = ESP_BT_CONTROLLER_STATUS_INITED; #ifdef CONFIG_PM /* disable low power mode */ - if (!g_lp_stat.pm_lock_released) + if (g_lp_cntl.no_light_sleep) + { + esp_pm_lock_release(s_light_sleep_pm_lock); + } + + if (g_lp_stat.pm_lock_released == 0) { esp32s3_pm_lockrelease(); - g_lp_stat.pm_lock_released = true; + g_lp_stat.pm_lock_released = 1; } else { @@ -2686,100 +2919,100 @@ int esp32s3_bt_controller_disable(void) } /**************************************************************************** - * Name: esp32s3_bt_controller_enable + * Name: esp32s3_bt_controller_get_status * * Description: - * Enable BT controller. + * Returns the status of the BT Controller * * Input Parameters: - * mode - the mode(BLE/BT/BTDM) to enable. For compatible of API, retain - * this argument. This mode must be equal as the mode in "cfg" of - * esp_bt_controller_init(). + * None * * Returned Value: - * Zero (OK) is returned on success. A negated errno value is returned - * on failure. + * The current status (type esp_bt_controller_status_t) * ****************************************************************************/ -int esp32s3_bt_controller_enable(esp_bt_mode_t mode) +esp_bt_controller_status_t esp32s3_bt_controller_get_status(void) { - int ret = OK; + return g_btdm_controller_status; +} - if (btdm_controller_status != ESP_BT_CONTROLLER_STATUS_INITED) - { - return ERROR; - } +/**************************************************************************** + * Name: esp32s3_vhci_host_check_send_available + * + * Description: + * Check if the host can send packet to controller or not. + * + * Input Parameters: + * None + * + * Returned Value: + * bool - true or false + * + ****************************************************************************/ - if (mode != btdm_controller_get_mode()) +bool esp32s3_vhci_host_check_send_available(void) +{ + if (g_btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) { - wlerr("invalid mode %d, controller support mode is %d", - mode, btdm_controller_get_mode()); - return ERROR; + return false; } -#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST - coex_enable(); -#endif - -#ifdef CONFIG_PM - /* enable low power mode */ - - esp32s3_pm_lockacquire(); - g_lp_stat.pm_lock_released = false; -#endif + return api_vhci_host_check_send_available(); +} - if (g_lp_cntl.enable) - { - btdm_controller_enable_sleep(true); - } +/**************************************************************************** + * Name: esp32s3_vhci_host_send_packet + * + * Description: + * Host send packet to controller. + * + * Input Parameters: + * data - the packet pointer + * len - the packet length + * + * Returned Value: + * None + * + ****************************************************************************/ - if (btdm_controller_enable(mode) != 0) +void esp32s3_vhci_host_send_packet(uint8_t *data, uint16_t len) +{ + if (g_btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) { - ret = ERROR; - goto error; + return; } - btdm_controller_status = ESP_BT_CONTROLLER_STATUS_ENABLED; - - return ret; - -error: - - /* disable low power mode */ - - btdm_controller_enable_sleep(false); - -#ifdef CONFIG_PM - if (!g_lp_stat.pm_lock_released) - { - esp32s3_pm_lockrelease(); - g_lp_stat.pm_lock_released = true; - } -#endif + async_wakeup_request(BTDM_ASYNC_WAKEUP_SRC_VHCI); -#if CONFIG_ESP32S3_WIFI_BT_COEXIST - coex_disable(); -#endif + api_vhci_host_send_packet(data, len); - return ret; + async_wakeup_request_end(BTDM_ASYNC_WAKEUP_SRC_VHCI); } /**************************************************************************** - * Name: esp32s3_bt_controller_get_status + * Name: esp32s3_vhci_register_callback * * Description: - * Returns the status of the BT Controller + * Register the vhci reference callback. * * Input Parameters: - * None + * callback - struct defined by vhci_host_callback structure. * * Returned Value: - * The current status (type esp_bt_controller_status_t) + * status - success or fail * ****************************************************************************/ -esp_bt_controller_status_t esp32s3_bt_controller_get_status(void) +int esp32s3_vhci_register_callback(const esp_vhci_host_callback_t *callback) { - return btdm_controller_status; + int ret = ERROR; + if (g_btdm_controller_status != ESP_BT_CONTROLLER_STATUS_ENABLED) + { + return ret; + } + + ret = api_vhci_host_register_callback( + (const vhci_host_callback_t *)callback) == 0 ? 0 : -1; + return ret; } diff --git a/arch/xtensa/src/esp32s3/esp32s3_clockconfig.c b/arch/xtensa/src/esp32s3/esp32s3_clockconfig.c index 787a4064854b8..0ff404b25a93f 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_clockconfig.c +++ b/arch/xtensa/src/esp32s3/esp32s3_clockconfig.c @@ -28,7 +28,7 @@ #include #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "hardware/esp32s3_soc.h" #include "hardware/esp32s3_uart.h" #include "hardware/esp32s3_system.h" diff --git a/arch/xtensa/src/esp32s3/esp32s3_dma.c b/arch/xtensa/src/esp32s3/esp32s3_dma.c index 203ba7f1301c7..c786d4945d6a6 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_dma.c +++ b/arch/xtensa/src/esp32s3/esp32s3_dma.c @@ -52,6 +52,9 @@ # define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) #endif +#define DMA_INVALID_PERIPH_ID (0x3F) +#define GDMA_CH_REG_ADDR(_r, _ch) ((_r) + (_ch) * GDMA_REG_OFFSET) + /**************************************************************************** * Private Data ****************************************************************************/ @@ -166,6 +169,55 @@ int32_t esp32s3_dma_request(enum esp32s3_dma_periph_e periph, return chan; } +/**************************************************************************** + * Name: esp32s3_dma_release + * + * Description: + * Release DMA channel from peripheral. + * + * Input Parameters: + * chan - Peripheral for which the DMA channel request was made + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32s3_dma_release(int chan) +{ + DEBUGASSERT(chan < ESP32S3_DMA_CHAN_MAX); + + nxmutex_lock(&g_dma_lock); + + /* Disconnect DMA TX channel from peripheral */ + + SET_GDMA_CH_REG(DMA_OUT_PERI_SEL_CH0_REG, chan, DMA_INVALID_PERIPH_ID); + + /* Disconnect DMA RX channel from peripheral */ + + SET_GDMA_CH_REG(DMA_IN_PERI_SEL_CH0_REG, chan, DMA_INVALID_PERIPH_ID); + CLR_GDMA_CH_BITS(DMA_IN_CONF0_CH0_REG, chan, DMA_MEM_TRANS_EN_CH0_M); + + /* Disable DMA TX/RX channels burst sending data */ + + CLR_GDMA_CH_BITS(DMA_OUT_CONF0_CH0_REG, chan, DMA_OUT_DATA_BURST_EN_CH0_M); + CLR_GDMA_CH_BITS(DMA_IN_CONF0_CH0_REG, chan, DMA_IN_DATA_BURST_EN_CH0_M); + + /* Disable DMA TX/RX channels burst reading descriptor link */ + + CLR_GDMA_CH_BITS(DMA_OUT_CONF0_CH0_REG, chan, DMA_OUTDSCR_BURST_EN_CH0_M); + CLR_GDMA_CH_BITS(DMA_IN_CONF0_CH0_REG, chan, DMA_INDSCR_BURST_EN_CH0_M); + + /* Reset the priority to 0 (lowest) */ + + SET_GDMA_CH_REG(DMA_OUT_PRI_CH0_REG, chan, 0); + SET_GDMA_CH_REG(DMA_IN_PRI_CH0_REG, chan, 0); + + g_dma_chan_used[chan] = false; + + nxmutex_unlock(&g_dma_lock); +} + /**************************************************************************** * Name: esp32s3_dma_setup * @@ -179,6 +231,7 @@ int32_t esp32s3_dma_request(enum esp32s3_dma_periph_e periph, * pbuf - RX/TX buffer pointer * len - RX/TX buffer length * tx - true: TX mode (transmitter); false: RX mode (receiver) + * chan - DMA channel of the receiver/transmitter * * Returned Value: * Bound pbuf data bytes @@ -186,7 +239,7 @@ int32_t esp32s3_dma_request(enum esp32s3_dma_periph_e periph, ****************************************************************************/ uint32_t esp32s3_dma_setup(struct esp32s3_dmadesc_s *dmadesc, uint32_t num, - uint8_t *pbuf, uint32_t len, bool tx) + uint8_t *pbuf, uint32_t len, bool tx, int chan) { int i; uint32_t regval; @@ -194,19 +247,59 @@ uint32_t esp32s3_dma_setup(struct esp32s3_dmadesc_s *dmadesc, uint32_t num, uint8_t *pdata = pbuf; uint32_t data_len; uint32_t buf_len; + int alignment = 4; + int dma_size = ESP32S3_DMA_BUFFER_MAX_SIZE; + bool buffer_in_psram = esp32s3_ptr_extram(pdata); + int block_size_index = 0; + uint32_t addr = GDMA_CH_REG_ADDR(DMA_IN_CONF0_CH0_REG, chan); + bool burst_en = REG_GET_FIELD(addr, DMA_IN_DATA_BURST_EN_CH0); DEBUGASSERT(dmadesc != NULL); DEBUGASSERT(num > 0); DEBUGASSERT(pbuf != NULL); DEBUGASSERT(len > 0); + DEBUGASSERT(chan >= 0 && chan < ESP32S3_DMA_CHAN_MAX); - for (i = 0; i < num; i++) + if (!tx && buffer_in_psram) + { + addr = GDMA_CH_REG_ADDR(DMA_IN_CONF1_CH0_REG, chan); + block_size_index = REG_GET_FIELD(addr, DMA_IN_EXT_MEM_BK_SIZE_CH0); + switch (block_size_index) + { + case ESP32S3_DMA_EXT_MEMBLK_64B: + alignment = 64; + break; + + case ESP32S3_DMA_EXT_MEMBLK_32B: + alignment = 32; + break; + + case ESP32S3_DMA_EXT_MEMBLK_16B: + default: + alignment = 16; + break; + } + + dma_size = 0x1000 - alignment; + } + else if(!tx && burst_en) { - data_len = MIN(bytes, ESP32S3_DMA_BUFLEN_MAX); + dma_size = ESP32S3_DMA_BUFLEN_MAX_4B_ALIGNED; + } - /* Buffer length must be rounded to next 32-bit boundary. */ + for (i = 0; i < num; i++) + { + data_len = MIN(bytes, dma_size); + if (!tx && (burst_en || buffer_in_psram)) + { + /* Buffer length must be rounded to next alignment boundary. */ - buf_len = ALIGN_UP(data_len, sizeof(uintptr_t)); + buf_len = ALIGN_UP(data_len, alignment); + } + else + { + buf_len = data_len; + } dmadesc[i].ctrl = ESP32S3_DMA_CTRL_OWN; @@ -463,3 +556,39 @@ void esp32s3_dma_init(void) nxmutex_unlock(&g_dma_lock); } +/**************************************************************************** + * Name: esp32s3_dma_deinit + * + * Description: + * Deinitialize DMA driver. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32s3_dma_deinit(void) +{ + nxmutex_lock(&g_dma_lock); + + g_dma_ref--; + + if (!g_dma_ref) + { + /* Disable DMA clock gating */ + + modifyreg32(DMA_MISC_CONF_REG, DMA_CLK_EN_M, 0); + + /* Disable DMA module by gating the clock and asserting the reset + * signal. + */ + + modifyreg32(SYSTEM_PERIP_CLK_EN1_REG, SYSTEM_DMA_CLK_EN_M, 0); + modifyreg32(SYSTEM_PERIP_RST_EN1_REG, 0, SYSTEM_DMA_RST_M); + } + + nxmutex_unlock(&g_dma_lock); +} diff --git a/arch/xtensa/src/esp32s3/esp32s3_dma.h b/arch/xtensa/src/esp32s3/esp32s3_dma.h index db2c91899d7a5..29427d4f14812 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_dma.h +++ b/arch/xtensa/src/esp32s3/esp32s3_dma.h @@ -54,17 +54,21 @@ extern "C" #define SET_GDMA_CH_BITS(_r, _ch, _b) modifyreg32((_r) + (_ch) * GDMA_REG_OFFSET, 0, (_b)) #define CLR_GDMA_CH_BITS(_r, _ch, _b) modifyreg32((_r) + (_ch) * GDMA_REG_OFFSET, (_b), 0) -/* DMA max data length */ +/* Maximum size of the buffer that can be attached to DMA descriptor */ -#define ESP32S3_DMA_DATALEN_MAX (0x1000 - 4) +#define ESP32S3_DMA_BUFFER_MAX_SIZE (0x1000 - 1) + +/* DMA max data length, and aligned to 4Bytes */ + +#define ESP32S3_DMA_BUFLEN_MAX_4B_ALIGNED (0x1000 - 4) /* DMA max buffer length */ -#define ESP32S3_DMA_BUFLEN_MAX ESP32S3_DMA_DATALEN_MAX +#define ESP32S3_DMA_BUFLEN_MAX ESP32S3_DMA_BUFFER_MAX_SIZE /* DMA channel number */ -#define ESP32S3_DMA_CHAN_MAX (3) +#define ESP32S3_DMA_CHAN_MAX (5) /* DMA RX MAX priority */ @@ -145,6 +149,22 @@ int32_t esp32s3_dma_request(enum esp32s3_dma_periph_e periph, uint32_t rx_prio, bool burst_en); +/**************************************************************************** + * Name: esp32s3_dma_release + * + * Description: + * Release DMA channel from peripheral. + * + * Input Parameters: + * chan - Peripheral for which the DMA channel request was made + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32s3_dma_release(int chan); + /**************************************************************************** * Name: esp32s3_dma_setup * @@ -158,6 +178,7 @@ int32_t esp32s3_dma_request(enum esp32s3_dma_periph_e periph, * pbuf - RX/TX buffer pointer * len - RX/TX buffer length * tx - true: TX mode (transmitter); false: RX mode (receiver) + * chan - DMA channel of the receiver/transmitter * * Returned Value: * Bound pbuf data bytes @@ -165,7 +186,7 @@ int32_t esp32s3_dma_request(enum esp32s3_dma_periph_e periph, ****************************************************************************/ uint32_t esp32s3_dma_setup(struct esp32s3_dmadesc_s *dmadesc, uint32_t num, - uint8_t *pbuf, uint32_t len, bool tx); + uint8_t *pbuf, uint32_t len, bool tx, int chan); /**************************************************************************** * Name: esp32s3_dma_load @@ -272,6 +293,22 @@ void esp32s3_dma_set_ext_memblk(int chan, bool tx, void esp32s3_dma_init(void); +/**************************************************************************** + * Name: esp32s3_dma_deinit + * + * Description: + * Deinitialize DMA driver. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32s3_dma_deinit(void); + #ifdef __cplusplus } #endif diff --git a/arch/xtensa/src/esp32s3/esp32s3_efuse.c b/arch/xtensa/src/esp32s3/esp32s3_efuse.c index fe138056cdec8..b843e8ca01763 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_efuse.c +++ b/arch/xtensa/src/esp32s3/esp32s3_efuse.c @@ -440,51 +440,6 @@ static int esp32s3_efuse_process(const efuse_desc_t *field[], void *ptr, return err; } -/**************************************************************************** - * Name: esp32s3_efuse_write_reg - * - * Description: - * Write value to efuse register. - * - * Input Parameters: - * blk - Block number of eFuse - * num_reg - The register number in the block - * value - Value to write - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void esp32s3_efuse_write_reg(uint32_t blk, uint32_t num_reg, - uint32_t value) -{ - uint32_t addr_wr_reg; - uint32_t reg_to_write; - uint32_t blk_start = g_start_efuse_wrreg[blk]; - - DEBUGASSERT(blk >= 0 && blk < EFUSE_BLK_MAX); - - DEBUGASSERT(num_reg <= 7); - - /* The block 0 and register 7 doesn't exist */ - - if (blk == 0 && num_reg == 7) - { - merr("Block 0 Register 7 doesn't exist!\n"); - return; - } - - addr_wr_reg = blk_start + num_reg * 4; - reg_to_write = getreg32(addr_wr_reg) | value; - - /* The register can be written in parts so we combine the new value - * with the one already available. - */ - - putreg32(reg_to_write, addr_wr_reg); -} - /**************************************************************************** * Name: esp32s3_efuse_write_blob * @@ -518,33 +473,6 @@ static int esp32s3_efuse_write_blob(uint32_t num_reg, int bit_offset, return OK; } -/**************************************************************************** - * Name: esp32s3_efuse_read_reg - * - * Description: - * Read efuse register. - * - * Input Parameters: - * blk - Block number of eFuse - * num_reg - The register number in the block - * - * Returned Value: - * Return the value in the efuse register. - * - ****************************************************************************/ - -static uint32_t esp32s3_efuse_read_reg(uint32_t blk, uint32_t num_reg) -{ - DEBUGASSERT(blk >= 0 && blk < EFUSE_BLK_MAX); - uint32_t value; - uint32_t blk_start = g_start_efuse_rdreg[blk]; - - DEBUGASSERT(num_reg <= 7); - - value = getreg32(blk_start + num_reg * 4); - return value; -} - /**************************************************************************** * Name: esp32s3_efuse_fill_buff * @@ -709,3 +637,73 @@ void esp32s3_efuse_burn_efuses(void) }; } +/**************************************************************************** + * Name: esp32s3_efuse_read_reg + * + * Description: + * Read efuse register. + * + * Input Parameters: + * blk - Block number of eFuse + * num_reg - The register number in the block + * + * Returned Value: + * Return the value in the efuse register. + * + ****************************************************************************/ + +uint32_t esp32s3_efuse_read_reg(uint32_t blk, uint32_t num_reg) +{ + DEBUGASSERT(blk >= 0 && blk < EFUSE_BLK_MAX); + uint32_t value; + uint32_t blk_start = g_start_efuse_rdreg[blk]; + + DEBUGASSERT(num_reg <= 7); + + value = getreg32(blk_start + num_reg * 4); + return value; +} + +/**************************************************************************** + * Name: esp32s3_efuse_write_reg + * + * Description: + * Write value to efuse register. + * + * Input Parameters: + * blk - Block number of eFuse + * num_reg - The register number in the block + * value - Value to write + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32s3_efuse_write_reg(uint32_t blk, uint32_t num_reg, uint32_t value) +{ + uint32_t addr_wr_reg; + uint32_t reg_to_write; + uint32_t blk_start = g_start_efuse_wrreg[blk]; + + DEBUGASSERT(blk >= 0 && blk < EFUSE_BLK_MAX); + + DEBUGASSERT(num_reg <= 7); + + /* The block 0 and register 7 doesn't exist */ + + if (blk == 0 && num_reg == 7) + { + merr("Block 0 Register 7 doesn't exist!\n"); + return; + } + + addr_wr_reg = blk_start + num_reg * 4; + reg_to_write = getreg32(addr_wr_reg) | value; + + /* The register can be written in parts so we combine the new value + * with the one already available. + */ + + putreg32(reg_to_write, addr_wr_reg); +} diff --git a/arch/xtensa/src/esp32s3/esp32s3_efuse.h b/arch/xtensa/src/esp32s3/esp32s3_efuse.h index ae3d0a81a007c..b9ee0a2b0cbf0 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_efuse.h +++ b/arch/xtensa/src/esp32s3/esp32s3_efuse.h @@ -162,6 +162,41 @@ int esp32s3_efuse_write_field(const efuse_desc_t *field[], void esp32s3_efuse_burn_efuses(void); +/**************************************************************************** + * Name: esp32s3_efuse_read_reg + * + * Description: + * Read efuse register. + * + * Input Parameters: + * blk - Block number of eFuse + * num_reg - The register number in the block + * + * Returned Value: + * Return the value in the efuse register. + * + ****************************************************************************/ + +uint32_t esp32s3_efuse_read_reg(uint32_t blk, uint32_t num_reg); + +/**************************************************************************** + * Name: esp32s3_efuse_write_reg + * + * Description: + * Write value to efuse register. + * + * Input Parameters: + * blk - Block number of eFuse + * num_reg - The register number in the block + * value - Value to write + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32s3_efuse_write_reg(uint32_t blk, uint32_t num_reg, uint32_t value); + /**************************************************************************** * Name: esp32s3_efuse_initialize * diff --git a/arch/xtensa/src/esp32s3/esp32s3_gpio.c b/arch/xtensa/src/esp32s3/esp32s3_gpio.c index d36b951b9fcf8..ea240f91622eb 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_gpio.c +++ b/arch/xtensa/src/esp32s3/esp32s3_gpio.c @@ -41,6 +41,7 @@ #include "esp32s3_irq.h" #include "hardware/esp32s3_gpio.h" #include "hardware/esp32s3_iomux.h" +#include "hardware/esp32s3_usb_serial_jtag.h" /**************************************************************************** * Pre-processor Definitions @@ -207,6 +208,17 @@ int esp32s3_configgpio(uint32_t pin, gpio_pinattr_t attr) func = 0; cntrl = 0; + /* if pin 19 or 20 disable the USB/JTAG function and pull-up */ + + if (pin == 19 || pin == 20) + { + uint32_t regval; + regval = getreg32(USB_SERIAL_JTAG_CONF0_REG); + regval &= ~(USB_SERIAL_JTAG_USB_PAD_ENABLE | + USB_SERIAL_JTAG_DP_PULLUP); + putreg32(regval, USB_SERIAL_JTAG_CONF0_REG); + } + /* Handle input pins */ if ((attr & INPUT) != 0) @@ -505,6 +517,17 @@ void esp32s3_gpioirqdisable(int irq) regval &= ~(GPIO_PIN0_INT_ENA_M | GPIO_PIN0_INT_TYPE_M); putreg32(regval, regaddr); + /* Clear pending GPIO interrupt status before enable IRQ */ + + if (pin < 32) + { + putreg32(1 << pin, GPIO_STATUS_W1TC_REG); + } + else + { + putreg32(1 << (pin - 32), GPIO_STATUS1_W1TC_REG); + } + /* Configuration done. Re-enable the GPIO interrupt. */ up_enable_irq(ESP32S3_IRQ_GPIO_INT_CPU); diff --git a/arch/xtensa/src/esp32s3/esp32s3_himem.c b/arch/xtensa/src/esp32s3/esp32s3_himem.c index e1855d3f6d563..dbaf9751f81d9 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_himem.c +++ b/arch/xtensa/src/esp32s3/esp32s3_himem.c @@ -32,9 +32,11 @@ #include "xtensa.h" #include "esp32s3_spiram.h" #include "esp32s3_himem.h" +#include "esp32s3_spiflash_mtd.h" #include "hardware/esp32s3_soc.h" #include "hardware/esp32s3_cache_memory.h" -#include "hardware/esp32s3_extmem.h" + +#include "soc/extmem_reg.h" /**************************************************************************** * Pre-processor Definitions @@ -82,7 +84,6 @@ # define SPIRAM_BANKSWITCH_RESERVE 0 #endif -#define MMU_PAGE_SIZE 0x10000 #define MMU_PAGE_TO_BYTES(page_num) ((page_num) * MMU_PAGE_SIZE) #define BYTES_TO_MMU_PAGE(bytes) ((bytes) / MMU_PAGE_SIZE) @@ -129,7 +130,6 @@ extern int cache_dbus_mmu_set(uint32_t ext_ram, uint32_t vaddr, static inline bool ramblock_idx_valid(int ramblock_idx); static inline bool rangeblock_idx_valid(int rangeblock_idx); -static void set_bank(int virt_bank, int phys_bank, int ct); static uint32_t esp_himem_get_range_start(void); static uint32_t esp_himem_get_range_block(void); static uint32_t esp_himem_get_phy_block(void); @@ -209,47 +209,6 @@ static inline bool rangeblock_idx_valid(int rangeblock_idx) return (rangeblock_idx >= 0 && rangeblock_idx < g_rangeblockcnt); } -/**************************************************************************** - * Name: set_bank - * - * Description: - * Set DCache mmu mapping. - * - * Input Parameters: - * virt_bank - Beginning of the virtual bank - * phys_bank - Beginning of the physical bank - * ct - Number of banks - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void set_bank(int virt_bank, int phys_bank, int ct) -{ - uint32_t regval; - - /* Suspend DRAM Case during configuration */ - - cache_suspend_dcache(); - ASSERT(cache_dbus_mmu_set(MMU_ACCESS_SPIRAM, - SOC_EXTRAM_DATA_LOW + - MMU_PAGE_TO_BYTES(virt_bank), - MMU_PAGE_TO_BYTES(phys_bank), 64, ct, 0) == 0); - - regval = getreg32(EXTMEM_DCACHE_CTRL1_REG); - regval &= ~EXTMEM_DCACHE_SHUT_CORE0_BUS; - putreg32(regval, EXTMEM_DCACHE_CTRL1_REG); - -#if defined(CONFIG_SMP) - regval = getreg32(EXTMEM_DCACHE_CTRL1_REG); - regval &= ~EXTMEM_DCACHE_SHUT_CORE1_BUS; - putreg32(regval, EXTMEM_DCACHE_CTRL1_REG); -#endif - - cache_resume_dcache(0); -} - /**************************************************************************** * Name: esp_himem_get_range_start * @@ -974,7 +933,7 @@ int esp_himem_map(esp_himem_handle_t handle, { virt_bank = himem_mmu_start + range->block_start + i + range_block; phys_bank = himem_phy_start + handle->block[i + ram_block]; - set_bank(virt_bank, phys_bank, 1); + esp32s3_set_bank(virt_bank, phys_bank, 1); } /* Set out pointer */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_i2s.c b/arch/xtensa/src/esp32s3/esp32s3_i2s.c index 34bda4b3c189f..06ee0116c2f25 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_i2s.c +++ b/arch/xtensa/src/esp32s3/esp32s3_i2s.c @@ -895,7 +895,8 @@ static IRAM_ATTR int i2s_txdma_setup(struct esp32s3_i2s_s *priv, bytes_queued = esp32s3_dma_setup(outlink, I2S_DMADESC_NUM, bfcontainer->buf, - bfcontainer->nbytes, I2S_TX); + bfcontainer->nbytes, I2S_TX, + priv->dma_channel); if (bytes_queued != bfcontainer->nbytes) { @@ -956,7 +957,8 @@ static int i2s_rxdma_setup(struct esp32s3_i2s_s *priv, bytes_queued = esp32s3_dma_setup(inlink, I2S_DMADESC_NUM, bfcontainer->apb->samp, - bfcontainer->nbytes, I2S_RX); + bfcontainer->nbytes, I2S_RX, + priv->dma_channel); if (bytes_queued != bfcontainer->nbytes) { @@ -2772,12 +2774,12 @@ static int i2s_send(struct i2s_dev_s *dev, struct ap_buffer_s *apb, nbytes -= (nbytes % (priv->data_width / 8)); - if (nbytes > (ESP32S3_DMA_DATALEN_MAX * I2S_DMADESC_NUM)) + if (nbytes > (ESP32S3_DMA_BUFLEN_MAX * I2S_DMADESC_NUM)) { i2serr("Required buffer size can't fit into DMA outlink " "(exceeds in %" PRIu32 " bytes). Try to increase the " "number of the DMA descriptors (CONFIG_I2S_DMADESC_NUM).", - nbytes - (ESP32S3_DMA_DATALEN_MAX * I2S_DMADESC_NUM)); + nbytes - (ESP32S3_DMA_BUFLEN_MAX * I2S_DMADESC_NUM)); return -EFBIG; } @@ -2880,7 +2882,7 @@ static int i2s_receive(struct i2s_dev_s *dev, struct ap_buffer_s *apb, nbytes -= (nbytes % (priv->data_width / 8)); - nbytes = MIN(nbytes, ESP32S3_DMA_DATALEN_MAX); + nbytes = MIN(nbytes, ESP32S3_DMA_BUFLEN_MAX); /* Allocate a buffer container in advance */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_idle.c b/arch/xtensa/src/esp32s3/esp32s3_idle.c index 16b714e6af5d4..25fbe6b9ef9b8 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_idle.c +++ b/arch/xtensa/src/esp32s3/esp32s3_idle.c @@ -24,20 +24,140 @@ #include +#include #include #include #include +#include #include "xtensa.h" +#include "esp32s3_pm.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* Values for the RTC Alarm to wake up from the PM_STANDBY mode + * (which corresponds to ESP32-C3 stop mode). If this alarm expires, + * the logic in this file will wakeup from PM_STANDBY mode and + * transition to PM_SLEEP mode (ESP32-C3 standby mode). + */ + +#ifdef CONFIG_PM +#ifndef CONFIG_PM_ALARM_SEC +# define CONFIG_PM_ALARM_SEC 15 +#endif + +#ifndef CONFIG_PM_ALARM_NSEC +# define CONFIG_PM_ALARM_NSEC 0 +#endif + +#ifndef CONFIG_PM_SLEEP_WAKEUP_SEC +# define CONFIG_PM_SLEEP_WAKEUP_SEC 20 +#endif + +#ifndef CONFIG_PM_SLEEP_WAKEUP_NSEC +# define CONFIG_PM_SLEEP_WAKEUP_NSEC 0 +#endif + +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: up_idlepm + * + * Description: + * Perform IDLE state power management. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void up_idlepm(void) +{ + irqstate_t flags; + static enum pm_state_e oldstate = PM_NORMAL; + enum pm_state_e newstate; + int ret; + + /* Decide, which power saving level can be obtained */ + + newstate = pm_checkstate(PM_IDLE_DOMAIN); + + /* Check for state changes */ + + if (newstate != oldstate) + { + flags = spin_lock_irqsave(NULL); + + /* Perform board-specific, state-dependent logic here */ + + _info("newstate= %d oldstate=%d\n", newstate, oldstate); + + /* Then force the global state change */ + + ret = pm_changestate(PM_IDLE_DOMAIN, newstate); + if (ret < 0) + { + /* The new state change failed, revert to the preceding state */ + + pm_changestate(PM_IDLE_DOMAIN, oldstate); + } + else + { + /* Save the new state */ + + oldstate = newstate; + } + + spin_unlock_irqrestore(NULL, flags); + + /* MCU-specific power management logic */ + + switch (newstate) + { + case PM_NORMAL: + break; + + case PM_IDLE: + break; + + case PM_STANDBY: + { + /* Enter Force-sleep mode */ + + esp32s3_pmstandby(CONFIG_PM_ALARM_SEC * 1000000 + + CONFIG_PM_ALARM_NSEC / 1000); + } + break; + + case PM_SLEEP: + { + /* Enter Deep-sleep mode */ + + esp32s3_pmsleep(CONFIG_PM_SLEEP_WAKEUP_SEC * 1000000 + + CONFIG_PM_SLEEP_WAKEUP_NSEC / 1000); + } + + default: + break; + } + } + else + { +#ifdef CONFIG_WATCHDOG + /* Announce the power management state change to feed watchdog */ + + pm_changestate(PM_IDLE_DOMAIN, PM_NORMAL); +#endif + } +} +#else +# define up_idlepm() +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -86,6 +206,10 @@ void up_idle(void) # if XCHAL_HAVE_INTERRUPTS __asm__ __volatile__ ("waiti 0"); # endif + + /* Perform IDLE mode power management */ + + up_idlepm(); #endif /* CONFIG_SUPPRESS_INTERRUPTS || CONFIG_SUPPRESS_TIMER_INTS */ #ifdef CONFIG_ESP32S3_SPEED_UP_ISR diff --git a/arch/xtensa/src/esp32s3/esp32s3_irq.c b/arch/xtensa/src/esp32s3/esp32s3_irq.c index 5e3dca56a316f..349bc006d1dbb 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_irq.c +++ b/arch/xtensa/src/esp32s3/esp32s3_irq.c @@ -687,22 +687,7 @@ void up_enable_irq(int irq) } /**************************************************************************** - * Name: xtensa_intstack_top - * - * Description: - * Return a pointer to the top of the correct interrupt stack for the - * given CPU. - * - ****************************************************************************/ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 -uintptr_t xtensa_intstack_top(void) -{ - return g_cpu_intstack_top[up_cpu_index()]; -} - -/**************************************************************************** - * Name: xtensa_intstack_alloc + * Name: up_get_intstackbase * * Description: * Return a pointer to the "alloc" the correct interrupt stack allocation @@ -710,9 +695,10 @@ uintptr_t xtensa_intstack_top(void) * ****************************************************************************/ -uintptr_t xtensa_intstack_alloc(void) +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 +uintptr_t up_get_intstackbase(int cpu) { - return g_cpu_intstack_top[up_cpu_index()] - INTSTACK_SIZE; + return g_cpu_intstack_top[cpu] - INTSTACK_SIZE; } #endif diff --git a/arch/xtensa/src/esp32s3/esp32s3_lcd.c b/arch/xtensa/src/esp32s3/esp32s3_lcd.c index 1615fcb1b6be1..7d84e627e0cf9 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_lcd.c +++ b/arch/xtensa/src/esp32s3/esp32s3_lcd.c @@ -41,13 +41,14 @@ #include "esp32s3_gpio.h" #include "esp32s3_dma.h" #include "esp32s3_irq.h" -#include "esp32s3_periph.h" #include "xtensa.h" #include "hardware/esp32s3_system.h" #include "hardware/esp32s3_gpio_sigmap.h" #include "hardware/esp32s3_lcd_cam.h" +#include "periph_ctrl.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -135,7 +136,7 @@ ESP32S3_LCD_DATA_WIDTH) #define ESP32S3_LCD_DMADESC_NUM (ESP32S3_LCD_FB_SIZE / \ - ESP32S3_DMA_DATALEN_MAX + 1) + ESP32S3_DMA_BUFLEN_MAX + 1) #define ESP32S3_LCD_LAYERS CONFIG_ESP32S3_LCD_BUFFER_LAYERS @@ -666,7 +667,7 @@ static void esp32s3_lcd_dmasetup(void) ESP32S3_LCD_DMADESC_NUM, layer->framebuffer, ESP32S3_LCD_FB_SIZE, - true); + true, priv->dma_channel); } } @@ -735,7 +736,7 @@ static void esp32s3_lcd_enableclk(void) lcdinfo("PCLK=%d/(%d + %d/%d)\n", ESP32S3_LCD_CLK_MHZ, ESP32S3_LCD_CLK_N, clk_b, clk_a); - esp32s3_periph_module_enable(PERIPH_LCD_CAM_MODULE); + periph_module_enable(PERIPH_LCD_CAM_MODULE); regval = (1 << LCD_CAM_LCD_CLKCNT_N_S) | LCD_CAM_CLK_EN_M | diff --git a/arch/xtensa/src/esp32s3/esp32s3_ledc.c b/arch/xtensa/src/esp32s3/esp32s3_ledc.c index d5ffba0a5bbb2..afbd8a9b78977 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_ledc.c +++ b/arch/xtensa/src/esp32s3/esp32s3_ledc.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "esp32s3_clockconfig.h" #include "esp32s3_gpio.h" @@ -104,15 +105,27 @@ /* LEDC clock resource */ -#define LEDC_CLK_RES (1) /* APB clock */ +#define LEDC_CLK_RES_APB (1) /* APB clock */ +#define LEDC_CLK_RES_RC_FAST (2) /* RC_FAST clock */ +#define LEDC_CLK_RES_XTAL (3) /* XTAL clock */ + +/* LEDC clock source frequency */ + +#define LEDC_CLK_APB_FREQ (80 * MHZ) /* APB clock frequency */ +#define LEDC_CLK_RC_FAST_FREQ (17.5 * MHZ) /* RC_FAST clock frequency */ +#define LEDC_CLK_XTAL_FREQ (40 * MHZ) /* XTAL clock frequency */ /* LEDC timer max reload */ #define LEDC_RELOAD_MAX (16384) /* 2^14 */ +/* LEDC timer max reload bit length */ + +#define LEDC_RELOAD_MAX_BIT_LEN (14) + /* LEDC timer max clock divider parameter */ -#define LEDC_CLKDIV_MAX (262144) /* 2^18 */ +#define LEDC_CLKDIV_MAX (1024) /* 2^10 */ /* LEDC timer registers mapping */ @@ -283,9 +296,9 @@ static struct esp32s3_ledc_s g_pwm3dev = }; #endif /* CONFIG_ESP32S3_LEDC_TIM3 */ -/* Clock reference count */ +/* Clock source */ -static uint32_t g_clk_ref; +static uint32_t clk_src = 0; /**************************************************************************** * Private functions @@ -311,19 +324,21 @@ static void ledc_enable_clk(void) flags = enter_critical_section(); - if (g_clk_ref == 0) + if (clk_src == 0) { setbits(SYSTEM_LEDC_CLK_EN, SYSTEM_PERIP_CLK_EN0_REG); resetbits(SYSTEM_LEDC_RST, SYSTEM_PERIP_RST_EN0_REG); - putreg32(LEDC_CLK_RES, LEDC_CONF_REG); - putreg32(LEDC_CLK_EN, LEDC_CONF_REG); + putreg32(LEDC_CLK_RES_APB, LEDC_CONF_REG); + setbits(LEDC_CLK_EN, LEDC_CONF_REG); + + /* We set default clock is APB. */ + + clk_src = LEDC_CLK_RES_APB; pwminfo("Enable ledc clock\n"); } - g_clk_ref++; - leave_critical_section(flags); } @@ -347,14 +362,13 @@ static void ledc_disable_clk(void) flags = enter_critical_section(); - g_clk_ref--; - - if (g_clk_ref == 0) + if (clk_src != 0) { pwminfo("Disable ledc clock\n"); setbits(SYSTEM_LEDC_RST, SYSTEM_PERIP_RST_EN0_REG); resetbits(SYSTEM_LEDC_CLK_EN, SYSTEM_PERIP_CLK_EN0_REG); + clk_src = 0; } leave_critical_section(flags); @@ -379,9 +393,41 @@ static void setup_timer(struct esp32s3_ledc_s *priv) irqstate_t flags; uint32_t regval; uint32_t reload; - uint32_t prescaler; - uint32_t shift = 1; - uint64_t pwmclk = esp_clk_apb_freq(); + float prescaler; + uint32_t integral_prescaler; + uint32_t fractional_prescaler; + uint8_t shift; + uint64_t pwmclk = LEDC_CLK_APB_FREQ; + + /* Determine the using clock source and set pwmclk */ + + switch (clk_src) + { + case LEDC_CLK_RES_APB: + + /* use APB clock */ + + pwmclk = LEDC_CLK_APB_FREQ; + break; + + case LEDC_CLK_RES_RC_FAST: + + /* use RC_FAST clock */ + + pwmclk = LEDC_CLK_RC_FAST_FREQ; + break; + + case LEDC_CLK_RES_XTAL: + + /* use XTAL clock */ + + pwmclk = LEDC_CLK_XTAL_FREQ; + break; + + default: + pwmerr("Invalid clock source or no clock has been inited !"); + break; + } /* Reset timer */ @@ -400,8 +446,8 @@ static void setup_timer(struct esp32s3_ledc_s *priv) * In ESP32S3, there are 3 clock resources for PWM: * * 1. APB clock (80 MHz) - * 2. RTC clock (8 MHz) - * 3. XTAL_CLK + * 2. RC_FAST_CLK (17.5 MHz) + * 3. XTAL_CLK (40 MHZ) * * We mostly use APB clock generally. * @@ -410,11 +456,11 @@ static void setup_timer(struct esp32s3_ledc_s *priv) * That is the solution that should give us the most accuracy in the timer * control. Subject to: * - * 2 <= presc <= 2^18(262144) + * 2 <= presc <= 2^14(16384) * 1 <= clkdiv <= 2^10 * - * clkdiv has 8-bit decimal precision, so - * clkdiv = pwmclk * 256 / 16384 / frequency would be optimal. + * clkdiv has 10-bit integral precision and 8-bit fractional precision, so + * clkdiv = pwmclk / 16384 / frequency would be optimal. * * Example: * @@ -431,34 +477,42 @@ static void setup_timer(struct esp32s3_ledc_s *priv) * shift = 14 */ - reload = (pwmclk * 256 / priv->frequency + LEDC_CLKDIV_MAX) / - LEDC_CLKDIV_MAX; - if (reload == 0) - { - reload = 1; - } - else if (reload > LEDC_RELOAD_MAX) - { - reload = LEDC_RELOAD_MAX; - } + /* Search the maximum value of timer reload value */ - for (int c = 2; c <= LEDC_RELOAD_MAX; c *= 2) - { - if (c * 2 > reload) + for (reload = LEDC_RELOAD_MAX , shift = LEDC_RELOAD_MAX_BIT_LEN; + reload > 1; + reload = (reload >> 1), shift -= 1) + { + if (reload * priv->frequency <= pwmclk) { - reload = c; break; } + } - shift++; - } + /* Caculate the prescaler */ + + prescaler = (float)pwmclk / priv->frequency / reload; - prescaler = pwmclk * 256 / reload / priv->frequency; + /* Get the integral part */ + + integral_prescaler = (uint32_t) prescaler; + + /* Get the fractional part. To write to the registers, value need to be + * multiply by 256 + */ + + fractional_prescaler = (uint32_t)((prescaler - integral_prescaler) * 256); + + /* Prevent prescaler goto 0. In esp32 series, prescaler == 1 means + * clock signal goes pass-through + */ + + if (integral_prescaler == 0) integral_prescaler = 1; pwminfo("PWM timer%" PRIu8 " frequency=%0.4f reload=%" PRIu32 " shift=%" PRIu32 " prescaler=%0.4f\n", - priv->num, (float)pwmclk / reload / ((float)prescaler / 256), - reload, shift, (float)prescaler / 256); + priv->num, (float)pwmclk / reload / ((float)prescaler), + reload, shift, (float)prescaler); /* Store reload for channel duty */ @@ -469,13 +523,10 @@ static void setup_timer(struct esp32s3_ledc_s *priv) /* Set timer clock divide and reload */ regval = (shift << LEDC_TIMER0_DUTY_RES_S) | - (prescaler << LEDC_CLK_DIV_TIMER0_S); + (fractional_prescaler << LEDC_CLK_DIV_TIMER0_S) | + (integral_prescaler << LEDC_CLK_DIV_TIMER0_S << 8); SET_TIMER_REG(priv, LEDC_TIMER0_CONF_REG, regval); - /* Setup to timer to use APB clock (80MHz) */ - - SET_TIMER_BITS(priv, LEDC_TIMER0_CONF_REG, LEDC_TICK_SEL_TIMER0); - /* Update clock divide and reload to hardware */ SET_TIMER_BITS(priv, LEDC_TIMER0_CONF_REG, LEDC_TIMER0_PARA_UP); @@ -523,6 +574,10 @@ static void setup_channel(struct esp32s3_ledc_s *priv, int cn) SET_CHAN_REG(chan, LEDC_CH0_CONF0_REG, 0); SET_CHAN_REG(chan, LEDC_CH0_CONF1_REG, 0); + /* Select the clock source */ + + SET_CHAN_REG(chan, LEDC_CH0_CONF0_REG, priv->num); + /* Set pulse phase 0 */ SET_CHAN_REG(chan, LEDC_CH0_HPOINT_REG, 0); diff --git a/arch/xtensa/src/esp32s3/esp32s3_libc_stubs.c b/arch/xtensa/src/esp32s3/esp32s3_libc_stubs.c index 56528eb1cfe14..0efe020acc895 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_libc_stubs.c +++ b/arch/xtensa/src/esp32s3/esp32s3_libc_stubs.c @@ -42,17 +42,12 @@ * Pre-processor Definitions ****************************************************************************/ -#define _lock_t int - #define ROM_MUTEX_MAGIC 0xbb10c433 /**************************************************************************** * Private Types ****************************************************************************/ -static mutex_t g_nxlock_common; -static mutex_t g_nxlock_recursive; - /* Forward declaration */ struct _reent; @@ -173,64 +168,108 @@ void _raise_r(struct _reent *r) void _lock_init(_lock_t *lock) { - nxmutex_init(&g_nxlock_common); - nxsem_get_value(&g_nxlock_common.sem, lock); + mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t)); + + nxmutex_init(mutex); + + *lock = (_lock_t)mutex; } void _lock_init_recursive(_lock_t *lock) { - nxmutex_init(&g_nxlock_recursive); - nxsem_get_value(&g_nxlock_recursive.sem, lock); + rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t)); + + nxrmutex_init(rmutex); + + *lock = (_lock_t)rmutex; } void _lock_close(_lock_t *lock) { - nxmutex_destroy(&g_nxlock_common); + mutex_t *mutex = (mutex_t *)(*lock); + + nxmutex_destroy(mutex); + kmm_free(*lock); *lock = 0; } void _lock_close_recursive(_lock_t *lock) { - nxmutex_destroy(&g_nxlock_recursive); + rmutex_t *rmutex = (rmutex_t *)(*lock); + + nxrmutex_destroy(rmutex); + kmm_free(*lock); *lock = 0; } void _lock_acquire(_lock_t *lock) { - nxmutex_lock(&g_nxlock_common); - nxsem_get_value(&g_nxlock_common.sem, lock); + if ((*lock) == NULL) + { + mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t)); + + nxmutex_init(mutex); + + *lock = (_lock_t)mutex; + } + + nxmutex_lock((mutex_t *)(*lock)); } void _lock_acquire_recursive(_lock_t *lock) { - nxmutex_lock(&g_nxlock_recursive); - nxsem_get_value(&g_nxlock_recursive.sem, lock); + if ((*lock) == NULL) + { + rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t)); + + nxrmutex_init(rmutex); + + *lock = (_lock_t)rmutex; + } + + nxrmutex_lock((rmutex_t *)(*lock)); } int _lock_try_acquire(_lock_t *lock) { - nxmutex_trylock(&g_nxlock_common); - nxsem_get_value(&g_nxlock_common.sem, lock); - return 0; + if ((*lock) == NULL) + { + mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t)); + + nxmutex_init(mutex); + + *lock = (_lock_t)mutex; + } + + return nxmutex_trylock((mutex_t *)(*lock)); } int _lock_try_acquire_recursive(_lock_t *lock) { - nxmutex_trylock(&g_nxlock_recursive); - nxsem_get_value(&g_nxlock_recursive.sem, lock); - return 0; + if ((*lock) == NULL) + { + rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t)); + + nxrmutex_init(rmutex); + + *lock = (_lock_t)rmutex; + } + + return nxrmutex_trylock((rmutex_t *)(*lock)); } void _lock_release(_lock_t *lock) { - nxmutex_unlock(&g_nxlock_common); - nxsem_get_value(&g_nxlock_common.sem, lock); + mutex_t *mutex = (mutex_t *)(*lock); + + nxmutex_unlock(mutex); } void _lock_release_recursive(_lock_t *lock) { - nxmutex_unlock(&g_nxlock_recursive); - nxsem_get_value(&g_nxlock_recursive.sem, lock); + rmutex_t *rmutex = (rmutex_t *)(*lock); + + nxrmutex_unlock(rmutex); } void __retarget_lock_init(_lock_t *lock) @@ -376,6 +415,9 @@ static const struct syscall_stub_table g_stub_table = void esp_setup_syscall_table(void) { + static_assert(sizeof(struct __lock) >= sizeof(mutex_t), + "Invalid size of struct __lock"); + syscall_table_ptr = (struct syscall_stub_table *)&g_stub_table; /* Newlib 3.3.0 is used in ROM, built with _RETARGETABLE_LOCKING. diff --git a/arch/xtensa/src/esp32s3/esp32s3_lowputc.c b/arch/xtensa/src/esp32s3/esp32s3_lowputc.c index 0ae6ba6576368..b8c7e264c20a6 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_lowputc.c +++ b/arch/xtensa/src/esp32s3/esp32s3_lowputc.c @@ -45,13 +45,13 @@ #include "hardware/esp32s3_uart.h" #include "hardware/esp32s3_soc.h" +#include "periph_ctrl.h" + #include "esp32s3_clockconfig.h" #include "esp32s3_gpio.h" #include "esp32s3_lowputc.h" -#include "esp32s3_periph.h" - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -706,7 +706,7 @@ void esp32s3_lowputc_send_byte(const struct esp32s3_uart_s *priv, void esp32s3_lowputc_enable_sysclk(const struct esp32s3_uart_s *priv) { - esp32s3_periph_module_enable(PERIPH_UART0_MODULE + priv->id); + periph_module_enable(PERIPH_UART0_MODULE + priv->id); } /**************************************************************************** diff --git a/arch/xtensa/src/esp32s3/esp32s3_otg.h b/arch/xtensa/src/esp32s3/esp32s3_otg.h index 82a885cb26fcc..728b072196932 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_otg.h +++ b/arch/xtensa/src/esp32s3/esp32s3_otg.h @@ -29,9 +29,6 @@ #include -#include "chip.h" -#include "hardware/esp32s3_otg.h" - #if defined(CONFIG_ESP32S3_OTG) /**************************************************************************** diff --git a/arch/xtensa/src/esp32s3/esp32s3_otg_device.c b/arch/xtensa/src/esp32s3/esp32s3_otg_device.c index bb7ffc69fef96..0d1d33a85a7ee 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_otg_device.c +++ b/arch/xtensa/src/esp32s3/esp32s3_otg_device.c @@ -5063,14 +5063,22 @@ static int esp32s3_pullup(struct usbdev_s *dev, bool enable) usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); irqstate_t flags = enter_critical_section(); - regval = esp32s3_getreg(ESP32S3_OTG_DCTL); if (enable) { /* Connect the device by clearing the soft disconnect bit in the DCTL * register. */ + regval = esp32s3_getreg(ESP32S3_OTG_DCTL); regval &= ~OTG_DCTL_SDIS; + esp32s3_putreg(regval, ESP32S3_OTG_DCTL); + + /* Set DP pull-up */ + + regval = esp32s3_getreg(USB_WRAP_OTG_CONF_REG); + regval &= ~USB_WRAP_DP_PULLDOWN; + regval |= USB_WRAP_DP_PULLUP; + esp32s3_putreg(regval, USB_WRAP_OTG_CONF_REG); } else { @@ -5078,10 +5086,18 @@ static int esp32s3_pullup(struct usbdev_s *dev, bool enable) * register. */ + regval = esp32s3_getreg(ESP32S3_OTG_DCTL); regval |= OTG_DCTL_SDIS; + esp32s3_putreg(regval, ESP32S3_OTG_DCTL); + + /* Set DP pull-down */ + + regval = esp32s3_getreg(USB_WRAP_OTG_CONF_REG); + regval &= ~USB_WRAP_DP_PULLUP; + regval |= USB_WRAP_DP_PULLDOWN; + esp32s3_putreg(regval, USB_WRAP_OTG_CONF_REG); } - esp32s3_putreg(regval, ESP32S3_OTG_DCTL); leave_critical_section(flags); return OK; } @@ -5297,11 +5313,12 @@ static void esp32s3_hwinitialize(struct esp32s3_usbdev_s *priv) regval |= RTC_CNTL_SW_HW_USB_PHY_SEL | RTC_CNTL_SW_USB_PHY_SEL; esp32s3_putreg(regval, RTC_CNTL_RTC_USB_CONF_REG); + /* Set USB DM and DP pin pull-down */ + regval = esp32s3_getreg(USB_WRAP_OTG_CONF_REG); - regval &= ~(USB_WRAP_PHY_SEL | USB_WRAP_DM_PULLUP | - USB_WRAP_DP_PULLDOWN | USB_WRAP_DM_PULLDOWN); - regval |= USB_WRAP_PAD_PULL_OVERRIDE | USB_WRAP_DP_PULLUP | - USB_WRAP_USB_PAD_ENABLE; + regval &= ~(USB_WRAP_PHY_SEL | USB_WRAP_DP_PULLUP | USB_WRAP_DM_PULLUP); + regval |= USB_WRAP_PAD_PULL_OVERRIDE | USB_WRAP_DP_PULLDOWN | + USB_WRAP_DM_PULLDOWN | USB_WRAP_USB_PAD_ENABLE; esp32s3_putreg(regval, USB_WRAP_OTG_CONF_REG); /* At start-up the core is in FS mode. */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_periph.c b/arch/xtensa/src/esp32s3/esp32s3_periph.c deleted file mode 100644 index 7b88878326aa6..0000000000000 --- a/arch/xtensa/src/esp32s3/esp32s3_periph.c +++ /dev/null @@ -1,713 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/esp32s3_periph.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "hardware/esp32s3_syscon.h" -#include "hardware/esp32s3_system.h" - -#include "esp32s3_reset_reasons.h" - -#include "xtensa.h" - -#include "esp32s3_periph.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static uint8_t ref_counts[PERIPH_MODULE_MAX]; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Get the reset reason for CPU. */ - -extern esp32s3_periph_module_t esp_rom_get_reset_reason(int cpu_no); - -/**************************************************************************** - * Name: esp32s3_periph_ll_get_clk_en_reg - * - * Description: - * Get module clock register through periph module - * - * Input Parameters: - * periph - Periph module (one of the esp32s3_periph_module_t values) - * - * Returned Value: - * Module clock register - * - ****************************************************************************/ - -static uint32_t IRAM_ATTR esp32s3_periph_ll_get_clk_en_reg( - esp32s3_periph_module_t periph) -{ - switch (periph) - { - case PERIPH_DEDIC_GPIO_MODULE: - return SYSTEM_CPU_PERI_CLK_EN_REG; - case PERIPH_RNG_MODULE: - case PERIPH_WIFI_MODULE: - case PERIPH_BT_MODULE: - case PERIPH_WIFI_BT_COMMON_MODULE: - case PERIPH_BT_BASEBAND_MODULE: - case PERIPH_BT_LC_MODULE: - return SYSTEM_WIFI_CLK_EN_REG; - case PERIPH_UART2_MODULE: - case PERIPH_SDMMC_MODULE: - case PERIPH_LCD_CAM_MODULE: - case PERIPH_GDMA_MODULE: - case PERIPH_HMAC_MODULE: - case PERIPH_DS_MODULE: - case PERIPH_AES_MODULE: - case PERIPH_SHA_MODULE: - case PERIPH_RSA_MODULE: - return SYSTEM_PERIP_CLK_EN1_REG; - default: - return SYSTEM_PERIP_CLK_EN0_REG; - } -} - -/**************************************************************************** - * Name: esp32s3_periph_ll_get_clk_en_mask - * - * Description: - * Get module clock bit through periph module - * - * Input Parameters: - * periph - Periph module (one of the esp32s3_periph_module_t values) - * - * Returned Value: - * Module clock bit - * - ****************************************************************************/ - -static inline uint32_t IRAM_ATTR esp32s3_periph_ll_get_clk_en_mask( - esp32s3_periph_module_t periph) -{ - switch (periph) - { - case PERIPH_SARADC_MODULE: - return SYSTEM_APB_SARADC_CLK_EN; - case PERIPH_RMT_MODULE: - return SYSTEM_RMT_CLK_EN; - case PERIPH_LEDC_MODULE: - return SYSTEM_LEDC_CLK_EN; - case PERIPH_UART0_MODULE: - return SYSTEM_UART_CLK_EN; - case PERIPH_UART1_MODULE: - return SYSTEM_UART1_CLK_EN; - case PERIPH_UART2_MODULE: - return SYSTEM_UART2_CLK_EN; - case PERIPH_USB_MODULE: - return SYSTEM_USB_CLK_EN; - case PERIPH_I2C0_MODULE: - return SYSTEM_I2C_EXT0_CLK_EN; - case PERIPH_I2C1_MODULE: - return SYSTEM_I2C_EXT1_CLK_EN; - case PERIPH_I2S0_MODULE: - return SYSTEM_I2S0_CLK_EN; - case PERIPH_I2S1_MODULE: - return SYSTEM_I2S1_CLK_EN; - case PERIPH_LCD_CAM_MODULE: - return SYSTEM_LCD_CAM_CLK_EN; - case PERIPH_TIMG0_MODULE: - return SYSTEM_TIMERGROUP_CLK_EN; - case PERIPH_TIMG1_MODULE: - return SYSTEM_TIMERGROUP1_CLK_EN; - case PERIPH_PWM0_MODULE: - return SYSTEM_PWM0_CLK_EN; - case PERIPH_PWM1_MODULE: - return SYSTEM_PWM1_CLK_EN; - case PERIPH_UHCI0_MODULE: - return SYSTEM_UHCI0_CLK_EN; - case PERIPH_UHCI1_MODULE: - return SYSTEM_UHCI1_CLK_EN; - case PERIPH_PCNT_MODULE: - return SYSTEM_PCNT_CLK_EN; - case PERIPH_SPI_MODULE: - return SYSTEM_SPI01_CLK_EN; - case PERIPH_SPI2_MODULE: - return SYSTEM_SPI2_CLK_EN; - case PERIPH_SPI3_MODULE: - return SYSTEM_SPI3_CLK_EN; - case PERIPH_SDMMC_MODULE: - return SYSTEM_SDIO_HOST_CLK_EN; - case PERIPH_TWAI_MODULE: - return SYSTEM_TWAI_CLK_EN; - case PERIPH_RNG_MODULE: - return SYSTEM_WIFI_CLK_RNG_EN; - case PERIPH_WIFI_MODULE: - return SYSTEM_WIFI_CLK_WIFI_EN_M; - case PERIPH_BT_MODULE: - return SYSTEM_WIFI_CLK_BT_EN_M; - case PERIPH_WIFI_BT_COMMON_MODULE: - return SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M; - case PERIPH_BT_BASEBAND_MODULE: - return SYSTEM_BT_BASEBAND_EN; - case PERIPH_BT_LC_MODULE: - return SYSTEM_BT_LC_EN; - case PERIPH_SYSTIMER_MODULE: - return SYSTEM_SYSTIMER_CLK_EN; - case PERIPH_DEDIC_GPIO_MODULE: - return SYSTEM_CLK_EN_DEDICATED_GPIO; - case PERIPH_GDMA_MODULE: - return SYSTEM_DMA_CLK_EN; - case PERIPH_AES_MODULE: - return SYSTEM_CRYPTO_AES_CLK_EN; - case PERIPH_SHA_MODULE: - return SYSTEM_CRYPTO_SHA_CLK_EN; - case PERIPH_RSA_MODULE: - return SYSTEM_CRYPTO_RSA_CLK_EN; - case PERIPH_HMAC_MODULE: - return SYSTEM_CRYPTO_HMAC_CLK_EN; - case PERIPH_DS_MODULE: - return SYSTEM_CRYPTO_DS_CLK_EN; - default: - return 0; - } -} - -/**************************************************************************** - * Name: esp32s3_periph_ll_get_rst_en_reg - * - * Description: - * Get system reset register through periph module - * - * Input Parameters: - * periph - Periph module (one of the esp32s3_periph_module_t values) - * - * Returned Value: - * System reset register - * - ****************************************************************************/ - -static uint32_t IRAM_ATTR esp32s3_periph_ll_get_rst_en_reg( - esp32s3_periph_module_t periph) -{ - switch (periph) - { - case PERIPH_DEDIC_GPIO_MODULE: - return SYSTEM_CPU_PERI_RST_EN_REG; - case PERIPH_RNG_MODULE: - case PERIPH_WIFI_MODULE: - case PERIPH_BT_MODULE: - case PERIPH_WIFI_BT_COMMON_MODULE: - case PERIPH_BT_BASEBAND_MODULE: - case PERIPH_BT_LC_MODULE: - return SYSTEM_CORE_RST_EN_REG; - case PERIPH_UART2_MODULE: - case PERIPH_SDMMC_MODULE: - case PERIPH_LCD_CAM_MODULE: - case PERIPH_GDMA_MODULE: - case PERIPH_HMAC_MODULE: - case PERIPH_DS_MODULE: - case PERIPH_AES_MODULE: - case PERIPH_SHA_MODULE: - case PERIPH_RSA_MODULE: - return SYSTEM_PERIP_RST_EN1_REG; - default: - return SYSTEM_PERIP_RST_EN0_REG; - } -} - -/**************************************************************************** - * Name: esp32s3_periph_ll_get_rst_en_mask - * - * Description: - * Get system reset bit through periph module - * - * Input Parameters: - * periph - Periph module (one of the esp32s3_periph_module_t values) - * enable - Whether hardware acceleration is enabled - * - * Returned Value: - * System reset bit - * - ****************************************************************************/ - -static inline uint32_t IRAM_ATTR esp32s3_periph_ll_get_rst_en_mask( - esp32s3_periph_module_t periph, - bool enable) -{ - switch (periph) - { - case PERIPH_SARADC_MODULE: - return SYSTEM_APB_SARADC_RST; - case PERIPH_RMT_MODULE: - return SYSTEM_RMT_RST; - case PERIPH_LEDC_MODULE: - return SYSTEM_LEDC_RST; - case PERIPH_WIFI_MODULE: - return SYSTEM_WIFIMAC_RST; - case PERIPH_BT_MODULE: - return (SYSTEM_BTBB_RST | SYSTEM_BTBB_REG_RST | - SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | - SYSTEM_RW_BTMAC_REG_RST | SYSTEM_RW_BTLP_REG_RST); - case PERIPH_UART0_MODULE: - return SYSTEM_UART_RST; - case PERIPH_UART1_MODULE: - return SYSTEM_UART1_RST; - case PERIPH_UART2_MODULE: - return SYSTEM_UART2_RST; - case PERIPH_USB_MODULE: - return SYSTEM_USB_RST; - case PERIPH_I2C0_MODULE: - return SYSTEM_I2C_EXT0_RST; - case PERIPH_I2C1_MODULE: - return SYSTEM_I2C_EXT1_RST; - case PERIPH_I2S0_MODULE: - return SYSTEM_I2S0_RST; - case PERIPH_I2S1_MODULE: - return SYSTEM_I2S1_RST; - case PERIPH_LCD_CAM_MODULE: - return SYSTEM_LCD_CAM_RST; - case PERIPH_TIMG0_MODULE: - return SYSTEM_TIMERGROUP_RST; - case PERIPH_TIMG1_MODULE: - return SYSTEM_TIMERGROUP1_RST; - case PERIPH_PWM0_MODULE: - return SYSTEM_PWM0_RST; - case PERIPH_PWM1_MODULE: - return SYSTEM_PWM1_RST; - case PERIPH_UHCI0_MODULE: - return SYSTEM_UHCI0_RST; - case PERIPH_UHCI1_MODULE: - return SYSTEM_UHCI1_RST; - case PERIPH_PCNT_MODULE: - return SYSTEM_PCNT_RST; - case PERIPH_SPI_MODULE: - return SYSTEM_SPI01_RST; - case PERIPH_SPI2_MODULE: - return SYSTEM_SPI2_RST; - case PERIPH_SPI3_MODULE: - return SYSTEM_SPI3_RST; - case PERIPH_SDMMC_MODULE: - return SYSTEM_SDIO_HOST_RST; - case PERIPH_TWAI_MODULE: - return SYSTEM_TWAI_RST; - case PERIPH_SYSTIMER_MODULE: - return SYSTEM_SYSTIMER_RST; - case PERIPH_DEDIC_GPIO_MODULE: - return SYSTEM_RST_EN_DEDICATED_GPIO; - case PERIPH_GDMA_MODULE: - return SYSTEM_DMA_RST; - case PERIPH_HMAC_MODULE: - return SYSTEM_CRYPTO_HMAC_RST; - case PERIPH_DS_MODULE: - return SYSTEM_CRYPTO_DS_RST; - case PERIPH_AES_MODULE: - if (enable) - { - /* Clear reset on digital signature, otherwise AES unit is - * held in reset also. - */ - - return (SYSTEM_CRYPTO_AES_RST | SYSTEM_CRYPTO_DS_RST); - } - else - { - /* Don't return other units to reset, as this pulls reset - * on RSA & SHA units, respectively. - */ - - return SYSTEM_CRYPTO_AES_RST; - } - - case PERIPH_SHA_MODULE: - if (enable) - { - /* Clear reset on digital signature and HMAC, otherwise SHA is - * held in reset - */ - - return (SYSTEM_CRYPTO_SHA_RST | SYSTEM_CRYPTO_DS_RST | - SYSTEM_CRYPTO_HMAC_RST) ; - } - else - { - /* Don't assert reset on secure boot, otherwise AES is - * held in reset - */ - - return SYSTEM_CRYPTO_SHA_RST; - } - - case PERIPH_RSA_MODULE: - if (enable) - { - /* also clear reset on digital signature, otherwise RSA is - * held in reset - */ - - return (SYSTEM_CRYPTO_RSA_RST | SYSTEM_CRYPTO_DS_RST); - } - else - { - /* don't reset digital signature unit, as this resets AES also */ - - return SYSTEM_CRYPTO_RSA_RST; - } - - default: - return 0; - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s3_periph_module_enable - * - * Description: - * Enable peripheral module - * - * Input Parameters: - * periph - Periph module (one of the esp32s3_periph_module_t values) - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_periph_module_enable(esp32s3_periph_module_t periph) -{ - irqstate_t flags = enter_critical_section(); - - ASSERT(periph < PERIPH_MODULE_MAX); - if (ref_counts[periph] == 0) - { - modifyreg32(esp32s3_periph_ll_get_clk_en_reg(periph), 0, - esp32s3_periph_ll_get_clk_en_mask(periph)); - modifyreg32(esp32s3_periph_ll_get_rst_en_reg(periph), - esp32s3_periph_ll_get_rst_en_mask(periph, true), 0); - } - - ref_counts[periph]++; - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: esp32s3_periph_module_disable - * - * Description: - * Disable peripheral module - * - * Input Parameters: - * periph - Periph module (one of enum esp32s3_periph_module_t values) - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_periph_module_disable(esp32s3_periph_module_t periph) -{ - irqstate_t flags = enter_critical_section(); - - ASSERT(periph < PERIPH_MODULE_MAX); - ref_counts[periph]--; - if (ref_counts[periph] == 0) - { - modifyreg32(esp32s3_periph_ll_get_clk_en_reg(periph), - esp32s3_periph_ll_get_clk_en_mask(periph), 0); - modifyreg32(esp32s3_periph_ll_get_rst_en_reg(periph), 0, - esp32s3_periph_ll_get_rst_en_mask(periph, false)); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: esp32s3_periph_module_reset - * - * Description: - * Reset peripheral module by asserting and de-asserting the reset signal. - * - * Input Parameters: - * periph - Periph module (one of the esp32s3_periph_module_t values) - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_periph_module_reset(esp32s3_periph_module_t periph) -{ - irqstate_t flags = enter_critical_section(); - - ASSERT(periph < PERIPH_MODULE_MAX); - - modifyreg32(esp32s3_periph_ll_get_rst_en_reg(periph), 0, - esp32s3_periph_ll_get_rst_en_mask(periph, false)); - modifyreg32(esp32s3_periph_ll_get_rst_en_reg(periph), - esp32s3_periph_ll_get_rst_en_mask(periph, false), 0); - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: esp32s3_periph_wifi_bt_common_module_enable - * - * Description: - * Enable Wi-Fi and BT common module. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_periph_wifi_bt_common_module_enable(void) -{ - irqstate_t flags = enter_critical_section(); - - if (ref_counts[PERIPH_WIFI_BT_COMMON_MODULE] == 0) - { - modifyreg32(SYSTEM_WIFI_CLK_EN_REG, - 0, SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M); - modifyreg32(SYSTEM_CORE_RST_EN_REG, 0, 0); - } - - ref_counts[PERIPH_WIFI_BT_COMMON_MODULE]++; - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: esp32s3_periph_wifi_bt_common_module_disable - * - * Description: - * Disable Wi-Fi and BT common module. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_periph_wifi_bt_common_module_disable(void) -{ - irqstate_t flags = enter_critical_section(); - - ref_counts[PERIPH_WIFI_BT_COMMON_MODULE]--; - - if (ref_counts[PERIPH_WIFI_BT_COMMON_MODULE] == 0) - { - modifyreg32(SYSTEM_WIFI_CLK_EN_REG, - SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M, 0); - modifyreg32(SYSTEM_CORE_RST_EN_REG, 0, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: esp32s3_perip_clk_init - * - * Description: - * This function disables clock of useless peripherals when cpu starts. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_perip_clk_init(void) -{ - uint32_t common_perip_clk; - uint32_t common_perip_clk1 = 0; - uint32_t hwcrypto_perip_clk; - uint32_t wifi_bt_sdio_clk; - -#ifndef CONFIG_SMP - soc_reset_reason_t rst_reas[1]; -#else - soc_reset_reason_t rst_reas[2]; -#endif - - rst_reas[0] = esp_rom_get_reset_reason(0); -#ifdef CONFIG_SMP - rst_reas[1] = esp_rom_get_reset_reason(1); -#endif - - /* For reason that only reset CPU, do not disable the clocks - * that have been enabled before reset. - */ - - if ((rst_reas[0] == RESET_REASON_CPU0_MWDT0 || - rst_reas[0] == RESET_REASON_CPU0_SW || - rst_reas[0] == RESET_REASON_CPU0_RTC_WDT || - rst_reas[0] == RESET_REASON_CPU0_MWDT1) -#ifdef CONFIG_SMP - || (rst_reas[1] == RESET_REASON_CPU1_MWDT0 || - rst_reas[1] == RESET_REASON_CPU1_SW || - rst_reas[1] == RESET_REASON_CPU1_RTC_WDT || - rst_reas[1] == RESET_REASON_CPU1_MWDT1) -#endif - ) - { - common_perip_clk = ~getreg32(SYSTEM_PERIP_CLK_EN0_REG); - hwcrypto_perip_clk = ~getreg32(SYSTEM_PERIP_CLK_EN1_REG); - wifi_bt_sdio_clk = ~getreg32(SYSTEM_WIFI_CLK_EN_REG); - } - else - { - common_perip_clk = SYSTEM_WDG_CLK_EN | - SYSTEM_I2S0_CLK_EN | -#ifndef CONFIG_UART0_SERIAL_CONSOLE - SYSTEM_UART_CLK_EN | -#endif -#ifndef CONFIG_UART1_SERIAL_CONSOLE - SYSTEM_UART1_CLK_EN | -#endif - SYSTEM_USB_CLK_EN | - SYSTEM_SPI2_CLK_EN | - SYSTEM_I2C_EXT0_CLK_EN | - SYSTEM_UHCI0_CLK_EN | - SYSTEM_RMT_CLK_EN | - SYSTEM_PCNT_CLK_EN | - SYSTEM_LEDC_CLK_EN | - SYSTEM_TIMERGROUP1_CLK_EN | - SYSTEM_SPI3_CLK_EN | - SYSTEM_SPI4_CLK_EN | - SYSTEM_PWM0_CLK_EN | - SYSTEM_TWAI_CLK_EN | - SYSTEM_PWM1_CLK_EN | - SYSTEM_I2S1_CLK_EN | - SYSTEM_SPI2_DMA_CLK_EN | - SYSTEM_SPI3_DMA_CLK_EN | - SYSTEM_PWM2_CLK_EN | - SYSTEM_PWM3_CLK_EN; -#ifndef CONFIG_UART2_SERIAL_CONSOLE - common_perip_clk1 = SYSTEM_UART2_CLK_EN; -#endif - hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN | - SYSTEM_CRYPTO_SHA_CLK_EN | - SYSTEM_CRYPTO_RSA_CLK_EN; - wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN | - SYSTEM_WIFI_CLK_BT_EN_M | - SYSTEM_WIFI_CLK_I2C_CLK_EN | - SYSTEM_WIFI_CLK_UNUSED_BIT12 | - SYSTEM_WIFI_CLK_SDIO_HOST_EN; - } - - /* Reset the communication peripherals like I2C, SPI, UART, I2S - * and bring them to known state. - */ - - common_perip_clk |= SYSTEM_I2S0_CLK_EN | -#ifndef CONFIG_UART0_SERIAL_CONSOLE - SYSTEM_UART_CLK_EN | -#endif -#ifndef CONFIG_UART1_SERIAL_CONSOLE - SYSTEM_UART1_CLK_EN | -#endif - SYSTEM_USB_CLK_EN | - SYSTEM_SPI2_CLK_EN | - SYSTEM_I2C_EXT0_CLK_EN | - SYSTEM_UHCI0_CLK_EN | - SYSTEM_RMT_CLK_EN | - SYSTEM_UHCI1_CLK_EN | - SYSTEM_SPI3_CLK_EN | - SYSTEM_SPI4_CLK_EN | - SYSTEM_I2C_EXT1_CLK_EN | - SYSTEM_I2S1_CLK_EN | - SYSTEM_SPI2_DMA_CLK_EN | - SYSTEM_SPI3_DMA_CLK_EN; -#ifndef CONFIG_UART2_SERIAL_CONSOLE - common_perip_clk1 |= SYSTEM_UART2_CLK_EN; -#endif - - /* Disable some peripheral clocks. */ - - modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk, 0); - modifyreg32(SYSTEM_PERIP_RST_EN0_REG, 0, common_perip_clk); - - modifyreg32(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1, 0); - modifyreg32(SYSTEM_PERIP_RST_EN1_REG, 0, common_perip_clk1); - - /* Disable hardware crypto clocks. */ - - modifyreg32(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk, 0); - modifyreg32(SYSTEM_PERIP_RST_EN1_REG, 0, hwcrypto_perip_clk); - - /* Force clear backup dma reset signal. This is a fix to the backup dma - * implementation in the ROM, the reset signal was not cleared when the - * backup dma was started, which caused the backup dma operation to fail. - */ - - modifyreg32(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_PERI_BACKUP_RST, 0); - - /* Disable WiFi/BT/SDIO clocks. */ - - modifyreg32(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk, 0); - modifyreg32(SYSTEM_WIFI_CLK_EN_REG, 0, SYSTEM_WIFI_CLK_EN); - - /* Set WiFi light sleep clock source to RTC slow clock */ - - REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0); - modifyreg32(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M, 0); - modifyreg32(SYSTEM_BT_LPCK_DIV_FRAC_REG, 0, SYSTEM_LPCLK_SEL_RTC_SLOW); - - /* Enable RNG clock. */ - - esp32s3_periph_module_enable(PERIPH_RNG_MODULE); - - /* Enable TimerGroup 0 clock to ensure its reference counter will never - * be decremented to 0 during normal operation and preventing it from - * being disabled. - * If the TimerGroup 0 clock is disabled and then reenabled, the watchdog - * registers (Flashboot protection included) will be reenabled, and some - * seconds later, will trigger an unintended reset. - */ - - esp32s3_periph_module_enable(PERIPH_TIMG0_MODULE); -} diff --git a/arch/xtensa/src/esp32s3/esp32s3_periph.h b/arch/xtensa/src/esp32s3/esp32s3_periph.h deleted file mode 100644 index 5741edec49e49..0000000000000 --- a/arch/xtensa/src/esp32s3/esp32s3_periph.h +++ /dev/null @@ -1,199 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/esp32s3_periph.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PERIPH_H -#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PERIPH_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -typedef enum -{ - PERIPH_LEDC_MODULE = 0, - PERIPH_UART0_MODULE, - PERIPH_UART1_MODULE, - PERIPH_UART2_MODULE, - PERIPH_USB_MODULE, - PERIPH_I2C0_MODULE, - PERIPH_I2C1_MODULE, - PERIPH_I2S0_MODULE, - PERIPH_I2S1_MODULE, - PERIPH_LCD_CAM_MODULE, - PERIPH_TIMG0_MODULE, - PERIPH_TIMG1_MODULE, - PERIPH_PWM0_MODULE, - PERIPH_PWM1_MODULE, - PERIPH_PWM2_MODULE, - PERIPH_PWM3_MODULE, - PERIPH_UHCI0_MODULE, - PERIPH_UHCI1_MODULE, - PERIPH_RMT_MODULE, - PERIPH_PCNT_MODULE, - PERIPH_SPI_MODULE, - PERIPH_SPI2_MODULE, - PERIPH_SPI3_MODULE, - PERIPH_SDMMC_MODULE, - PERIPH_TWAI_MODULE, - PERIPH_RNG_MODULE, - PERIPH_WIFI_MODULE, - PERIPH_BT_MODULE, - PERIPH_WIFI_BT_COMMON_MODULE, - PERIPH_BT_BASEBAND_MODULE, - PERIPH_BT_LC_MODULE, - PERIPH_AES_MODULE, - PERIPH_SHA_MODULE, - PERIPH_HMAC_MODULE, - PERIPH_DS_MODULE, - PERIPH_RSA_MODULE, - PERIPH_SYSTIMER_MODULE, - PERIPH_GDMA_MODULE, - PERIPH_DEDIC_GPIO_MODULE, - PERIPH_SARADC_MODULE, - PERIPH_TEMPSENSOR_MODULE, - PERIPH_MODULE_MAX -} esp32s3_periph_module_t; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s3_periph_module_enable - * - * Description: - * Enable peripheral module - * - * Input Parameters: - * periph - Periph module (one of enum esp32s3_periph_module_t values) - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_periph_module_enable(esp32s3_periph_module_t periph); - -/**************************************************************************** - * Name: esp32s3_periph_module_disable - * - * Description: - * Disable peripheral module - * - * Input Parameters: - * periph - Periph module (one of enum esp32s3_periph_module_t values) - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_periph_module_disable(esp32s3_periph_module_t periph); - -/**************************************************************************** - * Name: esp32s3_periph_module_reset - * - * Description: - * Reset peripheral module by asserting and de-asserting the reset signal. - * - * Input Parameters: - * periph - Periph module (one of the esp32s3_periph_module_t values) - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_periph_module_reset(esp32s3_periph_module_t periph); - -/**************************************************************************** - * Name: esp32s3_periph_wifi_bt_common_module_enable - * - * Description: - * Enable Wi-Fi and BT common module. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_periph_wifi_bt_common_module_enable(void); - -/**************************************************************************** - * Name: esp32s3_periph_wifi_bt_common_module_disable - * - * Description: - * Disable Wi-Fi and BT common module. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_periph_wifi_bt_common_module_disable(void); - -/**************************************************************************** - * Name: esp32s3_perip_clk_init - * - * Description: - * This function disables clock of useless peripherals when cpu starts. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_perip_clk_init(void); - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PERIPH_H */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_pm.c b/arch/xtensa/src/esp32s3/esp32s3_pm.c new file mode 100644 index 0000000000000..b89aadb405099 --- /dev/null +++ b/arch/xtensa/src/esp32s3/esp32s3_pm.c @@ -0,0 +1,1158 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/esp32s3_pm.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#ifdef CONFIG_PM + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "chip.h" +#include "xtensa.h" +#include "hardware/esp32s3_rtccntl.h" +#include "hardware/esp32s3_system.h" +#include "hardware/esp32s3_syscon.h" +#include "hardware/esp32s3_soc.h" +#include "hardware/esp32s3_uart.h" +#include "hardware/esp32s3_gpio.h" + +#include "esp32s3_rtc.h" +#include "esp32s3_pm.h" + +#include "soc/periph_defs.h" +#include "hal/clk_gate_ll.h" +#include "esp_private/esp_clk.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If light sleep time is less than that, don't power down flash */ + +#define FLASH_PD_MIN_SLEEP_TIME_US (2000) + +/* Minimal amount of time we can sleep for. */ + +#define LIGHT_SLEEP_MIN_TIME_US (200) + +#define RTC_MODULE_SLEEP_PREPARE_CYCLES (6) + +/* Time from VDD_SDIO power up to first flash read in ROM code */ + +#define VDD_SDIO_POWERUP_TO_FLASH_READ_US (700) + +/* Extra time it takes to enter and exit light sleep and deep sleep */ + +#define LIGHT_SLEEP_TIME_OVERHEAD_US (133) + +#ifdef CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ +#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ +#else +#define DEFAULT_CPU_FREQ_MHZ (160) +#endif + +#define DEFAULT_SLEEP_OUT_OVERHEAD_US (382) +#define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / DEFAULT_CPU_FREQ_MHZ) + +#define DEEP_SLEEP_WAKEUP_DELAY (2000) + +#define RTC_VDDSDIO_TIEH_1_8V 0 /* TIEH field value for 1.8V VDDSDIO */ +#define RTC_VDDSDIO_TIEH_3_3V 1 /* TIEH field value for 3.3V VDDSDIO */ + +#define RTC_GPIO_TRIG_EN BIT(2) /* GPIO wakeup */ +#define RTC_TIMER_TRIG_EN BIT(3) /* Timer wakeup */ +#define RTC_WIFI_TRIG_EN BIT(5) /* Wi-Fi wakeup (light sleep only) */ +#define RTC_UART0_TRIG_EN BIT(6) /* UART0 wakeup (light sleep only) */ +#define RTC_UART1_TRIG_EN BIT(7) /* UART1 wakeup (light sleep only) */ +#define RTC_BT_TRIG_EN BIT(10) /* BT wakeup (light sleep only) */ +#define RTC_XTAL32K_DEAD_TRIG_EN BIT(12) +#define RTC_USB_TRIG_EN BIT(14) +#define RTC_BROWNOUT_DET_TRIG_EN BIT(16) + +#define PERIPH_INFORM_OUT_SLEEP_OVERHEAD_NO (1) +#define PERIPH_SKIP_SLEEP_NO (1) + +#define UART_FSM_IDLE (0x0) +#define UART_FSM_TX_WAIT_SEND (0xf) + +#define ESP32S3_NUARTS (3) /* UART0-2 */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Power down options */ + +enum esp32s3_sleep_pd_option_e +{ + /* Power down the power domain in sleep mode */ + + ESP_PD_OPTION_OFF, + + /* Keep power domain enabled during sleep mode */ + + ESP_PD_OPTION_ON, + + /* Keep power domain enabled in sleep mode if it is needed + * by one of the wakeup options, otherwise power it down. + */ + + ESP_PD_OPTION_AUTO +}; + +/* Power domains which can be powered down in sleep mode. */ + +enum esp32s3_sleep_pd_domain_e +{ + ESP_PD_DOMAIN_RTC_PERIPH = 0, /* RTC IO, sensors */ + ESP_PD_DOMAIN_RTC_SLOW_MEM, /* RTC slow memory */ + ESP_PD_DOMAIN_RTC_FAST_MEM, /* RTC fast memory */ + ESP_PD_DOMAIN_XTAL, /* XTAL oscillator */ + ESP_PD_DOMAIN_CPU, /* CPU core */ + ESP_PD_DOMAIN_RTC8M, /* Internal 8M oscillator */ + ESP_PD_DOMAIN_VDDSDIO, /* VDD_SDIO */ + ESP_PD_DOMAIN_MAX /* Number of domains */ +}; + +/* Internal structure which holds all requested deep sleep parameters. */ + +struct esp32s3_sleep_config_s +{ + enum esp32s3_sleep_pd_option_e pd_options[ESP_PD_DOMAIN_MAX]; + uint64_t sleep_duration; + uint32_t wakeup_triggers : 15; + uint32_t ext1_trigger_mode : 1; + uint32_t ext1_rtc_gpio_mask : 22; + uint32_t ext0_trigger_level : 1; + uint32_t ext0_rtc_gpio_num : 5; + uint32_t gpio_wakeup_mask : 6; + uint32_t gpio_trigger_mode : 6; + uint32_t sleep_time_adjustment; + uint32_t ccount_ticks_record; + uint32_t sleep_time_overhead_out; + uint32_t rtc_clk_cal_period; + uint64_t rtc_ticks_at_sleep_start; +}; + +/* Structure describing vddsdio configuration. */ + +struct esp32s3_rtc_vddsdio_config_s +{ + uint32_t force : 1; /* If 1, use configuration from RTC registers; + * if 0, use EFUSE/bootstrapping pins. + */ + uint32_t enable : 1; /* Enable VDDSDIO regulator */ + uint32_t tieh : 1; /* Select VDDSDIO voltage. One of + * RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V + */ + uint32_t drefh : 2; /* Tuning parameter for VDDSDIO regulator */ + uint32_t drefm : 2; /* Tuning parameter for VDDSDIO regulator */ + uint32_t drefl : 2; /* Tuning parameter for VDDSDIO regulator */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline void IRAM_ATTR esp32s3_uart_tx_wait_idle(uint8_t uart_no); +static void IRAM_ATTR esp32s3_flush_uarts(void); +static void IRAM_ATTR esp32s3_suspend_uarts(void); +static void IRAM_ATTR esp32s3_resume_uarts(void); +static void IRAM_ATTR esp32s3_timer_wakeup_prepare(void); +static uint32_t IRAM_ATTR esp32s3_get_power_down_flags(void); +static void IRAM_ATTR esp32s3_set_vddsdio_config( + struct esp32s3_rtc_vddsdio_config_s config); +static int IRAM_ATTR esp32s3_get_vddsdio_config( + struct esp32s3_rtc_vddsdio_config_s *config); +static int IRAM_ATTR esp32s3_light_sleep_inner(uint32_t pd_flags, + uint32_t time_us, struct esp32s3_rtc_vddsdio_config_s config); +static int IRAM_ATTR esp32s3_sleep_start(uint32_t pd_flags); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct esp32s3_sleep_config_s g_config = +{ + .pd_options = + { ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, + ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, + ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, + ESP_PD_OPTION_AUTO + }, + .ccount_ticks_record = 0, + .sleep_time_overhead_out = DEFAULT_SLEEP_OUT_OVERHEAD_US, + .wakeup_triggers = 0 +}; + +static _Atomic uint32_t pm_wakelock = 0; + +/* Inform peripherals of light sleep wakeup overhead time */ + +inform_out_sleep_overhead_cb_t + g_periph_inform_out_sleep_overhead_cb[PERIPH_INFORM_OUT_SLEEP_OVERHEAD_NO]; + +/* Indicates if light sleep shoule be skipped by peripherals. */ + +skip_light_sleep_cb_t g_periph_skip_sleep_cb[PERIPH_SKIP_SLEEP_NO]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Pauses execution for us microseconds. */ + +extern void esp_rom_delay_us(uint32_t us); + +/**************************************************************************** + * Name: esp32s3_uart_tx_wait_idle + * + * Description: + * Wait until uart tx full empty and the last char send ok. + * + * Input Parameters: + * uart_no - 0 for UART0, 1 for UART1, 2 for UART2 + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void IRAM_ATTR esp32s3_uart_tx_wait_idle(uint8_t uart_no) +{ + uint32_t status; + do + { + status = getreg32(UART_STATUS_REG(uart_no)); + } + while ((status & (UART_ST_UTX_OUT_M | UART_TXFIFO_CNT_M)) != 0); +} + +/**************************************************************************** + * Name: esp32s3_flush_uarts + * + * Description: + * Wait until UART0/UART1 tx full empty and the last char send ok + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32s3_flush_uarts(void) +{ + int i; + + for (i = 0; i < ESP32S3_NUARTS; ++i) + { + if (periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) + { + esp32s3_uart_tx_wait_idle(i); + } + } +} + +/**************************************************************************** + * Name: esp32s3_suspend_uarts + * + * Description: + * Suspend UART0/UART1 output + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32s3_suspend_uarts(void) +{ + int i; + uint32_t uart_fsm = 0; + + for (i = 0; i < ESP32S3_NUARTS; ++i) + { + if (!periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) + { + continue; + } + + modifyreg32(UART_FLOW_CONF_REG(i), UART_FORCE_XON, + UART_SW_FLOW_CON_EN | UART_FORCE_XOFF); + do + { + uart_fsm = REG_GET_FIELD(UART_STATUS_REG(i), UART_ST_UTX_OUT); + } + while (!(uart_fsm == UART_FSM_IDLE || + uart_fsm == UART_FSM_TX_WAIT_SEND)); + } +} + +/**************************************************************************** + * Name: esp32s3_resume_uarts + * + * Description: + * Re-enable UART0/UART1/UART2 output + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32s3_resume_uarts(void) +{ + int i; + + for (i = 0; i < ESP32S3_NUARTS; ++i) + { + if (!periph_ll_periph_enabled(PERIPH_UART0_MODULE + i)) + { + continue; + } + + modifyreg32(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF, 0); + modifyreg32(UART_FLOW_CONF_REG(i), 0, UART_FORCE_XON); + modifyreg32(UART_FLOW_CONF_REG(i), UART_SW_FLOW_CON_EN | + UART_FORCE_XON, 0); + } +} + +/**************************************************************************** + * Name: esp32s3_get_power_down_flags + * + * Description: + * Get power domains that can be powered down + * + * Input Parameters: + * None + * + * Returned Value: + * Power domains + * + ****************************************************************************/ + +static uint32_t IRAM_ATTR esp32s3_get_power_down_flags(void) +{ + uint32_t pd_flags = 0; + + g_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] = ESP_PD_OPTION_ON; + + if (g_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] == ESP_PD_OPTION_AUTO) + { + if (g_config.wakeup_triggers & RTC_GPIO_TRIG_EN) + { + g_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = + ESP_PD_OPTION_ON; + } + else + { + g_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = + ESP_PD_OPTION_OFF; + } + } + + g_config.pd_options[ESP_PD_DOMAIN_CPU] = ESP_PD_OPTION_ON; + + /* Prepare flags based on the selected options */ + + if (g_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] != ESP_PD_OPTION_ON) + { + pd_flags |= RTC_SLEEP_PD_RTC_FAST_MEM; + } + + if (g_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] != ESP_PD_OPTION_ON) + { + pd_flags |= RTC_SLEEP_PD_RTC_SLOW_MEM; + } + + if (g_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) + { + pd_flags |= RTC_SLEEP_PD_RTC_PERIPH; + } + + if (g_config.pd_options[ESP_PD_DOMAIN_CPU] != ESP_PD_OPTION_ON) + { + pd_flags |= RTC_SLEEP_PD_CPU; + } + + if (g_config.pd_options[ESP_PD_DOMAIN_RTC8M] != ESP_PD_OPTION_ON) + { + pd_flags |= RTC_SLEEP_PD_INT_8M; + } + + if (g_config.pd_options[ESP_PD_DOMAIN_XTAL] != ESP_PD_OPTION_ON) + { + pd_flags |= RTC_SLEEP_PD_XTAL; + } + + g_config.pd_options[ESP_PD_DOMAIN_VDDSDIO] = ESP_PD_OPTION_ON; + + return pd_flags; +} + +/**************************************************************************** + * Name: esp32s3_timer_wakeup_prepare + * + * Description: + * Configure timer to wake-up + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32s3_timer_wakeup_prepare(void) +{ + int64_t ticks; + int64_t sleep_duration = (int64_t)g_config.sleep_duration - + (int64_t)g_config.sleep_time_adjustment; + if (sleep_duration < 0) + { + sleep_duration = 0; + } + + ticks = esp32s3_rtc_time_us_to_slowclk(sleep_duration, + g_config.rtc_clk_cal_period); + esp32s3_rtc_sleep_set_wakeup_time(g_config.rtc_ticks_at_sleep_start + + ticks); +} + +/**************************************************************************** + * Name: esp32s3_set_vddsdio_config + * + * Description: + * Set new VDDSDIO configuration using RTC registers. + * + * Input Parameters: + * config - New VDDSDIO configuration + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32s3_set_vddsdio_config( + struct esp32s3_rtc_vddsdio_config_s config) +{ + uint32_t val = 0; + val |= (config.force << RTC_CNTL_SDIO_FORCE_S); + val |= (config.enable << RTC_CNTL_XPD_SDIO_REG_S); + val |= (config.drefh << RTC_CNTL_DREFH_SDIO_S); + val |= (config.drefm << RTC_CNTL_DREFM_SDIO_S); + val |= (config.drefl << RTC_CNTL_DREFL_SDIO_S); + val |= (config.tieh << RTC_CNTL_SDIO_TIEH_S); + val |= RTC_CNTL_SDIO_REG_PD_EN; + putreg32((uint32_t)val, RTC_CNTL_RTC_SDIO_CONF_REG); +} + +/**************************************************************************** + * Name: esp32s3_get_vddsdio_config + * + * Description: + * Get current VDDSDIO configuration. + * + * Input Parameters: + * config - Incoming parameter address of VDDSDIO configuration to be saved + * + * Returned Value: + * Zero (OK) is returned on success. + * + ****************************************************************************/ + +static int IRAM_ATTR esp32s3_get_vddsdio_config( + struct esp32s3_rtc_vddsdio_config_s *config) +{ + struct esp32s3_rtc_vddsdio_config_s *result = config; + uint32_t strap_reg; + uint32_t sdio_conf_reg = getreg32(RTC_CNTL_RTC_SDIO_CONF_REG); + + result->drefh = (sdio_conf_reg & RTC_CNTL_DREFH_SDIO_M) + >> RTC_CNTL_DREFH_SDIO_S; + result->drefm = (sdio_conf_reg & RTC_CNTL_DREFM_SDIO_M) + >> RTC_CNTL_DREFM_SDIO_S; + result->drefl = (sdio_conf_reg & RTC_CNTL_DREFL_SDIO_M) + >> RTC_CNTL_DREFL_SDIO_S; + + if (sdio_conf_reg & RTC_CNTL_SDIO_FORCE) + { + /* Get configuration from RTC */ + + result->force = 1; + result->enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M) + >> RTC_CNTL_XPD_SDIO_REG_S; + result->tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) + >> RTC_CNTL_SDIO_TIEH_S; + + return OK; + } + + /* Otherwise, VDD_SDIO is controlled by bootstrapping pin */ + + strap_reg = getreg32(GPIO_STRAP_REG); + result->force = 0; + result->tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V + : RTC_VDDSDIO_TIEH_3_3V; + result->enable = 1; + + return OK; +} + +/**************************************************************************** + * Name: esp32s3_sleep_start + * + * Description: + * Enter low power mode. + * + * Input Parameters: + * pd_flags - Power domains + * + * Returned Value: + * 0 is returned on success or a negated errno value is returned + * + ****************************************************************************/ + +static int IRAM_ATTR esp32s3_sleep_start(uint32_t pd_flags) +{ + int result; + struct esp32s3_cpu_freq_config_s cpu_freq_config; + bool deep_sleep = pd_flags & RTC_SLEEP_PD_DIG; + + /* Stop UART output so that output is not lost due to APB frequency change. + * For light sleep, suspend UART output - it will resume after wakeup. + * For deep sleep, wait for the contents of UART FIFO to be sent. + */ + + if (deep_sleep == true) + { + esp32s3_flush_uarts(); + } + else + { + esp32s3_suspend_uarts(); + } + + /* Save current frequency and switch to XTAL */ + + esp32s3_rtc_clk_cpu_freq_get_config(&cpu_freq_config); + esp32s3_rtc_cpu_freq_set_xtal(); + + /* Enter sleep */ + + esp32s3_rtc_sleep_init(pd_flags | RTC_SLEEP_NO_ULTRA_LOW); + + /* Set state machine time for light sleep */ + + if (deep_sleep == false) + { + esp32s3_rtc_sleep_low_init(g_config.rtc_clk_cal_period); + } + + /* Configure timer wakeup */ + + if (g_config.wakeup_triggers & RTC_TIMER_TRIG_EN) + { + esp32s3_timer_wakeup_prepare(); + } + + result = esp32s3_rtc_sleep_start(g_config.wakeup_triggers, 0); + + /* Restore CPU frequency */ + + esp32s3_rtc_clk_cpu_freq_set_config(&cpu_freq_config); + + if (deep_sleep == false) + { + g_config.ccount_ticks_record = XTHAL_GET_CCOUNT(); + } + + /* Re-enable UART output */ + + esp32s3_resume_uarts(); + + return result; +} + +/**************************************************************************** + * Name: esp32s3_light_sleep_inner + * + * Description: + * Enter low power mode, then wait for flash to be ready on wakeup + * + * Input Parameters: + * pd_flags - Power domains + * time_us - Time to wait for spi_flash become ready + * config - VDDSDIO configuration + * + * Returned Value: + * 0 is returned on success or a negated errno value is returned + * + ****************************************************************************/ + +static int IRAM_ATTR esp32s3_light_sleep_inner(uint32_t pd_flags, + uint32_t time_us, struct esp32s3_rtc_vddsdio_config_s config) +{ + /* Enter sleep */ + + int err = esp32s3_sleep_start(pd_flags); + + /* If VDDSDIO regulator was controlled by RTC registers before sleep. + * restore the configuration. + */ + + if (config.force) + { + esp32s3_set_vddsdio_config(config); + } + + /* If SPI flash was powered down, wait for it to become ready. */ + + if (pd_flags & RTC_SLEEP_PD_VDDSDIO) + { + /* Wait for the flash chip to start up. */ + + esp_rom_delay_us(time_us); + } + + return err; +} + +/**************************************************************************** + * Name: esp32s3_periph_should_skip_sleep + * + * Description: + * Indicates if light sleep shoule be skipped by peripherals + * + * Input Parameters: + * None + * + * Returned Value: + * True is returned on success. Otherwise false. + * + ****************************************************************************/ + +static inline bool IRAM_ATTR esp32s3_periph_should_skip_sleep(void) +{ + for (int i = 0; i < PERIPH_SKIP_SLEEP_NO; i++) + { + if (g_periph_skip_sleep_cb[i]) + { + if (g_periph_skip_sleep_cb[i]() == true) + { + return true; + } + } + } + + return false; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s3_pm_register_skip_sleep_callback + * + * Description: + * Unregister callback function of skipping light sleep. + * + * Input Parameters: + * cb - Callback function + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32s3_pm_register_skip_sleep_callback(skip_light_sleep_cb_t cb) +{ + for (int i = 0; i < PERIPH_SKIP_SLEEP_NO; i++) + { + if (g_periph_skip_sleep_cb[i] == cb) + { + return OK; + } + else if (g_periph_skip_sleep_cb[i] == NULL) + { + g_periph_skip_sleep_cb[i] = cb; + return OK; + } + } + + return ERROR; +} + +/**************************************************************************** + * Name: esp32s3_pm_unregister_skip_sleep_callback + * + * Description: + * Register callback function of skipping light sleep. + * + * Input Parameters: + * cb - Callback function + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32s3_pm_unregister_skip_sleep_callback(skip_light_sleep_cb_t cb) +{ + for (int i = 0; i < PERIPH_SKIP_SLEEP_NO; i++) + { + if (g_periph_skip_sleep_cb[i] == cb) + { + g_periph_skip_sleep_cb[i] = NULL; + return OK; + } + } + + return ERROR; +} + +/**************************************************************************** + * Name: esp32s3_should_skip_light_sleep + * + * Description: + * Indicates if light sleep shoule be skipped. + * + * Input Parameters: + * None + * + * Returned Value: + * True is returned on success. Otherwise false. + * + ****************************************************************************/ + +bool IRAM_ATTR esp32s3_should_skip_light_sleep(void) +{ + if (esp32s3_periph_should_skip_sleep() == true) + { + return true; + } + + return false; +} + +/**************************************************************************** + * Name: esp32s3_pm_register_inform_out_sleep_overhead_callback + * + * Description: + * Register informing peripherals of light sleep wakeup overhead time + * callback function. + * + * Input Parameters: + * cb - Callback function + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32s3_pm_register_inform_out_sleep_overhead_callback( + inform_out_sleep_overhead_cb_t cb) +{ + for (int i = 0; i < PERIPH_INFORM_OUT_SLEEP_OVERHEAD_NO; i++) + { + if (g_periph_inform_out_sleep_overhead_cb[i] == cb) + { + return ERROR; + } + else if (g_periph_inform_out_sleep_overhead_cb[i] == NULL) + { + g_periph_inform_out_sleep_overhead_cb[i] = cb; + return OK; + } + } + + return ERROR; +} + +/**************************************************************************** + * Name: esp32s3_pm_unregister_inform_out_sleep_overhead_callback + * + * Description: + * Unregister informing peripherals of light sleep wakeup overhead time + * callback function. + * + * Input Parameters: + * cb - Callback function + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32s3_pm_unregister_inform_out_sleep_overhead_callback( + inform_out_sleep_overhead_cb_t cb) +{ + for (int i = 0; i < PERIPH_INFORM_OUT_SLEEP_OVERHEAD_NO; i++) + { + if (g_periph_inform_out_sleep_overhead_cb[i] == cb) + { + g_periph_inform_out_sleep_overhead_cb[i] = NULL; + return OK; + } + } + + return ERROR; +} + +/**************************************************************************** + * Name: esp32s3_periph_inform_out_sleep_overhead + * + * Description: + * Inform peripherals of light sleep wakeup overhead time + * + * Input Parameters: + * us - Light sleep wakeup overhead time + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s3_periph_inform_out_sleep_overhead(uint32_t us) +{ + for (int i = 0; i < PERIPH_INFORM_OUT_SLEEP_OVERHEAD_NO; i++) + { + if (g_periph_inform_out_sleep_overhead_cb[i]) + { + g_periph_inform_out_sleep_overhead_cb[i](us); + } + } +} + +/**************************************************************************** + * Name: esp32s3_sleep_enable_timer_wakeup + * + * Description: + * Enable wakeup by timer + * + * Input Parameters: + * time_in_us - Configure wake-up time interval + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s3_sleep_enable_timer_wakeup(uint64_t time_in_us) +{ + g_config.wakeup_triggers |= RTC_TIMER_TRIG_EN; + g_config.sleep_duration = time_in_us; +} + +/**************************************************************************** + * Name: esp32s3_sleep_enable_wifi_wakeup + * + * Description: + * Configure Wi-Fi wake-up source + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s3_sleep_enable_wifi_wakeup(void) +{ + g_config.wakeup_triggers |= RTC_WIFI_TRIG_EN; +} + +/**************************************************************************** + * Name: esp32s3_light_sleep_start + * + * Description: + * Enter light sleep mode + * + * Input Parameters: + * sleep_time - Actual sleep time + * + * Returned Value: + * 0 is returned on success or a negated errno value is returned + * + ****************************************************************************/ + +int IRAM_ATTR esp32s3_light_sleep_start(uint64_t *sleep_time) +{ + int ret = OK; + irqstate_t flags; + uint32_t pd_flags; + uint32_t flash_enable_time_us; + uint32_t vddsdio_pd_sleep_duration; + struct esp32s3_rtc_vddsdio_config_s vddsdio_config; + uint32_t rtc_cntl_xtl_buf_wait_cycles; + uint32_t sleep_time_overhead_in; + uint32_t ccount_at_sleep_start; + int64_t final_sleep_us; + int64_t min_sleep_us; + + flags = enter_critical_section(); + + g_config.ccount_ticks_record = XTHAL_GET_CCOUNT(); + g_config.rtc_ticks_at_sleep_start = esp32s3_rtc_time_get(); + ccount_at_sleep_start = XTHAL_GET_CCOUNT(); + sleep_time_overhead_in = (ccount_at_sleep_start - + g_config.ccount_ticks_record) / (esp_clk_cpu_freq() / 1000000ULL); + + /* Decide which power domains can be powered down */ + + pd_flags = esp32s3_get_power_down_flags(); + pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH; + g_config.rtc_clk_cal_period = + esp32s3_rtc_clk_cal(RTC_CAL_RTC_MUX, RTC_CLK_SRC_CAL_CYCLES); + + /* Adjustment time consists of parts below: + * 1. Hardware time waiting for internal 8M oscilate clock and XTAL; + * 2. Hardware state swithing time of the rtc main state machine; + * 3. Code execution time when clock is not stable; + * 4. Code execution time which can be measured; + */ + + rtc_cntl_xtl_buf_wait_cycles = esp32s3_rtc_time_us_to_slowclk( + RTC_CNTL_XTL_BUF_WAIT_SLP_US, g_config.rtc_clk_cal_period); + + g_config.sleep_time_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US + + sleep_time_overhead_in + g_config.sleep_time_overhead_out + + esp32s3_rtc_time_slowclk_to_us(rtc_cntl_xtl_buf_wait_cycles + + RTC_CNTL_CK8M_WAIT_SLP_CYCLES + RTC_CNTL_WAKEUP_DELAY_CYCLES, + g_config.rtc_clk_cal_period); + + flash_enable_time_us = VDD_SDIO_POWERUP_TO_FLASH_READ_US + + DEEP_SLEEP_WAKEUP_DELAY; + + esp32s3_periph_inform_out_sleep_overhead( + g_config.sleep_time_adjustment - sleep_time_overhead_in); + + esp32s3_get_vddsdio_config(&vddsdio_config); + + final_sleep_us = (int64_t)g_config.sleep_duration - + (int64_t)g_config.sleep_time_adjustment; + min_sleep_us = esp32s3_rtc_time_slowclk_to_us(RTC_CNTL_MIN_SLP_VAL_MIN, + g_config.rtc_clk_cal_period); + + /* If rtc timer wakeup source is enabled, need to compare final + * sleep duration and min sleep duration to avoid late wakeup + */ + + if ((g_config.wakeup_triggers & RTC_TIMER_TRIG_EN) && + (final_sleep_us <= min_sleep_us)) + { + ret = ERROR; + } + else + { + /* Enter sleep, then wait for flash to be ready on wakeup */ + + ret = esp32s3_light_sleep_inner(pd_flags, flash_enable_time_us, + vddsdio_config); + } + + if (sleep_time != NULL) + { + *sleep_time = esp32s3_rtc_time_slowclk_to_us(esp32s3_rtc_time_get() - + g_config.rtc_ticks_at_sleep_start, g_config.rtc_clk_cal_period); + } + + g_config.sleep_time_overhead_out = (XTHAL_GET_CCOUNT() - + g_config.ccount_ticks_record) / (esp_clk_cpu_freq() / 1000000ULL); + + leave_critical_section(flags); + + return ret; +} + +/**************************************************************************** + * Name: esp32s3_pmstandby + * + * Description: + * Enter force sleep. + * + * Input Parameters: + * time_in_us - Force sleep time interval + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s3_pmstandby(uint64_t time_in_us) +{ + uint64_t rtc_diff_us; + + /* Don't power down XTAL - powering it up takes different time on. */ + + esp32s3_sleep_enable_timer_wakeup(time_in_us); + esp32s3_light_sleep_start(&rtc_diff_us); + pwrinfo("Returned from auto-sleep, slept for %" PRIu32 " ms\n", + (uint32_t)(rtc_diff_us) / 1000); +} + +/**************************************************************************** + * Name: esp32s3_deep_sleep_start + * + * Description: + * Enter deep sleep mode + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s3_deep_sleep_start(void) +{ + uint32_t pd_flags; + + /* Record current RTC time */ + + g_config.rtc_ticks_at_sleep_start = esp32s3_rtc_time_get(); + + /* Decide which power domains can be powered down */ + + pd_flags = esp32s3_get_power_down_flags(); + g_config.rtc_clk_cal_period = getreg32(RTC_SLOW_CLK_CAL_REG); + + /* Correct the sleep time */ + + g_config.sleep_time_adjustment = DEEP_SLEEP_TIME_OVERHEAD_US; + + pd_flags |= RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_VDDSDIO | + RTC_SLEEP_PD_INT_8M | RTC_SLEEP_PD_XTAL; + + /* Enter deep sleep */ + + esp32s3_sleep_start(pd_flags); + + /* Because RTC is in a slower clock domain than the CPU, it + * can take several CPU cycles for the sleep mode to start. + */ + + while (1); +} + +/**************************************************************************** + * Name: esp32s3_pmsleep + * + * Description: + * Enter deep sleep. + * + * Input Parameters: + * time_in_us - Deep sleep time interval + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s3_pmsleep(uint64_t time_in_us) +{ + esp32s3_sleep_enable_timer_wakeup(time_in_us); + esp32s3_deep_sleep_start(); +} + +/**************************************************************************** + * Name: esp32s3_pm_lockacquire + * + * Description: + * Take a power management lock + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s3_pm_lockacquire(void) +{ + ++pm_wakelock; +} + +/**************************************************************************** + * Name: esp32s3_pm_lockrelease + * + * Description: + * Release the lock taken using esp32s3_pm_lockacquire. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s3_pm_lockrelease(void) +{ + --pm_wakelock; +} + +/**************************************************************************** + * Name: esp32s3_pm_lockstatus + * + * Description: + * Return power management lock status. + * + * Input Parameters: + * None + * + * Returned Value: + * Current pm_wakelock count + * + ****************************************************************************/ + +uint32_t IRAM_ATTR esp32s3_pm_lockstatus(void) +{ + return pm_wakelock; +} + +#endif /* CONFIG_PM */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_pm.h b/arch/xtensa/src/esp32s3/esp32s3_pm.h new file mode 100644 index 0000000000000..00076170a3dde --- /dev/null +++ b/arch/xtensa/src/esp32s3/esp32s3_pm.h @@ -0,0 +1,302 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/esp32s3_pm.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PM_H +#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#ifdef CONFIG_PM + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Callback function type for peripherals to + * know light sleep wakeup overhead. + */ + +typedef void (*inform_out_sleep_overhead_cb_t)(uint32_t); + +/* Callback function type for peripherals to skip light sleep. */ + +typedef bool (*skip_light_sleep_cb_t)(void); + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s3_sleep_enable_timer_wakeup + * + * Description: + * Configure wake-up interval + * + * Input Parameters: + * time_in_us - Configure wake-up time interval + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s3_sleep_enable_timer_wakeup(uint64_t time_in_us); + +/**************************************************************************** + * Name: esp32s3_light_sleep_start + * + * Description: + * Enter light sleep mode + * + * Input Parameters: + * sleep_time - Actual sleep time + * + * Returned Value: + * 0 is returned on success or a negated errno value is returned + * + ****************************************************************************/ + +int esp32s3_light_sleep_start(uint64_t *sleep_time); + +/**************************************************************************** + * Name: esp32s3_pmstandby + * + * Description: + * Enter force sleep time interval. + * + * Input Parameters: + * time_in_us - Force sleep time interval + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s3_pmstandby(uint64_t time_in_us); + +/**************************************************************************** + * Name: esp32s3_deep_sleep_start + * + * Description: + * Enter deep sleep mode + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s3_deep_sleep_start(void); + +/**************************************************************************** + * Name: esp32s3_pmsleep + * + * Description: + * Enter deep sleep. + * + * Input Parameters: + * time_in_us - Deep sleep time interval + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s3_pmsleep(uint64_t time_in_us); + +/**************************************************************************** + * Name: esp32s3_pm_lockacquire + * + * Description: + * Take a power management lock + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s3_pm_lockacquire(void); + +/**************************************************************************** + * Name: esp32s3_pm_lockrelease + * + * Description: + * Release the lock taken using esp32s3_pm_lockacquire. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s3_pm_lockrelease(void); + +/**************************************************************************** + * Name: esp32s3_pm_lockstatus + * + * Description: + * Return power management lock status. + * + * Input Parameters: + * None + * + * Returned Value: + * Current pm_wakelock count + * + ****************************************************************************/ + +uint32_t esp32s3_pm_lockstatus(void); + +/**************************************************************************** + * Name: esp32s3_sleep_enable_wifi_wakeup + * + * Description: + * Configure Wi-Fi wake-up source + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s3_sleep_enable_wifi_wakeup(void); + +/**************************************************************************** + * Name: esp32s3_should_skip_light_sleep + * + * Description: + * Indicates if light sleep shoule be skipped. + * + * Input Parameters: + * None + * + * Returned Value: + * True is returned on success. Otherwise false. + * + ****************************************************************************/ + +bool esp32s3_should_skip_light_sleep(void); + +/**************************************************************************** + * Name: esp32s3_pm_register_inform_out_sleep_overhead_callback + * + * Description: + * Register informing peripherals of light sleep wakeup overhead time + * callback function. + * + * Input Parameters: + * cb - Callback function + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32s3_pm_register_inform_out_sleep_overhead_callback( + inform_out_sleep_overhead_cb_t cb); + +/**************************************************************************** + * Name: esp32s3_pm_unregister_inform_out_sleep_overhead_callback + * + * Description: + * Unregister informing peripherals of light sleep wakeup overhead time + * callback function. + * + * Input Parameters: + * cb - Callback function + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32s3_pm_unregister_inform_out_sleep_overhead_callback( + inform_out_sleep_overhead_cb_t cb); + +/**************************************************************************** + * Name: esp32s3_pm_register_skip_sleep_callback + * + * Description: + * Unregister callback function of skipping light sleep. + * + * Input Parameters: + * cb - Callback function + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32s3_pm_register_skip_sleep_callback(skip_light_sleep_cb_t cb); + +/**************************************************************************** + * Name: esp32s3_pm_unregister_skip_sleep_callback + * + * Description: + * Register callback function of skipping light sleep. + * + * Input Parameters: + * cb - Callback function + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR). + * + ****************************************************************************/ + +int esp32s3_pm_unregister_skip_sleep_callback(skip_light_sleep_cb_t cb); + +#endif /* CONFIG_PM */ + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_PM_H */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_pminitialize.c b/arch/xtensa/src/esp32s3/esp32s3_pminitialize.c new file mode 100644 index 0000000000000..9b759c9056124 --- /dev/null +++ b/arch/xtensa/src/esp32s3/esp32s3_pminitialize.c @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/esp32s3_pminitialize.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#ifdef CONFIG_PM + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xtensa_pminitialize + * + * Description: + * Initialize the power management subsystem. + * + ****************************************************************************/ + +void xtensa_pminitialize(void) +{ + /* Initialize the NuttX power management subsystem proper */ + + pm_initialize(); +} + +#endif /* CONFIG_PM */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_psram_octal.c b/arch/xtensa/src/esp32s3/esp32s3_psram_octal.c index 675fa14e448f7..75d10b2c9e9ec 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_psram_octal.c +++ b/arch/xtensa/src/esp32s3/esp32s3_psram_octal.c @@ -33,13 +33,12 @@ #include "esp32s3_psram.h" #include "esp32s3_spi_timing.h" -#include "hardware/esp32s3_spi_mem_reg.h" #include "hardware/esp32s3_iomux.h" #include "hardware/esp32s3_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #include "hardware/esp32s3_syscon.h" #include "rom/esp32s3_spiflash.h" -#include "rom/esp32s3_opi_flash.h" +#include "rom/opi_flash.h" /**************************************************************************** * Pre-processor Definitions @@ -600,7 +599,7 @@ static void IRAM_ATTR config_psram_spi_phases(void) * ****************************************************************************/ -static inline void spi_flash_set_rom_required_regs(void) +void IRAM_ATTR spi_flash_set_rom_required_regs(void) { #ifdef CONFIG_ESP32S3_FLASH_MODE_OCT diff --git a/arch/xtensa/src/esp32s3/esp32s3_psram_quad.c b/arch/xtensa/src/esp32s3/esp32s3_psram_quad.c index 98e2a2e16aafc..81159dd378452 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_psram_quad.c +++ b/arch/xtensa/src/esp32s3/esp32s3_psram_quad.c @@ -31,11 +31,10 @@ #include "esp32s3_psram.h" #include "esp32s3_spi_timing.h" -#include "rom/esp32s3_spiflash.h" -#include "rom/esp32s3_opi_flash.h" -#include "hardware/esp32s3_spi_mem_reg.h" #include "hardware/esp32s3_iomux.h" #include "hardware/esp32s3_gpio_sigmap.h" +#include "rom/esp32s3_spiflash.h" +#include "rom/opi_flash.h" /* EFUSE */ @@ -148,6 +147,16 @@ static void psram_set_op_mode(int spi_num, int mode) } } +/* Redefine external struct members name */ + +#define addr_bit_len addrBitLen +#define cmd_bit_len cmdBitLen +#define dummy_bit_len dummyBitLen +#define tx_data txData +#define tx_data_bit_len txDataBitLen +#define rx_data rxData +#define rx_data_bit_len rxDataBitLen + static void _psram_exec_cmd(int spi_num, uint32_t cmd, int cmd_bit_len, uint32_t addr, int addr_bit_len, @@ -388,7 +397,7 @@ static void psram_gpio_config(void) int psram_enable(int mode, int vaddrmode) { - assert(mode < PSRAM_CACHE_MAX && \ + ASSERT(mode < PSRAM_CACHE_MAX && \ "we don't support any other mode for now."); psram_gpio_config(); diff --git a/arch/xtensa/src/esp32s3/esp32s3_qspi.c b/arch/xtensa/src/esp32s3/esp32s3_qspi.c index 544dfc4607393..15b1df582f678 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_qspi.c +++ b/arch/xtensa/src/esp32s3/esp32s3_qspi.c @@ -992,7 +992,7 @@ static int esp32s3_qspi_memory(struct qspi_dev_s *dev, QSPI_DMA_DESC_NUM, (uint8_t *)meminfo->buffer, meminfo->buflen, - true); + true, priv->dma_channel); esp32s3_dma_load(priv->dma_desc, priv->dma_channel, true); esp32s3_dma_enable(priv->dma_channel, true); } @@ -1008,7 +1008,7 @@ static int esp32s3_qspi_memory(struct qspi_dev_s *dev, QSPI_DMA_DESC_NUM, (uint8_t *)meminfo->buffer, meminfo->buflen, - false); + false, priv->dma_channel); esp32s3_dma_load(priv->dma_desc, priv->dma_channel, false); esp32s3_dma_enable(priv->dma_channel, false); } diff --git a/arch/xtensa/src/esp32s3/esp32s3_rng.c b/arch/xtensa/src/esp32s3/esp32s3_rng.c index 6164b40cf952b..63f1e891f9ebe 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_rng.c +++ b/arch/xtensa/src/esp32s3/esp32s3_rng.c @@ -41,10 +41,12 @@ #include #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "hardware/wdev_reg.h" #include "esp32s3_clockconfig.h" +#include "esp_random.h" + #if defined(CONFIG_ESP32S3_RNG) #if defined(CONFIG_DEV_RANDOM) || defined(CONFIG_DEV_URANDOM_ARCH) @@ -83,52 +85,6 @@ static const struct file_operations g_rngops = * Private functions ****************************************************************************/ -/**************************************************************************** - * Name: esp32s3_random - * - * Description: - * Read a random number (unsigned int 32-bit) from ESP32S3 PRNG. - * - * Input Parameters: - * none - * - * Returned Value: - * A uint32_t random number. - * - ****************************************************************************/ - -uint32_t IRAM_ATTR esp_random(void) -{ - /* The PRNG which implements WDEV_RANDOM register gets 2 bits - * of extra entropy from a hardware randomness source every APB clock cycle - * (provided Wi-Fi or BT are enabled). To make sure entropy is not drained - * faster than it is added, this function needs to wait for at least 1778 - * APB clock cycles after reading previous word. This implementation may - * actually wait a bit longer due to extra time spent in arithmetic and - * branch statements. - * - * As a (probably unnecessary) precaution to avoid returning the - * RNG state as-is, the result is XORed with additional - * WDEV_RND_REG reads while waiting. - */ - - uint32_t cpu_to_apb_freq_ratio = esp_clk_cpu_freq() / esp_clk_apb_freq(); - - static uint32_t last_ccount = 0; - uint32_t ccount; - uint32_t result = 0; - - do - { - ccount = XTHAL_GET_CCOUNT(); - result ^= getreg32(WDEV_RND_REG); - } - while (ccount - last_ccount < cpu_to_apb_freq_ratio * 1778); - - last_ccount = ccount; - return result ^ getreg32(WDEV_RND_REG); -} - /**************************************************************************** * Name: esp32s3_rng_read * diff --git a/arch/xtensa/src/esp32s3/esp32s3_rt_timer.c b/arch/xtensa/src/esp32s3/esp32s3_rt_timer.c index 33c47926b004f..ca28eb1737122 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_rt_timer.c +++ b/arch/xtensa/src/esp32s3/esp32s3_rt_timer.c @@ -33,6 +33,7 @@ #include #include +#include #include #include #include @@ -40,7 +41,7 @@ #include #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "esp32s3_irq.h" #include "esp32s3_rt_timer.h" #include "hardware/esp32s3_soc.h" @@ -369,11 +370,8 @@ static void start_rt_timer(struct rt_timer_s *timer, uint64_t timeout, bool repeat) { - irqstate_t flags; struct esp32s3_rt_priv_s *priv = &g_rt_priv; - flags = spin_lock_irqsave(&priv->lock); - /* Only idle timer can be started */ if (timer->state == RT_TIMER_IDLE) @@ -437,8 +435,6 @@ static void start_rt_timer(struct rt_timer_s *timer, { tmrwarn("Timer not in idle mode. Only idle timer can be started!\n"); } - - spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -458,11 +454,8 @@ static void start_rt_timer(struct rt_timer_s *timer, static void stop_rt_timer(struct rt_timer_s *timer) { - irqstate_t flags; struct esp32s3_rt_priv_s *priv = &g_rt_priv; - flags = spin_lock_irqsave(&priv->lock); - /* "start" function can set the timer's repeat flag, and "stop" function * should remove this flag. */ @@ -507,8 +500,6 @@ static void stop_rt_timer(struct rt_timer_s *timer) } } } - - spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -754,9 +745,16 @@ void esp32s3_rt_timer_start(struct rt_timer_s *timer, uint64_t timeout, bool repeat) { + irqstate_t flags; + struct esp32s3_rt_priv_s *priv = &g_rt_priv; + + flags = spin_lock_irqsave(&priv->lock); + stop_rt_timer(timer); start_rt_timer(timer, timeout, repeat); + + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** @@ -775,7 +773,12 @@ void esp32s3_rt_timer_start(struct rt_timer_s *timer, void esp32s3_rt_timer_stop(struct rt_timer_s *timer) { + irqstate_t flags; + struct esp32s3_rt_priv_s *priv = &g_rt_priv; + + flags = spin_lock_irqsave(&priv->lock); stop_rt_timer(timer); + spin_unlock_irqrestore(&priv->lock, flags); } /**************************************************************************** diff --git a/arch/xtensa/src/esp32s3/esp32s3_rtc.c b/arch/xtensa/src/esp32s3/esp32s3_rtc.c index fad06a91e3ac5..dd68de426344d 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_rtc.c +++ b/arch/xtensa/src/esp32s3/esp32s3_rtc.c @@ -33,6 +33,7 @@ #include "esp32s3_clockconfig.h" #include "esp32s3_rt_timer.h" +#include "esp32s3_reset_reasons.h" #include "hardware/esp32s3_bb.h" #include "hardware/esp32s3_nrx.h" @@ -44,14 +45,14 @@ #include "hardware/esp32s3_apb_ctrl.h" #include "hardware/regi2c_dig_reg.h" #include "hardware/regi2c_ctrl.h" -#include "hardware/esp32s3_spi_mem_reg.h" -#include "hardware/esp32s3_extmem.h" #include "hardware/esp32s3_syscon.h" #include "hardware/regi2c_bbpll.h" #include "hardware/regi2c_lp_bias.h" #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" +#include "soc/extmem_reg.h" +#include "soc/spi_mem_reg.h" #include "esp32s3_rtc.h" @@ -118,18 +119,24 @@ #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) -/* set sleep_init default param. */ - -#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 -#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 -#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_SLEEP_ON 0 -#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 -#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 1 -#define RTC_CNTL_PD_CUR_SLEEP_ON 0 -#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 -#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 0xf +/* Set sleep_init default param */ + +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT (5) +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP (0) +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT (14) +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_ULTRA_LOW (15) +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP (0) +#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT (1) +#define RTC_CNTL_BIASSLP_SLEEP_ON (0) +#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT (1) +#define RTC_CNTL_PD_CUR_SLEEP_ON (0) +#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT (0xf) + +#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT (0) +#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT (1) +#define RTC_CNTL_BIASSLP_MONITOR_ON (0) +#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT (1) +#define RTC_CNTL_PD_CUR_MONITOR_ON (0) /* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. @@ -164,22 +171,15 @@ .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ .bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \ .cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \ - .int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ + .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ .dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \ .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ .wdt_flashboot_mod_en = 0, \ - .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .dig_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ - : RTC_CNTL_DBIAS_SLP, \ - .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .rtc_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ - : RTC_CNTL_DBIAS_SLP, \ .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ - .xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \ + .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \ .deep_slp_reject = 1, \ - .light_slp_reject = 1 \ + .light_slp_reject = 1, \ + .rtc_dbias_slp = RTC_CNTL_DBIAS_1V10, \ } #define X32K_CONFIG_DEFAULT() { \ @@ -220,7 +220,7 @@ .xtal_fpu = 0, \ .bbpll_fpu = 0, \ .cpu_waiti_clk_gate = 1, \ - .cali_ocode = 0\ + .cali_ocode = 0 \ } /* The magic data for the struct esp32s3_rtc_backup_s that is in RTC slow @@ -276,12 +276,16 @@ struct esp32s3_rtc_sleep_config_s uint32_t dig_peri_pd_en : 1; /* power down digital peripherals */ uint32_t deep_slp : 1; /* power down digital domain */ uint32_t wdt_flashboot_mod_en : 1; /* enable WDT flashboot mode */ - uint32_t dig_dbias_wak : 5; /* set bias for digital domain, in active mode */ uint32_t dig_dbias_slp : 5; /* set bias for digital domain, in sleep mode */ - uint32_t rtc_dbias_wak : 5; /* set bias for RTC domain, in active mode */ uint32_t rtc_dbias_slp : 5; /* set bias for RTC domain, in sleep mode */ + uint32_t bias_sleep_monitor : 1; /* circuit control parameter, in monitor mode */ + uint32_t dbg_atten_slp : 4; /* voltage parameter, in sleep mode */ + uint32_t bias_sleep_slp : 1; /* circuit control parameter, in sleep mode */ + uint32_t pd_cur_monitor : 1; /* circuit control parameter, in monitor mode */ + uint32_t pd_cur_slp : 1; /* circuit control parameter, in sleep mode */ uint32_t vddsdio_pd_en : 1; /* power down VDDSDIO regulator */ uint32_t xtal_fpu : 1; /* keep main XTAL powered up in sleep */ + uint32_t rtc_regulator_fpu : 1; /* keep rtc regulator powered up in sleep */ uint32_t deep_slp_reject : 1; uint32_t light_slp_reject : 1; }; @@ -349,6 +353,8 @@ static RTC_DATA_ATTR struct esp32s3_rtc_backup_s rtc_saved_data; static struct esp32s3_rtc_backup_s *g_rtc_save; static bool g_rt_timer_enabled = false; +static uint32_t g_dig_dbias_pvt_non_240m = 27; +static uint32_t g_rtc_dbias_pvt_non_240m = 27; /**************************************************************************** * Private Function Prototypes @@ -407,6 +413,10 @@ extern void ets_update_cpu_frequency(uint32_t ticks_per_us); extern void esp_rom_delay_us(uint32_t us); +/* Get the reset reason for CPU. */ + +extern soc_reset_reason_t esp_rom_get_reset_reason(int cpu_no); + /**************************************************************************** * Name: esp32s3_rtc_sleep_pu * @@ -414,7 +424,7 @@ extern void esp_rom_delay_us(uint32_t us); * Configure whether certain peripherals are powered up in deep sleep. * * Input Parameters: - * cfg - power down flags as rtc_sleep_pu_config_t structure + * cfg - Power down flags as rtc_sleep_pu_config_t structure * * Returned Value: * None @@ -496,7 +506,7 @@ static void IRAM_ATTR esp32s3_rtc_clk_fast_freq_set( * These are the routines to work with such a representation. * * Input Parameters: - * val - register value + * val - Register value * * Returned Value: * true: Valid register value. @@ -517,8 +527,8 @@ static inline bool esp32s3_clk_val_is_valid(uint32_t val) * Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio * * Input Parameters: - * cal_clk - which clock to calibrate - * slowclk_cycles - number of slow clock cycles to count. + * cal_clk - Which clock to calibrate + * slowclk_cycles - Number of slow clock cycles to count. * * Returned Value: * Number of XTAL clock cycles within the given number of slow clock @@ -590,7 +600,7 @@ static uint32_t IRAM_ATTR esp32s3_rtc_clk_cal_internal( if (cal_clk == RTC_CAL_32K_XTAL || slow_freq == RTC_SLOW_FREQ_32K_XTAL) { - expected_freq = 32768; /* standard 32k XTAL */ + expected_freq = 32768; /* Standard 32k XTAL */ } else if (cal_clk == RTC_CAL_8MD256 || slow_freq == RTC_SLOW_FREQ_8MD256) { @@ -664,8 +674,8 @@ static void esp32s3_wait_dig_dbias_valid(uint64_t rtc_cycles) * Switch to XTAL frequency, does not disable the PLL * * Input Parameters: - * freq - XTAL frequency - * div - REF_TICK divider + * freq - XTAL frequency + * div - REF_TICK divider * * Returned Value: * none @@ -676,7 +686,7 @@ void IRAM_ATTR esp32s3_rtc_update_to_xtal(int freq, int div) { ets_update_cpu_frequency(freq); - /* set digital voltage for different cpu freq from xtal */ + /* Set digital voltage for different cpu freq from xtal */ if (freq <= 2) { @@ -740,7 +750,7 @@ static void IRAM_ATTR esp32s3_rtc_clk_slow_freq_set( * Enable 32 kHz XTAL oscillator * * Input Parameters: - * enable - boolean Enable/Disable + * enable - True to enable, false to disable * * Returned Value: * None @@ -781,8 +791,8 @@ static void IRAM_ATTR esp32s3_rtc_clk_32k_enable(bool enable) * Enable or disable 8 MHz internal oscillator * * Input Parameters: - * clk_8m_en - true to enable 8MHz generator, false to disable - * d256_en - true to enable /256 divider, false to disable + * clk_8m_en - True to enable 8MHz generator, false to disable + * d256_en - True to enable /256 divider, false to disable * * Returned Value: * None @@ -1225,8 +1235,8 @@ enum esp32s3_rtc_slow_freq_e IRAM_ATTR esp32s3_rtc_get_slow_clk(void) * Measure RTC slow clock's period, based on main XTAL frequency * * Input Parameters: - * cal_clk - clock to be measured - * slowclk_cycles - number of slow clock cycles to average + * cal_clk - Clock to be measured + * slowclk_cycles - Number of slow clock cycles to average * * Returned Value: * Average slow clock period in microseconds, Q13.19 fixed point format @@ -1285,7 +1295,7 @@ enum esp32s3_rtc_xtal_freq_e IRAM_ATTR esp32s3_rtc_clk_xtal_freq_get(void) * Name: esp32s3_rtc_clk_bbpll_disable * * Description: - * disable BBPLL. + * Disable BBPLL. * * Input Parameters: * None @@ -1508,17 +1518,27 @@ void esp32s3_rtc_clk_set(void) void IRAM_ATTR esp32s3_rtc_init(void) { struct esp32s3_rtc_priv_s cfg = RTC_CONFIG_DEFAULT(); + soc_reset_reason_t rst_reas = esp_rom_get_reset_reason(0); + + /* When power on, we need to set `cali_ocode` to 1, to do a OCode + * calibration, which will calibrate the rtc reference voltage to a + * tested value + */ + + if (rst_reas == RESET_REASON_CHIP_POWER_ON) + { + cfg.cali_ocode = 1; + } REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0); modifyreg32(RTC_CNTL_RTC_ANA_CONF_REG, RTC_CNTL_PVTMON_PU, 0); - modifyreg32(RTC_CNTL_RTC_TIMER1_REG, 0, - cfg.pll_wait ? RTC_CNTL_PLL_BUF_WAIT : 0); - - modifyreg32(RTC_CNTL_RTC_TIMER1_REG, 0, - cfg.ck8m_wait ? RTC_CNTL_CK8M_WAIT : 0); + REG_SET_FIELD(RTC_CNTL_RTC_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, + cfg.pll_wait); + REG_SET_FIELD(RTC_CNTL_RTC_TIMER1_REG, RTC_CNTL_CK8M_WAIT, + cfg.ck8m_wait); /* Moved from rtc sleep to rtc init to save sleep function running time */ @@ -1537,6 +1557,21 @@ void IRAM_ATTR esp32s3_rtc_init(void) REG_SET_FIELD(RTC_CNTL_RTC_TIMER3_REG, RTC_CNTL_BT_POWERUP_TIMER, 1); REG_SET_FIELD(RTC_CNTL_RTC_TIMER3_REG, RTC_CNTL_BT_WAIT_TIMER, 1); + REG_SET_FIELD(RTC_CNTL_RTC_TIMER6_REG, RTC_CNTL_CPU_TOP_POWERUP_TIMER, 1); + REG_SET_FIELD(RTC_CNTL_RTC_TIMER6_REG, RTC_CNTL_CPU_TOP_WAIT_TIMER, 1); + + /* Set rtc peri timer */ + + REG_SET_FIELD(RTC_CNTL_RTC_TIMER4_REG, RTC_CNTL_RTC_POWERUP_TIMER, 1); + REG_SET_FIELD(RTC_CNTL_RTC_TIMER4_REG, RTC_CNTL_RTC_WAIT_TIMER, 1); + + /* Set digital wrap timer */ + + REG_SET_FIELD(RTC_CNTL_RTC_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, 1); + REG_SET_FIELD(RTC_CNTL_RTC_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, 1); + REG_SET_FIELD(RTC_CNTL_RTC_TIMER6_REG, RTC_CNTL_DG_PERI_POWERUP_TIMER, 1); + REG_SET_FIELD(RTC_CNTL_RTC_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, 1); + /* Reset RTC bias to default value (needed if waking up from deep sleep) */ REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, @@ -1544,6 +1579,10 @@ void IRAM_ATTR esp32s3_rtc_init(void) REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, RTC_CNTL_DBIAS_1V10); + /* Set the wait time to the default value. */ + + REG_SET_FIELD(RTC_CNTL_RTC_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, + RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT); if (cfg.cali_ocode) { /* TODO: Use calibration from efuse if configured */ @@ -1551,6 +1590,10 @@ void IRAM_ATTR esp32s3_rtc_init(void) esp32s3_rtc_calibrate_ocode(); } + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, + g_rtc_dbias_pvt_non_240m); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, + g_dig_dbias_pvt_non_240m); if (cfg.clkctl_init) { /* clear CMMU clock force on */ @@ -1700,6 +1743,13 @@ void IRAM_ATTR esp32s3_rtc_init(void) modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD | RTC_CNTL_DG_PAD_FORCE_NOISO, 0); } + + /* force power down wifi and bt power domain */ + + modifyreg32(RTC_CNTL_DIG_ISO_REG, 0, RTC_CNTL_WIFI_FORCE_ISO); + modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_WIFI_FORCE_PD); + putreg32(0, RTC_CNTL_INT_ENA_RTC_REG); + putreg32(UINT32_MAX, RTC_CNTL_INT_CLR_RTC_REG); } /**************************************************************************** @@ -1809,7 +1859,7 @@ uint32_t IRAM_ATTR esp32s3_clk_slowclk_cal_get(void) * Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source. * * Input Parameters: - * t - value of RTC counter at which wakeup from sleep will happen. + * t - Value of RTC counter at which wakeup from sleep will happen. * * Returned Value: * None @@ -1820,6 +1870,10 @@ void IRAM_ATTR esp32s3_rtc_sleep_set_wakeup_time(uint64_t t) { putreg32(t & UINT32_MAX, RTC_CNTL_RTC_SLP_TIMER0_REG); putreg32((uint32_t)(t >> 32), RTC_CNTL_RTC_SLP_TIMER1_REG); + modifyreg32(RTC_CNTL_INT_CLR_RTC_REG, 0, + RTC_CNTL_RTC_MAIN_TIMER_INT_CLR_M); + modifyreg32(RTC_CNTL_RTC_SLP_TIMER1_REG, 0, + RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN_M); } /**************************************************************************** @@ -1993,6 +2047,126 @@ int IRAM_ATTR esp_rtc_clk_get_cpu_freq(void) void IRAM_ATTR esp32s3_rtc_sleep_init(uint32_t flags) { struct esp32s3_rtc_sleep_config_s cfg = RTC_SLEEP_CONFIG_DEFAULT(flags); + if (flags & RTC_SLEEP_PD_DIG) + { + DEBUGASSERT(flags & RTC_SLEEP_PD_XTAL); + cfg.dig_dbias_slp = 0; + + /* RTC voltage from high to low */ + + if ((flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) || + (!(flags & RTC_SLEEP_PD_INT_8M))) + { + /* RTC voltage in sleep mode >= 0.9v if 8MD256 select as RTC + * slow clock src, only need dbg_atten_slp set to 0 + * Support all features: + * - 8MD256 as RTC slow clock src + * - ADC/Temperature sensor in monitor mode (ULP) + * (also need pd_cur_monitor = 0) + * - RTC IO as input + * - RTC Memory at high temperature + * - ULP + * - Touch sensor + */ + + cfg.rtc_regulator_fpu = 1; + cfg.dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP; + } + else if (flags & RTC_SLEEP_NO_ULTRA_LOW) + { + /* RTC voltage in sleep mode >= 0.7v (default mode): + * Support follow features: + * - RTC IO as input + * - RTC Memory at high temperature + * - ULP + * - Touch sensor + */ + + cfg.rtc_regulator_fpu = 1; + cfg.dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; + } + else + { + /* RTC regulator not opened and rtc voltage is about 0.66v + * (ultra low power). + * Support follow features: + * - ULP + * - Touch sensor + */ + + cfg.rtc_regulator_fpu = 0; + cfg.dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_ULTRA_LOW; + } + } + else + { + cfg.rtc_regulator_fpu = 1; + + /* Voltage from high to low */ + + if ((flags & RTC_SLEEP_DIG_USE_8M) || !(flags & RTC_SLEEP_PD_XTAL)) + { + /* digital voltage not less than 1.1v, rtc voltage is about 1.1v + * Support all features: + * - XTAL + * - RC 8M used by digital system + * - 8MD256 as RTC slow clock src (only need dbg_atten_slp to 0) + * - ADC/Temperature sensor in monitor mode (ULP) + * (also need pd_cur_monitor = 0) + * - ULP + * - Touch sensor + */ + + cfg.dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; + cfg.dig_dbias_slp = RTC_CNTL_DBIAS_1V10; + } + else if (!(flags & RTC_SLEEP_PD_INT_8M)) + { + /* dbg_atten_slp need to set to 0. + * digital voltage is about 0.67v, rtc voltage is about 1.1v + * Support features: + * - 8MD256 as RTC slow clock src + * - ADC/Temperature sensor in monitor mode (ULP) + * (also need pd_cur_monitor = 0) + * - ULP + * - Touch sensor + */ + + cfg.dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; + cfg.dig_dbias_slp = 0; + } + else + { + /* digital voltage not less than 0.6v, rtc voltage is about 0.95v + * Support features: + * - ADC/Temperature sensor in monitor mode (ULP) + * (also need pd_cur_monitor = 0) + * - ULP + * - Touch sensor + */ + + cfg.dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT; + cfg.dig_dbias_slp = RTC_CNTL_DBIAS_SLP; + } + } + + if (!(flags & RTC_SLEEP_PD_XTAL)) + { + cfg.bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_ON; + cfg.pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_ON; + cfg.bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_ON; + cfg.pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_ON; + } + else + { + cfg.bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; + cfg.pd_cur_monitor = (flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) ? + RTC_CNTL_PD_CUR_MONITOR_ON : + RTC_CNTL_PD_CUR_MONITOR_DEFAULT; + + cfg.bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; + cfg.pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + } /* Starts here */ @@ -2031,7 +2205,7 @@ void IRAM_ATTR esp32s3_rtc_sleep_init(uint32_t flags) { modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO | RTC_CNTL_CPU_TOP_FORCE_ISO, 0); - modifyreg32(RTC_CNTL_RTC_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU, + modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU, RTC_CNTL_CPU_TOP_PD_EN); } else @@ -2043,103 +2217,94 @@ void IRAM_ATTR esp32s3_rtc_sleep_init(uint32_t flags) { modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO | RTC_CNTL_DG_PERI_FORCE_ISO, 0); - modifyreg32(RTC_CNTL_RTC_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU, + modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU, RTC_CNTL_DG_PERI_PD_EN); } else { - modifyreg32(RTC_CNTL_RTC_PWC_REG, RTC_CNTL_DG_PERI_PD_EN, 0); + modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN, 0); } if (cfg.rtc_peri_pd_en) { - modifyreg32(RTC_CNTL_RTC_PWC_REG, 0, RTC_CNTL_RTC_PD_EN); + modifyreg32(RTC_CNTL_RTC_PWC_REG, RTC_CNTL_RTC_FORCE_NOISO | + RTC_CNTL_RTC_FORCE_ISO | RTC_CNTL_RTC_FORCE_PU, + RTC_CNTL_RTC_PD_EN); } else { modifyreg32(RTC_CNTL_RTC_PWC_REG, RTC_CNTL_RTC_PD_EN, 0); } + DEBUGASSERT(!cfg.pd_cur_monitor || cfg.bias_sleep_monitor); + DEBUGASSERT(!cfg.pd_cur_slp || cfg.bias_sleep_slp); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, + cfg.rtc_dbias_slp); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, + cfg.dig_dbias_slp); + + REG_SET_FIELD(RTC_CNTL_RTC_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, + cfg.dbg_atten_slp); + REG_SET_FIELD(RTC_CNTL_RTC_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, + cfg.bias_sleep_slp); + REG_SET_FIELD(RTC_CNTL_RTC_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, + cfg.pd_cur_slp); REG_SET_FIELD(RTC_CNTL_RTC_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT); REG_SET_FIELD(RTC_CNTL_RTC_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, - RTC_CNTL_BIASSLP_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_RTC_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, - (!cfg.deep_slp && cfg.xtal_fpu) ? - RTC_CNTL_BIASSLP_SLEEP_ON : - RTC_CNTL_BIASSLP_SLEEP_DEFAULT); + cfg.bias_sleep_monitor); REG_SET_FIELD(RTC_CNTL_RTC_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, - RTC_CNTL_PD_CUR_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_RTC_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, - (!cfg.deep_slp && cfg.xtal_fpu) ? RTC_CNTL_PD_CUR_SLEEP_ON : - RTC_CNTL_PD_CUR_SLEEP_DEFAULT); + cfg.pd_cur_monitor); if (cfg.deep_slp) { - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_ISO | - RTC_CNTL_DG_PAD_FORCE_NOISO, 0); - - /* Shut down parts of RTC which may have been left - * enabled by the wireless drivers. - */ - + modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_DG_WRAP_PD_EN); modifyreg32(RTC_CNTL_RTC_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU, 0); } else { + REG_SET_FIELD(RTC_CNTL_RTC_REGULATOR_DRV_CTRL_REG, + RTC_CNTL_DG_VDD_DRV_B_SLP, + RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT); modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN, 0); - REG_SET_FIELD(RTC_CNTL_RTC_BIAS_CONF_REG, - RTC_CNTL_DBG_ATTEN_DEEP_SLP, 0); } - REG_SET_FIELD(RTC_CNTL_RTC_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, - cfg.xtal_fpu); + /* Mem force pu */ - if (REG_GET_FIELD(RTC_CNTL_RTC_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL) == - RTC_SLOW_FREQ_8MD256) + modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_LSLP_MEM_FORCE_PU); + modifyreg32(RTC_CNTL_RTC_PWC_REG, 0, RTC_CNTL_RTC_FASTMEM_FORCE_LPU | + RTC_CNTL_RTC_SLOWMEM_FORCE_LPU); + REG_SET_FIELD(RTC_CNTL_RTC_REG, RTC_CNTL_RTC_REGULATOR_FORCE_PU, + cfg.rtc_regulator_fpu); + if (!cfg.int_8m_pd_en) { - modifyreg32(RTC_CNTL_RTC_CLK_CONF_REG, 0, RTC_CNTL_CK8M_FORCE_PU); + REG_SET_BIT(RTC_CNTL_RTC_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); } else { - modifyreg32(RTC_CNTL_RTC_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, 0); - } - - /* Keep the RTC8M_CLK on in light_sleep mode if the - * ledc low-speed channel is clocked by RTC8M_CLK. - */ - - if (!cfg.deep_slp && GET_PERI_REG_MASK(RTC_CNTL_RTC_CLK_CONF_REG, - RTC_CNTL_DIG_CLK8M_EN_M)) - { - REG_CLR_BIT(RTC_CNTL_RTC_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD); - REG_SET_BIT(RTC_CNTL_RTC_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); + REG_CLR_BIT(RTC_CNTL_RTC_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); } - /* enable VDDSDIO control by state machine */ + /* Enable VDDSDIO control by state machine */ - modifyreg32(RTC_CNTL_RTC_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE, 0); + REG_CLR_BIT(RTC_CNTL_RTC_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); REG_SET_FIELD(RTC_CNTL_RTC_SDIO_CONF_REG, RTC_CNTL_SDIO_REG_PD_EN, cfg.vddsdio_pd_en); - - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, - cfg.rtc_dbias_slp); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, - cfg.rtc_dbias_wak); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, - cfg.dig_dbias_slp); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, - cfg.dig_dbias_wak); - REG_SET_FIELD(RTC_CNTL_RTC_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject); REG_SET_FIELD(RTC_CNTL_RTC_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); - REG_SET_FIELD(RTC_CNTL_RTC_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, - cfg.xtal_fpu); + /* Set wait cycle for touch or COCPU after deep sleep and light sleep. */ + + REG_SET_FIELD(RTC_CNTL_RTC_TIMER2_REG, + RTC_CNTL_ULPCP_TOUCH_START_WAIT, + RTC_CNTL_ULPCP_TOUCH_START_WAIT_IN_SLEEP); + + REG_SET_FIELD(RTC_CNTL_RTC_OPTIONS0_REG, + RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu); REG_SET_FIELD(RTC_CNTL_RTC_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu); } @@ -2151,8 +2316,8 @@ void IRAM_ATTR esp32s3_rtc_sleep_init(uint32_t flags) * Enter force sleep mode. * * Input Parameters: - * wakeup_opt - bit mask wake up reasons to enable - * reject_opt - bit mask of sleep reject reasons. + * wakeup_opt - Bit mask wake up reasons to enable + * reject_opt - Bit mask of sleep reject reasons. * * Returned Value: * non-zero if sleep was rejected by hardware @@ -2165,7 +2330,11 @@ int IRAM_ATTR esp32s3_rtc_sleep_start(uint32_t wakeup_opt, int reject; REG_SET_FIELD(RTC_CNTL_RTC_WAKEUP_STATE_REG, RTC_CNTL_RTC_WAKEUP_ENA, wakeup_opt); - putreg32((uint32_t)reject_opt, RTC_CNTL_RTC_SLP_REJECT_CONF_REG); + REG_SET_FIELD(RTC_CNTL_RTC_SLP_REJECT_CONF_REG, + RTC_CNTL_RTC_SLEEP_REJECT_ENA, reject_opt); + + modifyreg32(RTC_CNTL_INT_CLR_RTC_REG, 0, + RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR); /* Start entry into sleep mode */ @@ -2182,10 +2351,11 @@ int IRAM_ATTR esp32s3_rtc_sleep_start(uint32_t wakeup_opt, modifyreg32(RTC_CNTL_INT_CLR_RTC_REG, 0, RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR); - /* restore DBG_ATTEN to the default value */ + /* Recover default wait cycle for touch or COCPU after wakeup. */ + + REG_SET_FIELD(RTC_CNTL_RTC_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, + RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT); - REG_SET_FIELD(RTC_CNTL_RTC_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, - RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT); return reject; } @@ -2405,6 +2575,34 @@ void IRAM_ATTR esp32s3_rtc_bbpll_disable(void) RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); } +/**************************************************************************** + * Name: esp32c3_rtc_sleep_low_init + * + * Description: + * Low level initialize for rtc state machine waiting + * cycles after waking up. + * + * Input Parameters: + * slowclk_period - Re-calibrated slow clock period + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s3_rtc_sleep_low_init(uint32_t slowclk_period) +{ + /* Set 5 PWC state machine times to fit in main state machine time */ + + REG_SET_FIELD(RTC_CNTL_RTC_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, + RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); + REG_SET_FIELD(RTC_CNTL_RTC_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, + esp32s3_rtc_time_us_to_slowclk( + RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period)); + REG_SET_FIELD(RTC_CNTL_RTC_TIMER1_REG, RTC_CNTL_CK8M_WAIT, + RTC_CNTL_CK8M_WAIT_SLP_CYCLES); +} + /**************************************************************************** * Name: esp32s3_rtc_set_boot_time * @@ -2412,7 +2610,7 @@ void IRAM_ATTR esp32s3_rtc_bbpll_disable(void) * Set time to RTC register to replace the original boot time. * * Input Parameters: - * time_us - set time in microseconds. + * time_us - Set time in microseconds. * * Returned Value: * None @@ -2435,7 +2633,7 @@ void IRAM_ATTR esp32s3_rtc_set_boot_time(uint64_t time_us) * None * * Returned Value: - * time_us - get time in microseconds. + * time_us - Get time in microseconds. * ****************************************************************************/ @@ -2540,7 +2738,7 @@ time_t up_rtc_time(void) * able to set their time based on a standard timespec. * * Input Parameters: - * ts - the time to use + * ts - The time to use * * Returned Value: * Zero (OK) on success; a negated errno on failure diff --git a/arch/xtensa/src/esp32s3/esp32s3_rtc.h b/arch/xtensa/src/esp32s3/esp32s3_rtc.h index 0adcfb59394f8..7ad11eec4dc90 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_rtc.h +++ b/arch/xtensa/src/esp32s3/esp32s3_rtc.h @@ -68,6 +68,21 @@ extern "C" #define RTC_CLK_CAL_FRACT 19 +/* Cycles for RTC Timer clock source (internal oscillator) calibrate */ + +#define RTC_CLK_SRC_CAL_CYCLES (10) + +#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) +#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) +#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) +#define RTC_CNTL_WAKEUP_DELAY_CYCLES (4) + +#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100 +#define RTC_CNTL_SCK_DCAP_DEFAULT 255 + +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_IN_SLEEP (0xFF) +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT (0x10) + /**************************************************************************** * Public Types ****************************************************************************/ @@ -350,6 +365,23 @@ void esp32s3_rtc_init(void); uint64_t esp32s3_rtc_time_get(void); +/**************************************************************************** + * Name: esp32s3_rtc_sleep_low_init + * + * Description: + * Low level initialize for rtc state machine waiting + * cycles after waking up. + * + * Input Parameters: + * slowclk_period - Re-calibrated slow clock period + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s3_rtc_sleep_low_init(uint32_t slowclk_period); + /**************************************************************************** * Name: esp32s3_rtc_time_us_to_slowclk * diff --git a/arch/xtensa/src/esp32s3/esp32s3_spi.c b/arch/xtensa/src/esp32s3/esp32s3_spi.c index 80b5689fe9c0e..03f7f2b4606ca 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spi.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spi.c @@ -50,6 +50,7 @@ #ifdef CONFIG_ESP32S3_SPI_DMA #include "esp32s3_dma.h" +#include "hardware/esp32s3_dma.h" #endif #include "xtensa.h" @@ -136,6 +137,7 @@ struct esp32s3_spi_config_s #ifdef CONFIG_ESP32S3_SPI_DMA uint32_t dma_clk_bit; /* DMA clock enable bit */ uint32_t dma_rst_bit; /* DMA reset bit */ + uint8_t dma_periph; /* DMA peripheral */ #endif uint32_t cs_insig; /* SPI CS input signal index */ uint32_t cs_outsig; /* SPI CS output signal index */ @@ -204,12 +206,11 @@ static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv, const void *txbuffer, void *rxbuffer, uint32_t nwords); -#else +#endif static void esp32s3_spi_poll_exchange(struct esp32s3_spi_priv_s *priv, const void *txbuffer, void *rxbuffer, size_t nwords); -#endif #ifndef CONFIG_SPI_EXCHANGE static void esp32s3_spi_sndblock(struct spi_dev_s *dev, const void *txbuffer, @@ -222,9 +223,9 @@ static void esp32s3_spi_recvblock(struct spi_dev_s *dev, static int esp32s3_spi_trigger(struct spi_dev_s *dev); #endif #ifdef CONFIG_ESP32S3_SPI_DMA -static void esp32s3_spi_dma_init(struct spi_dev_s *dev); +static int esp32s3_spi_dma_init(struct spi_dev_s *dev); #endif -static void esp32s3_spi_init(struct spi_dev_s *dev); +static int esp32s3_spi_init(struct spi_dev_s *dev); static void esp32s3_spi_deinit(struct spi_dev_s *dev); /**************************************************************************** @@ -251,6 +252,7 @@ static const struct esp32s3_spi_config_s esp32s3_spi2_config = #ifdef CONFIG_ESP32S3_SPI_DMA .dma_clk_bit = SYSTEM_SPI2_DMA_CLK_EN, .dma_rst_bit = SYSTEM_SPI2_DMA_RST, + .dma_periph = ESP32S3_DMA_PERIPH_SPI2, #endif .cs_insig = FSPICS0_IN_IDX, .cs_outsig = FSPICS0_OUT_IDX, @@ -345,15 +347,16 @@ static const struct esp32s3_spi_config_s esp32s3_spi3_config = #ifdef CONFIG_ESP32S3_SPI_DMA .dma_clk_bit = SYSTEM_SPI3_DMA_CLK_EN, .dma_rst_bit = SYSTEM_SPI3_DMA_RST, + .dma_periph = ESP32S3_DMA_PERIPH_SPI3, #endif - .cs_insig = FSPICS0_IN_IDX, - .cs_outsig = FSPICS0_OUT_IDX, - .mosi_insig = FSPID_IN_IDX, - .mosi_outsig = FSPID_OUT_IDX, - .miso_insig = FSPIQ_IN_IDX, - .miso_outsig = FSPIQ_OUT_IDX, - .clk_insig = FSPICLK_IN_IDX, - .clk_outsig = FSPICLK_OUT_IDX + .cs_insig = SPI3_CS0_IN_IDX, + .cs_outsig = SPI3_CS0_OUT_IDX, + .mosi_insig = SPI3_D_IN_IDX, + .mosi_outsig = SPI3_D_OUT_IDX, + .miso_insig = SPI3_Q_IN_IDX, + .miso_outsig = SPI3_Q_OUT_IDX, + .clk_insig = SPI3_CLK_IN_IDX, + .clk_outsig = SPI3_CLK_OUT_IDX }; static const struct spi_ops_s esp32s3_spi3_ops = @@ -430,8 +433,8 @@ static struct esp32s3_spi_priv_s esp32s3_spi3_priv = * Set the bits of the SPI register. * * Input Parameters: - * addr - Address of the register of interest - * bits - Bits to be set + * addr - Address of the register of interest + * bits - Bits to be set * * Returned Value: * None. @@ -452,8 +455,8 @@ static inline void esp32s3_spi_set_regbits(uint32_t addr, uint32_t bits) * Clear the bits of the SPI register. * * Input Parameters: - * addr - Address of the register of interest - * bits - Bits to be cleared + * addr - Address of the register of interest + * bits - Bits to be cleared * * Returned Value: * None. @@ -511,8 +514,8 @@ static inline bool esp32s3_spi_iomux(struct esp32s3_spi_priv_s *priv) * Lock or unlock the SPI device. * * Input Parameters: - * dev - Device-specific state data - * lock - true: Lock SPI bus, false: unlock SPI bus + * dev - Device-specific state data + * lock - true: Lock SPI bus, false: unlock SPI bus * * Returned Value: * The result of lock or unlock the SPI device. @@ -894,10 +897,11 @@ static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv, { /* Reset SPI DMA TX FIFO */ - esp32s3_spi_set_regbits(SPI_DMA_CONF_REG(priv->config->id), - SPI_DMA_RESET_MASK); - esp32s3_spi_clr_regbits(SPI_DMA_CONF_REG(priv->config->id), - SPI_DMA_RESET_MASK); + SET_GDMA_CH_BITS(DMA_OUT_CONF0_CH0_REG, priv->dma_channel, + DMA_OUT_RST_CH0); + + CLR_GDMA_CH_BITS(DMA_OUT_CONF0_CH0_REG, priv->dma_channel, + DMA_OUT_RST_CH0); /* Enable SPI DMA TX */ @@ -905,7 +909,7 @@ static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv, SPI_DMA_TX_ENA_M); n = esp32s3_dma_setup(priv->dma_txdesc, SPI_DMA_DESC_NUM, - tp, bytes, true); + tp, bytes, true, priv->dma_channel); esp32s3_dma_load(priv->dma_txdesc, channel, true); esp32s3_dma_enable(channel, true); @@ -917,13 +921,21 @@ static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv, if (rp != NULL) { + /* Reset SPI DMA RX FIFO */ + + SET_GDMA_CH_BITS(DMA_IN_CONF0_CH0_REG, priv->dma_channel, + DMA_IN_RST_CH0); + + CLR_GDMA_CH_BITS(DMA_IN_CONF0_CH0_REG, priv->dma_channel, + DMA_IN_RST_CH0); + /* Enable SPI DMA RX */ esp32s3_spi_set_regbits(SPI_DMA_CONF_REG(priv->config->id), SPI_DMA_RX_ENA_M); esp32s3_dma_setup(priv->dma_rxdesc, SPI_DMA_DESC_NUM, - rp, bytes, false); + rp, bytes, false, priv->dma_channel); esp32s3_dma_load(priv->dma_rxdesc, channel, false); esp32s3_dma_enable(channel, false); @@ -979,6 +991,14 @@ static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv, static uint32_t esp32s3_spi_poll_send(struct esp32s3_spi_priv_s *priv, uint32_t wd) { +#ifdef CONFIG_ESP32S3_SPI_DMA + esp32s3_spi_clr_regbits(SPI_DMA_CONF_REG(priv->config->id), + SPI_DMA_TX_ENA_M); + + esp32s3_spi_clr_regbits(SPI_DMA_CONF_REG(priv->config->id), + SPI_DMA_RX_ENA_M); +#endif + uint32_t val; putreg32((priv->nbits - 1), SPI_MS_DLEN_REG(priv->config->id)); @@ -1059,6 +1079,14 @@ static void esp32s3_spi_poll_exchange(struct esp32s3_spi_priv_s *priv, void *rxbuffer, size_t nwords) { +#ifdef CONFIG_ESP32S3_SPI_DMA + esp32s3_spi_clr_regbits(SPI_DMA_CONF_REG(priv->config->id), + SPI_DMA_TX_ENA_M); + + esp32s3_spi_clr_regbits(SPI_DMA_CONF_REG(priv->config->id), + SPI_DMA_RX_ENA_M); +#endif + const uint32_t total_bytes = nwords * (priv->nbits / 8); uintptr_t bytes_remaining = total_bytes; const uint8_t *tp = (const uint8_t *)txbuffer; @@ -1198,7 +1226,7 @@ static void esp32s3_spi_exchange(struct spi_dev_s *dev, #ifdef CONFIG_ESP32S3_SPI_DMA size_t thld = CONFIG_ESP32S3_SPI_DMATHRESHOLD; - if (nwords > thld) + if ((nwords * priv->nbits) / 8 > thld) { esp32s3_spi_dma_exchange(priv, txbuffer, rxbuffer, nwords); } @@ -1277,7 +1305,7 @@ static void esp32s3_spi_recvblock(struct spi_dev_s *dev, * Trigger a previously configured DMA transfer. * * Input Parameters: - * dev - Device-specific state data + * dev - Device-specific state data * * Returned Value: * OK - Trigger was fired @@ -1293,6 +1321,8 @@ static int esp32s3_spi_trigger(struct spi_dev_s *dev) } #endif +#ifdef CONFIG_ESP32S3_SPI_DMA + /**************************************************************************** * Name: esp32s3_spi_dma_init * @@ -1300,15 +1330,14 @@ static int esp32s3_spi_trigger(struct spi_dev_s *dev) * Initialize ESP32-S3 SPI connection to GDMA engine. * * Input Parameters: - * dev - Device-specific state data + * dev - Device-specific state data * * Returned Value: - * None. + * OK on success; A negated errno value on failure. * ****************************************************************************/ -#ifdef CONFIG_ESP32S3_SPI_DMA -void esp32s3_spi_dma_init(struct spi_dev_s *dev) +static int esp32s3_spi_dma_init(struct spi_dev_s *dev) { struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)dev; @@ -1326,19 +1355,53 @@ void esp32s3_spi_dma_init(struct spi_dev_s *dev) /* Request a GDMA channel for SPI peripheral */ - priv->dma_channel = esp32s3_dma_request(ESP32S3_DMA_PERIPH_SPI2, 1, 1, + priv->dma_channel = esp32s3_dma_request(priv->config->dma_periph, 1, 1, true); if (priv->dma_channel < 0) { spierr("Failed to allocate GDMA channel\n"); - DEBUGPANIC(); + esp32s3_dma_deinit(); + return ERROR; } /* Disable segment transaction mode for SPI Master */ putreg32((SPI_SLV_RX_SEG_TRANS_CLR_EN_M | SPI_SLV_TX_SEG_TRANS_CLR_EN_M), SPI_DMA_CONF_REG(priv->config->id)); + + return OK; +} + +/**************************************************************************** + * Name: esp32s3_spi_dma_deinit + * + * Description: + * Deinitialize ESP32-S3 SPI GDMA engine. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32s3_spi_dma_deinit(struct spi_dev_s *dev) +{ + struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)dev; + + /* Release a DMA channel from peripheral */ + + esp32s3_dma_release(priv->dma_channel); + + /* Deinitialize DMA controller */ + + esp32s3_dma_deinit(); + + /* Disable DMA clock for the SPI peripheral */ + + modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, priv->config->dma_clk_bit, 0); } #endif @@ -1349,14 +1412,14 @@ void esp32s3_spi_dma_init(struct spi_dev_s *dev) * Initialize ESP32-S3 SPI hardware interface. * * Input Parameters: - * dev - Device-specific state data + * dev - Device-specific state data * * Returned Value: - * None. + * OK on success; A negated errno value on failure. * ****************************************************************************/ -static void esp32s3_spi_init(struct spi_dev_s *dev) +static int esp32s3_spi_init(struct spi_dev_s *dev) { struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)dev; const struct esp32s3_spi_config_s *config = priv->config; @@ -1427,12 +1490,19 @@ static void esp32s3_spi_init(struct spi_dev_s *dev) SPI_USER1_REG(priv->config->id)); #ifdef CONFIG_ESP32S3_SPI_DMA - esp32s3_spi_dma_init(dev); + if (esp32s3_spi_dma_init(dev) != OK) + { + modifyreg32(SYSTEM_PERIP_RST_EN0_REG, 0, priv->config->clk_bit); + modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, priv->config->clk_bit, 0); + return ERROR; + } #endif esp32s3_spi_setfrequency(dev, config->clk_freq); esp32s3_spi_setbits(dev, config->width); esp32s3_spi_setmode(dev, config->mode); + + return OK; } /**************************************************************************** @@ -1442,7 +1512,7 @@ static void esp32s3_spi_init(struct spi_dev_s *dev) * Deinitialize ESP32-S3 SPI hardware interface. * * Input Parameters: - * dev - Device-specific state data + * dev - Device-specific state data * * Returned Value: * None. @@ -1454,7 +1524,7 @@ static void esp32s3_spi_deinit(struct spi_dev_s *dev) struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)dev; #ifdef CONFIG_ESP32S3_SPI_DMA - modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, priv->config->dma_clk_bit, 0); + esp32s3_spi_dma_deinit(dev); #endif modifyreg32(SYSTEM_PERIP_RST_EN0_REG, 0, priv->config->clk_bit); @@ -1504,7 +1574,7 @@ static int esp32s3_spi_interrupt(int irq, void *context, void *arg) * Initialize the selected SPI bus. * * Input Parameters: - * port - Port number (for hardware that has multiple SPI interfaces) + * port - Port number (for hardware that has multiple SPI interfaces) * * Returned Value: * Valid SPI device structure reference on success; NULL on failure. @@ -1589,7 +1659,18 @@ struct spi_dev_s *esp32s3_spibus_initialize(int port) up_enable_irq(priv->config->irq); #endif - esp32s3_spi_init(spi_dev); + if (esp32s3_spi_init(spi_dev) != OK) + { +#ifdef CONFIG_ESP32S3_SPI_DMA + up_disable_irq(priv->config->irq); + esp32s3_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint); + irq_detach(priv->config->irq); + priv->cpuint = -ENOMEM; +#endif + nxmutex_unlock(&priv->lock); + return NULL; + } + priv->refs++; nxmutex_unlock(&priv->lock); @@ -1603,7 +1684,7 @@ struct spi_dev_s *esp32s3_spibus_initialize(int port) * Uninitialize an SPI bus. * * Input Parameters: - * dev - Device-specific state data + * dev - Device-specific state data * * Returned Value: * Zero (OK) is returned on success. Otherwise -1 (ERROR). diff --git a/arch/xtensa/src/esp32s3/esp32s3_spi.h b/arch/xtensa/src/esp32s3/esp32s3_spi.h index 3afed087b7241..37e7565d2c58c 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spi.h +++ b/arch/xtensa/src/esp32s3/esp32s3_spi.h @@ -69,7 +69,7 @@ extern "C" * Initialize the selected SPI bus. * * Input Parameters: - * port - Port number (for hardware that has multiple SPI interfaces) + * port - Port number (for hardware that has multiple SPI interfaces) * * Returned Value: * Valid SPI device structure reference on success; NULL on failure @@ -134,7 +134,7 @@ int esp32s3_spi3_cmddata(struct spi_dev_s *dev, * Uninitialize an SPI bus. * * Input Parameters: - * dev - Device-specific state data + * dev - Device-specific state data * * Returned Value: * Zero (OK) is returned on success. Otherwise -1 (ERROR). diff --git a/arch/xtensa/src/esp32s3/esp32s3_spi_slave.c b/arch/xtensa/src/esp32s3/esp32s3_spi_slave.c index f231c7ba8d34a..b1931230315c3 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spi_slave.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spi_slave.c @@ -904,7 +904,7 @@ static void spislave_setup_rx_dma(struct spislave_priv_s *priv) SPI_DMA_DESC_NUM, priv->rx_buffer + priv->rx_length, length, - false); + false, priv->dma_channel); esp32s3_dma_load(priv->dma_rxdesc, priv->dma_channel, false); priv->rx_dma_offset = priv->rx_length; @@ -948,7 +948,7 @@ static void spislave_setup_tx_dma(struct spislave_priv_s *priv) SPI_DMA_DESC_NUM, priv->tx_buffer, SPI_SLAVE_BUFSIZE, - true); + true, priv->dma_channel); esp32s3_dma_load(priv->dma_txdesc, priv->dma_channel, true); spislave_dma_tx_fifo_reset(priv); @@ -1150,6 +1150,35 @@ void spislave_dma_init(struct spislave_priv_s *priv) resetbits(SPI_RX_EOF_EN_M, SPI_DMA_CONF_REG(priv->config->id)); } + +/**************************************************************************** + * Name: spislave_dma_deinit + * + * Description: + * Deinitialize ESP32-S3 SPI slave GDMA engine. + * + * Input Parameters: + * dev - Device-specific state data + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void spislave_dma_deinit(struct spislave_priv_s *priv) +{ + /* Release a DMA channel from peripheral */ + + esp32s3_dma_release(priv->dma_channel); + + /* Deinitialize DMA controller */ + + esp32s3_dma_deinit(); + + /* Disable DMA clock for the SPI peripheral */ + + modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, priv->config->dma_clk_bit, 0); +} #endif /**************************************************************************** @@ -1347,7 +1376,7 @@ static void spislave_initialize(struct spi_slave_ctrlr_s *ctrlr) spislave_dma_init(priv); #endif - esp32s3_gpioirqenable(ESP32S3_PIN2IRQ(config->cs_pin), GPIO_INTR_POSEDGE); + esp32s3_gpioirqenable(ESP32S3_PIN2IRQ(config->cs_pin), RISING); /* Force a transaction done interrupt. * This interrupt won't fire yet because we initialized the SPI interrupt @@ -1390,7 +1419,7 @@ static void spislave_deinitialize(struct spi_slave_ctrlr_s *ctrlr) resetbits(SPI_TRANS_DONE_INT_ENA_M, SPI_DMA_INT_ENA_REG(priv->config->id)); #ifdef CONFIG_ESP32S3_SPI_DMA - resetbits(priv->config->dma_clk_bit, SYSTEM_PERIP_CLK_EN0_REG); + spislave_dma_deinit(priv); priv->rx_dma_offset = 0; #endif diff --git a/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c b/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c index 68c63c4f09a6f..280d19357a3fe 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c @@ -30,12 +30,13 @@ #include "esp32s3_gpio.h" #include "esp32s3_psram.h" #include "esp32s3_spi_timing.h" -#include "hardware/esp32s3_spi_mem_reg.h" #include "hardware/esp32s3_iomux.h" #include "hardware/esp32s3_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #include "rom/esp32s3_spiflash.h" -#include "rom/esp32s3_opi_flash.h" +#include "rom/opi_flash.h" + +#include "soc/spi_mem_reg.h" /**************************************************************************** * Pre-processor Definitions @@ -54,7 +55,7 @@ #endif #if defined(CONFIG_ESP32S3_FLASH_SAMPLE_MODE_DTR) -# if defined(CONFIG_ESP32S3_FLASH_FREQ_80M) +# if defined(CONFIG_ESP32S3_FLASH_FREQ_80M) # define ESP32S3_SPI_TIMING_FLASH_CORE_CLK 160 # elif defined(CONFIG_ESP32S3_FLASH_FREQ_120M) # define ESP32S3_SPI_TIMING_FLASH_CORE_CLK 240 diff --git a/arch/xtensa/src/esp32s3/esp32s3_spiflash.c b/arch/xtensa/src/esp32s3/esp32s3_spiflash.c index 87297483c6736..231fab51c4d04 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spiflash.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spiflash.c @@ -36,20 +36,22 @@ #include #include #include +#include #include "sched/sched.h" #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "hardware/esp32s3_efuse.h" -#include "hardware/esp32s3_extmem.h" -#include "hardware/esp32s3_spi_mem_reg.h" #include "hardware/esp32s3_cache_memory.h" #include "rom/esp32s3_spiflash.h" -#include "rom/esp32s3_opi_flash.h" #include "esp32s3_irq.h" #include "esp32s3_spiflash.h" +#include "soc/extmem_reg.h" +#include "soc/spi_mem_reg.h" +#include "rom/opi_flash.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -98,6 +100,7 @@ /* SPI flash hardware definition */ +# define FLASH_PAGE_SIZE (256) # define FLASH_SECTOR_SIZE (4096) /* SPI flash command */ @@ -206,14 +209,10 @@ extern void cache_invalidate_icache_all(void); * Private Data ****************************************************************************/ -static struct spiflash_guard_funcs g_spi_flash_guard_funcs = +static spi_flash_guard_funcs_t g_spi_flash_guard_funcs = { .start = spiflash_start, .end = spiflash_end, - .op_lock = NULL, - .op_unlock = NULL, - .address_is_safe = NULL, - .yield = NULL, }; static uint32_t s_flash_op_cache_state[CONFIG_SMP_NCPUS]; @@ -283,22 +282,26 @@ static void spiflash_resume_cache(void) static void spiflash_start(void) { struct tcb_s *tcb = this_task(); - int cpu = up_cpu_index(); int saved_priority = tcb->sched_priority; + int cpu; #ifdef CONFIG_SMP - int other_cpu = cpu ? 0 : 1; + int other_cpu; #endif nxrmutex_lock(&g_flash_op_mutex); - DEBUGASSERT(cpu == 0 || cpu == 1); - /* Temporary raise schedule priority */ nxsched_set_priority(tcb, SCHED_PRIORITY_MAX); + cpu = up_cpu_index(); #ifdef CONFIG_SMP + other_cpu = cpu == 1 ? 0 : 1; +#endif + + DEBUGASSERT(cpu == 0 || cpu == 1); +#ifdef CONFIG_SMP DEBUGASSERT(other_cpu == 0 || other_cpu == 1); DEBUGASSERT(other_cpu != cpu); if (OSINIT_OS_READY()) @@ -730,6 +733,28 @@ static void IRAM_ATTR spiflash_flushmapped(size_t start, size_t size) } } } + +/**************************************************************************** + * Name: spiflash_os_yield + * + * Description: + * Yield to other tasks, called during erase operations. + * + * Input Parameters: + * None + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static inline void IRAM_ATTR spiflash_os_yield(void) +{ + /* Delay 1 tick */ + + useconds_t us = TICK2USEC(1); + nxsig_usleep(us); +} #endif /* CONFIG_ESP32S3_SPI_FLASH_DONT_USE_ROM_CODE */ /**************************************************************************** @@ -1105,19 +1130,25 @@ int spi_flash_erase_range(uint32_t start_address, uint32_t size) int ret = OK; uint32_t addr = start_address; - spiflash_start(); - for (uint32_t i = 0; i < size; i += FLASH_SECTOR_SIZE) { + if (i > 0) + { + spiflash_os_yield(); + } + + spiflash_start(); wait_flash_idle(); enable_flash_write(); ERASE_FLASH_SECTOR(addr); addr += FLASH_SECTOR_SIZE; + wait_flash_idle(); + disable_flash_write(); + spiflash_end(); } - wait_flash_idle(); - disable_flash_write(); + spiflash_start(); spiflash_flushmapped(start_address, FLASH_SECTOR_SIZE * size); spiflash_end(); @@ -1152,10 +1183,11 @@ int spi_flash_write(uint32_t dest_addr, const void *buffer, uint32_t size) spiflash_start(); - for (int i = 0; i < size; i += SPI_BUFFER_BYTES) + while (tx_bytes) { uint32_t spi_buffer[SPI_BUFFER_WORDS]; - uint32_t n = MIN(tx_bytes, SPI_BUFFER_BYTES); + uint32_t n = FLASH_PAGE_SIZE - tx_addr % FLASH_PAGE_SIZE; + n = MIN(n, MIN(tx_bytes, SPI_BUFFER_BYTES)); #ifdef CONFIG_ESP32S3_SPIRAM diff --git a/arch/xtensa/src/esp32s3/esp32s3_spiflash_mtd.c b/arch/xtensa/src/esp32s3/esp32s3_spiflash_mtd.c index 2ac6d664240d0..ded890a90c339 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spiflash_mtd.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spiflash_mtd.c @@ -39,9 +39,11 @@ #include #include "hardware/esp32s3_soc.h" +#include "hardware/esp32s3_cache_memory.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "esp32s3_spiflash.h" +#include "esp32s3_spiram.h" #include "rom/esp32s3_spiflash.h" #include "esp32s3_spiflash_mtd.h" @@ -59,6 +61,9 @@ #define MTD_BLK2SIZE(_priv, _b) (MTD_BLK_SIZE * (_b)) #define MTD_SIZE2BLK(_priv, _s) ((_s) / MTD_BLK_SIZE) +#define SPI_FLASH_ENCRYPT_UNIT_SIZE (64) +#define SPI_FLASH_ENCRYPT_MIN_SIZE (16) + /**************************************************************************** * Private Types ****************************************************************************/ @@ -71,6 +76,7 @@ enum spiflash_op_code_e SPIFLASH_OP_CODE_WRITE = 0, SPIFLASH_OP_CODE_READ, SPIFLASH_OP_CODE_ERASE, + SPIFLASH_OP_CODE_SET_BANK, SPIFLASH_OP_CODE_ENCRYPT_READ, SPIFLASH_OP_CODE_ENCRYPT_WRITE }; @@ -84,7 +90,7 @@ struct esp32s3_mtd_dev_s /* SPI Flash data */ - const struct spiflash_legacy_data_s **data; + esp_rom_spiflash_legacy_data_t **data; }; #ifdef CONFIG_ESP32S3_SPI_FLASH_SUPPORT_PSRAM_STACK @@ -99,6 +105,7 @@ struct spiflash_work_arg uint32_t addr; uint8_t *buffer; uint32_t size; + uint32_t paddr; } op_arg; volatile int ret; @@ -131,6 +138,10 @@ static ssize_t esp32s3_write(struct mtd_dev_s *dev, off_t offset, size_t nbytes, const uint8_t *buffer); static ssize_t esp32s3_bwrite(struct mtd_dev_s *dev, off_t startblock, size_t nblocks, const uint8_t *buffer); +static int esp32s3_writedata_encrypt(struct mtd_dev_s *dev, off_t offset, + uint32_t size, const uint8_t *buffer); +static ssize_t esp32s3_write_encrypt(struct mtd_dev_s *dev, off_t offset, + size_t nbytes, const uint8_t *buffer); static ssize_t esp32s3_bwrite_encrypt(struct mtd_dev_s *dev, off_t startblock, size_t nblocks, @@ -144,7 +155,8 @@ static void esp32s3_spiflash_work(void *arg); static int esp32s3_async_op(enum spiflash_op_code_e opcode, uint32_t addr, const uint8_t *buffer, - uint32_t size); + uint32_t size, + uint32_t paddr); #endif /**************************************************************************** @@ -165,7 +177,7 @@ static const struct esp32s3_mtd_dev_s g_esp32s3_spiflash = #endif .name = "esp32s3_spiflash" }, - .data = (const struct spiflash_legacy_data_s **) + .data = (esp_rom_spiflash_legacy_data_t **) (&rom_spiflash_legacy_data), }; @@ -179,11 +191,11 @@ static const struct esp32s3_mtd_dev_s g_esp32s3_spiflash_encrypt = .read = esp32s3_read_decrypt, .ioctl = esp32s3_ioctl, #ifdef CONFIG_MTD_BYTE_WRITE - .write = NULL, + .write = esp32s3_write_encrypt, #endif .name = "esp32s3_spiflash_encrypt" }, - .data = (const struct spiflash_legacy_data_s **) + .data = (esp_rom_spiflash_legacy_data_t **) (&rom_spiflash_legacy_data), }; @@ -259,6 +271,12 @@ static void esp32s3_spiflash_work(void *arg) work_arg->ret = spi_flash_erase_range(work_arg->op_arg.addr, work_arg->op_arg.size); } + else if (work_arg->op_code == SPIFLASH_OP_CODE_SET_BANK) + { + work_arg->ret = cache_dbus_mmu_map(work_arg->op_arg.addr, + work_arg->op_arg.paddr, + work_arg->op_arg.size); + } else if (work_arg->op_code == SPIFLASH_OP_CODE_ENCRYPT_READ) { work_arg->ret = spi_flash_read_encrypted(work_arg->op_arg.addr, @@ -300,7 +318,8 @@ static void esp32s3_spiflash_work(void *arg) static int esp32s3_async_op(enum spiflash_op_code_e opcode, uint32_t addr, const uint8_t *buffer, - uint32_t size) + uint32_t size, + uint32_t paddr) { int ret; struct spiflash_work_arg work_arg = @@ -311,6 +330,7 @@ static int esp32s3_async_op(enum spiflash_op_code_e opcode, .addr = addr, .buffer = (uint8_t *)buffer, .size = size, + .paddr = paddr, }, .sem = NXSEM_INITIALIZER(0, 0) }; @@ -356,7 +376,7 @@ static int esp32s3_erase(struct mtd_dev_s *dev, off_t startblock, } #ifdef CONFIG_ESP32S3_STORAGE_MTD_DEBUG - finfo("%s(%p, 0x%x, %d)\n", __func__, dev, startblock, nblocks); + finfo("%s(%p, 0x%" PRIxOFF ", %zu)\n", __func__, dev, startblock, nblocks); finfo("spi_flash_erase_range(0x%x, %d)\n", offset, nbytes); #endif @@ -370,7 +390,8 @@ static int esp32s3_erase(struct mtd_dev_s *dev, off_t startblock, #ifdef CONFIG_ESP32S3_SPI_FLASH_SUPPORT_PSRAM_STACK if (stack_is_psram()) { - ret = esp32s3_async_op(SPIFLASH_OP_CODE_ERASE, offset, NULL, nbytes); + ret = esp32s3_async_op(SPIFLASH_OP_CODE_ERASE, offset, NULL, + nbytes, 0); } else #endif @@ -421,9 +442,10 @@ static ssize_t esp32s3_read(struct mtd_dev_s *dev, off_t offset, ssize_t ret; #ifdef CONFIG_ESP32S3_STORAGE_MTD_DEBUG - finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, offset, nbytes, buffer); + finfo("%s(%p, 0x%" PRIxOFF ", %zu, %p)\n", + __func__, dev, offset, nbytes, buffer); - finfo("spi_flash_read(0x%x, %p, %d)\n", offset, buffer, nbytes); + finfo("spi_flash_read(0x%" PRIxOFF ", %p, %zu)\n", offset, buffer, nbytes); #endif /* Acquire the mutex. */ @@ -438,7 +460,7 @@ static ssize_t esp32s3_read(struct mtd_dev_s *dev, off_t offset, if (stack_is_psram()) { ret = esp32s3_async_op(SPIFLASH_OP_CODE_READ, offset, - buffer, nbytes); + buffer, nbytes, 0); } else #endif @@ -484,8 +506,8 @@ static ssize_t esp32s3_bread(struct mtd_dev_s *dev, off_t startblock, uint32_t size = nblocks * MTD_BLK_SIZE; #ifdef CONFIG_ESP32S3_STORAGE_MTD_DEBUG - finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, startblock, nblocks, - buffer); + finfo("%s(%p, 0x%" PRIxOFF ", %zu, %p)\n", + __func__, dev, startblock, nblocks, buffer); #endif ret = esp32s3_read(dev, addr, size, buffer); @@ -527,9 +549,11 @@ static ssize_t esp32s3_read_decrypt(struct mtd_dev_s *dev, ssize_t ret; #ifdef CONFIG_ESP32S3_STORAGE_MTD_DEBUG - finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, offset, nbytes, buffer); + finfo("%s(%p, 0x%" PRIxOFF ", %zu, %p)\n", + __func__, dev, offset, nbytes, buffer); - finfo("spi_flash_read_encrypted(0x%x, %p, %d)\n", offset, buffer, nbytes); + finfo("spi_flash_read_encrypted(0x%" PRIxOFF ", %p, %zu)\n", + offset, buffer, nbytes); #endif /* Acquire the mutex. */ @@ -544,7 +568,7 @@ static ssize_t esp32s3_read_decrypt(struct mtd_dev_s *dev, if (stack_is_psram()) { ret = esp32s3_async_op(SPIFLASH_OP_CODE_ENCRYPT_READ, offset, - buffer, nbytes); + buffer, nbytes, 0); } else #endif @@ -592,8 +616,8 @@ static ssize_t esp32s3_bread_decrypt(struct mtd_dev_s *dev, uint32_t size = nblocks * MTD_BLK_SIZE; #ifdef CONFIG_ESP32S3_STORAGE_MTD_DEBUG - finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, startblock, nblocks, - buffer); + finfo("%s(%p, 0x%" PRIxOFF ", %zu, %p)\n", + __func__, dev, startblock, nblocks, buffer); #endif ret = esp32s3_read_decrypt(dev, addr, size, buffer); @@ -608,6 +632,144 @@ static ssize_t esp32s3_bread_decrypt(struct mtd_dev_s *dev, return ret; } +/**************************************************************************** + * Name: esp32s3_writedata_encrypt + * + * Description: + * Write plaintext data to SPI Flash at designated address by SPI Flash + * hardware encryption, and written data in SPI Flash is ciphertext. + * + * Input Parameters: + * dev - MTD device data + * offset - target address offset, must be 32Bytes-aligned + * size - data number, must be 32Bytes-aligned + * buffer - data buffer pointer + * + * Returned Value: + * 0 if success or a negative value if fail. + * + ****************************************************************************/ + +static int esp32s3_writedata_encrypt(struct mtd_dev_s *dev, off_t offset, + uint32_t size, const uint8_t *buffer) +{ + ssize_t ret; + +#ifdef CONFIG_ESP32S3_STORAGE_MTD_DEBUG + finfo("%s(%p, 0x%" PRIxOFF ", %zu, %p)\n", __func__, dev, offset, + size, buffer); +#endif + + DEBUGASSERT((offset % SPI_FLASH_ENCRYPT_MIN_SIZE) == 0); + DEBUGASSERT((size % SPI_FLASH_ENCRYPT_MIN_SIZE) == 0); + ret = nxmutex_lock(&g_lock); + if (ret < 0) + { + return ret; + } + +#ifdef CONFIG_ESP32S3_SPI_FLASH_SUPPORT_PSRAM_STACK + if (stack_is_psram()) + { + ret = esp32s3_async_op(SPIFLASH_OP_CODE_ENCRYPT_WRITE, offset, + buffer, size, 0); + } + else +#endif + { + ret = spi_flash_write_encrypted(offset, buffer, size); + } + + nxmutex_unlock(&g_lock); +#ifdef CONFIG_ESP32S3_STORAGE_MTD_DEBUG + finfo("%s()=%d\n", __func__, ret); +#endif + return ret; +} + +/**************************************************************************** + * Name: esp32s3_write_encrypt + * + * Description: + * Write data to SPI Flash at designated address by SPI Flash hardware + * encryption. + * + * Input Parameters: + * dev - MTD device data + * offset - target address offset, must be 16Bytes-aligned + * nbytes - data number, must be 16Bytes-aligned + * buffer - data buffer pointer + * + * Returned Value: + * Writen bytes if success or a negative value if fail. + * + ****************************************************************************/ + +static ssize_t esp32s3_write_encrypt(struct mtd_dev_s *dev, off_t offset, + size_t nbytes, const uint8_t *buffer) +{ + ssize_t ret; + size_t n; + off_t addr; + size_t wbytes; + uint32_t step; + uint8_t enc_buf[SPI_FLASH_ENCRYPT_UNIT_SIZE]; + + if ((offset % SPI_FLASH_ENCRYPT_MIN_SIZE) || + (nbytes % SPI_FLASH_ENCRYPT_MIN_SIZE)) + { + return -EINVAL; + } + else if (nbytes == 0) + { + return 0; + } + +#ifdef CONFIG_ESP32S3_STORAGE_MTD_DEBUG + finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, offset, nbytes, buffer); +#endif + + for (n = 0; n < nbytes; n += step) + { + /* The temporary buffer need to be seperated into + * 16-bytes, 32-bytes, 64-bytes(if supported). + */ + + addr = offset + n; + if ((addr % 64) == 0 && (nbytes - n) >= 64) + { + wbytes = 64; + } + else if ((addr % 32) == 0 && (nbytes - n) >= 32) + { + wbytes = 32; + } + else + { + wbytes = 16; + } + + memcpy(enc_buf, buffer + n, wbytes); + step = wbytes; + ret = esp32s3_writedata_encrypt(dev, addr, wbytes, enc_buf); + if (ret < 0) + { + break; + } + } + + if (ret >= 0) + { + ret = nbytes; + } + +#ifdef CONFIG_ESP32S3_STORAGE_MTD_DEBUG + finfo("esp32s3_write_encrypt()=%d\n", ret); +#endif + + return ret; +} + /**************************************************************************** * Name: esp32s3_write * @@ -639,9 +801,11 @@ static ssize_t esp32s3_write(struct mtd_dev_s *dev, off_t offset, } #ifdef CONFIG_ESP32S3_STORAGE_MTD_DEBUG - finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, offset, nbytes, buffer); + finfo("%s(%p, 0x%" PRIxOFF ", %zu, %p)\n", + __func__, dev, offset, nbytes, buffer); - finfo("spi_flash_write(0x%x, %p, %d)\n", offset, buffer, nbytes); + finfo("spi_flash_write(0x%" PRIxOFF ", %p, %zu)\n", + offset, buffer, nbytes); #endif /* Acquire the mutex. */ @@ -656,7 +820,7 @@ static ssize_t esp32s3_write(struct mtd_dev_s *dev, off_t offset, if (stack_is_psram()) { ret = esp32s3_async_op(SPIFLASH_OP_CODE_WRITE, offset, - buffer, nbytes); + buffer, nbytes, 0); } else #endif @@ -704,10 +868,11 @@ static ssize_t esp32s3_bwrite_encrypt(struct mtd_dev_s *dev, uint32_t size = nblocks * MTD_BLK_SIZE; #ifdef CONFIG_ESP32S3_STORAGE_MTD_DEBUG - finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, startblock, + finfo("%s(%p, 0x%" PRIxOFF ", %zu, %p)\n", __func__, dev, startblock, nblocks, buffer); - finfo("spi_flash_write_encrypted(0x%x, %p, %d)\n", addr, buffer, size); + finfo("spi_flash_write_encrypted(0x%x, %p, %" PRIu32 ")\n", + addr, buffer, size); #endif ret = nxmutex_lock(&g_lock); @@ -720,7 +885,7 @@ static ssize_t esp32s3_bwrite_encrypt(struct mtd_dev_s *dev, if (stack_is_psram()) { ret = esp32s3_async_op(SPIFLASH_OP_CODE_ENCRYPT_WRITE, addr, - buffer, size); + buffer, size, 0); } else #endif @@ -766,7 +931,7 @@ static ssize_t esp32s3_bwrite(struct mtd_dev_s *dev, off_t startblock, uint32_t size = nblocks * MTD_BLK_SIZE; #ifdef CONFIG_ESP32S3_STORAGE_MTD_DEBUG - finfo("%s(%p, 0x%x, %d, %p)\n", __func__, dev, startblock, + finfo("%s(%p, 0x%" PRIxOFF ", %zu, %p)\n", __func__, dev, startblock, nblocks, buffer); #endif @@ -863,6 +1028,43 @@ static int esp32s3_ioctl(struct mtd_dev_s *dev, int cmd, * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: esp32s3_set_bank + * + * Description: + * Set Ext-SRAM-Cache mmu mapping. + * + * Input Parameters: + * virt_bank - Beginning of the virtual bank + * phys_bank - Beginning of the physical bank + * ct - Number of banks + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32s3_set_bank(int virt_bank, int phys_bank, int ct) +{ + int ret; + uint32_t vaddr = SOC_EXTRAM_DATA_LOW + MMU_PAGE_SIZE * virt_bank; + uint32_t paddr = phys_bank * MMU_PAGE_SIZE; +#ifdef CONFIG_ESP32S3_SPI_FLASH_SUPPORT_PSRAM_STACK + if (stack_is_psram()) + { + ret = esp32s3_async_op(SPIFLASH_OP_CODE_SET_BANK, vaddr, NULL, ct, + paddr); + } + else +#endif + { + ret = cache_dbus_mmu_map(vaddr, paddr, ct); + } + + DEBUGASSERT(ret == 0); + UNUSED(ret); +} + /**************************************************************************** * Name: esp32s3_spiflash_alloc_mtdpart * @@ -885,7 +1087,7 @@ struct mtd_dev_s *esp32s3_spiflash_alloc_mtdpart(uint32_t mtd_offset, bool encrypted) { const struct esp32s3_mtd_dev_s *priv; - const esp32s3_spiflash_chip_t *chip; + const esp_rom_spiflash_chip_t *chip; struct mtd_dev_s *mtd_part; uint32_t blocks; uint32_t startblock; diff --git a/arch/xtensa/src/esp32s3/esp32s3_spiflash_mtd.h b/arch/xtensa/src/esp32s3/esp32s3_spiflash_mtd.h index 86f1c1f17410d..d459fe7cd9525 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spiflash_mtd.h +++ b/arch/xtensa/src/esp32s3/esp32s3_spiflash_mtd.h @@ -46,6 +46,24 @@ extern "C" * Public Function Prototypes ****************************************************************************/ +/**************************************************************************** + * Name: esp32s3_set_bank + * + * Description: + * Set Ext-SRAM-Cache mmu mapping. + * + * Input Parameters: + * virt_bank - Beginning of the virtual bank + * phys_bank - Beginning of the physical bank + * ct - Number of banks + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp32s3_set_bank(int virt_bank, int phys_bank, int ct); + /**************************************************************************** * Name: esp32s3_spiflash_mtd * diff --git a/arch/xtensa/src/esp32s3/esp32s3_spiram.c b/arch/xtensa/src/esp32s3/esp32s3_spiram.c index 8edf42e447955..c4722167f8926 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spiram.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spiram.c @@ -33,17 +33,19 @@ #include #include #include +#include #include #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "esp32s3_psram.h" #include "esp32s3_spiram.h" #include "hardware/esp32s3_soc.h" #include "hardware/esp32s3_cache_memory.h" -#include "hardware/esp32s3_extmem.h" #include "hardware/esp32s3_iomux.h" +#include "soc/extmem_reg.h" + #define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL #if defined(CONFIG_ESP32S3_SPIRAM) @@ -66,6 +68,22 @@ #define SPIRAM_VADDR_MAP_SIZE 0 #endif +/* Max MMU available paddr page num. + * `MMU_MAX_PADDR_PAGE_NUM * MMU_PAGE_SIZE` means the max paddr + * address supported by the MMU. e.g.: 16384 * 64KB, means MMU can + * support 1GB paddr at most + */ + +#define MMU_MAX_PADDR_PAGE_NUM 16384 + +/* This is the mask used for mapping. e.g.: 0x4200_0000 & MMU_VADDR_MASK */ + +#define MMU_VADDR_MASK 0x1FFFFFF + +/* MMU entry num */ + +#define MMU_ENTRY_NUM 512 + static bool g_spiram_inited; /* These variables are in bytes */ @@ -109,6 +127,7 @@ extern void cache_resume_dcache(uint32_t val); extern int cache_dbus_mmu_set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); +extern int cache_invalidate_addr(uint32_t addr, uint32_t size); /**************************************************************************** * Private Functions @@ -142,10 +161,189 @@ static inline uint32_t mmu_valid_space(uint32_t *start_address) return 0; } +/**************************************************************************** + * Name: mmu_check_valid_paddr_region + * + * Description: + * Check if the paddr region is valid. + * + * Input Parameters: + * paddr_start - start of the physical address + * len - length, in bytes + * + * Returned Value: + * True for valid. + * + ****************************************************************************/ + +static inline bool mmu_check_valid_paddr_region(uint32_t paddr_start, + uint32_t len) +{ + return (paddr_start < (MMU_PAGE_SIZE * MMU_MAX_PADDR_PAGE_NUM)) && + (len < (MMU_PAGE_SIZE * MMU_MAX_PADDR_PAGE_NUM)) && + ((paddr_start + len - 1) < + (MMU_PAGE_SIZE * MMU_MAX_PADDR_PAGE_NUM)); +} + +/**************************************************************************** + * Name: mmu_check_valid_ext_vaddr_region + * + * Description: + * Check if the external memory vaddr region is valid. + * + * Input Parameters: + * vaddr_start - start of the virtual address + * len - length, in bytes + * + * Returned Value: + * True for valid. + * + ****************************************************************************/ + +static inline bool mmu_check_valid_ext_vaddr_region(uint32_t vaddr_start, + uint32_t len) +{ + uint32_t vaddr_end = vaddr_start + len - 1; + bool valid = false; + valid |= (ADDRESS_IN_IRAM0_CACHE(vaddr_start) && + ADDRESS_IN_IRAM0_CACHE(vaddr_end)) | + (ADDRESS_IN_DRAM0_CACHE(vaddr_start) && + ADDRESS_IN_DRAM0_CACHE(vaddr_end)); + return valid; +} + +/**************************************************************************** + * Name: esp_mmu_map_region + * + * Description: + * To map a virtual address block to a physical memory block. + * + * Input Parameters: + * vaddr - Virtual address in CPU address space + * paddr - Physical address in Ext-SRAM + * len - Length to be mapped, in bytes + * mem_type - MMU target physical memory + * + * Returned Value: + * Actual mapped length. + * + ****************************************************************************/ + +static int IRAM_ATTR esp_mmu_map_region(uint32_t vaddr, uint32_t paddr, + uint32_t len, uint32_t mem_type) +{ + DEBUGASSERT(vaddr % MMU_PAGE_SIZE == 0); + DEBUGASSERT(paddr % MMU_PAGE_SIZE == 0); + DEBUGASSERT(mmu_check_valid_paddr_region(paddr, len)); + DEBUGASSERT(mmu_check_valid_ext_vaddr_region(vaddr, len)); + + uint32_t mmu_val; + uint32_t entry_id; + uint32_t page_num = (len + MMU_PAGE_SIZE - 1) / MMU_PAGE_SIZE; + uint32_t ret = page_num * MMU_PAGE_SIZE; + mmu_val = paddr >> 16; + bool write_back = false; + + while (page_num) + { + entry_id = (vaddr & MMU_VADDR_MASK) >> 16; + DEBUGASSERT(entry_id < MMU_ENTRY_NUM); + if (write_back == false && FLASH_MMU_TABLE[entry_id] != MMU_INVALID) + { + esp_spiram_writeback_cache(); + write_back = true; + } + + FLASH_MMU_TABLE[entry_id] = mmu_val | mem_type; + vaddr += MMU_PAGE_SIZE; + mmu_val++; + page_num--; + } + + return ret; +} + /**************************************************************************** * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: cache_dbus_mmu_map + * + * Description: + * Set Ext-SRAM-Cache mmu mapping. + * + * Input Parameters: + * vaddr - Virtual address in CPU address space + * paddr - Physical address in Ext-SRAM + * num - Pages to be set + * + * Returned Value: + * 0 if success or a negative value if fail. + * + ****************************************************************************/ + +int IRAM_ATTR cache_dbus_mmu_map(int vaddr, int paddr, int num) +{ + uint32_t regval; + irqstate_t flags; + uint32_t actual_mapped_len; + uint32_t cache_state[CONFIG_SMP_NCPUS]; + int cpu = up_cpu_index(); +#ifdef CONFIG_SMP + bool smp_start = OSINIT_OS_READY(); + int other_cpu = cpu ? 0 : 1; +#endif + + /* The MMU registers are implemented in such a way that lookups from the + * cache subsystem may collide with CPU access to the MMU registers. We use + * cache_suspend_dcache to make sure the cache is disabled. + */ + + flags = enter_critical_section(); + +#ifdef CONFIG_SMP + /* The other CPU might be accessing the cache at the same time, just by + * using variables in external RAM. + */ + + if (smp_start) + { + up_cpu_pause(other_cpu); + } + + cache_state[other_cpu] = cache_suspend_dcache(); +#endif + cache_state[cpu] = cache_suspend_dcache(); + + esp_mmu_map_region(vaddr, paddr, num * MMU_PAGE_SIZE, MMU_ACCESS_SPIRAM); + + regval = getreg32(EXTMEM_DCACHE_CTRL1_REG); + regval &= ~EXTMEM_DCACHE_SHUT_CORE0_BUS; + putreg32(regval, EXTMEM_DCACHE_CTRL1_REG); + +#if defined(CONFIG_SMP) + regval = getreg32(EXTMEM_DCACHE_CTRL1_REG); + regval &= ~EXTMEM_DCACHE_SHUT_CORE1_BUS; + putreg32(regval, EXTMEM_DCACHE_CTRL1_REG); +#endif + + cache_invalidate_addr(vaddr, num * MMU_PAGE_SIZE); + + cache_resume_dcache(cache_state[cpu]); + +#ifdef CONFIG_SMP + cache_resume_dcache(cache_state[other_cpu]); + if (smp_start) + { + up_cpu_resume(other_cpu); + } +#endif + + leave_critical_section(flags); + return 0; +} + /* Initially map all psram physical address to virtual address. * If psram physical size is larger than virtual address range, then only * map the virtual address range. @@ -354,7 +552,7 @@ int IRAM_ATTR instruction_flash2spiram_offset(void) } #endif -#if defined(CONFIG_ESP32_SPIRAM_RODATA) +#if defined(CONFIG_ESP32S3_SPIRAM_RODATA) void rodata_flash_page_info_init(void) { uint32_t rodata_page_cnt = ((uint32_t)_rodata_reserved_end - diff --git a/arch/xtensa/src/esp32s3/esp32s3_spiram.h b/arch/xtensa/src/esp32s3/esp32s3_spiram.h index be46bf53a9709..6bd24ec7ccbd3 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spiram.h +++ b/arch/xtensa/src/esp32s3/esp32s3_spiram.h @@ -34,6 +34,24 @@ extern "C" { #endif +/**************************************************************************** + * Name: cache_dbus_mmu_map + * + * Description: + * Set Ext-SRAM-Cache mmu mapping. + * + * Input Parameters: + * vaddr - Virtual address in CPU address space + * paddr - Physical address in Ext-SRAM + * num - Pages to be set + * + * Returned Value: + * 0 if success or a negative value if fail. + * + ****************************************************************************/ + +int cache_dbus_mmu_map(int vaddr, int paddr, int num); + /* Initialize spiram interface/hardware. Normally called from * cpu_start.c. * diff --git a/arch/xtensa/src/esp32s3/esp32s3_start.c b/arch/xtensa/src/esp32s3/esp32s3_start.c index 891d7a58a3592..922dec107f8f4 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_start.c +++ b/arch/xtensa/src/esp32s3/esp32s3_start.c @@ -31,13 +31,12 @@ #include #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "esp32s3_start.h" #include "esp32s3_lowputc.h" #include "esp32s3_clockconfig.h" #include "esp32s3_region.h" -#include "esp32s3_periph.h" #include "esp32s3_rtc.h" #include "esp32s3_spiram.h" #include "esp32s3_wdt.h" @@ -47,10 +46,29 @@ #include "esp32s3_spi_timing.h" #include "hardware/esp32s3_cache_memory.h" #include "hardware/esp32s3_system.h" -#include "hardware/esp32s3_extmem.h" #include "rom/esp32s3_libc_stubs.h" +#include "rom/opi_flash.h" #include "rom/esp32s3_spiflash.h" -#include "rom/esp32s3_opi_flash.h" + +#include "hal/mmu_hal.h" +#include "hal/mmu_types.h" +#include "hal/cache_types.h" +#include "hal/cache_ll.h" +#include "hal/cache_hal.h" +#include "soc/extmem_reg.h" +#include "rom/cache.h" +#include "spi_flash_mmap.h" + +#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT +# include "bootloader_init.h" +# include "bootloader_flash_priv.h" +# include "esp_rom_uart.h" +# include "esp_rom_sys.h" +# include "esp_app_format.h" +#endif + +#include "esp_clk_internal.h" +#include "periph_ctrl.h" /**************************************************************************** * Pre-processor Definitions @@ -62,15 +80,55 @@ # define showprogress(c) #endif -#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT +#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) +# ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT +# define PRIMARY_SLOT_OFFSET CONFIG_ESP32S3_OTA_PRIMARY_SLOT_OFFSET + /* Cache MMU address mask (MMU tables ignore bits which are zero) */ -#define PRIMARY_SLOT_OFFSET CONFIG_ESP32S3_OTA_PRIMARY_SLOT_OFFSET +# define MMU_FLASH_MASK (~(MMU_PAGE_SIZE - 1)) +# else + /* Force offset to the beginning of the whole image */ -#define HDR_ATTR locate_code(".entry_addr") used_code +# define PRIMARY_SLOT_OFFSET 0 +# endif +# define HDR_ATTR __attribute__((section(".entry_addr"))) \ + __attribute__((used)) +# define MMU_BLOCK_SIZE 0x00010000 /* 64 KB */ +# define CACHE_REG EXTMEM_ICACHE_CTRL1_REG +# define CACHE_MASK (EXTMEM_ICACHE_SHUT_IBUS_M | \ + EXTMEM_ICACHE_SHUT_DBUS_M) + +# define CHECKSUM_ALIGN 16 +# define IS_PADD(addr) (addr == 0) +# define IS_DRAM(addr) (addr >= SOC_DRAM_LOW && addr < SOC_DRAM_HIGH) +# define IS_IRAM(addr) (addr >= SOC_IRAM_LOW && addr < SOC_IRAM_HIGH) +# define IS_IROM(addr) (addr >= SOC_IROM_LOW && addr < SOC_IROM_HIGH) +# define IS_DROM(addr) (addr >= SOC_DROM_LOW && addr < SOC_DROM_HIGH) +# define IS_SRAM(addr) (IS_IRAM(addr) || IS_DRAM(addr)) +# define IS_MMAP(addr) (IS_IROM(addr) || IS_DROM(addr)) +# ifdef SOC_RTC_FAST_MEM_SUPPORTED +# define IS_RTC_FAST_IRAM(addr) \ + (addr >= SOC_RTC_IRAM_LOW && addr < SOC_RTC_IRAM_HIGH) +# define IS_RTC_FAST_DRAM(addr) \ + (addr >= SOC_RTC_DRAM_LOW && addr < SOC_RTC_DRAM_HIGH) +# else +# define IS_RTC_FAST_IRAM(addr) 0 +# define IS_RTC_FAST_DRAM(addr) 0 +# endif +# ifdef SOC_RTC_SLOW_MEM_SUPPORTED +# define IS_RTC_SLOW_DRAM(addr) \ + (addr >= SOC_RTC_DATA_LOW && addr < SOC_RTC_DATA_HIGH) +# else +# define IS_RTC_SLOW_DRAM(addr) 0 +# endif -/* Cache MMU address mask (MMU tables ignore bits which are zero) */ +# define IS_NONE(addr) (!IS_IROM(addr) && !IS_DROM(addr) \ + && !IS_IRAM(addr) && !IS_DRAM(addr) \ + && !IS_RTC_FAST_IRAM(addr) && !IS_RTC_FAST_DRAM(addr) \ + && !IS_RTC_SLOW_DRAM(addr) && !IS_PADD(addr)) -#define MMU_FLASH_MASK (~(MMU_PAGE_SIZE - 1)) +# define IS_MAPPING(addr) IS_IROM(addr) || IS_DROM(addr) #endif @@ -78,7 +136,8 @@ * Private Types ****************************************************************************/ -#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT +#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) extern uint8_t _image_irom_vma[]; extern uint8_t _image_irom_lma[]; extern uint8_t _image_irom_size[]; @@ -92,14 +151,9 @@ extern uint8_t _image_drom_size[]; * ROM Function Prototypes ****************************************************************************/ -#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT +#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) extern int ets_printf(const char *fmt, ...) printf_like(1, 2); -extern int cache_dbus_mmu_set(uint32_t ext_ram, uint32_t vaddr, - uint32_t paddr, uint32_t psize, uint32_t num, - uint32_t fixed); -extern int cache_ibus_mmu_set(uint32_t ext_ram, uint32_t vaddr, - uint32_t paddr, uint32_t psize, uint32_t num, - uint32_t fixed); #endif extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size, @@ -120,7 +174,6 @@ extern void cache_set_idrom_mmu_info(uint32_t instr_page_num, int i_off, int ro_off); #ifdef CONFIG_ESP32S3_DATA_CACHE_16KB -extern void cache_invalidate_dcache_all(void); extern int cache_occupy_addr(uint32_t addr, uint32_t size); #endif @@ -128,15 +181,17 @@ extern int cache_occupy_addr(uint32_t addr, uint32_t size); * Private Function Prototypes ****************************************************************************/ -#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT -noreturn_function void __start(void); +#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) +IRAM_ATTR noreturn_function void __start(void); #endif /**************************************************************************** * Private Data ****************************************************************************/ -#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT +#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \ + defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) HDR_ATTR static void (*_entry_point)(void) = __start; #endif @@ -144,6 +199,8 @@ HDR_ATTR static void (*_entry_point)(void) = __start; * Public Data ****************************************************************************/ +extern uint8_t _instruction_reserved_start[]; +extern uint8_t _instruction_reserved_end[]; extern uint8_t _rodata_reserved_start[]; extern uint8_t _rodata_reserved_end[]; @@ -174,6 +231,17 @@ noinstrument_function static void IRAM_ATTR configure_cpu_caches(void) { int s_instr_flash2spiram_off = 0; int s_rodata_flash2spiram_off = 0; + uint32_t _instruction_size = (uint32_t)&_instruction_reserved_end - + (uint32_t)&_instruction_reserved_start; + uint32_t cache_mmu_irom_size = + ((_instruction_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / + SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t); + + uint32_t _rodata_size = (uint32_t)&_rodata_reserved_end - + (uint32_t)&_rodata_reserved_start; + uint32_t cache_mmu_drom_size = + ((_rodata_size + SPI_FLASH_MMU_PAGE_SIZE - 1) / + SPI_FLASH_MMU_PAGE_SIZE) * sizeof(uint32_t); /* Configure the mode of instruction cache: cache size, cache line size. */ @@ -193,20 +261,16 @@ noinstrument_function static void IRAM_ATTR configure_cpu_caches(void) /* Configure the Cache MMU size for instruction and rodata in flash. */ - uint32_t rodata_reserved_start_align = - (uint32_t)_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1); - uint32_t cache_mmu_irom_size = - ((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) * - sizeof(uint32_t); - - uint32_t cache_mmu_drom_size = - (((uint32_t)_rodata_reserved_end - rodata_reserved_start_align + - MMU_PAGE_SIZE - 1) / - MMU_PAGE_SIZE) * sizeof(uint32_t); - cache_set_idrom_mmu_size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size); +#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS + s_instr_flash2spiram_off = instruction_flash2spiram_offset(); +#endif +#if CONFIG_SPIRAM_RODATA + s_rodata_flash2spiram_off = rodata_flash2spiram_offset(); +#endif + cache_set_idrom_mmu_info(cache_mmu_irom_size / sizeof(uint32_t), cache_mmu_drom_size / sizeof(uint32_t), (uint32_t)_rodata_reserved_start, @@ -297,6 +361,7 @@ noinstrument_function void noreturn_function IRAM_ATTR __esp32s3_start(void) esp32s3_region_protection(); +#ifndef CONFIG_ESPRESSIF_SIMPLE_BOOT /* Move CPU0 exception vectors to IRAM */ __asm__ __volatile__ ("wsr %0, vecbase\n"::"r" (_init_start)); @@ -309,6 +374,7 @@ noinstrument_function void noreturn_function IRAM_ATTR __esp32s3_start(void) { *dest++ = 0; } +#endif #ifndef CONFIG_SMP /* Make sure that the APP_CPU is disabled for now */ @@ -334,7 +400,7 @@ noinstrument_function void noreturn_function IRAM_ATTR __esp32s3_start(void) /* Initialize peripherals parameters */ - esp32s3_perip_clk_init(); + esp_perip_clk_init(); #ifndef CONFIG_SUPPRESS_UART_CONFIG /* Configure the UART so we can get debug output */ @@ -408,29 +474,6 @@ noinstrument_function void noreturn_function IRAM_ATTR __esp32s3_start(void) for (; ; ); /* Should not return */ } -/**************************************************************************** - * Name: calc_mmu_pages - * - * Description: - * Calculate the number of cache pages to map. - * - * Input Parameters: - * size - Size of data to map - * vaddr - Virtual address where data will be mapped - * - * Returned Value: - * Number of cache MMU pages required to do the mapping. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT -static inline uint32_t calc_mmu_pages(uint32_t size, uint32_t vaddr) -{ - return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_PAGE_SIZE - 1) / - MMU_PAGE_SIZE; -} -#endif - /**************************************************************************** * Name: map_rom_segments * @@ -445,55 +488,155 @@ static inline uint32_t calc_mmu_pages(uint32_t size, uint32_t vaddr) * ****************************************************************************/ -#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT -static int map_rom_segments(void) +#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \ + defined(CONFIG_ESPRESSIF_SIMPLE_BOOT) +static int map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, + uint32_t app_drom_size, uint32_t app_irom_start, + uint32_t app_irom_vaddr, uint32_t app_irom_size) { uint32_t rc = 0; - uint32_t regval; - uint32_t drom_lma_aligned; - uint32_t drom_vma_aligned; - uint32_t drom_page_count; - uint32_t irom_lma_aligned; - uint32_t irom_vma_aligned; - uint32_t irom_page_count; + uint32_t actual_mapped_len = 0; + uint32_t app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK; + uint32_t app_irom_vaddr_aligned = app_irom_vaddr & MMU_FLASH_MASK; + uint32_t app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK; + uint32_t app_drom_vaddr_aligned = app_drom_vaddr & MMU_FLASH_MASK; + +#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT + esp_image_header_t image_header; /* Header for entire image */ + esp_image_segment_header_t WORD_ALIGNED_ATTR segment_hdr; + bool padding_checksum = false; + unsigned int segments = 0; + unsigned int ram_segments = 0; + unsigned int rom_segments = 0; + size_t offset = CONFIG_BOOTLOADER_OFFSET_IN_FLASH; + + /* Read image header */ + + if (bootloader_flash_read(offset, &image_header, + sizeof(esp_image_header_t), + true) != ESP_OK) + { + ets_printf("Failed to load image header!\n"); + abort(); + } - size_t partition_offset = PRIMARY_SLOT_OFFSET; - uint32_t app_irom_lma = partition_offset + (uint32_t)_image_irom_lma; - uint32_t app_irom_size = (uint32_t)_image_irom_size; - uint32_t app_irom_vma = (uint32_t)_image_irom_vma; - uint32_t app_drom_lma = partition_offset + (uint32_t)_image_drom_lma; - uint32_t app_drom_size = (uint32_t)_image_drom_size; - uint32_t app_drom_vma = (uint32_t)_image_drom_vma; - - uint32_t autoload = cache_suspend_dcache(); - cache_invalidate_dcache_all(); + offset += sizeof(esp_image_header_t); - /* Clear the MMU entries that are already set up, so the new app only has - * the mappings it creates. - */ + /* Iterate for segment information parsing */ + + while (segments++ < 16 && rom_segments < 2) + { + /* Read segment header */ + + if (bootloader_flash_read(offset, &segment_hdr, + sizeof(esp_image_segment_header_t), + true) != ESP_OK) + { + ets_printf("failed to read segment header at %x\n", offset); + abort(); + } + + if (IS_NONE(segment_hdr.load_addr)) + { + break; + } + + if (IS_RTC_FAST_IRAM(segment_hdr.load_addr) || + IS_RTC_FAST_DRAM(segment_hdr.load_addr) || + IS_RTC_SLOW_DRAM(segment_hdr.load_addr)) + { + /* RTC segment is loaded by ROM bootloader */ + + ram_segments++; + } + + ets_printf("%s: lma 0x%08x vma 0x%08x len 0x%-6x (%u)\n", + IS_NONE(segment_hdr.load_addr) ? "???" : + IS_RTC_FAST_IRAM(segment_hdr.load_addr) || + IS_RTC_FAST_DRAM(segment_hdr.load_addr) || + IS_RTC_SLOW_DRAM(segment_hdr.load_addr) ? "rtc" : + IS_MMAP(segment_hdr.load_addr) ? + IS_IROM(segment_hdr.load_addr) ? "imap" : "dmap" : + IS_PADD(segment_hdr.load_addr) ? "padd" : + IS_DRAM(segment_hdr.load_addr) ? "dram" : "iram", + offset + sizeof(esp_image_segment_header_t), + segment_hdr.load_addr, segment_hdr.data_len, + segment_hdr.data_len); + + /* Fix drom and irom produced be the linker, as this + * is later invalidated by the elf2image command. + */ + + if (IS_DROM(segment_hdr.load_addr) && + segment_hdr.load_addr == (uint32_t)_image_drom_vma) + { + app_drom_start = offset + sizeof(esp_image_segment_header_t); + app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK; + rom_segments++; + } + + if (IS_IROM(segment_hdr.load_addr) && + segment_hdr.load_addr == (uint32_t)_image_irom_vma) + { + app_irom_start = offset + sizeof(esp_image_segment_header_t); + app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK; + rom_segments++; + } + + if (IS_SRAM(segment_hdr.load_addr)) + { + ram_segments++; + } + + offset += sizeof(esp_image_segment_header_t) + segment_hdr.data_len; + if (ram_segments == image_header.segment_count && !padding_checksum) + { + offset += (CHECKSUM_ALIGN - 1) - (offset % CHECKSUM_ALIGN) + 1; + padding_checksum = true; + } + } - for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) + if (segments == 0 || segments == 16) { - FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL; + ets_printf("Error parsing segments\n"); } - drom_lma_aligned = app_drom_lma & MMU_FLASH_MASK; - drom_vma_aligned = app_drom_vma & MMU_FLASH_MASK; - drom_page_count = calc_mmu_pages(app_drom_size, app_drom_vma); - rc = cache_dbus_mmu_set(MMU_ACCESS_FLASH, drom_vma_aligned, - drom_lma_aligned, 64, drom_page_count, 0); + ets_printf("total segments stored %d\n", segments - 1); +#endif + + cache_hal_disable(CACHE_TYPE_ALL); + + /* Clear the MMU entries that are already set up, + * so the new app only has the mappings it creates. + */ - irom_lma_aligned = app_irom_lma & MMU_FLASH_MASK; - irom_vma_aligned = app_irom_vma & MMU_FLASH_MASK; - irom_page_count = calc_mmu_pages(app_irom_size, app_irom_vma); - rc = cache_ibus_mmu_set(MMU_ACCESS_FLASH, irom_vma_aligned, - irom_lma_aligned, 64, irom_page_count, 0); + mmu_hal_unmap_all(); - regval = getreg32(EXTMEM_DCACHE_CTRL1_REG); - regval &= EXTMEM_DCACHE_SHUT_CORE0_BUS; - putreg32(regval, EXTMEM_DCACHE_CTRL1_REG); + mmu_hal_map_region(0, MMU_TARGET_FLASH0, + app_drom_vaddr_aligned, app_drom_start_aligned, + app_drom_size, &actual_mapped_len); - cache_resume_dcache(autoload); + mmu_hal_map_region(0, MMU_TARGET_FLASH0, + app_irom_vaddr_aligned, app_irom_start_aligned, + app_irom_size, &actual_mapped_len); + + /* ------------------Enable corresponding buses--------------------- */ + + cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, app_drom_vaddr_aligned, + app_drom_size); + cache_ll_l1_enable_bus(0, bus_mask); + bus_mask = cache_ll_l1_get_bus(0, app_irom_vaddr_aligned, app_irom_size); + cache_ll_l1_enable_bus(0, bus_mask); +#if CONFIG_ESPRESSIF_NUM_CPUS > 1 + bus_mask = cache_ll_l1_get_bus(1, app_drom_vaddr_aligned, app_drom_size); + cache_ll_l1_enable_bus(1, bus_mask); + bus_mask = cache_ll_l1_get_bus(1, app_irom_vaddr_aligned, app_irom_size); + cache_ll_l1_enable_bus(1, bus_mask); +#endif + + /* ------------------Enable Cache----------------------------------- */ + + cache_hal_enable(CACHE_TYPE_ALL); return (int)rc; } @@ -518,14 +661,34 @@ static int map_rom_segments(void) noinstrument_function void IRAM_ATTR __start(void) { -#ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT - if (map_rom_segments() != 0) +#if defined(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT) || \ + defined(CONFIG_ESPRESSIF_SIMPLE_BOOT) + size_t partition_offset = PRIMARY_SLOT_OFFSET; + uint32_t app_irom_start = partition_offset + (uint32_t)_image_irom_lma; + uint32_t app_irom_size = (uint32_t)_image_irom_size; + uint32_t app_irom_vaddr = (uint32_t)_image_irom_vma; + uint32_t app_drom_start = partition_offset + (uint32_t)_image_drom_lma; + uint32_t app_drom_size = (uint32_t)_image_drom_size; + uint32_t app_drom_vaddr = (uint32_t)_image_drom_vma; + +# ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT + __asm__ __volatile__ ("wsr %0, vecbase\n"::"r" (_init_start)); + + if (bootloader_init() != 0) { - ets_printf("Failed to setup XIP, aborting\n"); + ets_printf("Hardware init failed, aborting\n"); while (true); } +# endif + if (map_rom_segments(app_drom_start, app_drom_vaddr, app_drom_size, + app_irom_start, app_irom_vaddr, app_irom_size) != 0) + { + ets_printf("Failed to setup XIP, aborting\n"); + while (true); + } #endif + configure_cpu_caches(); __esp32s3_start(); diff --git a/arch/xtensa/src/esp32s3/esp32s3_textheap.c b/arch/xtensa/src/esp32s3/esp32s3_textheap.c index d6d1907fcc96e..29d4df36f752e 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_textheap.c +++ b/arch/xtensa/src/esp32s3/esp32s3_textheap.c @@ -31,21 +31,22 @@ #include #include +#include "hal/cache_hal.h" #include "hardware/esp32s3_soc.h" #ifdef CONFIG_ESP32S3_RTC_HEAP # include "esp32s3_rtcheap.h" #endif +#include "esp32s3_spiram.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#ifndef CONFIG_ESP32S3_RTC_HEAP -#error "No suitable heap available. Enable ESP32S3_RTC_HEAP." -#endif +#define EXTRAM_INSTRUCTION_BUS_LOW 0x42000000 +#define EXTRAM_INSTRUCTION_BUS_HIGH 0x44000000 -#define D_I_BUS_OFFSET 0x700000 +#define EXTRAM_D_I_BUS_OFFSET 0x6000000 /**************************************************************************** * Public Functions @@ -92,7 +93,19 @@ void *up_textheap_memalign(size_t align, size_t size) * can access it from the Instruction bus. */ - ret += D_I_BUS_OFFSET; + uintptr_t addr = (uintptr_t)ret; + if (SOC_DIRAM_DRAM_LOW <= addr && addr < SOC_DIRAM_DRAM_HIGH) + { + addr = MAP_DRAM_TO_IRAM(addr); + } + else + { + /* extram */ + + addr += EXTRAM_D_I_BUS_OFFSET; + } + + ret = (void *)addr; } } @@ -122,7 +135,7 @@ void up_textheap_free(void *p) else #endif { - p -= D_I_BUS_OFFSET; + p = up_textheap_data_address(p); kmm_free(p); } } @@ -156,6 +169,63 @@ bool up_textheap_heapmember(void *p) } #endif - p -= D_I_BUS_OFFSET; + p = up_textheap_data_address(p); return kmm_heapmember(p); } + +/**************************************************************************** + * Name: up_textheap_data_address + * + * Description: + * If an instruction bus address is specified, return the corresponding + * data bus address. Otherwise, return the given address as it is. + * + * For some platforms, up_textheap_memalign() might return memory regions + * with separate instruction/data bus mappings. In that case, + * up_textheap_memalign() returns the address of the instruction bus + * mapping. + * The instruction bus mapping might provide only limited data access. + * (For example, only read-only, word-aligned access.) + * You can use up_textheap_data_address() to query the corresponding data + * bus mapping. + * + ****************************************************************************/ + +FAR void *up_textheap_data_address(FAR void *p) +{ + uintptr_t addr = (uintptr_t)p; + if (SOC_DIRAM_IRAM_LOW <= addr && addr < SOC_DIRAM_IRAM_HIGH) + { + addr = MAP_IRAM_TO_DRAM(addr); + } + else if (EXTRAM_INSTRUCTION_BUS_LOW <= addr && + addr < EXTRAM_INSTRUCTION_BUS_HIGH) + { + /* extram */ + + addr -= EXTRAM_D_I_BUS_OFFSET; + } + + return (FAR void *)addr; +} + +/**************************************************************************** + * Name: up_textheap_data_sync + * + * Description: + * Ensure modifications made on the data bus addresses (the addresses + * returned by up_textheap_data_address) fully visible on the corresponding + * instruction bus addresses. + * + ****************************************************************************/ + +IRAM_ATTR void up_textheap_data_sync(void) +{ + irqstate_t flags = enter_critical_section(); + + esp_spiram_writeback_cache(); + cache_hal_disable(CACHE_TYPE_INSTRUCTION); + cache_hal_enable(CACHE_TYPE_INSTRUCTION); + + leave_critical_section(flags); +} diff --git a/arch/xtensa/src/esp32s3/esp32s3_twai.c b/arch/xtensa/src/esp32s3/esp32s3_twai.c index d7fb0adb0ee5a..c1e54d5b549cf 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_twai.c +++ b/arch/xtensa/src/esp32s3/esp32s3_twai.c @@ -44,9 +44,11 @@ #include "esp32s3_twai.h" #include "esp32s3_irq.h" #include "esp32s3_clockconfig.h" -#include "esp32s3_periph.h" + +#include "periph_ctrl.h" #include "hardware/esp32s3_system.h" +#include "hardware/esp32s3_twai.h" #include "hardware/esp32s3_gpio_sigmap.h" #if defined(CONFIG_ESP32S3_TWAI) @@ -1241,7 +1243,7 @@ struct can_dev_s *esp32s3_twaiinitialize(void) * Enable clocking to the TWAI module */ - esp32s3_periph_module_enable(PERIPH_TWAI_MODULE); + periph_module_enable(PERIPH_TWAI_MODULE); /* Configure CAN GPIO pins */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_twai.h b/arch/xtensa/src/esp32s3/esp32s3_twai.h index 7d1cb0ec03431..3bc91016f789a 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_twai.h +++ b/arch/xtensa/src/esp32s3/esp32s3_twai.h @@ -27,7 +27,6 @@ #include #include -#include "hardware/esp32s3_twai.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/xtensa/src/esp32s3/esp32s3_userspace.c b/arch/xtensa/src/esp32s3/esp32s3_userspace.c index ca94a1eef5ee6..29edf861f0cfb 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_userspace.c +++ b/arch/xtensa/src/esp32s3/esp32s3_userspace.c @@ -35,17 +35,18 @@ #include "chip.h" #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "esp32s3_irq.h" #include "esp32s3_userspace.h" #include "hardware/esp32s3_apb_ctrl.h" #include "hardware/esp32s3_cache_memory.h" -#include "hardware/esp32s3_extmem.h" #include "hardware/esp32s3_rom_layout.h" #include "hardware/esp32s3_sensitive.h" #include "hardware/esp32s3_soc.h" #include "hardware/esp32s3_wcl_core.h" +#include "soc/extmem_reg.h" + #ifdef CONFIG_BUILD_PROTECTED /**************************************************************************** @@ -80,9 +81,6 @@ #define WCL_SEQ_LAST_VAL 6 -#define I_D_SRAM_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW) -#define MAP_IRAM_TO_DRAM(addr) ((addr) - I_D_SRAM_OFFSET) - /* Categories bits for split line configuration */ #define PMS_SRAM_CATEGORY_BELOW 0x0 diff --git a/arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.c b/arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.c index 38986cb3944b2..ed9af91f97533 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.c +++ b/arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.c @@ -590,7 +590,7 @@ static xcpt_t wdt_lh_capture(struct watchdog_lowerhalf_s *lower, DEBUGASSERT(priv); - wdinfo("Entry: handler=0x%" PRIxPTR "\n", (uintptr_t) handler); + wdinfo("Entry: handler=%p\n", handler); /* Get the old handler to return it */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c index 74c40e541b308..f33434a66c518 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c +++ b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c @@ -54,7 +54,7 @@ #include #include "xtensa.h" -#include "xtensa_attr.h" +#include "esp_attr.h" #include "hardware/esp32s3_system.h" #include "hardware/esp32s3_rtccntl.h" #include "hardware/esp32s3_syscon.h" @@ -77,7 +77,16 @@ # endif #endif -#include "esp_hal_wifi.h" +#include "esp_log.h" +#include "esp_mac.h" +#include "esp_private/phy.h" +#include "esp_private/wifi.h" +#include "esp_random.h" +#include "esp_timer.h" +#include "esp_wpa.h" +#include "periph_ctrl.h" +#include "rom/ets_sys.h" +#include "soc/soc_caps.h" /**************************************************************************** * Pre-processor Definitions @@ -100,7 +109,7 @@ #define DEFAULT_LISTEN_INTERVAL CONFIG_EXAMPLE_WIFI_LISTEN_INTERVAL -#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal +#define RTC_CLK_CAL_FRACT 19 /* Number of fractional bits in values returned by rtc_clk_cal */ #define ets_timer _ETSTIMER_ @@ -116,6 +125,8 @@ # define DEFAULT_PS_MODE WIFI_PS_NONE #endif +#define ESP_MAX_PRIORITIES (25) + /**************************************************************************** * Private Types ****************************************************************************/ @@ -270,6 +281,7 @@ static void wifi_clock_enable(void); static void wifi_clock_disable(void); static void wifi_rtc_enable_iso(void); static void wifi_rtc_disable_iso(void); +static int64_t esp32s3_timer_get_time(void); static int32_t esp_nvs_set_i8(uint32_t handle, const char *key, int8_t value); static int32_t esp_nvs_get_i8(uint32_t handle, const char *key, @@ -334,15 +346,6 @@ static int coex_register_start_cb_wrapper(int (* cb)(void)); static int coex_schm_process_restart_wrapper(void); static int coex_schm_register_cb_wrapper(int type, int(*cb)(int)); -/**************************************************************************** - * Public Functions declaration - ****************************************************************************/ - -int64_t esp_timer_get_time(void); -void esp_fill_random(void *buf, size_t len); -uint32_t esp_log_timestamp(void); -uint8_t esp_crc8(const uint8_t *p, uint32_t len); - /**************************************************************************** * Private Data ****************************************************************************/ @@ -422,7 +425,7 @@ coex_adapter_funcs_t g_coex_adapter_funcs = ._is_in_isr = is_in_isr_wrapper, ._malloc_internal = esp_malloc_internal, ._free = esp_free, - ._esp_timer_get_time = esp_timer_get_time, + ._esp_timer_get_time = esp32s3_timer_get_time, ._timer_disarm = esp_timer_disarm, ._timer_done = esp32s3_timer_done, ._timer_setfn = esp_timer_setfn, @@ -489,8 +492,8 @@ wifi_osi_funcs_t g_wifi_osi_funcs = esp_dport_access_stall_other_cpu_end, ._wifi_apb80m_request = wifi_apb80m_request, ._wifi_apb80m_release = wifi_apb80m_release, - ._phy_disable = esp32s3_phy_disable, - ._phy_enable = esp32s3_phy_enable, + ._phy_disable = esp_phy_disable, + ._phy_enable = esp_phy_enable, ._phy_update_country_info = esp32s3_phy_update_country_info, ._read_mac = esp_wifi_read_mac, ._timer_arm = esp_timer_arm, @@ -503,7 +506,7 @@ wifi_osi_funcs_t g_wifi_osi_funcs = ._wifi_clock_disable = wifi_clock_disable, ._wifi_rtc_enable_iso = wifi_rtc_enable_iso, ._wifi_rtc_disable_iso = wifi_rtc_disable_iso, - ._esp_timer_get_time = esp_timer_get_time, + ._esp_timer_get_time = esp32s3_timer_get_time, ._nvs_set_i8 = esp_nvs_set_i8, ._nvs_get_i8 = esp_nvs_get_i8, ._nvs_set_u8 = esp_nvs_set_u8, @@ -912,7 +915,6 @@ static bool IRAM_ATTR wifi_is_from_isr(void) static void *esp_spin_lock_create(void) { -#ifdef CONFIG_SMP spinlock_t *lock; int tmp; @@ -927,11 +929,6 @@ static void *esp_spin_lock_create(void) spin_initialize(lock, SP_UNLOCKED); return lock; -#else - /* If return NULL, code may check fail */ - - return (void *)1; -#endif } /**************************************************************************** @@ -950,11 +947,7 @@ static void *esp_spin_lock_create(void) static void esp_spin_lock_delete(void *lock) { -#ifdef CONFIG_SMP kmm_free(lock); -#else - DEBUGASSERT((int)lock == 1); -#endif } /**************************************************************************** @@ -1809,9 +1802,15 @@ static int32_t esp_task_create_pinned_to_core(void *entry, int ret; cpu_set_t cpuset; #endif + uint32_t target_prio = prio; - pid = kthread_create(name, prio, stack_depth, entry, - (char * const *)param); + if (target_prio < ESP_MAX_PRIORITIES) + { + target_prio += esp_task_get_max_priority() - ESP_MAX_PRIORITIES; + } + + pid = kthread_create(name, target_prio, stack_depth, entry, + (char * const *)param); if (pid > 0) { if (task_handle != NULL) @@ -2741,8 +2740,7 @@ static void esp_timer_arm_us(void *ptimer, uint32_t us, bool repeat) static void wifi_reset_mac(void) { - modifyreg32(SYSCON_WIFI_RST_EN_REG, 0, SYSTEM_WIFIMAC_RST); - modifyreg32(SYSCON_WIFI_RST_EN_REG, SYSTEM_WIFIMAC_RST, 0); + periph_module_reset(PERIPH_WIFI_MODULE); } /**************************************************************************** @@ -2761,7 +2759,7 @@ static void wifi_reset_mac(void) static void wifi_clock_enable(void) { - modifyreg32(SYSTEM_WIFI_CLK_EN_REG, 0, SYSTEM_WIFI_CLK_WIFI_EN_M); + wifi_module_enable(); } /**************************************************************************** @@ -2780,7 +2778,7 @@ static void wifi_clock_enable(void) static void wifi_clock_disable(void) { - modifyreg32(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_WIFI_EN_M, 0); + wifi_module_disable(); } /**************************************************************************** @@ -2808,7 +2806,7 @@ static void wifi_rtc_disable_iso(void) } /**************************************************************************** - * Name: esp_timer_get_time + * Name: esp32s3_timer_get_time * * Description: * Get system time of type int64_t @@ -2821,7 +2819,7 @@ static void wifi_rtc_disable_iso(void) * ****************************************************************************/ -int64_t esp_timer_get_time(void) +int64_t esp32s3_timer_get_time(void) { return (int64_t)esp32s3_rt_timer_time_us(); } @@ -3109,38 +3107,6 @@ static int32_t esp_nvs_erase_key(uint32_t handle, const char *key) return -1; } -/**************************************************************************** - * Name: esp_fill_random - * - * Description: - * Fill random data int given buffer of given length - * - * Input Parameters: - * buf - buffer pointer - * len - buffer length - * - * Returned Value: - * - ****************************************************************************/ - -void esp_fill_random(void *buf, size_t len) -{ - uint8_t *p = (uint8_t *)buf; - uint32_t tmp; - uint32_t n; - - while (len > 0) - { - tmp = esp_random(); - n = len < 4 ? len : 4; - - memcpy(p, &tmp, n); - - p += n; - len -= n; - } -} - /**************************************************************************** * Name: esp_get_random * @@ -3438,10 +3404,13 @@ static void *esp_calloc_internal(size_t n, size_t size) return xtensa_imm_calloc(n, size); #else void *ptr = kmm_calloc(n, size); - if (esp32s3_ptr_extram(ptr)) + if (ptr != NULL) { - kmm_free(ptr); - return NULL; + if (esp32s3_ptr_extram(ptr)) + { + kmm_free(ptr); + return NULL; + } } return ptr; @@ -3470,10 +3439,13 @@ static void *esp_zalloc_internal(size_t size) return xtensa_imm_zalloc(size); #else void *ptr = kmm_zalloc(size); - if (esp32s3_ptr_extram(ptr)) + if (ptr != NULL) { - kmm_free(ptr); - return NULL; + if (esp32s3_ptr_extram(ptr)) + { + kmm_free(ptr); + return NULL; + } } return ptr; @@ -4135,6 +4107,8 @@ static IRAM_ATTR void esp_wifi_tx_done_cb(uint8_t ifidx, uint8_t *data, } } +#ifdef ESP32S3_WLAN_HAS_STA + /**************************************************************************** * Name: esp_wifi_auth_trans * @@ -4235,6 +4209,8 @@ static int esp_wifi_cipher_trans(uint32_t wifi_cipher) return cipher_mode; } +#endif /* ESP32S3_WLAN_HAS_STA */ + /**************************************************************************** * Name: esp_freq_to_channel * @@ -4390,10 +4366,6 @@ int coexist_printf(const char *format, ...) return 0; } -/**************************************************************************** - * Functions needed by libwpa_supplicant.a - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -4430,88 +4402,6 @@ int32_t esp_event_send_internal(esp_event_base_t event_base, return ret; } -/**************************************************************************** - * Name: esp_wifi_init - * - * Description: - * Initialize Wi-Fi - * - * Input Parameters: - * config - Initialization config parameters - * - * Returned Value: - * 0 if success or others if fail - * - ****************************************************************************/ - -int32_t esp_wifi_init(const wifi_init_config_t *config) -{ - int32_t ret; - -#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST - ret = coex_init(); - if (ret) - { - wlerr("ERROR: Failed to initialize coex error=%d\n", ret); - return ret; - } -#endif - - esp_wifi_internal_set_log_level(WIFI_LOG_DEBUG); - - ret = esp_wifi_init_internal(config); - if (ret) - { - wlerr("Failed to initialize Wi-Fi error=%d\n", ret); - return ret; - } - - ret = esp_supplicant_init(); - if (ret) - { - wlerr("Failed to initialize WPA supplicant error=%d\n", ret); - esp_wifi_deinit_internal(); - return ret; - } - - return 0; -} - -/**************************************************************************** - * Name: esp_wifi_deinit - * - * Description: - * Deinitialize Wi-Fi and free resource - * - * Input Parameters: - * None - * - * Returned Value: - * 0 if success or others if fail - * - ****************************************************************************/ - -int32_t esp_wifi_deinit(void) -{ - int ret; - - ret = esp_supplicant_deinit(); - if (ret) - { - wlerr("Failed to deinitialize supplicant\n"); - return ret; - } - - ret = esp_wifi_deinit_internal(); - if (ret != 0) - { - wlerr("Failed to deinitialize Wi-Fi\n"); - return ret; - } - - return ret; -} - /**************************************************************************** * Name: esp_wifi_free_eb * @@ -5117,6 +5007,7 @@ int esp_wifi_sta_essid(struct iwreq *iwr, bool set) { memset(wifi_cfg.sta.ssid, 0x0, SSID_MAX_LEN); memcpy(wifi_cfg.sta.ssid, pdata, len); + memset(wifi_cfg.sta.sae_h2e_identifier, 0x0, SAE_H2E_IDENTIFIER_LEN); wifi_cfg.sta.sae_pwe_h2e = WPA3_SAE_PWE_BOTH; if (g_sta_connected) @@ -5708,6 +5599,8 @@ int esp_wifi_sta_bitrate(struct iwreq *iwr, bool set) return OK; } +#endif /* ESP32S3_WLAN_HAS_STA */ + /**************************************************************************** * Name: esp_wifi_sta_get_txpower * @@ -5788,7 +5681,7 @@ int esp_wifi_sta_txpower(struct iwreq *iwr, bool set) } /**************************************************************************** - * Name: esp_wifi_sta_get_channel_range + * Name: esp_wifi_sta_channel * * Description: * Get station range of channel parameters. @@ -5901,6 +5794,8 @@ int esp_wifi_sta_country(struct iwreq *iwr, bool set) return OK; } +#ifdef ESP32S3_WLAN_HAS_STA + /**************************************************************************** * Name: esp_wifi_sta_rssi * @@ -6476,6 +6371,13 @@ int esp_wifi_softap_auth(struct iwreq *iwr, bool set) wifi_cfg.ap.authmode = WIFI_AUTH_WPA2_PSK; break; + case IW_AUTH_WPA_VERSION_WPA3: + wifi_cfg.ap.pmf_cfg.required = true; + wifi_cfg.ap.pmf_cfg.capable = false; + wifi_cfg.ap.sae_pwe_h2e = WPA3_SAE_PWE_BOTH; + wifi_cfg.ap.authmode = WIFI_AUTH_WPA3_PSK; + break; + default: wlerr("Invalid wpa version %" PRId32 "\n", iwr->u.param.value); diff --git a/arch/xtensa/src/esp32s3/esp32s3_wifi_utils.c b/arch/xtensa/src/esp32s3/esp32s3_wifi_utils.c index 9792a3803ea40..65d1704ccf228 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_wifi_utils.c +++ b/arch/xtensa/src/esp32s3/esp32s3_wifi_utils.c @@ -35,7 +35,16 @@ #include "esp32s3_wifi_adapter.h" #include "esp32s3_wifi_utils.h" #include "esp32s3_wireless.h" -#include "esp_hal_wifi.h" + +#include "esp_log.h" +#include "esp_mac.h" +#include "esp_private/phy.h" +#include "esp_private/wifi.h" +#include "esp_random.h" +#include "esp_timer.h" +#include "esp_wpa.h" +#include "rom/ets_sys.h" +#include "soc/soc_caps.h" /**************************************************************************** * Pre-processor Definitions @@ -87,7 +96,7 @@ static struct wifi_scan_result g_scan_priv = { .scan_signal = SEM_INITIALIZER(0), }; -static uint8_t g_channel_num = 0; +static uint8_t g_channel_num; static uint8_t g_channel_list[CHANNEL_MAX_NUM]; /**************************************************************************** @@ -201,6 +210,7 @@ int esp_wifi_start_scan(struct iwreq *iwr) if (ret != OK) { wlerr("ERROR: Scan error, ret: %d\n", ret); + ret = ERROR; } else { @@ -221,14 +231,17 @@ int esp_wifi_start_scan(struct iwreq *iwr) } } - if (config != NULL) + if (config) { kmm_free(config); config = NULL; - wlinfo("INFO: start scan\n"); } - g_scan_priv.scan_status = ESP_SCAN_RUN; + if (ret == OK) + { + wlinfo("INFO: start scan\n"); + g_scan_priv.scan_status = ESP_SCAN_RUN; + } return ret; } @@ -257,7 +270,7 @@ int esp_wifi_get_scan_results(struct iwreq *iwr) if (g_scan_priv.scan_status == ESP_SCAN_RUN) { irqstate_t irqstate = enter_critical_section(); - if (scan_block == false) + if (!scan_block) { scan_block = true; leave_critical_section(irqstate); @@ -273,7 +286,8 @@ int esp_wifi_get_scan_results(struct iwreq *iwr) } else if (g_scan_priv.scan_status == ESP_SCAN_DISABLED) { - return -EINVAL; + ret = -EINVAL; + goto exit_failed; } if ((iwr == NULL) || (g_scan_priv.scan_status != ESP_SCAN_DONE)) @@ -291,6 +305,13 @@ int esp_wifi_get_scan_results(struct iwreq *iwr) goto exit_failed; } + if (priv->scan_result_size <= 0) + { + ret = OK; + iwr->u.data.length = 0; + goto exit_free_buffer; + } + if (iwr->u.data.pointer == NULL || iwr->u.data.length < priv->scan_result_size) { @@ -299,14 +320,7 @@ int esp_wifi_get_scan_results(struct iwreq *iwr) ret = -E2BIG; iwr->u.data.pointer = NULL; iwr->u.data.length = priv->scan_result_size; - goto exit_failed; - } - - if (priv->scan_result_size <= 0) - { - ret = OK; - iwr->u.data.length = 0; - goto exit_free_buffer; + return ret; } /* Copy result to user buffer */ @@ -410,7 +424,7 @@ void esp_wifi_scan_event_parse(void) is_target_channel = true; } - if (is_target_channel == true) + if (is_target_channel) { result_size = WIFI_SCAN_RESULT_SIZE - priv->scan_result_size; @@ -544,12 +558,12 @@ void esp_wifi_scan_event_parse(void) /* Continue instead of break to log dropped AP results */ - if (parse_done == false) + if (!parse_done) { wlerr("ERROR: No more space in scan_result buffer\n"); } - if (ap_list_buffer != NULL) + if (ap_list_buffer) { kmm_free(ap_list_buffer); ap_list_buffer = NULL; diff --git a/arch/xtensa/src/esp32s3/esp32s3_wireless.c b/arch/xtensa/src/esp32s3/esp32s3_wireless.c index d507d1503143a..ca051d513af37 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_wireless.c +++ b/arch/xtensa/src/esp32s3/esp32s3_wireless.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include @@ -39,21 +38,24 @@ #include "hardware/esp32s3_syscon.h" #include "hardware/esp32s3_system.h" #include "esp32s3_irq.h" -#include "esp32s3_periph.h" +#include "esp32s3_partition.h" +#include "esp_private/phy.h" +#ifdef CONFIG_ESP32S3_WIFI +# include "esp_private/wifi.h" +# include "esp_wpa.h" +#endif +#include "esp_coexist_internal.h" +#include "periph_ctrl.h" #include "esp_phy_init.h" #include "phy_init_data.h" #include "esp32s3_wireless.h" -#include "esp32s3_partition.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define MAC_ADDR0_REG EFUSE_RD_MAC_SPI_SYS_0_REG -#define MAC_ADDR1_REG EFUSE_RD_MAC_SPI_SYS_1_REG - /* Software Interrupt */ #define SWI_IRQ ESP32S3_IRQ_INT_FROM_CPU2 @@ -81,12 +83,12 @@ struct esp_wireless_priv_s static inline void phy_digital_regs_store(void); static inline void phy_digital_regs_load(void); +static int esp_swi_irq(int irq, void *context, void *arg); /**************************************************************************** * Extern Functions declaration ****************************************************************************/ -extern void coex_pti_v2(void); extern uint8_t esp_crc8(const uint8_t *p, uint32_t len); extern void phy_wakeup_init(void); extern void phy_close_rf(void); @@ -116,10 +118,6 @@ static uint32_t *g_phy_digital_regs_mem = NULL; static bool g_is_phy_calibrated = false; -/* Reference count of power on of wifi and bt power domain */ - -static uint8_t g_wifi_bt_pd_controller; - /* Private data of the wireless common interface */ static struct esp_wireless_priv_s g_esp_wireless_priv; @@ -152,51 +150,51 @@ static const char *g_phy_type[ESP_PHY_INIT_DATA_TYPE_NUMBER] = static phy_country_to_bin_type_t g_country_code_map_type_table[] = { - {"01", ESP_PHY_INIT_DATA_TYPE_DEFAULT}, - {"AT", ESP_PHY_INIT_DATA_TYPE_CE}, - {"AU", ESP_PHY_INIT_DATA_TYPE_ACMA}, - {"BE", ESP_PHY_INIT_DATA_TYPE_CE}, - {"BG", ESP_PHY_INIT_DATA_TYPE_CE}, - {"BR", ESP_PHY_INIT_DATA_TYPE_ANATEL}, - {"CA", ESP_PHY_INIT_DATA_TYPE_ISED}, - {"CH", ESP_PHY_INIT_DATA_TYPE_CE}, - {"CN", ESP_PHY_INIT_DATA_TYPE_SRRC}, - {"CY", ESP_PHY_INIT_DATA_TYPE_CE}, - {"CZ", ESP_PHY_INIT_DATA_TYPE_CE}, - {"DE", ESP_PHY_INIT_DATA_TYPE_CE}, - {"DK", ESP_PHY_INIT_DATA_TYPE_CE}, - {"EE", ESP_PHY_INIT_DATA_TYPE_CE}, - {"ES", ESP_PHY_INIT_DATA_TYPE_CE}, - {"FI", ESP_PHY_INIT_DATA_TYPE_CE}, - {"FR", ESP_PHY_INIT_DATA_TYPE_CE}, - {"GB", ESP_PHY_INIT_DATA_TYPE_CE}, - {"GR", ESP_PHY_INIT_DATA_TYPE_CE}, - {"HK", ESP_PHY_INIT_DATA_TYPE_OFCA}, - {"HR", ESP_PHY_INIT_DATA_TYPE_CE}, - {"HU", ESP_PHY_INIT_DATA_TYPE_CE}, - {"IE", ESP_PHY_INIT_DATA_TYPE_CE}, - {"IN", ESP_PHY_INIT_DATA_TYPE_WPC}, - {"IS", ESP_PHY_INIT_DATA_TYPE_CE}, - {"IT", ESP_PHY_INIT_DATA_TYPE_CE}, - {"JP", ESP_PHY_INIT_DATA_TYPE_MIC}, - {"KR", ESP_PHY_INIT_DATA_TYPE_KCC}, - {"LI", ESP_PHY_INIT_DATA_TYPE_CE}, - {"LT", ESP_PHY_INIT_DATA_TYPE_CE}, - {"LU", ESP_PHY_INIT_DATA_TYPE_CE}, - {"LV", ESP_PHY_INIT_DATA_TYPE_CE}, - {"MT", ESP_PHY_INIT_DATA_TYPE_CE}, - {"MX", ESP_PHY_INIT_DATA_TYPE_IFETEL}, - {"NL", ESP_PHY_INIT_DATA_TYPE_CE}, - {"NO", ESP_PHY_INIT_DATA_TYPE_CE}, - {"NZ", ESP_PHY_INIT_DATA_TYPE_RCM}, - {"PL", ESP_PHY_INIT_DATA_TYPE_CE}, - {"PT", ESP_PHY_INIT_DATA_TYPE_CE}, - {"RO", ESP_PHY_INIT_DATA_TYPE_CE}, - {"SE", ESP_PHY_INIT_DATA_TYPE_CE}, - {"SI", ESP_PHY_INIT_DATA_TYPE_CE}, - {"SK", ESP_PHY_INIT_DATA_TYPE_CE}, - {"TW", ESP_PHY_INIT_DATA_TYPE_NCC}, - {"US", ESP_PHY_INIT_DATA_TYPE_FCC}, + {"01", ESP_PHY_INIT_DATA_TYPE_DEFAULT}, + {"AT", ESP_PHY_INIT_DATA_TYPE_CE}, + {"AU", ESP_PHY_INIT_DATA_TYPE_ACMA}, + {"BE", ESP_PHY_INIT_DATA_TYPE_CE}, + {"BG", ESP_PHY_INIT_DATA_TYPE_CE}, + {"BR", ESP_PHY_INIT_DATA_TYPE_ANATEL}, + {"CA", ESP_PHY_INIT_DATA_TYPE_ISED}, + {"CH", ESP_PHY_INIT_DATA_TYPE_CE}, + {"CN", ESP_PHY_INIT_DATA_TYPE_SRRC}, + {"CY", ESP_PHY_INIT_DATA_TYPE_CE}, + {"CZ", ESP_PHY_INIT_DATA_TYPE_CE}, + {"DE", ESP_PHY_INIT_DATA_TYPE_CE}, + {"DK", ESP_PHY_INIT_DATA_TYPE_CE}, + {"EE", ESP_PHY_INIT_DATA_TYPE_CE}, + {"ES", ESP_PHY_INIT_DATA_TYPE_CE}, + {"FI", ESP_PHY_INIT_DATA_TYPE_CE}, + {"FR", ESP_PHY_INIT_DATA_TYPE_CE}, + {"GB", ESP_PHY_INIT_DATA_TYPE_CE}, + {"GR", ESP_PHY_INIT_DATA_TYPE_CE}, + {"HK", ESP_PHY_INIT_DATA_TYPE_OFCA}, + {"HR", ESP_PHY_INIT_DATA_TYPE_CE}, + {"HU", ESP_PHY_INIT_DATA_TYPE_CE}, + {"IE", ESP_PHY_INIT_DATA_TYPE_CE}, + {"IN", ESP_PHY_INIT_DATA_TYPE_WPC}, + {"IS", ESP_PHY_INIT_DATA_TYPE_CE}, + {"IT", ESP_PHY_INIT_DATA_TYPE_CE}, + {"JP", ESP_PHY_INIT_DATA_TYPE_MIC}, + {"KR", ESP_PHY_INIT_DATA_TYPE_KCC}, + {"LI", ESP_PHY_INIT_DATA_TYPE_CE}, + {"LT", ESP_PHY_INIT_DATA_TYPE_CE}, + {"LU", ESP_PHY_INIT_DATA_TYPE_CE}, + {"LV", ESP_PHY_INIT_DATA_TYPE_CE}, + {"MT", ESP_PHY_INIT_DATA_TYPE_CE}, + {"MX", ESP_PHY_INIT_DATA_TYPE_IFETEL}, + {"NL", ESP_PHY_INIT_DATA_TYPE_CE}, + {"NO", ESP_PHY_INIT_DATA_TYPE_CE}, + {"NZ", ESP_PHY_INIT_DATA_TYPE_RCM}, + {"PL", ESP_PHY_INIT_DATA_TYPE_CE}, + {"PT", ESP_PHY_INIT_DATA_TYPE_CE}, + {"RO", ESP_PHY_INIT_DATA_TYPE_CE}, + {"SE", ESP_PHY_INIT_DATA_TYPE_CE}, + {"SI", ESP_PHY_INIT_DATA_TYPE_CE}, + {"SK", ESP_PHY_INIT_DATA_TYPE_CE}, + {"TW", ESP_PHY_INIT_DATA_TYPE_NCC}, + {"US", ESP_PHY_INIT_DATA_TYPE_FCC}, }; #endif @@ -302,6 +300,41 @@ static int esp_swi_irq(int irq, void *context, void *arg) return OK; } +#ifdef CONFIG_ESP32S3_WIFI + +/**************************************************************************** + * Name: esp_wifi_set_log_level + * + * Description: + * Sets the log level for the ESP32 WiFi module based on preprocessor + * definitions. The log level can be verbose, warning, or error. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp_wifi_set_log_level(void) +{ + wifi_log_level_t wifi_log_level = WIFI_LOG_NONE; + + /* set WiFi log level */ + +#if defined(CONFIG_DEBUG_WIRELESS_INFO) + wifi_log_level = WIFI_LOG_VERBOSE; +#elif defined(CONFIG_DEBUG_WIRELESS_WARN) + wifi_log_level = WIFI_LOG_WARNING; +#elif defined(CONFIG_LOG_MAXIMUM_LEVEL) + wifi_log_level = WIFI_LOG_ERROR; +#endif + + esp_wifi_internal_set_log_level(wifi_log_level); +} +#endif /* CONFIG_ESP32S3_WIFI */ + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -356,44 +389,6 @@ int phy_printf(const char *format, ...) return 0; } -/**************************************************************************** - * Name: esp32s3_phy_enable_clock - * - * Description: - * Enable PHY hardware clock - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_phy_enable_clock(void) -{ - esp32s3_periph_wifi_bt_common_module_enable(); -} - -/**************************************************************************** - * Name: esp32s3_phy_disable_clock - * - * Description: - * Disable PHY hardware clock - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_phy_disable_clock(void) -{ - esp32s3_periph_wifi_bt_common_module_disable(); -} - #ifdef CONFIG_ESP32S3_SUPPORT_MULTIPLE_PHY_INIT_DATA /**************************************************************************** @@ -540,7 +535,9 @@ static int phy_get_multiple_init_data(uint8_t *data, size_t length, return -ENOMEM; } - int ret = esp32s3_partition_read(phy_partion_label, length, control_info, + int ret = esp32s3_partition_read(phy_partion_label, + length, + control_info, sizeof(phy_control_info_data_t)); if (ret != OK) { @@ -592,8 +589,8 @@ static int phy_get_multiple_init_data(uint8_t *data, size_t length, if ((control_info->check_algorithm) == PHY_CRC_ALGORITHM) { ret = phy_crc_check(init_data_multiple, - control_info->multiple_bin_checksum, - sizeof(esp_phy_init_data_t) * control_info->number); + control_info->multiple_bin_checksum, + sizeof(esp_phy_init_data_t) * control_info->number); if (ret != OK) { kmm_free(init_data_multiple); @@ -869,89 +866,6 @@ void esp_phy_release_init_data(const esp_phy_init_data_t *init_data) } #endif -/**************************************************************************** - * Name: esp_read_mac - * - * Description: - * Read MAC address from efuse - * - * Input Parameters: - * mac - MAC address buffer pointer - * type - MAC address type - * - * Returned Value: - * 0 if success or -1 if fail - * - ****************************************************************************/ - -int32_t esp_read_mac(uint8_t *mac, esp_mac_type_t type) -{ - uint32_t regval[2]; - uint8_t tmp; - uint8_t *data = (uint8_t *)regval; - int i; - - if (mac == NULL) - { - wlerr("mac address param is NULL"); - return -1; - } - - if (type > ESP_MAC_BT) - { - wlerr("Input type is error=%d\n", type); - return -1; - } - - regval[0] = getreg32(MAC_ADDR0_REG); - regval[1] = getreg32(MAC_ADDR1_REG); - - for (i = 0; i < MAC_LEN; i++) - { - mac[i] = data[5 - i]; - } - - if (type == ESP_MAC_WIFI_SOFTAP) - { - tmp = mac[0]; - for (i = 0; i < 64; i++) - { - mac[0] = tmp | 0x02; - mac[0] ^= i << 2; - - if (mac[0] != tmp) - { - break; - } - } - - if (i >= 64) - { - wlerr("Failed to generate SoftAP MAC\n"); - return -1; - } - } - - if (type == ESP_MAC_BT) - { - tmp = mac[0]; - for (i = 0; i < 64; i++) - { - mac[0] = tmp | 0x02; - mac[0] ^= i << 2; - - if (mac[0] != tmp) - { - break; - } - } - - mac[5] += 1; - } - - return 0; -} - /**************************************************************************** * Name: esp32s3_phy_update_country_info * @@ -1000,182 +914,6 @@ int esp32s3_phy_update_country_info(const char *country) return OK; } -/**************************************************************************** - * Name: esp32s3_phy_disable - * - * Description: - * Deinitialize PHY hardware - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_phy_disable(void) -{ - irqstate_t flags; - flags = enter_critical_section(); - - g_phy_access_ref--; - - if (g_phy_access_ref == 0) - { - phy_digital_regs_store(); - - /* Disable PHY and RF. */ - - phy_close_rf(); - - /* Disable PHY temperature sensor */ - - phy_xpd_tsens(); - - /* Disable Wi-Fi/BT common peripheral clock. - * Do not disable clock for hardware RNG. - */ - - esp32s3_phy_disable_clock(); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: esp32s3_phy_enable - * - * Description: - * Initialize PHY hardware - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_phy_enable(void) -{ - static bool debug = false; - irqstate_t flags; - esp_phy_calibration_data_t *cal_data; - - if (debug == false) - { - char *phy_version = get_phy_version_str(); - wlinfo("phy_version %s\n", phy_version); - debug = true; - } - - flags = spin_lock_irqsave(NULL); - - if (g_phy_access_ref == 0) - { - esp32s3_phy_enable_clock(); - - if (g_is_phy_calibrated == false) - { - cal_data = kmm_zalloc(sizeof(esp_phy_calibration_data_t)); - if (cal_data == NULL) - { - wlerr("ERROR: Failed to allocate PHY" - "calibration data buffer."); - abort(); - } - -#if CONFIG_ESP_PHY_ENABLE_USB - phy_bbpll_en_usb(true); -#endif - wlinfo("calibrating"); - const esp_phy_init_data_t *init_data = esp_phy_get_init_data(); - if (init_data == NULL) - { - wlerr("ERROR: Failed to obtain PHY init data"); - abort(); - } - - register_chipv7_phy(init_data, cal_data, PHY_RF_CAL_FULL); - esp_phy_release_init_data(init_data); - g_is_phy_calibrated = true; - kmm_free(cal_data); - } - else - { - phy_wakeup_init(); - phy_digital_regs_load(); - } - } - - g_phy_access_ref++; - - spin_unlock_irqrestore(NULL, flags); -} - -/**************************************************************************** - * Name: esp_wifi_bt_power_domain_on - * - * Description: - * Initialize Bluetooth and Wi-Fi power domain - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp_wifi_bt_power_domain_on(void) -{ - irqstate_t flags; - - flags = enter_critical_section(); - - if (g_wifi_bt_pd_controller++ == 0) - { - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD, 0); - - modifyreg32(SYSCON_WIFI_RST_EN_REG, 0, MODEM_RESET_FIELD_WHEN_PU); - modifyreg32(SYSCON_WIFI_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU, 0); - - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO, 0); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: esp_wifi_bt_power_domain_off - * - * Description: - * Deinitialize Bluetooth and Wi-Fi power domain - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp_wifi_bt_power_domain_off(void) -{ - irqstate_t flags; - - flags = enter_critical_section(); - - if (--g_wifi_bt_pd_controller == 0) - { - modifyreg32(RTC_CNTL_DIG_ISO_REG, 0, RTC_CNTL_WIFI_FORCE_ISO); - modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_WIFI_FORCE_PD); - } - - leave_critical_section(flags); -} - /**************************************************************************** * Name: esp_timer_create * @@ -1523,3 +1261,92 @@ int esp_wireless_deinit(void) return OK; } + +#ifdef CONFIG_ESP32S3_WIFI + +/**************************************************************************** + * Name: esp_wifi_init + * + * Description: + * Initialize Wi-Fi + * + * Input Parameters: + * config - Initialization config parameters + * + * Returned Value: + * 0 if success or others if fail + * + ****************************************************************************/ + +int32_t esp_wifi_init(const wifi_init_config_t *config) +{ + int32_t ret; + + esp_wifi_power_domain_on(); + +#ifdef CONFIG_ESP32S3_WIFI_BT_COEXIST + ret = coex_init(); + if (ret) + { + wlerr("ERROR: Failed to initialize coex error=%d\n", ret); + return ret; + } +#endif /* CONFIG_ESP32S3_WIFI_BT_COEXIST */ + + esp_wifi_set_log_level(); + + ret = esp_wifi_init_internal(config); + if (ret) + { + wlerr("Failed to initialize Wi-Fi error=%d\n", ret); + return ret; + } + + esp_phy_modem_init(); + + ret = esp_supplicant_init(); + if (ret) + { + wlerr("Failed to initialize WPA supplicant error=%d\n", ret); + esp_wifi_deinit_internal(); + return ret; + } + + return 0; +} + +/**************************************************************************** + * Name: esp_wifi_deinit + * + * Description: + * Deinitialize Wi-Fi and free resource + * + * Input Parameters: + * None + * + * Returned Value: + * 0 if success or others if fail + * + ****************************************************************************/ + +int32_t esp_wifi_deinit(void) +{ + int ret; + + ret = esp_supplicant_deinit(); + if (ret) + { + wlerr("Failed to deinitialize supplicant\n"); + return ret; + } + + ret = esp_wifi_deinit_internal(); + if (ret != 0) + { + wlerr("Failed to deinitialize Wi-Fi\n"); + return ret; + } + + return ret; +} +#endif /* CONFIG_ESP32S3_WIFI */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_wireless.h b/arch/xtensa/src/esp32s3/esp32s3_wireless.h index a1f8c4a2431e7..d4dddbcf8538c 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_wireless.h +++ b/arch/xtensa/src/esp32s3/esp32s3_wireless.h @@ -31,10 +31,17 @@ #include #include -#include "xtensa_attr.h" +#include "esp_attr.h" #include "esp32s3_rt_timer.h" -#include "esp_hal_wifi.h" +#include "esp_log.h" +#include "esp_mac.h" +#include "esp_private/phy.h" +#include "esp_private/wifi.h" +#include "esp_random.h" +#include "esp_timer.h" +#include "rom/ets_sys.h" +#include "soc/soc_caps.h" /**************************************************************************** * Pre-processor Definitions @@ -76,103 +83,6 @@ struct esp_queuecache_s * Public Function Prototypes ****************************************************************************/ -/**************************************************************************** - * Name: esp_read_mac - * - * Description: - * Read MAC address from efuse - * - * Input Parameters: - * mac - MAC address buffer pointer - * type - MAC address type - * - * Returned Value: - * 0 if success or -1 if fail - * - ****************************************************************************/ - -int32_t esp_read_mac(uint8_t *mac, esp_mac_type_t type); - -/**************************************************************************** - * Name: esp32s3_phy_enable - * - * Description: - * Initialize PHY hardware - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_phy_enable(void); - -/**************************************************************************** - * Name: esp32s3_phy_disable - * - * Description: - * Deinitialize PHY hardware - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_phy_disable(void); - -/**************************************************************************** - * Name: esp32s3_phy_enable_clock - * - * Description: - * Enable PHY clock - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_phy_enable_clock(void); - -/**************************************************************************** - * Name: esp32s3_phy_disable_clock - * - * Description: - * Disable PHY clock - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_phy_disable_clock(void); - -/**************************************************************************** - * Name: esp32s3_phy_update_country_info - * - * Description: - * Update PHY init data according to country code - * - * Input Parameters: - * country - PHY init data type - * - * Returned Value: - * OK on success; a negated errno on failure - * - ****************************************************************************/ - -int esp32s3_phy_update_country_info(const char *country); - /**************************************************************************** * Functions needed by libphy.a ****************************************************************************/ @@ -209,22 +119,6 @@ uint32_t IRAM_ATTR esp_dport_access_reg_read(uint32_t reg); int phy_printf(const char *format, ...) printf_like(1, 2); -/**************************************************************************** - * Name: esp_wifi_bt_power_domain_on - * - * Description: - * Initialize Bluetooth and Wi-Fi power domain - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp_wifi_bt_power_domain_on(void); - /**************************************************************************** * Name: esp_timer_create * @@ -309,6 +203,22 @@ int32_t esp_timer_stop(esp_timer_handle_t timer); int32_t esp_timer_delete(esp_timer_handle_t timer); +/**************************************************************************** + * Name: esp32s3_phy_update_country_info + * + * Description: + * Update PHY init data according to country code + * + * Input Parameters: + * country - PHY init data type + * + * Returned Value: + * OK on success; a negated errno on failure + * + ****************************************************************************/ + +int esp32s3_phy_update_country_info(const char *country); + /**************************************************************************** * Name: esp_init_semcache * diff --git a/arch/xtensa/src/esp32s3/esp32s3_wlan.c b/arch/xtensa/src/esp32s3/esp32s3_wlan.c index 5ea27357387bd..92c37d74c307c 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_wlan.c +++ b/arch/xtensa/src/esp32s3/esp32s3_wlan.c @@ -150,7 +150,7 @@ struct wlan_priv_s /* Reference count of register Wi-Fi handler */ -static uint8_t g_callback_register_ref = 0; +static uint8_t g_callback_register_ref; static struct wlan_priv_s g_wlan_priv[ESP32S3_WLAN_DEVS]; @@ -1373,7 +1373,7 @@ int esp32s3_wlan_sta_set_linkstatus(bool linkstatus) { struct wlan_priv_s *priv = &g_wlan_priv[ESP32S3_WLAN_STA_DEVNO]; - if (linkstatus == true) + if (linkstatus) { netdev_carrier_on(&priv->dev); } diff --git a/arch/xtensa/src/esp32s3/hal.mk b/arch/xtensa/src/esp32s3/hal.mk index 7d8158e711d78..73f79c0b6a02b 100644 --- a/arch/xtensa/src/esp32s3/hal.mk +++ b/arch/xtensa/src/esp32s3/hal.mk @@ -20,18 +20,23 @@ # Include header paths -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)private_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_event$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)esp_private INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES) INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)private_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES) INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include$(DELIM)$(CHIP_SERIES) @@ -40,6 +45,7 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include$(DELIM)private INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)public_compat INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)platform_port$(DELIM)include @@ -49,8 +55,11 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)private_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)include # Linker scripts @@ -60,17 +69,29 @@ ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM) # Source files +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_api.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_utility.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_fields.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_table.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_utility.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)cpu.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_clk.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)hw_random.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mac_addr.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)periph_ctrl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_init.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk_init.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_sleep.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_time.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)mspi_timing_config.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_wdt.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c @@ -84,6 +105,9 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal_iram.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mpu_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mmu_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log_noos.c @@ -92,4 +116,38 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)bootloader_banner_wrap.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_console.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_console_loader.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_${CHIP_SERIES}.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_init.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common_loader.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash_config_${CHIP_SERIES}.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_init.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_loader.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_efuse.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_mem.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random_${CHIP_SERIES}.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)esp_image_format.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_sha.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)flash_encrypt.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_systimer.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_cache_esp32s2_esp32s3.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_fields.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)efuse_controller$(DELIM)keys$(DELIM)with_key_purposes$(DELIM)esp_efuse_api_key.c + + CHIP_ASRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_cache_writeback_esp32s3.S + + LDFLAGS += --wrap=bootloader_print_banner +endif + CFLAGS += ${DEFINE_PREFIX}ESP_PLATFORM=1 diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_aes.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_aes.h new file mode 100644 index 0000000000000..a017ebd886371 --- /dev/null +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_aes.h @@ -0,0 +1,780 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/hardware/esp32s3_aes.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_AES_H +#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_AES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s3_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* AES_KEY_0_REG register + * AES key register 0 + */ + +#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0) + +/* AES_KEY_0 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_0 0xFFFFFFFF +#define AES_KEY_0_M (AES_KEY_0_V << AES_KEY_0_S) +#define AES_KEY_0_V 0xFFFFFFFF +#define AES_KEY_0_S 0 + +/* AES_KEY_1_REG register + * AES key register 1 + */ + +#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4) + +/* AES_KEY_1 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_1 0xFFFFFFFF +#define AES_KEY_1_M (AES_KEY_1_V << AES_KEY_1_S) +#define AES_KEY_1_V 0xFFFFFFFF +#define AES_KEY_1_S 0 + +/* AES_KEY_2_REG register + * AES key register 2 + */ + +#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8) + +/* AES_KEY_2 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_2 0xFFFFFFFF +#define AES_KEY_2_M (AES_KEY_2_V << AES_KEY_2_S) +#define AES_KEY_2_V 0xFFFFFFFF +#define AES_KEY_2_S 0 + +/* AES_KEY_3_REG register + * AES key register 3 + */ + +#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc) + +/* AES_KEY_3 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_3 0xFFFFFFFF +#define AES_KEY_3_M (AES_KEY_3_V << AES_KEY_3_S) +#define AES_KEY_3_V 0xFFFFFFFF +#define AES_KEY_3_S 0 + +/* AES_KEY_4_REG register + * AES key register 4 + */ + +#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10) + +/* AES_KEY_4 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_4 0xFFFFFFFF +#define AES_KEY_4_M (AES_KEY_4_V << AES_KEY_4_S) +#define AES_KEY_4_V 0xFFFFFFFF +#define AES_KEY_4_S 0 + +/* AES_KEY_5_REG register + * AES key register 5 + */ + +#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14) + +/* AES_KEY_5 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_5 0xFFFFFFFF +#define AES_KEY_5_M (AES_KEY_5_V << AES_KEY_5_S) +#define AES_KEY_5_V 0xFFFFFFFF +#define AES_KEY_5_S 0 + +/* AES_KEY_6_REG register + * AES key register 6 + */ + +#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18) + +/* AES_KEY_6 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_6 0xFFFFFFFF +#define AES_KEY_6_M (AES_KEY_6_V << AES_KEY_6_S) +#define AES_KEY_6_V 0xFFFFFFFF +#define AES_KEY_6_S 0 + +/* AES_KEY_7_REG register + * AES key register 7 + */ + +#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c) + +/* AES_KEY_7 : R/W; bitpos: [31:0]; default: 0; + * Stores AES keys. + */ + +#define AES_KEY_7 0xFFFFFFFF +#define AES_KEY_7_M (AES_KEY_7_V << AES_KEY_7_S) +#define AES_KEY_7_V 0xFFFFFFFF +#define AES_KEY_7_S 0 + +/* AES_TEXT_IN_0_REG register + * Source data register 0 + */ + +#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20) + +/* AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_0 0xFFFFFFFF +#define AES_TEXT_IN_0_M (AES_TEXT_IN_0_V << AES_TEXT_IN_0_S) +#define AES_TEXT_IN_0_V 0xFFFFFFFF +#define AES_TEXT_IN_0_S 0 + +/* AES_TEXT_IN_1_REG register + * Source data register 1 + */ + +#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24) + +/* AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_1 0xFFFFFFFF +#define AES_TEXT_IN_1_M (AES_TEXT_IN_1_V << AES_TEXT_IN_1_S) +#define AES_TEXT_IN_1_V 0xFFFFFFFF +#define AES_TEXT_IN_1_S 0 + +/* AES_TEXT_IN_2_REG register + * Source data register 2 + */ + +#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28) + +/* AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_2 0xFFFFFFFF +#define AES_TEXT_IN_2_M (AES_TEXT_IN_2_V << AES_TEXT_IN_2_S) +#define AES_TEXT_IN_2_V 0xFFFFFFFF +#define AES_TEXT_IN_2_S 0 + +/* AES_TEXT_IN_3_REG register + * Source data register 3 + */ + +#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c) + +/* AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0; + * Stores the source data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_IN_3 0xFFFFFFFF +#define AES_TEXT_IN_3_M (AES_TEXT_IN_3_V << AES_TEXT_IN_3_S) +#define AES_TEXT_IN_3_V 0xFFFFFFFF +#define AES_TEXT_IN_3_S 0 + +/* AES_TEXT_OUT_0_REG register + * Result data register 0 + */ + +#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30) + +/* AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_0 0xFFFFFFFF +#define AES_TEXT_OUT_0_M (AES_TEXT_OUT_0_V << AES_TEXT_OUT_0_S) +#define AES_TEXT_OUT_0_V 0xFFFFFFFF +#define AES_TEXT_OUT_0_S 0 + +/* AES_TEXT_OUT_1_REG register + * Result data register 1 + */ + +#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34) + +/* AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_1 0xFFFFFFFF +#define AES_TEXT_OUT_1_M (AES_TEXT_OUT_1_V << AES_TEXT_OUT_1_S) +#define AES_TEXT_OUT_1_V 0xFFFFFFFF +#define AES_TEXT_OUT_1_S 0 + +/* AES_TEXT_OUT_2_REG register + * Result data register 2 + */ + +#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38) + +/* AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_2 0xFFFFFFFF +#define AES_TEXT_OUT_2_M (AES_TEXT_OUT_2_V << AES_TEXT_OUT_2_S) +#define AES_TEXT_OUT_2_V 0xFFFFFFFF +#define AES_TEXT_OUT_2_S 0 + +/* AES_TEXT_OUT_3_REG register + * Result data register 3 + */ + +#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c) + +/* AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0; + * Stores the result data when the AES Accelerator operates in the Typical + * AES working mode. + */ + +#define AES_TEXT_OUT_3 0xFFFFFFFF +#define AES_TEXT_OUT_3_M (AES_TEXT_OUT_3_V << AES_TEXT_OUT_3_S) +#define AES_TEXT_OUT_3_V 0xFFFFFFFF +#define AES_TEXT_OUT_3_S 0 + +/* AES_MODE_REG register + * AES working mode configuration register + */ + +#define AES_MODE_REG (DR_REG_AES_BASE + 0x40) + +/* AES_MODE : R/W; bitpos: [2:0]; default: 0; + * Defines the operation type of the AES Accelerator operating under the + * Typical AES working mode. + * & + * 0x0(AES_EN_128): AES-EN-128 # + * 0x1(AES_EN_192): AES-EN-192 # + * 0x2(AES_EN_256): AES-EN-256 # + * 0x4(AES_DE_128): AES-DE-128 # + * 0x5(AES_DE_192): AES-DE-192 # + * 0x6(AES_DE_256): AES-DE-256 + * & + */ + +#define AES_MODE 0x00000007 +#define AES_MODE_M (AES_MODE_V << AES_MODE_S) +#define AES_MODE_V 0x00000007 +#define AES_MODE_S 0 + +/* AES_ENDIAN_REG register + * Endian configuration register + */ + +#define AES_ENDIAN_REG (DR_REG_AES_BASE + 0x44) + +/* AES_ENDIAN : R/W; bitpos: [5:0]; default: 0; + * Defines the endianness of input and output texts. + * & + * [1:0] key endian # + * [3:2] text_in endian or in_stream endian # + * [5:4] text_out endian or out_stream endian # + * & + */ + +#define AES_ENDIAN 0x0000003F +#define AES_ENDIAN_M (AES_ENDIAN_V << AES_ENDIAN_S) +#define AES_ENDIAN_V 0x0000003F +#define AES_ENDIAN_S 0 + +/* AES_TRIGGER_REG register + * Operation start controlling register + */ + +#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48) + +/* AES_TRIGGER : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to start AES operation. + */ + +#define AES_TRIGGER (BIT(0)) +#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S) +#define AES_TRIGGER_V 0x00000001 +#define AES_TRIGGER_S 0 + +/* AES_STATE_REG register + * Operation status register + */ + +#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c) + +/* AES_STATE : RO; bitpos: [1:0]; default: 0; + * Stores the working status of the AES Accelerator. For details, see Table + * 3 for Typical AES working mode and Table 9 for DMA AES working mode. + * For typical AES; 0 = idle; 1 = busy. + * For DMA-AES; 0 = idle; 1 = busy; 2 = calculation_done. + */ + +#define AES_STATE 0x00000003 +#define AES_STATE_M (AES_STATE_V << AES_STATE_S) +#define AES_STATE_V 0x00000003 +#define AES_STATE_S 0 + +/* AES_IV_0_REG register + * initialization vector + */ + +#define AES_IV_0_REG (DR_REG_AES_BASE + 0x50) + +/* AES_IV_0 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 0th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_0 0xFFFFFFFF +#define AES_IV_0_M (AES_IV_0_V << AES_IV_0_S) +#define AES_IV_0_V 0xFFFFFFFF +#define AES_IV_0_S 0 + +/* AES_IV_1_REG register + * initialization vector + */ + +#define AES_IV_1_REG (DR_REG_AES_BASE + 0x54) + +/* AES_IV_1 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 1th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_1 0xFFFFFFFF +#define AES_IV_1_M (AES_IV_1_V << AES_IV_1_S) +#define AES_IV_1_V 0xFFFFFFFF +#define AES_IV_1_S 0 + +/* AES_IV_2_REG register + * initialization vector + */ + +#define AES_IV_2_REG (DR_REG_AES_BASE + 0x58) + +/* AES_IV_2 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 2th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_2 0xFFFFFFFF +#define AES_IV_2_M (AES_IV_2_V << AES_IV_2_S) +#define AES_IV_2_V 0xFFFFFFFF +#define AES_IV_2_S 0 + +/* AES_IV_3_REG register + * initialization vector + */ + +#define AES_IV_3_REG (DR_REG_AES_BASE + 0x5c) + +/* AES_IV_3 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 3th 32-bit piece of 128-bit initialization vector + */ + +#define AES_IV_3 0xFFFFFFFF +#define AES_IV_3_M (AES_IV_3_V << AES_IV_3_S) +#define AES_IV_3_V 0xFFFFFFFF +#define AES_IV_3_S 0 + +/* AES_H_0_REG register + * GCM hash subkey + */ + +#define AES_H_0_REG (DR_REG_AES_BASE + 0x60) + +/* AES_H_0 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_0 0xFFFFFFFF +#define AES_H_0_M (AES_H_0_V << AES_H_0_S) +#define AES_H_0_V 0xFFFFFFFF +#define AES_H_0_S 0 + +/* AES_H_1_REG register + * GCM hash subkey + */ + +#define AES_H_1_REG (DR_REG_AES_BASE + 0x64) + +/* AES_H_1 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_1 0xFFFFFFFF +#define AES_H_1_M (AES_H_1_V << AES_H_1_S) +#define AES_H_1_V 0xFFFFFFFF +#define AES_H_1_S 0 + +/* AES_H_2_REG register + * GCM hash subkey + */ + +#define AES_H_2_REG (DR_REG_AES_BASE + 0x68) + +/* AES_H_2 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_2 0xFFFFFFFF +#define AES_H_2_M (AES_H_2_V << AES_H_2_S) +#define AES_H_2_V 0xFFFFFFFF +#define AES_H_2_S 0 + +/* AES_H_3_REG register + * GCM hash subkey + */ + +#define AES_H_3_REG (DR_REG_AES_BASE + 0x6c) + +/* AES_H_3 : RO; bitpos: [31:0]; default: 0; + * GCM hash subkey + */ + +#define AES_H_3 0xFFFFFFFF +#define AES_H_3_M (AES_H_3_V << AES_H_3_S) +#define AES_H_3_V 0xFFFFFFFF +#define AES_H_3_S 0 + +/* AES_J0_0_REG register + * J0 + */ + +#define AES_J0_0_REG (DR_REG_AES_BASE + 0x70) + +/* AES_J0_0 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 0th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_0 0xFFFFFFFF +#define AES_J0_0_M (AES_J0_0_V << AES_J0_0_S) +#define AES_J0_0_V 0xFFFFFFFF +#define AES_J0_0_S 0 + +/* AES_J0_1_REG register + * J0 + */ + +#define AES_J0_1_REG (DR_REG_AES_BASE + 0x74) + +/* AES_J0_1 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 1th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_1 0xFFFFFFFF +#define AES_J0_1_M (AES_J0_1_V << AES_J0_1_S) +#define AES_J0_1_V 0xFFFFFFFF +#define AES_J0_1_S 0 + +/* AES_J0_2_REG register + * J0 + */ + +#define AES_J0_2_REG (DR_REG_AES_BASE + 0x78) + +/* AES_J0_2 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 2th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_2 0xFFFFFFFF +#define AES_J0_2_M (AES_J0_2_V << AES_J0_2_S) +#define AES_J0_2_V 0xFFFFFFFF +#define AES_J0_2_S 0 + +/* AES_J0_3_REG register + * J0 + */ + +#define AES_J0_3_REG (DR_REG_AES_BASE + 0x7c) + +/* AES_J0_3 : R/W; bitpos: [31:0]; default: 0; + * This register stores the 3th 32-bit piece of 128-bit J0 + */ + +#define AES_J0_3 0xFFFFFFFF +#define AES_J0_3_M (AES_J0_3_V << AES_J0_3_S) +#define AES_J0_3_V 0xFFFFFFFF +#define AES_J0_3_S 0 + +/* AES_T0_0_REG register + * T0 + */ + +#define AES_T0_0_REG (DR_REG_AES_BASE + 0x80) + +/* AES_T0_0 : RO; bitpos: [31:0]; default: 0; + * This register stores the 0th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_0 0xFFFFFFFF +#define AES_T0_0_M (AES_T0_0_V << AES_T0_0_S) +#define AES_T0_0_V 0xFFFFFFFF +#define AES_T0_0_S 0 + +/* AES_T0_1_REG register + * T0 + */ + +#define AES_T0_1_REG (DR_REG_AES_BASE + 0x84) + +/* AES_T0_1 : RO; bitpos: [31:0]; default: 0; + * This register stores the 1th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_1 0xFFFFFFFF +#define AES_T0_1_M (AES_T0_1_V << AES_T0_1_S) +#define AES_T0_1_V 0xFFFFFFFF +#define AES_T0_1_S 0 + +/* AES_T0_2_REG register + * T0 + */ + +#define AES_T0_2_REG (DR_REG_AES_BASE + 0x88) + +/* AES_T0_2 : RO; bitpos: [31:0]; default: 0; + * This register stores the 2th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_2 0xFFFFFFFF +#define AES_T0_2_M (AES_T0_2_V << AES_T0_2_S) +#define AES_T0_2_V 0xFFFFFFFF +#define AES_T0_2_S 0 + +/* AES_T0_3_REG register + * T0 + */ + +#define AES_T0_3_REG (DR_REG_AES_BASE + 0x8c) + +/* AES_T0_3 : RO; bitpos: [31:0]; default: 0; + * This register stores the 3th 32-bit piece of 128-bit T0 + */ + +#define AES_T0_3 0xFFFFFFFF +#define AES_T0_3_M (AES_T0_3_V << AES_T0_3_S) +#define AES_T0_3_V 0xFFFFFFFF +#define AES_T0_3_S 0 + +/* AES_DMA_ENABLE_REG register + * DMA enable register + */ + +#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90) + +/* AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0; + * Defines the working mode of the AES Accelerator. For details, see Table 1. + * 1'h0: typical AES operation + * 1'h1: DMA-AES operation + */ + +#define AES_DMA_ENABLE (BIT(0)) +#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S) +#define AES_DMA_ENABLE_V 0x00000001 +#define AES_DMA_ENABLE_S 0 + +/* AES_BLOCK_MODE_REG register + * Block operation type register + */ + +#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94) + +/* AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0; + * Defines the operation type of the AES Accelerator operating under the + * DMA-AES working mode. For details, see Table 8. + * & + * 3'h0(BLOCK_MODE_ECB): ECB # + * 3'h1(BLOCK_MODE_CBC): CBC # + * 3'h2(BLOCK_MODE_OFB): OFB # + * 3'h3(BLOCK_MODE_CTR): CTR # + * 3'h4(BLOCK_MODE_CFB8): CFB-8 # + * 3'h5(BLOCK_MODE_CFB128): CFB-128 # + * 3'h6(BLOCK_MODE_GCM): GCM + * & + */ + +#define AES_BLOCK_MODE 0x00000007 +#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S) +#define AES_BLOCK_MODE_V 0x00000007 +#define AES_BLOCK_MODE_S 0 + +/* AES_BLOCK_NUM_REG register + * Block number configuration register + */ + +#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98) + +/* AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; + * Stores the Block Number of plaintext or cipertext when the AES + * Accelerator operates under the DMA-AES working mode. For details, see + * Section 1.5.4. + */ + +#define AES_BLOCK_NUM 0xFFFFFFFF +#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S) +#define AES_BLOCK_NUM_V 0xFFFFFFFF +#define AES_BLOCK_NUM_S 0 + +/* AES_INC_SEL_REG register + * Standard incrementing function register + */ + +#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c) + +/* AES_INC_SEL : R/W; bitpos: [0]; default: 0; + * Defines the Standard Incrementing Function for CTR block operation. Set + * this bit to 0 or 1 to choose INC 32 or INC 128 . + */ + +#define AES_INC_SEL (BIT(0)) +#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S) +#define AES_INC_SEL_V 0x00000001 +#define AES_INC_SEL_S 0 + +/* AES_AAD_BLOCK_NUM_REG register + * AAD block number configuration register + */ + +#define AES_AAD_BLOCK_NUM_REG (DR_REG_AES_BASE + 0xa0) + +/* AES_AAD_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0; + * Stores the ADD Block Number for the GCM operation. + */ + +#define AES_AAD_BLOCK_NUM 0xFFFFFFFF +#define AES_AAD_BLOCK_NUM_M (AES_AAD_BLOCK_NUM_V << AES_AAD_BLOCK_NUM_S) +#define AES_AAD_BLOCK_NUM_V 0xFFFFFFFF +#define AES_AAD_BLOCK_NUM_S 0 + +/* AES_REMAINDER_BIT_NUM_REG register + * Remainder bit number of plaintext/ciphertext + */ + +#define AES_REMAINDER_BIT_NUM_REG (DR_REG_AES_BASE + 0xa4) + +/* AES_REMAINDER_BIT_NUM : R/W; bitpos: [6:0]; default: 0; + * Stores the Remainder Bit Number for the GCM operation. + */ + +#define AES_REMAINDER_BIT_NUM 0x0000007F +#define AES_REMAINDER_BIT_NUM_M (AES_REMAINDER_BIT_NUM_V << AES_REMAINDER_BIT_NUM_S) +#define AES_REMAINDER_BIT_NUM_V 0x0000007F +#define AES_REMAINDER_BIT_NUM_S 0 + +/* AES_CONTINUE_REG register + * Operation continue controlling register + */ + +#define AES_CONTINUE_REG (DR_REG_AES_BASE + 0xa8) + +/* AES_CONTINUE : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to continue AES operation. + */ + +#define AES_CONTINUE (BIT(0)) +#define AES_CONTINUE_M (AES_CONTINUE_V << AES_CONTINUE_S) +#define AES_CONTINUE_V 0x00000001 +#define AES_CONTINUE_S 0 + +/* AES_INT_CLR_REG register + * DMA-AES interrupt clear register + */ + +#define AES_INT_CLR_REG (DR_REG_AES_BASE + 0xac) + +/* AES_INT_CLR : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to clear AES interrupt. + */ + +#define AES_INT_CLR (BIT(0)) +#define AES_INT_CLR_M (AES_INT_CLR_V << AES_INT_CLR_S) +#define AES_INT_CLR_V 0x00000001 +#define AES_INT_CLR_S 0 + +/* AES_INT_ENA_REG register + * DMA-AES interrupt enable register + */ + +#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0) + +/* AES_INT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 to enable AES interrupt and 0 to disable interrupt. + */ + +#define AES_INT_ENA (BIT(0)) +#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S) +#define AES_INT_ENA_V 0x00000001 +#define AES_INT_ENA_S 0 + +/* AES_DATE_REG register + * Version control register + */ + +#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4) + +/* AES_DATE : R/W; bitpos: [29:0]; default: 538510612; + * Version control register + */ + +#define AES_DATE 0x3FFFFFFF +#define AES_DATE_M (AES_DATE_V << AES_DATE_S) +#define AES_DATE_V 0x3FFFFFFF +#define AES_DATE_S 0 + +/* AES_DMA_EXIT_REG register + * Operation exit controlling register + */ + +#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8) + +/* AES_DMA_EXIT : WO; bitpos: [0]; default: 0; + * Set this bit to 1 to exit AES operation. This register is only effective + * for DMA-AES operation. + */ + +#define AES_DMA_EXIT (BIT(0)) +#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S) +#define AES_DMA_EXIT_V 0x00000001 +#define AES_DMA_EXIT_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_AES_H */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_cache_memory.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_cache_memory.h index 7e41044b5f4e1..2d3cc64cfee3e 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_cache_memory.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_cache_memory.h @@ -25,73 +25,12 @@ #include #include "esp32s3_soc.h" +#include "soc/ext_mem_defs.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* IRAM0 is connected with Cache IBUS0 */ - -#define IRAM0_ADDRESS_LOW 0x40000000 -#define IRAM0_ADDRESS_HIGH 0x44000000 -#define IRAM0_CACHE_ADDRESS_LOW 0x42000000 -#define IRAM0_CACHE_ADDRESS_HIGH 0x44000000 - -/* DRAM0 is connected with Cache DBUS0 */ - -#define DRAM0_ADDRESS_LOW 0x3c000000 -#define DRAM0_ADDRESS_HIGH 0x40000000 -#define DRAM0_CACHE_ADDRESS_LOW 0x3c000000 -#define DRAM0_CACHE_ADDRESS_HIGH 0x3e000000 -#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH -#define ESP_CACHE_TEMP_ADDR 0x3c800000 - -#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - \ - bus_name##_ADDRESS_LOW) -#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW \ - && (vaddr) < \ - bus_name##_ADDRESS_HIGH) - -#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) -#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) -#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) -#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) - -#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE) -#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE) - -#define CACHE_IBUS 0 -#define CACHE_IBUS_MMU_START 0 -#define CACHE_IBUS_MMU_END 0x800 - -#define CACHE_DBUS 1 -#define CACHE_DBUS_MMU_START 0 -#define CACHE_DBUS_MMU_END 0x800 - -#define CACHE_IROM_MMU_START 0 -#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() -#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) - -#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END -#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() -#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) - -#define CACHE_DROM_MMU_MAX_END 0x400 - -#define ICACHE_MMU_SIZE 0x800 -#define DCACHE_MMU_SIZE 0x800 - -#define MMU_BUS_START(i) 0 -#define MMU_BUS_SIZE(i) 0x800 - -#define MMU_INVALID BIT(14) -#define MMU_TYPE BIT(15) -#define MMU_ACCESS_FLASH 0 -#define MMU_ACCESS_SPIRAM BIT(15) - -#define CACHE_MAX_SYNC_NUM 0x400000 -#define CACHE_MAX_LOCK_NUM 0x8000 - #define FLASH_MMU_TABLE ((volatile uint32_t *)DR_REG_MMU_TABLE) #define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE / sizeof(uint32_t)) @@ -104,15 +43,4 @@ #define BUS_ADDR_SIZE 0x200000 #define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1) -#define CACHE_ICACHE_LOW_SHIFT 0 -#define CACHE_ICACHE_HIGH_SHIFT 2 -#define CACHE_DCACHE_LOW_SHIFT 4 -#define CACHE_DCACHE_HIGH_SHIFT 6 - -#define CACHE_MEMORY_IBANK0_ADDR 0x40370000 -#define CACHE_MEMORY_IBANK1_ADDR 0x40374000 - -#define CACHE_MEMORY_DBANK0_ADDR 0x3fcf0000 -#define CACHE_MEMORY_DBANK1_ADDR 0x3fcf8000 - #endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_CACHE_MEMORY_H */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h deleted file mode 100644 index 8d19cfb61ce0f..0000000000000 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h +++ /dev/null @@ -1,2761 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_EXTMEM_H -#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_EXTMEM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32s3_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* EXTMEM_DCACHE_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0) - -/* EXTMEM_DCACHE_BLOCKSIZE_MODE : R/W; bitpos: [4:3]; default: 0; - * The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2: - * 64 bytes - */ - -#define EXTMEM_DCACHE_BLOCKSIZE_MODE 0x00000003 -#define EXTMEM_DCACHE_BLOCKSIZE_MODE_M (EXTMEM_DCACHE_BLOCKSIZE_MODE_V << EXTMEM_DCACHE_BLOCKSIZE_MODE_S) -#define EXTMEM_DCACHE_BLOCKSIZE_MODE_V 0x00000003 -#define EXTMEM_DCACHE_BLOCKSIZE_MODE_S 3 - -/* EXTMEM_DCACHE_SIZE_MODE : R/W; bitpos: [2]; default: 0; - * The bit is used to configure cache memory size.0: 32KB, 1: 64KB - */ - -#define EXTMEM_DCACHE_SIZE_MODE (BIT(2)) -#define EXTMEM_DCACHE_SIZE_MODE_M (EXTMEM_DCACHE_SIZE_MODE_V << EXTMEM_DCACHE_SIZE_MODE_S) -#define EXTMEM_DCACHE_SIZE_MODE_V 0x00000001 -#define EXTMEM_DCACHE_SIZE_MODE_S 2 - -/* EXTMEM_DCACHE_ENABLE : R/W; bitpos: [0]; default: 0; - * The bit is used to activate the data cache. 0: disable, 1: enable - */ - -#define EXTMEM_DCACHE_ENABLE (BIT(0)) -#define EXTMEM_DCACHE_ENABLE_M (EXTMEM_DCACHE_ENABLE_V << EXTMEM_DCACHE_ENABLE_S) -#define EXTMEM_DCACHE_ENABLE_V 0x00000001 -#define EXTMEM_DCACHE_ENABLE_S 0 - -/* EXTMEM_DCACHE_CTRL1_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x4) - -/* EXTMEM_DCACHE_SHUT_CORE1_BUS : R/W; bitpos: [1]; default: 1; - * The bit is used to disable core1 dbus, 0: enable, 1: disable - */ - -#define EXTMEM_DCACHE_SHUT_CORE1_BUS (BIT(1)) -#define EXTMEM_DCACHE_SHUT_CORE1_BUS_M (EXTMEM_DCACHE_SHUT_CORE1_BUS_V << EXTMEM_DCACHE_SHUT_CORE1_BUS_S) -#define EXTMEM_DCACHE_SHUT_CORE1_BUS_V 0x00000001 -#define EXTMEM_DCACHE_SHUT_CORE1_BUS_S 1 - -/* EXTMEM_DCACHE_SHUT_CORE0_BUS : R/W; bitpos: [0]; default: 1; - * The bit is used to disable core0 dbus, 0: enable, 1: disable - */ - -#define EXTMEM_DCACHE_SHUT_CORE0_BUS (BIT(0)) -#define EXTMEM_DCACHE_SHUT_CORE0_BUS_M (EXTMEM_DCACHE_SHUT_CORE0_BUS_V << EXTMEM_DCACHE_SHUT_CORE0_BUS_S) -#define EXTMEM_DCACHE_SHUT_CORE0_BUS_V 0x00000001 -#define EXTMEM_DCACHE_SHUT_CORE0_BUS_S 0 - -/* EXTMEM_DCACHE_TAG_POWER_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x8) - -/* EXTMEM_DCACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; - * The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1: - * power up - */ - -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU (BIT(2)) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_M (EXTMEM_DCACHE_TAG_MEM_FORCE_PU_V << EXTMEM_DCACHE_TAG_MEM_FORCE_PU_S) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_V 0x00000001 -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_S 2 - -/* EXTMEM_DCACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; - * The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, - * 1: power down - */ - -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD (BIT(1)) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_M (EXTMEM_DCACHE_TAG_MEM_FORCE_PD_V << EXTMEM_DCACHE_TAG_MEM_FORCE_PD_S) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_V 0x00000001 -#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_S 1 - -/* EXTMEM_DCACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1; - * The bit is used to close clock gating of dcache tag memory. 1: close - * gating, 0: open clock gating. - */ - -#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON (BIT(0)) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_M (EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V << EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S) -#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V 0x00000001 -#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S 0 - -/* EXTMEM_DCACHE_PRELOCK_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0xc) - -/* EXTMEM_DCACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function. - */ - -#define EXTMEM_DCACHE_PRELOCK_SCT1_EN (BIT(1)) -#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_M (EXTMEM_DCACHE_PRELOCK_SCT1_EN_V << EXTMEM_DCACHE_PRELOCK_SCT1_EN_S) -#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_V 0x00000001 -#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_S 1 - -/* EXTMEM_DCACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function. - */ - -#define EXTMEM_DCACHE_PRELOCK_SCT0_EN (BIT(0)) -#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_M (EXTMEM_DCACHE_PRELOCK_SCT0_EN_V << EXTMEM_DCACHE_PRELOCK_SCT0_EN_S) -#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_V 0x00000001 -#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_S 0 - -/* EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x10) - -/* EXTMEM_DCACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the first start virtual address of data - * prelock, which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG - */ - -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR 0xffffffff -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_M (EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V << EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S) -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V 0xffffffff -#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S 0 - -/* EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x14) - -/* EXTMEM_DCACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the second start virtual address of data - * prelock, which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG - */ - -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR 0xffffffff -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_M (EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V << EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S) -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V 0xffffffff -#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S 0 - -/* EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x18) - -/* EXTMEM_DCACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [31:16]; default: 0; - * The bits are used to configure the first length of data locking, which is - * combined with DCACHE_PRELOCK_SCT0_ADDR_REG - */ - -#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE 0x0000ffff -#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_M (EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V << EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S) -#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V 0x0000ffff -#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S 16 - -/* EXTMEM_DCACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [15:0]; default: 0; - * The bits are used to configure the second length of data locking, which - * is combined with DCACHE_PRELOCK_SCT1_ADDR_REG - */ - -#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE 0x0000ffff -#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_M (EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V << EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S) -#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V 0x0000ffff -#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S 0 - -/* EXTMEM_DCACHE_LOCK_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x1c) - -/* EXTMEM_DCACHE_LOCK_DONE : RO; bitpos: [2]; default: 1; - * The bit is used to indicate unlock/lock operation is finished. - */ - -#define EXTMEM_DCACHE_LOCK_DONE (BIT(2)) -#define EXTMEM_DCACHE_LOCK_DONE_M (EXTMEM_DCACHE_LOCK_DONE_V << EXTMEM_DCACHE_LOCK_DONE_S) -#define EXTMEM_DCACHE_LOCK_DONE_V 0x00000001 -#define EXTMEM_DCACHE_LOCK_DONE_S 2 - -/* EXTMEM_DCACHE_UNLOCK_ENA : R/W; bitpos: [1]; default: 0; - * The bit is used to enable unlock operation. It will be cleared by - * hardware after unlock operation done. - */ - -#define EXTMEM_DCACHE_UNLOCK_ENA (BIT(1)) -#define EXTMEM_DCACHE_UNLOCK_ENA_M (EXTMEM_DCACHE_UNLOCK_ENA_V << EXTMEM_DCACHE_UNLOCK_ENA_S) -#define EXTMEM_DCACHE_UNLOCK_ENA_V 0x00000001 -#define EXTMEM_DCACHE_UNLOCK_ENA_S 1 - -/* EXTMEM_DCACHE_LOCK_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable lock operation. It will be cleared by hardware - * after lock operation done. - */ - -#define EXTMEM_DCACHE_LOCK_ENA (BIT(0)) -#define EXTMEM_DCACHE_LOCK_ENA_M (EXTMEM_DCACHE_LOCK_ENA_V << EXTMEM_DCACHE_LOCK_ENA_S) -#define EXTMEM_DCACHE_LOCK_ENA_V 0x00000001 -#define EXTMEM_DCACHE_LOCK_ENA_S 0 - -/* EXTMEM_DCACHE_LOCK_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x20) - -/* EXTMEM_DCACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address for lock - * operations. It should be combined with DCACHE_LOCK_SIZE_REG. - */ - -#define EXTMEM_DCACHE_LOCK_ADDR 0xffffffff -#define EXTMEM_DCACHE_LOCK_ADDR_M (EXTMEM_DCACHE_LOCK_ADDR_V << EXTMEM_DCACHE_LOCK_ADDR_S) -#define EXTMEM_DCACHE_LOCK_ADDR_V 0xffffffff -#define EXTMEM_DCACHE_LOCK_ADDR_S 0 - -/* EXTMEM_DCACHE_LOCK_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x24) - -/* EXTMEM_DCACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0; - * The bits are used to configure the length for lock operations. The bits - * are the counts of cache block. It should be combined with - * DCACHE_LOCK_ADDR_REG. - */ - -#define EXTMEM_DCACHE_LOCK_SIZE 0x0000ffff -#define EXTMEM_DCACHE_LOCK_SIZE_M (EXTMEM_DCACHE_LOCK_SIZE_V << EXTMEM_DCACHE_LOCK_SIZE_S) -#define EXTMEM_DCACHE_LOCK_SIZE_V 0x0000ffff -#define EXTMEM_DCACHE_LOCK_SIZE_S 0 - -/* EXTMEM_DCACHE_SYNC_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28) - -/* EXTMEM_DCACHE_SYNC_DONE : RO; bitpos: [3]; default: 0; - * The bit is used to indicate clean/writeback/invalidate operation is - * finished. - */ - -#define EXTMEM_DCACHE_SYNC_DONE (BIT(3)) -#define EXTMEM_DCACHE_SYNC_DONE_M (EXTMEM_DCACHE_SYNC_DONE_V << EXTMEM_DCACHE_SYNC_DONE_S) -#define EXTMEM_DCACHE_SYNC_DONE_V 0x00000001 -#define EXTMEM_DCACHE_SYNC_DONE_S 3 - -/* EXTMEM_DCACHE_CLEAN_ENA : R/W; bitpos: [2]; default: 0; - * The bit is used to enable clean operation. It will be cleared by hardware - * after clean operation done. - */ - -#define EXTMEM_DCACHE_CLEAN_ENA (BIT(2)) -#define EXTMEM_DCACHE_CLEAN_ENA_M (EXTMEM_DCACHE_CLEAN_ENA_V << EXTMEM_DCACHE_CLEAN_ENA_S) -#define EXTMEM_DCACHE_CLEAN_ENA_V 0x00000001 -#define EXTMEM_DCACHE_CLEAN_ENA_S 2 - -/* EXTMEM_DCACHE_WRITEBACK_ENA : R/W; bitpos: [1]; default: 0; - * The bit is used to enable writeback operation. It will be cleared by - * hardware after writeback operation done. - */ - -#define EXTMEM_DCACHE_WRITEBACK_ENA (BIT(1)) -#define EXTMEM_DCACHE_WRITEBACK_ENA_M (EXTMEM_DCACHE_WRITEBACK_ENA_V << EXTMEM_DCACHE_WRITEBACK_ENA_S) -#define EXTMEM_DCACHE_WRITEBACK_ENA_V 0x00000001 -#define EXTMEM_DCACHE_WRITEBACK_ENA_S 1 - -/* EXTMEM_DCACHE_INVALIDATE_ENA : R/W; bitpos: [0]; default: 1; - * The bit is used to enable invalidate operation. It will be cleared by - * hardware after invalidate operation done. - */ - -#define EXTMEM_DCACHE_INVALIDATE_ENA (BIT(0)) -#define EXTMEM_DCACHE_INVALIDATE_ENA_M (EXTMEM_DCACHE_INVALIDATE_ENA_V << EXTMEM_DCACHE_INVALIDATE_ENA_S) -#define EXTMEM_DCACHE_INVALIDATE_ENA_V 0x00000001 -#define EXTMEM_DCACHE_INVALIDATE_ENA_S 0 - -/* EXTMEM_DCACHE_SYNC_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x2c) - -/* EXTMEM_DCACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address for clean - * operations. It should be combined with DCACHE_SYNC_SIZE_REG. - */ - -#define EXTMEM_DCACHE_SYNC_ADDR 0xffffffff -#define EXTMEM_DCACHE_SYNC_ADDR_M (EXTMEM_DCACHE_SYNC_ADDR_V << EXTMEM_DCACHE_SYNC_ADDR_S) -#define EXTMEM_DCACHE_SYNC_ADDR_V 0xffffffff -#define EXTMEM_DCACHE_SYNC_ADDR_S 0 - -/* EXTMEM_DCACHE_SYNC_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x30) - -/* EXTMEM_DCACHE_SYNC_SIZE : R/W; bitpos: [22:0]; default: 0; - * The bits are used to configure the length for sync operations. The bits - * are the counts of cache block. It should be combined with - * DCACHE_SYNC_ADDR_REG. - */ - -#define EXTMEM_DCACHE_SYNC_SIZE 0x007fffff -#define EXTMEM_DCACHE_SYNC_SIZE_M (EXTMEM_DCACHE_SYNC_SIZE_V << EXTMEM_DCACHE_SYNC_SIZE_S) -#define EXTMEM_DCACHE_SYNC_SIZE_V 0x007fffff -#define EXTMEM_DCACHE_SYNC_SIZE_S 0 - -/* EXTMEM_DCACHE_OCCUPY_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_OCCUPY_CTRL_REG (DR_REG_EXTMEM_BASE + 0x34) - -/* EXTMEM_DCACHE_OCCUPY_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate occupy operation is finished. - */ - -#define EXTMEM_DCACHE_OCCUPY_DONE (BIT(1)) -#define EXTMEM_DCACHE_OCCUPY_DONE_M (EXTMEM_DCACHE_OCCUPY_DONE_V << EXTMEM_DCACHE_OCCUPY_DONE_S) -#define EXTMEM_DCACHE_OCCUPY_DONE_V 0x00000001 -#define EXTMEM_DCACHE_OCCUPY_DONE_S 1 - -/* EXTMEM_DCACHE_OCCUPY_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable occupy operation. It will be cleared by - * hardware after issuing Auot-Invalidate Operation. - */ - -#define EXTMEM_DCACHE_OCCUPY_ENA (BIT(0)) -#define EXTMEM_DCACHE_OCCUPY_ENA_M (EXTMEM_DCACHE_OCCUPY_ENA_V << EXTMEM_DCACHE_OCCUPY_ENA_S) -#define EXTMEM_DCACHE_OCCUPY_ENA_V 0x00000001 -#define EXTMEM_DCACHE_OCCUPY_ENA_S 0 - -/* EXTMEM_DCACHE_OCCUPY_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_OCCUPY_ADDR_REG (DR_REG_EXTMEM_BASE + 0x38) - -/* EXTMEM_DCACHE_OCCUPY_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address for occupy - * operation. It should be combined with DCACHE_OCCUPY_SIZE_REG. - */ - -#define EXTMEM_DCACHE_OCCUPY_ADDR 0xffffffff -#define EXTMEM_DCACHE_OCCUPY_ADDR_M (EXTMEM_DCACHE_OCCUPY_ADDR_V << EXTMEM_DCACHE_OCCUPY_ADDR_S) -#define EXTMEM_DCACHE_OCCUPY_ADDR_V 0xffffffff -#define EXTMEM_DCACHE_OCCUPY_ADDR_S 0 - -/* EXTMEM_DCACHE_OCCUPY_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_OCCUPY_SIZE_REG (DR_REG_EXTMEM_BASE + 0x3c) - -/* EXTMEM_DCACHE_OCCUPY_SIZE : R/W; bitpos: [15:0]; default: 0; - * The bits are used to configure the length for occupy operation. The bits - * are the counts of cache block. It should be combined with - * DCACHE_OCCUPY_ADDR_REG. - */ - -#define EXTMEM_DCACHE_OCCUPY_SIZE 0x0000ffff -#define EXTMEM_DCACHE_OCCUPY_SIZE_M (EXTMEM_DCACHE_OCCUPY_SIZE_V << EXTMEM_DCACHE_OCCUPY_SIZE_S) -#define EXTMEM_DCACHE_OCCUPY_SIZE_V 0x0000ffff -#define EXTMEM_DCACHE_OCCUPY_SIZE_S 0 - -/* EXTMEM_DCACHE_PRELOAD_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x40) - -/* EXTMEM_DCACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 1: - * descending, 0: ascending. - */ - -#define EXTMEM_DCACHE_PRELOAD_ORDER (BIT(2)) -#define EXTMEM_DCACHE_PRELOAD_ORDER_M (EXTMEM_DCACHE_PRELOAD_ORDER_V << EXTMEM_DCACHE_PRELOAD_ORDER_S) -#define EXTMEM_DCACHE_PRELOAD_ORDER_V 0x00000001 -#define EXTMEM_DCACHE_PRELOAD_ORDER_S 2 - -/* EXTMEM_DCACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate preload operation is finished. - */ - -#define EXTMEM_DCACHE_PRELOAD_DONE (BIT(1)) -#define EXTMEM_DCACHE_PRELOAD_DONE_M (EXTMEM_DCACHE_PRELOAD_DONE_V << EXTMEM_DCACHE_PRELOAD_DONE_S) -#define EXTMEM_DCACHE_PRELOAD_DONE_V 0x00000001 -#define EXTMEM_DCACHE_PRELOAD_DONE_S 1 - -/* EXTMEM_DCACHE_PRELOAD_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable preload operation. It will be cleared by - * hardware after preload operation done. - */ - -#define EXTMEM_DCACHE_PRELOAD_ENA (BIT(0)) -#define EXTMEM_DCACHE_PRELOAD_ENA_M (EXTMEM_DCACHE_PRELOAD_ENA_V << EXTMEM_DCACHE_PRELOAD_ENA_S) -#define EXTMEM_DCACHE_PRELOAD_ENA_V 0x00000001 -#define EXTMEM_DCACHE_PRELOAD_ENA_S 0 - -/* EXTMEM_DCACHE_PRELOAD_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x44) - -/* EXTMEM_DCACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address for preload - * operation. It should be combined with DCACHE_PRELOAD_SIZE_REG. - */ - -#define EXTMEM_DCACHE_PRELOAD_ADDR 0xffffffff -#define EXTMEM_DCACHE_PRELOAD_ADDR_M (EXTMEM_DCACHE_PRELOAD_ADDR_V << EXTMEM_DCACHE_PRELOAD_ADDR_S) -#define EXTMEM_DCACHE_PRELOAD_ADDR_V 0xffffffff -#define EXTMEM_DCACHE_PRELOAD_ADDR_S 0 - -/* EXTMEM_DCACHE_PRELOAD_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x48) - -/* EXTMEM_DCACHE_PRELOAD_SIZE : R/W; bitpos: [15:0]; default: 0; - * The bits are used to configure the length for preload operation. The bits - * are the counts of cache block. It should be combined with - * DCACHE_PRELOAD_ADDR_REG.. - */ - -#define EXTMEM_DCACHE_PRELOAD_SIZE 0x0000ffff -#define EXTMEM_DCACHE_PRELOAD_SIZE_M (EXTMEM_DCACHE_PRELOAD_SIZE_V << EXTMEM_DCACHE_PRELOAD_SIZE_S) -#define EXTMEM_DCACHE_PRELOAD_SIZE_V 0x0000ffff -#define EXTMEM_DCACHE_PRELOAD_SIZE_S 0 - -/* EXTMEM_DCACHE_AUTOLOAD_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x4c) - -/* EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR : R/W; bitpos: [9]; default: 0; - * The bit is used to clear autoload buffer in dcache. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR (BIT(9)) -#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_M (EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_V << EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_S) -#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_V 0x00000001 -#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_S 9 - -/* EXTMEM_DCACHE_AUTOLOAD_SIZE : R/W; bitpos: [8:7]; default: 0; - * The bits are used to configure the numbers of the cache block for the - * issuing autoload operation. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SIZE 0x00000003 -#define EXTMEM_DCACHE_AUTOLOAD_SIZE_M (EXTMEM_DCACHE_AUTOLOAD_SIZE_V << EXTMEM_DCACHE_AUTOLOAD_SIZE_S) -#define EXTMEM_DCACHE_AUTOLOAD_SIZE_V 0x00000003 -#define EXTMEM_DCACHE_AUTOLOAD_SIZE_S 7 - -/* EXTMEM_DCACHE_AUTOLOAD_RQST : R/W; bitpos: [6:5]; default: 0; - * The bits are used to configure trigger conditions for autoload. 0/3: - * cache miss, 1: cache hit, 2: both cache miss and hit. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_RQST 0x00000003 -#define EXTMEM_DCACHE_AUTOLOAD_RQST_M (EXTMEM_DCACHE_AUTOLOAD_RQST_V << EXTMEM_DCACHE_AUTOLOAD_RQST_S) -#define EXTMEM_DCACHE_AUTOLOAD_RQST_V 0x00000003 -#define EXTMEM_DCACHE_AUTOLOAD_RQST_S 5 - -/* EXTMEM_DCACHE_AUTOLOAD_ORDER : R/W; bitpos: [4]; default: 0; - * The bits are used to configure the direction of autoload. 1: descending, - * 0: ascending. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_ORDER (BIT(4)) -#define EXTMEM_DCACHE_AUTOLOAD_ORDER_M (EXTMEM_DCACHE_AUTOLOAD_ORDER_V << EXTMEM_DCACHE_AUTOLOAD_ORDER_S) -#define EXTMEM_DCACHE_AUTOLOAD_ORDER_V 0x00000001 -#define EXTMEM_DCACHE_AUTOLOAD_ORDER_S 4 - -/* EXTMEM_DCACHE_AUTOLOAD_DONE : RO; bitpos: [3]; default: 1; - * The bit is used to indicate autoload operation is finished. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_DONE (BIT(3)) -#define EXTMEM_DCACHE_AUTOLOAD_DONE_M (EXTMEM_DCACHE_AUTOLOAD_DONE_V << EXTMEM_DCACHE_AUTOLOAD_DONE_S) -#define EXTMEM_DCACHE_AUTOLOAD_DONE_V 0x00000001 -#define EXTMEM_DCACHE_AUTOLOAD_DONE_S 3 - -/* EXTMEM_DCACHE_AUTOLOAD_ENA : R/W; bitpos: [2]; default: 0; - * The bit is used to enable and disable autoload operation. It is combined - * with dcache_autoload_done. 1: enable, 0: disable. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_ENA (BIT(2)) -#define EXTMEM_DCACHE_AUTOLOAD_ENA_M (EXTMEM_DCACHE_AUTOLOAD_ENA_V << EXTMEM_DCACHE_AUTOLOAD_ENA_S) -#define EXTMEM_DCACHE_AUTOLOAD_ENA_V 0x00000001 -#define EXTMEM_DCACHE_AUTOLOAD_ENA_S 2 - -/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [1]; default: 0; - * The bits are used to enable the second section for autoload operation. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA (BIT(1)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_M (EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V << EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S) -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V 0x00000001 -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S 1 - -/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [0]; default: 0; - * The bits are used to enable the first section for autoload operation. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA (BIT(0)) -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_M (EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_V << EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_S) -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_V 0x00000001 -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_S 0 - -/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x50) - -/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address of the first - * section for autoload operation. It should be combined with - * dcache_autoload_sct0_ena. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR 0xffffffff -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_M (EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V << EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S) -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V 0xffffffff -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S 0 - -/* EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x54) - -/* EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [26:0]; default: 0; - * The bits are used to configure the length of the first section for - * autoload operation. It should be combined with dcache_autoload_sct0_ena. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE 0x07ffffff -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_M (EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V << EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S) -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V 0x07ffffff -#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S 0 - -/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x58) - -/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address of the second - * section for autoload operation. It should be combined with - * dcache_autoload_sct1_ena. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR 0xffffffff -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_M (EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V << EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S) -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V 0xffffffff -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S 0 - -/* EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x5c) - -/* EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [26:0]; default: 0; - * The bits are used to configure the length of the second section for - * autoload operation. It should be combined with dcache_autoload_sct1_ena. - */ - -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE 0x07ffffff -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_M (EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V << EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S) -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V 0x07ffffff -#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S 0 - -/* EXTMEM_ICACHE_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x60) - -/* EXTMEM_ICACHE_BLOCKSIZE_MODE : R/W; bitpos: [3]; default: 0; - * The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes - */ - -#define EXTMEM_ICACHE_BLOCKSIZE_MODE (BIT(3)) -#define EXTMEM_ICACHE_BLOCKSIZE_MODE_M (EXTMEM_ICACHE_BLOCKSIZE_MODE_V << EXTMEM_ICACHE_BLOCKSIZE_MODE_S) -#define EXTMEM_ICACHE_BLOCKSIZE_MODE_V 0x00000001 -#define EXTMEM_ICACHE_BLOCKSIZE_MODE_S 3 - -/* EXTMEM_ICACHE_SIZE_MODE : R/W; bitpos: [2]; default: 0; - * The bit is used to configure cache memory size.0: 16KB, 1: 32KB - */ - -#define EXTMEM_ICACHE_SIZE_MODE (BIT(2)) -#define EXTMEM_ICACHE_SIZE_MODE_M (EXTMEM_ICACHE_SIZE_MODE_V << EXTMEM_ICACHE_SIZE_MODE_S) -#define EXTMEM_ICACHE_SIZE_MODE_V 0x00000001 -#define EXTMEM_ICACHE_SIZE_MODE_S 2 - -/* EXTMEM_ICACHE_WAY_MODE : R/W; bitpos: [1]; default: 0; - * The bit is used to configure cache way mode.0: 4-way, 1: 8-way - */ - -#define EXTMEM_ICACHE_WAY_MODE (BIT(1)) -#define EXTMEM_ICACHE_WAY_MODE_M (EXTMEM_ICACHE_WAY_MODE_V << EXTMEM_ICACHE_WAY_MODE_S) -#define EXTMEM_ICACHE_WAY_MODE_V 0x00000001 -#define EXTMEM_ICACHE_WAY_MODE_S 1 - -/* EXTMEM_ICACHE_ENABLE : R/W; bitpos: [0]; default: 0; - * The bit is used to activate the data cache. 0: disable, 1: enable - */ - -#define EXTMEM_ICACHE_ENABLE (BIT(0)) -#define EXTMEM_ICACHE_ENABLE_M (EXTMEM_ICACHE_ENABLE_V << EXTMEM_ICACHE_ENABLE_S) -#define EXTMEM_ICACHE_ENABLE_V 0x00000001 -#define EXTMEM_ICACHE_ENABLE_S 0 - -/* EXTMEM_ICACHE_CTRL1_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x64) - -/* EXTMEM_ICACHE_SHUT_CORE1_BUS : R/W; bitpos: [1]; default: 1; - * The bit is used to disable core1 ibus, 0: enable, 1: disable - */ - -#define EXTMEM_ICACHE_SHUT_CORE1_BUS (BIT(1)) -#define EXTMEM_ICACHE_SHUT_CORE1_BUS_M (EXTMEM_ICACHE_SHUT_CORE1_BUS_V << EXTMEM_ICACHE_SHUT_CORE1_BUS_S) -#define EXTMEM_ICACHE_SHUT_CORE1_BUS_V 0x00000001 -#define EXTMEM_ICACHE_SHUT_CORE1_BUS_S 1 - -/* EXTMEM_ICACHE_SHUT_CORE0_BUS : R/W; bitpos: [0]; default: 1; - * The bit is used to disable core0 ibus, 0: enable, 1: disable - */ - -#define EXTMEM_ICACHE_SHUT_CORE0_BUS (BIT(0)) -#define EXTMEM_ICACHE_SHUT_CORE0_BUS_M (EXTMEM_ICACHE_SHUT_CORE0_BUS_V << EXTMEM_ICACHE_SHUT_CORE0_BUS_S) -#define EXTMEM_ICACHE_SHUT_CORE0_BUS_V 0x00000001 -#define EXTMEM_ICACHE_SHUT_CORE0_BUS_S 0 - -/* EXTMEM_ICACHE_TAG_POWER_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x68) - -/* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; - * The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: - * power up - */ - -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU (BIT(2)) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M (EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V << EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V 0x00000001 -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S 2 - -/* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; - * The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: - * power down - */ - -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD (BIT(1)) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M (EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V << EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V 0x00000001 -#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S 1 - -/* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1; - * The bit is used to close clock gating of icache tag memory. 1: close - * gating, 0: open clock gating. - */ - -#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0)) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V << EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S) -#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x00000001 -#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0 - -/* EXTMEM_ICACHE_PRELOCK_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x6c) - -/* EXTMEM_ICACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0; - * The bit is used to enable the second section of prelock function. - */ - -#define EXTMEM_ICACHE_PRELOCK_SCT1_EN (BIT(1)) -#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_M (EXTMEM_ICACHE_PRELOCK_SCT1_EN_V << EXTMEM_ICACHE_PRELOCK_SCT1_EN_S) -#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_V 0x00000001 -#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_S 1 - -/* EXTMEM_ICACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0; - * The bit is used to enable the first section of prelock function. - */ - -#define EXTMEM_ICACHE_PRELOCK_SCT0_EN (BIT(0)) -#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_M (EXTMEM_ICACHE_PRELOCK_SCT0_EN_V << EXTMEM_ICACHE_PRELOCK_SCT0_EN_S) -#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_V 0x00000001 -#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_S 0 - -/* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x70) - -/* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the first start virtual address of data - * prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG - */ - -#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR 0xffffffff -#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_M (EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V << EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S) -#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V 0xffffffff -#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S 0 - -/* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x74) - -/* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the second start virtual address of data - * prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG - */ - -#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR 0xffffffff -#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_M (EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V << EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S) -#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V 0xffffffff -#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S 0 - -/* EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x78) - -/* EXTMEM_ICACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [31:16]; default: 0; - * The bits are used to configure the first length of data locking, which is - * combined with ICACHE_PRELOCK_SCT0_ADDR_REG - */ - -#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE 0x0000ffff -#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M (EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V << EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S) -#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V 0x0000ffff -#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S 16 - -/* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [15:0]; default: 0; - * The bits are used to configure the second length of data locking, which - * is combined with ICACHE_PRELOCK_SCT1_ADDR_REG - */ - -#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE 0x0000ffff -#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_M (EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V << EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S) -#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V 0x0000ffff -#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S 0 - -/* EXTMEM_ICACHE_LOCK_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x7c) - -/* EXTMEM_ICACHE_LOCK_DONE : RO; bitpos: [2]; default: 1; - * The bit is used to indicate unlock/lock operation is finished. - */ - -#define EXTMEM_ICACHE_LOCK_DONE (BIT(2)) -#define EXTMEM_ICACHE_LOCK_DONE_M (EXTMEM_ICACHE_LOCK_DONE_V << EXTMEM_ICACHE_LOCK_DONE_S) -#define EXTMEM_ICACHE_LOCK_DONE_V 0x00000001 -#define EXTMEM_ICACHE_LOCK_DONE_S 2 - -/* EXTMEM_ICACHE_UNLOCK_ENA : R/W; bitpos: [1]; default: 0; - * The bit is used to enable unlock operation. It will be cleared by - * hardware after unlock operation done. - */ - -#define EXTMEM_ICACHE_UNLOCK_ENA (BIT(1)) -#define EXTMEM_ICACHE_UNLOCK_ENA_M (EXTMEM_ICACHE_UNLOCK_ENA_V << EXTMEM_ICACHE_UNLOCK_ENA_S) -#define EXTMEM_ICACHE_UNLOCK_ENA_V 0x00000001 -#define EXTMEM_ICACHE_UNLOCK_ENA_S 1 - -/* EXTMEM_ICACHE_LOCK_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable lock operation. It will be cleared by hardware - * after lock operation done. - */ - -#define EXTMEM_ICACHE_LOCK_ENA (BIT(0)) -#define EXTMEM_ICACHE_LOCK_ENA_M (EXTMEM_ICACHE_LOCK_ENA_V << EXTMEM_ICACHE_LOCK_ENA_S) -#define EXTMEM_ICACHE_LOCK_ENA_V 0x00000001 -#define EXTMEM_ICACHE_LOCK_ENA_S 0 - -/* EXTMEM_ICACHE_LOCK_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x80) - -/* EXTMEM_ICACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address for lock - * operations. It should be combined with ICACHE_LOCK_SIZE_REG. - */ - -#define EXTMEM_ICACHE_LOCK_ADDR 0xffffffff -#define EXTMEM_ICACHE_LOCK_ADDR_M (EXTMEM_ICACHE_LOCK_ADDR_V << EXTMEM_ICACHE_LOCK_ADDR_S) -#define EXTMEM_ICACHE_LOCK_ADDR_V 0xffffffff -#define EXTMEM_ICACHE_LOCK_ADDR_S 0 - -/* EXTMEM_ICACHE_LOCK_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x84) - -/* EXTMEM_ICACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0; - * The bits are used to configure the length for lock operations. The bits - * are the counts of cache block. It should be combined with - * ICACHE_LOCK_ADDR_REG. - */ - -#define EXTMEM_ICACHE_LOCK_SIZE 0x0000ffff -#define EXTMEM_ICACHE_LOCK_SIZE_M (EXTMEM_ICACHE_LOCK_SIZE_V << EXTMEM_ICACHE_LOCK_SIZE_S) -#define EXTMEM_ICACHE_LOCK_SIZE_V 0x0000ffff -#define EXTMEM_ICACHE_LOCK_SIZE_S 0 - -/* EXTMEM_ICACHE_SYNC_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x88) - -/* EXTMEM_ICACHE_SYNC_DONE : RO; bitpos: [1]; default: 0; - * The bit is used to indicate invalidate operation is finished. - */ - -#define EXTMEM_ICACHE_SYNC_DONE (BIT(1)) -#define EXTMEM_ICACHE_SYNC_DONE_M (EXTMEM_ICACHE_SYNC_DONE_V << EXTMEM_ICACHE_SYNC_DONE_S) -#define EXTMEM_ICACHE_SYNC_DONE_V 0x00000001 -#define EXTMEM_ICACHE_SYNC_DONE_S 1 - -/* EXTMEM_ICACHE_INVALIDATE_ENA : R/W; bitpos: [0]; default: 1; - * The bit is used to enable invalidate operation. It will be cleared by - * hardware after invalidate operation done. - */ - -#define EXTMEM_ICACHE_INVALIDATE_ENA (BIT(0)) -#define EXTMEM_ICACHE_INVALIDATE_ENA_M (EXTMEM_ICACHE_INVALIDATE_ENA_V << EXTMEM_ICACHE_INVALIDATE_ENA_S) -#define EXTMEM_ICACHE_INVALIDATE_ENA_V 0x00000001 -#define EXTMEM_ICACHE_INVALIDATE_ENA_S 0 - -/* EXTMEM_ICACHE_SYNC_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x8c) - -/* EXTMEM_ICACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address for clean - * operations. It should be combined with ICACHE_SYNC_SIZE_REG. - */ - -#define EXTMEM_ICACHE_SYNC_ADDR 0xffffffff -#define EXTMEM_ICACHE_SYNC_ADDR_M (EXTMEM_ICACHE_SYNC_ADDR_V << EXTMEM_ICACHE_SYNC_ADDR_S) -#define EXTMEM_ICACHE_SYNC_ADDR_V 0xffffffff -#define EXTMEM_ICACHE_SYNC_ADDR_S 0 - -/* EXTMEM_ICACHE_SYNC_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x90) - -/* EXTMEM_ICACHE_SYNC_SIZE : R/W; bitpos: [22:0]; default: 0; - * The bits are used to configure the length for sync operations. The bits - * are the counts of cache block. It should be combined with - * ICACHE_SYNC_ADDR_REG. - */ - -#define EXTMEM_ICACHE_SYNC_SIZE 0x007fffff -#define EXTMEM_ICACHE_SYNC_SIZE_M (EXTMEM_ICACHE_SYNC_SIZE_V << EXTMEM_ICACHE_SYNC_SIZE_S) -#define EXTMEM_ICACHE_SYNC_SIZE_V 0x007fffff -#define EXTMEM_ICACHE_SYNC_SIZE_S 0 - -/* EXTMEM_ICACHE_PRELOAD_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x94) - -/* EXTMEM_ICACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0; - * The bit is used to configure the direction of preload operation. 1: - * descending, 0: ascending. - */ - -#define EXTMEM_ICACHE_PRELOAD_ORDER (BIT(2)) -#define EXTMEM_ICACHE_PRELOAD_ORDER_M (EXTMEM_ICACHE_PRELOAD_ORDER_V << EXTMEM_ICACHE_PRELOAD_ORDER_S) -#define EXTMEM_ICACHE_PRELOAD_ORDER_V 0x00000001 -#define EXTMEM_ICACHE_PRELOAD_ORDER_S 2 - -/* EXTMEM_ICACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1; - * The bit is used to indicate preload operation is finished. - */ - -#define EXTMEM_ICACHE_PRELOAD_DONE (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_DONE_M (EXTMEM_ICACHE_PRELOAD_DONE_V << EXTMEM_ICACHE_PRELOAD_DONE_S) -#define EXTMEM_ICACHE_PRELOAD_DONE_V 0x00000001 -#define EXTMEM_ICACHE_PRELOAD_DONE_S 1 - -/* EXTMEM_ICACHE_PRELOAD_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable preload operation. It will be cleared by - * hardware after preload operation done. - */ - -#define EXTMEM_ICACHE_PRELOAD_ENA (BIT(0)) -#define EXTMEM_ICACHE_PRELOAD_ENA_M (EXTMEM_ICACHE_PRELOAD_ENA_V << EXTMEM_ICACHE_PRELOAD_ENA_S) -#define EXTMEM_ICACHE_PRELOAD_ENA_V 0x00000001 -#define EXTMEM_ICACHE_PRELOAD_ENA_S 0 - -/* EXTMEM_ICACHE_PRELOAD_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x98) - -/* EXTMEM_ICACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address for preload - * operation. It should be combined with ICACHE_PRELOAD_SIZE_REG. - */ - -#define EXTMEM_ICACHE_PRELOAD_ADDR 0xffffffff -#define EXTMEM_ICACHE_PRELOAD_ADDR_M (EXTMEM_ICACHE_PRELOAD_ADDR_V << EXTMEM_ICACHE_PRELOAD_ADDR_S) -#define EXTMEM_ICACHE_PRELOAD_ADDR_V 0xffffffff -#define EXTMEM_ICACHE_PRELOAD_ADDR_S 0 - -/* EXTMEM_ICACHE_PRELOAD_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x9c) - -/* EXTMEM_ICACHE_PRELOAD_SIZE : R/W; bitpos: [15:0]; default: 0; - * The bits are used to configure the length for preload operation. The bits - * are the counts of cache block. It should be combined with - * ICACHE_PRELOAD_ADDR_REG.. - */ - -#define EXTMEM_ICACHE_PRELOAD_SIZE 0x0000ffff -#define EXTMEM_ICACHE_PRELOAD_SIZE_M (EXTMEM_ICACHE_PRELOAD_SIZE_V << EXTMEM_ICACHE_PRELOAD_SIZE_S) -#define EXTMEM_ICACHE_PRELOAD_SIZE_V 0x0000ffff -#define EXTMEM_ICACHE_PRELOAD_SIZE_S 0 - -/* EXTMEM_ICACHE_AUTOLOAD_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0xa0) - -/* EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR : R/W; bitpos: [9]; default: 0; - * The bit is used to clear autoload buffer in icache. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR (BIT(9)) -#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_M (EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_V << EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_S) -#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_V 0x00000001 -#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_S 9 - -/* EXTMEM_ICACHE_AUTOLOAD_SIZE : R/W; bitpos: [8:7]; default: 0; - * The bits are used to configure the numbers of the cache block for the - * issuing autoload operation. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SIZE 0x00000003 -#define EXTMEM_ICACHE_AUTOLOAD_SIZE_M (EXTMEM_ICACHE_AUTOLOAD_SIZE_V << EXTMEM_ICACHE_AUTOLOAD_SIZE_S) -#define EXTMEM_ICACHE_AUTOLOAD_SIZE_V 0x00000003 -#define EXTMEM_ICACHE_AUTOLOAD_SIZE_S 7 - -/* EXTMEM_ICACHE_AUTOLOAD_RQST : R/W; bitpos: [6:5]; default: 0; - * The bits are used to configure trigger conditions for autoload. 0/3: - * cache miss, 1: cache hit, 2: both cache miss and hit. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_RQST 0x00000003 -#define EXTMEM_ICACHE_AUTOLOAD_RQST_M (EXTMEM_ICACHE_AUTOLOAD_RQST_V << EXTMEM_ICACHE_AUTOLOAD_RQST_S) -#define EXTMEM_ICACHE_AUTOLOAD_RQST_V 0x00000003 -#define EXTMEM_ICACHE_AUTOLOAD_RQST_S 5 - -/* EXTMEM_ICACHE_AUTOLOAD_ORDER : R/W; bitpos: [4]; default: 0; - * The bits are used to configure the direction of autoload. 1: descending, - * 0: ascending. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_ORDER (BIT(4)) -#define EXTMEM_ICACHE_AUTOLOAD_ORDER_M (EXTMEM_ICACHE_AUTOLOAD_ORDER_V << EXTMEM_ICACHE_AUTOLOAD_ORDER_S) -#define EXTMEM_ICACHE_AUTOLOAD_ORDER_V 0x00000001 -#define EXTMEM_ICACHE_AUTOLOAD_ORDER_S 4 - -/* EXTMEM_ICACHE_AUTOLOAD_DONE : RO; bitpos: [3]; default: 1; - * The bit is used to indicate autoload operation is finished. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_DONE (BIT(3)) -#define EXTMEM_ICACHE_AUTOLOAD_DONE_M (EXTMEM_ICACHE_AUTOLOAD_DONE_V << EXTMEM_ICACHE_AUTOLOAD_DONE_S) -#define EXTMEM_ICACHE_AUTOLOAD_DONE_V 0x00000001 -#define EXTMEM_ICACHE_AUTOLOAD_DONE_S 3 - -/* EXTMEM_ICACHE_AUTOLOAD_ENA : R/W; bitpos: [2]; default: 0; - * The bit is used to enable and disable autoload operation. It is combined - * with icache_autoload_done. 1: enable, 0: disable. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_ENA (BIT(2)) -#define EXTMEM_ICACHE_AUTOLOAD_ENA_M (EXTMEM_ICACHE_AUTOLOAD_ENA_V << EXTMEM_ICACHE_AUTOLOAD_ENA_S) -#define EXTMEM_ICACHE_AUTOLOAD_ENA_V 0x00000001 -#define EXTMEM_ICACHE_AUTOLOAD_ENA_S 2 - -/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [1]; default: 0; - * The bits are used to enable the second section for autoload operation. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA (BIT(1)) -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_M (EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V << EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S) -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V 0x00000001 -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S 1 - -/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [0]; default: 0; - * The bits are used to enable the first section for autoload operation. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA (BIT(0)) -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_M (EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V << EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S) -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V 0x00000001 -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S 0 - -/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0xa4) - -/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address of the first - * section for autoload operation. It should be combined with - * icache_autoload_sct0_ena. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR 0xffffffff -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_M (EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V << EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S) -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V 0xffffffff -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S 0 - -/* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0xa8) - -/* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [26:0]; default: 0; - * The bits are used to configure the length of the first section for - * autoload operation. It should be combined with icache_autoload_sct0_ena. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE 0x07ffffff -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_M (EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V << EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S) -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V 0x07ffffff -#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S 0 - -/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0xac) - -/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address of the second - * section for autoload operation. It should be combined with - * icache_autoload_sct1_ena. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR 0xffffffff -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_M (EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V << EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S) -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V 0xffffffff -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S 0 - -/* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0xb0) - -/* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [26:0]; default: 0; - * The bits are used to configure the length of the second section for - * autoload operation. It should be combined with icache_autoload_sct1_ena. - */ - -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE 0x07ffffff -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_M (EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V << EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S) -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V 0x07ffffff -#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S 0 - -/* EXTMEM_IBUS_TO_FLASH_START_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0xb4) - -/* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W; bitpos: [31:0]; default: - * 1140850688; - * The bits are used to configure the start virtual address of ibus to - * access flash. The register is used to give constraints to ibus access - * counter. - */ - -#define EXTMEM_IBUS_TO_FLASH_START_VADDR 0xffffffff -#define EXTMEM_IBUS_TO_FLASH_START_VADDR_M (EXTMEM_IBUS_TO_FLASH_START_VADDR_V << EXTMEM_IBUS_TO_FLASH_START_VADDR_S) -#define EXTMEM_IBUS_TO_FLASH_START_VADDR_V 0xffffffff -#define EXTMEM_IBUS_TO_FLASH_START_VADDR_S 0 - -/* EXTMEM_IBUS_TO_FLASH_END_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0xb8) - -/* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W; bitpos: [31:0]; default: 1207959551; - * The bits are used to configure the end virtual address of ibus to access - * flash. The register is used to give constraints to ibus access counter. - */ - -#define EXTMEM_IBUS_TO_FLASH_END_VADDR 0xffffffff -#define EXTMEM_IBUS_TO_FLASH_END_VADDR_M (EXTMEM_IBUS_TO_FLASH_END_VADDR_V << EXTMEM_IBUS_TO_FLASH_END_VADDR_S) -#define EXTMEM_IBUS_TO_FLASH_END_VADDR_V 0xffffffff -#define EXTMEM_IBUS_TO_FLASH_END_VADDR_S 0 - -/* EXTMEM_DBUS_TO_FLASH_START_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0xbc) - -/* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the start virtual address of dbus to - * access flash. The register is used to give constraints to dbus access - * counter. - */ - -#define EXTMEM_DBUS_TO_FLASH_START_VADDR 0xffffffff -#define EXTMEM_DBUS_TO_FLASH_START_VADDR_M (EXTMEM_DBUS_TO_FLASH_START_VADDR_V << EXTMEM_DBUS_TO_FLASH_START_VADDR_S) -#define EXTMEM_DBUS_TO_FLASH_START_VADDR_V 0xffffffff -#define EXTMEM_DBUS_TO_FLASH_START_VADDR_S 0 - -/* EXTMEM_DBUS_TO_FLASH_END_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0xc0) - -/* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W; bitpos: [31:0]; default: 0; - * The bits are used to configure the end virtual address of dbus to access - * flash. The register is used to give constraints to dbus access counter. - */ - -#define EXTMEM_DBUS_TO_FLASH_END_VADDR 0xffffffff -#define EXTMEM_DBUS_TO_FLASH_END_VADDR_M (EXTMEM_DBUS_TO_FLASH_END_VADDR_V << EXTMEM_DBUS_TO_FLASH_END_VADDR_S) -#define EXTMEM_DBUS_TO_FLASH_END_VADDR_V 0xffffffff -#define EXTMEM_DBUS_TO_FLASH_END_VADDR_S 0 - -/* EXTMEM_CACHE_ACS_CNT_CLR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0xc4) - -/* EXTMEM_ICACHE_ACS_CNT_CLR : WOD; bitpos: [1]; default: 0; - * The bit is used to clear icache counter. - */ - -#define EXTMEM_ICACHE_ACS_CNT_CLR (BIT(1)) -#define EXTMEM_ICACHE_ACS_CNT_CLR_M (EXTMEM_ICACHE_ACS_CNT_CLR_V << EXTMEM_ICACHE_ACS_CNT_CLR_S) -#define EXTMEM_ICACHE_ACS_CNT_CLR_V 0x00000001 -#define EXTMEM_ICACHE_ACS_CNT_CLR_S 1 - -/* EXTMEM_DCACHE_ACS_CNT_CLR : WOD; bitpos: [0]; default: 0; - * The bit is used to clear dcache counter. - */ - -#define EXTMEM_DCACHE_ACS_CNT_CLR (BIT(0)) -#define EXTMEM_DCACHE_ACS_CNT_CLR_M (EXTMEM_DCACHE_ACS_CNT_CLR_V << EXTMEM_DCACHE_ACS_CNT_CLR_S) -#define EXTMEM_DCACHE_ACS_CNT_CLR_V 0x00000001 -#define EXTMEM_DCACHE_ACS_CNT_CLR_S 0 - -/* EXTMEM_IBUS_ACS_MISS_CNT_REG register - * ******* Description *********** - */ - -#define EXTMEM_IBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xc8) - -/* EXTMEM_IBUS_ACS_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The bits are used to count the number of the cache miss caused by ibus - * access flash/spiram. - */ - -#define EXTMEM_IBUS_ACS_MISS_CNT 0xffffffff -#define EXTMEM_IBUS_ACS_MISS_CNT_M (EXTMEM_IBUS_ACS_MISS_CNT_V << EXTMEM_IBUS_ACS_MISS_CNT_S) -#define EXTMEM_IBUS_ACS_MISS_CNT_V 0xffffffff -#define EXTMEM_IBUS_ACS_MISS_CNT_S 0 - -/* EXTMEM_IBUS_ACS_CNT_REG register - * ******* Description *********** - */ - -#define EXTMEM_IBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xcc) - -/* EXTMEM_IBUS_ACS_CNT : RO; bitpos: [31:0]; default: 0; - * The bits are used to count the number of ibus access flash/spiram through - * icache. - */ - -#define EXTMEM_IBUS_ACS_CNT 0xffffffff -#define EXTMEM_IBUS_ACS_CNT_M (EXTMEM_IBUS_ACS_CNT_V << EXTMEM_IBUS_ACS_CNT_S) -#define EXTMEM_IBUS_ACS_CNT_V 0xffffffff -#define EXTMEM_IBUS_ACS_CNT_S 0 - -/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG register - * ******* Description *********** - */ - -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xd0) - -/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The bits are used to count the number of the cache miss caused by dbus - * access flash. - */ - -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT 0xffffffff -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_M (EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V << EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S) -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V 0xffffffff -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S 0 - -/* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_REG register - * ******* Description *********** - */ - -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xd4) - -/* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT : RO; bitpos: [31:0]; default: 0; - * The bits are used to count the number of the cache miss caused by dbus - * access spiram. - */ - -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT 0xffffffff -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_M (EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V << EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S) -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V 0xffffffff -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S 0 - -/* EXTMEM_DBUS_ACS_CNT_REG register - * ******* Description *********** - */ - -#define EXTMEM_DBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xd8) - -/* EXTMEM_DBUS_ACS_CNT : RO; bitpos: [31:0]; default: 0; - * The bits are used to count the number of dbus access flash/spiram through - * dcache. - */ - -#define EXTMEM_DBUS_ACS_CNT 0xffffffff -#define EXTMEM_DBUS_ACS_CNT_M (EXTMEM_DBUS_ACS_CNT_V << EXTMEM_DBUS_ACS_CNT_S) -#define EXTMEM_DBUS_ACS_CNT_V 0xffffffff -#define EXTMEM_DBUS_ACS_CNT_S 0 - -/* EXTMEM_CACHE_ILG_INT_ENA_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_ILG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0xdc) - -/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W; bitpos: [8]; default: 0; - * The bit is used to enable interrupt by dbus counter overflow. - */ - -#define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(8)) -#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (EXTMEM_DBUS_CNT_OVF_INT_ENA_V << EXTMEM_DBUS_CNT_OVF_INT_ENA_S) -#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x00000001 -#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 8 - -/* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W; bitpos: [7]; default: 0; - * The bit is used to enable interrupt by ibus counter overflow. - */ - -#define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(7)) -#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (EXTMEM_IBUS_CNT_OVF_INT_ENA_V << EXTMEM_IBUS_CNT_OVF_INT_ENA_S) -#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x00000001 -#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 7 - -/* EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA : R/W; bitpos: [6]; default: 0; - * The bit is used to enable interrupt by dcache trying to replace a line - * whose blocks all have been occupied by occupy-mode. - */ - -#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA (BIT(6)) -#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_M (EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_V << EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_S) -#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_V 0x00000001 -#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_S 6 - -/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W; bitpos: [5]; default: 0; - * The bit is used to enable interrupt by mmu entry fault. - */ - -#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(5)) -#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V << EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S) -#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x00000001 -#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 5 - -/* EXTMEM_DCACHE_WRITE_FLASH_INT_ENA : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt by dcache trying to write flash. - */ - -#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA (BIT(4)) -#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_M (EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V << EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S) -#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V 0x00000001 -#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S 4 - -/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA : R/W; bitpos: [3]; default: 0; - * The bit is used to enable interrupt by preload configurations fault. - */ - -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(3)) -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_M (EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_V << EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_S) -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x00000001 -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_S 3 - -/* EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA : R/W; bitpos: [2]; default: 0; - * The bit is used to enable interrupt by sync configurations fault. - */ - -#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA (BIT(2)) -#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_M (EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_V << EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_S) -#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_V 0x00000001 -#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_S 2 - -/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W; bitpos: [1]; default: 0; - * The bit is used to enable interrupt by preload configurations fault. - */ - -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M (EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V << EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x00000001 -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S 1 - -/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable interrupt by sync configurations fault. - */ - -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA (BIT(0)) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M (EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V << EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V 0x00000001 -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S 0 - -/* EXTMEM_CACHE_ILG_INT_CLR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_ILG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0xe0) - -/* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD; bitpos: [8]; default: 0; - * The bit is used to clear interrupt by dbus counter overflow. - */ - -#define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(8)) -#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (EXTMEM_DBUS_CNT_OVF_INT_CLR_V << EXTMEM_DBUS_CNT_OVF_INT_CLR_S) -#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x00000001 -#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 8 - -/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD; bitpos: [7]; default: 0; - * The bit is used to clear interrupt by ibus counter overflow. - */ - -#define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(7)) -#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (EXTMEM_IBUS_CNT_OVF_INT_CLR_V << EXTMEM_IBUS_CNT_OVF_INT_CLR_S) -#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x00000001 -#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 7 - -/* EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR : WOD; bitpos: [6]; default: 0; - * The bit is used to clear interrupt by dcache trying to replace a line - * whose blocks all have been occupied by occupy-mode. - */ - -#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR (BIT(6)) -#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_M (EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_V << EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_S) -#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_V 0x00000001 -#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_S 6 - -/* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD; bitpos: [5]; default: 0; - * The bit is used to clear interrupt by mmu entry fault. - */ - -#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(5)) -#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M (EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V << EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S) -#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V 0x00000001 -#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S 5 - -/* EXTMEM_DCACHE_WRITE_FLASH_INT_CLR : WOD; bitpos: [4]; default: 0; - * The bit is used to clear interrupt by dcache trying to write flash. - */ - -#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR (BIT(4)) -#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_M (EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V << EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S) -#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V 0x00000001 -#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S 4 - -/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR : WOD; bitpos: [3]; default: 0; - * The bit is used to clear interrupt by preload configurations fault. - */ - -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(3)) -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_M (EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_V << EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_S) -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x00000001 -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_S 3 - -/* EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR : WOD; bitpos: [2]; default: 0; - * The bit is used to clear interrupt by sync configurations fault. - */ - -#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR (BIT(2)) -#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_M (EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_V << EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_S) -#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_V 0x00000001 -#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_S 2 - -/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD; bitpos: [1]; default: 0; - * The bit is used to clear interrupt by preload configurations fault. - */ - -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M (EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V << EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x00000001 -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S 1 - -/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD; bitpos: [0]; default: 0; - * The bit is used to clear interrupt by sync configurations fault. - */ - -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR (BIT(0)) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M (EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V << EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V 0x00000001 -#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S 0 - -/* EXTMEM_CACHE_ILG_INT_ST_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_ILG_INT_ST_REG (DR_REG_EXTMEM_BASE + 0xe4) - -/* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST : RO; bitpos: [11]; default: 0; - * The bit is used to indicate interrupt by dbus access spiram miss counter - * overflow. - */ - -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST (BIT(11)) -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_M (EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_V << EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_S) -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_V 0x00000001 -#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_S 11 - -/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO; bitpos: [10]; default: 0; - * The bit is used to indicate interrupt by dbus access flash miss counter - * overflow. - */ - -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST (BIT(10)) -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M (EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V << EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S) -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V 0x00000001 -#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S 10 - -/* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO; bitpos: [9]; default: 0; - * The bit is used to indicate interrupt by dbus access flash/spiram counter - * overflow. - */ - -#define EXTMEM_DBUS_ACS_CNT_OVF_ST (BIT(9)) -#define EXTMEM_DBUS_ACS_CNT_OVF_ST_M (EXTMEM_DBUS_ACS_CNT_OVF_ST_V << EXTMEM_DBUS_ACS_CNT_OVF_ST_S) -#define EXTMEM_DBUS_ACS_CNT_OVF_ST_V 0x00000001 -#define EXTMEM_DBUS_ACS_CNT_OVF_ST_S 9 - -/* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO; bitpos: [8]; default: 0; - * The bit is used to indicate interrupt by ibus access flash/spiram miss - * counter overflow. - */ - -#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST (BIT(8)) -#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M (EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V << EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S) -#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V 0x00000001 -#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S 8 - -/* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO; bitpos: [7]; default: 0; - * The bit is used to indicate interrupt by ibus access flash/spiram counter - * overflow. - */ - -#define EXTMEM_IBUS_ACS_CNT_OVF_ST (BIT(7)) -#define EXTMEM_IBUS_ACS_CNT_OVF_ST_M (EXTMEM_IBUS_ACS_CNT_OVF_ST_V << EXTMEM_IBUS_ACS_CNT_OVF_ST_S) -#define EXTMEM_IBUS_ACS_CNT_OVF_ST_V 0x00000001 -#define EXTMEM_IBUS_ACS_CNT_OVF_ST_S 7 - -/* EXTMEM_DCACHE_OCCUPY_EXC_ST : RO; bitpos: [6]; default: 0; - * The bit is used to indicate interrupt by dcache trying to replace a line - * whose blocks all have been occupied by occupy-mode. - */ - -#define EXTMEM_DCACHE_OCCUPY_EXC_ST (BIT(6)) -#define EXTMEM_DCACHE_OCCUPY_EXC_ST_M (EXTMEM_DCACHE_OCCUPY_EXC_ST_V << EXTMEM_DCACHE_OCCUPY_EXC_ST_S) -#define EXTMEM_DCACHE_OCCUPY_EXC_ST_V 0x00000001 -#define EXTMEM_DCACHE_OCCUPY_EXC_ST_S 6 - -/* EXTMEM_MMU_ENTRY_FAULT_ST : RO; bitpos: [5]; default: 0; - * The bit is used to indicate interrupt by mmu entry fault. - */ - -#define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(5)) -#define EXTMEM_MMU_ENTRY_FAULT_ST_M (EXTMEM_MMU_ENTRY_FAULT_ST_V << EXTMEM_MMU_ENTRY_FAULT_ST_S) -#define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x00000001 -#define EXTMEM_MMU_ENTRY_FAULT_ST_S 5 - -/* EXTMEM_DCACHE_WRITE_FLASH_ST : RO; bitpos: [4]; default: 0; - * The bit is used to indicate interrupt by dcache trying to write flash. - */ - -#define EXTMEM_DCACHE_WRITE_FLASH_ST (BIT(4)) -#define EXTMEM_DCACHE_WRITE_FLASH_ST_M (EXTMEM_DCACHE_WRITE_FLASH_ST_V << EXTMEM_DCACHE_WRITE_FLASH_ST_S) -#define EXTMEM_DCACHE_WRITE_FLASH_ST_V 0x00000001 -#define EXTMEM_DCACHE_WRITE_FLASH_ST_S 4 - -/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST : RO; bitpos: [3]; default: 0; - * The bit is used to indicate interrupt by preload configurations fault. - */ - -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST (BIT(3)) -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_M (EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_V << EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_S) -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_V 0x00000001 -#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_S 3 - -/* EXTMEM_DCACHE_SYNC_OP_FAULT_ST : RO; bitpos: [2]; default: 0; - * The bit is used to indicate interrupt by sync configurations fault. - */ - -#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST (BIT(2)) -#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_M (EXTMEM_DCACHE_SYNC_OP_FAULT_ST_V << EXTMEM_DCACHE_SYNC_OP_FAULT_ST_S) -#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_V 0x00000001 -#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_S 2 - -/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO; bitpos: [1]; default: 0; - * The bit is used to indicate interrupt by preload configurations fault. - */ - -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M (EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V << EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S) -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V 0x00000001 -#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S 1 - -/* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO; bitpos: [0]; default: 0; - * The bit is used to indicate interrupt by sync configurations fault. - */ - -#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST (BIT(0)) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M (EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V << EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S) -#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V 0x00000001 -#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S 0 - -/* EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0xe8) - -/* EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt by authentication fail. - */ - -#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA (BIT(4)) -#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M (EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V << EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S) -#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V 0x00000001 -#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S 4 - -/* EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA : R/W; bitpos: [3]; default: 0; - * The bit is used to enable interrupt by cpu access dcache while the - * corresponding dbus is disabled which include speculative access. - */ - -#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA (BIT(3)) -#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_M (EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_V << EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_S) -#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_V 0x00000001 -#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_S 3 - -/* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W; bitpos: [2]; default: 0; - * The bit is used to enable interrupt by authentication fail. - */ - -#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA (BIT(2)) -#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M (EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V << EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S) -#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V 0x00000001 -#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S 2 - -/* EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W; bitpos: [1]; default: 0; - * The bit is used to enable interrupt by ibus trying to write icache - */ - -#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA (BIT(1)) -#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M (EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V << EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S) -#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V 0x00000001 -#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S 1 - -/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable interrupt by cpu access icache while the - * corresponding ibus is disabled which include speculative access. - */ - -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M (EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V << EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S) -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V 0x00000001 -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S 0 - -/* EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0xec) - -/* EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD; bitpos: [4]; default: 0; - * The bit is used to clear interrupt by authentication fail. - */ - -#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR (BIT(4)) -#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M (EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V << EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S) -#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V 0x00000001 -#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S 4 - -/* EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR : WOD; bitpos: [3]; default: 0; - * The bit is used to clear interrupt by cpu access dcache while the - * corresponding dbus is disabled or dcache is disabled which include - * speculative access. - */ - -#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR (BIT(3)) -#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_M (EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_V << EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_S) -#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_V 0x00000001 -#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_S 3 - -/* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD; bitpos: [2]; default: 0; - * The bit is used to clear interrupt by authentication fail. - */ - -#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR (BIT(2)) -#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M (EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V << EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S) -#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V 0x00000001 -#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S 2 - -/* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD; bitpos: [1]; default: 0; - * The bit is used to clear interrupt by ibus trying to write icache - */ - -#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR (BIT(1)) -#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M (EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V << EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S) -#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V 0x00000001 -#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S 1 - -/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD; bitpos: [0]; default: 0; - * The bit is used to clear interrupt by cpu access icache while the - * corresponding ibus is disabled or icache is disabled which include - * speculative access. - */ - -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M (EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V << EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S) -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V 0x00000001 -#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S 0 - -/* EXTMEM_CORE0_ACS_CACHE_INT_ST_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0xf0) - -/* EXTMEM_CORE0_DBUS_REJECT_ST : RO; bitpos: [4]; default: 0; - * The bit is used to indicate interrupt by authentication fail. - */ - -#define EXTMEM_CORE0_DBUS_REJECT_ST (BIT(4)) -#define EXTMEM_CORE0_DBUS_REJECT_ST_M (EXTMEM_CORE0_DBUS_REJECT_ST_V << EXTMEM_CORE0_DBUS_REJECT_ST_S) -#define EXTMEM_CORE0_DBUS_REJECT_ST_V 0x00000001 -#define EXTMEM_CORE0_DBUS_REJECT_ST_S 4 - -/* EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST : RO; bitpos: [3]; default: 0; - * The bit is used to indicate interrupt by cpu access dcache while the - * core0_dbus is disabled or dcache is disabled which include speculative - * access. - */ - -#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST (BIT(3)) -#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_M (EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_V << EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_S) -#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_V 0x00000001 -#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_S 3 - -/* EXTMEM_CORE0_IBUS_REJECT_ST : RO; bitpos: [2]; default: 0; - * The bit is used to indicate interrupt by authentication fail. - */ - -#define EXTMEM_CORE0_IBUS_REJECT_ST (BIT(2)) -#define EXTMEM_CORE0_IBUS_REJECT_ST_M (EXTMEM_CORE0_IBUS_REJECT_ST_V << EXTMEM_CORE0_IBUS_REJECT_ST_S) -#define EXTMEM_CORE0_IBUS_REJECT_ST_V 0x00000001 -#define EXTMEM_CORE0_IBUS_REJECT_ST_S 2 - -/* EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO; bitpos: [1]; default: 0; - * The bit is used to indicate interrupt by ibus trying to write icache - */ - -#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST (BIT(1)) -#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M (EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V << EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S) -#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V 0x00000001 -#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S 1 - -/* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO; bitpos: [0]; default: 0; - * The bit is used to indicate interrupt by cpu access icache while the - * core0_ibus is disabled or icache is disabled which include speculative - * access. - */ - -#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) -#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M (EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V << EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S) -#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V 0x00000001 -#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S 0 - -/* EXTMEM_CORE1_ACS_CACHE_INT_ENA_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE1_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0xf4) - -/* EXTMEM_CORE1_DBUS_REJECT_INT_ENA : R/W; bitpos: [4]; default: 0; - * The bit is used to enable interrupt by authentication fail. - */ - -#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA (BIT(4)) -#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_M (EXTMEM_CORE1_DBUS_REJECT_INT_ENA_V << EXTMEM_CORE1_DBUS_REJECT_INT_ENA_S) -#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_V 0x00000001 -#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_S 4 - -/* EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA : R/W; bitpos: [3]; default: 0; - * The bit is used to enable interrupt by cpu access dcache while the - * corresponding dbus is disabled which include speculative access. - */ - -#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA (BIT(3)) -#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_M (EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_V << EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_S) -#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_V 0x00000001 -#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_S 3 - -/* EXTMEM_CORE1_IBUS_REJECT_INT_ENA : R/W; bitpos: [2]; default: 0; - * The bit is used to enable interrupt by authentication fail. - */ - -#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA (BIT(2)) -#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_M (EXTMEM_CORE1_IBUS_REJECT_INT_ENA_V << EXTMEM_CORE1_IBUS_REJECT_INT_ENA_S) -#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_V 0x00000001 -#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_S 2 - -/* EXTMEM_CORE1_IBUS_WR_IC_INT_ENA : R/W; bitpos: [1]; default: 0; - * The bit is used to enable interrupt by ibus trying to write icache - */ - -#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA (BIT(1)) -#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_M (EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_V << EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_S) -#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_V 0x00000001 -#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_S 1 - -/* EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable interrupt by cpu access icache while the - * corresponding ibus is disabled which include speculative access. - */ - -#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) -#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_M (EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_V << EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_S) -#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_V 0x00000001 -#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_S 0 - -/* EXTMEM_CORE1_ACS_CACHE_INT_CLR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE1_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0xf8) - -/* EXTMEM_CORE1_DBUS_REJECT_INT_CLR : WOD; bitpos: [4]; default: 0; - * The bit is used to clear interrupt by authentication fail. - */ - -#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR (BIT(4)) -#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_M (EXTMEM_CORE1_DBUS_REJECT_INT_CLR_V << EXTMEM_CORE1_DBUS_REJECT_INT_CLR_S) -#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_V 0x00000001 -#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_S 4 - -/* EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR : WOD; bitpos: [3]; default: 0; - * The bit is used to clear interrupt by cpu access dcache while the - * corresponding dbus is disabled or dcache is disabled which include - * speculative access. - */ - -#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR (BIT(3)) -#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_M (EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_V << EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_S) -#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_V 0x00000001 -#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_S 3 - -/* EXTMEM_CORE1_IBUS_REJECT_INT_CLR : WOD; bitpos: [2]; default: 0; - * The bit is used to clear interrupt by authentication fail. - */ - -#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR (BIT(2)) -#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_M (EXTMEM_CORE1_IBUS_REJECT_INT_CLR_V << EXTMEM_CORE1_IBUS_REJECT_INT_CLR_S) -#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_V 0x00000001 -#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_S 2 - -/* EXTMEM_CORE1_IBUS_WR_IC_INT_CLR : WOD; bitpos: [1]; default: 0; - * The bit is used to clear interrupt by ibus trying to write icache - */ - -#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR (BIT(1)) -#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_M (EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_V << EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_S) -#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_V 0x00000001 -#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_S 1 - -/* EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR : WOD; bitpos: [0]; default: 0; - * The bit is used to clear interrupt by cpu access icache while the - * corresponding ibus is disabled or icache is disabled which include - * speculative access. - */ - -#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) -#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_M (EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_V << EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_S) -#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_V 0x00000001 -#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_S 0 - -/* EXTMEM_CORE1_ACS_CACHE_INT_ST_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE1_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0xfc) - -/* EXTMEM_CORE1_DBUS_REJECT_ST : RO; bitpos: [4]; default: 0; - * The bit is used to indicate interrupt by authentication fail. - */ - -#define EXTMEM_CORE1_DBUS_REJECT_ST (BIT(4)) -#define EXTMEM_CORE1_DBUS_REJECT_ST_M (EXTMEM_CORE1_DBUS_REJECT_ST_V << EXTMEM_CORE1_DBUS_REJECT_ST_S) -#define EXTMEM_CORE1_DBUS_REJECT_ST_V 0x00000001 -#define EXTMEM_CORE1_DBUS_REJECT_ST_S 4 - -/* EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST : RO; bitpos: [3]; default: 0; - * The bit is used to indicate interrupt by cpu access dcache while the - * core1_dbus is disabled or dcache is disabled which include speculative - * access. - */ - -#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST (BIT(3)) -#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_M (EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_V << EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_S) -#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_V 0x00000001 -#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_S 3 - -/* EXTMEM_CORE1_IBUS_REJECT_ST : RO; bitpos: [2]; default: 0; - * The bit is used to indicate interrupt by authentication fail. - */ - -#define EXTMEM_CORE1_IBUS_REJECT_ST (BIT(2)) -#define EXTMEM_CORE1_IBUS_REJECT_ST_M (EXTMEM_CORE1_IBUS_REJECT_ST_V << EXTMEM_CORE1_IBUS_REJECT_ST_S) -#define EXTMEM_CORE1_IBUS_REJECT_ST_V 0x00000001 -#define EXTMEM_CORE1_IBUS_REJECT_ST_S 2 - -/* EXTMEM_CORE1_IBUS_WR_ICACHE_ST : RO; bitpos: [1]; default: 0; - * The bit is used to indicate interrupt by ibus trying to write icache - */ - -#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST (BIT(1)) -#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_M (EXTMEM_CORE1_IBUS_WR_ICACHE_ST_V << EXTMEM_CORE1_IBUS_WR_ICACHE_ST_S) -#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_V 0x00000001 -#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_S 1 - -/* EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST : RO; bitpos: [0]; default: 0; - * The bit is used to indicate interrupt by cpu access icache while the - * core1_ibus is disabled or icache is disabled which include speculative - * access. - */ - -#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) -#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_M (EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_V << EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_S) -#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_V 0x00000001 -#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_S 0 - -/* EXTMEM_CORE0_DBUS_REJECT_ST_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE0_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x100) - -/* EXTMEM_CORE0_DBUS_WORLD : RO; bitpos: [6]; default: 0; - * The bit is used to indicate the world of CPU access dbus when - * authentication fail. 0: WORLD0, 1: WORLD1 - */ - -#define EXTMEM_CORE0_DBUS_WORLD (BIT(6)) -#define EXTMEM_CORE0_DBUS_WORLD_M (EXTMEM_CORE0_DBUS_WORLD_V << EXTMEM_CORE0_DBUS_WORLD_S) -#define EXTMEM_CORE0_DBUS_WORLD_V 0x00000001 -#define EXTMEM_CORE0_DBUS_WORLD_S 6 - -/* EXTMEM_CORE0_DBUS_ATTR : RO; bitpos: [5:3]; default: 0; - * The bits are used to indicate the attribute of CPU access dbus when - * authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: - * write-able. - */ - -#define EXTMEM_CORE0_DBUS_ATTR 0x00000007 -#define EXTMEM_CORE0_DBUS_ATTR_M (EXTMEM_CORE0_DBUS_ATTR_V << EXTMEM_CORE0_DBUS_ATTR_S) -#define EXTMEM_CORE0_DBUS_ATTR_V 0x00000007 -#define EXTMEM_CORE0_DBUS_ATTR_S 3 - -/* EXTMEM_CORE0_DBUS_TAG_ATTR : RO; bitpos: [2:0]; default: 0; - * The bits are used to indicate the attribute of data from external memory - * when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, - * 4: write-able. - */ - -#define EXTMEM_CORE0_DBUS_TAG_ATTR 0x00000007 -#define EXTMEM_CORE0_DBUS_TAG_ATTR_M (EXTMEM_CORE0_DBUS_TAG_ATTR_V << EXTMEM_CORE0_DBUS_TAG_ATTR_S) -#define EXTMEM_CORE0_DBUS_TAG_ATTR_V 0x00000007 -#define EXTMEM_CORE0_DBUS_TAG_ATTR_S 0 - -/* EXTMEM_CORE0_DBUS_REJECT_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x104) - -/* EXTMEM_CORE0_DBUS_VADDR : RO; bitpos: [31:0]; default: 4294967295; - * The bits are used to indicate the virtual address of CPU access dbus when - * authentication fail. - */ - -#define EXTMEM_CORE0_DBUS_VADDR 0xffffffff -#define EXTMEM_CORE0_DBUS_VADDR_M (EXTMEM_CORE0_DBUS_VADDR_V << EXTMEM_CORE0_DBUS_VADDR_S) -#define EXTMEM_CORE0_DBUS_VADDR_V 0xffffffff -#define EXTMEM_CORE0_DBUS_VADDR_S 0 - -/* EXTMEM_CORE0_IBUS_REJECT_ST_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE0_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x108) - -/* EXTMEM_CORE0_IBUS_WORLD : RO; bitpos: [6]; default: 0; - * The bit is used to indicate the world of CPU access ibus when - * authentication fail. 0: WORLD0, 1: WORLD1 - */ - -#define EXTMEM_CORE0_IBUS_WORLD (BIT(6)) -#define EXTMEM_CORE0_IBUS_WORLD_M (EXTMEM_CORE0_IBUS_WORLD_V << EXTMEM_CORE0_IBUS_WORLD_S) -#define EXTMEM_CORE0_IBUS_WORLD_V 0x00000001 -#define EXTMEM_CORE0_IBUS_WORLD_S 6 - -/* EXTMEM_CORE0_IBUS_ATTR : RO; bitpos: [5:3]; default: 0; - * The bits are used to indicate the attribute of CPU access ibus when - * authentication fail. 0: invalidate, 1: execute-able, 2: read-able - */ - -#define EXTMEM_CORE0_IBUS_ATTR 0x00000007 -#define EXTMEM_CORE0_IBUS_ATTR_M (EXTMEM_CORE0_IBUS_ATTR_V << EXTMEM_CORE0_IBUS_ATTR_S) -#define EXTMEM_CORE0_IBUS_ATTR_V 0x00000007 -#define EXTMEM_CORE0_IBUS_ATTR_S 3 - -/* EXTMEM_CORE0_IBUS_TAG_ATTR : RO; bitpos: [2:0]; default: 0; - * The bits are used to indicate the attribute of data from external memory - * when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, - * 4: write-able. - */ - -#define EXTMEM_CORE0_IBUS_TAG_ATTR 0x00000007 -#define EXTMEM_CORE0_IBUS_TAG_ATTR_M (EXTMEM_CORE0_IBUS_TAG_ATTR_V << EXTMEM_CORE0_IBUS_TAG_ATTR_S) -#define EXTMEM_CORE0_IBUS_TAG_ATTR_V 0x00000007 -#define EXTMEM_CORE0_IBUS_TAG_ATTR_S 0 - -/* EXTMEM_CORE0_IBUS_REJECT_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x10c) - -/* EXTMEM_CORE0_IBUS_VADDR : RO; bitpos: [31:0]; default: 4294967295; - * The bits are used to indicate the virtual address of CPU access ibus - * when authentication fail. - */ - -#define EXTMEM_CORE0_IBUS_VADDR 0xffffffff -#define EXTMEM_CORE0_IBUS_VADDR_M (EXTMEM_CORE0_IBUS_VADDR_V << EXTMEM_CORE0_IBUS_VADDR_S) -#define EXTMEM_CORE0_IBUS_VADDR_V 0xffffffff -#define EXTMEM_CORE0_IBUS_VADDR_S 0 - -/* EXTMEM_CORE1_DBUS_REJECT_ST_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE1_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x110) - -/* EXTMEM_CORE1_DBUS_WORLD : RO; bitpos: [6]; default: 0; - * The bit is used to indicate the world of CPU access dbus when - * authentication fail. 0: WORLD0, 1: WORLD1 - */ - -#define EXTMEM_CORE1_DBUS_WORLD (BIT(6)) -#define EXTMEM_CORE1_DBUS_WORLD_M (EXTMEM_CORE1_DBUS_WORLD_V << EXTMEM_CORE1_DBUS_WORLD_S) -#define EXTMEM_CORE1_DBUS_WORLD_V 0x00000001 -#define EXTMEM_CORE1_DBUS_WORLD_S 6 - -/* EXTMEM_CORE1_DBUS_ATTR : RO; bitpos: [5:3]; default: 0; - * The bits are used to indicate the attribute of CPU access dbus when - * authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: - * write-able. - */ - -#define EXTMEM_CORE1_DBUS_ATTR 0x00000007 -#define EXTMEM_CORE1_DBUS_ATTR_M (EXTMEM_CORE1_DBUS_ATTR_V << EXTMEM_CORE1_DBUS_ATTR_S) -#define EXTMEM_CORE1_DBUS_ATTR_V 0x00000007 -#define EXTMEM_CORE1_DBUS_ATTR_S 3 - -/* EXTMEM_CORE1_DBUS_TAG_ATTR : RO; bitpos: [2:0]; default: 0; - * The bits are used to indicate the attribute of data from external memory - * when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, - * 4: write-able. - */ - -#define EXTMEM_CORE1_DBUS_TAG_ATTR 0x00000007 -#define EXTMEM_CORE1_DBUS_TAG_ATTR_M (EXTMEM_CORE1_DBUS_TAG_ATTR_V << EXTMEM_CORE1_DBUS_TAG_ATTR_S) -#define EXTMEM_CORE1_DBUS_TAG_ATTR_V 0x00000007 -#define EXTMEM_CORE1_DBUS_TAG_ATTR_S 0 - -/* EXTMEM_CORE1_DBUS_REJECT_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE1_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x114) - -/* EXTMEM_CORE1_DBUS_VADDR : RO; bitpos: [31:0]; default: 4294967295; - * The bits are used to indicate the virtual address of CPU access dbus when - * authentication fail. - */ - -#define EXTMEM_CORE1_DBUS_VADDR 0xffffffff -#define EXTMEM_CORE1_DBUS_VADDR_M (EXTMEM_CORE1_DBUS_VADDR_V << EXTMEM_CORE1_DBUS_VADDR_S) -#define EXTMEM_CORE1_DBUS_VADDR_V 0xffffffff -#define EXTMEM_CORE1_DBUS_VADDR_S 0 - -/* EXTMEM_CORE1_IBUS_REJECT_ST_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE1_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x118) - -/* EXTMEM_CORE1_IBUS_WORLD : RO; bitpos: [6]; default: 0; - * The bit is used to indicate the world of CPU access ibus when - * authentication fail. 0: WORLD0, 1: WORLD1 - */ - -#define EXTMEM_CORE1_IBUS_WORLD (BIT(6)) -#define EXTMEM_CORE1_IBUS_WORLD_M (EXTMEM_CORE1_IBUS_WORLD_V << EXTMEM_CORE1_IBUS_WORLD_S) -#define EXTMEM_CORE1_IBUS_WORLD_V 0x00000001 -#define EXTMEM_CORE1_IBUS_WORLD_S 6 - -/* EXTMEM_CORE1_IBUS_ATTR : RO; bitpos: [5:3]; default: 0; - * The bits are used to indicate the attribute of CPU access ibus when - * authentication fail. 0: invalidate, 1: execute-able, 2: read-able - */ - -#define EXTMEM_CORE1_IBUS_ATTR 0x00000007 -#define EXTMEM_CORE1_IBUS_ATTR_M (EXTMEM_CORE1_IBUS_ATTR_V << EXTMEM_CORE1_IBUS_ATTR_S) -#define EXTMEM_CORE1_IBUS_ATTR_V 0x00000007 -#define EXTMEM_CORE1_IBUS_ATTR_S 3 - -/* EXTMEM_CORE1_IBUS_TAG_ATTR : RO; bitpos: [2:0]; default: 0; - * The bits are used to indicate the attribute of data from external memory - * when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, - * 4: write-able. - */ - -#define EXTMEM_CORE1_IBUS_TAG_ATTR 0x00000007 -#define EXTMEM_CORE1_IBUS_TAG_ATTR_M (EXTMEM_CORE1_IBUS_TAG_ATTR_V << EXTMEM_CORE1_IBUS_TAG_ATTR_S) -#define EXTMEM_CORE1_IBUS_TAG_ATTR_V 0x00000007 -#define EXTMEM_CORE1_IBUS_TAG_ATTR_S 0 - -/* EXTMEM_CORE1_IBUS_REJECT_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CORE1_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x11c) - -/* EXTMEM_CORE1_IBUS_VADDR : RO; bitpos: [31:0]; default: 4294967295; - * The bits are used to indicate the virtual address of CPU access ibus - * when authentication fail. - */ - -#define EXTMEM_CORE1_IBUS_VADDR 0xffffffff -#define EXTMEM_CORE1_IBUS_VADDR_M (EXTMEM_CORE1_IBUS_VADDR_V << EXTMEM_CORE1_IBUS_VADDR_S) -#define EXTMEM_CORE1_IBUS_VADDR_V 0xffffffff -#define EXTMEM_CORE1_IBUS_VADDR_S 0 - -/* EXTMEM_CACHE_MMU_FAULT_CONTENT_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x120) - -/* EXTMEM_CACHE_MMU_FAULT_CODE : RO; bitpos: [19:16]; default: 0; - * The right-most 3 bits are used to indicate the operations which cause mmu - * fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, - * 4: cpu miss evict recovery address, 5: load miss evict recovery address, - * 6: external dma tx, 7: external dma rx. The most significant bit is used - * to indicate this operation occurs in which one icache. - */ - -#define EXTMEM_CACHE_MMU_FAULT_CODE 0x0000000f -#define EXTMEM_CACHE_MMU_FAULT_CODE_M (EXTMEM_CACHE_MMU_FAULT_CODE_V << EXTMEM_CACHE_MMU_FAULT_CODE_S) -#define EXTMEM_CACHE_MMU_FAULT_CODE_V 0x0000000f -#define EXTMEM_CACHE_MMU_FAULT_CODE_S 16 - -/* EXTMEM_CACHE_MMU_FAULT_CONTENT : RO; bitpos: [15:0]; default: 0; - * The bits are used to indicate the content of mmu entry which cause mmu - * fault.. - */ - -#define EXTMEM_CACHE_MMU_FAULT_CONTENT 0x0000ffff -#define EXTMEM_CACHE_MMU_FAULT_CONTENT_M (EXTMEM_CACHE_MMU_FAULT_CONTENT_V << EXTMEM_CACHE_MMU_FAULT_CONTENT_S) -#define EXTMEM_CACHE_MMU_FAULT_CONTENT_V 0x0000ffff -#define EXTMEM_CACHE_MMU_FAULT_CONTENT_S 0 - -/* EXTMEM_CACHE_MMU_FAULT_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_MMU_FAULT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x124) - -/* EXTMEM_CACHE_MMU_FAULT_VADDR : RO; bitpos: [31:0]; default: 0; - * The bits are used to indicate the virtual address which cause mmu fault.. - */ - -#define EXTMEM_CACHE_MMU_FAULT_VADDR 0xffffffff -#define EXTMEM_CACHE_MMU_FAULT_VADDR_M (EXTMEM_CACHE_MMU_FAULT_VADDR_V << EXTMEM_CACHE_MMU_FAULT_VADDR_S) -#define EXTMEM_CACHE_MMU_FAULT_VADDR_V 0xffffffff -#define EXTMEM_CACHE_MMU_FAULT_VADDR_S 0 - -/* EXTMEM_CACHE_WRAP_AROUND_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x128) - -/* EXTMEM_CACHE_SRAM_RD_WRAP_AROUND : R/W; bitpos: [1]; default: 0; - * The bit is used to enable wrap around mode when read data from spiram. - */ - -#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND (BIT(1)) -#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_M (EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_V << EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_S) -#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_V 0x00000001 -#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_S 1 - -/* EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W; bitpos: [0]; default: 0; - * The bit is used to enable wrap around mode when read data from flash. - */ - -#define EXTMEM_CACHE_FLASH_WRAP_AROUND (BIT(0)) -#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M (EXTMEM_CACHE_FLASH_WRAP_AROUND_V << EXTMEM_CACHE_FLASH_WRAP_AROUND_S) -#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V 0x00000001 -#define EXTMEM_CACHE_FLASH_WRAP_AROUND_S 0 - -/* EXTMEM_CACHE_MMU_POWER_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x12c) - -/* EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; - * The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power - * up - */ - -#define EXTMEM_CACHE_MMU_MEM_FORCE_PU (BIT(2)) -#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M (EXTMEM_CACHE_MMU_MEM_FORCE_PU_V << EXTMEM_CACHE_MMU_MEM_FORCE_PU_S) -#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V 0x00000001 -#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S 2 - -/* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; - * The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power - * down - */ - -#define EXTMEM_CACHE_MMU_MEM_FORCE_PD (BIT(1)) -#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M (EXTMEM_CACHE_MMU_MEM_FORCE_PD_V << EXTMEM_CACHE_MMU_MEM_FORCE_PD_S) -#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V 0x00000001 -#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S 1 - -/* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1; - * The bit is used to enable clock gating to save power when access mmu - * memory, 0: enable, 1: disable - */ - -#define EXTMEM_CACHE_MMU_MEM_FORCE_ON (BIT(0)) -#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M (EXTMEM_CACHE_MMU_MEM_FORCE_ON_V << EXTMEM_CACHE_MMU_MEM_FORCE_ON_S) -#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V 0x00000001 -#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S 0 - -/* EXTMEM_CACHE_STATE_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_STATE_REG (DR_REG_EXTMEM_BASE + 0x130) - -/* EXTMEM_DCACHE_STATE : RO; bitpos: [23:12]; default: 0; - * The bit is used to indicate whether dcache main fsm is in idle state or - * not. 1: in idle state, 0: not in idle state - */ - -#define EXTMEM_DCACHE_STATE 0x00000fff -#define EXTMEM_DCACHE_STATE_M (EXTMEM_DCACHE_STATE_V << EXTMEM_DCACHE_STATE_S) -#define EXTMEM_DCACHE_STATE_V 0x00000fff -#define EXTMEM_DCACHE_STATE_S 12 - -/* EXTMEM_ICACHE_STATE : RO; bitpos: [11:0]; default: 0; - * The bit is used to indicate whether icache main fsm is in idle state or - * not. 1: in idle state, 0: not in idle state - */ - -#define EXTMEM_ICACHE_STATE 0x00000fff -#define EXTMEM_ICACHE_STATE_M (EXTMEM_ICACHE_STATE_V << EXTMEM_ICACHE_STATE_S) -#define EXTMEM_ICACHE_STATE_V 0x00000fff -#define EXTMEM_ICACHE_STATE_S 0 - -/* EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE + 0x134) - -/* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W; bitpos: [1]; default: 0; - * Reserved - */ - -#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT (BIT(1)) -#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M (EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V << EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S) -#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V 0x00000001 -#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S 1 - -/* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W; bitpos: [0]; default: 0; - * Reserved - */ - -#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0)) -#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V << EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S) -#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x00000001 -#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S 0 - -/* EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0x138) - -/* EXTMEM_CLK_FORCE_ON_CRYPT : R/W; bitpos: [2]; default: 1; - * The bit is used to close clock gating of external memory encrypt and - * decrypt clock. 1: close gating, 0: open clock gating. - */ - -#define EXTMEM_CLK_FORCE_ON_CRYPT (BIT(2)) -#define EXTMEM_CLK_FORCE_ON_CRYPT_M (EXTMEM_CLK_FORCE_ON_CRYPT_V << EXTMEM_CLK_FORCE_ON_CRYPT_S) -#define EXTMEM_CLK_FORCE_ON_CRYPT_V 0x00000001 -#define EXTMEM_CLK_FORCE_ON_CRYPT_S 2 - -/* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W; bitpos: [1]; default: 1; - * The bit is used to close clock gating of automatic crypt clock. 1: close - * gating, 0: open clock gating. - */ - -#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT (BIT(1)) -#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M (EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V << EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S) -#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V 0x00000001 -#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S 1 - -/* EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W; bitpos: [0]; default: 1; - * The bit is used to close clock gating of manual crypt clock. 1: close - * gating, 0: open clock gating. - */ - -#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT (BIT(0)) -#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M (EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V << EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S) -#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V 0x00000001 -#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S 0 - -/* EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x13c) - -/* EXTMEM_ALLOC_WB_HOLD_ARBITER : R/W; bitpos: [0]; default: 0; - * Reserved - */ - -#define EXTMEM_ALLOC_WB_HOLD_ARBITER (BIT(0)) -#define EXTMEM_ALLOC_WB_HOLD_ARBITER_M (EXTMEM_ALLOC_WB_HOLD_ARBITER_V << EXTMEM_ALLOC_WB_HOLD_ARBITER_S) -#define EXTMEM_ALLOC_WB_HOLD_ARBITER_V 0x00000001 -#define EXTMEM_ALLOC_WB_HOLD_ARBITER_S 0 - -/* EXTMEM_CACHE_PRELOAD_INT_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x140) - -/* EXTMEM_DCACHE_PRELOAD_INT_CLR : WOD; bitpos: [5]; default: 0; - * The bit is used to clear the interrupt by dcache pre-load done. - */ - -#define EXTMEM_DCACHE_PRELOAD_INT_CLR (BIT(5)) -#define EXTMEM_DCACHE_PRELOAD_INT_CLR_M (EXTMEM_DCACHE_PRELOAD_INT_CLR_V << EXTMEM_DCACHE_PRELOAD_INT_CLR_S) -#define EXTMEM_DCACHE_PRELOAD_INT_CLR_V 0x00000001 -#define EXTMEM_DCACHE_PRELOAD_INT_CLR_S 5 - -/* EXTMEM_DCACHE_PRELOAD_INT_ENA : R/W; bitpos: [4]; default: 0; - * The bit is used to enable the interrupt by dcache pre-load done. - */ - -#define EXTMEM_DCACHE_PRELOAD_INT_ENA (BIT(4)) -#define EXTMEM_DCACHE_PRELOAD_INT_ENA_M (EXTMEM_DCACHE_PRELOAD_INT_ENA_V << EXTMEM_DCACHE_PRELOAD_INT_ENA_S) -#define EXTMEM_DCACHE_PRELOAD_INT_ENA_V 0x00000001 -#define EXTMEM_DCACHE_PRELOAD_INT_ENA_S 4 - -/* EXTMEM_DCACHE_PRELOAD_INT_ST : RO; bitpos: [3]; default: 0; - * The bit is used to indicate the interrupt by dcache pre-load done. - */ - -#define EXTMEM_DCACHE_PRELOAD_INT_ST (BIT(3)) -#define EXTMEM_DCACHE_PRELOAD_INT_ST_M (EXTMEM_DCACHE_PRELOAD_INT_ST_V << EXTMEM_DCACHE_PRELOAD_INT_ST_S) -#define EXTMEM_DCACHE_PRELOAD_INT_ST_V 0x00000001 -#define EXTMEM_DCACHE_PRELOAD_INT_ST_S 3 - -/* EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD; bitpos: [2]; default: 0; - * The bit is used to clear the interrupt by icache pre-load done. - */ - -#define EXTMEM_ICACHE_PRELOAD_INT_CLR (BIT(2)) -#define EXTMEM_ICACHE_PRELOAD_INT_CLR_M (EXTMEM_ICACHE_PRELOAD_INT_CLR_V << EXTMEM_ICACHE_PRELOAD_INT_CLR_S) -#define EXTMEM_ICACHE_PRELOAD_INT_CLR_V 0x00000001 -#define EXTMEM_ICACHE_PRELOAD_INT_CLR_S 2 - -/* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W; bitpos: [1]; default: 0; - * The bit is used to enable the interrupt by icache pre-load done. - */ - -#define EXTMEM_ICACHE_PRELOAD_INT_ENA (BIT(1)) -#define EXTMEM_ICACHE_PRELOAD_INT_ENA_M (EXTMEM_ICACHE_PRELOAD_INT_ENA_V << EXTMEM_ICACHE_PRELOAD_INT_ENA_S) -#define EXTMEM_ICACHE_PRELOAD_INT_ENA_V 0x00000001 -#define EXTMEM_ICACHE_PRELOAD_INT_ENA_S 1 - -/* EXTMEM_ICACHE_PRELOAD_INT_ST : RO; bitpos: [0]; default: 0; - * The bit is used to indicate the interrupt by icache pre-load done. - */ - -#define EXTMEM_ICACHE_PRELOAD_INT_ST (BIT(0)) -#define EXTMEM_ICACHE_PRELOAD_INT_ST_M (EXTMEM_ICACHE_PRELOAD_INT_ST_V << EXTMEM_ICACHE_PRELOAD_INT_ST_S) -#define EXTMEM_ICACHE_PRELOAD_INT_ST_V 0x00000001 -#define EXTMEM_ICACHE_PRELOAD_INT_ST_S 0 - -/* EXTMEM_CACHE_SYNC_INT_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_SYNC_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x144) - -/* EXTMEM_DCACHE_SYNC_INT_CLR : WOD; bitpos: [5]; default: 0; - * The bit is used to clear the interrupt by dcache sync done. - */ - -#define EXTMEM_DCACHE_SYNC_INT_CLR (BIT(5)) -#define EXTMEM_DCACHE_SYNC_INT_CLR_M (EXTMEM_DCACHE_SYNC_INT_CLR_V << EXTMEM_DCACHE_SYNC_INT_CLR_S) -#define EXTMEM_DCACHE_SYNC_INT_CLR_V 0x00000001 -#define EXTMEM_DCACHE_SYNC_INT_CLR_S 5 - -/* EXTMEM_DCACHE_SYNC_INT_ENA : R/W; bitpos: [4]; default: 0; - * The bit is used to enable the interrupt by dcache sync done. - */ - -#define EXTMEM_DCACHE_SYNC_INT_ENA (BIT(4)) -#define EXTMEM_DCACHE_SYNC_INT_ENA_M (EXTMEM_DCACHE_SYNC_INT_ENA_V << EXTMEM_DCACHE_SYNC_INT_ENA_S) -#define EXTMEM_DCACHE_SYNC_INT_ENA_V 0x00000001 -#define EXTMEM_DCACHE_SYNC_INT_ENA_S 4 - -/* EXTMEM_DCACHE_SYNC_INT_ST : RO; bitpos: [3]; default: 0; - * The bit is used to indicate the interrupt by dcache sync done. - */ - -#define EXTMEM_DCACHE_SYNC_INT_ST (BIT(3)) -#define EXTMEM_DCACHE_SYNC_INT_ST_M (EXTMEM_DCACHE_SYNC_INT_ST_V << EXTMEM_DCACHE_SYNC_INT_ST_S) -#define EXTMEM_DCACHE_SYNC_INT_ST_V 0x00000001 -#define EXTMEM_DCACHE_SYNC_INT_ST_S 3 - -/* EXTMEM_ICACHE_SYNC_INT_CLR : WOD; bitpos: [2]; default: 0; - * The bit is used to clear the interrupt by icache sync done. - */ - -#define EXTMEM_ICACHE_SYNC_INT_CLR (BIT(2)) -#define EXTMEM_ICACHE_SYNC_INT_CLR_M (EXTMEM_ICACHE_SYNC_INT_CLR_V << EXTMEM_ICACHE_SYNC_INT_CLR_S) -#define EXTMEM_ICACHE_SYNC_INT_CLR_V 0x00000001 -#define EXTMEM_ICACHE_SYNC_INT_CLR_S 2 - -/* EXTMEM_ICACHE_SYNC_INT_ENA : R/W; bitpos: [1]; default: 0; - * The bit is used to enable the interrupt by icache sync done. - */ - -#define EXTMEM_ICACHE_SYNC_INT_ENA (BIT(1)) -#define EXTMEM_ICACHE_SYNC_INT_ENA_M (EXTMEM_ICACHE_SYNC_INT_ENA_V << EXTMEM_ICACHE_SYNC_INT_ENA_S) -#define EXTMEM_ICACHE_SYNC_INT_ENA_V 0x00000001 -#define EXTMEM_ICACHE_SYNC_INT_ENA_S 1 - -/* EXTMEM_ICACHE_SYNC_INT_ST : RO; bitpos: [0]; default: 0; - * The bit is used to indicate the interrupt by icache sync done. - */ - -#define EXTMEM_ICACHE_SYNC_INT_ST (BIT(0)) -#define EXTMEM_ICACHE_SYNC_INT_ST_M (EXTMEM_ICACHE_SYNC_INT_ST_V << EXTMEM_ICACHE_SYNC_INT_ST_S) -#define EXTMEM_ICACHE_SYNC_INT_ST_V 0x00000001 -#define EXTMEM_ICACHE_SYNC_INT_ST_S 0 - -/* EXTMEM_CACHE_MMU_OWNER_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_MMU_OWNER_REG (DR_REG_EXTMEM_BASE + 0x148) - -/* EXTMEM_CACHE_MMU_OWNER : R/W; bitpos: [23:0]; default: 0; - * The bits are used to specify the owner of MMU.bit0: icache, bit1: dcache, - * bit2: dma, bit3: reserved. - */ - -#define EXTMEM_CACHE_MMU_OWNER 0x00ffffff -#define EXTMEM_CACHE_MMU_OWNER_M (EXTMEM_CACHE_MMU_OWNER_V << EXTMEM_CACHE_MMU_OWNER_S) -#define EXTMEM_CACHE_MMU_OWNER_V 0x00ffffff -#define EXTMEM_CACHE_MMU_OWNER_S 0 - -/* EXTMEM_CACHE_CONF_MISC_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_CONF_MISC_REG (DR_REG_EXTMEM_BASE + 0x14c) - -/* EXTMEM_CACHE_TRACE_ENA : R/W; bitpos: [2]; default: 1; - * The bit is used to enable cache trace function. - */ - -#define EXTMEM_CACHE_TRACE_ENA (BIT(2)) -#define EXTMEM_CACHE_TRACE_ENA_M (EXTMEM_CACHE_TRACE_ENA_V << EXTMEM_CACHE_TRACE_ENA_S) -#define EXTMEM_CACHE_TRACE_ENA_V 0x00000001 -#define EXTMEM_CACHE_TRACE_ENA_S 2 - -/* EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W; bitpos: [1]; default: 1; - * The bit is used to disable checking mmu entry fault by sync operation. - */ - -#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1)) -#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M (EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V << EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S) -#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V 0x00000001 -#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S 1 - -/* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W; bitpos: [0]; default: - * 1; - * The bit is used to disable checking mmu entry fault by preload operation. - */ - -#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0)) -#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V << EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S) -#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x00000001 -#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S 0 - -/* EXTMEM_DCACHE_FREEZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0x150) - -/* EXTMEM_DCACHE_FREEZE_DONE : RO; bitpos: [2]; default: 1; - * The bit is used to indicate dcache freeze success - */ - -#define EXTMEM_DCACHE_FREEZE_DONE (BIT(2)) -#define EXTMEM_DCACHE_FREEZE_DONE_M (EXTMEM_DCACHE_FREEZE_DONE_V << EXTMEM_DCACHE_FREEZE_DONE_S) -#define EXTMEM_DCACHE_FREEZE_DONE_V 0x00000001 -#define EXTMEM_DCACHE_FREEZE_DONE_S 2 - -/* EXTMEM_DCACHE_FREEZE_MODE : R/W; bitpos: [1]; default: 0; - * The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: - * assert hit if CPU miss - */ - -#define EXTMEM_DCACHE_FREEZE_MODE (BIT(1)) -#define EXTMEM_DCACHE_FREEZE_MODE_M (EXTMEM_DCACHE_FREEZE_MODE_V << EXTMEM_DCACHE_FREEZE_MODE_S) -#define EXTMEM_DCACHE_FREEZE_MODE_V 0x00000001 -#define EXTMEM_DCACHE_FREEZE_MODE_S 1 - -/* EXTMEM_DCACHE_FREEZE_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable dcache freeze mode - */ - -#define EXTMEM_DCACHE_FREEZE_ENA (BIT(0)) -#define EXTMEM_DCACHE_FREEZE_ENA_M (EXTMEM_DCACHE_FREEZE_ENA_V << EXTMEM_DCACHE_FREEZE_ENA_S) -#define EXTMEM_DCACHE_FREEZE_ENA_V 0x00000001 -#define EXTMEM_DCACHE_FREEZE_ENA_S 0 - -/* EXTMEM_ICACHE_FREEZE_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0x154) - -/* EXTMEM_ICACHE_FREEZE_DONE : RO; bitpos: [2]; default: 1; - * The bit is used to indicate icache freeze success - */ - -#define EXTMEM_ICACHE_FREEZE_DONE (BIT(2)) -#define EXTMEM_ICACHE_FREEZE_DONE_M (EXTMEM_ICACHE_FREEZE_DONE_V << EXTMEM_ICACHE_FREEZE_DONE_S) -#define EXTMEM_ICACHE_FREEZE_DONE_V 0x00000001 -#define EXTMEM_ICACHE_FREEZE_DONE_S 2 - -/* EXTMEM_ICACHE_FREEZE_MODE : R/W; bitpos: [1]; default: 0; - * The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: - * assert hit if CPU miss - */ - -#define EXTMEM_ICACHE_FREEZE_MODE (BIT(1)) -#define EXTMEM_ICACHE_FREEZE_MODE_M (EXTMEM_ICACHE_FREEZE_MODE_V << EXTMEM_ICACHE_FREEZE_MODE_S) -#define EXTMEM_ICACHE_FREEZE_MODE_V 0x00000001 -#define EXTMEM_ICACHE_FREEZE_MODE_S 1 - -/* EXTMEM_ICACHE_FREEZE_ENA : R/W; bitpos: [0]; default: 0; - * The bit is used to enable icache freeze mode - */ - -#define EXTMEM_ICACHE_FREEZE_ENA (BIT(0)) -#define EXTMEM_ICACHE_FREEZE_ENA_M (EXTMEM_ICACHE_FREEZE_ENA_V << EXTMEM_ICACHE_FREEZE_ENA_S) -#define EXTMEM_ICACHE_FREEZE_ENA_V 0x00000001 -#define EXTMEM_ICACHE_FREEZE_ENA_S 0 - -/* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG register - * ******* Description *********** - */ - -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0x158) - -/* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W; bitpos: [0]; default: 1; - * The bit is used to activate icache atomic operation protection. In this - * case, sync/lock operation can not interrupt miss-work. This feature does - * not work during invalidateAll operation. - */ - -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA (BIT(0)) -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M (EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V << EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S) -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V 0x00000001 -#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S 0 - -/* EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_REG register - * ******* Description *********** - */ - -#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0x15c) - -/* EXTMEM_DCACHE_ATOMIC_OPERATE_ENA : R/W; bitpos: [0]; default: 1; - * The bit is used to activate dcache atomic operation protection. In this - * case, sync/lock/occupy operation can not interrupt miss-work. This - * feature does not work during invalidateAll operation. - */ - -#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA (BIT(0)) -#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_M (EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_V << EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_S) -#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_V 0x00000001 -#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_S 0 - -/* EXTMEM_CACHE_REQUEST_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_REQUEST_REG (DR_REG_EXTMEM_BASE + 0x160) - -/* EXTMEM_CACHE_REQUEST_BYPASS : R/W; bitpos: [0]; default: 0; - * The bit is used to disable request recording which could cause - * performance issue - */ - -#define EXTMEM_CACHE_REQUEST_BYPASS (BIT(0)) -#define EXTMEM_CACHE_REQUEST_BYPASS_M (EXTMEM_CACHE_REQUEST_BYPASS_V << EXTMEM_CACHE_REQUEST_BYPASS_S) -#define EXTMEM_CACHE_REQUEST_BYPASS_V 0x00000001 -#define EXTMEM_CACHE_REQUEST_BYPASS_S 0 - -/* EXTMEM_CLOCK_GATE_REG register - * ******* Description *********** - */ - -#define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE + 0x164) - -/* EXTMEM_CLK_EN : R/W; bitpos: [0]; default: 1; - * Reserved - */ - -#define EXTMEM_CLK_EN (BIT(0)) -#define EXTMEM_CLK_EN_M (EXTMEM_CLK_EN_V << EXTMEM_CLK_EN_S) -#define EXTMEM_CLK_EN_V 0x00000001 -#define EXTMEM_CLK_EN_S 0 - -/* EXTMEM_CACHE_TAG_OBJECT_CTRL_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_TAG_OBJECT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x180) - -/* EXTMEM_DCACHE_TAG_OBJECT : R/W; bitpos: [1]; default: 0; - * Set this bit to set dcache tag memory as object. This bit should be - * onehot with the others fields inside this register. - */ - -#define EXTMEM_DCACHE_TAG_OBJECT (BIT(1)) -#define EXTMEM_DCACHE_TAG_OBJECT_M (EXTMEM_DCACHE_TAG_OBJECT_V << EXTMEM_DCACHE_TAG_OBJECT_S) -#define EXTMEM_DCACHE_TAG_OBJECT_V 0x00000001 -#define EXTMEM_DCACHE_TAG_OBJECT_S 1 - -/* EXTMEM_ICACHE_TAG_OBJECT : R/W; bitpos: [0]; default: 0; - * Set this bit to set icache tag memory as object. This bit should be - * onehot with the others fields inside this register. - */ - -#define EXTMEM_ICACHE_TAG_OBJECT (BIT(0)) -#define EXTMEM_ICACHE_TAG_OBJECT_M (EXTMEM_ICACHE_TAG_OBJECT_V << EXTMEM_ICACHE_TAG_OBJECT_S) -#define EXTMEM_ICACHE_TAG_OBJECT_V 0x00000001 -#define EXTMEM_ICACHE_TAG_OBJECT_S 0 - -/* EXTMEM_CACHE_TAG_WAY_OBJECT_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_TAG_WAY_OBJECT_REG (DR_REG_EXTMEM_BASE + 0x184) - -/* EXTMEM_CACHE_TAG_WAY_OBJECT : R/W; bitpos: [2:0]; default: 0; - * Set this bits to select which way of the tag-object will be accessed. 0: - * way0, 1: way1, 2: way2, 3: way3, .., 7: way7. - */ - -#define EXTMEM_CACHE_TAG_WAY_OBJECT 0x00000007 -#define EXTMEM_CACHE_TAG_WAY_OBJECT_M (EXTMEM_CACHE_TAG_WAY_OBJECT_V << EXTMEM_CACHE_TAG_WAY_OBJECT_S) -#define EXTMEM_CACHE_TAG_WAY_OBJECT_V 0x00000007 -#define EXTMEM_CACHE_TAG_WAY_OBJECT_S 0 - -/* EXTMEM_CACHE_VADDR_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_VADDR_REG (DR_REG_EXTMEM_BASE + 0x188) - -/* EXTMEM_CACHE_VADDR : R/W; bitpos: [31:0]; default: 0; - * Those bits stores the virtual address which will decide where inside the - * specified tag memory object will be accessed. - */ - -#define EXTMEM_CACHE_VADDR 0xffffffff -#define EXTMEM_CACHE_VADDR_M (EXTMEM_CACHE_VADDR_V << EXTMEM_CACHE_VADDR_S) -#define EXTMEM_CACHE_VADDR_V 0xffffffff -#define EXTMEM_CACHE_VADDR_S 0 - -/* EXTMEM_CACHE_TAG_CONTENT_REG register - * ******* Description *********** - */ - -#define EXTMEM_CACHE_TAG_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x18c) - -/* EXTMEM_CACHE_TAG_CONTENT : R/W; bitpos: [31:0]; default: 0; - * This is a constant place where we can write data to or read data from the - * tag memory on the specified cache. - */ - -#define EXTMEM_CACHE_TAG_CONTENT 0xffffffff -#define EXTMEM_CACHE_TAG_CONTENT_M (EXTMEM_CACHE_TAG_CONTENT_V << EXTMEM_CACHE_TAG_CONTENT_S) -#define EXTMEM_CACHE_TAG_CONTENT_V 0xffffffff -#define EXTMEM_CACHE_TAG_CONTENT_S 0 - -/* EXTMEM_DATE_REG register - * ******* Description *********** - */ - -#define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3fc) - -/* EXTMEM_DATE : R/W; bitpos: [27:0]; default: 33628944; - * version information. - */ - -#define EXTMEM_DATE 0x0fffffff -#define EXTMEM_DATE_M (EXTMEM_DATE_V << EXTMEM_DATE_S) -#define EXTMEM_DATE_V 0x0fffffff -#define EXTMEM_DATE_S 0 - -#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_EXTMEM_H */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h index df327581af21a..3a8ab206f0c1a 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h @@ -5893,4 +5893,15 @@ #define RTC_SLEEP_PD_XTAL BIT(11) +/* These flags are not power domains, but will affect some sleep parameters */ + +#define RTC_SLEEP_DIG_USE_8M BIT(16) +#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17) + +/* Avoid using ultra low power in deep sleep, in which RTCIO cannot + * be used as input, and RTCMEM can't work under high temperature + */ + +#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) + #endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_RTCCNTL_H */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h index f6337da0eca8c..9448a752c5022 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h @@ -30,268 +30,25 @@ #include #endif -#include "xtensa_attr.h" #include +#include "soc/soc.h" +#include "esp_attr.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Register Bits */ - -#define BIT31 0x80000000 -#define BIT30 0x40000000 -#define BIT29 0x20000000 -#define BIT28 0x10000000 -#define BIT27 0x08000000 -#define BIT26 0x04000000 -#define BIT25 0x02000000 -#define BIT24 0x01000000 -#define BIT23 0x00800000 -#define BIT22 0x00400000 -#define BIT21 0x00200000 -#define BIT20 0x00100000 -#define BIT19 0x00080000 -#define BIT18 0x00040000 -#define BIT17 0x00020000 -#define BIT16 0x00010000 -#define BIT15 0x00008000 -#define BIT14 0x00004000 -#define BIT13 0x00002000 -#define BIT12 0x00001000 -#define BIT11 0x00000800 -#define BIT10 0x00000400 -#define BIT9 0x00000200 -#define BIT8 0x00000100 -#define BIT7 0x00000080 -#define BIT6 0x00000040 -#define BIT5 0x00000020 -#define BIT4 0x00000010 -#define BIT3 0x00000008 -#define BIT2 0x00000004 -#define BIT1 0x00000002 -#define BIT0 0x00000001 - -#define PRO_CPU_NUM (0) -#define APP_CPU_NUM (1) - -#define PRO_CPUID (0xcdcd) -#define APP_CPUID (0xabab) - -/* Largest span of contiguous memory (DRAM or IRAM) in the address space */ - -#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) - -#define DR_REG_UART_BASE 0x60000000 -#define DR_REG_SPI1_BASE 0x60002000 -#define DR_REG_SPI0_BASE 0x60003000 -#define DR_REG_GPIO_BASE 0x60004000 -#define DR_REG_GPIO_SD_BASE 0x60004f00 - -#define DR_REG_FE2_BASE 0x60005000 -#define DR_REG_FE_BASE 0x60006000 - -#define DR_REG_EFUSE_BASE 0x60007000 -#define DR_REG_RTCCNTL_BASE 0x60008000 -#define DR_REG_RTCIO_BASE 0x60008400 -#define DR_REG_SENS_BASE 0x60008800 -#define DR_REG_RTC_I2C_BASE 0x60008C00 -#define DR_REG_IO_MUX_BASE 0x60009000 - -#define DR_REG_HINF_BASE 0x6000B000 -#define DR_REG_UHCI1_BASE 0x6000C000 - -#define DR_REG_I2S_BASE 0x6000F000 -#define DR_REG_UART1_BASE 0x60010000 - -#define DR_REG_BT_BASE 0x60011000 - -#define DR_REG_I2C_EXT_BASE 0x60013000 -#define DR_REG_UHCI0_BASE 0x60014000 - -#define DR_REG_SLCHOST_BASE 0x60015000 - -#define DR_REG_RMT_BASE 0x60016000 -#define DR_REG_PCNT_BASE 0x60017000 - -#define DR_REG_SLC_BASE 0x60018000 - -#define DR_REG_LEDC_BASE 0x60019000 - -#define DR_REG_NRX_BASE 0x6001CC00 -#define DR_REG_BB_BASE 0x6001D000 - -#define DR_REG_PWM0_BASE 0x6001E000 -#define DR_REG_TIMERGROUP0_BASE 0x6001F000 -#define DR_REG_TIMERGROUP1_BASE 0x60020000 -#define DR_REG_RTC_SLOWMEM_BASE 0x60021000 -#define DR_REG_SYSTIMER_BASE 0x60023000 -#define DR_REG_SPI2_BASE 0x60024000 -#define DR_REG_SPI3_BASE 0x60025000 -#define DR_REG_SYSCON_BASE 0x60026000 -#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ -#define DR_REG_I2C1_EXT_BASE 0x60027000 -#define DR_REG_SDMMC_BASE 0x60028000 - #define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (((i) > 3) ? ((((i) - 2) * 0x1000) + 0x10000) : (((i) - 2) * 0x1000))) -#define DR_REG_PERI_BACKUP_BASE 0x6002A000 - -#define DR_REG_TWAI_BASE 0x6002B000 -#define DR_REG_PWM1_BASE 0x6002C000 -#define DR_REG_I2S1_BASE 0x6002D000 -#define DR_REG_UART2_BASE 0x6002E000 - -#define DR_REG_USB_DEVICE_BASE 0x60038000 -#define DR_REG_USB_WRAP_BASE 0x60039000 -#define DR_REG_AES_BASE 0x6003A000 -#define DR_REG_SHA_BASE 0x6003B000 -#define DR_REG_RSA_BASE 0x6003C000 -#define DR_REG_HMAC_BASE 0x6003E000 -#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003D000 -#define DR_REG_GDMA_BASE 0x6003F000 -#define DR_REG_APB_SARADC_BASE 0x60040000 -#define DR_REG_LCD_CAM_BASE 0x60041000 - #define DR_REG_USB_BASE 0x60080000 -#define DR_REG_SYSTEM_BASE 0x600C0000 -#define DR_REG_SENSITIVE_BASE 0x600C1000 -#define DR_REG_INTERRUPT_BASE 0x600C2000 - -/* Cache configuration */ - -#define DR_REG_EXTMEM_BASE 0x600C4000 -#define DR_REG_MMU_TABLE 0x600C5000 -#define DR_REG_ITAG_TABLE 0x600C6000 -#define DR_REG_DTAG_TABLE 0x600C8000 - -#define DR_REG_EXT_MEM_ENC 0x600CC000 - #define DR_REG_ASSIST_DEBUG_BASE 0x600CE000 #define DR_REG_WORLD_CNTL_BASE 0x600D0000 #define DR_REG_DPORT_END 0x600D3FFC -#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) -#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ((i) > 1 ? 0xe000 : 0)) -#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ((i) > 1 ? 0xe000 : 0 )) -#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) -#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) -#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) -#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) -#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000) - -/* Registers Operation */ - -#define ETS_UNCACHED_ADDR(addr) (addr) -#define ETS_CACHED_ADDR(addr) (addr) - #ifndef __ASSEMBLY__ -/* Write value to register */ - -#define REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) - -/* Read value from register */ - -#define REG_READ(_r) (*(volatile uint32_t *)(_r)) - -/* Get bit or get bits from register */ - -#define REG_GET_BIT(_r, _b) (*(volatile uint32_t *)(_r) & (_b)) - -/* Set bit or set bits to register */ - -#define REG_SET_BIT(_r, _b) (*(volatile uint32_t *)(_r) |= (_b)) - -/* Clear bit or clear bits of register */ - -#define REG_CLR_BIT(_r, _b) (*(volatile uint32_t *)(_r) &= ~(_b)) - -/* Set bits of register controlled by mask */ - -#define REG_SET_BITS(_r, _b, _m) (*(volatile uint32_t *)(_r) = (*(volatile uint32_t *)(_r) & ~(_m)) | ((_b) & (_m))) - -/* Get field from register, - * used when _f is not left shifted by _f##_S - */ - -#define REG_GET_FIELD(addr, field) ((getreg32(addr) >> (field##_S)) & (field##_V)) - -/* Set field to register, - * used when _f is not left shifted by _f##_S - */ - -#define REG_SET_FIELD(addr, field, val) (modifyreg32((addr), (field##_M), (((uint32_t) val) & (field##_V)) << (field##_S))) - -/* Get field value from a variable, - * used when _f is not left shifted by _f##_S - */ - -#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) - -/* Get field value from a variable, - * used when _f is left shifted by _f##_S - */ - -#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) - -/* Set field value to a variable, - * used when _f is not left shifted by _f##_S - */ - -#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) - -/* Set field value to a variable, - * used when _f is left shifted by _f##_S - */ - -#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) - -/* Generate a value from a field value, - * used when _f is not left shifted by _f##_S - */ - -#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) - -/* Generate a value from a field value, - * used when _f is left shifted by _f##_S - */ - -#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) - -/* Read value from register */ - -#define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) - -/* Write value to register */ - -#define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val) - -/* Clear bits of register controlled by mask */ - -#define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))) - -/* Set bits of register controlled by mask */ - -#define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))) - -/* Get bits of register controlled by mask */ - -#define GET_PERI_REG_MASK(reg, mask) (READ_PERI_REG(reg) & (mask)) - -/* Get bits of register controlled by highest bit and lowest bit */ - -#define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) - -/* Set bits of register controlled by mask and shift */ - -#define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )) - -/* Get field of register */ - -#define GET_PERI_REG_BITS2(reg, mask,shift) ((READ_PERI_REG(reg)>>(shift))&(mask)) - /* Extract the field from the register and shift it to avoid wrong reading */ #define REG_MASK(_reg, _field) ((_reg & (_field##_M)) >> (_field##_S)) @@ -304,129 +61,7 @@ /* Peripheral Clock */ -#define APB_CLK_FREQ_ROM (40*1000000) -#define CPU_CLK_FREQ_ROM (40*1000000) -#define UART_CLK_FREQ_ROM (40*1000000) -#define EFUSE_CLK_FREQ_ROM (20*1000000) -#define CPU_CLK_FREQ APB_CLK_FREQ -#define APB_CLK_FREQ (80*1000000) -#define REF_CLK_FREQ (1000000) #define RTC_CLK_FREQ (20*1000000) -#define XTAL_CLK_FREQ (40*1000000) -#define UART_CLK_FREQ APB_CLK_FREQ -#define WDT_CLK_FREQ APB_CLK_FREQ -#define TIMER_CLK_FREQ (80000000>>4) -#define SPI_CLK_DIV 4 -#define TICKS_PER_US_ROM 40 -#define GPIO_MATRIX_DELAY_NS 0 - -/* Overall memory map */ - -#define SOC_DROM_LOW 0x3C000000 -#define SOC_DROM_HIGH 0x3D000000 -#define SOC_IROM_LOW 0x42000000 -#define SOC_IROM_HIGH 0x44000000 -#define SOC_IRAM_LOW 0x40370000 -#define SOC_IRAM_HIGH 0x403E0000 -#define SOC_DRAM_LOW 0x3FC88000 -#define SOC_DRAM_HIGH 0x3FD00000 - -#define SOC_RTC_IRAM_LOW 0x600FE000 -#define SOC_RTC_IRAM_HIGH 0x60100000 -#define SOC_RTC_DRAM_LOW 0x600FE000 -#define SOC_RTC_DRAM_HIGH 0x60100000 - -#define SOC_RTC_DATA_LOW 0x50000000 -#define SOC_RTC_DATA_HIGH 0x50002000 - -#define SOC_EXTRAM_DATA_LOW 0x3C000000 -#define SOC_EXTRAM_DATA_HIGH 0x3E000000 -#define SOC_IROM_MASK_LOW 0x40000000 -#define SOC_IROM_MASK_HIGH 0x4001A100 - -#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) - -/* First and last words of the D/IRAM region, for both the DRAM address - * as well as the IRAM alias. - */ - -#define SOC_DIRAM_IRAM_LOW 0x40378000 -#define SOC_DIRAM_IRAM_HIGH 0x403E0000 -#define SOC_DIRAM_DRAM_LOW 0x3FC88000 -#define SOC_DIRAM_DRAM_HIGH 0x3FCF0000 - -/* Region of memory accessible via DMA in internal memory. - * See esp_ptr_dma_capable(). - */ - -#define SOC_DMA_LOW 0x3FC88000 -#define SOC_DMA_HIGH 0x3FD00000 - -/* Region of memory accessible via DMA in external memory. - * See esp_ptr_dma_ext_capable(). - */ - -#define SOC_DMA_EXT_LOW SOC_EXTRAM_DATA_LOW -#define SOC_DMA_EXT_HIGH SOC_EXTRAM_DATA_HIGH - -/* Region of memory that is byte-accessible. - * See esp_ptr_byte_accessible(). - */ - -#define SOC_BYTE_ACCESSIBLE_LOW 0x3FC88000 -#define SOC_BYTE_ACCESSIBLE_HIGH 0x3FD00000 - -/* Region of memory that is internal, as in on the same silicon die as the - * ESP32 CPUs (excluding RTC data region, that's checked separately.) - * See esp_ptr_internal(). - */ - -#define SOC_MEM_INTERNAL_LOW 0x3FC88000 -#define SOC_MEM_INTERNAL_HIGH 0x403E2000 - -/* Start (highest address) of ROM boot stack, only relevant during - * early boot - */ - -#define SOC_ROM_STACK_START 0x3fcebf10 - -/* Interrupt cpu using table, Please see the core-isa.h */ - -/**************************************************************************** - * Intr num Level Type PRO CPU usage APP CPU usage - * 0 1 extern level WMAC Reserved - * 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA - * 2 1 extern level - * 3 1 extern level - * 4 1 extern level WBB - * 5 1 extern level BT/BLE Controller BT/BLE Controller - * 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1) - * 7 1 software BT/BLE VHCI BT/BLE VHCI - * 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX) - * 9 1 extern level - * 10 1 extern edge - * 11 3 profiling - * 12 1 extern level - * 13 1 extern level - * 14 7 nmi Reserved Reserved - * 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3) - * 16 5 timer - * 17 1 extern level - * 18 1 extern level - * 19 2 extern level - * 20 2 extern level - * 21 2 extern level - * 22 3 extern edge - * 23 3 extern level - * 24 4 extern level TG1_WDT - * 25 4 extern level CACHEERR - * 26 5 extern level - * 27 3 extern level Reserved Reserved - * 28 4 extern edge DPORT ACCESS DPORT ACCESS - * 29 3 software Reserved Reserved - * 30 4 extern edge Reserved Reserved - * 31 5 extern level - ****************************************************************************/ /* Core voltage needs to be increased in two cases: * 1. running at 240 MHz @@ -442,37 +77,6 @@ #define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 #define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 -/* CPU0 Interrupt number reserved, not touch this. */ - -#define ETS_WMAC_INUM 0 -#define ETS_BT_HOST_INUM 1 -#define ETS_WBB_INUM 4 -#define ETS_TG0_T1_INUM 10 /* use edge interrupt*/ -#define ETS_FRC1_INUM 22 -#define ETS_T1_WDT_INUM 24 -#define ETS_CACHEERR_INUM 25 -#define ETS_DPORT_INUM 28 - -/* CPU0 Interrupt number used in ROM, should be cancelled in SDK */ - -#define ETS_SLC_INUM 1 -#define ETS_UART0_INUM 5 -#define ETS_UART1_INUM 5 -#define ETS_SPI2_INUM 1 - -/* CPU0 Interrupt number used in ROM code only when module init function - * called, should pay attention here. - */ - -#define ETS_FRC_TIMER2_INUM 10 /* use edge*/ -#define ETS_GPIO_INUM 4 - -/* Other interrupt number should be managed by the user */ - -/* Invalid interrupt for number interrupt matrix */ - -#define ETS_INVALID_INUM 6 - #define MHZ (1000000) #define RTC_PLL_FREQ_320M 320 #define RTC_PLL_FREQ_480M 480 diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_spi_mem_reg.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_spi_mem_reg.h deleted file mode 100644 index bb80bde437015..0000000000000 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_spi_mem_reg.h +++ /dev/null @@ -1,3586 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/hardware/esp32s3_spi_mem_reg.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SPI_MEM_REG_H -#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SPI_MEM_REG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32s3_soc.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x0) - -/* SPI_MEM_FLASH_READ : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ - -/* Description: Read flash enable. Read flash operation will be triggered - * when the bit is set. The bit will be cleared once the operation done. - * 1: enable 0: disable. - */ - -#define SPI_MEM_FLASH_READ (BIT(31)) -#define SPI_MEM_FLASH_READ_M (BIT(31)) -#define SPI_MEM_FLASH_READ_V 0x1 -#define SPI_MEM_FLASH_READ_S 31 - -/* SPI_MEM_FLASH_WREN : R/W/SC ;bitpos:[30] ;default: 1'b0 ; */ - -/* Description: Write flash enable. Write enable command will be sent when - * the bit is set. The bit will be cleared once the operation done. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_FLASH_WREN (BIT(30)) -#define SPI_MEM_FLASH_WREN_M (BIT(30)) -#define SPI_MEM_FLASH_WREN_V 0x1 -#define SPI_MEM_FLASH_WREN_S 30 - -/* SPI_MEM_FLASH_WRDI : R/W/SC ;bitpos:[29] ;default: 1'b0 ; */ - -/* Description: Write flash disable. Write disable command will be sent when - * the bit is set. The bit will be cleared once the operation done. 1: enable - * 0: disable. - */ - -#define SPI_MEM_FLASH_WRDI (BIT(29)) -#define SPI_MEM_FLASH_WRDI_M (BIT(29)) -#define SPI_MEM_FLASH_WRDI_V 0x1 -#define SPI_MEM_FLASH_WRDI_S 29 - -/* SPI_MEM_FLASH_RDID : R/W/SC ;bitpos:[28] ;default: 1'b0 ; */ - -/* Description: Read JEDEC ID . Read ID command will be sent when the bit is - * set. The bit will be cleared once the operation done. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_FLASH_RDID (BIT(28)) -#define SPI_MEM_FLASH_RDID_M (BIT(28)) -#define SPI_MEM_FLASH_RDID_V 0x1 -#define SPI_MEM_FLASH_RDID_S 28 - -/* SPI_MEM_FLASH_RDSR : R/W/SC ;bitpos:[27] ;default: 1'b0 ; */ - -/* Description: Read status register-1. Read status operation will be - * triggered when the bit is set. The bit will be cleared once the operation - * done.1: enable 0: disable. - */ - -#define SPI_MEM_FLASH_RDSR (BIT(27)) -#define SPI_MEM_FLASH_RDSR_M (BIT(27)) -#define SPI_MEM_FLASH_RDSR_V 0x1 -#define SPI_MEM_FLASH_RDSR_S 27 - -/* SPI_MEM_FLASH_WRSR : R/W/SC ;bitpos:[26] ;default: 1'b0 ; */ - -/* Description: Write status register enable. Write status operation will - * be triggered when the bit is set. The bit will be cleared once the - * operation done. - * 1: enable - * 0:disable. - */ - -#define SPI_MEM_FLASH_WRSR (BIT(26)) -#define SPI_MEM_FLASH_WRSR_M (BIT(26)) -#define SPI_MEM_FLASH_WRSR_V 0x1 -#define SPI_MEM_FLASH_WRSR_S 26 - -/* SPI_MEM_FLASH_PP : R/W/SC ;bitpos:[25] ;default: 1'b0 ; */ - -/* Description: Page program enable(1 byte ~64 bytes data to be programmed). - * Page program operation will be triggered when the bit is set. The bit - * will be cleared once the operation done. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_FLASH_PP (BIT(25)) -#define SPI_MEM_FLASH_PP_M (BIT(25)) -#define SPI_MEM_FLASH_PP_V 0x1 -#define SPI_MEM_FLASH_PP_S 25 - -/* SPI_MEM_FLASH_SE : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ - -/* Description: Sector erase enable(4KB). Sector erase operation will be - * triggered when the bit is set. The bit will be cleared once the operation - * done.1: enable 0: disable. - */ - -#define SPI_MEM_FLASH_SE (BIT(24)) -#define SPI_MEM_FLASH_SE_M (BIT(24)) -#define SPI_MEM_FLASH_SE_V 0x1 -#define SPI_MEM_FLASH_SE_S 24 - -/* SPI_MEM_FLASH_BE : R/W/SC ;bitpos:[23] ;default: 1'b0 ; */ - -/* Description: Block erase enable(32KB) . Block erase operation will be - * triggered when the bit is set. The bit will be cleared once the operation - * done. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_FLASH_BE (BIT(23)) -#define SPI_MEM_FLASH_BE_M (BIT(23)) -#define SPI_MEM_FLASH_BE_V 0x1 -#define SPI_MEM_FLASH_BE_S 23 - -/* SPI_MEM_FLASH_CE : R/W/SC ;bitpos:[22] ;default: 1'b0 ; */ - -/* Description: Chip erase enable. Chip erase operation will be triggered - * when the bit is set. The bit will be cleared once the operation done. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_FLASH_CE (BIT(22)) -#define SPI_MEM_FLASH_CE_M (BIT(22)) -#define SPI_MEM_FLASH_CE_V 0x1 -#define SPI_MEM_FLASH_CE_S 22 - -/* SPI_MEM_FLASH_DP : R/W/SC ;bitpos:[21] ;default: 1'b0 ; */ - -/* Description: Drive Flash into power down. An operation will be triggered - * when the bit is set. The bit will be cleared once the operation done.1: - * enable 0: disable. - */ - -#define SPI_MEM_FLASH_DP (BIT(21)) -#define SPI_MEM_FLASH_DP_M (BIT(21)) -#define SPI_MEM_FLASH_DP_V 0x1 -#define SPI_MEM_FLASH_DP_S 21 - -/* SPI_MEM_FLASH_RES : R/W/SC ;bitpos:[20] ;default: 1'b0 ; */ - -/* Description: This bit combined with SPI_MEM_RESANDRES bit releases Flash - * from the power-down state or high performance mode and obtains the devices - * ID. The bit will be cleared once the operation done.1: enable 0: disable. - */ - -#define SPI_MEM_FLASH_RES (BIT(20)) -#define SPI_MEM_FLASH_RES_M (BIT(20)) -#define SPI_MEM_FLASH_RES_V 0x1 -#define SPI_MEM_FLASH_RES_S 20 - -/* SPI_MEM_FLASH_HPM : R/W/SC ;bitpos:[19] ;default: 1'b0 ; */ - -/* Description: Drive Flash into high performance mode. The bit will be - * cleared once the operation done.1: enable 0: disable. - */ - -#define SPI_MEM_FLASH_HPM (BIT(19)) -#define SPI_MEM_FLASH_HPM_M (BIT(19)) -#define SPI_MEM_FLASH_HPM_V 0x1 -#define SPI_MEM_FLASH_HPM_S 19 - -/* SPI_MEM_USR : R/W/SC ;bitpos:[18] ;default: 1'b0 ; */ - -/* Description: User define command enable. An operation will be triggered - * when the bit is set. The bit will be cleared once the operation done.1: - * enable 0: disable. - */ - -#define SPI_MEM_USR (BIT(18)) -#define SPI_MEM_USR_M (BIT(18)) -#define SPI_MEM_USR_V 0x1 -#define SPI_MEM_USR_S 18 - -/* SPI_MEM_FLASH_PE : R/W/SC ;bitpos:[17] ;default: 1'b0 ; */ - -/* Description: In user mode, it is set to indicate that program/erase - * operation will be triggered. The bit is combined with SPI_MEM_USR bit. The - * bit will be cleared once the operation done.1: enable 0: disable. - */ - -#define SPI_MEM_FLASH_PE (BIT(17)) -#define SPI_MEM_FLASH_PE_M (BIT(17)) -#define SPI_MEM_FLASH_PE_V 0x1 -#define SPI_MEM_FLASH_PE_S 17 - -#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x4) - -/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ - -/* Description: In user mode, it is the memory address. other then the - * bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a - * transfer. - */ - -#define SPI_MEM_USR_ADDR_VALUE 0xFFFFFFFF -#define SPI_MEM_USR_ADDR_VALUE_M ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S)) -#define SPI_MEM_USR_ADDR_VALUE_V 0xFFFFFFFF -#define SPI_MEM_USR_ADDR_VALUE_S 0 - -#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x8) - -/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ - -/* Description: In hardware 0xEB read operation, ADDR phase and DIN phase - * apply 4 signals(4-bit-mode). - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_FREAD_QIO (BIT(24)) -#define SPI_MEM_FREAD_QIO_M (BIT(24)) -#define SPI_MEM_FREAD_QIO_V 0x1 -#define SPI_MEM_FREAD_QIO_S 24 - -/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ - -/* Description: In hardware 0xBB read operation, ADDR phase and DIN phase - * apply 2 signals(2-bit-mode). - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_FREAD_DIO (BIT(23)) -#define SPI_MEM_FREAD_DIO_M (BIT(23)) -#define SPI_MEM_FREAD_DIO_V 0x1 -#define SPI_MEM_FREAD_DIO_S 23 - -/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */ - -/* Description: Two bytes data will be written to status register when it is - * set. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_WRSR_2B (BIT(22)) -#define SPI_MEM_WRSR_2B_M (BIT(22)) -#define SPI_MEM_WRSR_2B_V 0x1 -#define SPI_MEM_WRSR_2B_S 22 - -/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ - -/* Description: Write protect signal output when SPI is idle. - * 1: output high, - * 0: output low. - */ - -#define SPI_MEM_WP_REG (BIT(21)) -#define SPI_MEM_WP_REG_M (BIT(21)) -#define SPI_MEM_WP_REG_V 0x1 -#define SPI_MEM_WP_REG_S 21 - -/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ - -/* Description: In hardware 0x6B read operation, DIN phase apply 4 - * signals(4-bit-mode). - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_FREAD_QUAD (BIT(20)) -#define SPI_MEM_FREAD_QUAD_M (BIT(20)) -#define SPI_MEM_FREAD_QUAD_V 0x1 -#define SPI_MEM_FREAD_QUAD_S 20 - -/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */ - -/* Description: The bit is used to set MOSI line polarity, - * 1: high - * 0: low - */ - -#define SPI_MEM_D_POL (BIT(19)) -#define SPI_MEM_D_POL_M (BIT(19)) -#define SPI_MEM_D_POL_V 0x1 -#define SPI_MEM_D_POL_S 19 - -/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */ - -/* Description: The bit is used to set MISO line polarity - * 1: high - * 0: low - */ - -#define SPI_MEM_Q_POL (BIT(18)) -#define SPI_MEM_Q_POL_M (BIT(18)) -#define SPI_MEM_Q_POL_V 0x1 -#define SPI_MEM_Q_POL_S 18 - -/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */ - -/* Description: The Device ID is read out to SPI_MEM_RD_STATUS register, this - * bit combine with spi_mem_flash_res bit. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_RESANDRES (BIT(15)) -#define SPI_MEM_RESANDRES_M (BIT(15)) -#define SPI_MEM_RESANDRES_V 0x1 -#define SPI_MEM_RESANDRES_S 15 - -/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ - -/* Description: In hardware 0x3B read operation, DIN phase apply 2 signals. - * 1: enable - * 0: disable - */ - -#define SPI_MEM_FREAD_DUAL (BIT(14)) -#define SPI_MEM_FREAD_DUAL_M (BIT(14)) -#define SPI_MEM_FREAD_DUAL_V 0x1 -#define SPI_MEM_FREAD_DUAL_S 14 - -/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ - -/* Description: This bit should be set when SPI_MEM_FREAD_QIO, - * SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD or SPI_MEM_FREAD_DUAL is set. - */ - -#define SPI_MEM_FASTRD_MODE (BIT(13)) -#define SPI_MEM_FASTRD_MODE_M (BIT(13)) -#define SPI_MEM_FASTRD_MODE_V 0x1 -#define SPI_MEM_FASTRD_MODE_S 13 - -/* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ - -/* Description: For SPI1, enable crc32 when writing encrypted data to flash. - * 1: enable - * 0:disable - */ - -#define SPI_MEM_TX_CRC_EN (BIT(11)) -#define SPI_MEM_TX_CRC_EN_M (BIT(11)) -#define SPI_MEM_TX_CRC_EN_V 0x1 -#define SPI_MEM_TX_CRC_EN_S 11 - -/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ - -/* Description: For SPI1, initialize crc32 module before writing encrypted - * data to flash. Active low. - */ - -#define SPI_MEM_FCS_CRC_EN (BIT(10)) -#define SPI_MEM_FCS_CRC_EN_M (BIT(10)) -#define SPI_MEM_FCS_CRC_EN_V 0x1 -#define SPI_MEM_FCS_CRC_EN_S 10 - -/* SPI_MEM_FCMD_OCT : R/W ;bitpos:[9] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 8-bit-mode(8-bm) in CMD phase. */ - -#define SPI_MEM_FCMD_OCT (BIT(9)) -#define SPI_MEM_FCMD_OCT_M (BIT(9)) -#define SPI_MEM_FCMD_OCT_V 0x1 -#define SPI_MEM_FCMD_OCT_S 9 - -/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 4-bit-mode(4-bm) in CMD phase. */ - -#define SPI_MEM_FCMD_QUAD (BIT(8)) -#define SPI_MEM_FCMD_QUAD_M (BIT(8)) -#define SPI_MEM_FCMD_QUAD_V 0x1 -#define SPI_MEM_FCMD_QUAD_S 8 - -/* SPI_MEM_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 2-bit-mode(2-bm) in CMD phase. */ - -#define SPI_MEM_FCMD_DUAL (BIT(7)) -#define SPI_MEM_FCMD_DUAL_M (BIT(7)) -#define SPI_MEM_FCMD_DUAL_V 0x1 -#define SPI_MEM_FCMD_DUAL_S 7 - -/* SPI_MEM_FADDR_OCT : R/W ;bitpos:[6] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 8-bit-mode(8-bm) in ADDR phase. */ - -#define SPI_MEM_FADDR_OCT (BIT(6)) -#define SPI_MEM_FADDR_OCT_M (BIT(6)) -#define SPI_MEM_FADDR_OCT_V 0x1 -#define SPI_MEM_FADDR_OCT_S 6 - -/* SPI_MEM_FDIN_OCT : R/W ;bitpos:[5] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 8-bit-mode(8-bm) in DIN phase. */ - -#define SPI_MEM_FDIN_OCT (BIT(5)) -#define SPI_MEM_FDIN_OCT_M (BIT(5)) -#define SPI_MEM_FDIN_OCT_V 0x1 -#define SPI_MEM_FDIN_OCT_S 5 - -/* SPI_MEM_FDOUT_OCT : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 8-bit-mode(8-bm) in DOUT phase. */ - -#define SPI_MEM_FDOUT_OCT (BIT(4)) -#define SPI_MEM_FDOUT_OCT_M (BIT(4)) -#define SPI_MEM_FDOUT_OCT_V 0x1 -#define SPI_MEM_FDOUT_OCT_S 4 - -/* SPI_MEM_FDUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: In the DUMMY phase the signal level of SPI bus is output by - * the SPI0 controller. - */ - -#define SPI_MEM_FDUMMY_OUT (BIT(3)) -#define SPI_MEM_FDUMMY_OUT_M (BIT(3)) -#define SPI_MEM_FDUMMY_OUT_V 0x1 -#define SPI_MEM_FDUMMY_OUT_S 3 - -#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0xC) - -/* SPI_MEM_RXFIFO_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */ - -/* Description: SPI0 RX FIFO reset signal. Set this bit and clear it before - * SPI0 transfer starts. - */ - -#define SPI_MEM_RXFIFO_RST (BIT(30)) -#define SPI_MEM_RXFIFO_RST_M (BIT(30)) -#define SPI_MEM_RXFIFO_RST_V 0x1 -#define SPI_MEM_RXFIFO_RST_S 30 - -/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[11:2] ;default: 10'h3ff ; */ - -/* Description: After RES/DP/HPM/PES/PER command is sent, SPI1 may waits - * (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or * 256) SPI_CLK cycles. - */ - -#define SPI_MEM_CS_HOLD_DLY_RES 0x000003FF -#define SPI_MEM_CS_HOLD_DLY_RES_M ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S)) -#define SPI_MEM_CS_HOLD_DLY_RES_V 0x3FF -#define SPI_MEM_CS_HOLD_DLY_RES_S 2 - -/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -/* Description: SPI Bus clock (SPI_CLK) mode bits. 0: SPI Bus clock (SPI_CLK) - * is off when CS inactive - * 1: SPI_CLK is delayed one cycle after SPI_CS inactive - * 2: SPI_CLK isdelayed two cycles after SPI_CS inactive - * 3: SPI_CLK is always on. - */ - -#define SPI_MEM_CLK_MODE 0x00000003 -#define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S)) -#define SPI_MEM_CLK_MODE_V 0x3 -#define SPI_MEM_CLK_MODE_S 0 - -#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x10) - -/* SPI_MEM_SYNC_RESET : R/W/SC ;bitpos:[31] ;default: 1'b0 ; */ - -/* Description: The FSM will be reset. */ - -#define SPI_MEM_SYNC_RESET (BIT(31)) -#define SPI_MEM_SYNC_RESET_M (BIT(31)) -#define SPI_MEM_SYNC_RESET_V 0x1 -#define SPI_MEM_SYNC_RESET_S 31 - -/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */ - -/* Description: These bits are used to set the minimum CS high time tSHSL - * between SPI burst transfer when accesses to flash. tSHSL is - * (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. - */ - -#define SPI_MEM_CS_HOLD_DELAY 0x0000003F -#define SPI_MEM_CS_HOLD_DELAY_M ((SPI_MEM_CS_HOLD_DELAY_V)<<(SPI_MEM_CS_HOLD_DELAY_S)) -#define SPI_MEM_CS_HOLD_DELAY_V 0x3F -#define SPI_MEM_CS_HOLD_DELAY_S 25 - -/* SPI_MEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC - * bytes mode when accesses flash. - */ - -#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) -#define SPI_MEM_ECC_16TO18_BYTE_EN_M (BIT(14)) -#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x1 -#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 - -/* SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[13] ;default: 1'b1 ; */ - -/* Description: 1: MSPI skips page corner when accesses flash. 0: Not skip - * page corner when accesses flash. - */ - -#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (BIT(13)) -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x1 -#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 - -/* SPI_MEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ - -/* Description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the SPI_CS - * hold cycle in ECC mode when accessed flash. - */ - -#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007 -#define SPI_MEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_ECC_CS_HOLD_TIME_S)) -#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x7 -#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 - -/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */ - -/* Description: SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus - * clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits - * are combined with SPI_MEM_CS_HOLD bit. - */ - -#define SPI_MEM_CS_HOLD_TIME 0x0000001F -#define SPI_MEM_CS_HOLD_TIME_M ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S)) -#define SPI_MEM_CS_HOLD_TIME_V 0x1F -#define SPI_MEM_CS_HOLD_TIME_S 5 - -/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */ - -/* Description: (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS - * setup time. These bits are combined with SPI_MEM_CS_SETUP bit. - */ - -#define SPI_MEM_CS_SETUP_TIME 0x0000001F -#define SPI_MEM_CS_SETUP_TIME_M ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S)) -#define SPI_MEM_CS_SETUP_TIME_V 0x1F -#define SPI_MEM_CS_SETUP_TIME_S 0 - -#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x14) - -/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ - -/* Description: When SPI1 access to flash or Ext_RAM, set this bit in - * 1-division mode, f_SPI_CLK = f_MSPI_CORE_CLK. - */ - -#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) -#define SPI_MEM_CLK_EQU_SYSCLK_M (BIT(31)) -#define SPI_MEM_CLK_EQU_SYSCLK_V 0x1 -#define SPI_MEM_CLK_EQU_SYSCLK_S 31 - -/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ - -/* Description: When SPI1 accesses to flash or Ext_RAM, f_SPI_CLK = - * f_MSPI_CORE_CLK/(SPI_MEM_CLK_CNT_N + 1) - */ - -#define SPI_MEM_CLKCNT_N 0x000000FF -#define SPI_MEM_CLKCNT_N_M ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S)) -#define SPI_MEM_CLKCNT_N_V 0xFF -#define SPI_MEM_CLKCNT_N_S 16 - -/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ - -/* Description: It must be a floor value of ((SPI_MEM_CLKCNT_N+1)/2-1). */ - -#define SPI_MEM_CLKCNT_H 0x000000FF -#define SPI_MEM_CLKCNT_H_M ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S)) -#define SPI_MEM_CLKCNT_H_V 0xFF -#define SPI_MEM_CLKCNT_H_S 8 - -/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ - -/* Description: It must equal to the value of SPI_MEM_CLKCNT_N. */ - -#define SPI_MEM_CLKCNT_L 0x000000FF -#define SPI_MEM_CLKCNT_L_M ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S)) -#define SPI_MEM_CLKCNT_L_V 0xFF -#define SPI_MEM_CLKCNT_L_S 0 - -#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x18) - -/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ - -/* Description: Set this bit to enable enable the CMD phase of an - * operation. - */ - -#define SPI_MEM_USR_COMMAND (BIT(31)) -#define SPI_MEM_USR_COMMAND_M (BIT(31)) -#define SPI_MEM_USR_COMMAND_V 0x1 -#define SPI_MEM_USR_COMMAND_S 31 - -/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable enable the ADDR phase of an operation. - */ - -#define SPI_MEM_USR_ADDR (BIT(30)) -#define SPI_MEM_USR_ADDR_M (BIT(30)) -#define SPI_MEM_USR_ADDR_V 0x1 -#define SPI_MEM_USR_ADDR_S 30 - -/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable enable the DUMMY phase of an - * operation. - */ - -#define SPI_MEM_USR_DUMMY (BIT(29)) -#define SPI_MEM_USR_DUMMY_M (BIT(29)) -#define SPI_MEM_USR_DUMMY_V 0x1 -#define SPI_MEM_USR_DUMMY_S 29 - -/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable enable the DIN phase of a read-data - * operation. - */ - -#define SPI_MEM_USR_MISO (BIT(28)) -#define SPI_MEM_USR_MISO_M (BIT(28)) -#define SPI_MEM_USR_MISO_V 0x1 -#define SPI_MEM_USR_MISO_S 28 - -/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable the DOUT phase of an write-data - * operation. - */ - -#define SPI_MEM_USR_MOSI (BIT(27)) -#define SPI_MEM_USR_MOSI_M (BIT(27)) -#define SPI_MEM_USR_MOSI_V 0x1 -#define SPI_MEM_USR_MOSI_S 27 - -/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ - -/* Description: SPI_CLK is disabled(No clock edges) in DUMMY phase when the - * bit is enable. - */ - -#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) -#define SPI_MEM_USR_DUMMY_IDLE_M (BIT(26)) -#define SPI_MEM_USR_DUMMY_IDLE_V 0x1 -#define SPI_MEM_USR_DUMMY_IDLE_S 26 - -/* SPI_MEM_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ - -/* Description: DOUT phase only access to high-part of the buffer - * SPI_MEM_W8_REG~SPI_MEM_W15_REG. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_USR_MOSI_HIGHPART (BIT(25)) -#define SPI_MEM_USR_MOSI_HIGHPART_M (BIT(25)) -#define SPI_MEM_USR_MOSI_HIGHPART_V 0x1 -#define SPI_MEM_USR_MOSI_HIGHPART_S 25 - -/* SPI_MEM_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ - -/* Description: DIN phase only access to high-part of the buffer - * SPI_MEM_W8_REG~SPI_MEM_W15_REG. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_USR_MISO_HIGHPART (BIT(24)) -#define SPI_MEM_USR_MISO_HIGHPART_M (BIT(24)) -#define SPI_MEM_USR_MISO_HIGHPART_V 0x1 -#define SPI_MEM_USR_MISO_HIGHPART_S 24 - -/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 4-bit-mode(4-bm) in ADDR and DOUT - * phase in SPI1 write operation. - */ - -#define SPI_MEM_FWRITE_QIO (BIT(15)) -#define SPI_MEM_FWRITE_QIO_M (BIT(15)) -#define SPI_MEM_FWRITE_QIO_V 0x1 -#define SPI_MEM_FWRITE_QIO_S 15 - -/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 2-bm in ADDR and DOUT phase in SPI1 - * write operation. - */ - -#define SPI_MEM_FWRITE_DIO (BIT(14)) -#define SPI_MEM_FWRITE_DIO_M (BIT(14)) -#define SPI_MEM_FWRITE_DIO_V 0x1 -#define SPI_MEM_FWRITE_DIO_S 14 - -/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 4-bm in DOUT phase in SPI1 write - * operation. - */ - -#define SPI_MEM_FWRITE_QUAD (BIT(13)) -#define SPI_MEM_FWRITE_QUAD_M (BIT(13)) -#define SPI_MEM_FWRITE_QUAD_V 0x1 -#define SPI_MEM_FWRITE_QUAD_S 13 - -/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable 2-bm in DOUT phase in SPI1 write - * operation. - */ - -#define SPI_MEM_FWRITE_DUAL (BIT(12)) -#define SPI_MEM_FWRITE_DUAL_M (BIT(12)) -#define SPI_MEM_FWRITE_DUAL_V 0x1 -#define SPI_MEM_FWRITE_DUAL_S 12 - -/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ - -/* Description: This bit, combined with SPI_MEM_CK_IDLE_EDGE bit, is used to - * change the clock mode 0~3 of SPI_CLK. - */ - -#define SPI_MEM_CK_OUT_EDGE (BIT(9)) -#define SPI_MEM_CK_OUT_EDGE_M (BIT(9)) -#define SPI_MEM_CK_OUT_EDGE_V 0x1 -#define SPI_MEM_CK_OUT_EDGE_S 9 - -/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */ - -/* Description: Set this bit to keep SPI_CS low when MSPI is in PREP state. */ - -#define SPI_MEM_CS_SETUP (BIT(7)) -#define SPI_MEM_CS_SETUP_M (BIT(7)) -#define SPI_MEM_CS_SETUP_V 0x1 -#define SPI_MEM_CS_SETUP_S 7 - -/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ - -/* Description: Set this bit to keep SPI_CS low when MSPI is in DONE state. */ - -#define SPI_MEM_CS_HOLD (BIT(6)) -#define SPI_MEM_CS_HOLD_M (BIT(6)) -#define SPI_MEM_CS_HOLD_V 0x1 -#define SPI_MEM_CS_HOLD_S 6 - -#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x1C) - -/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */ - -/* Description: The length in bits of ADDR phase. The register value shall be - * (bit_num-1). - */ - -#define SPI_MEM_USR_ADDR_BITLEN 0x0000003F -#define SPI_MEM_USR_ADDR_BITLEN_M ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S)) -#define SPI_MEM_USR_ADDR_BITLEN_V 0x3F -#define SPI_MEM_USR_ADDR_BITLEN_S 26 - -/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */ - -/* Description: The SPI_CLK cycle length minus 1 of DUMMY phase. */ - -#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003F -#define SPI_MEM_USR_DUMMY_CYCLELEN_M ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S)) -#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x3F -#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 - -#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x20) - -/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ - -/* Description: The length in bits of CMD phase. The register value shall be - * (bit_num-1) - */ - -#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000F -#define SPI_MEM_USR_COMMAND_BITLEN_M ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S)) -#define SPI_MEM_USR_COMMAND_BITLEN_V 0xF -#define SPI_MEM_USR_COMMAND_BITLEN_S 28 - -/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ - -/* Description: The value of user defined(USR) command. */ - -#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFF -#define SPI_MEM_USR_COMMAND_VALUE_M ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S)) -#define SPI_MEM_USR_COMMAND_VALUE_V 0xFFFF -#define SPI_MEM_USR_COMMAND_VALUE_S 0 - -#define SPI_MEM_MOSI_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x24) - -/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ - -/* Description: The length in bits of DOUT phase. The register value shall be - * (bit_num-1). - */ - -#define SPI_MEM_USR_MOSI_DBITLEN 0x000003FF -#define SPI_MEM_USR_MOSI_DBITLEN_M ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S)) -#define SPI_MEM_USR_MOSI_DBITLEN_V 0x3FF -#define SPI_MEM_USR_MOSI_DBITLEN_S 0 - -#define SPI_MEM_MISO_DLEN_REG(i) (REG_SPI_MEM_BASE(i) + 0x28) - -/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ - -/* Description: The length in bits of DIN phase. The register value shall be - * (bit_num-1). - */ - -#define SPI_MEM_USR_MISO_DBITLEN 0x000003FF -#define SPI_MEM_USR_MISO_DBITLEN_M ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S)) -#define SPI_MEM_USR_MISO_DBITLEN_V 0x3FF -#define SPI_MEM_USR_MISO_DBITLEN_S 0 - -#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x2C) - -/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ - -/* Description: Mode bits in the flash fast read mode it is combined with - * SPI_MEM_FASTRD_MODE bit. - */ - -#define SPI_MEM_WB_MODE 0x000000FF -#define SPI_MEM_WB_MODE_M ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S)) -#define SPI_MEM_WB_MODE_V 0xFF -#define SPI_MEM_WB_MODE_S 16 - -/* SPI_MEM_STATUS : R/W/SS ;bitpos:[15:0] ;default: 16'b0 ; */ - -/* Description: The value is stored when set SPI_MEM_FLASH_RDSR bit and - * SPI_MEM_FLASH_RES bit. - */ - -#define SPI_MEM_STATUS 0x0000FFFF -#define SPI_MEM_STATUS_M ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S)) -#define SPI_MEM_STATUS_V 0xFFFF -#define SPI_MEM_STATUS_S 0 - -#define SPI_MEM_EXT_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x30) - -/* SPI_MEM_EXT_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: The register are the higher 32bits in the 64 bits address - * mode. - */ - -#define SPI_MEM_EXT_ADDR 0xFFFFFFFF -#define SPI_MEM_EXT_ADDR_M ((SPI_MEM_EXT_ADDR_V)<<(SPI_MEM_EXT_ADDR_S)) -#define SPI_MEM_EXT_ADDR_V 0xFFFFFFFF -#define SPI_MEM_EXT_ADDR_S 0 - -#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x34) - -/* SPI_MEM_AUTO_PER : R/W ;bitpos:[11] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable auto PER function. Hardware will sent - * out PER command if PES command is sent. - */ - -#define SPI_MEM_AUTO_PER (BIT(11)) -#define SPI_MEM_AUTO_PER_M (BIT(11)) -#define SPI_MEM_AUTO_PER_V 0x1 -#define SPI_MEM_AUTO_PER_S 11 - -/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */ - -/* Description: SPI_CS line keep low when the bit is set. */ - -#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) -#define SPI_MEM_CS_KEEP_ACTIVE_M (BIT(10)) -#define SPI_MEM_CS_KEEP_ACTIVE_V 0x1 -#define SPI_MEM_CS_KEEP_ACTIVE_S 10 - -/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ - -/* Description: - * 1: SPI_CLK line is high when MSPI is idle. - * 0: SPI_CLK line is low when MSPI is idle. - */ - -#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) -#define SPI_MEM_CK_IDLE_EDGE_M (BIT(9)) -#define SPI_MEM_CK_IDLE_EDGE_V 0x1 -#define SPI_MEM_CK_IDLE_EDGE_S 9 - -/* SPI_MEM_SSUB_PIN : R/W ;bitpos:[8] ;default: 1'b0 ; */ - -/* Description: Ext_RAM is connected to SPI SUBPIN bus. */ - -#define SPI_MEM_SSUB_PIN (BIT(8)) -#define SPI_MEM_SSUB_PIN_M (BIT(8)) -#define SPI_MEM_SSUB_PIN_V 0x1 -#define SPI_MEM_SSUB_PIN_S 8 - -/* SPI_MEM_FSUB_PIN : R/W ;bitpos:[7] ;default: 1'b0 ; */ - -/* Description: Flash is connected to SPI SUBPIN bus. */ - -#define SPI_MEM_FSUB_PIN (BIT(7)) -#define SPI_MEM_FSUB_PIN_M (BIT(7)) -#define SPI_MEM_FSUB_PIN_V 0x1 -#define SPI_MEM_FSUB_PIN_S 7 - -/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ - -/* Description: Set this bit to raise high SPI_CS1 pin, which means that the - * SPI device(Ext_RAM) connected to SPI_CS1 is in low level when SPI1 - * transfer starts. - */ - -#define SPI_MEM_CS1_DIS (BIT(1)) -#define SPI_MEM_CS1_DIS_M (BIT(1)) -#define SPI_MEM_CS1_DIS_V 0x1 -#define SPI_MEM_CS1_DIS_S 1 - -/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: Set this bit to raise high SPI_CS pin, which means that the - * SPI device(flash) connected to SPI_CS is in low level when SPI1 transfer - * starts. - */ - -#define SPI_MEM_CS0_DIS (BIT(0)) -#define SPI_MEM_CS0_DIS_M (BIT(0)) -#define SPI_MEM_CS0_DIS_V 0x1 -#define SPI_MEM_CS0_DIS_S 0 - -#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x38) - -/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'hffffffff ; */ - -/* Description: For SPI1, the value of crc32. */ - -#define SPI_MEM_TX_CRC_DATA 0xFFFFFFFF -#define SPI_MEM_TX_CRC_DATA_M ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S)) -#define SPI_MEM_TX_CRC_DATA_V 0xFFFFFFFF -#define SPI_MEM_TX_CRC_DATA_S 0 - -#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x3C) - -/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ - -/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to - * enable 4-bm in ADDR phase. - */ - -#define SPI_MEM_FADDR_QUAD (BIT(8)) -#define SPI_MEM_FADDR_QUAD_M (BIT(8)) -#define SPI_MEM_FADDR_QUAD_V 0x1 -#define SPI_MEM_FADDR_QUAD_S 8 - -/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */ - -/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to - * enable 4-bm in DOUT phase. - */ - -#define SPI_MEM_FDOUT_QUAD (BIT(7)) -#define SPI_MEM_FDOUT_QUAD_M (BIT(7)) -#define SPI_MEM_FDOUT_QUAD_V 0x1 -#define SPI_MEM_FDOUT_QUAD_S 7 - -/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */ - -/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to - * enable 4-bm in DIN phase. - */ - -#define SPI_MEM_FDIN_QUAD (BIT(6)) -#define SPI_MEM_FDIN_QUAD_M (BIT(6)) -#define SPI_MEM_FDIN_QUAD_V 0x1 -#define SPI_MEM_FDIN_QUAD_S 6 - -/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */ - -/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to - * enable 2-bm in ADDR phase. - */ - -#define SPI_MEM_FADDR_DUAL (BIT(5)) -#define SPI_MEM_FADDR_DUAL_M (BIT(5)) -#define SPI_MEM_FADDR_DUAL_V 0x1 -#define SPI_MEM_FADDR_DUAL_S 5 - -/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to - * enable 2-bm in DOUT phase. - */ - -#define SPI_MEM_FDOUT_DUAL (BIT(4)) -#define SPI_MEM_FDOUT_DUAL_M (BIT(4)) -#define SPI_MEM_FDOUT_DUAL_V 0x1 -#define SPI_MEM_FDOUT_DUAL_S 4 - -/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: When SPI1 accesses to flash or Ext_RAM, set this bit to - * enable 2-bm in DIN phase. - */ - -#define SPI_MEM_FDIN_DUAL (BIT(3)) -#define SPI_MEM_FDIN_DUAL_M (BIT(3)) -#define SPI_MEM_FDIN_DUAL_V 0x1 -#define SPI_MEM_FDIN_DUAL_S 3 - -/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: - * 1: The command value of SPI0 reads flash is SPI_MEM_USR_COMMAND_VALUE. - * 0: Hardware read command value, controlled by SPI_MEM_FREAD_QIO, - * SPI_MEM_FREAD_DIO, SPI_MEM_FREAD_QUAD, SPI_MEM_FREAD_DUAL and - * SPI_MEM_FASTRD_MODE bits. - */ - -#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) -#define SPI_MEM_CACHE_FLASH_USR_CMD_M (BIT(2)) -#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x1 -#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 - -/* SPI_MEM_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: - * Set this bit to enable SPI1 transfer with 32 bits address. The value of - * SPI_MEM_USR_ADDR_BITLEN should be 31. - */ - -#define SPI_MEM_CACHE_USR_CMD_4BYTE (BIT(1)) -#define SPI_MEM_CACHE_USR_CMD_4BYTE_M (BIT(1)) -#define SPI_MEM_CACHE_USR_CMD_4BYTE_V 0x1 -#define SPI_MEM_CACHE_USR_CMD_4BYTE_S 1 - -/* SPI_MEM_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable Cache's access and SPI0's transfer. */ - -#define SPI_MEM_CACHE_REQ_EN (BIT(0)) -#define SPI_MEM_CACHE_REQ_EN_M (BIT(0)) -#define SPI_MEM_CACHE_REQ_EN_V 0x1 -#define SPI_MEM_CACHE_REQ_EN_S 0 - -#define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x40) - -/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W ;bitpos:[27:22] ;default: 6'b1 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus - * 1 of DUMMY phase in write data transfer. - */ - -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003F -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S)) -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x3F -#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22 - -/* SPI_MEM_SRAM_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */ - -/* Description: Set the bit to enable OPI mode in all SPI0 Ext_RAM - * transfer. - */ - -#define SPI_MEM_SRAM_OCT (BIT(21)) -#define SPI_MEM_SRAM_OCT_M (BIT(21)) -#define SPI_MEM_SRAM_OCT_V 0x1 -#define SPI_MEM_SRAM_OCT_S 21 - -/* SPI_MEM_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[20] ;default: 1'b1 ; */ - -/* Description: - * 1: The command value of SPI0 write Ext_RAM is - * SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE. - * 0: The value is 0x3. - */ - -#define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) -#define SPI_MEM_CACHE_SRAM_USR_WCMD_M (BIT(20)) -#define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x1 -#define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 - -/* SPI_MEM_SRAM_ADDR_BITLEN : R/W ;bitpos:[19:14] ;default: 6'd23 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, it is the length in bits of - * ADDR phase. The register value shall be (bit_num-1). - */ - -#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003F -#define SPI_MEM_SRAM_ADDR_BITLEN_M ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S)) -#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x3F -#define SPI_MEM_SRAM_ADDR_BITLEN_S 14 - -/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'b1 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, it is the SPI_CLK cycles minus - * 1 of DUMMY phase in read data transfer. - */ - -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003F -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S)) -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x3F -#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 - -/* SPI_MEM_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */ - -/* Description: - * 1: The command value of SPI0 read Ext_RAM is - * SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE. - * 0: The value is 0x2. - */ - -#define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) -#define SPI_MEM_CACHE_SRAM_USR_RCMD_M (BIT(5)) -#define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x1 -#define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 - -/* SPI_MEM_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY - * phase in read operations. - */ - -#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4)) -#define SPI_MEM_USR_RD_SRAM_DUMMY_M (BIT(4)) -#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x1 -#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 - -/* SPI_MEM_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable DUMMY - * phase in write operations. - */ - -#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3)) -#define SPI_MEM_USR_WR_SRAM_DUMMY_M (BIT(3)) -#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x1 -#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 - -/* SPI_MEM_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: Set the bit to enable QPI mode in all SPI0 Ext_RAM transfer. - */ - -#define SPI_MEM_USR_SRAM_QIO (BIT(2)) -#define SPI_MEM_USR_SRAM_QIO_M (BIT(2)) -#define SPI_MEM_USR_SRAM_QIO_V 0x1 -#define SPI_MEM_USR_SRAM_QIO_S 2 - -/* SPI_MEM_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: Set the bit to enable 2-bm in all the phases of SPI0 Ext_RAM - * transfer. - */ - -#define SPI_MEM_USR_SRAM_DIO (BIT(1)) -#define SPI_MEM_USR_SRAM_DIO_M (BIT(1)) -#define SPI_MEM_USR_SRAM_DIO_V 0x1 -#define SPI_MEM_USR_SRAM_DIO_S 1 - -/* SPI_MEM_CACHE_USR_SCMD_4BYTE : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable SPI0 read Ext_RAM with 32 bits - * address. The value of SPI_MEM_SRAM_ADDR_BITLEN should be 31. - */ - -#define SPI_MEM_CACHE_USR_SCMD_4BYTE (BIT(0)) -#define SPI_MEM_CACHE_USR_SCMD_4BYTE_M (BIT(0)) -#define SPI_MEM_CACHE_USR_SCMD_4BYTE_V 0x1 -#define SPI_MEM_CACHE_USR_SCMD_4BYTE_S 0 - -#define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x44) - -/* SPI_MEM_SDUMMY_OUT : R/W ;bitpos:[22] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, in the DUMMY phase the signal - * level of SPI bus is output by the SPI0 controller. - */ - -#define SPI_MEM_SDUMMY_OUT (BIT(22)) -#define SPI_MEM_SDUMMY_OUT_M (BIT(22)) -#define SPI_MEM_SDUMMY_OUT_V 0x1 -#define SPI_MEM_SDUMMY_OUT_S 22 - -/* SPI_MEM_SCMD_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in - * CMD phase. - */ - -#define SPI_MEM_SCMD_OCT (BIT(21)) -#define SPI_MEM_SCMD_OCT_M (BIT(21)) -#define SPI_MEM_SCMD_OCT_V 0x1 -#define SPI_MEM_SCMD_OCT_S 21 - -/* SPI_MEM_SADDR_OCT : R/W ;bitpos:[20] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in - * ADDR phase. - */ - -#define SPI_MEM_SADDR_OCT (BIT(20)) -#define SPI_MEM_SADDR_OCT_M (BIT(20)) -#define SPI_MEM_SADDR_OCT_V 0x1 -#define SPI_MEM_SADDR_OCT_S 20 - -/* SPI_MEM_SDOUT_OCT : R/W ;bitpos:[19] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in - * DOUT phase. - */ - -#define SPI_MEM_SDOUT_OCT (BIT(19)) -#define SPI_MEM_SDOUT_OCT_M (BIT(19)) -#define SPI_MEM_SDOUT_OCT_V 0x1 -#define SPI_MEM_SDOUT_OCT_S 19 - -/* SPI_MEM_SDIN_OCT : R/W ;bitpos:[18] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 8-bm in - * DIN phase. - */ - -#define SPI_MEM_SDIN_OCT (BIT(18)) -#define SPI_MEM_SDIN_OCT_M (BIT(18)) -#define SPI_MEM_SDIN_OCT_V 0x1 -#define SPI_MEM_SDIN_OCT_S 18 - -/* SPI_MEM_SCMD_QUAD : R/W ;bitpos:[17] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in - * CMD phase. - */ - -#define SPI_MEM_SCMD_QUAD (BIT(17)) -#define SPI_MEM_SCMD_QUAD_M (BIT(17)) -#define SPI_MEM_SCMD_QUAD_V 0x1 -#define SPI_MEM_SCMD_QUAD_S 17 - -/* SPI_MEM_SADDR_QUAD : R/W ;bitpos:[16] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in - * ADDR phase. - */ - -#define SPI_MEM_SADDR_QUAD (BIT(16)) -#define SPI_MEM_SADDR_QUAD_M (BIT(16)) -#define SPI_MEM_SADDR_QUAD_V 0x1 -#define SPI_MEM_SADDR_QUAD_S 16 - -/* SPI_MEM_SDOUT_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in - * DOUT phase. - */ - -#define SPI_MEM_SDOUT_QUAD (BIT(15)) -#define SPI_MEM_SDOUT_QUAD_M (BIT(15)) -#define SPI_MEM_SDOUT_QUAD_V 0x1 -#define SPI_MEM_SDOUT_QUAD_S 15 - -/* SPI_MEM_SDIN_QUAD : R/W ;bitpos:[14] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 4-bm in - * DIN phase. - */ - -#define SPI_MEM_SDIN_QUAD (BIT(14)) -#define SPI_MEM_SDIN_QUAD_M (BIT(14)) -#define SPI_MEM_SDIN_QUAD_V 0x1 -#define SPI_MEM_SDIN_QUAD_S 14 - -/* SPI_MEM_SCMD_DUAL : R/W ;bitpos:[13] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in - * CMD phase. - */ - -#define SPI_MEM_SCMD_DUAL (BIT(13)) -#define SPI_MEM_SCMD_DUAL_M (BIT(13)) -#define SPI_MEM_SCMD_DUAL_V 0x1 -#define SPI_MEM_SCMD_DUAL_S 13 - -/* SPI_MEM_SADDR_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in - * ADDR phase. - */ - -#define SPI_MEM_SADDR_DUAL (BIT(12)) -#define SPI_MEM_SADDR_DUAL_M (BIT(12)) -#define SPI_MEM_SADDR_DUAL_V 0x1 -#define SPI_MEM_SADDR_DUAL_S 12 - -/* SPI_MEM_SDOUT_DUAL : R/W ;bitpos:[11] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in - * DOUT phase. - */ - -#define SPI_MEM_SDOUT_DUAL (BIT(11)) -#define SPI_MEM_SDOUT_DUAL_M (BIT(11)) -#define SPI_MEM_SDOUT_DUAL_V 0x1 -#define SPI_MEM_SDOUT_DUAL_S 11 - -/* SPI_MEM_SDIN_DUAL : R/W ;bitpos:[10] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit to enable 2-bm in - * DIN phase. - */ - -#define SPI_MEM_SDIN_DUAL (BIT(10)) -#define SPI_MEM_SDIN_DUAL_M (BIT(10)) -#define SPI_MEM_SDIN_DUAL_V 0x1 -#define SPI_MEM_SDIN_DUAL_S 10 - -/* SPI_MEM_SWB_MODE : R/W ;bitpos:[9:2] ;default: 8'b0 ; */ - -/* Description: Mode bits when SPI0 accesses to Ext_RAM. */ - -#define SPI_MEM_SWB_MODE 0x000000FF -#define SPI_MEM_SWB_MODE_M ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S)) -#define SPI_MEM_SWB_MODE_V 0xFF -#define SPI_MEM_SWB_MODE_S 2 - -/* SPI_MEM_SCLK_MODE : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ - -/* Description: SPI_CLK mode bits when SPI0 accesses to Ext_RAM. - * 0: SPI_CLK is off when CS inactive - * 1: SPI_CLK is delayed one cycle after CS inactive - * 2: SPI_CLK is delayed two cycles after CS inactive - * 3: SPI_CLK is always on. - */ - -#define SPI_MEM_SCLK_MODE 0x00000003 -#define SPI_MEM_SCLK_MODE_M ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S)) -#define SPI_MEM_SCLK_MODE_V 0x3 -#define SPI_MEM_SCLK_MODE_S 0 - -#define SPI_MEM_SRAM_DRD_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x48) - -/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN: R/W;bitpos:[31:28];default:4'h0; */ - -/* Description: When SPI0 reads Ext_RAM, it is the length in bits of CMD - * phase. The register value shall be (bit_num-1). - */ - -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 - -/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE: R/W;bitpos:[15:0];default:16'h0; */ - -/* Description: When SPI0 reads Ext_RAM, it is the command value of - * CMD phase. - */ - -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S)) -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF -#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 - -#define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x4C) - -/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN: R/W;bitpos:[31:28];default:4'h0; */ - -/* Description: When SPI0 writes Ext_RAM, it is the length in bits of CMD - * phase. The register value shall be (bit_num-1). - */ - -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 - -/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE: R/W;bitpos:[15:0];default: 16'h0; */ - -/* Description: When SPI0 writes Ext_RAM, it is the command value of - * CMD phase. - */ - -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S)) -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF -#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 - -#define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x50) - -/* SPI_MEM_SCLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, set this bit in 1-division - * mode, f_SPI_CLK = f_MSPI_CORE_CLK. - */ - -#define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) -#define SPI_MEM_SCLK_EQU_SYSCLK_M (BIT(31)) -#define SPI_MEM_SCLK_EQU_SYSCLK_V 0x1 -#define SPI_MEM_SCLK_EQU_SYSCLK_S 31 - -/* SPI_MEM_SCLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ - -/* Description: When SPI0 accesses to Ext_RAM, f_SPI_CLK = - * f_MSPI_CORE_CLK/(SPI_MEM_SCLKCNT_N+1) - */ - -#define SPI_MEM_SCLKCNT_N 0x000000FF -#define SPI_MEM_SCLKCNT_N_M ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S)) -#define SPI_MEM_SCLKCNT_N_V 0xFF -#define SPI_MEM_SCLKCNT_N_S 16 - -/* SPI_MEM_SCLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ - -/* Description: It must be a floor value of ((SPI_MEM_SCLKCNT_N+1)/2-1). */ - -#define SPI_MEM_SCLKCNT_H 0x000000FF -#define SPI_MEM_SCLKCNT_H_M ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S)) -#define SPI_MEM_SCLKCNT_H_V 0xFF -#define SPI_MEM_SCLKCNT_H_S 8 - -/* SPI_MEM_SCLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ - -/* Description: It must equal to the value of SPI_MEM_SCLKCNT_N. */ - -#define SPI_MEM_SCLKCNT_L 0x000000FF -#define SPI_MEM_SCLKCNT_L_M ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S)) -#define SPI_MEM_SCLKCNT_L_V 0xFF -#define SPI_MEM_SCLKCNT_L_S 0 - -#define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x54) - -/* SPI_MEM_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */ - -/* Description: The status of SPI1 state machine. - * 0: idle state(IDLE), - * 1: preparation state(PREP), - * 2: send command state(CMD), - * 3: send address state(ADDR), - * 4: red data state(DIN), - * 5:write data state(DOUT), - * 6: wait state(DUMMY), - * 7: done state(DONE). - */ - -#define SPI_MEM_ST 0x00000007 -#define SPI_MEM_ST_M ((SPI_MEM_ST_V)<<(SPI_MEM_ST_S)) -#define SPI_MEM_ST_V 0x7 -#define SPI_MEM_ST_S 0 - -#define SPI_MEM_W0_REG(i) (REG_SPI_MEM_BASE(i) + 0x58) - -/* SPI_MEM_BUF0 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF0 0xFFFFFFFF -#define SPI_MEM_BUF0_M ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S)) -#define SPI_MEM_BUF0_V 0xFFFFFFFF -#define SPI_MEM_BUF0_S 0 - -#define SPI_MEM_W1_REG(i) (REG_SPI_MEM_BASE(i) + 0x5C) - -/* SPI_MEM_BUF1 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF1 0xFFFFFFFF -#define SPI_MEM_BUF1_M ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S)) -#define SPI_MEM_BUF1_V 0xFFFFFFFF -#define SPI_MEM_BUF1_S 0 - -#define SPI_MEM_W2_REG(i) (REG_SPI_MEM_BASE(i) + 0x60) - -/* SPI_MEM_BUF2 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF2 0xFFFFFFFF -#define SPI_MEM_BUF2_M ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S)) -#define SPI_MEM_BUF2_V 0xFFFFFFFF -#define SPI_MEM_BUF2_S 0 - -#define SPI_MEM_W3_REG(i) (REG_SPI_MEM_BASE(i) + 0x64) - -/* SPI_MEM_BUF3 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF3 0xFFFFFFFF -#define SPI_MEM_BUF3_M ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S)) -#define SPI_MEM_BUF3_V 0xFFFFFFFF -#define SPI_MEM_BUF3_S 0 - -#define SPI_MEM_W4_REG(i) (REG_SPI_MEM_BASE(i) + 0x68) - -/* SPI_MEM_BUF4 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF4 0xFFFFFFFF -#define SPI_MEM_BUF4_M ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S)) -#define SPI_MEM_BUF4_V 0xFFFFFFFF -#define SPI_MEM_BUF4_S 0 - -#define SPI_MEM_W5_REG(i) (REG_SPI_MEM_BASE(i) + 0x6C) - -/* SPI_MEM_BUF5 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF5 0xFFFFFFFF -#define SPI_MEM_BUF5_M ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S)) -#define SPI_MEM_BUF5_V 0xFFFFFFFF -#define SPI_MEM_BUF5_S 0 - -#define SPI_MEM_W6_REG(i) (REG_SPI_MEM_BASE(i) + 0x70) - -/* SPI_MEM_BUF6 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF6 0xFFFFFFFF -#define SPI_MEM_BUF6_M ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S)) -#define SPI_MEM_BUF6_V 0xFFFFFFFF -#define SPI_MEM_BUF6_S 0 - -#define SPI_MEM_W7_REG(i) (REG_SPI_MEM_BASE(i) + 0x74) - -/* SPI_MEM_BUF7 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF7 0xFFFFFFFF -#define SPI_MEM_BUF7_M ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S)) -#define SPI_MEM_BUF7_V 0xFFFFFFFF -#define SPI_MEM_BUF7_S 0 - -#define SPI_MEM_W8_REG(i) (REG_SPI_MEM_BASE(i) + 0x78) - -/* SPI_MEM_BUF8 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF8 0xFFFFFFFF -#define SPI_MEM_BUF8_M ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S)) -#define SPI_MEM_BUF8_V 0xFFFFFFFF -#define SPI_MEM_BUF8_S 0 - -#define SPI_MEM_W9_REG(i) (REG_SPI_MEM_BASE(i) + 0x7C) - -/* SPI_MEM_BUF9 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF9 0xFFFFFFFF -#define SPI_MEM_BUF9_M ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S)) -#define SPI_MEM_BUF9_V 0xFFFFFFFF -#define SPI_MEM_BUF9_S 0 - -#define SPI_MEM_W10_REG(i) (REG_SPI_MEM_BASE(i) + 0x80) - -/* SPI_MEM_BUF10 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF10 0xFFFFFFFF -#define SPI_MEM_BUF10_M ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S)) -#define SPI_MEM_BUF10_V 0xFFFFFFFF -#define SPI_MEM_BUF10_S 0 - -#define SPI_MEM_W11_REG(i) (REG_SPI_MEM_BASE(i) + 0x84) - -/* SPI_MEM_BUF11 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF11 0xFFFFFFFF -#define SPI_MEM_BUF11_M ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S)) -#define SPI_MEM_BUF11_V 0xFFFFFFFF -#define SPI_MEM_BUF11_S 0 - -#define SPI_MEM_W12_REG(i) (REG_SPI_MEM_BASE(i) + 0x88) - -/* SPI_MEM_BUF12 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF12 0xFFFFFFFF -#define SPI_MEM_BUF12_M ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S)) -#define SPI_MEM_BUF12_V 0xFFFFFFFF -#define SPI_MEM_BUF12_S 0 - -#define SPI_MEM_W13_REG(i) (REG_SPI_MEM_BASE(i) + 0x8C) - -/* SPI_MEM_BUF13 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF13 0xFFFFFFFF -#define SPI_MEM_BUF13_M ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S)) -#define SPI_MEM_BUF13_V 0xFFFFFFFF -#define SPI_MEM_BUF13_S 0 - -#define SPI_MEM_W14_REG(i) (REG_SPI_MEM_BASE(i) + 0x90) - -/* SPI_MEM_BUF14 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF14 0xFFFFFFFF -#define SPI_MEM_BUF14_M ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S)) -#define SPI_MEM_BUF14_V 0xFFFFFFFF -#define SPI_MEM_BUF14_S 0 - -#define SPI_MEM_W15_REG(i) (REG_SPI_MEM_BASE(i) + 0x94) - -/* SPI_MEM_BUF15 : R/W/SS ;bitpos:[31:0] ;default: 32'b0 ; */ - -/* Description: data buffer */ - -#define SPI_MEM_BUF15 0xFFFFFFFF -#define SPI_MEM_BUF15_M ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S)) -#define SPI_MEM_BUF15_V 0xFFFFFFFF -#define SPI_MEM_BUF15_S 0 - -#define SPI_MEM_FLASH_WAITI_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x98) - -/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[15:10] ;default: 6'h0 ; */ - -/* Description: The dummy cycle length when wait flash idle(RDSR). */ - -#define SPI_MEM_WAITI_DUMMY_CYCLELEN 0x0000003F -#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S)) -#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V 0x3F -#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S 10 - -/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[9:2] ;default: 8'h05 ; */ - -/* Description: The command value of auto wait flash idle transfer(RDSR). */ - -#define SPI_MEM_WAITI_CMD 0x000000FF -#define SPI_MEM_WAITI_CMD_M ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S)) -#define SPI_MEM_WAITI_CMD_V 0xFF -#define SPI_MEM_WAITI_CMD_S 2 - -/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable DUMMY phase in auto wait flash idle - * transfer(RDSR). - */ - -#define SPI_MEM_WAITI_DUMMY (BIT(1)) -#define SPI_MEM_WAITI_DUMMY_M (BIT(1)) -#define SPI_MEM_WAITI_DUMMY_V 0x1 -#define SPI_MEM_WAITI_DUMMY_S 1 - -/* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable auto-waiting flash idle operation when - * PP/SE/BE/CE/WRSR/PES command is sent. - */ - -#define SPI_MEM_WAITI_EN (BIT(0)) -#define SPI_MEM_WAITI_EN_M (BIT(0)) -#define SPI_MEM_WAITI_EN_V 0x1 -#define SPI_MEM_WAITI_EN_S 0 - -#define SPI_MEM_FLASH_SUS_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x9C) - -/* SPI_MEM_PESR_IDLE_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ - -/* Description: - * 1: Separate PER flash wait idle and PES flash wait idle. - * 0: Not separate. - */ - -#define SPI_MEM_PESR_IDLE_EN (BIT(5)) -#define SPI_MEM_PESR_IDLE_EN_M (BIT(5)) -#define SPI_MEM_PESR_IDLE_EN_V 0x1 -#define SPI_MEM_PESR_IDLE_EN_S 5 - -/* SPI_MEM_PES_PER_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable PES transfer trigger PES transfer - * option. - */ - -#define SPI_MEM_PES_PER_EN (BIT(4)) -#define SPI_MEM_PES_PER_EN_M (BIT(4)) -#define SPI_MEM_PES_PER_EN_V 0x1 -#define SPI_MEM_PES_PER_EN_S 4 - -/* SPI_MEM_FLASH_PES_WAIT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: Set this bit to add delay time after program erase - * suspend(PES) command is sent. - */ - -#define SPI_MEM_FLASH_PES_WAIT_EN (BIT(3)) -#define SPI_MEM_FLASH_PES_WAIT_EN_M (BIT(3)) -#define SPI_MEM_FLASH_PES_WAIT_EN_V 0x1 -#define SPI_MEM_FLASH_PES_WAIT_EN_S 3 - -/* SPI_MEM_FLASH_PER_WAIT_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: Set this bit to add delay time after program erase resume - * (PER) is sent. - */ - -#define SPI_MEM_FLASH_PER_WAIT_EN (BIT(2)) -#define SPI_MEM_FLASH_PER_WAIT_EN_M (BIT(2)) -#define SPI_MEM_FLASH_PER_WAIT_EN_V 0x1 -#define SPI_MEM_FLASH_PER_WAIT_EN_S 2 - -/* SPI_MEM_FLASH_PES : R/W/SS/SC ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: program erase suspend bit, program erase suspend operation - * will be triggered when the bit is set. The bit will be cleared once the - * operation done. - * 1: enable - * 0:disable. - */ - -#define SPI_MEM_FLASH_PES (BIT(1)) -#define SPI_MEM_FLASH_PES_M (BIT(1)) -#define SPI_MEM_FLASH_PES_V 0x1 -#define SPI_MEM_FLASH_PES_S 1 - -/* SPI_MEM_FLASH_PER : R/W/SS/SC ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: program erase resume bit, program erase suspend operation - * will be triggered when the bit is set. The bit will be cleared once the - * operation done. - * 1: enable - * 0: disable. - */ - -#define SPI_MEM_FLASH_PER (BIT(0)) -#define SPI_MEM_FLASH_PER_M (BIT(0)) -#define SPI_MEM_FLASH_PER_V 0x1 -#define SPI_MEM_FLASH_PER_S 0 - -#define SPI_MEM_FLASH_SUS_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0xA0) - -/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[16:9] ;default: 8'h75 ; */ - -/* Description: Program/Erase suspend command value. */ - -#define SPI_MEM_FLASH_PES_COMMAND 0x000000FF -#define SPI_MEM_FLASH_PES_COMMAND_M ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S)) -#define SPI_MEM_FLASH_PES_COMMAND_V 0xFF -#define SPI_MEM_FLASH_PES_COMMAND_S 9 - -/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[8:1] ;default: 8'h7a ; */ - -/* Description: Program/Erase resume command value. */ - -#define SPI_MEM_FLASH_PER_COMMAND 0x000000FF -#define SPI_MEM_FLASH_PER_COMMAND_M ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S)) -#define SPI_MEM_FLASH_PER_COMMAND_V 0xFF -#define SPI_MEM_FLASH_PER_COMMAND_S 1 - -/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable auto-suspend function. */ - -#define SPI_MEM_FLASH_PES_EN (BIT(0)) -#define SPI_MEM_FLASH_PES_EN_M (BIT(0)) -#define SPI_MEM_FLASH_PES_EN_V 0x1 -#define SPI_MEM_FLASH_PES_EN_S 0 - -#define SPI_MEM_SUS_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0xA4) - -/* SPI_MEM_FLASH_PES_DLY_256 : R/W ;bitpos:[6] ;default: 1'b0 ; */ - -/* Description: Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. - * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) - * SPI_CLK cycles after PES command is sent. - * 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after - * PES command is sent. - */ - -#define SPI_MEM_FLASH_PES_DLY_256 (BIT(6)) -#define SPI_MEM_FLASH_PES_DLY_256_M (BIT(6)) -#define SPI_MEM_FLASH_PES_DLY_256_V 0x1 -#define SPI_MEM_FLASH_PES_DLY_256_S 6 - -/* SPI_MEM_FLASH_PER_DLY_256 : R/W ;bitpos:[5] ;default: 1'b0 ; */ - -/* Description: Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. - * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK cycles after - * PER command is sent. - * 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after - * PER command is sent. - */ - -#define SPI_MEM_FLASH_PER_DLY_256 (BIT(5)) -#define SPI_MEM_FLASH_PER_DLY_256_M (BIT(5)) -#define SPI_MEM_FLASH_PER_DLY_256_V 0x1 -#define SPI_MEM_FLASH_PER_DLY_256_S 5 - -/* SPI_MEM_FLASH_DP_DLY_256 : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: - * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK - * cycles after DP command is sent. - * 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP - * command is sent. - */ - -#define SPI_MEM_FLASH_DP_DLY_256 (BIT(4)) -#define SPI_MEM_FLASH_DP_DLY_256_M (BIT(4)) -#define SPI_MEM_FLASH_DP_DLY_256_V 0x1 -#define SPI_MEM_FLASH_DP_DLY_256_S 4 - -/* SPI_MEM_FLASH_RES_DLY_256 : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: - * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK - * cycles after RES command is sent. - * 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after - * RES command is sent. - */ - -#define SPI_MEM_FLASH_RES_DLY_256 (BIT(3)) -#define SPI_MEM_FLASH_RES_DLY_256_M (BIT(3)) -#define SPI_MEM_FLASH_RES_DLY_256_V 0x1 -#define SPI_MEM_FLASH_RES_DLY_256_S 3 - -/* SPI_MEM_FLASH_HPM_DLY_256 : R/W ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: - * 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 256) SPI_CLK - * cycles after HPM command is sent. - * 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after - * HPM command is sent. - */ - -#define SPI_MEM_FLASH_HPM_DLY_256 (BIT(2)) -#define SPI_MEM_FLASH_HPM_DLY_256_M (BIT(2)) -#define SPI_MEM_FLASH_HPM_DLY_256_V 0x1 -#define SPI_MEM_FLASH_HPM_DLY_256_S 2 - -/* SPI_MEM_FLASH_SUS : R/W/SS/SC ;bitpos:[0] ;default: 1'h0 ; */ - -/* Description: The status of flash suspend. This bit is set when PES command - * is sent, and cleared when PER is sent. Only used in SPI1. - */ - -#define SPI_MEM_FLASH_SUS (BIT(0)) -#define SPI_MEM_FLASH_SUS_M (BIT(0)) -#define SPI_MEM_FLASH_SUS_V 0x1 -#define SPI_MEM_FLASH_SUS_S 0 - -#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0xA8) - -/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ - -/* Description: Extra SPI_CLK cycles added in DUMMY phase for timing - * compensation. Active when SPI_MEM_TIMING_CALI bit is set. - */ - -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007 -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)) -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x7 -#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 - -/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for - * all reading operations. - */ - -#define SPI_MEM_TIMING_CALI (BIT(1)) -#define SPI_MEM_TIMING_CALI_M (BIT(1)) -#define SPI_MEM_TIMING_CALI_V 0x1 -#define SPI_MEM_TIMING_CALI_S 1 - -/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: Set this bit to power on HCLK. When PLL is powered on, the - * frequency of HCLK equals to that of PLL. Otherwise, the frequency equals - * to that of XTAL. - */ - -#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) -#define SPI_MEM_TIMING_CLK_ENA_M (BIT(0)) -#define SPI_MEM_TIMING_CLK_ENA_V 0x1 -#define SPI_MEM_TIMING_CLK_ENA_S 0 - -#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xAC) - -/* SPI_MEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ - -/* Description: SPI_DQS input delay mode. - * 0: No delay. - * 1: Delay for (SPI_MEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DINS_NUM+1) - * cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_MEM_DINS_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DINS_NUM+1) - * cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DINS_MODE 0x00000007 -#define SPI_MEM_DINS_MODE_M ((SPI_MEM_DINS_MODE_V)<<(SPI_MEM_DINS_MODE_S)) -#define SPI_MEM_DINS_MODE_V 0x7 -#define SPI_MEM_DINS_MODE_S 24 - -/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ - -/* Description: SPI_IO7 input delay mode. - * 0: No delay. - * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) - * cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DIN7_MODE 0x00000007 -#define SPI_MEM_DIN7_MODE_M ((SPI_MEM_DIN7_MODE_V)<<(SPI_MEM_DIN7_MODE_S)) -#define SPI_MEM_DIN7_MODE_V 0x7 -#define SPI_MEM_DIN7_MODE_S 21 - -/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ - -/* Description: SPI_IO6 input delay mode. - * 0: No delay. - * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. 5: Delay for (SPI_MEM_DIN$n_NUM+1) - * cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DIN6_MODE 0x00000007 -#define SPI_MEM_DIN6_MODE_M ((SPI_MEM_DIN6_MODE_V)<<(SPI_MEM_DIN6_MODE_S)) -#define SPI_MEM_DIN6_MODE_V 0x7 -#define SPI_MEM_DIN6_MODE_S 18 - -/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ - -/* Description: SPI_IO5 input delay mode. - * 0: No delay. - * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. 3: Delay for - * (SPI_MEM_DIN$n_NUM+1) - * cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative - * edge. - * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DIN5_MODE 0x00000007 -#define SPI_MEM_DIN5_MODE_M ((SPI_MEM_DIN5_MODE_V)<<(SPI_MEM_DIN5_MODE_S)) -#define SPI_MEM_DIN5_MODE_V 0x7 -#define SPI_MEM_DIN5_MODE_S 15 - -/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ - -/* Description: SPI_IO4 input delay mode. - * 0: No delay. - * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_MEM_DIN$n_NUM+1) - * cycles at HCLK negative edge and one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DIN4_MODE 0x00000007 -#define SPI_MEM_DIN4_MODE_M ((SPI_MEM_DIN4_MODE_V)<<(SPI_MEM_DIN4_MODE_S)) -#define SPI_MEM_DIN4_MODE_V 0x7 -#define SPI_MEM_DIN4_MODE_S 12 - -/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ - -/* Description: SPI_HD input delay mode. - * 0: No delay. - * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. 3: Delay for (SPI_MEM_DIN$n_NUM+1) - * cycles at HCLK positive edge and one cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DIN3_MODE 0x00000007 -#define SPI_MEM_DIN3_MODE_M ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S)) -#define SPI_MEM_DIN3_MODE_V 0x7 -#define SPI_MEM_DIN3_MODE_S 9 - -/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ - -/* Description: SPI_WP input delay mode. - * 0: No delay. - * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DIN2_MODE 0x00000007 -#define SPI_MEM_DIN2_MODE_M ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S)) -#define SPI_MEM_DIN2_MODE_V 0x7 -#define SPI_MEM_DIN2_MODE_S 6 - -/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ - -/* Description: SPI_Q input delay mode. - * 0: No delay. - * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DIN1_MODE 0x00000007 -#define SPI_MEM_DIN1_MODE_M ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S)) -#define SPI_MEM_DIN1_MODE_V 0x7 -#define SPI_MEM_DIN1_MODE_S 3 - -/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ - -/* Description: SPI_D input delay mode. - * 0: No delay. - * 1: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK nega tive edge. - * 4: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and o ne - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_MEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DIN0_MODE 0x00000007 -#define SPI_MEM_DIN0_MODE_M ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S)) -#define SPI_MEM_DIN0_MODE_V 0x7 -#define SPI_MEM_DIN0_MODE_S 0 - -#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0xB0) - -/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ - -/* Description: SPI_DQS input delay number. */ - -#define SPI_MEM_DINS_NUM 0x00000003 -#define SPI_MEM_DINS_NUM_M ((SPI_MEM_DINS_NUM_V)<<(SPI_MEM_DINS_NUM_S)) -#define SPI_MEM_DINS_NUM_V 0x3 -#define SPI_MEM_DINS_NUM_S 16 - -/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ - -/* Description: SPI_IO7 input delay number. */ - -#define SPI_MEM_DIN7_NUM 0x00000003 -#define SPI_MEM_DIN7_NUM_M ((SPI_MEM_DIN7_NUM_V)<<(SPI_MEM_DIN7_NUM_S)) -#define SPI_MEM_DIN7_NUM_V 0x3 -#define SPI_MEM_DIN7_NUM_S 14 - -/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ - -/* Description: SPI_IO6 input delay number. */ - -#define SPI_MEM_DIN6_NUM 0x00000003 -#define SPI_MEM_DIN6_NUM_M ((SPI_MEM_DIN6_NUM_V)<<(SPI_MEM_DIN6_NUM_S)) -#define SPI_MEM_DIN6_NUM_V 0x3 -#define SPI_MEM_DIN6_NUM_S 12 - -/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ - -/* Description: SPI_IO5 input delay number. */ - -#define SPI_MEM_DIN5_NUM 0x00000003 -#define SPI_MEM_DIN5_NUM_M ((SPI_MEM_DIN5_NUM_V)<<(SPI_MEM_DIN5_NUM_S)) -#define SPI_MEM_DIN5_NUM_V 0x3 -#define SPI_MEM_DIN5_NUM_S 10 - -/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ - -/* Description: SPI_IO4 input delay number. */ - -#define SPI_MEM_DIN4_NUM 0x00000003 -#define SPI_MEM_DIN4_NUM_M ((SPI_MEM_DIN4_NUM_V)<<(SPI_MEM_DIN4_NUM_S)) -#define SPI_MEM_DIN4_NUM_V 0x3 -#define SPI_MEM_DIN4_NUM_S 8 - -/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ - -/* Description: SPI_HD input delay number. */ - -#define SPI_MEM_DIN3_NUM 0x00000003 -#define SPI_MEM_DIN3_NUM_M ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S)) -#define SPI_MEM_DIN3_NUM_V 0x3 -#define SPI_MEM_DIN3_NUM_S 6 - -/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ - -/* Description: SPI_WP input delay number. */ - -#define SPI_MEM_DIN2_NUM 0x00000003 -#define SPI_MEM_DIN2_NUM_M ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S)) -#define SPI_MEM_DIN2_NUM_V 0x3 -#define SPI_MEM_DIN2_NUM_S 4 - -/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ - -/* Description: SPI_Q input delay number. */ - -#define SPI_MEM_DIN1_NUM 0x00000003 -#define SPI_MEM_DIN1_NUM_M ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S)) -#define SPI_MEM_DIN1_NUM_V 0x3 -#define SPI_MEM_DIN1_NUM_S 2 - -/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -/* Description: SPI_D input delay number. */ - -#define SPI_MEM_DIN0_NUM 0x00000003 -#define SPI_MEM_DIN0_NUM_M ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S)) -#define SPI_MEM_DIN0_NUM_V 0x3 -#define SPI_MEM_DIN0_NUM_S 0 - -#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xB4) - -/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -/* Description: SPI_DQS output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DOUTS_MODE (BIT(8)) -#define SPI_MEM_DOUTS_MODE_M (BIT(8)) -#define SPI_MEM_DOUTS_MODE_V 0x1 -#define SPI_MEM_DOUTS_MODE_S 8 - -/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ - -/* Description: SPI_IO7 output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DOUT7_MODE (BIT(7)) -#define SPI_MEM_DOUT7_MODE_M (BIT(7)) -#define SPI_MEM_DOUT7_MODE_V 0x1 -#define SPI_MEM_DOUT7_MODE_S 7 - -/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -/* Description: SPI_IO6 output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DOUT6_MODE (BIT(6)) -#define SPI_MEM_DOUT6_MODE_M (BIT(6)) -#define SPI_MEM_DOUT6_MODE_V 0x1 -#define SPI_MEM_DOUT6_MODE_S 6 - -/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -/* Description: SPI_IO5 output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DOUT5_MODE (BIT(5)) -#define SPI_MEM_DOUT5_MODE_M (BIT(5)) -#define SPI_MEM_DOUT5_MODE_V 0x1 -#define SPI_MEM_DOUT5_MODE_S 5 - -/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ - -/* Description: SPI_IO4 output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DOUT4_MODE (BIT(4)) -#define SPI_MEM_DOUT4_MODE_M (BIT(4)) -#define SPI_MEM_DOUT4_MODE_V 0x1 -#define SPI_MEM_DOUT4_MODE_S 4 - -/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ - -/* Description: SPI_HD output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DOUT3_MODE (BIT(3)) -#define SPI_MEM_DOUT3_MODE_M (BIT(3)) -#define SPI_MEM_DOUT3_MODE_V 0x1 -#define SPI_MEM_DOUT3_MODE_S 3 - -/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -/* Description: SPI_WP output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DOUT2_MODE (BIT(2)) -#define SPI_MEM_DOUT2_MODE_M (BIT(2)) -#define SPI_MEM_DOUT2_MODE_V 0x1 -#define SPI_MEM_DOUT2_MODE_S 2 - -/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ - -/* Description: SPI_Q output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DOUT1_MODE (BIT(1)) -#define SPI_MEM_DOUT1_MODE_M (BIT(1)) -#define SPI_MEM_DOUT1_MODE_V 0x1 -#define SPI_MEM_DOUT1_MODE_S 1 - -/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ - -/* Description: SPI_D output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_DOUT0_MODE (BIT(0)) -#define SPI_MEM_DOUT0_MODE_M (BIT(0)) -#define SPI_MEM_DOUT0_MODE_V 0x1 -#define SPI_MEM_DOUT0_MODE_S 0 - -#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0xBC) - -/* SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN: R/W ;bitpos:[4:2]; default: 3'd0; */ - -/* Description: Extra SPI_CLK cycles added in DUMMY phase for timing - * compensation, when SPI0 accesses to Ext_RAM. Active when - * SPI_SMEM_TIMING_CALI bit is set. - */ - -#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007 -#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S)) -#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x7 -#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 - -/* SPI_MEM_SPI_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: Set this bit to add extra SPI_CLK cycles in DUMMY phase for - * all reading operations. - */ - -#define SPI_MEM_SPI_SMEM_TIMING_CALI (BIT(1)) -#define SPI_MEM_SPI_SMEM_TIMING_CALI_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_TIMING_CALI_V 0x1 -#define SPI_MEM_SPI_SMEM_TIMING_CALI_S 1 - -/* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: Set this bit to power on HCLK. When PLL is powered on, the - * frequency of HCLK equals to that of PLL. Otherwise, the frequency equals - * to that of XTAL. - */ - -#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA (BIT(0)) -#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V 0x1 -#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_S 0 - -#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xC0) - -/* SPI_MEM_SPI_SMEM_DINS_MODE : R/W ;bitpos:[26:24] ;default: 3'h0 ; */ - -/* Description: SPI_DQS input delay mode. - * 0: No delay. - * 1: Delay for (SPI_SMEM_DINS_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_SMEM_DINS_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DINS_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DINS_MODE_M ((SPI_MEM_SPI_SMEM_DINS_MODE_V)<<(SPI_MEM_SPI_SMEM_DINS_MODE_S)) -#define SPI_MEM_SPI_SMEM_DINS_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DINS_MODE_S 24 - -/* SPI_MEM_SPI_SMEM_DIN7_MODE : R/W ;bitpos:[23:21] ;default: 3'h0 ; */ - -/* Description: SPI_IO7 input delay mode. - * 0: No delay. - * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DIN7_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN7_MODE_M ((SPI_MEM_SPI_SMEM_DIN7_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN7_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN7_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN7_MODE_S 21 - -/* SPI_MEM_SPI_SMEM_DIN6_MODE : R/W ;bitpos:[20:18] ;default: 3'h0 ; */ - -/* Description: SPI_IO6 input delay mode. - * 0: No delay. - * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (S PI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DIN6_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN6_MODE_M ((SPI_MEM_SPI_SMEM_DIN6_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN6_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN6_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN6_MODE_S 18 - -/* SPI_MEM_SPI_SMEM_DIN5_MODE : R/W ;bitpos:[17:15] ;default: 3'h0 ; */ - -/* Description: SPI_IO5 input delay mode. - * 0: No delay. - * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DIN5_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN5_MODE_M ((SPI_MEM_SPI_SMEM_DIN5_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN5_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN5_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN5_MODE_S 15 - -/* SPI_MEM_SPI_SMEM_DIN4_MODE : R/W ;bitpos:[14:12] ;default: 3'h0 ; */ - -/* Description: SPI_IO4 input delay mode. - * 0: No delay. - * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_SMEM_DIN$n_NUM+ 1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DIN4_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN4_MODE_M ((SPI_MEM_SPI_SMEM_DIN4_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN4_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN4_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN4_MODE_S 12 - -/* SPI_MEM_SPI_SMEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ - -/* Description: SPI_HD input delay mode. - * 0: No delay. - * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DIN3_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN3_MODE_M ((SPI_MEM_SPI_SMEM_DIN3_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN3_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN3_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN3_MODE_S 9 - -/* SPI_MEM_SPI_SMEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */ - -/* Description: SPI_WP input delay mode. - * 0: No delay. - * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DIN2_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN2_MODE_M ((SPI_MEM_SPI_SMEM_DIN2_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN2_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN2_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN2_MODE_S 6 - -/* SPI_MEM_SPI_SMEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */ - -/* Description: SPI_Q input delay mode. - * 0: No delay. - * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DIN1_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN1_MODE_M ((SPI_MEM_SPI_SMEM_DIN1_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN1_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN1_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN1_MODE_S 3 - -/* SPI_MEM_SPI_SMEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ - -/* Description: SPI_D input delay mode. - * 0: No delay. - * 1: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at MSPI_CORE_CLK negative edge. - * 2: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 3: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK positive edge and one - * cycle at MSPI_CORE_CLK negative edge. - * 4: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK positive edge. - * 5: Delay for (SPI_SMEM_DIN$n_NUM+1) cycles at HCLK negative edge and one - * cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DIN0_MODE 0x00000007 -#define SPI_MEM_SPI_SMEM_DIN0_MODE_M ((SPI_MEM_SPI_SMEM_DIN0_MODE_V)<<(SPI_MEM_SPI_SMEM_DIN0_MODE_S)) -#define SPI_MEM_SPI_SMEM_DIN0_MODE_V 0x7 -#define SPI_MEM_SPI_SMEM_DIN0_MODE_S 0 - -#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0xC4) - -/* SPI_MEM_SPI_SMEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ - -/* Description: SPI_DQS input delay number. */ - -#define SPI_MEM_SPI_SMEM_DINS_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DINS_NUM_M ((SPI_MEM_SPI_SMEM_DINS_NUM_V)<<(SPI_MEM_SPI_SMEM_DINS_NUM_S)) -#define SPI_MEM_SPI_SMEM_DINS_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DINS_NUM_S 16 - -/* SPI_MEM_SPI_SMEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ - -/* Description: SPI_IO7 input delay number. */ - -#define SPI_MEM_SPI_SMEM_DIN7_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN7_NUM_M ((SPI_MEM_SPI_SMEM_DIN7_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN7_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN7_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN7_NUM_S 14 - -/* SPI_MEM_SPI_SMEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ - -/* Description: SPI_IO6 input delay number. */ - -#define SPI_MEM_SPI_SMEM_DIN6_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN6_NUM_M ((SPI_MEM_SPI_SMEM_DIN6_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN6_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN6_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN6_NUM_S 12 - -/* SPI_MEM_SPI_SMEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ - -/* Description: SPI_IO5 input delay number. */ - -#define SPI_MEM_SPI_SMEM_DIN5_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN5_NUM_M ((SPI_MEM_SPI_SMEM_DIN5_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN5_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN5_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN5_NUM_S 10 - -/* SPI_MEM_SPI_SMEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ - -/* Description: SPI_IO4 input delay number. */ - -#define SPI_MEM_SPI_SMEM_DIN4_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN4_NUM_M ((SPI_MEM_SPI_SMEM_DIN4_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN4_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN4_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN4_NUM_S 8 - -/* SPI_MEM_SPI_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ - -/* Description: SPI_HD input delay number. */ - -#define SPI_MEM_SPI_SMEM_DIN3_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN3_NUM_M ((SPI_MEM_SPI_SMEM_DIN3_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN3_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN3_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN3_NUM_S 6 - -/* SPI_MEM_SPI_SMEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ - -/* Description: SPI_WP input delay number. */ - -#define SPI_MEM_SPI_SMEM_DIN2_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN2_NUM_M ((SPI_MEM_SPI_SMEM_DIN2_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN2_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN2_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN2_NUM_S 4 - -/* SPI_MEM_SPI_SMEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ - -/* Description: SPI_Q input delay number. */ - -#define SPI_MEM_SPI_SMEM_DIN1_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN1_NUM_M ((SPI_MEM_SPI_SMEM_DIN1_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN1_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN1_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN1_NUM_S 2 - -/* SPI_MEM_SPI_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ - -/* Description: SPI_D input delay number. */ - -#define SPI_MEM_SPI_SMEM_DIN0_NUM 0x00000003 -#define SPI_MEM_SPI_SMEM_DIN0_NUM_M ((SPI_MEM_SPI_SMEM_DIN0_NUM_V)<<(SPI_MEM_SPI_SMEM_DIN0_NUM_S)) -#define SPI_MEM_SPI_SMEM_DIN0_NUM_V 0x3 -#define SPI_MEM_SPI_SMEM_DIN0_NUM_S 0 - -#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0xC8) - -/* SPI_MEM_SPI_SMEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ - -/* Description: SPI_DQS output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DOUTS_MODE (BIT(8)) -#define SPI_MEM_SPI_SMEM_DOUTS_MODE_M (BIT(8)) -#define SPI_MEM_SPI_SMEM_DOUTS_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUTS_MODE_S 8 - -/* SPI_MEM_SPI_SMEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ - -/* Description: SPI_IO7 output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DOUT7_MODE (BIT(7)) -#define SPI_MEM_SPI_SMEM_DOUT7_MODE_M (BIT(7)) -#define SPI_MEM_SPI_SMEM_DOUT7_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT7_MODE_S 7 - -/* SPI_MEM_SPI_SMEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ - -/* Description: SPI_IO6 output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DOUT6_MODE (BIT(6)) -#define SPI_MEM_SPI_SMEM_DOUT6_MODE_M (BIT(6)) -#define SPI_MEM_SPI_SMEM_DOUT6_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT6_MODE_S 6 - -/* SPI_MEM_SPI_SMEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ - -/* Description: SPI_IO5 output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DOUT5_MODE (BIT(5)) -#define SPI_MEM_SPI_SMEM_DOUT5_MODE_M (BIT(5)) -#define SPI_MEM_SPI_SMEM_DOUT5_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT5_MODE_S 5 - -/* SPI_MEM_SPI_SMEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ - -/* Description: SPI_IO4 output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DOUT4_MODE (BIT(4)) -#define SPI_MEM_SPI_SMEM_DOUT4_MODE_M (BIT(4)) -#define SPI_MEM_SPI_SMEM_DOUT4_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT4_MODE_S 4 - -/* SPI_MEM_SPI_SMEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ - -/* Description: SPI_HD output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DOUT3_MODE (BIT(3)) -#define SPI_MEM_SPI_SMEM_DOUT3_MODE_M (BIT(3)) -#define SPI_MEM_SPI_SMEM_DOUT3_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT3_MODE_S 3 - -/* SPI_MEM_SPI_SMEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ - -/* Description: SPI_WP output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DOUT2_MODE (BIT(2)) -#define SPI_MEM_SPI_SMEM_DOUT2_MODE_M (BIT(2)) -#define SPI_MEM_SPI_SMEM_DOUT2_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT2_MODE_S 2 - -/* SPI_MEM_SPI_SMEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ - -/* Description: SPI_Q output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DOUT1_MODE (BIT(1)) -#define SPI_MEM_SPI_SMEM_DOUT1_MODE_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_DOUT1_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT1_MODE_S 1 - -/* SPI_MEM_SPI_SMEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ - -/* Description: SPI_D output delay mode. - * 0: No delay. - * 1: Delay one cycle at MSPI_CORE_CLK negative edge. - */ - -#define SPI_MEM_SPI_SMEM_DOUT0_MODE (BIT(0)) -#define SPI_MEM_SPI_SMEM_DOUT0_MODE_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_DOUT0_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DOUT0_MODE_S 0 - -#define SPI_MEM_ECC_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0xCC) - -/* SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ - -/* Description: Set this bit to calculate the error times of MSPI ECC read - * when accesses to flash. - */ - -#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN (BIT(8)) -#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_M (BIT(8)) -#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_ECC_ERR_INT_EN_S 8 - -/* SPI_MEM_ECC_ERR_INT_NUM : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ - -/* Description: Set the error times of MSPI ECC read to generate MSPI - * SPI_MEM_ECC_ERR_INT interrupt. - */ - -#define SPI_MEM_ECC_ERR_INT_NUM 0x000000FF -#define SPI_MEM_ECC_ERR_INT_NUM_M ((SPI_MEM_ECC_ERR_INT_NUM_V)<<(SPI_MEM_ECC_ERR_INT_NUM_S)) -#define SPI_MEM_ECC_ERR_INT_NUM_V 0xFF -#define SPI_MEM_ECC_ERR_INT_NUM_S 0 - -#define SPI_MEM_ECC_ERR_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xD0) - -/* SPI_MEM_ECC_ERR_ADDR : R/SS/WTC ;bitpos:[31:0] ;default: 32'h0 ; */ - -/* Description: These bits show the first MSPI ECC error address when - * SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to - * flash/Ext_RAM, including ECC byte error and data error. It is cleared by - * when SPI_MEM_ECC_ERR_INT_CLR bit is set. - */ - -#define SPI_MEM_ECC_ERR_ADDR 0xFFFFFFFF -#define SPI_MEM_ECC_ERR_ADDR_M ((SPI_MEM_ECC_ERR_ADDR_V)<<(SPI_MEM_ECC_ERR_ADDR_S)) -#define SPI_MEM_ECC_ERR_ADDR_V 0xFFFFFFFF -#define SPI_MEM_ECC_ERR_ADDR_S 0 - -#define SPI_MEM_ECC_ERR_BIT_REG(i) (REG_SPI_MEM_BASE(i) + 0xD4) - -/* SPI_MEM_ECC_ERR_CNT : RO ;bitpos:[24:17] ;default: 8'd0 ; */ - -/* Description: This bits show the error times of MSPI ECC read, including - * ECC byte error and data byte error. It is cleared by when - * SPI_MEM_ECC_ERR_INT_CLR bit is set. - */ - -#define SPI_MEM_ECC_ERR_CNT 0x000000FF -#define SPI_MEM_ECC_ERR_CNT_M ((SPI_MEM_ECC_ERR_CNT_V)<<(SPI_MEM_ECC_ERR_CNT_S)) -#define SPI_MEM_ECC_ERR_CNT_V 0xFF -#define SPI_MEM_ECC_ERR_CNT_S 17 - -/* SPI_MEM_ECC_BYTE_ERR : R/SS/WTC ;bitpos:[16] ;default: 1'd0 ; */ - -/* Description: It records the first ECC byte error when - * SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to - * flash/Ext_RAM. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit. - */ - -#define SPI_MEM_ECC_BYTE_ERR (BIT(16)) -#define SPI_MEM_ECC_BYTE_ERR_M (BIT(16)) -#define SPI_MEM_ECC_BYTE_ERR_V 0x1 -#define SPI_MEM_ECC_BYTE_ERR_S 16 - -/* SPI_MEM_ECC_CHK_ERR_BIT : R/SS/WTC ;bitpos:[15:13] ;default: 3'd0 ; */ - -/* Description: When SPI_MEM_ECC_BYTE_ERR is set, these bits show the error - * bit number of ECC byte. - */ - -#define SPI_MEM_ECC_CHK_ERR_BIT 0x00000007 -#define SPI_MEM_ECC_CHK_ERR_BIT_M ((SPI_MEM_ECC_CHK_ERR_BIT_V)<<(SPI_MEM_ECC_CHK_ERR_BIT_S)) -#define SPI_MEM_ECC_CHK_ERR_BIT_V 0x7 -#define SPI_MEM_ECC_CHK_ERR_BIT_S 13 - -/* SPI_MEM_ECC_DATA_ERR_BIT : R/SS/WTC ;bitpos:[12:6] ;default: 7'd0 ; */ - -/* Description: It records the first ECC data error bit number when - * SPI_FMEM_ECC_ERR_INT_EN/SPI_SMEM_ECC_ERR_INT_EN is set and accessed to - * flash/Ext_RAM. The value ranges from 0~127, corresponding to the bit - * number in 16 data bytes. It is cleared by SPI_MEM_ECC_ERR_INT_CLR bit. - */ - -#define SPI_MEM_ECC_DATA_ERR_BIT 0x0000007F -#define SPI_MEM_ECC_DATA_ERR_BIT_M ((SPI_MEM_ECC_DATA_ERR_BIT_V)<<(SPI_MEM_ECC_DATA_ERR_BIT_S)) -#define SPI_MEM_ECC_DATA_ERR_BIT_V 0x7F -#define SPI_MEM_ECC_DATA_ERR_BIT_S 6 - -#define SPI_MEM_SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0xDC) - -/* SPI_MEM_SPI_SMEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */ - -/* Description: These bits are used to set the minimum CS high time tSHSL - * between SPI burst transfer when accesses to external RAM. tSHSL is - * (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles. - */ - -#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY 0x0000003F -#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_M ((SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S)) -#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V 0x3F -#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S 25 - -/* SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ - -/* Description: Set this bit to calculate the error times of MSPI ECC read - * when accesses to external RAM. - */ - -#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN (BIT(24)) -#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_M (BIT(24)) -#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_ECC_ERR_INT_EN_S 24 - -/* SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC - * bytes mode when accesses to external RAM. - */ - -#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) -#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_M (BIT(16)) -#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_S 16 - -/* SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER: R/W;bitpos:[15];default:1'b1 ; */ - -/* Description: - * 1: MSPI skips page corner when accesses to external RAM. - * 0: Not skip page corner when accesses to external RAM. - */ - -#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) -#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_M (BIT(15)) -#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x1 -#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15 - -/* SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ - -/* Description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI - * CS hold cycles in ECC mode when accesses to external RAM. - */ - -#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME 0x00000007 -#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S)) -#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V 0x7 -#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S 12 - -/* SPI_MEM_SPI_SMEM_CS_HOLD_TIME : R/W ;bitpos:[11:7] ;default: 5'h1 ; */ - -/* Description: SPI Bus CS (SPI_CS) signal is delayed to inactive by SPI Bus - * clock (SPI_CLK), which is the SPI_CS hold time in non-ECC mode. These bits - * are combined with SPI_MEM_CS_HOLD bit. - */ - -#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME 0x0000001F -#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S)) -#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V 0x1F -#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S 7 - -/* SPI_MEM_SPI_SMEM_CS_SETUP_TIME : R/W ;bitpos:[6:2] ;default: 5'h1 ; */ - -/* Description: (cycles-1) of PREP phase by SPI_CLK, which is the SPI_CS - * setup time. These bits are combined with SPI_MEM_CS_SETUP bit. - */ - -#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME 0x0000001F -#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_M ((SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V)<<(SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S)) -#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V 0x1F -#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S 2 - -/* SPI_MEM_SPI_SMEM_CS_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: Set this bit to keep SPI_CS low when MSPI is in DONE state. */ - -#define SPI_MEM_SPI_SMEM_CS_HOLD (BIT(1)) -#define SPI_MEM_SPI_SMEM_CS_HOLD_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_CS_HOLD_V 0x1 -#define SPI_MEM_SPI_SMEM_CS_HOLD_S 1 - -/* SPI_MEM_SPI_SMEM_CS_SETUP : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: Set this bit to keep SPI_CS low when MSPI is in PREP state. */ - -#define SPI_MEM_SPI_SMEM_CS_SETUP (BIT(0)) -#define SPI_MEM_SPI_SMEM_CS_SETUP_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_CS_SETUP_V 0x1 -#define SPI_MEM_SPI_SMEM_CS_SETUP_S 0 - -#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xE0) - -/* SPI_MEM_SPI_FMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable HyperRAM address out when accesses to - * flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], 13'd0, - * spi_usr_addr_value[3:1]}. - */ - -#define SPI_MEM_SPI_FMEM_HYPERBUS_CA (BIT(30)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_M (BIT(30)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_V 0x1 -#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_S 30 - -/* SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable octa_ram address out when accesses to - * flash, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], 6'd0, - * spi_usr_addr_value[3:1],1'b0}. - */ - -#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR (BIT(29)) -#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_M (BIT(29)) -#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_V 0x1 -#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_S 29 - -/* SPI_MEM_SPI_FMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */ - -/* Description: Set this bit to invert SPI_DIFF when accesses to flash. */ - -#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV (BIT(28)) -#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_M (BIT(28)) -#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_V 0x1 -#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_S 28 - -/* SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable the vary dummy function in SPI - * HyperBus mode, when SPI0 accesses flash or SPI1 accesses flash or sram. - */ - -#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x1 -#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 - -/* SPI_MEM_SPI_FMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable the input of SPI_DQS signal in SPI - * phases of CMD and ADDR. - */ - -#define SPI_MEM_SPI_FMEM_DQS_CA_IN (BIT(26)) -#define SPI_MEM_SPI_FMEM_DQS_CA_IN_M (BIT(26)) -#define SPI_MEM_SPI_FMEM_DQS_CA_IN_V 0x1 -#define SPI_MEM_SPI_FMEM_DQS_CA_IN_S 26 - -/* SPI_MEM_SPI_FMEM_HYPERBUS_MODE : R/W ;bitpos:[25] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable the SPI HyperBus mode. */ - -#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE (BIT(25)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_M (BIT(25)) -#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_V 0x1 -#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_S 25 - -/* SPI_MEM_SPI_FMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable the differential SPI_CLK#. */ - -#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN (BIT(24)) -#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_M (BIT(24)) -#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_S 24 - -/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[22] ;default: 1'b0 ; */ - -/* Description: When SPI_FMEM_DDR_DQS_LOOP and SPI_FMEM_DDR_EN are set, - * 1: Use internal SPI_CLK as data strobe. - * 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not - * active. - */ - -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE (BIT(22)) -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_M (BIT(22)) -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_S 22 - -/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */ - -/* Description: - * 1: Use internal signal as data strobe, the strobe can not be delayed by - * input timing module. - * 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be - * delayed by input timing module - */ - -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP (BIT(21)) -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_M (BIT(21)) -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_S 21 - -/* SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ - -/* Description: The delay number of data strobe which from memory based on - * SPI_CLK. - */ - -#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD 0x0000007F -#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S)) -#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V 0x7F -#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S 14 - -/* SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ - -/* Description: Set this bit to mask the first or the last byte in MSPI ECC - * DDR read mode, when accesses to flash. - */ - -#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN (BIT(13)) -#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_M (BIT(13)) -#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_S 13 - -/* SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ - -/* Description: Set this bit to mask the first or the last byte in MSPI ECC - * DDR write mode, when accesses to flash. - */ - -#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN (BIT(12)) -#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_M (BIT(12)) -#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_S 12 - -/* SPI_MEM_SPI_FMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */ - -/* Description: It is the minimum output data length in the panda device. */ - -#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN 0x0000007F -#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S)) -#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V 0x7F -#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S 5 - -/* SPI_MEM_SPI_FMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: the bit is used to disable dual edge in command phase when - * DDR mode. - */ - -#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS (BIT(4)) -#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_M (BIT(4)) -#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S 4 - -/* SPI_MEM_SPI_FMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: Set the bit to reorder TX data of the word in DDR mode. */ - -#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP (BIT(3)) -#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_M (BIT(3)) -#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_S 3 - -/* SPI_MEM_SPI_FMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: Set the bit to reorder RX data of the word in DDR mode. */ - -#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP (BIT(2)) -#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_M (BIT(2)) -#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S 2 - -/* SPI_MEM_SPI_FMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: Set the bit to enable variable dummy cycle in DDRmode. */ - -#define SPI_MEM_SPI_FMEM_VAR_DUMMY (BIT(1)) -#define SPI_MEM_SPI_FMEM_VAR_DUMMY_M (BIT(1)) -#define SPI_MEM_SPI_FMEM_VAR_DUMMY_V 0x1 -#define SPI_MEM_SPI_FMEM_VAR_DUMMY_S 1 - -/* SPI_MEM_SPI_FMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: 1: in DDR mode, 0: in SDR mode. */ - -#define SPI_MEM_SPI_FMEM_DDR_EN (BIT(0)) -#define SPI_MEM_SPI_FMEM_DDR_EN_M (BIT(0)) -#define SPI_MEM_SPI_FMEM_DDR_EN_V 0x1 -#define SPI_MEM_SPI_FMEM_DDR_EN_S 0 - -#define SPI_MEM_SPI_SMEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0xE4) - -/* SPI_MEM_SPI_SMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable HyperRAM address out when accesses to - * external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4], - * 13'd0, spi_usr_addr_value[3:1]}. - */ - -#define SPI_MEM_SPI_SMEM_HYPERBUS_CA (BIT(30)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_M (BIT(30)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_V 0x1 -#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_S 30 - -/* SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable octa_ram address out when accesses to - * external RAM, which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4], - * 6'd0, spi_usr_addr_value[3:1], 1'b0}. - */ - -#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR (BIT(29)) -#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_M (BIT(29)) -#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_V 0x1 -#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_S 29 - -/* SPI_MEM_SPI_SMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */ - -/* Description: Set this bit to invert SPI_DIFF when accesses to external RAM - */ - -#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV (BIT(28)) -#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_M (BIT(28)) -#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_V 0x1 -#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_S 28 - -/* SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable the vary dummy function in SPI - * HyperBus mode, when SPI0 accesses to flash or SPI1 accesses flash or - * sram. - */ - -#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x1 -#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_S 27 - -/* SPI_MEM_SPI_SMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable the input of SPI_DQS signal in SPI - * phases of CMD and ADDR. - */ - -#define SPI_MEM_SPI_SMEM_DQS_CA_IN (BIT(26)) -#define SPI_MEM_SPI_SMEM_DQS_CA_IN_M (BIT(26)) -#define SPI_MEM_SPI_SMEM_DQS_CA_IN_V 0x1 -#define SPI_MEM_SPI_SMEM_DQS_CA_IN_S 26 - -/* SPI_MEM_SPI_SMEM_HYPERBUS_MODE : R/W ;bitpos:[25] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable the SPI HyperBus mode. */ - -#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE (BIT(25)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_M (BIT(25)) -#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_S 25 - -/* SPI_MEM_SPI_SMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ - -/* Description: Set this bit to enable the differential SPI_CLK#. */ - -#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN (BIT(24)) -#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_M (BIT(24)) -#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_S 24 - -/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[22] ;default: 1'b0 ; */ - -/* Description: When SPI_SMEM_DDR_DQS_LOOP and SPI_SMEM_DDR_EN are set, - * 1: Use internal SPI_CLK as data strobe. - * 0: Use internal ~SPI_CLK as data strobe. Otherwise this bit is not - * active. - */ - -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE (BIT(22)) -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_M (BIT(22)) -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S 22 - -/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */ - -/* Description: - * 1: Use internal signal as data strobe, the strobe can not be delayed by - * input timing module. - * 0: Use input SPI_DQS signal from PAD as data strobe, the strobe can be - * delayed by input timing module - */ - -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP (BIT(21)) -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_M (BIT(21)) -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_S 21 - -/* SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ - -/* Description: The delay number of data strobe which from memory based on - * SPI_CLK. - */ - -#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD 0x0000007F -#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V)<<(SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S)) -#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V 0x7F -#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S 14 - -/* SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ - -/* Description: Set this bit to mask the first or the last byte in MSPI ECC - * DDR read mode, when accesses to external RAM. - */ - -#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN (BIT(13)) -#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_M (BIT(13)) -#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_S 13 - -/* SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ - -/* Description: Set this bit to mask the first or the last byte in MSPI ECC - * DDR write mode, when accesses to external RAM. - */ - -#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN (BIT(12)) -#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_M (BIT(12)) -#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_S 12 - -/* SPI_MEM_SPI_SMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */ - -/* Description: It is the minimum output data length in the ddr psram. */ - -#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN 0x0000007F -#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V)<<(SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S)) -#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V 0x7F -#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S 5 - -/* SPI_MEM_SPI_SMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: the bit is used to disable dual edge in CMD phase when ddr - * mode. - */ - -#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS (BIT(4)) -#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_M (BIT(4)) -#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_S 4 - -/* SPI_MEM_SPI_SMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: Set the bit to reorder tx data of the word in spi ddr mode. */ - -#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP (BIT(3)) -#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_M (BIT(3)) -#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_S 3 - -/* SPI_MEM_SPI_SMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: Set the bit to reorder rx data of the word in spi ddr mode. */ - -#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP (BIT(2)) -#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_M (BIT(2)) -#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S 2 - -/* SPI_MEM_SPI_SMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: Set the bit to enable variable dummy cycle in spi ddr mode. */ - -#define SPI_MEM_SPI_SMEM_VAR_DUMMY (BIT(1)) -#define SPI_MEM_SPI_SMEM_VAR_DUMMY_M (BIT(1)) -#define SPI_MEM_SPI_SMEM_VAR_DUMMY_V 0x1 -#define SPI_MEM_SPI_SMEM_VAR_DUMMY_S 1 - -/* SPI_MEM_SPI_SMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: 1: in ddr mode, 0 in sdr mode */ - -#define SPI_MEM_SPI_SMEM_DDR_EN (BIT(0)) -#define SPI_MEM_SPI_SMEM_DDR_EN_M (BIT(0)) -#define SPI_MEM_SPI_SMEM_DDR_EN_V 0x1 -#define SPI_MEM_SPI_SMEM_DDR_EN_S 0 - -#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0xE8) - -/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ - -/* Description: Register clock gate enable signal. 1: Enable. 0: Disable. */ - -#define SPI_MEM_CLK_EN (BIT(0)) -#define SPI_MEM_CLK_EN_M (BIT(0)) -#define SPI_MEM_CLK_EN_V 0x1 -#define SPI_MEM_CLK_EN_S 0 - -#define SPI_MEM_CORE_CLK_SEL_REG(i) (REG_SPI_MEM_BASE(i) + 0xEC) - -/* SPI_MEM_CORE_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ - -/* Description: When the digital system clock selects PLL clock and the - * frequency of PLL clock is 480MHz, the value of SPI_MEM_CORE_CLK_SEL: - * 0: SPI0/1 module clock (MSPI_CORE_CLK) is 80MHz. - * 1: MSPI_CORE_CLK is 120MHz. - * 2: MSPI_CORE_CLK is 160MHz. - * 3: MSPI_CORE_CLK is 240MHz. When the digital system clock selects PLL - * clock and the frequency of PLL clock is 320MHz, the value of - * SPI_MEM_CORE_CLK_SEL: - * 0: MSPI_CORE_CLK is 80MHz. - * 1: MSPI_CORE_CLK is 80MHz. - * 2: MSPI_CORE_CLK 160MHz. - * 3: Not used. - */ - -#define SPI_MEM_CORE_CLK_SEL 0x00000003 -#define SPI_MEM_CORE_CLK_SEL_M ((SPI_MEM_CORE_CLK_SEL_V)<<(SPI_MEM_CORE_CLK_SEL_S)) -#define SPI_MEM_CORE_CLK_SEL_V 0x3 -#define SPI_MEM_CORE_CLK_SEL_S 0 - -#define SPI_MEM_INT_ENA_REG(i) (REG_SPI_MEM_BASE(i) + 0xF0) - -/* SPI_MEM_ECC_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: The enable bit for SPI_MEM_ECC_ERR_INT interrupt. */ - -#define SPI_MEM_ECC_ERR_INT_ENA (BIT(4)) -#define SPI_MEM_ECC_ERR_INT_ENA_M (BIT(4)) -#define SPI_MEM_ECC_ERR_INT_ENA_V 0x1 -#define SPI_MEM_ECC_ERR_INT_ENA_S 4 - -/* SPI_MEM_BROWN_OUT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: The enable bit for SPI_MEM_BROWN_OUT_INT interrupt. */ - -#define SPI_MEM_BROWN_OUT_INT_ENA (BIT(3)) -#define SPI_MEM_BROWN_OUT_INT_ENA_M (BIT(3)) -#define SPI_MEM_BROWN_OUT_INT_ENA_V 0x1 -#define SPI_MEM_BROWN_OUT_INT_ENA_S 3 - -/* SPI_MEM_TOTAL_TRANS_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: The enable bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. */ - -#define SPI_MEM_TOTAL_TRANS_END_INT_ENA (BIT(2)) -#define SPI_MEM_TOTAL_TRANS_END_INT_ENA_M (BIT(2)) -#define SPI_MEM_TOTAL_TRANS_END_INT_ENA_V 0x1 -#define SPI_MEM_TOTAL_TRANS_END_INT_ENA_S 2 - -/* SPI_MEM_PES_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: The enable bit for SPI_MEM_PES_END_INT interrupt. */ - -#define SPI_MEM_PES_END_INT_ENA (BIT(1)) -#define SPI_MEM_PES_END_INT_ENA_M (BIT(1)) -#define SPI_MEM_PES_END_INT_ENA_V 0x1 -#define SPI_MEM_PES_END_INT_ENA_S 1 - -/* SPI_MEM_PER_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: The enable bit for SPI_MEM_PER_END_INT interrupt. */ - -#define SPI_MEM_PER_END_INT_ENA (BIT(0)) -#define SPI_MEM_PER_END_INT_ENA_M (BIT(0)) -#define SPI_MEM_PER_END_INT_ENA_V 0x1 -#define SPI_MEM_PER_END_INT_ENA_S 0 - -#define SPI_MEM_INT_CLR_REG(i) (REG_SPI_MEM_BASE(i) + 0xF4) - -/* SPI_MEM_ECC_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: The clear bit for SPI_MEM_ECC_ERR_INT interrupt. - * SPI_MEM_ECC_ERR_ADDR and SPI_MEM_ECC_ERR_CNT will be cleared by the pulse - * of this bit. - */ - -#define SPI_MEM_ECC_ERR_INT_CLR (BIT(4)) -#define SPI_MEM_ECC_ERR_INT_CLR_M (BIT(4)) -#define SPI_MEM_ECC_ERR_INT_CLR_V 0x1 -#define SPI_MEM_ECC_ERR_INT_CLR_S 4 - -/* SPI_MEM_BROWN_OUT_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt. */ - -#define SPI_MEM_BROWN_OUT_INT_CLR (BIT(3)) -#define SPI_MEM_BROWN_OUT_INT_CLR_M (BIT(3)) -#define SPI_MEM_BROWN_OUT_INT_CLR_V 0x1 -#define SPI_MEM_BROWN_OUT_INT_CLR_S 3 - -/* SPI_MEM_TOTAL_TRANS_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: The clear bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. */ - -#define SPI_MEM_TOTAL_TRANS_END_INT_CLR (BIT(2)) -#define SPI_MEM_TOTAL_TRANS_END_INT_CLR_M (BIT(2)) -#define SPI_MEM_TOTAL_TRANS_END_INT_CLR_V 0x1 -#define SPI_MEM_TOTAL_TRANS_END_INT_CLR_S 2 - -/* SPI_MEM_PES_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: The clear bit for SPI_MEM_PES_END_INT interrupt. */ - -#define SPI_MEM_PES_END_INT_CLR (BIT(1)) -#define SPI_MEM_PES_END_INT_CLR_M (BIT(1)) -#define SPI_MEM_PES_END_INT_CLR_V 0x1 -#define SPI_MEM_PES_END_INT_CLR_S 1 - -/* SPI_MEM_PER_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: The clear bit for SPI_MEM_PER_END_INT interrupt. */ - -#define SPI_MEM_PER_END_INT_CLR (BIT(0)) -#define SPI_MEM_PER_END_INT_CLR_M (BIT(0)) -#define SPI_MEM_PER_END_INT_CLR_V 0x1 -#define SPI_MEM_PER_END_INT_CLR_S 0 - -#define SPI_MEM_INT_RAW_REG(i) (REG_SPI_MEM_BASE(i) + 0xF8) - -/* SPI_MEM_ECC_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: The raw bit for SPI_MEM_ECC_ERR_INT interrupt. When - * APB_CTRL_FECC_ERR_INT_EN is set and APB_CTRL_SECC_ERR_INT_EN is cleared, - * this bit is triggered when the error times of SPI0/1 ECC read flash are - * equal or bigger than APB_CTRL_ECC_ERR_INT_NUM. - * When APB_CTRL_FECC_ERR_INT_EN is cleared and APB_CTRL_SECC_ERR_INT_EN - * is set, this bit is triggered when the error times of SPI0/1 ECC read - * external RAM are equal or bigger than - * APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and - * APB_CTRL_SECC_ERR_INT_EN are set, this bit is triggered when the total - * error times of SPI0/1 ECC read external RAM and flash are equal or bigger - * than APB_CTRL_ECC_ERR_INT_NUM. When APB_CTRL_FECC_ERR_INT_EN and - * APB_CTRL_SECC_ERR_INT_EN are cleared, this bit will not be triggered. - */ - -#define SPI_MEM_ECC_ERR_INT_RAW (BIT(4)) -#define SPI_MEM_ECC_ERR_INT_RAW_M (BIT(4)) -#define SPI_MEM_ECC_ERR_INT_RAW_V 0x1 -#define SPI_MEM_ECC_ERR_INT_RAW_S 4 - -/* SPI_MEM_BROWN_OUT_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. - * 1: Triggered condition is that chip is loosing power and RTC module sends - * out brown out close flash request to SPI1. After SPI1 sends out suspend - * command to flash, this interrupt is triggered and MSPI returns to idle - * state. - * 0: Others. - */ - -#define SPI_MEM_BROWN_OUT_INT_RAW (BIT(3)) -#define SPI_MEM_BROWN_OUT_INT_RAW_M (BIT(3)) -#define SPI_MEM_BROWN_OUT_INT_RAW_V 0x1 -#define SPI_MEM_BROWN_OUT_INT_RAW_S 3 - -/* SPI_MEM_TOTAL_TRANS_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: The raw bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. - * 1: Triggered when SPI1 transfer is done and flash is already idle. When - * WRSR/PP/SE/BE/CE is sent and PES/PER command is sent, this bit is set when - * WRSR/PP/SE/BE/CE is success. - * 0: Others. - */ - -#define SPI_MEM_TOTAL_TRANS_END_INT_RAW (BIT(2)) -#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_M (BIT(2)) -#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_V 0x1 -#define SPI_MEM_TOTAL_TRANS_END_INT_RAW_S 2 - -/* SPI_MEM_PES_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: The raw bit for SPI_MEM_PES_END_INT interrupt. - * 1: Triggered when Auto Suspend command (0x75) is sent and flash is - * suspended successfully. - * 0: Others. - */ - -#define SPI_MEM_PES_END_INT_RAW (BIT(1)) -#define SPI_MEM_PES_END_INT_RAW_M (BIT(1)) -#define SPI_MEM_PES_END_INT_RAW_V 0x1 -#define SPI_MEM_PES_END_INT_RAW_S 1 - -/* SPI_MEM_PER_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: The raw bit for SPI_MEM_PER_END_INT interrupt. - * 1: Triggered when Auto Resume command (0x7A) is sent and flash is - * resumed successfully. - * 0: Others. - */ - -#define SPI_MEM_PER_END_INT_RAW (BIT(0)) -#define SPI_MEM_PER_END_INT_RAW_M (BIT(0)) -#define SPI_MEM_PER_END_INT_RAW_V 0x1 -#define SPI_MEM_PER_END_INT_RAW_S 0 - -#define SPI_MEM_INT_ST_REG(i) (REG_SPI_MEM_BASE(i) + 0xFC) - -/* SPI_MEM_ECC_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: The status bit for SPI_MEM_ECC_ERR_INT interrupt. */ - -#define SPI_MEM_ECC_ERR_INT_ST (BIT(4)) -#define SPI_MEM_ECC_ERR_INT_ST_M (BIT(4)) -#define SPI_MEM_ECC_ERR_INT_ST_V 0x1 -#define SPI_MEM_ECC_ERR_INT_ST_S 4 - -/* SPI_MEM_BROWN_OUT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: The status bit for SPI_MEM_BROWN_OUT_INT interrupt. */ - -#define SPI_MEM_BROWN_OUT_INT_ST (BIT(3)) -#define SPI_MEM_BROWN_OUT_INT_ST_M (BIT(3)) -#define SPI_MEM_BROWN_OUT_INT_ST_V 0x1 -#define SPI_MEM_BROWN_OUT_INT_ST_S 3 - -/* SPI_MEM_TOTAL_TRANS_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: The status bit for SPI_MEM_TOTAL_TRANS_END_INT interrupt. */ - -#define SPI_MEM_TOTAL_TRANS_END_INT_ST (BIT(2)) -#define SPI_MEM_TOTAL_TRANS_END_INT_ST_M (BIT(2)) -#define SPI_MEM_TOTAL_TRANS_END_INT_ST_V 0x1 -#define SPI_MEM_TOTAL_TRANS_END_INT_ST_S 2 - -/* SPI_MEM_PES_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: The status bit for SPI_MEM_PES_END_INT interrupt. */ - -#define SPI_MEM_PES_END_INT_ST (BIT(1)) -#define SPI_MEM_PES_END_INT_ST_M (BIT(1)) -#define SPI_MEM_PES_END_INT_ST_V 0x1 -#define SPI_MEM_PES_END_INT_ST_S 1 - -/* SPI_MEM_PER_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: The status bit for SPI_MEM_PER_END_INT interrupt. */ - -#define SPI_MEM_PER_END_INT_ST (BIT(0)) -#define SPI_MEM_PER_END_INT_ST_M (BIT(0)) -#define SPI_MEM_PER_END_INT_ST_V 0x1 -#define SPI_MEM_PER_END_INT_ST_S 0 - -#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3FC) - -/* SPI_MEM_DATE : R/W ;bitpos:[27:5] ;default: 23'h108082 ; */ - -/* Description: SPI register version. */ - -#define SPI_MEM_DATE 0x007FFFFF -#define SPI_MEM_DATE_M ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S)) -#define SPI_MEM_DATE_V 0x7FFFFF -#define SPI_MEM_DATE_S 5 - -/* SPI_MEM_SPICLK_PAD_DRV_CTL_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: SPI_CLK PAD driver control signal. - * 1: The driver of SPI_CLK PAD is controlled by the bits - * SPI_FMEM_SPICLK_FUN_DRV[1:0] and SPI_SMEM_SPICLK_FUN_DRV[1:0]. - * 0: The driver of SPI_CLK PAD is controlled by the bits - * IO_MUX_FUNC_DRV[1:0] of SPICLK PAD. - */ - -#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN (BIT(4)) -#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_M (BIT(4)) -#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_V 0x1 -#define SPI_MEM_SPICLK_PAD_DRV_CTL_EN_S 4 - -/* SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ - -/* Description: The driver of SPI_CLK PAD is controlled by the bits - * SPI_FMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN - * is set and MSPI accesses to flash. - */ - -#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV 0x00000003 -#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_M ((SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_V) << \ - (SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_S)) -#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_V 0x3 -#define SPI_MEM_SPI_FMEM_SPICLK_FUN_DRV_S 2 - -/* SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ - -/* Description: The driver of SPI_CLK PAD is controlled by the bits - * SPI_SMEM_SPICLK_FUN_DRV[1:0] when the bit SPI_SPICLK_PAD_DRV_CTL_EN - * is set and MSPI accesses to external RAM. - */ - -#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV 0x00000003 -#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_M ((SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V)<<(SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_S)) -#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_V 0x3 -#define SPI_MEM_SPI_SMEM_SPICLK_FUN_DRV_S 0 - -#ifdef __cplusplus -} -#endif - -#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SPI_MEM_REG_H */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_system.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_system.h index a207e931d8611..d11f3418338f8 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_system.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_system.h @@ -27,1731 +27,6 @@ #include "esp32s3_soc.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* SYSTEM_CORE_1_CONTROL_0_REG register - * Core0 control regiter 0 - */ - -#define SYSTEM_CORE_1_CONTROL_0_REG (DR_REG_SYSTEM_BASE + 0x0) - -/* SYSTEM_CONTROL_CORE_1_RESETING : R/W; bitpos: [2]; default: 1; - * Set 1 to let core1 reset - */ - -#define SYSTEM_CONTROL_CORE_1_RESETING (BIT(2)) -#define SYSTEM_CONTROL_CORE_1_RESETING_M (SYSTEM_CONTROL_CORE_1_RESETING_V << SYSTEM_CONTROL_CORE_1_RESETING_S) -#define SYSTEM_CONTROL_CORE_1_RESETING_V 0x00000001 -#define SYSTEM_CONTROL_CORE_1_RESETING_S 2 - -/* SYSTEM_CONTROL_CORE_1_CLKGATE_EN : R/W; bitpos: [1]; default: 0; - * Set 1 to open core1 clock - */ - -#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN (BIT(1)) -#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_M (SYSTEM_CONTROL_CORE_1_CLKGATE_EN_V << SYSTEM_CONTROL_CORE_1_CLKGATE_EN_S) -#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_V 0x00000001 -#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_S 1 - -/* SYSTEM_CONTROL_CORE_1_RUNSTALL : R/W; bitpos: [0]; default: 0; - * Set 1 to stall core1 - */ - -#define SYSTEM_CONTROL_CORE_1_RUNSTALL (BIT(0)) -#define SYSTEM_CONTROL_CORE_1_RUNSTALL_M (SYSTEM_CONTROL_CORE_1_RUNSTALL_V << SYSTEM_CONTROL_CORE_1_RUNSTALL_S) -#define SYSTEM_CONTROL_CORE_1_RUNSTALL_V 0x00000001 -#define SYSTEM_CONTROL_CORE_1_RUNSTALL_S 0 - -/* SYSTEM_CORE_1_CONTROL_1_REG register - * Core0 control regiter 1 - */ - -#define SYSTEM_CORE_1_CONTROL_1_REG (DR_REG_SYSTEM_BASE + 0x4) - -/* SYSTEM_CONTROL_CORE_1_MESSAGE : R/W; bitpos: [31:0]; default: 0; - * it's only a R/W register, no function, software can write any value - */ - -#define SYSTEM_CONTROL_CORE_1_MESSAGE 0xffffffff -#define SYSTEM_CONTROL_CORE_1_MESSAGE_M (SYSTEM_CONTROL_CORE_1_MESSAGE_V << SYSTEM_CONTROL_CORE_1_MESSAGE_S) -#define SYSTEM_CONTROL_CORE_1_MESSAGE_V 0xffffffff -#define SYSTEM_CONTROL_CORE_1_MESSAGE_S 0 - -/* SYSTEM_CPU_PERI_CLK_EN_REG register - * cpu_peripheral clock configuration register - */ - -#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x8) - -/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W; bitpos: [7]; default: 0; - * Set 1 to open dedicated_gpio module clk - */ - -#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7)) -#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (SYSTEM_CLK_EN_DEDICATED_GPIO_V << SYSTEM_CLK_EN_DEDICATED_GPIO_S) -#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x00000001 -#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7 - -/* SYSTEM_CLK_EN_ASSIST_DEBUG : R/W; bitpos: [6]; default: 0; - * Set 1 to open assist_debug module clock - */ - -#define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6)) -#define SYSTEM_CLK_EN_ASSIST_DEBUG_M (SYSTEM_CLK_EN_ASSIST_DEBUG_V << SYSTEM_CLK_EN_ASSIST_DEBUG_S) -#define SYSTEM_CLK_EN_ASSIST_DEBUG_V 0x00000001 -#define SYSTEM_CLK_EN_ASSIST_DEBUG_S 6 - -/* SYSTEM_CPU_PERI_RST_EN_REG register - * cpu_peripheral reset configuration regsiter - */ - -#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0xc) - -/* SYSTEM_RST_EN_DEDICATED_GPIO : R/W; bitpos: [7]; default: 1; - * Set 1 to let dedicated_gpio module reset - */ - -#define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7)) -#define SYSTEM_RST_EN_DEDICATED_GPIO_M (SYSTEM_RST_EN_DEDICATED_GPIO_V << SYSTEM_RST_EN_DEDICATED_GPIO_S) -#define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x00000001 -#define SYSTEM_RST_EN_DEDICATED_GPIO_S 7 - -/* SYSTEM_RST_EN_ASSIST_DEBUG : R/W; bitpos: [6]; default: 1; - * Set 1 to let assist_debug module reset - */ - -#define SYSTEM_RST_EN_ASSIST_DEBUG (BIT(6)) -#define SYSTEM_RST_EN_ASSIST_DEBUG_M (SYSTEM_RST_EN_ASSIST_DEBUG_V << SYSTEM_RST_EN_ASSIST_DEBUG_S) -#define SYSTEM_RST_EN_ASSIST_DEBUG_V 0x00000001 -#define SYSTEM_RST_EN_ASSIST_DEBUG_S 6 - -/* SYSTEM_CPU_PER_CONF_REG register - * cpu peripheral clock configuration register - */ - -#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x10) - -/* SYSTEM_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0; - * This field used to set delay cycle when cpu enter waiti mode, after delay - * waiti_clk will close - */ - -#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000f -#define SYSTEM_CPU_WAITI_DELAY_NUM_M (SYSTEM_CPU_WAITI_DELAY_NUM_V << SYSTEM_CPU_WAITI_DELAY_NUM_S) -#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0x0000000f -#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4 - -/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1; - * Set 1 to force cpu_waiti_clk enable. - */ - -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3)) -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (SYSTEM_CPU_WAIT_MODE_FORCE_ON_V << SYSTEM_CPU_WAIT_MODE_FORCE_ON_S) -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x00000001 -#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3 - -/* SYSTEM_PLL_FREQ_SEL : R/W; bitpos: [2]; default: 1; - * This field used to sel pll frequent. - */ - -#define SYSTEM_PLL_FREQ_SEL (BIT(2)) -#define SYSTEM_PLL_FREQ_SEL_M (SYSTEM_PLL_FREQ_SEL_V << SYSTEM_PLL_FREQ_SEL_S) -#define SYSTEM_PLL_FREQ_SEL_V 0x00000001 -#define SYSTEM_PLL_FREQ_SEL_S 2 - -/* SYSTEM_CPUPERIOD_SEL : R/W; bitpos: [1:0]; default: 0; - * This field used to sel cpu clock frequent. - */ - -#define SYSTEM_CPUPERIOD_SEL 0x00000003 -#define SYSTEM_CPUPERIOD_SEL_M (SYSTEM_CPUPERIOD_SEL_V << SYSTEM_CPUPERIOD_SEL_S) -#define SYSTEM_CPUPERIOD_SEL_V 0x00000003 -#define SYSTEM_CPUPERIOD_SEL_S 0 - -/* SYSTEM_MEM_PD_MASK_REG register - * memory power down mask configuration register - */ - -#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x14) - -/* SYSTEM_LSLP_MEM_PD_MASK : R/W; bitpos: [0]; default: 1; - * Set 1 to mask memory power down. - */ - -#define SYSTEM_LSLP_MEM_PD_MASK (BIT(0)) -#define SYSTEM_LSLP_MEM_PD_MASK_M (SYSTEM_LSLP_MEM_PD_MASK_V << SYSTEM_LSLP_MEM_PD_MASK_S) -#define SYSTEM_LSLP_MEM_PD_MASK_V 0x00000001 -#define SYSTEM_LSLP_MEM_PD_MASK_S 0 - -/* SYSTEM_PERIP_CLK_EN0_REG register - * peripheral clock configuration regsiter 0 - */ - -#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x18) - -/* SYSTEM_SPI4_CLK_EN : R/W; bitpos: [31]; default: 1; - * Set 1 to enable SPI4 clock - */ - -#define SYSTEM_SPI4_CLK_EN (BIT(31)) -#define SYSTEM_SPI4_CLK_EN_M (SYSTEM_SPI4_CLK_EN_V << SYSTEM_SPI4_CLK_EN_S) -#define SYSTEM_SPI4_CLK_EN_V 0x00000001 -#define SYSTEM_SPI4_CLK_EN_S 31 - -/* SYSTEM_ADC2_ARB_CLK_EN : R/W; bitpos: [30]; default: 1; - * Set 1 to enable ADC2_ARB clock - */ - -#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) -#define SYSTEM_ADC2_ARB_CLK_EN_M (SYSTEM_ADC2_ARB_CLK_EN_V << SYSTEM_ADC2_ARB_CLK_EN_S) -#define SYSTEM_ADC2_ARB_CLK_EN_V 0x00000001 -#define SYSTEM_ADC2_ARB_CLK_EN_S 30 - -/* SYSTEM_SYSTIMER_CLK_EN : R/W; bitpos: [29]; default: 1; - * Set 1 to enable SYSTEMTIMER clock - */ - -#define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) -#define SYSTEM_SYSTIMER_CLK_EN_M (SYSTEM_SYSTIMER_CLK_EN_V << SYSTEM_SYSTIMER_CLK_EN_S) -#define SYSTEM_SYSTIMER_CLK_EN_V 0x00000001 -#define SYSTEM_SYSTIMER_CLK_EN_S 29 - -/* SYSTEM_APB_SARADC_CLK_EN : R/W; bitpos: [28]; default: 1; - * Set 1 to enable APB_SARADC clock - */ - -#define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) -#define SYSTEM_APB_SARADC_CLK_EN_M (SYSTEM_APB_SARADC_CLK_EN_V << SYSTEM_APB_SARADC_CLK_EN_S) -#define SYSTEM_APB_SARADC_CLK_EN_V 0x00000001 -#define SYSTEM_APB_SARADC_CLK_EN_S 28 - -/* SYSTEM_SPI3_DMA_CLK_EN : R/W; bitpos: [27]; default: 1; - * Set 1 to enable SPI4 clock - */ - -#define SYSTEM_SPI3_DMA_CLK_EN (BIT(27)) -#define SYSTEM_SPI3_DMA_CLK_EN_M (SYSTEM_SPI3_DMA_CLK_EN_V << SYSTEM_SPI3_DMA_CLK_EN_S) -#define SYSTEM_SPI3_DMA_CLK_EN_V 0x00000001 -#define SYSTEM_SPI3_DMA_CLK_EN_S 27 - -/* SYSTEM_PWM3_CLK_EN : R/W; bitpos: [26]; default: 0; - * Set 1 to enable PWM3 clock - */ - -#define SYSTEM_PWM3_CLK_EN (BIT(26)) -#define SYSTEM_PWM3_CLK_EN_M (SYSTEM_PWM3_CLK_EN_V << SYSTEM_PWM3_CLK_EN_S) -#define SYSTEM_PWM3_CLK_EN_V 0x00000001 -#define SYSTEM_PWM3_CLK_EN_S 26 - -/* SYSTEM_PWM2_CLK_EN : R/W; bitpos: [25]; default: 0; - * Set 1 to enable PWM2 clock - */ - -#define SYSTEM_PWM2_CLK_EN (BIT(25)) -#define SYSTEM_PWM2_CLK_EN_M (SYSTEM_PWM2_CLK_EN_V << SYSTEM_PWM2_CLK_EN_S) -#define SYSTEM_PWM2_CLK_EN_V 0x00000001 -#define SYSTEM_PWM2_CLK_EN_S 25 - -/* SYSTEM_UART_MEM_CLK_EN : R/W; bitpos: [24]; default: 1; - * Set 1 to enable UART_MEM clock - */ - -#define SYSTEM_UART_MEM_CLK_EN (BIT(24)) -#define SYSTEM_UART_MEM_CLK_EN_M (SYSTEM_UART_MEM_CLK_EN_V << SYSTEM_UART_MEM_CLK_EN_S) -#define SYSTEM_UART_MEM_CLK_EN_V 0x00000001 -#define SYSTEM_UART_MEM_CLK_EN_S 24 - -/* SYSTEM_USB_CLK_EN : R/W; bitpos: [23]; default: 1; - * Set 1 to enable USB clock - */ - -#define SYSTEM_USB_CLK_EN (BIT(23)) -#define SYSTEM_USB_CLK_EN_M (SYSTEM_USB_CLK_EN_V << SYSTEM_USB_CLK_EN_S) -#define SYSTEM_USB_CLK_EN_V 0x00000001 -#define SYSTEM_USB_CLK_EN_S 23 - -/* SYSTEM_SPI2_DMA_CLK_EN : R/W; bitpos: [22]; default: 1; - * Set 1 to enable SPI2_DMA clock - */ - -#define SYSTEM_SPI2_DMA_CLK_EN (BIT(22)) -#define SYSTEM_SPI2_DMA_CLK_EN_M (SYSTEM_SPI2_DMA_CLK_EN_V << SYSTEM_SPI2_DMA_CLK_EN_S) -#define SYSTEM_SPI2_DMA_CLK_EN_V 0x00000001 -#define SYSTEM_SPI2_DMA_CLK_EN_S 22 - -/* SYSTEM_I2S1_CLK_EN : R/W; bitpos: [21]; default: 0; - * Set 1 to enable I2S1 clock - */ - -#define SYSTEM_I2S1_CLK_EN (BIT(21)) -#define SYSTEM_I2S1_CLK_EN_M (SYSTEM_I2S1_CLK_EN_V << SYSTEM_I2S1_CLK_EN_S) -#define SYSTEM_I2S1_CLK_EN_V 0x00000001 -#define SYSTEM_I2S1_CLK_EN_S 21 - -/* SYSTEM_PWM1_CLK_EN : R/W; bitpos: [20]; default: 0; - * Set 1 to enable PWM1 clock - */ - -#define SYSTEM_PWM1_CLK_EN (BIT(20)) -#define SYSTEM_PWM1_CLK_EN_M (SYSTEM_PWM1_CLK_EN_V << SYSTEM_PWM1_CLK_EN_S) -#define SYSTEM_PWM1_CLK_EN_V 0x00000001 -#define SYSTEM_PWM1_CLK_EN_S 20 - -/* SYSTEM_TWAI_CLK_EN : R/W; bitpos: [19]; default: 0; - * Set 1 to enable TWAI clock - */ - -#define SYSTEM_TWAI_CLK_EN (BIT(19)) -#define SYSTEM_TWAI_CLK_EN_M (SYSTEM_TWAI_CLK_EN_V << SYSTEM_TWAI_CLK_EN_S) -#define SYSTEM_TWAI_CLK_EN_V 0x00000001 -#define SYSTEM_TWAI_CLK_EN_S 19 - -/* SYSTEM_I2C_EXT1_CLK_EN : R/W; bitpos: [18]; default: 0; - * Set 1 to enable I2C_EXT1 clock - */ - -#define SYSTEM_I2C_EXT1_CLK_EN (BIT(18)) -#define SYSTEM_I2C_EXT1_CLK_EN_M (SYSTEM_I2C_EXT1_CLK_EN_V << SYSTEM_I2C_EXT1_CLK_EN_S) -#define SYSTEM_I2C_EXT1_CLK_EN_V 0x00000001 -#define SYSTEM_I2C_EXT1_CLK_EN_S 18 - -/* SYSTEM_PWM0_CLK_EN : R/W; bitpos: [17]; default: 0; - * Set 1 to enable PWM0 clock - */ - -#define SYSTEM_PWM0_CLK_EN (BIT(17)) -#define SYSTEM_PWM0_CLK_EN_M (SYSTEM_PWM0_CLK_EN_V << SYSTEM_PWM0_CLK_EN_S) -#define SYSTEM_PWM0_CLK_EN_V 0x00000001 -#define SYSTEM_PWM0_CLK_EN_S 17 - -/* SYSTEM_SPI3_CLK_EN : R/W; bitpos: [16]; default: 1; - * Set 1 to enable SPI3 clock - */ - -#define SYSTEM_SPI3_CLK_EN (BIT(16)) -#define SYSTEM_SPI3_CLK_EN_M (SYSTEM_SPI3_CLK_EN_V << SYSTEM_SPI3_CLK_EN_S) -#define SYSTEM_SPI3_CLK_EN_V 0x00000001 -#define SYSTEM_SPI3_CLK_EN_S 16 - -/* SYSTEM_TIMERGROUP1_CLK_EN : R/W; bitpos: [15]; default: 1; - * Set 1 to enable TIMERGROUP1 clock - */ - -#define SYSTEM_TIMERGROUP1_CLK_EN (BIT(15)) -#define SYSTEM_TIMERGROUP1_CLK_EN_M (SYSTEM_TIMERGROUP1_CLK_EN_V << SYSTEM_TIMERGROUP1_CLK_EN_S) -#define SYSTEM_TIMERGROUP1_CLK_EN_V 0x00000001 -#define SYSTEM_TIMERGROUP1_CLK_EN_S 15 - -/* SYSTEM_EFUSE_CLK_EN : R/W; bitpos: [14]; default: 1; - * Set 1 to enable EFUSE clock - */ - -#define SYSTEM_EFUSE_CLK_EN (BIT(14)) -#define SYSTEM_EFUSE_CLK_EN_M (SYSTEM_EFUSE_CLK_EN_V << SYSTEM_EFUSE_CLK_EN_S) -#define SYSTEM_EFUSE_CLK_EN_V 0x00000001 -#define SYSTEM_EFUSE_CLK_EN_S 14 - -/* SYSTEM_TIMERGROUP_CLK_EN : R/W; bitpos: [13]; default: 1; - * Set 1 to enable TIMERGROUP clock - */ - -#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) -#define SYSTEM_TIMERGROUP_CLK_EN_M (SYSTEM_TIMERGROUP_CLK_EN_V << SYSTEM_TIMERGROUP_CLK_EN_S) -#define SYSTEM_TIMERGROUP_CLK_EN_V 0x00000001 -#define SYSTEM_TIMERGROUP_CLK_EN_S 13 - -/* SYSTEM_UHCI1_CLK_EN : R/W; bitpos: [12]; default: 0; - * Set 1 to enable UHCI1 clock - */ - -#define SYSTEM_UHCI1_CLK_EN (BIT(12)) -#define SYSTEM_UHCI1_CLK_EN_M (SYSTEM_UHCI1_CLK_EN_V << SYSTEM_UHCI1_CLK_EN_S) -#define SYSTEM_UHCI1_CLK_EN_V 0x00000001 -#define SYSTEM_UHCI1_CLK_EN_S 12 - -/* SYSTEM_LEDC_CLK_EN : R/W; bitpos: [11]; default: 0; - * Set 1 to enable LEDC clock - */ - -#define SYSTEM_LEDC_CLK_EN (BIT(11)) -#define SYSTEM_LEDC_CLK_EN_M (SYSTEM_LEDC_CLK_EN_V << SYSTEM_LEDC_CLK_EN_S) -#define SYSTEM_LEDC_CLK_EN_V 0x00000001 -#define SYSTEM_LEDC_CLK_EN_S 11 - -/* SYSTEM_PCNT_CLK_EN : R/W; bitpos: [10]; default: 0; - * Set 1 to enable PCNT clock - */ - -#define SYSTEM_PCNT_CLK_EN (BIT(10)) -#define SYSTEM_PCNT_CLK_EN_M (SYSTEM_PCNT_CLK_EN_V << SYSTEM_PCNT_CLK_EN_S) -#define SYSTEM_PCNT_CLK_EN_V 0x00000001 -#define SYSTEM_PCNT_CLK_EN_S 10 - -/* SYSTEM_RMT_CLK_EN : R/W; bitpos: [9]; default: 0; - * Set 1 to enable RMT clock - */ - -#define SYSTEM_RMT_CLK_EN (BIT(9)) -#define SYSTEM_RMT_CLK_EN_M (SYSTEM_RMT_CLK_EN_V << SYSTEM_RMT_CLK_EN_S) -#define SYSTEM_RMT_CLK_EN_V 0x00000001 -#define SYSTEM_RMT_CLK_EN_S 9 - -/* SYSTEM_UHCI0_CLK_EN : R/W; bitpos: [8]; default: 0; - * Set 1 to enable UHCI0 clock - */ - -#define SYSTEM_UHCI0_CLK_EN (BIT(8)) -#define SYSTEM_UHCI0_CLK_EN_M (SYSTEM_UHCI0_CLK_EN_V << SYSTEM_UHCI0_CLK_EN_S) -#define SYSTEM_UHCI0_CLK_EN_V 0x00000001 -#define SYSTEM_UHCI0_CLK_EN_S 8 - -/* SYSTEM_I2C_EXT0_CLK_EN : R/W; bitpos: [7]; default: 0; - * Set 1 to enable I2C_EXT0 clock - */ - -#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) -#define SYSTEM_I2C_EXT0_CLK_EN_M (SYSTEM_I2C_EXT0_CLK_EN_V << SYSTEM_I2C_EXT0_CLK_EN_S) -#define SYSTEM_I2C_EXT0_CLK_EN_V 0x00000001 -#define SYSTEM_I2C_EXT0_CLK_EN_S 7 - -/* SYSTEM_SPI2_CLK_EN : R/W; bitpos: [6]; default: 1; - * Set 1 to enable SPI2 clock - */ - -#define SYSTEM_SPI2_CLK_EN (BIT(6)) -#define SYSTEM_SPI2_CLK_EN_M (SYSTEM_SPI2_CLK_EN_V << SYSTEM_SPI2_CLK_EN_S) -#define SYSTEM_SPI2_CLK_EN_V 0x00000001 -#define SYSTEM_SPI2_CLK_EN_S 6 - -/* SYSTEM_UART1_CLK_EN : R/W; bitpos: [5]; default: 1; - * Set 1 to enable UART1 clock - */ - -#define SYSTEM_UART1_CLK_EN (BIT(5)) -#define SYSTEM_UART1_CLK_EN_M (SYSTEM_UART1_CLK_EN_V << SYSTEM_UART1_CLK_EN_S) -#define SYSTEM_UART1_CLK_EN_V 0x00000001 -#define SYSTEM_UART1_CLK_EN_S 5 - -/* SYSTEM_I2S0_CLK_EN : R/W; bitpos: [4]; default: 0; - * Set 1 to enable I2S0 clock - */ - -#define SYSTEM_I2S0_CLK_EN (BIT(4)) -#define SYSTEM_I2S0_CLK_EN_M (SYSTEM_I2S0_CLK_EN_V << SYSTEM_I2S0_CLK_EN_S) -#define SYSTEM_I2S0_CLK_EN_V 0x00000001 -#define SYSTEM_I2S0_CLK_EN_S 4 - -/* SYSTEM_WDG_CLK_EN : R/W; bitpos: [3]; default: 1; - * Set 1 to enable WDG clock - */ - -#define SYSTEM_WDG_CLK_EN (BIT(3)) -#define SYSTEM_WDG_CLK_EN_M (SYSTEM_WDG_CLK_EN_V << SYSTEM_WDG_CLK_EN_S) -#define SYSTEM_WDG_CLK_EN_V 0x00000001 -#define SYSTEM_WDG_CLK_EN_S 3 - -/* SYSTEM_UART_CLK_EN : R/W; bitpos: [2]; default: 1; - * Set 1 to enable UART clock - */ - -#define SYSTEM_UART_CLK_EN (BIT(2)) -#define SYSTEM_UART_CLK_EN_M (SYSTEM_UART_CLK_EN_V << SYSTEM_UART_CLK_EN_S) -#define SYSTEM_UART_CLK_EN_V 0x00000001 -#define SYSTEM_UART_CLK_EN_S 2 - -/* SYSTEM_SPI01_CLK_EN : R/W; bitpos: [1]; default: 1; - * Set 1 to enable SPI01 clock - */ - -#define SYSTEM_SPI01_CLK_EN (BIT(1)) -#define SYSTEM_SPI01_CLK_EN_M (SYSTEM_SPI01_CLK_EN_V << SYSTEM_SPI01_CLK_EN_S) -#define SYSTEM_SPI01_CLK_EN_V 0x00000001 -#define SYSTEM_SPI01_CLK_EN_S 1 - -/* SYSTEM_TIMERS_CLK_EN : R/W; bitpos: [0]; default: 1; - * Set 1 to enable TIMERS clock - */ - -#define SYSTEM_TIMERS_CLK_EN (BIT(0)) -#define SYSTEM_TIMERS_CLK_EN_M (SYSTEM_TIMERS_CLK_EN_V << SYSTEM_TIMERS_CLK_EN_S) -#define SYSTEM_TIMERS_CLK_EN_V 0x00000001 -#define SYSTEM_TIMERS_CLK_EN_S 0 - -/* SYSTEM_PERIP_CLK_EN1_REG register - * peripheral clock configuration regsiter 1 - */ - -#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x1c) - -/* SYSTEM_USB_DEVICE_CLK_EN : R/W; bitpos: [10]; default: 1; - * Set 1 to enable USB_DEVICE clock - */ - -#define SYSTEM_USB_DEVICE_CLK_EN (BIT(10)) -#define SYSTEM_USB_DEVICE_CLK_EN_M (SYSTEM_USB_DEVICE_CLK_EN_V << SYSTEM_USB_DEVICE_CLK_EN_S) -#define SYSTEM_USB_DEVICE_CLK_EN_V 0x00000001 -#define SYSTEM_USB_DEVICE_CLK_EN_S 10 - -/* SYSTEM_UART2_CLK_EN : R/W; bitpos: [9]; default: 1; - * Set 1 to enable UART2 clock - */ - -#define SYSTEM_UART2_CLK_EN (BIT(9)) -#define SYSTEM_UART2_CLK_EN_M (SYSTEM_UART2_CLK_EN_V << SYSTEM_UART2_CLK_EN_S) -#define SYSTEM_UART2_CLK_EN_V 0x00000001 -#define SYSTEM_UART2_CLK_EN_S 9 - -/* SYSTEM_LCD_CAM_CLK_EN : R/W; bitpos: [8]; default: 0; - * Set 1 to enable LCD_CAM clock - */ - -#define SYSTEM_LCD_CAM_CLK_EN (BIT(8)) -#define SYSTEM_LCD_CAM_CLK_EN_M (SYSTEM_LCD_CAM_CLK_EN_V << SYSTEM_LCD_CAM_CLK_EN_S) -#define SYSTEM_LCD_CAM_CLK_EN_V 0x00000001 -#define SYSTEM_LCD_CAM_CLK_EN_S 8 - -/* SYSTEM_SDIO_HOST_CLK_EN : R/W; bitpos: [7]; default: 0; - * Set 1 to enable SDIO_HOST clock - */ - -#define SYSTEM_SDIO_HOST_CLK_EN (BIT(7)) -#define SYSTEM_SDIO_HOST_CLK_EN_M (SYSTEM_SDIO_HOST_CLK_EN_V << SYSTEM_SDIO_HOST_CLK_EN_S) -#define SYSTEM_SDIO_HOST_CLK_EN_V 0x00000001 -#define SYSTEM_SDIO_HOST_CLK_EN_S 7 - -/* SYSTEM_DMA_CLK_EN : R/W; bitpos: [6]; default: 0; - * Set 1 to enable DMA clock - */ - -#define SYSTEM_DMA_CLK_EN (BIT(6)) -#define SYSTEM_DMA_CLK_EN_M (SYSTEM_DMA_CLK_EN_V << SYSTEM_DMA_CLK_EN_S) -#define SYSTEM_DMA_CLK_EN_V 0x00000001 -#define SYSTEM_DMA_CLK_EN_S 6 - -/* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W; bitpos: [5]; default: 0; - * Set 1 to enable HMAC clock - */ - -#define SYSTEM_CRYPTO_HMAC_CLK_EN (BIT(5)) -#define SYSTEM_CRYPTO_HMAC_CLK_EN_M (SYSTEM_CRYPTO_HMAC_CLK_EN_V << SYSTEM_CRYPTO_HMAC_CLK_EN_S) -#define SYSTEM_CRYPTO_HMAC_CLK_EN_V 0x00000001 -#define SYSTEM_CRYPTO_HMAC_CLK_EN_S 5 - -/* SYSTEM_CRYPTO_DS_CLK_EN : R/W; bitpos: [4]; default: 0; - * Set 1 to enable DS clock - */ - -#define SYSTEM_CRYPTO_DS_CLK_EN (BIT(4)) -#define SYSTEM_CRYPTO_DS_CLK_EN_M (SYSTEM_CRYPTO_DS_CLK_EN_V << SYSTEM_CRYPTO_DS_CLK_EN_S) -#define SYSTEM_CRYPTO_DS_CLK_EN_V 0x00000001 -#define SYSTEM_CRYPTO_DS_CLK_EN_S 4 - -/* SYSTEM_CRYPTO_RSA_CLK_EN : R/W; bitpos: [3]; default: 0; - * Set 1 to enable RSA clock - */ - -#define SYSTEM_CRYPTO_RSA_CLK_EN (BIT(3)) -#define SYSTEM_CRYPTO_RSA_CLK_EN_M (SYSTEM_CRYPTO_RSA_CLK_EN_V << SYSTEM_CRYPTO_RSA_CLK_EN_S) -#define SYSTEM_CRYPTO_RSA_CLK_EN_V 0x00000001 -#define SYSTEM_CRYPTO_RSA_CLK_EN_S 3 - -/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W; bitpos: [2]; default: 0; - * Set 1 to enable SHA clock - */ - -#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) -#define SYSTEM_CRYPTO_SHA_CLK_EN_M (SYSTEM_CRYPTO_SHA_CLK_EN_V << SYSTEM_CRYPTO_SHA_CLK_EN_S) -#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x00000001 -#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 - -/* SYSTEM_CRYPTO_AES_CLK_EN : R/W; bitpos: [1]; default: 0; - * Set 1 to enable AES clock - */ - -#define SYSTEM_CRYPTO_AES_CLK_EN (BIT(1)) -#define SYSTEM_CRYPTO_AES_CLK_EN_M (SYSTEM_CRYPTO_AES_CLK_EN_V << SYSTEM_CRYPTO_AES_CLK_EN_S) -#define SYSTEM_CRYPTO_AES_CLK_EN_V 0x00000001 -#define SYSTEM_CRYPTO_AES_CLK_EN_S 1 - -/* SYSTEM_PERI_BACKUP_CLK_EN : R/W; bitpos: [0]; default: 0; - * Set 1 to enable BACKUP clock - */ - -#define SYSTEM_PERI_BACKUP_CLK_EN (BIT(0)) -#define SYSTEM_PERI_BACKUP_CLK_EN_M (SYSTEM_PERI_BACKUP_CLK_EN_V << SYSTEM_PERI_BACKUP_CLK_EN_S) -#define SYSTEM_PERI_BACKUP_CLK_EN_V 0x00000001 -#define SYSTEM_PERI_BACKUP_CLK_EN_S 0 - -/* SYSTEM_PERIP_RST_EN0_REG register - * peripheral reset configuration register0 - */ - -#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x20) - -/* SYSTEM_SPI4_RST : R/W; bitpos: [31]; default: 0; - * Set 1 to let SPI4 reset - */ - -#define SYSTEM_SPI4_RST (BIT(31)) -#define SYSTEM_SPI4_RST_M (SYSTEM_SPI4_RST_V << SYSTEM_SPI4_RST_S) -#define SYSTEM_SPI4_RST_V 0x00000001 -#define SYSTEM_SPI4_RST_S 31 - -/* SYSTEM_ADC2_ARB_RST : R/W; bitpos: [30]; default: 0; - * Set 1 to let ADC2_ARB reset - */ - -#define SYSTEM_ADC2_ARB_RST (BIT(30)) -#define SYSTEM_ADC2_ARB_RST_M (SYSTEM_ADC2_ARB_RST_V << SYSTEM_ADC2_ARB_RST_S) -#define SYSTEM_ADC2_ARB_RST_V 0x00000001 -#define SYSTEM_ADC2_ARB_RST_S 30 - -/* SYSTEM_SYSTIMER_RST : R/W; bitpos: [29]; default: 0; - * Set 1 to let SYSTIMER reset - */ - -#define SYSTEM_SYSTIMER_RST (BIT(29)) -#define SYSTEM_SYSTIMER_RST_M (SYSTEM_SYSTIMER_RST_V << SYSTEM_SYSTIMER_RST_S) -#define SYSTEM_SYSTIMER_RST_V 0x00000001 -#define SYSTEM_SYSTIMER_RST_S 29 - -/* SYSTEM_APB_SARADC_RST : R/W; bitpos: [28]; default: 0; - * Set 1 to let APB_SARADC reset - */ - -#define SYSTEM_APB_SARADC_RST (BIT(28)) -#define SYSTEM_APB_SARADC_RST_M (SYSTEM_APB_SARADC_RST_V << SYSTEM_APB_SARADC_RST_S) -#define SYSTEM_APB_SARADC_RST_V 0x00000001 -#define SYSTEM_APB_SARADC_RST_S 28 - -/* SYSTEM_SPI3_DMA_RST : R/W; bitpos: [27]; default: 0; - * Set 1 to let SPI3 reset - */ - -#define SYSTEM_SPI3_DMA_RST (BIT(27)) -#define SYSTEM_SPI3_DMA_RST_M (SYSTEM_SPI3_DMA_RST_V << SYSTEM_SPI3_DMA_RST_S) -#define SYSTEM_SPI3_DMA_RST_V 0x00000001 -#define SYSTEM_SPI3_DMA_RST_S 27 - -/* SYSTEM_PWM3_RST : R/W; bitpos: [26]; default: 0; - * Set 1 to let PWM3 reset - */ - -#define SYSTEM_PWM3_RST (BIT(26)) -#define SYSTEM_PWM3_RST_M (SYSTEM_PWM3_RST_V << SYSTEM_PWM3_RST_S) -#define SYSTEM_PWM3_RST_V 0x00000001 -#define SYSTEM_PWM3_RST_S 26 - -/* SYSTEM_PWM2_RST : R/W; bitpos: [25]; default: 0; - * Set 1 to let PWM2 reset - */ - -#define SYSTEM_PWM2_RST (BIT(25)) -#define SYSTEM_PWM2_RST_M (SYSTEM_PWM2_RST_V << SYSTEM_PWM2_RST_S) -#define SYSTEM_PWM2_RST_V 0x00000001 -#define SYSTEM_PWM2_RST_S 25 - -/* SYSTEM_UART_MEM_RST : R/W; bitpos: [24]; default: 0; - * Set 1 to let UART_MEM reset - */ - -#define SYSTEM_UART_MEM_RST (BIT(24)) -#define SYSTEM_UART_MEM_RST_M (SYSTEM_UART_MEM_RST_V << SYSTEM_UART_MEM_RST_S) -#define SYSTEM_UART_MEM_RST_V 0x00000001 -#define SYSTEM_UART_MEM_RST_S 24 - -/* SYSTEM_USB_RST : R/W; bitpos: [23]; default: 0; - * Set 1 to let USB reset - */ - -#define SYSTEM_USB_RST (BIT(23)) -#define SYSTEM_USB_RST_M (SYSTEM_USB_RST_V << SYSTEM_USB_RST_S) -#define SYSTEM_USB_RST_V 0x00000001 -#define SYSTEM_USB_RST_S 23 - -/* SYSTEM_SPI2_DMA_RST : R/W; bitpos: [22]; default: 0; - * Set 1 to let SPI2 reset - */ - -#define SYSTEM_SPI2_DMA_RST (BIT(22)) -#define SYSTEM_SPI2_DMA_RST_M (SYSTEM_SPI2_DMA_RST_V << SYSTEM_SPI2_DMA_RST_S) -#define SYSTEM_SPI2_DMA_RST_V 0x00000001 -#define SYSTEM_SPI2_DMA_RST_S 22 - -/* SYSTEM_I2S1_RST : R/W; bitpos: [21]; default: 0; - * Set 1 to let I2S1 reset - */ - -#define SYSTEM_I2S1_RST (BIT(21)) -#define SYSTEM_I2S1_RST_M (SYSTEM_I2S1_RST_V << SYSTEM_I2S1_RST_S) -#define SYSTEM_I2S1_RST_V 0x00000001 -#define SYSTEM_I2S1_RST_S 21 - -/* SYSTEM_PWM1_RST : R/W; bitpos: [20]; default: 0; - * Set 1 to let PWM1 reset - */ - -#define SYSTEM_PWM1_RST (BIT(20)) -#define SYSTEM_PWM1_RST_M (SYSTEM_PWM1_RST_V << SYSTEM_PWM1_RST_S) -#define SYSTEM_PWM1_RST_V 0x00000001 -#define SYSTEM_PWM1_RST_S 20 - -/* SYSTEM_TWAI_RST : R/W; bitpos: [19]; default: 0; - * Set 1 to let TWAI reset - */ - -#define SYSTEM_TWAI_RST (BIT(19)) -#define SYSTEM_TWAI_RST_M (SYSTEM_TWAI_RST_V << SYSTEM_TWAI_RST_S) -#define SYSTEM_TWAI_RST_V 0x00000001 -#define SYSTEM_TWAI_RST_S 19 - -/* SYSTEM_I2C_EXT1_RST : R/W; bitpos: [18]; default: 0; - * Set 1 to let I2C_EXT1 reset - */ - -#define SYSTEM_I2C_EXT1_RST (BIT(18)) -#define SYSTEM_I2C_EXT1_RST_M (SYSTEM_I2C_EXT1_RST_V << SYSTEM_I2C_EXT1_RST_S) -#define SYSTEM_I2C_EXT1_RST_V 0x00000001 -#define SYSTEM_I2C_EXT1_RST_S 18 - -/* SYSTEM_PWM0_RST : R/W; bitpos: [17]; default: 0; - * Set 1 to let PWM0 reset - */ - -#define SYSTEM_PWM0_RST (BIT(17)) -#define SYSTEM_PWM0_RST_M (SYSTEM_PWM0_RST_V << SYSTEM_PWM0_RST_S) -#define SYSTEM_PWM0_RST_V 0x00000001 -#define SYSTEM_PWM0_RST_S 17 - -/* SYSTEM_SPI3_RST : R/W; bitpos: [16]; default: 0; - * Set 1 to let SPI3 reset - */ - -#define SYSTEM_SPI3_RST (BIT(16)) -#define SYSTEM_SPI3_RST_M (SYSTEM_SPI3_RST_V << SYSTEM_SPI3_RST_S) -#define SYSTEM_SPI3_RST_V 0x00000001 -#define SYSTEM_SPI3_RST_S 16 - -/* SYSTEM_TIMERGROUP1_RST : R/W; bitpos: [15]; default: 0; - * Set 1 to let TIMERGROUP1 reset - */ - -#define SYSTEM_TIMERGROUP1_RST (BIT(15)) -#define SYSTEM_TIMERGROUP1_RST_M (SYSTEM_TIMERGROUP1_RST_V << SYSTEM_TIMERGROUP1_RST_S) -#define SYSTEM_TIMERGROUP1_RST_V 0x00000001 -#define SYSTEM_TIMERGROUP1_RST_S 15 - -/* SYSTEM_EFUSE_RST : R/W; bitpos: [14]; default: 0; - * Set 1 to let EFUSE reset - */ - -#define SYSTEM_EFUSE_RST (BIT(14)) -#define SYSTEM_EFUSE_RST_M (SYSTEM_EFUSE_RST_V << SYSTEM_EFUSE_RST_S) -#define SYSTEM_EFUSE_RST_V 0x00000001 -#define SYSTEM_EFUSE_RST_S 14 - -/* SYSTEM_TIMERGROUP_RST : R/W; bitpos: [13]; default: 0; - * Set 1 to let TIMERGROUP reset - */ - -#define SYSTEM_TIMERGROUP_RST (BIT(13)) -#define SYSTEM_TIMERGROUP_RST_M (SYSTEM_TIMERGROUP_RST_V << SYSTEM_TIMERGROUP_RST_S) -#define SYSTEM_TIMERGROUP_RST_V 0x00000001 -#define SYSTEM_TIMERGROUP_RST_S 13 - -/* SYSTEM_UHCI1_RST : R/W; bitpos: [12]; default: 0; - * Set 1 to let UHCI1 reset - */ - -#define SYSTEM_UHCI1_RST (BIT(12)) -#define SYSTEM_UHCI1_RST_M (SYSTEM_UHCI1_RST_V << SYSTEM_UHCI1_RST_S) -#define SYSTEM_UHCI1_RST_V 0x00000001 -#define SYSTEM_UHCI1_RST_S 12 - -/* SYSTEM_LEDC_RST : R/W; bitpos: [11]; default: 0; - * Set 1 to let LEDC reset - */ - -#define SYSTEM_LEDC_RST (BIT(11)) -#define SYSTEM_LEDC_RST_M (SYSTEM_LEDC_RST_V << SYSTEM_LEDC_RST_S) -#define SYSTEM_LEDC_RST_V 0x00000001 -#define SYSTEM_LEDC_RST_S 11 - -/* SYSTEM_PCNT_RST : R/W; bitpos: [10]; default: 0; - * Set 1 to let PCNT reset - */ - -#define SYSTEM_PCNT_RST (BIT(10)) -#define SYSTEM_PCNT_RST_M (SYSTEM_PCNT_RST_V << SYSTEM_PCNT_RST_S) -#define SYSTEM_PCNT_RST_V 0x00000001 -#define SYSTEM_PCNT_RST_S 10 - -/* SYSTEM_RMT_RST : R/W; bitpos: [9]; default: 0; - * Set 1 to let RMT reset - */ - -#define SYSTEM_RMT_RST (BIT(9)) -#define SYSTEM_RMT_RST_M (SYSTEM_RMT_RST_V << SYSTEM_RMT_RST_S) -#define SYSTEM_RMT_RST_V 0x00000001 -#define SYSTEM_RMT_RST_S 9 - -/* SYSTEM_UHCI0_RST : R/W; bitpos: [8]; default: 0; - * Set 1 to let UHCI0 reset - */ - -#define SYSTEM_UHCI0_RST (BIT(8)) -#define SYSTEM_UHCI0_RST_M (SYSTEM_UHCI0_RST_V << SYSTEM_UHCI0_RST_S) -#define SYSTEM_UHCI0_RST_V 0x00000001 -#define SYSTEM_UHCI0_RST_S 8 - -/* SYSTEM_I2C_EXT0_RST : R/W; bitpos: [7]; default: 0; - * Set 1 to let I2C_EXT0 reset - */ - -#define SYSTEM_I2C_EXT0_RST (BIT(7)) -#define SYSTEM_I2C_EXT0_RST_M (SYSTEM_I2C_EXT0_RST_V << SYSTEM_I2C_EXT0_RST_S) -#define SYSTEM_I2C_EXT0_RST_V 0x00000001 -#define SYSTEM_I2C_EXT0_RST_S 7 - -/* SYSTEM_SPI2_RST : R/W; bitpos: [6]; default: 0; - * Set 1 to let SPI2 reset - */ - -#define SYSTEM_SPI2_RST (BIT(6)) -#define SYSTEM_SPI2_RST_M (SYSTEM_SPI2_RST_V << SYSTEM_SPI2_RST_S) -#define SYSTEM_SPI2_RST_V 0x00000001 -#define SYSTEM_SPI2_RST_S 6 - -/* SYSTEM_UART1_RST : R/W; bitpos: [5]; default: 0; - * Set 1 to let UART1 reset - */ - -#define SYSTEM_UART1_RST (BIT(5)) -#define SYSTEM_UART1_RST_M (SYSTEM_UART1_RST_V << SYSTEM_UART1_RST_S) -#define SYSTEM_UART1_RST_V 0x00000001 -#define SYSTEM_UART1_RST_S 5 - -/* SYSTEM_I2S0_RST : R/W; bitpos: [4]; default: 0; - * Set 1 to let I2S0 reset - */ - -#define SYSTEM_I2S0_RST (BIT(4)) -#define SYSTEM_I2S0_RST_M (SYSTEM_I2S0_RST_V << SYSTEM_I2S0_RST_S) -#define SYSTEM_I2S0_RST_V 0x00000001 -#define SYSTEM_I2S0_RST_S 4 - -/* SYSTEM_WDG_RST : R/W; bitpos: [3]; default: 0; - * Set 1 to let WDG reset - */ - -#define SYSTEM_WDG_RST (BIT(3)) -#define SYSTEM_WDG_RST_M (SYSTEM_WDG_RST_V << SYSTEM_WDG_RST_S) -#define SYSTEM_WDG_RST_V 0x00000001 -#define SYSTEM_WDG_RST_S 3 - -/* SYSTEM_UART_RST : R/W; bitpos: [2]; default: 0; - * Set 1 to let UART reset - */ - -#define SYSTEM_UART_RST (BIT(2)) -#define SYSTEM_UART_RST_M (SYSTEM_UART_RST_V << SYSTEM_UART_RST_S) -#define SYSTEM_UART_RST_V 0x00000001 -#define SYSTEM_UART_RST_S 2 - -/* SYSTEM_SPI01_RST : R/W; bitpos: [1]; default: 0; - * Set 1 to let SPI01 reset - */ - -#define SYSTEM_SPI01_RST (BIT(1)) -#define SYSTEM_SPI01_RST_M (SYSTEM_SPI01_RST_V << SYSTEM_SPI01_RST_S) -#define SYSTEM_SPI01_RST_V 0x00000001 -#define SYSTEM_SPI01_RST_S 1 - -/* SYSTEM_TIMERS_RST : R/W; bitpos: [0]; default: 0; - * Set 1 to let TIMERS reset - */ - -#define SYSTEM_TIMERS_RST (BIT(0)) -#define SYSTEM_TIMERS_RST_M (SYSTEM_TIMERS_RST_V << SYSTEM_TIMERS_RST_S) -#define SYSTEM_TIMERS_RST_V 0x00000001 -#define SYSTEM_TIMERS_RST_S 0 - -/* SYSTEM_PERIP_RST_EN1_REG register - * peripheral reset configuration regsiter 1 - */ - -#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x24) - -/* SYSTEM_USB_DEVICE_RST : R/W; bitpos: [10]; default: 0; - * Set 1 to let USB_DEVICE reset - */ - -#define SYSTEM_USB_DEVICE_RST (BIT(10)) -#define SYSTEM_USB_DEVICE_RST_M (SYSTEM_USB_DEVICE_RST_V << SYSTEM_USB_DEVICE_RST_S) -#define SYSTEM_USB_DEVICE_RST_V 0x00000001 -#define SYSTEM_USB_DEVICE_RST_S 10 - -/* SYSTEM_UART2_RST : R/W; bitpos: [9]; default: 0; - * Set 1 to let UART2 reset - */ - -#define SYSTEM_UART2_RST (BIT(9)) -#define SYSTEM_UART2_RST_M (SYSTEM_UART2_RST_V << SYSTEM_UART2_RST_S) -#define SYSTEM_UART2_RST_V 0x00000001 -#define SYSTEM_UART2_RST_S 9 - -/* SYSTEM_LCD_CAM_RST : R/W; bitpos: [8]; default: 1; - * Set 1 to let LCD_CAM reset - */ - -#define SYSTEM_LCD_CAM_RST (BIT(8)) -#define SYSTEM_LCD_CAM_RST_M (SYSTEM_LCD_CAM_RST_V << SYSTEM_LCD_CAM_RST_S) -#define SYSTEM_LCD_CAM_RST_V 0x00000001 -#define SYSTEM_LCD_CAM_RST_S 8 - -/* SYSTEM_SDIO_HOST_RST : R/W; bitpos: [7]; default: 1; - * Set 1 to let SDIO_HOST reset - */ - -#define SYSTEM_SDIO_HOST_RST (BIT(7)) -#define SYSTEM_SDIO_HOST_RST_M (SYSTEM_SDIO_HOST_RST_V << SYSTEM_SDIO_HOST_RST_S) -#define SYSTEM_SDIO_HOST_RST_V 0x00000001 -#define SYSTEM_SDIO_HOST_RST_S 7 - -/* SYSTEM_DMA_RST : R/W; bitpos: [6]; default: 1; - * Set 1 to let DMA reset - */ - -#define SYSTEM_DMA_RST (BIT(6)) -#define SYSTEM_DMA_RST_M (SYSTEM_DMA_RST_V << SYSTEM_DMA_RST_S) -#define SYSTEM_DMA_RST_V 0x00000001 -#define SYSTEM_DMA_RST_S 6 - -/* SYSTEM_CRYPTO_HMAC_RST : R/W; bitpos: [5]; default: 1; - * Set 1 to let CRYPTO_HMAC reset - */ - -#define SYSTEM_CRYPTO_HMAC_RST (BIT(5)) -#define SYSTEM_CRYPTO_HMAC_RST_M (SYSTEM_CRYPTO_HMAC_RST_V << SYSTEM_CRYPTO_HMAC_RST_S) -#define SYSTEM_CRYPTO_HMAC_RST_V 0x00000001 -#define SYSTEM_CRYPTO_HMAC_RST_S 5 - -/* SYSTEM_CRYPTO_DS_RST : R/W; bitpos: [4]; default: 1; - * Set 1 to let CRYPTO_DS reset - */ - -#define SYSTEM_CRYPTO_DS_RST (BIT(4)) -#define SYSTEM_CRYPTO_DS_RST_M (SYSTEM_CRYPTO_DS_RST_V << SYSTEM_CRYPTO_DS_RST_S) -#define SYSTEM_CRYPTO_DS_RST_V 0x00000001 -#define SYSTEM_CRYPTO_DS_RST_S 4 - -/* SYSTEM_CRYPTO_RSA_RST : R/W; bitpos: [3]; default: 1; - * Set 1 to let CRYPTO_RSA reset - */ - -#define SYSTEM_CRYPTO_RSA_RST (BIT(3)) -#define SYSTEM_CRYPTO_RSA_RST_M (SYSTEM_CRYPTO_RSA_RST_V << SYSTEM_CRYPTO_RSA_RST_S) -#define SYSTEM_CRYPTO_RSA_RST_V 0x00000001 -#define SYSTEM_CRYPTO_RSA_RST_S 3 - -/* SYSTEM_CRYPTO_SHA_RST : R/W; bitpos: [2]; default: 1; - * Set 1 to let CRYPTO_SHA reset - */ - -#define SYSTEM_CRYPTO_SHA_RST (BIT(2)) -#define SYSTEM_CRYPTO_SHA_RST_M (SYSTEM_CRYPTO_SHA_RST_V << SYSTEM_CRYPTO_SHA_RST_S) -#define SYSTEM_CRYPTO_SHA_RST_V 0x00000001 -#define SYSTEM_CRYPTO_SHA_RST_S 2 - -/* SYSTEM_CRYPTO_AES_RST : R/W; bitpos: [1]; default: 1; - * Set 1 to let CRYPTO_AES reset - */ - -#define SYSTEM_CRYPTO_AES_RST (BIT(1)) -#define SYSTEM_CRYPTO_AES_RST_M (SYSTEM_CRYPTO_AES_RST_V << SYSTEM_CRYPTO_AES_RST_S) -#define SYSTEM_CRYPTO_AES_RST_V 0x00000001 -#define SYSTEM_CRYPTO_AES_RST_S 1 - -/* SYSTEM_PERI_BACKUP_RST : R/W; bitpos: [0]; default: 0; - * Set 1 to let BACKUP reset - */ - -#define SYSTEM_PERI_BACKUP_RST (BIT(0)) -#define SYSTEM_PERI_BACKUP_RST_M (SYSTEM_PERI_BACKUP_RST_V << SYSTEM_PERI_BACKUP_RST_S) -#define SYSTEM_PERI_BACKUP_RST_V 0x00000001 -#define SYSTEM_PERI_BACKUP_RST_S 0 - -/* SYSTEM_BT_LPCK_DIV_INT_REG register - * low power clock frequent division factor configuration regsiter - */ - -#define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x28) - -/* SYSTEM_BT_LPCK_DIV_NUM : R/W; bitpos: [11:0]; default: 255; - * This field is lower power clock frequent division factor - */ - -#define SYSTEM_BT_LPCK_DIV_NUM 0x00000fff -#define SYSTEM_BT_LPCK_DIV_NUM_M (SYSTEM_BT_LPCK_DIV_NUM_V << SYSTEM_BT_LPCK_DIV_NUM_S) -#define SYSTEM_BT_LPCK_DIV_NUM_V 0x00000fff -#define SYSTEM_BT_LPCK_DIV_NUM_S 0 - -/* SYSTEM_BT_LPCK_DIV_FRAC_REG register - * low power clock configuration register - */ - -#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x2c) - -/* SYSTEM_LPCLK_RTC_EN : R/W; bitpos: [28]; default: 0; - * Set 1 to enable RTC low power clock - */ - -#define SYSTEM_LPCLK_RTC_EN (BIT(28)) -#define SYSTEM_LPCLK_RTC_EN_M (SYSTEM_LPCLK_RTC_EN_V << SYSTEM_LPCLK_RTC_EN_S) -#define SYSTEM_LPCLK_RTC_EN_V 0x00000001 -#define SYSTEM_LPCLK_RTC_EN_S 28 - -/* SYSTEM_LPCLK_SEL_XTAL32K : R/W; bitpos: [27]; default: 0; - * Set 1 to select xtal32k clock as low power clock - */ - -#define SYSTEM_LPCLK_SEL_XTAL32K (BIT(27)) -#define SYSTEM_LPCLK_SEL_XTAL32K_M (SYSTEM_LPCLK_SEL_XTAL32K_V << SYSTEM_LPCLK_SEL_XTAL32K_S) -#define SYSTEM_LPCLK_SEL_XTAL32K_V 0x00000001 -#define SYSTEM_LPCLK_SEL_XTAL32K_S 27 - -/* SYSTEM_LPCLK_SEL_XTAL : R/W; bitpos: [26]; default: 0; - * Set 1 to select xtal clock as rtc low power clock - */ - -#define SYSTEM_LPCLK_SEL_XTAL (BIT(26)) -#define SYSTEM_LPCLK_SEL_XTAL_M (SYSTEM_LPCLK_SEL_XTAL_V << SYSTEM_LPCLK_SEL_XTAL_S) -#define SYSTEM_LPCLK_SEL_XTAL_V 0x00000001 -#define SYSTEM_LPCLK_SEL_XTAL_S 26 - -/* SYSTEM_LPCLK_SEL_8M : R/W; bitpos: [25]; default: 1; - * Set 1 to select 8m clock as rtc low power clock - */ - -#define SYSTEM_LPCLK_SEL_8M (BIT(25)) -#define SYSTEM_LPCLK_SEL_8M_M (SYSTEM_LPCLK_SEL_8M_V << SYSTEM_LPCLK_SEL_8M_S) -#define SYSTEM_LPCLK_SEL_8M_V 0x00000001 -#define SYSTEM_LPCLK_SEL_8M_S 25 - -/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W; bitpos: [24]; default: 0; - * Set 1 to select rtc-slow clock as rtc low power clock - */ - -#define SYSTEM_LPCLK_SEL_RTC_SLOW (BIT(24)) -#define SYSTEM_LPCLK_SEL_RTC_SLOW_M (SYSTEM_LPCLK_SEL_RTC_SLOW_V << SYSTEM_LPCLK_SEL_RTC_SLOW_S) -#define SYSTEM_LPCLK_SEL_RTC_SLOW_V 0x00000001 -#define SYSTEM_LPCLK_SEL_RTC_SLOW_S 24 - -/* SYSTEM_BT_LPCK_DIV_A : R/W; bitpos: [23:12]; default: 1; - * This field is lower power clock frequent division factor a - */ - -#define SYSTEM_BT_LPCK_DIV_A 0x00000fff -#define SYSTEM_BT_LPCK_DIV_A_M (SYSTEM_BT_LPCK_DIV_A_V << SYSTEM_BT_LPCK_DIV_A_S) -#define SYSTEM_BT_LPCK_DIV_A_V 0x00000fff -#define SYSTEM_BT_LPCK_DIV_A_S 12 - -/* SYSTEM_BT_LPCK_DIV_B : R/W; bitpos: [11:0]; default: 1; - * This field is lower power clock frequent division factor b - */ - -#define SYSTEM_BT_LPCK_DIV_B 0x00000fff -#define SYSTEM_BT_LPCK_DIV_B_M (SYSTEM_BT_LPCK_DIV_B_V << SYSTEM_BT_LPCK_DIV_B_S) -#define SYSTEM_BT_LPCK_DIV_B_V 0x00000fff -#define SYSTEM_BT_LPCK_DIV_B_S 0 - -/* SYSTEM_CPU_INTR_FROM_CPU_0_REG register - * interrupt source register 0 - */ - -#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x30) - -/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W; bitpos: [0]; default: 0; - * Set 1 to generate cpu interrupt 0 - */ - -#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_0_M (SYSTEM_CPU_INTR_FROM_CPU_0_V << SYSTEM_CPU_INTR_FROM_CPU_0_S) -#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x00000001 -#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0 - -/* SYSTEM_CPU_INTR_FROM_CPU_1_REG register - * interrupt source register 1 - */ - -#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x34) - -/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W; bitpos: [0]; default: 0; - * Set 1 to generate cpu interrupt 1 - */ - -#define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_1_M (SYSTEM_CPU_INTR_FROM_CPU_1_V << SYSTEM_CPU_INTR_FROM_CPU_1_S) -#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x00000001 -#define SYSTEM_CPU_INTR_FROM_CPU_1_S 0 - -/* SYSTEM_CPU_INTR_FROM_CPU_2_REG register - * interrupt source register 2 - */ - -#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x38) - -/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W; bitpos: [0]; default: 0; - * Set 1 to generate cpu interrupt 2 - */ - -#define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_2_M (SYSTEM_CPU_INTR_FROM_CPU_2_V << SYSTEM_CPU_INTR_FROM_CPU_2_S) -#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x00000001 -#define SYSTEM_CPU_INTR_FROM_CPU_2_S 0 - -/* SYSTEM_CPU_INTR_FROM_CPU_3_REG register - * interrupt source register 3 - */ - -#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x3c) - -/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W; bitpos: [0]; default: 0; - * Set 1 to generate cpu interrupt 3 - */ - -#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0)) -#define SYSTEM_CPU_INTR_FROM_CPU_3_M (SYSTEM_CPU_INTR_FROM_CPU_3_V << SYSTEM_CPU_INTR_FROM_CPU_3_S) -#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x00000001 -#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0 - -/* SYSTEM_RSA_PD_CTRL_REG register - * rsa memory power control register - */ - -#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x40) - -/* SYSTEM_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; - * Set 1 to force power down RSA memory,this bit has the highest priority. - */ - -#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2)) -#define SYSTEM_RSA_MEM_FORCE_PD_M (SYSTEM_RSA_MEM_FORCE_PD_V << SYSTEM_RSA_MEM_FORCE_PD_S) -#define SYSTEM_RSA_MEM_FORCE_PD_V 0x00000001 -#define SYSTEM_RSA_MEM_FORCE_PD_S 2 - -/* SYSTEM_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 0; - * Set 1 to force power up RSA memory, this bit has the second highest - * priority. - */ - -#define SYSTEM_RSA_MEM_FORCE_PU (BIT(1)) -#define SYSTEM_RSA_MEM_FORCE_PU_M (SYSTEM_RSA_MEM_FORCE_PU_V << SYSTEM_RSA_MEM_FORCE_PU_S) -#define SYSTEM_RSA_MEM_FORCE_PU_V 0x00000001 -#define SYSTEM_RSA_MEM_FORCE_PU_S 1 - -/* SYSTEM_RSA_MEM_PD : R/W; bitpos: [0]; default: 1; - * Set 1 to power down RSA memory. This bit has the lowest priority.When - * Digital Signature occupies the RSA, this bit is invalid. - */ - -#define SYSTEM_RSA_MEM_PD (BIT(0)) -#define SYSTEM_RSA_MEM_PD_M (SYSTEM_RSA_MEM_PD_V << SYSTEM_RSA_MEM_PD_S) -#define SYSTEM_RSA_MEM_PD_V 0x00000001 -#define SYSTEM_RSA_MEM_PD_S 0 - -/* SYSTEM_EDMA_CTRL_REG register - * EDMA control register - */ - -#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x44) - -/* SYSTEM_EDMA_RESET : R/W; bitpos: [1]; default: 0; - * Set 1 to let EDMA reset - */ - -#define SYSTEM_EDMA_RESET (BIT(1)) -#define SYSTEM_EDMA_RESET_M (SYSTEM_EDMA_RESET_V << SYSTEM_EDMA_RESET_S) -#define SYSTEM_EDMA_RESET_V 0x00000001 -#define SYSTEM_EDMA_RESET_S 1 - -/* SYSTEM_EDMA_CLK_ON : R/W; bitpos: [0]; default: 1; - * Set 1 to enable EDMA clock. - */ - -#define SYSTEM_EDMA_CLK_ON (BIT(0)) -#define SYSTEM_EDMA_CLK_ON_M (SYSTEM_EDMA_CLK_ON_V << SYSTEM_EDMA_CLK_ON_S) -#define SYSTEM_EDMA_CLK_ON_V 0x00000001 -#define SYSTEM_EDMA_CLK_ON_S 0 - -/* SYSTEM_CACHE_CONTROL_REG register - * Cache control register - */ - -#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x48) - -/* SYSTEM_DCACHE_RESET : R/W; bitpos: [3]; default: 0; - * Set 1 to let dcache reset - */ - -#define SYSTEM_DCACHE_RESET (BIT(3)) -#define SYSTEM_DCACHE_RESET_M (SYSTEM_DCACHE_RESET_V << SYSTEM_DCACHE_RESET_S) -#define SYSTEM_DCACHE_RESET_V 0x00000001 -#define SYSTEM_DCACHE_RESET_S 3 - -/* SYSTEM_DCACHE_CLK_ON : R/W; bitpos: [2]; default: 1; - * Set 1 to enable dcache clock - */ - -#define SYSTEM_DCACHE_CLK_ON (BIT(2)) -#define SYSTEM_DCACHE_CLK_ON_M (SYSTEM_DCACHE_CLK_ON_V << SYSTEM_DCACHE_CLK_ON_S) -#define SYSTEM_DCACHE_CLK_ON_V 0x00000001 -#define SYSTEM_DCACHE_CLK_ON_S 2 - -/* SYSTEM_ICACHE_RESET : R/W; bitpos: [1]; default: 0; - * Set 1 to let icache reset - */ - -#define SYSTEM_ICACHE_RESET (BIT(1)) -#define SYSTEM_ICACHE_RESET_M (SYSTEM_ICACHE_RESET_V << SYSTEM_ICACHE_RESET_S) -#define SYSTEM_ICACHE_RESET_V 0x00000001 -#define SYSTEM_ICACHE_RESET_S 1 - -/* SYSTEM_ICACHE_CLK_ON : R/W; bitpos: [0]; default: 1; - * Set 1 to enable icache clock - */ - -#define SYSTEM_ICACHE_CLK_ON (BIT(0)) -#define SYSTEM_ICACHE_CLK_ON_M (SYSTEM_ICACHE_CLK_ON_V << SYSTEM_ICACHE_CLK_ON_S) -#define SYSTEM_ICACHE_CLK_ON_V 0x00000001 -#define SYSTEM_ICACHE_CLK_ON_S 0 - -/* SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG register - * External memory encrypt and decrypt control register - */ - -#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x4c) - -/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W; bitpos: [3]; default: 0; - * Set 1 to enable download manual encrypt - */ - -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V << SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S) -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001 -#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 - -/* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W; bitpos: [2]; default: 0; - * Set 1 to enable download G0CB decrypt - */ - -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V << SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S) -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x00000001 -#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 - -/* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W; bitpos: [1]; default: 0; - * Set 1 to enable download DB encrypt. - */ - -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V << SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S) -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x00000001 -#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 - -/* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W; bitpos: [0]; default: 0; - * Set 1 to enable the SPI manual encrypt. - */ - -#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) -#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V << SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S) -#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x00000001 -#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 - -/* SYSTEM_RTC_FASTMEM_CONFIG_REG register - * RTC fast memory configuration register - */ - -#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x50) - -/* SYSTEM_RTC_MEM_CRC_FINISH : RO; bitpos: [31]; default: 0; - * This bit stores the status of RTC memory CRC.1 means finished. - */ - -#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31)) -#define SYSTEM_RTC_MEM_CRC_FINISH_M (SYSTEM_RTC_MEM_CRC_FINISH_V << SYSTEM_RTC_MEM_CRC_FINISH_S) -#define SYSTEM_RTC_MEM_CRC_FINISH_V 0x00000001 -#define SYSTEM_RTC_MEM_CRC_FINISH_S 31 - -/* SYSTEM_RTC_MEM_CRC_LEN : R/W; bitpos: [30:20]; default: 2047; - * This field is used to set length of RTC memory for CRC based on start - * address. - */ - -#define SYSTEM_RTC_MEM_CRC_LEN 0x000007ff -#define SYSTEM_RTC_MEM_CRC_LEN_M (SYSTEM_RTC_MEM_CRC_LEN_V << SYSTEM_RTC_MEM_CRC_LEN_S) -#define SYSTEM_RTC_MEM_CRC_LEN_V 0x000007ff -#define SYSTEM_RTC_MEM_CRC_LEN_S 20 - -/* SYSTEM_RTC_MEM_CRC_ADDR : R/W; bitpos: [19:9]; default: 0; - * This field is used to set address of RTC memory for CRC. - */ - -#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007ff -#define SYSTEM_RTC_MEM_CRC_ADDR_M (SYSTEM_RTC_MEM_CRC_ADDR_V << SYSTEM_RTC_MEM_CRC_ADDR_S) -#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x000007ff -#define SYSTEM_RTC_MEM_CRC_ADDR_S 9 - -/* SYSTEM_RTC_MEM_CRC_START : R/W; bitpos: [8]; default: 0; - * Set 1 to start the CRC of RTC memory - */ - -#define SYSTEM_RTC_MEM_CRC_START (BIT(8)) -#define SYSTEM_RTC_MEM_CRC_START_M (SYSTEM_RTC_MEM_CRC_START_V << SYSTEM_RTC_MEM_CRC_START_S) -#define SYSTEM_RTC_MEM_CRC_START_V 0x00000001 -#define SYSTEM_RTC_MEM_CRC_START_S 8 - -/* SYSTEM_RTC_FASTMEM_CRC_REG register - * RTC fast memory CRC control register - */ - -#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x54) - -/* SYSTEM_RTC_MEM_CRC_RES : RO; bitpos: [31:0]; default: 0; - * This field stores the CRC result of RTC memory. - */ - -#define SYSTEM_RTC_MEM_CRC_RES 0xffffffff -#define SYSTEM_RTC_MEM_CRC_RES_M (SYSTEM_RTC_MEM_CRC_RES_V << SYSTEM_RTC_MEM_CRC_RES_S) -#define SYSTEM_RTC_MEM_CRC_RES_V 0xffffffff -#define SYSTEM_RTC_MEM_CRC_RES_S 0 - -/* SYSTEM_REDUNDANT_ECO_CTRL_REG register - * ******* Description *********** - */ - -#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x58) - -/* SYSTEM_REDUNDANT_ECO_RESULT : RO; bitpos: [1]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1)) -#define SYSTEM_REDUNDANT_ECO_RESULT_M (SYSTEM_REDUNDANT_ECO_RESULT_V << SYSTEM_REDUNDANT_ECO_RESULT_S) -#define SYSTEM_REDUNDANT_ECO_RESULT_V 0x00000001 -#define SYSTEM_REDUNDANT_ECO_RESULT_S 1 - -/* SYSTEM_REDUNDANT_ECO_DRIVE : R/W; bitpos: [0]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_REDUNDANT_ECO_DRIVE (BIT(0)) -#define SYSTEM_REDUNDANT_ECO_DRIVE_M (SYSTEM_REDUNDANT_ECO_DRIVE_V << SYSTEM_REDUNDANT_ECO_DRIVE_S) -#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x00000001 -#define SYSTEM_REDUNDANT_ECO_DRIVE_S 0 - -/* SYSTEM_CLOCK_GATE_REG register - * ******* Description *********** - */ - -#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x5c) - -/* SYSTEM_CLK_EN : R/W; bitpos: [0]; default: 1; - * ******* Description *********** - */ - -#define SYSTEM_CLK_EN (BIT(0)) -#define SYSTEM_CLK_EN_M (SYSTEM_CLK_EN_V << SYSTEM_CLK_EN_S) -#define SYSTEM_CLK_EN_V 0x00000001 -#define SYSTEM_CLK_EN_S 0 - -/* SYSTEM_SYSCLK_CONF_REG register - * System clock configuration register. - */ - -#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x60) - -/* SYSTEM_CLK_DIV_EN : RO; bitpos: [19]; default: 0; - * Reserved. - */ - -#define SYSTEM_CLK_DIV_EN (BIT(19)) -#define SYSTEM_CLK_DIV_EN_M (SYSTEM_CLK_DIV_EN_V << SYSTEM_CLK_DIV_EN_S) -#define SYSTEM_CLK_DIV_EN_V 0x00000001 -#define SYSTEM_CLK_DIV_EN_S 19 - -/* SYSTEM_CLK_XTAL_FREQ : RO; bitpos: [18:12]; default: 0; - * This field is used to read xtal frequency in MHz. - */ - -#define SYSTEM_CLK_XTAL_FREQ 0x0000007f -#define SYSTEM_CLK_XTAL_FREQ_M (SYSTEM_CLK_XTAL_FREQ_V << SYSTEM_CLK_XTAL_FREQ_S) -#define SYSTEM_CLK_XTAL_FREQ_V 0x0000007f -#define SYSTEM_CLK_XTAL_FREQ_S 12 - -/* SYSTEM_SOC_CLK_SEL : R/W; bitpos: [11:10]; default: 0; - * This field is used to select soc clock. - */ - -#define SYSTEM_SOC_CLK_SEL 0x00000003 -#define SYSTEM_SOC_CLK_SEL_M (SYSTEM_SOC_CLK_SEL_V << SYSTEM_SOC_CLK_SEL_S) -#define SYSTEM_SOC_CLK_SEL_V 0x00000003 -#define SYSTEM_SOC_CLK_SEL_S 10 - -/* SYSTEM_PRE_DIV_CNT : R/W; bitpos: [9:0]; default: 1; - * This field is used to set the count of prescaler of XTAL_CLK. - */ - -#define SYSTEM_PRE_DIV_CNT 0x000003ff -#define SYSTEM_PRE_DIV_CNT_M (SYSTEM_PRE_DIV_CNT_V << SYSTEM_PRE_DIV_CNT_S) -#define SYSTEM_PRE_DIV_CNT_V 0x000003ff -#define SYSTEM_PRE_DIV_CNT_S 0 - -/* SYSTEM_MEM_PVT_REG register - * ******* Description *********** - */ - -#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x64) - -/* SYSTEM_MEM_VT_SEL : R/W; bitpos: [23:22]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_MEM_VT_SEL 0x00000003 -#define SYSTEM_MEM_VT_SEL_M (SYSTEM_MEM_VT_SEL_V << SYSTEM_MEM_VT_SEL_S) -#define SYSTEM_MEM_VT_SEL_V 0x00000003 -#define SYSTEM_MEM_VT_SEL_S 22 - -/* SYSTEM_MEM_TIMING_ERR_CNT : RO; bitpos: [21:6]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_MEM_TIMING_ERR_CNT 0x0000ffff -#define SYSTEM_MEM_TIMING_ERR_CNT_M (SYSTEM_MEM_TIMING_ERR_CNT_V << SYSTEM_MEM_TIMING_ERR_CNT_S) -#define SYSTEM_MEM_TIMING_ERR_CNT_V 0x0000ffff -#define SYSTEM_MEM_TIMING_ERR_CNT_S 6 - -/* SYSTEM_MEM_PVT_MONITOR_EN : R/W; bitpos: [5]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_MEM_PVT_MONITOR_EN (BIT(5)) -#define SYSTEM_MEM_PVT_MONITOR_EN_M (SYSTEM_MEM_PVT_MONITOR_EN_V << SYSTEM_MEM_PVT_MONITOR_EN_S) -#define SYSTEM_MEM_PVT_MONITOR_EN_V 0x00000001 -#define SYSTEM_MEM_PVT_MONITOR_EN_S 5 - -/* SYSTEM_MEM_ERR_CNT_CLR : WO; bitpos: [4]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_MEM_ERR_CNT_CLR (BIT(4)) -#define SYSTEM_MEM_ERR_CNT_CLR_M (SYSTEM_MEM_ERR_CNT_CLR_V << SYSTEM_MEM_ERR_CNT_CLR_S) -#define SYSTEM_MEM_ERR_CNT_CLR_V 0x00000001 -#define SYSTEM_MEM_ERR_CNT_CLR_S 4 - -/* SYSTEM_MEM_PATH_LEN : R/W; bitpos: [3:0]; default: 3; - * ******* Description *********** - */ - -#define SYSTEM_MEM_PATH_LEN 0x0000000f -#define SYSTEM_MEM_PATH_LEN_M (SYSTEM_MEM_PATH_LEN_V << SYSTEM_MEM_PATH_LEN_S) -#define SYSTEM_MEM_PATH_LEN_V 0x0000000f -#define SYSTEM_MEM_PATH_LEN_S 0 - -/* SYSTEM_COMB_PVT_LVT_CONF_REG register - * ******* Description *********** - */ - -#define SYSTEM_COMB_PVT_LVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x68) - -/* SYSTEM_COMB_PVT_MONITOR_EN_LVT : R/W; bitpos: [6]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_COMB_PVT_MONITOR_EN_LVT (BIT(6)) -#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_M (SYSTEM_COMB_PVT_MONITOR_EN_LVT_V << SYSTEM_COMB_PVT_MONITOR_EN_LVT_S) -#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_V 0x00000001 -#define SYSTEM_COMB_PVT_MONITOR_EN_LVT_S 6 - -/* SYSTEM_COMB_ERR_CNT_CLR_LVT : WO; bitpos: [5]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_COMB_ERR_CNT_CLR_LVT (BIT(5)) -#define SYSTEM_COMB_ERR_CNT_CLR_LVT_M (SYSTEM_COMB_ERR_CNT_CLR_LVT_V << SYSTEM_COMB_ERR_CNT_CLR_LVT_S) -#define SYSTEM_COMB_ERR_CNT_CLR_LVT_V 0x00000001 -#define SYSTEM_COMB_ERR_CNT_CLR_LVT_S 5 - -/* SYSTEM_COMB_PATH_LEN_LVT : R/W; bitpos: [4:0]; default: 3; - * ******* Description *********** - */ - -#define SYSTEM_COMB_PATH_LEN_LVT 0x0000001f -#define SYSTEM_COMB_PATH_LEN_LVT_M (SYSTEM_COMB_PATH_LEN_LVT_V << SYSTEM_COMB_PATH_LEN_LVT_S) -#define SYSTEM_COMB_PATH_LEN_LVT_V 0x0000001f -#define SYSTEM_COMB_PATH_LEN_LVT_S 0 - -/* SYSTEM_COMB_PVT_NVT_CONF_REG register - * ******* Description *********** - */ - -#define SYSTEM_COMB_PVT_NVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x6c) - -/* SYSTEM_COMB_PVT_MONITOR_EN_NVT : R/W; bitpos: [6]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_COMB_PVT_MONITOR_EN_NVT (BIT(6)) -#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_M (SYSTEM_COMB_PVT_MONITOR_EN_NVT_V << SYSTEM_COMB_PVT_MONITOR_EN_NVT_S) -#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_V 0x00000001 -#define SYSTEM_COMB_PVT_MONITOR_EN_NVT_S 6 - -/* SYSTEM_COMB_ERR_CNT_CLR_NVT : WO; bitpos: [5]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_COMB_ERR_CNT_CLR_NVT (BIT(5)) -#define SYSTEM_COMB_ERR_CNT_CLR_NVT_M (SYSTEM_COMB_ERR_CNT_CLR_NVT_V << SYSTEM_COMB_ERR_CNT_CLR_NVT_S) -#define SYSTEM_COMB_ERR_CNT_CLR_NVT_V 0x00000001 -#define SYSTEM_COMB_ERR_CNT_CLR_NVT_S 5 - -/* SYSTEM_COMB_PATH_LEN_NVT : R/W; bitpos: [4:0]; default: 3; - * ******* Description *********** - */ - -#define SYSTEM_COMB_PATH_LEN_NVT 0x0000001f -#define SYSTEM_COMB_PATH_LEN_NVT_M (SYSTEM_COMB_PATH_LEN_NVT_V << SYSTEM_COMB_PATH_LEN_NVT_S) -#define SYSTEM_COMB_PATH_LEN_NVT_V 0x0000001f -#define SYSTEM_COMB_PATH_LEN_NVT_S 0 - -/* SYSTEM_COMB_PVT_HVT_CONF_REG register - * ******* Description *********** - */ - -#define SYSTEM_COMB_PVT_HVT_CONF_REG (DR_REG_SYSTEM_BASE + 0x70) - -/* SYSTEM_COMB_PVT_MONITOR_EN_HVT : R/W; bitpos: [6]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_COMB_PVT_MONITOR_EN_HVT (BIT(6)) -#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_M (SYSTEM_COMB_PVT_MONITOR_EN_HVT_V << SYSTEM_COMB_PVT_MONITOR_EN_HVT_S) -#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_V 0x00000001 -#define SYSTEM_COMB_PVT_MONITOR_EN_HVT_S 6 - -/* SYSTEM_COMB_ERR_CNT_CLR_HVT : WO; bitpos: [5]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_COMB_ERR_CNT_CLR_HVT (BIT(5)) -#define SYSTEM_COMB_ERR_CNT_CLR_HVT_M (SYSTEM_COMB_ERR_CNT_CLR_HVT_V << SYSTEM_COMB_ERR_CNT_CLR_HVT_S) -#define SYSTEM_COMB_ERR_CNT_CLR_HVT_V 0x00000001 -#define SYSTEM_COMB_ERR_CNT_CLR_HVT_S 5 - -/* SYSTEM_COMB_PATH_LEN_HVT : R/W; bitpos: [4:0]; default: 3; - * ******* Description *********** - */ - -#define SYSTEM_COMB_PATH_LEN_HVT 0x0000001f -#define SYSTEM_COMB_PATH_LEN_HVT_M (SYSTEM_COMB_PATH_LEN_HVT_V << SYSTEM_COMB_PATH_LEN_HVT_S) -#define SYSTEM_COMB_PATH_LEN_HVT_V 0x0000001f -#define SYSTEM_COMB_PATH_LEN_HVT_S 0 - -/* SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG register - * ******* Description *********** - */ - -#define SYSTEM_COMB_PVT_ERR_LVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x74) - -/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 : RO; bitpos: [15:0]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_M (SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V << SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S) -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_V 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE0_S 0 - -/* SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG register - * ******* Description *********** - */ - -#define SYSTEM_COMB_PVT_ERR_NVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x78) - -/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 : RO; bitpos: [15:0]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_M (SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V << SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S) -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_V 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE0_S 0 - -/* SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG register - * ******* Description *********** - */ - -#define SYSTEM_COMB_PVT_ERR_HVT_SITE0_REG (DR_REG_SYSTEM_BASE + 0x7c) - -/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 : RO; bitpos: [15:0]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_M (SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V << SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S) -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_V 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE0_S 0 - -/* SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG register - * ******* Description *********** - */ - -#define SYSTEM_COMB_PVT_ERR_LVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x80) - -/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 : RO; bitpos: [15:0]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_M (SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V << SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S) -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_V 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE1_S 0 - -/* SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG register - * ******* Description *********** - */ - -#define SYSTEM_COMB_PVT_ERR_NVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x84) - -/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 : RO; bitpos: [15:0]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_M (SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V << SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S) -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_V 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE1_S 0 - -/* SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG register - * ******* Description *********** - */ - -#define SYSTEM_COMB_PVT_ERR_HVT_SITE1_REG (DR_REG_SYSTEM_BASE + 0x88) - -/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 : RO; bitpos: [15:0]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_M (SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V << SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S) -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_V 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE1_S 0 - -/* SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG register - * ******* Description *********** - */ - -#define SYSTEM_COMB_PVT_ERR_LVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x8c) - -/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 : RO; bitpos: [15:0]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_M (SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V << SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S) -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_V 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE2_S 0 - -/* SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG register - * ******* Description *********** - */ - -#define SYSTEM_COMB_PVT_ERR_NVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x90) - -/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 : RO; bitpos: [15:0]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_M (SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V << SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S) -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_V 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE2_S 0 - -/* SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG register - * ******* Description *********** - */ - -#define SYSTEM_COMB_PVT_ERR_HVT_SITE2_REG (DR_REG_SYSTEM_BASE + 0x94) - -/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 : RO; bitpos: [15:0]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_M (SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V << SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S) -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_V 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE2_S 0 - -/* SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG register - * ******* Description *********** - */ - -#define SYSTEM_COMB_PVT_ERR_LVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x98) - -/* SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 : RO; bitpos: [15:0]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_M (SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V << SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S) -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_V 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_LVT_SITE3_S 0 - -/* SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG register - * ******* Description *********** - */ - -#define SYSTEM_COMB_PVT_ERR_NVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0x9c) - -/* SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 : RO; bitpos: [15:0]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_M (SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V << SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S) -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_V 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_NVT_SITE3_S 0 - -/* SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG register - * ******* Description *********** - */ - -#define SYSTEM_COMB_PVT_ERR_HVT_SITE3_REG (DR_REG_SYSTEM_BASE + 0xa0) - -/* SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 : RO; bitpos: [15:0]; default: 0; - * ******* Description *********** - */ - -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_M (SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V << SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S) -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_V 0x0000ffff -#define SYSTEM_COMB_TIMING_ERR_CNT_HVT_SITE3_S 0 - -/* SYSTEM_DATE_REG register - * version register - */ - -#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xffc) - -/* SYSTEM_DATE : R/W; bitpos: [27:0]; default: 34607648; - * version register - */ - -#define SYSTEM_DATE 0x0fffffff -#define SYSTEM_DATE_M (SYSTEM_DATE_V << SYSTEM_DATE_S) -#define SYSTEM_DATE_V 0x0fffffff -#define SYSTEM_DATE_S 0 +#include "soc/system_reg.h" #endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_SYSTEM_H */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_uart.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_uart.h index 5258b439ae2ac..b893811de186d 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_uart.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_uart.h @@ -860,7 +860,7 @@ * Rx Filter configuration */ -#define UART_RX_FILT_REG (DR_REG_UART_BASE + 0x18) +#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18) /* UART_GLITCH_FILT_EN : R/W; bitpos: [8]; default: 0; * Set this bit to enable Rx signal filter. @@ -1280,7 +1280,7 @@ * Autobaud minimum low pulse duration register */ -#define UART_LOWPULSE_REG (DR_REG_UART_BASE + 0x28) +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) /* UART_LOWPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * This register stores the value of the minimum duration time of the low @@ -1296,7 +1296,7 @@ * Autobaud minimum high pulse duration register */ -#define UART_HIGHPULSE_REG (DR_REG_UART_BASE + 0x2c) +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2c) /* UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * This register stores the value of the maximum duration time for the high @@ -1312,7 +1312,7 @@ * Autobaud edge change count register */ -#define UART_RXD_CNT_REG (DR_REG_UART_BASE + 0x30) +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30) /* UART_RXD_EDGE_CNT : RO; bitpos: [9:0]; default: 0; * This register stores the count of rxd edge change. It is used in baud @@ -1328,7 +1328,7 @@ * Software flow-control configuration */ -#define UART_FLOW_CONF_REG (DR_REG_UART_BASE + 0x34) +#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34) /* UART_SEND_XOFF : R/W/SS/SC; bitpos: [5]; default: 0; * Set this bit to send Xoff char. It is cleared by hardware automatically. @@ -1389,7 +1389,7 @@ * Sleep-mode configuration */ -#define UART_SLEEP_CONF_REG (DR_REG_UART_BASE + 0x38) +#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) /* UART_ACTIVE_THRESHOLD : R/W; bitpos: [9:0]; default: 240; * The uart is activated from light sleeping mode when the input rxd edge @@ -1405,7 +1405,7 @@ * Software flow-control character configuration */ -#define UART_SWFC_CONF0_REG (DR_REG_UART_BASE + 0x3c) +#define UART_SWFC_CONF0_REG(i) (REG_UART_BASE(i) + 0x3c) /* UART_XOFF_CHAR : R/W; bitpos: [17:10]; default: 19; * This register stores the Xoff flow control char. @@ -1430,7 +1430,7 @@ * Software flow-control character configuration */ -#define UART_SWFC_CONF1_REG (DR_REG_UART_BASE + 0x40) +#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) /* UART_XON_CHAR : R/W; bitpos: [17:10]; default: 17; * This register stores the Xon flow control char. @@ -1455,7 +1455,7 @@ * Tx Break character configuration */ -#define UART_TXBRK_CONF_REG (DR_REG_UART_BASE + 0x44) +#define UART_TXBRK_CONF_REG(i) (REG_UART_BASE(i) + 0x44) /* UART_TX_BRK_NUM : R/W; bitpos: [7:0]; default: 10; * This register is used to configure the number of 0 to be sent after the @@ -1567,7 +1567,7 @@ * Pre-sequence timing configuration */ -#define UART_AT_CMD_PRECNT_REG (DR_REG_UART_BASE + 0x50) +#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x50) /* UART_PRE_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; * This register is used to configure the idle duration time before the @@ -1583,7 +1583,7 @@ * Post-sequence timing configuration */ -#define UART_AT_CMD_POSTCNT_REG (DR_REG_UART_BASE + 0x54) +#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x54) /* UART_POST_IDLE_NUM : R/W; bitpos: [15:0]; default: 2305; * This register is used to configure the duration time between the last @@ -1599,7 +1599,7 @@ * Timeout configuration */ -#define UART_AT_CMD_GAPTOUT_REG (DR_REG_UART_BASE + 0x58) +#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x58) /* UART_RX_GAP_TOUT : R/W; bitpos: [15:0]; default: 11; * This register is used to configure the duration time between the at_cmd @@ -1615,7 +1615,7 @@ * AT escape sequence detection configuration */ -#define UART_AT_CMD_CHAR_REG (DR_REG_UART_BASE + 0x5c) +#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x5c) /* UART_CHAR_NUM : R/W; bitpos: [15:8]; default: 3; * This register is used to configure the num of continuous at_cmd chars @@ -1705,7 +1705,7 @@ * Tx-FIFO write and read offset address. */ -#define UART_MEM_TX_STATUS_REG (DR_REG_UART_BASE + 0x64) +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x64) /* UART_TX_RADDR : RO; bitpos: [20:11]; default: 0; * This register stores the offset address in Tx-FIFO when Tx-FSM reads data @@ -1731,7 +1731,7 @@ * Rx-FIFO write and read offset address. */ -#define UART_MEM_RX_STATUS_REG (DR_REG_UART_BASE + 0x68) +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68) /* UART_RX_WADDR : RO; bitpos: [20:11]; default: 512; * This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl @@ -1758,7 +1758,7 @@ * UART transmit and receive status. */ -#define UART_FSM_STATUS_REG (DR_REG_UART_BASE + 0x6c) +#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c) /* UART_ST_UTX_OUT : RO; bitpos: [7:4]; default: 0; * This is the status register of transmitter. @@ -1782,7 +1782,7 @@ * Autobaud high pulse register */ -#define UART_POSPULSE_REG (DR_REG_UART_BASE + 0x70) +#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x70) /* UART_POSEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * This register stores the minimal input clock count between two positive @@ -1798,7 +1798,7 @@ * Autobaud low pulse register */ -#define UART_NEGPULSE_REG (DR_REG_UART_BASE + 0x74) +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x74) /* UART_NEGEDGE_MIN_CNT : RO; bitpos: [11:0]; default: 4095; * This register stores the minimal input clock count between two negative @@ -1910,7 +1910,7 @@ * UART Version register */ -#define UART_DATE_REG (DR_REG_UART_BASE + 0x7c) +#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x7c) /* UART_DATE : R/W; bitpos: [31:0]; default: 33587824; * This is the version register. @@ -1925,7 +1925,7 @@ * UART ID register */ -#define UART_ID_REG (DR_REG_UART_BASE + 0x80) +#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x80) /* UART_REG_UPDATE : R/W/SC; bitpos: [31]; default: 0; * Software write 1 would synchronize registers into UART Core clock domain diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_usb_serial_jtag.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_usb_serial_jtag.h index 1286d57af16ff..b370e654eeb72 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_usb_serial_jtag.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_usb_serial_jtag.h @@ -37,7 +37,7 @@ * USB_SERIAL_JTAG_EP1_REG. */ -#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_DEVICE_BASE + 0x0) +#define USB_SERIAL_JTAG_EP1_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x0) /* USB_SERIAL_JTAG_RDWR_BYTE : R/W; bitpos: [8:0]; default: 0; * Write and read byte data to/from UART Tx/Rx FIFO through this field. @@ -59,7 +59,7 @@ * USB_SERIAL_JTAG_CONF0_REG. */ -#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_DEVICE_BASE + 0x18) +#define USB_SERIAL_JTAG_CONF0_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x18) /* USB_SERIAL_JTAG_PHY_SEL : R/W; bitpos: [0]; default: 0; * Select internal/external PHY. 1’b0: internal PHY, 1’b1: external @@ -195,7 +195,7 @@ * USB_SERIAL_JTAG_TEST_REG. */ -#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_DEVICE_BASE + 0x1c) +#define USB_SERIAL_JTAG_TEST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x1c) /* USB_SERIAL_JTAG_TEST_ENABLE : R/W; bitpos: [0]; default: 0; * Enable test of the USB @@ -241,7 +241,7 @@ * USB_SERIAL_JTAG_MISC_CONF_REG. */ -#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x44) +#define USB_SERIAL_JTAG_MISC_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x44) /* USB_SERIAL_JTAG_CLK_EN : R/W; bitpos: [0]; default: 0; * 1'h1: Force clock on for register. 1'h0: Support clock only when @@ -258,7 +258,7 @@ * USB_SERIAL_JTAG_MEM_CONF_REG. */ -#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x48) +#define USB_SERIAL_JTAG_MEM_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x48) /* USB_SERIAL_JTAG_USB_MEM_PD : R/W; bitpos: [0]; default: 0; * 1: power down usb @@ -286,7 +286,7 @@ * USB_SERIAL_JTAG_EP1_CONF_REG. */ -#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_DEVICE_BASE + 0x4) +#define USB_SERIAL_JTAG_EP1_CONF_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x4) /* USB_SERIAL_JTAG_WR_DONE : WT; bitpos: [0]; default: 0; * Set this bit to indicate writing byte data to UART Tx FIFO is done. @@ -325,7 +325,7 @@ * USB_SERIAL_JTAG_JFIFO_ST_REG. */ -#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_DEVICE_BASE + 0x20) +#define USB_SERIAL_JTAG_JFIFO_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x20) /* USB_SERIAL_JTAG_IN_FIFO_CNT : RO; bitpos: [2:0]; default: 0; * JTAG in fifo * counter. @@ -410,7 +410,7 @@ * USB_SERIAL_JTAG_FRAM_NUM_REG. */ -#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_DEVICE_BASE + 0x24) +#define USB_SERIAL_JTAG_FRAM_NUM_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x24) /* USB_SERIAL_JTAG_SOF_FRAME_INDEX : RO; bitpos: [11:0]; default: 0; * Frame index of received SOF @@ -426,7 +426,7 @@ * USB_SERIAL_JTAG_IN_EP0_ST_REG. */ -#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x28) +#define USB_SERIAL_JTAG_IN_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x28) /* USB_SERIAL_JTAG_IN_EP0_STATE : RO; bitpos: [2:0]; default: 1; * State of IN Endpoint 0. @@ -459,7 +459,7 @@ * USB_SERIAL_JTAG_IN_EP1_ST_REG. */ -#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x2c) +#define USB_SERIAL_JTAG_IN_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x2c) /* USB_SERIAL_JTAG_IN_EP1_STATE : RO; bitpos: [2:0]; default: 1; * State of IN Endpoint 1. @@ -493,7 +493,7 @@ * USB_SERIAL_JTAG_IN_EP2_ST_REG. */ -#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x30) +#define USB_SERIAL_JTAG_IN_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x30) /* USB_SERIAL_JTAG_IN_EP2_STATE : RO; bitpos: [2:0]; default: 1; * State of IN Endpoint @@ -529,7 +529,7 @@ * USB_SERIAL_JTAG_IN_EP3_ST_REG. */ -#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_DEVICE_BASE + 0x34) +#define USB_SERIAL_JTAG_IN_EP3_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x34) /* USB_SERIAL_JTAG_IN_EP3_STATE : RO; bitpos: [2:0]; default: 1; * State of IN Endpoint @@ -565,7 +565,7 @@ * USB_SERIAL_JTAG_OUT_EP0_ST_REG. */ -#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_DEVICE_BASE + 0x38) +#define USB_SERIAL_JTAG_OUT_EP0_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x38) /* USB_SERIAL_JTAG_OUT_EP0_STATE : RO; bitpos: [2:0]; default: 0; * State of OUT Endpoint @@ -603,7 +603,7 @@ * USB_SERIAL_JTAG_OUT_EP1_ST_REG. */ -#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_DEVICE_BASE + 0x3c) +#define USB_SERIAL_JTAG_OUT_EP1_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x3c) /* USB_SERIAL_JTAG_OUT_EP1_STATE : RO; bitpos: [2:0]; default: 0; * State of OUT Endpoint @@ -651,7 +651,7 @@ * USB_SERIAL_JTAG_OUT_EP2_ST_REG. */ -#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_DEVICE_BASE + 0x40) +#define USB_SERIAL_JTAG_OUT_EP2_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x40) /* USB_SERIAL_JTAG_OUT_EP2_STATE : RO; bitpos: [2:0]; default: 0; * State of OUT Endpoint @@ -691,7 +691,7 @@ * USB_SERIAL_JTAG_INT_RAW_REG. */ -#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_DEVICE_BASE + 0x8) +#define USB_SERIAL_JTAG_INT_RAW_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x8) /* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; * The raw interrupt bit turns to high level when a flush command is @@ -828,7 +828,7 @@ * USB_SERIAL_JTAG_INT_ST_REG. */ -#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_DEVICE_BASE + 0xc) +#define USB_SERIAL_JTAG_INT_ST_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0xc) /* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ST : RO; bitpos: [0]; default: 0; * The raw interrupt status bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT @@ -959,7 +959,7 @@ * USB_SERIAL_JTAG_INT_ENA_REG. */ -#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_DEVICE_BASE + 0x10) +#define USB_SERIAL_JTAG_INT_ENA_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x10) /* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_ENA : R/W; bitpos: [0]; default: 0; * The interrupt enable bit for the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT * interrupt. @@ -1090,7 +1090,7 @@ * USB_SERIAL_JTAG_INT_CLR_REG. */ -#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_DEVICE_BASE + 0x14) +#define USB_SERIAL_JTAG_INT_CLR_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x14) /* USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT_CLR : WT; bitpos: [0]; default: 0; * Set this bit to clear the USB_SERIAL_JTAG_JTAG_IN_FLUSH_INT @@ -1219,7 +1219,7 @@ * USB_SERIAL_JTAG_DATE_REG. */ -#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_DEVICE_BASE + 0x80) +#define USB_SERIAL_JTAG_DATE_REG (DR_REG_USB_SERIAL_JTAG_BASE + 0x80) /* USB_SERIAL_JTAG_DATE : R/W; bitpos: [32:0]; default: 33583872; * register version. diff --git a/arch/xtensa/src/esp32s3/hardware/regi2c_saradc.h b/arch/xtensa/src/esp32s3/hardware/regi2c_saradc.h new file mode 100644 index 0000000000000..af6649bbb1bb9 --- /dev/null +++ b/arch/xtensa/src/esp32s3/hardware/regi2c_saradc.h @@ -0,0 +1,52 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s3/hardware/regi2c_saradc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_SARADC_H +#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_SARADC_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/** + * Register definitions for analog to calibrate initial code for getting a + * more precise voltage of SAR ADC. + */ + +#define I2C_ADC (0x69) +#define I2C_ADC_HOSTID (1) + +#define I2C_ADC1_ENCAL_GND (0x7) +#define I2C_ADC1_ENCAL_GND_MSB (0x5) +#define I2C_ADC1_ENCAL_GND_LSB (0x5) + +#define I2C_ADC1_INITVAL_L (0x0) +#define I2C_ADC1_INITVAL_L_MSB (0x7) +#define I2C_ADC1_INITVAL_L_LSB (0x0) + +#define I2C_ADC1_INITVAL_H (0x1) +#define I2C_ADC1_INITVAL_H_MSB (0x3) +#define I2C_ADC1_INITVAL_H_LSB (0x0) + +#define I2C_ADC1_DEF (0x2) +#define I2C_ADC1_DEF_MSB (0x6) +#define I2C_ADC1_DEF_LSB (0x4) + +#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_SARADC_H */ diff --git a/arch/xtensa/src/esp32s3/rom/esp32s3_libc_stubs.h b/arch/xtensa/src/esp32s3/rom/esp32s3_libc_stubs.h index ffc0d0f3d164c..c7cc0cb327d17 100644 --- a/arch/xtensa/src/esp32s3/rom/esp32s3_libc_stubs.h +++ b/arch/xtensa/src/esp32s3/rom/esp32s3_libc_stubs.h @@ -27,6 +27,7 @@ #include +#include #include #include #include @@ -38,8 +39,6 @@ #include -#define _lock_t int - /* Forward declaration */ struct _reent; diff --git a/arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h b/arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h deleted file mode 100644 index 7ac9219c2c952..0000000000000 --- a/arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h +++ /dev/null @@ -1,355 +0,0 @@ -/***************************************************************************** - * arch/xtensa/src/esp32s3/rom/esp32s3_opi_flash.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - *****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S3_ROM_ESP32S3_OPI_FLASH_H -#define __ARCH_XTENSA_SRC_ESP32S3_ROM_ESP32S3_OPI_FLASH_H - -/***************************************************************************** - * Included Files - *****************************************************************************/ - -#include -#include -#include -#include - -#ifdef __cplusplus -extern "C" -{ -#endif - -typedef struct -{ - uint8_t mode; - uint8_t cmd_bit_len; - uint16_t cmd; - uint32_t addr; - uint8_t addr_bit_len; - uint8_t dummy_bit_len; - uint8_t data_bit_len; - uint8_t cs_sel: 4; - uint8_t is_pe: 4; -} esp_rom_opiflash_cmd_t; - -typedef struct -{ - uint8_t addr_bit_len; - uint8_t dummy_bit_len; - uint16_t cmd; - uint8_t cmd_bit_len; - uint8_t var_dummy_en; -} esp_rom_opiflash_spi0rd_t; - -typedef struct -{ - esp_rom_opiflash_cmd_t rdid; - esp_rom_opiflash_cmd_t rdsr; - esp_rom_opiflash_cmd_t wren; - esp_rom_opiflash_cmd_t se; - esp_rom_opiflash_cmd_t be64k; - esp_rom_opiflash_cmd_t read; - esp_rom_opiflash_cmd_t pp; - esp_rom_opiflash_spi0rd_t cache_rd_cmd; -} esp_rom_opiflash_def_t; - -typedef struct -{ - uint16_t cmd; /* !< Command value */ - uint16_t cmd_bit_len; /* !< Command byte length */ - uint32_t *addr; /* !< Point to address value */ - uint32_t addr_bit_len; /* !< Address byte length */ - uint32_t *tx_data; /* !< Point to send data buffer */ - uint32_t tx_data_bit_len; /* !< Send data byte length. */ - uint32_t *rx_data; /* !< Point to recevie data buffer */ - uint32_t rx_data_bit_len; /* !< Recevie Data byte length. */ - uint32_t dummy_bit_len; -} esp_rom_spi_cmd_t; - -#define ESP_ROM_OPIFLASH_MUX_TAKE() -#define ESP_ROM_OPIFLASH_MUX_GIVE() -#define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0)) -#define ESP_ROM_OPIFLASH_SEL_CS1 (BIT(1)) - -/* Definition of MX25UM25645G Octa Flash - * SPI status register - */ - -#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 -#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 -#define ESP_ROM_SPIFLASH_BP0 BIT2 -#define ESP_ROM_SPIFLASH_BP1 BIT3 -#define ESP_ROM_SPIFLASH_BP2 BIT4 -#define ESP_ROM_SPIFLASH_QE BIT9 - -#define FLASH_OP_MODE_RDCMD_DOUT 0x3B -#define ESP_ROM_FLASH_SECTOR_SIZE 0x1000 -#define ESP_ROM_FLASH_BLOCK_SIZE_64K 0x10000 -#define ESP_ROM_FLASH_PAGE_SIZE 256 - -/* FLASH commands */ - -#define ROM_FLASH_CMD_RDID 0x9F -#define ROM_FLASH_CMD_WRSR 0x01 -#define ROM_FLASH_CMD_WRSR2 0x31 /* Not all SPI flash uses this command */ -#define ROM_FLASH_CMD_WREN 0x06 -#define ROM_FLASH_CMD_WRDI 0x04 -#define ROM_FLASH_CMD_RDSR 0x05 -#define ROM_FLASH_CMD_RDSR2 0x35 /* Not all SPI flash uses this command */ -#define ROM_FLASH_CMD_ERASE_SEC 0x20 -#define ROM_FLASH_CMD_ERASE_BLK_32K 0x52 -#define ROM_FLASH_CMD_ERASE_BLK_64K 0xD8 -#define ROM_FLASH_CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */ -#define ROM_FLASH_CMD_RSTEN 0x66 -#define ROM_FLASH_CMD_RST 0x99 - -#define ROM_FLASH_CMD_SE4B 0x21 -#define ROM_FLASH_CMD_SE4B_OCT 0xDE21 -#define ROM_FLASH_CMD_BE4B 0xDC -#define ROM_FLASH_CMD_BE4B_OCT 0x23DC -#define ROM_FLASH_CMD_RSTEN_OCT 0x9966 -#define ROM_FLASH_CMD_RST_OCT 0x6699 - -#define ROM_FLASH_CMD_FSTRD4B_STR 0x13EC -#define ROM_FLASH_CMD_FSTRD4B_DTR 0x11EE -#define ROM_FLASH_CMD_FSTRD4B 0x0C -#define ROM_FLASH_CMD_PP4B 0x12 -#define ROM_FLASH_CMD_PP4B_OCT 0xED12 - -#define ROM_FLASH_CMD_RDID_OCT 0x609F -#define ROM_FLASH_CMD_WREN_OCT 0xF906 -#define ROM_FLASH_CMD_RDSR_OCT 0xFA05 -#define ROM_FLASH_CMD_RDCR2 0x71 -#define ROM_FLASH_CMD_RDCR2_OCT 0x8E71 -#define ROM_FLASH_CMD_WRCR2 0x72 -#define ROM_FLASH_CMD_WRCR2_OCT 0x8D72 - -/* Definitions for GigaDevice GD25LX256E Flash */ - -#define ROM_FLASH_CMD_RDFSR_GD 0x70 -#define ROM_FLASH_CMD_RD_GD 0x03 -#define ROM_FLASH_CMD_RD4B_GD 0x13 -#define ROM_FLASH_CMD_FSTRD_GD 0x0B -#define ROM_FLASH_CMD_FSTRD4B_GD 0x0C -#define ROM_FLASH_CMD_FSTRD_OOUT_GD 0x8B -#define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C -#define ROM_FLASH_CMD_FSTRD_OIOSTR_GD 0xCB -#define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC -#define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD - -#define ROM_FLASH_CMD_PP_GD 0x02 -#define ROM_FLASH_CMD_PP4B_GD 0x12 -#define ROM_FLASH_CMD_PP_OOUT_GD 0x82 -#define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84 -#define ROM_FLASH_CMD_PP_OIO_GD 0xC2 -#define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E - -#define ROM_FLASH_CMD_SE_GD 0x20 -#define ROM_FLASH_CMD_SE4B_GD 0x21 -#define ROM_FLASH_CMD_BE32K_GD 0x52 -#define ROM_FLASH_CMD_BE32K4B_GD 0x5C -#define ROM_FLASH_CMD_BE64K_GD 0xD8 -#define ROM_FLASH_CMD_BE64K4B_GD 0xDC - -#define ROM_FLASH_CMD_EN4B_GD 0xB7 -#define ROM_FLASH_CMD_DIS4B_GD 0xE9 - -extern const esp_rom_opiflash_def_t *rom_opiflash_cmd_def; - -/* Init legacy driver for Octal Flash */ - -void esp_rom_opiflash_legacy_driver_init(const esp_rom_opiflash_def_t - *flash_cmd_def); - -/* Config the spi user command - * spi_num spi port - * pcmd pointer to accept the spi command struct - */ - -void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t *pcmd); - -/* Start a spi user command sequence - * spi_num spi port - * rx_buf buffer pointer to receive data - * rx_len receive data length in byte - * cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1 - * is_write_erase to indicate whether this is a write or erase - * operation, since the CPU would check permission - */ - -void esp_rom_spi_cmd_start(int spi_num, uint8_t *rx_buf, uint16_t rx_len, - uint8_t cs_en_mask, bool is_write_erase); - -/* Config opi flash pads according to efuse settings. */ - -void esp_rom_opiflash_pin_config(void); - -/* Set SPI read/write operation mode - * spi_num spi port - * mode Flash Read Mode - */ - -void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode); - -/* Set data swap mode in DTR(DDR) mode - * spi_num spi port - * wr_swap to decide whether to swap fifo data in dtr write operation - * rd_swap to decide whether to swap fifo data in dtr read operation - */ - -void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap); - -/* To send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G) - * spi_num spi port - */ - -void esp_rom_opiflash_mode_reset(int spi_num); - -/* To execute a flash operation command - * spi_num spi port - * mode Flash Read Mode - * cmd data to send in command field - * cmd_bit_len bit length of command field - * addr data to send in address field - * addr_bit_len bit length of address field - * dummy_bits bit length of dummy field - * mosi_data data buffer to be sent in mosi field - * mosi_bit_len bit length of data buffer to be sent in mosi field - * miso_data data buffer to accept data in miso field - * miso_bit_len bit length of data buffer to accept data in miso field - * cs_mark decide which cs pin to use. 0: cs0, 1: cs1 - * is_write_erase_operation to indicate whether this a write or erase - * flash operation - */ - -void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode, - uint32_t cmd, int cmd_bit_len, - uint32_t addr, int addr_bit_len, - int dummy_bits, - uint8_t *mosi_data, int mosi_bit_len, - uint8_t *miso_data, int miso_bit_len, - uint32_t cs_mask, - bool is_write_erase_operation); - -/* Send reset command to opi flash - * spi_num spi port - * mode Flash Operation Mode - */ - -void esp_rom_opiflash_soft_reset(int spi_num, - esp_rom_spiflash_read_mode_t mode); - -/* To read opi flash ID - * command format would be defined in initialization - * out_id buffer to accept id - * Return flash operation result - */ - -esp_rom_spiflash_result_t esp_rom_opiflash_read_id(uint8_t *out_id); - -/* To read opi flash status register - * command format would be defined in initialization - * Return opi flash status value - */ - -uint8_t esp_rom_opiflash_rdsr(void); - -/* Wait opi flash status register to be idle - * command format would be defined in initialization - * Return flash operation result - */ - -esp_rom_spiflash_result_t esp_rom_opiflash_wait_idle(void); - -/* To erase flash sector - * command format would be defined in initialization - * sector_num the sector to be erased - * Return flash operation result - */ - -esp_rom_spiflash_result_t -esp_rom_opiflash_erase_sector(uint32_t sector_num); - -/* Erase flash block - * command format would be defined in initialization - * block_num the block to be erased - * Return flash operation result - */ - -esp_rom_spiflash_result_t -esp_rom_opiflash_erase_block_64k(uint32_t block_num); - -/* To erase a flash area define by start address and length - * command format would be defined in initialization - * start_addr the start address to be erased - * area_len the erea length to be erased - * Return flash operation result - */ - -esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(uint32_t start_addr, - uint32_t area_len); - -/* To read data from opi flash - * command format would be defined in initialization - * flash_addr flash address to read data from - * data_addr data buffer to accept the data - * len data length to be read - * Return flash operation result - */ - -esp_rom_spiflash_result_t esp_rom_opiflash_read(uint32_t flash_addr, - void *data_addr, - int len); - -/* To write data to opi flash - * command format would be defined in initialization - * flash_addr flash address to write data to - * data_addr data buffer to write to flash - * len data length to write - * Return flash operation result - */ - -esp_rom_spiflash_result_t esp_rom_opiflash_write(uint32_t flash_addr, - const uint32_t *data_addr, - int len); - -/* Send WREN command - * command format would be defined in initialization - * arg not used, set to NULL - * Return flash operation result - */ - -esp_rom_spiflash_result_t esp_rom_opiflash_wren(void *arg); - -/* To configure SPI0 read flash command format for cache - * command format would be defined in initialization - */ - -void -esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, - const esp_rom_opiflash_spi0rd_t *cache); - -esp_rom_spiflash_result_t esp_rom_opiflash_read_raw(uint32_t flash_addr, - uint8_t *buf, int len); - -#ifdef __cplusplus -} -#endif - -#endif /* __ARCH_XTENSA_SRC_ESP32S3_ROM_ESP32S3_OPI_FLASH_H */ diff --git a/arch/xtensa/src/esp32s3/rom/esp32s3_spiflash.h b/arch/xtensa/src/esp32s3/rom/esp32s3_spiflash.h index 183f8150e15be..57bba4ebbec89 100644 --- a/arch/xtensa/src/esp32s3/rom/esp32s3_spiflash.h +++ b/arch/xtensa/src/esp32s3/rom/esp32s3_spiflash.h @@ -28,6 +28,11 @@ #include #include +#include "esp_rom_spiflash.h" +#include "rom/spi_flash.h" +#include "rom/opi_flash.h" +#include "esp_private/spi_flash_os.h" + #ifdef __cplusplus extern "C" { @@ -37,118 +42,16 @@ extern "C" * Pre-processor Definitions *****************************************************************************/ -#define PERIPHS_SPI_FLASH_CMD SPI_CMD_REG(1) -#define PERIPHS_SPI_FLASH_ADDR SPI_ADDR_REG(1) -#define PERIPHS_SPI_FLASH_CTRL SPI_CTRL_REG(1) -#define PERIPHS_SPI_FLASH_CTRL1 SPI_CTRL1_REG(1) -#define PERIPHS_SPI_FLASH_STATUS SPI_RD_STATUS_REG(1) -#define PERIPHS_SPI_FLASH_USRREG SPI_USER_REG(1) -#define PERIPHS_SPI_FLASH_USRREG1 SPI_USER1_REG(1) -#define PERIPHS_SPI_FLASH_USRREG2 SPI_USER2_REG(1) -#define PERIPHS_SPI_FLASH_C0 SPI_W0_REG(1) -#define PERIPHS_SPI_FLASH_C1 SPI_W1_REG(1) -#define PERIPHS_SPI_FLASH_C2 SPI_W2_REG(1) -#define PERIPHS_SPI_FLASH_C3 SPI_W3_REG(1) -#define PERIPHS_SPI_FLASH_C4 SPI_W4_REG(1) -#define PERIPHS_SPI_FLASH_C5 SPI_W5_REG(1) -#define PERIPHS_SPI_FLASH_C6 SPI_W6_REG(1) -#define PERIPHS_SPI_FLASH_C7 SPI_W7_REG(1) -#define PERIPHS_SPI_FLASH_TX_CRC SPI_TX_CRC_REG(1) - -#define SPI1_R_QIO_DUMMY_CYCLELEN 5 -#define SPI1_R_QIO_ADDR_BITSLEN 23 -#define SPI1_R_FAST_DUMMY_CYCLELEN 7 -#define SPI1_R_DIO_DUMMY_CYCLELEN 3 -#define SPI1_R_DIO_ADDR_BITSLEN 23 -#define SPI1_R_FAST_ADDR_BITSLEN 23 -#define SPI1_R_SIO_ADDR_BITSLEN 23 - -#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 - -#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_WRSR_2B - -/* SPI address register */ - -#define ESP_ROM_SPIFLASH_BYTES_LEN 24 -#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 -#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 64 -#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0x3f - -/* SPI status register */ - -#define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 -#define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 -#define ESP_ROM_SPIFLASH_BP0 BIT2 -#define ESP_ROM_SPIFLASH_BP1 BIT3 -#define ESP_ROM_SPIFLASH_BP2 BIT4 -#define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0 | \ - ESP_ROM_SPIFLASH_BP1 | \ - ESP_ROM_SPIFLASH_BP2) -#define ESP_ROM_SPIFLASH_QE BIT9 - /* Extra dummy for flash read */ #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M 0 #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M 1 #define ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M 2 -#define FLASH_ID_GD25LQ32C 0xC86016 - /***************************************************************************** * Public Types *****************************************************************************/ -typedef enum -{ - ESP_ROM_SPIFLASH_QIO_MODE = 0, - ESP_ROM_SPIFLASH_QOUT_MODE, - ESP_ROM_SPIFLASH_DIO_MODE, - ESP_ROM_SPIFLASH_DOUT_MODE, - ESP_ROM_SPIFLASH_FASTRD_MODE, - ESP_ROM_SPIFLASH_SLOWRD_MODE, - ESP_ROM_SPIFLASH_OPI_STR_MODE, - ESP_ROM_SPIFLASH_OPI_DTR_MODE, - ESP_ROM_SPIFLASH_OOUT_MODE, - ESP_ROM_SPIFLASH_OIO_STR_MODE, - ESP_ROM_SPIFLASH_OIO_DTR_MODE, -} esp_rom_spiflash_read_mode_t; - -typedef enum -{ - ESP_ROM_SPIFLASH_RESULT_OK, - ESP_ROM_SPIFLASH_RESULT_ERR, - ESP_ROM_SPIFLASH_RESULT_TIMEOUT -} esp_rom_spiflash_result_t; - -typedef struct -{ - uint32_t device_id; - uint32_t chip_size; /* chip size in bytes */ - uint32_t block_size; - uint32_t sector_size; - uint32_t page_size; - uint32_t status_mask; -} esp32s3_spiflash_chip_t; - -typedef struct -{ - uint8_t data_length; - uint8_t read_cmd0; - uint8_t read_cmd1; - uint8_t write_cmd; - uint16_t data_mask; - uint16_t data; -} esp_rom_spiflash_common_cmd_t; - -/* Global ROM spiflash data, as used by legacy SPI flash functions */ - -struct spiflash_legacy_data_s -{ - esp32s3_spiflash_chip_t chip; - uint8_t dummy_len_plus[3]; - uint8_t sig_matrix; -}; - /* Structure holding SPI flash access critical sections management functions. * * Flash API uses two types of functions for flash access management: @@ -330,7 +233,7 @@ void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); * Please do not call this function in SDK. * * Input Parameters: - * esp32s3_spiflash_chip_t *spi : The information for Flash, which is + * esp_rom_spiflash_chip_t *spi : The information for Flash, which is * exported from ld file. * * uint32_t *status : The pointer to which to return the Flash status value. @@ -343,7 +246,7 @@ void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); *****************************************************************************/ esp_rom_spiflash_result_t -esp_rom_spiflash_read_status(esp32s3_spiflash_chip_t *spi, +esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status); /***************************************************************************** @@ -355,7 +258,7 @@ esp_rom_spiflash_read_status(esp32s3_spiflash_chip_t *spi, * Please do not call this function in SDK. * * Input Parameters: - * esp32s3_spiflash_chip_t *spi : The information for Flash, which is + * esp_rom_spiflash_chip_t *spi : The information for Flash, which is * exported from ld file. * * uint32_t *status : The pointer to which to return the Flash status value. @@ -368,7 +271,7 @@ esp_rom_spiflash_read_status(esp32s3_spiflash_chip_t *spi, *****************************************************************************/ esp_rom_spiflash_result_t -esp32s3_spiflash_read_statushigh(esp32s3_spiflash_chip_t *spi, +esp32s3_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status); /***************************************************************************** @@ -380,7 +283,7 @@ esp32s3_spiflash_read_statushigh(esp32s3_spiflash_chip_t *spi, * Please do not call this function in SDK. * * Input Parameters: - * esp32s3_spiflash_chip_t *spi : The information for Flash, which is + * esp_rom_spiflash_chip_t *spi : The information for Flash, which is * exported from ld file. * * uint32_t status_value : Value to . @@ -393,7 +296,7 @@ esp32s3_spiflash_read_statushigh(esp32s3_spiflash_chip_t *spi, *****************************************************************************/ esp_rom_spiflash_result_t -esp32s3_spiflash_write_status(esp32s3_spiflash_chip_t *spi, +esp32s3_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); /***************************************************************************** @@ -405,7 +308,7 @@ esp32s3_spiflash_write_status(esp32s3_spiflash_chip_t *spi, * Please do not call this function in SDK. * * Input Parameters: - * esp32s3_spiflash_chip_t *spi : The information for Flash, which is + * esp_rom_spiflash_chip_t *spi : The information for Flash, which is * exported from ld file. * * uint32_t*status : The pointer to which to return the Flash status value. @@ -803,7 +706,7 @@ esp_rom_spiflash_write_encrypted(uint32_t flash_addr, * *****************************************************************************/ -esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp32s3_spiflash_chip_t +esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi); /***************************************************************************** @@ -851,7 +754,7 @@ void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, * *****************************************************************************/ -void spi_flash_guard_set(const struct spiflash_guard_funcs *funcs); +void spi_flash_guard_set(const spi_flash_guard_funcs_t *funcs); /***************************************************************************** * Name: spi_flash_write_encrypted @@ -1005,8 +908,6 @@ void spi_flash_enable_cache(uint32_t cpuid); * Public Data *****************************************************************************/ -extern struct spiflash_legacy_data_s *rom_spiflash_legacy_data; - #ifdef __cplusplus } #endif diff --git a/arch/xtensa/src/lx6/Toolchain.defs b/arch/xtensa/src/lx6/Toolchain.defs index 686dc70087734..0417bef85a288 100644 --- a/arch/xtensa/src/lx6/Toolchain.defs +++ b/arch/xtensa/src/lx6/Toolchain.defs @@ -102,7 +102,7 @@ ifeq ($(CONFIG_ARCH_INSTRUMENT_ALL),y) endif ARCHCFLAGS += -fno-common -ARCHCXXFLAGS += -fno-common -nostdinc++ +ARCHCXXFLAGS += -fno-common ARCHCFLAGS += -Wall -Wstrict-prototypes -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas ARCHCXXFLAGS += -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas @@ -111,6 +111,10 @@ ARCHCXXFLAGS += -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas # we can safely disregard warnings of the type "parameter passing for X changed in GCC 7.1." # Refer to : https://stackoverflow.com/questions/48149323/what-does-the-gcc-warning-project-parameter-passing-for-x-changed-in-gcc-7-1-m +ifneq ($(CONFIG_LIBCXXTOOLCHAIN),y) + ARCHCXXFLAGS += -nostdinc++ +endif + ifneq ($(CONFIG_ARCH_TOOLCHAIN_CLANG),y) ARCHCFLAGS += -Wno-psabi ARCHCXXFLAGS += -Wno-psabi diff --git a/arch/xtensa/src/lx7/Toolchain.defs b/arch/xtensa/src/lx7/Toolchain.defs index 6d5da909cf98d..c46fcca9d231f 100644 --- a/arch/xtensa/src/lx7/Toolchain.defs +++ b/arch/xtensa/src/lx7/Toolchain.defs @@ -106,7 +106,7 @@ ifeq ($(CONFIG_ARCH_INSTRUMENT_ALL),y) endif ARCHCFLAGS += -fno-common -ARCHCXXFLAGS += -fno-common -nostdinc++ +ARCHCXXFLAGS += -fno-common ARCHCFLAGS += -Wall -Wstrict-prototypes -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas ARCHCXXFLAGS += -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas @@ -115,6 +115,10 @@ ARCHCXXFLAGS += -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas # we can safely disregard warnings of the type "parameter passing for X changed in GCC 7.1." # Refer to : https://stackoverflow.com/questions/48149323/what-does-the-gcc-warning-project-parameter-passing-for-x-changed-in-gcc-7-1-m +ifneq ($(CONFIG_LIBCXXTOOLCHAIN),y) + ARCHCXXFLAGS += -nostdinc++ +endif + ifneq ($(CONFIG_ARCH_TOOLCHAIN_CLANG),y) ARCHCFLAGS += -Wno-psabi ARCHCXXFLAGS += -Wno-psabi diff --git a/arch/z16/include/irq.h b/arch/z16/include/irq.h index c153db2448013..37b5fbcb90b78 100644 --- a/arch/z16/include/irq.h +++ b/arch/z16/include/irq.h @@ -72,7 +72,7 @@ chipreg_t up_getsp(void); #ifndef __ASSEMBLY__ /* This holds a references to the current interrupt level - * register storage structure. If is non-NULL only during + * register storage structure. It is non-NULL only during * interrupt processing. */ diff --git a/arch/z16/src/Makefile b/arch/z16/src/Makefile index e1fcce7738de5..3456da90662fc 100644 --- a/arch/z16/src/Makefile +++ b/arch/z16/src/Makefile @@ -18,7 +18,7 @@ # ############################################################################ -include $(TOPDIR)/Make.defs +include $(TOPDIR)/tools/apps-or-nuttx-Make.defs include chip/Make.defs COMPILER = ${shell basename "$(CC)"} diff --git a/arch/z16/src/common/z16_exit.c b/arch/z16/src/common/z16_exit.c index af5fbc7f1e71d..85d274bf34c9d 100644 --- a/arch/z16/src/common/z16_exit.c +++ b/arch/z16/src/common/z16_exit.c @@ -60,8 +60,6 @@ void up_exit(int status) enter_critical_section(); - sinfo("TCB=%p exiting\n", tcb); - nxsched_dumponexit(); /* Destroy the task at the head of the ready to run list. */ diff --git a/arch/z16/src/common/z16_initialize.c b/arch/z16/src/common/z16_initialize.c index ad206c13ec708..0ab242f602235 100644 --- a/arch/z16/src/common/z16_initialize.c +++ b/arch/z16/src/common/z16_initialize.c @@ -33,7 +33,7 @@ ****************************************************************************/ /* This holds a references to the current interrupt level - * register storage structure. If is non-NULL only during + * register storage structure. It is non-NULL only during * interrupt processing. */ diff --git a/arch/z16/src/z16f/z16f_serial.c b/arch/z16/src/z16f/z16f_serial.c index a177e98401c63..82d3933066489 100644 --- a/arch/z16/src/z16f/z16f_serial.c +++ b/arch/z16/src/z16f/z16f_serial.c @@ -213,7 +213,7 @@ static uart_dev_t g_uart1port; static uint8_t z16f_disableuartirq(struct uart_dev_s *dev) { struct z16f_uart_s *priv = (struct z16f_uart_s *)dev->priv; - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(NULL); uint8_t state = priv->rxenabled ? STATE_RXENABLED : STATE_DISABLED | priv->txenabled ? STATE_TXENABLED : @@ -222,7 +222,7 @@ static uint8_t z16f_disableuartirq(struct uart_dev_s *dev) z16f_txint(dev, false); z16f_rxint(dev, false); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); return state; } @@ -232,12 +232,12 @@ static uint8_t z16f_disableuartirq(struct uart_dev_s *dev) static void z16f_restoreuartirq(struct uart_dev_s *dev, uint8_t state) { - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(NULL); z16f_txint(dev, (state & STATE_TXENABLED) ? true : false); z16f_rxint(dev, (state & STATE_RXENABLED) ? true : false); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/z80/src/Makefile b/arch/z80/src/Makefile index b99edba0e252a..3fe81ea10e1b2 100644 --- a/arch/z80/src/Makefile +++ b/arch/z80/src/Makefile @@ -20,7 +20,7 @@ # Makefile fragments -include $(TOPDIR)/Make.defs +include $(TOPDIR)/tools/apps-or-nuttx-Make.defs include chip/Make.defs # Compiler-Dependent Make: SDCC, Clang, or ZiLOG ZDS-II diff --git a/arch/z80/src/common/z80_exit.c b/arch/z80/src/common/z80_exit.c index a6afa43261942..9acbee62c325e 100644 --- a/arch/z80/src/common/z80_exit.c +++ b/arch/z80/src/common/z80_exit.c @@ -62,8 +62,6 @@ void up_exit(int status) enter_critical_section(); - sinfo("TCB=%p exiting\n", tcb); - nxsched_dumponexit(); /* Destroy the task at the head of the ready to run list. */ diff --git a/arch/z80/src/common/z80_initialize.c b/arch/z80/src/common/z80_initialize.c index 235974fc17f37..7415cc12cd2fa 100644 --- a/arch/z80/src/common/z80_initialize.c +++ b/arch/z80/src/common/z80_initialize.c @@ -34,7 +34,7 @@ ****************************************************************************/ /* This holds a references to the current interrupt level register storage - * structure. If is non-NULL only during interrupt processing. + * structure. It is non-NULL only during interrupt processing. */ volatile FAR chipreg_t *g_current_regs; diff --git a/arch/z80/src/ez80/switch.h b/arch/z80/src/ez80/switch.h index b404e02318b6c..ee51ccc0a2a02 100644 --- a/arch/z80/src/ez80/switch.h +++ b/arch/z80/src/ez80/switch.h @@ -115,7 +115,7 @@ #ifndef __ASSEMBLY__ /* This holds a references to the current interrupt level register - * storage structure. If is non-NULL only during interrupt processing. + * storage structure. It is non-NULL only during interrupt processing. */ extern volatile chipreg_t *g_current_regs; diff --git a/arch/z80/src/z180/switch.h b/arch/z80/src/z180/switch.h index 090d7e001c22e..fd9a5f06679b0 100644 --- a/arch/z80/src/z180/switch.h +++ b/arch/z80/src/z180/switch.h @@ -170,7 +170,7 @@ #ifndef __ASSEMBLY__ /* This holds a references to the current interrupt level register - * storage structure. If is non-NULL only during interrupt processing. + * storage structure. It is non-NULL only during interrupt processing. */ extern volatile chipreg_t *g_current_regs; diff --git a/arch/z80/src/z8/z8_serial.c b/arch/z80/src/z8/z8_serial.c index 31c2e7a91b6a6..e997a254cd05b 100644 --- a/arch/z80/src/z8/z8_serial.c +++ b/arch/z80/src/z8/z8_serial.c @@ -253,7 +253,7 @@ static inline uint8_t z8_getuart(FAR struct z8_uart_s *priv, uint8_t offset) static uint8_t z8_disableuartirq(FAR struct uart_dev_s *dev) { struct z8_uart_s *priv = (struct z8_uart_s *)dev->priv; - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(NULL); uint8_t state = priv->rxenabled ? STATE_RXENABLED : STATE_DISABLED | \ priv->txenabled ? @@ -262,7 +262,7 @@ static uint8_t z8_disableuartirq(FAR struct uart_dev_s *dev) z8_txint(dev, false); z8_rxint(dev, false); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); return state; } @@ -272,12 +272,12 @@ static uint8_t z8_disableuartirq(FAR struct uart_dev_s *dev) static void z8_restoreuartirq(FAR struct uart_dev_s *dev, uint8_t state) { - irqstate_t flags = enter_critical_section(); + irqstate_t flags = spin_lock_irqsave(NULL); z8_txint(dev, (state & STATE_TXENABLED) ? true : false); z8_rxint(dev, (state & STATE_RXENABLED) ? true : false); - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } /**************************************************************************** diff --git a/arch/z80/src/z80/switch.h b/arch/z80/src/z80/switch.h index a0db8420405f3..6b712c1c0f402 100644 --- a/arch/z80/src/z80/switch.h +++ b/arch/z80/src/z80/switch.h @@ -114,7 +114,7 @@ #ifndef __ASSEMBLY__ /* This holds a references to the current interrupt level register - * storage structure. If is non-NULL only during interrupt processing. + * storage structure. It is non-NULL only during interrupt processing. */ extern volatile chipreg_t *g_current_regs; diff --git a/binfmt/binfmt_execmodule.c b/binfmt/binfmt_execmodule.c index 3859a0bfe47ef..5b9f2fe694f94 100644 --- a/binfmt/binfmt_execmodule.c +++ b/binfmt/binfmt_execmodule.c @@ -120,9 +120,6 @@ static void exec_swap(FAR struct tcb_s *ptcb, FAR struct tcb_s *chtcb) int chndx; pid_t pid; irqstate_t flags; -#ifdef HAVE_GROUP_MEMBERS - FAR pid_t *tg_members; -#endif #ifdef CONFIG_SCHED_HAVE_PARENT # ifdef CONFIG_SCHED_CHILD_STATUS FAR struct child_status_s *tg_children; @@ -139,13 +136,13 @@ static void exec_swap(FAR struct tcb_s *ptcb, FAR struct tcb_s *chtcb) pndx = PIDHASH(ptcb->pid); chndx = PIDHASH(chtcb->pid); - DEBUGASSERT(g_pidhash[pndx]); - DEBUGASSERT(g_pidhash[chndx]); + DEBUGASSERT(nxsched_pidhash()[pndx]); + DEBUGASSERT(nxsched_pidhash()[chndx]); - /* Exchange g_pidhash index */ + /* Exchange nxsched_pidhash() index */ - g_pidhash[pndx] = chtcb; - g_pidhash[chndx] = ptcb; + nxsched_pidhash()[pndx] = chtcb; + nxsched_pidhash()[chndx] = ptcb; /* Exchange pid */ @@ -163,12 +160,6 @@ static void exec_swap(FAR struct tcb_s *ptcb, FAR struct tcb_s *chtcb) chtcb->group->tg_ppid = ptcb->group->tg_ppid; ptcb->group->tg_ppid = pid; -#ifdef HAVE_GROUP_MEMBERS - tg_members = chtcb->group->tg_members; - chtcb->group->tg_members = ptcb->group->tg_members; - ptcb->group->tg_members = tg_members; -#endif - #ifdef CONFIG_SCHED_HAVE_PARENT # ifdef CONFIG_SCHED_CHILD_STATUS tg_children = chtcb->group->tg_children; @@ -303,9 +294,11 @@ int exec_module(FAR struct binary_s *binp, } #endif - /* Note that tcb->flags are not modified. 0=normal task */ + /* Note that tcb->cmn.flags are not modified. 0=normal task */ + + /* tcb->cmn.flags |= TCB_FLAG_TTYPE_TASK; */ - /* tcb->flags |= TCB_FLAG_TTYPE_TASK; */ + tcb->cmn.flags |= TCB_FLAG_FREE_TCB; /* Initialize the task */ diff --git a/binfmt/binfmt_loadmodule.c b/binfmt/binfmt_loadmodule.c index f6ccb60c975cf..6537e6900cfa6 100644 --- a/binfmt/binfmt_loadmodule.c +++ b/binfmt/binfmt_loadmodule.c @@ -194,7 +194,7 @@ int load_module(FAR struct binary_s *bin, FAR const char *filename, /* Free the allocated fullpath */ - kmm_free(fullpath); + lib_free(fullpath); /* Break out of the loop with ret == OK on success */ diff --git a/binfmt/libelf/libelf_bind.c b/binfmt/libelf/libelf_bind.c index d6a26305e0047..743ac71aebde1 100644 --- a/binfmt/libelf/libelf_bind.c +++ b/binfmt/libelf/libelf_bind.c @@ -496,7 +496,7 @@ static int elf_relocateadd(FAR struct elf_loadinfo_s *loadinfo, int relidx, if (ret == -ESRCH) { - berr("Section %d reloc %d: " + bwarn("Section %d reloc %d: " "Undefined symbol[%d] has no name: %d\n", relidx, i, symidx, ret); } diff --git a/binfmt/libelf/libelf_coredump.c b/binfmt/libelf/libelf_coredump.c index 004d33fee13fe..4e3e85783ac37 100644 --- a/binfmt/libelf/libelf_coredump.c +++ b/binfmt/libelf/libelf_coredump.c @@ -91,7 +91,7 @@ static int elf_emit(FAR struct elf_dumpinfo_s *cinfo, { FAR const uint8_t *ptr = buf; size_t total = len; - int ret; + int ret = 0; while (total > 0) { @@ -122,7 +122,7 @@ static int elf_emit_align(FAR struct elf_dumpinfo_s *cinfo) ELF_PAGESIZE) - cinfo->stream->nput; unsigned char null[256]; off_t total = align; - off_t ret; + off_t ret = 0; memset(null, 0, sizeof(null)); @@ -187,9 +187,9 @@ static int elf_get_ntcb(void) int count = 0; int i; - for (i = 0; i < g_npidhash; i++) + for (i = 0; i < nxsched_npidhash(); i++) { - if (g_pidhash[i] != NULL) + if (nxsched_pidhash()[i] != NULL) { count++; } @@ -313,11 +313,11 @@ static void elf_emit_note(FAR struct elf_dumpinfo_s *cinfo) if (cinfo->pid == INVALID_PROCESS_ID) { - for (i = 0; i < g_npidhash; i++) + for (i = 0; i < nxsched_npidhash(); i++) { - if (g_pidhash[i] != NULL) + if (nxsched_pidhash()[i] != NULL) { - elf_emit_tcb_note(cinfo, g_pidhash[i]); + elf_emit_tcb_note(cinfo, nxsched_pidhash()[i]); } } } @@ -395,11 +395,11 @@ static void elf_emit_stack(FAR struct elf_dumpinfo_s *cinfo) if (cinfo->pid == INVALID_PROCESS_ID) { - for (i = 0; i < g_npidhash; i++) + for (i = 0; i < nxsched_npidhash(); i++) { - if (g_pidhash[i] != NULL) + if (nxsched_pidhash()[i] != NULL) { - elf_emit_tcb_stack(cinfo, g_pidhash[i]); + elf_emit_tcb_stack(cinfo, nxsched_pidhash()[i]); } } } @@ -520,11 +520,11 @@ static void elf_emit_phdr(FAR struct elf_dumpinfo_s *cinfo, if (cinfo->pid == INVALID_PROCESS_ID) { - for (i = 0; i < g_npidhash; i++) + for (i = 0; i < nxsched_npidhash(); i++) { - if (g_pidhash[i] != NULL) + if (nxsched_pidhash()[i] != NULL) { - elf_emit_tcb_phdr(cinfo, g_pidhash[i], &phdr, &offset); + elf_emit_tcb_phdr(cinfo, nxsched_pidhash()[i], &phdr, &offset); } } } diff --git a/binfmt/libelf/libelf_symbols.c b/binfmt/libelf/libelf_symbols.c index cfdd41d15e77a..bbc232cc760d5 100644 --- a/binfmt/libelf/libelf_symbols.c +++ b/binfmt/libelf/libelf_symbols.c @@ -76,7 +76,7 @@ static int elf_symname(FAR struct elf_loadinfo_s *loadinfo, if (sym->st_name == 0) { - berr("Symbol has no name\n"); + bwarn("Symbol has no name\n"); return -ESRCH; } @@ -292,7 +292,7 @@ int elf_symvalue(FAR struct elf_loadinfo_s *loadinfo, FAR Elf_Sym *sym, * indicate the nameless symbol. */ - berr("SHN_UNDEF: Failed to get symbol name: %d\n", ret); + bwarn("SHN_UNDEF: Failed to get symbol name: %d\n", ret); return ret; } diff --git a/boards/Board.mk b/boards/Board.mk index e0cc563a3e7c2..f355bc1fe4056 100644 --- a/boards/Board.mk +++ b/boards/Board.mk @@ -30,12 +30,12 @@ $(RCOBJS): $(ETCDIR)$(DELIM)%: % $(Q) mkdir -p $(dir $@) $(call PREPROCESS, $<, $@) -$(ETCSRC): $(addprefix $(BOARD_DIR)$(DELIM)src$(DELIM),$(RCRAWS)) $(RCOBJS) +$(ETCSRC): $(foreach raw,$(RCRAWS), $(if $(wildcard $(BOARD_DIR)$(DELIM)src$(DELIM)$(raw)), $(BOARD_DIR)$(DELIM)src$(DELIM)$(raw), $(if $(wildcard $(BOARD_COMMON_DIR)$(DELIM)$(raw)), $(BOARD_COMMON_DIR)$(DELIM)$(raw), $(BOARD_DIR)$(DELIM)src$(DELIM)$(raw)))) $(RCOBJS) $(foreach raw, $(RCRAWS), \ $(shell rm -rf $(ETCDIR)$(DELIM)$(raw)) \ $(shell mkdir -p $(dir $(ETCDIR)$(DELIM)$(raw))) \ - $(shell cp -rfp $(BOARD_DIR)$(DELIM)src$(DELIM)$(raw) $(ETCDIR)$(DELIM)$(raw))) - $(Q) genromfs -f romfs.img -d $(ETCDIR)$(DELIM)$(CONFIG_NSH_ROMFSMOUNTPT) -V "NSHInitVol" + $(shell cp -rfp $(if $(wildcard $(BOARD_DIR)$(DELIM)src$(DELIM)$(raw)), $(BOARD_DIR)$(DELIM)src$(DELIM)$(raw), $(if $(wildcard $(BOARD_COMMON_DIR)$(DELIM)$(raw)), $(BOARD_COMMON_DIR)$(DELIM)$(raw), $(BOARD_DIR)$(DELIM)src$(DELIM)$(raw))) $(ETCDIR)$(DELIM)$(raw))) + $(Q) genromfs -f romfs.img -d $(ETCDIR)$(DELIM)$(CONFIG_ETC_ROMFSMOUNTPT) -V "NSHInitVol" $(Q) echo "#include " > $@ $(Q) xxd -i romfs.img | sed -e "s/^unsigned char/const unsigned char aligned_data(4)/g" >> $@ $(Q) rm romfs.img diff --git a/boards/Kconfig b/boards/Kconfig index 720b6120678f7..1a2b68fb23d23 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -423,7 +423,7 @@ config ARCH_BOARD_FRANZININHO_WIFI config ARCH_BOARD_ESP32S3_DEVKIT bool "Espressif ESP32-S3 DevKit" - depends on ARCH_CHIP_ESP32S3WROOM1 || ARCH_CHIP_ESP32S3MINI1 || ARCH_CHIP_ESP32S3WROOM2 + depends on ARCH_CHIP_ESP32S3WROOM1 || ARCH_CHIP_ESP32S3MINI1 || ARCH_CHIP_ESP32S3WROOM2 || ARCH_CHIP_ESP32S3WROOM2_32M select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ @@ -447,7 +447,7 @@ config ARCH_BOARD_ESP32S3_EYE config ARCH_BOARD_ESP32S3_LCD_EV bool "Espressif ESP32-S3-LCD-EV Board" - depends on ARCH_CHIP_ESP32S3WROOM2 + depends on ARCH_CHIP_ESP32S3WROOM2 || ARCH_CHIP_ESP32S3WROOM2_32M select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ @@ -465,7 +465,7 @@ config ARCH_BOARD_ESP32S3_LCD_EV config ARCH_BOARD_ESP32S3_BOX bool "Espressif ESP32-S3-BOX" - depends on ARCH_CHIP_ESP32S3WROOM2 + depends on ARCH_CHIP_ESP32S3WROOM2 || ARCH_CHIP_ESP32S3WROOM2_32M select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ @@ -487,15 +487,23 @@ config ARCH_BOARD_ESP32S3_MEADOW The ESP32-S3-Meadow is a small-sized board produced by WildernessLabs featuring the ESP32-S3 CPU with 32MiB Octal SPI PSRAM and 64 MiB flash. -config ARCH_BOARD_ESP32C6_GENERIC - bool "Espressif ESP32-C6 Generic DevKit" - depends on ESPRESSIF_ESP32C6 +config ARCH_BOARD_ESP32C6_DEVKITC + bool "Espressif ESP32-C6-DevKitC-1" + depends on ARCH_CHIP_ESP32C6WROOM1 select ARCH_HAVE_BUTTONS select ARCH_HAVE_IRQBUTTONS ---help--- - The ESP32-C6 DevKit features the ESP32-C6 CPU with a RISC-V core. + The ESP32-C6 DevKitC-1 features the ESP32-C6 CPU with a RISC-V core. -config ARCH_BOARD_ESP32H2_GENERIC +config ARCH_BOARD_ESP32C6_DEVKITM + bool "Espressif ESP32-C6 DevKitM-1" + depends on ARCH_CHIP_ESP32C6MINI1 + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + The ESP32-C6 DevKitM-1 features the ESP32-C6 CPU with a RISC-V core. + +config ARCH_BOARD_ESP32H2_DEVKIT bool "Espressif ESP32-H2 Generic DevKit" depends on ESPRESSIF_ESP32H2 select ARCH_HAVE_BUTTONS @@ -510,15 +518,6 @@ config ARCH_BOARD_ET_STM32_STAMP The ET-STM32 Stamp features the STM32F103RET6 (Cortex M3) microcontroller. For board details, see: https://www.futurlec.com/ET-STM32_Stamp.shtml -config ARCH_BOARD_ESP32C6_DEVKIT - bool "Espressif ESP32-C6 DevKit" - depends on ARCH_CHIP_ESP32C6MINI1 || ARCH_CHIP_ESP32C6WROOM1 - ---help--- - The ESP32-C6 DevKit features the ESP32-C6 CPU with a RISC-V core. - It comes in two flavors, the ESP32-C6-DevKitM-1 and the ESP32-C6-DevKitC-02. - The ESP32-C6-DevKitM-1 version contains the ESP32-C6-MINI-1 module and the - ESP32-C6-DevKitC-02 version the ESP32-C6-WROOM-1. - config ARCH_BOARD_EZ80F910200KITG bool "ZiLOG ez80f910200kitg development kit" depends on ARCH_CHIP_EZ80F91 @@ -647,6 +646,25 @@ config ARCH_BOARD_GD32F450ZK_EVAL ---help--- GD32 MCU GD32F450ZK-EVAL board based on the GD32F4 GD32F450ZKT6 MCU. +config ARCH_BOARD_GD32F450ZK_AIOTBOX + bool "GD32 MCU GD32F450ZK-AIOTBOX" + depends on ARCH_CHIP_GD32F450ZK + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + GD32 MCU GD32F450ZK-AIOTBOX board based on the GD32F4 GD32F450ZKT6 MCU. + +config ARCH_BOARD_GD32F470ZK_AIOTBOX + bool "GD32 MCU GD32F470ZK-AIOTBOX" + depends on ARCH_CHIP_GD32F470ZK + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + GD32 MCU GD32F470ZK-AIOTBOX board based on the GD32F4 GD32F470ZKT6 MCU. + + config ARCH_BOARD_GD32F470ZK_EVAL bool "GD32 MCU GD32F470ZK" depends on ARCH_CHIP_GD32F470ZK @@ -1698,6 +1716,15 @@ config ARCH_BOARD_NUCLEO_G071RB This is a minimal configuration that supports low-level test of the Nucleo G071RB in the NuttX source tree. +config ARCH_BOARD_WEACT_STM32H743 + bool "WeAct Studio STM32H743" + depends on ARCH_CHIP_STM32H743VI + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + This is WeAct MiniSTM32H7xx (STM32H743VIT6) board. + config ARCH_BOARD_NUCLEO_H743ZI bool "STM32H743 Nucleo H743ZI" depends on ARCH_CHIP_STM32H743ZI @@ -1740,6 +1767,12 @@ config ARCH_BOARD_LINUM_STM32H753BI ---help--- The Linum board is based on the STMicro STM32H753BI MCU. +config ARCH_BOARD_OPENH743I + bool "Waveshare OpenH743I board" + depends on ARCH_CHIP_STM32H743II + ---help--- + Waveshare OpenH743I board based on the STMicro STM32H743II MCU. + config ARCH_BOARD_NUCLEO_L152RE bool "STM32L152 Nucleo L152RE" depends on ARCH_CHIP_STM32L152RE @@ -1828,7 +1861,7 @@ config ARCH_BOARD_QEMU_I486 config ARCH_BOARD_INTEL64_QEMU bool "Intel64 for Qemu simulator" - depends on ARCH_X86_64 || ARCH_INTEL64 + depends on ARCH_CHIP_INTEL64_QEMU ---help--- Port of NuttX to QEMU in intel64 mode. This port will also run on real generic Intel64 hardware. @@ -1836,6 +1869,9 @@ config ARCH_BOARD_INTEL64_QEMU config ARCH_BOARD_RASPBERRYPI_PICO bool "Raspberry Pi Pico board (not W)" depends on ARCH_CHIP_RP2040 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS ---help--- This is a port to the Raspberry Pi Pico board. @@ -1888,6 +1924,16 @@ config ARCH_BOARD_WAVESHARE_RP2040_LCD_1_28 This is a port to the Waveshare RP2040 LCD 1.28 board. Support is derived from Raspberry Pi Pico support. +config ARCH_BOARD_W5500_EVB_PICO + bool "WIZnet W5500-EVB-Pico board" + depends on ARCH_CHIP_RP2040 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + This is a port to the WIZnet W5500-EVB-Pico board. + Support is derived from Raspberry Pi Pico support. + config ARCH_BOARD_RX65N bool "RX65N renesas board" depends on ARCH_CHIP_R5F565NEDDFC @@ -2038,6 +2084,14 @@ config ARCH_BOARD_MR_CANHUBK3 This options selects support for NuttX on the NXP MR-CANHUBK3 board featuring the S32K344 Cortex-M7. +config ARCH_BOARD_MPS3_AN547 + bool "Arm MPS3 AN547" + depends on ARCH_CHIP_MPS3_AN547 + select ARCH_HAVE_IRQBUTTONS + ---help--- + This options selects support for NuttX on the MPS3 AN547 + board featuring the Cortex-M55. + config ARCH_BOARD_SABRE_6QUAD bool "NXP/Freescale i.MX6 Sabre-6Quad board" depends on ARCH_CHIP_IMX6_6QUAD @@ -2048,6 +2102,12 @@ config ARCH_BOARD_SABRE_6QUAD This options selects support for NuttX on the NXP/Freescale Sabre board featuring the iMX 6Quad CPU. +config ARCH_BOARD_TC397 + bool "Infineon's AURIX TC397 board: KIT_A2G_TC397_5V_TFT" + ---help--- + This options selects support for NuttX on the Infineon's AURIX board + board featuring the TC397 6Quad CPU. + config ARCH_BOARD_QEMU_ARMV7A bool "Qemu ARMv7a CPUs board" depends on ARCH_CHIP_QEMU_ARM @@ -2115,6 +2175,14 @@ config ARCH_BOARD_IMX8QM_MEK This options selects support for NuttX on the NXP i.MX8 QuadMax CPUs MEK configure board with ARM Cortex-A53. +config ARCH_BOARD_IMX93_EVK + bool "NXP i.MX93 CPUs EVK board" + depends on ARCH_CHIP_IMX93 + select ARCH_HAVE_IRQBUTTONS + ---help--- + This options selects support for NuttX on the NXP i.MX93 CPUs EVK + board with ARM Cortex-A55. + config ARCH_BOARD_SAMA5D2_XULT bool "Atmel SAMA5D2 Xplained Ultra development board" depends on ARCH_CHIP_ATSAMA5D27 @@ -2868,6 +2936,15 @@ config ARCH_BOARD_XMC4700RELAX ---help--- Infineon XMC4700 Relax +config ARCH_BOARD_XMC4800RELAX + bool "Infineon XMC4800 Relax" + depends on ARCH_CHIP_XMC4800 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + Infineon XMC4800 Relax + config ARCH_BOARD_VERDIN_MX8MP bool "Toradex Verdin i.MX8MP" depends on ARCH_CHIP_MX8MP @@ -2976,6 +3053,14 @@ config ARCH_BOARD_S698PM_DKIT ---help--- none +config ARCH_BOARD_HPM6360EVK + bool "Hpmicro hpm6360evk" + depends on ARCH_CHIP_HPM6360IPA + select ARCH_HAVE_LEDS + ---help--- + This is the board configuration for the port of NuttX to the Hpmicro hpm6750evk2 + board. This board features the RISC-V hpm6340. + config ARCH_BOARD_HPM6750EVK2 bool "Hpmicro hpm6750evk2" depends on ARCH_CHIP_HPM6750 @@ -3114,9 +3199,9 @@ config ARCH_BOARD default "esp32s3-meadow" if ARCH_BOARD_ESP32S3_MEADOW default "esp32s3-lcd-ev" if ARCH_BOARD_ESP32S3_LCD_EV default "esp32s3-box" if ARCH_BOARD_ESP32S3_BOX - default "esp32c6-devkit" if ARCH_BOARD_ESP32C6_DEVKIT - default "esp32c6-generic" if ARCH_BOARD_ESP32C6_GENERIC - default "esp32h2-generic" if ARCH_BOARD_ESP32H2_GENERIC + default "esp32c6-devkitc" if ARCH_BOARD_ESP32C6_DEVKITC + default "esp32c6-devkitm" if ARCH_BOARD_ESP32C6_DEVKITM + default "esp32h2-devkit" if ARCH_BOARD_ESP32H2_DEVKIT default "et-stm32-stamp" if ARCH_BOARD_ET_STM32_STAMP default "tlsr8278adk80d" if ARCH_BOARD_TLSR8278ADK80D default "ez80f910200kitg" if ARCH_BOARD_EZ80F910200KITG @@ -3131,7 +3216,9 @@ config ARCH_BOARD default "freedom-kl25z" if ARCH_BOARD_FREEDOM_KL25Z default "freedom-kl26z" if ARCH_BOARD_FREEDOM_KL26Z default "gd32f450zk-eval" if ARCH_BOARD_GD32F450ZK_EVAL + default "gd32f450zk-aiotbox" if ARCH_BOARD_GD32F450ZK_AIOTBOX default "gd32f470zk-eval" if ARCH_BOARD_GD32F470ZK_EVAL + default "gd32f470zk-aiotbox" if ARCH_BOARD_GD32F470ZK_AIOTBOX default "gd32f470ik-eval" if ARCH_BOARD_GD32F470IK_EVAL default "hifive1-revb" if ARCH_BOARD_HIFIVE1_REVB default "hymini-stm32v" if ARCH_BOARD_HYMINI_STM32V @@ -3209,11 +3296,13 @@ config ARCH_BOARD default "stm32g071b-disco" if ARCH_BOARD_STM32G071B_DISCO default "nucleo-g070rb" if ARCH_BOARD_NUCLEO_G070RB default "nucleo-g071rb" if ARCH_BOARD_NUCLEO_G071RB + default "weact-stm32h743" if ARCH_BOARD_WEACT_STM32H743 default "nucleo-h743zi" if ARCH_BOARD_NUCLEO_H743ZI default "nucleo-h743zi2" if ARCH_BOARD_NUCLEO_H743ZI2 default "nucleo-h745zi" if ARCH_BOARD_NUCLEO_H745ZI default "stm32h745i-disco" if ARCH_BOARD_STM32H745I_DISCO default "linum-stm32h753bi" if ARCH_BOARD_LINUM_STM32H753BI + default "openh743i" if ARCH_BOARD_OPENH743I default "nucleo-l073rz" if ARCH_BOARD_NUCLEO_L073RZ default "nucleo-l152re" if ARCH_BOARD_NUCLEO_L152RE default "nucleo-l432kc" if ARCH_BOARD_NUCLEO_L432KC @@ -3249,7 +3338,7 @@ config ARCH_BOARD default "pic32mx7mmb" if ARCH_BOARD_PIC32MX7MMB default "pic32mz-starterkit" if ARCH_BOARD_PIC32MZ_STARTERKIT default "qemu-i486" if ARCH_BOARD_QEMU_I486 - default "intel64-qemu" if ARCH_BOARD_INTEL64_QEMU + default "qemu-intel64" if ARCH_BOARD_INTEL64_QEMU default "raspberrypi-pico" if ARCH_BOARD_RASPBERRYPI_PICO default "raspberrypi-pico-w" if ARCH_BOARD_RASPBERRYPI_PICO_W default "pimoroni-tiny2040" if ARCH_BOARD_PIMORONI_TINY2040 @@ -3258,6 +3347,7 @@ config ARCH_BOARD default "adafruit-kb2040" if ARCH_BOARD_ADAFRUIT_KB2040 default "adafruit-qt-py-rp2040" if ARCH_BOARD_ADAFRUIT_QT_PY_RP2040 default "waveshare-rp2040-lcd-1.28" if ARCH_BOARD_WAVESHARE_RP2040_LCD_1_28 + default "w5500-evb-pico" if ARCH_BOARD_W5500_EVB_PICO default "rx65n" if ARCH_BOARD_RX65N default "rx65n-rsk1mb" if ARCH_BOARD_RX65N_RSK1MB default "rx65n-rsk2mb" if ARCH_BOARD_RX65N_RSK2MB @@ -3270,12 +3360,14 @@ config ARCH_BOARD default "s32k148evb" if ARCH_BOARD_S32K148EVB default "s32k344evb" if ARCH_BOARD_S32K344EVB default "mr-canhubk3" if ARCH_BOARD_MR_CANHUBK3 + default "mps3-an547" if ARCH_BOARD_MPS3_AN547 default "rv32m1-vega" if ARCH_BOARD_RV32M1_VEGA default "rv-virt" if ARCH_BOARD_QEMU_RV_VIRT default "star64" if ARCH_BOARD_JH7110_STAR64 default "canmv230" if ARCH_BOARD_K230_CANMV default "ox64" if ARCH_BOARD_BL808_OX64 default "sabre-6quad" if ARCH_BOARD_SABRE_6QUAD + default "tc397" if ARCH_BOARD_TC397 default "qemu-armv7a" if ARCH_BOARD_QEMU_ARMV7A default "qemu-armv8a" if ARCH_BOARD_QEMU_ARMV8A default "pinephone" if ARCH_BOARD_PINEPHONE @@ -3284,6 +3376,7 @@ config ARCH_BOARD default "fvp-armv8r" if ARCH_BOARD_FVP_ARMV8R default "fvp-armv8r-aarch32" if ARCH_BOARD_FVP_ARMV8R_AARCH32 default "imx8qm-mek" if ARCH_BOARD_IMX8QM_MEK + default "imx93-evk" if ARCH_BOARD_IMX93_EVK default "sama5d2-xult" if ARCH_BOARD_SAMA5D2_XULT default "giant-board" if ARCH_BOARD_GIANT_BOARD default "jupiter-nano" if ARCH_BOARD_JUPITER_NANO @@ -3364,6 +3457,7 @@ config ARCH_BOARD default "viewtool-stm32f107" if ARCH_BOARD_VIEWTOOL_STM32F107 default "xmc4500-relax" if ARCH_BOARD_XMC4500RELAX default "xmc4700-relax" if ARCH_BOARD_XMC4700RELAX + default "xmc4800-relax" if ARCH_BOARD_XMC4800RELAX default "verdin-mx8mp" if ARCH_BOARD_VERDIN_MX8MP default "z16f2800100zcog" if ARCH_BOARD_Z16F2800100ZCOG default "z20x" if ARCH_BOARD_Z20X @@ -3379,6 +3473,7 @@ config ARCH_BOARD default "xx3803" if ARCH_BOARD_XX3803 default "xx3823" if ARCH_BOARD_XX3823 default "s698pm-dkit" if ARCH_BOARD_S698PM_DKIT + default "hpm6360evk" if ARCH_BOARD_HPM6360EVK default "hpm6750evk2" if ARCH_BOARD_HPM6750EVK2 default "at32f437-mini" if ARCH_BOARD_AT32F437_MINI @@ -3476,6 +3571,12 @@ endif if ARCH_BOARD_SABRE_6QUAD source "boards/arm/imx6/sabre-6quad/Kconfig" endif +if ARCH_BOARD_TC397 +source "boards/tricore/tc3xx/tc397/Kconfig" +endif +if ARCH_BOARD_MPS3_AN547 +source "boards/arm/mps/mps3-an547/Kconfig" +endif if ARCH_BOARD_QEMU_ARMV7A source "boards/arm/qemu/qemu-armv7a/Kconfig" endif @@ -3497,6 +3598,9 @@ endif if ARCH_BOARD_IMX8QM_MEK source "boards/arm64/imx8/imx8qm-mek/Kconfig" endif +if ARCH_BOARD_IMX93_EVK +source "boards/arm64/imx9/imx93-evk/Kconfig" +endif if ARCH_BOARD_IMXRT1020_EVK source "boards/arm/imxrt/imxrt1020-evk/Kconfig" endif @@ -3545,9 +3649,15 @@ endif if ARCH_BOARD_GD32F450ZK_EVAL source "boards/arm/gd32f4/gd32f450zk-eval/Kconfig" endif +if ARCH_BOARD_GD32F450ZK_AIOTBOX +source "boards/arm/gd32f4/gd32f450zk-aiotbox/Kconfig" +endif if ARCH_BOARD_GD32F470ZK_EVAL source "boards/arm/gd32f4/gd32f470zk-eval/Kconfig" endif +if ARCH_BOARD_GD32F470ZK_AIOTBOX +source "boards/arm/gd32f4/gd32f470zk-aiotbox/Kconfig" +endif if ARCH_BOARD_GD32F470IK_EVAL source "boards/arm/gd32f4/gd32f470ik-eval/Kconfig" endif @@ -3650,6 +3760,15 @@ endif if ARCH_BOARD_NRF52840_DK source "boards/arm/nrf52/nrf52840-dk/Kconfig" endif +if ARCH_BOARD_THINGY52 +source "boards/arm/nrf52/thingy52/Kconfig" +endif +if ARCH_BOARD_THINGY91_NRF52 +source "boards/arm/nrf52/thingy91-nrf52/Kconfig" +endif +if ARCH_BOARD_NRF9160_DK_NRF52 +source "boards/arm/nrf52/nrf9160-dk-nrf52/Kconfig" +endif if ARCH_BOARD_NUTINY_NUC120 source "boards/arm/nuc1xx/nutiny-nuc120/Kconfig" endif @@ -3812,6 +3931,9 @@ endif if ARCH_BOARD_STM32H747I_DISCO source "boards/arm/stm32h7/stm32h747i-disco/Kconfig" endif +if ARCH_BOARD_WEACT_STM32H743 +source "boards/arm/stm32h7/weact-stm32h743/Kconfig" +endif if ARCH_BOARD_NUCLEO_H743ZI source "boards/arm/stm32h7/nucleo-h743zi/Kconfig" endif @@ -3827,6 +3949,9 @@ endif if ARCH_BOARD_LINUM_STM32H753BI source "boards/arm/stm32h7/linum-stm32h753bi/Kconfig" endif +if ARCH_BOARD_OPENH743I +source "boards/arm/stm32h7/openh743i/Kconfig" +endif if ARCH_BOARD_B_L475E_IOT01A source "boards/arm/stm32l4/b-l475e-iot01a/Kconfig" endif @@ -4070,6 +4195,9 @@ endif if ARCH_BOARD_XMC4700RELAX source "boards/arm/xmc4/xmc4700-relax/Kconfig" endif +if ARCH_BOARD_XMC4800RELAX +source "boards/arm/xmc4/xmc4800-relax/Kconfig" +endif if ARCH_BOARD_VERDIN_MX8MP source "boards/arm/mx8mp/verdin-mx8mp/Kconfig" endif @@ -4173,13 +4301,13 @@ if ARCH_BOARD_BL808_OX64 source "boards/risc-v/bl808/ox64/Kconfig" endif if ARCH_BOARD_ESP32C3_DEVKIT -source "boards/risc-v/esp32c3/esp32c3-devkit/Kconfig" +source "boards/risc-v/esp32c3-legacy/esp32c3-devkit/Kconfig" endif if ARCH_BOARD_ESP32C3_DEVKIT_RUST1 -source "boards/risc-v/esp32c3/esp32c3-devkit-rust-1/Kconfig" +source "boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/Kconfig" endif if ARCH_BOARD_ESP32C3_GENERIC -source "boards/risc-v/espressif/esp32c3-generic/Kconfig" +source "boards/risc-v/esp32c3/esp32c3-generic/Kconfig" endif if ARCH_BOARD_ESP32S2_KALUGA_1 source "boards/xtensa/esp32s2/esp32s2-kaluga-1/Kconfig" @@ -4205,14 +4333,14 @@ endif if ARCH_BOARD_ESP32S3_BOX source "boards/xtensa/esp32s3/esp32s3-box/Kconfig" endif -if ARCH_BOARD_ESP32C6_DEVKIT -source "boards/risc-v/esp32c6/esp32c6-devkit/Kconfig" -endif -if ARCH_BOARD_ESP32C6_GENERIC -source "boards/risc-v/espressif/esp32c6-generic/Kconfig" -endif -if ARCH_BOARD_ESP32H2_GENERIC -source "boards/risc-v/espressif/esp32h2-generic/Kconfig" +#if ARCH_BOARD_ESP32C6_DEVKITC +#source "boards/risc-v/esp32c6/esp32c6-devkitc/Kconfig" +#endif +#if ARCH_BOARD_ESP32C6_DEVKITM +#source "boards/risc-v/esp32c6/esp32c6-devkitm/Kconfig" +#endif +if ARCH_BOARD_ESP32H2_DEVKIT +source "boards/risc-v/esp32h2/esp32h2-devkit/Kconfig" endif if ARCH_BOARD_SIM source "boards/sim/sim/sim/Kconfig" @@ -4316,6 +4444,9 @@ endif if ARCH_BOARD_TLSR8278ADK80D source "boards/arm/tlsr82/tlsr8278adk80d/Kconfig" endif +if ARCH_BOARD_HPM6360EVK +source "boards/risc-v/hpm6000/hpm6360evk/Kconfig" +endif if ARCH_BOARD_HPM6750EVK2 source "boards/risc-v/hpm6750/hpm6750evk2/Kconfig" endif @@ -4342,10 +4473,16 @@ if ARCH_CHIP_ESP32S3 source "boards/xtensa/esp32s3/common/Kconfig" endif if ARCH_CHIP_ESP32C3 +source "boards/risc-v/esp32c3-legacy/common/Kconfig" +endif +if ARCH_CHIP_ESP32C3_GENERIC source "boards/risc-v/esp32c3/common/Kconfig" endif -if ARCH_CHIP_ESPRESSIF -source "boards/risc-v/espressif/common/Kconfig" +if ARCH_CHIP_ESP32C6 +source "boards/risc-v/esp32c6/common/Kconfig" +endif +if ARCH_CHIP_ESP32H2 +source "boards/risc-v/esp32h2/common/Kconfig" endif if ARCH_CHIP_SAMV7 source "boards/arm/samv7/common/Kconfig" @@ -4602,6 +4739,13 @@ config BOARDCTL_TESTSET Enables support for the BOARDIOC_SPINLOCK boardctl() command. Architecture specific logic must provide up_testset() interface. +config BOARDCTL_IRQ_AFFINITY + bool "Set an IRQ affinity to CPUs by software" + default n + depends on SMP + ---help--- + Enables support for Set an IRQ affinity to CPUs by software. + config BOARDCTL_IOCTL bool "Board-specific boardctl() commands" default n @@ -4617,6 +4761,12 @@ config BOARD_USBDEV_SERIALSTR ---help--- Use board unique serial number to iSerialNumber in the device descriptor. +config BOARD_USBDEV_PIDVID + bool "Board-specific usbdev pid/vid" + default n + ---help--- + Use board unique pid/vid. + config BOARD_MEMORY_RANGE string "Board memory range" default "" diff --git a/boards/arm/a1x/pcduino-a10/scripts/sdram.ld b/boards/arm/a1x/pcduino-a10/scripts/sdram.ld index 08df7d57726a7..ee083bcc4dcbd 100644 --- a/boards/arm/a1x/pcduino-a10/scripts/sdram.ld +++ b/boards/arm/a1x/pcduino-a10/scripts/sdram.ld @@ -83,6 +83,15 @@ SECTIONS _edata = ABSOLUTE(.); } > sdram + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > sdram + .bss : { _sbss = ABSOLUTE(.); @@ -93,15 +102,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > sdram - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > sdram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/am335x/beaglebone-black/scripts/sdram.ld b/boards/arm/am335x/beaglebone-black/scripts/sdram.ld index eaa1d306bf82b..9ab6b5af5e719 100644 --- a/boards/arm/am335x/beaglebone-black/scripts/sdram.ld +++ b/boards/arm/am335x/beaglebone-black/scripts/sdram.ld @@ -88,6 +88,15 @@ SECTIONS _edata = ABSOLUTE(.); } > ddr + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > ddr + .bss : { _sbss = ABSOLUTE(.); @@ -98,15 +107,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > ddr - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > ddr - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/at32/at32f437-mini/include/nsh_romfsimg.h b/boards/arm/at32/at32f437-mini/include/nsh_romfsimg.h deleted file mode 100644 index db6d674d88da0..0000000000000 --- a/boards/arm/at32/at32f437-mini/include/nsh_romfsimg.h +++ /dev/null @@ -1,111 +0,0 @@ -/**************************************************************************** - * boards/arm/at32/at32f437-mini/include/nsh_romfsimg.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -unsigned char romfs_img[] = -{ - 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x03, 0x70, - 0xc4, 0x28, 0xb0, 0x57, 0x72, 0x6f, 0x6d, 0x66, 0x73, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, - 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, - 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, - 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x02, 0x29, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x68, 0x2d, 0x93, 0xe3, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa2, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, - 0xd1, 0xd1, 0xfc, 0x90, 0x2e, 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x02, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xfd, 0xe0, - 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; - -unsigned int romfs_img_len = 1024; diff --git a/boards/arm/at32/at32f437-mini/src/Makefile b/boards/arm/at32/at32f437-mini/src/Makefile index f0d5bc351e0df..c714d8ed9ac7a 100644 --- a/boards/arm/at32/at32f437-mini/src/Makefile +++ b/boards/arm/at32/at32f437-mini/src/Makefile @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/at32/at32f437-mini/src/Make.defs +# boards/arm/at32/at32f437-mini/src/Makefile # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with @@ -80,4 +80,8 @@ ifeq ($(CONFIG_MTD_AT24XX),y) CSRCS += at32_at24.c endif -include $(TOPDIR)/boards/Board.mk \ No newline at end of file +ifeq ($(CONFIG_ETC_ROMFS),y) + CSRCS += etc_romfs.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/at32/at32f437-mini/src/etc_romfs.c b/boards/arm/at32/at32f437-mini/src/etc_romfs.c new file mode 100644 index 0000000000000..d1015996a8d1c --- /dev/null +++ b/boards/arm/at32/at32f437-mini/src/etc_romfs.c @@ -0,0 +1,119 @@ +/**************************************************************************** + * boards/arm/at32/at32f437-mini/src/etc_romfs.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +unsigned char romfs_img[] = +{ + 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x03, 0x70, + 0xc4, 0x28, 0xb0, 0x57, 0x72, 0x6f, 0x6d, 0x66, 0x73, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, + 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, + 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x02, 0x29, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x68, 0x2d, 0x93, 0xe3, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xa2, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0xaa, 0xb5, 0x65, 0x83, + 0x72, 0x63, 0x2e, 0x73, 0x79, 0x73, 0x69, 0x6e, 0x69, 0x74, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x23, 0x69, 0x66, 0x75, 0x70, 0x20, 0x63, 0x61, + 0x6e, 0x30, 0x0a, 0x0a, 0x69, 0x66, 0x20, 0x5b, 0x20, 0x2d, 0x62, 0x20, + 0x22, 0x2f, 0x64, 0x65, 0x76, 0x2f, 0x6d, 0x74, 0x64, 0x62, 0x6c, 0x6f, + 0x63, 0x6b, 0x30, 0x22, 0x20, 0x5d, 0x3b, 0x20, 0x74, 0x68, 0x65, 0x6e, + 0x0a, 0x6d, 0x6f, 0x75, 0x6e, 0x74, 0x20, 0x2d, 0x74, 0x20, 0x76, 0x66, + 0x61, 0x74, 0x20, 0x2f, 0x64, 0x65, 0x76, 0x2f, 0x6d, 0x74, 0x64, 0x62, + 0x6c, 0x6f, 0x63, 0x6b, 0x30, 0x20, 0x2f, 0x66, 0x6c, 0x61, 0x73, 0x68, + 0x0a, 0x66, 0x69, 0x0a, 0x0a, 0x69, 0x66, 0x20, 0x5b, 0x20, 0x2d, 0x62, + 0x20, 0x22, 0x2f, 0x64, 0x65, 0x76, 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0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xfe, 0x20, + 0x2e, 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xe0, 0x00, 0x00, 0x00, 0x60, + 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xfd, 0xc0, 0x2e, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17, + 0x8d, 0x9c, 0xac, 0xe7, 0x72, 0x63, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6d, 0x6f, 0x75, 0x6e, + 0x74, 0x20, 0x2d, 0x74, 0x20, 0x70, 0x72, 0x6f, 0x63, 0x66, 0x73, 0x20, + 0x2f, 0x70, 0x72, 0x6f, 0x63, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x02, 0x40, + 0x00, 0x00, 0x00, 0x00, 0xb6, 0x18, 0x23, 0xeb, 0x73, 0x79, 0x73, 0x63, + 0x6f, 0x6e, 0x66, 0x69, 0x67, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x03, 0x39, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x10, + 0x00, 0x00, 0x02, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xfa, 0xd0, + 0x2e, 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x40, + 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xfd, 0xc0, 0x2e, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, + 0xd1, 0xd1, 0xfc, 0x90, 0x2e, 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x02, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xfd, 0xe0, + 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +unsigned int romfs_img_len = 1024; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/boards/arm/at32/at32f437-mini/tool/mkromfs.sh b/boards/arm/at32/at32f437-mini/tool/mkromfs.sh index 5d97fc8d3083f..d831066fca4a4 100644 --- a/boards/arm/at32/at32f437-mini/tool/mkromfs.sh +++ b/boards/arm/at32/at32f437-mini/tool/mkromfs.sh @@ -3,9 +3,9 @@ genromfs -f romfs.img -d ../romfs -v -V "romfs" -xxd -i romfs.img nsh_romfsimg.h +xxd -i romfs.img etc_romfs.c -cp nsh_romfsimg.h ../include +cp etc_romfs.c ../src -rm romfs.img nsh_romfsimg.h +rm romfs.img etc_romfs.c diff --git a/boards/arm/cxd56xx/common/src/cxd56_alt1250.c b/boards/arm/cxd56xx/common/src/cxd56_alt1250.c index c27792236980f..7daa845684814 100644 --- a/boards/arm/cxd56xx/common/src/cxd56_alt1250.c +++ b/boards/arm/cxd56xx/common/src/cxd56_alt1250.c @@ -377,7 +377,8 @@ static void alt1250_reset(void) { /* Reset Altair modem device */ - board_alt1250_reset(); + alt1250_poweroff(); + alt1250_poweron(false); } /**************************************************************************** @@ -501,4 +502,44 @@ int board_alt1250_initialize(const char *devpath) return OK; } +/**************************************************************************** + * Name: board_alt1250_reset + * + * Description: + * Reset the Altair modem device on the board. + * + ****************************************************************************/ + +void board_alt1250_reset(void) +{ + /* power off Altair modem device */ + + board_alt1250_poweroff(); + + /* Hi-Z SHUTDOWN and PowerBTN signals before power-on */ + + cxd56_gpio_config(ALT1250_SHUTDOWN, false); + + /* power on alt1250 modem device and wait until the power is distributed */ + + board_alt1250_poweron(); + up_mdelay(POWER_ON_WAIT_TIME); + + /* Drive SHUTDOWN signal low */ + + cxd56_gpio_write(ALT1250_SHUTDOWN, 0); + + /* Keep the SHUTDOWN signal low for reset period */ + + up_mdelay(ACTIVE_SHUTDOWN_TIME); + + /* Undrive SHUTDOWN signal to rise up to high by pull-up */ + + cxd56_gpio_write_hiz(ALT1250_SHUTDOWN); + + /* Wait VDDIO on Alt1250 stable */ + + up_mdelay(TIME_TO_STABLE_VDDIO); +} + #endif diff --git a/boards/arm/cxd56xx/common/src/cxd56_crashdump.c b/boards/arm/cxd56xx/common/src/cxd56_crashdump.c index 4cb81a88255c8..cf33ffb6e44dd 100644 --- a/boards/arm/cxd56xx/common/src/cxd56_crashdump.c +++ b/boards/arm/cxd56xx/common/src/cxd56_crashdump.c @@ -186,12 +186,9 @@ void board_crashdump(uintptr_t sp, struct tcb_s *tcb, #if CONFIG_ARCH_INTERRUPTSTACK > 3 /* Get the limits on the interrupt stack memory */ -#ifdef CONFIG_SMP - pdump->info.stacks.interrupt.top = (uint32_t)arm_intstack_top(); -#else - pdump->info.stacks.interrupt.top = (uint32_t)g_intstacktop; -#endif - pdump->info.stacks.interrupt.size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); + pdump->info.stacks.interrupt.top = + up_get_intstackbase(up_cpu_index()) + INTSTACK_SIZE; + pdump->info.stacks.interrupt.size = INTSTACK_SIZE; /* If In interrupt Context save the interrupt stack data centered * about the interrupt stack pointer diff --git a/boards/arm/cxd56xx/drivers/sensors/cxd5610_gnss.c b/boards/arm/cxd56xx/drivers/sensors/cxd5610_gnss.c index 8be65863e2e22..d75c3fd770948 100644 --- a/boards/arm/cxd56xx/drivers/sensors/cxd5610_gnss.c +++ b/boards/arm/cxd56xx/drivers/sensors/cxd5610_gnss.c @@ -229,6 +229,7 @@ begin_packed_struct struct cmd_notify_pos_s int32_t lat32; int32_t lon32; int32_t alt32; + int16_t geo16; } end_packed_struct; begin_packed_struct struct cmd_notify_vel_s @@ -494,6 +495,7 @@ static int cxd5610_gnss_notify_pos(struct cxd5610_gnss_dev_s *priv, int len) int32_t lat32; int32_t lon32; int32_t alt32; + int16_t geo16 = 0; /* If the packet is invalid, do not update received data */ @@ -511,10 +513,15 @@ static int cxd5610_gnss_notify_pos(struct cxd5610_gnss_dev_s *priv, int len) cxd5610_store32(&lat32, ¶m->lat32); cxd5610_store32(&lon32, ¶m->lon32); cxd5610_store32(&alt32, ¶m->alt32); + if (GET_PACKET_VERSION(param->ver8) > 0) + { + cxd5610_store16(&geo16, ¶m->geo16); + } + receiver->latitude = (double)lat32 / 10000000.0; receiver->longitude = (double)lon32 / 10000000.0; receiver->altitude = (double)alt32 / 100.0; - receiver->geoid = 0.0; + receiver->geoid = (double)geo16 / 100.0; receiver->svtype = (param->mode >> 4); receiver->fix_indicator = (param->mode & 0xf); @@ -523,10 +530,12 @@ static int cxd5610_gnss_notify_pos(struct cxd5610_gnss_dev_s *priv, int len) receiver->pos_dataexist = 1; } - sninfo("lat=%.7lf[deg] lon=%.7lf[deg] alt=%.2lf[m] svtype=%d fix=%d\n", + sninfo("lat=%.7lf[deg] lon=%.7lf[deg] alt=%.2lf[m] " + "geo=%.2lf[m] svtype=%d fix=%d\n", receiver->latitude, receiver->longitude, receiver->altitude, + receiver->geoid, receiver->svtype, receiver->fix_indicator); @@ -1537,7 +1546,7 @@ static int cxd5610_gnss_initialize(struct cxd5610_gnss_dev_s *priv) /* Create thread for receiving from CXD5610 device */ - snprintf(arg1, 16, "0x%" PRIxPTR, (uintptr_t)priv); + snprintf(arg1, 16, "%p", priv); argv[0] = arg1; argv[1] = NULL; diff --git a/boards/arm/cxd56xx/spresense/Kconfig b/boards/arm/cxd56xx/spresense/Kconfig index 1b6fded184891..e2b6d51c436a2 100644 --- a/boards/arm/cxd56xx/spresense/Kconfig +++ b/boards/arm/cxd56xx/spresense/Kconfig @@ -838,6 +838,21 @@ config CXD56_EMMC_POWER_PIN_UART2_CTS endchoice +choice + prompt "BLE1507 Add-on board Reset Pin selection" + default CXD56_BLE1507_RESET_PIN_NONE + +config CXD56_BLE1507_RESET_PIN_NONE + bool "None" + +config CXD56_BLE1507_RESET_PIN_I2S0_DATA_IN + bool "Use PIN I2S0_DATA_IN" + +config CXD56_BLE1507_RESET_PIN_EMMC_DATA2 + bool "Use PIN EMMC_DATA2" + +endchoice + config CXD56_GNSS_ADDON bool "CXD5610 GNSS Add-on board" default n diff --git a/boards/arm/cxd56xx/spresense/include/board.h b/boards/arm/cxd56xx/spresense/include/board.h index e518e1f8c73a9..3806c433f181b 100644 --- a/boards/arm/cxd56xx/spresense/include/board.h +++ b/boards/arm/cxd56xx/spresense/include/board.h @@ -201,7 +201,13 @@ enum board_power_device POWER_AUDIO_MUTE = PMIC_GPO(6), POWER_IMAGE_SENSOR = PMIC_GPO(4), +#if defined(CONFIG_CXD56_BLE1507_RESET_PIN_I2S0_DATA_IN) + POWER_BTBLE = CHIP_GPIO(PIN_I2S0_DATA_IN), +#elif defined(CONFIG_CXD56_BLE1507_RESET_PIN_EMMC_DATA2) + POWER_BTBLE = CHIP_GPIO(PIN_EMMC_DATA2), +#else POWER_BTBLE = PMIC_NONE, +#endif POWER_SENSOR = PMIC_NONE, #if defined(CONFIG_CXD56_EMMC_POWER_PIN_I2S0_BCK) POWER_EMMC = CHIP_GPIO(PIN_I2S0_BCK), diff --git a/boards/arm/cxd56xx/spresense/include/cxd56_bmi160.h b/boards/arm/cxd56xx/spresense/include/cxd56_bmi160.h index 90b56541844f5..1367d8dc501f6 100644 --- a/boards/arm/cxd56xx/spresense/include/cxd56_bmi160.h +++ b/boards/arm/cxd56xx/spresense/include/cxd56_bmi160.h @@ -77,9 +77,9 @@ int board_bmi160_initialize(int bus); * ****************************************************************************/ -#ifdef CONFIG_SENSORS_BMI160_I2C +#ifdef CONFIG_SENSORS_BMI160_SCU_I2C int bmi160_init(struct i2c_master_s *dev, int port); -#else /* CONFIG_SENSORS_BMI160_SPI */ +#else /* CONFIG_SENSORS_BMI160_SCU_SPI */ int bmi160_init(struct spi_dev_s *dev); #endif @@ -101,10 +101,10 @@ int bmi160_init(struct spi_dev_s *dev); * ****************************************************************************/ -#ifdef CONFIG_SENSORS_BMI160_I2C +#ifdef CONFIG_SENSORS_BMI160_SCU_I2C int bmi160gyro_register(const char *devpath, int minor, struct i2c_master_s *dev, int port); -#else /* CONFIG_SENSORS_BMI160_SPI */ +#else /* CONFIG_SENSORS_BMI160_SCU_SPI */ int bmi160gyro_register(const char *devpath, int minor, struct spi_dev_s *dev); #endif @@ -127,10 +127,10 @@ int bmi160gyro_register(const char *devpath, int minor, * ****************************************************************************/ -#ifdef CONFIG_SENSORS_BMI160_I2C +#ifdef CONFIG_SENSORS_BMI160_SCU_I2C int bmi160accel_register(const char *devpath, int minor, struct i2c_master_s *dev, int port); -#else /* CONFIG_SENSORS_BMI160_SPI */ +#else /* CONFIG_SENSORS_BMI160_SCU_SPI */ int bmi160accel_register(const char *devpath, int minor, struct spi_dev_s *dev); #endif diff --git a/boards/arm/cxd56xx/spresense/scripts/ramconfig-new.ld b/boards/arm/cxd56xx/spresense/scripts/ramconfig-new.ld index 521fd8c58bbc9..ba2de421eafce 100644 --- a/boards/arm/cxd56xx/spresense/scripts/ramconfig-new.ld +++ b/boards/arm/cxd56xx/spresense/scripts/ramconfig-new.ld @@ -21,6 +21,7 @@ MEMORY { ram (rwx) : ORIGIN = 0x0d000000, LENGTH = 1536K + gnssram (rwx) : ORIGIN = 0x09000000, LENGTH = 640K } OUTPUT_ARCH(arm) @@ -29,6 +30,48 @@ EXTERN(_vectors) /* Force the vectors to be included in the output */ EXTERN(__stack) /* Force the __stack to be included in the output */ SECTIONS { + /* GNSS memory */ + + .gnssram.text : { + _sgnsstext = ABSOLUTE(.); + + /* Possible to locate text of any object file. + * *libxxx.a:*.o(.text .text.*) + * *libxxx.a:*.o(.rodata .rodata.*) + */ + + } > gnssram + + .gnssram.data . : ALIGN(4) { + /* Possible to locate data of any object file. + * *libxxx.a:*.o(.data .data.*) + */ + + } > gnssram + + .gnssram.bss . (NOLOAD) : { + . = ALIGN(4); + _gnssramsbss = ABSOLUTE(.); + + /* Possible to locate bss of any object file. + * *libxxx.a:*.o(.bss .bss.*) + * *libxxx.a:*.o(COMMON) + */ + + } > gnssram + + . = ALIGN(4); + _gnssramebss = ABSOLUTE(.); + + /* Whatever is left from the GNSS memory is used as a special heap. */ + + _sgnssheap = ABSOLUTE(.); + _egnssheap = ORIGIN(gnssram) + LENGTH(gnssram); + + ASSERT(_sgnssheap < _egnssheap, "Error: Out of memory") + + /* Application memory */ + .text : { _stext = ABSOLUTE(.); *(.vectors) diff --git a/boards/arm/cxd56xx/spresense/scripts/ramconfig.ld b/boards/arm/cxd56xx/spresense/scripts/ramconfig.ld index b2842e960c32b..0a0235886bc3e 100644 --- a/boards/arm/cxd56xx/spresense/scripts/ramconfig.ld +++ b/boards/arm/cxd56xx/spresense/scripts/ramconfig.ld @@ -21,6 +21,7 @@ MEMORY { ram (rwx) : ORIGIN = 0x0d000000, LENGTH = 1536K + gnssram (rwx) : ORIGIN = 0x09000000, LENGTH = 640K } OUTPUT_ARCH(arm) @@ -29,6 +30,48 @@ EXTERN(_vectors) /* Force the vectors to be included in the output */ EXTERN(__stack) /* Force the __stack to be included in the output */ SECTIONS { + /* GNSS memory */ + + .gnssram.text : { + _sgnsstext = ABSOLUTE(.); + + /* Possible to locate text of any object file. + * *libxxx.a:*.o(.text .text.*) + * *libxxx.a:*.o(.rodata .rodata.*) + */ + + } > gnssram + + .gnssram.data . : ALIGN(4) { + /* Possible to locate data of any object file. + * *libxxx.a:*.o(.data .data.*) + */ + + } > gnssram + + .gnssram.bss . (NOLOAD) : { + . = ALIGN(4); + _gnssramsbss = ABSOLUTE(.); + + /* Possible to locate bss of any object file. + * *libxxx.a:*.o(.bss .bss.*) + * *libxxx.a:*.o(COMMON) + */ + + } > gnssram + + . = ALIGN(4); + _gnssramebss = ABSOLUTE(.); + + /* Whatever is left from the GNSS memory is used as a special heap. */ + + _sgnssheap = ABSOLUTE(.); + _egnssheap = ORIGIN(gnssram) + LENGTH(gnssram); + + ASSERT(_sgnssheap < _egnssheap, "Error: Out of memory") + + /* Application memory */ + .text : { _stext = ABSOLUTE(.); *(.vectors) diff --git a/boards/arm/cxd56xx/spresense/src/cxd56_alt1250_power.c b/boards/arm/cxd56xx/spresense/src/cxd56_alt1250_power.c index fc3a612192554..82f48d4859474 100644 --- a/boards/arm/cxd56xx/spresense/src/cxd56_alt1250_power.c +++ b/boards/arm/cxd56xx/spresense/src/cxd56_alt1250_power.c @@ -38,19 +38,6 @@ #include "cxd56_gpio.h" #include "cxd56_pinconfig.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define RESET_INTERVAL_TIMEOUT MSEC2TICK(1) - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct wdog_s g_reset_wd; -static sem_t g_wd_wait; - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -113,52 +100,5 @@ int board_alt1250_powerkeep(bool enable) return board_set_reset_gpo(POWER_LTE); } } - -/**************************************************************************** - * Name: board_alt1250_timeout - * - * Description: - * Watchdog timer for timeout of reset interval. - * - ****************************************************************************/ - -static void board_alt1250_timeout(wdparm_t arg) -{ - sem_t *wd_wait = (sem_t *)arg; - - nxsem_post(wd_wait); -} - -/**************************************************************************** - * Name: board_alt1250_reset - * - * Description: - * Reset the Altair modem device on the board. - * - ****************************************************************************/ - -void board_alt1250_reset(void) -{ - memset(&g_reset_wd, 0, sizeof(struct wdog_s)); - nxsem_init(&g_wd_wait, 0, 0); - - /* Reset Altair modem device */ - - board_alt1250_poweroff(); - - /* ALT1250_SHUTDOWN should be low in the range 101usec to 100msec */ - - wd_start(&g_reset_wd, RESET_INTERVAL_TIMEOUT, - board_alt1250_timeout, (wdparm_t)&g_wd_wait); - - /* Wait for the watchdog timer to expire */ - - nxsem_wait_uninterruptible(&g_wd_wait); - - board_alt1250_poweron(); - - nxsem_destroy(&g_wd_wait); -} - #endif diff --git a/boards/arm/dm320/ntosd-dm320/configs/nsh/defconfig b/boards/arm/dm320/ntosd-dm320/configs/nsh/defconfig index ef776e92abdc7..248be9603094f 100644 --- a/boards/arm/dm320/ntosd-dm320/configs/nsh/defconfig +++ b/boards/arm/dm320/ntosd-dm320/configs/nsh/defconfig @@ -40,7 +40,6 @@ CONFIG_NET_TCP=y CONFIG_NET_UDP=y CONFIG_NET_UDP_CHECKSUMS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PTHREAD_STACK_DEFAULT=4096 CONFIG_RAM_SIZE=33554432 CONFIG_RAM_START=0x01100000 diff --git a/boards/arm/fvp-v8r-aarch32/fvp-armv8r-aarch32/CMakeLists.txt b/boards/arm/fvp-v8r-aarch32/fvp-armv8r-aarch32/CMakeLists.txt new file mode 100644 index 0000000000000..5a331f2f47356 --- /dev/null +++ b/boards/arm/fvp-v8r-aarch32/fvp-armv8r-aarch32/CMakeLists.txt @@ -0,0 +1,21 @@ +# ############################################################################## +# boards/arm/fvp-v8r-aarch32/fvp-armv8r-aarch32/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/fvp-v8r-aarch32/fvp-armv8r-aarch32/configs/nsh/defconfig b/boards/arm/fvp-v8r-aarch32/fvp-armv8r-aarch32/configs/nsh/defconfig index 639b071937734..bae6f387b0cff 100644 --- a/boards/arm/fvp-v8r-aarch32/fvp-armv8r-aarch32/configs/nsh/defconfig +++ b/boards/arm/fvp-v8r-aarch32/fvp-armv8r-aarch32/configs/nsh/defconfig @@ -35,7 +35,6 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 CONFIG_RAMLOG=y diff --git a/boards/arm/fvp-v8r-aarch32/fvp-armv8r-aarch32/scripts/dramboot.ld b/boards/arm/fvp-v8r-aarch32/fvp-armv8r-aarch32/scripts/dramboot.ld index 43d5a50499329..7ffc48c195c2a 100644 --- a/boards/arm/fvp-v8r-aarch32/fvp-armv8r-aarch32/scripts/dramboot.ld +++ b/boards/arm/fvp-v8r-aarch32/fvp-armv8r-aarch32/scripts/dramboot.ld @@ -84,6 +84,15 @@ SECTIONS _edata = ABSOLUTE(.); } > RAM AT > FLASH + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > RAM + .bss : { _sbss = ABSOLUTE(.); @@ -94,15 +103,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > RAM - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > RAM - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } @@ -112,4 +112,4 @@ SECTIONS .stab.index 0 : { *(.stab.index) } .stab.indexstr 0 : { *(.stab.indexstr) } .comment 0 : { *(.comment) } -} \ No newline at end of file +} diff --git a/boards/arm/fvp-v8r-aarch32/fvp-armv8r-aarch32/src/CMakeLists.txt b/boards/arm/fvp-v8r-aarch32/fvp-armv8r-aarch32/src/CMakeLists.txt new file mode 100644 index 0000000000000..8867f7f2c0a9b --- /dev/null +++ b/boards/arm/fvp-v8r-aarch32/fvp-armv8r-aarch32/src/CMakeLists.txt @@ -0,0 +1,29 @@ +# ############################################################################## +# boards/arm/fvp-v8r-aarch32/fvp-armv8r-aarch32/src/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS fvp_boardinit.c fvp_bringup.c) + +if(CONFIG_BOARDCTL) + list(APPEND SRCS fvp_appinit.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/dramboot.ld") diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/Kconfig b/boards/arm/gd32f4/gd32f450zk-aiotbox/Kconfig new file mode 100644 index 0000000000000..673c14a6df3b6 --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/Kconfig @@ -0,0 +1,87 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_GD32F450ZK_AIOTBOX + +choice + prompt "Select Console wiring." + default GD32F450ZK_AIOTBOX_CONSOLE_BOARD + ---help--- + Select where you will connect the console. + + Virtual COM Port: + + Advantage: Use the ST-Link as a console. No Extra wiring + needed. + + Disadvantage: Not the best choice for initial bring up. + + BOARD USART Connector: + + Advantage: You have a shield so it is easy. + + Disadvantage: You loose the use of the + other functions on PA9, PA10 + + GD32F450ZK_AIOTBOX + USART0 GPIO + -- ----- --------- ---- + RX USART0_RX PB7 + TX USART0_TX PB6 + -- ----- --------- --- + +config GD32F450ZK_AIOTBOX_CONSOLE_BOARD + bool "Aiotbox Com Connector" + select GD32_USART0 + select USART0_SERIALDRIVER + +config GD32F450ZK_AIOTBOX_CONSOLE_VIRTUAL + bool "Aiotbox Virtual ComPort" + select GD32_USART3 + select USART3_SERIALDRIVER + +config GD32F450ZK_AIOTBOX_CONSOLE_NONE + bool "No Serial Console" + +endchoice # "Select Console wiring" + + +choice + prompt "GD32F4 MCU Crystal Selected" + default GD32F4_BOARD_USE_HXTAL_AIOTBOX + +config GD32F4_BOARD_USE_HXTAL_AIOTBOX + bool "Aiotbox Use Hxtal as clock source" + # select GD32F4_BOARD_HXTAL_VALUE + +config GD32F4_BOARD_USE_IRC16_AIOTBOX + bool "Aiotbox Use IRC16M as clock source" + +endchoice # CPU Frequency + +config GD32F4_BOARD_HXTAL_VALUE + int "GD32F450Z Aiotbox Board Hxtal Value" + default 25000000 + depends on GD32F4_BOARD_USE_HXTAL_AIOTBOX + ---help--- + GD32F450Z Aiotbox Board Hxtal Value, default is 25MHz. + +choice + prompt "GD32F4 MCU System Frequency" + default GD32F4_200MHZ_AIOTBOX + +config GD32F4_200MHZ_AIOTBOX + bool "200 MHz" + +config GD32F4_168MHZ_AIOTBOX + bool "168 MHz" + +config GD32F4_120MHZ_AIOTBOX + bool "120 MHz" + +endchoice # CPU Frequency + + +endif # ARCH_BOARD_GD32F450ZK_AIOTBOX diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/configs/aiotboxnsh/defconfig b/boards/arm/gd32f4/gd32f450zk-aiotbox/configs/aiotboxnsh/defconfig new file mode 100644 index 0000000000000..c6bca4e3298c3 --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/configs/aiotboxnsh/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="gd32f450zk-aiotbox" +CONFIG_ARCH_BOARD_GD32F450ZK_AIOTBOX=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="gd32f4" +CONFIG_ARCH_CHIP_GD32F450ZK=y +CONFIG_ARCH_CHIP_GD32F4=y +CONFIG_ARCH_INTERRUPTSTACK=256 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_CUSTOMOPT=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_IRQ=y +CONFIG_DEBUG_LEDS=y +CONFIG_DEBUG_OPTLEVEL="-O0" +CONFIG_DEBUG_SCHED=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_GD32F4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_GD32F4_FLASH_CONFIG_K=y +CONFIG_GD32F4_I2C0=y +CONFIG_GD32F4_I2C1=y +CONFIG_GD32F4_USART2=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2C_POLLED=y +CONFIG_I2C_RESET=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART0_SERIAL_CONSOLE=y diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/include/board.h b/boards/arm/gd32f4/gd32f450zk-aiotbox/include/board.h new file mode 100644 index 0000000000000..c5f3cbacdf62e --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/include/board.h @@ -0,0 +1,389 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-aiotbox/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_GD32F450ZK_AIOTBOX_INCLUDE_BOARD_H +#define __BOARDS_ARM_GD32F450ZK_AIOTBOX_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +#define GD32_BOARD_SYSCLK_PLL_HXTAL + +/* Do not include GD32F4 header files here */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The GD32F450ZK-EVAL board features a single 25MHz crystal. + * + * This is the default configuration: + * System clock source : PLL (HXTAL) + * SYSCLK(Hz) : 200000000 Determined by PLL config + * HCLK(Hz) : 200000000 (GD32_SYSCLK_FREQUENCY) + * AHB Prescaler : 1 (GD32_RCU_CFG0_AHB_PSC) + * APB2 Prescaler : 2 (GD32_RCU_CFG0_APB2_PSC) + * APB1 Prescaler : 4 (GD32_RCU_CFG0_APB1_PSC) + * HXTAL value(Hz) : 25000000 (GD32_BOARD_XTAL) + * PLLM : 25 (GD32_PLL_PLLM) + * PLLN : 400 (RCU_PLL_PLLN) + * PLLP : 2 (GD32_PLL_PLLP) + * PLLQ : 7 (GD32_PLL_PLLQ) + */ + +/* IRC16M - 16 MHz RC factory-trimmed + * IRC32K - 32 KHz RC + * HXTAL - On-board crystal frequency is 25MHz + * LXTAL - 32.768 kHz + */ + +#ifndef CONFIG_GD32F4_BOARD_HXTAL_VALUE +# define GD32_BOARD_HXTAL 25000000ul +#else +# define GD32_BOARD_HXTAL CONFIG_GD32F4_BOARD_HXTAL_VALUE +#endif + +#define GD32_IRC16M_VALUE 16000000ul +#define GD32_IRC32K_VALUE 32000u +#define GD32_HXTAL_VALUE GD32_BOARD_HXTAL +#define GD32_LXTAL_VALUE 32768u + +#if defined(CONFIG_GD32F4_200MHZ_AIOTBOX) + +/* Main PLL Configuration. + * + * PLL source is HXTAL + * PLL_VCO = (GD32_HXTAL_VALUE / PLLM) * PLLN + * = (25,000,000 / 25) * 400 + * = 400,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 400,000,000 / 2 = 168,000,000 + * USB, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define GD32_PLL_PLLPSC RCU_PLL_PLLPSC(25) +#define GD32_PLL_PLLN RCU_PLL_PLLN(400) +#define GD32_PLL_PLLP RCU_PLL_PLLP(2) +#define GD32_PLL_PLLQ RCU_PLL_PLLQ(7) + +#define GD32_SYSCLK_FREQUENCY 200000000ul + +#elif defined(CONFIG_GD32F4_168MHZ_AIOTBOX) + +/* Main PLL Configuration. + * + * PLL source is HXTAL + * PLL_VCO = (GD32_HXTAL_VALUE / PLLM) * PLLN + * = (25,000,000 / 25) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define GD32_PLL_PLLPSC RCU_PLL_PLLPSC(25) +#define GD32_PLL_PLLN RCU_PLL_PLLN(336) +#define GD32_PLL_PLLP RCU_PLL_PLLP(2) +#define GD32_PLL_PLLQ RCU_PLL_PLLQ(7) + +#define GD32_SYSCLK_FREQUENCY 168000000ul + +#endif + +/* AHB clock (HCLK) is SYSCLK */ + +#define GD32_RCU_CFG0_AHB_PSC RCU_CFG0_AHBPSC_CKSYS_DIV1 /* HCLK = SYSCLK / 1 */ +#define GD32_HCLK_FREQUENCY GD32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK/2 */ + +#define GD32_RCU_CFG0_APB2_PSC RCU_CFG0_APB2PSC_CKAHB_DIV2 /* PCLK2 = HCLK / 2 */ +#define GD32_PCLK2_FREQUENCY (GD32_HCLK_FREQUENCY/2) + +/* APB1 clock (PCLK1) is HCLK/4 */ + +#define GD32_RCU_CFG0_APB1_PSC RCU_CFG0_APB1PSC_CKAHB_DIV4 /* PCLK1 = HCLK / 4 */ +#define GD32_PCLK1_FREQUENCY (GD32_HCLK_FREQUENCY / 4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define GD32_APB1_TIMER2_CLKIN (2*GD32_PCLK1_FREQUENCY) +#define GD32_APB1_TIMER3_CLKIN (2*GD32_PCLK1_FREQUENCY) +#define GD32_APB1_TIMER4_CLKIN (2*GD32_PCLK1_FREQUENCY) +#define GD32_APB1_TIMER5_CLKIN (2*GD32_PCLK1_FREQUENCY) +#define GD32_APB1_TIMER6_CLKIN (2*GD32_PCLK1_FREQUENCY) +#define GD32_APB1_TIMER7_CLKIN (2*GD32_PCLK1_FREQUENCY) +#define GD32_APB1_TIMER12_CLKIN (2*GD32_PCLK1_FREQUENCY) +#define GD32_APB1_TIMER13_CLKIN (2*GD32_PCLK1_FREQUENCY) +#define GD32_APB1_TIMER14_CLKIN (2*GD32_PCLK1_FREQUENCY) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define GD32_APB2_TIMER1_CLKIN (2*GD32_PCLK2_FREQUENCY) +#define GD32_APB2_TIMER8_CLKIN (2*GD32_PCLK2_FREQUENCY) +#define GD32_APB2_TIMER9_CLKIN (2*GD32_PCLK2_FREQUENCY) +#define GD32_APB2_TIMER10_CLKIN (2*GD32_PCLK2_FREQUENCY) +#define GD32_APB2_TIMER11_CLKIN (2*GD32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIMER1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIMER1_FREQUENCY GD32_HCLK_FREQUENCY +#define BOARD_TIMER2_FREQUENCY (GD32_HCLK_FREQUENCY/2) +#define BOARD_TIMER3_FREQUENCY (GD32_HCLK_FREQUENCY/2) +#define BOARD_TIMER4_FREQUENCY (GD32_HCLK_FREQUENCY/2) +#define BOARD_TIMER5_FREQUENCY (GD32_HCLK_FREQUENCY/2) +#define BOARD_TIMER6_FREQUENCY (GD32_HCLK_FREQUENCY/2) +#define BOARD_TIMER7_FREQUENCY (GD32_HCLK_FREQUENCY/2) +#define BOARD_TIMER8_FREQUENCY GD32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* The GD32F450ZK_EVAL board has board has three LEDs. The LED1, LED2 and + * LED3 are controlled by GPIO. LED1 is connected to PD4, LED2 is connected + * to PD5, LED3 is connected to PG3 + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values */ + +typedef enum +{ + BOARD_LED1 = 0, + BOARD_LED2 = 1, + BOARD_LED3 = 2, + BOARD_LEDS +} led_typedef_enum; + +/* LED bits */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) + +/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in + * include/board.h and src/gd32f4xx_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * + * + * SYMBOL Meaning LED state + * LED1 LED2 LED3 + * ---------------------- -------------------------- ------ ------ --- + */ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated ON OFF OFF */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF OFF ON */ +#define LED_INIRQ 4 /* In an interrupt ON ON OFF */ +#define LED_SIGNAL 5 /* In a signal handler ON OFF ON */ +#define LED_ASSERTION 6 /* An assertion failed OFF ON ON */ +#define LED_PANIC 7 /* The system has crashed FLASH ON ON */ +#define LED_IDLE 8 /* MCU is is sleep mode OFF FLASH OFF */ + +/* Button definitions *******************************************************/ + +/* The GD32F450Z Eval supports three user buttons: Wakeup, Tamper and + * User key, they are connected to GPIO PA0, PC13, PB14. + * A low value will be sensed when the button is depressed. + */ + +typedef enum +{ + BUTTON_WAKEUP = 0, + BUTTON_TAMPER = 1, + BUTTON_USER = 2, + NUM_BUTTONS +} key_typedef_enum; + +#define BUTTON_WAKEUP_BIT (1 << BUTTON_WAKEUP) +#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +#if defined(CONFIG_GD32F450ZK_AIOTBOX_CONSOLE_BOARD) + +/* USART0: + * + * These configurations assume that you are using a standard RS-232 + * shield with the serial interface with RX on PA10 and TX on PA10: + * + * -------- --------------- + * GD32F450ZK-EVAL + * -- ----- --------- ----- + * RX USART0_RX PB7 + * TX USART0_TX PB6 + * -- ----- --------- ----- + */ + +# define GPIO_USART0_RX GPIO_USART0_RX_3 +# define GPIO_USART0_TX GPIO_USART0_TX_3 + +# define GPIO_USART2_RX GPIO_USART2_RX_3 +# define GPIO_USART2_TX GPIO_USART2_TX_2 + +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART0_IFLOWCONTROL) +# define GPIO_USART0_RTS GPIO_USART0_RTS_1 +# endif +#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART0_OFLOWCONTROL) +# define GPIO_USART0_CTS GPIO_USART0_CTS_1 +# endif +#endif + +#if CONFIG_GD32F4_USART0_TXDMA +# define DMA_CHANNEL_USART0_TX DMA_REQ_USART0_TX +#endif +#if CONFIG_GD32F4_USART0_RXDMA +# define DMA_CHANNEL_USART0_RX DMA_REQ_USART0_RX_1 +#endif + +#if defined(CONFIG_GD32F4_USART_RXDMA) || defined(CONFIG_GD32F4_USART_TXDMA) +# define USART_DMA_INTEN (DMA_CHXCTL_SDEIE | DMA_CHXCTL_TAEIE | DMA_CHXCTL_FTFIE) +#endif + +/* USART3: + * Use USART3 and the USB virtual COM port + */ + +#if defined(GD32F450ZK_AIOTBOX_CONSOLE_VIRTUAL) +# define GPIO_USART3_RX GPIO_USART3_RX_3 +# define GPIO_USART3_TX GPIO_USART3_TX_3 +#endif + +/* I2C0 gpios: + * + * PB6 I2C0_SCL + * PB7 I2C0_SDA + * + */ + +#define GPIO_I2C0_SCL GPIO_I2C0_SCL_2 +#define GPIO_I2C0_SDA GPIO_I2C0_SDA_2 + +#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 +#define GPIO_I2C1_SDA GPIO_I2C1_SDA_4 + +/* SPI flash + * + * PG12 SPI5_MISO + * PG14 SPI5_MOSI + * PG13 SPI5_SCK + * + * PG9 SPI5_CS + * + */ + +#define GPIO_SPI5_CSPIN (GPIO_CFG_PORT_G | GPIO_PIN9_OUTPUT) + +#define GPIO_SPI5_MISO_PIN ((GPIO_SPI5_MISO & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) +#define GPIO_SPI5_MOSI_PIN ((GPIO_SPI5_MOSI & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) +#define GPIO_SPI5_SCK_PIN ((GPIO_SPI5_SCK & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) + +#define GPIO_SPI5_IO2_PIN ((GPIO_SPI5_IO2 & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) +#define GPIO_SPI5_IO3_PIN ((GPIO_SPI5_IO3 & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) + +#ifdef CONFIG_GD32F4_SPI0 +# define GPIO_SPI0_CSPIN (GPIO_CFG_PORT_B | GPIO_PIN9_OUTPUT) +# define GPIO_SPI0_MISO_PIN ((GPIO_SPI0_MISO_1 & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) +# define GPIO_SPI0_MOSI_PIN ((GPIO_SPI0_MOSI_1 & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) +# define GPIO_SPI0_SCK_PIN ((GPIO_SPI0_SCK_1 & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) +#endif + +#ifdef CONFIG_GD32F4_SPI0_DMA +# define DMA_CHANNEL_SPI0_TX DMA_REQ_SPI0_TX_1 +# define DMA_CHANNEL_SPI0_RX DMA_REQ_SPI0_RX_1 +#endif + +#ifdef CONFIG_GD32F4_SPI_DMA +# define SPI_DMA_INTEN (DMA_CHXCTL_SDEIE | DMA_CHXCTL_TAEIE | DMA_CHXCTL_FTFIE) +#endif + +/* The GD32 F4 connects to a DP83848 PHY using these pins: + * + * GD32F450Z Eval BOARD DP83848 + * GPIO SIGNAL PIN NAME + * -------- ------------ ------------- + * PB11 RMII_TX_EN TXEN + * PB12 RMII_TXD0 TXD0 + * PB13 RMII_TXD1 TXD1 + * PC4 RMII_RXD0 RXD_0/PHYAD1 + * PC5 RMII_RXD1 RXD_1/PHYAD2 + * PA7 RMII_CRS_DV RX_DV/MII_MODE + * PC1 RMII_MDC MDC + * PA2 RMII_MDIO MDIO + * NRST NRST RESET_N + * PA1 RMII_REF_CLK X1 + * PB15 RMII_INT PWR_DOWN/INT + * + * The PHY address is 1. + */ + +#define GPIO_ENET_RMII_TX_EN GPIO_ENET_RMII_TX_EN_1 +#define GPIO_ENET_RMII_TXD0 GPIO_ENET_RMII_TXD0_1 +#define GPIO_ENET_RMII_TXD1 GPIO_ENET_RMII_TXD1_1 + +#ifdef CONFIG_GD32F4_ENET_PTP + /* Enable pulse-per-second (PPS) output signal */ + +# define GPIO_ENET_PPS_OUT GPIO_ENET_PPS_OUT_1 +#endif + +/* SDIO gpios + * + * PD2 SDIO_CMD + * PC12 SDIO_CLK + * PC8 SDIO_DAT0 + * PC9 SDIO_DAT1 + * PC10 SDIO_DAT2 + * PC11 SDIO_DAT3 + * + */ + +#define GPIO_SDIO_CMD_PIN GPIO_SDIO_CMD_2 +#define GPIO_SDIO_CLK_PIN GPIO_SDIO_CK_2 +#define GPIO_SDIO_DAT0_PIN GPIO_SDIO_D0_2 +#define GPIO_SDIO_DAT1_PIN GPIO_SDIO_D1_3 +#define GPIO_SDIO_DAT2_PIN GPIO_SDIO_D2_3 +#define GPIO_SDIO_DAT3_PIN GPIO_SDIO_D3 + +#ifdef CONFIG_GD32F4_SDIO_DMA +# define SDIO_DMA_INTEN (DMA_CHXCTL_SDEIE | DMA_CHXCTL_TAEIE | DMA_CHXCTL_FTFIE) +#endif + +#endif /* __BOARDS_ARM_GD32F450ZK_EVAL_INCLUDE_BOARD_H */ diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/Make.defs b/boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/Make.defs new file mode 100644 index 0000000000000..c890b87cc55b6 --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +EXEEXT = .elf diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/gnu-elf.ld b/boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/gnu-elf.ld new file mode 100644 index 0000000000000..71448aa6cd954 --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/gnu-elf.ld @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-eval/scripts/gnu-elf.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +SECTIONS +{ + .text 0x00000000 : + { + _stext = . ; + *(.text) + *(.text.*) + *(.gnu.warning) + *(.stub) + *(.glue_7) + *(.glue_7t) + *(.jcr) + + /* C++ support: The .init and .fini sections contain specific logic + * to manage static constructors and destructors. + */ + + *(.gnu.linkonce.t.*) + *(.init) /* Old ABI */ + *(.fini) /* Old ABI */ + _etext = . ; + } + + .rodata : + { + _srodata = . ; + *(.rodata) + *(.rodata1) + *(.rodata.*) + *(.gnu.linkonce.r*) + _erodata = . ; + } + + .data : + { + _sdata = . ; + *(.data) + *(.data1) + *(.data.*) + *(.gnu.linkonce.d*) + . = ALIGN(4); + _edata = . ; + } + + /* C++ support. For each global and static local C++ object, + * GCC creates a small subroutine to construct the object. Pointers + * to these routines (not the routines themselves) are stored as + * simple, linear arrays in the .ctors section of the object file. + * Similarly, pointers to global/static destructor routines are + * stored in .dtors. + */ + + .ctors : + { + _sctors = . ; + *(.ctors) /* Old ABI: Unallocated */ + *(.init_array) /* New ABI: Allocated */ + _edtors = . ; + } + + .dtors : + { + _sdtors = . ; + *(.dtors) /* Old ABI: Unallocated */ + *(.fini_array) /* New ABI: Allocated */ + _edtors = . ; + } + + .bss : + { + _sbss = . ; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.b*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + } + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/kernel-space.ld b/boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/kernel-space.ld new file mode 100644 index 0000000000000..7018a914599b0 --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/kernel-space.ld @@ -0,0 +1,98 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-eval/scripts/kernel-space.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/ld.script b/boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/ld.script new file mode 100644 index 0000000000000..bb0866acc1c74 --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/ld.script @@ -0,0 +1,131 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-eval/scripts/ld.script + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The GD32F450ZKT6 has 3072Kb of FLASH beginning at address 0x0800:0000 and + * 256Kb of SRAM. SRAM is split up into four blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of SRAM beginning at address 0x2002:0000 + * 4) 64Kb of TCMSRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 3072K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/memory.ld b/boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/memory.ld new file mode 100644 index 0000000000000..d540022dbcd9a --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/memory.ld @@ -0,0 +1,85 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-eval/scripts/memory.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The GD32F450ZKT6 has 3072Kb of FLASH beginning at address 0x0800:0000 and + * 256Kb of SRAM. SRAM is split up into four blocks: + * + * 1) 112KB of SRAM beginning at address 0x2000:0000 + * 2) 16KB of SRAM beginning at address 0x2001:c000 + * 3) 64KB of SRAM beginning at address 0x2002:0000 + * 4) 64KB of TCMSRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed. Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x20000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x20000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x20000 2000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------- ---- Beginning of user heap. Can vary with other settings. + * 0x20001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K + usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K +} diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/user-space.ld b/boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/user-space.ld new file mode 100644 index 0000000000000..6a02688b69c61 --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/scripts/user-space.ld @@ -0,0 +1,112 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-eval/scripts/user-space.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +/* Make sure that the critical memory management functions are in user-space. + * the user heap memory manager will reside in user-space but be usable both + * by kernel- and user-space code + */ + +EXTERN(umm_initialize) +EXTERN(umm_addregion) + +EXTERN(malloc) +EXTERN(realloc) +EXTERN(zalloc) +EXTERN(free) + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/src/Makefile b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/Makefile new file mode 100644 index 0000000000000..14f92dd75314c --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/Makefile @@ -0,0 +1,61 @@ +############################################################################ +# boards/arm/gd32f4/gd32f450zk-aiotbox/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = gd32f4xx_boot.c + +# ifeq ($(CONFIG_BOARDCTL),y) +# CSRCS += gd32f4xx_appinit.c +# endif + +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += gd32f4xx_appinit.c gd32f4xx_bringup.c +else ifeq ($(CONFIG_BOARD_LATE_INITIALIZE),y) +CSRCS += gd32f4xx_bringup.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += gd32f4xx_autoleds.c +else +CSRCS += gd32f4xx_userleds.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += gd32f4xx_gpio.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += gd32f4xx_buttons.c +endif + +ifeq ($(CONFIG_SPI),y) +CSRCS += gd32f4xx_spi.c +endif + +ifeq ($(CONFIG_MMCSD),y) +CSRCS += gd32f4xx_sdio.c +endif + +ifeq ($(CONFIG_I2C), y) +CSRCS += gd32f4xx_i2c.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f450z_aiotbox.h b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f450z_aiotbox.h new file mode 100644 index 0000000000000..16649845f581b --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f450z_aiotbox.h @@ -0,0 +1,423 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f450z_aiotbox.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_GD32F4_GD32F450ZK_AIOTBOX_SRC_GD32F450Z_AIOTBOX_H +#define __BOARDS_ARM_GD32F4_GD32F450ZK_AIOTBOX_SRC_GD32F450Z_AIOTBOX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* procfs File System */ + +#ifdef CONFIG_FS_PROCFS +# ifdef CONFIG_NSH_PROC_MOUNTPOINT +# define GD32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT +# else +# define GD32_PROCFS_MOUNTPOINT "/proc" +# endif +#endif + +#ifdef CONFIG_FS_NXFFS +# ifndef CONFIG_GD32F4_NXFFS_MOUNTPT +# define CONFIG_GD32F4_NXFFS_MOUNTPT "/mnt/gd32nxffs" +# endif +#endif + +/* GD32F450ZK GPIO Pin Definitions ******************************************/ + +/* LED + * + * The GD32F450ZK-EVAL board has three LEDs, LED1, LED2 and LED3, that can be + * controlled by software. + * The following definitions assume the default Solder Bridges are installed. + */ + +#define GPIO_LED1 (GPIO_CFG_PORT_D | GPIO_CFG_OUTPUT_RESET | GPIO_PIN4_OUTPUT) +#define GPIO_LED2 (GPIO_CFG_PORT_D | GPIO_CFG_OUTPUT_RESET | GPIO_PIN5_OUTPUT) +#define GPIO_LED3 (GPIO_CFG_PORT_G | GPIO_CFG_OUTPUT_RESET | GPIO_PIN3_OUTPUT) + +#define LED1 GPIO_LED1 +#define LED2 GPIO_LED2 +#define LED3 GPIO_LED3 + +#define LED_DRIVER_PATH "/dev/userleds" + +/* BUTTONS + * + * The GD32F450Z Eval board has User, Tamper, and Wakeup key, the are + * connected to GPIO PB14, PC13 and PA0. + * A low value will be sensed when the button is depressed. + * + * Note: + * That the EXTI is included in the definition to enable + * an interrupt on this IO. + */ + +#define GPIO_BTN_USER (GPIO_CFG_PORT_B | GPIO_CFG_EXTI | GPIO_PIN14_INPUT) +#define GPIO_BTN_TAMPER (GPIO_CFG_PORT_C | GPIO_CFG_EXTI | GPIO_PIN13_INPUT) +#define GPIO_BTN_WAKEUP (GPIO_CFG_PORT_A | GPIO_CFG_EXTI | GPIO_PIN0_INPUT) +/* GPIO pins used by the GPIO Subsystem */ + +#define BOARD_NGPIOIN 1 /* Amount of GPIO Input pins */ +#define BOARD_NGPIOOUT 1 /* Amount of GPIO Output pins */ +#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ + +#define GPIO_IN1 (GPIO_CFG_MODE_INPUT | GPIO_CFG_PUPD_NONE | GPIO_CFG_PORT_B | GPIO_CFG_PIN_0) +#define GPIO_OUT1 (GPIO_CFG_MODE_OUTPUT | GPIO_CFG_OUTPUT_SET | GPIO_CFG_SPEED_50MHZ | \ + GPIO_CFG_PORT_B | GPIO_CFG_PIN_1) +#define GPIO_INT1 (GPIO_CFG_MODE_INPUT | GPIO_CFG_PUPD_NONE | GPIO_CFG_PORT_B | GPIO_CFG_PIN_2) + +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO + * support is not enabled. + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_GD32_SDIO) +# undef HAVE_SDIO +#endif + +#define SDIO_MINOR 0 /* Any minor number, default 0 */ +#define SDIO_SLOTNO 0 /* Only one slot */ + +#ifdef HAVE_SDIO +# if !defined(CONFIG_NSH_MMCSDSLOTNO) +# define CONFIG_NSH_MMCSDSLOTNO SDIO_SLOTNO +# elif CONFIG_NSH_MMCSDSLOTNO != 0 +# warning "Only one MMC/SD slot, slot 0" +# undef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO SDIO_SLOTNO +# endif + +# if defined(CONFIG_NSH_MMCSDMINOR) +# define SDIO_MINOR CONFIG_NSH_MMCSDMINOR +# else +# define SDIO_MINOR 0 +# endif +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Name: gd32_bringup + * + * Description: + * Perform architecture specific initialization + * + * CONFIG_BOARDCTL=y: + * If CONFIG_NSH_ARCHINIT=y: + * Called from the NSH library (or other application) + * Otherwise, assumed to be called from some other application. + * + * Otherwise CONFIG_BOARD_LATE_INITIALIZE=y: + * Called from board_late_initialize(). + * + * Otherwise, bad news: Never called + * + ****************************************************************************/ + +int gd32_bringup(void); + +/**************************************************************************** + * Name: gd32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the GD32F450Z + * Eval board. + * + ****************************************************************************/ + +#if defined(CONFIG_SPI) +void gd32_spidev_initialize(void); +#endif + +/**************************************************************************** + * Name: gd32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +#ifdef CONFIG_DEV_GPIO +int gd32_gpio_initialize(void); +#endif + +/**************************************************************************** + * Name: gd32_dma_alloc_init + * + * Description: + * Called to create a FAT DMA allocator + * + * Returned Value: + * 0 on success or -ENOMEM + * + ****************************************************************************/ + +void gd32_dma_alloc_init(void); + +#if defined (CONFIG_FAT_DMAMEMORY) +int gd32_dma_alloc_init(void); +#endif + +/**************************************************************************** + * Name: gd32_sdio_initialize + * + * Description: + * Called at application startup time to initialize the SCMMC + * functionality. + * + ****************************************************************************/ + +#ifdef CONFIG_MMCSD +int gd32_sdio_initialize(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_GD32F4_GD32F450ZK_AIOTBOX_SRC_GD32F450Z_AIOTBOX_H */ + +#ifdef CONFIG_I2C +void gd32_i2c_initialize(void); +#endif +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f450z_aiotbox.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_GD32F4_GD32F450ZK_AIOTBOX_SRC_GD32F450Z_AIOTBOX_H +#define __BOARDS_ARM_GD32F4_GD32F450ZK_AIOTBOX_SRC_GD32F450Z_AIOTBOX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* procfs File System */ + +#ifdef CONFIG_FS_PROCFS +# ifdef CONFIG_NSH_PROC_MOUNTPOINT +# define GD32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT +# else +# define GD32_PROCFS_MOUNTPOINT "/proc" +# endif +#endif + +#ifdef CONFIG_FS_NXFFS +# ifndef CONFIG_GD32F4_NXFFS_MOUNTPT +# define CONFIG_GD32F4_NXFFS_MOUNTPT "/mnt/gd32nxffs" +# endif +#endif + +/* GD32F450ZK GPIO Pin Definitions ******************************************/ + +/* LED + * + * The GD32F450ZK-EVAL board has three LEDs, LED1, LED2 and LED3, that can be + * controlled by software. + * The following definitions assume the default Solder Bridges are installed. + */ + +#define GPIO_LED1 (GPIO_CFG_PORT_D | GPIO_CFG_OUTPUT_RESET | GPIO_PIN4_OUTPUT) +#define GPIO_LED2 (GPIO_CFG_PORT_D | GPIO_CFG_OUTPUT_RESET | GPIO_PIN5_OUTPUT) +#define GPIO_LED3 (GPIO_CFG_PORT_G | GPIO_CFG_OUTPUT_RESET | GPIO_PIN3_OUTPUT) + +#define LED1 GPIO_LED1 +#define LED2 GPIO_LED2 +#define LED3 GPIO_LED3 + +#define LED_DRIVER_PATH "/dev/userleds" + +/* BUTTONS + * + * The GD32F450Z Eval board has User, Tamper, and Wakeup key, the are + * connected to GPIO PB14, PC13 and PA0. + * A low value will be sensed when the button is depressed. + * + * Note: + * That the EXTI is included in the definition to enable + * an interrupt on this IO. + */ + +#define GPIO_BTN_USER (GPIO_CFG_PORT_B | GPIO_CFG_EXTI | GPIO_PIN14_INPUT) +#define GPIO_BTN_TAMPER (GPIO_CFG_PORT_C | GPIO_CFG_EXTI | GPIO_PIN13_INPUT) +#define GPIO_BTN_WAKEUP (GPIO_CFG_PORT_A | GPIO_CFG_EXTI | GPIO_PIN0_INPUT) + +/* GPIO pins used by the GPIO Subsystem */ + +#define BOARD_NGPIOIN 1 /* Amount of GPIO Input pins */ +#define BOARD_NGPIOOUT 1 /* Amount of GPIO Output pins */ +#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ + +#define GPIO_IN1 (GPIO_CFG_MODE_INPUT | GPIO_CFG_PUPD_NONE | GPIO_CFG_PORT_B | GPIO_CFG_PIN_0) +#define GPIO_OUT1 (GPIO_CFG_MODE_OUTPUT | GPIO_CFG_OUTPUT_SET | GPIO_CFG_SPEED_50MHZ | \ + GPIO_CFG_PORT_B | GPIO_CFG_PIN_1) +#define GPIO_INT1 (GPIO_CFG_MODE_INPUT | GPIO_CFG_PUPD_NONE | GPIO_CFG_PORT_B | GPIO_CFG_PIN_2) + +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO + * support is not enabled. + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_GD32_SDIO) +# undef HAVE_SDIO +#endif + +#define SDIO_MINOR 0 /* Any minor number, default 0 */ +#define SDIO_SLOTNO 0 /* Only one slot */ + +#ifdef HAVE_SDIO +# if !defined(CONFIG_NSH_MMCSDSLOTNO) +# define CONFIG_NSH_MMCSDSLOTNO SDIO_SLOTNO +# elif CONFIG_NSH_MMCSDSLOTNO != 0 +# warning "Only one MMC/SD slot, slot 0" +# undef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO SDIO_SLOTNO +# endif + +# if defined(CONFIG_NSH_MMCSDMINOR) +# define SDIO_MINOR CONFIG_NSH_MMCSDMINOR +# else +# define SDIO_MINOR 0 +# endif +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Name: gd32_bringup + * + * Description: + * Perform architecture specific initialization + * + * CONFIG_BOARDCTL=y: + * If CONFIG_NSH_ARCHINIT=y: + * Called from the NSH library (or other application) + * Otherwise, assumed to be called from some other application. + * + * Otherwise CONFIG_BOARD_LATE_INITIALIZE=y: + * Called from board_late_initialize(). + * + * Otherwise, bad news: Never called + * + ****************************************************************************/ + +int gd32_bringup(void); + +/**************************************************************************** + * Name: gd32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the GD32F450Z + * Eval board. + * + ****************************************************************************/ + +#if defined(CONFIG_SPI) +void gd32_spidev_initialize(void); +#endif + +/**************************************************************************** + * Name: gd32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +#ifdef CONFIG_DEV_GPIO +int gd32_gpio_initialize(void); +#endif + +/**************************************************************************** + * Name: gd32_dma_alloc_init + * + * Description: + * Called to create a FAT DMA allocator + * + * Returned Value: + * 0 on success or -ENOMEM + * + ****************************************************************************/ + +void gd32_dma_alloc_init(void); + +#if defined (CONFIG_FAT_DMAMEMORY) +int gd32_dma_alloc_init(void); +#endif + +/**************************************************************************** + * Name: gd32_sdio_initialize + * + * Description: + * Called at application startup time to initialize the SCMMC + * functionality. + * + ****************************************************************************/ + +#ifdef CONFIG_MMCSD +int gd32_sdio_initialize(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_GD32F4_GD32F450ZK_AIOTBOX_SRC_GD32F450Z_AIOTBOX_H */ + +#ifdef CONFIG_I2C +void gd32_i2c_initialize(void); +#endif \ No newline at end of file diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_appinit.c b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_appinit.c new file mode 100644 index 0000000000000..76275d9b587c2 --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_appinit.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "gd32f4xx.h" +#include "gd32f450z_aiotbox.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + /* Perform board initialization here */ + + return gd32_bringup(); +} diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_autoleds.c b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_autoleds.c new file mode 100644 index 0000000000000..311a0881bfd8e --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_autoleds.c @@ -0,0 +1,177 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_autoleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "gd32f4xx_gpio.h" +#include "gd32f450z_aiotbox.h" +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* LED index */ + +static const uint32_t g_led_map[BOARD_LEDS] = +{ + LED1, + LED2, + LED3 +}; + +static bool g_initialized; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Turn on selected led */ + +static void gd32_aiotbox_led_on(led_typedef_enum led_num) +{ + gd32_gpio_write(g_led_map[led_num], true); +} + +/* Turn off selected led */ + +static void gd32_aiotbox_led_off(led_typedef_enum led_num) +{ + gd32_gpio_write(g_led_map[led_num], false); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + int i; + + /* Configure the LED GPIO for output. */ + + for (i = 0; i < nitems(g_led_map); i++) + { + gd32_gpio_config(g_led_map[i]); + } +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + default: + break; + + case LED_HEAPALLOCATE: + gd32_aiotbox_led_on(BOARD_LED1); + break; + + case LED_IRQSENABLED: + gd32_aiotbox_led_on(BOARD_LED2); + break; + + case LED_STACKCREATED: + gd32_aiotbox_led_on(BOARD_LED3); + g_initialized = true; + break; + + case LED_INIRQ: + gd32_aiotbox_led_on(BOARD_LED1); + gd32_aiotbox_led_on(BOARD_LED2); + break; + + case LED_SIGNAL: + gd32_aiotbox_led_on(BOARD_LED1); + gd32_aiotbox_led_on(BOARD_LED3); + break; + + case LED_ASSERTION: + gd32_aiotbox_led_on(BOARD_LED2); + gd32_aiotbox_led_on(BOARD_LED3); + break; + + case LED_PANIC: + gd32_aiotbox_led_on(BOARD_LED1); + break; + + case LED_IDLE : /* IDLE */ + gd32_aiotbox_led_on(BOARD_LED2); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + default: + break; + + case LED_SIGNAL: + gd32_aiotbox_led_off(BOARD_LED1); + gd32_aiotbox_led_off(BOARD_LED3); + break; + + case LED_INIRQ: + gd32_aiotbox_led_off(BOARD_LED1); + gd32_aiotbox_led_off(BOARD_LED2); + break; + + case LED_ASSERTION: + gd32_aiotbox_led_off(BOARD_LED2); + gd32_aiotbox_led_off(BOARD_LED3); + break; + + case LED_PANIC: + gd32_aiotbox_led_off(BOARD_LED1); + break; + + case LED_IDLE : /* IDLE */ + gd32_aiotbox_led_off(BOARD_LED2); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_boot.c b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_boot.c new file mode 100644 index 0000000000000..d8c90a8830060 --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_boot.c @@ -0,0 +1,85 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "gd32f450z_aiotbox.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_boardinitialize + * + * Description: + * All GD32F4xx architectures must provide the following entry point. + * This entry point is called early in the initialization + * after all memory has been configured and mapped but + * before any devices have been initialized. + * + ****************************************************************************/ + +void gd32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#if defined(CONFIG_SPI) + /* Configure SPI chip selects */ + + gd32_spidev_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() + * will be called immediately after up_initialize() is called and + * just before the initial application is started. This additional + * initialization phase may be used, for example, to initialize + * board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + gd32_bringup(); +} +#endif diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_bringup.c b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_bringup.c new file mode 100644 index 0000000000000..d068cec903f87 --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_bringup.c @@ -0,0 +1,363 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gd32f4xx.h" + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_GD32F4_ROMFS +#include "gd32f4xx_romfs.h" +#endif + +#include "gd32f450z_aiotbox.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y : + * Called from the NSH library via boardctl() + * + ****************************************************************************/ + +int gd32_bringup(void) +{ +#ifdef CONFIG_RAMMTD + uint8_t *ramstart; +#endif + + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, GD32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", + GD32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_RAMMTD + /* Create a RAM MTD device if configured */ + + ramstart = kmm_malloc(64 * 1024); + if (ramstart == NULL) + { + syslog(LOG_ERR, "ERROR: Allocation for RAM MTD failed\n"); + } + else + { + /* Initialized the RAM MTD */ + + struct mtd_dev_s *mtd = rammtd_initialize(ramstart, 64 * 1024); + if (mtd == NULL) + { + syslog(LOG_ERR, "ERROR: rammtd_initialize failed\n"); + kmm_free(ramstart); + } + else + { + /* Erase the RAM MTD */ + + ret = mtd->ioctl(mtd, MTDIOC_BULKERASE, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: IOCTL MTDIOC_BULKERASE failed\n"); + } + +#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) + /* Initialize a SMART Flash block device and bind it to the MTD + * device. + */ + + smart_initialize(0, mtd, NULL); + +#elif defined(CONFIG_FS_SPIFFS) + /* Register the MTD driver so that it can be accessed from the + * VFS. + */ + + ret = register_mtddriver("/dev/rammtd", mtd, 0755, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD driver: %d\n", + ret); + } + + /* Mount the SPIFFS file system */ + + ret = nx_mount("/dev/rammtd", "/mnt/spiffs", "spiffs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount SPIFFS at /mnt/spiffs: %d\n", + ret); + } + +#elif defined(CONFIG_FS_LITTLEFS) + /* Register the MTD driver so that it can be accessed from the + * VFS. + */ + + ret = register_mtddriver("/dev/rammtd", mtd, 0755, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD driver: %d\n", + ret); + } + + /* Mount the LittleFS file system */ + + ret = nx_mount("/dev/rammtd", "/mnt/lfs", "littlefs", 0, + "forceformat"); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount LittleFS at /mnt/lfs: %d\n", + ret); + } + +#elif defined(CONFIG_FS_NXFFS) + /* Initialize to provide NXFFS on the MTD interface */ + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: NXFFS initialization failed: %d\n", + ret); + } +#endif + } + } +#endif + +#if defined(CONFIG_INPUT_BUTTONS_LOWER) + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_GD32F4_ROMFS + /* Mount the romfs partition */ + + ret = gd32_romfs_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", + CONFIG_GD32F4_ROMFS_MOUNTPOINT, ret); + } +#endif + +#ifndef CONFIG_DISABLE_MOUNTPOINT + +# ifdef CONFIG_GD32F4_PROGMEM + + /* Create an instance of the GD32F4 FLASH program memory + * device driver + */ + + struct mtd_dev_s *mtd = progmem_initialize(); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: progmem_initialize failed\n"); + } + +# if defined(CONFIG_FS_NXFFS) + /* Initialize to provide NXFFS on the MTD interface */ + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: NXFFS initialization failed: %d\n", + ret); + } + + /* Mount the file system */ + + ret = nx_mount(NULL, CONFIG_GD32F4_NXFFS_MOUNTPT, "nxffs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the NXFFS volume: %d\n", + ret); + } +# elif defined(CONFIG_FS_LITTLEFS) + /* Initialize to provide LittleFS on the MTD interface */ + + ret = register_mtddriver("/dev/fmc", mtd, 0755, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); + return ret; + } + + /* Mount the file system at /mnt/fmc */ + + ret = nx_mount("/dev/fmc", "/mnt/fmc", "littlefs", 0, NULL); + if (ret < 0) + { + ret = nx_mount("/dev/fmc", "/mnt/fmc", "littlefs", 0, + "forceformat"); + if (ret < 0) + { + ferr("ERROR: Failed to mount the FS volume: %d\n", ret); + return ret; + } + } + + syslog(LOG_INFO, "INFO: LittleFS volume /mnt/fmc mount " \ + "on chip flash success: %d\n", ret); +# endif +# endif + +# ifdef HAVE_GD25 + + ret = gd32_gd25_automount(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the NXFFS \ + volume on spi flash: %d\n", ret); + } + +# endif + +# ifdef HAVE_AT24 + + ret = gd32_at24_wr_test(AT24_MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: I2C EEPROM write and read test fail: \ + %d\n", ret); + } + +# endif + +#endif /* CONFIG_FS_NXFFS */ + +#ifdef CONFIG_DEV_GPIO + /* Register the GPIO driver */ + + ret = gd32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_I2C + gd32_i2c_initialize(); +#endif + +#ifdef CONFIG_INPUT_BUTTONS +#ifdef CONFIG_INPUT_BUTTONS_LOWER + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + return ret; + } +#else + /* Enable BUTTON support for some other purpose */ + + board_button_initialize(); +#endif /* CONFIG_INPUT_BUTTONS_LOWER */ +#endif /* CONFIG_INPUT_BUTTONS */ + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", + ret); + } +#endif + + /* Configure SDIO chip selects */ + +#ifdef CONFIG_ARCH_HAVE_SDIO + ret = gd32_sdio_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: gd32_sdio_initialize() failed: %d\n", ret); + return ret; + } + + /* Mount the file system at /mnt/sd */ + + ret = nx_mount("/dev/mmcsd0", "/mnt/sd", "vfat", 0, NULL); + if (ret < 0) + { + ret = nx_mount("/dev/mmcsd0", "/mnt/sd", "vfat", 0, + "forceformat"); + if (ret < 0) + { + ferr("ERROR: Failed to mount the SD card: %d\n", ret); + return ret; + } + } + + syslog(LOG_INFO, "INFO: FAT volume /mnt/sd mount " \ + "sd card success: %d\n", ret); +#endif + return ret; +} diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_buttons.c b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_buttons.c new file mode 100644 index 0000000000000..3506eca15fd0c --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_buttons.c @@ -0,0 +1,190 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_buttons.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "gd32f4xx.h" +#include "gd32f450z_aiotbox.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint32_t g_button_boards[NUM_BUTTONS] = +{ + GPIO_BTN_USER, GPIO_BTN_TAMPER, GPIO_BTN_WAKEUP +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure each button */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + gd32_gpio_config(g_button_boards[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the BUTTON* + * definitions above for the meaning of each bit in the returned value. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret; + int i; + + /* Check each button */ + + for (i = 0, ret = 0; i < NUM_BUTTONS; i++) + { + /* The low value is sensed when the button is pressed */ + + if (!gd32_gpio_read(g_button_boards[i])) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current + * state of all buttons or board_button_irq() may be called to register + * button interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() + * may be called to collect the state of all buttons. board_buttons() + * returns an 32-bit bit set with each bit associated with a button. + * See the BUTTON_*_BIT definitions in board.h for the meaning of each + * bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value + * is a button enumeration value that uniquely identifies a button + * resource. See the BUTTON_* definitions in board.h for the meaning of + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + if (id >= 0 && id < NUM_BUTTONS) + { + uint8_t gpio_irq; + uint8_t gpio_irqnum; + irqstate_t flags; + int ret; + + /* Disable interrupts until we are done. This guarantees that the + * following operations are atomic. + */ + + flags = enter_critical_section(); + + /* Get gpio irq numbers */ + + ret = gd32_gpio_exti_irqnum_get(g_button_boards[id], &gpio_irqnum); + + if (ret < 0) + { + leave_critical_section(flags); + return ret; + } + + /* Are we attaching or detaching? */ + + if (irqhandler != NULL) + { + ret = gd32_exti_gpioirq_init(g_button_boards[id], EXTI_INTERRUPT, + EXTI_TRIG_RISING, &gpio_irq); + + if (ret < 0) + { + leave_critical_section(flags); + return ret; + } + + /* Attach and enable the interrupt */ + + gd32_exti_gpio_irq_attach(gpio_irq, irqhandler, arg); + up_enable_irq(gpio_irqnum); + } + else + { + /* Disable and detach the interrupt */ + + up_disable_irq(gpio_irqnum); + irq_detach(gpio_irqnum); + } + + leave_critical_section(flags); + } + + /* Return the old button handler (so that it can be restored) */ + + return OK; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_gpio.c b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_gpio.c new file mode 100644 index 0000000000000..b9c279c0953c9 --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_gpio.c @@ -0,0 +1,397 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" + +#include "gd32f4xx.h" +#include "gd32f450z_aiotbox.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct gd32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct gd32gpint_dev_s +{ + struct gd32gpio_dev_s gd32gpio; + pin_interrupt_t callback; +}; + +irqstate_t flags; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int gpio_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e gp_pintype); + +#if BOARD_NGPIOIN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value); +#endif + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +#endif + +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + + #if BOARD_NGPIOIN > 0 +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, + .go_setpintype = gpio_setpintype, +}; + +/* This array maps the GPIO pins used as INPUT */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1, +}; + +static struct gd32gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOOUT > 0 + +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, + .go_setpintype = gpio_setpintype, +}; + +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, +}; + +static struct gd32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 + +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, + .go_setpintype = gpio_setpintype, +}; + +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_INT1, +}; + +static struct gd32gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpio_setpintype + * + * Description: + * set gpio pintype. + * + ****************************************************************************/ + +static int gpio_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e gpio_pintype) +{ + struct gd32gpint_dev_s *gd32gpint = (struct gd32gpint_dev_s *)dev; + + UNUSED(gd32gpint); + UNUSED(gpio_pintype); + + gpioinfo("setpintype is not supported. \n"); + + return 0; +} + +#if BOARD_NGPIOIN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value) +{ + struct gd32gpio_dev_s *gd32gpio = (struct gd32gpio_dev_s *)dev; + + DEBUGASSERT(gd32gpio != NULL && value != NULL); + DEBUGASSERT(gd32gpio->id < BOARD_NGPIOIN); + gpioinfo("Reading...\n"); + + *value = gd32_gpio_read(g_gpioinputs[gd32gpio->id]); + return OK; +} +#endif + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct gd32gpio_dev_s *gd32gpio = (struct gd32gpio_dev_s *)dev; + + DEBUGASSERT(gd32gpio != NULL && value != NULL); + DEBUGASSERT(gd32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = gd32_gpio_read(g_gpiooutputs[gd32gpio->id]); + return OK; +} + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct gd32gpio_dev_s *gd32gpio = (struct gd32gpio_dev_s *)dev; + + DEBUGASSERT(gd32gpio != NULL); + DEBUGASSERT(gd32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + gd32_gpio_write(g_gpiooutputs[gd32gpio->id], value); + return OK; +} +#endif + +#if BOARD_NGPIOINT > 0 + +static int gd32gpio_interrupt(int irq, void *context, void *arg) +{ + struct gd32gpint_dev_s *gd32gpint = (struct gd32gpint_dev_s *)arg; + + DEBUGASSERT(gd32gpint != NULL && gd32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", gd32gpint->callback); + + gd32gpint->callback(&gd32gpint->gd32gpio.gpio, gd32gpint->gd32gpio.id); + return OK; +} + +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct gd32gpint_dev_s *gd32gpint = (struct gd32gpint_dev_s *)dev; + + DEBUGASSERT(gd32gpint != NULL && value != NULL); + DEBUGASSERT(gd32gpint->gd32gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = gd32_gpio_read(g_gpiointinputs[gd32gpint->gd32gpio.id]); + return OK; +} + +static int gpint_attach(struct gpio_dev_s *dev, pin_interrupt_t callback) +{ + struct gd32gpint_dev_s *gd32gpint = (struct gd32gpint_dev_s *)dev; + int ret; + uint8_t gpio_irq; + uint8_t gpio_irqnum; + + gpioinfo("Attaching the callback\n"); + + flags = enter_critical_section(); + + /* Make sure the interrupt is disabled */ + + ret = gd32_exti_gpioirq_init(g_gpiointinputs[gd32gpint->gd32gpio.id], + EXTI_INTERRUPT, EXTI_TRIG_RISING, &gpio_irq); + + if (ret < 0) + { + leave_critical_section(flags); + return ret; + } + + gd32_gpio_exti_irqnum_get(g_gpiointinputs[gd32gpint->gd32gpio.id], + &gpio_irqnum); + + /* Attach and disable the interrupt */ + + gd32_exti_gpio_irq_attach(gpio_irq, gd32gpio_interrupt, + &g_gpint[gd32gpint->gd32gpio.id]); + + /* Disable and the interrupt */ + + up_disable_irq(gpio_irqnum); + + leave_critical_section(flags); + gpioinfo("Attach %p\n", callback); + gd32gpint->callback = callback; + return OK; +} + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct gd32gpint_dev_s *gd32gpint = (struct gd32gpint_dev_s *)dev; + int ret; + uint8_t gpio_irqnum; + + flags = enter_critical_section(); + + /* Get gpio irq numbers */ + + ret = gd32_gpio_exti_irqnum_get(g_gpiointinputs[gd32gpint->gd32gpio.id], + &gpio_irqnum); + if (ret < 0) + { + leave_critical_section(flags); + return ret; + } + + if (enable) + { + if (gd32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Enable the interrupt */ + + up_disable_irq(gpio_irqnum); + } + } + else + { + up_disable_irq(gpio_irqnum); + gpioinfo("Disable the interrupt\n"); + } + + leave_critical_section(flags); + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int gd32_gpio_initialize(void) +{ + int pincount = 0; + int i; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + + gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pin that will be used as input */ + + gd32_gpio_config(g_gpioinputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pin that will be used as output */ + + gd32_gpio_write(g_gpiooutputs[i], 0); + gd32_gpio_config(g_gpiooutputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].gd32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].gd32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].gd32gpio.id = i; + (void)gpio_pin_register(&g_gpint[i].gd32gpio.gpio, pincount); + + /* Configure the pin that will be used as interrupt input */ + + gd32_gpio_config(g_gpiointinputs[i]); + + pincount++; + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_i2c.c b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_i2c.c new file mode 100644 index 0000000000000..259c3ac72521b --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_i2c.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_i2c.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ +#include +#include +#include +#include +#include + +#include + +#include"gd32f4xx.h" +#include"gd32f450z_aiotbox.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_I2C +void gd32_i2c_initialize(void) +{ + FAR struct i2c_master_s *i2c; + int ret; + i2cinfo("Initialize I2c\n"); + +#ifdef CONFIG_GD32F4_I2C0 + i2c = gd32_i2cbus_initialize(0); + + if (i2c == NULL) + { + i2cerr("init i2c0 faild.\n"); + return; + } + else + { + ret = i2c_register(i2c, 0); + + if (ret < 0) + { + i2cerr("registering i2c0 faild.\n"); + } + else + { + i2cinfo("registering i2c0 successed.\n"); + } + } + + i2c = NULL; +#endif +#ifdef CONFIG_GD32F4_I2C1 + i2c = gd32_i2cbus_initialize(1); + + if (i2c == NULL) + { + i2cerr("init i2c1 faild.\n"); + return; + } + else + { + ret = i2c_register(i2c, 1); + + if (ret < 0) + { + i2cerr("registering i2c1 faild.\n"); + } + else + { + i2cinfo("registering i2c1 successed.\n"); + } + } + +#endif +} + +#endif \ No newline at end of file diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_romfs.c b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_romfs.c new file mode 100644 index 0000000000000..1dccd7521ee13 --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_romfs.c @@ -0,0 +1,137 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_romfs.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include "gd32f4xx_romfs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_GD32F4_ROMFS +# error "CONFIG_GD32F4_ROMFS must be defined" +#else + +#ifndef CONFIG_GD32F4_ROMFS_IMAGEFILE +# error "CONFIG_GD32F4_ROMFS_IMAGEFILE must be defined" +#endif + +#ifndef CONFIG_GD32F4_ROMFS_DEV_MINOR +# error "CONFIG_GD32F4_ROMFS_DEV_MINOR must be defined" +#endif + +#ifndef CONFIG_GD32F4_ROMFS_MOUNTPOINT +# error "CONFIG_GD32F4_ROMFS_MOUNTPOINT must be defined" +#endif + +#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) + +#define STR2(m) #m +#define STR(m) STR2(m) + +#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) +#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_GD32F4_ROMFS_DEV_MINOR) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +__asm__ ( + " .section .rodata \n" + " .balign 16 \n" + " .globl romfs_data_begin \n" + "romfs_data_begin: \n" + " .incbin " STR(CONFIG_GD32F4_ROMFS_IMAGEFILE)"\n" + " .balign " STR(ROMFS_SECTOR_SIZE) "\n" + " .globl romfs_data_end \n" + "romfs_data_end: \n" + ); + +extern const uint8_t romfs_data_begin[]; +extern const uint8_t romfs_data_end[]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_romfs_initialize + * + * Description: + * Registers the aboveincluded binary file as block device. + * Then mounts the block device as ROMFS filesystems. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [romfs_data_begin .. romfs_data_end) should contain + * ROMFS volume data, as included in the assembly snippet above. + * + ****************************************************************************/ + +int gd32_romfs_initialize(void) +{ + uintptr_t romfs_data_len; + int ret; + + /* Create a ROM disk for the /etc filesystem */ + + romfs_data_len = romfs_data_end - romfs_data_begin; + + ret = romdisk_register(CONFIG_GD32F4_ROMFS_DEV_MINOR, romfs_data_begin, + NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); + if (ret < 0) + { + ferr("ERROR: romdisk_register failed: %d\n", -ret); + return ret; + } + + /* Mount the file system */ + + finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", + CONFIG_GD32F4_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); + + ret = nx_mount(MOUNT_DEVNAME, CONFIG_GD32F4_ROMFS_MOUNTPOINT, + "romfs", MS_RDONLY, NULL); + if (ret < 0) + { + ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", + MOUNT_DEVNAME, CONFIG_GD32F4_ROMFS_MOUNTPOINT, ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_GD32F4_ROMFS */ diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_romfs.h b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_romfs.h new file mode 100644 index 0000000000000..4f07aa926fa89 --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_romfs.h @@ -0,0 +1,62 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_romfs.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_GD32F4_GD32F450ZK_AIOTBOX_SRC_GD32F4XX_ROMFS_H +#define __BOARDS_ARM_GD32F4_GD32F450ZK_AIOTBOX_SRC_GD32F4XX_ROMFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_GD32F4_ROMFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ROMFS_SECTOR_SIZE 64 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_romfs_initialize + * + * Description: + * Registers built-in ROMFS image as block device and mounts it. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [romfs_data_begin .. romfs_data_end) should contain + * ROMFS volume data, as included in the assembly snippet in + * gd32f4xx_romfs.c. + * + ****************************************************************************/ + +int gd32_romfs_initialize(void); + +#endif /* CONFIG_GD32F4_ROMFS */ + +#endif /* __BOARDS_ARM_GD32F4_GD32F450ZK_EVAL_SRC_GD32F4XX_ROMFS_H */ diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_sdio.c b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_sdio.c new file mode 100644 index 0000000000000..b60338c225765 --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_sdio.c @@ -0,0 +1,149 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_sdio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "gd32f4xx.h" +#include "gd32f450z_aiotbox.h" + +#ifdef CONFIG_MMCSD + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Card detections requires card support and a card detection GPIO */ + +#define HAVE_NCD 1 +#if !defined(GPIO_SDMMC1_NCD) +# undef HAVE_NCD +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; +#ifdef HAVE_NCD +static bool g_sd_inserted; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_ncd_interrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef HAVE_NCD +static int gd32_ncd_interrupt(int irq, void *context) +{ + bool present; + + present = !gd32_gpio_read(GPIO_SDMMC1_NCD); + if (g_sdio_dev && present != g_sd_inserted) + { + sdio_mediachange(g_sdio_dev, present); + g_sd_inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +int gd32_sdio_initialize(void) +{ + int ret; + + /* Mount the SDIO-based MMC/SD block driver + * First, get an instance of the SDIO interface + */ + + finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_SLOTNO); + if (!g_sdio_dev) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); + + ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); + if (ret != OK) + { + ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + finfo("Successfully bound SDIO to the MMC/SD driver\n"); + +#ifdef HAVE_NCD + /* Use SD card detect pin to check if a card is g_sd_inserted */ + + g_sd_inserted = !gd32_gpio_read(GPIO_SDMMC1_NCD); + finfo("Card detect : %d\n", g_sd_inserted); + + sdio_mediachange(g_sdio_dev, g_sd_inserted); +#else + /* Assume that the SD card is inserted. What choice do we have? */ + + sdio_mediachange(g_sdio_dev, true); +#endif + + return OK; +} + +#endif /* CONFIG_MMCSD */ diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_spi.c b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_spi.c new file mode 100644 index 0000000000000..e0a133ad24472 --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_spi.c @@ -0,0 +1,283 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_spi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "gd32f4xx.h" +#include "gd32f450z_aiotbox.h" + +#if defined(CONFIG_SPI) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the GD32F450Z-EVAL. + * + ****************************************************************************/ + +void weak_function gd32_spidev_initialize(void) +{ +#ifdef CONFIG_GD32F4_SPI0 + /* Configure SPI0 CS GPIO for output */ + + gd32_gpio_config(GPIO_SPI0_CSPIN); + gd32_gpio_write(GPIO_SPI0_CSPIN, 1); +#endif +#ifdef CONFIG_GD32F4_SPI1 + /* Configure SPI1 CS GPIO for output */ + + gd32_gpio_config(GPIO_SPI1_CSPIN); + gd32_gpio_write(GPIO_SPI1_CSPIN, 1); +#endif +#ifdef CONFIG_GD32F4_SPI2 + /* Configure SPI2 CS GPIO for output */ + + gd32_gpio_config(GPIO_SPI2_CSPIN); + gd32_gpio_write(GPIO_SPI2_CSPIN, 1); +#endif +#ifdef CONFIG_GD32F4_SPI3 + /* Configure SPI3 CS GPIO for output */ + + gd32_gpio_config(GPIO_SPI3_CSPIN); + gd32_gpio_write(GPIO_SPI3_CSPIN, 1); +#endif +#ifdef CONFIG_GD32F4_SPI4 + /* Configure SPI4 CS GPIO for output */ + + gd32_gpio_config(GPIO_SPI4_CSPIN); + gd32_gpio_write(GPIO_SPI4_CSPIN, 1); +#endif +#ifdef CONFIG_GD32F4_SPI5 + /* Configure SPI5 CS GPIO for output */ + + gd32_gpio_config(GPIO_SPI5_CSPIN); + gd32_gpio_write(GPIO_SPI5_CSPIN, 1); +#endif +} + +/**************************************************************************** + * Name: gd32_spi[n]select and gd32_spi[n]status + * + * Description: + * The external functions, gd32_spi0-5select and gd32_spi0-5 status + * must be provided by board-specific logic. They are implementations of the + * select and status methods of the SPI interface defined by struct spi_ops_s + * (see include/nuttx/spi/spi.h). + * All other methods (including gd32_spibus_initialize()) are provided by + * common GD32F4 logic. To use this common SPI logic on your board: + * + * 1. Provide logic in gd32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide gd32_spi[n]select() and gd32_spi[n]status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to gd32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by gd32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_GD32F4_SPI0 +void gd32_spi0select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + gd32_gpio_write(GPIO_SPI0_CSPIN, !selected); +} + +uint8_t gd32_spi0status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_GD32F4_SPI1 +void gd32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + gd32_gpio_write(GPIO_SPI1_CSPIN, !selected); +} + +uint8_t gd32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_GD32F4_SPI2 +void gd32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + gd32_gpio_write(GPIO_SPI2_CSPIN, !selected); +} + +uint8_t gd32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_GD32F4_SPI3 +void gd32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + gd32_gpio_write(GPIO_SPI3_CSPIN, !selected); +} + +uint8_t gd32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_GD32F4_SPI4 +void gd32_spi4select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + gd32_gpio_write(GPIO_SPI4_CSPIN, !selected); +} + +uint8_t gd32_spi4status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_GD32F4_SPI5 +void gd32_spi5select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + gd32_gpio_write(GPIO_SPI5_CSPIN, !selected); +} + +uint8_t gd32_spi5status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: gd32_spi[n]cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_GD32F4_SPI0 +int gd32_spi0cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_GD32F4_SPI1 +int gd32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_GD32F4_SPI2 +int gd32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_GD32F4_SPI3 +int gd32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_GD32F4_SPI5 +int gd32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_GD32F4_SPI5 +int gd32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* defined(CONFIG_SPI) */ diff --git a/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_userleds.c b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_userleds.c new file mode 100644 index 0000000000000..554f3de9c3205 --- /dev/null +++ b/boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_userleds.c @@ -0,0 +1,149 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f450zk-aiotbox/src/gd32f4xx_userleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "gd32f4xx_gpio.h" +#include "gd32f450z_aiotbox.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* LED index */ + +static const uint32_t g_led_map[BOARD_LEDS] = +{ + LED1, + LED2, + LED3 +}; + +static const uint32_t g_led_setmap[BOARD_LEDS] = +{ + BOARD_LED1_BIT, + BOARD_LED2_BIT, + BOARD_LED3_BIT +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Turn on selected led */ + +static void gd32_aiotbox_led_on(led_typedef_enum led_num) +{ + gd32_gpio_write(g_led_map[led_num], true); +} + +/* Turn off selected led */ + +static void gd32_aiotbox_led_off(led_typedef_enum led_num) +{ + gd32_gpio_write(g_led_map[led_num], false); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the + * board_userled_initialize() is available to initialize the LED from user + * application logic. + * + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure the LED GPIO for output. */ + + for (i = 0; i < nitems(g_led_map); i++) + { + gd32_gpio_config(g_led_map[i]); + } + + return BOARD_LEDS; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is + * available to control the LED from user application logic. + * + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < nitems(g_led_map)) + { + gd32_gpio_write(g_led_map[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all() + * is available to control the LED from user application logic. + * NOTE: since there is only a single LED on-board, this is function + * is not very useful. + * + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED1-3 GPIOs for output */ + + for (i = 0; i < nitems(g_led_map); i++) + { + gd32_gpio_write(g_led_map[i], (ledset & g_led_setmap[i]) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/gd32f4/gd32f450zk-eval/src/Makefile b/boards/arm/gd32f4/gd32f450zk-eval/src/Makefile index 227eef9f65b3d..78d608d6b2c9d 100644 --- a/boards/arm/gd32f4/gd32f450zk-eval/src/Makefile +++ b/boards/arm/gd32f4/gd32f450zk-eval/src/Makefile @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/gd32f4/gd32f450zk-eval/src/Make.defs +# boards/arm/gd32f4/gd32f450zk-eval/src/Makefile # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with @@ -22,15 +22,16 @@ include $(TOPDIR)/Make.defs CSRCS = gd32f4xx_boot.c -ifeq ($(CONFIG_BOARDCTL),y) -CSRCS += gd32f4xx_appinit.c -endif # ifeq ($(CONFIG_BOARDCTL),y) -# CSRCS += gd32f4xx_appinit.c gd32f4xx_bringup.c -# else ifeq ($(CONFIG_BOARD_LATE_INITIALIZE),y) -# CSRCS += gd32f4xx_bringup.c +# CSRCS += gd32f4xx_appinit.c # endif +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += gd32f4xx_appinit.c gd32f4xx_bringup.c +else ifeq ($(CONFIG_BOARD_LATE_INITIALIZE),y) +CSRCS += gd32f4xx_bringup.c +endif + ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += gd32f4xx_autoleds.c else diff --git a/boards/arm/gd32f4/gd32f450zk-eval/src/gd32f450z_eval.h b/boards/arm/gd32f4/gd32f450zk-eval/src/gd32f450z_eval.h index 02f8f7d651003..f078889805508 100644 --- a/boards/arm/gd32f4/gd32f450zk-eval/src/gd32f450z_eval.h +++ b/boards/arm/gd32f4/gd32f450zk-eval/src/gd32f450z_eval.h @@ -180,6 +180,26 @@ #ifndef __ASSEMBLY__ +/**************************************************************************** + * Name: gd32_bringup + * + * Description: + * Perform architecture specific initialization + * + * CONFIG_BOARDCTL=y: + * If CONFIG_NSH_ARCHINIT=y: + * Called from the NSH library (or other application) + * Otherwise, assumed to be called from some other application. + * + * Otherwise CONFIG_BOARD_LATE_INITIALIZE=y: + * Called from board_late_initialize(). + * + * Otherwise, bad news: Never called + * + ****************************************************************************/ + +int gd32_bringup(void); + /**************************************************************************** * Name: gd32_spidev_initialize * diff --git a/boards/arm/gd32f4/gd32f450zk-eval/src/gd32f4xx_appinit.c b/boards/arm/gd32f4/gd32f450zk-eval/src/gd32f4xx_appinit.c index 81858f06f9454..89b9f0017c083 100644 --- a/boards/arm/gd32f4/gd32f450zk-eval/src/gd32f4xx_appinit.c +++ b/boards/arm/gd32f4/gd32f450zk-eval/src/gd32f4xx_appinit.c @@ -24,24 +24,14 @@ #include -#include -#include +#include +#include #include +#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_GD32F4_ROMFS -#include "gd32f4xx_romfs.h" -#endif +#include +#include "gd32f4xx.h" #include "gd32f450z_eval.h" /**************************************************************************** @@ -75,192 +65,7 @@ int board_app_initialize(uintptr_t arg) { - int ret; - static bool initialized = false; - - /* Have we already initialized? */ - - if (!initialized) - { -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, GD32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", - GD32_PROCFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_GD32F4_ROMFS - /* Mount the romfs partition */ - - ret = gd32_romfs_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_GD32F4_ROMFS_MOUNTPOINT, ret); - } -#endif - -#ifndef CONFIG_DISABLE_MOUNTPOINT - -# ifdef CONFIG_GD32F4_PROGMEM - - /* Create an instance of the GD32F4 FLASH program memory - * device driver - */ - - struct mtd_dev_s *mtd = progmem_initialize(); - if (!mtd) - { - syslog(LOG_ERR, "ERROR: progmem_initialize failed\n"); - } - -# if defined(CONFIG_FS_NXFFS) - /* Initialize to provide NXFFS on the MTD interface */ - - ret = nxffs_initialize(mtd); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: NXFFS initialization failed: %d\n", - ret); - } - - /* Mount the file system */ - - ret = nx_mount(NULL, CONFIG_GD32F4_NXFFS_MOUNTPT, "nxffs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount the NXFFS volume: %d\n", - ret); - } -# elif defined(CONFIG_FS_LITTLEFS) - /* Initialize to provide LittleFS on the MTD interface */ - - ret = register_mtddriver("/dev/fmc", mtd, 0755, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); - return ret; - } - - /* Mount the file system at /mnt/fmc */ - - ret = nx_mount("/dev/fmc", "/mnt/fmc", "littlefs", 0, NULL); - if (ret < 0) - { - ret = nx_mount("/dev/fmc", "/mnt/fmc", "littlefs", 0, - "forceformat"); - if (ret < 0) - { - ferr("ERROR: Failed to mount the FS volume: %d\n", ret); - return ret; - } - } - - syslog(LOG_INFO, "INFO: LittleFS volume /mnt/fmc mount " \ - "on chip flash success: %d\n", ret); -# endif -# endif - -# ifdef HAVE_GD25 - - ret = gd32_gd25_automount(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount the NXFFS \ - volume on spi flash: %d\n", ret); - } - -# endif - -# ifdef HAVE_AT24 - - ret = gd32_at24_wr_test(AT24_MINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: I2C EEPROM write and read test fail: \ - %d\n", ret); - } - -# endif - -#endif /* CONFIG_FS_NXFFS */ - -#ifdef CONFIG_DEV_GPIO - /* Register the GPIO driver */ - - ret = gd32_gpio_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS -#ifdef CONFIG_INPUT_BUTTONS_LOWER - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - return ret; - } -#else - /* Enable BUTTON support for some other purpose */ - - board_button_initialize(); -#endif /* CONFIG_INPUT_BUTTONS_LOWER */ -#endif /* CONFIG_INPUT_BUTTONS */ - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", - ret); - } -#endif - - /* Configure SDIO chip selects */ - -#ifdef CONFIG_ARCH_HAVE_SDIO - ret = gd32_sdio_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: gd32_sdio_initialize() failed: %d\n", ret); - return ret; - } - - /* Mount the file system at /mnt/sd */ - - ret = nx_mount("/dev/mmcsd0", "/mnt/sd", "vfat", 0, NULL); - if (ret < 0) - { - ret = nx_mount("/dev/mmcsd0", "/mnt/sd", "vfat", 0, - "forceformat"); - if (ret < 0) - { - ferr("ERROR: Failed to mount the SD card: %d\n", ret); - return ret; - } - } - - syslog(LOG_INFO, "INFO: FAT volume /mnt/sd mount " \ - "sd card success: %d\n", ret); -#endif - - /* Now we are initialized */ - - initialized = true; - } + /* Perform board initialization here */ - UNUSED(ret); - return OK; + return gd32_bringup(); } diff --git a/boards/arm/gd32f4/gd32f450zk-eval/src/gd32f4xx_boot.c b/boards/arm/gd32f4/gd32f450zk-eval/src/gd32f4xx_boot.c index 1a36b5aaa1653..dd3b25f99f9a3 100644 --- a/boards/arm/gd32f4/gd32f450zk-eval/src/gd32f4xx_boot.c +++ b/boards/arm/gd32f4/gd32f450zk-eval/src/gd32f4xx_boot.c @@ -78,13 +78,8 @@ void gd32_boardinitialize(void) #ifdef CONFIG_BOARD_LATE_INITIALIZE void board_late_initialize(void) { -#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_BOARDCTL) - /* Perform NSH initialization here instead of from the NSH. This - * alternative NSH initialization is necessary when NSH is ran in - * user-space but the initialization function must run in kernel space. - */ + /* Perform board-specific initialization */ - board_app_initialize(0); -#endif + gd32_bringup(); } #endif diff --git a/boards/arm/gd32f4/gd32f450zk-eval/src/gd32f4xx_bringup.c b/boards/arm/gd32f4/gd32f450zk-eval/src/gd32f4xx_bringup.c index 1cf8d19f36962..9ce24c29ebaf2 100644 --- a/boards/arm/gd32f4/gd32f450zk-eval/src/gd32f4xx_bringup.c +++ b/boards/arm/gd32f4/gd32f450zk-eval/src/gd32f4xx_bringup.c @@ -35,10 +35,23 @@ #include #include #include -#include #include #include +#include "gd32f4xx.h" + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_GD32F4_ROMFS +#include "gd32f4xx_romfs.h" +#endif + #include "gd32f450z_eval.h" /**************************************************************************** @@ -180,5 +193,167 @@ int gd32_bringup(void) } #endif +#ifdef CONFIG_GD32F4_ROMFS + /* Mount the romfs partition */ + + ret = gd32_romfs_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", + CONFIG_GD32F4_ROMFS_MOUNTPOINT, ret); + } +#endif + +#ifndef CONFIG_DISABLE_MOUNTPOINT + +# ifdef CONFIG_GD32F4_PROGMEM + + /* Create an instance of the GD32F4 FLASH program memory + * device driver + */ + + struct mtd_dev_s *mtd = progmem_initialize(); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: progmem_initialize failed\n"); + } + +# if defined(CONFIG_FS_NXFFS) + /* Initialize to provide NXFFS on the MTD interface */ + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: NXFFS initialization failed: %d\n", + ret); + } + + /* Mount the file system */ + + ret = nx_mount(NULL, CONFIG_GD32F4_NXFFS_MOUNTPT, "nxffs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the NXFFS volume: %d\n", + ret); + } +# elif defined(CONFIG_FS_LITTLEFS) + /* Initialize to provide LittleFS on the MTD interface */ + + ret = register_mtddriver("/dev/fmc", mtd, 0755, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); + return ret; + } + + /* Mount the file system at /mnt/fmc */ + + ret = nx_mount("/dev/fmc", "/mnt/fmc", "littlefs", 0, NULL); + if (ret < 0) + { + ret = nx_mount("/dev/fmc", "/mnt/fmc", "littlefs", 0, + "forceformat"); + if (ret < 0) + { + ferr("ERROR: Failed to mount the FS volume: %d\n", ret); + return ret; + } + } + + syslog(LOG_INFO, "INFO: LittleFS volume /mnt/fmc mount " + "on chip flash success: %d\n", ret); +# endif +# endif + +# ifdef HAVE_GD25 + + ret = gd32_gd25_automount(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the NXFFS \ + volume on spi flash: %d\n", ret); + } + +# endif + +# ifdef HAVE_AT24 + + ret = gd32_at24_wr_test(AT24_MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: I2C EEPROM write and read test fail: \ + %d\n", ret); + } + +# endif + +#endif /* CONFIG_FS_NXFFS */ + +#ifdef CONFIG_DEV_GPIO + /* Register the GPIO driver */ + + ret = gd32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS +#ifdef CONFIG_INPUT_BUTTONS_LOWER + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + return ret; + } +#else + /* Enable BUTTON support for some other purpose */ + + board_button_initialize(); +#endif /* CONFIG_INPUT_BUTTONS_LOWER */ +#endif /* CONFIG_INPUT_BUTTONS */ + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", + ret); + } +#endif + + /* Configure SDIO chip selects */ + +#ifdef CONFIG_ARCH_HAVE_SDIO + ret = gd32_sdio_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: gd32_sdio_initialize() failed: %d\n", ret); + return ret; + } + + /* Mount the file system at /mnt/sd */ + + ret = nx_mount("/dev/mmcsd0", "/mnt/sd", "vfat", 0, NULL); + if (ret < 0) + { + ret = nx_mount("/dev/mmcsd0", "/mnt/sd", "vfat", 0, + "forceformat"); + if (ret < 0) + { + ferr("ERROR: Failed to mount the SD card: %d\n", ret); + return ret; + } + } + + syslog(LOG_INFO, "INFO: FAT volume /mnt/sd mount " + "sd card success: %d\n", ret); +#endif return ret; } diff --git a/boards/arm/gd32f4/gd32f470ik-eval/scripts/Make.defs b/boards/arm/gd32f4/gd32f470ik-eval/scripts/Make.defs index 068515ee40c88..f0d61cb1d0b9b 100644 --- a/boards/arm/gd32f4/gd32f470ik-eval/scripts/Make.defs +++ b/boards/arm/gd32f4/gd32f470ik-eval/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/gd32f4/gd32f470zk-eval/scripts/Make.defs +# boards/arm/gd32f4/gd32f470ik-eval/scripts/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm/gd32f4/gd32f470ik-eval/src/Makefile b/boards/arm/gd32f4/gd32f470ik-eval/src/Makefile index 0d28f2554536a..66663ed05607e 100644 --- a/boards/arm/gd32f4/gd32f470ik-eval/src/Makefile +++ b/boards/arm/gd32f4/gd32f470ik-eval/src/Makefile @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/gd32f4/gd32f470zk-eval/src/Make.defs +# boards/arm/gd32f4/gd32f470ik-eval/src/Makefile # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with @@ -22,15 +22,16 @@ include $(TOPDIR)/Make.defs CSRCS = gd32f4xx_boot.c -ifeq ($(CONFIG_BOARDCTL),y) -CSRCS += gd32f4xx_appinit.c -endif # ifeq ($(CONFIG_BOARDCTL),y) -# CSRCS += gd32f4xx_appinit.c gd32f4xx_bringup.c -# else ifeq ($(CONFIG_BOARD_LATE_INITIALIZE),y) -# CSRCS += gd32f4xx_bringup.c +# CSRCS += gd32f4xx_appinit.c # endif +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += gd32f4xx_appinit.c gd32f4xx_bringup.c +else ifeq ($(CONFIG_BOARD_LATE_INITIALIZE),y) +CSRCS += gd32f4xx_bringup.c +endif + ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += gd32f4xx_autoleds.c else diff --git a/boards/arm/gd32f4/gd32f470ik-eval/src/gd32f470i_eval.h b/boards/arm/gd32f4/gd32f470ik-eval/src/gd32f470i_eval.h index b6cd49c95738c..bb57a0795332e 100644 --- a/boards/arm/gd32f4/gd32f470ik-eval/src/gd32f470i_eval.h +++ b/boards/arm/gd32f4/gd32f470ik-eval/src/gd32f470i_eval.h @@ -180,6 +180,26 @@ #ifndef __ASSEMBLY__ +/**************************************************************************** + * Name: gd32_bringup + * + * Description: + * Perform architecture specific initialization + * + * CONFIG_BOARDCTL=y: + * If CONFIG_NSH_ARCHINITIALIZE=y: + * Called from the NSH library (or other application) + * Otherwise, assumed to be called from some other application. + * + * Otherwise CONFIG_BOARD_LATE_INITIALIZE=y: + * Called from board_late_initialize(). + * + * Otherwise, bad news: Never called + * + ****************************************************************************/ + +int gd32_bringup(void); + /**************************************************************************** * Name: gd32_spidev_initialize * diff --git a/boards/arm/gd32f4/gd32f470ik-eval/src/gd32f4xx_appinit.c b/boards/arm/gd32f4/gd32f470ik-eval/src/gd32f4xx_appinit.c index bc3f216c4c006..941078f24e59f 100644 --- a/boards/arm/gd32f4/gd32f470ik-eval/src/gd32f4xx_appinit.c +++ b/boards/arm/gd32f4/gd32f470ik-eval/src/gd32f4xx_appinit.c @@ -24,24 +24,14 @@ #include -#include -#include +#include +#include #include +#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_GD32F4_ROMFS -#include "gd32f4xx_romfs.h" -#endif +#include +#include "gd32f4xx.h" #include "gd32f470i_eval.h" /**************************************************************************** @@ -75,192 +65,7 @@ int board_app_initialize(uintptr_t arg) { - int ret; - static bool initialized = false; - - /* Have we already initialized? */ - - if (!initialized) - { -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, GD32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", - GD32_PROCFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_GD32F4_ROMFS - /* Mount the romfs partition */ - - ret = gd32_romfs_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_GD32F4_ROMFS_MOUNTPOINT, ret); - } -#endif - -#ifndef CONFIG_DISABLE_MOUNTPOINT - -# ifdef CONFIG_GD32F4_PROGMEM - - /* Create an instance of the GD32F4 FLASH program memory - * device driver - */ - - struct mtd_dev_s *mtd = progmem_initialize(); - if (!mtd) - { - syslog(LOG_ERR, "ERROR: progmem_initialize failed\n"); - } - -# if defined(CONFIG_FS_NXFFS) - /* Initialize to provide NXFFS on the MTD interface */ - - ret = nxffs_initialize(mtd); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: NXFFS initialization failed: %d\n", - ret); - } - - /* Mount the file system */ - - ret = nx_mount(NULL, CONFIG_GD32F4_NXFFS_MOUNTPT, "nxffs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount the NXFFS volume: %d\n", - ret); - } -# elif defined(CONFIG_FS_LITTLEFS) - /* Initialize to provide LittleFS on the MTD interface */ - - ret = register_mtddriver("/dev/fmc", mtd, 0755, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); - return ret; - } - - /* Mount the file system at /mnt/fmc */ - - ret = nx_mount("/dev/fmc", "/mnt/fmc", "littlefs", 0, NULL); - if (ret < 0) - { - ret = nx_mount("/dev/fmc", "/mnt/fmc", "littlefs", 0, - "forceformat"); - if (ret < 0) - { - ferr("ERROR: Failed to mount the FS volume: %d\n", ret); - return ret; - } - } - - syslog(LOG_INFO, "INFO: LittleFS volume /mnt/fmc mount " \ - "on chip flash success: %d\n", ret); -# endif -# endif - -# ifdef HAVE_GD25 - - ret = gd32_gd25_automount(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount the LittleFS \ - volume on spi flash: %d\n", ret); - } - -# endif - -# ifdef HAVE_AT24 - - ret = gd32_at24_wr_test(AT24_MINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: I2C EEPROM write and read test fail: \ - %d\n", ret); - } - -# endif - -#endif /* CONFIG_FS_NXFFS */ - -#ifdef CONFIG_DEV_GPIO - /* Register the GPIO driver */ - - ret = gd32_gpio_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS -#ifdef CONFIG_INPUT_BUTTONS_LOWER - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - return ret; - } -#else - /* Enable BUTTON support for some other purpose */ - - board_button_initialize(); -#endif /* CONFIG_INPUT_BUTTONS_LOWER */ -#endif /* CONFIG_INPUT_BUTTONS */ - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", - ret); - } -#endif - - /* Configure SDIO chip selects */ - -#ifdef CONFIG_ARCH_HAVE_SDIO - ret = gd32_sdio_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: gd32_sdio_initialize() failed: %d\n", ret); - return ret; - } - - /* Mount the file system at /mnt/sd */ - - ret = nx_mount("/dev/mmcsd0", "/mnt/sd", "vfat", 0, NULL); - if (ret < 0) - { - ret = nx_mount("/dev/mmcsd0", "/mnt/sd", "vfat", 0, - "forceformat"); - if (ret < 0) - { - ferr("ERROR: Failed to mount the SD card: %d\n", ret); - return ret; - } - } - - syslog(LOG_INFO, "INFO: FAT volume /mnt/sd mount " \ - "sd card success: %d\n", ret); -#endif - - /* Now we are initialized */ - - initialized = true; - } + /* Perform board initialization here */ - UNUSED(ret); - return OK; + return gd32_bringup(); } diff --git a/boards/arm/gd32f4/gd32f470ik-eval/src/gd32f4xx_boot.c b/boards/arm/gd32f4/gd32f470ik-eval/src/gd32f4xx_boot.c index 6500db7179ac9..c89990a51e5d5 100644 --- a/boards/arm/gd32f4/gd32f470ik-eval/src/gd32f4xx_boot.c +++ b/boards/arm/gd32f4/gd32f470ik-eval/src/gd32f4xx_boot.c @@ -78,13 +78,8 @@ void gd32_boardinitialize(void) #ifdef CONFIG_BOARD_LATE_INITIALIZE void board_late_initialize(void) { -#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_BOARDCTL) - /* Perform NSH initialization here instead of from the NSH. This - * alternative NSH initialization is necessary when NSH is ran in - * user-space but the initialization function must run in kernel space. - */ + /* Perform board-specific initialization */ - board_app_initialize(0); -#endif + gd32_bringup(); } #endif diff --git a/boards/arm/gd32f4/gd32f470ik-eval/src/gd32f4xx_bringup.c b/boards/arm/gd32f4/gd32f470ik-eval/src/gd32f4xx_bringup.c index 79e93e5b80762..9f20a058ac492 100644 --- a/boards/arm/gd32f4/gd32f470ik-eval/src/gd32f4xx_bringup.c +++ b/boards/arm/gd32f4/gd32f470ik-eval/src/gd32f4xx_bringup.c @@ -35,10 +35,23 @@ #include #include #include -#include #include #include +#include "gd32f4xx.h" + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_GD32F4_ROMFS +#include "gd32f4xx_romfs.h" +#endif + #include "gd32f470i_eval.h" /**************************************************************************** @@ -180,5 +193,167 @@ int gd32_bringup(void) } #endif +#ifdef CONFIG_GD32F4_ROMFS + /* Mount the romfs partition */ + + ret = gd32_romfs_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", + CONFIG_GD32F4_ROMFS_MOUNTPOINT, ret); + } +#endif + +#ifndef CONFIG_DISABLE_MOUNTPOINT + +# ifdef CONFIG_GD32F4_PROGMEM + + /* Create an instance of the GD32F4 FLASH program memory + * device driver + */ + + struct mtd_dev_s *mtd = progmem_initialize(); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: progmem_initialize failed\n"); + } + +# if defined(CONFIG_FS_NXFFS) + /* Initialize to provide NXFFS on the MTD interface */ + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: NXFFS initialization failed: %d\n", + ret); + } + + /* Mount the file system */ + + ret = nx_mount(NULL, CONFIG_GD32F4_NXFFS_MOUNTPT, "nxffs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the NXFFS volume: %d\n", + ret); + } +# elif defined(CONFIG_FS_LITTLEFS) + /* Initialize to provide LittleFS on the MTD interface */ + + ret = register_mtddriver("/dev/fmc", mtd, 0755, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); + return ret; + } + + /* Mount the file system at /mnt/fmc */ + + ret = nx_mount("/dev/fmc", "/mnt/fmc", "littlefs", 0, NULL); + if (ret < 0) + { + ret = nx_mount("/dev/fmc", "/mnt/fmc", "littlefs", 0, + "forceformat"); + if (ret < 0) + { + ferr("ERROR: Failed to mount the FS volume: %d\n", ret); + return ret; + } + } + + syslog(LOG_INFO, "INFO: LittleFS volume /mnt/fmc mount " + "on chip flash success: %d\n", ret); +# endif +# endif + +# ifdef HAVE_GD25 + + ret = gd32_gd25_automount(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the NXFFS \ + volume on spi flash: %d\n", ret); + } + +# endif + +# ifdef HAVE_AT24 + + ret = gd32_at24_wr_test(AT24_MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: I2C EEPROM write and read test fail: \ + %d\n", ret); + } + +# endif + +#endif /* CONFIG_FS_NXFFS */ + +#ifdef CONFIG_DEV_GPIO + /* Register the GPIO driver */ + + ret = gd32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS +#ifdef CONFIG_INPUT_BUTTONS_LOWER + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + return ret; + } +#else + /* Enable BUTTON support for some other purpose */ + + board_button_initialize(); +#endif /* CONFIG_INPUT_BUTTONS_LOWER */ +#endif /* CONFIG_INPUT_BUTTONS */ + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", + ret); + } +#endif + + /* Configure SDIO chip selects */ + +#ifdef CONFIG_ARCH_HAVE_SDIO + ret = gd32_sdio_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: gd32_sdio_initialize() failed: %d\n", ret); + return ret; + } + + /* Mount the file system at /mnt/sd */ + + ret = nx_mount("/dev/mmcsd0", "/mnt/sd", "vfat", 0, NULL); + if (ret < 0) + { + ret = nx_mount("/dev/mmcsd0", "/mnt/sd", "vfat", 0, + "forceformat"); + if (ret < 0) + { + ferr("ERROR: Failed to mount the SD card: %d\n", ret); + return ret; + } + } + + syslog(LOG_INFO, "INFO: FAT volume /mnt/sd mount " + "sd card success: %d\n", ret); +#endif return ret; } diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/Kconfig b/boards/arm/gd32f4/gd32f470zk-aiotbox/Kconfig new file mode 100644 index 0000000000000..0b2870d2ba4af --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/Kconfig @@ -0,0 +1,143 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_GD32F470ZK_AIOTBOX + +choice + prompt "Select Console wiring." + default GD32F470ZK_AIOTBOX_CONSOLE_BOARD + ---help--- + Select where you will connect the console. + + Virtual COM Port: + + Advantage: Use the ST-Link as a console. No Extra wiring + needed. + + Disadvantage: Not the best choice for initial bring up. + + BOARD USART Connector: + + Advantage: You have a shield so it is easy. + + Disadvantage: You loose the use of the + other functions on PA9, PA10 + + GD32F470ZK_AIOTBOX + USART0 GPIO + -- ----- --------- ---- + RX USART0_RX PA10 + TX USART0_TX PA9 + -- ----- --------- --- + +config GD32F470ZK_AIOTBOX_CONSOLE_BOARD + bool "Aiotbox Com Connector" + select GD32_USART0 + select USART0_SERIALDRIVER + +config GD32F470ZK_AIOTBOX_CONSOLE_VIRTUAL + bool "Virtual ComPort" + select GD32_USART3 + select USART3_SERIALDRIVER + +config GD32F470ZK_AIOTBOX_CONSOLE_NONE + bool "No Serial Console" + +endchoice # "Select Console wiring" + + +choice + prompt "GD32F470Z MCU Crystal Selected" + default GD32F470Z_BOARD_USE_HXTAL_AIOTBOX + +config GD32F470Z_BOARD_USE_HXTAL_AIOTBOX + bool "Use Hxtal as clock source" + # select GD32F470Z_BOARD_HXTAL_VALUE + +config GD32F470Z_BOARD_USE_IRC16_AIOTBOX + bool "Use IRC16M as clock source" + +endchoice # CPU Frequency + +config GD32F470Z_BOARD_HXTAL_VALUE + int "GD32F470Z Eval Board Hxtal Value" + default 25000000 + depends on GD32F470Z_BOARD_USE_HXTAL + ---help--- + GD32F470Z Eval Board Hxtal Value, default is 25MHz. + +choice + prompt "GD32F470 MCU System Frequency" + default GD32F470_200MHZ_AIOTBOX + +config GD32F470_240MHZ_AIOTBOX + bool "240 MHz" + +config GD32F470_200MHZ_AIOTBOX + bool "200 MHz" + +config GD32F470_168MHZ_AIOTBOX + bool "168 MHz" + +config GD32F470_120MHZ_AIOTBOX + bool "120 MHz" + +endchoice # CPU Frequency + + +config GD32F470ZK_AIOTBOX_GD25_BLOCKMOUNT + bool "GD25 serial FLASH auto-mount" + default n + depends on GD32F4_SPI5 && MTD_GD25 + ---help--- + Automatically initialize the GD25 SPI FLASH driver when NSH starts. + +choice + prompt "GD25 SPI FLASH configuration" + default GD32F470ZK_AIOTBOX_GD25_NXFFS + depends on GD32F470ZK_AIOTBOX_GD25_BLOCKMOUNT + +config GD32F470ZK_AIOTBOX_GD25_FTL + bool "Create GD25 SPI FLASH block driver" + ---help--- + Create the MTD driver for the GD25 and "wrap" the GD25 as a standard + block driver that could then, for example, be mounted using FAT or + any other file system. Any file system may be used, but there will + be no wear-leveling. + +config GD32F470ZK_AIOTBOX_GD25_NXFFS + bool "Create GD25 serial FLASH NXFFS file system" + depends on FS_NXFFS + ---help--- + Create the MTD driver for the GD25 and mount the GD25 device as + a wear-leveling, NuttX FLASH file system (NXFFS). The downside of + NXFFS is that it can be very slow. + +config GD32F470ZK_AIOTBOX_GD25_LITTLEFS + bool "Create GD25 serial FLASH LFS file system" + depends on FS_LITTLEFS + ---help--- + Create the MTD driver for the GD25 and mount the GD25 device as + a wear-leveling, LittleFS FLASH file system (LFS). + +endchoice # GD25 serial FLASH configuration + +config GD32F470ZK_AIOTBOX_AT24_TEST + bool "I2C0 EEPROM AT2402 write and read test" + default n + depends on NSH_ARCHINIT && GD32F4_I2C0 && MTD_AT24XX + ---help--- + Automatically initialize and test the AT24 I2C EEPROM driver when + NSH starts. After test the I2C0 will be released. + +config AT24XX_MTD_BLOCKSIZE + int "AT24xx MTD block size" + default 8 + depends on GD32F470ZK_AIOTBOX_AT24_TEST + ---help--- + The block size must be an even multiple of the pages. + The page size of AT2402 on the board is 8 Byte. + +endif # ARCH_BOARD_GD32F470ZK_AIOTBOX diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/configs/aiotboxnsh/defconfig b/boards/arm/gd32f4/gd32f470zk-aiotbox/configs/aiotboxnsh/defconfig new file mode 100644 index 0000000000000..2c4654e88508d --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/configs/aiotboxnsh/defconfig @@ -0,0 +1,61 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="gd32f470zk-aiotbox" +CONFIG_ARCH_BOARD_GD32F470ZK_AIOTBOX=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="gd32f4" +CONFIG_ARCH_CHIP_GD32F470ZK=y +CONFIG_ARCH_CHIP_GD32F4=y +CONFIG_ARCH_INTERRUPTSTACK=256 +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_CUSTOMOPT=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_IRQ=y +CONFIG_DEBUG_LEDS=y +CONFIG_DEBUG_OPTLEVEL="-O0" +CONFIG_DEBUG_SCHED=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_GD32F4_DISABLE_IDLE_SLEEP_DURING_DEBUG=y +CONFIG_GD32F4_FLASH_CONFIG_K=y +CONFIG_GD32F4_I2C0=y +CONFIG_GD32F4_I2C1=y +CONFIG_GD32F4_SPI4=y +CONFIG_GD32F4_UART6=y +CONFIG_GD32F4_UART7=y +CONFIG_GD32F4_USART1=y +CONFIG_GD32F4_USART2=y +CONFIG_GD32F4_USART5=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2C_POLLED=y +CONFIG_I2C_RESET=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART0_SERIAL_CONSOLE=y diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/include/board.h b/boards/arm/gd32f4/gd32f470zk-aiotbox/include/board.h new file mode 100644 index 0000000000000..c2821e9657e7e --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/include/board.h @@ -0,0 +1,460 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-aiotbox/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_GD32F470ZK_AIOTBOX_INCLUDE_BOARD_H +#define __BOARDS_ARM_GD32F470ZK_AIOTBOX_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +#define GD32_BOARD_SYSCLK_PLL_HXTAL + +/* Do not include GD32F4 header files here */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The GD32F470ZK-EVAL board features a single 25MHz crystal. + * + * This is the default configuration: + * System clock source : PLL (HXTAL) + * SYSCLK(Hz) : 200000000 Determined by PLL config + * HCLK(Hz) : 200000000 (GD32_SYSCLK_FREQUENCY) + * AHB Prescaler : 1 (GD32_RCU_CFG0_AHB_PSC) + * APB2 Prescaler : 2 (GD32_RCU_CFG0_APB2_PSC) + * APB1 Prescaler : 4 (GD32_RCU_CFG0_APB1_PSC) + * HXTAL value(Hz) : 25000000 (GD32_BOARD_XTAL) + * PLLM : 25 (GD32_PLL_PLLM) + * PLLN : 400 (RCU_PLL_PLLN) + * PLLP : 2 (GD32_PLL_PLLP) + * PLLQ : 7 (GD32_PLL_PLLQ) + */ + +/* IRC16M - 16 MHz RC factory-trimmed + * IRC32K - 32 KHz RC + * HXTAL - On-board crystal frequency is 25MHz + * LXTAL - 32.768 kHz + */ + +#ifndef CONFIG_GD32F470_BOARD_HXTAL_VALUE +# define GD32_BOARD_HXTAL 25000000ul +#else +# define GD32_BOARD_HXTAL CONFIG_GD32F470_BOARD_HXTAL_VALUE +#endif + +#define GD32_IRC16M_VALUE 16000000ul +#define GD32_IRC32K_VALUE 32000u +#define GD32_HXTAL_VALUE GD32_BOARD_HXTAL +#define GD32_LXTAL_VALUE 32768u + +#if defined(CONFIG_GD32F470_200MHZ_AIOTBOX) + +/* Main PLL Configuration. + * + * PLL source is HXTAL + * PLL_VCO = (GD32_HXTAL_VALUE / PLLM) * PLLN + * = (25,000,000 / 25) * 400 + * = 400,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 400,000,000 / 2 = 168,000,000 + * USB, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define GD32_PLL_PLLPSC RCU_PLL_PLLPSC(25) +#define GD32_PLL_PLLN RCU_PLL_PLLN(400) +#define GD32_PLL_PLLP RCU_PLL_PLLP(2) +#define GD32_PLL_PLLQ RCU_PLL_PLLQ(7) + +#define GD32_SYSCLK_FREQUENCY 200000000ul + +#elif defined(CONFIG_GD32F470_168MHZ_AIOTBOX) + +/* Main PLL Configuration. + * + * PLL source is HXTAL + * PLL_VCO = (GD32_HXTAL_VALUE / PLLM) * PLLN + * = (25,000,000 / 25) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define GD32_PLL_PLLPSC RCU_PLL_PLLPSC(25) +#define GD32_PLL_PLLN RCU_PLL_PLLN(336) +#define GD32_PLL_PLLP RCU_PLL_PLLP(2) +#define GD32_PLL_PLLQ RCU_PLL_PLLQ(7) + +#define GD32_SYSCLK_FREQUENCY 168000000ul + +#elif defined(CONFIG_GD32F470_240MHZ_AIOTBOX) + +/* Main PLL Configuration. + * + * PLL source is HXTAL + * PLL_VCO = (GD32_HXTAL_VALUE / PLLM) * PLLN + * = (25,000,000 / 25) * 336 + * = 336,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 336,000,000 / 2 = 168,000,000 + * USB, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 48,000,000 + */ + +#define GD32_PLL_PLLPSC RCU_PLL_PLLPSC(25) +#define GD32_PLL_PLLN RCU_PLL_PLLN(480) +#define GD32_PLL_PLLP RCU_PLL_PLLP(2) +#define GD32_PLL_PLLQ RCU_PLL_PLLQ(7) + +#define GD32_SYSCLK_FREQUENCY 240000000ul + +#endif + +/* AHB clock (HCLK) is SYSCLK */ + +#define GD32_RCU_CFG0_AHB_PSC RCU_CFG0_AHBPSC_CKSYS_DIV1 /* HCLK = SYSCLK / 1 */ +#define GD32_HCLK_FREQUENCY GD32_SYSCLK_FREQUENCY + +/* APB2 clock (PCLK2) is HCLK/2 */ + +#define GD32_RCU_CFG0_APB2_PSC RCU_CFG0_APB2PSC_CKAHB_DIV2 /* PCLK2 = HCLK / 2 */ +#define GD32_PCLK2_FREQUENCY (GD32_HCLK_FREQUENCY/2) + +/* APB1 clock (PCLK1) is HCLK/4 */ + +#define GD32_RCU_CFG0_APB1_PSC RCU_CFG0_APB1PSC_CKAHB_DIV4 /* PCLK1 = HCLK / 4 */ +#define GD32_PCLK1_FREQUENCY (GD32_HCLK_FREQUENCY / 4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define GD32_APB1_TIMER2_CLKIN (2*GD32_PCLK1_FREQUENCY) +#define GD32_APB1_TIMER3_CLKIN (2*GD32_PCLK1_FREQUENCY) +#define GD32_APB1_TIMER4_CLKIN (2*GD32_PCLK1_FREQUENCY) +#define GD32_APB1_TIMER5_CLKIN (2*GD32_PCLK1_FREQUENCY) +#define GD32_APB1_TIMER6_CLKIN (2*GD32_PCLK1_FREQUENCY) +#define GD32_APB1_TIMER7_CLKIN (2*GD32_PCLK1_FREQUENCY) +#define GD32_APB1_TIMER12_CLKIN (2*GD32_PCLK1_FREQUENCY) +#define GD32_APB1_TIMER13_CLKIN (2*GD32_PCLK1_FREQUENCY) +#define GD32_APB1_TIMER14_CLKIN (2*GD32_PCLK1_FREQUENCY) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define GD32_APB2_TIMER1_CLKIN (2*GD32_PCLK2_FREQUENCY) +#define GD32_APB2_TIMER8_CLKIN (2*GD32_PCLK2_FREQUENCY) +#define GD32_APB2_TIMER9_CLKIN (2*GD32_PCLK2_FREQUENCY) +#define GD32_APB2_TIMER10_CLKIN (2*GD32_PCLK2_FREQUENCY) +#define GD32_APB2_TIMER11_CLKIN (2*GD32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIMER1,8 are on APB2, others on APB1 + */ + +#define BOARD_TIMER1_FREQUENCY GD32_HCLK_FREQUENCY +#define BOARD_TIMER2_FREQUENCY (GD32_HCLK_FREQUENCY/2) +#define BOARD_TIMER3_FREQUENCY (GD32_HCLK_FREQUENCY/2) +#define BOARD_TIMER4_FREQUENCY (GD32_HCLK_FREQUENCY/2) +#define BOARD_TIMER5_FREQUENCY (GD32_HCLK_FREQUENCY/2) +#define BOARD_TIMER6_FREQUENCY (GD32_HCLK_FREQUENCY/2) +#define BOARD_TIMER7_FREQUENCY (GD32_HCLK_FREQUENCY/2) +#define BOARD_TIMER8_FREQUENCY GD32_HCLK_FREQUENCY + +/* LED definitions **********************************************************/ + +/* The GD32F470ZK_EVAL board has board has three LEDs. The LED1, LED2 and + * LED3 are controlled by GPIO. LED1 is connected to PD4, LED2 is connected + * to PD5, LED3 is connected to PG3 + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values */ + +typedef enum +{ + BOARD_LED1 = 0, + BOARD_LED2 = 1, + BOARD_LED3 = 2, + BOARD_LEDS +} led_typedef_enum; + +/* LED bits */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) + +/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in + * include/board.h and src/gd32f4xx_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * + * + * SYMBOL Meaning LED state + * LED1 LED2 LED3 + * ---------------------- -------------------------- ------ ------ --- + */ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated ON OFF OFF */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF OFF ON */ +#define LED_INIRQ 4 /* In an interrupt ON ON OFF */ +#define LED_SIGNAL 5 /* In a signal handler ON OFF ON */ +#define LED_ASSERTION 6 /* An assertion failed OFF ON ON */ +#define LED_PANIC 7 /* The system has crashed FLASH ON ON */ +#define LED_IDLE 8 /* MCU is is sleep mode OFF FLASH OFF */ + +/* Button definitions *******************************************************/ + +/* The GD32F470Z Eval supports three user buttons: Wakeup, Tamper and + * User key, they are connected to GPIO PA0, PC13, PB14. + * A low value will be sensed when the button is depressed. + */ + +typedef enum +{ + BUTTON_WAKEUP = 0, + BUTTON_TAMPER = 1, + BUTTON_USER = 2, + NUM_BUTTONS +} key_typedef_enum; + +#define BUTTON_WAKEUP_BIT (1 << BUTTON_WAKEUP) +#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER) +#define BUTTON_USER_BIT (1 << BUTTON_USER) + +/* Alternate function pin selections ****************************************/ + +#if defined(CONFIG_GD32F470ZK_AIOTBOX_CONSOLE_BOARD) + +/* USART0: + * + * These configurations assume that you are using a standard RS-232 + * shield with the serial interface with RX on PA10 and TX on PA10: + * + * -------- --------------- + * GD32F470ZK-EVAL + * -- ----- --------- ----- + * RX USART0_RX PA10 + * TX USART0_TX PA9 + * -- ----- --------- ----- + */ + +# define GPIO_USART0_RX GPIO_USART0_RX_1 +# define GPIO_USART0_TX GPIO_USART0_TX_1 + +#if defined(CONFIG_SERIAL_IFLOWCONTROL) && defined(CONFIG_USART0_IFLOWCONTROL) +# define GPIO_USART0_RTS GPIO_USART0_RTS_1 +# endif +#if defined(CONFIG_SERIAL_OFLOWCONTROL) && defined(CONFIG_USART0_OFLOWCONTROL) +# define GPIO_USART0_CTS GPIO_USART0_CTS_1 +# endif +#endif + +#if CONFIG_GD32F4_USART0_TXDMA +# define DMA_CHANNEL_USART0_TX DMA_REQ_USART0_TX +#endif +#if CONFIG_GD32F4_USART0_RXDMA +# define DMA_CHANNEL_USART0_RX DMA_REQ_USART0_RX_1 +#endif + +#if defined(CONFIG_GD32F4_USART_RXDMA) || defined(CONFIG_GD32F4_USART_TXDMA) +# define USART_DMA_INTEN (DMA_CHXCTL_SDEIE | DMA_CHXCTL_TAEIE | DMA_CHXCTL_FTFIE) +#endif + +/* USART3: + * Use USART3 and the USB virtual COM port + */ + +#if defined(GD32F470ZK_AIOTBOX_CONSOLE_VIRTUAL) +# define GPIO_USART3_RX GPIO_USART3_RX_3 +# define GPIO_USART3_TX GPIO_USART3_TX_3 +#endif + +/* USART1 + * + * RX USART1_RX PD6 + * TX USART1_TX PD5 + */ +# define GPIO_USART1_RX GPIO_USART1_RX_2 +# define GPIO_USART1_TX GPIO_USART1_TX_2 + +/* USART2->RS485 + * + * RX USART2_RX PD9 + * TX USART2_TX PD8 + */ +# define GPIO_USART2_RX GPIO_USART2_RX_4 +# define GPIO_USART2_TX GPIO_USART2_TX_3 + +/* USART5 + * + * RX USART5_RX PC7 + * TX USART5_TX PC6 + */ +# define GPIO_USART5_RX GPIO_USART5_RX_2 +# define GPIO_USART5_TX GPIO_USART5_TX_2 + +/* UART6 + * + * RX UART6_RX PE8 + * TX UART6_TX PE7 + */ +# define GPIO_UART6_RX GPIO_UART6_RX_1 +# define GPIO_UART6_TX GPIO_UART6_TX_1 + +/* UART7 + * + * RX UART7_RX PE0 + * TX UART7_TX PE1 + */ + +/* I2C0 gpios: + * + * PB8 I2C0_SCL + * PB9 I2C0_SDA + */ + +#define GPIO_I2C0_SCL GPIO_I2C0_SCL_2 +#define GPIO_I2C0_SDA GPIO_I2C0_SDA_2 + +/* I2C1 gpios: + * + * PF1 I2C0_SCL + * PF0 I2C0_SDA + */ +#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 +#define GPIO_I2C1_SDA GPIO_I2C1_SDA_4 + +/* SPI -> FPC + * + * PF8 SPI4_MISO + * PF9 SPI4_MOSI + * PF7 SPI4_SCK + * PF6 SPI4_CS + */ + +#define GPIO_SPI4_CSPIN (GPIO_CFG_PORT_F | GPIO_PIN6_OUTPUT) +#define GPIO_SPI4_MISO_PIN ((GPIO_SPI4_MISO_3& ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) +#define GPIO_SPI4_MOSI_PIN ((GPIO_SPI4_MOSI_4 & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) +#define GPIO_SPI4_SCK_PIN ((GPIO_SPI4_SCK_3 & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) + +/* SPI flash + * + * PG12 SPI5_MISO + * PG14 SPI5_MOSI + * PG13 SPI5_SCK + * PG9 SPI5_CS + */ + +#define GPIO_SPI5_CSPIN (GPIO_CFG_PORT_G | GPIO_PIN9_OUTPUT) + +#define GPIO_SPI5_MISO_PIN ((GPIO_SPI5_MISO & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) +#define GPIO_SPI5_MOSI_PIN ((GPIO_SPI5_MOSI & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) +#define GPIO_SPI5_SCK_PIN ((GPIO_SPI5_SCK & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) + +#define GPIO_SPI5_IO2_PIN ((GPIO_SPI5_IO2 & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) +#define GPIO_SPI5_IO3_PIN ((GPIO_SPI5_IO3 & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) + +#ifdef CONFIG_GD32F4_SPI0 +# define GPIO_SPI0_CSPIN (GPIO_CFG_PORT_B | GPIO_PIN9_OUTPUT) +# define GPIO_SPI0_MISO_PIN ((GPIO_SPI0_MISO_1 & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) +# define GPIO_SPI0_MOSI_PIN ((GPIO_SPI0_MOSI_1 & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) +# define GPIO_SPI0_SCK_PIN ((GPIO_SPI0_SCK_1 & ~GPIO_CFG_SPEED_MASK) | GPIO_CFG_SPEED_25MHZ) +#endif + +#ifdef CONFIG_GD32F4_SPI0_DMA +# define DMA_CHANNEL_SPI0_TX DMA_REQ_SPI0_TX_1 +# define DMA_CHANNEL_SPI0_RX DMA_REQ_SPI0_RX_1 +#endif + +#ifdef CONFIG_GD32F4_SPI_DMA +# define SPI_DMA_INTEN (DMA_CHXCTL_SDEIE | DMA_CHXCTL_TAEIE | DMA_CHXCTL_FTFIE) +#endif + +/* The GD32 F4 connects to a DP83848 PHY using these pins: + * + * GD32F470Z Eval BOARD DP83848 + * GPIO SIGNAL PIN NAME + * -------- ------------ ------------- + * PB11 RMII_TX_EN TXEN + * PB12 RMII_TXD0 TXD0 + * PB13 RMII_TXD1 TXD1 + * PC4 RMII_RXD0 RXD_0/PHYAD1 + * PC5 RMII_RXD1 RXD_1/PHYAD2 + * PA7 RMII_CRS_DV RX_DV/MII_MODE + * PC1 RMII_MDC MDC + * PA2 RMII_MDIO MDIO + * NRST NRST RESET_N + * PA1 RMII_REF_CLK X1 + * PB15 RMII_INT PWR_DOWN/INT + * + * The PHY address is 1. + */ + +#define GPIO_ENET_RMII_TX_EN GPIO_ENET_RMII_TX_EN_1 +#define GPIO_ENET_RMII_TXD0 GPIO_ENET_RMII_TXD0_1 +#define GPIO_ENET_RMII_TXD1 GPIO_ENET_RMII_TXD1_1 + +#ifdef CONFIG_GD32F4_ENET_PTP + /* Enable pulse-per-second (PPS) output signal */ + +# define GPIO_ENET_PPS_OUT GPIO_ENET_PPS_OUT_1 +#endif + +/* SDIO gpios + * + * PD2 SDIO_CMD + * PC12 SDIO_CLK + * PC8 SDIO_DAT0 + * PC9 SDIO_DAT1 + * PC10 SDIO_DAT2 + * PC11 SDIO_DAT3 + */ + +#define GPIO_SDIO_CMD_PIN GPIO_SDIO_CMD_2 +#define GPIO_SDIO_CLK_PIN GPIO_SDIO_CK_2 +#define GPIO_SDIO_DAT0_PIN GPIO_SDIO_D0_2 +#define GPIO_SDIO_DAT1_PIN GPIO_SDIO_D1_3 +#define GPIO_SDIO_DAT2_PIN GPIO_SDIO_D2_3 +#define GPIO_SDIO_DAT3_PIN GPIO_SDIO_D3 + +#ifdef CONFIG_GD32F4_SDIO_DMA +# define SDIO_DMA_INTEN (DMA_CHXCTL_SDEIE | DMA_CHXCTL_TAEIE | DMA_CHXCTL_FTFIE) +#endif + +#endif /* __BOARDS_ARM_GD32F470ZK_AIOTBOX_INCLUDE_BOARD_H */ diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/Make.defs b/boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/Make.defs new file mode 100644 index 0000000000000..4c8edf0c30b51 --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/Make.defs @@ -0,0 +1,41 @@ +############################################################################ +# boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +EXEEXT = .elf diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/gnu-elf.ld b/boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/gnu-elf.ld new file mode 100644 index 0000000000000..a0895eb3e5f93 --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/gnu-elf.ld @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-eval/scripts/gnu-elf.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +SECTIONS +{ + .text 0x00000000 : + { + _stext = . ; + *(.text) + *(.text.*) + *(.gnu.warning) + *(.stub) + *(.glue_7) + *(.glue_7t) + *(.jcr) + + /* C++ support: The .init and .fini sections contain specific logic + * to manage static constructors and destructors. + */ + + *(.gnu.linkonce.t.*) + *(.init) /* Old ABI */ + *(.fini) /* Old ABI */ + _etext = . ; + } + + .rodata : + { + _srodata = . ; + *(.rodata) + *(.rodata1) + *(.rodata.*) + *(.gnu.linkonce.r*) + _erodata = . ; + } + + .data : + { + _sdata = . ; + *(.data) + *(.data1) + *(.data.*) + *(.gnu.linkonce.d*) + . = ALIGN(4); + _edata = . ; + } + + /* C++ support. For each global and static local C++ object, + * GCC creates a small subroutine to construct the object. Pointers + * to these routines (not the routines themselves) are stored as + * simple, linear arrays in the .ctors section of the object file. + * Similarly, pointers to global/static destructor routines are + * stored in .dtors. + */ + + .ctors : + { + _sctors = . ; + *(.ctors) /* Old ABI: Unallocated */ + *(.init_array) /* New ABI: Allocated */ + _edtors = . ; + } + + .dtors : + { + _sdtors = . ; + *(.dtors) /* Old ABI: Unallocated */ + *(.fini_array) /* New ABI: Allocated */ + _edtors = . ; + } + + .bss : + { + _sbss = . ; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.b*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + } + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/kernel-space.ld b/boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/kernel-space.ld new file mode 100644 index 0000000000000..8377a8e028e80 --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/kernel-space.ld @@ -0,0 +1,98 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-eval/scripts/kernel-space.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + .ARM.extab : { + *(.ARM.extab*) + } > kflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > kflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/ld.script b/boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/ld.script new file mode 100644 index 0000000000000..5061f61d2b7a9 --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/ld.script @@ -0,0 +1,131 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-eval/scripts/ld.script + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The GD32F470ZKT6 has 3072Kb of FLASH beginning at address 0x0800:0000 and + * 256Kb of SRAM. SRAM is split up into four blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of SRAM beginning at address 0x2002:0000 + * 4) 64Kb of TCMSRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 3072K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/memory.ld b/boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/memory.ld new file mode 100644 index 0000000000000..756f9879aed20 --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/memory.ld @@ -0,0 +1,85 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-eval/scripts/memory.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The GD32F470ZKT6 has 3072Kb of FLASH beginning at address 0x0800:0000 and + * 256Kb of SRAM. SRAM is split up into four blocks: + * + * 1) 112KB of SRAM beginning at address 0x2000:0000 + * 2) 16KB of SRAM beginning at address 0x2001:c000 + * 3) 64KB of SRAM beginning at address 0x2002:0000 + * 4) 64KB of TCMSRAM beginning at address 0x1000:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + * + * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of + * FLASH and 4Kb of SRAM. That is an excessive amount for the kernel which + * should fit into 64KB and, of course, can be optimized as needed. Allowing the + * additional does permit addition debug instrumentation to be added to the + * kernel space without overflowing the partition. + * + * Alignment of the user space FLASH partition is also a critical factor: + * The user space FLASH partition will be spanned with a single region of + * size 2**n bytes. The alignment of the user-space region must be the same. + * As a consequence, as the user-space increases in size, the alignment + * requirement also increases. + * + * This alignment requirement means that the largest user space FLASH region + * you can have will be 512KB at it would have to be positioned at + * 0x08800000. If you change this address, don't forget to change the + * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify + * the check in kernel/userspace.c. + * + * For the same reasons, the maximum size of the SRAM mapping is limited to + * 4KB. Both of these alignment limitations could be reduced by using + * multiple regions to map the FLASH/SDRAM range or perhaps with some + * clever use of subregions. + * + * A detailed memory map for the 112KB SRAM region is as follows: + * + * 0x20000 0000: Kernel .data region. Typical size: 0.1KB + * ------- ---- Kernel .bss region. Typical size: 1.8KB + * 0x20000 0800: Kernel IDLE thread stack (approximate). Size is + * determined by CONFIG_IDLETHREAD_STACKSIZE and + * adjustments for alignment. Typical is 1KB. + * ------- ---- Padded to 4KB + * 0x20000 1000: User .data region. Size is variable. + * ------- ---- User .bss region Size is variable. + * 0x20000 2000: Beginning of kernel heap. Size determined by + * CONFIG_MM_KERNEL_HEAPSIZE. + * ------- ---- Beginning of user heap. Can vary with other settings. + * 0x20001 c000: End+1 of CPU RAM + */ + +MEMORY +{ + /* 1024Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K + + /* 112Kb of contiguous SRAM */ + + ksram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K + usram (rwx) : ORIGIN = 0x20001000, LENGTH = 4K + xsram (rwx) : ORIGIN = 0x20002000, LENGTH = 104K +} diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/user-space.ld b/boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/user-space.ld new file mode 100644 index 0000000000000..5005e08f18203 --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/scripts/user-space.ld @@ -0,0 +1,112 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-eval/scripts/user-space.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +/* Make sure that the critical memory management functions are in user-space. + * the user heap memory manager will reside in user-space but be usable both + * by kernel- and user-space code + */ + +EXTERN(umm_initialize) +EXTERN(umm_addregion) + +EXTERN(malloc) +EXTERN(realloc) +EXTERN(zalloc) +EXTERN(free) + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/Makefile b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/Makefile new file mode 100644 index 0000000000000..b3c71590d48cf --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/Makefile @@ -0,0 +1,77 @@ +############################################################################ +# boards/arm/gd32f4/gd32f470zk-aiotbox/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = gd32f4xx_boot.c + +# ifeq ($(CONFIG_BOARDCTL),y) +# CSRCS += gd32f4xx_appinit.c +# endif + +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += gd32f4xx_appinit.c gd32f4xx_bringup.c +else ifeq ($(CONFIG_BOARD_LATE_INITIALIZE),y) +CSRCS += gd32f4xx_bringup.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += gd32f4xx_autoleds.c +else +CSRCS += gd32f4xx_userleds.c +endif + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += gd32f4xx_gpio.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += gd32f4xx_buttons.c +endif + +ifeq ($(CONFIG_SPI),y) +CSRCS += gd32f4xx_spi.c +endif + +ifeq ($(CONFIG_MMCSD),y) +CSRCS += gd32f4xx_sdio.c +endif + +ifeq ($(CONFIG_MTD_GD25),y) +CSRCS += gd32f4xx_gd25.c +endif + +ifeq ($(CONFIG_MTD_AT24XX), y) +CSRCS += gd32f4xx_at24.c +endif + +ifeq ($(CONFIG_BOARDCTL_RESET), y) +CSRCS += gd32f4xx_reset.c +endif + +ifeq ($(CONFIG_ETC_ROMFS), y) +CSRCS += etc_romfs.c +endif + +ifeq ($(CONFIG_I2C), y) +CSRCS += gd32f4xx_i2c.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/etc_romfs.c b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/etc_romfs.c new file mode 100644 index 0000000000000..ff6452f680ede --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/etc_romfs.c @@ -0,0 +1,119 @@ +/*************************************************************************** + * boards/arm/gd32f4/gd32f470zk-aiotbox/src/etc_romfs.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ***************************************************************************/ + +/*************************************************************************** + * Public Data + ***************************************************************************/ + +const unsigned char romfs_img[] = +{ + 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x01, 0x50, + 0x9f, 0x13, 0x82, 0x87, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56, + 0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, + 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, + 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +const unsigned int romfs_img_len = 1024; + +/*************************************************************************** + * Public Functions + ***************************************************************************/ diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f470z_aiotbox.h b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f470z_aiotbox.h new file mode 100644 index 0000000000000..0e45012f5adb6 --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f470z_aiotbox.h @@ -0,0 +1,297 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f470z_aiotbox.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_GD32F4_GD32F470ZK_AIOTBOX_SRC_GD32F470Z_AIOTBOX_H +#define __BOARDS_ARM_GD32F4_GD32F470ZK_AIOTBOX_SRC_GD32F470Z_AIOTBOX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* procfs File System */ + +#ifdef CONFIG_FS_PROCFS +# ifdef CONFIG_NSH_PROC_MOUNTPOINT +# define GD32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT +# else +# define GD32_PROCFS_MOUNTPOINT "/proc" +# endif +#endif + +#ifdef CONFIG_FS_NXFFS +# ifndef CONFIG_GD32F4_NXFFS_MOUNTPT +# define CONFIG_GD32F4_NXFFS_MOUNTPT "/mnt/gd32nxffs" +# endif +#endif + +/* GD32F470ZK GPIO Pin Definitions ******************************************/ + +/* LED + * + * The GD32F470ZK board has three LEDs, LED1, LED2 and LED3, that can be + * controlled by software. + * The following definitions assume the default Solder Bridges are installed. + */ + +#define GPIO_LED1 (GPIO_CFG_PORT_D | GPIO_CFG_OUTPUT_RESET | GPIO_PIN4_OUTPUT) +#define GPIO_LED2 (GPIO_CFG_PORT_D | GPIO_CFG_OUTPUT_RESET | GPIO_PIN5_OUTPUT) +#define GPIO_LED3 (GPIO_CFG_PORT_G | GPIO_CFG_OUTPUT_RESET | GPIO_PIN3_OUTPUT) + +#define LED1 GPIO_LED1 +#define LED2 GPIO_LED2 +#define LED3 GPIO_LED3 + +#define LED_DRIVER_PATH "/dev/userleds" + +/* BUTTONS + * + * The GD32F470Z AIOTBOX board has User, Tamper, and Wakeup key, the are + * connected to GPIO PB14, PC13 and PA0. + * A low value will be sensed when the button is depressed. + * + * Note: + * That the EXTI is included in the definition to enable + * an interrupt on this IO. + */ + +#define GPIO_BTN_USER (GPIO_CFG_PORT_B | GPIO_CFG_EXTI | GPIO_PIN14_INPUT) +#define GPIO_BTN_TAMPER (GPIO_CFG_PORT_C | GPIO_CFG_EXTI | GPIO_PIN13_INPUT) +#define GPIO_BTN_WAKEUP (GPIO_CFG_PORT_A | GPIO_CFG_EXTI | GPIO_PIN0_INPUT) + +/* SPI Flash ****************************************************************/ + +/* SPI FLASH (GD25Q40) + * + * PG12 SPI5_MISO + * PG14 SPI5_MOSI + * PG13 SPI5_SCK + * + * PG9 SPI5_CS + */ + +#define GPIO_SPI5_CS (GPIO_CFG_PORT_G | GPIO_PIN9_OUTPUT) +#define SPI_FLASH_CSNUM 5 + +#define HAVE_GD25 1 + +#if !defined(CONFIG_MTD_GD25) || !defined(CONFIG_GD32F4_SPI5) +# undef HAVE_GD25 +#endif + +/* Can't support AT24 features if mountpoints are disabled or if we were not + * asked to mount the AT25 part + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || \ + !defined(CONFIG_GD32F470ZK_AIOTBOX_GD25_BLOCKMOUNT) +# undef HAVE_GD25 +#endif + +#define HAVE_AT24 1 + +/* AT24 Serial EEPROM + * + * A AT24C02C Serial EEPPROM was used for tested I2C0. + */ + +#define AT24_BUS 0 +#define AT24_MINOR 0 + +#if !defined(CONFIG_MTD_AT24XX) || !defined(CONFIG_GD32F4_I2C0) +# undef HAVE_AT24 +#endif + +/* Can't support AT24 features if mountpoints are disabled or if we were not + * asked to mount the AT25 part + */ + +#ifndef CONFIG_GD32F470ZK_AIOTBOX_AT24_TEST +# undef HAVE_AT24 +#endif + +/* GPIO pins used by the GPIO Subsystem */ + +#define BOARD_NGPIOIN 1 /* Amount of GPIO Input pins */ +#define BOARD_NGPIOOUT 1 /* Amount of GPIO Output pins */ +#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ + +#define GPIO_IN1 (GPIO_CFG_MODE_INPUT | GPIO_CFG_PUPD_NONE | GPIO_CFG_PORT_B | GPIO_CFG_PIN_0) +#define GPIO_OUT1 (GPIO_CFG_MODE_OUTPUT | GPIO_CFG_OUTPUT_SET | GPIO_CFG_SPEED_50MHZ | \ + GPIO_CFG_PORT_B | GPIO_CFG_PIN_1) +#define GPIO_INT1 (GPIO_CFG_MODE_INPUT | GPIO_CFG_PUPD_NONE | GPIO_CFG_PORT_B | GPIO_CFG_PIN_2) + +/* Can't support MMC/SD features if mountpoints are disabled or if SDIO + * support is not enabled. + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_GD32_SDIO) +# undef HAVE_SDIO +#endif + +#define SDIO_MINOR 0 /* Any minor number, default 0 */ +#define SDIO_SLOTNO 0 /* Only one slot */ + +#ifdef HAVE_SDIO +# if !defined(CONFIG_NSH_MMCSDSLOTNO) +# define CONFIG_NSH_MMCSDSLOTNO SDIO_SLOTNO +# elif CONFIG_NSH_MMCSDSLOTNO != 0 +# warning "Only one MMC/SD slot, slot 0" +# undef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO SDIO_SLOTNO +# endif + +# if defined(CONFIG_NSH_MMCSDMINOR) +# define SDIO_MINOR CONFIG_NSH_MMCSDMINOR +# else +# define SDIO_MINOR 0 +# endif +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Name: gd32_bringup + * + * Description: + * Perform architecture specific initialization + * + * CONFIG_BOARDCTL=y: + * If CONFIG_NSH_ARCHINITIALIZE=y: + * Called from the NSH library (or other application) + * Otherwise, assumed to be called from some other application. + * + * Otherwise CONFIG_BOARD_LATE_INITIALIZE=y: + * Called from board_late_initialize(). + * + * Otherwise, bad news: Never called + * + ****************************************************************************/ + +int gd32_bringup(void); + +/**************************************************************************** + * Name: gd32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the GD32F470Z + * AIOTBOX board. + * + ****************************************************************************/ + +#if defined(CONFIG_SPI) +void gd32_spidev_initialize(void); +#endif + +/**************************************************************************** + * Name: gd32_i2c_initialize + * + * Description: + * Called to configure i2c chip initialize for the GD32F470Z + * AIOTBOX board. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) +void gd32_i2c_initialize(void); +#endif + +/**************************************************************************** + * Name: gd32_gd25_automount + * + * Description: + * Initialize, configure, and mount the GD25 SPI FLASH. The FLASH will + * be mounted at /dev/gd25. + * + ****************************************************************************/ + +#ifdef HAVE_GD25 +int gd32_gd25_automount(int minor); +#endif + +/**************************************************************************** + * Name: gd32_at24_wr_test + * + * Description: + * Write and read the AT24 serial EEPROM test. + * + ****************************************************************************/ + +#ifdef HAVE_AT24 +int gd32_at24_wr_test(int minor); +#endif + +/**************************************************************************** + * Name: gd32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +#ifdef CONFIG_DEV_GPIO +int gd32_gpio_initialize(void); +#endif + +/**************************************************************************** + * Name: gd32_dma_alloc_init + * + * Description: + * Called to create a FAT DMA allocator + * + * Returned Value: + * 0 on success or -ENOMEM + * + ****************************************************************************/ + +void gd32_dma_alloc_init(void); + +#if defined (CONFIG_FAT_DMAMEMORY) +int gd32_dma_alloc_init(void); +#endif + +/**************************************************************************** + * Name: gd32_sdio_initialize + * + * Description: + * Called at application startup time to initialize the SCMMC + * functionality. + * + ****************************************************************************/ + +#ifdef CONFIG_MMCSD +int gd32_sdio_initialize(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_GD32F4_GD32F470ZK_AIOTBOX_SRC_GD32F470Z_AIOTBOX_H */ diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_appinit.c b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_appinit.c new file mode 100644 index 0000000000000..5e18d067e3cf2 --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_appinit.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "gd32f4xx.h" +#include "gd32f470z_aiotbox.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + /* Perform board initialization here */ + + return gd32_bringup(); +} diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_at24.c b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_at24.c new file mode 100644 index 0000000000000..1e98c610a0eb0 --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_at24.c @@ -0,0 +1,155 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_at24.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "gd32f4xx.h" +#include "gd32f470z_aiotbox.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_at24_wr_test + * + * Description: + * Write and read the AT24 serial EEPROM test. + * + ****************************************************************************/ + +#ifdef HAVE_AT24 + +#define BUFFSIZE 16 +#define START_BLOCK 0 + +#if BUFFSIZE>=CONFIG_AT24XX_MTD_BLOCKSIZE +# define NBLOCK (BUFFSIZE/CONFIG_AT24XX_MTD_BLOCKSIZE) +#else +# error "BUFFSIZE should bigger than CONFIG_AT24XX_MTD_BLOCKSIZE" +#endif + +const uint8_t write_buf[BUFFSIZE] = +{ + 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, + 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf +}; + +int gd32_at24_wr_test(int minor) +{ + struct i2c_master_s *i2c; + struct mtd_dev_s *at24; + static bool initialized = false; + int ret; + ssize_t nblocks; + uint8_t *read_buf; + + /* Have we already initialized? */ + + if (!initialized) + { + /* No.. Get the I2C port driver */ + + finfo("Initialize TWI%d\n", AT24_BUS); + i2c = gd32_i2cbus_initialize(AT24_BUS); + if (!i2c) + { + ferr("ERROR: Failed to initialize TWI%d\n", AT24_BUS); + return -ENODEV; + } + + /* Now bind the I2C interface to the AT24 I2C EEPROM driver */ + + finfo("Bind the AT24 EEPROM driver to TWI%d\n", AT24_BUS); + at24 = at24c_initialize(i2c); + if (!at24) + { + ferr("ERROR: Failed to bind TWI%d to the AT24 EEPROM driver\n", + AT24_BUS); + return -ENODEV; + } + + /* Now we are initializeed */ + + initialized = true; + } + + /* Write start block is START_BLOCK, number of block is 2 */ + + nblocks = at24->bwrite(at24, START_BLOCK, NBLOCK, write_buf); + if (nblocks < NBLOCK) + { + ferr("ERROR: AT24 write failed: %zd\n", nblocks); + gd32_i2cbus_uninitialize(i2c); + return (int)nblocks; + } + + read_buf = kmm_malloc(BUFFSIZE); + + /* Read the data write before */ + + nblocks = at24->bread(at24, START_BLOCK, NBLOCK, read_buf); + if (nblocks < NBLOCK) + { + ferr("ERROR: AT24 read failed: %zd\n", nblocks); + gd32_i2cbus_uninitialize(i2c); + return (int)nblocks; + } + + if (memcmp(read_buf, write_buf, BUFFSIZE) != 0) + { + ferr("ERROR: Read buffer does not match write buffer\n"); + return -1; + } + + /* Release the I2C instance. + * REVISIT: Need an interface to release the AT24 instance too + */ + + ret = gd32_i2cbus_uninitialize(i2c); + if (ret < 0) + { + ferr("ERROR: Failed to release the I2C interface: %d\n", ret); + } + + syslog(LOG_INFO, "INFO: I2C EEPROM write and read success: \ + %d\n", ret); + + return OK; +} + +#endif /* HAVE_AT24 */ diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_autoleds.c b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_autoleds.c new file mode 100644 index 0000000000000..88ee47ac826b8 --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_autoleds.c @@ -0,0 +1,177 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_autoleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "gd32f4xx_gpio.h" +#include "gd32f470z_aiotbox.h" +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* LED index */ + +static const uint32_t g_led_map[BOARD_LEDS] = +{ + LED1, + LED2, + LED3 +}; + +static bool g_initialized; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Turn on selected led */ + +static void gd32_aiotbox_led_on(led_typedef_enum led_num) +{ + gd32_gpio_write(g_led_map[led_num], true); +} + +/* Turn off selected led */ + +static void gd32_aiotbox_led_off(led_typedef_enum led_num) +{ + gd32_gpio_write(g_led_map[led_num], false); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + int i; + + /* Configure the LED GPIO for output. */ + + for (i = 0; i < nitems(g_led_map); i++) + { + gd32_gpio_config(g_led_map[i]); + } +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + switch (led) + { + default: + break; + + case LED_HEAPALLOCATE: + gd32_aiotbox_led_on(BOARD_LED1); + break; + + case LED_IRQSENABLED: + gd32_aiotbox_led_on(BOARD_LED2); + break; + + case LED_STACKCREATED: + gd32_aiotbox_led_on(BOARD_LED3); + g_initialized = true; + break; + + case LED_INIRQ: + gd32_aiotbox_led_on(BOARD_LED1); + gd32_aiotbox_led_on(BOARD_LED2); + break; + + case LED_SIGNAL: + gd32_aiotbox_led_on(BOARD_LED1); + gd32_aiotbox_led_on(BOARD_LED3); + break; + + case LED_ASSERTION: + gd32_aiotbox_led_on(BOARD_LED2); + gd32_aiotbox_led_on(BOARD_LED3); + break; + + case LED_PANIC: + gd32_aiotbox_led_on(BOARD_LED1); + break; + + case LED_IDLE : /* IDLE */ + gd32_aiotbox_led_on(BOARD_LED2); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + default: + break; + + case LED_SIGNAL: + gd32_aiotbox_led_off(BOARD_LED1); + gd32_aiotbox_led_off(BOARD_LED3); + break; + + case LED_INIRQ: + gd32_aiotbox_led_off(BOARD_LED1); + gd32_aiotbox_led_off(BOARD_LED2); + break; + + case LED_ASSERTION: + gd32_aiotbox_led_off(BOARD_LED2); + gd32_aiotbox_led_off(BOARD_LED3); + break; + + case LED_PANIC: + gd32_aiotbox_led_off(BOARD_LED1); + break; + + case LED_IDLE : /* IDLE */ + gd32_aiotbox_led_off(BOARD_LED2); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_boot.c b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_boot.c new file mode 100644 index 0000000000000..1012be3a09de2 --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_boot.c @@ -0,0 +1,85 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "gd32f470z_aiotbox.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_boardinitialize + * + * Description: + * All GD32F4xx architectures must provide the following entry point. + * This entry point is called early in the initialization + * after all memory has been configured and mapped but + * before any devices have been initialized. + * + ****************************************************************************/ + +void gd32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#if defined(CONFIG_SPI) + /* Configure SPI chip selects */ + + gd32_spidev_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() + * will be called immediately after up_initialize() is called and + * just before the initial application is started. This additional + * initialization phase may be used, for example, to initialize + * board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + gd32_bringup(); +} +#endif diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_bringup.c b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_bringup.c new file mode 100644 index 0000000000000..7a34d65772f69 --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_bringup.c @@ -0,0 +1,363 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gd32f4xx.h" + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_GD32F4_ROMFS +#include "gd32f4xx_romfs.h" +#endif + +#include "gd32f470z_aiotbox.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y : + * Called from the NSH library via boardctl() + * + ****************************************************************************/ + +int gd32_bringup(void) +{ +#ifdef CONFIG_RAMMTD + uint8_t *ramstart; +#endif + + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, GD32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", + GD32_PROCFS_MOUNTPOINT, ret); + } +#endif + +#ifdef CONFIG_RAMMTD + /* Create a RAM MTD device if configured */ + + ramstart = kmm_malloc(64 * 1024); + if (ramstart == NULL) + { + syslog(LOG_ERR, "ERROR: Allocation for RAM MTD failed\n"); + } + else + { + /* Initialized the RAM MTD */ + + struct mtd_dev_s *mtd = rammtd_initialize(ramstart, 64 * 1024); + if (mtd == NULL) + { + syslog(LOG_ERR, "ERROR: rammtd_initialize failed\n"); + kmm_free(ramstart); + } + else + { + /* Erase the RAM MTD */ + + ret = mtd->ioctl(mtd, MTDIOC_BULKERASE, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: IOCTL MTDIOC_BULKERASE failed\n"); + } + +#if defined(CONFIG_MTD_SMART) && defined(CONFIG_FS_SMARTFS) + /* Initialize a SMART Flash block device and bind it to the MTD + * device. + */ + + smart_initialize(0, mtd, NULL); + +#elif defined(CONFIG_FS_SPIFFS) + /* Register the MTD driver so that it can be accessed from the + * VFS. + */ + + ret = register_mtddriver("/dev/rammtd", mtd, 0755, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD driver: %d\n", + ret); + } + + /* Mount the SPIFFS file system */ + + ret = nx_mount("/dev/rammtd", "/mnt/spiffs", "spiffs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount SPIFFS at /mnt/spiffs: %d\n", + ret); + } + +#elif defined(CONFIG_FS_LITTLEFS) + /* Register the MTD driver so that it can be accessed from the + * VFS. + */ + + ret = register_mtddriver("/dev/rammtd", mtd, 0755, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD driver: %d\n", + ret); + } + + /* Mount the LittleFS file system */ + + ret = nx_mount("/dev/rammtd", "/mnt/lfs", "littlefs", 0, + "forceformat"); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount LittleFS at /mnt/lfs: %d\n", + ret); + } + +#elif defined(CONFIG_FS_NXFFS) + /* Initialize to provide NXFFS on the MTD interface */ + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: NXFFS initialization failed: %d\n", + ret); + } +#endif + } + } +#endif + +#if defined(CONFIG_INPUT_BUTTONS_LOWER) + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_GD32F4_ROMFS + /* Mount the romfs partition */ + + ret = gd32_romfs_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", + CONFIG_GD32F4_ROMFS_MOUNTPOINT, ret); + } +#endif + +#ifndef CONFIG_DISABLE_MOUNTPOINT + +# ifdef CONFIG_GD32F4_PROGMEM + + /* Create an instance of the GD32F4 FLASH program memory + * device driver + */ + + struct mtd_dev_s *mtd = progmem_initialize(); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: progmem_initialize failed\n"); + } + +# if defined(CONFIG_FS_NXFFS) + /* Initialize to provide NXFFS on the MTD interface */ + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: NXFFS initialization failed: %d\n", + ret); + } + + /* Mount the file system */ + + ret = nx_mount(NULL, CONFIG_GD32F4_NXFFS_MOUNTPT, "nxffs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the NXFFS volume: %d\n", + ret); + } +# elif defined(CONFIG_FS_LITTLEFS) + /* Initialize to provide LittleFS on the MTD interface */ + + ret = register_mtddriver("/dev/fmc", mtd, 0755, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); + return ret; + } + + /* Mount the file system at /mnt/fmc */ + + ret = nx_mount("/dev/fmc", "/mnt/fmc", "littlefs", 0, NULL); + if (ret < 0) + { + ret = nx_mount("/dev/fmc", "/mnt/fmc", "littlefs", 0, + "forceformat"); + if (ret < 0) + { + ferr("ERROR: Failed to mount the FS volume: %d\n", ret); + return ret; + } + } + + syslog(LOG_INFO, "INFO: LittleFS volume /mnt/fmc mount " + "on chip flash success: %d\n", ret); +# endif +# endif + +#ifdef CONFIG_I2C + gd32_i2c_initialize(); +#endif + +# ifdef HAVE_GD25 + + ret = gd32_gd25_automount(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the NXFFS \ + volume on spi flash: %d\n", ret); + } + +# endif + +# ifdef HAVE_AT24 + + ret = gd32_at24_wr_test(AT24_MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: I2C EEPROM write and read test fail: \ + %d\n", ret); + } + +# endif + +#endif /* CONFIG_FS_NXFFS */ + +#ifdef CONFIG_DEV_GPIO + /* Register the GPIO driver */ + + ret = gd32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS +#ifdef CONFIG_INPUT_BUTTONS_LOWER + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + return ret; + } +#else + /* Enable BUTTON support for some other purpose */ + + board_button_initialize(); +#endif /* CONFIG_INPUT_BUTTONS_LOWER */ +#endif /* CONFIG_INPUT_BUTTONS */ + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", + ret); + } +#endif + + /* Configure SDIO chip selects */ + +#ifdef CONFIG_ARCH_HAVE_SDIO + ret = gd32_sdio_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: gd32_sdio_initialize() failed: %d\n", ret); + return ret; + } + + /* Mount the file system at /mnt/sd */ + + ret = nx_mount("/dev/mmcsd0", "/mnt/sd", "vfat", 0, NULL); + if (ret < 0) + { + ret = nx_mount("/dev/mmcsd0", "/mnt/sd", "vfat", 0, + "forceformat"); + if (ret < 0) + { + ferr("ERROR: Failed to mount the SD card: %d\n", ret); + return ret; + } + } + + syslog(LOG_INFO, "INFO: FAT volume /mnt/sd mount " + "sd card success: %d\n", ret); +#endif + return ret; +} diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_buttons.c b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_buttons.c new file mode 100644 index 0000000000000..0352373c004eb --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_buttons.c @@ -0,0 +1,190 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_buttons.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include + +#include "gd32f4xx.h" +#include "gd32f470z_aiotbox.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const uint32_t g_button_boards[NUM_BUTTONS] = +{ + GPIO_BTN_USER, GPIO_BTN_TAMPER, GPIO_BTN_WAKEUP +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure each button */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + gd32_gpio_config(g_button_boards[i]); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 32-bit bit set with each bit associated with a button. See the BUTTON* + * definitions above for the meaning of each bit in the returned value. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret; + int i; + + /* Check each button */ + + for (i = 0, ret = 0; i < NUM_BUTTONS; i++) + { + /* The low value is sensed when the button is pressed */ + + if (!gd32_gpio_read(g_button_boards[i])) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current + * state of all buttons or board_button_irq() may be called to register + * button interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() + * may be called to collect the state of all buttons. board_buttons() + * returns an 32-bit bit set with each bit associated with a button. + * See the BUTTON_*_BIT definitions in board.h for the meaning of each + * bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value + * is a button enumeration value that uniquely identifies a button + * resource. See the BUTTON_* definitions in board.h for the meaning of + * enumeration value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + if (id >= 0 && id < NUM_BUTTONS) + { + uint8_t gpio_irq; + uint8_t gpio_irqnum; + irqstate_t flags; + int ret; + + /* Disable interrupts until we are done. This guarantees that the + * following operations are atomic. + */ + + flags = enter_critical_section(); + + /* Get gpio irq numbers */ + + ret = gd32_gpio_exti_irqnum_get(g_button_boards[id], &gpio_irqnum); + + if (ret < 0) + { + leave_critical_section(flags); + return ret; + } + + /* Are we attaching or detaching? */ + + if (irqhandler != NULL) + { + ret = gd32_exti_gpioirq_init(g_button_boards[id], EXTI_INTERRUPT, + EXTI_TRIG_RISING, &gpio_irq); + + if (ret < 0) + { + leave_critical_section(flags); + return ret; + } + + /* Attach and enable the interrupt */ + + gd32_exti_gpio_irq_attach(gpio_irq, irqhandler, arg); + up_enable_irq(gpio_irqnum); + } + else + { + /* Disable and detach the interrupt */ + + up_disable_irq(gpio_irqnum); + irq_detach(gpio_irqnum); + } + + leave_critical_section(flags); + } + + /* Return the old button handler (so that it can be restored) */ + + return OK; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_gd25.c b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_gd25.c new file mode 100644 index 0000000000000..d5db8faf42eac --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_gd25.c @@ -0,0 +1,164 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_gd25.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "gd32f4xx.h" +#include "gd32f470z_aiotbox.h" + +#ifdef HAVE_GD25 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_gd25_automount + * + * Description: + * Initialize, configure, and mount the GD25 SPI FLASH. The FLASH will + * be mounted at /dev/gd25. + * + ****************************************************************************/ + +int gd32_gd25_automount(int minor) +{ + struct spi_dev_s *spi; + struct mtd_dev_s *mtd; + static bool initialized = false; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* No.. Get the SPI port driver */ + + spi = gd32_spibus_initialize(SPI_FLASH_CSNUM); + if (!spi) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI port %d\n", + SPI_FLASH_CSNUM); + return -ENODEV; + } + + /* Now bind the SPI interface to the GD25 SPI FLASH driver */ + + mtd = gd25_initialize(spi, 0); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: Failed to bind SPI port to the \ + GD25 FLASH driver\n"); + return -ENODEV; + } + +#if defined(CONFIG_GD32F470ZK_EVAL_GD25_FTL) + /* And finally, use the FTL layer to wrap the MTD driver as a block + * driver at /dev/mtdblockN, where N=minor device number. + */ + + ret = ftl_initialize(minor, mtd); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize the FTL layer: %d\n", + ret); + return ret; + } + +#elif defined(CONFIG_GD32F470ZK_EVAL_GD25_NXFFS) + /* Initialize to provide NXFFS on the MTD interface */ + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: NXFFS initialization failed: %d\n", ret); + return ret; + } + + /* Mount the file system at /mnt/gd25 */ + + ret = nx_mount(NULL, "/mnt/gd25", "nxffs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the NXFFS volume: %d\n", + ret); + return ret; + } + + syslog(LOG_INFO, "INFO: NXFFS volume /mnt/gd25 mount \ + spi flash success: %d\n", ret); + +#elif defined(CONFIG_GD32F470ZK_EVAL_GD25_LITTLEFS) + /* Initialize to provide LittleFS on the MTD interface */ + + ret = register_mtddriver("/dev/spiflash", mtd, 0755, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); + return ret; + } + + /* Mount the file system at /mnt/gd25 */ + + ret = nx_mount("/dev/spiflash", "/mnt/gd25", "littlefs", 0, NULL); + if (ret < 0) + { + ret = nx_mount("/dev/spiflash", "/mnt/gd25", "littlefs", 0, + "forceformat"); + if (ret < 0) + { + ferr("ERROR: Failed to mount the FS volume: %d\n", ret); + return ret; + } + } + + syslog(LOG_INFO, "INFO: LittleFS volume /mnt/gd25 mount \ + spi flash success: %d\n", ret); +#endif + + /* Now we are initialized */ + + initialized = true; + } + + UNUSED(ret); + + return OK; +} + +#endif /* HAVE_GD25 */ diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_gpio.c b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_gpio.c new file mode 100644 index 0000000000000..464242d95fec2 --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_gpio.c @@ -0,0 +1,492 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" + +#include "gd32f4xx.h" +#include "gd32f470z_aiotbox.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct gd32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint32_t pinconfig; + uint8_t id; +}; + +struct gd32gpint_dev_s +{ + struct gd32gpio_dev_s gd32gpio; + pin_interrupt_t callback; +}; + +irqstate_t flags; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int gpio_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e gp_pintype); + +#if BOARD_NGPIOIN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value); +#endif + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +#endif + +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + + #if BOARD_NGPIOIN > 0 +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, + .go_setpintype = gpio_setpintype, +}; + +/* This array maps the GPIO pins used as INPUT */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1, +}; + +static struct gd32gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOOUT > 0 + +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, + .go_setpintype = gpio_setpintype, +}; + +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, +}; + +static struct gd32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 + +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, + .go_setpintype = gpio_setpintype, +}; + +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_INT1, +}; + +static struct gd32gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpio_setpintype + * + * Description: + * set gpio pintype. + * + ****************************************************************************/ + +static int gpio_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e gpio_pintype) +{ + int ret = OK; + uint32_t pinconfig; + const struct gpio_operations_s *gpio_ops; + struct gd32gpint_dev_s *gd32gpint = (struct gd32gpint_dev_s *)dev; + + DEBUGASSERT(gd32gpint != NULL); + gpioinfo("Setpintype...\n"); + + /* Check if the new pintype is actually different from the old pintype */ + + if (gd32gpint->gd32gpio.gpio.gp_pintype == gpio_pintype) + { + /* Pintype has not changed. We're done already. */ + + return ret; + } + + if (gd32gpint->gd32gpio.gpio.gp_pintype >= GPIO_NPINTYPES) + { + gpioerr("pintype error\n"); + return -1; + } + + pinconfig = (gd32gpint->gd32gpio.pinconfig & + (GPIO_CFG_PIN_MASK | GPIO_CFG_PORT_MASK)); + + switch (gpio_pintype) + { + case GPIO_INPUT_PIN: + gd32_gpio_config(GPIO_CFG_MODE_INPUT | GPIO_CFG_PUPD_NONE | + pinconfig); + gpio_ops = &gpin_ops; + break; + case GPIO_INPUT_PIN_PULLUP: + gd32_gpio_config(GPIO_CFG_MODE_INPUT | GPIO_CFG_PUPD_PULLUP | + pinconfig); + gpio_ops = &gpin_ops; + break; + case GPIO_INPUT_PIN_PULLDOWN: + gd32_gpio_config(GPIO_CFG_MODE_INPUT | GPIO_CFG_PUPD_PULLDOWN | + pinconfig); + gpio_ops = &gpin_ops; + break; + case GPIO_OUTPUT_PIN: + gd32_gpio_config(GPIO_CFG_MODE_OUTPUT | GPIO_CFG_PP | + GPIO_CFG_SPEED_50MHZ | pinconfig); + gpio_ops = &gpout_ops; + break; + case GPIO_OUTPUT_PIN_OPENDRAIN: + gd32_gpio_config(GPIO_CFG_MODE_OUTPUT | GPIO_CFG_OD | + GPIO_CFG_SPEED_50MHZ | pinconfig); + gpio_ops = &gpout_ops; + break; + case GPIO_INTERRUPT_PIN: + case GPIO_INTERRUPT_RISING_PIN: + case GPIO_INTERRUPT_FALLING_PIN: + case GPIO_INTERRUPT_BOTH_PIN: + gd32_gpio_config(GPIO_CFG_MODE_INPUT | GPIO_PUPD_NONE | + pinconfig); + gpio_ops = &gpint_ops; + break; + default: + + /* Not support! */ + + return -EINVAL; + break; + } + + /* If the pin previously had an interrupt pintype... */ + + if ((gd32gpint->gd32gpio.gpio.gp_pintype >= GPIO_INTERRUPT_PIN) && + (gd32gpint->gd32gpio.gpio.gp_pintype < GPIO_NPINTYPES)) + { + /* ...disable the interrupt... */ + + ret = gpint_enable(dev, false); + if (ret < 0) + { + return ret; + } + + /* ...and detach the old callback. */ + + ret = gpint_attach(dev, NULL); + if (ret < 0) + { + return ret; + } + } + + /* Change the pintype and set of operations */ + + gd32gpint->gd32gpio.gpio.gp_pintype = gpio_pintype; + gd32gpint->gd32gpio.gpio.gp_ops = gpio_ops; + gd32gpint->gd32gpio.pinconfig = pinconfig; + + return 0; +} + +#if BOARD_NGPIOIN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value) +{ + struct gd32gpio_dev_s *gd32gpio = (struct gd32gpio_dev_s *)dev; + + DEBUGASSERT(gd32gpio != NULL && value != NULL); + gpioinfo("Reading...\n"); + + *value = gd32_gpio_read(gd32gpio->pinconfig); + + return OK; +} +#endif + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct gd32gpio_dev_s *gd32gpio = (struct gd32gpio_dev_s *)dev; + + DEBUGASSERT(gd32gpio != NULL && value != NULL); + gpioinfo("Reading...\n"); + + *value = gd32_gpio_read(gd32gpio->pinconfig); + + return OK; +} + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct gd32gpio_dev_s *gd32gpio = (struct gd32gpio_dev_s *)dev; + + DEBUGASSERT(gd32gpio != NULL); + gpioinfo("Writing %d\n", (int)value); + + gd32_gpio_write(gd32gpio->pinconfig, value); + + return OK; +} +#endif + +#if BOARD_NGPIOINT > 0 + +static int gd32gpio_interrupt(int irq, void *context, void *arg) +{ + struct gd32gpint_dev_s *gd32gpint = (struct gd32gpint_dev_s *)arg; + + DEBUGASSERT(gd32gpint != NULL && gd32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", gd32gpint->callback); + + gd32gpint->callback(&gd32gpint->gd32gpio.gpio, gd32gpint->gd32gpio.id); + return OK; +} + +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct gd32gpint_dev_s *gd32gpint = (struct gd32gpint_dev_s *)dev; + + DEBUGASSERT(gd32gpint != NULL && value != NULL); + DEBUGASSERT(gd32gpint->gd32gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = gd32_gpio_read(gd32gpint->gd32gpio.pinconfig); + + return OK; +} + +static int gpint_attach(struct gpio_dev_s *dev, pin_interrupt_t callback) +{ + struct gd32gpint_dev_s *gd32gpint = (struct gd32gpint_dev_s *)dev; + int ret; + uint8_t gpio_irq; + uint8_t gpio_irqnum; + + gpioinfo("Attaching the callback\n"); + + flags = enter_critical_section(); + + /* Make sure the interrupt is disabled */ + + ret = gd32_exti_gpioirq_init(g_gpiointinputs[gd32gpint->gd32gpio.id], + EXTI_INTERRUPT, EXTI_TRIG_RISING, &gpio_irq); + + if (ret < 0) + { + leave_critical_section(flags); + return ret; + } + + gd32_gpio_exti_irqnum_get(g_gpiointinputs[gd32gpint->gd32gpio.id], + &gpio_irqnum); + + /* Attach and disable the interrupt */ + + gd32_exti_gpio_irq_attach(gpio_irq, gd32gpio_interrupt, + &g_gpint[gd32gpint->gd32gpio.id]); + + /* Disable and the interrupt */ + + up_disable_irq(gpio_irqnum); + + leave_critical_section(flags); + gpioinfo("Attach %p\n", callback); + gd32gpint->callback = callback; + return OK; +} + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct gd32gpint_dev_s *gd32gpint = (struct gd32gpint_dev_s *)dev; + int ret; + uint8_t gpio_irqnum; + + flags = enter_critical_section(); + + /* Get gpio irq numbers */ + + ret = gd32_gpio_exti_irqnum_get(g_gpiointinputs[gd32gpint->gd32gpio.id], + &gpio_irqnum); + if (ret < 0) + { + leave_critical_section(flags); + return ret; + } + + if (enable) + { + if (gd32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Enable the interrupt */ + + up_disable_irq(gpio_irqnum); + } + } + else + { + up_disable_irq(gpio_irqnum); + gpioinfo("Disable the interrupt\n"); + } + + leave_critical_section(flags); + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int gd32_gpio_initialize(void) +{ + int pincount = 0; + int i; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].pinconfig = g_gpioinputs[i]; + g_gpin[i].id = i; + + gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pin that will be used as input */ + + gd32_gpio_config(g_gpioinputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].pinconfig = g_gpiooutputs[i]; + g_gpout[i].id = i; + + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pin that will be used as output */ + + gd32_gpio_write(g_gpiooutputs[i], 0); + gd32_gpio_config(g_gpiooutputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].gd32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].gd32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].gd32gpio.pinconfig = g_gpiointinputs[i]; + g_gpint[i].gd32gpio.id = i; + (void)gpio_pin_register(&g_gpint[i].gd32gpio.gpio, pincount); + + /* Configure the pin that will be used as interrupt input */ + + gd32_gpio_config(g_gpiointinputs[i]); + + pincount++; + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_i2c.c b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_i2c.c new file mode 100644 index 0000000000000..26169f9f2f574 --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_i2c.c @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_i2c.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ +#include +#include +#include +#include +#include + +#include + +#include"gd32f4xx.h" +#include "gd32f470z_aiotbox.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_I2C +void gd32_i2c_initialize(void) +{ + FAR struct i2c_master_s *i2c; + int ret; + i2cinfo("Initialize I2c\n"); + +#ifdef CONFIG_GD32F4_I2C0 + i2c = gd32_i2cbus_initialize(0); + + if (i2c == NULL) + { + i2cerr("init i2c0 faild.\n"); + return; + } + else + { + ret = i2c_register(i2c, 0); + + if (ret < 0) + { + i2cerr("registering i2c0 faild.\n"); + } + else + { + i2cinfo("registering i2c0 successed.\n"); + } + } + + i2c = NULL; +#endif +#ifdef CONFIG_GD32F4_I2C1 + i2c = gd32_i2cbus_initialize(1); + + if (i2c == NULL) + { + i2cerr("init i2c1 faild.\n"); + return; + } + else + { + ret = i2c_register(i2c, 1); + + if (ret < 0) + { + i2cerr("registering i2c1 faild.\n"); + } + else + { + i2cinfo("registering i2c1 successed.\n"); + } + } + +#endif +} + +#endif \ No newline at end of file diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_reset.c b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_reset.c new file mode 100644 index 0000000000000..a5607896f3d9b --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_reset.c @@ -0,0 +1,62 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_reset.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#ifdef CONFIG_BOARDCTL_RESET + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value int this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ + up_systemreset(); + return 0; +} + +#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_romfs.c b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_romfs.c new file mode 100644 index 0000000000000..a5b77da4470e0 --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_romfs.c @@ -0,0 +1,137 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_romfs.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include "gd32f4xx_romfs.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_GD32F4_ROMFS +# error "CONFIG_GD32F4_ROMFS must be defined" +#else + +#ifndef CONFIG_GD32F4_ROMFS_IMAGEFILE +# error "CONFIG_GD32F4_ROMFS_IMAGEFILE must be defined" +#endif + +#ifndef CONFIG_GD32F4_ROMFS_DEV_MINOR +# error "CONFIG_GD32F4_ROMFS_DEV_MINOR must be defined" +#endif + +#ifndef CONFIG_GD32F4_ROMFS_MOUNTPOINT +# error "CONFIG_GD32F4_ROMFS_MOUNTPOINT must be defined" +#endif + +#define NSECTORS(size) (((size) + ROMFS_SECTOR_SIZE - 1)/ROMFS_SECTOR_SIZE) + +#define STR2(m) #m +#define STR(m) STR2(m) + +#define MKMOUNT_DEVNAME(m) "/dev/ram" STR(m) +#define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_GD32F4_ROMFS_DEV_MINOR) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +__asm__ ( + " .section .rodata \n" + " .balign 16 \n" + " .globl romfs_data_begin \n" + "romfs_data_begin: \n" + " .incbin " STR(CONFIG_GD32F4_ROMFS_IMAGEFILE)"\n" + " .balign " STR(ROMFS_SECTOR_SIZE) "\n" + " .globl romfs_data_end \n" + "romfs_data_end: \n" + ); + +extern const uint8_t romfs_data_begin[]; +extern const uint8_t romfs_data_end[]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_romfs_initialize + * + * Description: + * Registers the aboveincluded binary file as block device. + * Then mounts the block device as ROMFS filesystems. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [romfs_data_begin .. romfs_data_end) should contain + * ROMFS volume data, as included in the assembly snippet above. + * + ****************************************************************************/ + +int gd32_romfs_initialize(void) +{ + uintptr_t romfs_data_len; + int ret; + + /* Create a ROM disk for the /etc filesystem */ + + romfs_data_len = romfs_data_end - romfs_data_begin; + + ret = romdisk_register(CONFIG_GD32F4_ROMFS_DEV_MINOR, romfs_data_begin, + NSECTORS(romfs_data_len), ROMFS_SECTOR_SIZE); + if (ret < 0) + { + ferr("ERROR: romdisk_register failed: %d\n", -ret); + return ret; + } + + /* Mount the file system */ + + finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", + CONFIG_GD32F4_ROMFS_MOUNTPOINT, MOUNT_DEVNAME); + + ret = nx_mount(MOUNT_DEVNAME, CONFIG_GD32F4_ROMFS_MOUNTPOINT, + "romfs", MS_RDONLY, NULL); + if (ret < 0) + { + ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", + MOUNT_DEVNAME, CONFIG_GD32F4_ROMFS_MOUNTPOINT, ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_GD32F4_ROMFS */ diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_romfs.h b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_romfs.h new file mode 100644 index 0000000000000..658ad1e38bac6 --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_romfs.h @@ -0,0 +1,62 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_romfs.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_GD32F4_GD32F470ZK_AIOTBOX_SRC_GD32F4XX_ROMFS_H +#define __BOARDS_ARM_GD32F4_GD32F470ZK_AIOTBOX_SRC_GD32F4XX_ROMFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_GD32F4_ROMFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ROMFS_SECTOR_SIZE 64 + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_romfs_initialize + * + * Description: + * Registers built-in ROMFS image as block device and mounts it. + * + * Returned Value: + * Zero (OK) on success, a negated errno value on error. + * + * Assumptions/Limitations: + * Memory addresses [romfs_data_begin .. romfs_data_end) should contain + * ROMFS volume data, as included in the assembly snippet in + * gd32f4xx_romfs.c. + * + ****************************************************************************/ + +int gd32_romfs_initialize(void); + +#endif /* CONFIG_GD32F4_ROMFS */ + +#endif /* __BOARDS_ARM_GD32F4_GD32F470ZK_EVAL_SRC_GD32F4XX_ROMFS_H */ diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_sdio.c b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_sdio.c new file mode 100644 index 0000000000000..3150f3f2fb54d --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_sdio.c @@ -0,0 +1,149 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_sdio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "gd32f4xx.h" +#include "gd32f470z_aiotbox.h" + +#ifdef CONFIG_MMCSD + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Card detections requires card support and a card detection GPIO */ + +#define HAVE_NCD 1 +#if !defined(GPIO_SDMMC1_NCD) +# undef HAVE_NCD +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; +#ifdef HAVE_NCD +static bool g_sd_inserted; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_ncd_interrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef HAVE_NCD +static int gd32_ncd_interrupt(int irq, void *context) +{ + bool present; + + present = !gd32_gpio_read(GPIO_SDMMC1_NCD); + if (g_sdio_dev && present != g_sd_inserted) + { + sdio_mediachange(g_sdio_dev, present); + g_sd_inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +int gd32_sdio_initialize(void) +{ + int ret; + + /* Mount the SDIO-based MMC/SD block driver + * First, get an instance of the SDIO interface + */ + + finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_SLOTNO); + if (!g_sdio_dev) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); + + ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); + if (ret != OK) + { + ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + finfo("Successfully bound SDIO to the MMC/SD driver\n"); + +#ifdef HAVE_NCD + /* Use SD card detect pin to check if a card is g_sd_inserted */ + + g_sd_inserted = !gd32_gpio_read(GPIO_SDMMC1_NCD); + finfo("Card detect : %d\n", g_sd_inserted); + + sdio_mediachange(g_sdio_dev, g_sd_inserted); +#else + /* Assume that the SD card is inserted. What choice do we have? */ + + sdio_mediachange(g_sdio_dev, true); +#endif + + return OK; +} + +#endif /* CONFIG_MMCSD */ diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_spi.c b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_spi.c new file mode 100644 index 0000000000000..9b83fcd01aa7a --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_spi.c @@ -0,0 +1,283 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_spi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "gd32f4xx.h" +#include "gd32f470z_aiotbox.h" + +#if defined(CONFIG_SPI) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the GD32F470Z-EVAL. + * + ****************************************************************************/ + +void weak_function gd32_spidev_initialize(void) +{ +#ifdef CONFIG_GD32F4_SPI0 + /* Configure SPI0 CS GPIO for output */ + + gd32_gpio_config(GPIO_SPI0_CSPIN); + gd32_gpio_write(GPIO_SPI0_CSPIN, 1); +#endif +#ifdef CONFIG_GD32F4_SPI1 + /* Configure SPI1 CS GPIO for output */ + + gd32_gpio_config(GPIO_SPI1_CSPIN); + gd32_gpio_write(GPIO_SPI1_CSPIN, 1); +#endif +#ifdef CONFIG_GD32F4_SPI2 + /* Configure SPI2 CS GPIO for output */ + + gd32_gpio_config(GPIO_SPI2_CSPIN); + gd32_gpio_write(GPIO_SPI2_CSPIN, 1); +#endif +#ifdef CONFIG_GD32F4_SPI3 + /* Configure SPI3 CS GPIO for output */ + + gd32_gpio_config(GPIO_SPI3_CSPIN); + gd32_gpio_write(GPIO_SPI3_CSPIN, 1); +#endif +#ifdef CONFIG_GD32F4_SPI4 + /* Configure SPI4 CS GPIO for output */ + + gd32_gpio_config(GPIO_SPI4_CSPIN); + gd32_gpio_write(GPIO_SPI4_CSPIN, 1); +#endif +#ifdef CONFIG_GD32F4_SPI5 + /* Configure SPI5 CS GPIO for output */ + + gd32_gpio_config(GPIO_SPI5_CSPIN); + gd32_gpio_write(GPIO_SPI5_CSPIN, 1); +#endif +} + +/**************************************************************************** + * Name: gd32_spi[n]select and gd32_spi[n]status + * + * Description: + * The external functions, gd32_spi0-5select and gd32_spi0-5 status + * must be provided by board-specific logic. They are implementations of the + * select and status methods of the SPI interface defined by struct spi_ops_s + * (see include/nuttx/spi/spi.h). + * All other methods (including gd32_spibus_initialize()) are provided by + * common GD32F4 logic. To use this common SPI logic on your board: + * + * 1. Provide logic in gd32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide gd32_spi[n]select() and gd32_spi[n]status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to gd32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by gd32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_GD32F4_SPI0 +void gd32_spi0select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + gd32_gpio_write(GPIO_SPI0_CSPIN, !selected); +} + +uint8_t gd32_spi0status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_GD32F4_SPI1 +void gd32_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + gd32_gpio_write(GPIO_SPI1_CSPIN, !selected); +} + +uint8_t gd32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_GD32F4_SPI2 +void gd32_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + gd32_gpio_write(GPIO_SPI2_CSPIN, !selected); +} + +uint8_t gd32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_GD32F4_SPI3 +void gd32_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + gd32_gpio_write(GPIO_SPI3_CSPIN, !selected); +} + +uint8_t gd32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_GD32F4_SPI4 +void gd32_spi4select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + gd32_gpio_write(GPIO_SPI4_CSPIN, !selected); +} + +uint8_t gd32_spi4status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_GD32F4_SPI5 +void gd32_spi5select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, + selected ? "assert" : "de-assert"); + + gd32_gpio_write(GPIO_SPI5_CSPIN, !selected); +} + +uint8_t gd32_spi5status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: gd32_spi[n]cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_GD32F4_SPI0 +int gd32_spi0cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_GD32F4_SPI1 +int gd32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_GD32F4_SPI2 +int gd32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_GD32F4_SPI3 +int gd32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_GD32F4_SPI5 +int gd32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_GD32F4_SPI5 +int gd32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* defined(CONFIG_SPI) */ diff --git a/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_userleds.c b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_userleds.c new file mode 100644 index 0000000000000..04395e01c0c52 --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_userleds.c @@ -0,0 +1,149 @@ +/**************************************************************************** + * boards/arm/gd32f4/gd32f470zk-aiotbox/src/gd32f4xx_userleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "gd32f4xx_gpio.h" +#include "gd32f470z_aiotbox.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* LED index */ + +static const uint32_t g_led_map[BOARD_LEDS] = +{ + LED1, + LED2, + LED3 +}; + +static const uint32_t g_led_setmap[BOARD_LEDS] = +{ + BOARD_LED1_BIT, + BOARD_LED2_BIT, + BOARD_LED3_BIT +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Turn on selected led */ + +static void gd32_aiotbox_led_on(led_typedef_enum led_num) +{ + gd32_gpio_write(g_led_map[led_num], true); +} + +/* Turn off selected led */ + +static void gd32_aiotbox_led_off(led_typedef_enum led_num) +{ + gd32_gpio_write(g_led_map[led_num], false); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the + * board_userled_initialize() is available to initialize the LED from user + * application logic. + * + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + int i; + + /* Configure the LED GPIO for output. */ + + for (i = 0; i < nitems(g_led_map); i++) + { + gd32_gpio_config(g_led_map[i]); + } + + return BOARD_LEDS; +} + +/**************************************************************************** + * Name: board_userled + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is + * available to control the LED from user application logic. + * + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < nitems(g_led_map)) + { + gd32_gpio_write(g_led_map[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + * + * Description: + * If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board + * LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all() + * is available to control the LED from user application logic. + * NOTE: since there is only a single LED on-board, this is function + * is not very useful. + * + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + int i; + + /* Configure LED1-3 GPIOs for output */ + + for (i = 0; i < nitems(g_led_map); i++) + { + gd32_gpio_write(g_led_map[i], (ledset & g_led_setmap[i]) != 0); + } +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/gd32f4/gd32f470zk-eval/include/nsh_romfsimg.h b/boards/arm/gd32f4/gd32f470zk-eval/include/nsh_romfsimg.h deleted file mode 100644 index 080de1625b49b..0000000000000 --- a/boards/arm/gd32f4/gd32f470zk-eval/include/nsh_romfsimg.h +++ /dev/null @@ -1,111 +0,0 @@ -/*************************************************************************** - * boards/arm/gd32f4/gd32f470zk-eval/include/nsh_romfsimg.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ***************************************************************************/ - -const unsigned char romfs_img[] = -{ - 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x01, 0x50, - 0x9f, 0x13, 0x82, 0x87, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56, - 0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, - 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, - 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, - 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x68, 0x2d, 0x96, 0x03, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, - 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x00, - 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x3a, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x6e, 0x8d, 0x9c, 0xab, 0x58, 0x72, 0x63, 0x53, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x23, 0x20, 0x43, 0x72, 0x65, 0x61, 0x74, 0x65, 0x20, 0x61, 0x20, 0x52, - 0x41, 0x4d, 0x44, 0x49, 0x53, 0x4b, 0x20, 0x61, 0x6e, 0x64, 0x20, 0x6d, - 0x6f, 0x75, 0x6e, 0x74, 0x20, 0x69, 0x74, 0x20, 0x61, 0x74, 0x20, 0x2f, - 0x74, 0x6d, 0x70, 0x0a, 0x0a, 0x6d, 0x6b, 0x72, 0x64, 0x20, 0x2d, 0x6d, - 0x20, 0x32, 0x20, 0x2d, 0x73, 0x20, 0x35, 0x31, 0x32, 0x20, 0x31, 0x30, - 0x32, 0x34, 0x0a, 0x6d, 0x6b, 0x66, 0x61, 0x74, 0x66, 0x73, 0x20, 0x2f, - 0x64, 0x65, 0x76, 0x2f, 0x72, 0x61, 0x6d, 0x32, 0x0a, 0x6d, 0x6f, 0x75, - 0x6e, 0x74, 0x20, 0x2d, 0x74, 0x20, 0x76, 0x66, 0x61, 0x74, 0x20, 0x2f, - 0x64, 0x65, 0x76, 0x2f, 0x72, 0x61, 0x6d, 0x32, 0x20, 0x2f, 0x74, 0x6d, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; - -const unsigned int romfs_img_len = 1024; diff --git a/boards/arm/gd32f4/gd32f470zk-eval/src/Makefile b/boards/arm/gd32f4/gd32f470zk-eval/src/Makefile index 1ff25088702e8..d4612d522a491 100644 --- a/boards/arm/gd32f4/gd32f470zk-eval/src/Makefile +++ b/boards/arm/gd32f4/gd32f470zk-eval/src/Makefile @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/gd32f4/gd32f470zk-eval/src/Make.defs +# boards/arm/gd32f4/gd32f470zk-eval/src/Makefile # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with @@ -22,15 +22,16 @@ include $(TOPDIR)/Make.defs CSRCS = gd32f4xx_boot.c -ifeq ($(CONFIG_BOARDCTL),y) -CSRCS += gd32f4xx_appinit.c -endif # ifeq ($(CONFIG_BOARDCTL),y) -# CSRCS += gd32f4xx_appinit.c gd32f4xx_bringup.c -# else ifeq ($(CONFIG_BOARD_LATE_INITIALIZE),y) -# CSRCS += gd32f4xx_bringup.c +# CSRCS += gd32f4xx_appinit.c # endif +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += gd32f4xx_appinit.c gd32f4xx_bringup.c +else ifeq ($(CONFIG_BOARD_LATE_INITIALIZE),y) +CSRCS += gd32f4xx_bringup.c +endif + ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += gd32f4xx_autoleds.c else @@ -65,4 +66,8 @@ ifeq ($(CONFIG_BOARDCTL_RESET), y) CSRCS += gd32f4xx_reset.c endif +ifeq ($(CONFIG_ETC_ROMFS), y) +CSRCS += etc_romfs.c +endif + include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/gd32f4/gd32f470zk-eval/src/etc_romfs.c b/boards/arm/gd32f4/gd32f470zk-eval/src/etc_romfs.c new file mode 100644 index 0000000000000..79c7e9a6b5ffb --- /dev/null +++ b/boards/arm/gd32f4/gd32f470zk-eval/src/etc_romfs.c @@ -0,0 +1,119 @@ +/*************************************************************************** + * boards/arm/gd32f4/gd32f470zk-eval/src/etc_romfs.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ***************************************************************************/ + +/*************************************************************************** + * Public Data + ***************************************************************************/ + +const unsigned char romfs_img[] = +{ + 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x01, 0x50, + 0x9f, 0x13, 0x82, 0x87, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56, + 0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, + 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, + 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; + +const unsigned int romfs_img_len = 1024; + +/*************************************************************************** + * Public Functions + ***************************************************************************/ diff --git a/boards/arm/gd32f4/gd32f470zk-eval/src/gd32f470z_eval.h b/boards/arm/gd32f4/gd32f470zk-eval/src/gd32f470z_eval.h index 77f772f29b9a9..a9fc5d06b902d 100644 --- a/boards/arm/gd32f4/gd32f470zk-eval/src/gd32f470z_eval.h +++ b/boards/arm/gd32f4/gd32f470zk-eval/src/gd32f470z_eval.h @@ -180,6 +180,26 @@ #ifndef __ASSEMBLY__ +/**************************************************************************** + * Name: gd32_bringup + * + * Description: + * Perform architecture specific initialization + * + * CONFIG_BOARDCTL=y: + * If CONFIG_NSH_ARCHINITIALIZE=y: + * Called from the NSH library (or other application) + * Otherwise, assumed to be called from some other application. + * + * Otherwise CONFIG_BOARD_LATE_INITIALIZE=y: + * Called from board_late_initialize(). + * + * Otherwise, bad news: Never called + * + ****************************************************************************/ + +int gd32_bringup(void); + /**************************************************************************** * Name: gd32_spidev_initialize * diff --git a/boards/arm/gd32f4/gd32f470zk-eval/src/gd32f4xx_appinit.c b/boards/arm/gd32f4/gd32f470zk-eval/src/gd32f4xx_appinit.c index dda59a79481d5..dbe9a91b9f54f 100644 --- a/boards/arm/gd32f4/gd32f470zk-eval/src/gd32f4xx_appinit.c +++ b/boards/arm/gd32f4/gd32f470zk-eval/src/gd32f4xx_appinit.c @@ -24,24 +24,14 @@ #include -#include -#include +#include +#include #include +#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#ifdef CONFIG_GD32F4_ROMFS -#include "gd32f4xx_romfs.h" -#endif +#include +#include "gd32f4xx.h" #include "gd32f470z_eval.h" /**************************************************************************** @@ -75,192 +65,7 @@ int board_app_initialize(uintptr_t arg) { - int ret; - static bool initialized = false; - - /* Have we already initialized? */ - - if (!initialized) - { -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, GD32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at %s: %d\n", - GD32_PROCFS_MOUNTPOINT, ret); - } -#endif - -#ifdef CONFIG_GD32F4_ROMFS - /* Mount the romfs partition */ - - ret = gd32_romfs_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", - CONFIG_GD32F4_ROMFS_MOUNTPOINT, ret); - } -#endif - -#ifndef CONFIG_DISABLE_MOUNTPOINT - -# ifdef CONFIG_GD32F4_PROGMEM - - /* Create an instance of the GD32F4 FLASH program memory - * device driver - */ - - struct mtd_dev_s *mtd = progmem_initialize(); - if (!mtd) - { - syslog(LOG_ERR, "ERROR: progmem_initialize failed\n"); - } - -# if defined(CONFIG_FS_NXFFS) - /* Initialize to provide NXFFS on the MTD interface */ - - ret = nxffs_initialize(mtd); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: NXFFS initialization failed: %d\n", - ret); - } - - /* Mount the file system */ - - ret = nx_mount(NULL, CONFIG_GD32F4_NXFFS_MOUNTPT, "nxffs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount the NXFFS volume: %d\n", - ret); - } -# elif defined(CONFIG_FS_LITTLEFS) - /* Initialize to provide LittleFS on the MTD interface */ - - ret = register_mtddriver("/dev/fmc", mtd, 0755, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); - return ret; - } - - /* Mount the file system at /mnt/fmc */ - - ret = nx_mount("/dev/fmc", "/mnt/fmc", "littlefs", 0, NULL); - if (ret < 0) - { - ret = nx_mount("/dev/fmc", "/mnt/fmc", "littlefs", 0, - "forceformat"); - if (ret < 0) - { - ferr("ERROR: Failed to mount the FS volume: %d\n", ret); - return ret; - } - } - - syslog(LOG_INFO, "INFO: LittleFS volume /mnt/fmc mount " \ - "on chip flash success: %d\n", ret); -# endif -# endif - -# ifdef HAVE_GD25 - - ret = gd32_gd25_automount(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount the NXFFS \ - volume on spi flash: %d\n", ret); - } - -# endif - -# ifdef HAVE_AT24 - - ret = gd32_at24_wr_test(AT24_MINOR); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: I2C EEPROM write and read test fail: \ - %d\n", ret); - } - -# endif - -#endif /* CONFIG_FS_NXFFS */ - -#ifdef CONFIG_DEV_GPIO - /* Register the GPIO driver */ - - ret = gd32_gpio_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_INPUT_BUTTONS -#ifdef CONFIG_INPUT_BUTTONS_LOWER - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); - return ret; - } -#else - /* Enable BUTTON support for some other purpose */ - - board_button_initialize(); -#endif /* CONFIG_INPUT_BUTTONS_LOWER */ -#endif /* CONFIG_INPUT_BUTTONS */ - -#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) - /* Register the LED driver */ - - ret = userled_lower_initialize(LED_DRIVER_PATH); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", - ret); - } -#endif - - /* Configure SDIO chip selects */ - -#ifdef CONFIG_ARCH_HAVE_SDIO - ret = gd32_sdio_initialize(); - if (ret != OK) - { - syslog(LOG_ERR, "ERROR: gd32_sdio_initialize() failed: %d\n", ret); - return ret; - } - - /* Mount the file system at /mnt/sd */ - - ret = nx_mount("/dev/mmcsd0", "/mnt/sd", "vfat", 0, NULL); - if (ret < 0) - { - ret = nx_mount("/dev/mmcsd0", "/mnt/sd", "vfat", 0, - "forceformat"); - if (ret < 0) - { - ferr("ERROR: Failed to mount the SD card: %d\n", ret); - return ret; - } - } - - syslog(LOG_INFO, "INFO: FAT volume /mnt/sd mount " \ - "sd card success: %d\n", ret); -#endif - - /* Now we are initialized */ - - initialized = true; - } + /* Perform board initialization here */ - UNUSED(ret); - return OK; + return gd32_bringup(); } diff --git a/boards/arm/gd32f4/gd32f470zk-eval/src/gd32f4xx_boot.c b/boards/arm/gd32f4/gd32f470zk-eval/src/gd32f4xx_boot.c index 055d98cdcdf5e..53b6ea21a5599 100644 --- a/boards/arm/gd32f4/gd32f470zk-eval/src/gd32f4xx_boot.c +++ b/boards/arm/gd32f4/gd32f470zk-eval/src/gd32f4xx_boot.c @@ -78,13 +78,8 @@ void gd32_boardinitialize(void) #ifdef CONFIG_BOARD_LATE_INITIALIZE void board_late_initialize(void) { -#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_BOARDCTL) - /* Perform NSH initialization here instead of from the NSH. This - * alternative NSH initialization is necessary when NSH is ran in - * user-space but the initialization function must run in kernel space. - */ + /* Perform board-specific initialization */ - board_app_initialize(0); -#endif + gd32_bringup(); } #endif diff --git a/boards/arm/gd32f4/gd32f470zk-eval/src/gd32f4xx_bringup.c b/boards/arm/gd32f4/gd32f470zk-eval/src/gd32f4xx_bringup.c index f6921d21a192c..63981f5add409 100644 --- a/boards/arm/gd32f4/gd32f470zk-eval/src/gd32f4xx_bringup.c +++ b/boards/arm/gd32f4/gd32f470zk-eval/src/gd32f4xx_bringup.c @@ -35,10 +35,23 @@ #include #include #include -#include #include #include +#include "gd32f4xx.h" + +#ifdef CONFIG_USERLED +# include +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_GD32F4_ROMFS +#include "gd32f4xx_romfs.h" +#endif + #include "gd32f470z_eval.h" /**************************************************************************** @@ -180,5 +193,167 @@ int gd32_bringup(void) } #endif +#ifdef CONFIG_GD32F4_ROMFS + /* Mount the romfs partition */ + + ret = gd32_romfs_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount romfs at %s: %d\n", + CONFIG_GD32F4_ROMFS_MOUNTPOINT, ret); + } +#endif + +#ifndef CONFIG_DISABLE_MOUNTPOINT + +# ifdef CONFIG_GD32F4_PROGMEM + + /* Create an instance of the GD32F4 FLASH program memory + * device driver + */ + + struct mtd_dev_s *mtd = progmem_initialize(); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: progmem_initialize failed\n"); + } + +# if defined(CONFIG_FS_NXFFS) + /* Initialize to provide NXFFS on the MTD interface */ + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: NXFFS initialization failed: %d\n", + ret); + } + + /* Mount the file system */ + + ret = nx_mount(NULL, CONFIG_GD32F4_NXFFS_MOUNTPT, "nxffs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the NXFFS volume: %d\n", + ret); + } +# elif defined(CONFIG_FS_LITTLEFS) + /* Initialize to provide LittleFS on the MTD interface */ + + ret = register_mtddriver("/dev/fmc", mtd, 0755, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); + return ret; + } + + /* Mount the file system at /mnt/fmc */ + + ret = nx_mount("/dev/fmc", "/mnt/fmc", "littlefs", 0, NULL); + if (ret < 0) + { + ret = nx_mount("/dev/fmc", "/mnt/fmc", "littlefs", 0, + "forceformat"); + if (ret < 0) + { + ferr("ERROR: Failed to mount the FS volume: %d\n", ret); + return ret; + } + } + + syslog(LOG_INFO, "INFO: LittleFS volume /mnt/fmc mount " + "on chip flash success: %d\n", ret); +# endif +# endif + +# ifdef HAVE_GD25 + + ret = gd32_gd25_automount(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the NXFFS \ + volume on spi flash: %d\n", ret); + } + +# endif + +# ifdef HAVE_AT24 + + ret = gd32_at24_wr_test(AT24_MINOR); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: I2C EEPROM write and read test fail: \ + %d\n", ret); + } + +# endif + +#endif /* CONFIG_FS_NXFFS */ + +#ifdef CONFIG_DEV_GPIO + /* Register the GPIO driver */ + + ret = gd32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS +#ifdef CONFIG_INPUT_BUTTONS_LOWER + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + return ret; + } +#else + /* Enable BUTTON support for some other purpose */ + + board_button_initialize(); +#endif /* CONFIG_INPUT_BUTTONS_LOWER */ +#endif /* CONFIG_INPUT_BUTTONS */ + +#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER) + /* Register the LED driver */ + + ret = userled_lower_initialize(LED_DRIVER_PATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", + ret); + } +#endif + + /* Configure SDIO chip selects */ + +#ifdef CONFIG_ARCH_HAVE_SDIO + ret = gd32_sdio_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: gd32_sdio_initialize() failed: %d\n", ret); + return ret; + } + + /* Mount the file system at /mnt/sd */ + + ret = nx_mount("/dev/mmcsd0", "/mnt/sd", "vfat", 0, NULL); + if (ret < 0) + { + ret = nx_mount("/dev/mmcsd0", "/mnt/sd", "vfat", 0, + "forceformat"); + if (ret < 0) + { + ferr("ERROR: Failed to mount the SD card: %d\n", ret); + return ret; + } + } + + syslog(LOG_INFO, "INFO: FAT volume /mnt/sd mount " + "sd card success: %d\n", ret); +#endif return ret; } diff --git a/boards/arm/imx6/sabre-6quad/configs/netnsh/defconfig b/boards/arm/imx6/sabre-6quad/configs/netnsh/defconfig index 6ca06d76b90c7..b509ce82fa46f 100644 --- a/boards/arm/imx6/sabre-6quad/configs/netnsh/defconfig +++ b/boards/arm/imx6/sabre-6quad/configs/netnsh/defconfig @@ -66,6 +66,7 @@ CONFIG_INTELHEX_BINARY=y CONFIG_IOB_BUFSIZE=1514 CONFIG_IOB_THROTTLE=16 CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBUV=y CONFIG_LIBUV_THREAD_STACKSIZE=3072 CONFIG_NET=y @@ -102,6 +103,7 @@ CONFIG_NSH_READLINE=y CONFIG_PATH_INITIAL="/system/bin" CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=3072 CONFIG_PREALLOC_TIMERS=4 +CONFIG_PSEUDOTERM=y CONFIG_RAM_SIZE=1073741824 CONFIG_RAM_START=0x10000000 CONFIG_RAM_VSTART=0x10000000 diff --git a/boards/arm/imx6/sabre-6quad/configs/netnsh_wb/defconfig b/boards/arm/imx6/sabre-6quad/configs/netnsh_wb/defconfig index 0e31325f83f41..8e50980c187b1 100644 --- a/boards/arm/imx6/sabre-6quad/configs/netnsh_wb/defconfig +++ b/boards/arm/imx6/sabre-6quad/configs/netnsh_wb/defconfig @@ -66,6 +66,7 @@ CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_IOB_BUFSIZE=1514 CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBUV=y CONFIG_LIBUV_THREAD_STACKSIZE=3072 CONFIG_NET=y @@ -104,6 +105,7 @@ CONFIG_NSH_READLINE=y CONFIG_PATH_INITIAL="/system/bin" CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=3072 CONFIG_PREALLOC_TIMERS=4 +CONFIG_PSEUDOTERM=y CONFIG_RAM_SIZE=1073741824 CONFIG_RAM_START=0x10000000 CONFIG_RAM_VSTART=0x10000000 diff --git a/boards/arm/imx6/sabre-6quad/scripts/dramboot.ld b/boards/arm/imx6/sabre-6quad/scripts/dramboot.ld index 66da05a575348..ab880dba6ca87 100644 --- a/boards/arm/imx6/sabre-6quad/scripts/dramboot.ld +++ b/boards/arm/imx6/sabre-6quad/scripts/dramboot.ld @@ -91,6 +91,13 @@ SECTIONS _edata = ABSOLUTE(.); } > ddr3 + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > ddr3 + .bss : { _sbss = ABSOLUTE(.); @@ -101,13 +108,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > ddr3 - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > ddr3 - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/imxrt/imxrt1060-evk/configs/lvgl/defconfig b/boards/arm/imxrt/imxrt1060-evk/configs/lvgl/defconfig index 6efe715202c60..2410b1e545681 100644 --- a/boards/arm/imxrt/imxrt1060-evk/configs/lvgl/defconfig +++ b/boards/arm/imxrt/imxrt1060-evk/configs/lvgl/defconfig @@ -44,13 +44,13 @@ CONFIG_INPUT=y CONFIG_INPUT_FT5X06=y CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_LV_MEM_CUSTOM=y -CONFIG_LV_PORT_USE_FBDEV=y -CONFIG_LV_PORT_USE_TOUCHPAD=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y CONFIG_LV_USE_DEMO_WIDGETS=y CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y CONFIG_MOTOROLA_SREC=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/imxrt/imxrt1064-evk/configs/knsh/Make.defs b/boards/arm/imxrt/imxrt1064-evk/configs/knsh/Make.defs index 81d5f340ecf9a..ae463b76ec0cc 100644 --- a/boards/arm/imxrt/imxrt1064-evk/configs/knsh/Make.defs +++ b/boards/arm/imxrt/imxrt1064-evk/configs/knsh/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/imxrt/imxrt1060-evk/configs/knsh/Make.defs +# boards/arm/imxrt/imxrt1064-evk/configs/knsh/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm/imxrt/imxrt1064-evk/configs/lvgl/defconfig b/boards/arm/imxrt/imxrt1064-evk/configs/lvgl/defconfig index ec0381a06c1a4..bddab67555aa0 100644 --- a/boards/arm/imxrt/imxrt1064-evk/configs/lvgl/defconfig +++ b/boards/arm/imxrt/imxrt1064-evk/configs/lvgl/defconfig @@ -46,13 +46,13 @@ CONFIG_INPUT=y CONFIG_INPUT_FT5X06=y CONFIG_INTELHEX_BINARY=y CONFIG_LPUART1_SERIAL_CONSOLE=y -CONFIG_LV_MEM_CUSTOM=y -CONFIG_LV_PORT_USE_FBDEV=y -CONFIG_LV_PORT_USE_TOUCHPAD=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y CONFIG_LV_USE_DEMO_WIDGETS=y CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y CONFIG_MOTOROLA_SREC=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/imxrt/imxrt1170-evk/configs/knsh/Make.defs b/boards/arm/imxrt/imxrt1170-evk/configs/knsh/Make.defs index 81d5f340ecf9a..cc76a9bf22317 100644 --- a/boards/arm/imxrt/imxrt1170-evk/configs/knsh/Make.defs +++ b/boards/arm/imxrt/imxrt1170-evk/configs/knsh/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/imxrt/imxrt1060-evk/configs/knsh/Make.defs +# boards/arm/imxrt/imxrt1170-evk/configs/knsh/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm/imxrt/teensy-4.x/configs/pikron-bb/defconfig b/boards/arm/imxrt/teensy-4.x/configs/pikron-bb/defconfig index 9eeb882f7b553..621a85a396f5f 100644 --- a/boards/arm/imxrt/teensy-4.x/configs/pikron-bb/defconfig +++ b/boards/arm/imxrt/teensy-4.x/configs/pikron-bb/defconfig @@ -123,7 +123,6 @@ CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_LINELEN=64 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_NXFONTS_DISABLE_16BPP=y CONFIG_NXFONTS_DISABLE_1BPP=y CONFIG_NXFONTS_DISABLE_24BPP=y diff --git a/boards/arm/kl/teensy-lc/include/board.h b/boards/arm/kl/teensy-lc/include/board.h index b7eb3a19b0d6d..0c9eb87ea8ddb 100644 --- a/boards/arm/kl/teensy-lc/include/board.h +++ b/boards/arm/kl/teensy-lc/include/board.h @@ -83,22 +83,22 @@ /* TPM0 Channels */ -#define GPIO_TPM0_CH0OUT PIN_TPM0_CH0_2 // Pin 22: PTC1 -#define GPIO_TPM0_CH1OUT PIN_TPM0_CH1_2 // Pin 23: PTC2 -#define GPIO_TPM0_CH2OUT PIN_TPM0_CH2_2 // Pin 9: PTC3 -#define GPIO_TPM0_CH3OUT PIN_TPM0_CH3_1 // Pin 10: PTC4 -#define GPIO_TPM0_CH4OUT PIN_TPM0_CH4_2 // Pin 6: PTD4 -#define GPIO_TPM0_CH5OUT PIN_TPM0_CH5_3 // Pin 20: PTD5 +#define GPIO_TPM0_CH0OUT PIN_TPM0_CH0_2 /* Pin 22: PTC1 */ +#define GPIO_TPM0_CH1OUT PIN_TPM0_CH1_2 /* Pin 23: PTC2 */ +#define GPIO_TPM0_CH2OUT PIN_TPM0_CH2_2 /* Pin 9: PTC3 */ +#define GPIO_TPM0_CH3OUT PIN_TPM0_CH3_1 /* Pin 10: PTC4 */ +#define GPIO_TPM0_CH4OUT PIN_TPM0_CH4_2 /* Pin 6: PTD4 */ +#define GPIO_TPM0_CH5OUT PIN_TPM0_CH5_3 /* Pin 20: PTD5 */ /* TPM1 Channels */ -#define GPIO_TPM1_CH0OUT PIN_TPM1_CH0_2 // Pin 16: PTB0 -#define GPIO_TPM1_CH1OUT PIN_TPM1_CH1_2 // Pin 17: PTB1 +#define GPIO_TPM1_CH0OUT PIN_TPM1_CH0_2 /* Pin 16: PTB0 */ +#define GPIO_TPM1_CH1OUT PIN_TPM1_CH1_2 /* Pin 17: PTB1 */ /* TPM2 Channels */ -#define GPIO_TPM2_CH0OUT PIN_TPM2_CH0_1 // Pin 3: PTA1 -#define GPIO_TPM2_CH1OUT PIN_TPM2_CH1_1 // Pin 4: PTA2 +#define GPIO_TPM2_CH0OUT PIN_TPM2_CH0_1 /* Pin 3: PTA1 */ +#define GPIO_TPM2_CH1OUT PIN_TPM2_CH1_1 /* Pin 4: PTA2 */ /* LED definitions **********************************************************/ @@ -122,12 +122,12 @@ * LED. Use pin 14 instead. */ -#define PIN_SPI0_SCK (PIN_SPI0_SCK_3 | PIN_ALT2_PULLUP) // Pin 14: PTD1 -#define PIN_SPI0_MISO (PIN_SPI0_MISO_4 | PIN_ALT2_PULLUP) // Pin 12: PTC7 -#define PIN_SPI0_MOSI (PIN_SPI0_MOSI_3 | PIN_ALT2_PULLUP) // Pin 11: PTC6 +#define PIN_SPI0_SCK (PIN_SPI0_SCK_3 | PIN_ALT2_PULLUP) /* Pin 14: PTD1 */ +#define PIN_SPI0_MISO (PIN_SPI0_MISO_4 | PIN_ALT2_PULLUP) /* Pin 12: PTC7 */ +#define PIN_SPI0_MOSI (PIN_SPI0_MOSI_3 | PIN_ALT2_PULLUP) /* Pin 11: PTC6 */ -#define PIN_SPI1_SCK (PIN_SPI1_SCK_2 | PIN_ALT2_PULLUP) // Pin 20: PTD5 -#define PIN_SPI1_MISO (PIN_SPI1_MISO_2 | PIN_ALT2_PULLUP) // Pin 1: PTB17 -#define PIN_SPI1_MOSI (PIN_SPI0_MOSI_1 | PIN_ALT2_PULLUP) // Pin 0: PTB16 +#define PIN_SPI1_SCK (PIN_SPI1_SCK_2 | PIN_ALT2_PULLUP) /* Pin 20: PTD5 */ +#define PIN_SPI1_MISO (PIN_SPI1_MISO_2 | PIN_ALT2_PULLUP) /* Pin 1: PTB17 */ +#define PIN_SPI1_MOSI (PIN_SPI0_MOSI_1 | PIN_ALT2_PULLUP) /* Pin 0: PTB16 */ #endif /* __BOARDS_ARM_KL_TEENSY_LC_INCLUDE_BOARD_H */ diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/configs/nsh/defconfig b/boards/arm/lpc17xx_40xx/lx_cpu/configs/nsh/defconfig index 0d23ad5f661c7..799787de64fb0 100644 --- a/boards/arm/lpc17xx_40xx/lx_cpu/configs/nsh/defconfig +++ b/boards/arm/lpc17xx_40xx/lx_cpu/configs/nsh/defconfig @@ -21,6 +21,7 @@ CONFIG_ARCH_RAMVECTORS=y CONFIG_ARCH_STACKDUMP=y CONFIG_BOARDCTL_APP_SYMTAB=y CONFIG_BOARDCTL_RESET=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=11934 CONFIG_BOOT_RUNFROMSDRAM=y CONFIG_BUILTIN=y @@ -125,7 +126,6 @@ CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_NXFLAT=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PRIORITY_INHERITANCE=y diff --git a/boards/arm/lpc17xx_40xx/lx_cpu/tools/oocd.sh b/boards/arm/lpc17xx_40xx/lx_cpu/tools/oocd.sh index d71e44b62258d..dd7b5eb8d136c 100644 --- a/boards/arm/lpc17xx_40xx/lx_cpu/tools/oocd.sh +++ b/boards/arm/lpc17xx_40xx/lx_cpu/tools/oocd.sh @@ -1,6 +1,6 @@ #!/bin/sh # -# See boards/arm/lpc17xx_40xx/lx_cpu/README.txt for information about +# See Documentation/platforms/arm/lpc40xx/boards/lx_cpu/README.txt for information about # this file. TOPDIR=$1 diff --git a/boards/arm/lpc214x/zp214xpa/tools/oocd.sh b/boards/arm/lpc214x/zp214xpa/tools/oocd.sh index 9360b9fe8cea8..0413aca4a55fa 100755 --- a/boards/arm/lpc214x/zp214xpa/tools/oocd.sh +++ b/boards/arm/lpc214x/zp214xpa/tools/oocd.sh @@ -1,6 +1,6 @@ #!/usr/bin/env bash # -# See boards/arm/lpc214x/zp214xpa/README.txt for information about +# See Documentation/platforms/arm/lpc214x/boards/zp214xpa/README.txt for information about # this file. TOPDIR=$1 diff --git a/boards/arm/lpc31xx/ea3131/configs/pgnsh/defconfig b/boards/arm/lpc31xx/ea3131/configs/pgnsh/defconfig index cf80de95b2f24..0aa1a3e572c51 100644 --- a/boards/arm/lpc31xx/ea3131/configs/pgnsh/defconfig +++ b/boards/arm/lpc31xx/ea3131/configs/pgnsh/defconfig @@ -19,9 +19,10 @@ CONFIG_BOARD_LOOPSPERMSEC=16945 CONFIG_BOOT_RUNFROMISRAM=y CONFIG_BUILD_2PASS=y CONFIG_DEFAULT_SMALL=y +CONFIG_EXPERIMENTAL=y CONFIG_FS_FAT=y -CONFIG_HOST_WINDOWS=y CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LEGACY_PAGING=y CONFIG_LPC31_SPI=y CONFIG_LPC31_UART=y CONFIG_M25P_SPIMODE=3 @@ -29,7 +30,6 @@ CONFIG_MMCSD=y CONFIG_MTD=y CONFIG_MTD_M25P=y CONFIG_NSH_ARCHINIT=y -CONFIG_PAGING=y CONFIG_PAGING_BLOCKINGFILL=y CONFIG_PAGING_NDATA=32 CONFIG_PAGING_NPPAGED=96 diff --git a/boards/arm/lpc31xx/ea3131/src/Makefile b/boards/arm/lpc31xx/ea3131/src/Makefile index 1a3cdaee019c9..c1217fb5d2368 100644 --- a/boards/arm/lpc31xx/ea3131/src/Makefile +++ b/boards/arm/lpc31xx/ea3131/src/Makefile @@ -42,7 +42,7 @@ ifeq ($(CONFIG_BOARDCTL),y) CSRCS += lpc31_appinit.c endif -ifeq ($(CONFIG_PAGING),y) +ifeq ($(CONFIG_LEGACY_PAGING),y) CSRCS += lpc31_fillpage.c endif diff --git a/boards/arm/lpc31xx/ea3131/src/ea3131.h b/boards/arm/lpc31xx/ea3131/src/ea3131.h index cb3f253462077..4d2d4e7f549d5 100644 --- a/boards/arm/lpc31xx/ea3131/src/ea3131.h +++ b/boards/arm/lpc31xx/ea3131/src/ea3131.h @@ -133,7 +133,7 @@ int lpc31_usbhost_initialize(void); * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING void weak_function lpc31_pginitialize(void); #endif diff --git a/boards/arm/lpc31xx/ea3131/src/lpc31_boot.c b/boards/arm/lpc31xx/ea3131/src/lpc31_boot.c index 3d3b939813a25..52fa4207fb726 100644 --- a/boards/arm/lpc31xx/ea3131/src/lpc31_boot.c +++ b/boards/arm/lpc31xx/ea3131/src/lpc31_boot.c @@ -108,7 +108,7 @@ void lpc31_boardinitialize(void) /* Set up mass storage device to support on demand paging */ -#if defined(CONFIG_PAGING) +#if defined(CONFIG_LEGACY_PAGING) if (lpc31_pginitialize) { lpc31_pginitialize(); diff --git a/boards/arm/lpc31xx/ea3131/src/lpc31_fillpage.c b/boards/arm/lpc31xx/ea3131/src/lpc31_fillpage.c index 95d04f9071e1f..f06e7aceb0ccf 100644 --- a/boards/arm/lpc31xx/ea3131/src/lpc31_fillpage.c +++ b/boards/arm/lpc31xx/ea3131/src/lpc31_fillpage.c @@ -31,7 +31,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING #ifdef CONFIG_PAGING_BINPATH # include # include @@ -520,4 +520,4 @@ void weak_function lpc31_pginitialize(void) */ } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/boards/arm/lpc31xx/ea3152/src/Makefile b/boards/arm/lpc31xx/ea3152/src/Makefile index 204429c3167f6..c42caa3d0d19b 100644 --- a/boards/arm/lpc31xx/ea3152/src/Makefile +++ b/boards/arm/lpc31xx/ea3152/src/Makefile @@ -36,7 +36,7 @@ endif ifeq ($(CONFIG_BOARDCTL),y) CSRCS += lpc31_appinit.c endif -ifeq ($(CONFIG_PAGING),y) +ifeq ($(CONFIG_LEGACY_PAGING),y) CSRCS += lpc31_fillpage.c endif diff --git a/boards/arm/lpc31xx/ea3152/src/ea3152.h b/boards/arm/lpc31xx/ea3152/src/ea3152.h index 576a72e04bd1d..acb76da85a761 100644 --- a/boards/arm/lpc31xx/ea3152/src/ea3152.h +++ b/boards/arm/lpc31xx/ea3152/src/ea3152.h @@ -103,7 +103,7 @@ void weak_function lpc31_usbinitialize(void); * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING void weak_function lpc31_pginitialize(void); #endif diff --git a/boards/arm/lpc31xx/ea3152/src/lpc31_boot.c b/boards/arm/lpc31xx/ea3152/src/lpc31_boot.c index 8a1bfeb1b4ff8..c6fc1e34f780c 100644 --- a/boards/arm/lpc31xx/ea3152/src/lpc31_boot.c +++ b/boards/arm/lpc31xx/ea3152/src/lpc31_boot.c @@ -95,7 +95,7 @@ void lpc31_boardinitialize(void) /* Set up mass storage device to support on demand paging */ -#if defined(CONFIG_PAGING) +#if defined(CONFIG_LEGACY_PAGING) if (lpc31_pginitialize) { lpc31_pginitialize(); diff --git a/boards/arm/lpc31xx/ea3152/src/lpc31_fillpage.c b/boards/arm/lpc31xx/ea3152/src/lpc31_fillpage.c index a5e214c94fdfd..46bb94187f7f8 100644 --- a/boards/arm/lpc31xx/ea3152/src/lpc31_fillpage.c +++ b/boards/arm/lpc31xx/ea3152/src/lpc31_fillpage.c @@ -31,7 +31,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING #ifdef CONFIG_PAGING_BINPATH # include # include @@ -523,4 +523,4 @@ void weak_function lpc31_pginitialize(void) */ } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/boards/arm/lpc31xx/olimex-lpc-h3131/tools/oocd.sh b/boards/arm/lpc31xx/olimex-lpc-h3131/tools/oocd.sh index 8162e3fc03ff5..938c731a0c892 100755 --- a/boards/arm/lpc31xx/olimex-lpc-h3131/tools/oocd.sh +++ b/boards/arm/lpc31xx/olimex-lpc-h3131/tools/oocd.sh @@ -1,6 +1,6 @@ #!/usr/bin/env bash # -# See boards/arm/lpc31xx/olimex-lpc-h3131/README.txt for information about +# See Documentation/platforms/arm/lpc31xx/boards/olimex-lpc-h3131/README.txt for information about # this file. TOPDIR=$1 diff --git a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/lvgl/defconfig b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/lvgl/defconfig index c55829eb9a009..514e39cd3b526 100644 --- a/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/lvgl/defconfig +++ b/boards/arm/lpc54xx/lpcxpresso-lpc54628/configs/lvgl/defconfig @@ -48,13 +48,13 @@ CONFIG_LPC54_LCD_VFRONTPORCH=4 CONFIG_LPC54_LCD_VPULSE=10 CONFIG_LPC54_LCD_VRAMBASE=0xa0000000 CONFIG_LPC54_USART0=y -CONFIG_LV_MEM_CUSTOM=y -CONFIG_LV_PORT_USE_FBDEV=y -CONFIG_LV_PORT_USE_TOUCHPAD=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y CONFIG_LV_USE_DEMO_WIDGETS=y CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y CONFIG_MM_REGIONS=2 CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=163840 diff --git a/boards/arm/mps/mps3-an547/Kconfig b/boards/arm/mps/mps3-an547/Kconfig new file mode 100644 index 0000000000000..5742f7270de57 --- /dev/null +++ b/boards/arm/mps/mps3-an547/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_MPS3_AN547 +endif diff --git a/boards/arm/mps/mps3-an547/README.txt b/boards/arm/mps/mps3-an547/README.txt new file mode 100644 index 0000000000000..6334b5e57532b --- /dev/null +++ b/boards/arm/mps/mps3-an547/README.txt @@ -0,0 +1,47 @@ +README.txt +========== + +This board configuration will use QEMU to emulate generic ARM v8-M series +hardware platform and provides support for these devices: + + - ARM Generic Timer + - CMSDK UART controller + +Contents +======== + - Getting Started + - Status + - Platform Features + - Debugging with QEMU + - FPU Support and Performance + - SMP Support + - References + +Getting Started +=============== + +1. Configuring and running + 1.1 Single Core + Configuring NuttX and compile: + $ ./tools/configure.sh -l mps3-an547:nsh + $ make + Running with qemu + $ qemu-system-arm -M mps3-an547 -nographic -kernel nuttx.bin + +Debugging with QEMU +=================== + +The nuttx ELF image can be debugged with QEMU. + +1. To debug the nuttx (ELF) with symbols, make sure the following change have + applied to defconfig. + ++CONFIG_DEBUG_SYMBOLS=y + +2. Run QEMU(at shell terminal 1) + + $ qemu-system-arm -M mps3-an547 -nographic -kernel nuttx.bin -S -s + +3. Run gdb with TUI, connect to QEMU, load nuttx and continue (at shell terminal 2) + + $ arm-none-eabi-gdb -tui --eval-command='target remote localhost:1234' nuttx diff --git a/boards/arm/mps/mps3-an547/configs/nsh/defconfig b/boards/arm/mps/mps3-an547/configs/nsh/defconfig new file mode 100644 index 0000000000000..63f915480bdad --- /dev/null +++ b/boards/arm/mps/mps3-an547/configs/nsh/defconfig @@ -0,0 +1,73 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="mps3-an547" +CONFIG_ARCH_BOARD_MPS3_AN547=y +CONFIG_ARCH_CHIP="mps" +CONFIG_ARCH_CHIP_MPS3_AN547=y +CONFIG_ARCH_CHIP_MPS=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARMV8M_SYSTICK=y +CONFIG_BUILTIN=y +CONFIG_CMSDK_UART0=y +CONFIG_CMSDK_UART0_BASE=0x49303000 +CONFIG_CMSDK_UART0_CLOCK=25000000 +CONFIG_CMSDK_UART0_OV_IRQ=59 +CONFIG_CMSDK_UART0_RX_IRQ=50 +CONFIG_CMSDK_UART0_SERIAL_CONSOLE=y +CONFIG_CMSDK_UART0_TX_IRQ=49 +CONFIG_CMSDK_UART=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SCHED=y +CONFIG_DEBUG_SCHED_ERROR=y +CONFIG_DEBUG_SCHED_INFO=y +CONFIG_DEBUG_SCHED_WARN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_TASK_STACKSIZE=4096 +CONFIG_DEV_ZERO=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_FS_TMPFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=4096 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBC_MEMFD_ERROR=y +CONFIG_MM_REGIONS=2 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAM_SIZE=2097152 +CONFIG_RAM_START=0x01000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SPINLOCK=y +CONFIG_STACK_COLORATION=y +CONFIG_STANDARD_SERIAL=y +CONFIG_START_DAY=25 +CONFIG_START_MONTH=4 +CONFIG_START_YEAR=2023 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_SYSTEM=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_TIMER=y +CONFIG_TIMER_ARCH=y +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/mps/mps3-an547/include/board.h b/boards/arm/mps/mps3-an547/include/board.h new file mode 100644 index 0000000000000..3109285a2bbc3 --- /dev/null +++ b/boards/arm/mps/mps3-an547/include/board.h @@ -0,0 +1,61 @@ +/**************************************************************************** + * boards/arm/mps/mps3-an547/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_MPS_MPS3_AN547_INCLUDE_BOARD_H +#define __BOARDS_ARM_MPS_MPS3_AN547_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MPS_SYSTICK_CLOCK (32 * 1000 * 1000) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_MPS_MPS3_AN547_INCLUDE_BOARD_H */ diff --git a/boards/arm/mps/mps3-an547/scripts/Make.defs b/boards/arm/mps/mps3-an547/scripts/Make.defs new file mode 100644 index 0000000000000..a391bf4768c20 --- /dev/null +++ b/boards/arm/mps/mps3-an547/scripts/Make.defs @@ -0,0 +1,45 @@ +############################################################################ +# boards/arm/mps/mps3-an547/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv8-m/Toolchain.defs + +LDSCRIPT = flash.ld + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +# NXFLAT module definitions + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# ELF module definitions + +LDELFFLAGS = -r -e main +LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/binfmt/libelf/gnu-elf.ld) diff --git a/boards/arm/mps/mps3-an547/scripts/flash.ld b/boards/arm/mps/mps3-an547/scripts/flash.ld new file mode 100644 index 0000000000000..b41e17a0e2e67 --- /dev/null +++ b/boards/arm/mps/mps3-an547/scripts/flash.ld @@ -0,0 +1,119 @@ +/**************************************************************************** + * boards/arm/mps/mps3-an547/scripts/flash.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x00000000, LENGTH = 512K + sram1 (rwx) : ORIGIN = 0x01000000, LENGTH = 2M + sram2 (rwx) : ORIGIN = 0x22000000, LENGTH = 2M +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(__start) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : ALIGN(4) { + *(.ARM.extab*) + } > flash + + .ARM.exidx : ALIGN(4) { + __exidx_start = ABSOLUTE(.); + *(.ARM.exidx*) + __exidx_end = ABSOLUTE(.); + } > flash + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } > flash + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + /* The RAM vector table (if present) should lie at the beginning of SRAM */ + + .ram_vectors : { + *(.ram_vectors) + } > sram1 + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram1 AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram1 + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/mps/mps3-an547/src/Makefile b/boards/arm/mps/mps3-an547/src/Makefile new file mode 100644 index 0000000000000..59ae8876b5dfb --- /dev/null +++ b/boards/arm/mps/mps3-an547/src/Makefile @@ -0,0 +1,25 @@ +############################################################################ +# boards/arm/mps/mps3-an547/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = mps3_bringup.c + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/mps/mps3-an547/src/mps3_bringup.c b/boards/arm/mps/mps3-an547/src/mps3_bringup.c new file mode 100644 index 0000000000000..95f975c6fb3f0 --- /dev/null +++ b/boards/arm/mps/mps3-an547/src/mps3_bringup.c @@ -0,0 +1,130 @@ +/**************************************************************************** + * boards/arm/mps/mps3-an547/src/mps3_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: mps3_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +static int mps3_bringup(void) +{ + int ret = 0; + +#ifdef CONFIG_FS_PROCFS + + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } + +#endif + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_intitialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board initialization */ + + mps3_bringup(); +} +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + UNUSED(arg); +#ifndef CONFIG_BOARD_LATE_INITIALIZE + + /* Perform board initialization */ + + return mps3_bringup(); +#else + return OK; +#endif +} + diff --git a/boards/arm/mx8mp/verdin-mx8mp/Kconfig b/boards/arm/mx8mp/verdin-mx8mp/Kconfig index f72f3c094ce4c..266805d38ca38 100644 --- a/boards/arm/mx8mp/verdin-mx8mp/Kconfig +++ b/boards/arm/mx8mp/verdin-mx8mp/Kconfig @@ -2,3 +2,9 @@ # For a description of the syntax of this configuration file, # see the file kconfig-language.txt in the NuttX tools repository. # + +config MX8MP_RUN_FROM_ITCM + bool "Run from Instruction Tightly Coupled Memory (ITCM)" + default n + ---help--- + Run software from ITCM instead of DDR memory \ No newline at end of file diff --git a/boards/arm/mx8mp/verdin-mx8mp/configs/rpmsg/defconfig b/boards/arm/mx8mp/verdin-mx8mp/configs/rpmsg/defconfig new file mode 100644 index 0000000000000..2d314132da26e --- /dev/null +++ b/boards/arm/mx8mp/verdin-mx8mp/configs/rpmsg/defconfig @@ -0,0 +1,73 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_ARCH_RAMFUNCS is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="verdin-mx8mp" +CONFIG_ARCH_BOARD_VERDIN_MX8MP=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="mx8mp" +CONFIG_ARCH_CHIP_MX8MP=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_ARM_MPU=y +CONFIG_BOARD_LOOPSPERMSEC=159972 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_RPMSG=y +CONFIG_DEV_SIMPLE_ADDRENV=y +CONFIG_FS_PROCFS=y +CONFIG_I2CTOOL_MAXADDR=0x7f +CONFIG_I2CTOOL_MAXBUS=6 +CONFIG_I2CTOOL_MINADDR=0x00 +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_I2C_RESET=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_LOCALE=y +CONFIG_MX8MP_I2C4=y +CONFIG_MX8MP_I2C=y +CONFIG_MX8MP_RUN_FROM_ITCM=y +CONFIG_MX8MP_UART4=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFCONFIG=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_PS=y +CONFIG_NSH_DISABLE_RPTUN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RPMSG_UART=y +CONFIG_RPMSG_UART_CONSOLE=y +CONFIG_RPTUN=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_START_DAY=10 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2014 +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_RAMTEST=y +CONFIG_UART4_SERIAL_CONSOLE=y diff --git a/boards/arm/mx8mp/verdin-mx8mp/scripts/Make.defs b/boards/arm/mx8mp/verdin-mx8mp/scripts/Make.defs index a4da6f694dee0..636d403e20afa 100644 --- a/boards/arm/mx8mp/verdin-mx8mp/scripts/Make.defs +++ b/boards/arm/mx8mp/verdin-mx8mp/scripts/Make.defs @@ -22,7 +22,12 @@ include $(TOPDIR)/.config include $(TOPDIR)/tools/Config.mk include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs +ifeq ($(CONFIG_MX8MP_RUN_FROM_ITCM),y) +LDSCRIPT = itcm.ld +else LDSCRIPT = ddr.ld +endif + ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 diff --git a/boards/arm/mx8mp/verdin-mx8mp/scripts/ddr.ld b/boards/arm/mx8mp/verdin-mx8mp/scripts/ddr.ld index 7924ba0d20d0b..2b9145471b0aa 100644 --- a/boards/arm/mx8mp/verdin-mx8mp/scripts/ddr.ld +++ b/boards/arm/mx8mp/verdin-mx8mp/scripts/ddr.ld @@ -41,6 +41,7 @@ SECTIONS { .text : { _stext = ABSOLUTE(.); + . = ALIGN(4); *(.vectors) *(.text .text.*) *(.fixup) @@ -55,6 +56,13 @@ SECTIONS _etext = ABSOLUTE(.); } > flash + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) + . = ALIGN(4); + } > flash + .init_section : { _sinit = ABSOLUTE(.); KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) diff --git a/boards/arm/mx8mp/verdin-mx8mp/scripts/itcm.ld b/boards/arm/mx8mp/verdin-mx8mp/scripts/itcm.ld index 8522ff443b4f3..49c9f66afb614 100644 --- a/boards/arm/mx8mp/verdin-mx8mp/scripts/itcm.ld +++ b/boards/arm/mx8mp/verdin-mx8mp/scripts/itcm.ld @@ -39,6 +39,7 @@ SECTIONS { .text : { _stext = ABSOLUTE(.); + . = ALIGN(4); *(.vectors) *(.text .text.*) *(.fixup) @@ -53,6 +54,13 @@ SECTIONS _etext = ABSOLUTE(.); } > flash + .resource_table : + { + . = ALIGN(8); + KEEP(*(.resource_table)) + . = ALIGN(4); + } > flash + .init_section : { _sinit = ABSOLUTE(.); KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) diff --git a/boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_bringup.c b/boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_bringup.c index 205d6a8625b1b..00db1f851830d 100644 --- a/boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_bringup.c +++ b/boards/arm/mx8mp/verdin-mx8mp/src/mx8mp_bringup.c @@ -25,7 +25,6 @@ #include #include #include - #include #include "verdin-mx8mp.h" @@ -35,10 +34,29 @@ # include "mx8mp_ina219.h" #endif +#ifdef CONFIG_MX8MP_RPMSG +# include +#endif + +#ifdef CONFIG_RPMSG_UART +# include +#endif + +#ifdef CONFIG_FS_PROCFS +# include +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ +#ifdef CONFIG_RPMSG_UART +void rpmsg_serialinit(void) +{ + uart_rpmsg_init("netcore", "proxy", 4096, true); +} +#endif + /**************************************************************************** * Name: mx8mp_bringup * @@ -51,6 +69,10 @@ int mx8mp_bringup(void) { int ret = OK; +#ifdef CONFIG_MX8MP_RPMSG + mx8mp_rptun_init("imx8mp-shmem", "netcore"); +#endif /* CONFIG_MX8MP_RPMSG */ + #if defined(CONFIG_USERLED) && !defined(CONFIG_ARCH_LEDS) #ifdef CONFIG_USERLED_LOWER /* Register the LED driver */ diff --git a/boards/arm/nrf52/common/include/nrf52_ieee802154.h b/boards/arm/nrf52/common/include/nrf52_ieee802154.h new file mode 100644 index 0000000000000..187348bf9eb6a --- /dev/null +++ b/boards/arm/nrf52/common/include/nrf52_ieee802154.h @@ -0,0 +1,50 @@ +/**************************************************************************** + * boards/arm/nrf52/common/include/nrf52_ieee802154.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_NRF52_COMMON_INCLUDE_NRF52_IEEE802154_H +#define __BOARDS_ARM_NRF52_COMMON_INCLUDE_NRF52_IEEE802154_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_ieee802154_initialize + * + * Description: + * Initialize IEEE802154 network. + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_NRF52_RADIO_IEEE802154 +int nrf52_ieee802154_initialize(void); +#endif + +#endif /* __BOARDS_ARM_NRF52_COMMON_INCLUDE_NRF52_IEEE802154_H */ diff --git a/boards/arm/nrf52/common/include/nrf52_mrf24j40.h b/boards/arm/nrf52/common/include/nrf52_mrf24j40.h new file mode 100644 index 0000000000000..cde0af36881c9 --- /dev/null +++ b/boards/arm/nrf52/common/include/nrf52_mrf24j40.h @@ -0,0 +1,67 @@ +/**************************************************************************** + * boards/arm/nrf52/common/include/nrf52_mrf24j40.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_NRF52_COMMON_INCLUDE_NRF52_MRF24J40_H +#define __BOARDS_ARM_NRF52_COMMON_INCLUDE_NRF52_MRF24J40_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct nrf52_mrf24j40_s +{ + struct mrf24j40_lower_s dev; + xcpt_t handler; + void *arg; + uint32_t intcfg; + uint8_t spidev; +}; + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_mrf24j40_devsetup + * + * Description: + * Initialize one the MRF24J40 device in one mikroBUS slot + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_IEEE802154_MRF24J40 +int nrf52_mrf24j40_devsetup(struct nrf52_mrf24j40_s *priv); +#endif + +#endif /* __BOARDS_ARM_NRF52_COMMON_INCLUDE_NRF52_MRF24J40_H */ diff --git a/boards/arm/nrf52/common/include/nrf52_progmem.h b/boards/arm/nrf52/common/include/nrf52_progmem.h index a26d211f988ff..f4dfab7dda26d 100644 --- a/boards/arm/nrf52/common/include/nrf52_progmem.h +++ b/boards/arm/nrf52/common/include/nrf52_progmem.h @@ -32,7 +32,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: nrf52_mtd_initialize + * Name: nrf52_progmem_init * * Description: * Initialize MTD drivers. diff --git a/boards/arm/nrf52/common/src/CMakeLists.txt b/boards/arm/nrf52/common/src/CMakeLists.txt index 7c3d75b759068..ade42fdd19d7c 100644 --- a/boards/arm/nrf52/common/src/CMakeLists.txt +++ b/boards/arm/nrf52/common/src/CMakeLists.txt @@ -36,6 +36,18 @@ if(CONFIG_ARCH_BOARD_COMMON) list(APPEND SRCS nrf52_lsm9ds1.c) endif() + if(CONFIG_BOARDCTL_RESET) + list(APPEND SRCS nrf52_reset.c) + endif() + + if(CONFIG_NRF52_RADIO_IEEE802154) + list(APPEND SRCS nrf52_ieee802154.c) + endif() + + if(CONFIG_IEEE802154_MRF24J40) + list(APPEND SRCS nrf52_mrf24j40.c) + endif() + target_sources(board PRIVATE ${SRCS}) endif() diff --git a/boards/arm/nrf52/common/src/Make.defs b/boards/arm/nrf52/common/src/Make.defs index 07994dc14a707..90031c5cf2f14 100644 --- a/boards/arm/nrf52/common/src/Make.defs +++ b/boards/arm/nrf52/common/src/Make.defs @@ -36,6 +36,18 @@ ifeq ($(CONFIG_SENSORS_LSM9DS1),y) CSRCS += nrf52_lsm9ds1.c endif +ifeq ($(CONFIG_BOARDCTL_RESET),y) +CSRCS += nrf52_reset.c +endif + +ifeq ($(CONFIG_NRF52_RADIO_IEEE802154),y) +CSRCS += nrf52_ieee802154.c +endif + +ifeq ($(CONFIG_IEEE802154_MRF24J40),y) +CSRCS += nrf52_mrf24j40.c +endif + DEPPATH += --dep-path src VPATH += :src CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src diff --git a/boards/arm/nrf52/common/src/nrf52_ieee802154.c b/boards/arm/nrf52/common/src/nrf52_ieee802154.c new file mode 100644 index 0000000000000..d2dcedd086162 --- /dev/null +++ b/boards/arm/nrf52/common/src/nrf52_ieee802154.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * boards/arm/nrf52/common/src/nrf52_ieee802154.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "nrf52_radio_ieee802154.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_ieee802154_initialize + * + * Description: + * Initialize the IEEE 802.15.4 network. + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int nrf52_ieee802154_initialize(void) +{ + struct ieee802154_radio_s *radio; + MACHANDLE mac; + int ret; + + /* Initialize and register the SPI MRF24J40 device */ + + radio = nrf52_radioi8_register(NULL); + if (radio == NULL) + { + wlerr("ERROR: Failed to initialize radio\n"); + return -ENODEV; + } + + /* Create a 802.15.4 MAC device from a 802.15.4 compatible radio device. */ + + mac = mac802154_create(radio); + if (mac == NULL) + { + wlerr("ERROR: Failed to initialize IEEE802.15.4 MAC\n"); + return -ENODEV; + } + +#ifdef CONFIG_IEEE802154_NETDEV + /* Use the IEEE802.15.4 MAC interface instance to create a 6LoWPAN + * network interface by wrapping the MAC intrface instance in a + * network device driver via mac802154dev_register(). + */ + + ret = mac802154netdev_register(mac); + if (ret < 0) + { + wlerr("ERROR: Failed to register the MAC network driver wpan%d: %d\n", + 0, ret); + return ret; + } +#endif + +#ifdef CONFIG_IEEE802154_MACDEV + /* If want to call these APIs from userspace, you have to wrap the MAC + * interface in a character device viamac802154dev_register(). + */ + + ret = mac802154dev_register(mac, 0); + if (ret < 0) + { + wlerr("ERROR:"); + wlerr(" Failed to register the MAC character driver /dev/ieee%d: %d\n", + 0, ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/nrf52/common/src/nrf52_lsm9ds1.c b/boards/arm/nrf52/common/src/nrf52_lsm9ds1.c index af6ba01b3d2d9..df22f74b2324a 100644 --- a/boards/arm/nrf52/common/src/nrf52_lsm9ds1.c +++ b/boards/arm/nrf52/common/src/nrf52_lsm9ds1.c @@ -54,6 +54,39 @@ int nrf52_lsm9ds1_initialize(int bus) { +#ifdef CONFIG_SENSORS_LSM9DS1_UORB + struct lsm9ds1_config_s config; + struct i2c_master_s *i2c; + int ret = OK; + + sninfo("Initializing LMS6DSL!\n"); + + i2c = nrf52_i2cbus_initialize(bus); + if (i2c == NULL) + { + return -ENODEV; + } + + sninfo("INFO: Initializing LMS9DS1 9DoF sensor over I2C%d\n", bus); + + config.i2c = i2c; + config.addr_acc = LSM9DS1ACCEL_ADDR1; + config.addr_gyro = LSM9DS1GYRO_ADDR1; + config.addr_mag = LSM9DS1MAG_ADDR1; + + /* Register sensor as uorb devices */ + + ret = lsm9ds1_register_uorb(0, &config); + if (ret < 0) + { + snerr("ERROR: Failed to initialize LMS9DS1 mag driver\n"); + return -ENODEV; + } + + sninfo("INFO: LMS9DS1 sensor has been initialized successfully\n"); + + return ret; +#else struct i2c_master_s *i2c; int ret = OK; @@ -67,7 +100,7 @@ int nrf52_lsm9ds1_initialize(int bus) sninfo("INFO: Initializing LMS9DS1 9DoF sensor over I2C%d\n", bus); - /* Register snesors as character devices */ + /* Register sensor as character devices */ ret = lsm9ds1mag_register(LSM9DS1MAG_DEVPATH, i2c, LSM9DS1MAG_ADDR1); if (ret < 0) @@ -94,4 +127,5 @@ int nrf52_lsm9ds1_initialize(int bus) } return ret; +#endif } diff --git a/boards/arm/nrf52/common/src/nrf52_mrf24j40.c b/boards/arm/nrf52/common/src/nrf52_mrf24j40.c new file mode 100644 index 0000000000000..dcfbf40840f34 --- /dev/null +++ b/boards/arm/nrf52/common/src/nrf52_mrf24j40.c @@ -0,0 +1,136 @@ +/**************************************************************************** + * boards/arm/nrf52/common/src/nrf52_mrf24j40.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "nrf52_gpio.h" +#include "nrf52_spi.h" + +#include "nrf52_mrf24j40.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_DRIVERS_WIRELESS +# error Wireless support requires CONFIG_DRIVERS_WIRELESS +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_mrf24j40_devsetup + * + * Description: + * Initialize one the MRF24J40 device in one mikroBUS slot + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int nrf52_mrf24j40_devsetup(struct nrf52_mrf24j40_s *priv) +{ + struct ieee802154_radio_s *radio; + MACHANDLE mac; + struct spi_dev_s *spi; + int ret; + + /* Configure pins */ + + nrf52_gpio_config(priv->intcfg); + + /* Initialize the SPI bus and get an instance of the SPI interface */ + + spi = nrf52_spibus_initialize(priv->spidev); + if (spi == NULL) + { + wlerr("Failed to initialize SPI bus %d\n", priv->spidev); + return -ENODEV; + } + + /* Initialize and register the SPI MRF24J40 device */ + + radio = mrf24j40_init(spi, &priv->dev); + if (radio == NULL) + { + wlerr("Failed to initialize SPI bus %d\n", priv->spidev); + return -ENODEV; + } + + /* Create a 802.15.4 MAC device from a 802.15.4 compatible radio device. */ + + mac = mac802154_create(radio); + if (mac == NULL) + { + wlerr("Failed to initialize IEEE802.15.4 MAC\n"); + return -ENODEV; + } + +#ifdef CONFIG_IEEE802154_NETDEV + /* Use the IEEE802.15.4 MAC interface instance to create a 6LoWPAN + * network interface by wrapping the MAC intrface instance in a + * network device driver via mac802154dev_register(). + */ + + ret = mac802154netdev_register(mac); + if (ret < 0) + { + wlerr("Failed to register the MAC network driver wpan%d: %d\n", + 0, ret); + return ret; + } +#endif + +#ifdef CONFIG_IEEE802154_MACDEV + /* If want to call these APIs from userspace, you have to wrap the MAC + * interface in a character device viamac802154dev_register(). + */ + + ret = mac802154dev_register(mac, 0); + if (ret < 0) + { + wlerr("Failed to register the MAC character driver /dev/ieee%d: %d\n", + 0, ret); + return ret; + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm/nrf52/common/src/nrf52_reset.c b/boards/arm/nrf52/common/src/nrf52_reset.c new file mode 100644 index 0000000000000..b701315f27e2f --- /dev/null +++ b/boards/arm/nrf52/common/src/nrf52_reset.c @@ -0,0 +1,62 @@ +/**************************************************************************** + * boards/arm/nrf52/common/src/nrf52_reset.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#ifdef CONFIG_BOARDCTL_RESET + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value int this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ + up_systemreset(); + return 0; +} + +#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/nrf52/nrf52832-dk/configs/mrf24j40_6lowpan/defconfig b/boards/arm/nrf52/nrf52832-dk/configs/mrf24j40_6lowpan/defconfig new file mode 100644 index 0000000000000..f0c31e2a45d19 --- /dev/null +++ b/boards/arm/nrf52/nrf52832-dk/configs/mrf24j40_6lowpan/defconfig @@ -0,0 +1,81 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nrf52832-dk" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NRF52832_DK=y +CONFIG_ARCH_CHIP="nrf52" +CONFIG_ARCH_CHIP_NRF52832=y +CONFIG_ARCH_CHIP_NRF52=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_STDARG_H=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=5500 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXAMPLES_NETTEST=y +CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0" +CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616 +CONFIG_EXAMPLES_NETTEST_TARGET2=y +CONFIG_EXAMPLES_UDP=y +CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617 +CONFIG_EXAMPLES_UDP_DEVNAME="wpan0" +CONFIG_EXAMPLES_UDP_IPv6=y +CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616 +CONFIG_EXAMPLES_UDP_TARGET2=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_IEEE802154_MRF24J40=y +CONFIG_IEEE802154_NETDEV=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_MAC802154_NTXDESC=36 +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDEV_HPWORK_THREAD=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_STATISTICS=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_NETLOCAL=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_6LOWPAN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_IPv6=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCPBACKLOG=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NRF52_GPIOTE=y +CONFIG_NRF52_SPI0_MASTER=y +CONFIG_NRF52_UART0=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_PROMPT_STRING="nsh-mrf> " +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=65535 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_TELNET_CLIENT=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/nrf52/nrf52832-dk/configs/mrf24j40_mac/defconfig b/boards/arm/nrf52/nrf52832-dk/configs/mrf24j40_mac/defconfig new file mode 100644 index 0000000000000..0b3a93261d496 --- /dev/null +++ b/boards/arm/nrf52/nrf52832-dk/configs/mrf24j40_mac/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nrf52832-dk" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NRF52832_DK=y +CONFIG_ARCH_CHIP="nrf52" +CONFIG_ARCH_CHIP_NRF52832=y +CONFIG_ARCH_CHIP_NRF52=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_STDARG_H=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=5500 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_IEEE802154_MRF24J40=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_MM_REGIONS=2 +CONFIG_NRF52_GPIOTE=y +CONFIG_NRF52_SPI0_MASTER=y +CONFIG_NRF52_UART0=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_PROMPT_STRING="nsh-mrf> " +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65535 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_STACK_COLORATION=y +CONFIG_STACK_USAGE=y +CONFIG_START_DAY=26 +CONFIG_START_MONTH=3 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/nrf52/nrf52832-dk/configs/timer/defconfig b/boards/arm/nrf52/nrf52832-dk/configs/timer/defconfig index 1592712d7d64d..2aeb152a31f06 100644 --- a/boards/arm/nrf52/nrf52832-dk/configs/timer/defconfig +++ b/boards/arm/nrf52/nrf52832-dk/configs/timer/defconfig @@ -25,7 +25,7 @@ CONFIG_FAT_LFN=y CONFIG_FS_FAT=y CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_MM_REGIONS=2 -CONFIG_NRF52_TIMER0=y +CONFIG_NRF52_TIMER1=y CONFIG_NRF52_UART0=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/nrf52/nrf52832-dk/include/board.h b/boards/arm/nrf52/nrf52832-dk/include/board.h index b77688958215c..092a3a0e10bd5 100644 --- a/boards/arm/nrf52/nrf52832-dk/include/board.h +++ b/boards/arm/nrf52/nrf52832-dk/include/board.h @@ -107,4 +107,16 @@ #define BOARD_UART0_RX_PIN (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN(8)) #define BOARD_UART0_TX_PIN (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | GPIO_PIN(6)) +/* SPI Pins *****************************************************************/ + +/* SPI0 - Arduino PINs + * SPI0_SCK - P0.25 (P13) + * SPI0_MISO - P0.24 (D12) + * SPI0_MOSI - P0.23 (D11) + */ + +#define BOARD_SPI0_SCK_PIN (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | GPIO_PIN(25)) +#define BOARD_SPI0_MISO_PIN (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN(24)) +#define BOARD_SPI0_MOSI_PIN (GPIO_OUTPUT | GPIO_PORT0 | GPIO_PIN(23)) + #endif /* __BOARDS_ARM_NRF52_NRF52832_DK_INCLUDE_BOARD_H */ diff --git a/boards/arm/nrf52/nrf52832-dk/src/CMakeLists.txt b/boards/arm/nrf52/nrf52832-dk/src/CMakeLists.txt index 7e61a0d0a9e85..d09591c71e5dc 100644 --- a/boards/arm/nrf52/nrf52832-dk/src/CMakeLists.txt +++ b/boards/arm/nrf52/nrf52832-dk/src/CMakeLists.txt @@ -34,6 +34,14 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS nrf52_buttons.c) endif() +if(CONFIG_NRF52_SPI_MASTER) + list(APPEND SRCS nrf52_spi.c) +endif() + +if(CONFIG_IEEE802154_MRF24J40) + list(APPEND SRCS nrf52_ieee802154_mrf24j40.c) +endif() + target_sources(board PRIVATE ${SRCS}) if(CONFIG_ARCH_BOARD_COMMON) diff --git a/boards/arm/nrf52/nrf52832-dk/src/Make.defs b/boards/arm/nrf52/nrf52832-dk/src/Make.defs index 7e4e6508fab84..7b6364940c3b0 100644 --- a/boards/arm/nrf52/nrf52832-dk/src/Make.defs +++ b/boards/arm/nrf52/nrf52832-dk/src/Make.defs @@ -36,6 +36,14 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += nrf52_buttons.c endif +ifeq ($(CONFIG_NRF52_SPI_MASTER),y) +CSRCS += nrf52_spi.c +endif + +ifeq ($(CONFIG_IEEE802154_MRF24J40),y) +CSRCS += nrf52_ieee802154_mrf24j40.c +endif + DEPPATH += --dep-path board VPATH += :board CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/nrf52/nrf52832-dk/src/nrf52832-dk.h b/boards/arm/nrf52/nrf52832-dk/src/nrf52832-dk.h index bdf5c8f0ad79d..c857ac3e5d524 100644 --- a/boards/arm/nrf52/nrf52832-dk/src/nrf52832-dk.h +++ b/boards/arm/nrf52/nrf52832-dk/src/nrf52832-dk.h @@ -64,6 +64,16 @@ #define GPIO_BUTTON3 (GPIO_INPUT | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN(15)) #define GPIO_BUTTON4 (GPIO_INPUT | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN(16)) +/* GPIO definitions *********************************************************/ + +/* MRF24J40 pins + * CS - P0.11 + * INT - P0.12 + */ + +#define GPIO_MRF24J40_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORT0 | GPIO_PIN(11)) +#define GPIO_MRF24J40_INT (GPIO_INPUT | GPIO_PORT0 | GPIO_PIN(12)) + /**************************************************************************** * Public Types ****************************************************************************/ @@ -94,5 +104,33 @@ int nrf52_bringup(void); +/**************************************************************************** + * Name: nrf52_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the nrf52840-dk board. + * + ****************************************************************************/ + +#ifdef CONFIG_NRF52_SPI_MASTER +void nrf52_spidev_initialize(void); +#endif + +/**************************************************************************** + * Name: nrf52_mrf24j40_initialize + * + * Description: + * Initialize the MRF24J40 device. + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_IEEE802154_MRF24J40 +int nrf52_mrf24j40_initialize(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __BOARDS_ARM_NRF52_NRF52832_DK_SRC_NRF52832_DK_H */ diff --git a/boards/arm/nrf52/nrf52832-dk/src/nrf52_boot.c b/boards/arm/nrf52/nrf52832-dk/src/nrf52_boot.c index a23cf76ca90c1..aeaf57d6305f9 100644 --- a/boards/arm/nrf52/nrf52832-dk/src/nrf52_boot.c +++ b/boards/arm/nrf52/nrf52832-dk/src/nrf52_boot.c @@ -54,6 +54,12 @@ void nrf52_board_initialize(void) #ifdef CONFIG_ARCH_LEDS board_autoled_initialize(); #endif + +#ifdef CONFIG_NRF52_SPI_MASTER + /* Configure SPI chip selects */ + + nrf52_spidev_initialize(); +#endif } /**************************************************************************** diff --git a/boards/arm/nrf52/nrf52832-dk/src/nrf52_bringup.c b/boards/arm/nrf52/nrf52832-dk/src/nrf52_bringup.c index d2d19c77ed3db..aca8f50019c28 100644 --- a/boards/arm/nrf52/nrf52832-dk/src/nrf52_bringup.c +++ b/boards/arm/nrf52/nrf52832-dk/src/nrf52_bringup.c @@ -53,13 +53,17 @@ # include "nrf52_sdc.h" #endif +#ifdef CONFIG_IEEE802154_MRF24J40 +# include "nrf52_mrf24j40.h" +#endif + #include "nrf52832-dk.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define NRF52_TIMER (0) +#define NRF52_TIMER (1) /**************************************************************************** * Public Functions @@ -138,7 +142,6 @@ int nrf52_bringup(void) #ifdef CONFIG_NRF52_SOFTDEVICE_CONTROLLER ret = nrf52_sdc_initialize(); - if (ret < 0) { syslog(LOG_ERR, "ERROR: nrf52_sdc_initialize() failed: %d\n", ret); @@ -153,6 +156,17 @@ int nrf52_bringup(void) } #endif /* CONFIG_MTD */ +#ifdef CONFIG_IEEE802154_MRF24J40 + /* Configure MRF24J40 wireless */ + + ret = nrf52_mrf24j40_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: nrf52_mrf24j40_initialize() failed: %d\n", + ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/boards/arm/nrf52/nrf52832-dk/src/nrf52_ieee802154_mrf24j40.c b/boards/arm/nrf52/nrf52832-dk/src/nrf52_ieee802154_mrf24j40.c new file mode 100644 index 0000000000000..13986ab94f3ea --- /dev/null +++ b/boards/arm/nrf52/nrf52832-dk/src/nrf52_ieee802154_mrf24j40.c @@ -0,0 +1,177 @@ +/**************************************************************************** + * boards/arm/nrf52/nrf52832-dk/src/nrf52_ieee802154_mrf24j40.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "nrf52_gpio.h" +#include "nrf52_gpiote.h" +#include "nrf52_spi.h" + +#include "nrf52_mrf24j40.h" + +#include "nrf52832-dk.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_NRF52_SPI0_MASTER +# error this driver requires CONFIG_NRF52_SPI0_MASTER +#endif + +#define NRF52_MRF24J40_SPI (0) + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* IRQ/GPIO access callbacks. These operations all hidden behind callbacks + * to isolate the MRF24J40 driver from differences in GPIO interrupt handling + * varying boards and MCUs. + * + * irq_attach - Attach the MRF24J40 interrupt handler to the GPIO + * interrupt + * irq_enable - Enable or disable the GPIO interrupt + */ + +static int nrf52_attach_irq(const struct mrf24j40_lower_s *lower, + xcpt_t handler, void *arg); +static void nrf52_enable_irq(const struct mrf24j40_lower_s *lower, + bool state); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the MRF24J40 + * driver. This structure provides information about the configuration + * of the MRF24J40 and provides some board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied + * by the driver and is presumed to persist while the driver is active. The + * memory must be writable because, under certain circumstances, the driver + * may modify frequency or X plate resistance values. + */ + +static struct nrf52_mrf24j40_s g_mrf24j40_priv = +{ + .dev.attach = nrf52_attach_irq, + .dev.enable = nrf52_enable_irq, + .handler = NULL, + .arg = NULL, + .intcfg = GPIO_MRF24J40_INT, + .spidev = NRF52_MRF24J40_SPI, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_attach_irq + * + * Description: + * Attach the MRF24J40 interrupt handler to the GPIO interrupt. + * + ****************************************************************************/ + +static int nrf52_attach_irq(const struct mrf24j40_lower_s *lower, + xcpt_t handler, void *arg) +{ + struct nrf52_mrf24j40_s *priv = (struct nrf52_mrf24j40_s *)lower; + + DEBUGASSERT(priv != NULL); + + /* Just save the handler for use when the interrupt is enabled */ + + priv->handler = handler; + priv->arg = arg; + return OK; +} + +/**************************************************************************** + * Name: nrf52_enable_irq + * + * Description: + * Enable or disable the GPIO interrupt + * + ****************************************************************************/ + +static void nrf52_enable_irq(const struct mrf24j40_lower_s *lower, + bool state) +{ + struct nrf52_mrf24j40_s *priv = (struct nrf52_mrf24j40_s *)lower; + + /* The caller should not attempt to enable interrupts if the handler + * has not yet been 'attached' + */ + + DEBUGASSERT(priv != NULL && (priv->handler != NULL || !state)); + + wlinfo("state:%d\n", (int)state); + + /* Attach and enable, or detach and disable */ + + if (state) + { + nrf52_gpiote_set_event(priv->intcfg, false, true, + priv->handler, priv->arg); + } + else + { + nrf52_gpiote_set_event(priv->intcfg, false, false, + priv->handler, priv->arg); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_mrf24j40_initialize + * + * Description: + * Initialize the MRF24J40 device. + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int nrf52_mrf24j40_initialize(void) +{ + int ret; + + ret = nrf52_mrf24j40_devsetup(&g_mrf24j40_priv); + if (ret < 0) + { + wlerr("Failed to initialize mrf24j40: %d\n", ret); + } + + return ret; +} diff --git a/boards/arm/nrf52/nrf52832-dk/src/nrf52_spi.c b/boards/arm/nrf52/nrf52832-dk/src/nrf52_spi.c new file mode 100644 index 0000000000000..7e8e6d3adfae3 --- /dev/null +++ b/boards/arm/nrf52/nrf52832-dk/src/nrf52_spi.c @@ -0,0 +1,177 @@ +/**************************************************************************** + * boards/arm/nrf52/nrf52832-dk/src/nrf52_spi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "nrf52_gpio.h" +#include "nrf52_spi.h" + +#include "nrf52832-dk.h" +#include + +#ifdef CONFIG_NRF52_SPI_MASTER + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nrf52_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the Nucleo-144 board. + * + ****************************************************************************/ + +void nrf52_spidev_initialize(void) +{ +#ifdef CONFIG_NRF52_SPI0_MASTER +# ifdef CONFIG_IEEE802154_MRF24J40 + /* Configure the SPI-based MRF24J40 chip select GPIO */ + + spiinfo("Configure GPIO for MRF24J40 SPI1/CS\n"); + + nrf52_gpio_config(GPIO_MRF24J40_CS); + nrf52_gpio_write(GPIO_MRF24J40_CS, true); +# endif +#endif +} + +/**************************************************************************** + * Name: nrf52_spi0/1/2/3/select and nrf52_spi0/1/2/3/status + * + * Description: + * The external functions, nrf52_spi0/1/2/3select and + * nrf52_spi0/1/2/3status must be provided by board-specific logic. + * They are implementations of the select and status methods of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * All other methods (including nrf52_spibus_initialize()) are provided + * by common NRF52 logic. To use this common SPI logic on your board: + * + * 1. Provide logic in nrf52_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide nrf52_spi0/1/2/3select() and nrf52_spi0/1/2/3status() + * functions in your board-specific logic. These functions will perform + * chip selection and status operations using GPIOs in the way your + * board is configured. + * 3. Add a calls to nrf52_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by nrf52_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_NRF52_SPI0_MASTER +void nrf52_spi0select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %08lx CS: %s\n", + (unsigned long)devid, selected ? "assert" : "de-assert"); + + switch (devid) + { +#ifdef CONFIG_IEEE802154_MRF24J40 + case SPIDEV_IEEE802154(0): + { + spiinfo("MRF24J40 device %s\n", + selected ? "asserted" : "de-asserted"); + + /* Set the GPIO low to select and high to de-select */ + + nrf52_gpio_write(GPIO_MRF24J40_CS, !selected); + break; + } +#endif + + default: + { + break; + } + } +} + +uint8_t nrf52_spi0status(struct spi_dev_s *dev, uint32_t devid) +{ + uint8_t status = 0; + + switch (devid) + { +#ifdef CONFIG_IEEE802154_MRF24J40 + case SPIDEV_IEEE802154(0): + { + status |= SPI_STATUS_PRESENT; + break; + } +#endif + + default: + { + break; + } + } + + return status; +} +#endif + +#ifdef CONFIG_NRF52_SPI1_MASTER +void nrf52_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %08lx CS: %s\n", + (unsigned long)devid, selected ? "assert" : "de-assert"); +} + +uint8_t nrf52_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_nrf52_SPI2_MASTER +void nrf52_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %08lx CS: %s\n", + (unsigned long)devid, selected ? "assert" : "de-assert"); +} + +uint8_t nrf52_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#endif /* CONFIG_NRF52_SPI_MASTER */ diff --git a/boards/arm/nrf52/nrf52840-dk/configs/ieee802154_6lowpan/defconfig b/boards/arm/nrf52/nrf52840-dk/configs/ieee802154_6lowpan/defconfig new file mode 100644 index 0000000000000..6afe61de129e8 --- /dev/null +++ b/boards/arm/nrf52/nrf52840-dk/configs/ieee802154_6lowpan/defconfig @@ -0,0 +1,81 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nrf52840-dk" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NRF52840_DK=y +CONFIG_ARCH_CHIP="nrf52" +CONFIG_ARCH_CHIP_NRF52840=y +CONFIG_ARCH_CHIP_NRF52=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_STDARG_H=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=5500 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXAMPLES_NETTEST=y +CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0" +CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616 +CONFIG_EXAMPLES_NETTEST_TARGET2=y +CONFIG_EXAMPLES_UDP=y +CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617 +CONFIG_EXAMPLES_UDP_DEVNAME="wpan0" +CONFIG_EXAMPLES_UDP_IPv6=y +CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616 +CONFIG_EXAMPLES_UDP_TARGET2=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_IEEE802154_NETDEV=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_MAC802154_NTXDESC=36 +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDEV_HPWORK_THREAD=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_STATISTICS=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_NETLOCAL=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_6LOWPAN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_IPv6=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCPBACKLOG=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NRF52_HFCLK_XTAL=y +CONFIG_NRF52_RADIO=y +CONFIG_NRF52_RADIO_IEEE802154=y +CONFIG_NRF52_UART0=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_PROMPT_STRING="nsh-nrf52> " +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=262144 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_TELNET_CLIENT=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/nrf52/nrf52840-dk/configs/ieee802154_mac/defconfig b/boards/arm/nrf52/nrf52840-dk/configs/ieee802154_mac/defconfig new file mode 100644 index 0000000000000..4d9a842623e5b --- /dev/null +++ b/boards/arm/nrf52/nrf52840-dk/configs/ieee802154_mac/defconfig @@ -0,0 +1,61 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nrf52840-dk" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NRF52840_DK=y +CONFIG_ARCH_CHIP="nrf52" +CONFIG_ARCH_CHIP_NRF52840=y +CONFIG_ARCH_CHIP_NRF52=y +CONFIG_ARCH_PERF_EVENTS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_STDARG_H=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=5500 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXPERIMENTAL=y +CONFIG_IDLETHREAD_STACKSIZE=4096 +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_MM_REGIONS=2 +CONFIG_NRF52_HFCLK_XTAL=y +CONFIG_NRF52_RADIO=y +CONFIG_NRF52_RADIO_IEEE802154=y +CONFIG_NRF52_TIMER1=y +CONFIG_NRF52_UART0=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_PROMPT_STRING="nsh-nrf52> " +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=262144 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKSTACKSIZE=4096 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKSTACKSIZE=4096 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_CANARIES=y +CONFIG_STACK_COLORATION=y +CONFIG_STACK_USAGE=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/nrf52/nrf52840-dk/configs/timer/defconfig b/boards/arm/nrf52/nrf52840-dk/configs/timer/defconfig index f65bb14ed8a33..3775f72f205c4 100644 --- a/boards/arm/nrf52/nrf52840-dk/configs/timer/defconfig +++ b/boards/arm/nrf52/nrf52840-dk/configs/timer/defconfig @@ -26,7 +26,7 @@ CONFIG_FS_FAT=y CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_MM_REGIONS=2 CONFIG_NRF52_RTC0=y -CONFIG_NRF52_TIMER0=y +CONFIG_NRF52_TIMER1=y CONFIG_NRF52_UART0=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/nrf52/nrf52840-dk/src/nrf52_bringup.c b/boards/arm/nrf52/nrf52840-dk/src/nrf52_bringup.c index f59b7b7a97254..26e8ea89ae135 100644 --- a/boards/arm/nrf52/nrf52840-dk/src/nrf52_bringup.c +++ b/boards/arm/nrf52/nrf52840-dk/src/nrf52_bringup.c @@ -61,13 +61,17 @@ # include "nrf52_lsm9ds1.h" #endif +#ifdef CONFIG_NRF52_RADIO_IEEE802154 +# include "nrf52_ieee802154.h" +#endif + #include "nrf52840-dk.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define NRF52_TIMER (0) +#define NRF52_TIMER (2) #define LMS9DS1_I2CBUS (0) /**************************************************************************** @@ -309,6 +313,15 @@ int nrf52_bringup(void) } #endif /* CONFIG_SENSORS_LSM6DSL */ +#ifdef CONFIG_NRF52_RADIO_IEEE802154 + ret = nrf52_ieee802154_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize IEE802154 radio: %d\n", + ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/boards/arm/nrf52/nrf52840-dongle/configs/ieee802154_mac/defconfig b/boards/arm/nrf52/nrf52840-dongle/configs/ieee802154_mac/defconfig new file mode 100644 index 0000000000000..3e3a0a98d22a5 --- /dev/null +++ b/boards/arm/nrf52/nrf52840-dongle/configs/ieee802154_mac/defconfig @@ -0,0 +1,65 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_SYSLOG_DEFAULT is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nrf52840-dongle" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NRF52840_DONGLE=y +CONFIG_ARCH_CHIP="nrf52" +CONFIG_ARCH_CHIP_NRF52840=y +CONFIG_ARCH_CHIP_NRF52=y +CONFIG_ARCH_PERF_EVENTS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_STDARG_H=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=5500 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXPERIMENTAL=y +CONFIG_IDLETHREAD_STACKSIZE=4096 +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_MM_REGIONS=2 +CONFIG_NRF52_HFCLK_XTAL=y +CONFIG_NRF52_RADIO=y +CONFIG_NRF52_RADIO_IEEE802154=y +CONFIG_NRF52_TIMER1=y +CONFIG_NRF52_USBDEV=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_PROMPT_STRING="nsh-dongle> " +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=262144 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKSTACKSIZE=4096 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKSTACKSIZE=4096 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_CANARIES=y +CONFIG_STACK_COLORATION=y +CONFIG_STACK_USAGE=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/nrf52/nrf52840-dongle/src/nrf52840-dongle.h b/boards/arm/nrf52/nrf52840-dongle/src/nrf52840-dongle.h index e2f688fb5a8cf..6c1791738343d 100644 --- a/boards/arm/nrf52/nrf52840-dongle/src/nrf52840-dongle.h +++ b/boards/arm/nrf52/nrf52840-dongle/src/nrf52840-dongle.h @@ -34,6 +34,18 @@ * Pre-processor Definitions ****************************************************************************/ +/* Configuration ************************************************************/ + +/* procfs File System */ + +#ifdef CONFIG_FS_PROCFS +# ifdef CONFIG_NSH_PROC_MOUNTPOINT +# define NRF52_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT +# else +# define NRF52_PROCFS_MOUNTPOINT "/proc" +# endif +#endif + /* LED definitions **********************************************************/ /* Definitions to configure LED GPIO as outputs */ diff --git a/boards/arm/nrf52/nrf52840-dongle/src/nrf52_bringup.c b/boards/arm/nrf52/nrf52840-dongle/src/nrf52_bringup.c index 1ad015a417544..fbcf6b4475ede 100644 --- a/boards/arm/nrf52/nrf52840-dongle/src/nrf52_bringup.c +++ b/boards/arm/nrf52/nrf52840-dongle/src/nrf52_bringup.c @@ -31,6 +31,10 @@ # include #endif +#ifdef CONFIG_NRF52_RADIO_IEEE802154 +# include "nrf52_ieee802154.h" +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -53,6 +57,17 @@ int nrf52_bringup(void) { int ret; +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, NRF52_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount the PROC filesystem: %d\n", ret); + } +#endif /* CONFIG_FS_PROCFS */ + #ifdef CONFIG_USERLED /* Register the LED driver */ @@ -63,6 +78,15 @@ int nrf52_bringup(void) } #endif +#ifdef CONFIG_NRF52_RADIO_IEEE802154 + ret = nrf52_ieee802154_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize IEE802154 radio: %d\n", + ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/boards/arm/nrf52/nrf9160-dk-nrf52/configs/ieee802154_6lowpan/defconfig b/boards/arm/nrf52/nrf9160-dk-nrf52/configs/ieee802154_6lowpan/defconfig new file mode 100644 index 0000000000000..473979b0702c8 --- /dev/null +++ b/boards/arm/nrf52/nrf9160-dk-nrf52/configs/ieee802154_6lowpan/defconfig @@ -0,0 +1,81 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nrf9160-dk-nrf52" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NRF9160_DK_NRF52=y +CONFIG_ARCH_CHIP="nrf52" +CONFIG_ARCH_CHIP_NRF52840=y +CONFIG_ARCH_CHIP_NRF52=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_STDARG_H=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=5500 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXAMPLES_NETTEST=y +CONFIG_EXAMPLES_NETTEST_DEVNAME="wpan0" +CONFIG_EXAMPLES_NETTEST_SERVER_PORTNO=61616 +CONFIG_EXAMPLES_NETTEST_TARGET2=y +CONFIG_EXAMPLES_UDP=y +CONFIG_EXAMPLES_UDP_CLIENT_PORTNO=61617 +CONFIG_EXAMPLES_UDP_DEVNAME="wpan0" +CONFIG_EXAMPLES_UDP_IPv6=y +CONFIG_EXAMPLES_UDP_SERVER_PORTNO=61616 +CONFIG_EXAMPLES_UDP_TARGET2=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_IEEE802154_NETDEV=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_MAC802154_NTXDESC=36 +CONFIG_MM_REGIONS=2 +CONFIG_NET=y +CONFIG_NETDEV_HPWORK_THREAD=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_STATISTICS=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_NETLOCAL=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_6LOWPAN=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_IPv6=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCPBACKLOG=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NRF52_HFCLK_XTAL=y +CONFIG_NRF52_RADIO=y +CONFIG_NRF52_RADIO_IEEE802154=y +CONFIG_NRF52_UART0=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_PROMPT_STRING="nsh-nrf91> " +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=262144 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_TELNET_CLIENT=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/nrf52/nrf9160-dk-nrf52/configs/ieee802154_mac/defconfig b/boards/arm/nrf52/nrf9160-dk-nrf52/configs/ieee802154_mac/defconfig new file mode 100644 index 0000000000000..1725e9d4d418b --- /dev/null +++ b/boards/arm/nrf52/nrf9160-dk-nrf52/configs/ieee802154_mac/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nrf9160-dk-nrf52" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_NRF9160_DK_NRF52=y +CONFIG_ARCH_CHIP="nrf52" +CONFIG_ARCH_CHIP_NRF52840=y +CONFIG_ARCH_CHIP_NRF52=y +CONFIG_ARCH_PERF_EVENTS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_STDARG_H=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=5500 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_IEEE802154=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXPERIMENTAL=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_IEEE802154_I8SAK=y +CONFIG_IEEE802154_MAC=y +CONFIG_IEEE802154_MACDEV=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_MM_REGIONS=2 +CONFIG_NRF52_HFCLK_XTAL=y +CONFIG_NRF52_RADIO=y +CONFIG_NRF52_RADIO_IEEE802154=y +CONFIG_NRF52_UART0=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_PROMPT_STRING="nsh-nrf91> " +CONFIG_NSH_READLINE=y +CONFIG_RAM_SIZE=262144 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_STACK_USAGE=y +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_IEEE802154=y diff --git a/boards/arm/nrf52/nrf9160-dk-nrf52/src/nrf52_bringup.c b/boards/arm/nrf52/nrf9160-dk-nrf52/src/nrf52_bringup.c index d5bb51e64471c..095fb9d4962d4 100644 --- a/boards/arm/nrf52/nrf9160-dk-nrf52/src/nrf52_bringup.c +++ b/boards/arm/nrf52/nrf9160-dk-nrf52/src/nrf52_bringup.c @@ -27,6 +27,14 @@ #include #include +#include + +#ifdef CONFIG_NRF52_RADIO_IEEE802154 +# include "nrf52_ieee802154.h" +#endif + +#include "nrf9160-dk-nrf52.h" + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -49,6 +57,26 @@ int nrf52_bringup(void) { int ret; +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, NRF52_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount the PROC filesystem: %d\n", ret); + } +#endif /* CONFIG_FS_PROCFS */ + +#ifdef CONFIG_NRF52_RADIO_IEEE802154 + ret = nrf52_ieee802154_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize IEE802154 radio: %d\n", + ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/boards/arm/nrf52/nrf9160-dk-nrf52/src/nrf9160-dk-nrf52.h b/boards/arm/nrf52/nrf9160-dk-nrf52/src/nrf9160-dk-nrf52.h index 82fe34c862c52..95744c9424315 100644 --- a/boards/arm/nrf52/nrf9160-dk-nrf52/src/nrf9160-dk-nrf52.h +++ b/boards/arm/nrf52/nrf9160-dk-nrf52/src/nrf9160-dk-nrf52.h @@ -34,6 +34,18 @@ * Pre-processor Definitions ****************************************************************************/ +/* Configuration ************************************************************/ + +/* procfs File System */ + +#ifdef CONFIG_FS_PROCFS +# ifdef CONFIG_NSH_PROC_MOUNTPOINT +# define NRF52_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT +# else +# define NRF52_PROCFS_MOUNTPOINT "/proc" +# endif +#endif + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/boards/arm/nrf53/common/src/CMakeLists.txt b/boards/arm/nrf53/common/src/CMakeLists.txt index b09c210700890..2dafcbe790448 100644 --- a/boards/arm/nrf53/common/src/CMakeLists.txt +++ b/boards/arm/nrf53/common/src/CMakeLists.txt @@ -32,6 +32,10 @@ if(CONFIG_ARCH_BOARD_COMMON) list(APPEND SRCS nrf53_progmem.c) endif() + if(CONFIG_BOARDCTL_RESET) + list(APPEND SRCS nrf53_reset.c) + endif() + target_sources(board PRIVATE ${SRCS}) endif() diff --git a/boards/arm/nrf53/common/src/Make.defs b/boards/arm/nrf53/common/src/Make.defs index 79e720c8d6159..a850bac42b0c1 100644 --- a/boards/arm/nrf53/common/src/Make.defs +++ b/boards/arm/nrf53/common/src/Make.defs @@ -32,6 +32,10 @@ ifeq ($(CONFIG_NRF53_PROGMEM),y) CSRCS += nrf53_progmem.c endif +ifeq ($(CONFIG_BOARDCTL_RESET),y) + CSRCS += nrf53_reset.c +endif + DEPPATH += --dep-path src VPATH += :src CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src diff --git a/boards/arm/nrf53/common/src/nrf53_reset.c b/boards/arm/nrf53/common/src/nrf53_reset.c new file mode 100644 index 0000000000000..625b615bc9c20 --- /dev/null +++ b/boards/arm/nrf53/common/src/nrf53_reset.c @@ -0,0 +1,62 @@ +/**************************************************************************** + * boards/arm/nrf53/common/src/nrf53_reset.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#ifdef CONFIG_BOARDCTL_RESET + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value int this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ + up_systemreset(); + return 0; +} + +#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/nrf53/nrf5340-dk/configs/rpmsghci_bt_cpuapp/defconfig b/boards/arm/nrf53/nrf5340-dk/configs/rpmsghci_bt_cpuapp/defconfig index 3cb64134b0503..39638b17ecf41 100644 --- a/boards/arm/nrf53/nrf5340-dk/configs/rpmsghci_bt_cpuapp/defconfig +++ b/boards/arm/nrf53/nrf5340-dk/configs/rpmsghci_bt_cpuapp/defconfig @@ -23,6 +23,7 @@ CONFIG_BLUETOOTH_RPMSG=y CONFIG_BOARD_LOOPSPERMSEC=5500 CONFIG_BTSAK=y CONFIG_BUILTIN=y +CONFIG_DEV_SIMPLE_ADDRENV=y CONFIG_DRIVERS_BLUETOOTH=y CONFIG_DRIVERS_WIRELESS=y CONFIG_EXPERIMENTAL=y @@ -42,15 +43,14 @@ CONFIG_NSH_DISABLE_IFUPDOWN=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 CONFIG_NSH_READLINE=y -CONFIG_OPENAMP=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=524288 CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y +CONFIG_RPMSG_LOCAL_CPUNAME="cpuapp" +CONFIG_RPMSG_PING=y CONFIG_RPTUN=y -CONFIG_RPTUN_LOCAL_CPUNAME="cpuapp" -CONFIG_RPTUN_PING=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SIG_EVTHREAD=y diff --git a/boards/arm/nrf53/nrf5340-dk/configs/rpmsghci_nimble_cpuapp/defconfig b/boards/arm/nrf53/nrf5340-dk/configs/rpmsghci_nimble_cpuapp/defconfig index 968bc25f1f2a1..534218c210b03 100644 --- a/boards/arm/nrf53/nrf5340-dk/configs/rpmsghci_nimble_cpuapp/defconfig +++ b/boards/arm/nrf53/nrf5340-dk/configs/rpmsghci_nimble_cpuapp/defconfig @@ -23,6 +23,7 @@ CONFIG_BLUETOOTH_MAX_CONN=2 CONFIG_BLUETOOTH_RPMSG=y CONFIG_BOARD_LOOPSPERMSEC=5500 CONFIG_BUILTIN=y +CONFIG_DEV_SIMPLE_ADDRENV=y CONFIG_DRIVERS_BLUETOOTH=y CONFIG_DRIVERS_WIRELESS=y CONFIG_EXPERIMENTAL=y @@ -43,15 +44,14 @@ CONFIG_NSH_DISABLE_IFUPDOWN=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 CONFIG_NSH_READLINE=y -CONFIG_OPENAMP=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=524288 CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y +CONFIG_RPMSG_LOCAL_CPUNAME="cpuapp" +CONFIG_RPMSG_PING=y CONFIG_RPTUN=y -CONFIG_RPTUN_LOCAL_CPUNAME="cpuapp" -CONFIG_RPTUN_PING=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_SIG_EVTHREAD=y diff --git a/boards/arm/nrf53/nrf5340-dk/configs/rpmsghci_sdc_cpunet/defconfig b/boards/arm/nrf53/nrf5340-dk/configs/rpmsghci_sdc_cpunet/defconfig index 79caf2728ded4..2a6c9fc6a8c43 100644 --- a/boards/arm/nrf53/nrf5340-dk/configs/rpmsghci_sdc_cpunet/defconfig +++ b/boards/arm/nrf53/nrf5340-dk/configs/rpmsghci_sdc_cpunet/defconfig @@ -22,6 +22,7 @@ CONFIG_BOARDCTL=y CONFIG_BOARDCTL_MKRD=y CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=5500 +CONFIG_DEV_SIMPLE_ADDRENV=y CONFIG_DRIVERS_BLUETOOTH=y CONFIG_DRIVERS_WIRELESS=y CONFIG_EXAMPLES_HELLO=y @@ -33,14 +34,13 @@ CONFIG_NRF53_SDC_MAX_COUNT=2 CONFIG_NRF53_SDC_PUB_ADDR=0x0102030405 CONFIG_NRF53_SOFTDEVICE_CONTROLLER=y CONFIG_NRF53_UART0=y -CONFIG_OPENAMP=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=65535 CONFIG_RAM_START=0x21000000 CONFIG_RAW_BINARY=y +CONFIG_RPMSG_LOCAL_CPUNAME="cpunet" +CONFIG_RPMSG_PING=y CONFIG_RPTUN=y -CONFIG_RPTUN_LOCAL_CPUNAME="cpunet" -CONFIG_RPTUN_PING=y CONFIG_RPTUN_STACKSIZE=2048 CONFIG_RR_INTERVAL=200 CONFIG_SCHED_LPWORK=y diff --git a/boards/arm/nrf53/nrf5340-dk/configs/rptun_cpuapp/defconfig b/boards/arm/nrf53/nrf5340-dk/configs/rptun_cpuapp/defconfig index 01fed5032f8dd..18f1a08116f35 100644 --- a/boards/arm/nrf53/nrf5340-dk/configs/rptun_cpuapp/defconfig +++ b/boards/arm/nrf53/nrf5340-dk/configs/rptun_cpuapp/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_CHIP_NRF53=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STDARG_H=y CONFIG_BOARD_LOOPSPERMSEC=5500 +CONFIG_DEV_SIMPLE_ADDRENV=y CONFIG_EXPERIMENTAL=y CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INTELHEX_BINARY=y @@ -27,15 +28,14 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 CONFIG_NSH_READLINE=y -CONFIG_OPENAMP=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=524288 CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y +CONFIG_RPMSG_LOCAL_CPUNAME="cpuapp" +CONFIG_RPMSG_PING=y CONFIG_RPMSG_UART=y CONFIG_RPTUN=y -CONFIG_RPTUN_LOCAL_CPUNAME="cpuapp" -CONFIG_RPTUN_PING=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=26 diff --git a/boards/arm/nrf53/nrf5340-dk/configs/rptun_cpunet/defconfig b/boards/arm/nrf53/nrf5340-dk/configs/rptun_cpunet/defconfig index 89ecdad90796b..34e3df4512ed4 100644 --- a/boards/arm/nrf53/nrf5340-dk/configs/rptun_cpunet/defconfig +++ b/boards/arm/nrf53/nrf5340-dk/configs/rptun_cpunet/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH_CHIP_NRF53=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STDARG_H=y CONFIG_BOARD_LOOPSPERMSEC=5500 +CONFIG_DEV_SIMPLE_ADDRENV=y CONFIG_EXPERIMENTAL=y CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INTELHEX_BINARY=y @@ -27,15 +28,14 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 CONFIG_NSH_READLINE=y -CONFIG_OPENAMP=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=65535 CONFIG_RAM_START=0x21000000 CONFIG_RAW_BINARY=y +CONFIG_RPMSG_LOCAL_CPUNAME="cpunet" +CONFIG_RPMSG_PING=y CONFIG_RPMSG_UART=y CONFIG_RPTUN=y -CONFIG_RPTUN_LOCAL_CPUNAME="cpunet" -CONFIG_RPTUN_PING=y CONFIG_RPTUN_STACKSIZE=2048 CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y diff --git a/boards/arm/nrf53/nrf5340-dk/src/nrf53_bringup.c b/boards/arm/nrf53/nrf5340-dk/src/nrf53_bringup.c index 785f57931e348..9ec8819969b96 100644 --- a/boards/arm/nrf53/nrf5340-dk/src/nrf53_bringup.c +++ b/boards/arm/nrf53/nrf5340-dk/src/nrf53_bringup.c @@ -226,9 +226,9 @@ int nrf53_bringup(void) #ifdef CONFIG_RPTUN #ifdef CONFIG_NRF53_APPCORE - nrf53_rptun_init("nrf53-shmem", "appcore"); + nrf53_rptun_init("appcore"); #else - nrf53_rptun_init("nrf53-shmem", "netcore"); + nrf53_rptun_init("netcore"); #endif #endif diff --git a/boards/arm/nrf53/thingy53/src/nrf53_bringup.c b/boards/arm/nrf53/thingy53/src/nrf53_bringup.c index 13f0c2df5c317..13a94fd2e00c7 100644 --- a/boards/arm/nrf53/thingy53/src/nrf53_bringup.c +++ b/boards/arm/nrf53/thingy53/src/nrf53_bringup.c @@ -205,9 +205,9 @@ int nrf53_bringup(void) #ifdef CONFIG_RPTUN #ifdef CONFIG_NRF53_APPCORE - nrf53_rptun_init("nrf53-shmem", "appcore"); + nrf53_rptun_init("appcore"); #else - nrf53_rptun_init("nrf53-shmem", "netcore"); + nrf53_rptun_init("netcore"); #endif #endif diff --git a/boards/arm/nrf91/common/src/CMakeLists.txt b/boards/arm/nrf91/common/src/CMakeLists.txt index 9492508ab4b73..b3b52600a32d9 100644 --- a/boards/arm/nrf91/common/src/CMakeLists.txt +++ b/boards/arm/nrf91/common/src/CMakeLists.txt @@ -32,6 +32,10 @@ if(CONFIG_ARCH_BOARD_COMMON) list(APPEND SRCS nrf91_progmem.c) endif() + if(CONFIG_BOARDCTL_RESET) + list(APPEND SRCS nrf91_reset.c) + endif() + target_sources(board PRIVATE ${SRCS}) endif() diff --git a/boards/arm/nrf91/common/src/Make.defs b/boards/arm/nrf91/common/src/Make.defs index 21036b1bb5a76..77695532bd99f 100644 --- a/boards/arm/nrf91/common/src/Make.defs +++ b/boards/arm/nrf91/common/src/Make.defs @@ -32,6 +32,10 @@ ifeq ($(CONFIG_NRF91_PROGMEM),y) CSRCS += nrf91_progmem.c endif +ifeq ($(CONFIG_BOARDCTL_RESET),y) + CSRCS += nrf91_reset.c +endif + DEPPATH += --dep-path src VPATH += :src CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src diff --git a/boards/arm/nrf91/common/src/nrf91_reset.c b/boards/arm/nrf91/common/src/nrf91_reset.c new file mode 100644 index 0000000000000..2fc95eb2d2db3 --- /dev/null +++ b/boards/arm/nrf91/common/src/nrf91_reset.c @@ -0,0 +1,62 @@ +/**************************************************************************** + * boards/arm/nrf91/common/src/nrf91_reset.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#ifdef CONFIG_BOARDCTL_RESET + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value int this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ + up_systemreset(); + return 0; +} + +#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/nrf91/nrf9160-dk/configs/modem_ns/defconfig b/boards/arm/nrf91/nrf9160-dk/configs/modem_ns/defconfig index 8d096a6972bb2..aa02e18695322 100644 --- a/boards/arm/nrf91/nrf9160-dk/configs/modem_ns/defconfig +++ b/boards/arm/nrf91/nrf9160-dk/configs/modem_ns/defconfig @@ -17,6 +17,7 @@ CONFIG_ARCH_CHIP_NRF9160=y CONFIG_ARCH_CHIP_NRF91=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_STDARG_H=y +CONFIG_ARCH_TRUSTZONE_NONSECURE=y CONFIG_ARMV8M_CMSE=y CONFIG_BOARD_LOOPSPERMSEC=5500 CONFIG_BUILTIN=y @@ -33,7 +34,6 @@ CONFIG_GPSUTILS_MINMEA_LIB=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y CONFIG_MM_REGIONS=2 CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y diff --git a/boards/arm/phy62xx/phy6222/configs/phy_sbp/defconfig b/boards/arm/phy62xx/phy6222/configs/phy_sbp/defconfig index e09e30feb4ef8..f8cdce8113f80 100644 --- a/boards/arm/phy62xx/phy6222/configs/phy_sbp/defconfig +++ b/boards/arm/phy62xx/phy6222/configs/phy_sbp/defconfig @@ -17,7 +17,6 @@ # CONFIG_NSH_DISABLE_EXIT is not set # CONFIG_NSH_DISABLE_EXPORT is not set # CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_HELP is not set # CONFIG_NSH_DISABLE_HEXDUMP is not set # CONFIG_NSH_DISABLE_KILL is not set # CONFIG_NSH_DISABLE_LS is not set diff --git a/boards/arm/phy62xx/phy6222/include/nsh_romfsimg.h b/boards/arm/phy62xx/phy6222/include/nsh_romfsimg.h deleted file mode 100644 index ff779fcedf875..0000000000000 --- a/boards/arm/phy62xx/phy6222/include/nsh_romfsimg.h +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/phy62xx/phy6222/include/nsh_romfsimg.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -unsigned char romfs_img[] = -{ - 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x00, 0xf0, - 0x4f, 0x15, 0x26, 0x7d, 0x76, 0x6f, 0x6c, 0x5f, 0x69, 0x6e, 0x69, 0x74, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, - 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, - 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, - 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x68, 0x2d, 0x96, 0x03, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; -unsigned int romfs_img_len = 1024; diff --git a/boards/arm/phy62xx/phy6222/src/Makefile b/boards/arm/phy62xx/phy6222/src/Makefile index 38dedc97973e0..77a66b5df03b9 100644 --- a/boards/arm/phy62xx/phy6222/src/Makefile +++ b/boards/arm/phy62xx/phy6222/src/Makefile @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f0l0g0/stm32f051-discovery/src/Makefile +# boards/arm/phy62xx/phy6222/src/Makefile # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with @@ -29,4 +29,8 @@ CSRCS += appinit.c CSRCS += reset.c +ifeq ($(CONFIG_ETC_ROMFS),y) +CSRCS += etc_romfs.c +endif + include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/phy62xx/phy6222/src/bringup.c b/boards/arm/phy62xx/phy6222/src/bringup.c index b3153405335a9..1e40688dc91d5 100644 --- a/boards/arm/phy62xx/phy6222/src/bringup.c +++ b/boards/arm/phy62xx/phy6222/src/bringup.c @@ -65,8 +65,8 @@ extern int phyplus_timer_initialize(const char *devpath, int timer); * Called from the NSH library * ****************************************************************************/ -#define PPLUS_MTD_START_OFFSET 0x60000 //start from 384k offset -#define PPLUS_MTD_SIZE 0x20000 //mtd size is 128k bytes +#define PPLUS_MTD_START_OFFSET 0x60000 /* start from 384k offset */ +#define PPLUS_MTD_SIZE 0x20000 /* mtd size is 128k bytes */ int phy62xx_bringup(void) { diff --git a/boards/arm/phy62xx/phy6222/src/etc_romfs.c b/boards/arm/phy62xx/phy6222/src/etc_romfs.c new file mode 100644 index 0000000000000..895245aca2416 --- /dev/null +++ b/boards/arm/phy62xx/phy6222/src/etc_romfs.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/phy62xx/phy6222/src/etc_romfs.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +unsigned char romfs_img[] = +{ + 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x00, 0xf0, + 0x4f, 0x15, 0x26, 0x7d, 0x76, 0x6f, 0x6c, 0x5f, 0x69, 0x6e, 0x69, 0x74, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, + 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, + 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x68, 0x2d, 0x96, 0x03, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, + 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x00, + 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x20, 0x2e, 0x2e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, + 0x8d, 0x9c, 0xac, 0xf9, 0x72, 0x63, 0x53, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x68, 0x34, 0x20, 0x26, + 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; +unsigned int romfs_img_len = 1024; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/boards/arm/qemu/qemu-armv7a/configs/nsh/defconfig b/boards/arm/qemu/qemu-armv7a/configs/nsh/defconfig index 81da34c485d38..30251f380e5f5 100644 --- a/boards/arm/qemu/qemu-armv7a/configs/nsh/defconfig +++ b/boards/arm/qemu/qemu-armv7a/configs/nsh/defconfig @@ -41,7 +41,6 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_ONESHOT=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAMLOG=y diff --git a/boards/arm/qemu/qemu-armv7a/configs/smp/defconfig b/boards/arm/qemu/qemu-armv7a/configs/smp/defconfig new file mode 100644 index 0000000000000..bf7e0fcd36ada --- /dev/null +++ b/boards/arm/qemu/qemu-armv7a/configs/smp/defconfig @@ -0,0 +1,66 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ALARM_ARCH=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="qemu-armv7a" +CONFIG_ARCH_BOARD_QEMU_ARMV7A=y +CONFIG_ARCH_CHIP="qemu" +CONFIG_ARCH_CHIP_QEMU_ARM=y +CONFIG_ARCH_CHIP_QEMU_CORTEXA7=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_LOWVECTORS=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_TASK_STACKSIZE=4096 +CONFIG_DEV_ZERO=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXPERIMENTAL=y +CONFIG_FLASH_SIZE=134217728 +CONFIG_FLASH_START=0 +CONFIG_FLASH_VSTART=0 +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=4096 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_ONESHOT=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAM_SIZE=134217728 +CONFIG_RAM_START=0x40000000 +CONFIG_RAM_VSTART=0x40000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SMP=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=25 +CONFIG_START_MONTH=4 +CONFIG_START_YEAR=2023 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_SYSTEM=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART1_BASE=0x9000000 +CONFIG_UART1_IRQ=33 +CONFIG_UART1_PL011=y +CONFIG_UART1_SERIAL_CONSOLE=y +CONFIG_UART_PL011=y +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/qemu/qemu-armv7a/scripts/dramboot.ld b/boards/arm/qemu/qemu-armv7a/scripts/dramboot.ld index 38db42193825f..6afca6ca6ce18 100644 --- a/boards/arm/qemu/qemu-armv7a/scripts/dramboot.ld +++ b/boards/arm/qemu/qemu-armv7a/scripts/dramboot.ld @@ -26,6 +26,20 @@ PHDRS SECTIONS { . = 0x40101000; + + /* where the global variable out-of-bounds detection information located */ +#ifdef CONFIG_MM_KASAN_GLOBAL + .kasan.unused : + { + *(.data..LASANLOC*) + } > ROM + .kasan.global : + { + KEEP (*(.data..LASAN0)) + KEEP (*(.data.rel.local..LASAN0)) + } > ROM +#endif + .text : { _stext = .; /* Text section */ *(.vectors) diff --git a/boards/arm/qemu/qemu-armv7a/src/qemu_bringup.c b/boards/arm/qemu/qemu-armv7a/src/qemu_bringup.c index 790b0350876a3..0fc675a2b39e2 100644 --- a/boards/arm/qemu/qemu-armv7a/src/qemu_bringup.c +++ b/boards/arm/qemu/qemu-armv7a/src/qemu_bringup.c @@ -41,96 +41,15 @@ * Pre-processor Definitions ****************************************************************************/ -#define QEMU_SPI_IRQ_BASE 32 +#ifndef QEMU_SPI_IRQ_BASE +#define QEMU_SPI_IRQ_BASE 32 +#endif /**************************************************************************** * Private Functions ****************************************************************************/ #if defined(CONFIG_LIBC_FDT) && defined(CONFIG_DEVICE_TREE) - -/**************************************************************************** - * Name: fdt_get_irq - * - * Description: - * Only can be use when the corresponding node's parent interrupt - * controller is intc node. - * - ****************************************************************************/ - -static int unused_code -fdt_get_irq(const void *fdt, int offset) -{ - const fdt32_t *pv; - int irq = -ENOENT; - - pv = fdt_getprop(fdt, offset, "interrupts", NULL); - if (pv != NULL) - { - irq = fdt32_ld(pv + 1) + QEMU_SPI_IRQ_BASE; - } - - return irq; -} - -/**************************************************************************** - * Name: fdt_get_irq_by_path - * - * Description: - * Only can be use when the corresponding node's parent interrupt - * controller is intc node. - * - ****************************************************************************/ - -static int unused_code -fdt_get_irq_by_path(const void *fdt, const char *path) -{ - return fdt_get_irq(fdt, fdt_path_offset(fdt, path)); -} - -/**************************************************************************** - * Name: fdt_get_reg_base - ****************************************************************************/ - -static uintptr_t unused_code -fdt_get_reg_base(const void *fdt, int offset) -{ - const void *reg; - uintptr_t addr = 0; - int parentoff; - - parentoff = fdt_parent_offset(fdt, offset); - if (parentoff < 0) - { - return addr; - } - - reg = fdt_getprop(fdt, offset, "reg", NULL); - if (reg != NULL) - { - if (fdt_address_cells(fdt, parentoff) == 2) - { - addr = fdt64_ld(reg); - } - else - { - addr = fdt32_ld(reg); - } - } - - return addr; -} - -/**************************************************************************** - * Name: fdt_get_reg_base_by_path - ****************************************************************************/ - -static uintptr_t unused_code -fdt_get_reg_base_by_path(const void *fdt, const char *path) -{ - return fdt_get_reg_base(fdt, fdt_path_offset(fdt, path)); -} - #ifdef CONFIG_DRIVERS_VIRTIO_MMIO /**************************************************************************** @@ -151,8 +70,8 @@ static void register_virtio_devices_from_fdt(const void *fdt) break; } - addr = fdt_get_reg_base(fdt, offset); - irqnum = fdt_get_irq(fdt, offset); + addr = fdt_get_reg_base(fdt, offset, 0); + irqnum = fdt_get_irq(fdt, offset, 1, QEMU_SPI_IRQ_BASE); if (addr > 0 && irqnum >= 0) { virtio_register_mmio_device((void *)addr, irqnum); diff --git a/boards/arm/rp2040/adafruit-feather-rp2040/configs/nshsram/defconfig b/boards/arm/rp2040/adafruit-feather-rp2040/configs/nshsram/defconfig index e7e942bb5d9fd..afe57d66cba82 100644 --- a/boards/arm/rp2040/adafruit-feather-rp2040/configs/nshsram/defconfig +++ b/boards/arm/rp2040/adafruit-feather-rp2040/configs/nshsram/defconfig @@ -5,6 +5,7 @@ # You can then do "make savedefconfig" to generate a new defconfig file that includes your # modifications. # +# CONFIG_DEBUG_OPT_UNUSED_SECTIONS is not set # CONFIG_LIBC_LONG_LONG is not set # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set diff --git a/boards/arm/rp2040/adafruit-kb2040/configs/nshsram/defconfig b/boards/arm/rp2040/adafruit-kb2040/configs/nshsram/defconfig index 6f36d88406fec..0de8616254426 100644 --- a/boards/arm/rp2040/adafruit-kb2040/configs/nshsram/defconfig +++ b/boards/arm/rp2040/adafruit-kb2040/configs/nshsram/defconfig @@ -5,6 +5,7 @@ # You can then do "make savedefconfig" to generate a new defconfig file that includes your # modifications. # +# CONFIG_DEBUG_OPT_UNUSED_SECTIONS is not set # CONFIG_LIBC_LONG_LONG is not set # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set diff --git a/boards/arm/rp2040/common/Kconfig b/boards/arm/rp2040/common/Kconfig index e29845a16204b..fd1e7ffafeba2 100644 --- a/boards/arm/rp2040/common/Kconfig +++ b/boards/arm/rp2040/common/Kconfig @@ -579,3 +579,35 @@ config RP2040_ENC28J60_RESET_GPIO range -1 29 endif # ENC28J60 + +if NET_W5500 + +config RP2040_W5500_SPI_CH + int "W5500 SPI channel number" + default 0 + range 0 1 + ---help--- + SPI device for W5500 chip. + +config RP2040_W5500_SPI_FREQ + int "W5500 SPI frequency (kHz)" + default 40000 + range 100 40000 + ---help--- + SPI frequency for W5500 chip. + +config RP2040_W5500_RST_GPIO + int "W5500 reset GPIO pin" + default 20 + range 0 29 + ---help--- + RP2040 pin number that connects to W5500 Reset + +config RP2040_W5500_INT_GPIO + int "W5500 interrupt GPIO pin" + default 21 + range 0 29 + ---help--- + RP2040 pin number that connects to W5500 Interrupt + +endif # NET_W5500 diff --git a/boards/arm/rp2040/common/include/rp2040_bmp280.h b/boards/arm/rp2040/common/include/rp2040_bmp280.h new file mode 100644 index 0000000000000..cd5467e90e468 --- /dev/null +++ b/boards/arm/rp2040/common/include/rp2040_bmp280.h @@ -0,0 +1,84 @@ +/**************************************************************************** + * boards/arm/rp2040/common/include/rp2040_bmp280.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_RP2040_COMMON_INCLUDE_RP2040_BMP280_H +#define __BOARDS_ARM_RP2040_COMMON_INCLUDE_RP2040_BMP280_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_bmp280_initialize + * + * Description: + * Initialize and register the BMP280 Pressure Sensor driver. + * + * Input Parameters: + * devno - The device number, used to build the device path as /dev/pressN + * busno - The I2C bus number + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_bmp280_initialize(int busno); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __BOARDS_ARM_RP2040_COMMON_INCLUDE_RP2040_BMP280_H */ diff --git a/boards/arm/rp2040/common/include/rp2040_uniqueid.h b/boards/arm/rp2040/common/include/rp2040_uniqueid.h new file mode 100644 index 0000000000000..46edcec3d867b --- /dev/null +++ b/boards/arm/rp2040/common/include/rp2040_uniqueid.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * boards/arm/rp2040/common/include/rp2040_uniqueid.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_RP2040_COMMON_INCLUDE_RP2040_UNIQUEID_H +#define __BOARDS_ARM_RP2040_COMMON_INCLUDE_RP2040_UNIQUEID_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RP2040_FLASH_ID_SIZE 8 +#define RP2040_FLASH_ID_BUFFER_SIZE 13 +#define RP2040_FLASH_ID_BUFFER_OFFSET 5 +#define RP2040_FLASH_RUID_CMD 0x4b + +#ifdef __cplusplus +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: rp2040_uniqueid_initialize + * + * Description: + * The RP2040 doesn't have a unique ID, so we load the ID from the + * connected flash chip. We use the flash ID to seed a simple xorshift + * PRNG. The PRNG then generates CONFIG_BOARDCTL_UNIQUEID_SIZE bytes, + * which we will use as the board's unique ID. + * + * Retrieving the flash id is somewhat slow and complex, so we only do + * this during initialization and store the result for later use. + * + * Assumptions/Limitations: + * This uniqueid implementation requires a flash chip. It should not be + * used on boards without flash. + * + ****************************************************************************/ + +void rp2040_uniqueid_initialize(void); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __BOARDS_ARM_RP2040_COMMON_INCLUDE_RP2040_UNIQUEID_H */ \ No newline at end of file diff --git a/boards/arm/rp2040/common/src/Make.defs b/boards/arm/rp2040/common/src/Make.defs index f7f13bce68479..89b476323e08f 100644 --- a/boards/arm/rp2040/common/src/Make.defs +++ b/boards/arm/rp2040/common/src/Make.defs @@ -79,6 +79,10 @@ ifeq ($(CONFIG_SENSORS_BMP180),y) CSRCS += rp2040_bmp180.c endif +ifeq ($(CONFIG_SENSORS_BMP280),y) + CSRCS += rp2040_bmp280.c +endif + ifeq ($(CONFIG_SENSORS_INA219),y) CSRCS += rp2040_ina219.c endif @@ -91,6 +95,14 @@ ifeq ($(CONFIG_LCD_BACKPACK),y) CSRCS += rp2040_lcd_backpack.c endif +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) + CSRCS += rp2040_uniqueid.c +endif + +ifeq ($(CONFIG_NET_W5500),y) +CSRCS += rp2040_w5500.c +endif + DEPPATH += --dep-path src VPATH += :src CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src diff --git a/boards/arm/rp2040/common/src/rp2040_bmp280.c b/boards/arm/rp2040/common/src/rp2040_bmp280.c new file mode 100644 index 0000000000000..09f8f5508c557 --- /dev/null +++ b/boards/arm/rp2040/common/src/rp2040_bmp280.c @@ -0,0 +1,108 @@ +/**************************************************************************** + * boards/arm/rp2040/common/src/rp2040_bmp280.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "rp2040_i2c.h" +#include "rp2040_bmp280.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_bmp280_initialize + * + * Description: + * Initialize and register the BMP280 Pressure Sensor driver. + * + * Input Parameters: + * devno - The device number, used to build the device path as /dev/pressN + * busno - The I2C bus number + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_bmp280_initialize(int busno) +{ + struct i2c_master_s *i2c; + int ret; + const int devno = 0; + + sninfo("Initializing BMP280!\n"); + + /* Initialize BMP280 */ + + i2c = rp2040_i2cbus_initialize(busno); + if (i2c) + { + /* Then try to register the barometer sensor in I2C0 */ + + ret = bmp280_register(devno, i2c); + if (ret < 0) + { + snerr("ERROR: Error registering BMP280 in I2C%d\n", busno); + } + } + else + { + ret = -ENODEV; + } + + return ret; +} + diff --git a/boards/arm/rp2040/common/src/rp2040_common_bringup.c b/boards/arm/rp2040/common/src/rp2040_common_bringup.c index 7fdc2d89fc35e..d344772644b92 100644 --- a/boards/arm/rp2040/common/src/rp2040_common_bringup.c +++ b/boards/arm/rp2040/common/src/rp2040_common_bringup.c @@ -63,6 +63,11 @@ #include "rp2040_bmp180.h" #endif +#ifdef CONFIG_SENSORS_BMP280 +#include +#include "rp2040_bmp280.h" +#endif + #ifdef CONFIG_RP2040_PWM #include "rp2040_pwm.h" #include "rp2040_pwmdev.h" @@ -460,7 +465,16 @@ int rp2040_common_bringup(void) if (ret < 0) { syslog(LOG_ERR, "Failed to initialize BMP180 driver: %d\n", ret); - return ret; + } +#endif + +#ifdef CONFIG_SENSORS_BMP280 + /* Try to register BMP280 device in I2C0 */ + + ret = board_bmp280_initialize(0); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize BMP280 driver: %d\n", ret); } #endif diff --git a/boards/arm/rp2040/common/src/rp2040_common_initialize.c b/boards/arm/rp2040/common/src/rp2040_common_initialize.c index 6e86c52986acf..f2106d28f5fbc 100644 --- a/boards/arm/rp2040/common/src/rp2040_common_initialize.c +++ b/boards/arm/rp2040/common/src/rp2040_common_initialize.c @@ -31,6 +31,7 @@ #include "arm_internal.h" #include "rp2040_gpio.h" +#include "rp2040_uniqueid.h" /**************************************************************************** * Pre-processor Definitions @@ -94,6 +95,23 @@ void rp2040_common_earlyinitialize(void) RP2040_GPIO_FUNC_UART); /* RTS */ #endif #endif + +#if defined(CONFIG_RP2040_CLK_GPOUT0) + rp2040_gpio_set_function(RP2040_GPIO_PIN_CLK_GPOUT0, + RP2040_GPIO_FUNC_CLOCKS); +#endif +#if defined(CONFIG_RP2040_CLK_GPOUT1) + rp2040_gpio_set_function(RP2040_GPIO_PIN_CLK_GPOUT1, + RP2040_GPIO_FUNC_CLOCKS); +#endif +#if defined(CONFIG_RP2040_CLK_GPOUT2) + rp2040_gpio_set_function(RP2040_GPIO_PIN_CLK_GPOUT2, + RP2040_GPIO_FUNC_CLOCKS); +#endif +#if defined(CONFIG_RP2040_CLK_GPOUT3) + rp2040_gpio_set_function(RP2040_GPIO_PIN_CLK_GPOUT3, + RP2040_GPIO_FUNC_CLOCKS); +#endif } /**************************************************************************** @@ -106,6 +124,10 @@ void rp2040_common_earlyinitialize(void) void rp2040_common_initialize(void) { +#ifdef CONFIG_BOARDCTL_UNIQUEID + rp2040_uniqueid_initialize(); +#endif + /* Set default I2C pin */ #ifdef CONFIG_RP2040_I2C0 @@ -159,4 +181,17 @@ void rp2040_common_initialize(void) rp2040_gpio_setdir(CONFIG_RP2040_SPI1_CS_GPIO, true); rp2040_gpio_put(CONFIG_RP2040_SPI1_CS_GPIO, true); #endif + +#ifdef CONFIG_NET_W5500 + /* W5500 Reset output */ + + rp2040_gpio_setdir(CONFIG_RP2040_W5500_RST_GPIO, true); + rp2040_gpio_put(CONFIG_RP2040_W5500_RST_GPIO, false); + rp2040_gpio_set_function(CONFIG_RP2040_W5500_RST_GPIO, + RP2040_GPIO_FUNC_SIO); + + /* W5500 Interrupt input */ + + rp2040_gpio_init(CONFIG_RP2040_W5500_INT_GPIO); +#endif } diff --git a/boards/arm/rp2040/common/src/rp2040_uniqueid.c b/boards/arm/rp2040/common/src/rp2040_uniqueid.c new file mode 100644 index 0000000000000..653028c2bcc34 --- /dev/null +++ b/boards/arm/rp2040/common/src/rp2040_uniqueid.c @@ -0,0 +1,341 @@ +/**************************************************************************** + * boards/arm/rp2040/common/src/rp2040_uniqueid.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include "rp2040_uniqueid.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ROM_FUNC_CIF ROM_TABLE_CODE('I', 'F') +#define ROM_FUNC_FEX ROM_TABLE_CODE('E', 'X') +#define ROM_FUNC_FFC ROM_TABLE_CODE('F', 'C') + +#define QSPI_SS_CTRL_OUTOVER_LSB 8 +#define QSPI_SS_CTRL_OUTOVER_VALUE_LOW 0x2 +#define QSPI_SS_CTRL_OUTOVER_VALUE_HIGH 0x3 +#define QSPI_SS_CTRL_OUTOVER_BITS 0x00000300 +#define QSPI_SS_CTRL 0x4001800c +#define XIP_BASE 0x10000000 +#define XIP_SSI_SR 0x18000028 +#define XIP_SSI_DR0 0x18000060 +#define SSI_SR_TFNF_BITS 0x00000002 +#define SSI_SR_RFNE_BITS 0x00000008 +#define BOOT2_SIZE_WORDS 64 +#define REG_ALIAS_XOR_BITS (0x1u << 12u) + +#define ROM_TABLE_CODE(c1, c2) ((c1) | ((c2) << 8)) +#define hw_alias_check_addr(addr) ((uintptr_t)(addr)) +#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | hw_alias_check_addr(addr))) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +typedef volatile uint32_t io_rw_32; +typedef void (*rom_cif_fn)(void); +typedef void (*rom_fex_fn)(void); +typedef void (*rom_ffc_fn)(void); +typedef void (*rom_flash_enter_cmd_xip_fn)(void); +typedef void *(*rom_table_lookup_fn)(uint16_t *table, uint32_t code); + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static inline void __compiler_memory_barrier(void); +static inline void *rom_hword_as_ptr(uint16_t rom_address); +static inline uint32_t rom_table_code(uint8_t c1, uint8_t c2); +static void *rf_lookup(uint32_t code); +static void hw_xor_bits(io_rw_32 *addr, uint32_t mask); +static void hw_write_masked(io_rw_32 *addr, + uint32_t values, + uint32_t write_mask); +static void flash_cs_force (bool high); +void rp2040_flash_cmd(const uint8_t *txbuf, uint8_t *rxbuf, size_t count); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint8_t g_uniqueid[CONFIG_BOARDCTL_UNIQUEID_SIZE]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: __compiler_memory_barrier + * + * Description: + * Prevent compiler from moving memory access across this barrier. + * + ****************************************************************************/ + +static inline void __compiler_memory_barrier(void) +{ +} + +/**************************************************************************** + * Name: rom_hword_as_ptr + * + * Description: + * Converts a (well known) address value into a pointer to that address. + * + ****************************************************************************/ + +static inline void *rom_hword_as_ptr(uint16_t rom_address) +{ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Warray-bounds" + return (void *)(uintptr_t)*(uint16_t *)(uintptr_t)rom_address; +#pragma GCC diagnostic pop +} + +/**************************************************************************** + * Name: + * + * Description: + * Return a bootrom lookup code based on two ASCII characters. + * + * Input Parameters: + * uint8_t c1: first character + * uint8_t c2: second character + * + * Returned Value: + * A code to use with rf_lookup + * + ****************************************************************************/ + +static inline uint32_t rom_table_code(uint8_t c1, uint8_t c2) +{ + return ROM_TABLE_CODE((uint32_t) c1, (uint32_t) c2); +} + +/**************************************************************************** + * Name: rf_lookup + * + * Description: + * Lookup a bootrom function by code. + * + * Input Parameters: + * uint32_t code: A code from rom_table_code() + * + * Returned Value: + * a pointer to the function, or NULL if the code does not match any + * bootrom function + * + ****************************************************************************/ + +always_inline_function static void *rf_lookup(uint32_t code) +{ + rom_table_lookup_fn rom_table_lookup; + rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(0x18); + uint16_t *func_table = (uint16_t *) rom_hword_as_ptr(0x14); + return rom_table_lookup(func_table, code); +} + +/**************************************************************************** + * Name: hw_xor_bits + * + * Description: + * Helper function for flash_cs_force. + * + ****************************************************************************/ + +always_inline_function static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) +{ + *(io_rw_32 *) hw_xor_alias_untyped((volatile void *) addr) = mask; +} + +/**************************************************************************** + * Name: hw_write_masked + * + * Description: + * Helper function for flash_cs_force. + * + ****************************************************************************/ + +always_inline_function static void hw_write_masked(io_rw_32 *addr, + uint32_t values, + uint32_t write_mask) +{ + hw_xor_bits(addr, (*addr ^ values) & write_mask); +} + +/**************************************************************************** + * Name: flash_cs_force + * + * Description: + * Override the chip select line to flash chip. + * + * Input Parameters: + * bool high: true to force CS high, false to force low + * + ****************************************************************************/ + +noinline_function locate_code(".ram_code.flash_cs_force") +static void flash_cs_force (bool high) +{ + uint32_t field_val = high ? + QSPI_SS_CTRL_OUTOVER_VALUE_HIGH : + QSPI_SS_CTRL_OUTOVER_VALUE_LOW; + hw_write_masked((io_rw_32 *)QSPI_SS_CTRL, + field_val << QSPI_SS_CTRL_OUTOVER_LSB, + QSPI_SS_CTRL_OUTOVER_BITS + ); +} + +/**************************************************************************** + * Name: rp2040_flash_cmd + * + * Description: + * Send a command to flash chip and receive the result. + * + * Input Parameters: + * uint8_t* txbuf: Pointer to buffer to send + * uint8_t* rxbuf: Pointer to buffer to hold received value + * size_t count: Number of bytes to send / receive + * + ****************************************************************************/ + +noinline_function locate_code(".ram_code.rp2040_flash_cmd") +void rp2040_flash_cmd(const uint8_t *txbuf, uint8_t *rxbuf, size_t count) +{ + rom_cif_fn connect_internal_flash = (rom_cif_fn)rf_lookup(ROM_FUNC_CIF); + rom_fex_fn flash_exit_xip = (rom_fex_fn)rf_lookup(ROM_FUNC_FEX); + rom_ffc_fn flash_flush_cache = (rom_ffc_fn)rf_lookup(ROM_FUNC_FFC); + + uint32_t boot2_copyout[BOOT2_SIZE_WORDS]; + for (int i = 0; i < BOOT2_SIZE_WORDS; ++i) + boot2_copyout[i] = ((uint32_t *)XIP_BASE)[i]; + __compiler_memory_barrier(); + connect_internal_flash(); + flash_exit_xip(); + + flash_cs_force(0); + size_t tx_cnt = count; + size_t rx_cnt = count; + + const size_t max_in_flight = 16 - 2; + while (tx_cnt || rx_cnt) + { + uint32_t flags = *((uint32_t *)XIP_SSI_SR); + + bool can_put = !!(flags & SSI_SR_TFNF_BITS); + bool can_get = !!(flags & SSI_SR_RFNE_BITS); + + if (can_put && tx_cnt && rx_cnt - tx_cnt < max_in_flight) + { + *((uint8_t *)XIP_SSI_DR0) = *txbuf++; + --tx_cnt; + } + + if (can_get && rx_cnt) + { + *rxbuf++ = *((uint8_t *)XIP_SSI_DR0); + --rx_cnt; + } + } + + flash_cs_force(1); + flash_flush_cache(); + ((void (*)(void))((intptr_t)boot2_copyout + 1))(); /* re-enable xip */ +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rp2040_uniqueid_initialize + * + * Description: + * The RP2040 doesn't have a unique ID, so we load the ID from the + * connected flash chip. We use the flash ID to seed a simple xorshift + * PRNG. The PRNG then generates CONFIG_BOARDCTL_UNIQUEID_SIZE bytes, + * which we will use as the board's unique ID. + * + * Retrieving the flash id is somewhat slow and complex, so we only do + * this during initialization and store the result for later use. + * + * Assumptions/Limitations: + * This uniqueid implementation requires a flash chip. It should not be + * used on boards without flash. + * + ****************************************************************************/ + +void rp2040_uniqueid_initialize(void) +{ + uint64_t x; + uint8_t txbuf[RP2040_FLASH_ID_BUFFER_SIZE]; + uint8_t rxbuf[RP2040_FLASH_ID_BUFFER_SIZE]; + + memset(g_uniqueid, 0xac, CONFIG_BOARDCTL_UNIQUEID_SIZE); + memset(txbuf, 0, RP2040_FLASH_ID_BUFFER_SIZE); + memset(rxbuf, 0, RP2040_FLASH_ID_BUFFER_SIZE); + txbuf[0] = RP2040_FLASH_RUID_CMD; + + rp2040_flash_cmd(txbuf, rxbuf, RP2040_FLASH_ID_BUFFER_SIZE); + + /* xorshift PRNG: */ + + x = *(uint64_t *)(rxbuf + RP2040_FLASH_ID_BUFFER_OFFSET); + for (int i = 0; i < CONFIG_BOARDCTL_UNIQUEID_SIZE; i++) + { + x ^= x >> 12; + x ^= x << 25; + x ^= x >> 27; + g_uniqueid[i] = (uint8_t)((x * 0x2545f4914f6cdd1dull) >> 32); + } +} + +/**************************************************************************** + * Name: board_uniqueid + * + * Description: + * Return a unique ID associated with the board. + * + * Input Parameters: + * uniqueid - A reference to a writable memory location provided by the + * caller to receive the board unique ID. The memory memory referenced + * by this pointer must be at least CONFIG_BOARDCTL_UNIQUEID_SIZE in + * length. + * + * Returned Value: + * Zero (OK) is returned on success. Otherwize a negated errno value is + * returned indicating the nature of the failure. + * + ****************************************************************************/ + +int board_uniqueid(FAR uint8_t *uniqueid) +{ + memcpy(uniqueid, g_uniqueid, CONFIG_BOARDCTL_UNIQUEID_SIZE); + return OK; +} diff --git a/boards/arm/rp2040/common/src/rp2040_w5500.c b/boards/arm/rp2040/common/src/rp2040_w5500.c new file mode 100644 index 0000000000000..761b2f24cff0c --- /dev/null +++ b/boards/arm/rp2040/common/src/rp2040_w5500.c @@ -0,0 +1,209 @@ +/**************************************************************************** + * boards/arm/rp2040/common/src/rp2040_w5500.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "rp2040_spi.h" +#include "rp2040_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Sanity Check *************************************************************/ + +#if (CONFIG_RP2040_W5500_SPI_CH == 0) && !defined(CONFIG_RP2040_SPI0) +# error "W5500 configured to use SPI0, but SPI0 is not enabled" +#endif + +#if (CONFIG_RP2040_W5500_SPI_CH == 1) && !defined(CONFIG_RP2040_SPI1) +# error "W5500 configured to use SPI1, but SPI1 is not enabled" +#endif + +/* SPI Assumptions **********************************************************/ + +#define W5500_DEVNO 0 /* Only one W5500 */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct rp2040_lower_s +{ + const struct w5500_lower_s lower; /* Low-level MCU interface */ + xcpt_t handler; /* W5500 interrupt handler */ + void *arg; /* Argument that accompanies IRQ */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int rp2040_attach(const struct w5500_lower_s *lower, xcpt_t handler, + void *arg); +static void rp2040_enable(const struct w5500_lower_s *lower, bool enable); +static void rp2040_reset(const struct w5500_lower_s *lower, bool reset); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct rp2040_lower_s g_enclower = +{ + .lower = + { + .frequency = (CONFIG_RP2040_W5500_SPI_FREQ * 1000), + .spidevid = 0, + .mode = SPIDEV_MODE0, + .attach = rp2040_attach, + .enable = rp2040_enable, + .reset = rp2040_reset, + }, + .handler = NULL, + .arg = NULL +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rp2040_attach + * + * Description: + * Attaches the interrupt handler to the GPIO. + * + * Input Parameters: + * lower - W5500 lower half + * handler - The handler function + * arg - Argument to pass to handler + * + * Returned Value: + * Zero (OK) is returned on success. + * + ****************************************************************************/ + +static int rp2040_attach(const struct w5500_lower_s *lower, + xcpt_t handler, + void *arg) +{ + struct rp2040_lower_s *priv = (struct rp2040_lower_s *)lower; + + priv->handler = handler; + priv->arg = arg; + rp2040_gpio_irq_attach(CONFIG_RP2040_W5500_INT_GPIO, + RP2040_GPIO_INTR_LEVEL_LOW, + priv->handler, priv->arg); + return OK; +} + +/**************************************************************************** + * Name: rp2040_enable + * + * Description: + * Enables the W5500 interrupt handler. + * + * Input Parameters: + * lower - W5500 lower half + * enable - true to enable, false to disable + * + ****************************************************************************/ + +static void rp2040_enable(const struct w5500_lower_s *lower, bool enable) +{ + struct rp2040_lower_s *priv = (struct rp2040_lower_s *)lower; + + DEBUGASSERT(priv->handler); + if (enable) + { + rp2040_gpio_enable_irq(CONFIG_RP2040_W5500_INT_GPIO); + } + else + { + rp2040_gpio_disable_irq(CONFIG_RP2040_W5500_INT_GPIO); + } +} + +/**************************************************************************** + * Name: rp2040_reset + * + * Description: + * Brings the W5500 in or out of reset. + * + * Input Parameters: + * lower - W5500 lower half + * reset - true to reset, false to enable + * + ****************************************************************************/ + +static void rp2040_reset(const struct w5500_lower_s *lower, bool reset) +{ + rp2040_gpio_put(CONFIG_RP2040_W5500_RST_GPIO, !reset); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arm_netinitialize + * + * Description: + * Initializes the SPI and W5500 drivers. + * + ****************************************************************************/ + +void arm_netinitialize(void) +{ + struct spi_dev_s *spi; + int ret; + + spi = rp2040_spibus_initialize(CONFIG_RP2040_W5500_SPI_CH); + if (!spi) + { + nerr("ERROR: Failed to initialize SPI port %d\n", + CONFIG_RP2040_W5500_SPI_CH); + return; + } + + ret = w5500_initialize(spi, &g_enclower.lower, W5500_DEVNO); + if (ret < 0) + { + nerr("ERROR: Failed to bind SPI%d W5500 device %d: %d\n", + CONFIG_RP2040_W5500_SPI_CH, W5500_DEVNO, ret); + return; + } + + ninfo("Bound SPI%d to W5500 device %d\n", + CONFIG_RP2040_W5500_SPI_CH, W5500_DEVNO); +} + diff --git a/boards/arm/rp2040/pimoroni-tiny2040/configs/nshsram/defconfig b/boards/arm/rp2040/pimoroni-tiny2040/configs/nshsram/defconfig index 5915108f7e193..19a92fc8976fb 100644 --- a/boards/arm/rp2040/pimoroni-tiny2040/configs/nshsram/defconfig +++ b/boards/arm/rp2040/pimoroni-tiny2040/configs/nshsram/defconfig @@ -5,6 +5,7 @@ # You can then do "make savedefconfig" to generate a new defconfig file that includes your # modifications. # +# CONFIG_DEBUG_OPT_UNUSED_SECTIONS is not set # CONFIG_LIBC_LONG_LONG is not set # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set diff --git a/boards/arm/rp2040/raspberrypi-pico-w/configs/nshsram/defconfig b/boards/arm/rp2040/raspberrypi-pico-w/configs/nshsram/defconfig index f69cc437406fd..5f3d066d51b34 100644 --- a/boards/arm/rp2040/raspberrypi-pico-w/configs/nshsram/defconfig +++ b/boards/arm/rp2040/raspberrypi-pico-w/configs/nshsram/defconfig @@ -5,6 +5,7 @@ # You can then do "make savedefconfig" to generate a new defconfig file that includes your # modifications. # +# CONFIG_DEBUG_OPT_UNUSED_SECTIONS is not set # CONFIG_LIBC_LONG_LONG is not set # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set diff --git a/boards/arm/rp2040/raspberrypi-pico-w/src/Make.defs b/boards/arm/rp2040/raspberrypi-pico-w/src/Make.defs index ab19f20657148..c7e70ef9da3f0 100644 --- a/boards/arm/rp2040/raspberrypi-pico-w/src/Make.defs +++ b/boards/arm/rp2040/raspberrypi-pico-w/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/rp2040/raspberrypi-pico/src/Make.defs +# boards/arm/rp2040/raspberrypi-pico-w/src/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm/rp2040/raspberrypi-pico/configs/bmp280/defconfig b/boards/arm/rp2040/raspberrypi-pico/configs/bmp280/defconfig new file mode 100644 index 0000000000000..c0cbc66e581d4 --- /dev/null +++ b/boards/arm/rp2040/raspberrypi-pico/configs/bmp280/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_DATE is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_RP2040_UART0 is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="raspberrypi-pico" +CONFIG_ARCH_BOARD_RASPBERRYPI_PICO=y +CONFIG_ARCH_CHIP="rp2040" +CONFIG_ARCH_CHIP_RP2040=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=10450 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_EXAMPLES_BMP280=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_NSH_USBCONSOLE=y +CONFIG_RAM_SIZE=270336 +CONFIG_RAM_START=0x20000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RP2040_I2C0=y +CONFIG_RP2040_I2C=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_BMP280=y +CONFIG_START_DAY=9 +CONFIG_START_MONTH=2 +CONFIG_START_YEAR=2021 +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y diff --git a/boards/arm/rp2040/raspberrypi-pico/configs/nshsram/defconfig b/boards/arm/rp2040/raspberrypi-pico/configs/nshsram/defconfig index 5a5342830ef57..fc30f62f790a8 100644 --- a/boards/arm/rp2040/raspberrypi-pico/configs/nshsram/defconfig +++ b/boards/arm/rp2040/raspberrypi-pico/configs/nshsram/defconfig @@ -5,6 +5,7 @@ # You can then do "make savedefconfig" to generate a new defconfig file that includes your # modifications. # +# CONFIG_DEBUG_OPT_UNUSED_SECTIONS is not set # CONFIG_LIBC_LONG_LONG is not set # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set diff --git a/boards/arm/rp2040/raspberrypi-pico/include/board.h b/boards/arm/rp2040/raspberrypi-pico/include/board.h index e22882ee6f27d..01cae6cef3e20 100644 --- a/boards/arm/rp2040/raspberrypi-pico/include/board.h +++ b/boards/arm/rp2040/raspberrypi-pico/include/board.h @@ -67,6 +67,57 @@ #define BOARD_NGPIOIN 1 #define BOARD_NGPIOINT 1 +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_NLEDS 1 + +#define BOARD_LED_GREEN BOARD_LED1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* This LED is not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/rp2040_autoleds.c. The LED is used to encode + * OS-related events as follows: + * + * -------------------- ----------------------------- ------ + * SYMBOL Meaning LED + * -------------------- ----------------------------- ------ + */ + +#define LED_STARTED 0 /* NuttX has been started OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON */ +#define LED_INIRQ 2 /* In an interrupt N/C */ +#define LED_SIGNAL 2 /* In a signal handler N/C */ +#define LED_ASSERTION 2 /* An assertion failed N/C */ +#define LED_PANIC 3 /* The system has crashed FLASH */ +#undef LED_IDLE /* Not used */ + +/* Thus if the LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If the LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/* BUTTON definitions *******************************************************/ + +#define NUM_BUTTONS 2 + +#define BUTTON_USER1 0 +#define BUTTON_USER2 1 +#define BUTTON_USER1_BIT (1 << BUTTON_USER1) +#define BUTTON_USER2_BIT (1 << BUTTON_USER2) + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/boards/arm/rp2040/raspberrypi-pico/src/Make.defs b/boards/arm/rp2040/raspberrypi-pico/src/Make.defs index 212f994e83089..9bbcee7c7ce12 100644 --- a/boards/arm/rp2040/raspberrypi-pico/src/Make.defs +++ b/boards/arm/rp2040/raspberrypi-pico/src/Make.defs @@ -28,6 +28,16 @@ ifeq ($(CONFIG_DEV_GPIO),y) CSRCS += rp2040_gpio.c endif +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += rp2040_autoleds.c +else +CSRCS += rp2040_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) + CSRCS += rp2040_buttons.c +endif + DEPPATH += --dep-path board VPATH += :board CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/rp2040/raspberrypi-pico/src/rp2040_autoleds.c b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_autoleds.c new file mode 100644 index 0000000000000..bba81a6f8bef1 --- /dev/null +++ b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_autoleds.c @@ -0,0 +1,167 @@ +/**************************************************************************** + * boards/arm/rp2040/raspberrypi-pico/src/rp2040_autoleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* There are four LED status indicators located on the EVK Board. The + * functions of these LEDs include: + * + * - Main Power Supply(D3) + * Green: DC 5V main supply is normal. + * Red: J2 input voltage is over 5.6V. + * Off: The board is not powered. + * - Reset RED LED(D15) + * - OpenSDA LED(D16) + * - USER LED(D18) + * + * Only a single LED, D18, is under software control. + * + * This LED is not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/rp2040_autoleds.c. The LED is used to encode + * OS-related events as follows: + * + * -------------------- ----------------------- ------ + * SYMBOL Meaning LED + * -------------------- ----------------------- ------ + * + * LED_STARTED 0 NuttX has been started OFF + * LED_HEAPALLOCATE 0 Heap has been allocated OFF + * LED_IRQSENABLED 0 Interrupts enabled OFF + * LED_STACKCREATED 1 Idle stack created ON + * LED_INIRQ 2 In an interrupt N/C + * LED_SIGNAL 2 In a signal handler N/C + * LED_ASSERTION 2 An assertion failed N/C + * LED_PANIC 3 The system has crashed FLASH + * LED_IDLE Not used + * + * Thus if the LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If the LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "rp2040_gpio.h" + +#include "rp2040_pico.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rp2040_autoled_initialize + * + * Description: + * Initialize NuttX-controlled LED logic + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIO for output */ + + rp2040_gpio_init(GPIO_LED1); + rp2040_gpio_setdir(GPIO_LED1, true); +} + +/**************************************************************************** + * Name: board_autoled_on + * + * Description: + * Turn on the "logical" LED state + * + * Input Parameters: + * led - Identifies the "logical" LED state (see definitions in + * include/board.h) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void board_autoled_on(int led) +{ + bool ledon = true; + + switch (led) + { + case 0: /* LED Off */ + ledon = false; + break; + + case 2: /* LED No change */ + return; + + case 1: /* LED On */ + case 3: /* LED On */ + break; + } + + rp2040_gpio_put(GPIO_LED1, ledon); /* High illuminates */ +} + +/**************************************************************************** + * Name: board_autoled_off + * + * Description: + * Turn off the "logical" LED state + * + * Input Parameters: + * led - Identifies the "logical" LED state (see definitions in + * include/board.h) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case 0: /* LED Off */ + case 1: /* LED Off */ + case 3: /* LED Off */ + break; + + case 2: /* LED No change */ + return; + } + + rp2040_gpio_put(GPIO_LED1, false); /* High illuminates */ +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/rp2040/raspberrypi-pico/src/rp2040_bringup.c b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_bringup.c index a20a397c00798..e303691b0a3e7 100644 --- a/boards/arm/rp2040/raspberrypi-pico/src/rp2040_bringup.c +++ b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_bringup.c @@ -37,6 +37,10 @@ #include "rp2040_common_bringup.h" #endif /* CONFIG_ARCH_BOARD_COMMON */ +#ifdef CONFIG_USERLED +# include +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -59,5 +63,26 @@ int rp2040_bringup(void) /* --- Place any board specific bringup code here --- */ +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, \ + "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + return OK; } diff --git a/boards/arm/rp2040/raspberrypi-pico/src/rp2040_buttons.c b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_buttons.c new file mode 100644 index 0000000000000..1350cd24ec975 --- /dev/null +++ b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_buttons.c @@ -0,0 +1,177 @@ +/**************************************************************************** + * boards/arm/rp2040/raspberrypi-pico/src/rp2040_buttons.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "rp2040_gpio.h" +#include "rp2040_pico.h" + +#if defined(CONFIG_ARCH_BUTTONS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_INPUT_BUTTONS) && !defined(CONFIG_ARCH_IRQBUTTONS) +# error "The NuttX Buttons Driver depends on IRQ support to work!\n" +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Pin configuration for external raspberrypi-pico buttons. */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER1, GPIO_BTN_USER2 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. And we will use interrupts */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* Initialize input pin */ + + rp2040_gpio_init(g_buttons[i]); + + /* pull-up = false : pull-down = false */ + + rp2040_gpio_set_pulls(g_buttons[i], false, false); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = rp2040_gpio_get(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns + * an 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + /* Make sure the interrupt is disabled */ + + rp2040_gpio_disable_irq(g_buttons[id]); + + /* Attach the interrupt handler */ + + ret = rp2040_gpio_irq_attach(g_buttons[id], + RP2040_GPIO_INTR_EDGE_LOW, + irqhandler, + arg); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); + return ret; + } + + /* Enable interruption for this pin */ + + rp2040_gpio_enable_irq(g_buttons[id]); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/rp2040/raspberrypi-pico/src/rp2040_pico.h b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_pico.h index 21a77bd9e8057..c62cbe39d596f 100644 --- a/boards/arm/rp2040/raspberrypi-pico/src/rp2040_pico.h +++ b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_pico.h @@ -27,6 +27,23 @@ #include +/* LEDs */ + +#define GPIO_LED1 25 /* The board's LED is connected to this pin */ + +/* Buttons */ + +/* Buttons GPIO pins definition */ + +#define GPIO_BTN_USER1 16 +#define GPIO_BTN_USER2 17 + +/* Buttons IRQ definitions */ + +#define MIN_IRQBUTTON BUTTON_USER1 +#define MAX_IRQBUTTON BUTTON_USER2 +#define NUM_IRQBUTTONS (BUTTON_USER1 - BUTTON_USER2 + 1) + int rp2040_bringup(void); #ifdef CONFIG_DEV_GPIO diff --git a/boards/arm/rp2040/raspberrypi-pico/src/rp2040_userleds.c b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_userleds.c new file mode 100644 index 0000000000000..e91f47458fbb0 --- /dev/null +++ b/boards/arm/rp2040/raspberrypi-pico/src/rp2040_userleds.c @@ -0,0 +1,215 @@ +/**************************************************************************** + * boards/arm/rp2040/raspberrypi-pico/src/rp2040_userleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "rp2040_gpio.h" + +#include "rp2040_pico.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case(PM_NORMAL): + { + /* Restore normal LEDs operation */ + + board_userled(BOARD_LED, true); + } + break; + + case(PM_IDLE): + { + /* Entering IDLE mode - Turn leds off */ + + board_userled(BOARD_LED, false); + } + break; + + case(PM_STANDBY): + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case(PM_SLEEP): + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED GPIO for output */ + + rp2040_gpio_init(GPIO_LED1); + rp2040_gpio_setdir(GPIO_LED1, true); + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + rp2040_gpio_put(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + rp2040_gpio_put(GPIO_LED1, (ledset & BOARD_LED1_BIT)); +} + +/**************************************************************************** + * Name: rp2040_led_pminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void rp2040_led_pminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + board_autoled_on(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/rp2040/w5500-evb-pico/Kconfig b/boards/arm/rp2040/w5500-evb-pico/Kconfig new file mode 100644 index 0000000000000..f18119a9e7399 --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_W5500_EVB_PICO + +endif diff --git a/boards/arm/rp2040/w5500-evb-pico/configs/usbnsh/defconfig b/boards/arm/rp2040/w5500-evb-pico/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..abcc5acdbea8c --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/configs/usbnsh/defconfig @@ -0,0 +1,74 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_LIBC_LONG_LONG is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_DATE is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_RP2040_UART0 is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="w5500-evb-pico" +CONFIG_ARCH_BOARD_W5500_EVB_PICO=y +CONFIG_ARCH_CHIP="rp2040" +CONFIG_ARCH_CHIP_RP2040=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=10450 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DISABLE_POSIX_TIMERS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x08080808 +CONFIG_NETDEV_WORK_THREAD=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NET_ETH_PKTSIZE=1516 +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_ICMPv6=y +CONFIG_NET_ICMPv6_AUTOCONF=y +CONFIG_NET_ICMPv6_SOCKET=y +CONFIG_NET_IPv6=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NET_W5500=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_NSH_USBCONSOLE=y +CONFIG_RAM_SIZE=270336 +CONFIG_RAM_START=0x20000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RP2040_SPI0=y +CONFIG_RP2040_SPI=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=9 +CONFIG_START_MONTH=2 +CONFIG_START_YEAR=2021 +CONFIG_SYSTEM_DHCPC_RENEW6=y +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING6=y +CONFIG_SYSTEM_PING=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_USBDEV=y +CONFIG_USBDEV_BUSPOWERED=y diff --git a/boards/arm/rp2040/w5500-evb-pico/include/board.h b/boards/arm/rp2040/w5500-evb-pico/include/board.h new file mode 100644 index 0000000000000..fa0544991f2fe --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/include/board.h @@ -0,0 +1,172 @@ +/**************************************************************************** + * boards/arm/rp2040/w5500-evb-pico/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_RP2040_W5500_EVB_PICO_INCLUDE_BOARD_H +#define __BOARDS_ARM_RP2040_W5500_EVB_PICO_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "rp2040_i2cdev.h" +#include "rp2040_spidev.h" +#include "rp2040_i2sdev.h" + +#include "rp2040_spisd.h" + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +#define MHZ 1000000 + +#define BOARD_XOSC_FREQ (12 * MHZ) +#define BOARD_PLL_SYS_FREQ (125 * MHZ) +#define BOARD_PLL_USB_FREQ (48 * MHZ) + +#define BOARD_REF_FREQ (12 * MHZ) +#define BOARD_SYS_FREQ (125 * MHZ) +#define BOARD_PERI_FREQ (125 * MHZ) +#define BOARD_USB_FREQ (48 * MHZ) +#define BOARD_ADC_FREQ (48 * MHZ) +#define BOARD_RTC_FREQ 46875 + +#define BOARD_UART_BASEFREQ BOARD_PERI_FREQ + +#define BOARD_TICK_CLOCK (1 * MHZ) + +/* GPIO definitions *********************************************************/ + +#define BOARD_GPIO_LED_PIN 25 +#define BOARD_NGPIOOUT 1 +#define BOARD_NGPIOIN 1 +#define BOARD_NGPIOINT 1 + +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs + * in any way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_NLEDS 1 + +#define BOARD_LED_GREEN BOARD_LED1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* This LED is not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/rp2040_autoleds.c. The LED is used to encode + * OS-related events as follows: + * + * -------------------- ----------------------------- ------ + * SYMBOL Meaning LED + * -------------------- ----------------------------- ------ + */ + +#define LED_STARTED 0 /* NuttX has been started OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON */ +#define LED_INIRQ 2 /* In an interrupt N/C */ +#define LED_SIGNAL 2 /* In a signal handler N/C */ +#define LED_ASSERTION 2 /* An assertion failed N/C */ +#define LED_PANIC 3 /* The system has crashed FLASH */ +#undef LED_IDLE /* Not used */ + +/* Thus if the LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If the LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/* BUTTON definitions *******************************************************/ + +#define NUM_BUTTONS 2 + +#define BUTTON_USER1 0 +#define BUTTON_USER2 1 +#define BUTTON_USER1_BIT (1 << BUTTON_USER1) +#define BUTTON_USER2_BIT (1 << BUTTON_USER2) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: rp2040_boardearlyinitialize + * + * Description: + * This is mostly a wrapper around the early board initialization code + * common to all boards based on the RP2040. This implementation does + * additionaly set the board's status LED. + * + ****************************************************************************/ + +void rp2040_boardearlyinitialize(void); + +/**************************************************************************** + * Name: rp2040_boardinitialize + * + * Description: + * This is a wrapper around the board initialization code common to all + * boards based on the RP2040. + * + ****************************************************************************/ + +void rp2040_boardinitialize(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_RP2040_W5500_EVB_PICO_INCLUDE_BOARD_H */ diff --git a/boards/arm/rp2040/w5500-evb-pico/include/rp2040_i2cdev.h b/boards/arm/rp2040/w5500-evb-pico/include/rp2040_i2cdev.h new file mode 100644 index 0000000000000..63a2235e63cad --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/include/rp2040_i2cdev.h @@ -0,0 +1,76 @@ +/**************************************************************************** + * boards/arm/rp2040/w5500-evb-pico/include/rp2040_i2cdev.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_RP2040_W5500_EVB_PICO_INCLUDE_RP2040_I2CDEV_H +#define __BOARDS_ARM_RP2040_W5500_EVB_PICO_INCLUDE_RP2040_I2CDEV_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_i2cdev_initialize + * + * Description: + * Initialize i2c driver and register the /dev/i2c device. + * + * Input Parameters: + * bus - The RP2040 I2C bus to initialize. 0: I2C0, 1: I2C1. Which ones + * are actually available depends on the board configuration. + * + ****************************************************************************/ + +#ifdef CONFIG_RP2040_I2C_DRIVER +int board_i2cdev_initialize(int bus); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_RP2040_W5500_EVB_PICO_INCLUDE_RP2040_I2CDEV_H */ diff --git a/boards/arm/rp2040/w5500-evb-pico/include/rp2040_i2sdev.h b/boards/arm/rp2040/w5500-evb-pico/include/rp2040_i2sdev.h new file mode 100644 index 0000000000000..a3550c457e473 --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/include/rp2040_i2sdev.h @@ -0,0 +1,72 @@ +/**************************************************************************** + * boards/arm/rp2040/w5500-evb-pico/include/rp2040_i2sdev.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_RP2040_W5500_EVB_PICO_INCLUDE_RP2040_I2SDEV_H +#define __BOARDS_ARM_RP2040_W5500_EVB_PICO_INCLUDE_RP2040_I2SDEV_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_i2sdev_initialize + * + * Description: + * Initialize i2s driver and register the /dev/audio/pcm0 device. + * + ****************************************************************************/ + +#ifdef CONFIG_RP2040_I2S +int board_i2sdev_initialize(int bus); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_RP2040_W5500_EVB_PICO_INCLUDE_RP2040_I2SDEV_H */ diff --git a/boards/arm/rp2040/w5500-evb-pico/include/rp2040_spidev.h b/boards/arm/rp2040/w5500-evb-pico/include/rp2040_spidev.h new file mode 100644 index 0000000000000..a03b99f83d246 --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/include/rp2040_spidev.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * boards/arm/rp2040/w5500-evb-pico/include/rp2040_spidev.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_RP2040_W5500_EVB_PICO_INCLUDE_RP2040_SPIDEV_H +#define __BOARDS_ARM_RP2040_W5500_EVB_PICO_INCLUDE_RP2040_SPIDEV_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_spidev_initialize + * + * Description: + * Initialize spi driver and register the /dev/spi device. + * + ****************************************************************************/ + +int board_spidev_initialize(int bus); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_RP2040_W5500_EVB_PICO_INCLUDE_RP2040_SPIDEV_H */ diff --git a/boards/arm/rp2040/w5500-evb-pico/include/rp2040_spisd.h b/boards/arm/rp2040/w5500-evb-pico/include/rp2040_spisd.h new file mode 100644 index 0000000000000..e02bb0d45587a --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/include/rp2040_spisd.h @@ -0,0 +1,83 @@ +/**************************************************************************** + * boards/arm/rp2040/w5500-evb-pico/include/rp2040_spisd.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_RP2040_W5500_EVB_PICO_INCLUDE_RP2040_SPISD_H +#define __BOARDS_ARM_RP2040_W5500_EVB_PICO_INCLUDE_RP2040_SPISD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_spisd_initialize + * + * Description: + * Initialize the SPI-based SD card. + * + ****************************************************************************/ + +#ifdef CONFIG_RP2040_SPISD +int board_spisd_initialize(int minor, int bus); +#endif + +/**************************************************************************** + * Name: board_spisd_status + * + * Description: + * Get the status whether SD Card is present or not. + * + ****************************************************************************/ + +#ifdef CONFIG_RP2040_SPISD +uint8_t board_spisd_status(struct spi_dev_s *dev, uint32_t devid); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_RP2040_W5500_EVB_PICO_INCLUDE_RP2040_SPISD_H */ diff --git a/boards/arm/rp2040/w5500-evb-pico/scripts/Make.defs b/boards/arm/rp2040/w5500-evb-pico/scripts/Make.defs new file mode 100644 index 0000000000000..142657cba2750 --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/scripts/Make.defs @@ -0,0 +1,45 @@ +############################################################################ +# boards/arm/rp2040/w5500-evb-pico/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/tools/rp2040/Config.mk +include $(TOPDIR)/arch/arm/src/armv6-m/Toolchain.defs + +ifeq ($(CONFIG_RP2040_FLASH_BOOT),y) + LDSCRIPT = w5500-evb-pico-flash.ld +else + LDSCRIPT = w5500-evb-pico-sram.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 diff --git a/boards/arm/rp2040/w5500-evb-pico/scripts/w5500-evb-pico-flash.ld b/boards/arm/rp2040/w5500-evb-pico/scripts/w5500-evb-pico-flash.ld new file mode 100644 index 0000000000000..3e9ef0443c2ad --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/scripts/w5500-evb-pico-flash.ld @@ -0,0 +1,119 @@ +/**************************************************************************** + * boards/arm/rp2040/w5500-evb-pico/scripts/w5500-evb-pico-flash.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x10000000, LENGTH = 2048K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 264K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .flash_begin : { + __flash_binary_start = .; + } > flash + + .boot2 : { + __boot2_start__ = .; + KEEP (*(.boot2)) + __boot2_end__ = .; + } > flash + + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .ram_vectors (COPY) : { + *(.ram_vectors) + } > sram + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + *(.ram_code.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .flash_section : { + . = ALIGN(4*1024); + *(.flash.*) + } > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/rp2040/w5500-evb-pico/scripts/w5500-evb-pico-sram.ld b/boards/arm/rp2040/w5500-evb-pico/scripts/w5500-evb-pico-sram.ld new file mode 100644 index 0000000000000..dc48b6dc89ee8 --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/scripts/w5500-evb-pico-sram.ld @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/rp2040/w5500-evb-pico/scripts/w5500-evb-pico-sram.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x10000000, LENGTH = 2048K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 264K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) + +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + rp2040_start.o(.text) + . = ALIGN(256); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > sram + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > sram + + .ARM.extab : { + *(.ARM.extab*) + } > sram + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > sram + __exidx_end = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + *(.ram_code.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram + + .flash_section : { + . = ALIGN(4*1024); + *(.flash.*) + } > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/rp2040/w5500-evb-pico/src/Make.defs b/boards/arm/rp2040/w5500-evb-pico/src/Make.defs new file mode 100644 index 0000000000000..7cf5f83719a70 --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/src/Make.defs @@ -0,0 +1,43 @@ +############################################################################ +# boards/arm/rp2040/w5500-evb-pico/src/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = rp2040_boardinitialize.c +CSRCS += rp2040_appinit.c +CSRCS += rp2040_bringup.c + +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += rp2040_gpio.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += rp2040_autoleds.c +else +CSRCS += rp2040_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) + CSRCS += rp2040_buttons.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/rp2040/w5500-evb-pico/src/rp2040_appinit.c b/boards/arm/rp2040/w5500-evb-pico/src/rp2040_appinit.c new file mode 100644 index 0000000000000..46eb4004aed91 --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/src/rp2040_appinit.c @@ -0,0 +1,76 @@ +/**************************************************************************** + * boards/arm/rp2040/w5500-evb-pico/src/rp2040_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "rp2040_pico.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return rp2040_bringup(); +#endif +} diff --git a/boards/arm/rp2040/w5500-evb-pico/src/rp2040_autoleds.c b/boards/arm/rp2040/w5500-evb-pico/src/rp2040_autoleds.c new file mode 100644 index 0000000000000..4c1224ba3a454 --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/src/rp2040_autoleds.c @@ -0,0 +1,167 @@ +/**************************************************************************** + * boards/arm/rp2040/w5500-evb-pico/src/rp2040_autoleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* There are four LED status indicators located on the EVK Board. The + * functions of these LEDs include: + * + * - Main Power Supply(D3) + * Green: DC 5V main supply is normal. + * Red: J2 input voltage is over 5.6V. + * Off: The board is not powered. + * - Reset RED LED(D15) + * - OpenSDA LED(D16) + * - USER LED(D18) + * + * Only a single LED, D18, is under software control. + * + * This LED is not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/rp2040_autoleds.c. The LED is used to encode + * OS-related events as follows: + * + * -------------------- ----------------------- ------ + * SYMBOL Meaning LED + * -------------------- ----------------------- ------ + * + * LED_STARTED 0 NuttX has been started OFF + * LED_HEAPALLOCATE 0 Heap has been allocated OFF + * LED_IRQSENABLED 0 Interrupts enabled OFF + * LED_STACKCREATED 1 Idle stack created ON + * LED_INIRQ 2 In an interrupt N/C + * LED_SIGNAL 2 In a signal handler N/C + * LED_ASSERTION 2 An assertion failed N/C + * LED_PANIC 3 The system has crashed FLASH + * LED_IDLE Not used + * + * Thus if the LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If the LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "rp2040_gpio.h" + +#include "rp2040_pico.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rp2040_autoled_initialize + * + * Description: + * Initialize NuttX-controlled LED logic + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIO for output */ + + rp2040_gpio_init(GPIO_LED1); + rp2040_gpio_setdir(GPIO_LED1, true); +} + +/**************************************************************************** + * Name: board_autoled_on + * + * Description: + * Turn on the "logical" LED state + * + * Input Parameters: + * led - Identifies the "logical" LED state (see definitions in + * include/board.h) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void board_autoled_on(int led) +{ + bool ledon = true; + + switch (led) + { + case 0: /* LED Off */ + ledon = false; + break; + + case 2: /* LED No change */ + return; + + case 1: /* LED On */ + case 3: /* LED On */ + break; + } + + rp2040_gpio_put(GPIO_LED1, ledon); /* High illuminates */ +} + +/**************************************************************************** + * Name: board_autoled_off + * + * Description: + * Turn off the "logical" LED state + * + * Input Parameters: + * led - Identifies the "logical" LED state (see definitions in + * include/board.h) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case 0: /* LED Off */ + case 1: /* LED Off */ + case 3: /* LED Off */ + break; + + case 2: /* LED No change */ + return; + } + + rp2040_gpio_put(GPIO_LED1, false); /* High illuminates */ +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/rp2040/w5500-evb-pico/src/rp2040_boardinitialize.c b/boards/arm/rp2040/w5500-evb-pico/src/rp2040_boardinitialize.c new file mode 100644 index 0000000000000..6f7e31cf9efab --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/src/rp2040_boardinitialize.c @@ -0,0 +1,87 @@ +/**************************************************************************** + * boards/arm/rp2040/w5500-evb-pico/src/rp2040_boardinitialize.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "rp2040_gpio.h" + +#ifdef CONFIG_ARCH_BOARD_COMMON +#include "rp2040_common_initialize.h" +#endif /* CONFIG_ARCH_BOARD_COMMON */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rp2040_boardearlyinitialize + * + * Description: + * + ****************************************************************************/ + +void rp2040_boardearlyinitialize(void) +{ + #ifdef CONFIG_ARCH_BOARD_COMMON + rp2040_common_earlyinitialize(); + #endif + + /* --- Place any board specific early initialization here --- */ + + /* Set board LED pin */ + + rp2040_gpio_init(BOARD_GPIO_LED_PIN); + rp2040_gpio_setdir(BOARD_GPIO_LED_PIN, true); + rp2040_gpio_put(BOARD_GPIO_LED_PIN, true); +} + +/**************************************************************************** + * Name: rp2040_boardinitialize + * + * Description: + * + ****************************************************************************/ + +void rp2040_boardinitialize(void) +{ + #ifdef CONFIG_ARCH_BOARD_COMMON + rp2040_common_initialize(); + #endif + + /* --- Place any board specific initialization here --- */ +} diff --git a/boards/arm/rp2040/w5500-evb-pico/src/rp2040_bringup.c b/boards/arm/rp2040/w5500-evb-pico/src/rp2040_bringup.c new file mode 100644 index 0000000000000..11e45f6704dd6 --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/src/rp2040_bringup.c @@ -0,0 +1,88 @@ +/**************************************************************************** + * boards/arm/rp2040/w5500-evb-pico/src/rp2040_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include + +#include "rp2040_pico.h" + +#ifdef CONFIG_ARCH_BOARD_COMMON +#include "rp2040_common_bringup.h" +#endif /* CONFIG_ARCH_BOARD_COMMON */ + +#ifdef CONFIG_USERLED +# include +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rp2040_bringup + ****************************************************************************/ + +int rp2040_bringup(void) +{ +#ifdef CONFIG_ARCH_BOARD_COMMON + + int ret = rp2040_common_bringup(); + if (ret < 0) + { + return ret; + } + +#endif /* CONFIG_ARCH_BOARD_COMMON */ + + /* --- Place any board specific bringup code here --- */ + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, \ + "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_INPUT_BUTTONS + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + + return OK; +} diff --git a/boards/arm/rp2040/w5500-evb-pico/src/rp2040_buttons.c b/boards/arm/rp2040/w5500-evb-pico/src/rp2040_buttons.c new file mode 100644 index 0000000000000..8d53fd19d5b4d --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/src/rp2040_buttons.c @@ -0,0 +1,177 @@ +/**************************************************************************** + * boards/arm/rp2040/w5500-evb-pico/src/rp2040_buttons.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "rp2040_gpio.h" +#include "rp2040_pico.h" + +#if defined(CONFIG_ARCH_BUTTONS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_INPUT_BUTTONS) && !defined(CONFIG_ARCH_IRQBUTTONS) +# error "The NuttX Buttons Driver depends on IRQ support to work!\n" +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Pin configuration for external w5500-evb-pico buttons. */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_USER1, GPIO_BTN_USER2 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. And we will use interrupts */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* Initialize input pin */ + + rp2040_gpio_init(g_buttons[i]); + + /* pull-up = false : pull-down = false */ + + rp2040_gpio_set_pulls(g_buttons[i], false, false); + } + + return NUM_BUTTONS; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint32_t ret = 0; + int i; + + /* Check that state of each key */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + /* A LOW value means that the key is pressed. */ + + bool released = rp2040_gpio_get(g_buttons[i]); + + /* Accumulate the set of depressed (not released) keys */ + + if (!released) + { + ret |= (1 << i); + } + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns + * an 32-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret = -EINVAL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + /* Make sure the interrupt is disabled */ + + rp2040_gpio_disable_irq(g_buttons[id]); + + /* Attach the interrupt handler */ + + ret = rp2040_gpio_irq_attach(g_buttons[id], + RP2040_GPIO_INTR_EDGE_LOW, + irqhandler, + arg); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); + return ret; + } + + /* Enable interruption for this pin */ + + rp2040_gpio_enable_irq(g_buttons[id]); + } + + return ret; +} +#endif + +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/boards/arm/rp2040/w5500-evb-pico/src/rp2040_gpio.c b/boards/arm/rp2040/w5500-evb-pico/src/rp2040_gpio.c new file mode 100644 index 0000000000000..cec12768f3134 --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/src/rp2040_gpio.c @@ -0,0 +1,392 @@ +/**************************************************************************** + * boards/arm/rp2040/w5500-evb-pico/src/rp2040_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include "arm_internal.h" +#include "chip.h" +#include "rp2040_gpio.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/* Output pins. GPIO25 is onboard LED any other outputs could be used. + */ + +#define GPIO_OUT1 25 + +/* Input pins. + */ + +#define GPIO_IN1 6 + +/* Interrupt pins. + */ + +#define GPIO_IRQPIN1 14 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct rp2040gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct rp2040gpint_dev_s +{ + struct rp2040gpio_dev_s rp2040gpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +#endif + +#if BOARD_NGPIOIN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value); +#endif + +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; + +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1 +}; + +static struct rp2040gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOIN > 0 +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; + +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1 +}; + +static struct rp2040gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOINT > 0 +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; + +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_IRQPIN1, +}; + +static struct rp2040gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpout_read + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct rp2040gpio_dev_s *rp2040gpio = + (struct rp2040gpio_dev_s *)dev; + + DEBUGASSERT(rp2040gpio != NULL && value != NULL); + DEBUGASSERT(rp2040gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = rp2040_gpio_get(g_gpiooutputs[rp2040gpio->id]); + return OK; +} + +/**************************************************************************** + * Name: gpout_write + ****************************************************************************/ + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct rp2040gpio_dev_s *rp2040gpio = + (struct rp2040gpio_dev_s *)dev; + + DEBUGASSERT(rp2040gpio != NULL); + DEBUGASSERT(rp2040gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + rp2040_gpio_put(g_gpiooutputs[rp2040gpio->id], value); + return OK; +} +#endif + +/**************************************************************************** + * Name: gpin_read + ****************************************************************************/ + +#if BOARD_NGPIOIN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value) +{ + struct rp2040gpio_dev_s *rp2040gpio = + (struct rp2040gpio_dev_s *)dev; + + DEBUGASSERT(rp2040gpio != NULL && value != NULL); + DEBUGASSERT(rp2040gpio->id < BOARD_NGPIOIN); + gpioinfo("Reading... pin %d\n", (int)g_gpioinputs[rp2040gpio->id]); + + *value = rp2040_gpio_get(g_gpioinputs[rp2040gpio->id]); + return OK; +} +#endif + +/**************************************************************************** + * Name: rp2040gpio_interrupt + ****************************************************************************/ + +#if BOARD_NGPIOINT > 0 +static int rp2040gpio_interrupt(int irq, void *context, void *arg) +{ + struct rp2040gpint_dev_s *rp2040gpint = + (struct rp2040gpint_dev_s *)arg; + + DEBUGASSERT(rp2040gpint != NULL && rp2040gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", rp2040gpint->callback); + + rp2040gpint->callback(&rp2040gpint->rp2040gpio.gpio, + rp2040gpint->rp2040gpio.id); + return OK; +} + +/**************************************************************************** + * Name: gpint_read + ****************************************************************************/ + +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct rp2040gpint_dev_s *rp2040gpint = + (struct rp2040gpint_dev_s *)dev; + + DEBUGASSERT(rp2040gpint != NULL && value != NULL); + DEBUGASSERT(rp2040gpint->rp2040gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = rp2040_gpio_get(g_gpiointinputs[rp2040gpint->rp2040gpio.id]); + return OK; +} + +/**************************************************************************** + * Name: gpint_attach + ****************************************************************************/ + +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct rp2040gpint_dev_s *rp2040gpint = + (struct rp2040gpint_dev_s *)dev; + int irq = g_gpiointinputs[rp2040gpint->rp2040gpio.id]; + int ret; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + rp2040_gpio_disable_irq(irq); + ret = rp2040_gpio_irq_attach(irq, + RP2040_GPIO_INTR_EDGE_LOW, + rp2040gpio_interrupt, + &g_gpint[rp2040gpint->rp2040gpio.id]); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); + return ret; + } + + gpioinfo("Attach %p\n", callback); + rp2040gpint->callback = callback; + return OK; +} + +/**************************************************************************** + * Name: gpint_enable + ****************************************************************************/ + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct rp2040gpint_dev_s *rp2040gpint = + (struct rp2040gpint_dev_s *)dev; + int irq = g_gpiointinputs[rp2040gpint->rp2040gpio.id]; + + if (enable) + { + if (rp2040gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + rp2040_gpio_enable_irq(irq); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + rp2040_gpio_disable_irq(irq); + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rp2040_dev_gpio_init + ****************************************************************************/ + +int rp2040_dev_gpio_init(void) +{ + int i; + int pincount = 0; + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, g_gpiooutputs[i]); + + /* Configure the pins that will be used as output */ + + rp2040_gpio_init(g_gpiooutputs[i]); + rp2040_gpio_setdir(g_gpiooutputs[i], true); + rp2040_gpio_put(g_gpiooutputs[i], false); + + pincount++; + } +#endif + + pincount = 0; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register(&g_gpin[i].gpio, g_gpioinputs[i]); + + /* Configure the pins that will be used as INPUT */ + + rp2040_gpio_init(g_gpioinputs[i]); + + pincount++; + } +#endif + + pincount = 0; + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].rp2040gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].rp2040gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].rp2040gpio.id = i; + gpio_pin_register(&g_gpint[i].rp2040gpio.gpio, g_gpiointinputs[i]); + + /* Configure the pins that will be used as interrupt input */ + + rp2040_gpio_init(g_gpiointinputs[i]); + + /* pull-up = false : pull-down = true */ + + rp2040_gpio_set_pulls(g_gpiointinputs[i], false, true); + + pincount++; + } +#endif + + return OK; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/rp2040/w5500-evb-pico/src/rp2040_pico.h b/boards/arm/rp2040/w5500-evb-pico/src/rp2040_pico.h new file mode 100644 index 0000000000000..c30da6d14ad81 --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/src/rp2040_pico.h @@ -0,0 +1,53 @@ +/**************************************************************************** + * boards/arm/rp2040/w5500-evb-pico/src/rp2040_pico.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_RP2040_W5500_EVB_PICO_SRC_RP2040_PICO_H +#define __BOARDS_ARM_RP2040_W5500_EVB_PICO_SRC_RP2040_PICO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/* LEDs */ + +#define GPIO_LED1 25 /* The board's LED is connected to this pin */ + +/* Buttons */ + +/* Buttons GPIO pins definition */ + +#define GPIO_BTN_USER1 16 +#define GPIO_BTN_USER2 17 + +/* Buttons IRQ definitions */ + +#define MIN_IRQBUTTON BUTTON_USER1 +#define MAX_IRQBUTTON BUTTON_USER2 +#define NUM_IRQBUTTONS (BUTTON_USER1 - BUTTON_USER2 + 1) + +int rp2040_bringup(void); + +#ifdef CONFIG_DEV_GPIO +int rp2040_dev_gpio_init(void); +#endif + +#endif /* __BOARDS_ARM_RP2040_W5500_EVB_PICO_SRC_RP2040_PICO_H */ diff --git a/boards/arm/rp2040/w5500-evb-pico/src/rp2040_userleds.c b/boards/arm/rp2040/w5500-evb-pico/src/rp2040_userleds.c new file mode 100644 index 0000000000000..950419129a54d --- /dev/null +++ b/boards/arm/rp2040/w5500-evb-pico/src/rp2040_userleds.c @@ -0,0 +1,215 @@ +/**************************************************************************** + * boards/arm/rp2040/w5500-evb-pico/src/rp2040_userleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "rp2040_gpio.h" + +#include "rp2040_pico.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED1, +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* LED Power Management */ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_PM +static struct pm_callback_s g_ledscb = +{ + .notify = led_pm_notify, + .prepare = led_pm_prepare, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: led_pm_notify + * + * Description: + * Notify the driver of new power state. This callback is called after + * all drivers have had the opportunity to prepare for the new power state. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static void led_pm_notify(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + switch (pmstate) + { + case(PM_NORMAL): + { + /* Restore normal LEDs operation */ + + board_userled(BOARD_LED, true); + } + break; + + case(PM_IDLE): + { + /* Entering IDLE mode - Turn leds off */ + + board_userled(BOARD_LED, false); + } + break; + + case(PM_STANDBY): + { + /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ + } + break; + + case(PM_SLEEP): + { + /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ + } + break; + + default: + { + /* Should not get here */ + } + break; + } +} +#endif + +/**************************************************************************** + * Name: led_pm_prepare + * + * Description: + * Request the driver to prepare for a new power state. This is a warning + * that the system is about to enter into a new power state. The driver + * should begin whatever operations that may be required to enter power + * state. The driver may abort the state change mode by returning a + * non-zero value from the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_PM +static int led_pm_prepare(struct pm_callback_s *cb, int domain, + enum pm_state_e pmstate) +{ + /* No preparation to change power modes is required by the LEDs driver. + * We always accept the state change by returning OK. + */ + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED GPIO for output */ + + rp2040_gpio_init(GPIO_LED1); + rp2040_gpio_setdir(GPIO_LED1, true); + + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + rp2040_gpio_put(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + rp2040_gpio_put(GPIO_LED1, (ledset & BOARD_LED1_BIT)); +} + +/**************************************************************************** + * Name: rp2040_led_pminitialize + ****************************************************************************/ + +#ifdef CONFIG_PM +void rp2040_led_pminitialize(void) +{ + /* Register to receive power management callbacks */ + + int ret = pm_register(&g_ledscb); + if (ret != OK) + { + board_autoled_on(LED_ASSERTION); + } +} +#endif /* CONFIG_PM */ + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/boards/arm/rp2040/waveshare-rp2040-lcd-1.28/configs/lvgl/defconfig b/boards/arm/rp2040/waveshare-rp2040-lcd-1.28/configs/lvgl/defconfig index 849234adc7384..ec536e71be1ff 100644 --- a/boards/arm/rp2040/waveshare-rp2040-lcd-1.28/configs/lvgl/defconfig +++ b/boards/arm/rp2040/waveshare-rp2040-lcd-1.28/configs/lvgl/defconfig @@ -38,17 +38,13 @@ CONFIG_LCD_DEV=y CONFIG_LCD_GC9A01=y CONFIG_LCD_GC9A01_BGR=y CONFIG_LCD_GC9A01_FREQUENCY=50000000 -CONFIG_LV_COLOR_16_SWAP=y -CONFIG_LV_DEMO_WIDGETS_SLIDESHOW=y CONFIG_LV_MEM_SIZE_KILOBYTES=48 -CONFIG_LV_PORT_LCDDEV_FULL_SCREEN_BUFFER=y -CONFIG_LV_PORT_USE_LCDDEV=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" -CONFIG_LV_USE_DEMO_BENCHMARK=y CONFIG_LV_USE_DEMO_STRESS=y CONFIG_LV_USE_DEMO_WIDGETS=y CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_LCD=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/rp2040/waveshare-rp2040-lcd-1.28/configs/nshsram/defconfig b/boards/arm/rp2040/waveshare-rp2040-lcd-1.28/configs/nshsram/defconfig index f4e28c41f2be0..850afe706d276 100644 --- a/boards/arm/rp2040/waveshare-rp2040-lcd-1.28/configs/nshsram/defconfig +++ b/boards/arm/rp2040/waveshare-rp2040-lcd-1.28/configs/nshsram/defconfig @@ -5,6 +5,7 @@ # You can then do "make savedefconfig" to generate a new defconfig file that includes your # modifications. # +# CONFIG_DEBUG_OPT_UNUSED_SECTIONS is not set # CONFIG_LIBC_LONG_LONG is not set # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set diff --git a/boards/arm/rp2040/waveshare-rp2040-lcd-1.28/scripts/Make.defs b/boards/arm/rp2040/waveshare-rp2040-lcd-1.28/scripts/Make.defs index 1ed7684fca819..76024c0da45dc 100644 --- a/boards/arm/rp2040/waveshare-rp2040-lcd-1.28/scripts/Make.defs +++ b/boards/arm/rp2040/waveshare-rp2040-lcd-1.28/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/rp2040/raspberrypi-pico/scripts/Make.defs +# boards/arm/rp2040/waveshare-rp2040-lcd-1.28/scripts/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm/rp2040/waveshare-rp2040-lcd-1.28/src/Make.defs b/boards/arm/rp2040/waveshare-rp2040-lcd-1.28/src/Make.defs index 212f994e83089..b901b1c6da99b 100644 --- a/boards/arm/rp2040/waveshare-rp2040-lcd-1.28/src/Make.defs +++ b/boards/arm/rp2040/waveshare-rp2040-lcd-1.28/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/rp2040/raspberrypi-pico/src/Make.defs +# boards/arm/rp2040/waveshare-rp2040-lcd-1.28/src/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm/s32k1xx/rddrone-bms772/include/nsh_romfsimg.h b/boards/arm/s32k1xx/rddrone-bms772/include/nsh_romfsimg.h deleted file mode 100644 index 1517f0b65c3cf..0000000000000 --- a/boards/arm/s32k1xx/rddrone-bms772/include/nsh_romfsimg.h +++ /dev/null @@ -1,230 +0,0 @@ -/**************************************************************************** - * boards/arm/s32k1xx/rddrone-bms772/include/nsh_romfsimg.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Copyright 2022 NXP */ - -#ifndef __BOARDS_ARM_S32K1XX_RDDRONE_BMS772_INCLUDE_NSH_ROMFSIMG_H -#define __BOARDS_ARM_S32K1XX_RDDRONE_BMS772_INCLUDE_NSH_ROMFSIMG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifdef CONFIG_DEBUG_FEATURES - -/* Full init script is used, including a call to the free command to show the - * memory usage after board initialization has finished. - */ - -const unsigned char aligned_data(4) romfs_img[] = -{ - 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x01, 0xb0, - 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0x00, 0x00, 0x00, 0x00 -}; -const unsigned int romfs_img_len = 1024; - -#else /* !CONFIG_DEBUG_FEATURES */ - -/* Init script does not call the free command to show available memory */ - -const unsigned char aligned_data(4) romfs_img[] = -{ - 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x01, 0xb0, - 0x4e, 0x7a, 0x78, 0x04, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56, - 0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, - 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, - 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, - 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x68, 0x2d, 0x96, 0x03, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x7a, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; -const unsigned int romfs_img_len = 1024; - -#endif /* CONFIG_DEBUG_FEATURES */ -#endif /* __BOARDS_ARM_S32K1XX_RDDRONE_BMS772_INCLUDE_NSH_ROMFSIMG_H */ diff --git a/boards/arm/s32k1xx/rddrone-bms772/src/Makefile b/boards/arm/s32k1xx/rddrone-bms772/src/Makefile index defcc4e21b08f..7491c5f33df65 100644 --- a/boards/arm/s32k1xx/rddrone-bms772/src/Makefile +++ b/boards/arm/s32k1xx/rddrone-bms772/src/Makefile @@ -67,4 +67,8 @@ ifeq ($(CONFIG_SMBUS_SBD),y) CSRCS += s32k1xx_smbus_sbd.c endif +ifeq ($(CONFIG_ETC_ROMFS),y) +CSRCS += etc_romfs.c +endif + include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/s32k1xx/rddrone-bms772/src/etc_romfs.c b/boards/arm/s32k1xx/rddrone-bms772/src/etc_romfs.c new file mode 100644 index 0000000000000..a5065a263f726 --- /dev/null +++ b/boards/arm/s32k1xx/rddrone-bms772/src/etc_romfs.c @@ -0,0 +1,230 @@ +/**************************************************************************** + * boards/arm/s32k1xx/rddrone-bms772/src/etc_romfs.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Copyright 2022 NXP */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_FEATURES + +/* Full init script is used, including a call to the free command to show the + * memory usage after board initialization has finished. + */ + +const unsigned char romfs_img[] = +{ + 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x01, 0xb0, + 0x98, 0xcd, 0xf3, 0x32, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56, + 0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; +const unsigned int romfs_img_len = 1024; + +#endif /* CONFIG_DEBUG_FEATURES */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/boards/arm/sama5/giant-board/scripts/dramboot.ld b/boards/arm/sama5/giant-board/scripts/dramboot.ld index a19c2f3da04de..6c8ed837370b4 100644 --- a/boards/arm/sama5/giant-board/scripts/dramboot.ld +++ b/boards/arm/sama5/giant-board/scripts/dramboot.ld @@ -88,6 +88,15 @@ SECTIONS _edata = ABSOLUTE(.); } > sdram + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > sdram + .bss : { _sbss = ABSOLUTE(.); @@ -98,15 +107,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > sdram - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > sdram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/giant-board/scripts/isram.ld b/boards/arm/sama5/giant-board/scripts/isram.ld index 2beb3044b032c..192d2be98d5a7 100644 --- a/boards/arm/sama5/giant-board/scripts/isram.ld +++ b/boards/arm/sama5/giant-board/scripts/isram.ld @@ -84,6 +84,15 @@ SECTIONS _edata = ABSOLUTE(.); } > isram + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > isram + .bss : { _sbss = ABSOLUTE(.); @@ -94,15 +103,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > isram - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > isram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/giant-board/scripts/uboot.ld b/boards/arm/sama5/giant-board/scripts/uboot.ld index 5e323a45750b1..0c3775da8e193 100644 --- a/boards/arm/sama5/giant-board/scripts/uboot.ld +++ b/boards/arm/sama5/giant-board/scripts/uboot.ld @@ -89,6 +89,15 @@ SECTIONS _edata = ABSOLUTE(.); } > sdram + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > sdram + .bss : { _sbss = ABSOLUTE(.); @@ -99,15 +108,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > sdram - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > sdram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/jupiter-nano/configs/sdmmc-nsh-net-resolvconf/defconfig b/boards/arm/sama5/jupiter-nano/configs/sdmmc-nsh-net-resolvconf/defconfig index 1a49bd8c7ce12..6e63c1b7ea467 100644 --- a/boards/arm/sama5/jupiter-nano/configs/sdmmc-nsh-net-resolvconf/defconfig +++ b/boards/arm/sama5/jupiter-nano/configs/sdmmc-nsh-net-resolvconf/defconfig @@ -31,6 +31,7 @@ CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_ROMFS=y CONFIG_EXAMPLES_HELLO=y CONFIG_EXAMPLES_TCPBLASTER=y CONFIG_EXAMPLES_TCPECHO=y @@ -74,13 +75,11 @@ CONFIG_NET_TCP_NOTIFIER=y CONFIG_NET_TCP_WRITE_BUFFERS=y CONFIG_NET_UDP=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_PROMPT_STRING="nsh> " CONFIG_NSH_QUOTE=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=268435456 CONFIG_RAM_START=0x20000000 diff --git a/boards/arm/sama5/jupiter-nano/include/nsh_romfsimg.h b/boards/arm/sama5/jupiter-nano/include/nsh_romfsimg.h deleted file mode 100644 index 7754a8b092e95..0000000000000 --- a/boards/arm/sama5/jupiter-nano/include/nsh_romfsimg.h +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/sama5/jupiter-nano/include/nsh_romfsimg.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -const unsigned char aligned_data(4) romfs_img[] = -{ - 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x01, 0x30, - 0x8b, 0x5f, 0xf8, 0x70, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56, - 0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, - 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, - 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, - 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x68, 0x2d, 0x96, 0x03, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xb5, 0x67, 0x75, - 0x72, 0x63, 0x2e, 0x73, 0x79, 0x73, 0x69, 0x6e, 0x69, 0x74, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x2b, 0x8d, 0x9c, 0xab, 0xdb, 0x72, 0x63, 0x53, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x69, 0x66, 0x63, 0x6f, 0x6e, 0x66, 0x69, 0x67, 0x20, 0x65, 0x74, 0x68, - 0x30, 0x20, 0x31, 0x30, 0x2e, 0x30, 0x2e, 0x30, 0x2e, 0x32, 0x0a, 0x69, - 0x66, 0x75, 0x70, 0x20, 0x65, 0x74, 0x68, 0x30, 0x0a, 0x74, 0x65, 0x6c, - 0x6e, 0x65, 0x74, 0x64, 0x20, 0x26, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, - 0xd1, 0xff, 0xfe, 0x90, 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0xe0, - 0x2e, 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; -unsigned int romfs_img_len = 1024; diff --git a/boards/arm/sama5/jupiter-nano/scripts/Make.defs b/boards/arm/sama5/jupiter-nano/scripts/Make.defs index 0204f78fedc60..38983443dfcbf 100644 --- a/boards/arm/sama5/jupiter-nano/scripts/Make.defs +++ b/boards/arm/sama5/jupiter-nano/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/sama5/sama5d2-xult/scripts/Make.defs +# boards/arm/sama5/jupiter-nano/scripts/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm/sama5/jupiter-nano/scripts/dramboot.ld b/boards/arm/sama5/jupiter-nano/scripts/dramboot.ld index 23bd38e06e5c5..fe28b4245c710 100644 --- a/boards/arm/sama5/jupiter-nano/scripts/dramboot.ld +++ b/boards/arm/sama5/jupiter-nano/scripts/dramboot.ld @@ -88,6 +88,15 @@ SECTIONS _edata = ABSOLUTE(.); } > sdram + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > sdram + .bss : { _sbss = ABSOLUTE(.); @@ -98,15 +107,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > sdram - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > sdram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/jupiter-nano/scripts/isram.ld b/boards/arm/sama5/jupiter-nano/scripts/isram.ld index 857d75d3b791d..f1f309662efbc 100644 --- a/boards/arm/sama5/jupiter-nano/scripts/isram.ld +++ b/boards/arm/sama5/jupiter-nano/scripts/isram.ld @@ -84,6 +84,15 @@ SECTIONS _edata = ABSOLUTE(.); } > isram + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > isram + .bss : { _sbss = ABSOLUTE(.); @@ -94,15 +103,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > isram - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > isram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/jupiter-nano/scripts/uboot.ld b/boards/arm/sama5/jupiter-nano/scripts/uboot.ld index af8359b069462..2045a6caca00f 100644 --- a/boards/arm/sama5/jupiter-nano/scripts/uboot.ld +++ b/boards/arm/sama5/jupiter-nano/scripts/uboot.ld @@ -89,6 +89,15 @@ SECTIONS _edata = ABSOLUTE(.); } > sdram + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > sdram + .bss : { _sbss = ABSOLUTE(.); @@ -99,15 +108,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > sdram - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > sdram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/jupiter-nano/src/Makefile b/boards/arm/sama5/jupiter-nano/src/Makefile index 48cbb39e9484b..5c6a583e88fa0 100644 --- a/boards/arm/sama5/jupiter-nano/src/Makefile +++ b/boards/arm/sama5/jupiter-nano/src/Makefile @@ -124,4 +124,8 @@ ifeq ($(CONFIG_BOARDCTL_RESET),y) CSRCS += sam_reset.c endif +ifeq ($(CONFIG_ETC_ROMFS),y) +CSRCS += etc_romfs.c +endif + include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/sama5/jupiter-nano/src/etc_romfs.c b/boards/arm/sama5/jupiter-nano/src/etc_romfs.c new file mode 100644 index 0000000000000..da472ddd5afe6 --- /dev/null +++ b/boards/arm/sama5/jupiter-nano/src/etc_romfs.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * boards/arm/sama5/jupiter-nano/src/etc_romfs.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +const unsigned char romfs_img[] = +{ + 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x01, 0x30, + 0x8b, 0x5f, 0xf8, 0x70, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56, + 0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, + 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, + 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x68, 0x2d, 0x96, 0x03, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xb5, 0x67, 0x75, + 0x72, 0x63, 0x2e, 0x73, 0x79, 0x73, 0x69, 0x6e, 0x69, 0x74, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x2b, 0x8d, 0x9c, 0xab, 0xdb, 0x72, 0x63, 0x53, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x69, 0x66, 0x63, 0x6f, 0x6e, 0x66, 0x69, 0x67, 0x20, 0x65, 0x74, 0x68, + 0x30, 0x20, 0x31, 0x30, 0x2e, 0x30, 0x2e, 0x30, 0x2e, 0x32, 0x0a, 0x69, + 0x66, 0x75, 0x70, 0x20, 0x65, 0x74, 0x68, 0x30, 0x0a, 0x74, 0x65, 0x6c, + 0x6e, 0x65, 0x74, 0x64, 0x20, 0x26, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x01, 0x10, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x00, + 0xd1, 0xff, 0xfe, 0x90, 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0xe0, + 0x2e, 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; +unsigned int romfs_img_len = 1024; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/boards/arm/sama5/sama5d2-xult/scripts/dramboot.ld b/boards/arm/sama5/sama5d2-xult/scripts/dramboot.ld index 23bd38e06e5c5..fe28b4245c710 100644 --- a/boards/arm/sama5/sama5d2-xult/scripts/dramboot.ld +++ b/boards/arm/sama5/sama5d2-xult/scripts/dramboot.ld @@ -88,6 +88,15 @@ SECTIONS _edata = ABSOLUTE(.); } > sdram + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > sdram + .bss : { _sbss = ABSOLUTE(.); @@ -98,15 +107,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > sdram - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > sdram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/sama5d2-xult/scripts/isram.ld b/boards/arm/sama5/sama5d2-xult/scripts/isram.ld index 857d75d3b791d..f1f309662efbc 100644 --- a/boards/arm/sama5/sama5d2-xult/scripts/isram.ld +++ b/boards/arm/sama5/sama5d2-xult/scripts/isram.ld @@ -84,6 +84,15 @@ SECTIONS _edata = ABSOLUTE(.); } > isram + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > isram + .bss : { _sbss = ABSOLUTE(.); @@ -94,15 +103,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > isram - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > isram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/sama5d2-xult/scripts/uboot.ld b/boards/arm/sama5/sama5d2-xult/scripts/uboot.ld index af8359b069462..2045a6caca00f 100644 --- a/boards/arm/sama5/sama5d2-xult/scripts/uboot.ld +++ b/boards/arm/sama5/sama5d2-xult/scripts/uboot.ld @@ -89,6 +89,15 @@ SECTIONS _edata = ABSOLUTE(.); } > sdram + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > sdram + .bss : { _sbss = ABSOLUTE(.); @@ -99,15 +108,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > sdram - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > sdram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/sama5d3-xplained/configs/bluetooth/defconfig b/boards/arm/sama5/sama5d3-xplained/configs/bluetooth/defconfig new file mode 100644 index 0000000000000..b4439e18dcf25 --- /dev/null +++ b/boards/arm/sama5/sama5d3-xplained/configs/bluetooth/defconfig @@ -0,0 +1,102 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEBUG_INFO is not set +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_SAMA5_UART0 is not set +# CONFIG_SAMA5_UHPHS_RHPORT1 is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ALLOW_MIT_COMPONENTS=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="sama5d3-xplained" +CONFIG_ARCH_BOARD_SAMA5D3_XPLAINED=y +CONFIG_ARCH_CHIP="sama5" +CONFIG_ARCH_CHIP_ATSAMA5D36=y +CONFIG_ARCH_CHIP_SAMA5=y +CONFIG_ARCH_CHIP_SAMA5D3=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_LOWVECTORS=y +CONFIG_BLUETOOTH_MAXSCANRESULT=100 +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=65775 +CONFIG_BOOT_RUNFROMSDRAM=y +CONFIG_BTSAK=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_NET=y +CONFIG_DEBUG_NET_ERROR=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEBUG_USB=y +CONFIG_DEBUG_USB_ERROR=y +CONFIG_DEBUG_USB_WARN=y +CONFIG_DEBUG_WIRELESS=y +CONFIG_DEBUG_WIRELESS_ERROR=y +CONFIG_DEBUG_WIRELESS_WARN=y +CONFIG_DISABLE_ENVIRON=y +CONFIG_DRIVERS_BLUETOOTH=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_EXAMPLES_HIDKBD=y +CONFIG_EXAMPLES_TOUCHSCREEN=y +CONFIG_EXAMPLES_TOUCHSCREEN_DEVPATH="/dev/mouse0" +CONFIG_EXAMPLES_TOUCHSCREEN_MOUSE=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_HIDKBD_NOGETREPORT=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NET=y +CONFIG_NET_BLUETOOTH=y +CONFIG_NET_LL_GUARDSIZE=14 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=32 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=268435456 +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_VSTART=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=200 +CONFIG_SAMA5D3XPLAINED_528MHZ=y +CONFIG_SAMA5_BOOT_SDRAM=y +CONFIG_SAMA5_DBGU=y +CONFIG_SAMA5_DBGU_CONSOLE=y +CONFIG_SAMA5_DBGU_NOCONFIG=y +CONFIG_SAMA5_HSMC=y +CONFIG_SAMA5_OHCI=y +CONFIG_SAMA5_OHCI_NEDS=20 +CONFIG_SAMA5_OHCI_NTDS=20 +CONFIG_SAMA5_OHCI_TDBUFFERS=20 +CONFIG_SAMA5_OHCI_TDBUFSIZE=1280 +CONFIG_SAMA5_SYSTEMRESET=y +CONFIG_SAMA5_UHPHS=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=31 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2014 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_USBHOST_BTHCI=y +CONFIG_USBHOST_COMPOSITE=y +CONFIG_USBHOST_HID=y +CONFIG_USBHOST_HIDKBD=y +CONFIG_USBHOST_HIDMOUSE=y +CONFIG_USBHOST_HUB=y +CONFIG_USBHOST_MSC=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_BLUETOOTH=y diff --git a/boards/arm/sama5/sama5d3-xplained/configs/ethernet-over-usb-2-high-speed/defconfig b/boards/arm/sama5/sama5d3-xplained/configs/ethernet-over-usb-2-high-speed/defconfig index 5ffccdb74faea..4382514edb3c7 100644 --- a/boards/arm/sama5/sama5d3-xplained/configs/ethernet-over-usb-2-high-speed/defconfig +++ b/boards/arm/sama5/sama5d3-xplained/configs/ethernet-over-usb-2-high-speed/defconfig @@ -67,7 +67,6 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_PROMPT_STRING="nsh> " -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=268435456 CONFIG_RAM_START=0x20000000 diff --git a/boards/arm/sama5/sama5d3-xplained/scripts/ddram.ld b/boards/arm/sama5/sama5d3-xplained/scripts/ddram.ld index e8b373acb24a9..7e19d4ec1428a 100644 --- a/boards/arm/sama5/sama5d3-xplained/scripts/ddram.ld +++ b/boards/arm/sama5/sama5d3-xplained/scripts/ddram.ld @@ -89,6 +89,15 @@ SECTIONS _edata = ABSOLUTE(.); } > sdram + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > sdram + .bss : { _sbss = ABSOLUTE(.); @@ -99,15 +108,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > sdram - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > sdram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/sama5d3-xplained/scripts/isram.ld b/boards/arm/sama5/sama5d3-xplained/scripts/isram.ld index 6a193d2f8a2ca..7308231c1dd1a 100644 --- a/boards/arm/sama5/sama5d3-xplained/scripts/isram.ld +++ b/boards/arm/sama5/sama5d3-xplained/scripts/isram.ld @@ -85,6 +85,15 @@ SECTIONS _edata = ABSOLUTE(.); } > isram + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > isram + .bss : { _sbss = ABSOLUTE(.); @@ -95,15 +104,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > isram - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > isram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/sama5d3-xplained/src/sam_usb.c b/boards/arm/sama5/sama5d3-xplained/src/sam_usb.c index f15c79a1d8362..1a4e760f582bd 100644 --- a/boards/arm/sama5/sama5d3-xplained/src/sam_usb.c +++ b/boards/arm/sama5/sama5d3-xplained/src/sam_usb.c @@ -302,6 +302,16 @@ int sam_usbhost_initialize(void) } #endif +#ifdef CONFIG_USBHOST_BTHCI + /* Register USB Bluetooth support */ + + ret = usbhost_bthci_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the bt controller: %d\n", ret); + } +#endif + #ifdef CONFIG_USBHOST_MSC /* Register theUSB host Mass Storage Class */ @@ -332,6 +342,16 @@ int sam_usbhost_initialize(void) } #endif +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + /* Then get an instance of the USB host interface. */ #ifdef CONFIG_SAMA5_OHCI diff --git a/boards/arm/sama5/sama5d3x-ek/scripts/ddram.ld b/boards/arm/sama5/sama5d3x-ek/scripts/ddram.ld index 678807c76f612..7e480faf7d086 100644 --- a/boards/arm/sama5/sama5d3x-ek/scripts/ddram.ld +++ b/boards/arm/sama5/sama5d3x-ek/scripts/ddram.ld @@ -89,6 +89,15 @@ SECTIONS _edata = ABSOLUTE(.); } > sdram + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > sdram + .bss : { _sbss = ABSOLUTE(.); @@ -99,15 +108,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > sdram - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > sdram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/sama5d3x-ek/scripts/isram.ld b/boards/arm/sama5/sama5d3x-ek/scripts/isram.ld index 7501d19059751..41c915c3fc270 100644 --- a/boards/arm/sama5/sama5d3x-ek/scripts/isram.ld +++ b/boards/arm/sama5/sama5d3x-ek/scripts/isram.ld @@ -85,6 +85,15 @@ SECTIONS _edata = ABSOLUTE(.); } > isram + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > isram + .bss : { _sbss = ABSOLUTE(.); @@ -95,15 +104,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > isram - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > isram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/sama5d3x-ek/scripts/nor-ddram.ld b/boards/arm/sama5/sama5d3x-ek/scripts/nor-ddram.ld index f317780db2318..44ca17c784217 100644 --- a/boards/arm/sama5/sama5d3x-ek/scripts/nor-ddram.ld +++ b/boards/arm/sama5/sama5d3x-ek/scripts/nor-ddram.ld @@ -96,6 +96,15 @@ SECTIONS _eronly = LOADADDR(.data); + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > sdram + .bss : { _sbss = ABSOLUTE(.); @@ -106,15 +115,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > sdram - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > sdram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/sama5d3x-ek/scripts/nor-isram.ld b/boards/arm/sama5/sama5d3x-ek/scripts/nor-isram.ld index 8e9a66396e0d6..54fc1d75698ee 100644 --- a/boards/arm/sama5/sama5d3x-ek/scripts/nor-isram.ld +++ b/boards/arm/sama5/sama5d3x-ek/scripts/nor-isram.ld @@ -92,16 +92,6 @@ SECTIONS _eronly = LOADADDR(.data); - .bss : - { - _sbss = ABSOLUTE(.); - *(.bss .bss.*) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(4); - _ebss = ABSOLUTE(.); - } > isram - .ramfunc ALIGN(4): { _sramfuncs = ABSOLUTE(.); @@ -109,8 +99,6 @@ SECTIONS _eramfuncs = ABSOLUTE(.); } > isram AT > norflash - _framfuncs = LOADADDR(.ramfunc); - /* Uninitialized data */ .noinit : @@ -120,6 +108,18 @@ SECTIONS _enoinit = ABSOLUTE(.); } > isram + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > isram + + _framfuncs = LOADADDR(.ramfunc); + /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/sama5d3x-ek/scripts/pg-sram.ld b/boards/arm/sama5/sama5d3x-ek/scripts/pg-sram.ld index cef2b97d297ec..bf1d16c7bb543 100644 --- a/boards/arm/sama5/sama5d3x-ek/scripts/pg-sram.ld +++ b/boards/arm/sama5/sama5d3x-ek/scripts/pg-sram.ld @@ -124,6 +124,15 @@ SECTIONS _edata = ABSOLUTE(.); } > data AT > locked + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > data + .bss : { _sbss = ABSOLUTE(.); @@ -134,15 +143,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > data - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > data - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/sama5d4-ek/configs/ipv6/defconfig b/boards/arm/sama5/sama5d4-ek/configs/ipv6/defconfig index 8b37277f2133c..3709add1b20d8 100644 --- a/boards/arm/sama5/sama5d4-ek/configs/ipv6/defconfig +++ b/boards/arm/sama5/sama5d4-ek/configs/ipv6/defconfig @@ -33,6 +33,7 @@ CONFIG_BOOT_RUNFROMSDRAM=y CONFIG_BUILTIN=y CONFIG_DEV_ZERO=y CONFIG_DRIVERS_AUDIO=y +CONFIG_ETC_ROMFS=y CONFIG_ETH0_PHY_KSZ8081=y CONFIG_EXAMPLES_NX=y CONFIG_EXAMPLES_NX_BPP=16 @@ -75,11 +76,9 @@ CONFIG_NET_TCPBACKLOG=y CONFIG_NET_TCP_WRITE_BUFFERS=y CONFIG_NET_UDP=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_NX=y CONFIG_NXFONT_SERIF22X28B=y CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/mnt/sdcard" diff --git a/boards/arm/sama5/sama5d4-ek/configs/nsh/defconfig b/boards/arm/sama5/sama5d4-ek/configs/nsh/defconfig index d55c23b442409..047b252d48139 100644 --- a/boards/arm/sama5/sama5d4-ek/configs/nsh/defconfig +++ b/boards/arm/sama5/sama5d4-ek/configs/nsh/defconfig @@ -32,6 +32,7 @@ CONFIG_BOOT_RUNFROMSDRAM=y CONFIG_BUILTIN=y CONFIG_DEV_ZERO=y CONFIG_DRIVERS_AUDIO=y +CONFIG_ETC_ROMFS=y CONFIG_ETH0_PHY_KSZ8081=y CONFIG_EXAMPLES_NX=y CONFIG_EXAMPLES_NX_BPP=16 @@ -77,11 +78,9 @@ CONFIG_NET_TCPBACKLOG=y CONFIG_NET_TCP_WRITE_BUFFERS=y CONFIG_NET_UDP=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_NX=y CONFIG_NXFONT_SERIF22X28B=y CONFIG_NXPLAYER_DEFAULT_MEDIADIR="/mnt/sdcard" diff --git a/boards/arm/sama5/sama5d4-ek/configs/nxwm/defconfig b/boards/arm/sama5/sama5d4-ek/configs/nxwm/defconfig index 8967bd12981be..645ff44b8ef58 100644 --- a/boards/arm/sama5/sama5d4-ek/configs/nxwm/defconfig +++ b/boards/arm/sama5/sama5d4-ek/configs/nxwm/defconfig @@ -36,6 +36,7 @@ CONFIG_BOOT_RUNFROMSDRAM=y CONFIG_BUILTIN=y CONFIG_DEV_ZERO=y CONFIG_DRIVERS_AUDIO=y +CONFIG_ETC_ROMFS=y CONFIG_ETH0_PHY_KSZ8081=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y @@ -80,12 +81,10 @@ CONFIG_NET_TCPBACKLOG=y CONFIG_NET_TCP_WRITE_BUFFERS=y CONFIG_NET_UDP=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LIBRARY=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_NX=y CONFIG_NXFONT_SANS28X37=y CONFIG_NXFONT_SANS28X37B=y diff --git a/boards/arm/sama5/sama5d4-ek/include/nsh_romfsimg.h b/boards/arm/sama5/sama5d4-ek/include/nsh_romfsimg.h deleted file mode 100644 index 38486878370e2..0000000000000 --- a/boards/arm/sama5/sama5d4-ek/include/nsh_romfsimg.h +++ /dev/null @@ -1,109 +0,0 @@ -/*************************************************************************** - * boards/arm/sama5/sama5d4-ek/include/nsh_romfsimg.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ***************************************************************************/ - -unsigned char romfs_img[] = { - 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x02, 0x00, - 0xe7, 0x04, 0x63, 0xbd, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56, - 0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, - 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, - 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, - 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x68, 0x2d, 0x96, 0x03, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; -unsigned int romfs_img_len = 1024; diff --git a/boards/arm/sama5/sama5d4-ek/scripts/dramboot.ld b/boards/arm/sama5/sama5d4-ek/scripts/dramboot.ld index 37163a9d8016f..91461f208f868 100644 --- a/boards/arm/sama5/sama5d4-ek/scripts/dramboot.ld +++ b/boards/arm/sama5/sama5d4-ek/scripts/dramboot.ld @@ -88,6 +88,15 @@ SECTIONS _edata = ABSOLUTE(.); } > sdram + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > sdram + .bss : { _sbss = ABSOLUTE(.); @@ -98,15 +107,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > sdram - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > sdram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/sama5d4-ek/scripts/isram.ld b/boards/arm/sama5/sama5d4-ek/scripts/isram.ld index 0b12243de56a6..21ec43c65d004 100644 --- a/boards/arm/sama5/sama5d4-ek/scripts/isram.ld +++ b/boards/arm/sama5/sama5d4-ek/scripts/isram.ld @@ -85,6 +85,15 @@ SECTIONS _edata = ABSOLUTE(.); } > isram + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > isram + .bss : { _sbss = ABSOLUTE(.); @@ -95,15 +104,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > isram - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > isram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/sama5d4-ek/scripts/uboot.ld b/boards/arm/sama5/sama5d4-ek/scripts/uboot.ld index b4823bf0e6d2c..615058812716d 100644 --- a/boards/arm/sama5/sama5d4-ek/scripts/uboot.ld +++ b/boards/arm/sama5/sama5d4-ek/scripts/uboot.ld @@ -89,6 +89,15 @@ SECTIONS _edata = ABSOLUTE(.); } > sdram + /* Uninitialized data */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > sdram + .bss : { _sbss = ABSOLUTE(.); @@ -99,15 +108,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > sdram - /* Uninitialized data */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > sdram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/sama5/sama5d4-ek/src/Makefile b/boards/arm/sama5/sama5d4-ek/src/Makefile index ee4f58cb8500d..f5e58d1efb884 100644 --- a/boards/arm/sama5/sama5d4-ek/src/Makefile +++ b/boards/arm/sama5/sama5d4-ek/src/Makefile @@ -126,4 +126,8 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += sam_buttons.c endif +ifeq ($(CONFIG_ETC_ROMFS),y) +CSRCS += etc_romfs.c +endif + include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/sama5/sama5d4-ek/src/etc_romfs.c b/boards/arm/sama5/sama5d4-ek/src/etc_romfs.c new file mode 100644 index 0000000000000..15baf9257785a --- /dev/null +++ b/boards/arm/sama5/sama5d4-ek/src/etc_romfs.c @@ -0,0 +1,118 @@ +/*************************************************************************** + * boards/arm/sama5/sama5d4-ek/src/etc_romfs.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ***************************************************************************/ + +/*************************************************************************** + * Public Data + ***************************************************************************/ + +unsigned char romfs_img[] = +{ + 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x02, 0x00, + 0xe7, 0x04, 0x63, 0xbd, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56, + 0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, + 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, + 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; +unsigned int romfs_img_len = 1024; + +/*************************************************************************** + * Public Functions + ***************************************************************************/ diff --git a/boards/arm/samv7/common/src/Make.defs b/boards/arm/samv7/common/src/Make.defs index fb0451229b457..34ca649098dc1 100644 --- a/boards/arm/samv7/common/src/Make.defs +++ b/boards/arm/samv7/common/src/Make.defs @@ -20,9 +20,7 @@ ifeq ($(CONFIG_ARCH_BOARD_COMMON),y) -ifeq ($(CONFIG_BOARDCTL_RESET),y) CSRCS += sam_reset.c -endif ifeq ($(CONFIG_BOARDCTL_BOOT_IMAGE),y) CSRCS += sam_boot_image.c diff --git a/boards/arm/samv7/common/src/sam_reset.c b/boards/arm/samv7/common/src/sam_reset.c index 67ffb709559f8..796e438f54723 100644 --- a/boards/arm/samv7/common/src/sam_reset.c +++ b/boards/arm/samv7/common/src/sam_reset.c @@ -27,12 +27,83 @@ #include #include -#ifdef CONFIG_BOARDCTL_RESET +#include "sam_systemreset.h" /**************************************************************************** * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: board_reset_cause + * + * Description: + * Get the cause of last board reset. This should call architecture + * specific logic to handle the register read. + * + * Input Parameters: + * cause - Pointer to boardioc_reset_cause_s structure to which the + * reason (and potentially subreason) is saved. + * + * Returned Value: + * This functions should always return succesfully with 0. We save + * BOARDIOC_RESETCAUSE_UNKOWN in cause structure if we are + * not able to get last reset cause from HW (which is unlikely). + * + ****************************************************************************/ + +#ifdef CONFIG_BOARDCTL_RESET_CAUSE +int board_reset_cause(FAR struct boardioc_reset_cause_s *cause) +{ + int rst_cause; + + /* Get the reset cause from hardware */ + + rst_cause = sam_get_reset_cause(); + + switch (rst_cause) + { + case SAMV7_RESET_PWRUP: + + /* Power up */ + + cause->cause = BOARDIOC_RESETCAUSE_SYS_CHIPPOR; + break; + case SAMV7_RESET_BACKUP: + + /* Wake up from backup (low power) mode */ + + cause->cause = BOARDIOC_RESETCAUSE_LOWPOWER; + break; + case SAMV7_RESET_WDOG: + + /* Watchdog error */ + + cause->cause = BOARDIOC_RESETCAUSE_CPU_RWDT; + break; + case SAMV7_RESET_SWRST: + + /* SW reset */ + + cause->cause = BOARDIOC_RESETCAUSE_CPU_SOFT; + break; + case SAMV7_RESET_NRST: + + /* Reset from user by pressing reset button */ + + cause->cause = BOARDIOC_RESETCAUSE_PIN; + break; + default: + + /* Unknown cause returned from HW */ + + cause->cause = BOARDIOC_RESETCAUSE_UNKOWN; + break; + } + + return 0; +} +#endif /* CONFIG_BOARDCTL_RESET_CAUSE */ + /**************************************************************************** * Name: board_reset * @@ -53,10 +124,10 @@ * ****************************************************************************/ +#ifdef CONFIG_BOARDCTL_RESET int board_reset(int status) { up_systemreset(); return 0; } - #endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/arm/samv7/same70-xplained/configs/adc/defconfig b/boards/arm/samv7/same70-xplained/configs/adc/defconfig index 153b38d4f4c42..b0e2a12a9ab24 100644 --- a/boards/arm/samv7/same70-xplained/configs/adc/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/adc/defconfig @@ -69,6 +69,7 @@ CONFIG_SAMV7_GPIOA_IRQ=y CONFIG_SAMV7_GPIOC_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y CONFIG_SAMV7_HSMCI0=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_SDRAMC=y CONFIG_SAMV7_SDRAMSIZE=2097152 CONFIG_SAMV7_TC0=y diff --git a/boards/arm/samv7/same70-xplained/configs/can/defconfig b/boards/arm/samv7/same70-xplained/configs/can/defconfig index b02e40e562c2b..866bf0c4096a1 100644 --- a/boards/arm/samv7/same70-xplained/configs/can/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/can/defconfig @@ -62,6 +62,7 @@ CONFIG_SAMV7_GPIOA_IRQ=y CONFIG_SAMV7_GPIOC_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y CONFIG_SAMV7_HSMCI0=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_MCAN0=y CONFIG_SAMV7_SDRAMC=y CONFIG_SAMV7_SDRAMSIZE=2097152 diff --git a/boards/arm/samv7/same70-xplained/configs/mcuboot-loader/defconfig b/boards/arm/samv7/same70-xplained/configs/mcuboot-loader/defconfig index 187b59a5ae715..4628f97f3f286 100644 --- a/boards/arm/samv7/same70-xplained/configs/mcuboot-loader/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/mcuboot-loader/defconfig @@ -63,6 +63,7 @@ CONFIG_SAMV7_GPIOA_IRQ=y CONFIG_SAMV7_GPIOC_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y CONFIG_SAMV7_HSMCI0=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_SDRAMC=y CONFIG_SAMV7_SDRAMSIZE=2097152 CONFIG_SAMV7_TWIHS0=y diff --git a/boards/arm/samv7/same70-xplained/configs/mcuboot-slot-confirm/defconfig b/boards/arm/samv7/same70-xplained/configs/mcuboot-slot-confirm/defconfig index 250dd4fc60c24..5042a8ef832b9 100644 --- a/boards/arm/samv7/same70-xplained/configs/mcuboot-slot-confirm/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/mcuboot-slot-confirm/defconfig @@ -61,6 +61,7 @@ CONFIG_SAMV7_GPIOA_IRQ=y CONFIG_SAMV7_GPIOC_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y CONFIG_SAMV7_HSMCI0=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_SDRAMC=y CONFIG_SAMV7_SDRAMSIZE=2097152 CONFIG_SAMV7_TWIHS0=y diff --git a/boards/arm/samv7/same70-xplained/configs/netnsh/defconfig b/boards/arm/samv7/same70-xplained/configs/netnsh/defconfig index d04c2718b5e0d..5717c6d057525 100644 --- a/boards/arm/samv7/same70-xplained/configs/netnsh/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/netnsh/defconfig @@ -92,6 +92,7 @@ CONFIG_SAMV7_GPIOA_IRQ=y CONFIG_SAMV7_GPIOC_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y CONFIG_SAMV7_HSMCI0=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_TWIHS0=y CONFIG_SAMV7_USART1=y CONFIG_SAMV7_XDMAC=y diff --git a/boards/arm/samv7/same70-xplained/configs/nsh/defconfig b/boards/arm/samv7/same70-xplained/configs/nsh/defconfig index 5b580bdbed956..099d0838dcc16 100644 --- a/boards/arm/samv7/same70-xplained/configs/nsh/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/nsh/defconfig @@ -62,6 +62,7 @@ CONFIG_SAMV7_GPIOA_IRQ=y CONFIG_SAMV7_GPIOC_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y CONFIG_SAMV7_HSMCI0=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_SDRAMC=y CONFIG_SAMV7_SDRAMSIZE=2097152 CONFIG_SAMV7_TWIHS0=y diff --git a/boards/arm/samv7/same70-xplained/configs/pwm/defconfig b/boards/arm/samv7/same70-xplained/configs/pwm/defconfig index eb9ce3f57cb42..fca9ee6b7b617 100644 --- a/boards/arm/samv7/same70-xplained/configs/pwm/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/pwm/defconfig @@ -67,6 +67,7 @@ CONFIG_SAMV7_GPIOA_IRQ=y CONFIG_SAMV7_GPIOC_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y CONFIG_SAMV7_HSMCI0=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_PWM0=y CONFIG_SAMV7_PWM0_CH0=y CONFIG_SAMV7_PWM0_CH1=y diff --git a/boards/arm/samv7/same70-xplained/configs/pysim/defconfig b/boards/arm/samv7/same70-xplained/configs/pysim/defconfig index 9ab5ce07cf5f5..40cfc06c99ab2 100644 --- a/boards/arm/samv7/same70-xplained/configs/pysim/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/pysim/defconfig @@ -98,7 +98,6 @@ CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_LINELEN=64 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=2048 CONFIG_PREALLOC_TIMERS=4 CONFIG_PSEUDOTERM=y @@ -130,6 +129,7 @@ CONFIG_SAMV7_GPIOA_IRQ=y CONFIG_SAMV7_GPIOC_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y CONFIG_SAMV7_HSMCI0=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_PWM0=y CONFIG_SAMV7_PWM0_CH0=y CONFIG_SAMV7_PWM0_CH1=y diff --git a/boards/arm/samv7/same70-xplained/configs/twm4nx/defconfig b/boards/arm/samv7/same70-xplained/configs/twm4nx/defconfig index 5a3dfb7ebc11b..27af153d1e6f5 100644 --- a/boards/arm/samv7/same70-xplained/configs/twm4nx/defconfig +++ b/boards/arm/samv7/same70-xplained/configs/twm4nx/defconfig @@ -103,6 +103,7 @@ CONFIG_SAMV7_GPIOA_IRQ=y CONFIG_SAMV7_GPIOC_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y CONFIG_SAMV7_HSMCI0=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_SDRAMC=y CONFIG_SAMV7_SDRAMSIZE=2097152 CONFIG_SAMV7_TWIHS0=y diff --git a/boards/arm/samv7/samv71-xult/configs/knsh/defconfig b/boards/arm/samv7/samv71-xult/configs/knsh/defconfig index 92969a92091cd..75541c9a9998a 100644 --- a/boards/arm/samv7/samv71-xult/configs/knsh/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/knsh/defconfig @@ -67,6 +67,7 @@ CONFIG_SAMV7_GPIOB_IRQ=y CONFIG_SAMV7_GPIOD_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y CONFIG_SAMV7_HSMCI0=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_SDRAMC=y CONFIG_SAMV7_SDRAMSIZE=2097152 CONFIG_SAMV7_TWIHS0=y diff --git a/boards/arm/samv7/samv71-xult/configs/mcuboot-loader/defconfig b/boards/arm/samv7/samv71-xult/configs/mcuboot-loader/defconfig index 261adc22329aa..69c522b89bc32 100644 --- a/boards/arm/samv7/samv71-xult/configs/mcuboot-loader/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/mcuboot-loader/defconfig @@ -48,6 +48,7 @@ CONFIG_SAMV7_GPIOA_IRQ=y CONFIG_SAMV7_GPIOB_IRQ=y CONFIG_SAMV7_GPIOD_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_SYSTEMRESET=y CONFIG_SAMV7_USART1=y CONFIG_SAMV7_XDMAC=y diff --git a/boards/arm/samv7/samv71-xult/configs/mcuboot-slot-confirm/defconfig b/boards/arm/samv7/samv71-xult/configs/mcuboot-slot-confirm/defconfig index 01dfbef3222b7..fff10ddb56985 100644 --- a/boards/arm/samv7/samv71-xult/configs/mcuboot-slot-confirm/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/mcuboot-slot-confirm/defconfig @@ -48,6 +48,7 @@ CONFIG_SAMV7_GPIOA_IRQ=y CONFIG_SAMV7_GPIOB_IRQ=y CONFIG_SAMV7_GPIOD_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_SYSTEMRESET=y CONFIG_SAMV7_USART1=y CONFIG_SAMV7_XDMAC=y diff --git a/boards/arm/samv7/samv71-xult/configs/mcuboot-swap-test/defconfig b/boards/arm/samv7/samv71-xult/configs/mcuboot-swap-test/defconfig index b3389d0e5da33..96b6f4aeb7bc5 100644 --- a/boards/arm/samv7/samv71-xult/configs/mcuboot-swap-test/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/mcuboot-swap-test/defconfig @@ -48,6 +48,7 @@ CONFIG_SAMV7_GPIOA_IRQ=y CONFIG_SAMV7_GPIOB_IRQ=y CONFIG_SAMV7_GPIOD_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_SYSTEMRESET=y CONFIG_SAMV7_USART1=y CONFIG_SAMV7_XDMAC=y diff --git a/boards/arm/samv7/samv71-xult/configs/mcuboot-update-agent/defconfig b/boards/arm/samv7/samv71-xult/configs/mcuboot-update-agent/defconfig index ad3d801a6b3bf..6d8b0b7ce2941 100644 --- a/boards/arm/samv7/samv71-xult/configs/mcuboot-update-agent/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/mcuboot-update-agent/defconfig @@ -102,6 +102,7 @@ CONFIG_SAMV7_GPIOB_IRQ=y CONFIG_SAMV7_GPIOD_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y CONFIG_SAMV7_HSMCI0=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_SYSTEMRESET=y CONFIG_SAMV7_TWIHS0=y CONFIG_SAMV7_USART1=y diff --git a/boards/arm/samv7/samv71-xult/configs/module/defconfig b/boards/arm/samv7/samv71-xult/configs/module/defconfig index ce8d367614fb5..a645fc3ca775c 100644 --- a/boards/arm/samv7/samv71-xult/configs/module/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/module/defconfig @@ -54,6 +54,7 @@ CONFIG_SAMV7_GPIOA_IRQ=y CONFIG_SAMV7_GPIOB_IRQ=y CONFIG_SAMV7_GPIOD_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_USART1=y CONFIG_SAMV7_XDMAC=y CONFIG_SCHED_HPWORK=y diff --git a/boards/arm/samv7/samv71-xult/configs/mrf24j40-starhub/defconfig b/boards/arm/samv7/samv71-xult/configs/mrf24j40-starhub/defconfig index ff629eaa75b0b..73ad408215949 100644 --- a/boards/arm/samv7/samv71-xult/configs/mrf24j40-starhub/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/mrf24j40-starhub/defconfig @@ -116,6 +116,7 @@ CONFIG_SAMV7_GPIOB_IRQ=y CONFIG_SAMV7_GPIOD_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y CONFIG_SAMV7_HSMCI0=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_SPI0=y CONFIG_SAMV7_USART1=y CONFIG_SAMV7_XDMAC=y diff --git a/boards/arm/samv7/samv71-xult/configs/mxtxplnd/defconfig b/boards/arm/samv7/samv71-xult/configs/mxtxplnd/defconfig index 492d5ce145ef8..3cf64f28326d6 100644 --- a/boards/arm/samv7/samv71-xult/configs/mxtxplnd/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/mxtxplnd/defconfig @@ -75,6 +75,7 @@ CONFIG_SAMV7_GPIOB_IRQ=y CONFIG_SAMV7_GPIOD_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y CONFIG_SAMV7_HSMCI0=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_SMC=y CONFIG_SAMV7_TWIHS0=y CONFIG_SAMV7_USART1=y diff --git a/boards/arm/samv7/samv71-xult/configs/netnsh/defconfig b/boards/arm/samv7/samv71-xult/configs/netnsh/defconfig index b3a22cbef520e..3c268ef02b936 100644 --- a/boards/arm/samv7/samv71-xult/configs/netnsh/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/netnsh/defconfig @@ -92,6 +92,7 @@ CONFIG_SAMV7_GPIOB_IRQ=y CONFIG_SAMV7_GPIOD_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y CONFIG_SAMV7_HSMCI0=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_TWIHS0=y CONFIG_SAMV7_USART1=y CONFIG_SAMV7_XDMAC=y diff --git a/boards/arm/samv7/samv71-xult/configs/nsh/defconfig b/boards/arm/samv7/samv71-xult/configs/nsh/defconfig index 13e2cfe00709e..9b0ca0d34c8dd 100644 --- a/boards/arm/samv7/samv71-xult/configs/nsh/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/nsh/defconfig @@ -64,6 +64,7 @@ CONFIG_SAMV7_GPIOB_IRQ=y CONFIG_SAMV7_GPIOD_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y CONFIG_SAMV7_HSMCI0=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_SDRAMC=y CONFIG_SAMV7_SDRAMSIZE=2097152 CONFIG_SAMV7_TWIHS0=y diff --git a/boards/arm/samv7/samv71-xult/configs/nxwm/defconfig b/boards/arm/samv7/samv71-xult/configs/nxwm/defconfig index 48ccb4df2f50f..729b503668c0e 100644 --- a/boards/arm/samv7/samv71-xult/configs/nxwm/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/nxwm/defconfig @@ -110,6 +110,7 @@ CONFIG_SAMV7_GPIOB_IRQ=y CONFIG_SAMV7_GPIOD_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y CONFIG_SAMV7_HSMCI0=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_SMC=y CONFIG_SAMV7_TWIHS0=y CONFIG_SAMV7_USART1=y diff --git a/boards/arm/samv7/samv71-xult/configs/vnc/defconfig b/boards/arm/samv7/samv71-xult/configs/vnc/defconfig index 8aa2fa8388f7a..1c3d3cca44b03 100644 --- a/boards/arm/samv7/samv71-xult/configs/vnc/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/vnc/defconfig @@ -102,6 +102,7 @@ CONFIG_SAMV7_GPIOB_IRQ=y CONFIG_SAMV7_GPIOD_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y CONFIG_SAMV7_HSMCI0=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_TWIHS0=y CONFIG_SAMV7_USART1=y CONFIG_SAMV7_XDMAC=y diff --git a/boards/arm/samv7/samv71-xult/configs/vnxwm/defconfig b/boards/arm/samv7/samv71-xult/configs/vnxwm/defconfig index e53e18f1e3384..fbc85f3a5ffc6 100644 --- a/boards/arm/samv7/samv71-xult/configs/vnxwm/defconfig +++ b/boards/arm/samv7/samv71-xult/configs/vnxwm/defconfig @@ -132,6 +132,7 @@ CONFIG_SAMV7_GPIOB_IRQ=y CONFIG_SAMV7_GPIOD_IRQ=y CONFIG_SAMV7_GPIO_IRQ=y CONFIG_SAMV7_HSMCI0=y +CONFIG_SAMV7_JTAG_FULL_SW_ENABLE=y CONFIG_SAMV7_TWIHS0=y CONFIG_SAMV7_USART1=y CONFIG_SAMV7_XDMAC=y diff --git a/boards/arm/samv7/samv71-xult/src/sam_bringup.c b/boards/arm/samv7/samv71-xult/src/sam_bringup.c index 9339e54980ff9..dd9f87c388fb3 100644 --- a/boards/arm/samv7/samv71-xult/src/sam_bringup.c +++ b/boards/arm/samv7/samv71-xult/src/sam_bringup.c @@ -61,6 +61,10 @@ # include #endif +#ifdef CONFIG_VNCSERVER +# include +#endif + #if defined(HAVE_RTC_DSXXXX) || defined(HAVE_RTC_PCF85263) # include # include @@ -562,11 +566,19 @@ int sam_bringup(void) #ifdef CONFIG_VIDEO_FB /* Initialize and register the LCD framebuffer driver */ +# ifdef CONFIG_VNCSERVER + ret = vnc_fb_register(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: vnc_fb_register() failed: %d\n", ret); + } +# else ret = fb_register(0, 0); if (ret < 0) { syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); } +# endif #endif /* If we got here then perhaps not all initialization was successful, but diff --git a/boards/arm/stm32/common/include/stm32_ds1307.h b/boards/arm/stm32/common/include/stm32_ds1307.h new file mode 100644 index 0000000000000..370e17ef401c9 --- /dev/null +++ b/boards/arm/stm32/common/include/stm32_ds1307.h @@ -0,0 +1,83 @@ +/**************************************************************************** + * boards/arm/stm32/common/include/stm32_ds1307.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DS1307_H +#define __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DS1307_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ds1307_initialize + * + * Description: + * Initialize and configure the DS1307 RTC + * + * Input Parameters: + * busno - The I2C bus number where DS1307 is connected. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_ds1307_initialize(int busno); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __BOARDS_ARM_STM32_COMMON_INCLUDE_STM32_DS1307_H */ diff --git a/boards/arm/stm32/common/src/CMakeLists.txt b/boards/arm/stm32/common/src/CMakeLists.txt index 7ee6cf5ed98a0..8557119f0ea59 100644 --- a/boards/arm/stm32/common/src/CMakeLists.txt +++ b/boards/arm/stm32/common/src/CMakeLists.txt @@ -56,6 +56,10 @@ if(CONFIG_LCD_SSD1306) list(APPEND SRCS stm32_ssd1306.c) endif() +if(CONFIG_RTC_DS1307) + list(APPEND SRCS stm32_ds1307.c) +endif() + if(CONFIG_SENSORS_LM75) list(APPEND SRCS stm32_lm75.c) endif() diff --git a/boards/arm/stm32/common/src/Make.defs b/boards/arm/stm32/common/src/Make.defs index 4cdb9f7ac281d..d99d07f06204b 100644 --- a/boards/arm/stm32/common/src/Make.defs +++ b/boards/arm/stm32/common/src/Make.defs @@ -60,6 +60,10 @@ ifeq ($(CONFIG_LCD_SSD1306),y) CSRCS += stm32_ssd1306.c endif +ifeq ($(CONFIG_RTC_DS1307),y) + CSRCS += stm32_ds1307.c +endif + ifeq ($(CONFIG_SENSORS_LM75),y) CSRCS += stm32_lm75.c endif diff --git a/boards/arm/stm32/common/src/stm32_bh1750.c b/boards/arm/stm32/common/src/stm32_bh1750.c index 09b77aa8e8bdc..612ded26b596b 100644 --- a/boards/arm/stm32/common/src/stm32_bh1750.c +++ b/boards/arm/stm32/common/src/stm32_bh1750.c @@ -28,7 +28,7 @@ #include #include -#include +#include #include #include @@ -61,6 +61,7 @@ int board_bh1750_initialize(int devno, int busno) { struct i2c_master_s *i2c; + char devpath[12]; int ret; sninfo("Initializing BH1750FVI!\n"); @@ -68,7 +69,6 @@ int board_bh1750_initialize(int devno, int busno) /* Initialize I2C */ i2c = stm32_i2cbus_initialize(busno); - if (!i2c) { return -ENODEV; @@ -76,6 +76,7 @@ int board_bh1750_initialize(int devno, int busno) /* Then register the ambient light sensor */ + snprintf(devpath, 12, "/dev/light%d", devno); ret = bh1750fvi_register(devpath, i2c, BH1750FVI_I2C_ADDR); if (ret < 0) { diff --git a/boards/arm/stm32/common/src/stm32_ds1307.c b/boards/arm/stm32/common/src/stm32_ds1307.c new file mode 100644 index 0000000000000..328730da77739 --- /dev/null +++ b/boards/arm/stm32/common/src/stm32_ds1307.c @@ -0,0 +1,97 @@ +/**************************************************************************** + * boards/arm/stm32/common/src/stm32_ds1307.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32.h" +#include "stm32_i2c.h" + +#if defined(CONFIG_I2C) && defined(CONFIG_RTC_DS1307) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ds1307_initialize + * + * Description: + * Initialize and configure the DS1307 RTC + * + * Input Parameters: + * busno - The I2C bus number where DS1307 is connected. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_ds1307_initialize(int busno) +{ + struct i2c_master_s *i2c; + int ret; + + rtcinfo("Initialize I2C%d\n", DS1307_I2C_BUS); + + /* Initialize I2C */ + + i2c = stm32_i2cbus_initialize(busno); + if (!i2c) + { + rtcerr("ERROR: Failed to initialize I2C%d\n", busno); + return -ENODEV; + } + + /* Now bind the I2C interface to the DS1307 RTC driver */ + + rtcinfo("Bind the DS1307 RTC driver to I2C%d\n", busno); + ret = dsxxxx_rtc_initialize(i2c); + if (ret < 0) + { + rtcerr("ERROR: Failed to bind I2C%d to the DS1307 RTC driver\n", + DS1307_I2C_BUS); + return -ENODEV; + } + + /* Synchronize the system time to the RTC time */ + + clock_synchronize(NULL); + + /* Now we are initialized */ + + return OK; +} + +#endif /* CONFIG_I2C && CONFIG_RTC_DS1307 */ diff --git a/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig b/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig index fb657574ade3c..13f96502f22d9 100644 --- a/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig +++ b/boards/arm/stm32/mikroe-stm32f4/configs/fulldemo/defconfig @@ -37,6 +37,8 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y CONFIG_DRIVERS_AUDIO=y +CONFIG_ETC_FATDEVNO=0 +CONFIG_ETC_ROMFS=y CONFIG_EXAMPLES_NX=y CONFIG_EXAMPLES_NX_BPP=16 CONFIG_EXAMPLES_TOUCHSCREEN=y @@ -67,13 +69,10 @@ CONFIG_MTD_CONFIG=y CONFIG_MTD_PARTITION=y CONFIG_MTD_SMART_SECTOR_SIZE=512 CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=0 CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_NSH_STRERROR=y CONFIG_NX=y CONFIG_NXFONT_SANS17X23B=y diff --git a/boards/arm/stm32/mikroe-stm32f4/include/nsh_romfsimg.h b/boards/arm/stm32/mikroe-stm32f4/include/nsh_romfsimg.h deleted file mode 100644 index 491bee0dc53db..0000000000000 --- a/boards/arm/stm32/mikroe-stm32f4/include/nsh_romfsimg.h +++ /dev/null @@ -1,110 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/mikroe-stm32f4/include/nsh_romfsimg.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -unsigned char romfs_img[] = -{ - 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x01, 0x80, - 0x42, 0x56, 0x48, 0x93, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56, - 0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, - 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, - 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, - 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x68, 0x2d, 0x96, 0x03, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, - 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See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +unsigned char romfs_img[] = +{ + 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x01, 0x80, + 0x42, 0x56, 0x48, 0x93, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56, + 0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, + 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, + 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; +unsigned int romfs_img_len = 1024; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig b/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig index 0358ce26cac0b..ee15d21198093 100644 --- a/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig +++ b/boards/arm/stm32/nucleo-f302r8/configs/qenco/defconfig @@ -29,7 +29,6 @@ # CONFIG_NSH_DISABLE_EXPORT is not set # CONFIG_NSH_DISABLE_FREE is not set # CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HELP is not set # CONFIG_NSH_DISABLE_HEXDUMP is not set # CONFIG_NSH_DISABLE_ITEF is not set # CONFIG_NSH_DISABLE_KILL is not set diff --git a/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c b/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c index 92474e389d87b..f9da1445cd337 100644 --- a/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c +++ b/boards/arm/stm32/nucleo-f429zi/src/stm32_bbsram.c @@ -74,7 +74,7 @@ #define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ BBSRAM_SIZE_FN2)) -#define BBSRAM_REAMINING (STM32F4_BBSRAM_SIZE-BBSRAM_USED) +#define BBSRAM_REAMINING (STM32_BBSRAM_SIZE-BBSRAM_USED) #if CONFIG_ARCH_INTERRUPTSTACK <= 3 # define BBSRAM_NUMBER_STACKS 1 #else @@ -136,7 +136,7 @@ typedef struct #if CONFIG_ARCH_INTERRUPTSTACK > 3 _stack_t interrupt; #endif -} stack_t; +} stacks_t; /* Not Used for reference only */ @@ -237,7 +237,7 @@ typedef struct int lineno; /* __LINE__ to up_assert */ pid_t pid; /* Process ID */ uint32_t regs[XCPTCONTEXT_REGS]; /* Interrupt register save area */ - stack_t stacks; /* Stack info */ + stacks_t stacks; /* Stack info */ #if CONFIG_TASK_NAME_SIZE > 0 char name[CONFIG_TASK_NAME_SIZE + 1]; /* Task name (with NULL * terminator) */ @@ -265,7 +265,7 @@ typedef struct * Private Data ****************************************************************************/ -static uint8_t g_sdata[STM32F4_BBSRAM_SIZE]; +static uint8_t g_sdata[STM32_BBSRAM_SIZE]; /**************************************************************************** * Private Functions @@ -288,7 +288,7 @@ static int hardfault_get_desc(struct bbsramd_s *desc) } else { - ret = file_ioctl(&filestruct, STM32F4_BBSRAM_GETDESC_IOCTL, + ret = file_ioctl(&filestruct, STM32_BBSRAM_GETDESC_IOCTL, (unsigned long)((uintptr_t)desc)); file_close(&filestruct); diff --git a/boards/arm/stm32/photon/configs/adb/defconfig b/boards/arm/stm32/photon/configs/adb/defconfig index 3507e390edff8..9e1d5337fae25 100644 --- a/boards/arm/stm32/photon/configs/adb/defconfig +++ b/boards/arm/stm32/photon/configs/adb/defconfig @@ -33,6 +33,7 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INIT_ENTRYPOINT="adbd_main" CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBUV=y CONFIG_MM_REGIONS=2 CONFIG_NSH_BUILTIN_APPS=y @@ -43,6 +44,7 @@ CONFIG_PHOTON_DFU_BOOTLOADER=y CONFIG_PHOTON_IWDG=y CONFIG_PHOTON_WDG_THREAD=y CONFIG_PREALLOC_TIMERS=4 +CONFIG_PSEUDOTERM=y CONFIG_RAMLOG=y CONFIG_RAMLOG_BUFSIZE=2048 CONFIG_RAMLOG_SYSLOG=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig index 8df134b8d029a..28396d4512fe7 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/adb/defconfig @@ -47,11 +47,13 @@ CONFIG_FILE_STREAM=y CONFIG_FS_PROCFS=y CONFIG_INIT_ENTRYPOINT="adbd_main" CONFIG_INIT_STACKSIZE=1024 +CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBUV=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=1024 CONFIG_NSH_LINELEN=80 +CONFIG_PSEUDOTERM=y CONFIG_RAM_SIZE=20480 CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y diff --git a/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig index 4e858180958f0..6770507cff9b4 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/nsh/defconfig @@ -16,7 +16,6 @@ # CONFIG_NSH_DISABLE_EXIT is not set # CONFIG_NSH_DISABLE_FREE is not set # CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HELP is not set # CONFIG_NSH_DISABLE_HEXDUMP is not set # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MKDIR is not set diff --git a/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig b/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig index b747f911c7e7a..25234cee9ce5d 100644 --- a/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig +++ b/boards/arm/stm32/stm32f103-minimum/configs/ssd1306/defconfig @@ -16,7 +16,6 @@ # CONFIG_NSH_DISABLE_EXIT is not set # CONFIG_NSH_DISABLE_FREE is not set # CONFIG_NSH_DISABLE_GET is not set -# CONFIG_NSH_DISABLE_HELP is not set # CONFIG_NSH_DISABLE_HEXDUMP is not set # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MKDIR is not set diff --git a/boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c b/boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c index 7dfe7d4460db6..d228b1bc9c61e 100644 --- a/boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c +++ b/boards/arm/stm32/stm32f103-minimum/src/stm32_bringup.c @@ -138,6 +138,11 @@ #include #endif +#ifdef CONFIG_I2C_DRIVER +#include +#include "stm32_i2c.h" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -172,6 +177,37 @@ # define MMCSD_MINOR 0 #endif +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ +#ifdef CONFIG_I2C_DRIVER +static void stm32_i2c_register(int bus) +{ + FAR struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + /**************************************************************************** * Private Data ****************************************************************************/ @@ -224,6 +260,19 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_I2C_DRIVER + /* Register I2C drivers on behalf of the I2C tool */ + #ifdef CONFIG_STM32_I2C1 + stm32_i2c_register(1); + #endif + #ifdef CONFIG_STM32_I2C2 + stm32_i2c_register(2); + #endif + #ifdef CONFIG_STM32_I2C3 + stm32_i2c_register(3); + #endif +#endif + #ifdef CONFIG_LCD_BACKPACK /* slcd:0, i2c:1, rows=2, cols=16 */ diff --git a/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig b/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig index 3937bcb12f4a8..53f4f96f47d05 100644 --- a/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig +++ b/boards/arm/stm32/stm32f334-disco/configs/powerled/defconfig @@ -15,7 +15,6 @@ # CONFIG_NSH_DISABLE_ENV is not set # CONFIG_NSH_DISABLE_EXPORT is not set # CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_HELP is not set # CONFIG_NSH_DISABLE_ITEF is not set # CONFIG_NSH_DISABLE_LOOPS is not set # CONFIG_NSH_DISABLE_LS is not set diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig new file mode 100644 index 0000000000000..63b2978778d21 --- /dev/null +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/adc/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_ADC1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig new file mode 100644 index 0000000000000..bff4a705267fb --- /dev/null +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/dac/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_PWM=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_CH1OUT=y +CONFIG_STM32_TIM3_PWM=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig new file mode 100644 index 0000000000000..decf1124942d1 --- /dev/null +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/hcsr04/defconfig @@ -0,0 +1,67 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_HCSR04=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_FREERUN=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig new file mode 100644 index 0000000000000..f65cc04dff2cb --- /dev/null +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/lm75/defconfig @@ -0,0 +1,73 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2CTOOL_MAXBUS=1 +CONFIG_I2CTOOL_MINBUS=1 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_LM75=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_I2C1=y +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_LM75=y +CONFIG_SYSTEM_LM75_CELSIUS=y +CONFIG_SYSTEM_LM75_DEVNAME="/dev/temp0" +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig new file mode 100644 index 0000000000000..da3463cf27bb9 --- /dev/null +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_master/defconfig @@ -0,0 +1,77 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MB_MASTER_FUNC_READWRITE_HOLDING_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_READ_COILS_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_READ_DISCRETE_INPUTS_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_READ_INPUT_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_WRITE_COIL_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_WRITE_HOLDING_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_WRITE_MULTIPLE_COILS_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_WRITE_MULTIPLE_HOLDING_ENABLED is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=4 +CONFIG_EXAMPLES_MODBUSMASTER=y +CONFIG_EXAMPLES_MODBUSMASTER_SLAVEADDR=10 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_MB_RTU_MASTER=y +CONFIG_MODBUS=y +CONFIG_MODBUS_MASTER=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_BAUD=38400 +CONFIG_USART2_PARITY=2 +CONFIG_USART2_RS485=y +CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig new file mode 100644 index 0000000000000..6c78a8ca9a09c --- /dev/null +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/modbus_slave/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MB_ASCII_ENABLED is not set +# CONFIG_MB_TCP_ENABLED is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=4 +CONFIG_EXAMPLES_MODBUS=y +CONFIG_EXAMPLES_MODBUS_PORT=1 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_MODBUS=y +CONFIG_MODBUS_SLAVE=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART2=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART2_BAUD=38400 +CONFIG_USART2_PARITY=2 +CONFIG_USART2_RS485=y +CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig index d9fb2d4370b2e..fed70c4f38cee 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/nsh/defconfig @@ -26,9 +26,8 @@ CONFIG_EXAMPLES_BUTTONS=y CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" -CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" CONFIG_EXAMPLES_BUTTONS_NAMES=y -CONFIG_EXAMPLES_BUTTONS_QTD=4 +CONFIG_EXAMPLES_BUTTONS_QTD=3 CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INIT_ENTRYPOINT="nsh_main" @@ -54,7 +53,7 @@ CONFIG_START_YEAR=2014 CONFIG_STM32_JTAG_SW_ENABLE=y CONFIG_STM32_OTGFS=y CONFIG_STM32_PWR=y -CONFIG_STM32_USART2=y +CONFIG_STM32_USART6=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig new file mode 100644 index 0000000000000..31b8275d9b0ca --- /dev/null +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/qencoder/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_QENCODER=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_QENCODER=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_TIM3=y +CONFIG_STM32_TIM3_QE=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig new file mode 100644 index 0000000000000..c5c17297957a8 --- /dev/null +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/rndis/defconfig @@ -0,0 +1,89 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_FS_PROCFS=y +CONFIG_FS_TMPFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_MEMFD_ERROR=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0x0 +CONFIG_NETINIT_NETMASK=0x0 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ARP_SEND=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RNDIS=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig index 5c50b8bacc865..0bac727099ead 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/sdcard/defconfig @@ -64,7 +64,7 @@ CONFIG_STM32_OTGFS=y CONFIG_STM32_PWR=y CONFIG_STM32_SDIO=y CONFIG_STM32_SDIO_CARD=y -CONFIG_STM32_USART2=y +CONFIG_STM32_USART6=y CONFIG_SYSTEM_NSH=y CONFIG_TASK_NAME_SIZE=0 -CONFIG_USART2_SERIAL_CONSOLE=y +CONFIG_USART6_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig new file mode 100644 index 0000000000000..8711ce9f4ac96 --- /dev/null +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/ssd1309/defconfig @@ -0,0 +1,71 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_EXAMPLES_FB=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_DD12864WO4A=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_NOGETRUN=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SPI1=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y +CONFIG_VIDEO_FB=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig new file mode 100644 index 0000000000000..c6a1565467cf8 --- /dev/null +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/usbmsc/defconfig @@ -0,0 +1,74 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set +# CONFIG_MMCSD_SPI is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAME3="SW6" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=4 +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_SDIO=y +CONFIG_STM32_SDIO_CARD=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBMSC=y +CONFIG_USBMSC_REMOVABLE=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig b/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig new file mode 100644 index 0000000000000..c72f161aef13b --- /dev/null +++ b/boards/arm/stm32/stm32f401rc-rs485/configs/usbnsh/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_FPU is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f401rc-rs485" +CONFIG_ARCH_BOARD_STM32F401RC_RS485=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="stm32" +CONFIG_ARCH_CHIP_STM32=y +CONFIG_ARCH_CHIP_STM32F401RC=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=8499 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_EXAMPLES_BUTTONS_NAME0="SW3" +CONFIG_EXAMPLES_BUTTONS_NAME1="SW4" +CONFIG_EXAMPLES_BUTTONS_NAME2="SW5" +CONFIG_EXAMPLES_BUTTONS_NAMES=y +CONFIG_EXAMPLES_BUTTONS_QTD=3 +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=98304 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2014 +CONFIG_STM32_JTAG_SW_ENABLE=y +CONFIG_STM32_OTGFS=y +CONFIG_STM32_PWR=y +CONFIG_STM32_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32/stm32f401rc-rs485/include/board.h b/boards/arm/stm32/stm32f401rc-rs485/include/board.h index 76400eae09a42..6ade75f5cb2b2 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/include/board.h +++ b/boards/arm/stm32/stm32f401rc-rs485/include/board.h @@ -256,47 +256,58 @@ extern "C" /* Alternate function pin selections ****************************************/ -/* USART1: - * RXD: PA10 CN9 pin 3, CN10 pin 33 - * PB7 CN7 pin 21 - * TXD: PA9 CN5 pin 1, CN10 pin 21 - * PB6 CN5 pin 3, CN10 pin 17 +/* USART2: + * RXD: PA3 CN4 pin 20 + * TXD: PA2 CN4 pin 18 */ -#if 1 -# define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */ -# define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */ -#else -# define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */ -# define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */ -#endif +#ifdef CONFIG_USART2_RS485 + /* Lets use for RS485 */ -/* USART2: - * RXD: PA3 CN9 pin 1 (See SB13, 14, 62, 63). CN10 pin 37 - * PD6 - * TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35 - * PD5 - */ +# define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */ +# define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */ -#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */ -#define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */ -#define GPIO_USART2_RTS GPIO_USART2_RTS_2 -#define GPIO_USART2_CTS GPIO_USART2_CTS_2 + /* RS485 DIR pin: PA1 */ + +# define GPIO_USART2_RS485_DIR (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\ + GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN1) + +#endif /* USART6: - * RXD: PC7 CN5 pin2, CN10 pin 19 - * PA12 CN10, pin 12 - * TXD: PC6 CN10, pin 4 - * PA11 CN10, pin 14 + * RXD: PC7 CN2 pin 15 + * TXD: PC6 CN2 pin 17 */ #define GPIO_USART6_RX GPIO_USART6_RX_1 /* PC7 */ #define GPIO_USART6_TX GPIO_USART6_TX_1 /* PC6 */ -/* UART RX DMA configurations */ +/* PWM + * + * The STM32F401RC-RS485 has no real on-board PWM devices, but the board + * can be configured to output a pulse train using TIM3 CH1 on PA6. + */ + +#define GPIO_TIM3_CH1OUT GPIO_TIM3_CH1OUT_1 + +/* Quadrature Encoder + * + * Use Timer 3 (TIM3) on channels 1 and 2 for QEncoder, using PB4 and PA7. + */ + +#define GPIO_TIM3_CH1IN GPIO_TIM3_CH1IN_2 +#define GPIO_TIM3_CH2IN GPIO_TIM3_CH2IN_1 + +/* HCSR04 driver */ + +/* Pins config to use with HC-SR04 sensor */ + +#define GPIO_HCSR04_INT (GPIO_INPUT |GPIO_FLOAT |GPIO_EXTI | GPIO_PORTB | GPIO_PIN1) +#define GPIO_HCSR04_TRIG (GPIO_OUTPUT_CLEAR | GPIO_OUTPUT | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN0) -#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 -#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 +#define BOARD_HCSR04_GPIO_INT GPIO_HCSR04_INT +#define BOARD_HCSR04_GPIO_TRIG GPIO_HCSR04_TRIG +#define BOARD_HCSR04_FRTIMER 1 /* TIM1 as free running timer */ /* I2C * @@ -379,20 +390,18 @@ extern "C" #define LED_PANIC 1 /* Buttons - * The STM32F401RC-RS485 has 4 user buttons: SW3, SW4, SW5 and - * SW6. They are connected to PB13, PB14, PB15 and PC6 respectively. + * The STM32F401RC-RS485 has 3 user buttons: SW3, SW4, and SW5. + * They are connected to PB13, PB14, and PB15 respectively. */ #define BUTTON_SW3 0 #define BUTTON_SW4 1 #define BUTTON_SW5 2 -#define BUTTON_SW6 3 -#define NUM_BUTTONS 4 +#define NUM_BUTTONS 3 #define BUTTON_SW3_BIT (1 << BUTTON_SW3) #define BUTTON_SW4_BIT (1 << BUTTON_SW4) #define BUTTON_SW5_BIT (1 << BUTTON_SW5) -#define BUTTON_SW6_BIT (1 << BUTTON_SW6) #define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_1 | GPIO_PULLUP) #define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1 | GPIO_PULLUP) diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/CMakeLists.txt b/boards/arm/stm32/stm32f401rc-rs485/src/CMakeLists.txt index 0c135ed752ae6..ac84ab514ea3d 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/CMakeLists.txt +++ b/boards/arm/stm32/stm32f401rc-rs485/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32/smt32f401rc-rs485/src/CMakeLists.txt +# boards/arm/stm32/stm32f401rc-rs485/src/CMakeLists.txt # # Licensed to the Apache Software Foundation (ASF) under one or more contributor # license agreements. See the NOTICE file distributed with this work for @@ -36,14 +36,30 @@ if(CONFIG_ARCH_BUTTONS) list(APPEND SRCS stm32_buttons.c) endif() +if(CONFIG_ADC) + list(APPEND SRCS stm32_adc.c) +endif() + if(CONFIG_STM32_SDIO) list(APPEND SRCS stm32_sdio.c) endif() +if(CONFIG_STM32_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + if(CONFIG_STM32_CONFIG_I2C_EE_24XXEEPROM) list(APPEND SRCS stm32_at24.c) endif() +if(CONFIG_STM32_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + target_sources(board PRIVATE ${SRCS}) if(CONFIG_ARCH_CHIP_STM32F401RC) diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/Make.defs b/boards/arm/stm32/stm32f401rc-rs485/src/Make.defs index 1ef2e1ece06dc..c482c747a1af0 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/Make.defs +++ b/boards/arm/stm32/stm32f401rc-rs485/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32/smt32f401rc-rs485/src/Make.defs +# boards/arm/stm32/stm32f401rc-rs485/src/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with @@ -20,8 +20,13 @@ include $(TOPDIR)/Make.defs -CSRCS = stm32_boot.c stm32_bringup.c +CSRCS = stm32_boot.c stm32_bringup.c stm32_spi.c +ifeq ($(CONFIG_VIDEO_FB),y) +ifeq ($(CONFIG_LCD_SSD1306),y) + CSRCS += stm32_lcd_ssd1306.c +endif +endif ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += stm32_autoleds.c @@ -39,14 +44,30 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += stm32_buttons.c endif +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + ifeq ($(CONFIG_STM32_SDIO),y) CSRCS += stm32_sdio.c endif +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + ifeq ($(CONFIG_I2C_EE_24XX),y) CSRCS += stm32_at24.c endif +ifeq ($(CONFIG_STM32_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + DEPPATH += --dep-path board VPATH += :board CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c new file mode 100644 index 0000000000000..83d304f30fd12 --- /dev/null +++ b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * boards/arm/stm32/stm32f401rc-rs485/src/stm32_adc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32_adc.h" +#include "stm32f401rc-rs485.h" + +#ifdef CONFIG_STM32_ADC1 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 2 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Identifying number of each ADC channel. */ + +/* There are two trimpots on the board connected to ADC1_IN0 and ADC1_IN4 */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 0, 4 +}; + +/* Configurations of pins used byte each ADC channels */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC1_IN0, + GPIO_ADC1_IN4 +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(void) +{ + struct adc_dev_s *adc; + int ret; + int i; + + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_adc1_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + aerr("ERROR: adc_register failed: %d\n", ret); + return ret; + } + + return OK; +} + +#endif /* CONFIG_STM32_ADC1 */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_boot.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_boot.c index bd2179b98d542..9191160faa231 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_boot.c +++ b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_boot.c @@ -57,6 +57,16 @@ void stm32_boardinitialize(void) #ifdef CONFIG_ARCH_LEDS board_autoled_initialize(); #endif + + /* Configure SPI chip selects if + * 1) SPI is not disabled, and + * 2) the weak function stm32_spidev_initialize() has been brought into + * the link. + */ + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) + stm32_spidev_initialize(); +#endif } /**************************************************************************** diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c index d9d138614c4c3..5695084a3c186 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c +++ b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_bringup.c @@ -47,6 +47,22 @@ #include +#ifdef CONFIG_SENSORS_LM75 +#include "stm32_lm75.h" +#endif + +#ifdef CONFIG_SENSORS_QENCODER +#include "board_qencoder.h" +#endif + +#ifdef CONFIG_RNDIS +# include +#endif + +#ifdef CONFIG_SENSORS_HCSR04 +#include "stm32_hcsr04.h" +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -145,6 +161,16 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_LM75_I2C + /* Configure and initialize the LM75 sensor */ + + ret = board_lm75_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_lm75_initialize() failed: %d\n", ret); + } +#endif + #ifdef CONFIG_INPUT_BUTTONS /* Register the BUTTON driver */ @@ -155,6 +181,36 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + ret = stm32_adc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + #ifdef HAVE_SDIO /* Initialize the SDIO block driver */ @@ -167,5 +223,39 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_SENSORS_QENCODER + /* Initialize and register the qencoder driver */ + + ret = board_qencoder_initialize(0, STM32F401RCRS485_QETIMER); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#if defined(CONFIG_RNDIS) && !defined(CONFIG_RNDIS_COMPOSITE) + uint8_t mac[6]; + mac[0] = 0xa0; /* TODO */ + mac[1] = (CONFIG_NETINIT_MACADDR_2 >> (8 * 0)) & 0xff; + mac[2] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 3)) & 0xff; + mac[3] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 2)) & 0xff; + mac[4] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 1)) & 0xff; + mac[5] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 0)) & 0xff; + usbdev_rndis_initialize(mac); +#endif + +#ifdef CONFIG_SENSORS_HCSR04 + /* Configure and initialize the HC-SR04 distance sensor */ + + ret = board_hcsr04_initialize(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_hcsr04_initialize() failed: %d\n", ret); + } +#endif + return ret; } diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_buttons.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_buttons.c index 85d2e79a263ee..8f7dfc1aaaea2 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_buttons.c +++ b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_buttons.c @@ -46,7 +46,7 @@ static const uint32_t g_buttons[NUM_BUTTONS] = { - GPIO_BTN_SW3, GPIO_BTN_SW4, GPIO_BTN_SW5, GPIO_BTN_SW6 + GPIO_BTN_SW3, GPIO_BTN_SW4, GPIO_BTN_SW5 }; /**************************************************************************** diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c new file mode 100644 index 0000000000000..bee053cc0ecfb --- /dev/null +++ b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * boards/arm/stm32/stm32f401rc-rs485/src/stm32_lcd_ssd1306.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32.h" +#include "stm32f401rc-rs485.h" + +#include "stm32_ssd1306.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define OLED_SPI_PORT 1 /* OLED display connected to SPI1 */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_lcd_initialize + ****************************************************************************/ + +int board_lcd_initialize(void) +{ + int ret; + + /* Initialize the RESET and DC pins */ + + stm32_configgpio(GPIO_OLED_RESET); + stm32_configgpio(GPIO_OLED_DC); + + /* Reset the OLED display */ + + stm32_gpiowrite(GPIO_OLED_RESET, 0); + up_mdelay(1); + stm32_gpiowrite(GPIO_OLED_RESET, 1); + up_mdelay(120); + + ret = board_ssd1306_initialize(OLED_SPI_PORT); + if (ret < 0) + { + lcderr("ERROR: Failed to initialize SSD1306\n"); + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: board_lcd_getdev + ****************************************************************************/ + +struct lcd_dev_s *board_lcd_getdev(int devno) +{ + return board_ssd1306_getdev(); +} + +/**************************************************************************** + * Name: board_lcd_uninitialize + ****************************************************************************/ + +void board_lcd_uninitialize(void) +{ + /* TO-FIX */ +} diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_pwm.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_pwm.c new file mode 100644 index 0000000000000..80eacc99644de --- /dev/null +++ b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_pwm.c @@ -0,0 +1,119 @@ +/**************************************************************************** + * boards/arm/stm32/stm32f401rc-rs485/src/stm32_pwm.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "stm32f401rc-rs485.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* PWM + * + * The STM32F401RC-RS485 has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM3 CH1. + * + */ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM3 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32_TIM3_PWM +# undef HAVE_PWM +#endif + +#if !defined(CONFIG_STM32_TIM3_CHANNEL) || CONFIG_STM32_TIM3_CHANNEL != STM32F401RCRS485_PWMCHANNEL +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Call stm32_pwminitialize() to get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(STM32F401RCRS485_PWMTIMER); + if (!pwm) + { + aerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + aerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_spi.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_spi.c new file mode 100644 index 0000000000000..db5633957f8c5 --- /dev/null +++ b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_spi.c @@ -0,0 +1,192 @@ +/**************************************************************************** + * boards/arm/stm32/stm32f401rc-rs485/src/stm32_spi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32.h" +#include "stm32f401rc-rs485.h" + +#if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || \ + defined(CONFIG_STM32_SPI3) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the stm32f401rc-rs485 + * board. + * + ****************************************************************************/ + +void weak_function stm32_spidev_initialize(void) +{ +#ifdef CONFIG_STM32_SPI1 + stm32_configgpio(GPIO_OLED_CS); /* OLED chip select */ +#endif +} + +/**************************************************************************** + * Name: stm32_spi1/2/3select and stm32_spi1/2/3status + * + * Description: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * (including stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_SPI1 +void stm32_spi1select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + stm32_gpiowrite(GPIO_OLED_CS, !selected); +} + +uint8_t stm32_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +void stm32_spi2select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +void stm32_spi3select(struct spi_dev_s *dev, + uint32_t devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} + +uint8_t stm32_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_spi1cmddata + * + * Description: + * Set or clear the SH1101A A0 or SD1306 D/C n bit to select data (true) + * or command (false). This function must be provided by platform-specific + * logic. This is an implementation of the cmddata method of the SPI + * interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * + * Input Parameters: + * + * spi - SPI device that controls the bus the device that requires the CMD/ + * DATA selection. + * devid - If there are multiple devices on the bus, this selects which one + * to select cmd or data. NOTE: This design restricts, for example, + * one one SPI display per SPI bus. + * cmd - true: select command; false: select data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_STM32_SPI1 +int stm32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ +#if defined(CONFIG_LCD_SSD1306) + if (devid == SPIDEV_DISPLAY(0)) + { + /* This is the Data/Command control pad which determines whether the + * data bits are data or a command. + */ + + stm32_gpiowrite(GPIO_OLED_DC, !cmd); + + return OK; + } +#endif + + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI2 +int stm32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +#ifdef CONFIG_STM32_SPI3 +int stm32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ + +#endif /* CONFIG_STM32_SPI1 || CONFIG_STM32_SPI2 */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c new file mode 100644 index 0000000000000..eb82d257418b0 --- /dev/null +++ b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c @@ -0,0 +1,92 @@ +/**************************************************************************** + * boards/arm/stm32/stm32f401rc-rs485/src/stm32_usb.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "stm32_otgfs.h" +#include "stm32_gpio.h" +#include "stm32f401rc-rs485.h" + +#ifdef CONFIG_STM32_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but CONFIG_USBDEV is not" +# undef HAVE_USB +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usb_configure + * + * Description: + * Called from stm32_boardinitialize very early in inialization to setup + * USB-related GPIO pins for the Olimex STM32 P407 board. + * + ****************************************************************************/ + +void stm32_usb_configure(void) +{ +#ifdef CONFIG_STM32_OTGFS + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* We don´t have the OTG FS VBUS sensing GPIO */ +#endif +} + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usbmsc.c b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..7992f9b3f68ec --- /dev/null +++ b/boards/arm/stm32/stm32f401rc-rs485/src/stm32_usbmsc.c @@ -0,0 +1,70 @@ +/**************************************************************************** + * boards/arm/stm32/stm32f401rc-rs485/src/stm32_usbmsc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "stm32.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization of the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized in board_app_initialize() + * (see stm32_appinit.c). + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + return stm32_mmcsd_initialize(port, CONFIG_SYSTEM_USBMSC_DEVMINOR1); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h b/boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h index 261d533b62a92..d123bb0374292 100644 --- a/boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h +++ b/boards/arm/stm32/stm32f401rc-rs485/src/stm32f401rc-rs485.h @@ -75,16 +75,15 @@ GPIO_SPEED_50MHz) /* Buttons - * The STM32F401RC-RS485 has 4 user buttons. + * The STM32F401RC-RS485 has 3 user buttons. * - SW3 is connected to the GPIO PB13. * - SW4 is connected to the GPIO PB14. * - SW5 is connected to the GPIO PB15. - * - SW6 is connected to the GPIO PC6. */ #define MIN_IRQBUTTON BUTTON_SW3 -#define MAX_IRQBUTTON BUTTON_SW6 -#define NUM_IRQBUTTONS 4 +#define MAX_IRQBUTTON BUTTON_SW5 +#define NUM_IRQBUTTONS 3 #define GPIO_BTN_SW3 \ (GPIO_INPUT |GPIO_FLOAT |GPIO_EXTI | GPIO_PORTB | GPIO_PIN13) @@ -92,29 +91,17 @@ (GPIO_INPUT |GPIO_FLOAT |GPIO_EXTI | GPIO_PORTB | GPIO_PIN14) #define GPIO_BTN_SW5 \ (GPIO_INPUT |GPIO_FLOAT |GPIO_EXTI | GPIO_PORTB | GPIO_PIN15) -#define GPIO_BTN_SW6 \ - (GPIO_INPUT |GPIO_FLOAT |GPIO_EXTI | GPIO_PORTC | GPIO_PIN6) -/* The shield uses the following pins: - * - * +5V - * GND - * SERIAL_TX=PA_2 USER_BUTTON=PC_13 - * SERIAL_RX=PA_3 LD2=PA_5 - * - * Analog Digital - * A0=PA_0 USART2RX D0=PA_3 D8 =PA_9 - * A1=PA_1 USART2TX D1=PA_2 D9 =PC_7 - * A2=PA_4 D2=PA_10 WIFI_CS=D10=PB_6 SPI_CS - * A3=PB_0 WIFI_INT=D3=PB_3 D11=PA_7 SPI_MOSI - * A4=PC_1 SD_CS=D4=PB_5 D12=PA_6 SPI_MISO - * A5=PC_0 WIFI_EN=D5=PB_4 LD2=D13=PA_5 SPI_SCK - * LED2=D6=PB_10 I2C1_SDA=D14=PB_9 WIFI Probe - * D7=PA_8 I2C1_SCL=D15=PB_8 WIFI Probe - * - * mostly from: https://mbed.org/platforms/ST-Nucleo-F401RE/ - * - */ +/* OLED SSD1309 */ + +#if defined(CONFIG_LCD_SSD1306) +# define GPIO_OLED_RESET (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN6) +# define GPIO_OLED_CS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN7) +# define GPIO_OLED_DC (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8) +#endif /* SPI1 off */ @@ -125,24 +112,6 @@ #define GPIO_SPI1_SCK_OFF (GPIO_INPUT | GPIO_PULLDOWN | \ GPIO_PORTA | GPIO_PIN5) -/* SSD1306 */ - -#define GPIO_SSD1306_CS (GPIO_OUTPUT|GPIO_OTYPER_PP(0)|GPIO_SPEED_2MHz|\ - GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN6) - -#define GPIO_SSD1306_CMD (GPIO_OUTPUT|GPIO_OTYPER_PP(0)|GPIO_OSPEED_2MHz|\ - GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN7) - -#define GPIO_SSD1306_RST (GPIO_OUTPUT|GPIO_OTYPER_PP(0)|GPIO_SPEED_2MHz|\ - GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN9) - -/* MCP2551 */ - -#define GPIO_MCP2515_CS (GPIO_OUTPUT|GPIO_OTYPER_PP(0)|GPIO_SPEED_2MHz|\ - GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN4) - -#define GPIO_MCP2515_IRQ (GPIO_INPUT|GPIO_FLOAT|GPIO_PORTA|GPIO_PIN1) - #ifdef HAVE_MMCSD # define GPIO_SPI_CS_SD_CARD_OFF \ (GPIO_INPUT | GPIO_PULLDOWN | GPIO_SPEED_2MHz | \ @@ -155,88 +124,21 @@ GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN5) #endif -/* Devices on the onboard bus. +/* PWM * - * Note that these are unshifted addresses. + * The STM32F401RC-RS485 has no real on-board PWM devices, but the board can + * be configured to output a pulse train using TIM3 CH1 on PA6. */ -#define NUCLEO_I2C_OBDEV_LED 0x55 -#define NUCLEO_I2C_OBDEV_HMC5883 0x1e - -/* Itead Joystick Shield - * - * See http://imall.iteadstudio.com/im120417014.html for more information - * about this joystick. - * - * --------- ----------------- --------------------------------- - * ARDUINO ITEAD NUCLEO-F4x1 - * PIN NAME SIGNAL SIGNAL - * --------- ----------------- --------------------------------- - * D3 Button E Output PB3 - * D4 Button D Output PB5 - * D5 Button C Output PB4 - * D6 Button B Output PB10 - * D7 Button A Output PA8 - * D8 Button F Output PA9 - * D9 Button G Output PC7 - * A0 Joystick Y Output PA0 ADC1_0 - * A1 Joystick X Output PA1 ADC1_1 - * --------- ----------------- --------------------------------- - * - * All buttons are pulled on the shield. A sensed low value indicates - * when the button is pressed. - * - * NOTE: Button F cannot be used with the default USART1 configuration - * because PA9 is configured for USART1_RX by default. Use select - * different USART1 pins in the board.h file or select a different - * USART or select CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS which will - * eliminate all but buttons A, B, and C. - */ +#define STM32F401RCRS485_PWMTIMER 3 +#define STM32F401RCRS485_PWMCHANNEL 1 -#define ADC_XOUPUT 1 /* X output is on ADC channel 1 */ -#define ADC_YOUPUT 0 /* Y output is on ADC channel 0 */ - -#define GPIO_BUTTON_A \ - (GPIO_INPUT | GPIO_PULLUP |GPIO_EXTI | GPIO_PORTA | GPIO_PIN8) -#define GPIO_BUTTON_B \ - (GPIO_INPUT | GPIO_PULLUP |GPIO_EXTI | GPIO_PORTB | GPIO_PIN10) -#define GPIO_BUTTON_C \ - (GPIO_INPUT | GPIO_PULLUP |GPIO_EXTI | GPIO_PORTB | GPIO_PIN4) -#define GPIO_BUTTON_D \ - (GPIO_INPUT | GPIO_PULLUP |GPIO_EXTI | GPIO_PORTB | GPIO_PIN5) -#define GPIO_BUTTON_E \ - (GPIO_INPUT | GPIO_PULLUP |GPIO_EXTI | GPIO_PORTB | GPIO_PIN3) -#define GPIO_BUTTON_F \ - (GPIO_INPUT | GPIO_PULLUP |GPIO_EXTI | GPIO_PORTA | GPIO_PIN9) -#define GPIO_BUTTON_G \ - (GPIO_INPUT | GPIO_PULLUP |GPIO_EXTI | GPIO_PORTC | GPIO_PIN7) - -/* Itead Joystick Signal interpretation: +/* Quadrature Encoder * - * --------- ----------------------- --------------------------- - * BUTTON TYPE NUTTX ALIAS - * --------- ----------------------- --------------------------- - * Button A Large button A JUMP/BUTTON 3 - * Button B Large button B FIRE/BUTTON 2 - * Button C Joystick select button SELECT/BUTTON 1 - * Button D Tiny Button D BUTTON 6 - * Button E Tiny Button E BUTTON 7 - * Button F Large Button F BUTTON 4 - * Button G Large Button G BUTTON 5 - * --------- ----------------------- --------------------------- + * Use Timer 3 (TIM3) on channels 1 and 2 for QEncoder, using PB4 and PA7. */ -#define GPIO_BUTTON_1 GPIO_BUTTON_C -#define GPIO_BUTTON_2 GPIO_BUTTON_B -#define GPIO_BUTTON_3 GPIO_BUTTON_A -#define GPIO_BUTTON_4 GPIO_BUTTON_F -#define GPIO_BUTTON_5 GPIO_BUTTON_G -#define GPIO_BUTTON_6 GPIO_BUTTON_D -#define GPIO_BUTTON_7 GPIO_BUTTON_E - -#define GPIO_SELECT GPIO_BUTTON_1 -#define GPIO_FIRE GPIO_BUTTON_2 -#define GPIO_JUMP GPIO_BUTTON_3 +#define STM32F401RCRS485_QETIMER 3 /**************************************************************************** * Public Data @@ -311,27 +213,18 @@ int stm32_adc_setup(void); #endif /**************************************************************************** - * Name: board_ajoy_initialize + * Name: stm32_pwm_setup * * Description: - * Initialize and register the button joystick driver - * - ****************************************************************************/ - -#ifdef CONFIG_INPUT_AJOYSTICK -int board_ajoy_initialize(void); -#endif - -/**************************************************************************** - * Name: stm32_mcp2515initialize + * Initialize PWM and register the PWM device. * - * Description: - * Initialize and register the MCP2515 CAN driver. + * Return Value: + * OK on success; a negated errno value on failure. * ****************************************************************************/ -#ifdef CONFIG_CAN_MCP2515 -int stm32_mcp2515initialize(const char *devpath); +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); #endif /**************************************************************************** @@ -366,4 +259,16 @@ struct i2c_master_s *stm32_i2cbus_initialize(int port); int stm32_at24_init(char *path); +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +#ifdef CONFIG_ADC +int stm32_adc_setup(void); +#endif + #endif /* __BOARDS_ARM_STM32_STM32F401RC_RS485_SRC_STM32F401RC_RS485_H */ diff --git a/boards/arm/stm32/stm32f411-minimum/Kconfig b/boards/arm/stm32/stm32f411-minimum/Kconfig index 9691e7195f87a..43f2f0018b8a8 100644 --- a/boards/arm/stm32/stm32f411-minimum/Kconfig +++ b/boards/arm/stm32/stm32f411-minimum/Kconfig @@ -34,4 +34,53 @@ config STM32F411MINIMUM_FLASH_MINOR ---help--- Sets the minor number for the FLASH MTD /dev entry +menuconfig STM32F411MINIMUM_HX711 + bool "Enable hx711 scale sensor" + default n + select ADC_HX711 + +if STM32F411MINIMUM_HX711 + +choice + prompt "Select GPIO port for clock pin" + default STM32F411MINIMUM_HX711_CLK_PORTA + +config STM32F411MINIMUM_HX711_CLK_PORTA + bool "Port A" +config STM32F411MINIMUM_HX711_CLK_PORTB + bool "Port B" + +endchoice # Select GPIO port for clock pin + +config STM32F411MINIMUM_HX711_CLK_PIN + int "Select GPIO pin number for clock pin" + default 1 + range 0 15 + +choice + prompt "Select GPIO port for data pin" + default STM32F411MINIMUM_HX711_DATA_PORTA + +config STM32F411MINIMUM_HX711_DATA_PORTA + bool "Port A" +config STM32F411MINIMUM_HX711_DATA_PORTB + bool "Port B" + +endchoice # Select GPIO port for data pin + +config STM32F411MINIMUM_HX711_DATA_PIN + int "Select GPIO pin number for data pin" + default 2 + range 0 15 + +endif # STM32F411MINIMUM_HX711 + +menuconfig STM32F411MINIMUM_GPIO + select DEV_GPIO + bool "enable gpio subsystem" + +if STM32F411MINIMUM_GPIO +source "boards/arm/stm32/stm32f411-minimum/Kconfig.gpio" +endif + endif diff --git a/boards/arm/stm32/stm32f411-minimum/Kconfig.gpio b/boards/arm/stm32/stm32f411-minimum/Kconfig.gpio new file mode 100644 index 0000000000000..75da4aaf2431b --- /dev/null +++ b/boards/arm/stm32/stm32f411-minimum/Kconfig.gpio @@ -0,0 +1,2623 @@ +config STM32F411MINIMUM_GPIO_A0 + bool "enable pin A0" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_A0 device node. + +if STM32F411MINIMUM_GPIO_A0 + +config STM32F411MINIMUM_GPIO_A0_NAME + string "Pin name" + default "gpio_a0" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_A0_OUT + +config STM32F411MINIMUM_GPIO_A0_OUT + bool "output" +config STM32F411MINIMUM_GPIO_A0_IN + bool "input" +config STM32F411MINIMUM_GPIO_A0_INT + bool "interrupt" + +endchoice # A0 Pin type + +if STM32F411MINIMUM_GPIO_A0_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_A0_OUT_OD + +config STM32F411MINIMUM_GPIO_A0_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_A0_OUT_PP + bool "push pull" + +endchoice # A0 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_A0_OUT_SET + +config STM32F411MINIMUM_GPIO_A0_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_A0_OUT_CLEAR + bool "clear" + +endchoice # A0 output default state + +endif # STM32F411MINIMUM_GPIO_A0_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_A0_PULL_UP + +config STM32F411MINIMUM_GPIO_A0_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_A0_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_A0_PULL_FLOAT + bool "float" + +endchoice # A0 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_A0_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_A0_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_A0_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_A0_SPEED_50MHz + bool "50MHz" + +endchoice # A0 speed + +endif # STM32F411MINIMUM_GPIO_A0 + +config STM32F411MINIMUM_GPIO_A1 + bool "enable pin A1" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_A1 device node. + +if STM32F411MINIMUM_GPIO_A1 + +config STM32F411MINIMUM_GPIO_A1_NAME + string "Pin name" + default "gpio_a1" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_A1_OUT + +config STM32F411MINIMUM_GPIO_A1_OUT + bool "output" +config STM32F411MINIMUM_GPIO_A1_IN + bool "input" +config STM32F411MINIMUM_GPIO_A1_INT + bool "interrupt" + +endchoice # A1 Pin type + +if STM32F411MINIMUM_GPIO_A1_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_A1_OUT_OD + +config STM32F411MINIMUM_GPIO_A1_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_A1_OUT_PP + bool "push pull" + +endchoice # A1 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_A1_OUT_SET + +config STM32F411MINIMUM_GPIO_A1_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_A1_OUT_CLEAR + bool "clear" + +endchoice # A1 output default state + +endif # STM32F411MINIMUM_GPIO_A1_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_A1_PULL_UP + +config STM32F411MINIMUM_GPIO_A1_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_A1_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_A1_PULL_FLOAT + bool "float" + +endchoice # A1 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_A1_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_A1_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_A1_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_A1_SPEED_50MHz + bool "50MHz" + +endchoice # A1 speed + +endif # STM32F411MINIMUM_GPIO_A1 + +config STM32F411MINIMUM_GPIO_A2 + bool "enable pin A2" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_A2 device node. + +if STM32F411MINIMUM_GPIO_A2 + +config STM32F411MINIMUM_GPIO_A2_NAME + string "Pin name" + default "gpio_a2" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_A2_OUT + +config STM32F411MINIMUM_GPIO_A2_OUT + bool "output" +config STM32F411MINIMUM_GPIO_A2_IN + bool "input" +config STM32F411MINIMUM_GPIO_A2_INT + bool "interrupt" + +endchoice # A2 Pin type + +if STM32F411MINIMUM_GPIO_A2_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_A2_OUT_OD + +config STM32F411MINIMUM_GPIO_A2_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_A2_OUT_PP + bool "push pull" + +endchoice # A2 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_A2_OUT_SET + +config STM32F411MINIMUM_GPIO_A2_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_A2_OUT_CLEAR + bool "clear" + +endchoice # A2 output default state + +endif # STM32F411MINIMUM_GPIO_A2_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_A2_PULL_UP + +config STM32F411MINIMUM_GPIO_A2_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_A2_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_A2_PULL_FLOAT + bool "float" + +endchoice # A2 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_A2_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_A2_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_A2_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_A2_SPEED_50MHz + bool "50MHz" + +endchoice # A2 speed + +endif # STM32F411MINIMUM_GPIO_A2 + +config STM32F411MINIMUM_GPIO_A3 + bool "enable pin A3" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_A3 device node. + +if STM32F411MINIMUM_GPIO_A3 + +config STM32F411MINIMUM_GPIO_A3_NAME + string "Pin name" + default "gpio_a3" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_A3_OUT + +config STM32F411MINIMUM_GPIO_A3_OUT + bool "output" +config STM32F411MINIMUM_GPIO_A3_IN + bool "input" +config STM32F411MINIMUM_GPIO_A3_INT + bool "interrupt" + +endchoice # A3 Pin type + +if STM32F411MINIMUM_GPIO_A3_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_A3_OUT_OD + +config STM32F411MINIMUM_GPIO_A3_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_A3_OUT_PP + bool "push pull" + +endchoice # A3 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_A3_OUT_SET + +config STM32F411MINIMUM_GPIO_A3_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_A3_OUT_CLEAR + bool "clear" + +endchoice # A3 output default state + +endif # STM32F411MINIMUM_GPIO_A3_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_A3_PULL_UP + +config STM32F411MINIMUM_GPIO_A3_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_A3_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_A3_PULL_FLOAT + bool "float" + +endchoice # A3 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_A3_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_A3_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_A3_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_A3_SPEED_50MHz + bool "50MHz" + +endchoice # A3 speed + +endif # STM32F411MINIMUM_GPIO_A3 + +config STM32F411MINIMUM_GPIO_A4 + bool "enable pin A4" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_A4 device node. + +if STM32F411MINIMUM_GPIO_A4 + +config STM32F411MINIMUM_GPIO_A4_NAME + string "Pin name" + default "gpio_a4" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_A4_OUT + +config STM32F411MINIMUM_GPIO_A4_OUT + bool "output" +config STM32F411MINIMUM_GPIO_A4_IN + bool "input" +config STM32F411MINIMUM_GPIO_A4_INT + bool "interrupt" + +endchoice # A4 Pin type + +if STM32F411MINIMUM_GPIO_A4_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_A4_OUT_OD + +config STM32F411MINIMUM_GPIO_A4_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_A4_OUT_PP + bool "push pull" + +endchoice # A4 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_A4_OUT_SET + +config STM32F411MINIMUM_GPIO_A4_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_A4_OUT_CLEAR + bool "clear" + +endchoice # A4 output default state + +endif # STM32F411MINIMUM_GPIO_A4_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_A4_PULL_UP + +config STM32F411MINIMUM_GPIO_A4_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_A4_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_A4_PULL_FLOAT + bool "float" + +endchoice # A4 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_A4_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_A4_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_A4_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_A4_SPEED_50MHz + bool "50MHz" + +endchoice # A4 speed + +endif # STM32F411MINIMUM_GPIO_A4 + +config STM32F411MINIMUM_GPIO_A5 + bool "enable pin A5" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_A5 device node. + +if STM32F411MINIMUM_GPIO_A5 + +config STM32F411MINIMUM_GPIO_A5_NAME + string "Pin name" + default "gpio_a5" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_A5_OUT + +config STM32F411MINIMUM_GPIO_A5_OUT + bool "output" +config STM32F411MINIMUM_GPIO_A5_IN + bool "input" +config STM32F411MINIMUM_GPIO_A5_INT + bool "interrupt" + +endchoice # A5 Pin type + +if STM32F411MINIMUM_GPIO_A5_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_A5_OUT_OD + +config STM32F411MINIMUM_GPIO_A5_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_A5_OUT_PP + bool "push pull" + +endchoice # A5 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_A5_OUT_SET + +config STM32F411MINIMUM_GPIO_A5_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_A5_OUT_CLEAR + bool "clear" + +endchoice # A5 output default state + +endif # STM32F411MINIMUM_GPIO_A5_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_A5_PULL_UP + +config STM32F411MINIMUM_GPIO_A5_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_A5_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_A5_PULL_FLOAT + bool "float" + +endchoice # A5 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_A5_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_A5_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_A5_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_A5_SPEED_50MHz + bool "50MHz" + +endchoice # A5 speed + +endif # STM32F411MINIMUM_GPIO_A5 + +config STM32F411MINIMUM_GPIO_A6 + bool "enable pin A6" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_A6 device node. + +if STM32F411MINIMUM_GPIO_A6 + +config STM32F411MINIMUM_GPIO_A6_NAME + string "Pin name" + default "gpio_a6" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_A6_OUT + +config STM32F411MINIMUM_GPIO_A6_OUT + bool "output" +config STM32F411MINIMUM_GPIO_A6_IN + bool "input" +config STM32F411MINIMUM_GPIO_A6_INT + bool "interrupt" + +endchoice # A6 Pin type + +if STM32F411MINIMUM_GPIO_A6_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_A6_OUT_OD + +config STM32F411MINIMUM_GPIO_A6_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_A6_OUT_PP + bool "push pull" + +endchoice # A6 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_A6_OUT_SET + +config STM32F411MINIMUM_GPIO_A6_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_A6_OUT_CLEAR + bool "clear" + +endchoice # A6 output default state + +endif # STM32F411MINIMUM_GPIO_A6_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_A6_PULL_UP + +config STM32F411MINIMUM_GPIO_A6_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_A6_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_A6_PULL_FLOAT + bool "float" + +endchoice # A6 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_A6_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_A6_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_A6_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_A6_SPEED_50MHz + bool "50MHz" + +endchoice # A6 speed + +endif # STM32F411MINIMUM_GPIO_A6 + +config STM32F411MINIMUM_GPIO_A7 + bool "enable pin A7" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_A7 device node. + +if STM32F411MINIMUM_GPIO_A7 + +config STM32F411MINIMUM_GPIO_A7_NAME + string "Pin name" + default "gpio_a7" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_A7_OUT + +config STM32F411MINIMUM_GPIO_A7_OUT + bool "output" +config STM32F411MINIMUM_GPIO_A7_IN + bool "input" +config STM32F411MINIMUM_GPIO_A7_INT + bool "interrupt" + +endchoice # A7 Pin type + +if STM32F411MINIMUM_GPIO_A7_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_A7_OUT_OD + +config STM32F411MINIMUM_GPIO_A7_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_A7_OUT_PP + bool "push pull" + +endchoice # A7 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_A7_OUT_SET + +config STM32F411MINIMUM_GPIO_A7_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_A7_OUT_CLEAR + bool "clear" + +endchoice # A7 output default state + +endif # STM32F411MINIMUM_GPIO_A7_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_A7_PULL_UP + +config STM32F411MINIMUM_GPIO_A7_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_A7_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_A7_PULL_FLOAT + bool "float" + +endchoice # A7 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_A7_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_A7_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_A7_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_A7_SPEED_50MHz + bool "50MHz" + +endchoice # A7 speed + +endif # STM32F411MINIMUM_GPIO_A7 + +config STM32F411MINIMUM_GPIO_A8 + bool "enable pin A8" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_A8 device node. + +if STM32F411MINIMUM_GPIO_A8 + +config STM32F411MINIMUM_GPIO_A8_NAME + string "Pin name" + default "gpio_a8" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_A8_OUT + +config STM32F411MINIMUM_GPIO_A8_OUT + bool "output" +config STM32F411MINIMUM_GPIO_A8_IN + bool "input" +config STM32F411MINIMUM_GPIO_A8_INT + bool "interrupt" + +endchoice # A8 Pin type + +if STM32F411MINIMUM_GPIO_A8_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_A8_OUT_OD + +config STM32F411MINIMUM_GPIO_A8_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_A8_OUT_PP + bool "push pull" + +endchoice # A8 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_A8_OUT_SET + +config STM32F411MINIMUM_GPIO_A8_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_A8_OUT_CLEAR + bool "clear" + +endchoice # A8 output default state + +endif # STM32F411MINIMUM_GPIO_A8_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_A8_PULL_UP + +config STM32F411MINIMUM_GPIO_A8_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_A8_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_A8_PULL_FLOAT + bool "float" + +endchoice # A8 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_A8_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_A8_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_A8_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_A8_SPEED_50MHz + bool "50MHz" + +endchoice # A8 speed + +endif # STM32F411MINIMUM_GPIO_A8 + +config STM32F411MINIMUM_GPIO_A9 + bool "enable pin A9" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_A9 device node. + +if STM32F411MINIMUM_GPIO_A9 + +config STM32F411MINIMUM_GPIO_A9_NAME + string "Pin name" + default "gpio_a9" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_A9_OUT + +config STM32F411MINIMUM_GPIO_A9_OUT + bool "output" +config STM32F411MINIMUM_GPIO_A9_IN + bool "input" +config STM32F411MINIMUM_GPIO_A9_INT + bool "interrupt" + +endchoice # A9 Pin type + +if STM32F411MINIMUM_GPIO_A9_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_A9_OUT_OD + +config STM32F411MINIMUM_GPIO_A9_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_A9_OUT_PP + bool "push pull" + +endchoice # A9 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_A9_OUT_SET + +config STM32F411MINIMUM_GPIO_A9_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_A9_OUT_CLEAR + bool "clear" + +endchoice # A9 output default state + +endif # STM32F411MINIMUM_GPIO_A9_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_A9_PULL_UP + +config STM32F411MINIMUM_GPIO_A9_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_A9_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_A9_PULL_FLOAT + bool "float" + +endchoice # A9 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_A9_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_A9_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_A9_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_A9_SPEED_50MHz + bool "50MHz" + +endchoice # A9 speed + +endif # STM32F411MINIMUM_GPIO_A9 + +config STM32F411MINIMUM_GPIO_A10 + bool "enable pin A10" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_A10 device node. + +if STM32F411MINIMUM_GPIO_A10 + +config STM32F411MINIMUM_GPIO_A10_NAME + string "Pin name" + default "gpio_a10" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_A10_OUT + +config STM32F411MINIMUM_GPIO_A10_OUT + bool "output" +config STM32F411MINIMUM_GPIO_A10_IN + bool "input" +config STM32F411MINIMUM_GPIO_A10_INT + bool "interrupt" + +endchoice # A10 Pin type + +if STM32F411MINIMUM_GPIO_A10_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_A10_OUT_OD + +config STM32F411MINIMUM_GPIO_A10_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_A10_OUT_PP + bool "push pull" + +endchoice # A10 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_A10_OUT_SET + +config STM32F411MINIMUM_GPIO_A10_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_A10_OUT_CLEAR + bool "clear" + +endchoice # A10 output default state + +endif # STM32F411MINIMUM_GPIO_A10_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_A10_PULL_UP + +config STM32F411MINIMUM_GPIO_A10_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_A10_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_A10_PULL_FLOAT + bool "float" + +endchoice # A10 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_A10_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_A10_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_A10_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_A10_SPEED_50MHz + bool "50MHz" + +endchoice # A10 speed + +endif # STM32F411MINIMUM_GPIO_A10 + +config STM32F411MINIMUM_GPIO_A11 + bool "enable pin A11" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_A11 device node. + +if STM32F411MINIMUM_GPIO_A11 + +config STM32F411MINIMUM_GPIO_A11_NAME + string "Pin name" + default "gpio_a11" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_A11_OUT + +config STM32F411MINIMUM_GPIO_A11_OUT + bool "output" +config STM32F411MINIMUM_GPIO_A11_IN + bool "input" +config STM32F411MINIMUM_GPIO_A11_INT + bool "interrupt" + +endchoice # A11 Pin type + +if STM32F411MINIMUM_GPIO_A11_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_A11_OUT_OD + +config STM32F411MINIMUM_GPIO_A11_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_A11_OUT_PP + bool "push pull" + +endchoice # A11 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_A11_OUT_SET + +config STM32F411MINIMUM_GPIO_A11_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_A11_OUT_CLEAR + bool "clear" + +endchoice # A11 output default state + +endif # STM32F411MINIMUM_GPIO_A11_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_A11_PULL_UP + +config STM32F411MINIMUM_GPIO_A11_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_A11_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_A11_PULL_FLOAT + bool "float" + +endchoice # A11 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_A11_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_A11_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_A11_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_A11_SPEED_50MHz + bool "50MHz" + +endchoice # A11 speed + +endif # STM32F411MINIMUM_GPIO_A11 + +config STM32F411MINIMUM_GPIO_A12 + bool "enable pin A12" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_A12 device node. + +if STM32F411MINIMUM_GPIO_A12 + +config STM32F411MINIMUM_GPIO_A12_NAME + string "Pin name" + default "gpio_a12" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_A12_OUT + +config STM32F411MINIMUM_GPIO_A12_OUT + bool "output" +config STM32F411MINIMUM_GPIO_A12_IN + bool "input" +config STM32F411MINIMUM_GPIO_A12_INT + bool "interrupt" + +endchoice # A12 Pin type + +if STM32F411MINIMUM_GPIO_A12_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_A12_OUT_OD + +config STM32F411MINIMUM_GPIO_A12_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_A12_OUT_PP + bool "push pull" + +endchoice # A12 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_A12_OUT_SET + +config STM32F411MINIMUM_GPIO_A12_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_A12_OUT_CLEAR + bool "clear" + +endchoice # A12 output default state + +endif # STM32F411MINIMUM_GPIO_A12_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_A12_PULL_UP + +config STM32F411MINIMUM_GPIO_A12_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_A12_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_A12_PULL_FLOAT + bool "float" + +endchoice # A12 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_A12_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_A12_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_A12_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_A12_SPEED_50MHz + bool "50MHz" + +endchoice # A12 speed + +endif # STM32F411MINIMUM_GPIO_A12 + +config STM32F411MINIMUM_GPIO_A15 + bool "enable pin A15" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_A15 device node. + +if STM32F411MINIMUM_GPIO_A15 + +config STM32F411MINIMUM_GPIO_A15_NAME + string "Pin name" + default "gpio_a15" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_A15_OUT + +config STM32F411MINIMUM_GPIO_A15_OUT + bool "output" +config STM32F411MINIMUM_GPIO_A15_IN + bool "input" +config STM32F411MINIMUM_GPIO_A15_INT + bool "interrupt" + +endchoice # A15 Pin type + +if STM32F411MINIMUM_GPIO_A15_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_A15_OUT_OD + +config STM32F411MINIMUM_GPIO_A15_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_A15_OUT_PP + bool "push pull" + +endchoice # A15 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_A15_OUT_SET + +config STM32F411MINIMUM_GPIO_A15_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_A15_OUT_CLEAR + bool "clear" + +endchoice # A15 output default state + +endif # STM32F411MINIMUM_GPIO_A15_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_A15_PULL_UP + +config STM32F411MINIMUM_GPIO_A15_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_A15_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_A15_PULL_FLOAT + bool "float" + +endchoice # A15 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_A15_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_A15_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_A15_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_A15_SPEED_50MHz + bool "50MHz" + +endchoice # A15 speed + +endif # STM32F411MINIMUM_GPIO_A15 + +config STM32F411MINIMUM_GPIO_B0 + bool "enable pin B0" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_B0 device node. + +if STM32F411MINIMUM_GPIO_B0 + +config STM32F411MINIMUM_GPIO_B0_NAME + string "Pin name" + default "gpio_b0" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_B0_OUT + +config STM32F411MINIMUM_GPIO_B0_OUT + bool "output" +config STM32F411MINIMUM_GPIO_B0_IN + bool "input" +config STM32F411MINIMUM_GPIO_B0_INT + bool "interrupt" + +endchoice # B0 Pin type + +if STM32F411MINIMUM_GPIO_B0_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_B0_OUT_OD + +config STM32F411MINIMUM_GPIO_B0_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_B0_OUT_PP + bool "push pull" + +endchoice # B0 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_B0_OUT_SET + +config STM32F411MINIMUM_GPIO_B0_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_B0_OUT_CLEAR + bool "clear" + +endchoice # B0 output default state + +endif # STM32F411MINIMUM_GPIO_B0_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_B0_PULL_UP + +config STM32F411MINIMUM_GPIO_B0_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_B0_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_B0_PULL_FLOAT + bool "float" + +endchoice # B0 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_B0_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_B0_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_B0_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_B0_SPEED_50MHz + bool "50MHz" + +endchoice # B0 speed + +endif # STM32F411MINIMUM_GPIO_B0 + +config STM32F411MINIMUM_GPIO_B1 + bool "enable pin B1" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_B1 device node. + +if STM32F411MINIMUM_GPIO_B1 + +config STM32F411MINIMUM_GPIO_B1_NAME + string "Pin name" + default "gpio_b1" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_B1_OUT + +config STM32F411MINIMUM_GPIO_B1_OUT + bool "output" +config STM32F411MINIMUM_GPIO_B1_IN + bool "input" +config STM32F411MINIMUM_GPIO_B1_INT + bool "interrupt" + +endchoice # B1 Pin type + +if STM32F411MINIMUM_GPIO_B1_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_B1_OUT_OD + +config STM32F411MINIMUM_GPIO_B1_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_B1_OUT_PP + bool "push pull" + +endchoice # B1 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_B1_OUT_SET + +config STM32F411MINIMUM_GPIO_B1_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_B1_OUT_CLEAR + bool "clear" + +endchoice # B1 output default state + +endif # STM32F411MINIMUM_GPIO_B1_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_B1_PULL_UP + +config STM32F411MINIMUM_GPIO_B1_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_B1_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_B1_PULL_FLOAT + bool "float" + +endchoice # B1 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_B1_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_B1_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_B1_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_B1_SPEED_50MHz + bool "50MHz" + +endchoice # B1 speed + +endif # STM32F411MINIMUM_GPIO_B1 + +config STM32F411MINIMUM_GPIO_B2 + bool "enable pin B2" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_B2 device node. + +if STM32F411MINIMUM_GPIO_B2 + +config STM32F411MINIMUM_GPIO_B2_NAME + string "Pin name" + default "gpio_b2" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_B2_OUT + +config STM32F411MINIMUM_GPIO_B2_OUT + bool "output" +config STM32F411MINIMUM_GPIO_B2_IN + bool "input" +config STM32F411MINIMUM_GPIO_B2_INT + bool "interrupt" + +endchoice # B2 Pin type + +if STM32F411MINIMUM_GPIO_B2_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_B2_OUT_OD + +config STM32F411MINIMUM_GPIO_B2_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_B2_OUT_PP + bool "push pull" + +endchoice # B2 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_B2_OUT_SET + +config STM32F411MINIMUM_GPIO_B2_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_B2_OUT_CLEAR + bool "clear" + +endchoice # B2 output default state + +endif # STM32F411MINIMUM_GPIO_B2_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_B2_PULL_UP + +config STM32F411MINIMUM_GPIO_B2_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_B2_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_B2_PULL_FLOAT + bool "float" + +endchoice # B2 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_B2_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_B2_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_B2_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_B2_SPEED_50MHz + bool "50MHz" + +endchoice # B2 speed + +endif # STM32F411MINIMUM_GPIO_B2 + +config STM32F411MINIMUM_GPIO_B3 + bool "enable pin B3" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_B3 device node. + +if STM32F411MINIMUM_GPIO_B3 + +config STM32F411MINIMUM_GPIO_B3_NAME + string "Pin name" + default "gpio_b3" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_B3_OUT + +config STM32F411MINIMUM_GPIO_B3_OUT + bool "output" +config STM32F411MINIMUM_GPIO_B3_IN + bool "input" +config STM32F411MINIMUM_GPIO_B3_INT + bool "interrupt" + +endchoice # B3 Pin type + +if STM32F411MINIMUM_GPIO_B3_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_B3_OUT_OD + +config STM32F411MINIMUM_GPIO_B3_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_B3_OUT_PP + bool "push pull" + +endchoice # B3 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_B3_OUT_SET + +config STM32F411MINIMUM_GPIO_B3_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_B3_OUT_CLEAR + bool "clear" + +endchoice # B3 output default state + +endif # STM32F411MINIMUM_GPIO_B3_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_B3_PULL_UP + +config STM32F411MINIMUM_GPIO_B3_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_B3_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_B3_PULL_FLOAT + bool "float" + +endchoice # B3 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_B3_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_B3_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_B3_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_B3_SPEED_50MHz + bool "50MHz" + +endchoice # B3 speed + +endif # STM32F411MINIMUM_GPIO_B3 + +config STM32F411MINIMUM_GPIO_B4 + bool "enable pin B4" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_B4 device node. + +if STM32F411MINIMUM_GPIO_B4 + +config STM32F411MINIMUM_GPIO_B4_NAME + string "Pin name" + default "gpio_b4" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_B4_OUT + +config STM32F411MINIMUM_GPIO_B4_OUT + bool "output" +config STM32F411MINIMUM_GPIO_B4_IN + bool "input" +config STM32F411MINIMUM_GPIO_B4_INT + bool "interrupt" + +endchoice # B4 Pin type + +if STM32F411MINIMUM_GPIO_B4_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_B4_OUT_OD + +config STM32F411MINIMUM_GPIO_B4_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_B4_OUT_PP + bool "push pull" + +endchoice # B4 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_B4_OUT_SET + +config STM32F411MINIMUM_GPIO_B4_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_B4_OUT_CLEAR + bool "clear" + +endchoice # B4 output default state + +endif # STM32F411MINIMUM_GPIO_B4_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_B4_PULL_UP + +config STM32F411MINIMUM_GPIO_B4_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_B4_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_B4_PULL_FLOAT + bool "float" + +endchoice # B4 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_B4_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_B4_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_B4_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_B4_SPEED_50MHz + bool "50MHz" + +endchoice # B4 speed + +endif # STM32F411MINIMUM_GPIO_B4 + +config STM32F411MINIMUM_GPIO_B5 + bool "enable pin B5" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_B5 device node. + +if STM32F411MINIMUM_GPIO_B5 + +config STM32F411MINIMUM_GPIO_B5_NAME + string "Pin name" + default "gpio_b5" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_B5_OUT + +config STM32F411MINIMUM_GPIO_B5_OUT + bool "output" +config STM32F411MINIMUM_GPIO_B5_IN + bool "input" +config STM32F411MINIMUM_GPIO_B5_INT + bool "interrupt" + +endchoice # B5 Pin type + +if STM32F411MINIMUM_GPIO_B5_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_B5_OUT_OD + +config STM32F411MINIMUM_GPIO_B5_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_B5_OUT_PP + bool "push pull" + +endchoice # B5 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_B5_OUT_SET + +config STM32F411MINIMUM_GPIO_B5_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_B5_OUT_CLEAR + bool "clear" + +endchoice # B5 output default state + +endif # STM32F411MINIMUM_GPIO_B5_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_B5_PULL_UP + +config STM32F411MINIMUM_GPIO_B5_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_B5_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_B5_PULL_FLOAT + bool "float" + +endchoice # B5 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_B5_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_B5_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_B5_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_B5_SPEED_50MHz + bool "50MHz" + +endchoice # B5 speed + +endif # STM32F411MINIMUM_GPIO_B5 + +config STM32F411MINIMUM_GPIO_B6 + bool "enable pin B6" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_B6 device node. + +if STM32F411MINIMUM_GPIO_B6 + +config STM32F411MINIMUM_GPIO_B6_NAME + string "Pin name" + default "gpio_b6" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_B6_OUT + +config STM32F411MINIMUM_GPIO_B6_OUT + bool "output" +config STM32F411MINIMUM_GPIO_B6_IN + bool "input" +config STM32F411MINIMUM_GPIO_B6_INT + bool "interrupt" + +endchoice # B6 Pin type + +if STM32F411MINIMUM_GPIO_B6_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_B6_OUT_OD + +config STM32F411MINIMUM_GPIO_B6_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_B6_OUT_PP + bool "push pull" + +endchoice # B6 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_B6_OUT_SET + +config STM32F411MINIMUM_GPIO_B6_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_B6_OUT_CLEAR + bool "clear" + +endchoice # B6 output default state + +endif # STM32F411MINIMUM_GPIO_B6_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_B6_PULL_UP + +config STM32F411MINIMUM_GPIO_B6_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_B6_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_B6_PULL_FLOAT + bool "float" + +endchoice # B6 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_B6_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_B6_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_B6_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_B6_SPEED_50MHz + bool "50MHz" + +endchoice # B6 speed + +endif # STM32F411MINIMUM_GPIO_B6 + +config STM32F411MINIMUM_GPIO_B7 + bool "enable pin B7" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_B7 device node. + +if STM32F411MINIMUM_GPIO_B7 + +config STM32F411MINIMUM_GPIO_B7_NAME + string "Pin name" + default "gpio_b7" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_B7_OUT + +config STM32F411MINIMUM_GPIO_B7_OUT + bool "output" +config STM32F411MINIMUM_GPIO_B7_IN + bool "input" +config STM32F411MINIMUM_GPIO_B7_INT + bool "interrupt" + +endchoice # B7 Pin type + +if STM32F411MINIMUM_GPIO_B7_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_B7_OUT_OD + +config STM32F411MINIMUM_GPIO_B7_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_B7_OUT_PP + bool "push pull" + +endchoice # B7 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_B7_OUT_SET + +config STM32F411MINIMUM_GPIO_B7_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_B7_OUT_CLEAR + bool "clear" + +endchoice # B7 output default state + +endif # STM32F411MINIMUM_GPIO_B7_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_B7_PULL_UP + +config STM32F411MINIMUM_GPIO_B7_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_B7_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_B7_PULL_FLOAT + bool "float" + +endchoice # B7 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_B7_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_B7_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_B7_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_B7_SPEED_50MHz + bool "50MHz" + +endchoice # B7 speed + +endif # STM32F411MINIMUM_GPIO_B7 + +config STM32F411MINIMUM_GPIO_B8 + bool "enable pin B8" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_B8 device node. + +if STM32F411MINIMUM_GPIO_B8 + +config STM32F411MINIMUM_GPIO_B8_NAME + string "Pin name" + default "gpio_b8" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_B8_OUT + +config STM32F411MINIMUM_GPIO_B8_OUT + bool "output" +config STM32F411MINIMUM_GPIO_B8_IN + bool "input" +config STM32F411MINIMUM_GPIO_B8_INT + bool "interrupt" + +endchoice # B8 Pin type + +if STM32F411MINIMUM_GPIO_B8_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_B8_OUT_OD + +config STM32F411MINIMUM_GPIO_B8_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_B8_OUT_PP + bool "push pull" + +endchoice # B8 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_B8_OUT_SET + +config STM32F411MINIMUM_GPIO_B8_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_B8_OUT_CLEAR + bool "clear" + +endchoice # B8 output default state + +endif # STM32F411MINIMUM_GPIO_B8_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_B8_PULL_UP + +config STM32F411MINIMUM_GPIO_B8_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_B8_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_B8_PULL_FLOAT + bool "float" + +endchoice # B8 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_B8_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_B8_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_B8_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_B8_SPEED_50MHz + bool "50MHz" + +endchoice # B8 speed + +endif # STM32F411MINIMUM_GPIO_B8 + +config STM32F411MINIMUM_GPIO_B9 + bool "enable pin B9" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_B9 device node. + +if STM32F411MINIMUM_GPIO_B9 + +config STM32F411MINIMUM_GPIO_B9_NAME + string "Pin name" + default "gpio_b9" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_B9_OUT + +config STM32F411MINIMUM_GPIO_B9_OUT + bool "output" +config STM32F411MINIMUM_GPIO_B9_IN + bool "input" +config STM32F411MINIMUM_GPIO_B9_INT + bool "interrupt" + +endchoice # B9 Pin type + +if STM32F411MINIMUM_GPIO_B9_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_B9_OUT_OD + +config STM32F411MINIMUM_GPIO_B9_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_B9_OUT_PP + bool "push pull" + +endchoice # B9 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_B9_OUT_SET + +config STM32F411MINIMUM_GPIO_B9_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_B9_OUT_CLEAR + bool "clear" + +endchoice # B9 output default state + +endif # STM32F411MINIMUM_GPIO_B9_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_B9_PULL_UP + +config STM32F411MINIMUM_GPIO_B9_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_B9_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_B9_PULL_FLOAT + bool "float" + +endchoice # B9 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_B9_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_B9_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_B9_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_B9_SPEED_50MHz + bool "50MHz" + +endchoice # B9 speed + +endif # STM32F411MINIMUM_GPIO_B9 + +config STM32F411MINIMUM_GPIO_B10 + bool "enable pin B10" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_B10 device node. + +if STM32F411MINIMUM_GPIO_B10 + +config STM32F411MINIMUM_GPIO_B10_NAME + string "Pin name" + default "gpio_b10" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_B10_OUT + +config STM32F411MINIMUM_GPIO_B10_OUT + bool "output" +config STM32F411MINIMUM_GPIO_B10_IN + bool "input" +config STM32F411MINIMUM_GPIO_B10_INT + bool "interrupt" + +endchoice # B10 Pin type + +if STM32F411MINIMUM_GPIO_B10_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_B10_OUT_OD + +config STM32F411MINIMUM_GPIO_B10_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_B10_OUT_PP + bool "push pull" + +endchoice # B10 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_B10_OUT_SET + +config STM32F411MINIMUM_GPIO_B10_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_B10_OUT_CLEAR + bool "clear" + +endchoice # B10 output default state + +endif # STM32F411MINIMUM_GPIO_B10_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_B10_PULL_UP + +config STM32F411MINIMUM_GPIO_B10_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_B10_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_B10_PULL_FLOAT + bool "float" + +endchoice # B10 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_B10_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_B10_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_B10_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_B10_SPEED_50MHz + bool "50MHz" + +endchoice # B10 speed + +endif # STM32F411MINIMUM_GPIO_B10 + +config STM32F411MINIMUM_GPIO_B12 + bool "enable pin B12" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_B12 device node. + +if STM32F411MINIMUM_GPIO_B12 + +config STM32F411MINIMUM_GPIO_B12_NAME + string "Pin name" + default "gpio_b12" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_B12_OUT + +config STM32F411MINIMUM_GPIO_B12_OUT + bool "output" +config STM32F411MINIMUM_GPIO_B12_IN + bool "input" +config STM32F411MINIMUM_GPIO_B12_INT + bool "interrupt" + +endchoice # B12 Pin type + +if STM32F411MINIMUM_GPIO_B12_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_B12_OUT_OD + +config STM32F411MINIMUM_GPIO_B12_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_B12_OUT_PP + bool "push pull" + +endchoice # B12 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_B12_OUT_SET + +config STM32F411MINIMUM_GPIO_B12_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_B12_OUT_CLEAR + bool "clear" + +endchoice # B12 output default state + +endif # STM32F411MINIMUM_GPIO_B12_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_B12_PULL_UP + +config STM32F411MINIMUM_GPIO_B12_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_B12_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_B12_PULL_FLOAT + bool "float" + +endchoice # B12 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_B12_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_B12_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_B12_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_B12_SPEED_50MHz + bool "50MHz" + +endchoice # B12 speed + +endif # STM32F411MINIMUM_GPIO_B12 + +config STM32F411MINIMUM_GPIO_B13 + bool "enable pin B13" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_B13 device node. + +if STM32F411MINIMUM_GPIO_B13 + +config STM32F411MINIMUM_GPIO_B13_NAME + string "Pin name" + default "gpio_b13" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_B13_OUT + +config STM32F411MINIMUM_GPIO_B13_OUT + bool "output" +config STM32F411MINIMUM_GPIO_B13_IN + bool "input" +config STM32F411MINIMUM_GPIO_B13_INT + bool "interrupt" + +endchoice # B13 Pin type + +if STM32F411MINIMUM_GPIO_B13_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_B13_OUT_OD + +config STM32F411MINIMUM_GPIO_B13_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_B13_OUT_PP + bool "push pull" + +endchoice # B13 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_B13_OUT_SET + +config STM32F411MINIMUM_GPIO_B13_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_B13_OUT_CLEAR + bool "clear" + +endchoice # B13 output default state + +endif # STM32F411MINIMUM_GPIO_B13_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_B13_PULL_UP + +config STM32F411MINIMUM_GPIO_B13_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_B13_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_B13_PULL_FLOAT + bool "float" + +endchoice # B13 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_B13_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_B13_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_B13_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_B13_SPEED_50MHz + bool "50MHz" + +endchoice # B13 speed + +endif # STM32F411MINIMUM_GPIO_B13 + +config STM32F411MINIMUM_GPIO_B14 + bool "enable pin B14" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_B14 device node. + +if STM32F411MINIMUM_GPIO_B14 + +config STM32F411MINIMUM_GPIO_B14_NAME + string "Pin name" + default "gpio_b14" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_B14_OUT + +config STM32F411MINIMUM_GPIO_B14_OUT + bool "output" +config STM32F411MINIMUM_GPIO_B14_IN + bool "input" +config STM32F411MINIMUM_GPIO_B14_INT + bool "interrupt" + +endchoice # B14 Pin type + +if STM32F411MINIMUM_GPIO_B14_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_B14_OUT_OD + +config STM32F411MINIMUM_GPIO_B14_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_B14_OUT_PP + bool "push pull" + +endchoice # B14 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_B14_OUT_SET + +config STM32F411MINIMUM_GPIO_B14_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_B14_OUT_CLEAR + bool "clear" + +endchoice # B14 output default state + +endif # STM32F411MINIMUM_GPIO_B14_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_B14_PULL_UP + +config STM32F411MINIMUM_GPIO_B14_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_B14_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_B14_PULL_FLOAT + bool "float" + +endchoice # B14 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_B14_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_B14_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_B14_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_B14_SPEED_50MHz + bool "50MHz" + +endchoice # B14 speed + +endif # STM32F411MINIMUM_GPIO_B14 + +config STM32F411MINIMUM_GPIO_B15 + bool "enable pin B15" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_B15 device node. + +if STM32F411MINIMUM_GPIO_B15 + +config STM32F411MINIMUM_GPIO_B15_NAME + string "Pin name" + default "gpio_b15" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_B15_OUT + +config STM32F411MINIMUM_GPIO_B15_OUT + bool "output" +config STM32F411MINIMUM_GPIO_B15_IN + bool "input" +config STM32F411MINIMUM_GPIO_B15_INT + bool "interrupt" + +endchoice # B15 Pin type + +if STM32F411MINIMUM_GPIO_B15_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_B15_OUT_OD + +config STM32F411MINIMUM_GPIO_B15_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_B15_OUT_PP + bool "push pull" + +endchoice # B15 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_B15_OUT_SET + +config STM32F411MINIMUM_GPIO_B15_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_B15_OUT_CLEAR + bool "clear" + +endchoice # B15 output default state + +endif # STM32F411MINIMUM_GPIO_B15_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_B15_PULL_UP + +config STM32F411MINIMUM_GPIO_B15_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_B15_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_B15_PULL_FLOAT + bool "float" + +endchoice # B15 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_B15_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_B15_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_B15_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_B15_SPEED_50MHz + bool "50MHz" + +endchoice # B15 speed + +endif # STM32F411MINIMUM_GPIO_B15 + +config STM32F411MINIMUM_GPIO_C13 + bool "enable pin C13" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_C13 device node. + +if STM32F411MINIMUM_GPIO_C13 + +config STM32F411MINIMUM_GPIO_C13_NAME + string "Pin name" + default "gpio_c13" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_C13_OUT + +config STM32F411MINIMUM_GPIO_C13_OUT + bool "output" +config STM32F411MINIMUM_GPIO_C13_IN + bool "input" +config STM32F411MINIMUM_GPIO_C13_INT + bool "interrupt" + +endchoice # C13 Pin type + +if STM32F411MINIMUM_GPIO_C13_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_C13_OUT_OD + +config STM32F411MINIMUM_GPIO_C13_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_C13_OUT_PP + bool "push pull" + +endchoice # C13 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_C13_OUT_SET + +config STM32F411MINIMUM_GPIO_C13_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_C13_OUT_CLEAR + bool "clear" + +endchoice # C13 output default state + +endif # STM32F411MINIMUM_GPIO_C13_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_C13_PULL_UP + +config STM32F411MINIMUM_GPIO_C13_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_C13_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_C13_PULL_FLOAT + bool "float" + +endchoice # C13 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_C13_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_C13_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_C13_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_C13_SPEED_50MHz + bool "50MHz" + +endchoice # C13 speed + +endif # STM32F411MINIMUM_GPIO_C13 + +config STM32F411MINIMUM_GPIO_C14 + bool "enable pin C14" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_C14 device node. + +if STM32F411MINIMUM_GPIO_C14 + +config STM32F411MINIMUM_GPIO_C14_NAME + string "Pin name" + default "gpio_c14" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_C14_OUT + +config STM32F411MINIMUM_GPIO_C14_OUT + bool "output" +config STM32F411MINIMUM_GPIO_C14_IN + bool "input" +config STM32F411MINIMUM_GPIO_C14_INT + bool "interrupt" + +endchoice # C14 Pin type + +if STM32F411MINIMUM_GPIO_C14_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_C14_OUT_OD + +config STM32F411MINIMUM_GPIO_C14_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_C14_OUT_PP + bool "push pull" + +endchoice # C14 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_C14_OUT_SET + +config STM32F411MINIMUM_GPIO_C14_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_C14_OUT_CLEAR + bool "clear" + +endchoice # C14 output default state + +endif # STM32F411MINIMUM_GPIO_C14_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_C14_PULL_UP + +config STM32F411MINIMUM_GPIO_C14_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_C14_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_C14_PULL_FLOAT + bool "float" + +endchoice # C14 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_C14_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_C14_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_C14_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_C14_SPEED_50MHz + bool "50MHz" + +endchoice # C14 speed + +endif # STM32F411MINIMUM_GPIO_C14 + +config STM32F411MINIMUM_GPIO_C15 + bool "enable pin C15" + ---help--- + Assume direct control over this pin. You will not be able to use this + pin for anything else other than general input/output access via + /dev/gpio_C15 device node. + +if STM32F411MINIMUM_GPIO_C15 + +config STM32F411MINIMUM_GPIO_C15_NAME + string "Pin name" + default "gpio_c15" + ---help--- + Pin name, it will accessible via /dev/%s file + +choice + prompt "Pin type" + default STM32F411MINIMUM_GPIO_C15_OUT + +config STM32F411MINIMUM_GPIO_C15_OUT + bool "output" +config STM32F411MINIMUM_GPIO_C15_IN + bool "input" +config STM32F411MINIMUM_GPIO_C15_INT + bool "interrupt" + +endchoice # C15 Pin type + +if STM32F411MINIMUM_GPIO_C15_OUT + +choice + prompt "output type" + default STM32F411MINIMUM_GPIO_C15_OUT_OD + +config STM32F411MINIMUM_GPIO_C15_OUT_OD + bool "open drain" +config STM32F411MINIMUM_GPIO_C15_OUT_PP + bool "push pull" + +endchoice # C15 output type + +choice + prompt "default state" + default STM32F411MINIMUM_GPIO_C15_OUT_SET + +config STM32F411MINIMUM_GPIO_C15_OUT_SET + bool "set" +config STM32F411MINIMUM_GPIO_C15_OUT_CLEAR + bool "clear" + +endchoice # C15 output default state + +endif # STM32F411MINIMUM_GPIO_C15_OUT + +choice + prompt "pull" + default STM32F411MINIMUM_GPIO_C15_PULL_UP + +config STM32F411MINIMUM_GPIO_C15_PULL_UP + bool "pull up" +config STM32F411MINIMUM_GPIO_C15_PULL_DOWN + bool "pull down" +config STM32F411MINIMUM_GPIO_C15_PULL_FLOAT + bool "float" + +endchoice # C15 pull + +choice + prompt "speed" + default STM32F411MINIMUM_GPIO_C15_SPEED_2MHz + +config STM32F411MINIMUM_GPIO_C15_SPEED_2MHz + bool "2MHz" +config STM32F411MINIMUM_GPIO_C15_SPEED_25MHz + bool "25MHz" +config STM32F411MINIMUM_GPIO_C15_SPEED_50MHz + bool "50MHz" + +endchoice # C15 speed + +endif # STM32F411MINIMUM_GPIO_C15 diff --git a/boards/arm/stm32/stm32f411-minimum/src/CMakeLists.txt b/boards/arm/stm32/stm32f411-minimum/src/CMakeLists.txt index c13bf9cf978a6..6dd6b45ddd0d1 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/CMakeLists.txt +++ b/boards/arm/stm32/stm32f411-minimum/src/CMakeLists.txt @@ -44,10 +44,18 @@ if(CONFIG_USBDEV_COMPOSITE) list(APPEND SRCS stm32_composite.c) endif() +if(CONFIG_STM32F411MINIMUM_GPIO) + list(APPEND SRCS stm32_gpio.c) +endif() + if(CONFIG_USBMSC) list(APPEND SRCS stm32_usbmsc.c) endif() +if(CONFIG_ADC_HX711) + list(APPEND SRCS stm32_hx711.c) +endif() + target_sources(board PRIVATE ${SRCS}) set_property(GLOBAL PROPERTY LD_SCRIPT diff --git a/boards/arm/stm32/stm32f411-minimum/src/Make.defs b/boards/arm/stm32/stm32f411-minimum/src/Make.defs index c3e8906ad613c..c95bd962787b8 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/Make.defs +++ b/boards/arm/stm32/stm32f411-minimum/src/Make.defs @@ -30,10 +30,18 @@ ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += stm32_autoleds.c endif +ifeq ($(CONFIG_ADC_HX711),y) + CSRCS += stm32_hx711.c +endif + ifeq ($(CONFIG_SPI),y) CSRCS += stm32_spi.c endif +ifeq ($(CONFIG_STM32F411MINIMUM_GPIO),y) + CSRCS += stm32_gpio.c +endif + ifeq ($(CONFIG_MTD_W25),y) CSRCS += stm32_w25.c endif diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_bringup.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_bringup.c index 320f4c4153c98..3acbb2187c998 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32_bringup.c +++ b/boards/arm/stm32/stm32f411-minimum/src/stm32_bringup.c @@ -84,6 +84,22 @@ int stm32_bringup(void) { int ret = OK; +#ifdef CONFIG_STM32F411MINIMUM_GPIO + ret = stm32_gpio_initialize(); + if (ret != OK) + { + gerr("ERROR: Failed to initialize gpio: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC_HX711 + ret = stm32_hx711_initialize(); + if (ret != OK) + { + aerr("ERROR: Failed to initialize hx711: %d\n", ret); + } +#endif + #if defined(CONFIG_STM32_OTGFS) && defined(CONFIG_USBHOST) /* Initialize USB host operation. stm32_usbhost_initialize() starts a * thread will monitor for USB connection and disconnection events. diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_gpio.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_gpio.c new file mode 100644 index 0000000000000..b62eff079b30b --- /dev/null +++ b/boards/arm/stm32/stm32f411-minimum/src/stm32_gpio.c @@ -0,0 +1,739 @@ +/**************************************************************************** + * boards/arm/stm32/stm32f411-minimum/src/stm32_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32.h" +#include "stm32f411-minimum.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct stm32gpint_dev_s +{ + struct stm32gpio_dev_s stm32gpio; + pin_interrupt_t callback; +}; + +struct stm32gpio_info_s +{ + uint32_t pin; + const char *pinname; /* Holds pin name like gpio_a0, gpio_custom_name */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIO_IN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value); +#endif + +#if BOARD_NGPIO_OUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +#endif + +#if BOARD_NGPIO_INT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); +static int gpint_attach(struct gpio_dev_s *dev, pin_interrupt_t callback); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if BOARD_NGPIO_IN > 0 +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; + +static struct stm32gpio_dev_s g_gpin[BOARD_NGPIO_IN]; +static const struct stm32gpio_info_s g_gpio_inputs[BOARD_NGPIO_IN] = +{ +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A0_IN + { .pin = GPIO_A0_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A0_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A1_IN + { .pin = GPIO_A1_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A1_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A2_IN + { .pin = GPIO_A2_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A2_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A3_IN + { .pin = GPIO_A3_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A3_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A4_IN + { .pin = GPIO_A4_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A4_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A5_IN + { .pin = GPIO_A5_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A5_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A6_IN + { .pin = GPIO_A6_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A6_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A7_IN + { .pin = GPIO_A7_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A7_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A8_IN + { .pin = GPIO_A8_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A8_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A9_IN + { .pin = GPIO_A9_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A9_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A10_IN + { .pin = GPIO_A10_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A10_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A11_IN + { .pin = GPIO_A11_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A11_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A12_IN + { .pin = GPIO_A12_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A12_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A15_IN + { .pin = GPIO_A15_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A15_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B0_IN + { .pin = GPIO_B0_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B0_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B1_IN + { .pin = GPIO_B1_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B1_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B2_IN + { .pin = GPIO_B2_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B2_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B3_IN + { .pin = GPIO_B3_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B3_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B4_IN + { .pin = GPIO_B4_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B4_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B5_IN + { .pin = GPIO_B5_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B5_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B6_IN + { .pin = GPIO_B6_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B6_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B7_IN + { .pin = GPIO_B7_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B7_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B8_IN + { .pin = GPIO_B8_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B8_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B9_IN + { .pin = GPIO_B9_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B9_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B10_IN + { .pin = GPIO_B10_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B10_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B12_IN + { .pin = GPIO_B12_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B12_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B13_IN + { .pin = GPIO_B13_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B13_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B14_IN + { .pin = GPIO_B14_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B14_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B15_IN + { .pin = GPIO_B15_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B15_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C13_IN + { .pin = GPIO_C13_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C13_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C14_IN + { .pin = GPIO_C14_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C14_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C15_IN + { .pin = GPIO_C15_IN, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C15_NAME }, +#endif +}; +#endif /* BOARD_NGPIO_IN > 0 */ + +#if BOARD_NGPIO_OUT > 0 +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; + +static struct stm32gpio_dev_s g_gpout[BOARD_NGPIO_OUT]; +static const struct stm32gpio_info_s g_gpio_outputs[BOARD_NGPIO_OUT] = +{ +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A0_OUT + { .pin = GPIO_A0_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A0_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A1_OUT + { .pin = GPIO_A1_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A1_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A2_OUT + { .pin = GPIO_A2_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A2_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A3_OUT + { .pin = GPIO_A3_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A3_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A4_OUT + { .pin = GPIO_A4_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A4_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A5_OUT + { .pin = GPIO_A5_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A5_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A6_OUT + { .pin = GPIO_A6_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A6_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A7_OUT + { .pin = GPIO_A7_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A7_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A8_OUT + { .pin = GPIO_A8_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A8_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A9_OUT + { .pin = GPIO_A9_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A9_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A10_OUT + { .pin = GPIO_A10_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A10_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A11_OUT + { .pin = GPIO_A11_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A11_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A12_OUT + { .pin = GPIO_A12_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A12_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A15_OUT + { .pin = GPIO_A15_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A15_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B0_OUT + { .pin = GPIO_B0_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B0_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B1_OUT + { .pin = GPIO_B1_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B1_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B2_OUT + { .pin = GPIO_B2_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B2_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B3_OUT + { .pin = GPIO_B3_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B3_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B4_OUT + { .pin = GPIO_B4_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B4_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B5_OUT + { .pin = GPIO_B5_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B5_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B6_OUT + { .pin = GPIO_B6_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B6_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B7_OUT + { .pin = GPIO_B7_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B7_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B8_OUT + { .pin = GPIO_B8_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B8_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B9_OUT + { .pin = GPIO_B9_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B9_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B10_OUT + { .pin = GPIO_B10_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B10_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B12_OUT + { .pin = GPIO_B12_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B12_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B13_OUT + { .pin = GPIO_B13_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B13_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B14_OUT + { .pin = GPIO_B14_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B14_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B15_OUT + { .pin = GPIO_B15_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B15_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C13_OUT + { .pin = GPIO_C13_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C13_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C14_OUT + { .pin = GPIO_C14_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C14_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C15_OUT + { .pin = GPIO_C15_OUT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C15_NAME }, +#endif +}; +#endif /* BOARD_NGPIO_OUT > 0 */ + +#if BOARD_NGPIO_INT > 0 +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; + +static struct stm32gpint_dev_s g_gpint[BOARD_NGPIO_INT]; +static const struct stm32gpio_info_s g_gpio_int_inputs[BOARD_NGPIO_INT] = +{ +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A0_INT + { .pin = GPIO_A0_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A0_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A1_INT + { .pin = GPIO_A1_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A1_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A2_INT + { .pin = GPIO_A2_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A2_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A3_INT + { .pin = GPIO_A3_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A3_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A4_INT + { .pin = GPIO_A4_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A4_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A5_INT + { .pin = GPIO_A5_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A5_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A6_INT + { .pin = GPIO_A6_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A6_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A7_INT + { .pin = GPIO_A7_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A7_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A8_INT + { .pin = GPIO_A8_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A8_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A9_INT + { .pin = GPIO_A9_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A9_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A10_INT + { .pin = GPIO_A10_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A10_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A11_INT + { .pin = GPIO_A11_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A11_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A12_INT + { .pin = GPIO_A12_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A12_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_A15_INT + { .pin = GPIO_A15_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_A15_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B0_INT + { .pin = GPIO_B0_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B0_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B1_INT + { .pin = GPIO_B1_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B1_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B2_INT + { .pin = GPIO_B2_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B2_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B3_INT + { .pin = GPIO_B3_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B3_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B4_INT + { .pin = GPIO_B4_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B4_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B5_INT + { .pin = GPIO_B5_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B5_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B6_INT + { .pin = GPIO_B6_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B6_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B7_INT + { .pin = GPIO_B7_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B7_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B8_INT + { .pin = GPIO_B8_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B8_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B9_INT + { .pin = GPIO_B9_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B9_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B10_INT + { .pin = GPIO_B10_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B10_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B12_INT + { .pin = GPIO_B12_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B12_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B13_INT + { .pin = GPIO_B13_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B13_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B14_INT + { .pin = GPIO_B14_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B14_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_B15_INT + { .pin = GPIO_B15_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_B15_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C13_INT + { .pin = GPIO_C13_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C13_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C14_INT + { .pin = GPIO_C14_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C14_NAME }, +#endif + +#ifdef CONFIG_STM32F411MINIMUM_GPIO_C15_INT + { .pin = GPIO_C15_INT, .pinname = CONFIG_STM32F411MINIMUM_GPIO_C15_NAME }, +#endif +}; +#endif /* BOARD_NGPIO_INT > 0 */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpin_read + ****************************************************************************/ + +#if BOARD_NGPIO_IN > 0 +static int gpin_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIO_IN); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpio_inputs[stm32gpio->id].pin); + return OK; +} +#endif + +/**************************************************************************** + * Name: gpout_read + ****************************************************************************/ + +#if BOARD_NGPIO_OUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIO_OUT); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpio_outputs[stm32gpio->id].pin); + return OK; +} +#endif + +/**************************************************************************** + * Name: gpout_write + ****************************************************************************/ + +#if BOARD_NGPIO_OUT > 0 +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIO_OUT); + gpioinfo("Writing %d\n", (int)value); + + stm32_gpiowrite(g_gpio_outputs[stm32gpio->id].pin, value); + return OK; +} +#endif + +/**************************************************************************** + * Name: gpint_read + ****************************************************************************/ + +#if BOARD_NGPIO_INT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + DEBUGASSERT(stm32gpint != NULL && value != NULL); + DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIO_INT); + gpioinfo("Reading int pin...\n"); + + *value = stm32_gpioread(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin); + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32gpio_interrupt + ****************************************************************************/ + +#if BOARD_NGPIO_INT > 0 +static int stm32gpio_interrupt(int irq, void *context, void *arg) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)arg; + + DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); + + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); + return OK; +} +#endif + +/**************************************************************************** + * Name: gpint_attach + ****************************************************************************/ + +#if BOARD_NGPIO_INT > 0 +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + stm32_gpiosetevent(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin, false, + false, false, NULL, NULL); + + gpioinfo("Attach %p\n", callback); + stm32gpint->callback = callback; + return OK; +} +#endif + +/**************************************************************************** + * Name: gpint_enable + ****************************************************************************/ + +#if BOARD_NGPIO_INT > 0 +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + if (enable) + { + if (stm32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + stm32_gpiosetevent(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin, + true, false, false, stm32gpio_interrupt, + &g_gpint[stm32gpint->stm32gpio.id]); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + stm32_gpiosetevent(g_gpio_int_inputs[stm32gpint->stm32gpio.id].pin, + false, false, false, NULL, NULL); + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers + * + ****************************************************************************/ + +int stm32_gpio_initialize(void) +{ + int i; + +#if BOARD_NGPIO_IN > 0 + for (i = 0; i < BOARD_NGPIO_IN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register_byname(&g_gpin[i].gpio, g_gpio_inputs[i].pinname); + + /* Configure the pin that will be used as input */ + + stm32_configgpio(g_gpio_inputs[i].pin); + } +#endif + +#if BOARD_NGPIO_OUT > 0 + for (i = 0; i < BOARD_NGPIO_OUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register_byname(&g_gpout[i].gpio, g_gpio_outputs[i].pinname); + + /* Configure the pin that will be used as output */ + + stm32_gpiowrite(g_gpio_outputs[i].pin, 0); + stm32_configgpio(g_gpio_outputs[i].pin); + } +#endif + +#if BOARD_NGPIO_INT > 0 + for (i = 0; i < BOARD_NGPIO_INT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].stm32gpio.id = i; + gpio_pin_register_byname(&g_gpint[i].stm32gpio.gpio, + g_gpio_int_inputs[i].pinname); + + /* Configure the pin that will be used as interrupt input */ + + stm32_configgpio(g_gpio_int_inputs[i].pin); + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32_hx711.c b/boards/arm/stm32/stm32f411-minimum/src/stm32_hx711.c new file mode 100644 index 0000000000000..8a1ba2b699df6 --- /dev/null +++ b/boards/arm/stm32/stm32f411-minimum/src/stm32_hx711.c @@ -0,0 +1,102 @@ +/**************************************************************************** + * boards/arm/stm32/stm32f411-minimum/src/stm32_hx711.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32f411-minimum.h" + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int stm32_hx711_clock_set(unsigned char minor, int value); +static int stm32_hx711_data_read(unsigned char minor); +static int stm32_hx711_data_irq(unsigned char minor, + xcpt_t handler, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +struct hx711_lower_s g_lower = +{ + .data_read = stm32_hx711_data_read, + .clock_set = stm32_hx711_clock_set, + .data_irq = stm32_hx711_data_irq, + .cleanup = NULL +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int stm32_hx711_clock_set(unsigned char minor, int value) +{ + UNUSED(minor); + + stm32_gpiowrite(HX711_CLK_PIN, value); + return OK; +} + +static int stm32_hx711_data_read(unsigned char minor) +{ + UNUSED(minor); + + return stm32_gpioread(HX711_DATA_PIN); +} + +static int stm32_hx711_data_irq(unsigned char minor, + xcpt_t handler, void *arg) +{ + UNUSED(minor); + + return stm32_gpiosetevent(HX711_DATA_PIN, false, true, true, handler, arg); +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int stm32_hx711_initialize(void) +{ + int ret; + + stm32_configgpio(HX711_DATA_PIN); + stm32_configgpio(HX711_CLK_PIN); + + ret = hx711_register(0, &g_lower); + if (ret != 0) + { + aerr("ERROR: Failed to register hx711 device: %d\n", ret); + return -1; + } + + return OK; +} diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum-gpio.h b/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum-gpio.h new file mode 100644 index 0000000000000..6b1d5689f410a --- /dev/null +++ b/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum-gpio.h @@ -0,0 +1,1922 @@ +/**************************************************************************** + * boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum-gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32_STM32F411_MINIMUM_SRC_STM32F411_MINIMUM_GPIO_H +#define __BOARDS_ARM_STM32_STM32F411_MINIMUM_SRC_STM32F411_MINIMUM_GPIO_H + +/* GPIO A0 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A0_OUT) +# define GPIO_A0_USED_OUT 1 +# define GPIO_A0_USED_INT 0 +# define GPIO_A0_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A0_INT) +# define GPIO_A0_USED_OUT 0 +# define GPIO_A0_USED_INT 1 +# define GPIO_A0_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A0_IN) +# define GPIO_A0_USED_OUT 0 +# define GPIO_A0_USED_INT 0 +# define GPIO_A0_USED_IN 1 +#else +# define GPIO_A0_USED_OUT 0 +# define GPIO_A0_USED_INT 0 +# define GPIO_A0_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A0_OUT_PP) +# define GPIO_A0_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_A0_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A0_OUT_CLEAR) +# define GPIO_A0_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_A0_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A0_PULL_DOWN) +# define GPIO_A0_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A0_PULL_FLOAT) +# define GPIO_A0_PULL GPIO_FLOAT +#else +# define GPIO_A0_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A0_SPEED_2MHz) +# define GPIO_A0_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A0_SPEED_25MHz) +# define GPIO_A0_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_A0_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO A1 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A1_OUT) +# define GPIO_A1_USED_OUT 1 +# define GPIO_A1_USED_INT 0 +# define GPIO_A1_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A1_INT) +# define GPIO_A1_USED_OUT 0 +# define GPIO_A1_USED_INT 1 +# define GPIO_A1_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A1_IN) +# define GPIO_A1_USED_OUT 0 +# define GPIO_A1_USED_INT 0 +# define GPIO_A1_USED_IN 1 +#else +# define GPIO_A1_USED_OUT 0 +# define GPIO_A1_USED_INT 0 +# define GPIO_A1_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A1_OUT_PP) +# define GPIO_A1_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_A1_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A1_OUT_CLEAR) +# define GPIO_A1_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_A1_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A1_PULL_DOWN) +# define GPIO_A1_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A1_PULL_FLOAT) +# define GPIO_A1_PULL GPIO_FLOAT +#else +# define GPIO_A1_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A1_SPEED_2MHz) +# define GPIO_A1_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A1_SPEED_25MHz) +# define GPIO_A1_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_A1_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO A2 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A2_OUT) +# define GPIO_A2_USED_OUT 1 +# define GPIO_A2_USED_INT 0 +# define GPIO_A2_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A2_INT) +# define GPIO_A2_USED_OUT 0 +# define GPIO_A2_USED_INT 1 +# define GPIO_A2_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A2_IN) +# define GPIO_A2_USED_OUT 0 +# define GPIO_A2_USED_INT 0 +# define GPIO_A2_USED_IN 1 +#else +# define GPIO_A2_USED_OUT 0 +# define GPIO_A2_USED_INT 0 +# define GPIO_A2_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A2_OUT_PP) +# define GPIO_A2_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_A2_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A2_OUT_CLEAR) +# define GPIO_A2_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_A2_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A2_PULL_DOWN) +# define GPIO_A2_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A2_PULL_FLOAT) +# define GPIO_A2_PULL GPIO_FLOAT +#else +# define GPIO_A2_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A2_SPEED_2MHz) +# define GPIO_A2_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A2_SPEED_25MHz) +# define GPIO_A2_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_A2_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO A3 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A3_OUT) +# define GPIO_A3_USED_OUT 1 +# define GPIO_A3_USED_INT 0 +# define GPIO_A3_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A3_INT) +# define GPIO_A3_USED_OUT 0 +# define GPIO_A3_USED_INT 1 +# define GPIO_A3_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A3_IN) +# define GPIO_A3_USED_OUT 0 +# define GPIO_A3_USED_INT 0 +# define GPIO_A3_USED_IN 1 +#else +# define GPIO_A3_USED_OUT 0 +# define GPIO_A3_USED_INT 0 +# define GPIO_A3_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A3_OUT_PP) +# define GPIO_A3_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_A3_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A3_OUT_CLEAR) +# define GPIO_A3_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_A3_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A3_PULL_DOWN) +# define GPIO_A3_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A3_PULL_FLOAT) +# define GPIO_A3_PULL GPIO_FLOAT +#else +# define GPIO_A3_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A3_SPEED_2MHz) +# define GPIO_A3_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A3_SPEED_25MHz) +# define GPIO_A3_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_A3_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO A4 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A4_OUT) +# define GPIO_A4_USED_OUT 1 +# define GPIO_A4_USED_INT 0 +# define GPIO_A4_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A4_INT) +# define GPIO_A4_USED_OUT 0 +# define GPIO_A4_USED_INT 1 +# define GPIO_A4_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A4_IN) +# define GPIO_A4_USED_OUT 0 +# define GPIO_A4_USED_INT 0 +# define GPIO_A4_USED_IN 1 +#else +# define GPIO_A4_USED_OUT 0 +# define GPIO_A4_USED_INT 0 +# define GPIO_A4_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A4_OUT_PP) +# define GPIO_A4_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_A4_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A4_OUT_CLEAR) +# define GPIO_A4_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_A4_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A4_PULL_DOWN) +# define GPIO_A4_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A4_PULL_FLOAT) +# define GPIO_A4_PULL GPIO_FLOAT +#else +# define GPIO_A4_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A4_SPEED_2MHz) +# define GPIO_A4_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A4_SPEED_25MHz) +# define GPIO_A4_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_A4_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO A5 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A5_OUT) +# define GPIO_A5_USED_OUT 1 +# define GPIO_A5_USED_INT 0 +# define GPIO_A5_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A5_INT) +# define GPIO_A5_USED_OUT 0 +# define GPIO_A5_USED_INT 1 +# define GPIO_A5_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A5_IN) +# define GPIO_A5_USED_OUT 0 +# define GPIO_A5_USED_INT 0 +# define GPIO_A5_USED_IN 1 +#else +# define GPIO_A5_USED_OUT 0 +# define GPIO_A5_USED_INT 0 +# define GPIO_A5_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A5_OUT_PP) +# define GPIO_A5_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_A5_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A5_OUT_CLEAR) +# define GPIO_A5_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_A5_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A5_PULL_DOWN) +# define GPIO_A5_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A5_PULL_FLOAT) +# define GPIO_A5_PULL GPIO_FLOAT +#else +# define GPIO_A5_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A5_SPEED_2MHz) +# define GPIO_A5_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A5_SPEED_25MHz) +# define GPIO_A5_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_A5_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO A6 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A6_OUT) +# define GPIO_A6_USED_OUT 1 +# define GPIO_A6_USED_INT 0 +# define GPIO_A6_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A6_INT) +# define GPIO_A6_USED_OUT 0 +# define GPIO_A6_USED_INT 1 +# define GPIO_A6_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A6_IN) +# define GPIO_A6_USED_OUT 0 +# define GPIO_A6_USED_INT 0 +# define GPIO_A6_USED_IN 1 +#else +# define GPIO_A6_USED_OUT 0 +# define GPIO_A6_USED_INT 0 +# define GPIO_A6_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A6_OUT_PP) +# define GPIO_A6_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_A6_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A6_OUT_CLEAR) +# define GPIO_A6_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_A6_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A6_PULL_DOWN) +# define GPIO_A6_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A6_PULL_FLOAT) +# define GPIO_A6_PULL GPIO_FLOAT +#else +# define GPIO_A6_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A6_SPEED_2MHz) +# define GPIO_A6_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A6_SPEED_25MHz) +# define GPIO_A6_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_A6_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO A7 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A7_OUT) +# define GPIO_A7_USED_OUT 1 +# define GPIO_A7_USED_INT 0 +# define GPIO_A7_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A7_INT) +# define GPIO_A7_USED_OUT 0 +# define GPIO_A7_USED_INT 1 +# define GPIO_A7_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A7_IN) +# define GPIO_A7_USED_OUT 0 +# define GPIO_A7_USED_INT 0 +# define GPIO_A7_USED_IN 1 +#else +# define GPIO_A7_USED_OUT 0 +# define GPIO_A7_USED_INT 0 +# define GPIO_A7_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A7_OUT_PP) +# define GPIO_A7_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_A7_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A7_OUT_CLEAR) +# define GPIO_A7_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_A7_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A7_PULL_DOWN) +# define GPIO_A7_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A7_PULL_FLOAT) +# define GPIO_A7_PULL GPIO_FLOAT +#else +# define GPIO_A7_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A7_SPEED_2MHz) +# define GPIO_A7_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A7_SPEED_25MHz) +# define GPIO_A7_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_A7_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO A8 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A8_OUT) +# define GPIO_A8_USED_OUT 1 +# define GPIO_A8_USED_INT 0 +# define GPIO_A8_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A8_INT) +# define GPIO_A8_USED_OUT 0 +# define GPIO_A8_USED_INT 1 +# define GPIO_A8_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A8_IN) +# define GPIO_A8_USED_OUT 0 +# define GPIO_A8_USED_INT 0 +# define GPIO_A8_USED_IN 1 +#else +# define GPIO_A8_USED_OUT 0 +# define GPIO_A8_USED_INT 0 +# define GPIO_A8_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A8_OUT_PP) +# define GPIO_A8_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_A8_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A8_OUT_CLEAR) +# define GPIO_A8_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_A8_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A8_PULL_DOWN) +# define GPIO_A8_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A8_PULL_FLOAT) +# define GPIO_A8_PULL GPIO_FLOAT +#else +# define GPIO_A8_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A8_SPEED_2MHz) +# define GPIO_A8_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A8_SPEED_25MHz) +# define GPIO_A8_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_A8_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO A9 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A9_OUT) +# define GPIO_A9_USED_OUT 1 +# define GPIO_A9_USED_INT 0 +# define GPIO_A9_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A9_INT) +# define GPIO_A9_USED_OUT 0 +# define GPIO_A9_USED_INT 1 +# define GPIO_A9_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A9_IN) +# define GPIO_A9_USED_OUT 0 +# define GPIO_A9_USED_INT 0 +# define GPIO_A9_USED_IN 1 +#else +# define GPIO_A9_USED_OUT 0 +# define GPIO_A9_USED_INT 0 +# define GPIO_A9_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A9_OUT_PP) +# define GPIO_A9_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_A9_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A9_OUT_CLEAR) +# define GPIO_A9_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_A9_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A9_PULL_DOWN) +# define GPIO_A9_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A9_PULL_FLOAT) +# define GPIO_A9_PULL GPIO_FLOAT +#else +# define GPIO_A9_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A9_SPEED_2MHz) +# define GPIO_A9_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A9_SPEED_25MHz) +# define GPIO_A9_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_A9_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO A10 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A10_OUT) +# define GPIO_A10_USED_OUT 1 +# define GPIO_A10_USED_INT 0 +# define GPIO_A10_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A10_INT) +# define GPIO_A10_USED_OUT 0 +# define GPIO_A10_USED_INT 1 +# define GPIO_A10_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A10_IN) +# define GPIO_A10_USED_OUT 0 +# define GPIO_A10_USED_INT 0 +# define GPIO_A10_USED_IN 1 +#else +# define GPIO_A10_USED_OUT 0 +# define GPIO_A10_USED_INT 0 +# define GPIO_A10_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A10_OUT_PP) +# define GPIO_A10_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_A10_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A10_OUT_CLEAR) +# define GPIO_A10_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_A10_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A10_PULL_DOWN) +# define GPIO_A10_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A10_PULL_FLOAT) +# define GPIO_A10_PULL GPIO_FLOAT +#else +# define GPIO_A10_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A10_SPEED_2MHz) +# define GPIO_A10_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A10_SPEED_25MHz) +# define GPIO_A10_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_A10_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO A11 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A11_OUT) +# define GPIO_A11_USED_OUT 1 +# define GPIO_A11_USED_INT 0 +# define GPIO_A11_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A11_INT) +# define GPIO_A11_USED_OUT 0 +# define GPIO_A11_USED_INT 1 +# define GPIO_A11_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A11_IN) +# define GPIO_A11_USED_OUT 0 +# define GPIO_A11_USED_INT 0 +# define GPIO_A11_USED_IN 1 +#else +# define GPIO_A11_USED_OUT 0 +# define GPIO_A11_USED_INT 0 +# define GPIO_A11_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A11_OUT_PP) +# define GPIO_A11_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_A11_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A11_OUT_CLEAR) +# define GPIO_A11_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_A11_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A11_PULL_DOWN) +# define GPIO_A11_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A11_PULL_FLOAT) +# define GPIO_A11_PULL GPIO_FLOAT +#else +# define GPIO_A11_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A11_SPEED_2MHz) +# define GPIO_A11_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A11_SPEED_25MHz) +# define GPIO_A11_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_A11_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO A12 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A12_OUT) +# define GPIO_A12_USED_OUT 1 +# define GPIO_A12_USED_INT 0 +# define GPIO_A12_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A12_INT) +# define GPIO_A12_USED_OUT 0 +# define GPIO_A12_USED_INT 1 +# define GPIO_A12_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A12_IN) +# define GPIO_A12_USED_OUT 0 +# define GPIO_A12_USED_INT 0 +# define GPIO_A12_USED_IN 1 +#else +# define GPIO_A12_USED_OUT 0 +# define GPIO_A12_USED_INT 0 +# define GPIO_A12_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A12_OUT_PP) +# define GPIO_A12_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_A12_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A12_OUT_CLEAR) +# define GPIO_A12_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_A12_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A12_PULL_DOWN) +# define GPIO_A12_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A12_PULL_FLOAT) +# define GPIO_A12_PULL GPIO_FLOAT +#else +# define GPIO_A12_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A12_SPEED_2MHz) +# define GPIO_A12_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A12_SPEED_25MHz) +# define GPIO_A12_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_A12_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO A15 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A15_OUT) +# define GPIO_A15_USED_OUT 1 +# define GPIO_A15_USED_INT 0 +# define GPIO_A15_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A15_INT) +# define GPIO_A15_USED_OUT 0 +# define GPIO_A15_USED_INT 1 +# define GPIO_A15_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A15_IN) +# define GPIO_A15_USED_OUT 0 +# define GPIO_A15_USED_INT 0 +# define GPIO_A15_USED_IN 1 +#else +# define GPIO_A15_USED_OUT 0 +# define GPIO_A15_USED_INT 0 +# define GPIO_A15_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A15_OUT_PP) +# define GPIO_A15_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_A15_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A15_OUT_CLEAR) +# define GPIO_A15_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_A15_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A15_PULL_DOWN) +# define GPIO_A15_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A15_PULL_FLOAT) +# define GPIO_A15_PULL GPIO_FLOAT +#else +# define GPIO_A15_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_A15_SPEED_2MHz) +# define GPIO_A15_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_A15_SPEED_25MHz) +# define GPIO_A15_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_A15_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO B0 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B0_OUT) +# define GPIO_B0_USED_OUT 1 +# define GPIO_B0_USED_INT 0 +# define GPIO_B0_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B0_INT) +# define GPIO_B0_USED_OUT 0 +# define GPIO_B0_USED_INT 1 +# define GPIO_B0_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B0_IN) +# define GPIO_B0_USED_OUT 0 +# define GPIO_B0_USED_INT 0 +# define GPIO_B0_USED_IN 1 +#else +# define GPIO_B0_USED_OUT 0 +# define GPIO_B0_USED_INT 0 +# define GPIO_B0_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B0_OUT_PP) +# define GPIO_B0_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_B0_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B0_OUT_CLEAR) +# define GPIO_B0_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_B0_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B0_PULL_DOWN) +# define GPIO_B0_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B0_PULL_FLOAT) +# define GPIO_B0_PULL GPIO_FLOAT +#else +# define GPIO_B0_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B0_SPEED_2MHz) +# define GPIO_B0_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B0_SPEED_25MHz) +# define GPIO_B0_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_B0_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO B1 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B1_OUT) +# define GPIO_B1_USED_OUT 1 +# define GPIO_B1_USED_INT 0 +# define GPIO_B1_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B1_INT) +# define GPIO_B1_USED_OUT 0 +# define GPIO_B1_USED_INT 1 +# define GPIO_B1_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B1_IN) +# define GPIO_B1_USED_OUT 0 +# define GPIO_B1_USED_INT 0 +# define GPIO_B1_USED_IN 1 +#else +# define GPIO_B1_USED_OUT 0 +# define GPIO_B1_USED_INT 0 +# define GPIO_B1_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B1_OUT_PP) +# define GPIO_B1_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_B1_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B1_OUT_CLEAR) +# define GPIO_B1_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_B1_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B1_PULL_DOWN) +# define GPIO_B1_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B1_PULL_FLOAT) +# define GPIO_B1_PULL GPIO_FLOAT +#else +# define GPIO_B1_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B1_SPEED_2MHz) +# define GPIO_B1_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B1_SPEED_25MHz) +# define GPIO_B1_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_B1_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO B2 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B2_OUT) +# define GPIO_B2_USED_OUT 1 +# define GPIO_B2_USED_INT 0 +# define GPIO_B2_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B2_INT) +# define GPIO_B2_USED_OUT 0 +# define GPIO_B2_USED_INT 1 +# define GPIO_B2_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B2_IN) +# define GPIO_B2_USED_OUT 0 +# define GPIO_B2_USED_INT 0 +# define GPIO_B2_USED_IN 1 +#else +# define GPIO_B2_USED_OUT 0 +# define GPIO_B2_USED_INT 0 +# define GPIO_B2_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B2_OUT_PP) +# define GPIO_B2_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_B2_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B2_OUT_CLEAR) +# define GPIO_B2_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_B2_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B2_PULL_DOWN) +# define GPIO_B2_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B2_PULL_FLOAT) +# define GPIO_B2_PULL GPIO_FLOAT +#else +# define GPIO_B2_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B2_SPEED_2MHz) +# define GPIO_B2_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B2_SPEED_25MHz) +# define GPIO_B2_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_B2_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO B3 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B3_OUT) +# define GPIO_B3_USED_OUT 1 +# define GPIO_B3_USED_INT 0 +# define GPIO_B3_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B3_INT) +# define GPIO_B3_USED_OUT 0 +# define GPIO_B3_USED_INT 1 +# define GPIO_B3_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B3_IN) +# define GPIO_B3_USED_OUT 0 +# define GPIO_B3_USED_INT 0 +# define GPIO_B3_USED_IN 1 +#else +# define GPIO_B3_USED_OUT 0 +# define GPIO_B3_USED_INT 0 +# define GPIO_B3_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B3_OUT_PP) +# define GPIO_B3_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_B3_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B3_OUT_CLEAR) +# define GPIO_B3_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_B3_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B3_PULL_DOWN) +# define GPIO_B3_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B3_PULL_FLOAT) +# define GPIO_B3_PULL GPIO_FLOAT +#else +# define GPIO_B3_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B3_SPEED_2MHz) +# define GPIO_B3_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B3_SPEED_25MHz) +# define GPIO_B3_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_B3_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO B4 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B4_OUT) +# define GPIO_B4_USED_OUT 1 +# define GPIO_B4_USED_INT 0 +# define GPIO_B4_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B4_INT) +# define GPIO_B4_USED_OUT 0 +# define GPIO_B4_USED_INT 1 +# define GPIO_B4_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B4_IN) +# define GPIO_B4_USED_OUT 0 +# define GPIO_B4_USED_INT 0 +# define GPIO_B4_USED_IN 1 +#else +# define GPIO_B4_USED_OUT 0 +# define GPIO_B4_USED_INT 0 +# define GPIO_B4_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B4_OUT_PP) +# define GPIO_B4_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_B4_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B4_OUT_CLEAR) +# define GPIO_B4_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_B4_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B4_PULL_DOWN) +# define GPIO_B4_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B4_PULL_FLOAT) +# define GPIO_B4_PULL GPIO_FLOAT +#else +# define GPIO_B4_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B4_SPEED_2MHz) +# define GPIO_B4_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B4_SPEED_25MHz) +# define GPIO_B4_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_B4_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO B5 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B5_OUT) +# define GPIO_B5_USED_OUT 1 +# define GPIO_B5_USED_INT 0 +# define GPIO_B5_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B5_INT) +# define GPIO_B5_USED_OUT 0 +# define GPIO_B5_USED_INT 1 +# define GPIO_B5_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B5_IN) +# define GPIO_B5_USED_OUT 0 +# define GPIO_B5_USED_INT 0 +# define GPIO_B5_USED_IN 1 +#else +# define GPIO_B5_USED_OUT 0 +# define GPIO_B5_USED_INT 0 +# define GPIO_B5_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B5_OUT_PP) +# define GPIO_B5_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_B5_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B5_OUT_CLEAR) +# define GPIO_B5_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_B5_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B5_PULL_DOWN) +# define GPIO_B5_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B5_PULL_FLOAT) +# define GPIO_B5_PULL GPIO_FLOAT +#else +# define GPIO_B5_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B5_SPEED_2MHz) +# define GPIO_B5_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B5_SPEED_25MHz) +# define GPIO_B5_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_B5_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO B6 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B6_OUT) +# define GPIO_B6_USED_OUT 1 +# define GPIO_B6_USED_INT 0 +# define GPIO_B6_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B6_INT) +# define GPIO_B6_USED_OUT 0 +# define GPIO_B6_USED_INT 1 +# define GPIO_B6_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B6_IN) +# define GPIO_B6_USED_OUT 0 +# define GPIO_B6_USED_INT 0 +# define GPIO_B6_USED_IN 1 +#else +# define GPIO_B6_USED_OUT 0 +# define GPIO_B6_USED_INT 0 +# define GPIO_B6_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B6_OUT_PP) +# define GPIO_B6_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_B6_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B6_OUT_CLEAR) +# define GPIO_B6_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_B6_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B6_PULL_DOWN) +# define GPIO_B6_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B6_PULL_FLOAT) +# define GPIO_B6_PULL GPIO_FLOAT +#else +# define GPIO_B6_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B6_SPEED_2MHz) +# define GPIO_B6_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B6_SPEED_25MHz) +# define GPIO_B6_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_B6_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO B7 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B7_OUT) +# define GPIO_B7_USED_OUT 1 +# define GPIO_B7_USED_INT 0 +# define GPIO_B7_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B7_INT) +# define GPIO_B7_USED_OUT 0 +# define GPIO_B7_USED_INT 1 +# define GPIO_B7_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B7_IN) +# define GPIO_B7_USED_OUT 0 +# define GPIO_B7_USED_INT 0 +# define GPIO_B7_USED_IN 1 +#else +# define GPIO_B7_USED_OUT 0 +# define GPIO_B7_USED_INT 0 +# define GPIO_B7_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B7_OUT_PP) +# define GPIO_B7_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_B7_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B7_OUT_CLEAR) +# define GPIO_B7_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_B7_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B7_PULL_DOWN) +# define GPIO_B7_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B7_PULL_FLOAT) +# define GPIO_B7_PULL GPIO_FLOAT +#else +# define GPIO_B7_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B7_SPEED_2MHz) +# define GPIO_B7_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B7_SPEED_25MHz) +# define GPIO_B7_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_B7_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO B8 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B8_OUT) +# define GPIO_B8_USED_OUT 1 +# define GPIO_B8_USED_INT 0 +# define GPIO_B8_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B8_INT) +# define GPIO_B8_USED_OUT 0 +# define GPIO_B8_USED_INT 1 +# define GPIO_B8_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B8_IN) +# define GPIO_B8_USED_OUT 0 +# define GPIO_B8_USED_INT 0 +# define GPIO_B8_USED_IN 1 +#else +# define GPIO_B8_USED_OUT 0 +# define GPIO_B8_USED_INT 0 +# define GPIO_B8_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B8_OUT_PP) +# define GPIO_B8_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_B8_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B8_OUT_CLEAR) +# define GPIO_B8_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_B8_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B8_PULL_DOWN) +# define GPIO_B8_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B8_PULL_FLOAT) +# define GPIO_B8_PULL GPIO_FLOAT +#else +# define GPIO_B8_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B8_SPEED_2MHz) +# define GPIO_B8_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B8_SPEED_25MHz) +# define GPIO_B8_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_B8_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO B9 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B9_OUT) +# define GPIO_B9_USED_OUT 1 +# define GPIO_B9_USED_INT 0 +# define GPIO_B9_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B9_INT) +# define GPIO_B9_USED_OUT 0 +# define GPIO_B9_USED_INT 1 +# define GPIO_B9_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B9_IN) +# define GPIO_B9_USED_OUT 0 +# define GPIO_B9_USED_INT 0 +# define GPIO_B9_USED_IN 1 +#else +# define GPIO_B9_USED_OUT 0 +# define GPIO_B9_USED_INT 0 +# define GPIO_B9_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B9_OUT_PP) +# define GPIO_B9_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_B9_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B9_OUT_CLEAR) +# define GPIO_B9_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_B9_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B9_PULL_DOWN) +# define GPIO_B9_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B9_PULL_FLOAT) +# define GPIO_B9_PULL GPIO_FLOAT +#else +# define GPIO_B9_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B9_SPEED_2MHz) +# define GPIO_B9_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B9_SPEED_25MHz) +# define GPIO_B9_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_B9_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO B10 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B10_OUT) +# define GPIO_B10_USED_OUT 1 +# define GPIO_B10_USED_INT 0 +# define GPIO_B10_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B10_INT) +# define GPIO_B10_USED_OUT 0 +# define GPIO_B10_USED_INT 1 +# define GPIO_B10_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B10_IN) +# define GPIO_B10_USED_OUT 0 +# define GPIO_B10_USED_INT 0 +# define GPIO_B10_USED_IN 1 +#else +# define GPIO_B10_USED_OUT 0 +# define GPIO_B10_USED_INT 0 +# define GPIO_B10_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B10_OUT_PP) +# define GPIO_B10_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_B10_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B10_OUT_CLEAR) +# define GPIO_B10_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_B10_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B10_PULL_DOWN) +# define GPIO_B10_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B10_PULL_FLOAT) +# define GPIO_B10_PULL GPIO_FLOAT +#else +# define GPIO_B10_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B10_SPEED_2MHz) +# define GPIO_B10_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B10_SPEED_25MHz) +# define GPIO_B10_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_B10_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO B12 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B12_OUT) +# define GPIO_B12_USED_OUT 1 +# define GPIO_B12_USED_INT 0 +# define GPIO_B12_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B12_INT) +# define GPIO_B12_USED_OUT 0 +# define GPIO_B12_USED_INT 1 +# define GPIO_B12_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B12_IN) +# define GPIO_B12_USED_OUT 0 +# define GPIO_B12_USED_INT 0 +# define GPIO_B12_USED_IN 1 +#else +# define GPIO_B12_USED_OUT 0 +# define GPIO_B12_USED_INT 0 +# define GPIO_B12_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B12_OUT_PP) +# define GPIO_B12_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_B12_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B12_OUT_CLEAR) +# define GPIO_B12_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_B12_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B12_PULL_DOWN) +# define GPIO_B12_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B12_PULL_FLOAT) +# define GPIO_B12_PULL GPIO_FLOAT +#else +# define GPIO_B12_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B12_SPEED_2MHz) +# define GPIO_B12_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B12_SPEED_25MHz) +# define GPIO_B12_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_B12_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO B13 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B13_OUT) +# define GPIO_B13_USED_OUT 1 +# define GPIO_B13_USED_INT 0 +# define GPIO_B13_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B13_INT) +# define GPIO_B13_USED_OUT 0 +# define GPIO_B13_USED_INT 1 +# define GPIO_B13_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B13_IN) +# define GPIO_B13_USED_OUT 0 +# define GPIO_B13_USED_INT 0 +# define GPIO_B13_USED_IN 1 +#else +# define GPIO_B13_USED_OUT 0 +# define GPIO_B13_USED_INT 0 +# define GPIO_B13_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B13_OUT_PP) +# define GPIO_B13_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_B13_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B13_OUT_CLEAR) +# define GPIO_B13_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_B13_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B13_PULL_DOWN) +# define GPIO_B13_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B13_PULL_FLOAT) +# define GPIO_B13_PULL GPIO_FLOAT +#else +# define GPIO_B13_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B13_SPEED_2MHz) +# define GPIO_B13_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B13_SPEED_25MHz) +# define GPIO_B13_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_B13_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO B14 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B14_OUT) +# define GPIO_B14_USED_OUT 1 +# define GPIO_B14_USED_INT 0 +# define GPIO_B14_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B14_INT) +# define GPIO_B14_USED_OUT 0 +# define GPIO_B14_USED_INT 1 +# define GPIO_B14_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B14_IN) +# define GPIO_B14_USED_OUT 0 +# define GPIO_B14_USED_INT 0 +# define GPIO_B14_USED_IN 1 +#else +# define GPIO_B14_USED_OUT 0 +# define GPIO_B14_USED_INT 0 +# define GPIO_B14_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B14_OUT_PP) +# define GPIO_B14_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_B14_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B14_OUT_CLEAR) +# define GPIO_B14_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_B14_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B14_PULL_DOWN) +# define GPIO_B14_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B14_PULL_FLOAT) +# define GPIO_B14_PULL GPIO_FLOAT +#else +# define GPIO_B14_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B14_SPEED_2MHz) +# define GPIO_B14_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B14_SPEED_25MHz) +# define GPIO_B14_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_B14_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO B15 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B15_OUT) +# define GPIO_B15_USED_OUT 1 +# define GPIO_B15_USED_INT 0 +# define GPIO_B15_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B15_INT) +# define GPIO_B15_USED_OUT 0 +# define GPIO_B15_USED_INT 1 +# define GPIO_B15_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B15_IN) +# define GPIO_B15_USED_OUT 0 +# define GPIO_B15_USED_INT 0 +# define GPIO_B15_USED_IN 1 +#else +# define GPIO_B15_USED_OUT 0 +# define GPIO_B15_USED_INT 0 +# define GPIO_B15_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B15_OUT_PP) +# define GPIO_B15_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_B15_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B15_OUT_CLEAR) +# define GPIO_B15_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_B15_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B15_PULL_DOWN) +# define GPIO_B15_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B15_PULL_FLOAT) +# define GPIO_B15_PULL GPIO_FLOAT +#else +# define GPIO_B15_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_B15_SPEED_2MHz) +# define GPIO_B15_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_B15_SPEED_25MHz) +# define GPIO_B15_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_B15_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO C13 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_C13_OUT) +# define GPIO_C13_USED_OUT 1 +# define GPIO_C13_USED_INT 0 +# define GPIO_C13_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_C13_INT) +# define GPIO_C13_USED_OUT 0 +# define GPIO_C13_USED_INT 1 +# define GPIO_C13_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_C13_IN) +# define GPIO_C13_USED_OUT 0 +# define GPIO_C13_USED_INT 0 +# define GPIO_C13_USED_IN 1 +#else +# define GPIO_C13_USED_OUT 0 +# define GPIO_C13_USED_INT 0 +# define GPIO_C13_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_C13_OUT_PP) +# define GPIO_C13_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_C13_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_C13_OUT_CLEAR) +# define GPIO_C13_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_C13_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_C13_PULL_DOWN) +# define GPIO_C13_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_C13_PULL_FLOAT) +# define GPIO_C13_PULL GPIO_FLOAT +#else +# define GPIO_C13_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_C13_SPEED_2MHz) +# define GPIO_C13_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_C13_SPEED_25MHz) +# define GPIO_C13_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_C13_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO C14 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_C14_OUT) +# define GPIO_C14_USED_OUT 1 +# define GPIO_C14_USED_INT 0 +# define GPIO_C14_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_C14_INT) +# define GPIO_C14_USED_OUT 0 +# define GPIO_C14_USED_INT 1 +# define GPIO_C14_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_C14_IN) +# define GPIO_C14_USED_OUT 0 +# define GPIO_C14_USED_INT 0 +# define GPIO_C14_USED_IN 1 +#else +# define GPIO_C14_USED_OUT 0 +# define GPIO_C14_USED_INT 0 +# define GPIO_C14_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_C14_OUT_PP) +# define GPIO_C14_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_C14_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_C14_OUT_CLEAR) +# define GPIO_C14_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_C14_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_C14_PULL_DOWN) +# define GPIO_C14_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_C14_PULL_FLOAT) +# define GPIO_C14_PULL GPIO_FLOAT +#else +# define GPIO_C14_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_C14_SPEED_2MHz) +# define GPIO_C14_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_C14_SPEED_25MHz) +# define GPIO_C14_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_C14_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO C15 Kconfig Mapping */ + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_C15_OUT) +# define GPIO_C15_USED_OUT 1 +# define GPIO_C15_USED_INT 0 +# define GPIO_C15_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_C15_INT) +# define GPIO_C15_USED_OUT 0 +# define GPIO_C15_USED_INT 1 +# define GPIO_C15_USED_IN 0 +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_C15_IN) +# define GPIO_C15_USED_OUT 0 +# define GPIO_C15_USED_INT 0 +# define GPIO_C15_USED_IN 1 +#else +# define GPIO_C15_USED_OUT 0 +# define GPIO_C15_USED_INT 0 +# define GPIO_C15_USED_IN 0 +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_C15_OUT_PP) +# define GPIO_C15_OUTTYPE GPIO_PUSHPULL +#else +# define GPIO_C15_OUTTYPE GPIO_OPENDRAIN +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_C15_OUT_CLEAR) +# define GPIO_C15_OUT_DEFAULT GPIO_OUTPUT_CLEAR +#else +# define GPIO_C15_OUT_DEFAULT GPIO_OUTPUT_SET +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_C15_PULL_DOWN) +# define GPIO_C15_PULL GPIO_PULLDOWN +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_C15_PULL_FLOAT) +# define GPIO_C15_PULL GPIO_FLOAT +#else +# define GPIO_C15_PULL GPIO_PULLUP +#endif + +#if defined(CONFIG_STM32F411MINIMUM_GPIO_C15_SPEED_2MHz) +# define GPIO_C15_SPEED GPIO_SPEED_2MHz +#elif defined(CONFIG_STM32F411MINIMUM_GPIO_C15_SPEED_25MHz) +# define GPIO_C15_SPEED GPIO_SPEED_25MHz +#else +# define GPIO_C15_SPEED GPIO_SPEED_50MHz +#endif + +/* GPIO_A0 definition */ + +#define GPIO_A0_OUT (GPIO_OUTPUT|GPIO_A0_OUTTYPE|GPIO_A0_OUT_DEFAULT|\ + GPIO_A0_PULL|GPIO_A0_SPEED|GPIO_PORTA|GPIO_PIN0) +#define GPIO_A0_IN (GPIO_INPUT|GPIO_A0_PULL|GPIO_A0_SPEED|\ + GPIO_PORTA|GPIO_PIN0) +#define GPIO_A0_INT (GPIO_A0_IN|GPIO_EXTI) + +/* GPIO_A1 definition */ + +#define GPIO_A1_OUT (GPIO_OUTPUT|GPIO_A1_OUTTYPE|GPIO_A1_OUT_DEFAULT|\ + GPIO_A1_PULL|GPIO_A1_SPEED|GPIO_PORTA|GPIO_PIN1) +#define GPIO_A1_IN (GPIO_INPUT|GPIO_A1_PULL|GPIO_A1_SPEED|\ + GPIO_PORTA|GPIO_PIN1) +#define GPIO_A1_INT (GPIO_A1_IN|GPIO_EXTI) + +/* GPIO_A2 definition */ + +#define GPIO_A2_OUT (GPIO_OUTPUT|GPIO_A2_OUTTYPE|GPIO_A2_OUT_DEFAULT|\ + GPIO_A2_PULL|GPIO_A2_SPEED|GPIO_PORTA|GPIO_PIN2) +#define GPIO_A2_IN (GPIO_INPUT|GPIO_A2_PULL|GPIO_A2_SPEED|\ + GPIO_PORTA|GPIO_PIN2) +#define GPIO_A2_INT (GPIO_A2_IN|GPIO_EXTI) + +/* GPIO_A3 definition */ + +#define GPIO_A3_OUT (GPIO_OUTPUT|GPIO_A3_OUTTYPE|GPIO_A3_OUT_DEFAULT|\ + GPIO_A3_PULL|GPIO_A3_SPEED|GPIO_PORTA|GPIO_PIN3) +#define GPIO_A3_IN (GPIO_INPUT|GPIO_A3_PULL|GPIO_A3_SPEED|\ + GPIO_PORTA|GPIO_PIN3) +#define GPIO_A3_INT (GPIO_A3_IN|GPIO_EXTI) + +/* GPIO_A4 definition */ + +#define GPIO_A4_OUT (GPIO_OUTPUT|GPIO_A4_OUTTYPE|GPIO_A4_OUT_DEFAULT|\ + GPIO_A4_PULL|GPIO_A4_SPEED|GPIO_PORTA|GPIO_PIN4) +#define GPIO_A4_IN (GPIO_INPUT|GPIO_A4_PULL|GPIO_A4_SPEED|\ + GPIO_PORTA|GPIO_PIN4) +#define GPIO_A4_INT (GPIO_A4_IN|GPIO_EXTI) + +/* GPIO_A5 definition */ + +#define GPIO_A5_OUT (GPIO_OUTPUT|GPIO_A5_OUTTYPE|GPIO_A5_OUT_DEFAULT|\ + GPIO_A5_PULL|GPIO_A5_SPEED|GPIO_PORTA|GPIO_PIN5) +#define GPIO_A5_IN (GPIO_INPUT|GPIO_A5_PULL|GPIO_A5_SPEED|\ + GPIO_PORTA|GPIO_PIN5) +#define GPIO_A5_INT (GPIO_A5_IN|GPIO_EXTI) + +/* GPIO_A6 definition */ + +#define GPIO_A6_OUT (GPIO_OUTPUT|GPIO_A6_OUTTYPE|GPIO_A6_OUT_DEFAULT|\ + GPIO_A6_PULL|GPIO_A6_SPEED|GPIO_PORTA|GPIO_PIN6) +#define GPIO_A6_IN (GPIO_INPUT|GPIO_A6_PULL|GPIO_A6_SPEED|\ + GPIO_PORTA|GPIO_PIN6) +#define GPIO_A6_INT (GPIO_A6_IN|GPIO_EXTI) + +/* GPIO_A7 definition */ + +#define GPIO_A7_OUT (GPIO_OUTPUT|GPIO_A7_OUTTYPE|GPIO_A7_OUT_DEFAULT|\ + GPIO_A7_PULL|GPIO_A7_SPEED|GPIO_PORTA|GPIO_PIN7) +#define GPIO_A7_IN (GPIO_INPUT|GPIO_A7_PULL|GPIO_A7_SPEED|\ + GPIO_PORTA|GPIO_PIN7) +#define GPIO_A7_INT (GPIO_A7_IN|GPIO_EXTI) + +/* GPIO_A8 definition */ + +#define GPIO_A8_OUT (GPIO_OUTPUT|GPIO_A8_OUTTYPE|GPIO_A8_OUT_DEFAULT|\ + GPIO_A8_PULL|GPIO_A8_SPEED|GPIO_PORTA|GPIO_PIN8) +#define GPIO_A8_IN (GPIO_INPUT|GPIO_A8_PULL|GPIO_A8_SPEED|\ + GPIO_PORTA|GPIO_PIN8) +#define GPIO_A8_INT (GPIO_A8_IN|GPIO_EXTI) + +/* GPIO_A9 definition */ + +#define GPIO_A9_OUT (GPIO_OUTPUT|GPIO_A9_OUTTYPE|GPIO_A9_OUT_DEFAULT|\ + GPIO_A9_PULL|GPIO_A9_SPEED|GPIO_PORTA|GPIO_PIN9) +#define GPIO_A9_IN (GPIO_INPUT|GPIO_A9_PULL|GPIO_A9_SPEED|\ + GPIO_PORTA|GPIO_PIN9) +#define GPIO_A9_INT (GPIO_A9_IN|GPIO_EXTI) + +/* GPIO_A10 definition */ + +#define GPIO_A10_OUT (GPIO_OUTPUT|GPIO_A10_OUTTYPE|GPIO_A10_OUT_DEFAULT|\ + GPIO_A10_PULL|GPIO_A10_SPEED|GPIO_PORTA|GPIO_PIN10) +#define GPIO_A10_IN (GPIO_INPUT|GPIO_A10_PULL|GPIO_A10_SPEED|\ + GPIO_PORTA|GPIO_PIN10) +#define GPIO_A10_INT (GPIO_A10_IN|GPIO_EXTI) + +/* GPIO_A11 definition */ + +#define GPIO_A11_OUT (GPIO_OUTPUT|GPIO_A11_OUTTYPE|GPIO_A11_OUT_DEFAULT|\ + GPIO_A11_PULL|GPIO_A11_SPEED|GPIO_PORTA|GPIO_PIN11) +#define GPIO_A11_IN (GPIO_INPUT|GPIO_A11_PULL|GPIO_A11_SPEED|\ + GPIO_PORTA|GPIO_PIN11) +#define GPIO_A11_INT (GPIO_A11_IN|GPIO_EXTI) + +/* GPIO_A12 definition */ + +#define GPIO_A12_OUT (GPIO_OUTPUT|GPIO_A12_OUTTYPE|GPIO_A12_OUT_DEFAULT|\ + GPIO_A12_PULL|GPIO_A12_SPEED|GPIO_PORTA|GPIO_PIN12) +#define GPIO_A12_IN (GPIO_INPUT|GPIO_A12_PULL|GPIO_A12_SPEED|\ + GPIO_PORTA|GPIO_PIN12) +#define GPIO_A12_INT (GPIO_A12_IN|GPIO_EXTI) + +/* GPIO_A15 definition */ + +#define GPIO_A15_OUT (GPIO_OUTPUT|GPIO_A15_OUTTYPE|GPIO_A15_OUT_DEFAULT|\ + GPIO_A15_PULL|GPIO_A15_SPEED|GPIO_PORTA|GPIO_PIN15) +#define GPIO_A15_IN (GPIO_INPUT|GPIO_A15_PULL|GPIO_A15_SPEED|\ + GPIO_PORTA|GPIO_PIN15) +#define GPIO_A15_INT (GPIO_A15_IN|GPIO_EXTI) + +/* GPIO_B0 definition */ + +#define GPIO_B0_OUT (GPIO_OUTPUT|GPIO_B0_OUTTYPE|GPIO_B0_OUT_DEFAULT|\ + GPIO_B0_PULL|GPIO_B0_SPEED|GPIO_PORTB|GPIO_PIN0) +#define GPIO_B0_IN (GPIO_INPUT|GPIO_B0_PULL|GPIO_B0_SPEED|\ + GPIO_PORTB|GPIO_PIN0) +#define GPIO_B0_INT (GPIO_B0_IN|GPIO_EXTI) + +/* GPIO_B1 definition */ + +#define GPIO_B1_OUT (GPIO_OUTPUT|GPIO_B1_OUTTYPE|GPIO_B1_OUT_DEFAULT|\ + GPIO_B1_PULL|GPIO_B1_SPEED|GPIO_PORTB|GPIO_PIN1) +#define GPIO_B1_IN (GPIO_INPUT|GPIO_B1_PULL|GPIO_B1_SPEED|\ + GPIO_PORTB|GPIO_PIN1) +#define GPIO_B1_INT (GPIO_B1_IN|GPIO_EXTI) + +/* GPIO_B2 definition */ + +#define GPIO_B2_OUT (GPIO_OUTPUT|GPIO_B2_OUTTYPE|GPIO_B2_OUT_DEFAULT|\ + GPIO_B2_PULL|GPIO_B2_SPEED|GPIO_PORTB|GPIO_PIN2) +#define GPIO_B2_IN (GPIO_INPUT|GPIO_B2_PULL|GPIO_B2_SPEED|\ + GPIO_PORTB|GPIO_PIN2) +#define GPIO_B2_INT (GPIO_B2_IN|GPIO_EXTI) + +/* GPIO_B3 definition */ + +#define GPIO_B3_OUT (GPIO_OUTPUT|GPIO_B3_OUTTYPE|GPIO_B3_OUT_DEFAULT|\ + GPIO_B3_PULL|GPIO_B3_SPEED|GPIO_PORTB|GPIO_PIN3) +#define GPIO_B3_IN (GPIO_INPUT|GPIO_B3_PULL|GPIO_B3_SPEED|\ + GPIO_PORTB|GPIO_PIN3) +#define GPIO_B3_INT (GPIO_B3_IN|GPIO_EXTI) + +/* GPIO_B4 definition */ + +#define GPIO_B4_OUT (GPIO_OUTPUT|GPIO_B4_OUTTYPE|GPIO_B4_OUT_DEFAULT|\ + GPIO_B4_PULL|GPIO_B4_SPEED|GPIO_PORTB|GPIO_PIN4) +#define GPIO_B4_IN (GPIO_INPUT|GPIO_B4_PULL|GPIO_B4_SPEED|\ + GPIO_PORTB|GPIO_PIN4) +#define GPIO_B4_INT (GPIO_B4_IN|GPIO_EXTI) + +/* GPIO_B5 definition */ + +#define GPIO_B5_OUT (GPIO_OUTPUT|GPIO_B5_OUTTYPE|GPIO_B5_OUT_DEFAULT|\ + GPIO_B5_PULL|GPIO_B5_SPEED|GPIO_PORTB|GPIO_PIN5) +#define GPIO_B5_IN (GPIO_INPUT|GPIO_B5_PULL|GPIO_B5_SPEED|\ + GPIO_PORTB|GPIO_PIN5) +#define GPIO_B5_INT (GPIO_B5_IN|GPIO_EXTI) + +/* GPIO_B6 definition */ + +#define GPIO_B6_OUT (GPIO_OUTPUT|GPIO_B6_OUTTYPE|GPIO_B6_OUT_DEFAULT|\ + GPIO_B6_PULL|GPIO_B6_SPEED|GPIO_PORTB|GPIO_PIN6) +#define GPIO_B6_IN (GPIO_INPUT|GPIO_B6_PULL|GPIO_B6_SPEED|\ + GPIO_PORTB|GPIO_PIN6) +#define GPIO_B6_INT (GPIO_B6_IN|GPIO_EXTI) + +/* GPIO_B7 definition */ + +#define GPIO_B7_OUT (GPIO_OUTPUT|GPIO_B7_OUTTYPE|GPIO_B7_OUT_DEFAULT|\ + GPIO_B7_PULL|GPIO_B7_SPEED|GPIO_PORTB|GPIO_PIN7) +#define GPIO_B7_IN (GPIO_INPUT|GPIO_B7_PULL|GPIO_B7_SPEED|\ + GPIO_PORTB|GPIO_PIN7) +#define GPIO_B7_INT (GPIO_B7_IN|GPIO_EXTI) + +/* GPIO_B8 definition */ + +#define GPIO_B8_OUT (GPIO_OUTPUT|GPIO_B8_OUTTYPE|GPIO_B8_OUT_DEFAULT|\ + GPIO_B8_PULL|GPIO_B8_SPEED|GPIO_PORTB|GPIO_PIN8) +#define GPIO_B8_IN (GPIO_INPUT|GPIO_B8_PULL|GPIO_B8_SPEED|\ + GPIO_PORTB|GPIO_PIN8) +#define GPIO_B8_INT (GPIO_B8_IN|GPIO_EXTI) + +/* GPIO_B9 definition */ + +#define GPIO_B9_OUT (GPIO_OUTPUT|GPIO_B9_OUTTYPE|GPIO_B9_OUT_DEFAULT|\ + GPIO_B9_PULL|GPIO_B9_SPEED|GPIO_PORTB|GPIO_PIN9) +#define GPIO_B9_IN (GPIO_INPUT|GPIO_B9_PULL|GPIO_B9_SPEED|\ + GPIO_PORTB|GPIO_PIN9) +#define GPIO_B9_INT (GPIO_B9_IN|GPIO_EXTI) + +/* GPIO_B10 definition */ + +#define GPIO_B10_OUT (GPIO_OUTPUT|GPIO_B10_OUTTYPE|GPIO_B10_OUT_DEFAULT|\ + GPIO_B10_PULL|GPIO_B10_SPEED|GPIO_PORTB|GPIO_PIN10) +#define GPIO_B10_IN (GPIO_INPUT|GPIO_B10_PULL|GPIO_B10_SPEED|\ + GPIO_PORTB|GPIO_PIN10) +#define GPIO_B10_INT (GPIO_B10_IN|GPIO_EXTI) + +/* GPIO_B12 definition */ + +#define GPIO_B12_OUT (GPIO_OUTPUT|GPIO_B12_OUTTYPE|GPIO_B12_OUT_DEFAULT|\ + GPIO_B12_PULL|GPIO_B12_SPEED|GPIO_PORTB|GPIO_PIN12) +#define GPIO_B12_IN (GPIO_INPUT|GPIO_B12_PULL|GPIO_B12_SPEED|\ + GPIO_PORTB|GPIO_PIN12) +#define GPIO_B12_INT (GPIO_B12_IN|GPIO_EXTI) + +/* GPIO_B13 definition */ + +#define GPIO_B13_OUT (GPIO_OUTPUT|GPIO_B13_OUTTYPE|GPIO_B13_OUT_DEFAULT|\ + GPIO_B13_PULL|GPIO_B13_SPEED|GPIO_PORTB|GPIO_PIN13) +#define GPIO_B13_IN (GPIO_INPUT|GPIO_B13_PULL|GPIO_B13_SPEED|\ + GPIO_PORTB|GPIO_PIN13) +#define GPIO_B13_INT (GPIO_B13_IN|GPIO_EXTI) + +/* GPIO_B14 definition */ + +#define GPIO_B14_OUT (GPIO_OUTPUT|GPIO_B14_OUTTYPE|GPIO_B14_OUT_DEFAULT|\ + GPIO_B14_PULL|GPIO_B14_SPEED|GPIO_PORTB|GPIO_PIN14) +#define GPIO_B14_IN (GPIO_INPUT|GPIO_B14_PULL|GPIO_B14_SPEED|\ + GPIO_PORTB|GPIO_PIN14) +#define GPIO_B14_INT (GPIO_B14_IN|GPIO_EXTI) + +/* GPIO_B15 definition */ + +#define GPIO_B15_OUT (GPIO_OUTPUT|GPIO_B15_OUTTYPE|GPIO_B15_OUT_DEFAULT|\ + GPIO_B15_PULL|GPIO_B15_SPEED|GPIO_PORTB|GPIO_PIN15) +#define GPIO_B15_IN (GPIO_INPUT|GPIO_B15_PULL|GPIO_B15_SPEED|\ + GPIO_PORTB|GPIO_PIN15) +#define GPIO_B15_INT (GPIO_B15_IN|GPIO_EXTI) + +/* GPIO_C13 definition */ + +#define GPIO_C13_OUT (GPIO_OUTPUT|GPIO_C13_OUTTYPE|GPIO_C13_OUT_DEFAULT|\ + GPIO_C13_PULL|GPIO_C13_SPEED|GPIO_PORTC|GPIO_PIN13) +#define GPIO_C13_IN (GPIO_INPUT|GPIO_C13_PULL|GPIO_C13_SPEED|\ + GPIO_PORTC|GPIO_PIN13) +#define GPIO_C13_INT (GPIO_C13_IN|GPIO_EXTI) + +/* GPIO_C14 definition */ + +#define GPIO_C14_OUT (GPIO_OUTPUT|GPIO_C14_OUTTYPE|GPIO_C14_OUT_DEFAULT|\ + GPIO_C14_PULL|GPIO_C14_SPEED|GPIO_PORTC|GPIO_PIN14) +#define GPIO_C14_IN (GPIO_INPUT|GPIO_C14_PULL|GPIO_C14_SPEED|\ + GPIO_PORTC|GPIO_PIN14) +#define GPIO_C14_INT (GPIO_C14_IN|GPIO_EXTI) + +/* GPIO_C15 definition */ + +#define GPIO_C15_OUT (GPIO_OUTPUT|GPIO_C15_OUTTYPE|GPIO_C15_OUT_DEFAULT|\ + GPIO_C15_PULL|GPIO_C15_SPEED|GPIO_PORTC|GPIO_PIN15) +#define GPIO_C15_IN (GPIO_INPUT|GPIO_C15_PULL|GPIO_C15_SPEED|\ + GPIO_PORTC|GPIO_PIN15) +#define GPIO_C15_INT (GPIO_C15_IN|GPIO_EXTI) + +#define BOARD_NGPIO_OUT \ + GPIO_A0_USED_OUT + \ + GPIO_A1_USED_OUT + \ + GPIO_A2_USED_OUT + \ + GPIO_A3_USED_OUT + \ + GPIO_A4_USED_OUT + \ + GPIO_A5_USED_OUT + \ + GPIO_A6_USED_OUT + \ + GPIO_A7_USED_OUT + \ + GPIO_A8_USED_OUT + \ + GPIO_A9_USED_OUT + \ + GPIO_A10_USED_OUT + \ + GPIO_A11_USED_OUT + \ + GPIO_A12_USED_OUT + \ + GPIO_A15_USED_OUT + \ + GPIO_B0_USED_OUT + \ + GPIO_B1_USED_OUT + \ + GPIO_B2_USED_OUT + \ + GPIO_B3_USED_OUT + \ + GPIO_B4_USED_OUT + \ + GPIO_B5_USED_OUT + \ + GPIO_B6_USED_OUT + \ + GPIO_B7_USED_OUT + \ + GPIO_B8_USED_OUT + \ + GPIO_B9_USED_OUT + \ + GPIO_B10_USED_OUT + \ + GPIO_B12_USED_OUT + \ + GPIO_B13_USED_OUT + \ + GPIO_B14_USED_OUT + \ + GPIO_B15_USED_OUT + \ + GPIO_C13_USED_OUT + \ + GPIO_C14_USED_OUT + \ + GPIO_C15_USED_OUT + +#define BOARD_NGPIO_IN \ + GPIO_A0_USED_IN + \ + GPIO_A1_USED_IN + \ + GPIO_A2_USED_IN + \ + GPIO_A3_USED_IN + \ + GPIO_A4_USED_IN + \ + GPIO_A5_USED_IN + \ + GPIO_A6_USED_IN + \ + GPIO_A7_USED_IN + \ + GPIO_A8_USED_IN + \ + GPIO_A9_USED_IN + \ + GPIO_A10_USED_IN + \ + GPIO_A11_USED_IN + \ + GPIO_A12_USED_IN + \ + GPIO_A15_USED_IN + \ + GPIO_B0_USED_IN + \ + GPIO_B1_USED_IN + \ + GPIO_B2_USED_IN + \ + GPIO_B3_USED_IN + \ + GPIO_B4_USED_IN + \ + GPIO_B5_USED_IN + \ + GPIO_B6_USED_IN + \ + GPIO_B7_USED_IN + \ + GPIO_B8_USED_IN + \ + GPIO_B9_USED_IN + \ + GPIO_B10_USED_IN + \ + GPIO_B12_USED_IN + \ + GPIO_B13_USED_IN + \ + GPIO_B14_USED_IN + \ + GPIO_B15_USED_IN + \ + GPIO_C13_USED_IN + \ + GPIO_C14_USED_IN + \ + GPIO_C15_USED_IN + +#define BOARD_NGPIO_INT \ + GPIO_A0_USED_INT + \ + GPIO_A1_USED_INT + \ + GPIO_A2_USED_INT + \ + GPIO_A3_USED_INT + \ + GPIO_A4_USED_INT + \ + GPIO_A5_USED_INT + \ + GPIO_A6_USED_INT + \ + GPIO_A7_USED_INT + \ + GPIO_A8_USED_INT + \ + GPIO_A9_USED_INT + \ + GPIO_A10_USED_INT + \ + GPIO_A11_USED_INT + \ + GPIO_A12_USED_INT + \ + GPIO_A15_USED_INT + \ + GPIO_B0_USED_INT + \ + GPIO_B1_USED_INT + \ + GPIO_B2_USED_INT + \ + GPIO_B3_USED_INT + \ + GPIO_B4_USED_INT + \ + GPIO_B5_USED_INT + \ + GPIO_B6_USED_INT + \ + GPIO_B7_USED_INT + \ + GPIO_B8_USED_INT + \ + GPIO_B9_USED_INT + \ + GPIO_B10_USED_INT + \ + GPIO_B12_USED_INT + \ + GPIO_B13_USED_INT + \ + GPIO_B14_USED_INT + \ + GPIO_B15_USED_INT + \ + GPIO_C13_USED_INT + \ + GPIO_C14_USED_INT + \ + GPIO_C15_USED_INT + +#if BOARD_NGPIO_INT > CONFIG_DEV_GPIO_NSIGNALS +# error You have enabled more interrupts than supported, adjust CONFIG_DEV_GPIO_NSIGNALS to support them all +#endif + +#endif /* __BOARDS_ARM_STM32_STM32F411_MINIMUM_SRC_STM32F411_MINIMUM_GPIO_H */ diff --git a/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum.h b/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum.h index c255d92dcf6c9..53770be2667d3 100644 --- a/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum.h +++ b/boards/arm/stm32/stm32f411-minimum/src/stm32f411-minimum.h @@ -27,9 +27,14 @@ #include #include +#include #include +#ifdef CONFIG_STM32F411MINIMUM_GPIO +#include "stm32f411-minimum-gpio.h" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -76,6 +81,29 @@ # endif #endif +/* HX711 pins */ + +#ifdef CONFIG_ADC_HX711 +# ifdef CONFIG_STM32F411MINIMUM_HX711_CLK_PORTB +# define HX711_CLK_PORT GPIO_PORTB +# else +# define HX711_CLK_PORT GPIO_PORTA +# endif + +# ifdef CONFIG_STM32F411MINIMUM_HX711_DATA_PORTB +# define HX711_DATA_PORT GPIO_PORTB +# else +# define HX711_DATA_PORT GPIO_PORTA +# endif + +#define HX711_CLK_PIN (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_OUTPUT_SET|\ + GPIO_SPEED_2MHz|GPIO_PULLUP|\ + HX711_CLK_PORT|CONFIG_STM32F411MINIMUM_HX711_CLK_PIN) +#define HX711_DATA_PIN (GPIO_INPUT|GPIO_SPEED_2MHz|GPIO_PULLUP|GPIO_EXTI|\ + HX711_DATA_PORT|CONFIG_STM32F411MINIMUM_HX711_DATA_PIN) + +#endif /* CONFIG_HX711 */ + /**************************************************************************** * Public Data ****************************************************************************/ @@ -99,6 +127,18 @@ extern struct spi_dev_s *g_spi2; void stm32_spidev_initialize(void); +/**************************************************************************** + * Name: stm32_hx711_initialize + * + * Description: + * Initialize hx711 chip + * + ****************************************************************************/ + +#ifdef CONFIG_ADC_HX711 +int stm32_hx711_initialize(void); +#endif + /**************************************************************************** * Name: stm32_mmcsd_initialize * @@ -148,6 +188,18 @@ void stm32_usbinitialize(void); int stm32_usbhost_initialize(void); #endif +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers + * + ****************************************************************************/ + +#ifdef CONFIG_STM32F411MINIMUM_GPIO +int stm32_gpio_initialize(void); +#endif + /**************************************************************************** * Name: stm32_bringup * diff --git a/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig b/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig index 41244b77560b5..f34da86dc6260 100644 --- a/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig +++ b/boards/arm/stm32/stm32f429i-disco/configs/lvgl/defconfig @@ -36,13 +36,13 @@ CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INPUT=y CONFIG_INPUT_STMPE811=y CONFIG_INTELHEX_BINARY=y -CONFIG_LV_MEM_CUSTOM=y -CONFIG_LV_PORT_USE_FBDEV=y -CONFIG_LV_PORT_USE_TOUCHPAD=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y CONFIG_LV_USE_DEMO_WIDGETS=y CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y CONFIG_MM_REGIONS=2 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y diff --git a/boards/arm/stm32/stm32f429i-disco/include/board.h b/boards/arm/stm32/stm32f429i-disco/include/board.h index 0cee8a9d2b6b9..ecc17d64aa570 100644 --- a/boards/arm/stm32/stm32f429i-disco/include/board.h +++ b/boards/arm/stm32/stm32f429i-disco/include/board.h @@ -205,6 +205,11 @@ #define GPIO_USART3_RX GPIO_USART3_RX_1 #define GPIO_USART3_TX GPIO_USART3_TX_1 + +/* CAN: */ +#define GPIO_CAN1_RX GPIO_CAN1_RX_2 +#define GPIO_CAN1_TX GPIO_CAN1_TX_2 + /* PWM * * The STM32F4 Discovery has no real on-board PWM devices, but the board can diff --git a/boards/arm/stm32/stm32f429i-disco/src/CMakeLists.txt b/boards/arm/stm32/stm32f429i-disco/src/CMakeLists.txt index a8f9a7bc9e9f0..de7abe79ac22d 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/CMakeLists.txt +++ b/boards/arm/stm32/stm32f429i-disco/src/CMakeLists.txt @@ -68,6 +68,10 @@ if(CONFIG_ADC) list(APPEND SRCS stm32_adc.c) endif() +if(CONFIG_STM32_CAN_CHARDRIVER) + list(APPEND SRCS stm32_can.c) +endif() + if(CONFIG_STM32F429I_DISCO_HIGHPRI) list(APPEND SRCS stm32_highpri.c) endif() diff --git a/boards/arm/stm32/stm32f429i-disco/src/Make.defs b/boards/arm/stm32/stm32f429i-disco/src/Make.defs index e9a8a185d667d..e958521d42147 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/Make.defs +++ b/boards/arm/stm32/stm32f429i-disco/src/Make.defs @@ -71,6 +71,10 @@ ifeq ($(CONFIG_ADC),y) CSRCS += stm32_adc.c endif +ifeq ($(CONFIG_STM32_CAN_CHARDRIVER),y) +CSRCS += stm32_can.c +endif + ifeq ($(CONFIG_STM32F429I_DISCO_HIGHPRI),y) CSRCS += stm32_highpri.c endif diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c index c854fb225643f..fbe1ff2a76312 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c +++ b/boards/arm/stm32/stm32f429i-disco/src/stm32_bringup.c @@ -415,6 +415,16 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_STM32_CAN_CHARDRIVER + /* Initialize CAN and register the CAN driver. */ + + ret = stm32_can_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_can_setup failed: %d\n", ret); + } +#endif + UNUSED(ret); return OK; } diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_can.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_can.c new file mode 100644 index 0000000000000..475c754dfa63c --- /dev/null +++ b/boards/arm/stm32/stm32f429i-disco/src/stm32_can.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/arm/stm32/stm32f429i-disco/src/stm32_can.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32.h" +#include "stm32_can.h" +#include "stm32f429i-disco.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +int stm32_can_setup(void) +{ +#if defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2) + struct can_dev_s *can; + int ret; + + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + canerr("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + canerr("ERROR: can_register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h b/boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h index fe4aab9c3dae0..668ca1dc37f13 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h +++ b/boards/arm/stm32/stm32f429i-disco/src/stm32f429i-disco.h @@ -388,5 +388,17 @@ int stm32_pwm_setup(void); int stm32_adc_setup(void); #endif +/**************************************************************************** + * Name: stm32_can_setup + * + * Description: + * Initialize CAN and register the CAN device + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_CAN_CHARDRIVER +int stm32_can_setup(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __BOARDS_ARM_STM32_STM32F429I_DISCO_SRC_STM32F429I_DISCO_H */ diff --git a/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig b/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig index c6d23c5874eb5..4fc11ff50f95d 100644 --- a/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig +++ b/boards/arm/stm32/stm32f4discovery/configs/adb/defconfig @@ -37,6 +37,7 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBUV=y CONFIG_MMCSD=y CONFIG_NSH_ARCHINIT=y @@ -45,6 +46,7 @@ CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=128 CONFIG_NSH_READLINE=y CONFIG_PREALLOC_TIMERS=4 +CONFIG_PSEUDOTERM=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y diff --git a/boards/arm/stm32/stm32f4discovery/src/Make.defs b/boards/arm/stm32/stm32f4discovery/src/Make.defs index 9bfa037602cf0..4db5b7fc3f096 100644 --- a/boards/arm/stm32/stm32f4discovery/src/Make.defs +++ b/boards/arm/stm32/stm32f4discovery/src/Make.defs @@ -88,10 +88,6 @@ ifeq ($(CONFIG_RGBLED),y) CSRCS += stm32_rgbled.c endif -ifeq ($(CONFIG_RTC_DS1307),y) -CSRCS += stm32_ds1307.c -endif - ifeq ($(CONFIG_PWM),y) CSRCS += stm32_pwm.c endif diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c b/boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c index 4a62e0b64a721..125fecee12160 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_bringup.c @@ -76,6 +76,10 @@ #include "stm32_bmp180.h" #endif +#ifdef CONFIG_RTC_DS1307 +#include "stm32_ds1307.h" +#endif + #ifdef CONFIG_SENSORS_MS56XX #include "stm32_ms5611.h" #endif @@ -454,7 +458,7 @@ int stm32_bringup(void) #endif #ifdef CONFIG_RTC_DS1307 - ret = stm32_ds1307_init(); + ret = board_ds1307_initialize(1); if (ret < 0) { syslog(LOG_ERR, "Failed to initialize DS1307 RTC driver: %d\n", ret); diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_ds1307.c b/boards/arm/stm32/stm32f4discovery/src/stm32_ds1307.c deleted file mode 100644 index 713823208ac8a..0000000000000 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_ds1307.c +++ /dev/null @@ -1,113 +0,0 @@ -/**************************************************************************** - * boards/arm/stm32/stm32f4discovery/src/stm32_ds1307.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include -#include -#include - -#include "stm32.h" -#include "stm32_i2c.h" -#include "stm32f4discovery.h" - -#if defined(CONFIG_I2C) && defined(CONFIG_RTC_DS1307) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define DS1307_I2C_ADDR 0x6f /* DS1307 I2C Address */ -#define DS1307_I2C_BUS 1 /* DS1307 is on I2C1 */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: stm32_ds1307_init - * - * Description: - * Initialize and configure the DS1307 RTC - * - ****************************************************************************/ - -int stm32_ds1307_init(void) -{ - struct i2c_master_s *i2c; - static bool initialized = false; - int ret; - - /* Have we already initialized? */ - - if (!initialized) - { - /* No.. Get the I2C bus driver */ - - rtcinfo("Initialize I2C%d\n", DS1307_I2C_BUS); - i2c = stm32_i2cbus_initialize(DS1307_I2C_BUS); - if (!i2c) - { - rtcerr("ERROR: Failed to initialize I2C%d\n", DS1307_I2C_BUS); - return -ENODEV; - } - - /* Now bind the I2C interface to the DS1307 RTC driver */ - - rtcinfo("Bind the DS1307 RTC driver to I2C%d\n", DS1307_I2C_BUS); - ret = dsxxxx_rtc_initialize(i2c); - if (ret < 0) - { - rtcerr("ERROR: Failed to bind I2C%d to the DS1307 RTC driver\n", - DS1307_I2C_BUS); - return -ENODEV; - } - -#ifdef CONFIG_I2C_DRIVER - /* Register the I2C to get the "nsh> i2c bus" command working */ - - ret = i2c_register(i2c, DS1307_I2C_BUS); - if (ret < 0) - { - rtcerr("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); - return -ENODEV; - } -#endif - - /* Synchronize the system time to the RTC time */ - - clock_synchronize(NULL); - - /* Now we are initialized */ - - initialized = true; - } - - return OK; -} - -#endif /* CONFIG_I2C && CONFIG_RTC_DS1307 */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h b/boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h index ab08656198caa..89048910bb339 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h +++ b/boards/arm/stm32/stm32f4discovery/src/stm32f4discovery.h @@ -522,18 +522,6 @@ int nunchuck_initialize(char *devname); int stm32_max7219init(const char *devpath); #endif -/**************************************************************************** - * Name: stm32_ds1307_init - * - * Description: - * Initialize and register the DS1307 RTC - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_DS1307 -int stm32_ds1307_init(void); -#endif - /**************************************************************************** * Name: stm32_st7032init * diff --git a/boards/arm/stm32f7/common/include/stm32_cs4344.h b/boards/arm/stm32f7/common/include/stm32_cs4344.h new file mode 100644 index 0000000000000..e0570c13261a8 --- /dev/null +++ b/boards/arm/stm32f7/common/include/stm32_cs4344.h @@ -0,0 +1,82 @@ +/**************************************************************************** + * boards/arm/stm32f7/common/include/stm32_cs4344.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CS4344_H +#define __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CS4344_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_cs4344_initialize + * + * Description: + * This function is called by platform-specific, setup logic to configure + * and register the CS4344 device. This function will register the driver + * as /dev/audio/pcm[x] where x is determined by the minor device number. + * + * Input Parameters: + * minor - The input device minor number + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_cs4344_initialize(int devno, int port); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __BOARDS_ARM_STM32F7_COMMON_INCLUDE_STM32_CS4344_H */ diff --git a/boards/arm/stm32f7/common/src/CMakeLists.txt b/boards/arm/stm32f7/common/src/CMakeLists.txt index 86cbaf93dd423..f2b17e2c09807 100644 --- a/boards/arm/stm32f7/common/src/CMakeLists.txt +++ b/boards/arm/stm32f7/common/src/CMakeLists.txt @@ -28,4 +28,8 @@ if(CONFIG_SENSORS_BMI270_I2C) list(APPEND SRCS stm32_bmi270.c) endif() +if(CONFIG_AUDIO_CS4344) + list(APPEND SRCS stm32_cs4344.c) +endif() + target_sources(board PRIVATE ${SRCS}) diff --git a/boards/arm/stm32f7/common/src/Make.defs b/boards/arm/stm32f7/common/src/Make.defs index 810fd6e833231..ae0d1bfe73c9e 100644 --- a/boards/arm/stm32f7/common/src/Make.defs +++ b/boards/arm/stm32f7/common/src/Make.defs @@ -28,6 +28,10 @@ ifeq ($(CONFIG_SENSORS_BMI270_I2C),y) CSRCS += stm32_bmi270.c endif +ifeq ($(CONFIG_AUDIO_CS4344),y) + CSRCS += stm32_cs4344.c +endif + DEPPATH += --dep-path src VPATH += :src CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src diff --git a/boards/arm/stm32f7/common/src/stm32_cs4344.c b/boards/arm/stm32f7/common/src/stm32_cs4344.c new file mode 100644 index 0000000000000..221cc7fd69319 --- /dev/null +++ b/boards/arm/stm32f7/common/src/stm32_cs4344.c @@ -0,0 +1,168 @@ +/**************************************************************************** + * boards/arm/stm32f7/common/src/stm32_cs4344.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +#include "stm32_i2s.h" +#include "stm32_pwr.h" +#include "stm32_rcc.h" + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_cs4344_initialize + * + * Description: + * This function is called by platform-specific, setup logic to configure + * and register the CS4344 device. This function will register the driver + * as /dev/audio/pcm[x] where x is determined by the minor device number. + * + * Input Parameters: + * minor - The input device minor number + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_cs4344_initialize(int devno, int port) +{ + struct audio_lowerhalf_s *cs4344; + struct audio_lowerhalf_s *pcm; + struct i2s_dev_s *i2s; + static bool initialized = false; + char devname[12]; + int ret; + + audinfo("minor %d\n", devno); + DEBUGASSERT(devno >= 0 && devno <= 25); + + /* Have we already initialized? Since we never uninitialize we must + * prevent multiple initializations. This is necessary, for example, + * when the touchscreen example is used as a built-in application in + * NSH and can be called numerous time. It will attempt to initialize + * each time. + */ + + if (!initialized) + { + /* Get an instance of the I2S interface for the CS4344 data channel */ + + i2s = stm32_i2sbus_initialize(port); + if (!i2s) + { + auderr("ERROR: Failed to initialize I2S%d\n", port); + ret = -ENODEV; + goto errout; + } + + /* Now we can use this I2S interface to initialize the CS4344 which + * will return an audio interface. + */ + + cs4344 = cs4344_initialize(i2s); + if (!cs4344) + { + auderr("ERROR: Failed to initialize the CS4344\n"); + ret = -ENODEV; + goto errout; + } + + /* No we can embed the CS4344/I2S conglomerate into a PCM decoder + * instance so that we will have a PCM front end for the the CS4344 + * driver. + */ + + pcm = pcm_decode_initialize(cs4344); + if (!pcm) + { + auderr("ERROR: Failed create the PCM decoder\n"); + ret = -ENODEV; + goto errout; + } + + /* Create a device name */ + + snprintf(devname, 12, "pcm%d", devno); + + /* Finally, we can register the PCM/CS4344/I2S audio device. + * + * Is anyone young enough to remember Rube Goldberg? + */ + + ret = audio_register(devname, pcm); + if (ret < 0) + { + auderr("ERROR: Failed to register /dev/%s device: %d\n", + devname, ret); + goto errout; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; + +errout: + return ret; +} + diff --git a/boards/arm/stm32f7/nucleo-144/configs/f722-can/Make.defs b/boards/arm/stm32f7/nucleo-144/configs/f722-can/Make.defs index 1978eced609ca..d8197ae04dab6 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f722-can/Make.defs +++ b/boards/arm/stm32f7/nucleo-144/configs/f722-can/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f7/nucleo-144/configs/f746-can/Make.defs +# boards/arm/stm32f7/nucleo-144/configs/f722-can/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm/stm32f7/nucleo-144/configs/f722-cansock/Make.defs b/boards/arm/stm32f7/nucleo-144/configs/f722-cansock/Make.defs index cf600c7fa135c..7f82a0478fc81 100644 --- a/boards/arm/stm32f7/nucleo-144/configs/f722-cansock/Make.defs +++ b/boards/arm/stm32f7/nucleo-144/configs/f722-cansock/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32f7/nucleo-144/configs/f746-cansock/Make.defs +# boards/arm/stm32f7/nucleo-144/configs/f722-cansock/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c b/boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c index 6fdec397f736a..f6232ea0a82c9 100644 --- a/boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c +++ b/boards/arm/stm32f7/nucleo-144/src/stm32_bbsram.c @@ -136,7 +136,7 @@ typedef struct #if CONFIG_ARCH_INTERRUPTSTACK > 3 _stack_t interrupt; #endif -} stack_t; +} stacks_t; /* Not Used for reference only */ @@ -237,7 +237,7 @@ typedef struct int lineno; /* __LINE__ to up_assert */ int pid; /* Process ID */ uint32_t regs[XCPTCONTEXT_REGS]; /* Interrupt register save area */ - stack_t stacks; /* Stack info */ + stacks_t stacks; /* Stack info */ #if CONFIG_TASK_NAME_SIZE > 0 char name[CONFIG_TASK_NAME_SIZE + 1]; /* Task name (with NULL * terminator) */ diff --git a/boards/arm/stm32f7/stm32f746g-disco/CMakeLists.txt b/boards/arm/stm32f7/stm32f746g-disco/CMakeLists.txt index ccb967cadddf2..d8031b208bf6d 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f746g-disco/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f7/stm32f746-disco/CMakeLists.txt +# boards/arm/stm32f7/stm32f746g-disco/CMakeLists.txt # # Licensed to the Apache Software Foundation (ASF) under one or more contributor # license agreements. See the NOTICE file distributed with this work for diff --git a/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig b/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig index dcf4cae4f61c6..140a8dc6b0d9f 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig +++ b/boards/arm/stm32f7/stm32f746g-disco/configs/lvgl/defconfig @@ -42,13 +42,13 @@ CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INPUT=y CONFIG_INPUT_FT5X06=y CONFIG_INTELHEX_BINARY=y -CONFIG_LV_MEM_CUSTOM=y -CONFIG_LV_PORT_USE_FBDEV=y -CONFIG_LV_PORT_USE_TOUCHPAD=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y CONFIG_LV_USE_DEMO_WIDGETS=y CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y CONFIG_MM_REGIONS=3 CONFIG_MQ_MAXMSGSIZE=256 CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt b/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt index e9c06610bef13..bd901ee506f41 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f7/stm32f746-disco/src/CMakeLists.txt +# boards/arm/stm32f7/stm32f746g-disco/src/CMakeLists.txt # # Licensed to the Apache Software Foundation (ASF) under one or more contributor # license agreements. See the NOTICE file distributed with this work for @@ -27,7 +27,7 @@ else() endif() if(CONFIG_ARCH_BUTTONS) - list(APPEND SRCS stm32_buttons.c) + list(APPEND SRCS stm32_buttons.c) endif() if(CONFIG_BOARDCTL) diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/CMakeLists.txt b/boards/arm/stm32f7/stm32f777zit6-meadow/CMakeLists.txt index 0369a5aa12768..b9c4f5461b4cf 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/CMakeLists.txt @@ -1,21 +1,21 @@ -############################################################################ -# boards/arm/stm32f7/stm32f77zit6-meadow/CMakeLists.txt +# ############################################################################## +# boards/arm/stm32f7/stm32f777zit6-meadow/CMakeLists.txt # -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at # -# http://www.apache.org/licenses/LICENSE-2.0 +# http://www.apache.org/licenses/LICENSE-2.0 # # Unless required by applicable law or agreed to in writing, software # distributed under the License is distributed on an "AS IS" BASIS, WITHOUT # WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. +# License for the specific language governing permissions and limitations under +# the License. # -############################################################################ +# ############################################################################## add_subdirectory(src) diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig new file mode 100644 index 0000000000000..e2286b77cfcce --- /dev/null +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/configs/i2s/defconfig @@ -0,0 +1,113 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="stm32f777zit6-meadow" +CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y +CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP_STM32F777ZI=y +CONFIG_ARCH_CHIP_STM32F7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_AUDIO=y +CONFIG_AUDIO_CS4344=y +CONFIG_AUDIO_EXCLUDE_TONE=y +CONFIG_AUDIO_EXCLUDE_VOLUME=y +CONFIG_AUDIO_I2S=y +CONFIG_BCH=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_PRODUCTID=0x0001 +CONFIG_CDCACM_PRODUCTSTR="Wilderness Labs" +CONFIG_CDCACM_VENDORID=0x2E6A +CONFIG_CDCACM_VENDORSTR="Meadow F7 Micro" +CONFIG_CRYPTO=y +CONFIG_CRYPTO_RANDOM_POOL=y +CONFIG_DEBUG_AUDIO=y +CONFIG_DEBUG_AUDIO_ERROR=y +CONFIG_DEBUG_AUDIO_INFO=y +CONFIG_DEBUG_AUDIO_WARN=y +CONFIG_DEBUG_DMA=y +CONFIG_DEBUG_DMA_ERROR=y +CONFIG_DEBUG_DMA_INFO=y +CONFIG_DEBUG_DMA_WARN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_I2S=y +CONFIG_DEBUG_I2S_ERROR=y +CONFIG_DEBUG_I2S_INFO=y +CONFIG_DEBUG_I2S_WARN=y +CONFIG_DEBUG_SCHED=y +CONFIG_DEBUG_SCHED_ERROR=y +CONFIG_DEBUG_SCHED_WARN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_URANDOM=y +CONFIG_DEV_URANDOM_RANDOM_POOL=y +CONFIG_DRIVERS_AUDIO=y +CONFIG_FS_PROCFS=y +CONFIG_FS_TMPFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2S=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_MEMFD_ERROR=y +CONFIG_MM_REGIONS=3 +CONFIG_MTD=y +CONFIG_MTD_BYTE_WRITE=y +CONFIG_MTD_PARTITION=y +CONFIG_MTD_SECT512=y +CONFIG_MTD_W25QXXXJV=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFCONFIG=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_DISABLE_PS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=14 +CONFIG_STM32F7_DMA1=y +CONFIG_STM32F7_I2S2=y +CONFIG_STM32F7_I2S2_MCK=y +CONFIG_STM32F7_I2S2_TX=y +CONFIG_STM32F7_OTGFS=y +CONFIG_STM32F7_QSPI_POLLING=y +CONFIG_STM32F7_QUADSPI=y +CONFIG_STM32F7_USART1=y +CONFIG_SYSLOG_DEFAULT=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS1" +CONFIG_SYSLOG_MAX_CHANNELS=2 +CONFIG_SYSTEM_FLASH_ERASEALL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NXPLAYER=y +CONFIG_SYSTEM_ZMODEM=y +CONFIG_SYSTEM_ZMODEM_PKTBUFSIZE=1024 +CONFIG_SYSTEM_ZMODEM_RCVBUFSIZE=1024 +CONFIG_SYSTEM_ZMODEM_SNDBUFSIZE=1024 +CONFIG_TASK_NAME_SIZE=64 +CONFIG_USBDEV=y +CONFIG_W25QXXXJV_QSPI_FREQUENCY=64000000 diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h index 9c054cd020149..b54790dd58fa8 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/include/board.h @@ -152,6 +152,13 @@ #define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) #define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2) +/* SAIx input frequency = 25 / M * N / Q / P + * 25000000 / 25 * 384 / 2 / 8 + */ + +#define STM32F7_SAI1_FREQUENCY (49142857) +#define STM32F7_SAI2_FREQUENCY (49142857) + /* Configure Dedicated Clock Configuration Register */ #define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1) @@ -163,12 +170,13 @@ #define STM32_RCC_DCKCFGR1_DFSDM1SRC 0 #define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0 -/* Configure factors for PLLI2S clock */ +/* Configure factors for PLLI2S clock */ +#define CONFIG_STM32F7_PLLI2S 1 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) -#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) -#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) -#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2) +#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(4) +#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(4) +#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(4) /* Configure Dedicated Clock Configuration Register 2 */ @@ -377,6 +385,10 @@ /* DMA Channel/Stream Selections ********************************************/ +#define DMACHAN_SAI2_A DMAMAP_SAI2_A +#define DMACHAN_SAI2_B DMAMAP_SAI2_B +#define DMACHAN_SAI1_B DMAMAP_SAI1_B + /* SDMMC */ /* Stream selections are arbitrary for now but might become important in the @@ -470,6 +482,25 @@ #define GPIO_I2C1_SCL (GPIO_I2C1_SCL_1|GPIO_SPEED_50MHz) #define GPIO_I2C1_SDA (GPIO_I2C1_SDA_1|GPIO_SPEED_50MHz) +/* Dumb definition to SPI2, just because it is needed by i2s driver */ + +#define GPIO_SPI2_SCK GPIO_SPI2_SCK_5 +#define GPIO_SPI2_MISO GPIO_SPI2_MISO_3 +#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_3 + +#define DMAMAP_SPI2_TX DMAMAP_SPI2_TX_2 +#define DMAMAP_SPI2_RX DMAMAP_SPI2_RX_2 + +/* I2S2 - CS4344 configuration uses I2S2 */ + +#define GPIO_I2S2_SD (GPIO_I2S2_SD_1) /* PB15 */ +#define GPIO_I2S2_CK (GPIO_I2S2_CK_3) /* PB13 */ +#define GPIO_I2S2_WS (GPIO_I2S2_WS_1) /* PB12 */ +#define GPIO_I2S2_MCK (GPIO_I2S2_MCK_0) /* PC6 */ + +#define DMACHAN_I2S2_RX DMAMAP_SPI2_RX_2 +#define DMACHAN_I2S2_TX DMAMAP_SPI2_TX_2 + /* QSPI Mapping */ #define GPIO_QSPI_CS (GPIO_QUADSPI_BK1_NCS_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz) diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt b/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt index 34786323b8981..bd527f27e1ef1 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/stm32f7/stm32f77zit6-meadow/src/CMakeLists.txt +# boards/arm/stm32f7/stm32f777zit6-meadow/src/CMakeLists.txt # # Licensed to the Apache Software Foundation (ASF) under one or more contributor # license agreements. See the NOTICE file distributed with this work for diff --git a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_bringup.c b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_bringup.c index 7c0b50331efab..601233061b33b 100644 --- a/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_bringup.c +++ b/boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_bringup.c @@ -32,6 +32,15 @@ #include #include +#include + +#ifdef CONFIG_AUDIO_CS4344 +# include "stm32_cs4344.h" +#endif + +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_rcc.h" #include "stm32f777zit6-meadow.h" @@ -139,6 +148,16 @@ int stm32_bringup(void) } #endif +#ifdef CONFIG_AUDIO_CS4344 + /* Configure CS4344 audio as /dev/pcm0 on I2S2 */ + + ret = board_cs4344_initialize(1, 2); + if (ret != OK) + { + syslog(LOG_ERR, "Failed to initialize CS4344 audio: %d\n", ret); + } +#endif + #ifdef CONFIG_BOARD_MEADOW_F7_CORE_COMPUTE /* Initialize all devices in the F7 Core Compute */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig new file mode 100644 index 0000000000000..374dbe6f4ff69 --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/buzzer/defconfig @@ -0,0 +1,61 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="linum-stm32h753bi" +CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H753BI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_EXAMPLES_PWM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MM_REGIONS=4 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_PWR=y +CONFIG_STM32H7_RTC=y +CONFIG_STM32H7_TIM4=y +CONFIG_STM32H7_TIM4_CH2OUT=y +CONFIG_STM32H7_TIM4_CHANNEL=2 +CONFIG_STM32H7_TIM4_PWM=y +CONFIG_STM32H7_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig new file mode 100644 index 0000000000000..8b7973c831543 --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/eeprom/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="linum-stm32h753bi" +CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H753BI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_ZERO=y +CONFIG_EEPROM=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FS_PROCFS=y +CONFIG_I2C=y +CONFIG_I2C_EE_24XX=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MM_REGIONS=4 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_I2C3=y +CONFIG_STM32H7_PWR=y +CONFIG_STM32H7_RTC=y +CONFIG_STM32H7_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig new file mode 100644 index 0000000000000..51cbb6195554b --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/leds/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_QUOTE is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="linum-stm32h753bi" +CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H753BI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_EXAMPLES_LEDS=y +CONFIG_EXAMPLES_LEDS_LEDSET=0x07 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MM_REGIONS=4 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_PWR=y +CONFIG_STM32H7_RTC=y +CONFIG_STM32H7_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USERLED=y +CONFIG_USERLED_LOWER=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig new file mode 100644 index 0000000000000..8cf685d943354 --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/littlefs/defconfig @@ -0,0 +1,69 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_QUOTE is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="linum-stm32h753bi" +CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H753BI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_TASK_STACKSIZE=4096 +CONFIG_EXAMPLES_ALARM=y +CONFIG_EXAMPLES_ALARM_STACKSIZE=2048 +CONFIG_FS_LITTLEFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MM_DEFAULT_ALIGNMENT=4 +CONFIG_MM_REGIONS=4 +CONFIG_MTD=y +CONFIG_MTD_W25QXXXJV=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=2048 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +CONFIG_RAMMTD=y +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_PWR=y +CONFIG_STM32H7_QSPI_INTERRUPTS=y +CONFIG_STM32H7_QUADSPI=y +CONFIG_STM32H7_RTC=y +CONFIG_STM32H7_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_STACKSIZE=2048 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_W25QXXXJV_QSPI_FREQUENCY=50000000 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig new file mode 100644 index 0000000000000..058d12e7b4769 --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/modbus_master/defconfig @@ -0,0 +1,79 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MB_MASTER_FUNC_READWRITE_HOLDING_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_READ_COILS_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_READ_DISCRETE_INPUTS_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_READ_INPUT_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_WRITE_COIL_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_WRITE_HOLDING_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_WRITE_MULTIPLE_COILS_ENABLED is not set +# CONFIG_MB_MASTER_FUNC_WRITE_MULTIPLE_HOLDING_ENABLED is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="linum-stm32h753bi" +CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H753BI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_EXAMPLES_MODBUSMASTER=y +CONFIG_EXAMPLES_MODBUSMASTER_PORT=2 +CONFIG_EXAMPLES_MODBUSMASTER_PROGNAME="mbmaster" +CONFIG_EXAMPLES_MODBUSMASTER_SLAVEADDR=10 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MB_PORT_HAS_CLOSE=y +CONFIG_MB_RTU_MASTER=y +CONFIG_MM_REGIONS=4 +CONFIG_MODBUS=y +CONFIG_MODBUS_MASTER=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_PWR=y +CONFIG_STM32H7_RTC=y +CONFIG_STM32H7_UART4=y +CONFIG_STM32H7_USART1=y +CONFIG_STM32H7_USART6=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_UART4_BAUD=38400 +CONFIG_UART4_PARITY=2 +CONFIG_UART4_RS485=y +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART6_BAUD=38400 +CONFIG_USART6_PARITY=2 +CONFIG_USART6_RS485=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig new file mode 100644 index 0000000000000..cbf7d7b38d258 --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/netnsh/defconfig @@ -0,0 +1,92 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="linum-stm32h753bi" +CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H753BI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETH0_PHY_KSZ8081=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=4096 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MM_REGIONS=4 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x08080808 +CONFIG_NETDEV_PHY_DEBUG=y +CONFIG_NETDEV_WORK_THREAD=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0x08080808 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_DISCOVER=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_ARP_SEND=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1500 +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_IGMP=y +CONFIG_NET_ROUTE=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_ETHMAC=y +CONFIG_STM32H7_PHYSR=30 +CONFIG_STM32H7_PHYSR_100FD=0x6 +CONFIG_STM32H7_PHYSR_100HD=0x2 +CONFIG_STM32H7_PHYSR_10FD=0x5 +CONFIG_STM32H7_PHYSR_10HD=0x1 +CONFIG_STM32H7_PHYSR_ALTCONFIG=y +CONFIG_STM32H7_PHYSR_ALTMODE=0x7 +CONFIG_STM32H7_PWR=y +CONFIG_STM32H7_RMII_MCO1=y +CONFIG_STM32H7_RTC=y +CONFIG_STM32H7_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/nshusb/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/nshusb/defconfig new file mode 100644 index 0000000000000..57c87d06057ab --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/nshusb/defconfig @@ -0,0 +1,61 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="linum-stm32h753bi" +CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H753BI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MM_REGIONS=4 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_OTG_ID_GPIO_DISABLE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_HSI48=y +CONFIG_STM32H7_OTGFS=y +CONFIG_STM32H7_PWR=y +CONFIG_STM32H7_RTC=y +CONFIG_STM32H7_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig new file mode 100644 index 0000000000000..83bd1eec47f51 --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/nxffs/defconfig @@ -0,0 +1,66 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_QUOTE is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="linum-stm32h753bi" +CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H753BI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FS_NXFFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MM_DEFAULT_ALIGNMENT=4 +CONFIG_MM_REGIONS=4 +CONFIG_MTD=y +CONFIG_MTD_W25QXXXJV=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMMTD=y +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_PWR=y +CONFIG_STM32H7_QSPI_INTERRUPTS=y +CONFIG_STM32H7_QUADSPI=y +CONFIG_STM32H7_RTC=y +CONFIG_STM32H7_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_NXFFS=y +CONFIG_TESTING_NXFFS_MOUNTPT="/mnt" +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_W25QXXXJV_QSPI_FREQUENCY=50000000 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig new file mode 100644 index 0000000000000..88c018f8bfc03 --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/rndis/defconfig @@ -0,0 +1,84 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="linum-stm32h753bi" +CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H753BI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FS_PROCFS=y +CONFIG_FS_TMPFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=4096 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_MEMFD_ERROR=y +CONFIG_LIBM=y +CONFIG_MM_REGIONS=4 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_NETCAT=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ARP_SEND=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_OTG_ID_GPIO_DISABLE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RNDIS=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_HSI48=y +CONFIG_STM32H7_OTGFS=y +CONFIG_STM32H7_PWR=y +CONFIG_STM32H7_RTC=y +CONFIG_STM32H7_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig new file mode 100644 index 0000000000000..cb14cb156de85 --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdcard/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="linum-stm32h753bi" +CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H753BI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FAT_DMAMEMORY=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_GRAN=y +CONFIG_GRAN_INTR=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=4096 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE=y +CONFIG_MM_REGIONS=4 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDMMC1_SDIO_MODE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_HSI48=y +CONFIG_STM32H7_PWR=y +CONFIG_STM32H7_RTC=y +CONFIG_STM32H7_SDMMC1=y +CONFIG_STM32H7_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig new file mode 100644 index 0000000000000..9d1f5f4b4c401 --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/socketcan/defconfig @@ -0,0 +1,72 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NET_ETHERNET is not set +# CONFIG_NET_IPv4 is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ALLOW_GPL_COMPONENTS=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="linum-stm32h753bi" +CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H753BI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_CANUTILS_CANDUMP=y +CONFIG_CANUTILS_CANSEND=y +CONFIG_CAN_PREALLOC_CONNS=2 +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_NET=y +CONFIG_DEBUG_NET_ERROR=y +CONFIG_DEBUG_NET_INFO=y +CONFIG_DEBUG_NET_WARN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=4 +CONFIG_NET=y +CONFIG_NETDEV_CAN_BITRATE_IOCTL=y +CONFIG_NETDEV_IFINDEX=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NET_CAN=y +CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE=500 +CONFIG_NET_CAN_RAW_TX_DEADLINE=y +CONFIG_NET_CAN_SOCK_OPTS=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAMLOG_SYSLOG=y +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_FDCAN1=y +CONFIG_STM32H7_FDCAN2=y +CONFIG_STM32H7_USART1=y +CONFIG_SYSLOG_TIMESTAMP=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig new file mode 100644 index 0000000000000..463f65b5e8c3c --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/usbmsc-sdcard/defconfig @@ -0,0 +1,77 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_SDMMC_IDMA is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="linum-stm32h753bi" +CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H753BI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FAT_DMAMEMORY=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_GRAN=y +CONFIG_GRAN_INTR=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=4096 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE=y +CONFIG_MM_REGIONS=4 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_OTG_ID_GPIO_DISABLE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDMMC1_SDIO_MODE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_HSI48=y +CONFIG_STM32H7_OTGFS=y +CONFIG_STM32H7_PWR=y +CONFIG_STM32H7_RTC=y +CONFIG_STM32H7_SDMMC1=y +CONFIG_STM32H7_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_USBMSC=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USBDEV=y +CONFIG_USBMSC=y +CONFIG_USBMSC_REMOVABLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig new file mode 100644 index 0000000000000..9b2cd50f1af2a --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/zmodem/defconfig @@ -0,0 +1,82 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="linum-stm32h753bi" +CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H753BI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FAT_DMAMEMORY=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_TMPFS=y +CONFIG_GRAN=y +CONFIG_GRAN_INTR=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=4096 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_MEMFD_ERROR=y +CONFIG_LIBM=y +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE=y +CONFIG_MM_REGIONS=4 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_OTG_ID_GPIO_DISABLE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SDMMC1_SDIO_MODE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_HSI48=y +CONFIG_STM32H7_OTGFS=y +CONFIG_STM32H7_PWR=y +CONFIG_STM32H7_RTC=y +CONFIG_STM32H7_SDMMC1=y +CONFIG_STM32H7_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_ZMODEM=y +CONFIG_SYSTEM_ZMODEM_PKTBUFSIZE=1024 +CONFIG_SYSTEM_ZMODEM_RCVBUFSIZE=1024 +CONFIG_SYSTEM_ZMODEM_SNDBUFSIZE=1024 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h index fae9926bc5e80..1568e8ff31d70 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h +++ b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h @@ -88,7 +88,7 @@ /* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR * - * PLL1_VCO = (25,000,000 / 5) * 192 = 960 MHz + * PLL1_VCO = (25 MHz / 5) * 192 = 960 MHz * * PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 480 MHz * PLL1Q = PLL1_VCO/4 = 800 MHz / 4 = 240 MHz @@ -100,32 +100,42 @@ RCC_PLLCFGR_DIVP1EN | \ RCC_PLLCFGR_DIVQ1EN | \ RCC_PLLCFGR_DIVR1EN) -#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(5) -#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(192) -#define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2) -#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4) -#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(4) #define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 5) * 192) #define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2) #define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4) #define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 4) -/* PLL2 */ +#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(5) +#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(192) +#define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2) +#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4) +#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(4) +/* PLL2, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR + * + * PLL1_VCO = (25 MHz / 2) * 48 = 600 MHz + * + * PLL2P = PLL2_VCO/2 = 600 MHz / 8 = 75 MHz + * PLL2Q = PLL2_VCO/4 = 600 MHz / 40 = 15 MHz + * PLL2R = PLL2_VCO/8 = 600 MHz / 3 = 200 MHz + */ #define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE | \ RCC_PLLCFGR_PLL2RGE_4_8_MHZ | \ - RCC_PLLCFGR_DIVP2EN) -#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(2) -#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(48) -#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(8) -#define STM32_PLLCFG_PLL2Q 1 -#define STM32_PLLCFG_PLL2R 3 + RCC_PLLCFGR_DIVP2EN | \ + RCC_PLLCFGR_DIVQ2EN | \ + RCC_PLLCFGR_DIVR2EN ) #define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 48) #define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 8) -#define STM32_PLL2Q_FREQUENCY -#define STM32_PLL2R_FREQUENCY +#define STM32_PLL2Q_FREQUENCY (STM32_VCO2_FREQUENCY / 40) +#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FREQUENCY / 3) + +#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(2) +#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(48) +#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(8) +#define STM32_PLLCFG_PLL2Q RCC_PLL2DIVR_Q2(40) +#define STM32_PLLCFG_PLL2R RCC_PLL2DIVR_R2(3) /* PLL3 */ @@ -258,31 +268,19 @@ /* SDMMC definitions ********************************************************/ -/* Init 400kHz, PLL1Q/(2*250) */ +/* Init 400 kHz, PLL1Q/(2*300) = 240 MHz / (2*300) = 400 Khz */ -#define STM32_SDMMC_INIT_CLKDIV (250 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_INIT_CLKDIV (300 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -/* Just set these to 25 MHz for now, - * PLL1Q/(2*4), for default speed 12.5MB/s +/* Just set these to 24 MHz for now, + * PLL1Q/(2*5) = 240 MHz / (2*5) = 24 MHz */ -#define STM32_SDMMC_MMCXFR_CLKDIV (4 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -#define STM32_SDMMC_SDXFR_CLKDIV (4 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_MMCXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_SDXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE -/* Ethernet definitions *****************************************************/ - -#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2 | GPIO_SPEED_100MHz) /* PG13 */ -#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1 | GPIO_SPEED_100MHz) /* PB13 */ -#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2 | GPIO_SPEED_100MHz) /* PG11 */ -#define GPIO_ETH_MDC (GPIO_ETH_MDC_0 | GPIO_SPEED_100MHz) /* PC1 */ -#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0 | GPIO_SPEED_100MHz) /* PA2 */ -#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0 | GPIO_SPEED_100MHz) /* PC4 */ -#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0 | GPIO_SPEED_100MHz) /* PC5 */ -#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0 | GPIO_SPEED_100MHz) /* PA7 */ -#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0 | GPIO_SPEED_100MHz) /* PA1 */ - /* LED definitions **********************************************************/ /* The board has 1 user LED RGB that could be used this diagnostic LED too. @@ -379,85 +377,67 @@ #endif -/* I2C4 - Used by Touchscreen and Audio Codec */ - -#define GPIO_I2C4_SCL (GPIO_I2C4_SCL_1 | GPIO_SPEED_50MHz) /* PD12 */ -#define GPIO_I2C4_SDA (GPIO_I2C4_SDA_1 | GPIO_SPEED_50MHz) /* PD13 */ - -/* LTDC */ - -#define GPIO_LTDC_R0 (GPIO_LTDC_R0_3 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_R1 (GPIO_LTDC_R1_3 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_R2 (GPIO_LTDC_R2_4 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_R3 (GPIO_LTDC_R3_3 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_R4 (GPIO_LTDC_R4_4 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_R5 (GPIO_LTDC_R5_4 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_R6 (GPIO_LTDC_R6_4 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_R7 (GPIO_LTDC_R7_3 | GPIO_SPEED_100MHz) - -#define GPIO_LTDC_G0 (GPIO_LTDC_G0_2 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_G1 (GPIO_LTDC_G1_2 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_G2 (GPIO_LTDC_G2_3 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_G3 (GPIO_LTDC_G3_4 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_G4 (GPIO_LTDC_G4_3 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_G5 (GPIO_LTDC_G5_3 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_G6 (GPIO_LTDC_G6_3 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_G7 (GPIO_LTDC_G7_3 | GPIO_SPEED_100MHz) - -#define GPIO_LTDC_B0 (GPIO_LTDC_B0_1 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_B1 (GPIO_LTDC_B1_2 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_B2 (GPIO_LTDC_B2_3 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_B3 (GPIO_LTDC_B3_3 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_B4 (GPIO_LTDC_B4_4 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_B5 (GPIO_LTDC_B5_3 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_B6 (GPIO_LTDC_B6_3 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_B7 (GPIO_LTDC_B7_3 | GPIO_SPEED_100MHz) +/* OTGFS */ -#define GPIO_LTDC_VSYNC (GPIO_LTDC_VSYNC_3 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_HSYNC (GPIO_LTDC_HSYNC_3 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_DE (GPIO_LTDC_DE_3 | GPIO_SPEED_100MHz) -#define GPIO_LTDC_CLK (GPIO_LTDC_CLK_3 | GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0 | GPIO_SPEED_100MHz) /* PA11 */ +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0 | GPIO_SPEED_100MHz) /* PA12 */ -/* DMA **********************************************************************/ +/* SDMMC1 - Used SD Card memory */ -#define DMAMAP_SPI3_RX DMAMAP_DMA12_SPI3RX_0 /* DMA1 */ -#define DMAMAP_SPI3_TX DMAMAP_DMA12_SPI3TX_0 /* DMA1 */ +#define GPIO_SDMMC1_CK (GPIO_SDMMC1_CK_0 | GPIO_SPEED_100MHz) /* PC12 */ +#define GPIO_SDMMC1_CMD (GPIO_SDMMC1_CMD_0 | GPIO_SPEED_100MHz) /* PD2 */ +#define GPIO_SDMMC1_D0 (GPIO_SDMMC1_D0_0 | GPIO_SPEED_100MHz) /* PC8 */ +#define GPIO_SDMMC1_D1 (GPIO_SDMMC1_D1_0 | GPIO_SPEED_100MHz) /* PC9 */ +#define GPIO_SDMMC1_D2 (GPIO_SDMMC1_D2_0 | GPIO_SPEED_100MHz) /* PC10 */ +#define GPIO_SDMMC1_D3 (GPIO_SDMMC1_D3_0 | GPIO_SPEED_100MHz) /* PC11 */ -/* LCD definitions */ +/* I2C3 - Used by eeprom memory */ -#define BOARD_LTDC_WIDTH 480 -#define BOARD_LTDC_HEIGHT 272 +#define GPIO_I2C3_SCL (GPIO_I2C3_SCL_2 | GPIO_SPEED_100MHz) /* PH7 */ +#define GPIO_I2C3_SDA (GPIO_I2C3_SDA_2 | GPIO_SPEED_100MHz) /* PH8 */ -#define BOARD_LTDC_OUTPUT_BPP 24 -#define BOARD_LTDC_HFP 32 -#define BOARD_LTDC_HBP 13 -#define BOARD_LTDC_VFP 2 -#define BOARD_LTDC_VBP 2 -#define BOARD_LTDC_HSYNC 41 -#define BOARD_LTDC_VSYNC 10 +/* PWM - Buzzer */ -#define BOARD_LTDC_PLLSAIN 192 -#define BOARD_LTDC_PLLSAIR 5 +#define GPIO_TIM17_CH1OUT (GPIO_TIM17_CH1NOUT_1) /* PB7 */ +#define GPIO_TIM4_CH2OUT (GPIO_TIM4_CH2OUT_1) /* PB7 */ -/* Pixel Clock Polarity */ +/* FDCAN1 */ -#define BOARD_LTDC_GCR_PCPOL 0 /* !LTDC_GCR_PCPOL */ +#define GPIO_CAN1_RX (GPIO_CAN1_RX_3|GPIO_SPEED_50MHz) /* PD0 */ +#define GPIO_CAN1_TX (GPIO_CAN1_TX_3|GPIO_SPEED_50MHz) /* PD1 */ -/* Data Enable Polarity */ +/* FDCAN2 */ -#define BOARD_LTDC_GCR_DEPOL 0 /* !LTDC_GCR_DEPOL */ +#define GPIO_CAN2_RX (GPIO_CAN2_RX_2|GPIO_SPEED_50MHz) /* PB5 - D11 */ +#define GPIO_CAN2_TX (GPIO_CAN2_TX_2|GPIO_SPEED_50MHz) /* PB6 - D1 */ -/* Vertical Sync Polarity */ +/* QSPI Mapping */ -#define BOARD_LTDC_GCR_VSPOL 0 /* !LTDC_GCR_VSPOL */ +#define GPIO_QSPI_CS (GPIO_QUADSPI_BK1_NCS_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz) /* PG6 */ +#define GPIO_QSPI_IO0 (GPIO_QUADSPI_BK1_IO0_1 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz) /* PF8 */ +#define GPIO_QSPI_IO1 (GPIO_QUADSPI_BK1_IO1_1 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz) /* PF9 */ +#define GPIO_QSPI_IO2 (GPIO_QUADSPI_BK1_IO2_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz) /* PF7 */ +#define GPIO_QSPI_IO3 (GPIO_QUADSPI_BK1_IO3_3 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz) /* PF6 */ +#define GPIO_QSPI_SCK (GPIO_QUADSPI_CLK_2 | GPIO_FLOAT | GPIO_PUSHPULL | GPIO_SPEED_100MHz) /* PF10 */ -/* Horizontal Sync Polarity */ +/* Select PLL2R to source clock of QSPI */ +#define BOARD_QSPI_CLK RCC_D1CCIPR_QSPISEL_PLL2 -#define BOARD_LTDC_GCR_HSPOL 0 /* !LTDC_GCR_HSPOL */ +/* Ethernet */ -/* GPIO pinset */ +#define BOARD_CFGR_MC01_SOURCE (RCC_CFGR_MCO1_HSE) +#define BOARD_CFGR_MC01_DIVIDER (RCC_CFGR_MCO1PRE(0)) +#define GPIO_MCO1 (GPIO_MCO1_0) /* PA8 */ -#define GPIO_LTDC_PINS 24 /* 24-bit display */ +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) /* PC1 */ +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) /* PA2 */ +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) /* PA7 */ +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) /* PA1 */ +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) /* PC4 */ +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) /* PC5 */ +#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2|GPIO_SPEED_100MHz) /* PG13 */ +#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_3|GPIO_SPEED_100MHz) /* PG14 */ +#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) /* PG11 */ /**************************************************************************** * Public Data diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt b/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt index f086c2a93b92a..89d40328adf9e 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/CMakeLists.txt @@ -32,6 +32,34 @@ if(CONFIG_BOARDCTL) list(APPEND SRCS stm32_appinitialize.c) endif() +if(CONFIG_STM32H7_OTGFS) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_STM32H7_SDMMC) + list(APPEND SRCS stm32_sdmmc.c) +endif() + +if(CONFIG_FAT_DMAMEMORY) + list(APPEND SRCS stm32_dma_alloc.c) +endif() + +if(CONFIG_I2C_EE_24XX) + list(APPEND SRCS stm32_at24.c) +endif() + +if(CONFIG_PWM) + list(APPEND SRCS stm32_pwm.c) +endif() + +if(CONFIG_MTD_W25QXXXJV) + list(APPEND SRCS stm32_w25q.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + target_sources(board PRIVATE ${SRCS}) set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile b/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile index c4a2f888c2701..3ba420bd68147 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/Makefile @@ -30,6 +30,34 @@ else endif endif +ifeq ($(CONFIG_STM32H7_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_STM32H7_SDMMC),y) +CSRCS += stm32_sdmmc.c +endif + +ifeq ($(CONFIG_FAT_DMAMEMORY),y) +CSRCS += stm32_dma_alloc.c +endif + +ifeq ($(CONFIG_I2C_EE_24XX),y) +CSRCS += stm32_at24.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_MTD_W25QXXXJV),y) +CSRCS += stm32_w25q.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + ifeq ($(CONFIG_BOARDCTL),y) CSRCS += stm32_appinitialize.c endif diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h b/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h index 99bf68190b205..72a6a9284e9f0 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/linum-stm32h753bi.h @@ -36,7 +36,7 @@ /* Configuration ************************************************************/ -/* LED */ +/* LED of board */ #define GPIO_LD1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTG | GPIO_PIN2) @@ -56,6 +56,61 @@ # undef HAVE_RTC_DRIVER #endif +/* USB OTG FS + * + * PA9 OTG_FS_VBUS VBUS sensing + * PI12 OTG_FS_PowerSwitchOn + * PI13 OTG_FS_Overcurrent + */ + +#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ + GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9) + +#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ + GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN12) + +#ifdef CONFIG_USBHOST +# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_EXTI|GPIO_FLOAT| \ + GPIO_SPEED_100MHz|GPIO_PUSHPULL| \ + GPIO_PORTI|GPIO_PIN13) +#else +# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ + GPIO_PUSHPULL|GPIO_PORTI|GPIO_PIN13) +#endif + +/* SD Card + * + * PG7 Card detected pin + * PD7 Enable power supply SD Card pin + */ + +#if defined(CONFIG_STM32H7_SDMMC1) +# define HAVE_SDIO +#endif + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_MMCSD_SDIO) +# undef HAVE_SDIO +#endif + +#define GPIO_SDIO_NCD (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTG | GPIO_PIN7) /* PG7 */ +#define GPIO_SD1_PWR_EN_N (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ + GPIO_OUTPUT_SET | GPIO_PORTD | GPIO_PIN7) /* PD7 */ + +#define SDIO_SLOTNO 0 +#define SDIO_MINOR 0 + +/* PWM */ + +#define BUZZER_PWMTIMER 4 + +/* Ethernet + * + * PI4 Reset PHY pin + */ + +#define GPIO_ETH_RESET (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_100MHz |\ + GPIO_OUTPUT_CLEAR | GPIO_PORTI | GPIO_PIN4) /* PI4 */ + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ @@ -77,4 +132,79 @@ int stm32_bringup(void); +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in inialization to setup + * USB-related GPIO pins for the LINUM-STM32H753BI board. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32H7_OTGFS +void weak_function stm32_usbinitialize(void); +#endif + +/**************************************************************************** + * Name: stm32_dma_alloc_init + * + * Description: + * Called to create a FAT DMA allocator. + * + * Returned Value: + * 0 on success or -ENOMEM + * + ****************************************************************************/ + +#if defined (CONFIG_FAT_DMAMEMORY) +int stm32_dma_alloc_init(void); +#endif + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support. + * + ****************************************************************************/ + +#ifdef HAVE_SDIO +int stm32_sdio_initialize(void); +#endif + +/**************************************************************************** + * Name: stm32_at24_init + * + * Description: + * Initialize and register the EEPROM for 24XX driver. + * + ****************************************************************************/ + +#ifdef CONFIG_I2C_EE_24XX +int stm32_at24_init(char *path); +#endif + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif +/**************************************************************************** + * Name: stm32_n25qxxx_setup + * + * Description: + * Initialize and register the FLash for N25QXXX driver. + * + ****************************************************************************/ + +#ifdef CONFIG_MTD_W25QXXXJV +int stm32_w25qxxx_setup(void); +#endif + #endif /* __BOARDS_ARM_STM32H7_LINUM_STM32H753BI_SRC_LINUM_STM32H753BI_H */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_at24.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_at24.c new file mode 100644 index 0000000000000..0558479a010db --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_at24.c @@ -0,0 +1,96 @@ +/**************************************************************************** + * boards/arm/stm32h7/linum-stm32h753bi/src/stm32_at24.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#include +#include +#include "stm32_i2c.h" + +#include "linum-stm32h753bi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define AT24_I2C_BUS 3 /* EEPROM chip is configured to use I2C3 */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_at24_init + * + * Description: + * Initialize and configure the AT24 serial EEPROM + * + ****************************************************************************/ + +int stm32_at24_init(char *path) +{ + FAR struct i2c_master_s *i2c; + static bool initialized = false; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* No.. Get the I2C bus driver */ + + finfo("Initialize I2C%d\n", AT24_I2C_BUS); + i2c = stm32_i2cbus_initialize(AT24_I2C_BUS); + if (!i2c) + { + ferr("ERROR: Failed to initialize I2C%d\n", AT24_I2C_BUS); + return -ENODEV; + } + + /* Now bind the I2C interface to the AT24 I2C EEPROM driver */ + + finfo("Bind the AT24 EEPROM driver to I2C%d\n", AT24_I2C_BUS); + ret = ee24xx_initialize(i2c, 0x54, path, EEPROM_24XX256, false); + if (ret < 0) + { + ferr("ERROR: Failed to bind I2C%d to the AT24 EEPROM driver\n", + AT24_I2C_BUS); + return -ENODEV; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c index 5987ccdab7cc8..c093ca3d4e2e1 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_bringup.c @@ -32,6 +32,7 @@ #include #include "stm32_gpio.h" +#include "stm32_i2c.h" #include "linum-stm32h753bi.h" @@ -44,10 +45,70 @@ # include "stm32_rtc.h" #endif +#ifdef CONFIG_STM32H7_FDCAN +#include "stm32_fdcan_sock.h" +#endif + +#ifdef CONFIG_RNDIS +#include +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2c_register(int bus) +{ + struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + syslog(LOG_ERR, "ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register I2C%d driver: %d\n", + bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) +static void stm32_i2ctool(void) +{ +#ifdef CONFIG_STM32H7_I2C3 + stm32_i2c_register(3); +#endif +#ifdef CONFIG_STM32H7_I2C4 + stm32_i2c_register(4); +#endif +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -77,6 +138,15 @@ int stm32_bringup(void) struct rtc_lowerhalf_s *lower; #endif +#ifdef CONFIG_STM32H7_RMII + /* Reset Ethernet PHY */ + + stm32_configgpio(GPIO_ETH_RESET); + stm32_gpiowrite(GPIO_ETH_RESET, 0); + usleep(50000); + stm32_gpiowrite(GPIO_ETH_RESET, 1); +#endif + #ifdef CONFIG_FS_PROCFS /* Mount the procfs file system */ @@ -124,5 +194,77 @@ int stm32_bringup(void) } #endif +#if defined(CONFIG_FAT_DMAMEMORY) + if (stm32_dma_alloc_init() < 0) + { + syslog(LOG_ERR, "DMA alloc FAILED"); + } +#endif + +#ifdef HAVE_SDIO + /* Initialize the SDIO block driver */ + + ret = stm32_sdio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize MMC/SD driver: %d\n", ret); + } +#endif + +#if defined(CONFIG_I2C) && defined(CONFIG_SYSTEM_I2CTOOL) + stm32_i2ctool(); +#endif + +#ifdef CONFIG_I2C_EE_24XX + ret = stm32_at24_init("/dev/eeprom"); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize EEPROM HX24LCXXB: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_NETDEV_LATEINIT + +# ifdef CONFIG_STM32H7_FDCAN1 + stm32_fdcansockinitialize(0); +# endif + +# ifdef CONFIG_STM32H7_FDCAN2 + stm32_fdcansockinitialize(1); +# endif + +#endif + +#ifdef CONFIG_MTD_W25QXXXJV + ret = stm32_w25qxxx_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_n25qxxx_setup failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_RNDIS) && !defined(CONFIG_RNDIS_COMPOSITE) + uint8_t mac[6]; + mac[0] = 0xa0; + mac[1] = (CONFIG_NETINIT_MACADDR_2 >> (8 * 0)) & 0xff; + mac[2] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 3)) & 0xff; + mac[3] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 2)) & 0xff; + mac[4] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 1)) & 0xff; + mac[5] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 0)) & 0xff; + usbdev_rndis_initialize(mac); +#endif + return OK; } diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_dma_alloc.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_dma_alloc.c new file mode 100644 index 0000000000000..2236dd4ffe5e1 --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_dma_alloc.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/arm/stm32h7/linum-stm32h753bi/src/stm32_dma_alloc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +#include "linum-stm32h753bi.h" + +#if defined(CONFIG_FAT_DMAMEMORY) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_GRAN) +# error microSD DMA support requires CONFIG_GRAN +#endif + +#define BOARD_DMA_ALLOC_POOL_SIZE (8*512) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static GRAN_HANDLE dma_allocator; + +/* The DMA heap size constrains the total number of things that can be + * ready to do DMA at a time. + * + * For example, FAT DMA depends on one sector-sized buffer per + * filesystem plus one sector-sized buffer per file. + * + * We use a fundamental alignment / granule size of 64B; this is + * sufficient to guarantee alignment for the largest STM32 DMA burst + * (16 beats x 32bits). + */ + +static uint8_t g_dma_heap[BOARD_DMA_ALLOC_POOL_SIZE] + aligned_data(64); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dma_alloc_init + * + * Description: + * All boards may optionally provide this API to instantiate a pool of + * memory for uses with FAST FS DMA operations. + * + ****************************************************************************/ + +int stm32_dma_alloc_init(void) +{ + dma_allocator = gran_initialize(g_dma_heap, + sizeof(g_dma_heap), + 7, /* 128B granule - must be > alignment (XXX bug?) */ + 6); /* 64B alignment */ + + if (dma_allocator == NULL) + { + return -ENOMEM; + } + + return OK; +} + +/* DMA-aware allocator stubs for the FAT filesystem. */ + +void *fat_dma_alloc(size_t size) +{ + return gran_alloc(dma_allocator, size); +} + +void fat_dma_free(void *memory, size_t size) +{ + gran_free(dma_allocator, memory, size); +} + +#endif /* CONFIG_FAT_DMAMEMORY */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c new file mode 100644 index 0000000000000..f9266ccb9d3cb --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c @@ -0,0 +1,108 @@ +/**************************************************************************** + * boards/arm/stm32h7/linum-stm32h753bi/src/stm32_pwm.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "linum-stm32h753bi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32H7_TIM4 +# undef HAVE_PWM +#endif + +#ifndef CONFIG_STM32H7_TIM4_PWM +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(BUZZER_PWMTIMER); + if (!pwm) + { + tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + tmrerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_sdmmc.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_sdmmc.c new file mode 100644 index 0000000000000..5fce66e5798af --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_sdmmc.c @@ -0,0 +1,163 @@ +/**************************************************************************** + * boards/arm/stm32h7/linum-stm32h753bi/src/stm32_sdmmc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "stm32_sdmmc.h" +#include "linum-stm32h753bi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Card detections requires card support and a card detection GPIO */ + +#define HAVE_NCD 1 +#if !defined(HAVE_SDIO) || !defined(GPIO_SDIO_NCD) +# undef HAVE_NCD +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; +#ifdef HAVE_NCD +static bool g_sd_inserted; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ncd_interrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +#ifdef HAVE_NCD +static int stm32_ncd_interrupt(int irq, void *context, void *param) +{ + bool present; + + present = !stm32_gpioread(GPIO_SDIO_NCD); + if (present != g_sd_inserted) + { + sdio_mediachange(g_sdio_dev, present); + g_sd_inserted = present; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +int stm32_sdio_initialize(void) +{ + int ret; + + /* Enable the Power Supply */ + + stm32_configgpio(GPIO_SD1_PWR_EN_N); + stm32_gpiowrite(GPIO_SD1_PWR_EN_N, 0); + + usleep(50000); + +#ifdef HAVE_NCD + /* Configure the card detect GPIO */ + + stm32_configgpio(GPIO_SDIO_NCD); + + /* Register an interrupt handler for the card detect pin */ + + stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, + stm32_ncd_interrupt, NULL); +#endif + + /* Mount the SDIO-based MMC/SD block driver */ + + /* First, get an instance of the SDIO interface */ + + finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_SLOTNO); + if (!g_sdio_dev) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); + + ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); + if (ret != OK) + { + ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + finfo("Successfully bound SDIO to the MMC/SD driver\n"); + +#ifdef HAVE_NCD + /* Use SD card detect pin to check if a card is g_sd_inserted */ + + g_sd_inserted = !stm32_gpioread(GPIO_SDIO_NCD); + finfo("Card detect : %d\n", g_sd_inserted); + + sdio_mediachange(g_sdio_dev, g_sd_inserted); +#else + /* Assume that the SD card is inserted. What choice do we have? */ + + sdio_mediachange(g_sdio_dev, true); +#endif + + return OK; +} diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c new file mode 100644 index 0000000000000..98cadf4a9f0e2 --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c @@ -0,0 +1,320 @@ +/**************************************************************************** + * boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usb.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_otg.h" +#include "linum-stm32h753bi.h" + +#ifdef CONFIG_STM32H7_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_LINUM_STM32H753BI_USBHOST_PRIO +# define CONFIG_LINUM_STM32H753BI_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_LINUM_STM32H753BI_USBHOST_STACKSIZE +# define CONFIG_LINUM_STM32H753BI_USBHOST_STACKSIZE 1024 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in inialization to setup + * USB-related GPIO pins for the linum-stm32h753bi board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32H7_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_LINUM_STM32H753BI_USBHOST_PRIO, + CONFIG_LINUM_STM32H753BI_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and status + * register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, and + * the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + /* Set the Power Switch by driving the active high enable pin */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, enable); +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usbmsc.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..36c604437dae7 --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usbmsc.c @@ -0,0 +1,59 @@ +/**************************************************************************** + * boards/arm/stm32h7/linum-stm32h753bi/src/stm32_usbmsc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization as needed to establish + * the mass storage device that will be exported by the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized in board_app_initialize() + * (see stm32_appinit.c). + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + stm32_mmcsd_initialize(0); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_w25q.c b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_w25q.c new file mode 100644 index 0000000000000..d49ea6bfddcbe --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/src/stm32_w25q.c @@ -0,0 +1,138 @@ +/**************************************************************************** + * boards/arm/stm32h7/linum-stm32h753bi/src/stm32_w25q.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include +#include + +#ifdef CONFIG_FS_NXFFS +#include +#endif + +#ifdef CONFIG_FS_SMARTFS +#include +#endif + +#include "linum-stm32h753bi.h" + +#include "stm32_qspi.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_w25qxxx_setup + * + * Description: + * This function is called by board-bringup logic to configure the + * flash device. + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +int stm32_w25qxxx_setup(void) +{ + struct qspi_dev_s *qspi_dev; + struct mtd_dev_s *mtd_dev; + int ret = -1; + + qspi_dev = stm32h7_qspi_initialize(0); + if (!qspi_dev) + { + _err("ERROR: Failed to initialize W25 minor %d: %d\n", + 0, ret); + return -1; + } + + mtd_dev = w25qxxxjv_initialize(qspi_dev, true); + if (!mtd_dev) + { + _err("ERROR: w25qxxxjv_initialize() failed!\n"); + return -1; + } + +#if defined(CONFIG_FS_NXFFS) && !defined(CONFIG_FS_LITTLEFS) + /* Initialize to provide NXFFS on the W25QXXX MTD interface */ + + ret = nxffs_initialize(mtd_dev); + if (ret < 0) + { + _err("ERROR: NXFFS initialization failed: %d\n", ret); + return ret; + } + + ret = nx_mount(NULL, "/w25", "nxffs", 0, "autoformat"); + if (ret < 0) + { + _err("ERROR: Failed to mount the NXFFS volume: %d\n", ret); + return ret; + } + +#endif + +#if !defined(CONFIG_FS_NXFFS) && defined(CONFIG_FS_LITTLEFS) + /* Register the MTD driver so that it can be accessed from the + * VFS. + */ + + ret = register_mtddriver("/dev/w25", mtd_dev, 0755, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD driver: %d\n", + ret); + } + + /* Mount the LittleFS file system */ + + ret = nx_mount("/dev/w25", "/w25", "littlefs", 0, "autoformat"); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount LittleFS at /w25: %d\n", + ret); + } +#endif + + return 0; +} diff --git a/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig b/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig index e7d74e1728073..7ed714b934bfa 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig +++ b/boards/arm/stm32h7/nucleo-h743zi2/configs/pysim/defconfig @@ -36,7 +36,6 @@ CONFIG_FS_PROCFS_REGISTER=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=2048 CONFIG_INTELHEX_BINARY=y CONFIG_IOEXPANDER=y CONFIG_LIBC_EXECFUNCS=y diff --git a/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile b/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile index 34f044927a8a4..6decb4738f56f 100644 --- a/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h743zi2/src/Makefile @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/stm32h7/nucleo-h743zi/src/Makefile +# boards/arm/stm32h7/nucleo-h743zi2/src/Makefile # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig index a2f54603b4ea5..49562d943e28f 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm4_rptun/defconfig @@ -21,6 +21,7 @@ CONFIG_BOARD_LOOPSPERMSEC=43103 CONFIG_BUILTIN=y CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_SIMPLE_ADDRENV=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INIT_ENTRYPOINT="nsh_main" @@ -31,15 +32,14 @@ CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 CONFIG_NSH_PROMPT_STRING="nsh-cm4> " CONFIG_NSH_READLINE=y -CONFIG_OPENAMP=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=245760 CONFIG_RAM_START=0x10000000 CONFIG_RAW_BINARY=y +CONFIG_RPMSG_PING=y CONFIG_RPMSG_UART=y CONFIG_RPMSG_UART_CONSOLE=y CONFIG_RPTUN=y -CONFIG_RPTUN_PING=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig index e78982e29f524..3375e07a23ca2 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/nsh_cm7_rptun/defconfig @@ -25,6 +25,7 @@ CONFIG_ARM_MPU_NREGIONS=8 CONFIG_BOARD_LOOPSPERMSEC=43103 CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_SIMPLE_ADDRENV=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_INIT_ENTRYPOINT="nsh_main" @@ -36,15 +37,14 @@ CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 CONFIG_NSH_PROMPT_STRING="nsh-cm7> " CONFIG_NSH_READLINE=y -CONFIG_OPENAMP=y CONFIG_OPENAMP_CACHE=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=245760 CONFIG_RAM_START=0x20010000 CONFIG_RAW_BINARY=y +CONFIG_RPMSG_PING=y CONFIG_RPMSG_UART=y CONFIG_RPTUN=y -CONFIG_RPTUN_PING=y CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 diff --git a/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig b/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig new file mode 100644 index 0000000000000..46c4ecce81ace --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h745zi/configs/pysim_cm7/defconfig @@ -0,0 +1,134 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ADC=y +CONFIG_ANALOG=y +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="nucleo-h745zi" +CONFIG_ARCH_BOARD_NUCLEO_H745ZI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H745ZI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_RAMVECTORS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_TASK_STACKSIZE=4096 +CONFIG_DEV_GPIO=y +CONFIG_DHCPC_RENEW_STACKSIZE=2048 +CONFIG_ETH0_PHY_LAN8742A=y +CONFIG_FAT_LCNAMES=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOEXPANDER=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y +CONFIG_MM_REGIONS=4 +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0xc0a8b201 +CONFIG_NETUTILS_DISCOVER=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ARP_IPIN=y +CONFIG_NET_ARP_SEND=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1500 +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_IGMP=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_ROUTE=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_CHECKSUMS=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=2048 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_PTHREAD_CLEANUP_STACKSIZE=1 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_PTHREAD_STACK_DEFAULT=2048 +CONFIG_PTHREAD_STACK_MIN=1024 +CONFIG_PWM=y +CONFIG_PWM_MULTICHAN=y +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=10 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKSTACKSIZE=2048 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKSTACKSIZE=2048 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_QENCODER=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_SPI=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_ADC1=y +CONFIG_STM32H7_ADC1_SAMPLE_FREQUENCY=5000 +CONFIG_STM32H7_ADC1_TIMTRIG=1 +CONFIG_STM32H7_DMA1=y +CONFIG_STM32H7_ETHMAC=y +CONFIG_STM32H7_HSI48=y +CONFIG_STM32H7_OTGFS=y +CONFIG_STM32H7_PHYSR=31 +CONFIG_STM32H7_PHYSR_100FD=0x0018 +CONFIG_STM32H7_PHYSR_100HD=0x0008 +CONFIG_STM32H7_PHYSR_10FD=0x0014 +CONFIG_STM32H7_PHYSR_10HD=0x0004 +CONFIG_STM32H7_PHYSR_ALTCONFIG=y +CONFIG_STM32H7_PHYSR_ALTMODE=0x001c +CONFIG_STM32H7_PWM_MULTICHAN=y +CONFIG_STM32H7_TIM1=y +CONFIG_STM32H7_TIM1_QE=y +CONFIG_STM32H7_TIM2=y +CONFIG_STM32H7_TIM2_ADC=y +CONFIG_STM32H7_TIM3=y +CONFIG_STM32H7_TIM3_CH1OUT=y +CONFIG_STM32H7_TIM3_CH2OUT=y +CONFIG_STM32H7_TIM3_CHANNEL1=y +CONFIG_STM32H7_TIM3_CHANNEL2=y +CONFIG_STM32H7_TIM3_PWM=y +CONFIG_STM32H7_USART3=y +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_PING_STACKSIZE=2048 +CONFIG_SYSTEM_TELNETD_SESSION_STACKSIZE=2048 +CONFIG_SYSTEM_TELNETD_STACKSIZE=2048 +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART3_SERIAL_CONSOLE=y +CONFIG_USBHOST=y +CONFIG_USBHOST_MSC=y +CONFIG_USBHOST_MSC_NOTIFIER=y +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/arm/stm32h7/nucleo-h745zi/include/board.h b/boards/arm/stm32h7/nucleo-h745zi/include/board.h index 5c75966617a7d..a6228b86d79b9 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/include/board.h +++ b/boards/arm/stm32h7/nucleo-h745zi/include/board.h @@ -281,6 +281,12 @@ /* Ethernet definitions *****************************************************/ +#define GPIO_ETH_MDC (GPIO_ETH_MDC_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0|GPIO_SPEED_100MHz) +#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0|GPIO_SPEED_100MHz) #define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2 /* PG13 */ #define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_1 /* PB 13 */ #define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_2 @@ -352,6 +358,14 @@ /* Alternate function pin selections ****************************************/ +/* ADC */ + +#define GPIO_ADC12_INP5 GPIO_ADC12_INP5_0 /* PB1 */ +#define GPIO_ADC123_INP10 GPIO_ADC123_INP10_0 /* PC0 */ +#define GPIO_ADC123_INP12 GPIO_ADC123_INP12_0 /* PC2 */ +#define GPIO_ADC12_INP13 GPIO_ADC12_INP13_0 /* PC3 */ +#define GPIO_ADC12_INP15 GPIO_ADC12_INP15_0 /* PA3 */ + /* USART1 (Arduino Serial Shield) */ #define GPIO_USART1_RX (GPIO_USART1_RX_3) /* PB7 */ @@ -365,6 +379,35 @@ #define DMAMAP_USART3_RX DMAMAP_DMA12_USART3RX_0 #define DMAMAP_USART3_TX DMAMAP_DMA12_USART3TX_1 +/* TIM1 */ + +#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2|GPIO_SPEED_50MHz) /* PE9 - D6 */ +#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1NOUT_3|GPIO_SPEED_50MHz) /* PE8 - D42 */ +#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2|GPIO_SPEED_50MHz) /* PE11 - D5 */ +#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2NOUT_3|GPIO_SPEED_50MHz) /* PE10 - D40 */ + +#define GPIO_TIM1_CH1IN (GPIO_TIM1_CH1IN_2|GPIO_SPEED_50MHz) /* PE9 */ +#define GPIO_TIM1_CH2IN (GPIO_TIM1_CH2IN_2|GPIO_SPEED_50MHz) /* PE11 */ + +/* TIM3 */ + +#define GPIO_TIM3_CH1OUT (GPIO_TIM3_CH1OUT_2|GPIO_SPEED_50MHz) /* PB4 */ +#define GPIO_TIM3_CH2OUT (GPIO_TIM3_CH2OUT_2|GPIO_SPEED_50MHz) /* PB5 */ + +#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH1IN_2|GPIO_SPEED_50MHz) /* PA4 */ +#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_2|GPIO_SPEED_50MHz) /* PB5 */ + +/* TIM4 */ + +#define GPIO_TIM4_CH1IN (GPIO_TIM4_CH1IN_2|GPIO_SPEED_50MHz) /* PD12 */ +#define GPIO_TIM4_CH2IN (GPIO_TIM4_CH2IN_2|GPIO_SPEED_50MHz) /* PD13 */ + +/* OTG */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) /* PA11 */ +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) /* PA12 */ +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) /* PA10 */ + /**************************************************************************** * Public Data ****************************************************************************/ diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/Makefile b/boards/arm/stm32h7/nucleo-h745zi/src/Makefile index d7694432ab679..561bc5d1b3ab7 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/Makefile +++ b/boards/arm/stm32h7/nucleo-h745zi/src/Makefile @@ -22,14 +22,38 @@ include $(TOPDIR)/Make.defs CSRCS = stm32_boot.c stm32_bringup.c +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + ifeq ($(CONFIG_ARCH_LEDS),y) CSRCS += stm32_autoleds.c else CSRCS += stm32_userleds.c endif +ifeq ($(CONFIG_STM32H7_OTGFS),y) +CSRCS += stm32_usb.c +endif + ifeq ($(CONFIG_BOARDCTL),y) CSRCS += stm32_appinitialize.c endif +ifeq ($(CONFIG_DEV_GPIO),y) +CSRCS += stm32_gpio.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += stm32_pwm.c +endif + +ifeq ($(CONFIG_SENSORS_QENCODER),y) +CSRCS += stm32_qencoder.c +endif + +ifeq ($(CONFIG_BOARDCTL_RESET),y) +CSRCS += stm32_reset.c +endif + include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h b/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h index 618a8f649b78f..6fb4d72bad987 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h +++ b/boards/arm/stm32h7/nucleo-h745zi/src/nucleo-h745zi.h @@ -167,15 +167,28 @@ /* GPIO pins used by the GPIO Subsystem */ -#define BOARD_NGPIOIN 1 /* Amount of GPIO Input pins */ -#define BOARD_NGPIOOUT 1 /* Amount of GPIO Output pins */ +#define BOARD_NGPIOIN 4 /* Amount of GPIO Input pins */ +#define BOARD_NGPIOOUT 8 /* Amount of GPIO Output pins */ #define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ /* Example, used free Ports on the board */ -#define GPIO_IN1 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN2) +#define GPIO_IN1 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN7) +#define GPIO_IN2 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN12) +#define GPIO_IN3 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN14) +#define GPIO_IN4 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN15) + #define GPIO_OUT1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN4) +#define GPIO_OUT2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ + GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN5) +#define GPIO_OUT3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ + GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN6) +#define GPIO_OUT4 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ + GPIO_OUTPUT_SET | GPIO_PORTA| GPIO_PIN5) +#define GPIO_OUT5 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ + GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN3) + #define GPIO_INT1 (GPIO_INPUT | GPIO_FLOAT | GPIO_PORTE | GPIO_PIN5) /* X-NUCLEO IKS01A2 */ @@ -211,7 +224,11 @@ /* PWM */ +#if defined(CONFIG_STM32H7_TIM1_PWM) #define NUCLEOH745ZI_PWMTIMER 1 +#else +#define NUCLEOH745ZI_PWMTIMER 3 +#endif /**************************************************************************** * Public Function Prototypes @@ -234,4 +251,70 @@ int stm32_bringup(void); +#ifdef CONFIG_STM32H7_OTGFS +void weak_function stm32_usbinitialize(void); +#endif + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +#ifdef CONFIG_ADC +int stm32_adc_setup(int adcno); +#endif + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO-Driver. + * + ****************************************************************************/ + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) +int stm32_gpio_initialize(void); +#endif + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. This function will start a thread that will monitor for + * device connection/disconnection events. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32H7_OTGFS) && defined(CONFIG_USBHOST) +int stm32_usbhost_initialize(void); +#endif + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +#ifdef CONFIG_PWM +int stm32_pwm_setup(void); +#endif + +/**************************************************************************** + * Name: stm32_qencoder_initialize + * + * Description: + * Initialize and register a qencoder + * + ****************************************************************************/ + +#ifdef CONFIG_SENSORS_QENCODER +int stm32_qencoder_initialize(const char *devpath, int timer); +#endif + #endif /* __BOARDS_ARM_STM32H7_NUCLEO_H745ZI_SRC_NUCLEO_H745ZI_H */ diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c new file mode 100644 index 0000000000000..e5c80f4073a4d --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c @@ -0,0 +1,222 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h745zi/src/stm32_adc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_adc.h" +#include "nucleo-h745zi.h" + +#ifdef CONFIG_ADC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 3 ADC interfaces are supported */ + +#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC2) || \ + defined(CONFIG_STM32H7_ADC3) +#ifndef CONFIG_STM32H7_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 5 +#define ADC3_NCHANNELS 1 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_STM32H7_ADC1 +/* Identifying number of each ADC channel: Variable Resistor. + * + * ADC1: {5, 10, 12, 13, 15}; + */ + +static const uint8_t g_adc1_chanlist[ADC1_NCHANNELS] = +{ + 5, 10, 12, 13, 15 +}; + +/* Configurations of pins used by each ADC channels + * + * ADC1: + * {GPIO_ADC12_INP5, GPIO_ADC123_INP10, GPIO_ADC123_INP12, GPIO_ADC12_INP13, + * GPIO_ADC12_INP15}; + */ + +static const uint32_t g_adc1_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC12_INP5, + GPIO_ADC123_INP10, + GPIO_ADC123_INP12, + GPIO_ADC12_INP13, + GPIO_ADC12_INP15 +}; +#endif + +#ifdef CONFIG_STM32H7_ADC3 +/* Identifying number of each ADC channel: Variable Resistor. + * + * ADC3: {6,}; + */ + +static const uint8_t g_adc3_chanlist[ADC1_NCHANNELS] = +{ + 6 +}; + +/* Configurations of pins used by each ADC channels + * + * + * ADC3: {GPIO_ADC3_INP6} + */ + +static const uint32_t g_adc3_pinlist[ADC3_NCHANNELS] = +{ + GPIO_ADC3_INP6 +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_adc_setup + * + * Description: + * Initialize ADC and register the ADC driver. + * + ****************************************************************************/ + +int stm32_adc_setup(int adcno) +{ +#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + char devname[10]; + + /* Check if we have already initialized */ + + if (!initialized) + { + snprintf(devname, 1, "/dev/adc%d", adcno); + +#endif +#if defined(CONFIG_STM32H7_ADC1) + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + if (g_adc1_pinlist[i] != 0) + { + stm32_configgpio(g_adc1_pinlist[i]); + } + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32h7_adc_initialize(1, g_adc1_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC1 interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register(devname, adc); + if (ret < 0) + { + aerr("ERROR: adc_register(%s) failed: %d\n", devname, ret); + return ret; + } + + devname[8]++; +#endif +#if defined(CONFIG_STM32H7_ADC3) + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC3_NCHANNELS; i++) + { + if (g_adc3_pinlist[i] != 0) + { + stm32_configgpio(g_adc3_pinlist[i]); + } + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32h7_adc_initialize(3, g_adc3_chanlist, ADC3_NCHANNELS); + if (adc == NULL) + { + aerr("ERROR: Failed to get ADC3 interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0 or 1" */ + + ret = adc_register(devname, adc); + if (ret < 0) + { + aerr("ERROR: adc_register(%s) failed: %d\n", devname, ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32H7_ADC1) || defined(CONFIG_STM32H7_ADC3) + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32H7_ADC1 || CONFIG_STM32H7_ADC2 || CONFIG_STM32H7_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c index a3a373affdf76..65b816f5d7636 100644 --- a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_bringup.c @@ -57,14 +57,14 @@ void rpmsg_serialinit(void) { #ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 - uart_rpmsg_init("cm7", "proxy", 4096, false); + uart_rpmsg_init("cm4", "proxy", 4096, false); #endif #ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM4 # ifdef CONFIG_RPMSG_UART_CONSOLE - uart_rpmsg_init("cm4", "proxy", 4096, true); + uart_rpmsg_init("cm7", "proxy", 4096, true); # else - uart_rpmsg_init("cm4", "proxy", 4096, false); + uart_rpmsg_init("cm7", "proxy", 4096, false); # endif #endif } @@ -104,11 +104,126 @@ int stm32_bringup(void) #ifdef CONFIG_RPTUN # ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 - stm32_rptun_init("cm7-shmem", "cm7"); + stm32_rptun_init("cm4"); # else - stm32_rptun_init("cm4-shmem", "cm4"); + stm32_rptun_init("cm7"); # endif #endif + #ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() + * starts a thread will monitor for USB connection and + * disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize USB host: %d\n", + ret); + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to start USB monitor: %d\n", + ret); + } +#endif + +#ifdef CONFIG_ADC + /* Initialize ADC and register the ADC driver. */ + + int adcno = 0; + +#ifdef CONFIG_STM32H7_ADC1 + adcno = 0; +#endif + +#ifdef CONFIG_STM32H7_ADC3 + adcno = 2; +#endif + + ret = stm32_adc_setup(adcno); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_adc_setup failed: %d\n", ret); + } +#endif /* CONFIG_ADC */ + +#ifdef CONFIG_DEV_GPIO + /* Register the GPIO driver */ + + ret = stm32_gpio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_NETDEV_LATEINIT + +# ifdef CONFIG_STM32H7_FDCAN1 + stm32_fdcansockinitialize(0); +# endif + +# ifdef CONFIG_STM32H7_FDCAN2 + stm32_fdcansockinitialize(1); +# endif + +#endif + +#ifdef CONFIG_SENSORS_QENCODER +#ifdef CONFIG_STM32H7_TIM1_QE + ret = stm32_qencoder_initialize("/dev/qe0", 1); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32H7_TIM3_QE + ret = stm32_qencoder_initialize("/dev/qe2", 3); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif + +#ifdef CONFIG_STM32H7_TIM4_QE + ret = stm32_qencoder_initialize("/dev/qe3", 4); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to register the qencoder: %d\n", + ret); + return ret; + } +#endif +#endif + +#ifdef CONFIG_PWM + /* Initialize PWM and register the PWM device. */ + + ret = stm32_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: stm32_pwm_setup() failed: %d\n", ret); + } +#endif + return OK; } diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_gpio.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_gpio.c new file mode 100644 index 0000000000000..2de003357c839 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_gpio.c @@ -0,0 +1,331 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h745zi/src/stm32_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "chip.h" +#include "stm32_gpio.h" +#include "nucleo-h745zi.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct stm32gpint_dev_s +{ + struct stm32gpio_dev_s stm32gpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int gpin_read(struct gpio_dev_s *dev, bool *value); +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct gpio_operations_s gpin_ops = +{ + .go_read = gpin_read, + .go_write = NULL, + .go_attach = NULL, + .go_enable = NULL, +}; + +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, +}; + +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, +}; + +#if BOARD_NGPIOIN > 0 +/* This array maps the GPIO pins used as INPUT */ + +static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = +{ + GPIO_IN1, + GPIO_IN2, + GPIO_IN3, + GPIO_IN4, +}; + +static struct stm32gpio_dev_s g_gpin[BOARD_NGPIOIN]; +#endif + +#if BOARD_NGPIOOUT +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_LD1, + GPIO_LD2, + GPIO_LD3, + GPIO_OUT1, + GPIO_OUT2, + GPIO_OUT3, + GPIO_OUT4, + GPIO_OUT5, +}; + +static struct stm32gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_INT1, +}; + +static struct stm32gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int stm32gpio_interrupt(int irq, void *context, void *arg) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)arg; + + DEBUGASSERT(stm32gpint != NULL && stm32gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", stm32gpint->callback); + + stm32gpint->callback(&stm32gpint->stm32gpio.gpio, + stm32gpint->stm32gpio.id); + return OK; +} + +static int gpin_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOIN); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpioinputs[stm32gpio->id]); + return OK; +} + +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL && value != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = stm32_gpioread(g_gpiooutputs[stm32gpio->id]); + return OK; +} + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct stm32gpio_dev_s *stm32gpio = + (struct stm32gpio_dev_s *)dev; + + DEBUGASSERT(stm32gpio != NULL); + DEBUGASSERT(stm32gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + stm32_gpiowrite(g_gpiooutputs[stm32gpio->id], value); + return OK; +} + +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + DEBUGASSERT(stm32gpint != NULL && value != NULL); + DEBUGASSERT(stm32gpint->stm32gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = stm32_gpioread(g_gpiointinputs[stm32gpint->stm32gpio.id]); + return OK; +} + +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], false, + false, false, NULL, NULL); + + gpioinfo("Attach %p\n", callback); + stm32gpint->callback = callback; + return OK; +} + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct stm32gpint_dev_s *stm32gpint = + (struct stm32gpint_dev_s *)dev; + + if (enable) + { + if (stm32gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + true, false, false, stm32gpio_interrupt, + &g_gpint[stm32gpint->stm32gpio.id]); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + stm32_gpiosetevent(g_gpiointinputs[stm32gpint->stm32gpio.id], + false, false, false, NULL, NULL); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_gpio_initialize + * + * Description: + * Initialize GPIO drivers for use with /apps/examples/gpio + * + ****************************************************************************/ + +int stm32_gpio_initialize(void) +{ + int i; + int pincount = 0; + +#if BOARD_NGPIOIN > 0 + for (i = 0; i < BOARD_NGPIOIN; i++) + { + /* Setup and register the GPIO pin */ + + g_gpin[i].gpio.gp_pintype = GPIO_INPUT_PIN; + g_gpin[i].gpio.gp_ops = &gpin_ops; + g_gpin[i].id = i; + gpio_pin_register(&g_gpin[i].gpio, pincount); + + /* Configure the pin that will be used as input */ + + stm32_configgpio(g_gpioinputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pin that will be used as output */ + + stm32_gpiowrite(g_gpiooutputs[i], 0); + stm32_configgpio(g_gpiooutputs[i]); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].stm32gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].stm32gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].stm32gpio.id = i; + gpio_pin_register(&g_gpint[i].stm32gpio.gpio, pincount); + + /* Configure the pin that will be used as interrupt input */ + + stm32_configgpio(g_gpiointinputs[i]); + + pincount++; + } +#endif + + return 0; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c new file mode 100644 index 0000000000000..b4228394d36e3 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c @@ -0,0 +1,112 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h745zi/src/stm32_pwm.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_pwm.h" +#include "nucleo-h745zi.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_PWM 1 + +#ifndef CONFIG_PWM +# undef HAVE_PWM +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_pwm_setup + * + * Description: + * Initialize PWM and register the PWM device. + * + ****************************************************************************/ + +int stm32_pwm_setup(void) +{ +#ifdef HAVE_PWM + static bool initialized = false; + struct pwm_lowerhalf_s *pwm; + int ret; + + /* Have we already initialized? */ + + if (!initialized) + { + /* Get an instance of the PWM interface */ + + pwm = stm32_pwminitialize(NUCLEOH745ZI_PWMTIMER); + if (pwm == NULL) + { + tmrerr("ERROR: Failed to get the STM32 PWM lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + #if defined(CONFIG_STM32H7_TIM1_PWM) + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + tmrerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#if defined(CONFIG_STM32H7_TIM3_PWM) + ret = pwm_register("/dev/pwm2", pwm); + if (ret < 0) + { + tmrerr("ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENODEV; +#endif +} diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_qencoder.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_qencoder.c new file mode 100644 index 0000000000000..a9c146a47cf7c --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_qencoder.c @@ -0,0 +1,65 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h745zi/src/stm32_qencoder.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "chip.h" +#include "arm_internal.h" +#include "stm32_qencoder.h" +#include "nucleo-h745zi.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: qe_devinit + * + * Description: + * All STM32H7 architectures must provide the following interface to work + * with examples/qencoder. + * + ****************************************************************************/ + +int stm32_qencoder_initialize(const char *devpath, int timer) +{ + int ret; + + /* Initialize a quadrature encoder interface. */ + + sninfo("Initializing the quadrature encoder using TIM%d\n", timer); + ret = stm32_qeinitialize(devpath, timer); + if (ret < 0) + { + snerr("ERROR: stm32_qeinitialize failed: %d\n", ret); + } + + return ret; +} diff --git a/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c new file mode 100644 index 0000000000000..d209e4a09fdb3 --- /dev/null +++ b/boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c @@ -0,0 +1,320 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h745zi/src/stm32_usb.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_otg.h" +#include "nucleo-h745zi.h" + +#ifdef CONFIG_STM32H7_OTGFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_USBHOST_DEFPRIO +# define CONFIG_USBHOST_DEFPRIO 100 +#endif + +#ifndef CONFIG_USBHOST_STACKSIZE +# define CONFIG_USBHOST_STACKSIZE 2048 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in inialization to setup + * USB-related GPIO pins for the nucleo-144 board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. + * No GPIO configuration is required + */ + + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32H7_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", CONFIG_USBHOST_DEFPRIO, + CONFIG_USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and status + * register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, and + * the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + /* Set the Power Switch by driving the active low enable pin */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable); +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/boards/arm/stm32h7/openh743i/CMakeLists.txt b/boards/arm/stm32h7/openh743i/CMakeLists.txt new file mode 100644 index 0000000000000..a49a0def59036 --- /dev/null +++ b/boards/arm/stm32h7/openh743i/CMakeLists.txt @@ -0,0 +1,21 @@ +# ############################################################################## +# boards/arm/stm32h7/openh743i/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32h7/openh743i/Kconfig b/boards/arm/stm32h7/openh743i/Kconfig new file mode 100644 index 0000000000000..b3b3f5e86346f --- /dev/null +++ b/boards/arm/stm32h7/openh743i/Kconfig @@ -0,0 +1,18 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_OPENH743I + +config OPENH743I_DISABLE_OTGFS_PWRON + bool "Disable OTGFS PWRON pin" + depends on USBHOST + default n + ---help--- + This option disable PWRON pin control from MCU. + Setting PWRON in high state somehow breaks USBDEV on OTGHS. + If both OTG peripherals are used, and OTGFS is used as HOST, + then the power switch enable pin must be set directly from 3.3V bus. + +endif # ARCH_BOARD_OPENH743I diff --git a/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig b/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig new file mode 100644 index 0000000000000..4448ea23551cc --- /dev/null +++ b/boards/arm/stm32h7/openh743i/configs/composite_fs/defconfig @@ -0,0 +1,89 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="openh743i" +CONFIG_ARCH_BOARD_OPENH743I=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H743II=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARDCTL_USBDEVCTRL=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_COMPOSITE=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_COMPOSITE_IAD=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_STATISTICS=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0x0 +CONFIG_NETINIT_MACADDR_1=0xdeadcafe +CONFIG_NETINIT_NETMASK=0x0 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_IPERF=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_ARP_SEND=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RNDIS=y +CONFIG_RNDIS_COMPOSITE=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_HSI48=y +CONFIG_STM32H7_OTGFS=y +CONFIG_STM32H7_SDMMC1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y +CONFIG_USBDEV_COMPOSITE=y +CONFIG_USBMSC=y +CONFIG_USBMSC_COMPOSITE=y diff --git a/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig b/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig new file mode 100644 index 0000000000000..b5ca7bcb7a732 --- /dev/null +++ b/boards/arm/stm32h7/openh743i/configs/composite_hs/defconfig @@ -0,0 +1,97 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="openh743i" +CONFIG_ARCH_BOARD_OPENH743I=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H743II=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_CDCACM_COMPOSITE=y +CONFIG_COMPOSITE_IAD=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0 +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_STATISTICS=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NETINIT_DRIPADDR=0x0 +CONFIG_NETINIT_MACADDR_1=0xdeadcafe +CONFIG_NETINIT_NETMASK=0x0 +CONFIG_NETINIT_NOMAC=y +CONFIG_NETINIT_THREAD=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_IPERF=y +CONFIG_NETUTILS_TELNETD=y +CONFIG_NET_ARP_SEND=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_LOOPBACK=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RNDIS=y +CONFIG_RNDIS_COMPOSITE=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_HSI48=y +CONFIG_STM32H7_OTGHS=y +CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI=y +CONFIG_STM32H7_SDMMC1=y +CONFIG_STM32H7_SYSCFG_IOCOMPENSATION=y +CONFIG_SYSTEM_COMPOSITE=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USBDEV=y +CONFIG_USBDEV_COMPOSITE=y +CONFIG_USBDEV_CUSTOM_TXFIFO_SIZE=y +CONFIG_USBDEV_DUALSPEED=y +CONFIG_USBDEV_EP1_TXFIFO_SIZE=128 +CONFIG_USBDEV_EP2_TXFIFO_SIZE=128 +CONFIG_USBDEV_EP3_TXFIFO_SIZE=128 +CONFIG_USBDEV_EP4_TXFIFO_SIZE=128 +CONFIG_USBDEV_EP5_TXFIFO_SIZE=512 +CONFIG_USBMSC=y +CONFIG_USBMSC_COMPOSITE=y diff --git a/boards/arm/stm32h7/openh743i/configs/nsh/defconfig b/boards/arm/stm32h7/openh743i/configs/nsh/defconfig new file mode 100644 index 0000000000000..325f560584728 --- /dev/null +++ b/boards/arm/stm32h7/openh743i/configs/nsh/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="openh743i" +CONFIG_ARCH_BOARD_OPENH743I=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H743II=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXPERIMENTAL=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=4 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig b/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig new file mode 100644 index 0000000000000..0d565ce894ee6 --- /dev/null +++ b/boards/arm/stm32h7/openh743i/configs/usbdev_hs_host_fs/defconfig @@ -0,0 +1,73 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="openh743i" +CONFIG_ARCH_BOARD_OPENH743I=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H743II=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_ASSERTIONS_EXPRESSION=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXPERIMENTAL=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=4 +CONFIG_NDEBUG=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_OPENH743I_DISABLE_OTGFS_PWRON=y +CONFIG_OTG_ID_GPIO_DISABLE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPNTHREADS=2 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_STACK_USAGE=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_HSI48=y +CONFIG_STM32H7_OTGFS=y +CONFIG_STM32H7_OTGFS_HOST=y +CONFIG_STM32H7_OTGHS=y +CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI=y +CONFIG_STM32H7_SYSCFG_IOCOMPENSATION=y +CONFIG_SYSTEM_CDCACM=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=32 +CONFIG_USBDEV=y +CONFIG_USBHOST=y +CONFIG_USBHOST_CDCACM=y +CONFIG_USBHOST_COMPOSITE=y +CONFIG_USBHOST_MSC=y diff --git a/boards/arm/stm32h7/openh743i/include/board.h b/boards/arm/stm32h7/openh743i/include/board.h new file mode 100644 index 0000000000000..3e283971b8dca --- /dev/null +++ b/boards/arm/stm32h7/openh743i/include/board.h @@ -0,0 +1,379 @@ +/**************************************************************************** + * boards/arm/stm32h7/openh743i/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32H7_OPENH743I_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32H7_OPENH743I_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/* Do not include STM32 H7 header files here */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The Openh743i board provides the following clock sources: + * + * X2: 32.768 KHz crystal for LSE + * X2: 8 MHz HSE crystal oscillator + * + * So we have these clock source available within the STM32 + * + * HSI: 16 MHz RC factory-trimmed + * LSI: 32 KHz RC + * HSE: 8 MHz oscillator X2 + * LSE: 32.768 kHz + */ + +#define STM32_BOARD_XTAL 8000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE = 8,000,000 + * + * When STM32_HSE_FREQUENCY / PLLM <= 2MHz VCOL must be selected. + * VCOH otherwise. + * + * PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * Subject to: + * + * 1 <= PLLM <= 63 + * 4 <= PLLN <= 512 + * 150 MHz <= PLL_VCOL <= 420MHz + * 192 MHz <= PLL_VCOH <= 836MHz + * + * SYSCLK = PLL_VCO / PLLP + * CPUCLK = SYSCLK / D1CPRE + * Subject to + * + * PLLP1 = {2, 4, 6, 8, ..., 128} + * PLLP2,3 = {2, 3, 4, ..., 128} + * CPUCLK <= 400 MHz + */ + +#define STM32_BOARD_USEHSE +#undef STM32_HSEBYP_ENABLE + +#define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE + +/* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR + * + * PLL1_VCO = (8,000,000 / 2) * 200 = 800 MHz + * + * PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz + * PLL1Q = PLL1_VCO/4 = 800 MHz / 4 = 200 MHz + * PLL1R = PLL1_VCO/8 = 800 MHz / 8 = 100 MHz + */ + +#define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \ + RCC_PLLCFGR_PLL1RGE_4_8_MHZ | \ + RCC_PLLCFGR_DIVP1EN | \ + RCC_PLLCFGR_DIVQ1EN | \ + RCC_PLLCFGR_DIVR1EN) +#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(2) +#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(200) +#define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2) +#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4) +#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(8) + +#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 200) +#define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2) +#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4) +#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 8) + +/* PLL2 */ + +#define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE | \ + RCC_PLLCFGR_PLL2RGE_4_8_MHZ | \ + RCC_PLLCFGR_DIVP2EN) +#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(2) +#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(200) +#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(40) +#define STM32_PLLCFG_PLL2Q 0 +#define STM32_PLLCFG_PLL2R 0 + +#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 200) +#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 2) +#define STM32_PLL2Q_FREQUENCY +#define STM32_PLL2R_FREQUENCY + +/* PLL3, wide 1 - 2 MHz input, enable DIVQ + * + * PLL3_VCO = (8,000,000 / 8) * 336 = 336 MHz + * + * PLL3P - TODO + * PLL3Q = PLL3_VCO / 7 = 336 MHz / 7 = 48 MHz + * PLL3R - TODO + */ + +#define STM32_PLLCFG_PLL3CFG (RCC_PLLCFGR_PLL3VCOSEL_WIDE | \ + RCC_PLLCFGR_PLL3RGE_1_2_MHZ | \ + RCC_PLLCFGR_DIVQ3EN) +#define STM32_PLLCFG_PLL3M RCC_PLLCKSELR_DIVM3(8) +#define STM32_PLLCFG_PLL3N RCC_PLL3DIVR_N3(336) +#define STM32_PLLCFG_PLL3P RCC_PLL3DIVR_P3(2) +#define STM32_PLLCFG_PLL3Q RCC_PLL3DIVR_Q3(7) +#define STM32_PLLCFG_PLL3R RCC_PLL3DIVR_R3(2) + +#define STM32_VCO3_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 100) +#define STM32_PLL3P_FREQUENCY +#define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FREQUENCY / 8) +#define STM32_PLL3R_FREQUENCY + +/* SYSCLK = PLL1P = 400 MHz + * CPUCLK = SYSCLK / 1 = 400 MHz + */ + +#define STM32_RCC_D1CFGR_D1CPRE (RCC_D1CFGR_D1CPRE_SYSCLK) +#define STM32_SYSCLK_FREQUENCY (STM32_PLL1P_FREQUENCY) +#define STM32_CPUCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 1) + +/* Configure Clock Assignments */ + +/* AHB clock (HCLK) is SYSCLK/2 (200 MHz max) + * HCLK1 = HCLK2 = HCLK3 = HCLK4 + */ + +#define STM32_RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_SYSCLKd2 /* HCLK = SYSCLK / 2 */ +#define STM32_ACLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* ACLK in D1, HCLK3 in D1 */ +#define STM32_HCLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* HCLK in D2, HCLK4 in D3 */ + +/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */ + +#define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* APB2 clock (PCLK2) is HCLK/4 (54 MHz) */ + +#define STM32_RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_HCLKd4 /* PCLK2 = HCLK / 4 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* APB3 clock (PCLK3) is HCLK/4 (54 MHz) */ + +#define STM32_RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_HCLKd4 /* PCLK3 = HCLK / 4 */ +#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* APB4 clock (PCLK4) is HCLK/4 (54 MHz) */ + +#define STM32_RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_HCLKd4 /* PCLK4 = HCLK / 4 */ +#define STM32_PCLK4_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timer clock frequencies */ + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Kernel Clock Configuration + * + * Note: look at Table 54 in ST Manual + */ + +/* I2C123 clock source - HSI */ + +#define STM32_RCC_D2CCIP2R_I2C123SRC RCC_D2CCIP2R_I2C123SEL_HSI + +/* I2C4 clock source - HSI */ + +#define STM32_RCC_D3CCIPR_I2C4SRC RCC_D3CCIPR_I2C4SEL_HSI + +/* SPI123 clock source - PLL1Q */ + +#define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL1 + +/* SPI45 clock source - APB (PCLK2?) */ + +#define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_APB + +/* SPI6 clock source - APB (PCLK4) */ + +#define STM32_RCC_D3CCIPR_SPI6SRC RCC_D3CCIPR_SPI6SEL_PCLK4 + +#if 1 +/* USB 1 and 2 clock source - HSI48 */ + +# define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_HSI48 +#else +/* USB 1 and 2 clock source - PLL3Q */ + +# define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_PLL3 +#endif + +/* ADC 1 2 3 clock source - pll2_pclk */ + +#define STM32_RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_PLL2 + +/* FLASH wait states + * + * ------------ ---------- ----------- + * Vcore MAX ACLK WAIT STATES + * ------------ ---------- ----------- + * 1.15-1.26 V 70 MHz 0 + * (VOS1 level) 140 MHz 1 + * 210 MHz 2 + * 1.05-1.15 V 55 MHz 0 + * (VOS2 level) 110 MHz 1 + * 165 MHz 2 + * 220 MHz 3 + * 0.95-1.05 V 45 MHz 0 + * (VOS3 level) 90 MHz 1 + * 135 MHz 2 + * 180 MHz 3 + * 225 MHz 4 + * ------------ ---------- ----------- + */ + +#define BOARD_FLASH_WAITSTATES 2 +#define BOARD_FLASH_PROGDELAY 3 +#define STM32_PWR_VOS_SCALE PWR_D3CR_VOS_SCALE_1 +#define STM32_VOS_OVERDRIVE 1 /* Enable VOS0 */ + +/* SDMMC definitions ********************************************************/ + +/* Init 400kHz, PLL1Q/(2*250) */ + +#define STM32_SDMMC_INIT_CLKDIV (250 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) + +/* Set these to 20 MHz (PLL1Q/(2*5)). + * Higher frequency doesn't work, probably due to poor board + * signal integrity + */ + +#define STM32_SDMMC_MMCXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_SDXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) + +#define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE + +/* LED definitions **********************************************************/ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_LED2 1 +#define BOARD_LED3 2 +#define BOARD_LED4 3 +#define BOARD_NLEDS 4 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) +#define BOARD_LED2_BIT (1 << BOARD_LED2) +#define BOARD_LED3_BIT (1 << BOARD_LED3) +#define BOARD_LED4_BIT (1 << BOARD_LED4) + +/* Alternate function pin selections ****************************************/ + +/* USART1 (CP2102 converter) */ + +#define GPIO_USART1_RX GPIO_USART1_RX_2 /* PA10 */ +#define GPIO_USART1_TX GPIO_USART1_TX_2 /* PA9 */ + +/* USART3 */ + +#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */ +#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */ + +/* USB OTG ULPI */ + +#define GPIO_OTG_HS_ULPI_CK (GPIO_OTG_HS_ULPI_CK_0|GPIO_SPEED_100MHz) +#define GPIO_OTG_HS_ULPI_D0 (GPIO_OTG_HS_ULPI_D0_0|GPIO_SPEED_100MHz) +#define GPIO_OTG_HS_ULPI_D1 (GPIO_OTG_HS_ULPI_D1_0|GPIO_SPEED_100MHz) +#define GPIO_OTG_HS_ULPI_D2 (GPIO_OTG_HS_ULPI_D2_0|GPIO_SPEED_100MHz) +#define GPIO_OTG_HS_ULPI_D3 (GPIO_OTG_HS_ULPI_D3_0|GPIO_SPEED_100MHz) +#define GPIO_OTG_HS_ULPI_D4 (GPIO_OTG_HS_ULPI_D4_0|GPIO_SPEED_100MHz) +#define GPIO_OTG_HS_ULPI_D5 (GPIO_OTG_HS_ULPI_D5_0|GPIO_SPEED_100MHz) +#define GPIO_OTG_HS_ULPI_D6 (GPIO_OTG_HS_ULPI_D6_0|GPIO_SPEED_100MHz) +#define GPIO_OTG_HS_ULPI_D7 (GPIO_OTG_HS_ULPI_D7_0|GPIO_SPEED_100MHz) +#define GPIO_OTG_HS_ULPI_DIR (GPIO_OTG_HS_ULPI_DIR_1|GPIO_SPEED_100MHz) /* PC2 */ +#define GPIO_OTG_HS_ULPI_NXT (GPIO_OTG_HS_ULPI_NXT_1|GPIO_SPEED_100MHz) /* PC3 */ +#define GPIO_OTG_HS_ULPI_STP (GPIO_OTG_HS_ULPI_STP_0|GPIO_SPEED_100MHz) + +/* OTGFS */ + +#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz) +#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz) + +/* SDMMC */ + +#define GPIO_SDMMC1_D0 (GPIO_SDMMC1_D0_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC1_D1 (GPIO_SDMMC1_D1_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC1_D2 (GPIO_SDMMC1_D2_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC1_D3 (GPIO_SDMMC1_D3_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC1_CK (GPIO_SDMMC1_CK_0|GPIO_SPEED_50MHz) +#define GPIO_SDMMC1_CMD (GPIO_SDMMC1_CMD_0|GPIO_SPEED_50MHz) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_STM32H7_OPENH743I_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/openh743i/scripts/Make.defs b/boards/arm/stm32h7/openh743i/scripts/Make.defs new file mode 100644 index 0000000000000..4acc499494cf7 --- /dev/null +++ b/boards/arm/stm32h7/openh743i/scripts/Make.defs @@ -0,0 +1,48 @@ +############################################################################ +# boards/arm/stm32h7/openh743i/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = flash.ld + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# ELF module definitions + +CELFFLAGS = $(CFLAGS) -mlong-calls # --target1-abs +CXXELFFLAGS = $(CXXFLAGS) -mlong-calls # --target1-abs + +LDELFFLAGS = -r -e main +LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/binfmt/libelf/gnu-elf.ld) diff --git a/boards/arm/stm32h7/openh743i/scripts/flash.ld b/boards/arm/stm32h7/openh743i/scripts/flash.ld new file mode 100644 index 0000000000000..14d41c4220a10 --- /dev/null +++ b/boards/arm/stm32h7/openh743i/scripts/flash.ld @@ -0,0 +1,198 @@ +/**************************************************************************** +* boards/arm/stm32h7/openh743i/scripts/flash.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32H743II has 2048Kb of main FLASH memory. The flash memory is + * partitioned into a User Flash memory and a System Flash memory. Each + * of these memories has two banks: + * + * 1) User Flash memory: + * + * Bank 1: Start address 0x0800:0000 to 0x080F:FFFF with 8 sectors, 128Kb each + * Bank 2: Start address 0x0810:0000 to 0x081F:FFFF with 8 sectors, 128Kb each + * + * 2) System Flash memory: + * + * Bank 1: Start address 0x1FF0:0000 to 0x1FF1:FFFF with 1 x 128Kb sector + * Bank 1: Start address 0x1FF4:0000 to 0x1FF5:FFFF with 1 x 128Kb sector + * + * 3) User option bytes for user configuration, only in Bank 1. + * + * In the STM32H743II, two different boot spaces can be selected through + * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and + * BOOT_ADD1 option bytes: + * + * 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0]. + * ST programmed value: Flash memory at 0x0800:0000 + * 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0]. + * ST programmed value: System bootloader at 0x1FF0:0000 + * + * NuttX does not modify these option bytes. On the unmodified openh743i + * board, the BOOT0 pin is at ground so by default, the STM32 will boot + * to address 0x0800:0000 in FLASH. + * + * The STM32H743II also has 1024Kb of data SRAM. + * SRAM is split up into several blocks and into three power domains: + * + * 1) TCM SRAMs are dedicated to the Cortex-M7 and are accessible with + * 0 wait states by the Cortex-M7 and by MDMA through AHBS slave bus + * + * 1.1) 128Kb of DTCM-RAM beginning at address 0x2000:0000 + * + * The DTCM-RAM is organized as 2 x 64Kb DTCM-RAMs on 2 x 32 bit + * DTCM ports. The DTCM-RAM could be used for critical real-time + * data, such as interrupt service routines or stack / heap memory. + * Both DTCM-RAMs can be used in parallel (for load/store operations) + * thanks to the Cortex-M7 dual issue capability. + * + * 1.2) 64Kb of ITCM-RAM beginning at address 0x0000:0000 + * + * This RAM is connected to ITCM 64-bit interface designed for + * execution of critical real-times routines by the CPU. + * + * 2) AXI SRAM (D1 domain) accessible by all system masters except BDMA + * through D1 domain AXI bus matrix + * + * 2.1) 512Kb of SRAM beginning at address 0x2400:0000 + * + * 3) AHB SRAM (D2 domain) accessible by all system masters except BDMA + * through D2 domain AHB bus matrix + * + * 3.1) 128Kb of SRAM1 beginning at address 0x3000:0000 + * 3.2) 128Kb of SRAM2 beginning at address 0x3002:0000 + * 3.3) 32Kb of SRAM3 beginning at address 0x3004:0000 + * + * SRAM1 - SRAM3 are one contiguous block: 288Kb at address 0x3000:0000 + * + * 4) AHB SRAM (D3 domain) accessible by most of system masters + * through D3 domain AHB bus matrix + * + * 4.1) 64Kb of SRAM4 beginning at address 0x3800:0000 + * 4.1) 4Kb of backup RAM beginning at address 0x3880:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K + flash (rx) : ORIGIN = 0x08000000, LENGTH = 2048K + dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K + dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K + sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K + sram1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K + sram2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K + sram3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K + sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K + bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : + { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : + { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Emit the the D3 power domain section for locating BDMA data + * + * Static data with locate_data(".sram4") will be located + * at start of SRAM4; the rest of SRAM4 will be added to the heap. + */ + + .sram4_reserve (NOLOAD) : + { + *(.sram4) + . = ALIGN(4); + _sram4_heap_start = ABSOLUTE(.); + } > sram4 + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32h7/openh743i/src/CMakeLists.txt b/boards/arm/stm32h7/openh743i/src/CMakeLists.txt new file mode 100644 index 0000000000000..f08137bf4a9e8 --- /dev/null +++ b/boards/arm/stm32h7/openh743i/src/CMakeLists.txt @@ -0,0 +1,45 @@ +# ############################################################################## +# boards/arm/stm32h7/openh743i/src/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_BOARDCTL) + list(APPEND SRCS stm32_appinitialize.c) +endif() + +if(CONFIG_STM32H7_SDMMC) + list(APPEND SRCS stm32_sdmmc.c) +endif() + +if(CONFIG_USBDEV OR CONFIG_USBHOST) + list(APPEND SRCS stm32_usb.c) +endif() + +if(CONFIG_USBMSC) + list(APPEND SRCS stm32_usbmsc.c) +endif() + +if(CONFIG_USBDEV_COMPOSITE) + list(APPEND SRCS stm32_composite.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/stm32h7/openh743i/src/Makefile b/boards/arm/stm32h7/openh743i/src/Makefile new file mode 100644 index 0000000000000..fc51176c22b28 --- /dev/null +++ b/boards/arm/stm32h7/openh743i/src/Makefile @@ -0,0 +1,47 @@ +############################################################################ +# boards/arm/stm32h7/openh743i/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += stm32_appinitialize.c +endif + +ifeq ($(CONFIG_STM32H7_SDMMC),y) +CSRCS += stm32_sdmmc.c +endif + +ifeq ($(CONFIG_USBDEV),y) +CSRCS += stm32_usb.c +else ifeq ($(CONFIG_USBHOST),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += stm32_usbmsc.c +endif + +ifeq ($(CONFIG_USBDEV_COMPOSITE),y) +CSRCS += stm32_composite.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h7/openh743i/src/openh743i.h b/boards/arm/stm32h7/openh743i/src/openh743i.h new file mode 100644 index 0000000000000..8c8ba22aa7b26 --- /dev/null +++ b/boards/arm/stm32h7/openh743i/src/openh743i.h @@ -0,0 +1,140 @@ +/**************************************************************************** + * boards/arm/stm32h7/openh743i/src/openh743i.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32H7_OPENH743I_SRC_OPENH743I_H +#define __BOARDS_ARM_STM32H7_OPENH743I_SRC_OPENH743I_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* procfs File System */ + +#ifdef CONFIG_FS_PROCFS +# ifdef CONFIG_NSH_PROC_MOUNTPOINT +# define STM32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT +# else +# define STM32_PROCFS_MOUNTPOINT "/proc" +# endif +#endif + +/* SD/TF Card'detected pin */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_MMCSD_SDIO) +# undef HAVE_SDIO +#endif + +#define GPIO_SDIO_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN13) + +#define SDIO_SLOTNO 0 +#define SDIO_MINOR 0 + +/* ULPI */ + +#define GPIO_ULPI_RESET (GPIO_OUTPUT|GPIO_PORTE|GPIO_PIN2|GPIO_OUTPUT_CLEAR) + +/* USB OTG FS + * + * PA9 OTG_FS_VBUS VBUS sensing (also connected to the green LED) + * PE2 OTG_FS_PowerSwitchOn + * PE3 OTG_FS_Overcurrent + */ + +#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ + GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9) + +#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz| \ + GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN2) + +#define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_EXTI|GPIO_FLOAT| \ + GPIO_SPEED_100MHz|GPIO_PUSHPULL| \ + GPIO_PORTE|GPIO_PIN3) + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y : + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void); + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +#ifdef CONFIG_STM32H7_SDMMC +int stm32_sdio_initialize(void); +#endif + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in inialization to setup + * USB-related GPIO pins for the board. + * + ****************************************************************************/ + +#ifdef CONFIG_STM32H7_OTGFS +void weak_function stm32_usbinitialize(void); +#endif + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. This function will start a thread that will monitor for + * device connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void); +#endif + +#endif /* __BOARDS_ARM_STM32H7_OPENH743I_SRC_OPENH743I_H */ diff --git a/boards/arm/stm32h7/openh743i/src/stm32_appinitialize.c b/boards/arm/stm32h7/openh743i/src/stm32_appinitialize.c new file mode 100644 index 0000000000000..39c57f6a6dd9e --- /dev/null +++ b/boards/arm/stm32h7/openh743i/src/stm32_appinitialize.c @@ -0,0 +1,76 @@ +/**************************************************************************** + * boards/arm/stm32h7/openh743i/src/stm32_appinitialize.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "openh743i.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return stm32_bringup(); +#endif +} diff --git a/boards/arm/stm32h7/openh743i/src/stm32_boot.c b/boards/arm/stm32h7/openh743i/src/stm32_boot.c new file mode 100644 index 0000000000000..977aa487cf67f --- /dev/null +++ b/boards/arm/stm32h7/openh743i/src/stm32_boot.c @@ -0,0 +1,85 @@ +/**************************************************************************** + * boards/arm/stm32h7/openh743i/src/stm32_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32_start.h" +#include "openh743i.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32H7_OTGFS_HOST) || defined(CONFIG_STM32H7_OTGHS_HOST) + /* Initialize USB */ + + stm32_usbinitialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() + * will be called immediately after up_initialize() is called and just + * before the initial application is started. This additional + * initialization phase may be used, for example, to initialize board- + * specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ +#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_BOARDCTL) + /* Perform board bring-up here instead of from the + * board_app_initialize(). + */ + + stm32_bringup(); +#endif +} +#endif diff --git a/boards/arm/stm32h7/openh743i/src/stm32_bringup.c b/boards/arm/stm32h7/openh743i/src/stm32_bringup.c new file mode 100644 index 0000000000000..d512d552c4d07 --- /dev/null +++ b/boards/arm/stm32h7/openh743i/src/stm32_bringup.c @@ -0,0 +1,123 @@ +/**************************************************************************** + * boards/arm/stm32h7/openh743i/src/stm32_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#ifdef CONFIG_RNDIS +# include +#endif + +#ifdef CONFIG_STM32H7_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "openh743i.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y && + * CONFIG_NSH_ARCHINIT: + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + + UNUSED(ret); + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount the PROC filesystem: %d\n", ret); + } +#endif /* CONFIG_FS_PROCFS */ + +#if defined(CONFIG_RNDIS) && !defined(CONFIG_RNDIS_COMPOSITE) + uint8_t mac[6]; + mac[0] = 0xa0; /* TODO */ + mac[1] = (CONFIG_NETINIT_MACADDR_2 >> (8 * 0)) & 0xff; + mac[2] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 3)) & 0xff; + mac[3] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 2)) & 0xff; + mac[4] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 1)) & 0xff; + mac[5] = (CONFIG_NETINIT_MACADDR_1 >> (8 * 0)) & 0xff; + usbdev_rndis_initialize(mac); +#endif + +#if defined(CONFIG_STM32H7_SDMMC) && !defined(CONFIG_CDCACM_CONSOLE) + /* Initialize the SDIO block driver */ + + ret = stm32_sdio_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize MMC/SD driver: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() + * starts a thread will monitor for USB connection and + * disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize USB host: %d\n", + ret); + } +#endif + + return OK; +} diff --git a/boards/arm/stm32h7/openh743i/src/stm32_composite.c b/boards/arm/stm32h7/openh743i/src/stm32_composite.c new file mode 100644 index 0000000000000..c3a221c3a2850 --- /dev/null +++ b/boards/arm/stm32h7/openh743i/src/stm32_composite.c @@ -0,0 +1,352 @@ +/**************************************************************************** + * boards/arm/stm32h7/openh743i/src/stm32_composite.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "stm32_otg.h" + +#include "openh743i.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define COMPOSITE0_DEV (3) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void *g_mschandle; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_mscclassobject + * + * Description: + * If the mass storage class driver is part of composite device, then + * its instantiation and configuration is a multi-step, board-specific, + * process (See comments for usbmsc_configure below). In this case, + * board-specific logic must provide board_mscclassobject(). + * + * board_mscclassobject() is called from the composite driver. It must + * encapsulate the instantiation and configuration of the mass storage + * class and the return the mass storage device's class driver instance + * to the composite driver. + * + * Input Parameters: + * classdev - The location to return the mass storage class' device + * instance. + * + * Returned Value: + * 0 on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static int board_mscclassobject(int minor, + struct usbdev_devinfo_s *devinfo, + struct usbdevclass_driver_s **classdev) +{ + int ret; + + DEBUGASSERT(g_mschandle == NULL); + + /* Configure the mass storage device */ + + uinfo("Configuring with NLUNS=1\n"); + ret = usbmsc_configure(1, &g_mschandle); + if (ret < 0) + { + uerr("ERROR: usbmsc_configure failed: %d\n", -ret); + return ret; + } + + uinfo("MSC handle=%p\n", g_mschandle); + + /* Bind the LUN(s) */ + + uinfo("Bind LUN=0 to /dev/mmcsd0\n"); + ret = usbmsc_bindlun(g_mschandle, "/dev/mmcsd0", 0, 0, 0, false); + if (ret < 0) + { + uerr("ERROR: usbmsc_bindlun failed for LUN 1 at /dev/mmcsd0: %d\n", + ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + return ret; + } + + /* Get the mass storage device's class object */ + + ret = usbmsc_classobject(g_mschandle, devinfo, classdev); + if (ret < 0) + { + uerr("ERROR: usbmsc_classobject failed: %d\n", -ret); + usbmsc_uninitialize(g_mschandle); + g_mschandle = NULL; + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: board_mscuninitialize + * + * Description: + * Un-initialize the USB storage class driver. + * This is just an application specific wrapper for usbmsc_unitialize() + * that is called form the composite device logic. + * + * Input Parameters: + * classdev - The class driver instrance previously give to the composite + * driver by board_mscclassobject(). + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +static void board_mscuninitialize(struct usbdevclass_driver_s *classdev) +{ + if (g_mschandle) + { + usbmsc_uninitialize(g_mschandle); + } + + g_mschandle = NULL; +} +#endif + +/**************************************************************************** + * Name: board_composite_connect + * + * Description: + * Connect the USB composite device on the specified USB device port for + * configuration 0. + * + * Input Parameters: + * port - The USB device port. + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +static void *board_composite0_connect(int port) +{ + struct composite_devdesc_s dev[COMPOSITE0_DEV]; + int ifnobase = 0; + int strbase = COMPOSITE_NSTRIDS; + int dev_idx = 0; + int epin = 1; + int epout = 1; + +#ifdef CONFIG_RNDIS_COMPOSITE + /* Configure the RNDIS USB device */ + + /* Ask the rndis driver to fill in the constants we didn't + * know here. + */ + + usbdev_rndis_get_composite_devdesc(&dev[dev_idx]); + + /* Interfaces */ + + dev[dev_idx].devinfo.ifnobase = ifnobase; + dev[dev_idx].minor = 0; + + /* Strings */ + + dev[dev_idx].devinfo.strbase = strbase; + + /* Endpoints */ + + dev[dev_idx].devinfo.epno[RNDIS_EP_INTIN_IDX] = epin++; + dev[dev_idx].devinfo.epno[RNDIS_EP_BULKIN_IDX] = epin++; + dev[dev_idx].devinfo.epno[RNDIS_EP_BULKOUT_IDX] = epout++; + + /* Count up the base numbers */ + + ifnobase += dev[dev_idx].devinfo.ninterfaces; + strbase += dev[dev_idx].devinfo.nstrings; + + dev_idx += 1; +#endif + +#ifdef CONFIG_CDCACM_COMPOSITE + /* Configure the CDC/ACM device */ + + /* Ask the cdcacm driver to fill in the constants we didn't + * know here. + */ + + cdcacm_get_composite_devdesc(&dev[dev_idx]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the CDC/ACM class */ + + dev[dev_idx].classobject = cdcacm_classobject; + dev[dev_idx].uninitialize = cdcacm_uninitialize; + + /* Interfaces */ + + dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[dev_idx].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[dev_idx].devinfo.epno[CDCACM_EP_INTIN_IDX] = epin++; + dev[dev_idx].devinfo.epno[CDCACM_EP_BULKIN_IDX] = epin++; + dev[dev_idx].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = epout++; + + /* Count up the base numbers */ + + ifnobase += dev[dev_idx].devinfo.ninterfaces; + strbase += dev[dev_idx].devinfo.nstrings; + + dev_idx += 1; +#endif + +#ifdef CONFIG_USBMSC_COMPOSITE + /* Configure the mass storage device device */ + + /* Ask the usbmsc driver to fill in the constants we didn't + * know here. + */ + + usbmsc_get_composite_devdesc(&dev[dev_idx]); + + /* Overwrite and correct some values... */ + + /* The callback functions for the USBMSC class */ + + dev[dev_idx].classobject = board_mscclassobject; + dev[dev_idx].uninitialize = board_mscuninitialize; + + /* Interfaces */ + + dev[dev_idx].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[dev_idx].minor = 0; /* The minor interface number */ + + /* Strings */ + + dev[dev_idx].devinfo.strbase = strbase; /* Offset to String Numbers */ + + /* Endpoints */ + + dev[dev_idx].devinfo.epno[USBMSC_EP_BULKIN_IDX] = epin++; + dev[dev_idx].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = epout++; + + /* Count up the base numbers */ + + ifnobase += dev[dev_idx].devinfo.ninterfaces; + strbase += dev[dev_idx].devinfo.nstrings; + + dev_idx += 1; +#endif + + /* Sanity checks */ + + DEBUGASSERT(epin < STM32_NENDPOINTS); + DEBUGASSERT(epout < STM32_NENDPOINTS); + + return composite_initialize(composite_getdevdescs(), dev, dev_idx); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_composite_initialize + * + * Description: + * Perform architecture specific initialization of a composite USB device. + * + ****************************************************************************/ + +int board_composite_initialize(int port) +{ +#if defined(CONFIG_CDCACM_CONSOLE) && defined(CONFIG_USBMSC_COMPOSITE) + stm32_sdio_initialize(); +#endif + return OK; +} + +/**************************************************************************** + * Name: board_composite_connect + * + * Description: + * Connect the USB composite device on the specified USB device port using + * the specified configuration. The interpretation of the configid is + * board specific. + * + * Input Parameters: + * port - The USB device port. + * configid - The USB composite configuration + * + * Returned Value: + * A non-NULL handle value is returned on success. NULL is returned on + * any failure. + * + ****************************************************************************/ + +void *board_composite_connect(int port, int configid) +{ + if (configid == 0) + { + return board_composite0_connect(port); + } + else + { + return NULL; + } +} diff --git a/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c b/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c new file mode 100644 index 0000000000000..dddadb282a33e --- /dev/null +++ b/boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c @@ -0,0 +1,149 @@ +/**************************************************************************** + * boards/arm/stm32h7/openh743i/src/stm32_sdmmc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "stm32_gpio.h" +#include "stm32_sdmmc.h" + +#include "openh743i.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_STM32H7_SDMMC1 +# error SDMMC1 supported only +#endif + +/* If IDMA is enabled, internal SRAM must be excluded from heap */ + +#if CONFIG_MM_REGIONS > 1 && defined(CONFIG_STM32H7_SDMMC_IDMA) +# error SDMMC1 with IDMA doesnt work CONFIG_MM_REGIONS > 1 +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; +static bool g_sd_inserted = 0xff; /* Impossible value */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ncd_interrupt + * + * Description: + * Card detect interrupt handler. + * + ****************************************************************************/ + +static int stm32_ncd_interrupt(int irq, void *context, void *param) +{ + bool present; + + present = !stm32_gpioread(GPIO_SDIO_NCD); + if (present != g_sd_inserted) + { + sdio_mediachange(g_sdio_dev, present); + g_sd_inserted = present; + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +int stm32_sdio_initialize(void) +{ + bool cd_status; + int ret; + + /* Configure the card detect GPIO */ + + stm32_configgpio(GPIO_SDIO_NCD); + + /* Register an interrupt handler for the card detect pin */ + + stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, + stm32_ncd_interrupt, NULL); + + /* Mount the SDIO-based MMC/SD block driver */ + + /* First, get an instance of the SDIO interface */ + + finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); + + g_sdio_dev = sdio_initialize(SDIO_SLOTNO); + if (!g_sdio_dev) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); + + ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); + if (ret != OK) + { + ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + finfo("Successfully bound SDIO to the MMC/SD driver\n"); + + /* Use SD card detect pin to check if a card is g_sd_inserted */ + + cd_status = !stm32_gpioread(GPIO_SDIO_NCD); + finfo("Card detect : %d\n", cd_status); + + sdio_mediachange(g_sdio_dev, cd_status); + + return OK; +} diff --git a/boards/arm/stm32h7/openh743i/src/stm32_usb.c b/boards/arm/stm32h7/openh743i/src/stm32_usb.c new file mode 100644 index 0000000000000..ae3044a20bfe3 --- /dev/null +++ b/boards/arm/stm32h7/openh743i/src/stm32_usb.c @@ -0,0 +1,327 @@ +/**************************************************************************** + * boards/arm/stm32h7/openh743i/src/stm32_usb.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "stm32_gpio.h" +#include "stm32_otg.h" + +#include "openh743i.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32H7_OTGFS_HOST) && defined(CONFIG_STM32H7_OTGHS_USBDEV) +# ifndef CONFIG_OPENH743I_DISABLE_OTGFS_PWRON +# error PWRON must be disabled for this configuration +# endif +#endif + +#define USBHOST_PRIO (100) +#define USBHOST_STACKSIZE (1024) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (; ; ) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in inialization to setup + * USB-related GPIO pins for the board. + * + ****************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* Configure the OTG FS VBUS sensing GPIO, + * Power On, and Overcurrent GPIOs + */ + +#ifdef CONFIG_STM32H7_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/**************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host + * functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int ret; + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + ret = kthread_create("usbhost", USBHOST_PRIO, USBHOST_STACKSIZE, + usbhost_waiter, NULL); + return ret < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be + * provided be each platform that implements the STM32 OTG FS host + * interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a + * charge pump or, if 5 V are available on the application board, a + * basic power switch, must be added externally to drive the 5 V VBUS + * line. The external charge pump can be driven by any GPIO output. + * When the application decides to power on VBUS using the chosen GPIO, + * it must also set the port power bit in the host port control and status + * register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, and + * the core clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. + * Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + /* Set the Power Switch by driving the active high enable pin. + * + * NOTE: Setting PWRON in high state somehow breaks USBDEV on OTGHS. + * If both OTG peripherals are used and OTGFS is used as HOST, + * then the power switch enable pin must be set directly from + * 3.3V bus. + */ + +#ifdef CONFIG_OPENH743I_DISABLE_OTGFS_PWRON + stm32_gpiowrite(GPIO_OTGFS_PWRON, enable); +#endif +} +#endif + +/**************************************************************************** + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent + * condition is detected. + * + * Input Parameters: + * handler - New overcurrent interrupt handler + * arg - The argument provided for the interrupt handler + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise, a negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_setup_overcurrent(xcpt_t handler, void *arg) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg); +} +#endif + +/**************************************************************************** + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV + * driver is used. This function is called whenever the USB enters or + * leaves suspend mode. This is an opportunity for the board logic to + * shutdown clocks, power, etc. while the USB is suspended. + * + ****************************************************************************/ + +void stm32_usbsuspend(struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} + +#ifdef CONFIG_STM32H7_OTGHS_EXTERNAL_ULPI +/**************************************************************************** + * Name: stm32_usbulpireset + * + * Description: + * Reset external ULPI. + * + ****************************************************************************/ + +void stm32_usbulpireset(struct usbdev_s *dev) +{ + stm32_configgpio(GPIO_ULPI_RESET); + + up_mdelay(5); + stm32_gpiowrite(GPIO_ULPI_RESET, true); + up_mdelay(10); + stm32_gpiowrite(GPIO_ULPI_RESET, false); + up_mdelay(10); +} +#endif diff --git a/boards/arm/stm32h7/openh743i/src/stm32_usbmsc.c b/boards/arm/stm32h7/openh743i/src/stm32_usbmsc.c new file mode 100644 index 0000000000000..2db1df3f0050b --- /dev/null +++ b/boards/arm/stm32h7/openh743i/src/stm32_usbmsc.c @@ -0,0 +1,70 @@ +/**************************************************************************** + * boards/arm/stm32h7/openh743i/src/stm32_usbmsc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "openh743i.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_USBDEV_CUSTOM_TXFIFO_SIZE) && \ + defined(CONFIG_USBDEV_DUALSPEED) +# error USBMSC high-speed require custom TXFIFO configuratin that set EPIN FIFO to >=512 +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization as needed to establish + * the mass storage device that will be exported by the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized in board_app_initialize() + * (see stm32_appinit.c). + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS + stm32_sdio_initialize(); +#else + return OK; +#endif +} diff --git a/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig b/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig index 31ac8e2a2176f..3000a9e18637a 100644 --- a/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig +++ b/boards/arm/stm32h7/stm32h745i-disco/configs/lvgl/defconfig @@ -43,6 +43,13 @@ CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INPUT=y CONFIG_INPUT_FT5X06=y CONFIG_INTELHEX_BINARY=y +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y +CONFIG_LV_USE_DEMO_WIDGETS=y +CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y CONFIG_MQ_MAXMSGSIZE=256 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm/stm32h7/weact-stm32h743/CMakeLists.txt b/boards/arm/stm32h7/weact-stm32h743/CMakeLists.txt new file mode 100644 index 0000000000000..25d0dc19677e2 --- /dev/null +++ b/boards/arm/stm32h7/weact-stm32h743/CMakeLists.txt @@ -0,0 +1,21 @@ +# ############################################################################## +# boards/arm/stm32h7/weact-stm32h743/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32h7/weact-stm32h743/Kconfig b/boards/arm/stm32h7/weact-stm32h743/Kconfig new file mode 100644 index 0000000000000..8b54c4f53abde --- /dev/null +++ b/boards/arm/stm32h7/weact-stm32h743/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_WEACT_STM32H743 + +endif # ARCH_BOARD_WEACT_STM32H743 diff --git a/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig b/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig new file mode 100644 index 0000000000000..9ba31bb78975c --- /dev/null +++ b/boards/arm/stm32h7/weact-stm32h743/configs/nsh/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="weact-stm32h743" +CONFIG_ARCH_BOARD_WEACT_STM32H743=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H743VI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXPERIMENTAL=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=4 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI=y +CONFIG_START_DAY=11 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2024 +CONFIG_STM32H7_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/weact-stm32h743/include/board.h b/boards/arm/stm32h7/weact-stm32h743/include/board.h new file mode 100644 index 0000000000000..c8a4e35099639 --- /dev/null +++ b/boards/arm/stm32h7/weact-stm32h743/include/board.h @@ -0,0 +1,366 @@ +/**************************************************************************** + * boards/arm/stm32h7/weact-stm32h743/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32H7_WEACT_STM32H743_INCLUDE_BOARD_H +#define __BOARDS_ARM_STM32H7_WEACT_STM32H743_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/* Do not include STM32 H7 header files here */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The WeAct STM32H743 board provides the following clock sources: + * + * MCO: 8 MHz from MCO output of ST-LINK is used as input clock (default) + * X2: 32.768 KHz crystal for LSE + * X3: HSE crystal oscillator (not provided) + * + * So we have these clock source available within the STM32 + * + * HSI: 16 MHz RC factory-trimmed + * LSI: 32 KHz RC + * HSE: 25 MHz crystal + * LSE: 32.768 kHz + */ + +#define STM32_BOARD_XTAL 25000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE = 25,000,000 + * + * When STM32_HSE_FREQUENCY / PLLM <= 2MHz VCOL must be selected. + * VCOH otherwise. + * + * PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * Subject to: + * + * 1 <= PLLM <= 63 + * 4 <= PLLN <= 512 + * 150 MHz <= PLL_VCOL <= 420MHz + * 192 MHz <= PLL_VCOH <= 836MHz + * + * SYSCLK = PLL_VCO / PLLP + * CPUCLK = SYSCLK / D1CPRE + * Subject to + * + * PLLP1 = {2, 4, 6, 8, ..., 128} + * PLLP2,3 = {2, 3, 4, ..., 128} + * CPUCLK <= 400 MHz + */ + +#define STM32_BOARD_USEHSE + +#define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE + +/* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR + * + * PLL1_VCO = (25 MHz / 5) * 192 = 960 MHz + * + * PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 480 MHz + * PLL1Q = PLL1_VCO/4 = 800 MHz / 4 = 240 MHz + * PLL1R = PLL1_VCO/8 = 800 MHz / 4 = 240 MHz + */ + +#define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \ + RCC_PLLCFGR_PLL1RGE_4_8_MHZ | \ + RCC_PLLCFGR_DIVP1EN | \ + RCC_PLLCFGR_DIVQ1EN | \ + RCC_PLLCFGR_DIVR1EN) + +#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 5) * 192) +#define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2) +#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4) +#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 4) + +#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(5) +#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(192) +#define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2) +#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4) +#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(4) + +/* PLL2, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR + * + * PLL1_VCO = (25 MHz / 2) * 48 = 600 MHz + * + * PLL2P = PLL2_VCO/2 = 600 MHz / 8 = 75 MHz + * PLL2Q = PLL2_VCO/4 = 600 MHz / 40 = 15 MHz + * PLL2R = PLL2_VCO/8 = 600 MHz / 3 = 200 MHz + */ +#define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE | \ + RCC_PLLCFGR_PLL2RGE_4_8_MHZ | \ + RCC_PLLCFGR_DIVP2EN | \ + RCC_PLLCFGR_DIVQ2EN | \ + RCC_PLLCFGR_DIVR2EN ) + +#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 48) +#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 8) +#define STM32_PLL2Q_FREQUENCY (STM32_VCO2_FREQUENCY / 40) +#define STM32_PLL2R_FREQUENCY (STM32_VCO2_FREQUENCY / 3) + +#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(2) +#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(48) +#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(8) +#define STM32_PLLCFG_PLL2Q RCC_PLL2DIVR_Q2(40) +#define STM32_PLLCFG_PLL2R RCC_PLL2DIVR_R2(3) + +/* PLL3 */ + +#define STM32_PLLCFG_PLL3CFG 0 +#define STM32_PLLCFG_PLL3M 0 +#define STM32_PLLCFG_PLL3N 0 +#define STM32_PLLCFG_PLL3P 0 +#define STM32_PLLCFG_PLL3Q 0 +#define STM32_PLLCFG_PLL3R 0 + +#define STM32_VCO3_FREQUENCY +#define STM32_PLL3P_FREQUENCY +#define STM32_PLL3Q_FREQUENCY +#define STM32_PLL3R_FREQUENCY + +/* SYSCLK = PLL1P = 480 MHz + * CPUCLK = SYSCLK / 1 = 480 MHz + */ + +#define STM32_RCC_D1CFGR_D1CPRE (RCC_D1CFGR_D1CPRE_SYSCLK) +#define STM32_SYSCLK_FREQUENCY (STM32_PLL1P_FREQUENCY) +#define STM32_CPUCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 1) + +/* Configure Clock Assignments */ + +/* AHB clock (HCLK) is SYSCLK/2 (480 MHz max) + * HCLK1 = HCLK2 = HCLK3 = HCLK4 + */ + +#define STM32_RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_SYSCLKd2 /* HCLK = SYSCLK / 2 */ +#define STM32_ACLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 2) /* ACLK in D1, HCLK3 in D1 */ +#define STM32_HCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 2) /* HCLK in D2, HCLK4 in D3 */ + +/* APB1 clock (PCLK1) is HCLK/2 (120 MHz) */ + +#define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB2 clock (PCLK2) is HCLK/2 (120 MHz) */ + +#define STM32_RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB3 clock (PCLK3) is HCLK/2 (120 MHz) */ + +#define STM32_RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_HCLKd2 /* PCLK3 = HCLK / 2 */ +#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* APB4 clock (PCLK4) is HCLK/2 (120 MHz) */ + +#define STM32_RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_HCLKd2 /* PCLK4 = HCLK / 2 */ +#define STM32_PCLK4_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timer clock frequencies */ + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Kernel Clock Configuration + * + * Note: look at Table 54 in ST Manual + */ + +/* I2C123 clock source - HSI */ + +#define STM32_RCC_D2CCIP2R_I2C123SRC RCC_D2CCIP2R_I2C123SEL_HSI + +/* I2C4 clock source - HSI */ + +#define STM32_RCC_D3CCIPR_I2C4SRC RCC_D3CCIPR_I2C4SEL_HSI + +/* SPI123 clock source - PLL1Q */ + +#define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL1 + +/* SPI45 clock source - APB (PCLK2?) */ + +#define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_APB + +/* SPI6 clock source - APB (PCLK4) */ + +#define STM32_RCC_D3CCIPR_SPI6SRC RCC_D3CCIPR_SPI6SEL_PCLK4 + +/* USB 1 and 2 clock source - HSI48 */ + +#define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_HSI48 + +/* ADC 1 2 3 clock source - pll2_pclk */ + +#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2 + +/* FLASH wait states + * + * ------------ ---------- ----------- + * Vcore MAX ACLK WAIT STATES + * ------------ ---------- ----------- + * 1.15-1.26 V 70 MHz 0 + * (VOS1 level) 140 MHz 1 + * 210 MHz 2 + * 1.05-1.15 V 55 MHz 0 + * (VOS2 level) 110 MHz 1 + * 165 MHz 2 + * 220 MHz 3 + * 0.95-1.05 V 45 MHz 0 + * (VOS3 level) 90 MHz 1 + * 135 MHz 2 + * 180 MHz 3 + * 225 MHz 4 + * ------------ ---------- ----------- + */ + +#define BOARD_FLASH_WAITSTATES 4 + +/* SDMMC definitions ********************************************************/ + +/* Init 400 kHz, PLL1Q/(2*300) = 240 MHz / (2*300) = 400 Khz */ + +#define STM32_SDMMC_INIT_CLKDIV (300 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) + +/* Just set these to 24 MHz for now, + * PLL1Q/(2*5) = 240 MHz / (2*5) = 24 MHz + */ + +#define STM32_SDMMC_MMCXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_SDXFR_CLKDIV (5 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) + +#define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE + +/* LED definitions **********************************************************/ + +/* The board has 1 user LED that could be used this diagnostic LED too. + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED1 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in + * include/board.h and src/stm32_leds.c. + * The LEDs are used to encode OS-related events as follows: + * + * + * SYMBOL Meaning LED state + * Red Green Blue + * ---------------------- -------------------------- ------ ------ --- + */ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ +#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */ +#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */ +#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */ +#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */ +#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */ +#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */ +#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */ + +/* Thus if the Green LED is statically on, NuttX has successfully booted and + * is, apparently, running normally. If the Red LED is flashing at + * approximately 2Hz, then a fatal error has been detected and the system + * has halted. + */ + +/* Button definitions *******************************************************/ + +/* The WeAct-STM32H743 board has two user buttons */ + +/* Alternate function pin selections ****************************************/ + +/* USART1 (Serial Console) */ + +#define GPIO_USART1_RX (GPIO_USART1_RX_1 | GPIO_SPEED_100MHz) /* PB15 */ +#define GPIO_USART1_TX (GPIO_USART1_TX_1 | GPIO_SPEED_100MHz) /* PB14 */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_STM32H7_WEACT_STM32H743_INCLUDE_BOARD_H */ diff --git a/boards/arm/stm32h7/weact-stm32h743/scripts/Make.defs b/boards/arm/stm32h7/weact-stm32h743/scripts/Make.defs new file mode 100644 index 0000000000000..dc4ea4b047557 --- /dev/null +++ b/boards/arm/stm32h7/weact-stm32h743/scripts/Make.defs @@ -0,0 +1,48 @@ +############################################################################ +# boards/arm/stm32h7/weact-stm32h743/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = flash.ld + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# ELF module definitions + +CELFFLAGS = $(CFLAGS) -mlong-calls # --target1-abs +CXXELFFLAGS = $(CXXFLAGS) -mlong-calls # --target1-abs + +LDELFFLAGS = -r -e main +LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/binfmt/libelf/gnu-elf.ld) diff --git a/boards/arm/stm32h7/weact-stm32h743/scripts/flash.ld b/boards/arm/stm32h7/weact-stm32h743/scripts/flash.ld new file mode 100644 index 0000000000000..86ddf38a1bd7c --- /dev/null +++ b/boards/arm/stm32h7/weact-stm32h743/scripts/flash.ld @@ -0,0 +1,201 @@ +/**************************************************************************** + * boards/arm/stm32h7/weact-stm32h743/scripts/flash.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The STM32H743VI has 2048Kb of main FLASH memory. The flash memory is + * partitioned into a User Flash memory and a System Flash memory. Each + * of these memories has two banks: + * + * 1) User Flash memory: + * + * Bank 1: Start address 0x0800:0000 to 0x080F:FFFF with 8 sectors, 128Kb each + * Bank 2: Start address 0x0810:0000 to 0x081F:FFFF with 8 sectors, 128Kb each + * + * 2) System Flash memory: + * + * Bank 1: Start address 0x1FF0:0000 to 0x1FF1:FFFF with 1 x 128Kb sector + * Bank 1: Start address 0x1FF4:0000 to 0x1FF5:FFFF with 1 x 128Kb sector + * + * 3) User option bytes for user configuration, only in Bank 1. + * + * In the STM32H743VI, two different boot spaces can be selected through + * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and + * BOOT_ADD1 option bytes: + * + * 1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0]. + * ST programmed value: Flash memory at 0x0800:0000 + * 2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0]. + * ST programmed value: System bootloader at 0x1FF0:0000 + * + * TODO: Check next paragraph with nucleo schematics + * + * NuttX does not modify these option bytes. On the unmodified NUCLEO-H743ZI + * board, the BOOT0 pin is at ground so by default, the STM32 will boot + * to address 0x0800:0000 in FLASH. + * + * The STM32H743VI also has 1024Kb of data SRAM. + * SRAM is split up into several blocks and into three power domains: + * + * 1) TCM SRAMs are dedicated to the Cortex-M7 and are accessible with + * 0 wait states by the Cortex-M7 and by MDMA through AHBS slave bus + * + * 1.1) 128Kb of DTCM-RAM beginning at address 0x2000:0000 + * + * The DTCM-RAM is organized as 2 x 64Kb DTCM-RAMs on 2 x 32 bit + * DTCM ports. The DTCM-RAM could be used for critical real-time + * data, such as interrupt service routines or stack / heap memory. + * Both DTCM-RAMs can be used in parallel (for load/store operations) + * thanks to the Cortex-M7 dual issue capability. + * + * 1.2) 64Kb of ITCM-RAM beginning at address 0x0000:0000 + * + * This RAM is connected to ITCM 64-bit interface designed for + * execution of critical real-times routines by the CPU. + * + * 2) AXI SRAM (D1 domain) accessible by all system masters except BDMA + * through D1 domain AXI bus matrix + * + * 2.1) 512Kb of SRAM beginning at address 0x2400:0000 + * + * 3) AHB SRAM (D2 domain) accessible by all system masters except BDMA + * through D2 domain AHB bus matrix + * + * 3.1) 128Kb of SRAM1 beginning at address 0x3000:0000 + * 3.2) 128Kb of SRAM2 beginning at address 0x3002:0000 + * 3.3) 32Kb of SRAM3 beginning at address 0x3004:0000 + * + * SRAM1 - SRAM3 are one contiguous block: 288Kb at address 0x3000:0000 + * + * 4) AHB SRAM (D3 domain) accessible by most of system masters + * through D3 domain AHB bus matrix + * + * 4.1) 64Kb of SRAM4 beginning at address 0x3800:0000 + * 4.1) 4Kb of backup RAM beginning at address 0x3880:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address range. + */ + +MEMORY +{ + itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K + flash (rx) : ORIGIN = 0x08000000, LENGTH = 2048K + dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K + dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K + sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K + sram1 (rwx) : ORIGIN = 0x30000000, LENGTH = 128K + sram2 (rwx) : ORIGIN = 0x30020000, LENGTH = 128K + sram3 (rwx) : ORIGIN = 0x30040000, LENGTH = 32K + sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K + bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K +} + +OUTPUT_ARCH(arm) +EXTERN(_vectors) +ENTRY(_stext) +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : + { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Emit the the D3 power domain section for locating BDMA data + * + * Static data with locate_data(".sram4") will be located + * at start of SRAM4; the rest of SRAM4 will be added to the heap. + */ + + .sram4_reserve (NOLOAD) : + { + *(.sram4) + . = ALIGN(4); + _sram4_heap_start = ABSOLUTE(.); + } > sram4 + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32h7/weact-stm32h743/scripts/memory.ld b/boards/arm/stm32h7/weact-stm32h743/scripts/memory.ld new file mode 100644 index 0000000000000..a696c26d92ba3 --- /dev/null +++ b/boards/arm/stm32h7/weact-stm32h743/scripts/memory.ld @@ -0,0 +1,52 @@ +/**************************************************************************** + * boards/arm/stm32h7/nucleo-h743zi/scripts/memory.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* TODO: Add description for memory organisation */ + +MEMORY +{ + /* ITCM boot address */ + + itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K + + /* 2048Kb FLASH */ + + kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K + uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K + xflash (rx) : ORIGIN = 0x08040000, LENGTH = 1792K + + /* 288Kb SRAM123 */ + + ksram (rwx) : ORIGIN = 0x30000000, LENGTH = 16K + usram (rwx) : ORIGIN = 0x30004000, LENGTH = 16K + xsram (rwx) : ORIGIN = 0x30008000, LENGTH = 288K - 32K + + /* 512Kb of contiguous AXI SRAM */ + + sram (rwx) : ORIGIN = 0x24000000, LENGTH = 512K + + /* DTCM SRAM */ + + dtcm1 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K + dtcm2 (rwx) : ORIGIN = 0x20010000, LENGTH = 64K + + sram4 (rwx) : ORIGIN = 0x38000000, LENGTH = 64K + bbram (rwx) : ORIGIN = 0x38800000, LENGTH = 4K +} diff --git a/boards/arm/stm32h7/weact-stm32h743/scripts/user-space.ld b/boards/arm/stm32h7/weact-stm32h743/scripts/user-space.ld new file mode 100644 index 0000000000000..f7cdb7a37a641 --- /dev/null +++ b/boards/arm/stm32h7/weact-stm32h743/scripts/user-space.ld @@ -0,0 +1,99 @@ +/**************************************************************************** +* boards/arm/stm32h7/nucleo-h743zi/scripts/user-space.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This depends on the memory.ld script having been included prior to + * this script. + */ + +OUTPUT_ARCH(arm) +SECTIONS +{ + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + .ARM.extab : { + *(.ARM.extab*) + } > uflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > uflash + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt b/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt new file mode 100644 index 0000000000000..b4971222b0b86 --- /dev/null +++ b/boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt @@ -0,0 +1,40 @@ +# ############################################################################## +# boards/arm/stm32h7/weact-stm32h743/src/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c) + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS stm32_autoleds.c) +else() + list(APPEND SRCS stm32_userleds.c) +endif() + +if(CONFIG_BOARDCTL) + list(APPEND SRCS stm32_appinitialize.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +if(NOT CONFIG_BUILD_FLAT) + add_subdirectory(${NUTTX_BOARD_DIR}/kernel) + set_property( + GLOBAL PROPERTY LD_SCRIPT_USER ${NUTTX_BOARD_DIR}/scripts/memory.ld + ${NUTTX_BOARD_DIR}/scripts/user-space.ld) +endif() diff --git a/boards/arm/stm32h7/weact-stm32h743/src/Makefile b/boards/arm/stm32h7/weact-stm32h743/src/Makefile new file mode 100644 index 0000000000000..c80e7e486f1a2 --- /dev/null +++ b/boards/arm/stm32h7/weact-stm32h743/src/Makefile @@ -0,0 +1,35 @@ +############################################################################ +# boards/arm/stm32h7/weact-stm32h743/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = stm32_boot.c stm32_bringup.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += stm32_appinitialize.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32h7/weact-stm32h743/src/stm32_appinitialize.c b/boards/arm/stm32h7/weact-stm32h743/src/stm32_appinitialize.c new file mode 100644 index 0000000000000..6f8b9899fb364 --- /dev/null +++ b/boards/arm/stm32h7/weact-stm32h743/src/stm32_appinitialize.c @@ -0,0 +1,76 @@ +/**************************************************************************** + * boards/arm/stm32h7/weact-stm32h743/src/stm32_appinitialize.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "weact-stm32h743.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return stm32_bringup(); +#endif +} diff --git a/boards/arm/stm32h7/weact-stm32h743/src/stm32_autoleds.c b/boards/arm/stm32h7/weact-stm32h743/src/stm32_autoleds.c new file mode 100644 index 0000000000000..fbb17c505e80f --- /dev/null +++ b/boards/arm/stm32h7/weact-stm32h743/src/stm32_autoleds.c @@ -0,0 +1,111 @@ +/**************************************************************************** + * boards/arm/stm32h7/weact-stm32h743/src/stm32_autoleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include +#include + +#include "stm32_gpio.h" +#include "weact-stm32h743.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline void set_led(bool v) +{ + ledinfo("Turn LED %s\n", v? "on":"off"); + stm32_gpiowrite(GPIO_LD1, !v); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED GPIO for output */ + + stm32_configgpio(GPIO_LD1); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + ledinfo("board_autoled_on(%d)\n", led); + + switch (led) + { + case LED_STARTED: + case LED_HEAPALLOCATE: + + /* As the board provides only one soft controllable LED, we simply + * turn it on when the board boots. + */ + + set_led(true); + break; + + case LED_PANIC: + + /* For panic state, the LED is blinking */ + + set_led(true); + break; + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case LED_PANIC: + + /* For panic state, the LED is blinking */ + + set_led(false); + break; + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c b/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c new file mode 100644 index 0000000000000..4d8fd4c54d627 --- /dev/null +++ b/boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c @@ -0,0 +1,79 @@ +/**************************************************************************** + * boards/arm/stm32h7/weact-stm32h743/src/stm32_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "arm_internal.h" +#include "stm32_start.h" +#include "weact-stm32h743.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void stm32_boardinitialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() + * will be called immediately after up_initialize() is called and just + * before the initial application is started. This additional + * initialization phase may be used, for example, to initialize board- + * specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + stm32_bringup(); +} +#endif diff --git a/boards/arm/stm32h7/weact-stm32h743/src/stm32_bringup.c b/boards/arm/stm32h7/weact-stm32h743/src/stm32_bringup.c new file mode 100644 index 0000000000000..677ecb1c94e55 --- /dev/null +++ b/boards/arm/stm32h7/weact-stm32h743/src/stm32_bringup.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/arm/stm32h7/weact-stm32h743/src/stm32_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include + +#include "weact-stm32h743.h" + +#include "stm32_gpio.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y && + * CONFIG_NSH_ARCHINIT: + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void) +{ + int ret = OK; + + UNUSED(ret); + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, STM32_PROCFS_MOUNTPOINT, "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to mount the PROC filesystem: %d\n", ret); + } +#endif /* CONFIG_FS_PROCFS */ + + return OK; +} diff --git a/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h b/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h new file mode 100644 index 0000000000000..be9c3fac6ccc0 --- /dev/null +++ b/boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/stm32h7/weact-stm32h743/src/weact-stm32h743.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32H7_WEACT_STM32H743_SRC_WEACT_STM32H743_H +#define __BOARDS_ARM_STM32H7_WEACT_STM32H743_SRC_WEACT_STM32H743_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* procfs File System */ + +#ifdef CONFIG_FS_PROCFS +# ifdef CONFIG_NSH_PROC_MOUNTPOINT +# define STM32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT +# else +# define STM32_PROCFS_MOUNTPOINT "/proc" +# endif +#endif + +/* LED + * + * The WeAct STM32H743 board has only one Blue LED (E3) controlled by GPIO. + * LED E3: connected to PC3 + */ + +#define GPIO_LD1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | \ + GPIO_OUTPUT_CLEAR | GPIO_PORTE | GPIO_PIN3) + +/* BUTTONS + * + * The pushbutton K1 is connected to GPIO PC13. + */ + +#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13) + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y && + * CONFIG_NSH_ARCHINIT: + * Called from the NSH library + * + ****************************************************************************/ + +int stm32_bringup(void); + +#endif /* __BOARDS_ARM_STM32H7_WEACT_STM32H743_SRC_WEACT_STM32H743_H */ diff --git a/boards/arm/stm32l4/nucleo-l432kc/include/board.h b/boards/arm/stm32l4/nucleo-l432kc/include/board.h index 5872e806802fb..3976a7fc8e62c 100644 --- a/boards/arm/stm32l4/nucleo-l432kc/include/board.h +++ b/boards/arm/stm32l4/nucleo-l432kc/include/board.h @@ -90,13 +90,9 @@ # define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */ #endif -/* USART2: Connected to STLInk Debug via PA2(TX), PA15(RX) */ +/* USART2: Connected to STLInk Debug via PA2(TX), PA3(RX) */ -#if defined(CONFIG_ARCH_BOARD_USART2_RX_PA3) -# define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */ -#elif defined(CONFIG_ARCH_BOARD_USART2_RX_PA15) -# define GPIO_USART2_RX GPIO_USART2_RX_2 /* PA15 */ -#endif +#define GPIO_USART2_RX GPIO_USART2_RX_1 /* PA3 */ #define GPIO_USART2_TX GPIO_USART2_TX_1 /* PA2 */ #define GPIO_USART2_RTS GPIO_USART2_RTS_2 #define GPIO_USART2_CTS GPIO_USART2_CTS_2 diff --git a/boards/arm/stm32l4/nucleo-l476rg/include/board.h b/boards/arm/stm32l4/nucleo-l476rg/include/board.h index d9d7ebb9c63bc..f4af2c4509a0c 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/include/board.h +++ b/boards/arm/stm32l4/nucleo-l476rg/include/board.h @@ -67,17 +67,17 @@ /* Alternate function pin selections ****************************************/ -/* CAN1: (added 31-03 -- Ben vd Veen (DisruptiveNL) - * RXD: PA11 - * PB8 +/* CAN1: + * RXD: PA11 CN10 pin 14 + * PB8 CN5 pin 10, CN10 pin 3 * PD0 - * TXD: PA12 - * PB9 + * TXD: PA12 CN10 pin 12 + * PB9 CN5 pin 9, CN10 pin 5 * PD1 */ -#define GPIO_CAN1_RX GPIO_CAN1_RX_2 /* PA11 - AF9 */ -#define GPIO_CAN1_TX GPIO_CAN1_TX_2 /* PA12 - AF9 */ +#define GPIO_CAN1_RX GPIO_CAN1_RX_1 /* PA11 */ +#define GPIO_CAN1_TX GPIO_CAN1_TX_1 /* PA12 */ /* USART1: * RXD: PA10 CN9 pin 3, CN10 pin 33 diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/Makefile b/boards/arm/stm32l4/nucleo-l476rg/src/Makefile index 7ada3fd731471..1d25aa14bceeb 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/Makefile +++ b/boards/arm/stm32l4/nucleo-l476rg/src/Makefile @@ -85,6 +85,14 @@ ifeq ($(CONFIG_SENSORS_BMP180),y) CSRCS += stm32_bmp180.c endif +ifeq ($(CONFIG_SENSORS_BMP280),y) + CSRCS += stm32_bmp280.c +endif + +ifeq ($(CONFIG_SENSORS_MPU9250),y) + CSRCS += stm32_mpu9250.c +endif + ifeq ($(CONFIG_PWM),y) CSRCS += stm32_pwm.c endif diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_appinit.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_appinit.c index a608045332149..9b88c4088250d 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_appinit.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_appinit.c @@ -51,6 +51,14 @@ #include "stm32l4_i2c.h" +#ifdef CONFIG_SENSORS_BMP280 +#include "stm32_bmp280.h" +#endif + +#ifdef CONFIG_SENSORS_MPU9250 +#include "stm32_mpu9250.h" +#endif + /**************************************************************************** * Private Data ****************************************************************************/ @@ -429,6 +437,34 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_SENSORS_BMP280 + /* Try to register BMP280 device in I2C1 */ + + ret = board_bmp280_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize BMP280 driver: %d\n", ret); + } + else + { + syslog(LOG_ERR, "Initialized BMP280 driver: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_MPU9250 + /* Try to register MPU9250 device in I2C1 */ + + ret = board_mpu9250_initialize(0, 1); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize MPU9250 driver: %d\n", ret); + } + else + { + syslog(LOG_INFO, "Initialized MPU9250 driver: %d\n", ret); + } +#endif + return ret; } diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.c new file mode 100644 index 0000000000000..b1fdd3bb192b1 --- /dev/null +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.c @@ -0,0 +1,109 @@ +/**************************************************************************** + * boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32l4.h" +#include "stm32l4_i2c.h" +#include "stm32_bmp280.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_bmp280_initialize + * + * Description: + * Initialize and register the BMP280 Pressure Sensor driver. + * + * Input Parameters: + * devno - The device number, used to build the device path as /dev/pressN + * busno - The I2C bus number + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_bmp280_initialize(int devno, int busno) +{ + struct i2c_master_s *i2c; + int ret; + + sninfo("Initializing BMP280!\n"); + + /* Initialize BMP280 */ + + i2c = stm32l4_i2cbus_initialize(busno); + + if (i2c) + { + /* Then try to register the barometer sensor in I2Cx */ + + ret = bmp280_register(devno, i2c); + if (ret < 0) + { + snerr("ERROR: Error registering BMP280 in I2C%d\n", busno); + } + } + else + { + ret = -ENODEV; + } + + return ret; +} + diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.h b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.h new file mode 100644 index 0000000000000..b40109cee1e11 --- /dev/null +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.h @@ -0,0 +1,84 @@ +/**************************************************************************** + * boards/arm/stm32l4/nucleo-l476rg/src/stm32_bmp280.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_BMP280_H +#define __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_BMP280_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_bmp280_initialize + * + * Description: + * Initialize and register the BMP280 Pressure Sensor driver. + * + * Input Parameters: + * devno - The device number, used to build the device path as /dev/pressN + * busno - The I2C bus number + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_bmp280_initialize(int devno, int busno); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_BMP280_H */ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.c new file mode 100644 index 0000000000000..5e00927759685 --- /dev/null +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "stm32l4.h" +#include "stm32l4_i2c.h" +#include "stm32_mpu9250.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_mpu9250_initialize + * + * Description: + * Initialize and register + * MPU9250 (Gyro + Accelerometer + Compass) Sensor driver. + * + * Input Parameters: + * devno - The device number, used to build the device path as + * /dev/uorb/sensor_accelx + * /dev/uorb/sensor_gyrox + * /dev/uorb/sensor_magx + * + * busno - The I2C bus number + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_mpu9250_initialize(int devno, int busno) +{ + struct i2c_master_s *i2c; + int ret; + + sninfo("Initializing MPU9250!\n"); + + /* Initialize MPU9250 */ + + i2c = stm32l4_i2cbus_initialize(busno); + if (i2c) + { + /* Then try to register the IMU sensor in I2Cx */ + + struct mpu9250_config_s mpuc; + memset(&mpuc, 0, sizeof(mpuc)); + mpuc.i2c = i2c; + mpuc.addr = 0x68; + + ret = mpu9250_register(devno, &mpuc); + if (ret < 0) + { + snerr("ERROR: Error registering MPU9250 in I2C%d\n", busno); + } + } + else + { + ret = -ENODEV; + } + + return ret; +} diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.h b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.h new file mode 100644 index 0000000000000..8282fb1e68075 --- /dev/null +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.h @@ -0,0 +1,89 @@ +/**************************************************************************** + * boards/arm/stm32l4/nucleo-l476rg/src/stm32_mpu9250.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_MPU9250_H +#define __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_MPU9250_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_mpu9250_initialize + * + * Description: + * Initialize and register + * MPU9250 (Gyro + Accelerometer + Compass) Sensor driver. + * + * Input Parameters: + * devno - The device number, used to build the device path as + * /dev/uorb/sensor_accelx + * /dev/uorb/sensor_gyrox + * /dev/uorb/sensor_magx + * + * busno - The I2C bus number + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_mpu9250_initialize(int devno, int busno); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __BOARDS_ARM_STM32L4_NUCLEO_L476RG_INCLUDE_NUCLEO_L476RG_MPU9250_H */ diff --git a/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig b/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig index 7ec46123ce6b6..1578b6c60c84f 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig +++ b/boards/arm/stm32l4/stm32l476vg-disco/configs/nsh/defconfig @@ -25,6 +25,7 @@ CONFIG_BOARD_LOOPSPERMSEC=8499 CONFIG_BUILTIN=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_ROMFS=y CONFIG_EXAMPLES_ALARM=y CONFIG_EXAMPLES_MEDIA=y CONFIG_FS_PROCFS=y @@ -40,12 +41,10 @@ CONFIG_MTD_N25QXXX=y CONFIG_MTD_PARTITION=y CONFIG_N25QXXX_SECTOR512=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=98304 CONFIG_RAM_START=0x20000000 diff --git a/boards/arm/stm32l4/stm32l476vg-disco/include/nsh_romfsimg.h b/boards/arm/stm32l4/stm32l476vg-disco/include/nsh_romfsimg.h deleted file mode 100644 index 4d375809edeb2..0000000000000 --- a/boards/arm/stm32l4/stm32l476vg-disco/include/nsh_romfsimg.h +++ /dev/null @@ -1,109 +0,0 @@ -/*************************************************************************** - * boards/arm/stm32l4/stm32l476vg-disco/include/nsh_romfsimg.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ***************************************************************************/ - -unsigned char romfs_img[] = { - 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x01, 0x80, - 0x42, 0x56, 0x48, 0x93, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56, - 0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, - 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, - 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, - 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x68, 0x2d, 0x96, 0x03, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; -unsigned int romfs_img_len = 1024; diff --git a/boards/arm/stm32l4/stm32l476vg-disco/include/rc.sysinit.template b/boards/arm/stm32l4/stm32l476vg-disco/include/rc.sysinit.template index acbbe6da1ef6a..fd5898636fa07 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/include/rc.sysinit.template +++ b/boards/arm/stm32l4/stm32l476vg-disco/include/rc.sysinit.template @@ -1,2 +1,2 @@ # sample rc.sysinit file; you must run tools/genromfs from within this -# location to convert this file to nsh_romfsimg.h for inclusion in the build +# location to convert this file to etc_romfs.c for inclusion in the build diff --git a/boards/arm/stm32l4/stm32l476vg-disco/include/rcS.template b/boards/arm/stm32l4/stm32l476vg-disco/include/rcS.template index 1e5059e7499af..d7f1e567fc1a9 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/include/rcS.template +++ b/boards/arm/stm32l4/stm32l476vg-disco/include/rcS.template @@ -1,2 +1,2 @@ # sample rcS file; you must run tools/genromfs from within this -# location to convert this file to nsh_romfsimg.h for inclusion in the build +# location to convert this file to etc_romfs.c for inclusion in the build diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile b/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile index 0ee7033705c13..6cbc4a82c16fd 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/Makefile @@ -48,4 +48,8 @@ ifeq ($(CONFIG_BOARDCTL),y) CSRCS += stm32_appinit.c endif +ifeq ($(CONFIG_ETC_ROMFS),y) +CSRCS += etc_romfs.c +endif + include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/etc_romfs.c b/boards/arm/stm32l4/stm32l476vg-disco/src/etc_romfs.c new file mode 100644 index 0000000000000..3752422bf713c --- /dev/null +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/etc_romfs.c @@ -0,0 +1,118 @@ +/*************************************************************************** + * boards/arm/stm32l4/stm32l476vg-disco/src/etc_romfs.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ***************************************************************************/ + +/*************************************************************************** + * Public Data + ***************************************************************************/ + +unsigned char romfs_img[] = +{ + 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x01, 0x80, + 0x42, 0x56, 0x48, 0x93, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56, + 0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, + 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, + 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; +unsigned int romfs_img_len = 1024; + +/*************************************************************************** + * Public Functions + ***************************************************************************/ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig index 7f236453b9eba..5651ad4c72973 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/configs/nsh/defconfig @@ -24,6 +24,7 @@ CONFIG_BOARD_LOOPSPERMSEC=9234 CONFIG_BUILTIN=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_ROMFS=y CONFIG_EXAMPLES_ALARM=y CONFIG_EXAMPLES_MEDIA=y CONFIG_EXAMPLES_RANDOM=y @@ -41,12 +42,10 @@ CONFIG_MM_REGIONS=3 CONFIG_MTD=y CONFIG_MTD_PARTITION=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_DISABLE_IFUPDOWN=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=98304 CONFIG_RAM_START=0x20000000 diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/nsh_romfsimg.h b/boards/arm/stm32l4/stm32l4r9ai-disco/include/nsh_romfsimg.h deleted file mode 100644 index edb2dc8a56721..0000000000000 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/nsh_romfsimg.h +++ /dev/null @@ -1,109 +0,0 @@ -/*************************************************************************** - * boards/arm/stm32l4/stm32l4r9ai-disco/include/nsh_romfsimg.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ***************************************************************************/ - -unsigned char romfs_img[] = { - 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x01, 0x80, - 0x42, 0x56, 0x48, 0x93, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56, - 0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, - 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, - 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, - 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x68, 0x2d, 0x96, 0x03, 0x69, 0x6e, 0x69, 0x74, 0x2e, 0x64, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, - 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00 -}; -unsigned int romfs_img_len = 1024; diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/rc.sysinit.template b/boards/arm/stm32l4/stm32l4r9ai-disco/include/rc.sysinit.template index acbbe6da1ef6a..fd5898636fa07 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/rc.sysinit.template +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/include/rc.sysinit.template @@ -1,2 +1,2 @@ # sample rc.sysinit file; you must run tools/genromfs from within this -# location to convert this file to nsh_romfsimg.h for inclusion in the build +# location to convert this file to etc_romfs.c for inclusion in the build diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/rcS.template b/boards/arm/stm32l4/stm32l4r9ai-disco/include/rcS.template index 1e5059e7499af..d7f1e567fc1a9 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/rcS.template +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/include/rcS.template @@ -1,2 +1,2 @@ # sample rcS file; you must run tools/genromfs from within this -# location to convert this file to nsh_romfsimg.h for inclusion in the build +# location to convert this file to etc_romfs.c for inclusion in the build diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile b/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile index ea6187b90280c..6ebd296e49aab 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/Makefile @@ -61,4 +61,8 @@ ifeq ($(CONFIG_BOARDCTL),y) CSRCS += stm32_appinit.c endif +ifeq ($(CONFIG_ETC_ROMFS),y) +CSRCS += etc_romfs.c +endif + include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/etc_romfs.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/etc_romfs.c new file mode 100644 index 0000000000000..fa5387160b3aa --- /dev/null +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/etc_romfs.c @@ -0,0 +1,118 @@ +/*************************************************************************** + * boards/arm/stm32l4/stm32l4r9ai-disco/src/etc_romfs.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ***************************************************************************/ + +/*************************************************************************** + * Public Data + ***************************************************************************/ + +unsigned char romfs_img[] = +{ + 0x2d, 0x72, 0x6f, 0x6d, 0x31, 0x66, 0x73, 0x2d, 0x00, 0x00, 0x01, 0x80, + 0x42, 0x56, 0x48, 0x93, 0x4e, 0x53, 0x48, 0x49, 0x6e, 0x69, 0x74, 0x56, + 0x6f, 0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x49, + 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xd1, 0xff, 0xff, 0x97, + 0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, 0x20, + 0x00, 0x00, 0x00, 0x00, 0xd1, 0xd1, 0xff, 0x80, 0x2e, 0x2e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 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0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; +unsigned int romfs_img_len = 1024; + +/*************************************************************************** + * Public Functions + ***************************************************************************/ diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/CMakeLists.txt b/boards/arm/stm32u5/nucleo-u5a5zj-q/CMakeLists.txt new file mode 100644 index 0000000000000..1168a509fb5cd --- /dev/null +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/CMakeLists.txt @@ -0,0 +1,21 @@ +# ############################################################################## +# boards/arm/stm32u5/nucleo-u5a5zj-q/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/scripts/Make.defs b/boards/arm/stm32u5/nucleo-u5a5zj-q/scripts/Make.defs index c368f3902b209..9476b26687d43 100644 --- a/boards/arm/stm32u5/nucleo-u5a5zj-q/scripts/Make.defs +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################## -# boards/arm/stm32u5/b-u585i-iot02a/scripts/Make.defs +# boards/arm/stm32u5/nucleo-u5a5zj-q/scripts/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt new file mode 100644 index 0000000000000..b60ca95d09e69 --- /dev/null +++ b/boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt @@ -0,0 +1,34 @@ +# ############################################################################## +# boards/arm/stm32u5/nucleo-u5a5zj-q/src/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS stm32_boot.c stm32_bringup.c stm32_spi.c) + +if(CONFIG_BOARDCTL) + list(APPEND SRCS stm32_appinit.c) +endif() + +if(CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG) + list(APPEND SRCS stm32_clockconfig.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +# TODO: make this the default and then allow boards to redefine +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/tiva/dk-tm4c129x/tools/oocd.sh b/boards/arm/tiva/dk-tm4c129x/tools/oocd.sh index ad0281ffd739c..45db5429096f6 100755 --- a/boards/arm/tiva/dk-tm4c129x/tools/oocd.sh +++ b/boards/arm/tiva/dk-tm4c129x/tools/oocd.sh @@ -1,6 +1,6 @@ #!/usr/bin/env bash # -# See boards/arm/tiva/dk-tm4c129x/README.txt for information about +# See Documentation/platforms/arm/tiva/boards/dk-tm4c129x/README.txt for information about # this file. TOPDIR=$1 diff --git a/boards/arm/tiva/lm3s6965-ek/CMakeLists.txt b/boards/arm/tiva/lm3s6965-ek/CMakeLists.txt index d2081c5c05e49..43e258b869a01 100644 --- a/boards/arm/tiva/lm3s6965-ek/CMakeLists.txt +++ b/boards/arm/tiva/lm3s6965-ek/CMakeLists.txt @@ -20,7 +20,7 @@ add_subdirectory(src) -if(NOT CONFIG_BUILD_FLAT) +if(CONFIG_BUILD_PROTECTED) add_subdirectory(kernel) set_property( GLOBAL PROPERTY LD_SCRIPT_USER ${CMAKE_CURRENT_LIST_DIR}/scripts/memory.ld diff --git a/boards/arm/tiva/lm3s6965-ek/kernel/CMakeLists.txt b/boards/arm/tiva/lm3s6965-ek/kernel/CMakeLists.txt new file mode 100644 index 0000000000000..fa755dfe96f3d --- /dev/null +++ b/boards/arm/tiva/lm3s6965-ek/kernel/CMakeLists.txt @@ -0,0 +1,21 @@ +# ############################################################################## +# boards/arm/tiva/lm3s6965-ek/kernel/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +target_sources(nuttx_user PRIVATE lm_userspace.c) diff --git a/boards/arm/tiva/lm3s6965-ek/tools/oocd.sh b/boards/arm/tiva/lm3s6965-ek/tools/oocd.sh index 5d8a9ba1275f0..c73c6be4d5c87 100755 --- a/boards/arm/tiva/lm3s6965-ek/tools/oocd.sh +++ b/boards/arm/tiva/lm3s6965-ek/tools/oocd.sh @@ -1,6 +1,6 @@ #!/usr/bin/env bash # -# See boards/arm/tiva/lm3s6965-ek/README.txt for information about +# See Documentation/platforms/arm/tiva/boards/lm3s6965-ek/README.txt for information about # this file. TOPDIR=$1 diff --git a/boards/arm/tiva/lm4f120-launchpad/tools/oocd.sh b/boards/arm/tiva/lm4f120-launchpad/tools/oocd.sh index d7726bdd424c5..c7c57bcde2c63 100755 --- a/boards/arm/tiva/lm4f120-launchpad/tools/oocd.sh +++ b/boards/arm/tiva/lm4f120-launchpad/tools/oocd.sh @@ -1,6 +1,6 @@ #!/usr/bin/env bash # -# See boards/arm/tiva/lm4f120-launchpad/README.txt for information about +# See Documentation/platforms/arm/tiva/boards/lm4f120-launchpad/README.txt for information about # this file. TOPDIR=$1 diff --git a/boards/arm/tiva/tm4c123g-launchpad/tools/oocd.sh b/boards/arm/tiva/tm4c123g-launchpad/tools/oocd.sh index 3ffd6ec9a65e6..c061313edad53 100755 --- a/boards/arm/tiva/tm4c123g-launchpad/tools/oocd.sh +++ b/boards/arm/tiva/tm4c123g-launchpad/tools/oocd.sh @@ -1,6 +1,6 @@ #!/usr/bin/env bash # -# See boards/arm/tiva/tm4c123g-launchpad/README.txt for information about +# See Documentation/platforms/arm/tiva/boards/tm4c123g-launchpad/README.txt for information about # this file. TOPDIR=$1 diff --git a/boards/arm/tiva/tm4c1294-launchpad/tools/oocd.sh b/boards/arm/tiva/tm4c1294-launchpad/tools/oocd.sh index 796f6ef396554..50fac61985ce2 100755 --- a/boards/arm/tiva/tm4c1294-launchpad/tools/oocd.sh +++ b/boards/arm/tiva/tm4c1294-launchpad/tools/oocd.sh @@ -1,6 +1,6 @@ #!/usr/bin/env bash # -# See boards/arm/tiva/tm4c1294-launchpad/README.txt for information about +# See Documentation/platforms/arm/tiva/boards/tm4c1294-launchpad/README.txt for information about # this file. TOPDIR=$1 diff --git a/boards/arm/tiva/tm4c129e-launchpad/tools/oocd.sh b/boards/arm/tiva/tm4c129e-launchpad/tools/oocd.sh index f9b2e6522db8c..a8c66c0db00f6 100755 --- a/boards/arm/tiva/tm4c129e-launchpad/tools/oocd.sh +++ b/boards/arm/tiva/tm4c129e-launchpad/tools/oocd.sh @@ -1,6 +1,6 @@ #!/usr/bin/env bash # -# See boards/arm/tiva/tm4c129e-launchpad/README.txt for information about +# See Documentation/platforms/arm/tiva/boards/tm4c129e-launchpad/README.txt for information about # this file. TOPDIR=$1 diff --git a/boards/arm/tlsr82/tlsr8278adk80d/configs/nsh/defconfig b/boards/arm/tlsr82/tlsr8278adk80d/configs/nsh/defconfig index 85f7d839efa76..64f59202a1aec 100644 --- a/boards/arm/tlsr82/tlsr8278adk80d/configs/nsh/defconfig +++ b/boards/arm/tlsr82/tlsr8278adk80d/configs/nsh/defconfig @@ -24,7 +24,6 @@ # CONFIG_NSH_DISABLE_ECHO is not set # CONFIG_NSH_DISABLE_EXIT is not set # CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_HELP is not set # CONFIG_NSH_DISABLE_ITEF is not set # CONFIG_NSH_DISABLE_KILL is not set # CONFIG_NSH_DISABLE_LOOPS is not set diff --git a/boards/arm/tlsr82/tlsr8278adk80d/scripts/flash_boot.ld b/boards/arm/tlsr82/tlsr8278adk80d/scripts/flash_boot.ld index d5f5dba405363..a498297402e2c 100644 --- a/boards/arm/tlsr82/tlsr8278adk80d/scripts/flash_boot.ld +++ b/boards/arm/tlsr82/tlsr8278adk80d/scripts/flash_boot.ld @@ -110,6 +110,15 @@ SECTIONS PROVIDE(_end_data_ = . ); } + /* data in ram but no need to clean in .s*/ + + .noinit (NOLOAD) : + { + . = ALIGN(4); + *(.noinit) + *(.noinit.*) + } + .bss : { . = ALIGN(4); @@ -120,14 +129,6 @@ SECTIONS *(.bss.*) } - /* data in ram but no need to clean in .s*/ - - .noinit (NOLOAD) : - { - . = ALIGN(4); - *(.noinit) - *(.noinit.*) - } . = ALIGN(4); PROVIDE(_ebss = .); diff --git a/boards/arm/tlsr82/tlsr8278adk80d/scripts/flash_boot_ble.ld b/boards/arm/tlsr82/tlsr8278adk80d/scripts/flash_boot_ble.ld index 8c1ecdd6dfb2c..822f0b0fe790a 100644 --- a/boards/arm/tlsr82/tlsr8278adk80d/scripts/flash_boot_ble.ld +++ b/boards/arm/tlsr82/tlsr8278adk80d/scripts/flash_boot_ble.ld @@ -187,6 +187,15 @@ SECTIONS PROVIDE(_end_data_ = . ); } + /* data in ram but no need to clean in .s*/ + + .noinit (NOLOAD) : + { + . = ALIGN(4); + *(.noinit) + *(.noinit.*) + } + .bss : { . = ALIGN(4); @@ -197,14 +206,6 @@ SECTIONS *(.bss.*) } - /* data in ram but no need to clean in .s*/ - - .noinit (NOLOAD) : - { - . = ALIGN(4); - *(.noinit) - *(.noinit.*) - } . = ALIGN(4); PROVIDE(_ebss = .); diff --git a/boards/arm/tms570/tms570ls31x-usb-kit/include/nsh_romfsimg.h b/boards/arm/tms570/tms570ls31x-usb-kit/include/nsh_romfsimg.h deleted file mode 100644 index 3c51fc8af568e..0000000000000 --- a/boards/arm/tms570/tms570ls31x-usb-kit/include/nsh_romfsimg.h +++ /dev/null @@ -1,41 +0,0 @@ -/**************************************************************************** - * boards/arm/tms570/tms570ls31x-usb-kit/include/nsh_romfsimg.h - * Copyright (C) 2013 PX4 Development Team. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name PX4 nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -/* nsh_romfsetc.h - * - * This file is a stub for 'make export' purposes; the actual ROMFS - * must be supplied by the library client. - */ - -extern unsigned char romfs_img[]; -extern unsigned int romfs_img_len; diff --git a/boards/arm/tms570/tms570ls31x-usb-kit/src/CMakeLists.txt b/boards/arm/tms570/tms570ls31x-usb-kit/src/CMakeLists.txt index 68002509aa93d..c241d8ea75185 100644 --- a/boards/arm/tms570/tms570ls31x-usb-kit/src/CMakeLists.txt +++ b/boards/arm/tms570/tms570ls31x-usb-kit/src/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# boards/arm/tms570/tms570ls31x-usb-kit/CMakeLists.txt +# boards/arm/tms570/tms570ls31x-usb-kit/src/CMakeLists.txt # # Licensed to the Apache Software Foundation (ASF) under one or more contributor # license agreements. See the NOTICE file distributed with this work for diff --git a/boards/arm/xmc4/xmc4500-relax/scripts/flash.ld b/boards/arm/xmc4/xmc4500-relax/scripts/flash.ld index 803890beccc37..6c532d30334f4 100644 --- a/boards/arm/xmc4/xmc4500-relax/scripts/flash.ld +++ b/boards/arm/xmc4/xmc4500-relax/scripts/flash.ld @@ -86,6 +86,15 @@ SECTIONS _edata = ABSOLUTE(.); } > sram AT > flash + /* Global data not cleared after reset. */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > sram + .bss : { _sbss = ABSOLUTE(.); @@ -96,15 +105,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > sram - /* Global data not cleared after reset. */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > sram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/xmc4/xmc4700-relax/scripts/flash.ld b/boards/arm/xmc4/xmc4700-relax/scripts/flash.ld index 6619531a2be59..8c3383516c5f2 100644 --- a/boards/arm/xmc4/xmc4700-relax/scripts/flash.ld +++ b/boards/arm/xmc4/xmc4700-relax/scripts/flash.ld @@ -91,6 +91,15 @@ SECTIONS _edata = ABSOLUTE(.); } > sram AT > flash + /* Global data not cleared after reset. */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > sram + .bss : { _sbss = ABSOLUTE(.); @@ -101,15 +110,6 @@ SECTIONS _ebss = ABSOLUTE(.); } > sram - /* Global data not cleared after reset. */ - - .noinit : - { - _snoinit = ABSOLUTE(.); - *(.noinit*) - _enoinit = ABSOLUTE(.); - } > sram - /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/arm/xmc4/xmc4800-relax/CMakeLists.txt b/boards/arm/xmc4/xmc4800-relax/CMakeLists.txt new file mode 100644 index 0000000000000..0822bfc3335e0 --- /dev/null +++ b/boards/arm/xmc4/xmc4800-relax/CMakeLists.txt @@ -0,0 +1,21 @@ +# ############################################################################## +# boards/arm/xmc4/xmc4800-relax/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/arm/xmc4/xmc4800-relax/Kconfig b/boards/arm/xmc4/xmc4800-relax/Kconfig new file mode 100644 index 0000000000000..9ca693408546d --- /dev/null +++ b/boards/arm/xmc4/xmc4800-relax/Kconfig @@ -0,0 +1,14 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_XMC4800RELAX + +config ECAT + bool "Enable EtherCAT interface" + default y + ---help--- + Enable start up of the EtherCAT interface and configure ports. + +endif diff --git a/boards/arm/xmc4/xmc4800-relax/configs/nsh/defconfig b/boards/arm/xmc4/xmc4800-relax/configs/nsh/defconfig new file mode 100644 index 0000000000000..b96ceae5a222c --- /dev/null +++ b/boards/arm/xmc4/xmc4800-relax/configs/nsh/defconfig @@ -0,0 +1,43 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_RAMFUNCS is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="xmc4800-relax" +CONFIG_ARCH_BOARD_XMC4800RELAX=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="xmc4" +CONFIG_ARCH_CHIP_XMC4800=y +CONFIG_ARCH_CHIP_XMC4=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=8000 +CONFIG_BUILTIN=y +CONFIG_DEBUG_NOOPT=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=65536 +CONFIG_RAM_START=0x20000000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=10 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2014 +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_RAMTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_XMC4_USIC0=y +CONFIG_XMC4_USIC0_CHAN1_NONE=y diff --git a/boards/arm/xmc4/xmc4800-relax/include/board.h b/boards/arm/xmc4/xmc4800-relax/include/board.h new file mode 100644 index 0000000000000..e3af15469f372 --- /dev/null +++ b/boards/arm/xmc4/xmc4800-relax/include/board.h @@ -0,0 +1,392 @@ +/**************************************************************************** + * boards/arm/xmc4/xmc4800-relax/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_XMC4_XMC4800_RELAX_INCLUDE_BOARD_H +#define __BOARDS_ARM_XMC4_XMC4800_RELAX_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +/* The maximum frequency for the XMC4800 is 144MHz. */ + +#undef BOARD_FCPU_120MHZ +#define BOARD_FCPU_144MHZ 1 + +/* Watchdog clock source selection */ + +#define WDT_CLKSRC_FOFI 0 /* fOFI clock */ +#define WDT_CLKSRC_FSTDY 1 /* fSTDY clock */ +#define WDT_CLKSRC_FPLL 2 /* fPLL clock */ + +/* External Clock source selection */ + +#define EXT_CLKSRC_FSYS 0 /* fSYS clock */ +#define EXT_CLKSRC_FUSB 2 /* fUSB clock divided by ECKDIV */ +#define EXT_CLKSRC_FPLL 3 /* fPLL clock divided by ECKDIV */ + +/* Factory Calibration */ + +#undef BOARD_FOFI_CALIBRATION /* Enable factory calibration */ + +/* On-board crystals */ + +#define BOARD_XTAL_FREQUENCY 12000000 /* 12MHz XTAL */ +#define BOARD_RTC_XTAL_FREQUENCY 32769 /* 32.768KHz RTC XTAL */ + +/* TODO: enable the RTC osc, use RTC for time/date + */ + +/* Select the external crystal as the PLL clock source */ + +#define BOARD_PLL_CLOCKSRC_XTAL 1 /* PLL Clock source == extnernal crystal */ +#undef BOARD_PLL_CLOCKSRC_OFI /* PLL Clock source != internal fast oscillator */ + +/* PLL Configuration: + * + * fXTAL = 12Mhz + * 260 MHz <= fVCO <= 520 MHz + * + * fVCO = fXTAL * ndiv / pdiv + * fPLL = fVCO / k2div + * fSYS = fPLL / sysdiv + * fETH = fSYS / 2 (fixed div by 2) + * fCCU = fSYS / ccudiv (div by 1 or 2) + * fCPU = fSYS / cpudiv (div by 1 or 2) + * fPERIPH = fCPU / pbdiv (div by 1 or 2) + */ + +#define BOARD_ENABLE_PLL 1 /* enable the PLL */ +#define CPU_FREQ 120 /* MHz */ + +/* TODO: Automate PLL calculations */ + +#if CPU_FREQ == 120 + +/* 120 MHz + * + * fVCO = 12MHz * 40 / 2 = 480MHz + * fPLL = 480MHz / 2 = 240MHz + * fSYS = fPLL / 2 = 120MHz + * fCCU = fSYS / 2 = 60MHz + * fCPU = fSYS / 1 = 120MHz + * fPB = fCPU / 2 = 60MHz + * fETH = fSYS / 2 = 60MHz + */ + +# define BOARD_PLL_NDIV 40 +# define BOARD_PLL_PDIV 1 +# define BOARD_PLL_K2DIV 4 +# define BOARD_PLL_SYSDIV 1 +# define BOARD_PLL_CPUDIV 1 +# define BOARD_PLL_PBDIV 2 +# define BOARD_PLL_CCUDIV 2 +# define BOARD_PLL_EBUDIV 4 + +#elif CPU_FREQ == 144 + +/* 144 MHz + * + * fVCO = 12MHz * 36 / 1 = 432MHz + * fPLL = 432MHz / 3 = 144MHz + * fSYS = fPLL / 1 = 144MHz + * fCCU = fSYS / 2 = 72MHz + * fCPU = fSYS / 1 = 144MHz + * fPB = fCPU / 2 = 72MHz + * fETH = fSYS / 2 = 72MHz + */ + +# define BOARD_PLL_NDIV 36 +# define BOARD_PLL_PDIV 1 +# define BOARD_PLL_K2DIV 3 +# define BOARD_PLL_SYSDIV 1 +# define BOARD_PLL_CPUDIV 1 +# define BOARD_PLL_PBDIV 2 +# define BOARD_PLL_CCUDIV 2 +# define BOARD_PLL_EBUDIV 2 + +#else +# error "Illegal or Unsupported CPU Frequency" +#endif + +# define BOARD_CCUDIV_ENABLE (BOARD_PLL_CCUDIV - 1) +# define BOARD_CPUDIV_ENABLE (BOARD_PLL_CPUDIV - 1) + +# define BOARD_VCO_FREQUENCY (BOARD_XTAL_FREQUENCY * BOARD_PLL_NDIV / BOARD_PLL_PDIV) +# define BOARD_PLL_FREQUENCY (BOARD_VCO_FREQUENCY / BOARD_PLL_K2DIV) +# define BOARD_SYS_FREQUENCY (BOARD_PLL_FREQUENCY / BOARD_PLL_SYSDIV) +# define BOARD_CCU_FREQUENCY (BOARD_SYS_FREQUENCY / BOARD_PLL_CCUDIV) +# define BOARD_CPU_FREQUENCY (BOARD_SYS_FREQUENCY / BOARD_PLL_CPUDIV) +# define BOARD_PERIPH_FREQUENCY (BOARD_CPU_FREQUENCY / BOARD_PLL_PBDIV) +# define BOARD_ETH_FREQUENCY (BOARD_SYS_FREQUENCY / 2) + +# define BOARD_WDT_SOURCE WDT_CLKSRC_FOFI +# define BOARD_WDTDIV 1 +# define BOARD_WDT_FREQUENCY 24000000 + +# define BOARD_EXT_SOURCE EXT_CLKSRC_FPLL +# define BOARD_PLL_ECKDIV 480 /* [1,512] */ + +# define kHz_1 1000 +# define MHz_1 (kHz_1 * kHz_1) +# define MHz_50 ( 50 * MHz_1) +# define MHz_260 (260 * MHz_1) +# define MHz_520 (520 * MHz_1) + +/* range check VCO frequency */ + +# if (BOARD_VCO_FREQUENCY < MHz_260) +# error "VCO freq must be >= 260 MHz" +# endif + +# if (BOARD_VCO_FREQUENCY > MHz_520) +# error "VCO freq must be <= 520 MHz" +# endif + +/* range check Ethernet MAC frequency */ + +# if (BOARD_ETH_FREQUENCY <= MHz_50) +# error "ETH freq must be > 50 MHz" +# endif + +/* check ccudiv cpudiv pbdiv against Table 11-5 + * of XMC4800 User Manual + */ + +#define CLKDIV_INDEX (4 * (BOARD_PLL_CCUDIV-1) + \ + 2 * (BOARD_PLL_CPUDIV-1) + \ + (BOARD_PLL_PBDIV-1) ) + +#if (CLKDIV_INDEX == 3) || (CLKDIV_INDEX == 4) || (CLKDIV_INDEX > 6) +# error "Illegal combination of dividers! Ref: Table 11-5 of UM" +#endif + +/* EXT clock settings */ + +#define BOARD_EXTCKL_ENABLE 1 /* 0 disables output */ + +#if BOARD_EXTCKL_ENABLE +# define EXTCLK_PIN_P0_8 8 +# define EXTCLK_PIN_P1_15 15 +# define BOARD_EXTCLK_PIN EXTCLK_PIN_P0_8 +# define BOARD_EXT_SOURCE EXT_CLKSRC_FPLL +# define BOARD_EXT_FREQUENCY (250 * kHz_1) /* Desired output freq */ +# define BOARD_EXTDIV (BOARD_PLL_FREQUENCY / BOARD_EXT_FREQUENCY) + +/* range check EXTDIV */ + +# if BOARD_EXTDIV > 512 +# error "EXTCLK Divisor out of range!" +# endif +#endif + +/* Standby clock source selection + * + * BOARD_STDBY_CLOCKSRC_OSI - Internal 32.768KHz slow oscillator + * BOARD_STDBY_CLOCKSRC_OSCULP - External 32.768KHz crystal + */ + +#define BOARD_STDBY_CLOCKSRC_OSI 1 +#undef BOARD_STDBY_CLOCKSRC_OSCULP +#define BOARD_STDBY_FREQUENCY 32768 + +/* USB PLL settings. + * + * fUSBPLL = 48MHz and fUSBPLLVCO = 384 MHz + * + * Note: Implicit divider of 2 and fUSBPLLVCO >= 260 MHz and + * fUSBPLLVCO <= 520 MHz + */ + +#define BOARD_ENABLE_USBPLL +#define BOARD_USB_PDIV 3 +#define BOARD_USB_NDIV 100 + +/* FLASH wait states */ + +#define BOARD_FLASH_WS 5 + +/* LED definitions **********************************************************/ + +/* The XMC4800 Relax board has two LEDs: + * + * LED1 P5.9 High output illuminates + * LED2 P5.8 High output illuminates + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. + * The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED0 0 +#define BOARD_LED1 1 +#define BOARD_NLEDS 2 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED0_BIT (1 << BOARD_LED0) +#define BOARD_LED1_BIT (1 << BOARD_LED1) + +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * + * SYMBOL Meaning LED state + * LED2 LED1 + * --------------------- -------------------------- ------ ------ + */ + +#define LED_STARTED 0 /* NuttX has been started OFF OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON OFF */ +#define LED_INIRQ 2 /* In an interrupt No change */ +#define LED_SIGNAL 2 /* In a signal handler No change */ +#define LED_ASSERTION 2 /* An assertion failed No change */ +#define LED_PANIC 3 /* The system has crashed N/C Blinking */ +#undef LED_IDLE /* MCU is is sleep mode Not used */ + +/* Thus if LED1 is statically on, NuttX has successfully booted and is, + * apparently, running normally. If LED2 is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/* Button definitions *******************************************************/ + +/* The XMC4800 Relax board has two buttons: + * + * BUTTON1 P15.13 Low input sensed when button pressed + * BUTTON2 P15.12 Low input sensed when button pressed + */ + +#define BUTTON_0 0 +#define BUTTON_1 1 +#define NUM_BUTTONS 2 + +#define BUTTON_0_BIT (1 << BUTTON_0) +#define BUTTON_1_BIT (1 << BUTTON_1) + +/* USIC0 ********************************************************************/ + +/* USIC0 CH0 is used as UART0 + * + * RX - P1.4 + * TX - P1.5 + */ + +#define BOARD_UART0_DX USIC_DXB +#define GPIO_UART0_RXD GPIO_U0C0_DX0B +#define GPIO_UART0_TXD (GPIO_U0C0_DOUT0_3 | GPIO_PADA1P_STRONGSOFT | GPIO_OUTPUT_SET) + +/* USIC2 CH0 is used as SPI4 + * + * MOSI - P3.8 (UC2C0.DOUT0) + * MISO - P3.7 (UC2C0.DX0C) + * SCLK - P3.9 (UC2C0.SCLKOUT) + */ + +#define BOARD_SPI_DX USIC_DXC +#define GPIO_SPI4_MOSI (GPIO_U2C0_DOUT0_2 | GPIO_PADA2_STRONGMEDIUM) +#define GPIO_SPI4_MISO (GPIO_U2C0_DX0C) +#define GPIO_SPI4_SCLK (GPIO_U2C0_SCLKOUT_1 | GPIO_PADA2_STRONGMEDIUM) + +/* ECAT0 configuration */ + +#define ECAT_CLK_25 GPIO_ECAT_CLK_25_1 +#define ECAT_LED_ERR GPIO_ECAT_LED_ERR +#define ECAT_LED_RUN GPIO_ECAT_LED_RUN +#define ECAT_MCLK GPIO_ECAT_MCLK +#define ECAT_MDO GPIO_ECAT_MDO +#define ECAT_PHY_RESET GPIO_ECAT_PHY_RESET + +#define ECAT_P0_LED_LINK_ACT GPIO_ECAT_P0_LED_LINK_ACT_1 +#define ECAT_P0_LINK_STATUS GPIO_ECAT_P0_LINK_STATUS +#define ECAT_P0_RXD0 GPIO_ECAT_P0_RXD0_1 +#define ECAT_P0_RXD1 GPIO_ECAT_P0_RXD1_1 +#define ECAT_P0_RXD2 GPIO_ECAT_P0_RXD2_1 +#define ECAT_P0_RXD3 GPIO_ECAT_P0_RXD3_1 +#define ECAT_P0_RX_CLK GPIO_ECAT_P0_RX_CLK_1 +#define ECAT_P0_RX_DV GPIO_ECAT_P0_RX_DV_1 +#define ECAT_P0_RX_ERR GPIO_ECAT_P0_RX_ERR +#define ECAT_P0_TX_CLK GPIO_ECAT_P0_TX_CLK_1 +#define ECAT_P0_TXD0 GPIO_ECAT_P0_TXD0_1 +#define ECAT_P0_TXD1 GPIO_ECAT_P0_TXD1_1 +#define ECAT_P0_TXD2 GPIO_ECAT_P0_TXD2_1 +#define ECAT_P0_TXD3 GPIO_ECAT_P0_TXD3_1 +#define ECAT_P0_TX_EN GPIO_ECAT_P0_TX_EN_1 + +#define ECAT_P1_LED_LINK_ACT GPIO_ECAT_P1_LED_LINK_ACT_1 +#define ECAT_P1_LINK_STATUS GPIO_ECAT_P1_LINK_STATUS_1 +#define ECAT_P1_RXD0 GPIO_ECAT_P1_RXD0_1 +#define ECAT_P1_RXD1 GPIO_ECAT_P1_RXD1_1 +#define ECAT_P1_RXD2 GPIO_ECAT_P1_RXD2_1 +#define ECAT_P1_RXD3 GPIO_ECAT_P1_RXD3_1 +#define ECAT_P1_RX_CLK GPIO_ECAT_P1_RX_CLK_1 +#define ECAT_P1_RX_DV GPIO_ECAT_P1_RX_DV_1 +#define ECAT_P1_RX_ERR GPIO_ECAT_P1_RX_ERR_1 +#define ECAT_P1_TX_CLK GPIO_ECAT_P1_TX_CLK +#define ECAT_P1_TXD0 GPIO_ECAT_P1_TXD0 +#define ECAT_P1_TXD1 GPIO_ECAT_P1_TXD1 +#define ECAT_P1_TXD2 GPIO_ECAT_P1_TXD2 +#define ECAT_P1_TXD3 GPIO_ECAT_P1_TXD3 +#define ECAT_P1_TX_EN GPIO_ECAT_P1_TX_EN + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_XMC4_XMC4800_RELAX_INCLUDE_BOARD_H */ diff --git a/boards/arm/xmc4/xmc4800-relax/scripts/Make.defs b/boards/arm/xmc4/xmc4800-relax/scripts/Make.defs new file mode 100644 index 0000000000000..2de14ea75bb8d --- /dev/null +++ b/boards/arm/xmc4/xmc4800-relax/scripts/Make.defs @@ -0,0 +1,46 @@ +############################################################################ +# boards/arm/xmc4/xmc4800-relax/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = flash.ld +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs + +LDMODULEFLAGS = -r -e module_initialize +LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld) diff --git a/boards/arm/xmc4/xmc4800-relax/scripts/flash.ld b/boards/arm/xmc4/xmc4800-relax/scripts/flash.ld new file mode 100644 index 0000000000000..0b3bdd380462d --- /dev/null +++ b/boards/arm/xmc4/xmc4800-relax/scripts/flash.ld @@ -0,0 +1,127 @@ +/**************************************************************************** + * boards/arm/xmc4/xmc4800-relax/scripts/flash.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + * + ****************************************************************************/ + +/* The XMC4800 has 2048Kb of FLASH accessible via: +* 1) the cacheable address space at 0x0800:0000 +* 2) the non-cacheable address space at 0x0c00:0000 +* +* The on-chip SRAM is split up into three blocks: +* 1) 96Kb of program memory beginning at the address 0x1ffe:8000 +* 2) 128Kb of data memory beginning at the address 0x2000:0000 +* 3) 128Kb of communication memory beginning at the address 0x2002:0000 +*/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x0c000000, LENGTH = 2048K + psram (rwx) : ORIGIN = 0x1ffe8000, LENGTH = 96K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K + dsram1 (rwx) : ORIGIN = 0x20000000, LENGTH = 128K + dsram2 (rwx) : ORIGIN = 0x20020000, LENGTH = 128K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : + { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : + { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > sram AT > flash + + /* Global data not cleared after reset. */ + + .noinit : + { + _snoinit = ABSOLUTE(.); + *(.noinit*) + _enoinit = ABSOLUTE(.); + } > sram + + .bss : + { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/arm/xmc4/xmc4800-relax/src/CMakeLists.txt b/boards/arm/xmc4/xmc4800-relax/src/CMakeLists.txt new file mode 100644 index 0000000000000..709b4c9c0ca6d --- /dev/null +++ b/boards/arm/xmc4/xmc4800-relax/src/CMakeLists.txt @@ -0,0 +1,43 @@ +# ############################################################################## +# boards/arm/xmc4/xmc4800-relax/src/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS xmc4_boot.c xmc4_bringup.c) + +if(CONFIG_INPUT_BUTTONS) + list(APPEND SRCS xmc4_buttons.c) +endif() + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS xmc4_autoleds.c) +else() + list(APPEND SRCS xmc4_userleds.c) +endif() + +if(CONFIG_XMC4_USCI_SPI) + list(APPEND SRCS xmc4_spi.c) +endif() + +if(CONFIG_BOARDCTL) + list(APPEND SRCS xmc4_appinit.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/flash.ld") diff --git a/boards/arm/xmc4/xmc4800-relax/src/Makefile b/boards/arm/xmc4/xmc4800-relax/src/Makefile new file mode 100644 index 0000000000000..2138d5de4a3dd --- /dev/null +++ b/boards/arm/xmc4/xmc4800-relax/src/Makefile @@ -0,0 +1,43 @@ +############################################################################ +# boards/arm/xmc4/xmc4800-relax/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = xmc4_boot.c xmc4_bringup.c + +ifeq ($(CONFIG_INPUT_BUTTONS),y) +CSRCS += xmc4_buttons.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += xmc4_autoleds.c +else +CSRCS += xmc4_userleds.c +endif + +ifeq ($(CONFIG_XMC4_USCI_SPI),y) +CSRCS += xmc4_spi.c +endif + +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += xmc4_appinit.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm/xmc4/xmc4800-relax/src/xmc4800-relax.h b/boards/arm/xmc4/xmc4800-relax/src/xmc4800-relax.h new file mode 100644 index 0000000000000..e47b8cab839d0 --- /dev/null +++ b/boards/arm/xmc4/xmc4800-relax/src/xmc4800-relax.h @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/arm/xmc4/xmc4800-relax/src/xmc4800-relax.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM_XMC4_XMC4800_RELAX_SRC_XMC4800_RELAX_H +#define __BOARDS_ARM_XMC4_XMC4800_RELAX_SRC_XMC4800_RELAX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "xmc4_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LEDs + * + * The XMC4800 Relax board has two LEDs: + * + * LED1 P5.9, Pad type A1+, High output illuminates + * LED2 P5.8, Pad type A1+ High output illuminates + */ + +#define GPIO_LED1 (GPIO_OUTPUT | GPIO_OUTPUT_PUSHPULL | \ + GPIO_PADA1P_STRONGSOFT | GPIO_PINCTRL_SOFTWARE | \ + GPIO_OUTPUT_CLEAR | GPIO_PORT5 | GPIO_PIN9) +#define GPIO_LED2 (GPIO_OUTPUT | GPIO_OUTPUT_PUSHPULL | \ + GPIO_PADA1P_STRONGSOFT | GPIO_PINCTRL_SOFTWARE | \ + GPIO_OUTPUT_CLEAR | GPIO_PORT5 | GPIO_PIN8) + +/* BUTTONS + * + * The XMC4800 Relax board has two buttons: + * + * BUTTON1 P15.13, Pad type A2, Low input sensed when button pressed + * BUTTON2 P15.12, Pad type A2, Low input sensed when button pressed + */ + +#define GPIO_BUTTON1 (GPIO_INPUT | GPIO_PINCTRL_SOFTWARE | \ + GPIO_PORT15 | GPIO_PIN13) +#define GPIO_BUTTON2 (GPIO_INPUT | GPIO_PINCTRL_SOFTWARE | \ + GPIO_PORT15 | GPIO_PIN12) + +/* SPIs Chip select */ + +#define GPIO_CS (GPIO_OUTPUT | GPIO_OUTPUT_PUSHPULL | \ + GPIO_PADA1P_STRONGSOFT | GPIO_PINCTRL_SOFTWARE | \ + GPIO_OUTPUT_SET | GPIO_PORT3 | GPIO_PIN10) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int xmc4_bringup(void); + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM_XMC4_XMC4800_RELAX_SRC_XMC4800_RELAX_H */ diff --git a/boards/arm/xmc4/xmc4800-relax/src/xmc4_appinit.c b/boards/arm/xmc4/xmc4800-relax/src/xmc4_appinit.c new file mode 100644 index 0000000000000..0e18b041b24a4 --- /dev/null +++ b/boards/arm/xmc4/xmc4800-relax/src/xmc4_appinit.c @@ -0,0 +1,71 @@ +/**************************************************************************** + * boards/arm/xmc4/xmc4800-relax/src/xmc4_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "xmc4800-relax.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifndef CONFIG_BOARD_LATE_INITIALIZE + /* Perform board initialization */ + + return xmc4_bringup(); +#else + return OK; +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ +} diff --git a/boards/arm/xmc4/xmc4800-relax/src/xmc4_autoleds.c b/boards/arm/xmc4/xmc4800-relax/src/xmc4_autoleds.c new file mode 100644 index 0000000000000..683bc786a5c37 --- /dev/null +++ b/boards/arm/xmc4/xmc4800-relax/src/xmc4_autoleds.c @@ -0,0 +1,177 @@ +/**************************************************************************** + * boards/arm/xmc4/xmc4800-relax/src/xmc4_autoleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* The XMC4800 Relax Lite v1 board has two LEDs: + * + * LED1 P5.9 High output illuminates + * LED2 P5.8 High output illuminates + * + * These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/sam_autoleds.c. The LEDs are used to encode + * OS-related events as follows: + * + * SYMBOL Meaning LED state + * LED1 LED2 + * ------------------ ------------------------ ------ ------ + * LED_STARTED NuttX has been started OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF + * LED_IRQSENABLED Interrupts enabled OFF OFF + * LED_STACKCREATED Idle stack created ON OFF + * LED_INIRQ In an interrupt No change + * LED_SIGNAL In a signal handler No change + * LED_ASSERTION An assertion failed No change + * LED_PANIC The system has crashed N/C Blinking + * LED_IDLE MCU is is sleep mode Not used + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "xmc4_gpio.h" +#include "xmc4800-relax.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void board_led1_on(int led) +{ + bool ledon = false; + + switch (led) + { + case 0: /* LED1=OFF */ + break; + + case 1: /* LED1=ON */ + ledon = true; + break; + + case 2: /* LED1=N/C */ + case 3: /* LED1=N/C */ + default: + return; + } + + xmc4_gpio_write(GPIO_LED1, ledon); +} + +static void board_led2_on(int led) +{ + bool ledon = false; + + switch (led) + { + case 0: /* LED2=OFF */ + case 1: /* LED2=OFF */ + break; + + case 3: /* LED2=ON */ + ledon = true; + break; + + case 2: /* LED2=N/C */ + default: + return; + } + + xmc4_gpio_write(GPIO_LED2, ledon); +} + +static void board_led1_off(int led) +{ + switch (led) + { + case 0: /* LED1=OFF */ + case 1: /* LED1=OFF */ + break; + + case 2: /* LED1=N/C */ + case 3: /* LED1=N/C */ + default: + return; + } + + xmc4_gpio_write(GPIO_LED1, false); +} + +static void board_led2_off(int led) +{ + switch (led) + { + case 0: /* LED2=OFF */ + case 1: /* LED2=OFF */ + case 3: /* LED2=OFF */ + break; + + case 2: /* LED2=N/C */ + default: + return; + } + + xmc4_gpio_write(GPIO_LED2, false); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + xmc4_gpio_config(GPIO_LED1); + xmc4_gpio_config(GPIO_LED2); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + board_led1_on(led); + board_led2_on(led); +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + board_led1_off(led); + board_led2_off(led); +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/arm/xmc4/xmc4800-relax/src/xmc4_boot.c b/boards/arm/xmc4/xmc4800-relax/src/xmc4_boot.c new file mode 100644 index 0000000000000..c46af6332da66 --- /dev/null +++ b/boards/arm/xmc4/xmc4800-relax/src/xmc4_boot.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/arm/xmc4/xmc4800-relax/src/xmc4_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "xmc4800-relax.h" + +#include "xmc4_ecat.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_board_initialize + * + * Description: + * All XMC4 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void xmc4_board_initialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_XMC4_USCI_SPI + xmc4_spidev_initialize(); +#endif + +#ifdef CONFIG_XMC4_ECAT + xmc4_ecat_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board initialization */ + + xmc4_bringup(); +} +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm/xmc4/xmc4800-relax/src/xmc4_bringup.c b/boards/arm/xmc4/xmc4800-relax/src/xmc4_bringup.c new file mode 100644 index 0000000000000..97ea35c150102 --- /dev/null +++ b/boards/arm/xmc4/xmc4800-relax/src/xmc4_bringup.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/arm/xmc4/xmc4800-relax/src/xmc4_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#ifdef CONFIG_XMC4_USCI_SPI +# include +#endif +#ifdef CONFIG_USERLED +# include +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int xmc4_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_XMC4_USCI_SPI + struct spi_dev_s *spi; + spi = xmc4_spibus_initialize(4); + + if (!spi) + { + return -ENODEV; + } + + ret = spi_register(spi, 0); + if (ret < 0) + { + snerr("ERROR: Failed to register driver: %d\n", ret); + } +#endif + +#ifdef CONFIG_USERLED + /* Register the LED driver */ + + ret = userled_lower_initialize("/dev/userleds"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret); + } +#endif + + return ret; +} diff --git a/boards/arm/xmc4/xmc4800-relax/src/xmc4_buttons.c b/boards/arm/xmc4/xmc4800-relax/src/xmc4_buttons.c new file mode 100644 index 0000000000000..dc997bbd1a6d6 --- /dev/null +++ b/boards/arm/xmc4/xmc4800-relax/src/xmc4_buttons.c @@ -0,0 +1,64 @@ +/**************************************************************************** + * boards/arm/xmc4/xmc4800-relax/src/xmc4_buttons.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include "xmc4800-relax.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ +#warning Missing logic + return 0; +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint32_t board_buttons(void) +{ +#warning Missing logic + return 0; +} + +/**************************************************************************** + * Name: board_button_irq + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ +#warning Missing logic + return -ENOSYS; +} +#endif /* CONFIG_ARCH_IRQBUTTONS */ diff --git a/boards/arm/xmc4/xmc4800-relax/src/xmc4_spi.c b/boards/arm/xmc4/xmc4800-relax/src/xmc4_spi.c new file mode 100644 index 0000000000000..9923f119dccf8 --- /dev/null +++ b/boards/arm/xmc4/xmc4800-relax/src/xmc4_spi.c @@ -0,0 +1,280 @@ +/**************************************************************************** + * boards/arm/xmc4/xmc4800-relax/src/xmc4_spi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "xmc4800-relax.h" +#include "xmc4_gpio.h" +#include "xmc4_spi.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins. + * + ****************************************************************************/ + +void weak_function xmc4_spidev_initialize(void) +{ + /* Configure SPI0 chip selects */ + +#ifdef CONFIG_XMC4_SPI0 +#endif + + /* Configure SPI1 chip selects */ + +#ifdef CONFIG_XMC4_SPI1 +#endif + + /* Configure SPI2 chip selects */ + +#if defined(CONFIG_XMC4_SPI2) +#endif + + /* Configure SPI3 chip selects */ + +#ifdef CONFIG_XMC4_SPI3 +#endif + + /* Configure SPI4 chip selects */ + +#ifdef CONFIG_XMC4_SPI4 + xmc4_gpio_config(GPIO_CS); +#endif +} + +/**************************************************************************** + * Name: xmc4_spi[n]select, xmc4_spi[n]status, and xmc4_spi[n]cmddata + * + * Description: + * These external functions must be provided by board-specific logic. They + * are implementations of the select, status, and cmddata methods of the + * SPI interface defined by struct spi_ops_s (see include/nuttx/spi/spi.h). + * All other methods including xmc4_spibus_initialize()) are provided by + * common xmc4 logic. To use this common SPI logic on your board: + * + * 1. Provide logic in xmc4_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide xmc4_spi[n]select() and xmc4_spi[n]status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board + * is configured. + * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide + * xmc4_spi[n]cmddata() functions in your board-specific logic. These + * functions will perform cmd/data selection operations using GPIOs in + * the way your board is configured. + * 3. Add a call to xmc4_spibus_initialize() in your low level application + * initialization logic + * 4. The handle returned by xmc4_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +/**************************************************************************** + * Name: xmc4_spi[n]select + * + * Description: + * PIO chip select pins may be programmed by the board specific logic in + * one of two different ways. First, the pins may be programmed as SPI + * peripherals. In that case, the pins are completely controlled by the + * SPI driver. This method still needs to be provided, but it may be only + * a stub. + * + * An alternative way to program the PIO chip select pins is as a normal + * GPIO output. In that case, the automatic control of the CS pins is + * bypassed and this function must provide control of the chip select. + * NOTE: In this case, the GPIO output pin does *not* have to be the + * same as the NPCS pin normal associated with the chip select number. + * + * Input Parameters: + * devid - Identifies the (logical) device + * selected - TRUE:Select the device, FALSE:De-select the device + * + * Returned Values: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_XMC4_SPI0 +void xmc4_spi0select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} +#endif + +#ifdef CONFIG_XMC4_SPI1 +void xmc4_spi1select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} +#endif + +#ifdef CONFIG_XMC4_SPI2 +void xmc4_spi2select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} +#endif + +#ifdef CONFIG_XMC4_SPI3 +void xmc4_spi3select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); +} +#endif + +#ifdef CONFIG_XMC4_SPI4 +void xmc4_spi4select(struct spi_dev_s *dev, uint32_t devid, + bool selected) +{ + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); + + xmc4_gpio_write(GPIO_CS, !selected); +} +#endif + +/**************************************************************************** + * Name: xmc4_spi[n]status + * + * Description: + * Return status information associated with the SPI device. + * + * Input Parameters: + * devid - Identifies the (logical) device + * + * Returned Values: + * Bit-encoded SPI status (see include/nuttx/spi/spi.h). + * + ****************************************************************************/ + +#ifdef CONFIG_XMC4_SPI0 +uint8_t xmc4_spi0status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_XMC4_SPI1 +uint8_t xmc4_spi1status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_XMC4_SPI2 +uint8_t xmc4_spi2status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_XMC4_SPI3 +uint8_t xmc4_spi3status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +#ifdef CONFIG_XMC4_SPI4 +uint8_t xmc4_spi4status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} +#endif + +/**************************************************************************** + * Name: xmc4_spi[n]cmddata + * + * Description: + * Some SPI interfaces, particularly with LCDs, and an auxiliary 9th data + * input that determines where the other 8 data bits represent command or + * data. These interfaces control that CMD/DATA GPIO output + * + * Input Parameters: + * devid - Identifies the (logical) device + * cmd - Determines where command or data should be selected. + * + * Returned Values: + * Bit-encoded SPI status (see include/nuttx/spi/spi.h). + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_XMC4_SPI0 +int xmc4_spi0cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return 0; +} +#endif + +#ifdef CONFIG_XMC4_SPI1 +int xmc4_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return 0; +} +#endif + +#ifdef CONFIG_XMC4_SPI2 +int xmc4_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return 0; +} +#endif + +#ifdef CONFIG_XMC4_SPI3 +int xmc4_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return 0; +} +#endif + +#ifdef CONFIG_XMC4_SPI4 +int xmc4_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return 0; +} +#endif +#endif /* CONFIG_SPI_CMDDATA */ diff --git a/boards/arm/xmc4/xmc4800-relax/src/xmc4_userleds.c b/boards/arm/xmc4/xmc4800-relax/src/xmc4_userleds.c new file mode 100644 index 0000000000000..a4cdac0d49468 --- /dev/null +++ b/boards/arm/xmc4/xmc4800-relax/src/xmc4_userleds.c @@ -0,0 +1,87 @@ +/**************************************************************************** + * boards/arm/xmc4/xmc4800-relax/src/xmc4_userleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include "xmc4_gpio.h" +#include "xmc4800-relax.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +uint32_t board_userled_initialize(void) +{ + /* Configure LED1-2 GPIOs for output */ + + xmc4_gpio_config(GPIO_LED1); + xmc4_gpio_config(GPIO_LED2); + return BOARD_NLEDS; +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + gpioconfig_t ledcfg; + + if (led == BOARD_LED0) + { + ledcfg = GPIO_LED1; + } + else if (led == BOARD_LED1) + { + ledcfg = GPIO_LED2; + } + else + { + return; + } + + xmc4_gpio_write(ledcfg, ledon); +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint32_t ledset) +{ + bool ledon; + + ledon = ((ledset & BOARD_LED0_BIT) != 0); + xmc4_gpio_write(GPIO_LED1, ledon); + + ledon = ((ledset & BOARD_LED1_BIT) != 0); + xmc4_gpio_write(GPIO_LED2, ledon); +} diff --git a/boards/arm64/a64/pinephone/configs/lcd/defconfig b/boards/arm64/a64/pinephone/configs/lcd/defconfig index 1d8fb09a607aa..7688f3fd93e74 100644 --- a/boards/arm64/a64/pinephone/configs/lcd/defconfig +++ b/boards/arm64/a64/pinephone/configs/lcd/defconfig @@ -39,7 +39,6 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PINEPHONE_LCD=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 diff --git a/boards/arm64/a64/pinephone/configs/lvgl/defconfig b/boards/arm64/a64/pinephone/configs/lvgl/defconfig index dc074fe0c73bc..05c976f14d248 100644 --- a/boards/arm64/a64/pinephone/configs/lvgl/defconfig +++ b/boards/arm64/a64/pinephone/configs/lvgl/defconfig @@ -47,17 +47,16 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LV_COLOR_DEPTH_32=y CONFIG_LV_DPI_DEF=267 CONFIG_LV_FONT_DEFAULT_MONTSERRAT_20=y -CONFIG_LV_MEM_SIZE_KILOBYTES=64 -CONFIG_LV_PORT_USE_FBDEV=y -CONFIG_LV_PORT_USE_TOUCHPAD=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y CONFIG_LV_USE_DEMO_WIDGETS=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PINEPHONE_LCD=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 diff --git a/boards/arm64/a64/pinephone/configs/nsh/defconfig b/boards/arm64/a64/pinephone/configs/nsh/defconfig index f2666816d11e4..78c4a380e0d2f 100644 --- a/boards/arm64/a64/pinephone/configs/nsh/defconfig +++ b/boards/arm64/a64/pinephone/configs/nsh/defconfig @@ -39,7 +39,6 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 CONFIG_RAMLOG=y diff --git a/boards/arm64/a64/pinephone/configs/sensor/defconfig b/boards/arm64/a64/pinephone/configs/sensor/defconfig index c6fa2de8bc152..27d214893dd9c 100644 --- a/boards/arm64/a64/pinephone/configs/sensor/defconfig +++ b/boards/arm64/a64/pinephone/configs/sensor/defconfig @@ -42,7 +42,6 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 CONFIG_RAMLOG=y diff --git a/boards/arm64/a64/pinephone/scripts/dramboot.ld b/boards/arm64/a64/pinephone/scripts/dramboot.ld index 15c82c9d32304..f5f515d4b819a 100644 --- a/boards/arm64/a64/pinephone/scripts/dramboot.ld +++ b/boards/arm64/a64/pinephone/scripts/dramboot.ld @@ -33,6 +33,7 @@ SECTIONS _start = .; .text : { _stext = .; /* Text section */ + *(.start .start.*) /* Place __start here */ *(.text) *(.text.cold) *(.text.unlikely) diff --git a/boards/arm64/fvp-v8r/fvp-armv8r/configs/citest/defconfig b/boards/arm64/fvp-v8r/fvp-armv8r/configs/citest/defconfig index 43d89f983e855..2decb87bcc5b7 100644 --- a/boards/arm64/fvp-v8r/fvp-armv8r/configs/citest/defconfig +++ b/boards/arm64/fvp-v8r/fvp-armv8r/configs/citest/defconfig @@ -20,7 +20,6 @@ CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SCHED=y CONFIG_DEBUG_SCHED_ERROR=y -CONFIG_DEBUG_SCHED_INFO=y CONFIG_DEBUG_SCHED_WARN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_TASK_STACKSIZE=8192 @@ -36,7 +35,6 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 CONFIG_RAMLOG=y diff --git a/boards/arm64/fvp-v8r/fvp-armv8r/configs/citest_smp/defconfig b/boards/arm64/fvp-v8r/fvp-armv8r/configs/citest_smp/defconfig index 9e1dfe3747193..e7a74f367bb09 100644 --- a/boards/arm64/fvp-v8r/fvp-armv8r/configs/citest_smp/defconfig +++ b/boards/arm64/fvp-v8r/fvp-armv8r/configs/citest_smp/defconfig @@ -20,7 +20,6 @@ CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SCHED=y CONFIG_DEBUG_SCHED_ERROR=y -CONFIG_DEBUG_SCHED_INFO=y CONFIG_DEBUG_SCHED_WARN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_TASK_STACKSIZE=8192 @@ -36,7 +35,6 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 CONFIG_RAMLOG=y diff --git a/boards/arm64/fvp-v8r/fvp-armv8r/configs/nsh/defconfig b/boards/arm64/fvp-v8r/fvp-armv8r/configs/nsh/defconfig index 3a7a507b1be1e..4d6ad5db682ff 100644 --- a/boards/arm64/fvp-v8r/fvp-armv8r/configs/nsh/defconfig +++ b/boards/arm64/fvp-v8r/fvp-armv8r/configs/nsh/defconfig @@ -21,7 +21,6 @@ CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SCHED=y CONFIG_DEBUG_SCHED_ERROR=y -CONFIG_DEBUG_SCHED_INFO=y CONFIG_DEBUG_SCHED_WARN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_TASK_STACKSIZE=8192 @@ -38,7 +37,6 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 CONFIG_RAMLOG=y diff --git a/boards/arm64/fvp-v8r/fvp-armv8r/configs/nsh_smp/defconfig b/boards/arm64/fvp-v8r/fvp-armv8r/configs/nsh_smp/defconfig index 07c0dacb29ea9..2aa238cb9025a 100644 --- a/boards/arm64/fvp-v8r/fvp-armv8r/configs/nsh_smp/defconfig +++ b/boards/arm64/fvp-v8r/fvp-armv8r/configs/nsh_smp/defconfig @@ -21,7 +21,6 @@ CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SCHED=y CONFIG_DEBUG_SCHED_ERROR=y -CONFIG_DEBUG_SCHED_INFO=y CONFIG_DEBUG_SCHED_WARN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_TASK_STACKSIZE=8192 @@ -38,7 +37,6 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 CONFIG_RAMLOG=y diff --git a/boards/arm64/fvp-v8r/fvp-armv8r/scripts/dramboot.ld b/boards/arm64/fvp-v8r/fvp-armv8r/scripts/dramboot.ld index ec2d6956c52ad..50d5ba78d41cd 100644 --- a/boards/arm64/fvp-v8r/fvp-armv8r/scripts/dramboot.ld +++ b/boards/arm64/fvp-v8r/fvp-armv8r/scripts/dramboot.ld @@ -33,6 +33,7 @@ SECTIONS _start = .; .text : { _stext = .; /* Text section */ + *(.start .start.*) /* Place __start here */ *(.text) *(.text.cold) *(.text.unlikely) diff --git a/boards/arm64/imx8/imx8qm-mek/configs/nsh/defconfig b/boards/arm64/imx8/imx8qm-mek/configs/nsh/defconfig index fdccfbd8fdf5b..f7408fe9f0016 100644 --- a/boards/arm64/imx8/imx8qm-mek/configs/nsh/defconfig +++ b/boards/arm64/imx8/imx8qm-mek/configs/nsh/defconfig @@ -20,7 +20,6 @@ CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SCHED=y CONFIG_DEBUG_SCHED_ERROR=y -CONFIG_DEBUG_SCHED_INFO=y CONFIG_DEBUG_SCHED_WARN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_TASK_STACKSIZE=8192 @@ -39,7 +38,6 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAMLOG=y CONFIG_RAM_SIZE=134217728 diff --git a/boards/arm64/imx8/imx8qm-mek/scripts/dramboot.ld b/boards/arm64/imx8/imx8qm-mek/scripts/dramboot.ld index 160a5f8f86db7..24e385d9948b5 100644 --- a/boards/arm64/imx8/imx8qm-mek/scripts/dramboot.ld +++ b/boards/arm64/imx8/imx8qm-mek/scripts/dramboot.ld @@ -33,6 +33,7 @@ SECTIONS _start = .; .text : { _stext = .; /* Text section */ + *(.start .start.*) /* Place __start here */ *(.text) *(.text.cold) *(.text.unlikely) diff --git a/boards/arm64/imx8/imx8qm-mek/src/Makefile b/boards/arm64/imx8/imx8qm-mek/src/Makefile index 7c5990d74f5c6..3c1c8afa97a96 100644 --- a/boards/arm64/imx8/imx8qm-mek/src/Makefile +++ b/boards/arm64/imx8/imx8qm-mek/src/Makefile @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm/imx6/sabre-6quad/src/Makefile +# boards/arm64/imx8/imx8qm-mek/src/Makefile # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/arm64/imx9/imx93-evk/Kconfig b/boards/arm64/imx9/imx93-evk/Kconfig new file mode 100644 index 0000000000000..0e63f5a5cbc73 --- /dev/null +++ b/boards/arm64/imx9/imx93-evk/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_IMX93_EVK +endif diff --git a/boards/arm64/imx9/imx93-evk/configs/bootloader/defconfig b/boards/arm64/imx9/imx93-evk/configs/bootloader/defconfig new file mode 100644 index 0000000000000..95ff53b67c8c2 --- /dev/null +++ b/boards/arm64/imx9/imx93-evk/configs/bootloader/defconfig @@ -0,0 +1,64 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="arm64" +CONFIG_ARCH_ARM64=y +CONFIG_ARCH_ARM64_EXCEPTION_LEVEL=3 +CONFIG_ARCH_BOARD="imx93-evk" +CONFIG_ARCH_BOARD_IMX93_EVK=y +CONFIG_ARCH_CHIP="imx9" +CONFIG_ARCH_CHIP_IMX93=y +CONFIG_ARCH_CHIP_IMX9=y +CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARM64_DCACHE_DISABLE=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_TASK_STACKSIZE=8192 +CONFIG_DEV_ZERO=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=8192 +CONFIG_IMX9_BOOTLOADER=y +CONFIG_IMX9_GPIO_IRQ=y +CONFIG_IMX9_LPUART1=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_MM_FILL_ALLOCATIONS=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAMLOG=y +CONFIG_RAM_SIZE=548864 +CONFIG_RAM_START=0x2049a000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=50 +CONFIG_SPINLOCK=y +CONFIG_STACK_COLORATION=y +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2022 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_SYSTEM=y +CONFIG_SYSTEM_TIME64=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y diff --git a/boards/arm64/imx9/imx93-evk/configs/nsh/defconfig b/boards/arm64/imx9/imx93-evk/configs/nsh/defconfig new file mode 100644 index 0000000000000..e2810cc58124b --- /dev/null +++ b/boards/arm64/imx9/imx93-evk/configs/nsh/defconfig @@ -0,0 +1,112 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_MMCSD_HAVE_WRITEPROTECT is not set +# CONFIG_MMCSD_IOCSUPPORT is not set +# CONFIG_MMCSD_MMCSUPPORT is not set +# CONFIG_MMCSD_SPI is not set +CONFIG_ARCH="arm64" +CONFIG_ARCH_ARM64=y +CONFIG_ARCH_BOARD="imx93-evk" +CONFIG_ARCH_BOARD_IMX93_EVK=y +CONFIG_ARCH_CHIP="imx9" +CONFIG_ARCH_CHIP_IMX93=y +CONFIG_ARCH_CHIP_IMX9=y +CONFIG_ARCH_EARLY_PRINT=y +CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_BUILTIN=y +CONFIG_CDCACM=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_TASK_STACKSIZE=8192 +CONFIG_DEV_ZERO=y +CONFIG_ETH0_PHY_MULTI=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_TCPBLASTER=y +CONFIG_EXAMPLES_UDPBLASTER=y +CONFIG_EXPERIMENTAL=y +CONFIG_FAT_DMAMEMORY=y +CONFIG_FS_FAT=y +CONFIG_FS_FATTIME=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_GRAN=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2C=y +CONFIG_I2C_RESET=y +CONFIG_IDLETHREAD_STACKSIZE=8192 +CONFIG_IMX9_DMA_ALLOC=y +CONFIG_IMX9_DMA_ALLOC_POOL_SIZE=81920 +CONFIG_IMX9_EDMA=y +CONFIG_IMX9_ENET1_RGMII=y +CONFIG_IMX9_ENET=y +CONFIG_IMX9_ENET_USE_OTP_MAC=y +CONFIG_IMX9_FLEXIO1_PWM=y +CONFIG_IMX9_GPIO_IRQ=y +CONFIG_IMX9_LPI2C1=y +CONFIG_IMX9_LPI2C1_DMA=y +CONFIG_IMX9_LPI2C_DMA=y +CONFIG_IMX9_LPI2C_DYNTIMEO=y +CONFIG_IMX9_LPI2C_DYNTIMEO_STARTSTOP=10 +CONFIG_IMX9_LPSPI6=y +CONFIG_IMX9_LPSPI6_DMA=y +CONFIG_IMX9_LPSPI_DMA=y +CONFIG_IMX9_LPUART1=y +CONFIG_IMX9_TPM3_PWM=y +CONFIG_IMX9_TPM3_PWM_CHMUX=0x00000003 +CONFIG_IMX9_USBDEV_USBC1=y +CONFIG_IMX9_USDHC2=y +CONFIG_IMX9_USDHC2_INVERT_CD=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LPUART1_SERIAL_CONSOLE=y +CONFIG_MMCSD=y +CONFIG_MMCSD_SDIO=y +CONFIG_NDEBUG=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM=y +CONFIG_PWM_NCHANNELS=4 +CONFIG_RAMLOG=y +CONFIG_RAM_SIZE=134217728 +CONFIG_RAM_START=0x80000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=50 +CONFIG_SDIO_BLOCKSETUP=y +CONFIG_SPI=y +CONFIG_SPINLOCK=y +CONFIG_STACK_COLORATION=y +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2022 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_CDCACM=y +CONFIG_SYSTEM_I2CTOOL=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_SYSTEM_SPITOOL=y +CONFIG_SYSTEM_SYSTEM=y +CONFIG_SYSTEM_TIME64=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y diff --git a/boards/arm64/imx9/imx93-evk/include/board.h b/boards/arm64/imx9/imx93-evk/include/board.h new file mode 100644 index 0000000000000..1d93aef9c7f2e --- /dev/null +++ b/boards/arm64/imx9/imx93-evk/include/board.h @@ -0,0 +1,261 @@ +/**************************************************************************** + * boards/arm64/imx9/imx93-evk/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM64_IMX9_IMX93_EVK_INCLUDE_BOARD_H +#define __BOARDS_ARM64_IMX9_IMX93_EVK_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Default PAD configurations */ + +#define IOMUX_LPI2C_DEFAULT (IOMUXC_PAD_OD_ENABLE | IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6) +#define IOMUX_LPSPI_DEFAULT (IOMUXC_PAD_PU_ON | IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6) +#define IOMUX_GPIO_DEFAULT (IOMUXC_PAD_FSEL_SLOW | IOMUXC_PAD_DSE_X6) + +/* UART pin muxings */ + +#define MUX_LPUART1_RX IOMUX_CFG(IOMUXC_PAD_UART1_RXD_LPUART1_RX, 0, IOMUXC_MUX_SION_ON) +#define MUX_LPUART1_TX IOMUX_CFG(IOMUXC_PAD_UART1_TXD_LPUART1_TX, IOMUXC_PAD_FSEL_SLOW | IOMUXC_PAD_DSE_X4, 0) + +/* FLEXIO to PWM pin muxings */ + +/* EVK signals + * GPIO_IO04 -> FLEXIO1_04 + * GPIO_IO05 -> FLEXIO1_05 + * GPIO_IO06 -> FLEXIO1_06 + * GPIO_IO07 -> FLEXIO1_07 + */ + +#define FLEXIO1_PWM0_MUX IOMUX_CFG(IOMUXC_PAD_GPIO_IO04_FLEXIO1_FLEXIO04, IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6, 0) +#define FLEXIO1_PWM1_MUX IOMUX_CFG(IOMUXC_PAD_GPIO_IO05_FLEXIO1_FLEXIO05, IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6, 0) +#define FLEXIO1_PWM2_MUX IOMUX_CFG(IOMUXC_PAD_GPIO_IO06_FLEXIO1_FLEXIO06, IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6, 0) +#define FLEXIO1_PWM3_MUX IOMUX_CFG(IOMUXC_PAD_GPIO_IO07_FLEXIO1_FLEXIO07, IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6, 0) + +/* LPI2Cs */ + +/* TPM3 ch3 to PWM pin GPIO_IO24 muxing */ + +#define TPM3_PWM3_MUX IOMUX_CFG(IOMUXC_PAD_GPIO_IO24_TPM3_CH3, IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_DSE_X6, 0) + +/* LPI2Cs */ + +#define MUX_LPI2C1_SCL IOMUX_CFG(IOMUXC_PAD_I2C1_SCL_LPI2C1_SCL, IOMUX_LPI2C_DEFAULT, IOMUXC_MUX_SION_ON) +#define MUX_LPI2C1_SDA IOMUX_CFG(IOMUXC_PAD_I2C1_SDA_LPI2C1_SDA, IOMUX_LPI2C_DEFAULT, IOMUXC_MUX_SION_ON) + +/* I2C reset functionality */ + +#define GPIO_LPI2C1_SCL_RESET (GPIO_PORT1 | GPIO_PIN0 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) +#define GPIO_LPI2C1_SDA_RESET (GPIO_PORT1 | GPIO_PIN1 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) + +/* LPSPIs */ + +#define MUX_LPSPI3_SCK IOMUX_CFG(IOMUXC_PAD_GPIO_IO11_LPSPI3_SCK, IOMUX_LPSPI_DEFAULT, IOMUXC_MUX_SION_ON) +#define MUX_LPSPI3_MOSI IOMUX_CFG(IOMUXC_PAD_GPIO_IO10_LPSPI3_SOUT, IOMUX_LPSPI_DEFAULT, IOMUXC_MUX_SION_ON) +#define MUX_LPSPI3_MISO IOMUX_CFG(IOMUXC_PAD_GPIO_IO09_LPSPI3_SIN, IOMUX_LPSPI_DEFAULT, IOMUXC_MUX_SION_ON) +#define MUX_LPSPI6_SCK IOMUX_CFG(IOMUXC_PAD_GPIO_IO03_LPSPI6_SCK, IOMUX_LPSPI_DEFAULT, IOMUXC_MUX_SION_ON) +#define MUX_LPSPI6_MOSI IOMUX_CFG(IOMUXC_PAD_GPIO_IO02_LPSPI6_SOUT, IOMUX_LPSPI_DEFAULT, IOMUXC_MUX_SION_ON) +#define MUX_LPSPI6_MISO IOMUX_CFG(IOMUXC_PAD_GPIO_IO01_LPSPI6_SIN, IOMUX_LPSPI_DEFAULT, IOMUXC_MUX_SION_ON) + +/* SPI CS */ + +#define MUX_LPSPI3_CS IOMUX_CFG(IOMUXC_PAD_GPIO_IO08_GPIO2_IO08, IOMUX_GPIO_DEFAULT, IOMUXC_MUX_SION_ON) +#define GPIO_LPSPI3_CS (GPIO_PORT2 | GPIO_PIN8 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) +#define MUX_LPSPI6_CS IOMUX_CFG(IOMUXC_PAD_GPIO_IO00_GPIO2_IO00, IOMUX_GPIO_DEFAULT, IOMUXC_MUX_SION_ON) +#define GPIO_LPSPI6_CS (GPIO_PORT2 | GPIO_PIN0 | GPIO_OUTPUT | GPIO_OUTPUT_ONE) + +/* USDHC */ + +/* Note: Need to set the SION for cmd and data pads (ERR052021) */ + +#define PIN_USDHC2_D0_MUX IOMUX_CFG(IOMUXC_PAD_SD2_DATA0_USDHC2_DATA0, IOMUXC_PAD_DSE_X1 | IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_PU_ON | IOMUXC_PAD_HYS_ST_ON, IOMUXC_MUX_SION_ON) +#define PIN_USDHC2_D1_MUX IOMUX_CFG(IOMUXC_PAD_SD2_DATA1_USDHC2_DATA1, IOMUXC_PAD_DSE_X1 | IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_PU_ON | IOMUXC_PAD_HYS_ST_ON, IOMUXC_MUX_SION_ON) +#define PIN_USDHC2_D2_MUX IOMUX_CFG(IOMUXC_PAD_SD2_DATA2_USDHC2_DATA2, IOMUXC_PAD_DSE_X1 | IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_PU_ON | IOMUXC_PAD_HYS_ST_ON, IOMUXC_MUX_SION_ON) +#define PIN_USDHC2_D3_MUX IOMUX_CFG(IOMUXC_PAD_SD2_DATA3_USDHC2_DATA3, IOMUXC_PAD_DSE_X1 | IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_PU_ON | IOMUXC_PAD_HYS_ST_ON, IOMUXC_MUX_SION_ON) +#define PIN_USDHC2_DCLK_MUX IOMUX_CFG(IOMUXC_PAD_SD2_DATA1_USDHC2_DATA1, IOMUXC_PAD_DSE_X6 | IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_PD_ON | IOMUXC_PAD_HYS_ST_ON, 0) +#define PIN_USDHC2_CMD_MUX IOMUX_CFG(IOMUXC_PAD_SD2_CMD_USDHC2_CMD, IOMUXC_PAD_DSE_X1 | IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_PU_ON | IOMUXC_PAD_HYS_ST_ON, IOMUXC_MUX_SION_ON) +#define PIN_USDHC2_CD_MUX IOMUX_CFG(IOMUXC_PAD_SD2_DATA3_USDHC2_DATA3, IOMUXC_PAD_DSE_X4 | IOMUXC_PAD_FSEL_FAST, 0) +#define PIN_USDHC2_VSELECT_MUX IOMUX_CFG(IOMUXC_PAD_SD2_VSELECT_USDHC2_VSELECT, IOMUXC_PAD_DSE_X5 | IOMUXC_PAD_FSEL_SFAST | IOMUXC_PAD_PD_ON, 0) + +/* 390 KHz for initial inquiry stuff */ + +#define BOARD_USDHC_IDMODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV256 +#define BOARD_USDHC_IDMODE_DIVISOR USDHC_SYSCTL_DVS_DIV(2) + +/* 25MHz for 1-bit wide bus */ + +#define BOARD_USDHC_MMCMODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV8 +#define BOARD_USDHC_MMCMODE_DIVISOR USDHC_SYSCTL_DVS_DIV(1) + +#define BOARD_USDHC_SD1MODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV8 +#define BOARD_USDHC_SD1MODE_DIVISOR USDHC_SYSCTL_DVS_DIV(1) + +/* 50MHz for 4-bit wide bus */ + +#define BOARD_USDHC_SD4MODE_PRESCALER USDHC_SYSCTL_SDCLKFS_DIV4 +#define BOARD_USDHC_SD4MODE_DIVISOR USDHC_SYSCTL_DVS_DIV(1) + +/* Set the PLL clocks as follows: + * + * - OSC24M : 24 MHz + * - ARMPLL_OUT : 1692 MHz + * - DRAMPLL : 933 MHz + * - SYSPLL1 : 4000 MHz + * - SYSPLL_PFD0 : 1000 MHz + * - SYSPLL_PFD1 : 800 MHz + * - SYSPLL_PFD2 : 625 MHz + * - AUDIOPLL_OUT : OFF + * - VIDEOPLL_OUT : OFF + * + * After reset all clock sources (OSCPLL) and root clocks (CLOCK_ROOT) are + * running, but gated (LPCG). + * + * By default, all peripheral root clocks are set to the 24 MHz oscillator. + */ + +#define ARMPLL_CFG PLL_CFG(IMX9_ARMPLL_BASE, false, PLL_PARMS(1, 2, 141, 0, 0)) +#define DRAMPLL_CFG PLL_CFG(IMX9_DRAMPLL_BASE, true, PLL_PARMS(1, 2, 155, 1, 2)) + +#define PLL_CFGS \ + { \ + PLL_CFG(IMX9_SYSPLL_BASE, true, PLL_PARMS(1, 4, 166, 2, 3)), \ + } + +#define PFD_CFGS \ + { \ + PFD_CFG(IMX9_SYSPLL_BASE, 0, PFD_PARMS(4, 0, true)), \ + PFD_CFG(IMX9_SYSPLL_BASE, 1, PFD_PARMS(5, 0, true)), \ + PFD_CFG(IMX9_SYSPLL_BASE, 2, PFD_PARMS(6, 2, true)), \ + } + +/* Ethernet configuration */ + +#define BOARD_ENET1_PHY_LIST \ +{ \ + { \ + .name = GMII_RTL8211F_NAME, \ + .id1 = GMII_PHYID1_RTL8211F, \ + .id2 = GMII_PHYID2_RTL8211F, \ + .status = GMII_RTL8211F_PHYSR_A43, \ + .address_lo = 2, \ + .address_high = 0xffff, \ + .mbps10 = GMII_RTL8211F_PHYSR_10MBPS, \ + .mbps100 = GMII_RTL8211F_PHYSR_100MBPS, \ + .duplex = GMII_RTL8211F_PHYSR_DUPLEX, \ + .clause = 22, \ + .mbps1000 = GMII_RTL8211F_PHYSR_1000MBPS, \ + .speed_mask = GMII_RTL8211F_PHYSR_SPEED_MASK, \ + }, \ +} + +#endif /* CONFIG_IMX9_ENET1 */ + +#ifdef CONFIG_IMX9_ENET1 + +#define MUX_ENET1_MDIO IOMUX_CFG(IOMUXC_PAD_ENET2_MDIO_ENET1_MDIO, IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6, IOMUXC_MUX_SION_ON) +#define MUX_ENET1_MDC IOMUX_CFG(IOMUXC_PAD_ENET2_MDC_ENET1_MDC, IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6, 0) + +#define MUX_ENET1_RX_DATA00 IOMUX_CFG(IOMUXC_PAD_ENET2_RD0_ENET1_RGMII_RD0, 0, 0) +#define MUX_ENET1_RX_DATA01 IOMUX_CFG(IOMUXC_PAD_ENET2_RD1_ENET1_RGMII_RD1, 0, 0) + +#define MUX_ENET1_TX_DATA00 IOMUX_CFG(IOMUXC_PAD_ENET2_TD0_ENET1_RGMII_TD0, IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6, 0) +#define MUX_ENET1_TX_DATA01 IOMUX_CFG(IOMUXC_PAD_ENET2_TD1_ENET1_RGMII_TD1, IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6, 0) + +#if defined(CONFIG_IMX9_ENET1_RGMII) + +# define MUX_ENET1_RX_DATA02 IOMUX_CFG(IOMUXC_PAD_ENET2_RD2_ENET1_RGMII_RD2, 0, 0) +# define MUX_ENET1_RX_DATA03 IOMUX_CFG(IOMUXC_PAD_ENET2_RD3_ENET1_RGMII_RD3, 0, 0) +# define MUX_ENET1_TX_DATA02 IOMUX_CFG(IOMUXC_PAD_ENET2_TD2_ENET1_RGMII_TD2, IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6, 0) +# define MUX_ENET1_TX_DATA03 IOMUX_CFG(IOMUXC_PAD_ENET2_TD3_ENET1_RGMII_TD3, IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6, 0) +# define MUX_ENET1_RXC IOMUX_CFG(IOMUXC_PAD_ENET2_RXC_ENET1_RGMII_RXC, 0, 0) +# define MUX_ENET1_TX_CTL IOMUX_CFG(IOMUXC_PAD_ENET2_TX_CTL_ENET1_RGMII_TX_CTL, IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6, 0) +# define MUX_ENET1_RX_CTL IOMUX_CFG(IOMUXC_PAD_ENET2_RX_CTL_ENET1_RGMII_RX_CTL, 0, 0) + +#elif defined(CONFIG_IMX9_ENET1_RMII) + +/* Same pin as TX_CTL for RGMII */ + +# define MUX_ENET1_TX_EN IOMUX_CFG(IOMUXC_PAD_ENET2_TX_CTL_ENET1_RGMII_TX_CTL, IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6, 0) + +/* Same pin as TX_DATA02 for RGMII */ + +# define MUX_ENET1_REF_CLK IOMUX_CFG(IOMUXC_PAD_ENET2_TD2_ENET1_RGMII_TD2, IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6, 0) + +/* Same pin as RX_CTL for RGMII */ + +# define MUX_ENET1_CRS_DV IOMUX_CFG(IOMUXC_PAD_ENET2_RX_CTL_ENET1_RGMII_RX_CTL, 0, 0) + +#else +#error ENET1 supports only RMII and RGMII +#endif + +#define BOARD_ENET1_PHY_LIST \ +{ \ + { \ + GMII_RTL8211F_NAME, \ + GMII_PHYID1_RTL8211F, \ + GMII_PHYID2_RTL8211F, \ + GMII_RTL8211F_PHYSR_A43, \ + 2, \ + 0xffff, \ + GMII_RTL8211F_PHYSR_10MBPS, \ + GMII_RTL8211F_PHYSR_100MBPS, \ + GMII_RTL8211F_PHYSR_DUPLEX, \ + 22, \ + GMII_RTL8211F_PHYSR_1000MBPS, \ + GMII_RTL8211F_PHYSR_SPEED_MASK, \ + }, \ +} + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM64_IMX9_IMX93_EVK_INCLUDE_BOARD_H */ diff --git a/boards/arm64/imx9/imx93-evk/include/board_memorymap.h b/boards/arm64/imx9/imx93-evk/include/board_memorymap.h new file mode 100644 index 0000000000000..07649afbc5df5 --- /dev/null +++ b/boards/arm64/imx9/imx93-evk/include/board_memorymap.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * boards/arm64/imx9/imx93-evk/include/board_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM64_IMX9_IMX93_EVK_INCLUDE_BOARD_MEMORYMAP_H +#define __BOARDS_ARM64_IMX9_IMX93_EVK_INCLUDE_BOARD_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM64_IMX9_IMX93_EVK_INCLUDE_BOARD_MEMORYMAP_H */ diff --git a/boards/arm64/imx9/imx93-evk/scripts/Make.defs b/boards/arm64/imx9/imx93-evk/scripts/Make.defs new file mode 100644 index 0000000000000..670686a3eb831 --- /dev/null +++ b/boards/arm64/imx9/imx93-evk/scripts/Make.defs @@ -0,0 +1,53 @@ +############################################################################ +# boards/arm64/imx9/imx93-evk/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/tools/imx9/Config.mk +include $(TOPDIR)/arch/arm64/src/Toolchain.defs + +ifeq ($(CONFIG_IMX9_BOOTLOADER),y) + LDSCRIPT = ocramboot.ld +else + LDSCRIPT = dramboot.ld +endif + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +# NXFLAT module definitions + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +# ELF module definitions + +CELFFLAGS = $(CFLAGS) -mlong-calls # --target1-abs +CXXELFFLAGS = $(CXXFLAGS) -mlong-calls # --target1-abs + +LDELFFLAGS = -r -e main +LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/binfmt/libelf/gnu-elf.ld) diff --git a/boards/arm64/imx9/imx93-evk/scripts/dramboot.ld b/boards/arm64/imx9/imx93-evk/scripts/dramboot.ld new file mode 100644 index 0000000000000..f437d8d13745a --- /dev/null +++ b/boards/arm64/imx9/imx93-evk/scripts/dramboot.ld @@ -0,0 +1,157 @@ +/**************************************************************************** + * boards/arm64/imx9/imx93-evk/scripts/dramboot.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +OUTPUT_ARCH(aarch64) + +ENTRY(__start) +EXTERN(__start) + +/* Memory is organized as follows: + * - Uboot reserved area is 0x00000000 - 0x00a00000 + * - NuttX is loaded to 0x80000000, u-boot expects us here + * - NuttX ROM and RAM are one continuous region, starting from 0x80000000 + with a size of 128MB + * - Heap memory is allocated from dram end to idlestack top + */ + +MEMORY +{ + dram (rwx) : ORIGIN = 0x80000000, LENGTH = 128M +} + +PHDRS +{ + /* R = 100, W = 010, X = 001 */ + + text PT_LOAD FLAGS(5); /* RX */ + rodata PT_LOAD FLAGS(4); /* R */ + data PT_LOAD FLAGS(6); /* RW */ +} + +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); /* Text section */ + *(.start .start.*) /* Place __start here */ + *(.text .text.*) + *(.text.cold) + *(.text.unlikely) + *(.fixup) + *(.gnu.warning) + } > dram :text + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > dram :text + + /* Vector table must be page aligned */ + + .vector : ALIGN(4096) + { + _vector_start = ABSOLUTE(.); + KEEP(*(.exc_vector_table)) + KEEP(*(".exc_vector_table.*")) + KEEP(*(.vectors)) + _vector_end = ABSOLUTE(.); + } > dram :text + + /* End of text data must be aligned to page boundary */ + + . = ALIGN(4096); + _etext = .; + _sztext = _etext - _stext; + + /* Start of RO data must be page aligned (mapped as read only) */ + + .rodata : ALIGN(4096) + { + _srodata = ABSOLUTE(.); /* Read-only data */ + *(.rodata .rodata.*) + *(.data.rel.ro) + *(.data.rel.ro.*) + } > dram :rodata + + /* End of RO data must be page aligned */ + + . = ALIGN(4096); + + _erodata = .; /* End of read-only data */ + _szrodata = _erodata - _srodata; + _eronly = .; /* End of read-only data */ + + .data : ALIGN(4096) + { + _sdata = ABSOLUTE(.); + *(.data.page_aligned) + *(.data .data.*) + . = ALIGN(8); + *(.data.rel) + *(.data.rel.*) + CONSTRUCTORS + . = ALIGN(8); + _edata = ABSOLUTE(.); + } > dram :data + + .bss : + { + . = ALIGN(8); + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > dram :data + + _szbss = _ebss - _sbss; + + .initstack : + { + _s_initstack = ABSOLUTE(.); + *(.initstack) + } > dram :data + + /* End of data must be page aligned */ + . = ALIGN(4096); + + g_idle_topstack = .; + _e_initstack = .; + _szdata = _e_initstack - _sdata; + + /* Sections to be discarded */ + /DISCARD/ : { + *(.exit.text) + *(.exit.data) + *(.exitcall.exit) + *(.eh_frame) + } + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } +} diff --git a/boards/arm64/imx9/imx93-evk/scripts/imx93_ca55.JLinkScript b/boards/arm64/imx9/imx93-evk/scripts/imx93_ca55.JLinkScript new file mode 100644 index 0000000000000..483fc7005f202 --- /dev/null +++ b/boards/arm64/imx9/imx93-evk/scripts/imx93_ca55.JLinkScript @@ -0,0 +1,58 @@ +/* Adds custom i.MX93 logic to replace default procedures from JLink */ + +int ResetTarget(void) { + + JLINK_SYS_Report("-- Resetting target device..."); + + JLINK_TIF_ActivateTargetReset(); + JLINK_Delay_us(50000); // _Delay_us: Keep reset active for some time so possible glitch filters on target do not filter out reset pulse + JLINK_TIF_ReleaseTargetReset(); + + // + // This device requires a special reset as default reset does not work for this device. + // + JLINK_TARGET_Halt(); // Make sure that the CPU is halted when reset is called + + return 0; +} + +void ConfigTargetSettings(void) { + // JLINK_SYS_Report("J-Link script: Manually configuring JTAG chain"); + + // AP[0]: AHB-AP (IDR: 0x74770001) + // AP[1]: APB-AP (IDR: 0x44770002) + + JLINK_ExecCommand("CORESIGHT_AddAP Index=0 Type=AHB-AP"); // Connects to System Bus + JLINK_ExecCommand("CORESIGHT_AddAP Index=1 Type=APB-AP"); // Connects to CoreSight/A-core Platform (see APBIC) + JLINK_ExecCommand("CORESIGHT_AddAP Index=3 Type=DAP-AP"); // Connects to a Cortex-M33 + JLINK_ExecCommand("CORESIGHT_AddAP Index=4 Type=DAP-AP"); // Connects to a EdgeLock (Risc-V) + JLINK_ExecCommand("CORESIGHT_AddAP Index=6 Type=MDM-AP"); // Connects to a MDM + + // A55_0 + JLINK_ExecCommand("CORESIGHT_SetCoreBaseAddr = 0x40810000"); // Location in AP address space where debug registers of core are located + JLINK_ExecCommand("CORESIGHT_SetCSCTICoreBaseAddr = 0x40820000"); // Location in AP address space where CTI that connects to the core is located + + // A55_1 + //JLINK_ExecCommand("CORESIGHT_SetCoreBaseAddr = 0x40910000"); // Location in AP address space where debug registers of core are located + //JLINK_ExecCommand("CORESIGHT_SetCSCTICoreBaseAddr = 0x40920000"); // Location in AP address space where CTI that connects to the core is located + + // There is also a debug core at SetCoreBaseAddr = 0x40840000, but don't know what it is + + JTAG_AllowTAPReset = 1; // J-Link is allowed to use a TAP reset for JTAG-chain auto-detection + + JLINK_JTAG_IRPre = 0; // Sum of IRLen of all JTAG TAPs preceding the one we want to communicate with + JLINK_JTAG_DRPre = 0; // Number of JTAG TAPs preceding the one we want to communicate with + JLINK_JTAG_IRPost = 0; // Sum of IRLen of all JTAG TAPs following the one we want to communicate with + JLINK_JTAG_DRPost = 0; // Number of JTAG TAPs following the one we want to communicate with + JLINK_JTAG_IRLen = 4; // IRLen of device we want to communicate with + + JLINK_JTAG_SetDeviceId(0, 0x6BA00477); + + // For Cortex-A55: + JLINK_ExecCommand("CORESIGHT_SetIndexAPBAPToUse = 1"); + // For Cortex-M33: + // JLINK_ExecCommand("CORESIGHT_SetIndexAPBAPToUse = 3"); + + return 0; +} + diff --git a/boards/arm64/imx9/imx93-evk/scripts/ocramboot.ld b/boards/arm64/imx9/imx93-evk/scripts/ocramboot.ld new file mode 100644 index 0000000000000..f87d22f8cd0cc --- /dev/null +++ b/boards/arm64/imx9/imx93-evk/scripts/ocramboot.ld @@ -0,0 +1,150 @@ +/**************************************************************************** + * boards/arm64/imx9/imx93-evk/scripts/ocramboot.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +OUTPUT_ARCH(aarch64) + +ENTRY(__start) +EXTERN(__start) + +/* Memory is organized as follows: + * - ahab reserves memory from 2048k to 0x2049a000 + * - NuttX is compiled into 0x2049a000, ahab expects NuttX here + * - Heap memory is allocated from ocram end to idlestack top + */ + +MEMORY +{ + ocram (rx) : ORIGIN = 0x2049a000, LENGTH = 0x40000 + ocram_data (rw) : ORIGIN = 0x204e0000, LENGTH = 0x2000 + ocram_noload (rw) : ORIGIN = 0x204f0000, LENGTH = 0x30000 +} + +PHDRS +{ + /* R = 100, W = 010, X = 001 */ + + text PT_LOAD FLAGS(5); /* RX */ + rodata PT_LOAD FLAGS(4); /* R */ + data PT_LOAD FLAGS(6); /* RW */ +} + +SECTIONS +{ + .text : + { + _stext = ABSOLUTE(.); /* Text section */ + *(.start .start.*) /* Place __start here */ + *(.text .text.*) + *(.text.cold) + *(.text.unlikely) + *(.fixup) + *(.gnu.warning) + } > ocram :text + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > ocram :text + + /* Vector table must be page aligned */ + + .vector : ALIGN(4096) + { + _vector_start = ABSOLUTE(.); + KEEP(*(.exc_vector_table)) + KEEP(*(".exc_vector_table.*")) + KEEP(*(.vectors)) + _vector_end = ABSOLUTE(.); + } > ocram :text + + _etext = .; + + .rodata : ALIGN(4096) + { + _srodata = ABSOLUTE(.); /* Read-only data */ + *(.rodata .rodata.*) + *(.data.rel.ro) + *(.data.rel.ro.*) + } > ocram :rodata + + _erodata = .; /* End of read-only data */ + _eronly = .; /* End of read-only data */ + + .data : ALIGN(4096) + { + _sdata = ABSOLUTE(.); + *(.data.page_aligned) + *(.data .data.*) + . = ALIGN(8); + *(.data.rel) + *(.data.rel.*) + CONSTRUCTORS + . = ALIGN(8); + _edata = ABSOLUTE(.); + } > ocram_data :data + + .bss (NOLOAD) : + { + . = ALIGN(8); + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } > ocram_noload :data + + .initstack : + { + _s_initstack = ABSOLUTE(.); + *(.initstack) + } > ocram_noload :data + + /* End of data must be page aligned */ + + . = ALIGN(4096); + + g_idle_topstack = .; + _e_initstack = .; + + _sztext = _srodata - _stext; /* _erodata is aligned, after _etext */ + _szrodata = _sdata - _srodata; /* _sdata is aligned, after _erodata */ + + /* Sections to be discarded */ + /DISCARD/ : { + *(.exit.text) + *(.exit.data) + *(.exitcall.exit) + *(.eh_frame) + } + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } +} + +_heapend = ORIGIN(ocram_noload) + LENGTH(ocram_noload); +_szdata = _heapend - _sdata; diff --git a/boards/arm64/imx9/imx93-evk/src/Makefile b/boards/arm64/imx9/imx93-evk/src/Makefile new file mode 100644 index 0000000000000..6a9b3eebfa594 --- /dev/null +++ b/boards/arm64/imx9/imx93-evk/src/Makefile @@ -0,0 +1,45 @@ +############################################################################ +# boards/arm64/imx9/imx93-evk/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = imx9_boardinit.c imx9_bringup.c + +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += imx9_appinit.c +endif + +ifeq ($(CONFIG_PWM),y) +CSRCS += imx9_pwm.c +endif + +ifeq ($(CONFIG_IMX9_LPI2C),y) +CSRCS += imx9_i2c.c +endif + +ifeq ($(CONFIG_IMX9_LPSPI),y) +CSRCS += imx9_spi.c +endif + +ifeq ($(CONFIG_IMX9_USDHC),y) +CSRCS += imx9_usdhc.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm64/imx9/imx93-evk/src/imx93-evk.h b/boards/arm64/imx9/imx93-evk/src/imx93-evk.h new file mode 100644 index 0000000000000..f8125289f4571 --- /dev/null +++ b/boards/arm64/imx9/imx93-evk/src/imx93-evk.h @@ -0,0 +1,125 @@ +/**************************************************************************** + * boards/arm64/imx9/imx93-evk/src/imx93-evk.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_ARM64_IMX9_IMX93_EVK_SRC_IMX93_EVK_H +#define __BOARDS_ARM64_IMX9_IMX93_EVK_SRC_IMX93_EVK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Checking needed by MMC/SDCard */ + +#ifdef CONFIG_NSH_MMCSDSLOTNO +# define SDIO_SLOTNO CONFIG_NSH_MMCSDSLOTNO +#else +# define SDIO_SLOTNO 0 +#endif + +#ifdef CONFIG_NSH_MMCSDMINOR +# define SDIO_MINOR CONFIG_NSH_MMCSDMINOR +#else +# define SDIO_MINOR 0 +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Functions Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +#if defined(CONFIG_BOARDCTL) || defined(CONFIG_BOARD_LATE_INITIALIZE) +int imx9_bringup(void); +#endif + +/**************************************************************************** + * Name: imx9_pwm_setup + * + * Description: + * Initialize PWM outputs + * + ****************************************************************************/ + +#if defined(CONFIG_PWM) +int imx9_pwm_setup(void); +#endif + +/**************************************************************************** + * Name: imx9_i2c_setup + * + * Description: + * Initialize I2C devices and driver + * + ****************************************************************************/ + +#if defined(CONFIG_I2C_DRIVER) +int imx9_i2c_initialize(void); +#endif + +/**************************************************************************** + * Name: imx9_spi_setup + * + * Description: + * Initialize SPI devices and driver + * + ****************************************************************************/ + +#if defined(CONFIG_SPI_DRIVER) +int imx9_spi_initialize(void); +#endif + +/**************************************************************************** + * Name: imx9_usdhc_init + * + * Description: + * Initialize uSDHC driver + * + ****************************************************************************/ + +#if defined(CONFIG_MMCSD) +int imx9_usdhc_init(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_ARM64_IMX9_IMX93_EVK_SRC_IMX93_EVK_H */ diff --git a/boards/arm64/imx9/imx93-evk/src/imx9_appinit.c b/boards/arm64/imx9/imx93-evk/src/imx9_appinit.c new file mode 100644 index 0000000000000..289395145ce57 --- /dev/null +++ b/boards/arm64/imx9/imx93-evk/src/imx9_appinit.c @@ -0,0 +1,76 @@ +/**************************************************************************** + * boards/arm64/imx9/imx93-evk/src/imx9_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "imx93-evk.h" + +#ifdef CONFIG_BOARDCTL + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ + UNUSED(arg); +#ifndef CONFIG_BOARD_LATE_INITIALIZE + /* Perform board initialization */ + + return imx9_bringup(); +#else + return OK; +#endif +} + +#endif /* CONFIG_BOARDCTL */ diff --git a/boards/arm64/imx9/imx93-evk/src/imx9_boardinit.c b/boards/arm64/imx9/imx93-evk/src/imx9_boardinit.c new file mode 100644 index 0000000000000..876b9014de6f0 --- /dev/null +++ b/boards/arm64/imx9/imx93-evk/src/imx9_boardinit.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/arm64/imx9/imx93-evk/src/imx9_boardinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "imx93-evk.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_memory_initialize + * + * Description: + * All i.MX8 architectures must provide the following entry point. This + * entry point is called early in the initialization before memory has + * been configured. This board-specific function is responsible for + * configuring any on-board memories. + * + * Logic in imx9_memory_initialize must be careful to avoid using any + * global variables because those will be uninitialized at the time this + * function is called. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx9_memory_initialize(void) +{ + /* SDRAM was initialized by a bootloader in the supported configurations. */ +} + +/**************************************************************************** + * Name: imx9_board_initialize + * + * Description: + * All i.MX8 architectures must provide the following entry point. This + * entry point is called in the initialization phase -- after + * imx_memory_initialize and after all memory has been configured and + * mapped but before any devices have been initialized. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx9_board_initialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_intitialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board initialization */ + + imx9_bringup(); +} +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/arm64/imx9/imx93-evk/src/imx9_bringup.c b/boards/arm64/imx9/imx93-evk/src/imx9_bringup.c new file mode 100644 index 0000000000000..57d2887c98cab --- /dev/null +++ b/boards/arm64/imx9/imx93-evk/src/imx9_bringup.c @@ -0,0 +1,113 @@ +/**************************************************************************** + * boards/arm64/imx9/imx93-evk/src/imx9_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "imx9_dma_alloc.h" + +#include "imx93-evk.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int imx9_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_IMX9_DMA_ALLOC + /* Initialize the DMA memory allocator */ + + ret = imx9_dma_alloc_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed initialize DMA allocator: %d\n", ret); + } +#endif + +#ifdef CONFIG_PWM + /* Configure PWM outputs */ + + ret = imx9_pwm_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed initialize PWM outputs: %d\n", ret); + } +#endif + +#if defined(CONFIG_I2C_DRIVER) + /* Configure I2C peripheral interfaces */ + + ret = imx9_i2c_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize I2C driver: %d\n", ret); + } +#endif + +#if defined(CONFIG_SPI_DRIVER) + /* Configure SPI peripheral interfaces */ + + ret = imx9_spi_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize SPI driver: %d\n", ret); + } +#endif + +#ifdef CONFIG_MMCSD + ret = imx9_usdhc_init(); + + if (ret < 0) + { + syslog(LOG_ERR, "Failed to init MMCSD driver: %d\n", ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/arm64/imx9/imx93-evk/src/imx9_i2c.c b/boards/arm64/imx9/imx93-evk/src/imx9_i2c.c new file mode 100644 index 0000000000000..8b687e9a0c281 --- /dev/null +++ b/boards/arm64/imx9/imx93-evk/src/imx9_i2c.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * boards/arm64/imx9/imx93-evk/src/imx9_i2c.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "imx9_lpi2c.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_i2c_init + * + * Description: + * Configure the I2C driver. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int imx9_i2c_initialize(void) +{ + int ret = OK; + +#ifdef CONFIG_IMX9_LPI2C1 + struct i2c_master_s *i2c; + + i2c = imx9_i2cbus_initialize(1); + if (i2c == NULL) + { + i2cerr("ERROR: Failed to init I2C0 interface\n"); + return -ENODEV; + } +#endif + +#ifdef CONFIG_I2C_DRIVER + ret = i2c_register(i2c, 0); + if (ret < 0) + { + i2cerr("ERROR: Failed to register I2C0 driver: %d\n", ret); + imx9_i2cbus_uninitialize(i2c); + return ret; + } +#endif + + return ret; +} diff --git a/boards/arm64/imx9/imx93-evk/src/imx9_pwm.c b/boards/arm64/imx9/imx93-evk/src/imx9_pwm.c new file mode 100644 index 0000000000000..494331617ad81 --- /dev/null +++ b/boards/arm64/imx9/imx93-evk/src/imx9_pwm.c @@ -0,0 +1,112 @@ +/**************************************************************************** + * boards/arm64/imx9/imx93-evk/src/imx9_pwm.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include + +#include "imx9_flexio_pwm.h" +#include "imx9_tpm_pwm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_pwm_setup + * + * Description: + * + * Initialize PWM and register PWM devices + * + * Input Parameters: + * None + * + * Returned Value: + * 0 on success, negated error value on error + * + ****************************************************************************/ + +int imx9_pwm_setup(void) +{ + struct pwm_lowerhalf_s *lower_half = NULL; + int ret = 0; + +#ifdef CONFIG_IMX9_FLEXIO1_PWM + lower_half = imx9_flexio_pwm_init(PWM_FLEXIO1); + + if (lower_half) + { + ret = pwm_register("/dev/pwm0", lower_half); + } + else + { + ret = -ENODEV; + } + + if (ret < 0) + { + return ret; + } +#endif + +#ifdef CONFIG_IMX9_FLEXIO2_PWM + lower_half = imx9_flexio_pwm_init(PWM_FLEXIO2); + + if (lower_half) + { + ret = pwm_register("/dev/pwm1", lower_half); + } + else + { + ret = -ENODEV; + } + + if (ret < 0) + { + return ret; + } +#endif + +#ifdef CONFIG_IMX9_TPM3_PWM + lower_half = imx9_tpm_pwm_init(PWM_TPM3); + + if (lower_half) + { + ret = pwm_register("/dev/pwm2", lower_half); + } + else + { + ret = -ENODEV; + } +#endif + + return ret; +} diff --git a/boards/arm64/imx9/imx93-evk/src/imx9_spi.c b/boards/arm64/imx9/imx93-evk/src/imx9_spi.c new file mode 100644 index 0000000000000..ffa9fd118f13a --- /dev/null +++ b/boards/arm64/imx9/imx93-evk/src/imx9_spi.c @@ -0,0 +1,162 @@ +/**************************************************************************** + * boards/arm64/imx9/imx93-evk/src/imx9_spi.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "imx9_gpio.h" +#include "imx9_lpspi.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI6 +static struct spi_dev_s *g_spi6; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#ifdef CONFIG_IMX9_LPSPI + +/**************************************************************************** + * Name: imx9_lpspix_select + * + * Description: + * Enable/disable the SPI chip select. The implementation of this method + * must include handshaking: If a device is selected, it must hold off + * all other attempts to select the device until the device is deselected. + * Required. + * + * Input Parameters: + * dev - Device-specific state data + * devid - Identifies the device to select + * selected - true: slave selected, false: slave de-selected + * + * Returned Value: + * None + * + ****************************************************************************/ + +void imx9_lpspi_select(struct spi_dev_s *dev, uint32_t devid, bool selected) +{ +#ifdef CONFIG_IMX9_LPSPI6 + if (dev == g_spi6) + { + imx9_gpio_write(GPIO_LPSPI6_CS, !selected); + } +#endif +} + +/**************************************************************************** + * Name: imx9_lpspix_status + * + * Description: + * Get SPI/MMC status. Optional. + * + * Input Parameters: + * dev - Device-specific state data + * devid - Identifies the device to report status on + * + * Returned Value: + * Returns a bitset of status values (see SPI_STATUS_* defines) + * + ****************************************************************************/ + +uint8_t imx9_lpspi_status(struct spi_dev_s *dev, uint32_t devid) +{ + return 0; +} + +/**************************************************************************** + * Name: imx9_lpspixcmddata + * + * Description: + * Some devices require an additional out-of-band bit to specify if the + * next word sent to the device is a command or data. This is typical, for + * example, in "9-bit" displays where the 9th bit is the CMD/DATA bit. + * This function provides selection of command or data. + * + * This "latches" the CMD/DATA state. It does not have to be called before + * every word is transferred; only when the CMD/DATA state changes. This + * method is required if CONFIG_SPI_CMDDATA is selected in the NuttX + * configuration + * + * Input Parameters: + * dev - Device-specific state data + * cmd - TRUE: The following word is a command; FALSE: the following words + * are data. + * + * Returned Value: + * OK unless an error occurs. Then a negated errno value is returned + * + ****************************************************************************/ + +int imx9_lpspi_cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) +{ + return -ENODEV; +} +#endif + +/**************************************************************************** + * Name: board_spi_initialize + * + * Description: + * Initialize and register SPI driver for the defined SPI ports. + * + ****************************************************************************/ + +int imx9_spi_initialize(void) +{ + int ret = OK; + +#if defined(CONFIG_IMX9_LPSPI) + /* Initialize SPI device */ + + g_spi6 = imx9_lpspibus_initialize(6); + if (g_spi6 == NULL) + { + spierr("Failed to initialize SPI6\n"); + return -ENODEV; + } +#endif /* CONFIG_MPFS_SPI0 */ + +#ifdef CONFIG_SPI_DRIVER + ret = spi_register(g_spi6, 0); + if (ret < 0) + { + spierr("Failed to register /dev/spi0: %d\n", ret); + } +#endif /* CONFIG_SPI_DRIVER */ + + return ret; +} diff --git a/boards/arm64/imx9/imx93-evk/src/imx9_usdhc.c b/boards/arm64/imx9/imx93-evk/src/imx9_usdhc.c new file mode 100644 index 0000000000000..54116fa795d54 --- /dev/null +++ b/boards/arm64/imx9/imx93-evk/src/imx9_usdhc.c @@ -0,0 +1,84 @@ +/**************************************************************************** + * boards/arm64/imx9/imx93-evk/src/imx9_usdhc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "imx9_usdhc.h" +#include "imx93-evk.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct sdio_dev_s *g_sdio_dev; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_usdhc_init + * + * Description: + * Configure the uSDHC driver. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int imx9_usdhc_init(void) +{ + int ret; + + /* First, get an instance of the SDIO interface */ + + finfo("Initializing SDIO slot %d\n", SDIO_SLOTNO); + + g_sdio_dev = imx9_usdhc_initialize(SDIO_SLOTNO); + if (!g_sdio_dev) + { + ferr("ERROR: Failed to initialize SDIO slot %d\n", SDIO_SLOTNO); + return -ENODEV; + } + + /* Now bind the SDIO interface to the MMC/SD driver */ + + finfo("Bind SDIO to the MMC/SD driver, minor=%d\n", SDIO_MINOR); + + ret = mmcsd_slotinitialize(SDIO_MINOR, g_sdio_dev); + if (ret != OK) + { + ferr("ERROR: Failed to bind SDIO to the MMC/SD driver: %d\n", ret); + return ret; + } + + return OK; +} + diff --git a/boards/arm64/qemu/qemu-armv8a/CMakeLists.txt b/boards/arm64/qemu/qemu-armv8a/CMakeLists.txt new file mode 100644 index 0000000000000..a35ee63f43a41 --- /dev/null +++ b/boards/arm64/qemu/qemu-armv8a/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# boards/arm64/qemu/qemu-armv8a/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/dramboot.ld") + +add_subdirectory(src) diff --git a/boards/arm64/qemu/qemu-armv8a/configs/citest/defconfig b/boards/arm64/qemu/qemu-armv8a/configs/citest/defconfig index 555e56126e8eb..43afdbef74d20 100644 --- a/boards/arm64/qemu/qemu-armv8a/configs/citest/defconfig +++ b/boards/arm64/qemu/qemu-armv8a/configs/citest/defconfig @@ -19,7 +19,6 @@ CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SCHED=y CONFIG_DEBUG_SCHED_ERROR=y -CONFIG_DEBUG_SCHED_INFO=y CONFIG_DEBUG_SCHED_WARN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_TASK_STACKSIZE=8192 @@ -37,7 +36,6 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 CONFIG_RAMLOG=y diff --git a/boards/arm64/qemu/qemu-armv8a/configs/citest_smp/defconfig b/boards/arm64/qemu/qemu-armv8a/configs/citest_smp/defconfig index 1bd0feb067aee..a4f51ab8c1df2 100644 --- a/boards/arm64/qemu/qemu-armv8a/configs/citest_smp/defconfig +++ b/boards/arm64/qemu/qemu-armv8a/configs/citest_smp/defconfig @@ -19,7 +19,6 @@ CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SCHED=y CONFIG_DEBUG_SCHED_ERROR=y -CONFIG_DEBUG_SCHED_INFO=y CONFIG_DEBUG_SCHED_WARN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_TASK_STACKSIZE=16384 @@ -35,7 +34,6 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=16384 CONFIG_RAMLOG=y diff --git a/boards/arm64/qemu/qemu-armv8a/configs/fb/defconfig b/boards/arm64/qemu/qemu-armv8a/configs/fb/defconfig index 93272e7273577..2d8d7edd504cd 100644 --- a/boards/arm64/qemu/qemu-armv8a/configs/fb/defconfig +++ b/boards/arm64/qemu/qemu-armv8a/configs/fb/defconfig @@ -46,13 +46,11 @@ CONFIG_IOB_BUFSIZE=1534 CONFIG_IOB_NBUFFERS=64 CONFIG_IOB_NCHAINS=64 CONFIG_IOB_THROTTLE=8 -CONFIG_LIBC_FDT=y CONFIG_MM_IOB=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_OPENAMP=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 CONFIG_RAM_SIZE=134217728 diff --git a/boards/arm64/qemu/qemu-armv8a/configs/netnsh/defconfig b/boards/arm64/qemu/qemu-armv8a/configs/netnsh/defconfig index df4f3ee45ceaa..6636dea2ee2e9 100644 --- a/boards/arm64/qemu/qemu-armv8a/configs/netnsh/defconfig +++ b/boards/arm64/qemu/qemu-armv8a/configs/netnsh/defconfig @@ -47,7 +47,6 @@ CONFIG_IOB_ALIGNMENT=16 CONFIG_IOB_BUFSIZE=1534 CONFIG_IOB_NBUFFERS=64 CONFIG_IOB_THROTTLE=8 -CONFIG_LIBC_FDT=y CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSCLIENT_ENTRIES=4 @@ -77,7 +76,6 @@ CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y CONFIG_NXPLAYER_HTTP_STREAMING_SUPPORT=y -CONFIG_OPENAMP=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 CONFIG_RAM_SIZE=134217728 @@ -99,6 +97,7 @@ CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_FDTDUMP=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NXPLAYER=y +CONFIG_SYSTEM_NXRECORDER=y CONFIG_SYSTEM_PING=y CONFIG_SYSTEM_SYSTEM=y CONFIG_SYSTEM_TELNETD_SESSION_STACKSIZE=8192 diff --git a/boards/arm64/qemu/qemu-armv8a/configs/netnsh_hv/defconfig b/boards/arm64/qemu/qemu-armv8a/configs/netnsh_hv/defconfig index 7a9c826be1367..055edb8c7728a 100644 --- a/boards/arm64/qemu/qemu-armv8a/configs/netnsh_hv/defconfig +++ b/boards/arm64/qemu/qemu-armv8a/configs/netnsh_hv/defconfig @@ -48,7 +48,6 @@ CONFIG_IOB_ALIGNMENT=16 CONFIG_IOB_BUFSIZE=1534 CONFIG_IOB_NBUFFERS=64 CONFIG_IOB_THROTTLE=8 -CONFIG_LIBC_FDT=y CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSCLIENT_ENTRIES=4 @@ -78,7 +77,6 @@ CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y CONFIG_NXPLAYER_HTTP_STREAMING_SUPPORT=y -CONFIG_OPENAMP=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 CONFIG_RAM_SIZE=134217728 @@ -100,6 +98,7 @@ CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_FDTDUMP=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NXPLAYER=y +CONFIG_SYSTEM_NXRECORDER=y CONFIG_SYSTEM_PING=y CONFIG_SYSTEM_SYSTEM=y CONFIG_SYSTEM_TELNETD_SESSION_STACKSIZE=8192 diff --git a/boards/arm64/qemu/qemu-armv8a/configs/netnsh_smp/defconfig b/boards/arm64/qemu/qemu-armv8a/configs/netnsh_smp/defconfig index 3567fc3e39985..58bd9851e095e 100644 --- a/boards/arm64/qemu/qemu-armv8a/configs/netnsh_smp/defconfig +++ b/boards/arm64/qemu/qemu-armv8a/configs/netnsh_smp/defconfig @@ -45,7 +45,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_IOB_BUFSIZE=1534 CONFIG_IOB_NBUFFERS=64 CONFIG_IOB_THROTTLE=8 -CONFIG_LIBC_FDT=y CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSCLIENT_ENTRIES=4 @@ -75,7 +74,6 @@ CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y CONFIG_NXPLAYER_HTTP_STREAMING_SUPPORT=y -CONFIG_OPENAMP=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 CONFIG_RAM_SIZE=134217728 @@ -98,6 +96,7 @@ CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_FDTDUMP=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NXPLAYER=y +CONFIG_SYSTEM_NXRECORDER=y CONFIG_SYSTEM_PING=y CONFIG_SYSTEM_SYSTEM=y CONFIG_SYSTEM_TASKSET=y diff --git a/boards/arm64/qemu/qemu-armv8a/configs/netnsh_smp_hv/defconfig b/boards/arm64/qemu/qemu-armv8a/configs/netnsh_smp_hv/defconfig index 7c9cf1b069b89..7e5d0d812f970 100644 --- a/boards/arm64/qemu/qemu-armv8a/configs/netnsh_smp_hv/defconfig +++ b/boards/arm64/qemu/qemu-armv8a/configs/netnsh_smp_hv/defconfig @@ -46,7 +46,6 @@ CONFIG_INTELHEX_BINARY=y CONFIG_IOB_BUFSIZE=1534 CONFIG_IOB_NBUFFERS=64 CONFIG_IOB_THROTTLE=8 -CONFIG_LIBC_FDT=y CONFIG_NET=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSCLIENT_ENTRIES=4 @@ -76,7 +75,6 @@ CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y CONFIG_NXPLAYER_HTTP_STREAMING_SUPPORT=y -CONFIG_OPENAMP=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 CONFIG_RAM_SIZE=134217728 @@ -99,6 +97,7 @@ CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_FDTDUMP=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NXPLAYER=y +CONFIG_SYSTEM_NXRECORDER=y CONFIG_SYSTEM_PING=y CONFIG_SYSTEM_SYSTEM=y CONFIG_SYSTEM_TASKSET=y diff --git a/boards/arm64/qemu/qemu-armv8a/configs/nsh/defconfig b/boards/arm64/qemu/qemu-armv8a/configs/nsh/defconfig index 25100dcaa36ea..3ba6aac5a8c90 100644 --- a/boards/arm64/qemu/qemu-armv8a/configs/nsh/defconfig +++ b/boards/arm64/qemu/qemu-armv8a/configs/nsh/defconfig @@ -23,7 +23,6 @@ CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SCHED=y CONFIG_DEBUG_SCHED_ERROR=y -CONFIG_DEBUG_SCHED_INFO=y CONFIG_DEBUG_SCHED_WARN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_TASK_STACKSIZE=8192 @@ -40,12 +39,10 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=8192 CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FDT=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 CONFIG_RAMLOG=y diff --git a/boards/arm64/qemu/qemu-armv8a/configs/nsh_fiq/defconfig b/boards/arm64/qemu/qemu-armv8a/configs/nsh_fiq/defconfig index 8976c6914cc42..df5a8611a4048 100644 --- a/boards/arm64/qemu/qemu-armv8a/configs/nsh_fiq/defconfig +++ b/boards/arm64/qemu/qemu-armv8a/configs/nsh_fiq/defconfig @@ -41,12 +41,10 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=8192 CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FDT=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 CONFIG_RAMLOG=y diff --git a/boards/arm64/qemu/qemu-armv8a/configs/nsh_gicv2/defconfig b/boards/arm64/qemu/qemu-armv8a/configs/nsh_gicv2/defconfig index 4ba30653b473f..f233e388e68b6 100644 --- a/boards/arm64/qemu/qemu-armv8a/configs/nsh_gicv2/defconfig +++ b/boards/arm64/qemu/qemu-armv8a/configs/nsh_gicv2/defconfig @@ -20,7 +20,6 @@ CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SCHED=y CONFIG_DEBUG_SCHED_ERROR=y -CONFIG_DEBUG_SCHED_INFO=y CONFIG_DEBUG_SCHED_WARN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_TASK_STACKSIZE=8192 @@ -38,7 +37,6 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 CONFIG_RAMLOG=y diff --git a/boards/arm64/qemu/qemu-armv8a/configs/nsh_smp/defconfig b/boards/arm64/qemu/qemu-armv8a/configs/nsh_smp/defconfig index 3a21ddf0f74fe..0927ffb6feb07 100644 --- a/boards/arm64/qemu/qemu-armv8a/configs/nsh_smp/defconfig +++ b/boards/arm64/qemu/qemu-armv8a/configs/nsh_smp/defconfig @@ -5,6 +5,7 @@ # You can then do "make savedefconfig" to generate a new defconfig file that includes your # modifications. # +# CONFIG_NSH_DISABLE_MW is not set CONFIG_ARCH="arm64" CONFIG_ARCH_ARM64=y CONFIG_ARCH_BOARD="qemu-armv8a" @@ -14,20 +15,22 @@ CONFIG_ARCH_CHIP_QEMU=y CONFIG_ARCH_CHIP_QEMU_A53=y CONFIG_ARCH_EARLY_PRINT=y CONFIG_ARCH_INTERRUPTSTACK=8192 +CONFIG_ARCH_STACKDUMP=y CONFIG_ARM64_STRING_FUNCTION=y +CONFIG_BENCHMARK_OSPERF=y CONFIG_BUILTIN=y CONFIG_DEBUG_ASSERTIONS=y CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SCHED=y CONFIG_DEBUG_SCHED_ERROR=y -CONFIG_DEBUG_SCHED_INFO=y CONFIG_DEBUG_SCHED_WARN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_TASK_STACKSIZE=16384 CONFIG_DEV_ZERO=y CONFIG_EXAMPLES_HELLO=y CONFIG_EXPERIMENTAL=y +CONFIG_FRAME_POINTER=y CONFIG_FS_PROCFS=y CONFIG_FS_PROCFS_REGISTER=y CONFIG_FS_ROMFS=y @@ -38,7 +41,7 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y +CONFIG_PIPES=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=16384 CONFIG_RAMLOG=y @@ -47,9 +50,11 @@ CONFIG_RAM_START=0x40000000 CONFIG_RAW_BINARY=y CONFIG_READLINE_CMD_HISTORY=y CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y CONFIG_SCHED_HPWORK=y CONFIG_SCHED_HPWORKPRIORITY=192 CONFIG_SMP=y +CONFIG_SMP_NCPUS=2 CONFIG_STACK_COLORATION=y CONFIG_START_MONTH=3 CONFIG_START_YEAR=2022 @@ -62,7 +67,6 @@ CONFIG_TESTING_GETPRIME=y CONFIG_TESTING_OSTEST=y CONFIG_TESTING_OSTEST_STACKSIZE=16384 CONFIG_TESTING_SMP=y -CONFIG_TICKET_SPINLOCK=y CONFIG_UART1_BASE=0x9000000 CONFIG_UART1_IRQ=33 CONFIG_UART1_PL011=y diff --git a/boards/arm64/qemu/qemu-armv8a/configs/nsh_smp_tickless/defconfig b/boards/arm64/qemu/qemu-armv8a/configs/nsh_smp_tickless/defconfig index 95eed2b60d46a..29b48dcc80986 100644 --- a/boards/arm64/qemu/qemu-armv8a/configs/nsh_smp_tickless/defconfig +++ b/boards/arm64/qemu/qemu-armv8a/configs/nsh_smp_tickless/defconfig @@ -20,7 +20,6 @@ CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SCHED=y CONFIG_DEBUG_SCHED_ERROR=y -CONFIG_DEBUG_SCHED_INFO=y CONFIG_DEBUG_SCHED_WARN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_TASK_STACKSIZE=16384 @@ -36,7 +35,6 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=16384 CONFIG_RAMLOG=y diff --git a/boards/arm64/qemu/qemu-armv8a/configs/sotest/defconfig b/boards/arm64/qemu/qemu-armv8a/configs/sotest/defconfig index 4ecdcd2e57542..dde988e6b42ae 100644 --- a/boards/arm64/qemu/qemu-armv8a/configs/sotest/defconfig +++ b/boards/arm64/qemu/qemu-armv8a/configs/sotest/defconfig @@ -28,7 +28,6 @@ CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SCHED=y CONFIG_DEBUG_SCHED_ERROR=y -CONFIG_DEBUG_SCHED_INFO=y CONFIG_DEBUG_SCHED_WARN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_TASK_STACKSIZE=8192 @@ -48,7 +47,6 @@ CONFIG_IDLETHREAD_STACKSIZE=8192 CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_DLFCN=y -CONFIG_LIBC_FDT=y CONFIG_MODLIB_DUMPBUFFER=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/arm64/qemu/qemu-armv8a/scripts/dramboot.ld b/boards/arm64/qemu/qemu-armv8a/scripts/dramboot.ld index c8857860ea1cd..55cfc44b9dda1 100644 --- a/boards/arm64/qemu/qemu-armv8a/scripts/dramboot.ld +++ b/boards/arm64/qemu/qemu-armv8a/scripts/dramboot.ld @@ -18,6 +18,8 @@ * ****************************************************************************/ +#include + OUTPUT_ARCH(aarch64) ENTRY(__start) @@ -30,9 +32,24 @@ PHDRS SECTIONS { . = 0x40280000; /* uboot load address */ + + /* where the global variable out-of-bounds detection information located */ +#ifdef CONFIG_MM_KASAN_GLOBAL + .kasan.unused : + { + *(.data..LASANLOC*) + } + .kasan.global : + { + KEEP (*(.data..LASAN0)) + KEEP (*(.data.rel.local..LASAN0)) + } +#endif + _start = .; .text : { _stext = .; /* Text section */ + *(.start .start.*) /* Place __start here */ *(.text) *(.text.cold) *(.text.unlikely) diff --git a/boards/arm64/qemu/qemu-armv8a/src/CMakeLists.txt b/boards/arm64/qemu/qemu-armv8a/src/CMakeLists.txt new file mode 100644 index 0000000000000..cdae09b23b848 --- /dev/null +++ b/boards/arm64/qemu/qemu-armv8a/src/CMakeLists.txt @@ -0,0 +1,32 @@ +# ############################################################################## +# boards/arm64/qemu/qemu-armv8a/src/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## +set(SRCS qemu_boardinit.c qemu_bringup.c) + +if(CONFIG_BOARDCTL) + list(APPEND SRCS qemu_appinit.c) + +endif() + +if(CONFIG_LIBC_FDT) + target_include_directories(board + PRIVATE ${NUTTX_DIR}/libs/libc/fdt/dtc/libfdt) +endif() + +target_sources(board PRIVATE ${SRCS}) diff --git a/boards/arm64/qemu/qemu-armv8a/src/qemu_bringup.c b/boards/arm64/qemu/qemu-armv8a/src/qemu_bringup.c index bf1b5c0543851..d5fdea93423dc 100644 --- a/boards/arm64/qemu/qemu-armv8a/src/qemu_bringup.c +++ b/boards/arm64/qemu/qemu-armv8a/src/qemu_bringup.c @@ -41,96 +41,15 @@ * Pre-processor Definitions ****************************************************************************/ -#define QEMU_SPI_IRQ_BASE 32 +#ifndef QEMU_SPI_IRQ_BASE +#define QEMU_SPI_IRQ_BASE 32 +#endif /**************************************************************************** * Private Functions ****************************************************************************/ #if defined(CONFIG_LIBC_FDT) && defined(CONFIG_DEVICE_TREE) - -/**************************************************************************** - * Name: fdt_get_irq - * - * Description: - * Only can be use when the corresponding node's parent interrupt - * controller is intc node. - * - ****************************************************************************/ - -static int unused_code -fdt_get_irq(const void *fdt, int offset) -{ - const fdt32_t *pv; - int irq = -ENOENT; - - pv = fdt_getprop(fdt, offset, "interrupts", NULL); - if (pv != NULL) - { - irq = fdt32_ld(pv + 1) + QEMU_SPI_IRQ_BASE; - } - - return irq; -} - -/**************************************************************************** - * Name: fdt_get_irq_by_path - * - * Description: - * Only can be use when the corresponding node's parent interrupt - * controller is intc node. - * - ****************************************************************************/ - -static int unused_code -fdt_get_irq_by_path(const void *fdt, const char *path) -{ - return fdt_get_irq(fdt, fdt_path_offset(fdt, path)); -} - -/**************************************************************************** - * Name: fdt_get_reg_base - ****************************************************************************/ - -static uintptr_t unused_code -fdt_get_reg_base(const void *fdt, int offset) -{ - const void *reg; - uintptr_t addr = 0; - int parentoff; - - parentoff = fdt_parent_offset(fdt, offset); - if (parentoff < 0) - { - return addr; - } - - reg = fdt_getprop(fdt, offset, "reg", NULL); - if (reg != NULL) - { - if (fdt_address_cells(fdt, parentoff) == 2) - { - addr = fdt64_ld(reg); - } - else - { - addr = fdt32_ld(reg); - } - } - - return addr; -} - -/**************************************************************************** - * Name: fdt_get_reg_base_by_path - ****************************************************************************/ - -static uintptr_t unused_code -fdt_get_reg_base_by_path(const void *fdt, const char *path) -{ - return fdt_get_reg_base(fdt, fdt_path_offset(fdt, path)); -} - #ifdef CONFIG_DRIVERS_VIRTIO_MMIO /**************************************************************************** @@ -151,8 +70,8 @@ static void register_virtio_devices_from_fdt(const void *fdt) break; } - addr = fdt_get_reg_base(fdt, offset); - irqnum = fdt_get_irq(fdt, offset); + addr = fdt_get_reg_base(fdt, offset, 0); + irqnum = fdt_get_irq(fdt, offset, 1, QEMU_SPI_IRQ_BASE); if (addr > 0 && irqnum >= 0) { virtio_register_mmio_device((void *)addr, irqnum); @@ -198,6 +117,16 @@ int qemu_bringup(void) { int ret; +#ifdef CONFIG_FS_TMPFS + /* Mount the tmp file system */ + + ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount tmpfs at /tmp: %d\n", ret); + } +#endif + #ifdef CONFIG_FS_PROCFS /* Mount the procfs file system */ diff --git a/boards/arm64/rk3399/nanopi_m4/configs/nsh/defconfig b/boards/arm64/rk3399/nanopi_m4/configs/nsh/defconfig index 1cb85eb4567ad..05d45a8ce4d6a 100644 --- a/boards/arm64/rk3399/nanopi_m4/configs/nsh/defconfig +++ b/boards/arm64/rk3399/nanopi_m4/configs/nsh/defconfig @@ -27,6 +27,7 @@ CONFIG_DEBUG_SCHED_WARN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_TASK_STACKSIZE=8192 CONFIG_DEV_ZERO=y +CONFIG_ETC_ROMFS=y CONFIG_EXAMPLES_HELLO=y CONFIG_EXAMPLES_LEDS=y CONFIG_EXPERIMENTAL=y @@ -38,11 +39,9 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=8192 CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 CONFIG_RAMLOG=y diff --git a/boards/arm64/rk3399/nanopi_m4/include/nsh_romfsimg.h b/boards/arm64/rk3399/nanopi_m4/include/nsh_romfsimg.h deleted file mode 100644 index 61cc98debb023..0000000000000 --- a/boards/arm64/rk3399/nanopi_m4/include/nsh_romfsimg.h +++ /dev/null @@ -1,22 +0,0 @@ -/*************************************************************************** - * boards/arm64/rk3399/nanopi_m4/include/nsh_romfsimg.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ***************************************************************************/ - -extern const unsigned char romfs_img[]; -extern unsigned int romfs_img_len; diff --git a/boards/arm64/rk3399/nanopi_m4/scripts/dramboot.ld b/boards/arm64/rk3399/nanopi_m4/scripts/dramboot.ld index bebe73fff0013..d202807ea601c 100644 --- a/boards/arm64/rk3399/nanopi_m4/scripts/dramboot.ld +++ b/boards/arm64/rk3399/nanopi_m4/scripts/dramboot.ld @@ -43,6 +43,7 @@ SECTIONS _start = .; .text : { _stext = .; /* Text section */ + *(.start .start.*) /* Place __start here */ *(.text) *(.text.cold) *(.text.unlikely) diff --git a/boards/arm64/rk3399/nanopi_m4/src/Makefile b/boards/arm64/rk3399/nanopi_m4/src/Makefile index 2f6fedebb4f67..e64f06871d03b 100644 --- a/boards/arm64/rk3399/nanopi_m4/src/Makefile +++ b/boards/arm64/rk3399/nanopi_m4/src/Makefile @@ -23,10 +23,8 @@ include $(TOPDIR)/Make.defs CSRCS = nanopi_m4_boardinit.c CSRCS += nanopi_m4_appinit.c -ifeq ($(CONFIG_NSH_ROMFSETC),y) -ifneq ($(CONFIG_NSH_CUSTOMROMFS),y) +ifeq ($(CONFIG_ETC_ROMFS),y) RCSRCS = etc/init.d/rc.sysinit etc/init.d/rcS endif -endif include $(TOPDIR)/boards/Board.mk diff --git a/boards/arm64/rk3399/pinephonepro/configs/nsh/defconfig b/boards/arm64/rk3399/pinephonepro/configs/nsh/defconfig index 6b747e755ba35..958406938eb08 100644 --- a/boards/arm64/rk3399/pinephonepro/configs/nsh/defconfig +++ b/boards/arm64/rk3399/pinephonepro/configs/nsh/defconfig @@ -41,7 +41,6 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_STACK_MIN=8192 CONFIG_RAMLOG=y diff --git a/boards/arm64/rk3399/pinephonepro/scripts/dramboot.ld b/boards/arm64/rk3399/pinephonepro/scripts/dramboot.ld index e50ea0b0ea1c3..f3a47b2719846 100644 --- a/boards/arm64/rk3399/pinephonepro/scripts/dramboot.ld +++ b/boards/arm64/rk3399/pinephonepro/scripts/dramboot.ld @@ -34,6 +34,7 @@ SECTIONS _start = .; .text : { _stext = .; /* Text section */ + *(.start .start.*) /* Place __start here */ *(.text) *(.text.cold) *(.text.unlikely) diff --git a/boards/arm64/rk3399/pinephonepro/src/Makefile b/boards/arm64/rk3399/pinephonepro/src/Makefile index 376c850d4d59f..c8d544bbc43b6 100644 --- a/boards/arm64/rk3399/pinephonepro/src/Makefile +++ b/boards/arm64/rk3399/pinephonepro/src/Makefile @@ -1,5 +1,5 @@ ############################################################################ -# boards/arm64/a64/pinephone/src/Makefile +# boards/arm64/rk3399/pinephonepro/src/Makefile # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/avr/at32uc3/avr32dev1/include/board.h b/boards/avr/at32uc3/avr32dev1/include/board.h index 89862b3adeadf..947488cbaee2b 100644 --- a/boards/avr/at32uc3/avr32dev1/include/board.h +++ b/boards/avr/at32uc3/avr32dev1/include/board.h @@ -124,7 +124,7 @@ /* Pin muliplexing selecion *************************************************/ #define PINMUX_USART1_RXD PINMUX_USART1_RXD_2 -#define PINMUX_USART1_TXD PINMUX_USART1_TXD_1 +#define PINMUX_USART1_TXD PINMUX_USART1_TXD_2 /* LED definitions **********************************************************/ diff --git a/boards/avr/at32uc3/avr32dev1/scripts/avr32dev1.ld b/boards/avr/at32uc3/avr32dev1/scripts/avr32dev1.ld index abe2d6c61c56f..bbf513faa2035 100644 --- a/boards/avr/at32uc3/avr32dev1/scripts/avr32dev1.ld +++ b/boards/avr/at32uc3/avr32dev1/scripts/avr32dev1.ld @@ -39,7 +39,8 @@ MEMORY SECTIONS { .text : { - _stext = ABSOLUTE(.); + . = ALIGN(4); + _stext = .; *(.vectors) *(.text .text.*) *(.fixup) @@ -51,27 +52,29 @@ SECTIONS *(.got) *(.gcc_except_table) *(.gnu.linkonce.r.*) - _etext = ABSOLUTE(.); + . = ALIGN(4); + _etext = .; } > flash - _eronly = ABSOLUTE(.); /* See below */ + _eronly = .; /* See below */ - .data : { - _sdata = ABSOLUTE(.); + .data : AT(_etext) { + . = ALIGN(4); + _sdata = .; *(.data .data.*) *(.gnu.linkonce.d.*) CONSTRUCTORS . = ALIGN(4); - _edata = ABSOLUTE(.); - } > intram AT > flash + _edata = .; + } > intram .bss : { /* BSS */ - _sbss = ABSOLUTE(.); + _sbss = .; *(.bss .bss.*) *(.gnu.linkonce.b.*) *(COMMON) . = ALIGN(4); - _ebss = ABSOLUTE(.); + _ebss = .; } > intram /* Stabs debugging sections. */ .stab 0 : { *(.stab) } diff --git a/boards/boardctl.c b/boards/boardctl.c index 2707bb161c6c9..c6cae7ba41581 100644 --- a/boards/boardctl.c +++ b/boards/boardctl.c @@ -30,6 +30,7 @@ #include #include +#include #include #include #include @@ -835,6 +836,25 @@ int boardctl(unsigned int cmd, uintptr_t arg) break; #endif +#ifdef CONFIG_BOARDCTL_IRQ_AFFINITY + /* CMD: BOARDIOC_IRQ_AFFINITY + * DESCRIPTION: Set an IRQ affinity by software. + * ARG: Integer array: + member 0 is the interrupt number + member 1 is the CPU index + * CONFIGURATION: CONFIG_BOARDCTL_IRQ_AFFINITY + * DEPENDENCIES: Bound Multi-Processing (CONFIG_BMP) + */ + + case BOARDIOC_IRQ_AFFINITY: + { + FAR unsigned int *affinity = (FAR unsigned int *)arg; + up_affinity_irq(affinity[0], affinity[1]); + ret = OK; + } + break; +#endif + default: { #ifdef CONFIG_BOARDCTL_IOCTL diff --git a/boards/renesas/sh1/us7032evb1/Kconfig b/boards/renesas/sh1/us7032evb1/Kconfig index 0636ec5e3403c..6393bdbf6f098 100644 --- a/boards/renesas/sh1/us7032evb1/Kconfig +++ b/boards/renesas/sh1/us7032evb1/Kconfig @@ -3,5 +3,5 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -if ARCH_BOARD_TWR_K60N512 +if ARCH_BOARD_US7032EVB1 endif diff --git a/boards/risc-v/bl602/bl602evb/scripts/ld.script b/boards/risc-v/bl602/bl602evb/scripts/ld.script index 167cf0a3252d4..bd305f9122eaf 100644 --- a/boards/risc-v/bl602/bl602evb/scripts/ld.script +++ b/boards/risc-v/bl602/bl602evb/scripts/ld.script @@ -164,39 +164,21 @@ SECTIONS PROVIDE ( __boot2_flash_cfg_end = . ); } > ram_tcm - .noinit (NOLOAD) : - { - . = ALIGN(16); - *(.noinit_idle_stack*) - } > ram_tcm - .bss (NOLOAD) : { - PROVIDE( __bss_start = ADDR(.bss) ); - PROVIDE( __bss_end = ADDR(.bss) + SIZEOF(.bss) ); - - PROVIDE( _sbss = __bss_start ); - PROVIDE( _ebss = __bss_end ); + PROVIDE( _sbss = ADDR(.bss) ); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss .bss.*) *(.gnu.linkonce.b.*) *(COMMON) + . = ALIGN(32); + _ebss = ABSOLUTE(.); } > ram_tcm - . = ALIGN(4); - - PROVIDE( _heap_start = . ); - PROVIDE( _heap_size = ADDR(.stack) - _heap_start ); - - /* .stack ORIGIN(ram_tcm) + LENGTH(ram_tcm) - __stack_size (NOLOAD) : */ - .stack ORIGIN(ram_tcm) + LENGTH(ram_tcm) (NOLOAD) : - { - PROVIDE( _sp_irq_base = . ); - /* . = . + __stack_size; */ - /* PROVIDE( _sp_main = . ); */ - } >ram_tcm + /* Heap end used in code */ + PROVIDE(__heap_end = ORIGIN(ram_tcm) + LENGTH(ram_tcm)); /*CFG FW used in code*/ PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start ); diff --git a/boards/risc-v/bl808/ox64/configs/nsh/defconfig b/boards/risc-v/bl808/ox64/configs/nsh/defconfig index 32aaa1ea5db9d..7cdd365ef2b5b 100644 --- a/boards/risc-v/bl808/ox64/configs/nsh/defconfig +++ b/boards/risc-v/bl808/ox64/configs/nsh/defconfig @@ -34,7 +34,7 @@ CONFIG_ARCH_USE_S_MODE=y CONFIG_BL808_UART3=y CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LATE_INITIALIZE=y -CONFIG_BOARD_LOOPSPERMSEC=116524 +CONFIG_BOARD_LOOPSPERMSEC=1120 CONFIG_BUILD_KERNEL=y CONFIG_DEBUG_ASSERTIONS=y CONFIG_DEBUG_ASSERTIONS_EXPRESSION=y @@ -79,6 +79,7 @@ CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_PROGNAME="init" CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y CONFIG_UART3_BAUD=2000000 CONFIG_UART3_SERIAL_CONSOLE=y CONFIG_USEC_PER_TICK=1000 diff --git a/boards/risc-v/bl808/ox64/scripts/ld.script b/boards/risc-v/bl808/ox64/scripts/ld.script index 94f115dd792ee..e47b594ff0ab1 100644 --- a/boards/risc-v/bl808/ox64/scripts/ld.script +++ b/boards/risc-v/bl808/ox64/scripts/ld.script @@ -116,6 +116,7 @@ SECTIONS *(.sbss.*) *(.gnu.linkonce.b*) *(COMMON) + . = ALIGN(32); _ebss = . ; } > ksram diff --git a/boards/risc-v/esp32c3/common/.gitignore b/boards/risc-v/esp32c3-legacy/common/.gitignore similarity index 100% rename from boards/risc-v/esp32c3/common/.gitignore rename to boards/risc-v/esp32c3-legacy/common/.gitignore diff --git a/boards/risc-v/esp32c3-legacy/common/Kconfig b/boards/risc-v/esp32c3-legacy/common/Kconfig new file mode 100644 index 0000000000000..bf9503f547993 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/common/Kconfig @@ -0,0 +1,74 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +config ESP32C3_MERGE_BINS + bool "Merge raw binary files into a single file" + default n + ---help--- + Merge the raw binary files into a single file for flashing to the + device. + This is only useful when the path to binary files (e.g. bootloader) + is provided via the ESPTOOL_BINDIR variable. + +choice ESP32C3_SPIFLASH_FS + prompt "Mount SPI Flash MTD on bring-up" + default ESP32C3_SPIFLASH_SMARTFS + depends on ESP32C3_MTD + optional + ---help--- + Mount the SPI Flash MTD with the selected File System format on board + bring-up. + If not selected, the MTD will be registered as a device node on /dev. + +config ESP32C3_SPIFLASH_SMARTFS + bool "SmartFS" + select FS_SMARTFS + select MTD_SMART + depends on !ESP32C3_SECURE_FLASH_ENC_ENABLED + +comment "SmartFS not supported with Flash Encryption" + depends on ESP32C3_SECURE_FLASH_ENC_ENABLED + +config ESP32C3_SPIFLASH_NXFFS + bool "NXFFS" + select FS_NXFFS + depends on !ESP32C3_SECURE_FLASH_ENC_ENABLED + +comment "NXFFS not supported with Flash Encryption" + depends on ESP32C3_SECURE_FLASH_ENC_ENABLED + +config ESP32C3_SPIFLASH_SPIFFS + bool "SPIFFS" + select FS_SPIFFS + depends on !ESP32C3_SECURE_FLASH_ENC_ENABLED + +comment "SPIFFS not supported with Flash Encryption" + depends on ESP32C3_SECURE_FLASH_ENC_ENABLED + +config ESP32C3_SPIFLASH_LITTLEFS + bool "LittleFS" + select FS_LITTLEFS + +config ESP32C3_SPIFLASH_MTD_CONFIG + bool "Non-volatile storage" + +endchoice # ESP32C3_SPIFLASH_FS + +config ESP32C3_SPIFLASH_FS_MOUNT_PT + string "File-system Mount Point" + depends on ESP32C3_SPIFLASH_LITTLEFS + default "/data" + +if LCD_ST7735 || LCD_ST7789 || LCD_GC9A01 + +config ESP32C3_LCD_RSTPIN + int "LCD reset pin" + default 9 + +config ESP32C3_LCD_BLPIN + int "LCD backlight pin" + default 18 + +endif # LCD_ST7735 || LCD_ST7789 || LCD_GC9A01 diff --git a/boards/risc-v/esp32c3-legacy/common/Makefile b/boards/risc-v/esp32c3-legacy/common/Makefile new file mode 100644 index 0000000000000..26c4aef36e522 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/common/Makefile @@ -0,0 +1,33 @@ +############################################################################# +# boards/risc-v/esp32c3-legacy/common/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +include board/Make.defs +include src/Make.defs + +DEPPATH += --dep-path board +DEPPATH += --dep-path src + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/risc-v/esp32c3/common/include/esp32c3_board_adc.h b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_adc.h similarity index 97% rename from boards/risc-v/esp32c3/common/include/esp32c3_board_adc.h rename to boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_adc.h index 5faff36ff412d..ad20948aa4fea 100644 --- a/boards/risc-v/esp32c3/common/include/esp32c3_board_adc.h +++ b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_adc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/include/esp32c3_board_adc.h + * boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_adc.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/include/esp32c3_board_apds9960.h b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_apds9960.h similarity index 97% rename from boards/risc-v/esp32c3/common/include/esp32c3_board_apds9960.h rename to boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_apds9960.h index 8aa05e802b412..b7448e3c45d2e 100644 --- a/boards/risc-v/esp32c3/common/include/esp32c3_board_apds9960.h +++ b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_apds9960.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/include/esp32c3_board_apds9960.h + * boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_apds9960.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/include/esp32c3_board_bmp180.h b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_bmp180.h similarity index 97% rename from boards/risc-v/esp32c3/common/include/esp32c3_board_bmp180.h rename to boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_bmp180.h index 211e1919dcb14..8492465fa547d 100644 --- a/boards/risc-v/esp32c3/common/include/esp32c3_board_bmp180.h +++ b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_bmp180.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/include/esp32c3_board_bmp180.h + * boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_bmp180.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/include/esp32c3_board_i2c.h b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_i2c.h similarity index 97% rename from boards/risc-v/esp32c3/common/include/esp32c3_board_i2c.h rename to boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_i2c.h index 0404336f4ef7c..5b705ba3830e1 100644 --- a/boards/risc-v/esp32c3/common/include/esp32c3_board_i2c.h +++ b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_i2c.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/include/esp32c3_board_i2c.h + * boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_i2c.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_ice40.h b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_ice40.h new file mode 100644 index 0000000000000..935077d7eeaa1 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_ice40.h @@ -0,0 +1,70 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_ice40.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C3_LEGACY_COMMON_INCLUDE_ESP32C3_BOARD_ICE40_H +#define __BOARDS_RISCV_ESP32C3_LEGACY_COMMON_INCLUDE_ESP32C3_BOARD_ICE40_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_ice40_setup + * + * Description: + * Initialize ICE40 FPGA GPIOs, SPI and register the ICE40 driver. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_ICE40 +int esp32c3_ice40_setup(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISCV_ESP32C3_COMMON_INCLUDE_ESP32C3_BOARD_BMP180_H */ diff --git a/boards/risc-v/esp32c3/common/include/esp32c3_board_ledc.h b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_ledc.h similarity index 97% rename from boards/risc-v/esp32c3/common/include/esp32c3_board_ledc.h rename to boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_ledc.h index adfb93f052b85..8bcc0b4cc299f 100644 --- a/boards/risc-v/esp32c3/common/include/esp32c3_board_ledc.h +++ b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_ledc.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/include/esp32c3_board_ledc.h + * boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_ledc.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/include/esp32c3_board_mpu60x0_i2c.h b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_mpu60x0_i2c.h similarity index 97% rename from boards/risc-v/esp32c3/common/include/esp32c3_board_mpu60x0_i2c.h rename to boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_mpu60x0_i2c.h index ff7059bf4a7c5..b4a812a947d0c 100644 --- a/boards/risc-v/esp32c3/common/include/esp32c3_board_mpu60x0_i2c.h +++ b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_mpu60x0_i2c.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/include/esp32c3_board_mpu60x0_i2c.h + * boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_mpu60x0_i2c.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/include/esp32c3_board_oneshot.h b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_oneshot.h similarity index 97% rename from boards/risc-v/esp32c3/common/include/esp32c3_board_oneshot.h rename to boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_oneshot.h index 8722b9e978b79..1260f71096f60 100644 --- a/boards/risc-v/esp32c3/common/include/esp32c3_board_oneshot.h +++ b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_oneshot.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/include/esp32c3_board_oneshot.h + * boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_oneshot.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/include/esp32c3_board_spidev.h b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_spidev.h similarity index 97% rename from boards/risc-v/esp32c3/common/include/esp32c3_board_spidev.h rename to boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_spidev.h index d015b224c0519..0b9318d3cd0dc 100644 --- a/boards/risc-v/esp32c3/common/include/esp32c3_board_spidev.h +++ b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_spidev.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/include/esp32c3_board_spidev.h + * boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_spidev.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/include/esp32c3_board_spiflash.h b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_spiflash.h similarity index 97% rename from boards/risc-v/esp32c3/common/include/esp32c3_board_spiflash.h rename to boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_spiflash.h index 4229983b708ae..d95fe68772ef9 100644 --- a/boards/risc-v/esp32c3/common/include/esp32c3_board_spiflash.h +++ b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_spiflash.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/include/esp32c3_board_spiflash.h + * boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_spiflash.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/include/esp32c3_board_spislavedev.h b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_spislavedev.h similarity index 97% rename from boards/risc-v/esp32c3/common/include/esp32c3_board_spislavedev.h rename to boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_spislavedev.h index b98f4b034ff04..7dadf594a6780 100644 --- a/boards/risc-v/esp32c3/common/include/esp32c3_board_spislavedev.h +++ b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_spislavedev.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/include/esp32c3_board_spislavedev.h + * boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_spislavedev.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/include/esp32c3_board_twai.h b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_twai.h similarity index 97% rename from boards/risc-v/esp32c3/common/include/esp32c3_board_twai.h rename to boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_twai.h index 57b5b1f9428cb..7f94acf584d85 100644 --- a/boards/risc-v/esp32c3/common/include/esp32c3_board_twai.h +++ b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_twai.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/include/esp32c3_board_twai.h + * boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_twai.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/include/esp32c3_board_wdt.h b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_wdt.h similarity index 97% rename from boards/risc-v/esp32c3/common/include/esp32c3_board_wdt.h rename to boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_wdt.h index df7e89a071a5a..be072878bc4e3 100644 --- a/boards/risc-v/esp32c3/common/include/esp32c3_board_wdt.h +++ b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_wdt.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/include/esp32c3_board_wdt.h + * boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_wdt.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/include/esp32c3_board_wlan.h b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_wlan.h similarity index 97% rename from boards/risc-v/esp32c3/common/include/esp32c3_board_wlan.h rename to boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_wlan.h index fdca410a6aaf3..493c31139ec19 100644 --- a/boards/risc-v/esp32c3/common/include/esp32c3_board_wlan.h +++ b/boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_wlan.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/include/esp32c3_board_wlan.h + * boards/risc-v/esp32c3-legacy/common/include/esp32c3_board_wlan.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3-legacy/common/kernel/Makefile b/boards/risc-v/esp32c3-legacy/common/kernel/Makefile new file mode 100644 index 0000000000000..340b2d8790d8c --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/common/kernel/Makefile @@ -0,0 +1,102 @@ +############################################################################ +# boards/risc-v/esp32c3-legacy/common/kernel/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +# The entry point name (if none is provided in the .config file) + +CONFIG_INIT_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) +USER_LDSCRIPT = $(call CONVERT_PATH,$(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)protected_memory.ld) +USER_LDSCRIPT += $(call CONVERT_PATH,$(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)user-space.ld) +USER_LDSCRIPT += $(call CONVERT_PATH,$(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32c3_rom.ld) +USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) +USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) + +USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(addprefix -T,$(addsuffix .tmp,$(USER_LDSCRIPT))) -melf32lriscv + +ifeq ($(CONFIG_DEBUG_LINK_MAP),y) +USER_LDFLAGS += --cref -Map="$(TOPDIR)$(DELIM)User.map" +endif + +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = esp32c3_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +ifeq ($(LD),$(CC)) + LDSTARTGROUP ?= -Wl,--start-group + LDENDGROUP ?= -Wl,--end-group + USER_LDFLAGS := $(addprefix -Xlinker ,$(USER_LDFLAGS)) + USER_LDFLAGS += $(CFLAGS) +else + LDSTARTGROUP ?= --start-group + LDENDGROUP ?= --end-group +endif + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +$(addsuffix .tmp,$(USER_LDSCRIPT)): $(USER_LDSCRIPT) + $(call PREPROCESS,$(patsubst %.tmp,%,$@),$@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) $(addsuffix .tmp,$(USER_LDSCRIPT)) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) $(LDSTARTGROUP) $(USER_LDLIBS) $(LDENDGROUP) $(USER_LIBGCC) + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + $(Q) echo "LD: nuttx_user.elf" + $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf +ifeq ($(CONFIG_INTELHEX_BINARY),y) + $(Q) echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + $(Q) echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) +endif + $(Q) $(call DELFILE,$(addsuffix .tmp,$(USER_LDSCRIPT))) + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/boards/risc-v/esp32c3-legacy/common/kernel/esp32c3_userspace.c b/boards/risc-v/esp32c3-legacy/common/kernel/esp32c3_userspace.c new file mode 100644 index 0000000000000..bb1b9148606fc --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/common/kernel/esp32c3_userspace.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/common/kernel/esp32c3_userspace.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by the linker script. */ + +extern uint8_t _stext[]; /* Start of .text */ +extern uint8_t _etext[]; /* End_1 of .text + .rodata */ +extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ +extern uint8_t _sdata[]; /* Start of .data */ +extern uint8_t _edata[]; /* End+1 of .data */ +extern uint8_t _sbss[]; /* Start of .bss */ +extern uint8_t _ebss[]; /* End+1 of .bss */ + +extern uint8_t __ld_udram_end[]; /* End+1 of user ram section */ + +const struct userspace_s userspace locate_data(".userspace") = +{ + /* General memory map */ + + .us_entrypoint = CONFIG_INIT_ENTRYPOINT, + .us_textstart = (uintptr_t)_stext, + .us_textend = (uintptr_t)_etext, + .us_datasource = (uintptr_t)_eronly, + .us_datastart = (uintptr_t)_sdata, + .us_dataend = (uintptr_t)_edata, + .us_bssstart = (uintptr_t)_sbss, + .us_bssend = (uintptr_t)_ebss, + + .us_heapend = (uintptr_t)__ld_udram_end, + + /* Memory manager heap structure */ + + .us_heap = &g_mmheap, + + /* Task/thread startup routines */ + + .task_startup = nxtask_startup, + + /* Signal handler trampoline */ + + .signal_handler = up_signal_handler, + + /* Userspace work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIBC_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/risc-v/espressif/common/scripts/.gitignore b/boards/risc-v/esp32c3-legacy/common/scripts/.gitignore similarity index 100% rename from boards/risc-v/espressif/common/scripts/.gitignore rename to boards/risc-v/esp32c3-legacy/common/scripts/.gitignore diff --git a/boards/risc-v/espressif/common/scripts/esp32c3_aliases.ld b/boards/risc-v/esp32c3-legacy/common/scripts/esp32c3_aliases.ld similarity index 79% rename from boards/risc-v/espressif/common/scripts/esp32c3_aliases.ld rename to boards/risc-v/esp32c3-legacy/common/scripts/esp32c3_aliases.ld index b9d9d90c673d2..44c1b84b6ba76 100644 --- a/boards/risc-v/espressif/common/scripts/esp32c3_aliases.ld +++ b/boards/risc-v/esp32c3-legacy/common/scripts/esp32c3_aliases.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/espressif/common/scripts/esp32c3_aliases.ld + * boards/risc-v/esp32c3-legacy/common/scripts/esp32c3_aliases.ld * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,13 +18,7 @@ * ****************************************************************************/ -cache_dbus_mmu_set = Cache_Dbus_MMU_Set; -cache_ibus_mmu_set = Cache_Ibus_MMU_Set; -cache_invalidate_icache_all = Cache_Invalidate_ICache_All; -cache_resume_icache = Cache_Resume_ICache; -cache_suspend_icache = Cache_Suspend_ICache; - -#ifdef CONFIG_ESPRESSIF_BLE +#ifdef CONFIG_ESP32C3_BLE /* Lower-case aliases for BLE library symbols not compliant to nxstyle */ diff --git a/boards/risc-v/esp32c3/common/scripts/esp32c3_rom.ld b/boards/risc-v/esp32c3-legacy/common/scripts/esp32c3_rom.ld similarity index 99% rename from boards/risc-v/esp32c3/common/scripts/esp32c3_rom.ld rename to boards/risc-v/esp32c3-legacy/common/scripts/esp32c3_rom.ld index a14a6e5ff0b91..8efd515925c90 100644 --- a/boards/risc-v/esp32c3/common/scripts/esp32c3_rom.ld +++ b/boards/risc-v/esp32c3-legacy/common/scripts/esp32c3_rom.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/scripts/esp32c3_rom.ld + * boards/risc-v/esp32c3-legacy/common/scripts/esp32c3_rom.ld * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3-legacy/common/scripts/flat_memory.ld b/boards/risc-v/esp32c3-legacy/common/scripts/flat_memory.ld new file mode 100644 index 0000000000000..f173923446d26 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/common/scripts/flat_memory.ld @@ -0,0 +1,151 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/common/scripts/flat_memory.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * ESP32-C3 Linker Script Memory Layout + * + * This file describes the memory layout (memory blocks) as virtual + * memory addresses. + * + * _sections.ld contains output sections to link compiler + * output into these memory blocks. + * + ****************************************************************************/ + +#include + +#include "esp32c3_aliases.ld" + +#define SRAM_IRAM_START 0x4037c000 +#define SRAM_DRAM_START 0x3fc7c000 + +/* ICache size is fixed to 16KB on ESP32-C3 */ + +#define ICACHE_SIZE 0x4000 +#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) + +/* 2nd stage bootloader iram_loader_seg start address */ + +#define SRAM_DRAM_END (0x403ce710 - I_D_SRAM_OFFSET) + +#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE) +#define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE) + +#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_ORG) + +#ifdef CONFIG_ESP32C3_FLASH_2M +# define FLASH_SIZE 0x200000 +#elif defined (CONFIG_ESP32C3_FLASH_4M) +# define FLASH_SIZE 0x400000 +#elif defined (CONFIG_ESP32C3_FLASH_8M) +# define FLASH_SIZE 0x800000 +#elif defined (CONFIG_ESP32C3_FLASH_16M) +# define FLASH_SIZE 0x1000000 +#endif + +MEMORY +{ +#ifdef CONFIG_ESP32C3_APP_FORMAT_MCUBOOT + /* The origin values for "metadata" and "ROM" memory regions are the actual + * load addresses. + * + * NOTE: The memory region starting from 0x0 with length represented by + * CONFIG_ESP32C3_APP_MCUBOOT_HEADER_SIZE is reserved for the MCUboot header, + * which will be prepended to the binary file by the "imgtool" during the + * signing of firmware image. + */ + + metadata (RX) : org = CONFIG_ESP32C3_APP_MCUBOOT_HEADER_SIZE, len = 0x20 + ROM (RX) : org = ORIGIN(metadata) + LENGTH(metadata), + len = FLASH_SIZE - ORIGIN(ROM) +#endif + + /* Below values assume the flash cache is on, and have the blocks this + * uses subtracted from the length of the various regions. The 'data access + * port' dram/drom regions map to the same iram/irom regions but are + * connected to the data port of the CPU and e.g. allow bytewise access. + */ + + iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE + + /* Flash mapped instruction data. */ + +#ifdef CONFIG_ESP32C3_APP_FORMAT_MCUBOOT + irom0_0_seg (RX) : org = 0x42000000, len = FLASH_SIZE +#else + /* The 0x20 offset is a convenience for the app binary image generation. + * Flash cache has 64KB pages. The .bin file which is flashed to the chip + * has a 0x18 byte file header, and each segment has a 0x08 byte segment + * header. Setting this offset makes it simple to meet the flash cache MMU's + * constraint that (paddr % 64KB == vaddr % 64KB). + */ + + irom0_0_seg (RX) : org = 0x42000020, len = FLASH_SIZE - 0x20 +#endif + + /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. */ + + dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = I_D_SRAM_SIZE + + /* Flash mapped constant data */ + +#ifdef CONFIG_ESP32C3_APP_FORMAT_MCUBOOT + /* The DROM segment origin is offset by 0x40 for mirroring the actual ROM + * image layout: + * 0x0 - 0x1F : MCUboot header + * 0x20 - 0x3F : Application image metadata section + * 0x40 onwards: ROM code and data + * This is required to meet the following constraint from the external + * flash MMU: + * VMA % 64KB == LMA % 64KB + * i.e. the lower 16 bits of both the virtual address (address seen by the + * CPU) and the load address (physical address of the external flash) must + * be equal. + */ + + drom0_0_seg (R) : org = 0x3c000000 + ORIGIN(ROM), + len = FLASH_SIZE - ORIGIN(ROM) +#else + /* The 0x20 offset is a convenience for the app binary image generation. + * Flash cache has 64KB pages. The .bin file which is flashed to the chip + * has a 0x18 byte file header, and each segment has a 0x08 byte segment + * header. Setting this offset makes it simple to meet the flash cache MMU's + * constraint that (paddr % 64KB == vaddr % 64KB). + */ + + drom0_0_seg (R) : org = 0x3c000020, len = FLASH_SIZE - 0x20 +#endif + + /* RTC fast memory. Persists over deep sleep. */ + + rtc_seg(RWX) : org = 0x50000000, len = 0x2000 +} + +#if CONFIG_ESP32C3_DEVKIT_RUN_IRAM + REGION_ALIAS("default_rodata_seg", dram0_0_seg); + REGION_ALIAS("default_code_seg", iram0_0_seg); +#else + REGION_ALIAS("default_rodata_seg", drom0_0_seg); + REGION_ALIAS("default_code_seg", irom0_0_seg); +#endif /* CONFIG_ESP32C3_DEVKIT_RUN_IRAM */ + +/* Mark the end of the RTC heap (top of the RTC region) */ + +_ertcheap = 0x50001fff; diff --git a/boards/risc-v/esp32c3-legacy/common/scripts/kernel-space.ld b/boards/risc-v/esp32c3-legacy/common/scripts/kernel-space.ld new file mode 100644 index 0000000000000..7a27c208eb57f --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/common/scripts/kernel-space.ld @@ -0,0 +1,226 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/common/scripts/kernel-space.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Provide these so there is no need for using config files for this */ + +__uirom_start = ORIGIN(UIROM); +__uirom_size = LENGTH(UIROM); +__uirom_end = ORIGIN(UIROM) + LENGTH(UIROM); +__udrom_start = ORIGIN(UDROM); +__udrom_size = LENGTH(UDROM); +__udrom_end = ORIGIN(UDROM) + LENGTH(UDROM); +__uiram_start = ORIGIN(UIRAM); +__uiram_size = LENGTH(UIRAM); +__uiram_end = ORIGIN(UIRAM) + LENGTH(UIRAM); +__udram_start = ORIGIN(UDRAM); +__udram_size = LENGTH(UDRAM); +__udram_end = ORIGIN(UDRAM) + LENGTH(UDRAM); + +/* Provide the kernel boundaries as well */ + +__kirom_start = ORIGIN(KIROM); +__kirom_size = LENGTH(KIROM); +__kdrom_start = ORIGIN(KDROM); +__kdrom_size = LENGTH(KDROM); +__kiram_start = ORIGIN(KIRAM); +__kiram_size = LENGTH(KIRAM); +__kiram_end = ORIGIN(KIRAM) + LENGTH(KIRAM); +__kdram_start = ORIGIN(KDRAM); +__kdram_size = LENGTH(KDRAM); +__kdram_end = ORIGIN(KDRAM) + LENGTH(KDRAM); + +ENTRY(_stext) + +SECTIONS +{ + .iram0.text : + { + _iram_start = ABSOLUTE(.); + + __vectors_start = ABSOLUTE(.); + + /* Vectors go to start of IRAM */ + + KEEP(*(.exception_vectors.text)); + . = ALIGN(4); + + __vectors_end = ABSOLUTE(.); + + *(.iram1) + *(.iram1.*) + + *libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*) + + *(.wifi0iram .wifi0iram.*) + *(.wifirxiram .wifirxiram.*) + *(.wifislpiram .wifislpiram.*) + *(.wifislprxiram .wifislprxiram.*) + + _iram_end = ABSOLUTE(.); + } >KIRAM + + /* This section is required to skip .iram0.text area because iram0_0_seg + * and dram0_0_seg reflect the same address space on different buses. + */ + + .dram0.dummy (NOLOAD): + { + . = ORIGIN(KDRAM) + _iram_end - _iram_start; + } >KDRAM + + .noinit (NOLOAD): + { + /* This section contains data that is not initialized during load, + * or during the application's initialization sequence. + */ + + *(.noinit) + *(.noinit.*) + } >KDRAM + + .dram0.data : + { + _sdata = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + __global_pointer$ = . + 0x800; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + *(.dram1) + *(.dram1.*) + . = ALIGN(4); + _edata = ABSOLUTE(.); + } >KDRAM + + /* Shared RAM */ + + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + + . = ALIGN (32); + _ebss = ABSOLUTE(.); + } >KDRAM + + .flash.text : + { + _stext = .; + + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + + _flash_cache_start = ABSOLUTE(0); + } >KIROM + + .flash_rodata_dummy (NOLOAD): + { + . = ALIGN(ALIGNOF(.flash.text)); + . = . + SIZEOF(.flash.text); + . = ALIGN(0x10000) + 0x20; + } >KDROM + + .flash.rodata : ALIGN(0x10) + { + _srodata = ABSOLUTE(.); + + *(.rodata) + *(.rodata.*) + + *(.srodata.*) + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ constructor and destructor tables: + * RISC-V GCC is configured with --enable-initfini-array so it emits an + * .init_array section instead. + */ + + _sinit = ABSOLUTE(.); + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)) + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array)) + _einit = ABSOLUTE(.); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + + /* C++ exception handlers table: */ + + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _erodata = ABSOLUTE(.); + + /* Literals are also RO data. */ + + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + } >KDROM +} diff --git a/boards/risc-v/esp32c3-legacy/common/scripts/legacy_sections.ld b/boards/risc-v/esp32c3-legacy/common/scripts/legacy_sections.ld new file mode 100644 index 0000000000000..9d4c615d93fc2 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/common/scripts/legacy_sections.ld @@ -0,0 +1,256 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/common/scripts/legacy_sections.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Default entry point: */ + +ENTRY(__start); + +SECTIONS +{ + .iram0.text : + { + _iram_start = ABSOLUTE(.); + + /* Vectors go to start of IRAM */ + + KEEP(*(.exception_vectors.text)); + . = ALIGN(4); + + *(.iram1) + *(.iram1.*) + + *libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*) + + *(.wifi0iram .wifi0iram.*) + *(.wifirxiram .wifirxiram.*) + *(.wifislpiram .wifislpiram.*) + *(.wifislprxiram .wifislprxiram.*) + + } >iram0_0_seg + + /* This section is required to skip .iram0.text area because iram0_0_seg + * and dram0_0_seg reflect the same address space on different buses. + */ + + .dram0.dummy (NOLOAD): + { + . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; + } >dram0_0_seg + + .noinit (NOLOAD): + { + /* This section contains data that is not initialized during load, + * or during the application's initialization sequence. + */ + + *(.noinit) + *(.noinit.*) + } >dram0_0_seg + + .dram0.data : + { + _sdata = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + __global_pointer$ = . + 0x800; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + *(.dram1) + *(.dram1.*) + . = ALIGN(4); + _edata = ABSOLUTE(.); + } >dram0_0_seg + + /* Shared RAM */ + + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + + . = ALIGN (32); + _ebss = ABSOLUTE(.); + } >dram0_0_seg + + .flash.text : + { + _stext = .; + + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + + _flash_cache_start = ABSOLUTE(0); + } >default_code_seg + + .flash_rodata_dummy (NOLOAD): + { + . = SIZEOF(.flash.text); + . = ALIGN(0x10000) + 0x20; + } >drom0_0_seg + + .flash.rodata : ALIGN(0x10) + { + _srodata = ABSOLUTE(.); + + *(.rodata) + *(.rodata.*) + + *(.srodata.*) + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ constructor and destructor tables: + * RISC-V GCC is configured with --enable-initfini-array so it emits an + * .init_array section instead. + */ + + _sinit = ABSOLUTE(.); + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)) + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array)) + _einit = ABSOLUTE(.); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + + /* C++ exception handlers table: */ + + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _erodata = ABSOLUTE(.); + + /* Literals are also RO data. */ + + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + } >default_rodata_seg + + /* Marks the end of IRAM code segment */ + + .iram0.text_end (NOLOAD) : + { + . = ALIGN (16); + } >iram0_0_seg + + .iram0.data : + { + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + } >iram0_0_seg + + .iram0.bss (NOLOAD) : + { + . = ALIGN(16); + *(.iram.bss) + *(.iram.bss*) + + . = ALIGN(16); + _iram_end = ABSOLUTE(.); + } >iram0_0_seg + + /* RTC fast memory holds RTC wake stub code !*/ + + .rtc.text : + { + . = ALIGN(4); + *(.rtc.literal .rtc.text) + } >rtc_seg + + /* This section is required to skip rtc.text area because the text and + * data segments reflect the same address space on different buses. + */ + + .rtc.dummy : + { + . = SIZEOF(.rtc.text); + } >rtc_seg + + /* RTC BSS section. */ + + .rtc.bss (NOLOAD) : + { + *(.rtc.bss) + } >rtc_seg + + /* RTC data section holds RTC wake stub data/rodata. */ + + .rtc.data : + { + *(.rtc.data) + *(.rtc.rodata) + + /* Whatever is left from the RTC memory is used as a special heap. */ + + _srtcheap = ABSOLUTE(.); + + } >rtc_seg +} + diff --git a/boards/risc-v/esp32c3/common/scripts/mcuboot_sections.ld b/boards/risc-v/esp32c3-legacy/common/scripts/mcuboot_sections.ld similarity index 98% rename from boards/risc-v/esp32c3/common/scripts/mcuboot_sections.ld rename to boards/risc-v/esp32c3-legacy/common/scripts/mcuboot_sections.ld index 39f9666b9622d..87049498d076a 100644 --- a/boards/risc-v/esp32c3/common/scripts/mcuboot_sections.ld +++ b/boards/risc-v/esp32c3-legacy/common/scripts/mcuboot_sections.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/scripts/mcuboot_sections.ld + * boards/risc-v/esp32c3-legacy/common/scripts/mcuboot_sections.ld * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -144,32 +144,6 @@ SECTIONS . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; } >dram0_0_seg - /* Shared RAM */ - - .dram0.bss (NOLOAD) : - { - /* .bss initialized on power-up */ - - . = ALIGN (8); - _sbss = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - KEEP (*(.bss)) - *(.bss.*) - *(.share.mem) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } >dram0_0_seg - .noinit (NOLOAD): { /* This section contains data that is not initialized during load, @@ -205,11 +179,33 @@ SECTIONS esp32c3_start.*(.rodata .rodata.*) _edata = ABSOLUTE(.); . = ALIGN(4); + } >dram0_0_seg AT>ROM - /* Heap starts at the end of .data */ + /* Shared RAM */ - _sheap = ABSOLUTE(.); - } >dram0_0_seg AT>ROM + .dram0.bss (NOLOAD) : + { + /* .bss initialized on power-up */ + + . = ALIGN (8); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + KEEP (*(.bss)) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(8); + _ebss = ABSOLUTE(.); + } >dram0_0_seg /* Marks the end of IRAM code segment */ diff --git a/boards/risc-v/esp32c3/common/scripts/protected_memory.ld b/boards/risc-v/esp32c3-legacy/common/scripts/protected_memory.ld similarity index 98% rename from boards/risc-v/esp32c3/common/scripts/protected_memory.ld rename to boards/risc-v/esp32c3-legacy/common/scripts/protected_memory.ld index a0ec6dd626f3a..75872dea8403d 100644 --- a/boards/risc-v/esp32c3/common/scripts/protected_memory.ld +++ b/boards/risc-v/esp32c3-legacy/common/scripts/protected_memory.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/scripts/protected_memory.ld + * boards/risc-v/esp32c3-legacy/common/scripts/protected_memory.ld * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3-legacy/common/scripts/user-space.ld b/boards/risc-v/esp32c3-legacy/common/scripts/user-space.ld new file mode 100644 index 0000000000000..f90bbc2961b91 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/common/scripts/user-space.ld @@ -0,0 +1,221 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/common/scripts/user-space.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +SECTIONS +{ + .metadata : + { + /* DROM metadata: + * - Destination address (VMA) for DROM region + * - Flash offset (LMA) for start of DROM region + * - Size of DROM region + */ + + LONG(ADDR(.userspace)) + LONG(LOADADDR(.userspace)) + LONG(SIZEOF(.userspace) + SIZEOF(.rodata)) + + /* IROM metadata: + * - Destination address (VMA) for IROM region + * - Flash offset (LMA) for start of IROM region + * - Size of IROM region + */ + + LONG(ADDR(.text)) + LONG(LOADADDR(.text)) + LONG(SIZEOF(.text)) + } >metadata + + /* section info */ + + __ld_uirom_start = ORIGIN(UIROM); + __ld_uirom_size = LENGTH(UIROM); + __ld_uirom_end = ORIGIN(UIROM) + LENGTH(UIROM); + __ld_udrom_start = ORIGIN(UDROM); + __ld_udrom_size = LENGTH(UDROM); + __ld_udrom_end = ORIGIN(UDROM) + LENGTH(UDROM); + __ld_uiram_start = ORIGIN(UIRAM); + __ld_uiram_size = LENGTH(UIRAM); + __ld_uiram_end = ORIGIN(UIRAM) + LENGTH(UIRAM); + __ld_udram_start = ORIGIN(UDRAM); + __ld_udram_size = LENGTH(UDRAM); + __ld_udram_end = ORIGIN(UDRAM) + LENGTH(UDRAM); + + _eronly = LOADADDR(.data); + + .userspace : { + *(.userspace) + } >UDROM AT>ROM + + /* Output sections for the Userspace image are given standard names, so + * instead of the Espressif-usual ".flash.text" we name it as ".text". + * The motivation is to ease debugging with GDB when loading symbols from + * both Kernel and User images since GDB's "add-symbol-file" command + * expects to find a .text section at the provided offset. + */ + + .rodata : + { + _srodata = ABSOLUTE(.); + + *(.rodata) + *(.rodata.*) + + *(.srodata.*) + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ constructor and destructor tables: + * RISC-V GCC is configured with --enable-initfini-array so it emits an + * .init_array section instead. + */ + + _sinit = ABSOLUTE(.); + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)) + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array)) + _einit = ABSOLUTE(.); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + + /* C++ exception handlers table: */ + + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _erodata = ABSOLUTE(.); + + /* Literals are also RO data. */ + + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + } >UDROM AT>ROM + + .iram0.text : + { + _iram_start = ABSOLUTE(.); + + *(.iram1) + *(.iram1.*) + + _iram_end = ABSOLUTE(.); + } >UIRAM AT>ROM + + /* This section is required to skip .iram0.text area because iram0_0_seg + * and dram0_0_seg reflect the same address space on different buses. + */ + + .dram0.dummy (NOLOAD): + { + . = ORIGIN(UDRAM) + _iram_end - _iram_start; + } >UDRAM + + .noinit (NOLOAD): + { + /* This section contains data that is not initialized during load, + * or during the application's initialization sequence. + */ + + *(.noinit) + *(.noinit.*) + } >UDRAM + + .data : + { + _sdata = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + *(.dram1) + *(.dram1.*) + . = ALIGN(4); + _edata = ABSOLUTE(.); + } >UDRAM AT>ROM + + /* Shared RAM */ + + .bss (NOLOAD) : + { + . = ALIGN (8); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + + . = ALIGN (32); + _ebss = ABSOLUTE(.); + } >UDRAM + + .flash_text_dummy (NOLOAD) : ALIGN(0x00010000) + { + . = SIZEOF(.userspace) + SIZEOF(.rodata); + } >UIROM + + .text : ALIGN(0x00010000) + { + _stext = .; + + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + _etext = .; + } >UIROM AT>ROM +} diff --git a/boards/risc-v/esp32c3-legacy/common/src/Make.defs b/boards/risc-v/esp32c3-legacy/common/src/Make.defs new file mode 100644 index 0000000000000..1c1720e25a8b6 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/common/src/Make.defs @@ -0,0 +1,103 @@ +############################################################################# +# boards/risc-v/esp32c3-legacy/common/src/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +ifeq ($(CONFIG_ARCH_BOARD_COMMON),y) + +ifeq ($(CONFIG_ESP32C3_SPI),y) + CSRCS += esp32c3_board_spi.c +endif + +ifeq ($(CONFIG_SPI_DRIVER),y) + CSRCS += esp32c3_board_spidev.c +endif + +ifeq ($(CONFIG_SPI_SLAVE_DRIVER),y) + CSRCS += esp32c3_board_spislavedev.c +endif + +ifeq ($(CONFIG_ESP32C3_SPIFLASH),y) + CSRCS += esp32c3_board_spiflash.c +endif + +ifeq ($(CONFIG_I2C_DRIVER),y) + CSRCS += esp32c3_board_i2c.c +endif + +ifeq ($(CONFIG_ESP32C3_WIRELESS),y) + CSRCS += esp32c3_board_wlan.c +endif + +ifeq ($(CONFIG_CAN),y) + CSRCS += esp32c3_board_twai.c +endif + +ifeq ($(CONFIG_WATCHDOG),y) + CSRCS += esp32c3_board_wdt.c +endif + +ifeq ($(CONFIG_ONESHOT),y) + CSRCS += esp32c3_board_oneshot.c +endif + +ifeq ($(CONFIG_PWM),y) + CSRCS += esp32c3_board_ledc.c +endif + +ifeq ($(CONFIG_ADC),y) + CSRCS += esp32c3_board_adc.c +endif + +ifeq ($(CONFIG_SENSORS_BMP180),y) + CSRCS += esp32c3_board_bmp180.c +endif + +ifeq ($(CONFIG_LCD_ST7735),y) + CSRCS += esp32c3_board_st7735.c +endif + +ifeq ($(CONFIG_LCD_ST7789),y) + CSRCS += esp32c3_board_st7789.c +endif + +ifeq ($(CONFIG_LCD_GC9A01),y) + CSRCS += esp32c3_board_gc9a01.c +endif + +ifeq ($(CONFIG_SENSORS_APDS9960),y) + CSRCS += esp32c3_board_apds9960.c +endif + +ifeq ($(CONFIG_LCD_APA102),y) + CSRCS += esp32c3_board_apa102.c +endif + +ifeq ($(CONFIG_MPU60X0_I2C),y) + CSRCS += esp32c3_board_mpu60x0_i2c.c +endif + +ifeq ($(CONFIG_SPI_ICE40),y) + CSRCS += esp32c3_board_ice40.c +endif + +DEPPATH += --dep-path src +VPATH += :src +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src + +endif diff --git a/boards/risc-v/esp32c3/common/src/esp32c3_board_adc.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_adc.c similarity index 98% rename from boards/risc-v/esp32c3/common/src/esp32c3_board_adc.c rename to boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_adc.c index 15c418eeda571..f5d4dddd4d3a9 100644 --- a/boards/risc-v/esp32c3/common/src/esp32c3_board_adc.c +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_adc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/src/esp32c3_board_adc.c + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_adc.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/src/esp32c3_board_apa102.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_apa102.c similarity index 98% rename from boards/risc-v/esp32c3/common/src/esp32c3_board_apa102.c rename to boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_apa102.c index afa4e7efad071..a900146c6af20 100644 --- a/boards/risc-v/esp32c3/common/src/esp32c3_board_apa102.c +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_apa102.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/src/esp32c3_board_apa102.c + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_apa102.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/src/esp32c3_board_apds9960.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_apds9960.c similarity index 98% rename from boards/risc-v/esp32c3/common/src/esp32c3_board_apds9960.c rename to boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_apds9960.c index fb34f345ab1bf..d013f868d5045 100644 --- a/boards/risc-v/esp32c3/common/src/esp32c3_board_apds9960.c +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_apds9960.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/src/esp32c3_board_apds9960.c + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_apds9960.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/src/esp32c3_board_bmp180.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_bmp180.c similarity index 97% rename from boards/risc-v/esp32c3/common/src/esp32c3_board_bmp180.c rename to boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_bmp180.c index 8acba5655d8c3..9f223bbac89ee 100644 --- a/boards/risc-v/esp32c3/common/src/esp32c3_board_bmp180.c +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_bmp180.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/src/esp32c3_board_bmp180.c + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_bmp180.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/src/esp32c3_board_gc9a01.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_gc9a01.c similarity index 98% rename from boards/risc-v/esp32c3/common/src/esp32c3_board_gc9a01.c rename to boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_gc9a01.c index 285620cfcd196..758adc0099179 100644 --- a/boards/risc-v/esp32c3/common/src/esp32c3_board_gc9a01.c +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_gc9a01.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/src/esp32c3_board_gc9a01.c + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_gc9a01.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/src/esp32c3_board_i2c.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_i2c.c similarity index 97% rename from boards/risc-v/esp32c3/common/src/esp32c3_board_i2c.c rename to boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_i2c.c index 6ad33d61ab59f..1d8b351d00ccf 100644 --- a/boards/risc-v/esp32c3/common/src/esp32c3_board_i2c.c +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_i2c.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/src/esp32c3_board_i2c.c + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_i2c.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_ice40.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_ice40.c new file mode 100644 index 0000000000000..f5e1ef1a0157a --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_ice40.c @@ -0,0 +1,82 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_ice40.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "nuttx/spi/ice40.h" + +#include "esp32c3_ice40.h" +#include "esp32c3_board_ice40.h" + +#include "esp32c3_gpio.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_ice40_setup + * + * Description: + * Initialize ICE40 FPGA GPIOs, SPI and register the ICE40 driver. + * + ****************************************************************************/ + +int esp32c3_ice40_setup(void) +{ + struct ice40_dev_s *ice40; + + /* Initialize ICE40 FPGA GPIOs and SPI interface */ + + ice40 = esp32c3_ice40_initialize(CONFIG_ESP32C3_ICE40_CDONEPIN, + CONFIG_ESP32C3_ICE40_CRSTPIN, + CONFIG_ESP32C3_ICE40_CSPIN, + CONFIG_ESP32C3_ICE40_SPI_PORT); + if (ice40 <= 0) + { + _err("ERROR: Failed to initialize ICE40 driver\n"); + return -ENODEV; + } + + /* Register the ICE40 FPGA device at "/dev/ice40-0" */ + + int ret = ice40_register("/dev/ice40-0", ice40); + if (ret < 0) + { + _err("ERROR: Failed to register ICE40 driver: %d\n", ret); + return ret; + } + + return OK; +} diff --git a/boards/risc-v/esp32c3/common/src/esp32c3_board_ledc.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_ledc.c similarity index 98% rename from boards/risc-v/esp32c3/common/src/esp32c3_board_ledc.c rename to boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_ledc.c index 835430b934dca..65f7c983be4a9 100644 --- a/boards/risc-v/esp32c3/common/src/esp32c3_board_ledc.c +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_ledc.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/src/esp32c3_board_ledc.c + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_ledc.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/src/esp32c3_board_mpu60x0_i2c.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_mpu60x0_i2c.c similarity index 97% rename from boards/risc-v/esp32c3/common/src/esp32c3_board_mpu60x0_i2c.c rename to boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_mpu60x0_i2c.c index a64e736255801..a321085c5d3a1 100644 --- a/boards/risc-v/esp32c3/common/src/esp32c3_board_mpu60x0_i2c.c +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_mpu60x0_i2c.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/src/esp32c3_board_mpu60x0_i2c.c + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_mpu60x0_i2c.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/src/esp32c3_board_oneshot.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_oneshot.c similarity index 97% rename from boards/risc-v/esp32c3/common/src/esp32c3_board_oneshot.c rename to boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_oneshot.c index ada850f682972..709bd6626985c 100644 --- a/boards/risc-v/esp32c3/common/src/esp32c3_board_oneshot.c +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_oneshot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/src/esp32c3_board_oneshot.c + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_oneshot.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/src/esp32c3_board_spi.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_spi.c similarity index 97% rename from boards/risc-v/esp32c3/common/src/esp32c3_board_spi.c rename to boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_spi.c index b29b822eefc77..3e54fdfbc4c04 100644 --- a/boards/risc-v/esp32c3/common/src/esp32c3_board_spi.c +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_spi.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/src/esp32c3_board_spi.c + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_spi.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/src/esp32c3_board_spidev.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_spidev.c similarity index 97% rename from boards/risc-v/esp32c3/common/src/esp32c3_board_spidev.c rename to boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_spidev.c index 834b72fdb852d..b858a6ad091f4 100644 --- a/boards/risc-v/esp32c3/common/src/esp32c3_board_spidev.c +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_spidev.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/src/esp32c3_board_spidev.c + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_spidev.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/src/esp32c3_board_spiflash.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_spiflash.c similarity index 99% rename from boards/risc-v/esp32c3/common/src/esp32c3_board_spiflash.c rename to boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_spiflash.c index 4b4a0ea9d2c98..9aecca8c1ae5d 100644 --- a/boards/risc-v/esp32c3/common/src/esp32c3_board_spiflash.c +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_spiflash.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/src/esp32c3_board_spiflash.c + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_spiflash.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/src/esp32c3_board_spislavedev.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_spislavedev.c similarity index 97% rename from boards/risc-v/esp32c3/common/src/esp32c3_board_spislavedev.c rename to boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_spislavedev.c index c6721661df0aa..199109c4bb244 100644 --- a/boards/risc-v/esp32c3/common/src/esp32c3_board_spislavedev.c +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_spislavedev.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/src/esp32c3_board_spislavedev.c + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_spislavedev.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/src/esp32c3_board_st7735.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_st7735.c similarity index 98% rename from boards/risc-v/esp32c3/common/src/esp32c3_board_st7735.c rename to boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_st7735.c index d2f40dad06eb9..9e8bc3f7cfce4 100644 --- a/boards/risc-v/esp32c3/common/src/esp32c3_board_st7735.c +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_st7735.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/src/esp32c3_board_st7735.c + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_st7735.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/src/esp32c3_board_st7789.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_st7789.c similarity index 98% rename from boards/risc-v/esp32c3/common/src/esp32c3_board_st7789.c rename to boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_st7789.c index 99c82855c75f5..8a53f5bb45353 100644 --- a/boards/risc-v/esp32c3/common/src/esp32c3_board_st7789.c +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_st7789.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/src/esp32c3_board_st7789.c + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_st7789.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/src/esp32c3_board_twai.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_twai.c similarity index 97% rename from boards/risc-v/esp32c3/common/src/esp32c3_board_twai.c rename to boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_twai.c index 2e80ab043ab08..62bf5b38539a9 100644 --- a/boards/risc-v/esp32c3/common/src/esp32c3_board_twai.c +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_twai.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/src/esp32c3_board_twai.c + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_twai.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/src/esp32c3_board_wdt.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_wdt.c similarity index 97% rename from boards/risc-v/esp32c3/common/src/esp32c3_board_wdt.c rename to boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_wdt.c index fead26bdb3027..ac82af01e8395 100644 --- a/boards/risc-v/esp32c3/common/src/esp32c3_board_wdt.c +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_wdt.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/src/esp32c3_board_wdt.c + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_wdt.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/common/src/esp32c3_board_wlan.c b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_wlan.c similarity index 97% rename from boards/risc-v/esp32c3/common/src/esp32c3_board_wlan.c rename to boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_wlan.c index 35b621eafbbbf..9a19fdf361a5c 100644 --- a/boards/risc-v/esp32c3/common/src/esp32c3_board_wlan.c +++ b/boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_wlan.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/common/src/esp32c3_board_wlan.c + * boards/risc-v/esp32c3-legacy/common/src/esp32c3_board_wlan.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/Kconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/Kconfig similarity index 100% rename from boards/risc-v/esp32c3/esp32c3-devkit-rust-1/Kconfig rename to boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/Kconfig diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/configs/brickmatch/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/configs/brickmatch/defconfig new file mode 100644 index 0000000000000..2dabaed38ffe9 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/configs/brickmatch/defconfig @@ -0,0 +1,71 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ESP32C3_UART0 is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit-rust-1" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT_RUST1=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3MINI1=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_I2C=y +CONFIG_DEBUG_I2C_ERROR=y +CONFIG_DEBUG_I2C_WARN=y +CONFIG_DEV_ZERO=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_ESP32C3_DMA=y +CONFIG_ESP32C3_GPIO_IRQ=y +CONFIG_ESP32C3_I2C0=y +CONFIG_ESP32C3_I2C0_SCLPIN=8 +CONFIG_ESP32C3_I2C0_SDAPIN=10 +CONFIG_ESP32C3_SPI2=y +CONFIG_ESP32C3_SPI2_CLKPIN=4 +CONFIG_ESP32C3_SPI2_CSPIN=0 +CONFIG_ESP32C3_SPI2_DMA=y +CONFIG_ESP32C3_SPI2_MISOPIN=6 +CONFIG_ESP32C3_SPI2_MOSIPIN=5 +CONFIG_ESP32C3_USBSERIAL=y +CONFIG_EXAMPLES_FB=y +CONFIG_FS_PROCFS=y +CONFIG_GAMES_BRICKMATCH=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_APA102=y +CONFIG_LCD_APA102_FREQUENCY=10000000 +CONFIG_LCD_DEV=y +CONFIG_LCD_FRAMEBUFFER=y +CONFIG_LCD_NOGETRUN=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_APDS9960=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_VIDEO_FB=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/configs/nsh/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/configs/nsh/defconfig new file mode 100644 index 0000000000000..867a40fd22e38 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/configs/nsh/defconfig @@ -0,0 +1,42 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ESP32C3_UART0 is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit-rust-1" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT_RUST1=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3MINI1=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_USBSERIAL=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/include/board.h b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/include/board.h new file mode 100644 index 0000000000000..a14d51ac10ad0 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/include/board.h @@ -0,0 +1,50 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_RUST1_INCLUDE_BOARD_H +#define __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_RUST1_INCLUDE_BOARD_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NUM_BUTTONS 1 + +#define LED_STARTED 0 /* ON */ +#define LED_HEAPALLOCATE 1 /* ON */ +#define LED_IRQSENABLED 2 /* N/A */ +#define LED_STACKCREATED 3 /* N/A */ +#define LED_INIRQ 4 /* N/A */ +#define LED_SIGNAL 5 /* N/A */ +#define LED_ASSERTION 6 /* N/A */ +#define LED_PANIC 7 /* Blinking */ +#define LED_CPU 8 /* N/A */ + +/* Clocking *****************************************************************/ + +#define BOARD_XTAL_FREQUENCY 40000000 + +/* GPIO pins used by the GPIO Subsystem */ + +#define BOARD_NGPIOOUT 2 /* Amount of GPIO Output pins */ +#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ + +#endif /* __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_RUST1_INCLUDE_BOARD_H */ + diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/include/board_memorymap.h b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/include/board_memorymap.h new file mode 100644 index 0000000000000..1cedff7271c27 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/include/board_memorymap.h @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/include/board_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_RUST1_INCLUDE_BOARD_MEMORYMAP_H +#define __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_RUST1_INCLUDE_BOARD_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Kernel ROM */ + +#define KIROM_START (uintptr_t)__kirom_start +#define KIROM_SIZE (uintptr_t)__kirom_size +#define KDROM_START (uintptr_t)__kdrom_start +#define KDROM_SIZE (uintptr_t)__kdrom_size + +/* Kernel RAM */ + +#define KIRAM_START (uintptr_t)__kiram_start +#define KIRAM_SIZE (uintptr_t)__kiram_size +#define KIRAM_END (uintptr_t)__kiram_end +#define KDRAM_START (uintptr_t)__kdram_start +#define KDRAM_SIZE (uintptr_t)__kdram_size +#define KDRAM_END (uintptr_t)__kdram_end + +/* Exception vectors */ + +#define VECTORS_START (uintptr_t)__vectors_start +#define VECTORS_END (uintptr_t)__vectors_end + +/* User ROM */ + +#define UIROM_START (uintptr_t)__uirom_start +#define UIROM_SIZE (uintptr_t)__uirom_size +#define UIROM_END (uintptr_t)__uirom_end +#define UDROM_START (uintptr_t)__udrom_start +#define UDROM_SIZE (uintptr_t)__udrom_size +#define UDROM_END (uintptr_t)__udrom_end + +/* User RAM */ + +#define UIRAM_START (uintptr_t)__uiram_start +#define UIRAM_SIZE (uintptr_t)__uiram_size +#define UIRAM_END (uintptr_t)__uiram_end +#define UDRAM_START (uintptr_t)__udram_start +#define UDRAM_SIZE (uintptr_t)__udram_size +#define UDRAM_END (uintptr_t)__udram_end + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Kernel ROM (RX) */ + +extern uint8_t __kirom_start[]; +extern uint8_t __kirom_size[]; +extern uint8_t __kdrom_start[]; +extern uint8_t __kdrom_size[]; + +/* Kernel RAM (RW) */ + +extern uint8_t __kiram_start[]; +extern uint8_t __kiram_size[]; +extern uint8_t __kiram_end[]; +extern uint8_t __kdram_start[]; +extern uint8_t __kdram_size[]; +extern uint8_t __kdram_end[]; + +/* Exception vectors */ + +extern uint8_t __vectors_start[]; +extern uint8_t __vectors_end[]; + +/* User ROM (RX) */ + +extern uint8_t __uirom_start[]; +extern uint8_t __uirom_size[]; +extern uint8_t __uirom_end[]; +extern uint8_t __udrom_start[]; +extern uint8_t __udrom_size[]; +extern uint8_t __udrom_end[]; + +/* User RAM (RW) */ + +extern uint8_t __uiram_start[]; +extern uint8_t __uiram_size[]; +extern uint8_t __uiram_end[]; +extern uint8_t __udram_start[]; +extern uint8_t __udram_size[]; +extern uint8_t __udram_end[]; + +#endif /* __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_RUST1_INCLUDE_BOARD_MEMORYMAP_H */ diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/scripts/Make.defs b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/scripts/Make.defs new file mode 100644 index 0000000000000..0ffdde4108b57 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/scripts/Make.defs @@ -0,0 +1,66 @@ +############################################################################ +# boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +########################################################################### + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/tools/esp32c3/Config.mk +include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs + +ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32c3_rom.ld + +# Pick the linker scripts from the board level if they exist, if not +# pick the common linker scripts. + +ifeq ($(CONFIG_BUILD_PROTECTED),y) + ARCHSCRIPT += $(call FINDSCRIPT,protected_memory.ld) + ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld) +else + ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) + + ifeq ($(CONFIG_ESP32C3_APP_FORMAT_MCUBOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) + else + ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) + endif +endif + +ARCHPICFLAGS = -fpic + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) + +LDMODULEFLAGS = -melf32lriscv -r -e module_initialize +LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld) + +# ELF module definitions + +CELFFLAGS = $(CFLAGS) +CXXELFFLAGS = $(CXXFLAGS) + +LDELFFLAGS = -melf32lriscv -r -e main +LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)$(DELIM)binfmt$(DELIM)libelf$(DELIM)gnu-elf.ld) diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/Make.defs b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/Make.defs new file mode 100644 index 0000000000000..ab11c05ed2e89 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/Make.defs @@ -0,0 +1,43 @@ +############################################################################# +# boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +CSRCS = esp32c3_boot.c esp32c3_bringup.c + +ifeq ($(CONFIG_BOARDCTL),y) + CSRCS += esp32c3_appinit.c + + ifeq ($(CONFIG_BOARDCTL_RESET),y) + CSRCS += esp32c3_reset.c + endif +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) + CSRCS += esp32c3_autoleds.c +endif + +ifeq ($(CONFIG_BOARDCTL_IOCTL),y) + CSRCS += esp32c3_ioctl.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3-devkit-rust-1.h b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3-devkit-rust-1.h similarity index 100% rename from boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3-devkit-rust-1.h rename to boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3-devkit-rust-1.h diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_appinit.c b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_appinit.c new file mode 100644 index 0000000000000..bef1068289bbb --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_appinit.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "esp32c3-devkit-rust-1.h" + +#ifdef CONFIG_BOARDCTL + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return esp32c3_bringup(); +#endif +} + +#endif /* CONFIG_BOARDCTL */ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_autoleds.c b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_autoleds.c similarity index 97% rename from boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_autoleds.c rename to boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_autoleds.c index 55c0c8e86ea3d..0e1acfd2df634 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_autoleds.c +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_autoleds.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_autoleds.c + * boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_autoleds.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_boot.c b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_boot.c new file mode 100644 index 0000000000000..33c8a5d4505a0 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_boot.c @@ -0,0 +1,87 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "riscv_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_board_initialize + * + * Description: + * All ESP32-C3 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void esp32c3_board_initialize(void) +{ +#ifdef CONFIG_ARCH_PERF_EVENTS + up_perf_init(NULL); +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + esp32c3_bringup(); +} +#endif diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_bringup.c b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_bringup.c new file mode 100644 index 0000000000000..ac8257210e816 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_bringup.c @@ -0,0 +1,168 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "esp32c3_wlan.h" +#include "esp32c3_spiflash.h" +#include "esp32c3_partition.h" +#include "esp32c3-devkit-rust-1.h" + +#include "esp32c3_rtc.h" +#ifdef CONFIG_ESP32C3_EFUSE +# include "esp32c3_efuse.h" +#endif + +#ifdef CONFIG_ESP32C3_SHA_ACCELERATOR +# include "esp32c3_sha.h" +#endif + +#ifdef CONFIG_RTC_DRIVER +# include "esp32c3_rtc_lowerhalf.h" +#endif + +#ifdef CONFIG_ESP32C3_BLE +# include "esp32c3_ble.h" +#endif + +#include "esp32c3_board_apds9960.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y + * Called from the NSH library + * + ****************************************************************************/ + +int esp32c3_bringup(void) +{ + int ret; + +#if defined(CONFIG_ESP32C3_EFUSE) + ret = esp32c3_efuse_initialize("/dev/efuse"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to init EFUSE: %d\n", ret); + } +#endif + +#if defined(CONFIG_ESP32C3_SHA_ACCELERATOR) && \ + !defined(CONFIG_CRYPTO_CRYPTODEV_HARDWARE) + ret = esp32c3_sha_init(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize SHA: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_TMPFS + /* Mount the tmpfs file system */ + + ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount tmpfs at %s: %d\n", + CONFIG_LIBC_TMPDIR, ret); + } +#endif + +#ifdef CONFIG_RTC_DRIVER + /* Instantiate the ESP32-C3 RTC driver */ + + ret = esp32c3_rtc_driverinit(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to Instantiate the RTC driver: %d\n", ret); + } +#endif + +#ifdef CONFIG_VIDEO_FB + /* Initialize and register the framebuffer driver */ + + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_APDS9960 + /* Register the APDS-9960 gesture sensor */ + + ret = board_apds9960_initialize(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_apds9960_initialize() failed: %d\n", + ret); + } +#endif + + /* If we got here then perhaps not all initialization was successful, but + * at least enough succeeded to bring-up NSH with perhaps reduced + * capabilities. + */ + + UNUSED(ret); + return OK; +} diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_ioctl.c b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_ioctl.c new file mode 100644 index 0000000000000..636b09cbe9104 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_ioctl.c @@ -0,0 +1,72 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_ioctl.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#ifdef CONFIG_BOARDCTL_IOCTL + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ioctl + * + * Description: + * The "landing site" for much of the boardctl() interface. Generic board- + * control functions invoked via ioctl() get routed through here. + * + * Since we don't do anything unusual at the moment, this function + * accomplishes nothing except avoid a missing-function linker error if + * CONFIG_BOARDCTL_IOCTL is selected. + * + * Input Parameters: + * cmd - IOCTL command being requested. + * arg - Arguments for the IOCTL. + * + * Returned Value: + * we don't yet support any boardctl IOCTLs. This function always returns + * -ENOTTY which is the standard IOCTL return value when a command is not + * supported + * + ****************************************************************************/ + +int board_ioctl(unsigned int cmd, uintptr_t arg) +{ + switch (cmd) + { + default: + return -ENOTTY; + } + + return OK; +} + +#endif /* CONFIG_BOARDCTL_IOCTL */ diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_reset.c b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_reset.c new file mode 100644 index 0000000000000..9d627271649f1 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_reset.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/esp32c3-devkit-rust-1/src/esp32c3_reset.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include "esp32c3_systemreset.h" + +#ifdef CONFIG_BOARDCTL_RESET + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value in this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ + syslog(LOG_INFO, "reboot status=%d\n", status); + + switch (status) + { + case EXIT_SUCCESS: + up_shutdown_handler(); + break; + case CONFIG_BOARD_ASSERT_RESET_VALUE: + break; + default: + break; + } + + up_systemreset(); + + return 0; +} + +#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/Kconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/Kconfig new file mode 100644 index 0000000000000..f55de8a3a62cb --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/Kconfig @@ -0,0 +1,60 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_ESP32C3_DEVKIT + +if PM + +config PM_ALARM_SEC + int "PM_STANDBY delay (seconds)" + default 15 + ---help--- + Number of seconds to wait in PM_STANDBY before going to PM_STANDBY mode. + +config PM_ALARM_NSEC + int "PM_STANDBY delay (nanoseconds)" + default 0 + ---help--- + Number of additional nanoseconds to wait in PM_STANDBY before going to PM_STANDBY mode. + +config PM_SLEEP_WAKEUP_SEC + int "PM_SLEEP delay (seconds)" + default 20 + ---help--- + Number of seconds to wait in PM_SLEEP. + +config PM_SLEEP_WAKEUP_NSEC + int "PM_SLEEP delay (nanoseconds)" + default 0 + ---help--- + Number of additional nanoseconds to wait in PM_SLEEP. + +endif # PM + +config ESP32C3_DEVKIT_RUN_IRAM + bool "Run from IRAM" + default n + +config ESP32C3_STORAGE_MTD_ENCRYPT + bool "Encrypt Storage MTD partition" + default y + depends on ESP32C3_SECURE_FLASH_ENC_ENABLED + +config ESP32C3_STORAGE_MTD_OFFSET + hex "Storage MTD base address in SPI Flash" + default 0x180000 if !ESP32C3_HAVE_OTA_PARTITION + default 0x250000 if ESP32C3_HAVE_OTA_PARTITION + depends on ESP32C3_MTD + ---help--- + MTD base address in SPI Flash. + +config ESP32C3_STORAGE_MTD_SIZE + hex "Storage MTD size in SPI Flash" + default 0x100000 + depends on ESP32C3_MTD + ---help--- + MTD size in SPI Flash. + +endif # ARCH_BOARD_ESP32C3_DEVKIT diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/adc/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/adc/defconfig new file mode 100644 index 0000000000000..ef808f2b18fd3 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/adc/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_ADC1=y +CONFIG_ESP32C3_ADC1_CHANNEL0=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_GROUPSIZE=1 +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/autopm/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/autopm/defconfig new file mode 100644 index 0000000000000..9ab50dead0734 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/autopm/defconfig @@ -0,0 +1,68 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_ESP32C3_AUTO_SLEEP=y +CONFIG_ESP32C3_WIFI=y +CONFIG_EXAMPLE_POWER_SAVE_MIN_MODEM=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_NAME_MAX=48 +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETINIT_DHCPC=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1514 +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_TCP=y +CONFIG_NET_UDP=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_DEFAULT=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TLS_TASK_NELEM=4 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y +CONFIG_WIRELESS_WAPI_STACKSIZE=4096 diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/ble/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/ble/defconfig new file mode 100644 index 0000000000000..425c8fe3ddb51 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/ble/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BTSAK=y +CONFIG_BUILTIN=y +CONFIG_DRIVERS_BLUETOOTH=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_ESP32C3_BLE=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NAME_MAX=48 +CONFIG_NETDEV_LATEINIT=y +CONFIG_NET_BLUETOOTH=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_TCP=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_DEFAULT=y +CONFIG_SPINLOCK=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_BLUETOOTH=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/bmp180/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/bmp180/defconfig new file mode 100644 index 0000000000000..a64d7e2a4d10a --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/bmp180/defconfig @@ -0,0 +1,46 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_I2C0=y +CONFIG_EXAMPLES_BMP180=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SENSORS=y +CONFIG_SENSORS_BMP180=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/coremark/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/coremark/defconfig new file mode 100644 index 0000000000000..235c755bdbd2d --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/coremark/defconfig @@ -0,0 +1,33 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NDEBUG is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_BENCHMARK_COREMARK=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_DEBUG_CUSTOMOPT=y +CONFIG_DEBUG_OPTLEVEL="-O3" +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_ENTRYPOINT="coremark_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/crypto/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/crypto/defconfig new file mode 100644 index 0000000000000..75b791c7db699 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/crypto/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_CRYPTO=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CRYPTODEV=y +CONFIG_CRYPTO_CRYPTODEV_HARDWARE=y +CONFIG_CRYPTO_RANDOM_POOL=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_AES_ACCELERATOR=y +CONFIG_ESP32C3_SHA_ACCELERATOR=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_CRYPTO=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/cxx/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/cxx/defconfig new file mode 100644 index 0000000000000..bee6917a4fcc7 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/cxx/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBCXX=y +CONFIG_LIBCXXABI=y +CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_CXXTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/efuse/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/efuse/defconfig new file mode 100644 index 0000000000000..f95e761e410cc --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/efuse/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MW is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_EFUSE=y +CONFIG_ESP32C3_EFUSE=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/elf/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/elf/defconfig new file mode 100644 index 0000000000000..733052ae6bd9b --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/elf/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=8192 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ELF=y +CONFIG_EXAMPLES_ELF=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLO_STACKSIZE=8192 +CONFIG_EXECFUNCS_HAVE_SYMTAB=y +CONFIG_EXECFUNCS_SYSTEM_SYMTAB=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_IDLETHREAD_STACKSIZE=8192 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=8192 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=8192 +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PTHREAD_STACK_DEFAULT=8192 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=20 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2020 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=12 +CONFIG_TLS_NELEM=4 +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/gdbstub/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/gdbstub/defconfig new file mode 100644 index 0000000000000..62864d769a7c2 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/gdbstub/defconfig @@ -0,0 +1,81 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_FLOAT_H=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_ESP32C3_SPIFLASH=y +CONFIG_ESP32C3_SPIFLASH_SPIFFS=y +CONFIG_ESP32C3_WIFI=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_NBUFFERS=124 +CONFIG_IOB_THROTTLE=24 +CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_LIB_GDBSTUB=y +CONFIG_NAME_MAX=48 +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETUTILS_CJSON=y +CONFIG_NETUTILS_IPERF=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1514 +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_DELAYED_ACK=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_WRITE_BUFFERS=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_DEFAULT=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_GDBSTUB=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TLS_TASK_NELEM=4 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y +CONFIG_WIRELESS_WAPI_INITCONF=y +CONFIG_WIRELESS_WAPI_STACKSIZE=4096 diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/gpio/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/gpio/defconfig new file mode 100644 index 0000000000000..53b6d882a0a20 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/gpio/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_GPIO=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_GPIO_IRQ=y +CONFIG_EXAMPLES_GPIO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=12 +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/knsh/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/knsh/defconfig new file mode 100644 index 0000000000000..e5d7ee023be47 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/knsh/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ESP32C3_REGION_PROTECTION is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_USE_MPU=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILD_PROTECTED=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_ZERO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_NUTTX_USERSPACE=0x3c080018 +CONFIG_PASS1_BUILDIR="boards/risc-v/esp32c3-legacy/common/kernel" +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/lvgl/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/lvgl/defconfig new file mode 100644 index 0000000000000..3a04fd941cdf6 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/lvgl/defconfig @@ -0,0 +1,62 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_LV_BUILD_EXAMPLES is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_SPI2=y +CONFIG_ESP32C3_SPI_SWCS=y +CONFIG_EXAMPLES_LVGLDEMO=y +CONFIG_FS_PROCFS=y +CONFIG_GRAPHICS_LVGL=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LCD=y +CONFIG_LCD_DEV=y +CONFIG_LCD_GC9A01=y +CONFIG_LCD_NOGETRUN=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LV_NUTTX_LCD_DOUBLE_BUFFER=y +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y +CONFIG_LV_USE_DEMO_WIDGETS=y +CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_LCD=y +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_MQ_MSGS=16 +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPI_CMDDATA=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/mcuboot_slot_confirm/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/mcuboot_slot_confirm/defconfig new file mode 100644 index 0000000000000..416e0e057cb01 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/mcuboot_slot_confirm/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_APP_FORMAT_MCUBOOT=y +CONFIG_ESP32C3_ESPTOOL_TARGET_SECONDARY=y +CONFIG_ESP32C3_SPIFLASH=y +CONFIG_EXAMPLES_MCUBOOT_SLOT_CONFIRM=y +CONFIG_FS_PROCFS=y +CONFIG_FS_SMARTFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_MTD_SMART=y +CONFIG_NAME_MAX=48 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_LOSMART=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SMARTFS_MAXNAMLEN=48 +CONFIG_START_DAY=10 +CONFIG_START_MONTH=9 +CONFIG_START_YEAR=2021 +CONFIG_SYSTEM_FLASH_ERASEALL=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_FSTEST=y +CONFIG_TESTING_FSTEST_MOUNTPT="/mnt" +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/module/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/module/defconfig new file mode 100644 index 0000000000000..651617ffc904f --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/module/defconfig @@ -0,0 +1,44 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_EXAMPLES_MODULE=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MODULE=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/nsh/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/nsh/defconfig new file mode 100644 index 0000000000000..6611a77b6e4bc --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/nsh/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_ZERO=y +CONFIG_FRAME_POINTER=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/nvcfgdata/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/nvcfgdata/defconfig new file mode 100644 index 0000000000000..7cfaebed438ce --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/nvcfgdata/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BCH=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_SPIFLASH=y +CONFIG_ESP32C3_SPIFLASH_MTD_CONFIG=y +CONFIG_ESP32C3_STORAGE_MTD_OFFSET=0x3e6000 +CONFIG_ESP32C3_STORAGE_MTD_SIZE=0x3000 +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_MTD_CONFIG=y +CONFIG_MTD_CONFIG_FAIL_SAFE=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_CFGDATA=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_MTD_CONFIG_FAIL_SAFE=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/oneshot/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/oneshot/defconfig new file mode 100644 index 0000000000000..e81879c2a5244 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/oneshot/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_ONESHOT=y +CONFIG_ESP32C3_TIMER0=y +CONFIG_ESP32C3_TIMER1=y +CONFIG_EXAMPLES_ONESHOT=y +CONFIG_EXAMPLES_TIMER=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_ONESHOT=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_TIMER=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/ostest/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/ostest/defconfig new file mode 100644 index 0000000000000..67813aabfaa4e --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/ostest/defconfig @@ -0,0 +1,43 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/pm/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/pm/defconfig new file mode 100644 index 0000000000000..b649c3927afaa --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/pm/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PM=y +CONFIG_PM_GOVERNOR_EXPLICIT_RELAX=-1 +CONFIG_PM_GOVERNOR_GREEDY=y +CONFIG_PM_PROCFS=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/pwm/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/pwm/defconfig new file mode 100644 index 0000000000000..021c6072252e8 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/pwm/defconfig @@ -0,0 +1,45 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_LEDC=y +CONFIG_ESP32C3_LEDC_TIM0=y +CONFIG_EXAMPLES_PWM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/random/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/random/defconfig new file mode 100644 index 0000000000000..82a57e2dbb037 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/random/defconfig @@ -0,0 +1,45 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_URANDOM=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_RNG=y +CONFIG_EXAMPLES_RANDOM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/romfs/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/romfs/defconfig new file mode 100644 index 0000000000000..d07378991f63f --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/romfs/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=6 +CONFIG_EXAMPLES_ROMFS=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/rtc/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/rtc/defconfig new file mode 100644 index 0000000000000..2cade8528847c --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/rtc/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_RT_TIMER=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_ALARM=y +CONFIG_RTC_DRIVER=y +CONFIG_RTC_NALARMS=2 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/sotest/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/sotest/defconfig new file mode 100644 index 0000000000000..1461052663914 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/sotest/defconfig @@ -0,0 +1,46 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_OS_SYMTAB=y +CONFIG_BOARDCTL_ROMDISK=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ESP32C3_RTC_HEAP=y +CONFIG_EXAMPLES_SOTEST=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_DLFCN=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/spiflash/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/spiflash/defconfig new file mode 100644 index 0000000000000..8c41d1de705ee --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/spiflash/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_SPIFLASH=y +CONFIG_ESP32C3_SPIFLASH_SMARTFS=y +CONFIG_ESP32C3_STORAGE_MTD_OFFSET=0x110000 +CONFIG_ESP32C3_STORAGE_MTD_SIZE=0xf0000 +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NAME_MAX=48 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_LOSMART=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SMARTFS_MAXNAMLEN=48 +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_FLASH_ERASEALL=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_FSTEST=y +CONFIG_TESTING_FSTEST_MOUNTPT="/mnt" +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/sta_softap/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/sta_softap/defconfig new file mode 100644 index 0000000000000..1e543387989b7 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/sta_softap/defconfig @@ -0,0 +1,81 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_WIRELESS=y +CONFIG_DEBUG_WIRELESS_ERROR=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_ESP32C3_SPIFLASH=y +CONFIG_ESP32C3_SPIFLASH_SPIFFS=y +CONFIG_ESP32C3_STORAGE_MTD_OFFSET=0x110000 +CONFIG_ESP32C3_STORAGE_MTD_SIZE=0xf0000 +CONFIG_ESP32C3_WIFI=y +CONFIG_ESP32C3_WIFI_STATION_SOFTAP=y +CONFIG_EXAMPLES_DHCPD=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_MM_REGIONS=3 +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETUTILS_CJSON=y +CONFIG_NETUTILS_DHCPD=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1514 +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_UDP=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_DEFAULT=y +CONFIG_SPIFFS_NAME_MAX=48 +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TLS_TASK_NELEM=4 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y +CONFIG_WIRELESS_WAPI_INITCONF=y +CONFIG_WIRELESS_WAPI_STACKSIZE=4096 diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/tickless/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/tickless/defconfig new file mode 100644 index 0000000000000..8f94776fcf53e --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/tickless/defconfig @@ -0,0 +1,44 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_TICKLESS=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/timer/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/timer/defconfig new file mode 100644 index 0000000000000..473cc3a53bd2d --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/timer/defconfig @@ -0,0 +1,46 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_TIMER0=y +CONFIG_ESP32C3_TIMER1=y +CONFIG_EXAMPLES_TIMER=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_TIMER=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/twai/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/twai/defconfig new file mode 100644 index 0000000000000..b78d5653da115 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/twai/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3MINI1=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_TWAI0=y +CONFIG_ETC_ROMFS=y +CONFIG_EXAMPLES_CAN=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/uid/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/uid/defconfig new file mode 100644 index 0000000000000..4ec4c11b387f2 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/uid/defconfig @@ -0,0 +1,43 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_UNIQUEID=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/usbconsole/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/usbconsole/defconfig new file mode 100644 index 0000000000000..b18f3764c07a7 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/usbconsole/defconfig @@ -0,0 +1,45 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ESP32C3_UART0 is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_USBSERIAL=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_HOST_MACOS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/watchdog/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/watchdog/defconfig new file mode 100644 index 0000000000000..fd24d97b143e6 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/watchdog/defconfig @@ -0,0 +1,46 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP32C3_MWDT0=y +CONFIG_ESP32C3_MWDT1=y +CONFIG_EXAMPLES_WATCHDOG=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WATCHDOG=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/watcher/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/watcher/defconfig new file mode 100644 index 0000000000000..16bbdf473b233 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/watcher/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_DRIVERS_NOTE=y +CONFIG_ESP32C3_MWDT0=y +CONFIG_ESP32C3_MWDT1=y +CONFIG_EXAMPLES_WATCHER=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_INSTRUMENTATION=y +CONFIG_SCHED_INSTRUMENTATION_SWITCH=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WATCHDOG=y diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/wifi/defconfig b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/wifi/defconfig new file mode 100644 index 0000000000000..0e9578798de62 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/configs/wifi/defconfig @@ -0,0 +1,76 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32c3-legacy" +CONFIG_ARCH_CHIP_ESP32C3=y +CONFIG_ARCH_CHIP_ESP32C3WROOM02=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_ESP32C3_SPIFLASH=y +CONFIG_ESP32C3_SPIFLASH_SPIFFS=y +CONFIG_ESP32C3_WIFI=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_NBUFFERS=124 +CONFIG_IOB_THROTTLE=24 +CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_NAME_MAX=48 +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETUTILS_CJSON=y +CONFIG_NETUTILS_IPERF=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ETH_PKTSIZE=1514 +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_DELAYED_ACK=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_WRITE_BUFFERS=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_DEFAULT=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TLS_TASK_NELEM=4 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y +CONFIG_WIRELESS_WAPI_INITCONF=y +CONFIG_WIRELESS_WAPI_STACKSIZE=4096 diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/include/board.h b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/include/board.h new file mode 100644 index 0000000000000..6b6552b455317 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/include/board.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/esp32c3-devkit/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_INCLUDE_BOARD_H +#define __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_INCLUDE_BOARD_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Clocking *****************************************************************/ + +#define BOARD_XTAL_FREQUENCY 40000000 + +/* GPIO pins used by the GPIO Subsystem */ + +#define BOARD_NGPIOOUT 2 /* Amount of GPIO Output pins */ +#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ + +#endif /* __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_INCLUDE_BOARD_H */ + diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/include/board_memorymap.h b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/include/board_memorymap.h new file mode 100644 index 0000000000000..ae6f7d97de4bb --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/include/board_memorymap.h @@ -0,0 +1,116 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/esp32c3-devkit/include/board_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_INCLUDE_BOARD_MEMORYMAP_H +#define __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_INCLUDE_BOARD_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Kernel ROM */ + +#define KIROM_START (uintptr_t)__kirom_start +#define KIROM_SIZE (uintptr_t)__kirom_size +#define KDROM_START (uintptr_t)__kdrom_start +#define KDROM_SIZE (uintptr_t)__kdrom_size + +/* Kernel RAM */ + +#define KIRAM_START (uintptr_t)__kiram_start +#define KIRAM_SIZE (uintptr_t)__kiram_size +#define KIRAM_END (uintptr_t)__kiram_end +#define KDRAM_START (uintptr_t)__kdram_start +#define KDRAM_SIZE (uintptr_t)__kdram_size +#define KDRAM_END (uintptr_t)__kdram_end + +/* Exception vectors */ + +#define VECTORS_START (uintptr_t)__vectors_start +#define VECTORS_END (uintptr_t)__vectors_end + +/* User ROM */ + +#define UIROM_START (uintptr_t)__uirom_start +#define UIROM_SIZE (uintptr_t)__uirom_size +#define UIROM_END (uintptr_t)__uirom_end +#define UDROM_START (uintptr_t)__udrom_start +#define UDROM_SIZE (uintptr_t)__udrom_size +#define UDROM_END (uintptr_t)__udrom_end + +/* User RAM */ + +#define UIRAM_START (uintptr_t)__uiram_start +#define UIRAM_SIZE (uintptr_t)__uiram_size +#define UIRAM_END (uintptr_t)__uiram_end +#define UDRAM_START (uintptr_t)__udram_start +#define UDRAM_SIZE (uintptr_t)__udram_size +#define UDRAM_END (uintptr_t)__udram_end + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Kernel ROM (RX) */ + +extern uint8_t __kirom_start[]; +extern uint8_t __kirom_size[]; +extern uint8_t __kdrom_start[]; +extern uint8_t __kdrom_size[]; + +/* Kernel RAM (RW) */ + +extern uint8_t __kiram_start[]; +extern uint8_t __kiram_size[]; +extern uint8_t __kiram_end[]; +extern uint8_t __kdram_start[]; +extern uint8_t __kdram_size[]; +extern uint8_t __kdram_end[]; + +/* Exception vectors */ + +extern uint8_t __vectors_start[]; +extern uint8_t __vectors_end[]; + +/* User ROM (RX) */ + +extern uint8_t __uirom_start[]; +extern uint8_t __uirom_size[]; +extern uint8_t __uirom_end[]; +extern uint8_t __udrom_start[]; +extern uint8_t __udrom_size[]; +extern uint8_t __udrom_end[]; + +/* User RAM (RW) */ + +extern uint8_t __uiram_start[]; +extern uint8_t __uiram_size[]; +extern uint8_t __uiram_end[]; +extern uint8_t __udram_start[]; +extern uint8_t __udram_size[]; +extern uint8_t __udram_end[]; + +#endif /* __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_INCLUDE_BOARD_MEMORYMAP_H */ diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/scripts/Make.defs b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/scripts/Make.defs new file mode 100644 index 0000000000000..790e20407ca0a --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/scripts/Make.defs @@ -0,0 +1,66 @@ +############################################################################ +# boards/risc-v/esp32c3-legacy/esp32c3-devkit/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +########################################################################### + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/tools/esp32c3/Config.mk +include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs + +ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32c3_rom.ld + +# Pick the linker scripts from the board level if they exist, if not +# pick the common linker scripts. + +ifeq ($(CONFIG_BUILD_PROTECTED),y) + ARCHSCRIPT += $(call FINDSCRIPT,protected_memory.ld) + ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld) +else + ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) + + ifeq ($(CONFIG_ESP32C3_APP_FORMAT_MCUBOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) + else + ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) + endif +endif + +ARCHPICFLAGS = -fpic + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -Werror=return-type +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) + +LDMODULEFLAGS = -melf32lriscv -r -e module_initialize +LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld) + +# ELF module definitions + +CELFFLAGS = $(CFLAGS) +CXXELFFLAGS = $(CXXFLAGS) + +LDELFFLAGS = -melf32lriscv -r -e main +LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)$(DELIM)binfmt$(DELIM)libelf$(DELIM)gnu-elf.ld) diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/Make.defs b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/Make.defs new file mode 100644 index 0000000000000..92dcab25f951c --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/Make.defs @@ -0,0 +1,52 @@ +############################################################################# +# boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +CSRCS = esp32c3_boot.c esp32c3_bringup.c + +ifeq ($(CONFIG_BOARDCTL),y) + CSRCS += esp32c3_appinit.c + + ifeq ($(CONFIG_BOARDCTL_RESET),y) + CSRCS += esp32c3_reset.c + endif +endif + +ifeq ($(CONFIG_DEV_GPIO),y) + CSRCS += esp32c3_gpio.c +endif + +ifeq ($(CONFIG_BOARDCTL_IOCTL),y) + CSRCS += esp32c3_ioctl.c +endif + +ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) + CSRCS += esp32c3_uid.c +endif + +ifeq ($(CONFIG_ETC_ROMFS),y) + RCSRCS = etc/init.d/rc.sysinit etc/init.d/rcS + RCRAWS = etc/group etc/passwd +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3-devkit.h similarity index 97% rename from boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h rename to boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3-devkit.h index 860c090d66a38..56a7a08efe65a 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3-devkit.h @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h + * boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3-devkit.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_appinit.c b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_appinit.c new file mode 100644 index 0000000000000..22d57f459b427 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_appinit.c @@ -0,0 +1,80 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "esp32c3-devkit.h" + +#ifdef CONFIG_BOARDCTL + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return esp32c3_bringup(); +#endif +} + +#endif /* CONFIG_BOARDCTL */ diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_boot.c b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_boot.c new file mode 100644 index 0000000000000..ccf2a843978f3 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_boot.c @@ -0,0 +1,86 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "riscv_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_board_initialize + * + * Description: + * All ESP32-C3 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void esp32c3_board_initialize(void) +{ +#ifdef CONFIG_ARCH_PERF_EVENTS + up_perf_init(NULL); +#endif + + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + esp32c3_bringup(); +} +#endif diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_bringup.c b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_bringup.c new file mode 100644 index 0000000000000..9e8acf45827be --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_bringup.c @@ -0,0 +1,405 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "esp32c3_wlan.h" +#include "esp32c3_spiflash.h" +#include "esp32c3_partition.h" + +#include "esp32c3-devkit.h" +#include "esp32c3_board_adc.h" +#include "esp32c3_board_bmp180.h" +#include "esp32c3_board_i2c.h" +#include "esp32c3_board_ledc.h" +#include "esp32c3_board_oneshot.h" +#include "esp32c3_board_spiflash.h" +#include "esp32c3_board_spidev.h" +#include "esp32c3_board_spislavedev.h" +#include "esp32c3_board_twai.h" +#include "esp32c3_board_wdt.h" +#include "esp32c3_board_wlan.h" +#include "esp32c3_board_mpu60x0_i2c.h" +#include "esp32c3_board_ice40.h" + +#ifdef CONFIG_SPI +# include "esp32c3_spi.h" +#endif + +#ifdef CONFIG_LCD_DEV +# include +# include +#endif + +#ifdef CONFIG_VIDEO_FB +# include +#endif + +#ifdef CONFIG_ESP32C3_RT_TIMER +# include "esp32c3_rt_timer.h" +#endif + +#ifdef CONFIG_TIMER +# include "esp32c3_tim_lowerhalf.h" +#endif + +#include "esp32c3_rtc.h" +#ifdef CONFIG_ESP32C3_EFUSE +# include "esp32c3_efuse.h" +#endif + +#ifdef CONFIG_ESP32C3_SHA_ACCELERATOR +# include "esp32c3_sha.h" +#endif + +#ifdef CONFIG_RTC_DRIVER +# include "esp32c3_rtc_lowerhalf.h" +#endif + +#ifdef CONFIG_ESP32C3_BLE +# include "esp32c3_ble.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_bringup + * + * Description: + * Perform architecture-specific initialization + * + * CONFIG_BOARD_LATE_INITIALIZE=y + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y + * Called from the NSH library + * + ****************************************************************************/ + +int esp32c3_bringup(void) +{ + int ret; + +#if defined(CONFIG_ESP32C3_EFUSE) + ret = esp32c3_efuse_initialize("/dev/efuse"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to init EFUSE: %d\n", ret); + } +#endif + +#if defined(CONFIG_ESP32C3_SHA_ACCELERATOR) && \ + !defined(CONFIG_CRYPTO_CRYPTODEV_HARDWARE) + ret = esp32c3_sha_init(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize SHA: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_TMPFS + /* Mount the tmpfs file system */ + + ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount tmpfs at %s: %d\n", + CONFIG_LIBC_TMPDIR, ret); + } +#endif + +#ifdef CONFIG_ESP32C3_SPIFLASH + ret = board_spiflash_init(); + if (ret) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI Flash\n"); + } +#endif + +#ifdef CONFIG_ESP32C3_PARTITION_TABLE + ret = esp32c3_partition_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize partition error=%d\n", + ret); + } +#endif + +#ifdef CONFIG_DEV_GPIO + ret = esp32c3_gpio_init(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); + } +#endif + +#if defined(CONFIG_SPI_DRIVER) && defined(CONFIG_ESP32C3_SPI2) + ret = board_spidev_initialize(ESP32C3_SPI2); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize SPI%d driver: %d\n", + ESP32C3_SPI2, ret); + } +#endif + +#if defined(CONFIG_SPI_SLAVE_DRIVER) && defined(CONFIG_ESP32C3_SPI2) + ret = board_spislavedev_initialize(ESP32C3_SPI2); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize SPI%d Slave driver: %d\n", + ESP32C3_SPI2, ret); + } +#endif + +#ifdef CONFIG_VIDEO_FB + ret = fb_register(0, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize Frame Buffer Driver.\n"); + } +#elif defined(CONFIG_LCD) + ret = board_lcd_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize LCD.\n"); + } +#endif + +#ifdef CONFIG_LCD_DEV + ret = lcddev_register(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: lcddev_register() failed: %d\n", ret); + } +#endif + +#if defined(CONFIG_I2C_DRIVER) + /* Configure I2C peripheral interfaces */ + + ret = board_i2c_init(); + + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize I2C driver: %d\n", ret); + } +#endif + +#ifdef CONFIG_CAN + + /* Initialize TWAI and register the TWAI driver. */ + + ret = board_twai_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_twai_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_SENSORS_BMP180 + /* Try to register BMP180 device in I2C0 */ + + ret = board_bmp180_initialize(0, 0); + + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize BMP180 " + "Driver for I2C0: %d\n", ret); + } +#endif + +#ifdef CONFIG_WATCHDOG + /* Configure watchdog timer */ + + ret = board_wdt_init(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize watchdog drivers: %d\n", + ret); + } +#endif + +/* First, register the timer drivers and let timer 1 for oneshot + * if it is enabled. + */ + +#ifdef CONFIG_TIMER + +#if defined(CONFIG_ESP32C3_TIMER0) && !defined(CONFIG_ESP32C3_RT_TIMER) + ret = esp32c3_timer_initialize("/dev/timer0", TIMER0); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize timer driver: %d\n", + ret); + } +#endif + +#if defined(CONFIG_ESP32C3_TIMER1) && !defined(CONFIG_ONESHOT) + ret = esp32c3_timer_initialize("/dev/timer1", TIMER1); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to initialize timer driver: %d\n", + ret); + } +#endif + +#endif /* CONFIG_TIMER */ + + /* Now register one oneshot driver */ + +#if defined(CONFIG_ONESHOT) && defined(CONFIG_ESP32C3_TIMER1) + + ret = board_oneshot_init(ONESHOT_TIMER, ONESHOT_RESOLUTION_US); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_oneshot_init() failed: %d\n", ret); + } + +#endif /* CONFIG_ONESHOT */ + +#ifdef CONFIG_ESP32C3_RT_TIMER + ret = esp32c3_rt_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESP32C3_WIRELESS + +#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST + ret = esp32c3_wifi_bt_coexist_init(); + if (ret) + { + syslog(LOG_ERR, "ERROR: Failed to initialize Wi-Fi and BT coexist\n"); + } +#endif + +#ifdef CONFIG_ESP32C3_BLE + ret = esp32c3_ble_initialize(); + if (ret) + { + syslog(LOG_ERR, "ERROR: Failed to initialize BLE\n"); + } +#endif + +#ifdef CONFIG_ESP32C3_WIFI + + ret = board_wlan_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_wlan_init() failed: %d\n", ret); + } + +#endif + +#endif /* CONFIG_ESP32C3_WIRELESS */ + +#ifdef CONFIG_ESP32C3_LEDC + ret = board_ledc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_ledc_setup() failed: %d\n", ret); + } +#endif /* CONFIG_ESP32C3_LEDC */ + +#ifdef CONFIG_ESP32C3_ADC + ret = board_adc_init(); + if (ret) + { + syslog(LOG_ERR, "ERROR: board_adc_init() failed: %d\n", ret); + } +#endif /* CONFIG_ESP32C3_ADC */ + +#ifdef CONFIG_RTC_DRIVER + /* Instantiate the ESP32-C3 RTC driver */ + + ret = esp32c3_rtc_driverinit(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to Instantiate the RTC driver: %d\n", ret); + } +#endif + +#ifdef CONFIG_MPU60X0_I2C + /* Try to register MPU60x0 device in I2C0 */ + + ret = board_mpu60x0_initialize(0, 0); + + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize MPU60x0 " + "Driver for I2C0: %d\n", ret); + } +#endif + +#ifdef CONFIG_SPI_ICE40 + ret = esp32c3_ice40_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize ICE40: %d\n", ret); + } +#endif + + /* If we got here then perhaps not all initialization was successful, but + * at least enough succeeded to bring-up NSH with perhaps reduced + * capabilities. + */ + + UNUSED(ret); + return OK; +} diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_gpio.c b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_gpio.c new file mode 100644 index 0000000000000..ac424a419db4e --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_gpio.c @@ -0,0 +1,409 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include + +#include + +#include "esp32c3-devkit.h" +#include "esp32c3_gpio.h" +#include "hardware/esp32c3_gpio_sigmap.h" + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Pin 1 and 2 are used for this example as GPIO outputs. */ + +#define GPIO_OUT1 1 +#define GPIO_OUT2 2 + +#if !defined(CONFIG_ESP32C3_GPIO_IRQ) && BOARD_NGPIOINT > 0 +# error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" +#endif + +/* Interrupt pins. GPIO9 is used as an example, any other inputs could be + * used. + */ + +#define GPIO_IRQPIN 9 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct esp32c3gpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct esp32c3gpint_dev_s +{ + struct esp32c3gpio_dev_s esp32c3gpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +static int gpout_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e pintype); +#endif + +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); +static int gpint_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e pintype); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, + .go_setpintype = gpout_setpintype, +}; + +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, GPIO_OUT2 +}; + +static struct esp32c3gpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, + .go_setpintype = gpint_setpintype, +}; + +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_IRQPIN, +}; + +static struct esp32c3gpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpout_read + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct esp32c3gpio_dev_s *esp32c3gpio = + (struct esp32c3gpio_dev_s *)dev; + + DEBUGASSERT(esp32c3gpio != NULL && value != NULL); + DEBUGASSERT(esp32c3gpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = esp32c3_gpioread(g_gpiooutputs[esp32c3gpio->id]); + return OK; +} + +/**************************************************************************** + * Name: gpout_write + ****************************************************************************/ + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct esp32c3gpio_dev_s *esp32c3gpio = + (struct esp32c3gpio_dev_s *)dev; + + DEBUGASSERT(esp32c3gpio != NULL); + DEBUGASSERT(esp32c3gpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + esp32c3_gpiowrite(g_gpiooutputs[esp32c3gpio->id], value); + return OK; +} + +/**************************************************************************** + * Name: gpout_setpintype + ****************************************************************************/ + +static int gpout_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e pintype) +{ + struct esp32c3gpio_dev_s *esp32c3gpio = + (struct esp32c3gpio_dev_s *)dev; + + DEBUGASSERT(esp32c3gpio != NULL); + DEBUGASSERT(esp32c3gpio->id < BOARD_NGPIOOUT); + gpioinfo("Setting pintype: %d\n", (int)pintype); + + esp32c3_gpio_matrix_out(g_gpiooutputs[esp32c3gpio->id], + SIG_GPIO_OUT_IDX, 0, 0); + + switch (pintype) + { + case GPIO_INPUT_PIN: + esp32c3_configgpio(g_gpiooutputs[esp32c3gpio->id], INPUT); + break; + case GPIO_INPUT_PIN_PULLUP: + esp32c3_configgpio(g_gpiooutputs[esp32c3gpio->id], INPUT_PULLUP); + break; + case GPIO_INPUT_PIN_PULLDOWN: + esp32c3_configgpio(g_gpiooutputs[esp32c3gpio->id], INPUT_PULLDOWN); + break; + case GPIO_OUTPUT_PIN: + esp32c3_configgpio(g_gpiooutputs[esp32c3gpio->id], INPUT | OUTPUT); + break; + case GPIO_OUTPUT_PIN_OPENDRAIN: + esp32c3_configgpio(g_gpiooutputs[esp32c3gpio->id], INPUT | + OUTPUT_OPEN_DRAIN); + break; + default: + return ERROR; + break; + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: esp32c3gpio_interrupt + ****************************************************************************/ + +#if BOARD_NGPIOINT > 0 +static int esp32c3gpio_interrupt(int irq, void *context, void *arg) +{ + struct esp32c3gpint_dev_s *esp32c3gpint = + (struct esp32c3gpint_dev_s *)arg; + + DEBUGASSERT(esp32c3gpint != NULL && esp32c3gpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", esp32c3gpint->callback); + + esp32c3gpint->callback(&esp32c3gpint->esp32c3gpio.gpio, + esp32c3gpint->esp32c3gpio.id); + return OK; +} + +/**************************************************************************** + * Name: gpint_read + ****************************************************************************/ + +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct esp32c3gpint_dev_s *esp32c3gpint = + (struct esp32c3gpint_dev_s *)dev; + + DEBUGASSERT(esp32c3gpint != NULL && value != NULL); + DEBUGASSERT(esp32c3gpint->esp32c3gpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = esp32c3_gpioread(g_gpiointinputs[esp32c3gpint->esp32c3gpio.id]); + return OK; +} + +/**************************************************************************** + * Name: gpint_attach + ****************************************************************************/ + +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct esp32c3gpint_dev_s *esp32c3gpint = + (struct esp32c3gpint_dev_s *)dev; + int irq = ESP32C3_PIN2IRQ(g_gpiointinputs[esp32c3gpint->esp32c3gpio.id]); + int ret; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + esp32c3_gpioirqdisable(irq); + ret = irq_attach(irq, + esp32c3gpio_interrupt, + &g_gpint[esp32c3gpint->esp32c3gpio.id]); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); + return ret; + } + + gpioinfo("Attach %p\n", callback); + esp32c3gpint->callback = callback; + return OK; +} + +/**************************************************************************** + * Name: gpint_enable + ****************************************************************************/ + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct esp32c3gpint_dev_s *esp32c3gpint = + (struct esp32c3gpint_dev_s *)dev; + int irq = ESP32C3_PIN2IRQ(g_gpiointinputs[esp32c3gpint->esp32c3gpio.id]); + + if (enable) + { + if (esp32c3gpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + esp32c3_gpioirqenable(irq, RISING); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + esp32c3_gpioirqdisable(irq); + } + + return OK; +} + +/**************************************************************************** + * Name: gpint_setpintype + ****************************************************************************/ + +static int gpint_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e pintype) +{ + struct esp32c3gpint_dev_s *esp32c3gpint = + (struct esp32c3gpint_dev_s *)dev; + + DEBUGASSERT(esp32c3gpint != NULL); + DEBUGASSERT(esp32c3gpint->esp32c3gpio.id < BOARD_NGPIOINT); + gpioinfo("Setting pintype: %d\n", (int)pintype); + switch (pintype) + { + case GPIO_INTERRUPT_HIGH_PIN: + esp32c3_configgpio(g_gpiointinputs[esp32c3gpint->esp32c3gpio.id], + INPUT_PULLUP); + break; + case GPIO_INTERRUPT_LOW_PIN: + esp32c3_configgpio(g_gpiointinputs[esp32c3gpint->esp32c3gpio.id], + INPUT_PULLDOWN); + break; + default: + return ERROR; + break; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32c3_gpio_init + ****************************************************************************/ + +int esp32c3_gpio_init(void) +{ + int pincount = 0; + int i; + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pins that will be used as output */ + + esp32c3_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp32c3_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_1 | + INPUT_FUNCTION_1); + esp32c3_gpiowrite(g_gpiooutputs[i], 0); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].esp32c3gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].esp32c3gpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].esp32c3gpio.id = i; + gpio_pin_register(&g_gpint[i].esp32c3gpio.gpio, pincount); + + /* Configure the pins that will be used as interrupt input */ + + esp32c3_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_1 | PULLDOWN); + + pincount++; + } +#endif + + return OK; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_ioctl.c b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_ioctl.c new file mode 100644 index 0000000000000..5cec969b1b4f3 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_ioctl.c @@ -0,0 +1,72 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_ioctl.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#ifdef CONFIG_BOARDCTL_IOCTL + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ioctl + * + * Description: + * The "landing site" for much of the boardctl() interface. Generic board- + * control functions invoked via ioctl() get routed through here. + * + * Since we don't do anything unusual at the moment, this function + * accomplishes nothing except avoid a missing-function linker error if + * CONFIG_BOARDCTL_IOCTL is selected. + * + * Input Parameters: + * cmd - IOCTL command being requested. + * arg - Arguments for the IOCTL. + * + * Returned Value: + * we don't yet support any boardctl IOCTLs. This function always returns + * -ENOTTY which is the standard IOCTL return value when a command is not + * supported + * + ****************************************************************************/ + +int board_ioctl(unsigned int cmd, uintptr_t arg) +{ + switch (cmd) + { + default: + return -ENOTTY; + } + + return OK; +} + +#endif /* CONFIG_BOARDCTL_IOCTL */ diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_reset.c b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_reset.c new file mode 100644 index 0000000000000..d3fc9344e6ba9 --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_reset.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_reset.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include "esp32c3_systemreset.h" + +#ifdef CONFIG_BOARDCTL_RESET + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value in this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ + syslog(LOG_INFO, "reboot status=%d\n", status); + + switch (status) + { + case EXIT_SUCCESS: + up_shutdown_handler(); + break; + case CONFIG_BOARD_ASSERT_RESET_VALUE: + break; + default: + break; + } + + up_systemreset(); + + return 0; +} + +#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_uid.c b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_uid.c new file mode 100644 index 0000000000000..d1a8fb5b254ee --- /dev/null +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_uid.c @@ -0,0 +1,49 @@ +/**************************************************************************** + * boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/esp32c3_uid.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "esp32c3_uid.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#if defined(CONFIG_BOARDCTL_UNIQUEID) +int board_uniqueid(uint8_t *uniqueid) +{ + if (uniqueid == NULL) + { + return -EINVAL; + } + + esp32c3_get_uniqueid(uniqueid); + return OK; +} +#endif diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/etc/group b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/etc/group similarity index 100% rename from boards/risc-v/esp32c3/esp32c3-devkit/src/etc/group rename to boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/etc/group diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/etc/init.d/rc.sysinit b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/etc/init.d/rc.sysinit similarity index 79% rename from boards/risc-v/esp32c3/esp32c3-devkit/src/etc/init.d/rc.sysinit rename to boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/etc/init.d/rc.sysinit index 044f5b69509c1..d7832773304bf 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/etc/init.d/rc.sysinit +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/etc/init.d/rc.sysinit @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit/src/etc/init.d/rc.sysinit + * boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/etc/init.d/rc.sysinit * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -23,14 +23,14 @@ #define CONCAT_(x, y) x##y #define CONCAT(x, y) CONCAT_(x, y) -#ifdef CONFIG_NSH_ROMFSETC +#ifdef CONFIG_ETC_ROMFS #ifdef CONFIG_FS_FAT /* Create a RAMDISK and mount it at /tmp */ -mkrd -m CONFIG_NSH_FATDEVNO -s CONFIG_NSH_FATSECTSIZE CONFIG_NSH_FATNSECTORS -mkfatfs CONCAT(/dev/ram, CONFIG_NSH_FATDEVNO) -mount -t vfat CONCAT(/dev/ram, CONFIG_NSH_FATDEVNO) CONFIG_NSH_FATMOUNTPT +mkrd -m CONFIG_ETC_FATDEVNO -s CONFIG_ETC_FATSECTSIZE CONFIG_ETC_FATNSECTORS +mkfatfs CONCAT(/dev/ram, CONFIG_ETC_FATDEVNO) +mount -t vfat CONCAT(/dev/ram, CONFIG_ETC_FATDEVNO) CONFIG_ETC_FATMOUNTPT #endif /* CONFIG_FS_FAT */ -#endif /* CONFIG_NSH_ROMFSETC */ +#endif /* CONFIG_ETC_ROMFS */ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/etc/init.d/rcS b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/etc/init.d/rcS similarity index 93% rename from boards/risc-v/esp32c3/esp32c3-devkit/src/etc/init.d/rcS rename to boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/etc/init.d/rcS index 516a7cf649da4..504982dfcfe19 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/etc/init.d/rcS +++ b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/etc/init.d/rcS @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit/src/etc/init.d/rcS + * boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/etc/init.d/rcS * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/etc/passwd b/boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/etc/passwd similarity index 100% rename from boards/risc-v/esp32c3/esp32c3-devkit/src/etc/passwd rename to boards/risc-v/esp32c3-legacy/esp32c3-devkit/src/etc/passwd diff --git a/boards/risc-v/esp32c3/common/Kconfig b/boards/risc-v/esp32c3/common/Kconfig index bf9503f547993..711e47f2d55bf 100644 --- a/boards/risc-v/esp32c3/common/Kconfig +++ b/boards/risc-v/esp32c3/common/Kconfig @@ -3,7 +3,7 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -config ESP32C3_MERGE_BINS +config ESPRESSIF_MERGE_BINS bool "Merge raw binary files into a single file" default n ---help--- @@ -12,63 +12,39 @@ config ESP32C3_MERGE_BINS This is only useful when the path to binary files (e.g. bootloader) is provided via the ESPTOOL_BINDIR variable. -choice ESP32C3_SPIFLASH_FS +choice ESPRESSIF_SPIFLASH_FS prompt "Mount SPI Flash MTD on bring-up" - default ESP32C3_SPIFLASH_SMARTFS - depends on ESP32C3_MTD + default ESPRESSIF_SPIFLASH_SMARTFS + depends on ESPRESSIF_MTD optional ---help--- Mount the SPI Flash MTD with the selected File System format on board bring-up. If not selected, the MTD will be registered as a device node on /dev. -config ESP32C3_SPIFLASH_SMARTFS +config ESPRESSIF_SPIFLASH_SMARTFS bool "SmartFS" select FS_SMARTFS select MTD_SMART - depends on !ESP32C3_SECURE_FLASH_ENC_ENABLED -comment "SmartFS not supported with Flash Encryption" - depends on ESP32C3_SECURE_FLASH_ENC_ENABLED - -config ESP32C3_SPIFLASH_NXFFS +config ESPRESSIF_SPIFLASH_NXFFS bool "NXFFS" select FS_NXFFS - depends on !ESP32C3_SECURE_FLASH_ENC_ENABLED - -comment "NXFFS not supported with Flash Encryption" - depends on ESP32C3_SECURE_FLASH_ENC_ENABLED -config ESP32C3_SPIFLASH_SPIFFS +config ESPRESSIF_SPIFLASH_SPIFFS bool "SPIFFS" select FS_SPIFFS - depends on !ESP32C3_SECURE_FLASH_ENC_ENABLED -comment "SPIFFS not supported with Flash Encryption" - depends on ESP32C3_SECURE_FLASH_ENC_ENABLED - -config ESP32C3_SPIFLASH_LITTLEFS +config ESPRESSIF_SPIFLASH_LITTLEFS bool "LittleFS" select FS_LITTLEFS -config ESP32C3_SPIFLASH_MTD_CONFIG +config ESPRESSIF_SPIFLASH_MTD_CONFIG bool "Non-volatile storage" -endchoice # ESP32C3_SPIFLASH_FS +endchoice # ESPRESSIF_SPIFLASH_FS -config ESP32C3_SPIFLASH_FS_MOUNT_PT +config ESPRESSIF_SPIFLASH_FS_MOUNT_PT string "File-system Mount Point" - depends on ESP32C3_SPIFLASH_LITTLEFS + depends on ESPRESSIF_SPIFLASH_LITTLEFS default "/data" - -if LCD_ST7735 || LCD_ST7789 || LCD_GC9A01 - -config ESP32C3_LCD_RSTPIN - int "LCD reset pin" - default 9 - -config ESP32C3_LCD_BLPIN - int "LCD backlight pin" - default 18 - -endif # LCD_ST7735 || LCD_ST7789 || LCD_GC9A01 diff --git a/boards/risc-v/esp32c3/common/include/esp_board_ledc.h b/boards/risc-v/esp32c3/common/include/esp_board_ledc.h new file mode 100644 index 0000000000000..06eeedd0ea6b5 --- /dev/null +++ b/boards/risc-v/esp32c3/common/include/esp_board_ledc.h @@ -0,0 +1,74 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/common/include/esp_board_ledc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C3_COMMON_INCLUDE_ESP_BOARD_LEDC_H +#define __BOARDS_RISCV_ESP32C3_COMMON_INCLUDE_ESP_BOARD_LEDC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ledc_setup + * + * Description: + * Initialize LEDC PWM and register the PWM device. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_LEDC +int board_ledc_setup(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISCV_ESP32C3_COMMON_INCLUDE_ESP_BOARD_LEDC_H */ diff --git a/boards/risc-v/esp32c3/common/include/esp_board_rmt.h b/boards/risc-v/esp32c3/common/include/esp_board_rmt.h new file mode 100644 index 0000000000000..74fd115341c0b --- /dev/null +++ b/boards/risc-v/esp32c3/common/include/esp_board_rmt.h @@ -0,0 +1,97 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/common/include/esp_board_rmt.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISC_V_ESP32C3_COMMON_INCLUDE_ESP_BOARD_RMT_H +#define __BOARDS_RISC_V_ESP32C3_COMMON_INCLUDE_ESP_BOARD_RMT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_ESP_RMT + +/**************************************************************************** + * Name: board_rmt_rxinitialize + * + * Description: + * Initialize the RMT peripheral and register an RX device. + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the RX channel + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_rmt_rxinitialize(int ch, int pin); + +/**************************************************************************** + * Name: board_rmt_txinitialize + * + * Description: + * Initialize the RMT peripheral and register an TX device. + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the TX channel + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_rmt_txinitialize(int ch, int pin); + +#endif /* CONFIG_ESP_RMT */ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISC_V_ESP32C3_COMMON_INCLUDE_ESP_BOARD_RMT_H */ diff --git a/boards/risc-v/esp32c3/common/include/esp_board_spiflash.h b/boards/risc-v/esp32c3/common/include/esp_board_spiflash.h new file mode 100644 index 0000000000000..9e647a384e80d --- /dev/null +++ b/boards/risc-v/esp32c3/common/include/esp_board_spiflash.h @@ -0,0 +1,74 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/common/include/esp_board_spiflash.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C3_COMMON_INCLUDE_ESP_BOARD_SPIFLASH_H +#define __BOARDS_RISCV_ESP32C3_COMMON_INCLUDE_ESP_BOARD_SPIFLASH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_spiflash_init + * + * Description: + * Initialize the SPIFLASH and register the MTD device. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_SPIFLASH +int board_spiflash_init(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISCV_ESP32C3_COMMON_INCLUDE_ESP_BOARD_SPIFLASH_H */ diff --git a/boards/risc-v/esp32c3/common/include/esp_board_wlan.h b/boards/risc-v/esp32c3/common/include/esp_board_wlan.h new file mode 100644 index 0000000000000..4d51ebec4b443 --- /dev/null +++ b/boards/risc-v/esp32c3/common/include/esp_board_wlan.h @@ -0,0 +1,73 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/common/include/esp_board_wlan.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C3_COMMON_INCLUDE_ESP_BOARD_WLAN_H +#define __BOARDS_RISCV_ESP32C3_COMMON_INCLUDE_ESP_BOARD_WLAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_WIFI + +/**************************************************************************** + * Name: board_wlan_init + * + * Description: + * Configure the wireless subsystem. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int board_wlan_init(void); + +#endif /* CONFIG_ESPRESSIF_WIFI */ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISCV_ESP32C3_COMMON_INCLUDE_ESP_BOARD_WLAN_H */ diff --git a/boards/risc-v/esp32c3/common/kernel/Makefile b/boards/risc-v/esp32c3/common/kernel/Makefile deleted file mode 100644 index c5b22e6a9189c..0000000000000 --- a/boards/risc-v/esp32c3/common/kernel/Makefile +++ /dev/null @@ -1,102 +0,0 @@ -############################################################################ -# boards/risc-v/esp32c3/esp32c3-devkit/kernel/Makefile -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################ - -include $(TOPDIR)/Make.defs - -# The entry point name (if none is provided in the .config file) - -CONFIG_INIT_ENTRYPOINT ?= user_start -ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) - -# Get the paths to the libraries and the links script path in format that -# is appropriate for the host OS - -USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) -USER_LDSCRIPT = $(call CONVERT_PATH,$(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)protected_memory.ld) -USER_LDSCRIPT += $(call CONVERT_PATH,$(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)user-space.ld) -USER_LDSCRIPT += $(call CONVERT_PATH,$(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32c3_rom.ld) -USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) -USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) - -USER_LDFLAGS = --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(addprefix -T,$(addsuffix .tmp,$(USER_LDSCRIPT))) -melf32lriscv - -ifeq ($(CONFIG_DEBUG_LINK_MAP),y) -USER_LDFLAGS += --cref -Map="$(TOPDIR)$(DELIM)User.map" -endif - -USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) -USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" - -# Source files - -CSRCS = esp32c3_userspace.c -COBJS = $(CSRCS:.c=$(OBJEXT)) -OBJS = $(COBJS) - -ifeq ($(LD),$(CC)) - LDSTARTGROUP ?= -Wl,--start-group - LDENDGROUP ?= -Wl,--end-group - USER_LDFLAGS := $(addprefix -Xlinker ,$(USER_LDFLAGS)) - USER_LDFLAGS += $(CFLAGS) -else - LDSTARTGROUP ?= --start-group - LDENDGROUP ?= --end-group -endif - -# Targets: - -all: $(TOPDIR)$(DELIM)nuttx_user.elf -.PHONY: nuttx_user.elf depend clean distclean - -$(COBJS): %$(OBJEXT): %.c - $(call COMPILE, $<, $@) - -$(addsuffix .tmp,$(USER_LDSCRIPT)): $(USER_LDSCRIPT) - $(call PREPROCESS,$(patsubst %.tmp,%,$@),$@) - -# Create the nuttx_user.elf file containing all of the user-mode code - -nuttx_user.elf: $(OBJS) $(addsuffix .tmp,$(USER_LDSCRIPT)) - $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) $(LDSTARTGROUP) $(USER_LDLIBS) $(LDENDGROUP) $(USER_LIBGCC) - -$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf - $(Q) echo "LD: nuttx_user.elf" - $(Q) cp -a nuttx_user.elf $(TOPDIR)$(DELIM)nuttx_user.elf -ifeq ($(CONFIG_INTELHEX_BINARY),y) - $(Q) echo "CP: nuttx_user.hex" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex nuttx_user.elf $(USER_HEXFILE) -endif -ifeq ($(CONFIG_RAW_BINARY),y) - $(Q) echo "CP: nuttx_user.bin" - $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary nuttx_user.elf $(USER_BINFILE) -endif - $(Q) $(call DELFILE,$(addsuffix .tmp,$(USER_LDSCRIPT))) - -.depend: - -depend: .depend - -clean: - $(call DELFILE, nuttx_user.elf) - $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") - $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") - $(call CLEAN) - -distclean: clean diff --git a/boards/risc-v/esp32c3/common/kernel/esp32c3_userspace.c b/boards/risc-v/esp32c3/common/kernel/esp32c3_userspace.c deleted file mode 100644 index 837c8c7d5d920..0000000000000 --- a/boards/risc-v/esp32c3/common/kernel/esp32c3_userspace.c +++ /dev/null @@ -1,100 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit/kernel/esp32c3_userspace.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include -#include -#include - -#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -#ifndef CONFIG_NUTTX_USERSPACE -# error "CONFIG_NUTTX_USERSPACE not defined" -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* These 'addresses' of these values are setup by the linker script. */ - -extern uint8_t _stext[]; /* Start of .text */ -extern uint8_t _etext[]; /* End_1 of .text + .rodata */ -extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ -extern uint8_t _sdata[]; /* Start of .data */ -extern uint8_t _edata[]; /* End+1 of .data */ -extern uint8_t _sbss[]; /* Start of .bss */ -extern uint8_t _ebss[]; /* End+1 of .bss */ - -extern uint8_t __ld_udram_end[]; /* End+1 of user ram section */ - -const struct userspace_s userspace locate_data(".userspace") = -{ - /* General memory map */ - - .us_entrypoint = CONFIG_INIT_ENTRYPOINT, - .us_textstart = (uintptr_t)_stext, - .us_textend = (uintptr_t)_etext, - .us_datasource = (uintptr_t)_eronly, - .us_datastart = (uintptr_t)_sdata, - .us_dataend = (uintptr_t)_edata, - .us_bssstart = (uintptr_t)_sbss, - .us_bssend = (uintptr_t)_ebss, - - .us_heapend = (uintptr_t)__ld_udram_end, - - /* Memory manager heap structure */ - - .us_heap = &g_mmheap, - - /* Task/thread startup routines */ - - .task_startup = nxtask_startup, - - /* Signal handler trampoline */ - - .signal_handler = up_signal_handler, - - /* Userspace work queue support (declared in include/nuttx/wqueue.h) */ - -#ifdef CONFIG_LIBC_USRWORK - .work_usrstart = work_usrstart, -#endif -}; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/risc-v/esp32c3/common/scripts/common.ld b/boards/risc-v/esp32c3/common/scripts/common.ld new file mode 100644 index 0000000000000..7b2292738b2f7 --- /dev/null +++ b/boards/risc-v/esp32c3/common/scripts/common.ld @@ -0,0 +1,35 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/common/scripts/common.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ +#include + +#if CONFIG_ESPRESSIF_SOC_RTC_MEM_SUPPORTED +# define ESP_BOOTLOADER_RESERVE_RTC 0 + + /* rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files). + * For rtc_timer_data_in_rtc_mem section. + */ +# define RTC_TIMER_RESERVE_RTC (24) + +# ifdef CONFIG_ARCH_CHIP_ESP32 +# define RESERVE_RTC_MEM (RTC_TIMER_RESERVE_RTC) +# else +# define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC) +# endif /* CONFIG_ARCH_CHIP_ESP32 */ +#endif /* CONFIG_ESPRESSIF_SOC_RTC_MEM_SUPPORTED */ diff --git a/boards/risc-v/esp32c3/common/scripts/esp32c3_aliases.ld b/boards/risc-v/esp32c3/common/scripts/esp32c3_aliases.ld index 9acf82c28b90d..3606cec4f5acb 100644 --- a/boards/risc-v/esp32c3/common/scripts/esp32c3_aliases.ld +++ b/boards/risc-v/esp32c3/common/scripts/esp32c3_aliases.ld @@ -18,7 +18,15 @@ * ****************************************************************************/ -#ifdef CONFIG_ESP32C3_BLE +cache_set_idrom_mmu_size = Cache_Set_IDROM_MMU_Size; +cache_dbus_mmu_set = Cache_Dbus_MMU_Set; +cache_ibus_mmu_set = Cache_Ibus_MMU_Set; +cache_invalidate_icache_all = Cache_Invalidate_ICache_All; +cache_resume_icache = Cache_Resume_ICache; +cache_suspend_icache = Cache_Suspend_ICache; +cache_invalidate_icache_all = Cache_Invalidate_ICache_All; + +#ifdef CONFIG_ESPRESSIF_BLE /* Lower-case aliases for BLE library symbols not compliant to nxstyle */ diff --git a/boards/risc-v/espressif/common/scripts/esp32c3_flat_memory.ld b/boards/risc-v/esp32c3/common/scripts/esp32c3_flat_memory.ld similarity index 95% rename from boards/risc-v/espressif/common/scripts/esp32c3_flat_memory.ld rename to boards/risc-v/esp32c3/common/scripts/esp32c3_flat_memory.ld index a9fc160421417..2ae8fa2d8f064 100644 --- a/boards/risc-v/espressif/common/scripts/esp32c3_flat_memory.ld +++ b/boards/risc-v/esp32c3/common/scripts/esp32c3_flat_memory.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/espressif/common/scripts/esp32c3_flat_memory.ld + * boards/risc-v/esp32c3/common/scripts/esp32c3_flat_memory.ld * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -73,6 +73,9 @@ MEMORY metadata (RX) : org = CONFIG_ESPRESSIF_APP_MCUBOOT_HEADER_SIZE, len = 0x20 ROM (RX) : org = ORIGIN(metadata) + LENGTH(metadata), len = FLASH_SIZE - ORIGIN(ROM) +#elif defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) + ROM (RX) : org = ORIGIN(ROM), + len = FLASH_SIZE - ORIGIN(ROM) #endif /* Below values assume the flash cache is on, and have the blocks this @@ -95,7 +98,7 @@ MEMORY * constraint that (paddr % 64KB == vaddr % 64KB). */ - irom0_0_seg (RX) : org = 0x42000020, len = FLASH_SIZE - 0x20 + irom0_0_seg (RX) : org = 0x42000000, len = FLASH_SIZE #endif /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. */ @@ -128,7 +131,7 @@ MEMORY * constraint that (paddr % 64KB == vaddr % 64KB). */ - drom0_0_seg (R) : org = 0x3c000020, len = FLASH_SIZE - 0x20 + drom0_0_seg (R) : org = 0x3c000000, len = FLASH_SIZE #endif /* RTC fast memory (executable). Persists over deep sleep. */ diff --git a/boards/risc-v/espressif/common/scripts/esp32c3_legacy_sections.ld b/boards/risc-v/esp32c3/common/scripts/esp32c3_legacy_sections.ld similarity index 98% rename from boards/risc-v/espressif/common/scripts/esp32c3_legacy_sections.ld rename to boards/risc-v/esp32c3/common/scripts/esp32c3_legacy_sections.ld index 75694ba589360..d93020dd9d07f 100644 --- a/boards/risc-v/espressif/common/scripts/esp32c3_legacy_sections.ld +++ b/boards/risc-v/esp32c3/common/scripts/esp32c3_legacy_sections.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/espressif/common/scripts/esp32c3_legacy_sections.ld + * boards/risc-v/esp32c3/common/scripts/esp32c3_legacy_sections.ld * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -59,31 +59,6 @@ SECTIONS . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; } >dram0_0_seg - /* Shared RAM */ - - .dram0.bss (NOLOAD) : - { - . = ALIGN (8); - _sbss = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.share.mem) - *(.gnu.linkonce.b.*) - *(COMMON) - - . = ALIGN (8); - _ebss = ABSOLUTE(.); - } >dram0_0_seg - .noinit (NOLOAD): { /* This section contains data that is not initialized during load, @@ -126,10 +101,31 @@ SECTIONS *libsched.a:irq_dispatch.*(.rodata .rodata.*) . = ALIGN(4); _edata = ABSOLUTE(.); + } >dram0_0_seg + + /* Shared RAM */ - /* Heap starts at the end of .data */ + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) - _sheap = ABSOLUTE(.); + . = ALIGN (8); + _ebss = ABSOLUTE(.); } >dram0_0_seg .flash.text : diff --git a/boards/risc-v/espressif/common/scripts/esp32c3_mcuboot_sections.ld b/boards/risc-v/esp32c3/common/scripts/esp32c3_mcuboot_sections.ld similarity index 83% rename from boards/risc-v/espressif/common/scripts/esp32c3_mcuboot_sections.ld rename to boards/risc-v/esp32c3/common/scripts/esp32c3_mcuboot_sections.ld index 960df6ebac234..7549e40fa254c 100644 --- a/boards/risc-v/espressif/common/scripts/esp32c3_mcuboot_sections.ld +++ b/boards/risc-v/esp32c3/common/scripts/esp32c3_mcuboot_sections.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/espressif/common/scripts/esp32c3_mcuboot_sections.ld + * boards/risc-v/esp32c3/common/scripts/esp32c3_mcuboot_sections.ld * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -59,6 +59,17 @@ SECTIONS _image_drom_lma = LOADADDR(.flash.rodata); _image_drom_size = LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) - _image_drom_lma; + .flash.appdesc : ALIGN(0x10) + { + _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ + _rodata_start = ABSOLUTE(.); + + /* Create an empty gap within this section. Thanks to this, the end of this + * section will match .flash.rodata's begin address. Thus, both sections + * will be merged when creating the final bin image. */ + . = ALIGN(ALIGNOF(.flash.rodata)); + } >default_rodata_seg + .flash.rodata : { _srodata = ABSOLUTE(.); @@ -115,6 +126,16 @@ SECTIONS . = ALIGN(4); } >drom0_0_seg AT>ROM + .flash.rodata_noload (NOLOAD) : + { + /* + This is a symbol marking the flash.rodata end, this can be used for mmu driver to maintain virtual address + We don't need to include the noload rodata in this section + */ + _rodata_reserved_end = ABSOLUTE(.); + . = ALIGN (4); + } > default_rodata_seg AT > ROM + .iram0.text : { _iram_start = ABSOLUTE(.); @@ -126,6 +147,9 @@ SECTIONS *(.iram1) *(.iram1.*) + *libarch.a:*cache_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*) *libarch.a:esp_spiflash.*(.literal .text .literal.* .text.*) esp_head.*(.literal .text .literal.* .text.*) esp_start.*(.literal .text .literal.* .text.*) @@ -144,32 +168,6 @@ SECTIONS . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; } >dram0_0_seg - /* Shared RAM */ - - .dram0.bss (NOLOAD) : - { - /* .bss initialized on power-up */ - - . = ALIGN (8); - _sbss = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - KEEP (*(.bss)) - *(.bss.*) - *(.share.mem) - *(.gnu.linkonce.b.*) - *(COMMON) - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } >dram0_0_seg - .noinit (NOLOAD): { /* This section contains data that is not initialized during load, @@ -200,16 +198,40 @@ SECTIONS KEEP (*(.gnu.linkonce.s2.*)) KEEP (*(.jcr)) *(.dram1 .dram1.*) + *libarch.a:*cache_hal.*(.rodata .rodata.*) + *libarch.a:*mpu_hal.*(.rodata .rodata.*) + *libarch.a:*mmu_hal.*(.rodata .rodata.*) *libarch.a:esp_spiflash.*(.rodata .rodata.*) esp_head.*(.rodata .rodata.*) esp_start.*(.rodata .rodata.*) _edata = ABSOLUTE(.); - . = ALIGN(4); + } >dram0_0_seg AT>ROM - /* Heap starts at the end of .data */ + /* Shared RAM */ - _sheap = ABSOLUTE(.); - } >dram0_0_seg AT>ROM + .dram0.bss (NOLOAD) : + { + /* .bss initialized on power-up */ + + . = ALIGN (8); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + KEEP (*(.bss)) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(32); + _ebss = ABSOLUTE(.); + } >dram0_0_seg /* Marks the end of IRAM code segment */ @@ -262,6 +284,8 @@ SECTIONS .flash.text : ALIGN(0x0000FFFF) { _stext = .; + _instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */ + _text_start = ABSOLUTE(.); *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ @@ -270,6 +294,8 @@ SECTIONS *(.gnu.version) . = ALIGN(4); + _text_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */ _etext = .; } >irom0_0_seg AT>ROM diff --git a/boards/risc-v/esp32c3/common/scripts/esp32c3_simple_boot_sections.ld b/boards/risc-v/esp32c3/common/scripts/esp32c3_simple_boot_sections.ld new file mode 100644 index 0000000000000..e45c748124415 --- /dev/null +++ b/boards/risc-v/esp32c3/common/scripts/esp32c3_simple_boot_sections.ld @@ -0,0 +1,439 @@ +/**************************************************************************** + * boards/risc-v/espressif/common/scripts/esp32c3_simple_boot_sections.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Default entry point: */ + +ENTRY(__start); + +SECTIONS +{ + .iram0.text : + { + _iram_start = ABSOLUTE(.); + + /* Vectors go to start of IRAM */ + + KEEP(*(.exception_vectors.text)); + . = ALIGN(4); + + *(.iram1) + *(.iram1.*) + *libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*) + + *libarch.a:*brownout.*(.text .text.* .literal .literal.*) + *libarch.a:*cpu.*(.text .text.* .literal .literal.*) + *libarch.a:*gpio_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*periph_ctrl.*(.text .text.* .literal .literal.*) + *libarch.a:*clk.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk_tree.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk_tree_common.*(.text .text.* .literal .literal.*) + *libarch.a:*clk_tree_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_init.*(.text .text.* .literal .literal.*) + *libarch.a:*regi2c_ctrl.*(.text .text.* .literal .literal.*) + *libarch.a:*gpio_periph.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_clk.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_clk_init.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_sleep.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_time.*(.text .text.* .literal .literal.*) + *libarch.a:*systimer.*(.text .text.* .literal .literal.*) + *libarch.a:*systimer_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_hal_iram.*(.text .text.* .literal .literal.*) + *libarch.a:*wdt_hal_iram.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_banner_wrap.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_init.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_common.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_common_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_console.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_console_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_esp32c3.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_flash.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_flash_config_esp32c3.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_clock_init.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_clock_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_efuse.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_panic.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_mem.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_random.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_random_esp32c3.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_image_format.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_soc.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_sha.*(.text .text.* .literal .literal.*) + *libarch.a:*flash_encrypt.*(.text .text.* .literal .literal.*) + *libarch.a:*cache_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_periph.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_uart.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_sys.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_spiflash.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_efuse_fields.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_efuse_api_key.*(.text .text.* .literal .literal.*) + *libarch.a:*efuse_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*log.*(.text .text.* .literal .literal.*) + *libarch.a:*log_noos.*(.text .text.* .literal .literal.*) + *libarch.a:esp_spiflash.*(.literal .text .literal.* .text.*) + + esp_head.*(.literal .text .literal.* .text.*) + esp_start.*(.literal .text .literal.* .text.*) + + *(.wifi0iram.*) + *(.wifirxiram.*) + *(.wifislpiram.*) + *(.wifiorslpiram.*) + *(.wifislprxiram.*) + + } >iram0_0_seg AT > ROM + + /* This section is required to skip .iram0.text area because iram0_0_seg + * and dram0_0_seg reflect the same address space on different buses. + */ + + .dram0.dummy (NOLOAD): + { + . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; + } >dram0_0_seg + + .noinit (NOLOAD): + { + /* This section contains data that is not initialized during load, + * or during the application's initialization sequence. + */ + + *(.noinit) + *(.noinit.*) + } >dram0_0_seg + + .dram0.data : + { + . = ALIGN (16); + _data_start = ABSOLUTE(.); + _sdata = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + __global_pointer$ = . + 0x800; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + *(.dram1) + *(.dram1.*) + *libsched.a:irq_dispatch.*(.rodata .rodata.*) + + *libarch.a:*brownout.*(.rodata .rodata.*) + *libarch.a:*cpu.*(.rodata .rodata.*) + *libarch.a:*gpio_hal.*(.rodata .rodata.*) + *libarch.a:*periph_ctrl.*(.rodata .rodata.*) + *libarch.a:*clk.*(.rodata .rodata.*) + *libarch.a:*esp_clk.*(.rodata .rodata.*) + *libarch.a:*esp_clk_tree.*(.rodata .rodata.*) + *libarch.a:*esp_clk_tree_common.*(.rodata .rodata.*) + *libarch.a:*clk_tree_hal.*(.rodata .rodata.*) + *libarch.a:*rtc_init.*(.rodata .rodata.*) + *libarch.a:*regi2c_ctrl.*(.rodata .rodata.*) + *libarch.a:*gpio_periph.*(.rodata .rodata.*) + *libarch.a:*rtc_clk.*(.rodata .rodata.*) + *libarch.a:*rtc_clk_init.*(.rodata .rodata.*) + *libarch.a:*rtc_sleep.*(.rodata .rodata.*) + *libarch.a:*rtc_time.*(.rodata .rodata.*) + *libarch.a:*systimer.*(.rodata .rodata.*) + *libarch.a:*systimer_hal.*(.rodata .rodata.*) + *libarch.a:*uart_hal_iram.*(.rodata .rodata.*) + *libarch.a:*wdt_hal_iram.*(.rodata .rodata.*) + *libarch.a:*bootloader_banner_wrap.*(.rodata .rodata.*) + *libarch.a:*bootloader_init.*(.rodata .rodata.*) + *libarch.a:*bootloader_common.*(.rodata .rodata.*) + *libarch.a:*bootloader_common_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_console.*(.rodata .rodata.*) + *libarch.a:*bootloader_console_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_esp32c3.*(.rodata .rodata.*) + *libarch.a:*bootloader_flash.*(.rodata .rodata.*) + *libarch.a:*bootloader_flash_config_esp32c3.*(.rodata .rodata.*) + *libarch.a:*bootloader_clock_init.*(.rodata .rodata.*) + *libarch.a:*bootloader_clock_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_efuse.*(.rodata .rodata.*) + *libarch.a:*bootloader_panic.*(.rodata .rodata.*) + *libarch.a:*bootloader_mem.*(.rodata .rodata.*) + *libarch.a:*bootloader_random.*(.rodata .rodata.*) + *libarch.a:*bootloader_random_esp32c3.*(.rodata .rodata.*) + *libarch.a:*esp_image_format.*(.rodata .rodata.*) + *libarch.a:*bootloader_soc.*(.rodata .rodata.*) + *libarch.a:*bootloader_sha.*(.rodata .rodata.*) + *libarch.a:*flash_encrypt.*(.rodata .rodata.*) + *libarch.a:*cache_hal.*(.rodata .rodata.*) + *libarch.a:*uart_hal.*(.rodata .rodata.*) + *libarch.a:*mpu_hal.*(.rodata .rodata.*) + *libarch.a:*mmu_hal.*(.rodata .rodata.*) + *libarch.a:*uart_periph.*(.rodata .rodata.*) + *libarch.a:*esp_rom_uart.*(.rodata .rodata.*) + *libarch.a:*esp_rom_sys.*(.rodata .rodata.*) + *libarch.a:*esp_rom_spiflash.*(.rodata .rodata.*) + *libarch.a:*esp_efuse_fields.*(.rodata .rodata.*) + *libarch.a:*esp_efuse_api_key.*(.rodata .rodata.*) + *libarch.a:*efuse_hal.*(.rodata .rodata.*) + *libarch.a:*log.*(.rodata .rodata.*) + *libarch.a:*log_noos.*(.rodata .rodata.*) + *libarch.a:esp_spiflash.*(.rodata .rodata.*) + + esp_head.*(.rodata .rodata.*) + esp_start.*(.rodata .rodata.*) + + . = ALIGN(4); + _edata = ABSOLUTE(.); + _data_end = ABSOLUTE(.); + } >dram0_0_seg AT > ROM + + /* Shared RAM */ + + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + + . = ALIGN (8); + _ebss = ABSOLUTE(.); + _bss_end = ABSOLUTE(.); + } >dram0_0_seg + + _image_irom_vma = ADDR(.flash.text); + _image_irom_lma = LOADADDR(.flash.text); + _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_lma; + + .flash.text : ALIGN(0xFFFF) + { + _stext = .; + _instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */ + _text_start = ABSOLUTE(.); + + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + + _text_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */ + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + + _flash_cache_start = ABSOLUTE(0); + } >default_code_seg AT > ROM + + .flash_rodata_dummy (NOLOAD) : ALIGN(0xFFFF) + { + /* Start at the same alignment constraint than .flash.text */ + + /* . = ALIGN(ALIGNOF(.flash.text)); */ + + /* Create an empty gap as big as .flash.text section */ + + . = . + SIZEOF(.flash.text); + + /* Prepare the alignment of the section above. Few bytes (0x20) must be + * added for the mapping header. + */ + + /*. = ALIGN(0x10000) + 0x20; */ + } >default_rodata_seg + + _image_drom_vma = ADDR(.flash.rodata); + _image_drom_lma = LOADADDR(.flash.rodata); + _image_drom_size = LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) - _image_drom_lma; + + .flash.appdesc : ALIGN(0x10) + { + _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ + _rodata_start = ABSOLUTE(.); + + /* Create an empty gap within this section. Thanks to this, the end of this + * section will match .flash.rodata's begin address. Thus, both sections + * will be merged when creating the final bin image. */ + . = ALIGN(ALIGNOF(.flash.rodata)); + } >default_rodata_seg + + .flash.rodata : ALIGN(0xFFFF) + { + _srodata = ABSOLUTE(.); + *(EXCLUDE_FILE (*libarch.a:esp_spiflash.* esp_head.* esp_start.*) .rodata) + *(EXCLUDE_FILE (*libarch.a:esp_spiflash.* esp_head.* esp_start.*) .rodata.*) + + *(.rodata) + *(.rodata.*) + *(.rodata_wlog_verbose.*) + *(.rodata_wlog_debug.*) + *(.rodata_wlog_info.*) + *(.rodata_wlog_warning.*) + *(.rodata_wlog_error.*) + + *(.srodata.*) + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ constructor and destructor tables: + * RISC-V GCC is configured with --enable-initfini-array so it emits an + * .init_array section instead. + */ + + _sinit = ABSOLUTE(.); + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)) + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array)) + _einit = ABSOLUTE(.); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + + /* C++ exception handlers table: */ + + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _erodata = ABSOLUTE(.); + + /* Literals are also RO data. */ + + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + } >default_rodata_seg AT > ROM + + .flash.rodata_noload (NOLOAD) : + { + /* + This is a symbol marking the flash.rodata end, this can be used for mmu driver to maintain virtual address + We don't need to include the noload rodata in this section + */ + _rodata_reserved_end = ABSOLUTE(.); + . = ALIGN (4); + } > default_rodata_seg AT > ROM + + /* Marks the end of IRAM code segment */ + + .iram0.text_end (NOLOAD) : + { + . = ALIGN (16); + } >iram0_0_seg + + .iram0.data : + { + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + } >iram0_0_seg + + .iram0.bss (NOLOAD) : + { + . = ALIGN(16); + *(.iram.bss) + *(.iram.bss*) + + . = ALIGN(16); + _iram_end = ABSOLUTE(.); + } >iram0_0_seg + + /* RTC fast memory holds RTC wake stub code !*/ + + .rtc.text : + { + . = ALIGN(4); + *(.rtc.literal .rtc.text) + } >rtc_iram_seg + + /* RTC BSS section. */ + + .rtc.bss (NOLOAD) : + { + *(.rtc.bss) + } >rtc_iram_seg + + /* RTC data section holds RTC wake stub data/rodata. */ + + .rtc.data : + { + *(.rtc.data) + *(.rtc.data.*) + *(.rtc.rodata) + *(.rtc.rodata.*) + } >rtc_iram_seg + + /* This section holds RTC data that should have fixed addresses. + * The data are not initialized at power-up and are retained during deep sleep. + */ + .rtc_reserved (NOLOAD): + { + . = ALIGN(4); + _rtc_reserved_start = ABSOLUTE(.); + /* New data can only be added here to ensure existing data are not moved. + Because data have adhered to the end of the segment and code is relied on it. + >> put new data here << */ + + *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) + KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*)) + _rtc_reserved_end = ABSOLUTE(.); + } > rtc_reserved_seg + + _rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start; + ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)), + "RTC reserved segment data does not fit.") + +} diff --git a/boards/risc-v/esp32c3/common/scripts/flat_memory.ld b/boards/risc-v/esp32c3/common/scripts/flat_memory.ld deleted file mode 100644 index c0c7937457898..0000000000000 --- a/boards/risc-v/esp32c3/common/scripts/flat_memory.ld +++ /dev/null @@ -1,151 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/common/scripts/flat_memory.ld - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * ESP32-C3 Linker Script Memory Layout - * - * This file describes the memory layout (memory blocks) as virtual - * memory addresses. - * - * _sections.ld contains output sections to link compiler - * output into these memory blocks. - * - ****************************************************************************/ - -#include - -#include "esp32c3_aliases.ld" - -#define SRAM_IRAM_START 0x4037c000 -#define SRAM_DRAM_START 0x3fc7c000 - -/* ICache size is fixed to 16KB on ESP32-C3 */ - -#define ICACHE_SIZE 0x4000 -#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) - -/* 2nd stage bootloader iram_loader_seg start address */ - -#define SRAM_DRAM_END (0x403ce710 - I_D_SRAM_OFFSET) - -#define SRAM_IRAM_ORG (SRAM_IRAM_START + ICACHE_SIZE) -#define SRAM_DRAM_ORG (SRAM_DRAM_START + ICACHE_SIZE) - -#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_ORG) - -#ifdef CONFIG_ESP32C3_FLASH_2M -# define FLASH_SIZE 0x200000 -#elif defined (CONFIG_ESP32C3_FLASH_4M) -# define FLASH_SIZE 0x400000 -#elif defined (CONFIG_ESP32C3_FLASH_8M) -# define FLASH_SIZE 0x800000 -#elif defined (CONFIG_ESP32C3_FLASH_16M) -# define FLASH_SIZE 0x1000000 -#endif - -MEMORY -{ -#ifdef CONFIG_ESP32C3_APP_FORMAT_MCUBOOT - /* The origin values for "metadata" and "ROM" memory regions are the actual - * load addresses. - * - * NOTE: The memory region starting from 0x0 with length represented by - * CONFIG_ESP32C3_APP_MCUBOOT_HEADER_SIZE is reserved for the MCUboot header, - * which will be prepended to the binary file by the "imgtool" during the - * signing of firmware image. - */ - - metadata (RX) : org = CONFIG_ESP32C3_APP_MCUBOOT_HEADER_SIZE, len = 0x20 - ROM (RX) : org = ORIGIN(metadata) + LENGTH(metadata), - len = FLASH_SIZE - ORIGIN(ROM) -#endif - - /* Below values assume the flash cache is on, and have the blocks this - * uses subtracted from the length of the various regions. The 'data access - * port' dram/drom regions map to the same iram/irom regions but are - * connected to the data port of the CPU and e.g. allow bytewise access. - */ - - iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE - - /* Flash mapped instruction data. */ - -#ifdef CONFIG_ESP32C3_APP_FORMAT_MCUBOOT - irom0_0_seg (RX) : org = 0x42000000, len = FLASH_SIZE -#else - /* The 0x20 offset is a convenience for the app binary image generation. - * Flash cache has 64KB pages. The .bin file which is flashed to the chip - * has a 0x18 byte file header, and each segment has a 0x08 byte segment - * header. Setting this offset makes it simple to meet the flash cache MMU's - * constraint that (paddr % 64KB == vaddr % 64KB). - */ - - irom0_0_seg (RX) : org = 0x42000020, len = FLASH_SIZE - 0x20 -#endif - - /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. */ - - dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = I_D_SRAM_SIZE - - /* Flash mapped constant data */ - -#ifdef CONFIG_ESP32C3_APP_FORMAT_MCUBOOT - /* The DROM segment origin is offset by 0x40 for mirroring the actual ROM - * image layout: - * 0x0 - 0x1F : MCUboot header - * 0x20 - 0x3F : Application image metadata section - * 0x40 onwards: ROM code and data - * This is required to meet the following constraint from the external - * flash MMU: - * VMA % 64KB == LMA % 64KB - * i.e. the lower 16 bits of both the virtual address (address seen by the - * CPU) and the load address (physical address of the external flash) must - * be equal. - */ - - drom0_0_seg (R) : org = 0x3c000000 + ORIGIN(ROM), - len = FLASH_SIZE - ORIGIN(ROM) -#else - /* The 0x20 offset is a convenience for the app binary image generation. - * Flash cache has 64KB pages. The .bin file which is flashed to the chip - * has a 0x18 byte file header, and each segment has a 0x08 byte segment - * header. Setting this offset makes it simple to meet the flash cache MMU's - * constraint that (paddr % 64KB == vaddr % 64KB). - */ - - drom0_0_seg (R) : org = 0x3c000020, len = FLASH_SIZE - 0x20 -#endif - - /* RTC fast memory. Persists over deep sleep. */ - - rtc_seg(RWX) : org = 0x50000000, len = 0x2000 -} - -#if CONFIG_ESP32C3_DEVKIT_RUN_IRAM - REGION_ALIAS("default_rodata_seg", dram0_0_seg); - REGION_ALIAS("default_code_seg", iram0_0_seg); -#else - REGION_ALIAS("default_rodata_seg", drom0_0_seg); - REGION_ALIAS("default_code_seg", irom0_0_seg); -#endif /* CONFIG_ESP32C3_DEVKIT_RUN_IRAM */ - -/* Mark the end of the RTC heap (top of the RTC region) */ - -_ertcheap = 0x50001fff; diff --git a/boards/risc-v/esp32c3/common/scripts/kernel-space.ld b/boards/risc-v/esp32c3/common/scripts/kernel-space.ld deleted file mode 100644 index 014ad10ecb047..0000000000000 --- a/boards/risc-v/esp32c3/common/scripts/kernel-space.ld +++ /dev/null @@ -1,230 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/common/scripts/kernel-space.ld - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Provide these so there is no need for using config files for this */ - -__uirom_start = ORIGIN(UIROM); -__uirom_size = LENGTH(UIROM); -__uirom_end = ORIGIN(UIROM) + LENGTH(UIROM); -__udrom_start = ORIGIN(UDROM); -__udrom_size = LENGTH(UDROM); -__udrom_end = ORIGIN(UDROM) + LENGTH(UDROM); -__uiram_start = ORIGIN(UIRAM); -__uiram_size = LENGTH(UIRAM); -__uiram_end = ORIGIN(UIRAM) + LENGTH(UIRAM); -__udram_start = ORIGIN(UDRAM); -__udram_size = LENGTH(UDRAM); -__udram_end = ORIGIN(UDRAM) + LENGTH(UDRAM); - -/* Provide the kernel boundaries as well */ - -__kirom_start = ORIGIN(KIROM); -__kirom_size = LENGTH(KIROM); -__kdrom_start = ORIGIN(KDROM); -__kdrom_size = LENGTH(KDROM); -__kiram_start = ORIGIN(KIRAM); -__kiram_size = LENGTH(KIRAM); -__kiram_end = ORIGIN(KIRAM) + LENGTH(KIRAM); -__kdram_start = ORIGIN(KDRAM); -__kdram_size = LENGTH(KDRAM); -__kdram_end = ORIGIN(KDRAM) + LENGTH(KDRAM); - -ENTRY(_stext) - -SECTIONS -{ - .iram0.text : - { - _iram_start = ABSOLUTE(.); - - __vectors_start = ABSOLUTE(.); - - /* Vectors go to start of IRAM */ - - KEEP(*(.exception_vectors.text)); - . = ALIGN(4); - - __vectors_end = ABSOLUTE(.); - - *(.iram1) - *(.iram1.*) - - *libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*) - - *(.wifi0iram .wifi0iram.*) - *(.wifirxiram .wifirxiram.*) - *(.wifislpiram .wifislpiram.*) - *(.wifislprxiram .wifislprxiram.*) - - _iram_end = ABSOLUTE(.); - } >KIRAM - - /* This section is required to skip .iram0.text area because iram0_0_seg - * and dram0_0_seg reflect the same address space on different buses. - */ - - .dram0.dummy (NOLOAD): - { - . = ORIGIN(KDRAM) + _iram_end - _iram_start; - } >KDRAM - - /* Shared RAM */ - - .dram0.bss (NOLOAD) : - { - . = ALIGN (8); - _sbss = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.share.mem) - *(.gnu.linkonce.b.*) - *(COMMON) - - . = ALIGN (8); - _ebss = ABSOLUTE(.); - } >KDRAM - - .noinit (NOLOAD): - { - /* This section contains data that is not initialized during load, - * or during the application's initialization sequence. - */ - - *(.noinit) - *(.noinit.*) - } >KDRAM - - .dram0.data : - { - _sdata = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) - __global_pointer$ = . + 0x800; - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - *(.jcr) - *(.dram1) - *(.dram1.*) - . = ALIGN(4); - _edata = ABSOLUTE(.); - - /* Heap starts at the end of .data */ - - _sheap = ABSOLUTE(.); - } >KDRAM - - .flash.text : - { - _stext = .; - - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.fini.literal) - *(.fini) - *(.gnu.version) - _etext = .; - - /* Similar to _iram_start, this symbol goes here so it is - * resolved by addr2line in preference to the first symbol in - * the flash.text segment. - */ - - _flash_cache_start = ABSOLUTE(0); - } >KIROM - - .flash_rodata_dummy (NOLOAD): - { - . = ALIGN(ALIGNOF(.flash.text)); - . = . + SIZEOF(.flash.text); - . = ALIGN(0x10000) + 0x20; - } >KDROM - - .flash.rodata : ALIGN(0x10) - { - _srodata = ABSOLUTE(.); - - *(.rodata) - *(.rodata.*) - - *(.srodata.*) - - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table .gcc_except_table.*) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - . = (. + 3) & ~ 3; - __eh_frame = ABSOLUTE(.); - KEEP(*(.eh_frame)) - . = (. + 7) & ~ 3; - - /* C++ constructor and destructor tables: - * RISC-V GCC is configured with --enable-initfini-array so it emits an - * .init_array section instead. - */ - - _sinit = ABSOLUTE(.); - KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)) - KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array)) - _einit = ABSOLUTE(.); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - - /* C++ exception handlers table: */ - - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - _erodata = ABSOLUTE(.); - - /* Literals are also RO data. */ - - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - } >KDROM -} diff --git a/boards/risc-v/esp32c3/common/scripts/legacy_sections.ld b/boards/risc-v/esp32c3/common/scripts/legacy_sections.ld deleted file mode 100644 index 41a03c4824c59..0000000000000 --- a/boards/risc-v/esp32c3/common/scripts/legacy_sections.ld +++ /dev/null @@ -1,260 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/common/scripts/legacy_sections.ld - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Default entry point: */ - -ENTRY(__start); - -SECTIONS -{ - .iram0.text : - { - _iram_start = ABSOLUTE(.); - - /* Vectors go to start of IRAM */ - - KEEP(*(.exception_vectors.text)); - . = ALIGN(4); - - *(.iram1) - *(.iram1.*) - - *libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*) - - *(.wifi0iram .wifi0iram.*) - *(.wifirxiram .wifirxiram.*) - *(.wifislpiram .wifislpiram.*) - *(.wifislprxiram .wifislprxiram.*) - - } >iram0_0_seg - - /* This section is required to skip .iram0.text area because iram0_0_seg - * and dram0_0_seg reflect the same address space on different buses. - */ - - .dram0.dummy (NOLOAD): - { - . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; - } >dram0_0_seg - - /* Shared RAM */ - - .dram0.bss (NOLOAD) : - { - . = ALIGN (8); - _sbss = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.share.mem) - *(.gnu.linkonce.b.*) - *(COMMON) - - . = ALIGN (8); - _ebss = ABSOLUTE(.); - } >dram0_0_seg - - .noinit (NOLOAD): - { - /* This section contains data that is not initialized during load, - * or during the application's initialization sequence. - */ - - *(.noinit) - *(.noinit.*) - } >dram0_0_seg - - .dram0.data : - { - _sdata = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) - __global_pointer$ = . + 0x800; - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - *(.jcr) - *(.dram1) - *(.dram1.*) - . = ALIGN(4); - _edata = ABSOLUTE(.); - - /* Heap starts at the end of .data */ - - _sheap = ABSOLUTE(.); - } >dram0_0_seg - - .flash.text : - { - _stext = .; - - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.fini.literal) - *(.fini) - *(.gnu.version) - _etext = .; - - /* Similar to _iram_start, this symbol goes here so it is - * resolved by addr2line in preference to the first symbol in - * the flash.text segment. - */ - - _flash_cache_start = ABSOLUTE(0); - } >default_code_seg - - .flash_rodata_dummy (NOLOAD): - { - . = SIZEOF(.flash.text); - . = ALIGN(0x10000) + 0x20; - } >drom0_0_seg - - .flash.rodata : ALIGN(0x10) - { - _srodata = ABSOLUTE(.); - - *(.rodata) - *(.rodata.*) - - *(.srodata.*) - - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table .gcc_except_table.*) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - . = (. + 3) & ~ 3; - __eh_frame = ABSOLUTE(.); - KEEP(*(.eh_frame)) - . = (. + 7) & ~ 3; - - /* C++ constructor and destructor tables: - * RISC-V GCC is configured with --enable-initfini-array so it emits an - * .init_array section instead. - */ - - _sinit = ABSOLUTE(.); - KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)) - KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array)) - _einit = ABSOLUTE(.); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - - /* C++ exception handlers table: */ - - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - _erodata = ABSOLUTE(.); - - /* Literals are also RO data. */ - - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - } >default_rodata_seg - - /* Marks the end of IRAM code segment */ - - .iram0.text_end (NOLOAD) : - { - . = ALIGN (16); - } >iram0_0_seg - - .iram0.data : - { - . = ALIGN(16); - *(.iram.data) - *(.iram.data*) - } >iram0_0_seg - - .iram0.bss (NOLOAD) : - { - . = ALIGN(16); - *(.iram.bss) - *(.iram.bss*) - - . = ALIGN(16); - _iram_end = ABSOLUTE(.); - } >iram0_0_seg - - /* RTC fast memory holds RTC wake stub code !*/ - - .rtc.text : - { - . = ALIGN(4); - *(.rtc.literal .rtc.text) - } >rtc_seg - - /* This section is required to skip rtc.text area because the text and - * data segments reflect the same address space on different buses. - */ - - .rtc.dummy : - { - . = SIZEOF(.rtc.text); - } >rtc_seg - - /* RTC BSS section. */ - - .rtc.bss (NOLOAD) : - { - *(.rtc.bss) - } >rtc_seg - - /* RTC data section holds RTC wake stub data/rodata. */ - - .rtc.data : - { - *(.rtc.data) - *(.rtc.rodata) - - /* Whatever is left from the RTC memory is used as a special heap. */ - - _srtcheap = ABSOLUTE(.); - - } >rtc_seg -} - diff --git a/boards/risc-v/esp32c3/common/scripts/user-space.ld b/boards/risc-v/esp32c3/common/scripts/user-space.ld deleted file mode 100644 index 543bac4a1349a..0000000000000 --- a/boards/risc-v/esp32c3/common/scripts/user-space.ld +++ /dev/null @@ -1,221 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/common/scripts/user-space.ld - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -SECTIONS -{ - .metadata : - { - /* DROM metadata: - * - Destination address (VMA) for DROM region - * - Flash offset (LMA) for start of DROM region - * - Size of DROM region - */ - - LONG(ADDR(.userspace)) - LONG(LOADADDR(.userspace)) - LONG(SIZEOF(.userspace) + SIZEOF(.rodata)) - - /* IROM metadata: - * - Destination address (VMA) for IROM region - * - Flash offset (LMA) for start of IROM region - * - Size of IROM region - */ - - LONG(ADDR(.text)) - LONG(LOADADDR(.text)) - LONG(SIZEOF(.text)) - } >metadata - - /* section info */ - - __ld_uirom_start = ORIGIN(UIROM); - __ld_uirom_size = LENGTH(UIROM); - __ld_uirom_end = ORIGIN(UIROM) + LENGTH(UIROM); - __ld_udrom_start = ORIGIN(UDROM); - __ld_udrom_size = LENGTH(UDROM); - __ld_udrom_end = ORIGIN(UDROM) + LENGTH(UDROM); - __ld_uiram_start = ORIGIN(UIRAM); - __ld_uiram_size = LENGTH(UIRAM); - __ld_uiram_end = ORIGIN(UIRAM) + LENGTH(UIRAM); - __ld_udram_start = ORIGIN(UDRAM); - __ld_udram_size = LENGTH(UDRAM); - __ld_udram_end = ORIGIN(UDRAM) + LENGTH(UDRAM); - - _eronly = LOADADDR(.data); - - .userspace : { - *(.userspace) - } >UDROM AT>ROM - - /* Output sections for the Userspace image are given standard names, so - * instead of the Espressif-usual ".flash.text" we name it as ".text". - * The motivation is to ease debugging with GDB when loading symbols from - * both Kernel and User images since GDB's "add-symbol-file" command - * expects to find a .text section at the provided offset. - */ - - .rodata : - { - _srodata = ABSOLUTE(.); - - *(.rodata) - *(.rodata.*) - - *(.srodata.*) - - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.gnu.linkonce.r.*) - *(.rodata1) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table .gcc_except_table.*) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - . = (. + 3) & ~ 3; - __eh_frame = ABSOLUTE(.); - KEEP(*(.eh_frame)) - . = (. + 7) & ~ 3; - - /* C++ constructor and destructor tables: - * RISC-V GCC is configured with --enable-initfini-array so it emits an - * .init_array section instead. - */ - - _sinit = ABSOLUTE(.); - KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)) - KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array)) - _einit = ABSOLUTE(.); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - - /* C++ exception handlers table: */ - - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - _erodata = ABSOLUTE(.); - - /* Literals are also RO data. */ - - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - } >UDROM AT>ROM - - .iram0.text : - { - _iram_start = ABSOLUTE(.); - - *(.iram1) - *(.iram1.*) - - _iram_end = ABSOLUTE(.); - } >UIRAM AT>ROM - - /* This section is required to skip .iram0.text area because iram0_0_seg - * and dram0_0_seg reflect the same address space on different buses. - */ - - .dram0.dummy (NOLOAD): - { - . = ORIGIN(UDRAM) + _iram_end - _iram_start; - } >UDRAM - - /* Shared RAM */ - - .bss (NOLOAD) : - { - . = ALIGN (8); - _sbss = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.share.mem) - *(.gnu.linkonce.b.*) - *(COMMON) - - . = ALIGN (8); - _ebss = ABSOLUTE(.); - } >UDRAM - - .noinit (NOLOAD): - { - /* This section contains data that is not initialized during load, - * or during the application's initialization sequence. - */ - - *(.noinit) - *(.noinit.*) - } >UDRAM - - .data : - { - _sdata = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - *(.jcr) - *(.dram1) - *(.dram1.*) - . = ALIGN(4); - _edata = ABSOLUTE(.); - } >UDRAM AT>ROM - - .flash_text_dummy (NOLOAD) : ALIGN(0x00010000) - { - . = SIZEOF(.userspace) + SIZEOF(.rodata); - } >UIROM - - .text : ALIGN(0x00010000) - { - _stext = .; - - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.fini.literal) - *(.fini) - *(.gnu.version) - _etext = .; - } >UIROM AT>ROM -} diff --git a/boards/risc-v/esp32c3/common/src/Make.defs b/boards/risc-v/esp32c3/common/src/Make.defs index 571977ba284b7..ab73484da0834 100644 --- a/boards/risc-v/esp32c3/common/src/Make.defs +++ b/boards/risc-v/esp32c3/common/src/Make.defs @@ -20,76 +20,24 @@ ifeq ($(CONFIG_ARCH_BOARD_COMMON),y) -ifeq ($(CONFIG_ESP32C3_SPI),y) - CSRCS += esp32c3_board_spi.c +ifeq ($(CONFIG_ESPRESSIF_LEDC),y) + CSRCS += esp_board_ledc.c endif -ifeq ($(CONFIG_SPI_DRIVER),y) - CSRCS += esp32c3_board_spidev.c +ifeq ($(CONFIG_ESP_RMT),y) + CSRCS += esp_board_rmt.c endif -ifeq ($(CONFIG_SPI_SLAVE_DRIVER),y) - CSRCS += esp32c3_board_spislavedev.c +ifeq ($(CONFIG_ESPRESSIF_SPIFLASH),y) + CSRCS += esp_board_spiflash.c endif -ifeq ($(CONFIG_ESP32C3_SPIFLASH),y) - CSRCS += esp32c3_board_spiflash.c +ifeq ($(CONFIG_ESPRESSIF_TWAI),y) + CSRCS += esp_board_twai.c endif -ifeq ($(CONFIG_I2C_DRIVER),y) - CSRCS += esp32c3_board_i2c.c -endif - -ifeq ($(CONFIG_ESP32C3_WIRELESS),y) - CSRCS += esp32c3_board_wlan.c -endif - -ifeq ($(CONFIG_CAN),y) - CSRCS += esp32c3_board_twai.c -endif - -ifeq ($(CONFIG_WATCHDOG),y) - CSRCS += esp32c3_board_wdt.c -endif - -ifeq ($(CONFIG_ONESHOT),y) - CSRCS += esp32c3_board_oneshot.c -endif - -ifeq ($(CONFIG_PWM),y) - CSRCS += esp32c3_board_ledc.c -endif - -ifeq ($(CONFIG_ADC),y) - CSRCS += esp32c3_board_adc.c -endif - -ifeq ($(CONFIG_SENSORS_BMP180),y) - CSRCS += esp32c3_board_bmp180.c -endif - -ifeq ($(CONFIG_LCD_ST7735),y) - CSRCS += esp32c3_board_st7735.c -endif - -ifeq ($(CONFIG_LCD_ST7789),y) - CSRCS += esp32c3_board_st7789.c -endif - -ifeq ($(CONFIG_LCD_GC9A01),y) - CSRCS += esp32c3_board_gc9a01.c -endif - -ifeq ($(CONFIG_SENSORS_APDS9960),y) - CSRCS += esp32c3_board_apds9960.c -endif - -ifeq ($(CONFIG_LCD_APA102),y) - CSRCS += esp32c3_board_apa102.c -endif - -ifeq ($(CONFIG_MPU60X0_I2C),y) - CSRCS += esp32c3_board_mpu60x0_i2c.c +ifeq ($(CONFIG_ESPRESSIF_WIFI),y) + CSRCS += esp_board_wlan.c endif DEPPATH += --dep-path src diff --git a/boards/risc-v/esp32c3/common/src/esp_board_ledc.c b/boards/risc-v/esp32c3/common/src/esp_board_ledc.c new file mode 100644 index 0000000000000..907ac1660800c --- /dev/null +++ b/boards/risc-v/esp32c3/common/src/esp_board_ledc.c @@ -0,0 +1,147 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/common/src/esp_board_ledc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include + +#include "espressif/esp_ledc.h" + +#include "esp_board_ledc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LEDC_TIMER0 0 +#define LEDC_TIMER1 1 +#define LEDC_TIMER2 2 +#define LEDC_TIMER3 3 + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ledc_setup + * + * Description: + * Initialize LEDC PWM and register the PWM device. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int board_ledc_setup(void) +{ + int ret = OK; + struct pwm_lowerhalf_s *pwm; + +#ifdef CONFIG_ESPRESSIF_LEDC_TIMER0 + pwm = esp_ledc_init(LEDC_TIMER0); + if (!pwm) + { + syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 0 lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ESPRESSIF_LEDC_TIMER1 + pwm = esp_ledc_init(LEDC_TIMER1); + if (!pwm) + { + syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 1 lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm1" */ + + ret = pwm_register("/dev/pwm1", pwm); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ESPRESSIF_LEDC_TIMER2 + pwm = esp_ledc_init(LEDC_TIMER2); + if (!pwm) + { + syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 2 lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm2" */ + + ret = pwm_register("/dev/pwm2", pwm); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ESPRESSIF_LEDC_TIMER3 + pwm = esp_ledc_init(LEDC_TIMER3); + if (!pwm) + { + syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 3 lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm3" */ + + ret = pwm_register("/dev/pwm3", pwm); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + + return ret; +} + diff --git a/boards/risc-v/esp32c3/common/src/esp_board_rmt.c b/boards/risc-v/esp32c3/common/src/esp_board_rmt.c new file mode 100644 index 0000000000000..0d15d2e77cf70 --- /dev/null +++ b/boards/risc-v/esp32c3/common/src/esp_board_rmt.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/common/src/esp_board_rmt.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#ifdef CONFIG_WS2812_NON_SPI_DRIVER +#include + +#include "espressif/esp_ws2812.h" +#endif + +#include "espressif/esp_rmt.h" + +#ifdef CONFIG_ESP_RMT + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_rmt_rxinitialize + * + * Description: + * Initialize the RMT peripheral and register an RX device. + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the RX channel + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_rmt_rxinitialize(int ch, int pin) +{ + int ret; + + struct rmt_dev_s *rmt = esp_rmt_rx_init(ch, pin); + + ret = rmtchar_register(rmt); + if (ret < 0) + { + rmterr("ERROR: rmtchar_register failed: %d\n", ret); + return ret; + } + + return ret; +} + +/**************************************************************************** + * Name: board_rmt_txinitialize + * + * Description: + * Initialize the RMT peripheral and register an TX device. + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the TX channel + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_rmt_txinitialize(int ch, int pin) +{ + int ret; + struct rmt_dev_s *rmt; +#ifdef CONFIG_WS2812_NON_SPI_DRIVER + struct ws2812_dev_s *led; +#endif + + rmt = esp_rmt_tx_init(ch, pin); + if (rmt == NULL) + { + rmterr("ERROR: esp_rmt_tx_init failed\n"); + return -ENODEV; + } + + ret = rmtchar_register(rmt); + if (ret < 0) + { + rmterr("ERROR: rmtchar_register failed: %d\n", ret); + return ret; + } + +#ifdef CONFIG_WS2812_NON_SPI_DRIVER + led = esp_ws2812_setup("/dev/leds0", rmt, CONFIG_WS2812_LED_COUNT, false); + if (led == NULL) + { + rmterr("ERROR: esp_ws2812_setup failed\n"); + return -ENODEV; + } +#endif + + return ret; +} +#endif diff --git a/boards/risc-v/esp32c3/common/src/esp_board_spiflash.c b/boards/risc-v/esp32c3/common/src/esp_board_spiflash.c new file mode 100644 index 0000000000000..7e1c40ccb7f82 --- /dev/null +++ b/boards/risc-v/esp32c3/common/src/esp_board_spiflash.c @@ -0,0 +1,417 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/common/src/esp_board_spiflash.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "inttypes.h" +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#ifdef CONFIG_BCH +#include +#endif + +#include "espressif/esp_spiflash.h" +#include "espressif/esp_spiflash_mtd.h" + +#include "esp_board_spiflash.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: setup_smartfs + * + * Description: + * Provide a block driver wrapper around MTD partition and mount a + * SMART FS over it. + * + * Parameters: + * smartn - Number used to register the mtd partition: /dev/smartx, where + * x = smartn. + * mtd - Pointer to a pre-allocated mtd partition. + * mnt_pt - Mount point + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +#if defined (CONFIG_ESPRESSIF_SPIFLASH_SMARTFS) +static int setup_smartfs(int smartn, struct mtd_dev_s *mtd, + const char *mnt_pt) +{ + int ret = OK; + char path[22]; + + ret = smart_initialize(smartn, mtd, NULL); + if (ret < 0) + { + syslog(LOG_INFO, "smart_initialize failed, " + "Trying to erase first...\n"); + ret = mtd->ioctl(mtd, MTDIOC_BULKERASE, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: ioctl(BULKERASE) failed: %d\n", ret); + return ret; + } + + syslog(LOG_INFO, "Erase successful, initializing it again.\n"); + ret = smart_initialize(smartn, mtd, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: smart_initialize failed: %d\n", ret); + return ret; + } + } + + if (mnt_pt != NULL) + { + snprintf(path, sizeof(path), "/dev/smart%d", smartn); + + ret = nx_mount(path, mnt_pt, "smartfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the FS volume: %d\n", ret); + if (ret == -ENODEV) + { + syslog(LOG_WARNING, "Smartfs seems unformatted. " + "Did you run 'mksmartfs /dev/smart%d'?\n", smartn); + } + + return ret; + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: setup_littlefs + * + * Description: + * Register a mtd driver and mount a Little FS over it. + * + * Parameters: + * path - Path name used to register the mtd driver. + * mtd - Pointer to a pre-allocated mtd partition. + * mnt_pt - Mount point + * priv - Privileges + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +#if defined (CONFIG_ESPRESSIF_SPIFLASH_LITTLEFS) +static int setup_littlefs(const char *path, struct mtd_dev_s *mtd, + const char *mnt_pt, int priv) +{ + int ret = OK; + + ret = register_mtddriver(path, mtd, priv, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); + return ERROR; + } + + if (mnt_pt != NULL) + { + ret = nx_mount(path, mnt_pt, "littlefs", 0, NULL); + if (ret < 0) + { + ret = nx_mount(path, mnt_pt, "littlefs", 0, "forceformat"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the FS volume: %d\n", + ret); + return ret; + } + } + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: setup_spiffs + * + * Description: + * Register a mtd driver and mount a SPIFFS over it. + * + * Parameters: + * path - Path name used to register the mtd driver. + * mtd - Pointer to a pre-allocated mtd partition. + * mnt_pt - Mount point + * priv - Privileges + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +#if defined (CONFIG_ESPRESSIF_SPIFLASH_SPIFFS) +static int setup_spiffs(const char *path, struct mtd_dev_s *mtd, + const char *mnt_pt, int priv) +{ + int ret = OK; + + ret = register_mtddriver(path, mtd, priv, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); + return ERROR; + } + + if (mnt_pt != NULL) + { + ret = nx_mount(path, mnt_pt, "spiffs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the FS volume: %d\n", ret); + return ret; + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: setup_nxffs + * + * Description: + * Register a mtd driver and mount a NXFFS over it. + * + * Parameters: + * mtd - Pointer to a pre-allocated mtd partition. + * mnt_pt - Mount point + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +#if defined (CONFIG_ESPRESSIF_SPIFLASH_NXFFS) +static int setup_nxffs(struct mtd_dev_s *mtd, const char *mnt_pt) +{ + int ret = OK; + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: NXFFS init failed: %d\n", ret); + return ret; + } + + if (mnt_pt != NULL) + { + ret = nx_mount(NULL, mnt_pt, "nxffs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the FS volume: %d\n", ret); + return ret; + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: init_storage_partition + * + * Description: + * Initialize partition that is dedicated to general use. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int init_storage_partition(void) +{ + int ret = OK; + struct mtd_dev_s *mtd; + + mtd = esp_spiflash_alloc_mtdpart(CONFIG_ESPRESSIF_STORAGE_MTD_OFFSET, + CONFIG_ESPRESSIF_STORAGE_MTD_SIZE); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: Failed to alloc MTD partition of SPI Flash\n"); + return ERROR; + } + +#if defined (CONFIG_ESPRESSIF_SPIFLASH_SMARTFS) + + ret = setup_smartfs(0, mtd, "/data"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to setup smartfs\n"); + return ret; + } + +#elif defined (CONFIG_ESPRESSIF_SPIFLASH_NXFFS) + + ret = setup_nxffs(mtd, "/data"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to setup nxffs\n"); + return ret; + } + +#elif defined (CONFIG_ESPRESSIF_SPIFLASH_LITTLEFS) + + const char *path = "/dev/espflash"; + ret = setup_littlefs(path, mtd, "/data", 0755); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to setup littlefs\n"); + return ret; + } + +#elif defined (CONFIG_ESPRESSIF_SPIFLASH_SPIFFS) + + const char *path = "/dev/espflash"; + ret = setup_spiffs(path, mtd, "/data", 0755); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to setup spiffs\n"); + return ret; + } + +#elif defined (CONFIG_ESPRESSIF_SPIFLASH_MTD_CONFIG) + +# if defined (CONFIG_TESTING_MTD_CONFIG_FAIL_SAFE) + + /* To test power-loss resilient kv system, + * we write possible power-loss flash layout into flash + * then start kv system to see if it recovers. + * To do so, we need a mtd driver so that test code can + * write into flash. + */ + + const char *path = CONFIG_TESTING_MTD_CONFIG_FAIL_SAFE_MOUNTPT_NAME; + ret = register_mtddriver(path, mtd, 0777, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); + return ret; + } + +# else + + ret = mtdconfig_register(mtd); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to setup mtd config\n"); + return ret; + } + +# endif + +#else + + ret = register_mtddriver("/dev/espflash", mtd, 0755, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); + return ret; + } + +#endif + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_spiflash_init + * + * Description: + * Initialize the SPI Flash and register the MTD device. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int board_spiflash_init(void) +{ + int ret = OK; + + esp_spiflash_init(); + + ret = init_storage_partition(); + if (ret < 0) + { + return ret; + } + + return ret; +} + diff --git a/boards/risc-v/esp32c3/common/src/esp_board_twai.c b/boards/risc-v/esp32c3/common/src/esp_board_twai.c new file mode 100644 index 0000000000000..70e560978294e --- /dev/null +++ b/boards/risc-v/esp32c3/common/src/esp_board_twai.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/common/src/esp_board_twai.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "espressif/esp_twai.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define TWAI_PORT 0 + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_twai_setup + * + * Description: + * Initialize TWAI and register the TWAI device + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int board_twai_setup(void) +{ +#ifdef CONFIG_ESPRESSIF_TWAI + struct can_dev_s *twai; + int ret; + + /* Call esp_twaiinitialize() to get an instance of the TWAI + * interface + * */ + + twai = esp_twaiinitialize(TWAI_PORT); + if (twai == NULL) + { + canerr("ERROR: Failed to get TWAI interface\n"); + return -ENODEV; + } + + /* Register the TWAI driver at "/dev/can0" */ + + ret = can_register("/dev/can0", twai); + if (ret < 0) + { + canerr("ERROR: TWAI0 register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/risc-v/esp32c3/common/src/esp_board_wlan.c b/boards/risc-v/esp32c3/common/src/esp_board_wlan.c new file mode 100644 index 0000000000000..24a7fe17b0032 --- /dev/null +++ b/boards/risc-v/esp32c3/common/src/esp_board_wlan.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/common/src/esp_board_wlan.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "espressif/esp_wlan.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_wlan_init + * + * Description: + * Configure the wireless subsystem. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int board_wlan_init(void) +{ + int ret = OK; + +#ifdef ESP_WLAN_HAS_STA + ret = esp_wlan_sta_initialize(); + if (ret) + { + wlerr("ERROR: Failed to initialize Wi-Fi station\n"); + return ret; + } +#endif /* ESP_WLAN_HAS_STA */ + +#ifdef ESP_WLAN_HAS_SOFTAP + ret = esp_wlan_softap_initialize(); + if (ret) + { + wlerr("ERROR: Failed to initialize Wi-Fi softAP\n"); + return ret; + } +#endif /* ESP_WLAN_HAS_SOFTAP */ + + return ret; +} + diff --git a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/configs/brickmatch/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/configs/brickmatch/defconfig deleted file mode 100644 index f4f86c45d11d1..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/configs/brickmatch/defconfig +++ /dev/null @@ -1,71 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ESP32C3_UART0 is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit-rust-1" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT_RUST1=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3MINI1=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_I2C=y -CONFIG_DEBUG_I2C_ERROR=y -CONFIG_DEBUG_I2C_WARN=y -CONFIG_DEV_ZERO=y -CONFIG_DRIVERS_VIDEO=y -CONFIG_ESP32C3_DMA=y -CONFIG_ESP32C3_GPIO_IRQ=y -CONFIG_ESP32C3_I2C0=y -CONFIG_ESP32C3_I2C0_SCLPIN=8 -CONFIG_ESP32C3_I2C0_SDAPIN=10 -CONFIG_ESP32C3_SPI2=y -CONFIG_ESP32C3_SPI2_CLKPIN=4 -CONFIG_ESP32C3_SPI2_CSPIN=0 -CONFIG_ESP32C3_SPI2_DMA=y -CONFIG_ESP32C3_SPI2_MISOPIN=6 -CONFIG_ESP32C3_SPI2_MOSIPIN=5 -CONFIG_ESP32C3_USBSERIAL=y -CONFIG_EXAMPLES_FB=y -CONFIG_FS_PROCFS=y -CONFIG_GAMES_BRICKMATCH=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_APA102=y -CONFIG_LCD_APA102_FREQUENCY=10000000 -CONFIG_LCD_DEV=y -CONFIG_LCD_FRAMEBUFFER=y -CONFIG_LCD_NOGETRUN=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_APDS9960=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_VIDEO_FB=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/configs/nsh/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/configs/nsh/defconfig deleted file mode 100644 index c4a9babc85cf3..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/configs/nsh/defconfig +++ /dev/null @@ -1,42 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ESP32C3_UART0 is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit-rust-1" -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT_RUST1=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3MINI1=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESP32C3_USBSERIAL=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/include/board.h b/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/include/board.h deleted file mode 100644 index a0a65c219cb75..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/include/board.h +++ /dev/null @@ -1,50 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit-rust-1/include/board.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_RUST1_INCLUDE_BOARD_H -#define __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_RUST1_INCLUDE_BOARD_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define NUM_BUTTONS 1 - -#define LED_STARTED 0 /* ON */ -#define LED_HEAPALLOCATE 1 /* ON */ -#define LED_IRQSENABLED 2 /* N/A */ -#define LED_STACKCREATED 3 /* N/A */ -#define LED_INIRQ 4 /* N/A */ -#define LED_SIGNAL 5 /* N/A */ -#define LED_ASSERTION 6 /* N/A */ -#define LED_PANIC 7 /* Blinking */ -#define LED_CPU 8 /* N/A */ - -/* Clocking *****************************************************************/ - -#define BOARD_XTAL_FREQUENCY 40000000 - -/* GPIO pins used by the GPIO Subsystem */ - -#define BOARD_NGPIOOUT 2 /* Amount of GPIO Output pins */ -#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ - -#endif /* __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_RUST1_INCLUDE_BOARD_H */ - diff --git a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/include/board_memorymap.h b/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/include/board_memorymap.h deleted file mode 100644 index a3a55023b45bf..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/include/board_memorymap.h +++ /dev/null @@ -1,116 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit-rust-1/include/board_memorymap.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_RUST1_INCLUDE_BOARD_MEMORYMAP_H -#define __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_RUST1_INCLUDE_BOARD_MEMORYMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Kernel ROM */ - -#define KIROM_START (uintptr_t)__kirom_start -#define KIROM_SIZE (uintptr_t)__kirom_size -#define KDROM_START (uintptr_t)__kdrom_start -#define KDROM_SIZE (uintptr_t)__kdrom_size - -/* Kernel RAM */ - -#define KIRAM_START (uintptr_t)__kiram_start -#define KIRAM_SIZE (uintptr_t)__kiram_size -#define KIRAM_END (uintptr_t)__kiram_end -#define KDRAM_START (uintptr_t)__kdram_start -#define KDRAM_SIZE (uintptr_t)__kdram_size -#define KDRAM_END (uintptr_t)__kdram_end - -/* Exception vectors */ - -#define VECTORS_START (uintptr_t)__vectors_start -#define VECTORS_END (uintptr_t)__vectors_end - -/* User ROM */ - -#define UIROM_START (uintptr_t)__uirom_start -#define UIROM_SIZE (uintptr_t)__uirom_size -#define UIROM_END (uintptr_t)__uirom_end -#define UDROM_START (uintptr_t)__udrom_start -#define UDROM_SIZE (uintptr_t)__udrom_size -#define UDROM_END (uintptr_t)__udrom_end - -/* User RAM */ - -#define UIRAM_START (uintptr_t)__uiram_start -#define UIRAM_SIZE (uintptr_t)__uiram_size -#define UIRAM_END (uintptr_t)__uiram_end -#define UDRAM_START (uintptr_t)__udram_start -#define UDRAM_SIZE (uintptr_t)__udram_size -#define UDRAM_END (uintptr_t)__udram_end - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Kernel ROM (RX) */ - -extern uint8_t __kirom_start[]; -extern uint8_t __kirom_size[]; -extern uint8_t __kdrom_start[]; -extern uint8_t __kdrom_size[]; - -/* Kernel RAM (RW) */ - -extern uint8_t __kiram_start[]; -extern uint8_t __kiram_size[]; -extern uint8_t __kiram_end[]; -extern uint8_t __kdram_start[]; -extern uint8_t __kdram_size[]; -extern uint8_t __kdram_end[]; - -/* Exception vectors */ - -extern uint8_t __vectors_start[]; -extern uint8_t __vectors_end[]; - -/* User ROM (RX) */ - -extern uint8_t __uirom_start[]; -extern uint8_t __uirom_size[]; -extern uint8_t __uirom_end[]; -extern uint8_t __udrom_start[]; -extern uint8_t __udrom_size[]; -extern uint8_t __udrom_end[]; - -/* User RAM (RW) */ - -extern uint8_t __uiram_start[]; -extern uint8_t __uiram_size[]; -extern uint8_t __uiram_end[]; -extern uint8_t __udram_start[]; -extern uint8_t __udram_size[]; -extern uint8_t __udram_end[]; - -#endif /* __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_RUST1_INCLUDE_BOARD_MEMORYMAP_H */ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/include/nsh_romfsimg.h b/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/include/nsh_romfsimg.h deleted file mode 100644 index f09b3d9ef73ce..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/include/nsh_romfsimg.h +++ /dev/null @@ -1,25 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit-rust-1/include/nsh_romfsimg.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_RUST1_INCLUDE_NSH_ROMFSIMG_H -#define __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_RUST1_INCLUDE_NSH_ROMFSIMG_H -extern const unsigned char romfs_img[]; -extern const unsigned int romfs_img_len; -#endif diff --git a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/scripts/Make.defs b/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/scripts/Make.defs deleted file mode 100644 index 9e40d54f62446..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/scripts/Make.defs +++ /dev/null @@ -1,66 +0,0 @@ -############################################################################ -# boards/risc-v/esp32c3/esp32c3-devkit-rust-1/scripts/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -########################################################################### - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/tools/esp32c3/Config.mk -include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs - -ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32c3_rom.ld - -# Pick the linker scripts from the board level if they exist, if not -# pick the common linker scripts. - -ifeq ($(CONFIG_BUILD_PROTECTED),y) - ARCHSCRIPT += $(call FINDSCRIPT,protected_memory.ld) - ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld) -else - ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) - - ifeq ($(CONFIG_ESP32C3_APP_FORMAT_MCUBOOT),y) - ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) - else - ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) - endif -endif - -ARCHPICFLAGS = -fpic - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -# Loadable module definitions - -CMODULEFLAGS = $(CFLAGS) - -LDMODULEFLAGS = -melf32lriscv -r -e module_initialize -LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld) - -# ELF module definitions - -CELFFLAGS = $(CFLAGS) -CXXELFFLAGS = $(CXXFLAGS) - -LDELFFLAGS = -melf32lriscv -r -e main -LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)$(DELIM)binfmt$(DELIM)libelf$(DELIM)gnu-elf.ld) diff --git a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/Make.defs b/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/Make.defs deleted file mode 100644 index ee830b674d67c..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/Make.defs +++ /dev/null @@ -1,43 +0,0 @@ -############################################################################# -# boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/Makefile -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################# - -include $(TOPDIR)/Make.defs - -CSRCS = esp32c3_boot.c esp32c3_bringup.c - -ifeq ($(CONFIG_BOARDCTL),y) - CSRCS += esp32c3_appinit.c - - ifeq ($(CONFIG_BOARDCTL_RESET),y) - CSRCS += esp32c3_reset.c - endif -endif - -ifeq ($(CONFIG_ARCH_LEDS),y) - CSRCS += esp32c3_autoleds.c -endif - -ifeq ($(CONFIG_BOARDCTL_IOCTL),y) - CSRCS += esp32c3_ioctl.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_appinit.c b/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_appinit.c deleted file mode 100644 index d015d58a45f0a..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_appinit.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_appinit.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "esp32c3-devkit-rust-1.h" - -#ifdef CONFIG_BOARDCTL - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_app_initialize - * - * Description: - * Perform application specific initialization. This function is never - * called directly from application code, but only indirectly via the - * (non-standard) boardctl() interface using the command BOARDIOC_INIT. - * - * Input Parameters: - * arg - The boardctl() argument is passed to the board_app_initialize() - * implementation without modification. The argument has no - * meaning to NuttX; the meaning of the argument is a contract - * between the board-specific initialization logic and the - * matching application logic. The value could be such things as a - * mode enumeration value, a set of DIP switch settings, a - * pointer to configuration data read from a file or serial FLASH, - * or whatever you would like to do with it. Every implementation - * should accept zero/NULL as a default configuration. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure to indicate the nature of the failure. - * - ****************************************************************************/ - -int board_app_initialize(uintptr_t arg) -{ -#ifdef CONFIG_BOARD_LATE_INITIALIZE - /* Board initialization already performed by board_late_initialize() */ - - return OK; -#else - /* Perform board-specific initialization */ - - return esp32c3_bringup(); -#endif -} - -#endif /* CONFIG_BOARDCTL */ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_boot.c b/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_boot.c deleted file mode 100644 index 1057370794f76..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_boot.c +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_boot.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include "riscv_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c3_board_initialize - * - * Description: - * All ESP32-C3 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void esp32c3_board_initialize(void) -{ -#ifdef CONFIG_ARCH_PERF_EVENTS - up_perf_init(NULL); -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - esp32c3_bringup(); -} -#endif diff --git a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_bringup.c b/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_bringup.c deleted file mode 100644 index 638c2dc34ae37..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_bringup.c +++ /dev/null @@ -1,168 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_bringup.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "esp32c3_wlan.h" -#include "esp32c3_spiflash.h" -#include "esp32c3_partition.h" -#include "esp32c3-devkit-rust-1.h" - -#include "esp32c3_rtc.h" -#ifdef CONFIG_ESP32C3_EFUSE -# include "esp32c3_efuse.h" -#endif - -#ifdef CONFIG_ESP32C3_SHA_ACCELERATOR -# include "esp32c3_sha.h" -#endif - -#ifdef CONFIG_RTC_DRIVER -# include "esp32c3_rtc_lowerhalf.h" -#endif - -#ifdef CONFIG_ESP32C3_BLE -# include "esp32c3_ble.h" -#endif - -#include "esp32c3_board_apds9960.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c3_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y - * Called from board_late_initialize(). - * - * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y - * Called from the NSH library - * - ****************************************************************************/ - -int esp32c3_bringup(void) -{ - int ret; - -#if defined(CONFIG_ESP32C3_EFUSE) - ret = esp32c3_efuse_initialize("/dev/efuse"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to init EFUSE: %d\n", ret); - } -#endif - -#if defined(CONFIG_ESP32C3_SHA_ACCELERATOR) && \ - !defined(CONFIG_CRYPTO_CRYPTODEV_HARDWARE) - ret = esp32c3_sha_init(); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to initialize SHA: %d\n", ret); - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#ifdef CONFIG_FS_TMPFS - /* Mount the tmpfs file system */ - - ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount tmpfs at %s: %d\n", - CONFIG_LIBC_TMPDIR, ret); - } -#endif - -#ifdef CONFIG_RTC_DRIVER - /* Instantiate the ESP32-C3 RTC driver */ - - ret = esp32c3_rtc_driverinit(); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to Instantiate the RTC driver: %d\n", ret); - } -#endif - -#ifdef CONFIG_VIDEO_FB - /* Initialize and register the framebuffer driver */ - - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_APDS9960 - /* Register the APDS-9960 gesture sensor */ - - ret = board_apds9960_initialize(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_apds9960_initialize() failed: %d\n", - ret); - } -#endif - - /* If we got here then perhaps not all initialization was successful, but - * at least enough succeeded to bring-up NSH with perhaps reduced - * capabilities. - */ - - UNUSED(ret); - return OK; -} diff --git a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_ioctl.c b/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_ioctl.c deleted file mode 100644 index 49ff906c2f25d..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_ioctl.c +++ /dev/null @@ -1,72 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_ioctl.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#ifdef CONFIG_BOARDCTL_IOCTL - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_ioctl - * - * Description: - * The "landing site" for much of the boardctl() interface. Generic board- - * control functions invoked via ioctl() get routed through here. - * - * Since we don't do anything unusual at the moment, this function - * accomplishes nothing except avoid a missing-function linker error if - * CONFIG_BOARDCTL_IOCTL is selected. - * - * Input Parameters: - * cmd - IOCTL command being requested. - * arg - Arguments for the IOCTL. - * - * Returned Value: - * we don't yet support any boardctl IOCTLs. This function always returns - * -ENOTTY which is the standard IOCTL return value when a command is not - * supported - * - ****************************************************************************/ - -int board_ioctl(unsigned int cmd, uintptr_t arg) -{ - switch (cmd) - { - default: - return -ENOTTY; - } - - return OK; -} - -#endif /* CONFIG_BOARDCTL_IOCTL */ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_reset.c b/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_reset.c deleted file mode 100644 index cf9d29d1e1c23..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_reset.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit-rust-1/src/esp32c3_reset.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include "esp32c3_systemreset.h" - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value in this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - syslog(LOG_INFO, "reboot status=%d\n", status); - - switch (status) - { - case EXIT_SUCCESS: - up_shutdown_handler(); - break; - case CONFIG_BOARD_ASSERT_RESET_VALUE: - break; - default: - break; - } - - up_systemreset(); - - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/Kconfig b/boards/risc-v/esp32c3/esp32c3-devkit/Kconfig deleted file mode 100644 index 737c22452fa92..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/Kconfig +++ /dev/null @@ -1,64 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -if ARCH_BOARD_ESP32C3_DEVKIT - -if PM - -config PM_ALARM_SEC - int "PM_STANDBY delay (seconds)" - default 15 - depends on PM - ---help--- - Number of seconds to wait in PM_STANDBY before going to PM_STANDBY mode. - -config PM_ALARM_NSEC - int "PM_STANDBY delay (nanoseconds)" - default 0 - depends on PM - ---help--- - Number of additional nanoseconds to wait in PM_STANDBY before going to PM_STANDBY mode. - -config PM_SLEEP_WAKEUP_SEC - int "PM_SLEEP delay (seconds)" - default 20 - depends on PM - ---help--- - Number of seconds to wait in PM_SLEEP. - -config PM_SLEEP_WAKEUP_NSEC - int "PM_SLEEP delay (nanoseconds)" - default 0 - depends on PM - ---help--- - Number of additional nanoseconds to wait in PM_SLEEP. - -endif # PM - -config ESP32C3_DEVKIT_RUN_IRAM - bool "Run from IRAM" - default n - -config ESP32C3_STORAGE_MTD_ENCRYPT - bool "Encrypt Storage MTD partition" - default y - depends on ESP32C3_SECURE_FLASH_ENC_ENABLED - -config ESP32C3_STORAGE_MTD_OFFSET - hex "Storage MTD base address in SPI Flash" - default 0x180000 if !ESP32C3_HAVE_OTA_PARTITION - default 0x250000 if ESP32C3_HAVE_OTA_PARTITION - depends on ESP32C3_MTD - ---help--- - MTD base address in SPI Flash. - -config ESP32C3_STORAGE_MTD_SIZE - hex "Storage MTD size in SPI Flash" - default 0x100000 - depends on ESP32C3_MTD - ---help--- - MTD size in SPI Flash. - -endif # ARCH_BOARD_ESP32C3_DEVKIT diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/adc/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/adc/defconfig deleted file mode 100644 index d532e71d1157c..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/adc/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESP32C3_ADC1=y -CONFIG_ESP32C3_ADC1_CHANNEL0=y -CONFIG_EXAMPLES_ADC=y -CONFIG_EXAMPLES_ADC_GROUPSIZE=1 -CONFIG_EXAMPLES_ADC_SWTRIG=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/autopm/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/autopm/defconfig deleted file mode 100644 index 10551337083c6..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/autopm/defconfig +++ /dev/null @@ -1,68 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_IEEE80211=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_ESP32C3_AUTO_SLEEP=y -CONFIG_ESP32C3_WIFI=y -CONFIG_EXAMPLE_POWER_SAVE_MIN_MODEM=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=3072 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBC_MAX_EXITFUNS=1 -CONFIG_NAME_MAX=48 -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_PHY_IOCTL=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETINIT_DHCPC=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=1514 -CONFIG_NET_ICMP=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_TCP=y -CONFIG_NET_UDP=y -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LINELEN=64 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PTHREAD_MUTEX_TYPES=y -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SIG_DEFAULT=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_SYSTEM_DHCPC_RENEW=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TLS_TASK_NELEM=4 -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_WAPI=y -CONFIG_WIRELESS_WAPI_CMDTOOL=y -CONFIG_WIRELESS_WAPI_STACKSIZE=4096 diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/ble/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/ble/defconfig deleted file mode 100644 index 33db79264f859..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/ble/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -CONFIG_ALLOW_BSD_COMPONENTS=y -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BTSAK=y -CONFIG_BUILTIN=y -CONFIG_DRIVERS_BLUETOOTH=y -CONFIG_DRIVERS_IEEE80211=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_ESP32C3_BLE=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=3072 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_NAME_MAX=48 -CONFIG_NETDEV_LATEINIT=y -CONFIG_NET_BLUETOOTH=y -CONFIG_NET_SOCKOPTS=y -CONFIG_NET_TCP=y -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LINELEN=64 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PTHREAD_MUTEX_TYPES=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SIG_DEFAULT=y -CONFIG_SPINLOCK=y -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_BLUETOOTH=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/bmp180/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/bmp180/defconfig deleted file mode 100644 index 9c093552c539e..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/bmp180/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESP32C3_I2C0=y -CONFIG_EXAMPLES_BMP180=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SENSORS=y -CONFIG_SENSORS_BMP180=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/coremark/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/coremark/defconfig deleted file mode 100644 index bddc8c8a83736..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/coremark/defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NDEBUG is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_BENCHMARK_COREMARK=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_DEBUG_CUSTOMOPT=y -CONFIG_DEBUG_OPTLEVEL="-O3" -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=3072 -CONFIG_INIT_ENTRYPOINT="coremark_main" -CONFIG_INIT_STACKSIZE=3072 -CONFIG_INTELHEX_BINARY=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/crypto/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/crypto/defconfig deleted file mode 100644 index 6deea2d88076a..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/crypto/defconfig +++ /dev/null @@ -1,50 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ALLOW_BSD_COMPONENTS=y -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_CRYPTO=y -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_CRYPTODEV=y -CONFIG_CRYPTO_CRYPTODEV_HARDWARE=y -CONFIG_CRYPTO_RANDOM_POOL=y -CONFIG_DEV_ZERO=y -CONFIG_ESP32C3_AES_ACCELERATOR=y -CONFIG_ESP32C3_SHA_ACCELERATOR=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_CRYPTO=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/cxx/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/cxx/defconfig deleted file mode 100644 index 2d8b34cc2e2b5..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/cxx/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBCXX=y -CONFIG_LIBCXXABI=y -CONFIG_LIBC_MAX_EXITFUNS=1 -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_LIBM=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_CXXTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/efuse/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/efuse/defconfig deleted file mode 100644 index 60e16c95a3ad7..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/efuse/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_MB is not set -# CONFIG_NSH_DISABLE_MH is not set -# CONFIG_NSH_DISABLE_MW is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_EFUSE=y -CONFIG_ESP32C3_EFUSE=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/elf/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/elf/defconfig deleted file mode 100644 index 9db821d235394..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/elf/defconfig +++ /dev/null @@ -1,57 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_DISABLE_LOSMART is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=8192 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_ROMDISK=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ELF=y -CONFIG_EXAMPLES_ELF=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_HELLO_STACKSIZE=8192 -CONFIG_EXECFUNCS_HAVE_SYMTAB=y -CONFIG_EXECFUNCS_SYSTEM_SYMTAB=y -CONFIG_FS_PROCFS=y -CONFIG_FS_ROMFS=y -CONFIG_IDLETHREAD_STACKSIZE=8192 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=8192 -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_LIBM=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_FILE_APPS=y -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=8192 -CONFIG_PREALLOC_TIMERS=0 -CONFIG_PTHREAD_STACK_DEFAULT=8192 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=20 -CONFIG_START_MONTH=3 -CONFIG_START_YEAR=2020 -CONFIG_SYMTAB_ORDEREDBYNAME=y -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=12 -CONFIG_TLS_NELEM=4 -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/gdbstub/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/gdbstub/defconfig deleted file mode 100644 index 7e52b5600d74f..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/gdbstub/defconfig +++ /dev/null @@ -1,81 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ALLOW_BSD_COMPONENTS=y -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_FLOAT_H=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DRIVERS_IEEE80211=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_ESP32C3_SPIFLASH=y -CONFIG_ESP32C3_SPIFLASH_SPIFFS=y -CONFIG_ESP32C3_WIFI=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=3072 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_NBUFFERS=124 -CONFIG_IOB_THROTTLE=24 -CONFIG_LIBC_MAX_EXITFUNS=1 -CONFIG_LIB_GDBSTUB=y -CONFIG_NAME_MAX=48 -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_PHY_IOCTL=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETUTILS_CJSON=y -CONFIG_NETUTILS_IPERF=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=1514 -CONFIG_NET_ICMP=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_DELAYED_ACK=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NET_UDP_WRITE_BUFFERS=y -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LINELEN=64 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PTHREAD_MUTEX_TYPES=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SIG_DEFAULT=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_SYSTEM_DHCPC_RENEW=y -CONFIG_SYSTEM_GDBSTUB=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TLS_TASK_NELEM=4 -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_WAPI=y -CONFIG_WIRELESS_WAPI_CMDTOOL=y -CONFIG_WIRELESS_WAPI_INITCONF=y -CONFIG_WIRELESS_WAPI_STACKSIZE=4096 diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/gpio/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/gpio/defconfig deleted file mode 100644 index 0e6d213637735..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/gpio/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_GPIO=y -CONFIG_DEV_ZERO=y -CONFIG_ESP32C3_GPIO_IRQ=y -CONFIG_EXAMPLES_GPIO=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1536 -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_TASK_NAME_SIZE=12 -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/knsh/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/knsh/defconfig deleted file mode 100644 index a93bb3181dbfd..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/knsh/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ESP32C3_REGION_PROTECTION is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_ARCH_USE_MPU=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILD_PROTECTED=y -CONFIG_BUILTIN=y -CONFIG_DEBUG_ASSERTIONS=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEV_ZERO=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_NUTTX_USERSPACE=0x3c080018 -CONFIG_PASS1_BUILDIR="boards/risc-v/esp32c3/common/kernel" -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RAW_BINARY=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_STACK_COLORATION=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/lvgl/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/lvgl/defconfig deleted file mode 100644 index ee85f87d5fab5..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/lvgl/defconfig +++ /dev/null @@ -1,63 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_LV_BUILD_EXAMPLES is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESP32C3_SPI2=y -CONFIG_ESP32C3_SPI_SWCS=y -CONFIG_EXAMPLES_LVGLDEMO=y -CONFIG_FS_PROCFS=y -CONFIG_GRAPHICS_LVGL=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LCD=y -CONFIG_LCD_DEV=y -CONFIG_LCD_GC9A01=y -CONFIG_LCD_NOGETRUN=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_LV_COLOR_16_SWAP=y -CONFIG_LV_DEMO_WIDGETS_SLIDESHOW=y -CONFIG_LV_MEM_CUSTOM=y -CONFIG_LV_PORT_LCDDEV_DOUBLE_BUFFER=y -CONFIG_LV_PORT_USE_LCDDEV=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" -CONFIG_LV_USE_DEMO_WIDGETS=y -CONFIG_LV_USE_LOG=y -CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_MQ_MSGS=16 -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SPI_CMDDATA=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/mcuboot_slot_confirm/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/mcuboot_slot_confirm/defconfig deleted file mode 100644 index b95e1c0cb9bf9..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/mcuboot_slot_confirm/defconfig +++ /dev/null @@ -1,54 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESP32C3_APP_FORMAT_MCUBOOT=y -CONFIG_ESP32C3_ESPTOOL_TARGET_SECONDARY=y -CONFIG_ESP32C3_SPIFLASH=y -CONFIG_EXAMPLES_MCUBOOT_SLOT_CONFIRM=y -CONFIG_FS_PROCFS=y -CONFIG_FS_SMARTFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_MTD_SMART=y -CONFIG_NAME_MAX=48 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_LOSMART=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SMARTFS_MAXNAMLEN=48 -CONFIG_START_DAY=10 -CONFIG_START_MONTH=9 -CONFIG_START_YEAR=2021 -CONFIG_SYSTEM_FLASH_ERASEALL=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_FSTEST=y -CONFIG_TESTING_FSTEST_MOUNTPT="/mnt" -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/module/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/module/defconfig deleted file mode 100644 index 690203b5fa677..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/module/defconfig +++ /dev/null @@ -1,44 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_ROMDISK=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_EXAMPLES_MODULE=y -CONFIG_FS_PROCFS=y -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=3072 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_MODULE=y -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LINELEN=64 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/nsh/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/nsh/defconfig deleted file mode 100644 index f53c09c51d1bb..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/nsh/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEV_ZERO=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/nvcfgdata/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/nvcfgdata/defconfig deleted file mode 100644 index aa2b4d5e30f2f..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/nvcfgdata/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BCH=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESP32C3_SPIFLASH=y -CONFIG_ESP32C3_SPIFLASH_MTD_CONFIG=y -CONFIG_ESP32C3_STORAGE_MTD_OFFSET=0x3e6000 -CONFIG_ESP32C3_STORAGE_MTD_SIZE=0x3000 -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_MTD_CONFIG=y -CONFIG_MTD_CONFIG_FAIL_SAFE=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_CFGDATA=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_MTD_CONFIG_FAIL_SAFE=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/oneshot/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/oneshot/defconfig deleted file mode 100644 index 103406f56c845..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/oneshot/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESP32C3_ONESHOT=y -CONFIG_ESP32C3_TIMER0=y -CONFIG_ESP32C3_TIMER1=y -CONFIG_EXAMPLES_ONESHOT=y -CONFIG_EXAMPLES_TIMER=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_ONESHOT=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_TIMER=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/ostest/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/ostest/defconfig deleted file mode 100644 index 7abccd7294aac..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/ostest/defconfig +++ /dev/null @@ -1,43 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/pm/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/pm/defconfig deleted file mode 100644 index 607589c253b38..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/pm/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_FS_PROCFS=y -CONFIG_FS_PROCFS_REGISTER=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PM=y -CONFIG_PM_GOVERNOR_EXPLICIT_RELAX=-1 -CONFIG_PM_GOVERNOR_GREEDY=y -CONFIG_PM_PROCFS=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/pwm/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/pwm/defconfig deleted file mode 100644 index 105dbe3eff871..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/pwm/defconfig +++ /dev/null @@ -1,45 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESP32C3_LEDC=y -CONFIG_ESP32C3_LEDC_TIM0=y -CONFIG_EXAMPLES_PWM=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/random/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/random/defconfig deleted file mode 100644 index 9cbdb91bfd70c..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/random/defconfig +++ /dev/null @@ -1,45 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_URANDOM=y -CONFIG_DEV_ZERO=y -CONFIG_ESP32C3_RNG=y -CONFIG_EXAMPLES_RANDOM=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/romfs/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/romfs/defconfig deleted file mode 100644 index c9d70d0a599ec..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/romfs/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_EXAMPLES_ROMFS=y -CONFIG_FS_PROCFS=y -CONFIG_FS_ROMFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=6 -CONFIG_NSH_ROMFSETC=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/rtc/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/rtc/defconfig deleted file mode 100644 index 3fb307d087499..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/rtc/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESP32C3_RT_TIMER=y -CONFIG_EXAMPLES_ALARM=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC=y -CONFIG_RTC_ALARM=y -CONFIG_RTC_DRIVER=y -CONFIG_RTC_NALARMS=2 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/sotest/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/sotest/defconfig deleted file mode 100644 index f0aa1d19349b3..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/sotest/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_OS_SYMTAB=y -CONFIG_BOARDCTL_ROMDISK=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_ESP32C3_RTC_HEAP=y -CONFIG_EXAMPLES_SOTEST=y -CONFIG_FS_PROCFS=y -CONFIG_FS_ROMFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=3072 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_DLFCN=y -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LINELEN=64 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/spiflash/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/spiflash/defconfig deleted file mode 100644 index 41d643e3435cb..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/spiflash/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESP32C3_SPIFLASH=y -CONFIG_ESP32C3_SPIFLASH_SMARTFS=y -CONFIG_ESP32C3_STORAGE_MTD_OFFSET=0x110000 -CONFIG_ESP32C3_STORAGE_MTD_SIZE=0xf0000 -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NAME_MAX=48 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_LOSMART=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_SMARTFS_MAXNAMLEN=48 -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_FLASH_ERASEALL=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_FSTEST=y -CONFIG_TESTING_FSTEST_MOUNTPT="/mnt" -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/sta_softap/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/sta_softap/defconfig deleted file mode 100644 index ca2aa6bfae300..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/sta_softap/defconfig +++ /dev/null @@ -1,81 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ALLOW_BSD_COMPONENTS=y -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DEBUG_ASSERTIONS=y -CONFIG_DEBUG_FEATURES=y -CONFIG_DEBUG_WIRELESS=y -CONFIG_DEBUG_WIRELESS_ERROR=y -CONFIG_DRIVERS_IEEE80211=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_ESP32C3_SPIFLASH=y -CONFIG_ESP32C3_SPIFLASH_SPIFFS=y -CONFIG_ESP32C3_STORAGE_MTD_OFFSET=0x110000 -CONFIG_ESP32C3_STORAGE_MTD_SIZE=0xf0000 -CONFIG_ESP32C3_WIFI=y -CONFIG_ESP32C3_WIFI_STATION_SOFTAP=y -CONFIG_EXAMPLES_DHCPD=y -CONFIG_EXPERIMENTAL=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=3072 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_MAX_EXITFUNS=1 -CONFIG_MM_REGIONS=3 -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_PHY_IOCTL=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETUTILS_CJSON=y -CONFIG_NETUTILS_DHCPD=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=1514 -CONFIG_NET_ICMP=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_UDP=y -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LINELEN=64 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PTHREAD_MUTEX_TYPES=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SIG_DEFAULT=y -CONFIG_SPIFFS_NAME_MAX=48 -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_SYSTEM_DHCPC_RENEW=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TLS_TASK_NELEM=4 -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_WAPI=y -CONFIG_WIRELESS_WAPI_CMDTOOL=y -CONFIG_WIRELESS_WAPI_INITCONF=y -CONFIG_WIRELESS_WAPI_STACKSIZE=4096 diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/tickless/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/tickless/defconfig deleted file mode 100644 index 8a5fa7baa47f3..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/tickless/defconfig +++ /dev/null @@ -1,44 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESP32C3_TICKLESS=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/timer/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/timer/defconfig deleted file mode 100644 index 0458cc5341894..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/timer/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESP32C3_TIMER0=y -CONFIG_ESP32C3_TIMER1=y -CONFIG_EXAMPLES_TIMER=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_TIMER=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/twai/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/twai/defconfig deleted file mode 100644 index 92b86bf3c5614..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/twai/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3MINI1=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESP32C3_TWAI0=y -CONFIG_EXAMPLES_CAN=y -CONFIG_FS_PROCFS=y -CONFIG_FS_ROMFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_PRIORITY_INHERITANCE=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/uid/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/uid/defconfig deleted file mode 100644 index c0823183acea8..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/uid/defconfig +++ /dev/null @@ -1,43 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_UNIQUEID=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/usbconsole/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/usbconsole/defconfig deleted file mode 100644 index d60597df4521d..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/usbconsole/defconfig +++ /dev/null @@ -1,45 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ESP32C3_UART0 is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESP32C3_USBSERIAL=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_HOST_MACOS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/watchdog/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/watchdog/defconfig deleted file mode 100644 index 45cc990321008..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/watchdog/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESP32C3_MWDT0=y -CONFIG_ESP32C3_MWDT1=y -CONFIG_EXAMPLES_WATCHDOG=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_WATCHDOG=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/watcher/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/watcher/defconfig deleted file mode 100644 index fbdaf4366a034..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/watcher/defconfig +++ /dev/null @@ -1,50 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_DRIVERS_NOTE=y -CONFIG_ESP32C3_MWDT0=y -CONFIG_ESP32C3_MWDT1=y -CONFIG_EXAMPLES_WATCHER=y -CONFIG_FS_FAT=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_INSTRUMENTATION=y -CONFIG_SCHED_INSTRUMENTATION_SWITCH=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_WATCHDOG=y diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/wifi/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/wifi/defconfig deleted file mode 100644 index 5446fed3e9b8d..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/wifi/defconfig +++ /dev/null @@ -1,76 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ALLOW_BSD_COMPONENTS=y -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c3" -CONFIG_ARCH_CHIP_ESP32C3=y -CONFIG_ARCH_CHIP_ESP32C3WROOM02=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=16717 -CONFIG_BUILTIN=y -CONFIG_DRIVERS_IEEE80211=y -CONFIG_DRIVERS_WIRELESS=y -CONFIG_ESP32C3_SPIFLASH=y -CONFIG_ESP32C3_SPIFLASH_SPIFFS=y -CONFIG_ESP32C3_WIFI=y -CONFIG_FS_PROCFS=y -CONFIG_HAVE_CXX=y -CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_IDLETHREAD_STACKSIZE=3072 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_IOB_NBUFFERS=124 -CONFIG_IOB_THROTTLE=24 -CONFIG_LIBC_MAX_EXITFUNS=1 -CONFIG_NAME_MAX=48 -CONFIG_NETDB_DNSCLIENT=y -CONFIG_NETDEV_LATEINIT=y -CONFIG_NETDEV_PHY_IOCTL=y -CONFIG_NETDEV_WIRELESS_IOCTL=y -CONFIG_NETUTILS_CJSON=y -CONFIG_NETUTILS_IPERF=y -CONFIG_NET_BROADCAST=y -CONFIG_NET_ETH_PKTSIZE=1514 -CONFIG_NET_ICMP=y -CONFIG_NET_ICMP_SOCKET=y -CONFIG_NET_TCP=y -CONFIG_NET_TCP_DELAYED_ACK=y -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_UDP=y -CONFIG_NET_UDP_WRITE_BUFFERS=y -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_LINELEN=64 -CONFIG_NSH_READLINE=y -CONFIG_PREALLOC_TIMERS=4 -CONFIG_PTHREAD_MUTEX_TYPES=y -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_LPWORK=y -CONFIG_SCHED_WAITPID=y -CONFIG_SIG_DEFAULT=y -CONFIG_START_DAY=6 -CONFIG_START_MONTH=12 -CONFIG_START_YEAR=2011 -CONFIG_SYSTEM_DHCPC_RENEW=y -CONFIG_SYSTEM_NSH=y -CONFIG_SYSTEM_PING=y -CONFIG_TLS_TASK_NELEM=4 -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_WAPI=y -CONFIG_WIRELESS_WAPI_CMDTOOL=y -CONFIG_WIRELESS_WAPI_INITCONF=y -CONFIG_WIRELESS_WAPI_STACKSIZE=4096 diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/include/board.h b/boards/risc-v/esp32c3/esp32c3-devkit/include/board.h deleted file mode 100644 index 07d6e4c5f9b4c..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/include/board.h +++ /dev/null @@ -1,38 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit/include/board.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_INCLUDE_BOARD_H -#define __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_INCLUDE_BOARD_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -#define BOARD_XTAL_FREQUENCY 40000000 - -/* GPIO pins used by the GPIO Subsystem */ - -#define BOARD_NGPIOOUT 2 /* Amount of GPIO Output pins */ -#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ - -#endif /* __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_INCLUDE_BOARD_H */ - diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/include/board_memorymap.h b/boards/risc-v/esp32c3/esp32c3-devkit/include/board_memorymap.h deleted file mode 100644 index 0010a78d00595..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/include/board_memorymap.h +++ /dev/null @@ -1,116 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit/include/board_memorymap.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_INCLUDE_BOARD_MEMORYMAP_H -#define __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_INCLUDE_BOARD_MEMORYMAP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Kernel ROM */ - -#define KIROM_START (uintptr_t)__kirom_start -#define KIROM_SIZE (uintptr_t)__kirom_size -#define KDROM_START (uintptr_t)__kdrom_start -#define KDROM_SIZE (uintptr_t)__kdrom_size - -/* Kernel RAM */ - -#define KIRAM_START (uintptr_t)__kiram_start -#define KIRAM_SIZE (uintptr_t)__kiram_size -#define KIRAM_END (uintptr_t)__kiram_end -#define KDRAM_START (uintptr_t)__kdram_start -#define KDRAM_SIZE (uintptr_t)__kdram_size -#define KDRAM_END (uintptr_t)__kdram_end - -/* Exception vectors */ - -#define VECTORS_START (uintptr_t)__vectors_start -#define VECTORS_END (uintptr_t)__vectors_end - -/* User ROM */ - -#define UIROM_START (uintptr_t)__uirom_start -#define UIROM_SIZE (uintptr_t)__uirom_size -#define UIROM_END (uintptr_t)__uirom_end -#define UDROM_START (uintptr_t)__udrom_start -#define UDROM_SIZE (uintptr_t)__udrom_size -#define UDROM_END (uintptr_t)__udrom_end - -/* User RAM */ - -#define UIRAM_START (uintptr_t)__uiram_start -#define UIRAM_SIZE (uintptr_t)__uiram_size -#define UIRAM_END (uintptr_t)__uiram_end -#define UDRAM_START (uintptr_t)__udram_start -#define UDRAM_SIZE (uintptr_t)__udram_size -#define UDRAM_END (uintptr_t)__udram_end - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/* Kernel ROM (RX) */ - -extern uint8_t __kirom_start[]; -extern uint8_t __kirom_size[]; -extern uint8_t __kdrom_start[]; -extern uint8_t __kdrom_size[]; - -/* Kernel RAM (RW) */ - -extern uint8_t __kiram_start[]; -extern uint8_t __kiram_size[]; -extern uint8_t __kiram_end[]; -extern uint8_t __kdram_start[]; -extern uint8_t __kdram_size[]; -extern uint8_t __kdram_end[]; - -/* Exception vectors */ - -extern uint8_t __vectors_start[]; -extern uint8_t __vectors_end[]; - -/* User ROM (RX) */ - -extern uint8_t __uirom_start[]; -extern uint8_t __uirom_size[]; -extern uint8_t __uirom_end[]; -extern uint8_t __udrom_start[]; -extern uint8_t __udrom_size[]; -extern uint8_t __udrom_end[]; - -/* User RAM (RW) */ - -extern uint8_t __uiram_start[]; -extern uint8_t __uiram_size[]; -extern uint8_t __uiram_end[]; -extern uint8_t __udram_start[]; -extern uint8_t __udram_size[]; -extern uint8_t __udram_end[]; - -#endif /* __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_INCLUDE_BOARD_MEMORYMAP_H */ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/include/nsh_romfsimg.h b/boards/risc-v/esp32c3/esp32c3-devkit/include/nsh_romfsimg.h deleted file mode 100644 index 6b293e9f3b518..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/include/nsh_romfsimg.h +++ /dev/null @@ -1,25 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit/include/nsh_romfsimg.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_INCLUDE_NSH_ROMFSIMG_H -#define __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_INCLUDE_NSH_ROMFSIMG_H -extern const unsigned char romfs_img[]; -extern const unsigned int romfs_img_len; -#endif diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/scripts/Make.defs b/boards/risc-v/esp32c3/esp32c3-devkit/scripts/Make.defs deleted file mode 100644 index 4a8969ecff9f9..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/scripts/Make.defs +++ /dev/null @@ -1,66 +0,0 @@ -############################################################################ -# boards/risc-v/esp32c3/esp32c3-devkit/scripts/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -########################################################################### - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/tools/esp32c3/Config.mk -include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs - -ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32c3_rom.ld - -# Pick the linker scripts from the board level if they exist, if not -# pick the common linker scripts. - -ifeq ($(CONFIG_BUILD_PROTECTED),y) - ARCHSCRIPT += $(call FINDSCRIPT,protected_memory.ld) - ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld) -else - ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) - - ifeq ($(CONFIG_ESP32C3_APP_FORMAT_MCUBOOT),y) - ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) - else - ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) - endif -endif - -ARCHPICFLAGS = -fpic - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -Werror=return-type -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -# Loadable module definitions - -CMODULEFLAGS = $(CFLAGS) - -LDMODULEFLAGS = -melf32lriscv -r -e module_initialize -LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld) - -# ELF module definitions - -CELFFLAGS = $(CFLAGS) -CXXELFFLAGS = $(CXXFLAGS) - -LDELFFLAGS = -melf32lriscv -r -e main -LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)$(DELIM)binfmt$(DELIM)libelf$(DELIM)gnu-elf.ld) diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/Make.defs b/boards/risc-v/esp32c3/esp32c3-devkit/src/Make.defs deleted file mode 100644 index 83ecb43b6ec07..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/Make.defs +++ /dev/null @@ -1,54 +0,0 @@ -############################################################################# -# boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################# - -include $(TOPDIR)/Make.defs - -CSRCS = esp32c3_boot.c esp32c3_bringup.c - -ifeq ($(CONFIG_BOARDCTL),y) - CSRCS += esp32c3_appinit.c - - ifeq ($(CONFIG_BOARDCTL_RESET),y) - CSRCS += esp32c3_reset.c - endif -endif - -ifeq ($(CONFIG_DEV_GPIO),y) - CSRCS += esp32c3_gpio.c -endif - -ifeq ($(CONFIG_BOARDCTL_IOCTL),y) - CSRCS += esp32c3_ioctl.c -endif - -ifeq ($(CONFIG_BOARDCTL_UNIQUEID),y) - CSRCS += esp32c3_uid.c -endif - -ifeq ($(CONFIG_NSH_ROMFSETC),y) -ifneq ($(CONFIG_NSH_CUSTOMROMFS),y) - RCSRCS = etc/init.d/rc.sysinit etc/init.d/rcS - RCRAWS = etc/group etc/passwd -endif -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_appinit.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_appinit.c deleted file mode 100644 index 4f683dc85c8ed..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_appinit.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_appinit.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "esp32c3-devkit.h" - -#ifdef CONFIG_BOARDCTL - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_app_initialize - * - * Description: - * Perform application specific initialization. This function is never - * called directly from application code, but only indirectly via the - * (non-standard) boardctl() interface using the command BOARDIOC_INIT. - * - * Input Parameters: - * arg - The boardctl() argument is passed to the board_app_initialize() - * implementation without modification. The argument has no - * meaning to NuttX; the meaning of the argument is a contract - * between the board-specific initialization logic and the - * matching application logic. The value could be such things as a - * mode enumeration value, a set of DIP switch settings, a - * pointer to configuration data read from a file or serial FLASH, - * or whatever you would like to do with it. Every implementation - * should accept zero/NULL as a default configuration. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure to indicate the nature of the failure. - * - ****************************************************************************/ - -int board_app_initialize(uintptr_t arg) -{ -#ifdef CONFIG_BOARD_LATE_INITIALIZE - /* Board initialization already performed by board_late_initialize() */ - - return OK; -#else - /* Perform board-specific initialization */ - - return esp32c3_bringup(); -#endif -} - -#endif /* CONFIG_BOARDCTL */ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_boot.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_boot.c deleted file mode 100644 index 934a05b72ec2f..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_boot.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_boot.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "riscv_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c3_board_initialize - * - * Description: - * All ESP32-C3 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void esp32c3_board_initialize(void) -{ -#ifdef CONFIG_ARCH_PERF_EVENTS - up_perf_init(NULL); -#endif - - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - esp32c3_bringup(); -} -#endif diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c deleted file mode 100644 index dbb5708cf2bfa..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c +++ /dev/null @@ -1,396 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "esp32c3_wlan.h" -#include "esp32c3_spiflash.h" -#include "esp32c3_partition.h" - -#include "esp32c3-devkit.h" -#include "esp32c3_board_adc.h" -#include "esp32c3_board_bmp180.h" -#include "esp32c3_board_i2c.h" -#include "esp32c3_board_ledc.h" -#include "esp32c3_board_oneshot.h" -#include "esp32c3_board_spiflash.h" -#include "esp32c3_board_spidev.h" -#include "esp32c3_board_spislavedev.h" -#include "esp32c3_board_twai.h" -#include "esp32c3_board_wdt.h" -#include "esp32c3_board_wlan.h" -#include "esp32c3_board_mpu60x0_i2c.h" - -#ifdef CONFIG_SPI -# include "esp32c3_spi.h" -#endif - -#ifdef CONFIG_LCD_DEV -# include -# include -#endif - -#ifdef CONFIG_VIDEO_FB -# include -#endif - -#ifdef CONFIG_ESP32C3_RT_TIMER -# include "esp32c3_rt_timer.h" -#endif - -#ifdef CONFIG_TIMER -# include "esp32c3_tim_lowerhalf.h" -#endif - -#include "esp32c3_rtc.h" -#ifdef CONFIG_ESP32C3_EFUSE -# include "esp32c3_efuse.h" -#endif - -#ifdef CONFIG_ESP32C3_SHA_ACCELERATOR -# include "esp32c3_sha.h" -#endif - -#ifdef CONFIG_RTC_DRIVER -# include "esp32c3_rtc_lowerhalf.h" -#endif - -#ifdef CONFIG_ESP32C3_BLE -# include "esp32c3_ble.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c3_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y - * Called from board_late_initialize(). - * - * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y - * Called from the NSH library - * - ****************************************************************************/ - -int esp32c3_bringup(void) -{ - int ret; - -#if defined(CONFIG_ESP32C3_EFUSE) - ret = esp32c3_efuse_initialize("/dev/efuse"); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to init EFUSE: %d\n", ret); - } -#endif - -#if defined(CONFIG_ESP32C3_SHA_ACCELERATOR) && \ - !defined(CONFIG_CRYPTO_CRYPTODEV_HARDWARE) - ret = esp32c3_sha_init(); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to initialize SHA: %d\n", ret); - } -#endif - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#ifdef CONFIG_FS_TMPFS - /* Mount the tmpfs file system */ - - ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount tmpfs at %s: %d\n", - CONFIG_LIBC_TMPDIR, ret); - } -#endif - -#ifdef CONFIG_ESP32C3_SPIFLASH - ret = board_spiflash_init(); - if (ret) - { - syslog(LOG_ERR, "ERROR: Failed to initialize SPI Flash\n"); - } -#endif - -#ifdef CONFIG_ESP32C3_PARTITION_TABLE - ret = esp32c3_partition_init(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize partition error=%d\n", - ret); - } -#endif - -#ifdef CONFIG_DEV_GPIO - ret = esp32c3_gpio_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); - } -#endif - -#if defined(CONFIG_SPI_DRIVER) && defined(CONFIG_ESP32C3_SPI2) - ret = board_spidev_initialize(ESP32C3_SPI2); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize SPI%d driver: %d\n", - ESP32C3_SPI2, ret); - } -#endif - -#if defined(CONFIG_SPI_SLAVE_DRIVER) && defined(CONFIG_ESP32C3_SPI2) - ret = board_spislavedev_initialize(ESP32C3_SPI2); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize SPI%d Slave driver: %d\n", - ESP32C3_SPI2, ret); - } -#endif - -#ifdef CONFIG_VIDEO_FB - ret = fb_register(0, 0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize Frame Buffer Driver.\n"); - } -#elif defined(CONFIG_LCD) - ret = board_lcd_initialize(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to initialize LCD.\n"); - } -#endif - -#ifdef CONFIG_LCD_DEV - ret = lcddev_register(0); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: lcddev_register() failed: %d\n", ret); - } -#endif - -#if defined(CONFIG_I2C_DRIVER) - /* Configure I2C peripheral interfaces */ - - ret = board_i2c_init(); - - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize I2C driver: %d\n", ret); - } -#endif - -#ifdef CONFIG_CAN - - /* Initialize TWAI and register the TWAI driver. */ - - ret = board_twai_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_twai_setup failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_SENSORS_BMP180 - /* Try to register BMP180 device in I2C0 */ - - ret = board_bmp180_initialize(0, 0); - - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize BMP180 " - "Driver for I2C0: %d\n", ret); - } -#endif - -#ifdef CONFIG_WATCHDOG - /* Configure watchdog timer */ - - ret = board_wdt_init(); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to initialize watchdog drivers: %d\n", - ret); - } -#endif - -/* First, register the timer drivers and let timer 1 for oneshot - * if it is enabled. - */ - -#ifdef CONFIG_TIMER - -#if defined(CONFIG_ESP32C3_TIMER0) && !defined(CONFIG_ESP32C3_RT_TIMER) - ret = esp32c3_timer_initialize("/dev/timer0", TIMER0); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to initialize timer driver: %d\n", - ret); - } -#endif - -#if defined(CONFIG_ESP32C3_TIMER1) && !defined(CONFIG_ONESHOT) - ret = esp32c3_timer_initialize("/dev/timer1", TIMER1); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to initialize timer driver: %d\n", - ret); - } -#endif - -#endif /* CONFIG_TIMER */ - - /* Now register one oneshot driver */ - -#if defined(CONFIG_ONESHOT) && defined(CONFIG_ESP32C3_TIMER1) - - ret = board_oneshot_init(ONESHOT_TIMER, ONESHOT_RESOLUTION_US); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_oneshot_init() failed: %d\n", ret); - } - -#endif /* CONFIG_ONESHOT */ - -#ifdef CONFIG_ESP32C3_RT_TIMER - ret = esp32c3_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - -#ifdef CONFIG_ESP32C3_WIRELESS - -#ifdef CONFIG_ESP32C3_WIFI_BT_COEXIST - ret = esp32c3_wifi_bt_coexist_init(); - if (ret) - { - syslog(LOG_ERR, "ERROR: Failed to initialize Wi-Fi and BT coexist\n"); - } -#endif - -#ifdef CONFIG_ESP32C3_BLE - ret = esp32c3_ble_initialize(); - if (ret) - { - syslog(LOG_ERR, "ERROR: Failed to initialize BLE\n"); - } -#endif - -#ifdef CONFIG_ESP32C3_WIFI - - ret = board_wlan_init(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_wlan_init() failed: %d\n", ret); - } - -#endif - -#endif /* CONFIG_ESP32C3_WIRELESS */ - -#ifdef CONFIG_ESP32C3_LEDC - ret = board_ledc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_ledc_setup() failed: %d\n", ret); - } -#endif /* CONFIG_ESP32C3_LEDC */ - -#ifdef CONFIG_ESP32C3_ADC - ret = board_adc_init(); - if (ret) - { - syslog(LOG_ERR, "ERROR: board_adc_init() failed: %d\n", ret); - } -#endif /* CONFIG_ESP32C3_ADC */ - -#ifdef CONFIG_RTC_DRIVER - /* Instantiate the ESP32-C3 RTC driver */ - - ret = esp32c3_rtc_driverinit(); - if (ret < 0) - { - syslog(LOG_ERR, - "ERROR: Failed to Instantiate the RTC driver: %d\n", ret); - } -#endif - -#ifdef CONFIG_MPU60X0_I2C - /* Try to register MPU60x0 device in I2C0 */ - - ret = board_mpu60x0_initialize(0, 0); - - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize MPU60x0 " - "Driver for I2C0: %d\n", ret); - } -#endif - - /* If we got here then perhaps not all initialization was successful, but - * at least enough succeeded to bring-up NSH with perhaps reduced - * capabilities. - */ - - UNUSED(ret); - return OK; -} diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c deleted file mode 100644 index 4152f848ba4a4..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c +++ /dev/null @@ -1,409 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_gpio.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include - -#include - -#include - -#include "esp32c3-devkit.h" -#include "esp32c3_gpio.h" -#include "hardware/esp32c3_gpio_sigmap.h" - -#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Pin 1 and 2 are used for this example as GPIO outputs. */ - -#define GPIO_OUT1 1 -#define GPIO_OUT2 2 - -#if !defined(CONFIG_ESP32C3_GPIO_IRQ) && BOARD_NGPIOINT > 0 -# error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" -#endif - -/* Interrupt pins. GPIO9 is used as an example, any other inputs could be - * used. - */ - -#define GPIO_IRQPIN 9 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct esp32c3gpio_dev_s -{ - struct gpio_dev_s gpio; - uint8_t id; -}; - -struct esp32c3gpint_dev_s -{ - struct esp32c3gpio_dev_s esp32c3gpio; - pin_interrupt_t callback; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#if BOARD_NGPIOOUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value); -static int gpout_write(struct gpio_dev_s *dev, bool value); -static int gpout_setpintype(struct gpio_dev_s *dev, - enum gpio_pintype_e pintype); -#endif - -#if BOARD_NGPIOINT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value); -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback); -static int gpint_enable(struct gpio_dev_s *dev, bool enable); -static int gpint_setpintype(struct gpio_dev_s *dev, - enum gpio_pintype_e pintype); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if BOARD_NGPIOOUT > 0 -static const struct gpio_operations_s gpout_ops = -{ - .go_read = gpout_read, - .go_write = gpout_write, - .go_attach = NULL, - .go_enable = NULL, - .go_setpintype = gpout_setpintype, -}; - -/* This array maps the GPIO pins used as OUTPUT */ - -static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = -{ - GPIO_OUT1, GPIO_OUT2 -}; - -static struct esp32c3gpio_dev_s g_gpout[BOARD_NGPIOOUT]; -#endif - -#if BOARD_NGPIOINT > 0 -static const struct gpio_operations_s gpint_ops = -{ - .go_read = gpint_read, - .go_write = NULL, - .go_attach = gpint_attach, - .go_enable = gpint_enable, - .go_setpintype = gpint_setpintype, -}; - -/* This array maps the GPIO pins used as INTERRUPT INPUTS */ - -static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = -{ - GPIO_IRQPIN, -}; - -static struct esp32c3gpint_dev_s g_gpint[BOARD_NGPIOINT]; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: gpout_read - ****************************************************************************/ - -#if BOARD_NGPIOOUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value) -{ - struct esp32c3gpio_dev_s *esp32c3gpio = - (struct esp32c3gpio_dev_s *)dev; - - DEBUGASSERT(esp32c3gpio != NULL && value != NULL); - DEBUGASSERT(esp32c3gpio->id < BOARD_NGPIOOUT); - gpioinfo("Reading...\n"); - - *value = esp32c3_gpioread(g_gpiooutputs[esp32c3gpio->id]); - return OK; -} - -/**************************************************************************** - * Name: gpout_write - ****************************************************************************/ - -static int gpout_write(struct gpio_dev_s *dev, bool value) -{ - struct esp32c3gpio_dev_s *esp32c3gpio = - (struct esp32c3gpio_dev_s *)dev; - - DEBUGASSERT(esp32c3gpio != NULL); - DEBUGASSERT(esp32c3gpio->id < BOARD_NGPIOOUT); - gpioinfo("Writing %d\n", (int)value); - - esp32c3_gpiowrite(g_gpiooutputs[esp32c3gpio->id], value); - return OK; -} - -/**************************************************************************** - * Name: gpout_setpintype - ****************************************************************************/ - -static int gpout_setpintype(struct gpio_dev_s *dev, - enum gpio_pintype_e pintype) -{ - struct esp32c3gpio_dev_s *esp32c3gpio = - (struct esp32c3gpio_dev_s *)dev; - - DEBUGASSERT(esp32c3gpio != NULL); - DEBUGASSERT(esp32c3gpio->id < BOARD_NGPIOOUT); - gpioinfo("Setting pintype: %d\n", (int)pintype); - - esp32c3_gpio_matrix_out(g_gpiooutputs[esp32c3gpio->id], - SIG_GPIO_OUT_IDX, 0, 0); - - switch (pintype) - { - case GPIO_INPUT_PIN: - esp32c3_configgpio(g_gpiooutputs[esp32c3gpio->id], INPUT); - break; - case GPIO_INPUT_PIN_PULLUP: - esp32c3_configgpio(g_gpiooutputs[esp32c3gpio->id], INPUT_PULLUP); - break; - case GPIO_INPUT_PIN_PULLDOWN: - esp32c3_configgpio(g_gpiooutputs[esp32c3gpio->id], INPUT_PULLDOWN); - break; - case GPIO_OUTPUT_PIN: - esp32c3_configgpio(g_gpiooutputs[esp32c3gpio->id], INPUT | OUTPUT); - break; - case GPIO_OUTPUT_PIN_OPENDRAIN: - esp32c3_configgpio(g_gpiooutputs[esp32c3gpio->id], INPUT | - OUTPUT_OPEN_DRAIN); - break; - default: - return ERROR; - break; - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: esp32c3gpio_interrupt - ****************************************************************************/ - -#if BOARD_NGPIOINT > 0 -static int esp32c3gpio_interrupt(int irq, void *context, void *arg) -{ - struct esp32c3gpint_dev_s *esp32c3gpint = - (struct esp32c3gpint_dev_s *)arg; - - DEBUGASSERT(esp32c3gpint != NULL && esp32c3gpint->callback != NULL); - gpioinfo("Interrupt! callback=%p\n", esp32c3gpint->callback); - - esp32c3gpint->callback(&esp32c3gpint->esp32c3gpio.gpio, - esp32c3gpint->esp32c3gpio.id); - return OK; -} - -/**************************************************************************** - * Name: gpint_read - ****************************************************************************/ - -static int gpint_read(struct gpio_dev_s *dev, bool *value) -{ - struct esp32c3gpint_dev_s *esp32c3gpint = - (struct esp32c3gpint_dev_s *)dev; - - DEBUGASSERT(esp32c3gpint != NULL && value != NULL); - DEBUGASSERT(esp32c3gpint->esp32c3gpio.id < BOARD_NGPIOINT); - gpioinfo("Reading int pin...\n"); - - *value = esp32c3_gpioread(g_gpiointinputs[esp32c3gpint->esp32c3gpio.id]); - return OK; -} - -/**************************************************************************** - * Name: gpint_attach - ****************************************************************************/ - -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback) -{ - struct esp32c3gpint_dev_s *esp32c3gpint = - (struct esp32c3gpint_dev_s *)dev; - int irq = ESP32C3_PIN2IRQ(g_gpiointinputs[esp32c3gpint->esp32c3gpio.id]); - int ret; - - gpioinfo("Attaching the callback\n"); - - /* Make sure the interrupt is disabled */ - - esp32c3_gpioirqdisable(irq); - ret = irq_attach(irq, - esp32c3gpio_interrupt, - &g_gpint[esp32c3gpint->esp32c3gpio.id]); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", callback); - esp32c3gpint->callback = callback; - return OK; -} - -/**************************************************************************** - * Name: gpint_enable - ****************************************************************************/ - -static int gpint_enable(struct gpio_dev_s *dev, bool enable) -{ - struct esp32c3gpint_dev_s *esp32c3gpint = - (struct esp32c3gpint_dev_s *)dev; - int irq = ESP32C3_PIN2IRQ(g_gpiointinputs[esp32c3gpint->esp32c3gpio.id]); - - if (enable) - { - if (esp32c3gpint->callback != NULL) - { - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising edge */ - - esp32c3_gpioirqenable(irq, RISING); - } - } - else - { - gpioinfo("Disable the interrupt\n"); - esp32c3_gpioirqdisable(irq); - } - - return OK; -} - -/**************************************************************************** - * Name: gpint_setpintype - ****************************************************************************/ - -static int gpint_setpintype(struct gpio_dev_s *dev, - enum gpio_pintype_e pintype) -{ - struct esp32c3gpint_dev_s *esp32c3gpint = - (struct esp32c3gpint_dev_s *)dev; - - DEBUGASSERT(esp32c3gpint != NULL); - DEBUGASSERT(esp32c3gpint->esp32c3gpio.id < BOARD_NGPIOINT); - gpioinfo("Setting pintype: %d\n", (int)pintype); - switch (pintype) - { - case GPIO_INTERRUPT_HIGH_PIN: - esp32c3_configgpio(g_gpiointinputs[esp32c3gpint->esp32c3gpio.id], - INPUT_PULLUP); - break; - case GPIO_INTERRUPT_LOW_PIN: - esp32c3_configgpio(g_gpiointinputs[esp32c3gpint->esp32c3gpio.id], - INPUT_PULLDOWN); - break; - default: - return ERROR; - break; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c3_gpio_init - ****************************************************************************/ - -int esp32c3_gpio_init(void) -{ - int pincount = 0; - int i; - -#if BOARD_NGPIOOUT > 0 - for (i = 0; i < BOARD_NGPIOOUT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; - g_gpout[i].gpio.gp_ops = &gpout_ops; - g_gpout[i].id = i; - gpio_pin_register(&g_gpout[i].gpio, pincount); - - /* Configure the pins that will be used as output */ - - esp32c3_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp32c3_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_1 | - INPUT_FUNCTION_1); - esp32c3_gpiowrite(g_gpiooutputs[i], 0); - - pincount++; - } -#endif - -#if BOARD_NGPIOINT > 0 - for (i = 0; i < BOARD_NGPIOINT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpint[i].esp32c3gpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; - g_gpint[i].esp32c3gpio.gpio.gp_ops = &gpint_ops; - g_gpint[i].esp32c3gpio.id = i; - gpio_pin_register(&g_gpint[i].esp32c3gpio.gpio, pincount); - - /* Configure the pins that will be used as interrupt input */ - - esp32c3_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_1 | PULLDOWN); - - pincount++; - } -#endif - - return OK; -} -#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_ioctl.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_ioctl.c deleted file mode 100644 index 54579a8c3a795..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_ioctl.c +++ /dev/null @@ -1,72 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_ioctl.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include - -#ifdef CONFIG_BOARDCTL_IOCTL - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_ioctl - * - * Description: - * The "landing site" for much of the boardctl() interface. Generic board- - * control functions invoked via ioctl() get routed through here. - * - * Since we don't do anything unusual at the moment, this function - * accomplishes nothing except avoid a missing-function linker error if - * CONFIG_BOARDCTL_IOCTL is selected. - * - * Input Parameters: - * cmd - IOCTL command being requested. - * arg - Arguments for the IOCTL. - * - * Returned Value: - * we don't yet support any boardctl IOCTLs. This function always returns - * -ENOTTY which is the standard IOCTL return value when a command is not - * supported - * - ****************************************************************************/ - -int board_ioctl(unsigned int cmd, uintptr_t arg) -{ - switch (cmd) - { - default: - return -ENOTTY; - } - - return OK; -} - -#endif /* CONFIG_BOARDCTL_IOCTL */ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_reset.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_reset.c deleted file mode 100644 index ad7059cbfe12d..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_reset.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_reset.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include "esp32c3_systemreset.h" - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value in this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - syslog(LOG_INFO, "reboot status=%d\n", status); - - switch (status) - { - case EXIT_SUCCESS: - up_shutdown_handler(); - break; - case CONFIG_BOARD_ASSERT_RESET_VALUE: - break; - default: - break; - } - - up_systemreset(); - - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_uid.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_uid.c deleted file mode 100644 index f01bed46c012e..0000000000000 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_uid.c +++ /dev/null @@ -1,49 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_uid.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -#include "esp32c3_uid.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -#if defined(CONFIG_BOARDCTL_UNIQUEID) -int board_uniqueid(uint8_t *uniqueid) -{ - if (uniqueid == NULL) - { - return -EINVAL; - } - - esp32c3_get_uniqueid(uniqueid); - return OK; -} -#endif diff --git a/boards/risc-v/espressif/esp32c3-generic/Kconfig b/boards/risc-v/esp32c3/esp32c3-generic/Kconfig similarity index 100% rename from boards/risc-v/espressif/esp32c3-generic/Kconfig rename to boards/risc-v/esp32c3/esp32c3-generic/Kconfig diff --git a/boards/risc-v/esp32c3/esp32c3-generic/configs/buttons/defconfig b/boards/risc-v/esp32c3/esp32c3-generic/configs/buttons/defconfig new file mode 100644 index 0000000000000..f2cfa6af70132 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/configs/buttons/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-generic" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3_GENERIC=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_GPIO_IRQ=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-generic/configs/gpio/defconfig b/boards/risc-v/esp32c3/esp32c3-generic/configs/gpio/defconfig new file mode 100644 index 0000000000000..247f6389cbb9c --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/configs/gpio/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-generic" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3_GENERIC=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_GPIO=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_GPIO_IRQ=y +CONFIG_EXAMPLES_GPIO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-generic/configs/mcuboot_nsh/defconfig b/boards/risc-v/esp32c3/esp32c3-generic/configs/mcuboot_nsh/defconfig new file mode 100644 index 0000000000000..5965c3834326d --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/configs/mcuboot_nsh/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-generic" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3_GENERIC=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-generic/configs/nsh/defconfig b/boards/risc-v/esp32c3/esp32c3-generic/configs/nsh/defconfig new file mode 100644 index 0000000000000..0eb62976513cd --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/configs/nsh/defconfig @@ -0,0 +1,46 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-generic" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3_GENERIC=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-generic/configs/ostest/defconfig b/boards/risc-v/esp32c3/esp32c3-generic/configs/ostest/defconfig new file mode 100644 index 0000000000000..7671ee9bc2eac --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/configs/ostest/defconfig @@ -0,0 +1,45 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-generic" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3_GENERIC=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-generic/configs/pwm/defconfig b/boards/risc-v/esp32c3/esp32c3-generic/configs/pwm/defconfig new file mode 100644 index 0000000000000..b284e6dd87147 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/configs/pwm/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-generic" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3_GENERIC=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_LEDC=y +CONFIG_ESPRESSIF_LEDC_TIMER0=y +CONFIG_EXAMPLES_PWM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-generic/configs/random/defconfig b/boards/risc-v/esp32c3/esp32c3-generic/configs/random/defconfig new file mode 100644 index 0000000000000..8aab7a02bfa07 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/configs/random/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-generic" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3_GENERIC=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_URANDOM=y +CONFIG_DEV_ZERO=y +CONFIG_EXAMPLES_RANDOM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2023 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-generic/configs/rmt/defconfig b/boards/risc-v/esp32c3/esp32c3-generic/configs/rmt/defconfig new file mode 100644 index 0000000000000..e22df83852090 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/configs/rmt/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NDEBUG is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-generic" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3_GENERIC=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESP_RMT=y +CONFIG_EXAMPLES_RMTCHAR=y +CONFIG_EXAMPLES_RMTCHAR_RX=y +CONFIG_EXAMPLES_RMTCHAR_RX_DEVPATH="/dev/rmt2" +CONFIG_EXAMPLES_RMTCHAR_TX=y +CONFIG_EXAMPLES_WS2812=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RMT=y +CONFIG_RMTCHAR=y +CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE=512 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WS2812=y +CONFIG_WS2812_LED_COUNT=100 +CONFIG_WS2812_NON_SPI_DRIVER=y diff --git a/boards/risc-v/esp32c3/esp32c3-generic/configs/rtc/defconfig b/boards/risc-v/esp32c3/esp32c3-generic/configs/rtc/defconfig new file mode 100644 index 0000000000000..819aaf3c82a95 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/configs/rtc/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-generic" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3_GENERIC=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_DATE=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_ALARM=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=4 +CONFIG_START_YEAR=2023 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-generic/configs/spiflash/defconfig b/boards/risc-v/esp32c3/esp32c3-generic/configs/spiflash/defconfig new file mode 100644 index 0000000000000..ee0a9f7a69e09 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/configs/spiflash/defconfig @@ -0,0 +1,54 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-generic" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3_GENERIC=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_SPIFLASH=y +CONFIG_ESPRESSIF_SPIFLASH_SMARTFS=y +CONFIG_ESPRESSIF_STORAGE_MTD_OFFSET=0x110000 +CONFIG_ESPRESSIF_STORAGE_MTD_SIZE=0xf0000 +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NAME_MAX=48 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_LOSMART=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_SMARTFS_MAXNAMLEN=48 +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_FLASH_ERASEALL=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_FSTEST=y +CONFIG_TESTING_FSTEST_MOUNTPT="/mnt" +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-generic/configs/sta_softap/defconfig b/boards/risc-v/esp32c3/esp32c3-generic/configs/sta_softap/defconfig new file mode 100644 index 0000000000000..21b3732119efc --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/configs/sta_softap/defconfig @@ -0,0 +1,82 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NDEBUG is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-generic" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3_GENERIC=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_ESPRESSIF_SPIFLASH=y +CONFIG_ESPRESSIF_SPIFLASH_SPIFFS=y +CONFIG_ESPRESSIF_WIFI=y +CONFIG_ESPRESSIF_WIFI_STATION_SOFTAP=y +CONFIG_EXAMPLES_DHCPD=y +CONFIG_EXAMPLES_RANDOM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=8192 +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_THROTTLE=24 +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETDEV_WORK_THREAD=y +CONFIG_NETUTILS_CJSON=y +CONFIG_NETUTILS_DHCPD=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_DELAYED_ACK=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_DEFAULT=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_TLS_TASK_NELEM=4 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y +CONFIG_WIRELESS_WAPI_INITCONF=y diff --git a/boards/risc-v/esp32c3/esp32c3-generic/configs/tickless/defconfig b/boards/risc-v/esp32c3/esp32c3-generic/configs/tickless/defconfig new file mode 100644 index 0000000000000..96acf24e7c820 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/configs/tickless/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-generic" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3_GENERIC=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_TICKLESS=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USEC_PER_TICK=10000 diff --git a/boards/risc-v/esp32c3/esp32c3-generic/configs/timers/defconfig b/boards/risc-v/esp32c3/esp32c3-generic/configs/timers/defconfig new file mode 100644 index 0000000000000..f17e504a732f0 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/configs/timers/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-generic" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3_GENERIC=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_EXAMPLES_ONESHOT=y +CONFIG_EXAMPLES_TIMER=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_ONESHOT=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=28 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2023 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_TIMER=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-generic/configs/twai/defconfig b/boards/risc-v/esp32c3/esp32c3-generic/configs/twai/defconfig new file mode 100644 index 0000000000000..19fa27569f4e2 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/configs/twai/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-generic" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3_GENERIC=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_TWAI0=y +CONFIG_EXAMPLES_CAN=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-generic/configs/usbconsole/defconfig b/boards/risc-v/esp32c3/esp32c3-generic/configs/usbconsole/defconfig new file mode 100644 index 0000000000000..abb43ab4fb750 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/configs/usbconsole/defconfig @@ -0,0 +1,46 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ESPRESSIF_UART0 is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-generic" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3_GENERIC=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_USBSERIAL=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y diff --git a/boards/risc-v/esp32c3/esp32c3-generic/configs/watchdog/defconfig b/boards/risc-v/esp32c3/esp32c3-generic/configs/watchdog/defconfig new file mode 100644 index 0000000000000..7920e537543c6 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/configs/watchdog/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-generic" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3_GENERIC=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_MWDT0=y +CONFIG_ESPRESSIF_MWDT1=y +CONFIG_EXAMPLES_WATCHDOG=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c3/esp32c3-generic/configs/wifi/defconfig b/boards/risc-v/esp32c3/esp32c3-generic/configs/wifi/defconfig new file mode 100644 index 0000000000000..57b13c7375e14 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/configs/wifi/defconfig @@ -0,0 +1,78 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NDEBUG is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c3-generic" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y +CONFIG_ARCH_CHIP="esp32c3" +CONFIG_ARCH_CHIP_ESP32C3_GENERIC=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_ESPRESSIF_SPIFLASH=y +CONFIG_ESPRESSIF_SPIFLASH_SPIFFS=y +CONFIG_ESPRESSIF_WIFI=y +CONFIG_EXAMPLES_RANDOM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=8192 +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_THROTTLE=24 +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETDEV_WORK_THREAD=y +CONFIG_NETUTILS_CJSON=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_DELAYED_ACK=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_DEFAULT=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_TLS_TASK_NELEM=4 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y +CONFIG_WIRELESS_WAPI_INITCONF=y diff --git a/boards/risc-v/esp32c3/esp32c3-generic/include/board.h b/boards/risc-v/esp32c3/esp32c3-generic/include/board.h new file mode 100644 index 0000000000000..a2adecb9abdc3 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/include/board.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/esp32c3-generic/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C3_ESP32C3_GENERIC_INCLUDE_BOARD_H +#define __BOARDS_RISCV_ESP32C3_ESP32C3_GENERIC_INCLUDE_BOARD_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* GPIO pins used by the GPIO Subsystem */ + +#define BOARD_NGPIOOUT 2 /* Amount of GPIO Output pins */ +#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ + +/* ESP32C3-Generic GPIOs ****************************************************/ + +/* BOOT Button */ + +#define BUTTON_BOOT 9 + +#endif /* __BOARDS_RISCV_ESP32C3_ESP32C3_GENERIC_INCLUDE_BOARD_H */ + diff --git a/boards/risc-v/esp32c3/esp32c3-generic/scripts/Make.defs b/boards/risc-v/esp32c3/esp32c3-generic/scripts/Make.defs new file mode 100644 index 0000000000000..28f81bf61a177 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/scripts/Make.defs @@ -0,0 +1,66 @@ +############################################################################ +# boards/risc-v/esp32c3/esp32c3-generic/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +########################################################################### + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/tools/espressif/Config.mk +include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs + +# Remove quotes from CONFIG_ESPRESSIF_CHIP_SERIES configuration + +CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES)) + +# Pick the linker scripts from the board level if they exist, if not +# pick the common linker scripts. + +ARCHSCRIPT += $(BOARD_COMMON_DIR)/scripts/$(CHIP_SERIES)_aliases.ld +ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_flat_memory.ld) + +ifeq ($(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_mcuboot_sections.ld) +else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_simple_boot_sections.ld) +else + ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_legacy_sections.ld) +endif + +ARCHPICFLAGS = -fpic + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -Werror=return-type -Werror +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) + +LDMODULEFLAGS = -melf32lriscv -r -e module_initialize +LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld) + +# ELF module definitions + +CELFFLAGS = $(CFLAGS) +CXXELFFLAGS = $(CXXFLAGS) + +LDELFFLAGS = -melf32lriscv -r -e main +LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/binfmt/libelf/gnu-elf.ld) diff --git a/boards/risc-v/esp32c3/esp32c3-generic/src/Make.defs b/boards/risc-v/esp32c3/esp32c3-generic/src/Make.defs new file mode 100644 index 0000000000000..b23cab8ea059c --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/src/Make.defs @@ -0,0 +1,43 @@ +############################################################################# +# boards/risc-v/esp32c3/esp32c3-generic/src/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +CSRCS = esp32c3_boot.c esp32c3_bringup.c + +ifeq ($(CONFIG_BOARDCTL),y) + CSRCS += esp32c3_appinit.c + + ifeq ($(CONFIG_BOARDCTL_RESET),y) + CSRCS += esp32c3_reset.c + endif +endif + +ifeq ($(CONFIG_DEV_GPIO),y) + CSRCS += esp32c3_gpio.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) + CSRCS += esp32c3_buttons.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3-generic.h b/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3-generic.h new file mode 100644 index 0000000000000..6311c461b42c2 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3-generic.h @@ -0,0 +1,119 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3-generic.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C3_ESP32C3_GENERIC_SRC_ESP32C3_GENERIC_H +#define __BOARDS_RISCV_ESP32C3_ESP32C3_GENERIC_SRC_ESP32C3_GENERIC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RMT gpio */ + +#define RMT_RXCHANNEL 2 +#define RMT_TXCHANNEL 0 + +#ifdef CONFIG_RMT_LOOP_TEST_MODE +# define RMT_INPUT_PIN 0 +# define RMT_OUTPUT_PIN 0 +#else +# define RMT_INPUT_PIN 2 +# define RMT_OUTPUT_PIN 8 +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_bringup + * + * Description: + * Perform architecture-specific initialization. + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y : + * Called from the NSH library via board_app_initialize(). + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int esp_bringup(void); + +/**************************************************************************** + * Name: board_twai_setup + * + * Description: + * Initialize TWAI and register the TWAI device + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_TWAI +int board_twai_setup(void); +#endif + +/**************************************************************************** + * Name: esp_gpio_init + * + * Description: + * Configure the GPIO driver. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +#ifdef CONFIG_DEV_GPIO +int esp_gpio_init(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISCV_ESP32C3_ESP32C3_GENERIC_SRC_ESP32C3_GENERIC_H */ diff --git a/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_appinit.c b/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_appinit.c new file mode 100644 index 0000000000000..431387e8c63db --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_appinit.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "esp32c3-generic.h" + +#ifdef CONFIG_BOARDCTL + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return esp_bringup(); +#endif +} + +#endif /* CONFIG_BOARDCTL */ diff --git a/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_boot.c b/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_boot.c new file mode 100644 index 0000000000000..c133d101a31ea --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_boot.c @@ -0,0 +1,89 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "riscv_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_board_initialize + * + * Description: + * All Espressif boards must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_board_initialize(void) +{ +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + esp_bringup(); +} +#endif diff --git a/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_bringup.c b/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_bringup.c new file mode 100644 index 0000000000000..1dd0f62e82bc9 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_bringup.c @@ -0,0 +1,268 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "esp_board_ledc.h" +#include "esp_board_spiflash.h" + +#ifdef CONFIG_WATCHDOG +# include "espressif/esp_wdt.h" +#endif + +#ifdef CONFIG_TIMER +# include "espressif/esp_timer.h" +#endif + +#ifdef CONFIG_ONESHOT +# include "espressif/esp_oneshot.h" +#endif + +#ifdef CONFIG_RTC_DRIVER +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_DEV_GPIO +# include "espressif/esp_gpio.h" +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_ESP_RMT +# include "esp_board_rmt.h" +#endif + +#ifdef CONFIG_ESPRESSIF_WIFI_BT_COEXIST +# include "esp_coexist_internal.h" +#endif + +#ifdef CONFIG_ESPRESSIF_WIFI +# include "esp_board_wlan.h" +#endif + +#include "esp32c3-generic.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_bringup + * + * Description: + * Perform architecture-specific initialization. + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y : + * Called from the NSH library via board_app_initialize(). + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int esp_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + _err("Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_TMPFS + /* Mount the tmpfs file system */ + + ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); + if (ret < 0) + { + _err("Failed to mount tmpfs at %s: %d\n", CONFIG_LIBC_TMPDIR, ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_MWDT0 + ret = esp_wdt_initialize("/dev/watchdog0", ESP_WDT_MWDT0); + if (ret < 0) + { + _err("Failed to initialize WDT: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_MWDT1 + ret = esp_wdt_initialize("/dev/watchdog1", ESP_WDT_MWDT1); + if (ret < 0) + { + _err("Failed to initialize WDT: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_RWDT + ret = esp_wdt_initialize("/dev/watchdog2", ESP_WDT_RWDT); + if (ret < 0) + { + _err("Failed to initialize WDT: %d\n", ret); + } +#endif + +#ifdef CONFIG_TIMER + ret = esp_timer_initialize(0); + if (ret < 0) + { + _err("Failed to initialize Timer 0: %d\n", ret); + } + +#ifndef CONFIG_ONESHOT + ret = esp_timer_initialize(1); + if (ret < 0) + { + _err("Failed to initialize Timer 1: %d\n", ret); + } +#endif +#endif + +#ifdef CONFIG_ESPRESSIF_SPIFLASH + ret = board_spiflash_init(); + if (ret) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI Flash\n"); + } +#endif + +#ifdef CONFIG_ESPRESSIF_WIFI_BT_COEXIST + esp_coex_adapter_register(&g_coex_adapter_funcs); + coex_pre_init(); +#endif + +#ifdef CONFIG_ESPRESSIF_WIFI + ret = board_wlan_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize wireless subsystem=%d\n", + ret); + } +#endif + +#ifdef CONFIG_ONESHOT + ret = esp_oneshot_initialize(); + if (ret < 0) + { + _err("Failed to initialize Oneshot Timer: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESP_RMT + ret = board_rmt_txinitialize(RMT_TXCHANNEL, RMT_OUTPUT_PIN); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); + } + + ret = board_rmt_rxinitialize(RMT_RXCHANNEL, RMT_INPUT_PIN); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_RTC_DRIVER + /* Initialize the RTC driver */ + + ret = esp_rtc_driverinit(); + if (ret < 0) + { + _err("Failed to initialize the RTC driver: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_TWAI + + /* Initialize TWAI and register the TWAI driver. */ + + ret = board_twai_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_twai_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DEV_GPIO + ret = esp_gpio_init(); + if (ret < 0) + { + ierr("Failed to initialize GPIO Driver: %d\n", ret); + } +#endif + +#if defined(CONFIG_INPUT_BUTTONS) && defined(CONFIG_INPUT_BUTTONS_LOWER) + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + ierr("ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_LEDC + ret = board_ledc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_ledc_setup() failed: %d\n", ret); + } +#endif /* CONFIG_ESPRESSIF_LEDC */ + + /* If we got here then perhaps not all initialization was successful, but + * at least enough succeeded to bring-up NSH with perhaps reduced + * capabilities. + */ + + return ret; +} diff --git a/boards/risc-v/espressif/esp32c3-generic/src/esp32c3_buttons.c b/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_buttons.c similarity index 98% rename from boards/risc-v/espressif/esp32c3-generic/src/esp32c3_buttons.c rename to boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_buttons.c index c1f2c06cbad35..71f07e7dd8fcf 100644 --- a/boards/risc-v/espressif/esp32c3-generic/src/esp32c3_buttons.c +++ b/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/espressif/esp32c3-generic/src/esp32c3_buttons.c + * boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_buttons.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -43,7 +43,7 @@ /* Arch */ -#include "esp_gpio.h" +#include "espressif/esp_gpio.h" /* Board */ diff --git a/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_gpio.c b/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_gpio.c new file mode 100644 index 0000000000000..f828b859db0d5 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_gpio.c @@ -0,0 +1,512 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Config */ + +#include + +/* Libc */ + +#include +#include +#include +#include + +/* NuttX */ + +#include +#include +#include + +/* Arch */ + +#include "espressif/esp_gpio.h" + +/* Board */ + +#include "esp32c3-generic.h" +#include + +/* HAL */ + +#include + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Pin 1 and 2 are used for this example as GPIO outputs. */ + +#define GPIO_OUT1 1 +#define GPIO_OUT2 2 + +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 +# error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" +#endif + +/* Interrupt pins. GPIO9 is used as an example, any other inputs could be + * used. + */ + +#define GPIO_IRQPIN 9 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct espgpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct espgpint_dev_s +{ + struct espgpio_dev_s espgpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +static int gpout_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e pintype); +#endif + +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); +static int gpint_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e pintype); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, + .go_setpintype = gpout_setpintype, +}; + +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, GPIO_OUT2 +}; + +static struct espgpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, + .go_setpintype = gpint_setpintype, +}; + +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_IRQPIN, +}; + +static struct espgpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpout_read + * + * Description: + * Read a digital output pin. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * value - A pointer to store the state of the pin. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct espgpio_dev_s *espgpio = (struct espgpio_dev_s *)dev; + + DEBUGASSERT(espgpio != NULL && value != NULL); + DEBUGASSERT(espgpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = esp_gpioread(g_gpiooutputs[espgpio->id]); + return OK; +} + +/**************************************************************************** + * Name: gpout_write + * + * Description: + * Write to a digital output pin. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * value - The value to be written. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct espgpio_dev_s *espgpio = (struct espgpio_dev_s *)dev; + + DEBUGASSERT(espgpio != NULL); + DEBUGASSERT(espgpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + esp_gpiowrite(g_gpiooutputs[espgpio->id], value); + return OK; +} + +/**************************************************************************** + * Name: gpout_setpintype + * + * Description: + * Set digital output pin type. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * pintype - The pin type. See nuttx/ioexpander/gpio.h. + * + * Returned Value: + * Zero (OK) on success; -1 (ERROR) otherwise. + * + ****************************************************************************/ + +static int gpout_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e pintype) +{ + struct espgpio_dev_s *espgpio = (struct espgpio_dev_s *)dev; + + DEBUGASSERT(espgpio != NULL); + DEBUGASSERT(espgpio->id < BOARD_NGPIOOUT); + gpioinfo("Setting pintype: %d\n", (int)pintype); + + esp_gpio_matrix_out(g_gpiooutputs[espgpio->id], + SIG_GPIO_OUT_IDX, 0, 0); + + switch (pintype) + { + case GPIO_INPUT_PIN: + esp_configgpio(g_gpiooutputs[espgpio->id], INPUT); + break; + case GPIO_INPUT_PIN_PULLUP: + esp_configgpio(g_gpiooutputs[espgpio->id], INPUT_PULLUP); + break; + case GPIO_INPUT_PIN_PULLDOWN: + esp_configgpio(g_gpiooutputs[espgpio->id], INPUT_PULLDOWN); + break; + case GPIO_OUTPUT_PIN: + esp_configgpio(g_gpiooutputs[espgpio->id], INPUT | OUTPUT); + break; + case GPIO_OUTPUT_PIN_OPENDRAIN: + esp_configgpio(g_gpiooutputs[espgpio->id], + INPUT | OUTPUT_OPEN_DRAIN); + break; + default: + return ERROR; + break; + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: espgpio_interrupt + * + * Description: + * Digital input interrupt handler. + * + * Input Parameters: + * irq - Identifier of the interrupt request. + * context - Context data from the ISR. + * arg - Opaque pointer to the internal driver state structure. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +#if BOARD_NGPIOINT > 0 +static int espgpio_interrupt(int irq, void *context, void *arg) +{ + struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)arg; + + DEBUGASSERT(espgpint != NULL && espgpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", espgpint->callback); + + espgpint->callback(&espgpint->espgpio.gpio, espgpint->espgpio.id); + return OK; +} + +/**************************************************************************** + * Name: gpint_read + * + * Description: + * Read a digital input pin. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * value - A pointer to store the state of the pin. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct espgpint_dev_s *espgpint = + (struct espgpint_dev_s *)dev; + + DEBUGASSERT(espgpint != NULL && value != NULL); + DEBUGASSERT(espgpint->espgpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = esp_gpioread(g_gpiointinputs[espgpint->espgpio.id]); + return OK; +} + +/**************************************************************************** + * Name: gpint_attach + * + * Description: + * Attach the ISR to IRQ and register the callback. But it still doesn't + * enable interrupt yet. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * callback - User callback function. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct espgpint_dev_s *espgpint = + (struct espgpint_dev_s *)dev; + int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); + int ret; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(irq); + ret = irq_attach(irq, + espgpio_interrupt, + &g_gpint[espgpint->espgpio.id]); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); + return ret; + } + + gpioinfo("Attach %p\n", callback); + espgpint->callback = callback; + return OK; +} + +/**************************************************************************** + * Name: gpint_enable + * + * Description: + * Enable/Disable interrupt. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * enable - True to enable, false to disable. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; + int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); + + if (enable) + { + if (espgpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + esp_gpioirqenable(irq, RISING); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + esp_gpioirqdisable(irq); + } + + return OK; +} + +/**************************************************************************** + * Name: gpint_setpintype + * + * Description: + * Set digital interrupt pin type. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * pintype - The pin type. See nuttx/ioexpander/gpio.h. + * + * Returned Value: + * Zero (OK) on success; -1 (ERROR) otherwise. + * + ****************************************************************************/ + +static int gpint_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e pintype) +{ + struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; + + DEBUGASSERT(espgpint != NULL); + DEBUGASSERT(espgpint->espgpio.id < BOARD_NGPIOINT); + gpioinfo("Setting pintype: %d\n", (int)pintype); + switch (pintype) + { + case GPIO_INTERRUPT_HIGH_PIN: + esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], + INPUT_PULLUP); + break; + case GPIO_INTERRUPT_LOW_PIN: + esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], + INPUT_PULLDOWN); + break; + default: + return ERROR; + break; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_gpio_init + * + * Description: + * Configure the GPIO driver. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +int esp_gpio_init(void) +{ + int pincount = 0; + int i; + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pins that will be used as output */ + + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_1 | INPUT_FUNCTION_1); + esp_gpiowrite(g_gpiooutputs[i], 0); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].espgpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].espgpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].espgpio.id = i; + gpio_pin_register(&g_gpint[i].espgpio.gpio, pincount); + + /* Configure the pins that will be used as interrupt input */ + + esp_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_1 | PULLDOWN); + + pincount++; + } +#endif + + return OK; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_reset.c b/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_reset.c new file mode 100644 index 0000000000000..5d5981518a753 --- /dev/null +++ b/boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_reset.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/risc-v/esp32c3/esp32c3-generic/src/esp32c3_reset.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "espressif/esp_systemreset.h" + +#ifdef CONFIG_BOARDCTL_RESET + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value in this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ + syslog(LOG_INFO, "reboot status=%d\n", status); + + switch (status) + { + case EXIT_SUCCESS: + up_shutdown_handler(); + break; + case CONFIG_BOARD_ASSERT_RESET_VALUE: + default: + break; + } + + up_systemreset(); + + return 0; +} + +#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/risc-v/esp32c6/common/Kconfig b/boards/risc-v/esp32c6/common/Kconfig new file mode 100644 index 0000000000000..711e47f2d55bf --- /dev/null +++ b/boards/risc-v/esp32c6/common/Kconfig @@ -0,0 +1,50 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +config ESPRESSIF_MERGE_BINS + bool "Merge raw binary files into a single file" + default n + ---help--- + Merge the raw binary files into a single file for flashing to the + device. + This is only useful when the path to binary files (e.g. bootloader) + is provided via the ESPTOOL_BINDIR variable. + +choice ESPRESSIF_SPIFLASH_FS + prompt "Mount SPI Flash MTD on bring-up" + default ESPRESSIF_SPIFLASH_SMARTFS + depends on ESPRESSIF_MTD + optional + ---help--- + Mount the SPI Flash MTD with the selected File System format on board + bring-up. + If not selected, the MTD will be registered as a device node on /dev. + +config ESPRESSIF_SPIFLASH_SMARTFS + bool "SmartFS" + select FS_SMARTFS + select MTD_SMART + +config ESPRESSIF_SPIFLASH_NXFFS + bool "NXFFS" + select FS_NXFFS + +config ESPRESSIF_SPIFLASH_SPIFFS + bool "SPIFFS" + select FS_SPIFFS + +config ESPRESSIF_SPIFLASH_LITTLEFS + bool "LittleFS" + select FS_LITTLEFS + +config ESPRESSIF_SPIFLASH_MTD_CONFIG + bool "Non-volatile storage" + +endchoice # ESPRESSIF_SPIFLASH_FS + +config ESPRESSIF_SPIFLASH_FS_MOUNT_PT + string "File-system Mount Point" + depends on ESPRESSIF_SPIFLASH_LITTLEFS + default "/data" diff --git a/boards/risc-v/esp32c6/common/Makefile b/boards/risc-v/esp32c6/common/Makefile index e3eff7f6f00da..f6fc6ec001c3e 100644 --- a/boards/risc-v/esp32c6/common/Makefile +++ b/boards/risc-v/esp32c6/common/Makefile @@ -21,9 +21,13 @@ include $(TOPDIR)/Make.defs include board/Make.defs +include src/Make.defs DEPPATH += --dep-path board +DEPPATH += --dep-path src include $(TOPDIR)/boards/Board.mk -BOARDDIR = $(ARCHSRCDIR)$(DELIM)board \ No newline at end of file +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/risc-v/esp32c6/common/include/esp_board_ledc.h b/boards/risc-v/esp32c6/common/include/esp_board_ledc.h new file mode 100644 index 0000000000000..cbdb9378f9ed7 --- /dev/null +++ b/boards/risc-v/esp32c6/common/include/esp_board_ledc.h @@ -0,0 +1,74 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/common/include/esp_board_ledc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C6_COMMON_INCLUDE_ESP_BOARD_LEDC_H +#define __BOARDS_RISCV_ESP32C6_COMMON_INCLUDE_ESP_BOARD_LEDC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ledc_setup + * + * Description: + * Initialize LEDC PWM and register the PWM device. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_LEDC +int board_ledc_setup(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISCV_ESP32C6_COMMON_INCLUDE_ESP_BOARD_LEDC_H */ diff --git a/boards/risc-v/esp32c6/common/include/esp_board_rmt.h b/boards/risc-v/esp32c6/common/include/esp_board_rmt.h new file mode 100644 index 0000000000000..eae34fa67111c --- /dev/null +++ b/boards/risc-v/esp32c6/common/include/esp_board_rmt.h @@ -0,0 +1,97 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/common/include/esp_board_rmt.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISC_V_ESP32C6_COMMON_INCLUDE_ESP_BOARD_RMT_H +#define __BOARDS_RISC_V_ESP32C6_COMMON_INCLUDE_ESP_BOARD_RMT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_ESP_RMT + +/**************************************************************************** + * Name: board_rmt_rxinitialize + * + * Description: + * Initialize the RMT peripheral and register an RX device. + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the RX channel + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_rmt_rxinitialize(int ch, int pin); + +/**************************************************************************** + * Name: board_rmt_txinitialize + * + * Description: + * Initialize the RMT peripheral and register an TX device. + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the TX channel + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_rmt_txinitialize(int ch, int pin); + +#endif /* CONFIG_ESP_RMT */ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISC_V_ESP32C6_COMMON_INCLUDE_ESP_BOARD_RMT_H */ diff --git a/boards/risc-v/esp32c6/common/include/esp_board_spiflash.h b/boards/risc-v/esp32c6/common/include/esp_board_spiflash.h new file mode 100644 index 0000000000000..cf05e85b98616 --- /dev/null +++ b/boards/risc-v/esp32c6/common/include/esp_board_spiflash.h @@ -0,0 +1,74 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/common/include/esp_board_spiflash.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C6_COMMON_INCLUDE_ESP_BOARD_SPIFLASH_H +#define __BOARDS_RISCV_ESP32C6_COMMON_INCLUDE_ESP_BOARD_SPIFLASH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_spiflash_init + * + * Description: + * Initialize the SPIFLASH and register the MTD device. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_SPIFLASH +int board_spiflash_init(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISCV_ESP32C6_COMMON_INCLUDE_ESP_BOARD_SPIFLASH_H */ diff --git a/boards/risc-v/esp32c6/common/include/esp_board_wlan.h b/boards/risc-v/esp32c6/common/include/esp_board_wlan.h new file mode 100644 index 0000000000000..1334eef607d70 --- /dev/null +++ b/boards/risc-v/esp32c6/common/include/esp_board_wlan.h @@ -0,0 +1,73 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/common/include/esp_board_wlan.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C6_COMMON_INCLUDE_ESP_BOARD_WLAN_H +#define __BOARDS_RISCV_ESP32C6_COMMON_INCLUDE_ESP_BOARD_WLAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_WIFI + +/**************************************************************************** + * Name: board_wlan_init + * + * Description: + * Configure the wireless subsystem. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int board_wlan_init(void); + +#endif /* CONFIG_ESPRESSIF_WIFI */ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISCV_ESP32C6_COMMON_INCLUDE_ESP_BOARD_WLAN_H */ diff --git a/boards/risc-v/esp32c6/common/scripts/.gitignore b/boards/risc-v/esp32c6/common/scripts/.gitignore index c34dcbe02fa04..0fa3d8108a58d 100644 --- a/boards/risc-v/esp32c6/common/scripts/.gitignore +++ b/boards/risc-v/esp32c6/common/scripts/.gitignore @@ -1,2 +1 @@ /*.ld.tmp - diff --git a/boards/risc-v/esp32c6/common/scripts/common.ld b/boards/risc-v/esp32c6/common/scripts/common.ld new file mode 100644 index 0000000000000..09d1012918e97 --- /dev/null +++ b/boards/risc-v/esp32c6/common/scripts/common.ld @@ -0,0 +1,35 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/common/scripts/common.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ +#include + +#if CONFIG_ESPRESSIF_SOC_RTC_MEM_SUPPORTED +# define ESP_BOOTLOADER_RESERVE_RTC 0 + + /* rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files). + * For rtc_timer_data_in_rtc_mem section. + */ +# define RTC_TIMER_RESERVE_RTC (24) + +# ifdef CONFIG_ARCH_CHIP_ESP32 +# define RESERVE_RTC_MEM (RTC_TIMER_RESERVE_RTC) +# else +# define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC) +# endif /* CONFIG_ARCH_CHIP_ESP32 */ +#endif /* CONFIG_ESPRESSIF_SOC_RTC_MEM_SUPPORTED */ diff --git a/boards/risc-v/espressif/common/scripts/esp32c6_aliases.ld b/boards/risc-v/esp32c6/common/scripts/esp32c6_aliases.ld similarity index 82% rename from boards/risc-v/espressif/common/scripts/esp32c6_aliases.ld rename to boards/risc-v/esp32c6/common/scripts/esp32c6_aliases.ld index 29335e191c66a..65e91e5bd1f6b 100644 --- a/boards/risc-v/espressif/common/scripts/esp32c6_aliases.ld +++ b/boards/risc-v/esp32c6/common/scripts/esp32c6_aliases.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/espressif/common/scripts/esp32c6_aliases.ld + * boards/risc-v/esp32c6/common/scripts/esp32c6_aliases.ld * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,6 +18,11 @@ * ****************************************************************************/ +cache_set_idrom_mmu_size = Cache_Set_IDROM_MMU_Size; +cache_resume_icache = Cache_Resume_ICache; +cache_suspend_icache = Cache_Suspend_ICache; +cache_invalidate_icache_all = Cache_Invalidate_ICache_All; + #ifdef CONFIG_ESPRESSIF_BLE /* Lower-case aliases for BLE library symbols not compliant to nxstyle */ diff --git a/boards/risc-v/espressif/common/scripts/esp32c6_flat_memory.ld b/boards/risc-v/esp32c6/common/scripts/esp32c6_flat_memory.ld similarity index 92% rename from boards/risc-v/espressif/common/scripts/esp32c6_flat_memory.ld rename to boards/risc-v/esp32c6/common/scripts/esp32c6_flat_memory.ld index 3517df7fdb1bd..9660b328216ba 100644 --- a/boards/risc-v/espressif/common/scripts/esp32c6_flat_memory.ld +++ b/boards/risc-v/esp32c6/common/scripts/esp32c6_flat_memory.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/espressif/common/scripts/esp32c6_flat_memory.ld + * boards/risc-v/esp32c6/common/scripts/esp32c6_flat_memory.ld * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -34,11 +34,9 @@ #define SRAM_IRAM_START 0x40800000 #define SRAM_DRAM_START 0x40800000 -#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) - /* 2nd stage bootloader iram_loader_seg start address */ -#define SRAM_DRAM_END (0x4086e610 - I_D_SRAM_OFFSET) +#define SRAM_DRAM_END (0x4086e610) #define SRAM_IRAM_ORG (SRAM_IRAM_START) #define SRAM_DRAM_ORG (SRAM_DRAM_START) @@ -54,6 +52,11 @@ MEMORY { +#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT + ROM (R) : org = ORIGIN(ROM), + len = IDRAM0_2_SEG_SIZE +#endif + /* Below values assume the flash cache is on, and have the blocks this * uses subtracted from the length of the various regions. The 'data access * port' dram/drom regions map to the same iram/irom regions but are @@ -71,7 +74,7 @@ MEMORY * constraint that (paddr % 64KB == vaddr % 64KB). */ - irom_seg (RX) : org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20 + irom_seg (RX) : org = 0x42000000, len = IDRAM0_2_SEG_SIZE /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. * Enabling Bluetooth & Trace Memory features in menuconfig will decrease @@ -89,7 +92,7 @@ MEMORY * constraint that (paddr % 64KB == vaddr % 64KB). */ - drom_seg (R) : org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20 + drom_seg (R) : org = 0x42000000, len = IDRAM0_2_SEG_SIZE /* RTC fast memory (executable). Persists over deep sleep. */ diff --git a/boards/risc-v/espressif/common/scripts/esp32c6_legacy_sections.ld b/boards/risc-v/esp32c6/common/scripts/esp32c6_legacy_sections.ld similarity index 97% rename from boards/risc-v/espressif/common/scripts/esp32c6_legacy_sections.ld rename to boards/risc-v/esp32c6/common/scripts/esp32c6_legacy_sections.ld index 95a878a294e79..522befd967d21 100644 --- a/boards/risc-v/espressif/common/scripts/esp32c6_legacy_sections.ld +++ b/boards/risc-v/esp32c6/common/scripts/esp32c6_legacy_sections.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/espressif/common/scripts/esp32c6_legacy_sections.ld + * boards/risc-v/esp32c6/common/scripts/esp32c6_legacy_sections.ld * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -83,31 +83,6 @@ SECTIONS . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; } >dram0_0_seg - /* Shared RAM */ - - .dram0.bss (NOLOAD) : - { - . = ALIGN(8); - _sbss = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.share.mem) - *(.gnu.linkonce.b.*) - *(COMMON) - - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } >dram0_0_seg - .noinit (NOLOAD): { /* This section contains data that is not initialized during load, @@ -153,10 +128,31 @@ SECTIONS *libsched.a:irq_dispatch.*(.rodata .rodata.*) . = ALIGN(4); _edata = ABSOLUTE(.); + } >dram0_0_seg - /* Heap starts at the end of .data */ + /* Shared RAM */ - _sheap = ABSOLUTE(.); + .dram0.bss (NOLOAD) : + { + . = ALIGN(8); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + + . = ALIGN(32); + _ebss = ABSOLUTE(.); } >dram0_0_seg .flash.text : diff --git a/boards/risc-v/esp32c6/common/scripts/esp32c6_rom.ld b/boards/risc-v/esp32c6/common/scripts/esp32c6_rom.ld deleted file mode 100644 index 5a4177d1ca286..0000000000000 --- a/boards/risc-v/esp32c6/common/scripts/esp32c6_rom.ld +++ /dev/null @@ -1,517 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c6/common/scripts/esp32c6_rom.ld - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* ROM function interface esp32c6_rom.ld for esp32c6 - * - * - * Generated from ./interface-esp32c6.yml md5sum 93b28a9e1fe42d212018eb4336849208 - * - * Compatible with ROM where ECO version equal or greater to 0. - * - * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. - */ - -/*************************************** - Group common - ***************************************/ - -/* Functions */ -rtc_get_reset_reason = 0x40000018; -analog_super_wdt_reset_happened = 0x4000001c; -rtc_get_wakeup_cause = 0x40000020; -rtc_unhold_all_pads = 0x40000024; -ets_printf = 0x40000028; -ets_install_putc1 = 0x4000002c; -ets_install_putc2 = 0x40000030; -ets_install_uart_printf = 0x40000034; -ets_install_usb_printf = 0x40000038; -ets_get_printf_channel = 0x4000003c; -ets_delay_us = 0x40000040; -ets_get_cpu_frequency = 0x40000044; -ets_update_cpu_frequency = 0x40000048; -ets_install_lock = 0x4000004c; -UartRxString = 0x40000050; -UartGetCmdLn = 0x40000054; -uart_tx_one_char = 0x40000058; -uart_tx_one_char2 = 0x4000005c; -uart_rx_one_char = 0x40000060; -uart_rx_one_char_block = 0x40000064; -uart_rx_intr_handler = 0x40000068; -uart_rx_readbuff = 0x4000006c; -uartAttach = 0x40000070; -uart_tx_flush = 0x40000074; -uart_tx_wait_idle = 0x40000078; -uart_div_modify = 0x4000007c; -ets_write_char_uart = 0x40000080; -uart_tx_switch = 0x40000084; -roundup2 = 0x40000088; -multofup = 0x4000008c; -software_reset = 0x40000090; -software_reset_cpu = 0x40000094; -ets_clk_assist_debug_clock_enable = 0x40000098; -clear_super_wdt_reset_flag = 0x4000009c; -disable_default_watchdog = 0x400000a0; -esp_rom_set_rtc_wake_addr = 0x400000a4; -esp_rom_get_rtc_wake_addr = 0x400000a8; -send_packet = 0x400000ac; -recv_packet = 0x400000b0; -GetUartDevice = 0x400000b4; -UartDwnLdProc = 0x400000b8; -GetSecurityInfoProc = 0x400000bc; -Uart_Init = 0x400000c0; -ets_set_user_start = 0x400000c4; -/* Data (.data, .bss, .rodata) */ -ets_rom_layout_p = 0x4004fffc; -ets_ops_table_ptr = 0x4087fff8; -g_saved_pc = 0x4087fffc; - - -/*************************************** - Group miniz - ***************************************/ - -/* Functions */ -mz_adler32 = 0x400000c8; -mz_free = 0x400000cc; -tdefl_compress = 0x400000d0; -tdefl_compress_buffer = 0x400000d4; -tdefl_compress_mem_to_heap = 0x400000d8; -tdefl_compress_mem_to_mem = 0x400000dc; -tdefl_compress_mem_to_output = 0x400000e0; -tdefl_get_adler32 = 0x400000e4; -tdefl_get_prev_return_status = 0x400000e8; -tdefl_init = 0x400000ec; -tdefl_write_image_to_png_file_in_memory = 0x400000f0; -tdefl_write_image_to_png_file_in_memory_ex = 0x400000f4; -tinfl_decompress = 0x400000f8; -tinfl_decompress_mem_to_callback = 0x400000fc; -tinfl_decompress_mem_to_heap = 0x40000100; -tinfl_decompress_mem_to_mem = 0x40000104; - - -/*************************************** - Group tjpgd - ***************************************/ - -/* Functions */ -jd_prepare = 0x40000108; -jd_decomp = 0x4000010c; - - -/*************************************** - Group spiflash_legacy - ***************************************/ - -/* Functions */ -esp_rom_spiflash_wait_idle = 0x40000110; -esp_rom_spiflash_write_encrypted = 0x40000114; -esp_rom_spiflash_write_encrypted_dest = 0x40000118; -esp_rom_spiflash_write_encrypted_enable = 0x4000011c; -esp_rom_spiflash_write_encrypted_disable = 0x40000120; -esp_rom_spiflash_erase_chip = 0x40000124; -_esp_rom_spiflash_erase_sector = 0x40000128; -_esp_rom_spiflash_erase_block = 0x4000012c; -_esp_rom_spiflash_write = 0x40000130; -_esp_rom_spiflash_read = 0x40000134; -_esp_rom_spiflash_unlock = 0x40000138; -_SPIEraseArea = 0x4000013c; -_SPI_write_enable = 0x40000140; -esp_rom_spiflash_erase_sector = 0x40000144; -esp_rom_spiflash_erase_block = 0x40000148; -esp_rom_spiflash_write = 0x4000014c; -esp_rom_spiflash_read = 0x40000150; -esp_rom_spiflash_unlock = 0x40000154; -SPIEraseArea = 0x40000158; -SPI_write_enable = 0x4000015c; -esp_rom_spiflash_config_param = 0x40000160; -esp_rom_spiflash_read_user_cmd = 0x40000164; -esp_rom_spiflash_select_qio_pins = 0x40000168; -esp_rom_spi_flash_auto_sus_res = 0x4000016c; -esp_rom_spi_flash_send_resume = 0x40000170; -esp_rom_spi_flash_update_id = 0x40000174; -esp_rom_spiflash_config_clk = 0x40000178; -esp_rom_spiflash_config_readmode = 0x4000017c; -esp_rom_spiflash_read_status = 0x40000180; -esp_rom_spiflash_read_statushigh = 0x40000184; -esp_rom_spiflash_write_status = 0x40000188; -spi_cache_mode_switch = 0x4000018c; -spi_common_set_dummy_output = 0x40000190; -spi_common_set_flash_cs_timing = 0x40000194; -esp_rom_spi_set_address_bit_len = 0x40000198; -SPILock = 0x4000019c; -SPIMasterReadModeCnfig = 0x400001a0; -SPI_Common_Command = 0x400001a4; -SPI_WakeUp = 0x400001a8; -SPI_block_erase = 0x400001ac; -SPI_chip_erase = 0x400001b0; -SPI_init = 0x400001b4; -SPI_page_program = 0x400001b8; -SPI_read_data = 0x400001bc; -SPI_sector_erase = 0x400001c0; -SelectSpiFunction = 0x400001c4; -SetSpiDrvs = 0x400001c8; -Wait_SPI_Idle = 0x400001cc; -spi_dummy_len_fix = 0x400001d0; -Disable_QMode = 0x400001d4; -Enable_QMode = 0x400001d8; -spi_flash_attach = 0x400001dc; -spi_flash_get_chip_size = 0x400001e0; -spi_flash_guard_set = 0x400001e4; -spi_flash_guard_get = 0x400001e8; -spi_flash_read_encrypted = 0x400001ec; -/* Data (.data, .bss, .rodata) */ -rom_spiflash_legacy_funcs = 0x4087fff0; -rom_spiflash_legacy_data = 0x4087ffec; -g_flash_guard_ops = 0x4087fff4; - -/* Note: esp_rom_spiflash_write_disable was moved from esp32c6.rom.spiflash.ld */ -esp_rom_spiflash_write_disable = 0x40000278; - -/*************************************** - Group hal_wdt - ***************************************/ - -/* Functions */ -wdt_hal_init = 0x40000394; -wdt_hal_deinit = 0x40000398; -wdt_hal_config_stage = 0x4000039c; -wdt_hal_write_protect_disable = 0x400003a0; -wdt_hal_write_protect_enable = 0x400003a4; -wdt_hal_enable = 0x400003a8; -wdt_hal_disable = 0x400003ac; -wdt_hal_handle_intr = 0x400003b0; -wdt_hal_feed = 0x400003b4; -wdt_hal_set_flashboot_en = 0x400003b8; -wdt_hal_is_enabled = 0x400003bc; - - -/*************************************** - Group hal_systimer - ***************************************/ - -/* Functions */ -/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */ -/* systimer_hal_init = 0x400003c0; */ -/* systimer_hal_deinit = 0x400003c4; */ - -systimer_hal_set_tick_rate_ops = 0x400003c8; -systimer_hal_get_counter_value = 0x400003cc; -systimer_hal_get_time = 0x400003d0; -systimer_hal_set_alarm_target = 0x400003d4; -systimer_hal_set_alarm_period = 0x400003d8; -systimer_hal_get_alarm_value = 0x400003dc; -systimer_hal_enable_alarm_int = 0x400003e0; -systimer_hal_on_apb_freq_update = 0x400003e4; -systimer_hal_counter_value_advance = 0x400003e8; -systimer_hal_enable_counter = 0x400003ec; -systimer_hal_select_alarm_mode = 0x400003f0; -systimer_hal_connect_alarm_counter = 0x400003f4; -systimer_hal_counter_can_stall_by_cpu = 0x400003f8; - - -/*************************************** - Group cache - ***************************************/ - -/* Functions */ -Cache_Get_ICache_Line_Size = 0x40000628; -Cache_Get_Mode = 0x4000062c; -Cache_Address_Through_Cache = 0x40000630; -ROM_Boot_Cache_Init = 0x40000634; -MMU_Set_Page_Mode = 0x40000638; -MMU_Get_Page_Mode = 0x4000063c; -Cache_Invalidate_ICache_Items = 0x40000640; -Cache_Op_Addr = 0x40000644; -Cache_Invalidate_Addr = 0x40000648; -Cache_Invalidate_ICache_All = 0x4000064c; -Cache_Mask_All = 0x40000650; -Cache_UnMask_Dram0 = 0x40000654; -Cache_Suspend_ICache_Autoload = 0x40000658; -Cache_Resume_ICache_Autoload = 0x4000065c; -Cache_Start_ICache_Preload = 0x40000660; -Cache_ICache_Preload_Done = 0x40000664; -Cache_End_ICache_Preload = 0x40000668; -Cache_Config_ICache_Autoload = 0x4000066c; -Cache_Enable_ICache_Autoload = 0x40000670; -Cache_Disable_ICache_Autoload = 0x40000674; -Cache_Enable_ICache_PreLock = 0x40000678; -Cache_Disable_ICache_PreLock = 0x4000067c; -Cache_Lock_ICache_Items = 0x40000680; -Cache_Unlock_ICache_Items = 0x40000684; -Cache_Lock_Addr = 0x40000688; -Cache_Unlock_Addr = 0x4000068c; -Cache_Disable_ICache = 0x40000690; -Cache_Enable_ICache = 0x40000694; -Cache_Suspend_ICache = 0x40000698; -Cache_Resume_ICache = 0x4000069c; -Cache_Freeze_ICache_Enable = 0x400006a0; -Cache_Freeze_ICache_Disable = 0x400006a4; -Cache_Set_IDROM_MMU_Size = 0x400006a8; -Cache_Get_IROM_MMU_End = 0x400006ac; -Cache_Get_DROM_MMU_End = 0x400006b0; -Cache_MMU_Init = 0x400006b4; -Cache_MSPI_MMU_Set = 0x400006b8; -Cache_Travel_Tag_Memory = 0x400006bc; -Cache_Get_Virtual_Addr = 0x400006c0; -/* Data (.data, .bss, .rodata) */ -rom_cache_op_cb = 0x4087ffcc; -rom_cache_internal_table_ptr = 0x4087ffc8; - - -/*************************************** - Group clock - ***************************************/ - -/* Functions */ -ets_clk_get_xtal_freq = 0x400006c4; -ets_clk_get_cpu_freq = 0x400006c8; -ets_clk_apb_wait_ready = 0x400006cc; -ets_clk_mspi_apb_wait_ready = 0x400006d0; - - -/*************************************** - Group gpio - ***************************************/ - -/* Functions */ -gpio_input_get = 0x400006d4; -gpio_matrix_in = 0x400006d8; -gpio_matrix_out = 0x400006dc; -gpio_output_disable = 0x400006e0; -gpio_output_enable = 0x400006e4; -gpio_output_set = 0x400006e8; -gpio_pad_hold = 0x400006ec; -gpio_pad_input_disable = 0x400006f0; -gpio_pad_input_enable = 0x400006f4; -gpio_pad_pulldown = 0x400006f8; -gpio_pad_pullup = 0x400006fc; -gpio_pad_select_gpio = 0x40000700; -gpio_pad_set_drv = 0x40000704; -gpio_pad_unhold = 0x40000708; -gpio_pin_wakeup_disable = 0x4000070c; -gpio_pin_wakeup_enable = 0x40000710; -gpio_bypass_matrix_in = 0x40000714; - - -/*************************************** - Group interrupts - ***************************************/ - -/* Functions */ -esprv_intc_int_set_priority = 0x40000718; -esprv_intc_int_set_threshold = 0x4000071c; -esprv_intc_int_enable = 0x40000720; -esprv_intc_int_disable = 0x40000724; -esprv_intc_int_set_type = 0x40000728; -PROVIDE( intr_handler_set = 0x4000072c ); -intr_matrix_set = 0x40000730; -ets_intr_lock = 0x40000734; -ets_intr_unlock = 0x40000738; -ets_isr_attach = 0x4000073c; -ets_isr_mask = 0x40000740; -ets_isr_unmask = 0x40000744; - - -/*************************************** - Group crypto - ***************************************/ - -/* Functions */ -md5_vector = 0x40000748; -MD5Init = 0x4000074c; -MD5Update = 0x40000750; -MD5Final = 0x40000754; -crc32_le = 0x40000758; -crc16_le = 0x4000075c; -crc8_le = 0x40000760; -crc32_be = 0x40000764; -crc16_be = 0x40000768; -crc8_be = 0x4000076c; -esp_crc8 = 0x40000770; -ets_sha_enable = 0x40000774; -ets_sha_disable = 0x40000778; -ets_sha_get_state = 0x4000077c; -ets_sha_init = 0x40000780; -ets_sha_process = 0x40000784; -ets_sha_starts = 0x40000788; -ets_sha_update = 0x4000078c; -ets_sha_finish = 0x40000790; -ets_sha_clone = 0x40000794; -ets_hmac_enable = 0x40000798; -ets_hmac_disable = 0x4000079c; -ets_hmac_calculate_message = 0x400007a0; -ets_hmac_calculate_downstream = 0x400007a4; -ets_hmac_invalidate_downstream = 0x400007a8; -ets_jtag_enable_temporarily = 0x400007ac; -ets_aes_enable = 0x400007b0; -ets_aes_disable = 0x400007b4; -ets_aes_setkey = 0x400007b8; -ets_aes_block = 0x400007bc; -ets_aes_setkey_dec = 0x400007c0; -ets_aes_setkey_enc = 0x400007c4; -ets_bigint_enable = 0x400007c8; -ets_bigint_disable = 0x400007cc; -ets_bigint_multiply = 0x400007d0; -ets_bigint_modmult = 0x400007d4; -ets_bigint_modexp = 0x400007d8; -ets_bigint_wait_finish = 0x400007dc; -ets_bigint_getz = 0x400007e0; -ets_ds_enable = 0x400007e4; -ets_ds_disable = 0x400007e8; -ets_ds_start_sign = 0x400007ec; -ets_ds_is_busy = 0x400007f0; -ets_ds_finish_sign = 0x400007f4; -ets_ds_encrypt_params = 0x400007f8; -ets_mgf1_sha256 = 0x400007fc; -/* Data (.data, .bss, .rodata) */ -crc32_le_table_ptr = 0x4004fff8; -crc16_le_table_ptr = 0x4004fff4; -crc8_le_table_ptr = 0x4004fff0; -crc32_be_table_ptr = 0x4004ffec; -crc16_be_table_ptr = 0x4004ffe8; -crc8_be_table_ptr = 0x4004ffe4; - - -/*************************************** - Group efuse - ***************************************/ - -/* Functions */ -ets_efuse_read = 0x40000800; -ets_efuse_program = 0x40000804; -ets_efuse_clear_program_registers = 0x40000808; -ets_efuse_write_key = 0x4000080c; -ets_efuse_get_read_register_address = 0x40000810; -ets_efuse_get_key_purpose = 0x40000814; -ets_efuse_key_block_unused = 0x40000818; -ets_efuse_find_unused_key_block = 0x4000081c; -ets_efuse_rs_calculate = 0x40000820; -ets_efuse_count_unused_key_blocks = 0x40000824; -ets_efuse_secure_boot_enabled = 0x40000828; -ets_efuse_secure_boot_aggressive_revoke_enabled = 0x4000082c; -ets_efuse_cache_encryption_enabled = 0x40000830; -ets_efuse_download_modes_disabled = 0x40000834; -ets_efuse_find_purpose = 0x40000838; -ets_efuse_force_send_resume = 0x4000083c; -ets_efuse_get_flash_delay_us = 0x40000840; -ets_efuse_get_mac = 0x40000844; -ets_efuse_get_uart_print_control = 0x40000848; -ets_efuse_direct_boot_mode_disabled = 0x4000084c; -ets_efuse_security_download_modes_enabled = 0x40000850; -ets_efuse_set_timing = 0x40000854; -ets_efuse_jtag_disabled = 0x40000858; -ets_efuse_usb_print_is_disabled = 0x4000085c; -ets_efuse_usb_download_mode_disabled = 0x40000860; -ets_efuse_usb_device_disabled = 0x40000864; -ets_efuse_secure_boot_fast_wake_enabled = 0x40000868; - - -/*************************************** - Group secureboot - ***************************************/ - -/* Functions */ -ets_emsa_pss_verify = 0x4000086c; -ets_rsa_pss_verify = 0x40000870; -ets_secure_boot_verify_bootloader_with_keys = 0x40000874; -ets_secure_boot_verify_signature = 0x40000878; -ets_secure_boot_read_key_digests = 0x4000087c; -ets_secure_boot_revoke_public_key_digest = 0x40000880; - - -/*************************************** - Group usb_device_uart - ***************************************/ - -/* Functions */ -usb_serial_device_rx_one_char = 0x40000a80; -usb_serial_device_rx_one_char_block = 0x40000a84; -usb_serial_device_tx_flush = 0x40000a88; -usb_serial_device_tx_one_char = 0x40000a8c; - - -/*************************************** - Group lldesc - ***************************************/ - -/* Functions */ -lldesc_build_chain = 0x40000a90; - - -/*************************************** - Group sip - ***************************************/ - -/* Functions */ -sip_after_tx_complete = 0x40000a94; -sip_alloc_to_host_evt = 0x40000a98; -sip_download_begin = 0x40000a9c; -sip_get_ptr = 0x40000aa0; -sip_get_state = 0x40000aa4; -sip_init_attach = 0x40000aa8; -sip_install_rx_ctrl_cb = 0x40000aac; -sip_install_rx_data_cb = 0x40000ab0; -sip_is_active = 0x40000ab4; -sip_post_init = 0x40000ab8; -sip_reclaim_from_host_cmd = 0x40000abc; -sip_reclaim_tx_data_pkt = 0x40000ac0; -sip_send = 0x40000ac4; -sip_to_host_chain_append = 0x40000ac8; -sip_to_host_evt_send_done = 0x40000acc; - - -/*************************************** - Group slc - ***************************************/ - -/* Functions */ -slc_add_credits = 0x40000ad0; -slc_enable = 0x40000ad4; -slc_from_host_chain_fetch = 0x40000ad8; -slc_from_host_chain_recycle = 0x40000adc; -slc_has_pkt_to_host = 0x40000ae0; -slc_init_attach = 0x40000ae4; -slc_init_credit = 0x40000ae8; -slc_reattach = 0x40000aec; -slc_send_to_host_chain = 0x40000af0; -slc_set_host_io_max_window = 0x40000af4; -slc_to_host_chain_recycle = 0x40000af8; - -/*************************************** - Group memory and string - ***************************************/ - -memset = 0x400004a8; -memcpy = 0x400004ac; -memmove = 0x400004b0; -memcmp = 0x400004b4; -memccpy = 0x40000518; -memchr = 0x4000051c; -memrchr = 0x40000520; -strcpy = 0x400004b8; -strncpy = 0x400004bc; -strcmp = 0x400004c0; -strncmp = 0x400004c4; -strlen = 0x400004c8; -strstr = 0x400004cc; -strchr = 0x40000534; -strlcpy = 0x40000544; -strnlen = 0x40000558; -bzero = 0x400004d0; \ No newline at end of file diff --git a/boards/risc-v/esp32c6/common/scripts/esp32c6_simple_boot_sections.ld b/boards/risc-v/esp32c6/common/scripts/esp32c6_simple_boot_sections.ld new file mode 100644 index 0000000000000..4b6f5aa1c82c3 --- /dev/null +++ b/boards/risc-v/esp32c6/common/scripts/esp32c6_simple_boot_sections.ld @@ -0,0 +1,445 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/common/scripts/esp32c6_simple_boot_sections.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Default entry point: */ + +ENTRY(__start); + +SECTIONS +{ + .iram0.text : + { + _iram_start = ABSOLUTE(.); + + /* Vectors go to start of IRAM */ + + KEEP(*(.exception_vectors.text)); + . = ALIGN(4); + + *(.iram1) + *(.iram1.*) + *libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*) + + *libarch.a:*brownout.*(.text .text.* .literal .literal.*) + *libarch.a:*cpu.*(.text .text.* .literal .literal.*) + *libarch.a:*gpio_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*periph_ctrl.*(.text .text.* .literal .literal.*) + *libarch.a:*clk.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk_tree.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk_tree_common.*(.text .text.* .literal .literal.*) + *libarch.a:*clk_tree_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*pmu_init.*(.text .text.* .literal .literal.*) + *libarch.a:*modem_clock.*(.text .text.* .literal .literal.*) + *libarch.a:*regi2c_ctrl.*(.text .text.* .literal .literal.*) + *libarch.a:*gpio_periph.*(.text .text.* .literal .literal.*) + *libarch.a:*modem_clock_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_systimer.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_wdt.*(.text .text.* .literal .literal.*) + *libarch.a:*ocode_init.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_regi2c_esp32c6.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_clk.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_clk_init.*(.text .text.* .literal .literal.*) + *libarch.a:*pmu_sleep.*(.text .text.* .literal .literal.*) + *libarch.a:*pmu_param.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_time.*(.text .text.* .literal .literal.*) + *libarch.a:*systimer.*(.text .text.* .literal .literal.*) + *libarch.a:*systimer_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_hal_iram.*(.text .text.* .literal .literal.*) + *libarch.a:*wdt_hal_iram.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_banner_wrap.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_init.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_common.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_common_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_console.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_console_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_esp32c6.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_flash.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_flash_config_esp32c6.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_clock_init.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_clock_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_efuse.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_panic.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_mem.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_random.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_random_esp32c6.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_image_format.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_soc.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_sha.*(.text .text.* .literal .literal.*) + *libarch.a:*flash_encrypt.*(.text .text.* .literal .literal.*) + *libarch.a:*cache_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_periph.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_uart.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_sys.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_spiflash.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_efuse_fields.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_efuse_api_key.*(.text .text.* .literal .literal.*) + *libarch.a:*efuse_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*log.*(.text .text.* .literal .literal.*) + *libarch.a:*log_noos.*(.text .text.* .literal .literal.*) + *libarch.a:esp_spiflash.*(.literal .text .literal.* .text.*) + + esp_head.*(.literal .text .literal.* .text.*) + esp_start.*(.literal .text .literal.* .text.*) + + *(.wifi0iram.*) + *(.wifirxiram.*) + *(.wifislpiram.*) + *(.wifiorslpiram.*) + *(.wifislprxiram.*) + } >iram0_0_seg AT > ROM + + /* Marks the end of IRAM code segment */ + + .iram0.text_end (NOLOAD) : + { + . = ALIGN (16); + } >iram0_0_seg + + .iram0.data : + { + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + } >iram0_0_seg + + .iram0.bss (NOLOAD) : + { + . = ALIGN(16); + *(.iram.bss) + *(.iram.bss*) + + . = ALIGN(16); + _iram_end = ABSOLUTE(.); + } >iram0_0_seg + + /* This section is required to skip .iram0.text area because iram0_0_seg + * and dram0_0_seg reflect the same address space on different buses. + */ + + .dram0.dummy (NOLOAD): + { + . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; + } >dram0_0_seg + + .noinit (NOLOAD): + { + /* This section contains data that is not initialized during load, + * or during the application's initialization sequence. + */ + + *(.noinit) + *(.noinit.*) + } >dram0_0_seg + + .dram0.data : + { + . = ALIGN (16); + _data_start = ABSOLUTE(.); + _sdata = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + __global_pointer$ = . + 0x800; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + *(.dram1) + *(.dram1.*) + *libsched.a:irq_dispatch.*(.rodata .rodata.*) + + *libarch.a:*brownout.*(.rodata .rodata.*) + *libarch.a:*cpu.*(.rodata .rodata.*) + *libarch.a:*gpio_hal.*(.rodata .rodata.*) + *libarch.a:*periph_ctrl.*(.rodata .rodata.*) + *libarch.a:*clk.*(.rodata .rodata.*) + *libarch.a:*esp_clk.*(.rodata .rodata.*) + *libarch.a:*esp_clk_tree.*(.rodata .rodata.*) + *libarch.a:*esp_clk_tree_common.*(.rodata .rodata.*) + *libarch.a:*clk_tree_hal.*(.rodata .rodata.*) + *libarch.a:*pmu_init.*(.rodata .rodata.*) + *libarch.a:*modem_clock.*(.rodata .rodata.*) + *libarch.a:*regi2c_ctrl.*(.rodata .rodata.*) + *libarch.a:*gpio_periph.*(.rodata .rodata.*) + *libarch.a:*modem_clock_hal.*(.rodata .rodata.*) + *libarch.a:*esp_rom_systimer.*(.rodata .rodata.*) + *libarch.a:*esp_rom_wdt.*(.rodata .rodata.*) + *libarch.a:*ocode_init.*(.rodata .rodata.*) + *libarch.a:*esp_rom_regi2c_esp32c6.*(.rodata .rodata.*) + *libarch.a:*rtc_clk.*(.rodata .rodata.*) + *libarch.a:*rtc_clk_init.*(.rodata .rodata.*) + *libarch.a:*pmu_param.*(.rodata .rodata.*) + *libarch.a:*pmu_sleep.*(.rodata .rodata.*) + *libarch.a:*rtc_time.*(.rodata .rodata.*) + *libarch.a:*systimer.*(.rodata .rodata.*) + *libarch.a:*systimer_hal.*(.rodata .rodata.*) + *libarch.a:*uart_hal_iram.*(.rodata .rodata.*) + *libarch.a:*wdt_hal_iram.*(.rodata .rodata.*) + *libarch.a:*bootloader_banner_wrap.*(.rodata .rodata.*) + *libarch.a:*bootloader_init.*(.rodata .rodata.*) + *libarch.a:*bootloader_common.*(.rodata .rodata.*) + *libarch.a:*bootloader_common_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_console.*(.rodata .rodata.*) + *libarch.a:*bootloader_console_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_esp32c6.*(.rodata .rodata.*) + *libarch.a:*bootloader_flash.*(.rodata .rodata.*) + *libarch.a:*bootloader_flash_config_esp32c6.*(.rodata .rodata.*) + *libarch.a:*bootloader_clock_init.*(.rodata .rodata.*) + *libarch.a:*bootloader_clock_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_efuse.*(.rodata .rodata.*) + *libarch.a:*bootloader_panic.*(.rodata .rodata.*) + *libarch.a:*bootloader_mem.*(.rodata .rodata.*) + *libarch.a:*bootloader_random.*(.rodata .rodata.*) + *libarch.a:*bootloader_random_esp32c6.*(.rodata .rodata.*) + *libarch.a:*esp_image_format.*(.rodata .rodata.*) + *libarch.a:*bootloader_soc.*(.rodata .rodata.*) + *libarch.a:*bootloader_sha.*(.rodata .rodata.*) + *libarch.a:*flash_encrypt.*(.rodata .rodata.*) + *libarch.a:*cache_hal.*(.rodata .rodata.*) + *libarch.a:*uart_hal.*(.rodata .rodata.*) + *libarch.a:*mpu_hal.*(.rodata .rodata.*) + *libarch.a:*mmu_hal.*(.rodata .rodata.*) + *libarch.a:*uart_periph.*(.rodata .rodata.*) + *libarch.a:*esp_rom_uart.*(.rodata .rodata.*) + *libarch.a:*esp_rom_sys.*(.rodata .rodata.*) + *libarch.a:*esp_rom_spiflash.*(.rodata .rodata.*) + *libarch.a:*esp_efuse_fields.*(.rodata .rodata.*) + *libarch.a:*esp_efuse_api_key.*(.rodata .rodata.*) + *libarch.a:*efuse_hal.*(.rodata .rodata.*) + *libarch.a:*log.*(.rodata .rodata.*) + *libarch.a:*log_noos.*(.rodata .rodata.*) + *libarch.a:esp_spiflash.*(.rodata .rodata.*) + + esp_head.*(.rodata .rodata.*) + esp_start.*(.rodata .rodata.*) + + . = ALIGN(4); + _edata = ABSOLUTE(.); + _data_end = ABSOLUTE(.); + } >dram0_0_seg AT > ROM + + /* Shared RAM */ + + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + + . = ALIGN (32); + _ebss = ABSOLUTE(.); + _bss_end = ABSOLUTE(.); + } >dram0_0_seg + + _image_irom_vma = ADDR(.flash.text); + _image_irom_lma = LOADADDR(.flash.text); + _image_irom_size = SIZEOF(.flash.text); + + .flash.text_dummy (NOLOAD) : + { + . = ALIGN(0x10000); + } > ROM + + .flash.text : + { + _stext = .; + _instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */ + _text_start = ABSOLUTE(.); + + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + + _text_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); /* This is a symbol marking the flash.text end, this can be used for mmu driver to maintain virtual address */ + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + + _flash_cache_start = ABSOLUTE(0); + } >default_code_seg AT > ROM + + .flash_rodata_dummy (NOLOAD) : + { + . += SIZEOF(.flash.text); + . = ALIGN(0x10000); + } >default_rodata_seg AT > ROM + + _image_drom_vma = ADDR(.flash.rodata); + _image_drom_lma = LOADADDR(.flash.rodata); + _image_drom_size = SIZEOF(.flash.rodata); + + .flash.appdesc : ALIGN(0x10) + { + _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ + _rodata_start = ABSOLUTE(.); + + /* Create an empty gap within this section. Thanks to this, the end of this + * section will match .flash.rodata's begin address. Thus, both sections + * will be merged when creating the final bin image. */ + . = ALIGN(ALIGNOF(.flash.rodata)); + } >default_rodata_seg + + .flash.rodata : + { + _srodata = ABSOLUTE(.); + + *(.rodata) + *(.rodata.*) + *(.rodata_wlog_verbose.*) + *(.rodata_wlog_debug.*) + *(.rodata_wlog_info.*) + *(.rodata_wlog_warning.*) + *(.rodata_wlog_error.*) + + *(.srodata.*) + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ constructor and destructor tables: + * RISC-V GCC is configured with --enable-initfini-array so it emits an + * .init_array section instead. + */ + + _sinit = ABSOLUTE(.); + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)) + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array)) + _einit = ABSOLUTE(.); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + + /* C++ exception handlers table: */ + + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _erodata = ABSOLUTE(.); + + /* Literals are also RO data. */ + + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + } >default_rodata_seg AT > ROM + + .flash.rodata_noload (NOLOAD) : + { + /* + This is a symbol marking the flash.rodata end, this can be used for mmu driver to maintain virtual address + We don't need to include the noload rodata in this section + */ + _rodata_reserved_end = ABSOLUTE(.); + . = ALIGN (4); + } > default_rodata_seg AT > ROM + + /* RTC fast memory holds RTC wake stub code !*/ + + .rtc.text : + { + . = ALIGN(4); + *(.rtc.literal .rtc.text) + } >rtc_iram_seg + + /* RTC BSS section. */ + + .rtc.bss (NOLOAD) : + { + *(.rtc.bss) + } >rtc_iram_seg + + /* RTC data section holds RTC wake stub data/rodata. */ + + .rtc.data : + { + *(.rtc.data) + *(.rtc.data.*) + *(.rtc.rodata) + *(.rtc.rodata.*) + } >rtc_iram_seg + + /* This section holds RTC data that should have fixed addresses. + * The data are not initialized at power-up and are retained during deep sleep. + */ + .rtc_reserved (NOLOAD): + { + . = ALIGN(4); + _rtc_reserved_start = ABSOLUTE(.); + /* New data can only be added here to ensure existing data are not moved. + Because data have adhered to the end of the segment and code is relied on it. + >> put new data here << */ + + *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) + KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*)) + _rtc_reserved_end = ABSOLUTE(.); + } > rtc_reserved_seg + + _rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start; + ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)), + "RTC reserved segment data does not fit.") + +} + diff --git a/boards/risc-v/esp32c6/common/scripts/flat_memory.ld b/boards/risc-v/esp32c6/common/scripts/flat_memory.ld deleted file mode 100644 index 30d4d139b11a7..0000000000000 --- a/boards/risc-v/esp32c6/common/scripts/flat_memory.ld +++ /dev/null @@ -1,104 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c6/common/scripts/flat_memory.ld - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * This file describes the memory layout (memory blocks) as virtual - * memory addresses. - * - * legacy_sections.ld contains output sections to link compiler - * output into these memory blocks. - * - ****************************************************************************/ - -#include - -#define SRAM_IRAM_START 0x40800000 -#define SRAM_DRAM_START 0x40800000 - -#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) - -/* 2nd stage bootloader iram_loader_seg start address */ - -#define SRAM_DRAM_END (0x4086e610 - I_D_SRAM_OFFSET) - -#define SRAM_IRAM_ORG (SRAM_IRAM_START) -#define SRAM_DRAM_ORG (SRAM_DRAM_START) - -#define I_D_SRAM_SIZE (SRAM_DRAM_END - SRAM_DRAM_ORG) - -/* IDRAM0_2_SEG_SIZE_DEFAULT is used when page size is 64KB */ - -#define CONFIG_MMU_PAGE_SIZE 0x10000 -#define IDRAM0_2_SEG_SIZE (CONFIG_MMU_PAGE_SIZE << 8) - -#define DRAM0_0_SEG_LEN I_D_SRAM_SIZE - -MEMORY -{ - /* All these values assume the flash cache is on, and have the blocks it - * uses subtracted from the length of the various regions. The 'data access - * port' dram/drom regions map to the same iram/irom regions but are - * connected to the data port of the CPU and eg allow byte-wise access. - */ - - iram0_0_seg (RX) : org = SRAM_IRAM_ORG, len = I_D_SRAM_SIZE - - /* Flash mapped instruction data. - * - * The 0x20 offset is a convenience for the app binary image generation. - * Flash cache has 64KB pages. The .bin file which is flashed to the chip - * has a 0x18 byte file header, and each segment has a 0x08 byte segment - * header. Setting this offset makes it simple to meet the flash cache MMU's - * constraint that (paddr % 64KB == vaddr % 64KB). - */ - - irom0_0_seg (RX) : org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20 - - /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. - * Enabling Bluetooth & Trace Memory features in menuconfig will decrease - * the amount of RAM available. - */ - - dram0_0_seg (RW) : org = SRAM_DRAM_ORG, len = DRAM0_0_SEG_LEN - - /* Flash mapped constant data */ - - drom0_0_seg (R) : org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20 - - /* RTC fast memory (executable). Persists over deep sleep. */ - - rtc_iram_seg(RWX) : org = 0x50000000, len = 0x4000 - -} - -/* Heap ends at the start of the static data of the ROM bootloader */ - -_eheap = 0x4086ad08; - -#if CONFIG_ESP32C6_DEVKIT_RUN_IRAM - REGION_ALIAS("default_rodata_seg", dram0_0_seg); - REGION_ALIAS("default_code_seg", iram0_0_seg); -#else - REGION_ALIAS("default_rodata_seg", drom0_0_seg); - REGION_ALIAS("default_code_seg", irom0_0_seg); -#endif /* CONFIG_ESP32C6_DEVKIT_RUN_IRAM */ - REGION_ALIAS("rtc_data_seg", rtc_iram_seg ); - REGION_ALIAS("rtc_slow_seg", rtc_iram_seg ); - REGION_ALIAS("rtc_data_location", rtc_iram_seg ); diff --git a/boards/risc-v/esp32c6/common/scripts/legacy_sections.ld b/boards/risc-v/esp32c6/common/scripts/legacy_sections.ld deleted file mode 100644 index eadef0438c438..0000000000000 --- a/boards/risc-v/esp32c6/common/scripts/legacy_sections.ld +++ /dev/null @@ -1,233 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c6/common/scripts/legacy_sections.ld - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/* Default entry point: */ - -ENTRY(__start); - -SECTIONS -{ - .iram0.text : - { - _iram_start = ABSOLUTE(.); - - /* Vectors go to start of IRAM */ - - KEEP(*(.exception_vectors.text)); - . = ALIGN(4); - - *(.iram1) - *(.iram1.*) - - } >iram0_0_seg - - /* Marks the end of IRAM code segment */ - - .iram0.text_end (NOLOAD) : - { - . = ALIGN (16); - } >iram0_0_seg - - .iram0.data : - { - . = ALIGN(16); - *(.iram.data) - *(.iram.data*) - } >iram0_0_seg - - .iram0.bss (NOLOAD) : - { - . = ALIGN(16); - *(.iram.bss) - *(.iram.bss*) - - . = ALIGN(16); - _iram_end = ABSOLUTE(.); - } >iram0_0_seg - - /* This section is required to skip .iram0.text area because iram0_0_seg - * and dram0_0_seg reflect the same address space on different buses. - */ - - .dram0.dummy (NOLOAD): - { - . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; - } >dram0_0_seg - - /* Shared RAM */ - - .dram0.bss (NOLOAD) : - { - . = ALIGN (8); - _sbss = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.share.mem) - *(.gnu.linkonce.b.*) - *(COMMON) - - . = ALIGN (8); - _ebss = ABSOLUTE(.); - - /* Uninitialized .bss */ - - *(.noinit) - *(.noinit.*) - - } >dram0_0_seg - - .dram0.data : - { - _sdata = ABSOLUTE(.); - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - *(.data1) - __global_pointer$ = . + 0x800; - *(.sdata) - *(.sdata.*) - *(.gnu.linkonce.s.*) - *(.sdata2) - *(.sdata2.*) - *(.gnu.linkonce.s2.*) - *(.jcr) - *(.dram1) - *(.dram1.*) - . = ALIGN(4); - _edata = ABSOLUTE(.); - - /* Heap starts at the end of .data */ - - _sheap = ABSOLUTE(.); - } >dram0_0_seg - - .flash.text : - { - _stext = .; - - *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) - *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.fini.literal) - *(.fini) - *(.gnu.version) - _etext = .; - - /* Similar to _iram_start, this symbol goes here so it is - * resolved by addr2line in preference to the first symbol in - * the flash.text segment. - */ - - _flash_cache_start = ABSOLUTE(0); - } >default_code_seg - - .flash_rodata_dummy (NOLOAD): - { - . = SIZEOF(.flash.text); - . = ALIGN(0x10000) + 0x20; - } >drom0_0_seg - - .flash.rodata : ALIGN(0x10) - { - _srodata = ABSOLUTE(.); - - *(.rodata) - *(.rodata.*) - *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ - *(.gnu.linkonce.r.*) - *(.rodata1) - *(.srodata.*) - __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); - *(.xt_except_table) - *(.gcc_except_table .gcc_except_table.*) - *(.gnu.linkonce.e.*) - *(.gnu.version_r) - . = (. + 3) & ~ 3; - __eh_frame = ABSOLUTE(.); - KEEP(*(.eh_frame)) - . = (. + 7) & ~ 3; - - /* C++ constructor and destructor tables: */ - - _sinit = ABSOLUTE(.); - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*(.ctors)) - _einit = ABSOLUTE(.); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*(.dtors)) - - /* C++ exception handlers table: */ - - __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); - *(.xt_except_desc) - *(.gnu.linkonce.h.*) - __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); - *(.xt_except_desc_end) - *(.dynamic) - *(.gnu.version_d) - _erodata = ABSOLUTE(.); - - /* Literals are also RO data. */ - - _lit4_start = ABSOLUTE(.); - *(*.lit4) - *(.lit4.*) - *(.gnu.linkonce.lit4.*) - _lit4_end = ABSOLUTE(.); - . = ALIGN(4); - } >default_rodata_seg - - /* RTC fast memory holds RTC wake stub code !*/ - - .rtc.text : - { - . = ALIGN(4); - *(.rtc.literal .rtc.text) - } >rtc_iram_seg - - /* This section is required to skip rtc.text area because the text and - * data segements reflect the same address space on different buses. - */ - - .rtc.dummy : - { - . = SIZEOF(.rtc.text); - } >rtc_iram_seg - - /* RTC data section holds RTC wake stub data/rodata. */ - - .rtc.data : - { - *(.rtc.data) - *(.rtc.rodata) - } >rtc_iram_seg -} diff --git a/boards/risc-v/esp32c6/common/src/Make.defs b/boards/risc-v/esp32c6/common/src/Make.defs new file mode 100644 index 0000000000000..36a1c1ce041c2 --- /dev/null +++ b/boards/risc-v/esp32c6/common/src/Make.defs @@ -0,0 +1,47 @@ +############################################################################# +# boards/risc-v/esp32c6/common/src/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +ifeq ($(CONFIG_ARCH_BOARD_COMMON),y) + +ifeq ($(CONFIG_ESPRESSIF_LEDC),y) + CSRCS += esp_board_ledc.c +endif + +ifeq ($(CONFIG_ESP_RMT),y) + CSRCS += esp_board_rmt.c +endif + +ifeq ($(CONFIG_ESPRESSIF_SPIFLASH),y) + CSRCS += esp_board_spiflash.c +endif + +ifeq ($(CONFIG_ESPRESSIF_TWAI),y) + CSRCS += esp_board_twai.c +endif + +ifeq ($(CONFIG_ESPRESSIF_WIFI),y) + CSRCS += esp_board_wlan.c +endif + +DEPPATH += --dep-path src +VPATH += :src +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src + +endif diff --git a/boards/risc-v/esp32c6/common/src/esp_board_ledc.c b/boards/risc-v/esp32c6/common/src/esp_board_ledc.c new file mode 100644 index 0000000000000..4ec63eb80bb83 --- /dev/null +++ b/boards/risc-v/esp32c6/common/src/esp_board_ledc.c @@ -0,0 +1,147 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/common/src/esp_board_ledc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include + +#include "espressif/esp_ledc.h" + +#include "esp_board_ledc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LEDC_TIMER0 0 +#define LEDC_TIMER1 1 +#define LEDC_TIMER2 2 +#define LEDC_TIMER3 3 + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ledc_setup + * + * Description: + * Initialize LEDC PWM and register the PWM device. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int board_ledc_setup(void) +{ + int ret = OK; + struct pwm_lowerhalf_s *pwm; + +#ifdef CONFIG_ESPRESSIF_LEDC_TIMER0 + pwm = esp_ledc_init(LEDC_TIMER0); + if (!pwm) + { + syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 0 lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ESPRESSIF_LEDC_TIMER1 + pwm = esp_ledc_init(LEDC_TIMER1); + if (!pwm) + { + syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 1 lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm1" */ + + ret = pwm_register("/dev/pwm1", pwm); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ESPRESSIF_LEDC_TIMER2 + pwm = esp_ledc_init(LEDC_TIMER2); + if (!pwm) + { + syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 2 lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm2" */ + + ret = pwm_register("/dev/pwm2", pwm); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ESPRESSIF_LEDC_TIMER3 + pwm = esp_ledc_init(LEDC_TIMER3); + if (!pwm) + { + syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 3 lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm3" */ + + ret = pwm_register("/dev/pwm3", pwm); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + + return ret; +} + diff --git a/boards/risc-v/esp32c6/common/src/esp_board_rmt.c b/boards/risc-v/esp32c6/common/src/esp_board_rmt.c new file mode 100644 index 0000000000000..9c3eefd321e20 --- /dev/null +++ b/boards/risc-v/esp32c6/common/src/esp_board_rmt.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/common/src/esp_board_rmt.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#ifdef CONFIG_WS2812_NON_SPI_DRIVER +#include + +#include "espressif/esp_ws2812.h" +#endif + +#include "espressif/esp_rmt.h" + +#ifdef CONFIG_ESP_RMT + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_rmt_rxinitialize + * + * Description: + * Initialize the RMT peripheral and register an RX device. + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the RX channel + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_rmt_rxinitialize(int ch, int pin) +{ + int ret; + + struct rmt_dev_s *rmt = esp_rmt_rx_init(ch, pin); + + ret = rmtchar_register(rmt); + if (ret < 0) + { + rmterr("ERROR: rmtchar_register failed: %d\n", ret); + return ret; + } + + return ret; +} + +/**************************************************************************** + * Name: board_rmt_txinitialize + * + * Description: + * Initialize the RMT peripheral and register an TX device. + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the TX channel + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_rmt_txinitialize(int ch, int pin) +{ + int ret; + struct rmt_dev_s *rmt; +#ifdef CONFIG_WS2812_NON_SPI_DRIVER + struct ws2812_dev_s *led; +#endif + + rmt = esp_rmt_tx_init(ch, pin); + if (rmt == NULL) + { + rmterr("ERROR: esp_rmt_tx_init failed\n"); + return -ENODEV; + } + + ret = rmtchar_register(rmt); + if (ret < 0) + { + rmterr("ERROR: rmtchar_register failed: %d\n", ret); + return ret; + } + +#ifdef CONFIG_WS2812_NON_SPI_DRIVER + led = esp_ws2812_setup("/dev/leds0", rmt, CONFIG_WS2812_LED_COUNT, false); + if (led == NULL) + { + rmterr("ERROR: esp_ws2812_setup failed\n"); + return -ENODEV; + } +#endif + + return ret; +} +#endif diff --git a/boards/risc-v/esp32c6/common/src/esp_board_spiflash.c b/boards/risc-v/esp32c6/common/src/esp_board_spiflash.c new file mode 100644 index 0000000000000..716d74fba579d --- /dev/null +++ b/boards/risc-v/esp32c6/common/src/esp_board_spiflash.c @@ -0,0 +1,417 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/common/src/esp_board_spiflash.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "inttypes.h" +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#ifdef CONFIG_BCH +#include +#endif + +#include "espressif/esp_spiflash.h" +#include "espressif/esp_spiflash_mtd.h" + +#include "esp_board_spiflash.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: setup_smartfs + * + * Description: + * Provide a block driver wrapper around MTD partition and mount a + * SMART FS over it. + * + * Parameters: + * smartn - Number used to register the mtd partition: /dev/smartx, where + * x = smartn. + * mtd - Pointer to a pre-allocated mtd partition. + * mnt_pt - Mount point + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +#if defined (CONFIG_ESPRESSIF_SPIFLASH_SMARTFS) +static int setup_smartfs(int smartn, struct mtd_dev_s *mtd, + const char *mnt_pt) +{ + int ret = OK; + char path[22]; + + ret = smart_initialize(smartn, mtd, NULL); + if (ret < 0) + { + syslog(LOG_INFO, "smart_initialize failed, " + "Trying to erase first...\n"); + ret = mtd->ioctl(mtd, MTDIOC_BULKERASE, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: ioctl(BULKERASE) failed: %d\n", ret); + return ret; + } + + syslog(LOG_INFO, "Erase successful, initializing it again.\n"); + ret = smart_initialize(smartn, mtd, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: smart_initialize failed: %d\n", ret); + return ret; + } + } + + if (mnt_pt != NULL) + { + snprintf(path, sizeof(path), "/dev/smart%d", smartn); + + ret = nx_mount(path, mnt_pt, "smartfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the FS volume: %d\n", ret); + if (ret == -ENODEV) + { + syslog(LOG_WARNING, "Smartfs seems unformatted. " + "Did you run 'mksmartfs /dev/smart%d'?\n", smartn); + } + + return ret; + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: setup_littlefs + * + * Description: + * Register a mtd driver and mount a Little FS over it. + * + * Parameters: + * path - Path name used to register the mtd driver. + * mtd - Pointer to a pre-allocated mtd partition. + * mnt_pt - Mount point + * priv - Privileges + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +#if defined (CONFIG_ESPRESSIF_SPIFLASH_LITTLEFS) +static int setup_littlefs(const char *path, struct mtd_dev_s *mtd, + const char *mnt_pt, int priv) +{ + int ret = OK; + + ret = register_mtddriver(path, mtd, priv, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); + return ERROR; + } + + if (mnt_pt != NULL) + { + ret = nx_mount(path, mnt_pt, "littlefs", 0, NULL); + if (ret < 0) + { + ret = nx_mount(path, mnt_pt, "littlefs", 0, "forceformat"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the FS volume: %d\n", + ret); + return ret; + } + } + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: setup_spiffs + * + * Description: + * Register a mtd driver and mount a SPIFFS over it. + * + * Parameters: + * path - Path name used to register the mtd driver. + * mtd - Pointer to a pre-allocated mtd partition. + * mnt_pt - Mount point + * priv - Privileges + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +#if defined (CONFIG_ESPRESSIF_SPIFLASH_SPIFFS) +static int setup_spiffs(const char *path, struct mtd_dev_s *mtd, + const char *mnt_pt, int priv) +{ + int ret = OK; + + ret = register_mtddriver(path, mtd, priv, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); + return ERROR; + } + + if (mnt_pt != NULL) + { + ret = nx_mount(path, mnt_pt, "spiffs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the FS volume: %d\n", ret); + return ret; + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: setup_nxffs + * + * Description: + * Register a mtd driver and mount a NXFFS over it. + * + * Parameters: + * mtd - Pointer to a pre-allocated mtd partition. + * mnt_pt - Mount point + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +#if defined (CONFIG_ESPRESSIF_SPIFLASH_NXFFS) +static int setup_nxffs(struct mtd_dev_s *mtd, const char *mnt_pt) +{ + int ret = OK; + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: NXFFS init failed: %d\n", ret); + return ret; + } + + if (mnt_pt != NULL) + { + ret = nx_mount(NULL, mnt_pt, "nxffs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the FS volume: %d\n", ret); + return ret; + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: init_storage_partition + * + * Description: + * Initialize partition that is dedicated to general use. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int init_storage_partition(void) +{ + int ret = OK; + struct mtd_dev_s *mtd; + + mtd = esp_spiflash_alloc_mtdpart(CONFIG_ESPRESSIF_STORAGE_MTD_OFFSET, + CONFIG_ESPRESSIF_STORAGE_MTD_SIZE); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: Failed to alloc MTD partition of SPI Flash\n"); + return ERROR; + } + +#if defined (CONFIG_ESPRESSIF_SPIFLASH_SMARTFS) + + ret = setup_smartfs(0, mtd, "/data"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to setup smartfs\n"); + return ret; + } + +#elif defined (CONFIG_ESPRESSIF_SPIFLASH_NXFFS) + + ret = setup_nxffs(mtd, "/data"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to setup nxffs\n"); + return ret; + } + +#elif defined (CONFIG_ESPRESSIF_SPIFLASH_LITTLEFS) + + const char *path = "/dev/espflash"; + ret = setup_littlefs(path, mtd, "/data", 0755); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to setup littlefs\n"); + return ret; + } + +#elif defined (CONFIG_ESPRESSIF_SPIFLASH_SPIFFS) + + const char *path = "/dev/espflash"; + ret = setup_spiffs(path, mtd, "/data", 0755); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to setup spiffs\n"); + return ret; + } + +#elif defined (CONFIG_ESPRESSIF_SPIFLASH_MTD_CONFIG) + +# if defined (CONFIG_TESTING_MTD_CONFIG_FAIL_SAFE) + + /* To test power-loss resilient kv system, + * we write possible power-loss flash layout into flash + * then start kv system to see if it recovers. + * To do so, we need a mtd driver so that test code can + * write into flash. + */ + + const char *path = CONFIG_TESTING_MTD_CONFIG_FAIL_SAFE_MOUNTPT_NAME; + ret = register_mtddriver(path, mtd, 0777, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); + return ret; + } + +# else + + ret = mtdconfig_register(mtd); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to setup mtd config\n"); + return ret; + } + +# endif + +#else + + ret = register_mtddriver("/dev/espflash", mtd, 0755, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); + return ret; + } + +#endif + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_spiflash_init + * + * Description: + * Initialize the SPI Flash and register the MTD device. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int board_spiflash_init(void) +{ + int ret = OK; + + esp_spiflash_init(); + + ret = init_storage_partition(); + if (ret < 0) + { + return ret; + } + + return ret; +} + diff --git a/boards/risc-v/esp32c6/common/src/esp_board_twai.c b/boards/risc-v/esp32c6/common/src/esp_board_twai.c new file mode 100644 index 0000000000000..499e4e7c48e27 --- /dev/null +++ b/boards/risc-v/esp32c6/common/src/esp_board_twai.c @@ -0,0 +1,105 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/common/src/esp_board_twai.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "espressif/esp_twai.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_twai_setup + * + * Description: + * Initialize TWAI and register the TWAI device + * + * Input Parameters: + * port - Port number (for hardware that has multiple TWAI interfaces) + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int board_twai_setup(int port) +{ +#ifdef CONFIG_ESPRESSIF_TWAI + struct can_dev_s *twai; + int ret; + + /* Call esp_twaiinitialize() to get an instance of the TWAI + * interface + * */ + + twai = esp_twaiinitialize(port); + if (twai == NULL) + { + canerr("ERROR: Failed to get TWAI interface\n"); + return -ENODEV; + } + +#ifdef CONFIG_ESPRESSIF_TWAI0 + /* Register the TWAI driver at "/dev/can0" */ + + ret = can_register("/dev/can0", twai); + if (ret < 0) + { + canerr("ERROR: TWAI0 register failed: %d\n", ret); + return ret; + } +#endif /* CONFIG_ESPRESSIF_TWAI0 */ + +#ifdef CONFIG_ESPRESSIF_TWAI1 + /* Register the TWAI driver at "/dev/can1" */ + + ret = can_register("/dev/can1", twai); + if (ret < 0) + { + canerr("ERROR: TWAI1 register failed: %d\n", ret); + return ret; + } +#endif /* CONFIG_ESPRESSIF_TWAI1 */ + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/risc-v/esp32c6/common/src/esp_board_wlan.c b/boards/risc-v/esp32c6/common/src/esp_board_wlan.c new file mode 100644 index 0000000000000..0ae40b1387165 --- /dev/null +++ b/boards/risc-v/esp32c6/common/src/esp_board_wlan.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/common/src/esp_board_wlan.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "espressif/esp_wlan.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_wlan_init + * + * Description: + * Configure the wireless subsystem. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int board_wlan_init(void) +{ + int ret = OK; + +#ifdef ESP_WLAN_HAS_STA + ret = esp_wlan_sta_initialize(); + if (ret) + { + wlerr("ERROR: Failed to initialize Wi-Fi station\n"); + return ret; + } +#endif /* ESP_WLAN_HAS_STA */ + +#ifdef ESP_WLAN_HAS_SOFTAP + ret = esp_wlan_softap_initialize(); + if (ret) + { + wlerr("ERROR: Failed to initialize Wi-Fi softAP\n"); + return ret; + } +#endif /* ESP_WLAN_HAS_SOFTAP */ + + return ret; +} + diff --git a/boards/risc-v/esp32c6/esp32c6-devkit/Kconfig b/boards/risc-v/esp32c6/esp32c6-devkit/Kconfig deleted file mode 100644 index 2e5312bb53982..0000000000000 --- a/boards/risc-v/esp32c6/esp32c6-devkit/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -if ARCH_BOARD_ESP32C6_DEVKIT - -config ESP32C6_DEVKIT_RUN_IRAM - bool "Run from IRAM" - default n - -endif # ARCH_BOARD_ESP32C6_DEVKIT diff --git a/boards/risc-v/esp32c6/esp32c6-devkit/configs/coremark/defconfig b/boards/risc-v/esp32c6/esp32c6-devkit/configs/coremark/defconfig deleted file mode 100644 index 5fcd33b030fcd..0000000000000 --- a/boards/risc-v/esp32c6/esp32c6-devkit/configs/coremark/defconfig +++ /dev/null @@ -1,33 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NDEBUG is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c6-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C6_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c6" -CONFIG_ARCH_CHIP_ESP32C6=y -CONFIG_ARCH_CHIP_ESP32C6WROOM1=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_BENCHMARK_COREMARK=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_DEBUG_CUSTOMOPT=y -CONFIG_DEBUG_OPTLEVEL="-O3" -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=3072 -CONFIG_INIT_ENTRYPOINT="coremark_main" -CONFIG_INIT_STACKSIZE=3072 -CONFIG_INTELHEX_BINARY=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkit/configs/nsh/defconfig b/boards/risc-v/esp32c6/esp32c6-devkit/configs/nsh/defconfig deleted file mode 100644 index 71584df0f9d78..0000000000000 --- a/boards/risc-v/esp32c6/esp32c6-devkit/configs/nsh/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c6-devkit" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C6_DEVKIT=y -CONFIG_ARCH_CHIP="esp32c6" -CONFIG_ARCH_CHIP_ESP32C6=y -CONFIG_ARCH_CHIP_ESP32C6WROOM1=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y -CONFIG_DEV_ZERO=y -CONFIG_FRAME_POINTER=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkit/include/board.h b/boards/risc-v/esp32c6/esp32c6-devkit/include/board.h deleted file mode 100644 index def71e6886302..0000000000000 --- a/boards/risc-v/esp32c6/esp32c6-devkit/include/board.h +++ /dev/null @@ -1,33 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c6/esp32c6-devkit/include/board.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKIT_INCLUDE_BOARD_H -#define __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKIT_INCLUDE_BOARD_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Clocking *****************************************************************/ - -#define BOARD_XTAL_FREQUENCY 40000000 - -#endif /* __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKIT_INCLUDE_BOARD_H */ - diff --git a/boards/risc-v/esp32c6/esp32c6-devkit/scripts/Make.defs b/boards/risc-v/esp32c6/esp32c6-devkit/scripts/Make.defs deleted file mode 100644 index bad90b6473878..0000000000000 --- a/boards/risc-v/esp32c6/esp32c6-devkit/scripts/Make.defs +++ /dev/null @@ -1,56 +0,0 @@ -############################################################################ -# boards/risc-v/esp32c6/esp32c6-devkit/scripts/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -########################################################################### - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/tools/esp32c6/Config.mk -include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs - -ARCHSCRIPT += $(BOARD_COMMON_DIR)$(DELIM)scripts$(DELIM)esp32c6_rom.ld - -# Pick the linker scripts from the board level if they exist, if not -# pick the common linker scripts. - -ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) -ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) - -ARCHPICFLAGS = -fpic - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -Werror=return-type -Werror -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -# Loadable module definitions - -CMODULEFLAGS = $(CFLAGS) - -LDMODULEFLAGS = -melf32lriscv -r -e module_initialize -LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld) - -# ELF module definitions - -CELFFLAGS = $(CFLAGS) -CXXELFFLAGS = $(CXXFLAGS) - -LDELFFLAGS = -melf32lriscv -r -e main -LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)$(DELIM)binfmt$(DELIM)libelf$(DELIM)gnu-elf.ld) diff --git a/boards/risc-v/esp32c6/esp32c6-devkit/src/Make.defs b/boards/risc-v/esp32c6/esp32c6-devkit/src/Make.defs deleted file mode 100644 index 2faeed7ff35b1..0000000000000 --- a/boards/risc-v/esp32c6/esp32c6-devkit/src/Make.defs +++ /dev/null @@ -1,34 +0,0 @@ -############################################################################# -# boards/risc-v/esp32c6/esp32c6-devkit/src/Makefile -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################# - -include $(TOPDIR)/Make.defs - -CSRCS = esp32c6_boot.c esp32c6_bringup.c - -ifeq ($(CONFIG_BOARDCTL),y) -CSRCS += esp32c6_appinit.c -ifeq ($(CONFIG_BOARDCTL_RESET),y) -CSRCS += esp32c6_reset.c -endif -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6-devkit.h b/boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6-devkit.h deleted file mode 100644 index 3756d0806e3b9..0000000000000 --- a/boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6-devkit.h +++ /dev/null @@ -1,67 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6-devkit.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKIT_SRC_ESP32C6_DEVKIT_H -#define __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKIT_SRC_ESP32C6_DEVKIT_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c6_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_LIB_BOARDCTL=y : - * Called from the NSH library via board_app_initialize() - * - ****************************************************************************/ - -int esp32c6_bringup(void); - -#endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKIT_SRC_ESP32C6_DEVKIT_H */ diff --git a/boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_appinit.c b/boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_appinit.c deleted file mode 100644 index 556802578a59b..0000000000000 --- a/boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_appinit.c +++ /dev/null @@ -1,80 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_appinit.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "esp32c6-devkit.h" - -#ifdef CONFIG_BOARDCTL - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_app_initialize - * - * Description: - * Perform application specific initialization. This function is never - * called directly from application code, but only indirectly via the - * (non-standard) boardctl() interface using the command BOARDIOC_INIT. - * - * Input Parameters: - * arg - The boardctl() argument is passed to the board_app_initialize() - * implementation without modification. The argument has no - * meaning to NuttX; the meaning of the argument is a contract - * between the board-specific initialization logic and the - * matching application logic. The value could be such things as a - * mode enumeration value, a set of DIP switch settings, a - * pointer to configuration data read from a file or serial FLASH, - * or whatever you would like to do with it. Every implementation - * should accept zero/NULL as a default configuration. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure to indicate the nature of the failure. - * - ****************************************************************************/ - -int board_app_initialize(uintptr_t arg) -{ -#ifdef CONFIG_BOARD_LATE_INITIALIZE - /* Board initialization already performed by board_late_initialize() */ - - return OK; -#else - /* Perform board-specific initialization */ - - return esp32c6_bringup(); -#endif -} - -#endif /* CONFIG_BOARDCTL */ diff --git a/boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_boot.c b/boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_boot.c deleted file mode 100644 index f72e6f33cd761..0000000000000 --- a/boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_boot.c +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_boot.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include -#include - -#include "esp32c6-devkit.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c6_board_initialize - * - * Description: - * All ESP32C6 architectures must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - ****************************************************************************/ - -void esp32c6_board_initialize(void) -{ - /* Configure on-board LEDs if LED support has been selected. */ - -#ifdef CONFIG_ARCH_LEDS - board_autoled_initialize(); -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - esp32c6_bringup(); -} -#endif diff --git a/boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_bringup.c b/boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_bringup.c deleted file mode 100644 index 59dbf68268418..0000000000000 --- a/boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_bringup.c +++ /dev/null @@ -1,86 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_bringup.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "esp32c6-devkit.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32c6_bringup - * - * Description: - * Perform architecture-specific initialization - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y : - * Called from the NSH library - * - ****************************************************************************/ - -int esp32c6_bringup(void) -{ - int ret; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); - } -#endif - - /* If we got here then perhaps not all initialization was successful, but - * at least enough succeeded to bring-up NSH with perhaps reduced - * capabilities. - */ - - UNUSED(ret); - return OK; -} diff --git a/boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_reset.c b/boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_reset.c deleted file mode 100644 index b0af460d247b8..0000000000000 --- a/boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_reset.c +++ /dev/null @@ -1,63 +0,0 @@ -/**************************************************************************** - * boards/risc-v/esp32c6/esp32c6-devkit/src/esp32c6_reset.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value in this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - up_systemreset(); - - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/Kconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/Kconfig new file mode 100644 index 0000000000000..e5a4b21549e37 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_ESP32C6_DEVKITC + +endif # ARCH_BOARD_ESP32C6_DEVKITC diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/buttons/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/buttons/defconfig new file mode 100644 index 0000000000000..191455ae8cf17 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/buttons/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESPRESSIF_GPIO_IRQ=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/gpio/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/gpio/defconfig new file mode 100644 index 0000000000000..3305fa6ed7ba1 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/gpio/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_GPIO=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESPRESSIF_GPIO_IRQ=y +CONFIG_EXAMPLES_GPIO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/nsh/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/nsh/defconfig new file mode 100644 index 0000000000000..b1472b5bbb893 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/nsh/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/ostest/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/ostest/defconfig new file mode 100644 index 0000000000000..4e6d27267bbdc --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/ostest/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/pwm/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/pwm/defconfig new file mode 100644 index 0000000000000..8d2ae636982df --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/pwm/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESPRESSIF_LEDC=y +CONFIG_ESPRESSIF_LEDC_TIMER0=y +CONFIG_EXAMPLES_PWM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/random/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/random/defconfig new file mode 100644 index 0000000000000..dfb6e66ef2790 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/random/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_URANDOM=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_EXAMPLES_RANDOM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2023 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/rmt/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/rmt/defconfig new file mode 100644 index 0000000000000..bc2256d9e4569 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/rmt/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESP_RMT=y +CONFIG_EXAMPLES_RMTCHAR=y +CONFIG_EXAMPLES_RMTCHAR_RX=y +CONFIG_EXAMPLES_RMTCHAR_RX_DEVPATH="/dev/rmt2" +CONFIG_EXAMPLES_RMTCHAR_TX=y +CONFIG_EXAMPLES_WS2812=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RMT=y +CONFIG_RMTCHAR=y +CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE=512 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WS2812=y +CONFIG_WS2812_LED_COUNT=100 +CONFIG_WS2812_NON_SPI_DRIVER=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/rtc/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/rtc/defconfig new file mode 100644 index 0000000000000..44d530c38658c --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/rtc/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_DATE=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_ALARM=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=4 +CONFIG_START_YEAR=2023 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/spiflash/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/spiflash/defconfig new file mode 100644 index 0000000000000..34d7c0826af9c --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/spiflash/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESPRESSIF_SPIFLASH=y +CONFIG_ESPRESSIF_SPIFLASH_SMARTFS=y +CONFIG_ESPRESSIF_STORAGE_MTD_OFFSET=0x110000 +CONFIG_ESPRESSIF_STORAGE_MTD_SIZE=0xf0000 +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NAME_MAX=48 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_LOSMART=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_SMARTFS_MAXNAMLEN=48 +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_FLASH_ERASEALL=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_FSTEST=y +CONFIG_TESTING_FSTEST_MOUNTPT="/mnt" +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/sta_softap/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/sta_softap/defconfig new file mode 100644 index 0000000000000..98a7f6d7fd9b1 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/sta_softap/defconfig @@ -0,0 +1,84 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NDEBUG is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESPRESSIF_SPIFLASH=y +CONFIG_ESPRESSIF_SPIFLASH_SPIFFS=y +CONFIG_ESPRESSIF_WIFI=y +CONFIG_ESPRESSIF_WIFI_STATION_SOFTAP=y +CONFIG_EXAMPLES_DHCPD=y +CONFIG_EXAMPLES_RANDOM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=8192 +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_THROTTLE=24 +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETDEV_WORK_THREAD=y +CONFIG_NETUTILS_CJSON=y +CONFIG_NETUTILS_DHCPD=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_DELAYED_ACK=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_DEFAULT=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_TLS_TASK_NELEM=4 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y +CONFIG_WIRELESS_WAPI_INITCONF=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/tickless/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/tickless/defconfig new file mode 100644 index 0000000000000..863b89814802c --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/tickless/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_TICKLESS=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USEC_PER_TICK=10000 diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/timers/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/timers/defconfig new file mode 100644 index 0000000000000..1c1443314cf8c --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/timers/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_EXAMPLES_ONESHOT=y +CONFIG_EXAMPLES_TIMER=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_ONESHOT=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=28 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2023 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_TIMER=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/twai/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/twai/defconfig new file mode 100644 index 0000000000000..07dbe7953739d --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/twai/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESPRESSIF_TWAI0=y +CONFIG_EXAMPLES_CAN=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/usbconsole/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/usbconsole/defconfig new file mode 100644 index 0000000000000..fd54523bd2554 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/usbconsole/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ESPRESSIF_UART0 is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESPRESSIF_USBSERIAL=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/watchdog/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/watchdog/defconfig new file mode 100644 index 0000000000000..e114433d41f5f --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/watchdog/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESPRESSIF_MWDT0=y +CONFIG_ESPRESSIF_MWDT1=y +CONFIG_EXAMPLES_WATCHDOG=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/wifi/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/wifi/defconfig new file mode 100644 index 0000000000000..1777c25bcd331 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/wifi/defconfig @@ -0,0 +1,80 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NDEBUG is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESPRESSIF_SPIFLASH=y +CONFIG_ESPRESSIF_SPIFLASH_SPIFFS=y +CONFIG_ESPRESSIF_WIFI=y +CONFIG_EXAMPLES_RANDOM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=8192 +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_THROTTLE=24 +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETDEV_WORK_THREAD=y +CONFIG_NETUTILS_CJSON=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_DELAYED_ACK=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_DEFAULT=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_TLS_TASK_NELEM=4 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y +CONFIG_WIRELESS_WAPI_INITCONF=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/include/board.h b/boards/risc-v/esp32c6/esp32c6-devkitc/include/board.h new file mode 100644 index 0000000000000..bccce6531cdbb --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/include/board.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/esp32c6-devkitc/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKITC_INCLUDE_BOARD_H +#define __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKITC_INCLUDE_BOARD_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* GPIO pins used by the GPIO Subsystem */ + +#define BOARD_NGPIOOUT 2 /* Amount of GPIO Output pins */ +#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ + +/* ESP32C6-Generic GPIOs ****************************************************/ + +/* BOOT Button */ + +#define BUTTON_BOOT 9 + +#endif /* __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKITC_INCLUDE_BOARD_H */ + diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/scripts/Make.defs b/boards/risc-v/esp32c6/esp32c6-devkitc/scripts/Make.defs new file mode 100644 index 0000000000000..0402a2c36f254 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/scripts/Make.defs @@ -0,0 +1,64 @@ +############################################################################ +# boards/risc-v/esp32c6/esp32c6-devkitc/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +########################################################################### + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/tools/espressif/Config.mk +include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs + +# Remove quotes from CONFIG_ESPRESSIF_CHIP_SERIES configuration + +CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES)) + +# Pick the linker scripts from the board level if they exist, if not +# pick the common linker scripts. + +ARCHSCRIPT += $(BOARD_COMMON_DIR)/scripts/$(CHIP_SERIES)_aliases.ld +ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_flat_memory.ld) + +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_simple_boot_sections.ld) +else + ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_legacy_sections.ld) +endif + +ARCHPICFLAGS = -fpic + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -Werror=return-type -Werror +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) + +LDMODULEFLAGS = -melf32lriscv -r -e module_initialize +LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld) + +# ELF module definitions + +CELFFLAGS = $(CFLAGS) +CXXELFFLAGS = $(CXXFLAGS) + +LDELFFLAGS = -melf32lriscv -r -e main +LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/binfmt/libelf/gnu-elf.ld) diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/src/Make.defs b/boards/risc-v/esp32c6/esp32c6-devkitc/src/Make.defs new file mode 100644 index 0000000000000..700ca6648ac97 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/src/Make.defs @@ -0,0 +1,43 @@ +############################################################################# +# boards/risc-v/esp32c6/esp32c6-devkitc/src/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +CSRCS = esp32c6_boot.c esp32c6_bringup.c + +ifeq ($(CONFIG_BOARDCTL),y) + CSRCS += esp32c6_appinit.c + + ifeq ($(CONFIG_BOARDCTL_RESET),y) + CSRCS += esp32c6_reset.c + endif +endif + +ifeq ($(CONFIG_DEV_GPIO),y) + CSRCS += esp32c6_gpio.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) + CSRCS += esp32c6_buttons.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6-devkitc.h b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6-devkitc.h new file mode 100644 index 0000000000000..bf9551b5edbeb --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6-devkitc.h @@ -0,0 +1,119 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6-devkitc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKITC_SRC_ESP32C6_DEVKITC_H +#define __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKITC_SRC_ESP32C6_DEVKITC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RMT gpio */ + +#define RMT_RXCHANNEL 2 +#define RMT_TXCHANNEL 0 + +#ifdef CONFIG_RMT_LOOP_TEST_MODE +# define RMT_INPUT_PIN 0 +# define RMT_OUTPUT_PIN 0 +#else +# define RMT_INPUT_PIN 2 +# define RMT_OUTPUT_PIN 8 +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_bringup + * + * Description: + * Perform architecture-specific initialization. + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y : + * Called from the NSH library via board_app_initialize(). + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int esp_bringup(void); + +/**************************************************************************** + * Name: board_twai_setup + * + * Description: + * Initialize TWAI and register the TWAI device + * + * Input Parameters: + * port - Port number (for hardware that has multiple TWAI interfaces) + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_TWAI +int board_twai_setup(int port); +#endif + +/**************************************************************************** + * Name: esp_gpio_init + * + * Description: + * Configure the GPIO driver. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +#ifdef CONFIG_DEV_GPIO +int esp_gpio_init(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKITC_SRC_ESP32C6_DEVKITC_H */ diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_appinit.c b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_appinit.c new file mode 100644 index 0000000000000..0795f4564ab44 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_appinit.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "esp32c6-devkitc.h" + +#ifdef CONFIG_BOARDCTL + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return esp_bringup(); +#endif +} + +#endif /* CONFIG_BOARDCTL */ diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_boot.c b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_boot.c new file mode 100644 index 0000000000000..bf3b3cac14dd3 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_boot.c @@ -0,0 +1,89 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "riscv_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_board_initialize + * + * Description: + * All Espressif boards must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_board_initialize(void) +{ +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + esp_bringup(); +} +#endif diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_bringup.c b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_bringup.c new file mode 100644 index 0000000000000..f353dda0ff735 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_bringup.c @@ -0,0 +1,279 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "esp_board_ledc.h" +#include "esp_board_spiflash.h" + +#ifdef CONFIG_WATCHDOG +# include "espressif/esp_wdt.h" +#endif + +#ifdef CONFIG_TIMER +# include "espressif/esp_timer.h" +#endif + +#ifdef CONFIG_ONESHOT +# include "espressif/esp_oneshot.h" +#endif + +#ifdef CONFIG_RTC_DRIVER +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_DEV_GPIO +# include "espressif/esp_gpio.h" +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_ESP_RMT +# include "esp_board_rmt.h" +#endif + +#ifdef CONFIG_ESPRESSIF_WIFI_BT_COEXIST +# include "esp_coexist_internal.h" +#endif + +#ifdef CONFIG_ESPRESSIF_WIFI +# include "esp_board_wlan.h" +#endif + +#include "esp32c6-devkitc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_bringup + * + * Description: + * Perform architecture-specific initialization. + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y : + * Called from the NSH library via board_app_initialize(). + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int esp_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + _err("Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_TMPFS + /* Mount the tmpfs file system */ + + ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); + if (ret < 0) + { + _err("Failed to mount tmpfs at %s: %d\n", CONFIG_LIBC_TMPDIR, ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_MWDT0 + ret = esp_wdt_initialize("/dev/watchdog0", ESP_WDT_MWDT0); + if (ret < 0) + { + _err("Failed to initialize WDT: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_MWDT1 + ret = esp_wdt_initialize("/dev/watchdog1", ESP_WDT_MWDT1); + if (ret < 0) + { + _err("Failed to initialize WDT: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_RWDT + ret = esp_wdt_initialize("/dev/watchdog2", ESP_WDT_RWDT); + if (ret < 0) + { + _err("Failed to initialize WDT: %d\n", ret); + } +#endif + +#ifdef CONFIG_TIMER + ret = esp_timer_initialize(0); + if (ret < 0) + { + _err("Failed to initialize Timer 0: %d\n", ret); + } + +#ifndef CONFIG_ONESHOT + ret = esp_timer_initialize(1); + if (ret < 0) + { + _err("Failed to initialize Timer 1: %d\n", ret); + } +#endif +#endif + +#ifdef CONFIG_ONESHOT + ret = esp_oneshot_initialize(); + if (ret < 0) + { + _err("Failed to initialize Oneshot Timer: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESP_RMT + ret = board_rmt_txinitialize(RMT_TXCHANNEL, RMT_OUTPUT_PIN); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); + } + + ret = board_rmt_rxinitialize(RMT_RXCHANNEL, RMT_INPUT_PIN); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_RTC_DRIVER + /* Initialize the RTC driver */ + + ret = esp_rtc_driverinit(); + if (ret < 0) + { + _err("Failed to initialize the RTC driver: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_SPIFLASH + ret = board_spiflash_init(); + if (ret) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI Flash\n"); + } +#endif + +#ifdef CONFIG_ESPRESSIF_TWAI0 + + /* Initialize TWAI and register the TWAI driver. */ + + ret = board_twai_setup(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: TWAI0 board_twai_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_TWAI1 + + /* Initialize TWAI and register the TWAI driver. */ + + ret = board_twai_setup(1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: TWAI1 board_twai_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_WIFI_BT_COEXIST + esp_coex_adapter_register(&g_coex_adapter_funcs); + coex_pre_init(); +#endif + +#ifdef CONFIG_ESPRESSIF_WIFI + ret = board_wlan_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize wireless subsystem=%d\n", + ret); + } +#endif + +#ifdef CONFIG_DEV_GPIO + ret = esp_gpio_init(); + if (ret < 0) + { + ierr("Failed to initialize GPIO Driver: %d\n", ret); + } +#endif + +#if defined(CONFIG_INPUT_BUTTONS) && defined(CONFIG_INPUT_BUTTONS_LOWER) + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + ierr("ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_LEDC + ret = board_ledc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_ledc_setup() failed: %d\n", ret); + } +#endif /* CONFIG_ESPRESSIF_LEDC */ + + /* If we got here then perhaps not all initialization was successful, but + * at least enough succeeded to bring-up NSH with perhaps reduced + * capabilities. + */ + + return ret; +} diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_buttons.c b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_buttons.c new file mode 100644 index 0000000000000..d73973070aae7 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_buttons.c @@ -0,0 +1,198 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_buttons.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Config */ + +#include + +/* Libc */ + +#include +#include +#include +#include +#include + +/* NuttX */ + +#include +#include +#include +#include + +/* Arch */ + +#include "espressif/esp_gpio.h" + +/* Board */ + +#include "esp32c6-devkitc.h" +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * Input Parameters: + * None. + * + * Returned Value: + * The number of buttons that were initialized. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP); + return 1; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. + * + * Input Parameters: + * None. + * + * Returned Value: + * An 8-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint8_t ret = 0; + int i = 0; + int n = 0; + + bool b0 = esp_gpioread(BUTTON_BOOT); + + for (i = 0; i < 10; i++) + { + up_mdelay(1); /* TODO */ + + bool b1 = esp_gpioread(BUTTON_BOOT); + + if (b0 == b1) + { + n++; + } + else + { + n = 0; + } + + if (3 == n) + { + break; + } + + b0 = b1; + } + + iinfo("b=%d n=%d\n", b0, n); + + /* Low value means that the button is pressed */ + + if (!b0) + { + ret = 0x1; + } + + return ret; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + * Input Parameters: + * id - Identifies the button to be monitored. It is equivalent to + * the bit used to report the button state in the return value + * from board_buttons(). + * irqhandler - The handler that will be invoked when the interrupt occurs. + * arg - Pointer to the arguments that will be provided to the + * interrupt handler. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret; + DEBUGASSERT(id == 0); + + int irq = ESP_PIN2IRQ(BUTTON_BOOT); + + if (NULL != irqhandler) + { + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(irq); + + gpioinfo("Attach %p\n", irqhandler); + + ret = irq_attach(irq, irqhandler, arg); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); + return ret; + } + + /* Configure the interrupt for rising and falling edges */ + + gpioinfo("Enabling the interrupt\n"); + esp_gpioirqenable(irq, CHANGE); + } + else + { + gpioinfo("Disable the interrupt\n"); + esp_gpioirqdisable(irq); + } + + return OK; +} +#endif diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_gpio.c b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_gpio.c new file mode 100644 index 0000000000000..f6a1dd88eda2f --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_gpio.c @@ -0,0 +1,512 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Config */ + +#include + +/* Libc */ + +#include +#include +#include +#include + +/* NuttX */ + +#include +#include +#include + +/* Arch */ + +#include "espressif/esp_gpio.h" + +/* Board */ + +#include "esp32c6-devkitc.h" +#include + +/* HAL */ + +#include + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Pin 1 and 2 are used for this example as GPIO outputs. */ + +#define GPIO_OUT1 1 +#define GPIO_OUT2 2 + +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 +# error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" +#endif + +/* Interrupt pins. GPIO9 is used as an example, any other inputs could be + * used. + */ + +#define GPIO_IRQPIN 9 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct espgpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct espgpint_dev_s +{ + struct espgpio_dev_s espgpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +static int gpout_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e pintype); +#endif + +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); +static int gpint_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e pintype); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, + .go_setpintype = gpout_setpintype, +}; + +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, GPIO_OUT2 +}; + +static struct espgpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, + .go_setpintype = gpint_setpintype, +}; + +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_IRQPIN, +}; + +static struct espgpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpout_read + * + * Description: + * Read a digital output pin. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * value - A pointer to store the state of the pin. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct espgpio_dev_s *espgpio = (struct espgpio_dev_s *)dev; + + DEBUGASSERT(espgpio != NULL && value != NULL); + DEBUGASSERT(espgpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = esp_gpioread(g_gpiooutputs[espgpio->id]); + return OK; +} + +/**************************************************************************** + * Name: gpout_write + * + * Description: + * Write to a digital output pin. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * value - The value to be written. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct espgpio_dev_s *espgpio = (struct espgpio_dev_s *)dev; + + DEBUGASSERT(espgpio != NULL); + DEBUGASSERT(espgpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + esp_gpiowrite(g_gpiooutputs[espgpio->id], value); + return OK; +} + +/**************************************************************************** + * Name: gpout_setpintype + * + * Description: + * Set digital output pin type. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * pintype - The pin type. See nuttx/ioexpander/gpio.h. + * + * Returned Value: + * Zero (OK) on success; -1 (ERROR) otherwise. + * + ****************************************************************************/ + +static int gpout_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e pintype) +{ + struct espgpio_dev_s *espgpio = (struct espgpio_dev_s *)dev; + + DEBUGASSERT(espgpio != NULL); + DEBUGASSERT(espgpio->id < BOARD_NGPIOOUT); + gpioinfo("Setting pintype: %d\n", (int)pintype); + + esp_gpio_matrix_out(g_gpiooutputs[espgpio->id], + SIG_GPIO_OUT_IDX, 0, 0); + + switch (pintype) + { + case GPIO_INPUT_PIN: + esp_configgpio(g_gpiooutputs[espgpio->id], INPUT); + break; + case GPIO_INPUT_PIN_PULLUP: + esp_configgpio(g_gpiooutputs[espgpio->id], INPUT_PULLUP); + break; + case GPIO_INPUT_PIN_PULLDOWN: + esp_configgpio(g_gpiooutputs[espgpio->id], INPUT_PULLDOWN); + break; + case GPIO_OUTPUT_PIN: + esp_configgpio(g_gpiooutputs[espgpio->id], INPUT | OUTPUT); + break; + case GPIO_OUTPUT_PIN_OPENDRAIN: + esp_configgpio(g_gpiooutputs[espgpio->id], + INPUT | OUTPUT_OPEN_DRAIN); + break; + default: + return ERROR; + break; + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: espgpio_interrupt + * + * Description: + * Digital input interrupt handler. + * + * Input Parameters: + * irq - Identifier of the interrupt request. + * context - Context data from the ISR. + * arg - Opaque pointer to the internal driver state structure. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +#if BOARD_NGPIOINT > 0 +static int espgpio_interrupt(int irq, void *context, void *arg) +{ + struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)arg; + + DEBUGASSERT(espgpint != NULL && espgpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", espgpint->callback); + + espgpint->callback(&espgpint->espgpio.gpio, espgpint->espgpio.id); + return OK; +} + +/**************************************************************************** + * Name: gpint_read + * + * Description: + * Read a digital input pin. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * value - A pointer to store the state of the pin. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct espgpint_dev_s *espgpint = + (struct espgpint_dev_s *)dev; + + DEBUGASSERT(espgpint != NULL && value != NULL); + DEBUGASSERT(espgpint->espgpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = esp_gpioread(g_gpiointinputs[espgpint->espgpio.id]); + return OK; +} + +/**************************************************************************** + * Name: gpint_attach + * + * Description: + * Attach the ISR to IRQ and register the callback. But it still doesn't + * enable interrupt yet. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * callback - User callback function. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct espgpint_dev_s *espgpint = + (struct espgpint_dev_s *)dev; + int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); + int ret; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(irq); + ret = irq_attach(irq, + espgpio_interrupt, + &g_gpint[espgpint->espgpio.id]); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); + return ret; + } + + gpioinfo("Attach %p\n", callback); + espgpint->callback = callback; + return OK; +} + +/**************************************************************************** + * Name: gpint_enable + * + * Description: + * Enable/Disable interrupt. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * enable - True to enable, false to disable. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; + int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); + + if (enable) + { + if (espgpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + esp_gpioirqenable(irq, RISING); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + esp_gpioirqdisable(irq); + } + + return OK; +} + +/**************************************************************************** + * Name: gpint_setpintype + * + * Description: + * Set digital interrupt pin type. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * pintype - The pin type. See nuttx/ioexpander/gpio.h. + * + * Returned Value: + * Zero (OK) on success; -1 (ERROR) otherwise. + * + ****************************************************************************/ + +static int gpint_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e pintype) +{ + struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; + + DEBUGASSERT(espgpint != NULL); + DEBUGASSERT(espgpint->espgpio.id < BOARD_NGPIOINT); + gpioinfo("Setting pintype: %d\n", (int)pintype); + switch (pintype) + { + case GPIO_INTERRUPT_HIGH_PIN: + esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], + INPUT_PULLUP); + break; + case GPIO_INTERRUPT_LOW_PIN: + esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], + INPUT_PULLDOWN); + break; + default: + return ERROR; + break; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_gpio_init + * + * Description: + * Configure the GPIO driver. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +int esp_gpio_init(void) +{ + int pincount = 0; + int i; + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pins that will be used as output */ + + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_1 | INPUT_FUNCTION_1); + esp_gpiowrite(g_gpiooutputs[i], 0); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].espgpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].espgpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].espgpio.id = i; + gpio_pin_register(&g_gpint[i].espgpio.gpio, pincount); + + /* Configure the pins that will be used as interrupt input */ + + esp_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_1 | PULLDOWN); + + pincount++; + } +#endif + + return OK; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_reset.c b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_reset.c new file mode 100644 index 0000000000000..c6bfb5a94f634 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_reset.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_reset.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "espressif/esp_systemreset.h" + +#ifdef CONFIG_BOARDCTL_RESET + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value in this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ + syslog(LOG_INFO, "reboot status=%d\n", status); + + switch (status) + { + case EXIT_SUCCESS: + up_shutdown_handler(); + break; + case CONFIG_BOARD_ASSERT_RESET_VALUE: + default: + break; + } + + up_systemreset(); + + return 0; +} + +#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/Kconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/Kconfig new file mode 100644 index 0000000000000..d10b4750ed886 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_ESP32C6_DEVKITM + +endif # ARCH_BOARD_ESP32C6_DEVKITM diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/buttons/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/buttons/defconfig new file mode 100644 index 0000000000000..d704ddc3998fb --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/buttons/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitm" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITM=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6MINI1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESPRESSIF_GPIO_IRQ=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/gpio/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/gpio/defconfig new file mode 100644 index 0000000000000..785e61b00f723 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/gpio/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitm" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITM=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6MINI1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_GPIO=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESPRESSIF_GPIO_IRQ=y +CONFIG_EXAMPLES_GPIO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/nsh/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/nsh/defconfig new file mode 100644 index 0000000000000..dee9f24e8b413 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/nsh/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitm" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITM=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6MINI1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/ostest/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/ostest/defconfig new file mode 100644 index 0000000000000..9c5ded957727a --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/ostest/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitm" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITM=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6MINI1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/pwm/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/pwm/defconfig new file mode 100644 index 0000000000000..f59571032257f --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/pwm/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitm" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITM=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6MINI1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESPRESSIF_LEDC=y +CONFIG_ESPRESSIF_LEDC_TIMER0=y +CONFIG_EXAMPLES_PWM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/random/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/random/defconfig new file mode 100644 index 0000000000000..10aa7f05a1415 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/random/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitm" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITM=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6MINI1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_URANDOM=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_EXAMPLES_RANDOM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2023 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/rmt/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/rmt/defconfig new file mode 100644 index 0000000000000..83c60a5fd6bd2 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/rmt/defconfig @@ -0,0 +1,60 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitm" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITM=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6MINI1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESP_RMT=y +CONFIG_EXAMPLES_RMTCHAR=y +CONFIG_EXAMPLES_RMTCHAR_RX=y +CONFIG_EXAMPLES_RMTCHAR_RX_DEVPATH="/dev/rmt2" +CONFIG_EXAMPLES_RMTCHAR_TX=y +CONFIG_EXAMPLES_WS2812=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RMT=y +CONFIG_RMTCHAR=y +CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE=512 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WS2812=y +CONFIG_WS2812_LED_COUNT=100 +CONFIG_WS2812_NON_SPI_DRIVER=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/rtc/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/rtc/defconfig new file mode 100644 index 0000000000000..aebbfb3be72c3 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/rtc/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitm" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITM=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6MINI1=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_DATE=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_ALARM=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=4 +CONFIG_START_YEAR=2023 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/spiflash/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/spiflash/defconfig new file mode 100644 index 0000000000000..9cf53838d753d --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/spiflash/defconfig @@ -0,0 +1,56 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitm" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITM=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6MINI1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESPRESSIF_SPIFLASH=y +CONFIG_ESPRESSIF_SPIFLASH_SMARTFS=y +CONFIG_ESPRESSIF_STORAGE_MTD_OFFSET=0x110000 +CONFIG_ESPRESSIF_STORAGE_MTD_SIZE=0xf0000 +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NAME_MAX=48 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_LOSMART=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_SMARTFS_MAXNAMLEN=48 +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_FLASH_ERASEALL=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_FSTEST=y +CONFIG_TESTING_FSTEST_MOUNTPT="/mnt" +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/sta_softap/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/sta_softap/defconfig new file mode 100644 index 0000000000000..98a7f6d7fd9b1 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/sta_softap/defconfig @@ -0,0 +1,84 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NDEBUG is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESPRESSIF_SPIFLASH=y +CONFIG_ESPRESSIF_SPIFLASH_SPIFFS=y +CONFIG_ESPRESSIF_WIFI=y +CONFIG_ESPRESSIF_WIFI_STATION_SOFTAP=y +CONFIG_EXAMPLES_DHCPD=y +CONFIG_EXAMPLES_RANDOM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=8192 +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_THROTTLE=24 +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETDEV_WORK_THREAD=y +CONFIG_NETUTILS_CJSON=y +CONFIG_NETUTILS_DHCPD=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_DELAYED_ACK=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_DEFAULT=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_TLS_TASK_NELEM=4 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y +CONFIG_WIRELESS_WAPI_INITCONF=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/tickless/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/tickless/defconfig new file mode 100644 index 0000000000000..99a9eb50fb4ee --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/tickless/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitm" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITM=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6MINI1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_TICKLESS=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USEC_PER_TICK=10000 diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/timers/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/timers/defconfig new file mode 100644 index 0000000000000..9b45f723e95b2 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/timers/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitm" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITM=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6MINI1=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_EXAMPLES_ONESHOT=y +CONFIG_EXAMPLES_TIMER=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_ONESHOT=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=28 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2023 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_TIMER=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/twai/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/twai/defconfig new file mode 100644 index 0000000000000..8a005b242099b --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/twai/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitm" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITM=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6MINI1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESPRESSIF_TWAI0=y +CONFIG_EXAMPLES_CAN=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/usbconsole/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/usbconsole/defconfig new file mode 100644 index 0000000000000..31f74e696717f --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/usbconsole/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ESPRESSIF_UART0 is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitm" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITM=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6MINI1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESPRESSIF_USBSERIAL=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/watchdog/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/watchdog/defconfig new file mode 100644 index 0000000000000..7ac5f1a14bdd9 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/watchdog/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitm" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITM=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6MINI1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESPRESSIF_MWDT0=y +CONFIG_ESPRESSIF_MWDT1=y +CONFIG_EXAMPLES_WATCHDOG=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/configs/wifi/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/wifi/defconfig new file mode 100644 index 0000000000000..98a7f6d7fd9b1 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/configs/wifi/defconfig @@ -0,0 +1,84 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NDEBUG is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32c6-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32C6_DEVKITC=y +CONFIG_ARCH_CHIP="esp32c6" +CONFIG_ARCH_CHIP_ESP32C6=y +CONFIG_ARCH_CHIP_ESP32C6WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_DRIVERS_IEEE80211=y +CONFIG_DRIVERS_WIRELESS=y +CONFIG_ESPRESSIF_ESP32C6=y +CONFIG_ESPRESSIF_SPIFLASH=y +CONFIG_ESPRESSIF_SPIFLASH_SPIFFS=y +CONFIG_ESPRESSIF_WIFI=y +CONFIG_ESPRESSIF_WIFI_STATION_SOFTAP=y +CONFIG_EXAMPLES_DHCPD=y +CONFIG_EXAMPLES_RANDOM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=8192 +CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_THROTTLE=24 +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_WIRELESS_IOCTL=y +CONFIG_NETDEV_WORK_THREAD=y +CONFIG_NETUTILS_CJSON=y +CONFIG_NETUTILS_DHCPD=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_TCP=y +CONFIG_NET_TCP_DELAYED_ACK=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_DEFAULT=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DHCPC_RENEW=y +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_TLS_TASK_NELEM=4 +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WIRELESS=y +CONFIG_WIRELESS_WAPI=y +CONFIG_WIRELESS_WAPI_CMDTOOL=y +CONFIG_WIRELESS_WAPI_INITCONF=y diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/include/board.h b/boards/risc-v/esp32c6/esp32c6-devkitm/include/board.h new file mode 100644 index 0000000000000..0e49afffa8cb0 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/include/board.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/esp32c6-devkitm/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKITM_INCLUDE_BOARD_H +#define __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKITM_INCLUDE_BOARD_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* GPIO pins used by the GPIO Subsystem */ + +#define BOARD_NGPIOOUT 2 /* Amount of GPIO Output pins */ +#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ + +/* ESP32C6-Generic GPIOs ****************************************************/ + +/* BOOT Button */ + +#define BUTTON_BOOT 9 + +#endif /* __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKITM_INCLUDE_BOARD_H */ + diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/scripts/Make.defs b/boards/risc-v/esp32c6/esp32c6-devkitm/scripts/Make.defs new file mode 100644 index 0000000000000..c8c8cea774c77 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/scripts/Make.defs @@ -0,0 +1,64 @@ +############################################################################ +# boards/risc-v/esp32c6/esp32c6-devkitm/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +########################################################################### + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/tools/espressif/Config.mk +include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs + +# Remove quotes from CONFIG_ESPRESSIF_CHIP_SERIES configuration + +CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES)) + +# Pick the linker scripts from the board level if they exist, if not +# pick the common linker scripts. + +ARCHSCRIPT += $(BOARD_COMMON_DIR)/scripts/$(CHIP_SERIES)_aliases.ld +ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_flat_memory.ld) + +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_simple_boot_sections.ld) +else + ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_legacy_sections.ld) +endif + +ARCHPICFLAGS = -fpic + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -Werror=return-type -Werror +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) + +LDMODULEFLAGS = -melf32lriscv -r -e module_initialize +LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld) + +# ELF module definitions + +CELFFLAGS = $(CFLAGS) +CXXELFFLAGS = $(CXXFLAGS) + +LDELFFLAGS = -melf32lriscv -r -e main +LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/binfmt/libelf/gnu-elf.ld) diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/src/Make.defs b/boards/risc-v/esp32c6/esp32c6-devkitm/src/Make.defs new file mode 100644 index 0000000000000..a1786c4b01af6 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/src/Make.defs @@ -0,0 +1,43 @@ +############################################################################# +# boards/risc-v/esp32c6/esp32c6-devkitm/src/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +CSRCS = esp32c6_boot.c esp32c6_bringup.c + +ifeq ($(CONFIG_BOARDCTL),y) + CSRCS += esp32c6_appinit.c + + ifeq ($(CONFIG_BOARDCTL_RESET),y) + CSRCS += esp32c6_reset.c + endif +endif + +ifeq ($(CONFIG_DEV_GPIO),y) + CSRCS += esp32c6_gpio.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) + CSRCS += esp32c6_buttons.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6-devkitm.h b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6-devkitm.h new file mode 100644 index 0000000000000..37ec160e064cf --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6-devkitm.h @@ -0,0 +1,119 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6-devkitm.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKITM_SRC_ESP32C6_DEVKITM_H +#define __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKITM_SRC_ESP32C6_DEVKITM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RMT gpio */ + +#define RMT_RXCHANNEL 2 +#define RMT_TXCHANNEL 0 + +#ifdef CONFIG_RMT_LOOP_TEST_MODE +# define RMT_INPUT_PIN 0 +# define RMT_OUTPUT_PIN 0 +#else +# define RMT_INPUT_PIN 2 +# define RMT_OUTPUT_PIN 8 +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_bringup + * + * Description: + * Perform architecture-specific initialization. + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y : + * Called from the NSH library via board_app_initialize(). + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int esp_bringup(void); + +/**************************************************************************** + * Name: board_twai_setup + * + * Description: + * Initialize TWAI and register the TWAI device + * + * Input Parameters: + * port - Port number (for hardware that has multiple TWAI interfaces) + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_TWAI +int board_twai_setup(int port); +#endif + +/**************************************************************************** + * Name: esp_gpio_init + * + * Description: + * Configure the GPIO driver. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +#ifdef CONFIG_DEV_GPIO +int esp_gpio_init(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISCV_ESP32C6_ESP32C6_DEVKITM_SRC_ESP32C6_DEVKITM_H */ diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_appinit.c b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_appinit.c new file mode 100644 index 0000000000000..b406972ff99a3 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_appinit.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "esp32c6-devkitm.h" + +#ifdef CONFIG_BOARDCTL + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return esp_bringup(); +#endif +} + +#endif /* CONFIG_BOARDCTL */ diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_boot.c b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_boot.c new file mode 100644 index 0000000000000..c19f5519a1df4 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_boot.c @@ -0,0 +1,89 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "riscv_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_board_initialize + * + * Description: + * All Espressif boards must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_board_initialize(void) +{ +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + + esp_bringup(); +} +#endif diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_bringup.c b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_bringup.c new file mode 100644 index 0000000000000..03737dfe4431f --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_bringup.c @@ -0,0 +1,279 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "esp_board_ledc.h" +#include "esp_board_spiflash.h" + +#ifdef CONFIG_WATCHDOG +# include "espressif/esp_wdt.h" +#endif + +#ifdef CONFIG_TIMER +# include "espressif/esp_timer.h" +#endif + +#ifdef CONFIG_ONESHOT +# include "espressif/esp_oneshot.h" +#endif + +#ifdef CONFIG_RTC_DRIVER +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_DEV_GPIO +# include "espressif/esp_gpio.h" +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_ESP_RMT +# include "esp_board_rmt.h" +#endif + +#ifdef CONFIG_ESPRESSIF_WIFI_BT_COEXIST +# include "esp_coexist_internal.h" +#endif + +#ifdef CONFIG_ESPRESSIF_WIFI +# include "esp_board_wlan.h" +#endif + +#include "esp32c6-devkitm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_bringup + * + * Description: + * Perform architecture-specific initialization. + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y : + * Called from the NSH library via board_app_initialize(). + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int esp_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + _err("Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_TMPFS + /* Mount the tmpfs file system */ + + ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); + if (ret < 0) + { + _err("Failed to mount tmpfs at %s: %d\n", CONFIG_LIBC_TMPDIR, ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_MWDT0 + ret = esp_wdt_initialize("/dev/watchdog0", ESP_WDT_MWDT0); + if (ret < 0) + { + _err("Failed to initialize WDT: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_MWDT1 + ret = esp_wdt_initialize("/dev/watchdog1", ESP_WDT_MWDT1); + if (ret < 0) + { + _err("Failed to initialize WDT: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_RWDT + ret = esp_wdt_initialize("/dev/watchdog2", ESP_WDT_RWDT); + if (ret < 0) + { + _err("Failed to initialize WDT: %d\n", ret); + } +#endif + +#ifdef CONFIG_TIMER + ret = esp_timer_initialize(0); + if (ret < 0) + { + _err("Failed to initialize Timer 0: %d\n", ret); + } + +#ifndef CONFIG_ONESHOT + ret = esp_timer_initialize(1); + if (ret < 0) + { + _err("Failed to initialize Timer 1: %d\n", ret); + } +#endif +#endif + +#ifdef CONFIG_ONESHOT + ret = esp_oneshot_initialize(); + if (ret < 0) + { + _err("Failed to initialize Oneshot Timer: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESP_RMT + ret = board_rmt_txinitialize(RMT_TXCHANNEL, RMT_OUTPUT_PIN); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); + } + + ret = board_rmt_rxinitialize(RMT_RXCHANNEL, RMT_INPUT_PIN); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_RTC_DRIVER + /* Initialize the RTC driver */ + + ret = esp_rtc_driverinit(); + if (ret < 0) + { + _err("Failed to initialize the RTC driver: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_SPIFLASH + ret = board_spiflash_init(); + if (ret) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI Flash\n"); + } +#endif + +#ifdef CONFIG_ESPRESSIF_TWAI0 + + /* Initialize TWAI and register the TWAI driver. */ + + ret = board_twai_setup(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_twai_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_TWAI1 + + /* Initialize TWAI and register the TWAI driver. */ + + ret = board_twai_setup(1); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_twai_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_WIFI_BT_COEXIST + esp_coex_adapter_register(&g_coex_adapter_funcs); + coex_pre_init(); +#endif + +#ifdef CONFIG_ESPRESSIF_WIFI + ret = board_wlan_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize wireless subsystem=%d\n", + ret); + } +#endif + +#ifdef CONFIG_DEV_GPIO + ret = esp_gpio_init(); + if (ret < 0) + { + ierr("Failed to initialize GPIO Driver: %d\n", ret); + } +#endif + +#if defined(CONFIG_INPUT_BUTTONS) && defined(CONFIG_INPUT_BUTTONS_LOWER) + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + ierr("ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_LEDC + ret = board_ledc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_ledc_setup() failed: %d\n", ret); + } +#endif /* CONFIG_ESPRESSIF_LEDC */ + + /* If we got here then perhaps not all initialization was successful, but + * at least enough succeeded to bring-up NSH with perhaps reduced + * capabilities. + */ + + return ret; +} diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_buttons.c b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_buttons.c new file mode 100644 index 0000000000000..43bba7c094a78 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_buttons.c @@ -0,0 +1,198 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_buttons.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Config */ + +#include + +/* Libc */ + +#include +#include +#include +#include +#include + +/* NuttX */ + +#include +#include +#include +#include + +/* Arch */ + +#include "espressif/esp_gpio.h" + +/* Board */ + +#include "esp32c6-devkitm.h" +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * Input Parameters: + * None. + * + * Returned Value: + * The number of buttons that were initialized. + * + ****************************************************************************/ + +uint32_t board_button_initialize(void) +{ + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP); + return 1; +} + +/**************************************************************************** + * Name: board_buttons + * + * Description: + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. + * + * Input Parameters: + * None. + * + * Returned Value: + * An 8-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT definitions in board.h for the meaning of each bit. + * + ****************************************************************************/ + +uint32_t board_buttons(void) +{ + uint8_t ret = 0; + int i = 0; + int n = 0; + + bool b0 = esp_gpioread(BUTTON_BOOT); + + for (i = 0; i < 10; i++) + { + up_mdelay(1); /* TODO */ + + bool b1 = esp_gpioread(BUTTON_BOOT); + + if (b0 == b1) + { + n++; + } + else + { + n = 0; + } + + if (3 == n) + { + break; + } + + b0 = b1; + } + + iinfo("b=%d n=%d\n", b0, n); + + /* Low value means that the button is pressed */ + + if (!b0) + { + ret = 0x1; + } + + return ret; +} + +/**************************************************************************** + * Name: board_button_irq + * + * Description: + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. + * + * Input Parameters: + * id - Identifies the button to be monitored. It is equivalent to + * the bit used to report the button state in the return value + * from board_buttons(). + * irqhandler - The handler that will be invoked when the interrupt occurs. + * arg - Pointer to the arguments that will be provided to the + * interrupt handler. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +int board_button_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret; + DEBUGASSERT(id == 0); + + int irq = ESP_PIN2IRQ(BUTTON_BOOT); + + if (NULL != irqhandler) + { + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(irq); + + gpioinfo("Attach %p\n", irqhandler); + + ret = irq_attach(irq, irqhandler, arg); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); + return ret; + } + + /* Configure the interrupt for rising and falling edges */ + + gpioinfo("Enabling the interrupt\n"); + esp_gpioirqenable(irq, CHANGE); + } + else + { + gpioinfo("Disable the interrupt\n"); + esp_gpioirqdisable(irq); + } + + return OK; +} +#endif diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_gpio.c b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_gpio.c new file mode 100644 index 0000000000000..acbac397e35c1 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_gpio.c @@ -0,0 +1,512 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Config */ + +#include + +/* Libc */ + +#include +#include +#include +#include + +/* NuttX */ + +#include +#include +#include + +/* Arch */ + +#include "espressif/esp_gpio.h" + +/* Board */ + +#include "esp32c6-devkitm.h" +#include + +/* HAL */ + +#include + +#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Pin 1 and 2 are used for this example as GPIO outputs. */ + +#define GPIO_OUT1 1 +#define GPIO_OUT2 2 + +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 +# error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" +#endif + +/* Interrupt pins. GPIO9 is used as an example, any other inputs could be + * used. + */ + +#define GPIO_IRQPIN 9 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct espgpio_dev_s +{ + struct gpio_dev_s gpio; + uint8_t id; +}; + +struct espgpint_dev_s +{ + struct espgpio_dev_s espgpio; + pin_interrupt_t callback; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value); +static int gpout_write(struct gpio_dev_s *dev, bool value); +static int gpout_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e pintype); +#endif + +#if BOARD_NGPIOINT > 0 +static int gpint_read(struct gpio_dev_s *dev, bool *value); +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback); +static int gpint_enable(struct gpio_dev_s *dev, bool enable); +static int gpint_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e pintype); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static const struct gpio_operations_s gpout_ops = +{ + .go_read = gpout_read, + .go_write = gpout_write, + .go_attach = NULL, + .go_enable = NULL, + .go_setpintype = gpout_setpintype, +}; + +/* This array maps the GPIO pins used as OUTPUT */ + +static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = +{ + GPIO_OUT1, GPIO_OUT2 +}; + +static struct espgpio_dev_s g_gpout[BOARD_NGPIOOUT]; +#endif + +#if BOARD_NGPIOINT > 0 +static const struct gpio_operations_s gpint_ops = +{ + .go_read = gpint_read, + .go_write = NULL, + .go_attach = gpint_attach, + .go_enable = gpint_enable, + .go_setpintype = gpint_setpintype, +}; + +/* This array maps the GPIO pins used as INTERRUPT INPUTS */ + +static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = +{ + GPIO_IRQPIN, +}; + +static struct espgpint_dev_s g_gpint[BOARD_NGPIOINT]; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gpout_read + * + * Description: + * Read a digital output pin. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * value - A pointer to store the state of the pin. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +#if BOARD_NGPIOOUT > 0 +static int gpout_read(struct gpio_dev_s *dev, bool *value) +{ + struct espgpio_dev_s *espgpio = (struct espgpio_dev_s *)dev; + + DEBUGASSERT(espgpio != NULL && value != NULL); + DEBUGASSERT(espgpio->id < BOARD_NGPIOOUT); + gpioinfo("Reading...\n"); + + *value = esp_gpioread(g_gpiooutputs[espgpio->id]); + return OK; +} + +/**************************************************************************** + * Name: gpout_write + * + * Description: + * Write to a digital output pin. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * value - The value to be written. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +static int gpout_write(struct gpio_dev_s *dev, bool value) +{ + struct espgpio_dev_s *espgpio = (struct espgpio_dev_s *)dev; + + DEBUGASSERT(espgpio != NULL); + DEBUGASSERT(espgpio->id < BOARD_NGPIOOUT); + gpioinfo("Writing %d\n", (int)value); + + esp_gpiowrite(g_gpiooutputs[espgpio->id], value); + return OK; +} + +/**************************************************************************** + * Name: gpout_setpintype + * + * Description: + * Set digital output pin type. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * pintype - The pin type. See nuttx/ioexpander/gpio.h. + * + * Returned Value: + * Zero (OK) on success; -1 (ERROR) otherwise. + * + ****************************************************************************/ + +static int gpout_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e pintype) +{ + struct espgpio_dev_s *espgpio = (struct espgpio_dev_s *)dev; + + DEBUGASSERT(espgpio != NULL); + DEBUGASSERT(espgpio->id < BOARD_NGPIOOUT); + gpioinfo("Setting pintype: %d\n", (int)pintype); + + esp_gpio_matrix_out(g_gpiooutputs[espgpio->id], + SIG_GPIO_OUT_IDX, 0, 0); + + switch (pintype) + { + case GPIO_INPUT_PIN: + esp_configgpio(g_gpiooutputs[espgpio->id], INPUT); + break; + case GPIO_INPUT_PIN_PULLUP: + esp_configgpio(g_gpiooutputs[espgpio->id], INPUT_PULLUP); + break; + case GPIO_INPUT_PIN_PULLDOWN: + esp_configgpio(g_gpiooutputs[espgpio->id], INPUT_PULLDOWN); + break; + case GPIO_OUTPUT_PIN: + esp_configgpio(g_gpiooutputs[espgpio->id], INPUT | OUTPUT); + break; + case GPIO_OUTPUT_PIN_OPENDRAIN: + esp_configgpio(g_gpiooutputs[espgpio->id], + INPUT | OUTPUT_OPEN_DRAIN); + break; + default: + return ERROR; + break; + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: espgpio_interrupt + * + * Description: + * Digital input interrupt handler. + * + * Input Parameters: + * irq - Identifier of the interrupt request. + * context - Context data from the ISR. + * arg - Opaque pointer to the internal driver state structure. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +#if BOARD_NGPIOINT > 0 +static int espgpio_interrupt(int irq, void *context, void *arg) +{ + struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)arg; + + DEBUGASSERT(espgpint != NULL && espgpint->callback != NULL); + gpioinfo("Interrupt! callback=%p\n", espgpint->callback); + + espgpint->callback(&espgpint->espgpio.gpio, espgpint->espgpio.id); + return OK; +} + +/**************************************************************************** + * Name: gpint_read + * + * Description: + * Read a digital input pin. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * value - A pointer to store the state of the pin. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +static int gpint_read(struct gpio_dev_s *dev, bool *value) +{ + struct espgpint_dev_s *espgpint = + (struct espgpint_dev_s *)dev; + + DEBUGASSERT(espgpint != NULL && value != NULL); + DEBUGASSERT(espgpint->espgpio.id < BOARD_NGPIOINT); + gpioinfo("Reading int pin...\n"); + + *value = esp_gpioread(g_gpiointinputs[espgpint->espgpio.id]); + return OK; +} + +/**************************************************************************** + * Name: gpint_attach + * + * Description: + * Attach the ISR to IRQ and register the callback. But it still doesn't + * enable interrupt yet. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * callback - User callback function. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +static int gpint_attach(struct gpio_dev_s *dev, + pin_interrupt_t callback) +{ + struct espgpint_dev_s *espgpint = + (struct espgpint_dev_s *)dev; + int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); + int ret; + + gpioinfo("Attaching the callback\n"); + + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(irq); + ret = irq_attach(irq, + espgpio_interrupt, + &g_gpint[espgpint->espgpio.id]); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); + return ret; + } + + gpioinfo("Attach %p\n", callback); + espgpint->callback = callback; + return OK; +} + +/**************************************************************************** + * Name: gpint_enable + * + * Description: + * Enable/Disable interrupt. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * enable - True to enable, false to disable. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +static int gpint_enable(struct gpio_dev_s *dev, bool enable) +{ + struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; + int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); + + if (enable) + { + if (espgpint->callback != NULL) + { + gpioinfo("Enabling the interrupt\n"); + + /* Configure the interrupt for rising edge */ + + esp_gpioirqenable(irq, RISING); + } + } + else + { + gpioinfo("Disable the interrupt\n"); + esp_gpioirqdisable(irq); + } + + return OK; +} + +/**************************************************************************** + * Name: gpint_setpintype + * + * Description: + * Set digital interrupt pin type. + * + * Parameters: + * dev - A pointer to the gpio driver struct. + * pintype - The pin type. See nuttx/ioexpander/gpio.h. + * + * Returned Value: + * Zero (OK) on success; -1 (ERROR) otherwise. + * + ****************************************************************************/ + +static int gpint_setpintype(struct gpio_dev_s *dev, + enum gpio_pintype_e pintype) +{ + struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; + + DEBUGASSERT(espgpint != NULL); + DEBUGASSERT(espgpint->espgpio.id < BOARD_NGPIOINT); + gpioinfo("Setting pintype: %d\n", (int)pintype); + switch (pintype) + { + case GPIO_INTERRUPT_HIGH_PIN: + esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], + INPUT_PULLUP); + break; + case GPIO_INTERRUPT_LOW_PIN: + esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], + INPUT_PULLDOWN); + break; + default: + return ERROR; + break; + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_gpio_init + * + * Description: + * Configure the GPIO driver. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +int esp_gpio_init(void) +{ + int pincount = 0; + int i; + +#if BOARD_NGPIOOUT > 0 + for (i = 0; i < BOARD_NGPIOOUT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; + g_gpout[i].gpio.gp_ops = &gpout_ops; + g_gpout[i].id = i; + gpio_pin_register(&g_gpout[i].gpio, pincount); + + /* Configure the pins that will be used as output */ + + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_1 | INPUT_FUNCTION_1); + esp_gpiowrite(g_gpiooutputs[i], 0); + + pincount++; + } +#endif + +#if BOARD_NGPIOINT > 0 + for (i = 0; i < BOARD_NGPIOINT; i++) + { + /* Setup and register the GPIO pin */ + + g_gpint[i].espgpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; + g_gpint[i].espgpio.gpio.gp_ops = &gpint_ops; + g_gpint[i].espgpio.id = i; + gpio_pin_register(&g_gpint[i].espgpio.gpio, pincount); + + /* Configure the pins that will be used as interrupt input */ + + esp_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_1 | PULLDOWN); + + pincount++; + } +#endif + + return OK; +} +#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_reset.c b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_reset.c new file mode 100644 index 0000000000000..c1b51c7f83dc7 --- /dev/null +++ b/boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_reset.c @@ -0,0 +1,81 @@ +/**************************************************************************** + * boards/risc-v/esp32c6/esp32c6-devkitm/src/esp32c6_reset.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "espressif/esp_systemreset.h" + +#ifdef CONFIG_BOARDCTL_RESET + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value in this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ + syslog(LOG_INFO, "reboot status=%d\n", status); + + switch (status) + { + case EXIT_SUCCESS: + up_shutdown_handler(); + break; + case CONFIG_BOARD_ASSERT_RESET_VALUE: + default: + break; + } + + up_systemreset(); + + return 0; +} + +#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/risc-v/esp32h2/common/Kconfig b/boards/risc-v/esp32h2/common/Kconfig new file mode 100644 index 0000000000000..711e47f2d55bf --- /dev/null +++ b/boards/risc-v/esp32h2/common/Kconfig @@ -0,0 +1,50 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +config ESPRESSIF_MERGE_BINS + bool "Merge raw binary files into a single file" + default n + ---help--- + Merge the raw binary files into a single file for flashing to the + device. + This is only useful when the path to binary files (e.g. bootloader) + is provided via the ESPTOOL_BINDIR variable. + +choice ESPRESSIF_SPIFLASH_FS + prompt "Mount SPI Flash MTD on bring-up" + default ESPRESSIF_SPIFLASH_SMARTFS + depends on ESPRESSIF_MTD + optional + ---help--- + Mount the SPI Flash MTD with the selected File System format on board + bring-up. + If not selected, the MTD will be registered as a device node on /dev. + +config ESPRESSIF_SPIFLASH_SMARTFS + bool "SmartFS" + select FS_SMARTFS + select MTD_SMART + +config ESPRESSIF_SPIFLASH_NXFFS + bool "NXFFS" + select FS_NXFFS + +config ESPRESSIF_SPIFLASH_SPIFFS + bool "SPIFFS" + select FS_SPIFFS + +config ESPRESSIF_SPIFLASH_LITTLEFS + bool "LittleFS" + select FS_LITTLEFS + +config ESPRESSIF_SPIFLASH_MTD_CONFIG + bool "Non-volatile storage" + +endchoice # ESPRESSIF_SPIFLASH_FS + +config ESPRESSIF_SPIFLASH_FS_MOUNT_PT + string "File-system Mount Point" + depends on ESPRESSIF_SPIFLASH_LITTLEFS + default "/data" diff --git a/boards/risc-v/esp32h2/common/Makefile b/boards/risc-v/esp32h2/common/Makefile new file mode 100644 index 0000000000000..2d123bc64529f --- /dev/null +++ b/boards/risc-v/esp32h2/common/Makefile @@ -0,0 +1,33 @@ +############################################################################# +# boards/risc-v/esp32h2/common/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +include board/Make.defs +include src/Make.defs + +DEPPATH += --dep-path board +DEPPATH += --dep-path src + +include $(TOPDIR)/boards/Board.mk + +ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src +BOARDDIR = $(ARCHSRCDIR)$(DELIM)board +CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/risc-v/esp32h2/common/include/esp_board_ledc.h b/boards/risc-v/esp32h2/common/include/esp_board_ledc.h new file mode 100644 index 0000000000000..2737e3564d54f --- /dev/null +++ b/boards/risc-v/esp32h2/common/include/esp_board_ledc.h @@ -0,0 +1,74 @@ +/**************************************************************************** + * boards/risc-v/esp32h2/common/include/esp_board_ledc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32H2_COMMON_INCLUDE_ESP_BOARD_LEDC_H +#define __BOARDS_RISCV_ESP32H2_COMMON_INCLUDE_ESP_BOARD_LEDC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ledc_setup + * + * Description: + * Initialize LEDC PWM and register the PWM device. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_LEDC +int board_ledc_setup(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISCV_ESP32H2_COMMON_INCLUDE_ESP_BOARD_LEDC_H */ diff --git a/boards/risc-v/esp32h2/common/include/esp_board_rmt.h b/boards/risc-v/esp32h2/common/include/esp_board_rmt.h new file mode 100644 index 0000000000000..0e713aaee0fa3 --- /dev/null +++ b/boards/risc-v/esp32h2/common/include/esp_board_rmt.h @@ -0,0 +1,97 @@ +/**************************************************************************** + * boards/risc-v/esp32h2/common/include/esp_board_rmt.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISC_V_ESP32H2_COMMON_INCLUDE_ESP_BOARD_RMT_H +#define __BOARDS_RISC_V_ESP32H2_COMMON_INCLUDE_ESP_BOARD_RMT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_ESP_RMT + +/**************************************************************************** + * Name: board_rmt_rxinitialize + * + * Description: + * Initialize the RMT peripheral and register an RX device. + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the RX channel + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_rmt_rxinitialize(int ch, int pin); + +/**************************************************************************** + * Name: board_rmt_txinitialize + * + * Description: + * Initialize the RMT peripheral and register an TX device. + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the TX channel + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_rmt_txinitialize(int ch, int pin); + +#endif /* CONFIG_ESP_RMT */ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISC_V_ESP32H2_COMMON_INCLUDE_ESP_BOARD_RMT_H */ diff --git a/boards/risc-v/esp32h2/common/include/esp_board_spiflash.h b/boards/risc-v/esp32h2/common/include/esp_board_spiflash.h new file mode 100644 index 0000000000000..909eb2e2309d5 --- /dev/null +++ b/boards/risc-v/esp32h2/common/include/esp_board_spiflash.h @@ -0,0 +1,74 @@ +/**************************************************************************** + * boards/risc-v/esp32h2/common/include/esp_board_spiflash.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32H2_COMMON_INCLUDE_ESP_BOARD_SPIFLASH_H +#define __BOARDS_RISCV_ESP32H2_COMMON_INCLUDE_ESP_BOARD_SPIFLASH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_spiflash_init + * + * Description: + * Initialize the SPIFLASH and register the MTD device. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_SPIFLASH +int board_spiflash_init(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISCV_ESP32H2_COMMON_INCLUDE_ESP_BOARD_SPIFLASH_H */ diff --git a/boards/risc-v/esp32h2/common/scripts/.gitignore b/boards/risc-v/esp32h2/common/scripts/.gitignore new file mode 100644 index 0000000000000..0fa3d8108a58d --- /dev/null +++ b/boards/risc-v/esp32h2/common/scripts/.gitignore @@ -0,0 +1 @@ +/*.ld.tmp diff --git a/boards/risc-v/esp32h2/common/scripts/common.ld b/boards/risc-v/esp32h2/common/scripts/common.ld new file mode 100644 index 0000000000000..3265d61d8828d --- /dev/null +++ b/boards/risc-v/esp32h2/common/scripts/common.ld @@ -0,0 +1,35 @@ +/**************************************************************************** + * boards/risc-v/esp32h2/common/scripts/common.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ +#include + +#if CONFIG_ESPRESSIF_SOC_RTC_MEM_SUPPORTED +# define ESP_BOOTLOADER_RESERVE_RTC 0 + + /* rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files). + * For rtc_timer_data_in_rtc_mem section. + */ +# define RTC_TIMER_RESERVE_RTC (24) + +# ifdef CONFIG_ARCH_CHIP_ESP32 +# define RESERVE_RTC_MEM (RTC_TIMER_RESERVE_RTC) +# else +# define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC) +# endif /* CONFIG_ARCH_CHIP_ESP32 */ +#endif /* CONFIG_ESPRESSIF_SOC_RTC_MEM_SUPPORTED */ diff --git a/boards/risc-v/espressif/common/scripts/esp32h2_aliases.ld b/boards/risc-v/esp32h2/common/scripts/esp32h2_aliases.ld similarity index 85% rename from boards/risc-v/espressif/common/scripts/esp32h2_aliases.ld rename to boards/risc-v/esp32h2/common/scripts/esp32h2_aliases.ld index 89c145fbb1376..5019400aa8e42 100644 --- a/boards/risc-v/espressif/common/scripts/esp32h2_aliases.ld +++ b/boards/risc-v/esp32h2/common/scripts/esp32h2_aliases.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/espressif/common/scripts/esp32h2_aliases.ld + * boards/risc-v/esp32h2/common/scripts/esp32h2_aliases.ld * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,6 +18,10 @@ * ****************************************************************************/ +cache_resume_icache = Cache_Resume_ICache; +cache_suspend_icache = Cache_Suspend_ICache; +cache_invalidate_icache_all = Cache_Invalidate_ICache_All; + #ifdef CONFIG_ESPRESSIF_BLE /* Lower-case aliases for BLE library symbols not compliant to nxstyle */ diff --git a/boards/risc-v/espressif/common/scripts/esp32h2_flat_memory.ld b/boards/risc-v/esp32h2/common/scripts/esp32h2_flat_memory.ld similarity index 91% rename from boards/risc-v/espressif/common/scripts/esp32h2_flat_memory.ld rename to boards/risc-v/esp32h2/common/scripts/esp32h2_flat_memory.ld index 8d86c12da959f..809704f5d3537 100644 --- a/boards/risc-v/espressif/common/scripts/esp32h2_flat_memory.ld +++ b/boards/risc-v/esp32h2/common/scripts/esp32h2_flat_memory.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/espressif/common/scripts/esp32h2_flat_memory.ld + * boards/risc-v/esp32h2/common/scripts/esp32h2_flat_memory.ld * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -34,11 +34,9 @@ #define SRAM_IRAM_START 0x40800000 #define SRAM_DRAM_START 0x40800000 -#define I_D_SRAM_OFFSET (SRAM_IRAM_START - SRAM_DRAM_START) - /* 2nd stage bootloader iram_loader_seg start address */ -#define SRAM_DRAM_END (0x4083efd0 - I_D_SRAM_OFFSET) +#define SRAM_DRAM_END (0x4083efd0) #define SRAM_IRAM_ORG (SRAM_IRAM_START) #define SRAM_DRAM_ORG (SRAM_DRAM_START) @@ -54,6 +52,11 @@ MEMORY { +#ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT + ROM (R) : org = ORIGIN(ROM), + len = IDRAM0_2_SEG_SIZE +#endif + /* Below values assume the flash cache is on, and have the blocks this * uses subtracted from the length of the various regions. The 'data access * port' dram/drom regions map to the same iram/irom regions but are @@ -71,7 +74,7 @@ MEMORY * constraint that (paddr % 64KB == vaddr % 64KB). */ - irom_seg (RX) : org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20 + irom_seg (RX) : org = 0x42000000, len = IDRAM0_2_SEG_SIZE /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. * Enabling Bluetooth & Trace Memory features in menuconfig will decrease @@ -89,7 +92,7 @@ MEMORY * constraint that (paddr % 64KB == vaddr % 64KB). */ - drom_seg (R) : org = 0x42000020, len = IDRAM0_2_SEG_SIZE - 0x20 + drom_seg (R) : org = 0x42000000, len = IDRAM0_2_SEG_SIZE /* RTC fast memory (executable). Persists over deep sleep. */ @@ -106,7 +109,7 @@ MEMORY } /* The lines below define location alias for .rtc.data section - * ESP32-C6 has no distinguished LP(RTC) fast and slow memory sections, + * ESP32-H2 has no distinguished LP(RTC) fast and slow memory sections, * instead, there is a unified LP_RAM section. * Thus, the following region segments are not configurable like on other targets */ diff --git a/boards/risc-v/espressif/common/scripts/esp32h2_legacy_sections.ld b/boards/risc-v/esp32h2/common/scripts/esp32h2_legacy_sections.ld similarity index 97% rename from boards/risc-v/espressif/common/scripts/esp32h2_legacy_sections.ld rename to boards/risc-v/esp32h2/common/scripts/esp32h2_legacy_sections.ld index b40e93140808f..951ef2b75c41e 100644 --- a/boards/risc-v/espressif/common/scripts/esp32h2_legacy_sections.ld +++ b/boards/risc-v/esp32h2/common/scripts/esp32h2_legacy_sections.ld @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/espressif/common/scripts/esp32h2_legacy_sections.ld + * boards/risc-v/esp32h2/common/scripts/esp32h2_legacy_sections.ld * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -83,31 +83,6 @@ SECTIONS . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; } >dram0_0_seg - /* Shared RAM */ - - .dram0.bss (NOLOAD) : - { - . = ALIGN(8); - _sbss = ABSOLUTE(.); - *(.dynsbss) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.sb.*) - *(.scommon) - *(.sbss2) - *(.sbss2.*) - *(.gnu.linkonce.sb2.*) - *(.dynbss) - *(.bss) - *(.bss.*) - *(.share.mem) - *(.gnu.linkonce.b.*) - *(COMMON) - - . = ALIGN(8); - _ebss = ABSOLUTE(.); - } >dram0_0_seg - .noinit (NOLOAD): { /* This section contains data that is not initialized during load, @@ -153,10 +128,31 @@ SECTIONS *libsched.a:irq_dispatch.*(.rodata .rodata.*) . = ALIGN(4); _edata = ABSOLUTE(.); + } >dram0_0_seg - /* Heap starts at the end of .data */ + /* Shared RAM */ - _sheap = ABSOLUTE(.); + .dram0.bss (NOLOAD) : + { + . = ALIGN(8); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + + . = ALIGN(32); + _ebss = ABSOLUTE(.); } >dram0_0_seg .flash.text : diff --git a/boards/risc-v/esp32h2/common/scripts/esp32h2_simple_boot_sections.ld b/boards/risc-v/esp32h2/common/scripts/esp32h2_simple_boot_sections.ld new file mode 100644 index 0000000000000..51a41b20731e0 --- /dev/null +++ b/boards/risc-v/esp32h2/common/scripts/esp32h2_simple_boot_sections.ld @@ -0,0 +1,408 @@ +/**************************************************************************** + * boards/risc-v/esp32h2/common/scripts/esp32h2_simple_boot_sections.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Default entry point: */ + +ENTRY(__start); + +SECTIONS +{ + .iram0.text : + { + _iram_start = ABSOLUTE(.); + + /* Vectors go to start of IRAM */ + + KEEP(*(.exception_vectors.text)); + . = ALIGN(4); + + *(.iram1) + *(.iram1.*) + *libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*) + + *libarch.a:*brownout.*(.text .text.* .literal .literal.*) + *libarch.a:*cpu.*(.text .text.* .literal .literal.*) + *libarch.a:*gpio_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*periph_ctrl.*(.text .text.* .literal .literal.*) + *libarch.a:*clk.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk_tree.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk_tree_common.*(.text .text.* .literal .literal.*) + *libarch.a:*clk_tree_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*pmu_init.*(.text .text.* .literal .literal.*) + *libarch.a:*modem_clock.*(.text .text.* .literal .literal.*) + *libarch.a:*regi2c_ctrl.*(.text .text.* .literal .literal.*) + *libarch.a:*gpio_periph.*(.text .text.* .literal .literal.*) + *libarch.a:*modem_clock_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_systimer.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_wdt.*(.text .text.* .literal .literal.*) + *libarch.a:*ocode_init.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_regi2c_esp32h2.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_clk.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_clk_init.*(.text .text.* .literal .literal.*) + *libarch.a:*pmu_sleep.*(.text .text.* .literal .literal.*) + *libarch.a:*pmu_param.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_time.*(.text .text.* .literal .literal.*) + *libarch.a:*systimer.*(.text .text.* .literal .literal.*) + *libarch.a:*systimer_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_hal_iram.*(.text .text.* .literal .literal.*) + *libarch.a:*wdt_hal_iram.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_banner_wrap.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_init.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_common.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_common_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_console.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_console_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_esp32h2.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_flash.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_flash_config_esp32h2.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_clock_init.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_clock_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_efuse.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_panic.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_mem.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_random.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_random_esp32h2.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_image_format.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_soc.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_sha.*(.text .text.* .literal .literal.*) + *libarch.a:*flash_encrypt.*(.text .text.* .literal .literal.*) + *libarch.a:*cache_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_periph.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_uart.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_sys.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_spiflash.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_efuse_fields.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_efuse_api_key.*(.text .text.* .literal .literal.*) + *libarch.a:*efuse_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*log.*(.text .text.* .literal .literal.*) + *libarch.a:*log_noos.*(.text .text.* .literal .literal.*) + *libarch.a:esp_spiflash.*(.literal .text .literal.* .text.*) + + esp_head.*(.literal .text .literal.* .text.*) + esp_start.*(.literal .text .literal.* .text.*) + + } >iram0_0_seg AT > ROM + + /* Marks the end of IRAM code segment */ + + .iram0.text_end (NOLOAD) : + { + . = ALIGN (16); + } >iram0_0_seg + + .iram0.data : + { + . = ALIGN(16); + *(.iram.data) + *(.iram.data*) + } >iram0_0_seg + + .iram0.bss (NOLOAD) : + { + . = ALIGN(16); + *(.iram.bss) + *(.iram.bss*) + + . = ALIGN(16); + _iram_end = ABSOLUTE(.); + } >iram0_0_seg + + /* This section is required to skip .iram0.text area because iram0_0_seg + * and dram0_0_seg reflect the same address space on different buses. + */ + + .dram0.dummy (NOLOAD): + { + . = ORIGIN(dram0_0_seg) + _iram_end - _iram_start; + } >dram0_0_seg + + .noinit (NOLOAD): + { + /* This section contains data that is not initialized during load, + * or during the application's initialization sequence. + */ + + *(.noinit) + *(.noinit.*) + } >dram0_0_seg + + .dram0.data : + { + . = ALIGN (16); + _data_start = ABSOLUTE(.); + _sdata = ABSOLUTE(.); + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.data1) + __global_pointer$ = . + 0x800; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + *(.jcr) + *(.dram1) + *(.dram1.*) + *libsched.a:irq_dispatch.*(.rodata .rodata.*) + + *libarch.a:*brownout.*(.rodata .rodata.*) + *libarch.a:*cpu.*(.rodata .rodata.*) + *libarch.a:*gpio_hal.*(.rodata .rodata.*) + *libarch.a:*periph_ctrl.*(.rodata .rodata.*) + *libarch.a:*clk.*(.rodata .rodata.*) + *libarch.a:*esp_clk.*(.rodata .rodata.*) + *libarch.a:*esp_clk_tree.*(.rodata .rodata.*) + *libarch.a:*esp_clk_tree_common.*(.rodata .rodata.*) + *libarch.a:*clk_tree_hal.*(.rodata .rodata.*) + *libarch.a:*pmu_init.*(.rodata .rodata.*) + *libarch.a:*modem_clock.*(.rodata .rodata.*) + *libarch.a:*regi2c_ctrl.*(.rodata .rodata.*) + *libarch.a:*gpio_periph.*(.rodata .rodata.*) + *libarch.a:*modem_clock_hal.*(.rodata .rodata.*) + *libarch.a:*esp_rom_systimer.*(.rodata .rodata.*) + *libarch.a:*esp_rom_wdt.*(.rodata .rodata.*) + *libarch.a:*ocode_init.*(.rodata .rodata.*) + *libarch.a:*esp_rom_regi2c_esp32h2.*(.rodata .rodata.*) + *libarch.a:*rtc_clk.*(.rodata .rodata.*) + *libarch.a:*rtc_clk_init.*(.rodata .rodata.*) + *libarch.a:*pmu_param.*(.rodata .rodata.*) + *libarch.a:*pmu_sleep.*(.rodata .rodata.*) + *libarch.a:*rtc_time.*(.rodata .rodata.*) + *libarch.a:*systimer.*(.rodata .rodata.*) + *libarch.a:*systimer_hal.*(.rodata .rodata.*) + *libarch.a:*uart_hal_iram.*(.rodata .rodata.*) + *libarch.a:*wdt_hal_iram.*(.rodata .rodata.*) + *libarch.a:*bootloader_banner_wrap.*(.rodata .rodata.*) + *libarch.a:*bootloader_init.*(.rodata .rodata.*) + *libarch.a:*bootloader_common.*(.rodata .rodata.*) + *libarch.a:*bootloader_common_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_console.*(.rodata .rodata.*) + *libarch.a:*bootloader_console_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_esp32h2.*(.rodata .rodata.*) + *libarch.a:*bootloader_flash.*(.rodata .rodata.*) + *libarch.a:*bootloader_flash_config_esp32h2.*(.rodata .rodata.*) + *libarch.a:*bootloader_clock_init.*(.rodata .rodata.*) + *libarch.a:*bootloader_clock_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_efuse.*(.rodata .rodata.*) + *libarch.a:*bootloader_panic.*(.rodata .rodata.*) + *libarch.a:*bootloader_mem.*(.rodata .rodata.*) + *libarch.a:*bootloader_random.*(.rodata .rodata.*) + *libarch.a:*bootloader_random_esp32h2.*(.rodata .rodata.*) + *libarch.a:*esp_image_format.*(.rodata .rodata.*) + *libarch.a:*bootloader_soc.*(.rodata .rodata.*) + *libarch.a:*bootloader_sha.*(.rodata .rodata.*) + *libarch.a:*flash_encrypt.*(.rodata .rodata.*) + *libarch.a:*cache_hal.*(.rodata .rodata.*) + *libarch.a:*uart_hal.*(.rodata .rodata.*) + *libarch.a:*mpu_hal.*(.rodata .rodata.*) + *libarch.a:*mmu_hal.*(.rodata .rodata.*) + *libarch.a:*uart_periph.*(.rodata .rodata.*) + *libarch.a:*esp_rom_uart.*(.rodata .rodata.*) + *libarch.a:*esp_rom_sys.*(.rodata .rodata.*) + *libarch.a:*esp_rom_spiflash.*(.rodata .rodata.*) + *libarch.a:*esp_efuse_fields.*(.rodata .rodata.*) + *libarch.a:*esp_efuse_api_key.*(.rodata .rodata.*) + *libarch.a:*efuse_hal.*(.rodata .rodata.*) + *libarch.a:*log.*(.rodata .rodata.*) + *libarch.a:*log_noos.*(.rodata .rodata.*) + *libarch.a:esp_spiflash.*(.rodata .rodata.*) + + esp_head.*(.rodata .rodata.*) + esp_start.*(.rodata .rodata.*) + + . = ALIGN(4); + _edata = ABSOLUTE(.); + _data_end = ABSOLUTE(.); + } >dram0_0_seg AT > ROM + + /* Shared RAM */ + + .dram0.bss (NOLOAD) : + { + . = ALIGN (8); + _bss_start = ABSOLUTE(.); + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.bss) + *(.bss.*) + *(.share.mem) + *(.gnu.linkonce.b.*) + *(COMMON) + + . = ALIGN (32); + _ebss = ABSOLUTE(.); + _bss_end = ABSOLUTE(.); + } >dram0_0_seg + + _image_irom_vma = ADDR(.flash.text); + _image_irom_lma = LOADADDR(.flash.text); + _image_irom_size = SIZEOF(.flash.text); + + .flash.text_dummy (NOLOAD) : + { + . = ALIGN(0x10000); + } > ROM + + .flash.text : + { + _stext = .; + + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + _etext = .; + + /* Similar to _iram_start, this symbol goes here so it is + * resolved by addr2line in preference to the first symbol in + * the flash.text segment. + */ + + _flash_cache_start = ABSOLUTE(0); + } >default_code_seg AT > ROM + + .flash_rodata_dummy (NOLOAD) : + { + . += SIZEOF(.flash.text); + . = ALIGN(0x10000); + } >default_rodata_seg AT > ROM + + _image_drom_vma = ADDR(.flash.rodata); + _image_drom_lma = LOADADDR(.flash.rodata); + _image_drom_size = SIZEOF(.flash.rodata); + + .flash.rodata : + { + _srodata = ABSOLUTE(.); + + *(.rodata) + *(.rodata.*) + + *(.srodata.*) + + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table .gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + . = (. + 3) & ~ 3; + __eh_frame = ABSOLUTE(.); + KEEP(*(.eh_frame)) + . = (. + 7) & ~ 3; + + /* C++ constructor and destructor tables: + * RISC-V GCC is configured with --enable-initfini-array so it emits an + * .init_array section instead. + */ + + _sinit = ABSOLUTE(.); + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*)) + KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array)) + _einit = ABSOLUTE(.); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + + /* C++ exception handlers table: */ + + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _erodata = ABSOLUTE(.); + + /* Literals are also RO data. */ + + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + } >default_rodata_seg AT > ROM + + /* RTC fast memory holds RTC wake stub code !*/ + + .rtc.text : + { + . = ALIGN(4); + *(.rtc.literal .rtc.text) + } >rtc_iram_seg + + /* RTC BSS section. */ + + .rtc.bss (NOLOAD) : + { + *(.rtc.bss) + } >rtc_iram_seg + + /* RTC data section holds RTC wake stub data/rodata. */ + + .rtc.data : + { + *(.rtc.data) + *(.rtc.data.*) + *(.rtc.rodata) + *(.rtc.rodata.*) + } >rtc_iram_seg + + /* This section holds RTC data that should have fixed addresses. + * The data are not initialized at power-up and are retained during deep sleep. + */ + .rtc_reserved (NOLOAD): + { + . = ALIGN(4); + _rtc_reserved_start = ABSOLUTE(.); + /* New data can only be added here to ensure existing data are not moved. + Because data have adhered to the end of the segment and code is relied on it. + >> put new data here << */ + + *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) + KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*)) + _rtc_reserved_end = ABSOLUTE(.); + } > rtc_reserved_seg + + _rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start; + ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)), + "RTC reserved segment data does not fit.") + +} diff --git a/boards/risc-v/esp32h2/common/src/Make.defs b/boards/risc-v/esp32h2/common/src/Make.defs new file mode 100644 index 0000000000000..55f4960451aab --- /dev/null +++ b/boards/risc-v/esp32h2/common/src/Make.defs @@ -0,0 +1,43 @@ +############################################################################# +# boards/risc-v/esp32h2/common/src/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +ifeq ($(CONFIG_ARCH_BOARD_COMMON),y) + +ifeq ($(CONFIG_ESPRESSIF_LEDC),y) + CSRCS += esp_board_ledc.c +endif + +ifeq ($(CONFIG_ESP_RMT),y) + CSRCS += esp_board_rmt.c +endif + +ifeq ($(CONFIG_ESPRESSIF_SPIFLASH),y) + CSRCS += esp_board_spiflash.c +endif + +ifeq ($(CONFIG_ESPRESSIF_TWAI),y) + CSRCS += esp_board_twai.c +endif + +DEPPATH += --dep-path src +VPATH += :src +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src + +endif diff --git a/boards/risc-v/esp32h2/common/src/esp_board_ledc.c b/boards/risc-v/esp32h2/common/src/esp_board_ledc.c new file mode 100644 index 0000000000000..cfc95bfd7a696 --- /dev/null +++ b/boards/risc-v/esp32h2/common/src/esp_board_ledc.c @@ -0,0 +1,147 @@ +/**************************************************************************** + * boards/risc-v/esp32h2/common/src/esp_board_ledc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include + +#include "espressif/esp_ledc.h" + +#include "esp_board_ledc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define LEDC_TIMER0 0 +#define LEDC_TIMER1 1 +#define LEDC_TIMER2 2 +#define LEDC_TIMER3 3 + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_ledc_setup + * + * Description: + * Initialize LEDC PWM and register the PWM device. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int board_ledc_setup(void) +{ + int ret = OK; + struct pwm_lowerhalf_s *pwm; + +#ifdef CONFIG_ESPRESSIF_LEDC_TIMER0 + pwm = esp_ledc_init(LEDC_TIMER0); + if (!pwm) + { + syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 0 lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm0" */ + + ret = pwm_register("/dev/pwm0", pwm); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ESPRESSIF_LEDC_TIMER1 + pwm = esp_ledc_init(LEDC_TIMER1); + if (!pwm) + { + syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 1 lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm1" */ + + ret = pwm_register("/dev/pwm1", pwm); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ESPRESSIF_LEDC_TIMER2 + pwm = esp_ledc_init(LEDC_TIMER2); + if (!pwm) + { + syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 2 lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm2" */ + + ret = pwm_register("/dev/pwm2", pwm); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + +#ifdef CONFIG_ESPRESSIF_LEDC_TIMER3 + pwm = esp_ledc_init(LEDC_TIMER3); + if (!pwm) + { + syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 3 lower half\n"); + return -ENODEV; + } + + /* Register the PWM driver at "/dev/pwm3" */ + + ret = pwm_register("/dev/pwm3", pwm); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); + return ret; + } +#endif + + return ret; +} + diff --git a/boards/risc-v/esp32h2/common/src/esp_board_rmt.c b/boards/risc-v/esp32h2/common/src/esp_board_rmt.c new file mode 100644 index 0000000000000..2b7d2f9fb4f7a --- /dev/null +++ b/boards/risc-v/esp32h2/common/src/esp_board_rmt.c @@ -0,0 +1,150 @@ +/**************************************************************************** + * boards/risc-v/esp32h2/common/src/esp_board_rmt.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#ifdef CONFIG_WS2812_NON_SPI_DRIVER +#include + +#include "espressif/esp_ws2812.h" +#endif + +#include "espressif/esp_rmt.h" + +#ifdef CONFIG_ESP_RMT + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_rmt_rxinitialize + * + * Description: + * Initialize the RMT peripheral and register an RX device. + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the RX channel + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_rmt_rxinitialize(int ch, int pin) +{ + int ret; + + struct rmt_dev_s *rmt = esp_rmt_rx_init(ch, pin); + + ret = rmtchar_register(rmt); + if (ret < 0) + { + rmterr("ERROR: rmtchar_register failed: %d\n", ret); + return ret; + } + + return ret; +} + +/**************************************************************************** + * Name: board_rmt_txinitialize + * + * Description: + * Initialize the RMT peripheral and register an TX device. + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the TX channel + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_rmt_txinitialize(int ch, int pin) +{ + int ret; + struct rmt_dev_s *rmt; +#ifdef CONFIG_WS2812_NON_SPI_DRIVER + struct ws2812_dev_s *led; +#endif + + rmt = esp_rmt_tx_init(ch, pin); + if (rmt == NULL) + { + rmterr("ERROR: esp_rmt_tx_init failed\n"); + return -ENODEV; + } + + ret = rmtchar_register(rmt); + if (ret < 0) + { + rmterr("ERROR: rmtchar_register failed: %d\n", ret); + return ret; + } + +#ifdef CONFIG_WS2812_NON_SPI_DRIVER + led = esp_ws2812_setup("/dev/leds0", rmt, CONFIG_WS2812_LED_COUNT, false); + if (led == NULL) + { + rmterr("ERROR: esp_ws2812_setup failed\n"); + return -ENODEV; + } +#endif + + return ret; +} +#endif diff --git a/boards/risc-v/esp32h2/common/src/esp_board_spiflash.c b/boards/risc-v/esp32h2/common/src/esp_board_spiflash.c new file mode 100644 index 0000000000000..be7e840960f3d --- /dev/null +++ b/boards/risc-v/esp32h2/common/src/esp_board_spiflash.c @@ -0,0 +1,417 @@ +/**************************************************************************** + * boards/risc-v/esp32h2/common/src/esp_board_spiflash.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "inttypes.h" +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#ifdef CONFIG_BCH +#include +#endif + +#include "espressif/esp_spiflash.h" +#include "espressif/esp_spiflash_mtd.h" + +#include "esp_board_spiflash.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: setup_smartfs + * + * Description: + * Provide a block driver wrapper around MTD partition and mount a + * SMART FS over it. + * + * Parameters: + * smartn - Number used to register the mtd partition: /dev/smartx, where + * x = smartn. + * mtd - Pointer to a pre-allocated mtd partition. + * mnt_pt - Mount point + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +#if defined (CONFIG_ESPRESSIF_SPIFLASH_SMARTFS) +static int setup_smartfs(int smartn, struct mtd_dev_s *mtd, + const char *mnt_pt) +{ + int ret = OK; + char path[22]; + + ret = smart_initialize(smartn, mtd, NULL); + if (ret < 0) + { + syslog(LOG_INFO, "smart_initialize failed, " + "Trying to erase first...\n"); + ret = mtd->ioctl(mtd, MTDIOC_BULKERASE, 0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: ioctl(BULKERASE) failed: %d\n", ret); + return ret; + } + + syslog(LOG_INFO, "Erase successful, initializing it again.\n"); + ret = smart_initialize(smartn, mtd, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: smart_initialize failed: %d\n", ret); + return ret; + } + } + + if (mnt_pt != NULL) + { + snprintf(path, sizeof(path), "/dev/smart%d", smartn); + + ret = nx_mount(path, mnt_pt, "smartfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the FS volume: %d\n", ret); + if (ret == -ENODEV) + { + syslog(LOG_WARNING, "Smartfs seems unformatted. " + "Did you run 'mksmartfs /dev/smart%d'?\n", smartn); + } + + return ret; + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: setup_littlefs + * + * Description: + * Register a mtd driver and mount a Little FS over it. + * + * Parameters: + * path - Path name used to register the mtd driver. + * mtd - Pointer to a pre-allocated mtd partition. + * mnt_pt - Mount point + * priv - Privileges + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +#if defined (CONFIG_ESPRESSIF_SPIFLASH_LITTLEFS) +static int setup_littlefs(const char *path, struct mtd_dev_s *mtd, + const char *mnt_pt, int priv) +{ + int ret = OK; + + ret = register_mtddriver(path, mtd, priv, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); + return ERROR; + } + + if (mnt_pt != NULL) + { + ret = nx_mount(path, mnt_pt, "littlefs", 0, NULL); + if (ret < 0) + { + ret = nx_mount(path, mnt_pt, "littlefs", 0, "forceformat"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the FS volume: %d\n", + ret); + return ret; + } + } + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: setup_spiffs + * + * Description: + * Register a mtd driver and mount a SPIFFS over it. + * + * Parameters: + * path - Path name used to register the mtd driver. + * mtd - Pointer to a pre-allocated mtd partition. + * mnt_pt - Mount point + * priv - Privileges + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +#if defined (CONFIG_ESPRESSIF_SPIFLASH_SPIFFS) +static int setup_spiffs(const char *path, struct mtd_dev_s *mtd, + const char *mnt_pt, int priv) +{ + int ret = OK; + + ret = register_mtddriver(path, mtd, priv, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); + return ERROR; + } + + if (mnt_pt != NULL) + { + ret = nx_mount(path, mnt_pt, "spiffs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the FS volume: %d\n", ret); + return ret; + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: setup_nxffs + * + * Description: + * Register a mtd driver and mount a NXFFS over it. + * + * Parameters: + * mtd - Pointer to a pre-allocated mtd partition. + * mnt_pt - Mount point + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +#if defined (CONFIG_ESPRESSIF_SPIFLASH_NXFFS) +static int setup_nxffs(struct mtd_dev_s *mtd, const char *mnt_pt) +{ + int ret = OK; + + ret = nxffs_initialize(mtd); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: NXFFS init failed: %d\n", ret); + return ret; + } + + if (mnt_pt != NULL) + { + ret = nx_mount(NULL, mnt_pt, "nxffs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount the FS volume: %d\n", ret); + return ret; + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: init_storage_partition + * + * Description: + * Initialize partition that is dedicated to general use. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int init_storage_partition(void) +{ + int ret = OK; + struct mtd_dev_s *mtd; + + mtd = esp_spiflash_alloc_mtdpart(CONFIG_ESPRESSIF_STORAGE_MTD_OFFSET, + CONFIG_ESPRESSIF_STORAGE_MTD_SIZE); + if (!mtd) + { + syslog(LOG_ERR, "ERROR: Failed to alloc MTD partition of SPI Flash\n"); + return ERROR; + } + +#if defined (CONFIG_ESPRESSIF_SPIFLASH_SMARTFS) + + ret = setup_smartfs(0, mtd, "/data"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to setup smartfs\n"); + return ret; + } + +#elif defined (CONFIG_ESPRESSIF_SPIFLASH_NXFFS) + + ret = setup_nxffs(mtd, "/data"); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to setup nxffs\n"); + return ret; + } + +#elif defined (CONFIG_ESPRESSIF_SPIFLASH_LITTLEFS) + + const char *path = "/dev/espflash"; + ret = setup_littlefs(path, mtd, "/data", 0755); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to setup littlefs\n"); + return ret; + } + +#elif defined (CONFIG_ESPRESSIF_SPIFLASH_SPIFFS) + + const char *path = "/dev/espflash"; + ret = setup_spiffs(path, mtd, "/data", 0755); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to setup spiffs\n"); + return ret; + } + +#elif defined (CONFIG_ESPRESSIF_SPIFLASH_MTD_CONFIG) + +# if defined (CONFIG_TESTING_MTD_CONFIG_FAIL_SAFE) + + /* To test power-loss resilient kv system, + * we write possible power-loss flash layout into flash + * then start kv system to see if it recovers. + * To do so, we need a mtd driver so that test code can + * write into flash. + */ + + const char *path = CONFIG_TESTING_MTD_CONFIG_FAIL_SAFE_MOUNTPT_NAME; + ret = register_mtddriver(path, mtd, 0777, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); + return ret; + } + +# else + + ret = mtdconfig_register(mtd); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to setup mtd config\n"); + return ret; + } + +# endif + +#else + + ret = register_mtddriver("/dev/espflash", mtd, 0755, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to register MTD: %d\n", ret); + return ret; + } + +#endif + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_spiflash_init + * + * Description: + * Initialize the SPI Flash and register the MTD device. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int board_spiflash_init(void) +{ + int ret = OK; + + esp_spiflash_init(); + + ret = init_storage_partition(); + if (ret < 0) + { + return ret; + } + + return ret; +} + diff --git a/boards/risc-v/esp32h2/common/src/esp_board_twai.c b/boards/risc-v/esp32h2/common/src/esp_board_twai.c new file mode 100644 index 0000000000000..4db11128c891c --- /dev/null +++ b/boards/risc-v/esp32h2/common/src/esp_board_twai.c @@ -0,0 +1,94 @@ +/**************************************************************************** + * boards/risc-v/esp32h2/common/src/esp_board_twai.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "espressif/esp_twai.h" + +#ifdef CONFIG_CAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define TWAI_PORT 0 + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_twai_setup + * + * Description: + * Initialize TWAI and register the TWAI device + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int board_twai_setup(void) +{ +#ifdef CONFIG_ESPRESSIF_TWAI + struct can_dev_s *twai; + int ret; + + /* Call esp_twaiinitialize() to get an instance of the TWAI + * interface + * */ + + twai = esp_twaiinitialize(TWAI_PORT); + if (twai == NULL) + { + canerr("ERROR: Failed to get TWAI interface\n"); + return -ENODEV; + } + + /* Register the TWAI driver at "/dev/can0" */ + + ret = can_register("/dev/can0", twai); + if (ret < 0) + { + canerr("ERROR: TWAI0 register failed: %d\n", ret); + return ret; + } + + return OK; +#else + return -ENODEV; +#endif +} + +#endif /* CONFIG_CAN */ diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/Kconfig b/boards/risc-v/esp32h2/esp32h2-devkit/Kconfig new file mode 100644 index 0000000000000..dfb818e6ab1bd --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_ESP32H2_DEVKIT + +endif # ARCH_BOARD_ESP32H2_DEVKIT diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/buttons/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/buttons/defconfig new file mode 100644 index 0000000000000..4662baad2154a --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/buttons/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32h2-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_CHIP="esp32h2" +CONFIG_ARCH_CHIP_ESP32H2=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32H2=y +CONFIG_ESPRESSIF_GPIO_IRQ=y +CONFIG_EXAMPLES_BUTTONS=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INPUT=y +CONFIG_INPUT_BUTTONS=y +CONFIG_INPUT_BUTTONS_LOWER=y +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/gpio/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/gpio/defconfig new file mode 100644 index 0000000000000..4c4a8801249f9 --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/gpio/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32h2-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y +CONFIG_ARCH_CHIP="esp32h2" +CONFIG_ARCH_CHIP_ESP32H2=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_GPIO=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32H2=y +CONFIG_ESPRESSIF_GPIO_IRQ=y +CONFIG_EXAMPLES_GPIO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/nsh/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/nsh/defconfig new file mode 100644 index 0000000000000..3e02bebfd2804 --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/nsh/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32h2-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y +CONFIG_ARCH_CHIP="esp32h2" +CONFIG_ARCH_CHIP_ESP32H2=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32H2=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/ostest/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/ostest/defconfig new file mode 100644 index 0000000000000..00ecbd4707e59 --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/ostest/defconfig @@ -0,0 +1,46 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32h2-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y +CONFIG_ARCH_CHIP="esp32h2" +CONFIG_ARCH_CHIP_ESP32H2=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32H2=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/pwm/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/pwm/defconfig new file mode 100644 index 0000000000000..1ccb576da7858 --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/pwm/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32h2-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y +CONFIG_ARCH_CHIP="esp32h2" +CONFIG_ARCH_CHIP_ESP32H2=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32H2=y +CONFIG_ESPRESSIF_LEDC=y +CONFIG_ESPRESSIF_LEDC_TIMER0=y +CONFIG_EXAMPLES_PWM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/random/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/random/defconfig new file mode 100644 index 0000000000000..e8e53d015d1a4 --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/random/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32h2-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y +CONFIG_ARCH_CHIP="esp32h2" +CONFIG_ARCH_CHIP_ESP32H2=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_URANDOM=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32H2=y +CONFIG_EXAMPLES_RANDOM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2023 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/rmt/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/rmt/defconfig new file mode 100644 index 0000000000000..a4ef3497e0d2f --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/rmt/defconfig @@ -0,0 +1,59 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32h2-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y +CONFIG_ARCH_CHIP="esp32h2" +CONFIG_ARCH_CHIP_ESP32H2=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32H2=y +CONFIG_ESP_RMT=y +CONFIG_EXAMPLES_RMTCHAR=y +CONFIG_EXAMPLES_RMTCHAR_RX=y +CONFIG_EXAMPLES_RMTCHAR_RX_DEVPATH="/dev/rmt2" +CONFIG_EXAMPLES_RMTCHAR_TX=y +CONFIG_EXAMPLES_WS2812=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RMT=y +CONFIG_RMTCHAR=y +CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE=512 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WS2812=y +CONFIG_WS2812_LED_COUNT=100 +CONFIG_WS2812_NON_SPI_DRIVER=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/rtc/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/rtc/defconfig new file mode 100644 index 0000000000000..286e3b26df8f6 --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/rtc/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32h2-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y +CONFIG_ARCH_CHIP="esp32h2" +CONFIG_ARCH_CHIP_ESP32H2=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32H2=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_DATE=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_ALARM=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=4 +CONFIG_START_YEAR=2023 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/spiflash/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/spiflash/defconfig new file mode 100644 index 0000000000000..92491e5a3c229 --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/spiflash/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32h2-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y +CONFIG_ARCH_CHIP="esp32h2" +CONFIG_ARCH_CHIP_ESP32H2=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32H2=y +CONFIG_ESPRESSIF_SPIFLASH=y +CONFIG_ESPRESSIF_SPIFLASH_SMARTFS=y +CONFIG_ESPRESSIF_STORAGE_MTD_OFFSET=0x110000 +CONFIG_ESPRESSIF_STORAGE_MTD_SIZE=0xf0000 +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NAME_MAX=48 +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_LOSMART=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_SMARTFS_MAXNAMLEN=48 +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_FLASH_ERASEALL=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_FSTEST=y +CONFIG_TESTING_FSTEST_MOUNTPT="/mnt" +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/tickless/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/tickless/defconfig new file mode 100644 index 0000000000000..cfdffb2111fac --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/tickless/defconfig @@ -0,0 +1,48 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32h2-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y +CONFIG_ARCH_CHIP="esp32h2" +CONFIG_ARCH_CHIP_ESP32H2=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32H2=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_TICKLESS=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_USEC_PER_TICK=10000 diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/timers/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/timers/defconfig new file mode 100644 index 0000000000000..2d8a356248a1c --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/timers/defconfig @@ -0,0 +1,50 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32h2-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y +CONFIG_ARCH_CHIP="esp32h2" +CONFIG_ARCH_CHIP_ESP32H2=y +CONFIG_ARCH_INTERRUPTSTACK=1536 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32H2=y +CONFIG_EXAMPLES_ONESHOT=y +CONFIG_EXAMPLES_TIMER=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_ONESHOT=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=28 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2023 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_TIMER=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/twai/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/twai/defconfig new file mode 100644 index 0000000000000..97af35aa5f535 --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/twai/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32h2-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y +CONFIG_ARCH_CHIP="esp32h2" +CONFIG_ARCH_CHIP_ESP32H2=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32H2=y +CONFIG_ESPRESSIF_TWAI0=y +CONFIG_EXAMPLES_CAN=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/usbconsole/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/usbconsole/defconfig new file mode 100644 index 0000000000000..a000704805cad --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/usbconsole/defconfig @@ -0,0 +1,47 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ESPRESSIF_UART0 is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32h2-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y +CONFIG_ARCH_CHIP="esp32h2" +CONFIG_ARCH_CHIP_ESP32H2=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_RESET=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32H2=y +CONFIG_ESPRESSIF_USBSERIAL=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/watchdog/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/watchdog/defconfig new file mode 100644 index 0000000000000..f11fc17c171b4 --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/watchdog/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="esp32h2-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32H2_DEVKIT=y +CONFIG_ARCH_CHIP="esp32h2" +CONFIG_ARCH_CHIP_ESP32H2=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=15000 +CONFIG_BUILTIN=y +CONFIG_DEV_ZERO=y +CONFIG_ESPRESSIF_ESP32H2=y +CONFIG_ESPRESSIF_MWDT0=y +CONFIG_ESPRESSIF_MWDT1=y +CONFIG_EXAMPLES_WATCHDOG=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NSH_STRERROR=y +CONFIG_PREALLOC_TIMERS=0 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=29 +CONFIG_START_MONTH=11 +CONFIG_START_YEAR=2019 +CONFIG_SYSTEM_DUMPSTACK=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/include/board.h b/boards/risc-v/esp32h2/esp32h2-devkit/include/board.h new file mode 100644 index 0000000000000..40d78d3ce91f6 --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/include/board.h @@ -0,0 +1,40 @@ +/**************************************************************************** + * boards/risc-v/esp32h2/esp32h2-devkit/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32H2_ESP32H2_DEVKIT_INCLUDE_BOARD_H +#define __BOARDS_RISCV_ESP32H2_ESP32H2_DEVKIT_INCLUDE_BOARD_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* GPIO pins used by the GPIO Subsystem */ + +#define BOARD_NGPIOOUT 2 /* Amount of GPIO Output pins */ +#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ + +/* ESP32H2-Generic GPIOs ****************************************************/ + +/* BOOT Button */ + +#define BUTTON_BOOT 9 + +#endif /* __BOARDS_RISCV_ESP32H2_ESP32H2_DEVKIT_INCLUDE_BOARD_H */ + diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/scripts/Make.defs b/boards/risc-v/esp32h2/esp32h2-devkit/scripts/Make.defs new file mode 100644 index 0000000000000..eb5773bfae86c --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/scripts/Make.defs @@ -0,0 +1,65 @@ +############################################################################ +# boards/risc-v/esp32h2/esp32h2-devkit/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +########################################################################### + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/tools/espressif/Config.mk +include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs + +# Remove quotes from CONFIG_ESPRESSIF_CHIP_SERIES configuration + +CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES)) + +# Pick the linker scripts from the board level if they exist, if not +# pick the common linker scripts. + +ARCHSCRIPT += $(BOARD_COMMON_DIR)/scripts/$(CHIP_SERIES)_aliases.ld + +ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_flat_memory.ld) + +ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_simple_boot_sections.ld) +else + ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_legacy_sections.ld) +endif + +ARCHPICFLAGS = -fpic + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -Werror=return-type -Werror +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +# Loadable module definitions + +CMODULEFLAGS = $(CFLAGS) + +LDMODULEFLAGS = -melf32lriscv -r -e module_initialize +LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld) + +# ELF module definitions + +CELFFLAGS = $(CFLAGS) +CXXELFFLAGS = $(CXXFLAGS) + +LDELFFLAGS = -melf32lriscv -r -e main +LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/binfmt/libelf/gnu-elf.ld) diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/src/Make.defs b/boards/risc-v/esp32h2/esp32h2-devkit/src/Make.defs new file mode 100644 index 0000000000000..66102c2e47a83 --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/src/Make.defs @@ -0,0 +1,43 @@ +############################################################################# +# boards/risc-v/esp32h2/esp32h2-devkit/src/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################# + +include $(TOPDIR)/Make.defs + +CSRCS = esp32h2_boot.c esp32h2_bringup.c + +ifeq ($(CONFIG_BOARDCTL),y) + CSRCS += esp32h2_appinit.c + + ifeq ($(CONFIG_BOARDCTL_RESET),y) + CSRCS += esp32h2_reset.c + endif +endif + +ifeq ($(CONFIG_DEV_GPIO),y) + CSRCS += esp32h2_gpio.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) + CSRCS += esp32h2_buttons.c +endif + +DEPPATH += --dep-path board +VPATH += :board +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2-devkit.h b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2-devkit.h new file mode 100644 index 0000000000000..be5bef72f63ec --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2-devkit.h @@ -0,0 +1,119 @@ +/**************************************************************************** + * boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2-devkit.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_ESP32H2_ESP32H2_DEVKIT_SRC_ESP32H2_DEVKIT_H +#define __BOARDS_RISCV_ESP32H2_ESP32H2_DEVKIT_SRC_ESP32H2_DEVKIT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* RMT gpio */ + +#define RMT_RXCHANNEL 2 +#define RMT_TXCHANNEL 0 + +#ifdef CONFIG_RMT_LOOP_TEST_MODE +# define RMT_INPUT_PIN 0 +# define RMT_OUTPUT_PIN 0 +#else +# define RMT_INPUT_PIN 2 +# define RMT_OUTPUT_PIN 8 +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_bringup + * + * Description: + * Perform architecture-specific initialization. + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y : + * Called from the NSH library via board_app_initialize(). + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int esp_bringup(void); + +/**************************************************************************** + * Name: board_twai_setup + * + * Description: + * Initialize TWAI and register the TWAI device + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_TWAI +int board_twai_setup(void); +#endif + +/**************************************************************************** + * Name: esp_gpio_init + * + * Description: + * Configure the GPIO driver. + * + * Returned Value: + * Zero (OK). + * + ****************************************************************************/ + +#ifdef CONFIG_DEV_GPIO +int esp_gpio_init(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISCV_ESP32H2_ESP32H2_DEVKIT_SRC_ESP32H2_DEVKIT_H */ diff --git a/boards/risc-v/espressif/esp32h2-generic/src/esp32h2_appinit.c b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_appinit.c similarity index 97% rename from boards/risc-v/espressif/esp32h2-generic/src/esp32h2_appinit.c rename to boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_appinit.c index 2070289f5d45a..e900efecdbd2c 100644 --- a/boards/risc-v/espressif/esp32h2-generic/src/esp32h2_appinit.c +++ b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_appinit.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/espressif/esp32h2-generic/src/esp32h2_appinit.c + * boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_appinit.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -28,7 +28,7 @@ #include -#include "esp32h2-generic.h" +#include "esp32h2-devkit.h" #ifdef CONFIG_BOARDCTL diff --git a/boards/risc-v/espressif/esp32h2-generic/src/esp32h2_boot.c b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_boot.c similarity index 98% rename from boards/risc-v/espressif/esp32h2-generic/src/esp32h2_boot.c rename to boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_boot.c index 76594281e591a..fa1c5bae28216 100644 --- a/boards/risc-v/espressif/esp32h2-generic/src/esp32h2_boot.c +++ b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_boot.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/espressif/esp32h2-generic/src/esp32h2_boot.c + * boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_boot.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_bringup.c b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_bringup.c new file mode 100644 index 0000000000000..481d6d1340eba --- /dev/null +++ b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_bringup.c @@ -0,0 +1,246 @@ +/**************************************************************************** + * boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "esp_board_ledc.h" +#include "esp_board_spiflash.h" + +#ifdef CONFIG_WATCHDOG +# include "espressif/esp_wdt.h" +#endif + +#ifdef CONFIG_TIMER +# include "espressif/esp_timer.h" +#endif + +#ifdef CONFIG_ONESHOT +# include "espressif/esp_oneshot.h" +#endif + +#ifdef CONFIG_RTC_DRIVER +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_DEV_GPIO +# include "espressif/esp_gpio.h" +#endif + +#ifdef CONFIG_INPUT_BUTTONS +# include +#endif + +#ifdef CONFIG_ESP_RMT +# include "esp_board_rmt.h" +#endif + +#include "esp32h2-devkit.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_bringup + * + * Description: + * Perform architecture-specific initialization. + * + * CONFIG_BOARD_LATE_INITIALIZE=y : + * Called from board_late_initialize(). + * + * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y : + * Called from the NSH library via board_app_initialize(). + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +int esp_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + _err("Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_TMPFS + /* Mount the tmpfs file system */ + + ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); + if (ret < 0) + { + _err("Failed to mount tmpfs at %s: %d\n", CONFIG_LIBC_TMPDIR, ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_MWDT0 + ret = esp_wdt_initialize("/dev/watchdog0", ESP_WDT_MWDT0); + if (ret < 0) + { + _err("Failed to initialize WDT: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_MWDT1 + ret = esp_wdt_initialize("/dev/watchdog1", ESP_WDT_MWDT1); + if (ret < 0) + { + _err("Failed to initialize WDT: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_RWDT + ret = esp_wdt_initialize("/dev/watchdog2", ESP_WDT_RWDT); + if (ret < 0) + { + _err("Failed to initialize WDT: %d\n", ret); + } +#endif + +#ifdef CONFIG_TIMER + ret = esp_timer_initialize(0); + if (ret < 0) + { + _err("Failed to initialize Timer 0: %d\n", ret); + } + +#ifndef CONFIG_ONESHOT + ret = esp_timer_initialize(1); + if (ret < 0) + { + _err("Failed to initialize Timer 1: %d\n", ret); + } +#endif +#endif + +#ifdef CONFIG_ONESHOT + ret = esp_oneshot_initialize(); + if (ret < 0) + { + _err("Failed to initialize Oneshot Timer: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESP_RMT + ret = board_rmt_txinitialize(RMT_TXCHANNEL, RMT_OUTPUT_PIN); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); + } + + ret = board_rmt_rxinitialize(RMT_RXCHANNEL, RMT_INPUT_PIN); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_RTC_DRIVER + /* Initialize the RTC driver */ + + ret = esp_rtc_driverinit(); + if (ret < 0) + { + _err("Failed to initialize the RTC driver: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_SPIFLASH + ret = board_spiflash_init(); + if (ret) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SPI Flash\n"); + } +#endif + +#ifdef CONFIG_ESPRESSIF_TWAI + + /* Initialize TWAI and register the TWAI driver. */ + + ret = board_twai_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_twai_setup failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_DEV_GPIO + ret = esp_gpio_init(); + if (ret < 0) + { + ierr("Failed to initialize GPIO Driver: %d\n", ret); + } +#endif + +#if defined(CONFIG_INPUT_BUTTONS) && defined(CONFIG_INPUT_BUTTONS_LOWER) + /* Register the BUTTON driver */ + + ret = btn_lower_initialize("/dev/buttons"); + if (ret < 0) + { + ierr("ERROR: btn_lower_initialize() failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESPRESSIF_LEDC + ret = board_ledc_setup(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_ledc_setup() failed: %d\n", ret); + } +#endif /* CONFIG_ESPRESSIF_LEDC */ + + /* If we got here then perhaps not all initialization was successful, but + * at least enough succeeded to bring-up NSH with perhaps reduced + * capabilities. + */ + + return ret; +} diff --git a/boards/risc-v/espressif/esp32h2-generic/src/esp32h2_buttons.c b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_buttons.c similarity index 97% rename from boards/risc-v/espressif/esp32h2-generic/src/esp32h2_buttons.c rename to boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_buttons.c index 6000365e80a89..78f0ebae0e7a4 100644 --- a/boards/risc-v/espressif/esp32h2-generic/src/esp32h2_buttons.c +++ b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_buttons.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/espressif/esp32h2-generic/src/esp32h2_buttons.c + * boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_buttons.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -43,11 +43,11 @@ /* Arch */ -#include "esp_gpio.h" +#include "espressif/esp_gpio.h" /* Board */ -#include "esp32h2-generic.h" +#include "esp32h2-devkit.h" #include /**************************************************************************** diff --git a/boards/risc-v/espressif/esp32h2-generic/src/esp32h2_gpio.c b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_gpio.c similarity index 99% rename from boards/risc-v/espressif/esp32h2-generic/src/esp32h2_gpio.c rename to boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_gpio.c index a863491408437..17cf6091cbdf4 100644 --- a/boards/risc-v/espressif/esp32h2-generic/src/esp32h2_gpio.c +++ b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_gpio.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/espressif/esp32h2-generic/src/esp32h2_gpio.c + * boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_gpio.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -41,11 +41,11 @@ /* Arch */ -#include "esp_gpio.h" +#include "espressif/esp_gpio.h" /* Board */ -#include "esp32h2-generic.h" +#include "esp32h2-devkit.h" #include /* HAL */ diff --git a/boards/risc-v/espressif/esp32h2-generic/src/esp32h2_reset.c b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_reset.c similarity index 96% rename from boards/risc-v/espressif/esp32h2-generic/src/esp32h2_reset.c rename to boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_reset.c index b01e3de2d2f8e..77118e5d2e14a 100644 --- a/boards/risc-v/espressif/esp32h2-generic/src/esp32h2_reset.c +++ b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_reset.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/espressif/esp32h2-generic/src/esp32h2_reset.c + * boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_reset.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -31,7 +31,7 @@ #include #include -#include "esp_systemreset.h" +#include "espressif/esp_systemreset.h" #ifdef CONFIG_BOARDCTL_RESET diff --git a/boards/risc-v/espressif/common/Kconfig b/boards/risc-v/espressif/common/Kconfig deleted file mode 100644 index f2a26a919ccbe..0000000000000 --- a/boards/risc-v/espressif/common/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -config ESPRESSIF_MERGE_BINS - bool "Merge raw binary files into a single file" - default n - ---help--- - Merge the raw binary files into a single file for flashing to the - device. - This is only useful when the path to binary files (e.g. bootloader) - is provided via the ESPTOOL_BINDIR variable. diff --git a/boards/risc-v/espressif/common/Makefile b/boards/risc-v/espressif/common/Makefile deleted file mode 100644 index 546b3a62b48ca..0000000000000 --- a/boards/risc-v/espressif/common/Makefile +++ /dev/null @@ -1,33 +0,0 @@ -############################################################################# -# boards/risc-v/espressif/common/Makefile -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################# - -include $(TOPDIR)/Make.defs - -include board/Make.defs -include src/Make.defs - -DEPPATH += --dep-path board -DEPPATH += --dep-path src - -include $(TOPDIR)/boards/Board.mk - -ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src -BOARDDIR = $(ARCHSRCDIR)$(DELIM)board -CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include diff --git a/boards/risc-v/espressif/common/include/esp_board_ledc.h b/boards/risc-v/espressif/common/include/esp_board_ledc.h deleted file mode 100644 index df6bc291a0810..0000000000000 --- a/boards/risc-v/espressif/common/include/esp_board_ledc.h +++ /dev/null @@ -1,74 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/common/include/esp_board_ledc.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_RISCV_ESPRESSIF_COMMON_INCLUDE_ESP_BOARD_LEDC_H -#define __BOARDS_RISCV_ESPRESSIF_COMMON_INCLUDE_ESP_BOARD_LEDC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: board_ledc_setup - * - * Description: - * Initialize LEDC PWM and register the PWM device. - * - * Input Parameters: - * None. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_ESPRESSIF_LEDC -int board_ledc_setup(void); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_RISCV_ESPRESSIF_COMMON_INCLUDE_ESP_BOARD_LEDC_H */ diff --git a/boards/risc-v/espressif/common/scripts/common.ld b/boards/risc-v/espressif/common/scripts/common.ld deleted file mode 100644 index 2f93e1b7957fa..0000000000000 --- a/boards/risc-v/espressif/common/scripts/common.ld +++ /dev/null @@ -1,35 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/common/scripts/common.ld - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ -#include - -#if CONFIG_ESPRESSIF_SOC_RTC_MEM_SUPPORTED -# define ESP_BOOTLOADER_RESERVE_RTC 0 - - /* rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files). - * For rtc_timer_data_in_rtc_mem section. - */ -# define RTC_TIMER_RESERVE_RTC (24) - -# ifdef CONFIG_ARCH_CHIP_ESP32 -# define RESERVE_RTC_MEM (RTC_TIMER_RESERVE_RTC) -# else -# define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC) -# endif /* CONFIG_ARCH_CHIP_ESP32 */ -#endif /* CONFIG_ESPRESSIF_SOC_RTC_MEM_SUPPORTED */ diff --git a/boards/risc-v/espressif/common/src/Make.defs b/boards/risc-v/espressif/common/src/Make.defs deleted file mode 100644 index fff6e89461ff0..0000000000000 --- a/boards/risc-v/espressif/common/src/Make.defs +++ /dev/null @@ -1,31 +0,0 @@ -############################################################################# -# boards/risc-v/espressif/common/src/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################# - -ifeq ($(CONFIG_ARCH_BOARD_COMMON),y) - -ifeq ($(CONFIG_ESPRESSIF_LEDC),y) - CSRCS += esp_board_ledc.c -endif - -DEPPATH += --dep-path src -VPATH += :src -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)src - -endif diff --git a/boards/risc-v/espressif/common/src/esp_board_ledc.c b/boards/risc-v/espressif/common/src/esp_board_ledc.c deleted file mode 100644 index 4c6033abf8436..0000000000000 --- a/boards/risc-v/espressif/common/src/esp_board_ledc.c +++ /dev/null @@ -1,147 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/common/src/esp_board_ledc.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include - -#include "esp_ledc.h" - -#include "esp_board_ledc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define LEDC_TIMER0 0 -#define LEDC_TIMER1 1 -#define LEDC_TIMER2 2 -#define LEDC_TIMER3 3 - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_ledc_setup - * - * Description: - * Initialize LEDC PWM and register the PWM device. - * - * Input Parameters: - * None. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int board_ledc_setup(void) -{ - int ret = OK; - struct pwm_lowerhalf_s *pwm; - -#ifdef CONFIG_ESPRESSIF_LEDC_TIMER0 - pwm = esp_ledc_init(LEDC_TIMER0); - if (!pwm) - { - syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 0 lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm0" */ - - ret = pwm_register("/dev/pwm0", pwm); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_ESPRESSIF_LEDC_TIMER1 - pwm = esp_ledc_init(LEDC_TIMER1); - if (!pwm) - { - syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 1 lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm1" */ - - ret = pwm_register("/dev/pwm1", pwm); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_ESPRESSIF_LEDC_TIMER2 - pwm = esp_ledc_init(LEDC_TIMER2); - if (!pwm) - { - syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 2 lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm2" */ - - ret = pwm_register("/dev/pwm2", pwm); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - -#ifdef CONFIG_ESPRESSIF_LEDC_TIMER3 - pwm = esp_ledc_init(LEDC_TIMER3); - if (!pwm) - { - syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 3 lower half\n"); - return -ENODEV; - } - - /* Register the PWM driver at "/dev/pwm3" */ - - ret = pwm_register("/dev/pwm3", pwm); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret); - return ret; - } -#endif - - return ret; -} - diff --git a/boards/risc-v/espressif/esp32c3-generic/configs/buttons/defconfig b/boards/risc-v/espressif/esp32c3-generic/configs/buttons/defconfig deleted file mode 100644 index 1c3fe6d497930..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/configs/buttons/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_GPIO_IRQ=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32c3-generic/configs/gpio/defconfig b/boards/risc-v/espressif/esp32c3-generic/configs/gpio/defconfig deleted file mode 100644 index f76919c44a97c..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/configs/gpio/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_GPIO=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_GPIO_IRQ=y -CONFIG_EXAMPLES_GPIO=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32c3-generic/configs/mcuboot_nsh/defconfig b/boards/risc-v/espressif/esp32c3-generic/configs/mcuboot_nsh/defconfig deleted file mode 100644 index e9e52805b137d..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/configs/mcuboot_nsh/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32c3-generic/configs/nsh/defconfig b/boards/risc-v/espressif/esp32c3-generic/configs/nsh/defconfig deleted file mode 100644 index e5ae74000f1f4..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/configs/nsh/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32c3-generic/configs/pwm/defconfig b/boards/risc-v/espressif/esp32c3-generic/configs/pwm/defconfig deleted file mode 100644 index 382635d7d1253..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/configs/pwm/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_LEDC=y -CONFIG_ESPRESSIF_LEDC_TIMER0=y -CONFIG_EXAMPLES_PWM=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32c3-generic/configs/random/defconfig b/boards/risc-v/espressif/esp32c3-generic/configs/random/defconfig deleted file mode 100644 index 6e7aa75dbd6c3..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/configs/random/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_URANDOM=y -CONFIG_DEV_ZERO=y -CONFIG_EXAMPLES_RANDOM=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=3 -CONFIG_START_YEAR=2023 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32c3-generic/configs/rtc/defconfig b/boards/risc-v/espressif/esp32c3-generic/configs/rtc/defconfig deleted file mode 100644 index dfed670b9d610..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/configs/rtc/defconfig +++ /dev/null @@ -1,51 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_EXAMPLES_ALARM=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_DATE=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC=y -CONFIG_RTC_ALARM=y -CONFIG_RTC_DRIVER=y -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=4 -CONFIG_START_YEAR=2023 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32c3-generic/configs/tickless/defconfig b/boards/risc-v/espressif/esp32c3-generic/configs/tickless/defconfig deleted file mode 100644 index 4ccae308888f4..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/configs/tickless/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_TICKLESS=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_USEC_PER_TICK=10000 diff --git a/boards/risc-v/espressif/esp32c3-generic/configs/timers/defconfig b/boards/risc-v/espressif/esp32c3-generic/configs/timers/defconfig deleted file mode 100644 index 221498a024ed9..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/configs/timers/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_EXAMPLES_ONESHOT=y -CONFIG_EXAMPLES_TIMER=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_ONESHOT=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=28 -CONFIG_START_MONTH=3 -CONFIG_START_YEAR=2023 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_TIMER=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32c3-generic/configs/usbconsole/defconfig b/boards/risc-v/espressif/esp32c3-generic/configs/usbconsole/defconfig deleted file mode 100644 index 6a58081690bb5..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/configs/usbconsole/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ESPRESSIF_UART0 is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_USBSERIAL=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y diff --git a/boards/risc-v/espressif/esp32c3-generic/configs/watchdog/defconfig b/boards/risc-v/espressif/esp32c3-generic/configs/watchdog/defconfig deleted file mode 100644 index b6982e992306a..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/configs/watchdog/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c3-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C3_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_EXAMPLES_WATCHDOG=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_WATCHDOG=y diff --git a/boards/risc-v/espressif/esp32c3-generic/include/board.h b/boards/risc-v/espressif/esp32c3-generic/include/board.h deleted file mode 100644 index 2d2b63f7993ee..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/include/board.h +++ /dev/null @@ -1,40 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/esp32c3-generic/include/board.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_RISCV_ESPRESSIF_ESP32C3_GENERIC_INCLUDE_BOARD_H -#define __BOARDS_RISCV_ESPRESSIF_ESP32C3_GENERIC_INCLUDE_BOARD_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* GPIO pins used by the GPIO Subsystem */ - -#define BOARD_NGPIOOUT 2 /* Amount of GPIO Output pins */ -#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ - -/* ESP32C3-Generic GPIOs ****************************************************/ - -/* BOOT Button */ - -#define BUTTON_BOOT 9 - -#endif /* __BOARDS_RISCV_ESPRESSIF_ESP32C3_GENERIC_INCLUDE_BOARD_H */ - diff --git a/boards/risc-v/espressif/esp32c3-generic/scripts/Make.defs b/boards/risc-v/espressif/esp32c3-generic/scripts/Make.defs deleted file mode 100644 index 9236ebb6fc4b5..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/scripts/Make.defs +++ /dev/null @@ -1,64 +0,0 @@ -############################################################################ -# boards/risc-v/espressif/esp32c3-generic/scripts/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -########################################################################### - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/tools/espressif/Config.mk -include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs - -# Remove quotes from CONFIG_ESPRESSIF_CHIP_SERIES configuration - -CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES)) - -# Pick the linker scripts from the board level if they exist, if not -# pick the common linker scripts. - -ARCHSCRIPT += $(BOARD_COMMON_DIR)/scripts/$(CHIP_SERIES)_aliases.ld -ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_flat_memory.ld) - -ifeq ($(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT),y) - ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_mcuboot_sections.ld) -else - ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_legacy_sections.ld) -endif - -ARCHPICFLAGS = -fpic - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -Werror=return-type -Werror -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -# Loadable module definitions - -CMODULEFLAGS = $(CFLAGS) - -LDMODULEFLAGS = -melf32lriscv -r -e module_initialize -LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld) - -# ELF module definitions - -CELFFLAGS = $(CFLAGS) -CXXELFFLAGS = $(CXXFLAGS) - -LDELFFLAGS = -melf32lriscv -r -e main -LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/binfmt/libelf/gnu-elf.ld) diff --git a/boards/risc-v/espressif/esp32c3-generic/src/Make.defs b/boards/risc-v/espressif/esp32c3-generic/src/Make.defs deleted file mode 100644 index 13618fe08054f..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/src/Make.defs +++ /dev/null @@ -1,43 +0,0 @@ -############################################################################# -# boards/risc-v/espressif/esp32c3-generic/src/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################# - -include $(TOPDIR)/Make.defs - -CSRCS = esp32c3_boot.c esp32c3_bringup.c - -ifeq ($(CONFIG_BOARDCTL),y) - CSRCS += esp32c3_appinit.c - - ifeq ($(CONFIG_BOARDCTL_RESET),y) - CSRCS += esp32c3_reset.c - endif -endif - -ifeq ($(CONFIG_DEV_GPIO),y) - CSRCS += esp32c3_gpio.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) - CSRCS += esp32c3_buttons.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/risc-v/espressif/esp32c3-generic/src/esp32c3-generic.h b/boards/risc-v/espressif/esp32c3-generic/src/esp32c3-generic.h deleted file mode 100644 index 5ad4c459d58a3..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/src/esp32c3-generic.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/esp32c3-generic/src/esp32c3-generic.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_RISCV_ESPRESSIF_ESP32C3_GENERIC_SRC_ESP32C3_GENERIC_H -#define __BOARDS_RISCV_ESPRESSIF_ESP32C3_GENERIC_SRC_ESP32C3_GENERIC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_bringup - * - * Description: - * Perform architecture-specific initialization. - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y : - * Called from the NSH library via board_app_initialize(). - * - * Input Parameters: - * None. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. - * - ****************************************************************************/ - -int esp_bringup(void); - -/**************************************************************************** - * Name: esp_gpio_init - * - * Description: - * Configure the GPIO driver. - * - * Returned Value: - * Zero (OK). - * - ****************************************************************************/ - -#ifdef CONFIG_DEV_GPIO -int esp_gpio_init(void); -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_RISCV_ESPRESSIF_ESP32C3_GENERIC_SRC_ESP32C3_GENERIC_H */ diff --git a/boards/risc-v/espressif/esp32c3-generic/src/esp32c3_appinit.c b/boards/risc-v/espressif/esp32c3-generic/src/esp32c3_appinit.c deleted file mode 100644 index c79226c3b1a03..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/src/esp32c3_appinit.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/esp32c3-generic/src/esp32c3_appinit.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "esp32c3-generic.h" - -#ifdef CONFIG_BOARDCTL - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_app_initialize - * - * Description: - * Perform application specific initialization. This function is never - * called directly from application code, but only indirectly via the - * (non-standard) boardctl() interface using the command BOARDIOC_INIT. - * - * Input Parameters: - * arg - The boardctl() argument is passed to the board_app_initialize() - * implementation without modification. The argument has no - * meaning to NuttX; the meaning of the argument is a contract - * between the board-specific initialization logic and the - * matching application logic. The value could be such things as a - * mode enumeration value, a set of DIP switch settings, a - * pointer to configuration data read from a file or serial FLASH, - * or whatever you would like to do with it. Every implementation - * should accept zero/NULL as a default configuration. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure to indicate the nature of the failure. - * - ****************************************************************************/ - -int board_app_initialize(uintptr_t arg) -{ -#ifdef CONFIG_BOARD_LATE_INITIALIZE - /* Board initialization already performed by board_late_initialize() */ - - return OK; -#else - /* Perform board-specific initialization */ - - return esp_bringup(); -#endif -} - -#endif /* CONFIG_BOARDCTL */ diff --git a/boards/risc-v/espressif/esp32c3-generic/src/esp32c3_boot.c b/boards/risc-v/espressif/esp32c3-generic/src/esp32c3_boot.c deleted file mode 100644 index 771f211aacdd3..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/src/esp32c3_boot.c +++ /dev/null @@ -1,89 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/esp32c3-generic/src/esp32c3_boot.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "riscv_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_board_initialize - * - * Description: - * All Espressif boards must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_board_initialize(void) -{ -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - esp_bringup(); -} -#endif diff --git a/boards/risc-v/espressif/esp32c3-generic/src/esp32c3_bringup.c b/boards/risc-v/espressif/esp32c3-generic/src/esp32c3_bringup.c deleted file mode 100644 index 6829848bb2e63..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/src/esp32c3_bringup.c +++ /dev/null @@ -1,192 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/esp32c3-generic/src/esp32c3_bringup.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "esp_board_ledc.h" - -#ifdef CONFIG_WATCHDOG -# include "esp_wdt.h" -#endif - -#ifdef CONFIG_TIMER -# include "esp_timer.h" -#endif - -#ifdef CONFIG_ONESHOT -# include "esp_oneshot.h" -#endif - -#ifdef CONFIG_RTC_DRIVER -# include "esp_rtc.h" -#endif - -#ifdef CONFIG_DEV_GPIO -# include "esp_gpio.h" -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#include "esp32c3-generic.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_bringup - * - * Description: - * Perform architecture-specific initialization. - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y : - * Called from the NSH library via board_app_initialize(). - * - * Input Parameters: - * None. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. - * - ****************************************************************************/ - -int esp_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - _err("Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#ifdef CONFIG_FS_TMPFS - /* Mount the tmpfs file system */ - - ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); - if (ret < 0) - { - _err("Failed to mount tmpfs at %s: %d\n", CONFIG_LIBC_TMPDIR, ret); - } -#endif - -#ifdef CONFIG_WATCHDOG - ret = esp_wdt_initialize(); - if (ret < 0) - { - _err("Failed to initialize WDT: %d\n", ret); - } -#endif - -#ifdef CONFIG_TIMER - ret = esp_timer_initialize(0); - if (ret < 0) - { - _err("Failed to initialize Timer 0: %d\n", ret); - } - -#ifndef CONFIG_ONESHOT - ret = esp_timer_initialize(1); - if (ret < 0) - { - _err("Failed to initialize Timer 1: %d\n", ret); - } -#endif -#endif - -#ifdef CONFIG_ONESHOT - ret = esp_oneshot_initialize(); - if (ret < 0) - { - _err("Failed to initialize Oneshot Timer: %d\n", ret); - } -#endif - -#ifdef CONFIG_RTC_DRIVER - /* Initialize the RTC driver */ - - ret = esp_rtc_driverinit(); - if (ret < 0) - { - _err("Failed to initialize the RTC driver: %d\n", ret); - } -#endif - -#ifdef CONFIG_DEV_GPIO - ret = esp_gpio_init(); - if (ret < 0) - { - ierr("Failed to initialize GPIO Driver: %d\n", ret); - } -#endif - -#if defined(CONFIG_INPUT_BUTTONS) && defined(CONFIG_INPUT_BUTTONS_LOWER) - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - ierr("ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ESPRESSIF_LEDC - ret = board_ledc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_ledc_setup() failed: %d\n", ret); - } -#endif /* CONFIG_ESPRESSIF_LEDC */ - - /* If we got here then perhaps not all initialization was successful, but - * at least enough succeeded to bring-up NSH with perhaps reduced - * capabilities. - */ - - return ret; -} diff --git a/boards/risc-v/espressif/esp32c3-generic/src/esp32c3_gpio.c b/boards/risc-v/espressif/esp32c3-generic/src/esp32c3_gpio.c deleted file mode 100644 index 5ed5be4e7bf76..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/src/esp32c3_gpio.c +++ /dev/null @@ -1,512 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/esp32c3-generic/src/esp32c3_gpio.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* Config */ - -#include - -/* Libc */ - -#include -#include -#include -#include - -/* NuttX */ - -#include -#include -#include - -/* Arch */ - -#include "esp_gpio.h" - -/* Board */ - -#include "esp32c3-generic.h" -#include - -/* HAL */ - -#include - -#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Pin 1 and 2 are used for this example as GPIO outputs. */ - -#define GPIO_OUT1 1 -#define GPIO_OUT2 2 - -#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 -# error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" -#endif - -/* Interrupt pins. GPIO9 is used as an example, any other inputs could be - * used. - */ - -#define GPIO_IRQPIN 9 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct espgpio_dev_s -{ - struct gpio_dev_s gpio; - uint8_t id; -}; - -struct espgpint_dev_s -{ - struct espgpio_dev_s espgpio; - pin_interrupt_t callback; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#if BOARD_NGPIOOUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value); -static int gpout_write(struct gpio_dev_s *dev, bool value); -static int gpout_setpintype(struct gpio_dev_s *dev, - enum gpio_pintype_e pintype); -#endif - -#if BOARD_NGPIOINT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value); -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback); -static int gpint_enable(struct gpio_dev_s *dev, bool enable); -static int gpint_setpintype(struct gpio_dev_s *dev, - enum gpio_pintype_e pintype); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if BOARD_NGPIOOUT > 0 -static const struct gpio_operations_s gpout_ops = -{ - .go_read = gpout_read, - .go_write = gpout_write, - .go_attach = NULL, - .go_enable = NULL, - .go_setpintype = gpout_setpintype, -}; - -/* This array maps the GPIO pins used as OUTPUT */ - -static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = -{ - GPIO_OUT1, GPIO_OUT2 -}; - -static struct espgpio_dev_s g_gpout[BOARD_NGPIOOUT]; -#endif - -#if BOARD_NGPIOINT > 0 -static const struct gpio_operations_s gpint_ops = -{ - .go_read = gpint_read, - .go_write = NULL, - .go_attach = gpint_attach, - .go_enable = gpint_enable, - .go_setpintype = gpint_setpintype, -}; - -/* This array maps the GPIO pins used as INTERRUPT INPUTS */ - -static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = -{ - GPIO_IRQPIN, -}; - -static struct espgpint_dev_s g_gpint[BOARD_NGPIOINT]; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: gpout_read - * - * Description: - * Read a digital output pin. - * - * Parameters: - * dev - A pointer to the gpio driver struct. - * value - A pointer to store the state of the pin. - * - * Returned Value: - * Zero (OK). - * - ****************************************************************************/ - -#if BOARD_NGPIOOUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value) -{ - struct espgpio_dev_s *espgpio = (struct espgpio_dev_s *)dev; - - DEBUGASSERT(espgpio != NULL && value != NULL); - DEBUGASSERT(espgpio->id < BOARD_NGPIOOUT); - gpioinfo("Reading...\n"); - - *value = esp_gpioread(g_gpiooutputs[espgpio->id]); - return OK; -} - -/**************************************************************************** - * Name: gpout_write - * - * Description: - * Write to a digital output pin. - * - * Parameters: - * dev - A pointer to the gpio driver struct. - * value - The value to be written. - * - * Returned Value: - * Zero (OK). - * - ****************************************************************************/ - -static int gpout_write(struct gpio_dev_s *dev, bool value) -{ - struct espgpio_dev_s *espgpio = (struct espgpio_dev_s *)dev; - - DEBUGASSERT(espgpio != NULL); - DEBUGASSERT(espgpio->id < BOARD_NGPIOOUT); - gpioinfo("Writing %d\n", (int)value); - - esp_gpiowrite(g_gpiooutputs[espgpio->id], value); - return OK; -} - -/**************************************************************************** - * Name: gpout_setpintype - * - * Description: - * Set digital output pin type. - * - * Parameters: - * dev - A pointer to the gpio driver struct. - * pintype - The pin type. See nuttx/ioexpander/gpio.h. - * - * Returned Value: - * Zero (OK) on success; -1 (ERROR) otherwise. - * - ****************************************************************************/ - -static int gpout_setpintype(struct gpio_dev_s *dev, - enum gpio_pintype_e pintype) -{ - struct espgpio_dev_s *espgpio = (struct espgpio_dev_s *)dev; - - DEBUGASSERT(espgpio != NULL); - DEBUGASSERT(espgpio->id < BOARD_NGPIOOUT); - gpioinfo("Setting pintype: %d\n", (int)pintype); - - esp_gpio_matrix_out(g_gpiooutputs[espgpio->id], - SIG_GPIO_OUT_IDX, 0, 0); - - switch (pintype) - { - case GPIO_INPUT_PIN: - esp_configgpio(g_gpiooutputs[espgpio->id], INPUT); - break; - case GPIO_INPUT_PIN_PULLUP: - esp_configgpio(g_gpiooutputs[espgpio->id], INPUT_PULLUP); - break; - case GPIO_INPUT_PIN_PULLDOWN: - esp_configgpio(g_gpiooutputs[espgpio->id], INPUT_PULLDOWN); - break; - case GPIO_OUTPUT_PIN: - esp_configgpio(g_gpiooutputs[espgpio->id], INPUT | OUTPUT); - break; - case GPIO_OUTPUT_PIN_OPENDRAIN: - esp_configgpio(g_gpiooutputs[espgpio->id], - INPUT | OUTPUT_OPEN_DRAIN); - break; - default: - return ERROR; - break; - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: espgpio_interrupt - * - * Description: - * Digital input interrupt handler. - * - * Input Parameters: - * irq - Identifier of the interrupt request. - * context - Context data from the ISR. - * arg - Opaque pointer to the internal driver state structure. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -#if BOARD_NGPIOINT > 0 -static int espgpio_interrupt(int irq, void *context, void *arg) -{ - struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)arg; - - DEBUGASSERT(espgpint != NULL && espgpint->callback != NULL); - gpioinfo("Interrupt! callback=%p\n", espgpint->callback); - - espgpint->callback(&espgpint->espgpio.gpio, espgpint->espgpio.id); - return OK; -} - -/**************************************************************************** - * Name: gpint_read - * - * Description: - * Read a digital input pin. - * - * Parameters: - * dev - A pointer to the gpio driver struct. - * value - A pointer to store the state of the pin. - * - * Returned Value: - * Zero (OK). - * - ****************************************************************************/ - -static int gpint_read(struct gpio_dev_s *dev, bool *value) -{ - struct espgpint_dev_s *espgpint = - (struct espgpint_dev_s *)dev; - - DEBUGASSERT(espgpint != NULL && value != NULL); - DEBUGASSERT(espgpint->espgpio.id < BOARD_NGPIOINT); - gpioinfo("Reading int pin...\n"); - - *value = esp_gpioread(g_gpiointinputs[espgpint->espgpio.id]); - return OK; -} - -/**************************************************************************** - * Name: gpint_attach - * - * Description: - * Attach the ISR to IRQ and register the callback. But it still doesn't - * enable interrupt yet. - * - * Parameters: - * dev - A pointer to the gpio driver struct. - * callback - User callback function. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback) -{ - struct espgpint_dev_s *espgpint = - (struct espgpint_dev_s *)dev; - int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); - int ret; - - gpioinfo("Attaching the callback\n"); - - /* Make sure the interrupt is disabled */ - - esp_gpioirqdisable(irq); - ret = irq_attach(irq, - espgpio_interrupt, - &g_gpint[espgpint->espgpio.id]); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", callback); - espgpint->callback = callback; - return OK; -} - -/**************************************************************************** - * Name: gpint_enable - * - * Description: - * Enable/Disable interrupt. - * - * Parameters: - * dev - A pointer to the gpio driver struct. - * enable - True to enable, false to disable. - * - * Returned Value: - * Zero (OK). - * - ****************************************************************************/ - -static int gpint_enable(struct gpio_dev_s *dev, bool enable) -{ - struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; - int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); - - if (enable) - { - if (espgpint->callback != NULL) - { - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising edge */ - - esp_gpioirqenable(irq, RISING); - } - } - else - { - gpioinfo("Disable the interrupt\n"); - esp_gpioirqdisable(irq); - } - - return OK; -} - -/**************************************************************************** - * Name: gpint_setpintype - * - * Description: - * Set digital interrupt pin type. - * - * Parameters: - * dev - A pointer to the gpio driver struct. - * pintype - The pin type. See nuttx/ioexpander/gpio.h. - * - * Returned Value: - * Zero (OK) on success; -1 (ERROR) otherwise. - * - ****************************************************************************/ - -static int gpint_setpintype(struct gpio_dev_s *dev, - enum gpio_pintype_e pintype) -{ - struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; - - DEBUGASSERT(espgpint != NULL); - DEBUGASSERT(espgpint->espgpio.id < BOARD_NGPIOINT); - gpioinfo("Setting pintype: %d\n", (int)pintype); - switch (pintype) - { - case GPIO_INTERRUPT_HIGH_PIN: - esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], - INPUT_PULLUP); - break; - case GPIO_INTERRUPT_LOW_PIN: - esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], - INPUT_PULLDOWN); - break; - default: - return ERROR; - break; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_gpio_init - * - * Description: - * Configure the GPIO driver. - * - * Returned Value: - * Zero (OK). - * - ****************************************************************************/ - -int esp_gpio_init(void) -{ - int pincount = 0; - int i; - -#if BOARD_NGPIOOUT > 0 - for (i = 0; i < BOARD_NGPIOOUT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; - g_gpout[i].gpio.gp_ops = &gpout_ops; - g_gpout[i].id = i; - gpio_pin_register(&g_gpout[i].gpio, pincount); - - /* Configure the pins that will be used as output */ - - esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_1 | INPUT_FUNCTION_1); - esp_gpiowrite(g_gpiooutputs[i], 0); - - pincount++; - } -#endif - -#if BOARD_NGPIOINT > 0 - for (i = 0; i < BOARD_NGPIOINT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpint[i].espgpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; - g_gpint[i].espgpio.gpio.gp_ops = &gpint_ops; - g_gpint[i].espgpio.id = i; - gpio_pin_register(&g_gpint[i].espgpio.gpio, pincount); - - /* Configure the pins that will be used as interrupt input */ - - esp_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_1 | PULLDOWN); - - pincount++; - } -#endif - - return OK; -} -#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/risc-v/espressif/esp32c3-generic/src/esp32c3_reset.c b/boards/risc-v/espressif/esp32c3-generic/src/esp32c3_reset.c deleted file mode 100644 index f6689c4a51f6f..0000000000000 --- a/boards/risc-v/espressif/esp32c3-generic/src/esp32c3_reset.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/esp32c3-generic/src/esp32c3_reset.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "esp_systemreset.h" - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value in this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - syslog(LOG_INFO, "reboot status=%d\n", status); - - switch (status) - { - case EXIT_SUCCESS: - up_shutdown_handler(); - break; - case CONFIG_BOARD_ASSERT_RESET_VALUE: - default: - break; - } - - up_systemreset(); - - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/risc-v/espressif/esp32c6-generic/Kconfig b/boards/risc-v/espressif/esp32c6-generic/Kconfig deleted file mode 100644 index b8f2c2b0232e1..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -if ARCH_BOARD_ESP32C6_GENERIC - -endif # ARCH_BOARD_ESP32C6_GENERIC diff --git a/boards/risc-v/espressif/esp32c6-generic/configs/buttons/defconfig b/boards/risc-v/espressif/esp32c6-generic/configs/buttons/defconfig deleted file mode 100644 index 2475ace8f7de6..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/configs/buttons/defconfig +++ /dev/null @@ -1,52 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c6-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C6_GENERIC=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32C6=y -CONFIG_ESPRESSIF_GPIO_IRQ=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32c6-generic/configs/gpio/defconfig b/boards/risc-v/espressif/esp32c6-generic/configs/gpio/defconfig deleted file mode 100644 index bf50b0727f8b6..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/configs/gpio/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c6-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C6_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_GPIO=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32C6=y -CONFIG_ESPRESSIF_GPIO_IRQ=y -CONFIG_EXAMPLES_GPIO=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32c6-generic/configs/nsh/defconfig b/boards/risc-v/espressif/esp32c6-generic/configs/nsh/defconfig deleted file mode 100644 index f53741648451f..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/configs/nsh/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c6-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C6_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32C6=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32c6-generic/configs/ostest/defconfig b/boards/risc-v/espressif/esp32c6-generic/configs/ostest/defconfig deleted file mode 100644 index df57912d1a50b..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/configs/ostest/defconfig +++ /dev/null @@ -1,46 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c6-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C6_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32C6=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32c6-generic/configs/pwm/defconfig b/boards/risc-v/espressif/esp32c6-generic/configs/pwm/defconfig deleted file mode 100644 index 1ab64eb3174b7..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/configs/pwm/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c6-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C6_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32C6=y -CONFIG_ESPRESSIF_LEDC=y -CONFIG_ESPRESSIF_LEDC_TIMER0=y -CONFIG_EXAMPLES_PWM=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32c6-generic/configs/random/defconfig b/boards/risc-v/espressif/esp32c6-generic/configs/random/defconfig deleted file mode 100644 index f9853f93321b7..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/configs/random/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c6-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C6_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_URANDOM=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32C6=y -CONFIG_EXAMPLES_RANDOM=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=3 -CONFIG_START_YEAR=2023 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32c6-generic/configs/rtc/defconfig b/boards/risc-v/espressif/esp32c6-generic/configs/rtc/defconfig deleted file mode 100644 index 3d6988d808dab..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/configs/rtc/defconfig +++ /dev/null @@ -1,52 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c6-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C6_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32C6=y -CONFIG_EXAMPLES_ALARM=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_DATE=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC=y -CONFIG_RTC_ALARM=y -CONFIG_RTC_DRIVER=y -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=4 -CONFIG_START_YEAR=2023 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32c6-generic/configs/tickless/defconfig b/boards/risc-v/espressif/esp32c6-generic/configs/tickless/defconfig deleted file mode 100644 index 2bd1369757436..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/configs/tickless/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c6-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C6_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32C6=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_TICKLESS=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_USEC_PER_TICK=10000 diff --git a/boards/risc-v/espressif/esp32c6-generic/configs/timers/defconfig b/boards/risc-v/espressif/esp32c6-generic/configs/timers/defconfig deleted file mode 100644 index c36bb8b8b4418..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/configs/timers/defconfig +++ /dev/null @@ -1,50 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c6-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C6_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32C6=y -CONFIG_EXAMPLES_ONESHOT=y -CONFIG_EXAMPLES_TIMER=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_ONESHOT=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=28 -CONFIG_START_MONTH=3 -CONFIG_START_YEAR=2023 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_TIMER=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32c6-generic/configs/usbconsole/defconfig b/boards/risc-v/espressif/esp32c6-generic/configs/usbconsole/defconfig deleted file mode 100644 index ab2d8f96cda98..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/configs/usbconsole/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ESPRESSIF_UART0 is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c6-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C6_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32C6=y -CONFIG_ESPRESSIF_USBSERIAL=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y diff --git a/boards/risc-v/espressif/esp32c6-generic/configs/watchdog/defconfig b/boards/risc-v/espressif/esp32c6-generic/configs/watchdog/defconfig deleted file mode 100644 index 6b0858915a54c..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/configs/watchdog/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32c6-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32C6_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32C6=y -CONFIG_EXAMPLES_WATCHDOG=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_WATCHDOG=y diff --git a/boards/risc-v/espressif/esp32c6-generic/include/board.h b/boards/risc-v/espressif/esp32c6-generic/include/board.h deleted file mode 100644 index 2a07d2e4cf8e3..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/include/board.h +++ /dev/null @@ -1,40 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/esp32c6-generic/include/board.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_RISCV_ESPRESSIF_ESP32C6_GENERIC_INCLUDE_BOARD_H -#define __BOARDS_RISCV_ESPRESSIF_ESP32C6_GENERIC_INCLUDE_BOARD_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* GPIO pins used by the GPIO Subsystem */ - -#define BOARD_NGPIOOUT 2 /* Amount of GPIO Output pins */ -#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ - -/* ESP32C6-Generic GPIOs ****************************************************/ - -/* BOOT Button */ - -#define BUTTON_BOOT 9 - -#endif /* __BOARDS_RISCV_ESPRESSIF_ESP32C6_GENERIC_INCLUDE_BOARD_H */ - diff --git a/boards/risc-v/espressif/esp32c6-generic/scripts/Make.defs b/boards/risc-v/espressif/esp32c6-generic/scripts/Make.defs deleted file mode 100644 index 792bef6cd71dc..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/scripts/Make.defs +++ /dev/null @@ -1,60 +0,0 @@ -############################################################################ -# boards/risc-v/espressif/esp32c6-generic/scripts/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -########################################################################### - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/tools/espressif/Config.mk -include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs - -# Remove quotes from CONFIG_ESPRESSIF_CHIP_SERIES configuration - -CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES)) - -# Pick the linker scripts from the board level if they exist, if not -# pick the common linker scripts. - -ARCHSCRIPT += $(BOARD_COMMON_DIR)/scripts/$(CHIP_SERIES)_aliases.ld - -ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_flat_memory.ld) -ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_legacy_sections.ld) - -ARCHPICFLAGS = -fpic - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -Werror=return-type -Werror -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -# Loadable module definitions - -CMODULEFLAGS = $(CFLAGS) - -LDMODULEFLAGS = -melf32lriscv -r -e module_initialize -LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld) - -# ELF module definitions - -CELFFLAGS = $(CFLAGS) -CXXELFFLAGS = $(CXXFLAGS) - -LDELFFLAGS = -melf32lriscv -r -e main -LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/binfmt/libelf/gnu-elf.ld) diff --git a/boards/risc-v/espressif/esp32c6-generic/src/Make.defs b/boards/risc-v/espressif/esp32c6-generic/src/Make.defs deleted file mode 100644 index bbd7474093554..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/src/Make.defs +++ /dev/null @@ -1,43 +0,0 @@ -############################################################################# -# boards/risc-v/espressif/esp32c6-generic/src/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################# - -include $(TOPDIR)/Make.defs - -CSRCS = esp32c6_boot.c esp32c6_bringup.c - -ifeq ($(CONFIG_BOARDCTL),y) - CSRCS += esp32c6_appinit.c - - ifeq ($(CONFIG_BOARDCTL_RESET),y) - CSRCS += esp32c6_reset.c - endif -endif - -ifeq ($(CONFIG_DEV_GPIO),y) - CSRCS += esp32c6_gpio.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) - CSRCS += esp32c6_buttons.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/risc-v/espressif/esp32c6-generic/src/esp32c6-generic.h b/boards/risc-v/espressif/esp32c6-generic/src/esp32c6-generic.h deleted file mode 100644 index 0c7325e5c1ce3..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/src/esp32c6-generic.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/esp32c6-generic/src/esp32c6-generic.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_RISCV_ESPRESSIF_ESP32C6_GENERIC_SRC_ESP32C6_GENERIC_H -#define __BOARDS_RISCV_ESPRESSIF_ESP32C6_GENERIC_SRC_ESP32C6_GENERIC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_bringup - * - * Description: - * Perform architecture-specific initialization. - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y : - * Called from the NSH library via board_app_initialize(). - * - * Input Parameters: - * None. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. - * - ****************************************************************************/ - -int esp_bringup(void); - -/**************************************************************************** - * Name: esp_gpio_init - * - * Description: - * Configure the GPIO driver. - * - * Returned Value: - * Zero (OK). - * - ****************************************************************************/ - -#ifdef CONFIG_DEV_GPIO -int esp_gpio_init(void); -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_RISCV_ESPRESSIF_ESP32C6_GENERIC_SRC_ESP32C6_GENERIC_H */ diff --git a/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_appinit.c b/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_appinit.c deleted file mode 100644 index 2097b7046beef..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_appinit.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/esp32c6-generic/src/esp32c6_appinit.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "esp32c6-generic.h" - -#ifdef CONFIG_BOARDCTL - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_app_initialize - * - * Description: - * Perform application specific initialization. This function is never - * called directly from application code, but only indirectly via the - * (non-standard) boardctl() interface using the command BOARDIOC_INIT. - * - * Input Parameters: - * arg - The boardctl() argument is passed to the board_app_initialize() - * implementation without modification. The argument has no - * meaning to NuttX; the meaning of the argument is a contract - * between the board-specific initialization logic and the - * matching application logic. The value could be such things as a - * mode enumeration value, a set of DIP switch settings, a - * pointer to configuration data read from a file or serial FLASH, - * or whatever you would like to do with it. Every implementation - * should accept zero/NULL as a default configuration. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure to indicate the nature of the failure. - * - ****************************************************************************/ - -int board_app_initialize(uintptr_t arg) -{ -#ifdef CONFIG_BOARD_LATE_INITIALIZE - /* Board initialization already performed by board_late_initialize() */ - - return OK; -#else - /* Perform board-specific initialization */ - - return esp_bringup(); -#endif -} - -#endif /* CONFIG_BOARDCTL */ diff --git a/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_boot.c b/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_boot.c deleted file mode 100644 index c22b26cd1faf1..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_boot.c +++ /dev/null @@ -1,89 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/esp32c6-generic/src/esp32c6_boot.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "riscv_internal.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_board_initialize - * - * Description: - * All Espressif boards must provide the following entry point. - * This entry point is called early in the initialization -- after all - * memory has been configured and mapped but before any devices have been - * initialized. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp_board_initialize(void) -{ -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called immediately after up_initialize() is called and just before - * the initial application is started. This additional initialization - * phase may be used, for example, to initialize board-specific device - * drivers. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef CONFIG_BOARD_LATE_INITIALIZE -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - - esp_bringup(); -} -#endif diff --git a/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_bringup.c b/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_bringup.c deleted file mode 100644 index a5e3076d44476..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_bringup.c +++ /dev/null @@ -1,192 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/esp32c6-generic/src/esp32c6_bringup.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "esp_board_ledc.h" - -#ifdef CONFIG_WATCHDOG -# include "esp_wdt.h" -#endif - -#ifdef CONFIG_TIMER -# include "esp_timer.h" -#endif - -#ifdef CONFIG_ONESHOT -# include "esp_oneshot.h" -#endif - -#ifdef CONFIG_RTC_DRIVER -# include "esp_rtc.h" -#endif - -#ifdef CONFIG_DEV_GPIO -# include "esp_gpio.h" -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#include "esp32c6-generic.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_bringup - * - * Description: - * Perform architecture-specific initialization. - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y : - * Called from the NSH library via board_app_initialize(). - * - * Input Parameters: - * None. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. - * - ****************************************************************************/ - -int esp_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - _err("Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#ifdef CONFIG_FS_TMPFS - /* Mount the tmpfs file system */ - - ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); - if (ret < 0) - { - _err("Failed to mount tmpfs at %s: %d\n", CONFIG_LIBC_TMPDIR, ret); - } -#endif - -#ifdef CONFIG_WATCHDOG - ret = esp_wdt_initialize(); - if (ret < 0) - { - _err("Failed to initialize WDT: %d\n", ret); - } -#endif - -#ifdef CONFIG_TIMER - ret = esp_timer_initialize(0); - if (ret < 0) - { - _err("Failed to initialize Timer 0: %d\n", ret); - } - -#ifndef CONFIG_ONESHOT - ret = esp_timer_initialize(1); - if (ret < 0) - { - _err("Failed to initialize Timer 1: %d\n", ret); - } -#endif -#endif - -#ifdef CONFIG_ONESHOT - ret = esp_oneshot_initialize(); - if (ret < 0) - { - _err("Failed to initialize Oneshot Timer: %d\n", ret); - } -#endif - -#ifdef CONFIG_RTC_DRIVER - /* Initialize the RTC driver */ - - ret = esp_rtc_driverinit(); - if (ret < 0) - { - _err("Failed to initialize the RTC driver: %d\n", ret); - } -#endif - -#ifdef CONFIG_DEV_GPIO - ret = esp_gpio_init(); - if (ret < 0) - { - ierr("Failed to initialize GPIO Driver: %d\n", ret); - } -#endif - -#if defined(CONFIG_INPUT_BUTTONS) && defined(CONFIG_INPUT_BUTTONS_LOWER) - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - ierr("ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ESPRESSIF_LEDC - ret = board_ledc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_ledc_setup() failed: %d\n", ret); - } -#endif /* CONFIG_ESPRESSIF_LEDC */ - - /* If we got here then perhaps not all initialization was successful, but - * at least enough succeeded to bring-up NSH with perhaps reduced - * capabilities. - */ - - return ret; -} diff --git a/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_buttons.c b/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_buttons.c deleted file mode 100644 index bdb9c422b736f..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_buttons.c +++ /dev/null @@ -1,198 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/esp32c6-generic/src/esp32c6_buttons.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* Config */ - -#include - -/* Libc */ - -#include -#include -#include -#include -#include - -/* NuttX */ - -#include -#include -#include -#include - -/* Arch */ - -#include "esp_gpio.h" - -/* Board */ - -#include "esp32c6-generic.h" -#include - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_button_initialize - * - * Description: - * board_button_initialize() must be called to initialize button resources. - * After that, board_buttons() may be called to collect the current state - * of all buttons or board_button_irq() may be called to register button - * interrupt handlers. - * - * Input Parameters: - * None. - * - * Returned Value: - * The number of buttons that were initialized. - * - ****************************************************************************/ - -uint32_t board_button_initialize(void) -{ - esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP); - return 1; -} - -/**************************************************************************** - * Name: board_buttons - * - * Description: - * After board_button_initialize() has been called, board_buttons() may be - * called to collect the state of all buttons. - * - * Input Parameters: - * None. - * - * Returned Value: - * An 8-bit bit set with each bit associated with a button. See the - * BUTTON_*_BIT definitions in board.h for the meaning of each bit. - * - ****************************************************************************/ - -uint32_t board_buttons(void) -{ - uint8_t ret = 0; - int i = 0; - int n = 0; - - bool b0 = esp_gpioread(BUTTON_BOOT); - - for (i = 0; i < 10; i++) - { - up_mdelay(1); /* TODO */ - - bool b1 = esp_gpioread(BUTTON_BOOT); - - if (b0 == b1) - { - n++; - } - else - { - n = 0; - } - - if (3 == n) - { - break; - } - - b0 = b1; - } - - iinfo("b=%d n=%d\n", b0, n); - - /* Low value means that the button is pressed */ - - if (!b0) - { - ret = 0x1; - } - - return ret; -} - -/**************************************************************************** - * Name: board_button_irq - * - * Description: - * board_button_irq() may be called to register an interrupt handler that - * will be called when a button is depressed or released. The ID value is - * a button enumeration value that uniquely identifies a button resource. - * See the BUTTON_* definitions in board.h for the meaning of enumeration - * value. - * - * Input Parameters: - * id - Identifies the button to be monitored. It is equivalent to - * the bit used to report the button state in the return value - * from board_buttons(). - * irqhandler - The handler that will be invoked when the interrupt occurs. - * arg - Pointer to the arguments that will be provided to the - * interrupt handler. - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -#ifdef CONFIG_ARCH_IRQBUTTONS -int board_button_irq(int id, xcpt_t irqhandler, void *arg) -{ - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP_PIN2IRQ(BUTTON_BOOT); - - if (NULL != irqhandler) - { - /* Make sure the interrupt is disabled */ - - esp_gpioirqdisable(irq); - - gpioinfo("Attach %p\n", irqhandler); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - /* Configure the interrupt for rising and falling edges */ - - gpioinfo("Enabling the interrupt\n"); - esp_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp_gpioirqdisable(irq); - } - - return OK; -} -#endif diff --git a/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_gpio.c b/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_gpio.c deleted file mode 100644 index d1c462c4965c9..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_gpio.c +++ /dev/null @@ -1,512 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/esp32c6-generic/src/esp32c6_gpio.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/* Config */ - -#include - -/* Libc */ - -#include -#include -#include -#include - -/* NuttX */ - -#include -#include -#include - -/* Arch */ - -#include "esp_gpio.h" - -/* Board */ - -#include "esp32c6-generic.h" -#include - -/* HAL */ - -#include - -#if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Pin 1 and 2 are used for this example as GPIO outputs. */ - -#define GPIO_OUT1 1 -#define GPIO_OUT2 2 - -#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 -# error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" -#endif - -/* Interrupt pins. GPIO9 is used as an example, any other inputs could be - * used. - */ - -#define GPIO_IRQPIN 9 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct espgpio_dev_s -{ - struct gpio_dev_s gpio; - uint8_t id; -}; - -struct espgpint_dev_s -{ - struct espgpio_dev_s espgpio; - pin_interrupt_t callback; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -#if BOARD_NGPIOOUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value); -static int gpout_write(struct gpio_dev_s *dev, bool value); -static int gpout_setpintype(struct gpio_dev_s *dev, - enum gpio_pintype_e pintype); -#endif - -#if BOARD_NGPIOINT > 0 -static int gpint_read(struct gpio_dev_s *dev, bool *value); -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback); -static int gpint_enable(struct gpio_dev_s *dev, bool enable); -static int gpint_setpintype(struct gpio_dev_s *dev, - enum gpio_pintype_e pintype); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#if BOARD_NGPIOOUT > 0 -static const struct gpio_operations_s gpout_ops = -{ - .go_read = gpout_read, - .go_write = gpout_write, - .go_attach = NULL, - .go_enable = NULL, - .go_setpintype = gpout_setpintype, -}; - -/* This array maps the GPIO pins used as OUTPUT */ - -static const uint32_t g_gpiooutputs[BOARD_NGPIOOUT] = -{ - GPIO_OUT1, GPIO_OUT2 -}; - -static struct espgpio_dev_s g_gpout[BOARD_NGPIOOUT]; -#endif - -#if BOARD_NGPIOINT > 0 -static const struct gpio_operations_s gpint_ops = -{ - .go_read = gpint_read, - .go_write = NULL, - .go_attach = gpint_attach, - .go_enable = gpint_enable, - .go_setpintype = gpint_setpintype, -}; - -/* This array maps the GPIO pins used as INTERRUPT INPUTS */ - -static const uint32_t g_gpiointinputs[BOARD_NGPIOINT] = -{ - GPIO_IRQPIN, -}; - -static struct espgpint_dev_s g_gpint[BOARD_NGPIOINT]; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: gpout_read - * - * Description: - * Read a digital output pin. - * - * Parameters: - * dev - A pointer to the gpio driver struct. - * value - A pointer to store the state of the pin. - * - * Returned Value: - * Zero (OK). - * - ****************************************************************************/ - -#if BOARD_NGPIOOUT > 0 -static int gpout_read(struct gpio_dev_s *dev, bool *value) -{ - struct espgpio_dev_s *espgpio = (struct espgpio_dev_s *)dev; - - DEBUGASSERT(espgpio != NULL && value != NULL); - DEBUGASSERT(espgpio->id < BOARD_NGPIOOUT); - gpioinfo("Reading...\n"); - - *value = esp_gpioread(g_gpiooutputs[espgpio->id]); - return OK; -} - -/**************************************************************************** - * Name: gpout_write - * - * Description: - * Write to a digital output pin. - * - * Parameters: - * dev - A pointer to the gpio driver struct. - * value - The value to be written. - * - * Returned Value: - * Zero (OK). - * - ****************************************************************************/ - -static int gpout_write(struct gpio_dev_s *dev, bool value) -{ - struct espgpio_dev_s *espgpio = (struct espgpio_dev_s *)dev; - - DEBUGASSERT(espgpio != NULL); - DEBUGASSERT(espgpio->id < BOARD_NGPIOOUT); - gpioinfo("Writing %d\n", (int)value); - - esp_gpiowrite(g_gpiooutputs[espgpio->id], value); - return OK; -} - -/**************************************************************************** - * Name: gpout_setpintype - * - * Description: - * Set digital output pin type. - * - * Parameters: - * dev - A pointer to the gpio driver struct. - * pintype - The pin type. See nuttx/ioexpander/gpio.h. - * - * Returned Value: - * Zero (OK) on success; -1 (ERROR) otherwise. - * - ****************************************************************************/ - -static int gpout_setpintype(struct gpio_dev_s *dev, - enum gpio_pintype_e pintype) -{ - struct espgpio_dev_s *espgpio = (struct espgpio_dev_s *)dev; - - DEBUGASSERT(espgpio != NULL); - DEBUGASSERT(espgpio->id < BOARD_NGPIOOUT); - gpioinfo("Setting pintype: %d\n", (int)pintype); - - esp_gpio_matrix_out(g_gpiooutputs[espgpio->id], - SIG_GPIO_OUT_IDX, 0, 0); - - switch (pintype) - { - case GPIO_INPUT_PIN: - esp_configgpio(g_gpiooutputs[espgpio->id], INPUT); - break; - case GPIO_INPUT_PIN_PULLUP: - esp_configgpio(g_gpiooutputs[espgpio->id], INPUT_PULLUP); - break; - case GPIO_INPUT_PIN_PULLDOWN: - esp_configgpio(g_gpiooutputs[espgpio->id], INPUT_PULLDOWN); - break; - case GPIO_OUTPUT_PIN: - esp_configgpio(g_gpiooutputs[espgpio->id], INPUT | OUTPUT); - break; - case GPIO_OUTPUT_PIN_OPENDRAIN: - esp_configgpio(g_gpiooutputs[espgpio->id], - INPUT | OUTPUT_OPEN_DRAIN); - break; - default: - return ERROR; - break; - } - - return OK; -} -#endif - -/**************************************************************************** - * Name: espgpio_interrupt - * - * Description: - * Digital input interrupt handler. - * - * Input Parameters: - * irq - Identifier of the interrupt request. - * context - Context data from the ISR. - * arg - Opaque pointer to the internal driver state structure. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -#if BOARD_NGPIOINT > 0 -static int espgpio_interrupt(int irq, void *context, void *arg) -{ - struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)arg; - - DEBUGASSERT(espgpint != NULL && espgpint->callback != NULL); - gpioinfo("Interrupt! callback=%p\n", espgpint->callback); - - espgpint->callback(&espgpint->espgpio.gpio, espgpint->espgpio.id); - return OK; -} - -/**************************************************************************** - * Name: gpint_read - * - * Description: - * Read a digital input pin. - * - * Parameters: - * dev - A pointer to the gpio driver struct. - * value - A pointer to store the state of the pin. - * - * Returned Value: - * Zero (OK). - * - ****************************************************************************/ - -static int gpint_read(struct gpio_dev_s *dev, bool *value) -{ - struct espgpint_dev_s *espgpint = - (struct espgpint_dev_s *)dev; - - DEBUGASSERT(espgpint != NULL && value != NULL); - DEBUGASSERT(espgpint->espgpio.id < BOARD_NGPIOINT); - gpioinfo("Reading int pin...\n"); - - *value = esp_gpioread(g_gpiointinputs[espgpint->espgpio.id]); - return OK; -} - -/**************************************************************************** - * Name: gpint_attach - * - * Description: - * Attach the ISR to IRQ and register the callback. But it still doesn't - * enable interrupt yet. - * - * Parameters: - * dev - A pointer to the gpio driver struct. - * callback - User callback function. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -static int gpint_attach(struct gpio_dev_s *dev, - pin_interrupt_t callback) -{ - struct espgpint_dev_s *espgpint = - (struct espgpint_dev_s *)dev; - int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); - int ret; - - gpioinfo("Attaching the callback\n"); - - /* Make sure the interrupt is disabled */ - - esp_gpioirqdisable(irq); - ret = irq_attach(irq, - espgpio_interrupt, - &g_gpint[espgpint->espgpio.id]); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", callback); - espgpint->callback = callback; - return OK; -} - -/**************************************************************************** - * Name: gpint_enable - * - * Description: - * Enable/Disable interrupt. - * - * Parameters: - * dev - A pointer to the gpio driver struct. - * enable - True to enable, false to disable. - * - * Returned Value: - * Zero (OK). - * - ****************************************************************************/ - -static int gpint_enable(struct gpio_dev_s *dev, bool enable) -{ - struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; - int irq = ESP_PIN2IRQ(g_gpiointinputs[espgpint->espgpio.id]); - - if (enable) - { - if (espgpint->callback != NULL) - { - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising edge */ - - esp_gpioirqenable(irq, RISING); - } - } - else - { - gpioinfo("Disable the interrupt\n"); - esp_gpioirqdisable(irq); - } - - return OK; -} - -/**************************************************************************** - * Name: gpint_setpintype - * - * Description: - * Set digital interrupt pin type. - * - * Parameters: - * dev - A pointer to the gpio driver struct. - * pintype - The pin type. See nuttx/ioexpander/gpio.h. - * - * Returned Value: - * Zero (OK) on success; -1 (ERROR) otherwise. - * - ****************************************************************************/ - -static int gpint_setpintype(struct gpio_dev_s *dev, - enum gpio_pintype_e pintype) -{ - struct espgpint_dev_s *espgpint = (struct espgpint_dev_s *)dev; - - DEBUGASSERT(espgpint != NULL); - DEBUGASSERT(espgpint->espgpio.id < BOARD_NGPIOINT); - gpioinfo("Setting pintype: %d\n", (int)pintype); - switch (pintype) - { - case GPIO_INTERRUPT_HIGH_PIN: - esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], - INPUT_PULLUP); - break; - case GPIO_INTERRUPT_LOW_PIN: - esp_configgpio(g_gpiointinputs[espgpint->espgpio.id], - INPUT_PULLDOWN); - break; - default: - return ERROR; - break; - } - - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_gpio_init - * - * Description: - * Configure the GPIO driver. - * - * Returned Value: - * Zero (OK). - * - ****************************************************************************/ - -int esp_gpio_init(void) -{ - int pincount = 0; - int i; - -#if BOARD_NGPIOOUT > 0 - for (i = 0; i < BOARD_NGPIOOUT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpout[i].gpio.gp_pintype = GPIO_OUTPUT_PIN; - g_gpout[i].gpio.gp_ops = &gpout_ops; - g_gpout[i].id = i; - gpio_pin_register(&g_gpout[i].gpio, pincount); - - /* Configure the pins that will be used as output */ - - esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_1 | INPUT_FUNCTION_1); - esp_gpiowrite(g_gpiooutputs[i], 0); - - pincount++; - } -#endif - -#if BOARD_NGPIOINT > 0 - for (i = 0; i < BOARD_NGPIOINT; i++) - { - /* Setup and register the GPIO pin */ - - g_gpint[i].espgpio.gpio.gp_pintype = GPIO_INTERRUPT_PIN; - g_gpint[i].espgpio.gpio.gp_ops = &gpint_ops; - g_gpint[i].espgpio.id = i; - gpio_pin_register(&g_gpint[i].espgpio.gpio, pincount); - - /* Configure the pins that will be used as interrupt input */ - - esp_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_1 | PULLDOWN); - - pincount++; - } -#endif - - return OK; -} -#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */ diff --git a/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_reset.c b/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_reset.c deleted file mode 100644 index 9bdf617ab6297..0000000000000 --- a/boards/risc-v/espressif/esp32c6-generic/src/esp32c6_reset.c +++ /dev/null @@ -1,81 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/esp32c6-generic/src/esp32c6_reset.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include "esp_systemreset.h" - -#ifdef CONFIG_BOARDCTL_RESET - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_reset - * - * Description: - * Reset board. Support for this function is required by board-level - * logic if CONFIG_BOARDCTL_RESET is selected. - * - * Input Parameters: - * status - Status information provided with the reset event. This - * meaning of this status information is board-specific. If not - * used by a board, the value zero may be provided in calls to - * board_reset(). - * - * Returned Value: - * If this function returns, then it was not possible to power-off the - * board due to some constraints. The return value in this case is a - * board-specific reason for the failure to shutdown. - * - ****************************************************************************/ - -int board_reset(int status) -{ - syslog(LOG_INFO, "reboot status=%d\n", status); - - switch (status) - { - case EXIT_SUCCESS: - up_shutdown_handler(); - break; - case CONFIG_BOARD_ASSERT_RESET_VALUE: - default: - break; - } - - up_systemreset(); - - return 0; -} - -#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/boards/risc-v/espressif/esp32h2-generic/Kconfig b/boards/risc-v/espressif/esp32h2-generic/Kconfig deleted file mode 100644 index 91a3b3330a4c0..0000000000000 --- a/boards/risc-v/espressif/esp32h2-generic/Kconfig +++ /dev/null @@ -1,8 +0,0 @@ -# -# For a description of the syntax of this configuration file, -# see the file kconfig-language.txt in the NuttX tools repository. -# - -if ARCH_BOARD_ESP32H2_GENERIC - -endif # ARCH_BOARD_ESP32H2_GENERIC diff --git a/boards/risc-v/espressif/esp32h2-generic/configs/buttons/defconfig b/boards/risc-v/espressif/esp32h2-generic/configs/buttons/defconfig deleted file mode 100644 index 3bbf7f8489446..0000000000000 --- a/boards/risc-v/espressif/esp32h2-generic/configs/buttons/defconfig +++ /dev/null @@ -1,52 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32h2-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32H2_GENERIC=y -CONFIG_ARCH_BUTTONS=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_IRQBUTTONS=y -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32H2=y -CONFIG_ESPRESSIF_GPIO_IRQ=y -CONFIG_EXAMPLES_BUTTONS=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INPUT=y -CONFIG_INPUT_BUTTONS=y -CONFIG_INPUT_BUTTONS_LOWER=y -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32h2-generic/configs/gpio/defconfig b/boards/risc-v/espressif/esp32h2-generic/configs/gpio/defconfig deleted file mode 100644 index 8183b29d4ee99..0000000000000 --- a/boards/risc-v/espressif/esp32h2-generic/configs/gpio/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32h2-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32H2_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_GPIO=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32H2=y -CONFIG_ESPRESSIF_GPIO_IRQ=y -CONFIG_EXAMPLES_GPIO=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32h2-generic/configs/nsh/defconfig b/boards/risc-v/espressif/esp32h2-generic/configs/nsh/defconfig deleted file mode 100644 index c06a765e64f13..0000000000000 --- a/boards/risc-v/espressif/esp32h2-generic/configs/nsh/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32h2-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32H2_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32H2=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32h2-generic/configs/pwm/defconfig b/boards/risc-v/espressif/esp32h2-generic/configs/pwm/defconfig deleted file mode 100644 index eb4aa244732eb..0000000000000 --- a/boards/risc-v/espressif/esp32h2-generic/configs/pwm/defconfig +++ /dev/null @@ -1,49 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32h2-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32H2_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32H2=y -CONFIG_ESPRESSIF_LEDC=y -CONFIG_ESPRESSIF_LEDC_TIMER0=y -CONFIG_EXAMPLES_PWM=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_FLOATINGPOINT=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32h2-generic/configs/random/defconfig b/boards/risc-v/espressif/esp32h2-generic/configs/random/defconfig deleted file mode 100644 index 55b4548abc2ec..0000000000000 --- a/boards/risc-v/espressif/esp32h2-generic/configs/random/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32h2-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32H2_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_URANDOM=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32H2=y -CONFIG_EXAMPLES_RANDOM=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=3 -CONFIG_START_YEAR=2023 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32h2-generic/configs/rtc/defconfig b/boards/risc-v/espressif/esp32h2-generic/configs/rtc/defconfig deleted file mode 100644 index d168b1fbfa47a..0000000000000 --- a/boards/risc-v/espressif/esp32h2-generic/configs/rtc/defconfig +++ /dev/null @@ -1,52 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32h2-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32H2_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32H2=y -CONFIG_EXAMPLES_ALARM=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_DISABLE_DATE=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_RTC=y -CONFIG_RTC_ALARM=y -CONFIG_RTC_DRIVER=y -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=5 -CONFIG_START_MONTH=4 -CONFIG_START_YEAR=2023 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32h2-generic/configs/tickless/defconfig b/boards/risc-v/espressif/esp32h2-generic/configs/tickless/defconfig deleted file mode 100644 index 30d4497642068..0000000000000 --- a/boards/risc-v/espressif/esp32h2-generic/configs/tickless/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32h2-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32H2_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32H2=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_TICKLESS=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_USEC_PER_TICK=10000 diff --git a/boards/risc-v/espressif/esp32h2-generic/configs/timers/defconfig b/boards/risc-v/espressif/esp32h2-generic/configs/timers/defconfig deleted file mode 100644 index afa1b573ca9c6..0000000000000 --- a/boards/risc-v/espressif/esp32h2-generic/configs/timers/defconfig +++ /dev/null @@ -1,50 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32h2-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32H2_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=1536 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32H2=y -CONFIG_EXAMPLES_ONESHOT=y -CONFIG_EXAMPLES_TIMER=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_ONESHOT=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=28 -CONFIG_START_MONTH=3 -CONFIG_START_YEAR=2023 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_TIMER=y -CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/risc-v/espressif/esp32h2-generic/configs/usbconsole/defconfig b/boards/risc-v/espressif/esp32h2-generic/configs/usbconsole/defconfig deleted file mode 100644 index d71ce19a275ea..0000000000000 --- a/boards/risc-v/espressif/esp32h2-generic/configs/usbconsole/defconfig +++ /dev/null @@ -1,47 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_ESPRESSIF_UART0 is not set -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32h2-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32H2_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARDCTL_RESET=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32H2=y -CONFIG_ESPRESSIF_USBSERIAL=y -CONFIG_EXAMPLES_HELLO=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y diff --git a/boards/risc-v/espressif/esp32h2-generic/configs/watchdog/defconfig b/boards/risc-v/espressif/esp32h2-generic/configs/watchdog/defconfig deleted file mode 100644 index 5b117394146bd..0000000000000 --- a/boards/risc-v/espressif/esp32h2-generic/configs/watchdog/defconfig +++ /dev/null @@ -1,48 +0,0 @@ -# -# This file is autogenerated: PLEASE DO NOT EDIT IT. -# -# You can use "make menuconfig" to make any modifications to the installed .config file. -# You can then do "make savedefconfig" to generate a new defconfig file that includes your -# modifications. -# -# CONFIG_NSH_ARGCAT is not set -# CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ARCH="risc-v" -CONFIG_ARCH_BOARD="esp32h2-generic" -CONFIG_ARCH_BOARD_COMMON=y -CONFIG_ARCH_BOARD_ESP32H2_GENERIC=y -CONFIG_ARCH_CHIP="espressif" -CONFIG_ARCH_CHIP_ESPRESSIF=y -CONFIG_ARCH_INTERRUPTSTACK=2048 -CONFIG_ARCH_RISCV=y -CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=15000 -CONFIG_BUILTIN=y -CONFIG_DEV_ZERO=y -CONFIG_ESPRESSIF_ESP32H2=y -CONFIG_EXAMPLES_WATCHDOG=y -CONFIG_FS_PROCFS=y -CONFIG_IDLETHREAD_STACKSIZE=2048 -CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y -CONFIG_LIBC_PERROR_STDOUT=y -CONFIG_LIBC_STRERROR=y -CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 -CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FILEIOSIZE=512 -CONFIG_NSH_READLINE=y -CONFIG_NSH_STRERROR=y -CONFIG_PREALLOC_TIMERS=0 -CONFIG_RR_INTERVAL=200 -CONFIG_SCHED_BACKTRACE=y -CONFIG_SCHED_WAITPID=y -CONFIG_START_DAY=29 -CONFIG_START_MONTH=11 -CONFIG_START_YEAR=2019 -CONFIG_SYSTEM_DUMPSTACK=y -CONFIG_SYSTEM_NSH=y -CONFIG_TESTING_GETPRIME=y -CONFIG_TESTING_OSTEST=y -CONFIG_UART0_SERIAL_CONSOLE=y -CONFIG_WATCHDOG=y diff --git a/boards/risc-v/espressif/esp32h2-generic/include/board.h b/boards/risc-v/espressif/esp32h2-generic/include/board.h deleted file mode 100644 index 338340dd14ce8..0000000000000 --- a/boards/risc-v/espressif/esp32h2-generic/include/board.h +++ /dev/null @@ -1,40 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/esp32h2-generic/include/board.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_RISCV_ESPRESSIF_ESP32H2_GENERIC_INCLUDE_BOARD_H -#define __BOARDS_RISCV_ESPRESSIF_ESP32H2_GENERIC_INCLUDE_BOARD_H - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* GPIO pins used by the GPIO Subsystem */ - -#define BOARD_NGPIOOUT 2 /* Amount of GPIO Output pins */ -#define BOARD_NGPIOINT 1 /* Amount of GPIO Input w/ Interruption pins */ - -/* ESP32H2-Generic GPIOs ****************************************************/ - -/* BOOT Button */ - -#define BUTTON_BOOT 9 - -#endif /* __BOARDS_RISCV_ESPRESSIF_ESP32H2_GENERIC_INCLUDE_BOARD_H */ - diff --git a/boards/risc-v/espressif/esp32h2-generic/scripts/Make.defs b/boards/risc-v/espressif/esp32h2-generic/scripts/Make.defs deleted file mode 100644 index 250aab7d1bb86..0000000000000 --- a/boards/risc-v/espressif/esp32h2-generic/scripts/Make.defs +++ /dev/null @@ -1,60 +0,0 @@ -############################################################################ -# boards/risc-v/espressif/esp32h2-generic/scripts/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -########################################################################### - -include $(TOPDIR)/.config -include $(TOPDIR)/tools/Config.mk -include $(TOPDIR)/tools/espressif/Config.mk -include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs - -# Remove quotes from CONFIG_ESPRESSIF_CHIP_SERIES configuration - -CHIP_SERIES = $(patsubst "%",%,$(CONFIG_ESPRESSIF_CHIP_SERIES)) - -# Pick the linker scripts from the board level if they exist, if not -# pick the common linker scripts. - -ARCHSCRIPT += $(BOARD_COMMON_DIR)/scripts/$(CHIP_SERIES)_aliases.ld - -ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_flat_memory.ld) -ARCHSCRIPT += $(call FINDSCRIPT,$(CHIP_SERIES)_legacy_sections.ld) - -ARCHPICFLAGS = -fpic - -CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -Werror=return-type -Werror -CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) -CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -# Loadable module definitions - -CMODULEFLAGS = $(CFLAGS) - -LDMODULEFLAGS = -melf32lriscv -r -e module_initialize -LDMODULEFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/libs/libc/modlib/gnu-elf.ld) - -# ELF module definitions - -CELFFLAGS = $(CFLAGS) -CXXELFFLAGS = $(CXXFLAGS) - -LDELFFLAGS = -melf32lriscv -r -e main -LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/binfmt/libelf/gnu-elf.ld) diff --git a/boards/risc-v/espressif/esp32h2-generic/src/Make.defs b/boards/risc-v/espressif/esp32h2-generic/src/Make.defs deleted file mode 100644 index 4267506a2e8ea..0000000000000 --- a/boards/risc-v/espressif/esp32h2-generic/src/Make.defs +++ /dev/null @@ -1,43 +0,0 @@ -############################################################################# -# boards/risc-v/espressif/esp32h2-generic/src/Make.defs -# -# Licensed to the Apache Software Foundation (ASF) under one or more -# contributor license agreements. See the NOTICE file distributed with -# this work for additional information regarding copyright ownership. The -# ASF licenses this file to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance with the -# License. You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the -# License for the specific language governing permissions and limitations -# under the License. -# -############################################################################# - -include $(TOPDIR)/Make.defs - -CSRCS = esp32h2_boot.c esp32h2_bringup.c - -ifeq ($(CONFIG_BOARDCTL),y) - CSRCS += esp32h2_appinit.c - - ifeq ($(CONFIG_BOARDCTL_RESET),y) - CSRCS += esp32h2_reset.c - endif -endif - -ifeq ($(CONFIG_DEV_GPIO),y) - CSRCS += esp32h2_gpio.c -endif - -ifeq ($(CONFIG_ARCH_BUTTONS),y) - CSRCS += esp32h2_buttons.c -endif - -DEPPATH += --dep-path board -VPATH += :board -CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board diff --git a/boards/risc-v/espressif/esp32h2-generic/src/esp32h2-generic.h b/boards/risc-v/espressif/esp32h2-generic/src/esp32h2-generic.h deleted file mode 100644 index 4afa8f622a2a7..0000000000000 --- a/boards/risc-v/espressif/esp32h2-generic/src/esp32h2-generic.h +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/esp32h2-generic/src/esp32h2-generic.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_RISCV_ESPRESSIF_ESP32H2_GENERIC_SRC_ESP32H2_GENERIC_H -#define __BOARDS_RISCV_ESPRESSIF_ESP32H2_GENERIC_SRC_ESP32H2_GENERIC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_bringup - * - * Description: - * Perform architecture-specific initialization. - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y : - * Called from the NSH library via board_app_initialize(). - * - * Input Parameters: - * None. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. - * - ****************************************************************************/ - -int esp_bringup(void); - -/**************************************************************************** - * Name: esp_gpio_init - * - * Description: - * Configure the GPIO driver. - * - * Returned Value: - * Zero (OK). - * - ****************************************************************************/ - -#ifdef CONFIG_DEV_GPIO -int esp_gpio_init(void); -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __BOARDS_RISCV_ESPRESSIF_ESP32H2_GENERIC_SRC_ESP32H2_GENERIC_H */ diff --git a/boards/risc-v/espressif/esp32h2-generic/src/esp32h2_bringup.c b/boards/risc-v/espressif/esp32h2-generic/src/esp32h2_bringup.c deleted file mode 100644 index 3fc9ca542a999..0000000000000 --- a/boards/risc-v/espressif/esp32h2-generic/src/esp32h2_bringup.c +++ /dev/null @@ -1,192 +0,0 @@ -/**************************************************************************** - * boards/risc-v/espressif/esp32h2-generic/src/esp32h2_bringup.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include - -#include - -#include "esp_board_ledc.h" - -#ifdef CONFIG_WATCHDOG -# include "esp_wdt.h" -#endif - -#ifdef CONFIG_TIMER -# include "esp_timer.h" -#endif - -#ifdef CONFIG_ONESHOT -# include "esp_oneshot.h" -#endif - -#ifdef CONFIG_RTC_DRIVER -# include "esp_rtc.h" -#endif - -#ifdef CONFIG_DEV_GPIO -# include "esp_gpio.h" -#endif - -#ifdef CONFIG_INPUT_BUTTONS -# include -#endif - -#include "esp32h2-generic.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_bringup - * - * Description: - * Perform architecture-specific initialization. - * - * CONFIG_BOARD_LATE_INITIALIZE=y : - * Called from board_late_initialize(). - * - * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y : - * Called from the NSH library via board_app_initialize(). - * - * Input Parameters: - * None. - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. - * - ****************************************************************************/ - -int esp_bringup(void) -{ - int ret = OK; - -#ifdef CONFIG_FS_PROCFS - /* Mount the procfs file system */ - - ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); - if (ret < 0) - { - _err("Failed to mount procfs at /proc: %d\n", ret); - } -#endif - -#ifdef CONFIG_FS_TMPFS - /* Mount the tmpfs file system */ - - ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); - if (ret < 0) - { - _err("Failed to mount tmpfs at %s: %d\n", CONFIG_LIBC_TMPDIR, ret); - } -#endif - -#ifdef CONFIG_WATCHDOG - ret = esp_wdt_initialize(); - if (ret < 0) - { - _err("Failed to initialize WDT: %d\n", ret); - } -#endif - -#ifdef CONFIG_TIMER - ret = esp_timer_initialize(0); - if (ret < 0) - { - _err("Failed to initialize Timer 0: %d\n", ret); - } - -#ifndef CONFIG_ONESHOT - ret = esp_timer_initialize(1); - if (ret < 0) - { - _err("Failed to initialize Timer 1: %d\n", ret); - } -#endif -#endif - -#ifdef CONFIG_ONESHOT - ret = esp_oneshot_initialize(); - if (ret < 0) - { - _err("Failed to initialize Oneshot Timer: %d\n", ret); - } -#endif - -#ifdef CONFIG_RTC_DRIVER - /* Initialize the RTC driver */ - - ret = esp_rtc_driverinit(); - if (ret < 0) - { - _err("Failed to initialize the RTC driver: %d\n", ret); - } -#endif - -#ifdef CONFIG_DEV_GPIO - ret = esp_gpio_init(); - if (ret < 0) - { - ierr("Failed to initialize GPIO Driver: %d\n", ret); - } -#endif - -#if defined(CONFIG_INPUT_BUTTONS) && defined(CONFIG_INPUT_BUTTONS_LOWER) - /* Register the BUTTON driver */ - - ret = btn_lower_initialize("/dev/buttons"); - if (ret < 0) - { - ierr("ERROR: btn_lower_initialize() failed: %d\n", ret); - } -#endif - -#ifdef CONFIG_ESPRESSIF_LEDC - ret = board_ledc_setup(); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: board_ledc_setup() failed: %d\n", ret); - } -#endif /* CONFIG_ESPRESSIF_LEDC */ - - /* If we got here then perhaps not all initialization was successful, but - * at least enough succeeded to bring-up NSH with perhaps reduced - * capabilities. - */ - - return ret; -} diff --git a/boards/risc-v/fe310/hifive1-revb/configs/nsh/defconfig b/boards/risc-v/fe310/hifive1-revb/configs/nsh/defconfig index e52d30801aaa1..cc9493dc9100d 100644 --- a/boards/risc-v/fe310/hifive1-revb/configs/nsh/defconfig +++ b/boards/risc-v/fe310/hifive1-revb/configs/nsh/defconfig @@ -20,7 +20,6 @@ # CONFIG_NSH_DISABLE_CAT is not set # CONFIG_NSH_DISABLE_ECHO is not set # CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_HELP is not set # CONFIG_NSH_DISABLE_KILL is not set # CONFIG_NSH_DISABLE_LOSMART is not set # CONFIG_NSH_DISABLE_LS is not set diff --git a/boards/risc-v/hpm6000/hpm6360evk/CMakeLists.txt b/boards/risc-v/hpm6000/hpm6360evk/CMakeLists.txt new file mode 100644 index 0000000000000..b7a67c0d2b74e --- /dev/null +++ b/boards/risc-v/hpm6000/hpm6360evk/CMakeLists.txt @@ -0,0 +1,21 @@ +# ############################################################################## +# boards/risc-v/hpm6000/hpm6360evk/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/risc-v/hpm6000/hpm6360evk/Kconfig b/boards/risc-v/hpm6000/hpm6360evk/Kconfig new file mode 100644 index 0000000000000..e78989271d37d --- /dev/null +++ b/boards/risc-v/hpm6000/hpm6360evk/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see misc/tools/kconfig-language.txt. +# + +if ARCH_BOARD_HPM6360EVK + +endif diff --git a/boards/risc-v/hpm6000/hpm6360evk/README.txt b/boards/risc-v/hpm6000/hpm6360evk/README.txt new file mode 100644 index 0000000000000..7ef9d1b9e8de6 --- /dev/null +++ b/boards/risc-v/hpm6000/hpm6360evk/README.txt @@ -0,0 +1,42 @@ +1. Download and install toolchain + + $ curl https://github.com/hpmicro/riscv-gnu-toolchain/releases/tag/2022.05.15 + +2. Download and install openocd + + Download hpmicro sdk_env, openocd in the path: sdk_env/tools/openocd + +3. Configure and build NuttX + + $ mkdir ./nuttxspace + $ cd ./nuttxspace + $ git clone https://github.com/apache/nuttx.git nuttx + $ git clone https://github.com/apache/nuttx-apps.git apps + $ cd nuttx + $ make distclean + $ ./tools/configure.sh hpm6750evk2:nsh + $ make menuconfig + $ make V=1 + + Note: make menuconfig to config toolchain + ================== + To switch GNU riscv64 toolchain to GNU riscv32 toolchain, the following option must be selected: + + System Type ---> + Toolchain Selection ---> + [ ] Generic GNU RV64 toolchain + [x] Generic GNU RV32 toolchain + + Make sure HPMicro GNU riscv32 toolchain have been installed and be found in PATH. + +4. Debug the nuttx with openocd and run + + $ picocom -b 115200 /dev/ttyACM0 + + When using fireDAP, command as follows. Those cfg files in the path: sdk_env/hpm_sdk/boards/openocd. + $ openocd -f probes/cmsis_dap.cfg -f soc/hpm6750-single-core.cfg -f boards/hpm6750evk2.cfg + + $ riscv32-unknown-elf-gdb ./nuttx + (gdb) target extended-remote [ip_addr]:3333 + (gdb) load + (gdb) c diff --git a/boards/risc-v/hpm6000/hpm6360evk/configs/nsh/defconfig b/boards/risc-v/hpm6000/hpm6360evk/configs/nsh/defconfig new file mode 100644 index 0000000000000..ede6f76f17ca8 --- /dev/null +++ b/boards/risc-v/hpm6000/hpm6360evk/configs/nsh/defconfig @@ -0,0 +1,80 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_ENVIRON is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_FS_PROCFS_EXCLUDE_BLOCKS is not set +# CONFIG_FS_PROCFS_EXCLUDE_ENVIRON is not set +# CONFIG_FS_PROCFS_EXCLUDE_MEMDUMP is not set +# CONFIG_FS_PROCFS_EXCLUDE_MEMINFO is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNT is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_USAGE is not set +# CONFIG_FS_PROCFS_EXCLUDE_VERSION is not set +# CONFIG_NSH_DISABLEBG is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_ENV is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_PRINTF is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_STANDARD_SERIAL is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="hpm6360evk" +CONFIG_ARCH_BOARD_HPM6360EVK=y +CONFIG_ARCH_CHIP="hpm6000" +CONFIG_ARCH_CHIP_HPM6000=y +CONFIG_ARCH_CHIP_HPM6360IPA=y +CONFIG_ARCH_INTERRUPTSTACK=8192 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=10000 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEFAULT_SMALL=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_BINFS=y +CONFIG_FS_PROCFS=y +CONFIG_HPM_UART0=y +CONFIG_IDLETHREAD_STACKSIZE=8192 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=8192 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=64 +CONFIG_NSH_STRERROR=y +CONFIG_RAM_SIZE=262144 +CONFIG_RAM_START=0x00080000 +CONFIG_RISCV_TOOLCHAIN_GNU_RV32=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_TERMIOS=y +CONFIG_START_DAY=7 +CONFIG_START_MONTH=2 +CONFIG_START_YEAR=2023 +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/risc-v/hpm6000/hpm6360evk/include/board.h b/boards/risc-v/hpm6000/hpm6360evk/include/board.h new file mode 100644 index 0000000000000..7eb8371a89d46 --- /dev/null +++ b/boards/risc-v/hpm6000/hpm6360evk/include/board.h @@ -0,0 +1,135 @@ +/**************************************************************************** + * boards/risc-v/hpm6000/hpm6360evk/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_HPM6000_HPM6360EVK_INCLUDE_BOARD_H +#define __BOARDS_RISCV_HPM6000_HPM6360EVK_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LED definitions **********************************************************/ + +/* There are four LED status indicators located on the EVK Board. + * The functions of these LEDs include: + * + * - Main Power Supply(D3) + * Green: DC 5V main supply is normal. + * Red: J2 input voltage is over 5.6V. + * Off: The board is not powered. + * - Reset RED LED(D15) + * - OpenSDA LED(D16) + * - USER LED(D18) + * + * Only a single LED, D18, is under software control. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_USERLED 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_USERLED_BIT (1 << BOARD_USERLED) + +/* This LED is not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/imxrt_autoleds.c. The LED is used to encode + * OS-related events as follows: + * + * -------------------- ----------------------------- ------ + * SYMBOL Meaning LED + * -------------------- ----------------------------- ------ + */ + +#define LED_STARTED 0 /* NuttX has been started OFF */ +#define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF */ +#define LED_STACKCREATED 1 /* Idle stack created ON */ +#define LED_INIRQ 2 /* In an interrupt N/C */ +#define LED_SIGNAL 2 /* In a signal handler N/C */ +#define LED_ASSERTION 2 /* An assertion failed N/C */ +#define LED_PANIC 3 /* The system has crashed FLASH */ +#undef LED_IDLE /* Not used */ + +/* Thus if the LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If the LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/* Button definitions *******************************************************/ + +/* The IMXRT board has one external user button + * + * 1. SW8 (IRQ88) GPIO5-00 + */ + +#define BUTTON_SW8 0 +#define NUM_BUTTONS 3 + +#define BUTTON_SW8_BIT (1 << BUTTON_SW8) + +/* UARTs */ + +#define GPIO_UART0_RXD (GPIO_UART0_RXD4 | IOC_PAD_UART_DEFAULT) +#define GPIO_UART0_TXD (GPIO_UART0_TXD4 | IOC_PAD_UART_DEFAULT) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: hpm6340_boardinitialize + ****************************************************************************/ + +void hpm6360_boardinitialize(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_RISCV_HPM6000_HPM6360EVK_INCLUDE_BOARD_H */ diff --git a/boards/risc-v/hpm6000/hpm6360evk/scripts/Make.defs b/boards/risc-v/hpm6000/hpm6360evk/scripts/Make.defs new file mode 100644 index 0000000000000..a57179aa6ff7f --- /dev/null +++ b/boards/risc-v/hpm6000/hpm6360evk/scripts/Make.defs @@ -0,0 +1,34 @@ +############################################################################ +# boards/risc-v/hpm6000/hpm6360evk/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs + +LDSCRIPT = ld.script + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS += $(CFLAGS) -D__ASSEMBLY__ diff --git a/boards/risc-v/hpm6000/hpm6360evk/scripts/flash.script b/boards/risc-v/hpm6000/hpm6360evk/scripts/flash.script new file mode 100644 index 0000000000000..25f8fd8aff055 --- /dev/null +++ b/boards/risc-v/hpm6000/hpm6360evk/scripts/flash.script @@ -0,0 +1,108 @@ +/**************************************************************************** + * boards/risc-v/hpm6000/hpm6360evk/scripts/ld.script + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + flash (rx) : ORIGIN = 0x80000000, LENGTH = 16M + ilm (rx) : ORIGIN = 0x00000000, LENGTH = 128K + dlm (rwx) : ORIGIN = 0x00080000, LENGTH = 128K + axi_sram (wx) : ORIGIN = 0x01080000, LENGTH = 256K + axi_sram_noncacheable (wx) : ORIGIN = 0x010C0000, LENGTH = 256K + ahb_sram (w) : ORIGIN = 0xF0300000, LENGTH = 32k +} + +OUTPUT_ARCH("riscv") + +EXTERN(_vectors) +SECTIONS +{ + .nor_cfg_option 0x80000400: { + KEEP(*(.nor_cfg_option)) + } > flash + + .boot_header 0x80001000 : { + __boot_header_start__ = .; + KEEP(*(.boot_header)) + KEEP(*(.fw_info_table)) + KEEP(*(.dc_info)) + __boot_header_end__ = .; + } > flash + + .text 0x80003000 : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > flash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.d.*) + *(.gnu.linkonce.s.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > dlm AT > flash + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.sbss .sbss.*) + *(.gnu.linkonce.b.*) + *(.gnu.linkonce.sb.*) + *(COMMON) + . = ALIGN(32); + _ebss = ABSOLUTE(.); + } > dlm + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/risc-v/hpm6000/hpm6360evk/scripts/ld.script b/boards/risc-v/hpm6000/hpm6360evk/scripts/ld.script new file mode 100644 index 0000000000000..6f3d8d1a3b81a --- /dev/null +++ b/boards/risc-v/hpm6000/hpm6360evk/scripts/ld.script @@ -0,0 +1,95 @@ +/**************************************************************************** + * boards/risc-v/hpm6750/hpm6750evk2/scripts/ld.script + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + ilm (rx) : ORIGIN = 0x00000000, LENGTH = 128K + dlm (rwx) : ORIGIN = 0x00080000, LENGTH = 128K + axi_sram (wx) : ORIGIN = 0x01080000, LENGTH = 256K + axi_sram_noncacheable (wx) : ORIGIN = 0x010C0000, LENGTH = 256K + ahb_sram (w) : ORIGIN = 0xF0300000, LENGTH = 32k +} + +OUTPUT_ARCH("riscv") + +EXTERN(_vectors) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > ilm + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(.init_array .init_array.*)) + _einit = ABSOLUTE(.); + } > ilm + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.d.*) + *(.gnu.linkonce.s.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > dlm AT > ilm + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.sbss .sbss.*) + *(.gnu.linkonce.b.*) + *(.gnu.linkonce.sb.*) + *(COMMON) + . = ALIGN(32); + _ebss = ABSOLUTE(.); + } > dlm + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/risc-v/hpm6000/hpm6360evk/src/CMakeLists.txt b/boards/risc-v/hpm6000/hpm6360evk/src/CMakeLists.txt new file mode 100644 index 0000000000000..ce9c6a3067f9c --- /dev/null +++ b/boards/risc-v/hpm6000/hpm6360evk/src/CMakeLists.txt @@ -0,0 +1,37 @@ +# ############################################################################## +# boards/risc-v/hpm6000/hpm6360evk/src/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS hpm6360_bringup.c hpm6360_boot.c hpm6360_appinit.c) + +if(CONFIG_BOARDCTL) + if(EXISTS hpm6360_appinit.c) + list(APPEND SRCS hpm6360_appinit.c) + endif() +endif() + +if(CONFIG_ARCH_LEDS) + list(APPEND SRCS hpm6360_autoleds.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set(LDFILE ld.script) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/${LDFILE}") diff --git a/boards/risc-v/hpm6000/hpm6360evk/src/Makefile b/boards/risc-v/hpm6000/hpm6360evk/src/Makefile new file mode 100644 index 0000000000000..0ed94a7ed74ac --- /dev/null +++ b/boards/risc-v/hpm6000/hpm6360evk/src/Makefile @@ -0,0 +1,33 @@ +############################################################################ +# boards/risc-v/hpm6000/hpm6360evk/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = hpm6360_bringup.c hpm6360_boot.c + +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += hpm6360_appinit.c +endif + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += hpm6360_autoleds.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_appinit.c b/boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_appinit.c new file mode 100644 index 0000000000000..dfad6aed9e6a6 --- /dev/null +++ b/boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_appinit.c @@ -0,0 +1,74 @@ +/**************************************************************************** + * boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "hpm6360evk.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform architecture specific initialization + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + + return hpm6360_bringup(); +#endif +} diff --git a/boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_autoleds.c b/boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_autoleds.c new file mode 100644 index 0000000000000..95dca5dbc04ff --- /dev/null +++ b/boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_autoleds.c @@ -0,0 +1,165 @@ +/**************************************************************************** + * boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_autoleds.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* There are four LED status indicators located on the EVK Board. The + * functions of these LEDs include: + * + * - Main Power Supply(D3) + * Green: DC 5V main supply is normal. + * Red: J2 input voltage is over 5.6V. + * Off: The board is not powered. + * - Reset RED LED(D21) + * - OpenSDA LED(D20) + * - USER LED(D18) + * + * Only a single LED, D18, is under software control. + * + * This LED is not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the usage by the board port is defined in + * include/board.h and src/imxrt_autoleds.c. The LED is used to encode + * OS-related events as follows: + * + * -------------------- ----------------------- ------ + * SYMBOL Meaning LED + * -------------------- ----------------------- ------ + * + * LED_STARTED 0 NuttX has been started OFF + * LED_HEAPALLOCATE 0 Heap has been allocated OFF + * LED_IRQSENABLED 0 Interrupts enabled OFF + * LED_STACKCREATED 1 Idle stack created ON + * LED_INIRQ 2 In an interrupt N/C + * LED_SIGNAL 2 In a signal handler N/C + * LED_ASSERTION 2 An assertion failed N/C + * LED_PANIC 3 The system has crashed FLASH + * LED_IDLE Not used + * + * Thus if the LED is statically on, NuttX has successfully booted and is, + * apparently, running normally. If the LED is flashing at approximately + * 2Hz, then a fatal error has been detected and the system has halted. + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "hpm_gpio.h" +#include "hpm_iomux.h" +#include +#include "hpm6360evk.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imxrt_autoled_initialize + * + * Description: + * Initialize NuttX-controlled LED logic + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void hpm6360_autoled_initialize(void) +{ + /* Configure LED GPIO for output */ + + hpm_gpio_config(GPIO_LED); +} + +/**************************************************************************** + * Name: board_autoled_on + * + * Description: + * Turn on the "logical" LED state + * + * Input Parameters: + * led - Identifies the "logical" LED state (see definitions in + * include/board.h) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void board_autoled_on(int led) +{ + bool ledoff = false; + + switch (led) + { + case 0: /* LED Off */ + ledoff = true; + break; + + case 2: /* LED No change */ + return; + + case 1: /* LED On */ + case 3: /* LED On */ + break; + } + + hpm_gpio_write(GPIO_LED, ledoff); /* Low illuminates */ +} + +/**************************************************************************** + * Name: board_autoled_off + * + * Description: + * Turn off the "logical" LED state + * + * Input Parameters: + * led - Identifies the "logical" LED state (see definitions in + * include/board.h) + * + * Returned Value: + * None + * + ****************************************************************************/ + +void board_autoled_off(int led) +{ + switch (led) + { + case 0: /* LED Off */ + case 1: /* LED Off */ + case 3: /* LED Off */ + break; + + case 2: /* LED No change */ + return; + } + + hpm_gpio_write(GPIO_LED, true); /* Low illuminates */ +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_boot.c b/boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_boot.c new file mode 100644 index 0000000000000..b3f14f88759f8 --- /dev/null +++ b/boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_boot.c @@ -0,0 +1,64 @@ +/**************************************************************************** + * boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_boot.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "hpm6360evk.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: hpm6340_boardinitialize + * + * Description: + * All FE310 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void hpm6360_boardinitialize(void) +{ + /* Configure on-board LEDs if LED support has been selected. */ + +#ifdef CONFIG_ARCH_LEDS + hpm6360_autoled_initialize(); +#endif +} diff --git a/boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_bringup.c b/boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_bringup.c new file mode 100644 index 0000000000000..9f6a44f0cd73f --- /dev/null +++ b/boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_bringup.c @@ -0,0 +1,67 @@ +/**************************************************************************** + * boards/risc-v/hpm6000/hpm6360evk/src/hpm6360_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: hpm6750_bringup + ****************************************************************************/ + +int hpm6360_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_FS_BINFS + /* Mount the binfs file system */ + + ret = nx_mount(NULL, "/bin", "binfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount binfs at /bin: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + serr("ERROR: Failed to mount procfs at %s: %d\n", "/proc", ret); + } +#endif + + return ret; +} diff --git a/boards/risc-v/hpm6000/hpm6360evk/src/hpm6360evk.h b/boards/risc-v/hpm6000/hpm6360evk/src/hpm6360evk.h new file mode 100644 index 0000000000000..7ba51655a6b55 --- /dev/null +++ b/boards/risc-v/hpm6000/hpm6360evk/src/hpm6360evk.h @@ -0,0 +1,78 @@ +/**************************************************************************** + * boards/risc-v/hpm6000/hpm6360evk/src/hpm6360evk.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISCV_HPM6000_HPM6360EVK_SRC_HPM6360EVK_H +#define __BOARDS_RISCV_HPM6000_HPM6360EVK_SRC_HPM6360EVK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "hpm_gpio.h" +#include "hpm_iomux.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* GPIO Pin Definitions *****************************************************/ + +/* LEDs */ + +/* There are four LED status indicators located on the EVK Board. + * The functions of these LEDs include: + * + * - Main Power Supply(D3) + * Green: DC 5V main supply is normal. + * Red: J2 input voltage is over 5.6V. + * Off: The board is not powered. + * - Reset RED LED(D15) + * - OpenSDA LED(D16) + * - USER LED(D18) + * + * Only a single LED, D18, is under software control. + */ + +#define GPIO_LED (GPIO_OUTPUT | GPIO_OUTPUT_ZERO | GPIO_PORTA | GPIO_PIN7) /* PA07 */ + +#define LED_DRIVER_PATH "/dev/userleds" + +int hpm6360_bringup(void); + +/**************************************************************************** + * Name: imxrt_autoled_initialize + * + * Description: + * Initialize NuttX-controlled LED logic + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void hpm6360_autoled_initialize(void); +#endif + +#endif /* __BOARDS_RISCV_HPM6000_HPM6360EVK_SRC_HPM6360EVK_H */ diff --git a/boards/risc-v/hpm6750/hpm6750evk2/configs/nsh/defconfig b/boards/risc-v/hpm6750/hpm6750evk2/configs/nsh/defconfig index f2ba149e9ed7f..0379b4666e569 100644 --- a/boards/risc-v/hpm6750/hpm6750evk2/configs/nsh/defconfig +++ b/boards/risc-v/hpm6750/hpm6750evk2/configs/nsh/defconfig @@ -24,7 +24,6 @@ # CONFIG_NSH_DISABLE_ENV is not set # CONFIG_NSH_DISABLE_EXEC is not set # CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_HELP is not set # CONFIG_NSH_DISABLE_KILL is not set # CONFIG_NSH_DISABLE_LOSMART is not set # CONFIG_NSH_DISABLE_LS is not set diff --git a/boards/risc-v/jh7110/star64/scripts/ld.script b/boards/risc-v/jh7110/star64/scripts/ld.script index 2bb18a56635bd..4d9190a9377aa 100644 --- a/boards/risc-v/jh7110/star64/scripts/ld.script +++ b/boards/risc-v/jh7110/star64/scripts/ld.script @@ -116,6 +116,7 @@ SECTIONS *(.sbss.*) *(.gnu.linkonce.b*) *(COMMON) + . = ALIGN(32); _ebss = . ; } > ksram diff --git a/boards/risc-v/k210/maix-bit/scripts/ld.script b/boards/risc-v/k210/maix-bit/scripts/ld.script index 44370ae567ce4..282206762d370 100644 --- a/boards/risc-v/k210/maix-bit/scripts/ld.script +++ b/boards/risc-v/k210/maix-bit/scripts/ld.script @@ -81,7 +81,7 @@ SECTIONS *(.gnu.linkonce.b.*) *(.gnu.linkonce.sb.*) *(COMMON) - . = ALIGN(8); + . = ALIGN(32); _ebss = ABSOLUTE(.); } > sram diff --git a/boards/risc-v/k210/maix-bit/scripts/user-space.ld b/boards/risc-v/k210/maix-bit/scripts/user-space.ld index d51266a3a6e10..206b7e5beb5dd 100644 --- a/boards/risc-v/k210/maix-bit/scripts/user-space.ld +++ b/boards/risc-v/k210/maix-bit/scripts/user-space.ld @@ -75,7 +75,7 @@ SECTIONS *(.sbss .sbss.*) *(.gnu.linkonce.b.*) *(COMMON) - . = ALIGN(8); + . = ALIGN(32); _ebss = ABSOLUTE(.); } > usram diff --git a/boards/risc-v/k230/canmv230/CMakeLists.txt b/boards/risc-v/k230/canmv230/CMakeLists.txt new file mode 100644 index 0000000000000..66e5edf33a0ca --- /dev/null +++ b/boards/risc-v/k230/canmv230/CMakeLists.txt @@ -0,0 +1,21 @@ +# ############################################################################## +# boards/risc-v/k230/canmv230/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/risc-v/k230/canmv230/configs/knsh/defconfig b/boards/risc-v/k230/canmv230/configs/knsh/defconfig new file mode 100644 index 0000000000000..88b6579618da9 --- /dev/null +++ b/boards/risc-v/k230/canmv230/configs/knsh/defconfig @@ -0,0 +1,92 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_16550_ADDRWIDTH=0 +CONFIG_16550_REGWIDTH=32 +CONFIG_16550_SERIAL_DISABLE_REORDERING=y +CONFIG_16550_SUPRESS_CONFIG=y +CONFIG_16550_UART0=y +CONFIG_16550_UART0_BASE=0x91400000 +CONFIG_16550_UART0_CLOCK=50000000 +CONFIG_16550_UART0_IRQ=41 +CONFIG_16550_UART0_SERIAL_CONSOLE=y +CONFIG_16550_UART=y +CONFIG_16550_WAIT_LCR=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_ADDRENV=y +CONFIG_ARCH_BOARD="canmv230" +CONFIG_ARCH_BOARD_K230_CANMV=y +CONFIG_ARCH_CHIP="k230" +CONFIG_ARCH_CHIP_K230=y +CONFIG_ARCH_DATA_NPAGES=128 +CONFIG_ARCH_DATA_VBASE=0xC0100000 +CONFIG_ARCH_HEAP_NPAGES=128 +CONFIG_ARCH_HEAP_VBASE=0xC0200000 +CONFIG_ARCH_INTERRUPTSTACK=3072 +CONFIG_ARCH_KERNEL_STACKSIZE=3072 +CONFIG_ARCH_PGPOOL_MAPPING=y +CONFIG_ARCH_PGPOOL_PBASE=0x8600000 +CONFIG_ARCH_PGPOOL_SIZE=10485760 +CONFIG_ARCH_PGPOOL_VBASE=0x8600000 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_TEXT_NPAGES=128 +CONFIG_ARCH_TEXT_VBASE=0xC0000000 +CONFIG_ARCH_USE_MMU=y +CONFIG_ARCH_USE_MPU=y +CONFIG_ARCH_USE_S_MODE=y +CONFIG_BINFMT_ELF_EXECUTABLE=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=53291 +CONFIG_BUILD_KERNEL=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEV_ZERO=y +CONFIG_ELF=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_FILEPATH="/system/bin/init" +CONFIG_INIT_MOUNT=y +CONFIG_INIT_MOUNT_FLAGS=0x1 +CONFIG_INIT_MOUNT_TARGET="/system/bin" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y +CONFIG_MEMSET_64BIT=y +CONFIG_MEMSET_OPTSPEED=y +CONFIG_MM_PGALLOC=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PATH_INITIAL="/system/bin" +CONFIG_RAM_SIZE=16777216 +CONFIG_RAM_START=0x8200000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_UART_ARCH_MMIO=y +CONFIG_STACK_COLORATION=y +CONFIG_STANDARD_SERIAL=y +CONFIG_START_DAY=17 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2023 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_PROGNAME="init" +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/risc-v/k230/canmv230/configs/master/defconfig b/boards/risc-v/k230/canmv230/configs/master/defconfig new file mode 100644 index 0000000000000..9df94e26f27f2 --- /dev/null +++ b/boards/risc-v/k230/canmv230/configs/master/defconfig @@ -0,0 +1,109 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_16550_ADDRWIDTH=0 +CONFIG_16550_REGWIDTH=32 +CONFIG_16550_SERIAL_DISABLE_REORDERING=y +CONFIG_16550_SUPRESS_CONFIG=y +CONFIG_16550_UART0=y +CONFIG_16550_UART0_BASE=0x91400000 +CONFIG_16550_UART0_CLOCK=50000000 +CONFIG_16550_UART0_IRQ=41 +CONFIG_16550_UART0_SERIAL_CONSOLE=y +CONFIG_16550_UART=y +CONFIG_16550_WAIT_LCR=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_ADDRENV=y +CONFIG_ARCH_BOARD="canmv230" +CONFIG_ARCH_BOARD_K230_CANMV=y +CONFIG_ARCH_CHIP="k230" +CONFIG_ARCH_CHIP_K230=y +CONFIG_ARCH_DATA_NPAGES=128 +CONFIG_ARCH_DATA_VBASE=0xC0100000 +CONFIG_ARCH_HEAP_NPAGES=128 +CONFIG_ARCH_HEAP_VBASE=0xC0200000 +CONFIG_ARCH_INTERRUPTSTACK=3072 +CONFIG_ARCH_KERNEL_STACKSIZE=3072 +CONFIG_ARCH_PGPOOL_MAPPING=y +CONFIG_ARCH_PGPOOL_PBASE=0x8200000 +CONFIG_ARCH_PGPOOL_SIZE=14680064 +CONFIG_ARCH_PGPOOL_VBASE=0x8200000 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_TEXT_NPAGES=128 +CONFIG_ARCH_TEXT_VBASE=0xC0000000 +CONFIG_ARCH_USE_MMU=y +CONFIG_ARCH_USE_MPU=y +CONFIG_ARCH_USE_S_MODE=y +CONFIG_BINFMT_ELF_EXECUTABLE=y +CONFIG_BLK_RPMSG_SERVER=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=53291 +CONFIG_BUILD_KERNEL=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEV_RPMSG_SERVER=y +CONFIG_DEV_SIMPLE_ADDRENV=y +CONFIG_DEV_ZERO=y +CONFIG_ELF=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_FS_RPMSGFS_SERVER=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_FILEPATH="/system/bin/init" +CONFIG_INIT_MOUNT=y +CONFIG_INIT_MOUNT_FLAGS=0x1 +CONFIG_INIT_MOUNT_TARGET="/system/bin" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_K230_RPTUN_MASTER=y +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBC_HOSTNAME="master" +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y +CONFIG_MEMSET_64BIT=y +CONFIG_MEMSET_OPTSPEED=y +CONFIG_MM_PGALLOC=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_PROMPT_STRING="" +CONFIG_NSH_READLINE=y +CONFIG_NUTTSBI=y +CONFIG_NUTTSBI_IPI_BASE=0xf04000000 +CONFIG_NUTTSBI_MTIMECMP_BASE=0xf04004000 +CONFIG_NUTTSBI_MTIME_BASE=0xf0400bff8 +CONFIG_PATH_INITIAL="/system/bin" +CONFIG_RAM_SIZE=16777216 +CONFIG_RAM_START=0x8000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RPMSG_PING=y +CONFIG_RPMSG_UART=y +CONFIG_RPTUN=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_UART_ARCH_MMIO=y +CONFIG_STACK_COLORATION=y +CONFIG_STANDARD_SERIAL=y +CONFIG_START_DAY=10 +CONFIG_START_MONTH=2 +CONFIG_START_YEAR=2024 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSLOG_RPMSG_SERVER=y +CONFIG_SYSTEM_CUTERM=y +CONFIG_SYSTEM_CUTERM_DEFAULT_DEVICE="/dev/ttyRpmsg" +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_PROGNAME="init" +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/risc-v/k230/canmv230/configs/nsbi/defconfig b/boards/risc-v/k230/canmv230/configs/nsbi/defconfig new file mode 100644 index 0000000000000..5e566067f338d --- /dev/null +++ b/boards/risc-v/k230/canmv230/configs/nsbi/defconfig @@ -0,0 +1,95 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_16550_ADDRWIDTH=0 +CONFIG_16550_REGWIDTH=32 +CONFIG_16550_SERIAL_DISABLE_REORDERING=y +CONFIG_16550_SUPRESS_CONFIG=y +CONFIG_16550_UART0=y +CONFIG_16550_UART0_BASE=0x91400000 +CONFIG_16550_UART0_CLOCK=50000000 +CONFIG_16550_UART0_IRQ=41 +CONFIG_16550_UART0_SERIAL_CONSOLE=y +CONFIG_16550_UART=y +CONFIG_16550_WAIT_LCR=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_ADDRENV=y +CONFIG_ARCH_BOARD="canmv230" +CONFIG_ARCH_BOARD_K230_CANMV=y +CONFIG_ARCH_CHIP="k230" +CONFIG_ARCH_CHIP_K230=y +CONFIG_ARCH_DATA_NPAGES=128 +CONFIG_ARCH_DATA_VBASE=0xC0100000 +CONFIG_ARCH_HEAP_NPAGES=128 +CONFIG_ARCH_HEAP_VBASE=0xC0200000 +CONFIG_ARCH_INTERRUPTSTACK=3072 +CONFIG_ARCH_KERNEL_STACKSIZE=3072 +CONFIG_ARCH_PGPOOL_MAPPING=y +CONFIG_ARCH_PGPOOL_PBASE=0x8600000 +CONFIG_ARCH_PGPOOL_SIZE=10485760 +CONFIG_ARCH_PGPOOL_VBASE=0x8600000 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_TEXT_NPAGES=128 +CONFIG_ARCH_TEXT_VBASE=0xC0000000 +CONFIG_ARCH_USE_MMU=y +CONFIG_ARCH_USE_MPU=y +CONFIG_ARCH_USE_S_MODE=y +CONFIG_BINFMT_ELF_EXECUTABLE=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=53291 +CONFIG_BUILD_KERNEL=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEV_ZERO=y +CONFIG_ELF=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_FILEPATH="/system/bin/init" +CONFIG_INIT_MOUNT=y +CONFIG_INIT_MOUNT_FLAGS=0x1 +CONFIG_INIT_MOUNT_TARGET="/system/bin" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y +CONFIG_MEMSET_64BIT=y +CONFIG_MEMSET_OPTSPEED=y +CONFIG_MM_PGALLOC=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_NUTTSBI=y +CONFIG_NUTTSBI_IPI_BASE=0xf04000000 +CONFIG_NUTTSBI_MTIMECMP_BASE=0xf04004000 +CONFIG_NUTTSBI_MTIME_BASE=0xf0400bff8 +CONFIG_PATH_INITIAL="/system/bin" +CONFIG_RAM_SIZE=16777216 +CONFIG_RAM_START=0x8080000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_UART_ARCH_MMIO=y +CONFIG_STACK_COLORATION=y +CONFIG_STANDARD_SERIAL=y +CONFIG_START_DAY=15 +CONFIG_START_YEAR=2024 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_PROGNAME="init" +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/risc-v/k230/canmv230/configs/nsh/defconfig b/boards/risc-v/k230/canmv230/configs/nsh/defconfig index abbbd4ce1830b..509d68fde686b 100644 --- a/boards/risc-v/k230/canmv230/configs/nsh/defconfig +++ b/boards/risc-v/k230/canmv230/configs/nsh/defconfig @@ -26,10 +26,12 @@ CONFIG_ARCH_CHIP_K230=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y -CONFIG_BOARD_LOOPSPERMSEC=6366 +CONFIG_BOARD_LOOPSPERMSEC=53291 CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y CONFIG_DEV_ZERO=y CONFIG_ELF=y +CONFIG_EXAMPLES_CALIB_UDELAY=y CONFIG_EXAMPLES_HELLO=y CONFIG_FS_PROCFS=y CONFIG_IDLETHREAD_STACKSIZE=2048 @@ -46,7 +48,7 @@ CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y CONFIG_PATH_INITIAL="/system/bin" -CONFIG_RAM_SIZE=134217728 +CONFIG_RAM_SIZE=16777216 CONFIG_RAM_START=0x8000000 CONFIG_RAW_BINARY=y CONFIG_READLINE_CMD_HISTORY=y diff --git a/boards/risc-v/k230/canmv230/configs/pnsh/defconfig b/boards/risc-v/k230/canmv230/configs/pnsh/defconfig new file mode 100644 index 0000000000000..c253a47975f37 --- /dev/null +++ b/boards/risc-v/k230/canmv230/configs/pnsh/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_16550_ADDRWIDTH=0 +CONFIG_16550_REGWIDTH=32 +CONFIG_16550_SERIAL_DISABLE_REORDERING=y +CONFIG_16550_SUPRESS_CONFIG=y +CONFIG_16550_UART0=y +CONFIG_16550_UART0_BASE=0x91400000 +CONFIG_16550_UART0_CLOCK=50000000 +CONFIG_16550_UART0_IRQ=43 +CONFIG_16550_UART0_SERIAL_CONSOLE=y +CONFIG_16550_UART=y +CONFIG_16550_WAIT_LCR=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="canmv230" +CONFIG_ARCH_BOARD_K230_CANMV=y +CONFIG_ARCH_CHIP="k230" +CONFIG_ARCH_CHIP_K230=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_USE_MPU=y +CONFIG_BOARD_LOOPSPERMSEC=53291 +CONFIG_BUILD_PROTECTED=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEV_ZERO=y +CONFIG_ELF=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_NUTTX_USERSPACE=0x8040000 +CONFIG_PASS1_BUILDIR="boards/risc-v/k230/canmv230/kernel" +CONFIG_PATH_INITIAL="/system/bin" +CONFIG_RAM_SIZE=16777216 +CONFIG_RAM_START=0x8000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_UART_ARCH_MMIO=y +CONFIG_STACK_COLORATION=y +CONFIG_STANDARD_SERIAL=y +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2021 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_STACKSIZE=3072 +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/risc-v/k230/canmv230/configs/remote/defconfig b/boards/risc-v/k230/canmv230/configs/remote/defconfig new file mode 100644 index 0000000000000..39aeb0ae02935 --- /dev/null +++ b/boards/risc-v/k230/canmv230/configs/remote/defconfig @@ -0,0 +1,90 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_ARCH="risc-v" +CONFIG_ARCH_ADDRENV=y +CONFIG_ARCH_BOARD="canmv230" +CONFIG_ARCH_BOARD_K230_CANMV=y +CONFIG_ARCH_CHIP="k230" +CONFIG_ARCH_CHIP_K230=y +CONFIG_ARCH_DATA_NPAGES=128 +CONFIG_ARCH_DATA_VBASE=0xC0100000 +CONFIG_ARCH_HEAP_NPAGES=128 +CONFIG_ARCH_HEAP_VBASE=0xC0200000 +CONFIG_ARCH_INTERRUPTSTACK=3072 +CONFIG_ARCH_KERNEL_STACKSIZE=3072 +CONFIG_ARCH_PGPOOL_MAPPING=y +CONFIG_ARCH_PGPOOL_PBASE=0x7200000 +CONFIG_ARCH_PGPOOL_SIZE=14680064 +CONFIG_ARCH_PGPOOL_VBASE=0x7200000 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_TEXT_NPAGES=128 +CONFIG_ARCH_TEXT_VBASE=0xC0000000 +CONFIG_ARCH_USE_MMU=y +CONFIG_ARCH_USE_MPU=y +CONFIG_ARCH_USE_S_MODE=y +CONFIG_BINFMT_ELF_EXECUTABLE=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=106613 +CONFIG_BUILD_KERNEL=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEV_SIMPLE_ADDRENV=y +CONFIG_DEV_ZERO=y +CONFIG_ELF=y +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_FS_RPMSGFS=y +CONFIG_FS_TMPFS=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_FILEPATH="/system/bin/init" +CONFIG_INIT_MOUNT=y +CONFIG_INIT_MOUNT_FLAGS=0x1 +CONFIG_INIT_MOUNT_TARGET="/system/bin" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBC_HOSTNAME="remote" +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y +CONFIG_MEMSET_64BIT=y +CONFIG_MEMSET_OPTSPEED=y +CONFIG_MM_PGALLOC=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_PROMPT_STRING="remote> " +CONFIG_NSH_READLINE=y +CONFIG_NUTTSBI=y +CONFIG_NUTTSBI_IPI_BASE=0xf04000000 +CONFIG_NUTTSBI_MTIMECMP_BASE=0xf04004000 +CONFIG_NUTTSBI_MTIME_BASE=0xf0400bff8 +CONFIG_PATH_INITIAL="/system/bin" +CONFIG_RAM_SIZE=16777216 +CONFIG_RAM_START=0x7000000 +CONFIG_RAW_BINARY=y +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RPMSG_PING=y +CONFIG_RPMSG_UART=y +CONFIG_RPMSG_UART_CONSOLE=y +CONFIG_RPTUN=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_STACK_COLORATION=y +CONFIG_STANDARD_SERIAL=y +CONFIG_START_DAY=10 +CONFIG_START_MONTH=2 +CONFIG_START_YEAR=2024 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_PROGNAME="init" +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/risc-v/k230/canmv230/include/board_memorymap.h b/boards/risc-v/k230/canmv230/include/board_memorymap.h index d2de8b3261cd2..4c5a5e09d3953 100644 --- a/boards/risc-v/k230/canmv230/include/board_memorymap.h +++ b/boards/risc-v/k230/canmv230/include/board_memorymap.h @@ -31,23 +31,16 @@ * Pre-processor Definitions ****************************************************************************/ -/* DDR start address */ - -#define K230_DDR_BASE (0x8000000) -#define K230_DDR_SIZE (0x8000000) - /* Kernel code memory (RX) */ #define KFLASH_START (uintptr_t)__kflash_start #define KFLASH_SIZE (uintptr_t)__kflash_size -#define KSRAM_START (uintptr_t)__ksram_start -#define KSRAM_SIZE (uintptr_t)__ksram_size -#define KSRAM_END (uintptr_t)__ksram_end /* Kernel RAM (RW) */ -#define PGPOOL_START (uintptr_t)__pgheap_start -#define PGPOOL_SIZE (uintptr_t)__pgheap_size +#define KSRAM_START (uintptr_t)__ksram_start +#define KSRAM_SIZE (uintptr_t)__ksram_size +#define KSRAM_END (uintptr_t)__ksram_end /* Page pool (RWX) */ diff --git a/boards/risc-v/k230/canmv230/kernel/Makefile b/boards/risc-v/k230/canmv230/kernel/Makefile new file mode 100644 index 0000000000000..641ba764f4c27 --- /dev/null +++ b/boards/risc-v/k230/canmv230/kernel/Makefile @@ -0,0 +1,92 @@ +############################################################################ +# boards/risc-v/k230/canmv230/kernel/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +# The entry point name (if none is provided in the .config file) + +CONFIG_INIT_ENTRYPOINT ?= user_start +ENTRYPT = $(patsubst "%",%,$(CONFIG_INIT_ENTRYPOINT)) + + +# Get the paths to the libraries and the links script path in format that +# is appropriate for the host OS + +USER_LIBPATHS = $(addprefix -L,$(call CONVERT_PATH,$(addprefix $(TOPDIR)$(DELIM),$(dir $(USERLIBS))))) +USER_LDSCRIPT = -T $(call CONVERT_PATH,$(BOARD_DIR)$(DELIM)scripts$(DELIM)ld-userland.script) +USER_HEXFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.hex) +USER_SRECFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.srec) +USER_BINFILE += $(call CONVERT_PATH,$(TOPDIR)$(DELIM)nuttx_user.bin) + +USER_LDFLAGS = -melf64lriscv --undefined=$(ENTRYPT) --entry=$(ENTRYPT) $(USER_LDSCRIPT) +USER_LDLIBS = $(patsubst lib%,-l%,$(basename $(notdir $(USERLIBS)))) +USER_LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}" + +# Source files + +CSRCS = k230_userspace.c +COBJS = $(CSRCS:.c=$(OBJEXT)) +OBJS = $(COBJS) + +# Targets: + +all: $(TOPDIR)$(DELIM)nuttx_user.elf $(TOPDIR)$(DELIM)User.map +.PHONY: nuttx_user.elf depend clean distclean + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +# Create the nuttx_user.elf file containing all of the user-mode code + +nuttx_user.elf: $(OBJS) + $(Q) $(LD) -o $@ $(USER_LDFLAGS) $(USER_LIBPATHS) $(OBJS) --start-group $(USER_LDLIBS) --end-group $(USER_LIBGCC) + +$(TOPDIR)$(DELIM)nuttx_user.elf: nuttx_user.elf + @echo "LD: nuttx_user.elf" + $(Q) cp -a $^ $(TOPDIR)$(DELIM)$^ +ifeq ($(CONFIG_INTELHEX_BINARY),y) + @echo "CP: nuttx_user.hex" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex $^ $(USER_HEXFILE) +endif +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: nuttx_user.srec" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec $^ $(USER_SRECFILE) +endif +ifeq ($(CONFIG_RAW_BINARY),y) + @echo "CP: nuttx_user.bin" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary $^ $(USER_BINFILE) +endif + +$(TOPDIR)$(DELIM)User.map: nuttx_user.elf + @echo "MK: User.map" + $(Q) $(NM) -n $^ >$(TOPDIR)$(DELIM)User.map + $(Q) $(CROSSDEV)size $^ + +.depend: + +depend: .depend + +clean: + $(call DELFILE, nuttx_user.elf) + $(call DELFILE, "$(TOPDIR)$(DELIM)nuttx_user.*") + $(call DELFILE, "$(TOPDIR)$(DELIM)User.map") + $(call CLEAN) + +distclean: clean diff --git a/boards/risc-v/k230/canmv230/kernel/k230_userspace.c b/boards/risc-v/k230/canmv230/kernel/k230_userspace.c new file mode 100644 index 0000000000000..c399a795d48f3 --- /dev/null +++ b/boards/risc-v/k230/canmv230/kernel/k230_userspace.c @@ -0,0 +1,100 @@ +/**************************************************************************** + * boards/risc-v/k230/canmv230/kernel/k230_userspace.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include + +#if defined(CONFIG_BUILD_PROTECTED) && !defined(__KERNEL__) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_NUTTX_USERSPACE +# error "CONFIG_NUTTX_USERSPACE not defined" +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* These 'addresses' of these values are setup by the linker script. */ + +extern uint8_t _stext[]; /* Start of .text */ +extern uint8_t _etext[]; /* End_1 of .text + .rodata */ +extern const uint8_t _eronly[]; /* End+1 of read only section (.text + .rodata) */ +extern uint8_t _sdata[]; /* Start of .data */ +extern uint8_t _edata[]; /* End+1 of .data */ +extern uint8_t _sbss[]; /* Start of .bss */ +extern uint8_t _ebss[]; /* End+1 of .bss */ + +extern uint8_t __ld_usram_end[]; /* End+1 of user ram section */ + +const struct userspace_s userspace locate_data(".userspace") = +{ + /* General memory map */ + + .us_entrypoint = CONFIG_INIT_ENTRYPOINT, + .us_textstart = (uintptr_t)_stext, + .us_textend = (uintptr_t)_etext, + .us_datasource = (uintptr_t)_eronly, + .us_datastart = (uintptr_t)_sdata, + .us_dataend = (uintptr_t)_edata, + .us_bssstart = (uintptr_t)_sbss, + .us_bssend = (uintptr_t)_ebss, + + .us_heapend = (uintptr_t)__ld_usram_end, + + /* Memory manager heap structure */ + + .us_heap = &g_mmheap, + + /* Task/thread startup routines */ + + .task_startup = nxtask_startup, + + /* Signal handler trampoline */ + + .signal_handler = up_signal_handler, + + /* User-space work queue support (declared in include/nuttx/wqueue.h) */ + +#ifdef CONFIG_LIBC_USRWORK + .work_usrstart = work_usrstart, +#endif +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#endif /* CONFIG_BUILD_PROTECTED && !__KERNEL__ */ diff --git a/boards/risc-v/k230/canmv230/scripts/Make.defs b/boards/risc-v/k230/canmv230/scripts/Make.defs index 16db926273b4b..f57aaf736a610 100644 --- a/boards/risc-v/k230/canmv230/scripts/Make.defs +++ b/boards/risc-v/k230/canmv230/scripts/Make.defs @@ -24,7 +24,17 @@ include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs ifeq ($(CONFIG_ARCH_CHIP_K230),y) ifeq ($(CONFIG_BUILD_KERNEL),y) +ifeq ($(CONFIG_NUTTSBI),y) + ifeq ($(CONFIG_RPTUN),y) + LDSCRIPT = ld-rptun.script + else + LDSCRIPT = ld-nuttsbi.script + endif +else LDSCRIPT = ld-kernel.script +endif +else ifeq ($(CONFIG_BUILD_PROTECTED),y) + LDSCRIPT = ld-protected.script else LDSCRIPT = ld-flat.script endif @@ -46,5 +56,35 @@ CELFFLAGS = $(CFLAGS) CXXELFFLAGS = $(CXXFLAGS) LDELFFLAGS = --oformat elf64-littleriscv -LDELFFLAGS += -r -e main -LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/binfmt/libelf/gnu-elf.ld) +ifeq ($(CONFIG_BINFMT_ELF_RELOCATABLE),y) +LDELFFLAGS += -r +endif + +# POSTBUILD management + +# KERNEL builds need real ROMFS and even OpenSBI wrapping + +ifeq ($(CONFIG_BUILD_KERNEL),y) +ifeq ($(wildcard $(BOARD_DIR)$(DELIM)src$(DELIM)romfs_boot.c),) +define POSTBUILD + $(Q) echo "Please replace stub ROMFS with real one." + $(Q) rm $(BOARD_DIR)$(DELIM)src$(DELIM)libboard.a +endef +else ifneq ($(CONFIG_NUTTSBI),y) +define POSTBUILD + $(Q) echo "Please wrap nuttx.bin with OpenSBI to run on target." +endef +else +define POSTBUILD + $(Q) echo "Please try nuttx.bin on target." +endef +endif +endif + +# PROTECTED build needs pad-combine operations + +ifeq ($(CONFIG_BUILD_PROTECTED),y) +define POSTBUILD + $(Q) echo "pad-combine nuttx.bin and nuttx_user.bin to try on target." +endef +endif diff --git a/boards/risc-v/k230/canmv230/scripts/gnu-elf.ld b/boards/risc-v/k230/canmv230/scripts/gnu-elf.ld new file mode 100644 index 0000000000000..c304a4398241e --- /dev/null +++ b/boards/risc-v/k230/canmv230/scripts/gnu-elf.ld @@ -0,0 +1,132 @@ +/**************************************************************************** + * boards/risc-v/k230/camnv230/scripts/gnu-elf.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +SECTIONS +{ + . = 0xC0000000; + .text : + { + _stext = . ; + *(.text) + *(.text.*) + *(.gnu.warning) + *(.stub) + *(.glue_7) + *(.glue_7t) + *(.jcr) + + /* C++ support: The .init and .fini sections contain specific logic + * to manage static constructors and destructors. + */ + + *(.gnu.linkonce.t.*) + *(.init) /* Old ABI */ + *(.fini) /* Old ABI */ + _etext = . ; + } + + .rodata : + { + _srodata = . ; + *(.rodata) + *(.rodata1) + *(.rodata.*) + *(.gnu.linkonce.r*) + _erodata = . ; + } + + . = 0xC0101000; + .data : + { + _sdata = . ; + *(.data) + *(.data1) + *(.data.*) + *(.gnu.linkonce.d*) + . = ALIGN(4); + _edata = . ; + } + + /* C++ support. For each global and static local C++ object, + * GCC creates a small subroutine to construct the object. Pointers + * to these routines (not the routines themselves) are stored as + * simple, linear arrays in the .ctors section of the object file. + * Similarly, pointers to global/static destructor routines are + * stored in .dtors. + */ + + .ctors : + { + _sctors = . ; + KEEP (*(.ctors)) /* Old ABI: Unallocated */ + KEEP (*(.init_array)) /* New ABI: Allocated */ + KEEP (*(SORT(.init_array.*))) + _ectors = . ; + } + + .dtors : + { + _sdtors = . ; + KEEP (*(.dtors)) /* Old ABI: Unallocated */ + KEEP (*(.fini_array)) /* New ABI: Allocated */ + KEEP (*(SORT(.fini_array.*))) + _edtors = . ; + } + + .bss : + { + _sbss = . ; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.b*) + *(COMMON) + _ebss = . ; + } + + /* Thread local storage support */ + .tdata : { + _stdata = ABSOLUTE(.); + KEEP (*(.tdata .tdata.* .gnu.linkonce.td.*)); + _etdata = ABSOLUTE(.); + } + + .tbss : { + _stbss = ABSOLUTE(.); + KEEP (*(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon)); + _etbss = ABSOLUTE(.); + } + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/risc-v/k230/canmv230/scripts/ld-flat.script b/boards/risc-v/k230/canmv230/scripts/ld-flat.script index 400a5831cda10..3e340ddfaae3f 100644 --- a/boards/risc-v/k230/canmv230/scripts/ld-flat.script +++ b/boards/risc-v/k230/canmv230/scripts/ld-flat.script @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/risc-v/qemu-rv/rv-virt/scripts/ld.script + * boards/risc-v/k230/canmv230/scripts/ld-flat.script * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,9 +18,12 @@ * ****************************************************************************/ +#include + + SECTIONS { - . = 0x08000000; + . = CONFIG_RAM_START; .text : { @@ -111,10 +114,11 @@ SECTIONS *(.sbss.*) *(.gnu.linkonce.b*) *(COMMON) + . = ALIGN(32); _ebss = . ; } - /* Stabs debugging sections. */ + /* Stabs debugging sections. */ .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } diff --git a/boards/risc-v/k230/canmv230/scripts/ld-kernel.script b/boards/risc-v/k230/canmv230/scripts/ld-kernel.script new file mode 100644 index 0000000000000..cf673c7456b92 --- /dev/null +++ b/boards/risc-v/k230/canmv230/scripts/ld-kernel.script @@ -0,0 +1,143 @@ +/**************************************************************************** + * boards/risc-v/k230/canmv230/scripts/ld-kernel.script + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + kflash (rx) : ORIGIN = 0x08200000, LENGTH = 1024K /* w/ cache */ + ksram (rwx) : ORIGIN = 0x08300000, LENGTH = 1024K /* w/ cache */ + pgram (rwx) : ORIGIN = 0x08600000, LENGTH = 10M /* w/ cache */ +} + +OUTPUT_ARCH("riscv") + +/* Provide the kernel boundaries */ + +__kflash_start = ORIGIN(kflash); +__kflash_size = LENGTH(kflash); +__ksram_start = ORIGIN(ksram); +__ksram_size = LENGTH(ksram); +__ksram_end = ORIGIN(ksram) + LENGTH(ksram); + +/* Page heap */ + +__pgheap_start = ORIGIN(pgram); +__pgheap_size = LENGTH(pgram); + +SECTIONS +{ + . = 0x8200000; + + .text : + { + _stext = . ; + *(.text) + *(.text.*) + *(.gnu.warning) + *(.stub) + *(.glue_7) + *(.glue_7t) + *(.jcr) + + /* C++ support: The .init and .fini sections contain specific logic + * to manage static constructors and destructors. + */ + + *(.gnu.linkonce.t.*) + *(.init) /* Old ABI */ + *(.fini) /* Old ABI */ + _etext = . ; + } + + .rodata : + { + _srodata = . ; + *(.rodata) + *(.rodata1) + *(.rodata.*) + *(.gnu.linkonce.r*) + _erodata = . ; + } + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = . ; + *(.data) + *(.data1) + *(.data.*) + *(.gnu.linkonce.d*) + . = ALIGN(4); + _edata = . ; + } + + .bss : + { + _sbss = . ; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.b*) + *(COMMON) + _ebss = . ; + } > ksram + + /* Page tables here, align to 4K boundary */ + + .pgtables (NOLOAD) : ALIGN(0x1000) { + *(.pgtables) + . = ALIGN(4); + } > ksram + + /* Stack top */ + + .stack_top : { + . = ALIGN(32); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/risc-v/k230/canmv230/scripts/ld-nuttsbi.script b/boards/risc-v/k230/canmv230/scripts/ld-nuttsbi.script new file mode 100644 index 0000000000000..1c0ace8b2f985 --- /dev/null +++ b/boards/risc-v/k230/canmv230/scripts/ld-nuttsbi.script @@ -0,0 +1,143 @@ +/**************************************************************************** + * boards/risc-v/k230/canmv230/scripts/ld-nuttsbi.script + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +MEMORY +{ + kflash (rx) : ORIGIN = 0x8000000, LENGTH = 384K /* w/ cache */ + ksram (rwx) : ORIGIN = 0x8080000, LENGTH = 128K /* w/ cache */ + pgram (rwx) : ORIGIN = 0x8600000, LENGTH = 10M /* w/ cache */ +} + +OUTPUT_ARCH("riscv") + +/* Provide the kernel boundaries */ + +__kflash_start = ORIGIN(kflash); +__kflash_size = LENGTH(kflash); +__ksram_start = ORIGIN(ksram); +__ksram_size = LENGTH(ksram); +__ksram_end = ORIGIN(ksram) + LENGTH(ksram); + +/* Page heap */ + +__pgheap_start = ORIGIN(pgram); +__pgheap_size = LENGTH(pgram); + +SECTIONS +{ + . = 0x8000000; + + .text : + { + _stext = . ; + *(.text) + *(.text.*) + *(.gnu.warning) + *(.stub) + *(.glue_7) + *(.glue_7t) + *(.jcr) + + /* C++ support: The .init and .fini sections contain specific logic + * to manage static constructors and destructors. + */ + + *(.gnu.linkonce.t.*) + *(.init) /* Old ABI */ + *(.fini) /* Old ABI */ + _etext = . ; + } + + .rodata : + { + _srodata = . ; + *(.rodata) + *(.rodata1) + *(.rodata.*) + *(.gnu.linkonce.r*) + _erodata = . ; + } + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = . ; + *(.data) + *(.data1) + *(.data.*) + *(.gnu.linkonce.d*) + . = ALIGN(4); + _edata = . ; + } + + .bss : + { + _sbss = . ; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.b*) + *(COMMON) + _ebss = . ; + } > ksram + + /* Page tables here, align to 4K boundary */ + + .pgtables (NOLOAD) : ALIGN(0x1000) { + *(.pgtables) + . = ALIGN(4); + } > ksram + + /* Stack top */ + + .stack_top : { + . = ALIGN(32); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/risc-v/k230/canmv230/scripts/ld-protected.script b/boards/risc-v/k230/canmv230/scripts/ld-protected.script new file mode 100644 index 0000000000000..94bb995eb7aa4 --- /dev/null +++ b/boards/risc-v/k230/canmv230/scripts/ld-protected.script @@ -0,0 +1,122 @@ +/**************************************************************************** + * boards/risc-v/k230/canmv230/scripts/ld-protected.script + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This shares memory layout with ld-userland.script */ + +MEMORY +{ + kflash (rx) : ORIGIN = 0x8000000, LENGTH = 256K /* w/ cache */ + uflash (rx) : ORIGIN = 0x8040000, LENGTH = 256K /* w/ cache */ + + ksram (rwx) : ORIGIN = 0x8200000, LENGTH = 1024K /* w/ cache */ + usram (rwx) : ORIGIN = 0x8300000, LENGTH = 1024K /* w/ cache */ +} + + +OUTPUT_ARCH("riscv") + +/* Provide these to avoid using config files for them */ + +__uflash_start = ORIGIN(uflash); +__uflash_size = LENGTH(uflash); +__usram_start = ORIGIN(usram); +__usram_size = LENGTH(usram); + +/* Provide the kernel boundaries as well */ + +__kflash_start = ORIGIN(kflash); +__kflash_size = LENGTH(kflash); +__ksram_start = ORIGIN(ksram); +__ksram_size = LENGTH(ksram); +__ksram_end = ORIGIN(ksram) + LENGTH(ksram); + +ENTRY(_stext) +EXTERN(__start) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.start .start.*) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.* .srodata .srodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > kflash + + .init_section : ALIGN(4) { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > kflash + + _eronly = ABSOLUTE(.); + + .data : ALIGN(4) { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.d.*) + *(.gnu.linkonce.s.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > ksram AT > kflash + + PROVIDE(__global_pointer$ = _sdata + ((_edata - _sdata) / 2)); + + .bss : ALIGN(4) { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.sbss .sbss.*) + *(.gnu.linkonce.b.*) + *(.gnu.linkonce.sb.*) + *(COMMON) + } > ksram + + /* Page tables here, align to 4K boundary */ + .pgtables (NOLOAD) : ALIGN(0x1000) { + *(.pgtables) + . = ALIGN(32); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/risc-v/k230/canmv230/scripts/ld-rptun.script b/boards/risc-v/k230/canmv230/scripts/ld-rptun.script new file mode 100644 index 0000000000000..64a8fe8b749aa --- /dev/null +++ b/boards/risc-v/k230/canmv230/scripts/ld-rptun.script @@ -0,0 +1,170 @@ +/**************************************************************************** + * boards/risc-v/k230/canmv230/scripts/ld-rptun.script + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include + +/* Enlage kernel data size or pgpool config to reduce nuttx.bin size */ + +#define KSRAM_SIZE (1536*1024) + +/* We only respect RAM and PGPOOL configs for simplicity */ + +#define PGRAM_ADDR (CONFIG_ARCH_PGPOOL_PBASE) +#define PGRAM_SIZE (CONFIG_ARCH_PGPOOL_SIZE) +#define PGRAM_END (PGRAM_ADDR + PGRAM_SIZE) +#define CFRAM_END (CONFIG_RAM_START + CONFIG_RAM_SIZE) + +#if (PGRAM_ADDR < CONFIG_RAM_START) || (PGRAM_END > CFRAM_END) + #error invalid RAM or PGPOOL configuration! +#endif + +#if (PGRAM_END < CFRAM_END) + # warn are we wasting CFRAM_END-PGRAM_END bytes? +#endif + +#define KTEXT_ADDR (CONFIG_RAM_START) +#define KRAM_TOTAL (PGRAM_ADDR - KTEXT_ADDR) /* ignore space after pgpool */ + +#define KTEXT_SIZE (KRAM_TOTAL-KSRAM_SIZE) +#define KSRAM_ADDR (KTEXT_ADDR + KTEXT_SIZE) + +MEMORY +{ + kflash (rx) : ORIGIN = KTEXT_ADDR, LENGTH = KTEXT_SIZE /* w/ cache */ + ksram (rwx) : ORIGIN = KSRAM_ADDR, LENGTH = KSRAM_SIZE /* w/ cache */ + pgram (rwx) : ORIGIN = PGRAM_ADDR, LENGTH = PGRAM_SIZE /* w/ cache */ +} + +OUTPUT_ARCH("riscv") + +/* Provide the kernel boundaries, used in board memory map */ + +__kflash_start = ORIGIN(kflash); +__kflash_size = LENGTH(kflash); +__ksram_start = ORIGIN(ksram); +__ksram_size = LENGTH(ksram); +__ksram_end = ORIGIN(ksram) + LENGTH(ksram); + +/* Page heap */ + +__pgheap_start = ORIGIN(pgram); +__pgheap_size = LENGTH(pgram); + +SECTIONS +{ + . = KTEXT_ADDR; + + .text : + { + _stext = . ; + *(.text) + *(.text.*) + *(.gnu.warning) + *(.stub) + *(.glue_7) + *(.glue_7t) + *(.jcr) + + /* C++ support: The .init and .fini sections contain specific logic + * to manage static constructors and destructors. + */ + + *(.gnu.linkonce.t.*) + *(.init) /* Old ABI */ + *(.fini) /* Old ABI */ + _etext = . ; + } + + .rodata : + { + _srodata = . ; + *(.rodata) + *(.rodata1) + *(.rodata.*) + *(.gnu.linkonce.r*) + _erodata = . ; + } + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = . ; + *(.data) + *(.data1) + *(.data.*) + *(.gnu.linkonce.d*) + . = ALIGN(4); + _edata = . ; + } + + .bss : + { + _sbss = . ; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.b*) + *(COMMON) + _ebss = . ; + } > ksram + + /* Page tables here, align to 4K boundary */ + + .pgtables (NOLOAD) : ALIGN(0x1000) { + *(.pgtables) + . = ALIGN(4); + } > ksram + + /* Stack top */ + + .stack_top : { + . = ALIGN(32); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/risc-v/k230/canmv230/scripts/ld-userland.script b/boards/risc-v/k230/canmv230/scripts/ld-userland.script new file mode 100644 index 0000000000000..09b26d71484a1 --- /dev/null +++ b/boards/risc-v/k230/canmv230/scripts/ld-userland.script @@ -0,0 +1,112 @@ +/**************************************************************************** + * boards/risc-v/k230/canmv230/scripts/ld-userland.script + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* NOTE: This shares memory layout with ld-protected.script */ + +MEMORY +{ + kflash (rx) : ORIGIN = 0x8000000, LENGTH = 256K /* w/ cache */ + uflash (rx) : ORIGIN = 0x8040000, LENGTH = 256K /* w/ cache */ + + ksram (rwx) : ORIGIN = 0x8200000, LENGTH = 1024K /* w/ cache */ + usram (rwx) : ORIGIN = 0x8300000, LENGTH = 1024K /* w/ cache */ +} + +OUTPUT_ARCH("riscv") + +SECTIONS +{ + /* section info */ + + __ld_uflash_start = ORIGIN(uflash); + __ld_uflash_end = ORIGIN(uflash)+ LENGTH(uflash); + __ld_uflash_size = LENGTH(uflash); + + __ld_usram_start = ORIGIN(usram); + __ld_usram_end = ORIGIN(usram)+ LENGTH(usram); + __ld_usram_size = LENGTH(usram); + + .userspace : { + *(.userspace) + } > uflash + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.* .srodata .srodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > uflash + + .init_section : { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } > uflash + + __exidx_start = ABSOLUTE(.); + + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + . = ALIGN(4); + _edata = ABSOLUTE(.); + } > usram AT > uflash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.sbss .sbss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + _ebss = ABSOLUTE(.); + } > usram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/risc-v/k230/canmv230/src/.gitignore b/boards/risc-v/k230/canmv230/src/.gitignore index 1baf09ba3ae0f..7c0a8cdf91bec 100644 --- a/boards/risc-v/k230/canmv230/src/.gitignore +++ b/boards/risc-v/k230/canmv230/src/.gitignore @@ -1 +1,4 @@ -/etctmp* +etctmp/ +etctmp.c +romfs_boot.c + diff --git a/boards/risc-v/k230/canmv230/src/CMakeLists.txt b/boards/risc-v/k230/canmv230/src/CMakeLists.txt new file mode 100644 index 0000000000000..4cef81e6736fb --- /dev/null +++ b/boards/risc-v/k230/canmv230/src/CMakeLists.txt @@ -0,0 +1,51 @@ +# ############################################################################## +# boards/risc-v/k230/canmv230/src/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS canmv_init.c) + +if(CONFIG_BUILD_KERNEL) + if(EXISTS romfs_boot.c) + list(APPEND SRCS romfs_boot.c) + else() + list(APPEND SRCS romfs_stub.c) + endif() +endif() + +target_sources(board PRIVATE ${SRCS}) + +if(CONFIG_ARCH_CHIP_K230) + if(CONFIG_BUILD_KERNEL) + if(CONFIG_NUTTSBI) + if(CONFIG_RPTUN) + set(LDFILE ld-rptun.script) + else() + set(LDFILE ld-nuttsbi.script) + endif() + else() + set(LDFILE ld-kernel.script) + endif() + elseif(CONFIG_BUILD_PROTECTED) + set(LDFILE ld-protected.script) + else() + set(LDFILE ld-flat.script) + endif() +endif() + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/${LDFILE}") diff --git a/boards/risc-v/k230/canmv230/src/Makefile b/boards/risc-v/k230/canmv230/src/Makefile index b514e41ee0f3b..352df6a5929cd 100644 --- a/boards/risc-v/k230/canmv230/src/Makefile +++ b/boards/risc-v/k230/canmv230/src/Makefile @@ -1,5 +1,5 @@ ############################################################################ -# boards/risc-v/k230/canmv-k230/src/Makefile +# boards/risc-v/k230/canmv230/src/Makefile # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with @@ -22,6 +22,20 @@ include $(TOPDIR)/Make.defs RCSRCS = etc/init.d/rc.sysinit etc/init.d/rcS -CSRCS = k230_appinit.c +CSRCS = canmv_init.c + +ifeq ($(CONFIG_BUILD_KERNEL),y) +CSRCS += $(if $(wildcard romfs_boot.c), romfs_boot.c, romfs_stub.c) +endif include $(TOPDIR)/boards/Board.mk + +# don't use single-colon targets as they may coflict with those included ones. +# use double-colon targets to avoid collisions below. + +ifeq ($(CONFIG_BUILD_KERNEL),y) +.PHONY: clean +clean:: + $(call DELFILE, romfs_boot.c) +endif + diff --git a/boards/risc-v/k230/canmv230/src/canmv_init.c b/boards/risc-v/k230/canmv230/src/canmv_init.c new file mode 100644 index 0000000000000..c3ebc88e01cb6 --- /dev/null +++ b/boards/risc-v/k230/canmv230/src/canmv_init.c @@ -0,0 +1,203 @@ +/**************************************************************************** + * boards/risc-v/k230/canmv230/src/canmv_init.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_RPMSG_UART +# include +#endif + +#if !defined(CONFIG_BUILD_KERNEL) || defined(CONFIG_NUTTSBI) +# include "k230_hart.h" +#endif + +#ifdef CONFIG_RPTUN +# include "k230_rptun.h" +#endif + +#ifdef CONFIG_BUILD_KERNEL +#include "romfs.h" +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_BUILD_KERNEL +#define SECTORSIZE 512 +#define NSECTORS(b) (((b) + SECTORSIZE - 1) / SECTORSIZE) +#endif /* CONFIG_BUILD_KERNEL */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void debug_dumps(void) +{ + /* Dumps to aid investigation */ + +#if !defined(CONFIG_BUILD_KERNEL) || defined(CONFIG_NUTTSBI) + sinfo("is_big=%d\n", k230_hart_is_big()); +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int board_reset(int status) +{ + _alert("status=%d, halt now.\n", status); + while (1) + { + asm volatile("wfi"); + } + + return 0; +} + +#ifdef CONFIG_RPMSG_UART +/**************************************************************************** + * Name: rpmsg_serialinit + * Description: initialize /dev/ttyRpmsg device + ****************************************************************************/ + +void rpmsg_serialinit(void) +{ +#ifdef CONFIG_K230_RPTUN_MASTER + uart_rpmsg_init("remote", "Rpmsg", 4096, false); +#else + uart_rpmsg_init("master", "Rpmsg", 4096, true); +#endif +} +#endif + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform architecture specific initialization + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifdef CONFIG_BOARD_LATE_INITIALIZE + /* Board initialization already performed by board_late_initialize() */ + + return OK; +#else + /* Perform board-specific initialization */ + +#ifdef CONFIG_NSH_ARCHINIT + + mount(NULL, "/proc", "procfs", 0, NULL); + +#endif + debug_dumps(); + return OK; +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called after up_initialize() and board_early_initialize() and just + * before the initial application is started. This additional + * initialization phase may be used, for example, to initialize board- + * specific device drivers for which board_early_initialize() is not + * suitable. + * + * Waiting for events, use of I2C, SPI, etc are permissible in the context + * of board_late_initialize(). That is because board_late_initialize() + * will run on a temporary, internal kernel thread. + * + ****************************************************************************/ + +void board_late_initialize(void) +{ + debug_dumps(); + + /* Perform board-specific initialization */ + +#ifdef CONFIG_BUILD_KERNEL + /* Create ROM disk for mount in nx_start_application */ + + if (NSECTORS(romfs_img_len) > 1) + { + int ret = OK; + ret = romdisk_register(0, romfs_img, NSECTORS(romfs_img_len), + SECTORSIZE); + if (ret < 0) + { + ferr("ERROR: Failed to register romfs: %d\n", -ret); + } + } +#endif /* CONFIG_BUILD_KERNEL */ + +#ifdef CONFIG_NSH_ARCHINIT + + mount(NULL, "/proc", "procfs", 0, NULL); + +#endif + +#ifdef CONFIG_RPTUN +# ifdef CONFIG_K230_RPTUN_MASTER + k230_rptun_init("remote"); +# else + k230_rptun_init("master"); +# endif +#endif +} diff --git a/boards/risc-v/k230/canmv230/src/k230_appinit.c b/boards/risc-v/k230/canmv230/src/k230_appinit.c deleted file mode 100644 index f1c170db97fee..0000000000000 --- a/boards/risc-v/k230/canmv230/src/k230_appinit.c +++ /dev/null @@ -1,120 +0,0 @@ -/**************************************************************************** - * boards/risc-v/k230/canmv230/src/k230_appinit.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: board_app_initialize - * - * Description: - * Perform architecture specific initialization - * - * Input Parameters: - * arg - The boardctl() argument is passed to the board_app_initialize() - * implementation without modification. The argument has no - * meaning to NuttX; the meaning of the argument is a contract - * between the board-specific initialization logic and the - * matching application logic. The value could be such things as a - * mode enumeration value, a set of DIP switch switch settings, a - * pointer to configuration data read from a file or serial FLASH, - * or whatever you would like to do with it. Every implementation - * should accept zero/NULL as a default configuration. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned on - * any failure to indicate the nature of the failure. - * - ****************************************************************************/ - -int board_app_initialize(uintptr_t arg) -{ -#ifdef CONFIG_BOARD_LATE_INITIALIZE - /* Board initialization already performed by board_late_initialize() */ - - return OK; -#else - /* Perform board-specific initialization */ - -#ifdef CONFIG_NSH_ARCHINIT - - mount(NULL, "/proc", "procfs", 0, NULL); - -#endif - - return OK; -#endif -} - -/**************************************************************************** - * Name: board_late_initialize - * - * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional - * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will - * be called after up_initialize() and board_early_initialize() and just - * before the initial application is started. This additional - * initialization phase may be used, for example, to initialize board- - * specific device drivers for which board_early_initialize() is not - * suitable. - * - * Waiting for events, use of I2C, SPI, etc are permissible in the context - * of board_late_initialize(). That is because board_late_initialize() - * will run on a temporary, internal kernel thread. - * - ****************************************************************************/ - -void board_late_initialize(void) -{ - /* Perform board-specific initialization */ - -#ifdef CONFIG_NSH_ARCHINIT - - mount(NULL, "/proc", "procfs", 0, NULL); - -#endif -} diff --git a/boards/risc-v/k230/canmv230/src/romfs.h b/boards/risc-v/k230/canmv230/src/romfs.h new file mode 100644 index 0000000000000..4578780ffd8dc --- /dev/null +++ b/boards/risc-v/k230/canmv230/src/romfs.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * boards/risc-v/k230/canmv230/src/romfs.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISC_V_K230_CANMV230_SRC_ROMFS_H +#define __BOARDS_RISC_V_K230_CANMV230_SRC_ROMFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +extern const unsigned char romfs_img[]; +extern const unsigned int romfs_img_len; + +#endif /* __BOARDS_RISC_V_K230_CANMV230_SRC_ROMFS_H */ diff --git a/boards/risc-v/k230/canmv230/src/romfs_stub.c b/boards/risc-v/k230/canmv230/src/romfs_stub.c new file mode 100644 index 0000000000000..ea39e5e6a3c87 --- /dev/null +++ b/boards/risc-v/k230/canmv230/src/romfs_stub.c @@ -0,0 +1,38 @@ +/**************************************************************************** + * boards/risc-v/k230/canmv230/src/romfs_stub.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +weak_data const unsigned char aligned_data(4) romfs_img[] = +{ + 0x00 +}; +weak_data const unsigned int romfs_img_len = 1; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/boards/risc-v/litex/arty_a7/Kconfig b/boards/risc-v/litex/arty_a7/Kconfig index 4109837f084f5..93f47111820cd 100644 --- a/boards/risc-v/litex/arty_a7/Kconfig +++ b/boards/risc-v/litex/arty_a7/Kconfig @@ -16,52 +16,48 @@ config LITEX_SDIO select ARCH_HAVE_SDIO select SDIO_DMA +if LITEX_SDIO + config LITEX_SDIO1 bool "Enable SDIO1" default LITEX_SDIO select LITEX_SDIO_DMA - depends on LITEX_SDIO config LITEX_IDMODE_FREQ int "ID mode frequency" default 400000 - depends on LITEX_SDIO ---help--- Initial, ID mode SD frequency config LITEX_MMCXFR_FREQ int "MMC transfer frequency" default 25000000 - depends on LITEX_SDIO ---help--- Frequency to use for transferring data to/from an MMC card config LITEX_SD4BIT_FREQ int "SD 4-bit transfer frequency" default 50000000 - depends on LITEX_SDIO ---help--- Frequency to use for transferring data to/from an SD card using all four data lines. config LITEX_SDIO_MOUNT bool "Mount SDIO at startup" default n - depends on LITEX_SDIO config LITEX_SDIO_MOUNT_BLKDEV string "SDIO block device name" default "/dev/mmcsd0" - depends on LITEX_SDIO config LITEX_SDIO_MOUNT_MOUNTPOINT string "SDIO mountpoint" default "/mnt" - depends on LITEX_SDIO config LITEX_SDIO_MOUNT_FSTYPE string "SDIO file system type" default "vfat" - depends on LITEX_SDIO + +endif # LITEX_SDIO config LITEX_APPLICATION_RAMDISK bool "Use application ramdisk" diff --git a/boards/risc-v/mpfs/common/src/mpfs_composite.c b/boards/risc-v/mpfs/common/src/mpfs_composite.c index a8530f284923e..ef24c9c58893b 100644 --- a/boards/risc-v/mpfs/common/src/mpfs_composite.c +++ b/boards/risc-v/mpfs/common/src/mpfs_composite.c @@ -34,7 +34,7 @@ #include "mpfs.h" -#if defined(CONFIG_BOARDCTL_USBDEVCTRL) && defined(CONFIG_USBDEV_COMPOSITE) +#if defined(CONFIG_USBDEV_COMPOSITE) /**************************************************************************** * Private Data @@ -174,6 +174,28 @@ int board_composite_initialize(int port) } #endif +/**************************************************************************** + * Name: board_composite_uninitialize + * + * Description: + * Perform architecture specific initialization of a composite USB device. + * + * Input Parameters: + * port - port number, unused + * + * Returned Value: + * OK always + * + ****************************************************************************/ + +#ifdef CONFIG_USBMSC_COMPOSITE +int board_composite_uninitialize(int port) +{ + board_mscuninitialize(NULL); + return OK; +} +#endif + /**************************************************************************** * Name: board_usbmsc_initialize * @@ -218,91 +240,95 @@ void *board_composite_connect(int port, int configid) * The standard is to use one CDC/ACM and one USB mass storage device. */ - if (configid == 0) - { -#ifdef CONFIG_USBMSC_COMPOSITE - struct composite_devdesc_s dev[2]; - int ifnobase = 0; - int strbase = COMPOSITE_NSTRIDS; + struct composite_devdesc_s dev[2]; + int devs = 0; + int ifnobase = 0; + int strbase = COMPOSITE_NSTRIDS; + if (configid == 0 || configid == 1) + { +#ifdef CONFIG_CDCACM_COMPOSITE /* Configure the CDC/ACM device */ /* Ask the cdcacm driver to fill in the constants we didn't * know here. */ - cdcacm_get_composite_devdesc(&dev[0]); + cdcacm_get_composite_devdesc(&dev[devs]); /* Overwrite and correct some values... */ /* The callback functions for the CDC/ACM class */ - dev[0].classobject = cdcacm_classobject; - dev[0].uninitialize = cdcacm_uninitialize; + dev[devs].classobject = cdcacm_classobject; + dev[devs].uninitialize = cdcacm_uninitialize; /* Interfaces */ - dev[0].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[0].minor = 0; /* The minor interface number */ + dev[devs].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[devs].minor = 0; /* The minor interface number */ /* Strings */ - dev[0].devinfo.strbase = strbase; /* Offset to String Numbers */ + dev[devs].devinfo.strbase = strbase; /* Offset to String Numbers */ /* Endpoints */ - dev[0].devinfo.epno[CDCACM_EP_BULKIN_IDX] = 3; - dev[0].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = 3; - dev[0].devinfo.epno[CDCACM_EP_INTIN_IDX] = 4; + dev[devs].devinfo.epno[CDCACM_EP_BULKIN_IDX] = 3; + dev[devs].devinfo.epno[CDCACM_EP_BULKOUT_IDX] = 3; + dev[devs].devinfo.epno[CDCACM_EP_INTIN_IDX] = 4; /* Count up the base numbers */ - ifnobase += dev[0].devinfo.ninterfaces; - strbase += dev[0].devinfo.nstrings; + ifnobase += dev[devs].devinfo.ninterfaces; + strbase += dev[devs].devinfo.nstrings; + devs++; +#endif + } + + if (configid == 1) + { +#ifdef CONFIG_USBMSC_COMPOSITE /* Configure the mass storage device device */ /* Ask the usbmsc driver to fill in the constants we didn't * know here. */ - usbmsc_get_composite_devdesc(&dev[1]); + usbmsc_get_composite_devdesc(&dev[devs]); /* Overwrite and correct some values... */ /* The callback functions for the USBMSC class */ - dev[1].classobject = board_mscclassobject; - dev[1].uninitialize = board_mscuninitialize; + dev[devs].classobject = board_mscclassobject; + dev[devs].uninitialize = board_mscuninitialize; /* Interfaces */ - dev[1].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ - dev[1].minor = 0; /* The minor interface number */ + dev[devs].devinfo.ifnobase = ifnobase; /* Offset to Interface-IDs */ + dev[devs].minor = 0; /* The minor interface number */ /* Strings */ - dev[1].devinfo.strbase = strbase; /* Offset to String Numbers */ + dev[devs].devinfo.strbase = strbase; /* Offset to String Numbers */ /* Endpoints */ - dev[1].devinfo.epno[USBMSC_EP_BULKIN_IDX] = 1; - dev[1].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = 2; + dev[devs].devinfo.epno[USBMSC_EP_BULKIN_IDX] = 1; + dev[devs].devinfo.epno[USBMSC_EP_BULKOUT_IDX] = 2; /* Count up the base numbers */ - ifnobase += dev[1].devinfo.ninterfaces; - strbase += dev[1].devinfo.nstrings; + ifnobase += dev[devs].devinfo.ninterfaces; + strbase += dev[devs].devinfo.nstrings; - return composite_initialize(composite_getdevdescs(), dev, 2); -#else - return NULL; + devs++; #endif } - else - { - return NULL; - } + + return composite_initialize(composite_getdevdescs(), dev, devs); } -#endif /* CONFIG_BOARDCTL_USBDEVCTRL && CONFIG_USBDEV_COMPOSITE */ +#endif /* CONFIG_USBDEV_COMPOSITE */ diff --git a/boards/risc-v/mpfs/common/src/mpfs_emmcsd.c b/boards/risc-v/mpfs/common/src/mpfs_emmcsd.c index 25a0ed09d6638..400f68f4c8584 100644 --- a/boards/risc-v/mpfs/common/src/mpfs_emmcsd.c +++ b/boards/risc-v/mpfs/common/src/mpfs_emmcsd.c @@ -27,8 +27,9 @@ #include #include #include +#include -#include "mpfs_emmcsd.h" +#include "mpfs_sdio.h" #include "board_config.h" /**************************************************************************** @@ -37,10 +38,44 @@ static struct sdio_dev_s *g_sdio_dev; +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void partition_handler(FAR struct partition_s *part, FAR void *arg) +{ + unsigned partition = *(int *)arg; + char devname[] = "/dev/mmcsd0p0"; + + if (partition < 10 && part->index == partition) + { + devname[sizeof(devname) - 2] = partition + 48; + register_blockpartition(devname, 0, "/dev/mmcsd0", part->firstblock, + part->nblocks); + } +} + /**************************************************************************** * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: mpfs_board_register_partition + * + * Description: + * Register partitions found in mmcsd0 + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int mpfs_board_register_partition(unsigned partition) +{ + return parse_block_partition("/dev/mmcsd0", partition_handler, &partition); +} + /**************************************************************************** * Name: board_emmcsd_init * diff --git a/boards/risc-v/mpfs/common/src/mpfs_usb.c b/boards/risc-v/mpfs/common/src/mpfs_usb.c index 627a5d71c951c..0c198aeb81bae 100644 --- a/boards/risc-v/mpfs/common/src/mpfs_usb.c +++ b/boards/risc-v/mpfs/common/src/mpfs_usb.c @@ -75,7 +75,7 @@ int mpfs_board_usb_init(void) return ret; } - if (board_composite_connect(0, 0) == NULL) + if (board_composite_connect(0, 1) == NULL) { syslog(LOG_ERR, "Failed to connect composite: %d\n", ret); return ret; diff --git a/boards/risc-v/mpfs/icicle/configs/knsh/defconfig b/boards/risc-v/mpfs/icicle/configs/knsh/defconfig index 4ffae40eb10db..0421b7398d800 100644 --- a/boards/risc-v/mpfs/icicle/configs/knsh/defconfig +++ b/boards/risc-v/mpfs/icicle/configs/knsh/defconfig @@ -78,6 +78,7 @@ CONFIG_NSH_FILE_APPS=y CONFIG_NSH_LINELEN=160 CONFIG_NSH_STRERROR=y CONFIG_NUTTSBI=y +CONFIG_NUTTSBI_IPI_BASE=0x02000000 CONFIG_NUTTSBI_MTIMECMP_BASE=0x02004000 CONFIG_NUTTSBI_MTIME_BASE=0x0200bff8 CONFIG_PREALLOC_TIMERS=4 diff --git a/boards/risc-v/mpfs/icicle/configs/rpmsg-ch1/defconfig b/boards/risc-v/mpfs/icicle/configs/rpmsg-ch1/defconfig index b7ee1caff5550..d9c0ffe27aacb 100644 --- a/boards/risc-v/mpfs/icicle/configs/rpmsg-ch1/defconfig +++ b/boards/risc-v/mpfs/icicle/configs/rpmsg-ch1/defconfig @@ -27,6 +27,7 @@ CONFIG_DEBUG_ASSERTIONS=y CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_SIMPLE_ADDRENV=y CONFIG_DEV_ZERO=y CONFIG_EXPERIMENTAL=y CONFIG_FAT_LCNAMES=y @@ -81,7 +82,6 @@ CONFIG_NSH_DISABLE_USLEEP=y CONFIG_NSH_DISABLE_WGET=y CONFIG_NSH_DISABLE_XD=y CONFIG_NSH_LINELEN=160 -CONFIG_OPENAMP=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=1048576 CONFIG_RAM_START=0xa2200000 diff --git a/boards/risc-v/mpfs/icicle/configs/rpmsg-ch2/defconfig b/boards/risc-v/mpfs/icicle/configs/rpmsg-ch2/defconfig index 961ad494f19d7..4a2d73e522ecf 100644 --- a/boards/risc-v/mpfs/icicle/configs/rpmsg-ch2/defconfig +++ b/boards/risc-v/mpfs/icicle/configs/rpmsg-ch2/defconfig @@ -27,6 +27,7 @@ CONFIG_DEBUG_ASSERTIONS=y CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_SIMPLE_ADDRENV=y CONFIG_DEV_ZERO=y CONFIG_EXPERIMENTAL=y CONFIG_FAT_LCNAMES=y @@ -80,7 +81,6 @@ CONFIG_NSH_DISABLE_USLEEP=y CONFIG_NSH_DISABLE_WGET=y CONFIG_NSH_DISABLE_XD=y CONFIG_NSH_LINELEN=160 -CONFIG_OPENAMP=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=1048576 CONFIG_RAM_START=0xa3200000 diff --git a/boards/risc-v/mpfs/icicle/configs/usb/defconfig b/boards/risc-v/mpfs/icicle/configs/usb/defconfig index f0a5002328536..c8360e3945e8f 100644 --- a/boards/risc-v/mpfs/icicle/configs/usb/defconfig +++ b/boards/risc-v/mpfs/icicle/configs/usb/defconfig @@ -90,7 +90,6 @@ CONFIG_NSH_DISABLE_USLEEP=y CONFIG_NSH_DISABLE_WGET=y CONFIG_NSH_DISABLE_XD=y CONFIG_NSH_LINELEN=160 -CONFIG_OPENAMP=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=1048576 CONFIG_RAM_START=0xa2200000 diff --git a/boards/risc-v/mpfs/icicle/scripts/ld-envm-opensbi.script b/boards/risc-v/mpfs/icicle/scripts/ld-envm-opensbi.script index 265db0c5ef158..419d441b776f6 100644 --- a/boards/risc-v/mpfs/icicle/scripts/ld-envm-opensbi.script +++ b/boards/risc-v/mpfs/icicle/scripts/ld-envm-opensbi.script @@ -36,12 +36,12 @@ SECTIONS PROVIDE(__l2lim_end = ORIGIN(l2lim) + LENGTH(l2lim)); .text.sbi : { - _ssbi_ddr = ABSOLUTE(.); + _ssbi_ram = ABSOLUTE(.); sbi* riscv_atomic* riscv_locks* riscv_asm* - _esbi_ddr = ABSOLUTE(.); + _esbi_ram = ABSOLUTE(.); . = ALIGN(0x2000); . += 16k; /* OpenSBI heap, aligned, at least 16k */ } > ddr diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/citest/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/citest/defconfig index 946b2bf7c4248..919e6ecd81efe 100644 --- a/boards/risc-v/qemu-rv/rv-virt/configs/citest/defconfig +++ b/boards/risc-v/qemu-rv/rv-virt/configs/citest/defconfig @@ -16,6 +16,7 @@ CONFIG_16550_UART0_CLOCK=3686400 CONFIG_16550_UART0_IRQ=37 CONFIG_16550_UART0_SERIAL_CONSOLE=y CONFIG_16550_UART=y +CONFIG_ALLOW_MIT_COMPONENTS=y CONFIG_ARCH="risc-v" CONFIG_ARCH_BOARD="rv-virt" CONFIG_ARCH_BOARD_QEMU_RV_VIRT=y @@ -27,33 +28,67 @@ CONFIG_ARCH_CHIP_QEMU_RV_ISA_C=y CONFIG_ARCH_CHIP_QEMU_RV_ISA_M=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_RISCV=y +CONFIG_ARCH_SETJMP_H=y CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=6366 CONFIG_BUILTIN=y +CONFIG_CANCELLATION_POINTS=y +CONFIG_CM_FS_TEST=y +CONFIG_CM_MM_TEST=y +CONFIG_CM_PTHREAD_TEST=y +CONFIG_CM_SCHED_TEST=y +CONFIG_CM_TIME_TEST=y CONFIG_DEBUG_ASSERTIONS=y CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_SIMPLE_ADDRENV=y CONFIG_DEV_ZERO=y +CONFIG_DRIVERS_VIRTIO=y +CONFIG_DRIVERS_VIRTIO_BLK=y +CONFIG_DRIVERS_VIRTIO_MMIO=y CONFIG_ELF=y +CONFIG_ETC_ROMFS=y CONFIG_EXAMPLES_HELLO=y CONFIG_EXAMPLES_HELLOXX=y CONFIG_EXAMPLES_PIPE=y CONFIG_EXAMPLES_POPEN=y +CONFIG_EXAMPLES_ROMFS=y CONFIG_EXAMPLES_USRSOCKTEST=y +CONFIG_FAT_LFN=y +CONFIG_FS_AIO=y +CONFIG_FS_FAT=y CONFIG_FS_HOSTFS=y +CONFIG_FS_NAMED_SEMAPHORES=y CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_FS_SHMFS=y +CONFIG_FS_TMPFS=y CONFIG_HAVE_CXX=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INTELHEX_BINARY=y +CONFIG_IOB_NBUFFERS=128 +CONFIG_IOB_NCHAINS=4 +CONFIG_LIBCXX=y +CONFIG_LIBCXXABI=y CONFIG_LIBC_ENVPATH=y CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBC_LOCALE_CATALOG=y +CONFIG_LIBC_LOCALTIME=y +CONFIG_LIBC_MAX_EXITFUNS=32 +CONFIG_LIBC_MEMFD_ERROR=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y +CONFIG_MM_IOB=y +CONFIG_MQ_MAXMSGSIZE=128 CONFIG_NET=y CONFIG_NETDEV_LATEINIT=y CONFIG_NETUTILS_NETINIT=y +CONFIG_NET_ICMP=y +CONFIG_NET_LOCAL=y CONFIG_NET_USRSOCK=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y @@ -63,21 +98,41 @@ CONFIG_NSH_READLINE=y CONFIG_PATH_INITIAL="/system/bin" CONFIG_PREALLOC_TIMERS=0 CONFIG_PSEUDOFS_SOFTLINKS=y +CONFIG_PTHREAD_CLEANUP_STACKSIZE=4 +CONFIG_PTHREAD_SPINLOCKS=y +CONFIG_PTHREAD_STACK_MIN=2048 CONFIG_RAM_SIZE=33554432 CONFIG_RAM_START=0x80000000 CONFIG_READLINE_CMD_HISTORY=y CONFIG_RISCV_SEMIHOSTING_HOSTFS=y -CONFIG_RR_INTERVAL=200 +CONFIG_RR_INTERVAL=10 +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPNTHREADS=1 CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_USER_IDENTITY=y CONFIG_SERIAL_UART_ARCH_MMIO=y +CONFIG_SIG_DEFAULT=y +CONFIG_SIG_EVTHREAD=y +CONFIG_SPINLOCK=y CONFIG_STACK_COLORATION=y CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_POPEN=y +CONFIG_TESTING_CMOCKA=y +CONFIG_TESTING_CXXTEST=y +CONFIG_TESTING_FMEMOPEN_TEST=y +CONFIG_TESTING_FOPENCOOKIE_TEST=y +CONFIG_TESTING_FSTEST=y CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_LTP=y CONFIG_TESTING_MM=y +CONFIG_TESTING_OPEN_MEMSTREAM=y CONFIG_TESTING_OSTEST=y +CONFIG_TESTING_SCANFTEST=y +CONFIG_TESTS_TESTSUITES=y +CONFIG_TLS_NELEM=8 CONFIG_USEC_PER_TICK=1000 diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/fb/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/fb/defconfig index 187efe1915d78..5b419054c63cf 100644 --- a/boards/risc-v/qemu-rv/rv-virt/configs/fb/defconfig +++ b/boards/risc-v/qemu-rv/rv-virt/configs/fb/defconfig @@ -69,7 +69,6 @@ CONFIG_NSH_READLINE=y CONFIG_NSH_SYMTAB=y CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" -CONFIG_OPENAMP=y CONFIG_PATH_INITIAL="/system/bin" CONFIG_RAM_SIZE=33554432 CONFIG_RAM_START=0x80000000 diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/fb64/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/fb64/defconfig index d3b4ab51484fe..add1402b9633d 100644 --- a/boards/risc-v/qemu-rv/rv-virt/configs/fb64/defconfig +++ b/boards/risc-v/qemu-rv/rv-virt/configs/fb64/defconfig @@ -69,7 +69,6 @@ CONFIG_NSH_READLINE=y CONFIG_NSH_SYMTAB=y CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" -CONFIG_OPENAMP=y CONFIG_PATH_INITIAL="/system/bin" CONFIG_RAM_SIZE=33554432 CONFIG_RAM_START=0x80000000 diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/kfb64/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/kfb64/defconfig new file mode 100644 index 0000000000000..d78ba1556b6cd --- /dev/null +++ b/boards/risc-v/qemu-rv/rv-virt/configs/kfb64/defconfig @@ -0,0 +1,110 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_16550_ADDRWIDTH=0 +CONFIG_16550_UART0=y +CONFIG_16550_UART0_BASE=0x10000000 +CONFIG_16550_UART0_CLOCK=3686400 +CONFIG_16550_UART0_IRQ=35 +CONFIG_16550_UART0_SERIAL_CONSOLE=y +CONFIG_16550_UART=y +CONFIG_ALLOW_BSD_COMPONENTS=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_ADDRENV=y +CONFIG_ARCH_BOARD="rv-virt" +CONFIG_ARCH_BOARD_QEMU_RV_VIRT=y +CONFIG_ARCH_CHIP="qemu-rv" +CONFIG_ARCH_CHIP_QEMU_RV64=y +CONFIG_ARCH_CHIP_QEMU_RV=y +CONFIG_ARCH_CHIP_QEMU_RV_ISA_A=y +CONFIG_ARCH_CHIP_QEMU_RV_ISA_C=y +CONFIG_ARCH_CHIP_QEMU_RV_ISA_M=y +CONFIG_ARCH_DATA_NPAGES=128 +CONFIG_ARCH_DATA_VBASE=0xC0100000 +CONFIG_ARCH_HEAP_NPAGES=128 +CONFIG_ARCH_HEAP_VBASE=0xC0200000 +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_KERNEL_STACKSIZE=3072 +CONFIG_ARCH_PGPOOL_MAPPING=y +CONFIG_ARCH_PGPOOL_PBASE=0x80600000 +CONFIG_ARCH_PGPOOL_SIZE=4194304 +CONFIG_ARCH_PGPOOL_VBASE=0x80600000 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_SHM_NPAGES=512 +CONFIG_ARCH_SHM_VBASE=0xC2000000 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_TEXT_NPAGES=128 +CONFIG_ARCH_TEXT_VBASE=0xC0000000 +CONFIG_ARCH_USE_MMU=y +CONFIG_ARCH_USE_MPU=y +CONFIG_ARCH_USE_S_MODE=y +CONFIG_BINFMT_ELF_EXECUTABLE=y +CONFIG_BOARDCTL_POWEROFF=y +CONFIG_BOARD_LOOPSPERMSEC=6366 +CONFIG_BUILD_KERNEL=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_SIMPLE_ADDRENV=y +CONFIG_DEV_ZERO=y +CONFIG_DRIVERS_VIDEO=y +CONFIG_DRIVERS_VIRTIO=y +CONFIG_DRIVERS_VIRTIO_GPU=y +CONFIG_DRIVERS_VIRTIO_MMIO=y +CONFIG_DRIVERS_VIRTIO_SERIAL=y +CONFIG_ELF=y +CONFIG_EXAMPLES_FB=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_HOSTFS=y +CONFIG_FS_LARGEFILE=y +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_FILEPATH="/system/bin/init" +CONFIG_INIT_MOUNT=y +CONFIG_INIT_MOUNT_DATA="fs=../apps" +CONFIG_INIT_MOUNT_FLAGS=0x1 +CONFIG_INIT_MOUNT_FSTYPE="hostfs" +CONFIG_INIT_MOUNT_SOURCE="" +CONFIG_INIT_MOUNT_TARGET="/system" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y +CONFIG_MEMSET_64BIT=y +CONFIG_MEMSET_OPTSPEED=y +CONFIG_MM_PGALLOC=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PATH_INITIAL="/system/bin" +CONFIG_RAM_SIZE=2097152 +CONFIG_RAM_START=0x80400000 +CONFIG_RAM_VSTART=0x80400000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RISCV_SEMIHOSTING_HOSTFS=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_UART_ARCH_MMIO=y +CONFIG_STACK_COLORATION=y +CONFIG_START_DAY=5 +CONFIG_START_MONTH=5 +CONFIG_START_YEAR=2024 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_PROGNAME="init" +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_VIDEO_FB=y diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/knetnsh64/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/knetnsh64/defconfig index 4096db7fe1556..99915a5889b95 100644 --- a/boards/risc-v/qemu-rv/rv-virt/configs/knetnsh64/defconfig +++ b/boards/risc-v/qemu-rv/rv-virt/configs/knetnsh64/defconfig @@ -32,16 +32,19 @@ CONFIG_ARCH_HEAP_VBASE=0xC0200000 CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_KERNEL_STACKSIZE=3072 CONFIG_ARCH_PGPOOL_MAPPING=y -CONFIG_ARCH_PGPOOL_PBASE=0x80400000 +CONFIG_ARCH_PGPOOL_PBASE=0x80600000 CONFIG_ARCH_PGPOOL_SIZE=4194304 -CONFIG_ARCH_PGPOOL_VBASE=0x80400000 +CONFIG_ARCH_PGPOOL_VBASE=0x80600000 CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RV_EXT_SSTC=y +CONFIG_ARCH_SETJMP_H=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_TEXT_NPAGES=128 CONFIG_ARCH_TEXT_VBASE=0xC0000000 CONFIG_ARCH_USE_MMU=y CONFIG_ARCH_USE_MPU=y CONFIG_ARCH_USE_S_MODE=y +CONFIG_BINFMT_ELF_EXECUTABLE=y CONFIG_BOARD_LOOPSPERMSEC=6366 CONFIG_BUILD_KERNEL=y CONFIG_CODECS_HASH_MD5=y @@ -79,6 +82,7 @@ CONFIG_LIBC_ENVPATH=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y CONFIG_MEMSET_64BIT=y CONFIG_MEMSET_OPTSPEED=y CONFIG_MM_PGALLOC=y @@ -111,11 +115,10 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_OPENAMP=y CONFIG_PATH_INITIAL="/system/bin" CONFIG_RAM_SIZE=2097152 -CONFIG_RAM_START=0x80200000 -CONFIG_RAM_VSTART=0x80200000 +CONFIG_RAM_START=0x80400000 +CONFIG_RAM_VSTART=0x80400000 CONFIG_READLINE_CMD_HISTORY=y CONFIG_RISCV_SEMIHOSTING_HOSTFS=y CONFIG_RR_INTERVAL=200 @@ -134,3 +137,4 @@ CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_PROGNAME="init" CONFIG_SYSTEM_PING=y CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/knetnsh64_smp/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/knetnsh64_smp/defconfig index 8121bce81e51c..b77ee69fc3aa9 100644 --- a/boards/risc-v/qemu-rv/rv-virt/configs/knetnsh64_smp/defconfig +++ b/boards/risc-v/qemu-rv/rv-virt/configs/knetnsh64_smp/defconfig @@ -32,16 +32,19 @@ CONFIG_ARCH_HEAP_VBASE=0xC0200000 CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_KERNEL_STACKSIZE=3072 CONFIG_ARCH_PGPOOL_MAPPING=y -CONFIG_ARCH_PGPOOL_PBASE=0x80400000 +CONFIG_ARCH_PGPOOL_PBASE=0x80600000 CONFIG_ARCH_PGPOOL_SIZE=4194304 -CONFIG_ARCH_PGPOOL_VBASE=0x80400000 +CONFIG_ARCH_PGPOOL_VBASE=0x80600000 CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RV_EXT_SSTC=y +CONFIG_ARCH_SETJMP_H=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_TEXT_NPAGES=128 CONFIG_ARCH_TEXT_VBASE=0xC0000000 CONFIG_ARCH_USE_MMU=y CONFIG_ARCH_USE_MPU=y CONFIG_ARCH_USE_S_MODE=y +CONFIG_BINFMT_ELF_EXECUTABLE=y CONFIG_BOARD_LOOPSPERMSEC=6366 CONFIG_BUILD_KERNEL=y CONFIG_CODECS_HASH_MD5=y @@ -80,6 +83,7 @@ CONFIG_LIBC_ENVPATH=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y CONFIG_MEMCPY_64BIT=y CONFIG_MEMCPY_VIK=y CONFIG_MEMSET_64BIT=y @@ -114,11 +118,10 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_OPENAMP=y CONFIG_PATH_INITIAL="/system/bin" CONFIG_RAM_SIZE=2097152 -CONFIG_RAM_START=0x80200000 -CONFIG_RAM_VSTART=0x80200000 +CONFIG_RAM_START=0x80400000 +CONFIG_RAM_VSTART=0x80400000 CONFIG_READLINE_CMD_HISTORY=y CONFIG_RISCV_SEMIHOSTING_HOSTFS=y CONFIG_RR_INTERVAL=200 @@ -138,4 +141,5 @@ CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_PROGNAME="init" CONFIG_SYSTEM_PING=y CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y CONFIG_TESTING_SMP=y diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/knsh32/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/knsh32/defconfig index 86d381bd078a6..8e088fe67cbcc 100644 --- a/boards/risc-v/qemu-rv/rv-virt/configs/knsh32/defconfig +++ b/boards/risc-v/qemu-rv/rv-virt/configs/knsh32/defconfig @@ -25,15 +25,15 @@ CONFIG_ARCH_CHIP_QEMU_RV_ISA_A=y CONFIG_ARCH_CHIP_QEMU_RV_ISA_C=y CONFIG_ARCH_CHIP_QEMU_RV_ISA_M=y CONFIG_ARCH_DATA_NPAGES=128 -CONFIG_ARCH_DATA_VBASE=0xC0400000 +CONFIG_ARCH_DATA_VBASE=0xC0100000 CONFIG_ARCH_HEAP_NPAGES=128 CONFIG_ARCH_HEAP_VBASE=0xC0800000 CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_KERNEL_STACKSIZE=3072 CONFIG_ARCH_PGPOOL_MAPPING=y -CONFIG_ARCH_PGPOOL_PBASE=0x80800000 +CONFIG_ARCH_PGPOOL_PBASE=0x80a00000 CONFIG_ARCH_PGPOOL_SIZE=4194304 -CONFIG_ARCH_PGPOOL_VBASE=0x80800000 +CONFIG_ARCH_PGPOOL_VBASE=0x80a00000 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_TEXT_NPAGES=128 @@ -41,8 +41,14 @@ CONFIG_ARCH_TEXT_VBASE=0xC0000000 CONFIG_ARCH_USE_MMU=y CONFIG_ARCH_USE_MPU=y CONFIG_ARCH_USE_S_MODE=y +CONFIG_BINFMT_ELF_EXECUTABLE=y +CONFIG_BOARDCTL_POWEROFF=y CONFIG_BOARD_LOOPSPERMSEC=6366 CONFIG_BUILD_KERNEL=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_ZERO=y CONFIG_ELF=y CONFIG_EXAMPLES_HELLO=m @@ -57,11 +63,11 @@ CONFIG_INIT_MOUNT_FSTYPE="hostfs" CONFIG_INIT_MOUNT_SOURCE="" CONFIG_INIT_MOUNT_TARGET="/system" CONFIG_INIT_STACKSIZE=3072 -CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_ENVPATH=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y CONFIG_MM_PGALLOC=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y @@ -70,7 +76,7 @@ CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y CONFIG_PATH_INITIAL="/system/bin" CONFIG_RAM_SIZE=4194304 -CONFIG_RAM_START=0x80400000 +CONFIG_RAM_START=0x80600000 CONFIG_READLINE_CMD_HISTORY=y CONFIG_RISCV_SEMIHOSTING_HOSTFS=y CONFIG_RR_INTERVAL=200 @@ -84,4 +90,5 @@ CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_PROGNAME="init" CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y CONFIG_USEC_PER_TICK=1000 diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/knsh32_paging/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/knsh32_paging/defconfig new file mode 100644 index 0000000000000..83d0b07e31dd8 --- /dev/null +++ b/boards/risc-v/qemu-rv/rv-virt/configs/knsh32_paging/defconfig @@ -0,0 +1,98 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ASSERTIONS_FILENAME is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NDEBUG is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_16550_ADDRWIDTH=0 +CONFIG_16550_UART0=y +CONFIG_16550_UART0_BASE=0x10000000 +CONFIG_16550_UART0_CLOCK=3686400 +CONFIG_16550_UART0_IRQ=35 +CONFIG_16550_UART0_SERIAL_CONSOLE=y +CONFIG_16550_UART=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_ADDRENV=y +CONFIG_ARCH_BOARD="rv-virt" +CONFIG_ARCH_BOARD_QEMU_RV_VIRT=y +CONFIG_ARCH_CHIP="qemu-rv" +CONFIG_ARCH_CHIP_QEMU_RV32=y +CONFIG_ARCH_CHIP_QEMU_RV=y +CONFIG_ARCH_CHIP_QEMU_RV_ISA_A=y +CONFIG_ARCH_CHIP_QEMU_RV_ISA_C=y +CONFIG_ARCH_CHIP_QEMU_RV_ISA_M=y +CONFIG_ARCH_DATA_NPAGES=128 +CONFIG_ARCH_DATA_VBASE=0xC0100000 +CONFIG_ARCH_HEAP_NPAGES=2048 +CONFIG_ARCH_HEAP_VBASE=0xC0800000 +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_KERNEL_STACKSIZE=3072 +CONFIG_ARCH_PGPOOL_MAPPING=y +CONFIG_ARCH_PGPOOL_PBASE=0x80a00000 +CONFIG_ARCH_PGPOOL_SIZE=4194304 +CONFIG_ARCH_PGPOOL_VBASE=0x80a00000 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RV_EXT_SSTC=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_TEXT_NPAGES=128 +CONFIG_ARCH_TEXT_VBASE=0xC0000000 +CONFIG_ARCH_USE_MMU=y +CONFIG_ARCH_USE_MPU=y +CONFIG_ARCH_USE_S_MODE=y +CONFIG_BINFMT_ELF_EXECUTABLE=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=6366 +CONFIG_BUILD_KERNEL=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_ZERO=y +CONFIG_ELF=y +CONFIG_EXAMPLES_HELLO=m +CONFIG_EXAMPLES_HELLO_STACKSIZE=8192 +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_GRAN_INTR=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_FILEPATH="/system/bin/init" +CONFIG_INIT_MOUNT=y +CONFIG_INIT_MOUNT_FLAGS=0x1 +CONFIG_INIT_MOUNT_TARGET="/system/bin" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y +CONFIG_MM_PGALLOC=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PAGING=y +CONFIG_PATH_INITIAL="/system/bin" +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=1048576 +CONFIG_RAM_SIZE=4194304 +CONFIG_RAM_START=0x80600000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_UART_ARCH_MMIO=y +CONFIG_SIG_DEFAULT=y +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2021 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSLOG_TIMESTAMP=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_PROGNAME="init" +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_TLS_LOG2_MAXSTACK=20 +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/knsh32_romfs/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/knsh32_romfs/defconfig new file mode 100644 index 0000000000000..3e4538546aa53 --- /dev/null +++ b/boards/risc-v/qemu-rv/rv-virt/configs/knsh32_romfs/defconfig @@ -0,0 +1,92 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ASSERTIONS_FILENAME is not set +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NDEBUG is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_16550_ADDRWIDTH=0 +CONFIG_16550_UART0=y +CONFIG_16550_UART0_BASE=0x10000000 +CONFIG_16550_UART0_CLOCK=3686400 +CONFIG_16550_UART0_IRQ=35 +CONFIG_16550_UART0_SERIAL_CONSOLE=y +CONFIG_16550_UART=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_ADDRENV=y +CONFIG_ARCH_BOARD="rv-virt" +CONFIG_ARCH_BOARD_QEMU_RV_VIRT=y +CONFIG_ARCH_CHIP="qemu-rv" +CONFIG_ARCH_CHIP_QEMU_RV32=y +CONFIG_ARCH_CHIP_QEMU_RV=y +CONFIG_ARCH_CHIP_QEMU_RV_ISA_A=y +CONFIG_ARCH_CHIP_QEMU_RV_ISA_C=y +CONFIG_ARCH_CHIP_QEMU_RV_ISA_M=y +CONFIG_ARCH_DATA_NPAGES=128 +CONFIG_ARCH_DATA_VBASE=0xC0100000 +CONFIG_ARCH_HEAP_NPAGES=128 +CONFIG_ARCH_HEAP_VBASE=0xC0800000 +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_KERNEL_STACKSIZE=3072 +CONFIG_ARCH_PGPOOL_MAPPING=y +CONFIG_ARCH_PGPOOL_PBASE=0x80a00000 +CONFIG_ARCH_PGPOOL_SIZE=4194304 +CONFIG_ARCH_PGPOOL_VBASE=0x80a00000 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RV_EXT_SSTC=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_TEXT_NPAGES=128 +CONFIG_ARCH_TEXT_VBASE=0xC0000000 +CONFIG_ARCH_USE_MMU=y +CONFIG_ARCH_USE_MPU=y +CONFIG_ARCH_USE_S_MODE=y +CONFIG_BINFMT_ELF_EXECUTABLE=y +CONFIG_BOARD_LATE_INITIALIZE=y +CONFIG_BOARD_LOOPSPERMSEC=6366 +CONFIG_BUILD_KERNEL=y +CONFIG_DEV_ZERO=y +CONFIG_ELF=y +CONFIG_EXAMPLES_HELLO=m +CONFIG_EXAMPLES_HELLO_STACKSIZE=8192 +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_FILEPATH="/system/bin/init" +CONFIG_INIT_MOUNT=y +CONFIG_INIT_MOUNT_FLAGS=0x1 +CONFIG_INIT_MOUNT_TARGET="/system/bin" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y +CONFIG_MM_PGALLOC=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PATH_INITIAL="/system/bin" +CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=8193 +CONFIG_RAM_SIZE=4194304 +CONFIG_RAM_START=0x80600000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_UART_ARCH_MMIO=y +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2021 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSLOG_TIMESTAMP=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_NSH_PROGNAME="init" +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/knsh64/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/knsh64/defconfig index b665b39c6e4b8..fca3035cc7506 100644 --- a/boards/risc-v/qemu-rv/rv-virt/configs/knsh64/defconfig +++ b/boards/risc-v/qemu-rv/rv-virt/configs/knsh64/defconfig @@ -31,9 +31,9 @@ CONFIG_ARCH_HEAP_VBASE=0xC0200000 CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_KERNEL_STACKSIZE=3072 CONFIG_ARCH_PGPOOL_MAPPING=y -CONFIG_ARCH_PGPOOL_PBASE=0x80400000 +CONFIG_ARCH_PGPOOL_PBASE=0x80600000 CONFIG_ARCH_PGPOOL_SIZE=4194304 -CONFIG_ARCH_PGPOOL_VBASE=0x80400000 +CONFIG_ARCH_PGPOOL_VBASE=0x80600000 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_TEXT_NPAGES=128 @@ -41,6 +41,8 @@ CONFIG_ARCH_TEXT_VBASE=0xC0000000 CONFIG_ARCH_USE_MMU=y CONFIG_ARCH_USE_MPU=y CONFIG_ARCH_USE_S_MODE=y +CONFIG_BINFMT_ELF_EXECUTABLE=y +CONFIG_BOARDCTL_POWEROFF=y CONFIG_BOARD_LOOPSPERMSEC=6366 CONFIG_BUILD_KERNEL=y CONFIG_DEBUG_ASSERTIONS=y @@ -61,11 +63,11 @@ CONFIG_INIT_MOUNT_FSTYPE="hostfs" CONFIG_INIT_MOUNT_SOURCE="" CONFIG_INIT_MOUNT_TARGET="/system" CONFIG_INIT_STACKSIZE=3072 -CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_ENVPATH=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y CONFIG_MEMSET_64BIT=y CONFIG_MEMSET_OPTSPEED=y CONFIG_MM_PGALLOC=y @@ -76,8 +78,8 @@ CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y CONFIG_PATH_INITIAL="/system/bin" CONFIG_RAM_SIZE=2097152 -CONFIG_RAM_START=0x80200000 -CONFIG_RAM_VSTART=0x80200000 +CONFIG_RAM_START=0x80400000 +CONFIG_RAM_VSTART=0x80400000 CONFIG_READLINE_CMD_HISTORY=y CONFIG_RISCV_SEMIHOSTING_HOSTFS=y CONFIG_RR_INTERVAL=200 @@ -92,4 +94,5 @@ CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_PROGNAME="init" CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y CONFIG_USEC_PER_TICK=1000 diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/ksmp64/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/ksmp64/defconfig index d9e9dcd111c1e..02474f42fdd6b 100644 --- a/boards/risc-v/qemu-rv/rv-virt/configs/ksmp64/defconfig +++ b/boards/risc-v/qemu-rv/rv-virt/configs/ksmp64/defconfig @@ -31,16 +31,18 @@ CONFIG_ARCH_HEAP_VBASE=0xC0200000 CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_KERNEL_STACKSIZE=3072 CONFIG_ARCH_PGPOOL_MAPPING=y -CONFIG_ARCH_PGPOOL_PBASE=0x80400000 +CONFIG_ARCH_PGPOOL_PBASE=0x80600000 CONFIG_ARCH_PGPOOL_SIZE=4194304 -CONFIG_ARCH_PGPOOL_VBASE=0x80400000 +CONFIG_ARCH_PGPOOL_VBASE=0x80600000 CONFIG_ARCH_RISCV=y +CONFIG_ARCH_RV_EXT_SSTC=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_TEXT_NPAGES=128 CONFIG_ARCH_TEXT_VBASE=0xC0000000 CONFIG_ARCH_USE_MMU=y CONFIG_ARCH_USE_MPU=y CONFIG_ARCH_USE_S_MODE=y +CONFIG_BINFMT_ELF_EXECUTABLE=y CONFIG_BOARD_LOOPSPERMSEC=6366 CONFIG_BUILD_KERNEL=y CONFIG_DEBUG_FULLOPT=y @@ -65,6 +67,7 @@ CONFIG_LIBC_ENVPATH=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y CONFIG_MEMSET_64BIT=y CONFIG_MEMSET_OPTSPEED=y CONFIG_MM_PGALLOC=y @@ -75,8 +78,8 @@ CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y CONFIG_PATH_INITIAL="/system/bin" CONFIG_RAM_SIZE=2097152 -CONFIG_RAM_START=0x80200000 -CONFIG_RAM_VSTART=0x80200000 +CONFIG_RAM_START=0x80400000 +CONFIG_RAM_VSTART=0x80400000 CONFIG_READLINE_CMD_HISTORY=y CONFIG_RISCV_SEMIHOSTING_HOSTFS=y CONFIG_RR_INTERVAL=200 @@ -93,4 +96,5 @@ CONFIG_SYSLOG_TIMESTAMP=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_PROGNAME="init" CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y CONFIG_TESTING_SMP=y diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/libcxx32/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/libcxx32/defconfig new file mode 100644 index 0000000000000..a29ab0705aead --- /dev/null +++ b/boards/risc-v/qemu-rv/rv-virt/configs/libcxx32/defconfig @@ -0,0 +1,69 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_16550_ADDRWIDTH=0 +CONFIG_16550_UART0=y +CONFIG_16550_UART0_BASE=0x10000000 +CONFIG_16550_UART0_CLOCK=3686400 +CONFIG_16550_UART0_IRQ=37 +CONFIG_16550_UART0_SERIAL_CONSOLE=y +CONFIG_16550_UART=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="rv-virt" +CONFIG_ARCH_BOARD_QEMU_RV_VIRT=y +CONFIG_ARCH_CHIP="qemu-rv" +CONFIG_ARCH_CHIP_QEMU_RV32=y +CONFIG_ARCH_CHIP_QEMU_RV=y +CONFIG_ARCH_CHIP_QEMU_RV_ISA_A=y +CONFIG_ARCH_CHIP_QEMU_RV_ISA_C=y +CONFIG_ARCH_CHIP_QEMU_RV_ISA_M=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6366 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_ZERO=y +CONFIG_ELF=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_HOSTFS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBCXX=y +CONFIG_LIBCXXABI=y +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PATH_INITIAL="/system/bin" +CONFIG_RAM_SIZE=33554432 +CONFIG_RAM_START=0x80000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RISCV_SEMIHOSTING_HOSTFS=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_UART_ARCH_MMIO=y +CONFIG_STACK_COLORATION=y +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2021 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_CXXTEST=y +CONFIG_TESTING_OSTEST=y +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/libcxx64/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/libcxx64/defconfig new file mode 100644 index 0000000000000..3600ca930cae9 --- /dev/null +++ b/boards/risc-v/qemu-rv/rv-virt/configs/libcxx64/defconfig @@ -0,0 +1,69 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_DISABLE_OS_API is not set +# CONFIG_NSH_DISABLE_LOSMART is not set +CONFIG_16550_ADDRWIDTH=0 +CONFIG_16550_UART0=y +CONFIG_16550_UART0_BASE=0x10000000 +CONFIG_16550_UART0_CLOCK=3686400 +CONFIG_16550_UART0_IRQ=37 +CONFIG_16550_UART0_SERIAL_CONSOLE=y +CONFIG_16550_UART=y +CONFIG_ARCH="risc-v" +CONFIG_ARCH_BOARD="rv-virt" +CONFIG_ARCH_BOARD_QEMU_RV_VIRT=y +CONFIG_ARCH_CHIP="qemu-rv" +CONFIG_ARCH_CHIP_QEMU_RV64=y +CONFIG_ARCH_CHIP_QEMU_RV=y +CONFIG_ARCH_CHIP_QEMU_RV_ISA_A=y +CONFIG_ARCH_CHIP_QEMU_RV_ISA_C=y +CONFIG_ARCH_CHIP_QEMU_RV_ISA_M=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_RISCV=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=6366 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_ZERO=y +CONFIG_ELF=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_FS_HOSTFS=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBCXX=y +CONFIG_LIBCXXABI=y +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBC_PERROR_STDOUT=y +CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y +CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PATH_INITIAL="/system/bin" +CONFIG_RAM_SIZE=33554432 +CONFIG_RAM_START=0x80000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_RISCV_SEMIHOSTING_HOSTFS=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SERIAL_UART_ARCH_MMIO=y +CONFIG_STACK_COLORATION=y +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2021 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_CXXTEST=y +CONFIG_TESTING_OSTEST=y +CONFIG_USEC_PER_TICK=1000 diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/netnsh/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/netnsh/defconfig index e7c1c9259cd12..8ee9a344527cb 100644 --- a/boards/risc-v/qemu-rv/rv-virt/configs/netnsh/defconfig +++ b/boards/risc-v/qemu-rv/rv-virt/configs/netnsh/defconfig @@ -95,7 +95,6 @@ CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" CONFIG_NXPLAYER_HTTP_STREAMING_SUPPORT=y CONFIG_NXPLAYER_MAINTHREAD_STACKSIZE=3072 -CONFIG_OPENAMP=y CONFIG_PATH_INITIAL="/system/bin" CONFIG_RAM_SIZE=33554432 CONFIG_RAM_START=0x80000000 @@ -117,6 +116,7 @@ CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_STACKSIZE=3072 CONFIG_SYSTEM_NXPLAYER=y +CONFIG_SYSTEM_NXRECORDER=y CONFIG_SYSTEM_PING=y CONFIG_TESTING_GETPRIME=y CONFIG_TESTING_OSTEST=y diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/netnsh64/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/netnsh64/defconfig index 743e893eb685f..8529b9fd19691 100644 --- a/boards/risc-v/qemu-rv/rv-virt/configs/netnsh64/defconfig +++ b/boards/risc-v/qemu-rv/rv-virt/configs/netnsh64/defconfig @@ -95,7 +95,7 @@ CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" CONFIG_NXPLAYER_HTTP_STREAMING_SUPPORT=y CONFIG_NXPLAYER_MAINTHREAD_STACKSIZE=3072 -CONFIG_OPENAMP=y +CONFIG_NXRECORDER_MAINTHREAD_STACKSIZE=3072 CONFIG_PATH_INITIAL="/system/bin" CONFIG_RAM_SIZE=33554432 CONFIG_RAM_START=0x80000000 @@ -117,6 +117,7 @@ CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_STACKSIZE=3072 CONFIG_SYSTEM_NXPLAYER=y +CONFIG_SYSTEM_NXRECORDER=y CONFIG_SYSTEM_PING=y CONFIG_TESTING_GETPRIME=y CONFIG_TESTING_OSTEST=y diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/netnsh64_smp/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/netnsh64_smp/defconfig index a2601227bf5d4..86462d4ce83f1 100644 --- a/boards/risc-v/qemu-rv/rv-virt/configs/netnsh64_smp/defconfig +++ b/boards/risc-v/qemu-rv/rv-virt/configs/netnsh64_smp/defconfig @@ -99,7 +99,7 @@ CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" CONFIG_NXPLAYER_HTTP_STREAMING_SUPPORT=y CONFIG_NXPLAYER_MAINTHREAD_STACKSIZE=3072 -CONFIG_OPENAMP=y +CONFIG_NXRECORDER_MAINTHREAD_STACKSIZE=3072 CONFIG_PATH_INITIAL="/system/bin" CONFIG_RAM_SIZE=33554432 CONFIG_RAM_START=0x80000000 @@ -122,6 +122,7 @@ CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_STACKSIZE=3072 CONFIG_SYSTEM_NXPLAYER=y +CONFIG_SYSTEM_NXRECORDER=y CONFIG_SYSTEM_PING=y CONFIG_TESTING_GETPRIME=y CONFIG_TESTING_OSTEST=y diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/netnsh_smp/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/netnsh_smp/defconfig index 0d6fc990af6c4..28d1f9ac7a850 100644 --- a/boards/risc-v/qemu-rv/rv-virt/configs/netnsh_smp/defconfig +++ b/boards/risc-v/qemu-rv/rv-virt/configs/netnsh_smp/defconfig @@ -99,7 +99,6 @@ CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" CONFIG_NXPLAYER_HTTP_STREAMING_SUPPORT=y CONFIG_NXPLAYER_MAINTHREAD_STACKSIZE=3072 -CONFIG_OPENAMP=y CONFIG_PATH_INITIAL="/system/bin" CONFIG_RAM_SIZE=33554432 CONFIG_RAM_START=0x80000000 @@ -122,6 +121,7 @@ CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_STACKSIZE=3072 CONFIG_SYSTEM_NXPLAYER=y +CONFIG_SYSTEM_NXRECORDER=y CONFIG_SYSTEM_PING=y CONFIG_TESTING_GETPRIME=y CONFIG_TESTING_OSTEST=y diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/nsh/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/nsh/defconfig index 4aa6358ebd55d..f3f3c075db2dd 100644 --- a/boards/risc-v/qemu-rv/rv-virt/configs/nsh/defconfig +++ b/boards/risc-v/qemu-rv/rv-virt/configs/nsh/defconfig @@ -26,29 +26,29 @@ CONFIG_ARCH_CHIP_QEMU_RV_ISA_M=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARDCTL_POWEROFF=y CONFIG_BOARD_LOOPSPERMSEC=6366 CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_ZERO=y CONFIG_ELF=y -CONFIG_EXAMPLES_HELLO=m +CONFIG_EXAMPLES_HELLO=y CONFIG_FS_HOSTFS=y CONFIG_FS_PROCFS=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_ENVPATH=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_SYMTAB=y -CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" CONFIG_PATH_INITIAL="/system/bin" CONFIG_RAM_SIZE=33554432 CONFIG_RAM_START=0x80000000 @@ -62,5 +62,6 @@ CONFIG_START_MONTH=12 CONFIG_START_YEAR=2021 CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y CONFIG_TESTING_OSTEST=y CONFIG_USEC_PER_TICK=1000 diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/nsh64/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/nsh64/defconfig index 37cd640d5fe23..68120193b9235 100644 --- a/boards/risc-v/qemu-rv/rv-virt/configs/nsh64/defconfig +++ b/boards/risc-v/qemu-rv/rv-virt/configs/nsh64/defconfig @@ -27,32 +27,31 @@ CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y CONFIG_BCH=y +CONFIG_BOARDCTL_POWEROFF=y CONFIG_BOARD_LOOPSPERMSEC=6366 CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEVICE_TREE=y CONFIG_DEV_ZERO=y CONFIG_ELF=y -CONFIG_EXAMPLES_HELLO=m +CONFIG_EXAMPLES_HELLO=y CONFIG_FS_HOSTFS=y CONFIG_FS_PROCFS=y CONFIG_IDLETHREAD_STACKSIZE=2048 CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INIT_STACKSIZE=3072 -CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_ENVPATH=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y +CONFIG_LIBM=y CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_READLINE=y -CONFIG_NSH_SYMTAB=y -CONFIG_NSH_SYMTAB_ARRAYNAME="g_symtab" -CONFIG_NSH_SYMTAB_COUNTNAME="g_nsymbols" CONFIG_PATH_INITIAL="/system/bin" CONFIG_RAM_SIZE=33554432 CONFIG_RAM_START=0x80000000 @@ -67,5 +66,6 @@ CONFIG_START_YEAR=2021 CONFIG_SYMTAB_ORDEREDBYNAME=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_NSH_STACKSIZE=3072 +CONFIG_TESTING_GETPRIME=y CONFIG_TESTING_OSTEST=y CONFIG_USEC_PER_TICK=1000 diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/smp/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/smp/defconfig index 72dac67156e5d..00c13282e896c 100644 --- a/boards/risc-v/qemu-rv/rv-virt/configs/smp/defconfig +++ b/boards/risc-v/qemu-rv/rv-virt/configs/smp/defconfig @@ -21,7 +21,6 @@ # CONFIG_NSH_DISABLE_CAT is not set # CONFIG_NSH_DISABLE_CD is not set # CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_HELP is not set # CONFIG_NSH_DISABLE_LOSMART is not set # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MOUNT is not set diff --git a/boards/risc-v/qemu-rv/rv-virt/configs/smp64/defconfig b/boards/risc-v/qemu-rv/rv-virt/configs/smp64/defconfig index a235e13ccb513..13fa9bf746e0b 100644 --- a/boards/risc-v/qemu-rv/rv-virt/configs/smp64/defconfig +++ b/boards/risc-v/qemu-rv/rv-virt/configs/smp64/defconfig @@ -21,7 +21,6 @@ # CONFIG_NSH_DISABLE_CAT is not set # CONFIG_NSH_DISABLE_CD is not set # CONFIG_NSH_DISABLE_FREE is not set -# CONFIG_NSH_DISABLE_HELP is not set # CONFIG_NSH_DISABLE_LOSMART is not set # CONFIG_NSH_DISABLE_LS is not set # CONFIG_NSH_DISABLE_MOUNT is not set @@ -44,6 +43,7 @@ CONFIG_ARCH_CHIP_QEMU_RV=y CONFIG_ARCH_CHIP_QEMU_RV_ISA_A=y CONFIG_ARCH_CHIP_QEMU_RV_ISA_C=y CONFIG_ARCH_CHIP_QEMU_RV_ISA_M=y +CONFIG_ARCH_CHIP_QEMU_RV_ISA_V=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_RISCV=y CONFIG_ARCH_STACKDUMP=y diff --git a/boards/risc-v/qemu-rv/rv-virt/include/nsh_romfsimg.h b/boards/risc-v/qemu-rv/rv-virt/include/nsh_romfsimg.h deleted file mode 100644 index 2531e9e47c027..0000000000000 --- a/boards/risc-v/qemu-rv/rv-virt/include/nsh_romfsimg.h +++ /dev/null @@ -1,25 +0,0 @@ -/**************************************************************************** - * boards/risc-v/qemu-rv/rv-virt/include/nsh_romfsimg.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_RISCV_QEMU_RV_RV_VIRT_INCLUDE_NSH_ROMFSIMG_H -#define __BOARDS_RISCV_QEMU_RV_RV_VIRT_INCLUDE_NSH_ROMFSIMG_H -extern const unsigned char romfs_img[]; -extern const unsigned int romfs_img_len; -#endif diff --git a/boards/risc-v/qemu-rv/rv-virt/scripts/Make.defs b/boards/risc-v/qemu-rv/rv-virt/scripts/Make.defs index 453bad37bc62c..53cc132fad17d 100644 --- a/boards/risc-v/qemu-rv/rv-virt/scripts/Make.defs +++ b/boards/risc-v/qemu-rv/rv-virt/scripts/Make.defs @@ -24,11 +24,7 @@ include $(TOPDIR)/arch/risc-v/src/common/Toolchain.defs ifeq ($(CONFIG_ARCH_CHIP_QEMU_RV),y) ifeq ($(CONFIG_BUILD_KERNEL),y) -ifeq ($(CONFIG_ARCH_CHIP_QEMU_RV64),y) - LDSCRIPT = ld-kernel64.script -else - LDSCRIPT = ld-kernel32.script -endif + LDSCRIPT = ld-kernel.script else LDSCRIPT = ld.script endif @@ -55,5 +51,25 @@ else LDELFFLAGS = --oformat elf64-littleriscv endif -LDELFFLAGS += -r -e main -LDELFFLAGS += -T $(call CONVERT_PATH,$(TOPDIR)/binfmt/libelf/gnu-elf.ld) +ifeq ($(CONFIG_BINFMT_ELF_RELOCATABLE),y) +LDELFFLAGS += -r +endif + +# POSTBUILD management + +# KERNEL builds need real ROMFS + +ifeq ($(CONFIG_BUILD_KERNEL),y) +ifeq ($(CONFIG_RISCV_SEMIHOSTING_HOSTFS),) +ifeq ($(wildcard $(BOARD_DIR)$(DELIM)src$(DELIM)romfs_boot.c),) +define POSTBUILD + $(Q) echo "Please replace stub ROMFS with real one." + $(Q) rm $(BOARD_DIR)$(DELIM)src$(DELIM)libboard.a +endef +else +define POSTBUILD + $(Q) echo "Please try nuttx.bin on target." +endef +endif +endif +endif diff --git a/boards/risc-v/qemu-rv/rv-virt/scripts/gnu-elf.ld b/boards/risc-v/qemu-rv/rv-virt/scripts/gnu-elf.ld new file mode 100644 index 0000000000000..d5e77d8e2c09c --- /dev/null +++ b/boards/risc-v/qemu-rv/rv-virt/scripts/gnu-elf.ld @@ -0,0 +1,131 @@ +/**************************************************************************** + * boards/risc-v/qemu-rv/rv-virt/scripts/gnu-elf.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +SECTIONS +{ + . = 0xC0000000; + .text : + { + _stext = . ; + *(.text) + *(.text.*) + *(.gnu.warning) + *(.stub) + *(.glue_7) + *(.glue_7t) + *(.jcr) + + /* C++ support: The .init and .fini sections contain specific logic + * to manage static constructors and destructors. + */ + + *(.gnu.linkonce.t.*) + *(.init) /* Old ABI */ + *(.fini) /* Old ABI */ + _etext = . ; + } + + .rodata : + { + _srodata = . ; + *(.rodata) + *(.rodata1) + *(.rodata.*) + *(.gnu.linkonce.r*) + _erodata = . ; + } + + . = 0xC0101000; + .data : + { + _sdata = . ; + *(.data) + *(.data1) + *(.data.*) + *(.gnu.linkonce.d*) + . = ALIGN(4); + _edata = . ; + } + + /* C++ support. For each global and static local C++ object, + * GCC creates a small subroutine to construct the object. Pointers + * to these routines (not the routines themselves) are stored as + * simple, linear arrays in the .ctors section of the object file. + * Similarly, pointers to global/static destructor routines are + * stored in .dtors. + */ + + .ctors : + { + _sctors = . ; + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _ectors = . ; + } + + .dtors : + { + _sdtors = . ; + KEEP (*(.dtors)) /* Old ABI: Unallocated */ + KEEP (*(.fini_array)) /* New ABI: Allocated */ + KEEP (*(SORT(.fini_array.*))) + _edtors = . ; + } + + .bss : + { + _sbss = . ; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.b*) + *(COMMON) + _ebss = . ; + } + + /* Thread local storage support */ + .tdata : { + _stdata = ABSOLUTE(.); + KEEP (*(.tdata .tdata.* .gnu.linkonce.td.*)); + _etdata = ABSOLUTE(.); + } + + .tbss : { + _stbss = ABSOLUTE(.); + KEEP (*(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon)); + _etbss = ABSOLUTE(.); + } + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/risc-v/qemu-rv/rv-virt/scripts/ld-kernel.script b/boards/risc-v/qemu-rv/rv-virt/scripts/ld-kernel.script new file mode 100644 index 0000000000000..193a833f3281d --- /dev/null +++ b/boards/risc-v/qemu-rv/rv-virt/scripts/ld-kernel.script @@ -0,0 +1,179 @@ +/**************************************************************************** + * boards/risc-v/qemu-rv/rv-virt/scripts/ld.script + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include + +#define KTEXT_ADDR 0x80200000 + +#ifdef CONFIG_ARCH_RV32 +#define KTEXT_SIZE 4194304 +#else +#define KTEXT_SIZE 2097152 +#endif + +#define KSRAM_ADDR (CONFIG_RAM_START) +#define KSRAM_SIZE (CONFIG_RAM_SIZE) +#define PGRAM_ADDR (CONFIG_ARCH_PGPOOL_PBASE) +#define PGRAM_SIZE (CONFIG_ARCH_PGPOOL_SIZE) + +MEMORY +{ + kflash (rx) : ORIGIN = KTEXT_ADDR, LENGTH = KTEXT_SIZE /* w/ cache */ + ksram (rwx) : ORIGIN = KSRAM_ADDR, LENGTH = KSRAM_SIZE /* w/ cache */ + pgram (rwx) : ORIGIN = PGRAM_ADDR, LENGTH = PGRAM_SIZE /* w/ cache */ +} + +OUTPUT_ARCH("riscv") + +/* Provide the kernel boundaries */ + +__kflash_start = ORIGIN(kflash); +__kflash_size = LENGTH(kflash); +__ksram_start = ORIGIN(ksram); +__ksram_size = LENGTH(ksram); +__ksram_end = ORIGIN(ksram) + LENGTH(ksram); + +/* Page heap */ + +__pgheap_start = ORIGIN(pgram); +__pgheap_size = LENGTH(pgram); + +SECTIONS +{ + . = 0x80000000; + + /* where the global variable out-of-bounds detection information located */ +#ifdef CONFIG_MM_KASAN_GLOBAL + .kasan.unused : + { + *(.data..LASANLOC*) + } + .kasan.global : + { + KEEP (*(.data..LASAN0)) + KEEP (*(.data.rel.local..LASAN0)) + } +#endif + + .text : + { + _stext = . ; + *(.text) + *(.text.*) + *(.gnu.warning) + *(.stub) + *(.glue_7) + *(.glue_7t) + *(.jcr) + + /* C++ support: The .init and .fini sections contain specific logic + * to manage static constructors and destructors. + */ + + *(.gnu.linkonce.t.*) + *(.init) /* Old ABI */ + *(.fini) /* Old ABI */ + _etext = . ; + } + + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } + + .rodata : + { + _srodata = . ; + *(.rodata) + *(.rodata1) + *(.rodata.*) + *(.gnu.linkonce.r*) + _erodata = . ; + } + + .tdata : { + _stdata = ABSOLUTE(.); + *(.tdata .tdata.* .gnu.linkonce.td.*); + _etdata = ABSOLUTE(.); + } + + .tbss : { + _stbss = ABSOLUTE(.); + *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); + _etbss = ABSOLUTE(.); + } + + _eronly = ABSOLUTE(.); + + .data : + { + _sdata = . ; + *(.data) + *(.data1) + *(.data.*) + *(.gnu.linkonce.d*) + . = ALIGN(4); + _edata = . ; + } + + /* Page tables here, align to 4K boundary */ + + .pgtables (NOLOAD) : ALIGN(0x1000) { + *(.pgtables) + . = ALIGN(4); + } > ksram + + .bss : + { + _sbss = . ; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.b*) + *(COMMON) + _ebss = . ; + } > ksram + + /* Stack top */ + + .stack_top : { + . = ALIGN(32); + _ebss = ABSOLUTE(.); + } > ksram + + /* Stabs debugging sections. */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/boards/risc-v/qemu-rv/rv-virt/scripts/ld-kernel32.script b/boards/risc-v/qemu-rv/rv-virt/scripts/ld-kernel32.script deleted file mode 100644 index ae9c92bfb01b7..0000000000000 --- a/boards/risc-v/qemu-rv/rv-virt/scripts/ld-kernel32.script +++ /dev/null @@ -1,143 +0,0 @@ -/**************************************************************************** - * boards/risc-v/qemu-rv/rv-virt/scripts/ld.script - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -MEMORY -{ - kflash (rx) : ORIGIN = 0x80000000, LENGTH = 4096K /* w/ cache */ - ksram (rwx) : ORIGIN = 0x80400000, LENGTH = 4096K /* w/ cache */ - pgram (rwx) : ORIGIN = 0x80800000, LENGTH = 4096K /* w/ cache */ -} - -OUTPUT_ARCH("riscv") - -/* Provide the kernel boundaries */ - -__kflash_start = ORIGIN(kflash); -__kflash_size = LENGTH(kflash); -__ksram_start = ORIGIN(ksram); -__ksram_size = LENGTH(ksram); -__ksram_end = ORIGIN(ksram) + LENGTH(ksram); - -/* Page heap */ - -__pgheap_start = ORIGIN(pgram); -__pgheap_size = LENGTH(pgram); - -SECTIONS -{ - . = 0x80000000; - - .text : - { - _stext = . ; - *(.text) - *(.text.*) - *(.gnu.warning) - *(.stub) - *(.glue_7) - *(.glue_7t) - *(.jcr) - - /* C++ support: The .init and .fini sections contain specific logic - * to manage static constructors and destructors. - */ - - *(.gnu.linkonce.t.*) - *(.init) /* Old ABI */ - *(.fini) /* Old ABI */ - _etext = . ; - } - - .rodata : - { - _srodata = . ; - *(.rodata) - *(.rodata1) - *(.rodata.*) - *(.gnu.linkonce.r*) - _erodata = . ; - } - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } - - _eronly = ABSOLUTE(.); - - .data : - { - _sdata = . ; - *(.data) - *(.data1) - *(.data.*) - *(.gnu.linkonce.d*) - . = ALIGN(4); - _edata = . ; - } - - /* Page tables here, align to 4K boundary */ - - .pgtables (NOLOAD) : ALIGN(0x1000) { - *(.pgtables) - . = ALIGN(4); - } > ksram - - .bss : - { - _sbss = . ; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.b*) - *(COMMON) - _ebss = . ; - } > ksram - - /* Stack top */ - - .stack_top : { - . = ALIGN(32); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/risc-v/qemu-rv/rv-virt/scripts/ld-kernel64.script b/boards/risc-v/qemu-rv/rv-virt/scripts/ld-kernel64.script deleted file mode 100644 index bfab060ee6845..0000000000000 --- a/boards/risc-v/qemu-rv/rv-virt/scripts/ld-kernel64.script +++ /dev/null @@ -1,143 +0,0 @@ -/**************************************************************************** - * boards/risc-v/qemu-rv/rv-virt/scripts/ld.script - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -MEMORY -{ - kflash (rx) : ORIGIN = 0x80000000, LENGTH = 2048K /* w/ cache */ - ksram (rwx) : ORIGIN = 0x80200000, LENGTH = 2048K /* w/ cache */ - pgram (rwx) : ORIGIN = 0x80400000, LENGTH = 4096K /* w/ cache */ -} - -OUTPUT_ARCH("riscv") - -/* Provide the kernel boundaries */ - -__kflash_start = ORIGIN(kflash); -__kflash_size = LENGTH(kflash); -__ksram_start = ORIGIN(ksram); -__ksram_size = LENGTH(ksram); -__ksram_end = ORIGIN(ksram) + LENGTH(ksram); - -/* Page heap */ - -__pgheap_start = ORIGIN(pgram); -__pgheap_size = LENGTH(pgram); - -SECTIONS -{ - . = 0x80000000; - - .text : - { - _stext = . ; - *(.text) - *(.text.*) - *(.gnu.warning) - *(.stub) - *(.glue_7) - *(.glue_7t) - *(.jcr) - - /* C++ support: The .init and .fini sections contain specific logic - * to manage static constructors and destructors. - */ - - *(.gnu.linkonce.t.*) - *(.init) /* Old ABI */ - *(.fini) /* Old ABI */ - _etext = . ; - } - - .rodata : - { - _srodata = . ; - *(.rodata) - *(.rodata1) - *(.rodata.*) - *(.gnu.linkonce.r*) - _erodata = . ; - } - - .tdata : { - _stdata = ABSOLUTE(.); - *(.tdata .tdata.* .gnu.linkonce.td.*); - _etdata = ABSOLUTE(.); - } - - .tbss : { - _stbss = ABSOLUTE(.); - *(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon); - _etbss = ABSOLUTE(.); - } - - _eronly = ABSOLUTE(.); - - .data : - { - _sdata = . ; - *(.data) - *(.data1) - *(.data.*) - *(.gnu.linkonce.d*) - . = ALIGN(4); - _edata = . ; - } - - .bss : - { - _sbss = . ; - *(.bss) - *(.bss.*) - *(.sbss) - *(.sbss.*) - *(.gnu.linkonce.b*) - *(COMMON) - _ebss = . ; - } > ksram - - /* Page tables here, align to 4K boundary */ - - .pgtables (NOLOAD) : ALIGN(0x1000) { - *(.pgtables) - . = ALIGN(4); - } > ksram - - /* Stack top */ - - .stack_top : { - . = ALIGN(32); - _ebss = ABSOLUTE(.); - } > ksram - - /* Stabs debugging sections. */ - - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_info 0 : { *(.debug_info) } - .debug_line 0 : { *(.debug_line) } - .debug_pubnames 0 : { *(.debug_pubnames) } - .debug_aranges 0 : { *(.debug_aranges) } -} diff --git a/boards/risc-v/qemu-rv/rv-virt/scripts/ld.script b/boards/risc-v/qemu-rv/rv-virt/scripts/ld.script index 664bbb178f1d7..95d38cf3a93ae 100644 --- a/boards/risc-v/qemu-rv/rv-virt/scripts/ld.script +++ b/boards/risc-v/qemu-rv/rv-virt/scripts/ld.script @@ -22,6 +22,19 @@ SECTIONS { . = 0x80000000; + /* where the global variable out-of-bounds detection information located */ +#ifdef CONFIG_MM_KASAN_GLOBAL + .kasan.unused : + { + *(.data..LASANLOC*) + } + .kasan.global : + { + KEEP (*(.data..LASAN0)) + KEEP (*(.data.rel.local..LASAN0)) + } +#endif + .text : { _stext = . ; @@ -43,6 +56,14 @@ SECTIONS _etext = . ; } + .init_section : + { + _sinit = ABSOLUTE(.); + KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP(*(.init_array .ctors)) + _einit = ABSOLUTE(.); + } + .rodata : { _srodata = . ; @@ -78,30 +99,6 @@ SECTIONS _edata = . ; } - /* C++ support. For each global and static local C++ object, - * GCC creates a small subroutine to construct the object. Pointers - * to these routines (not the routines themselves) are stored as - * simple, linear arrays in the .ctors section of the object file. - * Similarly, pointers to global/static destructor routines are - * stored in .dtors. - */ - - .ctors : - { - _sctors = . ; - *(.ctors) /* Old ABI: Unallocated */ - *(.init_array) /* New ABI: Allocated */ - _edtors = . ; - } - - .dtors : - { - _sdtors = . ; - *(.dtors) /* Old ABI: Unallocated */ - *(.fini_array) /* New ABI: Allocated */ - _edtors = . ; - } - .bss : { _sbss = . ; @@ -111,6 +108,7 @@ SECTIONS *(.sbss.*) *(.gnu.linkonce.b*) *(COMMON) + . = ALIGN(32); _ebss = . ; } diff --git a/boards/risc-v/qemu-rv/rv-virt/src/.gitignore b/boards/risc-v/qemu-rv/rv-virt/src/.gitignore index cc92d189b53c2..57a29acdfd346 100644 --- a/boards/risc-v/qemu-rv/rv-virt/src/.gitignore +++ b/boards/risc-v/qemu-rv/rv-virt/src/.gitignore @@ -1,2 +1,3 @@ etctmp etctmp.c +romfs_boot.c diff --git a/boards/risc-v/qemu-rv/rv-virt/src/CMakeLists.txt b/boards/risc-v/qemu-rv/rv-virt/src/CMakeLists.txt index c4ba3579b458e..f33cd75cef778 100644 --- a/boards/risc-v/qemu-rv/rv-virt/src/CMakeLists.txt +++ b/boards/risc-v/qemu-rv/rv-virt/src/CMakeLists.txt @@ -25,11 +25,7 @@ target_sources(board PRIVATE ${SRCS}) if(CONFIG_ARCH_CHIP_QEMU_RV) if(CONFIG_BUILD_KERNEL) - if(CONFIG_ARCH_CHIP_QEMU_RV64) - set(LDFILE ld-kernel64.script) - else() - set(LDFILE ld-kernel32.script) - endif() + set(LDFILE ld-kernel.script) else() set(LDFILE ld.script) endif() diff --git a/boards/risc-v/qemu-rv/rv-virt/src/Makefile b/boards/risc-v/qemu-rv/rv-virt/src/Makefile index dc09f91be700c..f49f361f52f97 100644 --- a/boards/risc-v/qemu-rv/rv-virt/src/Makefile +++ b/boards/risc-v/qemu-rv/rv-virt/src/Makefile @@ -24,4 +24,19 @@ RCSRCS = etc/init.d/rc.sysinit etc/init.d/rcS CSRCS = qemu_rv_appinit.c +ifeq ($(CONFIG_BUILD_KERNEL),y) +ifeq ($(CONFIG_RISCV_SEMIHOSTING_HOSTFS),) +CSRCS += $(if $(wildcard romfs_boot.c), romfs_boot.c, romfs_stub.c) +endif +endif + include $(TOPDIR)/boards/Board.mk + +# don't use single-colon targets as they may coflict with those included ones. +# use double-colon targets to avoid collisions below. + +ifeq ($(CONFIG_BUILD_KERNEL),y) +.PHONY: clean +clean:: + $(call DELFILE, romfs_boot.c) +endif diff --git a/boards/risc-v/qemu-rv/rv-virt/src/qemu_rv_appinit.c b/boards/risc-v/qemu-rv/rv-virt/src/qemu_rv_appinit.c index e8f61fc38fd38..fb3292a84a2a9 100644 --- a/boards/risc-v/qemu-rv/rv-virt/src/qemu_rv_appinit.c +++ b/boards/risc-v/qemu-rv/rv-virt/src/qemu_rv_appinit.c @@ -28,12 +28,21 @@ #include #include #include +#include #include +#include #include #include +#ifndef CONFIG_BUILD_KERNEL +#include "hardware/qemu_rv_memorymap.h" +#include "qemu_rv_memorymap.h" +#endif +#include "riscv_internal.h" +#include "romfs.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -47,6 +56,9 @@ #endif #define QEMU_VIRTIO_MMIO_NUM 8 +#define SECTORSIZE 512 +#define NSECTORS(b) (((b) + SECTORSIZE - 1) / SECTORSIZE) + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -108,7 +120,13 @@ int board_app_initialize(uintptr_t arg) #ifdef CONFIG_NSH_ARCHINIT +#ifdef CONFIG_FS_PROCFS mount(NULL, "/proc", "procfs", 0, NULL); +#endif + +#ifdef CONFIG_FS_TMPFS + mount(NULL, "/tmp", "tmpfs", 0, NULL); +#endif #endif @@ -119,3 +137,62 @@ int board_app_initialize(uintptr_t arg) return OK; #endif } + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called after up_initialize() and board_early_initialize() and just + * before the initial application is started. This additional + * initialization phase may be used, for example, to initialize board- + * specific device drivers for which board_early_initialize() is not + * suitable. + * + * Waiting for events, use of I2C, SPI, etc are permissible in the context + * of board_late_initialize(). That is because board_late_initialize() + * will run on a temporary, internal kernel thread. + * + ****************************************************************************/ + +void board_late_initialize(void) +{ + /* Perform board-specific initialization */ + +#if defined(CONFIG_BUILD_KERNEL) && !defined(CONFIG_RISCV_SEMIHOSTING_HOSTFS) + /* Create ROM disk for mount in nx_start_application */ + + if (NSECTORS(romfs_img_len) > 1) + { + int ret = OK; + ret = romdisk_register(0, romfs_img, NSECTORS(romfs_img_len), + SECTORSIZE); + if (ret < 0) + { + ferr("ERROR: Failed to register romfs: %d\n", -ret); + } + } +#endif /* CONFIG_BUILD_KERNEL && !CONFIG_RISCV_SEMIHOSTING_HOSTFS */ + +#ifdef CONFIG_NSH_ARCHINIT + + mount(NULL, "/proc", "procfs", 0, NULL); + +#endif +} + +#ifdef CONFIG_BOARDCTL_POWEROFF +int board_power_off(int status) +{ +#ifdef CONFIG_BUILD_KERNEL + riscv_sbi_system_reset(SBI_SRST_TYPE_SHUTDOWN, SBI_SRST_REASON_NONE); +#else + *(FAR volatile uint32_t *)QEMU_RV_RESET_BASE = QEMU_RV_RESET_DONE; +#endif + + UNUSED(status); + return 0; +} +#endif diff --git a/boards/risc-v/qemu-rv/rv-virt/src/romfs.h b/boards/risc-v/qemu-rv/rv-virt/src/romfs.h new file mode 100644 index 0000000000000..746170cba0ce1 --- /dev/null +++ b/boards/risc-v/qemu-rv/rv-virt/src/romfs.h @@ -0,0 +1,39 @@ +/**************************************************************************** + * boards/risc-v/qemu-rv/rv-virt/src/romfs.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_RISC_V_QEMU_RV_RV_VIRT_SRC_ROMFS_H +#define __BOARDS_RISC_V_QEMU_RV_RV_VIRT_SRC_ROMFS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +extern const unsigned char romfs_img[]; +extern const unsigned int romfs_img_len; + +#endif /* __BOARDS_RISC_V_QEMU_RV_RV_VIRT_SRC_ROMFS_H */ diff --git a/boards/risc-v/qemu-rv/rv-virt/src/romfs_stub.c b/boards/risc-v/qemu-rv/rv-virt/src/romfs_stub.c new file mode 100644 index 0000000000000..8d47136f28476 --- /dev/null +++ b/boards/risc-v/qemu-rv/rv-virt/src/romfs_stub.c @@ -0,0 +1,38 @@ +/**************************************************************************** + * boards/risc-v/qemu-rv/rv-virt/src/romfs_stub.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +weak_data const unsigned char aligned_data(4) romfs_img[] = +{ + 0x00 +}; +weak_data const unsigned int romfs_img_len = 1; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/boards/sim/sim/sim/Kconfig b/boards/sim/sim/sim/Kconfig index a6b54741628e2..d68906cbd3d24 100644 --- a/boards/sim/sim/sim/Kconfig +++ b/boards/sim/sim/sim/Kconfig @@ -10,10 +10,10 @@ config EXAMPLES_TOUCHSCREEN_BGCOLOR default 0x007b68ee depends on EXAMPLES_TOUCHSCREEN -config SIM_RPTUN_MASTER - bool "Remote Processor Tunneling Role" +config SIM_RPMSG_MASTER + bool "Rpmsg Master" default n - depends on RPTUN + depends on RPMSG if SIM_TOUCHSCREEN diff --git a/boards/sim/sim/sim/configs/adb/defconfig b/boards/sim/sim/sim/configs/adb/defconfig index 088b0094e6aa2..28bdb43e18780 100644 --- a/boards/sim/sim/sim/configs/adb/defconfig +++ b/boards/sim/sim/sim/configs/adb/defconfig @@ -7,7 +7,6 @@ # # CONFIG_NET_ETHERNET is not set CONFIG_ADBD_FILE_SERVICE=y -CONFIG_ADBD_FILE_SYMLINK=y CONFIG_ADBD_LOGCAT_SERVICE=y CONFIG_ADBD_SHELL_SERVICE=y CONFIG_ADBD_SOCKET_SERVICE=y @@ -24,6 +23,7 @@ CONFIG_FS_PROCFS=y CONFIG_FS_TMPFS=y CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_LIBC_DLFCN=y +CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBUV=y CONFIG_LIBUV_UTILS_TEST=y CONFIG_MM_BACKTRACE=8 @@ -44,6 +44,7 @@ CONFIG_NSH_CONSOLE_LOGIN=y CONFIG_NSH_READLINE=y CONFIG_NSH_TELNET_LOGIN=y CONFIG_PSEUDOFS_SOFTLINKS=y +CONFIG_PSEUDOTERM=y CONFIG_RAMLOG=y CONFIG_RAMLOG_SYSLOG=y CONFIG_READLINE_CMD_HISTORY=y diff --git a/boards/sim/sim/sim/configs/alsa/defconfig b/boards/sim/sim/sim/configs/alsa/defconfig index 60fb1a63e4784..d98ffd9e9823a 100644 --- a/boards/sim/sim/sim/configs/alsa/defconfig +++ b/boards/sim/sim/sim/configs/alsa/defconfig @@ -20,6 +20,9 @@ CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_HELLO=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y @@ -36,13 +39,9 @@ CONFIG_LIBC_ENVPATH=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_MAX_EXITFUNS=1 CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_READLINE_TABCOMPLETION=y CONFIG_SCHED_HAVE_PARENT=y diff --git a/boards/sim/sim/sim/configs/bas/defconfig b/boards/sim/sim/sim/configs/bas/defconfig index ca916c87d69e9..657eb8b0d9c39 100644 --- a/boards/sim/sim/sim/configs/bas/defconfig +++ b/boards/sim/sim/sim/configs/bas/defconfig @@ -15,6 +15,9 @@ CONFIG_BOARD_LOOPSPERMSEC=0 CONFIG_BOOT_RUNFROMEXTSRAM=y CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y @@ -29,11 +32,8 @@ CONFIG_LIBC_MAX_EXITFUNS=1 CONFIG_LIBM=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_SCHED_HAVE_PARENT=y CONFIG_SCHED_WAITPID=y diff --git a/boards/sim/sim/sim/configs/bastest/defconfig b/boards/sim/sim/sim/configs/bastest/defconfig index 50dadd987355a..f28fbf3f00b5c 100644 --- a/boards/sim/sim/sim/configs/bastest/defconfig +++ b/boards/sim/sim/sim/configs/bastest/defconfig @@ -13,12 +13,16 @@ CONFIG_ARCH_CHIP="sim" CONFIG_ARCH_SIM=y CONFIG_BOARDCTL_APP_SYMTAB=y CONFIG_BOARDCTL_POWEROFF=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=0 CONFIG_BOOT_RUNFROMEXTSRAM=y CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_BASTEST=y CONFIG_EXAMPLES_BASTEST_DEVMINOR=6 CONFIG_EXAMPLES_BASTEST_DEVPATH="/dev/ram6" @@ -40,16 +44,12 @@ CONFIG_LIBC_MAX_EXITFUNS=1 CONFIG_LIBC_STRERROR=y CONFIG_LIBM=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_CONSOLE_LOGIN=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_MOTD=y CONFIG_NSH_MOTD_STRING="MOTD: username=admin password=Administrator" CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_READLINE_TABCOMPLETION=y CONFIG_SCHED_HAVE_PARENT=y diff --git a/boards/sim/sim/sim/configs/bluetooth/defconfig b/boards/sim/sim/sim/configs/bluetooth/defconfig index 6a30af2d7b8d3..0d8e46f00d567 100644 --- a/boards/sim/sim/sim/configs/bluetooth/defconfig +++ b/boards/sim/sim/sim/configs/bluetooth/defconfig @@ -26,6 +26,9 @@ CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y CONFIG_DRIVERS_BLUETOOTH=y CONFIG_DRIVERS_WIRELESS=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_HELLO=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y @@ -47,13 +50,9 @@ CONFIG_NETINIT_NETLOCAL=y CONFIG_NET_BLUETOOTH=y CONFIG_NET_STATISTICS=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_PREALLOC_MQ_MSGS=64 CONFIG_READLINE_TABCOMPLETION=y diff --git a/boards/sim/sim/sim/configs/bthcisock/defconfig b/boards/sim/sim/sim/configs/bthcisock/defconfig index ba512382ec44d..9bbf26d83e5b7 100644 --- a/boards/sim/sim/sim/configs/bthcisock/defconfig +++ b/boards/sim/sim/sim/configs/bthcisock/defconfig @@ -27,6 +27,9 @@ CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y CONFIG_DRIVERS_BLUETOOTH=y CONFIG_DRIVERS_WIRELESS=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_HELLO=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y @@ -48,13 +51,9 @@ CONFIG_NETINIT_NETLOCAL=y CONFIG_NET_BLUETOOTH=y CONFIG_NET_STATISTICS=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_PREALLOC_MQ_MSGS=64 CONFIG_READLINE_TABCOMPLETION=y diff --git a/boards/sim/sim/sim/configs/btuart/defconfig b/boards/sim/sim/sim/configs/btuart/defconfig index feebe89b94a71..94e4e0a063286 100644 --- a/boards/sim/sim/sim/configs/btuart/defconfig +++ b/boards/sim/sim/sim/configs/btuart/defconfig @@ -17,14 +17,13 @@ CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DRIVERS_BLUETOOTH=y CONFIG_DRIVERS_WIRELESS=y +CONFIG_ETC_ROMFS=y CONFIG_FS_PROCFS=y CONFIG_FS_ROMFS=y CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSETC=y CONFIG_SCHED_HAVE_PARENT=y CONFIG_SCHED_WAITPID=y CONFIG_SIM_HCISOCKET=y diff --git a/boards/sim/sim/sim/configs/citest/defconfig b/boards/sim/sim/sim/configs/citest/defconfig index 70ffa16a74e55..c67f4eae55acf 100644 --- a/boards/sim/sim/sim/configs/citest/defconfig +++ b/boards/sim/sim/sim/configs/citest/defconfig @@ -8,6 +8,7 @@ # CONFIG_NET_ARP is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_NSH_NETINIT is not set +CONFIG_ALLOW_MIT_COMPONENTS=y CONFIG_ALLSYMS=y CONFIG_ARCH="sim" CONFIG_ARCH_BOARD="sim" @@ -17,77 +18,133 @@ CONFIG_ARCH_MATH_H=y CONFIG_ARCH_SIM=y CONFIG_BOARDCTL_APP_SYMTAB=y CONFIG_BOARDCTL_POWEROFF=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=0 CONFIG_BOOT_RUNFROMEXTSRAM=y CONFIG_BUILTIN=y +CONFIG_CANCELLATION_POINTS=y +CONFIG_CM_FS_TEST=y +CONFIG_CM_MM_TEST=y +CONFIG_CM_PTHREAD_TEST=y +CONFIG_CM_SCHED_TEST=y +CONFIG_CM_TIME_TEST=y CONFIG_DEBUG_ASSERTIONS=y CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_GPIO=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y CONFIG_EXAMPLES_GPIO=y CONFIG_EXAMPLES_HELLO=y CONFIG_EXAMPLES_HELLOXX=y CONFIG_EXAMPLES_PIPE=y CONFIG_EXAMPLES_POPEN=y +CONFIG_EXAMPLES_ROMFS=y CONFIG_EXAMPLES_USRSOCKTEST=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y +CONFIG_FRAME_POINTER=y CONFIG_FSUTILS_PASSWD=y CONFIG_FSUTILS_PASSWD_READONLY=y +CONFIG_FS_AIO=y CONFIG_FS_BINFS=y CONFIG_FS_FAT=y +CONFIG_FS_HOSTFS=y +CONFIG_FS_NAMED_SEMAPHORES=y CONFIG_FS_PROCFS=y CONFIG_FS_RAMMAP=y CONFIG_FS_ROMFS=y +CONFIG_FS_SHMFS=y +CONFIG_FS_TMPFS=y CONFIG_GPIO_LOWER_HALF=y CONFIG_HAVE_CXX=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_IOB_NBUFFERS=128 +CONFIG_IOB_NCHAINS=4 CONFIG_IOEXPANDER=y CONFIG_IOEXPANDER_DUMMY=y CONFIG_LIBCXX=y +CONFIG_LIBC_DLFCN=y CONFIG_LIBC_ENVPATH=y CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBC_LOCALE_CATALOG=y CONFIG_LIBC_LOCALE_GETTEXT=y -CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_LIBC_LOCALTIME=y +CONFIG_LIBC_MAX_EXITFUNS=32 +CONFIG_LIBC_MEMFD_ERROR=y +CONFIG_LIBC_NETDB=y CONFIG_LIBC_NUMBERED_ARGS=y CONFIG_LIBC_SCANSET=y +CONFIG_LIBUV=y +CONFIG_LIBUV_THREADPOOL_SIZE=4 +CONFIG_LIBUV_THREAD_STACKSIZE=16384 +CONFIG_LIBUV_UTILS_STACKSIZE=65536 +CONFIG_LIBUV_UTILS_TEST=y +CONFIG_MM_IOB=y +CONFIG_MQ_MAXMSGSIZE=128 CONFIG_NET=y +CONFIG_NETDEV_HPWORK_THREAD=y +CONFIG_NETDEV_IFINDEX=y +CONFIG_NETDEV_LATEINIT=y +CONFIG_NET_ICMP=y +CONFIG_NET_LOCAL=y CONFIG_NET_USRSOCK=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 -CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_DISABLE_DATE=y +CONFIG_NSH_DISABLE_TIMEDATECTL=y CONFIG_NSH_MOTD=y CONFIG_NSH_MOTD_STRING="MOTD: username=admin password=Administrator" CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" +CONFIG_PM=y +CONFIG_PM_RUNTIME=y CONFIG_PSEUDOFS_ATTRIBUTES=y CONFIG_PSEUDOFS_SOFTLINKS=y +CONFIG_PTHREAD_CLEANUP_STACKSIZE=4 +CONFIG_PTHREAD_SPINLOCKS=y +CONFIG_PTHREAD_STACK_MIN=2048 CONFIG_READLINE_TABCOMPLETION=y +CONFIG_REGULATOR=y +CONFIG_RR_INTERVAL=10 +CONFIG_RTC=y +CONFIG_RTC_ARCH=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_BACKTRACE=y +CONFIG_SCHED_CHILD_STATUS=y CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_LPNTHREADS=1 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_USER_IDENTITY=y +CONFIG_SIG_DEFAULT=y +CONFIG_SIG_EVTHREAD=y CONFIG_SIM_WALLTIME_SIGNAL=y +CONFIG_SPINLOCK=y CONFIG_START_MONTH=6 CONFIG_START_YEAR=2008 CONFIG_SYSTEM_DUMPSTACK=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_POPEN=y +CONFIG_TESTING_CMOCKA=y CONFIG_TESTING_CXXTEST=y +CONFIG_TESTING_DRIVER_TEST=y +CONFIG_TESTING_DRIVER_TEST_SIMPLE=y CONFIG_TESTING_FMEMOPEN_TEST=y CONFIG_TESTING_FOPENCOOKIE_TEST=y CONFIG_TESTING_FSTEST=y CONFIG_TESTING_FSTEST_MOUNTPT="/tmp" CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_LTP=y CONFIG_TESTING_MM=y CONFIG_TESTING_OPEN_MEMSTREAM=y CONFIG_TESTING_OSTEST=y CONFIG_TESTING_SCANFTEST=y CONFIG_TESTING_SCANFTEST_FNAME="/tmp/test.txt" +CONFIG_TESTS_TESTSUITES=y +CONFIG_TLS_NELEM=16 +CONFIG_TLS_TASK_NELEM=8 diff --git a/boards/sim/sim/sim/configs/crypto/defconfig b/boards/sim/sim/sim/configs/crypto/defconfig index 8efd95a706d08..e186a113b7b01 100644 --- a/boards/sim/sim/sim/configs/crypto/defconfig +++ b/boards/sim/sim/sim/configs/crypto/defconfig @@ -28,6 +28,9 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_GPIO=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_GPIO=y CONFIG_EXAMPLES_HELLO=y CONFIG_FAT_LCNAMES=y @@ -57,13 +60,9 @@ CONFIG_MBEDTLS_SHA1_ALT=y CONFIG_MBEDTLS_SHA256_ALT=y CONFIG_MBEDTLS_SHA512_ALT=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_PSEUDOFS_ATTRIBUTES=y CONFIG_PSEUDOFS_SOFTLINKS=y diff --git a/boards/sim/sim/sim/configs/duktape/defconfig b/boards/sim/sim/sim/configs/duktape/defconfig index ef3af62075ae6..b7612fe3fa998 100644 --- a/boards/sim/sim/sim/configs/duktape/defconfig +++ b/boards/sim/sim/sim/configs/duktape/defconfig @@ -19,6 +19,9 @@ CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_HELLO=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y @@ -37,16 +40,12 @@ CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_MAX_EXITFUNS=1 CONFIG_LIBM=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_CONSOLE_LOGIN=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_MOTD=y CONFIG_NSH_MOTD_STRING="MOTD: username=admin password=Administrator" CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_READLINE_TABCOMPLETION=y CONFIG_SCHED_HAVE_PARENT=y diff --git a/boards/sim/sim/sim/configs/foc/defconfig b/boards/sim/sim/sim/configs/foc/defconfig index c0e71bfffb61c..3c4cb9311899d 100644 --- a/boards/sim/sim/sim/configs/foc/defconfig +++ b/boards/sim/sim/sim/configs/foc/defconfig @@ -22,6 +22,9 @@ CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_FOC=y CONFIG_EXAMPLES_FOC_FIXED16_INST=2 CONFIG_EXAMPLES_FOC_FLOAT_INST=2 @@ -64,15 +67,11 @@ CONFIG_MOTOR_FOC=y CONFIG_MOTOR_FOC_DUMMY=y CONFIG_MOTOR_FOC_INST=4 CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_MOTD=y CONFIG_NSH_MOTD_STRING="MOTD: username=admin password=Administrator" CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_READLINE_TABCOMPLETION=y CONFIG_SCHED_HAVE_PARENT=y diff --git a/boards/sim/sim/sim/configs/ipforward/defconfig b/boards/sim/sim/sim/configs/ipforward/defconfig index 944926a929b6f..bd7df5fb4ba9a 100644 --- a/boards/sim/sim/sim/configs/ipforward/defconfig +++ b/boards/sim/sim/sim/configs/ipforward/defconfig @@ -22,6 +22,9 @@ CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_IPFORWARD=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y @@ -47,13 +50,9 @@ CONFIG_NET_TCPBACKLOG=y CONFIG_NET_TCP_WRITE_BUFFERS=y CONFIG_NET_TUN=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_READLINE_TABCOMPLETION=y CONFIG_SCHED_HAVE_PARENT=y diff --git a/boards/sim/sim/sim/configs/libcxxtest/defconfig b/boards/sim/sim/sim/configs/libcxxtest/defconfig index a747e790fc523..a21ea68a04427 100644 --- a/boards/sim/sim/sim/configs/libcxxtest/defconfig +++ b/boards/sim/sim/sim/configs/libcxxtest/defconfig @@ -28,6 +28,8 @@ CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_HELLO=y CONFIG_EXAMPLES_HELLOXX=y CONFIG_EXAMPLES_NETTEST=y @@ -71,11 +73,8 @@ CONFIG_NET_TCP_WRITE_BUFFERS=y CONFIG_NET_UDP=y CONFIG_NET_UDP_NOTIFIER=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_READLINE_TABCOMPLETION=y CONFIG_RTC=y diff --git a/boards/sim/sim/sim/configs/lua/defconfig b/boards/sim/sim/sim/configs/lua/defconfig index 2ef0f058c03b6..5b3a0c8d7df5d 100644 --- a/boards/sim/sim/sim/configs/lua/defconfig +++ b/boards/sim/sim/sim/configs/lua/defconfig @@ -20,6 +20,9 @@ CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_LUA_MODULE=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y @@ -45,13 +48,9 @@ CONFIG_LUA_LFS_MODULE=y CONFIG_LUA_LSYSLOG_MODULE=y CONFIG_LUA_LUV_MODULE=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_PSEUDOFS_ATTRIBUTES=y CONFIG_READLINE_CMD_HISTORY=y diff --git a/boards/sim/sim/sim/configs/lvgl_fb/defconfig b/boards/sim/sim/sim/configs/lvgl_fb/defconfig index cb76cb66bea2b..89c589c3c98ad 100644 --- a/boards/sim/sim/sim/configs/lvgl_fb/defconfig +++ b/boards/sim/sim/sim/configs/lvgl_fb/defconfig @@ -30,14 +30,13 @@ CONFIG_INIT_ARGS="\"widgets\"" CONFIG_INIT_ENTRYPOINT="lvgldemo_main" CONFIG_INPUT=y CONFIG_LV_COLOR_DEPTH_32=y -CONFIG_LV_COLOR_SCREEN_TRANSP=y -CONFIG_LV_MEM_CUSTOM=y -CONFIG_LV_PORT_USE_FBDEV=y -CONFIG_LV_PORT_USE_TOUCHPAD=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y CONFIG_LV_USE_DEMO_WIDGETS=y CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NXFONTS_DISABLE_16BPP=y diff --git a/boards/sim/sim/sim/configs/lvgl_lcd/defconfig b/boards/sim/sim/sim/configs/lvgl_lcd/defconfig index 75d50e0880c59..f4473002c5540 100644 --- a/boards/sim/sim/sim/configs/lvgl_lcd/defconfig +++ b/boards/sim/sim/sim/configs/lvgl_lcd/defconfig @@ -31,16 +31,15 @@ CONFIG_INPUT=y CONFIG_LCD=y CONFIG_LCD_DEV=y CONFIG_LV_COLOR_DEPTH_32=y -CONFIG_LV_COLOR_SCREEN_TRANSP=y -CONFIG_LV_MEM_CUSTOM=y -CONFIG_LV_PORT_LCDDEV_DOUBLE_BUFFER=y -CONFIG_LV_PORT_LCDDEV_FULL_SCREEN_BUFFER=y -CONFIG_LV_PORT_USE_LCDDEV=y -CONFIG_LV_PORT_USE_TOUCHPAD=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" +CONFIG_LV_NUTTX_LCD_DOUBLE_BUFFER=y +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y CONFIG_LV_USE_DEMO_WIDGETS=y CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_LCD=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_BUILTIN_APPS=y CONFIG_NXFONTS_DISABLE_16BPP=y diff --git a/boards/sim/sim/sim/configs/matter/defconfig b/boards/sim/sim/sim/configs/matter/defconfig index 5eb4d39f562ca..ceb5f995f5a89 100644 --- a/boards/sim/sim/sim/configs/matter/defconfig +++ b/boards/sim/sim/sim/configs/matter/defconfig @@ -25,6 +25,9 @@ CONFIG_DEV_URANDOM=y CONFIG_DEV_ZERO=y CONFIG_DRIVERS_BLUETOOTH=y CONFIG_DRIVERS_WIRELESS=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_GPIO=y CONFIG_EXAMPLES_HELLO=y CONFIG_FAT_LCNAMES=y @@ -93,15 +96,11 @@ CONFIG_NET_UDP=y CONFIG_NET_UDP_NOTIFIER=y CONFIG_NET_UDP_WRITE_BUFFERS=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_MOTD=y CONFIG_NSH_MOTD_STRING="MOTD: username=admin password=Administrator" CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_PSEUDOFS_ATTRIBUTES=y CONFIG_PSEUDOFS_SOFTLINKS=y @@ -111,7 +110,6 @@ CONFIG_SCHED_HAVE_PARENT=y CONFIG_SCHED_WAITPID=y CONFIG_SIM_HCISOCKET=y CONFIG_SIM_HOSTFS=y -CONFIG_SIM_M32=y CONFIG_SIM_NETDEV=y CONFIG_SIM_NET_BRIDGE=y CONFIG_SIM_WALLTIME_SIGNAL=y diff --git a/boards/sim/sim/sim/configs/minibasic/defconfig b/boards/sim/sim/sim/configs/minibasic/defconfig index aa495a99437fc..52b4afc4004c9 100644 --- a/boards/sim/sim/sim/configs/minibasic/defconfig +++ b/boards/sim/sim/sim/configs/minibasic/defconfig @@ -18,6 +18,9 @@ CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_HELLO=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y @@ -35,13 +38,9 @@ CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_MAX_EXITFUNS=1 CONFIG_LIBM=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_READLINE_TABCOMPLETION=y CONFIG_SCHED_HAVE_PARENT=y diff --git a/boards/sim/sim/sim/configs/minmea/defconfig b/boards/sim/sim/sim/configs/minmea/defconfig index 0d39a65038678..88b5730777bb0 100644 --- a/boards/sim/sim/sim/configs/minmea/defconfig +++ b/boards/sim/sim/sim/configs/minmea/defconfig @@ -21,6 +21,9 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_GPIO=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_GPIO=y CONFIG_EXAMPLES_HELLO=y CONFIG_FAT_LCNAMES=y @@ -46,16 +49,12 @@ CONFIG_LIBC_LOCALE_GETTEXT=y CONFIG_LIBC_MAX_EXITFUNS=1 CONFIG_LIBC_NUMBERED_ARGS=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_CONSOLE_LOGIN=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_MOTD=y CONFIG_NSH_MOTD_STRING="MOTD: username=admin password=Administrator" CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_PSEUDOFS_ATTRIBUTES=y CONFIG_PSEUDOFS_SOFTLINKS=y diff --git a/boards/sim/sim/sim/configs/module/defconfig b/boards/sim/sim/sim/configs/module/defconfig index 37bdae5a39586..5c8e2cb3c5c68 100644 --- a/boards/sim/sim/sim/configs/module/defconfig +++ b/boards/sim/sim/sim/configs/module/defconfig @@ -19,6 +19,7 @@ CONFIG_BOOT_RUNFROMEXTSRAM=y CONFIG_BUILTIN=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_EXAMPLES_LIBTEST=y CONFIG_EXAMPLES_MODULE=y CONFIG_EXAMPLES_MODULE_DEVMINOR=4 CONFIG_EXAMPLES_MODULE_DEVPATH="/dev/ram4" diff --git a/boards/sim/sim/sim/configs/nimble/defconfig b/boards/sim/sim/sim/configs/nimble/defconfig index 0a1cc0045a579..9de97378d0f3b 100644 --- a/boards/sim/sim/sim/configs/nimble/defconfig +++ b/boards/sim/sim/sim/configs/nimble/defconfig @@ -29,6 +29,9 @@ CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y CONFIG_DRIVERS_BLUETOOTH=y CONFIG_DRIVERS_WIRELESS=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_HELLO=y CONFIG_EXAMPLES_NIMBLE=y CONFIG_FAT_LCNAMES=y @@ -53,13 +56,9 @@ CONFIG_NET_STATISTICS=y CONFIG_NIMBLE=y CONFIG_NIMBLE_ROLE_PERIPHERAL=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_PREALLOC_MQ_MSGS=64 CONFIG_PTHREAD_MUTEX_TYPES=y diff --git a/boards/sim/sim/sim/configs/nsh/defconfig b/boards/sim/sim/sim/configs/nsh/defconfig index 9d509e53ea3a7..fbb4f2874e791 100644 --- a/boards/sim/sim/sim/configs/nsh/defconfig +++ b/boards/sim/sim/sim/configs/nsh/defconfig @@ -20,6 +20,9 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_GPIO=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_GPIO=y CONFIG_EXAMPLES_HELLO=y CONFIG_FAT_LCNAMES=y @@ -44,16 +47,12 @@ CONFIG_LIBC_LOCALE_GETTEXT=y CONFIG_LIBC_MAX_EXITFUNS=1 CONFIG_LIBC_NUMBERED_ARGS=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_CONSOLE_LOGIN=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_MOTD=y CONFIG_NSH_MOTD_STRING="MOTD: username=admin password=Administrator" CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_PSEUDOFS_ATTRIBUTES=y CONFIG_PSEUDOFS_SOFTLINKS=y diff --git a/boards/sim/sim/sim/configs/nsh2/defconfig b/boards/sim/sim/sim/configs/nsh2/defconfig index 508ebf2f2b2de..e4bfdc0b851a2 100644 --- a/boards/sim/sim/sim/configs/nsh2/defconfig +++ b/boards/sim/sim/sim/configs/nsh2/defconfig @@ -17,6 +17,9 @@ CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_DRIVERS_VIDEO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_NX=y CONFIG_EXAMPLES_NXHELLO=y CONFIG_EXAMPLES_NXHELLO_FONTID=6 @@ -36,10 +39,7 @@ CONFIG_INPUT=y CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_NX=y CONFIG_NXFONT_SANS23X27=y CONFIG_NXFONT_SANS28X37B=y diff --git a/boards/sim/sim/sim/configs/nxcamera/defconfig b/boards/sim/sim/sim/configs/nxcamera/defconfig index 0544380b14864..faa3692029d8c 100644 --- a/boards/sim/sim/sim/configs/nxcamera/defconfig +++ b/boards/sim/sim/sim/configs/nxcamera/defconfig @@ -22,6 +22,9 @@ CONFIG_DEV_GPIO=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y CONFIG_DRIVERS_VIDEO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_GPIO=y CONFIG_EXAMPLES_HELLO=y CONFIG_FAT_LCNAMES=y @@ -45,19 +48,16 @@ CONFIG_LIBC_MAX_EXITFUNS=1 CONFIG_LIBC_NUMBERED_ARGS=y CONFIG_LIBYUV=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_PSEUDOFS_ATTRIBUTES=y CONFIG_PSEUDOFS_SOFTLINKS=y CONFIG_READLINE_TABCOMPLETION=y CONFIG_SCHED_BACKTRACE=y CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SIM_FBBPP=32 CONFIG_SIM_FBHEIGHT=480 CONFIG_SIM_FBWIDTH=640 CONFIG_SIM_X11FB=y diff --git a/boards/sim/sim/sim/configs/nxlines/defconfig b/boards/sim/sim/sim/configs/nxlines/defconfig index b1c7bdc2aa74e..234735d942078 100644 --- a/boards/sim/sim/sim/configs/nxlines/defconfig +++ b/boards/sim/sim/sim/configs/nxlines/defconfig @@ -18,6 +18,9 @@ CONFIG_BOARD_LOOPSPERMSEC=0 CONFIG_DEBUG_SYMBOLS=y CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_DRIVERS_VIDEO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_NXLINES=y CONFIG_EXAMPLES_NXLINES_BGCOLOR=0x00006400 CONFIG_EXAMPLES_NXLINES_BORDERCOLOR=0x00ffff00 @@ -35,11 +38,8 @@ CONFIG_INIT_ENTRYPOINT="nxlines_main" CONFIG_LIBC_MAX_EXITFUNS=1 CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_LIBRARY=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_NX=y CONFIG_NXFONT_SANS23X27=y CONFIG_NXFONT_SANS28X37B=y diff --git a/boards/sim/sim/sim/configs/nxwm/defconfig b/boards/sim/sim/sim/configs/nxwm/defconfig index 7026aa62b5ff9..6dd1c95594edc 100644 --- a/boards/sim/sim/sim/configs/nxwm/defconfig +++ b/boards/sim/sim/sim/configs/nxwm/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_SIM=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DISABLE_POSIX_TIMERS=y CONFIG_DRIVERS_VIDEO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y CONFIG_FS_FAT=y @@ -26,11 +29,8 @@ CONFIG_IDLETHREAD_STACKSIZE=8192 CONFIG_INIT_ENTRYPOINT="nxwm_main" CONFIG_LIBC_MAX_EXITFUNS=1 CONFIG_MQ_MAXMSGSIZE=64 -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_LIBRARY=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_NX=y CONFIG_NXFONT_SANS23X27=y CONFIG_NXFONT_SANS28X37B=y diff --git a/boards/sim/sim/sim/configs/posix_test/defconfig b/boards/sim/sim/sim/configs/posix_test/defconfig index 509eb1f9ef789..c18d7842a3e94 100644 --- a/boards/sim/sim/sim/configs/posix_test/defconfig +++ b/boards/sim/sim/sim/configs/posix_test/defconfig @@ -25,6 +25,9 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_GPIO=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_GPIO=y CONFIG_EXAMPLES_HELLO=y CONFIG_FAT_LCNAMES=y @@ -58,15 +61,11 @@ CONFIG_LIBC_PASSWD_FILE=y CONFIG_MQ_MAXMSGSIZE=64 CONFIG_NDEBUG=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_MOTD=y CONFIG_NSH_MOTD_STRING="MOTD: username=admin password=Administrator" CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_PIPES=y CONFIG_PSEUDOFS_ATTRIBUTES=y diff --git a/boards/sim/sim/sim/configs/romfs/defconfig b/boards/sim/sim/sim/configs/romfs/defconfig index f1ebc7f6eeb1d..c0405d55aacf7 100644 --- a/boards/sim/sim/sim/configs/romfs/defconfig +++ b/boards/sim/sim/sim/configs/romfs/defconfig @@ -13,12 +13,16 @@ CONFIG_ARCH_CHIP="sim" CONFIG_ARCH_SIM=y CONFIG_BOARDCTL_APP_SYMTAB=y CONFIG_BOARDCTL_POWEROFF=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=0 CONFIG_BOOT_RUNFROMEXTSRAM=y CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_HELLO=y CONFIG_EXAMPLES_ROMFS=y CONFIG_FAT_LCNAMES=y @@ -36,16 +40,12 @@ CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBC_MAX_EXITFUNS=1 CONFIG_LIBC_STRERROR=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_CONSOLE_LOGIN=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_MOTD=y CONFIG_NSH_MOTD_STRING="MOTD: username=admin password=Administrator" CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=6 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_READLINE_TABCOMPLETION=y CONFIG_SCHED_HAVE_PARENT=y diff --git a/boards/sim/sim/sim/configs/rpproxy/defconfig b/boards/sim/sim/sim/configs/rpproxy/defconfig index 78ed69137d6eb..6e4db7b916c2f 100644 --- a/boards/sim/sim/sim/configs/rpproxy/defconfig +++ b/boards/sim/sim/sim/configs/rpproxy/defconfig @@ -49,7 +49,6 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_PROMPT_STRING="proxy> " CONFIG_NSH_READLINE=y -CONFIG_OPENAMP=y CONFIG_READLINE_CMD_HISTORY=y CONFIG_READLINE_TABCOMPLETION=y CONFIG_RPMSGMTD=y diff --git a/boards/sim/sim/sim/configs/rpserver/defconfig b/boards/sim/sim/sim/configs/rpserver/defconfig index a69704bf56239..de82d119c3ebd 100644 --- a/boards/sim/sim/sim/configs/rpserver/defconfig +++ b/boards/sim/sim/sim/configs/rpserver/defconfig @@ -66,7 +66,6 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_PROMPT_STRING="server> " CONFIG_NSH_READLINE=y -CONFIG_OPENAMP=y CONFIG_RAMMTD=y CONFIG_READLINE_CMD_HISTORY=y CONFIG_READLINE_TABCOMPLETION=y @@ -90,7 +89,7 @@ CONFIG_SIM_HOSTFS=y CONFIG_SIM_M32=y CONFIG_SIM_NETDEV=y CONFIG_SIM_NET_BRIDGE=y -CONFIG_SIM_RPTUN_MASTER=y +CONFIG_SIM_RPMSG_MASTER=y CONFIG_SIM_UART0_NAME="/dev/ttyUSB0" CONFIG_SIM_UART_NUMBER=1 CONFIG_SYSLOG_PREFIX=y diff --git a/boards/sim/sim/sim/configs/rust/defconfig b/boards/sim/sim/sim/configs/rust/defconfig index adc1ab2366401..40a4626fc593b 100644 --- a/boards/sim/sim/sim/configs/rust/defconfig +++ b/boards/sim/sim/sim/configs/rust/defconfig @@ -20,6 +20,9 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_GPIO=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_GPIO=y CONFIG_EXAMPLES_HELLO_RUST=y CONFIG_FAT_LCNAMES=y @@ -43,16 +46,12 @@ CONFIG_LIBC_LOCALE_CATALOG=y CONFIG_LIBC_LOCALE_GETTEXT=y CONFIG_LIBC_MAX_EXITFUNS=1 CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_CONSOLE_LOGIN=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_MOTD=y CONFIG_NSH_MOTD_STRING="MOTD: username=admin password=Administrator" CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_PSEUDOFS_ATTRIBUTES=y CONFIG_PSEUDOFS_SOFTLINKS=y diff --git a/boards/sim/sim/sim/configs/segger/defconfig b/boards/sim/sim/sim/configs/segger/defconfig index 7834435d6c28e..b1a401a13d339 100644 --- a/boards/sim/sim/sim/configs/segger/defconfig +++ b/boards/sim/sim/sim/configs/segger/defconfig @@ -22,6 +22,9 @@ CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y CONFIG_DRIVERS_NOTE=y CONFIG_DRIVERS_NOTE_MAX=5 +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_GPIO=y CONFIG_EXAMPLES_HELLO=y CONFIG_FAT_LCNAMES=y @@ -46,15 +49,11 @@ CONFIG_LIBC_LOCALE_GETTEXT=y CONFIG_LIBC_MAX_EXITFUNS=1 CONFIG_NOTE_RTT=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_MOTD=y CONFIG_NSH_MOTD_STRING="MOTD: username=admin password=Administrator" CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_PSEUDOFS_ATTRIBUTES=y CONFIG_PSEUDOFS_SOFTLINKS=y diff --git a/boards/sim/sim/sim/configs/smartfs/defconfig b/boards/sim/sim/sim/configs/smartfs/defconfig index 14247c75e6ce3..b7813e243432c 100644 --- a/boards/sim/sim/sim/configs/smartfs/defconfig +++ b/boards/sim/sim/sim/configs/smartfs/defconfig @@ -23,6 +23,8 @@ CONFIG_DEBUG_FS_ERROR=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_HELLO=y CONFIG_FSUTILS_PASSWD=y CONFIG_FSUTILS_PASSWD_READONLY=y @@ -41,7 +43,6 @@ CONFIG_MTD_N25QXXX=y CONFIG_MTD_PARTITION=y CONFIG_MTD_SMART=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_CONSOLE_LOGIN=y CONFIG_NSH_DISABLE_LOSMART=y @@ -49,8 +50,6 @@ CONFIG_NSH_FILE_APPS=y CONFIG_NSH_MOTD=y CONFIG_NSH_MOTD_STRING="MOTD: username=admin password=Administrator" CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PSEUDOFS_ATTRIBUTES=y CONFIG_PSEUDOFS_SOFTLINKS=y CONFIG_QSPI_FLASH=y diff --git a/boards/sim/sim/sim/configs/sqlite/defconfig b/boards/sim/sim/sim/configs/sqlite/defconfig new file mode 100644 index 0000000000000..a787eb702ecae --- /dev/null +++ b/boards/sim/sim/sim/configs/sqlite/defconfig @@ -0,0 +1,58 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="sim" +CONFIG_ARCH_BOARD="sim" +CONFIG_ARCH_BOARD_SIM=y +CONFIG_ARCH_CHIP="sim" +CONFIG_ARCH_SIM=y +CONFIG_BOARDCTL_POWEROFF=y +CONFIG_BOARD_LOOPSPERMSEC=0 +CONFIG_BOOT_RUNFROMEXTSRAM=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_LOOP=y +CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 +CONFIG_EXAMPLES_HELLO=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FSUTILS_PASSWD=y +CONFIG_FSUTILS_PASSWD_READONLY=y +CONFIG_FS_FAT=y +CONFIG_FS_HOSTFS=y +CONFIG_FS_LARGEFILE=y +CONFIG_FS_LOCK_BUCKET_SIZE=4 +CONFIG_FS_PROCFS=y +CONFIG_FS_ROMFS=y +CONFIG_FS_TMPFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTERPRETERS_MINIBASIC=y +CONFIG_INTERPRETER_MINIBASIC_TESTSCRIPT=y +CONFIG_LIBC_DLFCN=y +CONFIG_LIBC_ENVPATH=y +CONFIG_LIBC_EXECFUNCS=y +CONFIG_LIBC_MAX_EXITFUNS=1 +CONFIG_LIB_SQLITE=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILE_APPS=y +CONFIG_NSH_READLINE=y +CONFIG_PATH_INITIAL="/bin" +CONFIG_PSEUDOFS_SOFTLINKS=y +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SIM_HOSTFS=y +CONFIG_START_MONTH=6 +CONFIG_START_YEAR=2008 +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_SYSTEM=y +CONFIG_UTILS_SQLITE=y diff --git a/boards/sim/sim/sim/configs/tcploop/defconfig b/boards/sim/sim/sim/configs/tcploop/defconfig index b12d9a24d21d0..5a2f135db5190 100644 --- a/boards/sim/sim/sim/configs/tcploop/defconfig +++ b/boards/sim/sim/sim/configs/tcploop/defconfig @@ -22,6 +22,9 @@ CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_TCPBLASTER=y CONFIG_EXAMPLES_TCPBLASTER_LOOPBACK=y CONFIG_FAT_LCNAMES=y @@ -49,13 +52,9 @@ CONFIG_NET_TCPBACKLOG=y CONFIG_NET_TCP_WRITE_BUFFERS=y CONFIG_NET_TUN=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_READLINE_TABCOMPLETION=y CONFIG_SCHED_HAVE_PARENT=y diff --git a/boards/sim/sim/sim/configs/toywasm/defconfig b/boards/sim/sim/sim/configs/toywasm/defconfig index c39eb9cd25ae7..fa63d549a931d 100644 --- a/boards/sim/sim/sim/configs/toywasm/defconfig +++ b/boards/sim/sim/sim/configs/toywasm/defconfig @@ -21,6 +21,8 @@ CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_FSUTILS_PASSWD=y CONFIG_FSUTILS_PASSWD_READONLY=y CONFIG_FS_BINFS=y @@ -59,11 +61,8 @@ CONFIG_NET_TCP_WRITE_BUFFERS=y CONFIG_NET_UDP=y CONFIG_NET_UDP_NOTIFIER=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_READLINE_TABCOMPLETION=y CONFIG_RTC=y diff --git a/boards/sim/sim/sim/configs/udgram/defconfig b/boards/sim/sim/sim/configs/udgram/defconfig index 8a041378a7884..60f75396cb2f0 100644 --- a/boards/sim/sim/sim/configs/udgram/defconfig +++ b/boards/sim/sim/sim/configs/udgram/defconfig @@ -18,6 +18,9 @@ CONFIG_BOARD_LOOPSPERMSEC=0 CONFIG_BOOT_RUNFROMEXTSRAM=y CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_HELLO=y CONFIG_EXAMPLES_UDGRAM=y CONFIG_EXAMPLES_UDGRAM_CLIENT_STACKSIZE=8192 @@ -36,11 +39,8 @@ CONFIG_NET=y CONFIG_NET_LOCAL=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_SCHED_HAVE_PARENT=y CONFIG_SCHED_WAITPID=y diff --git a/boards/sim/sim/sim/configs/unionfs/defconfig b/boards/sim/sim/sim/configs/unionfs/defconfig index 729530f58f91b..4bc7d6b745acd 100644 --- a/boards/sim/sim/sim/configs/unionfs/defconfig +++ b/boards/sim/sim/sim/configs/unionfs/defconfig @@ -11,10 +11,14 @@ CONFIG_ARCH_BOARD="sim" CONFIG_ARCH_BOARD_SIM=y CONFIG_ARCH_CHIP="sim" CONFIG_ARCH_SIM=y +CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=0 CONFIG_BOOT_RUNFROMEXTSRAM=y CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=2 CONFIG_EXAMPLES_UNIONFS=y CONFIG_EXAMPLES_UNIONFS_RAMDEVNO_A=4 CONFIG_EXAMPLES_UNIONFS_RAMDEVNO_B=5 @@ -32,11 +36,8 @@ CONFIG_LIBC_MAX_EXITFUNS=1 CONFIG_LIBC_STRERROR=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_SCHED_HAVE_PARENT=y CONFIG_SCHED_WAITPID=y diff --git a/boards/sim/sim/sim/configs/usbdev/defconfig b/boards/sim/sim/sim/configs/usbdev/defconfig index 0c793c679dce7..5b0092e959c98 100644 --- a/boards/sim/sim/sim/configs/usbdev/defconfig +++ b/boards/sim/sim/sim/configs/usbdev/defconfig @@ -7,7 +7,6 @@ # # CONFIG_SIM_UART_DMA is not set CONFIG_ADBD_FILE_SERVICE=y -CONFIG_ADBD_FILE_SYMLINK=y CONFIG_ADBD_SHELL_SERVICE=y CONFIG_ADBD_USB_BOARDCTL=y CONFIG_ADBD_USB_SERVER=y @@ -38,6 +37,7 @@ CONFIG_FS_PROCFS=y CONFIG_FS_TMPFS=y CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_LIBC_DLFCN=y +CONFIG_LIBC_EXECFUNCS=y CONFIG_LIBUV=y CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDB_DNSCLIENT_MAXRESPONSE=1024 @@ -59,6 +59,7 @@ CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_READLINE=y CONFIG_PSEUDOFS_SOFTLINKS=y +CONFIG_PSEUDOTERM=y CONFIG_READLINE_CMD_HISTORY=y CONFIG_READLINE_TABCOMPLETION=y CONFIG_RNDIS=y diff --git a/boards/sim/sim/sim/configs/userfs/defconfig b/boards/sim/sim/sim/configs/userfs/defconfig index 2f822c2859ac1..d5c17981f9712 100644 --- a/boards/sim/sim/sim/configs/userfs/defconfig +++ b/boards/sim/sim/sim/configs/userfs/defconfig @@ -20,6 +20,9 @@ CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_USERFS=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y @@ -39,13 +42,9 @@ CONFIG_NET_LOCAL=y CONFIG_NET_LOOPBACK=y CONFIG_NET_UDP=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_READLINE_TABCOMPLETION=y CONFIG_SCHED_HAVE_PARENT=y diff --git a/boards/sim/sim/sim/configs/ustream/defconfig b/boards/sim/sim/sim/configs/ustream/defconfig index 68dacb2e3af8a..7fe126ca4167f 100644 --- a/boards/sim/sim/sim/configs/ustream/defconfig +++ b/boards/sim/sim/sim/configs/ustream/defconfig @@ -19,6 +19,9 @@ CONFIG_BOARD_LOOPSPERMSEC=0 CONFIG_BOOT_RUNFROMEXTSRAM=y CONFIG_BUILTIN=y CONFIG_DEBUG_SYMBOLS=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_HELLO=y CONFIG_EXAMPLES_USTREAM=y CONFIG_FAT_LCNAMES=y @@ -36,11 +39,8 @@ CONFIG_NET=y CONFIG_NET_LOCAL=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_SCHED_HAVE_PARENT=y CONFIG_SCHED_WAITPID=y diff --git a/boards/sim/sim/sim/configs/vpnkit/defconfig b/boards/sim/sim/sim/configs/vpnkit/defconfig index 4720bccf2a385..2f111228f4438 100644 --- a/boards/sim/sim/sim/configs/vpnkit/defconfig +++ b/boards/sim/sim/sim/configs/vpnkit/defconfig @@ -21,6 +21,8 @@ CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_HELLO=y CONFIG_EXAMPLES_NETTEST=y CONFIG_FSUTILS_PASSWD=y @@ -60,11 +62,8 @@ CONFIG_NET_TCP_WRITE_BUFFERS=y CONFIG_NET_UDP=y CONFIG_NET_UDP_NOTIFIER=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_READLINE_TABCOMPLETION=y CONFIG_RTC=y diff --git a/boards/sim/sim/sim/configs/wakaama/defconfig b/boards/sim/sim/sim/configs/wakaama/defconfig index 693a3269bfb4b..eec583a6ab4af 100644 --- a/boards/sim/sim/sim/configs/wakaama/defconfig +++ b/boards/sim/sim/sim/configs/wakaama/defconfig @@ -25,6 +25,9 @@ CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_WGET=y CONFIG_FAT_LCNAMES=y CONFIG_FAT_LFN=y @@ -46,14 +49,10 @@ CONFIG_NET_USRSOCK_ICMPv6=y CONFIG_NET_USRSOCK_TCP=y CONFIG_NET_USRSOCK_UDP=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_MOTD=y CONFIG_NSH_MOTD_STRING="MOTD: username=admin password=Administrator" CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_READLINE_TABCOMPLETION=y CONFIG_SCHED_HAVE_PARENT=y CONFIG_SCHED_SPORADIC=y diff --git a/boards/sim/sim/sim/configs/wamr/defconfig b/boards/sim/sim/sim/configs/wamr/defconfig index 174f4bd9e40ff..233129f6e7496 100644 --- a/boards/sim/sim/sim/configs/wamr/defconfig +++ b/boards/sim/sim/sim/configs/wamr/defconfig @@ -23,6 +23,9 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_GPIO=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_GPIO=y CONFIG_EXAMPLES_HELLO=y CONFIG_FSUTILS_PASSWD=y @@ -63,13 +66,9 @@ CONFIG_NET_BINDTODEVICE=y CONFIG_NET_SOCKOPTS=y CONFIG_NET_TUN=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_PSEUDOFS_ATTRIBUTES=y CONFIG_READLINE_CMD_HISTORY=y diff --git a/boards/sim/sim/sim/configs/zipfs/defconfig b/boards/sim/sim/sim/configs/zipfs/defconfig index 93673e3992a35..a0b5f674d2c52 100644 --- a/boards/sim/sim/sim/configs/zipfs/defconfig +++ b/boards/sim/sim/sim/configs/zipfs/defconfig @@ -20,6 +20,9 @@ CONFIG_DEBUG_SYMBOLS=y CONFIG_DEV_GPIO=y CONFIG_DEV_LOOP=y CONFIG_DEV_ZERO=y +CONFIG_ETC_FATDEVNO=2 +CONFIG_ETC_ROMFS=y +CONFIG_ETC_ROMFSDEVNO=1 CONFIG_EXAMPLES_GPIO=y CONFIG_EXAMPLES_HELLO=y CONFIG_FAT_LCNAMES=y @@ -47,15 +50,11 @@ CONFIG_LIBC_MAX_EXITFUNS=1 CONFIG_LIBC_NUMBERED_ARGS=y CONFIG_LIB_ZLIB=y CONFIG_NSH_ARCHINIT=y -CONFIG_NSH_ARCHROMFS=y CONFIG_NSH_BUILTIN_APPS=y -CONFIG_NSH_FATDEVNO=2 CONFIG_NSH_FILE_APPS=y CONFIG_NSH_MOTD=y CONFIG_NSH_MOTD_STRING="MOTD: username=admin password=Administrator" CONFIG_NSH_READLINE=y -CONFIG_NSH_ROMFSDEVNO=1 -CONFIG_NSH_ROMFSETC=y CONFIG_PATH_INITIAL="/bin" CONFIG_PSEUDOFS_ATTRIBUTES=y CONFIG_PSEUDOFS_SOFTLINKS=y diff --git a/boards/sim/sim/sim/include/nsh_romfsimg.h b/boards/sim/sim/sim/include/nsh_romfsimg.h deleted file mode 100644 index f2024724671f8..0000000000000 --- a/boards/sim/sim/sim/include/nsh_romfsimg.h +++ /dev/null @@ -1,25 +0,0 @@ -/**************************************************************************** - * boards/sim/sim/sim/include/nsh_romfsimg.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __BOARDS_SIM_SIM_SIM_INCLUDE_NSH_ROMFSIMG_H -#define __BOARDS_SIM_SIM_SIM_INCLUDE_NSH_ROMFSIMG_H -extern const unsigned char romfs_img[]; -extern const unsigned int romfs_img_len; -#endif /* __BOARDS_SIM_SIM_SIM_INCLUDE_NSH_ROMFSIMG_H */ diff --git a/boards/sim/sim/sim/scripts/Make.defs b/boards/sim/sim/sim/scripts/Make.defs index efc9dd93831ba..457298f8d406e 100644 --- a/boards/sim/sim/sim/scripts/Make.defs +++ b/boards/sim/sim/sim/scripts/Make.defs @@ -83,6 +83,10 @@ else ifeq ($(CONFIG_MM_KASAN_ALL),y) ARCHOPTIMIZATION += -fsanitize=kernel-address endif +ifeq ($(CONFIG_MM_KASAN_GLOBAL),y) + ARCHOPTIMIZATION += --param asan-globals=1 +endif + ifeq ($(CONFIG_SIM_UBSAN),y) ARCHOPTIMIZATION += -fsanitize=undefined else @@ -102,7 +106,7 @@ endif # Add -fno-common because macOS "ld -r" doesn't seem to pick objects # for common symbols. ARCHCFLAGS += -fno-common -ARCHCXXFLAGS += -fno-common -nostdinc++ +ARCHCXXFLAGS += -fno-common # Add -fvisibility=hidden # Because we don't want export nuttx's symbols to share libraries @@ -116,6 +120,10 @@ ARCHCXXFLAGS += -ffunction-sections -fdata-sections ARCHCFLAGS += -Wall -Wstrict-prototypes -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas ARCHCXXFLAGS += -Wall -Wshadow -Wundef -Wno-attributes -Wno-unknown-pragmas +ifneq ($(CONFIG_LIBCXXTOOLCHAIN),y) + ARCHCXXFLAGS += -nostdinc++ +endif + ifneq ($(CONFIG_CXX_STANDARD),) ARCHCXXFLAGS += -std=$(CONFIG_CXX_STANDARD) endif diff --git a/boards/sim/sim/sim/src/CMakeLists.txt b/boards/sim/sim/sim/src/CMakeLists.txt index a984ba7af3ab6..332ce58c1bb34 100644 --- a/boards/sim/sim/sim/src/CMakeLists.txt +++ b/boards/sim/sim/sim/src/CMakeLists.txt @@ -64,7 +64,7 @@ target_sources(board PRIVATE ${SRCS}) set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/gnu-elf.ld") -if(CONFIG_NSH_ROMFSETC AND CONFIG_NSH_ARCHROMFS) +if(CONFIG_ETC_ROMFS) nuttx_add_romfs( NAME etc diff --git a/boards/sim/sim/sim/src/Makefile b/boards/sim/sim/sim/src/Makefile index d8d590dd5fd7f..9aa65fd1f4052 100644 --- a/boards/sim/sim/sim/src/Makefile +++ b/boards/sim/sim/sim/src/Makefile @@ -52,12 +52,10 @@ else endif endif -ifeq ($(CONFIG_NSH_ROMFSETC),y) -ifneq ($(CONFIG_NSH_CUSTOMROMFS),y) +ifeq ($(CONFIG_ETC_ROMFS),y) RCSRCS = etc/init.d/rc.sysinit etc/init.d/rcS RCRAWS = etc/group etc/passwd endif -endif ifeq ($(CONFIG_ARCH_BUTTONS),y) CSRCS += sim_buttons.c diff --git a/boards/sim/sim/sim/src/etc/init.d/rc.sysinit b/boards/sim/sim/sim/src/etc/init.d/rc.sysinit index 1d2f23dc31aaf..ab4f07b4510a0 100644 --- a/boards/sim/sim/sim/src/etc/init.d/rc.sysinit +++ b/boards/sim/sim/sim/src/etc/init.d/rc.sysinit @@ -23,14 +23,14 @@ #define CONCAT_(x, y) x##y #define CONCAT(x, y) CONCAT_(x, y) -#ifdef CONFIG_NSH_ROMFSETC +#ifdef CONFIG_ETC_ROMFS #ifdef CONFIG_FS_FAT /* Create a RAMDISK and mount it at /tmp */ -mkrd -m CONFIG_NSH_FATDEVNO -s CONFIG_NSH_FATSECTSIZE CONFIG_NSH_FATNSECTORS -mkfatfs CONCAT(/dev/ram, CONFIG_NSH_FATDEVNO) -mount -t vfat CONCAT(/dev/ram, CONFIG_NSH_FATDEVNO) CONFIG_NSH_FATMOUNTPT +mkrd -m CONFIG_ETC_FATDEVNO -s CONFIG_ETC_FATSECTSIZE CONFIG_ETC_FATNSECTORS +mkfatfs CONCAT(/dev/ram, CONFIG_ETC_FATDEVNO) +mount -t vfat CONCAT(/dev/ram, CONFIG_ETC_FATDEVNO) CONFIG_ETC_FATMOUNTPT #endif /* CONFIG_FS_FAT */ -#endif /* CONFIG_NSH_ROMFSETC */ +#endif /* CONFIG_ETC_ROMFS */ diff --git a/boards/sim/sim/sim/src/sim_bringup.c b/boards/sim/sim/sim/src/sim_bringup.c index 4d85affd9c0d0..8c7fecbd25915 100644 --- a/boards/sim/sim/sim/src/sim_bringup.c +++ b/boards/sim/sim/sim/src/sim_bringup.c @@ -47,7 +47,7 @@ #include #include #include -#include +#include #include #include #include @@ -61,6 +61,10 @@ #include #endif +#ifdef CONFIG_VNCSERVER +# include +#endif + #if defined(CONFIG_INPUT_BUTTONS_LOWER) && defined(CONFIG_SIM_BUTTONS) #include #endif @@ -75,7 +79,7 @@ #ifdef CONFIG_RPMSG_UART void rpmsg_serialinit(void) { -#ifdef CONFIG_SIM_RPTUN_MASTER +#ifdef CONFIG_SIM_RPMSG_MASTER uart_rpmsg_init("proxy", "proxy", 4096, false); #else uart_rpmsg_init("server", "proxy", 4096, true); @@ -288,11 +292,19 @@ int sim_bringup(void) #ifdef CONFIG_VIDEO_FB /* Initialize and register the simulated framebuffer driver */ +# ifdef CONFIG_VNCSERVER + ret = vnc_fb_register(0); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: vnc_fb_register() failed: %d\n", ret); + } +# else ret = fb_register(0, 0); if (ret < 0) { syslog(LOG_ERR, "ERROR: fb_register() failed: %d\n", ret); } +# endif #endif #ifdef CONFIG_SIM_CAMERA @@ -300,10 +312,10 @@ int sim_bringup(void) sim_camera_initialize(); - ret = video_initialize(CONFIG_SIM_CAMERA_DEV_PATH); + ret = capture_initialize(CONFIG_SIM_CAMERA_DEV_PATH); if (ret < 0) { - syslog(LOG_ERR, "ERROR: video_initialize() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: capture_initialize() failed: %d\n", ret); } #endif @@ -463,11 +475,12 @@ int sim_bringup(void) #endif #ifdef CONFIG_RPTUN -#ifdef CONFIG_SIM_RPTUN_MASTER +# ifdef CONFIG_SIM_RPMSG_MASTER sim_rptun_init("server-proxy", "proxy", SIM_RPTUN_MASTER | SIM_RPTUN_NOBOOT); -#else +# else sim_rptun_init("server-proxy", "server", SIM_RPTUN_SLAVE); +# endif #endif #ifdef CONFIG_DEV_RPMSG @@ -483,7 +496,6 @@ int sim_bringup(void) #ifdef CONFIG_RPMSGMTD rpmsgmtd_register("server", "/dev/rammtd", NULL); #endif -#endif #ifdef CONFIG_SIM_WTGAHRS2_UARTN #if CONFIG_SIM_WTGAHRS2_UARTN == 0 diff --git a/boards/sparc/s698pm/s698pm-dkit/scripts/Make.defs b/boards/sparc/s698pm/s698pm-dkit/scripts/Make.defs index 45f2dc12442e7..c42a985bb3ba2 100644 --- a/boards/sparc/s698pm/s698pm-dkit/scripts/Make.defs +++ b/boards/sparc/s698pm/s698pm-dkit/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/sparc/s698pm/s698pm_dkit/scripts/Make.defs +# boards/sparc/s698pm/s698pm-dkit/scripts/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/tricore/tc3xx/tc397/Kconfig b/boards/tricore/tc3xx/tc397/Kconfig new file mode 100644 index 0000000000000..b262f16c87a47 --- /dev/null +++ b/boards/tricore/tc3xx/tc397/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_TC397 +endif diff --git a/boards/tricore/tc3xx/tc397/configs/nsh/defconfig b/boards/tricore/tc3xx/tc397/configs/nsh/defconfig new file mode 100644 index 0000000000000..8501d45700bd2 --- /dev/null +++ b/boards/tricore/tc3xx/tc397/configs/nsh/defconfig @@ -0,0 +1,55 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="tricore" +CONFIG_ARCH_BOARD="tc397" +CONFIG_ARCH_BOARD_TC397=y +CONFIG_ARCH_CHIP="tc3xx" +CONFIG_ARCH_CHIP_TC397=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_TRICORE=y +CONFIG_BOARD_LOOPSPERMSEC=99369 +CONFIG_BOOT_RUNFROMSDRAM=y +CONFIG_BUILTIN=y +CONFIG_DEBUG_ASSERTIONS=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_DEV_ZERO=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXPERIMENTAL=y +CONFIG_FS_PROCFS=y +CONFIG_FS_TMPFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_LIBC_MEMFD_ERROR=y +CONFIG_NDEBUG=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x70000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_HPWORKPRIORITY=192 +CONFIG_SCHED_WAITPID=y +CONFIG_SPINLOCK=y +CONFIG_STACK_COLORATION=y +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2016 +CONFIG_SYMTAB_ORDEREDBYNAME=y +CONFIG_SYSLOG_BUFFER=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" +CONFIG_SYSLOG_INTBUFFER=y +CONFIG_SYSLOG_MAX_CHANNELS=2 +CONFIG_SYSTEM_NSH=y +CONFIG_TESTING_GETPRIME=y +CONFIG_TESTING_OSTEST=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/tricore/tc3xx/tc397/include/board.h b/boards/tricore/tc3xx/tc397/include/board.h new file mode 100644 index 0000000000000..0100cc08f8066 --- /dev/null +++ b/boards/tricore/tc3xx/tc397/include/board.h @@ -0,0 +1,38 @@ +/**************************************************************************** + * boards/tricore/tc3xx/tc397/include/board.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_TRICORE_TC3XX_TC397_INCLUDE_BOARD_H +#define __BOARDS_TRICORE_TC3XX_TC397_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Definitions + ****************************************************************************/ + +#endif /* __BOARDS_TRICORE_TC3XX_TC397_INCLUDE_BOARD_H */ diff --git a/boards/tricore/tc3xx/tc397/include/board_memorymap.h b/boards/tricore/tc3xx/tc397/include/board_memorymap.h new file mode 100644 index 0000000000000..16c40b3653f42 --- /dev/null +++ b/boards/tricore/tc3xx/tc397/include/board_memorymap.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * boards/tricore/tc3xx/tc397/include/board_memorymap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_TRICORE_TC3XX_TC397_INCLUDE_BOARD_MEMORYMAP_H +#define __BOARDS_TRICORE_TC3XX_TC397_INCLUDE_BOARD_MEMORYMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_TRICORE_TC3XX_TC397_INCLUDE_BOARD_MEMORYMAP_H */ diff --git a/boards/tricore/tc3xx/tc397/scripts/Lcf_Tasking_Tricore_Tc.lsl b/boards/tricore/tc3xx/tc397/scripts/Lcf_Tasking_Tricore_Tc.lsl new file mode 100644 index 0000000000000..22da9c07792a4 --- /dev/null +++ b/boards/tricore/tc3xx/tc397/scripts/Lcf_Tasking_Tricore_Tc.lsl @@ -0,0 +1,1476 @@ +/**************************************************************************** + * boards/tricore/tc3xx/tc397/scripts/Lcf_Tasking_Tricore_Tc.lsl + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include "../../../include/nuttx/config.h" + +#define LCF_CSA0_SIZE 40k +#define LCF_USTACK0_SIZE CONFIG_IDLETHREAD_STACKSIZE +#define LCF_ISTACK0_SIZE CONFIG_ARCH_INTERRUPTSTACK + +#define LCF_CSA1_SIZE 40k +#define LCF_USTACK1_SIZE CONFIG_IDLETHREAD_STACKSIZE +#define LCF_ISTACK1_SIZE CONFIG_ARCH_INTERRUPTSTACK + +#define LCF_CSA2_SIZE 40k +#define LCF_USTACK2_SIZE CONFIG_IDLETHREAD_STACKSIZE +#define LCF_ISTACK2_SIZE CONFIG_ARCH_INTERRUPTSTACK + +#define LCF_CSA3_SIZE 40k +#define LCF_USTACK3_SIZE CONFIG_IDLETHREAD_STACKSIZE +#define LCF_ISTACK3_SIZE CONFIG_ARCH_INTERRUPTSTACK + +#define LCF_CSA4_SIZE 40k +#define LCF_USTACK4_SIZE CONFIG_IDLETHREAD_STACKSIZE +#define LCF_ISTACK4_SIZE CONFIG_ARCH_INTERRUPTSTACK + +#define LCF_CSA5_SIZE 40k +#define LCF_USTACK5_SIZE CONFIG_IDLETHREAD_STACKSIZE +#define LCF_ISTACK5_SIZE CONFIG_ARCH_INTERRUPTSTACK + +#define LCF_HEAP_SIZE 4k + +#define LCF_CPU0 0 +#define LCF_CPU1 1 +#define LCF_CPU2 2 +#define LCF_CPU3 3 +#define LCF_CPU4 4 +#define LCF_CPU5 5 + + +/*Un comment one of the below statements to enable CpuX DMI RAM to hold global variables*/ +#define LCF_DEFAULT_HOST LCF_CPU0 +/*#define LCF_DEFAULT_HOST LCF_CPU1*/ +/*#define LCF_DEFAULT_HOST LCF_CPU2*/ +/*#define LCF_DEFAULT_HOST LCF_CPU3*/ +/*#define LCF_DEFAULT_HOST LCF_CPU4*/ +/*#define LCF_DEFAULT_HOST LCF_CPU5*/ + +#define LCF_DSPR5_START 0x10000000 +#define LCF_DSPR5_SIZE 96k + +#define LCF_DSPR4_START 0x30000000 +#define LCF_DSPR4_SIZE 96k + +#define LCF_DSPR3_START 0x40000000 +#define LCF_DSPR3_SIZE 96k + +#define LCF_DSPR2_START 0x50000000 +#define LCF_DSPR2_SIZE 96k + +#define LCF_DSPR1_START 0x60000000 +#define LCF_DSPR1_SIZE 240k + +#define LCF_DSPR0_START 0x70000000 +#define LCF_DSPR0_SIZE 240k + +#define LCF_CSA5_OFFSET (LCF_DSPR5_SIZE - 1k - LCF_CSA5_SIZE) +#define LCF_ISTACK5_OFFSET (LCF_CSA5_OFFSET - 256 - LCF_ISTACK5_SIZE) +#define LCF_USTACK5_OFFSET (LCF_ISTACK5_OFFSET - 256 - LCF_USTACK5_SIZE) + +#define LCF_CSA4_OFFSET (LCF_DSPR4_SIZE - 1k - LCF_CSA4_SIZE) +#define LCF_ISTACK4_OFFSET (LCF_CSA4_OFFSET - 256 - LCF_ISTACK4_SIZE) +#define LCF_USTACK4_OFFSET (LCF_ISTACK4_OFFSET - 256 - LCF_USTACK4_SIZE) + +#define LCF_CSA3_OFFSET (LCF_DSPR3_SIZE - 1k - LCF_CSA3_SIZE) +#define LCF_ISTACK3_OFFSET (LCF_CSA3_OFFSET - 256 - LCF_ISTACK3_SIZE) +#define LCF_USTACK3_OFFSET (LCF_ISTACK3_OFFSET - 256 - LCF_USTACK3_SIZE) + +#define LCF_CSA2_OFFSET (LCF_DSPR2_SIZE - 1k - LCF_CSA2_SIZE) +#define LCF_ISTACK2_OFFSET (LCF_CSA2_OFFSET - 256 - LCF_ISTACK2_SIZE) +#define LCF_USTACK2_OFFSET (LCF_ISTACK2_OFFSET - 256 - LCF_USTACK2_SIZE) + +#define LCF_CSA1_OFFSET (LCF_DSPR1_SIZE - 1k - LCF_CSA1_SIZE) +#define LCF_ISTACK1_OFFSET (LCF_CSA1_OFFSET - 256 - LCF_ISTACK1_SIZE) +#define LCF_USTACK1_OFFSET (LCF_ISTACK1_OFFSET - 256 - LCF_USTACK1_SIZE) + +#define LCF_CSA0_OFFSET (LCF_DSPR0_SIZE - 1k - LCF_CSA0_SIZE) +#define LCF_ISTACK0_OFFSET (LCF_CSA0_OFFSET - 256 - LCF_ISTACK0_SIZE) +#define LCF_USTACK0_OFFSET (LCF_ISTACK0_OFFSET - 256 - LCF_USTACK0_SIZE) + +#define LCF_HEAP0_OFFSET (LCF_USTACK0_OFFSET - LCF_HEAP_SIZE) +#define LCF_HEAP1_OFFSET (LCF_USTACK1_OFFSET - LCF_HEAP_SIZE) +#define LCF_HEAP2_OFFSET (LCF_USTACK2_OFFSET - LCF_HEAP_SIZE) +#define LCF_HEAP3_OFFSET (LCF_USTACK3_OFFSET - LCF_HEAP_SIZE) +#define LCF_HEAP4_OFFSET (LCF_USTACK4_OFFSET - LCF_HEAP_SIZE) +#define LCF_HEAP5_OFFSET (LCF_USTACK5_OFFSET - LCF_HEAP_SIZE) + +#define LCF_INTVEC0_START 0x802FE000 +#define LCF_INTVEC1_START 0x805FE000 +#define LCF_INTVEC2_START 0x808FE000 +#define LCF_INTVEC3_START 0x80BFE000 +#define LCF_INTVEC4_START 0x80EFE000 +#define LCF_INTVEC5_START 0x80FFE000 + +#define LCF_TRAPVEC0_START 0x80000100 +#define LCF_TRAPVEC1_START 0x80300000 +#define LCF_TRAPVEC2_START 0x80600000 +#define LCF_TRAPVEC3_START 0x80900000 +#define LCF_TRAPVEC4_START 0x80C00000 +#define LCF_TRAPVEC5_START 0x80F00000 + +#define LCF_STARTPTR_CPU0 0x80000000 +#define LCF_STARTPTR_CPU1 0x80300100 +#define LCF_STARTPTR_CPU2 0x80600100 +#define LCF_STARTPTR_CPU3 0x80900100 +#define LCF_STARTPTR_CPU4 0x80C00100 +#define LCF_STARTPTR_CPU5 0x80F00100 + +#define LCF_STARTPTR_NC_CPU0 0xA0000000 +#define LCF_STARTPTR_NC_CPU1 0xA0300100 +#define LCF_STARTPTR_NC_CPU2 0xA0600100 +#define LCF_STARTPTR_NC_CPU3 0xA0900100 +#define LCF_STARTPTR_NC_CPU4 0xA0C00100 +#define LCF_STARTPTR_NC_CPU5 0xA0F00100 + +#define INTTAB0 (LCF_INTVEC0_START) +#define INTTAB1 (LCF_INTVEC1_START) +#define INTTAB2 (LCF_INTVEC2_START) +#define INTTAB3 (LCF_INTVEC3_START) +#define INTTAB4 (LCF_INTVEC4_START) +#define INTTAB5 (LCF_INTVEC5_START) +#define TRAPTAB0 (LCF_TRAPVEC0_START) +#define TRAPTAB1 (LCF_TRAPVEC1_START) +#define TRAPTAB2 (LCF_TRAPVEC2_START) +#define TRAPTAB3 (LCF_TRAPVEC3_START) +#define TRAPTAB4 (LCF_TRAPVEC4_START) +#define TRAPTAB5 (LCF_TRAPVEC5_START) + +#define RESET LCF_STARTPTR_NC_CPU0 + +#include "tc1v1_6_2.lsl" + +// Specify a multi-core processor environment (mpe) + +processor mpe +{ + derivative = tc39; +} + +derivative tc39 +{ + core tc0 + { + architecture = TC1V1.6.2; + space_id_offset = 100; // add 100 to all space IDs in the architecture definition + copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections + } + + core tc1 // core 1 TC16E + { + architecture = TC1V1.6.2; + space_id_offset = 200; // add 200 to all space IDs in the architecture definition + copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections + } + + core tc2 // core 2 TC16P + { + architecture = TC1V1.6.2; + space_id_offset = 300; // add 300 to all space IDs in the architecture definition + copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections + } + + core tc3 // core 3 TC16P + { + architecture = TC1V1.6.2; + space_id_offset = 400; // add 300 to all space IDs in the architecture definition + copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections + } + + core tc4 // core 4 TC16P + { + architecture = TC1V1.6.2; + space_id_offset = 500; // add 300 to all space IDs in the architecture definition + copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections + } + + core tc5 // core 5 TC16P + { + architecture = TC1V1.6.2; + space_id_offset = 600; // add 300 to all space IDs in the architecture definition + copytable_space = vtc:linear; // use the copy table in the virtual core for 'bss' and initialized data sections + } + + core vtc + { + architecture = TC1V1.6.2; + import tc0; // add all address spaces of core tc0 to core vtc for linking and locating + import tc1; // tc1 + import tc2; // tc2 + import tc3; // tc3 + import tc4; // tc4 + import tc5; // tc5 + } + + bus sri + { + mau = 8; + width = 32; + + // map shared addresses one-to-one to real cores and virtual cores + map (dest=bus:tc0:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + map (dest=bus:tc1:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + map (dest=bus:tc2:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + map (dest=bus:tc3:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + map (dest=bus:tc4:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + map (dest=bus:tc5:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + map (dest=bus:vtc:fpi_bus, src_offset=0, dest_offset=0, size=0xc0000000); + } + + memory dsram5 // Data Scratch Pad Ram + { + mau = 8; + size = 96k; + type = ram; + map (dest=bus:tc5:fpi_bus, dest_offset=0xd0000000, size=96k, priority=8); + map (dest=bus:sri, dest_offset=0x10000000, size=96k); + } + + memory psram5 // Program Scratch Pad Ram + { + mau = 8; + size = 64k; + type = ram; + map (dest=bus:tc5:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); + map (dest=bus:sri, dest_offset=0x10100000, size=64k); + } + + memory dsram4 // Data Scratch Pad Ram + { + mau = 8; + size = 96k; + type = ram; + map (dest=bus:tc4:fpi_bus, dest_offset=0xd0000000, size=96k, priority=8); + map (dest=bus:sri, dest_offset=0x30000000, size=96k); + } + + memory psram4 // Program Scratch Pad Ram + { + mau = 8; + size = 64k; + type = ram; + map (dest=bus:tc4:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); + map (dest=bus:sri, dest_offset=0x30100000, size=64k); + } + + memory dsram3 // Data Scratch Pad Ram + { + mau = 8; + size = 96k; + type = ram; + map (dest=bus:tc3:fpi_bus, dest_offset=0xd0000000, size=96k, priority=8); + map (dest=bus:sri, dest_offset=0x40000000, size=96k); + } + + memory psram3 // Program Scratch Pad Ram + { + mau = 8; + size = 64k; + type = ram; + map (dest=bus:tc3:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); + map (dest=bus:sri, dest_offset=0x40100000, size=64k); + } + + memory dsram2 // Data Scratch Pad Ram + { + mau = 8; + size = 96k; + type = ram; + map (dest=bus:tc2:fpi_bus, dest_offset=0xd0000000, size=96k, priority=8); + map (dest=bus:sri, dest_offset=0x50000000, size=96k); + } + + memory psram2 // Program Scratch Pad Ram + { + mau = 8; + size = 64k; + type = ram; + map (dest=bus:tc2:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); + map (dest=bus:sri, dest_offset=0x50100000, size=64k); + } + + memory dsram1 // Data Scratch Pad Ram + { + mau = 8; + size = 240k; + type = ram; + map (dest=bus:tc1:fpi_bus, dest_offset=0xd0000000, size=240k, priority=8); + map (dest=bus:sri, dest_offset=0x60000000, size=240k); + } + + memory psram1 // Program Scratch Pad Ram + { + mau = 8; + size = 64k; + type = ram; + map (dest=bus:tc1:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); + map (dest=bus:sri, dest_offset=0x60100000, size=64k); + } + + memory dsram0 // Data Scratch Pad Ram + { + mau = 8; + size = 240k; + type = ram; + map (dest=bus:tc0:fpi_bus, dest_offset=0xd0000000, size=240k, priority=8); + map (dest=bus:sri, dest_offset=0x70000000, size=240k); + } + + memory psram0 // Program Scratch Pad Ram + { + mau = 8; + size = 64k; + type = ram; + map (dest=bus:tc0:fpi_bus, dest_offset=0xc0000000, size=64k, priority=8); + map (dest=bus:sri, dest_offset=0x70100000, size=64k); + } + + memory pfls0 + { + mau = 8; + size = 3M; + type = rom; + map cached (dest=bus:sri, dest_offset=0x80000000, size=3M); + map not_cached (dest=bus:sri, dest_offset=0xa0000000, reserved, size=3M); + } + + memory pfls1 + { + mau = 8; + size = 3M; + type = rom; + map cached (dest=bus:sri, dest_offset=0x80300000, size=3M); + map not_cached (dest=bus:sri, dest_offset=0xa0300000, reserved, size=3M); + } + + memory pfls2 + { + mau = 8; + size = 3M; + type = rom; + map cached (dest=bus:sri, dest_offset=0x80600000, size=3M); + map not_cached (dest=bus:sri, dest_offset=0xa0600000, reserved, size=3M); + } + + memory pfls3 + { + mau = 8; + size = 3M; + type = rom; + map cached (dest=bus:sri, dest_offset=0x80900000, size=3M); + map not_cached (dest=bus:sri, dest_offset=0xa0900000, reserved, size=3M); + } + + memory pfls4 + { + mau = 8; + size = 3M; + type = rom; + map cached (dest=bus:sri, dest_offset=0x80c00000, size=3M); + map not_cached (dest=bus:sri, dest_offset=0xa0c00000, reserved, size=3M); + } + + memory pfls5 + { + mau = 8; + size = 1M; + type = rom; + map cached (dest=bus:sri, dest_offset=0x80f00000, size=1M); + map not_cached (dest=bus:sri, dest_offset=0xa0f00000, reserved, size=1M); + } + + memory dfls0 + { + mau = 8; + size = 1M; + type = reserved nvram; + map (dest=bus:sri, dest_offset=0xaf000000, size=1M ); + } + + memory ucb + { + mau = 8; + size = 24k; + type = rom; + map (dest=bus:sri, dest_offset=0xaf400000, reserved, size=24k); + } + + memory cpu0_dlmu + { + mau = 8; + size = 64k; + type = ram; + map cached (dest=bus:sri, dest_offset=0x90000000, size=64k); + map not_cached (dest=bus:sri, dest_offset=0xb0000000, reserved, size=64k); + } + + memory cpu1_dlmu + { + mau = 8; + size = 64k; + type = ram; + map cached (dest=bus:sri, dest_offset=0x90010000, size=64k); + map not_cached (dest=bus:sri, dest_offset=0xb0010000, reserved, size=64k); + } + + memory cpu2_dlmu + { + mau = 8; + size = 64k; + type = ram; + map cached (dest=bus:sri, dest_offset=0x90020000, size=64k); + map not_cached (dest=bus:sri, dest_offset=0xb0020000, reserved, size=64k); + } + + memory cpu3_dlmu + { + mau = 8; + size = 64k; + type = ram; + map cached (dest=bus:sri, dest_offset=0x90030000, size=64k); + map not_cached (dest=bus:sri, dest_offset=0xb0030000, reserved, size=64k); + } + + memory lmuram + { + mau = 8; + size = 768K; + type = ram; + map cached (dest=bus:sri, dest_offset=0x90040000, size=768K); + map not_cached (dest=bus:sri, dest_offset=0xb0040000, reserved, size=768K); + } + + memory cpu4_dlmu + { + mau = 8; + size = 64k; + type = ram; + map cached (dest=bus:sri, dest_offset=0x90100000, size=64k); + map not_cached (dest=bus:sri, dest_offset=0xb0100000, reserved, size=64k); + } + + memory cpu5_dlmu + { + mau = 8; + size = 64k; + type = ram; + map cached (dest=bus:sri, dest_offset=0x90110000, size=64k); + map not_cached (dest=bus:sri, dest_offset=0xb0110000, reserved, size=64k); + } + + memory edmem + { + mau = 8; + size = 4M; + type = ram; + map (dest=bus:sri, dest_offset=0x99000000, size=4M); + map (dest=bus:sri, dest_offset=0xb9000000, reserved, size=4M); + } + +#if (__VERSION__ >= 6003) + section_setup :vtc:linear + { + heap "heap" (min_size = (1k), fixed, align = 8); + } +#endif + + section_setup :vtc:linear + { + start_address + ( + symbol = "_START" + ); + } + + section_setup :vtc:linear + { + stack "ustack_tc0" (min_size = 1k, fixed, align = 8); + stack "istack_tc0" (min_size = 1k, fixed, align = 8); + stack "ustack_tc1" (min_size = 1k, fixed, align = 8); + stack "istack_tc1" (min_size = 1k, fixed, align = 8); + stack "ustack_tc2" (min_size = 1k, fixed, align = 8); + stack "istack_tc2" (min_size = 1k, fixed, align = 8); + stack "ustack_tc3" (min_size = 1k, fixed, align = 8); + stack "istack_tc3" (min_size = 1k, fixed, align = 8); + stack "ustack_tc4" (min_size = 1k, fixed, align = 8); + stack "istack_tc4" (min_size = 1k, fixed, align = 8); + stack "ustack_tc5" (min_size = 1k, fixed, align = 8); + stack "istack_tc5" (min_size = 1k, fixed, align = 8); + } + + /*Section setup for the copy table*/ + section_setup :vtc:linear + { + copytable + ( + align = 4, + dest = linear, + table + { + symbol = "_lc_ub_table_tc0"; + space = :tc0:linear, :tc0:abs24, :tc0:abs18, :tc0:csa; + }, + table + { + symbol = "_lc_ub_table_tc1"; + space = :tc1:linear, :tc1:abs24, :tc1:abs18, :tc1:csa; + }, + table + { + symbol = "_lc_ub_table_tc2"; + space = :tc2:linear, :tc2:abs24, :tc2:abs18, :tc2:csa; + }, + table + { + symbol = "_lc_ub_table_tc3"; + space = :tc3:linear, :tc3:abs24, :tc3:abs18, :tc3:csa; + }, + table + { + symbol = "_lc_ub_table_tc4"; + space = :tc4:linear, :tc4:abs24, :tc4:abs18, :tc4:csa; + }, + table + { + symbol = "_lc_ub_table_tc5"; + space = :tc5:linear, :tc5:abs24, :tc5:abs18, :tc5:csa; + } + ); + } + + /*Sections located at absolute fixed address*/ + + section_layout :vtc:linear + { + /*Fixed memory Allocations for stack memory and CSA*/ + group (ordered) + { + group ustack5(align = 8, run_addr = mem:dsram5[LCF_USTACK5_OFFSET]) + { + stack "ustack_tc5" (size = LCF_USTACK5_SIZE); + } + "__USTACK5":= sizeof(group:ustack5) > 0 ? "_lc_ue_ustack_tc5" : 0; + "__USTACK5_END"="_lc_gb_ustack5"; + + group istack5(align = 8, run_addr = mem:dsram5[LCF_ISTACK5_OFFSET]) + { + stack "istack_tc5" (size = LCF_ISTACK5_SIZE); + } + "__ISTACK5":= sizeof(group:istack5) > 0 ? "_lc_ue_istack_tc5" : 0; + "__ISTACK5_END"="_lc_gb_istack5"; + + group (align = 64, attributes=rw, run_addr=mem:dsram5[LCF_CSA5_OFFSET]) + reserved "csa_tc5" (size = LCF_CSA5_SIZE); + "__CSA5":= "_lc_ub_csa_tc5"; + "__CSA5_END":= "_lc_ue_csa_tc5"; + } + group (ordered) + { + group ustack4(align = 8, run_addr = mem:dsram4[LCF_USTACK4_OFFSET]) + { + stack "ustack_tc4" (size = LCF_USTACK4_SIZE); + } + "__USTACK4":= sizeof(group:ustack4) > 0 ? "_lc_ue_ustack_tc4" : 0; + "__USTACK4_END"="_lc_gb_ustack4"; + + group istack4(align = 8, run_addr = mem:dsram4[LCF_ISTACK4_OFFSET]) + { + stack "istack_tc4" (size = LCF_ISTACK4_SIZE); + } + "__ISTACK4":= sizeof(group:istack4) > 0 ? "_lc_ue_istack_tc4" : 0; + "__ISTACK4_END"="_lc_gb_istack4"; + + group (align = 64, attributes=rw, run_addr=mem:dsram4[LCF_CSA4_OFFSET]) + reserved "csa_tc4" (size = LCF_CSA4_SIZE); + "__CSA4":= "_lc_ub_csa_tc4"; + "__CSA4_END":= "_lc_ue_csa_tc4"; + } + group (ordered) + { + group ustack3(align = 8, run_addr = mem:dsram3[LCF_USTACK3_OFFSET]) + { + stack "ustack_tc3" (size = LCF_USTACK3_SIZE); + } + "__USTACK3":= sizeof(group:ustack3) > 0 ? "_lc_ue_ustack_tc3" : 0; + "__USTACK3_END"="_lc_gb_ustack3"; + + group istack3(align = 8, run_addr = mem:dsram3[LCF_ISTACK3_OFFSET]) + { + stack "istack_tc3" (size = LCF_ISTACK3_SIZE); + } + "__ISTACK3":= sizeof(group:istack3) > 0 ? "_lc_ue_istack_tc3" : 0; + "__ISTACK3_END"="_lc_gb_istack3"; + + group (align = 64, attributes=rw, run_addr=mem:dsram3[LCF_CSA3_OFFSET]) + reserved "csa_tc3" (size = LCF_CSA3_SIZE); + "__CSA3":= "_lc_ub_csa_tc3"; + "__CSA3_END":= "_lc_ue_csa_tc3"; + } + group (ordered) + { + group ustack2(align = 8, run_addr = mem:dsram2[LCF_USTACK2_OFFSET]) + { + stack "ustack_tc2" (size = LCF_USTACK2_SIZE); + } + "__USTACK2":= sizeof(group:ustack2) > 0 ? "_lc_ue_ustack_tc2" : 0; + "__USTACK2_END"="_lc_gb_ustack2"; + + group istack2(align = 8, run_addr = mem:dsram2[LCF_ISTACK2_OFFSET]) + { + stack "istack_tc2" (size = LCF_ISTACK2_SIZE); + } + "__ISTACK2":= sizeof(group:istack2) > 0 ? "_lc_ue_istack_tc2" : 0; + "__ISTACK2_END"="_lc_gb_istack2"; + + group (align = 64, attributes=rw, run_addr=mem:dsram2[LCF_CSA2_OFFSET]) + reserved "csa_tc2" (size = LCF_CSA2_SIZE); + "__CSA2":= "_lc_ub_csa_tc2"; + "__CSA2_END":= "_lc_ue_csa_tc2"; + } + group (ordered) + { + group ustack1(align = 8, run_addr = mem:dsram1[LCF_USTACK1_OFFSET]) + { + stack "ustack_tc1" (size = LCF_USTACK1_SIZE); + } + "__USTACK1":= sizeof(group:ustack1) > 0 ? "_lc_ue_ustack_tc1" : 0; + "__USTACK1_END"="_lc_gb_ustack1"; + + group istack1(align = 8, run_addr = mem:dsram1[LCF_ISTACK1_OFFSET]) + { + stack "istack_tc1" (size = LCF_ISTACK1_SIZE); + } + "__ISTACK1":= sizeof(group:istack1) > 0 ? "_lc_ue_istack_tc1" : 0; + "__ISTACK1_END"="_lc_gb_istack1"; + + group (align = 64, attributes=rw, run_addr=mem:dsram1[LCF_CSA1_OFFSET]) + reserved "csa_tc1" (size = LCF_CSA1_SIZE); + "__CSA1":= "_lc_ub_csa_tc1"; + "__CSA1_END":= "_lc_ue_csa_tc1"; + } + group (ordered) + { + group ustack0(align = 8, run_addr = mem:dsram0[LCF_USTACK0_OFFSET]) + { + stack "ustack_tc0" (size = LCF_USTACK0_SIZE); + } + "__USTACK0":= sizeof(group:ustack0) > 0 ? "_lc_ue_ustack_tc0" : 0; + "__USTACK0_END"="_lc_gb_ustack0"; + + group istack0(align = 8, run_addr = mem:dsram0[LCF_ISTACK0_OFFSET]) + { + stack "istack_tc0" (size = LCF_ISTACK0_SIZE); + } + "__ISTACK0":= sizeof(group:istack0) > 0 ? "_lc_ue_istack_tc0" : 0; + "__ISTACK0_END"="_lc_gb_istack0"; + + group (align = 64, attributes=rw, run_addr=mem:dsram0[LCF_CSA0_OFFSET]) + reserved "csa_tc0" (size = LCF_CSA0_SIZE); + "__CSA0":= "_lc_ub_csa_tc0"; + "__CSA0_END":= "_lc_ue_csa_tc0"; + } + + /*Fixed memory Allocations for _START*/ + group (ordered) + { + group reset (run_addr=RESET) + { + section "reset" ( size = 0x20, fill = 0x0800, attributes = r ) + { + select ".text.start"; + } + } + group interface_const (run_addr=mem:pfls0[0x0020]) + { + select "*.interface_const"; + } + "__IF_CONST" := addressof(group:interface_const); + "__START0" := LCF_STARTPTR_NC_CPU0; + "__START1" := LCF_STARTPTR_NC_CPU1; + "__START2" := LCF_STARTPTR_NC_CPU2; + "__START3" := LCF_STARTPTR_NC_CPU3; + "__START4" := LCF_STARTPTR_NC_CPU4; + "__START5" := LCF_STARTPTR_NC_CPU5; + } + + /*Fixed memory Allocations for Trap Vector Table*/ + group (ordered) + { + group trapvec_tc0 (align = 8, run_addr=LCF_TRAPVEC0_START) + { + section "trapvec_tc0" (size=0x100, attributes=rx, fill=0) + { + select "(.text.traptab_cpu0*)"; + } + } + group trapvec_tc1 (align = 8, run_addr=LCF_TRAPVEC1_START) + { + section "trapvec_tc1" (size=0x100, attributes=rx, fill=0) + { + select "(.text.traptab_cpu1*)"; + } + } + group trapvec_tc2 (align = 8, run_addr=LCF_TRAPVEC2_START) + { + section "trapvec_tc2" (size=0x100, attributes=rx, fill=0) + { + select "(.text.traptab_cpu2*)"; + } + } + group trapvec_tc3 (align = 8, run_addr=LCF_TRAPVEC3_START) + { + section "trapvec_tc3" (size=0x100, attributes=rx, fill=0) + { + select "(.text.traptab_cpu3*)"; + } + } + group trapvec_tc4 (align = 8, run_addr=LCF_TRAPVEC4_START) + { + section "trapvec_tc4" (size=0x100, attributes=rx, fill=0) + { + select "(.text.traptab_cpu4*)"; + } + } + group trapvec_tc5 (align = 8, run_addr=LCF_TRAPVEC5_START) + { + section "trapvec_tc5" (size=0x100, attributes=rx, fill=0) + { + select "(.text.traptab_cpu5*)"; + } + } + "__TRAPTAB_CPU0" := TRAPTAB0; + "__TRAPTAB_CPU1" := TRAPTAB1; + "__TRAPTAB_CPU2" := TRAPTAB2; + "__TRAPTAB_CPU3" := TRAPTAB3; + "__TRAPTAB_CPU4" := TRAPTAB4; + "__TRAPTAB_CPU5" := TRAPTAB5; + } + + /*Fixed memory Allocations for Start up code*/ + group (ordered) + { + group start_tc0 (run_addr=LCF_STARTPTR_NC_CPU0) + { + select "(.text.start_cpu0*)"; + } + group start_tc1 (run_addr=LCF_STARTPTR_NC_CPU1) + { + select "(.text.start_cpu1*)"; + } + group start_tc2 (run_addr=LCF_STARTPTR_NC_CPU2) + { + select "(.text.start_cpu2*)"; + } + group start_tc3 (run_addr=LCF_STARTPTR_NC_CPU3) + { + select "(.text.start_cpu3*)"; + } + group start_tc4 (run_addr=LCF_STARTPTR_NC_CPU4) + { + select "(.text.start_cpu4*)"; + } + group start_tc5 (run_addr=LCF_STARTPTR_NC_CPU5) + { + select "(.text.start_cpu5*)"; + } + "__ENABLE_INDIVIDUAL_C_INIT_CPU0" := 0; /* Not used */ + "__ENABLE_INDIVIDUAL_C_INIT_CPU1" := 0; + "__ENABLE_INDIVIDUAL_C_INIT_CPU2" := 0; + "__ENABLE_INDIVIDUAL_C_INIT_CPU3" := 0; + "__ENABLE_INDIVIDUAL_C_INIT_CPU4" := 0; + "__ENABLE_INDIVIDUAL_C_INIT_CPU5" := 0; + } + + /*Fixed memory Allocations for Interrupt Vector Table*/ + group (ordered) + { + group int_tab_tc0 (ordered) + { +# include "inttab0.lsl" + } + group int_tab_tc1 (ordered) + { +# include "inttab1.lsl" + } + group int_tab_tc2 (ordered) + { +# include "inttab2.lsl" + } + group int_tab_tc3 (ordered) + { +# include "inttab3.lsl" + } + group int_tab_tc4 (ordered) + { +# include "inttab4.lsl" + } + group int_tab_tc5 (ordered) + { +# include "inttab5.lsl" + } + "_lc_u_int_tab" = (LCF_INTVEC0_START); + "__INTTAB_CPU0" = (LCF_INTVEC0_START); + "__INTTAB_CPU1" = (LCF_INTVEC1_START); + "__INTTAB_CPU2" = (LCF_INTVEC2_START); + "__INTTAB_CPU3" = (LCF_INTVEC3_START); + "__INTTAB_CPU4" = (LCF_INTVEC4_START); + "__INTTAB_CPU5" = (LCF_INTVEC5_START); + } + + /*Fixed memory Allocations for BMHD*/ + group (ordered) + { + group bmh_0_orig (run_addr=mem:ucb[0x0000]) + { + select ".rodata.bmhd_0_orig"; + } + group bmh_1_orig (run_addr=mem:ucb[0x0200]) + { + select ".rodata.bmhd_1_orig"; + } + group bmh_2_orig (run_addr=mem:ucb[0x0400]) + { + select ".rodata.bmhd_2_orig"; + } + group bmh_3_orig (run_addr=mem:ucb[0x0600]) + { + select ".rodata.bmhd_3_orig"; + } + group bmh_blank (run_addr=mem:ucb[0x0800]) + { + } + group bmh_0_copy (run_addr=mem:ucb[0x1000]) + { + select ".rodata.bmhd_0_copy"; + } + group bmh_1_copy (run_addr=mem:ucb[0x1200]) + { + select ".rodata.bmhd_1_copy"; + } + group bmh_2_copy (run_addr=mem:ucb[0x1400]) + { + select ".rodata.bmhd_2_copy"; + } + group bmh_3_copy (run_addr=mem:ucb[0x1600]) + { + select ".rodata.bmhd_3_copy"; + } + } + } + + /*Near Abbsolute Addressable Data Sections*/ + section_layout :vtc:abs18 + { + /*Near Absolute Data, selectable with patterns and user defined sections*/ + group + { + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram5) + { + select "(.zdata.zdata_cpu5|.zdata.zdata_cpu5.*)"; + select "(.zbss.zbss_cpu5|.zbss.zbss_cpu5.*)"; + } + + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram4) + { + select "(.zdata.zdata_cpu4|.zdata.zdata_cpu4.*)"; + select "(.zbss.zbss_cpu4|.zbss.zbss_cpu4.*)"; + } + + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram3) + { + select "(.zdata.zdata_cpu3|.zdata.zdata_cpu3.*)"; + select "(.zbss.zbss_cpu3|.zbss.zbss_cpu3.*)"; + } + + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) + { + select "(.zdata.zdata_cpu2|.zdata.zdata_cpu2.*)"; + select "(.zbss.zbss_cpu2|.zbss.zbss_cpu2.*)"; + } + + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) + { + select "(.zdata.zdata_cpu1|.zdata.zdata_cpu1.*)"; + select "(.zbss.zbss_cpu1|.zbss.zbss_cpu1.*)"; + } + + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) + { + select "(.zdata.zdata_cpu0|.zdata.zdata_cpu0.*)"; + select "(.zbss.zbss_cpu0|.zbss.zbss_cpu0.*)"; + } + + group (ordered, attributes=rw, run_addr = mem:cpu0_dlmu) + { + select "(.zdata.zlmudata|.zdata.zlmudata.*)"; + select "(.zbss.zlmubss|.zbss.zlmubss.*)"; + } + } + + /*Near Absolute Data, selectable by toolchain*/ +# if LCF_DEFAULT_HOST == LCF_CPU5 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram5) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU4 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram4) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU3 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram3) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU2 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) +# endif + { + group zdata_mcal(attributes=rw) + { + select ".zdata.dsprInit.cpu0.32bit"; + select ".zdata.dsprInit.cpu0.16bit"; + select ".zdata.dsprInit.cpu0.8bit"; + } + + group zdata_powerOn(attributes=rw) + { + select ".zdata.dsprPowerOnInit.cpu0.32bit"; + select ".zdata.dsprPowerOnInit.cpu0.16bit"; + select ".zdata.dsprPowerOnInit.cpu0.8bit"; + } + + group zbss_mcal(attributes=rw) + { + select ".zbss.dsprClearOnInit.cpu0.32bit"; + select ".zbss.dsprClearOnInit.cpu0.16bit"; + select ".zbss.dsprClearOnInit.cpu0.8bit"; + } + + group zbss_noClear(attributes=rw) + { + select ".zbss.dsprNoInit.cpu0.32bit"; + select ".zbss.dsprNoInit.cpu0.16bit"; + select ".zbss.dsprNoInit.cpu0.8bit"; + } + + group zbss_powerOn(attributes=rw) + { + select ".zbss.dsprPowerOnClear.cpu0.32bit"; + select ".zbss.dsprPowerOnClear.cpu0.16bit"; + select ".zbss.dsprPowerOnClear.cpu0.8bit"; + } + + group zdata(attributes=rw) + { + select "(.zdata|.zdata.*)"; + select "(.zbss|.zbss.*)"; + } + } + + /*Near Absolute Const, selectable with patterns and user defined sections*/ + group + { + group (ordered, align = 4, contiguous, run_addr=mem:pfls0) + { + select ".zrodata.Ifx_Ssw_Tc0.*"; + select ".zrodata.Ifx_Ssw_Tc1.*"; + select ".zrodata.Ifx_Ssw_Tc2.*"; + select ".zrodata.Ifx_Ssw_Tc3.*"; + select ".zrodata.Ifx_Ssw_Tc4.*"; + select ".zrodata.Ifx_Ssw_Tc5.*"; + select ".zrodata.Cpu0_Main.*"; + select ".zrodata.Cpu1_Main.*"; + select ".zrodata.Cpu2_Main.*"; + select ".zrodata.Cpu3_Main.*"; + select ".zrodata.Cpu4_Main.*"; + select ".zrodata.Cpu5_Main.*"; + + /*Near Absolute Const, selectable by toolchain*/ + select ".zrodata.const.cpu0.32bit"; + select ".zrodata.const.cpu0.16bit"; + select ".zrodata.const.cpu0.8bit"; + select ".zrodata.config.cpu0.32bit"; + select ".zrodata.config.cpu0.16bit"; + select ".zrodata.config.cpu0.8bit"; + select "(.zrodata|.zrodata.*)"; + } + } + } + + /*Relative A0/A1/A8/A9 Addressable Sections*/ + section_layout :vtc:linear + { + /*Relative A0 Addressable Data, selectable by toolchain*/ +# if LCF_DEFAULT_HOST == LCF_CPU5 + group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram5) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU4 + group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram4) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU3 + group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram3) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU2 + group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group a0 (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) +# endif + { + select "(.data_a0.sdata|.data_a0.sdata.*)"; + select "(.bss_a0.sbss|.bss_a0.sbss.*)"; + } + "_SMALL_DATA_" := sizeof(group:a0) > 0 ? addressof(group:a0) : addressof(group:a0) & 0xF0000000 + 32k; + "__A0_MEM" = "_SMALL_DATA_"; + + /*Relative A1 Addressable Const, selectable by toolchain*/ + /*Small constant sections, No option given for CPU specific user sections to make generated code portable across Cpus*/ +# if LCF_DEFAULT_HOST == LCF_CPU5 + group a1 (ordered, align = 4, run_addr=mem:pfls5) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU4 + group a1 (ordered, align = 4, run_addr=mem:pfls4) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU3 + group a1 (ordered, align = 4, run_addr=mem:pfls3) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU2 + group a1 (ordered, align = 4, run_addr=mem:pfls2) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group a1 (ordered, align = 4, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group a1 (ordered, align = 4, run_addr=mem:pfls0) +# endif + { + select "(.rodata_a1.srodata|.rodata_a1.srodata.*)"; + select "(.ldata|.ldata.*)"; + } + "_LITERAL_DATA_" := sizeof(group:a1) > 0 ? addressof(group:a1) : addressof(group:a1) & 0xF0000000 + 32k; + "__A1_MEM" = "_LITERAL_DATA_"; + + /*Relative A9 Addressable Data, selectable with patterns and user defined sections*/ + group a9 (ordered, align = 4, run_addr=mem:lmuram) + { + select "(.data_a9.a9sdata|.data_a9.a9sdata.*)"; + select "(.bss_a9.a9sbss|.bss_a9.a9sbss.*)"; + } + "_A9_DATA_" := sizeof(group:a9) > 0 ? addressof(group:a9) : addressof(group:a9) & 0xF0000000 + 32k; + "__A9_MEM" = "_A9_DATA_"; + + /*Relative A8 Addressable Const, selectable with patterns and user defined sections*/ +# if LCF_DEFAULT_HOST == LCF_CPU5 + group a8 (ordered, align = 4, run_addr=mem:pfls5) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU4 + group a8 (ordered, align = 4, run_addr=mem:pfls4) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU3 + group a8 (ordered, align = 4, run_addr=mem:pfls3) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU2 + group a8 (ordered, align = 4, run_addr=mem:pfls2) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group a8 (ordered, align = 4, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group a8 (ordered, align = 4, run_addr=mem:pfls0) +# endif + { + select "(.rodata_a8.a8srodata|.rodata_a8.a8srodata.*)"; + } + "_A8_DATA_" := sizeof(group:a8) > 0 ? addressof(group:a8) : addressof(group:a8) & 0xF0000000 + 32k; + "__A8_MEM" = "_A8_DATA_"; + } + + /*Far Data / Far Const Sections, selectable with patterns and user defined sections*/ + section_layout :vtc:linear + { + /*Far Data Sections, selectable with patterns and user defined sections*/ + group + { + /*DSRAM sections*/ + group + { + group (ordered, attributes=rw, run_addr=mem:dsram5) + { + select ".data.Ifx_Ssw_Tc5.*"; + select ".data.Cpu5_Main.*"; + select "(.data.data_cpu5|.data.data_cpu5.*)"; + select ".bss.Ifx_Ssw_Tc5.*"; + select ".bss.Cpu5_Main.*"; + select "(.bss.bss_cpu5|.bss.bss_cpu5.*)"; + } + group (ordered, attributes=rw, run_addr=mem:dsram4) + { + select ".data.Ifx_Ssw_Tc4.*"; + select ".data.Cpu4_Main.*"; + select "(.data.data_cpu4|.data.data_cpu4.*)"; + select ".bss.Ifx_Ssw_Tc4.*"; + select ".bss.Cpu4_Main.*"; + select "(.bss.bss_cpu4|.bss.bss_cpu4.*)"; + } + group (ordered, attributes=rw, run_addr=mem:dsram3) + { + select ".data.Ifx_Ssw_Tc3.*"; + select ".data.Cpu3_Main.*"; + select "(.data.data_cpu3|.data.data_cpu3.*)"; + select ".bss.Ifx_Ssw_Tc3.*"; + select ".bss.Cpu3_Main.*"; + select "(.bss.bss_cpu3|.bss.bss_cpu3.*)"; + } + group (ordered, attributes=rw, run_addr=mem:dsram2) + { + select ".data.Ifx_Ssw_Tc2.*"; + select ".data.Cpu2_Main.*"; + select "(.data.data_cpu2|.data.data_cpu2.*)"; + select ".bss.Ifx_Ssw_Tc2.*"; + select ".bss.Cpu2_Main.*"; + select "(.bss.bss_cpu2|.bss.bss_cpu2.*)"; + } + group (ordered, attributes=rw, run_addr=mem:dsram1) + { + select ".data.Ifx_Ssw_Tc1.*"; + select ".data.Cpu1_Main.*"; + select "(.data.data_cpu1|.data.data_cpu1.*)"; + select ".bss.Ifx_Ssw_Tc1.*"; + select ".bss.Cpu1_Main.*"; + select "(.bss.bss_cpu1|.bss.bss_cpu1.*)"; + } + group (ordered, attributes=rw, run_addr=mem:dsram0) + { + select ".data.Ifx_Ssw_Tc0.*"; + select ".data.Cpu0_Main.*"; + select "(.data.data_cpu0|.data.data_cpu0.*)"; + select ".bss.Ifx_Ssw_Tc0.*"; + select ".bss.Cpu0_Main.*"; + select "(.bss.bss_cpu0|.bss.bss_cpu0.*)"; + } + } + + /*LMU Data sections*/ + group + { + group (ordered, attributes=rw, run_addr = mem:cpu0_dlmu) + { + select "(.data.lmudata_cpu0|.data.lmudata_cpu0.*)"; + select "(.bss.lmubss_cpu0|.bss.lmubss_cpu0.*)"; + } + group (ordered, attributes=rw, run_addr = mem:cpu1_dlmu) + { + select "(.data.lmudata_cpu1|.data.lmudata_cpu1.*)"; + select "(.bss.lmubss_cpu1|.bss.lmubss_cpu1.*)"; + } + group (ordered, attributes=rw, run_addr = mem:cpu2_dlmu) + { + select "(.data.lmudata_cpu2|.data.lmudata_cpu2.*)"; + select "(.bss.lmubss_cpu2|.bss.lmubss_cpu2.*)"; + } + group (ordered, attributes=rw, run_addr = mem:cpu3_dlmu) + { + select "(.data.lmudata_cpu3|.data.lmudata_cpu3.*)"; + select "(.bss.lmubss_cpu3|.bss.lmubss_cpu3.*)"; + } + group (ordered, attributes=rw, run_addr = mem:cpu4_dlmu) + { + select "(.data.lmudata_cpu4|.data.lmudata_cpu4.*)"; + select "(.bss.lmubss_cpu4|.bss.lmubss_cpu4.*)"; + } + group (ordered, attributes=rw, run_addr = mem:cpu5_dlmu) + { + select "(.data.lmudata_cpu5|.data.lmudata_cpu5.*)"; + select "(.bss.lmubss_cpu5|.bss.lmubss_cpu5.*)"; + } + group (ordered, attributes=rw, run_addr=mem:lmuram) + { + select "(.data.lmudata|.data.lmudata.*)"; + select "(.bss.lmubss|.bss.lmubss.*)"; + } + } + } + + /*Far Data Sections, selectable by toolchain*/ +# if LCF_DEFAULT_HOST == LCF_CPU5 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram5) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU4 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram4) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU3 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram3) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU2 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram2) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group (ordered, contiguous, align = 4, attributes=rw, run_addr = mem:dsram0) +# endif + { + group data_mcal(attributes=rw) + { + select ".data.farDsprInit.cpu0.32bit"; + select ".data.farDsprInit.cpu0.16bit"; + select ".data.farDsprInit.cpu0.8bit"; + } + + group bss_mcal(attributes=rw) + { + select ".bss.farDsprClearOnInit.cpu0.32bit"; + select ".bss.farDsprClearOnInit.cpu0.16bit"; + select ".bss.farDsprClearOnInit.cpu0.8bit"; + } + + group bss_noInit(attributes=rw) + { + select ".bss.farDsprNoInit.cpu0.32bit"; + select ".bss.farDsprNoInit.cpu0.16bit"; + select ".bss.farDsprNoInit.cpu0.8bit"; + } + + group data(attributes=rw) + { + select "(.data|.data.*)"; + select "(.bss|.bss.*)"; + } + } + + /*Heap allocation*/ +# if LCF_DEFAULT_HOST == LCF_CPU5 + group (ordered, align = 4, run_addr = mem:dsram5[LCF_HEAP5_OFFSET]) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU4 + group (ordered, align = 4, run_addr = mem:dsram4[LCF_HEAP4_OFFSET]) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU3 + group (ordered, align = 4, run_addr = mem:dsram3[LCF_HEAP3_OFFSET]) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU2 + group (ordered, align = 4, run_addr = mem:dsram2[LCF_HEAP2_OFFSET]) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group (ordered, align = 4, run_addr = mem:dsram1[LCF_HEAP1_OFFSET]) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group (ordered, align = 4, run_addr = mem:dsram0[LCF_HEAP0_OFFSET]) +# endif + { + heap "heap" (size = LCF_HEAP_SIZE); + } + + /*Far Const Sections, selectable with patterns and user defined sections*/ + group + { + group (ordered, align = 4, run_addr=mem:pfls0) + { + select ".rodata.Ifx_Ssw_Tc0.*"; + select ".rodata.Cpu0_Main.*"; + select "(.rodata.rodata_cpu0|.rodata.rodata_cpu0.*)"; + } + group (ordered, align = 4, run_addr=mem:pfls1) + { + select ".rodata.Cpu1_Main.*"; + select ".rodata.Ifx_Ssw_Tc1.*"; + select "(.rodata.rodata_cpu1|.rodata.rodata_cpu1.*)"; + } + group (ordered, align = 4, run_addr=mem:pfls2) + { + select ".rodata.Ifx_Ssw_Tc2.*"; + select ".rodata.Cpu2_Main.*"; + select "(.rodata.rodata_cpu2|.rodata.rodata_cpu2.*)"; + } + group (ordered, align = 4, run_addr=mem:pfls3) + { + select ".rodata.Ifx_Ssw_Tc3.*"; + select ".rodata.Cpu3_Main.*"; + select "(.rodata.rodata_cpu3|.rodata.rodata_cpu3.*)"; + } + group (ordered, align = 4, run_addr=mem:pfls4) + { + select ".rodata.Ifx_Ssw_Tc4.*"; + select ".rodata.Cpu4_Main.*"; + select "(.rodata.rodata_cpu4|.rodata.rodata_cpu4.*)"; + } + group (ordered, align = 4, run_addr=mem:pfls5) + { + select ".rodata.Ifx_Ssw_Tc5.*"; + select ".rodata.Cpu5_Main.*"; + select "(.rodata.rodata_cpu5|.rodata.rodata_cpu5.*)"; + } + } + + /*Far Const Sections, selectable by toolchain*/ +# if LCF_DEFAULT_HOST == LCF_CPU5 + group (ordered, align = 4, run_addr=mem:pfls5) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU4 + group ordered, align = 4, run_addr=mem:pfls4) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU3 + group (ordered, align = 4, run_addr=mem:pfls3) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU2 + group (ordered, align = 4, run_addr=mem:pfls2) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group (ordered, align = 4, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group (ordered, align = 4, run_addr=mem:pfls0) +# endif + { + select ".rodata.farConst.cpu0.32bit"; + select ".rodata.farConst.cpu0.16bit"; + select ".rodata.farConst.cpu0.8bit"; + select "(.rodata|.rodata.*)"; + } + } + + /* PSRAM Code selections*/ + section_layout :vtc:linear + { + /*Code Sections, selectable with patterns and user defined sections*/ + group + { + /*Program Scratchpad Sections*/ + group + { + group code_psram0 (ordered, attributes=rwx, copy, run_addr=mem:psram0) + { + select "(.text.cpu0_psram|.text.cpu0_psram.*)"; + select "(.text.psram_text_cpu0|.text.psram_text_cpu0.*)"; + } + group code_psram1 (ordered, attributes=rwx, copy, run_addr=mem:psram1) + { + select "(.text.cpu1_psram|.text.cpu1_psram.*)"; + select "(.text.psram_text_cpu1|.text.psram_text_cpu1.*)"; + } + group code_psram2 (ordered, attributes=rwx, copy, run_addr=mem:psram2) + { + select "(.text.cpu2_psram|.text.cpu2_psram.*)"; + select "(.text.psram_text_cpu2|.text.psram_text_cpu2.*)"; + } + group code_psram3 (ordered, attributes=rwx, copy, run_addr=mem:psram3) + { + select "(.text.cpu3_psram|.text.cpu3_psram.*)"; + select "(.text.psram_text_cpu3|.text.psram_text_cpu3.*)"; + } + group code_psram4 (ordered, attributes=rwx, copy, run_addr=mem:psram4) + { + select "(.text.cpu4_psram|.text.cpu4_psram.*)"; + select "(.text.psram_text_cpu4|.text.psram_text_cpu4.*)"; + } + group code_psram5 (ordered, attributes=rwx, copy, run_addr=mem:psram5) + { + select "(.text.cpu5_psram|.text.cpu5_psram.*)"; + select "(.text.psram_text_cpu5|.text.psram_text_cpu5.*)"; + } + } + } + } + + /* FLS Code selections*/ + section_layout :vtc:linear + { + /*Code Sections, selectable with patterns and user defined sections*/ + group + { + /*Cpu specific PFLASH Sections*/ + group + { + group (ordered, align = 4, run_addr=mem:pfls0) + { + select ".text.Ifx_Ssw_Tc0.*"; + select ".text.Cpu0_Main.*"; + select ".text.CompilerTasking.Ifx_C_Init"; + select "(.text.text_cpu0|.text.text_cpu0.*)"; + } + group (ordered, align = 4, run_addr=mem:pfls1) + { + select ".text.Ifx_Ssw_Tc1.*"; + select ".text.Cpu1_Main.*"; + select "(.text.text_cpu1|.text.text_cpu1.*)"; + } + group (ordered, align = 4, run_addr=mem:pfls2) + { + select ".text.Ifx_Ssw_Tc2.*"; + select ".text.Cpu2_Main.*"; + select "(.text.text_cpu2|.text.text_cpu2.*)"; + } + group (ordered, align = 4, run_addr=mem:pfls3) + { + select ".text.Ifx_Ssw_Tc3.*"; + select ".text.Cpu3_Main.*"; + select "(.text.text_cpu3|.text.text_cpu3.*)"; + } + group (ordered, align = 4, run_addr=mem:pfls4) + { + select ".text.Ifx_Ssw_Tc4.*"; + select ".text.Cpu4_Main.*"; + select ".text.text_cpu4*"; + select "(.text.text_cpu4|.text.text_cpu4.*)"; + } + group (ordered, align = 4, run_addr=mem:pfls5) + { + select ".text.Ifx_Ssw_Tc5.*"; + select ".text.Cpu5_Main.*"; + select ".text.text_cpu5*"; + select "(.text.text_cpu5|.text.text_cpu5.*)"; + } + } + } + + /*Code Sections, selectable by toolchain*/ +# if LCF_DEFAULT_HOST == LCF_CPU5 + group (ordered, run_addr=mem:pfls5) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU4 + group ordered, run_addr=mem:pfls4) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU3 + group (ordered, run_addr=mem:pfls3) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU2 + group (ordered, run_addr=mem:pfls2) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU1 + group (ordered, run_addr=mem:pfls1) +# endif +# if LCF_DEFAULT_HOST == LCF_CPU0 + group (ordered, run_addr=mem:pfls0) +# endif + { + select ".text.fast.pfls.cpu0"; + select ".text.slow.pfls.cpu0"; + select ".text.5ms.pfls.cpu0"; + select ".text.10ms.pfls.cpu0"; + select ".text.callout.pfls.cpu0"; + select "(.text|.text.*)"; + } + } +} diff --git a/boards/tricore/tc3xx/tc397/scripts/Make.defs b/boards/tricore/tc3xx/tc397/scripts/Make.defs new file mode 100644 index 0000000000000..2a5ae5bf8bc20 --- /dev/null +++ b/boards/tricore/tc3xx/tc397/scripts/Make.defs @@ -0,0 +1,32 @@ +############################################################################ +# boards/tricore/tc3xx/tc397/scripts/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/tricore/src/tc3xx/Toolchain.defs + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)Lcf_Tasking_Tricore_Tc.lsl + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ diff --git a/boards/tricore/tc3xx/tc397/src/Makefile b/boards/tricore/tc3xx/tc397/src/Makefile new file mode 100644 index 0000000000000..83c7719356456 --- /dev/null +++ b/boards/tricore/tc3xx/tc397/src/Makefile @@ -0,0 +1,29 @@ +############################################################################ +# boards/tricore/tc3xx/tc397/src/Makefile +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/Make.defs + +CSRCS = tc397_boardinit.c tc397_bringup.c + +ifeq ($(CONFIG_BOARDCTL),y) +CSRCS += tc397_appinit.c +endif + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/tricore/tc3xx/tc397/src/tc397.h b/boards/tricore/tc3xx/tc397/src/tc397.h new file mode 100644 index 0000000000000..776c0ae73e2fb --- /dev/null +++ b/boards/tricore/tc3xx/tc397/src/tc397.h @@ -0,0 +1,63 @@ +/**************************************************************************** + * boards/tricore/tc3xx/tc397/src/tc397.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_TRICORE_TC3XX_TC397_SRC_TC397_H +#define __BOARDS_TRICORE_TC3XX_TC397_SRC_TC397_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Functions Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: tc397_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +#if defined(CONFIG_BOARDCTL) || defined(CONFIG_BOARD_LATE_INITIALIZE) +int tc397_bringup(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_TRICORE_TC3XX_TC397_SRC_TC397_H */ diff --git a/boards/tricore/tc3xx/tc397/src/tc397_appinit.c b/boards/tricore/tc3xx/tc397/src/tc397_appinit.c new file mode 100644 index 0000000000000..dd419bd85f22a --- /dev/null +++ b/boards/tricore/tc3xx/tc397/src/tc397_appinit.c @@ -0,0 +1,75 @@ +/**************************************************************************** + * boards/tricore/tc3xx/tc397/src/tc397_appinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "tc397.h" + +#ifdef CONFIG_BOARDCTL + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initialization logic and the + * matching application logic. The value could be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifndef CONFIG_BOARD_LATE_INITIALIZE + /* Perform board initialization */ + + return tc397_bringup(); +#else + return OK; +#endif +} + +#endif /* CONFIG_BOARDCTL */ diff --git a/boards/tricore/tc3xx/tc397/src/tc397_boardinit.c b/boards/tricore/tc3xx/tc397/src/tc397_boardinit.c new file mode 100644 index 0000000000000..41259440a2a92 --- /dev/null +++ b/boards/tricore/tc3xx/tc397/src/tc397_boardinit.c @@ -0,0 +1,119 @@ +/**************************************************************************** + * boards/tricore/tc3xx/tc397/src/tc397_boardinit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include "chip.h" +#include "tc397.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tc397_memory_initialize + * + * Description: + * All i.MX6 architectures must provide the following entry point. This + * entry point is called early in the initialization before memory has + * been configured. This board-specific function is responsible for + * configuring any on-board memories. + * + * Logic in tc397_memory_initialize must be careful to avoid using any + * global variables because those will be uninitialized at the time this + * function is called. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void tc397_memory_initialize(void) +{ + /* SDRAM was initialized by a bootloader in the supported configurations. */ +} + +/**************************************************************************** + * Name: tc397_board_initialize + * + * Description: + * All i.MX6 architectures must provide the following entry point. This + * entry point is called in the initialization phase -- after + * tc397_memory_initialize and after all memory has been configured and + * mapped but before any devices have been initialized. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void tc397_board_initialize(void) +{ +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_intitialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board initialization */ + + tc397_bringup(); +} +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/tricore/tc3xx/tc397/src/tc397_bringup.c b/boards/tricore/tc3xx/tc397/src/tc397_bringup.c new file mode 100644 index 0000000000000..25936c520cfb2 --- /dev/null +++ b/boards/tricore/tc3xx/tc397/src/tc397_bringup.c @@ -0,0 +1,73 @@ +/**************************************************************************** + * boards/tricore/tc3xx/tc397/src/tc397_bringup.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "tc397.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: tc397_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int tc397_bringup(void) +{ + int ret; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret); + } +#endif + +#ifdef CONFIG_FS_TMPFS + /* Mount the tmpfs file system */ + + ret = nx_mount(NULL, CONFIG_LIBC_TMPDIR, "tmpfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount tmpfs at %s: %d\n", + CONFIG_LIBC_TMPDIR, ret); + } +#endif + + UNUSED(ret); + return OK; +} diff --git a/boards/x86_64/intel64/qemu-intel64/CMakeLists.txt b/boards/x86_64/intel64/qemu-intel64/CMakeLists.txt new file mode 100644 index 0000000000000..924df77850d27 --- /dev/null +++ b/boards/x86_64/intel64/qemu-intel64/CMakeLists.txt @@ -0,0 +1,21 @@ +# ############################################################################## +# boards/x86_64/intel64/qemu-intel64/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +add_subdirectory(src) diff --git a/boards/x86_64/intel64/qemu-intel64/configs/earlyfb/defconfig b/boards/x86_64/intel64/qemu-intel64/configs/earlyfb/defconfig new file mode 100644 index 0000000000000..7b23a3c833c03 --- /dev/null +++ b/boards/x86_64/intel64/qemu-intel64/configs/earlyfb/defconfig @@ -0,0 +1,65 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_SERIAL is not set +CONFIG_ARCH="x86_64" +CONFIG_ARCH_BOARD="qemu-intel64" +CONFIG_ARCH_BOARD_INTEL64_QEMU=y +CONFIG_ARCH_CHIP="intel64" +CONFIG_ARCH_CHIP_INTEL64_QEMU=y +CONFIG_ARCH_INTEL64_CORE_FREQ_KHZ=2600000 +CONFIG_ARCH_SIZET_LONG=y +CONFIG_ARCH_X86_64=y +CONFIG_BOARD_LOOPSPERMSEC=999 +CONFIG_BOOT_RUNFROMEXTSRAM=y +CONFIG_BUILTIN=y +CONFIG_CONSOLE_SYSLOG=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_PCI=y +CONFIG_DEBUG_PCI_ERROR=y +CONFIG_DEBUG_PCI_INFO=y +CONFIG_DEBUG_PCI_WARN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLO_STACKSIZE=4194304 +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=4194304 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=4194304 +CONFIG_LIBM=y +CONFIG_MULTBOOT2_FB_TERM=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFCONFIG=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_READLINE=y +CONFIG_NXFONTS=y +CONFIG_NXFONT_MONO5X8=y +CONFIG_PREALLOC_CHILDSTATUS=16 +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_PTHREAD_STACK_DEFAULT=4194304 +CONFIG_PTHREAD_STACK_MIN=4194304 +CONFIG_RAM_SIZE=268435456 +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_IRQMONITOR=y +CONFIG_SCHED_TICKLESS=y +CONFIG_SCHED_TICKLESS_ALARM=y +CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP=y +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_DEFAULT=y +CONFIG_START_DAY=3 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_CLE=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_TIME64=y +CONFIG_USEC_PER_TICK=1 +CONFIG_VIRT=y +CONFIG_VIRT_QEMU_EDU=y +CONFIG_VIRT_QEMU_PCI_TEST=y diff --git a/boards/x86_64/intel64/qemu-intel64/configs/nsh/defconfig b/boards/x86_64/intel64/qemu-intel64/configs/nsh/defconfig index cc5f5d72ff125..e487c9031d023 100644 --- a/boards/x86_64/intel64/qemu-intel64/configs/nsh/defconfig +++ b/boards/x86_64/intel64/qemu-intel64/configs/nsh/defconfig @@ -18,6 +18,7 @@ CONFIG_ARCH="x86_64" CONFIG_ARCH_BOARD="qemu-intel64" CONFIG_ARCH_BOARD_INTEL64_QEMU=y CONFIG_ARCH_CHIP="intel64" +CONFIG_ARCH_CHIP_INTEL64_QEMU=y CONFIG_ARCH_INTEL64_CORE_FREQ_KHZ=2600000 CONFIG_ARCH_SIZET_LONG=y CONFIG_ARCH_X86_64=y diff --git a/boards/x86_64/intel64/qemu-intel64/configs/ostest/defconfig b/boards/x86_64/intel64/qemu-intel64/configs/ostest/defconfig index dcd95a1fe82b9..c6ca8f3d851b2 100644 --- a/boards/x86_64/intel64/qemu-intel64/configs/ostest/defconfig +++ b/boards/x86_64/intel64/qemu-intel64/configs/ostest/defconfig @@ -18,12 +18,14 @@ CONFIG_ARCH="x86_64" CONFIG_ARCH_BOARD="qemu-intel64" CONFIG_ARCH_BOARD_INTEL64_QEMU=y CONFIG_ARCH_CHIP="intel64" +CONFIG_ARCH_CHIP_INTEL64_QEMU=y CONFIG_ARCH_INTEL64_CORE_FREQ_KHZ=2600000 CONFIG_ARCH_SIZET_LONG=y CONFIG_ARCH_X86_64=y CONFIG_BOARD_LOOPSPERMSEC=999 CONFIG_BOOT_RUNFROMEXTSRAM=y CONFIG_CONSOLE_SYSLOG=y +CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_IDLETHREAD_STACKSIZE=4194304 CONFIG_INIT_ENTRYPOINT="ostest_main" diff --git a/boards/x86_64/intel64/qemu-intel64/configs/pcitest/defconfig b/boards/x86_64/intel64/qemu-intel64/configs/pcitest/defconfig new file mode 100644 index 0000000000000..5f2c44e58a4b2 --- /dev/null +++ b/boards/x86_64/intel64/qemu-intel64/configs/pcitest/defconfig @@ -0,0 +1,70 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +CONFIG_16550_ADDRWIDTH=16 +CONFIG_16550_UART0=y +CONFIG_16550_UART0_BASE=0x3f8 +CONFIG_16550_UART0_CLOCK=1843200 +CONFIG_16550_UART0_IRQ=36 +CONFIG_16550_UART0_RXBUFSIZE=16 +CONFIG_16550_UART0_SERIAL_CONSOLE=y +CONFIG_16550_UART0_TXBUFSIZE=16 +CONFIG_16550_UART=y +CONFIG_ARCH="x86_64" +CONFIG_ARCH_BOARD="qemu-intel64" +CONFIG_ARCH_BOARD_INTEL64_QEMU=y +CONFIG_ARCH_CHIP="intel64" +CONFIG_ARCH_CHIP_INTEL64_QEMU=y +CONFIG_ARCH_INTEL64_CORE_FREQ_KHZ=2600000 +CONFIG_ARCH_SIZET_LONG=y +CONFIG_ARCH_X86_64=y +CONFIG_BOARD_LOOPSPERMSEC=999 +CONFIG_BOOT_RUNFROMEXTSRAM=y +CONFIG_BUILTIN=y +CONFIG_CONSOLE_SYSLOG=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_PCI=y +CONFIG_DEBUG_PCI_ERROR=y +CONFIG_DEBUG_PCI_INFO=y +CONFIG_DEBUG_PCI_WARN=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLO_STACKSIZE=4194304 +CONFIG_FS_PROCFS=y +CONFIG_IDLETHREAD_STACKSIZE=4194304 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=4194304 +CONFIG_LIBM=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFCONFIG=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_CHILDSTATUS=16 +CONFIG_PRIORITY_INHERITANCE=y +CONFIG_PTHREAD_MUTEX_TYPES=y +CONFIG_PTHREAD_STACK_DEFAULT=4194304 +CONFIG_PTHREAD_STACK_MIN=4194304 +CONFIG_RAM_SIZE=268435456 +CONFIG_SCHED_CHILD_STATUS=y +CONFIG_SCHED_HAVE_PARENT=y +CONFIG_SCHED_IRQMONITOR=y +CONFIG_SCHED_TICKLESS=y +CONFIG_SCHED_TICKLESS_ALARM=y +CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP=y +CONFIG_SCHED_WAITPID=y +CONFIG_SIG_DEFAULT=y +CONFIG_START_DAY=3 +CONFIG_START_MONTH=3 +CONFIG_START_YEAR=2011 +CONFIG_SYSTEM_CLE=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_TIME64=y +CONFIG_USEC_PER_TICK=1 +CONFIG_VIRT=y +CONFIG_VIRT_QEMU_EDU=y +CONFIG_VIRT_QEMU_PCI_TEST=y diff --git a/boards/x86_64/intel64/qemu-intel64/scripts/Make.defs b/boards/x86_64/intel64/qemu-intel64/scripts/Make.defs index f9a264dfbb76d..e55817d63fb3c 100644 --- a/boards/x86_64/intel64/qemu-intel64/scripts/Make.defs +++ b/boards/x86_64/intel64/qemu-intel64/scripts/Make.defs @@ -20,48 +20,6 @@ include $(TOPDIR)/.config include $(TOPDIR)/tools/Config.mk - -ifeq ($(CONFIG_DEBUG_SYMBOLS),y) - ARCHOPTIMIZATION = -g -endif - -ifneq ($(CONFIG_DEBUG_NOOPT),y) - ARCHOPTIMIZATION += -O2 -fno-optimize-sibling-calls -fno-omit-frame-pointer -fno-crossjumping -fno-delete-null-pointer-checks - -endif +include $(TOPDIR)/arch/x86_64/src/intel64/Toolchain.defs ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)qemu.ld - -ARCHCPUFLAGS = -fPIC -fno-stack-protector -mno-red-zone -mrdrnd -ARCHPICFLAGS = -fPIC -ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef - -# We have to use a cross-development toolchain under Cygwin because the native -# Cygwin toolchains don't generate ELF binaries. - -ifeq ($(CONFIG_WINDOWS_CYGWIN),y) -CROSSDEV = i486-nuttx-elf- -endif - -ifeq ($(CONFIG_HOST_MACOS),y) -CROSSDEV = x86_64-elf- -endif - -CC = $(CROSSDEV)gcc -CPP = $(CROSSDEV)gcc -E -LD = $(CROSSDEV)ld -STRIP = $(CROSSDEV)strip --strip-unneeded -AR = $(CROSSDEV)ar rcs -NM = $(CROSSDEV)nm -OBJCOPY = $(CROSSDEV)objcopy -OBJDUMP = $(CROSSDEV)objdump - -CFLAGS := $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe -CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -AFLAGS := $(CFLAGS) -D__ASSEMBLY__ - -ifeq ($(CONFIG_HOST_MACOS),y) -AFLAGS += -Wa,--divide -endif - -EXEEXT = .elf diff --git a/boards/x86_64/intel64/qemu-intel64/scripts/qemu.ld b/boards/x86_64/intel64/qemu-intel64/scripts/qemu.ld index 92b9a985c690f..4702c25b387ed 100644 --- a/boards/x86_64/intel64/qemu-intel64/scripts/qemu.ld +++ b/boards/x86_64/intel64/qemu-intel64/scripts/qemu.ld @@ -79,6 +79,7 @@ SECTIONS *(.gcc_except_table) *(.gnu.linkonce.r.*) *(.eh_frame) + *(.note.gnu.*) _erodata = ABSOLUTE(.); } @@ -98,7 +99,7 @@ SECTIONS *(.bss .bss.*) *(.gnu.linkonce.b.*) *(COMMON) - . = ALIGN(4); + . = ALIGN(16); _ebss = ABSOLUTE(.); } diff --git a/boards/x86_64/intel64/qemu-intel64/src/CMakeLists.txt b/boards/x86_64/intel64/qemu-intel64/src/CMakeLists.txt new file mode 100644 index 0000000000000..a343c0b0f313b --- /dev/null +++ b/boards/x86_64/intel64/qemu-intel64/src/CMakeLists.txt @@ -0,0 +1,33 @@ +# ############################################################################## +# boards/x86_64/intel64/qemu-intel64/src/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS qemu_boot.c qemu_bringup.c qemu_net.c) + +if(CONFIG_BOARDCTL) + list(APPEND SRCS qemu_appinit.c) +endif() + +if(CONFIG_BOARDCTL_RESET) + list(APPEND SRCS qemu_reset.c) +endif() + +target_sources(board PRIVATE ${SRCS}) + +set_property(GLOBAL PROPERTY LD_SCRIPT "${NUTTX_BOARD_DIR}/scripts/qemu.ld") diff --git a/boards/x86_64/intel64/qemu-intel64/src/Makefile b/boards/x86_64/intel64/qemu-intel64/src/Makefile index 7bdacd1f3cccd..41d7c4b173c1c 100644 --- a/boards/x86_64/intel64/qemu-intel64/src/Makefile +++ b/boards/x86_64/intel64/qemu-intel64/src/Makefile @@ -20,10 +20,14 @@ include $(TOPDIR)/Make.defs -CSRCS = qemu_boot.c qemu_bringup.c qemu_freq.c qemu_net.c +CSRCS = qemu_boot.c qemu_bringup.c qemu_net.c ifeq ($(CONFIG_BOARDCTL),y) CSRCS += qemu_appinit.c endif +ifeq ($(CONFIG_BOARDCTL_RESET),y) + CSRCS += qemu_reset.c +endif + include $(TOPDIR)/boards/Board.mk diff --git a/boards/x86_64/intel64/qemu-intel64/src/qemu_bringup.c b/boards/x86_64/intel64/qemu-intel64/src/qemu_bringup.c index 7cd5d551372f8..38675a887ef89 100644 --- a/boards/x86_64/intel64/qemu-intel64/src/qemu_bringup.c +++ b/boards/x86_64/intel64/qemu-intel64/src/qemu_bringup.c @@ -31,8 +31,12 @@ #include #include -#include +#ifdef CONFIG_ONESHOT +# include +#endif + +#include "x86_64_internal.h" #include "qemu_intel64.h" /**************************************************************************** @@ -45,8 +49,18 @@ int qemu_bringup(void) { +#ifdef CONFIG_ONESHOT + struct oneshot_lowerhalf_s *os = NULL; +#endif + int ret = OK; + /* Initialize the PCI bus */ + +#ifdef CONFIG_PCI + x86_64_pci_init(); +#endif + #ifdef CONFIG_FS_PROCFS /* Mount the procfs file system */ @@ -57,5 +71,13 @@ int qemu_bringup(void) } #endif +#ifdef CONFIG_ONESHOT + os = oneshot_initialize(0, 10); + if (os) + { + oneshot_register("/dev/oneshot", os); + } +#endif + return ret; } diff --git a/boards/x86_64/intel64/qemu-intel64/src/qemu_freq.c b/boards/x86_64/intel64/qemu-intel64/src/qemu_freq.c deleted file mode 100644 index 8782a487b0c6f..0000000000000 --- a/boards/x86_64/intel64/qemu-intel64/src/qemu_freq.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************** - * boards/x86_64/intel64/qemu-intel64/src/qemu_freq.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include -#include - -#include -#include - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -extern unsigned long x86_64_timer_freq; - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: x86_64_timer_initialize - * - * Description: - * Initializes all platform-specific timer facilities. This function is - * called early in the initialization sequence by up_initialize(). - * On return, the current up-time should be available from - * up_timer_gettime() and the interval timer is ready for use (but not - * actively timing. - * - * Provided by platform-specific code and called from the architecture- - * specific logic. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - * Assumptions: - * Called early in the initialization sequence before any special - * concurrency protections are required. - * - ****************************************************************************/ - -void x86_64_timer_calibrate_freq(void) -{ -#ifdef CONFIG_ARCH_INTEL64_HAVE_TSC_DEADLINE - - unsigned long crystal_freq; - unsigned long numerator; - unsigned long denominator; - - asm volatile("cpuid" - : "=c" (crystal_freq), "=b" (numerator), "=a" (denominator) - : "a" (X86_64_CPUID_TSC) - : "rdx", "memory"); - - if (numerator == 0 || denominator == 0 || crystal_freq == 0) - { - x86_64_timer_freq = CONFIG_ARCH_INTEL64_CORE_FREQ_KHZ * 1000L; - } - else - { - x86_64_timer_freq = crystal_freq / denominator * numerator; - } - -#else - x86_64_timer_freq = CONFIG_ARCH_INTEL64_APIC_FREQ_KHZ * 1000L; -#endif -} diff --git a/boards/x86_64/intel64/qemu-intel64/src/qemu_net.c b/boards/x86_64/intel64/qemu-intel64/src/qemu_net.c index 7514c9dfd741a..d538dae96f602 100644 --- a/boards/x86_64/intel64/qemu-intel64/src/qemu_net.c +++ b/boards/x86_64/intel64/qemu-intel64/src/qemu_net.c @@ -49,7 +49,7 @@ * ****************************************************************************/ -#ifdef CONFIG_NET +#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) void x86_64_netinitialize(void) { } diff --git a/boards/x86_64/intel64/qemu-intel64/src/qemu_reset.c b/boards/x86_64/intel64/qemu-intel64/src/qemu_reset.c new file mode 100644 index 0000000000000..8e17027c340bc --- /dev/null +++ b/boards/x86_64/intel64/qemu-intel64/src/qemu_reset.c @@ -0,0 +1,57 @@ +/**************************************************************************** + * boards/x86_64/intel64/qemu-intel64/src/qemu_reset.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value int this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ + up_systemreset(); + return 0; +} diff --git a/boards/xtensa/esp32/common/include/esp32_board_dac.h b/boards/xtensa/esp32/common/include/esp32_board_dac.h new file mode 100644 index 0000000000000..b364590db7c25 --- /dev/null +++ b/boards/xtensa/esp32/common/include/esp32_board_dac.h @@ -0,0 +1,84 @@ +/**************************************************************************** + * boards/xtensa/esp32/common/include/esp32_board_dac.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_XTENSA_ESP32_COMMON_INCLUDE_ESP32_DAC_H +#define __BOARDS_XTENSA_ESP32_COMMON_INCLUDE_ESP32_DAC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_dac_initialize + * + * Description: + * Initialize and register the Digital to Analog Convertor (DAC) driver. + * + * Input Parameters: + * path - The device number, used to build the device path as + * /dev/dacN + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_dac_initialize(const char *path); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __BOARDS_XTENSA_ESP32_COMMON_INCLUDE_ESP32_DAC_H */ diff --git a/boards/xtensa/esp32/common/include/esp32_board_rmt.h b/boards/xtensa/esp32/common/include/esp32_board_rmt.h new file mode 100644 index 0000000000000..0d218892f7eec --- /dev/null +++ b/boards/xtensa/esp32/common/include/esp32_board_rmt.h @@ -0,0 +1,97 @@ +/**************************************************************************** + * boards/xtensa/esp32/common/include/esp32_board_rmt.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_XTENSA_ESP32_COMMON_INCLUDE_ESP32_BOARD_RMT_H +#define __BOARDS_XTENSA_ESP32_COMMON_INCLUDE_ESP32_BOARD_RMT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_ESP_RMT + +/**************************************************************************** + * Name: board_rmt_rxinitialize + * + * Description: + * Initialize the RMT peripheral and register an RX device. + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the RX channel + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_rmt_rxinitialize(int ch, int pin); + +/**************************************************************************** + * Name: board_rmt_txinitialize + * + * Description: + * Initialize the RMT peripheral and register an TX device. + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the TX channel + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_rmt_txinitialize(int ch, int pin); + +#endif /* CONFIG_ESP_RMT */ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_XTENSA_ESP32_COMMON_INCLUDE_ESP32_BOARD_RMT_H */ diff --git a/boards/xtensa/esp32/common/include/esp32_zerocross.h b/boards/xtensa/esp32/common/include/esp32_zerocross.h new file mode 100644 index 0000000000000..bed369cbe93bc --- /dev/null +++ b/boards/xtensa/esp32/common/include/esp32_zerocross.h @@ -0,0 +1,73 @@ +/**************************************************************************** + * boards/xtensa/esp32/common/include/esp32_zerocross.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_EXTENSA_ESP32_COMMON_INCLUDE_ESPM32_ZEROCROSS_H +#define __BOARDS_EXTENSA_ESP32_COMMON_INCLUDE_ESPM32_ZEROCROSS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_zerocross_initialize + * + * Description: + * Initialize and register the zero cross driver + * + ****************************************************************************/ + +int board_zerocross_initialize(int devno); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __BOARDS_EXTENSA_ESP32_COMMON_INCLUDE_ESPM32_ZEROCROSS_H */ diff --git a/boards/xtensa/esp32/common/scripts/legacy_sections.ld b/boards/xtensa/esp32/common/scripts/legacy_sections.ld index 705b02fbbd574..c61da8a5b5549 100644 --- a/boards/xtensa/esp32/common/scripts/legacy_sections.ld +++ b/boards/xtensa/esp32/common/scripts/legacy_sections.ld @@ -112,6 +112,7 @@ SECTIONS *(.wifirxiram .wifirxiram.*) *(.wifi0iram .wifi0iram.*) + *(.wifiorslpiram .wifiorslpiram.*) *(.wifislpiram .wifislpiram.*) *(.wifislprxiram .wifislprxiram.*) *(.phyiram .phyiram.*) @@ -132,15 +133,39 @@ SECTIONS . = ALIGN (8); _sbss = ABSOLUTE(.); _bss_start = ABSOLUTE(.); + *(EXCLUDE_FILE(*libble_app.a *libbt.a *libbtdm_app.a *libnimble.a) .bss EXCLUDE_FILE(*libble_app.a *libbt.a *libbtdm_app.a *libnimble.a) .bss.*) *(.ext_ram.bss*) + *(EXCLUDE_FILE(*libble_app.a *libbt.a *libbtdm_app.a *libnimble.a) COMMON) + . = ALIGN(4); + _bt_controller_bss_start = ABSOLUTE(.); + *libble_app.a:(.bss .bss.*) + . = ALIGN(4); + _bt_controller_bss_end = ABSOLUTE(.); + . = ALIGN(4); + _bt_controller_common_start = ABSOLUTE(.); + *libble_app.a:(COMMON) + . = ALIGN(4); + _bt_controller_common_end = ABSOLUTE(.); + . = ALIGN(4); _bt_bss_start = ABSOLUTE(.); - *libbt.a:(.bss .bss.* COMMON) - . = ALIGN (4); + *libbt.a:(.bss .bss.*) + . = ALIGN(4); _bt_bss_end = ABSOLUTE(.); + . = ALIGN(4); + _bt_common_start = ABSOLUTE(.); + *libbt.a:(COMMON) + . = ALIGN(4); + _bt_common_end = ABSOLUTE(.); + . = ALIGN(4); _btdm_bss_start = ABSOLUTE(.); - *libbtdm_app.a:(.bss .bss.* COMMON) - . = ALIGN (4); + *libbtdm_app.a:(.bss .bss.*) + . = ALIGN(4); _btdm_bss_end = ABSOLUTE(.); + . = ALIGN(4); + _btdm_common_start = ABSOLUTE(.); + *libbtdm_app.a:(COMMON) + . = ALIGN(4); + _btdm_common_end = ABSOLUTE(.); . = ALIGN (8); *(.dynsbss) *(.sbss) @@ -253,6 +278,13 @@ SECTIONS _srodata = ABSOLUTE(.); *(.rodata) *(.rodata.*) +#ifdef CONFIG_ESP32_WIRELESS + *(.rodata_wlog_verbose.*) + *(.rodata_wlog_debug.*) + *(.rodata_wlog_info.*) + *(.rodata_wlog_warning.*) + *(.rodata_wlog_error.*) +#endif *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ *(.gnu.linkonce.r.*) *(.rodata1) @@ -288,6 +320,13 @@ SECTIONS *(.xt_except_desc_end) *(.dynamic) *(.gnu.version_d) + + /* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */ + + soc_reserved_memory_region_start = ABSOLUTE(.); + KEEP (*(.reserved_memory_address)) + soc_reserved_memory_region_end = ABSOLUTE(.); + _erodata = ABSOLUTE(.); /* Literals are also RO data. */ _lit4_start = ABSOLUTE(.); diff --git a/boards/xtensa/esp32/common/src/Make.defs b/boards/xtensa/esp32/common/src/Make.defs index 121dea0e4fb75..6ff049752f7ac 100644 --- a/boards/xtensa/esp32/common/src/Make.defs +++ b/boards/xtensa/esp32/common/src/Make.defs @@ -140,8 +140,16 @@ ifeq ($(CONFIG_RGBLED),y) CSRCS += esp32_rgbled.c endif -ifeq ($(CONFIG_ESP32_RMT),y) - CSRCS += esp32_rmt.c +ifeq ($(CONFIG_ESP_RMT),y) + CSRCS += esp32_board_rmt.c +endif + +#ifeq ($(CONFIG_DAC),y) + CSRCS += esp32_board_dac.c +#endif + +ifeq ($(CONFIG_SENSORS_ZEROCROSS),y) + CSRCS += esp32_zerocross.c endif DEPPATH += --dep-path src diff --git a/boards/xtensa/esp32/common/src/esp32_board_dac.c b/boards/xtensa/esp32/common/src/esp32_board_dac.c new file mode 100644 index 0000000000000..fb71f35b12912 --- /dev/null +++ b/boards/xtensa/esp32/common/src/esp32_board_dac.c @@ -0,0 +1,79 @@ +/**************************************************************************** + * boards/xtensa/esp32/common/src/esp32_board_dac.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include +#include + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_dac_initialize + * + * Description: + * Initialize and register the Digital to Analog Convertor (DAC) driver. + * + * Input Parameters: + * path - The device number, used to build the device path as + * /dev/dacN + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_dac_initialize(const char *path) +{ + int ret; + + /* Initialize DAC */ + + struct dac_dev_s *dev = esp32_dac_initialize(); + if (dev != NULL) + { + /* Try to register the DAC */ + + ret = dac_register(path, dev); + if (ret < 0) + { + snerr("ERROR: Error registering DAC\n"); + } + } + else + { + ret = -ENODEV; + } + + return ret; +} diff --git a/boards/xtensa/esp32/common/src/esp32_board_rmt.c b/boards/xtensa/esp32/common/src/esp32_board_rmt.c new file mode 100644 index 0000000000000..993ec87361e94 --- /dev/null +++ b/boards/xtensa/esp32/common/src/esp32_board_rmt.c @@ -0,0 +1,155 @@ +/**************************************************************************** + * boards/xtensa/esp32/common/src/esp32_board_rmt.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "xtensa.h" + +#include +#include +#ifdef CONFIG_WS2812_NON_SPI_DRIVER +#include + +#include "espressif/esp_ws2812.h" +#endif + +#include "espressif/esp_rmt.h" + +#ifdef CONFIG_ESP_RMT + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_rmt_rxinitialize + * + * Description: + * Initialize the RMT peripheral and register an RX device. + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the RX channel + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_rmt_rxinitialize(int ch, int pin) +{ + int ret; + + struct rmt_dev_s *rmt = esp_rmt_rx_init(ch, pin); + + ret = rmtchar_register(rmt); + if (ret < 0) + { + rmterr("ERROR: rmtchar_register failed: %d\n", ret); + return ret; + } + + return ret; +} + +/**************************************************************************** + * Name: board_rmt_txinitialize + * + * Description: + * Initialize the RMT peripheral and register an TX device. + * + * Input Parameters: + * ch - The RMT's channel that will be used + * pin - The pin used for the TX channel + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int board_rmt_txinitialize(int ch, int pin) +{ + int ret; + struct rmt_dev_s *rmt; +#ifdef CONFIG_WS2812_NON_SPI_DRIVER + struct ws2812_dev_s *led; +#endif + + rmt = esp_rmt_tx_init(ch, pin); + + if (rmt == NULL) + { + rmterr("ERROR: esp_rmt_tx_init failed\n"); + return -ENODEV; + } + + ret = rmtchar_register(rmt); + if (ret < 0) + { + rmterr("ERROR: rmtchar_register failed: %d\n", ret); + return ret; + } + +#ifdef CONFIG_WS2812_NON_SPI_DRIVER + led = esp_ws2812_setup("/dev/leds0", rmt, + CONFIG_WS2812_LED_COUNT, false); + + if (led == NULL) + { + rmterr("ERROR: esp_ws2812_setup failed\n"); + return -ENODEV; + } +#endif + + return ret; +} +#endif diff --git a/boards/xtensa/esp32/common/src/esp32_rmt.c b/boards/xtensa/esp32/common/src/esp32_rmt.c deleted file mode 100644 index 44714b657fcc2..0000000000000 --- a/boards/xtensa/esp32/common/src/esp32_rmt.c +++ /dev/null @@ -1,282 +0,0 @@ -/**************************************************************************** - * boards/xtensa/esp32/common/src/esp32_rmt.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -#include "xtensa.h" - -#include -#include "esp32_rmt.h" - -#ifdef CONFIG_ESP32_RMT - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define APB_PERIOD (12.5) - -#define T0H ((uint16_t)(350 / APB_PERIOD)) // ns -#define T0L ((uint16_t)(900 / APB_PERIOD)) // ns -#define T1H ((uint16_t)(900 / APB_PERIOD)) // ns -#define T1L ((uint16_t)(350 / APB_PERIOD)) // ns -#define RES ((uint16_t)(60000 / APB_PERIOD)) // ns - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -static int rmt_open(struct file *filep) -{ - struct inode *inode = filep->f_inode; - struct rmt_dev_channel_s *dev_data = inode->i_private; - - struct rmt_dev_s *parent_dev = - (struct rmt_dev_s *)dev_data->parent_dev; - int ret; - irqstate_t flags; - DEBUGASSERT(parent_dev); - - nxsem_wait(&dev_data->tx_sem); - - flags = spin_lock_irqsave(&parent_dev->lock); - - if (dev_data->open_count == 0) - { - int ch_idx = dev_data->ch_idx; - - uint32_t reg0_addr = RMT_CHNCONF0_REG(ch_idx); - uint32_t reg1_addr = RMT_CHNCONF1_REG(ch_idx); - uint32_t reg_val = 0x00; - - /* a single memory block with double buffering is enough */ - - uint32_t mem_blocks = 1; - dev_data->available_words = RMT_DATA_MEMORY_BLOCK_WORDS*mem_blocks; - dev_data->reload_thresh = dev_data->available_words / 2; - uint32_t start_addr_chn = RMT_DATA_BASE_ADDR + - RMT_DATA_MEMORY_BLOCK_WORDS * 4 * ch_idx; - - dev_data->start_address = start_addr_chn; - - reg_val = (mem_blocks) << 24; - uint32_t clock_divider = 1; - reg_val |= (clock_divider); - putreg32(reg_val, reg0_addr); - reg_val = 0; - - /* use APB clock */ - - reg_val |= RMT_REF_ALWAYS_ON_CHN; - - /* memory block in transmission mode */ - - reg_val &= ~RMT_MEM_OWNER_CHN; - putreg32(reg_val, reg1_addr); - - /* set when the buffer swapping IRQ must be generated */ - - uint32_t reload_addr = RMT_CHN_TX_LIM_REG(ch_idx); - rmtinfo("Setting thr limit at %08X to %d", - reload_addr, dev_data->reload_thresh); - putreg32(dev_data->reload_thresh, reload_addr); - - /* allow direct access to RMT's memory */ - - modifyreg32(RMT_APB_CONF_REG, 0, BIT(0)); - } - else - { - rmtwarn("Be careful on opening this channel multiple times"); - } - - dev_data->open_count += 1; - - ret = OK; - - spin_unlock_irqrestore(&parent_dev->lock, flags); - nxsem_post(&dev_data->tx_sem); - - return ret; -} - -static int rmt_close(struct file *filep) -{ - struct inode *inode = filep->f_inode; - struct rmt_dev_channel_s *dev_data = inode->i_private; - - struct rmt_dev_s *parent_dev = - (struct rmt_dev_s *)dev_data->parent_dev; - - int ret; - irqstate_t flags; - DEBUGASSERT(parent_dev); - nxsem_wait(&dev_data->tx_sem); - flags = spin_lock_irqsave(&parent_dev->lock); - - dev_data->open_count -= 1; - - ret = OK; - - spin_unlock_irqrestore(&parent_dev->lock, flags); - nxsem_post(&dev_data->tx_sem); - return ret; -} - -static ssize_t rmt_write(struct file *filep, - const char *data, - size_t len) -{ - struct inode *inode = filep->f_inode; - struct rmt_dev_channel_s *dev_data = inode->i_private; - - struct rmt_dev_s *parent_dev = - (struct rmt_dev_s *)dev_data->parent_dev; - - irqstate_t flags; - size_t len_in_words = len / 4; - - DEBUGASSERT(parent_dev); - - if (data == NULL || (len_in_words == 0) || (len % 4)) - { - return -EINVAL; - } - - flags = spin_lock_irqsave(&parent_dev->lock); - - /* set RMT's memory as writable */ - - uint32_t reg1_addr = RMT_CHNCONF1_REG(dev_data->ch_idx); - modifyreg32(reg1_addr, 0, RMT_MEM_RD_RST_CHN); - modifyreg32(reg1_addr, RMT_MEM_RD_RST_CHN, 0); - - dev_data->src = (uint32_t *)data; - dev_data->src_offset = 0; - dev_data->words_to_send = len_in_words; - - /* enable IRQs for buffer refill and End-of-Transmition (EOT) */ - - modifyreg32( - RMT_INT_ENA_REG, - 0, - RMT_CHN_TX_THR_EVENT_INT_ENA(dev_data->ch_idx) | - RMT_CHN_TX_END_INT_ENA(dev_data->ch_idx)); - - rmt_load_tx_buffer(dev_data); - - /* tell RMT to start the transmition */ - - modifyreg32(reg1_addr, 0, RMT_TX_START_CHN(dev_data->ch_idx)); - - spin_unlock_irqrestore(&parent_dev->lock, flags); - - /* wait for the transmition to finish */ - - nxsem_wait(&dev_data->tx_sem); - nxsem_post(&dev_data->tx_sem); - - return len; -} - -/**************************************************************************** - * Name: board_rmt_initialize - * - * Description: - * Initialize and register the RMT driver - * - * Input Parameters: - * devno - The device number, used to build the device path as /dev/rmtN - * rmt_dev - Pointer to the RMT device that will be used - * nleds - number of LEDs - * - * Returned Value: - * Zero (OK) on success; a negated errno value on failure. - * - ****************************************************************************/ - -static const struct file_operations g_rmt_channel_fops = -{ - rmt_open, /* open */ - rmt_close, /* close */ - NULL, /* read */ - rmt_write, /* write */ - NULL, /* seek */ - NULL, /* ioctl */ -}; - -int board_rmt_initialize(int channel, int output_pin) -{ - struct rmt_dev_s *rmt_dev = esp32_rmtinitialize(); - DEBUGASSERT(rmt_dev); - - char devpath[13]; - int ret; - - rmt_attach_pin_to_channel(rmt_dev, channel, output_pin); - - struct rmt_dev_channel_s *channel_data = &(rmt_dev->channels[channel]); - - /* Register the RMT driver at the specified location. */ - - snprintf(devpath, sizeof(devpath), "/dev/rmt%d", channel); - - /* Register the character driver */ - - ret = register_driver(devpath, &g_rmt_channel_fops, 0666, channel_data); - - if (ret < 0) - { - rmterr("ERROR: board_rmt_initialize(%s) failed: %d\n", - devpath, ret); - return ret; - } - - return OK; -} -#endif diff --git a/boards/xtensa/esp32/common/src/esp32_zerocross.c b/boards/xtensa/esp32/common/src/esp32_zerocross.c new file mode 100644 index 0000000000000..45a945508b3dc --- /dev/null +++ b/boards/xtensa/esp32/common/src/esp32_zerocross.c @@ -0,0 +1,148 @@ +/**************************************************************************** + * boards/xtensa/esp32/common/src/esp32_zerocross.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include "esp32_gpio.h" +#include "hardware/esp32_gpio_sigmap.h" +#include "esp32-wrover-kit.h" +#include "esp32_zerocross.h" + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void zcross_enable(const struct zc_lowerhalf_s *lower, + zc_interrupt_t handler, void *arg); + +static int zcross_interrupt(int irq, void *context, void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Current interrupt handler and argument */ + +static zc_interrupt_t g_zcrosshandler; +static void *g_zcrossarg; + +/* This is the zero cross lower half driver interface */ + +static struct zc_lowerhalf_s g_zcrosslower = +{ + .zc_enable = zcross_enable, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: zcross_enable + * + * Description: + * Enable interrupts on the selected zero cross pin. And empty + * set will disable all interrupts. + * + ****************************************************************************/ + +static void zcross_enable(const struct zc_lowerhalf_s *lower, + zc_interrupt_t handler, void *arg) +{ + irqstate_t flags; + int irq = ESP32_PIN2IRQ(GPIO_ZERO_CROSS_IRQ); + int ret; + + flags = enter_critical_section(); + + if (handler) + { + g_zcrosshandler = handler; + g_zcrossarg = arg; + } + + /* Start with all interrupts disabled */ + + esp32_gpioirqdisable(irq); + + ret = irq_attach(irq, zcross_interrupt, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: zcross_enable() failed: %d\n", ret); + leave_critical_section(flags); + } + + esp32_gpioirqenable(irq, RISING); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: zcross_interrupt + * + * Description: + * Zero Cross interrupt handler + * + ****************************************************************************/ + +static int zcross_interrupt(int irq, void *context, void *arg) +{ + DEBUGASSERT(g_zcrosshandler != NULL); + if (g_zcrosshandler) + { + g_zcrosshandler(&g_zcrosslower, g_zcrossarg); + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_zerocross_initialize + * + * Description: + * Initialize and register the zero cross driver + * + ****************************************************************************/ + +int board_zerocross_initialize(int devno) +{ + esp32_configgpio(GPIO_ZERO_CROSS_IRQ, INPUT_FUNCTION_3 | PULLUP); + + /* Register the zero cross device as /dev/zc0 */ + + return zc_register("/dev/zc0", &g_zcrosslower); +} diff --git a/boards/xtensa/esp32/esp32-2432S028/configs/lvgl/defconfig b/boards/xtensa/esp32/esp32-2432S028/configs/lvgl/defconfig index 6c422cf96737a..cb2e7aa893aa0 100644 --- a/boards/xtensa/esp32/esp32-2432S028/configs/lvgl/defconfig +++ b/boards/xtensa/esp32/esp32-2432S028/configs/lvgl/defconfig @@ -30,20 +30,20 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LCD_DEV=y CONFIG_LCD_ILI9341=y CONFIG_LCD_ILI9341_IFACE0=y -CONFIG_LV_COLOR_16_SWAP=y -CONFIG_LV_DEMO_WIDGETS_SLIDESHOW=y -CONFIG_LV_MEM_CUSTOM=y -CONFIG_LV_PORT_LCDDEV_DOUBLE_BUFFER=y -CONFIG_LV_PORT_USE_LCDDEV=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y CONFIG_LV_USE_DEMO_WIDGETS=y CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_LCD=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-2432S028/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-2432S028/configs/nsh/defconfig index 6704302841ec1..57b3af76eefbd 100644 --- a/boards/xtensa/esp32/esp32-2432S028/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-2432S028/configs/nsh/defconfig @@ -24,6 +24,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-audio-kit/configs/audio/defconfig b/boards/xtensa/esp32/esp32-audio-kit/configs/audio/defconfig index 0038e2c7fc198..cb25b520c8aba 100644 --- a/boards/xtensa/esp32/esp32-audio-kit/configs/audio/defconfig +++ b/boards/xtensa/esp32/esp32-audio-kit/configs/audio/defconfig @@ -33,6 +33,7 @@ CONFIG_AUDIO_NUM_BUFFERS=4 CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_TASK_STACKSIZE=4096 CONFIG_DEV_URANDOM=y @@ -65,6 +66,7 @@ CONFIG_I2C=y CONFIG_I2S_DMADESC_NUM=4 CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NAME_MAX=48 diff --git a/boards/xtensa/esp32/esp32-audio-kit/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-audio-kit/configs/nsh/defconfig index 49d27058fe9a4..3ea695f09e231 100644 --- a/boards/xtensa/esp32/esp32-audio-kit/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-audio-kit/configs/nsh/defconfig @@ -25,6 +25,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-audio-kit/configs/wifi/defconfig b/boards/xtensa/esp32/esp32-audio-kit/configs/wifi/defconfig index dc09cac1573ac..025be20c32cad 100644 --- a/boards/xtensa/esp32/esp32-audio-kit/configs/wifi/defconfig +++ b/boards/xtensa/esp32/esp32-audio-kit/configs/wifi/defconfig @@ -37,6 +37,7 @@ CONFIG_ESP32_WIFI=y CONFIG_FS_PROCFS=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NAME_MAX=48 diff --git a/boards/xtensa/esp32/esp32-devkitc/Kconfig b/boards/xtensa/esp32/esp32-devkitc/Kconfig index ba68cdbe1a154..4bb9a6a531472 100644 --- a/boards/xtensa/esp32/esp32-devkitc/Kconfig +++ b/boards/xtensa/esp32/esp32-devkitc/Kconfig @@ -10,28 +10,24 @@ if PM config PM_ALARM_SEC int "PM_STANDBY delay (seconds)" default 15 - depends on PM ---help--- Number of seconds to wait in PM_STANDBY before going to PM_STANDBY mode. config PM_ALARM_NSEC int "PM_STANDBY delay (nanoseconds)" default 0 - depends on PM ---help--- Number of additional nanoseconds to wait in PM_STANDBY before going to PM_STANDBY mode. config PM_SLEEP_WAKEUP_SEC int "PM_SLEEP delay (seconds)" default 20 - depends on PM ---help--- Number of seconds to wait in PM_SLEEP. config PM_SLEEP_WAKEUP_NSEC int "PM_SLEEP delay (nanoseconds)" default 0 - depends on PM ---help--- Number of additional nanoseconds to wait in PM_SLEEP. diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/audio/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/audio/defconfig index 077f2f341470a..7f0e3d834a2c5 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/audio/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/audio/defconfig @@ -18,7 +18,7 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y -CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y @@ -39,7 +39,6 @@ CONFIG_CS4344_BUFFER_SIZE=2048 CONFIG_CS4344_INFLIGHT=4 CONFIG_CS4344_NUM_BUFFERS=2 CONFIG_CS4344_WORKER_STACKSIZE=4096 -CONFIG_DEBUG_NOOPT=y CONFIG_DEFAULT_TASK_STACKSIZE=4096 CONFIG_DEV_URANDOM=y CONFIG_DRIVERS_AUDIO=y @@ -66,6 +65,7 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_I2S_DMADESC_NUM=4 CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=24 CONFIG_IOB_THROTTLE=0 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/ble/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/ble/defconfig index ec1bd9b4e17e2..35954edc08976 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/ble/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/ble/defconfig @@ -36,6 +36,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_MTD_PARTITION_NAMES=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/blewifi/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/blewifi/defconfig index c988cbc1d7676..0cf81f77ba92a 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/blewifi/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/blewifi/defconfig @@ -38,7 +38,6 @@ CONFIG_ESP32_SPIFLASH_SPIFFS=y CONFIG_ESP32_STORAGE_MTD_SIZE=0x80000 CONFIG_ESP32_UART0=y CONFIG_ESP32_WIFI=y -CONFIG_ESP32_WIFI_BT_COEXIST=y CONFIG_ESP32_WIFI_STATION_SOFTAP=y CONFIG_EXAMPLES_DHCPD=y CONFIG_EXAMPLE_POWER_SAVE_MIN_MODEM=y @@ -47,6 +46,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NAME_MAX=48 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/bmp280/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/bmp280/defconfig index 963dd0b825356..232d0dd5c8f8b 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/bmp280/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/bmp280/defconfig @@ -34,6 +34,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/buttons/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/buttons/defconfig index 53b53a0e48ab2..361b4b5261c8e 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/buttons/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/buttons/defconfig @@ -29,6 +29,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INPUT=y CONFIG_INPUT_BUTTONS=y CONFIG_INPUT_BUTTONS_LOWER=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/cxx/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/cxx/defconfig index c29b2775788b7..4cbfc6144a173 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/cxx/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/cxx/defconfig @@ -24,6 +24,7 @@ CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LIBCXX=y CONFIG_LIBCXXABI=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/dac/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/dac/defconfig new file mode 100644 index 0000000000000..d1f1abdfc4ae4 --- /dev/null +++ b/boards/xtensa/esp32/esp32-devkitc/configs/dac/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ANALOG=y +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32_DEVKITC=y +CONFIG_ARCH_CHIP="esp32" +CONFIG_ARCH_CHIP_ESP32=y +CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DAC=y +CONFIG_ESP32_UART0=y +CONFIG_EXAMPLES_DAC=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=3 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSLOG_BUFFER=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/efuse/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/efuse/defconfig index 417acf66e9424..5f66555b6a00c 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/efuse/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/efuse/defconfig @@ -45,6 +45,7 @@ CONFIG_ESP32_WIFI=y CONFIG_FS_PROCFS=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NAME_MAX=48 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/elf/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/elf/defconfig index 01db1c6438c8e..bb14a814b6c56 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/elf/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/elf/defconfig @@ -36,6 +36,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_PERROR_STDOUT=y CONFIG_LIBC_STRERROR=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/knsh/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/knsh/defconfig index 365381ce4534c..56c46e1e198f9 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/knsh/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/knsh/defconfig @@ -35,6 +35,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NDEBUG=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/leds/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/leds/defconfig index 82ddbd87df361..5468ef105c2be 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/leds/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/leds/defconfig @@ -26,6 +26,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/max6675/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/max6675/defconfig index 4317ce3182492..d33878a4a7f57 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/max6675/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/max6675/defconfig @@ -28,6 +28,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/mcp2515/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/mcp2515/defconfig index 7639547de8714..94f44deed96c0 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/mcp2515/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/mcp2515/defconfig @@ -32,6 +32,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_nsh/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_nsh/defconfig index 6443f1ade7e37..b8e892c918573 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_nsh/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_nsh/defconfig @@ -20,13 +20,13 @@ CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_ESP32_APP_FORMAT_MCUBOOT=y -CONFIG_ESP32_BOOTLOADER_BUILD_FROM_SOURCE=y CONFIG_ESP32_UART0=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_slot_confirm/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_slot_confirm/defconfig index 73cec80517750..c1b57be7a60b0 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_slot_confirm/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_slot_confirm/defconfig @@ -30,6 +30,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_update_agent/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_update_agent/defconfig index 7e4a46965b748..93c0997965501 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_update_agent/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_update_agent/defconfig @@ -35,9 +35,9 @@ CONFIG_EXAMPLES_MCUBOOT_UPDATE_AGENT_DL_BUFFER_SIZE=4096 CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y -CONFIG_HOST_MACOS=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NAME_MAX=48 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/modbus/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/modbus/defconfig index f7438f0119d5a..61044ab9b59e8 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/modbus/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/modbus/defconfig @@ -33,6 +33,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_MODBUS=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/module/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/module/defconfig index 95c1575f0c954..f950dc11a2ccf 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/module/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/module/defconfig @@ -37,6 +37,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_MODULE=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/mqttc/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/mqttc/defconfig index 847ee5877939e..2151a2933a0a2 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/mqttc/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/mqttc/defconfig @@ -33,6 +33,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=24 CONFIG_IOB_THROTTLE=0 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/ms5611/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/ms5611/defconfig index e90cbf8b9b0da..26d676efcc4f8 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/ms5611/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/ms5611/defconfig @@ -33,6 +33,7 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_I2CTOOL_DEFFREQ=100000 CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_MS56XX_I2C_FREQUENCY=100000 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/nsh/defconfig index 13cdd958df971..07b9e4c75faed 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/nsh/defconfig @@ -25,6 +25,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/nxdiag/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/nxdiag/defconfig index b7feb3c00de06..ad468781c9be4 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/nxdiag/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/nxdiag/defconfig @@ -25,6 +25,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/nxlooper/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/nxlooper/defconfig index 470c674f31853..7edfcc0363673 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/nxlooper/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/nxlooper/defconfig @@ -67,6 +67,7 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_I2S_DMADESC_NUM=4 CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=24 CONFIG_IOB_THROTTLE=0 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/oneshot/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/oneshot/defconfig index 848b503de58e1..381c9ea910b99 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/oneshot/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/oneshot/defconfig @@ -33,6 +33,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/ostest/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/ostest/defconfig index f86a0ef898380..233b8a72d489e 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/ostest/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/ostest/defconfig @@ -26,6 +26,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/pm/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/pm/defconfig index 9b9edee515097..7f6c0ca6aadc3 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/pm/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/pm/defconfig @@ -21,10 +21,12 @@ CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_ESP32_UART0=y CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y @@ -35,6 +37,7 @@ CONFIG_NSH_READLINE=y CONFIG_PM=y CONFIG_PM_GOVERNOR_EXPLICIT_RELAX=-1 CONFIG_PM_GOVERNOR_GREEDY=y +CONFIG_PM_PROCFS=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/psram/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/psram/defconfig index 90539ded89e1c..9450b5475eb07 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/psram/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/psram/defconfig @@ -30,6 +30,7 @@ CONFIG_HEAP2_BASE=0x3f800000 CONFIG_HEAP2_SIZE=4194304 CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=36 CONFIG_IOB_NCHAINS=36 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/psram_usrheap/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/psram_usrheap/defconfig index 412f89482f5f8..171374f6b016d 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/psram_usrheap/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/psram_usrheap/defconfig @@ -32,6 +32,7 @@ CONFIG_HEAP2_BASE=0x3f800000 CONFIG_HEAP2_SIZE=4194304 CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=36 CONFIG_IOB_NCHAINS=36 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/pwm/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/pwm/defconfig index fd021f08c385c..e75c41c011b7a 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/pwm/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/pwm/defconfig @@ -34,6 +34,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/qemu-openeth/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/qemu-openeth/defconfig new file mode 100644 index 0000000000000..79830b1ef9216 --- /dev/null +++ b/boards/xtensa/esp32/esp32-devkitc/configs/qemu-openeth/defconfig @@ -0,0 +1,69 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32-devkitc" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32_DEVKITC=y +CONFIG_ARCH_CHIP="esp32" +CONFIG_ARCH_CHIP_ESP32=y +CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ESP32_OPENETH=y +CONFIG_ESP32_QEMU_IMAGE=y +CONFIG_ESP32_UART0=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=3 +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0a000203 +CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDEV_WORK_THREAD=y +CONFIG_NETINIT_DRIPADDR=0x0a000202 +CONFIG_NETINIT_IPADDR=0x0a000215 +CONFIG_NET_ARP_SEND=y +CONFIG_NET_BINDTODEVICE=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_NPOLLWAITERS=4 +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_ROUTE=y +CONFIG_NET_TCP=y +CONFIG_NET_TCPBACKLOG=y +CONFIG_NET_TCP_NPOLLWAITERS=8 +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NET_UDP_NPOLLWAITERS=8 +CONFIG_NET_UDP_WRITE_BUFFERS=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSLOG_BUFFER=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_PING=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/random/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/random/defconfig index c42af820f8150..57b7c36e0ffa7 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/random/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/random/defconfig @@ -27,6 +27,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/rmt/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/rmt/defconfig index 6bf5a0109fedd..3878b2eacec7b 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/rmt/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/rmt/defconfig @@ -19,15 +19,18 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y -CONFIG_ESP32_RMT=y CONFIG_ESP32_UART0=y -CONFIG_EXAMPLES_WS2812_ESP32_RMT=y -CONFIG_EXPERIMENTAL=y +CONFIG_ESP_RMT=y +CONFIG_EXAMPLES_RMTCHAR=y +CONFIG_EXAMPLES_RMTCHAR_RX=y +CONFIG_EXAMPLES_RMTCHAR_TX=y +CONFIG_EXAMPLES_WS2812=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y @@ -38,6 +41,9 @@ CONFIG_NSH_READLINE=y CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 +CONFIG_RMT=y +CONFIG_RMTCHAR=y +CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE=256 CONFIG_RR_INTERVAL=200 CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 @@ -46,3 +52,6 @@ CONFIG_START_YEAR=2011 CONFIG_SYSLOG_BUFFER=y CONFIG_SYSTEM_NSH=y CONFIG_UART0_SERIAL_CONSOLE=y +CONFIG_WS2812=y +CONFIG_WS2812_LED_COUNT=100 +CONFIG_WS2812_NON_SPI_DRIVER=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/rtc/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/rtc/defconfig index 30d5a25e7cbad..3b416b5659233 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/rtc/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/rtc/defconfig @@ -27,6 +27,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/sotest/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/sotest/defconfig index e2d6dd418b295..ce8e61efc7006 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/sotest/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/sotest/defconfig @@ -38,6 +38,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LIBC_DLFCN=y CONFIG_MM_REGIONS=3 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/spiflash/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/spiflash/defconfig index b163476ddce2b..995265f89f8a2 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/spiflash/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/spiflash/defconfig @@ -27,6 +27,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/tickless/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/tickless/defconfig index e4c0520485010..9d3da049d94bf 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/tickless/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/tickless/defconfig @@ -26,6 +26,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/timer/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/timer/defconfig index fe11edc7cd05e..91672a7d7f405 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/timer/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/timer/defconfig @@ -30,6 +30,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/twai/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/twai/defconfig index 165b64cb20c86..f4421b99edffc 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/twai/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/twai/defconfig @@ -27,6 +27,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/wamr_wasi_debug/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/wamr_wasi_debug/defconfig index 02d35f1b345be..1051b41122f75 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/wamr_wasi_debug/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/wamr_wasi_debug/defconfig @@ -7,6 +7,7 @@ # # CONFIG_ARCH_FPU is not set # CONFIG_ARCH_LEDS is not set +# CONFIG_FS_ANONMAP is not set # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_NSH_DISABLE_DATE is not set @@ -27,15 +28,13 @@ CONFIG_BUILTIN=y CONFIG_DEBUG_ASSERTIONS=y CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_MM=y -CONFIG_DEBUG_MM_ERROR=y -CONFIG_DEBUG_MM_WARN=y CONFIG_DEBUG_SYMBOLS=y CONFIG_DEFAULT_TASK_STACKSIZE=8192 CONFIG_DEV_LOOP=y CONFIG_DEV_URANDOM=y CONFIG_DEV_URANDOM_XORSHIFT128=y CONFIG_DEV_ZERO=y +CONFIG_DISABLE_MQUEUE_SYSV=y CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y CONFIG_EFUSE=y @@ -43,6 +42,7 @@ CONFIG_ESP32_EFUSE=y CONFIG_ESP32_IRAM_HEAP=y CONFIG_ESP32_RTC_HEAP=y CONFIG_ESP32_SPIFLASH=y +CONFIG_ESP32_STORAGE_MTD_SIZE=0x280000 CONFIG_ESP32_UART0=y CONFIG_ESP32_WIFI=y CONFIG_EXPERIMENTAL=y @@ -51,8 +51,8 @@ CONFIG_FS_PROCFS=y CONFIG_HOST_MACOS=y CONFIG_IDLETHREAD_STACKSIZE=4096 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y -CONFIG_INTERPRETERS_TOYWASM=y CONFIG_INTERPRETERS_WAMR=y CONFIG_INTERPRETERS_WAMR_AOT=y CONFIG_INTERPRETERS_WAMR_BULK_MEMORY=y @@ -69,7 +69,6 @@ CONFIG_IOB_THROTTLE=0 CONFIG_LIBC_DLFCN=y CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LIBM=y -CONFIG_MM_DUMP_ON_FAILURE=y CONFIG_MM_REGIONS=3 CONFIG_NETDB_DNSCLIENT=y CONFIG_NETDEV_LATEINIT=y @@ -92,7 +91,6 @@ CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=200 CONFIG_NSH_READLINE=y CONFIG_POSIX_SPAWN_DEFAULT_STACKSIZE=2048 -CONFIG_PREALLOC_MQ_MSGS=4 CONFIG_PREALLOC_TIMERS=4 CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/watchdog/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/watchdog/defconfig index b2705489dfb52..31f480fed27de 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/watchdog/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/watchdog/defconfig @@ -29,6 +29,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/watcher/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/watcher/defconfig index 8552ddf9510eb..ef39d05fa4f1b 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/watcher/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/watcher/defconfig @@ -29,6 +29,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/wifi/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/wifi/defconfig index 404fa6c94ec7c..f3a1bf7f9fa84 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/wifi/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/wifi/defconfig @@ -34,6 +34,7 @@ CONFIG_ESP32_WIFI=y CONFIG_FS_PROCFS=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NAME_MAX=48 diff --git a/boards/xtensa/esp32/esp32-devkitc/src/esp32-devkitc.h b/boards/xtensa/esp32/esp32-devkitc/src/esp32-devkitc.h index ae9f3edbb56cb..0e3ad3f7d7f5b 100644 --- a/boards/xtensa/esp32/esp32-devkitc/src/esp32-devkitc.h +++ b/boards/xtensa/esp32/esp32-devkitc/src/esp32-devkitc.h @@ -68,8 +68,16 @@ /* RMT gpio */ -#define RMT_OUTPUT_PIN 4 -#define RMT_CHANNEL 0 +#define RMT_RXCHANNEL 1 +#define RMT_TXCHANNEL 0 + +#ifdef CONFIG_RMT_LOOP_TEST_MODE +# define RMT_INPUT_PIN 0 +# define RMT_OUTPUT_PIN 0 +#else +# define RMT_INPUT_PIN 2 +# define RMT_OUTPUT_PIN 4 +#endif /**************************************************************************** * Public Types @@ -227,5 +235,18 @@ int board_ws2812_initialize( # endif # endif +/**************************************************************************** + * Name: openeth_initialize + * + * Description: + * This function may called from application-specific logic during its + * to perform board-specific initialization of the Open ETH interface + * + * + ****************************************************************************/ +#ifdef CONFIG_ESP32_OPENETH +int esp32_openeth_initialize(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __BOARDS_XTENSA_ESP32_ESP32_DEVKITC_SRC_ESP32_DEVKITC_H */ diff --git a/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c b/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c index dd384b163ef70..a4f0bb69b78d3 100644 --- a/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c +++ b/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c @@ -161,8 +161,12 @@ # include "esp32_max6675.h" #endif -#ifdef CONFIG_ESP32_RMT -# include "esp32_rmt.h" +#ifdef CONFIG_DAC +# include "esp32_board_dac.h" +#endif + +#ifdef CONFIG_ESP_RMT +# include "esp32_board_rmt.h" #endif #include "esp32-devkitc.h" @@ -332,6 +336,14 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_ESP32_OPENETH + ret = esp32_openeth_initialize(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize Open ETH ethernet.\n"); + } +#endif + /* First, register the timer drivers and let timer 1 for oneshot * if it is enabled. */ @@ -637,11 +649,25 @@ int esp32_bringup(void) } #endif -#ifdef CONFIG_ESP32_RMT - ret = board_rmt_initialize(RMT_CHANNEL, RMT_OUTPUT_PIN); +#ifdef CONFIG_DAC + ret = board_dac_initialize(CONFIG_ESP32_DAC_DEVPATH); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_dac_initialize(0) failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_ESP_RMT + ret = board_rmt_txinitialize(RMT_TXCHANNEL, RMT_OUTPUT_PIN); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); + } + + ret = board_rmt_rxinitialize(RMT_RXCHANNEL, RMT_INPUT_PIN); if (ret < 0) { - syslog(LOG_ERR, "ERROR: board_rmt_initialize() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); } #endif @@ -668,7 +694,7 @@ int esp32_bringup(void) #endif #ifdef CONFIG_WS2812 -# ifndef CONFIG_WS2812_NON_SPI_DRIVER +# ifndef CONFIG_WS2812_NON_SPI_DRIVER ret = board_ws2812_initialize(0, ESP32_SPI3, CONFIG_WS2812_LED_COUNT); if (ret < 0) { diff --git a/boards/xtensa/esp32/esp32-devkitc/src/esp32_ledc.c b/boards/xtensa/esp32/esp32-devkitc/src/esp32_ledc.c index ed8583870048a..7f424fddb2eee 100644 --- a/boards/xtensa/esp32/esp32-devkitc/src/esp32_ledc.c +++ b/boards/xtensa/esp32/esp32-devkitc/src/esp32_ledc.c @@ -33,7 +33,6 @@ #include -#include "chip.h" #include "esp32_ledc.h" /**************************************************************************** diff --git a/boards/xtensa/esp32/esp32-devkitc/src/esp32_twai.c b/boards/xtensa/esp32/esp32-devkitc/src/esp32_twai.c index 59cfc6b7876a6..d464e236d1ef7 100644 --- a/boards/xtensa/esp32/esp32-devkitc/src/esp32_twai.c +++ b/boards/xtensa/esp32/esp32-devkitc/src/esp32_twai.c @@ -30,8 +30,6 @@ #include #include -#include "chip.h" - #include "esp32_twai.h" #include "esp32-devkitc.h" diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/buttons/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/buttons/defconfig index e0a0701d86f39..ca8d00df731e0 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/configs/buttons/defconfig +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/buttons/defconfig @@ -28,6 +28,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INPUT=y CONFIG_INPUT_BUTTONS=y CONFIG_INPUT_BUTTONS_LOWER=y diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/ethernet/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/ethernet/defconfig index db5b7677d263b..b756592d2ba1c 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/configs/ethernet/defconfig +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/ethernet/defconfig @@ -25,6 +25,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NETDB_DNSCLIENT=y diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/nsh/defconfig index c362c05585be0..559cf37d677dc 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/nsh/defconfig @@ -24,6 +24,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/oneshot/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/oneshot/defconfig index de50b41df510e..5a1d5fe3a55bb 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/configs/oneshot/defconfig +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/oneshot/defconfig @@ -32,6 +32,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/rtc/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/rtc/defconfig index aa7ba1232dd34..771659d423062 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/configs/rtc/defconfig +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/rtc/defconfig @@ -26,6 +26,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-lyrat/configs/audio/defconfig b/boards/xtensa/esp32/esp32-lyrat/configs/audio/defconfig index f1f9e6a9fdb8e..417a8ca65c877 100644 --- a/boards/xtensa/esp32/esp32-lyrat/configs/audio/defconfig +++ b/boards/xtensa/esp32/esp32-lyrat/configs/audio/defconfig @@ -18,7 +18,7 @@ CONFIG_ARCH_BOARD_ESP32_LYRAT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y -CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y @@ -33,7 +33,6 @@ CONFIG_AUDIO_NUM_BUFFERS=4 CONFIG_BOARDCTL_ROMDISK=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y -CONFIG_DEBUG_NOOPT=y CONFIG_DEFAULT_TASK_STACKSIZE=4096 CONFIG_DEV_URANDOM=y CONFIG_DRIVERS_AUDIO=y @@ -66,6 +65,7 @@ CONFIG_I2C=y CONFIG_I2S_DMADESC_NUM=4 CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=24 CONFIG_IOB_THROTTLE=0 diff --git a/boards/xtensa/esp32/esp32-lyrat/configs/buttons/defconfig b/boards/xtensa/esp32/esp32-lyrat/configs/buttons/defconfig index fcc1daaa76358..6237a3b0c964d 100644 --- a/boards/xtensa/esp32/esp32-lyrat/configs/buttons/defconfig +++ b/boards/xtensa/esp32/esp32-lyrat/configs/buttons/defconfig @@ -32,6 +32,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INPUT=y CONFIG_INPUT_BUTTONS=y CONFIG_INPUT_BUTTONS_LOWER=y diff --git a/boards/xtensa/esp32/esp32-lyrat/configs/mmcsdspi/defconfig b/boards/xtensa/esp32/esp32-lyrat/configs/mmcsdspi/defconfig index ebf1abf81ec8b..be89d007b2b6c 100644 --- a/boards/xtensa/esp32/esp32-lyrat/configs/mmcsdspi/defconfig +++ b/boards/xtensa/esp32/esp32-lyrat/configs/mmcsdspi/defconfig @@ -42,6 +42,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=4000000 diff --git a/boards/xtensa/esp32/esp32-lyrat/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-lyrat/configs/nsh/defconfig index 5d5541c707783..dbcce40bb917a 100644 --- a/boards/xtensa/esp32/esp32-lyrat/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-lyrat/configs/nsh/defconfig @@ -25,6 +25,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-lyrat/configs/nxrecorder/defconfig b/boards/xtensa/esp32/esp32-lyrat/configs/nxrecorder/defconfig index 0dbc0c9edeff8..1dfdd1e7c1d02 100644 --- a/boards/xtensa/esp32/esp32-lyrat/configs/nxrecorder/defconfig +++ b/boards/xtensa/esp32/esp32-lyrat/configs/nxrecorder/defconfig @@ -61,7 +61,7 @@ CONFIG_I2C=y CONFIG_I2S_DMADESC_NUM=4 CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" -CONFIG_INIT_STACKSIZE=2048 +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MMCSD=y CONFIG_MM_REGIONS=3 diff --git a/boards/xtensa/esp32/esp32-lyrat/configs/rtptools/defconfig b/boards/xtensa/esp32/esp32-lyrat/configs/rtptools/defconfig index cd1d6d167b8b3..5b557a7b672c8 100644 --- a/boards/xtensa/esp32/esp32-lyrat/configs/rtptools/defconfig +++ b/boards/xtensa/esp32/esp32-lyrat/configs/rtptools/defconfig @@ -69,6 +69,7 @@ CONFIG_I2C=y CONFIG_I2S_DMADESC_NUM=4 CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_IOB_NBUFFERS=256 CONFIG_IOB_THROTTLE=72 diff --git a/boards/xtensa/esp32/esp32-lyrat/configs/wifi/defconfig b/boards/xtensa/esp32/esp32-lyrat/configs/wifi/defconfig index 178ff6a58c98b..1fb4fc37a3eab 100644 --- a/boards/xtensa/esp32/esp32-lyrat/configs/wifi/defconfig +++ b/boards/xtensa/esp32/esp32-lyrat/configs/wifi/defconfig @@ -37,6 +37,7 @@ CONFIG_ESP32_WIFI=y CONFIG_FS_PROCFS=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NAME_MAX=48 diff --git a/boards/xtensa/esp32/esp32-pico-kit/Kconfig b/boards/xtensa/esp32/esp32-pico-kit/Kconfig index 95b24e60058c4..15cc55e846bd1 100644 --- a/boards/xtensa/esp32/esp32-pico-kit/Kconfig +++ b/boards/xtensa/esp32/esp32-pico-kit/Kconfig @@ -10,28 +10,24 @@ if PM config PM_ALARM_SEC int "PM_STANDBY delay (seconds)" default 15 - depends on PM ---help--- Number of seconds to wait in PM_STANDBY before going to PM_STANDBY mode. config PM_ALARM_NSEC int "PM_STANDBY delay (nanoseconds)" default 0 - depends on PM ---help--- Number of additional nanoseconds to wait in PM_STANDBY before going to PM_STANDBY mode. config PM_SLEEP_WAKEUP_SEC int "PM_SLEEP delay (seconds)" default 20 - depends on PM ---help--- Number of seconds to wait in PM_SLEEP. config PM_SLEEP_WAKEUP_NSEC int "PM_SLEEP delay (nanoseconds)" default 0 - depends on PM ---help--- Number of additional nanoseconds to wait in PM_SLEEP. diff --git a/boards/xtensa/esp32/esp32-pico-kit/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-pico-kit/configs/nsh/defconfig index 9d20bb0ad9bde..85028106e9f1b 100644 --- a/boards/xtensa/esp32/esp32-pico-kit/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-pico-kit/configs/nsh/defconfig @@ -24,6 +24,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-sparrow-kit/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-sparrow-kit/configs/nsh/defconfig index 1cec9907f2b65..14775903e5eb1 100644 --- a/boards/xtensa/esp32/esp32-sparrow-kit/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-sparrow-kit/configs/nsh/defconfig @@ -22,12 +22,26 @@ CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y +CONFIG_AUDIO=y +CONFIG_AUDIO_DMA=y +CONFIG_AUDIO_FORMAT_RAW=y +CONFIG_AUDIO_I2S=y CONFIG_BME680_ENABLE_IIR_FILTER=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y +CONFIG_DMA=y +CONFIG_DMA_LINK=y +CONFIG_DRIVERS_AUDIO=y CONFIG_DRIVERS_VIDEO=y CONFIG_ESP32_I2C0=y CONFIG_ESP32_I2C0_SDAPIN=21 +CONFIG_ESP32_I2S0=y +CONFIG_ESP32_I2S0_BCLKPIN=25 +CONFIG_ESP32_I2S0_DATA_BIT_WIDTH_24BIT=y +CONFIG_ESP32_I2S0_DINPIN=26 +CONFIG_ESP32_I2S0_SAMPLE_RATE=8000 +CONFIG_ESP32_I2S0_WSPIN=27 +CONFIG_ESP32_I2S=y CONFIG_ESP32_LEDC=y CONFIG_ESP32_LEDC_CHANNEL0_PIN=14 CONFIG_ESP32_LEDC_CHANNEL1_PIN=13 @@ -47,8 +61,10 @@ CONFIG_FS_FAT=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_I2S_DMADESC_NUM=4 CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LCD_DEV=y @@ -75,6 +91,7 @@ CONFIG_RGBLED_INVERT=y CONFIG_RGBLED_LIGHTNESS_CORRECTION=y CONFIG_RGBLED_PWM_FREQ=200 CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_HPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SENSORS=y CONFIG_SENSORS_BME680=y diff --git a/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32-sparrow-kit.h b/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32-sparrow-kit.h index 787ccf99390f2..c4b87b22d9e65 100644 --- a/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32-sparrow-kit.h +++ b/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32-sparrow-kit.h @@ -106,6 +106,28 @@ int esp32_mmcsd_initialize(int minor); int esp32_spiflash_init(void); +/**************************************************************************** + * Name: board_i2sdev_initialize + * + * Description: + * This function is called by platform-specific, setup logic to configure + * and register the generic I2S audio driver. This function will register + * the driver as /dev/audio/pcm[x] where x is determined by the I2S port + * number. + * + * Input Parameters: + * port - The I2S port used for the device + * + * Returned Value: + * Zero is returned on success. Otherwise, a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +#if defined CONFIG_ESP32_I2S0 || defined CONFIG_ESP32_I2S1 +int board_i2sdev_initialize(int port); +#endif + /**************************************************************************** * Name: esp32_gpio_init ****************************************************************************/ diff --git a/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_bringup.c b/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_bringup.c index 3665696ccb4dd..4b06008116c96 100644 --- a/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_bringup.c +++ b/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_bringup.c @@ -80,6 +80,10 @@ # include "esp32_board_i2c.h" #endif +#ifdef CONFIG_ESP32_I2S +# include "esp32_i2s.h" +#endif + #ifdef CONFIG_SENSORS_BMP180 # include "esp32_bmp180.h" #endif @@ -343,6 +347,23 @@ int esp32_bringup(void) #endif +#ifdef CONFIG_ESP32_I2S + +#ifdef CONFIG_ESP32_I2S0 + + /* Configure I2S generic audio on I2S0 */ + + ret = board_i2sdev_initialize(ESP32_I2S0); + if (ret < 0) + { + syslog(LOG_ERR, "Failed to initialize I2S%d driver: %d\n", + CONFIG_ESP32_I2S0, ret); + } + +#endif /* CONFIG_ESP32_I2S0 */ + +#endif /* CONFIG_ESP32_I2S */ + #ifdef CONFIG_SENSORS_BMP180 /* Try to register BMP180 device in I2C0 */ diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/bmp180/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/bmp180/defconfig index c4b50a67c7c57..d066c0a5cea0b 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/bmp180/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/bmp180/defconfig @@ -27,6 +27,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/buttons/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/buttons/defconfig index e7383fb8fecca..d42485101a214 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/buttons/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/buttons/defconfig @@ -29,6 +29,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INPUT=y CONFIG_INPUT_BUTTONS=y CONFIG_INPUT_BUTTONS_LOWER=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/gpio/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/gpio/defconfig index f62412a4ff812..f5fbcae5a290f 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/gpio/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/gpio/defconfig @@ -28,6 +28,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/lcd1602/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/lcd1602/defconfig index 09fbf32721bc7..8e75755d3ecab 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/lcd1602/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/lcd1602/defconfig @@ -28,6 +28,7 @@ CONFIG_HAVE_CXXINITIALIZE=y CONFIG_I2C=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LCD_BACKPACK=y CONFIG_MM_REGIONS=3 diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/leds/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/leds/defconfig index 239ff5dd77bb1..374b8e4300368 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/leds/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/leds/defconfig @@ -26,6 +26,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/lua/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/lua/defconfig index 609992e0e27e7..9831f59ae5565 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/lua/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/lua/defconfig @@ -47,6 +47,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INPUT=y CONFIG_INPUT_BUTTONS=y CONFIG_INPUT_BUTTONS_LOWER=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/lvgl/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/lvgl/defconfig index 9fd2d2cf46a3f..0626bd77163d0 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/lvgl/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/lvgl/defconfig @@ -35,20 +35,20 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LCD_DEV=y CONFIG_LCD_ILI9341=y CONFIG_LCD_ILI9341_IFACE0=y -CONFIG_LV_COLOR_16_SWAP=y -CONFIG_LV_DEMO_WIDGETS_SLIDESHOW=y -CONFIG_LV_MEM_CUSTOM=y -CONFIG_LV_PORT_LCDDEV_DOUBLE_BUFFER=y -CONFIG_LV_PORT_USE_LCDDEV=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" +CONFIG_LV_NUTTX_LCD_DOUBLE_BUFFER=y +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y CONFIG_LV_USE_DEMO_WIDGETS=y CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_LCD=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/mmcsdspi/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/mmcsdspi/defconfig index 3a82ce042b074..6154fbf428eb9 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/mmcsdspi/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/mmcsdspi/defconfig @@ -42,6 +42,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MMCSD=y CONFIG_MMCSD_SPICLOCK=4000000 diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/nsh/defconfig index 41e6ac700b2c6..9bf9881da0480 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/nsh/defconfig @@ -25,6 +25,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/nx/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/nx/defconfig index c4934a214b89c..98bb38fc273d5 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/nx/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/nx/defconfig @@ -41,6 +41,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LCD_ILI9341=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/oneshot/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/oneshot/defconfig index d58512d5c308c..91efa1395ed1d 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/oneshot/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/oneshot/defconfig @@ -32,6 +32,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/rtc/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/rtc/defconfig index f9dde553ebb95..f9bb10ee574fd 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/rtc/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/rtc/defconfig @@ -27,6 +27,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32-wrover-kit.h b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32-wrover-kit.h index 1b9c715f47ee2..f1b040f0c8f96 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32-wrover-kit.h +++ b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32-wrover-kit.h @@ -57,6 +57,9 @@ #define ONESHOT_TIMER 1 #define ONESHOT_RESOLUTION_US 1 +/* Zero Cross */ +#define GPIO_ZERO_CROSS_IRQ 22 + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_bringup.c b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_bringup.c index b5261dc59c15f..342b518e6817d 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_bringup.c +++ b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_bringup.c @@ -105,6 +105,10 @@ # include "esp32_lcd_backpack.h" #endif +#ifdef CONFIG_SENSORS_ZEROCROSS +# include "esp32_zerocross.h" +#endif + #include "esp32-wrover-kit.h" /**************************************************************************** @@ -385,6 +389,17 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_SENSORS_ZEROCROSS + /* Register Zero Cross Driver */ + + ret = board_zerocross_initialize(0); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: board_zerocross_initialize() failed: %d\n", ret); + } +#endif + /* If we got here then perhaps not all initialization was successful, but * at least enough succeeded to bring-up NSH with perhaps reduced * capabilities. diff --git a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/gps/defconfig b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/gps/defconfig index 7193dc7a82571..1a7c1600b87e5 100644 --- a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/gps/defconfig +++ b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/gps/defconfig @@ -31,6 +31,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/nsh/defconfig b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/nsh/defconfig index da7fcacffcc49..159b056a895c7 100644 --- a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/nsh/defconfig +++ b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/nsh/defconfig @@ -27,6 +27,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/sx127x/defconfig b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/sx127x/defconfig index 39c7d423bd0a3..1684ab15948be 100644 --- a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/sx127x/defconfig +++ b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/sx127x/defconfig @@ -36,6 +36,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LPWAN_SX127X=y CONFIG_LPWAN_SX127X_FSKOOK=y diff --git a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/scripts/Make.defs b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/scripts/Make.defs index cac88f8f7477a..b85e6a7196398 100644 --- a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/scripts/Make.defs +++ b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/xtensa/esp32/ttgo_lora_esp32/scripts/Make.defs +# boards/xtensa/esp32/lilygo_tbeam_lora_gps/scripts/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/Make.defs b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/Make.defs index 9c57b91e1063d..9852cc7b3f8a5 100644 --- a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/Make.defs +++ b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/xtensa/esp32/ttgo_lora_esp32/src/Make.defs +# boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/xtensa/esp32/ttgo_eink5_v2/Kconfig b/boards/xtensa/esp32/ttgo_eink5_v2/Kconfig index dc8ebd7910877..74ba92947ae2e 100644 --- a/boards/xtensa/esp32/ttgo_eink5_v2/Kconfig +++ b/boards/xtensa/esp32/ttgo_eink5_v2/Kconfig @@ -10,28 +10,24 @@ if PM config PM_ALARM_SEC int "PM_STANDBY delay (seconds)" default 15 - depends on PM ---help--- Number of seconds to wait in PM_STANDBY before going to PM_STANDBY mode. config PM_ALARM_NSEC int "PM_STANDBY delay (nanoseconds)" default 0 - depends on PM ---help--- Number of additional nanoseconds to wait in PM_STANDBY before going to PM_STANDBY mode. config PM_SLEEP_WAKEUP_SEC int "PM_SLEEP delay (seconds)" default 20 - depends on PM ---help--- Number of seconds to wait in PM_SLEEP. config PM_SLEEP_WAKEUP_NSEC int "PM_SLEEP delay (nanoseconds)" default 0 - depends on PM ---help--- Number of additional nanoseconds to wait in PM_SLEEP. diff --git a/boards/xtensa/esp32/ttgo_eink5_v2/configs/fb/defconfig b/boards/xtensa/esp32/ttgo_eink5_v2/configs/fb/defconfig index ba179a10f33bd..03db6a4de0145 100644 --- a/boards/xtensa/esp32/ttgo_eink5_v2/configs/fb/defconfig +++ b/boards/xtensa/esp32/ttgo_eink5_v2/configs/fb/defconfig @@ -28,6 +28,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LCD_PORTRAIT=y CONFIG_MM_REGIONS=3 diff --git a/boards/xtensa/esp32/ttgo_lora_esp32/configs/nsh/defconfig b/boards/xtensa/esp32/ttgo_lora_esp32/configs/nsh/defconfig index 96e26fb97ef0b..3eaf03bb20571 100644 --- a/boards/xtensa/esp32/ttgo_lora_esp32/configs/nsh/defconfig +++ b/boards/xtensa/esp32/ttgo_lora_esp32/configs/nsh/defconfig @@ -28,6 +28,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32/ttgo_lora_esp32/configs/sx127x/defconfig b/boards/xtensa/esp32/ttgo_lora_esp32/configs/sx127x/defconfig index 82f7817e3b580..2abbba71ddfd9 100644 --- a/boards/xtensa/esp32/ttgo_lora_esp32/configs/sx127x/defconfig +++ b/boards/xtensa/esp32/ttgo_lora_esp32/configs/sx127x/defconfig @@ -37,6 +37,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LPWAN_SX127X=y CONFIG_LPWAN_SX127X_FSKOOK=y diff --git a/boards/xtensa/esp32/ttgo_t_display_esp32/Kconfig b/boards/xtensa/esp32/ttgo_t_display_esp32/Kconfig index b9fcf41810a4b..5b8fd99e9b0ed 100644 --- a/boards/xtensa/esp32/ttgo_t_display_esp32/Kconfig +++ b/boards/xtensa/esp32/ttgo_t_display_esp32/Kconfig @@ -10,28 +10,24 @@ if PM config PM_ALARM_SEC int "PM_STANDBY delay (seconds)" default 15 - depends on PM ---help--- Number of seconds to wait in PM_STANDBY before going to PM_STANDBY mode. config PM_ALARM_NSEC int "PM_STANDBY delay (nanoseconds)" default 0 - depends on PM ---help--- Number of additional nanoseconds to wait in PM_STANDBY before going to PM_STANDBY mode. config PM_SLEEP_WAKEUP_SEC int "PM_SLEEP delay (seconds)" default 20 - depends on PM ---help--- Number of seconds to wait in PM_SLEEP. config PM_SLEEP_WAKEUP_NSEC int "PM_SLEEP delay (nanoseconds)" default 0 - depends on PM ---help--- Number of additional nanoseconds to wait in PM_SLEEP. diff --git a/boards/xtensa/esp32/ttgo_t_display_esp32/configs/lvgl_fb/defconfig b/boards/xtensa/esp32/ttgo_t_display_esp32/configs/lvgl_fb/defconfig index 0b28b8b2d5482..5e26376208868 100644 --- a/boards/xtensa/esp32/ttgo_t_display_esp32/configs/lvgl_fb/defconfig +++ b/boards/xtensa/esp32/ttgo_t_display_esp32/configs/lvgl_fb/defconfig @@ -34,6 +34,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LCD_FRAMEBUFFER=y @@ -42,12 +43,13 @@ CONFIG_LCD_ST7789_XOFFSET=53 CONFIG_LCD_ST7789_XRES=135 CONFIG_LCD_ST7789_YOFFSET=40 CONFIG_LCD_ST7789_YRES=240 -CONFIG_LV_MEM_CUSTOM=y -CONFIG_LV_PORT_USE_FBDEV=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y CONFIG_LV_USE_DEMO_WIDGETS=y CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/ttgo_t_display_esp32/configs/lvgl_lcd/defconfig b/boards/xtensa/esp32/ttgo_t_display_esp32/configs/lvgl_lcd/defconfig index ebf26510f62c1..62248a151753f 100644 --- a/boards/xtensa/esp32/ttgo_t_display_esp32/configs/lvgl_lcd/defconfig +++ b/boards/xtensa/esp32/ttgo_t_display_esp32/configs/lvgl_lcd/defconfig @@ -33,6 +33,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_LCD=y CONFIG_LCD_DEV=y @@ -41,14 +42,15 @@ CONFIG_LCD_ST7789_XOFFSET=53 CONFIG_LCD_ST7789_XRES=135 CONFIG_LCD_ST7789_YOFFSET=40 CONFIG_LCD_ST7789_YRES=240 -CONFIG_LV_COLOR_16_SWAP=y -CONFIG_LV_MEM_CUSTOM=y -CONFIG_LV_PORT_LCDDEV_DOUBLE_BUFFER=y -CONFIG_LV_PORT_USE_LCDDEV=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" +CONFIG_LV_NUTTX_LCD_DOUBLE_BUFFER=y +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y CONFIG_LV_USE_DEMO_WIDGETS=y CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_LCD=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/ttgo_t_display_esp32/configs/nsh/defconfig b/boards/xtensa/esp32/ttgo_t_display_esp32/configs/nsh/defconfig index 3bc6dde0f2252..5e34915fe29bd 100644 --- a/boards/xtensa/esp32/ttgo_t_display_esp32/configs/nsh/defconfig +++ b/boards/xtensa/esp32/ttgo_t_display_esp32/configs/nsh/defconfig @@ -25,6 +25,7 @@ CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32s2/common/include/esp32s2_board_rmt.h b/boards/xtensa/esp32s2/common/include/esp32s2_board_rmt.h index 1b4026f648562..6682746c9681e 100644 --- a/boards/xtensa/esp32s2/common/include/esp32s2_board_rmt.h +++ b/boards/xtensa/esp32s2/common/include/esp32s2_board_rmt.h @@ -56,10 +56,10 @@ extern "C" * Name: board_rmt_rxinitialize * * Description: - * Initialize the RMT peripheral and register a RX device. + * Initialize the RMT peripheral and register an RX device. * * Input Parameters: - * ch - the RMT's channel that will be used + * ch - The RMT's channel that will be used * pin - The pin used for the RX channel * * Returned Value: @@ -73,10 +73,10 @@ int board_rmt_rxinitialize(int ch, int pin); * Name: board_rmt_txinitialize * * Description: - * Initialize the RMT peripheral and register a TX device. + * Initialize the RMT peripheral and register an TX device. * * Input Parameters: - * ch - the RMT's channel that will be used + * ch - The RMT's channel that will be used * pin - The pin used for the TX channel * * Returned Value: diff --git a/boards/xtensa/esp32s2/common/src/esp32s2_board_rmt.c b/boards/xtensa/esp32s2/common/src/esp32s2_board_rmt.c index 2cdd10164be9a..243c710db6d49 100644 --- a/boards/xtensa/esp32s2/common/src/esp32s2_board_rmt.c +++ b/boards/xtensa/esp32s2/common/src/esp32s2_board_rmt.c @@ -74,10 +74,10 @@ * Name: board_rmt_rxinitialize * * Description: - * Initialize the RMT peripheral and register a RX device. + * Initialize the RMT peripheral and register an RX device. * * Input Parameters: - * ch - the RMT's channel that will be used + * ch - The RMT's channel that will be used * pin - The pin used for the RX channel * * Returned Value: @@ -105,10 +105,10 @@ int board_rmt_rxinitialize(int ch, int pin) * Name: board_rmt_txinitialize * * Description: - * Initialize the RMT peripheral and register a TX device. + * Initialize the RMT peripheral and register an TX device. * * Input Parameters: - * ch - the RMT's channel that will be used + * ch - The RMT's channel that will be used * pin - The pin used for the TX channel * * Returned Value: diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/lvgl_ili9341/defconfig b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/lvgl_ili9341/defconfig index 712471c80ebc8..ce81b39db946a 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/lvgl_ili9341/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/lvgl_ili9341/defconfig @@ -39,15 +39,15 @@ CONFIG_LCD=y CONFIG_LCD_DEV=y CONFIG_LCD_ILI9341=y CONFIG_LCD_ILI9341_IFACE0=y -CONFIG_LV_COLOR_16_SWAP=y -CONFIG_LV_DEMO_WIDGETS_SLIDESHOW=y -CONFIG_LV_MEM_CUSTOM=y -CONFIG_LV_PORT_LCDDEV_DOUBLE_BUFFER=y -CONFIG_LV_PORT_USE_LCDDEV=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" +CONFIG_LV_NUTTX_LCD_DOUBLE_BUFFER=y +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y CONFIG_LV_USE_DEMO_WIDGETS=y CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_LCD=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/lvgl_st7789/defconfig b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/lvgl_st7789/defconfig index 087adcaf79f51..d43ba68663d21 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/lvgl_st7789/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/lvgl_st7789/defconfig @@ -41,15 +41,15 @@ CONFIG_LCD=y CONFIG_LCD_DEV=y CONFIG_LCD_ST7789=y CONFIG_LCD_ST7789_FREQUENCY=10000000 -CONFIG_LV_COLOR_16_SWAP=y -CONFIG_LV_DEMO_WIDGETS_SLIDESHOW=y -CONFIG_LV_MEM_CUSTOM=y -CONFIG_LV_PORT_LCDDEV_DOUBLE_BUFFER=y -CONFIG_LV_PORT_USE_LCDDEV=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" +CONFIG_LV_NUTTX_LCD_DOUBLE_BUFFER=y +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y CONFIG_LV_USE_DEMO_WIDGETS=y CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_LCD=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y CONFIG_NSH_FILEIOSIZE=512 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/mcuboot_nsh/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/mcuboot_nsh/defconfig index 706fccf1b4ed4..ee78ad4e4569c 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/mcuboot_nsh/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/mcuboot_nsh/defconfig @@ -20,7 +20,6 @@ CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_ESP32S2_APP_FORMAT_MCUBOOT=y -CONFIG_ESP32S2_BOOTLOADER_BUILD_FROM_SOURCE=y CONFIG_ESP32S2_SPIFLASH=y CONFIG_ESP32S2_UART0=y CONFIG_FS_PROCFS=y diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs index dbcc0add214a5..f4386876f5493 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# boards/xtensa/esp32s2/esp32s2-devkitc/scripts/Make.defs +# boards/xtensa/esp32s2/esp32s2-saola-1/scripts/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2-saola-1.h b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2-saola-1.h index 768efbad6e15c..756a4bfcca14c 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2-saola-1.h +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2-saola-1.h @@ -61,7 +61,7 @@ # define RMT_OUTPUT_PIN 0 #else # define RMT_INPUT_PIN 2 -# define RMT_OUTPUT_PIN 4 +# define RMT_OUTPUT_PIN 18 #endif /**************************************************************************** diff --git a/boards/xtensa/esp32s3/common/include/esp32s3_board_adc.h b/boards/xtensa/esp32s3/common/include/esp32s3_board_adc.h new file mode 100644 index 0000000000000..ff0784285b556 --- /dev/null +++ b/boards/xtensa/esp32s3/common/include/esp32s3_board_adc.h @@ -0,0 +1,74 @@ +/**************************************************************************** + * boards/xtensa/esp32s3/common/include/esp32s3_board_adc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_XTENSA_ESP32S3_COMMON_INCLUDE_ESP32S3_BOARD_ADC_H +#define __BOARDS_XTENSA_ESP32S3_COMMON_INCLUDE_ESP32S3_BOARD_ADC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: board_adc_init + * + * Description: + * Configure the ADC driver. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S3_ADC +int board_adc_init(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_XTENSA_ESP32S3_COMMON_INCLUDE_ESP32S3_BOARD_ADC_H */ diff --git a/boards/xtensa/esp32s3/common/include/esp32s3_board_rmt.h b/boards/xtensa/esp32s3/common/include/esp32s3_board_rmt.h index 2acdc337688e8..0b9fbb618a7f6 100644 --- a/boards/xtensa/esp32s3/common/include/esp32s3_board_rmt.h +++ b/boards/xtensa/esp32s3/common/include/esp32s3_board_rmt.h @@ -56,10 +56,10 @@ extern "C" * Name: board_rmt_rxinitialize * * Description: - * Initialize the RMT peripheral and register a RX device. + * Initialize the RMT peripheral and register an RX device. * * Input Parameters: - * ch - the RMT's channel that will be used + * ch - The RMT's channel that will be used * pin - The pin used for the RX channel * * Returned Value: @@ -73,10 +73,10 @@ int board_rmt_rxinitialize(int ch, int pin); * Name: board_rmt_txinitialize * * Description: - * Initialize the RMT peripheral and register a TX device. + * Initialize the RMT peripheral and register an TX device. * * Input Parameters: - * ch - the RMT's channel that will be used + * ch - The RMT's channel that will be used * pin - The pin used for the TX channel * * Returned Value: diff --git a/boards/xtensa/esp32s3/common/include/esp32s3_board_spidev.h b/boards/xtensa/esp32s3/common/include/esp32s3_board_spidev.h new file mode 100644 index 0000000000000..4f33d11e2c7eb --- /dev/null +++ b/boards/xtensa/esp32s3/common/include/esp32s3_board_spidev.h @@ -0,0 +1,79 @@ +/**************************************************************************** + * boards/xtensa/esp32s3/common/include/esp32s3_board_spidev.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_XTENSA_ESP32S3_COMMON_INCLUDE_ESP32S3_BOARD_SPIDEV_H +#define __BOARDS_XTENSA_ESP32S3_COMMON_INCLUDE_ESP32S3_BOARD_SPIDEV_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_SPI_DRIVER +/**************************************************************************** + * Name: board_spidev_initialize + * + * Description: + * Initialize SPI driver and register the /dev/spi device. + * + * Input Parameters: + * port - The SPI bus number, used to build the device path as /dev/spiN + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int board_spidev_initialize(int port); + +#endif /* CONFIG_SPI_DRIVER */ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_XTENSA_ESP32S3_COMMON_INCLUDE_ESP32S3_BOARD_SPIDEV_H */ diff --git a/boards/xtensa/esp32s3/common/kernel/Makefile b/boards/xtensa/esp32s3/common/kernel/Makefile index 05a0355e19542..676bebe804f88 100644 --- a/boards/xtensa/esp32s3/common/kernel/Makefile +++ b/boards/xtensa/esp32s3/common/kernel/Makefile @@ -1,5 +1,5 @@ ############################################################################ -# boards/xtensa/esp32s3/esp32s3-devkit/kernel/Makefile +# boards/xtensa/esp32s3/common/kernel/Makefile # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/boards/xtensa/esp32s3/common/scripts/flat_memory.ld b/boards/xtensa/esp32s3/common/scripts/flat_memory.ld index 0df435f6507d9..84a84d0e9c146 100644 --- a/boards/xtensa/esp32s3/common/scripts/flat_memory.ld +++ b/boards/xtensa/esp32s3/common/scripts/flat_memory.ld @@ -48,6 +48,8 @@ #ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT #define SRAM_IRAM_END 0x403ba000 +#elif defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) +#define SRAM_IRAM_END 0x403c0000 #else #define SRAM_IRAM_END 0x403cc700 #endif @@ -77,6 +79,8 @@ # define FLASH_SIZE 0x2000000 #endif +#define RESERVE_RTC_MEM 24 + MEMORY { #ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT @@ -92,6 +96,16 @@ MEMORY metadata (RX) : org = CONFIG_ESP32S3_APP_MCUBOOT_HEADER_SIZE, len = 0x20 ROM (RX) : org = ORIGIN(metadata) + LENGTH(metadata), len = FLASH_SIZE - ORIGIN(ROM) +#elif defined (CONFIG_ESPRESSIF_SIMPLE_BOOT) + /* The 0x20 offset is a convenience for the app binary image generation. + * Flash cache has 64KB pages. The .bin file which is flashed to the chip + * has a 0x18 byte file header, and each segment has a 0x08 byte segment + * header. Setting this offset makes it simple to meet the flash cache MMU's + * constraint that (paddr % 64KB == vaddr % 64KB). + */ + + ROM (RX) : org = 0x20, + len = FLASH_SIZE - ORIGIN(ROM) #endif /* Below values assume the flash cache is on, and have the blocks this @@ -109,12 +123,7 @@ MEMORY #ifdef CONFIG_ESP32S3_APP_FORMAT_MCUBOOT irom0_0_seg (RX) : org = 0x42000000, len = FLASH_SIZE #else - /* The 0x20 offset is a convenience for the app binary image generation. - * Flash cache has 64KB pages. The .bin file which is flashed to the chip - * has a 0x18 byte file header, and each segment has a 0x08 byte segment - * header. Setting this offset makes it simple to meet the flash cache MMU's - * constraint that (paddr % 64KB == vaddr % 64KB). - */ + /* (See ROM segment above for meaning of 0x20 offset.) */ irom0_0_seg (RX) : org = 0x42000020, len = FLASH_SIZE - 0x20 #endif @@ -144,23 +153,27 @@ MEMORY drom0_0_seg (R) : org = 0x3c000000 + ORIGIN(ROM), len = FLASH_SIZE - ORIGIN(ROM) #else - /* The 0x20 offset is a convenience for the app binary image generation. - * Flash cache has 64KB pages. The .bin file which is flashed to the chip - * has a 0x18 byte file header, and each segment has a 0x08 byte segment - * header. Setting this offset makes it simple to meet the flash cache MMU's - * constraint that (paddr % 64KB == vaddr % 64KB). - */ + /* (See ROM segment above for meaning of 0x20 offset.) */ drom0_0_seg (R) : org = 0x3c000020, len = FLASH_SIZE - 0x20 #endif /* RTC fast memory (executable). Persists over deep sleep. */ - rtc_iram_seg(RWX) : org = 0x600fe000, len = 0x2000 + rtc_iram_seg(RWX) : org = 0x600fe000, len = 0x2000 - RESERVE_RTC_MEM /* RTC fast memory (same block as above), viewed from data bus */ - rtc_data_seg(RW) : org = 0x600fe000, len = 0x2000 + rtc_data_seg(RW) : org = 0x600fe000, len = 0x2000 - RESERVE_RTC_MEM + + /* We reduced the size of rtc_iram_seg by RESERVE_RTC_MEM value. + It reserves the amount of RTC fast memory that we use for this memory segment. + This segment is intended for keeping: + - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files). + - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on). + The aim of this is to keep data that will not be moved around and have a fixed address. + */ + rtc_reserved_seg(RW) : org = 0x600fe000 + 0x2000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM /* RTC slow memory (data accessible). Persists over deep sleep. * Start of RTC slow memory is reserved for ULP co-processor code + data, diff --git a/boards/xtensa/esp32s3/common/scripts/kernel-space.ld b/boards/xtensa/esp32s3/common/scripts/kernel-space.ld index 12aaaf667b531..e08c2bca08d18 100644 --- a/boards/xtensa/esp32s3/common/scripts/kernel-space.ld +++ b/boards/xtensa/esp32s3/common/scripts/kernel-space.ld @@ -118,6 +118,8 @@ SECTIONS *libsched.a:irq_csection.*(.literal .text .literal.* .text.*) *libsched.a:irq_dispatch.*(.literal .text .literal.* .text.*) + *libc.a:*lib_instrument.*(.text .text.* .literal .literal.*) + *(.wifirxiram .wifirxiram.*) *(.wifi0iram .wifi0iram.*) *(.wifiorslpiram .wifiorslpiram.*) @@ -168,6 +170,8 @@ SECTIONS *libsched.a:irq_csection.*(.bss .bss.* COMMON) *libsched.a:irq_dispatch.*(.bss .bss.* COMMON) + *libc.a:*lib_instrument.*(.bss .bss.* COMMON) + . = ALIGN(8); _ebss = ABSOLUTE(.); } >KDRAM @@ -214,6 +218,8 @@ SECTIONS *libsched.a:irq_csection.*(.rodata .rodata.*) *libsched.a:irq_dispatch.*(.rodata .rodata.*) + *libc.a:*lib_instrument.*(.rodata .rodata.*) + . = ALIGN(4); _edata = ABSOLUTE(.); @@ -225,6 +231,8 @@ SECTIONS .flash.text : { _stext = .; + _instruction_reserved_start = ABSOLUTE(.); + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ *(.fini.literal) @@ -239,6 +247,7 @@ SECTIONS . += 16; + _instruction_reserved_end = ABSOLUTE(.); _etext = .; } >KIROM diff --git a/boards/xtensa/esp32s3/common/scripts/legacy_sections.ld b/boards/xtensa/esp32s3/common/scripts/legacy_sections.ld index ed4a6cbb34852..0b1626ed35604 100644 --- a/boards/xtensa/esp32s3/common/scripts/legacy_sections.ld +++ b/boards/xtensa/esp32s3/common/scripts/legacy_sections.ld @@ -87,6 +87,9 @@ SECTIONS *libarch.a:xtensa_modifyreg32.*(.literal .text .literal.* .text.*) *libarch.a:xtensa_testset.*(.literal .text .literal.* .text.*) + *libarch.a:*esp_rom_spiflash.*(.literal .text .literal.* .text.*) + *libarch.a:*esp_rom_cache_esp32s2_esp32s3.*(.literal .text .literal.* .text.*) + #ifdef CONFIG_ESP32S3_BLE *libc.a:sq_remlast.*(.literal .text .literal.* .text.*) #endif @@ -102,6 +105,8 @@ SECTIONS *libsched.a:sched_thistask.*(.literal .text .literal.* .text.*) *libsched.a:spinlock.*(.literal .text .literal.* .text.*) + *libc.a:*lib_instrument.*(.literal .text .literal.* .text.*) + #ifdef CONFIG_ESP32S3_SPEED_UP_ISR *libarch.a:xtensa_switchcontext.*(.literal.up_switch_context .text.up_switch_context) @@ -237,6 +242,8 @@ SECTIONS .flash.text : { _stext = .; + _instruction_reserved_start = ABSOLUTE(.); + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ *(.fini.literal) @@ -251,6 +258,7 @@ SECTIONS . += 16; + _instruction_reserved_end = ABSOLUTE(.); _etext = .; } >default_code_seg diff --git a/boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld b/boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld index fd1f8e92b5ca3..189ae150afb37 100644 --- a/boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld +++ b/boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld @@ -61,7 +61,7 @@ SECTIONS _image_drom_lma = LOADADDR(.flash.rodata); _image_drom_size = LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) - _image_drom_lma; - .flash.rodata : + .flash.rodata : ALIGN(4) { _rodata_reserved_start = .; @@ -69,8 +69,6 @@ SECTIONS *(EXCLUDE_FILE (esp32s3_start.*) .rodata) *(EXCLUDE_FILE (esp32s3_start.*) .rodata.*) - *(.rodata) - *(.rodata.*) #ifdef CONFIG_ESP32S3_WIRELESS *(.rodata_wlog_verbose.*) *(.rodata_wlog_debug.*) @@ -128,7 +126,7 @@ SECTIONS /* Send .iram0 code to iram */ - .iram0.vectors : + .iram0.vectors : ALIGN(4) { _iram_start = ABSOLUTE(.); @@ -168,7 +166,7 @@ SECTIONS *(.init) } >iram0_0_seg AT>ROM - .iram0.text : + .iram0.text : ALIGN(4) { /* Code marked as running out of IRAM */ @@ -185,6 +183,10 @@ SECTIONS *libarch.a:xtensa_irqdispatch.*(.literal .text .literal.* .text.*) *libarch.a:xtensa_modifyreg32.*(.literal .text .literal.* .text.*) *libarch.a:xtensa_testset.*(.literal .text .literal.* .text.*) + *libarch.a:*cache_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*) #ifdef CONFIG_ESP32S3_BLE *libc.a:sq_remlast.*(.literal .text .literal.* .text.*) @@ -299,7 +301,7 @@ SECTIONS . = ALIGN(4); } >dram0_0_seg - .dram0.data : + .dram0.data : ALIGN(4) { /* .data initialized on power-up in ROMed configurations. */ @@ -320,6 +322,12 @@ SECTIONS *libphy.a:(.rodata .rodata.*) *libarch.a:xtensa_context.*(.rodata .rodata.*) + *libarch.a:esp32s3_spiflash.*(.rodata .rodata.*) + *libarch.a:*cache_hal.*(.rodata .rodata.*) + *libarch.a:*uart_hal.*(.rodata .rodata.*) + *libarch.a:*mpu_hal.*(.rodata .rodata.*) + *libarch.a:*mmu_hal.*(.rodata .rodata.*) + #if defined(CONFIG_STACK_CANARIES) && \ (defined(CONFIG_ESP32S3_SPIFLASH) || \ defined(CONFIG_ESP32S3_SPIRAM)) @@ -393,6 +401,8 @@ SECTIONS .flash.text : ALIGN(0x00010000) { _stext = .; + _instruction_reserved_start = ABSOLUTE(.); + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ *(.fini.literal) @@ -407,6 +417,7 @@ SECTIONS . += 16; + _instruction_reserved_end = ABSOLUTE(.); _etext = .; } >irom0_0_seg AT>ROM diff --git a/boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld b/boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld new file mode 100644 index 0000000000000..a7c15d17ba340 --- /dev/null +++ b/boards/xtensa/esp32s3/common/scripts/simple_boot_sections.ld @@ -0,0 +1,572 @@ +/**************************************************************************** + * boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#include + +/* Default entry point: */ + +ENTRY(__start); + +_diram_i_start = 0x40378000; + +SECTIONS +{ + /* Send .iram0 code to iram */ + + .iram0.vectors : + { + _iram_start = ABSOLUTE(.); + + /* Vectors go to IRAM. */ + + _init_start = ABSOLUTE(.); + + /* Vectors according to builds/RF-2015.2-win32/esp108_v1_2_s5_512int_2/config.html */ + + . = 0x0; + KEEP (*(.window_vectors.text)); + . = 0x180; + KEEP (*(.xtensa_level2_vector.text)); + . = 0x1c0; + KEEP (*(.xtensa_level3_vector.text)); + . = 0x200; + KEEP (*(.xtensa_level4_vector.text)); + . = 0x240; + KEEP (*(.xtensa_level5_vector.text)); + . = 0x280; + KEEP (*(.debug_exception_vector.text)); + . = 0x2c0; + KEEP (*(.nmi_vector.text)); + . = 0x300; + KEEP (*(.kernel_exception_vector.text)); + . = 0x340; + KEEP (*(.user_exception_vector.text)); + . = 0x3c0; + KEEP (*(.double_exception_vector.text)); + . = 0x400; + *(.*_vector.literal) + + . = ALIGN(16); + + *(.entry.text) + *(.init.literal) + *(.init) + _init_end = ABSOLUTE(.); + } >iram0_0_seg AT>ROM + + .iram0.text : + { + /* Code marked as running out of IRAM */ + + *(.iram1 .iram1.*) + esp32s3_start.*(.literal .text .literal.* .text.*) + + *libarch.a:esp32s3_cpuindex.*(.literal .text .literal.* .text.*) + *libarch.a:esp32s3_irq.*(.literal .text .literal.* .text.*) + *libarch.a:esp32s3_user.*(.literal .text .literal.* .text.*) + *libarch.a:esp32s3_spiflash.*(.literal .text .literal.* .text.*) + *libarch.a:xtensa_assert.*(.literal .text .literal.* .text.*) + *libarch.a:xtensa_cpuint.*(.literal .text .literal.* .text.*) + *libarch.a:xtensa_cpupause.*(.literal .text .literal.* .text.*) + *libarch.a:xtensa_irqdispatch.*(.literal .text .literal.* .text.*) + *libarch.a:xtensa_modifyreg32.*(.literal .text .literal.* .text.*) + *libarch.a:xtensa_testset.*(.literal .text .literal.* .text.*) + +#ifdef CONFIG_ESP32S3_BLE + *libc.a:sq_remlast.*(.literal .text .literal.* .text.*) +#endif + + *libdrivers.a:syslog_flush.*(.literal .text .literal.* .text.*) + + *libsched.a:assert.*(.literal .text .literal.* .text.*) + *libsched.a:irq_csection.*(.literal .text .literal.* .text.*) + *libsched.a:irq_dispatch.*(.literal .text .literal.* .text.*) + *libsched.a:irq_spinlock.*(.literal .text .literal.* .text.*) + *libsched.a:sched_note.*(.literal .text .literal.* .text.*) + *libsched.a:sched_suspendscheduler.*(.literal .text .literal.* .text.*) + *libsched.a:sched_thistask.*(.literal .text .literal.* .text.*) + *libsched.a:spinlock.*(.literal .text .literal.* .text.*) + *libsched.a:*sched_get_stackinfo.*(.literal .text .literal.* .text.*) + +#ifdef CONFIG_ESP32S3_SPEED_UP_ISR + *libarch.a:xtensa_switchcontext.*(.literal.up_switch_context .text.up_switch_context) + + *libarch.a:esp32s3_timerisr.*(.literal.systimer_isr .text.systimer_isr) + *libarch.a:esp32s3_idle.*(.literal.up_idle .text.up_idle) + *libarch.a:esp32s3_dma.*(.literal.esp32s3_dma_load .text.esp32s3_dma_load \ + .literal.esp32s3_dma_enable .text.esp32s3_dma_enable) + + *libsched.a:sched_processtimer.*(.literal.nxsched_process_timer .text.nxsched_process_timer) + *libsched.a:clock_initialize.*(.literal.clock_timer .text.clock_timer) + *libsched.a:wd_start.*(.literal.wd_timer .text.wd_timer) + *libsched.a:sched_roundrobin.*(.literal.nxsched_process_roundrobin .text.nxsched_process_roundrobin) + *libsched.a:sched_reprioritizertr.*(.literal.nxsched_reprioritize_rtr .text.nxsched_reprioritize_rtr) + *libsched.a:sched_removereadytorun.*(.literal.nxsched_remove_readytorun .text.nxsched_remove_readytorun) + *libsched.a:sched_addreadytorun.*(.literal.nxsched_add_readytorun .text.nxsched_add_readytorun) + *libsched.a:sched_addprioritized.*(.literal.nxsched_add_prioritized .text.nxsched_add_prioritized) + *libsched.a:sched_mergepending.*(.literal.nxsched_merge_pending .text.nxsched_merge_pending) + *libsched.a:sched_resumescheduler.*(.literal.nxsched_resume_scheduler .text.nxsched_resume_scheduler) + + *libc.a:sq_remfirst.*(.literal.sq_remfirst .text.sq_remfirst) +#endif + + *libarch.a:esp32s3_spi_timing.*(.literal .text .literal.* .text.*) +#ifdef CONFIG_ESP32S3_SPIRAM_MODE_QUAD + *libarch.a:esp32s3_psram_quad.*(.literal .text .literal.* .text.*) +#endif +#ifdef CONFIG_ESP32S3_SPIRAM_MODE_OCT + *libarch.a:esp32s3_psram_octal.*(.literal .text .literal.* .text.*) +#endif +#if defined(CONFIG_STACK_CANARIES) && \ + (defined(CONFIG_ESP32S3_SPIFLASH) || \ + defined(CONFIG_ESP32S3_SPIRAM)) + *libc.a:lib_stackchk.*(.literal .text .literal.* .text.*) +#endif + + *libarch.a:*brownout_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*cpu.*(.text .text.* .literal .literal.*) + *libarch.a:*gpio_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*periph_ctrl.*(.text .text.* .literal .literal.*) + *libarch.a:*clk.*(.text .text.* .literal .literal.*) + *libarch.a:*efuse_hal.*(.literal.is_eco0 .text.is_eco0) + *libarch.a:*esp_clk.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk_tree.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_clk_tree_common.*(.text .text.* .literal .literal.*) + *libarch.a:*clk_tree_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_init.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_clk.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_clk_init.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_sleep.*(.text .text.* .literal .literal.*) + *libarch.a:*rtc_time.*(.text .text.* .literal .literal.*) + *libarch.a:*regi2c_ctrl.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_hal_iram.*(.text .text.* .literal .literal.*) + *libarch.a:*wdt_hal_iram.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_banner_wrap.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_init.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_common.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_common_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_console.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_console_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_esp32s3.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_flash.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_flash_config_esp32s3.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_clock_init.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_clock_loader.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_efuse.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_panic.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_mem.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_random.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable) + *libarch.a:*bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable) + *libarch.a:*bootloader_random_esp32s3.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_image_format.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_soc.*(.text .text.* .literal .literal.*) + *libarch.a:*bootloader_sha.*(.text .text.* .literal .literal.*) + *libarch.a:*flash_encrypt.*(.text .text.* .literal .literal.*) + *libarch.a:*cache_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mpu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*efuse_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*uart_periph.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_uart.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_sys.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_spiflash.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_cache_esp32s2_esp32s3.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_rom_wdt.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_efuse_fields.*(.text .text.* .literal .literal.*) + *libarch.a:*esp_efuse_api_key.*(.text .text.* .literal .literal.*) + *libarch.a:*log.*(.text .text.* .literal .literal.*) + *libarch.a:*log_noos.*(.text .text.* .literal .literal.*) + *libarch.a:*cpu_region_protect.*(.text .text.* .literal .literal.*) + *libarch.a:*mspi_timing_tuning.*(.text .text.* .literal .literal.*) + + *libc.a:*lib_instrument.*(.text .text.* .literal .literal.*) + + *(.wifirxiram .wifirxiram.*) + *(.wifi0iram .wifi0iram.*) + *(.wifiorslpiram .wifiorslpiram.*) + *(.wifislpiram .wifislpiram.*) + *(.wifislprxiram .wifislprxiram.*) + *(.phyiram .phyiram.*) + + /* align + add 16B for CPU dummy speculative instr. fetch */ + + . = ALIGN(4) + 16; + + _iram_text = ABSOLUTE(.); + } >iram0_0_seg AT > ROM + + .dram0.dummy (NOLOAD) : + { + /* This section is required to skip .iram0.text area because iram0_0_seg + * and dram0_0_seg reflect the same address space on different buses. + */ + + . = ORIGIN(dram0_0_seg) + MAX(_iram_end, _diram_i_start) - _diram_i_start; + } >dram0_0_seg + + /* Shared RAM */ + + .dram0.bss (NOLOAD) : + { + /* .bss initialized on power-up */ + + . = ALIGN(8); + _bss_start = ABSOLUTE(.); + _sbss = ABSOLUTE(.); + + *(.bss .bss.*) + *(COMMON) + *(.dynsbss) + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + *(.dynbss) + *(.share.mem) + *(.gnu.linkonce.b.*) + + . = ALIGN(8); + _ebss = ABSOLUTE(.); + _bss_end = ABSOLUTE(.); + } >dram0_0_seg + + .noinit (NOLOAD) : + { + /* This section contains data that is not initialized during load, + * or during the application's initialization sequence. + */ + + . = ALIGN(4); + + *(.noinit .noinit.*) + + . = ALIGN(4); + } >dram0_0_seg + + .dram0.data : + { + /* .data initialized on power-up in ROMed configurations. */ + . = ALIGN (16); + _data_start = ABSOLUTE(.); + _sdata = ABSOLUTE(.); + KEEP (*(.data)) + KEEP (*(.data.*)) + KEEP (*(.gnu.linkonce.d.*)) + KEEP (*(.data1)) + KEEP (*(.sdata)) + KEEP (*(.sdata.*)) + KEEP (*(.gnu.linkonce.s.*)) + KEEP (*(.sdata2)) + KEEP (*(.sdata2.*)) + KEEP (*(.gnu.linkonce.s2.*)) + KEEP (*(.jcr)) + *(.dram1 .dram1.*) + esp32s3_start.*(.rodata .rodata.*) + + *libphy.a:(.rodata .rodata.*) + *libarch.a:xtensa_context.*(.rodata .rodata.*) +#if defined(CONFIG_STACK_CANARIES) && \ + (defined(CONFIG_ESP32S3_SPIFLASH) || \ + defined(CONFIG_ESP32S3_SPIRAM)) + *libc.a:lib_stackchk.*(.rodata .rodata.*) +#endif + + *libsched.a:*sched_get_stackinfo.*(.rodata .rodata.*) + *libarch.a:esp32s3_spiflash.*(.rodata .rodata.*) + *libarch.a:*brownout.*(.rodata .rodata.*) + *libarch.a:*cpu.*(.rodata .rodata.*) + *libarch.a:*gpio_hal.*(.rodata .rodata.*) + *libarch.a:*periph_ctrl.*(.rodata .rodata.*) + *libarch.a:*clk.*(.rodata .rodata.*) + *libarch.a:*esp_clk.*(.rodata .rodata.*) + *libarch.a:*esp_clk_tree.*(.rodata .rodata.*) + *libarch.a:*esp_clk_tree_common.*(.rodata .rodata.*) + *libarch.a:*clk_tree_hal.*(.rodata .rodata.*) + *libarch.a:*rtc_init.*(.rodata .rodata.*) + *libarch.a:*rtc_clk.*(.rodata .rodata.*) + *libarch.a:*rtc_clk_init.*(.rodata .rodata.*) + *libarch.a:*rtc_sleep.*(.rodata .rodata.*) + *libarch.a:*rtc_time.*(.rodata .rodata.*) + *libarch.a:*regi2c_ctrl.*(.rodata .rodata.*) + *libarch.a:*uart_hal_iram.*(.rodata .rodata.*) + *libarch.a:*wdt_hal_iram.*(.rodata .rodata.*) + *libarch.a:*bootloader_banner_wrap.*(.rodata .rodata.*) + *libarch.a:*bootloader_init.*(.rodata .rodata.*) + *libarch.a:*bootloader_common.*(.rodata .rodata.*) + *libarch.a:*bootloader_common_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_console.*(.rodata .rodata.*) + *libarch.a:*bootloader_console_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_esp32s3.*(.rodata .rodata.*) + *libarch.a:*bootloader_flash.*(.rodata .rodata.*) + *libarch.a:*bootloader_flash_config_esp32s3.*(.rodata .rodata.*) + *libarch.a:*bootloader_clock_init.*(.rodata .rodata.*) + *libarch.a:*bootloader_clock_loader.*(.rodata .rodata.*) + *libarch.a:*bootloader_efuse.*(.rodata .rodata.*) + *libarch.a:*bootloader_panic.*(.rodata .rodata.*) + *libarch.a:*bootloader_mem.*(.rodata .rodata.*) + *libarch.a:*bootloader_random.*(.rodata .rodata.*) + *libarch.a:*bootloader_random_esp32s3.*(.rodata .rodata.*) + *libarch.a:*esp_image_format.*(.rodata .rodata.*) + *libarch.a:*bootloader_soc.*(.rodata .rodata.*) + *libarch.a:*bootloader_sha.*(.rodata .rodata.*) + *libarch.a:*flash_encrypt.*(.rodata .rodata.*) + *libarch.a:*cache_hal.*(.rodata .rodata.*) + *libarch.a:*uart_hal.*(.rodata .rodata.*) + *libarch.a:*mpu_hal.*(.rodata .rodata.*) + *libarch.a:*mmu_hal.*(.rodata .rodata.*) + *libarch.a:*uart_periph.*(.rodata .rodata.*) + *libarch.a:*esp_rom_uart.*(.rodata .rodata.*) + *libarch.a:*esp_rom_sys.*(.rodata .rodata.*) + *libarch.a:*esp_rom_spiflash.*(.rodata .rodata.*) + *libarch.a:*esp_rom_cache_esp32s2_esp32s3.*(.rodata .rodata.*) + *libarch.a:*esp_rom_wdt.*(.rodata .rodata.*) + *libarch.a:*esp_efuse_fields.*(.rodata .rodata.*) + *libarch.a:*esp_efuse_api_key.*(.rodata .rodata.*) + *libarch.a:*log.*(.rodata .rodata.*) + *libarch.a:*log_noos.*(.rodata .rodata.*) + *libarch.a:*cpu_region_protect.*(.rodata .rodata.*) + *libarch.a:*mspi_timing_tuning.*(.rodata .rodata.*) +#ifdef CONFIG_ESP32S3_SPIRAM_MODE_QUAD + *libarch.a:esp32s3_psram_quad.*(.rodata .rodata.*) +#endif +#ifdef CONFIG_ESP32S3_SPIRAM_MODE_OCT + *libarch.a:esp32s3_psram_octal.*(.rodata .rodata.*) +#endif + + . = ALIGN(4); + _edata = ABSOLUTE(.); + _data_end = ABSOLUTE(.); + + /* Heap starts at the end of .data */ + + _sheap = ABSOLUTE(.); + } >dram0_0_seg AT>ROM + + _image_drom_vma = ADDR(.flash.rodata); + _image_drom_lma = LOADADDR(.flash.rodata); + _image_drom_size = LOADADDR(.flash.rodata) + SIZEOF(.flash.rodata) - _image_drom_lma; + + /* The alignment of the ".flash.rodata" output section is forced to + * 0x00010000 (64KB) to ensure that it will be allocated at the beginning + * of the next available Flash block. + * This is required to meet the following constraint from the external + * flash MMU: + * VMA % 64KB == LMA % 64KB + * i.e. the lower 16 bits of both the virtual address (address seen by the + * CPU) and the load address (physical address of the external flash) must + * be equal. + */ + + .flash.rodata_dummy (NOLOAD) : + { + . = ALIGN(0x10000); + } > ROM + + .flash.rodata : + { + _rodata_reserved_start = ABSOLUTE(.); + + _srodata = ABSOLUTE(.); + *(EXCLUDE_FILE (esp32s3_start.*) .rodata) + *(EXCLUDE_FILE (esp32s3_start.*) .rodata.*) + + *(.rodata) + *(.rodata.*) +#ifdef CONFIG_ESP32S3_WIRELESS + *(.rodata_wlog_verbose.*) + *(.rodata_wlog_debug.*) + *(.rodata_wlog_info.*) + *(.rodata_wlog_warning.*) + *(.rodata_wlog_error.*) +#endif + *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.gnu.linkonce.r.*) + *(.rodata1) + __XT_EXCEPTION_TABLE_ = ABSOLUTE(.); + *(.xt_except_table) + *(.gcc_except_table) + *(.gcc_except_table.*) + *(.gnu.linkonce.e.*) + *(.gnu.version_r) + *(.eh_frame) + + . = ALIGN(4); + + /* C++ constructor and destructor tables, properly ordered: */ + + _sinit = ABSOLUTE(.); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + _einit = ABSOLUTE(.); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + + /* C++ exception handlers table: */ + + __XT_EXCEPTION_DESCS_ = ABSOLUTE(.); + *(.xt_except_desc) + *(.gnu.linkonce.h.*) + __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); + *(.xt_except_desc_end) + *(.dynamic) + *(.gnu.version_d) + _erodata = ABSOLUTE(.); + + /* Literals are also RO data. */ + + _lit4_start = ABSOLUTE(.); + *(*.lit4) + *(.lit4.*) + *(.gnu.linkonce.lit4.*) + _lit4_end = ABSOLUTE(.); + . = ALIGN(4); + } >drom0_0_seg AT>ROM + + .flash.rodata_noload (NOLOAD) : + { + /* + This is a symbol marking the flash.rodata end, this can be + used for mmu driver to maintain virtual address + We don't need to include the noload rodata in this section + */ + _rodata_reserved_end = ABSOLUTE(.); + . = ALIGN (4); + mapping[rodata_noload] + } >drom0_0_seg + + _image_irom_vma = ADDR(.flash.text); + _image_irom_lma = LOADADDR(.flash.text); + _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_lma; + + .flash.text_dummy (NOLOAD) : + { + . += SIZEOF(.flash.rodata); + . = ALIGN(0x10000); + } >default_code_seg AT> ROM + + .flash.text : + { + _stext = .; + _instruction_reserved_start = ABSOLUTE(.); + + *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) + *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */ + *(.fini.literal) + *(.fini) + *(.gnu.version) + + /* CPU will try to prefetch up to 16 bytes of instructions. + * This means that any configuration (e.g. MMU, PMS) must allow + * safe access to up to 16 bytes after the last real instruction, add + * dummy bytes to ensure this + */ + + . += 16; + + _instruction_reserved_end = ABSOLUTE(.); + _etext = .; + } >irom0_0_seg AT>ROM + + /* Marks the end of IRAM code segment */ + + .iram0.text_end (NOLOAD) : + { + /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and + * 256B alignment for PMS split lines. + */ + + . += 16; + . = ALIGN(256); + _iram_end = ABSOLUTE(.); + } >iram0_0_seg + + .iram0.data : + { + . = ALIGN(4); + + *(.iram.data) + *(.iram.data.*) + } >iram0_0_seg + + .iram0.bss (NOLOAD) : + { + . = ALIGN(4); + + *(.iram.bss) + *(.iram.bss.*) + + . = ALIGN(4); + _iram_end = ABSOLUTE(.); + } >iram0_0_seg + + .rtc.text : + { + . = ALIGN(4); + *(.rtc.literal .rtc.text) + } >rtc_iram_seg AT>ROM + + /* RTC BSS section. */ + + .rtc.bss (NOLOAD) : + { + *(.rtc.bss) + } >rtc_slow_seg + + .rtc.data : + { + . = ALIGN(4); + *(.rtc.data) + *(.rtc.data.*) + *(.rtc.rodata) + *(.rtc.rodata.*) + + /* Whatever is left from the RTC memory is used as a special heap. */ + + . = ALIGN (4); + _srtcheap = ABSOLUTE(.); + } >rtc_slow_seg + + /* + * This section holds RTC data that should have fixed addresses. + * The data are not initialized at power-up and are retained during deep sleep. + */ + .rtc_reserved (NOLOAD): + { + . = ALIGN(4); + _rtc_reserved_start = ABSOLUTE(.); + /* New data can only be added here to ensure existing data are not moved. + Because data have adhered to the end of the segment and code is relied on it. + >> put new data here << */ + + *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) + KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*)) + _rtc_reserved_end = ABSOLUTE(.); + } > rtc_reserved_seg + +} diff --git a/boards/xtensa/esp32s3/common/src/Make.defs b/boards/xtensa/esp32s3/common/src/Make.defs index 68c7f067e10da..67841238c39d4 100644 --- a/boards/xtensa/esp32s3/common/src/Make.defs +++ b/boards/xtensa/esp32s3/common/src/Make.defs @@ -32,6 +32,10 @@ ifeq ($(CONFIG_ESP32S3_SPIFLASH),y) CSRCS += esp32s3_board_spiflash.c endif +ifeq ($(CONFIG_SPI_DRIVER),y) + CSRCS += esp32s3_board_spidev.c +endif + ifeq ($(CONFIG_ESP32S3_WIFI),y) CSRCS += esp32s3_board_wlan.c endif @@ -56,6 +60,10 @@ ifeq ($(CONFIG_ESP32S3_OTG),y) CSRCS += esp32s3_board_usb.c endif +ifeq ($(CONFIG_ESP32S3_ADC),y) + CSRCS += esp32s3_board_adc.c +endif + ifeq ($(CONFIG_NET_LAN9250),y) CSRCS += esp32s3_lan9250.c endif diff --git a/boards/xtensa/esp32s3/common/src/esp32s3_board_adc.c b/boards/xtensa/esp32s3/common/src/esp32s3_board_adc.c new file mode 100644 index 0000000000000..5093eca274fb8 --- /dev/null +++ b/boards/xtensa/esp32s3/common/src/esp32s3_board_adc.c @@ -0,0 +1,192 @@ +/**************************************************************************** + * boards/xtensa/esp32s3/common/src/esp32s3_board_adc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +#include "esp32s3_adc.h" + +#include "esp32s3_board_adc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_adc_register + * + * Description: + * Register the ADC driver. + * + * Input Parameters: + * channel - ADC channel number. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +static int board_adc_register(int channel) +{ + int ret; + char devname[12]; + FAR struct adc_dev_s *adcdev; + + adcdev = kmm_malloc(sizeof(struct adc_dev_s)); + if (adcdev == NULL) + { + aerr("ERROR: Failed to allocate adc_dev_s instance\n"); + return -ENOMEM; + } + + memset(adcdev, 0, sizeof(struct adc_dev_s)); + esp32s3_adc_init(channel, adcdev); + snprintf(devname, 12, "/dev/adc%d", channel); + + /* Register the ADC driver at "/dev/adcx_x" */ + + ret = adc_register(devname, adcdev); + if (ret < 0) + { + kmm_free(adcdev); + syslog(LOG_ERR, "ERROR: adc_register %s failed: %d\n", devname, ret); + return ret; + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_adc_init + * + * Description: + * Configure the ADC driver. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int board_adc_init(void) +{ + int ret; + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL0 + ret = board_adc_register(ESP32S3_ADC1_CHANNEL0); + if (ret != OK) + { + return ret; + } +#endif + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL1 + ret = board_adc_register(ESP32S3_ADC1_CHANNEL1); + if (ret != OK) + { + return ret; + } +#endif + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL2 + ret = board_adc_register(ESP32S3_ADC1_CHANNEL2); + if (ret != OK) + { + return ret; + } +#endif + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL3 + ret = board_adc_register(ESP32S3_ADC1_CHANNEL3); + if (ret != OK) + { + return ret; + } +#endif + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL4 + ret = board_adc_register(ESP32S3_ADC1_CHANNEL4); + if (ret != OK) + { + return ret; + } +#endif + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL5 + ret = board_adc_register(ESP32S3_ADC1_CHANNEL5); + if (ret != OK) + { + return ret; + } +#endif + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL6 + ret = board_adc_register(ESP32S3_ADC1_CHANNEL6); + if (ret != OK) + { + return ret; + } +#endif + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL7 + ret = board_adc_register(ESP32S3_ADC1_CHANNEL7); + if (ret != OK) + { + return ret; + } +#endif + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL8 + ret = board_adc_register(ESP32S3_ADC1_CHANNEL8); + if (ret != OK) + { + return ret; + } +#endif + +#ifdef CONFIG_ESP32S3_ADC1_CHANNEL9 + ret = board_adc_register(ESP32S3_ADC1_CHANNEL9); + if (ret != OK) + { + return ret; + } +#endif + + return ret; +} diff --git a/boards/xtensa/esp32s3/common/src/esp32s3_board_rmt.c b/boards/xtensa/esp32s3/common/src/esp32s3_board_rmt.c index a3d178105ea0d..f42d2b33acd7f 100644 --- a/boards/xtensa/esp32s3/common/src/esp32s3_board_rmt.c +++ b/boards/xtensa/esp32s3/common/src/esp32s3_board_rmt.c @@ -74,10 +74,10 @@ * Name: board_rmt_rxinitialize * * Description: - * Initialize the RMT peripheral and register a RX device. + * Initialize the RMT peripheral and register an RX device. * * Input Parameters: - * ch - the RMT's channel that will be used + * ch - The RMT's channel that will be used * pin - The pin used for the RX channel * * Returned Value: @@ -105,10 +105,10 @@ int board_rmt_rxinitialize(int ch, int pin) * Name: board_rmt_txinitialize * * Description: - * Initialize the RMT peripheral and register a TX device. + * Initialize the RMT peripheral and register an TX device. * * Input Parameters: - * ch - the RMT's channel that will be used + * ch - The RMT's channel that will be used * pin - The pin used for the TX channel * * Returned Value: diff --git a/boards/xtensa/esp32s3/common/src/esp32s3_board_spidev.c b/boards/xtensa/esp32s3/common/src/esp32s3_board_spidev.c new file mode 100644 index 0000000000000..c5d391e9be4c9 --- /dev/null +++ b/boards/xtensa/esp32s3/common/src/esp32s3_board_spidev.c @@ -0,0 +1,79 @@ +/**************************************************************************** + * boards/xtensa/esp32s3/common/src/esp32s3_board_spidev.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include "esp32s3_spi.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_spidev_initialize + * + * Description: + * Initialize SPI driver and register the /dev/spi device. + * + * Input Parameters: + * port - The SPI bus number, used to build the device path as /dev/spiN + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int board_spidev_initialize(int port) +{ + int ret; + struct spi_dev_s *spi; + + spiinfo("Initializing /dev/spi%d...\n", port); + + /* Initialize SPI device */ + + spi = esp32s3_spibus_initialize(port); + if (spi == NULL) + { + spierr("Failed to initialize SPI%d.\n", port); + return -ENODEV; + } + + ret = spi_register(spi, port); + if (ret < 0) + { + spierr("Failed to register /dev/spi%d: %d\n", port, ret); + + esp32s3_spibus_uninitialize(spi); + } + + return ret; +} diff --git a/boards/xtensa/esp32s3/common/src/esp32s3_lan9250.c b/boards/xtensa/esp32s3/common/src/esp32s3_lan9250.c index fe7120077619a..707e712a58e8e 100644 --- a/boards/xtensa/esp32s3/common/src/esp32s3_lan9250.c +++ b/boards/xtensa/esp32s3/common/src/esp32s3_lan9250.c @@ -35,14 +35,13 @@ #include #include "xtensa.h" +#include "esp32s3_efuse.h" #include "esp32s3_gpio.h" #ifdef CONFIG_LAN9250_SPI #include "esp32s3_spi.h" #else #include "esp32s3_qspi.h" #endif -#include "hardware/esp32s3_efuse.h" -#include "hardware/esp32s3_gpio_sigmap.h" /**************************************************************************** * Pre-processor Definitions @@ -175,8 +174,8 @@ static void lan9250_getmac(const struct lan9250_lower_s *lower, uint8_t *mac) uint32_t regval[2]; uint8_t *data = (uint8_t *)regval; - regval[0] = getreg32(EFUSE_RD_MAC_SPI_SYS_0_REG); - regval[1] = getreg32(EFUSE_RD_MAC_SPI_SYS_1_REG); + regval[0] = esp32s3_efuse_read_reg(EFUSE_BLK1, 0); + regval[1] = esp32s3_efuse_read_reg(EFUSE_BLK1, 1); for (int i = 0; i < 6; i++) { diff --git a/boards/xtensa/esp32s3/esp32s3-box/Kconfig b/boards/xtensa/esp32s3/esp32s3-box/Kconfig index 9d021c1718067..b47e2effcc7b0 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/Kconfig +++ b/boards/xtensa/esp32s3/esp32s3-box/Kconfig @@ -27,6 +27,10 @@ config ESP32S3_STORAGE_MTD_OFFSET config ESP32S3_STORAGE_MTD_SIZE hex "Storage MTD size in SPI Flash" default 0x100000 + range 0x0 0x400000 if ESP32S3_FLASH_4M + range 0x0 0x800000 if ESP32S3_FLASH_8M + range 0x0 0x1000000 if ESP32S3_FLASH_16M + range 0x0 0x2000000 if ESP32S3_FLASH_32M depends on ESP32S3_MTD ---help--- MTD size in SPI Flash. diff --git a/boards/xtensa/esp32s3/esp32s3-box/configs/lvgl-3/defconfig b/boards/xtensa/esp32s3/esp32s3-box/configs/lvgl-3/defconfig index f2d9550a5429c..1aef75f0f70f6 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/configs/lvgl-3/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-box/configs/lvgl-3/defconfig @@ -53,18 +53,16 @@ CONFIG_INTELHEX_BINARY=y CONFIG_LCD_ILI9341=y CONFIG_LCD_ILI9341_IFACE0=y CONFIG_LCD_RPORTRAIT=y -CONFIG_LV_COLOR_16_SWAP=y CONFIG_LV_FONT_MONTSERRAT_20=y -CONFIG_LV_MEMCPY_MEMSET_STD=y -CONFIG_LV_MEM_CUSTOM=y -CONFIG_LV_PORT_LCDDEV_DOUBLE_BUFFER=y -CONFIG_LV_PORT_LCDDEV_FULL_SCREEN_BUFFER=y -CONFIG_LV_PORT_USE_LCDDEV=y -CONFIG_LV_PORT_USE_TOUCHPAD=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" +CONFIG_LV_NUTTX_LCD_DOUBLE_BUFFER=y +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y CONFIG_LV_USE_DEMO_WIDGETS=y CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_LCD=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y CONFIG_MM_REGIONS=2 CONFIG_NDEBUG=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32s3/esp32s3-box/configs/lvgl/defconfig b/boards/xtensa/esp32s3/esp32s3-box/configs/lvgl/defconfig index 772f14f4b48de..eb0904d421356 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/configs/lvgl/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-box/configs/lvgl/defconfig @@ -56,18 +56,16 @@ CONFIG_LCD_ST7789_BGR=y CONFIG_LCD_ST7789_FREQUENCY=40000000 CONFIG_LCD_ST7789_XRES=320 CONFIG_LCD_ST7789_YRES=240 -CONFIG_LV_COLOR_16_SWAP=y CONFIG_LV_FONT_MONTSERRAT_20=y -CONFIG_LV_MEMCPY_MEMSET_STD=y -CONFIG_LV_MEM_CUSTOM=y -CONFIG_LV_PORT_LCDDEV_DOUBLE_BUFFER=y -CONFIG_LV_PORT_LCDDEV_FULL_SCREEN_BUFFER=y -CONFIG_LV_PORT_USE_LCDDEV=y -CONFIG_LV_PORT_USE_TOUCHPAD=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" +CONFIG_LV_NUTTX_LCD_DOUBLE_BUFFER=y +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y CONFIG_LV_USE_DEMO_WIDGETS=y CONFIG_LV_USE_LOG=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_LCD=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y CONFIG_MM_REGIONS=2 CONFIG_NDEBUG=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32s3/esp32s3-box/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-box/scripts/Make.defs index 1f4857cd1753a..9fb14d9885791 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/scripts/Make.defs +++ b/boards/xtensa/esp32s3/esp32s3-box/scripts/Make.defs @@ -38,6 +38,8 @@ else ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) + else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld) else ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) endif diff --git a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_st7789.c b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_st7789.c index ecdb50f964867..5c42132d224c3 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_st7789.c +++ b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_st7789.c @@ -1,5 +1,5 @@ /**************************************************************************** - * boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd.c + * boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_st7789.c * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/Kconfig b/boards/xtensa/esp32s3/esp32s3-devkit/Kconfig index d08044077b99c..59a4479022ccb 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/Kconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/Kconfig @@ -27,6 +27,10 @@ config ESP32S3_STORAGE_MTD_OFFSET config ESP32S3_STORAGE_MTD_SIZE hex "Storage MTD size in SPI Flash" default 0x100000 + range 0x0 0x400000 if ESP32S3_FLASH_4M + range 0x0 0x800000 if ESP32S3_FLASH_8M + range 0x0 0x1000000 if ESP32S3_FLASH_16M + range 0x0 0x2000000 if ESP32S3_FLASH_32M depends on ESP32S3_MTD ---help--- MTD size in SPI Flash. @@ -60,4 +64,32 @@ config ESP32S3_SPIFLASH_LITTLEFS endchoice # ESP32S3_SPIFLASH_FS +if PM + +config PM_ALARM_SEC + int "PM_STANDBY delay (seconds)" + default 15 + ---help--- + Number of seconds to wait in PM_STANDBY before going to PM_STANDBY mode. + +config PM_ALARM_NSEC + int "PM_STANDBY delay (nanoseconds)" + default 0 + ---help--- + Number of additional nanoseconds to wait in PM_STANDBY before going to PM_STANDBY mode. + +config PM_SLEEP_WAKEUP_SEC + int "PM_SLEEP delay (seconds)" + default 20 + ---help--- + Number of seconds to wait in PM_SLEEP. + +config PM_SLEEP_WAKEUP_NSEC + int "PM_SLEEP delay (nanoseconds)" + default 0 + ---help--- + Number of additional nanoseconds to wait in PM_SLEEP. + +endif # PM + endif # ARCH_BOARD_ESP32S3_DEVKIT diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/adc/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/adc/defconfig new file mode 100644 index 0000000000000..388a7fc6a5f12 --- /dev/null +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/adc/defconfig @@ -0,0 +1,53 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32s3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32S3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32s3" +CONFIG_ARCH_CHIP_ESP32S3=y +CONFIG_ARCH_CHIP_ESP32S3WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ESP32S3_ADC1_CHANNEL0=y +CONFIG_ESP32S3_ADC1_CHANNEL1=y +CONFIG_ESP32S3_ADC1_CHANNEL2=y +CONFIG_ESP32S3_ADC=y +CONFIG_ESP32S3_UART0=y +CONFIG_EXAMPLES_ADC=y +CONFIG_EXAMPLES_ADC_SWTRIG=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSLOG_BUFFER=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/eth_lan9250/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/eth_lan9250/defconfig index 798c4c7d4e625..53e3bad04dcf5 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/eth_lan9250/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/eth_lan9250/defconfig @@ -25,6 +25,7 @@ CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_DEFAULT_TASK_STACKSIZE=4096 +CONFIG_ESP32S3_EFUSE=y CONFIG_ESP32S3_GPIO_IRQ=y CONFIG_ESP32S3_SPI2=y CONFIG_ESP32S3_SPI_SWCS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/mcuboot_nsh/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/mcuboot_nsh/defconfig index 5dff764aa8b7e..da2a46922336e 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/mcuboot_nsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/mcuboot_nsh/defconfig @@ -22,7 +22,6 @@ CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_ESP32S3_APP_FORMAT_MCUBOOT=y -CONFIG_ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE=y CONFIG_ESP32S3_SPIFLASH=y CONFIG_ESP32S3_UART0=y CONFIG_FS_PROCFS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/pm/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/pm/defconfig new file mode 100644 index 0000000000000..4db0b72d6833d --- /dev/null +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/pm/defconfig @@ -0,0 +1,52 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32s3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32S3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32s3" +CONFIG_ARCH_CHIP_ESP32S3=y +CONFIG_ARCH_CHIP_ESP32S3WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ESP32S3_UART0=y +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PM=y +CONFIG_PM_GOVERNOR_EXPLICIT_RELAX=-1 +CONFIG_PM_GOVERNOR_GREEDY=y +CONFIG_PM_PROCFS=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSLOG_BUFFER=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/pwm/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/pwm/defconfig index 1421e4de0dcf6..e2719f2ff674e 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/pwm/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/pwm/defconfig @@ -20,8 +20,6 @@ CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y -CONFIG_DEBUG_FULLOPT=y -CONFIG_DEBUG_SYMBOLS=y CONFIG_ESP32S3_LEDC=y CONFIG_ESP32S3_LEDC_TIM0=y CONFIG_ESP32S3_LEDC_TIM1=y @@ -29,6 +27,8 @@ CONFIG_ESP32S3_LEDC_TIM2=y CONFIG_ESP32S3_LEDC_TIM3=y CONFIG_ESP32S3_UART0=y CONFIG_EXAMPLES_PWM=y +CONFIG_EXAMPLES_PWM_CHANNEL1=0 +CONFIG_EXAMPLES_PWM_CHANNEL2=1 CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y @@ -41,6 +41,8 @@ CONFIG_NSH_FILEIOSIZE=512 CONFIG_NSH_LINELEN=64 CONFIG_NSH_READLINE=y CONFIG_PREALLOC_TIMERS=4 +CONFIG_PWM_MULTICHAN=y +CONFIG_PWM_NCHANNELS=2 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/rmt/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/rmt/defconfig index 20eebbea88e2e..0847742af4085 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/rmt/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/rmt/defconfig @@ -26,6 +26,7 @@ CONFIG_ESP32S3_UART0=y CONFIG_ESP_RMT=y CONFIG_EXAMPLES_RMTCHAR=y CONFIG_EXAMPLES_RMTCHAR_RX=y +CONFIG_EXAMPLES_RMTCHAR_RX_DEVPATH="/dev/rmt4" CONFIG_EXAMPLES_RMTCHAR_TX=y CONFIG_EXAMPLES_WS2812=y CONFIG_FS_PROCFS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/spi/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/spi/defconfig new file mode 100644 index 0000000000000..9b4462a2a2052 --- /dev/null +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/spi/defconfig @@ -0,0 +1,49 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32s3-devkit" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32S3_DEVKIT=y +CONFIG_ARCH_CHIP="esp32s3" +CONFIG_ARCH_CHIP_ESP32S3=y +CONFIG_ARCH_CHIP_ESP32S3WROOM1=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ESP32S3_SPI2=y +CONFIG_ESP32S3_SPI3=y +CONFIG_ESP32S3_UART0=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_WAITPID=y +CONFIG_SPITOOL_MINBUS=2 +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSLOG_BUFFER=y +CONFIG_SYSTEM_NSH=y +CONFIG_SYSTEM_SPITOOL=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/sta_softap/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/sta_softap/defconfig index b34e2671e97cb..1bfcec92d5be7 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/sta_softap/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/sta_softap/defconfig @@ -72,8 +72,9 @@ CONFIG_RR_INTERVAL=200 CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SIG_DEFAULT=y +CONFIG_SMP=y +CONFIG_SMP_NCPUS=2 CONFIG_SPIFFS_NAME_MAX=128 -CONFIG_SPINLOCK=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 CONFIG_START_YEAR=2011 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/toywasm/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/toywasm/defconfig index c456b6fe66858..7c467ccac6cd1 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/toywasm/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/toywasm/defconfig @@ -15,7 +15,7 @@ CONFIG_ARCH_BOARD_COMMON=y CONFIG_ARCH_BOARD_ESP32S3_DEVKIT=y CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y -CONFIG_ARCH_CHIP_ESP32S3WROOM2=y +CONFIG_ARCH_CHIP_ESP32S3WROOM2_32M=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y @@ -28,7 +28,6 @@ CONFIG_ESP32S3_RT_TIMER_TASK_STACK_SIZE=4096 CONFIG_ESP32S3_SPIFLASH=y CONFIG_ESP32S3_SPIRAM=y CONFIG_ESP32S3_SPIRAM_MODE_OCT=y -CONFIG_ESP32S3_SPI_FLASH_USE_32BIT_ADDRESS=y CONFIG_ESP32S3_STORAGE_MTD_SIZE=0x1e80000 CONFIG_ESP32S3_UART0=y CONFIG_ESP32S3_WIFI=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs index 5bca3415a06d5..9d7ea3f173e11 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs +++ b/boards/xtensa/esp32s3/esp32s3-devkit/scripts/Make.defs @@ -38,6 +38,8 @@ else ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) + else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld) else ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) endif diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c index bdeca8b1af772..408cd913d6e53 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c +++ b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c @@ -100,6 +100,19 @@ # include "esp32s3_board_rmt.h" #endif +#ifdef CONFIG_ESP32S3_SPI +#include "esp32s3_spi.h" +#include "esp32s3_board_spidev.h" +#endif + +#ifdef CONFIG_ESP32S3_AES_ACCELERATOR +# include "esp32s3_aes.h" +#endif + +#ifdef CONFIG_ESP32S3_ADC +#include "esp32s3_board_adc.h" +#endif + #include "esp32s3-devkit.h" /**************************************************************************** @@ -138,6 +151,24 @@ int esp32s3_bringup(void) } #endif +#if defined(CONFIG_ESP32S3_SPI) && defined(CONFIG_SPI_DRIVER) + #ifdef CONFIG_ESP32S3_SPI2 + ret = board_spidev_initialize(ESP32S3_SPI2); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to init spidev 2: %d\n", ret); + } + #endif + + #ifdef CONFIG_ESP32S3_SPI3 + ret = board_spidev_initialize(ESP32S3_SPI3); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to init spidev 3: %d\n", ret); + } + #endif +#endif + #if defined(CONFIG_ESP32S3_EFUSE) ret = esp32s3_efuse_initialize("/dev/efuse"); if (ret < 0) @@ -415,6 +446,30 @@ int esp32s3_bringup(void) } #endif +#ifdef CONFIG_ESP32S3_AES_ACCELERATOR + ret = esp32s3_aes_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize AES: %d\n", ret); + } +#ifdef CONFIG_ESP32S3_AES_ACCELERATOR_TEST + else + { + esp32s3_aes_test(); + } +#endif +#endif + +#ifdef CONFIG_ESP32S3_ADC + /* Configure ADC */ + + ret = board_adc_init(); + if (ret) + { + syslog(LOG_ERR, "ERROR: board_adc_init() failed: %d\n", ret); + } +#endif + /* If we got here then perhaps not all initialization was successful, but * at least enough succeeded to bring-up NSH with perhaps reduced * capabilities. diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_ledc.c b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_ledc.c index 04ab0439120ec..deb6728dfd083 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_ledc.c +++ b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_ledc.c @@ -33,7 +33,6 @@ #include -#include "chip.h" #include "esp32s3_ledc.h" /**************************************************************************** diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_twai.c b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_twai.c index 998a49c2e228c..d6b98e28efc19 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_twai.c +++ b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_twai.c @@ -30,8 +30,6 @@ #include #include -#include "chip.h" - #include "esp32s3_twai.h" #include "esp32s3-devkit.h" diff --git a/boards/xtensa/esp32s3/esp32s3-eye/Kconfig b/boards/xtensa/esp32s3/esp32s3-eye/Kconfig index 51df4a13d509f..175d4960b8b76 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/Kconfig +++ b/boards/xtensa/esp32s3/esp32s3-eye/Kconfig @@ -15,6 +15,10 @@ config ESP32S3_STORAGE_MTD_OFFSET config ESP32S3_STORAGE_MTD_SIZE hex "Storage MTD size in SPI Flash" default 0x100000 + range 0x0 0x400000 if ESP32S3_FLASH_4M + range 0x0 0x800000 if ESP32S3_FLASH_8M + range 0x0 0x1000000 if ESP32S3_FLASH_16M + range 0x0 0x2000000 if ESP32S3_FLASH_32M depends on ESP32S3_MTD ---help--- MTD size in SPI Flash. diff --git a/boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs index 001d639323c96..48aebb5325366 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs +++ b/boards/xtensa/esp32s3/esp32s3-eye/scripts/Make.defs @@ -36,7 +36,13 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld) else ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) - ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) + ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) + else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld) + else + ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) + endif endif ifneq ($(CONFIG_DEBUG_NOOPT),y) diff --git a/boards/xtensa/esp32s3/esp32s3-lcd-ev/Kconfig b/boards/xtensa/esp32s3/esp32s3-lcd-ev/Kconfig index 3d26b68551054..bcfaffaf9ca62 100644 --- a/boards/xtensa/esp32s3/esp32s3-lcd-ev/Kconfig +++ b/boards/xtensa/esp32s3/esp32s3-lcd-ev/Kconfig @@ -16,6 +16,10 @@ config ESP32S3_STORAGE_MTD_OFFSET config ESP32S3_STORAGE_MTD_SIZE hex "Storage MTD size in SPI Flash" default 0x100000 + range 0x0 0x400000 if ESP32S3_FLASH_4M + range 0x0 0x800000 if ESP32S3_FLASH_8M + range 0x0 0x1000000 if ESP32S3_FLASH_16M + range 0x0 0x2000000 if ESP32S3_FLASH_32M depends on ESP32S3_MTD ---help--- MTD size in SPI Flash. diff --git a/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/lvgl/defconfig b/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/lvgl/defconfig index d23d82c408f77..bc9536cc47620 100644 --- a/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/lvgl/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/lvgl/defconfig @@ -50,13 +50,12 @@ CONFIG_INPUT=y CONFIG_INPUT_FT5X06=y CONFIG_INTELHEX_BINARY=y CONFIG_LV_FONT_MONTSERRAT_20=y -CONFIG_LV_MEMCPY_MEMSET_STD=y -CONFIG_LV_MEM_CUSTOM=y -CONFIG_LV_PORT_USE_FBDEV=y -CONFIG_LV_PORT_USE_TOUCHPAD=y -CONFIG_LV_TICK_CUSTOM=y -CONFIG_LV_TICK_CUSTOM_INCLUDE="port/lv_port_tick.h" +CONFIG_LV_USE_CLIB_MALLOC=y +CONFIG_LV_USE_CLIB_SPRINTF=y +CONFIG_LV_USE_CLIB_STRING=y CONFIG_LV_USE_DEMO_WIDGETS=y +CONFIG_LV_USE_NUTTX=y +CONFIG_LV_USE_NUTTX_TOUCHSCREEN=y CONFIG_MM_REGIONS=2 CONFIG_NDEBUG=y CONFIG_NSH_ARCHINIT=y diff --git a/boards/xtensa/esp32s3/esp32s3-lcd-ev/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-lcd-ev/scripts/Make.defs index e35a09b999617..4ac4c5647167d 100644 --- a/boards/xtensa/esp32s3/esp32s3-lcd-ev/scripts/Make.defs +++ b/boards/xtensa/esp32s3/esp32s3-lcd-ev/scripts/Make.defs @@ -38,6 +38,8 @@ else ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) + else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld) else ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) endif diff --git a/boards/xtensa/esp32s3/esp32s3-meadow/Kconfig b/boards/xtensa/esp32s3/esp32s3-meadow/Kconfig index 3d5cc808aa16b..f4c4c26adef75 100644 --- a/boards/xtensa/esp32s3/esp32s3-meadow/Kconfig +++ b/boards/xtensa/esp32s3/esp32s3-meadow/Kconfig @@ -15,6 +15,10 @@ config ESP32S3_STORAGE_MTD_OFFSET config ESP32S3_STORAGE_MTD_SIZE hex "Storage MTD size in SPI Flash" default 0x100000 + range 0x0 0x400000 if ESP32S3_FLASH_4M + range 0x0 0x800000 if ESP32S3_FLASH_8M + range 0x0 0x1000000 if ESP32S3_FLASH_16M + range 0x0 0x2000000 if ESP32S3_FLASH_32M depends on ESP32S3_MTD ---help--- MTD size in SPI Flash. diff --git a/boards/xtensa/esp32s3/esp32s3-meadow/scripts/Make.defs b/boards/xtensa/esp32s3/esp32s3-meadow/scripts/Make.defs index 28863294b13d7..b3d65c6cb8988 100644 --- a/boards/xtensa/esp32s3/esp32s3-meadow/scripts/Make.defs +++ b/boards/xtensa/esp32s3/esp32s3-meadow/scripts/Make.defs @@ -36,7 +36,13 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) ARCHSCRIPT += $(call FINDSCRIPT,kernel-space.ld) else ARCHSCRIPT += $(call FINDSCRIPT,flat_memory.ld) - ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) + ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,mcuboot_sections.ld) + else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + ARCHSCRIPT += $(call FINDSCRIPT,simple_boot_sections.ld) + else + ARCHSCRIPT += $(call FINDSCRIPT,legacy_sections.ld) + endif endif ifneq ($(CONFIG_DEBUG_NOOPT),y) diff --git a/cmake/nuttx_add_application.cmake b/cmake/nuttx_add_application.cmake index 3cdda5f0ad932..fc12f28518b1d 100644 --- a/cmake/nuttx_add_application.cmake +++ b/cmake/nuttx_add_application.cmake @@ -206,12 +206,14 @@ function(nuttx_add_application) # using target_link_libraries for dependencies provides linking as well as # interface include and libraries foreach(dep ${DEPENDS}) - get_target_property(dep_type ${dep} TYPE) - if(${dep_type} STREQUAL "STATIC_LIBRARY") - target_link_libraries(${TARGET} PRIVATE ${dep}) - else() - add_dependencies(${TARGET} ${dep}) + nuttx_add_dependencies(TARGET ${TARGET} DEPENDS ${dep}) + if(TARGET ${dep}) + get_target_property(dep_type ${dep} TYPE) + if(${dep_type} STREQUAL "STATIC_LIBRARY") + target_link_libraries(${TARGET} PRIVATE ${dep}) + endif() endif() + endforeach() endif() endfunction() diff --git a/cmake/nuttx_add_library.cmake b/cmake/nuttx_add_library.cmake index 997ed228ed71e..8bd3d16fa6ae1 100644 --- a/cmake/nuttx_add_library.cmake +++ b/cmake/nuttx_add_library.cmake @@ -26,11 +26,18 @@ function(nuttx_add_library_internal target) # ensure nuttx_context is created before this add_dependencies(${target} nuttx_context) + # add specified search directories for CXX targets + target_include_directories( + ${target} + PRIVATE + $<$:$>> + ) + # add main include directories target_include_directories( ${target} SYSTEM - PUBLIC ${CMAKE_SOURCE_DIR}/include ${CMAKE_BINARY_DIR}/include - ${CMAKE_BINARY_DIR}/include_arch) + PRIVATE ${CMAKE_SOURCE_DIR}/include ${CMAKE_BINARY_DIR}/include + ${CMAKE_BINARY_DIR}/include_arch) # Set global compile options & definitions We use the "nuttx" target to hold # these properties so that libraries added after this property is set can read @@ -131,16 +138,19 @@ function(nuttx_add_kernel_library target) # Add kernel options & definitions See note above in # nuttx_add_library_internal() on syntax and nuttx target use - target_compile_options( - ${kernel_target} - PRIVATE $>) - target_compile_definitions( - ${kernel_target} - PRIVATE $>) - target_include_directories( - ${kernel_target} - PRIVATE - $>) + if(NOT ARGS_SPLIT OR NOT "${target}" STREQUAL "${kernel_target}") + target_compile_options( + ${kernel_target} + PRIVATE + $>) + target_compile_definitions( + ${kernel_target} + PRIVATE $>) + target_include_directories( + ${kernel_target} + PRIVATE + $>) + endif() if(NOT "${target}" STREQUAL "${kernel_target}") # The k${target} lib will have the same sources added to that ${target} lib. @@ -200,3 +210,22 @@ function(nuttx_library_import library_name library_path) set_target_properties(${library_name} PROPERTIES IMPORTED_LOCATION ${library_path}) endfunction() + +# nuttx_add_external_library +# +# the target library of add_library has been called in external CMakeLists.txt +# so that they can be added to the final link +# +# Usually used with Nuttx to include an external system that already supports +# CMake compilation +function(nuttx_add_external_library target) + cmake_parse_arguments(ARGS "" MODE "" ${ARGN}) + if(NOT ARGS_MODE) + set_property(GLOBAL APPEND PROPERTY NUTTX_SYSTEM_LIBRARIES ${target}) + elseif("${ARGS_MODE}" STREQUAL "APPS") + set_property(GLOBAL APPEND PROPERTY NUTTX_APPS_LIBRARIES ${target}) + elseif("${ARGS_MODE}" STREQUAL "KERNEL") + set_property(GLOBAL APPEND PROPERTY NUTTX_KERNEL_LIBRARIES ${target}) + endif() + nuttx_add_library_internal(${target}) +endfunction() diff --git a/cmake/nuttx_add_romfs.cmake b/cmake/nuttx_add_romfs.cmake index e844357a1bb6d..e600341accf28 100644 --- a/cmake/nuttx_add_romfs.cmake +++ b/cmake/nuttx_add_romfs.cmake @@ -59,11 +59,12 @@ function(nuttx_add_romfs) foreach(rcsrc ${RCSRCS}) get_filename_component(rcpath ${rcsrc} DIRECTORY) + separate_arguments(CMAKE_C_FLAG_ARGS NATIVE_COMMAND ${CMAKE_C_FLAGS}) add_custom_command( OUTPUT ${rcsrc} COMMAND ${CMAKE_COMMAND} -E make_directory ${rcpath} COMMAND - ${CMAKE_C_COMPILER} ${CMAKE_C_FLAGS} -E -P -x c + ${CMAKE_C_COMPILER} ${CMAKE_C_FLAG_ARGS} -E -P -x c -I${CMAKE_BINARY_DIR}/include ${CMAKE_CURRENT_SOURCE_DIR}/${rcsrc} > ${rcsrc} DEPENDS nuttx_context ${CMAKE_CURRENT_SOURCE_DIR}/${rcsrc}) diff --git a/cmake/nuttx_allsyms.cmake b/cmake/nuttx_allsyms.cmake new file mode 100644 index 0000000000000..44b1a8d3fc03d --- /dev/null +++ b/cmake/nuttx_allsyms.cmake @@ -0,0 +1,129 @@ +# ############################################################################## +# cmake/nuttx_allsyms.cmake +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +# ~~~ +# define_allsyms_link_target +# +# Description: +# Wrapper of cmake declaration of nuttx executable +# in order to implement ALLSYMS. +# +# When declaring the target to be `nuttx`, +# create an empty allsyms source file for it; +# When the target is declared as something else, +# the link behavior of the `nuttx` target is cloned +# and added to actually generate the allsyms file. +# +# Parameters: +# inter_target : declaration of target +# dep_target : targets which depends on +# allsyms_file : generated allsyms file name +# ~~~ +macro(define_allsyms_link_target inter_target dep_target allsyms_file) + if(${inter_target} STREQUAL nuttx) + # create an empty allsyms source file for `nuttx` + set(ALLSYMS_SOURCE ${CMAKE_BINARY_DIR}/allsyms_empty.c) + if(NOT EXISTS ${ALLSYMS_SOURCE}) + file(WRITE ${ALLSYMS_SOURCE} "#include \n\n") + file(APPEND ${ALLSYMS_SOURCE} "#include \n") + file(APPEND ${ALLSYMS_SOURCE} "extern int g_nallsyms;\n\n") + file(APPEND ${ALLSYMS_SOURCE} "extern struct symtab_s g_allsyms[];\n\n") + file(APPEND ${ALLSYMS_SOURCE} "int g_nallsyms = 1;\n\n") + file( + APPEND ${ALLSYMS_SOURCE} + "struct symtab_s g_allsyms[1] = {{ \"Unknown\", (FAR void *)0x00000000 }};\n\n" + ) + endif() + target_sources(nuttx PRIVATE ${ALLSYMS_SOURCE}) + set(ALLSYMS_INCDIR ${CMAKE_SOURCE_DIR}/include ${CMAKE_BINARY_DIR}/include + ${CMAKE_BINARY_DIR}/include_arch) + set_source_files_properties( + ${ALLSYMS_SOURCE} PROPERTIES INCLUDE_DIRECTORIES "${ALLSYMS_INCDIR}") + else() + # generate `g_allsyms` file + add_custom_command( + OUTPUT ${allsyms_file}.c POST_BUILD + COMMAND ${NUTTX_DIR}/tools/mkallsyms.py ${CMAKE_BINARY_DIR}/${dep_target} + ${allsyms_file}.c + DEPENDS ${dep_target} + WORKING_DIRECTORY ${CMAKE_BINARY_DIR} + COMMAND_EXPAND_LISTS) + + # relink target with allsysm.c which generated by the elf of the previous + # phase + add_executable( + ${inter_target} ${allsyms_file}.c + $,EXCLUDE,allsyms_empty>) + + # relink target and nuttx have exactly the same configuration + target_include_directories( + ${inter_target} SYSTEM + PUBLIC ${CMAKE_SOURCE_DIR}/include ${CMAKE_BINARY_DIR}/include + ${CMAKE_BINARY_DIR}/include_arch) + target_compile_definitions( + ${inter_target} PRIVATE $) + target_compile_options( + ${inter_target} + PRIVATE $) + target_link_options(${inter_target} PRIVATE + $) + target_link_libraries(${inter_target} + PRIVATE $) + endif() +endmacro() + +# nuttx link with allsysm +define_allsyms_link_target(nuttx NULL NULL) +# allsyms link phase 1 with generated allsyms source file +define_allsyms_link_target(allsyms_inter nuttx allsyms_first_link) +# allsyms link phase 2 since the table offset may changed +define_allsyms_link_target(allsyms_nuttx allsyms_inter allsyms_final_link) + +# finally use allsyms_nuttx to overwrite the already generated nuttx +add_custom_command( + TARGET allsyms_nuttx + POST_BUILD + COMMAND ${CMAKE_COMMAND} -E copy_if_different allsyms_nuttx nuttx DEPENDS + allsyms_nuttx + COMMENT "Overwrite nuttx with allsyms_nuttx") + +# regenerate binary outputs in different formats (.bin, .hex, etc) +if(CONFIG_INTELHEX_BINARY) + add_custom_command( + TARGET allsyms_nuttx + POST_BUILD + COMMAND ${CMAKE_OBJCOPY} -O ihex allsyms_nuttx nuttx.hex DEPENDS nuttx-hex + COMMENT "Regenerate nuttx.hex") + +endif() +if(CONFIG_MOTOROLA_SREC) + add_custom_command( + TARGET allsyms_nuttx + POST_BUILD + COMMAND ${CMAKE_OBJCOPY} -O srec allsyms_nuttx nuttx.srec DEPENDS nuttx-srec + COMMENT "Regenerate nuttx.srec") +endif() +if(CONFIG_RAW_BINARY) + add_custom_command( + TARGET allsyms_nuttx + POST_BUILD + COMMAND ${CMAKE_OBJCOPY} -O binary allsyms_nuttx nuttx.bin DEPENDS nuttx-bin + COMMENT "Regenerate nuttx.bin") +endif() diff --git a/cmake/nuttx_export_header.cmake b/cmake/nuttx_export_header.cmake index 1918a4e01d4f7..d883f20e8f177 100644 --- a/cmake/nuttx_export_header.cmake +++ b/cmake/nuttx_export_header.cmake @@ -1,5 +1,5 @@ # ############################################################################## -# cmake/nuttx_export_headers.cmake +# cmake/nuttx_export_header.cmake # # Licensed to the Apache Software Foundation (ASF) under one or more contributor # license agreements. See the NOTICE file distributed with this work for diff --git a/cmake/nuttx_generate_headers.cmake b/cmake/nuttx_generate_headers.cmake index b4a2049e47efd..af12b4352adef 100644 --- a/cmake/nuttx_generate_headers.cmake +++ b/cmake/nuttx_generate_headers.cmake @@ -49,8 +49,13 @@ if(NOT EXISTS ${CMAKE_BINARY_DIR}/include/arch) endif() if(NOT EXISTS ${CMAKE_BINARY_DIR}/include_arch/arch/board) - nuttx_create_symlink(${NUTTX_BOARD_DIR}/include - ${CMAKE_BINARY_DIR}/include_arch/arch/board) + if(EXISTS ${NUTTX_BOARD_DIR}/include) + nuttx_create_symlink(${NUTTX_BOARD_DIR}/include + ${CMAKE_BINARY_DIR}/include_arch/arch/board) + elseif(EXISTS ${NUTTX_BOARD_DIR}/../common/include) + nuttx_create_symlink(${NUTTX_BOARD_DIR}/../common/include + ${CMAKE_BINARY_DIR}/include_arch/arch/board) + endif() endif() if(NOT EXISTS ${CMAKE_BINARY_DIR}/include_arch/arch/chip) diff --git a/cmake/nuttx_kconfig.cmake b/cmake/nuttx_kconfig.cmake index 2b19a1cd74b93..b20d7860f5b64 100644 --- a/cmake/nuttx_kconfig.cmake +++ b/cmake/nuttx_kconfig.cmake @@ -18,14 +18,36 @@ # # ############################################################################## +macro(encode_brackets contents) + string(REGEX REPLACE "\\[" "__OPEN_BRACKET__" ${contents} "${${contents}}") + string(REGEX REPLACE "\\]" "__CLOSE_BRACKET__" ${contents} "${${contents}}") +endmacro() + +macro(decode_brackets contents) + string(REGEX REPLACE "__OPEN_BRACKET__" "[" ${contents} "${${contents}}") + string(REGEX REPLACE "__CLOSE_BRACKET__" "]" ${contents} "${${contents}}") +endmacro() + +macro(encode_semicolon contents) + string(REGEX REPLACE ";" "__SEMICOLON__" ${contents} "${${contents}}") +endmacro() + +macro(decode_semicolon contents) + string(REGEX REPLACE "__SEMICOLON__" ";" ${contents} "${${contents}}") +endmacro() + function(nuttx_export_kconfig_by_value kconfigfile config) file(STRINGS ${kconfigfile} ConfigContents) + encode_brackets(ConfigContents) foreach(NameAndValue ${ConfigContents}) + decode_brackets(NameAndValue) + encode_semicolon(NameAndValue) string(REGEX REPLACE "^[ ]+" "" NameAndValue ${NameAndValue}) string(REGEX MATCH "^CONFIG[^=]+" Name ${NameAndValue}) if(Name STREQUAL ${config}) string(REPLACE "${Name}=" "" Value ${NameAndValue}) string(REPLACE "\"" "" Value ${Value}) + decode_semicolon(Value) set(${Name} ${Value} PARENT_SCOPE) @@ -41,7 +63,10 @@ function(nuttx_export_kconfig kconfigfile) set(${key} PARENT_SCOPE) endforeach() file(STRINGS ${kconfigfile} ConfigContents) + encode_brackets(ConfigContents) foreach(NameAndValue ${ConfigContents}) + decode_brackets(NameAndValue) + encode_semicolon(NameAndValue) # Strip leading spaces string(REGEX REPLACE "^[ ]+" "" NameAndValue ${NameAndValue}) @@ -54,7 +79,7 @@ function(nuttx_export_kconfig kconfigfile) # remove extra quotes string(REPLACE "\"" "" Value ${Value}) - + decode_semicolon(Value) # Set the variable set(${Name} ${Value} diff --git a/cmake/nuttx_mkconfig.cmake b/cmake/nuttx_mkconfig.cmake index 19aeee494b371..71500c355aa58 100644 --- a/cmake/nuttx_mkconfig.cmake +++ b/cmake/nuttx_mkconfig.cmake @@ -40,6 +40,14 @@ if(COMPARE_RESULT EQUAL 0 AND EXISTS ${CONFIG_H}) return() endif() +set(BASE_DEFCONFIG "${NUTTX_BOARD}/${NUTTX_CONFIG}") +execute_process( + COMMAND ${CMAKE_COMMAND} -E compare_files ${CMAKE_BINARY_DIR}/.config + ${CMAKE_BINARY_DIR}/.config.orig RESULT_VARIABLE COMPARE_RESULT) +if(COMPARE_RESULT) + string(APPEND BASE_DEFCONFIG "-dirty") +endif() + set(DEQUOTELIST # NuttX "CONFIG_DEBUG_OPTLEVEL" # Custom debug level @@ -81,13 +89,20 @@ file(APPEND ${CONFIG_H} "#define CONFIG_y 1\n") file(APPEND ${CONFIG_H} "#define CONFIG_m 2\n\n") file(APPEND ${CONFIG_H} "/* General Definitions ***********************************/\n") +file(APPEND ${CONFIG_H} "#define CONFIG_BASE_DEFCONFIG \"${BASE_DEFCONFIG}\"\n") file(STRINGS ${CMAKE_BINARY_DIR}/.config ConfigContents) +encode_brackets(ConfigContents) foreach(NameAndValue ${ConfigContents}) + decode_brackets(NameAndValue) + encode_semicolon(NameAndValue) string(REGEX REPLACE "^[ ]+" "" NameAndValue ${NameAndValue}) string(REGEX MATCH "^CONFIG[^=]+" NAME ${NameAndValue}) + # skip BASE_DEFCONFIG here as it is handled above + if("${NAME}" STREQUAL "CONFIG_BASE_DEFCONFIG") + continue() + endif() string(REPLACE "${NAME}=" "" VALUE ${NameAndValue}) - if(NAME AND NOT "${VALUE}" STREQUAL "") if(${VALUE} STREQUAL "y") file(APPEND ${CONFIG_H} "#define ${NAME} 1\n") @@ -99,7 +114,8 @@ foreach(NameAndValue ${ConfigContents}) foreach(dequote ${DEQUOTELIST}) if("${NAME}" STREQUAL "${dequote}") if(NOT "${VALUE}" STREQUAL "\"\"") - string(REGEX REPLACE "\"" "" VALUE ${VALUE}) + string(REGEX REPLACE "^\"(.*)\"$" "\\1" VALUE "${VALUE}") + string(REGEX REPLACE "\\\\\\\"" "\"" VALUE "${VALUE}") else() set(VALUE) file(APPEND ${CONFIG_H} "#undef ${NAME}\n") @@ -108,6 +124,7 @@ foreach(NameAndValue ${ConfigContents}) endif() endforeach() if(NOT "${VALUE}" STREQUAL "") + decode_semicolon(VALUE) file(APPEND ${CONFIG_H} "#define ${NAME} ${VALUE}\n") endif() endif() diff --git a/cmake/nuttx_source_file_properties.cmake b/cmake/nuttx_source_file_properties.cmake new file mode 100644 index 0000000000000..25a7f6493db26 --- /dev/null +++ b/cmake/nuttx_source_file_properties.cmake @@ -0,0 +1,46 @@ +# ############################################################################## +# cmake/nuttx_source_file_properties.cmake +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +# Because `set_source_files_properties` in cmake will overwrite the properties +# instead of appending them. This module implements addition and deletion by +# first `getting_source_file_property` and then `set_source_files_properties` + +# addition +function(nuttx_append_source_file_properties SOURCE_FILE PROPERTY_NAME + PROPERTY_VALUE) + get_source_file_property(curr_value ${SOURCE_FILE} ${PROPERTY_NAME}) + if(NOT curr_value) + set(curr_value "") + endif() + set_source_files_properties( + ${SOURCE_FILE} PROPERTIES ${PROPERTY_NAME} + "${curr_value} ${PROPERTY_VALUE}") +endfunction() + +# deletion +function(nuttx_remove_source_file_property SOURCE_FILE PROPERTY_NAME + VALUE_TO_REMOVE) + get_source_file_property(curr_value ${SOURCE_FILE} ${PROPERTY_NAME}) + if(curr_value) + string(REPLACE ${VALUE_TO_REMOVE} "" new_value ${curr_value}) + set_source_files_properties(${SOURCE_FILE} PROPERTIES ${PROPERTY_NAME} + "${new_value}") + endif() +endfunction() diff --git a/crypto/bn.c b/crypto/bn.c index e21368bab9474..6796fcca4f978 100644 --- a/crypto/bn.c +++ b/crypto/bn.c @@ -58,7 +58,7 @@ /* Custom assert macro - easy to disable */ -#define require(p, msg) assert(p && msg) +#define require(p, msg) ASSERT(p && msg) /**************************************************************************** * Private Functions Prototype diff --git a/drivers/Kconfig b/drivers/Kconfig index 77031932d2f03..22603be331640 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -37,6 +37,7 @@ source "drivers/pipes/Kconfig" source "drivers/power/Kconfig" source "drivers/regmap/Kconfig" source "drivers/rmt/Kconfig" +source "drivers/rpmsg/Kconfig" source "drivers/rptun/Kconfig" source "drivers/sensors/Kconfig" source "drivers/serial/Kconfig" @@ -58,3 +59,5 @@ source "drivers/usrsock/Kconfig" source "drivers/dma/Kconfig" source "drivers/devicetree/Kconfig" source "drivers/reset/Kconfig" +source "drivers/pci/Kconfig" +source "drivers/virt/Kconfig" diff --git a/drivers/Makefile b/drivers/Makefile index e553af04d3e83..40ed2d38af12e 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -56,6 +56,7 @@ include pipes/Make.defs include power/Make.defs include regmap/Make.defs include rmt/Make.defs +include rpmsg/Make.defs include rptun/Make.defs include sensors/Make.defs include serial/Make.defs @@ -76,6 +77,8 @@ include rc/Make.defs include segger/Make.defs include usrsock/Make.defs include reset/Make.defs +include pci/Make.defs +include virt/Make.defs ifeq ($(CONFIG_SPECIFIC_DRIVERS),y) -include platform/Make.defs diff --git a/drivers/analog/CMakeLists.txt b/drivers/analog/CMakeLists.txt index 3631ef0b73c57..2a5e8ebb92909 100644 --- a/drivers/analog/CMakeLists.txt +++ b/drivers/analog/CMakeLists.txt @@ -91,6 +91,10 @@ if(CONFIG_ADC) if(CONFIG_ADC_LTC1867L) list(APPEND SRCS ltc1867l.c) endif() + + if(CONFIG_ADC_HX711) + list(APPEND SRCS hx711.c) + endif() endif() if(CONFIG_LMP92001) diff --git a/drivers/analog/Kconfig b/drivers/analog/Kconfig index b6536a49bb36c..c7a5f0885b673 100644 --- a/drivers/analog/Kconfig +++ b/drivers/analog/Kconfig @@ -192,6 +192,43 @@ endchoice endif # ADC_MAX1161X +config ADC_HX711 + bool "Avia Semiconductor HX711 support" + default n + ---help--- + Enable driver to support Avia Semiconductor HX711 ADC + designed for weight scales. + + Driver supports both 'a' and 'b' channels with 32, 64 + and 128 gain. + + Driver does not support continuous read and is not buffered. + Driver uses interrupts to not hog the CPU while waiting + for hx711 to be ready. + +if ADC_HX711 + +config ADC_HA711_ADD_DELAY + bool "Add 1us delay between clock pulses" + default y if BOARD_LOOPSPERMSEC >= 15000 + ---help--- + HX711 requires about 1us between clock pulses to work. + This is not an issue on slower chips, but faster chips + will most likely try to clock HX711 too fast, which + will result in data lose. + + If this is enabled, code will insert 1us of delay to each + clock change. Enable this only if you get data lose, or + else you will just introduce unnecessary delay to your + program. + + Best way to know if you need this, is to compile + HX711 demo program and run it. If there are no errors + reported during runtime, you can turn this of. If you + see communication errors, then you should enable this. + +endif # ADC_HX711 + endif # ADC config COMP @@ -208,6 +245,16 @@ config DAC if DAC +config DAC_FIFOSIZE + int "DAC buffer size" + default 8 + range 1 255 + ---help--- + This variable defines the size of the DAC ring buffer that is used + to queue sent DAC data until they can be retrieved by the + controller. This size is limited to 255 to fit uint8_t type used + in DAC driver. + config DAC_AD5410 bool "AD5410 support" default n diff --git a/drivers/analog/Make.defs b/drivers/analog/Make.defs index c649266018b15..45ee37f371d4a 100644 --- a/drivers/analog/Make.defs +++ b/drivers/analog/Make.defs @@ -103,6 +103,10 @@ endif ifeq ($(CONFIG_ADC_LTC1867L),y) CSRCS += ltc1867l.c endif + +ifeq ($(CONFIG_ADC_HX711),y) + CSRCS += hx711.c +endif endif ifeq ($(CONFIG_LMP92001),y) diff --git a/drivers/analog/hx711.c b/drivers/analog/hx711.c new file mode 100644 index 0000000000000..089a780743c9f --- /dev/null +++ b/drivers/analog/hx711.c @@ -0,0 +1,970 @@ +/**************************************************************************** + * drivers/analog/hx711.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include + +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define DEVNAME_FMT "/dev/hx711_%d" +#define DEVNAME_FMTLEN (11 + 3 + 1) + +/* hx711 is a 24 bit ADC, but in case they decide to do like a + * hx771s(uperb) with 32 bit resolution, here is easy to change def + */ + +#define HX711_BITS_PER_READ 24 + +#define HX711_TARE_MAX_LOOP 64 +#define HX711_TARE_NSAMPLES 5 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct hx711_dev_s +{ + FAR struct hx711_lower_s *lower; + mutex_t excl; + sem_t hx711_ready; + int crefs; + int unlinked; + unsigned char minor; + + int val_per_unit; + long tare; + unsigned char average; + unsigned char gain; + char channel; + signed char sign; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int hx711_open(FAR struct file *filep); +static int hx711_close(FAR struct file *filep); +static int hx711_unlink(FAR struct inode *inode); +static int hx711_ioctl(FAR struct file *filep, int cmd, unsigned long arg); +static ssize_t hx711_read(FAR struct file *filep, + FAR char *buf, size_t buflen); +static int32_t hx711_single_read(FAR struct hx711_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct file_operations g_hx711_fops = +{ +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + .unlink = hx711_unlink, +#endif /* CONFIG_DISABLE_PSEUDOFS_OPERATIONS */ + .open = hx711_open, + .close = hx711_close, + .read = hx711_read, + .ioctl = hx711_ioctl +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: hx711_tare + * + * Description: + * Tares the scale. Function will read some number of samples and will + * check if these readings are stable (more or less the same within + * specified precision). If operation is a success, next call to read() + * will return value close to 0 (if no force is applied to tensometer). + * + * Input Parameters: + * dev - hx711 instance to tare + * precision - precision with which to tare the scale. If set to 100 + * function will set new tare if min-max values read are + * less than 100 + * + * Returned Value: + * OK - on success + * -EIO - no communication with the hx711 + * -ETIME - scale was not stable for HX711_TARE_NSAMPLES loops + * + ****************************************************************************/ + +static int hx711_tare(FAR struct hx711_dev_s *dev, float precision) +{ + int32_t samples[HX711_TARE_NSAMPLES]; + int i; + int j; + int min; + int max; + long tare; + int prec; + long taresave; + signed char signsave; + + /* If value per unit is defined, we assume precision is specified + * in units, calculate raw value for precision + */ + + prec = dev->val_per_unit > 0 ? precision * dev->val_per_unit : precision; + + /* Save old tare value and sign, which we will restore when we + * have an error + */ + + taresave = dev->tare; + signsave = dev->sign; + + /* Reset tare value and sign during taring */ + + dev->tare = 0; + dev->sign = 1; + + for (i = 0; i != HX711_TARE_NSAMPLES; i++) + { + samples[i] = hx711_single_read(dev); + if (samples[i] == INT32_MIN) + { + dev->tare = taresave; + dev->sign = signsave; + return -EIO; + } + } + + for (i = 0; i != HX711_TARE_MAX_LOOP; i++) + { + /* Check if scale reading is stable */ + + min = INT_MAX; + max = INT_MIN; + for (j = 0; j != HX711_TARE_NSAMPLES; j++) + { + min = samples[j] < min ? samples[j] : min; + max = samples[j] > max ? samples[j] : max; + } + + if (max - min <= prec) + { + /* Scale readings are stable within specified precision. + * Use average of these readings to set new tare value. + */ + + for (tare = j = 0; j != HX711_TARE_NSAMPLES; j++) + { + tare += samples[j]; + } + + tare /= HX711_TARE_NSAMPLES; + dev->tare = tare; + dev->sign = signsave; + return OK; + } + + /* Reading is not yet stable, perform next read and check + * stability again + */ + + samples[i % HX711_TARE_NSAMPLES] = hx711_single_read(dev); + if (samples[i % HX711_TARE_NSAMPLES] == INT32_MIN) + { + dev->tare = taresave; + dev->sign = signsave; + return -EIO; + } + } + + /* If we get here, we couldn't get stable readings within specified + * limit + */ + + dev->tare = taresave; + dev->sign = signsave; + return -ETIME; +} + +/**************************************************************************** + * Name: hx711_ioctl + * + * Description: + * Perform device specific operations. + * + * Input Parameters: + * filep - file on vfs associated with the driver. + * cmd - command to perform + * arg - argument for the cmd + * + * Returned Value: + * Returns OK on success or negated errno on failure. + * + ****************************************************************************/ + +static int hx711_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + FAR struct hx711_dev_s *dev; + int ret; + + dev = filep->f_inode->i_private; + + /* Get exclusive access to the hx711 driver state */ + + ret = nxmutex_lock(&dev->excl); + if (ret < 0) + { + return ret; + } + + ret = OK; + switch (cmd) + { + case HX711_SET_AVERAGE: + if (arg < 1 || arg > HX711_MAX_AVG_SAMPLES) + { + /* Averaging more than HX711_MAX_AVG_SAMPLES samples could + * overflow averaging variable leading to invalid reading. + */ + + ret = -EINVAL; + break; + } + + dev->average = arg; + break; + + case HX711_SET_CHANNEL: + if (arg != 'a' || arg != 'b') + { + /* Only channel a or b are available */ + + ret = -EINVAL; + break; + } + + dev->channel = arg; + + if (dev->channel == 'b') + { + /* Only valid gain for channel b is 32, adjust */ + + dev->gain = 32; + } + + if (dev->channel == 'a') + { + /* If we are switching from channel 'b', gain will be 32, + * which is invalid value for channel 'a'. If current gain + * is not valid for channel 'a', set default value of 128 + */ + + if (dev->gain != 128 && dev->gain != 64) + { + dev->gain = 128; + } + } + + /* Channel setting will be applied after next read from hx711, + * we have to do one dummy read, so that user can immediately + * read from new channel + */ + + if (hx711_single_read(dev) == INT32_MIN) + { + ret = -EIO; + } + + break; + + case HX711_SET_GAIN: + if (dev->channel == 'a' && (arg != 128 || arg != 64)) + { + /* For channel 'a' only gain of value 128 and 64 are valid */ + + ret = -EINVAL; + break; + } + else if (dev->channel == 'b' && arg != 32) + { + /* For channel 'b' only gain of 32 is valid */ + + ret = -EINVAL; + break; + } + + dev->gain = arg; + + break; + + case HX711_SET_VAL_PER_UNIT: + dev->val_per_unit = arg; + break; + + case HX711_GET_AVERAGE: + { + unsigned *ptr = (unsigned *)((uintptr_t)arg); + if (ptr == NULL) + { + ret = -EINVAL; + break; + } + + *ptr = dev->average; + break; + } + + case HX711_GET_CHANNEL: + { + char *ptr = (char *)((uintptr_t)arg); + if (ptr == NULL) + { + ret = -EINVAL; + break; + } + + *ptr = dev->channel; + break; + } + + case HX711_GET_GAIN: + { + unsigned char *ptr = (unsigned char *)((uintptr_t)arg); + if (ptr == NULL) + { + ret = -EINVAL; + break; + } + + *ptr = dev->gain; + break; + } + + case HX711_GET_VAL_PER_UNIT: + { + unsigned *ptr = (unsigned *)((uintptr_t)arg); + if (ptr == NULL) + { + ret = -EINVAL; + break; + } + + *ptr = dev->val_per_unit; + break; + } + + case HX711_TARE: + { + float *precision = (float *)((uintptr_t)arg); + if (precision == NULL) + { + ret = -EINVAL; + break; + } + + ret = hx711_tare(dev, *precision); + break; + } + + case HX711_SET_SIGN: + { + int *sign = (int *)((uintptr_t)arg); + if (sign == NULL || (*sign != 1 && *sign != -1)) + { + ret = EINVAL; + break; + } + + dev->sign = *sign; + break; + } + + default: + ret = EINVAL; + } + + nxmutex_unlock(&dev->excl); + return ret; +} + +/**************************************************************************** + * Name: hx711_data_interrupt + * + * Description: + * Function is called when we are waiting for hx711 to be ready and once + * data line goes from HIGH to LOW state. + * + * Input Parameters: + * arg - hx711 device instance + * + ****************************************************************************/ + +static int hx711_data_interrupt(int irq, FAR void *context, FAR void *arg) +{ + UNUSED(irq); + UNUSED(context); + FAR struct hx711_dev_s *dev = arg; + + nxsem_post(&dev->hx711_ready); + return 0; +} + +/**************************************************************************** + * Name: hx711_wait_ready + * + * Description: + * Waits for conversion to be ready to read. + * + * Input Parameters: + * dev - hx711 device instance + * + * Returned Value: + * Function returns OK when chip is ready for reading, or -EIO, which + * means there is problem communicating with the device. + * + ****************************************************************************/ + +static int hx711_wait_ready(FAR struct hx711_dev_s *dev) +{ + int ret; + struct timespec tp; + + /* It is possible that there was no read() call for long enough + * that hx711 is already ready, if that is the case just quickly return + */ + + if (dev->lower->data_read(dev->minor) == 0) + { + return OK; + } + + /* Install data line interrupt, so we know when hx711 is ready. + * This can even be 100ms between sampling, and up to 500ms when + * hx711 goes out of low power mode + */ + + if ((ret = dev->lower->data_irq(dev->minor, hx711_data_interrupt, dev))) + { + return ret; + } + + /* During waiting for ready signal, clock should be low */ + + dev->lower->clock_set(dev->minor, 0); + + clock_gettime(CLOCK_MONOTONIC, &tp); + tp.tv_sec += 1; + + if ((ret = nxsem_timedwait(&dev->hx711_ready, &tp))) + { + /* Chip not ready for long time. This probably mean that the + * hx711 chip is not properly (if at all) connected. + */ + + dev->lower->data_irq(dev->minor, NULL, NULL); + return -EIO; + } + + /* hx711 is ready */ + + dev->lower->data_irq(dev->minor, NULL, NULL); + return OK; +} + +/**************************************************************************** + * Name: hx711_delay + * + * Description: + * hx711 datasheet specifies that time between clock changes should be + * between 0.2us and 50us, with typical value of 1us. On slow MCUs this + * is not a problem, as all operations between clocking take longer than + * that time, but on fast CHIP, clocking without delay will cause data + * lose. + * + ****************************************************************************/ + +static void hx711_delay(void) +{ +#ifdef CONFIG_ADC_HX711_ADD_DELAY + up_delay(1); +#endif +} + +/**************************************************************************** + * Name: hx711_single_read + * + * Description: + * Reads single, 24bit adc data from hx711. Function will perform + * conversion form 24bit 2's complement to 32bit 2's complement. + * + * Input Parameters: + * dev - hx711 instance to perform read from. + * + * Returned Value: + * Read value from hx711. Returned value is stored on 24 bits of + * int32_t type. If there was error during read, function will + * return INT32_MIN. + * + ****************************************************************************/ + +static int32_t hx711_single_read(FAR struct hx711_dev_s *dev) +{ + int32_t value; + int i; + int pulses; + int flags; + int ret; + + /* Wait for conversion to be finished */ + + if ((ret = hx711_wait_ready(dev))) + { + /* Timeout while waiting for chip, assuming chip is not connected */ + + nxmutex_unlock(&dev->excl); + return INT32_MIN; + } + + /* Even though we are clocking the hx711, we must perform whole readout + * without interruption. This is because, if we set clock pin to HIGH, + * hx711 will go into low power mode in 60us unless we set clock to LOW + * within that time. + */ + + flags = enter_critical_section(); + + for (value = i = 0; i != HX711_BITS_PER_READ; i++) + { + dev->lower->clock_set(dev->minor, 1); + hx711_delay(); + + /* Data is sent MSB first */ + + value |= dev->lower->data_read(dev->minor); + value <<= 1; + dev->lower->clock_set(dev->minor, 0); + hx711_delay(); + } + + /* Next few clock pulses will determine type of next conversion + * hx711 will perform. We gotta do this in the same critical + * section block as read. + * + * 1 pulse - Channel A, Gain 128 + * 2 pulses - Channel B, Gain 32 + * 3 pulses - Channel A, Gain 64 + */ + + if (dev->channel == 'b') + { + /* Channel B has static gain of 32 */ + + pulses = 2; + } + else + { + /* channel A has 2 possible gains, either 128 or 64. */ + + pulses = dev->gain == 128 ? 1 : 3; + } + + for (i = 0; i != pulses; i++) + { + dev->lower->clock_set(dev->minor, 1); + hx711_delay(); + dev->lower->clock_set(dev->minor, 0); + hx711_delay(); + } + + leave_critical_section(flags); + + /* Data is sent in standard 2's complement, but we just stored + * 24bit integer in a 32bit integer. For positives reading this + * makes no difference, but if we have just returned 24bit negative + * number in 32bit integer, we would end up with positive (and false) + * reading. + * + * If number is negative, convert it to 32bit negative. + */ + + if (value & 0x800000) + { + value |= 0xff000000; + } + + /* Apply tare value and sign at the end */ + + return dev->sign * (value - dev->tare); +} + +/**************************************************************************** + * Name: hx711_read + * + * Description: + * Performs read from the hx711 device. Only a single value can be read + * with single call, but when averaging is enabled, driver will read + * configured number of points and will return single, average value + * of them all. + * + * Input Parameters: + * filep - file on vfs associated with the driver. + * buf - pointer to 32bit integer where value will be stored. + * buflen - size of buf, must be equal to 4 (sizeof(int32_t)) + * + * Returned Value: + * On success 4 is returned (sizeof(int32_t)), as in number of bytes + * copied to userspace. On failure, negated errno is returned. + * + ****************************************************************************/ + +static ssize_t hx711_read(FAR struct file *filep, + FAR char *buf, size_t buflen) +{ + FAR struct hx711_dev_s *dev; + int ret; + int32_t value; /* 24bit value from hx711 will be stored here */ + int32_t average; + int i; + + value = 0; + dev = filep->f_inode->i_private; + + if (buflen == 0) + { + return 0; + } + + if (buflen < sizeof(int32_t)) + { + return -EINVAL; + } + + /* Get exclusive access to the hx711 driver state */ + + ret = nxmutex_lock(&dev->excl); + if (ret < 0) + { + return ret; + } + + for (i = 1; i <= (int)dev->average; i++) + { + value = hx711_single_read(dev); + if (value == INT32_MIN) + { + /* There was error while reading sample. */ + + nxmutex_unlock(&dev->excl); + return -EIO; + } + + average = (average * (i - 1) + value) / i; + } + + /* We are done with the device, so free mutex for next possible client */ + + nxmutex_unlock(&dev->excl); + + /* If user specified value per unit, we convert raw data into units */ + + if (dev->val_per_unit > 0) + { + average /= dev->val_per_unit; + } + + /* Copy data back to userspace and exit */ + + if (buflen == sizeof(int32_t)) + { + /* int32 was passed, assuming binary operation from C code */ + + memcpy(buf, &average, sizeof(average)); + return sizeof(int32_t); + } + else + { + /* Something else passed, assuming it's shell operation. If it's + * called from C, it's assumed user wants c-string. + */ + + ret = snprintf(buf, buflen, "%"PRIi32"\n", average); + + /* snprintf returns number of bytes written (or that would have + * been written) without null byte, but we return number of bytes + * written including that byte, hence +1. + */ + + ret += 1; + + /* If buflen is not big enough, snprintf() will return number + * of bytes that would have been written to buf if enough space + * had been available and not number of bytes actually written. + * We must return number of bytes actually written, so we take + * smaller value. + */ + + return MIN(ret, (int)buflen); + } +} + +/**************************************************************************** + * Name: hx711_cleanup + * + * Description: + * Called when last user closed hx711 dsevice and that device is (or was) + * unlinked. + * + * Input Parameters: + * dev - hx711 device instance. + * + ****************************************************************************/ + +static void hx711_cleanup(FAR struct hx711_dev_s *dev) +{ + /* Put chip into sleep state by setting clock to HIGH */ + + dev->lower->clock_set(dev->minor, 1); + + if (dev->lower->cleanup) + { + dev->lower->cleanup(dev->minor); + } + + nxmutex_destroy(&dev->excl); + nxsem_destroy(&dev->hx711_ready); + kmm_free(dev); +} + +/**************************************************************************** + * Name: hx711_open + * + * Description: + * Open driver for use by userspace application. + * + * Input Parameters: + * filep - pointer to a file structure to open + * + * Returned Value: + * OK on success, or negated errno on failure + * + ****************************************************************************/ + +static int hx711_open(FAR struct file *filep) +{ + FAR struct hx711_dev_s *dev; + int ret; + + dev = filep->f_inode->i_private; + + /* Get exclusive access to the hx711 driver state */ + + ret = nxmutex_lock(&dev->excl); + if (ret < 0) + { + return ret; + } + + /* Increment the count of open references on the driver */ + + dev->crefs++; + DEBUGASSERT(dev->crefs > 0); + + nxmutex_unlock(&dev->excl); + return OK; +} + +/**************************************************************************** + * Name: hx711_close + * + * Description: + * Closes the driver device. If this is last reference and file has been + * unlinked, we will also free resources allocated by ipcc_register() + * + * Input Parameters: + * filep - pointer to a file structure to close. + * + * Returned Value: + * OK on success, or negated errno on failure. + * + ****************************************************************************/ + +static int hx711_close(FAR struct file *filep) +{ + FAR struct hx711_dev_s *dev; + int ret; + + dev = filep->f_inode->i_private; + + /* Get exclusive access to the hx711 driver state */ + + ret = nxmutex_lock(&dev->excl); + if (ret < 0) + { + return ret; + } + + /* Decrement the count of open references on the driver */ + + DEBUGASSERT(dev->crefs > 0); + dev->crefs--; + + if (dev->crefs <= 0 && dev->unlinked) + { + /* If count ref is zero and file has been unlinked, it + * means nobody uses the driver and seems like nobody + * wants to use it anymore, so free up resources. This + * also means we are last holders of excl mutex, which + * will be destroyed in cleanup function, so we don't + * have to unlock it here. + */ + + hx711_cleanup(dev); + return OK; + } + + nxmutex_unlock(&dev->excl); + return OK; +} + +/**************************************************************************** + * Name: hx711_unlink + * + * Description: + * Action to take upon file unlinking. Function will free resources if + * noone is using the driver when unlinking occured. If driver is still + * in use, it will be marked as unlinked and resource freeing will take + * place in hx711_close() function instead, once last reference is closed. + * + * Input Parameters: + * inode - driver inode that is being unlinked. + * + * Returned Value: + * OK on successfull close, or negated errno on failure. + * + ****************************************************************************/ + +static int hx711_unlink(FAR struct inode *inode) +{ + FAR struct hx711_dev_s *dev; + int ret; + + dev = inode->i_private; + + /* Get exclusive access to the hx711 driver state */ + + ret = nxmutex_lock(&dev->excl); + if (ret < 0) + { + return ret; + } + + /* Is anyone still using the driver? */ + + if (dev->crefs <= 0) + { + /* No, we are free to free resources */ + + hx711_cleanup(dev); + return OK; + } + + /* Yes, someone is still using the driver, just mark file + * as unlinked and free resources in hx711_close() once last + * reference is closed. + */ + + dev->unlinked = true; + nxmutex_unlock(&dev->excl); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: hx711_register + * + * Description: + * Register new hx711 device in /dev/hx711_%d. Multiple hx711 can be + * supported by providing different minor number. When driver calls + * platform specific function, minor number is passed back, so platform + * can know which hx711 is manipulated. + * + * Input Parameters: + * minor - unique number identifying hx711 chip. + * lower - provided by platform code to manipulate hx711 with platform + * dependant functions> + * + * Returned Value: + * OK on success, or negated errno on failure + * + ****************************************************************************/ + +int hx711_register(unsigned char minor, FAR struct hx711_lower_s *lower) +{ + FAR struct hx711_dev_s *dev; + char devname[DEVNAME_FMTLEN]; + int ret; + + dev = kmm_zalloc(sizeof(*dev)); + if (dev == NULL) + { + return -ENOMEM; + } + + snprintf(devname, DEVNAME_FMTLEN, DEVNAME_FMT, minor); + ret = register_driver(devname, &g_hx711_fops, 0666, dev); + if (ret) + { + kmm_free(dev); + return ret; + } + + dev->channel = 'a'; + dev->gain = 128; + dev->lower = lower; + dev->average = 1; + dev->sign = 1; + nxmutex_init(&dev->excl); + nxsem_init(&dev->hx711_ready, 0, 0); + + /* Put chip into working state by setting clock to LOW */ + + dev->lower->clock_set(dev->minor, 0); + + return OK; +} diff --git a/drivers/analog/mcp48xx.c b/drivers/analog/mcp48xx.c index 10092984d27d9..19b01747834a3 100644 --- a/drivers/analog/mcp48xx.c +++ b/drivers/analog/mcp48xx.c @@ -106,8 +106,6 @@ static int mcp48xx_ioctl(FAR struct dac_dev_s *dev, int cmd, * Private Data ****************************************************************************/ -static struct mcp48xx_dev_s g_devpriv; - static const struct dac_ops_s g_dacops = { mcp48xx_reset, /* ao_reset */ @@ -118,12 +116,6 @@ static const struct dac_ops_s g_dacops = mcp48xx_ioctl /* ao_ioctl */ }; -static struct dac_dev_s g_dacdev = -{ - &g_dacops, /* ad_ops */ - &g_devpriv /* ad_priv */ -}; - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -337,15 +329,35 @@ FAR struct dac_dev_s *mcp48xx_initialize(FAR struct spi_dev_s *spi, uint32_t spidev) { FAR struct mcp48xx_dev_s *priv; + FAR struct dac_dev_s *dacdev; int i; /* Sanity check */ DEBUGASSERT(spi != NULL); + /* Initialize the DAC device structure */ + + priv = kmm_malloc(sizeof(struct mcp48xx_dev_s)); + if (priv == NULL) + { + aerr("ERROR: Failed to allocate mcp48xx_dev_s instance\n"); + free(priv); + return NULL; + } + + dacdev = kmm_malloc(sizeof(struct dac_dev_s)); + if (dacdev == NULL) + { + aerr("ERROR: Failed to allocate dac_dev_s instance\n"); + return NULL; + } + + dacdev->ad_ops = &g_dacops; + dacdev->ad_priv = priv; + /* Initialize the MCP48XX device structure */ - priv = (FAR struct mcp48xx_dev_s *)g_dacdev.ad_priv; priv->spi = spi; priv->spidev = spidev; @@ -356,7 +368,7 @@ FAR struct dac_dev_s *mcp48xx_initialize(FAR struct spi_dev_s *spi, priv->cmd[i] = MCP48XX_SHDN | MCP48XX_GA; } - return &g_dacdev; + return dacdev; } #endif /* CONFIG_MCP48XX */ diff --git a/drivers/audio/audio_i2s.c b/drivers/audio/audio_i2s.c index 536a8d599b9e2..c427b6e5ed1fe 100644 --- a/drivers/audio/audio_i2s.c +++ b/drivers/audio/audio_i2s.c @@ -185,6 +185,9 @@ static int audio_i2s_getcaps(FAR struct audio_lowerhalf_s *dev, int type, /* Report the Sample rates we support */ caps->ac_controls.hw[0] = AUDIO_SAMP_RATE_DEF_ALL; + + caps->ac_channels = 2; + break; } diff --git a/drivers/bch/bchdev_unregister.c b/drivers/bch/bchdev_unregister.c index f476de72a7064..6eeb45d42eec5 100644 --- a/drivers/bch/bchdev_unregister.c +++ b/drivers/bch/bchdev_unregister.c @@ -91,13 +91,6 @@ int bchdev_unregister(FAR const char *chardev) return ret; } - /* Lock out context switches. If there are no other references - * and no context switches, then we can assume that we can safely - * teardown the driver. - */ - - sched_lock(); - /* Check if the internal structure is non-busy (we hold one reference). */ if (bch->refs > 1) @@ -117,8 +110,6 @@ int bchdev_unregister(FAR const char *chardev) goto errout_with_lock; } - sched_unlock(); - /* Release the internal structure */ bch->refs = 0; @@ -126,6 +117,5 @@ int bchdev_unregister(FAR const char *chardev) errout_with_lock: bch->refs--; - sched_unlock(); return ret; } diff --git a/drivers/can/Kconfig b/drivers/can/Kconfig index 1d663c7569138..d6a2b88a1d6ed 100644 --- a/drivers/can/Kconfig +++ b/drivers/can/Kconfig @@ -193,4 +193,44 @@ config MCP2515_SPI_SCK_FREQUENCY endif # CAN_MCP2515 -endif +menuconfig CAN_SJA1000 + tristate "Philips/NXP SJA1000 devices" + +if CAN_SJA1000 + +config CAN_SJA1000_BITRATE + int "SJA1000 bitrate" + default 1000000 + ---help--- + SJA1000 bit rate. + +config CAN_SJA1000_SJW + int "SJA1000 Synchronization Jump Width" + default 1 + range 1 4 + ---help--- + The duration of a synchronization jump is SJW. + +config CAN_SJA1000_SAM + bool "The CAN bus is sampled 3 times" + default false + ---help--- + Recommended for low to medium speed buses + to filter spikes on the bus-line. + +config CAN_SJA1000_SAMPLEP + int "SJA1000 CAN sample point (Percentage)" + default 87 + range 0 100 + +config CANBUS_REGDEBUG + bool "CAN BUS register debug enable." + default false + +config CAN_SJA1000_DEBUG + bool "SJA1000 CAN BUS trace debug enable." + default false + +endif # CAN_SJA1000 + +endif # CAN diff --git a/drivers/can/Make.defs b/drivers/can/Make.defs index 5d4014e7f14b1..49a4e7ca0ee05 100644 --- a/drivers/can/Make.defs +++ b/drivers/can/Make.defs @@ -28,6 +28,10 @@ ifeq ($(CONFIG_CAN_MCP2515),y) CSRCS += mcp2515.c endif +ifeq ($(CONFIG_CAN_SJA1000),y) + CSRCS += sja1000.c +endif + # Include CAN device driver build support DEPPATH += --dep-path can diff --git a/drivers/can/sja1000.c b/drivers/can/sja1000.c new file mode 100644 index 0000000000000..5da5f81566164 --- /dev/null +++ b/drivers/can/sja1000.c @@ -0,0 +1,1174 @@ +/**************************************************************************** + * drivers/can/sja1000.c + * + * SJA1000 CAN driver based on esp32c3_twai.c + * + * License header retained from original source. + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include "sja1000.h" + +#include + +#ifdef CONFIG_CAN_SJA1000 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration + * ************************************************************/ + +#if defined(CONFIG_CAN_SJA1000_DEBUG) +#define cantrace _info +#else +#define cantrace _none +#endif /* CONFIG_CAN_SJA1000_DEBUG */ + +/* Default values written to various registers on initialization */ + +#define SJA1000_INIT_TEC 0 +#define SJA1000_INIT_REC 0 +#define SJA1000_INIT_EWL 96 + +#define SJA1000_ACCEPTANCE_CODE 0x0 /* 32-bit address to match */ +#define SJA1000_ACCEPTANCE_MASK 0xffffffff /* 32-bit address mask */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* SJA1000 Register access */ + +#ifdef CONFIG_CANBUS_REGDEBUG +static void sja1000_printreg(uint32_t addr, uint32_t value); +#endif + +/* SJA1000 methods */ + +static void sja1000_reset(struct can_dev_s *dev); +static int sja1000_setup(struct can_dev_s *dev); +static void sja1000_shutdown(struct can_dev_s *dev); +static void sja1000_rxint(struct can_dev_s *dev, bool enable); +static void sja1000_txint(struct can_dev_s *dev, bool enable); +static int sja1000_ioctl(struct can_dev_s *dev, int cmd, unsigned long arg); +static int sja1000_remoterequest(struct can_dev_s *dev, uint16_t id); +static int sja1000_send(struct can_dev_s *dev, struct can_msg_s *msg); +static bool sja1000_txready(struct can_dev_s *dev); +static bool sja1000_txempty(struct can_dev_s *dev); + +/* SJA1000 interrupts */ + +static int sja1000_interrupt(FAR struct sja1000_config_s *config, + void *arg); + +/* SJA1000 acceptance filter */ + +static void sja1000_set_acc_filter(struct sja1000_dev_s *priv, + uint32_t code, uint32_t mask, + bool single_filter); + +/* SJA1000 bit-timing initialization */ + +static int sja1000_baud_rate(struct sja1000_dev_s *priv, int rate, + int clock, int sjw, int sampl_pt, int flags); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct can_ops_s g_sja1000ops = +{ + .co_reset = sja1000_reset, + .co_setup = sja1000_setup, + .co_shutdown = sja1000_shutdown, + .co_rxint = sja1000_rxint, + .co_txint = sja1000_txint, + .co_ioctl = sja1000_ioctl, + .co_remoterequest = sja1000_remoterequest, + .co_send = sja1000_send, + .co_txready = sja1000_txready, + .co_txempty = sja1000_txempty, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sja1000_printreg + * + * Description: + * Print the value read from a register. + * + * Input Parameters: + * addr - The register address + * value - The register value + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_CANBUS_REGDEBUG +static void sja1000_printreg(uint32_t addr, uint32_t value) +{ + static uint32_t prevaddr; + static uint32_t preval; + static uint32_t count; + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && value == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + caninfo("...\n"); + } + + return; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + caninfo("[repeats %" PRId32 " more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = value; + count = 1; + } + + /* Show the register value read */ + + caninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, value); +} +#endif /* CONFIG_CANBUS_REGDEBUG */ + +/**************************************************************************** + * Name: sja1000_reset + * + * Description: + * Reset the SJA1000 device. Called early to initialize the hardware. + *This function is called, before litex_sja1000_setup() and on error + *conditions. + * + * Input Parameters: + * dev - An instance of the "upper half" CAN driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void sja1000_reset(struct can_dev_s *dev) +{ + struct sja1000_dev_s *priv = (struct sja1000_dev_s *)dev->cd_priv; + struct sja1000_config_s *config = priv->config; + uint8_t port = config->port; + irqstate_t flags; + int ret; + + caninfo("SJA1000 Device %" PRIu8 "\n", port); + +#ifdef CONFIG_ARCH_HAVE_MULTICPU + flags = spin_lock_irqsave(&priv->lock); +#else + flags = enter_critical_section(); +#endif /* CONFIG_ARCH_HAVE_MULTICPU */ + + /* Disable the SJA1000 and stop ongoing transmissions */ + + uint32_t mode_value = SJA1000_RESET_MODE_M | SJA1000_LISTEN_ONLY_MODE_M; + sja1000_putreg(priv, + SJA1000_MODE_REG, mode_value); /* Enter Reset Mode */ + + sja1000_modifyreg32(priv, + SJA1000_CLOCK_DIVIDER_REG, 0, SJA1000_EXT_MODE_M); + + sja1000_putreg(priv, SJA1000_INT_ENA_REG, 0); /* Disable interrupts */ + sja1000_getreg(priv, SJA1000_STATUS_REG); /* Clear status bits */ + + sja1000_putreg(priv, + SJA1000_TX_ERR_CNT_REG, SJA1000_INIT_TEC); /* TEC */ + sja1000_putreg(priv, + SJA1000_RX_ERR_CNT_REG, SJA1000_INIT_REC); /* REC */ + sja1000_putreg(priv, + SJA1000_ERR_WARNING_LIMIT_REG, SJA1000_INIT_EWL); /* EWL */ + + sja1000_set_acc_filter( + priv, SJA1000_ACCEPTANCE_CODE, SJA1000_ACCEPTANCE_MASK, true); + + /* Set bit timing */ + + ret = sja1000_baud_rate(priv, config->bitrate, config->clk_freq, + config->sjw, config->samplep, 0); + + if (ret != OK) + { + canerr("ERROR: Failed to set bit timing: %d\n", ret); + } + + /* Restart the SJA1000 */ + + if (config->loopback) + { + /* Leave Reset Mode, enter Test Mode */ + + sja1000_putreg(priv, SJA1000_MODE_REG, SJA1000_SELF_TEST_MODE_M); + } + else + { + /* Leave Reset Mode */ + + sja1000_putreg(priv, SJA1000_MODE_REG, 0); + } + + /* Abort transmission, release RX buffer and clear overrun. + * Command register can only be modified when in Operation Mode. + */ + + sja1000_putreg(priv, SJA1000_CMD_REG, SJA1000_ABORT_TX_M + | SJA1000_RELEASE_BUF_M + | SJA1000_CLR_OVERRUN_M); + +#ifdef CONFIG_ARCH_HAVE_MULTICPU + spin_unlock_irqrestore(&priv->lock, flags); +#else + leave_critical_section(flags); +#endif /* CONFIG_ARCH_HAVE_MULTICPU */ +} + +/**************************************************************************** + * Name: sja1000_setup + * + * Description: + * Configure the SJA1000. This method is called the first time that the + *SJA1000 device is opened. This will occur when the port is first opened. + * This setup includes configuring and attaching SJA1000 interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" CAN driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int sja1000_setup(struct can_dev_s *dev) +{ + struct sja1000_dev_s *priv = (struct sja1000_dev_s *)dev->cd_priv; + struct sja1000_config_s *config = priv->config; + uint8_t port = config->port; + irqstate_t flags; + int ret = OK; + + caninfo("SJA1000 (%" PRIu8 ")\n", port); + +#ifdef CONFIG_ARCH_HAVE_MULTICPU + flags = spin_lock_irqsave(&priv->lock); +#else + flags = enter_critical_section(); +#endif /* CONFIG_ARCH_HAVE_MULTICPU */ + + sja1000_putreg(priv, SJA1000_INT_ENA_REG, SJA1000_DEFAULT_INTERRUPTS); + + /* clear latched interrupts */ + + sja1000_getreg(priv, SJA1000_INT_RAW_REG); + + /* Attach the SJA1000 interrupts and handler. */ + + ret = config->attach( + config, (sja1000_handler_t)sja1000_interrupt, (FAR void *)dev); + if (ret < 0) + { + canerr("ERROR: Failed to attach to IRQ Handler!\n"); + return ret; + } + +#ifdef CONFIG_ARCH_HAVE_MULTICPU + spin_unlock_irqrestore(&priv->lock, flags); +#else + leave_critical_section(flags); +#endif /* CONFIG_ARCH_HAVE_MULTICPU */ + + return ret; +} + +/**************************************************************************** + * Name: sja1000_shutdown + * + * Description: + * Disable the SJA1000. This method is called when the SJA1000 device is + *closed. This method reverses the operation the setup method. + * + * Input Parameters: + * dev - An instance of the "upper half" CAN driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void sja1000_shutdown(struct can_dev_s *dev) +{ + int ret; + struct sja1000_dev_s *priv = (struct sja1000_dev_s *)dev->cd_priv; + struct sja1000_config_s *config = priv->config; + uint8_t port = config->port; + + cantrace("shutdown SJA1000 (%" PRIu8 ")\n", port); + + /* Detach the SJA1000 interrupts and handler. */ + + ret = config->detach(config); + if (ret < 0) + { + canerr("ERROR: Failed to detach from IRQ Handler!\n"); + } +} + +/**************************************************************************** + * Name: sja1000_rxint + * + * Description: + * Call to enable or disable RX interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" CAN driver state structure. + * enable - Enable or disable receive interrupt. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void sja1000_rxint(struct can_dev_s *dev, bool enable) +{ + struct sja1000_dev_s *priv = (struct sja1000_dev_s *)dev->cd_priv; + struct sja1000_config_s *config = priv->config; + uint8_t port = config->port; + uint32_t regval; + irqstate_t flags; + + cantrace("SJA1000 (%" PRIu8 ") enable: %d\n", port, enable); + + /* The INT_ENA register is also modified from the interrupt handler, + * so we have to protect this code section. + */ + +#ifdef CONFIG_ARCH_HAVE_MULTICPU + flags = spin_lock_irqsave(&priv->lock); +#else + flags = enter_critical_section(); +#endif /* CONFIG_ARCH_HAVE_MULTICPU */ + + regval = sja1000_getreg(priv, SJA1000_INT_ENA_REG); + if (enable) + { + regval |= SJA1000_RX_INT_ENA_M; + } + else + { + regval &= ~SJA1000_RX_INT_ENA_M; + } + + sja1000_putreg(priv, SJA1000_INT_ENA_REG, regval); +#ifdef CONFIG_ARCH_HAVE_MULTICPU + spin_unlock_irqrestore(&priv->lock, flags); +#else + leave_critical_section(flags); +#endif /* CONFIG_ARCH_HAVE_MULTICPU */ +} + +/**************************************************************************** + * Name: sja1000_txint + * + * Description: + * Call to enable or disable TX interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" CAN driver state structure. + * enable - Enable or disable transmit interrupt. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void sja1000_txint(struct can_dev_s *dev, bool enable) +{ + struct sja1000_dev_s *priv = (struct sja1000_dev_s *)dev->cd_priv; + struct sja1000_config_s *config = priv->config; + uint8_t port = config->port; + uint32_t regval; + irqstate_t flags; + + cantrace("SJA1000 (%" PRIu8 ") enable: %d\n", port, enable); + + /* Only disabling of the TX interrupt is supported here. The TX interrupt + * is automatically enabled just before a message is sent in order to + * avoid lost TX interrupts. + */ + + if (!enable) + { + /* TX interrupts are also disabled from the interrupt handler, so we + * have to protect this code section. + */ + +#ifdef CONFIG_ARCH_HAVE_MULTICPU + flags = spin_lock_irqsave(&priv->lock); +#else + flags = enter_critical_section(); +#endif /* CONFIG_ARCH_HAVE_MULTICPU */ + + /* Disable all TX interrupts */ + + regval = sja1000_getreg(priv, SJA1000_INT_ENA_REG); + regval &= ~(SJA1000_TX_INT_ENA_M); + sja1000_putreg(priv, SJA1000_INT_ENA_REG, regval); +#ifdef CONFIG_ARCH_HAVE_MULTICPU + spin_unlock_irqrestore(&priv->lock, flags); +#else + leave_critical_section(flags); +#endif /* CONFIG_ARCH_HAVE_MULTICPU */ + } + + cantrace("Exiting.\n"); +} + +/**************************************************************************** + * Name: sja1000_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + * Input Parameters: + * dev - An instance of the "upper half" CAN driver state structure. + * cmd - A ioctl command. + * arg - A ioctl argument. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int sja1000_ioctl(struct can_dev_s *dev, int cmd, unsigned long arg) +{ + struct sja1000_dev_s *priv = (struct sja1000_dev_s *)dev->cd_priv; + struct sja1000_config_s *config = priv->config; + int ret = -ENOTTY; + uint8_t port = config->port; + + cantrace("SJA1000 (%" PRIu8 ") cmd=%04x arg=%lu\n", port, cmd, arg); + + /* Handle the command */ + + switch (cmd) + { + /* CANIOC_GET_BITTIMING: + * Description: Return the current bit timing settings + * Argument: A pointer to a write-able instance of struct + * canioc_bittiming_s in which current bit timing + * values will be returned. + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR) is returned with the errno variable set + * to indicate the nature of the error. + * Dependencies: None + */ + + case CANIOC_GET_BITTIMING: + { + struct canioc_bittiming_s *bt = (struct canioc_bittiming_s *)arg; + uint32_t timing0; + uint32_t timing1; + uint32_t brp; + + DEBUGASSERT(bt != NULL); + + timing0 = sja1000_getreg(priv, SJA1000_BUS_TIMING_0_REG); + timing1 = sja1000_getreg(priv, SJA1000_BUS_TIMING_1_REG); + + brp = ((timing0 & SJA1000_BAUD_PRESC_M) + 1) * 2; + bt->bt_sjw = ((timing0 & SJA1000_SYNC_JUMP_WIDTH_M) + >> SJA1000_SYNC_JUMP_WIDTH_S) + + 1; + + bt->bt_tseg1 + = ((timing1 & SJA1000_TIME_SEG1_M) >> SJA1000_TIME_SEG1_S) + + 1; + bt->bt_tseg2 + = ((timing1 & SJA1000_TIME_SEG2_M) >> SJA1000_TIME_SEG2_S) + + 1; + bt->bt_baud = config->clk_freq + / (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); + + cantrace("Retrieved baud rate. TS1: %" PRId8 " TS2: %" PRId8 + " BRP: %" PRId32 "\n", + bt->bt_tseg1, bt->bt_tseg2, brp); + cantrace("timing0: 0x%" PRIx32 ", timing1: 0x%" PRIx32 " Baud: " + "%" PRId32 + "\n", + timing0, timing1, bt->bt_baud); + + ret = OK; + } + break; + + /* Unsupported/unrecognized command */ + + default: + canerr("ERROR: Unrecognized command: %04x\n", cmd); + break; + } + + return ret; +} + +static int sja1000_remoterequest(struct can_dev_s *dev, uint16_t id) +{ + canwarn("Remote request not implemented\n"); + return -ENOSYS; +} + +/**************************************************************************** + * Name: sja1000_send + * + * Description: + * Send one SJA1000 message. + * + * One SJA1000-message consists of a maximum of 10 bytes. A message is + * composed of at least the first 2 bytes (when there are no data bytes). + * + * Byte 0: Bits 0-7: Bits 3-10 of the 11-bit SJA1000 identifier + * Byte 1: Bits 5-7: Bits 0-2 of the 11-bit SJA1000 identifier + * Bit 4: Remote Transmission Request (RTR) + * Bits 0-3: Data Length Code (DLC) + * Bytes 2-10: SJA1000 data + * + * Input Parameters: + * dev - An instance of the "upper half" CAN driver state structure. + * msg - A message to send. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int sja1000_send(struct can_dev_s *dev, struct can_msg_s *msg) +{ + struct sja1000_dev_s *priv = (struct sja1000_dev_s *)dev->cd_priv; + struct sja1000_config_s *config = priv->config; + uint32_t regval; + uint32_t i; + uint32_t len; + uint32_t id; + uint32_t frame_info; + irqstate_t flags; + uint8_t port = config->port; + int ret = OK; + + cantrace("SJA1000 (%" PRIu8 ") ID: %" PRIu32 " DLC: %" PRIu8 "\n", port, + (uint32_t)msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc); + + len = (uint32_t)msg->cm_hdr.ch_dlc; + if (len > CAN_MAXDATALEN) + len = CAN_MAXDATALEN; + + frame_info = len; + + if (msg->cm_hdr.ch_rtr) + { + frame_info |= (1 << 6); + } + +#ifdef CONFIG_ARCH_HAVE_MULTICPU + flags = spin_lock_irqsave(&priv->lock); +#else + flags = enter_critical_section(); +#endif /* CONFIG_ARCH_HAVE_MULTICPU */ + + /* Make sure that TX interrupts are enabled BEFORE sending the + * message. + * + * NOTE: The INT_ENA is also modified from the interrupt handler, but the + * following is safe because interrupts are disabled here. + */ + + regval = sja1000_getreg(priv, SJA1000_INT_ENA_REG); + regval |= SJA1000_TX_INT_ENA_M; + sja1000_putreg(priv, SJA1000_INT_ENA_REG, regval); + + /* Set up the transfer */ + +#ifdef CONFIG_CAN_EXTID + if (msg->cm_hdr.ch_extid) + { + /* The provided ID should be 29 bits */ + + id = (uint32_t)msg->cm_hdr.ch_id; + DEBUGASSERT((id & ~CAN_MAX_EXTMSGID) == 0); + frame_info |= (1 << 7); + sja1000_putreg(priv, SJA1000_DATA_0_REG, frame_info); + + id <<= 3; + sja1000_putreg(priv, SJA1000_DATA_4_REG, id & 0xff); + id >>= 8; + sja1000_putreg(priv, SJA1000_DATA_3_REG, id & 0xff); + id >>= 8; + sja1000_putreg(priv, SJA1000_DATA_2_REG, id & 0xff); + id >>= 8; + sja1000_putreg(priv, SJA1000_DATA_1_REG, id & 0xff); + for (i = 0; i < len; i++) + { + sja1000_putreg(priv, + (SJA1000_DATA_5_REG + i), msg->cm_data[i]); + } + } + else +#endif + { + /* The provided ID should be 11 bits */ + + id = (uint32_t)msg->cm_hdr.ch_id; + DEBUGASSERT((id & ~CAN_MAX_STDMSGID) == 0); + sja1000_putreg(priv, SJA1000_DATA_0_REG, frame_info); + id <<= 5; + sja1000_putreg(priv, SJA1000_DATA_1_REG, (id >> 8) & 0xff); + sja1000_putreg(priv, SJA1000_DATA_2_REG, id & 0xff); + for (i = 0; i < len; i++) + { + sja1000_putreg(priv, + (SJA1000_DATA_3_REG + i), msg->cm_data[i]); + } + } + + /* Send the message */ + + if (config->loopback) + { + sja1000_putreg(priv, SJA1000_CMD_REG, + SJA1000_SELF_RX_REQ_M | SJA1000_ABORT_TX_M); + } + else + { + sja1000_putreg(priv, SJA1000_CMD_REG, SJA1000_TX_REQ_M); + } + +#ifdef CONFIG_ARCH_HAVE_MULTICPU + spin_unlock_irqrestore(&priv->lock, flags); +#else + leave_critical_section(flags); +#endif /* CONFIG_ARCH_HAVE_MULTICPU */ + + return ret; +} + +/**************************************************************************** + * Name: sja1000_txready + * + * Description: + * Return true if the SJA1000 hardware can accept another TX message. + * + * Input Parameters: + * dev - An instance of the "upper half" CAN driver state structure. + * + * Returned Value: + * True if the SJA1000 hardware is ready to accept another TX message. + * + ****************************************************************************/ + +static bool sja1000_txready(struct can_dev_s *dev) +{ + struct sja1000_dev_s *priv = dev->cd_priv; + struct sja1000_config_s *config = priv->config; + uint8_t port = config->port; + uint32_t regval = sja1000_getreg(priv, SJA1000_STATUS_REG); + + caninfo("SJA1000 (%" PRIu8 ") txready: %d\n", port, + ((regval & SJA1000_TX_BUF_ST_M) != 0)); + return ((regval & SJA1000_TX_BUF_ST_M) != 0); +} + +/**************************************************************************** + * Name: sja1000_txempty + * + * Description: + * Return true if all message have been sent. If for example, the SJA1000 + * hardware implements FIFOs, then this would mean the transmit FIFO is + * empty. This method is called when the driver needs to make sure that + * all characters are "drained" from the TX hardware before calling + * co_shutdown(). + * + * Input Parameters: + * dev - An instance of the "upper half" CAN driver state structure. + * + * Returned Value: + * True if there are no pending TX transfers in the SJA1000 hardware. + * + ****************************************************************************/ + +static bool sja1000_txempty(struct can_dev_s *dev) +{ + struct sja1000_dev_s *priv = dev->cd_priv; + struct sja1000_config_s *config = priv->config; + uint8_t port = config->port; + uint32_t regval = sja1000_getreg(priv, SJA1000_STATUS_REG); + + caninfo("SJA1000 (%" PRIu8 ") txempty: %d\n", port, + ((regval & SJA1000_TX_BUF_ST_M) != 0)); + return ((regval & SJA1000_TX_BUF_ST_M) != 0); +} + +/**************************************************************************** + * Name: sja1000_interrupt + * + * Description: + * SJA1000 RX/TX interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * arg - The pointer to driver structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int sja1000_interrupt(FAR struct sja1000_config_s *config, void *arg) +{ +#ifdef CONFIG_CAN_SJA1000 + struct can_dev_s *dev = (struct can_dev_s *)arg; + struct sja1000_dev_s *priv = dev->cd_priv; + struct can_hdr_s hdr; + uint8_t data[8]; + uint32_t frame_info; + uint32_t len; + uint32_t datastart; + uint32_t regval; + uint32_t i; + + /* Read the interrupt register results in clearing bits */ + + regval = sja1000_getreg(priv, SJA1000_INT_RAW_REG); + + cantrace("Entered. Regval = 0x%" PRIx32 "\n", regval); + + /* Check for a receive interrupt */ + + if ((regval & SJA1000_RX_INT_ST_M) != 0) + { + memset(&hdr, 0, sizeof(hdr)); + memset(data, 0, sizeof(data)); + + frame_info = sja1000_getreg(priv, SJA1000_DATA_0_REG); + + /* Construct the SJA1000 header */ + + if (frame_info & (1 << 6)) + { + hdr.ch_rtr = 1; + } + +#ifdef CONFIG_CAN_EXTID + if (frame_info & (1 << 7)) + { + /* The provided ID should be 29 bits */ + + hdr.ch_extid = 1; + hdr.ch_id = (sja1000_getreg(priv, SJA1000_DATA_1_REG) << 21) + + (sja1000_getreg(priv, SJA1000_DATA_2_REG) << 13) + + (sja1000_getreg(priv, SJA1000_DATA_3_REG) << 5) + + (sja1000_getreg(priv, SJA1000_DATA_4_REG) >> 3); + datastart = SJA1000_DATA_5_REG; + } + else +#endif /* CONFIG_CAN_EXTID */ + { + /* The provided ID should be 11 bits */ + + hdr.ch_id = (sja1000_getreg(priv, SJA1000_DATA_1_REG) << 3) + + (sja1000_getreg(priv, SJA1000_DATA_2_REG) >> 5); + datastart = SJA1000_DATA_3_REG; + } + + len = frame_info & 0xf; + if (len > CAN_MAXDATALEN) + { + len = CAN_MAXDATALEN; + } + + hdr.ch_dlc = len; + + for (i = 0; i < len; i++) + { + data[i] = sja1000_getreg(priv, (datastart + i)); + } + + /* Release the receive buffer */ + + sja1000_putreg(priv, SJA1000_CMD_REG, SJA1000_RELEASE_BUF_M); + +#ifdef CONFIG_CAN_ERRORS + hdr.ch_error = 0; /* Error reporting not supported */ +#endif /* CONFIG_CAN_ERRORS */ + can_receive(dev, &hdr, data); + } + + /* Check for TX buffer complete */ + + if ((regval & SJA1000_TX_INT_ST_M) != 0) + { + /* Disable all further TX buffer interrupts */ + + regval = sja1000_getreg(priv, SJA1000_INT_ENA_REG); + regval &= ~SJA1000_TX_INT_ENA_M; + sja1000_putreg(priv, SJA1000_INT_ENA_REG, regval); + + /* Indicate that the TX is done and a new TX buffer is available */ + + can_txdone(dev); + } + +#endif /* CONFIG_CAN_SJA1000 */ + return OK; +} + +/**************************************************************************** + * Name: sja1000_set_acc_filter + * + * Description: + * Call to set acceptance filter. + * Must be called in reset mode. + * + * Input Parameters: + * priv - Private SJA1000 context + * code - Acceptance Code. + * mask - Acceptance Mask. + * single_filter - Whether to enable single filter mode. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void sja1000_set_acc_filter(struct sja1000_dev_s *priv, + uint32_t code, uint32_t mask, + bool single_filter) +{ + uint32_t regval; + uint32_t code_swapped = __builtin_bswap32(code); + uint32_t mask_swapped = __builtin_bswap32(mask); + + regval = sja1000_getreg(priv, SJA1000_MODE_REG); + if (single_filter) + { + regval |= SJA1000_RX_FILTER_MODE_M; + } + else + { + regval &= ~(SJA1000_RX_FILTER_MODE_M); + } + + sja1000_putreg(priv, SJA1000_MODE_REG, regval); + + for (int i = 0; i < 4; i++) + { + sja1000_putreg(priv, (SJA1000_DATA_0_REG + i), + ((code_swapped >> (i * 8)) & 0xff)); + sja1000_putreg(priv, (SJA1000_DATA_4_REG + i), + ((mask_swapped >> (i * 8)) & 0xff)); + } +} + +/**************************************************************************** + * Name: sja1000_baud_rate + * + * Description: + * Set the CAN bus timing registers based on the configured bit-rate and + * sample point position. + * + * The bit timing logic monitors the serial bus-line and performs sampling + * and adjustment of the sample point by synchronizing on the start-bit edge + * and resynchronizing on the following edges. + * + * Its operation may be explained simply by splitting nominal bit time into + * three segments as follows: + * + * 1. Synchronization segment (SYNC_SEG): a bit change is expected to occur + * within this time segment. It has a fixed length of one time quantum + * (1 x tCAN). + * 2. Bit segment 1 (BS1): defines the location of the sample point. It + * includes the PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration + * is programmable between 1 and 16 time quanta but may be automatically + * lengthened to compensate for positive phase drifts due to differences + * in the frequency of the various nodes of the network. + * 3. Bit segment 2 (BS2): defines the location of the transmit point. It + * represents the PHASE_SEG2 of the CAN standard. Its duration is + * programmable between 1 and 8 time quanta but may also be automatically + * shortened to compensate for negative phase drifts. + * + * Pictorially: + * + * |<----------------- NOMINAL BIT TIME ----------------->| + * |<- SYNC_SEG ->|<------ BS1 ------>|<------ BS2 ------>| + * |<---- Tq ---->|<----- Tbs1 ------>|<----- Tbs2 ------>| + * + * Where + * Tbs1 is the duration of the BS1 segment + * Tbs2 is the duration of the BS2 segment + * Tq is the "Time Quantum" + * + * Relationships: + * + * baud = 1 / bit_time + * bit_time = Tq + Tbs1 + Tbs2 + * Tbs1 = Tq * ts1 + * Tbs2 = Tq * ts2 + * Tq = brp * Tcan + * + * Where: + * Tcan is the period of the APB clock + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int sja1000_baud_rate(struct sja1000_dev_s *priv, int rate, + int clock, int sjw, int sampl_pt, int flags) +{ + struct sja1000_config_s *config = priv->config; + const struct can_bittiming_const_s *timing = config->bittiming_const; + int best_error = 1000000000; + int error; + int best_tseg = 0; + int best_brp = 0; + int best_rate = 0; + int brp = 0; + int tseg = 0; + int tseg1 = 0; + int tseg2 = 0; + uint32_t timing0; + uint32_t timing1; + + /* tseg even = round down, odd = round up */ + + for (tseg = (0 + 0 + 2) * 2; + tseg <= (timing->tseg2_max + timing->tseg1_max + 2) * 2 + 1; tseg++) + { + brp = clock / ((1 + tseg / 2) * rate) + tseg % 2; + if (brp == 0 || brp > 64) + { + continue; + } + + error = rate - clock / (brp * (1 + tseg / 2)); + if (error < 0) + { + error = -error; + } + + if (error <= best_error) + { + best_error = error; + best_tseg = tseg / 2; + best_brp = brp; + best_rate = clock / (brp * (1 + tseg / 2)); + } + } + + if (best_error && (rate / best_error < 10)) + { + canerr( + "baud rate %d is not possible with %d Hz clock\n", rate, clock); + canerr("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n", + best_rate, best_brp, best_tseg, tseg1, tseg2); + return -EINVAL; + } + + tseg2 = best_tseg - (sampl_pt * (best_tseg + 1)) / 100 + 1; + if (tseg2 < 0) + { + tseg2 = 0; + } + + if (tseg2 > timing->tseg2_max) + { + tseg2 = timing->tseg2_max; + } + + tseg1 = best_tseg - tseg2; + if (tseg1 > timing->tseg1_max) + { + tseg1 = timing->tseg1_max; + tseg2 = best_tseg - tseg1; + } + + caninfo("Setting baud rate. TS1: %d TS2: %d BRP: %d\n", tseg1, tseg2, + best_brp); + + /* Configure bit timing */ + + timing0 = ((best_brp - 1) / 2) & SJA1000_BAUD_PRESC_M; + timing0 |= ((sjw - 1) << SJA1000_SYNC_JUMP_WIDTH_S) + & SJA1000_SYNC_JUMP_WIDTH_M; + timing1 = (tseg1 - 1) & SJA1000_TIME_SEG1_M; + timing1 |= ((tseg2 - 1) << SJA1000_TIME_SEG2_S) & SJA1000_TIME_SEG2_M; + + if (config->triple_sample) + { + /* The bus is sampled 3 times (recommended for low to medium speed + * buses to spikes on the bus-line). + */ + + timing1 |= (config->triple_sample << SJA1000_TIME_SAMP_S) + & SJA1000_TIME_SAMP_M; + } + + cantrace("Writing to BTR0, BTR1: timing0: 0x%" PRIx32 " timing1: " + "0x%" PRIx32 "\n", + timing0, timing1); + + sja1000_putreg(priv, SJA1000_BUS_TIMING_1_REG, timing1); + sja1000_putreg(priv, SJA1000_BUS_TIMING_0_REG, timing0); + +#ifdef CONFIG_CANBUS_REGDEBUG + timing1 = sja1000_getreg(priv, SJA1000_BUS_TIMING_1_REG); + timing0 = sja1000_getreg(priv, SJA1000_BUS_TIMING_0_REG); + caninfo("Read-verify: timing0: 0x%" PRIx32 " timing1: 0x%" PRIx32 "\n", + timing0, timing1); +#endif /* CONFIG_CANBUS_REGDEBUG */ + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sja1000_instantiate + * + * Description: + * Initialize the selected SJA1000 CAN Bus Controller + * + * Input Parameters: + * priv - An instance of the "lower half" CAN driver state structure. + * + * Returned Value: + * Valid CAN device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +FAR struct can_dev_s *sja1000_instantiate(FAR struct sja1000_dev_s *priv) +{ + struct sja1000_config_s *config = priv->config; + FAR struct can_dev_s *dev; + irqstate_t flags; + + DEBUGASSERT(dev); + DEBUGASSERT(priv); + DEBUGASSERT(config); + + cantrace("Starting sja1000_instantiate()!\n"); + + /* Allocate a CAN Device structure */ + + dev = kmm_zalloc(sizeof(struct can_dev_s)); + if (dev == NULL) + { + canerr("ERROR: Failed to allocate instance of can_dev_s!\n"); + return NULL; + } + +#ifdef CONFIG_ARCH_HAVE_MULTICPU + flags = spin_lock_irqsave(&priv->lock); +#else + flags = enter_critical_section(); +#endif /* CONFIG_ARCH_HAVE_MULTICPU */ + +#ifdef CONFIG_ARCH_HAVE_MULTICPU + priv->lock = SP_UNLOCKED; +#endif /* CONFIG_ARCH_HAVE_MULTICPU */ + + dev->cd_ops = &g_sja1000ops; + dev->cd_priv = (FAR void *)priv; + +#ifdef CONFIG_ARCH_HAVE_MULTICPU + spin_unlock_irqrestore(&priv->lock, flags); +#else + leave_critical_section(flags); +#endif /* CONFIG_ARCH_HAVE_MULTICPU */ + + /* Reset chip */ + + sja1000_reset(dev); + + return dev; +} + +#endif /* CONFIG_CAN_SJA1000 */ diff --git a/drivers/can/sja1000.h b/drivers/can/sja1000.h new file mode 100644 index 0000000000000..ee156b88408fe --- /dev/null +++ b/drivers/can/sja1000.h @@ -0,0 +1,911 @@ +/**************************************************************************** + * drivers/can/sja1000.h + * + * SJA1000 CAN driver based on esp32c3_twai.h + * + * License header retained from original source. + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __DRIVERS_CAN_SJA1000_H +#define __DRIVERS_CAN_SJA1000_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Default interrupts - Exclude data overrun (bit[3]) and brp_div (bit[4]) + */ + +#define SJA1000_DEFAULT_INTERRUPTS 0xe7 + +/* Number of standard/extended filters */ + +#define SJA1000_NFILTERS 1 + +/* SJA1000_MODE_REG register + * Mode Register + */ + +#define SJA1000_MODE_REG (0x00) + +/* SJA1000_RX_FILTER_MODE : R/W; bitpos: [3]; default: 0; + * This bit is used to configure the filter mode. 0: Dual filter mode; 1: + * Single filter mode. + */ + +#define SJA1000_RX_FILTER_MODE (BIT(3)) +#define SJA1000_RX_FILTER_MODE_M \ + (SJA1000_RX_FILTER_MODE_V << SJA1000_RX_FILTER_MODE_S) +#define SJA1000_RX_FILTER_MODE_V 0x00000001 +#define SJA1000_RX_FILTER_MODE_S 3 + +/* SJA1000_SELF_TEST_MODE : R/W; bitpos: [2]; default: 0; + * 1: Self test mode. In this mode the TX nodes can perform a successful + * transmission without receiving the acknowledge signal. This mode is often + * used to test a single node with the self reception request command. + */ + +#define SJA1000_SELF_TEST_MODE (BIT(2)) +#define SJA1000_SELF_TEST_MODE_M \ + (SJA1000_SELF_TEST_MODE_V << SJA1000_SELF_TEST_MODE_S) +#define SJA1000_SELF_TEST_MODE_V 0x00000001 +#define SJA1000_SELF_TEST_MODE_S 2 + +/* SJA1000_LISTEN_ONLY_MODE : R/W; bitpos: [1]; default: 0; + * 1: Listen only mode. In this mode the nodes will only receive messages + * from the bus, without generating the acknowledge signal nor updating the + * RX error counter. + */ + +#define SJA1000_LISTEN_ONLY_MODE (BIT(1)) +#define SJA1000_LISTEN_ONLY_MODE_M \ + (SJA1000_LISTEN_ONLY_MODE_V << SJA1000_LISTEN_ONLY_MODE_S) +#define SJA1000_LISTEN_ONLY_MODE_V 0x00000001 +#define SJA1000_LISTEN_ONLY_MODE_S 1 + +/* SJA1000_RESET_MODE : R/W; bitpos: [0]; default: 1; + * This bit is used to configure the operating mode of the SJA1000 + * Controller. 1: Reset mode; 0: Operating mode. + */ + +#define SJA1000_RESET_MODE (BIT(0)) +#define SJA1000_RESET_MODE_M (SJA1000_RESET_MODE_V << SJA1000_RESET_MODE_S) +#define SJA1000_RESET_MODE_V 0x00000001 +#define SJA1000_RESET_MODE_S 0 + +/* SJA1000_CMD_REG register + * Command Register + */ + +#define SJA1000_CMD_REG (0x01) + +/* SJA1000_SELF_RX_REQ : WO; bitpos: [4]; default: 0; + * Self reception request command. Set the bit to 1 to allow a message be + * transmitted and received simultaneously. + */ + +#define SJA1000_SELF_RX_REQ (BIT(4)) +#define SJA1000_SELF_RX_REQ_M \ + (SJA1000_SELF_RX_REQ_V << SJA1000_SELF_RX_REQ_S) +#define SJA1000_SELF_RX_REQ_V 0x00000001 +#define SJA1000_SELF_RX_REQ_S 4 + +/* SJA1000_CLR_OVERRUN : WO; bitpos: [3]; default: 0; + * Set the bit to 1 to clear the data overrun status bit. + */ + +#define SJA1000_CLR_OVERRUN (BIT(3)) +#define SJA1000_CLR_OVERRUN_M \ + (SJA1000_CLR_OVERRUN_V << SJA1000_CLR_OVERRUN_S) +#define SJA1000_CLR_OVERRUN_V 0x00000001 +#define SJA1000_CLR_OVERRUN_S 3 + +/* SJA1000_RELEASE_BUF : WO; bitpos: [2]; default: 0; + * Set the bit to 1 to release the RX buffer. + */ + +#define SJA1000_RELEASE_BUF (BIT(2)) +#define SJA1000_RELEASE_BUF_M \ + (SJA1000_RELEASE_BUF_V << SJA1000_RELEASE_BUF_S) +#define SJA1000_RELEASE_BUF_V 0x00000001 +#define SJA1000_RELEASE_BUF_S 2 + +/* SJA1000_ABORT_TX : WO; bitpos: [1]; default: 0; + * Set the bit to 1 to cancel a pending transmission request. + */ + +#define SJA1000_ABORT_TX (BIT(1)) +#define SJA1000_ABORT_TX_M (SJA1000_ABORT_TX_V << SJA1000_ABORT_TX_S) +#define SJA1000_ABORT_TX_V 0x00000001 +#define SJA1000_ABORT_TX_S 1 + +/* SJA1000_TX_REQ : WO; bitpos: [0]; default: 0; + * Set the bit to 1 to allow the driving nodes start transmission. + */ + +#define SJA1000_TX_REQ (BIT(0)) +#define SJA1000_TX_REQ_M (SJA1000_TX_REQ_V << SJA1000_TX_REQ_S) +#define SJA1000_TX_REQ_V 0x00000001 +#define SJA1000_TX_REQ_S 0 + +/* SJA1000_STATUS_REG register + * Status register + */ + +#define SJA1000_STATUS_REG (0x02) + +/* SJA1000_MISS_ST : RO; bitpos: [8]; default: 0; + * This bit reflects whether the data packet in the RX FIFO is complete. 1: + * The current packet is missing; 0: The current packet is complete + */ + +#define SJA1000_MISS_ST (BIT(8)) +#define SJA1000_MISS_ST_M (SJA1000_MISS_ST_V << SJA1000_MISS_ST_S) +#define SJA1000_MISS_ST_V 0x00000001 +#define SJA1000_MISS_ST_S 8 + +/* SJA1000_BUS_OFF_ST : RO; bitpos: [7]; default: 0; + * 1: In bus-off status, the SJA1000 Controller is no longer involved in bus + * activities. + */ + +#define SJA1000_BUS_OFF_ST (BIT(7)) +#define SJA1000_BUS_OFF_ST_M (SJA1000_BUS_OFF_ST_V << SJA1000_BUS_OFF_ST_S) +#define SJA1000_BUS_OFF_ST_V 0x00000001 +#define SJA1000_BUS_OFF_ST_S 7 + +/* SJA1000_ERR_ST : RO; bitpos: [6]; default: 0; + * 1: At least one of the RX/TX error counter has reached or exceeded the + * value set in register SJA1000_ERR_WARNING_LIMIT_REG. + */ + +#define SJA1000_ERR_ST (BIT(6)) +#define SJA1000_ERR_ST_M (SJA1000_ERR_ST_V << SJA1000_ERR_ST_S) +#define SJA1000_ERR_ST_V 0x00000001 +#define SJA1000_ERR_ST_S 6 + +/* SJA1000_TX_ST : RO; bitpos: [5]; default: 0; + * 1: The SJA1000 Controller is transmitting a message to the bus. + */ + +#define SJA1000_TX_ST (BIT(5)) +#define SJA1000_TX_ST_M (SJA1000_TX_ST_V << SJA1000_TX_ST_S) +#define SJA1000_TX_ST_V 0x00000001 +#define SJA1000_TX_ST_S 5 + +/* SJA1000_RX_ST : RO; bitpos: [4]; default: 0; + * 1: The SJA1000 Controller is receiving a message from the bus. + */ + +#define SJA1000_RX_ST (BIT(4)) +#define SJA1000_RX_ST_M (SJA1000_RX_ST_V << SJA1000_RX_ST_S) +#define SJA1000_RX_ST_V 0x00000001 +#define SJA1000_RX_ST_S 4 + +/* SJA1000_TX_COMPLETE : RO; bitpos: [3]; default: 0; + * 1: The SJA1000 controller has successfully received a packet from the + * bus. + */ + +#define SJA1000_TX_COMPLETE (BIT(3)) +#define SJA1000_TX_COMPLETE_M \ + (SJA1000_TX_COMPLETE_V << SJA1000_TX_COMPLETE_S) +#define SJA1000_TX_COMPLETE_V 0x00000001 +#define SJA1000_TX_COMPLETE_S 3 + +/* SJA1000_TX_BUF_ST : RO; bitpos: [2]; default: 0; + * 1: The TX buffer is empty, the CPU may write a message into it. + */ + +#define SJA1000_TX_BUF_ST (BIT(2)) +#define SJA1000_TX_BUF_ST_M (SJA1000_TX_BUF_ST_V << SJA1000_TX_BUF_ST_S) +#define SJA1000_TX_BUF_ST_V 0x00000001 +#define SJA1000_TX_BUF_ST_S 2 + +/* SJA1000_OVERRUN_ST : RO; bitpos: [1]; default: 0; + * 1: The RX FIFO is full and data overrun has occurred. + */ + +#define SJA1000_OVERRUN_ST (BIT(1)) +#define SJA1000_OVERRUN_ST_M (SJA1000_OVERRUN_ST_V << SJA1000_OVERRUN_ST_S) +#define SJA1000_OVERRUN_ST_V 0x00000001 +#define SJA1000_OVERRUN_ST_S 1 + +/* SJA1000_RX_BUF_ST : RO; bitpos: [0]; default: 0; + * 1: The data in the RX buffer is not empty, with at least one received + * data packet. + */ + +#define SJA1000_RX_BUF_ST (BIT(0)) +#define SJA1000_RX_BUF_ST_M (SJA1000_RX_BUF_ST_V << SJA1000_RX_BUF_ST_S) +#define SJA1000_RX_BUF_ST_V 0x00000001 +#define SJA1000_RX_BUF_ST_S 0 + +/* SJA1000_INT_RAW_REG register + * Interrupt Register + */ + +#define SJA1000_INT_RAW_REG (0x03) + +/* SJA1000_BUS_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * Error interrupt. If this bit is set to 1, it indicates an error is + * detected on the bus. + */ + +#define SJA1000_BUS_ERR_INT_ST (BIT(7)) +#define SJA1000_BUS_ERR_INT_ST_M \ + (SJA1000_BUS_ERR_INT_ST_V << SJA1000_BUS_ERR_INT_ST_S) +#define SJA1000_BUS_ERR_INT_ST_V 0x00000001 +#define SJA1000_BUS_ERR_INT_ST_S 7 + +/* SJA1000_ARB_LOST_INT_ST : RO; bitpos: [6]; default: 0; + * Arbitration lost interrupt. If this bit is set to 1, it indicates an + * arbitration lost interrupt is generated. + */ + +#define SJA1000_ARB_LOST_INT_ST (BIT(6)) +#define SJA1000_ARB_LOST_INT_ST_M \ + (SJA1000_ARB_LOST_INT_ST_V << SJA1000_ARB_LOST_INT_ST_S) +#define SJA1000_ARB_LOST_INT_ST_V 0x00000001 +#define SJA1000_ARB_LOST_INT_ST_S 6 + +/* SJA1000_ERR_PASSIVE_INT_ST : RO; bitpos: [5]; default: 0; + * Error passive interrupt. If this bit is set to 1, it indicates the + * SJA1000 Controller is switched between error active status and error + * passive status due to the change of error counters. + */ + +#define SJA1000_ERR_PASSIVE_INT_ST (BIT(5)) +#define SJA1000_ERR_PASSIVE_INT_ST_M \ + (SJA1000_ERR_PASSIVE_INT_ST_V << SJA1000_ERR_PASSIVE_INT_ST_S) +#define SJA1000_ERR_PASSIVE_INT_ST_V 0x00000001 +#define SJA1000_ERR_PASSIVE_INT_ST_S 5 + +/* SJA1000_OVERRUN_INT_ST : RO; bitpos: [3]; default: 0; + * Data overrun interrupt. If this bit is set to 1, it indicates a data + * overrun interrupt is generated in the RX FIFO. + */ + +#define SJA1000_OVERRUN_INT_ST (BIT(3)) +#define SJA1000_OVERRUN_INT_ST_M \ + (SJA1000_OVERRUN_INT_ST_V << SJA1000_OVERRUN_INT_ST_S) +#define SJA1000_OVERRUN_INT_ST_V 0x00000001 +#define SJA1000_OVERRUN_INT_ST_S 3 + +/* SJA1000_ERR_WARN_INT_ST : RO; bitpos: [2]; default: 0; + * Error warning interrupt. If this bit is set to 1, it indicates the error + * status signal and the bus-off status signal of Status register have + * changed (e.g., switched from 0 to 1 or from 1 to 0). + */ + +#define SJA1000_ERR_WARN_INT_ST (BIT(2)) +#define SJA1000_ERR_WARN_INT_ST_M \ + (SJA1000_ERR_WARN_INT_ST_V << SJA1000_ERR_WARN_INT_ST_S) +#define SJA1000_ERR_WARN_INT_ST_V 0x00000001 +#define SJA1000_ERR_WARN_INT_ST_S 2 + +/* SJA1000_TX_INT_ST : RO; bitpos: [1]; default: 0; + * Transmit interrupt. If this bit is set to 1, it indicates the message + * transmitting mis- sion is finished and a new transmission is able to + * execute. + */ + +#define SJA1000_TX_INT_ST (BIT(1)) +#define SJA1000_TX_INT_ST_M (SJA1000_TX_INT_ST_V << SJA1000_TX_INT_ST_S) +#define SJA1000_TX_INT_ST_V 0x00000001 +#define SJA1000_TX_INT_ST_S 1 + +/* SJA1000_RX_INT_ST : RO; bitpos: [0]; default: 0; + * Receive interrupt. If this bit is set to 1, it indicates there are + * messages to be handled in the RX FIFO. + */ + +#define SJA1000_RX_INT_ST (BIT(0)) +#define SJA1000_RX_INT_ST_M (SJA1000_RX_INT_ST_V << SJA1000_RX_INT_ST_S) +#define SJA1000_RX_INT_ST_V 0x00000001 +#define SJA1000_RX_INT_ST_S 0 + +/* SJA1000_INT_ENA_REG register + * Interrupt Enable Register + */ + +#define SJA1000_INT_ENA_REG (0x04) + +/* SJA1000_BUS_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * Set this bit to 1 to enable error interrupt. + */ + +#define SJA1000_BUS_ERR_INT_ENA (BIT(7)) +#define SJA1000_BUS_ERR_INT_ENA_M \ + (SJA1000_BUS_ERR_INT_ENA_V << SJA1000_BUS_ERR_INT_ENA_S) +#define SJA1000_BUS_ERR_INT_ENA_V 0x00000001 +#define SJA1000_BUS_ERR_INT_ENA_S 7 + +/* SJA1000_ARB_LOST_INT_ENA : R/W; bitpos: [6]; default: 0; + * Set this bit to 1 to enable arbitration lost interrupt. + */ + +#define SJA1000_ARB_LOST_INT_ENA (BIT(6)) +#define SJA1000_ARB_LOST_INT_ENA_M \ + (SJA1000_ARB_LOST_INT_ENA_V << SJA1000_ARB_LOST_INT_ENA_S) +#define SJA1000_ARB_LOST_INT_ENA_V 0x00000001 +#define SJA1000_ARB_LOST_INT_ENA_S 6 + +/* SJA1000_ERR_PASSIVE_INT_ENA : R/W; bitpos: [5]; default: 0; + * Set this bit to 1 to enable error passive interrupt. + */ + +#define SJA1000_ERR_PASSIVE_INT_ENA (BIT(5)) +#define SJA1000_ERR_PASSIVE_INT_ENA_M \ + (SJA1000_ERR_PASSIVE_INT_ENA_V << SJA1000_ERR_PASSIVE_INT_ENA_S) +#define SJA1000_ERR_PASSIVE_INT_ENA_V 0x00000001 +#define SJA1000_ERR_PASSIVE_INT_ENA_S 5 + +/* SJA1000_OVERRUN_INT_ENA : R/W; bitpos: [3]; default: 0; + * Set this bit to 1 to enable data overrun interrupt. + */ + +#define SJA1000_OVERRUN_INT_ENA (BIT(3)) +#define SJA1000_OVERRUN_INT_ENA_M \ + (SJA1000_OVERRUN_INT_ENA_V << SJA1000_OVERRUN_INT_ENA_S) +#define SJA1000_OVERRUN_INT_ENA_V 0x00000001 +#define SJA1000_OVERRUN_INT_ENA_S 3 + +/* SJA1000_ERR_WARN_INT_ENA : R/W; bitpos: [2]; default: 0; + * Set this bit to 1 to enable error warning interrupt. + */ + +#define SJA1000_ERR_WARN_INT_ENA (BIT(2)) +#define SJA1000_ERR_WARN_INT_ENA_M \ + (SJA1000_ERR_WARN_INT_ENA_V << SJA1000_ERR_WARN_INT_ENA_S) +#define SJA1000_ERR_WARN_INT_ENA_V 0x00000001 +#define SJA1000_ERR_WARN_INT_ENA_S 2 + +/* SJA1000_TX_INT_ENA : R/W; bitpos: [1]; default: 0; + * Set this bit to 1 to enable transmit interrupt. + */ + +#define SJA1000_TX_INT_ENA (BIT(1)) +#define SJA1000_TX_INT_ENA_M (SJA1000_TX_INT_ENA_V << SJA1000_TX_INT_ENA_S) +#define SJA1000_TX_INT_ENA_V 0x00000001 +#define SJA1000_TX_INT_ENA_S 1 + +/* SJA1000_RX_INT_ENA : R/W; bitpos: [0]; default: 0; + * Set this bit to 1 to enable receive interrupt. + */ + +#define SJA1000_RX_INT_ENA (BIT(0)) +#define SJA1000_RX_INT_ENA_M (SJA1000_RX_INT_ENA_V << SJA1000_RX_INT_ENA_S) +#define SJA1000_RX_INT_ENA_V 0x00000001 +#define SJA1000_RX_INT_ENA_S 0 + +/* SJA1000_BUS_TIMING_0_REG register + * Bus Timing Register 0 + */ + +#define SJA1000_BUS_TIMING_0_REG (0x06) + +/* SJA1000_SYNC_JUMP_WIDTH : RO | R/W; bitpos: [7:6]; default: 0; + * Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. + */ + +#define SJA1000_SYNC_JUMP_WIDTH 0x00000003 +#define SJA1000_SYNC_JUMP_WIDTH_M \ + (SJA1000_SYNC_JUMP_WIDTH_V << SJA1000_SYNC_JUMP_WIDTH_S) +#define SJA1000_SYNC_JUMP_WIDTH_V 0x00000003 +#define SJA1000_SYNC_JUMP_WIDTH_S 6 + +/* SJA1000_BAUD_PRESC : RO | R/W; bitpos: [5:0]; default: 0; + * Baud Rate Prescaler, determines the frequency dividing ratio. + */ + +#define SJA1000_BAUD_PRESC 0x0000003F +#define SJA1000_BAUD_PRESC_M (SJA1000_BAUD_PRESC_V << SJA1000_BAUD_PRESC_S) +#define SJA1000_BAUD_PRESC_V 0x0000003F +#define SJA1000_BAUD_PRESC_S 0 + +/* SJA1000_BUS_TIMING_1_REG register + * Bus Timing Register 1 + */ + +#define SJA1000_BUS_TIMING_1_REG (0x07) + +/* SJA1000_TIME_SAMP : RO | R/W; bitpos: [7]; default: 0; + * The number of sample points. 0: the bus is sampled once; 1: the bus is + * sampled three times + */ + +#define SJA1000_TIME_SAMP (BIT(7)) +#define SJA1000_TIME_SAMP_M (SJA1000_TIME_SAMP_V << SJA1000_TIME_SAMP_S) +#define SJA1000_TIME_SAMP_V 0x00000001 +#define SJA1000_TIME_SAMP_S 7 + +/* SJA1000_TIME_SEG2 : RO | R/W; bitpos: [6:4]; default: 0; + * The width of PBS2. + */ + +#define SJA1000_TIME_SEG2 0x00000007 +#define SJA1000_TIME_SEG2_M (SJA1000_TIME_SEG2_V << SJA1000_TIME_SEG2_S) +#define SJA1000_TIME_SEG2_V 0x00000007 +#define SJA1000_TIME_SEG2_S 4 + +/* SJA1000_TIME_SEG1 : RO | R/W; bitpos: [3:0]; default: 0; + * The width of PBS1. + */ + +#define SJA1000_TIME_SEG1 0x0000000F +#define SJA1000_TIME_SEG1_M (SJA1000_TIME_SEG1_V << SJA1000_TIME_SEG1_S) +#define SJA1000_TIME_SEG1_V 0x0000000F +#define SJA1000_TIME_SEG1_S 0 + +/* SJA1000_ARB_LOST_CAP_REG register + * Arbitration Lost Capture Register + */ + +#define SJA1000_ARB_LOST_CAP_REG (0x0B) + +/* SJA1000_ARB_LOST_CAP : RO; bitpos: [4:0]; default: 0; + * This register contains information about the bit position of lost + * arbitration. + */ + +#define SJA1000_ARB_LOST_CAP 0x0000001F +#define SJA1000_ARB_LOST_CAP_M \ + (SJA1000_ARB_LOST_CAP_V << SJA1000_ARB_LOST_CAP_S) +#define SJA1000_ARB_LOST_CAP_V 0x0000001F +#define SJA1000_ARB_LOST_CAP_S 0 + +/* SJA1000_ERR_CODE_CAP_REG register + * Error Code Capture Register + */ + +#define SJA1000_ERR_CODE_CAP_REG (0x0C) + +/* SJA1000_ECC_TYPE : RO; bitpos: [7:6]; default: 0; + * This register contains information about error types: 00: bit error; 01: + * form error; 10: stuff error; 11: other type of error + */ + +#define SJA1000_ECC_TYPE 0x00000003 +#define SJA1000_ECC_TYPE_M (SJA1000_ECC_TYPE_V << SJA1000_ECC_TYPE_S) +#define SJA1000_ECC_TYPE_V 0x00000003 +#define SJA1000_ECC_TYPE_S 6 + +/* SJA1000_ECC_DIRECTION : RO; bitpos: [5]; default: 0; + * This register contains information about transmission direction of the + * node when error occurs. 1: Error occurs when receiving a message; 0: + * Error occurs when transmitting a message + */ + +#define SJA1000_ECC_DIRECTION (BIT(5)) +#define SJA1000_ECC_DIRECTION_M \ + (SJA1000_ECC_DIRECTION_V << SJA1000_ECC_DIRECTION_S) +#define SJA1000_ECC_DIRECTION_V 0x00000001 +#define SJA1000_ECC_DIRECTION_S 5 + +/* SJA1000_ECC_SEGMENT : RO; bitpos: [4:0]; default: 0; + * This register contains information about the location of errors, see + * Table 181 for details. + */ + +#define SJA1000_ECC_SEGMENT 0x0000001F +#define SJA1000_ECC_SEGMENT_M \ + (SJA1000_ECC_SEGMENT_V << SJA1000_ECC_SEGMENT_S) +#define SJA1000_ECC_SEGMENT_V 0x0000001F +#define SJA1000_ECC_SEGMENT_S 0 + +/* SJA1000_ERR_WARNING_LIMIT_REG register + * Error Warning Limit Register + */ + +#define SJA1000_ERR_WARNING_LIMIT_REG (0x0D) + +/* SJA1000_ERR_WARNING_LIMIT : RO | R/W; bitpos: [7:0]; default: 96; + * Error warning threshold. In the case when any of a error counter value + * exceeds the threshold, or all the error counter values are below the + * threshold, an error warning interrupt will be triggered (given the enable + * signal is valid). + */ + +#define SJA1000_ERR_WARNING_LIMIT 0x000000FF +#define SJA1000_ERR_WARNING_LIMIT_M \ + (SJA1000_ERR_WARNING_LIMIT_V << SJA1000_ERR_WARNING_LIMIT_S) +#define SJA1000_ERR_WARNING_LIMIT_V 0x000000FF +#define SJA1000_ERR_WARNING_LIMIT_S 0 + +/* SJA1000_RX_ERR_CNT_REG register + * Receive Error Counter Register + */ + +#define SJA1000_RX_ERR_CNT_REG (0x0E) + +/* SJA1000_RX_ERR_CNT : RO | R/W; bitpos: [7:0]; default: 0; + * The RX error counter register, reflects value changes under reception + * status. + */ + +#define SJA1000_RX_ERR_CNT 0x000000FF +#define SJA1000_RX_ERR_CNT_M (SJA1000_RX_ERR_CNT_V << SJA1000_RX_ERR_CNT_S) +#define SJA1000_RX_ERR_CNT_V 0x000000FF +#define SJA1000_RX_ERR_CNT_S 0 + +/* SJA1000_TX_ERR_CNT_REG register + * Transmit Error Counter Register + */ + +#define SJA1000_TX_ERR_CNT_REG (0x0F) + +/* SJA1000_TX_ERR_CNT : RO | R/W; bitpos: [7:0]; default: 0; + * The TX error counter register, reflects value changes under transmission + * status. + */ + +#define SJA1000_TX_ERR_CNT 0x000000FF +#define SJA1000_TX_ERR_CNT_M (SJA1000_TX_ERR_CNT_V << SJA1000_TX_ERR_CNT_S) +#define SJA1000_TX_ERR_CNT_V 0x000000FF +#define SJA1000_TX_ERR_CNT_S 0 + +/* SJA1000_DATA_0_REG register + * Data register 0 + */ + +#define SJA1000_DATA_0_REG (0x10) + +/* SJA1000_TX_BYTE_0 : WO; bitpos: [7:0]; default: 0; + * Stored the 0th byte information of the data to be transmitted under + * operating mode. + */ + +#define SJA1000_TX_BYTE_0 0x000000FF +#define SJA1000_TX_BYTE_0_M (SJA1000_TX_BYTE_0_V << SJA1000_TX_BYTE_0_S) +#define SJA1000_TX_BYTE_0_V 0x000000FF +#define SJA1000_TX_BYTE_0_S 0 + +/* SJA1000_ACCEPTANCE_CODE_0 : WO; bitpos: [7:0]; default: 0; + * Stored the 0th byte of the filter code in reset mode. + */ + +#define SJA1000_ACCEPTANCE_CODE_0 0x000000FF +#define SJA1000_ACCEPTANCE_CODE_0_M \ + (SJA1000_ACCEPTANCE_CODE_0_V << SJA1000_ACCEPTANCE_CODE_0_S) +#define SJA1000_ACCEPTANCE_CODE_0_V 0x000000FF +#define SJA1000_ACCEPTANCE_CODE_0_S 0 + +/* SJA1000_DATA_1_REG register + * Data register 1 + */ + +#define SJA1000_DATA_1_REG (0x11) + +/* SJA1000_TX_BYTE_1 : WO; bitpos: [7:0]; default: 0; + * Stored the 1st byte information of the data to be transmitted under + * operating mode. + */ + +#define SJA1000_TX_BYTE_1 0x000000FF +#define SJA1000_TX_BYTE_1_M (SJA1000_TX_BYTE_1_V << SJA1000_TX_BYTE_1_S) +#define SJA1000_TX_BYTE_1_V 0x000000FF +#define SJA1000_TX_BYTE_1_S 0 + +/* SJA1000_ACCEPTANCE_CODE_1 : WO; bitpos: [7:0]; default: 0; + * Stored the 1st byte of the filter code in reset mode. + */ + +#define SJA1000_ACCEPTANCE_CODE_1 0x000000FF +#define SJA1000_ACCEPTANCE_CODE_1_M \ + (SJA1000_ACCEPTANCE_CODE_1_V << SJA1000_ACCEPTANCE_CODE_1_S) +#define SJA1000_ACCEPTANCE_CODE_1_V 0x000000FF +#define SJA1000_ACCEPTANCE_CODE_1_S 0 + +/* SJA1000_DATA_2_REG register + * Data register 2 + */ + +#define SJA1000_DATA_2_REG (0x12) + +/* SJA1000_TX_BYTE_2 : WO; bitpos: [7:0]; default: 0; + * Stored the 2nd byte information of the data to be transmitted under + * operating mode. + */ + +#define SJA1000_TX_BYTE_2 0x000000FF +#define SJA1000_TX_BYTE_2_M (SJA1000_TX_BYTE_2_V << SJA1000_TX_BYTE_2_S) +#define SJA1000_TX_BYTE_2_V 0x000000FF +#define SJA1000_TX_BYTE_2_S 0 + +/* SJA1000_ACCEPTANCE_CODE_2 : WO; bitpos: [7:0]; default: 0; + * Stored the 2nd byte of the filter code in reset mode. + */ + +#define SJA1000_ACCEPTANCE_CODE_2 0x000000FF +#define SJA1000_ACCEPTANCE_CODE_2_M \ + (SJA1000_ACCEPTANCE_CODE_2_V << SJA1000_ACCEPTANCE_CODE_2_S) +#define SJA1000_ACCEPTANCE_CODE_2_V 0x000000FF +#define SJA1000_ACCEPTANCE_CODE_2_S 0 + +/* SJA1000_DATA_3_REG register + * Data register 3 + */ + +#define SJA1000_DATA_3_REG (0x13) + +/* SJA1000_TX_BYTE_3 : WO; bitpos: [7:0]; default: 0; + * Stored the 3rd byte information of the data to be transmitted under + * operating mode. + */ + +#define SJA1000_TX_BYTE_3 0x000000FF +#define SJA1000_TX_BYTE_3_M (SJA1000_TX_BYTE_3_V << SJA1000_TX_BYTE_3_S) +#define SJA1000_TX_BYTE_3_V 0x000000FF +#define SJA1000_TX_BYTE_3_S 0 + +/* SJA1000_ACCEPTANCE_CODE_3 : WO; bitpos: [7:0]; default: 0; + * Stored the 3rd byte of the filter code in reset mode. + */ + +#define SJA1000_ACCEPTANCE_CODE_3 0x000000FF +#define SJA1000_ACCEPTANCE_CODE_3_M \ + (SJA1000_ACCEPTANCE_CODE_3_V << SJA1000_ACCEPTANCE_CODE_3_S) +#define SJA1000_ACCEPTANCE_CODE_3_V 0x000000FF +#define SJA1000_ACCEPTANCE_CODE_3_S 0 + +/* SJA1000_DATA_4_REG register + * Data register 4 + */ + +#define SJA1000_DATA_4_REG (0x14) + +/* SJA1000_TX_BYTE_4 : WO; bitpos: [7:0]; default: 0; + * Stored the 4th byte information of the data to be transmitted under + * operating mode. + */ + +#define SJA1000_TX_BYTE_4 0x000000FF +#define SJA1000_TX_BYTE_4_M (SJA1000_TX_BYTE_4_V << SJA1000_TX_BYTE_4_S) +#define SJA1000_TX_BYTE_4_V 0x000000FF +#define SJA1000_TX_BYTE_4_S 0 + +/* SJA1000_ACCEPTANCE_MASK_0 : WO; bitpos: [7:0]; default: 0; + * Stored the 0th byte of the filter code in reset mode. + */ + +#define SJA1000_ACCEPTANCE_MASK_0 0x000000FF +#define SJA1000_ACCEPTANCE_MASK_0_M \ + (SJA1000_ACCEPTANCE_MASK_0_V << SJA1000_ACCEPTANCE_MASK_0_S) +#define SJA1000_ACCEPTANCE_MASK_0_V 0x000000FF +#define SJA1000_ACCEPTANCE_MASK_0_S 0 + +/* SJA1000_DATA_5_REG register + * Data register 5 + */ + +#define SJA1000_DATA_5_REG (0x15) + +/* SJA1000_TX_BYTE_5 : WO; bitpos: [7:0]; default: 0; + * Stored the 5th byte information of the data to be transmitted under + * operating mode. + */ + +#define SJA1000_TX_BYTE_5 0x000000FF +#define SJA1000_TX_BYTE_5_M (SJA1000_TX_BYTE_5_V << SJA1000_TX_BYTE_5_S) +#define SJA1000_TX_BYTE_5_V 0x000000FF +#define SJA1000_TX_BYTE_5_S 0 + +/* SJA1000_ACCEPTANCE_MASK_1 : WO; bitpos: [7:0]; default: 0; + * Stored the 1st byte of the filter code in reset mode. + */ + +#define SJA1000_ACCEPTANCE_MASK_1 0x000000FF +#define SJA1000_ACCEPTANCE_MASK_1_M \ + (SJA1000_ACCEPTANCE_MASK_1_V << SJA1000_ACCEPTANCE_MASK_1_S) +#define SJA1000_ACCEPTANCE_MASK_1_V 0x000000FF +#define SJA1000_ACCEPTANCE_MASK_1_S 0 + +/* SJA1000_DATA_6_REG register + * Data register 6 + */ + +#define SJA1000_DATA_6_REG (0x16) + +/* SJA1000_TX_BYTE_6 : WO; bitpos: [7:0]; default: 0; + * Stored the 6th byte information of the data to be transmitted under + * operating mode. + */ + +#define SJA1000_TX_BYTE_6 0x000000FF +#define SJA1000_TX_BYTE_6_M (SJA1000_TX_BYTE_6_V << SJA1000_TX_BYTE_6_S) +#define SJA1000_TX_BYTE_6_V 0x000000FF +#define SJA1000_TX_BYTE_6_S 0 + +/* SJA1000_ACCEPTANCE_MASK_2 : WO; bitpos: [7:0]; default: 0; + * Stored the 2nd byte of the filter code in reset mode. + */ + +#define SJA1000_ACCEPTANCE_MASK_2 0x000000FF +#define SJA1000_ACCEPTANCE_MASK_2_M \ + (SJA1000_ACCEPTANCE_MASK_2_V << SJA1000_ACCEPTANCE_MASK_2_S) +#define SJA1000_ACCEPTANCE_MASK_2_V 0x000000FF +#define SJA1000_ACCEPTANCE_MASK_2_S 0 + +/* SJA1000_DATA_7_REG register + * Data register 7 + */ + +#define SJA1000_DATA_7_REG (0x17) + +/* SJA1000_TX_BYTE_7 : WO; bitpos: [7:0]; default: 0; + * Stored the 7th byte information of the data to be transmitted under + * operating mode. + */ + +#define SJA1000_TX_BYTE_7 0x000000FF +#define SJA1000_TX_BYTE_7_M (SJA1000_TX_BYTE_7_V << SJA1000_TX_BYTE_7_S) +#define SJA1000_TX_BYTE_7_V 0x000000FF +#define SJA1000_TX_BYTE_7_S 0 + +/* SJA1000_ACCEPTANCE_MASK_3 : WO; bitpos: [7:0]; default: 0; + * Stored the 3th byte of the filter code in reset mode. + */ + +#define SJA1000_ACCEPTANCE_MASK_3 0x000000FF +#define SJA1000_ACCEPTANCE_MASK_3_M \ + (SJA1000_ACCEPTANCE_MASK_3_V << SJA1000_ACCEPTANCE_MASK_3_S) +#define SJA1000_ACCEPTANCE_MASK_3_V 0x000000FF +#define SJA1000_ACCEPTANCE_MASK_3_S 0 + +/* SJA1000_DATA_8_REG register + * Data register 8 + */ + +#define SJA1000_DATA_8_REG (0x18) + +/* SJA1000_TX_BYTE_8 : WO; bitpos: [7:0]; default: 0; + * Stored the 8th byte information of the data to be transmitted under + * operating mode. + */ + +#define SJA1000_TX_BYTE_8 0x000000FF +#define SJA1000_TX_BYTE_8_M (SJA1000_TX_BYTE_8_V << SJA1000_TX_BYTE_8_S) +#define SJA1000_TX_BYTE_8_V 0x000000FF +#define SJA1000_TX_BYTE_8_S 0 + +/* SJA1000_DATA_9_REG register + * Data register 9 + */ + +#define SJA1000_DATA_9_REG (0x19) + +/* SJA1000_TX_BYTE_9 : WO; bitpos: [7:0]; default: 0; + * Stored the 9th byte information of the data to be transmitted under + * operating mode. + */ + +#define SJA1000_TX_BYTE_9 0x000000FF +#define SJA1000_TX_BYTE_9_M (SJA1000_TX_BYTE_9_V << SJA1000_TX_BYTE_9_S) +#define SJA1000_TX_BYTE_9_V 0x000000FF +#define SJA1000_TX_BYTE_9_S 0 + +/* SJA1000_DATA_10_REG register + * Data register 10 + */ + +#define SJA1000_DATA_10_REG (0x1A) + +/* SJA1000_TX_BYTE_10 : WO; bitpos: [7:0]; default: 0; + * Stored the 10th byte information of the data to be transmitted under + * operating mode. + */ + +#define SJA1000_TX_BYTE_10 0x000000FF +#define SJA1000_TX_BYTE_10_M (SJA1000_TX_BYTE_10_V << SJA1000_TX_BYTE_10_S) +#define SJA1000_TX_BYTE_10_V 0x000000FF +#define SJA1000_TX_BYTE_10_S 0 + +/* SJA1000_DATA_11_REG register + * Data register 11 + */ + +#define SJA1000_DATA_11_REG (0x1B) + +/* SJA1000_TX_BYTE_11 : WO; bitpos: [7:0]; default: 0; + * Stored the 11th byte information of the data to be transmitted under + * operating mode. + */ + +#define SJA1000_TX_BYTE_11 0x000000FF +#define SJA1000_TX_BYTE_11_M (SJA1000_TX_BYTE_11_V << SJA1000_TX_BYTE_11_S) +#define SJA1000_TX_BYTE_11_V 0x000000FF +#define SJA1000_TX_BYTE_11_S 0 + +/* SJA1000_DATA_12_REG register + * Data register 12 + */ + +#define SJA1000_DATA_12_REG (0x1C) + +/* SJA1000_TX_BYTE_12 : WO; bitpos: [7:0]; default: 0; + * Stored the 12th byte information of the data to be transmitted under + * operating mode. + */ + +#define SJA1000_TX_BYTE_12 0x000000FF +#define SJA1000_TX_BYTE_12_M (SJA1000_TX_BYTE_12_V << SJA1000_TX_BYTE_12_S) +#define SJA1000_TX_BYTE_12_V 0x000000FF +#define SJA1000_TX_BYTE_12_S 0 + +/* SJA1000_RX_MESSAGE_CNT_REG register + * Receive Message Counter Register + */ + +#define SJA1000_RX_MESSAGE_CNT_REG (0x1D) + +/* SJA1000_RX_MESSAGE_COUNTER : RO; bitpos: [6:0]; default: 0; + * This register reflects the number of messages available within the RX + * FIFO. + */ + +#define SJA1000_RX_MESSAGE_COUNTER 0x0000007F +#define SJA1000_RX_MESSAGE_COUNTER_M \ + (SJA1000_RX_MESSAGE_COUNTER_V << SJA1000_RX_MESSAGE_COUNTER_S) +#define SJA1000_RX_MESSAGE_COUNTER_V 0x0000007F +#define SJA1000_RX_MESSAGE_COUNTER_S 0 + +/* SJA1000_CLOCK_DIVIDER_REG register + * Clock Divider register + */ + +#define SJA1000_CLOCK_DIVIDER_REG (0x1F) + +/* SJA1000_CLOCK_OFF : RO | R/W; bitpos: [3]; default: 0; + * This bit can be configured under reset mode. 1: Disable the external + * CLKOUT pin; 0: Enable the external CLKOUT pin + */ + +#define SJA1000_CLOCK_OFF (BIT(3)) +#define SJA1000_CLOCK_OFF_M (SJA1000_CLOCK_OFF_V << SJA1000_CLOCK_OFF_S) +#define SJA1000_CLOCK_OFF_V 0x00000001 +#define SJA1000_CLOCK_OFF_S 3 + +/* SJA1000_EXT_MODE : RO | R/W; bitpos: [7]; default: 0; + * This bit can be configured under reset mode. 1: Extended mode, compatible + * with CAN2.0B; 0: Basic mode + */ + +#define SJA1000_EXT_MODE (BIT(7)) +#define SJA1000_EXT_MODE_M (SJA1000_EXT_MODE_V << SJA1000_EXT_MODE_S) +#define SJA1000_EXT_MODE_V 0x00000001 +#define SJA1000_EXT_MODE_S 7 + +/* SJA1000_CD : R/W; bitpos: [7:0]; default: 0; + * These bits are used to configure frequency dividing coefficients of the + * external CLKOUT pin. + */ + +#define SJA1000_CD 0x00000007 +#define SJA1000_CD_M (SJA1000_CD_V << SJA1000_CD_S) +#define SJA1000_CD_V 0x00000007 +#define SJA1000_CD_S 0 + +#endif /* __DRIVERS_CAN_SJA1000_H */ diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 832247e32065d..ba421065d7715 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -10,7 +10,7 @@ if CLK config CLK_RPMSG bool "RPMSG clk driver" default n - depends on RPTUN + depends on RPMSG ---help--- RPMSG clk are proxy/master pairs clock that operate clks between client and server processor. diff --git a/drivers/devicetree/CMakeLists.txt b/drivers/devicetree/CMakeLists.txt index 465401bc6134e..e9585d2da57c8 100644 --- a/drivers/devicetree/CMakeLists.txt +++ b/drivers/devicetree/CMakeLists.txt @@ -20,5 +20,7 @@ if(CONFIG_DEVICE_TREE) set(SRCS fdt.c) + target_include_directories(drivers + PRIVATE ${NUTTX_DIR}/libs/libc/fdt/dtc/libfdt) target_sources(drivers PRIVATE ${SRCS}) endif() diff --git a/drivers/devicetree/Kconfig b/drivers/devicetree/Kconfig index 123dcb5f001f4..80e0e16cc62e7 100644 --- a/drivers/devicetree/Kconfig +++ b/drivers/devicetree/Kconfig @@ -6,5 +6,6 @@ menuconfig DEVICE_TREE bool "Device Tree Support" default n + select LIBC_FDT ---help--- Interface for interacting with devicetree. diff --git a/drivers/devicetree/Make.defs b/drivers/devicetree/Make.defs index 956de78a0d43f..c8af98c8cf6ba 100644 --- a/drivers/devicetree/Make.defs +++ b/drivers/devicetree/Make.defs @@ -22,6 +22,8 @@ ifeq ($(CONFIG_DEVICE_TREE),y) CSRCS += fdt.c +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)libs$(DELIM)libc$(DELIM)fdt$(DELIM)dtc$(DELIM)libfdt + DEPPATH += --dep-path devicetree VPATH += :devicetree diff --git a/drivers/devicetree/fdt.c b/drivers/devicetree/fdt.c index f07f23357df24..6aa4c8a0fb81d 100644 --- a/drivers/devicetree/fdt.c +++ b/drivers/devicetree/fdt.c @@ -28,6 +28,7 @@ #include #include #include +#include /**************************************************************************** * Private Data @@ -41,20 +42,6 @@ static FAR const char *g_fdt_base = NULL; * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: fdt_register - * - * Description: - * Store the pointer to the flattened device tree and verify that it at - * least appears to be valid. This function will not fully parse the FDT. - * - * Return: - * Return -EINVAL if the fdt header does not have the expected magic value. - * otherwise return OK. If OK is not returned the existing entry for FDT - * is not modified. - * - ****************************************************************************/ - int fdt_register(FAR const char *fdt_base) { struct fdt_header_s *fdt_header; @@ -71,16 +58,235 @@ int fdt_register(FAR const char *fdt_base) return OK; } -/**************************************************************************** - * Name: fdt_get - * - * Description: - * Return the pointer to a raw FDT. NULL is returned if no FDT has been - * loaded. - * - ****************************************************************************/ - FAR const char *fdt_get(void) { return g_fdt_base; } + +int fdt_get_irq(FAR const void *fdt, int nodeoffset, + int offset, int irqbase) +{ + FAR const fdt32_t *pv; + int irq = -1; + + pv = fdt_getprop(fdt, nodeoffset, "interrupts", NULL); + if (pv != NULL) + { + irq = fdt32_ld(pv + offset) + irqbase; + } + + return irq; +} + +int fdt_get_irq_by_path(FAR const void *fdt, int offset, + const char *path, int irqbase) +{ + return fdt_get_irq(fdt, fdt_path_offset(fdt, path), offset, irqbase); +} + +int fdt_get_parent_address_cells(FAR const void *fdt, int offset) +{ + int parentoff; + + parentoff = fdt_parent_offset(fdt, offset); + if (parentoff < 0) + { + return parentoff; + } + + return fdt_address_cells(fdt, parentoff); +} + +int fdt_get_parent_size_cells(FAR const void *fdt, int offset) +{ + int parentoff; + + parentoff = fdt_parent_offset(fdt, offset); + if (parentoff < 0) + { + return parentoff; + } + + return fdt_size_cells(fdt, parentoff); +} + +uintptr_t fdt_ld_by_cells(FAR const void *value, int cells) +{ + if (cells == 2) + { + return fdt64_ld(value); + } + else + { + return fdt32_ld(value); + } +} + +uintptr_t fdt_get_reg_base_by_name(FAR const void *fdt, int offset, + const char *reg_name) +{ + uintptr_t addr = 0; + + int reg_index + = fdt_stringlist_search(fdt, offset, "reg-names", reg_name); + if (reg_index < 0) + { + return addr; + } + + return fdt_get_reg_base(fdt, offset, reg_index); +} + +uintptr_t fdt_get_reg_base(FAR const void *fdt, int offset, int index) +{ + FAR const void *reg; + uintptr_t addr = 0; + int reg_length; + + /* Register cells contain a tuple of two values */ + + index *= 2; + + reg = fdt_getprop(fdt, offset, "reg", ®_length); + if (reg != NULL) + { + if ((index * sizeof(uintptr_t)) > reg_length) + { + return addr; + } + + addr = fdt_ld_by_cells(reg + index * sizeof(uintptr_t), + fdt_get_parent_address_cells(fdt, offset)); + } + + return addr; +} + +uintptr_t fdt_get_reg_size(FAR const void *fdt, int offset) +{ + FAR const void *reg; + uintptr_t size = 0; + + reg = fdt_getprop(fdt, offset, "reg", NULL); + if (reg != NULL) + { + size = fdt_ld_by_cells(reg, fdt_get_parent_size_cells(fdt, offset)); + } + + return size; +} + +uintptr_t fdt_get_reg_base_by_path(FAR const void *fdt, FAR const char *path) +{ + return fdt_get_reg_base(fdt, fdt_path_offset(fdt, path), 0); +} + +bool fdt_device_is_available(FAR const void *fdt, int node) +{ + const char *status = fdt_getprop(fdt, node, "status", NULL); + if (!status) + { + return true; + } + + if (!strcmp(status, "ok") || !strcmp(status, "okay")) + { + return true; + } + + return false; +} + +const char *fdt_get_node_label(FAR const void *fdt, int node) +{ + int symbols_offset; + int property_offset; + int ret; + const char *property_name; + const char *label_name; + char path_buffer[CONFIG_PATH_MAX] = + { + 0 + }; + + symbols_offset = fdt_path_offset(fdt, "/__symbols__"); + if (symbols_offset < 0) + { + return NULL; + } + + ret = fdt_get_path(fdt, node, path_buffer, sizeof(path_buffer)); + if (ret < 0) + { + return NULL; + } + + fdt_for_each_property_offset(property_offset, fdt, symbols_offset) + { + property_name = fdt_getprop_by_offset( + fdt, property_offset, &label_name, NULL); + + /* The symbols section is a list of parameters in the format + * label_name = node_path. So the value of each property needs to be + * checked with the full path found earlier. + * + */ + + if (!strncmp(property_name, path_buffer, sizeof(path_buffer))) + { + return label_name; + } + } + + return NULL; +} + +uintptr_t fdt_get_clock_frequency(FAR const void *fdt, int offset) +{ + const void *pv; + uintptr_t clock_frequency = 0; + + pv = fdt_getprop(fdt, offset, "clock-frequency", NULL); + if (!pv) + { + return clock_frequency; + } + + clock_frequency = fdt_ld_by_cells(pv, + fdt_get_parent_address_cells(fdt, + offset)); + + return clock_frequency; +} + +uintptr_t fdt_get_clock_frequency_from_clocks(FAR const void *fdt, + int offset, + int index) +{ + const fdt32_t *pv; + fdt32_t clk_phandle; + int pv_offset; + uintptr_t clock_frequency = 0; + int clk_length; + + pv = fdt_getprop(fdt, offset, "clocks", &clk_length); + if (!pv) + { + return clock_frequency; + } + + if ((index * sizeof(fdt32_t)) > clk_length) + { + return clock_frequency; + } + + clk_phandle = fdt32_ld(pv + index); + + pv_offset = fdt_node_offset_by_phandle(fdt, clk_phandle); + if (pv_offset < 0) + { + return clock_frequency; + } + + return fdt_get_clock_frequency(fdt, pv_offset); +} diff --git a/drivers/eeprom/i2c_xx24xx.c b/drivers/eeprom/i2c_xx24xx.c index 722cfe5afbf9c..959545da86f30 100644 --- a/drivers/eeprom/i2c_xx24xx.c +++ b/drivers/eeprom/i2c_xx24xx.c @@ -873,7 +873,7 @@ int ee24xx_initialize(FAR struct i2c_master_s *bus, uint8_t devaddr, } } - finfo("EEPROM device %s, %d bytes, %d per page, addrlen %d, %s\n", + finfo("EEPROM device %s, %" PRIu32 " bytes, %d per page, addrlen %d, %s\n", devname, eedev->size, eedev->pgsize, eedev->addrlen, eedev->readonly ? "readonly" : ""); diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index 5c07626d4e9c3..dbb1c8d7007df 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -47,7 +47,7 @@ config INPUT_UINPUT config UINPUT_RPMSG bool "Enable uinput RPMSG" depends on INPUT_UINPUT - depends on RPTUN + depends on RPMSG default n ---help--- Enable support uinput cross core communication diff --git a/drivers/input/uinput.c b/drivers/input/uinput.c index 4f6d9ce6ae742..fa4425978e301 100644 --- a/drivers/input/uinput.c +++ b/drivers/input/uinput.c @@ -26,6 +26,7 @@ #include #include +#include #include #include #include diff --git a/drivers/ioexpander/Kconfig b/drivers/ioexpander/Kconfig index 77c9b2eb96971..ed69d67ac6f9b 100644 --- a/drivers/ioexpander/Kconfig +++ b/drivers/ioexpander/Kconfig @@ -16,7 +16,7 @@ if IOEXPANDER config IOEXPANDER_RPMSG bool "IO expander RPMSG server and client" - depends on RPTUN + depends on RPMSG default n select IOEXPANDER_INT_ENABLE ---help--- @@ -56,6 +56,31 @@ config IOEXPANDER_DUMMY_INT_POLLDELAY endif # IOEXPANDER_DUMMY +config IOEXPANDER_ICJX + bool "iC-JX SPI IO expander" + default n + depends on SPI + ---help--- + Enable support for the iC-JX expander from iC-Haus GmbH manufacturer. + SPI peripheral is used for the communication. + +if IOEXPANDER_ICJX + +config ICJX_MULTIPLE + bool "Multiple iC-JX Devices" + default n + ---help--- + Can be defined to support multiple iC-JX devices on board. + +config ICJX_INT_ENABLE + bool "Enable iC-JX Interrupt Support" + default n + select IOEXPANDER_INT_ENABLE + ---help--- + Enable driver interrupt functionality + +endif # IOEXPANDER_ICJX + config IOEXPANDER_ISO1H812G bool "ISO1H812G SPI IO expander" default n diff --git a/drivers/ioexpander/Make.defs b/drivers/ioexpander/Make.defs index 2777af4415b49..cdf0921ccddce 100644 --- a/drivers/ioexpander/Make.defs +++ b/drivers/ioexpander/Make.defs @@ -32,6 +32,10 @@ ifeq ($(CONFIG_IOEXPANDER_DUMMY),y) CSRCS += ioe_dummy.c endif +ifeq ($(CONFIG_IOEXPANDER_ICJX),y) + CSRCS += icjx.c +endif + ifeq ($(CONFIG_IOEXPANDER_ISO1H812G),y) CSRCS += iso1h812g.c endif diff --git a/drivers/ioexpander/icjx.c b/drivers/ioexpander/icjx.c new file mode 100644 index 0000000000000..f79df627b1e9c --- /dev/null +++ b/drivers/ioexpander/icjx.c @@ -0,0 +1,1117 @@ +/**************************************************************************** + * drivers/ioexpander/icjx.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "icjx.h" + +#ifdef CONFIG_IOEXPANDER_ICJX + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ICJX_NOP 0x00 +#define ICJX_RNW 0x01 +#define ICJX_NOB1 0x0f +#define ICJX_NOB2 0x1e +#define ICJX_CONTROL 0x59 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct icjx_callback_s +{ + ioe_pinset_t pinset; + ioe_callback_t function; + FAR void *arg; +}; + +struct icjx_dev_s +{ + struct ioexpander_dev_s dev; /* Nested structure to allow casting + * as public gpio expander. */ + FAR struct icjx_config_s *config; /* Board configuration data */ + FAR struct spi_dev_s *spi; /* Saved SPI driver instance */ + + uint16_t outpins; + uint16_t outstate; + uint16_t irqpins; + mutex_t lock; + +#ifdef CONFIG_IOEXPANDER_INT_ENABLE + struct work_s work; + struct icjx_callback_s callback; +#endif +}; + +/**************************************************************************** + * Private Function Protototypes + ****************************************************************************/ + +/* SPI helpers */ + +static void icjx_select(FAR struct spi_dev_s *spi, + FAR struct icjx_config_s *config, int bits); +static void icjx_deselect(FAR struct spi_dev_s *spi, + FAR struct icjx_config_s *config); + +/* Read/Write helpers */ + +static int icjx_read(FAR struct icjx_dev_s *priv, uint8_t reg, + uint16_t *data, int nob); +static int icjx_write(FAR struct icjx_dev_s *priv, uint8_t reg, + uint16_t data, int nob); + +/* I/O Expander Methods */ + +static int icjx_direction(FAR struct ioexpander_dev_s *dev, uint8_t pin, + int dir); +static int icjx_option(FAR struct ioexpander_dev_s *dev, uint8_t pin, + int opt, void *regval); +static int icjx_writepin(FAR struct ioexpander_dev_s *dev, uint8_t pin, + bool value); +static int icjx_readpin(FAR struct ioexpander_dev_s *dev, uint8_t pin, + FAR bool *value); +#ifdef CONFIG_IOEXPANDER_MULTIPIN +static int icjx_multiwritepin(FAR struct ioexpander_dev_s *dev, + FAR const uint8_t *pins, + FAR const bool *values, int count); +static int icjx_multireadpin(FAR struct ioexpander_dev_s *dev, + FAR const uint8_t *pins, FAR bool *values, + int count); +#endif +#ifdef CONFIG_IOEXPANDER_INT_ENABLE +static FAR void *icjx_attach(FAR struct ioexpander_dev_s *dev, + ioe_pinset_t pinset, ioe_callback_t callback, + FAR void *arg); +static int icjx_detach(FAR struct ioexpander_dev_s *dev, FAR void *handle); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifndef CONFIG_ICJX_MULTIPLE +/* If only a single device is supported, then the driver state structure may + * as well be pre-allocated. + */ + +static struct icjx_dev_s g_icjx; +#endif + +/* I/O expander vtable */ + +static const struct ioexpander_ops_s g_icjx_ops = +{ + icjx_direction, + icjx_option, + icjx_writepin, + icjx_readpin, + icjx_readpin +#ifdef CONFIG_IOEXPANDER_MULTIPIN + , icjx_multiwritepin + , icjx_multireadpin + , icjx_multireadpin +#endif +#ifdef CONFIG_IOEXPANDER_INT_ENABLE + , icjx_attach + , icjx_detach +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: icjx_select + * + * Description: + * Select the SPI, locking and re-configuring if necessary + * + * Input Parameters: + * spi - Reference to the SPI driver structure + * config - Reference to iC-JX configuration structure + * bits - Number of SPI bits + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void icjx_select(FAR struct spi_dev_s *spi, + FAR struct icjx_config_s *config, int bits) +{ + /* Select iC-JX chip (locking the SPI bus in case there are multiple + * devices competing for the SPI bus + */ + + SPI_LOCK(spi, true); + SPI_SELECT(spi, SPIDEV_EXPANDER(config->id), true); + + /* Now make sure that the SPI bus is configured for the iC-JX (it + * might have gotten configured for a different device while unlocked) + */ + + SPI_SETMODE(spi, config->mode); + SPI_SETBITS(spi, bits); + SPI_SETFREQUENCY(spi, config->frequency); +} + +/**************************************************************************** + * Name: icjx_deselect + * + * Description: + * De-select the SPI + * + * Input Parameters: + * spi - Reference to the SPI driver structure + * config - Reference to iC-JX configuration structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void icjx_deselect(FAR struct spi_dev_s *spi, + FAR struct icjx_config_s *config) +{ + /* De-select iC-JX chip and relinquish the SPI bus. */ + + SPI_SELECT(spi, SPIDEV_EXPANDER(config->id), false); + SPI_LOCK(spi, false); +} + +/**************************************************************************** + * Name: icjx_read + * + * Description: + * Helper function for register read operation. + * + * Input Parameters: + * priv - Pointer to icjx_dev_s structure + * reg - Register offset (see icjx.h) + * data - Pointer to read data + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int icjx_read(FAR struct icjx_dev_s *priv, uint8_t reg, + uint16_t *data, int nob) +{ + uint8_t startaddr; + uint8_t tx_buffer[6]; + uint8_t rx_buffer[6]; + + startaddr = (priv->config->addr << 6) | (reg << 1) | ICJX_RNW; + tx_buffer[0] = startaddr; + tx_buffer[1] = ICJX_NOP; + tx_buffer[2] = nob; + + icjx_select(priv->spi, priv->config, 8); + SPI_EXCHANGE(priv->spi, tx_buffer, rx_buffer, 3); + + *data = rx_buffer[2]; + + if (priv->config->verification) + { + if (nob == ICJX_NOB2) + { + tx_buffer[0] = rx_buffer[2]; + SPI_EXCHANGE(priv->spi, tx_buffer, rx_buffer, 1); + *data |= rx_buffer[0] << 8; + tx_buffer[0] = rx_buffer[0]; + startaddr = (priv->config->addr << 6) | + ((reg + 1) << 1) | ICJX_RNW; + } + else + { + tx_buffer[0] = rx_buffer[2]; + } + + tx_buffer[1] = ICJX_CONTROL; + SPI_EXCHANGE(priv->spi, tx_buffer, rx_buffer, 2); + } + + icjx_deselect(priv->spi, priv->config); + + if (priv->config->verification) + { + if (rx_buffer[0] != startaddr) + { + gpioerr("ERROR: Data verification error for register 0x%x!\n", + reg); + return -EIO; + } + + if (rx_buffer[1] != ICJX_CONTROL) + { + gpioerr("ERROR: Control byte verification error for register" + "0x%x!\n", reg); + return -EIO; + } + } + + return OK; +} + +/**************************************************************************** + * Name: icjx_write + * + * Description: + * Helper function for register write operation. + * + * Input Parameters: + * priv - Pointer to icjx_dev_s structure + * reg - Register offset (see icjx.h) + * data - Data to be written + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int icjx_write(FAR struct icjx_dev_s *priv, uint8_t reg, + uint16_t data, int nob) +{ + uint8_t startaddr; + uint8_t bytes_to_exchange; + uint8_t tx_buffer[6]; + uint8_t rx_buffer[6]; + int ver_idx; + int data_len; + + data_len = 1; + ver_idx = 2; + bytes_to_exchange = 0; + startaddr = (priv->config->addr << 6) | (reg << 1); + tx_buffer[bytes_to_exchange++] = startaddr; + tx_buffer[bytes_to_exchange++] = nob; + tx_buffer[bytes_to_exchange++] = data & 0xff; + if (nob == ICJX_NOB2) + { + data_len = 2; + tx_buffer[bytes_to_exchange++] = (data >> 8) & 0xff; + } + + if (priv->config->verification) + { + tx_buffer[bytes_to_exchange++] = (priv->config->addr << 6) | + ((reg + (data_len - 1)) << 1); + tx_buffer[bytes_to_exchange++] = ICJX_CONTROL; + } + + icjx_select(priv->spi, priv->config, 8); + SPI_EXCHANGE(priv->spi, tx_buffer, rx_buffer, bytes_to_exchange); + icjx_deselect(priv->spi, priv->config); + + if (priv->config->verification) + { + if (rx_buffer[ver_idx++] != nob) + { + gpioerr("ERROR: Start address verification error for register" + "0x%x!\n", reg); + return -EIO; + } + + for (int i = 0; i < data_len; i++) + { + if (rx_buffer[ver_idx++] != ((data >> (i * 8)) & 0xff)) + { + gpioerr("ERROR: Data verification error for register 0x%x!\n", + reg); + return -EIO; + } + } + + if (rx_buffer[ver_idx++] != ICJX_CONTROL) + { + gpioerr("ERROR: Control verification error for register 0x%x!\n", + reg); + return -EIO; + } + } + + return OK; +} + +/**************************************************************************** + * Name: icjx_direction + * + * Description: + * iC-JX is only input pin. However interface is provided in order + * to avoid system falls if called. + * + * Input Parameters: + * dev - Device-specific state data + * pin - The index of the pin to alter in this call + * dir - One of the IOEXPANDER_DIRECTION_ macros + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int icjx_direction(FAR struct ioexpander_dev_s *dev, uint8_t pin, + int dir) +{ + FAR struct icjx_dev_s *priv = (FAR struct icjx_dev_s *)dev; + uint8_t outpins; + uint16_t out_set; + uint8_t regaddr; + int ret; + + if (dir != IOEXPANDER_DIRECTION_IN && + dir != IOEXPANDER_DIRECTION_OUT) + { + return -EINVAL; + } + + DEBUGASSERT(priv != NULL && priv->config != NULL && pin < 16); + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + if (dir == IOEXPANDER_DIRECTION_OUT) + { + priv->outpins |= (1 << pin); + } + else + { + priv->outpins &= ~(1 << pin); + } + + if (pin < 8) + { + regaddr = ICJX_CTRL_WORD_2_A; + outpins = priv->outpins & 0xff; + } + else + { + regaddr = ICJX_CTRL_WORD_2_B; + outpins = (priv->outpins >> 8) & 0xff; + } + + ret = icjx_read(priv, regaddr, &out_set, ICJX_NOB1); + if (ret < 0) + { + nxmutex_unlock(&priv->lock); + return ret; + } + + /* Enable output generation */ + + if ((outpins & 0xf) != 0) + { + out_set |= ICJX_CTRL_WORD_2_NIOL; + } + else + { + out_set &= ~ICJX_CTRL_WORD_2_NIOL; + } + + if ((outpins & 0xf0) != 0) + { + out_set |= ICJX_CTRL_WORD_2_NIOH; + } + else + { + out_set &= ~ICJX_CTRL_WORD_2_NIOH; + } + + ret = icjx_write(priv, regaddr, out_set, ICJX_NOB1); + nxmutex_unlock(&priv->lock); + + return ret; +} + +/**************************************************************************** + * Name: icjx_option + * + * Description: + * Set pin options. Required. + * Since all IO expanders have various pin options, this API allows setting + * pin options in a flexible way. + * + * Input Parameters: + * dev - Device-specific state data + * pin - The index of the pin to alter in this call + * opt - One of the IOEXPANDER_OPTION_ macros + * value - The option's value + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int icjx_option(FAR struct ioexpander_dev_s *dev, uint8_t pin, + int opt, FAR void *value) +{ + /* TODO: Implementation of iC-JX options should be here. This includes + * setup of filters, ADC etc. The right way to implement + * this would probably be to introduce config structure to + * include/nuttx/ioexpanders/icjx.h that the user could use for the + * nibbles configuration. + * + * Currently only interrupts are implemented. + */ + + FAR struct icjx_dev_s *priv = (FAR struct icjx_dev_s *)dev; + uint8_t data; + uint8_t reg; + int ret; + + DEBUGASSERT(priv != NULL && priv->config != NULL); + + gpioinfo("Expander id=%02x pin=%u option=%u\n", + priv->config->id, pin, opt); + + if (opt == IOEXPANDER_OPTION_INTCFG) + { + unsigned int ival = (unsigned int)((uintptr_t)value); + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + switch (ival) + { + case IOEXPANDER_VAL_HIGH: + case IOEXPANDER_VAL_LOW: + case IOEXPANDER_VAL_RISING: + case IOEXPANDER_VAL_FALLING: + case IOEXPANDER_VAL_BOTH: + priv->irqpins |= 1 << pin; + break; + case IOEXPANDER_VAL_DISABLE: + priv->irqpins &= ~(1 << pin); + break; + default: + nxmutex_unlock(&priv->lock); + return -EINVAL; + } + + /* We have to modify ICJX_CHNG_INT_EN_A or ICJX_CHNG_INT_EN_B + * register. + */ + + if (pin < 8) + { + reg = ICJX_CHNG_INT_EN_A; + data = priv->irqpins & 0xff; + } + else + { + reg = ICJX_CHNG_INT_EN_B; + data = (priv->irqpins >> 8) & 0xff; + } + + ret = icjx_write(priv, reg, data, ICJX_NOB1); + if (ret < 0) + { + gpioerr("Cannot write to %s register\n.", + reg == ICJX_CHNG_INT_EN_A ? + "ICJX_CHNG_INT_EN_A" : "ICJX_CHNG_INT_EN_B"); + } + + nxmutex_unlock(&priv->lock); + } + else + { + return -ENOTTY; + } + + return ret; +} + +/**************************************************************************** + * Name: icjx_writepin + * + * Description: + * Set the pin level. Required. + * + * Input Parameters: + * dev - Device-specific state data + * pin - The index of the pin to alter in this call + * value - The pin level. Usually TRUE will set the pin high, + * except if OPTION_INVERT has been set on this pin. + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int icjx_writepin(FAR struct ioexpander_dev_s *dev, uint8_t pin, + bool value) +{ + FAR struct icjx_dev_s *priv = (FAR struct icjx_dev_s *)dev; + uint8_t outstate; + uint8_t regaddr; + int ret; + + if (pin > 16) + { + return -ENXIO; + } + + DEBUGASSERT(priv != NULL && priv->config != NULL); + + gpioinfo("Expander id=%02x, pin=%u\n", priv->config->id, pin); + + /* Get exclusive access to the I/O Expander */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + if ((priv->outpins & (1 << pin)) == 0) + { + gpioerr("ERROR: pin%u is an input\n", pin); + nxmutex_unlock(&priv->lock); + return -EINVAL; + } + + /* Set/clear a bit in outstate. */ + + if (value) + { + priv->outstate |= (1 << pin); + } + else + { + priv->outstate &= ~(1 << pin); + } + + if (pin < 8) + { + regaddr = ICJX_OUTPUT_A; + outstate = priv->outstate & 0xff; + } + else + { + regaddr = ICJX_OUTPUT_B; + outstate = (priv->outstate >> 8) & 0xff; + } + + ret = icjx_write(priv, regaddr, outstate, ICJX_NOB1); + nxmutex_unlock(&priv->lock); + + return ret; +} + +/**************************************************************************** + * Name: icjx_readpin + * + * Description: + * Read the actual PIN level. This can be different from the last value + * written to this pin. Required. + * + * Input Parameters: + * dev - Device-specific state data + * pin - The index of the pin + * value - Pointer to a buffer where the pin level is stored. Usually + * TRUE if the pin is high, except if OPTION_INVERT has been + * set this pin. + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int icjx_readpin(FAR struct ioexpander_dev_s *dev, uint8_t pin, + FAR bool *value) +{ + FAR struct icjx_dev_s *priv = (FAR struct icjx_dev_s *)dev; + uint8_t regaddr; + uint16_t data; + int ret; + + if (pin > 16) + { + return -ENXIO; + } + + DEBUGASSERT(priv != NULL && priv->config != NULL && value != NULL); + + gpioinfo("Expander addr=%02x, pin=%u\n", priv->config->addr, pin); + + /* Get exclusive access to the I/O Expander */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + /* Make sure that this is an output pin */ + + if ((priv->outpins & (1 << pin)) != 0) + { + *value = ((priv->outstate & (1 << pin)) != 0); + nxmutex_unlock(&priv->lock); + return OK; + } + + regaddr = pin < 8 ? ICJX_INPUT_A : ICJX_INPUT_B; + + ret = icjx_read(priv, regaddr, &data, ICJX_NOB1); + nxmutex_unlock(&priv->lock); + if (ret != OK) + { + return ret; + } + + *value = (bool)((data >> (pin & 0xf)) & 1); + return OK; +} + +/**************************************************************************** + * Name: icjx_multiwritepin + * + * Description: + * Set the pin level for multiple pins. This routine may be faster than + * individual pin accesses. Optional. + * + * Input Parameters: + * dev - Device-specific state data + * pins - The list of pin indexes to alter in this call + * values - The list of pin levels. + * count - Number of pins to be written + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +#ifdef CONFIG_IOEXPANDER_MULTIPIN +static int icjx_multiwritepin(FAR struct ioexpander_dev_s *dev, + FAR const uint8_t *pins, + FAR const bool *values, int count) +{ + FAR struct icjx_dev_s *priv = (FAR struct icjx_dev_s *)dev; + int ret; + int pin; + int value; + + if (count >= 16) + { + return -ENXIO; + } + + DEBUGASSERT(priv != NULL && priv->config != NULL); + + /* Get exclusive access to the I/O Expander */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + for (int i = 0; i < count; i++) + { + pin = pins[i]; + value = values[i]; + + gpioinfo("Expander id=%02x, pin=%u\n", priv->config->id, pin); + + if ((priv->outpins & (1 << pin)) == 0) + { + gpioerr("ERROR: pin%u is an input\n", pin); + nxmutex_unlock(&priv->lock); + return -EINVAL; + } + + /* Set/clear a bit in outstate. */ + + if (value) + { + priv->outstate |= (1 << pin); + } + else + { + priv->outstate &= ~(1 << pin); + } + } + + ret = icjx_write(priv, ICJX_OUTPUT_A, priv->outstate, ICJX_NOB2); + nxmutex_unlock(&priv->lock); + + return ret; +} + +/**************************************************************************** + * Name: icjx_multireadpin + * + * Description: + * Read the actual level for multiple pins. This routine may be faster than + * individual pin accesses. Optional. + * + * Input Parameters: + * dev - Device-specific state data + * pin - The list of pin indexes to read + * values - Pointer to a buffer where the pin levels are stored. + * count - Number of pins to be read + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int icjx_multireadpin(FAR struct ioexpander_dev_s *dev, + FAR const uint8_t *pins, FAR bool *values, + int count) +{ + FAR struct icjx_dev_s *priv = (FAR struct icjx_dev_s *)dev; + uint16_t data; + int pin; + int ret; + + if (count > 16) + { + return -ENXIO; + } + + DEBUGASSERT(priv != NULL && priv->config != NULL && values != NULL); + + /* Get exclusive access to the I/O Expander */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + for (int i = 0; i < count; i++) + { + pin = pins[i]; + + gpioinfo("Expander id=%02x, pin=%u\n", priv->config->id, pin); + + if ((priv->outpins & (1 << pin)) != 0) + { + values[i] = (bool)((priv->outstate & (1 << pin)) != 0); + } + } + + ret = icjx_read(priv, ICJX_INPUT_A, &data, ICJX_NOB2); + nxmutex_unlock(&priv->lock); + if (ret != OK) + { + return ret; + } + + for (int i = 0; i < count; i++) + { + values[i] = (bool)((data >> (pins[i] & 0xf)) & 1); + } + + return OK; +} +#endif /* CONFIG_IOEXPANDER_MULTIPIN */ + +/**************************************************************************** + * Name: icjx_attach + * + * Description: + * Attach and enable a pin interrupt callback function. + * + * Input Parameters: + * dev - Device-specific state data + * pinset - The set of pin events that will generate the callback + * callback - The pointer to callback function. NULL will detach the + * callback. + * arg - User-provided callback argument + * + * Returned Value: + * A non-NULL handle value is returned on success. This handle may be + * used later to detach and disable the pin interrupt. + * + ****************************************************************************/ + +#ifdef CONFIG_IOEXPANDER_INT_ENABLE +static FAR void *icjx_attach(FAR struct ioexpander_dev_s *dev, + ioe_pinset_t pinset, ioe_callback_t callback, + FAR void *arg) +{ + FAR struct icjx_dev_s *priv = (FAR struct icjx_dev_s *)dev; + FAR void *handle = NULL; + int ret; + + /* Get exclusive access */ + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return NULL; + } + + if (priv->callback.function == NULL) + { + /* Yes.. use this entry */ + + priv->callback.pinset = pinset; + priv->callback.function = callback; + priv->callback.arg = arg; + handle = &priv->callback; + } + + /* Add this callback to the table */ + + nxmutex_unlock(&priv->lock); + return handle; +} + +/**************************************************************************** + * Name: icjx_detach + * + * Description: + * Detach and disable a pin interrupt callback function. + * + * Input Parameters: + * dev - Device-specific state data + * handle - The non-NULL opaque value return by pca9555_attch() + * + * Returned Value: + * 0 on success, else a negative error code + * + ****************************************************************************/ + +static int icjx_detach(FAR struct ioexpander_dev_s *dev, FAR void *handle) +{ + FAR struct icjx_callback_s *cb = + (FAR struct icjx_callback_s *)handle; + + cb->pinset = 0; + cb->function = NULL; + cb->arg = NULL; + return OK; +} + +/**************************************************************************** + * Name: icjx_interrupt_worker + * + * Description: + * Handle GPIO interrupt events (this function actually executes in the + * context of the worker thread). + * + ****************************************************************************/ + +#ifdef CONFIG_ICJX_INT_ENABLE +static void icjx_interrupt_worker(void *arg) +{ + FAR struct icjx_dev_s *priv = (FAR struct icjx_dev_s *)arg; + uint16_t change_of_input; + uint16_t isr; + ioe_pinset_t irq_match; + int ret; + + /* Read interrupt status register */ + + icjx_read(priv, ICJX_INT_STATUS_A, &isr, ICJX_NOB2); + while (isr != 0) + { + if ((isr & ICJX_ISR_A_DCHI) != 0) + { + ret = icjx_read(priv, ICJX_CHNG_MSG_A, &change_of_input, + ICJX_NOB2); + if (ret == OK) + { + irq_match = change_of_input & priv->callback.pinset; + if (irq_match != 0) + { + /* Change of input.. perform the callback */ + + priv->callback.function(&priv->dev, irq_match, + priv->callback.arg); + } + } + } + + /* Clear interrupt and check ISR again */ + + icjx_write(priv, ICJX_CTRL_WORD_4, ICJX_CTRL_WORD_4_EOI, ICJX_NOB1); + icjx_read(priv, ICJX_INT_STATUS_A, &isr, ICJX_NOB2); + } +} + +/**************************************************************************** + * Name: icjx_interrupt + * + * Description: + * Handle GPIO interrupt events (this function executes in the + * context of the interrupt). + * + ****************************************************************************/ + +static int icjx_interrupt(int irq, FAR void *context, FAR void *arg) +{ + FAR struct icjx_dev_s *priv = (FAR struct icjx_dev_s *)arg; + + /* Create HP work to handle the interrupt. We do not want to do + * this in the interrupt handler because SPI communication speed. + */ + + DEBUGASSERT(work_available(&priv->work)); + DEBUGVERIFY(work_queue(HPWORK, &priv->work, icjx_interrupt_worker, + (void *)priv, 0)); + + return OK; +} + +#endif /* CONFIG_ICJX_INT_ENABLE */ +#endif /* CONFIG_IOEXPANDER_INT_ENABLE */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: icjx_initialize + * + * Description: + * Instantiate and configure the ICJXxx device driver to use the + * provided SPI device instance. + * + * Input Parameters: + * spi - A SPI driver instance + * config - Persistent board configuration data + * + * Returned Value: + * an ioexpander_dev_s instance on success, NULL on failure. + * + ****************************************************************************/ + +FAR struct ioexpander_dev_s *icjx_initialize(FAR struct spi_dev_s *spi, + FAR struct icjx_config_s *config) +{ + FAR struct icjx_dev_s *priv; + uint8_t regval; + int ret; + +#ifdef CONFIG_ICJX_MULTIPLE + /* Allocate the device state structure */ + + priv = kmm_zalloc(sizeof(struct icjx_dev_s)); + if (!priv) + { + gpioerr("ERROR: Failed to allocate driver instance\n"); + return NULL; + } +#else + /* Use the one-and-only I/O Expander driver instance */ + + priv = &g_icjx; +#endif + + /* Initialize the device state structure */ + + priv->dev.ops = &g_icjx_ops; + priv->spi = spi; + priv->config = config; + priv->outpins = 0; + priv->outstate = 0; + priv->irqpins = 0; + +#ifdef CONFIG_ICJX_INT_ENABLE + config->attach(config, icjx_interrupt, priv); + config->enable(config, true); +#endif + + nxmutex_init(&priv->lock); + + /* Set pull up/down based on expander configuration. This is the first + * time we are accessing the expander therefore we do not have to worry + * about reading the register content first. + */ + + regval = (config->current_src << 4) | config->current_src; + + ret = icjx_write(priv, ICJX_CTRL_WORD_2_A, regval, ICJX_NOB1); + if (ret < 0) + { + gpioerr("ERROR: Could write to ICJX_CTRL_WORD_2_A: %d!\n", ret); + goto err; + } + + ret = icjx_write(priv, ICJX_CTRL_WORD_2_B, regval, ICJX_NOB1); + if (ret < 0) + { + gpioerr("ERROR: Could write to ICJX_CTRL_WORD_2_B: %d!\n", ret); + goto err; + } + + /* Bypass filters as those are not yet supported. */ + + regval = ICJX_CTRL_WORD_1_BYP0 | ICJX_CTRL_WORD_1_BYP1; + ret = icjx_write(priv, ICJX_CTRL_WORD_1_A, regval, ICJX_NOB1); + if (ret < 0) + { + gpioerr("ERROR: Could write to ICJX_CTRL_WORD_1_A: %d!\n", ret); + goto err; + } + + ret = icjx_write(priv, ICJX_CTRL_WORD_1_B, regval, ICJX_NOB1); + if (ret < 0) + { + gpioerr("ERROR: Could write to ICJX_CTRL_WORD_1_B: %d!\n", ret); + goto err; + } + + /* Clear initial interrupts if any */ + + icjx_write(priv, ICJX_CTRL_WORD_4, ICJX_CTRL_WORD_4_EOI, ICJX_NOB1); + + return &priv->dev; + +err: + nxmutex_destroy(&priv->lock); +#ifdef CONFIG_ICJX_MULTIPLE + kmm_free(priv); +#endif + return NULL; +} + +#endif /* CONFIG_IOEXPANDER_ICJX */ diff --git a/drivers/ioexpander/icjx.h b/drivers/ioexpander/icjx.h new file mode 100644 index 0000000000000..550924394c091 --- /dev/null +++ b/drivers/ioexpander/icjx.h @@ -0,0 +1,126 @@ +/**************************************************************************** + * drivers/ioexpander/icjx.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __DRIVERS_IOEXPANDER_ICJX_H +#define __DRIVERS_IOEXPANDER_ICJX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#if defined(CONFIG_IOEXPANDER) && defined(CONFIG_IOEXPANDER_ICJX) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Prerequisites: + * CONFIG_SPI + * SPI support is required + * CONFIG_IOEXPANDER + * Enables I/O expander support + * + * CONFIG_IOEXPANDER_ICJX + * Enables support for the ICJX driver (Needs CONFIG_INPUT) + * CONFIG_ICJX_MULTIPLE + * Can be defined to support multiple ICJX devices on board. + */ + +#ifndef CONFIG_SPI +# error "CONFIG_SPI is required by ICJX" +#endif + +/* iC-JX Registers **********************************************************/ + +#define ICJX_INPUT_A 0x00 +#define ICJX_INPUT_B 0x01 +#define ICJX_CHNG_MSG_A 0x02 +#define ICJX_CNNG_MSG_B 0x03 +#define ICJX_INT_STATUS_A 0x04 +#define ICJX_INT_STATUS_B 0x05 +#define ICJX_OVERCURR_MSG_A 0x06 +#define ICJX_OVERCURR_MSG_B 0x07 +#define ICJX_OVERCURR_STATUS_A 0x08 +#define ICJX_OVERCURR_STATUS_B 0x09 +#define ICJX_ADC_DATA_1 0x0A +#define ICJX_ADC_DATA_2 0x0B +#define ICJX_OUTPUT_A 0x0C +#define ICJX_OUTPUT_B 0x0D +#define ICJX_FLASH_PULSE_A 0x0E +#define ICJX_FLASH_PULSE_B 0x0F +#define ICJX_CHNG_INT_EN_A 0x10 +#define ICJX_CHNG_INT_EN_B 0x11 +#define ICJX_OVERCURR_INT_EN_A 0x12 +#define ICJX_OVERCURR_INT_EN_B 0x13 +#define ICJX_CTRL_WORD_1_A 0x14 +#define ICJX_CTRL_WORD_1_B 0x15 +#define ICJX_CTRL_WORD_2_A 0x16 +#define ICJX_CTRL_WORD_2_B 0x17 +#define ICJX_CTRL_WORD_3_A 0x18 +#define ICJX_CTRL_WORD_3_B 0x19 +#define ICJX_CTRL_WORD_4 0x1A +#define ICJX_CTRL_WORD_5 0x1B +#define ICJX_CTRL_WORD_6 0x1C +#define ICJX_DEV_ID 0x1D +#define ICJX_TEST_1 0x1E +#define ICJX_TEST_2 0x1F + +/* Control Word 1 */ + +#define ICJX_CTRL_WORD_1_BYP0 (1 << 3) +#define ICJX_CTRL_WORD_1_BYP1 (1 << 7) + +/* Control Word 2 */ + +#define ICJX_CTRL_WORD_2_NIOL (1 << 3) +#define ICJX_CTRL_WORD_2_NIOH (1 << 7) + +/* Control Word 4 */ + +#define ICJX_CTRL_WORD_4_EOI (1 << 7) + +/* Interrupt Status Register A */ + +#define ICJX_ISR_A_SCS (1 << 0) +#define ICJX_ISR_A_ET1 (1 << 1) +#define ICJX_ISR_A_ET2 (1 << 2) +#define ICJX_ISR_A_ISCI (1 << 4) +#define ICJX_ISR_A_IET1 (1 << 5) +#define ICJX_ISR_A_IET2 (1 << 6) +#define ICJX_ISR_A_DCHI (1 << 7) + +/* Interrupt Status Register B */ + +#define ICJX_ISR_B_USA (1 << 0) +#define ICJX_ISR_B_USD (1 << 1) +#define ICJX_ISR_B_EOC (1 << 2) +#define ICJX_ISR_B_IUSA (1 << 4) +#define ICJX_ISR_B_IUSD (1 << 5) +#define ICJX_ISR_B_ISD (1 << 6) +#define ICJX_ISR_B_IOEC (1 << 7) + +#endif /* CONFIG_IOEXPANDER && CONFIG_IOEXPANDER_ICJX */ +#endif /* __DRIVERS_IOEXPANDER_ICJX_H */ diff --git a/drivers/ioexpander/pcf8574.c b/drivers/ioexpander/pcf8574.c index 8245da7d00129..2e16a0fe1ba4e 100644 --- a/drivers/ioexpander/pcf8574.c +++ b/drivers/ioexpander/pcf8574.c @@ -939,7 +939,6 @@ static void pcf8574_irqworker(void *arg) /* Re-start the poll timer */ - sched_lock(); ret = wd_start(&priv->wdog, PCF8574_POLLDELAY, pcf8574_poll_expiry, (wdparm_t)priv); if (ret < 0) @@ -951,10 +950,6 @@ static void pcf8574_irqworker(void *arg) /* Re-enable interrupts */ priv->config->enable(priv->config, true); - -#ifdef CONFIG_PCF8574_INT_POLL - sched_unlock(); -#endif } #endif diff --git a/drivers/ioexpander/tca64xx.c b/drivers/ioexpander/tca64xx.c index 91c9c517e3d11..f0ca5e8731007 100644 --- a/drivers/ioexpander/tca64xx.c +++ b/drivers/ioexpander/tca64xx.c @@ -1212,7 +1212,6 @@ static void tca64_irqworker(void *arg) /* Re-start the poll timer */ - sched_lock(); ret = wd_start(&priv->wdog, TCA64XX_POLLDELAY, tca64_poll_expiry, (wdparm_t)priv); if (ret < 0) @@ -1224,10 +1223,6 @@ static void tca64_irqworker(void *arg) /* Re-enable interrupts */ priv->config->enable(priv->config, true); - -#ifdef CONFIG_TCA64XX_INT_POLL - sched_unlock(); -#endif } #endif diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index f2582dc40d113..05b5e6a53dc24 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -25,12 +25,12 @@ config DEV_ASCII config DEV_RPMSG bool "RPMSG Device Client Support" default n - depends on RPTUN + depends on RPMSG config DEV_RPMSG_SERVER bool "RPMSG Device Server Support" default n - depends on RPTUN + depends on RPMSG choice prompt "Select OP-TEE dev implementation" @@ -74,12 +74,12 @@ config DRVR_MKRD config BLK_RPMSG bool "RPMSG Block Client Support" default n - depends on RPTUN + depends on RPMSG config BLK_RPMSG_SERVER bool "RPMSG Block Server Support" default n - depends on RPTUN + depends on RPMSG # ARCH needs to support memory access while CPU is running to be able to use # the LWL CONSOLE diff --git a/drivers/misc/rpmsgdev_server.c b/drivers/misc/rpmsgdev_server.c index 856db037ec378..b68ff588c677d 100644 --- a/drivers/misc/rpmsgdev_server.c +++ b/drivers/misc/rpmsgdev_server.c @@ -28,6 +28,7 @@ #include #include +#include #include #include #include @@ -324,15 +325,16 @@ static void rpmsgdev_poll_worker(FAR void *arg) container_of(fds, FAR struct rpmsgdev_device_s, fd); FAR struct rpmsgdev_notify_s msg; - DEBUGASSERT(dev->cfd != 0); - - msg.header.command = RPMSGDEV_NOTIFY; - msg.revents = fds->revents; - msg.fds = dev->cfd; + if (dev->cfd != 0) + { + msg.header.command = RPMSGDEV_NOTIFY; + msg.revents = fds->revents; + msg.fds = dev->cfd; - fds->revents = 0; + fds->revents = 0; - rpmsg_send(&server->ept, &msg, sizeof(msg)); + rpmsg_send(&server->ept, &msg, sizeof(msg)); + } } /**************************************************************************** diff --git a/drivers/misc/rwbuffer.c b/drivers/misc/rwbuffer.c index 009756c1a027a..8e57625dcfdda 100644 --- a/drivers/misc/rwbuffer.c +++ b/drivers/misc/rwbuffer.c @@ -141,19 +141,11 @@ static void rwb_wrflush(FAR struct rwbuffer_s *rwb) { size_t padblocks; + DEBUGASSERT(rwb->wrblockstart % rwb->wralignblocks == 0); + finfo("Flushing: blockstart=0x%08lx nblocks=%d from buffer=%p\n", (long)rwb->wrblockstart, rwb->wrnblocks, rwb->wrbuffer); - padblocks = rwb->wrblockstart % rwb->wralignblocks; - if (padblocks) - { - memmove(rwb->wrbuffer + padblocks * rwb->blocksize, - rwb->wrbuffer, rwb->wrnblocks * rwb->blocksize); - rwb->wrblockstart -= padblocks; - rwb->wrnblocks += padblocks; - rwb_read_(rwb, rwb->wrblockstart, padblocks, rwb->wrbuffer); - } - padblocks = rwb->wrnblocks % rwb->wralignblocks; if (padblocks) { @@ -326,40 +318,11 @@ static ssize_t rwb_writebuffer(FAR struct rwbuffer_s *rwb, nblocks -= ncopy; } - /* 5. We update a portion at the beginning of the write buffer */ - - else /* if (rwb->wrblockstart >= startblock && wrbend >= newend) */ - { - FAR uint8_t *dest; - FAR const uint8_t *src; - size_t ncopy; - - DEBUGASSERT(rwb->wrblockstart >= startblock && wrbend >= newend); - - /* Move the cached data to the end of the write buffer */ - - ncopy = rwb->wrblockstart - startblock; - if (ncopy > rwb->wrmaxblocks - rwb->wrnblocks) - { - ncopy = rwb->wrmaxblocks - rwb->wrnblocks; - } - - dest = rwb->wrbuffer + ncopy * rwb->blocksize; - memmove(dest, rwb->wrbuffer, ncopy * rwb->blocksize); - - rwb->wrblockstart -= ncopy; - rwb->wrnblocks += ncopy; - - /* Copy the data from the updating region to the beginning - * of the write buffer. - */ - - ncopy = newend - rwb->wrblockstart; - src = wrbuffer + (nblocks - ncopy) * rwb->blocksize; - memcpy(rwb->wrbuffer, src, ncopy * rwb->blocksize); - - nblocks -= ncopy; - } + /* 5. We update a portion at the beginning of the write buffer. + * For writes that are ahead of the writerbuffer, we first flush and + * then process the write in the new writebuffer to ensure that each + * wrblockstart is aligned according to wralignblocks. + */ } /* Use the block cache unless the buffer size is bigger than block cache */ @@ -372,17 +335,42 @@ static ssize_t rwb_writebuffer(FAR struct rwbuffer_s *rwb, return ret; } } - else if (nblocks) + + while (nblocks > 0) { + size_t padblocks; + size_t remain = nblocks; + /* Flush the write buffer */ rwb_wrflush(rwb); + /* Get the alignment padding of startblock, and read the contents + * of the padding area, ensure that wrblockstart is aligned + * according to wralignblocks. + */ + + padblocks = startblock % rwb->wralignblocks; + rwb->wrblockstart = startblock - padblocks; + rwb->wrnblocks = padblocks; + rwb_read_(rwb, rwb->wrblockstart, padblocks, rwb->wrbuffer); + + if (remain > rwb->wrmaxblocks - padblocks) + { + remain = rwb->wrmaxblocks - padblocks; + } + /* Buffer the data in the write buffer */ - memcpy(rwb->wrbuffer, wrbuffer, nblocks * rwb->blocksize); - rwb->wrblockstart = startblock; - rwb->wrnblocks = nblocks; + memcpy(rwb->wrbuffer + padblocks * rwb->blocksize, wrbuffer, + remain * rwb->blocksize); + rwb->wrnblocks += remain; + + /* Update remain state of write buffer */ + + nblocks -= remain; + startblock += remain; + wrbuffer += remain * rwb->blocksize; } if (rwb->wrnblocks > 0) @@ -989,7 +977,10 @@ static ssize_t rwb_read_(FAR struct rwbuffer_s *rwb, off_t startblock, * the user buffer. */ - ret = rwb->rhreload(rwb->dev, rdbuffer, startblock, nblocks); + if (nblocks) + { + ret = rwb->rhreload(rwb->dev, rdbuffer, startblock, nblocks); + } } return ret; diff --git a/drivers/mmcsd/mmcsd_sdio.c b/drivers/mmcsd/mmcsd_sdio.c index 68ee8ff5d26a2..a4073fa263d7d 100644 --- a/drivers/mmcsd/mmcsd_sdio.c +++ b/drivers/mmcsd/mmcsd_sdio.c @@ -3395,7 +3395,7 @@ static int mmcsd_sdinitialize(FAR struct mmcsd_state_s *priv) mmcsd_decode_scr(priv, scr); - if ((priv->caps & SDIO_CAPS_4BIT_ONLY) != 0) + if ((priv->caps & SDIO_CAPS_4BIT) != 0) { /* Select width (4-bit) bus operation (if the card supports it) */ diff --git a/drivers/modem/alt1250/alt1250.c b/drivers/modem/alt1250/alt1250.c index 336f941fd72aa..6280515031ad1 100644 --- a/drivers/modem/alt1250/alt1250.c +++ b/drivers/modem/alt1250/alt1250.c @@ -640,6 +640,7 @@ static int alt1250_power_control(FAR struct alt1250_dev_s *dev, #ifdef CONFIG_PM case LTE_CMDID_STOPAPI: + case LTE_CMDID_RESTARTAPI: case LTE_CMDID_SUSPEND: alt1250_receive_daemon_response(req); break; @@ -1380,6 +1381,19 @@ static int alt1250_pm_prepare(struct pm_callback_s *cb, int domain, ret = alt1250_send_daemon_request(ALT1250_EVTBIT_STOPAPI); + if (ret) + { + return ERROR; + } + else + { + return OK; + } + } + else if (pmstate == PM_NORMAL) + { + ret = alt1250_send_daemon_request(ALT1250_EVTBIT_RESTARTAPI); + if (ret) { return ERROR; diff --git a/drivers/modem/alt1250/altcom_lwm2m_hdlr.c b/drivers/modem/alt1250/altcom_lwm2m_hdlr.c index 21c88ea17af96..eb7a8b1ddcb56 100644 --- a/drivers/modem/alt1250/altcom_lwm2m_hdlr.c +++ b/drivers/modem/alt1250/altcom_lwm2m_hdlr.c @@ -26,11 +26,18 @@ #include #include #include +#include #include #include "altcom_lwm2m_hdlr.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NO_MEMBER (-1) + /**************************************************************************** * Private Function Prototypes ****************************************************************************/ @@ -328,17 +335,16 @@ static int32_t stop_ov_request_hndl(FAR uint8_t *pktbuf, size_t pktsz, } /**************************************************************************** - * name: fwup_srvop_handle + * name: fwupdate_notice_hndl ****************************************************************************/ -static int32_t fwup_srvop_handle(FAR uint8_t *pktbuf, size_t pktsz, +static int32_t fwupdate_notice_hndl(FAR uint8_t *pktbuf, size_t pktsz, FAR void **cb_args, size_t arglen) { uint8_t *ep; FAR int *event = (FAR int *)&cb_args[0]; /* Expected unsolicited event - * %LWM2MOPEV: [,.... * %LWM2MEV: [,.... */ @@ -352,13 +358,31 @@ static int32_t fwup_srvop_handle(FAR uint8_t *pktbuf, size_t pktsz, } /**************************************************************************** - * name: fwupdate_notice_hndl + * name: parse_inst_number ****************************************************************************/ -static int32_t fwupdate_notice_hndl(FAR uint8_t *pktbuf, size_t pktsz, - FAR void **cb_args, size_t arglen) +static int parse_inst_number(FAR uint8_t **buf, FAR size_t *bufsz) { - return fwup_srvop_handle(pktbuf, pktsz, cb_args, arglen); + int ret = 0; + + if (!isdigit(**buf)) + { + return NO_MEMBER; + } + + while (*bufsz) + { + if (!isdigit(**buf)) + { + break; + } + + ret = ret * 10 + ((**buf) - '0'); + (*bufsz)--; + (*buf)++; + } + + return ret; } /**************************************************************************** @@ -366,9 +390,57 @@ static int32_t fwupdate_notice_hndl(FAR uint8_t *pktbuf, size_t pktsz, ****************************************************************************/ static int32_t server_op_notice_hndl(FAR uint8_t *pktbuf, size_t pktsz, - FAR void **cb_args, size_t arglen) + FAR void **cb_args, size_t arglen) { - return fwup_srvop_handle(pktbuf, pktsz, cb_args, arglen); + int i; + FAR int *event = (FAR int *)&cb_args[0]; + FAR int *srvid = (FAR int *)&cb_args[1]; + FAR int *inst = (FAR int *)cb_args[2]; + + /* The content of "inst" is a type of struct lwm2mstub_instance_s in fact. + * But actually it is the same as int[4]. + * To make simpler logic, inst is defined as int[4] (int pointer). + */ + + /* Set invalid value as initialize */ + + *srvid = -1; + inst[0] = -1; + inst[1] = -1; + inst[2] = -1; + inst[3] = -1; + + /* Expected unsolicited event + * %LWM2MOPEV: [,[],[], + * [],[], + * [],[][,]] + */ + + *event = parse_inst_number(&pktbuf, &pktsz); + if (*event < 0) + { + return ERROR; + } + + if (pktsz > 0 && pktbuf[0] == ',') + { + pktsz--; + pktbuf++; + + *srvid = parse_inst_number(&pktbuf, &pktsz); + + for (i = 0; i < 4 && pktsz > 0 && pktbuf[0] == ','; i++) + { + /* Skip comma */ + + pktbuf++; + pktsz--; + + inst[i] = parse_inst_number(&pktbuf, &pktsz); + } + } + + return OK; } /**************************************************************************** diff --git a/drivers/mtd/CMakeLists.txt b/drivers/mtd/CMakeLists.txt index bf8307ffdf32f..af7fbcdeaf4c4 100644 --- a/drivers/mtd/CMakeLists.txt +++ b/drivers/mtd/CMakeLists.txt @@ -85,6 +85,10 @@ if(CONFIG_MTD) list(APPEND SRCS at24xx.c) endif() + if(CONFIG_MTD_AT25EE) + list(APPEND SRCS at25ee.c) + endif() + if(CONFIG_MTD_AT45DB) list(APPEND SRCS at45db.c) endif() diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 136272bdff682..ac27e511f4f5b 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -33,7 +33,8 @@ config MTD_PARTITION is described in: include/nuttx/mtd/mtd.h - FAR struct mtd_dev_s *mtd_partition(FAR struct mtd_dev_s *mtd, off_t offset, off_t nblocks); + FAR struct mtd_dev_s *mtd_partition(FAR struct mtd_dev_s *mtd, + off_t offset, off_t nblocks); Each call to mtd_partition() will create a new MTD driver instance managing the sub-region of flash beginning at 'offset' (in blocks) @@ -115,7 +116,8 @@ config MTD_READAHEAD select DRVR_INVALIDATE select DRVR_READBYTES ---help--- - Build the mtd_rwbuffer layer and enable support for read-ahead buffering. + Build the mtd_rwbuffer layer and enable support for read-ahead + buffering. if MTD_READAHEAD @@ -193,6 +195,13 @@ config MTD_CONFIG_FAIL_SAFE This replaces the drivers/mtd/mtd_config, which is resilient to power loss. +config MTD_WRITE_ALIGN_SIZE + int "align size [1,2,4,8,16] for per write operation" + default 1 + depends on MTD_CONFIG_FAIL_SAFE + ---help--- + align size will be one of 1,2,4,8,16 + endif # MTD_CONFIG comment "MTD Device Drivers" @@ -269,17 +278,82 @@ config MTD_NAND_EMBEDDEDECC only one supported) is Micron, 4-bit ECC, device size = 1Gb or 2Gb or 4Gb. +config MTD_NAND_RAM + bool "Enable virtual NAND Flash" + default n + ---help--- + Enable a virtual NAND Flash device emulated from RAM in the simulator. + +if MTD_NAND_RAM + +config MTD_NAND_RAM_SIZE + int "Size of the virtual NAND Flash in MB." + default 2 + ---help--- + Size of the virtual NAND Flash in megabytes. + +config MTD_NAND_RAM_DEBUG + bool "Enable debugging of virtual NAND Flash." + default n + ---help--- + Enables debug info being written to syslog for virtual NAND Flash + device emulated from RAM in the simulator. + +config MTD_NAND_RAM_DEBUG_LEVEL + int "Debugging level of virtual NAND Flash raw lower half operations." + depends on MTD_NAND_RAM_DEBUG + default 1 + range 1 3 + ---help--- + 1 - Log every instruction. + 2 - Log every 5 instructions. + 3 - Log every 10 instructions. + +config MTD_NAND_RAM_STATUS + int "Log status of virtual NAND Flash." + depends on MTD_NAND_RAM_DEBUG + default 3 + range 1 8 + ---help--- + 1 - Log every instruction. + 2 - Log every 5 instructions. + 3 - Log every 10 instructions. + 4 - Log every 50 instructions. + 5 - Log every 100 instructions. + 6 - Log every 500 instructions. + 7 - Log every 1000 instructions. + 8 - Log every 5000 instructions. + +endif #MTD_NAND_RAM + +config MTD_NAND_WRAPPER + bool "Enable logging wrapper for NAND flash upper half operations." + default n + +if MTD_NAND_WRAPPER + +config MTD_NAND_WRAPPER_DEBUG_LEVEL + int "Log level of upper half of virtual NAND Flash." + default 1 + range 1 3 + ---help--- + 1 - Log every instruction. + 2 - Log every 5 instructions. + 3 - Log every 10 instructions. + +endif # MTD_NAND_WRAPPER + endif # MTD_NAND config RPMSGMTD bool "MTD RPMSG Client Enable" default n - depends on RPTUN + depends on RPMSG config RPMSGMTD_SERVER bool "MTD RPMSG Server Enable" default n - depends on RPTUN + depends on RPMSG config RAMMTD bool "RAM-based MTD driver" @@ -350,7 +424,7 @@ config NULLMTD_BLOCKSIZE default 512 config NULLMTD_ERASESIZE - int "MTD null detault erase block size" + int "MTD null default erase block size" default 4096 config NULLMTD_ERASESTATE @@ -382,10 +456,10 @@ config AT24XX_SIZE int "AT24xx size (Kbit)" default 64 ---help--- - This is the XX in the AT24Cxx part number. For example, if you have a - AT 24C512, then the correct value is 512. This value is also the capacity - of the part in kilobits. For example, the 24C512 supports 512 Kbits or - 512 /8 = 64 KiB. + This is the XX in the AT24Cxx part number. For example, if you have + an AT24C64, then the correct value is 64. + This value is also the capacity of the part in kilobits. + For example, the 64 supports 64 Kbits or 64/8 = 8 KiB. config AT24XX_ADDR hex "AT24XX I2C address" @@ -403,8 +477,8 @@ config AT24XX_EXTENDED bool "Extended memory" default n ---help--- - If the device supports extended memory, then this operation may be set - to enabled the MTDIOC_EXTENDED ioctl() operation. When the + If the device supports extended memory, then this operation may be + set to enable the MTDIOC_EXTENDED ioctl() operation. When the extended operation is selected, calls to the driver read method will return data from the extended memory region. @@ -422,12 +496,107 @@ config AT24XX_FREQUENCY int "AT24xx I2C bus frequency" default 100000 ---help--- - Set the I2C frequency to use when accessing the AT24CXX EEPROM. This value - must represent a valid I2C speed (normally less than 400.000) or the driver - might fail. + Set the I2C frequency to use when accessing the AT24CXX EEPROM. + This value must represent a valid I2C speed (normally less than + 400.000) or the driver might fail. endif # MTD_AT24XX +config MTD_AT25EE + bool "SPI-based AT25xx EEPROM" + default n + select SPI + select MTD_BYTE_WRITE + ---help--- + Build support for SPI-based AT25xx type EEPROMs. MTD on EEPROM can + perform poorly, so it is possible only usable if the EEPROM has a + clock speed 10MHz or higher. EEPROMs that use the same commands as + the 25AA160 should work OK. + +if MTD_AT25EE + +choice + prompt "Block Size" + default USE_NATIVE_AT25EE_BLOCK_SIZE + ---help--- + For applications where a file system is used on the AT25 EEPROM, + the tiny page sizes will result in very inefficient EEPROM usage. + In such cases, it is better if blocks are comprised of "clusters" of + pages so that the file system block size is, say, 128, 256 or + 512 bytes. + + In any event, the block size *must* be an even multiple of the + number of pages and, often, needs to be a factor 2. + + This is up to the user to check! + +config USE_NATIVE_AT25EE_BLOCK_SIZE + bool "Use EEPROM's native block size" + +config MANUALLY_SET_AT25EE_BLOCK_SIZE + bool "Manually set block size" + +endchoice # Block Size + +if MANUALLY_SET_AT25EE_BLOCK_SIZE + +config MANUAL_AT25EE_BLOCK_SIZE + int "Manually-set EEPROM block size" + default 512 + +endif # MANUALLY_SET_BLOCK_SIZE + +config AT25EE_ENABLE_BLOCK_ERASE + bool "Enabled block erase" + default n + ---help--- + EEPROM does not need to be erased before write. However, in some + applications (e.g if an erase verify is wanted, or if a particular + file system requires this) block erase (i.e. writing each byte to + 0xff) can be enabled here. + +config AT25EE_SPIMODE + int "AT25EE SPI Mode" + default 0 + +config AT25EE_SPIFREQUENCY + int "AT25EE SPI Frequency" + default 10000000 + +config AT25EE_START_DELAY + int "AT25EE startdelay" + ---help--- + The delay between CS active and first CLK. In ns. + depends on SPI_DELAY_CONTROL + range 0 1000000 + default 5000 + +config AT25EE_STOP_DELAY + int "AT25EE stopdelay" + ---help--- + The delay between last CLK and CS inactive. In ns. + depends on SPI_DELAY_CONTROL + range 0 1000000 + default 5000 + +config AT25EE_CS_DELAY + int "AT25EE csdelay" + ---help--- + The delay between CS inactive and CS active again. In ns. + depends on SPI_DELAY_CONTROL + range 0 1000000 + default 5000 + +config AT25EE_IFDELAY + int "AT25EE ifdelay" + ---help--- + The delay between frames. In ns. + depends on SPI_DELAY_CONTROL + range 0 1000000 + default 5000 + +endif # MTD_AT25EE + config MTD_AT25 bool "SPI-based AT25 FLASH" default n @@ -502,18 +671,20 @@ config M25P_MANUFACTURER hex "M25P manufacturers ID" default 0x20 ---help--- - Various manufacturers may have produced the parts. 0x20 is the manufacturer ID - for the STMicro MP25x serial FLASH. If, for example, you are using the a Macronix - International MX25 serial FLASH, the correct manufacturer ID would be 0xc2. + Various manufacturers may have produced the parts. + 0x20 is the manufacturer ID for the STMicro MP25x serial FLASH. + If, for example, you are using the a Macronix International MX25 + serial FLASH, the correct manufacturer ID would be 0xc2. config M25P_MEMORY_TYPE hex "M25P memory type ID" default 0x20 ---help--- - The memory type for M25 "P" series is 0x20, but the driver also supports "F" series - devices, such as the EON EN25F80 part which adds a 4K sector erase capability. The - memory type for "F" series parts from EON is 0x31. The 4K sector erase size will - automatically be enabled when filesystems that can use it are enabled, such as SMART. + The memory type for M25 "P" series is 0x20, but the driver also + supports "F" series devices, such as the EON EN25F80 part which adds + a 4K sector erase capability. The memory type for "F" series parts + from EON is 0x31. The 4K sector erase size will automatically be + enabled when filesystems that can use it are enabled, such as SMART. config MT25Q_MEMORY_TYPE hex "MT25Q memory type ID" @@ -527,7 +698,8 @@ config M25P_SUBSECTOR_ERASE ---help--- Some devices (such as the EON EN25F80) support a smaller erase block size (4K vs 64K). This option enables support for sub-sector erase. - The SMART file system can take advantage of this option if it is enabled. + The SMART file system can take advantage of this option if it is + enabled. endif # MTD_M25P @@ -558,7 +730,8 @@ config MX25L_SUBSECTOR_ERASE ---help--- Some devices (such as the EON EN25F80) support a smaller erase block size (4K vs 64K). This option enables support for sub-sector erase. - The SMART file system can take advantage of this option if it is enabled. + The SMART file system can take advantage of this option if it is + enabled. config MX25L_DEBUG bool "Enable driver debug features" @@ -672,7 +845,8 @@ config MTD_W25QXXXJV bool "QuadSPI-based Winbond W25QXXXJV family FLASH" default n ---help--- - Support the W25Q016JV, W25Q032JV, W25Q064JV, W25Q128JV, W25Q256JV, W25Q512JV, W25Q01JV + Support the W25Q016JV, W25Q032JV, W25Q064JV, W25Q128JV, W25Q256JV, + W25Q512JV, W25Q01JV if MTD_W25QXXXJV @@ -744,13 +918,14 @@ config MTD_SMART bool "Sector Mapped Allocation for Really Tiny (SMART) Flash support" default n ---help--- - The MP25x series of Flash devices are typically very small and have a very large - erase block size. This causes issues with the standard Flash Translation Layer - block driver since it tries to allocate a RAM block the size of a flash erase - block, which is typically 64K. This block driver uses a different approach - to sacrifice performance for RAM memory footprint by saving data in sectors - (typically 2K - 4K based on memory size) and relocating sectors as needed when - an erase block needs to be erased. + The MP25x series of Flash devices are typically very small and have a + very large erase block size. This causes issues with the standard + Flash Translation Layer block driver since it tries to allocate a RAM + block the size of a flash erase block, which is typically 64K. + This block driver uses a different approach to sacrifice performance + for RAM memory footprint by saving data in sectors (typically 2K - 4K + based on memory size) and relocating sectors as needed when an erase + block needs to be erased. if MTD_SMART @@ -766,9 +941,9 @@ config MTD_SMART_SECTOR_SIZE int "SMART Device sector size" default 1024 ---help--- - Sets the size of a single allocation on the SMART device. Larger sector sizes - reduce overhead per sector, but cause more wasted space with a lot of smaller - files. + Sets the size of a single allocation on the SMART device. + Larger sector sizes reduce overhead per sector, but cause more wasted + space with a lot of smaller files. config MTD_SMART_WRITEBUFFER bool "Enable SMART write buffering" @@ -785,10 +960,11 @@ config MTD_SMART_WEAR_LEVEL depends on MTD_SMART default y ---help--- - Adds extra logic and RAM to guarantee equal wear leveling of the FLASH - device by recording and monitoring erase block operations and selecting - sector allocations to ensure all erase blocks are worn evenly. This will - evenly wear both dynamic and static data on the device. + Adds extra logic and RAM to guarantee equal wear leveling of the + FLASH device by recording and monitoring erase block operations and + selecting sector allocations to ensure all erase blocks are worn + evenly. This will evenly wear both dynamic and static data on the + device. if MTD_SMART_WEAR_LEVEL && !SMART_CRC_16 @@ -796,11 +972,11 @@ config MTD_SMART_CONVERT_WEAR_FORMAT bool "Convert existing non wear leveling FLASH to wear leveling" default n ---help--- - Adds a little extra code which detects an existing SMART format on a device - that was created prior to the wear leveling implementation. This conversion - only works if either no CRC is being used or if CRC-8 is being used as other - CRC versions use a different header format and require a mksmartfs on the - device even if an existing format is there. + Adds a little extra code which detects an existing SMART format on a + device that was created prior to the wear leveling implementation. + This conversion only works if either no CRC is being used or if CRC-8 + is being used as other CRC versions use a different header format and + require a mksmartfs on the device even if an existing format is there endif # MTD_SMART_WEAR_LEVEL && !SMART_CRC_16 @@ -809,17 +985,19 @@ config MTD_SMART_ENABLE_CRC depends on MTD_SMART default n ---help--- - Enables logic to compute and validate a CRC for logical sectors. The - CRC is calculated for all bytes in the logical sector. The CRC size is - selectable (8-bit, 16-bit, 32-bit). For added protection, larger CRCs should - be used with larger (2K - 4K) sector sizes. Enabling CRC protection will - cause increased sector relocation and increased erase block erasures since - directory and wear-level status updates can no longer be performed in-place - and mandate re-writing the information to a new sector. + Enables logic to compute and validate a CRC for logical sectors. + The CRC is calculated for all bytes in the logical sector. + The CRC size is selectable (8-bit, 16-bit, 32-bit). For added + protection, larger CRCs should be used with larger (2K - 4K) sector + sizes. Enabling CRC protection will cause increased sector + relocation and increased erase block erasures since directory and + wear-level status updates can no longer be performed in-place and + mandate re-writing the information to a new sector. - An 8-bit CRC protection scheme can be added to an existing non-CRC formatted - SMART volume without needing to reformat the drive. As sectors are re-written - or relocated, they will be converted to CRC protected sectors. + An 8-bit CRC protection scheme can be added to an existing non-CRC + formatted SMART volume without needing to reformat the drive. As + sectors are re-written or relocated, they will be converted to CRC + protected sectors. choice prompt "CRC level selection" @@ -827,9 +1005,9 @@ choice default SMART_CRC_8 ---help--- Select the level of CRC protection implemented in the SMART MTD layer. - Smaller CRC selection uses less overhead per logical sectors, but also has - a higher probability of not detecting multiple bit errors. Devices with - larger logical sector sizes should use a larger CRC. + Smaller CRC selection uses less overhead per logical sectors, but + also has a higher probability of not detecting multiple bit errors. + Devices with larger logical sector sizes should use a larger CRC. config SMART_CRC_8 bool "CRC-8" @@ -858,52 +1036,54 @@ config MTD_SMART_MINIMIZE_RAM depends on MTD_SMART default 0 ---help--- - Reduces RAM usage in the SMART MTD layer by replacing the 1-for-1 logical to - physical sector map with a smaller cache-based structure. This can save a - considerable amount of RAM on devices with a large sector count, but at the - expense of increased read/write times when a cache miss occurs. If the - requested logical sector has not been cached, then the device will need to be - scanned to located it on the physical medium. + Reduces RAM usage in the SMART MTD layer by replacing the 1-for-1 + logical to physical sector map with a smaller cache-based structure. + This can save a considerable amount of RAM on devices with a large + sector count, but at the expense of increased read/write times when a + cache miss occurs. If the requested logical sector has not been + cached, then the device will need to be scanned to located it on the + physical medium. config MTD_SMART_SECTOR_CACHE_SIZE int "Number of entries in the SMART logical sector cache" depends on MTD_SMART_MINIMIZE_RAM default 512 ---help--- - Sets the size of the cache used for logical to physical sector mapping. A - larger number allows larger files to be "seek"ed randomly without encountering - cache misses. Any files larger than CACH_SIZE * SECTOR_SIZE that are sought - start to end will cause the cache to flush forcing manual scanning of the - MTD device to find the logical to physical mappings. + Sets the size of the cache used for logical to physical sector + mapping. A larger number allows larger files to be "seek"ed randomly + without encountering cache misses. Any files larger than + CACHE_SIZE * SECTOR_SIZE that are sought start to end will cause the + cache to flush forcing manual scanning of the MTD device to find the + logical to physical mappings. config MTD_SMART_SECTOR_PACK_COUNTS bool "Pack free and release counts when possible" depends on MTD_SMART_MINIMIZE_RAM default y ---help--- - For volumes with 16 sectors per erase block or less, this option causes the - free sector and released sector counts used for allocation and garbage - collection to be packed such that two values are stored per byte. For - volumes with 16 sectors per erase block, the 4 LSBs are packed and all of - the high-order bits are packed separately (8 per byte). This squeezes even - more RAM out. + For volumes with 16 sectors per erase block or less, this option + causes the free sector and released sector counts used for allocation + and garbage collection to be packed such that two values are stored + per byte. For volumes with 16 sectors per erase block, the 4 LSBs + are packed and all of the high-order bits are packed separately + (8 per byte). This squeezes even more RAM out. config MTD_SMART_SECTOR_ERASE_DEBUG bool "Track Erase Block erasure counts" depends on MTD_SMART default n ---help--- - Allocates an Erase Block erase count array and keeps track of the number - of erases per erase block. This data is then presented on the procfs - interface. + Allocates an Erase Block erase count array and keeps track of the + number of erases per erase block. This data is then presented on the + procfs interface. config MTD_SMART_ALLOC_DEBUG bool "RAM Allocation Debug" depends on MTD_SMART default n ---help--- - Records all SMART MTD layer allocations for debug purposes and makes them - accessible from the ProcFS interface if it is enabled. + Records all SMART MTD layer allocations for debug purposes and makes + them accessible from the ProcFS interface if it is enabled. endif # MTD_SMART @@ -938,8 +1118,8 @@ config RAMTRON_EMULATE_SECTOR_SHIFT For purpose of the VFAT file system, we emulate them. Specify sector shift value to determine emulated sector size. - The relationship between sector shift value and emulated sector size is - described in the equation: + The relationship between sector shift value and emulated sector size + is described in the equation: RAMTRON_EMULATE_SECTOR_SIZE = (1 << RAMTRON_EMULATE_SECTOR_SHIFT) sector shift value : sector size in bytes @@ -1007,11 +1187,12 @@ config SST25_SLOWWRITE bool default n ---help--- - There used to be a bug in the current code when using the higher speed AAI - write sequence. The nature of the bug is that the WRDI instruction is not - working. At the end of the AAI sequence, the status register continues to - report that the SST25 is write enabled (WEL bit) and in AAI mode (AAI - bit). This has been fixed by David Sidrane! + There used to be a bug in the current code when using the higher + speed AAI write sequence. The nature of the bug is that the WRDI + instruction is not working. At the end of the AAI sequence, the + status register continues to report that the SST25 is write enabled + (WEL bit) and in AAI mode (AAI bit). + This has been fixed by David Sidrane! config SST25_SLOWREAD bool @@ -1026,8 +1207,8 @@ config MTD_SST25XX ---help--- With the 64 MBit and larger parts, SST changed the write mechanism to support page write instead of byte/word write like the smaller parts. - As a result, the SST25 driver is not compatible with the larger density - parts, and the SST25XX driver must be used instead. + As a result, the SST25 driver is not compatible with the larger + density parts, and the SST25XX driver must be used instead. if MTD_SST25XX @@ -1043,15 +1224,16 @@ config SST25XX_MANUFACTURER hex "Manufacturers ID" default 0xBF ---help--- - Various manufacturers may have produced the parts. 0xBF is the manufacturer ID - for the parts manufactured by SST. + Various manufacturers may have produced the parts. 0xBF is the + manufacturer ID for the parts manufactured by SST. config SST25XX_MEMORY_TYPE hex "Memory type ID" default 0x25 ---help--- - The memory type for SST25VF065 series is 0x25, but this can be modified if needed - to support compatible devices from different manufacturers. + The memory type for SST25VF065 series is 0x25, but this can be + modified if needed to support compatible devices from different + manufacturers. endif # MTD_SST25XX @@ -1060,7 +1242,8 @@ config MTD_SST26 default n select SPI ---help--- - These part are also different from SST25 and SST25XX, they support both SPI and QSPI. + These part are also different from SST25 and SST25XX, they support + both SPI and QSPI. if MTD_SST26 @@ -1076,15 +1259,16 @@ config SST26_MANUFACTURER hex "Manufacturers ID" default 0xBF ---help--- - Various manufacturers may have produced the parts. 0xBF is the manufacturer ID - for the parts manufactured by SST. + Various manufacturers may have produced the parts. 0xBF is the + manufacturer ID for the parts manufactured by SST. config SST26_MEMORY_TYPE hex "Memory type ID" default 0x26 ---help--- - The memory type for SST26VF0xx series is 0x26, but this can be modified if needed - to support compatible devices from different manufacturers. + The memory type for SST26VF0xx series is 0x26, but this can be + modified if needed to support compatible devices from different + manufacturers. config SST26_DEBUG bool "Debug output from the SST26 driver" diff --git a/drivers/mtd/Make.defs b/drivers/mtd/Make.defs index 0db6d50965eb4..6956610c3cd90 100644 --- a/drivers/mtd/Make.defs +++ b/drivers/mtd/Make.defs @@ -60,6 +60,15 @@ CSRCS += mtd_nand.c mtd_onfi.c mtd_nandscheme.c mtd_nandmodel.c mtd_modeltab.c ifeq ($(CONFIG_MTD_NAND_SWECC),y) CSRCS += mtd_nandecc.c hamming.c endif + +ifeq ($(CONFIG_MTD_NAND_RAM), y) +CSRCS += mtd_nandram.c +endif + +ifeq ($(CONFIG_MTD_NAND_WRAPPER), y) +CSRCS += mtd_nandwrapper.c +endif + endif ifeq ($(CONFIG_RAMMTD),y) @@ -86,6 +95,10 @@ ifeq ($(CONFIG_MTD_AT24XX),y) CSRCS += at24xx.c endif +ifeq ($(CONFIG_MTD_AT25EE),y) +CSRCS += at25ee.c +endif + ifeq ($(CONFIG_MTD_AT45DB),y) CSRCS += at45db.c endif diff --git a/drivers/mtd/at25ee.c b/drivers/mtd/at25ee.c new file mode 100644 index 0000000000000..45873a7c46cec --- /dev/null +++ b/drivers/mtd/at25ee.c @@ -0,0 +1,1083 @@ +/**************************************************************************** + * drivers/mtd/at25ee.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#ifdef CONFIG_MTD_AT25EE + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_AT25EE_SPIMODE +# define CONFIG_AT25EE_SPIMODE 0 +#endif + +/* EEPROM commands + * High bit of low nibble used for A8 in 25xx040/at25040 products + */ + +#define AT25EE_CMD_WRSR 0x01 +#define AT25EE_CMD_WRITE 0x02 +#define AT25EE_CMD_READ 0x03 +#define AT25EE_CMD_WRDIS 0x04 +#define AT25EE_CMD_RDSR 0x05 +#define AT25EE_CMD_WREN 0x06 + +/* Following commands will be available some day via IOCTLs + * PE 0x42 Page erase (25xx512/1024) + * SE 0xD8 Sector erase (25xx512/1024) + * CE 0xC7 Chip erase (25xx512/1024) + * RDID 0xAB Wake up and read electronic signature (25xx512/1024) + * DPD 0xB9 Sleep (25xx512/1024) + * + * Identification page access for ST devices + * RDID/RDLS 0x83 Read identification page / Read ID page lock status + * WRID/LID 0x82 Write identification page / Lock ID page + */ + +/* SR bits definitions */ + +#define AT25EE_SR_WIP 0x01 /* Write in Progress */ +#define AT25EE_SR_WEL 0x02 /* Write Enable Latch */ +#define AT25EE_SR_BP0 0x04 /* First Block Protect bit */ +#define AT25EE_SR_BP1 0x08 /* Second Block Protect bit */ +#define AT25EE_SR_WPEN 0x80 /* Write Protect Enable */ + +#define AT25EE_DUMMY 0xFF + +/* For applications where a file system is used on the AT25EE, the tiny page + * sizes will result in very inefficient EEPROM usage. In such cases, it is + * better if blocks are comprised of "clusters" of pages so that the file + * system block size is, say, 256 or 512 bytes. + * In any event, the block size *must* be an even multiple of the pages. + */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Device geometry description, compact form (2 bytes per entry) */ + +struct at25ee_geom_s +{ + uint8_t bytes : 4; /* Power of 2 of 128 bytes (0:128 1:256 2:512 etc) */ + uint8_t pagesize : 4; /* Power of 2 of 8 bytes (0:8 1:16 2:32 3:64 etc) */ + uint8_t addrlen : 4; /* Number of bytes in command address field */ + uint8_t flags : 4; /* Addr. management for 25xx040, 1=A8 in inst */ +}; + +/* This type represents the state of the MTD device. The struct mtd_dev_s + * must appear at the beginning of the definition so that you can freely + * cast between pointers to struct mtd_dev_s and struct at25ee_dev_s. + */ + +struct at25ee_dev_s +{ + struct mtd_dev_s mtd; /* MTD interface */ + struct spi_dev_s *spi; /* SPI device where the EEPROM is attached */ + uint32_t size; /* in bytes, expanded from geometry */ + uint16_t pgsize; /* write block size, in bytes, expanded from + * geometry + */ + uint16_t npages; /* numpages, derived from geometry */ + uint16_t addrlen; /* number of BITS in data addresses */ + uint16_t blocksize; /* Block sized to report */ + mutex_t lock; /* file access serialization */ + uint8_t readonly; /* Flags */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void at25ee_lock(FAR struct spi_dev_s *dev); + +/* MTD driver methods */ + +static int at25ee_erase(FAR struct mtd_dev_s *dev, + off_t startblock, + size_t nblocks); +static ssize_t at25ee_bread(FAR struct mtd_dev_s *dev, + off_t startblock, + size_t nblocks, FAR uint8_t *buf); +static ssize_t at25ee_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, + size_t nblocks, FAR const uint8_t *buf); +static ssize_t at25ee_read(FAR struct mtd_dev_s *dev, off_t offset, + size_t nbytes, FAR uint8_t *buf); +static ssize_t at25ee_write(FAR struct mtd_dev_s *dev, off_t offset, + size_t nbytes, FAR const uint8_t *buf); +static int at25ee_ioctl(FAR struct mtd_dev_s *dev, int cmd, + unsigned long arg); +static void at25ee_writepage(FAR struct at25ee_dev_s *priv, uint32_t devaddr, + FAR const uint8_t *data, size_t len); +static void at25ee_writeenable(FAR struct at25ee_dev_s *priv, int enable); +static void at25ee_waitwritecomplete(struct at25ee_dev_s *priv); +static void at25ee_sendcmd(FAR struct spi_dev_s *spi, uint8_t cmd, + uint8_t addrlen, uint32_t addr); +static inline void at25ee_unlock(FAR struct spi_dev_s *dev); +static void at25ee_lock(FAR struct spi_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Supported device geometries. + * One geometry can fit more than one device. + * The user will use an enum'd index from include/eeprom/spi_xx25xx.h + */ + +static const struct at25ee_geom_s g_at25ee_devices[] = +{ + /* Microchip devices */ + + { + 0, 1, 1, 0 + }, /* 25xx010A 128 16 1 */ + { + 1, 1, 1, 0 + }, /* 25xx020A 256 16 1 */ + { + 2, 1, 1, 1 + }, /* 25xx040 512 16 1+bit */ + { + 3, 1, 1, 0 + }, /* 25xx080 1024 16 1 */ + { + 3, 2, 2, 0 + }, /* 25xx080B 1024 32 2 */ + { + 4, 1, 2, 0 + }, /* 25xx160 2048 16 2 */ + { + 4, 2, 2, 0 + }, /* 25xx160B/D 2048 32 2 */ + { + 5, 2, 2, 0 + }, /* 25xx320 4096 32 2 */ + { + 6, 2, 2, 0 + }, /* 25xx640 8192 32 2 */ + { + 7, 3, 2, 0 + }, /* 25xx128 16384 64 2 */ + { + 8, 3, 2, 0 + }, /* 25xx256 32768 64 2 */ + { + 9, 4, 2, 0 + }, /* 25xx512 65536 128 2 */ + { + 10, 5, 3, 0 + }, /* 25xx1024 131072 256 3 */ + + /* Atmel devices */ + + { + 0, 0, 1, 0 + }, /* AT25010B 128 8 1 */ + { + 1, 0, 1, 0 + }, /* AT25020B 256 8 1 */ + { + 2, 0, 1, 1 + }, /* AT25040B 512 8 1+bit */ + + /* STM devices */ + + { + 11, 5, 3, 0 + }, /* M95M02 262144 256 3 */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: at25ee_lock + * + * Description: + * On SPI buses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the buses for a sequence of + * transfers. The bus should be locked before the chip is selected. + * + * This is a blocking call and will not return until we have exclusive + * access to the SPI bus. We will retain that exclusive access until the + * bus is unlocked. + * + * After locking the SPI bus, the we also need call the setfrequency, + * setbits, and setmode methods to make sure that the SPI is properly + * configured for the device. If the SPI bus is being shared, then it may + * have been left in an incompatible state. + * + * Input Parameters: + * dev - pointer to device structure + * Returned Value: + * none + * + ****************************************************************************/ + +static void at25ee_lock(FAR struct spi_dev_s *dev) +{ + SPI_LOCK(dev, true); + SPI_SETMODE(dev, CONFIG_AT25EE_SPIMODE); + SPI_SETBITS(dev, 8); + SPI_HWFEATURES(dev, 0); + SPI_SETFREQUENCY(dev, CONFIG_AT25EE_SPIFREQUENCY); +#ifdef CONFIG_SPI_DELAY_CONTROL + SPI_SETDELAY(dev, CONFIG_AT25EE_START_DELAY, CONFIG_AT25EE_STOP_DELAY, + CONFIG_AT25EE_CS_DELAY, CONFIG_AT25EE_IFDELAY); +#endif +} + +/**************************************************************************** + * Name: at25ee_unlock + * + * Description: + * Unlocks the SPI bus + * + * Input Parameters: + * dev - pointer to device structure + * Returned Value: + * none + * + ****************************************************************************/ + +static inline void at25ee_unlock(FAR struct spi_dev_s *dev) +{ + SPI_LOCK(dev, false); +} + +/**************************************************************************** + * Name: at25ee_sendcmd + * + * Description: + * Send command and address as one transaction to take advantage + * of possible faster DMA transfers. + * Sending byte per byte is MUCH slower. + * + * Input Parameters: + * spi - a reference to the spi device + * cmd - SPI command to send + * addrlen - length of the address, in bits + * addr - address to write to + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void at25ee_sendcmd(FAR struct spi_dev_s *spi, uint8_t cmd, + uint8_t addrlen, uint32_t addr) +{ + uint8_t buf[4]; + int cmdlen = 1; + + /* Store command */ + + buf[0] = cmd; + + /* Store address according to its length */ + + if (addrlen == 9) + { + buf[0] |= (((addr >> 8) & 1) << 3); + } + + if (addrlen > 16) + { + buf[cmdlen++] = (addr >> 16) & 0xff; + } + + if (addrlen > 9) + { + buf[cmdlen++] = (addr >> 8) & 0xff; + } + + buf[cmdlen++] = addr & 0xff; + + SPI_SNDBLOCK(spi, buf, cmdlen); +} + +/**************************************************************************** + * Name: at25ee_waitwritecomplete + * + * Description: + * loop until the write operation is done. + * + * Input Parameters: + * priv - a reference to the device structure + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void at25ee_waitwritecomplete(struct at25ee_dev_s *priv) +{ + uint8_t status; + + /* Loop as long as the memory is busy with a write cycle */ + + do + { + /* Select this FLASH part */ + + at25ee_lock(priv->spi); + SPI_SELECT(priv->spi, SPIDEV_EEPROM(0), true); + + /* Send "Read Status Register (RDSR)" command */ + + SPI_SEND(priv->spi, AT25EE_CMD_RDSR); + + /* Send a dummy byte to generate the clock needed to shift out the + * status + */ + + status = SPI_SEND(priv->spi, AT25EE_DUMMY); + + /* Deselect the FLASH */ + + SPI_SELECT(priv->spi, SPIDEV_EEPROM(0), false); + at25ee_unlock(priv->spi); + + /* Given that writing could take up to a few milliseconds, + * the following short delay in the "busy" case will allow + * other peripherals to access the SPI bus. + */ + + if ((status & AT25EE_SR_WIP) != 0) + { + nxsig_usleep(1000); + } + } + while ((status & AT25EE_SR_WIP) != 0); +} + +/**************************************************************************** + * Name: at25ee_writeenable + * + * Description: + * Enable or disable write operations. + * This is required before any write, since a lot of operations + * automatically disable the write latch. + * + * Input Parameters: + * priv - a reference to the device structure + * enable - enable (true) or disable(false) write operations + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void at25ee_writeenable(FAR struct at25ee_dev_s *priv, int enable) +{ + at25ee_lock(priv->spi); + SPI_SELECT(priv->spi, SPIDEV_EEPROM(0), true); + + SPI_SEND(priv->spi, enable ? AT25EE_CMD_WREN : AT25EE_CMD_WRDIS); + + SPI_SELECT(priv->spi, SPIDEV_EEPROM(0), false); + at25ee_unlock(priv->spi); +} + +/**************************************************************************** + * Name: at25ee_writepage + * + * Description: + * Write data to the EEPROM, NOT crossing page boundaries. + * + * Input Parameters: + * priv - a reference to the device structure + * devaddr - the address to start the write + * data - pointer to data buffer to write + * len - length of the data to write + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void at25ee_writepage(FAR struct at25ee_dev_s *priv, uint32_t devaddr, + FAR const uint8_t *data, size_t len) +{ + at25ee_lock(priv->spi); + SPI_SELECT(priv->spi, SPIDEV_EEPROM(0), true); + + at25ee_sendcmd(priv->spi, AT25EE_CMD_WRITE, priv->addrlen, devaddr); + SPI_SNDBLOCK(priv->spi, data, len); + + SPI_SELECT(priv->spi, SPIDEV_EEPROM(0), false); + at25ee_unlock(priv->spi); +} + +/**************************************************************************** + * Name: at25ee_eraseall + * + * Description: + * Erase all data in the device + * + * Input Parameters: + * priv - a reference to the device structure + * devaddr - the address to start the write + * data - pointer to data buffer to write + * len - length of the data to write + * + * Returned Value: + * none + * + ****************************************************************************/ + +static int at25ee_eraseall(FAR struct at25ee_dev_s *priv) +{ + uint8_t *buf; + int startblock = 0; + + DEBUGASSERT(priv); + + buf = kmm_malloc(priv->pgsize); + if (!buf) + { + ferr("ERROR: Failed to alloc memory for at25ee eraseall!\n"); + return -ENOMEM; + } + + memset(buf, 0xff, priv->pgsize); + + for (startblock = 0; startblock < priv->npages; startblock++) + { + uint16_t offset = startblock * priv->pgsize; + at25ee_write(&priv->mtd, offset, priv->pgsize, buf); + } + + kmm_free(buf); + return OK; +} + +/**************************************************************************** + * Name: at25ee_erase + * + * Description: + * Erase a number of blocks of data. + * + * Input Parameters: + * dev - a reference to the device structure + * startblock - start block of the erase + * nblocks - nblocks to erase + * + * Returned Value: + * Success (OK) or fail (negated error code) + ****************************************************************************/ + +static int at25ee_erase(FAR struct mtd_dev_s *dev, + off_t startblock, + size_t nblocks) +{ +#ifndef CONFIG_AT25EE_ENABLE_BLOCK_ERASE + return (int)nblocks; +#else + FAR struct at25ee_dev_s *priv = (FAR struct at25ee_dev_s *)dev; + uint8_t *buf; + size_t blocksleft; + + DEBUGASSERT(dev); + + if (priv->blocksize > priv->pgsize) + { + startblock *= (priv->blocksize / priv->pgsize); + nblocks *= (priv->blocksize / priv->pgsize); + } + + blocksleft = nblocks; + + if (startblock >= priv->npages) + { + return -E2BIG; + } + + buf = kmm_malloc(priv->pgsize); + if (!buf) + { + ferr("ERROR: Failed to alloc memory for at25ee erase!\n"); + return -ENOMEM; + } + + memset(buf, 0xff, priv->pgsize); + + if (startblock + nblocks > priv->npages) + { + nblocks = priv->npages - startblock; + } + + finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks); + + while (blocksleft-- > 0) + { + off_t offset = startblock * priv->pgsize; + + finfo("startblock: %08lx offset: %d\n", (long)startblock, (int)offset); + at25ee_write(dev, offset, priv->pgsize, buf); + startblock++; + } + + kmm_free(buf); + if (priv->blocksize > priv->pgsize) + { + return (int)(nblocks / (priv->blocksize / priv->pgsize)); + } + else + { + return (int)nblocks; + } +#endif +} + +/**************************************************************************** + * Name: at25ee_read + * + * Description: + * Read a number of bytes of data. + * + * Input Parameters: + * dev - a reference to the device structure + * offset - start of the memory to read + * nbytes - number of bytes to read + * buffer - pointer to variable to store the read data + * + * Returned Value: + * Size of the data read + ****************************************************************************/ + +static ssize_t at25ee_read(FAR struct mtd_dev_s *dev, off_t offset, + size_t nbytes, FAR uint8_t *buf) +{ + int ret; + FAR struct at25ee_dev_s *priv = (FAR struct at25ee_dev_s *)dev; + + DEBUGASSERT(buf); + DEBUGASSERT(dev); + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return ret; + } + + if ((offset + nbytes) > priv->size) + { + return 0; /* end-of-file */ + } + + at25ee_lock(priv->spi); + + SPI_SELECT(priv->spi, SPIDEV_EEPROM(0), true); + + /* STM32F4Disco: There is a 25 us delay here */ + + at25ee_sendcmd(priv->spi, AT25EE_CMD_READ, priv->addrlen, offset); + + SPI_RECVBLOCK(priv->spi, buf, nbytes); + + SPI_SELECT(priv->spi, SPIDEV_EEPROM(0), false); + + at25ee_unlock(priv->spi); + + nxmutex_unlock(&priv->lock); + return nbytes; +} + +/**************************************************************************** + * Name: at25ee_write + * + * Description: + * Write a number of bytes of data. + * + * Input Parameters: + * dev - a reference to the device structure + * offset - start of the memory to write + * nbytes - number of bytes to write + * buf - pointer to buffer of data to write + * + * Returned Value: + * Size of the data written + ****************************************************************************/ + +static ssize_t at25ee_write(FAR struct mtd_dev_s *dev, off_t offset, + size_t nbytes, FAR const uint8_t *buf) +{ + int ret = -EACCES; + FAR struct at25ee_dev_s *priv = (FAR struct at25ee_dev_s *)dev; + int pageoff; + size_t cnt; + + DEBUGASSERT(buf); + DEBUGASSERT(dev); + + if (priv->readonly) + { + return -EPERM; + } + + /* Forbid writes past the end of the device */ + + if (nbytes + offset >= priv->size) + { + return 0; + } + + ret = nxmutex_lock(&priv->lock); + if (ret < 0) + { + return 0; + } + + /* From this point no failure cannot be detected anymore. + * The user should verify the write by rereading memory. + */ + + ret = nbytes; /* save number of bytes written */ + + /* Writes can't happen in a row like the read does. + * The EEPROM is made of pages, and write sequences + * cannot cross page boundaries. So every time the last + * byte of a page is programmed, the SPI transaction is + * stopped, and the status register is read until the + * write operation has completed. + */ + + /* First, write some page-unaligned data */ + + pageoff = offset & (priv->pgsize - 1); + cnt = priv->pgsize - pageoff; + if (cnt > nbytes) + { + cnt = nbytes; + } + + if (pageoff > 0) + { + at25ee_writeenable(priv, true); + at25ee_writepage(priv, offset, buf, cnt); + at25ee_waitwritecomplete(priv); + nbytes -= cnt; + buf += cnt; + offset += cnt; + } + + /* Then, write remaining bytes at page-aligned addresses */ + + while (nbytes > 0) + { + cnt = nbytes; + if (cnt > priv->pgsize) + { + cnt = priv->pgsize; + } + + at25ee_writeenable(priv, true); + at25ee_writepage(priv, offset, buf, cnt); + at25ee_waitwritecomplete(priv); + nbytes -= cnt; + buf += cnt; + offset += cnt; + } + + nxmutex_unlock(&priv->lock); + return ret; +} + +/**************************************************************************** + * Name: at25ee_bread + * + * Description: + * Read a number of blocks of data. + * + * Input Parameters: + * dev - a reference to the device structure + * startblock - start block of the read + * nblocks - nblocks to read + * buf - pointer to variable to store the read data + * + * Returned Value: + * Number of blocks written + ****************************************************************************/ + +static ssize_t at25ee_bread(FAR struct mtd_dev_s *dev, + off_t startblock, + size_t nblocks, FAR uint8_t *buf) +{ + FAR struct at25ee_dev_s *priv = (FAR struct at25ee_dev_s *)dev; + off_t offset; + ssize_t nread; + size_t i; + + DEBUGASSERT(dev); + DEBUGASSERT(buf); + + if (priv->blocksize > priv->pgsize) + { + startblock *= (priv->blocksize / priv->pgsize); + nblocks *= (priv->blocksize / priv->pgsize); + } + + finfo("startblock: %08lx nblocks: %lu\n", + (unsigned long)startblock, (unsigned long)nblocks); + + if (startblock >= priv->npages) + { + return 0; + } + + if (startblock + nblocks > priv->npages) + { + nblocks = priv->npages - startblock; + } + + /* Convert the access from startblock and number of blocks to a byte + * offset and number of bytes. + */ + + offset = startblock * priv->pgsize; + + /* Then perform the byte-oriented read for each block separately */ + + for (i = 0; i < nblocks; i++) + { + nread = at25ee_read(dev, offset, priv->pgsize, buf); + if (nread < 0) + { + return nread; + } + + offset += priv->pgsize; + buf += priv->pgsize; + } + + if (priv->blocksize > priv->pgsize) + { + return nblocks / (priv->blocksize / priv->pgsize); + } + else + { + return nblocks; + } +} + +/**************************************************************************** + * Name: at25ee_bwrite + * + * Description: + * Write a number of blocks of data. + * + * Input Parameters: + * dev - a reference to the device structure + * startblock - starting block to write to + * nblocks - nblocks to write + * buf - pointer to data buffer to write + * + * Returned Value: + * Size of the data written + ****************************************************************************/ + +static ssize_t at25ee_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, + size_t nblocks, FAR const uint8_t *buf) +{ + FAR struct at25ee_dev_s *priv = (FAR struct at25ee_dev_s *)dev; + size_t blocksleft; + + DEBUGASSERT(dev); + DEBUGASSERT(buf); + + if (priv->blocksize > priv->pgsize) + { + startblock *= (priv->blocksize / priv->pgsize); + nblocks *= (priv->blocksize / priv->pgsize); + } + + blocksleft = nblocks; + + if (startblock >= priv->npages) + { + return 0; + } + + if (startblock + nblocks > priv->npages) + { + nblocks = priv->npages - startblock; + } + + finfo("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks); + + while (blocksleft-- > 0) + { + off_t offset = startblock * priv->pgsize; + + finfo("startblock: %08lx offset: %d\n", (long)startblock, (int)offset); + at25ee_write(dev, offset, priv->pgsize, buf); + startblock++; + buf += priv->pgsize; + } + + if (priv->blocksize > priv->pgsize) + { + return nblocks / (priv->blocksize / priv->pgsize); + } + else + { + return nblocks; + } +} + +/**************************************************************************** + * Name: at25ee_ioctl + * * Description: + * IOCTLS relating to the EEPROM mtd device + * + * Input Parameters: + * dev - a reference to the device structure + * cmd - ioctl command + * arg - ioctl argument + * + * Returned Value: + * Success (OK) or fail (negated error code) + ****************************************************************************/ + +static int at25ee_ioctl(FAR struct mtd_dev_s *dev, + int cmd, + unsigned long arg) +{ + FAR struct at25ee_dev_s *priv = (FAR struct at25ee_dev_s *)dev; + int ret = -EINVAL; /* Assume good command with bad parameters */ + + DEBUGASSERT(dev); + + finfo("cmd: %d\n", cmd); + + switch (cmd) + { + case MTDIOC_GEOMETRY: + { + FAR struct mtd_geometry_s *geo = (FAR struct mtd_geometry_s *) + ((uintptr_t)arg); + if (geo) + { + memset(geo, 0, sizeof(*geo)); + + /* Populate the geometry structure with information need to + * know the capacity and how to access the device. + * + * NOTE: + * that the device is treated as though it where just an array + * of fixed size blocks. + * That is most likely not true, but the client will expect the + * device logic to do whatever is necessary to make it appear + * so. + * + * blocksize: + * May be user defined. + * The block size for the at24XX devices may be larger than + * the page size in order to better support file systems. + * The read and write functions translate BLOCKS to pages + * for the small flash devices + * erasesize: + * It has to be at least as big as the blocksize, bigger + * serves no purpose. + * neraseblocks + * Note that the device size is in kilobits and must be + * scaled by 1024 / 8 + */ + + if (priv->blocksize > priv->pgsize) + { + geo->blocksize = priv->blocksize; + geo->erasesize = priv->blocksize; + geo->neraseblocks = priv->size / priv->blocksize; + } + else + { + geo->blocksize = priv->pgsize; + geo->erasesize = priv->pgsize; + geo->neraseblocks = priv->npages; + } + + ret = OK; + + finfo("blocksize: %" PRId32 " erasesize: %" PRId32 + " neraseblocks: %" PRId32 "\n", + geo->blocksize, geo->erasesize, geo->neraseblocks); + } + } + break; + + case BIOC_PARTINFO: + { + FAR struct partition_info_s *info = + (FAR struct partition_info_s *)arg; + if (info != NULL) + { + if (priv->blocksize > priv->pgsize) + { + info->numsectors = priv->size / priv->blocksize; + info->sectorsize = priv->blocksize; + } + else + { + info->numsectors = priv->npages; + info->sectorsize = priv->pgsize; + } + + info->startsector = 0; + info->parent[0] = '\0'; + ret = OK; + } + } + break; + + case MTDIOC_BULKERASE: + ret = at25ee_eraseall(priv); + break; + + default: + ret = -ENOTTY; /* Bad command */ + break; + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: at25ee_initialize + * + * Description: + * Create an initialized MTD device instance for an AT25 SPI EEPROM + * MTD devices are not registered in the file system, but are created + * as instances that can be bound to other functions + * (such as a block or character driver front end). + * + * Input Parameters: + * dev - a reference to the spi device structure + * devtype - device type, from include/nuttx/eeprom/spi_xx25xx.h + * readonly - sets block driver to be readonly + * + * Returned Value: + * Initialised device instance (success) or NULL (fail) + * + ****************************************************************************/ + +FAR struct mtd_dev_s *at25ee_initialize(FAR struct spi_dev_s *dev, + int devtype, int readonly) +{ + FAR struct at25ee_dev_s *priv; + + DEBUGASSERT(dev); + + /* Check device type early */ + + if ((devtype < 0) || + (devtype >= sizeof(g_at25ee_devices) / sizeof(g_at25ee_devices[0]))) + { + return NULL; + } + + priv = kmm_zalloc(sizeof(struct at25ee_dev_s)); + if (priv == NULL) + { + ferr("ERROR: Failed to allocate device structure\n"); + return NULL; + } + + /* Initialize the allocated structure */ + + nxmutex_init(&priv->lock); + + priv->spi = dev; + priv->size = 128 << g_at25ee_devices[devtype].bytes; + priv->pgsize = 8 << g_at25ee_devices[devtype].pagesize; + priv->addrlen = g_at25ee_devices[devtype].addrlen << 3; + priv->npages = priv->size / priv->pgsize; +#ifdef CONFIG_USE_NATIVE_AT25EE_BLOCK_SIZE + priv->blocksize = priv->pgsize; +#else + if ((CONFIG_MANUAL_AT25EE_BLOCK_SIZE % priv->pgsize) || + (CONFIG_MANUAL_AT25EE_BLOCK_SIZE > priv->size)) + { + ferr("ERROR: Configured block size is incorrect!\n"); + DEBUGASSERT(0); + priv->blocksize = priv->pgsize; + } + else + { + priv->blocksize = CONFIG_MANUAL_AT25EE_BLOCK_SIZE; + } + +#endif + if ((g_at25ee_devices[devtype].flags & 1)) + { + priv->addrlen = 9; + } + + priv->readonly = !!readonly; + + finfo("EEPROM device, %"PRIu32" bytes, " + "%u per page, addrlen %u, readonly %d\n", + priv->size, priv->pgsize, priv->addrlen, + priv->readonly); + + priv->mtd.erase = at25ee_erase; + priv->mtd.bread = at25ee_bread; + priv->mtd.bwrite = at25ee_bwrite; + priv->mtd.read = at25ee_read; + priv->mtd.write = at25ee_write; + priv->mtd.ioctl = at25ee_ioctl; + priv->mtd.name = "at25ee"; + + /* Return the implementation-specific state structure as the MTD device */ + + finfo("Return %p\n", priv); + return (FAR struct mtd_dev_s *)priv; +} + +#endif /* CONFIG_MTD_AT25EE */ diff --git a/drivers/mtd/filemtd.c b/drivers/mtd/filemtd.c index cdb562e1ffe10..5fd6d614cf0d0 100644 --- a/drivers/mtd/filemtd.c +++ b/drivers/mtd/filemtd.c @@ -119,6 +119,8 @@ static ssize_t file_bytewrite(FAR struct mtd_dev_s *dev, off_t offset, #endif static int filemtd_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg); +static int filemtd_isbad(FAR struct mtd_dev_s *dev, off_t block); +static int filemtd_markbad(FAR struct mtd_dev_s *dev, off_t block); #ifdef CONFIG_MTD_LOOP static ssize_t mtd_loop_read(FAR struct file *filep, FAR char *buffer, @@ -149,6 +151,28 @@ static const struct file_operations g_fops = * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: filemtd_isbad + ****************************************************************************/ + +static int filemtd_isbad(FAR struct mtd_dev_s *dev, off_t block) +{ + /* We always think it's all GOODBLOCK */ + + return 0; +} + +/**************************************************************************** + * Name: filemtd_markbad + ****************************************************************************/ + +static int filemtd_markbad(FAR struct mtd_dev_s *dev, off_t block) +{ + /* Provides a dummy interface */ + + return 0; +} + /**************************************************************************** * Name: filemtd_write ****************************************************************************/ @@ -279,19 +303,12 @@ static int filemtd_erase(FAR struct mtd_dev_s *dev, off_t startblock, nblocks = priv->nblocks - startblock; } - /* Convert the erase block to a logical block and the number of blocks - * in logical block numbers - */ - - startblock *= (priv->erasesize / priv->blocksize); - nblocks *= (priv->erasesize / priv->blocksize); - /* Get the offset corresponding to the first block and the size * corresponding to the number of blocks. */ - offset = startblock * priv->blocksize; - nbytes = nblocks * priv->blocksize; + offset = startblock * priv->erasesize; + nbytes = nblocks * priv->erasesize; /* Then erase the data in the file */ @@ -303,7 +320,7 @@ static int filemtd_erase(FAR struct mtd_dev_s *dev, off_t startblock, nbytes -= MIN(nbytes, sizeof(buffer)); } - return OK; + return nblocks; } /**************************************************************************** @@ -807,17 +824,19 @@ FAR struct mtd_dev_s *filemtd_initialize(FAR const char *path, size_t offset, * nullified by kmm_zalloc). */ - priv->mtd.erase = filemtd_erase; - priv->mtd.bread = filemtd_bread; - priv->mtd.bwrite = filemtd_bwrite; - priv->mtd.read = filemtd_byteread; + priv->mtd.erase = filemtd_erase; + priv->mtd.bread = filemtd_bread; + priv->mtd.bwrite = filemtd_bwrite; + priv->mtd.read = filemtd_byteread; #ifdef CONFIG_MTD_BYTE_WRITE - priv->mtd.write = file_bytewrite; + priv->mtd.write = file_bytewrite; #endif - priv->mtd.ioctl = filemtd_ioctl; - priv->mtd.name = "filemtd"; - priv->offset = offset; - priv->nblocks = nblocks; + priv->mtd.ioctl = filemtd_ioctl; + priv->mtd.isbad = filemtd_isbad; + priv->mtd.markbad = filemtd_markbad; + priv->mtd.name = "filemtd"; + priv->offset = offset; + priv->nblocks = nblocks; return &priv->mtd; } diff --git a/drivers/mtd/mtd_config_fs.c b/drivers/mtd/mtd_config_fs.c index aac530ae15ed4..f1f8079f5ffd9 100644 --- a/drivers/mtd/mtd_config_fs.c +++ b/drivers/mtd/mtd_config_fs.c @@ -81,6 +81,9 @@ #define NVS_SPECIAL_ATE_ID 0xffffffff +#define NVS_ALIGN_SIZE CONFIG_MTD_WRITE_ALIGN_SIZE +#define NVS_ALIGN_UP(x) (((x) + NVS_ALIGN_SIZE - 1) & ~(NVS_ALIGN_SIZE - 1)) + /**************************************************************************** * Private Types ****************************************************************************/ @@ -110,8 +113,15 @@ begin_packed_struct struct nvs_ate uint16_t key_len; /* Key string len */ uint8_t part; /* Part of a multipart data - future extension */ uint8_t crc8; /* Crc8 check of the ate entry */ - uint8_t expired; /* 0xFF-newest entry, others-old entry */ - uint8_t reserved[3]; /* For future extension */ +#if CONFIG_MTD_WRITE_ALIGN_SIZE <= 4 + /* stay compatible with situation which align byte be 1 */ + + uint8_t expired[NVS_ALIGN_SIZE]; + uint8_t reserved[4 - NVS_ALIGN_SIZE]; +#else + uint8_t padding[NVS_ALIGN_UP(12) - 12]; + uint8_t expired[NVS_ALIGN_SIZE]; +#endif } end_packed_struct; /**************************************************************************** @@ -577,6 +587,40 @@ static int nvs_close_ate_valid(FAR struct nvs_fs *fs, return 1; } +/**************************************************************************** + * Name: nvs_flash_write_multi_blk + * + * Description: + * Store multi align block in flash + * + * Returned Value: + * number of bytes at the end of addr which is left to write next time. + * zero indicates all bytes were written . On error returns -ERRNO code. + ****************************************************************************/ + +int nvs_flash_write_multi_blk(FAR struct nvs_fs *fs, const uint8_t *addr, + size_t size) +{ + size_t blk_cnt; + int left; + int rc; + + blk_cnt = size / NVS_ALIGN_SIZE; + left = size % NVS_ALIGN_SIZE; + + if (blk_cnt) + { + rc = nvs_flash_data_wrt(fs, addr, size - left); + if (rc) + { + ferr("Write multi data value failed, rc=%d\n", rc); + return rc; + } + } + + return left; +} + /**************************************************************************** * Name: nvs_flash_wrt_entry * @@ -591,6 +635,9 @@ static int nvs_flash_wrt_entry(FAR struct nvs_fs *fs, uint32_t id, { int rc; struct nvs_ate entry; + uint16_t left; + uint16_t copy_len = 0; + uint8_t buf[NVS_ALIGN_SIZE]; memset(&entry, fs->erasestate, sizeof(entry)); entry.id = id; @@ -600,22 +647,58 @@ static int nvs_flash_wrt_entry(FAR struct nvs_fs *fs, uint32_t id, nvs_ate_crc8_update(&entry); - /* Let's sew key and data into one, key comes first, then data */ + /* Let's save key and data into one, key comes first, then data */ - rc = nvs_flash_data_wrt(fs, key, key_size); - if (rc) + rc = nvs_flash_write_multi_blk(fs, key, key_size); + if (rc < 0) { - ferr("Write key failed, rc=%d\n", rc); return rc; } - rc = nvs_flash_data_wrt(fs, data, len); if (rc) { - ferr("Write value failed, rc=%d\n", rc); + /* Write align block which inlcude part key + part data */ + + left = rc; + memset(buf, fs->erasestate, NVS_ALIGN_SIZE); + + copy_len = (left + len) <= NVS_ALIGN_SIZE ? + len : (NVS_ALIGN_SIZE - left); + + memcpy(buf, key + key_size - left, left); + memcpy(buf + left, data, copy_len); + rc = nvs_flash_data_wrt(fs, buf, NVS_ALIGN_SIZE); + if (rc) + { + ferr("Write value failed, rc=%d\n", rc); + return rc; + } + } + + rc = nvs_flash_write_multi_blk(fs, data + copy_len, len - copy_len); + if (rc < 0) + { return rc; } + if (rc) + { + /* Add padding at the end of data */ + + left = rc; + memset(buf, fs->erasestate, NVS_ALIGN_SIZE); + memcpy(buf, data + len - left, left); + + rc = nvs_flash_data_wrt(fs, buf, NVS_ALIGN_SIZE); + if (rc) + { + ferr("Write value failed, rc=%d\n", rc); + return rc; + } + } + + /* Last, let's save entry to flash */ + rc = nvs_flash_ate_wrt(fs, &entry); if (rc) { @@ -666,10 +749,16 @@ static int nvs_recover_last_ate(FAR struct nvs_fs *fs, /* Found a valid ate, update data_end_addr and *addr */ data_end_addr &= ADDR_BLOCK_MASK; - data_end_addr += end_ate.offset + end_ate.key_len + end_ate.len; + data_end_addr += end_ate.offset + + NVS_ALIGN_UP(end_ate.key_len + end_ate.len); *addr = ate_end_addr; } + if (ate_end_addr < sizeof(struct nvs_ate)) + { + break; + } + ate_end_addr -= sizeof(struct nvs_ate); } @@ -829,10 +918,11 @@ static int nvs_add_gc_done_ate(FAR struct nvs_fs *fs) static int nvs_expire_ate(FAR struct nvs_fs *fs, uint32_t addr) { - uint8_t expired = 0; + uint8_t expired[NVS_ALIGN_SIZE]; + memset(expired, ~fs->erasestate, sizeof(expired)); return nvs_flash_wrt(fs, addr + offsetof(struct nvs_ate, expired), - &expired, sizeof(expired)); + expired, sizeof(expired)); } /**************************************************************************** @@ -906,7 +996,7 @@ static int nvs_gc(FAR struct nvs_fs *fs) return rc; } - if (gc_ate.expired != fs->erasestate) + if (gc_ate.expired[0] != fs->erasestate) { /* Deleted or old ate, ignore it */ @@ -932,7 +1022,7 @@ static int nvs_gc(FAR struct nvs_fs *fs) nvs_ate_crc8_update(&gc_ate); rc = nvs_flash_block_move(fs, data_addr, - gc_ate.key_len + gc_ate.len); + NVS_ALIGN_UP(gc_ate.key_len + gc_ate.len)); if (rc) { return rc; @@ -1117,8 +1207,8 @@ static int nvs_startup(FAR struct nvs_fs *fs) /* Complete write of ate was performed */ fs->data_wra = addr & ADDR_BLOCK_MASK; - fs->data_wra += last_ate.offset + last_ate.key_len + - last_ate.len; + fs->data_wra += last_ate.offset + + NVS_ALIGN_UP(last_ate.key_len + last_ate.len); finfo("recovered data_wra=0x%" PRIx32 "\n", fs->data_wra); } @@ -1277,7 +1367,7 @@ static int nvs_startup(FAR struct nvs_fs *fs) if (nvs_ate_valid(fs, &second_ate) && second_ate.id == last_ate.id - && second_ate.expired == fs->erasestate) + && second_ate.expired[0] == fs->erasestate) { finfo("same id at 0x%" PRIx32 ", key_len %" PRIu16 ", " "offset %" PRIu16 "\n", @@ -1393,7 +1483,7 @@ static ssize_t nvs_read_entry(FAR struct nvs_fs *fs, FAR const uint8_t *key, { /* It is old or deleted, return -ENOENT */ - if (wlk_ate.expired != fs->erasestate) + if (wlk_ate.expired[0] != fs->erasestate) { return -ENOENT; } @@ -1482,13 +1572,14 @@ static ssize_t nvs_write(FAR struct nvs_fs *fs, /* Data now contains input data and input key, input key first. */ - data_size = key_size + pdata->len; + data_size = NVS_ALIGN_UP(key_size + pdata->len); /* The maximum data size is block size - 3 ate * where: 1 ate for data, 1 ate for block close, 1 ate for gc done. */ - finfo("key_size=%zu, len=%zu\n", key_size, pdata->len); + finfo("key_size=%zu, len=%zu, data_size = %zu\n", key_size, + pdata->len, data_size); if ((data_size > (fs->geo.erasesize - 3 * sizeof(struct nvs_ate))) || ((pdata->len > 0) && (pdata->configdata == NULL))) @@ -1548,7 +1639,7 @@ static ssize_t nvs_write(FAR struct nvs_fs *fs, { /* If prev ate is expired, it is deleted. */ - if (wlk_ate.expired != fs->erasestate) + if (wlk_ate.expired[0] != fs->erasestate) { /* Skip delete entry as it is already the * last one. @@ -1572,7 +1663,7 @@ static ssize_t nvs_write(FAR struct nvs_fs *fs, } } else if (pdata->len == wlk_ate.len && - wlk_ate.expired == fs->erasestate) + wlk_ate.expired[0] == fs->erasestate) { /* Do not try to compare if lengths are not equal * or prev one is deleted. @@ -1619,7 +1710,7 @@ static ssize_t nvs_write(FAR struct nvs_fs *fs, /* Nvs is changed after gc, we will look for the old ate. */ - if (prev_found && wlk_ate.expired == fs->erasestate) + if (prev_found && wlk_ate.expired[0] == fs->erasestate) { finfo("prev entry exists, search for it\n"); @@ -1662,7 +1753,7 @@ static ssize_t nvs_write(FAR struct nvs_fs *fs, * already expired) */ - if (prev_found && wlk_ate.expired == fs->erasestate) + if (prev_found && wlk_ate.expired[0] == fs->erasestate) { rc = nvs_expire_ate(fs, hist_addr); finfo("expir prev entry, %" PRIx32 ", rc %d\n", @@ -1832,7 +1923,7 @@ static int nvs_next(FAR struct nvs_fs *fs, if (nvs_ate_valid(fs, &step_ate) && step_ate.id != NVS_SPECIAL_ATE_ID - && step_ate.expired == fs->erasestate) + && step_ate.expired[0] == fs->erasestate) { break; } diff --git a/drivers/mtd/mtd_nand.c b/drivers/mtd/mtd_nand.c index f4776d8a6f2cc..88175faceefb1 100644 --- a/drivers/mtd/mtd_nand.c +++ b/drivers/mtd/mtd_nand.c @@ -44,6 +44,7 @@ #include #include #include +#include #include #include diff --git a/drivers/mtd/mtd_nandram.c b/drivers/mtd/mtd_nandram.c new file mode 100644 index 0000000000000..cfaaef7366ed4 --- /dev/null +++ b/drivers/mtd/mtd_nandram.c @@ -0,0 +1,475 @@ +/**************************************************************************** + * drivers/mtd/mtd_nandram.c + * This file deals with the raw lower half of the device driver, and manages + * reading and writing to the actual NAND Flash device that has been emulated + * from RAM. + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_MTD_NAND_RAM_DEBUG + +#define NAND_RAM_DEBUG_1 1 +#define NAND_RAM_DEBUG_2 5 +#define NAND_RAM_DEBUG_3 10 + +#define NAND_RAM_STATUS_1 1 +#define NAND_RAM_STATUS_2 5 +#define NAND_RAM_STATUS_3 10 +#define NAND_RAM_STATUS_4 50 +#define NAND_RAM_STATUS_5 100 +#define NAND_RAM_STATUS_6 500 +#define NAND_RAM_STATUS_7 1000 +#define NAND_RAM_STATUS_8 5000 + +#if CONFIG_MTD_NAND_RAM_DEBUG_LEVEL == 1 +#define NAND_RAM_DEBUG_LEVEL NAND_RAM_DEBUG_1 +#elif CONFIG_MTD_NAND_RAM_DEBUG_LEVEL == 2 +#define NAND_RAM_DEBUG_LEVEL NAND_RAM_DEBUG_2 +#elif CONFIG_MTD_NAND_RAM_DEBUG_LEVEL == 3 +#define NAND_RAM_DEBUG_LEVEL NAND_RAM_DEBUG_3 +#endif /* CONFIG_MTD_NAND_RAM_DEBUG_LEVEL */ + +#if CONFIG_MTD_NAND_RAM_STATUS == 1 +#define NAND_RAM_STATUS_LEVEL NAND_RAM_STATUS_1 +#elif CONFIG_MTD_NAND_RAM_STATUS == 2 +#define NAND_RAM_STATUS_LEVEL NAND_RAM_STATUS_2 +#elif CONFIG_MTD_NAND_RAM_STATUS == 3 +#define NAND_RAM_STATUS_LEVEL NAND_RAM_STATUS_3 +#elif CONFIG_MTD_NAND_RAM_STATUS == 4 +#define NAND_RAM_STATUS_LEVEL NAND_RAM_STATUS_4 +#elif CONFIG_MTD_NAND_RAM_STATUS == 5 +#define NAND_RAM_STATUS_LEVEL NAND_RAM_STATUS_5 +#elif CONFIG_MTD_NAND_RAM_STATUS == 6 +#define NAND_RAM_STATUS_LEVEL NAND_RAM_STATUS_6 +#elif CONFIG_MTD_NAND_RAM_STATUS == 7 +#define NAND_RAM_STATUS_LEVEL NAND_RAM_STATUS_7 +#elif CONFIG_MTD_NAND_RAM_STATUS == 8 +#define NAND_RAM_STATUS_LEVEL NAND_RAM_STATUS_8 +#endif /* CONFIG_MTD_NAND_RAM_STATUS */ + +#define NAND_RAM_LOG(str, ...) \ + { \ + if (nand_ram_ins_i % NAND_RAM_DEBUG_LEVEL == 0) \ + { \ + syslog(LOG_DEBUG, "nand_ram: " str, __VA_ARGS__); \ + } \ + } \ + +#define NAND_RAM_STATUS_LOG(str, ...) \ + syslog(LOG_DEBUG, "nand_ram_status: " str, __VA_ARGS__); + +#else + +#define NAND_RAM_LOG +#define NAND_RAM_STATUS_LOG + +#endif /* CONFIG_MTD_NAND_RAM_DEBUG */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct nand_ram_data_s +{ + uint8_t page[NAND_RAM_PAGE_SIZE / 8]; +}; + +/* 512 B page spare scheme */ + +struct nand_ram_spare_s +{ + uint8_t ecc_0; /* 0 */ + uint8_t ecc_1; + uint8_t ecc_2; + uint8_t ecc_3; + uint8_t __res1; + uint8_t bad; /* 5 */ /* NAND_RAM_BLOCK_* */ + uint8_t ecc_4; + uint8_t ecc_5; + + /* Using reserved (8 bytes) */ + + uint16_t n_read; + uint16_t n_write; /* 10 */ + uint16_t n_erase; + uint8_t free; /* Erased page: NAND_RAM_PAGE_* */ + uint8_t __res2; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint64_t nand_ram_ins_i = 0; /* Instruction counter */ +static mutex_t nand_ram_dev_mut; +static struct nand_ram_data_s nand_ram_flash_data[NAND_RAM_N_PAGES]; +static struct nand_ram_spare_s nand_ram_flash_spare[NAND_RAM_N_PAGES]; + +/* Hard coded array for bad block indexes */ + +static int g_nand_ram_rand_bad_blk_indx[] = + { + 4, 14, 19, 21, 28, 30, 107, + 108, 164, 173, 179, 229, 268, + 362, 377, 382, 396, 410, 412, + 419, 428, 456, 500, 0 + }; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * External Functions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nand_ram_storage_status + * + * Description: + * Writes per-page status of virtual NAND Flash. + * + ****************************************************************************/ + +static void nand_ram_storage_status(void) +{ + uint32_t i; + uint16_t reads; + uint16_t writes; + uint16_t erases; + uint8_t bad; + + /* Wear */ + + for (i = 0; i < NAND_RAM_N_PAGES; i++) + { + reads = nand_ram_flash_spare[i].n_read; + writes = nand_ram_flash_spare[i].n_write; + erases = nand_ram_flash_spare[i].n_erase; + bad = (nand_ram_flash_spare[i].bad != NAND_RAM_BLOCK_GOOD); + + NAND_RAM_STATUS_LOG( + "Block %3d, Page %6d, Bad: %1d |" + " Reads: %6d, Writes: %6d, Erases: %6d\n", + i >> NAND_RAM_LOG_PAGES_PER_BLOCK, i, bad, + reads, writes, erases); + } + + return; +} + +static inline void nand_ram_status(void) +{ + if (nand_ram_ins_i % NAND_RAM_STATUS_LEVEL == 0) + { + nand_ram_storage_status(); + } +} + +/**************************************************************************** + * Name: nand_ram_storage_init + * + * Description: + * Initializes the actual NAND Device that is emulated from RAM. + * + ****************************************************************************/ + +static void nand_ram_storage_init(void) +{ + int i; + + memset(nand_ram_flash_data, 0xff, + sizeof(struct nand_ram_data_s) * NAND_RAM_N_PAGES); + memset(nand_ram_flash_spare, 0, + sizeof(struct nand_ram_spare_s) * NAND_RAM_N_PAGES); + + for (i = 0; i < NAND_RAM_N_PAGES; i++) + { + nand_ram_flash_spare[i].free = NAND_RAM_PAGE_FREE; + nand_ram_flash_spare[i].bad = NAND_RAM_BLOCK_GOOD; + } + + /* Bad blocks */ + + for (i = 0; + g_nand_ram_rand_bad_blk_indx[i] != 0 && + g_nand_ram_rand_bad_blk_indx[i] < NAND_RAM_N_BLOCKS; + i++) + { + int j; + + for (j = 0; j < NAND_RAM_PAGES_PER_BLOCK; j++) + { + int page = (g_nand_ram_rand_bad_blk_indx[i] << + NAND_RAM_LOG_PAGES_PER_BLOCK)+j; + + /* Set bad block marker to Anything but NAND_RAM_BLOCK_GOOD */ + + nand_ram_flash_spare[page].bad = 0; + } + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nand_ram_eraseblock + * + * Description: + * Erases a block on the device. + * + * Input Parameters: + * raw: NAND MTD Device raw structure. + * block: Block number (0 indexing) to erase + * + * Returned Value: + * 0: Successful + * < 0: Error + * + ****************************************************************************/ + +int nand_ram_eraseblock(FAR struct nand_raw_s *raw, off_t block) +{ + int i; + uint32_t start_page; + uint32_t end_page; + + start_page = block << NAND_RAM_LOG_PAGES_PER_BLOCK; + end_page = start_page + NAND_RAM_PAGES_PER_BLOCK; + + nxmutex_lock(&nand_ram_dev_mut); + nand_ram_ins_i++; + + NAND_RAM_LOG( + "[LOWER %lu | %s] Block %d, Start Page: %d, Last Page: %d", + nand_ram_ins_i, "eraseblock", block, start_page, end_page - 1 + ); + nand_ram_status(); + + /* [start_page, end_page) is cleared (all bits are set) */ + + memset(nand_ram_flash_data + start_page, 0xff, + (end_page - start_page) * sizeof(struct nand_ram_data_s)); + for (i = start_page; i < end_page; i++) + { + nand_ram_flash_spare[i].n_erase++; + nand_ram_flash_spare[i].free = 1; + } + + NAND_RAM_LOG("[LOWER %lu | %s] Done\n", nand_ram_ins_i, "eraseblock"); + + nxmutex_unlock(&nand_ram_dev_mut); + + return OK; +} + +/**************************************************************************** + * Name: nand_ram_rawread + * + * Description: + * Reads a page from the device. + * + * Input Parameters: + * raw: NAND MTD Device raw structure. + * block: Block number (0 indexing) to erase + * page: Page number (0 indexing) in (relative to) that block + * data: Preallocated memory where the data will be copied to + * spare: Preallocated memory where the spare data will be copied to + * + * Returned Value: + * 0: Successful + * + ****************************************************************************/ + +int nand_ram_rawread(FAR struct nand_raw_s *raw, off_t block, + unsigned int page, FAR void *data, FAR void *spare) +{ + int ret; + uint32_t read_page; + struct nand_ram_data_s *read_page_data; + struct nand_ram_spare_s *read_page_spare; + + read_page = (block << NAND_RAM_LOG_PAGES_PER_BLOCK) + page; + read_page_data = nand_ram_flash_data + read_page; + read_page_spare = nand_ram_flash_spare + read_page; + + ret = OK; + + nxmutex_lock(&nand_ram_dev_mut); + nand_ram_ins_i++; + + NAND_RAM_LOG("[LOWER %lu | %s] Page %d\n", + nand_ram_ins_i, "rawread", read_page); + nand_ram_status(); + + if (nand_ram_flash_spare[read_page].bad != NAND_RAM_BLOCK_GOOD) + { + ret = -EFAULT; + NAND_RAM_LOG("[LOWER %lu | %s] Failed: %s\n", + nand_ram_ins_i, "rawread", EFAULT_STR); + goto errout; + } + + nand_ram_flash_spare[read_page].n_read++; + + if (data != NULL) + { + memcpy(data, (const void *)read_page_data, NAND_RAM_PAGE_SIZE); + } + + if (spare != NULL) + { + memcpy(spare, (const void *)read_page_spare, NAND_RAM_PAGE_SIZE); + } + + NAND_RAM_LOG("[LOWER %lu | %s] Done\n", nand_ram_ins_i, "rawread"); + +errout: + nxmutex_unlock(&nand_ram_dev_mut); + + return ret; +} + +/**************************************************************************** + * Name: nand_ram_rawread + * + * Description: + * Writes a page to the device. + * + * Input Parameters: + * raw: NAND MTD Device raw structure. + * block: Block number (0 indexing) to erase + * page: Page number (0 indexing) in (relative to) that block + * data: Preallocated memory where the data will be copied to + * spare: Preallocated memory where the spare data will be copied to + * + * Returned Value: + * 0: Successful + * -EACCESS: The page's block needs to be erased first before writing to it + * + ****************************************************************************/ + +int nand_ram_rawwrite(FAR struct nand_raw_s *raw, off_t block, + unsigned int page, FAR const void *data, + FAR const void *spare) +{ + int ret; + uint32_t write_page; + struct nand_ram_data_s *write_page_data; + struct nand_ram_spare_s *write_page_spare; + + write_page = (block << NAND_RAM_LOG_PAGES_PER_BLOCK) + page; + write_page_data = nand_ram_flash_data + write_page; + write_page_spare = nand_ram_flash_spare + write_page; + + ret = OK; + + nxmutex_lock(&nand_ram_dev_mut); + nand_ram_ins_i++; + + NAND_RAM_LOG("[LOWER %lu | %s] Page %d\n", + nand_ram_ins_i, "rawwrite", write_page); + nand_ram_status(); + + if (nand_ram_flash_spare[write_page].free != NAND_RAM_PAGE_FREE) + { + ret = -EACCES; + NAND_RAM_LOG("[LOWER %lu | %s] Failed: %s\n", + nand_ram_ins_i, "rawwrite", EACCES_STR); + goto errout; + } + + nand_ram_flash_spare[write_page].n_write++; + + if (data != NULL) + { + memcpy((void *)write_page_data, data, NAND_RAM_PAGE_SIZE); + } + + if (spare != NULL) + { + memcpy((void *)write_page_spare, data, NAND_RAM_PAGE_SIZE); + } + + NAND_RAM_LOG("[LOWER %lu | %s] Done\n", nand_ram_ins_i, "rawwrite"); + +errout: + nxmutex_unlock(&nand_ram_dev_mut); + + return ret; +} + +/**************************************************************************** + * Name: nand_ram_init + * + * Description: + * Driver init. + * + * Input Parameters: + * raw: NAND MTD Device raw structure. + * + * Returned Value: + * A non-NULL MTD driver instance is returned on success. NULL is + * returned on any failure. + * + ****************************************************************************/ + +FAR struct mtd_dev_s *nand_ram_initialize(struct nand_raw_s *raw) +{ + NAND_RAM_LOG("[LOWER | %s]\n", "initialize"); + + nand_ram_storage_init(); + nxmutex_init(&nand_ram_dev_mut); + + raw->model.devid = 123; + raw->model.pagesize = NAND_RAM_PAGE_SIZE; + raw->model.sparesize = NAND_RAM_SPARE_SIZE; + raw->model.devsize = NAND_RAM_SIZE / (1024 * 1024); + raw->model.blocksize = NAND_RAM_BLOCK_SIZE / 1024; + raw->model.scheme = &g_nand_sparescheme512; + + raw->eraseblock = nand_ram_eraseblock; + raw->rawread = nand_ram_rawread; + raw->rawwrite = nand_ram_rawwrite; + + return nand_raw_initialize(raw); +} diff --git a/drivers/mtd/mtd_nandwrapper.c b/drivers/mtd/mtd_nandwrapper.c new file mode 100644 index 0000000000000..83e6bbc9862d9 --- /dev/null +++ b/drivers/mtd/mtd_nandwrapper.c @@ -0,0 +1,418 @@ +/**************************************************************************** + * drivers/mtd/mtd_nandwrapper.c + * This deals with the wrapper over the upper half of the driver, to enable + * logging for debugging, and essentially passes the parameters right to the + * actual upper half of the NAND Flash device driver without changing them. + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NAND_WRAPPER_DEBUG_1 1 +#define NAND_WRAPPER_DEBUG_2 5 +#define NAND_WRAPPER_DEBUG_3 10 + +#if CONFIG_MTD_NAND_WRAPPER_DEBUG_LEVEL == 1 +#define NAND_WRAPPER_DEBUG_LEVEL NAND_WRAPPER_DEBUG_1 +#elif CONFIG_MTD_NAND_WRAPPER_DEBUG_LEVEL == 2 +#define NAND_WRAPPER_DEBUG_LEVEL NAND_WRAPPER_DEBUG_2 +#elif CONFIG_MTD_NAND_WRAPPER_DEBUG_LEVEL == 3 +#define NAND_WRAPPER_DEBUG_LEVEL NAND_WRAPPER_DEBUG_3 +#endif /* CONFIG_MTD_NAND_WRAPPER_DEBUG_LEVEL */ + +#define NAND_WRAPPER_LOG(str, ...) \ + { \ + if(nand_wrapper_ins_i % NAND_WRAPPER_DEBUG_LEVEL == 0) \ + { \ + syslog(LOG_DEBUG, "nand_wrapper: " str, __VA_ARGS__); \ + } \ + } + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint64_t nand_wrapper_ins_i = 0; /* Instruction counter */ +static mutex_t nand_wrapper_dev_mut; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * External Functions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nand_wrapper_erase + * + * Description: + * Wrapper for NAND MTD erase method. + * + * Input Parameters: + * dev: NAND MTD Device (with an actual type of `nand_wrapper_dev_s` + * startblock: Block number (0-indexing) to start erasing + * nblocks: Number of blocks to erase + * + * Returned Value: + * 0: Successful + * < 0: Error + * + * Assumptions/Limitations: + * This assumes `dev` is specifically of type `struct nand_wrapper_dev_s *` + * + ****************************************************************************/ + +int nand_wrapper_erase(FAR struct mtd_dev_s *dev, off_t startblock, + size_t nblocks) +{ + int ret; + FAR struct nand_wrapper_dev_s *nand_dev; + + nand_dev = (struct nand_wrapper_dev_s *)dev; + + nxmutex_lock(&nand_wrapper_dev_mut); + nand_wrapper_ins_i++; + NAND_WRAPPER_LOG("[UPPER %lu | %s] Startblock: %d, N Blocks: %ld\n", + nand_wrapper_ins_i, "erase", startblock, nblocks); + DEBUGASSERT(nand_dev && nand_dev->under.mtd.erase); + + ret = nand_dev->under.mtd.erase(dev, startblock, nblocks); + + if (ret >= 0) + { + NAND_WRAPPER_LOG("[UPPER %lu | %s] Done\n", + nand_wrapper_ins_i, "erase"); + } + else + { + NAND_WRAPPER_LOG("[UPPER %lu | %s] Failed: %d!\n", + nand_wrapper_ins_i, "erase", ret); + } + + nxmutex_unlock(&nand_wrapper_dev_mut); + + return ret; +} + +/**************************************************************************** + * Name: nand_wrapper_bread + * + * Description: + * Wrapper for NAND MTD bread method. + * + * Input Parameters: + * dev: MTD Device + * startpage: Page number (0-indexing) to start reading + * npages: Number of pages to read. + * buffer: Preallocated memory where the data will be copied to + * + * Returned Value: + * 0: Successful + * < 0: Error + * + * Assumptions/Limitations: + * This assumes `dev` is specifically of type `struct nand_wrapper_dev_s *` + * + ****************************************************************************/ + +ssize_t nand_wrapper_bread(FAR struct mtd_dev_s *dev, off_t startpage, + size_t npages, FAR uint8_t *buffer) +{ + int ret; + FAR struct nand_wrapper_dev_s *nand_dev; + + nand_dev = (struct nand_wrapper_dev_s *)dev; + + nxmutex_lock(&nand_wrapper_dev_mut); + nand_wrapper_ins_i++; + NAND_WRAPPER_LOG("[UPPER %lu | %s] " + "Startblock: %d, N Pages: %ld, Buffer: %p\n", + nand_wrapper_ins_i, "bread", startpage, npages, buffer); + DEBUGASSERT(nand_dev && nand_dev->under.mtd.bread); + + ret = nand_dev->under.mtd.bread(dev, startpage, npages, buffer); + + if (ret >= 0) + { + NAND_WRAPPER_LOG("[UPPER %lu | %s] Done\n", + nand_wrapper_ins_i, "bread"); + } + else + { + NAND_WRAPPER_LOG("[UPPER %lu | %s] Failed: %d!\n", + nand_wrapper_ins_i, "bread", ret); + } + + nxmutex_unlock(&nand_wrapper_dev_mut); + + return ret; +} + +/**************************************************************************** + * Name: nand_wrapper_bwrite + * + * Description: + * Wrapper for NAND MTD bwrite method. + * + * Input Parameters: + * dev: MTD Device + * startpage: Page number (0-indexing) to start reading + * npages: Number of pages to read. + * buffer: Data which will be written to the device + * + * Returned Value: + * 0: Successful + * < 0: Error + * + * Assumptions/Limitations: + * This assumes the length of `buffer` would be the same as the size of + * `npages * block_size`. This also assumes `dev` is specifically of + * type `struct nand_wrapper_dev_s *` + * + ****************************************************************************/ + +ssize_t nand_wrapper_bwrite(FAR struct mtd_dev_s *dev, off_t startpage, + size_t npages, FAR const uint8_t *buffer) +{ + int ret; + FAR struct nand_wrapper_dev_s *nand_dev; + + nand_dev = (struct nand_wrapper_dev_s *)dev; + + nxmutex_lock(&nand_wrapper_dev_mut); + nand_wrapper_ins_i++; + NAND_WRAPPER_LOG("[UPPER %lu | %s] " + "Startblock: %d, N Pages: %ld, Buffer: %p \n", + nand_wrapper_ins_i, "bwrite", startpage, npages, buffer); + DEBUGASSERT(nand_dev && nand_dev->under.mtd.bwrite); + + ret = nand_dev->under.mtd.bwrite(dev, startpage, npages, buffer); + + if (ret >= 0) + { + NAND_WRAPPER_LOG("[UPPER %lu | %s] Done\n", + nand_wrapper_ins_i, "bwrite"); + } + else + { + NAND_WRAPPER_LOG("[UPPER %lu | %s] Failed: %d!\n", + nand_wrapper_ins_i, "bwrite", ret); + } + + nxmutex_unlock(&nand_wrapper_dev_mut); + + return ret; +} + +/**************************************************************************** + * Name: nand_wrapper_ioctl + * + * Description: + * Wrapper for NAND MTD ioctl method. + * + * Input Parameters: + * dev: MTD Device + * cmd: Command for IOCTL + * arg: Any argument required by command + * + * Returned Value: + * 0: Successful + * < 0: Error + * + * Assumptions/Limitations: + * This assumes `dev` is specifically of type `struct nand_wrapper_dev_s *` + * + ****************************************************************************/ + +int nand_wrapper_ioctl(FAR struct mtd_dev_s *dev, int cmd, + unsigned long arg) +{ + int ret; + FAR struct nand_wrapper_dev_s *nand_dev; + + nand_dev = (struct nand_wrapper_dev_s *)dev; + + nxmutex_lock(&nand_wrapper_dev_mut); + nand_wrapper_ins_i++; + NAND_WRAPPER_LOG("[UPPER %lu | %s] Command: %d, Arg : %ld\n", + nand_wrapper_ins_i, "ioctl", cmd, arg); + DEBUGASSERT(nand_dev && nand_dev->under.mtd.ioctl); + + ret = nand_dev->under.mtd.ioctl(dev, cmd, arg); + + if (ret >= 0) + { + NAND_WRAPPER_LOG("[UPPER %lu | %s] Done\n", + nand_wrapper_ins_i, "ioctl"); + } + else + { + NAND_WRAPPER_LOG("[UPPER %lu | %s] Failed: %d!\n", + nand_wrapper_ins_i, "ioctl", ret); + } + + nxmutex_unlock(&nand_wrapper_dev_mut); + + return ret; +} + +/**************************************************************************** + * Name: nand_wrapper_isbad + * + * Description: + * Wrapper for NAND MTD isbad method. + * + * Input Parameters: + * dev: MTD Device + * block: Block number (0-indexing) to check if it is bad + * + * Returned Value: + * 0: Successful + * < 0: Error + * + * Assumptions/Limitations: + * This assumes `dev` is specifically of type `struct nand_wrapper_dev_s *` + * + ****************************************************************************/ + +int nand_wrapper_isbad(FAR struct mtd_dev_s *dev, off_t block) +{ + int ret; + FAR struct nand_wrapper_dev_s *nand_dev; + + nand_dev = (struct nand_wrapper_dev_s *)dev; + + nxmutex_lock(&nand_wrapper_dev_mut); + nand_wrapper_ins_i++; + NAND_WRAPPER_LOG("[UPPER %lu | %s] Blocks: %d\n", + nand_wrapper_ins_i, "isbad", block); + DEBUGASSERT(nand_dev && nand_dev->under.mtd.isbad); + + ret = nand_dev->under.mtd.isbad(dev, block); + + if (ret >= 0) + { + NAND_WRAPPER_LOG("[UPPER %lu | %s] Done\n", + nand_wrapper_ins_i, "isbad"); + } + else + { + NAND_WRAPPER_LOG("[UPPER %lu | %s] Failed: %d!\n", + nand_wrapper_ins_i, "isbad", ret); + } + + nxmutex_unlock(&nand_wrapper_dev_mut); + + return ret; +} + +/**************************************************************************** + * Name: nand_wrapper_markbad + * + * Description: + * Wrapper for NAND MTD markbad method. + * + * Input Parameters: + * dev: MTD Device + * block: Block number (0-indexing) to mark it as bad + * + * Returned Value: + * 0: Successful + * < 0: Error + * + * Assumptions/Limitations: + * This assumes `dev` is specifically of type `struct nand_wrapper_dev_s *` + * + ****************************************************************************/ + +int nand_wrapper_markbad(FAR struct mtd_dev_s *dev, off_t block) +{ + int ret; + FAR struct nand_wrapper_dev_s *nand_dev; + + nand_dev = (struct nand_wrapper_dev_s *)dev; + + nxmutex_lock(&nand_wrapper_dev_mut); + nand_wrapper_ins_i++; + NAND_WRAPPER_LOG("[UPPER %lu | %s] Blocks: %d\n", + nand_wrapper_ins_i, "markbad", block); + DEBUGASSERT(nand_dev && nand_dev->under.mtd.markbad); + + ret = nand_dev->under.mtd.markbad(dev, block); + + if (ret >= 0) + { + NAND_WRAPPER_LOG("[UPPER %lu | %s] Done\n", + nand_wrapper_ins_i, "markbad"); + } + else + { + NAND_WRAPPER_LOG("[UPPER %lu | %s] Failed: %d!\n", + nand_wrapper_ins_i, "markbad", ret); + } + + nxmutex_unlock(&nand_wrapper_dev_mut); + + return ret; +} + +/**************************************************************************** + * Name: nand_wrapper_initialize + * + * Description: + * Initializes wrapper. + * + * Returned Value: + * 0: Successful + * < 0: Error + * + ****************************************************************************/ + +void nand_wrapper_initialize(void) +{ + nxmutex_init(&nand_wrapper_dev_mut); +} diff --git a/drivers/mtd/rpmsgmtd.c b/drivers/mtd/rpmsgmtd.c index a3889da490a20..541f1aa2bd4b1 100644 --- a/drivers/mtd/rpmsgmtd.c +++ b/drivers/mtd/rpmsgmtd.c @@ -74,7 +74,8 @@ struct rpmsgmtd_cookie_s static int rpmsgmtd_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks); -static int rpmsgmtd_get_geometry(FAR struct rpmsgmtd_s *dev); +static int rpmsgmtd_get_geometry(FAR struct rpmsgmtd_s *dev, + FAR struct mtd_geometry_s *geometry); static ssize_t rpmsgmtd_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks, FAR uint8_t *buffer); static ssize_t rpmsgmtd_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, @@ -109,6 +110,9 @@ static int rpmsgmtd_bread_handler(FAR struct rpmsg_endpoint *ept, static int rpmsgmtd_read_handler(FAR struct rpmsg_endpoint *ept, FAR void *data, size_t len, uint32_t src, FAR void *priv); +static int rpmsgmtd_geometry_handler(FAR struct rpmsg_endpoint *ept, + FAR void *data, size_t len, + uint32_t src, FAR void *priv); static int rpmsgmtd_ioctl_handler(FAR struct rpmsg_endpoint *ept, FAR void *data, size_t len, uint32_t src, FAR void *priv); @@ -132,12 +136,13 @@ static void rpmsgmtd_ns_bound(struct rpmsg_endpoint *ept); static const rpmsg_ept_cb g_rpmsgmtd_handler[] = { - [RPMSGMTD_ERASE] = rpmsgmtd_default_handler, - [RPMSGMTD_BREAD] = rpmsgmtd_bread_handler, - [RPMSGMTD_BWRITE] = rpmsgmtd_default_handler, - [RPMSGMTD_READ] = rpmsgmtd_read_handler, - [RPMSGMTD_WRITE] = rpmsgmtd_default_handler, - [RPMSGMTD_IOCTL] = rpmsgmtd_ioctl_handler, + [RPMSGMTD_ERASE] = rpmsgmtd_default_handler, + [RPMSGMTD_BREAD] = rpmsgmtd_bread_handler, + [RPMSGMTD_BWRITE] = rpmsgmtd_default_handler, + [RPMSGMTD_READ] = rpmsgmtd_read_handler, + [RPMSGMTD_WRITE] = rpmsgmtd_default_handler, + [RPMSGMTD_GEOMETRY] = rpmsgmtd_geometry_handler, + [RPMSGMTD_IOCTL] = rpmsgmtd_ioctl_handler, }; /**************************************************************************** @@ -191,25 +196,53 @@ static int rpmsgmtd_erase(FAR struct mtd_dev_s *dev, off_t startblock, * ****************************************************************************/ -static int rpmsgmtd_get_geometry(FAR struct rpmsgmtd_s *dev) +static int rpmsgmtd_get_geometry(FAR struct rpmsgmtd_s *dev, + FAR struct mtd_geometry_s *geometry) { + FAR struct rpmsgmtd_s *priv = dev; + struct rpmsgmtd_geometry_s msg; int ret; - ret = nxmutex_lock(&dev->geolock); + /* Sanity checks */ + + DEBUGASSERT(priv != NULL); + + ret = nxmutex_lock(&priv->geolock); if (ret < 0) { return ret; } - if (dev->geo.blocksize == 0) + /* Return the perviously got geometry */ + + if (priv->geo.blocksize != 0) { - /* Get the server mtd device geometry */ + if (geometry != NULL) + { + memcpy(geometry, &priv->geo, sizeof(*geometry)); + } - ret = rpmsgmtd_ioctl(&dev->mtd, MTDIOC_GEOMETRY, - (unsigned long)&dev->geo); + goto out; } - nxmutex_unlock(&dev->geolock); + ret = rpmsgmtd_send_recv(priv, RPMSGMTD_GEOMETRY, true, &msg.header, + sizeof(msg), NULL); + + if (ret >= 0) + { + priv->geo.blocksize = msg.blocksize; + priv->geo.erasesize = msg.erasesize; + priv->geo.neraseblocks = msg.neraseblocks; + strlcpy(priv->geo.model, msg.model, sizeof(priv->geo.model)); + + if (geometry != NULL) + { + memcpy(geometry, &priv->geo, sizeof(*geometry)); + } + } + +out: + nxmutex_unlock(&priv->geolock); return ret; } @@ -250,7 +283,7 @@ static ssize_t rpmsgmtd_bread(FAR struct mtd_dev_s *dev, off_t startblock, /* Get the server mtd geometry */ - ret = rpmsgmtd_get_geometry(priv); + ret = rpmsgmtd_get_geometry(priv, NULL); if (ret < 0) { ferr("Get geometry failed, ret=%d\n", ret); @@ -314,7 +347,7 @@ static ssize_t rpmsgmtd_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, /* Get the server mtd geometry */ - ret = rpmsgmtd_get_geometry(priv); + ret = rpmsgmtd_get_geometry(priv, NULL); if (ret < 0) { ferr("Get geometry failed, ret=%d\n", ret); @@ -552,8 +585,6 @@ static ssize_t rpmsgmtd_ioctl_arglen(int cmd) { switch (cmd) { - case MTDIOC_GEOMETRY: - return sizeof(struct mtd_geometry_s); case MTDIOC_PROTECT: case MTDIOC_UNPROTECT: return sizeof(struct mtd_protect_s); @@ -587,6 +618,11 @@ static int rpmsgmtd_ioctl(FAR struct mtd_dev_s *dev, int cmd, ssize_t arglen; size_t msglen; + if (cmd == MTDIOC_GEOMETRY) + { + return rpmsgmtd_get_geometry(priv, (FAR struct mtd_geometry_s *)arg); + } + /* Sanity checks */ DEBUGASSERT(priv != NULL); @@ -854,6 +890,42 @@ static int rpmsgmtd_read_handler(FAR struct rpmsg_endpoint *ept, return 0; } +/**************************************************************************** + * Name: rpmsgmtd_geometry_handler + * + * Description: + * Rpmsg-mtd geometry response handler, this function will be called to + * process the return message of rpmsgmtd_get_geometry(). + * + * Parameters: + * ept - The rpmsg endpoint + * data - The return message + * len - The return message length + * src - unknow + * priv - unknow + * + * Returned Values: + * Always OK + * + ****************************************************************************/ + +static int rpmsgmtd_geometry_handler(FAR struct rpmsg_endpoint *ept, + FAR void *data, size_t len, + uint32_t src, FAR void *priv) +{ + FAR struct rpmsgmtd_header_s *header = data; + FAR struct rpmsgmtd_cookie_s *cookie = + (FAR struct rpmsgmtd_cookie_s *)(uintptr_t)header->cookie; + + if (cookie->result >= 0) + { + memcpy(cookie->data, data, len); + } + + rpmsg_post(ept, &cookie->sem); + return 0; +} + /**************************************************************************** * Name: rpmsgmtd_ioctl_handler * diff --git a/drivers/mtd/rpmsgmtd.h b/drivers/mtd/rpmsgmtd.h index 39d01b068f073..5a80375351053 100644 --- a/drivers/mtd/rpmsgmtd.h +++ b/drivers/mtd/rpmsgmtd.h @@ -35,13 +35,15 @@ #define RPMSGMTD_NAME_PREFIX "rpmsgmtd-" #define RPMSGMTD_NAME_PREFIX_LEN 9 +#define RPMSGMTD_NAME_MAX 32 #define RPMSGMTD_ERASE 1 #define RPMSGMTD_BREAD 2 #define RPMSGMTD_BWRITE 3 #define RPMSGMTD_READ 4 #define RPMSGMTD_WRITE 5 -#define RPMSGMTD_IOCTL 6 +#define RPMSGMTD_GEOMETRY 6 +#define RPMSGMTD_IOCTL 7 /**************************************************************************** * Public Types @@ -82,6 +84,15 @@ begin_packed_struct struct rpmsgmtd_read_s #define rpmsgmtd_write_s rpmsgmtd_read_s +begin_packed_struct struct rpmsgmtd_geometry_s +{ + struct rpmsgmtd_header_s header; + uint32_t blocksize; + uint32_t erasesize; + uint32_t neraseblocks; + char model[RPMSGMTD_NAME_MAX + 1]; +} end_packed_struct; + begin_packed_struct struct rpmsgmtd_ioctl_s { struct rpmsgmtd_header_s header; diff --git a/drivers/mtd/rpmsgmtd_server.c b/drivers/mtd/rpmsgmtd_server.c index 7a9654d730d48..c0b5218a749bc 100644 --- a/drivers/mtd/rpmsgmtd_server.c +++ b/drivers/mtd/rpmsgmtd_server.c @@ -70,6 +70,9 @@ static int rpmsgmtd_read_handler(FAR struct rpmsg_endpoint *ept, static int rpmsgmtd_write_handler(FAR struct rpmsg_endpoint *ept, FAR void *data, size_t len, uint32_t src, FAR void *priv); +static int rpmsgmtd_geometry_handler(FAR struct rpmsg_endpoint *ept, + FAR void *data, size_t len, + uint32_t src, FAR void *priv); static int rpmsgmtd_ioctl_handler(FAR struct rpmsg_endpoint *ept, FAR void *data, size_t len, uint32_t src, FAR void *priv); @@ -93,12 +96,13 @@ static int rpmsgmtd_ept_cb(FAR struct rpmsg_endpoint *ept, static const rpmsg_ept_cb g_rpmsgmtd_handler[] = { - [RPMSGMTD_ERASE] = rpmsgmtd_erase_handler, - [RPMSGMTD_BREAD] = rpmsgmtd_bread_handler, - [RPMSGMTD_BWRITE] = rpmsgmtd_bwrite_handler, - [RPMSGMTD_READ] = rpmsgmtd_read_handler, - [RPMSGMTD_WRITE] = rpmsgmtd_write_handler, - [RPMSGMTD_IOCTL] = rpmsgmtd_ioctl_handler, + [RPMSGMTD_ERASE] = rpmsgmtd_erase_handler, + [RPMSGMTD_BREAD] = rpmsgmtd_bread_handler, + [RPMSGMTD_BWRITE] = rpmsgmtd_bwrite_handler, + [RPMSGMTD_READ] = rpmsgmtd_read_handler, + [RPMSGMTD_WRITE] = rpmsgmtd_write_handler, + [RPMSGMTD_GEOMETRY] = rpmsgmtd_geometry_handler, + [RPMSGMTD_IOCTL] = rpmsgmtd_ioctl_handler, }; /**************************************************************************** @@ -284,6 +288,39 @@ static int rpmsgmtd_write_handler(FAR struct rpmsg_endpoint *ept, return 0; } +/**************************************************************************** + * Name: rpmsgmtd_geometry_handler + ****************************************************************************/ + +static int rpmsgmtd_geometry_handler(FAR struct rpmsg_endpoint *ept, + FAR void *data, size_t len, + uint32_t src, FAR void *priv) +{ + FAR struct rpmsgmtd_server_s *server = ept->priv; + FAR struct rpmsgmtd_geometry_s *msg = data; + struct mtd_geometry_s geo; + + msg->header.result = MTD_IOCTL(server->dev, MTDIOC_GEOMETRY, + (unsigned long)&geo); + + if (msg->header.result < 0) + { + ferr("mtd get geometry result error: %" PRId32 "\n", + msg->header.result); + goto send; + } + + DEBUGASSERT(strlen(geo.model) <= RPMSGMTD_NAME_MAX); + + msg->blocksize = geo.blocksize; + msg->erasesize = geo.erasesize; + msg->neraseblocks = geo.neraseblocks; + strlcpy(msg->model, geo.model, sizeof(msg->model)); + +send: + return rpmsg_send(ept, msg, len); +} + /**************************************************************************** * Name: rpmsgmtd_ioctl_handler ****************************************************************************/ diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index be6130891b885..96a0e8ec40590 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -56,7 +56,7 @@ comment "General Ethernet MAC Driver Options" config NET_RPMSG_DRV bool "RPMSG net driver" - depends on RPTUN + depends on RPMSG select ARCH_HAVE_NETDEV_STATISTICS ---help--- Use the RPMSG as net device, transfer packet between remoteproc. @@ -549,6 +549,13 @@ choice config ETH0_PHY_NONE bool "No PHY support" +config ETH0_PHY_MULTI + bool "Multiple PHYs are supported" + ---help--- + The Board will provide a list of PHYs to probe for. + The first one found on the bpard will be used. + This setting is not supported by all Ethernet drivers. + config ETH0_PHY_AM79C874 bool "AMD Am79C874 PHY" @@ -603,6 +610,9 @@ config ETH0_PHY_LAN8740A config ETH0_PHY_LAN8742A bool "SMSC LAN8742A PHY" +config ETH0_PHY_RTL8211F + bool "Realtek RTL8211F PHY" + config ETH0_PHY_DM9161 bool "Davicom DM9161 PHY" @@ -656,6 +666,9 @@ config ETH1_PHY_TJA1101 config ETH1_PHY_LAN8720 bool "SMSC LAN8720 PHY" +config ETH1_PHY_RTL8211F + bool "Realtek RTL8211F PHY" + config ETH1_PHY_DM9161 bool "Davicom DM9161 PHY" diff --git a/drivers/net/lan9250.c b/drivers/net/lan9250.c index 256371b160dac..6dec277bbf9ab 100644 --- a/drivers/net/lan9250.c +++ b/drivers/net/lan9250.c @@ -1521,7 +1521,7 @@ static void lan9250_txavail_work(FAR void *arg) /* Ignore the notification if the interface is not yet up */ - if (IFF_IS_UP(dev->d_flags)) + if (IFF_IS_UP(dev->d_flags) && priv->tx_available) { /* Check if there is room in the hardware to hold another outgoing * packet. @@ -2258,29 +2258,8 @@ static int lan9250_txavail(FAR struct net_driver_s *dev) { FAR struct lan9250_driver_s *priv = (FAR struct lan9250_driver_s *)dev->d_private; - irqstate_t flags; - - /* Lock the SPI bus so that we have exclusive access for but SPI and - * LAN9250 SPI private data. - */ - - lan9250_lock_spi(priv); - - flags = enter_critical_section(); - /* Since SPI is locked, so interrupt work must not really process when - * CPU run here, so: - * - * - priv->tx_available = true, TX data FIFO is available and its related - * interrupt is disable. - * - priv->tx_available = false, TX data FIFO is unavailable and its - * related interrupt is enable, so when this interrupt triggers, - * function "devif_poll" will poll the network for new XMIT data. - */ - - if (IFF_IS_UP(dev->d_flags) && - priv->tx_available && - work_available(&priv->txpoll_work)) + if (work_available(&priv->txpoll_work)) { /* Schedule to serialize the poll on the worker thread. */ @@ -2288,10 +2267,6 @@ static int lan9250_txavail(FAR struct net_driver_s *dev) lan9250_txavail_work, priv, 0); } - /* Un-lock the SPI bus */ - - leave_critical_section(flags); - lan9250_unlock_spi(priv); return OK; } diff --git a/drivers/net/netdev_upperhalf.c b/drivers/net/netdev_upperhalf.c index 61302617482ef..a97f3202b3c63 100644 --- a/drivers/net/netdev_upperhalf.c +++ b/drivers/net/netdev_upperhalf.c @@ -115,6 +115,40 @@ static int quota_fetch_dec(FAR struct netdev_lowerhalf_s *lower, #endif } +/**************************************************************************** + * Name: quota_is_valid + * + * Description: + * Check if the quota of the lower half is not too big. + * + ****************************************************************************/ + +static bool quota_is_valid(FAR struct netdev_lowerhalf_s *lower) +{ + int total = 0; + int type; + + for (type = 0; type < NETPKT_TYPENUM; type++) + { + total += netdev_lower_quota_load(lower, type); + } + + if (total > NETPKT_BUFNUM) + { + nerr("ERROR: Too big quota when registering device: %d\n", total); + return false; + } + + if (total > NETPKT_BUFNUM / 2) + { + nwarn("WARNING: The quota of the registering device may consume more " + "than half of the network buffers, which may hurt performance. " + "Please consider decreasing driver quota or increasing nIOB.\n"); + } + + return true; +} + /**************************************************************************** * Name: netpkt_get * @@ -405,6 +439,69 @@ static void eth_input(FAR struct net_driver_s *dev) } #endif +/**************************************************************************** + * Name: ip_input + * + * Description: + * Handle L3 packet input. + * + * Input Parameters: + * dev - Reference to the NuttX network driver state structure + * + * Assumptions: + * Called with the network locked. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_MBIM +static void ip_input(FAR struct net_driver_s *dev) +{ + /* We only accept IP packets of the configured type */ + +#ifdef CONFIG_NET_IPv4 + if ((IPv4BUF->vhl & IP_VERSION_MASK) == IPv4_VERSION) + { + ninfo("IPv4 frame\n"); + NETDEV_RXIPV4(dev); + + /* Receive an IPv4 packet from the network device */ + + ipv4_input(dev); + } + else +#endif +#ifdef CONFIG_NET_IPv6 + if ((IPv6BUF->vtc & IP_VERSION_MASK) == IPv6_VERSION) + { + ninfo("IPv6 frame\n"); + NETDEV_RXIPV6(dev); + + /* Give the IPv6 packet to the network layer */ + + ipv6_input(dev); + } + else +#endif + { + ninfo("INFO: Dropped, Unknown type\n"); + NETDEV_RXDROPPED(dev); + dev->d_len = 0; + } + + /* If the above function invocation resulted in data + * that should be sent out on the network, + * the field d_len will set to a value > 0. + */ + + if (dev->d_len > 0) + { + /* And send the packet */ + + netdev_upper_txpoll(dev); + } +} +#endif + /**************************************************************************** * Function: netdev_upper_rxpoll_work * @@ -465,6 +562,11 @@ static void netdev_upper_rxpoll_work(FAR struct netdev_upperhalf_s *upper) eth_input(dev); break; #endif +#ifdef CONFIG_NET_MBIM + case NET_LL_MBIM: + ip_input(dev); + break; +#endif #ifdef CONFIG_NET_CAN case NET_LL_CAN: ninfo("CAN frame"); @@ -961,7 +1063,7 @@ int netdev_lower_register(FAR struct netdev_lowerhalf_s *dev, FAR struct netdev_upperhalf_s *upper; int ret; - if (dev == NULL || dev->ops == NULL || + if (dev == NULL || quota_is_valid(dev) == false || dev->ops == NULL || dev->ops->transmit == NULL || dev->ops->receive == NULL) { return -EINVAL; diff --git a/drivers/net/tun.c b/drivers/net/tun.c index e4374185b9c13..9a81cd7e10609 100644 --- a/drivers/net/tun.c +++ b/drivers/net/tun.c @@ -306,6 +306,13 @@ static int tun_txpoll(FAR struct net_driver_s *dev) int ret; DEBUGASSERT(priv->read_buf == NULL); + +#ifdef CONFIG_NET_PKT + /* When packet sockets are enabled, feed the frame into the tap */ + + pkt_input(dev); +#endif + priv->read_d_len = dev->d_len; priv->read_buf = dev->d_iob; netdev_iob_clear(dev); @@ -990,6 +997,7 @@ static ssize_t tun_write(FAR struct file *filep, FAR const char *buffer, if (priv->write_d_len == 0) { net_lock(); + netdev_iob_release(&priv->dev); ret = netdev_iob_prepare(&priv->dev, false, 0); priv->dev.d_buf = NULL; if (ret < 0) diff --git a/drivers/note/note_driver.c b/drivers/note/note_driver.c index 758f1c5a774c7..b02d94e98f34c 100644 --- a/drivers/note/note_driver.c +++ b/drivers/note/note_driver.c @@ -162,8 +162,8 @@ static void note_driver_instrument_leave(FAR void *this_fn, FAR void *call_site, FAR void *arg) noinstrument_function; static struct instrument_s g_note_instrument = { - .entry = note_driver_instrument_enter, - .exit = note_driver_instrument_leave, + .enter = note_driver_instrument_enter, + .leave = note_driver_instrument_leave, }; #endif @@ -1969,7 +1969,7 @@ int note_driver_register(FAR struct note_driver_s *driver) if (!initialized) { - instrument_register(g_note_instrument) + instrument_register(&g_note_instrument); initialized = true; } #endif diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig new file mode 100644 index 0000000000000..85aa4a7988a81 --- /dev/null +++ b/drivers/pci/Kconfig @@ -0,0 +1,11 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +menuconfig PCI + bool "Support for PCI Bus" + default n + ---help--- + Enables support for the PCI bus. + Backend bust be provided by per-arch or per-board implementation. diff --git a/drivers/pci/Make.defs b/drivers/pci/Make.defs new file mode 100644 index 0000000000000..2b0a4c49016ef --- /dev/null +++ b/drivers/pci/Make.defs @@ -0,0 +1,30 @@ +############################################################################ +# drivers/pci/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +ifeq ($(CONFIG_PCI),y) + +CSRCS += pci.c + +# Include PCI device driver build support + +DEPPATH += --dep-path pci +VPATH += :pci +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)drivers$(DELIM)pci +endif diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c new file mode 100644 index 0000000000000..9e9ba848a1d2b --- /dev/null +++ b/drivers/pci/pci.c @@ -0,0 +1,832 @@ +/**************************************************************************** + * drivers/pci/pci.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* For now hard code jailhouse as a flag. In the future we can determine this + * by looking at the CPUID base for "Jailhouse\0\0\0" + */ + +#define JAILHOUSE_ENABLED 1 + +#define PCI_BDF(bus, slot, func) (((uint32_t)bus << 8) | \ + ((uint32_t)slot << 3) | \ + func) + +/**************************************************************************** + * Private Functions Definitions + ****************************************************************************/ + +static void pci_probe_device(FAR struct pci_bus_s *root_bus, + uint8_t bus_idx, uint8_t slot_idx, uint8_t func, + FAR const struct pci_dev_type_s **types); + +static uint8_t pci_check_pci_bridge(FAR struct pci_bus_s *root_bus, + uint8_t bus_idx, uint8_t slot_idx, + uint8_t dev_func); + +static void pci_scan_device(FAR struct pci_bus_s *root_bus, + uint8_t bus_idx, uint8_t slot_idx, + FAR const struct pci_dev_type_s **types); + +static void pci_scan_bus(FAR struct pci_bus_s *root_bus, + uint8_t bus_idx, + FAR const struct pci_dev_type_s **types); + +static void pci_set_cmd_bit(FAR struct pci_dev_s *dev, uint16_t bitmask); + +static void pci_clear_cmd_bit(FAR struct pci_dev_s *dev, uint16_t bitmask); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +const struct pci_dev_type_s *g_pci_device_types[] = +{ +#ifdef CONFIG_VIRT_QEMU_PCI_TEST + &g_pci_type_qemu_pci_test, +#endif +#ifdef CONFIG_VIRT_QEMU_EDU + &g_pci_type_qemu_edu, +#endif + NULL, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pci_probe + * + * Description: + * Checks if the specified device is supported and if so calls probe on it + * + * Input Parameters: + * root_bus - The root bus device that lets us address the whole tree + * bus - Bus ID + * slot - Device Slot + * func - Device Function + * types - List of pointers to devices types recognized, NULL terminated + * + ****************************************************************************/ + +static void pci_probe_device(FAR struct pci_bus_s *root_bus, + uint8_t bus_idx, uint8_t slot_idx, uint8_t func, + FAR const struct pci_dev_type_s **types) +{ + struct pci_dev_s tmp_dev; + uint32_t class_rev; + uint16_t vid; + uint16_t id; + int i; + + tmp_dev.bus = root_bus; + tmp_dev.bdf = PCI_BDF(bus_idx, slot_idx, func); + + vid = root_bus->ops->pci_cfg_read(&tmp_dev, PCI_CONFIG_VENDOR, 2); + id = root_bus->ops->pci_cfg_read(&tmp_dev, PCI_CONFIG_DEVICE, 2); + + /* This is reading rev prog_if subclass and class */ + + class_rev = root_bus->ops->pci_cfg_read(&tmp_dev, PCI_CONFIG_REV_ID, 4); + + pci_dev_dump(&tmp_dev); + + for (i = 0; types[i] != NULL; i++) + { + if (types[i]->vendor == PCI_ID_ANY || + types[i]->vendor == vid) + { + if (types[i]->device == PCI_ID_ANY || + types[i]->device == id) + { + if (types[i]->class_rev == PCI_ID_ANY || + types[i]->class_rev == class_rev) + { + pciinfo("Found: %s\n", types[i]->name); + if (types[i]->probe) + { + pciinfo("[%02x:%02x.%x] Probing\n", + bus_idx, slot_idx, func); + types[i]->probe(root_bus, types[i], tmp_dev.bdf); + } + else + { + pcierr("[%02x:%02x.%x] Error: Invalid" + "device probe function\n", + bus_idx, slot_idx, func); + } + + break; + } + } + } + } +} + +/**************************************************************************** + * Name: pci_check_pci_bridge + * + * Description: + * Checks if the specified device is PCI bridge and return the sub-bridge + * idx if found. Otherwise return 0. + * + * Input Parameters: + * root_bus - The root bus device that lets us address the whole tree + * bus - Bus ID + * slot - Device Slot + * func - Device Function + * + ****************************************************************************/ + +static uint8_t pci_check_pci_bridge(FAR struct pci_bus_s *root_bus, + uint8_t bus_idx, uint8_t slot_idx, + uint8_t dev_func) +{ + struct pci_dev_s tmp_dev; + uint8_t base_class; + uint8_t sub_class; + uint8_t secondary_bus; + + tmp_dev.bus = root_bus; + tmp_dev.bdf = PCI_BDF(bus_idx, slot_idx, dev_func); + + /* Check if this is a PCI-PCI bridge device */ + + base_class = root_bus->ops->pci_cfg_read(&tmp_dev, PCI_CONFIG_CLASS, 1); + sub_class = root_bus->ops->pci_cfg_read(&tmp_dev, PCI_CONFIG_SUBCLASS, 1); + + if ((base_class == PCI_CLASS_BASE_BRG_DEV) && + (sub_class == PCI_CLASS_SUB_PCI_BRG)) + { + /* This is a bridge device we need to determine the bus idx and + * enumerate it just like we do the root. + */ + + pciinfo("[%02x:%02x.%x] Found Bridge\n", + bus_idx, slot_idx, dev_func); + + secondary_bus = root_bus->ops->pci_cfg_read( + &tmp_dev, PCI_CONFIG_SEC_BUS, 1); + + return secondary_bus; + } + + return 0; +} + +/**************************************************************************** + * Name: pci_scan_device + * + * Description: + * Checks if the specified device is a bus and iterates over it or + * if it is a real device initializes it if recognized. + * + * Input Parameters: + * root_bus - The root bus device that lets us address the whole tree + * bus - Bus ID + * slot - Device Slot + * types - List of pointers to devices types recognized, NULL terminated + * + ****************************************************************************/ + +static void pci_scan_device(FAR struct pci_bus_s *root_bus, + uint8_t bus_idx, uint8_t slot_idx, + FAR const struct pci_dev_type_s **types) +{ + struct pci_dev_s tmp_dev; + uint8_t multi_function; + uint8_t dev_func = 0; + uint16_t vid; + uint8_t sec_bus; + + tmp_dev.bus = root_bus; + tmp_dev.bdf = PCI_BDF(bus_idx, slot_idx, dev_func); + vid = root_bus->ops->pci_cfg_read(&tmp_dev, PCI_CONFIG_VENDOR, 2); + if (vid == 0xffff) + { + return; + } + + multi_function = root_bus->ops->pci_cfg_read( + &tmp_dev, PCI_CONFIG_HEADER_TYPE, 1) & PCI_HEADER_MASK_MULTI; + + /* Jailhouse breaks the PCI spec by allowing you to pass individual + * functions of a multi-function device. In this case we need to + * scan each of the functions not just function 0. + */ + + if (multi_function || JAILHOUSE_ENABLED) + { + /* This is a multi-function device that we need to iterate over */ + + for (dev_func = 0; dev_func < 8; dev_func++) + { + tmp_dev.bdf = PCI_BDF(bus_idx, slot_idx, dev_func); + vid = root_bus->ops->pci_cfg_read(&tmp_dev, PCI_CONFIG_VENDOR, 2); + + if (vid != 0xffff) + { + sec_bus = pci_check_pci_bridge( + root_bus, bus_idx, slot_idx, dev_func); + + if (sec_bus) + { + pci_scan_bus(root_bus, sec_bus, types); + continue; + } + + pci_probe_device(root_bus, bus_idx, slot_idx, dev_func, types); + } + } + } + else + { + /* Check if this is a PCI-PCI bridge device with MF=0 */ + + sec_bus = pci_check_pci_bridge(root_bus, bus_idx, slot_idx, dev_func); + if (sec_bus) + { + pci_scan_bus(root_bus, sec_bus, types); + } + else + { + pci_probe_device(root_bus, bus_idx, slot_idx, dev_func, types); + } + } +} + +/**************************************************************************** + * Name: pci_scan_bus + * + * Description: + * Iterates over all slots on bus looking for devices and buses to + * enumerate. + * + * Input Parameters: + * root_bus - The root bus device that lets us address the whole tree + * bus - Bus ID + * types - List of pointers to devices types recognized, NULL terminated + * + ****************************************************************************/ + +static void pci_scan_bus(FAR struct pci_bus_s *root_bus, + uint8_t bus_idx, + FAR const struct pci_dev_type_s **types) +{ + uint8_t slot_idx; + + for (slot_idx = 0; slot_idx < 32; slot_idx++) + { + pci_scan_device(root_bus, bus_idx, slot_idx, types); + } +} + +/**************************************************************************** + * Name: pci_set_cmd_bit + * + * Description: + * This sets an individual bit in the command register for a device. + * + * Input Parameters: + * dev - device + * bit - Bit to set + * + ****************************************************************************/ + +static void pci_set_cmd_bit(FAR struct pci_dev_s *dev, uint16_t bitmask) +{ + uint16_t cmd; + + cmd = dev->bus->ops->pci_cfg_read(dev, PCI_CONFIG_COMMAND, 2); + dev->bus->ops->pci_cfg_write(dev, PCI_CONFIG_COMMAND, + (cmd | bitmask), 2); +} + +/**************************************************************************** + * Name: pci_clear_cmd_bit + * + * Description: + * This clears an individual bit in the command register for a device. + * + * Input Parameters: + * dev - device + * bit - Bit to set + * + ****************************************************************************/ + +static void pci_clear_cmd_bit(FAR struct pci_dev_s *dev, uint16_t bitmask) +{ + uint16_t cmd; + + cmd = dev->bus->ops->pci_cfg_read(dev, PCI_CONFIG_COMMAND, 2); + dev->bus->ops->pci_cfg_write(dev, PCI_CONFIG_COMMAND, + (cmd & ~bitmask), 2); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pci_enumerate + * + * Description: + * Scan the PCI bus and enumerate the devices. + * Initialize any recognized devices, given in types. + * + * Input Parameters: + * bus - PCI-E bus structure + * types - List of pointers to devices types recognized, NULL terminated + * + * Returned Value: + * 0: success, <0: A negated errno + * + ****************************************************************************/ + +int pci_enumerate(FAR struct pci_bus_s *bus, + FAR const struct pci_dev_type_s **types) +{ + if (!bus) + { + return -EINVAL; + } + + if (!types) + { + return -EINVAL; + } + + pci_scan_bus(bus, 0, types); + return OK; +} + +/**************************************************************************** + * Name: pci_initialize + * + * Description: + * Initialize the PCI-E bus and enumerate the devices with give devices + * type array + * + * Input Parameters: + * bus - An PCIE bus + * types - A array of PCIE device types + * num - Number of device types + * + * Returned Value: + * OK if the driver was successfully register; A negated errno value is + * returned on any failure. + * + ****************************************************************************/ + +int pci_initialize(FAR struct pci_bus_s *bus) +{ + return pci_enumerate(bus, g_pci_device_types); +} + +/**************************************************************************** + * Name: pci_enable_io + * + * Description: + * Enable MMIO or IOPORT + * + * Input Parameters: + * dev - device + * space - which resource is being enabled + * PCI_SYS_RES_IOPORT for io port address decoding or + * PCI_SYS_RES_MEM for memory + * + * Return value: + * -EINVAL: error + * OK: OK + * + ****************************************************************************/ + +int pci_enable_io(FAR struct pci_dev_s *dev, int res) +{ + switch (res) + { + case PCI_SYS_RES_IOPORT: + { + pci_set_cmd_bit(dev, PCI_CMD_IO_SPACE); + return OK; + } + + case PCI_SYS_RES_MEM: + { + pci_set_cmd_bit(dev, PCI_CMD_MEM_SPACE); + return OK; + } + } + + return -EINVAL; +} + +/**************************************************************************** + * Name: pci_disable_io + * + * Description: + * Enable MMIO or IOPORT + * + * Input Parameters: + * dev - device + * space - which resource is being disabled + * PCI_SYS_RES_IOPORT for io port address decoding or + * PCI_SYS_RES_MEM for memory + * + * Return value: + * -EINVAL: error + * OK: OK + * + ****************************************************************************/ + +int pci_disable_io(FAR struct pci_dev_s *dev, int res) +{ + switch (res) + { + case PCI_SYS_RES_IOPORT: + { + pci_clear_cmd_bit(dev, PCI_CMD_IO_SPACE); + return OK; + } + + case PCI_SYS_RES_MEM: + { + pci_clear_cmd_bit(dev, PCI_CMD_MEM_SPACE); + return OK; + } + } + + return -EINVAL; +} + +/**************************************************************************** + * Name: pci_enable_bus_master + * + * Description: + * Enable bus mastering for device so it can perform PCI accesses + * + * Input Parameters: + * dev - device + * + * Return value: + * -EINVAL: error + * OK: OK + * + ****************************************************************************/ + +int pci_enable_bus_master(FAR struct pci_dev_s *dev) +{ + pci_set_cmd_bit(dev, PCI_CMD_BUS_MSTR); + return OK; +} + +/**************************************************************************** + * Name: pci_disable_bus_master + * + * Description: + * Disable bus mastering for device + * + * Input Parameters: + * dev - device + * + * Return value: + * -EINVAL: error + * OK: OK + * + ****************************************************************************/ + +int pci_disable_bus_master(FAR struct pci_dev_s *dev) +{ + pci_clear_cmd_bit(dev, PCI_CMD_BUS_MSTR); + return OK; +} + +/**************************************************************************** + * Name: pci_bar_valid + * + * Description: + * Determine in if the address in the BAR is valid + * + * Input Parameters: + * dev - device + * bar_id - bar number + * + * Return value: + * -EINVAL: error + * OK: OK + * + ****************************************************************************/ + +int pci_bar_valid(FAR struct pci_dev_s *dev, uint8_t bar_id) +{ + uint32_t bar = dev->bus->ops->pci_cfg_read(dev, + PCI_HEADER_NORM_BAR0 + (bar_id * 4), 4); + + if (bar == PCI_BAR_INVALID) + { + return -EINVAL; + } + + return OK; +} + +/**************************************************************************** + * Name: pci_bar_is_64 + * + * Description: + * Determine in if the bar address is 64 bit. If it is the address includes + * the address in the next bar location. + * + * Input Parameters: + * dev - device + * bar_id - bar number + * + * Return value: + * true: 64bit address + * + ****************************************************************************/ + +bool pci_bar_is_64(FAR struct pci_dev_s *dev, uint8_t bar_id) +{ + uint32_t bar = dev->bus->ops->pci_cfg_read(dev, + PCI_HEADER_NORM_BAR0 + (bar_id * 4), 4); + + /* Check that it is memory and not io port */ + + if ((bar & PCI_BAR_LAYOUT_MASK) != PCI_BAR_LAYOUT_MEM) + { + return false; + } + + if (((bar & PCI_BAR_TYPE_MASK) >> PCI_BAR_TYPE_OFFSET) == PCI_BAR_TYPE_64) + { + return true; + } + + return false; +} + +/**************************************************************************** + * Name: pci_bar_size + * + * Description: + * Determine the size of the address space required by the BAR + * + * Input Parameters: + * dev - device + * bar_id - bar number + * + * Return value: + * Size of address space + * + ****************************************************************************/ + +uint64_t pci_bar_size(FAR struct pci_dev_s *dev, uint8_t bar_id) +{ + FAR const struct pci_bus_ops_s *dev_ops = dev->bus->ops; + uint32_t bar; + uint32_t size; + uint64_t full_size; + uint8_t bar_offset; + + bar_offset = PCI_HEADER_NORM_BAR0 + (bar_id * 4); + bar = dev_ops->pci_cfg_read(dev, bar_offset, 4); + + /* Write all 1 to the BAR. We are looking for which bits will change */ + + dev_ops->pci_cfg_write(dev, bar_offset, 0xffffffff, 4); + full_size = dev_ops->pci_cfg_read(dev, bar_offset, 4); + + /* Resore BAR to original values */ + + dev_ops->pci_cfg_write(dev, bar_offset, bar, 4); + + if (full_size == 0) + { + /* This is not a valid bar */ + + return 0; + } + + if ((bar & PCI_BAR_LAYOUT_MASK) == PCI_BAR_LAYOUT_MEM) + { + full_size &= PCI_BAR_MEM_BASE_MASK; + } + else + { + full_size &= PCI_BAR_IO_BASE_MASK; + } + + /* If it is 64 bit address check the next bar as well */ + + if (pci_bar_is_64(dev, bar_id)) + { + bar_offset += 4; + bar = dev_ops->pci_cfg_read(dev, bar_offset, 4); + dev_ops->pci_cfg_write(dev, bar_offset, 0xffffffff, 4); + size = dev_ops->pci_cfg_read(dev, bar_offset, 4); + dev_ops->pci_cfg_write(dev, bar_offset, bar, 4); + full_size |= ((uint64_t)size << 32); + } + else + { + full_size |= (uint64_t)(0xffffffff) << 32; + } + + return ~full_size + 1; +} + +/**************************************************************************** + * Name: pci_bar_addr + * + * Description: + * Determine the size of the address space required by the BAR + * + * Input Parameters: + * dev - device + * bar_id - bar number + * + * Return value: + * full bar address + * + ****************************************************************************/ + +uint64_t pci_bar_addr(FAR struct pci_dev_s *dev, uint8_t bar_id) +{ + FAR const struct pci_bus_ops_s *dev_ops = dev->bus->ops; + uint64_t addr; + uint8_t bar_offset; + + bar_offset = PCI_HEADER_NORM_BAR0 + (bar_id * 4); + addr = dev_ops->pci_cfg_read(dev, bar_offset, 4); + + if ((addr & PCI_BAR_LAYOUT_MASK) == PCI_BAR_LAYOUT_MEM) + { + addr &= PCI_BAR_MEM_BASE_MASK; + } + else + { + addr &= PCI_BAR_IO_BASE_MASK; + } + + /* If it is 64 bit address check the next bar as well */ + + if (pci_bar_is_64(dev, bar_id)) + { + bar_offset += 4; + addr |= (uint64_t)(dev_ops->pci_cfg_read(dev, bar_offset, 4)) << 32; + } + + return addr; +} + +/**************************************************************************** + * Name: pci_dev_dump + * + * Description: + * Dump the configuration information for the device + * + * Input Parameters: + * dev - device + * + ****************************************************************************/ + +void pci_dev_dump(FAR struct pci_dev_s *dev) +{ + FAR const struct pci_bus_ops_s *dev_ops = dev->bus->ops; + uint8_t bar_mem_type = 0; + uint8_t bar_id; + uint32_t bar; + uint64_t bar_size; + uint64_t bar_addr; + uint8_t cap_id; + uint8_t cap_offset; + uint32_t bdf; + uint16_t vid; + uint16_t pid; + uint8_t header; + uint8_t progif; + uint8_t subclass; + uint8_t class; + uint8_t int_pin; + uint8_t int_line; + + bdf = dev->bdf; + vid = dev_ops->pci_cfg_read(dev, PCI_CONFIG_VENDOR, 2); + pid = dev_ops->pci_cfg_read(dev, PCI_CONFIG_DEVICE, 2); + header = dev_ops->pci_cfg_read(dev, PCI_CONFIG_HEADER_TYPE, 1); + progif = dev_ops->pci_cfg_read(dev, PCI_CONFIG_PROG_IF, 1); + subclass = dev_ops->pci_cfg_read(dev, PCI_CONFIG_SUBCLASS, 1); + class = dev_ops->pci_cfg_read(dev, PCI_CONFIG_CLASS, 1); + + pciinfo("[%02x:%02x.%x] %04x:%04x\n", + bdf >> 8, (bdf & 0xff) >> 3, bdf & 0x7, vid, pid); + pciinfo("\ttype %02x Prog IF %02x Class %02x Subclass %02x\n", + header, progif, class, subclass); + + cap_offset = dev_ops->pci_cfg_read(dev, PCI_HEADER_NORM_CAP, 1); + while (cap_offset) + { + cap_id = dev_ops->pci_cfg_read(dev, cap_offset, 1); + if (cap_id > PCI_CAP_ID_END) + { + pcierr("Invalid PCI Capability Found, Skipping. %d\n", cap_id); + DEBUGPANIC(); + break; + } + + pciinfo("\tCAP %02x\n", cap_id); + cap_offset = dev_ops->pci_cfg_read(dev, cap_offset + 1, 1); + } + + if ((header & PCI_HEADER_TYPE_MASK) != PCI_HEADER_NORMAL) + { + return; + } + + int_pin = dev_ops->pci_cfg_read(dev, PCI_HEADER_NORM_INT_PIN, 1); + int_line = dev_ops->pci_cfg_read(dev, PCI_HEADER_NORM_INT_LINE, 1); + pciinfo("\tINT Pin %02x Line %02x\n", int_pin, int_line); + + for (bar_id = 0; bar_id < PCI_BAR_CNT; bar_id++) + { + if (pci_bar_valid(dev, bar_id) != OK) + { + continue; + } + + bar = dev_ops->pci_cfg_read(dev, + PCI_HEADER_NORM_BAR0 + (bar_id * 4), 4); + + bar_size = pci_bar_size(dev, bar_id); + bar_addr = pci_bar_addr(dev, bar_id); + if ((bar & PCI_BAR_LAYOUT_MASK) == PCI_BAR_LAYOUT_MEM) + { + switch ((bar & PCI_BAR_TYPE_MASK) >> PCI_BAR_TYPE_OFFSET) + { + case PCI_BAR_TYPE_64: + bar_mem_type = 64; + break; + case PCI_BAR_TYPE_32: + bar_mem_type = 32; + break; + case PCI_BAR_TYPE_16: + bar_mem_type = 16; + break; + default: + bar_mem_type = 0; + } + + pciinfo("\tBAR [%d] MEM %db range %p-%p (%p)\n", + bar_id, bar_mem_type, + bar_addr, bar_addr + bar_size - 1, bar_size); + } + else + { + pciinfo("\tBAR [%d] PIO range %p-%p (%p)\n", + bar_id, + bar_addr, bar_addr + bar_size - 1, bar_size); + } + + /* Skip next bar if this one was 64bit */ + + if (bar_mem_type == 64) + { + bar_id++; + } + } +} diff --git a/drivers/pipes/pipe.c b/drivers/pipes/pipe.c index 61918b8f5e9d3..4220db4d7ac22 100644 --- a/drivers/pipes/pipe.c +++ b/drivers/pipes/pipe.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include @@ -207,8 +208,8 @@ static int pipe_register(size_t bufsize, int flags, int file_pipe(FAR struct file *filep[2], size_t bufsize, int flags) { char devname[32]; + int nonblock = !!(flags & O_NONBLOCK); int ret; - bool blocking; /* Register a new pipe device */ @@ -218,10 +219,6 @@ int file_pipe(FAR struct file *filep[2], size_t bufsize, int flags) return ret; } - /* Check for the O_NONBLOCK bit on flags */ - - blocking = (flags & O_NONBLOCK) == 0; - /* Get a write file descriptor */ ret = file_open(filep[1], devname, O_WRONLY | O_NONBLOCK | flags); @@ -232,9 +229,9 @@ int file_pipe(FAR struct file *filep[2], size_t bufsize, int flags) /* Clear O_NONBLOCK if it was set previously */ - if (blocking) + if (!nonblock) { - ret = file_fcntl(filep[1], F_SETFL, flags & (~O_NONBLOCK)); + ret = file_ioctl(filep[1], FIONBIO, &nonblock); if (ret < 0) { goto errout_with_driver; @@ -284,6 +281,7 @@ int file_pipe(FAR struct file *filep[2], size_t bufsize, int flags) int pipe2(int fd[2], int flags) { char devname[32]; + int nonblock = !!(flags & O_NONBLOCK); int ret; /* Register a new pipe device */ @@ -305,9 +303,9 @@ int pipe2(int fd[2], int flags) /* Clear O_NONBLOCK if it was set previously */ - if ((flags & O_NONBLOCK) == 0) + if (!nonblock) { - ret = fcntl(fd[1], F_SETFL, flags & (~O_NONBLOCK)); + ret = ioctl(fd[1], FIONBIO, &nonblock); if (ret < 0) { goto errout_with_driver; diff --git a/drivers/power/battery/goldfish_battery.c b/drivers/power/battery/goldfish_battery.c index 1991ab9794e11..0009bbe130c5b 100644 --- a/drivers/power/battery/goldfish_battery.c +++ b/drivers/power/battery/goldfish_battery.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/power/pm/CMakeLists.txt b/drivers/power/pm/CMakeLists.txt index 94df6762aaf95..519bf923ff9c4 100644 --- a/drivers/power/pm/CMakeLists.txt +++ b/drivers/power/pm/CMakeLists.txt @@ -43,6 +43,12 @@ if(CONFIG_PM) # Governor implementations + if(CONFIG_PM_GOVERNOR_STABILITY) + + list(APPEND SRCS stability_governor.c) + + endif() + if(CONFIG_PM_GOVERNOR_ACTIVITY) list(APPEND SRCS activity_governor.c) diff --git a/drivers/power/pm/Kconfig b/drivers/power/pm/Kconfig index fb2447da872dc..f8bf3d5b1803f 100644 --- a/drivers/power/pm/Kconfig +++ b/drivers/power/pm/Kconfig @@ -47,6 +47,16 @@ config PM_GOVERNOR_GREEDY considering any states locked by calls to pm_stay() (accessible via BOARDIOC_PM_STAY boardctl calls). +config PM_GOVERNOR_STABILITY + bool "Stability governor" + ---help--- + This governor will hold power state to ensure the request is stable + enough, other behavior is similar with greedy. + only when stay in WFI for enough time allow goto target state, or + will backward to the last state used. + considering any states locked by calls to pm_stay() (accessible + via BOARDIOC_PM_STAY boardctl calls). + config PM_GOVERNOR_ACTIVITY bool "Activity based" ---help--- @@ -77,6 +87,40 @@ config PM_GOVERNOR_EXPLICIT_RELAX if set to timeout (unit: ms), that means pm_staytimeout(ms). pm_relax() will be auto called after timeout. +if PM_GOVERNOR_STABILITY + +config PM_GOVERNOR_STABILITY_IDLE_THRESH + int "Enter idle thresh >= (ticks)" + default 0 + ---help--- + Only if first time try goto idle, can remain wfi for (ticks) + and second time still try goto this state, goto idle, + otherwise keep last state. + only if remained for >=(ticks), allow goto idle state. + set to 0 disable stability check for idle state. + +config PM_GOVERNOR_STABILITY_STANDBY_THRESH + int "Enter standby thresh >= (ticks)" + default 0 + ---help--- + Only if first time try goto standby, can remain wfi for (ticks) + and second time still try goto this state, goto standby, + otherwise keep last state. + only if remained for >=(ticks), allow goto standby state. + set to 0 disable stability check for standby state. + +config PM_GOVERNOR_STABILITY_SLEEP_THRESH + int "Enter sleep thresh >= (ticks)" + default 0 + ---help--- + Only if first time try goto sleep, can remain wfi for (ticks) + and second time still try goto this state, goto sleep, + otherwise keep last state. + only if remained for >=(ticks), allow goto sleep state. + set to 0 disable stability check for sleep state. + +endif # PM_GOVERNOR_STABILITY + if PM_GOVERNOR_ACTIVITY config PM_GOVERNOR_SLICEMS diff --git a/drivers/power/pm/Make.defs b/drivers/power/pm/Make.defs index 645bb7a0bbddc..d26a28712a7c3 100644 --- a/drivers/power/pm/Make.defs +++ b/drivers/power/pm/Make.defs @@ -39,6 +39,12 @@ endif # Governor implementations +ifeq ($(CONFIG_PM_GOVERNOR_STABILITY),y) + +CSRCS += stability_governor.c + +endif + ifeq ($(CONFIG_PM_GOVERNOR_ACTIVITY),y) CSRCS += activity_governor.c diff --git a/drivers/power/pm/activity_governor.c b/drivers/power/pm/activity_governor.c index 64b8eb0fd18ee..c3fbf0cb4d523 100644 --- a/drivers/power/pm/activity_governor.c +++ b/drivers/power/pm/activity_governor.c @@ -141,7 +141,7 @@ static void governor_initialize(void); static void governor_statechanged(int domain, enum pm_state_e newstate); static enum pm_state_e governor_checkstate(int domain); static void governor_activity(int domain, int count); -static void governor_timer(int domain); +static void governor_timer(int domain, enum pm_state_e newstate); static void governor_update(int domain, int16_t accum); /**************************************************************************** @@ -526,7 +526,7 @@ static void governor_statechanged(int domain, enum pm_state_e newstate) { /* Start PM timer to decrease PM state */ - governor_timer(domain); + governor_timer(domain, newstate); } } @@ -543,18 +543,18 @@ static void governor_timer_cb(wdparm_t arg) * state level. * * Input Parameters: - * domain - The PM domain associated with the accumulator + * domain - The PM domain associated with the accumulator + * newstate - The PM domain newstate * * Returned Value: * None. * ****************************************************************************/ -static void governor_timer(int domain) +static void governor_timer(int domain, enum pm_state_e newstate) { FAR struct pm_domain_state_s *pdomstate; FAR struct pm_domain_s *pdom; - uint8_t state; static const int pmtick[3] = { @@ -565,11 +565,10 @@ static void governor_timer(int domain) pdom = &g_pmglobals.domain[domain]; pdomstate = &g_pm_activity_governor.domain_states[domain]; - state = pdom->state; - if (state < PM_SLEEP && dq_empty(&pdom->wakelock[state])) + if (newstate < PM_SLEEP && dq_empty(&pdom->wakelock[newstate])) { - sclock_t delay = pmtick[state] + + sclock_t delay = pmtick[newstate] + pdomstate->btime - clock_systime_ticks(); sclock_t left = wd_gettime(&pdomstate->wdog); diff --git a/drivers/power/pm/pm.h b/drivers/power/pm/pm.h index 6cff511cabfc7..b934e653b1f62 100644 --- a/drivers/power/pm/pm.h +++ b/drivers/power/pm/pm.h @@ -62,6 +62,10 @@ struct pm_domain_s struct timespec start; struct timespec wake[PM_COUNT]; struct timespec sleep[PM_COUNT]; + + /* When procfs read update wake or sleep up-to-now */ + + bool in_sleep; #endif /* Auto update or not */ diff --git a/drivers/power/pm/pm_autoupdate.c b/drivers/power/pm/pm_autoupdate.c index 5b8e9e02774c6..d36a90f021b3c 100644 --- a/drivers/power/pm/pm_autoupdate.c +++ b/drivers/power/pm/pm_autoupdate.c @@ -40,7 +40,7 @@ static void pm_auto_updatestate_cb(FAR void *arg) { - int domain = (uintptr_t)arg; + int domain = (intptr_t)arg; enum pm_state_e newstate; irqstate_t flags; @@ -81,12 +81,13 @@ void pm_auto_updatestate(int domain) if (up_interrupt_context()) { work_queue(HPWORK, &pdom->update_work, - pm_auto_updatestate_cb, (FAR void *)domain, 0); + pm_auto_updatestate_cb, + (FAR void *)(intptr_t)domain, 0); } else #endif { - pm_auto_updatestate_cb((FAR void *)domain); + pm_auto_updatestate_cb((FAR void *)(intptr_t)domain); } } } diff --git a/drivers/power/pm/pm_changestate.c b/drivers/power/pm/pm_changestate.c index 412edf43f1fbb..677350807338c 100644 --- a/drivers/power/pm/pm_changestate.c +++ b/drivers/power/pm/pm_changestate.c @@ -39,6 +39,96 @@ * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: pm_stats + * + * Description: + * Statistic when domain on state change events. + * + * Input Parameters: + * dom - Identifies the target domain for Statistic + * curstate - Identifies the current PM state + * newstate - Identifies the new PM state + * + * Returned Value: + * None. + * + ****************************************************************************/ +#ifdef CONFIG_PM_PROCFS +static void pm_stats(FAR struct pm_domain_s *dom, int curstate, int newstate) +{ + struct timespec now; + struct timespec ts; + + clock_systime_timespec(&now); + ts = now; + clock_timespec_subtract(&ts, &dom->start, &ts); + + /* Update start */ + + dom->start = now; + + if (newstate == PM_RESTORE) + { + /* Wakeup from WFI */ + + clock_timespec_add(&ts, &dom->sleep[curstate], &dom->sleep[curstate]); + dom->in_sleep = false; + } + else + { + /* Sleep to WFI */ + + clock_timespec_add(&ts, &dom->wake[curstate], &dom->wake[curstate]); + dom->in_sleep = true; + } +} + +/**************************************************************************** + * Name: pm_stats_preparefail + * + * Description: + * Statistic the domain on drivers prepare failed. + * + * Input Parameters: + * domain - Identifies the target domain for Statistic + * callback - The prepare failed callback + * newstate - The target new state to prepare + * ret - The driver prepare failed returned value + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void pm_stats_preparefail(int domain, + FAR struct pm_callback_s *callback, + int newstate, int ret) +{ + struct timespec ts; + FAR struct pm_preparefail_s *pf = &callback->preparefail[domain]; + + if (pf->state != PM_RESTORE) + { + clock_systime_timespec(&ts); + clock_timespec_subtract(&ts, &pf->start, &ts); + clock_timespec_add(&ts, &pf->duration[pf->state], + &pf->duration[pf->state]); + pf->state = PM_RESTORE; + } + + if (ret < 0) + { + clock_systime_timespec(&pf->start); + pf->state = newstate; + } +} + +#else +# define pm_stats(dom, curstate, newstate) +# define pm_stats_preparefail(domain, callback, newstate, ret) +#endif + /**************************************************************************** * Name: pm_prepall * @@ -48,6 +138,7 @@ * Input Parameters: * domain - Identifies the domain of the new PM state * newstate - Identifies the new PM state + * restore - Indicate currently in revert the preceding prepare stage. * * Returned Value: * 0 (OK) means that the callback function for all registered drivers @@ -60,7 +151,7 @@ * ****************************************************************************/ -static int pm_prepall(int domain, enum pm_state_e newstate) +static int pm_prepall(int domain, enum pm_state_e newstate, bool restore) { FAR dq_entry_t *entry; int ret = OK; @@ -81,6 +172,10 @@ static int pm_prepall(int domain, enum pm_state_e newstate) /* Yes.. prepare the driver */ ret = cb->prepare(cb, domain, newstate); + if (!restore) + { + pm_stats_preparefail(domain, cb, newstate, ret); + } } } } @@ -100,6 +195,10 @@ static int pm_prepall(int domain, enum pm_state_e newstate) /* Yes.. prepare the driver */ ret = cb->prepare(cb, domain, newstate); + if (!restore) + { + pm_stats_preparefail(domain, cb, newstate, ret); + } } } } @@ -168,35 +267,6 @@ static inline void pm_changeall(int domain, enum pm_state_e newstate) } } -#ifdef CONFIG_PM_PROCFS -static void pm_stats(FAR struct pm_domain_s *dom, int curstate, int newstate) -{ - struct timespec ts; - - clock_systime_timespec(&ts); - clock_timespec_subtract(&ts, &dom->start, &ts); - - if (newstate == PM_RESTORE) - { - /* Wakeup from WFI */ - - clock_timespec_add(&ts, &dom->sleep[curstate], &dom->sleep[curstate]); - } - else - { - /* Sleep to WFI */ - - clock_timespec_add(&ts, &dom->wake[curstate], &dom->wake[curstate]); - } - - /* Update start */ - - clock_systime_timespec(&dom->start); -} -#else -# define pm_stats(dom, curstate, newstate) -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -250,7 +320,7 @@ int pm_changestate(int domain, enum pm_state_e newstate) * drivers may refuse the state state change. */ - ret = pm_prepall(domain, newstate); + ret = pm_prepall(domain, newstate, false); if (ret != OK) { /* One or more drivers is not ready for this state change. @@ -258,7 +328,7 @@ int pm_changestate(int domain, enum pm_state_e newstate) */ newstate = g_pmglobals.domain[domain].state; - pm_prepall(domain, newstate); + pm_prepall(domain, newstate, true); } } @@ -272,10 +342,6 @@ int pm_changestate(int domain, enum pm_state_e newstate) */ pm_changeall(domain, newstate); - if (newstate != PM_RESTORE) - { - g_pmglobals.domain[domain].state = newstate; - } /* Notify governor of (possible) state change */ @@ -284,6 +350,13 @@ int pm_changestate(int domain, enum pm_state_e newstate) g_pmglobals.domain[domain].governor->statechanged(domain, newstate); } + /* Domain state update after statechanged done */ + + if (newstate != PM_RESTORE) + { + g_pmglobals.domain[domain].state = newstate; + } + /* Restore the interrupt state */ pm_domain_unlock(domain, flags); diff --git a/drivers/power/pm/pm_initialize.c b/drivers/power/pm/pm_initialize.c index 2149de1ba4051..38488bc820bf7 100644 --- a/drivers/power/pm/pm_initialize.c +++ b/drivers/power/pm/pm_initialize.c @@ -89,12 +89,18 @@ void pm_initialize(void) gov = pm_greedy_governor_initialize(); #elif defined(CONFIG_PM_GOVERNOR_ACTIVITY) gov = pm_activity_governor_initialize(); +#elif defined(CONFIG_PM_GOVERNOR_STABILITY) + gov = pm_stability_governor_initialize(); #else static struct pm_governor_s null; gov = &null; #endif pm_set_governor(i, gov); +#if defined(CONFIG_PM_PROCFS) + clock_systime_timespec(&g_pmglobals.domain[i].start); +#endif + nxrmutex_init(&g_pmglobals.domain[i].lock); #if CONFIG_PM_GOVERNOR_EXPLICIT_RELAX diff --git a/drivers/power/pm/pm_procfs.c b/drivers/power/pm/pm_procfs.c index 61760fb62c75f..5aea817018030 100644 --- a/drivers/power/pm/pm_procfs.c +++ b/drivers/power/pm/pm_procfs.c @@ -44,17 +44,22 @@ * Pre-processor Definitions ****************************************************************************/ -#define STHDR "DOMAIN%d WAKE SLEEP TOTAL\n" -#define WAHDR "DOMAIN%d STATE COUNT TIME\n" +#define STHDR "DOMAIN%-2d WAKE SLEEP TOTAL\n" +#define PFHDR "CALLBACKS IDLE STANDBY SLEEP\n" +#define WAHDR "DOMAIN%-2d STATE COUNT TIME\n" #ifdef CONFIG_SYSTEM_TIME64 -# define STFMT "%-8s %8" PRIu64 "s %02" PRIu64 "%% %8" PRIu64 "s %02" \ - PRIu64 "%% %8" PRIu64 "s %02" PRIu64 "%%\n" -# define WAFMT "%-12s %-10s %4" PRIu32 " %8" PRIu64 "s\n" +# define STFMT "%-18s %8" PRIu64 "s %3" PRIu64 "%% %8" PRIu64 "s %3" \ + PRIu64 "%% %8" PRIu64 "s %3" PRIu64 "%%\n" +# define PFFMT "%-18p %8" PRIu64 "s %3" PRIu64 "%% %8" PRIu64 "s %3" \ + PRIu64 "%% %8" PRIu64 "s %3" PRIu64 "%%\n" +# define WAFMT "%-25s %-14s %-14" PRIu32 " %" PRIu64 "s\n" #else -# define STFMT "%-8s %8" PRIu32 "s %02" PRIu32 "%% %8" PRIu32 "s %02" \ - PRIu32 "%% %8" PRIu32 "s %02" PRIu32 "%%\n" -# define WAFMT "%-12s %-10s %4" PRIu32 " %8" PRIu32 "s\n" +# define STFMT "%-18s %8" PRIu32 "s %3" PRIu32 "%% %8" PRIu32 "s %3" \ + PRIu32 "%% %8" PRIu32 "s %3" PRIu32 "%%\n" +# define PFFMT "%-18p %8" PRIu32 "s %3" PRIu32 "%% %8" PRIu32 "s %3" \ + PRIu32 "%% %8" PRIu32 "s %3" PRIu32 "%%\n" +# define WAFMT "%-25s %-14s %-14" PRIu32 " %" PRIu32 "s\n" #endif /* Determines the size of an intermediate buffer that must be large enough @@ -100,6 +105,8 @@ static ssize_t pm_read_state(FAR struct file *filep, FAR char *buffer, size_t buflen); static ssize_t pm_read_wakelock(FAR struct file *filep, FAR char *buffer, size_t buflen); +static ssize_t pm_read_preparefail(FAR struct file *filep, FAR char *buffer, + size_t buflen); static ssize_t pm_read(FAR struct file *filep, FAR char *buffer, size_t buflen); static int pm_dup(FAR const struct file *oldp, @@ -149,8 +156,9 @@ const struct procfs_operations g_pm_operations = static const struct pm_file_ops_s g_pm_files[] = { - {"state", pm_read_state}, - {"wakelock", pm_read_wakelock}, + {"state", pm_read_state}, + {"wakelock", pm_read_wakelock}, + {"preparefail", pm_read_preparefail}, }; static FAR const char *g_pm_state[PM_COUNT] = @@ -252,17 +260,27 @@ static int pm_close(FAR struct file *filep) return OK; } +/**************************************************************************** + * Name: pm_read_state + * + * Description: + * The statistic values about every domain states. + * + ****************************************************************************/ + static ssize_t pm_read_state(FAR struct file *filep, FAR char *buffer, size_t buflen) { FAR struct pm_domain_s *dom; FAR struct pm_file_s *pmfile; + time_t sleep[PM_COUNT]; + time_t wake[PM_COUNT]; irqstate_t flags; size_t totalsize = 0; size_t linesize; size_t copysize; off_t offset; - uint32_t sum = 0; + time_t sum = 0; uint32_t state; finfo("buffer=%p buflen=%d\n", buffer, (int)buflen); @@ -290,7 +308,26 @@ static ssize_t pm_read_state(FAR struct file *filep, FAR char *buffer, for (state = 0; state < PM_COUNT; state++) { - sum += dom->wake[state].tv_sec + dom->sleep[state].tv_sec; + wake[state] = dom->wake[state].tv_sec; + sleep[state] = dom->sleep[state].tv_sec; + + if (state == dom->state) + { + struct timespec ts; + + clock_systime_timespec(&ts); + clock_timespec_subtract(&ts, &dom->start, &ts); + if (dom->in_sleep) + { + sleep[state] += ts.tv_sec; + } + else + { + wake[state] += ts.tv_sec; + } + } + + sum += wake[state] + sleep[state]; } sum = sum ? sum : 1; @@ -299,14 +336,14 @@ static ssize_t pm_read_state(FAR struct file *filep, FAR char *buffer, { time_t total; - total = dom->wake[state].tv_sec + dom->sleep[state].tv_sec; + total = wake[state] + sleep[state]; linesize = snprintf(pmfile->line, PM_LINELEN, STFMT, g_pm_state[state], - dom->wake[state].tv_sec, - 100 * dom->wake[state].tv_sec / sum, - dom->sleep[state].tv_sec, - 100 * dom->sleep[state].tv_sec / sum, + wake[state], + 100 * wake[state] / sum, + sleep[state], + 100 * sleep[state] / sum, total, 100 * total / sum); buffer += copysize; @@ -398,6 +435,101 @@ static ssize_t pm_read_wakelock(FAR struct file *filep, FAR char *buffer, return totalsize; } +/**************************************************************************** + * Name: pm_read_preparefail + * + * Description: + * The statistic values about prepare callback failed. + * + ****************************************************************************/ + +static ssize_t pm_read_preparefail(FAR struct file *filep, FAR char *buffer, + size_t buflen) +{ + FAR struct pm_preparefail_s *pf; + FAR struct pm_file_s *pmfile; + FAR struct pm_callback_s *cb; + FAR struct pm_domain_s *dom; + FAR dq_entry_t *entry; + irqstate_t flags; + size_t totalsize = 0; + size_t linesize; + size_t copysize; + off_t offset; + time_t sum = 0; + uint32_t state; + + finfo("buffer=%p buflen=%d\n", buffer, (int)buflen); + + /* Recover our private data from the struct file instance */ + + pmfile = (FAR struct pm_file_s *)filep->f_priv; + dom = &g_pmglobals.domain[pmfile->domain]; + DEBUGASSERT(pmfile); + DEBUGASSERT(dom); + + /* Save the file offset and the user buffer information */ + + offset = filep->f_pos; + + /* Then list the power state */ + + linesize = snprintf(pmfile->line, PM_LINELEN, PFHDR); + copysize = procfs_memcpy(pmfile->line, linesize, buffer, + buflen, &offset); + totalsize += copysize; + + flags = pm_domain_lock(pmfile->domain); + for (entry = dq_peek(&g_pmglobals.registry); + entry; entry = dq_next(entry)) + { + cb = (FAR struct pm_callback_s *)entry; + pf = &cb->preparefail[pmfile->domain]; + for (state = 0; state < PM_COUNT; state++) + { + sum += pf->duration[state].tv_sec; + } + } + + sum = sum ? sum : 1; + for (entry = dq_peek(&g_pmglobals.registry); + entry; entry = dq_next(entry)) + { + time_t total = 0; + + cb = (FAR struct pm_callback_s *)entry; + pf = &cb->preparefail[pmfile->domain]; + for (state = 0; state < PM_COUNT; state++) + { + total += pf->duration[state].tv_sec; + } + + if (total == 0) + { + continue; + } + + linesize = snprintf(pmfile->line, PM_LINELEN, PFFMT, + cb->prepare, + pf->duration[PM_IDLE].tv_sec, + 100 * pf->duration[PM_IDLE].tv_sec / sum, + pf->duration[PM_STANDBY].tv_sec, + 100 * pf->duration[PM_STANDBY].tv_sec / sum, + pf->duration[PM_SLEEP].tv_sec, + 100 * pf->duration[PM_SLEEP].tv_sec / sum + ); + buffer += copysize; + buflen -= copysize; + copysize = procfs_memcpy(pmfile->line, linesize, buffer, + buflen, &offset); + totalsize += copysize; + } + + pm_domain_unlock(pmfile->domain, flags); + filep->f_pos += totalsize; + return totalsize; +} + /**************************************************************************** * Name: pm_read ****************************************************************************/ diff --git a/drivers/power/pm/pm_register.c b/drivers/power/pm/pm_register.c index 6a0b8e9dcb597..b671062f67383 100644 --- a/drivers/power/pm/pm_register.c +++ b/drivers/power/pm/pm_register.c @@ -64,6 +64,14 @@ int pm_register(FAR struct pm_callback_s *callbacks) flags = pm_lock(&g_pmglobals.reglock); dq_addlast(&callbacks->entry, &g_pmglobals.registry); + +#ifdef CONFIG_PM_PROCFS + for (int domain = 0; domain < CONFIG_PM_NDOMAINS; domain++) + { + callbacks->preparefail[domain].state = PM_RESTORE; + } +#endif + pm_unlock(&g_pmglobals.reglock, flags); return 0; diff --git a/drivers/power/pm/stability_governor.c b/drivers/power/pm/stability_governor.c new file mode 100644 index 0000000000000..c2fd6ff6f0850 --- /dev/null +++ b/drivers/power/pm/stability_governor.c @@ -0,0 +1,239 @@ +/**************************************************************************** + * drivers/power/pm/stability_governor.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +#include + +#include "pm.h" + +/**************************************************************************** + * Private Type Declarations + ****************************************************************************/ + +struct pm_stability_governor_domain_s +{ + /* Timer to wakeup system, delay the sleep request */ + + struct wdog_s wdog; + + /* The Idle is wakeup from the governor wdog itself */ + + bool wdog_wakeup; + + /* This state has not been maintained long enough to meet the threshold. */ + + enum pm_state_e state_pending; +}; + +struct pm_stability_governor_s +{ + struct pm_stability_governor_domain_s domain[CONFIG_PM_NDOMAINS]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* PM governor methods */ + +static void stability_governor_statechanged(int domain, + enum pm_state_e newstate); +static enum pm_state_e stability_governor_checkstate(int domain); +static void stability_governor_activity(int domain, int count); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct pm_governor_s g_stability_governor_ops = +{ + NULL, /* initialize */ + NULL, /* deinitialize */ + stability_governor_statechanged, /* statechanged */ + stability_governor_checkstate, /* checkstate */ + stability_governor_activity, /* activity */ + NULL /* priv */ +}; + +static const clock_t g_stability_governor_thresh[PM_COUNT] = +{ + 0, + CONFIG_PM_GOVERNOR_STABILITY_IDLE_THRESH, + CONFIG_PM_GOVERNOR_STABILITY_STANDBY_THRESH, + CONFIG_PM_GOVERNOR_STABILITY_SLEEP_THRESH, +}; + +static struct pm_stability_governor_s g_stability_governor; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Timer cb only to make sure system will wake from WFI */ + +static void stability_governor_timer_cb(wdparm_t arg) +{ +} + +/**************************************************************************** + * Name: stability_governor_statechanged + ****************************************************************************/ + +static void stability_governor_statechanged(int domain, + enum pm_state_e newstate) +{ + if (newstate == PM_RESTORE) + { + if (WDOG_ISACTIVE(&g_stability_governor.domain[domain].wdog)) + { + sclock_t left; + + /* The left tick from wdog, if >0 should be other irq source */ + + left = wd_gettime(&g_stability_governor.domain[domain].wdog); + if (left <= 0) + { + g_stability_governor.domain[domain].wdog_wakeup = true; + } + + /* Don't have to execute callback */ + + wd_cancel(&g_stability_governor.domain[domain].wdog); + } + } + else + { + enum pm_state_e state; + clock_t thresh; + + state = g_stability_governor.domain[domain].state_pending; + thresh = g_stability_governor_thresh[state]; + + if (thresh > 0 && state != newstate) + { + wd_start(&g_stability_governor.domain[domain].wdog, thresh, + stability_governor_timer_cb, 0); + } + } +} + +/**************************************************************************** + * Name: user_governor_checkstate + ****************************************************************************/ + +static enum pm_state_e stability_governor_checkstate(int domain) +{ + FAR struct pm_stability_governor_domain_s *gdom; + FAR struct pm_domain_s *pdom; + enum pm_state_e state_pending; + enum pm_state_e state; + irqstate_t flags; + bool wdog_wakeup; + + gdom = &g_stability_governor.domain[domain]; + pdom = &g_pmglobals.domain[domain]; + state = PM_NORMAL; + + /* We disable interrupts since pm_stay()/pm_relax() could be simultaneously + * invoked, which modifies the stay count which we are about to read + */ + + flags = pm_domain_lock(domain); + + /* Find the lowest power-level which is not locked. */ + + while (dq_empty(&pdom->wakelock[state]) && state < (PM_COUNT - 1)) + { + state++; + } + + state_pending = gdom->state_pending; + wdog_wakeup = gdom->wdog_wakeup; + gdom->state_pending = state; + gdom->wdog_wakeup = false; + + /* If pm stability check disabled state or pm stable enough, do nothing */ + + if (g_stability_governor_thresh[state] > 0 && + (!wdog_wakeup || state_pending != state)) + { + state = pdom->state; + if (g_stability_governor_thresh[state] > 0) + { + /* The domain last state can not be backward, need to holding + * to the lowest power-level with stability check disabled + */ + + for (; state > PM_NORMAL; state--) + { + if (g_stability_governor_thresh[state] == 0) + { + break; + } + } + } + } + + pm_domain_unlock(domain, flags); + + /* Return the found state */ + + return state; +} + +/**************************************************************************** + * Name: greedy_activity + ****************************************************************************/ + +static void stability_governor_activity(int domain, int count) +{ + pm_staytimeout(domain, PM_NORMAL, (count ? count : 1) * 1000); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pm_stability_governor_initialize + * + * Description: + * Register the user_governor driver as the specified device. + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise a negated errno value is + * returned to indicate the nature of the failure. + * + ****************************************************************************/ + +FAR const struct pm_governor_s *pm_stability_governor_initialize(void) +{ + return &g_stability_governor_ops; +} diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig index 07b529f3ce235..aadf3095521f7 100644 --- a/drivers/power/supply/Kconfig +++ b/drivers/power/supply/Kconfig @@ -68,7 +68,7 @@ config REGULATOR_GPIO config REGULATOR_RPMSG bool "Regulator RPMSG driver support" - depends on RPTUN + depends on RPMSG default n ---help--- The RPMSG regulator driver implements the common regulator APIs, inside which diff --git a/drivers/power/supply/regulator.c b/drivers/power/supply/regulator.c index b7781b1a25141..f95d48333a9bb 100644 --- a/drivers/power/supply/regulator.c +++ b/drivers/power/supply/regulator.c @@ -30,6 +30,7 @@ #include #include +#include #include #include #include diff --git a/drivers/rpmsg/CMakeLists.txt b/drivers/rpmsg/CMakeLists.txt new file mode 100644 index 0000000000000..02d54ca413840 --- /dev/null +++ b/drivers/rpmsg/CMakeLists.txt @@ -0,0 +1,31 @@ +# ############################################################################## +# drivers/rpmsg/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +if(CONFIG_RPMSG) + set(SRCS) + + list(APPEND SRCS rpmsg.c) + + if(CONFIG_RPMSG_PING) + list(APPEND SRCS rpmsg_ping.c) + endif() + + target_sources(drivers PRIVATE ${SRCS}) +endif() diff --git a/drivers/rpmsg/Kconfig b/drivers/rpmsg/Kconfig new file mode 100644 index 0000000000000..c96a7d5692604 --- /dev/null +++ b/drivers/rpmsg/Kconfig @@ -0,0 +1,24 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +config RPMSG + bool + default n + select OPENAMP + +if RPMSG + +config RPMSG_LOCAL_CPUNAME + string "Rpmsg Local Cpuname" + default LIBC_HOSTNAME + +config RPMSG_PING + bool "rpmsg ping support" + default n + ---help--- + This is for debugging & profiling, create ping rpmsg + channel, user can use it to get send/recv speed & latency. + +endif # RPMSG diff --git a/drivers/rpmsg/Make.defs b/drivers/rpmsg/Make.defs new file mode 100644 index 0000000000000..64595ca252342 --- /dev/null +++ b/drivers/rpmsg/Make.defs @@ -0,0 +1,34 @@ +############################################################################ +# drivers/rpmsg/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Don't build anything if there is no RPMSG support + +ifeq ($(CONFIG_RPMSG),y) + +CSRCS += rpmsg.c + +ifeq ($(CONFIG_RPMSG_PING),y) +CSRCS += rpmsg_ping.c +endif + +DEPPATH += --dep-path rpmsg +VPATH += :rpmsg + +endif diff --git a/drivers/rpmsg/rpmsg.c b/drivers/rpmsg/rpmsg.c new file mode 100644 index 0000000000000..9c0fb6c03c510 --- /dev/null +++ b/drivers/rpmsg/rpmsg.c @@ -0,0 +1,525 @@ +/**************************************************************************** + * drivers/rpmsg/rpmsg.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include "rpmsg_ping.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct rpmsg_bind_s +{ + char name[RPMSG_NAME_SIZE]; + uint32_t dest; + struct metal_list node; +}; + +struct rpmsg_cb_s +{ + FAR void *priv; + rpmsg_dev_cb_t device_created; + rpmsg_dev_cb_t device_destroy; + rpmsg_match_cb_t ns_match; + rpmsg_bind_cb_t ns_bind; + struct metal_list node; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int rpmsg_dev_ioctl(FAR struct file *filep, int cmd, + unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static METAL_DECLARE_LIST(g_rpmsg_cb); +static METAL_DECLARE_LIST(g_rpmsg); + +static rmutex_t g_rpmsg_lock = NXRMUTEX_INITIALIZER; + +static const struct file_operations g_rpmsg_dev_ops = +{ + NULL, /* open */ + NULL, /* close */ + NULL, /* read */ + NULL, /* write */ + NULL, /* seek */ + rpmsg_dev_ioctl, /* ioctl */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static inline FAR struct rpmsg_s * +rpmsg_get_by_rdev(FAR struct rpmsg_device *rdev) +{ + if (!rdev) + { + return NULL; + } + + return metal_container_of(rdev, struct rpmsg_s, rdev); +} + +static int rpmsg_dev_ioctl_(FAR struct rpmsg_s *rpmsg, int cmd, + unsigned long arg) +{ + int ret = OK; + + switch (cmd) + { + case RPMSGIOC_PANIC: + rpmsg->ops->panic(rpmsg); + break; + case RPMSGIOC_DUMP: + rpmsg->ops->dump(rpmsg); + break; +#ifdef CONFIG_RPMSG_PING + case RPMSGIOC_PING: + ret = rpmsg_ping(&rpmsg->ping, (FAR const struct rpmsg_ping_s *)arg); + break; +#endif + default: + ret = rpmsg->ops->ioctl(rpmsg, cmd, arg); + break; + } + + return ret; +} + +static int rpmsg_dev_ioctl(FAR struct file *filep, int cmd, + unsigned long arg) +{ + FAR struct rpmsg_s *rpmsg = filep->f_inode->i_private; + + return rpmsg_dev_ioctl_(rpmsg, cmd, arg); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int rpmsg_wait(FAR struct rpmsg_endpoint *ept, FAR sem_t *sem) +{ + FAR struct rpmsg_s *rpmsg; + + if (!ept || !sem) + { + return -EINVAL; + } + + rpmsg = rpmsg_get_by_rdev(ept->rdev); + if (!rpmsg || !rpmsg->ops->wait) + { + return nxsem_wait_uninterruptible(sem); + } + + return rpmsg->ops->wait(rpmsg, sem); +} + +int rpmsg_post(FAR struct rpmsg_endpoint *ept, FAR sem_t *sem) +{ + FAR struct rpmsg_s *rpmsg; + + if (!ept || !sem) + { + return -EINVAL; + } + + rpmsg = rpmsg_get_by_rdev(ept->rdev); + if (!rpmsg || !rpmsg->ops->post) + { + return nxsem_post(sem); + } + + return rpmsg->ops->post(rpmsg, sem); +} + +FAR const char *rpmsg_get_cpuname(FAR struct rpmsg_device *rdev) +{ + FAR struct rpmsg_s *rpmsg = rpmsg_get_by_rdev(rdev); + + if (!rpmsg) + { + return NULL; + } + + return rpmsg->ops->get_cpuname(rpmsg); +} + +int rpmsg_get_tx_buffer_size(FAR struct rpmsg_device *rdev) +{ + FAR struct rpmsg_s *rpmsg = rpmsg_get_by_rdev(rdev); + + if (!rpmsg) + { + return -EINVAL; + } + + return rpmsg->ops->get_tx_buffer_size(rpmsg); +} + +int rpmsg_get_rx_buffer_size(FAR struct rpmsg_device *rdev) +{ + FAR struct rpmsg_s *rpmsg = rpmsg_get_by_rdev(rdev); + + if (!rpmsg) + { + return -EINVAL; + } + + return rpmsg->ops->get_rx_buffer_size(rpmsg); +} + +int rpmsg_register_callback(FAR void *priv, + rpmsg_dev_cb_t device_created, + rpmsg_dev_cb_t device_destroy, + rpmsg_match_cb_t ns_match, + rpmsg_bind_cb_t ns_bind) +{ + FAR struct metal_list *node; + FAR struct metal_list *bnode; + FAR struct rpmsg_cb_s *cb; + FAR struct rpmsg_s *rpmsg; + + cb = kmm_zalloc(sizeof(struct rpmsg_cb_s)); + if (!cb) + { + return -ENOMEM; + } + + cb->priv = priv; + cb->device_created = device_created; + cb->device_destroy = device_destroy; + cb->ns_match = ns_match; + cb->ns_bind = ns_bind; + + nxrmutex_lock(&g_rpmsg_lock); + + metal_list_for_each(&g_rpmsg, node) + { + rpmsg = metal_container_of(node, struct rpmsg_s, node); + if (!rpmsg->rdev->ns_unbind_cb) + { + continue; + } + + if (device_created) + { + device_created(rpmsg->rdev, priv); + } + + if (ns_bind == NULL) + { + continue; + } + + DEBUGASSERT(ns_match != NULL); +again: + + nxrmutex_lock(&rpmsg->lock); + + metal_list_for_each(&rpmsg->bind, bnode) + { + FAR struct rpmsg_bind_s *bind; + + bind = metal_container_of(bnode, struct rpmsg_bind_s, node); + if (ns_match(rpmsg->rdev, priv, bind->name, bind->dest)) + { + metal_list_del(bnode); + nxrmutex_unlock(&rpmsg->lock); + ns_bind(rpmsg->rdev, priv, bind->name, bind->dest); + + kmm_free(bind); + goto again; + } + } + + nxrmutex_unlock(&rpmsg->lock); + } + + metal_list_add_tail(&g_rpmsg_cb, &cb->node); + nxrmutex_unlock(&g_rpmsg_lock); + + return 0; +} + +void rpmsg_unregister_callback(FAR void *priv, + rpmsg_dev_cb_t device_created, + rpmsg_dev_cb_t device_destroy, + rpmsg_match_cb_t ns_match, + rpmsg_bind_cb_t ns_bind) +{ + FAR struct metal_list *node; + FAR struct metal_list *pnode; + + nxrmutex_lock(&g_rpmsg_lock); + + metal_list_for_each(&g_rpmsg_cb, node) + { + FAR struct rpmsg_cb_s *cb = NULL; + + cb = metal_container_of(node, struct rpmsg_cb_s, node); + if (cb->priv == priv && + cb->device_created == device_created && + cb->device_destroy == device_destroy && + cb->ns_match == ns_match && + cb->ns_bind == ns_bind) + { + metal_list_del(&cb->node); + kmm_free(cb); + + break; + } + } + + if (device_destroy) + { + metal_list_for_each(&g_rpmsg, pnode) + { + FAR struct rpmsg_s *rpmsg; + + rpmsg = metal_container_of(pnode, struct rpmsg_s, node); + if (rpmsg->rdev->ns_unbind_cb) + { + device_destroy(rpmsg->rdev, priv); + } + } + } + + nxrmutex_unlock(&g_rpmsg_lock); +} + +void rpmsg_ns_bind(FAR struct rpmsg_device *rdev, + FAR const char *name, uint32_t dest) +{ + FAR struct rpmsg_s *rpmsg = rpmsg_get_by_rdev(rdev); + FAR struct rpmsg_bind_s *bind; + FAR struct metal_list *node; + + nxrmutex_lock(&g_rpmsg_lock); + + metal_list_for_each(&g_rpmsg_cb, node) + { + FAR struct rpmsg_cb_s *cb; + + cb = metal_container_of(node, struct rpmsg_cb_s, node); + if (cb->ns_match && cb->ns_match(rdev, cb->priv, name, dest)) + { + rpmsg_bind_cb_t ns_bind = cb->ns_bind; + FAR void *cb_priv = cb->priv; + + nxrmutex_unlock(&g_rpmsg_lock); + DEBUGASSERT(ns_bind != NULL); + ns_bind(rdev, cb_priv, name, dest); + + return; + } + } + + nxrmutex_unlock(&g_rpmsg_lock); + + bind = kmm_malloc(sizeof(struct rpmsg_bind_s)); + if (bind == NULL) + { + return; + } + + bind->dest = dest; + strlcpy(bind->name, name, RPMSG_NAME_SIZE); + + nxrmutex_lock(&rpmsg->lock); + metal_list_add_tail(&rpmsg->bind, &bind->node); + nxrmutex_unlock(&rpmsg->lock); +} + +void rpmsg_ns_unbind(FAR struct rpmsg_device *rdev, + FAR const char *name, uint32_t dest) +{ + FAR struct rpmsg_s *rpmsg = rpmsg_get_by_rdev(rdev); + FAR struct metal_list *node; + + nxrmutex_lock(&rpmsg->lock); + + metal_list_for_each(&rpmsg->bind, node) + { + FAR struct rpmsg_bind_s *bind; + + bind = metal_container_of(node, struct rpmsg_bind_s, node); + + if (bind->dest == dest && !strncmp(bind->name, name, RPMSG_NAME_SIZE)) + { + metal_list_del(node); + kmm_free(bind); + break; + } + } + + nxrmutex_unlock(&rpmsg->lock); +} + +void rpmsg_device_created(FAR struct rpmsg_s *rpmsg) +{ + FAR struct rpmsg_cb_s *cb; + FAR struct metal_list *node; + + nxrmutex_lock(&g_rpmsg_lock); + + metal_list_for_each(&g_rpmsg_cb, node) + { + cb = metal_container_of(node, struct rpmsg_cb_s, node); + if (cb->device_created) + { + cb->device_created(rpmsg->rdev, cb->priv); + } + } + + nxrmutex_unlock(&g_rpmsg_lock); + +#ifdef CONFIG_RPMSG_PING + rpmsg_ping_init(rpmsg->rdev, &rpmsg->ping); +#endif +} + +void rpmsg_device_destory(FAR struct rpmsg_s *rpmsg) +{ + FAR struct rpmsg_cb_s *cb; + FAR struct metal_list *node; + FAR struct metal_list *tmp; + +#ifdef CONFIG_RPMSG_PING + rpmsg_ping_deinit(&rpmsg->ping); +#endif + + nxrmutex_lock(&rpmsg->lock); + + metal_list_for_each_safe(&rpmsg->bind, node, tmp) + { + FAR struct rpmsg_bind_s *bind; + + bind = metal_container_of(node, struct rpmsg_bind_s, node); + metal_list_del(node); + kmm_free(bind); + } + + nxrmutex_unlock(&rpmsg->lock); + + nxrmutex_lock(&g_rpmsg_lock); + + /* Broadcast device_destroy to all registers */ + + metal_list_for_each(&g_rpmsg_cb, node) + { + cb = metal_container_of(node, struct rpmsg_cb_s, node); + if (cb->device_destroy) + { + cb->device_destroy(rpmsg->rdev, cb->priv); + } + } + + nxrmutex_unlock(&g_rpmsg_lock); +} + +int rpmsg_register(FAR const char *path, FAR struct rpmsg_s *rpmsg, + FAR const struct rpmsg_ops_s *ops) +{ + int ret; + + ret = register_driver(path, &g_rpmsg_dev_ops, 0222, rpmsg); + if (ret < 0) + { + return ret; + } + + metal_list_init(&rpmsg->bind); + nxrmutex_init(&rpmsg->lock); + rpmsg->ops = ops; + + /* Add priv to list */ + + nxrmutex_lock(&g_rpmsg_lock); + metal_list_add_tail(&g_rpmsg, &rpmsg->node); + nxrmutex_unlock(&g_rpmsg_lock); + + return ret; +} + +void rpmsg_unregister(FAR const char *path, FAR struct rpmsg_s *rpmsg) +{ + nxrmutex_lock(&g_rpmsg_lock); + metal_list_del(&rpmsg->node); + nxrmutex_unlock(&g_rpmsg_lock); + + nxrmutex_destroy(&rpmsg->lock); + + unregister_driver(path); +} + +int rpmsg_ioctl(FAR const char *cpuname, int cmd, unsigned long arg) +{ + FAR struct metal_list *node; + int ret = OK; + + nxrmutex_lock(&g_rpmsg_lock); + + metal_list_for_each(&g_rpmsg, node) + { + FAR struct rpmsg_s *rpmsg; + + rpmsg = metal_container_of(node, struct rpmsg_s, node); + + if (!cpuname || !strcmp(rpmsg_get_cpuname(rpmsg->rdev), cpuname)) + { + ret = rpmsg_dev_ioctl_(rpmsg, cmd, arg); + if (ret < 0) + { + break; + } + } + } + + nxrmutex_unlock(&g_rpmsg_lock); + return ret; +} + +int rpmsg_panic(FAR const char *cpuname) +{ + return rpmsg_ioctl(cpuname, RPMSGIOC_PANIC, 0); +} + +void rpmsg_dump_all(void) +{ + rpmsg_ioctl(NULL, RPMSGIOC_DUMP, 0); +} diff --git a/drivers/rpmsg/rpmsg_ping.c b/drivers/rpmsg/rpmsg_ping.c new file mode 100644 index 0000000000000..883392a4a2fea --- /dev/null +++ b/drivers/rpmsg/rpmsg_ping.c @@ -0,0 +1,242 @@ +/**************************************************************************** + * drivers/rpmsg/rpmsg_ping.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "rpmsg_ping.h" + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +#define RPMSG_PING_EPT_NAME "rpmsg-ping" +#define RPMSG_PING_SEND 1 +#define RPMSG_PING_SEND_CHECK 2 +#define RPMSG_PING_SEND_NOACK 3 +#define RPMSG_PING_ACK 4 +#define RPMSG_PING_CHECK_DATA 0xee + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +begin_packed_struct struct rpmsg_ping_msg_s +{ + uint32_t cmd; + uint32_t len; + uint64_t cookie; + uint8_t data[1]; +} end_packed_struct; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int rpmsg_ping_ept_cb(FAR struct rpmsg_endpoint *ept, + FAR void *data, size_t len, uint32_t src, + FAR void *priv) +{ + FAR struct rpmsg_ping_msg_s *msg = data; + FAR sem_t *sem = (FAR sem_t *)(uintptr_t)msg->cookie; + + if (msg->cmd == RPMSG_PING_SEND) + { + msg->cmd = RPMSG_PING_ACK; + rpmsg_send(ept, msg, len); + } + else if (msg->cmd == RPMSG_PING_SEND_CHECK) + { + size_t data_len; + size_t i; + + data_len = msg->len - sizeof(struct rpmsg_ping_msg_s) + 1; + for (i = 0; i < data_len; i++) + { + if (msg->data[i] != RPMSG_PING_CHECK_DATA) + { + syslog(LOG_ERR, "rptun ping remote receive data error!\n"); + break; + } + + msg->data[i] = 0; + } + + msg->cmd = RPMSG_PING_ACK; + rpmsg_send(ept, msg, len); + } + else if (msg->cmd == RPMSG_PING_ACK) + { + nxsem_post(sem); + } + + return 0; +} + +static int rpmsg_ping_once(FAR struct rpmsg_endpoint *ept, + int len, int ack, uint32_t *buf_len) +{ + FAR struct rpmsg_ping_msg_s *msg; + int ret; + + msg = rpmsg_get_tx_payload_buffer(ept, buf_len, true); + if (!msg) + { + return -ENOMEM; + } + + len = MAX(len, sizeof(struct rpmsg_ping_msg_s)); + len = MIN(len, *buf_len); + + memset(msg, 0, len); + + if (ack) + { + sem_t sem; + + msg->cmd = (ack == 1)? RPMSG_PING_SEND : RPMSG_PING_SEND_CHECK; + msg->len = len; + msg->cookie = (uintptr_t)&sem; + + if (msg->cmd == RPMSG_PING_SEND_CHECK) + { + memset(msg->data, RPMSG_PING_CHECK_DATA, + len - sizeof(struct rpmsg_ping_msg_s) + 1); + } + + nxsem_init(&sem, 0, 0); + + ret = rpmsg_send_nocopy(ept, msg, len); + if (ret >= 0) + { + nxsem_wait_uninterruptible(&sem); + } + + nxsem_destroy(&sem); + } + else + { + msg->cmd = RPMSG_PING_SEND_NOACK; + msg->len = len; + ret = rpmsg_send_nocopy(ept, msg, len); + } + + return ret; +} + +static void rpmsg_ping_logout(FAR const char *s, clock_t value) +{ + struct timespec ts; + + perf_convert(value, &ts); + +#ifdef CONFIG_SYSTEM_TIME64 + syslog(LOG_INFO, "%s: %" PRIu64 " s, %ld ns\n", s, ts.tv_sec, ts.tv_nsec); +#else + syslog(LOG_INFO, "%s: %" PRIu32 " s, %ld ns\n", s, ts.tv_sec, ts.tv_nsec); +#endif +} + +static void rpmsg_ping_logout_rate(uint64_t len, clock_t avg) +{ + struct timespec ts; + size_t ratebits; + size_t rateint; + size_t ratedec; + + perf_convert(avg, &ts); + + ratebits = len * 8 * 1000000000 / (ts.tv_sec * NSEC_PER_SEC + ts.tv_nsec); + rateint = ratebits / 1000000; + ratedec = ratebits - rateint * 1000000; + + syslog(LOG_INFO, "rate: %zu.%06zu Mbits/sec\n", rateint, ratedec); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int rpmsg_ping(FAR struct rpmsg_endpoint *ept, + FAR const struct rpmsg_ping_s *ping) +{ + clock_t min = CLOCK_MAX; + clock_t max = 0; + uint64_t total = 0; + uint32_t buf_len = 0; + int send_len = 0; + int i; + + if (!ept || !ping || ping->times <= 0) + { + return -EINVAL; + } + + for (i = 0; i < ping->times; i++) + { + clock_t tm = perf_gettime(); + + send_len = rpmsg_ping_once(ept, ping->len, ping->ack, &buf_len); + if (send_len < 0) + { + return send_len; + } + + tm = perf_gettime() - tm; + min = MIN(min, tm); + max = MAX(max, tm); + total += tm; + + nxsig_usleep(ping->sleep * USEC_PER_MSEC); + } + + syslog(LOG_INFO, "ping times: %d\n", ping->times); + + rpmsg_ping_logout("avg", total / ping->times); + rpmsg_ping_logout("min", min); + rpmsg_ping_logout("max", max); + rpmsg_ping_logout_rate(send_len, total / ping->times); + + return 0; +} + +int rpmsg_ping_init(FAR struct rpmsg_device *rdev, + FAR struct rpmsg_endpoint *ept) +{ + return rpmsg_create_ept(ept, rdev, RPMSG_PING_EPT_NAME, + RPMSG_ADDR_ANY, RPMSG_ADDR_ANY, + rpmsg_ping_ept_cb, NULL); +} + +void rpmsg_ping_deinit(FAR struct rpmsg_endpoint *ept) +{ + rpmsg_destroy_ept(ept); +} diff --git a/drivers/rpmsg/rpmsg_ping.h b/drivers/rpmsg/rpmsg_ping.h new file mode 100644 index 0000000000000..dc85939142cc5 --- /dev/null +++ b/drivers/rpmsg/rpmsg_ping.h @@ -0,0 +1,43 @@ +/**************************************************************************** + * drivers/rpmsg/rpmsg_ping.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __DRIVERS_RPMSG_RPMSG_PING_H +#define __DRIVERS_RPMSG_RPMSG_PING_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_RPMSG_PING + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +int rpmsg_ping_init(FAR struct rpmsg_device *rdev, + FAR struct rpmsg_endpoint *ept); +void rpmsg_ping_deinit(FAR struct rpmsg_endpoint *ept); +int rpmsg_ping(FAR struct rpmsg_endpoint *ept, + FAR const struct rpmsg_ping_s *ping); + +#endif /* CONFIG_RPMSG_PING */ +#endif /* __DRIVERS_RPMSG_RPMSG_PING_H */ diff --git a/drivers/rptun/CMakeLists.txt b/drivers/rptun/CMakeLists.txt index e4b81d83f989b..a3375d79d42de 100644 --- a/drivers/rptun/CMakeLists.txt +++ b/drivers/rptun/CMakeLists.txt @@ -20,11 +20,7 @@ if(CONFIG_RPTUN) set(SRCS) - list(APPEND SRCS rptun.c rptun_dump.c) - - if(CONFIG_RPTUN_PING) - list(APPEND SRCS rptun_ping.c) - endif() + list(APPEND SRCS rptun.c) target_include_directories(drivers PRIVATE ${NUTTX_DIR}/openamp/open-amp/lib) target_sources(drivers PRIVATE ${SRCS}) diff --git a/drivers/rptun/Kconfig b/drivers/rptun/Kconfig index add132c8f3b55..ae65529417881 100644 --- a/drivers/rptun/Kconfig +++ b/drivers/rptun/Kconfig @@ -6,42 +6,24 @@ menuconfig RPTUN bool "Remote Proc Tunnel Driver Support" default n - depends on OPENAMP + select RPMSG ---help--- RPTUN driver is used for multi-cores' communication. if RPTUN -choice - prompt "rptun dispatch method" - -config RPTUN_THREAD - bool "rptun thread" - -config RPTUN_WORKQUEUE - bool "rptun workqueue" - depends on SCHED_WORKQUEUE - -endchoice - config RPTUN_PRIORITY int "rptun thread priority" - depends on RPTUN_THREAD default 224 config RPTUN_STACKSIZE int "rptun stack size" - depends on RPTUN_THREAD default 4096 config RPTUN_LOADER bool "rptun loader support" default n -config RPTUN_LOCAL_CPUNAME - string "rptun local cpuname" - default LIBC_HOSTNAME - config RPTUN_PM bool "rptun power management" depends on PM @@ -52,11 +34,4 @@ config RPTUN_PM goto RAM-retention mode, can't access from another CPU. So, we provide this method to resolve this. -config RPTUN_PING - bool "rptun ping support" - default n - ---help--- - This is for rptun debugging & profiling, create ping RPMSG - channel, user can use it to get send/recv speed & latency. - endif # RPTUN diff --git a/drivers/rptun/Make.defs b/drivers/rptun/Make.defs index a3fcfdbb2f02e..029eb034d43ea 100644 --- a/drivers/rptun/Make.defs +++ b/drivers/rptun/Make.defs @@ -22,11 +22,7 @@ ifeq ($(CONFIG_RPTUN),y) -CSRCS += rptun.c rptun_dump.c - -ifeq ($(CONFIG_RPTUN_PING),y) -CSRCS += rptun_ping.c -endif +CSRCS += rptun.c DEPPATH += --dep-path rptun VPATH += :rptun diff --git a/drivers/rptun/rptun.c b/drivers/rptun/rptun.c index ad1943caff311..2ca3b601f8aa5 100644 --- a/drivers/rptun/rptun.c +++ b/drivers/rptun/rptun.c @@ -35,14 +35,14 @@ #include #include #include -#include -#include -#include #include +#include +#include #include #include - -#include "rptun.h" +#include +#include +#include /**************************************************************************** * Pre-processor Definitions @@ -60,43 +60,17 @@ struct rptun_priv_s { + struct rpmsg_s rpmsg; + struct rpmsg_virtio_device rvdev; FAR struct rptun_dev_s *dev; struct remoteproc rproc; - struct rpmsg_virtio_device rvdev; struct rpmsg_virtio_shm_pool pool[2]; - struct metal_list bind; - rmutex_t lock; - struct metal_list node; sem_t semtx; -#ifdef CONFIG_RPTUN_WORKQUEUE - struct work_s work; -#else sem_t semrx; pid_t tid; -#endif #ifdef CONFIG_RPTUN_PM bool stay; #endif -#ifdef CONFIG_RPTUN_PING - struct rpmsg_endpoint ping; -#endif -}; - -struct rptun_bind_s -{ - char name[RPMSG_NAME_SIZE]; - uint32_t dest; - struct metal_list node; -}; - -struct rptun_cb_s -{ - FAR void *priv; - rpmsg_dev_cb_t device_created; - rpmsg_dev_cb_t device_destroy; - rpmsg_match_cb_t ns_match; - rpmsg_bind_cb_t ns_bind; - struct metal_list node; }; struct rptun_store_s @@ -126,13 +100,8 @@ rptun_get_mem(FAR struct remoteproc *rproc, FAR struct remoteproc_mem *buf); static int rptun_notify_wait(FAR struct remoteproc *rproc, uint32_t id); -static void rptun_ns_bind(FAR struct rpmsg_device *rdev, - FAR const char *name, uint32_t dest); - static int rptun_dev_start(FAR struct remoteproc *rproc); static int rptun_dev_stop(FAR struct remoteproc *rproc, bool stop_ns); -static int rptun_dev_ioctl(FAR struct file *filep, int cmd, - unsigned long arg); #ifdef CONFIG_RPTUN_LOADER static int rptun_store_open(FAR void *store_, FAR const char *path, @@ -150,6 +119,16 @@ static metal_phys_addr_t rptun_pa_to_da(FAR struct rptun_dev_s *dev, static metal_phys_addr_t rptun_da_to_pa(FAR struct rptun_dev_s *dev, metal_phys_addr_t da); +static int rptun_wait(FAR struct rpmsg_s *rpmsg, FAR sem_t *sem); +static int rptun_post(FAR struct rpmsg_s *rpmsg, FAR sem_t *sem); +static int rptun_ioctl(FAR struct rpmsg_s *rpmsg, int cmd, + unsigned long arg); +static void rptun_panic_(FAR struct rpmsg_s *rpmsg); +static void rptun_dump(FAR struct rpmsg_s *rpmsg); +static FAR const char *rptun_get_cpuname(FAR struct rpmsg_s *rpmsg); +static int rptun_get_tx_buffer_size(FAR struct rpmsg_s *rpmsg); +static int rptun_get_rx_buffer_size(FAR struct rpmsg_s *rpmsg); + /**************************************************************************** * Private Data ****************************************************************************/ @@ -166,18 +145,8 @@ static const struct remoteproc_ops g_rptun_ops = .notify_wait = rptun_notify_wait, }; -static const struct file_operations g_rptun_devops = -{ - NULL, /* open */ - NULL, /* close */ - NULL, /* read */ - NULL, /* write */ - NULL, /* seek */ - rptun_dev_ioctl, /* ioctl */ -}; - #ifdef CONFIG_RPTUN_LOADER -static const struct image_store_ops g_rptun_storeops = +static const struct image_store_ops g_rptun_store_ops = { .open = rptun_store_open, .close = rptun_store_close, @@ -186,15 +155,48 @@ static const struct image_store_ops g_rptun_storeops = }; #endif -static METAL_DECLARE_LIST(g_rptun_cb); -static METAL_DECLARE_LIST(g_rptun_priv); - -static rmutex_t g_rptun_lockcb = NXRMUTEX_INITIALIZER; +static const struct rpmsg_ops_s g_rptun_rpmsg_ops = +{ + rptun_wait, + rptun_post, + rptun_ioctl, + rptun_panic_, + rptun_dump, + rptun_get_cpuname, + rptun_get_tx_buffer_size, + rptun_get_rx_buffer_size, +}; /**************************************************************************** * Private Functions ****************************************************************************/ +static int rptun_buffer_nused(FAR struct rpmsg_virtio_device *rvdev, bool rx) +{ + FAR struct virtqueue *vq = rx ? rvdev->rvq : rvdev->svq; + uint16_t nused = vq->vq_ring.avail->idx - vq->vq_ring.used->idx; + + if ((rpmsg_virtio_get_role(rvdev) == RPMSG_HOST) ^ rx) + { + return nused; + } + else + { + return vq->vq_nentries - nused; + } +} + +static void rptun_wakeup_tx(FAR struct rptun_priv_s *priv) +{ + int semcount; + + nxsem_get_value(&priv->semtx, &semcount); + while (semcount++ < 1) + { + nxsem_post(&priv->semtx); + } +} + #ifdef CONFIG_RPTUN_PM static inline void rptun_pm_action(FAR struct rptun_priv_s *priv, bool stay) @@ -239,25 +241,6 @@ static void rptun_worker(FAR void *arg) remoteproc_get_notification(&priv->rproc, RPTUN_NOTIFY_ALL); } -#ifdef CONFIG_RPTUN_WORKQUEUE -static void rptun_wakeup_rx(FAR struct rptun_priv_s *priv) -{ - work_queue(HPWORK, &priv->work, rptun_worker, priv, 0); -} - -static void rptun_in_recursive(int tid, FAR void *arg) -{ - *((FAR bool *)arg) = (nxsched_gettid() == tid); -} - -static bool rptun_is_recursive(FAR struct rptun_priv_s *priv) -{ - bool in = false; - work_foreach(HPWORK, rptun_in_recursive, &in); - return in; -} - -#else static int rptun_thread(int argc, FAR char *argv[]) { FAR struct rptun_priv_s *priv; @@ -294,18 +277,6 @@ static bool rptun_is_recursive(FAR struct rptun_priv_s *priv) { return nxsched_gettid() == priv->tid; } -#endif - -static void rptun_wakeup_tx(FAR struct rptun_priv_s *priv) -{ - int semcount; - - nxsem_get_value(&priv->semtx, &semcount); - while (semcount++ < 1) - { - nxsem_post(&priv->semtx); - } -} static int rptun_callback(FAR void *arg, uint32_t vqid) { @@ -457,102 +428,209 @@ static int rptun_notify_wait(FAR struct remoteproc *rproc, uint32_t id) return 0; } -static void *rptun_get_priv_by_rdev(FAR struct rpmsg_device *rdev) +static void rptun_dump_buffer(FAR struct rpmsg_virtio_device *rvdev, + bool rx) { - FAR struct rpmsg_virtio_device *rvdev; - FAR struct virtio_device *vdev; - FAR struct remoteproc_virtio *rpvdev; - FAR struct remoteproc *rproc; + FAR struct virtqueue *vq = rx ? rvdev->rvq : rvdev->svq; + FAR void *addr; + int desc_idx; + int num; + int i; - if (!rdev) + num = rptun_buffer_nused(rvdev, rx); + metal_log(METAL_LOG_EMERGENCY, + " %s buffer, total %d, pending %d\n", + rx ? "RX" : "TX", vq->vq_nentries, num); + + for (i = 0; i < num; i++) { - return NULL; + if ((rpmsg_virtio_get_role(rvdev) == RPMSG_HOST) ^ rx) + { + desc_idx = (vq->vq_ring.used->idx + i) & (vq->vq_nentries - 1); + desc_idx = vq->vq_ring.avail->ring[desc_idx]; + } + else + { + desc_idx = (vq->vq_ring.avail->idx + i) & (vq->vq_nentries - 1); + desc_idx = vq->vq_ring.used->ring[desc_idx].id; + } + + addr = metal_io_phys_to_virt(vq->shm_io, + vq->vq_ring.desc[desc_idx].addr); + if (addr) + { + FAR struct rpmsg_hdr *hdr = addr; + FAR struct rpmsg_endpoint *ept; + + ept = rpmsg_get_ept_from_addr(&rvdev->rdev, + rx ? hdr->dst : hdr->src); + if (ept) + { + metal_log(METAL_LOG_EMERGENCY, + " %s buffer %p hold by %s\n", + rx ? "RX" : "TX", hdr, ept->name); + } + } } +} - rvdev = metal_container_of(rdev, struct rpmsg_virtio_device, rdev); - vdev = rvdev->vdev; - if (!vdev) +static int rptun_wait(FAR struct rpmsg_s *rpmsg, FAR sem_t *sem) +{ + FAR struct rptun_priv_s *priv = (FAR struct rptun_priv_s *)rpmsg; + int ret; + + if (!rptun_is_recursive(priv)) { - return NULL; + return nxsem_wait_uninterruptible(sem); } - rpvdev = metal_container_of(vdev, struct remoteproc_virtio, vdev); - rproc = rpvdev->priv; - if (!rproc) + while (1) { - return NULL; + ret = nxsem_trywait(sem); + if (ret >= 0) + { + break; + } + + nxsem_wait(&priv->semtx); + rptun_worker(priv); } - return rproc->priv; + return ret; } -static void rptun_ns_bind(FAR struct rpmsg_device *rdev, - FAR const char *name, uint32_t dest) +static int rptun_post(FAR struct rpmsg_s *rpmsg, FAR sem_t *sem) { - FAR struct rptun_priv_s *priv = rptun_get_priv_by_rdev(rdev); - FAR struct rptun_bind_s *bind; - FAR struct metal_list *node; + FAR struct rptun_priv_s *priv = (FAR struct rptun_priv_s *)rpmsg; + int semcount; + int ret; - nxrmutex_lock(&g_rptun_lockcb); + nxsem_get_value(sem, &semcount); + ret = nxsem_post(sem); - metal_list_for_each(&g_rptun_cb, node) + if (priv && semcount >= 0) { - FAR struct rptun_cb_s *cb; - - cb = metal_container_of(node, struct rptun_cb_s, node); - if (cb->ns_match && cb->ns_match(rdev, cb->priv, name, dest)) - { - rpmsg_bind_cb_t ns_bind = cb->ns_bind; - FAR void *cb_priv = cb->priv; + rptun_wakeup_tx(priv); + } - nxrmutex_unlock(&g_rptun_lockcb); + return ret; +} - DEBUGASSERT(ns_bind != NULL); - ns_bind(rdev, cb_priv, name, dest); +static int rptun_ioctl(FAR struct rpmsg_s *rpmsg, int cmd, unsigned long arg) +{ + FAR struct rptun_priv_s *priv = (FAR struct rptun_priv_s *)rpmsg; + int ret = OK; - return; - } + switch (cmd) + { + case RPTUNIOC_START: + if (priv->rproc.state == RPROC_OFFLINE) + { + ret = rptun_dev_start(&priv->rproc); + } + else + { + ret = rptun_dev_stop(&priv->rproc, false); + if (ret == OK) + { + ret = rptun_dev_start(&priv->rproc); + } + } + break; + case RPTUNIOC_STOP: + ret = rptun_dev_stop(&priv->rproc, true); + break; + case RPTUNIOC_RESET: + RPTUN_RESET(priv->dev, arg); + break; + default: + ret = -ENOTTY; + break; } - nxrmutex_unlock(&g_rptun_lockcb); + return ret; +} - bind = kmm_malloc(sizeof(struct rptun_bind_s)); - if (bind == NULL) +static void rptun_panic_(FAR struct rpmsg_s *rpmsg) +{ + FAR struct rptun_priv_s *priv = (FAR struct rptun_priv_s *)rpmsg; + + RPTUN_PANIC(priv->dev); +} + +static void rptun_dump(FAR struct rpmsg_s *rpmsg) +{ + FAR struct rptun_priv_s *priv = (FAR struct rptun_priv_s *)rpmsg; + FAR struct rpmsg_virtio_device *rvdev = &priv->rvdev; + FAR struct rpmsg_device *rdev = rpmsg->rdev; + FAR struct rpmsg_endpoint *ept; + FAR struct metal_list *node; + bool needlock = true; + + if (!rvdev->vdev) { return; } - bind->dest = dest; - strlcpy(bind->name, name, RPMSG_NAME_SIZE); + if (up_interrupt_context() || sched_idletask() || + nxmutex_is_hold(&rdev->lock)) + { + needlock = false; + } - nxrmutex_lock(&priv->lock); - metal_list_add_tail(&priv->bind, &bind->node); - nxrmutex_unlock(&priv->lock); -} + if (needlock) + { + metal_mutex_acquire(&rdev->lock); + } -static void rptun_ns_unbind(FAR struct rpmsg_device *rdev, - FAR const char *name, uint32_t dest) -{ - FAR struct rptun_priv_s *priv = rptun_get_priv_by_rdev(rdev); - FAR struct metal_list *node; + metal_log(METAL_LOG_EMERGENCY, + "Dump rpmsg info between cpu (master: %s)%s <==> %s:\n", + rpmsg_virtio_get_role(rvdev) == RPMSG_HOST ? "yes" : "no", + CONFIG_RPMSG_LOCAL_CPUNAME, rpmsg_get_cpuname(rdev)); + + metal_log(METAL_LOG_EMERGENCY, "rpmsg vq RX:\n"); + virtqueue_dump(rvdev->rvq); + metal_log(METAL_LOG_EMERGENCY, "rpmsg vq TX:\n"); + virtqueue_dump(rvdev->svq); - nxrmutex_lock(&priv->lock); + metal_log(METAL_LOG_EMERGENCY, " rpmsg ept list:\n"); - metal_list_for_each(&priv->bind, node) + metal_list_for_each(&rdev->endpoints, node) { - struct rptun_bind_s *bind; + ept = metal_container_of(node, struct rpmsg_endpoint, node); + metal_log(METAL_LOG_EMERGENCY, " ept %s\n", ept->name); + } - bind = metal_container_of(node, struct rptun_bind_s, node); + metal_log(METAL_LOG_EMERGENCY, " rpmsg buffer list:\n"); - if (bind->dest == dest && !strncmp(bind->name, name, RPMSG_NAME_SIZE)) - { - metal_list_del(node); - kmm_free(bind); - break; - } + rptun_dump_buffer(rvdev, true); + rptun_dump_buffer(rvdev, false); + + if (needlock) + { + metal_mutex_release(&rdev->lock); } - nxrmutex_unlock(&priv->lock); +#ifdef CONFIG_RPTUN_PM + metal_log(METAL_LOG_EMERGENCY, "rptun headrx %d\n", priv->headrx); +#endif +} + +static FAR const char *rptun_get_cpuname(FAR struct rpmsg_s *rpmsg) +{ + FAR struct rptun_priv_s *priv = (FAR struct rptun_priv_s *)rpmsg; + + return RPTUN_GET_CPUNAME(priv->dev); +} + +static int rptun_get_tx_buffer_size(FAR struct rpmsg_s *rpmsg) +{ + return rpmsg_virtio_get_buffer_size(rpmsg->rdev); +} + +static int rptun_get_rx_buffer_size(FAR struct rpmsg_s *rpmsg) +{ + return rpmsg_virtio_get_rx_buffer_size(rpmsg->rdev); } static int rptun_dev_start(FAR struct remoteproc *rproc) @@ -560,8 +638,6 @@ static int rptun_dev_start(FAR struct remoteproc *rproc) FAR struct rptun_priv_s *priv = rproc->priv; FAR struct virtio_device *vdev; FAR struct rptun_rsc_s *rsc; - FAR struct metal_list *node; - FAR struct rptun_cb_s *cb; unsigned int role = RPMSG_REMOTE; int ret; @@ -580,7 +656,7 @@ static int rptun_dev_start(FAR struct remoteproc *rproc) }; ret = remoteproc_load(rproc, RPTUN_GET_FIRMWARE(priv->dev), - &store, &g_rptun_storeops, NULL); + &store, &g_rptun_store_ops, NULL); if (ret) { return ret; @@ -630,7 +706,10 @@ static int rptun_dev_start(FAR struct remoteproc *rproc) v0sz = ALIGN_UP(vring_size(rsc->rpmsg_vring0.num, align0), align0); v1sz = ALIGN_UP(vring_size(rsc->rpmsg_vring1.num, align1), align1); - if (rsc->rpmsg_vring0.da == 0 || rsc->rpmsg_vring1.da == 0) + if (rsc->rpmsg_vring0.da == 0 || + rsc->rpmsg_vring0.da == FW_RSC_U32_ADDR_ANY || + rsc->rpmsg_vring1.da == 0 || + rsc->rpmsg_vring1.da == FW_RSC_U32_ADDR_ANY) { tbsz = ALIGN_UP(sizeof(struct rptun_rsc_s), MAX(align0, align1)); @@ -690,14 +769,14 @@ static int rptun_dev_start(FAR struct remoteproc *rproc) true, }; - ret = rpmsg_init_vdev_with_config(&priv->rvdev, vdev, rptun_ns_bind, + ret = rpmsg_init_vdev_with_config(&priv->rvdev, vdev, rpmsg_ns_bind, metal_io_get_region(), priv->pool, &config); } else { - ret = rpmsg_init_vdev(&priv->rvdev, vdev, rptun_ns_bind, + ret = rpmsg_init_vdev(&priv->rvdev, vdev, rpmsg_ns_bind, metal_io_get_region(), priv->pool); } @@ -707,7 +786,7 @@ static int rptun_dev_start(FAR struct remoteproc *rproc) return ret; } - priv->rvdev.rdev.ns_unbind_cb = rptun_ns_unbind; + priv->rvdev.rdev.ns_unbind_cb = rpmsg_ns_unbind; /* Remote proc start */ @@ -727,24 +806,12 @@ static int rptun_dev_start(FAR struct remoteproc *rproc) /* Broadcast device_created to all registers */ - nxrmutex_lock(&g_rptun_lockcb); - - metal_list_for_each(&g_rptun_cb, node) - { - cb = metal_container_of(node, struct rptun_cb_s, node); - if (cb->device_created) - { - cb->device_created(&priv->rvdev.rdev, cb->priv); - } - } + rpmsg_device_created(&priv->rpmsg); - nxrmutex_unlock(&g_rptun_lockcb); + /* Open tx buffer return callback */ virtqueue_enable_cb(priv->rvdev.svq); -#ifdef CONFIG_RPTUN_PING - rptun_ping_init(&priv->rvdev, &priv->ping); -#endif return 0; } @@ -752,9 +819,6 @@ static int rptun_dev_stop(FAR struct remoteproc *rproc, bool stop_ns) { FAR struct rptun_priv_s *priv = rproc->priv; FAR struct rpmsg_device *rdev = &priv->rvdev.rdev; - FAR struct metal_list *node; - FAR struct metal_list *tmp; - FAR struct rptun_cb_s *cb; if (priv->rproc.state == RPROC_OFFLINE) { @@ -768,43 +832,11 @@ static int rptun_dev_stop(FAR struct remoteproc *rproc, bool stop_ns) rdev->support_ns = stop_ns; -#ifdef CONFIG_RPTUN_PING - rptun_ping_deinit(&priv->ping); -#endif - - nxrmutex_lock(&priv->lock); - - metal_list_for_each_safe(&priv->bind, node, tmp) - { - FAR struct rptun_bind_s *bind; - - bind = metal_container_of(node, struct rptun_bind_s, node); - metal_list_del(node); - kmm_free(bind); - } - - nxrmutex_unlock(&priv->lock); - /* Unregister callback from mbox */ RPTUN_UNREGISTER_CALLBACK(priv->dev); - /* Remove priv from list */ - - nxrmutex_lock(&g_rptun_lockcb); - - /* Broadcast device_destroy to all registers */ - - metal_list_for_each(&g_rptun_cb, node) - { - cb = metal_container_of(node, struct rptun_cb_s, node); - if (cb->device_destroy) - { - cb->device_destroy(&priv->rvdev.rdev, cb->priv); - } - } - - nxrmutex_unlock(&g_rptun_lockcb); + rpmsg_device_destory(&priv->rpmsg); /* Remote proc remove */ @@ -818,59 +850,6 @@ static int rptun_dev_stop(FAR struct remoteproc *rproc, bool stop_ns) return OK; } -static int rptun_do_ioctl(FAR struct rptun_priv_s *priv, int cmd, - unsigned long arg) -{ - int ret = OK; - - switch (cmd) - { - case RPTUNIOC_START: - if (priv->rproc.state == RPROC_OFFLINE) - { - ret = rptun_dev_start(&priv->rproc); - } - else - { - ret = rptun_dev_stop(&priv->rproc, false); - if (ret == OK) - { - ret = rptun_dev_start(&priv->rproc); - } - } - break; - case RPTUNIOC_STOP: - ret = rptun_dev_stop(&priv->rproc, true); - break; - case RPTUNIOC_RESET: - RPTUN_RESET(priv->dev, arg); - break; - case RPTUNIOC_PANIC: - RPTUN_PANIC(priv->dev); - break; - case RPTUNIOC_DUMP: - rptun_dump(&priv->rvdev); - break; -#ifdef CONFIG_RPTUN_PING - case RPTUNIOC_PING: - rptun_ping(&priv->ping, (FAR const struct rptun_ping_s *)arg); - break; -#endif - default: - ret = -ENOTTY; - break; - } - - return ret; -} - -static int rptun_dev_ioctl(FAR struct file *filep, int cmd, - unsigned long arg) -{ - FAR struct inode *inode = filep->f_inode; - return rptun_do_ioctl(inode->i_private, cmd, arg); -} - #ifdef CONFIG_RPTUN_LOADER static int rptun_store_open(FAR void *store_, FAR const char *path, @@ -986,224 +965,17 @@ static metal_phys_addr_t rptun_da_to_pa(FAR struct rptun_dev_s *dev, return da; } -static int rptun_ioctl_foreach(FAR const char *cpuname, int cmd, - unsigned long value) -{ - FAR struct metal_list *node; - int ret = OK; - - metal_list_for_each(&g_rptun_priv, node) - { - FAR struct rptun_priv_s *priv; - - priv = metal_container_of(node, struct rptun_priv_s, node); - - if (!cpuname || !strcmp(RPTUN_GET_CPUNAME(priv->dev), cpuname)) - { - ret = rptun_do_ioctl(priv, cmd, value); - if (ret < 0) - break; - } - } - - return ret; -} - /**************************************************************************** * Public Functions ****************************************************************************/ -int rpmsg_wait(FAR struct rpmsg_endpoint *ept, FAR sem_t *sem) -{ - FAR struct rptun_priv_s *priv; - int ret; - - if (!ept || !sem) - { - return -EINVAL; - } - - priv = rptun_get_priv_by_rdev(ept->rdev); - if (!priv || !rptun_is_recursive(priv)) - { - return nxsem_wait_uninterruptible(sem); - } - - while (1) - { - ret = nxsem_trywait(sem); - if (ret >= 0) - { - break; - } - - nxsem_wait(&priv->semtx); - rptun_worker(priv); - } - - return ret; -} - -int rpmsg_post(FAR struct rpmsg_endpoint *ept, FAR sem_t *sem) -{ - FAR struct rptun_priv_s *priv; - int semcount; - int ret; - - if (!ept || !sem) - { - return -EINVAL; - } - - nxsem_get_value(sem, &semcount); - ret = nxsem_post(sem); - - priv = rptun_get_priv_by_rdev(ept->rdev); - if (priv && semcount >= 0) - { - rptun_wakeup_tx(priv); - } - - return ret; -} - -FAR const char *rpmsg_get_cpuname(FAR struct rpmsg_device *rdev) -{ - FAR struct rptun_priv_s *priv = rptun_get_priv_by_rdev(rdev); - - return RPTUN_GET_CPUNAME(priv->dev); -} - -int rpmsg_register_callback(FAR void *priv_, - rpmsg_dev_cb_t device_created, - rpmsg_dev_cb_t device_destroy, - rpmsg_match_cb_t ns_match, - rpmsg_bind_cb_t ns_bind) -{ - FAR struct metal_list *node; - FAR struct metal_list *bnode; - FAR struct rptun_cb_s *cb; - - cb = kmm_zalloc(sizeof(struct rptun_cb_s)); - if (!cb) - { - return -ENOMEM; - } - - cb->priv = priv_; - cb->device_created = device_created; - cb->device_destroy = device_destroy; - cb->ns_match = ns_match; - cb->ns_bind = ns_bind; - - nxrmutex_lock(&g_rptun_lockcb); - - metal_list_for_each(&g_rptun_priv, node) - { - FAR struct rptun_priv_s *priv; - - priv = metal_container_of(node, struct rptun_priv_s, node); - if (priv->rproc.state != RPROC_RUNNING) - { - continue; - } - - if (device_created) - { - device_created(&priv->rvdev.rdev, priv_); - } - - if (ns_bind == NULL) - { - continue; - } - - DEBUGASSERT(ns_match != NULL); -again: - nxrmutex_lock(&priv->lock); - - metal_list_for_each(&priv->bind, bnode) - { - FAR struct rptun_bind_s *bind; - - bind = metal_container_of(bnode, struct rptun_bind_s, node); - if (ns_match(&priv->rvdev.rdev, priv_, bind->name, bind->dest)) - { - metal_list_del(bnode); - nxrmutex_unlock(&priv->lock); - - ns_bind(&priv->rvdev.rdev, priv_, bind->name, bind->dest); - kmm_free(bind); - goto again; - } - } - - nxrmutex_unlock(&priv->lock); - } - - metal_list_add_tail(&g_rptun_cb, &cb->node); - nxrmutex_unlock(&g_rptun_lockcb); - - return 0; -} - -void rpmsg_unregister_callback(FAR void *priv_, - rpmsg_dev_cb_t device_created, - rpmsg_dev_cb_t device_destroy, - rpmsg_match_cb_t ns_match, - rpmsg_bind_cb_t ns_bind) -{ - FAR struct metal_list *node; - FAR struct metal_list *pnode; - - nxrmutex_lock(&g_rptun_lockcb); - - metal_list_for_each(&g_rptun_cb, node) - { - FAR struct rptun_cb_s *cb = NULL; - - cb = metal_container_of(node, struct rptun_cb_s, node); - if (cb->priv == priv_ && - cb->device_created == device_created && - cb->device_destroy == device_destroy && - cb->ns_match == ns_match && - cb->ns_bind == ns_bind) - { - metal_list_del(&cb->node); - kmm_free(cb); - - break; - } - } - - if (device_destroy) - { - metal_list_for_each(&g_rptun_priv, pnode) - { - struct rptun_priv_s *priv; - - priv = metal_container_of(pnode, - struct rptun_priv_s, node); - - if (priv->rproc.state == RPROC_RUNNING) - { - device_destroy(&priv->rvdev.rdev, priv_); - } - } - } - - nxrmutex_unlock(&g_rptun_lockcb); -} - int rptun_initialize(FAR struct rptun_dev_s *dev) { struct metal_init_params params = METAL_INIT_DEFAULTS; FAR struct rptun_priv_s *priv; - static bool onceinit; -#ifndef CONFIG_RPTUN_WORKQUEUE + static bool onceinit = false; FAR char *argv[3]; char arg1[19]; -#endif char name[32]; int ret; @@ -1228,24 +1000,15 @@ int rptun_initialize(FAR struct rptun_dev_s *dev) priv->dev = dev; remoteproc_init(&priv->rproc, &g_rptun_ops, priv); - metal_list_init(&priv->bind); - nxrmutex_init(&priv->lock); snprintf(name, sizeof(name), "/dev/rptun/%s", RPTUN_GET_CPUNAME(dev)); - ret = register_driver(name, &g_rptun_devops, 0222, priv); + ret = rpmsg_register(name, &priv->rpmsg, &g_rptun_rpmsg_ops); if (ret < 0) { goto err_driver; } nxsem_init(&priv->semtx, 0, 0); - -#ifdef CONFIG_RPTUN_WORKQUEUE - if (RPTUN_IS_AUTOSTART(dev)) - { - work_queue(HPWORK, &priv->work, rptun_start_worker, priv, 0); - } -#else nxsem_init(&priv->semrx, 0, 0); snprintf(arg1, sizeof(arg1), "0x%" PRIxPTR, (uintptr_t)priv); argv[0] = (void *)RPTUN_GET_CPUNAME(dev); @@ -1256,23 +1019,19 @@ int rptun_initialize(FAR struct rptun_dev_s *dev) CONFIG_RPTUN_STACKSIZE, rptun_thread, argv); if (ret < 0) { - unregister_driver(name); - nxsem_destroy(&priv->semtx); - nxsem_destroy(&priv->semrx); - goto err_driver; + goto err_thread; } -#endif /* Add priv to list */ - nxrmutex_lock(&g_rptun_lockcb); - metal_list_add_tail(&g_rptun_priv, &priv->node); - nxrmutex_unlock(&g_rptun_lockcb); - return OK; +err_thread: + nxsem_destroy(&priv->semtx); + nxsem_destroy(&priv->semrx); + rpmsg_unregister(name, &priv->rpmsg); + err_driver: - nxrmutex_destroy(&priv->lock); kmm_free(priv); err_mem: @@ -1282,40 +1041,15 @@ int rptun_initialize(FAR struct rptun_dev_s *dev) int rptun_boot(FAR const char *cpuname) { - return rptun_ioctl_foreach(cpuname, RPTUNIOC_START, 0); + return rpmsg_ioctl(cpuname, RPTUNIOC_START, 0); } int rptun_poweroff(FAR const char *cpuname) { - return rptun_ioctl_foreach(cpuname, RPTUNIOC_STOP, 0); + return rpmsg_ioctl(cpuname, RPTUNIOC_STOP, 0); } int rptun_reset(FAR const char *cpuname, int value) { - return rptun_ioctl_foreach(cpuname, RPTUNIOC_RESET, value); -} - -int rptun_panic(FAR const char *cpuname) -{ - return rptun_ioctl_foreach(cpuname, RPTUNIOC_PANIC, 0); -} - -int rptun_buffer_nused(FAR struct rpmsg_virtio_device *rvdev, bool rx) -{ - FAR struct virtqueue *vq = rx ? rvdev->rvq : rvdev->svq; - uint16_t nused = vq->vq_ring.avail->idx - vq->vq_ring.used->idx; - - if ((rpmsg_virtio_get_role(rvdev) == RPMSG_HOST) ^ rx) - { - return nused; - } - else - { - return vq->vq_nentries - nused; - } -} - -void rptun_dump_all(void) -{ - rptun_ioctl_foreach(NULL, RPTUNIOC_DUMP, 0); + return rpmsg_ioctl(cpuname, RPTUNIOC_RESET, value); } diff --git a/drivers/rptun/rptun.h b/drivers/rptun/rptun.h deleted file mode 100644 index 77038b6dfedf4..0000000000000 --- a/drivers/rptun/rptun.h +++ /dev/null @@ -1,44 +0,0 @@ -/**************************************************************************** - * drivers/rptun/rptun.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __DRIVERS_RPTUN_RPTUN_H -#define __DRIVERS_RPTUN_RPTUN_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -int rptun_buffer_nused(FAR struct rpmsg_virtio_device *rvdev, bool rx); -void rptun_dump(FAR struct rpmsg_virtio_device *rvdev); - -int rptun_ping_init(FAR struct rpmsg_virtio_device *rvdev, - FAR struct rpmsg_endpoint *ept); -void rptun_ping_deinit(FAR struct rpmsg_endpoint *ept); -int rptun_ping(FAR struct rpmsg_endpoint *ept, - FAR const struct rptun_ping_s *ping); - -#endif /* __DRIVERS_RPTUN_RPTUN_H */ diff --git a/drivers/rptun/rptun_dump.c b/drivers/rptun/rptun_dump.c index 9061569e08a39..b51152f32a597 100644 --- a/drivers/rptun/rptun_dump.c +++ b/drivers/rptun/rptun_dump.c @@ -115,7 +115,7 @@ void rptun_dump(FAR struct rpmsg_virtio_device *rvdev) metal_log(METAL_LOG_EMERGENCY, "Dump rpmsg info between cpu (master: %s)%s <==> %s:\n", rpmsg_virtio_get_role(rvdev) == RPMSG_HOST ? "yes" : "no", - CONFIG_RPTUN_LOCAL_CPUNAME, rpmsg_get_cpuname(rdev)); + CONFIG_RPMSG_LOCAL_CPUNAME, rpmsg_get_cpuname(rdev)); metal_log(METAL_LOG_EMERGENCY, "rpmsg vq RX:\n"); virtqueue_dump(rvdev->rvq); diff --git a/drivers/rptun/rptun_ping.c b/drivers/rptun/rptun_ping.c deleted file mode 100644 index ea8302aeb2a67..0000000000000 --- a/drivers/rptun/rptun_ping.c +++ /dev/null @@ -1,194 +0,0 @@ -/**************************************************************************** - * drivers/rptun/rptun_ping.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include -#include -#include -#include - -#include "rptun.h" - -/**************************************************************************** - * Pre-processor definitions - ****************************************************************************/ - -#define RPTUN_PING_EPT_NAME "rpmsg-ping" -#define RPTUN_PING_SEND 1 -#define RPTUN_PING_SEND_NOACK 2 -#define RPTUN_PING_ACK 3 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -begin_packed_struct struct rptun_ping_msg_s -{ - uint32_t cmd; - uint32_t len; - uint64_t cookie; -} end_packed_struct; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static int rptun_ping_ept_cb(FAR struct rpmsg_endpoint *ept, - FAR void *data, size_t len, uint32_t src, - FAR void *priv) -{ - FAR struct rptun_ping_msg_s *msg = data; - FAR sem_t *sem = (FAR sem_t *)(uintptr_t)msg->cookie; - - if (msg->cmd == RPTUN_PING_SEND) - { - msg->cmd = RPTUN_PING_ACK; - rpmsg_send(ept, msg, len); - } - else if (msg->cmd == RPTUN_PING_ACK) - { - nxsem_post(sem); - } - - return 0; -} - -static int rptun_ping_once(FAR struct rpmsg_endpoint *ept, - int len, bool ack) -{ - FAR struct rptun_ping_msg_s *msg; - uint32_t space; - int ret; - - msg = rpmsg_get_tx_payload_buffer(ept, &space, true); - if (!msg) - { - return -ENOMEM; - } - - len = MAX(len, sizeof(struct rptun_ping_msg_s)); - len = MIN(len, space); - - memset(msg, 0, len); - - if (ack) - { - sem_t sem; - - msg->cmd = RPTUN_PING_SEND; - msg->len = len; - msg->cookie = (uintptr_t)&sem; - - nxsem_init(&sem, 0, 0); - - ret = rpmsg_send_nocopy(ept, msg, len); - if (ret >= 0) - { - nxsem_wait_uninterruptible(&sem); - } - - nxsem_destroy(&sem); - } - else - { - msg->cmd = RPTUN_PING_SEND_NOACK; - msg->len = len; - ret = rpmsg_send_nocopy(ept, msg, len); - } - - return ret; -} - -static void rptun_ping_logout(FAR const char *s, clock_t value) -{ - struct timespec ts; - - perf_convert(value, &ts); - -#ifdef CONFIG_SYSTEM_TIME64 - syslog(LOG_INFO, "%s: s %" PRIu64 ", ns %ld\n", s, ts.tv_sec, ts.tv_nsec); -#else - syslog(LOG_INFO, "%s: s %" PRIu32 ", ns %ld\n", s, ts.tv_sec, ts.tv_nsec); -#endif -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int rptun_ping(FAR struct rpmsg_endpoint *ept, - FAR const struct rptun_ping_s *ping) -{ - clock_t min = ULONG_MAX; - clock_t max = 0; - uint64_t total = 0; - int i; - - if (!ept || !ping || ping->times <= 0) - { - return -EINVAL; - } - - for (i = 0; i < ping->times; i++) - { - clock_t tm = perf_gettime(); - - int ret = rptun_ping_once(ept, ping->len, ping->ack); - if (ret < 0) - { - return ret; - } - - tm = perf_gettime() - tm; - min = MIN(min, tm); - max = MAX(max, tm); - total += tm; - - nxsig_usleep(ping->sleep * USEC_PER_MSEC); - } - - syslog(LOG_INFO, "ping times: %d\n", ping->times); - - rptun_ping_logout("avg", total / ping->times); - rptun_ping_logout("min", min); - rptun_ping_logout("max", max); - - return 0; -} - -int rptun_ping_init(FAR struct rpmsg_virtio_device *rvdev, - FAR struct rpmsg_endpoint *ept) -{ - return rpmsg_create_ept(ept, &rvdev->rdev, RPTUN_PING_EPT_NAME, - RPMSG_ADDR_ANY, RPMSG_ADDR_ANY, - rptun_ping_ept_cb, NULL); -} - -void rptun_ping_deinit(FAR struct rpmsg_endpoint *ept) -{ - rpmsg_destroy_ept(ept); -} diff --git a/drivers/segger/note_sysview.c b/drivers/segger/note_sysview.c index 807ee225eb69f..fc0b00bd8b122 100644 --- a/drivers/segger/note_sysview.c +++ b/drivers/segger/note_sysview.c @@ -164,11 +164,11 @@ static void note_sysview_send_tasklist(void) { int i; - for (i = 0; i < g_npidhash; i++) + for (i = 0; i < nxsched_npidhash(); i++) { - if (g_pidhash[i] != NULL) + if (nxsched_pidhash()[i] != NULL) { - note_sysview_send_taskinfo(g_pidhash[i]); + note_sysview_send_taskinfo(nxsched_pidhash()[i]); } } } @@ -247,7 +247,7 @@ static void note_sysview_irqhandler(FAR struct note_driver_s *drv, int irq, if (enter) { - driver->irq[up_cpu_index()] = irq; + driver->irq[this_cpu()] = irq; SEGGER_SYSVIEW_OnTaskStopExec(); SEGGER_SYSVIEW_RecordEnterISR(); @@ -270,7 +270,7 @@ static void note_sysview_irqhandler(FAR struct note_driver_s *drv, int irq, } } - driver->irq[up_cpu_index()] = 0; + driver->irq[this_cpu()] = 0; } } #endif @@ -337,7 +337,7 @@ static void note_sysview_syscall_leave(FAR struct note_driver_s *drv, unsigned int note_sysview_get_interrupt_id(void) { - return g_note_sysview_driver.irq[up_cpu_index()]; + return g_note_sysview_driver.irq[this_cpu()]; } /**************************************************************************** diff --git a/drivers/sensors/CMakeLists.txt b/drivers/sensors/CMakeLists.txt index d803163b64b5d..cf13bc90791d2 100644 --- a/drivers/sensors/CMakeLists.txt +++ b/drivers/sensors/CMakeLists.txt @@ -56,12 +56,30 @@ if(CONFIG_SENSORS) list(APPEND SRCS adxl345_base.c) endif() + if(CONFIG_SENSORS_ADXL362) + list(APPEND SRCS adxl362_uorb.c) + endif() + + if(CONFIG_SENSORS_BH1749NUC) + list(APPEND SRCS bh1749nuc_base.c) + if(CONFIG_SENSORS_BH1749NUC_UORB) + list(APPEND SRCS bh1749nuc_uorb.c) + else() + list(APPEND SRCS bh1749nuc.c) + endif() + endif() + if(CONFIG_SENSORS_DHTXX) list(APPEND SRCS dhtxx.c) endif() if(CONFIG_SENSORS_BMI270) - list(APPEND SRCS bmi270.c) + list(APPEND SRCS bmi270_base.c) + if(CONFIG_SENSORS_BMI270_UORB) + list(APPEND SRCS bmi270_uorb.c) + else() + list(APPEND SRCS bmi270.c) + endif() endif() # These drivers depend on I2C support @@ -113,7 +131,12 @@ if(CONFIG_SENSORS) endif() if(CONFIG_SENSORS_LSM9DS1) - list(APPEND SRCS lsm9ds1.c) + list(APPEND SRCS lsm9ds1_base.c) + if(CONFIG_SENSORS_LSM9DS1_UORB) + list(APPEND SRCS lsm9ds1_uorb.c) + else() + list(APPEND SRCS lsm9ds1.c) + endif() endif() if(CONFIG_SENSORS_MSA301) @@ -137,7 +160,12 @@ if(CONFIG_SENSORS) endif() if(CONFIG_SENSORS_BMI160) - list(APPEND SRCS bmi160.c) + list(APPEND SRCS bmi160_base.c) + if(CONFIG_SENSORS_BMI160_UORB) + list(APPEND SRCS bmi160_uorb.c) + else() + list(APPEND SRCS bmi160.c) + endif() endif() if(CONFIG_SENSORS_BMP180) @@ -248,6 +276,10 @@ if(CONFIG_SENSORS) list(APPEND SRCS ltr308_uorb.c) endif() + if(CONFIG_SENSORS_BMM150) + list(APPEND SRCS bmm150_uorb.c) + endif() + endif() # CONFIG_I2C # These drivers depend on SPI support @@ -259,7 +291,11 @@ if(CONFIG_SENSORS) endif() if(CONFIG_SENSORS_ADXL372) - list(APPEND SRCS adxl372.c) + if(CONFIG_SENSORS_ADXL372_UORB) + list(APPEND SRCS adxl372_uorb.c) + else() + list(APPEND SRCS adxl372.c) + endif() endif() if(CONFIG_LIS3DSH) diff --git a/drivers/sensors/Kconfig b/drivers/sensors/Kconfig index 8de08bc8c5e06..21bdd56f7ae25 100644 --- a/drivers/sensors/Kconfig +++ b/drivers/sensors/Kconfig @@ -20,7 +20,7 @@ config USENSOR config SENSORS_RPMSG bool "Sensor RPMSG Support" default n - depends on RPTUN + depends on RPMSG ---help--- Allow application to read or control remote sensor device by RPMSG. @@ -141,6 +141,43 @@ config SENSORS_BH1749NUC ---help--- Enable driver support for the Rohm BH1749NUC color sensor. +if SENSORS_BH1749NUC + +config BH1749NUC_I2C_FREQUENCY + int "BH1749NUC I2C frequency" + default 400000 + +config SENSORS_BH1749NUC_UORB + bool "BH1749NUC UORB Interface" + default n + +if SENSORS_BH1749NUC_UORB + +config SENSORS_BH1749NUC_POLL + bool "Enables polling sensor data" + default n + ---help--- + Enables polling of sensor. + +config SENSORS_BH1749NUC_POLL_INTERVAL + int "Polling interval in microseconds, default 1 sec" + depends on SENSORS_BH1749NUC_POLL + default 1000000 + range 0 4294967295 + ---help--- + The interval until a new sensor measurement will be triggered. + +config SENSORS_BH1749NUC_THREAD_STACKSIZE + int "Worker thread stack size" + depends on SENSORS_BH1749NUC_POLL + default 1024 + ---help--- + The stack size for the worker thread. + +endif #SENSORS_BH1749NUC_UORB + +endif # SENSORS_BH1749NUC + config SENSORS_BH1750FVI bool "Rohm BH1750FVI Ambient Light Sensor support" default n @@ -223,6 +260,35 @@ config SENSORS_BMI270 if SENSORS_BMI270 +config SENSORS_BMI270_UORB + bool "Bosch BMI270 UORB" + default n + +if SENSORS_BMI270_UORB + +config SENSORS_BMI270_POLL + bool "Enables polling sensor data" + default n + ---help--- + Enables polling of sensor. + +config SENSORS_BMI270_POLL_INTERVAL + int "Polling interval in microseconds, default 1 sec" + depends on SENSORS_BMI270_POLL + default 1000000 + range 0 4294967295 + ---help--- + The interval until a new sensor measurement will be triggered. + +config SENSORS_BMI270_THREAD_STACKSIZE + int "Worker thread stack size" + depends on SENSORS_BMI270_POLL + default 1024 + ---help--- + The stack size for the worker thread. + +endif #SENSORS_BMI270_UORB + choice prompt "BMI270 Interface" default SENSORS_BMI270_SPI @@ -251,6 +317,42 @@ config SENSORS_BMI270_LOAD_FROM_HEAP endif # SENSORS_BMI270 +config SENSORS_BMM150 + bool "Bosch BMM150 Magnetometer support (uorb)" + default n + select I2C + ---help--- + Enable driver support for the Bosch BMM150 magnetometer sensor. + +if SENSORS_BMM150 + +config BMM150_I2C_FREQUENCY + int "BMM150 I2C frequency" + default 400000 + +config SENSORS_BMM150_POLL + bool "Enables polling sensor data" + default n + ---help--- + Enables polling of sensor. + +config SENSORS_BMM150_POLL_INTERVAL + int "Polling interval in microseconds, default 1 sec" + depends on SENSORS_BMM150_POLL + default 1000000 + range 0 4294967295 + ---help--- + The interval until a new sensor measurement will be triggered. + +config SENSORS_BMM150_THREAD_STACKSIZE + int "Worker thread stack size" + depends on SENSORS_BMM150_POLL + default 1024 + ---help--- + The stack size for the worker thread. + +endif # SENSORS_BMM150 + config SENSORS_BMP180 bool "Bosch BMP180 Barometer Sensor support" default n @@ -290,35 +392,32 @@ config SENSORS_BME680 ---help--- Enable driver for the Bosch BME680 sensor. +if SENSORS_BME680 + config BME680_I2C_FREQUENCY int "BME680 I2C frequency" - depends on SENSORS_BME680 default 400000 config BME680_DISABLE_PRESS_MEAS bool "Disable Pressure Measurement" - depends on SENSORS_BME680 default n ---help--- If enabled, the sensor will not measure pressure. config BME680_DISABLE_HUM_MEAS bool "Disable Humidity Measurement" - depends on SENSORS_BME680 default n ---help--- If enabled, the sensor will not measure humidity. config BME680_DISABLE_GAS_MEAS bool "Disable Gas Measurement" - depends on SENSORS_BME680 default n ---help--- If enabled, the sensor will not measure gas. config BME680_ENABLE_IIR_FILTER bool "Enable IIR Filter" - depends on SENSORS_BME680 default n ---help--- Enable IIR filtering for temperature and pressure @@ -326,7 +425,6 @@ config BME680_ENABLE_IIR_FILTER config SENSORS_BME680_POLL_INTERVAL int "Polling interval in microseconds, default 3 sec" - depends on SENSORS_BME680 default 3000000 range 0 4294967295 ---help--- @@ -334,11 +432,12 @@ config SENSORS_BME680_POLL_INTERVAL config SENSORS_BME680_THREAD_STACKSIZE int "Worker thread stack size" - depends on SENSORS_BME680 default 1024 ---help--- The stack size for the worker thread. +endif # SENSORS_BME680 + config SENSORS_DHTXX bool "DHTxx humidity/temperature Sensor support" default n @@ -387,6 +486,22 @@ config SENSORS_HCSR04 ---help--- Enable driver support for the HC-SR04 Distance Sensor. +if SENSORS_HCSR04 + +config HCSR04_DEBUG + bool "Debug support for the HC-SR04" + default n + ---help--- + Enables debug features for the HC-SR04 + +config HCSR04_NPOLLWAITERS + int "Number of waiters to poll" + default 1 + ---help--- + Number of waiters to poll + +endif # SENSORS_HCSR04 + config SENSORS_HYT271 bool "IST HYT271 Humidity and Temperature Sensor support" default n @@ -415,22 +530,6 @@ config SENSORS_HYT271_THREAD_STACKSIZE ---help--- The stack size for the worker thread. -if SENSORS_HCSR04 - -config HCSR04_DEBUG - bool "Debug support for the HC-SR04" - default n - ---help--- - Enables debug features for the HC-SR04 - -config HCSR04_NPOLLWAITERS - int "Number of waiters to poll" - default 1 - ---help--- - Number of waiters to poll - -endif # SENSORS_HCSR04 - config SENSORS_ISL29023 bool "Renesas ISL29023 ALS sensor" default n @@ -605,6 +704,36 @@ config SENSORS_LSM9DS1 ---help--- Enable driver support for the STMicro LSM9DS1. +config SENSORS_LSM9DS1_UORB + bool "LSM9DS1 UORB Interface" + default n + depends on SENSORS_LSM9DS1 + +if SENSORS_LSM9DS1_UORB + +config SENSORS_LSM9DS1_POLL + bool "Enables polling sensor data" + default n + ---help--- + Enables polling of sensor. + +config SENSORS_LSM9DS1_POLL_INTERVAL + int "Polling interval in microseconds, default 1 sec" + depends on SENSORS_LSM9DS1_POLL + default 1000000 + range 0 4294967295 + ---help--- + The interval until a new sensor measurement will be triggered. + +config SENSORS_LSM9DS1_THREAD_STACKSIZE + int "Worker thread stack size" + depends on SENSORS_LSM9DS1_POLL + default 1024 + ---help--- + The stack size for the worker thread. + +endif #SENSORS_LSM9DS1_UORB + config SENSORS_MSA301 bool "MSA301 support" default n @@ -616,7 +745,7 @@ config LSM9DS1_I2C_FREQUENCY int "LSM9DS1 I2C frequency" default 400000 range 1 400000 - depends on SENSORS_LSM9DS1 + depends on SENSORS_LSM9DS1 || SENSORS_LSM9DS1_UORB config SENSORS_LPS25H bool "STMicro LPS25H pressure sensor" @@ -862,6 +991,37 @@ config ADXL345_REGDEBUG endif # SENSORS_ADXL345 +config SENSORS_ADXL362 + bool "Analog Devices ADXL362 Driver" + default n + ---help--- + Enables support for the ADXL362 driver + +if SENSORS_ADXL362 + +config SENSORS_ADXL362_POLL + bool "Enables polling sensor data" + default n + ---help--- + Enables polling of sensor. + +config SENSORS_ADXL362_POLL_INTERVAL + int "Polling interval in microseconds, default 1 sec" + depends on SENSORS_ADXL362_POLL + default 1000000 + range 0 4294967295 + ---help--- + The interval until a new sensor measurement will be triggered. + +config SENSORS_ADXL362_THREAD_STACKSIZE + int "Worker thread stack size" + depends on SENSORS_ADXL362_POLL + default 1024 + ---help--- + The stack size for the worker thread. + +endif # SENSORS_ADXL362 + config SENSORS_ADXL372 bool "Analog Devices ADXL372 Sensor support" default n @@ -869,6 +1029,39 @@ config SENSORS_ADXL372 ---help--- Enable driver support for the Analog Devices ADXL372 Sensor. +if SENSORS_ADXL372 + +config SENSORS_ADXL372_UORB + bool "ADXL372 UORB interface" + default n + +if SENSORS_ADXL372_UORB + +config SENSORS_ADXL372_POLL + bool "Enables polling sensor data" + default n + ---help--- + Enables polling of sensor. + +config SENSORS_ADXL372_POLL_INTERVAL + int "Polling interval in microseconds, default 1 sec" + depends on SENSORS_ADXL372_POLL + default 1000000 + range 0 4294967295 + ---help--- + The interval until a new sensor measurement will be triggered. + +config SENSORS_ADXL372_THREAD_STACKSIZE + int "Worker thread stack size" + depends on SENSORS_ADXL372_POLL + default 1024 + ---help--- + The stack size for the worker thread. + +endif #SENSORS_ADXL372_UORB + +endif # SENSORS_ADXL372 + config SENSORS_MPU60X0 bool "Invensense MPU60x0 Sensor support" default n diff --git a/drivers/sensors/Make.defs b/drivers/sensors/Make.defs index 8e513ab06e4da..9e0d5e8881e51 100644 --- a/drivers/sensors/Make.defs +++ b/drivers/sensors/Make.defs @@ -65,8 +65,13 @@ ifeq ($(CONFIG_SENSORS_DHTXX),y) endif ifeq ($(CONFIG_SENSORS_BMI270),y) + CSRCS += bmi270_base.c +ifeq ($(CONFIG_SENSORS_BMI270_UORB),y) + CSRCS += bmi270_bmi.c +else CSRCS += bmi270.c endif +endif # These drivers depend on I2C support @@ -121,7 +126,12 @@ ifeq ($(CONFIG_SENSORS_LSM6DSL),y) endif ifeq ($(CONFIG_SENSORS_LSM9DS1),y) - CSRCS += lsm9ds1.c + CSRCS += lsm9ds1_base.c + ifeq ($(CONFIG_SENSORS_LSM9DS1_UORB),y) + CSRCS += lsm9ds1_uorb.c + else + CSRCS += lsm9ds1.c + endif endif ifeq ($(CONFIG_SENSORS_MSA301),y) @@ -137,8 +147,13 @@ ifeq ($(CONFIG_ADXL345_I2C),y) endif ifeq ($(CONFIG_SENSORS_BH1749NUC),y) + CSRCS += bh1749nuc_base.c +ifeq ($(CONFIG_SENSORS_BH1749NUC_UORB),y) + CSRCS += bh1749nuc_uorb.c +else CSRCS += bh1749nuc.c endif +endif ifeq ($(CONFIG_SENSORS_BH1750FVI),y) CSRCS += bh1750fvi.c @@ -157,6 +172,10 @@ else endif endif +ifeq ($(CONFIG_SENSORS_BMM150),y) + CSRCS += bmm150.c +endif + ifeq ($(CONFIG_SENSORS_BMP180),y) CSRCS += bmp180_base.c ifeq ($(CONFIG_SENSORS_BMP180_UORB),y) @@ -270,6 +289,10 @@ ifeq ($(CONFIG_SENSORS_LTR308),y) CSRCS += ltr308_uorb.c endif +ifeq ($(CONFIG_SENSORS_BMM150),y) + CSRCS += bmm150_uorb.c +endif + endif # CONFIG_I2C # These drivers depend on SPI support @@ -280,9 +303,17 @@ ifeq ($(CONFIG_ADXL345_SPI),y) CSRCS += adxl345_spi.c endif +ifeq ($(CONFIG_SENSORS_ADXL362),y) + CSRCS += adxl362_uorb.c +endif + ifeq ($(CONFIG_SENSORS_ADXL372),y) +ifeq ($(CONFIG_SENSORS_ADXL372_UORB),y) + CSRCS += adxl372_uorb.c +else CSRCS += adxl372.c endif +endif ifeq ($(CONFIG_LIS3DSH),y) CSRCS += lis3dsh.c diff --git a/drivers/sensors/adxl362_uorb.c b/drivers/sensors/adxl362_uorb.c new file mode 100644 index 0000000000000..b1842e5bee349 --- /dev/null +++ b/drivers/sensors/adxl362_uorb.c @@ -0,0 +1,651 @@ +/**************************************************************************** + * drivers/sensors/adxl362_uorb.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ADXL362_SPI_FREQUENCY 1000000 +#define ADXL362_SPI_MODE SPIDEV_MODE0 + +#define ADXL362_WRITE 0x0a +#define ADXL362_READ 0x0b +#define ADXL362_FIFO 0x0d + +#define ADXL362_DEVID_AD 0x00 +# define ADXL362_DEVID_AD_VALUE 0xad +#define ADXL362_DEVID_MST 0x01 +# define ADXL362_DEVID_MST_VALUE 0x1d +#define ADXL362_PARTID 0x02 +# define ADXL362_PARTID_VALUE 0xf2 +#define ADXL362_REVID 0x03 +#define ADXL362_XDATA 0x08 +#define ADXL362_YDATA 0x09 +#define ADXL362_ZDATA 0x0a +#define ADXL362_STATUS 0x0b +#define ADXL362_FIFO_L 0x0c +#define ADXL362_FIFO_H 0x0d +#define ADXL362_XDATA_L 0x0e +#define ADXL362_XDATA_H 0x0f +#define ADXL362_YDATA_L 0x10 +#define ADXL362_YDATA_H 0x11 +#define ADXL362_ZDATA_L 0x12 +#define ADXL362_ZDATA_H 0x13 +#define ADXL362_TMEP_L 0x14 +#define ADXL362_TEMP_H 0x15 +#define ADXL362_SOFT_RESET 0x1f +# define ADXL362_SOFT_RESET_VALUE 0x52 +#define ADXL362_THRESH_ACT_L 0x20 +#define ADXL362_THRESH_ACT_H 0x21 +#define ADXL362_TIME_ACT 0x22 +#define ADXL362_THRESH_INACT_L 0x23 +#define ADXL362_THRESH_INACT_H 0x24 +#define ADXL362_TIME_INACT_L 0x25 +#define ADXL362_TIME_INACT_H 0x26 +#define ADXL362_ACT_INACT_CTL 0x27 +#define ADXL362_FIFO_CONTROL 0x28 +#define ADXL362_FIFO_SAMPLES 0x29 +#define ADXL362_INTMAP1 0x2a +#define ADXL362_INTMAP2 0x2b +#define ADXL362_FILTER_CTL 0x2c +# define ADXL362_FILTER_CTL_DEFAULT 0x13 +#define ADXL362_POWER_CTL 0x2d +# define ADXL362_LOW_NOISE (0 << 4) +# define ADXL362_ULTRALOW_NOISE (2 << 4) +# define ADXL362_POWER_MODE_STANDBY 0 +# define ADXL362_POWER_MODE_MEASURE 2 +#define ADXL362_SELF_TEST 0x2e + +#define CONSTANTS_ONE_G 9.8f +#define ADXL362_TEMP_SCALE 0.065f + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct adxl362_sensor_s +{ + struct sensor_lowerhalf_s lower; + FAR struct spi_dev_s *spi; + int devno; + float scale; +#ifdef CONFIG_SENSORS_ADXL362_POLL + bool enabled; + unsigned long interval; + sem_t run; +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static uint8_t adxl362_getreg8(FAR struct adxl362_sensor_s *priv, + uint8_t regaddr); +static void adxl362_putreg8(FAR struct adxl362_sensor_s *priv, + uint8_t regaddr, uint8_t regval); +static void adxl362_getregs(FAR struct adxl362_sensor_s *priv, + uint8_t regaddr, FAR uint8_t *regval, int len); +static int16_t adxl362_data(FAR uint8_t *data); +static int adxl362_checkid(FAR struct adxl362_sensor_s *priv); +static void adxl362_start(FAR struct adxl362_sensor_s *priv); +static void adxl362_stop(FAR struct adxl362_sensor_s *priv); + +/* Sensor ops functions */ + +static int adxl362_activate(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + bool enable); +static int adxl362_set_interval(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR unsigned long *period_us); +#ifndef CONFIG_SENSORS_ADXL362_POLL +static int adxl362_fetch(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR char *buffer, size_t buflen); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct sensor_ops_s g_adxl362_accel_ops = +{ + NULL, /* open */ + NULL, /* close */ + adxl362_activate, + adxl362_set_interval, + NULL, /* batch */ +#ifdef CONFIG_SENSORS_ADXL362_POLL + NULL, /* fetch */ +#else + adxl362_fetch, +#endif + NULL, /* selftest */ + NULL, /* set_calibvalue */ + NULL, /* calibrate */ + NULL, /* control */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: adxl362_getreg8 + * + * Description: + * Read from an 8-bit ADXL362 register + * + ****************************************************************************/ + +static uint8_t adxl362_getreg8(FAR struct adxl362_sensor_s *priv, + uint8_t regaddr) +{ + uint8_t regval = 0; + + SPI_LOCK(priv->spi, true); + + SPI_SETFREQUENCY(priv->spi, ADXL362_SPI_FREQUENCY); + SPI_SETMODE(priv->spi, ADXL362_SPI_MODE); + + /* Select the ADXL362 */ + + SPI_SELECT(priv->spi, SPIDEV_ACCELEROMETER(priv->devno), true); + + /* Send register to read and get the next byte */ + + SPI_SEND(priv->spi, ADXL362_READ); + SPI_SEND(priv->spi, regaddr); + SPI_RECVBLOCK(priv->spi, ®val, 1); + + /* Deselect the ADXL362 */ + + SPI_SELECT(priv->spi, SPIDEV_ACCELEROMETER(priv->devno), false); + + /* Unlock bus */ + + SPI_LOCK(priv->spi, false); + + return regval; +} + +/**************************************************************************** + * Name: adxl362_putreg8 + * + * Description: + * Write a value to an 8-bit ADXL362 register + * + ****************************************************************************/ + +static void adxl362_putreg8(FAR struct adxl362_sensor_s *priv, + uint8_t regaddr, uint8_t regval) +{ + SPI_LOCK(priv->spi, true); + + SPI_SETFREQUENCY(priv->spi, ADXL362_SPI_FREQUENCY); + SPI_SETMODE(priv->spi, ADXL362_SPI_MODE); + + /* Select the ADXL362 */ + + SPI_SELECT(priv->spi, SPIDEV_ACCELEROMETER(priv->devno), true); + + /* Send register address and set the value */ + + SPI_SEND(priv->spi, ADXL362_WRITE); + SPI_SEND(priv->spi, regaddr); + SPI_SEND(priv->spi, regval); + + /* Deselect the ADXL362 */ + + SPI_SELECT(priv->spi, SPIDEV_ACCELEROMETER(priv->devno), false); + + /* Unlock bus */ + + SPI_LOCK(priv->spi, false); +} + +/**************************************************************************** + * Name: adxl362_getregs + * + * Description: + * Read bytes from specified regaddr + * + ****************************************************************************/ + +static void adxl362_getregs(FAR struct adxl362_sensor_s *priv, + uint8_t regaddr, FAR uint8_t *regval, int len) +{ + /* If SPI bus is shared then lock and configure it */ + + SPI_LOCK(priv->spi, true); + + SPI_SETFREQUENCY(priv->spi, ADXL362_SPI_FREQUENCY); + SPI_SETMODE(priv->spi, ADXL362_SPI_MODE); + + /* Select the ADXL362 */ + + SPI_SELECT(priv->spi, SPIDEV_ACCELEROMETER(priv->devno), true); + + /* Send register to read and get the next 2 bytes */ + + SPI_SEND(priv->spi, ADXL362_READ); + SPI_SEND(priv->spi, regaddr); + SPI_RECVBLOCK(priv->spi, regval, len); + + /* Deselect the ADXL362 */ + + SPI_SELECT(priv->spi, SPIDEV_ACCELEROMETER(priv->devno), false); + + /* Unlock bus */ + + SPI_LOCK(priv->spi, false); +} + +/**************************************************************************** + * Name: adxl362_data + ****************************************************************************/ + +static int16_t adxl362_data(FAR uint8_t *data) +{ + return (int16_t)(data[0] | (data[1]) << 8); +} + +/**************************************************************************** + * Name: adxl362_checkid + * + * Description: + * Read and verify the ADXL362 chip ID + * + ****************************************************************************/ + +static int adxl362_checkid(FAR struct adxl362_sensor_s *priv) +{ + uint8_t id = 0; + + id = adxl362_getreg8(priv, ADXL362_DEVID_AD); + if (id != ADXL362_DEVID_AD_VALUE) + { + snerr("Wrong AD! %02x\n", id); + return -ENODEV; + } + + id = adxl362_getreg8(priv, ADXL362_DEVID_MST); + if (id != ADXL362_DEVID_MST_VALUE) + { + snerr("Wrong MST! %02x\n", id); + return -ENODEV; + } + + id = adxl362_getreg8(priv, ADXL362_PARTID); + if (id != ADXL362_PARTID_VALUE) + { + snerr("Wrong PARTID! %02x\n", id); + return -ENODEV; + } + + return OK; +} + +/**************************************************************************** + * Name: adxl362_reset + * + * Description: + * Soft reset + * + ****************************************************************************/ + +static void adxl362_reset(FAR struct adxl362_sensor_s *priv) +{ + adxl362_putreg8(priv, ADXL362_SOFT_RESET, ADXL362_SOFT_RESET_VALUE); + up_mdelay(5); +} + +/**************************************************************************** + * Name: adxl362_start + ****************************************************************************/ + +static void adxl362_start(FAR struct adxl362_sensor_s *priv) +{ + adxl362_putreg8(priv, ADXL362_POWER_CTL, ADXL362_POWER_MODE_MEASURE); + + /* Wait for sensor ready - otherwise the first measuremet is garbage */ + + up_mdelay(5); +} + +/**************************************************************************** + * Name: adxl362_stop + ****************************************************************************/ + +static void adxl362_stop(FAR struct adxl362_sensor_s *priv) +{ + adxl362_putreg8(priv, ADXL362_POWER_CTL, 0); +} + +/**************************************************************************** + * Name: adxl362_activate + * + * Description: + * Enable or disable sensor device. when enable sensor, sensor will + * work in current mode(if not set, use default mode). when disable + * sensor, it will disable sense path and stop convert. + * + * Input Parameters: + * lower - The instance of lower half sensor driver. + * filep - The pointer of file, represents each user using the sensor. + * enable - true(enable) and false(disable). + * + * Returned Value: + * Return 0 if the driver was success; A negated errno + * value is returned on any failure. + * + * Assumptions/Limitations: + * none. + * + ****************************************************************************/ + +static int adxl362_activate(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + bool enable) +{ + FAR struct adxl362_sensor_s *priv = (FAR struct adxl362_sensor_s *)lower; +#ifdef CONFIG_SENSORS_ADXL362_POLL + bool start_thread = false; +#endif + + if (enable) + { +#ifdef CONFIG_SENSORS_ADXL362_POLL + if (!priv->enabled) + { + start_thread = true; + } +#endif + + adxl362_start(priv); + } + else + { + adxl362_stop(priv); + } + +#ifdef CONFIG_SENSORS_ADXL362_POLL + priv->enabled = enable; + + if (start_thread) + { + /* Wake up the thread */ + + nxsem_post(&priv->run); + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: adxl362_set_interval + * + * Description: + * Set the sensor output data period in microseconds for a given sensor. + * If *period_us > max_delay it will be truncated to max_delay and if + * *period_us < min_delay it will be replaced by min_delay. + * + * Input Parameters: + * lower - The instance of lower half sensor driver. + * filep - The pointer of file, represents each user using the sensor. + * period_us - The time between report data, in us. It may by overwrite + * by lower half driver. + * + * Returned Value: + * Return 0 if the driver was success; A negated errno + * value is returned on any failure. + * + * Assumptions/Limitations: + * none. + * + ****************************************************************************/ + +static int adxl362_set_interval(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR unsigned long *period_us) +{ +#ifdef CONFIG_SENSORS_ADXL362_POLL + FAR struct adxl362_sensor_s *priv = (FAR struct adxl362_sensor_s *)lower; + + priv->interval = *period_us; +#endif + + return OK; +} + +#ifndef CONFIG_SENSORS_ADXL362_POLL +/**************************************************************************** + * Name: adxl362_set_interval + ****************************************************************************/ + +static int adxl362_fetch(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, FAR char *buffer, + size_t buflen) +{ + FAR struct adxl362_sensor_s *priv = (FAR struct adxl362_sensor_s *)lower; + struct sensor_accel accel; + uint8_t data[8]; + + /* Wait for data ready */ + + while (!(adxl362_getreg8(priv, ADXL362_STATUS) & 0x01)); + + /* Get data */ + + adxl362_getregs(priv, ADXL362_XDATA_L, (FAR uint8_t *)data, 8); + + accel.timestamp = sensor_get_timestamp(); + accel.x = (float)adxl362_data(&data[0]) * priv->scale; + accel.y = (float)adxl362_data(&data[2]) * priv->scale; + accel.z = (float)adxl362_data(&data[4]) * priv->scale; + accel.temperature = (float)adxl362_data(&data[6]) * ADXL362_TEMP_SCALE; + + memcpy(buffer, &accel, sizeof(accel)); + + return sizeof(accel); +} +#endif + +#ifdef CONFIG_SENSORS_ADXL362_POLL +/**************************************************************************** + * Name: adxl362_thread + * + * Description: Thread for performing interval measurement cycle and data + * read. + * + * Parameter: + * argc - Number opf arguments + * argv - Pointer to argument list + * + ****************************************************************************/ + +static int adxl362_thread(int argc, FAR char **argv) +{ + FAR struct adxl362_sensor_s *priv + = (FAR struct adxl362_sensor_s *)((uintptr_t)strtoul(argv[1], NULL, + 16)); + struct sensor_accel accel; + uint8_t data[8]; + int ret; + + while (true) + { + if ((!priv->enabled)) + { + /* Waiting to be woken up */ + + ret = nxsem_wait(&priv->run); + if (ret < 0) + { + continue; + } + } + + /* Read accel */ + + if (priv->enabled) + { + /* Wait for data ready */ + + while (!(adxl362_getreg8(priv, ADXL362_STATUS) & 0x01)); + + adxl362_getregs(priv, ADXL362_XDATA_L, (FAR uint8_t *)data, 8); + + accel.timestamp = sensor_get_timestamp(); + accel.x = (float)adxl362_data(&data[0]) * priv->scale; + accel.y = (float)adxl362_data(&data[2]) * priv->scale; + accel.z = (float)adxl362_data(&data[4]) * priv->scale; + accel.temperature = + (float)adxl362_data(&data[6]) * ADXL362_TEMP_SCALE; + + priv->lower.push_event(priv->lower.priv, &accel, sizeof(accel)); + } + + /* Sleeping thread before fetching the next sensor data */ + + nxsig_usleep(priv->interval); + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: adxl362_register + * + * Description: + * Register the ADXL362 character device as 'devpath' + * + * Input Parameters: + * devno - Sensor device number. + * dev - An instance of the SPI or I2C interface to use to communicate + * with ADXL362 + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int adxl362_register(int devno, FAR struct spi_dev_s *spi) +{ + FAR struct adxl362_sensor_s *priv; + int ret; +#ifdef CONFIG_SENSORS_ADXL362_POLL + FAR char *argv[2]; + char arg1[32]; +#endif + + /* Sanity check */ + + DEBUGASSERT(spi != NULL); + + /* Initialize the ADXL362 device structure */ + + priv = kmm_zalloc(sizeof(struct adxl362_sensor_s)); + if (priv == NULL) + { + return -ENOMEM; + } + + priv->spi = spi; + priv->lower.ops = &g_adxl362_accel_ops; + priv->lower.type = SENSOR_TYPE_ACCELEROMETER; + priv->lower.nbuffer = 1; + priv->scale = (CONSTANTS_ONE_G / 1000.0f); + priv->devno = devno; +#ifdef CONFIG_SENSORS_ADXL362_POLL + priv->enabled = false; + priv->interval = CONFIG_SENSORS_ADXL362_POLL_INTERVAL; + + nxsem_init(&priv->run, 0, 0); +#endif + + /* Read and verify the deviceid */ + + ret = adxl362_checkid(priv); + if (ret < 0) + { + snerr("Wrong Device ID!\n"); + kmm_free(priv); + return ret; + } + + /* Soft reset */ + + adxl362_reset(priv); + + /* Register the character driver */ + + ret = sensor_register(&priv->lower, devno); + if (ret < 0) + { + snerr("Failed to register accel driver: %d\n", ret); + kmm_free(priv); + } + +#ifdef CONFIG_SENSORS_ADXL362_POLL + /* Create thread for polling sensor data */ + + snprintf(arg1, 16, "%p", priv); + argv[0] = arg1; + argv[1] = NULL; + + ret = kthread_create("adxl362_thread", SCHED_PRIORITY_DEFAULT, + CONFIG_SENSORS_ADXL362_THREAD_STACKSIZE, + adxl362_thread, + argv); + if (ret < 0) + { + kmm_free(priv); + } +#endif + + return ret; +} diff --git a/drivers/sensors/adxl372.c b/drivers/sensors/adxl372.c index a380fd7094de5..95eb9d01ec533 100644 --- a/drivers/sensors/adxl372.c +++ b/drivers/sensors/adxl372.c @@ -225,7 +225,7 @@ static uint8_t adxl372_read_register(FAR struct adxl372_dev_s *dev, /* Transmit the register address from where we want to read. */ - SPI_SEND(dev->spi, reg_addr | ADXL372_READ); + SPI_SEND(dev->spi, (reg_addr << 1) | ADXL372_READ); /* Write an idle byte while receiving the requested data */ @@ -266,7 +266,7 @@ static void adxl372_read_registerblk(FAR struct adxl372_dev_s *dev, /* Transmit the register address from where we want to start reading */ - SPI_SEND(dev->spi, reg_addr | ADXL372_READ); + SPI_SEND(dev->spi, (reg_addr << 1) | ADXL372_READ); /* Write idle bytes while receiving the requested data */ @@ -306,7 +306,7 @@ static void adxl372_write_register(FAR struct adxl372_dev_s *dev, /* Transmit the register address to where we want to write */ - SPI_SEND(dev->spi, reg_addr | ADXL372_WRITE); + SPI_SEND(dev->spi, (reg_addr << 1) | ADXL372_WRITE); /* Transmit the content which should be written into the register */ @@ -345,7 +345,7 @@ static void adxl372_write_registerblk(FAR struct adxl372_dev_s *dev, /* Transmit the register address to where we want to start writing */ - SPI_SEND(dev->spi, reg_addr | ADXL372_WRITE); + SPI_SEND(dev->spi, (reg_addr << 1) | ADXL372_WRITE); /* Transmit the content which should be written in the register block */ diff --git a/drivers/sensors/adxl372_uorb.c b/drivers/sensors/adxl372_uorb.c new file mode 100644 index 0000000000000..cbfe7a0f43306 --- /dev/null +++ b/drivers/sensors/adxl372_uorb.c @@ -0,0 +1,615 @@ +/**************************************************************************** + * drivers/sensors/adxl372_uorb.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CONSTANTS_ONE_G 9.8f + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct adxl372_sensor_s +{ + struct sensor_lowerhalf_s lower; + FAR struct spi_dev_s *spi; + float scale; + int devno; +#ifdef CONFIG_SENSORS_ADXL372_POLL + bool enabled; + unsigned long interval; + sem_t run; +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static uint8_t adxl372_getreg8(FAR struct adxl372_sensor_s *priv, + uint8_t regaddr); +static void adxl372_putreg8(FAR struct adxl372_sensor_s *priv, + uint8_t regaddr, uint8_t regval); +static void adxl372_getregs(FAR struct adxl372_sensor_s *priv, + uint8_t regaddr, FAR uint8_t *regval, int len); +static int16_t adxl372_data(FAR uint8_t *data); +static int adxl372_checkid(FAR struct adxl372_sensor_s *priv); +static void adxl372_start(FAR struct adxl372_sensor_s *priv); +static void adxl372_stop(FAR struct adxl372_sensor_s *priv); + +/* Sensor ops functions */ + +static int adxl372_activate(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + bool enable); +static int adxl372_set_interval(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR unsigned long *period_us); +#ifndef CONFIG_SENSORS_ADXL372_POLL +static int adxl372_fetch(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR char *buffer, size_t buflen); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct sensor_ops_s g_adxl372_accel_ops = +{ + NULL, /* open */ + NULL, /* close */ + adxl372_activate, + adxl372_set_interval, + NULL, /* batch */ +#ifdef CONFIG_SENSORS_ADXL372_POLL + NULL, /* fetch */ +#else + adxl372_fetch, +#endif + NULL, /* selftest */ + NULL, /* set_calibvalue */ + NULL, /* calibrate */ + NULL /* control */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: adxl372_getreg8 + * + * Description: + * Read from an 8-bit ADXL372 register + * + ****************************************************************************/ + +static uint8_t adxl372_getreg8(FAR struct adxl372_sensor_s *priv, + uint8_t regaddr) +{ + uint8_t regval = 0; + + SPI_LOCK(priv->spi, true); + + SPI_SETFREQUENCY(priv->spi, ADXL372_SPI_FREQUENCY); + SPI_SETMODE(priv->spi, ADXL372_SPI_MODE); + + /* Select the ADXL372 */ + + SPI_SELECT(priv->spi, SPIDEV_ACCELEROMETER(priv->devno), true); + + /* Send register to read and get the next byte */ + + SPI_SEND(priv->spi, (regaddr << 1) | ADXL372_READ); + SPI_RECVBLOCK(priv->spi, ®val, 1); + + /* Deselect the ADXL372 */ + + SPI_SELECT(priv->spi, SPIDEV_ACCELEROMETER(priv->devno), false); + + /* Unlock bus */ + + SPI_LOCK(priv->spi, false); + + return regval; +} + +/**************************************************************************** + * Name: adxl372_putreg8 + * + * Description: + * Write a value to an 8-bit ADXL372 register + * + ****************************************************************************/ + +static void adxl372_putreg8(FAR struct adxl372_sensor_s *priv, + uint8_t regaddr, uint8_t regval) +{ + SPI_LOCK(priv->spi, true); + + SPI_SETFREQUENCY(priv->spi, ADXL372_SPI_FREQUENCY); + SPI_SETMODE(priv->spi, ADXL372_SPI_MODE); + + /* Select the ADXL372 */ + + SPI_SELECT(priv->spi, SPIDEV_ACCELEROMETER(priv->devno), true); + + /* Send register address and set the value */ + + SPI_SEND(priv->spi, (regaddr << 1) | ADXL372_WRITE); + SPI_SEND(priv->spi, regval); + + /* Deselect the ADXL372 */ + + SPI_SELECT(priv->spi, SPIDEV_ACCELEROMETER(priv->devno), false); + + /* Unlock bus */ + + SPI_LOCK(priv->spi, false); +} + +/**************************************************************************** + * Name: adxl372_getregs + * + * Description: + * Read bytes from specified regaddr + * + ****************************************************************************/ + +static void adxl372_getregs(FAR struct adxl372_sensor_s *priv, + uint8_t regaddr, FAR uint8_t *regval, int len) +{ + /* If SPI bus is shared then lock and configure it */ + + SPI_LOCK(priv->spi, true); + + SPI_SETFREQUENCY(priv->spi, ADXL372_SPI_FREQUENCY); + SPI_SETMODE(priv->spi, ADXL372_SPI_MODE); + + /* Select the ADXL372 */ + + SPI_SELECT(priv->spi, SPIDEV_ACCELEROMETER(priv->devno), true); + + /* Send register to read and get the next 2 bytes */ + + SPI_SEND(priv->spi, (regaddr << 1) | ADXL372_READ); + SPI_RECVBLOCK(priv->spi, regval, len); + + /* Deselect the ADXL372 */ + + SPI_SELECT(priv->spi, SPIDEV_ACCELEROMETER(priv->devno), false); + + /* Unlock bus */ + + SPI_LOCK(priv->spi, false); +} + +/**************************************************************************** + * Name: adxl372_data + ****************************************************************************/ + +static int16_t adxl372_data(FAR uint8_t *data) +{ + return ((int16_t)(((data[0] << 8) | (data[1] & 0xf0)))) >> 4; +} + +/**************************************************************************** + * Name: adxl372_checkid + * + * Description: + * Read and verify the ADXL372 chip ID + * + ****************************************************************************/ + +static int adxl372_checkid(FAR struct adxl372_sensor_s *priv) +{ + uint8_t id = 0; + + id = adxl372_getreg8(priv, ADXL372_DEVID_AD); + if (id != ADXL372_DEVID_AD_VALUE) + { + snerr("Wrong AD! %02x\n", id); + return -ENODEV; + } + + id = adxl372_getreg8(priv, ADXL372_DEVID_MST); + if (id != ADXL372_DEVID_MST_VALUE) + { + snerr("Wrong MST! %02x\n", id); + return -ENODEV; + } + + id = adxl372_getreg8(priv, ADXL372_PARTID); + if (id != ADXL372_PARTID_VALUE) + { + snerr("Wrong PARTID! %02x\n", id); + return -ENODEV; + } + + return OK; +} + +/**************************************************************************** + * Name: adxl372_start + ****************************************************************************/ + +static void adxl372_start(FAR struct adxl372_sensor_s *priv) +{ + adxl372_putreg8(priv, ADXL372_POWER_CTL, + ADXL372_POWER_HPF_DISABLE | + ADXL372_POWER_MODE_MEASURE); +} + +/**************************************************************************** + * Name: adxl372_stop + ****************************************************************************/ + +static void adxl372_stop(FAR struct adxl372_sensor_s *priv) +{ + adxl372_putreg8(priv, ADXL372_POWER_CTL, 0); +} + +/**************************************************************************** + * Name: adxl372_reset + ****************************************************************************/ + +static void adxl372_reset(FAR struct adxl372_sensor_s *priv) +{ + int wdcnt = 10; + + /* Set stanby mode */ + + adxl372_putreg8(priv, ADXL372_POWER_CTL, 0); + + /* Wait for boot to finish (15 ms error timeout) */ + + up_mdelay(5); + while (wdcnt > 0 && (0 != adxl372_getreg8(priv, ADXL372_RESET))) + { + up_mdelay(1); + wdcnt--; + } + + /* Reset ADXL372 Accelerometer. Write only. Begin a boot. */ + + adxl372_putreg8(priv, ADXL372_RESET_VALUE, ADXL372_RESET); + + /* Wait for boot to finish (15 ms error timeout) */ + + up_mdelay(5); + wdcnt = 10; + while (wdcnt > 0 && (0 != adxl372_getreg8(priv, ADXL372_RESET))) + { + up_mdelay(1); + wdcnt--; + } +} + +/**************************************************************************** + * Name: adxl372_activate + * + * Description: + * Enable or disable sensor device. when enable sensor, sensor will + * work in current mode(if not set, use default mode). when disable + * sensor, it will disable sense path and stop convert. + * + * Input Parameters: + * lower - The instance of lower half sensor driver. + * filep - The pointer of file, represents each user using the sensor. + * enable - true(enable) and false(disable). + * + * Returned Value: + * Return 0 if the driver was success; A negated errno + * value is returned on any failure. + * + * Assumptions/Limitations: + * none. + * + ****************************************************************************/ + +static int adxl372_activate(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + bool enable) +{ + FAR struct adxl372_sensor_s *priv = (FAR struct adxl372_sensor_s *)lower; +#ifdef CONFIG_SENSORS_ADXL372_POLL + bool start_thread = false; +#endif + + if (enable) + { +#ifdef CONFIG_SENSORS_ADXL372_POLL + if (!priv->enabled) + { + start_thread = true; + } +#endif + + adxl372_start(priv); + } + else + { + adxl372_stop(priv); + } + +#ifdef CONFIG_SENSORS_ADXL372_POLL + priv->enabled = enable; + + if (start_thread) + { + /* Wake up the thread */ + + nxsem_post(&priv->run); + } +#endif + + return OK; +} + +/**************************************************************************** + * Name: adxl372_set_interval + * + * Description: + * Set the sensor output data period in microseconds for a given sensor. + * If *period_us > max_delay it will be truncated to max_delay and if + * *period_us < min_delay it will be replaced by min_delay. + * + * Input Parameters: + * lower - The instance of lower half sensor driver. + * filep - The pointer of file, represents each user using the sensor. + * period_us - The time between report data, in us. It may by overwrite + * by lower half driver. + * + * Returned Value: + * Return 0 if the driver was success; A negated errno + * value is returned on any failure. + * + * Assumptions/Limitations: + * none. + * + ****************************************************************************/ + +static int adxl372_set_interval(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR unsigned long *period_us) +{ +#ifdef CONFIG_SENSORS_ADXL372_POLL + FAR struct adxl372_sensor_s *priv = (FAR struct adxl372_sensor_s *)lower; + + priv->interval = *period_us; +#endif + + return OK; +} + +#ifndef CONFIG_SENSORS_ADXL372_POLL +/**************************************************************************** + * Name: adxl372_fetch + ****************************************************************************/ + +static int adxl372_fetch(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, FAR char *buffer, + size_t buflen) +{ + FAR struct adxl372_sensor_s *priv = (FAR struct adxl372_sensor_s *)lower; + struct sensor_accel accel; + uint8_t data[6]; + + /* Wait for data ready */ + + while (!(adxl372_getreg8(priv, ADXL372_STATUS) & 0x01)); + + /* Get data */ + + adxl372_getregs(priv, ADXL372_XDATA_H, (FAR uint8_t *)data, 6); + + accel.timestamp = sensor_get_timestamp(); + accel.x = (float)adxl372_data(&data[0]) * priv->scale; + accel.y = (float)adxl372_data(&data[2]) * priv->scale; + accel.z = (float)adxl372_data(&data[4]) * priv->scale; + accel.temperature = 0; + + memcpy(buffer, &accel, sizeof(accel)); + + return sizeof(accel); +} +#endif + +#ifdef CONFIG_SENSORS_ADXL372_POLL +/**************************************************************************** + * Name: adxl372_thread + * + * Description: Thread for performing interval measurement cycle and data + * read. + * + * Parameter: + * argc - Number opf arguments + * argv - Pointer to argument list + * + ****************************************************************************/ + +static int adxl372_thread(int argc, FAR char **argv) +{ + FAR struct adxl372_sensor_s *priv + = (FAR struct adxl372_sensor_s *)((uintptr_t)strtoul(argv[1], NULL, + 16)); + struct sensor_accel accel; + uint8_t data[6]; + int ret; + + while (true) + { + if ((!priv->enabled)) + { + /* Waiting to be woken up */ + + ret = nxsem_wait(&priv->run); + if (ret < 0) + { + continue; + } + } + + /* Read accel */ + + if (priv->enabled) + { + /* Wait for data ready */ + + while (!(adxl372_getreg8(priv, ADXL372_STATUS) & 0x01)); + + adxl372_getregs(priv, ADXL372_XDATA_H, (FAR uint8_t *)data, 6); + + accel.timestamp = sensor_get_timestamp(); + accel.x = (float)adxl372_data(&data[0]) * priv->scale; + accel.y = (float)adxl372_data(&data[2]) * priv->scale; + accel.z = (float)adxl372_data(&data[4]) * priv->scale; + accel.temperature = 0; + + priv->lower.push_event(priv->lower.priv, &accel, sizeof(accel)); + } + + /* Sleeping thread before fetching the next sensor data */ + + nxsig_usleep(priv->interval); + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: adxl372_register + * + * Description: + * Register the ADXL372 character device as 'devpath' + * + * Input Parameters: + * devno - Sensor device number. + * dev - An instance of the SPI or I2C interface to use to communicate + * with ADXL372 + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int adxl372_register_uorb(int devno, FAR struct spi_dev_s *spi) +{ + FAR struct adxl372_sensor_s *priv; + int ret; +#ifdef CONFIG_SENSORS_ADXL372_POLL + FAR char *argv[2]; + char arg1[32]; +#endif + + /* Sanity check */ + + DEBUGASSERT(spi != NULL); + + /* Initialize the ADXL372 device structure */ + + priv = kmm_zalloc(sizeof(struct adxl372_sensor_s)); + if (priv == NULL) + { + return -ENOMEM; + } + + priv->spi = spi; + priv->lower.ops = &g_adxl372_accel_ops; + priv->lower.type = SENSOR_TYPE_ACCELEROMETER; + priv->lower.nbuffer = 1; + priv->scale = (CONSTANTS_ONE_G / 10.0f); + priv->devno = devno; +#ifdef CONFIG_SENSORS_ADXL372_POLL + priv->enabled = false; + priv->interval = CONFIG_SENSORS_ADXL372_POLL_INTERVAL; + + nxsem_init(&priv->run, 0, 0); +#endif + + /* Read and verify the deviceid */ + + ret = adxl372_checkid(priv); + if (ret < 0) + { + snerr("Wrong Device ID!\n"); + kmm_free(priv); + return ret; + } + + /* Reset device */ + + adxl372_reset(priv); + + /* Register the character driver */ + + ret = sensor_register(&priv->lower, devno); + if (ret < 0) + { + snerr("Failed to register accel driver: %d\n", ret); + kmm_free(priv); + } + +#ifdef CONFIG_SENSORS_ADXL372_POLL + /* Create thread for polling sensor data */ + + snprintf(arg1, 16, "%p", priv); + argv[0] = arg1; + argv[1] = NULL; + + ret = kthread_create("adxl372_thread", SCHED_PRIORITY_DEFAULT, + CONFIG_SENSORS_ADXL372_THREAD_STACKSIZE, + adxl372_thread, + argv); + if (ret < 0) + { + kmm_free(priv); + } +#endif + + return ret; +} diff --git a/drivers/sensors/ak09912.c b/drivers/sensors/ak09912.c index fbe91bbeec415..2c2c9102650e8 100644 --- a/drivers/sensors/ak09912.c +++ b/drivers/sensors/ak09912.c @@ -85,7 +85,7 @@ * The unit is 10 millisecond. */ -#define AK09912_POLLING_TIMEOUT (1) // 10 ms +#define AK09912_POLLING_TIMEOUT (1) /* 10 ms */ /* The parameter for compensating. */ diff --git a/drivers/sensors/bh1749nuc.c b/drivers/sensors/bh1749nuc.c index 8c1a91cad4963..d9405fb1d832a 100644 --- a/drivers/sensors/bh1749nuc.c +++ b/drivers/sensors/bh1749nuc.c @@ -24,66 +24,7 @@ #include -#include -#include -#include -#include - -#include -#include - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define BH1749NUC_I2C_FREQ 400000 - -#define BH1749NUC_MANUFACTID 0xE0 /* Manufact ID */ -#define BH1749NUC_PARTID 0x0D /* Part ID */ - -/* BH1749NUC Registers */ - -#define BH1749NUC_SYSTEM_CONTROL 0x40 -#define BH1749NUC_MODE_CONTROL1 0x41 -#define BH1749NUC_MODE_CONTROL2 0x42 -#define BH1749NUC_RED_DATA_LSB 0x50 -#define BH1749NUC_GREEN_DATA_LSB 0x52 -#define BH1749NUC_BLUE_DATA_LSB 0x54 -#define BH1749NUC_IR_DATA_LSB 0x58 -#define BH1749NUC_GREEN2_DATA_LSB 0x5a -#define BH1749NUC_MANUFACTURER_ID 0x92 - -/* Register SYSTEM_CONTROL */ - -#define BH1749NUC_SYSTEM_CONTROL_SW_RESET (1 << 7) -#define BH1749NUC_SYSTEM_CONTROL_INT_RESET (1 << 6) - -/* Register MODE_CONTROL1 */ - -#define BH1749NUC_MODE_CONTROL1_IR_GAIN_X1 (0x20) -#define BH1749NUC_MODE_CONTROL1_IR_GAIN_X32 (0x60) -#define BH1749NUC_MODE_CONTROL1_RGB_GAIN_X1 (0x08) -#define BH1749NUC_MODE_CONTROL1_RGB_GAIN_X32 (0x18) -#define BH1749NUC_MODE_CONTROL1_MEAS_TIME160MS (0x02) - -/* Register MODE_CONTROL2 */ - -#define BH1749NUC_MODE_CONTROL2_RGBI_EN (1 << 4) - -/**************************************************************************** - * Private Type Definitions - ****************************************************************************/ - -/* Structure for bh1749nuc device */ - -struct bh1749nuc_dev_s -{ - FAR struct i2c_master_s *i2c; /* I2C interface */ - int freq; /* Frequency */ - uint8_t addr; /* I2C address */ -}; +#include "bh1749nuc_base.h" /**************************************************************************** * Private Function Prototypes @@ -120,146 +61,6 @@ static const struct file_operations g_bh1749nucfops = * Private Functions ****************************************************************************/ -/**************************************************************************** - * Name: bh1749nuc_getreg8 - * - * Description: - * Read from an 8-bit BH1749NUC register - * - ****************************************************************************/ - -static uint8_t bh1749nuc_getreg8(FAR struct bh1749nuc_dev_s *priv, - uint8_t regaddr) -{ - struct i2c_msg_s msg[2]; - uint8_t regval = 0; - int ret; - - msg[0].frequency = priv->freq; - msg[0].addr = priv->addr; - msg[0].flags = I2C_M_NOSTOP; - msg[0].buffer = ®addr; - msg[0].length = 1; - - msg[1].frequency = priv->freq; - msg[1].addr = priv->addr; - msg[1].flags = I2C_M_READ; - msg[1].buffer = ®val; - msg[1].length = 1; - - ret = I2C_TRANSFER(priv->i2c, msg, 2); - if (ret < 0) - { - snerr("I2C_TRANSFER failed: %d\n", ret); - } - - return regval; -} - -/**************************************************************************** - * Name: bh1749nuc_read16 - * - * Description: - * Read 16-bit register - * - ****************************************************************************/ - -static uint16_t bh1749nuc_read16(FAR struct bh1749nuc_dev_s *priv, - uint8_t regaddr) -{ - struct i2c_msg_s msg[2]; - uint8_t regval[2]; - int ret; - - msg[0].frequency = priv->freq; - msg[0].addr = priv->addr; - msg[0].flags = I2C_M_NOSTOP; - msg[0].buffer = ®addr; - msg[0].length = 1; - - msg[1].frequency = priv->freq; - msg[1].addr = priv->addr; - msg[1].flags = I2C_M_READ; - msg[1].buffer = (uint8_t *)®val; - msg[1].length = 2; - - ret = I2C_TRANSFER(priv->i2c, msg, 2); - if (ret < 0) - { - snerr("I2C_TRANSFER failed: %d\n", ret); - } - - return regval[1] << 8 | regval[0] << 0; -} - -/**************************************************************************** - * Name: bh1749nuc_putreg8 - * - * Description: - * Write to an 8-bit BH1749NUC register - * - ****************************************************************************/ - -static void bh1749nuc_putreg8(FAR struct bh1749nuc_dev_s *priv, - uint8_t regaddr, uint8_t regval) -{ - struct i2c_msg_s msg[2]; - uint8_t txbuffer[2]; - int ret; - - txbuffer[0] = regaddr; - txbuffer[1] = regval; - - msg[0].frequency = priv->freq; - msg[0].addr = priv->addr; - msg[0].flags = 0; - msg[0].buffer = txbuffer; - msg[0].length = 2; - - ret = I2C_TRANSFER(priv->i2c, msg, 1); - if (ret < 0) - { - snerr("I2C_TRANSFER failed: %d\n", ret); - } -} - -/**************************************************************************** - * Name: bh1749nuc_checkid - * - * Description: - * Read and verify the BH1749NUC chip ID - * - ****************************************************************************/ - -static int bh1749nuc_checkid(FAR struct bh1749nuc_dev_s *priv) -{ - uint8_t id; - - /* Read Manufact ID */ - - id = bh1749nuc_getreg8(priv, BH1749NUC_MANUFACTURER_ID); - if (id != BH1749NUC_MANUFACTID) - { - /* Manufact ID is not Correct */ - - snerr("Wrong Manufact ID! %02x\n", id); - return -ENODEV; - } - - /* Read Part ID */ - - id = bh1749nuc_getreg8(priv, BH1749NUC_SYSTEM_CONTROL); - if ((id & 0x3f) != BH1749NUC_PARTID) - { - /* Part ID is not Correct */ - - snerr("Wrong Part ID! %02x\n", id); - return -ENODEV; - } - - return OK; -} - /**************************************************************************** * Name: bh1749nuc_open * @@ -402,7 +203,7 @@ int bh1749nuc_register(FAR const char *devpath, FAR struct i2c_master_s *i2c, priv->i2c = i2c; priv->addr = addr; - priv->freq = BH1749NUC_I2C_FREQ; + priv->freq = CONFIG_BH1749NUC_I2C_FREQUENCY; /* Check Device ID */ diff --git a/drivers/sensors/bh1749nuc_base.c b/drivers/sensors/bh1749nuc_base.c new file mode 100644 index 0000000000000..01e86ad87574a --- /dev/null +++ b/drivers/sensors/bh1749nuc_base.c @@ -0,0 +1,173 @@ +/**************************************************************************** + * drivers/sensors/bh1749nuc_base.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "bh1749nuc_base.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: bh1749nuc_getreg8 + * + * Description: + * Read from an 8-bit BH1749NUC register + * + ****************************************************************************/ + +uint8_t bh1749nuc_getreg8(FAR struct bh1749nuc_dev_s *priv, uint8_t regaddr) +{ + struct i2c_msg_s msg[2]; + uint8_t regval = 0; + int ret; + + msg[0].frequency = priv->freq; + msg[0].addr = priv->addr; + msg[0].flags = I2C_M_NOSTOP; + msg[0].buffer = ®addr; + msg[0].length = 1; + + msg[1].frequency = priv->freq; + msg[1].addr = priv->addr; + msg[1].flags = I2C_M_READ; + msg[1].buffer = ®val; + msg[1].length = 1; + + ret = I2C_TRANSFER(priv->i2c, msg, 2); + if (ret < 0) + { + snerr("I2C_TRANSFER failed: %d\n", ret); + } + + return regval; +} + +/**************************************************************************** + * Name: bh1749nuc_read16 + * + * Description: + * Read 16-bit register + * + ****************************************************************************/ + +uint16_t bh1749nuc_read16(FAR struct bh1749nuc_dev_s *priv, uint8_t regaddr) +{ + struct i2c_msg_s msg[2]; + uint8_t regval[2]; + int ret; + + msg[0].frequency = priv->freq; + msg[0].addr = priv->addr; + msg[0].flags = I2C_M_NOSTOP; + msg[0].buffer = ®addr; + msg[0].length = 1; + + msg[1].frequency = priv->freq; + msg[1].addr = priv->addr; + msg[1].flags = I2C_M_READ; + msg[1].buffer = (uint8_t *)®val; + msg[1].length = 2; + + ret = I2C_TRANSFER(priv->i2c, msg, 2); + if (ret < 0) + { + snerr("I2C_TRANSFER failed: %d\n", ret); + } + + return regval[1] << 8 | regval[0] << 0; +} + +/**************************************************************************** + * Name: bh1749nuc_putreg8 + * + * Description: + * Write to an 8-bit BH1749NUC register + * + ****************************************************************************/ + +void bh1749nuc_putreg8(FAR struct bh1749nuc_dev_s *priv, + uint8_t regaddr, uint8_t regval) +{ + struct i2c_msg_s msg[2]; + uint8_t txbuffer[2]; + int ret; + + txbuffer[0] = regaddr; + txbuffer[1] = regval; + + msg[0].frequency = priv->freq; + msg[0].addr = priv->addr; + msg[0].flags = 0; + msg[0].buffer = txbuffer; + msg[0].length = 2; + + ret = I2C_TRANSFER(priv->i2c, msg, 1); + if (ret < 0) + { + snerr("I2C_TRANSFER failed: %d\n", ret); + } +} + +/**************************************************************************** + * Name: bh1749nuc_checkid + * + * Description: + * Read and verify the BH1749NUC chip ID + * + ****************************************************************************/ + +int bh1749nuc_checkid(FAR struct bh1749nuc_dev_s *priv) +{ + uint8_t id; + + /* Read Manufact ID */ + + id = bh1749nuc_getreg8(priv, BH1749NUC_MANUFACTURER_ID); + if (id != BH1749NUC_MANUFACTID) + { + /* Manufact ID is not Correct */ + + snerr("Wrong Manufact ID! %02x\n", id); + return -ENODEV; + } + + /* Read Part ID */ + + id = bh1749nuc_getreg8(priv, BH1749NUC_SYSTEM_CONTROL); + if ((id & 0x3f) != BH1749NUC_PARTID) + { + /* Part ID is not Correct */ + + snerr("Wrong Part ID! %02x\n", id); + return -ENODEV; + } + + return OK; +} diff --git a/drivers/sensors/bh1749nuc_base.h b/drivers/sensors/bh1749nuc_base.h new file mode 100644 index 0000000000000..838ceff125f49 --- /dev/null +++ b/drivers/sensors/bh1749nuc_base.h @@ -0,0 +1,100 @@ +/**************************************************************************** + * drivers/sensors/bh1749nuc_base.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_SENSORS_BH1749NUC_BASE_H +#define __INCLUDE_NUTTX_SENSORS_BH1749NUC_BASE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define BH1749NUC_MANUFACTID 0xE0 /* Manufact ID */ +#define BH1749NUC_PARTID 0x0D /* Part ID */ + +/* BH1749NUC Registers */ + +#define BH1749NUC_SYSTEM_CONTROL 0x40 +#define BH1749NUC_MODE_CONTROL1 0x41 +#define BH1749NUC_MODE_CONTROL2 0x42 +#define BH1749NUC_RED_DATA_LSB 0x50 +#define BH1749NUC_GREEN_DATA_LSB 0x52 +#define BH1749NUC_BLUE_DATA_LSB 0x54 +#define BH1749NUC_IR_DATA_LSB 0x58 +#define BH1749NUC_GREEN2_DATA_LSB 0x5a +#define BH1749NUC_MANUFACTURER_ID 0x92 + +/* Register SYSTEM_CONTROL */ + +#define BH1749NUC_SYSTEM_CONTROL_SW_RESET (1 << 7) +#define BH1749NUC_SYSTEM_CONTROL_INT_RESET (1 << 6) + +/* Register MODE_CONTROL1 */ + +#define BH1749NUC_MODE_CONTROL1_IR_GAIN_X1 (0x20) +#define BH1749NUC_MODE_CONTROL1_IR_GAIN_X32 (0x60) +#define BH1749NUC_MODE_CONTROL1_RGB_GAIN_X1 (0x08) +#define BH1749NUC_MODE_CONTROL1_RGB_GAIN_X32 (0x18) +#define BH1749NUC_MODE_CONTROL1_MEAS_TIME160MS (0x02) + +/* Register MODE_CONTROL2 */ + +#define BH1749NUC_MODE_CONTROL2_RGBI_EN (1 << 4) +#define BH1749NUC_MODE_CONTROL2_VALID (1 << 7) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Structure for bh1749nuc device */ + +struct bh1749nuc_dev_s +{ + FAR struct i2c_master_s *i2c; /* I2C interface */ + int freq; /* Frequency */ + uint8_t addr; /* I2C address */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +uint8_t bh1749nuc_getreg8(FAR struct bh1749nuc_dev_s *priv, uint8_t regaddr); +uint16_t bh1749nuc_read16(FAR struct bh1749nuc_dev_s *priv, uint8_t regaddr); +void bh1749nuc_putreg8(FAR struct bh1749nuc_dev_s *priv, + uint8_t regaddr, uint8_t regval); +int bh1749nuc_checkid(FAR struct bh1749nuc_dev_s *priv); + +#endif /* __INCLUDE_NUTTX_SENSORS_BH1749NUC_BASE_H */ diff --git a/drivers/sensors/bh1749nuc_uorb.c b/drivers/sensors/bh1749nuc_uorb.c new file mode 100644 index 0000000000000..53f3debb84125 --- /dev/null +++ b/drivers/sensors/bh1749nuc_uorb.c @@ -0,0 +1,540 @@ +/**************************************************************************** + * drivers/sensors/bh1749nuc_uorb.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include + +#include "bh1749nuc_base.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Type Definitions + ****************************************************************************/ + +enum bh1749nuc_idx_e +{ + BH1749NUC_RGB_IDX = 0, + BH1749NUC_IR_IDX, + BH1749NUC_MAX_IDX +}; + +struct bh1749nuc_sensor_dev_s; +struct bh1749nuc_sensor_s +{ + struct sensor_lowerhalf_s lower; + int gain; + FAR struct bh1749nuc_sensor_dev_s *dev; +#ifdef CONFIG_SENSORS_BH1749NUC_POLL + unsigned long interval; + uint64_t last_update; +#endif + bool enabled; +}; + +struct bh1749nuc_sensor_dev_s +{ + struct bh1749nuc_sensor_s priv[BH1749NUC_MAX_IDX]; + struct bh1749nuc_dev_s dev; + float scale_r; + float scale_g; + float scale_b; + float scale_ir; + mutex_t lock; +#ifdef CONFIG_SENSORS_BH1749NUC_POLL + sem_t run; +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int bh1749nuc_activate(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, bool enable); +#ifndef CONFIG_SENSORS_BH1749NUC_POLL +static int bh1749nuc_fetch(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR char *buffer, size_t buflen); +#endif +static int bh1749nuc_set_interval(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR unsigned long *period_us); +static int bh1749nuc_control(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct sensor_ops_s g_bh1749nuc_sensor_ops = +{ + NULL, /* open */ + NULL, /* close */ + bh1749nuc_activate, + bh1749nuc_set_interval, + NULL, /* batch */ +#ifdef CONFIG_SENSORS_BH1749NUC_POLL + NULL, /* fetch */ +#else + bh1749nuc_fetch, +#endif + NULL, /* selftest */ + NULL, /* set_calibvalue */ + NULL, /* calibrate */ + bh1749nuc_control +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: bh1749nuc_activate + ****************************************************************************/ + +static int bh1749nuc_activate(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, bool enable) +{ + FAR struct bh1749nuc_sensor_s *priv = NULL; + FAR struct bh1749nuc_dev_s *dev = NULL; + uint8_t val = 0; +#ifdef CONFIG_SENSORS_BH1749NUC_POLL + bool start_thread = false; +#endif + + /* Get dev */ + + priv = (FAR struct bh1749nuc_sensor_s *)lower; + dev = &priv->dev->dev; + + nxmutex_lock(&priv->dev->lock); + + if (enable) + { +#ifdef CONFIG_SENSORS_BH1749NUC_POLL + if (!priv->enabled) + { + start_thread = true; + priv->last_update = sensor_get_timestamp(); + } +#endif + + /* MODE_CONTROL1 */ + + val = (BH1749NUC_MODE_CONTROL1_MEAS_TIME160MS | + BH1749NUC_MODE_CONTROL1_IR_GAIN_X1 | + BH1749NUC_MODE_CONTROL1_RGB_GAIN_X1); + bh1749nuc_putreg8(dev, BH1749NUC_MODE_CONTROL1, val); + + /* MODE_CONTROL2 */ + + val = BH1749NUC_MODE_CONTROL2_RGBI_EN; + bh1749nuc_putreg8(dev, BH1749NUC_MODE_CONTROL2, val); + } + else + { + /* Stop sampling */ + + val = 0; + bh1749nuc_putreg8(dev, BH1749NUC_MODE_CONTROL2, val); + } + + priv->enabled = enable; + +#ifdef CONFIG_SENSORS_BH1749NUC_POLL + if (start_thread) + { + /* Wake up the thread */ + + nxsem_post(&priv->dev->run); + } +#endif + + nxmutex_unlock(&priv->dev->lock); + + return OK; +} + +#ifndef CONFIG_SENSORS_BH1749NUC_POLL +/**************************************************************************** + * Name: bh1749nuc_fetch + ****************************************************************************/ + +static int bh1749nuc_fetch(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR char *buffer, size_t buflen) +{ + FAR struct bh1749nuc_sensor_s *priv = NULL; + FAR struct bh1749nuc_dev_s *dev = NULL; + struct sensor_rgb rgb_data; + struct sensor_ir ir_data; + uint16_t tmp = 0; + uint64_t now = sensor_get_timestamp(); + int ret = 0; + + /* Get dev */ + + priv = (FAR struct bh1749nuc_sensor_s *)lower; + dev = &priv->dev->dev; + + nxmutex_lock(&priv->dev->lock); + + if (!priv->enabled) + { + ret = -EACCES; + goto errout; + } + + /* Get data without wait for VALID flag - otherwise the sensor freezes + * when we read RBG and IR data one after another + */ + + if (lower->type == SENSOR_TYPE_RGB) + { + if (buflen != sizeof(rgb_data)) + { + ret = -EINVAL; + goto errout; + } + + rgb_data.timestamp = now; + tmp = bh1749nuc_read16(dev, BH1749NUC_RED_DATA_LSB); + rgb_data.r = (tmp * priv->dev->scale_r); + tmp = bh1749nuc_read16(dev, BH1749NUC_GREEN_DATA_LSB); + rgb_data.g = (tmp * priv->dev->scale_g); + tmp = bh1749nuc_read16(dev, BH1749NUC_BLUE_DATA_LSB); + rgb_data.b = (tmp * priv->dev->scale_b); + + memcpy(buffer, &rgb_data, sizeof(rgb_data)); + ret = sizeof(rgb_data); + } + else if (lower->type == SENSOR_TYPE_IR) + { + if (buflen != sizeof(ir_data)) + { + ret = -EINVAL; + goto errout; + } + + ir_data.timestamp = now; + tmp = bh1749nuc_read16(dev, BH1749NUC_IR_DATA_LSB); + ir_data.ir = (tmp * priv->dev->scale_ir); + + memcpy(buffer, &ir_data, sizeof(ir_data)); + ret = sizeof(ir_data); + } + +errout: + nxmutex_unlock(&priv->dev->lock); + return ret; +} +#endif + +/**************************************************************************** + * Name: bh1749nuc_cotrol + ****************************************************************************/ + +static int bh1749nuc_control(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, int cmd, + unsigned long arg) +{ + FAR struct bh1749nuc_sensor_s *priv = NULL; + int ret = OK; + + priv = (FAR struct bh1749nuc_sensor_s *)lower; + UNUSED(priv); + + switch (cmd) + { + default: + { + snerr("ERROR: Unrecognized cmd: %d\n", cmd); + ret = -ENOTTY; + break; + } + } + + return ret; +} + +/**************************************************************************** + * Name: bh1749nuc_set_interval + ****************************************************************************/ + +static int bh1749nuc_set_interval(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR unsigned long *interval) +{ +#ifdef CONFIG_SENSORS_BH1749NUC_POLL + FAR struct bh1749nuc_sensor_s *priv = NULL; + + priv = (FAR struct bh1749nuc_sensor_s *)lower; + + priv->interval = *interval; +#endif + + return OK; +} + +#ifdef CONFIG_SENSORS_BH1749NUC_POLL +/**************************************************************************** + * Name: bh1749nuc_thread + * + * Description: Thread for performing interval measurement cycle and data + * read. + * + * Parameter: + * argc - Number opf arguments + * argv - Pointer to argument list + * + ****************************************************************************/ + +static int bh1749nuc_thread(int argc, FAR char **argv) +{ + FAR struct bh1749nuc_sensor_dev_s *dev = + (FAR struct bh1749nuc_sensor_dev_s *)((uintptr_t)strtoul(argv[1], NULL, + 16)); + FAR struct bh1749nuc_sensor_s *rgb = &dev->priv[BH1749NUC_RGB_IDX]; + FAR struct bh1749nuc_sensor_s *ir = &dev->priv[BH1749NUC_IR_IDX]; + struct sensor_rgb rgb_data; + struct sensor_ir ir_data; + uint64_t min_interval; + uint16_t tmp = 0; + uint64_t now = sensor_get_timestamp(); + int ret = 0; + + while (true) + { + if ((!rgb->enabled) && (!ir->enabled)) + { + /* Waiting to be woken up */ + + ret = nxsem_wait(&dev->run); + if (ret < 0) + { + continue; + } + } + + /* Wait for data */ + + while (!(bh1749nuc_getreg8(&dev->dev, BH1749NUC_MODE_CONTROL2) & + BH1749NUC_MODE_CONTROL2_VALID)); + + /* Get timestamp */ + + now = sensor_get_timestamp(); + + if (rgb->enabled) + { + rgb_data.timestamp = now; + tmp = bh1749nuc_read16(&dev->dev, BH1749NUC_RED_DATA_LSB); + rgb_data.r = (tmp * dev->scale_r); + tmp = bh1749nuc_read16(&dev->dev, BH1749NUC_GREEN_DATA_LSB); + rgb_data.g = (tmp * dev->scale_g); + tmp = bh1749nuc_read16(&dev->dev, BH1749NUC_BLUE_DATA_LSB); + rgb_data.b = (tmp * dev->scale_b); + + rgb->lower.push_event(rgb->lower.priv, + &rgb_data, sizeof(rgb_data)); + } + + if (ir->enabled) + { + ir_data.timestamp = now; + tmp = bh1749nuc_read16(&dev->dev, BH1749NUC_IR_DATA_LSB); + ir_data.ir = (tmp * dev->scale_ir); + + ir->lower.push_event(ir->lower.priv, + &ir_data, sizeof(ir_data)); + } + + /* Sleeping thread before fetching the next sensor data */ + + min_interval = MIN(rgb->interval, ir->interval); + nxsig_usleep(min_interval); + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: bh1749nuc_register_uorb + * + * Description: + * Register the BH1749NUC uorb device as 'devpath' + * + * Input Parameters: + * devno - The user specifies device number, from 0. + * config - device configuration + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int bh1749nuc_register_uorb(int devno, FAR struct bh1749nuc_config_s *config) +{ + FAR struct bh1749nuc_sensor_dev_s *dev = NULL; + FAR struct bh1749nuc_sensor_s *tmp = NULL; + int ret = OK; +#ifdef CONFIG_SENSORS_BH1749NUC_POLL + FAR char *argv[2]; + char arg1[32]; +#endif + + /* Without config info, we can't do anything. */ + + if (config == NULL) + { + return -EINVAL; + } + + /* Initialize the device structure. */ + + dev = kmm_malloc(sizeof(struct bh1749nuc_sensor_dev_s)); + if (dev == NULL) + { + snerr("ERROR: Failed to allocate bh1749nuc device instance\n"); + return -ENOMEM; + } + + memset(dev, 0, sizeof(struct bh1749nuc_sensor_dev_s)); + nxmutex_init(&dev->lock); +#ifdef CONFIG_SENSORS_BH1749NUC_POLL + nxsem_init(&dev->run, 0, 0); +#endif + + /* Configure dev */ + + dev->dev.i2c = config->i2c; + dev->dev.addr = config->addr; + dev->dev.freq = CONFIG_BH1749NUC_I2C_FREQUENCY; + + /* Check Device ID */ + + ret = bh1749nuc_checkid(&dev->dev); + if (ret < 0) + { + snerr("Failed to register driver: %d\n", ret); + return ret; + } + + /* Return data in lux unit for RGB and IR */ + + dev->scale_r = (20.0f / 71.0f) * (1e-6 / 1.46e-7); + dev->scale_g = (20.0f / 99.0f) * (1e-6 / 1.46e-7); + dev->scale_b = (20.0f / 70.0f) * (1e-6 / 1.46e-7); + dev->scale_ir = (20.0f / 25.0f) * (1e-6 / 1.46e-7); + + /* Register sensor */ + + tmp = &dev->priv[BH1749NUC_RGB_IDX]; + tmp->lower.type = SENSOR_TYPE_RGB; + tmp->lower.ops = &g_bh1749nuc_sensor_ops; + tmp->dev = dev; + tmp->gain = 1; +#ifdef CONFIG_SENSORS_BH1749NUC_POLL + tmp->enabled = false; + tmp->interval = CONFIG_SENSORS_BH1749NUC_POLL_INTERVAL; +#endif + + ret = sensor_register(&tmp->lower, devno); + if (ret < 0) + { + goto rgb_err; + } + + /* Register sensor */ + + tmp = &dev->priv[BH1749NUC_IR_IDX]; + tmp->lower.type = SENSOR_TYPE_IR; + tmp->lower.ops = &g_bh1749nuc_sensor_ops; + tmp->dev = dev; + tmp->gain = 1; +#ifdef CONFIG_SENSORS_BH1749NUC_POLL + tmp->enabled = false; + tmp->interval = CONFIG_SENSORS_BH1749NUC_POLL_INTERVAL; +#endif + + ret = sensor_register(&tmp->lower, devno); + if (ret < 0) + { + goto ir_err; + } + + /* SW Reset */ + + bh1749nuc_putreg8(&dev->dev, BH1749NUC_SYSTEM_CONTROL, + BH1749NUC_SYSTEM_CONTROL_SW_RESET); + +#ifdef CONFIG_SENSORS_BH1749NUC_POLL + /* Create thread for polling sensor data */ + + snprintf(arg1, 16, "%p", dev); + argv[0] = arg1; + argv[1] = NULL; + + ret = kthread_create("bh1749nuc_thread", SCHED_PRIORITY_DEFAULT, + CONFIG_SENSORS_BH1749NUC_THREAD_STACKSIZE, + bh1749nuc_thread, + argv); + if (ret < 0) + { + goto thr_err; + } +#endif + + return ret; + +#ifdef CONFIG_SENSORS_BH1749NUC_POLL + thr_err: +#endif + sensor_unregister(&dev->priv[BH1749NUC_IR_IDX].lower, devno); +ir_err: + sensor_unregister(&dev->priv[BH1749NUC_RGB_IDX].lower, devno); +rgb_err: + kmm_free(dev); + return ret; +} diff --git a/drivers/sensors/bmi160.c b/drivers/sensors/bmi160.c index 8635f2f4623f5..b50ba4537ff54 100644 --- a/drivers/sensors/bmi160.c +++ b/drivers/sensors/bmi160.c @@ -147,7 +147,7 @@ static ssize_t bmi160_read(FAR struct file *filep, FAR char *buffer, if (len < sizeof(struct accel_gyro_st_s)) { - snerr("Expected buffer size is %lu\n", sizeof(struct accel_gyro_st_s)); + snerr("Expected buffer size is %u\n", sizeof(struct accel_gyro_st_s)); return 0; } diff --git a/drivers/sensors/bmi160_base.c b/drivers/sensors/bmi160_base.c index 95600d89883f9..41b40b3120943 100644 --- a/drivers/sensors/bmi160_base.c +++ b/drivers/sensors/bmi160_base.c @@ -38,6 +38,25 @@ * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: bmi160_configspi + * + * Description: + * + ****************************************************************************/ + +#ifdef CONFIG_SENSORS_BMI160_SPI +static void bmi160_configspi(FAR struct spi_dev_s *spi) +{ + /* Configure SPI for the BMI160 */ + + SPI_SETMODE(spi, SPIDEV_MODE0); + SPI_SETBITS(spi, 8); + SPI_HWFEATURES(spi, 0); + SPI_SETFREQUENCY(spi, BMI160_SPI_MAXFREQUENCY); +} +#endif + /**************************************************************************** * Private Data ****************************************************************************/ diff --git a/drivers/sensors/bmi160_base.h b/drivers/sensors/bmi160_base.h index 4b91fa39b9b81..130233c9eecf0 100644 --- a/drivers/sensors/bmi160_base.h +++ b/drivers/sensors/bmi160_base.h @@ -240,22 +240,4 @@ void bmi160_getregs(FAR struct bmi160_dev_s *priv, uint8_t regaddr, int bmi160_checkid(FAR struct bmi160_dev_s *priv); -/**************************************************************************** - * Name: bmi160_configspi - * - * Description: - * - ****************************************************************************/ - -#ifdef CONFIG_SENSORS_BMI160_SPI -inline void bmi160_configspi(FAR struct spi_dev_s *spi) -{ - /* Configure SPI for the BMI160 */ - - SPI_SETMODE(spi, SPIDEV_MODE0); - SPI_SETBITS(spi, 8); - SPI_HWFEATURES(spi, 0); - SPI_SETFREQUENCY(spi, BMI160_SPI_MAXFREQUENCY); -} -#endif #endif /* __INCLUDE_NUTTX_SENSORS_BMI160_COMMOM_H */ diff --git a/drivers/sensors/bmi160_uorb.c b/drivers/sensors/bmi160_uorb.c index 38595f6b0f480..2eb5ef6309769 100644 --- a/drivers/sensors/bmi160_uorb.c +++ b/drivers/sensors/bmi160_uorb.c @@ -716,6 +716,10 @@ static int bmi160_register_gyro(int devno, return ret; } +/**************************************************************************** + * Public Functions + ****************************************************************************/ + /**************************************************************************** * Name: bmi160_register * diff --git a/drivers/sensors/bmi270.c b/drivers/sensors/bmi270.c index cbaf5de2f5cdb..6095898683271 100644 --- a/drivers/sensors/bmi270.c +++ b/drivers/sensors/bmi270.c @@ -37,197 +37,12 @@ # include #endif -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define BMI270_SPI_MAXFREQUENCY 10000000 -#define BMI270_I2C_FREQ 400000 - -#define DEVID 0x24 - -#define BMI270_CHIP_ID (0x00) /* Chip ID */ -#define BMI270_ERROR (0x02) /* Error register */ -#define BMI270_PMU_STAT (0x03) /* Current power mode */ -#define BMI270_DATA_0 (0x04) /* MAG X 7:0 (LSB) */ -#define BMI270_DATA_1 (0x05) /* MAG X 15:8 (MSB) */ -#define BMI270_DATA_2 (0x06) /* MAG Y 7:0 (LSB) */ -#define BMI270_DATA_3 (0x07) /* MAG Y 15:8 (MSB) */ -#define BMI270_DATA_4 (0x08) /* MAG Z 7:0 (LSB) */ -#define BMI270_DATA_5 (0x09) /* MAG Z 15:8 (MSB) */ -#define BMI270_DATA_6 (0x0A) /* RHALL 7:0 (LSB) */ -#define BMI270_DATA_7 (0x0B) /* RHALL 15:8 (MSB) */ -#define BMI270_DATA_8 (0x0C) /* GYR X 7:0 (LSB) */ -#define BMI270_DATA_9 (0x0D) /* GYR X 15:8 (MSB) */ -#define BMI270_DATA_10 (0x0E) /* GYR Y 7:0 (LSB) */ -#define BMI270_DATA_11 (0x0F) /* GYR Y 15:8 (MSB) */ -#define BMI270_DATA_12 (0x10) /* GYR Z 7:0 (LSB) */ -#define BMI270_DATA_13 (0x11) /* GYR Z 15:8 (MSB) */ -#define BMI270_DATA_14 (0x12) /* ACC X 7:0 (LSB) */ -#define BMI270_DATA_15 (0x13) /* ACC X 15:8 (MSB) */ -#define BMI270_DATA_16 (0x14) /* ACC Y 7:0 (LSB) */ -#define BMI270_DATA_17 (0x15) /* ACC Y 15:8 (MSB) */ -#define BMI270_DATA_18 (0x16) /* ACC Z 7:0 (LSB) */ -#define BMI270_DATA_19 (0x17) /* ACC Z 15:8 (MSB) */ -#define BMI270_SENSORTIME_0 (0x18) /* Sensor time 0 */ -#define BMI270_SENSORTIME_1 (0x19) /* Sensor time 1 */ -#define BMI270_SENSORTIME_2 (0x1A) /* Sensor time 2 */ -#define BMI270_EVENT (0x1B) /* Sensor event flags */ -#define BMI270_INTR_STAT_0 (0x1C) /* Interrupt status */ -#define BMI270_INTR_STAT_1 (0x1D) -#define BMI270_SC_OUT_0 (0x1E) /* Step counting value */ -#define BMI270_SC_OUT_1 (0x1f) /* Step counting value */ -#define BMI270_WR_GEST_ACT (0x20) /* Wrist gesture and activity detection */ -#define BMI270_INTERNAL_STAT (0x21) /* Internal status */ -#define BMI270_TEMPERATURE_0 (0x22) /* Temperature */ -#define BMI270_TEMPERATURE_1 (0x23) -#define BMI270_FIFO_LENGTH_0 (0x24) /* FIFO length */ -#define BMI270_FIFO_LENGTH_1 (0x25) -#define BMI270_FIFO_DATA (0x26) -#define BMI270_FEAT_PAGE (0x2f) /* Page number for feature configuration and output registers */ - /* TODO: Features 0x30-0x3f */ -#define BMI270_ACC_CONFIG (0x40) /* ACCEL config for ODR, bandwidth and undersampling */ -#define BMI270_ACC_RANGE (0x41) /* ACCEL range */ -#define BMI270_GYR_CONFIG (0x42) /* GYRO config for ODR and bandwidth */ -#define BMI270_GYR_RANGE (0x43) /* GYRO range */ -#define BMI270_AUX_CONFIG (0x44) /* AUX config for ODR*/ -#define BMI270_FIFO_DOWN (0x45) /* GYRO and ACCEL downsampling rates for FIFO */ -#define BMI270_FIFO_WTM_0 (0x46) /* FIFO Watermark level */ -#define BMI270_FIFO_WTM_1 (0x47) /* FIFO Watermark level */ -#define BMI270_FIFO_CONFIG_0 (0x48) /* FIFO config */ -#define BMI270_FIFO_CONFIG_1 (0x49) -#define BMI270_SATURATION (0x4A) /* Saturation */ -#define BMI270_AUX_DEV_ID (0x4B) /* Auxiliary interface device_id */ -#define BMI270_AUX_IF_CONF (0x4C) /* Auxiliary interface configuration */ -#define BMI270_AUX_RD_ADDR (0x4C) /* Auxiliary interface read address */ -#define BMI270_AUX_WR_ADDR (0x4E) /* Auxiliary interface write address */ -#define BMI270_AUX_WR_DATA (0x4F) /* Auxiliary interface write data */ -#define BMI270_ERR_REG_MSK (0x52) -#define BMI270_INT1_IO_CTRL (0x53) /* INT pin configuration */ -#define BMI270_INT2_IO_CTRL (0x54) -#define BMI270_INT_LATCH (0x55) /* Configure interrupt modes */ -#define BMI270_INT1_MAP_FEAT (0x56) /* Interrupt/Feature mapping on INT1 */ -#define BMI270_INT2_MAP_FEAT (0x57) /* Interrupt/Feature mapping on INT2 */ -#define BMI270_INT_MAP_DATA (0x58) /* Data Interrupt mapping for both INT pins */ -#define BMI270_INIT_CTRL (0x59) /* Start initialization */ -#define BMI270_INIT_ADDR_0 (0x5b) /* Base address of the initialization data */ -#define BMI270_INIT_ADDR_1 (0x5c) -#define BMI270_INIT_DATA (0x5e) /* Initialization register */ -#define BMI270_INTERNAL_ERROR (0x5f) -#define BMI270_AUX_IF_TRIM (0x68) /* Auxiliary interface trim */ -#define BMI270_GYR_CRT_CONF (0x69) /* Component Retrimming for Gyroscope */ -#define BMI270_NMV_CONFIG (0x6A) /* NVM Configuration */ -#define BMI270_IF_CONFIG (0x6B) /* Serial interface configuration */ -#define BMI270_DRV (0x6C) /* Drive strength control */ -#define BMI270_ACC_SELF_TEST (0x6D) /* Acc self test */ -#define BMI270_GYR_SELF_TEST (0x6E) /* Gyro self test */ -#define BMI270_NV_CONFIG (0x70) /* SPI/I2C selection */ -#define BMI270_OFFSET_0 (0x71) /* ACCEL and GYRO offset */ -#define BMI270_OFFSET_1 (0x72) -#define BMI270_OFFSET_2 (0x73) -#define BMI270_OFFSET_3 (0x74) -#define BMI270_OFFSET_4 (0x75) -#define BMI270_OFFSET_5 (0x76) -#define BMI270_OFFSET_6 (0x77) -#define BMI270_PWR_CONF (0x7C) /* Power mode configuration */ -#define BMI270_PWR_CTRL (0x7D) /* Power mode control */ -#define BMI270_CMD (0x7e) /* Command register */ - -/* Register 0x21 - INTERNAL_STATUS */ - -#define INTSTAT_MSG_MASK (7) -#define INTSTAT_MSG_NOTINIT (0x00) -#define INTSTAT_MSG_INITOK (0x01) - -/* Register 0x40 - ACCEL_CONFIG accel bandwidth */ - -#define ACCEL_OSR4_AVG1 (0 << 4) -#define ACCEL_OSR2_AVG2 (1 << 4) -#define ACCEL_NORMAL_AVG4 (2 << 4) -#define ACCEL_CIC_AVG8 (3 << 4) -#define ACCEL_RES_AVG2 (4 << 4) -#define ACCEL_RES_AVG4 (5 << 4) -#define ACCEL_RES_AVG8 (6 << 4) -#define ACCEL_RES_AVG16 (7 << 4) -#define ACCEL_RES_AVG32 (8 << 4) -#define ACCEL_RES_AVG64 (9 << 4) -#define ACCEL_RES_AVG128 (10 << 4) - -#define ACCEL_ODR_0_78HZ (0x01) -#define ACCEL_ODR_1_56HZ (0x02) -#define ACCEL_ODR_3_12HZ (0x03) -#define ACCEL_ODR_6_25HZ (0x04) -#define ACCEL_ODR_12_5HZ (0x05) -#define ACCEL_ODR_25HZ (0x06) -#define ACCEL_ODR_50HZ (0x07) -#define ACCEL_ODR_100HZ (0x08) -#define ACCEL_ODR_200HZ (0x09) -#define ACCEL_ODR_400HZ (0x0A) -#define ACCEL_ODR_800HZ (0x0B) -#define ACCEL_ODR_1600HZ (0x0C) - -/* Register 0x42 - GYRO_CONFIG accel bandwidth */ - -#define GYRO_OSR4_MODE (0 << 4) -#define GYRO_OSR2_MODE (1 << 4) -#define GYRO_NORMAL_MODE (2 << 4) -#define GYRO_CIC_MODE (3 << 4) - -#define GYRO_ODR_25HZ (0x06) -#define GYRO_ODR_50HZ (0x07) -#define GYRO_ODR_100HZ (0x08) -#define GYRO_ODR_200HZ (0x09) -#define GYRO_ODR_400HZ (0x0A) -#define GYRO_ODR_800HZ (0x0B) -#define GYRO_ODR_1600HZ (0x0C) -#define GYRO_ODR_3200HZ (0x0D) - -/* Register 0x7d - PWR_CONF */ - -#define PWRCONF_APS_ON (1 << 0) -#define PWRCONF_FSW_ON (1 << 1) -#define PWRCONF_FUP_ON (1 << 2) - -/* Register 0x7d - PWR_CTRL */ - -#define PWRCTRL_AUX_EN (1 << 0) -#define PWRCTRL_GYR_EN (1 << 1) -#define PWRCTRL_ACC_EN (1 << 2) -#define PWRCTRL_TEMP_EN (1 << 3) - -/* Register 0x7e - CMD */ - -#define CMD_SOFTRESET (0xB6) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct bmi270_dev_s -{ -#ifdef CONFIG_SENSORS_BMI270_I2C - FAR struct i2c_master_s *i2c; /* I2C interface */ - uint8_t addr; /* I2C address */ - int freq; /* Frequency <= 3.4MHz */ -#else /* CONFIG_SENSORS_BMI270_SPI */ - FAR struct spi_dev_s *spi; /* SPI interface */ -#endif -}; +#include "bmi270_base.h" /**************************************************************************** * Private Functions ****************************************************************************/ -static uint8_t bmi270_getreg8(FAR struct bmi270_dev_s *priv, - uint8_t regaddr); -static void bmi270_putreg8(FAR struct bmi270_dev_s *priv, uint8_t regaddr, - uint8_t regval); - -static void bmi270_getregs(FAR struct bmi270_dev_s *priv, uint8_t regaddr, - FAR uint8_t *regval, int len); -static void bmi270_putregs(FAR struct bmi270_dev_s *priv, uint8_t regaddr, - FAR uint8_t *regval, int len); - /* Character driver methods */ static int bmi270_open(FAR struct file *filep); @@ -237,8 +52,6 @@ static ssize_t bmi270_read(FAR struct file *filep, FAR char *buffer, static int bmi270_ioctl(FAR struct file *filep, int cmd, unsigned long arg); -static int bmi270_checkid(FAR struct bmi270_dev_s *priv); - /**************************************************************************** * Private Data ****************************************************************************/ @@ -255,1058 +68,6 @@ static const struct file_operations g_bmi270fops = bmi270_ioctl, /* ioctl */ }; -/* BMI270 configuration file - provided by BOSH */ - -static const uint8_t g_bmi270_config_file[] = -{ - 0xc8, 0x2e, 0x00, 0x2e, 0x80, 0x2e, 0x3d, 0xb1, 0xc8, 0x2e, 0x00, 0x2e, - 0x80, 0x2e, 0x91, 0x03, 0x80, 0x2e, 0xbc, 0xb0, 0x80, 0x2e, 0xa3, 0x03, - 0xc8, 0x2e, 0x00, 0x2e, 0x80, 0x2e, 0x00, 0xb0, 0x50, 0x30, 0x21, 0x2e, - 0x59, 0xf5, 0x10, 0x30, 0x21, 0x2e, 0x6a, 0xf5, 0x80, 0x2e, 0x3b, 0x03, - 0x00, 0x00, 0x00, 0x00, 0x08, 0x19, 0x01, 0x00, 0x22, 0x00, 0x75, 0x00, - 0x00, 0x10, 0x00, 0x10, 0xd1, 0x00, 0xb3, 0x43, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0xe0, 0x5f, 0x00, 0x00, - 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x19, 0x00, 0x00, - 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0xe0, 0xaa, 0x38, - 0x05, 0xe0, 0x90, 0x30, 0xfa, 0x00, 0x96, 0x00, 0x4b, 0x09, 0x11, 0x00, - 0x11, 0x00, 0x02, 0x00, 0x2d, 0x01, 0xd4, 0x7b, 0x3b, 0x01, 0xdb, 0x7a, - 0x04, 0x00, 0x3f, 0x7b, 0xcd, 0x6c, 0xc3, 0x04, 0x85, 0x09, 0xc3, 0x04, - 0xec, 0xe6, 0x0c, 0x46, 0x01, 0x00, 0x27, 0x00, 0x19, 0x00, 0x96, 0x00, - 0xa0, 0x00, 0x01, 0x00, 0x0c, 0x00, 0xf0, 0x3c, 0x00, 0x01, 0x01, 0x00, - 0x03, 0x00, 0x01, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x32, 0x00, 0x05, 0x00, - 0xee, 0x06, 0x04, 0x00, 0xc8, 0x00, 0x00, 0x00, 0x04, 0x00, 0xa8, 0x05, - 0xee, 0x06, 0x00, 0x04, 0xbc, 0x02, 0xb3, 0x00, 0x85, 0x07, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb4, 0x00, 0x01, 0x00, 0xb9, 0x00, - 0x01, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x80, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x80, 0x2e, 0x00, 0xc1, 0xfd, 0x2d, 0xde, 0x00, 0xeb, 0x00, - 0xda, 0x00, 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x04, 0xc0, 0x00, 0x5b, 0xf5, - 0xc9, 0x01, 0x1e, 0xf2, 0x80, 0x00, 0x3f, 0xff, 0x19, 0xf4, 0x58, 0xf5, - 0x66, 0xf5, 0x64, 0xf5, 0xc0, 0xf1, 0xf0, 0x00, 0xe0, 0x00, 0xcd, 0x01, - 0xd3, 0x01, 0xdb, 0x01, 0xff, 0x7f, 0xff, 0x01, 0xe4, 0x00, 0x74, 0xf7, - 0xf3, 0x00, 0xfa, 0x00, 0xff, 0x3f, 0xca, 0x03, 0x6c, 0x38, 0x56, 0xfe, - 0x44, 0xfd, 0xbc, 0x02, 0xf9, 0x06, 0x00, 0xfc, 0x12, 0x02, 0xae, 0x01, - 0x58, 0xfa, 0x9a, 0xfd, 0x77, 0x05, 0xbb, 0x02, 0x96, 0x01, 0x95, 0x01, - 0x7f, 0x01, 0x82, 0x01, 0x89, 0x01, 0x87, 0x01, 0x88, 0x01, 0x8a, 0x01, - 0x8c, 0x01, 0x8f, 0x01, 0x8d, 0x01, 0x92, 0x01, 0x91, 0x01, 0xdd, 0x00, - 0x9f, 0x01, 0x7e, 0x01, 0xdb, 0x00, 0xb6, 0x01, 0x70, 0x69, 0x26, 0xd3, - 0x9c, 0x07, 0x1f, 0x05, 0x9d, 0x00, 0x00, 0x08, 0xbc, 0x05, 0x37, 0xfa, - 0xa2, 0x01, 0xaa, 0x01, 0xa1, 0x01, 0xa8, 0x01, 0xa0, 0x01, 0xa8, 0x05, - 0xb4, 0x01, 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0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, - 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1 -}; - -/**************************************************************************** - * Name: bmi270_configspi - * - * Description: - * - ****************************************************************************/ - -#ifdef CONFIG_SENSORS_BMI270_SPI -static inline void bmi270_configspi(FAR struct spi_dev_s *spi) -{ - /* Configure SPI for the BMI270 */ - - SPI_SETMODE(spi, SPIDEV_MODE0); - SPI_SETBITS(spi, 8); - SPI_HWFEATURES(spi, 0); - SPI_SETFREQUENCY(spi, BMI270_SPI_MAXFREQUENCY); -} -#endif - -/**************************************************************************** - * Name: bmi270_getreg8 - * - * Description: - * Read from an 8-bit BMI270 register - * - ****************************************************************************/ - -static uint8_t bmi270_getreg8(FAR struct bmi270_dev_s *priv, uint8_t regaddr) -{ -#ifdef CONFIG_SENSORS_BMI270_I2C - struct i2c_msg_s msg[2]; - uint8_t regval = 0; - int ret; - - msg[0].frequency = priv->freq; - msg[0].addr = priv->addr; - msg[0].flags = I2C_M_NOSTOP; - msg[0].buffer = ®addr; - msg[0].length = 1; - - msg[1].frequency = priv->freq; - msg[1].addr = priv->addr; - msg[1].flags = I2C_M_READ; - msg[1].buffer = ®val; - msg[1].length = 1; - - ret = I2C_TRANSFER(priv->i2c, msg, 2); - if (ret < 0) - { - snerr("I2C_TRANSFER failed: %d\n", ret); - } - - return regval; -#else /* CONFIG_SENSORS_BMI270_SPI */ - uint8_t regval[2]; - - /* If SPI bus is shared then lock and configure it */ - - SPI_LOCK(priv->spi, true); - bmi270_configspi(priv->spi); - - /* Select the BMI270 */ - - SPI_SELECT(priv->spi, SPIDEV_IMU(0), true); - - /* Send register to read and get the next 2 bytes */ - - SPI_SEND(priv->spi, regaddr | 0x80); - SPI_RECVBLOCK(priv->spi, regval, 2); - - /* Deselect the BMI270 */ - - SPI_SELECT(priv->spi, SPIDEV_IMU(0), false); - - /* Unlock bus */ - - SPI_LOCK(priv->spi, false); - - /* The first byte has to be dropped */ - - return regval[1]; -#endif -} - -/**************************************************************************** - * Name: bmi270_putreg8 - * - * Description: - * Write a value to an 8-bit BMI270 register - * - ****************************************************************************/ - -static void bmi270_putreg8(FAR struct bmi270_dev_s *priv, uint8_t regaddr, - uint8_t regval) -{ -#ifdef CONFIG_SENSORS_BMI270_I2C - struct i2c_msg_s msg[2]; - uint8_t txbuffer[2]; - int ret; - - txbuffer[0] = regaddr; - txbuffer[1] = regval; - - msg[0].frequency = priv->freq; - msg[0].addr = priv->addr; - msg[0].flags = 0; - msg[0].buffer = txbuffer; - msg[0].length = 2; - - ret = I2C_TRANSFER(priv->i2c, msg, 1); - if (ret < 0) - { - snerr("I2C_TRANSFER failed: %d\n", ret); - } - -#else /* CONFIG_SENSORS_BMI270_SPI */ - /* If SPI bus is shared then lock and configure it */ - - SPI_LOCK(priv->spi, true); - bmi270_configspi(priv->spi); - - /* Select the BMI270 */ - - SPI_SELECT(priv->spi, SPIDEV_IMU(0), true); - - /* Send register address and set the value */ - - SPI_SEND(priv->spi, regaddr); - SPI_SEND(priv->spi, regval); - - /* Deselect the BMI270 */ - - SPI_SELECT(priv->spi, SPIDEV_IMU(0), false); - - /* Unlock bus */ - - SPI_LOCK(priv->spi, false); -#endif -} - -/**************************************************************************** - * Name: bmi270_getregs - * - * Description: - * Read cnt bytes from specified dev_addr and reg_addr - * - ****************************************************************************/ - -static void bmi270_getregs(FAR struct bmi270_dev_s *priv, uint8_t regaddr, - FAR uint8_t *regval, int len) -{ -#ifdef CONFIG_SENSORS_BMI270_I2C - struct i2c_msg_s msg[2]; - int ret; - - msg[0].frequency = priv->freq; - msg[0].addr = priv->addr; - msg[0].flags = I2C_M_NOSTOP; - msg[0].buffer = ®addr; - msg[0].length = 1; - - msg[1].frequency = priv->freq; - msg[1].addr = priv->addr; - msg[1].flags = I2C_M_READ; - msg[1].buffer = regval; - msg[1].length = len; - - ret = I2C_TRANSFER(priv->i2c, msg, 2); - if (ret < 0) - { - snerr("I2C_TRANSFER failed: %d\n", ret); - } -#else /* CONFIG_SENSORS_BMI270_SPI */ - uint8_t dummy = 0; - - /* If SPI bus is shared then lock and configure it */ - - SPI_LOCK(priv->spi, true); - bmi270_configspi(priv->spi); - - /* Select the BMI270 */ - - SPI_SELECT(priv->spi, SPIDEV_IMU(0), true); - - /* Send register to read and get bytes */ - - SPI_SEND(priv->spi, regaddr | 0x80); - SPI_RECVBLOCK(priv->spi, &dummy, 1); - SPI_RECVBLOCK(priv->spi, regval, len); - - /* Deselect the BMI270 */ - - SPI_SELECT(priv->spi, SPIDEV_IMU(0), false); - - /* Unlock bus */ - - SPI_LOCK(priv->spi, false); -#endif -} - -/**************************************************************************** - * Name: bmi270_putregs - * - * Description: - * Send cnt bytes for specified dev_addr and reg_addr - * - ****************************************************************************/ - -static void bmi270_putregs(FAR struct bmi270_dev_s *priv, uint8_t regaddr, - FAR uint8_t *regval, int len) -{ -#ifdef CONFIG_SENSORS_BMI270_I2C - struct i2c_msg_s msg[2]; - int ret; - - msg[0].frequency = priv->freq; - msg[0].addr = priv->addr; - msg[0].flags = I2C_M_NOSTOP; - msg[0].buffer = ®addr; - msg[0].length = 1; - - msg[1].frequency = priv->freq; - msg[1].addr = priv->addr; - msg[1].flags = 0; - msg[1].buffer = regval; - msg[1].length = len; - - ret = I2C_TRANSFER(priv->i2c, msg, 2); - if (ret < 0) - { - snerr("I2C_TRANSFER failed: %d\n", ret); - } -#else /* CONFIG_SENSORS_BMI270_SPI */ - /* If SPI bus is shared then lock and configure it */ - - SPI_LOCK(priv->spi, true); - bmi270_configspi(priv->spi); - - /* Select the BMI270 */ - - SPI_SELECT(priv->spi, SPIDEV_IMU(0), true); - - /* Send register to read and get bytes */ - - SPI_SEND(priv->spi, regaddr); - SPI_SNDBLOCK(priv->spi, regval, len); - - /* Deselect the BMI270 */ - - SPI_SELECT(priv->spi, SPIDEV_IMU(0), false); - - /* Unlock bus */ - - SPI_LOCK(priv->spi, false); -#endif -} - -/**************************************************************************** - * Name: bmi270_set_normal_imu - * - * Description: - * set bmi270 to normal IMU mode. - * - ****************************************************************************/ - -static void bmi270_set_normal_imu(FAR struct bmi270_dev_s *priv) -{ - /* Enable acquisition of acc and gyro */ - - bmi270_putreg8(priv, BMI270_PWR_CTRL, PWRCTRL_GYR_EN | PWRCTRL_ACC_EN); - up_mdelay(30); - - /* Set accel and gyro output data rate */ - - bmi270_putreg8(priv, BMI270_ACC_CONFIG, - ACCEL_NORMAL_AVG4 | ACCEL_ODR_100HZ); - bmi270_putreg8(priv, BMI270_GYR_CONFIG, - GYRO_NORMAL_MODE | GYRO_ODR_100HZ); - - /* Disable the adv_power_save bit */ - - bmi270_putreg8(priv, BMI270_PWR_CONF, PWRCONF_FSW_ON); -} - -/**************************************************************************** - * Name: bmi270_init_seq - * - * Description: - * set bmi270 to normal IMU mode. - * - ****************************************************************************/ - -static int bmi270_init_seq(FAR struct bmi270_dev_s *priv) -{ - FAR uint8_t *tmp = NULL; - uint8_t regval = 0; - - /* Check if initialization already done */ - - regval = bmi270_getreg8(priv, BMI270_INTERNAL_STAT); - if ((regval & INTSTAT_MSG_MASK) == INTSTAT_MSG_INITOK) - { - return OK; - } - - /* Disable PWR_CONF.adv_power_save */ - - bmi270_putreg8(priv, BMI270_PWR_CONF, 0); - up_mdelay(5); - - /* Prepare config load INIT_CTRL=0x00 */ - - bmi270_putreg8(priv, BMI270_INIT_CTRL, 0); - -#ifdef CONFIG_SENSORS_BMI270_LOAD_FROM_HEAP - - /* Copy configuration to RAM */ - - tmp = kmm_malloc(sizeof(g_bmi270_config_file)); - if (tmp == NULL) - { - snerr("Failed to allocate memory for configuration file\n"); - return -ENOMEM; - } - - memcpy(tmp, g_bmi270_config_file, sizeof(g_bmi270_config_file)); - -#else - - /* Transfer directly from const data memory */ - - tmp = (FAR uint8_t *)&g_bmi270_config_file; - -#endif - - /* Load configuration - start with byte 0 */ - - bmi270_putregs(priv, BMI270_INIT_DATA, - tmp, - sizeof(g_bmi270_config_file)); - -#ifdef CONFIG_SENSORS_BMI270_LOAD_FROM_HEAP - kmm_free(tmp); -#endif - - /* Complete config load INIT_CTRL=0x01 */ - - bmi270_putreg8(priv, BMI270_INIT_CTRL, 1); - - up_mdelay(150); - - /* Check initialization status */ - - regval = bmi270_getreg8(priv, BMI270_INTERNAL_STAT); - if ((regval & INTSTAT_MSG_MASK) != INTSTAT_MSG_INITOK) - { - snerr("Initialization failed status=%d\n", regval); - return -EACCES; - } - - return OK; -} - /**************************************************************************** * Name: bmi270_open * @@ -1400,33 +161,6 @@ static int bmi270_ioctl(FAR struct file *filep, int cmd, unsigned long arg) return -ENOTTY; } -/**************************************************************************** - * Name: bmi270_checkid - * - * Description: - * Read and verify the BMI270 chip ID - * - ****************************************************************************/ - -static int bmi270_checkid(FAR struct bmi270_dev_s *priv) -{ - uint8_t devid = 0; - - /* Read device ID */ - - devid = bmi270_getreg8(priv, BMI270_CHIP_ID); - sninfo("devid: %04x\n", devid); - - if (devid != (uint16_t) DEVID) - { - /* ID is not Correct */ - - return -ENODEV; - } - - return OK; -} - /**************************************************************************** * Name: bmi270_register * diff --git a/drivers/sensors/bmi270_base.c b/drivers/sensors/bmi270_base.c new file mode 100644 index 0000000000000..0e082e812360d --- /dev/null +++ b/drivers/sensors/bmi270_base.c @@ -0,0 +1,1118 @@ +/**************************************************************************** + * drivers/sensors/bmi270_base.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +# include "bmi270_base.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* BMI270 configuration file - provided by BOSH */ + +const uint8_t g_bmi270_config_file[] = +{ + 0xc8, 0x2e, 0x00, 0x2e, 0x80, 0x2e, 0x3d, 0xb1, 0xc8, 0x2e, 0x00, 0x2e, + 0x80, 0x2e, 0x91, 0x03, 0x80, 0x2e, 0xbc, 0xb0, 0x80, 0x2e, 0xa3, 0x03, + 0xc8, 0x2e, 0x00, 0x2e, 0x80, 0x2e, 0x00, 0xb0, 0x50, 0x30, 0x21, 0x2e, + 0x59, 0xf5, 0x10, 0x30, 0x21, 0x2e, 0x6a, 0xf5, 0x80, 0x2e, 0x3b, 0x03, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x19, 0x01, 0x00, 0x22, 0x00, 0x75, 0x00, + 0x00, 0x10, 0x00, 0x10, 0xd1, 0x00, 0xb3, 0x43, 0x80, 0x2e, 0x00, 0xc1, + 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, + 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, + 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, + 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, + 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, + 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, + 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, + 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, + 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, + 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, + 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, + 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, + 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, + 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0xe0, 0x5f, 0x00, 0x00, + 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x92, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x19, 0x00, 0x00, + 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0xe0, 0xaa, 0x38, + 0x05, 0xe0, 0x90, 0x30, 0xfa, 0x00, 0x96, 0x00, 0x4b, 0x09, 0x11, 0x00, + 0x11, 0x00, 0x02, 0x00, 0x2d, 0x01, 0xd4, 0x7b, 0x3b, 0x01, 0xdb, 0x7a, + 0x04, 0x00, 0x3f, 0x7b, 0xcd, 0x6c, 0xc3, 0x04, 0x85, 0x09, 0xc3, 0x04, + 0xec, 0xe6, 0x0c, 0x46, 0x01, 0x00, 0x27, 0x00, 0x19, 0x00, 0x96, 0x00, + 0xa0, 0x00, 0x01, 0x00, 0x0c, 0x00, 0xf0, 0x3c, 0x00, 0x01, 0x01, 0x00, + 0x03, 0x00, 0x01, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x32, 0x00, 0x05, 0x00, + 0xee, 0x06, 0x04, 0x00, 0xc8, 0x00, 0x00, 0x00, 0x04, 0x00, 0xa8, 0x05, + 0xee, 0x06, 0x00, 0x04, 0xbc, 0x02, 0xb3, 0x00, 0x85, 0x07, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb4, 0x00, 0x01, 0x00, 0xb9, 0x00, + 0x01, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00, 0x80, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x80, 0x2e, 0x00, 0xc1, 0xfd, 0x2d, 0xde, 0x00, 0xeb, 0x00, + 0xda, 0x00, 0x00, 0x0c, 0xff, 0x0f, 0x00, 0x04, 0xc0, 0x00, 0x5b, 0xf5, + 0xc9, 0x01, 0x1e, 0xf2, 0x80, 0x00, 0x3f, 0xff, 0x19, 0xf4, 0x58, 0xf5, + 0x66, 0xf5, 0x64, 0xf5, 0xc0, 0xf1, 0xf0, 0x00, 0xe0, 0x00, 0xcd, 0x01, + 0xd3, 0x01, 0xdb, 0x01, 0xff, 0x7f, 0xff, 0x01, 0xe4, 0x00, 0x74, 0xf7, + 0xf3, 0x00, 0xfa, 0x00, 0xff, 0x3f, 0xca, 0x03, 0x6c, 0x38, 0x56, 0xfe, + 0x44, 0xfd, 0xbc, 0x02, 0xf9, 0x06, 0x00, 0xfc, 0x12, 0x02, 0xae, 0x01, + 0x58, 0xfa, 0x9a, 0xfd, 0x77, 0x05, 0xbb, 0x02, 0x96, 0x01, 0x95, 0x01, + 0x7f, 0x01, 0x82, 0x01, 0x89, 0x01, 0x87, 0x01, 0x88, 0x01, 0x8a, 0x01, + 0x8c, 0x01, 0x8f, 0x01, 0x8d, 0x01, 0x92, 0x01, 0x91, 0x01, 0xdd, 0x00, + 0x9f, 0x01, 0x7e, 0x01, 0xdb, 0x00, 0xb6, 0x01, 0x70, 0x69, 0x26, 0xd3, + 0x9c, 0x07, 0x1f, 0x05, 0x9d, 0x00, 0x00, 0x08, 0xbc, 0x05, 0x37, 0xfa, + 0xa2, 0x01, 0xaa, 0x01, 0xa1, 0x01, 0xa8, 0x01, 0xa0, 0x01, 0xa8, 0x05, + 0xb4, 0x01, 0xb4, 0x01, 0xce, 0x00, 0xd0, 0x00, 0xfc, 0x00, 0xc5, 0x01, + 0xff, 0xfb, 0xb1, 0x00, 0x00, 0x38, 0x00, 0x30, 0xfd, 0xf5, 0xfc, 0xf5, + 0xcd, 0x01, 0xa0, 0x00, 0x5f, 0xff, 0x00, 0x40, 0xff, 0x00, 0x00, 0x80, + 0x6d, 0x0f, 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0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, + 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, + 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1, + 0x80, 0x2e, 0x00, 0xc1, 0x80, 0x2e, 0x00, 0xc1 +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: bmi270_configspi + * + * Description: + * + ****************************************************************************/ + +#ifdef CONFIG_SENSORS_BMI270_SPI +static void bmi270_configspi(FAR struct spi_dev_s *spi) +{ + /* Configure SPI for the BMI270 */ + + SPI_SETMODE(spi, SPIDEV_MODE0); + SPI_SETBITS(spi, 8); + SPI_HWFEATURES(spi, 0); + SPI_SETFREQUENCY(spi, BMI270_SPI_MAXFREQUENCY); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: bmi270_getreg8 + * + * Description: + * Read from an 8-bit BMI270 register + * + ****************************************************************************/ + +uint8_t bmi270_getreg8(FAR struct bmi270_dev_s *priv, uint8_t regaddr) +{ +#ifdef CONFIG_SENSORS_BMI270_I2C + struct i2c_msg_s msg[2]; + uint8_t regval = 0; + int ret; + + msg[0].frequency = priv->freq; + msg[0].addr = priv->addr; + msg[0].flags = I2C_M_NOSTOP; + msg[0].buffer = ®addr; + msg[0].length = 1; + + msg[1].frequency = priv->freq; + msg[1].addr = priv->addr; + msg[1].flags = I2C_M_READ; + msg[1].buffer = ®val; + msg[1].length = 1; + + ret = I2C_TRANSFER(priv->i2c, msg, 2); + if (ret < 0) + { + snerr("I2C_TRANSFER failed: %d\n", ret); + } + + return regval; +#else /* CONFIG_SENSORS_BMI270_SPI */ + uint8_t regval[2]; + + /* If SPI bus is shared then lock and configure it */ + + SPI_LOCK(priv->spi, true); + bmi270_configspi(priv->spi); + + /* Select the BMI270 */ + + SPI_SELECT(priv->spi, SPIDEV_IMU(0), true); + + /* Send register to read and get the next 2 bytes */ + + SPI_SEND(priv->spi, regaddr | 0x80); + SPI_RECVBLOCK(priv->spi, regval, 2); + + /* Deselect the BMI270 */ + + SPI_SELECT(priv->spi, SPIDEV_IMU(0), false); + + /* Unlock bus */ + + SPI_LOCK(priv->spi, false); + + /* The first byte has to be dropped */ + + return regval[1]; +#endif +} + +/**************************************************************************** + * Name: bmi270_putreg8 + * + * Description: + * Write a value to an 8-bit BMI270 register + * + ****************************************************************************/ + +void bmi270_putreg8(FAR struct bmi270_dev_s *priv, uint8_t regaddr, + uint8_t regval) +{ +#ifdef CONFIG_SENSORS_BMI270_I2C + struct i2c_msg_s msg[2]; + uint8_t txbuffer[2]; + int ret; + + txbuffer[0] = regaddr; + txbuffer[1] = regval; + + msg[0].frequency = priv->freq; + msg[0].addr = priv->addr; + msg[0].flags = 0; + msg[0].buffer = txbuffer; + msg[0].length = 2; + + ret = I2C_TRANSFER(priv->i2c, msg, 1); + if (ret < 0) + { + snerr("I2C_TRANSFER failed: %d\n", ret); + } + +#else /* CONFIG_SENSORS_BMI270_SPI */ + /* If SPI bus is shared then lock and configure it */ + + SPI_LOCK(priv->spi, true); + bmi270_configspi(priv->spi); + + /* Select the BMI270 */ + + SPI_SELECT(priv->spi, SPIDEV_IMU(0), true); + + /* Send register address and set the value */ + + SPI_SEND(priv->spi, regaddr); + SPI_SEND(priv->spi, regval); + + /* Deselect the BMI270 */ + + SPI_SELECT(priv->spi, SPIDEV_IMU(0), false); + + /* Unlock bus */ + + SPI_LOCK(priv->spi, false); +#endif +} + +/**************************************************************************** + * Name: bmi270_getregs + * + * Description: + * Read cnt bytes from specified dev_addr and reg_addr + * + ****************************************************************************/ + +void bmi270_getregs(FAR struct bmi270_dev_s *priv, uint8_t regaddr, + FAR uint8_t *regval, int len) +{ +#ifdef CONFIG_SENSORS_BMI270_I2C + struct i2c_msg_s msg[2]; + int ret; + + msg[0].frequency = priv->freq; + msg[0].addr = priv->addr; + msg[0].flags = I2C_M_NOSTOP; + msg[0].buffer = ®addr; + msg[0].length = 1; + + msg[1].frequency = priv->freq; + msg[1].addr = priv->addr; + msg[1].flags = I2C_M_READ; + msg[1].buffer = regval; + msg[1].length = len; + + ret = I2C_TRANSFER(priv->i2c, msg, 2); + if (ret < 0) + { + snerr("I2C_TRANSFER failed: %d\n", ret); + } +#else /* CONFIG_SENSORS_BMI270_SPI */ + uint8_t dummy = 0; + + /* If SPI bus is shared then lock and configure it */ + + SPI_LOCK(priv->spi, true); + bmi270_configspi(priv->spi); + + /* Select the BMI270 */ + + SPI_SELECT(priv->spi, SPIDEV_IMU(0), true); + + /* Send register to read and get bytes */ + + SPI_SEND(priv->spi, regaddr | 0x80); + SPI_RECVBLOCK(priv->spi, &dummy, 1); + SPI_RECVBLOCK(priv->spi, regval, len); + + /* Deselect the BMI270 */ + + SPI_SELECT(priv->spi, SPIDEV_IMU(0), false); + + /* Unlock bus */ + + SPI_LOCK(priv->spi, false); +#endif +} + +/**************************************************************************** + * Name: bmi270_putregs + * + * Description: + * Send cnt bytes for specified dev_addr and reg_addr + * + ****************************************************************************/ + +void bmi270_putregs(FAR struct bmi270_dev_s *priv, uint8_t regaddr, + FAR uint8_t *regval, int len) +{ +#ifdef CONFIG_SENSORS_BMI270_I2C + struct i2c_msg_s msg[2]; + int ret; + + msg[0].frequency = priv->freq; + msg[0].addr = priv->addr; + msg[0].flags = I2C_M_NOSTOP; + msg[0].buffer = ®addr; + msg[0].length = 1; + + msg[1].frequency = priv->freq; + msg[1].addr = priv->addr; + msg[1].flags = 0; + msg[1].buffer = regval; + msg[1].length = len; + + ret = I2C_TRANSFER(priv->i2c, msg, 2); + if (ret < 0) + { + snerr("I2C_TRANSFER failed: %d\n", ret); + } +#else /* CONFIG_SENSORS_BMI270_SPI */ + /* If SPI bus is shared then lock and configure it */ + + SPI_LOCK(priv->spi, true); + bmi270_configspi(priv->spi); + + /* Select the BMI270 */ + + SPI_SELECT(priv->spi, SPIDEV_IMU(0), true); + + /* Send register to read and get bytes */ + + SPI_SEND(priv->spi, regaddr); + SPI_SNDBLOCK(priv->spi, regval, len); + + /* Deselect the BMI270 */ + + SPI_SELECT(priv->spi, SPIDEV_IMU(0), false); + + /* Unlock bus */ + + SPI_LOCK(priv->spi, false); +#endif +} + +/**************************************************************************** + * Name: bmi270_set_normal_imu + * + * Description: + * set bmi270 to normal IMU mode. + * + ****************************************************************************/ + +void bmi270_set_normal_imu(FAR struct bmi270_dev_s *priv) +{ + /* Enable acquisition of acc and gyro */ + + bmi270_putreg8(priv, BMI270_PWR_CTRL, PWRCTRL_GYR_EN | PWRCTRL_ACC_EN); + up_mdelay(30); + + /* Set accel and gyro output data rate */ + + bmi270_putreg8(priv, BMI270_ACC_CONFIG, + ACCEL_NORMAL_AVG4 | ACCEL_ODR_100HZ); + bmi270_putreg8(priv, BMI270_GYR_CONFIG, + GYRO_NORMAL_MODE | GYRO_ODR_100HZ); + + /* Disable the adv_power_save bit */ + + bmi270_putreg8(priv, BMI270_PWR_CONF, PWRCONF_FSW_ON); +} + +/**************************************************************************** + * Name: bmi270_init_seq + * + * Description: + * set bmi270 to normal IMU mode. + * + ****************************************************************************/ + +int bmi270_init_seq(FAR struct bmi270_dev_s *priv) +{ + FAR uint8_t *tmp = NULL; + uint8_t regval = 0; + + /* Check if initialization already done */ + + regval = bmi270_getreg8(priv, BMI270_INTERNAL_STAT); + if ((regval & INTSTAT_MSG_MASK) == INTSTAT_MSG_INITOK) + { + return OK; + } + + /* Disable PWR_CONF.adv_power_save */ + + bmi270_putreg8(priv, BMI270_PWR_CONF, 0); + up_mdelay(5); + + /* Prepare config load INIT_CTRL=0x00 */ + + bmi270_putreg8(priv, BMI270_INIT_CTRL, 0); + +#ifdef CONFIG_SENSORS_BMI270_LOAD_FROM_HEAP + + /* Copy configuration to RAM */ + + tmp = kmm_malloc(sizeof(g_bmi270_config_file)); + if (tmp == NULL) + { + snerr("Failed to allocate memory for configuration file\n"); + return -ENOMEM; + } + + memcpy(tmp, g_bmi270_config_file, sizeof(g_bmi270_config_file)); + +#else + + /* Transfer directly from const data memory */ + + tmp = (FAR uint8_t *)&g_bmi270_config_file; + +#endif + + /* Load configuration - start with byte 0 */ + + bmi270_putregs(priv, BMI270_INIT_DATA, + tmp, + sizeof(g_bmi270_config_file)); + +#ifdef CONFIG_SENSORS_BMI270_LOAD_FROM_HEAP + kmm_free(tmp); +#endif + + /* Complete config load INIT_CTRL=0x01 */ + + bmi270_putreg8(priv, BMI270_INIT_CTRL, 1); + + up_mdelay(150); + + /* Check initialization status */ + + regval = bmi270_getreg8(priv, BMI270_INTERNAL_STAT); + if ((regval & INTSTAT_MSG_MASK) != INTSTAT_MSG_INITOK) + { + snerr("Initialization failed status=%d\n", regval); + return -EACCES; + } + + return OK; +} + +/**************************************************************************** + * Name: bmi270_checkid + * + * Description: + * Read and verify the BMI270 chip ID + * + ****************************************************************************/ + +int bmi270_checkid(FAR struct bmi270_dev_s *priv) +{ + uint8_t devid = 0; + + /* Read device ID */ + + devid = bmi270_getreg8(priv, BMI270_CHIP_ID); + sninfo("devid: %04x\n", devid); + + if (devid != (uint16_t) DEVID) + { + /* ID is not Correct */ + + return -ENODEV; + } + + return OK; +} diff --git a/drivers/sensors/bmi270_base.h b/drivers/sensors/bmi270_base.h new file mode 100644 index 0000000000000..b70295f84fab5 --- /dev/null +++ b/drivers/sensors/bmi270_base.h @@ -0,0 +1,260 @@ +/**************************************************************************** + * drivers/sensors/bmi270_base.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_SENSORS_BMI270_BASE_H +#define __INCLUDE_NUTTX_SENSORS_BMI270_BASE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#ifdef CONFIG_SENSORS_BMI270_I2C +# include +#else +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define BMI270_SPI_MAXFREQUENCY 10000000 +#define BMI270_I2C_FREQ 400000 + +#define DEVID 0x24 + +#define BMI270_CHIP_ID (0x00) /* Chip ID */ +#define BMI270_ERROR (0x02) /* Error register */ +#define BMI270_PMU_STAT (0x03) /* Current power mode */ +#define BMI270_DATA_0 (0x04) /* MAG X 7:0 (LSB) */ +#define BMI270_DATA_1 (0x05) /* MAG X 15:8 (MSB) */ +#define BMI270_DATA_2 (0x06) /* MAG Y 7:0 (LSB) */ +#define BMI270_DATA_3 (0x07) /* MAG Y 15:8 (MSB) */ +#define BMI270_DATA_4 (0x08) /* MAG Z 7:0 (LSB) */ +#define BMI270_DATA_5 (0x09) /* MAG Z 15:8 (MSB) */ +#define BMI270_DATA_6 (0x0a) /* RHALL 7:0 (LSB) */ +#define BMI270_DATA_7 (0x0b) /* RHALL 15:8 (MSB) */ + +#define BMI270_DATA_8 (0x0c) /* ACC X 7:0 (LSB) */ +#define BMI270_DATA_9 (0x0d) /* ACC X 15:8 (MSB) */ +#define BMI270_DATA_10 (0x0e) /* ACC Y 7:0 (LSB) */ +#define BMI270_DATA_11 (0x0f) /* ACC Y 15:8 (MSB) */ +#define BMI270_DATA_12 (0x10) /* ACC Z 7:0 (LSB) */ +#define BMI270_DATA_13 (0x11) /* ACC Z 15:8 (MSB) */ + +#define BMI270_DATA_14 (0x12) /* GYR X 7:0 (LSB) */ +#define BMI270_DATA_15 (0x13) /* GYR X 15:8 (MSB) */ +#define BMI270_DATA_16 (0x14) /* GYR Y 7:0 (LSB) */ +#define BMI270_DATA_17 (0x15) /* GYR Y 15:8 (MSB) */ +#define BMI270_DATA_18 (0x16) /* GYR Z 7:0 (LSB) */ +#define BMI270_DATA_19 (0x17) /* GYR Z 15:8 (MSB) */ +#define BMI270_SENSORTIME_0 (0x18) /* Sensor time 0 */ +#define BMI270_SENSORTIME_1 (0x19) /* Sensor time 1 */ +#define BMI270_SENSORTIME_2 (0x1A) /* Sensor time 2 */ +#define BMI270_EVENT (0x1B) /* Sensor event flags */ +#define BMI270_INTR_STAT_0 (0x1C) /* Interrupt status */ +#define BMI270_INTR_STAT_1 (0x1D) +#define BMI270_SC_OUT_0 (0x1E) /* Step counting value */ +#define BMI270_SC_OUT_1 (0x1f) /* Step counting value */ +#define BMI270_WR_GEST_ACT (0x20) /* Wrist gesture and activity detection */ +#define BMI270_INTERNAL_STAT (0x21) /* Internal status */ +#define BMI270_TEMPERATURE_0 (0x22) /* Temperature */ +#define BMI270_TEMPERATURE_1 (0x23) +#define BMI270_FIFO_LENGTH_0 (0x24) /* FIFO length */ +#define BMI270_FIFO_LENGTH_1 (0x25) +#define BMI270_FIFO_DATA (0x26) +#define BMI270_FEAT_PAGE (0x2f) /* Page number for feature configuration and output registers */ + /* TODO: Features 0x30-0x3f */ +#define BMI270_ACC_CONFIG (0x40) /* ACCEL config for ODR, bandwidth and undersampling */ +#define BMI270_ACC_RANGE (0x41) /* ACCEL range */ +#define BMI270_GYR_CONFIG (0x42) /* GYRO config for ODR and bandwidth */ +#define BMI270_GYR_RANGE (0x43) /* GYRO range */ +#define BMI270_AUX_CONFIG (0x44) /* AUX config for ODR */ +#define BMI270_FIFO_DOWN (0x45) /* GYRO and ACCEL downsampling rates for FIFO */ +#define BMI270_FIFO_WTM_0 (0x46) /* FIFO Watermark level */ +#define BMI270_FIFO_WTM_1 (0x47) /* FIFO Watermark level */ +#define BMI270_FIFO_CONFIG_0 (0x48) /* FIFO config */ +#define BMI270_FIFO_CONFIG_1 (0x49) +#define BMI270_SATURATION (0x4A) /* Saturation */ +#define BMI270_AUX_DEV_ID (0x4B) /* Auxiliary interface device_id */ +#define BMI270_AUX_IF_CONF (0x4C) /* Auxiliary interface configuration */ +#define BMI270_AUX_RD_ADDR (0x4C) /* Auxiliary interface read address */ +#define BMI270_AUX_WR_ADDR (0x4E) /* Auxiliary interface write address */ +#define BMI270_AUX_WR_DATA (0x4F) /* Auxiliary interface write data */ +#define BMI270_ERR_REG_MSK (0x52) +#define BMI270_INT1_IO_CTRL (0x53) /* INT pin configuration */ +#define BMI270_INT2_IO_CTRL (0x54) +#define BMI270_INT_LATCH (0x55) /* Configure interrupt modes */ +#define BMI270_INT1_MAP_FEAT (0x56) /* Interrupt/Feature mapping on INT1 */ +#define BMI270_INT2_MAP_FEAT (0x57) /* Interrupt/Feature mapping on INT2 */ +#define BMI270_INT_MAP_DATA (0x58) /* Data Interrupt mapping for both INT pins */ +#define BMI270_INIT_CTRL (0x59) /* Start initialization */ +#define BMI270_INIT_ADDR_0 (0x5b) /* Base address of the initialization data */ +#define BMI270_INIT_ADDR_1 (0x5c) +#define BMI270_INIT_DATA (0x5e) /* Initialization register */ +#define BMI270_INTERNAL_ERROR (0x5f) +#define BMI270_AUX_IF_TRIM (0x68) /* Auxiliary interface trim */ +#define BMI270_GYR_CRT_CONF (0x69) /* Component Retrimming for Gyroscope */ +#define BMI270_NMV_CONFIG (0x6A) /* NVM Configuration */ +#define BMI270_IF_CONFIG (0x6B) /* Serial interface configuration */ +#define BMI270_DRV (0x6C) /* Drive strength control */ +#define BMI270_ACC_SELF_TEST (0x6D) /* Acc self test */ +#define BMI270_GYR_SELF_TEST (0x6E) /* Gyro self test */ +#define BMI270_NV_CONFIG (0x70) /* SPI/I2C selection */ +#define BMI270_OFFSET_0 (0x71) /* ACCEL and GYRO offset */ +#define BMI270_OFFSET_1 (0x72) +#define BMI270_OFFSET_2 (0x73) +#define BMI270_OFFSET_3 (0x74) +#define BMI270_OFFSET_4 (0x75) +#define BMI270_OFFSET_5 (0x76) +#define BMI270_OFFSET_6 (0x77) +#define BMI270_PWR_CONF (0x7C) /* Power mode configuration */ +#define BMI270_PWR_CTRL (0x7D) /* Power mode control */ +#define BMI270_CMD (0x7e) /* Command register */ + +/* Register 0x21 - INTERNAL_STATUS */ + +#define INTSTAT_MSG_MASK (7) +#define INTSTAT_MSG_NOTINIT (0x00) +#define INTSTAT_MSG_INITOK (0x01) + +/* Register 0x40 - ACCEL_CONFIG accel bandwidth */ + +#define ACCEL_OSR4_AVG1 (0 << 4) +#define ACCEL_OSR2_AVG2 (1 << 4) +#define ACCEL_NORMAL_AVG4 (2 << 4) +#define ACCEL_CIC_AVG8 (3 << 4) +#define ACCEL_RES_AVG2 (4 << 4) +#define ACCEL_RES_AVG4 (5 << 4) +#define ACCEL_RES_AVG8 (6 << 4) +#define ACCEL_RES_AVG16 (7 << 4) +#define ACCEL_RES_AVG32 (8 << 4) +#define ACCEL_RES_AVG64 (9 << 4) +#define ACCEL_RES_AVG128 (10 << 4) + +#define ACCEL_ODR_0_78HZ (0x01) +#define ACCEL_ODR_1_56HZ (0x02) +#define ACCEL_ODR_3_12HZ (0x03) +#define ACCEL_ODR_6_25HZ (0x04) +#define ACCEL_ODR_12_5HZ (0x05) +#define ACCEL_ODR_25HZ (0x06) +#define ACCEL_ODR_50HZ (0x07) +#define ACCEL_ODR_100HZ (0x08) +#define ACCEL_ODR_200HZ (0x09) +#define ACCEL_ODR_400HZ (0x0A) +#define ACCEL_ODR_800HZ (0x0B) +#define ACCEL_ODR_1600HZ (0x0C) + +/* Register 0x41 - ACC_RANGE accel range */ + +#define ACCEL_RANGE_2G (0x00) +#define ACCEL_RANGE_4G (0x01) +#define ACCEL_RANGE_8G (0x02) +#define ACCEL_RANGE_16G (0x03) + +/* Register 0x42 - GYRO_CONFIG accel bandwidth */ + +#define GYRO_OSR4_MODE (0 << 4) +#define GYRO_OSR2_MODE (1 << 4) +#define GYRO_NORMAL_MODE (2 << 4) +#define GYRO_CIC_MODE (3 << 4) + +#define GYRO_ODR_25HZ (0x06) +#define GYRO_ODR_50HZ (0x07) +#define GYRO_ODR_100HZ (0x08) +#define GYRO_ODR_200HZ (0x09) +#define GYRO_ODR_400HZ (0x0A) +#define GYRO_ODR_800HZ (0x0B) +#define GYRO_ODR_1600HZ (0x0C) +#define GYRO_ODR_3200HZ (0x0D) + +/* Register 0x43 - GYR_RANGE gyr range */ + +#define GYRO_RANGE_2000 (0x00) +#define GYRO_RANGE_1000 (0x01) +#define GYRO_RANGE_500 (0x02) +#define GYRO_RANGE_250 (0x03) +#define GYRO_RANGE_125 (0x04) + +/* Register 0x7d - PWR_CONF */ + +#define PWRCONF_APS_ON (1 << 0) +#define PWRCONF_FSW_ON (1 << 1) +#define PWRCONF_FUP_ON (1 << 2) + +/* Register 0x7d - PWR_CTRL */ + +#define PWRCTRL_AUX_EN (1 << 0) +#define PWRCTRL_GYR_EN (1 << 1) +#define PWRCTRL_ACC_EN (1 << 2) +#define PWRCTRL_TEMP_EN (1 << 3) + +/* Register 0x7e - CMD */ + +#define CMD_SOFTRESET (0xB6) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct bmi270_dev_s +{ +#ifdef CONFIG_SENSORS_BMI270_I2C + FAR struct i2c_master_s *i2c; /* I2C interface */ + uint8_t addr; /* I2C address */ + int freq; /* Frequency <= 3.4MHz */ +#else /* CONFIG_SENSORS_BMI270_SPI */ + FAR struct spi_dev_s *spi; /* SPI interface */ +#endif +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +extern const uint8_t g_bmi270_config_file[]; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +uint8_t bmi270_getreg8(FAR struct bmi270_dev_s *priv, uint8_t regaddr); +void bmi270_putreg8(FAR struct bmi270_dev_s *priv, uint8_t regaddr, + uint8_t regval); +void bmi270_getregs(FAR struct bmi270_dev_s *priv, uint8_t regaddr, + FAR uint8_t *regval, int len); +void bmi270_putregs(FAR struct bmi270_dev_s *priv, uint8_t regaddr, + FAR uint8_t *regval, int len); + +void bmi270_set_normal_imu(FAR struct bmi270_dev_s *priv); +int bmi270_init_seq(FAR struct bmi270_dev_s *priv); +int bmi270_checkid(FAR struct bmi270_dev_s *priv); + +#endif /* __INCLUDE_NUTTX_SENSORS_BMI270_BASE_H */ diff --git a/drivers/sensors/bmi270_uorb.c b/drivers/sensors/bmi270_uorb.c new file mode 100644 index 0000000000000..68aaa9229f15d --- /dev/null +++ b/drivers/sensors/bmi270_uorb.c @@ -0,0 +1,707 @@ +/**************************************************************************** + * drivers/sensors/bmi270_uorb.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "bmi270_base.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CONSTANTS_ONE_G 9.8f + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +enum bmi270_idx_e +{ + BMI270_ACCEL_IDX = 0, + BMI270_GYRO_IDX, + BMI270_MAX_IDX +}; + +struct bmi270_sensor_s +{ + struct sensor_lowerhalf_s lower; + uint64_t last_update; + float scale; + FAR void *dev; + bool enabled; +#ifdef CONFIG_SENSORS_BMI270_POLL + unsigned long interval; +#endif + struct bmi270_dev_s base; +}; + +struct bmi270_sensor_dev_s +{ + struct bmi270_sensor_s priv[BMI270_MAX_IDX]; + mutex_t lock; +#ifdef CONFIG_SENSORS_BMI270_POLL + sem_t run; +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Sensor methods */ + +static int bmi270_activate(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + bool enable); +static int bmi270_set_interval(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR unsigned long *period_us); +#ifndef CONFIG_SENSORS_BMI270_POLL +static int bmi270_fetch(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR char *buffer, size_t buflen); +#endif +static int bmi270_control(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + int cmd, unsigned long arg); + +/* Helpers */ + +static int bmi270_accel_scale(FAR struct bmi270_sensor_s *priv, + uint8_t scale); +static int bmi270_gyro_scale(FAR struct bmi270_sensor_s *priv, + uint16_t scale); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct sensor_ops_s g_sensor_ops = +{ + NULL, /* open */ + NULL, /* close */ + bmi270_activate, + bmi270_set_interval, + NULL, /* batch */ +#ifdef CONFIG_SENSORS_BMI270_POLL + NULL, /* fetch */ +#else + bmi270_fetch, +#endif + NULL, /* selftest */ + NULL, /* set_calibvalue */ + NULL, /* calibrate */ + bmi270_control +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: bmi270_activate + ****************************************************************************/ + +static int bmi270_activate(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, bool enable) +{ + FAR struct bmi270_sensor_s *priv = NULL; + FAR struct bmi270_sensor_dev_s *dev = NULL; + bool start = false; + bool stop = false; + int ret = OK; + int tmp = 0; + + priv = (FAR struct bmi270_sensor_s *)lower; + dev = priv->dev; + + nxmutex_lock(&dev->lock); + + tmp = (dev->priv[BMI270_ACCEL_IDX].enabled + + dev->priv[BMI270_GYRO_IDX].enabled); + + if (enable && tmp == 0) + { + /* One time start */ + + start = true; + } + else if (!enable && tmp == 1) + { + /* One time stop */ + + stop = true; + } + + priv->enabled = enable; + + nxmutex_unlock(&dev->lock); + + if (start) + { + /* Set normal mode */ + + bmi270_set_normal_imu(&priv->base); + +#ifdef CONFIG_SENSORS_BMI270_POLL + priv->last_update = sensor_get_timestamp(); + + /* Wake up the thread */ + + nxsem_post(&dev->run); +#endif + } + + else if (stop) + { + /* Disable acquisition of acc and gyro */ + + bmi270_putreg8(&priv->base, BMI270_PWR_CTRL, 0); + up_mdelay(30); + } + + return ret; +} + +/**************************************************************************** + * Name: bmi270_set_interval + ****************************************************************************/ + +static int bmi270_set_interval(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR unsigned long *interval) +{ +#ifdef CONFIG_SENSORS_BMI270_POLL + FAR struct bmi270_sensor_s *priv = NULL; + + priv = (FAR struct bmi270_sensor_s *)lower; + + priv->interval = *interval; +#endif + + return OK; +} + +#ifndef CONFIG_SENSORS_BMI270_POLL +/**************************************************************************** + * Name: bmi270_set_interval + ****************************************************************************/ + +static int bmi270_fetch(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, FAR char *buffer, + size_t buflen) +{ + FAR struct bmi270_sensor_s *priv = NULL; + int16_t data[3]; + int ret = OK; + + priv = (FAR struct bmi270_sensor_s *)lower; + + switch (lower->type) + { + case SENSOR_TYPE_ACCELEROMETER: + { + struct sensor_accel accel; + + bmi270_getregs(&priv->base, BMI270_DATA_8, + (FAR uint8_t *)data, 6); + + accel.timestamp = sensor_get_timestamp(); + accel.x = data[0] * priv->scale; + accel.y = data[1] * priv->scale; + accel.z = data[2] * priv->scale; + + memcpy(buffer, &accel, sizeof(accel)); + ret = sizeof(accel); + + break; + } + + case SENSOR_TYPE_GYROSCOPE: + { + struct sensor_gyro gyro; + + bmi270_getregs(&priv->base, BMI270_DATA_14, + (FAR uint8_t *)data, 6); + + gyro.timestamp = sensor_get_timestamp(); + gyro.x = data[0] * priv->scale; + gyro.y = data[1] * priv->scale; + gyro.z = data[2] * priv->scale; + + memcpy(buffer, &gyro, sizeof(gyro)); + ret = sizeof(gyro); + + break; + } + + default: + { + ret = -EINVAL; + break; + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: bmi270_cotrol + ****************************************************************************/ + +static int bmi270_control(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, int cmd, + unsigned long arg) +{ + FAR struct bmi270_sensor_s *priv = NULL; + int ret = OK; + + priv = (FAR struct bmi270_sensor_s *)lower; + + switch (cmd) + { + /* Set full scale command */ + + case SNIOC_SET_SCALE_XL: + { + if (priv->lower.type == SENSOR_TYPE_GYROSCOPE) + { + ret = bmi270_gyro_scale(priv, arg); + } + else if (priv->lower.type == SENSOR_TYPE_ACCELEROMETER) + { + ret = bmi270_accel_scale(priv, arg); + } + + break; + } + + default: + { + snerr("ERROR: Unrecognized cmd: %d\n", cmd); + ret = -ENOTTY; + break; + } + } + + return ret; +} + +/**************************************************************************** + * Name: bmi270_midpoint + * + * Description: + * Find the midpoint between two numbers. + * + ****************************************************************************/ + +static uint32_t bmi270_midpoint(uint32_t a, uint32_t b) +{ + return (uint32_t)(((uint64_t)a + + (uint64_t)b + (uint64_t)1) / (uint64_t)2); +} + +/**************************************************************************** + * Name: bmi270_accel_scale + ****************************************************************************/ + +static int bmi270_accel_scale(FAR struct bmi270_sensor_s *priv, + uint8_t scale) +{ + int ret = OK; + + if (scale < bmi270_midpoint(2, 4)) + { + bmi270_putreg8(&priv->base, BMI270_ACC_RANGE, ACCEL_RANGE_2G); + priv->scale = CONSTANTS_ONE_G / 16384.f; + } + else if (scale < bmi270_midpoint(4, 8)) + { + bmi270_putreg8(&priv->base, BMI270_ACC_RANGE, ACCEL_RANGE_4G); + priv->scale = CONSTANTS_ONE_G / 8192.f; + } + else if (scale < bmi270_midpoint(8, 16)) + { + bmi270_putreg8(&priv->base, BMI270_ACC_RANGE, ACCEL_RANGE_8G); + priv->scale = CONSTANTS_ONE_G / 4096.f; + } + else + { + bmi270_putreg8(&priv->base, BMI270_ACC_RANGE, ACCEL_RANGE_16G); + priv->scale = CONSTANTS_ONE_G / 2048.f; + } + + return ret; +} + +/**************************************************************************** + * Name: bmi270_gyro_scale + ****************************************************************************/ + +static int bmi270_gyro_scale(FAR struct bmi270_sensor_s *priv, + uint16_t scale) +{ + int ret = OK; + + if (scale < bmi270_midpoint(125, 250)) + { + bmi270_putreg8(&priv->base, BMI270_GYR_RANGE, GYRO_RANGE_125); + priv->scale = (M_PI / 180.0f) * 125.f / 32768.f; + } + else if (scale < bmi270_midpoint(250, 500)) + { + bmi270_putreg8(&priv->base, BMI270_GYR_RANGE, GYRO_RANGE_250); + priv->scale = (M_PI / 180.0f) * 250.f / 32768.f; + } + else if (scale < bmi270_midpoint(500, 1000)) + { + bmi270_putreg8(&priv->base, BMI270_GYR_RANGE, GYRO_RANGE_500); + priv->scale = (M_PI / 180.0f) * 500.f / 32768.f; + } + else if (scale < bmi270_midpoint(1000, 2000)) + { + bmi270_putreg8(&priv->base, BMI270_GYR_RANGE, GYRO_RANGE_1000); + priv->scale = (M_PI / 180.0f) * 1000.f / 32768.f; + } + else + { + bmi270_putreg8(&priv->base, BMI270_GYR_RANGE, GYRO_RANGE_2000); + priv->scale = (M_PI / 180.0f) * 2000.f / 32768.f; + } + + return ret; +} + +#ifdef CONFIG_SENSORS_BMI270_POLL +/**************************************************************************** + * Name: bmi270_accel_data + * + * Description: + * Get and push accel data from struct sensor_data_s + * + * Parameter: + * priv - Internal private lower half driver instance + * buf - Point to data + * + * Return: + * OK - on success + * + ****************************************************************************/ + +static void bmi270_accel_data(FAR struct bmi270_sensor_s *priv, + FAR int16_t *buf) +{ + FAR struct sensor_lowerhalf_s *lower = &priv->lower; + struct sensor_accel accel; + uint64_t now = sensor_get_timestamp(); + + if (!priv->enabled || now - priv->last_update < priv->interval) + { + return; + } + + priv->last_update = now; + + accel.timestamp = now; + accel.x = buf[0] * priv->scale; + accel.y = buf[1] * priv->scale; + accel.z = buf[2] * priv->scale; + accel.temperature = 0; + + lower->push_event(lower->priv, &accel, sizeof(accel)); +} + +/**************************************************************************** + * Name: bmi270_gyro_data + * + * Description: + * Get and push gyro data from struct sensor_data_s + * + * Parameter: + * priv - Internal private lower half driver instance + * buf - Point to data + * + * Return: + * OK - on success + * + ****************************************************************************/ + +static void bmi270_gyro_data(FAR struct bmi270_sensor_s *priv, + FAR int16_t *buf) +{ + FAR struct sensor_lowerhalf_s *lower = &priv->lower; + struct sensor_gyro gyro; + uint64_t now = sensor_get_timestamp(); + + if (!priv->enabled || now - priv->last_update < priv->interval) + { + return; + } + + priv->last_update = now; + + gyro.timestamp = now; + gyro.x = buf[0] * priv->scale; + gyro.y = buf[1] * priv->scale; + gyro.z = buf[2] * priv->scale; + gyro.temperature = 0; + + lower->push_event(lower->priv, &gyro, sizeof(gyro)); +} + +/**************************************************************************** + * Name: bmi270_thread + * + * Description: + * Thread for performing interval measurement cycle and data read. + * + * Parameter: + * argc - Number opf arguments + * argv - Pointer to argument list + * + ****************************************************************************/ + +static int bmi270_thread(int argc, FAR char **argv) +{ + FAR struct bmi270_sensor_dev_s *dev + = (FAR struct bmi270_sensor_dev_s *)((uintptr_t)strtoul(argv[1], NULL, + 16)); + FAR struct bmi270_sensor_s *accel = &dev->priv[BMI270_ACCEL_IDX]; + FAR struct bmi270_sensor_s *gyro = &dev->priv[BMI270_GYRO_IDX]; + unsigned long min_interval; + int16_t data[6]; + int ret; + + while (true) + { + if ((!accel->enabled) && (!gyro->enabled)) + { + /* Waiting to be woken up */ + + ret = nxsem_wait(&dev->run); + if (ret < 0) + { + continue; + } + } + + /* Get data */ + + bmi270_getregs(&gyro->base, BMI270_DATA_8, (uint8_t *)data, 12); + + /* Read accel */ + + if (accel->enabled) + { + bmi270_accel_data(accel, data); + } + + /* Read gyro */ + + if (gyro->enabled) + { + bmi270_gyro_data(gyro, &data[3]); + } + + /* Sleeping thread before fetching the next sensor data */ + + min_interval = MIN(accel->interval, gyro->interval); + nxsig_usleep(min_interval); + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: bmi270_register_uorb + * + * Description: + * Register the BMI270 IMU as sensor device + * + * Input Parameters: + * devno - Instance number for driver + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_SENSORS_BMI270_I2C +int bmi270_register_uorb(int devno, FAR struct i2c_master_s *i2c, + uint8_t addr) +#else /* CONFIG_SENSORS_BMI270_SPI */ +int bmi270_register_uorb(int devno, FAR struct spi_dev_s *spi) +#endif +{ + FAR struct bmi270_sensor_dev_s *dev = NULL; + FAR struct bmi270_sensor_s *tmp = NULL; +#ifdef CONFIG_SENSORS_BMI270_POLL + FAR char *argv[2]; + char arg1[32]; +#endif + int ret = OK; + + /* Initialize the device structure. */ + + dev = (FAR struct bmi270_sensor_dev_s *)kmm_malloc(sizeof(*dev)); + if (dev == NULL) + { + snerr("ERROR: Failed to allocate instance\n"); + return -ENOMEM; + } + + memset(dev, 0, sizeof(*dev)); + nxmutex_init(&dev->lock); +#ifdef CONFIG_SENSORS_BMI270_POLL + nxsem_init(&dev->run, 0, 0); +#endif + + /* Accelerometer register */ + + tmp = &dev->priv[BMI270_ACCEL_IDX]; + tmp->dev = dev; +#ifdef CONFIG_SENSORS_BMI270_I2C + tmp->base.i2c = i2c; + tmp->base.addr = addr; +#else + tmp->base.spi = spi; +#endif + tmp->lower.ops = &g_sensor_ops; + tmp->lower.type = SENSOR_TYPE_ACCELEROMETER; + tmp->lower.nbuffer = 1; +#ifdef CONFIG_SENSORS_BMI270_POLL + tmp->enabled = false; + tmp->interval = CONFIG_SENSORS_BMI270_POLL_INTERVAL; +#endif + + ret = sensor_register(&tmp->lower, devno); + if (ret < 0) + { + snerr("sensor_register failed: %d\n", ret); + goto gyro_err; + } + + /* Gyroscope register */ + + tmp = &dev->priv[BMI270_GYRO_IDX]; + tmp->dev = dev; +#ifdef CONFIG_SENSORS_BMI270_I2C + tmp->base.i2c = i2c; + tmp->base.addr = addr; +#else + tmp->base.spi = spi; +#endif + tmp->lower.ops = &g_sensor_ops; + tmp->lower.type = SENSOR_TYPE_GYROSCOPE; + tmp->lower.nbuffer = 1; +#ifdef CONFIG_SENSORS_BMI270_POLL + tmp->enabled = false; + tmp->interval = CONFIG_SENSORS_BMI270_POLL_INTERVAL; +#endif + + ret = sensor_register(&tmp->lower, devno); + if (ret < 0) + { + snerr("sensor_register failed: %d\n", ret); + goto gyro_err; + } + +#ifdef CONFIG_SENSORS_BMI270_SPI + /* BMI270 detects communication bus is SPI by rising edge of CS. */ + + bmi270_getreg8(&tmp->base, 0x00); + bmi270_getreg8(&tmp->base, 0x00); + up_udelay(200); +#endif + + /* Initialization sequence */ + + ret = bmi270_init_seq(&tmp->base); + if (ret != 0) + { + return ret; + } + + /* Set default scale */ + + bmi270_accel_scale(&dev->priv[BMI270_ACCEL_IDX], 2); + bmi270_gyro_scale(&dev->priv[BMI270_GYRO_IDX], 2000); + +#ifdef CONFIG_SENSORS_BMI270_POLL + /* Create thread for polling sensor data */ + + snprintf(arg1, 16, "%p", dev); + argv[0] = arg1; + argv[1] = NULL; + + ret = kthread_create("bmi270_thread", SCHED_PRIORITY_DEFAULT, + CONFIG_SENSORS_BMI270_THREAD_STACKSIZE, + bmi270_thread, + argv); + if (ret < 0) + { + goto thr_err; + } +#endif + + return ret; + +#ifdef CONFIG_SENSORS_BMI270_POLL +thr_err: +#endif +#ifdef AUX_MAG_SUPPORTED + sensor_unregister(&dev->priv[BMI270_MAG_IDX].lower, devno); +mag_err: +#endif + sensor_unregister(&dev->priv[BMI270_GYRO_IDX].lower, devno); +gyro_err: + sensor_unregister(&dev->priv[BMI270_ACCEL_IDX].lower, devno); + + kmm_free(dev); + + return ret; +} diff --git a/drivers/sensors/bmm150_uorb.c b/drivers/sensors/bmm150_uorb.c new file mode 100644 index 0000000000000..30ce9b5509aa6 --- /dev/null +++ b/drivers/sensors/bmm150_uorb.c @@ -0,0 +1,767 @@ +/**************************************************************************** + * drivers/sensors/bmm150_uorb.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define BMM150_CHIPID_VAL 0x32 + +#define BMM150_CHIPID 0x40 +#define BMM150_DATA_X_LSB 0x42 +#define BMM150_DATA_X_MSB 0x43 +#define BMM150_DATA_Y_LSB 0x44 +#define BMM150_DATA_Y_MSB 0x45 +#define BMM150_DATA_Z_LSB 0x46 +#define BMM150_DATA_Z_MSB 0x47 +#define BMM150_RHALL_LSB 0x48 +#define BMM150_RHALL_MSB 0x49 +#define BMM150_IRQSTAT 0x4a +#define BMM150_POWER 0x4b +#define BMM150_MODE 0x4c +#define BMM150_INTEN 0x4d +#define BMM150_INTCFG 0x4e +#define BMM150_LOW_THR 0x4f +#define BMM150_HIGH_THR 0x50 +#define BMM150_REPXY 0x51 +#define BMM150_REPZ 0x52 + +/* TRIM registers - NVM */ + +#define BMM150_TRIM_X1 0x5d /* 0 */ +#define BMM150_TRIM_Y1 0x5e /* 1 */ +#define BMM150_TRIM_Z4_LSB 0x62 /* 5 */ +#define BMM150_TRIM_Z4_MSB 0x63 /* 6 */ +#define BMM150_TRIM_X2 0x64 /* 7 */ +#define BMM150_TRIM_Y2 0x65 /* 8 */ +#define BMM150_TRIM_Z2_LSB 0x68 /* 11 */ +#define BMM150_TRIM_Z2_MSB 0x69 /* 12 */ +#define BMM150_TRIM_Z1_LSB 0x6a /* 13 */ +#define BMM150_TRIM_Z1_MSB 0x6b /* 14 */ +#define BMM150_TRIM_XYZ1_LSB 0x6c /* 15 */ +#define BMM150_TRIM_XYZ1_MSB 0x6d /* 16 */ +#define BMM150_TRIM_Z3_LSB 0x6e /* 17 */ +#define BMM150_TRIM_Z3_MSB 0x6f /* 18 */ +#define BMM150_TRIM_XY2 0x70 /* 19 */ +#define BMM150_TRIM_XY1 0x71 /* 20 */ + +#define POWER_CONTROL (1 << 0) + +#define MODE_SELFTEST 0x01 +#define MODE_OPMODE_NORMAL (0 << 1) +#define MODE_OPMODE_FORCED (1 << 1) +#define MODE_OPMODE_SLEEP (2 << 1) +#define MODE_OPMODE_MASK (3 << 1) + +#define MODE_DATARATE_10HZ (0 << 3) +#define MODE_DATARATE_2HZ (1 << 3) +#define MODE_DATARATE_6HZ (2 << 3) +#define MODE_DATARATE_8HZ (3 << 3) +#define MODE_DATARATE_15HZ (4 << 3) +#define MODE_DATARATE_20HZ (5 << 3) +#define MODE_DATARATE_25HZ (6 << 3) +#define MODE_DATARATE_30HZ (7 << 3) + +#define MODE_ADV_SELFTEST0 (1 << 6) +#define MODE_ADV_SELFTEST1 (1 << 7) + +#define INTCFG_EN_X (1 << 3) +#define INTCFG_EN_Y (1 << 4) +#define INTCFG_EN_Z (1 << 5) + +/**************************************************************************** + * Private Type Definitions + ****************************************************************************/ + +struct bmm150_trim_s +{ + int8_t x1; + int8_t y1; + int8_t x2; + int8_t y2; + uint16_t z1; + int16_t z2; + int16_t z3; + int16_t z4; + int8_t xy1; + int8_t xy2; + uint16_t xyz1; +}; + +/* Used by the driver to manage the device */ + +struct bmm150_sensor_dev_s +{ + struct sensor_lowerhalf_s lower; + struct bmm150_trim_s trim; + bool enabled; + struct bmm150_config_s config; + uint32_t freq; + mutex_t lock; +#ifdef CONFIG_SENSORS_BMM150_POLL + unsigned long interval; + uint64_t last_update; + sem_t run; +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int bmm150_activate(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, bool enable); +#ifndef CONFIG_SENSORS_BMM150_POLL +static int bmm150_fetch(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR char *buffer, size_t buflen); +#endif +static int bmm150_set_interval(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR unsigned long *period_us); + +/* Helpers */ + +static float bmm150_getx(FAR struct bmm150_sensor_dev_s *dev, + FAR int16_t *data); +static float bmm150_gety(FAR struct bmm150_sensor_dev_s *dev, + FAR int16_t *data); +static float bmm150_getz(FAR struct bmm150_sensor_dev_s *dev, + FAR int16_t *data); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct sensor_ops_s g_bmm150_sensor_ops = +{ + NULL, /* open */ + NULL, /* close */ + bmm150_activate, + bmm150_set_interval, + NULL, /* batch */ +#ifdef CONFIG_SENSORS_BMM150_POLL + NULL, /* fetch */ +#else + bmm150_fetch, +#endif + NULL, /* selftest */ + NULL, /* set_calibvalue */ + NULL, /* calibrate */ + NULL, /* control */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: bmm150_getreg8 + * + * Description: + * Read from an 8-bit BMM150 register + * + ****************************************************************************/ + +static uint8_t bmm150_getreg8(FAR struct bmm150_sensor_dev_s *priv, + uint8_t regaddr) +{ + struct i2c_msg_s msg[2]; + uint8_t regval = 0; + int ret; + + msg[0].frequency = priv->freq; + msg[0].addr = priv->config.addr; + msg[0].flags = I2C_M_NOSTOP; + msg[0].buffer = ®addr; + msg[0].length = 1; + + msg[1].frequency = priv->freq; + msg[1].addr = priv->config.addr; + msg[1].flags = I2C_M_READ; + msg[1].buffer = ®val; + msg[1].length = 1; + + ret = I2C_TRANSFER(priv->config.i2c, msg, 2); + if (ret < 0) + { + snerr("I2C_TRANSFER failed: %d\n", ret); + } + + return regval; +} + +/**************************************************************************** + * Name: bmm150_getregs + * + * Description: + * Read cnt bytes from specified dev_addr and reg_addr + * + ****************************************************************************/ + +void bmm150_getregs(FAR struct bmm150_sensor_dev_s *priv, uint8_t regaddr, + FAR uint8_t *regval, int len) +{ + struct i2c_msg_s msg[2]; + int ret; + + msg[0].frequency = priv->freq; + msg[0].addr = priv->config.addr; + msg[0].flags = I2C_M_NOSTOP; + msg[0].buffer = ®addr; + msg[0].length = 1; + + msg[1].frequency = priv->freq; + msg[1].addr = priv->config.addr; + msg[1].flags = I2C_M_READ; + msg[1].buffer = regval; + msg[1].length = len; + + ret = I2C_TRANSFER(priv->config.i2c, msg, 2); + if (ret < 0) + { + snerr("I2C_TRANSFER failed: %d\n", ret); + } +} + +/**************************************************************************** + * Name: bmm150_putreg8 + * + * Description: + * Write to an 8-bit BMM150 register + * + ****************************************************************************/ + +static void bmm150_putreg8(FAR struct bmm150_sensor_dev_s *priv, + uint8_t regaddr, uint8_t regval) +{ + struct i2c_msg_s msg[2]; + uint8_t txbuffer[2]; + int ret; + + txbuffer[0] = regaddr; + txbuffer[1] = regval; + + msg[0].frequency = priv->freq; + msg[0].addr = priv->config.addr; + msg[0].flags = 0; + msg[0].buffer = txbuffer; + msg[0].length = 2; + + ret = I2C_TRANSFER(priv->config.i2c, msg, 1); + if (ret < 0) + { + snerr("I2C_TRANSFER failed: %d\n", ret); + } +} + +/**************************************************************************** + * Name: bmm150_initialize + * + * Description: + * Intialzie BMM150 driver + * + ****************************************************************************/ + +static int bmm150_initialzie(FAR struct bmm150_sensor_dev_s *dev) +{ + uint8_t data[21]; + uint16_t u16; + int16_t i16; + uint8_t id = 0; + int ret = OK; + + /* Set Power Control */ + + bmm150_putreg8(dev, BMM150_POWER, POWER_CONTROL); + + /* Start-Up Time */ + + up_mdelay(3); + + /* Read Chip ID */ + + id = bmm150_getreg8(dev, BMM150_CHIPID); + if (id != BMM150_CHIPID_VAL) + { + /* Chip ID is not Correct */ + + snerr("Wrong chip ID! %02x\n", id); + ret = -ENODEV; + goto errout; + } + + /* Get TRIM registers */ + + bmm150_getregs(dev, BMM150_TRIM_X1, (FAR uint8_t *)data, 20); + + dev->trim.x1 = (int8_t)data[0]; + dev->trim.y1 = (int8_t)data[1]; + dev->trim.x2 = (int8_t)data[7]; + dev->trim.y2 = (int8_t)data[8]; + u16 = ((uint16_t)(data[14] << 8) + data[11]); + dev->trim.z1 = u16; + i16 = ((int16_t)(data[12] << 8) + data[11]); + dev->trim.z2 = i16; + i16 = ((int16_t)(data[18] << 8) + data[17]); + dev->trim.z3 = i16; + i16 = ((int16_t)(data[6] << 8) + data[7]); + dev->trim.z4 = i16; + dev->trim.xy1 = (int8_t)data[20]; + dev->trim.xy2 = (int8_t)data[19]; + u16 = ((uint16_t)(data[16] << 8) + data[15]); + dev->trim.xyz1 = u16; + +errout: + + /* Clear Power Control */ + + bmm150_putreg8(dev, BMM150_POWER, 0); + + return ret; +} + +/**************************************************************************** + * Name: bmm150_activate + ****************************************************************************/ + +static int bmm150_activate(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, bool enable) +{ + FAR struct bmm150_sensor_dev_s *dev = NULL; +#ifdef CONFIG_SENSORS_BMM150_POLL + bool start_thread = false; +#endif + uint8_t val = 0; + + dev = (FAR struct bmm150_sensor_dev_s *)lower; + + nxmutex_lock(&dev->lock); + + if (enable) + { +#ifdef CONFIG_SENSORS_BMM150_POLL + if (!dev->enabled) + { + start_thread = true; + dev->last_update = sensor_get_timestamp(); + } +#endif + + /* Set Power Control */ + + bmm150_putreg8(dev, BMM150_POWER, POWER_CONTROL); + + /* Start-Up Time */ + + up_mdelay(3); + + /* Set Normal Mode */ + + val = bmm150_getreg8(dev, BMM150_MODE); + val &= ~MODE_OPMODE_MASK; + val |= MODE_OPMODE_NORMAL; + bmm150_putreg8(dev, BMM150_MODE, val); + + /* Enable XYZ - active low */ + + val = 0; + bmm150_putreg8(dev, BMM150_INTCFG, val); + } + else + { + /* Set Sleep Mode */ + + val = bmm150_getreg8(dev, BMM150_MODE); + val |= MODE_OPMODE_SLEEP; + bmm150_putreg8(dev, BMM150_MODE, val); + } + + dev->enabled = enable; + +#ifdef CONFIG_SENSORS_BMM150_POLL + if (start_thread) + { + /* Wake up the thread */ + + nxsem_post(&dev->run); + } +#endif + + nxmutex_unlock(&dev->lock); + + return OK; +} + +/**************************************************************************** + * Name: bmm150_getx + ****************************************************************************/ + +static float bmm150_getx(FAR struct bmm150_sensor_dev_s *dev, + FAR int16_t *data) +{ + float tmp = 0.0f; + float x0 = 0.0f; + float x1 = 0.0f; + float x2 = 0.0f; + float x3 = 0.0f; + float x4 = 0.0f; + + /* TODO: check overflow */ + + x0 = dev->trim.xyz1 * 16384.0f / data[3]; + tmp = x0 - 16384.0f; + x1 = dev->trim.xy2 * (tmp * tmp / 268435456.0f); + x2 = x1 + tmp * dev->trim.xy1 / 16384.0f; + x3 = dev->trim.x2 + 160.0f; + x4 = data[0] * (x2 + 256.0f) * x3; + tmp = ((x4 / 8192.0f) + dev->trim.x1 * 8.0f) / 16.0f; + + return tmp; +} + +/**************************************************************************** + * Name: bmm150_gety + ****************************************************************************/ + +static float bmm150_gety(FAR struct bmm150_sensor_dev_s *dev, + FAR int16_t *data) +{ + float tmp = 0.0f; + float y0 = 0.0f; + float y1 = 0.0f; + float y2 = 0.0f; + float y3 = 0.0f; + float y4 = 0.0f; + + /* TODO: check overflow */ + + y0 = dev->trim.xyz1 * 16384.0f / data[3]; + tmp = y0 - 16384.0f; + y1 = dev->trim.xy2 * (tmp * tmp / 268435456.0f); + y2 = y1 + tmp * dev->trim.xy1 / 16384.0f; + y3 = dev->trim.y2 + 160.0f; + y4 = data[1] * (y2 + 256.0f) * y3; + tmp = ((y4 / 8192.0f) + dev->trim.y1 * 8.0f) / 16.0f; + + return tmp; +} + +/**************************************************************************** + * Name: bmm150_getz + ****************************************************************************/ + +static float bmm150_getz(FAR struct bmm150_sensor_dev_s *dev, + FAR int16_t *data) +{ + float tmp = 0.0f; + float z0 = 0.0f; + float z1 = 0.0f; + float z2 = 0.0f; + float z3 = 0.0f; + float z4 = 0.0f; + float z5 = 0.0f; + + /* TODO: check overflow */ + + z0 = data[2] - dev->trim.z4; + z1 = data[3] - dev->trim.xyz1; + z2 = dev->trim.z3 * z1; + z3 = dev->trim.z1 * data[3] / 32768.0f; + z4 = dev->trim.z2 + z3; + z5 = z0 * 121072.0f - z2; + tmp = (z5 / (z4 * 4.0f)) / 16.0f; + + return tmp; +} + +#ifndef CONFIG_SENSORS_BMM150_POLL +/**************************************************************************** + * Name: bmm150_fetch + ****************************************************************************/ + +static int bmm150_fetch(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR char *buffer, size_t buflen) +{ + FAR struct bmm150_sensor_dev_s *dev = + (FAR struct bmm150_sensor_dev_s *)lower; + struct sensor_mag mag_data; + int16_t data[4]; + uint64_t now = sensor_get_timestamp(); + int ret = 0; + + nxmutex_lock(&dev->lock); + + if (!dev->enabled) + { + ret = -EACCES; + goto errout; + } + + if (buflen != sizeof(mag_data)) + { + ret = -EINVAL; + goto errout; + } + + /* Get data */ + + do + { + bmm150_getregs(dev, BMM150_DATA_X_LSB, (FAR uint8_t *)data, 8); + } + while (!(data[3] & 1)); + + /* Correct data */ + + data[0] >>= 3; + data[1] >>= 3; + data[2] >>= 1; + data[3] >>= 2; + + /* Get compensated data */ + + mag_data.timestamp = now; + mag_data.x = bmm150_getx(dev, data); + mag_data.y = bmm150_gety(dev, data); + mag_data.z = bmm150_getz(dev, data); + + memcpy(buffer, &mag_data, sizeof(mag_data)); + ret = sizeof(mag_data); + +errout: + nxmutex_unlock(&dev->lock); + return ret; +} +#endif + +/**************************************************************************** + * Name: bmm150_set_interval + ****************************************************************************/ + +static int bmm150_set_interval(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR unsigned long *interval) +{ +#ifdef CONFIG_SENSORS_BMM150_POLL + FAR struct bmm150_sensor_dev_s *dev = + (FAR struct bmm150_sensor_dev_s *)lower; + + dev->interval = *interval; +#endif + + return OK; +} + +#ifdef CONFIG_SENSORS_BMM150_POLL +/**************************************************************************** + * Name: bmm150_thread + * + * Description: Thread for performing interval measurement cycle and data + * read. + * + * Parameter: + * argc - Number opf arguments + * argv - Pointer to argument list + * + ****************************************************************************/ + +static int bmm150_thread(int argc, FAR char **argv) +{ + FAR struct bmm150_sensor_dev_s *dev = + (FAR struct bmm150_sensor_dev_s *)((uintptr_t)strtoul(argv[1], NULL, + 16)); + struct sensor_mag mag_data; + int16_t data[4]; + int ret = 0; + + while (true) + { + if (!dev->enabled) + { + /* Waiting to be woken up */ + + ret = nxsem_wait(&dev->run); + if (ret < 0) + { + continue; + } + } + + if (dev->enabled) + { + /* Get data */ + + bmm150_getregs(dev, BMM150_DATA_X_LSB, (FAR uint8_t *)data, 8); + + /* Correct data */ + + data[0] >>= 3; + data[1] >>= 3; + data[2] >>= 1; + data[3] >>= 2; + + /* Get compensated data */ + + mag_data.timestamp = sensor_get_timestamp(); + mag_data.x = bmm150_getx(dev, data); + mag_data.y = bmm150_gety(dev, data); + mag_data.z = bmm150_getz(dev, data); + dev->lower.push_event(dev->lower.priv, + &mag_data, sizeof(mag_data)); + } + + /* Sleeping thread before fetching the next sensor data */ + + nxsig_usleep(dev->interval); + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: bmm150_register_uorb + * + * Description: + * Register the BMM150 uorb device as 'devpath' + * + * Input Parameters: + * devno - The user specifies device number, from 0. + * config - device configuration + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int bmm150_register_uorb(int devno, FAR struct bmm150_config_s *config) +{ + FAR struct bmm150_sensor_dev_s *dev = NULL; +#ifdef CONFIG_SENSORS_BMM150_POLL + FAR char *argv[2]; + char arg1[32]; +#endif + int ret = OK; + + /* Without config info, we can't do anything. */ + + if (config == NULL) + { + return -EINVAL; + } + + /* Initialize the device structure. */ + + dev = kmm_malloc(sizeof(struct bmm150_sensor_dev_s)); + if (dev == NULL) + { + snerr("ERROR: Failed to allocate bmm150 device instance\n"); + return -ENOMEM; + } + + memset(dev, 0, sizeof(struct bmm150_sensor_dev_s)); + nxmutex_init(&dev->lock); +#ifdef CONFIG_SENSORS_BMM150_POLL + nxsem_init(&dev->run, 0, 0); +#endif + + /* Configure dev */ + + dev->config.i2c = config->i2c; + dev->config.addr = config->addr; + dev->freq = CONFIG_BMM150_I2C_FREQUENCY; + + /* Register sensor */ + + dev->lower.type = SENSOR_TYPE_MAGNETIC_FIELD; + dev->lower.ops = &g_bmm150_sensor_ops; +#ifdef CONFIG_SENSORS_BMM150_POLL + dev->enabled = false; + dev->interval = CONFIG_SENSORS_BMM150_POLL_INTERVAL; +#endif + + /* Check Device ID */ + + ret = bmm150_initialzie(dev); + if (ret < 0) + { + snerr("Failed to initialize driver: %d\n", ret); + return ret; + } + + /* Regsiter driver */ + + ret = sensor_register(&dev->lower, devno); + if (ret < 0) + { + goto mag_err; + } + +#ifdef CONFIG_SENSORS_BMM150_POLL + /* Create thread for polling sensor data */ + + snprintf(arg1, 16, "%p", dev); + argv[0] = arg1; + argv[1] = NULL; + + ret = kthread_create("bmm150_thread", SCHED_PRIORITY_DEFAULT, + CONFIG_SENSORS_BMM150_THREAD_STACKSIZE, + bmm150_thread, + argv); + if (ret < 0) + { + goto thr_err; + } +#endif + + return ret; + +#ifdef CONFIG_SENSORS_BMM150_POLL + thr_err: +#endif + sensor_unregister(&dev->lower, devno); +mag_err: + kmm_free(dev); + return ret; +} diff --git a/drivers/sensors/ds18b20_uorb.c b/drivers/sensors/ds18b20_uorb.c index 62b7a1f88743b..f17147d105d1f 100644 --- a/drivers/sensors/ds18b20_uorb.c +++ b/drivers/sensors/ds18b20_uorb.c @@ -531,7 +531,7 @@ static int ds18b20_set_alarm(FAR struct ds18b20_dev_s *dev, if (spad[DS18B20_SPAD_TH_OFFSET] != alarm->thigh || spad[DS18B20_SPAD_TL_OFFSET] != alarm->tlow) { - snerr("ERROR: Expected alarm trigger does not match, " \ + snerr("ERROR: Expected alarm trigger does not match, " "received TH: %d, TL: %d\n", spad[DS18B20_SPAD_TH_OFFSET], spad[DS18B20_SPAD_TL_OFFSET]); @@ -802,7 +802,7 @@ static int ds18b20_set_interval(FAR struct sensor_lowerhalf_s *lower, * read. * * Parameter: - * argc - Number opf arguments + * argc - Number of arguments * argv - Pointer to argument list ****************************************************************************/ diff --git a/drivers/sensors/hyt271_uorb.c b/drivers/sensors/hyt271_uorb.c index 7e3591eb3c3b8..74f0447d195df 100644 --- a/drivers/sensors/hyt271_uorb.c +++ b/drivers/sensors/hyt271_uorb.c @@ -773,7 +773,7 @@ static int hyt271_set_interval(FAR struct sensor_lowerhalf_s *lower, * read. * * Parameter: - * argc - Number opf arguments + * argc - Number of arguments * argv - Pointer to argument list ****************************************************************************/ diff --git a/drivers/sensors/lsm9ds1.c b/drivers/sensors/lsm9ds1.c index 23e578d4d1a15..ece7affa7747b 100644 --- a/drivers/sensors/lsm9ds1.c +++ b/drivers/sensors/lsm9ds1.c @@ -24,542 +24,14 @@ #include -#include -#include -#include -#include - -#include -#include -#include -#include -#include +#include "lsm9ds1_base.h" #if defined(CONFIG_I2C) && defined(CONFIG_SENSORS_LSM9DS1) -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_LSM9DS1_I2C_FREQUENCY -# define CONFIG_LSM9DS1_I2C_FREQUENCY 400000 -#endif - -/* Register Addresses *******************************************************/ - -/* Accelerometer and gyroscope registers */ - -#define LSM9DS1_ACT_THS 0x04 /* Inactivity threshold */ -#define LSM9DS1_ACT_DUR 0x05 /* Inactivity duration */ -#define LSM9DS1_INT_GEN_CFG_XL 0x06 /* Accelerometer interrupt configuration */ -#define LSM9DS1_INT_GEN_THS_X_XL 0x07 /* Accelerometer X interrupt threshold */ -#define LSM9DS1_INT_GEN_THS_Y_XL 0x08 /* Accelerometer Y interrupt threshold */ -#define LSM9DS1_INT_GEN_THS_Z_XL 0x09 /* Accelerometer Z interrupt threshold */ -#define LSM9DS1_INT_GEN_DUR_XL 0x0a /* Accelerometer interrupt duration */ -#define LSM9DS1_REFERENCE_G 0x0b /* Gyroscope reference value for high-pass filter */ -#define LSM9DS1_INT1_CTRL 0x0c /* INT1_A/G pin control */ -#define LSM9DS1_INT2_CTRL 0x0d /* INT2_A/G pin control */ -#define LSM9DS1_WHO_AM_I 0x0f /* Accelerometer and gyroscope device identification */ -#define LSM9DS1_CTRL_REG1_G 0x10 /* Gyroscope control register 1 */ -#define LSM9DS1_CTRL_REG2_G 0x11 /* Gyroscope control register 2 */ -#define LSM9DS1_CTRL_REG3_G 0x12 /* Gyroscope control register 3 */ -#define LSM9DS1_ORIENT_CFG_G 0x13 /* Gyroscope sign and orientation */ -#define LSM9DS1_INT_GEN_SRC_G 0x14 /* Gyroscope interrupt source */ -#define LSM9DS1_OUT_TEMP_L 0x15 /* Temperature low byte */ -#define LSM9DS1_OUT_TEMP_H 0x16 /* Temperature high byte */ -#define LSM9DS1_STATUS_REG 0x17 /* Status register */ -#define LSM9DS1_OUT_X_L_G 0x18 /* Gyroscope pitch (X) low byte */ -#define LSM9DS1_OUT_X_H_G 0x19 /* Gyroscope pitch (X) high byte */ -#define LSM9DS1_OUT_Y_L_G 0x1a /* Gyroscope roll (Y) low byte */ -#define LSM9DS1_OUT_Y_H_G 0x1b /* Gyroscope roll (Y) high byte */ -#define LSM9DS1_OUT_Z_L_G 0x1c /* Gyroscope yaw (Z) low byte */ -#define LSM9DS1_OUT_Z_H_G 0x1d /* Gyroscope yaw (Z) high byte */ -#define LSM9DS1_CTRL_REG4 0x1e /* Control register 4 */ -#define LSM9DS1_CTRL_REG5_XL 0x1f /* Accelerometer control register 5 */ -#define LSM9DS1_CTRL_REG6_XL 0x20 /* Accelerometer control register 6 */ -#define LSM9DS1_CTRL_REG7_XL 0x21 /* Accelerometer control register 7 */ -#define LSM9DS1_CTRL_REG8 0x22 /* Control register 8 */ -#define LSM9DS1_CTRL_REG9 0x23 /* Control register 9 */ -#define LSM9DS1_CTRL_REG10 0x24 /* Control register 10 */ -#define LSM9DS1_INT_GEN_SRC_XL 0x26 /* Accelerometer interrupt source */ -#define LSM9DS1_STATUS_REG2 0x27 /* Status register 2 */ -#define LSM9DS1_OUT_X_L_XL 0x28 /* Accelerometer X low byte */ -#define LSM9DS1_OUT_X_H_XL 0x29 /* Accelerometer X high byte */ -#define LSM9DS1_OUT_Y_L_XL 0x2a /* Accelerometer Y low byte */ -#define LSM9DS1_OUT_Y_H_XL 0x2b /* Accelerometer Y high byte */ -#define LSM9DS1_OUT_Z_L_XL 0x2c /* Accelerometer Z low byte */ -#define LSM9DS1_OUT_Z_H_XL 0x2d /* Accelerometer Z high byte */ -#define LSM9DS1_FIFO_CTRL 0x2e /* FIFO control register */ -#define LSM9DS1_FIFO_SRC 0x2f /* FIFO status control register */ -#define LSM9DS1_INT_GEN_CFG_G 0x30 /* Gyroscope interrupt configuration */ -#define LSM9DS1_INT_GEN_THS_XH_G 0x31 /* Gyroscope pitch (X) interrupt threshold high byte */ -#define LSM9DS1_INT_GEN_THS_XL_G 0x32 /* Gyroscope pitch (X) interrupt threshold low byte */ -#define LSM9DS1_INT_GEN_THS_YH_G 0x33 /* Gyroscope roll (Y) interrupt threshold high byte */ -#define LSM9DS1_INT_GEN_THS_YL_G 0x34 /* Gyroscope roll (Y) interrupt threshold low byte */ -#define LSM9DS1_INT_GEN_THS_ZH_G 0x35 /* Gyroscope yaw (Z) interrupt threshold high byte */ -#define LSM9DS1_INT_GEN_THS_ZL_G 0x36 /* Gyroscope yaw (Z) interrupt threshold low byte */ -#define LSM9DS1_INT_GEN_DUR_G 0x37 /* Gyroscope interrupt duration */ - -/* Magnetometer registers */ - -#define LSM9DS1_OFFSET_X_REG_L_M 0x05 /* X low byte offset */ -#define LSM9DS1_OFFSET_X_REG_H_M 0x06 /* X high byte offset */ -#define LSM9DS1_OFFSET_Y_REG_L_M 0x07 /* Y low byte offset */ -#define LSM9DS1_OFFSET_Y_REG_H_M 0x08 /* Y high byte offset */ -#define LSM9DS1_OFFSET_Z_REG_L_M 0x09 /* Z low byte offset */ -#define LSM9DS1_OFFSET_Z_REG_H_M 0x0a /* Z high byte offset */ -#define LSM9DS1_WHO_AM_I_M 0x0f /* Device identification */ -#define LSM9DS1_CTRL_REG1_M 0x20 /* Control register 1 */ -#define LSM9DS1_CTRL_REG2_M 0x21 /* Control register 2 */ -#define LSM9DS1_CTRL_REG3_M 0x22 /* Control register 3 */ -#define LSM9DS1_CTRL_REG4_M 0x23 /* Control register 4 */ -#define LSM9DS1_CTRL_REG5_M 0x24 /* Control register 5 */ -#define LSM9DS1_STATUS_REG_M 0x27 /* Status register */ -#define LSM9DS1_OUT_X_L_M 0x28 /* X low byte */ -#define LSM9DS1_OUT_X_H_M 0x29 /* X high byte */ -#define LSM9DS1_OUT_Y_L_M 0x2a /* Y low byte */ -#define LSM9DS1_OUT_Y_H_M 0x2b /* Y high byte */ -#define LSM9DS1_OUT_Z_L_M 0x2c /* Z low byte */ -#define LSM9DS1_OUT_Z_H_M 0x2d /* Z high byte */ -#define LSM9DS1_INT_CFG_M 0x30 /* Interrupt configuration */ -#define LSM9DS1_INT_SRC_M 0x31 /* Interrupt source */ -#define LSM9DS1_INT_THS_L_M 0x32 /* Interrupt threshold low byte */ -#define LSM9DS1_INT_THS_H_M 0x33 /* Interrupt threshold high byte */ - -/* Register Bit Definitions *************************************************/ - -/* Inactivity threshold register */ - -#define LSM9DS1_ACT_THS_ACT_THS_SHIFT 0 /* Inactivity threshold */ -#define LSM9DS1_ACT_THS_ACT_THS_MASK (127 << LSM9DS1_ACT_THS_ACT_THS_SHIFT) -#define LSM9DS1_ACT_THS_SLEEP_ON_INACT_EN (1 << 7) /* Gyroscope operating mode during inactivity */ - -/* Accelerometer interrupt configuration register */ - -#define LSM9DS1_INT_GEN_CFG_XL_XLIE_XL (1 << 0) /* X-axis low byte interrupt enable */ -#define LSM9DS1_INT_GEN_CFG_XL_XHIE_XL (1 << 1) /* X-axis high byte interrupt enable */ -#define LSM9DS1_INT_GEN_CFG_XL_YLIE_XL (1 << 2) /* Y-axis low byte interrupt enable */ -#define LSM9DS1_INT_GEN_CFG_XL_YHIE_XL (1 << 3) /* Y-axis high byte interrupt enable */ -#define LSM9DS1_INT_GEN_CFG_XL_ZLIE_XL (1 << 4) /* Z-axis low byte interrupt enable */ -#define LSM9DS1_INT_GEN_CFG_XL_ZHIE_XL (1 << 5) /* Z-axis high byte interrupt enable */ -#define LSM9DS1_INT_GEN_CFG_XL_6D (1 << 6) /* 6-direction detection function for interrupt */ -#define LSM9DS1_INT_GEN_CFG_XL_AOI_XL (1 << 7) /* AND/OR combination of interrupt events */ - -/* Accelerometer interrupt duration register */ - -#define LSM9DS1_INT_GEN_DUR_XL_DUR_XL_SHIFT 0 /* Enter/exit interrupt duration */ -#define LSM9DS1_INT_GEN_DUR_XL_DUR_XL_MASK (127 << LSM9DS1_INT_GEN_DUR_XL_DUR_XL_SHIFT) -#define LSM9DS1_INT_GEN_DUR_XL_WAIT_XL (1 << 7) /* Wait function enabled on duration counter */ - -/* INT1_A/G pin control register */ - -#define LSM9DS1_INT1_CTRL_INT1_DRDY_XL (1 << 0) /* Accelerometer data ready */ -#define LSM9DS1_INT1_CTRL_INT1_DRDY_G (1 << 1) /* Gyroscope data ready */ -#define LSM9DS1_INT1_CTRL_INT1_BOOT (1 << 2) /* Boot status available */ -#define LSM9DS1_INT1_CTRL_INT1_FTH (1 << 3) /* FIFO threshold interrupt */ -#define LSM9DS1_INT1_CTRL_INT1_OVR (1 << 4) /* Overrun interrupt */ -#define LSM9DS1_INT1_CTRL_INT1_FSS5 (1 << 5) /* FSS5 interrupt */ -#define LSM9DS1_INT1_CTRL_INT1_IG_XL (1 << 6) /* Accelerometer interrupt enable */ -#define LSM9DS1_INT1_CTRL_INT1_IG_G (1 << 7) /* Gyroscope interrupt enable */ - -/* INT2_A/G pin control register */ - -#define LSM9DS1_INT2_CTRL_INT2_DRDY_XL (1 << 0) /* Accelerometer data ready */ -#define LSM9DS1_INT2_CTRL_INT2_DRDY_G (1 << 1) /* Gyroscope data ready */ -#define LSM9DS1_INT2_CTRL_INT2_DRDY_TEMP (1 << 2) /* Temperature data ready */ -#define LSM9DS1_INT2_CTRL_INT2_FTH (1 << 3) /* FIFO threshold interrupt */ -#define LSM9DS1_INT2_CTRL_INT2_OVR (1 << 4) /* Overrun interrupt */ -#define LSM9DS1_INT2_CTRL_INT2_FSS5 (1 << 5) /* FSS5 interrupt */ -#define LSM9DS1_INT2_CTRL_INT2_INACT (1 << 7) /* Inactivity interrupt output signal */ - -/* Device identification register */ - -#define LSM9DS1_WHO_AM_I_VALUE 0x68 - -/* Gyroscope control register 1 */ - -#define LSM9DS1_CTRL_REG1_G_BW_G_SHIFT 0 /* Gyroscope bandwidth selection */ -#define LSM9DS1_CTRL_REG1_G_BW_G_MASK (3 << LSM9DS1_CTRL_REG1_G_BW_G_SHIFT) -#define LSM9DS1_CTRL_REG1_G_FS_G_SHIFT 3 /* Gyroscope full-scale selection */ -#define LSM9DS1_CTRL_REG1_G_FS_G_MASK (3 << LSM9DS1_CTRL_REG1_G_FS_G_SHIFT) -# define LSM9DS1_CTRL_REG1_G_FS_G_245DPS (0 << LSM9DS1_CTRL_REG1_G_FS_G_SHIFT) /* 245 dps */ -# define LSM9DS1_CTRL_REG1_G_FS_G_500DPS (1 << LSM9DS1_CTRL_REG1_G_FS_G_SHIFT) /* 500 dps */ -# define LSM9DS1_CTRL_REG1_G_FS_G_2000DPS (3 << LSM9DS1_CTRL_REG1_G_FS_G_SHIFT) /* 2000 dps */ - -#define LSM9DS1_CTRL_REG1_G_ODR_G_SHIFT 5 /* Gyroscope bandwidth selection */ -#define LSM9DS1_CTRL_REG1_G_ODR_G_MASK (7 << LSM9DS1_CTRL_REG1_G_ODR_G_SHIFT) -# define LSM9DS1_CTRL_REG1_G_ODR_G_POWERDOWN (0 << LSM9DS1_CTRL_REG1_G_ODR_G_SHIFT) /* Power-down mode */ -# define LSM9DS1_CTRL_REG1_G_ODR_G_14p9HZ (1 << LSM9DS1_CTRL_REG1_G_ODR_G_SHIFT) /* 14.9 Hz */ -# define LSM9DS1_CTRL_REG1_G_ODR_G_59p5HZ (2 << LSM9DS1_CTRL_REG1_G_ODR_G_SHIFT) /* 59.5 Hz */ -# define LSM9DS1_CTRL_REG1_G_ODR_G_119HZ (3 << LSM9DS1_CTRL_REG1_G_ODR_G_SHIFT) /* 119 Hz */ -# define LSM9DS1_CTRL_REG1_G_ODR_G_238HZ (4 << LSM9DS1_CTRL_REG1_G_ODR_G_SHIFT) /* 238 Hz */ -# define LSM9DS1_CTRL_REG1_G_ODR_G_476HZ (5 << LSM9DS1_CTRL_REG1_G_ODR_G_SHIFT) /* 476 Hz */ -# define LSM9DS1_CTRL_REG1_G_ODR_G_952HZ (6 << LSM9DS1_CTRL_REG1_G_ODR_G_SHIFT) /* 952 Hz */ - -/* Gyroscope control register 2 */ - -#define LSM9DS1_CTRL_REG2_G_OUT_SEL_SHIFT 0 /* Out selection configuration */ -#define LSM9DS1_CTRL_REG2_G_OUT_SEL_MASK (3 << LSM9DS1_CTRL_REG2_G_OUT_SEL_SHIFT) -#define LSM9DS1_CTRL_REG2_G_INT_SEL_SHIFT 2 /* INT selection configuration */ -#define LSM9DS1_CTRL_REG2_G_INT_SEL_MASK (3 << LSM9DS1_CTRL_REG2_G_INT_SEL_SHIFT) - -/* Gyroscope control register 3 */ - -#define LSM9DS1_CTRL_REG3_G_HPCF_G_SHIFT 0 /* Gyroscope high-pass filter cutoff frequency selection */ -#define LSM9DS1_CTRL_REG3_G_HPCF_G_MASK (15 << LSM9DS1_CTRL_REG3_G_HPCF_G_SHIFT) -#define LSM9DS1_CTRL_REG3_G_HP_EN (1 << 6) /* High-pass filter enable */ -#define LSM9DS1_CTRL_REG3_G_LP_MODE (1 << 7) /* Low-power mode enable */ - -/* Gyroscope sign and orientation register */ - -#define LSM9DS1_ORIENT_CFG_G_ORIENT_SHIFT 0 /* Directional user orientation selection */ -#define LSM9DS1_ORIENT_CFG_G_ORIENT_MASK (3 << LSM9DS1_ORIENT_CFG_G_ORIENT_SHIFT) -#define LSM9DS1_ORIENT_CFG_G_SIGNZ_G (1 << 3) /* Yaw axis (Z) angular rate sign */ -#define LSM9DS1_ORIENT_CFG_G_SIGNY_G (1 << 4) /* Roll axis (Y) angular rate sign */ -#define LSM9DS1_ORIENT_CFG_G_SIGNX_G (1 << 5) /* Pitch axis (X) angular rate sign */ - -/* Gyroscope interrupt source register */ - -#define LSM9DS1_INT_GEN_SRC_G_XL_G (1 << 0) /* Pitch (X) low */ -#define LSM9DS1_INT_GEN_SRC_G_XH_G (1 << 1) /* Pitch (X) high */ -#define LSM9DS1_INT_GEN_SRC_G_YL_G (1 << 2) /* Roll (Y) low */ -#define LSM9DS1_INT_GEN_SRC_G_YH_G (1 << 3) /* Roll (Y) high */ -#define LSM9DS1_INT_GEN_SRC_G_ZL_G (1 << 4) /* Yaw (Z) low */ -#define LSM9DS1_INT_GEN_SRC_G_ZH_G (1 << 5) /* Yaw (Z) high */ -#define LSM9DS1_INT_GEN_SRC_G_IA_G (1 << 6) /* Interrupt active */ - -/* Status register */ - -#define LSM9DS1_STATUS_REG_XLDA (1 << 0) /* Accelerometer new data available */ -#define LSM9DS1_STATUS_REG_GDA (1 << 1) /* Gyroscope new data available */ -#define LSM9DS1_STATUS_REG_TDA (1 << 2) /* Temperature sensor new data available */ -#define LSM9DS1_STATUS_REG_BOOT_STATUS (1 << 3) /* Boot running flag signal */ -#define LSM9DS1_STATUS_REG_INACT (1 << 4) /* Inactivity interrupt output signal */ -#define LSM9DS1_STATUS_REG_IG_G (1 << 5) /* Gyroscope interrupt output signal */ -#define LSM9DS1_STATUS_REG_IG_XL (1 << 6) /* Accelerometer interrupt output signal */ - -/* Control register 4 */ - -#define LSM9DS1_CTRL_REG4_4D_XL1 (1 << 0) /* 4D option enabled on interrupt */ -#define LSM9DS1_CTRL_REG4_LIR_XL1 (1 << 1) /* Latched interrupt */ -#define LSM9DS1_CTRL_REG4_XEN_G (1 << 3) /* Gyroscope's pitch axis (X) output enable */ -#define LSM9DS1_CTRL_REG4_YEN_G (1 << 4) /* Gyroscope's roll axis (Y) output enable */ -#define LSM9DS1_CTRL_REG4_ZEN_G (1 << 5) /* Gyroscope's yaw axis (Z) output enable */ - -/* Accelerometer control register 5 */ - -#define LSM9DS1_CTRL_REG5_XL_XEN_XL (1 << 3) /* Accelerometer's X-axis output enable */ -#define LSM9DS1_CTRL_REG5_XL_YEN_XL (1 << 4) /* Accelerometer's Y-axis output enable */ -#define LSM9DS1_CTRL_REG5_XL_ZEN_XL (1 << 5) /* Accelerometer's Z-axis output enable */ - -#define LSM9DS1_CTRL_REG5_XL_DEC_SHIFT 6 /* Decimation of acceleration data on OUT REG and FIFO */ -#define LSM9DS1_CTRL_REG5_XL_DEC_MASK (3 << LSM9DS1_CTRL_REG5_XL_DEC_SHIFT) -# define LSM9DS1_CTRL_REG5_XL_DEC_NODEC (0 << LSM9DS1_CTRL_REG5_XL_DEC_SHIFT) /* No decimation */ -# define LSM9DS1_CTRL_REG5_XL_DEC_2SAMPLES (1 << LSM9DS1_CTRL_REG5_XL_DEC_SHIFT) /* Update every 2 samples */ -# define LSM9DS1_CTRL_REG5_XL_DEC_4SAMPLES (2 << LSM9DS1_CTRL_REG5_XL_DEC_SHIFT) /* Update every 4 samples */ -# define LSM9DS1_CTRL_REG5_XL_DEC_8SAMPLES (3 << LSM9DS1_CTRL_REG5_XL_DEC_SHIFT) /* Update every 8 samples */ - -/* Accelerometer control register 6 */ - -#define LSM9DS1_CTRL_REG6_XL_BW_XL_SHIFT 0 /* Anti-aliasing filter bandwidth selection */ -#define LSM9DS1_CTRL_REG6_XL_BW_XL_MASK (3 << LSM9DS1_CTRL_REG6_XL_BW_XL_SHIFT) -# define LSM9DS1_CTRL_REG6_XL_BW_XL_408HZ (0 << LSM9DS1_CTRL_REG6_XL_BW_XL_SHIFT) /* 408 Hz */ -# define LSM9DS1_CTRL_REG6_XL_BW_XL_211HZ (1 << LSM9DS1_CTRL_REG6_XL_BW_XL_SHIFT) /* 211 Hz */ -# define LSM9DS1_CTRL_REG6_XL_BW_XL_105HZ (2 << LSM9DS1_CTRL_REG6_XL_BW_XL_SHIFT) /* 105 Hz */ -# define LSM9DS1_CTRL_REG6_XL_BW_XL_50HZ (3 << LSM9DS1_CTRL_REG6_XL_BW_XL_SHIFT) /* 50 Hz */ - -#define LSM9DS1_CTRL_REG6_XL_BW_SCAL_ODR (1 << 2) /* Bandwidth selection */ - -#define LSM9DS1_CTRL_REG6_XL_FS_XL_SHIFT 3 /* Accelerometer full-scale selection */ -#define LSM9DS1_CTRL_REG6_XL_FS_XL_MASK (3 << LSM9DS1_CTRL_REG6_XL_FS_XL_SHIFT) -# define LSM9DS1_CTRL_REG6_XL_FS_XL_2G (0 << LSM9DS1_CTRL_REG6_XL_FS_XL_SHIFT) /* +/- 2 g */ -# define LSM9DS1_CTRL_REG6_XL_FS_XL_16G (1 << LSM9DS1_CTRL_REG6_XL_FS_XL_SHIFT) /* +/- 16 g */ -# define LSM9DS1_CTRL_REG6_XL_FS_XL_4G (2 << LSM9DS1_CTRL_REG6_XL_FS_XL_SHIFT) /* +/- 4 g */ -# define LSM9DS1_CTRL_REG6_XL_FS_XL_8G (3 << LSM9DS1_CTRL_REG6_XL_FS_XL_SHIFT) /* +/- 8 g */ - -#define LSM9DS1_CTRL_REG6_XL_ODR_XL_SHIFT 5 /* Output data rate and power mode selection */ -#define LSM9DS1_CTRL_REG6_XL_ODR_XL_MASK (7 << LSM9DS1_CTRL_REG6_XL_ODR_XL_SHIFT) -# define LSM9DS1_CTRL_REG6_XL_ODR_XL_POWERDOWN (0 << LSM9DS1_CTRL_REG6_XL_ODR_XL_SHIFT) /* Power-down mode */ -# define LSM9DS1_CTRL_REG6_XL_ODR_XL_10HZ (1 << LSM9DS1_CTRL_REG6_XL_ODR_XL_SHIFT) /* 10 Hz */ -# define LSM9DS1_CTRL_REG6_XL_ODR_XL_50HZ (2 << LSM9DS1_CTRL_REG6_XL_ODR_XL_SHIFT) /* 50 Hz */ -# define LSM9DS1_CTRL_REG6_XL_ODR_XL_119HZ (3 << LSM9DS1_CTRL_REG6_XL_ODR_XL_SHIFT) /* 119 Hz */ -# define LSM9DS1_CTRL_REG6_XL_ODR_XL_238HZ (4 << LSM9DS1_CTRL_REG6_XL_ODR_XL_SHIFT) /* 238 Hz */ -# define LSM9DS1_CTRL_REG6_XL_ODR_XL_476HZ (5 << LSM9DS1_CTRL_REG6_XL_ODR_XL_SHIFT) /* 476 Hz */ -# define LSM9DS1_CTRL_REG6_XL_ODR_XL_952HZ (6 << LSM9DS1_CTRL_REG6_XL_ODR_XL_SHIFT) /* 952 Hz */ - -/* Accelerometer control register 7 */ - -#define LSM9DS1_CTRL_REG7_XL_HPIS1 (1 << 0) /* High-pass filter enabled */ -#define LSM9DS1_CTRL_REG7_XL_FDS (1 << 2) /* Filtered data selection */ - -#define LSM9DS1_CTRL_REG7_XL_DCF_SHIFT 5 /* Accelerometer digital filter cutoff frequency selection */ -#define LSM9DS1_CTRL_REG7_XL_DCF_MASK (3 << LSM9DS1_CTRL_REG7_XL_DCF_SHIFT) -# define LSM9DS1_CTRL_REG7_XL_DCF_ODR_DIV50 (0 << LSM9DS1_CTRL_REG7_XL_DCF_SHIFT) -# define LSM9DS1_CTRL_REG7_XL_DCF_ODR_DIV100 (1 << LSM9DS1_CTRL_REG7_XL_DCF_SHIFT) -# define LSM9DS1_CTRL_REG7_XL_DCF_ODR_DIV9 (2 << LSM9DS1_CTRL_REG7_XL_DCF_SHIFT) -# define LSM9DS1_CTRL_REG7_XL_DCF_ODR_DIV400 (3 << LSM9DS1_CTRL_REG7_XL_DCF_SHIFT) -#define LSM9DS1_CTRL_REG7_XL_HR (1 << 7) /* High resolution mode enable */ - -/* Control register 8 */ - -#define LSM9DS1_CTRL_REG8_SW_RESET (1 << 0) /* Software reset */ -#define LSM9DS1_CTRL_REG8_BLE (1 << 1) /* Big/little endian data selection */ -#define LSM9DS1_CTRL_REG8_IF_ADD_INC (1 << 2) /* Register address automatically incremented during a multibyte access */ -#define LSM9DS1_CTRL_REG8_SIM (1 << 3) /* SPI serial interface mode selection */ -#define LSM9DS1_CTRL_REG8_PP_OD (1 << 4) /* Push-pull/open-drain selection on the INT1_A/G and INT2_A/G pins */ -#define LSM9DS1_CTRL_REG8_H_LACTIVE (1 << 5) /* Interrupt activation level */ -#define LSM9DS1_CTRL_REG8_BDU (1 << 6) /* Block data update */ -#define LSM9DS1_CTRL_REG8_BOOT (1 << 7) /* Reboot memory content */ - -/* Control register 9 */ - -#define LSM9DS1_CTRL_REG9_STOP_ON_FTH (1 << 0) /* Enable FIFO threshold level use */ -#define LSM9DS1_CTRL_REG9_FIFO_EN (1 << 1) /* FIFO memory enable */ -#define LSM9DS1_CTRL_REG9_I2C_DISABLE (1 << 2) /* Disable I2C interface */ -#define LSM9DS1_CTRL_REG9_DRDY_MASK_BIT (1 << 3) /* Data available enable bit */ -#define LSM9DS1_CTRL_REG9_FIFO_TEMP_EN (1 << 4) /* Temperature data storage in FIFO enable */ -#define LSM9DS1_CTRL_REG9_SLEEP_G (1 << 6) /* Gyroscope sleep mode enable */ - -/* Control register 10 */ - -#define LSM9DS1_CTRL_REG10_ST_XL (1 << 0) /* Linear acceleration sensor self-test enable */ -#define LSM9DS1_CTRL_REG10_ST_G (1 << 2) /* Angular rate sensor self-test enable */ - -/* Accelerometer interrupt source register */ - -#define LSM9DS1_INT_GEN_SRC_XL_XL_XL (1 << 0) /* Accelerometer's X low event */ -#define LSM9DS1_INT_GEN_SRC_XL_XH_XL (1 << 1) /* Accelerometer's X high event */ -#define LSM9DS1_INT_GEN_SRC_XL_YL_XL (1 << 2) /* Accelerometer's Y low event */ -#define LSM9DS1_INT_GEN_SRC_XL_YH_XL (1 << 3) /* Accelerometer's Y high event */ -#define LSM9DS1_INT_GEN_SRC_XL_ZL_XL (1 << 4) /* Accelerometer's Z low event */ -#define LSM9DS1_INT_GEN_SRC_XL_ZH_XL (1 << 5) /* Accelerometer's Z high event */ -#define LSM9DS1_INT_GEN_SRC_XL_IA_XL (1 << 6) /* Interrupt active */ - -/* Status register 2 */ - -#define LSM9DS1_STATUS_REG2_XLDA (1 << 0) /* Accelerometer new data available */ -#define LSM9DS1_STATUS_REG2_GDA (1 << 1) /* Gyroscope new data available */ -#define LSM9DS1_STATUS_REG2_TDA (1 << 2) /* Temperature sensor new data available */ -#define LSM9DS1_STATUS_REG2_BOOT_STATUS (1 << 3) /* Boot running flag signal */ -#define LSM9DS1_STATUS_REG2_INACT (1 << 4) /* Inactivity interrupt output signal */ -#define LSM9DS1_STATUS_REG2_IG_G (1 << 5) /* Gyroscope interrupt output signal */ -#define LSM9DS1_STATUS_REG2_IG_XL (1 << 6) /* Accelerometer interrupt output signal */ - -/* FIFO control register */ - -#define LSM9DS1_FIFO_CTRL_FTH_SHIFT 0 /* FIFO threshold level setting */ -#define LSM9DS1_FIFO_CTRL_FTH_MASK (31 << LSM9DS1_FIFO_CTRL_FTH_SHIFT) -#define LSM9DS1_FIFO_CTRL_FMODE_SHIFT 5 /* FIFO mode selection bits */ -#define LSM9DS1_FIFO_CTRL_FMODE_MASK (7 << LSM9DS1_FIFO_CTRL_FMODE_SHIFT) -# define LSM9DS1_FIFO_CTRL_FMODE_BYPASS (0 << LSM9DS1_FIFO_CTRL_FMODE_SHIFT) /* Bypass mode */ -# define LSM9DS1_FIFO_CTRL_FMODE_FIFO (1 << LSM9DS1_FIFO_CTRL_FMODE_SHIFT) /* FIFO mode */ -# define LSM9DS1_FIFO_CTRL_FMODE_CONT_FIFO (3 << LSM9DS1_FIFO_CTRL_FMODE_SHIFT) /* Continuous-to-FIFO mode */ -# define LSM9DS1_FIFO_CTRL_FMODE_BYPASS_CONT (4 << LSM9DS1_FIFO_CTRL_FMODE_SHIFT) /* Bypass-to-continuous mode */ -# define LSM9DS1_FIFO_CTRL_FMODE_CONT (5 << LSM9DS1_FIFO_CTRL_FMODE_SHIFT) /* Continuous mode */ - -/* FIFO status control register */ - -#define LSM9DS1_FIFO_SRC_FSS_SHIFT 0 /* Number of unread samples stored into FIFO */ -#define LSM9DS1_FIFO_SRC_FSS_MASK (63 << LSM9DS1_FIFO_SRC_FSS_SHIFT) -#define LSM9DS1_FIFO_SRC_OVRN (1 << 6) /* FIFO overrun status */ -#define LSM9DS1_FIFO_SRC_FTH (1 << 7) /* FIFO threshold status */ - -/* Gyroscope interrupt configuration register */ - -#define LSM9DS1_INT_GEN_CFG_G_XLIE_G (1 << 0) /* Pitch (X) axis low event interrupt enable */ -#define LSM9DS1_INT_GEN_CFG_G_XHIE_G (1 << 1) /* Pitch (X) axis high event interrupt enable */ -#define LSM9DS1_INT_GEN_CFG_G_YLIE_G (1 << 2) /* Roll (Y) axis low event interrupt enable */ -#define LSM9DS1_INT_GEN_CFG_G_YHIE_G (1 << 3) /* Roll (Y) axis high event interrupt enable */ -#define LSM9DS1_INT_GEN_CFG_G_ZLIE_G (1 << 4) /* Yaw (Z) axis low event interrupt enable */ -#define LSM9DS1_INT_GEN_CFG_G_ZHIE_G (1 << 5) /* Yaw (Z) axis high event interrupt enable */ -#define LSM9DS1_INT_GEN_CFG_G_LIR_G (1 << 6) /* Latch interrupt request */ -#define LSM9DS1_INT_GEN_CFG_G_AOI_G (1 << 7) /* AND/OR combination of interrupt events */ - -/* Gyroscope interrupt threshold registers */ - -#define LSM9DS1_INT_GEN_THS_XH_G_THS_XH_G_SHIFT 0 /* X interrupt threshold high byte */ -#define LSM9DS1_INT_GEN_THS_XH_G_THS_XH_G_MASK (127 << LSM9DS1_INT_GEN_THS_XH_G_THS_XH_G_SHIFT) -#define LSM9DS1_INT_GEN_THS_XH_G_DCRM_G (1 << 7) /* Decrement or reset counter mode selection */ - -/* Gyroscope interrupt duration register */ - -#define LSM9DS1_INT_GEN_DUR_G_DUR_G_SHIFT 0 /* Enter/exit interrupt duration */ -#define LSM9DS1_INT_GEN_DUR_G_DUR_G_MASK (127 << LSM9DS1_INT_GEN_DUR_G_DUR_G_SHIFT) -#define LSM9DS1_INT_GEN_DUR_G_WAIT_G (1 << 7) /* Exit from interrupt wait function enable */ - -/* Device identification register */ - -#define LSM9DS1_WHO_AM_I_M_VALUE 0x3d - -/* Magnetometer control register 1 */ - -#define LSM9DS1_CTRL_REG1_M_ST (1 << 0) /* Self-test enable */ -#define LSM9DS1_CTRL_REG1_M_FAST_ODR (1 << 1) /* Enable data rates higher than 80 Hz */ - -#define LSM9DS1_CTRL_REG1_M_DO_SHIFT 2 /* Output data rate selection */ -#define LSM9DS1_CTRL_REG1_M_DO_MASK (7 << LSM9DS1_CTRL_REG1_M_DO_SHIFT) -# define LSM9DS1_CTRL_REG1_M_DO_0p625HZ (0 << LSM9DS1_CTRL_REG1_M_DO_SHIFT) /* 0.625 Hz */ -# define LSM9DS1_CTRL_REG1_M_DO_1p25HZ (1 << LSM9DS1_CTRL_REG1_M_DO_SHIFT) /* 1.25 Hz */ -# define LSM9DS1_CTRL_REG1_M_DO_2p5HZ (2 << LSM9DS1_CTRL_REG1_M_DO_SHIFT) /* 2.5 Hz */ -# define LSM9DS1_CTRL_REG1_M_DO_5HZ (3 << LSM9DS1_CTRL_REG1_M_DO_SHIFT) /* 5 Hz */ -# define LSM9DS1_CTRL_REG1_M_DO_10HZ (4 << LSM9DS1_CTRL_REG1_M_DO_SHIFT) /* 10 Hz */ -# define LSM9DS1_CTRL_REG1_M_DO_20HZ (5 << LSM9DS1_CTRL_REG1_M_DO_SHIFT) /* 20 Hz */ -# define LSM9DS1_CTRL_REG1_M_DO_40HZ (6 << LSM9DS1_CTRL_REG1_M_DO_SHIFT) /* 40 Hz */ -# define LSM9DS1_CTRL_REG1_M_DO_80HZ (7 << LSM9DS1_CTRL_REG1_M_DO_SHIFT) /* 80 Hz */ - -#define LSM9DS1_CTRL_REG1_M_OM_SHIFT 5 /* X and Y axes operative mode selection */ -#define LSM9DS1_CTRL_REG1_M_OM_MASK (3 << LSM9DS1_CTRL_REG1_M_OM_SHIFT) -# define LSM9DS1_CTRL_REG1_M_OM_LOW (0 << LSM9DS1_CTRL_REG1_M_OM_SHIFT) /* Low-power mode */ -# define LSM9DS1_CTRL_REG1_M_OM_MEDIUM (1 << LSM9DS1_CTRL_REG1_M_OM_SHIFT) /* Medium-performance mode */ -# define LSM9DS1_CTRL_REG1_M_OM_HIGH (2 << LSM9DS1_CTRL_REG1_M_OM_SHIFT) /* High-performance mode */ -# define LSM9DS1_CTRL_REG1_M_OM_ULTRAHIGH (3 << LSM9DS1_CTRL_REG1_M_OM_SHIFT) /* Ultra-high performance mode */ - -#define LSM9DS1_CTRL_REG1_M_TEMP_COMP (1 << 7) /* Temperature compensation enable */ - -/* Magnetometer control register 2 */ - -#define LSM9DS1_CTRL_REG2_M_SOFT_RST (1 << 2) /* Configuration register and user register reset */ -#define LSM9DS1_CTRL_REG2_M_REBOOT (1 << 3) /* Reboot memory content */ - -#define LSM9DS1_CTRL_REG2_M_FS_SHIFT 5 /* Full-scale configuration */ -#define LSM9DS1_CTRL_REG2_M_FS_MASK (3 << LSM9DS1_CTRL_REG2_M_FS_SHIFT) -# define LSM9DS1_CTRL_REG2_M_FS_4GAUSS (0 << LSM9DS1_CTRL_REG2_M_FS_SHIFT) /* +/- 4 gauss */ -# define LSM9DS1_CTRL_REG2_M_FS_8GAUSS (1 << LSM9DS1_CTRL_REG2_M_FS_SHIFT) /* +/- 8 gauss */ -# define LSM9DS1_CTRL_REG2_M_FS_12GAUSS (2 << LSM9DS1_CTRL_REG2_M_FS_SHIFT) /* +/- 12 gauss */ -# define LSM9DS1_CTRL_REG2_M_FS_16GAUSS (3 << LSM9DS1_CTRL_REG2_M_FS_SHIFT) /* +/- 16 gauss */ - -/* Magnetometer control register 3 */ - -#define LSM9DS1_CTRL_REG3_M_MD_SHIFT 0 /* Operating mode selection */ -#define LSM9DS1_CTRL_REG3_M_MD_MASK (3 << LSM9DS1_CTRL_REG3_M_MD_SHIFT) -# define LSM9DS1_CTRL_REG3_M_MD_CONT (0 << LSM9DS1_CTRL_REG3_M_MD_SHIFT) /* Continuous-conversion mode */ -# define LSM9DS1_CTRL_REG3_M_MD_SINGLE (1 << LSM9DS1_CTRL_REG3_M_MD_SHIFT) /* Single-conversion mode */ -# define LSM9DS1_CTRL_REG3_M_MD_POWERDOWN (2 << LSM9DS1_CTRL_REG3_M_MD_SHIFT) /* Power-down mode */ -# define LSM9DS1_CTRL_REG3_M_MD_POWERDOWN2 (3 << LSM9DS1_CTRL_REG3_M_MD_SHIFT) /* Power-down mode */ - -#define LSM9DS1_CTRL_REG3_M_SIM (1 << 2) /* SPI serial interface mode selection */ -#define LSM9DS1_CTRL_REG3_M_LP (1 << 5) /* Low-power mode configuration */ -#define LSM9DS1_CTRL_REG3_M_I2C_DISABLE (1 << 7) /* Disable I2C interface */ - -/* Magnetometer control register 4 */ - -#define LSM9DS1_CTRL_REG4_M_BLE (1 << 1) /* Big/little endian data selection */ - -#define LSM9DS1_CTRL_REG4_M_OMZ_SHIFT 2 /* Z-axis operative mode selection */ -#define LSM9DS1_CTRL_REG4_M_OMZ_MASK (3 << LSM9DS1_CTRL_REG4_M_OMZ_SHIFT) -# define LSM9DS1_CTRL_REG4_M_OMZ_LOW (0 << LSM9DS1_CTRL_REG4_M_OMZ_SHIFT) /* Low-power mode */ -# define LSM9DS1_CTRL_REG4_M_OMZ_MEDIUM (1 << LSM9DS1_CTRL_REG4_M_OMZ_SHIFT) /* Medium-performance mode */ -# define LSM9DS1_CTRL_REG4_M_OMZ_HIGH (2 << LSM9DS1_CTRL_REG4_M_OMZ_SHIFT) /* High-performance mode */ -# define LSM9DS1_CTRL_REG4_M_OMZ_ULTRAHIGH (3 << LSM9DS1_CTRL_REG4_M_OMZ_SHIFT) /* Ultra-high performance mode */ - -/* Magnetometer control register 5 */ - -#define LSM9DS1_CTRL_REG5_M_BDU (1 << 6) /* Block data update */ -#define LSM9DS1_CTRL_REG5_M_FAST_READ (1 << 7) /* Fast read enable */ - -/* Magnetometer status register */ - -#define LSM9DS1_STATUS_REG_M_XDA (1 << 0) /* X-axis new data available */ -#define LSM9DS1_STATUS_REG_M_YDA (1 << 1) /* Y-axis new data available */ -#define LSM9DS1_STATUS_REG_M_ZDA (1 << 2) /* Z-axis new data available */ -#define LSM9DS1_STATUS_REG_M_ZYXDA (1 << 3) /* X, Y and Z-axis new data available */ -#define LSM9DS1_STATUS_REG_M_XOR (1 << 4) /* X-axis data overrun */ -#define LSM9DS1_STATUS_REG_M_YOR (1 << 5) /* Y-axis data overrun */ -#define LSM9DS1_STATUS_REG_M_ZOR (1 << 6) /* Z-axis data overrun */ -#define LSM9DS1_STATUS_REG_M_ZYXOR (1 << 7) /* X, Y and Z-axis data overrun */ - -/* Magnetometer interrupt configuration register */ - -#define LSM9DS1_INT_CFG_M_IEN (1 << 0) /* Interrupt enable on the INT_M pin */ -#define LSM9DS1_INT_CFG_M_IEL (1 << 1) /* Latch interrupt request */ -#define LSM9DS1_INT_CFG_M_IEA (1 << 2) /* Interrupt active configuration on INT_MAG */ -#define LSM9DS1_INT_CFG_M_ZIEN (1 << 5) /* Z-axis interrupt enable */ -#define LSM9DS1_INT_CFG_M_YIEN (1 << 6) /* Y-axis interrupt enable */ -#define LSM9DS1_INT_CFG_M_XIEN (1 << 7) /* X-axis interrupt enable */ - -/* Magnetometer interrupt source register */ - -#define LSM9DS1_INT_SRC_M_INT (1 << 0) /* Interrupt occurred */ -#define LSM9DS1_INT_SRC_M_MROI (1 << 1) /* Internal measurement range overflow */ -#define LSM9DS1_INT_SRC_M_NTH_Z (1 << 2) /* Value on Z-axis exceeds threshold on negative side */ -#define LSM9DS1_INT_SRC_M_NTH_Y (1 << 3) /* Value on Y-axis exceeds threshold on negative side */ -#define LSM9DS1_INT_SRC_M_NTH_X (1 << 4) /* Value on X-axis exceeds threshold on negative side */ -#define LSM9DS1_INT_SRC_M_PTH_Z (1 << 5) /* Value on Z-axis exceeds threshold on positive side */ -#define LSM9DS1_INT_SRC_M_PTH_Y (1 << 6) /* Value on Y-axis exceeds threshold on positive side */ -#define LSM9DS1_INT_SRC_M_PTH_X (1 << 7) /* Value on X-axis exceeds threshold on positive side */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct lsm9ds1_dev_s; -struct lsm9ds1_ops_s -{ - CODE int (*config)(FAR struct lsm9ds1_dev_s *priv); - CODE int (*start)(FAR struct lsm9ds1_dev_s *priv); - CODE int (*stop)(FAR struct lsm9ds1_dev_s *priv); - CODE int (*setsamplerate)(FAR struct lsm9ds1_dev_s *priv, - uint32_t samplerate); - CODE int (*setfullscale)(FAR struct lsm9ds1_dev_s *priv, - uint32_t fullscale); -}; - -struct lsm9ds1_dev_s -{ - FAR struct i2c_master_s *i2c; /* I2C interface */ - uint8_t addr; /* I2C address */ - - FAR const struct lsm9ds1_ops_s *ops; - - uint32_t samplerate; /* Output data rate */ - uint8_t datareg; /* Output data register of X low byte */ -}; - /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -/* I2C Helpers */ - -static int lsm9ds1_readreg8(FAR struct lsm9ds1_dev_s *priv, uint8_t regaddr, - FAR uint8_t *regval); -static int lsm9ds1_writereg8(FAR struct lsm9ds1_dev_s *priv, uint8_t regaddr, - uint8_t regval); -static int lsm9ds1_modifyreg8(FAR struct lsm9ds1_dev_s *priv, - uint8_t regaddr, uint8_t clearbits, - uint8_t setbits); - -/* Other Helpers */ - -static uint32_t lsm9ds1_midpoint(uint32_t a, uint32_t b); - -/* Accelerometer Operations */ - -static int lsm9ds1accelgyro_config(FAR struct lsm9ds1_dev_s *priv); -static int lsm9ds1accel_start(FAR struct lsm9ds1_dev_s *priv); -static int lsm9ds1accel_stop(FAR struct lsm9ds1_dev_s *priv); -static int lsm9ds1accelgyro_setsamplerate(FAR struct lsm9ds1_dev_s *priv, - uint32_t samplerate); -static int lsm9ds1accel_setfullscale(FAR struct lsm9ds1_dev_s *priv, - uint32_t fullscale); - -/* Gyroscope Operations */ - -static int lsm9ds1gyro_start(FAR struct lsm9ds1_dev_s *priv); -static int lsm9ds1gyro_stop(FAR struct lsm9ds1_dev_s *priv); -static int lsm9ds1gyro_setfullscale(FAR struct lsm9ds1_dev_s *priv, - uint32_t fullscale); - -/* Magnetometer Operations */ - -static int lsm9ds1mag_config(FAR struct lsm9ds1_dev_s *priv); -static int lsm9ds1mag_start(FAR struct lsm9ds1_dev_s *priv); -static int lsm9ds1mag_stop(FAR struct lsm9ds1_dev_s *priv); -static int lsm9ds1mag_setfullscale(FAR struct lsm9ds1_dev_s *priv, - uint32_t fullscale); -static int lsm9ds1mag_setsamplerate(FAR struct lsm9ds1_dev_s *priv, - uint32_t samplerate); - /* Character Driver Methods */ static ssize_t lsm9ds1_read(FAR struct file *filep, FAR char *buffer, @@ -590,605 +62,10 @@ static const struct file_operations g_fops = lsm9ds1_ioctl, /* ioctl */ }; -static const struct lsm9ds1_ops_s g_lsm9ds1accel_ops = -{ - lsm9ds1accelgyro_config, - lsm9ds1accel_start, - lsm9ds1accel_stop, - lsm9ds1accelgyro_setsamplerate, - lsm9ds1accel_setfullscale, -}; - -static const struct lsm9ds1_ops_s g_lsm9ds1gyro_ops = -{ - lsm9ds1accelgyro_config, - lsm9ds1gyro_start, - lsm9ds1gyro_stop, - lsm9ds1accelgyro_setsamplerate, - lsm9ds1gyro_setfullscale, -}; - -static const struct lsm9ds1_ops_s g_lsm9ds1mag_ops = -{ - lsm9ds1mag_config, - lsm9ds1mag_start, - lsm9ds1mag_stop, - lsm9ds1mag_setsamplerate, - lsm9ds1mag_setfullscale, -}; - /**************************************************************************** * Private Functions ****************************************************************************/ -/**************************************************************************** - * Name: lsm9ds1_readreg8 - * - * Description: - * Read from an 8-bit register. - * - ****************************************************************************/ - -static int lsm9ds1_readreg8(FAR struct lsm9ds1_dev_s *priv, uint8_t regaddr, - FAR uint8_t *regval) -{ - struct i2c_config_s config; - int ret; - - /* Sanity check */ - - DEBUGASSERT(priv != NULL); - DEBUGASSERT(regval != NULL); - - /* Set up the I2C configuration */ - - config.frequency = CONFIG_LSM9DS1_I2C_FREQUENCY; - config.address = priv->addr; - config.addrlen = 7; - - /* Write the register address */ - - ret = i2c_write(priv->i2c, &config, ®addr, sizeof(regaddr)); - if (ret < 0) - { - snerr("ERROR: i2c_write failed: %d\n", ret); - return ret; - } - - /* Restart and read 8 bits from the register */ - - ret = i2c_read(priv->i2c, &config, regval, sizeof(*regval)); - if (ret < 0) - { - snerr("ERROR: i2c_read failed: %d\n", ret); - return ret; - } - - sninfo("addr: %02x value: %02x\n", regaddr, *regval); - return OK; -} - -/**************************************************************************** - * Name: lsm9ds1_writereg8 - * - * Description: - * Write to an 8-bit register. - * - ****************************************************************************/ - -static int lsm9ds1_writereg8(FAR struct lsm9ds1_dev_s *priv, uint8_t regaddr, - uint8_t regval) -{ - struct i2c_config_s config; - uint8_t buffer[2]; - int ret; - - /* Sanity check */ - - DEBUGASSERT(priv != NULL); - - /* Set up a 2-byte message to send */ - - buffer[0] = regaddr; - buffer[1] = regval; - - /* Set up the I2C configuration */ - - config.frequency = CONFIG_LSM9DS1_I2C_FREQUENCY; - config.address = priv->addr; - config.addrlen = 7; - - /* Write the register address followed by the data (no RESTART) */ - - ret = i2c_write(priv->i2c, &config, buffer, sizeof(buffer)); - if (ret < 0) - { - snerr("ERROR: i2c_write failed: %d\n", ret); - return ret; - } - - sninfo("addr: %02x value: %02x\n", regaddr, regval); - return OK; -} - -/**************************************************************************** - * Name: lsm9ds1_modifyreg8 - * - * Description: - * Modify an 8-bit register. - * - ****************************************************************************/ - -static int lsm9ds1_modifyreg8(FAR struct lsm9ds1_dev_s *priv, - uint8_t regaddr, - uint8_t clearbits, - uint8_t setbits) -{ - int ret; - uint8_t regval; - - /* Sanity check */ - - DEBUGASSERT(priv != NULL); - - ret = lsm9ds1_readreg8(priv, regaddr, ®val); - if (ret < 0) - { - snerr("ERROR: lsm9ds1_readreg8 failed: %d\n", ret); - return ret; - } - - regval &= ~clearbits; - regval |= setbits; - - ret = lsm9ds1_writereg8(priv, regaddr, regval); - if (ret < 0) - { - snerr("ERROR: lsm9ds1_writereg8 failed: %d\n", ret); - return ret; - } - - return OK; -} - -/**************************************************************************** - * Name: lsm9ds1_midpoint - * - * Description: - * Find the midpoint between two numbers. - * - ****************************************************************************/ - -static uint32_t lsm9ds1_midpoint(uint32_t a, uint32_t b) -{ - return (uint32_t)(((uint64_t)a + - (uint64_t)b + (uint64_t)1) / (uint64_t)2); -} - -/**************************************************************************** - * Name: lsm9ds1accelgyro_config - * - * Description: - * Configure the accelerometer and gyroscope. - * - ****************************************************************************/ - -static int lsm9ds1accelgyro_config(FAR struct lsm9ds1_dev_s *priv) -{ - int ret; - uint8_t regval; - - /* Sanity check */ - - DEBUGASSERT(priv != NULL); - - /* Get the device identification */ - - ret = lsm9ds1_readreg8(priv, LSM9DS1_WHO_AM_I, ®val); - if (ret < 0) - { - snerr("ERROR: lsm9ds1_readreg8 failed: %d\n", ret); - return ret; - } - - if (regval != LSM9DS1_WHO_AM_I_VALUE) - { - snerr("ERROR: Invalid device identification %02x\n", regval); - return -ENODEV; - } - - return OK; -} - -/**************************************************************************** - * Name: lsm9ds1accel_start - * - * Description: - * Start the accelerometer. - * - ****************************************************************************/ - -static int lsm9ds1accel_start(FAR struct lsm9ds1_dev_s *priv) -{ - uint8_t setbits; - - /* Sanity check */ - - DEBUGASSERT(priv != NULL); - - if (priv->samplerate < lsm9ds1_midpoint(10, 50)) - { - setbits = LSM9DS1_CTRL_REG6_XL_ODR_XL_10HZ; - } - else if (priv->samplerate < lsm9ds1_midpoint(50, 119)) - { - setbits = LSM9DS1_CTRL_REG6_XL_ODR_XL_50HZ; - } - else if (priv->samplerate < lsm9ds1_midpoint(119, 238)) - { - setbits = LSM9DS1_CTRL_REG6_XL_ODR_XL_119HZ; - } - else if (priv->samplerate < lsm9ds1_midpoint(238, 476)) - { - setbits = LSM9DS1_CTRL_REG6_XL_ODR_XL_238HZ; - } - else if (priv->samplerate < lsm9ds1_midpoint(476, 952)) - { - setbits = LSM9DS1_CTRL_REG6_XL_ODR_XL_476HZ; - } - else - { - setbits = LSM9DS1_CTRL_REG6_XL_ODR_XL_952HZ; - } - - return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG6_XL, - LSM9DS1_CTRL_REG6_XL_ODR_XL_MASK, setbits); -} - -/**************************************************************************** - * Name: lsm9ds1accel_stop - * - * Description: - * Stop the accelerometer. - * - ****************************************************************************/ - -static int lsm9ds1accel_stop(FAR struct lsm9ds1_dev_s *priv) -{ - /* Sanity check */ - - DEBUGASSERT(priv != NULL); - - return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG6_XL, - LSM9DS1_CTRL_REG6_XL_ODR_XL_MASK, - LSM9DS1_CTRL_REG6_XL_ODR_XL_POWERDOWN); -} - -/**************************************************************************** - * Name: lsm9ds1accelgyro_setsamplerate - * - * Description: - * Set the accelerometer or gyroscope's sample rate. - * - ****************************************************************************/ - -static int lsm9ds1accelgyro_setsamplerate(FAR struct lsm9ds1_dev_s *priv, - uint32_t samplerate) -{ - /* Sanity check */ - - DEBUGASSERT(priv != NULL); - - priv->samplerate = samplerate; - return OK; -} - -/**************************************************************************** - * Name: lsm9ds1accel_setfullscale - * - * Description: - * Set the accelerometer's full-scale range. - * - ****************************************************************************/ - -static int lsm9ds1accel_setfullscale(FAR struct lsm9ds1_dev_s *priv, - uint32_t fullscale) -{ - uint8_t setbits; - - /* Sanity check */ - - DEBUGASSERT(priv != NULL); - - if (fullscale < lsm9ds1_midpoint(2, 4)) - { - setbits = LSM9DS1_CTRL_REG6_XL_FS_XL_2G; - } - else if (fullscale < lsm9ds1_midpoint(4, 8)) - { - setbits = LSM9DS1_CTRL_REG6_XL_FS_XL_4G; - } - else if (fullscale < lsm9ds1_midpoint(8, 16)) - { - setbits = LSM9DS1_CTRL_REG6_XL_FS_XL_8G; - } - else - { - setbits = LSM9DS1_CTRL_REG6_XL_FS_XL_16G; - } - - return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG6_XL, - LSM9DS1_CTRL_REG6_XL_FS_XL_MASK, setbits); -} - -/**************************************************************************** - * Name: lsm9ds1gyro_start - * - * Description: - * Start the gyroscope. - * - ****************************************************************************/ - -static int lsm9ds1gyro_start(FAR struct lsm9ds1_dev_s *priv) -{ - uint8_t setbits; - - /* Sanity check */ - - DEBUGASSERT(priv != NULL); - - if (priv->samplerate < lsm9ds1_midpoint(14, 59)) - { - setbits = LSM9DS1_CTRL_REG1_G_ODR_G_14p9HZ; - } - else if (priv->samplerate < lsm9ds1_midpoint(59, 119)) - { - setbits = LSM9DS1_CTRL_REG1_G_ODR_G_59p5HZ; - } - else if (priv->samplerate < lsm9ds1_midpoint(119, 238)) - { - setbits = LSM9DS1_CTRL_REG1_G_ODR_G_119HZ; - } - else if (priv->samplerate < lsm9ds1_midpoint(238, 476)) - { - setbits = LSM9DS1_CTRL_REG1_G_ODR_G_238HZ; - } - else if (priv->samplerate < lsm9ds1_midpoint(476, 952)) - { - setbits = LSM9DS1_CTRL_REG1_G_ODR_G_476HZ; - } - else - { - setbits = LSM9DS1_CTRL_REG1_G_ODR_G_952HZ; - } - - return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG1_G, - LSM9DS1_CTRL_REG1_G_ODR_G_MASK, setbits); -} - -/**************************************************************************** - * Name: lsm9ds1gyro_stop - * - * Description: - * Stop the gyroscope. - * - ****************************************************************************/ - -static int lsm9ds1gyro_stop(FAR struct lsm9ds1_dev_s *priv) -{ - /* Sanity check */ - - DEBUGASSERT(priv != NULL); - - return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG1_G, - LSM9DS1_CTRL_REG1_G_ODR_G_MASK, - LSM9DS1_CTRL_REG1_G_ODR_G_POWERDOWN); -} - -/**************************************************************************** - * Name: lsm9ds1gyro_setfullscale - * - * Description: - * Set the gyroscope's full-scale range. - * - ****************************************************************************/ - -static int lsm9ds1gyro_setfullscale(FAR struct lsm9ds1_dev_s *priv, - uint32_t fullscale) -{ - uint8_t setbits; - - /* Sanity check */ - - DEBUGASSERT(priv != NULL); - - if (fullscale < lsm9ds1_midpoint(245, 500)) - { - setbits = LSM9DS1_CTRL_REG1_G_FS_G_245DPS; - } - else if (fullscale < lsm9ds1_midpoint(500, 2000)) - { - setbits = LSM9DS1_CTRL_REG1_G_FS_G_500DPS; - } - else - { - setbits = LSM9DS1_CTRL_REG1_G_FS_G_2000DPS; - } - - return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG1_G, - LSM9DS1_CTRL_REG1_G_FS_G_MASK, setbits); -} - -/**************************************************************************** - * Name: lsm9ds1mag_config - * - * Description: - * Configure the magnetometer. - * - ****************************************************************************/ - -static int lsm9ds1mag_config(FAR struct lsm9ds1_dev_s *priv) -{ - int ret; - uint8_t regval; - - /* Sanity check */ - - DEBUGASSERT(priv != NULL); - - /* Get the device identification */ - - ret = lsm9ds1_readreg8(priv, LSM9DS1_WHO_AM_I_M, ®val); - if (ret < 0) - { - snerr("ERROR: lsm9ds1_readreg8 failed: %d\n", ret); - return ret; - } - - if (regval != LSM9DS1_WHO_AM_I_M_VALUE) - { - snerr("ERROR: Invalid device identification %02x\n", regval); - return -ENODEV; - } - - return OK; -} - -/**************************************************************************** - * Name: lsm9ds1mag_start - * - * Description: - * Start the magnetometer. - * - ****************************************************************************/ - -static int lsm9ds1mag_start(FAR struct lsm9ds1_dev_s *priv) -{ - /* Sanity check */ - - DEBUGASSERT(priv != NULL); - - return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG3_M, - LSM9DS1_CTRL_REG3_M_MD_MASK, - LSM9DS1_CTRL_REG3_M_MD_CONT); -} - -/**************************************************************************** - * Name: lsm9ds1mag_stop - * - * Description: - * Stop the magnetometer. - * - ****************************************************************************/ - -static int lsm9ds1mag_stop(FAR struct lsm9ds1_dev_s *priv) -{ - /* Sanity check */ - - DEBUGASSERT(priv != NULL); - - return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG3_M, - LSM9DS1_CTRL_REG3_M_MD_MASK, - LSM9DS1_CTRL_REG3_M_MD_POWERDOWN2); -} - -/**************************************************************************** - * Name: lsm9ds1mag_setfullscale - * - * Description: - * Set the magnetometer's full-scale range. - * - ****************************************************************************/ - -static int lsm9ds1mag_setfullscale(FAR struct lsm9ds1_dev_s *priv, - uint32_t fullscale) -{ - uint8_t setbits; - - /* Sanity check */ - - DEBUGASSERT(priv != NULL); - - if (fullscale < lsm9ds1_midpoint(4, 8)) - { - setbits = LSM9DS1_CTRL_REG2_M_FS_4GAUSS; - } - else if (fullscale < lsm9ds1_midpoint(8, 12)) - { - setbits = LSM9DS1_CTRL_REG2_M_FS_8GAUSS; - } - else if (fullscale < lsm9ds1_midpoint(12, 16)) - { - setbits = LSM9DS1_CTRL_REG2_M_FS_12GAUSS; - } - else - { - setbits = LSM9DS1_CTRL_REG2_M_FS_16GAUSS; - } - - return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG2_M, - LSM9DS1_CTRL_REG2_M_FS_MASK, setbits); -} - -/**************************************************************************** - * Name: lsm9ds1mag_setsamplerate - * - * Description: - * Set the magnetometer's sample rate. - * - ****************************************************************************/ - -static int lsm9ds1mag_setsamplerate(FAR struct lsm9ds1_dev_s *priv, - uint32_t samplerate) -{ - uint8_t setbits; - - /* Sanity check */ - - DEBUGASSERT(priv != NULL); - - /* The magnetometer can change its sample rate without exiting - * power-down mode, so we don't need to save the value for later, - * unlike the accelerometer and gyroscope. - */ - - if (samplerate < lsm9ds1_midpoint(0, 1)) - { - setbits = LSM9DS1_CTRL_REG1_M_DO_0p625HZ; - } - else if (samplerate < lsm9ds1_midpoint(1, 2)) - { - setbits = LSM9DS1_CTRL_REG1_M_DO_1p25HZ; - } - else if (samplerate < lsm9ds1_midpoint(2, 5)) - { - setbits = LSM9DS1_CTRL_REG1_M_DO_2p5HZ; - } - else if (samplerate < lsm9ds1_midpoint(5, 10)) - { - setbits = LSM9DS1_CTRL_REG1_M_DO_5HZ; - } - else if (samplerate < lsm9ds1_midpoint(10, 20)) - { - setbits = LSM9DS1_CTRL_REG1_M_DO_10HZ; - } - else if (samplerate < lsm9ds1_midpoint(20, 40)) - { - setbits = LSM9DS1_CTRL_REG1_M_DO_20HZ; - } - else if (samplerate < lsm9ds1_midpoint(40, 80)) - { - setbits = LSM9DS1_CTRL_REG1_M_DO_40HZ; - } - else - { - setbits = LSM9DS1_CTRL_REG1_M_DO_80HZ; - } - - return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG1_M, - LSM9DS1_CTRL_REG1_M_DO_MASK, setbits); -} - /**************************************************************************** * Name: lsm9ds1_read * diff --git a/drivers/sensors/lsm9ds1_base.c b/drivers/sensors/lsm9ds1_base.c new file mode 100644 index 0000000000000..43ce757a96cac --- /dev/null +++ b/drivers/sensors/lsm9ds1_base.c @@ -0,0 +1,717 @@ +/**************************************************************************** + * drivers/sensors/lsm9ds1_base.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "lsm9ds1_base.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Accelerometer Operations */ + +static int lsm9ds1accelgyro_config(FAR struct lsm9ds1_dev_s *priv); +static int lsm9ds1accel_start(FAR struct lsm9ds1_dev_s *priv); +static int lsm9ds1accel_stop(FAR struct lsm9ds1_dev_s *priv); +static int lsm9ds1accelgyro_setsamplerate(FAR struct lsm9ds1_dev_s *priv, + uint32_t samplerate); +static int lsm9ds1accel_setfullscale(FAR struct lsm9ds1_dev_s *priv, + uint32_t fullscale); + +/* Gyroscope Operations */ + +static int lsm9ds1gyro_start(FAR struct lsm9ds1_dev_s *priv); +static int lsm9ds1gyro_stop(FAR struct lsm9ds1_dev_s *priv); +static int lsm9ds1gyro_setfullscale(FAR struct lsm9ds1_dev_s *priv, + uint32_t fullscale); + +/* Magnetometer Operations */ + +static int lsm9ds1mag_config(FAR struct lsm9ds1_dev_s *priv); +static int lsm9ds1mag_start(FAR struct lsm9ds1_dev_s *priv); +static int lsm9ds1mag_stop(FAR struct lsm9ds1_dev_s *priv); +static int lsm9ds1mag_setfullscale(FAR struct lsm9ds1_dev_s *priv, + uint32_t fullscale); +static int lsm9ds1mag_setsamplerate(FAR struct lsm9ds1_dev_s *priv, + uint32_t samplerate); + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +const struct lsm9ds1_ops_s g_lsm9ds1accel_ops = +{ + lsm9ds1accelgyro_config, + lsm9ds1accel_start, + lsm9ds1accel_stop, + lsm9ds1accelgyro_setsamplerate, + lsm9ds1accel_setfullscale, +}; + +const struct lsm9ds1_ops_s g_lsm9ds1gyro_ops = +{ + lsm9ds1accelgyro_config, + lsm9ds1gyro_start, + lsm9ds1gyro_stop, + lsm9ds1accelgyro_setsamplerate, + lsm9ds1gyro_setfullscale, +}; + +const struct lsm9ds1_ops_s g_lsm9ds1mag_ops = +{ + lsm9ds1mag_config, + lsm9ds1mag_start, + lsm9ds1mag_stop, + lsm9ds1mag_setsamplerate, + lsm9ds1mag_setfullscale, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lsm9ds1accelgyro_config + * + * Description: + * Configure the accelerometer and gyroscope. + * + ****************************************************************************/ + +static int lsm9ds1accelgyro_config(FAR struct lsm9ds1_dev_s *priv) +{ + uint8_t regval; + int ret; + + /* Sanity check */ + + DEBUGASSERT(priv != NULL); + + /* Get the device identification */ + + ret = lsm9ds1_readreg8(priv, LSM9DS1_WHO_AM_I, ®val); + if (ret < 0) + { + snerr("ERROR: lsm9ds1_readreg8 failed: %d\n", ret); + return ret; + } + + if (regval != LSM9DS1_WHO_AM_I_VALUE) + { + snerr("ERROR: Invalid device identification %02x\n", regval); + return -ENODEV; + } + + return OK; +} + +/**************************************************************************** + * Name: lsm9ds1accel_start + * + * Description: + * Start the accelerometer. + * + ****************************************************************************/ + +static int lsm9ds1accel_start(FAR struct lsm9ds1_dev_s *priv) +{ + uint8_t setbits; + + /* Sanity check */ + + DEBUGASSERT(priv != NULL); + + if (priv->samplerate < lsm9ds1_midpoint(10, 50)) + { + setbits = LSM9DS1_CTRL_REG6_XL_ODR_XL_10HZ; + } + else if (priv->samplerate < lsm9ds1_midpoint(50, 119)) + { + setbits = LSM9DS1_CTRL_REG6_XL_ODR_XL_50HZ; + } + else if (priv->samplerate < lsm9ds1_midpoint(119, 238)) + { + setbits = LSM9DS1_CTRL_REG6_XL_ODR_XL_119HZ; + } + else if (priv->samplerate < lsm9ds1_midpoint(238, 476)) + { + setbits = LSM9DS1_CTRL_REG6_XL_ODR_XL_238HZ; + } + else if (priv->samplerate < lsm9ds1_midpoint(476, 952)) + { + setbits = LSM9DS1_CTRL_REG6_XL_ODR_XL_476HZ; + } + else + { + setbits = LSM9DS1_CTRL_REG6_XL_ODR_XL_952HZ; + } + + return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG6_XL, + LSM9DS1_CTRL_REG6_XL_ODR_XL_MASK, setbits); +} + +/**************************************************************************** + * Name: lsm9ds1accel_stop + * + * Description: + * Stop the accelerometer. + * + ****************************************************************************/ + +static int lsm9ds1accel_stop(FAR struct lsm9ds1_dev_s *priv) +{ + /* Sanity check */ + + DEBUGASSERT(priv != NULL); + + return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG6_XL, + LSM9DS1_CTRL_REG6_XL_ODR_XL_MASK, + LSM9DS1_CTRL_REG6_XL_ODR_XL_POWERDOWN); +} + +/**************************************************************************** + * Name: lsm9ds1accelgyro_setsamplerate + * + * Description: + * Set the accelerometer or gyroscope's sample rate. + * + ****************************************************************************/ + +static int lsm9ds1accelgyro_setsamplerate(FAR struct lsm9ds1_dev_s *priv, + uint32_t samplerate) +{ + /* Sanity check */ + + DEBUGASSERT(priv != NULL); + + priv->samplerate = samplerate; + return OK; +} + +/**************************************************************************** + * Name: lsm9ds1accel_setfullscale + * + * Description: + * Set the accelerometer's full-scale range. + * + ****************************************************************************/ + +static int lsm9ds1accel_setfullscale(FAR struct lsm9ds1_dev_s *priv, + uint32_t fullscale) +{ + uint8_t setbits; + + /* Sanity check */ + + DEBUGASSERT(priv != NULL); + + if (fullscale < lsm9ds1_midpoint(2, 4)) + { + setbits = LSM9DS1_CTRL_REG6_XL_FS_XL_2G; + } + else if (fullscale < lsm9ds1_midpoint(4, 8)) + { + setbits = LSM9DS1_CTRL_REG6_XL_FS_XL_4G; + } + else if (fullscale < lsm9ds1_midpoint(8, 16)) + { + setbits = LSM9DS1_CTRL_REG6_XL_FS_XL_8G; + } + else + { + setbits = LSM9DS1_CTRL_REG6_XL_FS_XL_16G; + } + + return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG6_XL, + LSM9DS1_CTRL_REG6_XL_FS_XL_MASK, setbits); +} + +/**************************************************************************** + * Name: lsm9ds1gyro_start + * + * Description: + * Start the gyroscope. + * + ****************************************************************************/ + +static int lsm9ds1gyro_start(FAR struct lsm9ds1_dev_s *priv) +{ + uint8_t setbits; + + /* Sanity check */ + + DEBUGASSERT(priv != NULL); + + if (priv->samplerate < lsm9ds1_midpoint(14, 59)) + { + setbits = LSM9DS1_CTRL_REG1_G_ODR_G_14p9HZ; + } + else if (priv->samplerate < lsm9ds1_midpoint(59, 119)) + { + setbits = LSM9DS1_CTRL_REG1_G_ODR_G_59p5HZ; + } + else if (priv->samplerate < lsm9ds1_midpoint(119, 238)) + { + setbits = LSM9DS1_CTRL_REG1_G_ODR_G_119HZ; + } + else if (priv->samplerate < lsm9ds1_midpoint(238, 476)) + { + setbits = LSM9DS1_CTRL_REG1_G_ODR_G_238HZ; + } + else if (priv->samplerate < lsm9ds1_midpoint(476, 952)) + { + setbits = LSM9DS1_CTRL_REG1_G_ODR_G_476HZ; + } + else + { + setbits = LSM9DS1_CTRL_REG1_G_ODR_G_952HZ; + } + + return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG1_G, + LSM9DS1_CTRL_REG1_G_ODR_G_MASK, setbits); +} + +/**************************************************************************** + * Name: lsm9ds1gyro_stop + * + * Description: + * Stop the gyroscope. + * + ****************************************************************************/ + +static int lsm9ds1gyro_stop(FAR struct lsm9ds1_dev_s *priv) +{ + /* Sanity check */ + + DEBUGASSERT(priv != NULL); + + return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG1_G, + LSM9DS1_CTRL_REG1_G_ODR_G_MASK, + LSM9DS1_CTRL_REG1_G_ODR_G_POWERDOWN); +} + +/**************************************************************************** + * Name: lsm9ds1gyro_setfullscale + * + * Description: + * Set the gyroscope's full-scale range. + * + ****************************************************************************/ + +static int lsm9ds1gyro_setfullscale(FAR struct lsm9ds1_dev_s *priv, + uint32_t fullscale) +{ + uint8_t setbits; + + /* Sanity check */ + + DEBUGASSERT(priv != NULL); + + if (fullscale < lsm9ds1_midpoint(245, 500)) + { + setbits = LSM9DS1_CTRL_REG1_G_FS_G_245DPS; + } + else if (fullscale < lsm9ds1_midpoint(500, 2000)) + { + setbits = LSM9DS1_CTRL_REG1_G_FS_G_500DPS; + } + else + { + setbits = LSM9DS1_CTRL_REG1_G_FS_G_2000DPS; + } + + return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG1_G, + LSM9DS1_CTRL_REG1_G_FS_G_MASK, setbits); +} + +/**************************************************************************** + * Name: lsm9ds1mag_config + * + * Description: + * Configure the magnetometer. + * + ****************************************************************************/ + +static int lsm9ds1mag_config(FAR struct lsm9ds1_dev_s *priv) +{ + uint8_t regval; + int ret; + + /* Sanity check */ + + DEBUGASSERT(priv != NULL); + + /* Get the device identification */ + + ret = lsm9ds1_readreg8(priv, LSM9DS1_WHO_AM_I_M, ®val); + if (ret < 0) + { + snerr("ERROR: lsm9ds1_readreg8 failed: %d\n", ret); + return ret; + } + + if (regval != LSM9DS1_WHO_AM_I_M_VALUE) + { + snerr("ERROR: Invalid device identification %02x\n", regval); + return -ENODEV; + } + + return OK; +} + +/**************************************************************************** + * Name: lsm9ds1mag_start + * + * Description: + * Start the magnetometer. + * + ****************************************************************************/ + +static int lsm9ds1mag_start(FAR struct lsm9ds1_dev_s *priv) +{ + /* Sanity check */ + + DEBUGASSERT(priv != NULL); + + return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG3_M, + LSM9DS1_CTRL_REG3_M_MD_MASK, + LSM9DS1_CTRL_REG3_M_MD_CONT); +} + +/**************************************************************************** + * Name: lsm9ds1mag_stop + * + * Description: + * Stop the magnetometer. + * + ****************************************************************************/ + +static int lsm9ds1mag_stop(FAR struct lsm9ds1_dev_s *priv) +{ + /* Sanity check */ + + DEBUGASSERT(priv != NULL); + + return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG3_M, + LSM9DS1_CTRL_REG3_M_MD_MASK, + LSM9DS1_CTRL_REG3_M_MD_POWERDOWN2); +} + +/**************************************************************************** + * Name: lsm9ds1mag_setfullscale + * + * Description: + * Set the magnetometer's full-scale range. + * + ****************************************************************************/ + +static int lsm9ds1mag_setfullscale(FAR struct lsm9ds1_dev_s *priv, + uint32_t fullscale) +{ + uint8_t setbits; + + /* Sanity check */ + + DEBUGASSERT(priv != NULL); + + if (fullscale < lsm9ds1_midpoint(4, 8)) + { + setbits = LSM9DS1_CTRL_REG2_M_FS_4GAUSS; + } + else if (fullscale < lsm9ds1_midpoint(8, 12)) + { + setbits = LSM9DS1_CTRL_REG2_M_FS_8GAUSS; + } + else if (fullscale < lsm9ds1_midpoint(12, 16)) + { + setbits = LSM9DS1_CTRL_REG2_M_FS_12GAUSS; + } + else + { + setbits = LSM9DS1_CTRL_REG2_M_FS_16GAUSS; + } + + return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG2_M, + LSM9DS1_CTRL_REG2_M_FS_MASK, setbits); +} + +/**************************************************************************** + * Name: lsm9ds1mag_setsamplerate + * + * Description: + * Set the magnetometer's sample rate. + * + ****************************************************************************/ + +static int lsm9ds1mag_setsamplerate(FAR struct lsm9ds1_dev_s *priv, + uint32_t samplerate) +{ + uint8_t setbits; + + /* Sanity check */ + + DEBUGASSERT(priv != NULL); + + /* The magnetometer can change its sample rate without exiting + * power-down mode, so we don't need to save the value for later, + * unlike the accelerometer and gyroscope. + */ + + if (samplerate < lsm9ds1_midpoint(0, 1)) + { + setbits = LSM9DS1_CTRL_REG1_M_DO_0p625HZ; + } + else if (samplerate < lsm9ds1_midpoint(1, 2)) + { + setbits = LSM9DS1_CTRL_REG1_M_DO_1p25HZ; + } + else if (samplerate < lsm9ds1_midpoint(2, 5)) + { + setbits = LSM9DS1_CTRL_REG1_M_DO_2p5HZ; + } + else if (samplerate < lsm9ds1_midpoint(5, 10)) + { + setbits = LSM9DS1_CTRL_REG1_M_DO_5HZ; + } + else if (samplerate < lsm9ds1_midpoint(10, 20)) + { + setbits = LSM9DS1_CTRL_REG1_M_DO_10HZ; + } + else if (samplerate < lsm9ds1_midpoint(20, 40)) + { + setbits = LSM9DS1_CTRL_REG1_M_DO_20HZ; + } + else if (samplerate < lsm9ds1_midpoint(40, 80)) + { + setbits = LSM9DS1_CTRL_REG1_M_DO_40HZ; + } + else + { + setbits = LSM9DS1_CTRL_REG1_M_DO_80HZ; + } + + return lsm9ds1_modifyreg8(priv, LSM9DS1_CTRL_REG1_M, + LSM9DS1_CTRL_REG1_M_DO_MASK, setbits); +} + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lsm9ds1_readreg8 + * + * Description: + * Read from an 8-bit register. + * + ****************************************************************************/ + +int lsm9ds1_readreg8(FAR struct lsm9ds1_dev_s *priv, + uint8_t regaddr, FAR uint8_t *regval) +{ + struct i2c_config_s config; + int ret; + + /* Sanity check */ + + DEBUGASSERT(priv != NULL); + DEBUGASSERT(regval != NULL); + + /* Set up the I2C configuration */ + + config.frequency = CONFIG_LSM9DS1_I2C_FREQUENCY; + config.address = priv->addr; + config.addrlen = 7; + + /* Write the register address */ + + ret = i2c_write(priv->i2c, &config, ®addr, sizeof(regaddr)); + if (ret < 0) + { + snerr("ERROR: i2c_write failed: %d\n", ret); + return ret; + } + + /* Restart and read 8 bits from the register */ + + ret = i2c_read(priv->i2c, &config, regval, sizeof(*regval)); + if (ret < 0) + { + snerr("ERROR: i2c_read failed: %d\n", ret); + return ret; + } + + sninfo("addr: %02x value: %02x\n", regaddr, *regval); + return OK; +} + +/**************************************************************************** + * Name: lsm9ds1_readreg + * + * Description: + * Read bytes from registers + * + ****************************************************************************/ + +int lsm9ds1_readreg(FAR struct lsm9ds1_dev_s *priv, + uint8_t regaddr, FAR uint8_t *regval, uint8_t len) +{ + struct i2c_config_s config; + int ret; + + /* Sanity check */ + + DEBUGASSERT(priv != NULL); + DEBUGASSERT(regval != NULL); + + /* Set up the I2C configuration */ + + config.frequency = CONFIG_LSM9DS1_I2C_FREQUENCY; + config.address = priv->addr; + config.addrlen = 7; + + /* Write the register address */ + + ret = i2c_write(priv->i2c, &config, ®addr, sizeof(regaddr)); + if (ret < 0) + { + snerr("ERROR: i2c_write failed: %d\n", ret); + return ret; + } + + /* Restart and read 8 bits from the register */ + + ret = i2c_read(priv->i2c, &config, regval, sizeof(*regval) * len); + if (ret < 0) + { + snerr("ERROR: i2c_read failed: %d\n", ret); + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: lsm9ds1_writereg8 + * + * Description: + * Write to an 8-bit register. + * + ****************************************************************************/ + +int lsm9ds1_writereg8(FAR struct lsm9ds1_dev_s *priv, + uint8_t regaddr, uint8_t regval) +{ + struct i2c_config_s config; + uint8_t buffer[2]; + int ret; + + /* Sanity check */ + + DEBUGASSERT(priv != NULL); + + /* Set up a 2-byte message to send */ + + buffer[0] = regaddr; + buffer[1] = regval; + + /* Set up the I2C configuration */ + + config.frequency = CONFIG_LSM9DS1_I2C_FREQUENCY; + config.address = priv->addr; + config.addrlen = 7; + + /* Write the register address followed by the data (no RESTART) */ + + ret = i2c_write(priv->i2c, &config, buffer, sizeof(buffer)); + if (ret < 0) + { + snerr("ERROR: i2c_write failed: %d\n", ret); + return ret; + } + + sninfo("addr: %02x value: %02x\n", regaddr, regval); + return OK; +} + +/**************************************************************************** + * Name: lsm9ds1_modifyreg8 + * + * Description: + * Modify an 8-bit register. + * + ****************************************************************************/ + +int lsm9ds1_modifyreg8(FAR struct lsm9ds1_dev_s *priv, + uint8_t regaddr, uint8_t clearbits, + uint8_t setbits) +{ + uint8_t regval; + int ret; + + /* Sanity check */ + + DEBUGASSERT(priv != NULL); + + ret = lsm9ds1_readreg8(priv, regaddr, ®val); + if (ret < 0) + { + snerr("ERROR: lsm9ds1_readreg8 failed: %d\n", ret); + return ret; + } + + regval &= ~clearbits; + regval |= setbits; + + ret = lsm9ds1_writereg8(priv, regaddr, regval); + if (ret < 0) + { + snerr("ERROR: lsm9ds1_writereg8 failed: %d\n", ret); + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: lsm9ds1_midpoint + * + * Description: + * Find the midpoint between two numbers. + * + ****************************************************************************/ + +uint32_t lsm9ds1_midpoint(uint32_t a, uint32_t b) +{ + return (uint32_t)(((uint64_t)a + + (uint64_t)b + (uint64_t)1) / (uint64_t)2); +} + diff --git a/drivers/sensors/lsm9ds1_base.h b/drivers/sensors/lsm9ds1_base.h new file mode 100644 index 0000000000000..e972d65670eac --- /dev/null +++ b/drivers/sensors/lsm9ds1_base.h @@ -0,0 +1,537 @@ +/**************************************************************************** + * drivers/sensors/lsm9ds1_base.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_SENSORS_LSM9DS1_COMMOM_H +#define __INCLUDE_NUTTX_SENSORS_LSM9DS1_COMMOM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Addresses *******************************************************/ + +/* Accelerometer and gyroscope registers */ + +#define LSM9DS1_ACT_THS 0x04 /* Inactivity threshold */ +#define LSM9DS1_ACT_DUR 0x05 /* Inactivity duration */ +#define LSM9DS1_INT_GEN_CFG_XL 0x06 /* Accelerometer interrupt configuration */ +#define LSM9DS1_INT_GEN_THS_X_XL 0x07 /* Accelerometer X interrupt threshold */ +#define LSM9DS1_INT_GEN_THS_Y_XL 0x08 /* Accelerometer Y interrupt threshold */ +#define LSM9DS1_INT_GEN_THS_Z_XL 0x09 /* Accelerometer Z interrupt threshold */ +#define LSM9DS1_INT_GEN_DUR_XL 0x0a /* Accelerometer interrupt duration */ +#define LSM9DS1_REFERENCE_G 0x0b /* Gyroscope reference value for high-pass filter */ +#define LSM9DS1_INT1_CTRL 0x0c /* INT1_A/G pin control */ +#define LSM9DS1_INT2_CTRL 0x0d /* INT2_A/G pin control */ +#define LSM9DS1_WHO_AM_I 0x0f /* Accelerometer and gyroscope device identification */ +#define LSM9DS1_CTRL_REG1_G 0x10 /* Gyroscope control register 1 */ +#define LSM9DS1_CTRL_REG2_G 0x11 /* Gyroscope control register 2 */ +#define LSM9DS1_CTRL_REG3_G 0x12 /* Gyroscope control register 3 */ +#define LSM9DS1_ORIENT_CFG_G 0x13 /* Gyroscope sign and orientation */ +#define LSM9DS1_INT_GEN_SRC_G 0x14 /* Gyroscope interrupt source */ +#define LSM9DS1_OUT_TEMP_L 0x15 /* Temperature low byte */ +#define LSM9DS1_OUT_TEMP_H 0x16 /* Temperature high byte */ +#define LSM9DS1_STATUS_REG 0x17 /* Status register */ +#define LSM9DS1_OUT_X_L_G 0x18 /* Gyroscope pitch (X) low byte */ +#define LSM9DS1_OUT_X_H_G 0x19 /* Gyroscope pitch (X) high byte */ +#define LSM9DS1_OUT_Y_L_G 0x1a /* Gyroscope roll (Y) low byte */ +#define LSM9DS1_OUT_Y_H_G 0x1b /* Gyroscope roll (Y) high byte */ +#define LSM9DS1_OUT_Z_L_G 0x1c /* Gyroscope yaw (Z) low byte */ +#define LSM9DS1_OUT_Z_H_G 0x1d /* Gyroscope yaw (Z) high byte */ +#define LSM9DS1_CTRL_REG4 0x1e /* Control register 4 */ +#define LSM9DS1_CTRL_REG5_XL 0x1f /* Accelerometer control register 5 */ +#define LSM9DS1_CTRL_REG6_XL 0x20 /* Accelerometer control register 6 */ +#define LSM9DS1_CTRL_REG7_XL 0x21 /* Accelerometer control register 7 */ +#define LSM9DS1_CTRL_REG8 0x22 /* Control register 8 */ +#define LSM9DS1_CTRL_REG9 0x23 /* Control register 9 */ +#define LSM9DS1_CTRL_REG10 0x24 /* Control register 10 */ +#define LSM9DS1_INT_GEN_SRC_XL 0x26 /* Accelerometer interrupt source */ +#define LSM9DS1_STATUS_REG2 0x27 /* Status register 2 */ +#define LSM9DS1_OUT_X_L_XL 0x28 /* Accelerometer X low byte */ +#define LSM9DS1_OUT_X_H_XL 0x29 /* Accelerometer X high byte */ +#define LSM9DS1_OUT_Y_L_XL 0x2a /* Accelerometer Y low byte */ +#define LSM9DS1_OUT_Y_H_XL 0x2b /* Accelerometer Y high byte */ +#define LSM9DS1_OUT_Z_L_XL 0x2c /* Accelerometer Z low byte */ +#define LSM9DS1_OUT_Z_H_XL 0x2d /* Accelerometer Z high byte */ +#define LSM9DS1_FIFO_CTRL 0x2e /* FIFO control register */ +#define LSM9DS1_FIFO_SRC 0x2f /* FIFO status control register */ +#define LSM9DS1_INT_GEN_CFG_G 0x30 /* Gyroscope interrupt configuration */ +#define LSM9DS1_INT_GEN_THS_XH_G 0x31 /* Gyroscope pitch (X) interrupt threshold high byte */ +#define LSM9DS1_INT_GEN_THS_XL_G 0x32 /* Gyroscope pitch (X) interrupt threshold low byte */ +#define LSM9DS1_INT_GEN_THS_YH_G 0x33 /* Gyroscope roll (Y) interrupt threshold high byte */ +#define LSM9DS1_INT_GEN_THS_YL_G 0x34 /* Gyroscope roll (Y) interrupt threshold low byte */ +#define LSM9DS1_INT_GEN_THS_ZH_G 0x35 /* Gyroscope yaw (Z) interrupt threshold high byte */ +#define LSM9DS1_INT_GEN_THS_ZL_G 0x36 /* Gyroscope yaw (Z) interrupt threshold low byte */ +#define LSM9DS1_INT_GEN_DUR_G 0x37 /* Gyroscope interrupt duration */ + +/* Magnetometer registers */ + +#define LSM9DS1_OFFSET_X_REG_L_M 0x05 /* X low byte offset */ +#define LSM9DS1_OFFSET_X_REG_H_M 0x06 /* X high byte offset */ +#define LSM9DS1_OFFSET_Y_REG_L_M 0x07 /* Y low byte offset */ +#define LSM9DS1_OFFSET_Y_REG_H_M 0x08 /* Y high byte offset */ +#define LSM9DS1_OFFSET_Z_REG_L_M 0x09 /* Z low byte offset */ +#define LSM9DS1_OFFSET_Z_REG_H_M 0x0a /* Z high byte offset */ +#define LSM9DS1_WHO_AM_I_M 0x0f /* Device identification */ +#define LSM9DS1_CTRL_REG1_M 0x20 /* Control register 1 */ +#define LSM9DS1_CTRL_REG2_M 0x21 /* Control register 2 */ +#define LSM9DS1_CTRL_REG3_M 0x22 /* Control register 3 */ +#define LSM9DS1_CTRL_REG4_M 0x23 /* Control register 4 */ +#define LSM9DS1_CTRL_REG5_M 0x24 /* Control register 5 */ +#define LSM9DS1_STATUS_REG_M 0x27 /* Status register */ +#define LSM9DS1_OUT_X_L_M 0x28 /* X low byte */ +#define LSM9DS1_OUT_X_H_M 0x29 /* X high byte */ +#define LSM9DS1_OUT_Y_L_M 0x2a /* Y low byte */ +#define LSM9DS1_OUT_Y_H_M 0x2b /* Y high byte */ +#define LSM9DS1_OUT_Z_L_M 0x2c /* Z low byte */ +#define LSM9DS1_OUT_Z_H_M 0x2d /* Z high byte */ +#define LSM9DS1_INT_CFG_M 0x30 /* Interrupt configuration */ +#define LSM9DS1_INT_SRC_M 0x31 /* Interrupt source */ +#define LSM9DS1_INT_THS_L_M 0x32 /* Interrupt threshold low byte */ +#define LSM9DS1_INT_THS_H_M 0x33 /* Interrupt threshold high byte */ + +/* Register Bit Definitions *************************************************/ + +/* Inactivity threshold register */ + +#define LSM9DS1_ACT_THS_ACT_THS_SHIFT 0 /* Inactivity threshold */ +#define LSM9DS1_ACT_THS_ACT_THS_MASK (127 << LSM9DS1_ACT_THS_ACT_THS_SHIFT) +#define LSM9DS1_ACT_THS_SLEEP_ON_INACT_EN (1 << 7) /* Gyroscope operating mode during inactivity */ + +/* Accelerometer interrupt configuration register */ + +#define LSM9DS1_INT_GEN_CFG_XL_XLIE_XL (1 << 0) /* X-axis low byte interrupt enable */ +#define LSM9DS1_INT_GEN_CFG_XL_XHIE_XL (1 << 1) /* X-axis high byte interrupt enable */ +#define LSM9DS1_INT_GEN_CFG_XL_YLIE_XL (1 << 2) /* Y-axis low byte interrupt enable */ +#define LSM9DS1_INT_GEN_CFG_XL_YHIE_XL (1 << 3) /* Y-axis high byte interrupt enable */ +#define LSM9DS1_INT_GEN_CFG_XL_ZLIE_XL (1 << 4) /* Z-axis low byte interrupt enable */ +#define LSM9DS1_INT_GEN_CFG_XL_ZHIE_XL (1 << 5) /* Z-axis high byte interrupt enable */ +#define LSM9DS1_INT_GEN_CFG_XL_6D (1 << 6) /* 6-direction detection function for interrupt */ +#define LSM9DS1_INT_GEN_CFG_XL_AOI_XL (1 << 7) /* AND/OR combination of interrupt events */ + +/* Accelerometer interrupt duration register */ + +#define LSM9DS1_INT_GEN_DUR_XL_DUR_XL_SHIFT 0 /* Enter/exit interrupt duration */ +#define LSM9DS1_INT_GEN_DUR_XL_DUR_XL_MASK (127 << LSM9DS1_INT_GEN_DUR_XL_DUR_XL_SHIFT) +#define LSM9DS1_INT_GEN_DUR_XL_WAIT_XL (1 << 7) /* Wait function enabled on duration counter */ + +/* INT1_A/G pin control register */ + +#define LSM9DS1_INT1_CTRL_INT1_DRDY_XL (1 << 0) /* Accelerometer data ready */ +#define LSM9DS1_INT1_CTRL_INT1_DRDY_G (1 << 1) /* Gyroscope data ready */ +#define LSM9DS1_INT1_CTRL_INT1_BOOT (1 << 2) /* Boot status available */ +#define LSM9DS1_INT1_CTRL_INT1_FTH (1 << 3) /* FIFO threshold interrupt */ +#define LSM9DS1_INT1_CTRL_INT1_OVR (1 << 4) /* Overrun interrupt */ +#define LSM9DS1_INT1_CTRL_INT1_FSS5 (1 << 5) /* FSS5 interrupt */ +#define LSM9DS1_INT1_CTRL_INT1_IG_XL (1 << 6) /* Accelerometer interrupt enable */ +#define LSM9DS1_INT1_CTRL_INT1_IG_G (1 << 7) /* Gyroscope interrupt enable */ + +/* INT2_A/G pin control register */ + +#define LSM9DS1_INT2_CTRL_INT2_DRDY_XL (1 << 0) /* Accelerometer data ready */ +#define LSM9DS1_INT2_CTRL_INT2_DRDY_G (1 << 1) /* Gyroscope data ready */ +#define LSM9DS1_INT2_CTRL_INT2_DRDY_TEMP (1 << 2) /* Temperature data ready */ +#define LSM9DS1_INT2_CTRL_INT2_FTH (1 << 3) /* FIFO threshold interrupt */ +#define LSM9DS1_INT2_CTRL_INT2_OVR (1 << 4) /* Overrun interrupt */ +#define LSM9DS1_INT2_CTRL_INT2_FSS5 (1 << 5) /* FSS5 interrupt */ +#define LSM9DS1_INT2_CTRL_INT2_INACT (1 << 7) /* Inactivity interrupt output signal */ + +/* Device identification register */ + +#define LSM9DS1_WHO_AM_I_VALUE 0x68 + +/* Gyroscope control register 1 */ + +#define LSM9DS1_CTRL_REG1_G_BW_G_SHIFT 0 /* Gyroscope bandwidth selection */ +#define LSM9DS1_CTRL_REG1_G_BW_G_MASK (3 << LSM9DS1_CTRL_REG1_G_BW_G_SHIFT) +#define LSM9DS1_CTRL_REG1_G_FS_G_SHIFT 3 /* Gyroscope full-scale selection */ +#define LSM9DS1_CTRL_REG1_G_FS_G_MASK (3 << LSM9DS1_CTRL_REG1_G_FS_G_SHIFT) +# define LSM9DS1_CTRL_REG1_G_FS_G_245DPS (0 << LSM9DS1_CTRL_REG1_G_FS_G_SHIFT) /* 245 dps */ +# define LSM9DS1_CTRL_REG1_G_FS_G_500DPS (1 << LSM9DS1_CTRL_REG1_G_FS_G_SHIFT) /* 500 dps */ +# define LSM9DS1_CTRL_REG1_G_FS_G_2000DPS (3 << LSM9DS1_CTRL_REG1_G_FS_G_SHIFT) /* 2000 dps */ + +#define LSM9DS1_CTRL_REG1_G_ODR_G_SHIFT 5 /* Gyroscope bandwidth selection */ +#define LSM9DS1_CTRL_REG1_G_ODR_G_MASK (7 << LSM9DS1_CTRL_REG1_G_ODR_G_SHIFT) +# define LSM9DS1_CTRL_REG1_G_ODR_G_POWERDOWN (0 << LSM9DS1_CTRL_REG1_G_ODR_G_SHIFT) /* Power-down mode */ +# define LSM9DS1_CTRL_REG1_G_ODR_G_14p9HZ (1 << LSM9DS1_CTRL_REG1_G_ODR_G_SHIFT) /* 14.9 Hz */ +# define LSM9DS1_CTRL_REG1_G_ODR_G_59p5HZ (2 << LSM9DS1_CTRL_REG1_G_ODR_G_SHIFT) /* 59.5 Hz */ +# define LSM9DS1_CTRL_REG1_G_ODR_G_119HZ (3 << LSM9DS1_CTRL_REG1_G_ODR_G_SHIFT) /* 119 Hz */ +# define LSM9DS1_CTRL_REG1_G_ODR_G_238HZ (4 << LSM9DS1_CTRL_REG1_G_ODR_G_SHIFT) /* 238 Hz */ +# define LSM9DS1_CTRL_REG1_G_ODR_G_476HZ (5 << LSM9DS1_CTRL_REG1_G_ODR_G_SHIFT) /* 476 Hz */ +# define LSM9DS1_CTRL_REG1_G_ODR_G_952HZ (6 << LSM9DS1_CTRL_REG1_G_ODR_G_SHIFT) /* 952 Hz */ + +/* Gyroscope control register 2 */ + +#define LSM9DS1_CTRL_REG2_G_OUT_SEL_SHIFT 0 /* Out selection configuration */ +#define LSM9DS1_CTRL_REG2_G_OUT_SEL_MASK (3 << LSM9DS1_CTRL_REG2_G_OUT_SEL_SHIFT) +#define LSM9DS1_CTRL_REG2_G_INT_SEL_SHIFT 2 /* INT selection configuration */ +#define LSM9DS1_CTRL_REG2_G_INT_SEL_MASK (3 << LSM9DS1_CTRL_REG2_G_INT_SEL_SHIFT) + +/* Gyroscope control register 3 */ + +#define LSM9DS1_CTRL_REG3_G_HPCF_G_SHIFT 0 /* Gyroscope high-pass filter cutoff frequency selection */ +#define LSM9DS1_CTRL_REG3_G_HPCF_G_MASK (15 << LSM9DS1_CTRL_REG3_G_HPCF_G_SHIFT) +#define LSM9DS1_CTRL_REG3_G_HP_EN (1 << 6) /* High-pass filter enable */ +#define LSM9DS1_CTRL_REG3_G_LP_MODE (1 << 7) /* Low-power mode enable */ + +/* Gyroscope sign and orientation register */ + +#define LSM9DS1_ORIENT_CFG_G_ORIENT_SHIFT 0 /* Directional user orientation selection */ +#define LSM9DS1_ORIENT_CFG_G_ORIENT_MASK (3 << LSM9DS1_ORIENT_CFG_G_ORIENT_SHIFT) +#define LSM9DS1_ORIENT_CFG_G_SIGNZ_G (1 << 3) /* Yaw axis (Z) angular rate sign */ +#define LSM9DS1_ORIENT_CFG_G_SIGNY_G (1 << 4) /* Roll axis (Y) angular rate sign */ +#define LSM9DS1_ORIENT_CFG_G_SIGNX_G (1 << 5) /* Pitch axis (X) angular rate sign */ + +/* Gyroscope interrupt source register */ + +#define LSM9DS1_INT_GEN_SRC_G_XL_G (1 << 0) /* Pitch (X) low */ +#define LSM9DS1_INT_GEN_SRC_G_XH_G (1 << 1) /* Pitch (X) high */ +#define LSM9DS1_INT_GEN_SRC_G_YL_G (1 << 2) /* Roll (Y) low */ +#define LSM9DS1_INT_GEN_SRC_G_YH_G (1 << 3) /* Roll (Y) high */ +#define LSM9DS1_INT_GEN_SRC_G_ZL_G (1 << 4) /* Yaw (Z) low */ +#define LSM9DS1_INT_GEN_SRC_G_ZH_G (1 << 5) /* Yaw (Z) high */ +#define LSM9DS1_INT_GEN_SRC_G_IA_G (1 << 6) /* Interrupt active */ + +/* Status register */ + +#define LSM9DS1_STATUS_REG_XLDA (1 << 0) /* Accelerometer new data available */ +#define LSM9DS1_STATUS_REG_GDA (1 << 1) /* Gyroscope new data available */ +#define LSM9DS1_STATUS_REG_TDA (1 << 2) /* Temperature sensor new data available */ +#define LSM9DS1_STATUS_REG_BOOT_STATUS (1 << 3) /* Boot running flag signal */ +#define LSM9DS1_STATUS_REG_INACT (1 << 4) /* Inactivity interrupt output signal */ +#define LSM9DS1_STATUS_REG_IG_G (1 << 5) /* Gyroscope interrupt output signal */ +#define LSM9DS1_STATUS_REG_IG_XL (1 << 6) /* Accelerometer interrupt output signal */ + +/* Control register 4 */ + +#define LSM9DS1_CTRL_REG4_4D_XL1 (1 << 0) /* 4D option enabled on interrupt */ +#define LSM9DS1_CTRL_REG4_LIR_XL1 (1 << 1) /* Latched interrupt */ +#define LSM9DS1_CTRL_REG4_XEN_G (1 << 3) /* Gyroscope's pitch axis (X) output enable */ +#define LSM9DS1_CTRL_REG4_YEN_G (1 << 4) /* Gyroscope's roll axis (Y) output enable */ +#define LSM9DS1_CTRL_REG4_ZEN_G (1 << 5) /* Gyroscope's yaw axis (Z) output enable */ + +/* Accelerometer control register 5 */ + +#define LSM9DS1_CTRL_REG5_XL_XEN_XL (1 << 3) /* Accelerometer's X-axis output enable */ +#define LSM9DS1_CTRL_REG5_XL_YEN_XL (1 << 4) /* Accelerometer's Y-axis output enable */ +#define LSM9DS1_CTRL_REG5_XL_ZEN_XL (1 << 5) /* Accelerometer's Z-axis output enable */ + +#define LSM9DS1_CTRL_REG5_XL_DEC_SHIFT 6 /* Decimation of acceleration data on OUT REG and FIFO */ +#define LSM9DS1_CTRL_REG5_XL_DEC_MASK (3 << LSM9DS1_CTRL_REG5_XL_DEC_SHIFT) +# define LSM9DS1_CTRL_REG5_XL_DEC_NODEC (0 << LSM9DS1_CTRL_REG5_XL_DEC_SHIFT) /* No decimation */ +# define LSM9DS1_CTRL_REG5_XL_DEC_2SAMPLES (1 << LSM9DS1_CTRL_REG5_XL_DEC_SHIFT) /* Update every 2 samples */ +# define LSM9DS1_CTRL_REG5_XL_DEC_4SAMPLES (2 << LSM9DS1_CTRL_REG5_XL_DEC_SHIFT) /* Update every 4 samples */ +# define LSM9DS1_CTRL_REG5_XL_DEC_8SAMPLES (3 << LSM9DS1_CTRL_REG5_XL_DEC_SHIFT) /* Update every 8 samples */ + +/* Accelerometer control register 6 */ + +#define LSM9DS1_CTRL_REG6_XL_BW_XL_SHIFT 0 /* Anti-aliasing filter bandwidth selection */ +#define LSM9DS1_CTRL_REG6_XL_BW_XL_MASK (3 << LSM9DS1_CTRL_REG6_XL_BW_XL_SHIFT) +# define LSM9DS1_CTRL_REG6_XL_BW_XL_408HZ (0 << LSM9DS1_CTRL_REG6_XL_BW_XL_SHIFT) /* 408 Hz */ +# define LSM9DS1_CTRL_REG6_XL_BW_XL_211HZ (1 << LSM9DS1_CTRL_REG6_XL_BW_XL_SHIFT) /* 211 Hz */ +# define LSM9DS1_CTRL_REG6_XL_BW_XL_105HZ (2 << LSM9DS1_CTRL_REG6_XL_BW_XL_SHIFT) /* 105 Hz */ +# define LSM9DS1_CTRL_REG6_XL_BW_XL_50HZ (3 << LSM9DS1_CTRL_REG6_XL_BW_XL_SHIFT) /* 50 Hz */ + +#define LSM9DS1_CTRL_REG6_XL_BW_SCAL_ODR (1 << 2) /* Bandwidth selection */ + +#define LSM9DS1_CTRL_REG6_XL_FS_XL_SHIFT 3 /* Accelerometer full-scale selection */ +#define LSM9DS1_CTRL_REG6_XL_FS_XL_MASK (3 << LSM9DS1_CTRL_REG6_XL_FS_XL_SHIFT) +# define LSM9DS1_CTRL_REG6_XL_FS_XL_2G (0 << LSM9DS1_CTRL_REG6_XL_FS_XL_SHIFT) /* +/- 2 g */ +# define LSM9DS1_CTRL_REG6_XL_FS_XL_16G (1 << LSM9DS1_CTRL_REG6_XL_FS_XL_SHIFT) /* +/- 16 g */ +# define LSM9DS1_CTRL_REG6_XL_FS_XL_4G (2 << LSM9DS1_CTRL_REG6_XL_FS_XL_SHIFT) /* +/- 4 g */ +# define LSM9DS1_CTRL_REG6_XL_FS_XL_8G (3 << LSM9DS1_CTRL_REG6_XL_FS_XL_SHIFT) /* +/- 8 g */ + +#define LSM9DS1_CTRL_REG6_XL_ODR_XL_SHIFT 5 /* Output data rate and power mode selection */ +#define LSM9DS1_CTRL_REG6_XL_ODR_XL_MASK (7 << LSM9DS1_CTRL_REG6_XL_ODR_XL_SHIFT) +# define LSM9DS1_CTRL_REG6_XL_ODR_XL_POWERDOWN (0 << LSM9DS1_CTRL_REG6_XL_ODR_XL_SHIFT) /* Power-down mode */ +# define LSM9DS1_CTRL_REG6_XL_ODR_XL_10HZ (1 << LSM9DS1_CTRL_REG6_XL_ODR_XL_SHIFT) /* 10 Hz */ +# define LSM9DS1_CTRL_REG6_XL_ODR_XL_50HZ (2 << LSM9DS1_CTRL_REG6_XL_ODR_XL_SHIFT) /* 50 Hz */ +# define LSM9DS1_CTRL_REG6_XL_ODR_XL_119HZ (3 << LSM9DS1_CTRL_REG6_XL_ODR_XL_SHIFT) /* 119 Hz */ +# define LSM9DS1_CTRL_REG6_XL_ODR_XL_238HZ (4 << LSM9DS1_CTRL_REG6_XL_ODR_XL_SHIFT) /* 238 Hz */ +# define LSM9DS1_CTRL_REG6_XL_ODR_XL_476HZ (5 << LSM9DS1_CTRL_REG6_XL_ODR_XL_SHIFT) /* 476 Hz */ +# define LSM9DS1_CTRL_REG6_XL_ODR_XL_952HZ (6 << LSM9DS1_CTRL_REG6_XL_ODR_XL_SHIFT) /* 952 Hz */ + +/* Accelerometer control register 7 */ + +#define LSM9DS1_CTRL_REG7_XL_HPIS1 (1 << 0) /* High-pass filter enabled */ +#define LSM9DS1_CTRL_REG7_XL_FDS (1 << 2) /* Filtered data selection */ + +#define LSM9DS1_CTRL_REG7_XL_DCF_SHIFT 5 /* Accelerometer digital filter cutoff frequency selection */ +#define LSM9DS1_CTRL_REG7_XL_DCF_MASK (3 << LSM9DS1_CTRL_REG7_XL_DCF_SHIFT) +# define LSM9DS1_CTRL_REG7_XL_DCF_ODR_DIV50 (0 << LSM9DS1_CTRL_REG7_XL_DCF_SHIFT) +# define LSM9DS1_CTRL_REG7_XL_DCF_ODR_DIV100 (1 << LSM9DS1_CTRL_REG7_XL_DCF_SHIFT) +# define LSM9DS1_CTRL_REG7_XL_DCF_ODR_DIV9 (2 << LSM9DS1_CTRL_REG7_XL_DCF_SHIFT) +# define LSM9DS1_CTRL_REG7_XL_DCF_ODR_DIV400 (3 << LSM9DS1_CTRL_REG7_XL_DCF_SHIFT) +#define LSM9DS1_CTRL_REG7_XL_HR (1 << 7) /* High resolution mode enable */ + +/* Control register 8 */ + +#define LSM9DS1_CTRL_REG8_SW_RESET (1 << 0) /* Software reset */ +#define LSM9DS1_CTRL_REG8_BLE (1 << 1) /* Big/little endian data selection */ +#define LSM9DS1_CTRL_REG8_IF_ADD_INC (1 << 2) /* Register address automatically incremented during a multibyte access */ +#define LSM9DS1_CTRL_REG8_SIM (1 << 3) /* SPI serial interface mode selection */ +#define LSM9DS1_CTRL_REG8_PP_OD (1 << 4) /* Push-pull/open-drain selection on the INT1_A/G and INT2_A/G pins */ +#define LSM9DS1_CTRL_REG8_H_LACTIVE (1 << 5) /* Interrupt activation level */ +#define LSM9DS1_CTRL_REG8_BDU (1 << 6) /* Block data update */ +#define LSM9DS1_CTRL_REG8_BOOT (1 << 7) /* Reboot memory content */ + +/* Control register 9 */ + +#define LSM9DS1_CTRL_REG9_STOP_ON_FTH (1 << 0) /* Enable FIFO threshold level use */ +#define LSM9DS1_CTRL_REG9_FIFO_EN (1 << 1) /* FIFO memory enable */ +#define LSM9DS1_CTRL_REG9_I2C_DISABLE (1 << 2) /* Disable I2C interface */ +#define LSM9DS1_CTRL_REG9_DRDY_MASK_BIT (1 << 3) /* Data available enable bit */ +#define LSM9DS1_CTRL_REG9_FIFO_TEMP_EN (1 << 4) /* Temperature data storage in FIFO enable */ +#define LSM9DS1_CTRL_REG9_SLEEP_G (1 << 6) /* Gyroscope sleep mode enable */ + +/* Control register 10 */ + +#define LSM9DS1_CTRL_REG10_ST_XL (1 << 0) /* Linear acceleration sensor self-test enable */ +#define LSM9DS1_CTRL_REG10_ST_G (1 << 2) /* Angular rate sensor self-test enable */ + +/* Accelerometer interrupt source register */ + +#define LSM9DS1_INT_GEN_SRC_XL_XL_XL (1 << 0) /* Accelerometer's X low event */ +#define LSM9DS1_INT_GEN_SRC_XL_XH_XL (1 << 1) /* Accelerometer's X high event */ +#define LSM9DS1_INT_GEN_SRC_XL_YL_XL (1 << 2) /* Accelerometer's Y low event */ +#define LSM9DS1_INT_GEN_SRC_XL_YH_XL (1 << 3) /* Accelerometer's Y high event */ +#define LSM9DS1_INT_GEN_SRC_XL_ZL_XL (1 << 4) /* Accelerometer's Z low event */ +#define LSM9DS1_INT_GEN_SRC_XL_ZH_XL (1 << 5) /* Accelerometer's Z high event */ +#define LSM9DS1_INT_GEN_SRC_XL_IA_XL (1 << 6) /* Interrupt active */ + +/* Status register 2 */ + +#define LSM9DS1_STATUS_REG2_XLDA (1 << 0) /* Accelerometer new data available */ +#define LSM9DS1_STATUS_REG2_GDA (1 << 1) /* Gyroscope new data available */ +#define LSM9DS1_STATUS_REG2_TDA (1 << 2) /* Temperature sensor new data available */ +#define LSM9DS1_STATUS_REG2_BOOT_STATUS (1 << 3) /* Boot running flag signal */ +#define LSM9DS1_STATUS_REG2_INACT (1 << 4) /* Inactivity interrupt output signal */ +#define LSM9DS1_STATUS_REG2_IG_G (1 << 5) /* Gyroscope interrupt output signal */ +#define LSM9DS1_STATUS_REG2_IG_XL (1 << 6) /* Accelerometer interrupt output signal */ + +/* FIFO control register */ + +#define LSM9DS1_FIFO_CTRL_FTH_SHIFT 0 /* FIFO threshold level setting */ +#define LSM9DS1_FIFO_CTRL_FTH_MASK (31 << LSM9DS1_FIFO_CTRL_FTH_SHIFT) +#define LSM9DS1_FIFO_CTRL_FMODE_SHIFT 5 /* FIFO mode selection bits */ +#define LSM9DS1_FIFO_CTRL_FMODE_MASK (7 << LSM9DS1_FIFO_CTRL_FMODE_SHIFT) +# define LSM9DS1_FIFO_CTRL_FMODE_BYPASS (0 << LSM9DS1_FIFO_CTRL_FMODE_SHIFT) /* Bypass mode */ +# define LSM9DS1_FIFO_CTRL_FMODE_FIFO (1 << LSM9DS1_FIFO_CTRL_FMODE_SHIFT) /* FIFO mode */ +# define LSM9DS1_FIFO_CTRL_FMODE_CONT_FIFO (3 << LSM9DS1_FIFO_CTRL_FMODE_SHIFT) /* Continuous-to-FIFO mode */ +# define LSM9DS1_FIFO_CTRL_FMODE_BYPASS_CONT (4 << LSM9DS1_FIFO_CTRL_FMODE_SHIFT) /* Bypass-to-continuous mode */ +# define LSM9DS1_FIFO_CTRL_FMODE_CONT (5 << LSM9DS1_FIFO_CTRL_FMODE_SHIFT) /* Continuous mode */ + +/* FIFO status control register */ + +#define LSM9DS1_FIFO_SRC_FSS_SHIFT 0 /* Number of unread samples stored into FIFO */ +#define LSM9DS1_FIFO_SRC_FSS_MASK (63 << LSM9DS1_FIFO_SRC_FSS_SHIFT) +#define LSM9DS1_FIFO_SRC_OVRN (1 << 6) /* FIFO overrun status */ +#define LSM9DS1_FIFO_SRC_FTH (1 << 7) /* FIFO threshold status */ + +/* Gyroscope interrupt configuration register */ + +#define LSM9DS1_INT_GEN_CFG_G_XLIE_G (1 << 0) /* Pitch (X) axis low event interrupt enable */ +#define LSM9DS1_INT_GEN_CFG_G_XHIE_G (1 << 1) /* Pitch (X) axis high event interrupt enable */ +#define LSM9DS1_INT_GEN_CFG_G_YLIE_G (1 << 2) /* Roll (Y) axis low event interrupt enable */ +#define LSM9DS1_INT_GEN_CFG_G_YHIE_G (1 << 3) /* Roll (Y) axis high event interrupt enable */ +#define LSM9DS1_INT_GEN_CFG_G_ZLIE_G (1 << 4) /* Yaw (Z) axis low event interrupt enable */ +#define LSM9DS1_INT_GEN_CFG_G_ZHIE_G (1 << 5) /* Yaw (Z) axis high event interrupt enable */ +#define LSM9DS1_INT_GEN_CFG_G_LIR_G (1 << 6) /* Latch interrupt request */ +#define LSM9DS1_INT_GEN_CFG_G_AOI_G (1 << 7) /* AND/OR combination of interrupt events */ + +/* Gyroscope interrupt threshold registers */ + +#define LSM9DS1_INT_GEN_THS_XH_G_THS_XH_G_SHIFT 0 /* X interrupt threshold high byte */ +#define LSM9DS1_INT_GEN_THS_XH_G_THS_XH_G_MASK (127 << LSM9DS1_INT_GEN_THS_XH_G_THS_XH_G_SHIFT) +#define LSM9DS1_INT_GEN_THS_XH_G_DCRM_G (1 << 7) /* Decrement or reset counter mode selection */ + +/* Gyroscope interrupt duration register */ + +#define LSM9DS1_INT_GEN_DUR_G_DUR_G_SHIFT 0 /* Enter/exit interrupt duration */ +#define LSM9DS1_INT_GEN_DUR_G_DUR_G_MASK (127 << LSM9DS1_INT_GEN_DUR_G_DUR_G_SHIFT) +#define LSM9DS1_INT_GEN_DUR_G_WAIT_G (1 << 7) /* Exit from interrupt wait function enable */ + +/* Device identification register */ + +#define LSM9DS1_WHO_AM_I_M_VALUE 0x3d + +/* Magnetometer control register 1 */ + +#define LSM9DS1_CTRL_REG1_M_ST (1 << 0) /* Self-test enable */ +#define LSM9DS1_CTRL_REG1_M_FAST_ODR (1 << 1) /* Enable data rates higher than 80 Hz */ + +#define LSM9DS1_CTRL_REG1_M_DO_SHIFT 2 /* Output data rate selection */ +#define LSM9DS1_CTRL_REG1_M_DO_MASK (7 << LSM9DS1_CTRL_REG1_M_DO_SHIFT) +# define LSM9DS1_CTRL_REG1_M_DO_0p625HZ (0 << LSM9DS1_CTRL_REG1_M_DO_SHIFT) /* 0.625 Hz */ +# define LSM9DS1_CTRL_REG1_M_DO_1p25HZ (1 << LSM9DS1_CTRL_REG1_M_DO_SHIFT) /* 1.25 Hz */ +# define LSM9DS1_CTRL_REG1_M_DO_2p5HZ (2 << LSM9DS1_CTRL_REG1_M_DO_SHIFT) /* 2.5 Hz */ +# define LSM9DS1_CTRL_REG1_M_DO_5HZ (3 << LSM9DS1_CTRL_REG1_M_DO_SHIFT) /* 5 Hz */ +# define LSM9DS1_CTRL_REG1_M_DO_10HZ (4 << LSM9DS1_CTRL_REG1_M_DO_SHIFT) /* 10 Hz */ +# define LSM9DS1_CTRL_REG1_M_DO_20HZ (5 << LSM9DS1_CTRL_REG1_M_DO_SHIFT) /* 20 Hz */ +# define LSM9DS1_CTRL_REG1_M_DO_40HZ (6 << LSM9DS1_CTRL_REG1_M_DO_SHIFT) /* 40 Hz */ +# define LSM9DS1_CTRL_REG1_M_DO_80HZ (7 << LSM9DS1_CTRL_REG1_M_DO_SHIFT) /* 80 Hz */ + +#define LSM9DS1_CTRL_REG1_M_OM_SHIFT 5 /* X and Y axes operative mode selection */ +#define LSM9DS1_CTRL_REG1_M_OM_MASK (3 << LSM9DS1_CTRL_REG1_M_OM_SHIFT) +# define LSM9DS1_CTRL_REG1_M_OM_LOW (0 << LSM9DS1_CTRL_REG1_M_OM_SHIFT) /* Low-power mode */ +# define LSM9DS1_CTRL_REG1_M_OM_MEDIUM (1 << LSM9DS1_CTRL_REG1_M_OM_SHIFT) /* Medium-performance mode */ +# define LSM9DS1_CTRL_REG1_M_OM_HIGH (2 << LSM9DS1_CTRL_REG1_M_OM_SHIFT) /* High-performance mode */ +# define LSM9DS1_CTRL_REG1_M_OM_ULTRAHIGH (3 << LSM9DS1_CTRL_REG1_M_OM_SHIFT) /* Ultra-high performance mode */ + +#define LSM9DS1_CTRL_REG1_M_TEMP_COMP (1 << 7) /* Temperature compensation enable */ + +/* Magnetometer control register 2 */ + +#define LSM9DS1_CTRL_REG2_M_SOFT_RST (1 << 2) /* Configuration register and user register reset */ +#define LSM9DS1_CTRL_REG2_M_REBOOT (1 << 3) /* Reboot memory content */ + +#define LSM9DS1_CTRL_REG2_M_FS_SHIFT 5 /* Full-scale configuration */ +#define LSM9DS1_CTRL_REG2_M_FS_MASK (3 << LSM9DS1_CTRL_REG2_M_FS_SHIFT) +# define LSM9DS1_CTRL_REG2_M_FS_4GAUSS (0 << LSM9DS1_CTRL_REG2_M_FS_SHIFT) /* +/- 4 gauss */ +# define LSM9DS1_CTRL_REG2_M_FS_8GAUSS (1 << LSM9DS1_CTRL_REG2_M_FS_SHIFT) /* +/- 8 gauss */ +# define LSM9DS1_CTRL_REG2_M_FS_12GAUSS (2 << LSM9DS1_CTRL_REG2_M_FS_SHIFT) /* +/- 12 gauss */ +# define LSM9DS1_CTRL_REG2_M_FS_16GAUSS (3 << LSM9DS1_CTRL_REG2_M_FS_SHIFT) /* +/- 16 gauss */ + +/* Magnetometer control register 3 */ + +#define LSM9DS1_CTRL_REG3_M_MD_SHIFT 0 /* Operating mode selection */ +#define LSM9DS1_CTRL_REG3_M_MD_MASK (3 << LSM9DS1_CTRL_REG3_M_MD_SHIFT) +# define LSM9DS1_CTRL_REG3_M_MD_CONT (0 << LSM9DS1_CTRL_REG3_M_MD_SHIFT) /* Continuous-conversion mode */ +# define LSM9DS1_CTRL_REG3_M_MD_SINGLE (1 << LSM9DS1_CTRL_REG3_M_MD_SHIFT) /* Single-conversion mode */ +# define LSM9DS1_CTRL_REG3_M_MD_POWERDOWN (2 << LSM9DS1_CTRL_REG3_M_MD_SHIFT) /* Power-down mode */ +# define LSM9DS1_CTRL_REG3_M_MD_POWERDOWN2 (3 << LSM9DS1_CTRL_REG3_M_MD_SHIFT) /* Power-down mode */ + +#define LSM9DS1_CTRL_REG3_M_SIM (1 << 2) /* SPI serial interface mode selection */ +#define LSM9DS1_CTRL_REG3_M_LP (1 << 5) /* Low-power mode configuration */ +#define LSM9DS1_CTRL_REG3_M_I2C_DISABLE (1 << 7) /* Disable I2C interface */ + +/* Magnetometer control register 4 */ + +#define LSM9DS1_CTRL_REG4_M_BLE (1 << 1) /* Big/little endian data selection */ + +#define LSM9DS1_CTRL_REG4_M_OMZ_SHIFT 2 /* Z-axis operative mode selection */ +#define LSM9DS1_CTRL_REG4_M_OMZ_MASK (3 << LSM9DS1_CTRL_REG4_M_OMZ_SHIFT) +# define LSM9DS1_CTRL_REG4_M_OMZ_LOW (0 << LSM9DS1_CTRL_REG4_M_OMZ_SHIFT) /* Low-power mode */ +# define LSM9DS1_CTRL_REG4_M_OMZ_MEDIUM (1 << LSM9DS1_CTRL_REG4_M_OMZ_SHIFT) /* Medium-performance mode */ +# define LSM9DS1_CTRL_REG4_M_OMZ_HIGH (2 << LSM9DS1_CTRL_REG4_M_OMZ_SHIFT) /* High-performance mode */ +# define LSM9DS1_CTRL_REG4_M_OMZ_ULTRAHIGH (3 << LSM9DS1_CTRL_REG4_M_OMZ_SHIFT) /* Ultra-high performance mode */ + +/* Magnetometer control register 5 */ + +#define LSM9DS1_CTRL_REG5_M_BDU (1 << 6) /* Block data update */ +#define LSM9DS1_CTRL_REG5_M_FAST_READ (1 << 7) /* Fast read enable */ + +/* Magnetometer status register */ + +#define LSM9DS1_STATUS_REG_M_XDA (1 << 0) /* X-axis new data available */ +#define LSM9DS1_STATUS_REG_M_YDA (1 << 1) /* Y-axis new data available */ +#define LSM9DS1_STATUS_REG_M_ZDA (1 << 2) /* Z-axis new data available */ +#define LSM9DS1_STATUS_REG_M_ZYXDA (1 << 3) /* X, Y and Z-axis new data available */ +#define LSM9DS1_STATUS_REG_M_XOR (1 << 4) /* X-axis data overrun */ +#define LSM9DS1_STATUS_REG_M_YOR (1 << 5) /* Y-axis data overrun */ +#define LSM9DS1_STATUS_REG_M_ZOR (1 << 6) /* Z-axis data overrun */ +#define LSM9DS1_STATUS_REG_M_ZYXOR (1 << 7) /* X, Y and Z-axis data overrun */ + +/* Magnetometer interrupt configuration register */ + +#define LSM9DS1_INT_CFG_M_IEN (1 << 0) /* Interrupt enable on the INT_M pin */ +#define LSM9DS1_INT_CFG_M_IEL (1 << 1) /* Latch interrupt request */ +#define LSM9DS1_INT_CFG_M_IEA (1 << 2) /* Interrupt active configuration on INT_MAG */ +#define LSM9DS1_INT_CFG_M_ZIEN (1 << 5) /* Z-axis interrupt enable */ +#define LSM9DS1_INT_CFG_M_YIEN (1 << 6) /* Y-axis interrupt enable */ +#define LSM9DS1_INT_CFG_M_XIEN (1 << 7) /* X-axis interrupt enable */ + +/* Magnetometer interrupt source register */ + +#define LSM9DS1_INT_SRC_M_INT (1 << 0) /* Interrupt occurred */ +#define LSM9DS1_INT_SRC_M_MROI (1 << 1) /* Internal measurement range overflow */ +#define LSM9DS1_INT_SRC_M_NTH_Z (1 << 2) /* Value on Z-axis exceeds threshold on negative side */ +#define LSM9DS1_INT_SRC_M_NTH_Y (1 << 3) /* Value on Y-axis exceeds threshold on negative side */ +#define LSM9DS1_INT_SRC_M_NTH_X (1 << 4) /* Value on X-axis exceeds threshold on negative side */ +#define LSM9DS1_INT_SRC_M_PTH_Z (1 << 5) /* Value on Z-axis exceeds threshold on positive side */ +#define LSM9DS1_INT_SRC_M_PTH_Y (1 << 6) /* Value on Y-axis exceeds threshold on positive side */ +#define LSM9DS1_INT_SRC_M_PTH_X (1 << 7) /* Value on X-axis exceeds threshold on positive side */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct lsm9ds1_dev_s; +struct lsm9ds1_ops_s +{ + CODE int (*config)(FAR struct lsm9ds1_dev_s *priv); + CODE int (*start)(FAR struct lsm9ds1_dev_s *priv); + CODE int (*stop)(FAR struct lsm9ds1_dev_s *priv); + CODE int (*setsamplerate)(FAR struct lsm9ds1_dev_s *priv, + uint32_t samplerate); + CODE int (*setfullscale)(FAR struct lsm9ds1_dev_s *priv, + uint32_t fullscale); +}; + +struct lsm9ds1_dev_s +{ + FAR struct i2c_master_s *i2c; /* I2C interface */ + FAR const struct lsm9ds1_ops_s *ops; /* Ops */ + uint8_t addr; /* I2C address */ + uint32_t samplerate; /* Output data rate */ + uint8_t datareg; /* Output data register of X low byte */ +}; + +/**************************************************************************** + * Public data + ****************************************************************************/ + +extern const struct lsm9ds1_ops_s g_lsm9ds1accel_ops; +extern const struct lsm9ds1_ops_s g_lsm9ds1gyro_ops; +extern const struct lsm9ds1_ops_s g_lsm9ds1mag_ops; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +int lsm9ds1_readreg8(FAR struct lsm9ds1_dev_s *priv, + uint8_t regaddr, FAR uint8_t *regval); +int lsm9ds1_readreg(FAR struct lsm9ds1_dev_s *priv, + uint8_t regaddr, FAR uint8_t *regval, uint8_t len); +int lsm9ds1_writereg8(FAR struct lsm9ds1_dev_s *priv, + uint8_t regaddr, uint8_t regval); +int lsm9ds1_modifyreg8(FAR struct lsm9ds1_dev_s *priv, + uint8_t regaddr, uint8_t clearbits, + uint8_t setbits); +uint32_t lsm9ds1_midpoint(uint32_t a, uint32_t b); + +#endif /* __INCLUDE_NUTTX_SENSORS_LSM9DS1_COMMOM_H */ diff --git a/drivers/sensors/lsm9ds1_uorb.c b/drivers/sensors/lsm9ds1_uorb.c new file mode 100644 index 0000000000000..6875d5b5830c4 --- /dev/null +++ b/drivers/sensors/lsm9ds1_uorb.c @@ -0,0 +1,803 @@ +/**************************************************************************** + * drivers/sensors/lsm9ds1_uorb.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "lsm9ds1_base.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CONSTANTS_ONE_G 9.8f + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +enum lsm9ds1_idx_e +{ + LSM9DS1_ACCEL_IDX = 0, + LSM9DS1_GYRO_IDX, + LSM9DS1_MAG_IDX, + LSM9DS1_MAX_IDX +}; + +struct lsm9ds1_sensor_s +{ + struct sensor_lowerhalf_s lower; + uint64_t last_update; + float scale; + FAR void *dev; +#ifdef CONFIG_SENSORS_LSM9DS1_POLL + bool enabled; + unsigned long interval; +#endif + struct lsm9ds1_dev_s base; +}; + +struct lsm9ds1_sensor_dev_s +{ + struct lsm9ds1_sensor_s priv[3]; + mutex_t lock; +#ifdef CONFIG_SENSORS_LSM9DS1_POLL + sem_t run; +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Sensor methods */ + +static int lsm9ds1_activate(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + bool enable); +static int lsm9ds1_set_interval(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR unsigned long *period_us); +#ifndef CONFIG_SENSORS_LSM9DS1_POLL +static int lsm9ds1_fetch(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR char *buffer, size_t buflen); +#endif +static int lsm9ds1_control(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + int cmd, unsigned long arg); + +/* Helpers */ + +static int lsm9ds1_mag_scale(FAR struct lsm9ds1_sensor_s *priv, + uint8_t scale); +static int lsm9ds1_accel_scale(FAR struct lsm9ds1_sensor_s *priv, + uint8_t scale); +static int lsm9ds1_gyro_scale(FAR struct lsm9ds1_sensor_s *priv, + uint8_t scale); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct sensor_ops_s g_sensor_ops = +{ + NULL, /* open */ + NULL, /* close */ + .activate = lsm9ds1_activate, + .set_interval = lsm9ds1_set_interval, + NULL, /* batch */ +#ifdef CONFIG_SENSORS_LSM9DS1_POLL + NULL, /* fetch */ +#else + .fetch = lsm9ds1_fetch, +#endif + NULL, /* selftest */ + NULL, /* set_calibvalue */ + NULL, /* calibrate */ + .control = lsm9ds1_control +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lsm9ds1_activate + ****************************************************************************/ + +static int lsm9ds1_activate(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, bool enable) +{ +#ifdef CONFIG_SENSORS_LSM9DS1_POLL + FAR struct lsm9ds1_sensor_s *priv = NULL; + FAR struct lsm9ds1_sensor_dev_s *dev = NULL; + bool start_thread = false; + int ret = OK; + + priv = container_of(lower, struct lsm9ds1_sensor_s, lower); + dev = priv->dev; + + if (enable) + { + if (!priv->enabled) + { + start_thread = true; + priv->last_update = sensor_get_timestamp(); + } + + ret = priv->base.ops->start(&priv->base); + } + else + { + ret = priv->base.ops->stop(&priv->base); + } + + priv->enabled = enable; + + if (start_thread) + { + /* Wake up the thread */ + + nxsem_post(&dev->run); + } + + return ret; +#else + return OK; +#endif +} + +/**************************************************************************** + * Name: lsm9ds1_set_interval + ****************************************************************************/ + +static int lsm9ds1_set_interval(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, + FAR unsigned long *interval) +{ +#ifdef CONFIG_SENSORS_LSM9DS1_POLL + FAR struct lsm9ds1_sensor_s *priv = NULL; + + priv = container_of(lower, struct lsm9ds1_sensor_s, lower); + + priv->interval = *interval; +#endif + + return OK; +} + +/**************************************************************************** + * Name: lsm9ds1_data + ****************************************************************************/ + +static int16_t lsm9ds1_data(int16_t data) +{ + /* The value is positive */ + + if (data < 0x8000) + { + data = data; + } + + /* The value is negative, so find its absolute value by taking the + * two's complement + */ + + else if (data > 0x8000) + { + data = -(~data + 1); + } + + /* The value is negative and can't be represented as a positive + * int16_t value + */ + + else + { + data = -32768; + } + + return data; +} + +#ifndef CONFIG_SENSORS_LSM9DS1_POLL +/**************************************************************************** + * Name: lsm9ds1_set_interval + ****************************************************************************/ + +static int lsm9ds1_fetch(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, FAR char *buffer, + size_t buflen) +{ + FAR struct lsm9ds1_sensor_s *priv = NULL; + int16_t data[3]; + int ret = OK; + + priv = container_of(lower, struct lsm9ds1_sensor_s, lower); + + switch (lower->type) + { + case SENSOR_TYPE_ACCELEROMETER: + { + struct sensor_accel accel; + + ret = lsm9ds1_readreg(&priv->base, LSM9DS1_OUT_X_L_XL, + (FAR uint8_t *)data, 6); + + accel.timestamp = sensor_get_timestamp(); + accel.x = (int16_t)lsm9ds1_data(data[0]) * priv->scale; + accel.y = (int16_t)lsm9ds1_data(data[1]) * priv->scale; + accel.z = (int16_t)lsm9ds1_data(data[2]) * priv->scale; + + memcpy(buffer, &accel, sizeof(accel)); + + break; + } + + case SENSOR_TYPE_GYROSCOPE: + { + struct sensor_gyro gyro; + + ret = lsm9ds1_readreg(&priv->base, LSM9DS1_OUT_X_L_G, + (FAR uint8_t *)data, 6); + + gyro.timestamp = sensor_get_timestamp(); + gyro.x = (int16_t)lsm9ds1_data(data[0]) * priv->scale; + gyro.y = (int16_t)lsm9ds1_data(data[1]) * priv->scale; + gyro.z = (int16_t)lsm9ds1_data(data[2]) * priv->scale; + + memcpy(buffer, &gyro, sizeof(gyro)); + + break; + } + + case SENSOR_TYPE_MAGNETIC_FIELD: + { + struct sensor_mag mag; + + ret = lsm9ds1_readreg(&priv->base, LSM9DS1_OUT_X_L_M, + (FAR uint8_t *)data, 6); + + mag.timestamp = sensor_get_timestamp(); + mag.x = (int16_t)lsm9ds1_data(data[0]) * priv->scale; + mag.y = (int16_t)lsm9ds1_data(data[1]) * priv->scale; + mag.z = (int16_t)lsm9ds1_data(data[2]) * priv->scale; + + memcpy(buffer, &mag, sizeof(mag)); + + break; + } + + default: + { + ret = -EINVAL; + break; + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: lsm9ds1_cotrol + ****************************************************************************/ + +static int lsm9ds1_control(FAR struct sensor_lowerhalf_s *lower, + FAR struct file *filep, int cmd, + unsigned long arg) +{ + FAR struct lsm9ds1_sensor_s *priv = NULL; + int ret = OK; + + priv = container_of(lower, struct lsm9ds1_sensor_s, lower); + + switch (cmd) + { + /* Set full scale command */ + + case SNIOC_SET_SCALE_XL: + { + if (priv->lower.type == SENSOR_TYPE_GYROSCOPE) + { + ret = lsm9ds1_gyro_scale(priv, arg); + } + else if (priv->lower.type == SENSOR_TYPE_ACCELEROMETER) + { + ret = lsm9ds1_accel_scale(priv, arg); + } + else if (priv->lower.type == SENSOR_TYPE_MAGNETIC_FIELD) + { + ret = lsm9ds1_mag_scale(priv, arg); + } + + break; + } + + default: + { + snerr("ERROR: Unrecognized cmd: %d\n", cmd); + ret = -ENOTTY; + break; + } + } + + return ret; +} + +/**************************************************************************** + * Name: lsm9ds1_mag_scale + ****************************************************************************/ + +static int lsm9ds1_mag_scale(FAR struct lsm9ds1_sensor_s *priv, + uint8_t scale) +{ + int ret = OK; + + ret = priv->base.ops->setfullscale(&priv->base, scale); + if (ret < 0) + { + return ret; + } + + if (scale < lsm9ds1_midpoint(4, 8)) + { + priv->scale = 8.f / 65536.f; + } + else if (scale < lsm9ds1_midpoint(8, 12)) + { + priv->scale = 16.f / 65536.f; + } + else if (scale < lsm9ds1_midpoint(12, 16)) + { + priv->scale = 24.f / 65536.f; + } + else + { + priv->scale = 32.f / 65536.f; + } + + return ret; +} + +/**************************************************************************** + * Name: lsm9ds1_accel_scale + ****************************************************************************/ + +static int lsm9ds1_accel_scale(FAR struct lsm9ds1_sensor_s *priv, + uint8_t scale) +{ + int ret = OK; + + ret = priv->base.ops->setfullscale(&priv->base, scale); + if (ret < 0) + { + return ret; + } + + if (scale < lsm9ds1_midpoint(2, 4)) + { + priv->scale = CONSTANTS_ONE_G / 16384.f; + } + else if (scale < lsm9ds1_midpoint(4, 8)) + { + priv->scale = CONSTANTS_ONE_G / 8192.f; + } + else if (scale < lsm9ds1_midpoint(8, 16)) + { + priv->scale = CONSTANTS_ONE_G / 4096.f; + } + else + { + priv->scale = CONSTANTS_ONE_G / 2048.f; + } + + return ret; +} + +/**************************************************************************** + * Name: lsm9ds1_gyro_scale + ****************************************************************************/ + +static int lsm9ds1_gyro_scale(FAR struct lsm9ds1_sensor_s *priv, + uint8_t scale) +{ + int ret = OK; + + ret = priv->base.ops->setfullscale(&priv->base, scale); + if (ret < 0) + { + return ret; + } + + if (scale < lsm9ds1_midpoint(245, 500)) + { + priv->scale = (M_PI / 180.0f) * 245.f / 32768.f; + } + else if (scale < lsm9ds1_midpoint(500, 2000)) + { + priv->scale = (M_PI / 180.0f) * 500.f / 32768.f; + } + else + { + priv->scale = (M_PI / 180.0f) * 2000.f / 32768.f; + } + + return ret; +} + +#ifdef CONFIG_SENSORS_LSM9DS1_POLL +/**************************************************************************** + * Name: lsm9ds1_accel_data + * + * Description: get and push accel data from struct sensor_data_s + * + * Parameter: + * priv - Internal private lower half driver instance + * buf - Point to data + * + * Return: + * OK - on success + * + ****************************************************************************/ + +static void lsm9ds1_accel_data(FAR struct lsm9ds1_sensor_s *priv, + FAR int16_t *buf) +{ + FAR struct sensor_lowerhalf_s *lower = &priv->lower; + struct sensor_accel accel; + uint64_t now = sensor_get_timestamp(); + + if (!priv->enabled || now - priv->last_update < priv->interval) + { + return; + } + + priv->last_update = now; + + accel.timestamp = now; + accel.x = (int16_t)lsm9ds1_data(buf[0]) * priv->scale; + accel.y = (int16_t)lsm9ds1_data(buf[1]) * priv->scale; + accel.z = (int16_t)lsm9ds1_data(buf[2]) * priv->scale; + accel.temperature = 0; + + lower->push_event(lower->priv, &accel, sizeof(accel)); +} + +/**************************************************************************** + * Name: lsm9ds1_gyro_data + * + * Description: get and push gyro data from struct sensor_data_s + * + * Parameter: + * priv - Internal private lower half driver instance + * buf - Point to data + * + * Return: + * OK - on success + * + ****************************************************************************/ + +static void lsm9ds1_gyro_data(FAR struct lsm9ds1_sensor_s *priv, + FAR int16_t *buf) +{ + FAR struct sensor_lowerhalf_s *lower = &priv->lower; + struct sensor_gyro gyro; + uint64_t now = sensor_get_timestamp(); + + if (!priv->enabled || now - priv->last_update < priv->interval) + { + return; + } + + priv->last_update = now; + + gyro.timestamp = now; + gyro.x = (int16_t)lsm9ds1_data(buf[0]) * priv->scale; + gyro.y = (int16_t)lsm9ds1_data(buf[1]) * priv->scale; + gyro.z = (int16_t)lsm9ds1_data(buf[2]) * priv->scale; + gyro.temperature = 0; + + lower->push_event(lower->priv, &gyro, sizeof(gyro)); +} + +/**************************************************************************** + * Name: lsm9ds1_mag_data + * + * Description: get and push magnetometer data from struct sensor_data_s + * + * Parameter: + * priv - Internal private lower half driver instance + * buf - Point to data + * + * Return: + * OK - on success + * + ****************************************************************************/ + +static void lsm9ds1_mag_data(FAR struct lsm9ds1_sensor_s *priv, + FAR int16_t *buf) +{ + FAR struct sensor_lowerhalf_s *lower = &priv->lower; + struct sensor_mag mag; + uint64_t now = sensor_get_timestamp(); + + if (!priv->enabled || now - priv->last_update < priv->interval) + { + return; + } + + priv->last_update = now; + + mag.timestamp = now; + mag.x = (int16_t)lsm9ds1_data(buf[0]) * priv->scale; + mag.y = (int16_t)lsm9ds1_data(buf[1]) * priv->scale; + mag.z = (int16_t)lsm9ds1_data(buf[2]) * priv->scale; + mag.temperature = 0; + + lower->push_event(lower->priv, &mag, sizeof(mag)); +} + +/**************************************************************************** + * Name: lsm9ds1_thread + * + * Description: Thread for performing interval measurement cycle and data + * read. + * + * Parameter: + * argc - Number opf arguments + * argv - Pointer to argument list + * + ****************************************************************************/ + +static int lsm9ds1_thread(int argc, FAR char **argv) +{ + FAR struct lsm9ds1_sensor_dev_s *dev + = (FAR struct lsm9ds1_sensor_dev_s *)((uintptr_t)strtoul(argv[1], NULL, + 16)); + FAR struct lsm9ds1_sensor_s *accel = &dev->priv[LSM9DS1_ACCEL_IDX]; + FAR struct lsm9ds1_sensor_s *gyro = &dev->priv[LSM9DS1_GYRO_IDX]; + FAR struct lsm9ds1_sensor_s *mag = &dev->priv[LSM9DS1_MAG_IDX]; + unsigned long min_interval; + int16_t adata[3]; + int16_t gdata[3]; + int16_t mdata[3]; + int ret; + + while (true) + { + if ((!accel->enabled) && (!gyro->enabled) && (!mag->enabled)) + { + /* Waiting to be woken up */ + + ret = nxsem_wait(&dev->run); + if (ret < 0) + { + continue; + } + } + + /* Read accel */ + + if (accel->enabled) + { + ret = lsm9ds1_readreg(&accel->base, + LSM9DS1_OUT_X_L_XL, (uint8_t *)adata, 6); + lsm9ds1_accel_data(accel, adata); + } + + /* Read gyro */ + + if (gyro->enabled) + { + ret = lsm9ds1_readreg(&gyro->base, + LSM9DS1_OUT_X_L_G, (uint8_t *)gdata, 6); + lsm9ds1_gyro_data(gyro, gdata); + } + + /* Read mag */ + + if (mag->enabled) + { + ret = lsm9ds1_readreg(&mag->base, + LSM9DS1_OUT_X_L_M, (uint8_t *)mdata, 6); + lsm9ds1_mag_data(mag, mdata); + } + + /* Sleeping thread before fetching the next sensor data */ + + min_interval = MIN(accel->interval, gyro->interval); + min_interval = MIN(min_interval, mag->interval); + nxsig_usleep(min_interval); + } + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lsm9ds1_register_uorb + * + * Description: + * Register the LSM9DS1 IMU as sensor device + * + * Input Parameters: + * devno - Instance number for driver + * config - configuratio + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int lsm9ds1_register_uorb(int devno, FAR struct lsm9ds1_config_s *config) +{ + FAR struct lsm9ds1_sensor_dev_s *dev = NULL; + FAR struct lsm9ds1_sensor_s *tmp = NULL; +#ifdef CONFIG_SENSORS_LSM9DS1_POLL + FAR char *argv[2]; + char arg1[32]; +#endif + int ret = OK; + + /* Initialize the device structure. */ + + dev = (FAR struct lsm9ds1_sensor_dev_s *)kmm_malloc(sizeof(*dev)); + if (dev == NULL) + { + snerr("ERROR: Failed to allocate instance\n"); + return -ENOMEM; + } + + memset(dev, 0, sizeof(*dev)); + nxmutex_init(&dev->lock); +#ifdef CONFIG_SENSORS_LSM9DS1_POLL + nxsem_init(&dev->run, 0, 0); +#endif + + /* Accelerometer register */ + + tmp = &dev->priv[LSM9DS1_ACCEL_IDX]; + tmp->dev = dev; + tmp->base.ops = &g_lsm9ds1accel_ops; + tmp->base.i2c = config->i2c; + tmp->base.addr = config->addr_acc; + tmp->lower.ops = &g_sensor_ops; + tmp->lower.type = SENSOR_TYPE_ACCELEROMETER; + tmp->lower.nbuffer = 1; +#ifdef CONFIG_SENSORS_LSM9DS1_POLL + tmp->enabled = false; + tmp->interval = CONFIG_SENSORS_LSM9DS1_POLL_INTERVAL; +#endif + + ret = sensor_register(&tmp->lower, devno); + if (ret < 0) + { + snerr("sensor_register failed: %d\n", ret); + goto gyro_err; + } + + lsm9ds1_accel_scale(tmp, 2); + + /* Gyroscope register */ + + tmp = &dev->priv[LSM9DS1_GYRO_IDX]; + tmp->dev = dev; + tmp->base.ops = &g_lsm9ds1gyro_ops; + tmp->base.i2c = config->i2c; + tmp->base.addr = config->addr_gyro; + tmp->lower.ops = &g_sensor_ops; + tmp->lower.type = SENSOR_TYPE_GYROSCOPE; + tmp->lower.nbuffer = 1; +#ifdef CONFIG_SENSORS_LSM9DS1_POLL + tmp->enabled = false; + tmp->interval = CONFIG_SENSORS_LSM9DS1_POLL_INTERVAL; +#endif + + ret = sensor_register(&tmp->lower, devno); + if (ret < 0) + { + snerr("sensor_register failed: %d\n", ret); + goto gyro_err; + } + + lsm9ds1_gyro_scale(tmp, 245); + + /* Magnetic register */ + + tmp = &dev->priv[LSM9DS1_MAG_IDX]; + tmp->dev = dev; + tmp->base.ops = &g_lsm9ds1mag_ops; + tmp->base.i2c = config->i2c; + tmp->base.addr = config->addr_mag; + tmp->lower.ops = &g_sensor_ops; + tmp->lower.type = SENSOR_TYPE_MAGNETIC_FIELD; + tmp->lower.nbuffer = 1; +#ifdef CONFIG_SENSORS_LSM9DS1_POLL + tmp->enabled = false; + tmp->interval = CONFIG_SENSORS_LSM9DS1_POLL_INTERVAL; +#endif + + ret = sensor_register(&tmp->lower, devno); + if (ret < 0) + { + snerr("sensor_register failed: %d\n", ret); + goto mag_err; + } + + lsm9ds1_mag_scale(tmp, 4); + +#ifdef CONFIG_SENSORS_LSM9DS1_POLL + /* Create thread for polling sensor data */ + + snprintf(arg1, 16, "%p", dev); + argv[0] = arg1; + argv[1] = NULL; + + ret = kthread_create("lsm9ds1_thread", SCHED_PRIORITY_DEFAULT, + CONFIG_SENSORS_LSM9DS1_THREAD_STACKSIZE, + lsm9ds1_thread, + argv); + if (ret < 0) + { + goto thr_err; + } +#endif + + return ret; + +#ifdef CONFIG_SENSORS_LSM9DS1_POLL +thr_err: +#endif + sensor_unregister(&dev->priv[LSM9DS1_MAG_IDX].lower, devno); +mag_err: + sensor_unregister(&dev->priv[LSM9DS1_GYRO_IDX].lower, devno); +gyro_err: + sensor_unregister(&dev->priv[LSM9DS1_ACCEL_IDX].lower, devno); + + kmm_free(dev); + + return ret; +} diff --git a/drivers/sensors/mpu9250_uorb.c b/drivers/sensors/mpu9250_uorb.c index 50db5e695ca76..acd32b47cee6b 100644 --- a/drivers/sensors/mpu9250_uorb.c +++ b/drivers/sensors/mpu9250_uorb.c @@ -1842,7 +1842,7 @@ static void mpu9250_mag_data(FAR struct mpu9250_sensor_s *priv, * read. * * Parameter: - * argc - Number opf arguments + * argc - Number of arguments * argv - Pointer to argument list ****************************************************************************/ diff --git a/drivers/sensors/ms56xx_uorb.c b/drivers/sensors/ms56xx_uorb.c index 0bb8d2507df35..5c29900c6764b 100644 --- a/drivers/sensors/ms56xx_uorb.c +++ b/drivers/sensors/ms56xx_uorb.c @@ -366,7 +366,7 @@ static inline void baro_measure_read(FAR struct ms56xx_dev_s *priv, * read. * * Parameter: - * argc - Number opf arguments + * argc - Number of arguments * argv - Pointer to argument list ****************************************************************************/ diff --git a/drivers/sensors/sensor_rpmsg.c b/drivers/sensors/sensor_rpmsg.c index 81e37d5b4cf84..eb8a997740975 100644 --- a/drivers/sensors/sensor_rpmsg.c +++ b/drivers/sensors/sensor_rpmsg.c @@ -27,6 +27,7 @@ #include #include +#include #include #include #include diff --git a/drivers/serial/CMakeLists.txt b/drivers/serial/CMakeLists.txt index d5ca56d70db81..aae88c806b489 100644 --- a/drivers/serial/CMakeLists.txt +++ b/drivers/serial/CMakeLists.txt @@ -26,8 +26,8 @@ if(CONFIG_SERIAL_GDBSTUB) list(APPEND SRCS serial_gdbstub.c) endif() -if(CONFIG_UART_PL011) - list(APPEND SRCS serial_pl011.c) +if(CONFIG_CMSDK_UART) + list(APPEND SRCS serial_cmsdk.c) endif() if(CONFIG_SERIAL_RXDMA) @@ -40,6 +40,10 @@ if(CONFIG_16550_UART) list(APPEND SRCS uart_16550.c) endif() +if(CONFIG_UART_PL011) + list(APPEND SRCS uart_pl011.c) +endif() + if(CONFIG_RPMSG_UART) list(APPEND SRCS uart_rpmsg.c) endif() diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 067795ea7e441..ee312a2b9a631 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -61,6 +61,15 @@ if UART_PL011 source "drivers/serial/Kconfig-pl011" endif +menuconfig CMSDK_UART + bool "CMSDK UART Chip support" + select ARCH_HAVE_SERIAL_TERMIOS + default n + +if CMSDK_UART +source "drivers/serial/Kconfig-cmsdk" +endif # CMSDK_UART + menuconfig 16550_UART bool "16550 UART Chip support" select ARCH_HAVE_SERIAL_TERMIOS @@ -86,7 +95,7 @@ config MCU_SERIAL config RPMSG_UART bool "UART RPMSG support" default n - depends on RPTUN + depends on RPMSG select ARCH_HAVE_SERIAL_TERMIOS select SERIAL_RXDMA select SERIAL_TXDMA diff --git a/drivers/serial/Kconfig-cmsdk b/drivers/serial/Kconfig-cmsdk new file mode 100644 index 0000000000000..bf793cb3d813f --- /dev/null +++ b/drivers/serial/Kconfig-cmsdk @@ -0,0 +1,150 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if CMSDK_UART + +config CMSDK_UART0 + bool "CMSDK UART0" + default n + +if CMSDK_UART0 + +config CMSDK_UART0_BASE + hex "CMSDK UART0 base address" + +config CMSDK_UART0_CLOCK + int "CMSDK UART0 clock" + +config CMSDK_UART0_TX_IRQ + int "CMSDK UART0 TX IRQ number" + +config CMSDK_UART0_RX_IRQ + int "CMSDK UART0 RX IRQ number" + +config CMSDK_UART0_OV_IRQ + int "CMSDK UART0 OVERRUN IRQ number" + +config CMSDK_UART0_BAUD + int "CMSDK UART0 BAUD" + default 115200 + +config CMSDK_UART0_RXBUFSIZE + int "CMSDK UART0 RX buffer size" + default 256 + ---help--- + CMSDK UART0 RX buffer size. Default: 256 + +config CMSDK_UART0_TXBUFSIZE + int "CMSDK UART0 TX buffer size" + default 256 + ---help--- + CMSDK UART0 TX buffer size. Default: 256 + +endif # CMSDK_UART0 + +config CMSDK_UART1 + bool "CMSDK UART1" + default n + +if CMSDK_UART1 + +config CMSDK_UART1_BASE + hex "CMSDK UART1 base address" + +config CMSDK_UART1_CLOCK + int "CMSDK UART1 clock" + +config CMSDK_UART1_TX_IRQ + int "CMSDK UART1 TX IRQ number" + +config CMSDK_UART1_RX_IRQ + int "CMSDK UART1 RX IRQ number" + +config CMSDK_UART1_OV_IRQ + int "CMSDK UART1 OVERRUN IRQ number" + +config CMSDK_UART1_BAUD + int "CMSDK UART1 BAUD" + default 115200 + +config CMSDK_UART1_RXBUFSIZE + int "CMSDK UART1 RX buffer size" + default 256 + ---help--- + CMSDK UART1 RX buffer size. Default: 256 + +config CMSDK_UART1_TXBUFSIZE + int "CMSDK UART1 TX buffer size" + default 256 + ---help--- + CMSDK UART1 TX buffer size. Default: 256 + +endif # CMSDK_UART1 + +config CMSDK_UART2 + bool "CMSDK UART2" + default n + +if CMSDK_UART2 + +config CMSDK_UART2_BASE + hex "CMSDK UART2 base address" + +config CMSDK_UART2_CLOCK + hex "CMSDK UART2 clock" + +config CMSDK_UART2_TX_IRQ + int "CMSDK UART2 TX IRQ number" + +config CMSDK_UART2_RX_IRQ + int "CMSDK UART2 RX IRQ number" + +config CMSDK_UART2_OV_IRQ + int "CMSDK UART2 OVERRUN IRQ number" + +config CMSDK_UART2_BAUD + int "CMSDK UART2 BAUD" + default 115200 + +config CMSDK_UART2_RXBUFSIZE + int "CMSDK UART2 RX buffer size" + default 256 + ---help--- + CMSDK UART2 RX buffer size. Default: 256 + +config CMSDK_UART2_TXBUFSIZE + int "CMSDK UART2 TX buffer size" + default 256 + ---help--- + CMSDK UART2 TX buffer size. Default: 256 + +endif # CMSDK_UART2 + +choice + prompt "CMSDK Serial Console" + default CMSDK_NO_SERIAL_CONSOLE + depends on DEV_CONSOLE + +config CMSDK_UART0_SERIAL_CONSOLE + bool "CMSDK UART0 serial console" + depends on CMSDK_UART0 + select SERIAL_CONSOLE + +config CMSDK_UART1_SERIAL_CONSOLE + bool "CMSDK UART1 serial console" + depends on CMSDK_UART1 + select SERIAL_CONSOLE + +config CMSDK_UART2_SERIAL_CONSOLE + bool "CMSDK UART2 serial console" + depends on CMSDK_UART2 + select SERIAL_CONSOLE + +config CMSDK_NO_SERIAL_CONSOLE + bool "No CMSDK serial console" + +endchoice # CMSDK Serial Console + +endif # CMSDK_UART diff --git a/drivers/serial/Kconfig-pl011 b/drivers/serial/Kconfig-pl011 index 9d562761bc971..b2df5f9d383b9 100644 --- a/drivers/serial/Kconfig-pl011 +++ b/drivers/serial/Kconfig-pl011 @@ -10,51 +10,75 @@ config UART0_PL011 select UART0_SERIALDRIVER default n +if UART0_PL011 + +config UART0_BASE + hex "UART0 base address" + +config UART0_IRQ + int "PL011 UART0 IRQ number" + +config UART0_CLK_FREQ + int "PL011 UART0 clock frequency" + default 24000000 + +endif # UART0_PL011 + config UART1_PL011 bool "UART1 PL011" select UART1_SERIALDRIVER default n +if UART1_PL011 + +config UART1_BASE + hex "UART1 base address" + +config UART1_IRQ + int "PL011 UART1 IRQ number" + +config UART1_CLK_FREQ + int "PL011 UART1 clock frequency" + default 24000000 + +endif # UART1_PL011 + config UART2_PL011 bool "UART2 PL011" select UART2_SERIALDRIVER default n +if UART2_PL011 + +config UART2_BASE + hex "UART2 base address" + +config UART2_IRQ + int "PL011 UART2 IRQ number" + +config UART2_CLK_FREQ + int "PL011 UART2 clock frequency" + default 24000000 + +endif # UART2_PL011 + config UART3_PL011 bool "UART3 PL011" select UART3_SERIALDRIVER default n -config UART0_BASE - hex "UART0 base address" - depends on UART0_PL011 - -config UART1_BASE - hex "UART1 base address" - depends on UART1_PL011 - -config UART2_BASE - hex "UART2 base address" - depends on UART2_PL011 +if UART3_PL011 config UART3_BASE hex "UART3 base address" - depends on UART3_PL011 - -config UART0_IRQ - int "PL011 UART0 IRQ number" - depends on UART0_PL011 - -config UART1_IRQ - int "PL011 UART1 IRQ number" - depends on UART1_PL011 - -config UART2_IRQ - int "PL011 UART2 IRQ number" - depends on UART2_PL011 config UART3_IRQ int "PL011 UART3 IRQ number" - depends on UART3_PL011 + +config UART3_CLK_FREQ + int "PL011 UART3 clock frequency" + default 24000000 + +endif # UART3_PL011 endif # UART_PL011 diff --git a/drivers/serial/Make.defs b/drivers/serial/Make.defs index 3975d45ccd167..28665d01f2fd5 100644 --- a/drivers/serial/Make.defs +++ b/drivers/serial/Make.defs @@ -26,8 +26,8 @@ ifeq ($(CONFIG_SERIAL_GDBSTUB),y) CSRCS += serial_gdbstub.c endif -ifeq ($(CONFIG_UART_PL011),y) - CSRCS += serial_pl011.c +ifeq ($(CONFIG_CMSDK_UART),y) + CSRCS += serial_cmsdk.c endif ifeq ($(CONFIG_SERIAL_RXDMA),y) @@ -40,6 +40,10 @@ ifeq ($(CONFIG_16550_UART),y) CSRCS += uart_16550.c endif +ifeq ($(CONFIG_UART_PL011),y) + CSRCS += uart_pl011.c +endif + ifeq ($(CONFIG_RPMSG_UART),y) CSRCS += uart_rpmsg.c endif diff --git a/drivers/serial/pty.c b/drivers/serial/pty.c index cb363283552fc..e9272cdb72e5f 100644 --- a/drivers/serial/pty.c +++ b/drivers/serial/pty.c @@ -285,32 +285,21 @@ static int pty_open(FAR struct file *filep) } } - /* If one side of the driver has been unlinked, then refuse further - * opens. - */ + /* First open? */ - if (devpair->pp_unlinked) - { - ret = -EIDRM; - } - else + if (devpair->pp_nopen == 0) { - /* First open? */ - - if (devpair->pp_nopen == 0) - { - /* Yes, create the internal pipe */ + /* Yes, create the internal pipe */ - ret = pty_pipe(devpair); - } + ret = pty_pipe(devpair); + } - /* Increment the count of open references on the driver */ + /* Increment the count of open references on the driver */ - if (ret >= 0) - { - devpair->pp_nopen++; - DEBUGASSERT(devpair->pp_nopen > 0); - } + if (ret >= 0) + { + devpair->pp_nopen++; + DEBUGASSERT(devpair->pp_nopen > 0); } nxmutex_unlock(&devpair->pp_lock); @@ -318,7 +307,7 @@ static int pty_open(FAR struct file *filep) } /**************************************************************************** - * Name: pty_open + * Name: pty_close ****************************************************************************/ static int pty_close(FAR struct file *filep) @@ -372,6 +361,7 @@ static int pty_close(FAR struct file *filep) { /* Yes.. Free the device pair now (without freeing the semaphore) */ + nxmutex_unlock(&devpair->pp_lock); pty_destroy(devpair); return OK; } @@ -961,6 +951,7 @@ static int pty_unlink(FAR struct inode *inode) if (devpair->pp_nopen == 0) { + nxmutex_unlock(&devpair->pp_lock); pty_destroy(devpair); return OK; } diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 43a4552796886..5d746b83f48f3 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -112,6 +112,9 @@ static int uart_ioctl(FAR struct file *filep, int cmd, unsigned long arg); static int uart_poll(FAR struct file *filep, FAR struct pollfd *fds, bool setup); +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS +static int uart_unlink(FAR struct inode *inode); +#endif /**************************************************************************** * Public Function Prototypes @@ -129,15 +132,18 @@ int CONFIG_TTY_LAUNCH_ENTRYPOINT(int argc, char *argv[]); static const struct file_operations g_serialops = { - uart_open, /* open */ - uart_close, /* close */ - uart_read, /* read */ - uart_write, /* write */ - NULL, /* seek */ - uart_ioctl, /* ioctl */ - NULL, /* mmap */ - NULL, /* truncate */ - uart_poll /* poll */ + uart_open, /* open */ + uart_close, /* close */ + uart_read, /* read */ + uart_write, /* write */ + NULL, /* seek */ + uart_ioctl, /* ioctl */ + NULL, /* mmap */ + NULL, /* truncate */ + uart_poll /* poll */ +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + , uart_unlink /* unlink */ +#endif }; #ifdef CONFIG_TTY_LAUNCH @@ -181,7 +187,7 @@ static int uart_putxmitchar(FAR uart_dev_t *dev, int ch, bool oktoblock) dev->xmit.buffer[dev->xmit.head] = ch; dev->xmit.head = nexthead; - return OK; + break; } /* The TX buffer is full. Should be block, waiting for the hardware @@ -725,6 +731,20 @@ static int uart_close(FAR struct file *filep) */ uart_reset_sem(dev); + + if (dev->unlinked) + { + nxmutex_unlock(&dev->closelock); + nxmutex_destroy(&dev->xmit.lock); + nxmutex_destroy(&dev->recv.lock); + nxmutex_destroy(&dev->closelock); + nxmutex_destroy(&dev->polllock); + nxsem_destroy(&dev->xmitsem); + nxsem_destroy(&dev->recvsem); + uart_release(dev); + return OK; + } + nxmutex_unlock(&dev->closelock); return OK; } @@ -874,10 +894,8 @@ static ssize_t uart_read(FAR struct file *filep, { /* Skipping character count down */ - if (dev->escape-- > 0) - { - continue; - } + dev->escape--; + continue; } /* Echo if the character is not a control byte */ @@ -1705,6 +1723,46 @@ static int uart_poll(FAR struct file *filep, return ret; } +/**************************************************************************** + * Name: uart_unlink + ****************************************************************************/ + +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS +static int uart_unlink(FAR struct inode *inode) +{ + FAR uart_dev_t *dev; + int ret; + + DEBUGASSERT(inode->i_private != NULL); + + dev = inode->i_private; + ret = nxmutex_lock(&dev->closelock); + if (ret < 0) + { + /* A signal received while waiting for the last close operation. */ + + return ret; + } + + if (dev->open_count <= 0) + { + nxmutex_unlock(&dev->closelock); + nxmutex_destroy(&dev->xmit.lock); + nxmutex_destroy(&dev->recv.lock); + nxmutex_destroy(&dev->closelock); + nxmutex_destroy(&dev->polllock); + nxsem_destroy(&dev->xmitsem); + nxsem_destroy(&dev->recvsem); + uart_release(dev); + return OK; + } + + dev->unlinked = true; + nxmutex_unlock(&dev->closelock); + return OK; +} +#endif + /**************************************************************************** * Name: uart_nxsched_foreach_cb ****************************************************************************/ diff --git a/drivers/serial/serial_cmsdk.c b/drivers/serial/serial_cmsdk.c new file mode 100644 index 0000000000000..16f84ca937193 --- /dev/null +++ b/drivers/serial/serial_cmsdk.c @@ -0,0 +1,796 @@ +/**************************************************************************** + * drivers/serial/serial_cmsdk.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct uart_cmsdk_s +{ + uint32_t uartbase; /* Base address of UART registers */ + uint32_t baud; /* Configured baud */ + uint32_t uartclk; /* UART clock frequency */ + uint8_t tx_irq; + uint8_t rx_irq; + uint8_t ov_irq; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int uart_cmsdk_setup(FAR struct uart_dev_s *dev); +static void uart_cmsdk_shutdown(FAR struct uart_dev_s *dev); +static int uart_cmsdk_attach(FAR struct uart_dev_s *dev); +static void uart_cmsdk_detach(FAR struct uart_dev_s *dev); +static int uart_cmsdk_rx_interrupt(int irq, FAR void *context, + FAR void *arg); +static int uart_cmsdk_ov_interrupt(int irq, FAR void *context, + FAR void *arg); +static int uart_cmsdk_tx_interrupt(int irq, FAR void *context, + FAR void *arg); +static int uart_cmsdk_ioctl(FAR struct file *filep, int cmd, + unsigned long arg); +static int uart_cmsdk_receive(FAR struct uart_dev_s *dev, + FAR unsigned int *status); +static void uart_cmsdk_rxint(FAR struct uart_dev_s *dev, bool enable); +static bool uart_cmsdk_rxavailable(FAR struct uart_dev_s *dev); +static void uart_cmsdk_send(FAR struct uart_dev_s *dev, int ch); +static void uart_cmsdk_txint(FAR struct uart_dev_s *dev, bool enable); +static bool uart_cmsdk_txready(FAR struct uart_dev_s *dev); +static bool uart_cmsdk_txempty(FAR struct uart_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = uart_cmsdk_setup, + .shutdown = uart_cmsdk_shutdown, + .attach = uart_cmsdk_attach, + .detach = uart_cmsdk_detach, + .ioctl = uart_cmsdk_ioctl, + .receive = uart_cmsdk_receive, + .rxint = uart_cmsdk_rxint, + .rxavailable = uart_cmsdk_rxavailable, + .send = uart_cmsdk_send, + .txint = uart_cmsdk_txint, + .txready = uart_cmsdk_txready, + .txempty = uart_cmsdk_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_CMSDK_UART0 +static char g_uart0rxbuffer[CONFIG_CMSDK_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_CMSDK_UART0_TXBUFSIZE]; +#endif +#ifdef CONFIG_CMSDK_UART1 +static char g_uart1rxbuffer[CONFIG_CMSDK_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_CMSDK_UART1_TXBUFSIZE]; +#endif +#ifdef CONFIG_CMSDK_UART2 +static char g_uart2rxbuffer[CONFIG_CMSDK_UART2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_CMSDK_UART2_TXBUFSIZE]; +#endif + +/* This describes the state of the CMSDK uart0 port. */ + +#ifdef CONFIG_CMSDK_UART0 +static struct uart_cmsdk_s g_uart0priv = +{ + .uartbase = CONFIG_CMSDK_UART0_BASE, + .baud = CONFIG_CMSDK_UART0_BAUD, + .uartclk = CONFIG_CMSDK_UART0_CLOCK, + .tx_irq = CONFIG_CMSDK_UART0_TX_IRQ, + .rx_irq = CONFIG_CMSDK_UART0_RX_IRQ, + .ov_irq = CONFIG_CMSDK_UART0_OV_IRQ, +}; + +static uart_dev_t g_uart0port = +{ + .recv = + { + .size = CONFIG_CMSDK_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + .xmit = + { + .size = CONFIG_CMSDK_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; +#endif + +/* This describes the state of the CMSDK uart1 port. */ + +#ifdef CONFIG_CMSDK_UART1 +static struct uart_cmsdk_s g_uart1priv = +{ + .uartbase = CONFIG_CMSDK_UART1_BASE, + .baud = CONFIG_CMSDK_UART1_BAUD, + .uartclk = CONFIG_CMSDK_UART1_CLOCK, + .tx_irq = CONFIG_CMSDK_UART1_TX_IRQ, + .rx_irq = CONFIG_CMSDK_UART1_RX_IRQ, + .ov_irq = CONFIG_CMSDK_UART1_OV_IRQ, +}; + +static uart_dev_t g_uart1port = +{ + .recv = + { + .size = CONFIG_CMSDK_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + .xmit = + { + .size = CONFIG_CMSDK_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; +#endif + +#ifdef CONFIG_CMSDK_UART2 +static struct uart_cmsdk_s g_uart2priv = +{ + .uartbase = CONFIG_CMSDK_UART2_BASE, + .baud = CONFIG_CMSDK_UART2_BAUD, + .uartclk = CONFIG_CMSDK_UART2_CLOCK, + .tx_irq = CONFIG_CMSDK_UART2_TX_IRQ, + .rx_irq = CONFIG_CMSDK_UART2_RX_IRQ, + .ov_irq = CONFIG_CMSDK_UART2_OV_IRQ, +}; + +static uart_dev_t g_uart2port = +{ + .recv = + { + .size = CONFIG_CMSDK_UART2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + .xmit = + { + .size = CONFIG_CMSDK_UART2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; +#endif + +/* Which UART with be console */ + +#if defined(CONFIG_CMSDK_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* UART0=console */ +#elif defined(CONFIG_CMSDK_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1=console */ +#elif defined(CONFIG_CMSDK_UART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart2port /* UART2=console */ +#endif + +#ifdef CONFIG_CMSDK_UART0 +# define TTYS0_DEV g_uart0port +#endif + +#ifdef CONFIG_CMSDK_UART1 +# define TTYS1_DEV g_uart1port +#endif + +#ifdef CONFIG_CMSDK_UART2 +# define TTYS2_DEV g_uart2port +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: uart_cmsdk_serialin + ****************************************************************************/ + +static inline uint32_t uart_cmsdk_serialin(FAR struct uart_cmsdk_s *priv, + uint32_t offset) +{ + return *((FAR volatile uint32_t *)priv->uartbase + offset); +} + +/**************************************************************************** + * Name: uart_cmsdk_serialout + ****************************************************************************/ + +static inline void uart_cmsdk_serialout(FAR struct uart_cmsdk_s *priv, + uint32_t offset, uint32_t value) +{ + *((FAR volatile uint32_t *)priv->uartbase + offset) = value; +} + +/**************************************************************************** + * Name: uart_cmsdk_serialmodify + ****************************************************************************/ + +static uint32_t uart_cmsdk_serialmodify(FAR struct uart_cmsdk_s *priv, + uint32_t offset, uint32_t clearbits, + uint32_t setbits) +{ + uint32_t oldval; + uint32_t newval; + + oldval = uart_cmsdk_serialin(priv, offset); + newval = (oldval & ~clearbits) | setbits; + uart_cmsdk_serialout(priv, offset, newval); + + return oldval; +} + +/**************************************************************************** + * Name: uart_cmsdk_disableuartint + ****************************************************************************/ + +static inline uint32_t +uart_cmsdk_disableuartint(FAR struct uart_cmsdk_s *priv) +{ + return uart_cmsdk_serialmodify(priv, UART_CTRL_OFFSET, UART_CTRL_ALLIE, 0); +} + +/**************************************************************************** + * Name: uart_cmsdk_restoreuartint + ****************************************************************************/ + +static inline void uart_cmsdk_restoreuartint(FAR struct uart_cmsdk_s *priv, + uint32_t ier) +{ + uart_cmsdk_serialmodify(priv, UART_CTRL_OFFSET, 0, ier & UART_CTRL_ALLIE); +} + +/**************************************************************************** + * Name: uart_cmsdk_divisor + * + * Description: + * Select a divider to produce the BAUD from the UART_CLK. + * + * DIV = UART_CLK / BAUD + * + * Between UART_BAUDDIV_MIN and UART_BAUDDIV_MAX. + * + ****************************************************************************/ + +static inline uint32_t uart_cmsdk_divisor(FAR struct uart_cmsdk_s *priv) +{ + return priv->uartclk / priv->baud; +} + +/**************************************************************************** + * Name: uart_cmsdk_setup + * + * Description: + * Configure the UART baud, bits, parity, fifos, etc. This + * method is called the first time that the serial port is + * opened. + * + ****************************************************************************/ + +static int uart_cmsdk_setup(FAR struct uart_dev_s *dev) +{ + FAR struct uart_cmsdk_s *priv = dev->priv; + uint32_t bauddiv; + + /* Set the BAUD divisor */ + + bauddiv = uart_cmsdk_divisor(priv); + uart_cmsdk_serialout(priv, UART_BAUDDIV_OFFSET, bauddiv); + + /* Enable TX and RX logic */ + + uart_cmsdk_serialmodify(priv, UART_CTRL_OFFSET, + 0, UART_CTRL_TX_ENABLE | UART_CTRL_RX_ENABLE); + + return OK; +} + +/**************************************************************************** + * Name: uart_cmsdk_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ****************************************************************************/ + +static void uart_cmsdk_shutdown(struct uart_dev_s *dev) +{ + FAR struct uart_cmsdk_s *priv = dev->priv; + + uart_cmsdk_disableuartint(priv); +} + +/**************************************************************************** + * Name: uart_cmsdk_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. + * This method is called when the serial port is opened. + * Normally, this is just after the setup() method is called, + * however, the serial console may operate in a non-interrupt driven + * mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the + * attach method (unless the hardware supports multiple levels of + * interrupt enabling). The RX and TX + * interrupts are not enabled until the txint() and rxint() + * methods are called. + * + ****************************************************************************/ + +static int uart_cmsdk_attach(struct uart_dev_s *dev) +{ + FAR struct uart_cmsdk_s *priv = dev->priv; + int ret = 0; + + /* Attach and enable the IRQ */ + + ret = irq_attach(priv->tx_irq, uart_cmsdk_tx_interrupt, dev); + ret |= irq_attach(priv->rx_irq, uart_cmsdk_rx_interrupt, dev); + ret |= irq_attach(priv->ov_irq, uart_cmsdk_ov_interrupt, dev); +#ifndef CONFIG_ARCH_NOINTC + if (ret == OK) + { + /* Enable the interrupt (RX and TX interrupts are still disabled + * in the UART + */ + + up_enable_irq(priv->tx_irq); + up_enable_irq(priv->rx_irq); + up_enable_irq(priv->ov_irq); + } +#endif + + return ret; +} + +/**************************************************************************** + * Name: uart_cmsdk_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. + * The exception is the serial console which is never shutdown. + * + ****************************************************************************/ + +static void uart_cmsdk_detach(FAR struct uart_dev_s *dev) +{ + FAR struct uart_cmsdk_s *priv = dev->priv; + + up_disable_irq(priv->tx_irq); + irq_detach(priv->tx_irq); + up_disable_irq(priv->rx_irq); + irq_detach(priv->rx_irq); + up_disable_irq(priv->ov_irq); + irq_detach(priv->ov_irq); +} + +/**************************************************************************** + * Name: uart_cmsdk_interrupt + * + * Description: + * This is the UART interrupt handler. It will be invoked when an + * interrupt received on the 'irq' It should call uart_transmitchars or + * uart_receivechar to perform the appropriate data transfers. The + * interrupt handling logic must be able to map the 'irq' number into the + * appropriate uart_cmsdk_s structure in order to call these functions. + * + ****************************************************************************/ + +static int uart_cmsdk_rx_interrupt(int irq, FAR void *context, FAR void *arg) +{ + FAR struct uart_dev_s *dev = arg; + FAR struct uart_cmsdk_s *priv; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = dev->priv; + + uart_cmsdk_serialout(priv, UART_INTSTS_OFFSET, UART_INTSTATUS_RX); + uart_recvchars(dev); + + return OK; +} + +static int uart_cmsdk_ov_interrupt(int irq, FAR void *context, FAR void *arg) +{ + FAR struct uart_dev_s *dev = arg; + FAR struct uart_cmsdk_s *priv; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = dev->priv; + if (uart_cmsdk_serialin(priv, UART_INTSTS_OFFSET) & + UART_INTSTATUS_RX_OVERRUN) + { + uart_cmsdk_serialout(priv, UART_INTSTS_OFFSET, + UART_INTSTATUS_RX_OVERRUN); + uart_cmsdk_serialout(priv, UART_STATE_OFFSET, + UART_STATE_RX_BUF_OVERRUN); + } + + if (uart_cmsdk_serialin(priv, UART_INTSTS_OFFSET) & + UART_INTSTATUS_TX_OVERRUN) + { + uart_cmsdk_serialout(priv, UART_INTSTS_OFFSET, + UART_INTSTATUS_TX_OVERRUN); + uart_cmsdk_serialout(priv, UART_STATE_OFFSET, + UART_STATE_TX_BUF_OVERRUN); + } + + return OK; +} + +static int uart_cmsdk_tx_interrupt(int irq, FAR void *context, FAR void *arg) +{ + FAR struct uart_dev_s *dev = arg; + FAR struct uart_cmsdk_s *priv; + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + priv = dev->priv; + + uart_cmsdk_serialout(priv, UART_INTSTS_OFFSET, UART_INTSTATUS_TX); + uart_xmitchars(dev); + + return OK; +} + +/**************************************************************************** + * Name: uart_cmsdk_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + ****************************************************************************/ + +static int uart_cmsdk_ioctl(struct file *filep, int cmd, unsigned long arg) +{ + FAR struct uart_dev_s *dev = filep->f_inode->i_private; + FAR struct uart_cmsdk_s *priv = dev->priv; + int ret; + + switch (cmd) + { + case TCGETS: + { + FAR struct termios *termiosp = (FAR struct termios *)arg; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + cfsetispeed(termiosp, priv->baud); + termiosp->c_cflag = CS8; + break; + } + break; + + case TCSETS: + { + FAR struct termios *termiosp = (FAR struct termios *)arg; + irqstate_t flags; + + if (!termiosp) + { + ret = -EINVAL; + break; + } + + flags = enter_critical_section(); + priv->baud = cfgetispeed(termiosp); + uart_cmsdk_setup(dev); + leave_critical_section(flags); + } + break; + + default: + ret = -ENOTTY; + break; + } + + return ret; +} + +/**************************************************************************** + * Name: uart_cmsdk_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int uart_cmsdk_receive(struct uart_dev_s *dev, + FAR unsigned int *status) +{ + FAR struct uart_cmsdk_s *priv = dev->priv; + + *status = uart_cmsdk_serialin(priv, UART_STATE_OFFSET); + return uart_cmsdk_serialin(priv, UART_RBR_OFFSET); +} + +/**************************************************************************** + * Name: uart_cmsdk_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void uart_cmsdk_rxint(struct uart_dev_s *dev, bool enable) +{ + FAR struct uart_cmsdk_s *priv = dev->priv; + + if (enable) + { + uart_cmsdk_serialmodify(priv, UART_CTRL_OFFSET, + 0, UART_CTRL_RX_INT_ENABLE | UART_CTRL_RX_OVERRUN_INT_ENABLE); + } + else + { + uart_cmsdk_serialmodify(priv, UART_CTRL_OFFSET, + UART_CTRL_RX_INT_ENABLE | UART_CTRL_RX_OVERRUN_INT_ENABLE, 0); + } +} + +/**************************************************************************** + * Name: uart_cmsdk_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ****************************************************************************/ + +static bool uart_cmsdk_rxavailable(struct uart_dev_s *dev) +{ + FAR struct uart_cmsdk_s *priv = dev->priv; + + return uart_cmsdk_serialin(priv, UART_STATE_OFFSET) & + UART_STATE_RX_BUF_FULL; +} + +/**************************************************************************** + * Name: uart_cmsdk_send + * + * Description: + * This method will send one byte on the UART + * + ****************************************************************************/ + +static void uart_cmsdk_send(struct uart_dev_s *dev, int ch) +{ + FAR struct uart_cmsdk_s *priv = dev->priv; + + uart_cmsdk_serialout(priv, UART_THR_OFFSET, ch); +} + +/**************************************************************************** + * Name: uart_cmsdk_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void uart_cmsdk_txint(struct uart_dev_s *dev, bool enable) +{ + FAR struct uart_cmsdk_s *priv = dev->priv; + irqstate_t flags; + + flags = enter_critical_section(); + if (enable) + { + uart_cmsdk_serialmodify(priv, UART_CTRL_OFFSET, + 0, UART_CTRL_TX_INT_ENABLE | UART_CTRL_TX_OVERRUN_INT_ENABLE); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); + } + else + { + uart_cmsdk_serialmodify(priv, UART_CTRL_OFFSET, + UART_CTRL_TX_INT_ENABLE | UART_CTRL_TX_OVERRUN_INT_ENABLE, 0); + } + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: uart_cmsdk_txready + * + * Description: + * Return true if the tranmsit fifo is not full + * + ****************************************************************************/ + +static bool uart_cmsdk_txready(struct uart_dev_s *dev) +{ + FAR struct uart_cmsdk_s *priv = dev->priv; + + return !(uart_cmsdk_serialin(priv, UART_STATE_OFFSET) & + UART_STATE_TX_BUF_FULL); +} + +/**************************************************************************** + * Name: uart_cmsdk_txempty + * + * Description: + * Return true if the transmit fifo is empty + * + ****************************************************************************/ + +static bool uart_cmsdk_txempty(struct uart_dev_s *dev) +{ + FAR struct uart_cmsdk_s *priv = dev->priv; + + return !(uart_cmsdk_serialin(priv, UART_STATE_OFFSET) & + UART_STATE_TX_BUF_FULL); +} + +#ifdef HAVE_CMSDK_CONSOLE +/**************************************************************************** + * Name: uart_cmsdk_putc + * + * Description: + * Write one character to the UART (polled) + * + ****************************************************************************/ + +static void uart_cmsdk_putc(FAR struct uart_cmsdk_s *priv, int ch) +{ + while (uart_cmsdk_serialin(priv, UART_STATE_OFFSET) & + UART_STATE_TX_BUF_FULL); + uart_cmsdk_serialout(priv, UART_THR_OFFSET, ch); +} +#endif + +/**************************************************************************** + * Public Funtions + ****************************************************************************/ + +/**************************************************************************** + * Name: cmsdk_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before uart_serialinit. + * + * NOTE: Configuration of the CONSOLE UART was performed by uart_lowsetup() + * very early in the boot sequence. + * + ****************************************************************************/ + +void cmsdk_earlyserialinit(void) +{ + /* Configure all UARTs (except the CONSOLE UART) and disable interrupts */ +#ifdef CONFIG_CMSDK_UART0 + uart_cmsdk_disableuartint(&g_uart0priv); +#endif +#ifdef CONFIG_CMSDK_UART1 + uart_cmsdk_disableuartint(&g_uart1priv); +#endif +#ifdef CONFIG_CMSDK_UART2 + uart_cmsdk_disableuartint(&g_uart2priv); +#endif + + /* Configuration whichever one is the console */ + +#ifdef CONSOLE_DEV + CONSOLE_DEV.isconsole = true; + uart_cmsdk_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: cmsdk_serialinit + * + * Description: + * Register serial console and serial ports. This assumes that + * up_earlyserialinit was called previously. + * + ****************************************************************************/ + +void cmsdk_serialinit(void) +{ +#ifdef CONSOLE_DEV + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif +#ifdef TTYS0_DEV + (void)uart_register("/dev/ttyS0", &TTYS0_DEV); +#endif +#ifdef TTYS1_DEV + (void)uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +#ifdef TTYS2_DEV + (void)uart_register("/dev/ttyS2", &TTYS2_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +#ifdef HAVE_CMSDK_CONSOLE +int up_putc(int ch) +{ + FAR struct uart_cmsdk_s *priv = CONSOLE_DEV.priv; + uint32_t ier; + + ier = uart_cmsdk_disableuartint(priv); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + uart_cmsdk_putc(priv, '\r'); + } + + uart_cmsdk_putc(priv, ch); + uart_cmsdk_restoreuartint(priv, ier); + return ch; +} +#endif diff --git a/drivers/serial/serial_pl011.c b/drivers/serial/serial_pl011.c deleted file mode 100644 index d77fbc8a32ae8..0000000000000 --- a/drivers/serial/serial_pl011.c +++ /dev/null @@ -1,849 +0,0 @@ -/*************************************************************************** - * drivers/serial/serial_pl011.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ***************************************************************************/ - -/*************************************************************************** - * Included Files - ***************************************************************************/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_SERIAL_TERMIOS -# include -#endif - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#ifdef CONFIG_UART_PL011 - -/*************************************************************************** - * Pre-processor Definitions - ***************************************************************************/ - -/* Which UART with be tty0/console and which tty1-4? The console will - * always be ttyS0. If there is no console then will use the lowest - * numbered UART. - */ - -/* First pick the console and ttys0. This could be any of UART1-5 */ - -#if defined(CONFIG_UART1_SERIAL_CONSOLE) -# define CONSOLE_DEV g_uart1port /* UART1 is console */ -# define TTYS0_DEV g_uart1port /* UART1 is ttyS0 */ -# define UART1_ASSIGNED 1 -#endif - -#define PL011_BIT_MASK(x, y) (((2 << (x)) - 1) << (y)) - -/* PL011 Uart Flags Register */ -#define PL011_FR_CTS BIT(0) /* clear to send - inverted */ -#define PL011_FR_DSR BIT(1) /* data set ready - inverted - */ -#define PL011_FR_DCD BIT(2) /* data carrier detect - - * inverted */ -#define PL011_FR_BUSY BIT(3) /* busy transmitting data */ -#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */ -#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */ -#define PL011_FR_RXFF BIT(6) /* receive FIFO full */ -#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */ -#define PL011_FR_RI BIT(8) /* ring indicator - inverted */ - -/* PL011 Integer baud rate register */ -#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */ - -/* PL011 Fractional baud rate register */ -#define PL011_FBRD_BAUD_DIVFRAC 0x3f -#define PL011_FBRD_WIDTH 6u - -/* PL011 Receive status register / error clear register */ -#define PL011_RSR_ECR_FE BIT(0) /* framing error */ -#define PL011_RSR_ECR_PE BIT(1) /* parity error */ -#define PL011_RSR_ECR_BE BIT(2) /* break error */ -#define PL011_RSR_ECR_OE BIT(3) /* overrun error */ - -#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \ - PL011_RSR_ECR_BE | PL011_RSR_ECR_OE) - -/* PL011 Line Control Register */ -#define PL011_LCRH_BRK BIT(0) /* send break */ -#define PL011_LCRH_PEN BIT(1) /* enable parity */ -#define PL011_LCRH_EPS BIT(2) /* select even parity */ -#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */ -#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */ -#define PL011_LCRH_WLEN_SHIFT 5 /* word length */ -#define PL011_LCRH_WLEN_WIDTH 2 -#define PL011_LCRH_SPS BIT(7) /* stick parity bit */ - -#define PL011_LCRH_WLEN_SIZE(x) ((x) - 5) - -#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \ - PL011_LCRH_SPS | \ - PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \ - PL011_LCRH_WLEN_SHIFT)) - -#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS) -#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN) -#define PL011_LCRH_PARITY_NONE (0) - -/* PL011 Control Register */ -#define PL011_CR_UARTEN BIT(0) /* enable uart operations */ -#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */ -#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */ -#define PL011_CR_LBE BIT(7) /* loop back enable */ -#define PL011_CR_TXE BIT(8) /* transmit enable */ -#define PL011_CR_RXE BIT(9) /* receive enable */ -#define PL011_CR_DTR BIT(10) /* data transmit ready */ -#define PL011_CR_RTS BIT(11) /* request to send */ -#define PL011_CR_Out1 BIT(12) -#define PL011_CR_Out2 BIT(13) -#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable - */ -#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable - */ - -/* PL011 Interrupt Fifo Level Select Register */ -#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */ -#define PL011_IFLS_TXIFLSEL_WIDTH 3 -#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */ -#define PL011_IFLS_RXIFLSEL_WIDTH 3 - -/* PL011 Interrupt Mask Set/Clear Register */ -#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */ -#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */ -#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */ -#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */ -#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */ -#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */ -#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt - * mask */ -#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt - * mask */ -#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask - */ -#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask - */ -#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt - * mask */ - -#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \ - PL011_IMSC_PEIM | PL011_IMSC_BEIM | \ - PL011_IMSC_OEIM) - -#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \ - PL011_IMSC_PEIM | PL011_IMSC_FEIM | \ - PL011_IMSC_RIMIM | \ - PL011_IMSC_CTSMIM | \ - PL011_IMSC_DCDMIM | \ - PL011_IMSC_DSRMIM | \ - PL011_IMSC_RXIM | PL011_IMSC_TXIM | \ - PL011_IMSC_RTIM) - -/*************************************************************************** - * Private Types - ***************************************************************************/ - -/* UART PL011 register map structure */ - -struct pl011_regs -{ - uint32_t dr; /* data register */ - union - { - uint32_t rsr; - uint32_t ecr; - }; - - uint32_t reserved_0[4]; - uint32_t fr; /* flags register */ - uint32_t reserved_1; - uint32_t ilpr; - uint32_t ibrd; - uint32_t fbrd; - uint32_t lcr_h; - uint32_t cr; - uint32_t ifls; - uint32_t imsc; - uint32_t ris; - uint32_t mis; - uint32_t icr; - uint32_t dmacr; -}; - -struct pl011_config -{ - volatile struct pl011_regs *uart; - uint32_t sys_clk_freq; -}; - -/* Device data structure */ - -struct pl011_data -{ - uint32_t baud_rate; - bool sbsa; -}; - -struct pl011_uart_port_s -{ - struct pl011_data data; - struct pl011_config config; - unsigned int irq_num; - bool is_console; -}; - -/*************************************************************************** - * Private Functions - ***************************************************************************/ - -static void pl011_enable(const struct pl011_uart_port_s *sport) -{ - const struct pl011_config *config = &sport->config; - - config->uart->cr |= PL011_CR_UARTEN; -} - -static void pl011_disable(const struct pl011_uart_port_s *sport) -{ - const struct pl011_config *config = &sport->config; - - config->uart->cr &= ~PL011_CR_UARTEN; -} - -static void pl011_enable_fifo(const struct pl011_uart_port_s *sport) -{ - const struct pl011_config *config = &sport->config; - - config->uart->lcr_h |= PL011_LCRH_FEN; -} - -static void pl011_disable_fifo(const struct pl011_uart_port_s *sport) -{ - const struct pl011_config *config = &sport->config; - - config->uart->lcr_h &= ~PL011_LCRH_FEN; -} - -static int pl011_set_baudrate(const struct pl011_uart_port_s *sport, - uint32_t clk, uint32_t baudrate) -{ - const struct pl011_config *config = &sport->config; - - /* Avoiding float calculations, bauddiv is left shifted by 6 */ - - uint64_t bauddiv = - (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U); - - /* Valid bauddiv value - * uart_clk (min) >= 16 x baud_rate (max) - * uart_clk (max) <= 16 x 65535 x baud_rate (min) - */ - - if ((bauddiv < (1U << PL011_FBRD_WIDTH)) || - (bauddiv > (65535U << PL011_FBRD_WIDTH))) - { - return -EINVAL; - } - - config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH; - config->uart->fbrd = bauddiv & ((1U << PL011_FBRD_WIDTH) - 1U); - - /* In order to internally update the contents of ibrd or fbrd, a - * lcr_h write must always be performed at the end - * ARM DDI 0183F, Pg 3-13 - */ - - config->uart->lcr_h = config->uart->lcr_h; - - return 0; -} - -static void pl011_irq_tx_enable(const struct pl011_uart_port_s *sport) -{ - const struct pl011_config *config = &sport->config; - - config->uart->imsc |= PL011_IMSC_TXIM; -} - -static void pl011_irq_tx_disable(const struct pl011_uart_port_s *sport) -{ - const struct pl011_config *config = &sport->config; - - config->uart->imsc &= ~PL011_IMSC_TXIM; -} - -static void pl011_irq_rx_enable(const struct pl011_uart_port_s *sport) -{ - const struct pl011_config *config = &sport->config; - - config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM; -} - -static void pl011_irq_rx_disable(const struct pl011_uart_port_s *sport) -{ - const struct pl011_config *config = &sport->config; - - config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM); -} - -static int pl011_irq_tx_complete(const struct pl011_uart_port_s *sport) -{ - const struct pl011_config *config = &sport->config; - - /* check for TX FIFO empty */ - - return config->uart->fr & PL011_FR_TXFE; -} - -static int pl011_irq_rx_ready(const struct pl011_uart_port_s *sport) -{ - const struct pl011_config *config = &sport->config; - const struct pl011_data *data = &sport->data; - - if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE)) - { - return false; - } - - return (config->uart->imsc & PL011_IMSC_RXIM) && - (!(config->uart->fr & PL011_FR_RXFE)); -} - -/*************************************************************************** - * Name: pl011_txready - * - * Description: - * Return true if the tranmsit fifo is not full - * - ***************************************************************************/ - -static bool pl011_txready(struct uart_dev_s *dev) -{ - struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; - const struct pl011_config *config = &sport->config; - struct pl011_data *data = &sport->data; - - if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE)) - { - return false; - } - - return (config->uart->imsc & PL011_IMSC_TXIM) && - pl011_irq_tx_complete(sport); -} - -/*************************************************************************** - * Name: pl011_txempty - * - * Description: - * Return true if the transmit fifo is empty - * - ***************************************************************************/ - -static bool pl011_txempty(struct uart_dev_s *dev) -{ - struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; - - return pl011_irq_tx_complete(sport); -} - -/*************************************************************************** - * Name: pl011_send - * - * Description: - * This method will send one byte on the UART - * - ***************************************************************************/ - -static void pl011_send(struct uart_dev_s *dev, int ch) -{ - struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; - const struct pl011_config *config = &sport->config; - - config->uart->dr = ch; -} - -/*************************************************************************** - * Name: pl011_rxavailable - * - * Description: - * Return true if the receive fifo is not empty - * - ***************************************************************************/ - -static bool pl011_rxavailable(struct uart_dev_s *dev) -{ - struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; - const struct pl011_config *config = &sport->config; - struct pl011_data *data = &sport->data; - - if (!data->sbsa && - (!(config->uart->cr & PL011_CR_UARTEN) || - !(config->uart->cr & PL011_CR_RXE))) - { - return false; - } - - return (config->uart->fr & PL011_FR_RXFE) == 0U; -} - -/*************************************************************************** - * Name: pl011_rxint - * - * Description: - * Call to enable or disable RX interrupts - * - ***************************************************************************/ - -static void pl011_rxint(struct uart_dev_s *dev, bool enable) -{ - struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; - - if (enable) - { - pl011_irq_rx_enable(sport); - } - else - { - pl011_irq_rx_disable(sport); - } -} - -/*************************************************************************** - * Name: pl011_txint - * - * Description: - * Call to enable or disable TX interrupts - * - ***************************************************************************/ - -static void pl011_txint(struct uart_dev_s *dev, bool enable) -{ - struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; - irqstate_t flags; - - flags = enter_critical_section(); - - if (enable) - { - pl011_irq_tx_enable(sport); - - /* Fake a TX interrupt here by just calling uart_xmitchars() with - * interrupts disabled (note this may recurse). - */ - - uart_xmitchars(dev); - } - else - { - pl011_irq_tx_disable(sport); - } - - leave_critical_section(flags); -} - -/*************************************************************************** - * Name: pl011_receive - * - * Description: - * Called (usually) from the interrupt level to receive one - * character from the UART. Error bits associated with the - * receipt are provided in the return 'status'. - * - ***************************************************************************/ - -static int pl011_receive(struct uart_dev_s *dev, unsigned int *status) -{ - struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; - const struct pl011_config *config = &sport->config; - unsigned int rx; - - rx = config->uart->dr; - - *status = 0; - - return rx; -} - -/*************************************************************************** - * Name: pl011_ioctl - * - * Description: - * All ioctl calls will be routed through this method - * for current qemu configure, - * - ***************************************************************************/ - -static int pl011_ioctl(struct file *filep, int cmd, unsigned long arg) -{ - int ret = OK; - UNUSED(filep); - UNUSED(arg); - - switch (cmd) - { - case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ - case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ - default: - { - ret = -ENOTTY; - break; - } - } - - return ret; -} - -/*************************************************************************** - * Name: pl011_irq_handler (and front-ends) - * - * Description: - * This is the common UART interrupt handler. It should cal - * uart_transmitchars or uart_receivechar to perform the appropriate data - * transfers. - * - ***************************************************************************/ - -static int pl011_irq_handler(int irq, void *context, void *arg) -{ - struct uart_dev_s *dev = (struct uart_dev_s *)arg; - struct pl011_uart_port_s *sport; - UNUSED(irq); - UNUSED(context); - - DEBUGASSERT(dev != NULL && dev->priv != NULL); - sport = (struct pl011_uart_port_s *)dev->priv; - - if (pl011_irq_rx_ready(sport)) - { - uart_recvchars(dev); - } - - if (pl011_txready(dev)) - { - uart_xmitchars(dev); - } - - return OK; -} - -/*************************************************************************** - * Name: pl011_detach - * - * Description: - * Detach UART interrupts. This method is called when the serial port is - * closed normally just before the shutdown method is called. The - * exception is the serial console which is never shutdown. - * - ***************************************************************************/ - -static void pl011_detach(struct uart_dev_s *dev) -{ - struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; - - up_disable_irq(sport->irq_num); - irq_detach(sport->irq_num); -} - -/*************************************************************************** - * Name: pl011_attach - * - * Description: - * Configure the UART to operation in interrupt driven mode. - * This method is called when the serial port is opened. - * Normally, this is just after the setup() method is called, - * however, the serial console may operate in - * a non-interrupt driven mode during the boot phase. - * - * RX and TX interrupts are not enabled when by the attach method - * (unless the hardware supports multiple levels of interrupt - * enabling). The RX and TX interrupts are not enabled until - * the txint() and rxint() methods are called. - * - ***************************************************************************/ - -static int pl011_attach(struct uart_dev_s *dev) -{ - struct pl011_uart_port_s *sport; - struct pl011_data *data; - int ret; - - sport = (struct pl011_uart_port_s *)dev->priv; - data = &sport->data; - - ret = irq_attach(sport->irq_num, pl011_irq_handler, dev); - - if (ret == OK) - { - up_enable_irq(sport->irq_num); - } - else - { - sinfo("error ret=%d\n", ret); - } - - if (!data->sbsa) - { - pl011_enable(sport); - } - - return ret; -} - -/*************************************************************************** - * Name: pl011_shutdown - * - * Description: - * Disable the UART. This method is called when the serial - * port is closed - * - ***************************************************************************/ - -static void pl011_shutdown(struct uart_dev_s *dev) -{ - UNUSED(dev); - sinfo("%s: call unexpected\n", __func__); -} - -static int pl011_setup(struct uart_dev_s *dev) -{ - struct pl011_uart_port_s *sport = (struct pl011_uart_port_s *)dev->priv; - const struct pl011_config *config = &sport->config; - struct pl011_data *data = &sport->data; - int ret; - uint32_t lcrh; - irqstate_t i_flags; - - i_flags = up_irq_save(); - - /* If working in SBSA mode, we assume that UART is already configured, - * or does not require configuration at all (if UART is emulated by - * virtualization software). - */ - - if (!data->sbsa) - { - /* disable the uart */ - - pl011_disable(sport); - pl011_disable_fifo(sport); - - /* Set baud rate */ - - ret = pl011_set_baudrate(sport, config->sys_clk_freq, - data->baud_rate); - if (ret != 0) - { - up_irq_restore(i_flags); - return ret; - } - - /* Setting the default character format */ - - lcrh = config->uart->lcr_h & ~(PL011_LCRH_FORMAT_MASK); - lcrh &= ~(BIT(0) | BIT(7)); - lcrh |= PL011_LCRH_WLEN_SIZE(8) << PL011_LCRH_WLEN_SHIFT; - config->uart->lcr_h = lcrh; - - /* Enabling the FIFOs */ - - pl011_enable_fifo(sport); - } - - /* initialize all IRQs as masked */ - - config->uart->imsc = 0U; - config->uart->icr = PL011_IMSC_MASK_ALL; - - if (!data->sbsa) - { - config->uart->dmacr = 0U; - config->uart->cr &= ~(BIT(14) | BIT(15) | BIT(1)); - config->uart->cr |= PL011_CR_RXE | PL011_CR_TXE; - } - - up_irq_restore(i_flags); - - return 0; -} - -/*************************************************************************** - * Private Data - ***************************************************************************/ - -/* Serial driver UART operations */ - -static const struct uart_ops_s g_uart_ops = -{ - .setup = pl011_setup, - .shutdown = pl011_shutdown, - .attach = pl011_attach, - .detach = pl011_detach, - .ioctl = pl011_ioctl, - .receive = pl011_receive, - .rxint = pl011_rxint, - .rxavailable = pl011_rxavailable, -#ifdef CONFIG_SERIAL_IFLOWCONTROL - .rxflowcontrol = NULL, -#endif - .send = pl011_send, - .txint = pl011_txint, - .txready = pl011_txready, - .txempty = pl011_txempty, -}; - -/* This describes the state of the uart1 port. */ - -static struct pl011_uart_port_s g_uart1priv = -{ - .data = - { - .baud_rate = CONFIG_UART1_BAUD, - .sbsa = false, - }, - - .config = - { - .uart = (volatile struct pl011_regs *)CONFIG_UART1_BASE, - .sys_clk_freq = 24000000, - }, - - .irq_num = CONFIG_UART1_IRQ, - .is_console = 1, -}; - -/* I/O buffers */ - -static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; -static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; - -static struct uart_dev_s g_uart1port = -{ - .recv = - { - .size = CONFIG_UART1_RXBUFSIZE, - .buffer = g_uart1rxbuffer, - }, - - .xmit = - { - .size = CONFIG_UART1_TXBUFSIZE, - .buffer = g_uart1txbuffer, - }, - - .ops = &g_uart_ops, - .priv = &g_uart1priv, -}; - -/*************************************************************************** - * Public Functions - ***************************************************************************/ - -/*************************************************************************** - * Name: pl011_earlyserialinit - * - * Description: - * see nuttx/serial/uart_pl011.h - * - ***************************************************************************/ - -void pl011_earlyserialinit(void) -{ - /* Enable the console UART. The other UARTs will be initialized if and - * when they are first opened. - */ -#ifdef CONSOLE_DEV - CONSOLE_DEV.isconsole = true; - pl011_setup(&CONSOLE_DEV); -#endif -} - -/*************************************************************************** - * Name: up_putc - * - * Description: - * Provide priority, low-level access to support OS debug - * writes - * - ***************************************************************************/ - -int up_putc(int ch) -{ -#ifdef CONSOLE_DEV - struct uart_dev_s *dev = &CONSOLE_DEV; - - /* Check for LF */ - - if (ch == '\n') - { - /* Add CR */ - - pl011_send(dev, '\r'); - } - - pl011_send(dev, ch); -#endif - - return ch; -} - -/*************************************************************************** - * Name: pl011_serialinit - * - * Description: - * see nuttx/serial/uart_pl011.h - * - ***************************************************************************/ - -void pl011_serialinit(void) -{ -#ifdef CONSOLE_DEV - int ret; - - ret = uart_register("/dev/console", &CONSOLE_DEV); - if (ret < 0) - { - sinfo("error at register dev/console, ret =%d\n", ret); - } - - ret = uart_register("/dev/ttyS0", &TTYS0_DEV); - - if (ret < 0) - { - sinfo("error at register dev/ttyS0, ret =%d\n", ret); - } -#endif -} - -#endif /* USE_SERIALDRIVER */ diff --git a/drivers/serial/uart_16550.c b/drivers/serial/uart_16550.c index 418a91bca4cc7..747383a6f51f0 100644 --- a/drivers/serial/uart_16550.c +++ b/drivers/serial/uart_16550.c @@ -683,17 +683,6 @@ static inline void u16550_disableuartint(FAR struct u16550_s *priv, u16550_serialout(priv, UART_IER_OFFSET, priv->ier); } -/**************************************************************************** - * Name: u16550_restoreuartint - ****************************************************************************/ - -static inline void u16550_restoreuartint(FAR struct u16550_s *priv, - uint32_t ier) -{ - priv->ier |= ier & UART_IER_ALLIE; - u16550_serialout(priv, UART_IER_OFFSET, priv->ier); -} - /**************************************************************************** * Name: u16550_enablebreaks ****************************************************************************/ @@ -1705,8 +1694,12 @@ static bool u16550_txempty(struct uart_dev_s *dev) #ifdef HAVE_16550_CONSOLE static void u16550_putc(FAR struct u16550_s *priv, int ch) { + irqstate_t flags; + + flags = spin_lock_irqsave(NULL); while ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_THRE) == 0); u16550_serialout(priv, UART_THR_OFFSET, (uart_datawidth_t)ch); + spin_unlock_irqrestore(NULL, flags); } #endif @@ -1779,13 +1772,6 @@ void u16550_serialinit(void) int up_putc(int ch) { FAR struct u16550_s *priv = (FAR struct u16550_s *)CONSOLE_DEV.priv; - irqstate_t flags; - - /* All interrupts must be disabled to prevent re-entrancy and to prevent - * interrupts from firing in the serial driver code. - */ - - flags = enter_critical_section(); /* Check for LF */ @@ -1797,7 +1783,6 @@ int up_putc(int ch) } u16550_putc(priv, ch); - leave_critical_section(flags); return ch; } diff --git a/drivers/serial/uart_pl011.c b/drivers/serial/uart_pl011.c new file mode 100644 index 0000000000000..16619009d59d7 --- /dev/null +++ b/drivers/serial/uart_pl011.c @@ -0,0 +1,1042 @@ +/*************************************************************************** + * drivers/serial/uart_pl011.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ***************************************************************************/ + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_SERIAL_TERMIOS +# include +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_UART_PL011 + +/*************************************************************************** + * Pre-processor Definitions + ***************************************************************************/ + +/* Which UART with be tty0/console and which tty1-4? The console will + * always be ttyS0. If there is no console then will use the lowest + * numbered UART. + */ + +/* First pick the console and ttys0. This could be any of UART1-5 */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_UART0_PL011) +# define HAVE_PL011_CONSOLE 1 +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_UART1_PL011) +# define HAVE_PL011_CONSOLE 1 +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_UART2_PL011) +# define HAVE_PL011_CONSOLE 1 +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_UART3_PL011) +# define HAVE_PL011_CONSOLE 1 +#else +# undef HAVE_PL011_CONSOLE 1 +#endif + +#define PL011_BIT_MASK(x, y) (((2 << (x)) - 1) << (y)) + +/* PL011 Uart Flags Register */ +#define PL011_FR_CTS BIT(0) /* clear to send - inverted */ +#define PL011_FR_DSR BIT(1) /* data set ready - inverted + */ +#define PL011_FR_DCD BIT(2) /* data carrier detect - + * inverted */ +#define PL011_FR_BUSY BIT(3) /* busy transmitting data */ +#define PL011_FR_RXFE BIT(4) /* receive FIFO empty */ +#define PL011_FR_TXFF BIT(5) /* transmit FIFO full */ +#define PL011_FR_RXFF BIT(6) /* receive FIFO full */ +#define PL011_FR_TXFE BIT(7) /* transmit FIFO empty */ +#define PL011_FR_RI BIT(8) /* ring indicator - inverted */ + +/* PL011 Integer baud rate register */ +#define PL011_IBRD_BAUD_DIVINT_MASK 0xff /* 16 bits of divider */ + +/* PL011 Fractional baud rate register */ +#define PL011_FBRD_BAUD_DIVFRAC 0x3f +#define PL011_FBRD_WIDTH 6u + +/* PL011 Receive status register / error clear register */ +#define PL011_RSR_ECR_FE BIT(0) /* framing error */ +#define PL011_RSR_ECR_PE BIT(1) /* parity error */ +#define PL011_RSR_ECR_BE BIT(2) /* break error */ +#define PL011_RSR_ECR_OE BIT(3) /* overrun error */ + +#define PL011_RSR_ERROR_MASK (PL011_RSR_ECR_FE | PL011_RSR_ECR_PE | \ + PL011_RSR_ECR_BE | PL011_RSR_ECR_OE) + +/* PL011 Line Control Register */ +#define PL011_LCRH_BRK BIT(0) /* send break */ +#define PL011_LCRH_PEN BIT(1) /* enable parity */ +#define PL011_LCRH_EPS BIT(2) /* select even parity */ +#define PL011_LCRH_STP2 BIT(3) /* select two stop bits */ +#define PL011_LCRH_FEN BIT(4) /* enable FIFOs */ +#define PL011_LCRH_WLEN_SHIFT 5 /* word length */ +#define PL011_LCRH_WLEN_WIDTH 2 +#define PL011_LCRH_SPS BIT(7) /* stick parity bit */ + +#define PL011_LCRH_WLEN_SIZE(x) ((x) - 5) + +#define PL011_LCRH_FORMAT_MASK (PL011_LCRH_PEN | PL011_LCRH_EPS | \ + PL011_LCRH_SPS | \ + PL011_BIT_MASK(PL011_LCRH_WLEN_WIDTH, \ + PL011_LCRH_WLEN_SHIFT)) + +#define PL011_LCRH_PARTIY_EVEN (PL011_LCRH_PEN | PL011_LCRH_EPS) +#define PL011_LCRH_PARITY_ODD (PL011_LCRH_PEN) +#define PL011_LCRH_PARITY_NONE (0) + +/* PL011 Control Register */ +#define PL011_CR_UARTEN BIT(0) /* enable uart operations */ +#define PL011_CR_SIREN BIT(1) /* enable IrDA SIR */ +#define PL011_CR_SIRLP BIT(2) /* IrDA SIR low power mode */ +#define PL011_CR_LBE BIT(7) /* loop back enable */ +#define PL011_CR_TXE BIT(8) /* transmit enable */ +#define PL011_CR_RXE BIT(9) /* receive enable */ +#define PL011_CR_DTR BIT(10) /* data transmit ready */ +#define PL011_CR_RTS BIT(11) /* request to send */ +#define PL011_CR_Out1 BIT(12) +#define PL011_CR_Out2 BIT(13) +#define PL011_CR_RTSEn BIT(14) /* RTS hw flow control enable + */ +#define PL011_CR_CTSEn BIT(15) /* CTS hw flow control enable + */ + +/* PL011 Interrupt Fifo Level Select Register */ +#define PL011_IFLS_TXIFLSEL_SHIFT 0 /* bits 2:0 */ +#define PL011_IFLS_TXIFLSEL_WIDTH 3 +#define PL011_IFLS_RXIFLSEL_SHIFT 3 /* bits 5:3 */ +#define PL011_IFLS_RXIFLSEL_WIDTH 3 + +/* PL011 Interrupt Mask Set/Clear Register */ +#define PL011_IMSC_RIMIM BIT(0) /* RTR modem interrupt mask */ +#define PL011_IMSC_CTSMIM BIT(1) /* CTS modem interrupt mask */ +#define PL011_IMSC_DCDMIM BIT(2) /* DCD modem interrupt mask */ +#define PL011_IMSC_DSRMIM BIT(3) /* DSR modem interrupt mask */ +#define PL011_IMSC_RXIM BIT(4) /* receive interrupt mask */ +#define PL011_IMSC_TXIM BIT(5) /* transmit interrupt mask */ +#define PL011_IMSC_RTIM BIT(6) /* receive timeout interrupt + * mask */ +#define PL011_IMSC_FEIM BIT(7) /* framing error interrupt + * mask */ +#define PL011_IMSC_PEIM BIT(8) /* parity error interrupt mask + */ +#define PL011_IMSC_BEIM BIT(9) /* break error interrupt mask + */ +#define PL011_IMSC_OEIM BIT(10) /* overrun error interrupt + * mask */ + +#define PL011_IMSC_ERROR_MASK (PL011_IMSC_FEIM | \ + PL011_IMSC_PEIM | PL011_IMSC_BEIM | \ + PL011_IMSC_OEIM) + +#define PL011_IMSC_MASK_ALL (PL011_IMSC_OEIM | PL011_IMSC_BEIM | \ + PL011_IMSC_PEIM | PL011_IMSC_FEIM | \ + PL011_IMSC_RIMIM | \ + PL011_IMSC_CTSMIM | \ + PL011_IMSC_DCDMIM | \ + PL011_IMSC_DSRMIM | \ + PL011_IMSC_RXIM | PL011_IMSC_TXIM | \ + PL011_IMSC_RTIM) + +/*************************************************************************** + * Private Types + ***************************************************************************/ + +/* UART PL011 register map structure */ + +struct pl011_regs +{ + uint32_t dr; /* data register */ + union + { + uint32_t rsr; + uint32_t ecr; + }; + + uint32_t reserved_0[4]; + uint32_t fr; /* flags register */ + uint32_t reserved_1; + uint32_t ilpr; + uint32_t ibrd; + uint32_t fbrd; + uint32_t lcr_h; + uint32_t cr; + uint32_t ifls; + uint32_t imsc; + uint32_t ris; + uint32_t mis; + uint32_t icr; + uint32_t dmacr; +}; + +struct pl011_config +{ + FAR volatile struct pl011_regs *uart; + uint32_t sys_clk_freq; +}; + +/* Device data structure */ + +struct pl011_data +{ + uint32_t baud_rate; + bool sbsa; +}; + +struct pl011_uart_port_s +{ + struct pl011_data data; + struct pl011_config config; + unsigned int irq_num; +}; + +static int pl011_setup(FAR struct uart_dev_s *dev); +static void pl011_shutdown(FAR struct uart_dev_s *dev); +static int pl011_attach(FAR struct uart_dev_s *dev); +static void pl011_detach(FAR struct uart_dev_s *dev); +static int pl011_ioctl(FAR struct file *filep, int cmd, unsigned long arg); +static int pl011_receive(FAR struct uart_dev_s *dev, + FAR unsigned int *status); +static void pl011_rxint(FAR struct uart_dev_s *dev, bool enable); +static bool pl011_rxavailable(FAR struct uart_dev_s *dev); +static void pl011_send(FAR struct uart_dev_s *dev, int ch); +static void pl011_txint(FAR struct uart_dev_s *dev, bool enable); +static bool pl011_txready(FAR struct uart_dev_s *dev); +static bool pl011_txempty(FAR struct uart_dev_s *dev); + +/*************************************************************************** + * Private Data + ***************************************************************************/ + +/* Serial driver UART operations */ + +static const struct uart_ops_s g_uart_ops = +{ + .setup = pl011_setup, + .shutdown = pl011_shutdown, + .attach = pl011_attach, + .detach = pl011_detach, + .ioctl = pl011_ioctl, + .receive = pl011_receive, + .rxint = pl011_rxint, + .rxavailable = pl011_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = pl011_send, + .txint = pl011_txint, + .txready = pl011_txready, + .txempty = pl011_txempty, +}; + +/* I/O buffers */ + +#ifdef CONFIG_UART0_PL011 +static char g_uart0rxbuffer[CONFIG_UART0_RXBUFSIZE]; +static char g_uart0txbuffer[CONFIG_UART0_TXBUFSIZE]; +#endif +#ifdef CONFIG_UART1_PL011 +static char g_uart1rxbuffer[CONFIG_UART1_RXBUFSIZE]; +static char g_uart1txbuffer[CONFIG_UART1_TXBUFSIZE]; +#endif +#ifdef CONFIG_UART2_PL011 +static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE]; +static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; +#endif +#ifdef CONFIG_UART3_PL011 +static char g_uart3rxbuffer[CONFIG_UART3_RXBUFSIZE]; +static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE]; +#endif + +/* This describes the state of the uart0 port. */ + +#ifdef CONFIG_UART0_PL011 + +static struct pl011_uart_port_s g_uart0priv = +{ + .data = + { + .baud_rate = CONFIG_UART0_BAUD, + .sbsa = false, + }, + + .config = + { + .uart = (FAR volatile struct pl011_regs *)CONFIG_UART0_BASE, + .sys_clk_freq = CONFIG_UART0_CLK_FREQ, + }, + + .irq_num = CONFIG_UART0_IRQ, +}; + +/* I/O buffers */ + +static struct uart_dev_s g_uart0port = +{ + .recv = + { + .size = CONFIG_UART0_RXBUFSIZE, + .buffer = g_uart0rxbuffer, + }, + + .xmit = + { + .size = CONFIG_UART0_TXBUFSIZE, + .buffer = g_uart0txbuffer, + }, + + .ops = &g_uart_ops, + .priv = &g_uart0priv, +}; + +#endif /* CONFIG_UART0_PL011 */ + +/* This describes the state of the uart1 port. */ + +#ifdef CONFIG_UART1_PL011 + +static struct pl011_uart_port_s g_uart1priv = +{ + .data = + { + .baud_rate = CONFIG_UART1_BAUD, + .sbsa = false, + }, + + .config = + { + .uart = (FAR volatile struct pl011_regs *)CONFIG_UART1_BASE, + .sys_clk_freq = CONFIG_UART1_CLK_FREQ, + }, + + .irq_num = CONFIG_UART1_IRQ, +}; + +/* I/O buffers */ + +static struct uart_dev_s g_uart1port = +{ + .recv = + { + .size = CONFIG_UART1_RXBUFSIZE, + .buffer = g_uart1rxbuffer, + }, + + .xmit = + { + .size = CONFIG_UART1_TXBUFSIZE, + .buffer = g_uart1txbuffer, + }, + + .ops = &g_uart_ops, + .priv = &g_uart1priv, +}; + +#endif /* CONFIG_UART1_PL011 */ + +/* This describes the state of the uart2 port. */ + +#ifdef CONFIG_UART2_PL011 + +static struct pl011_uart_port_s g_uart2priv = +{ + .data = + { + .baud_rate = CONFIG_UART2_BAUD, + .sbsa = false, + }, + + .config = + { + .uart = (FAR volatile struct pl011_regs *)CONFIG_UART2_BASE, + .sys_clk_freq = CONFIG_UART2_CLK_FREQ, + }, + + .irq_num = CONFIG_UART2_IRQ, +}; + +/* I/O buffers */ + +static struct uart_dev_s g_uart2port = +{ + .recv = + { + .size = CONFIG_UART2_RXBUFSIZE, + .buffer = g_uart2rxbuffer, + }, + + .xmit = + { + .size = CONFIG_UART2_TXBUFSIZE, + .buffer = g_uart2txbuffer, + }, + + .ops = &g_uart_ops, + .priv = &g_uart2priv, +}; + +#endif /* CONFIG_UART2_PL011 */ + +/* This describes the state of the uart3 port. */ + +#ifdef CONFIG_UART3_PL011 + +static struct pl011_uart_port_s g_uart3priv = +{ + .data = + { + .baud_rate = CONFIG_UART3_BAUD, + .sbsa = false, + }, + + .config = + { + .uart = (FAR volatile struct pl011_regs *)CONFIG_UART3_BASE, + .sys_clk_freq = CONFIG_UART3_CLK_FREQ, + }, + + .irq_num = CONFIG_UART3_IRQ, +}; + +/* I/O buffers */ + +static struct uart_dev_s g_uart3port = +{ + .recv = + { + .size = CONFIG_UART3_RXBUFSIZE, + .buffer = g_uart3rxbuffer, + }, + + .xmit = + { + .size = CONFIG_UART3_TXBUFSIZE, + .buffer = g_uart3txbuffer, + }, + + .ops = &g_uart_ops, + .priv = &g_uart3priv, +}; + +#endif /* CONFIG_UART3_PL011 */ + +#if defined(CONFIG_UART0_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart0port /* UART0 is console */ +#elif defined(CONFIG_UART1_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart1port /* UART1 is console */ +#elif defined(CONFIG_UART2_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart2port /* UART2 is console */ +#elif defined(CONFIG_UART3_SERIAL_CONSOLE) +# define CONSOLE_DEV g_uart3port /* UART3 is console */ +#endif + +#ifdef CONFIG_UART0_PL011 +# define TTYS0_DEV g_uart0port +#endif + +#ifdef CONFIG_UART1_PL011 +# define TTYS1_DEV g_uart1port +#endif + +#ifdef CONFIG_UART2_PL011 +# define TTYS2_DEV g_uart2port +#endif + +#ifdef CONFIG_UART3_PL011 +# define TTYS3_DEV g_uart3port +#endif + +/*************************************************************************** + * Private Functions + ***************************************************************************/ + +static void pl011_enable(FAR const struct pl011_uart_port_s *sport) +{ + FAR const struct pl011_config *config = &sport->config; + + config->uart->cr |= PL011_CR_UARTEN; +} + +static void pl011_disable(FAR const struct pl011_uart_port_s *sport) +{ + FAR const struct pl011_config *config = &sport->config; + + config->uart->cr &= ~PL011_CR_UARTEN; +} + +static void pl011_enable_fifo(FAR const struct pl011_uart_port_s *sport) +{ + FAR const struct pl011_config *config = &sport->config; + + config->uart->lcr_h |= PL011_LCRH_FEN; +} + +static void pl011_disable_fifo(FAR const struct pl011_uart_port_s *sport) +{ + FAR const struct pl011_config *config = &sport->config; + + config->uart->lcr_h &= ~PL011_LCRH_FEN; +} + +static int pl011_set_baudrate(FAR const struct pl011_uart_port_s *sport, + uint32_t clk, uint32_t baudrate) +{ + FAR const struct pl011_config *config = &sport->config; + + /* Avoiding float calculations, bauddiv is left shifted by 6 */ + + uint64_t bauddiv = + (((uint64_t)clk) << PL011_FBRD_WIDTH) / (baudrate * 16U); + + /* Valid bauddiv value + * uart_clk (min) >= 16 x baud_rate (max) + * uart_clk (max) <= 16 x 65535 x baud_rate (min) + */ + + if ((bauddiv < (1U << PL011_FBRD_WIDTH)) || + (bauddiv > (65535U << PL011_FBRD_WIDTH))) + { + return -EINVAL; + } + + config->uart->ibrd = bauddiv >> PL011_FBRD_WIDTH; + config->uart->fbrd = bauddiv & ((1U << PL011_FBRD_WIDTH) - 1U); + + /* In order to internally update the contents of ibrd or fbrd, a + * lcr_h write must always be performed at the end + * ARM DDI 0183F, Pg 3-13 + */ + + config->uart->lcr_h = config->uart->lcr_h; + + return 0; +} + +static void pl011_irq_tx_enable(FAR const struct pl011_uart_port_s *sport) +{ + FAR const struct pl011_config *config = &sport->config; + + config->uart->imsc |= PL011_IMSC_TXIM; +} + +static void pl011_irq_tx_disable(FAR const struct pl011_uart_port_s *sport) +{ + FAR const struct pl011_config *config = &sport->config; + + config->uart->imsc &= ~PL011_IMSC_TXIM; +} + +static void pl011_irq_rx_enable(FAR const struct pl011_uart_port_s *sport) +{ + FAR const struct pl011_config *config = &sport->config; + + config->uart->imsc |= PL011_IMSC_RXIM | PL011_IMSC_RTIM; +} + +static void pl011_irq_rx_disable(FAR const struct pl011_uart_port_s *sport) +{ + FAR const struct pl011_config *config = &sport->config; + + config->uart->imsc &= ~(PL011_IMSC_RXIM | PL011_IMSC_RTIM); +} + +static int pl011_irq_tx_complete(FAR const struct pl011_uart_port_s *sport) +{ + FAR const struct pl011_config *config = &sport->config; + + /* check for TX FIFO empty */ + + return config->uart->fr & PL011_FR_TXFE; +} + +static int pl011_irq_rx_ready(FAR const struct pl011_uart_port_s *sport) +{ + FAR const struct pl011_config *config = &sport->config; + FAR const struct pl011_data *data = &sport->data; + + if (!data->sbsa && !(config->uart->cr & PL011_CR_RXE)) + { + return false; + } + + return (config->uart->imsc & PL011_IMSC_RXIM) && + (!(config->uart->fr & PL011_FR_RXFE)); +} + +/*************************************************************************** + * Name: pl011_txready + * + * Description: + * Return true if the tranmsit fifo is not full + * + ***************************************************************************/ + +static bool pl011_txready(FAR struct uart_dev_s *dev) +{ + FAR struct pl011_uart_port_s *sport = dev->priv; + FAR const struct pl011_config *config = &sport->config; + FAR struct pl011_data *data = &sport->data; + + if (!data->sbsa && !(config->uart->cr & PL011_CR_TXE)) + { + return false; + } + + return (config->uart->imsc & PL011_IMSC_TXIM) && + pl011_irq_tx_complete(sport); +} + +/*************************************************************************** + * Name: pl011_txempty + * + * Description: + * Return true if the transmit fifo is empty + * + ***************************************************************************/ + +static bool pl011_txempty(FAR struct uart_dev_s *dev) +{ + FAR struct pl011_uart_port_s *sport = dev->priv; + + return pl011_irq_tx_complete(sport); +} + +/*************************************************************************** + * Name: pl011_send + * + * Description: + * This method will send one byte on the UART + * + ***************************************************************************/ + +static void pl011_send(FAR struct uart_dev_s *dev, int ch) +{ + FAR struct pl011_uart_port_s *sport = dev->priv; + FAR const struct pl011_config *config = &sport->config; + + config->uart->dr = ch; +} + +/*************************************************************************** + * Name: pl011_rxavailable + * + * Description: + * Return true if the receive fifo is not empty + * + ***************************************************************************/ + +static bool pl011_rxavailable(FAR struct uart_dev_s *dev) +{ + FAR struct pl011_uart_port_s *sport = dev->priv; + FAR const struct pl011_config *config = &sport->config; + FAR struct pl011_data *data = &sport->data; + + if (!data->sbsa && + (!(config->uart->cr & PL011_CR_UARTEN) || + !(config->uart->cr & PL011_CR_RXE))) + { + return false; + } + + return (config->uart->fr & PL011_FR_RXFE) == 0U; +} + +/*************************************************************************** + * Name: pl011_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ***************************************************************************/ + +static void pl011_rxint(FAR struct uart_dev_s *dev, bool enable) +{ + FAR struct pl011_uart_port_s *sport = dev->priv; + + if (enable) + { + pl011_irq_rx_enable(sport); + } + else + { + pl011_irq_rx_disable(sport); + } +} + +/*************************************************************************** + * Name: pl011_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ***************************************************************************/ + +static void pl011_txint(FAR struct uart_dev_s *dev, bool enable) +{ + FAR struct pl011_uart_port_s *sport = dev->priv; + irqstate_t flags; + + flags = enter_critical_section(); + + if (enable) + { + pl011_irq_tx_enable(sport); + + /* Fake a TX interrupt here by just calling uart_xmitchars() with + * interrupts disabled (note this may recurse). + */ + + uart_xmitchars(dev); + } + else + { + pl011_irq_tx_disable(sport); + } + + leave_critical_section(flags); +} + +/*************************************************************************** + * Name: pl011_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the UART. Error bits associated with the + * receipt are provided in the return 'status'. + * + ***************************************************************************/ + +static int pl011_receive(FAR struct uart_dev_s *dev, + FAR unsigned int *status) +{ + FAR struct pl011_uart_port_s *sport = dev->priv; + FAR const struct pl011_config *config = &sport->config; + unsigned int rx; + + rx = config->uart->dr; + + *status = 0; + + return rx; +} + +/*************************************************************************** + * Name: pl011_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * for current qemu configure, + * + ***************************************************************************/ + +static int pl011_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + int ret = OK; + UNUSED(filep); + UNUSED(arg); + + switch (cmd) + { + case TIOCSBRK: /* BSD compatibility: Turn break on, unconditionally */ + case TIOCCBRK: /* BSD compatibility: Turn break off, unconditionally */ + default: + { + ret = -ENOTTY; + break; + } + } + + return ret; +} + +/*************************************************************************** + * Name: pl011_irq_handler (and front-ends) + * + * Description: + * This is the common UART interrupt handler. It should cal + * uart_transmitchars or uart_receivechar to perform the appropriate data + * transfers. + * + ***************************************************************************/ + +static int pl011_irq_handler(int irq, FAR void *context, FAR void *arg) +{ + FAR struct uart_dev_s *dev = arg; + FAR struct pl011_uart_port_s *sport; + UNUSED(irq); + UNUSED(context); + + DEBUGASSERT(dev != NULL && dev->priv != NULL); + sport = dev->priv; + + if (pl011_irq_rx_ready(sport)) + { + uart_recvchars(dev); + } + + if (pl011_txready(dev)) + { + uart_xmitchars(dev); + } + + return OK; +} + +/*************************************************************************** + * Name: pl011_detach + * + * Description: + * Detach UART interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. The + * exception is the serial console which is never shutdown. + * + ***************************************************************************/ + +static void pl011_detach(FAR struct uart_dev_s *dev) +{ + FAR struct pl011_uart_port_s *sport = dev->priv; + + up_disable_irq(sport->irq_num); + irq_detach(sport->irq_num); +} + +/*************************************************************************** + * Name: pl011_attach + * + * Description: + * Configure the UART to operation in interrupt driven mode. + * This method is called when the serial port is opened. + * Normally, this is just after the setup() method is called, + * however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method + * (unless the hardware supports multiple levels of interrupt + * enabling). The RX and TX interrupts are not enabled until + * the txint() and rxint() methods are called. + * + ***************************************************************************/ + +static int pl011_attach(FAR struct uart_dev_s *dev) +{ + FAR struct pl011_uart_port_s *sport; + FAR struct pl011_data *data; + int ret; + + sport = dev->priv; + data = &sport->data; + + ret = irq_attach(sport->irq_num, pl011_irq_handler, dev); + + if (ret == OK) + { + up_enable_irq(sport->irq_num); + } + else + { + sinfo("error ret=%d\n", ret); + } + + if (!data->sbsa) + { + pl011_enable(sport); + } + + return ret; +} + +/*************************************************************************** + * Name: pl011_shutdown + * + * Description: + * Disable the UART. This method is called when the serial + * port is closed + * + ***************************************************************************/ + +static void pl011_shutdown(FAR struct uart_dev_s *dev) +{ + UNUSED(dev); + sinfo("%s: call unexpected\n", __func__); +} + +static int pl011_setup(FAR struct uart_dev_s *dev) +{ + FAR struct pl011_uart_port_s *sport = dev->priv; + FAR const struct pl011_config *config = &sport->config; + FAR struct pl011_data *data = &sport->data; + int ret; + uint32_t lcrh; + irqstate_t i_flags; + + i_flags = up_irq_save(); + + /* If working in SBSA mode, we assume that UART is already configured, + * or does not require configuration at all (if UART is emulated by + * virtualization software). + */ + + if (!data->sbsa) + { + /* disable the uart */ + + pl011_disable(sport); + pl011_disable_fifo(sport); + + /* Set baud rate */ + + ret = pl011_set_baudrate(sport, config->sys_clk_freq, + data->baud_rate); + if (ret != 0) + { + up_irq_restore(i_flags); + return ret; + } + + /* Setting the default character format */ + + lcrh = config->uart->lcr_h & ~(PL011_LCRH_FORMAT_MASK); + lcrh &= ~(BIT(0) | BIT(7)); + lcrh |= PL011_LCRH_WLEN_SIZE(8) << PL011_LCRH_WLEN_SHIFT; + config->uart->lcr_h = lcrh; + + /* Enabling the FIFOs */ + + pl011_enable_fifo(sport); + } + + /* initialize all IRQs as masked */ + + config->uart->imsc = 0U; + config->uart->icr = PL011_IMSC_MASK_ALL; + + if (!data->sbsa) + { + config->uart->dmacr = 0U; + config->uart->cr &= ~(BIT(14) | BIT(15) | BIT(1)); + config->uart->cr |= PL011_CR_RXE | PL011_CR_TXE; + } + + up_irq_restore(i_flags); + + return 0; +} + +/*************************************************************************** + * Public Functions + ***************************************************************************/ + +/*************************************************************************** + * Name: pl011_earlyserialinit + * + * Description: + * see nuttx/serial/uart_pl011.h + * + ***************************************************************************/ + +void pl011_earlyserialinit(void) +{ + /* Enable the console UART. The other UARTs will be initialized if and + * when they are first opened. + */ +#ifdef CONSOLE_DEV + CONSOLE_DEV.isconsole = true; + pl011_setup(&CONSOLE_DEV); +#endif +} + +/*************************************************************************** + * Name: pl011_serialinit + * + * Description: + * Register serial console and serial ports. This assumes that + * pl011_earlyserialinit was called previously. + * + ***************************************************************************/ + +void pl011_serialinit(void) +{ +#ifdef CONSOLE_DEV + uart_register("/dev/console", &CONSOLE_DEV); +#endif +#ifdef TTYS0_DEV + uart_register("/dev/ttyS0", &TTYS0_DEV); +#endif +#ifdef TTYS1_DEV + uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +#ifdef TTYS2_DEV + uart_register("/dev/ttyS2", &TTYS2_DEV); +#endif +#ifdef TTYS3_DEV + uart_register("/dev/ttyS3", &TTYS3_DEV); +#endif +} + +/*************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ***************************************************************************/ + +#ifdef HAVE_PL011_CONSOLE +int up_putc(int ch) +{ + FAR struct uart_dev_s *dev = &CONSOLE_DEV; + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + pl011_send(dev, '\r'); + } + + pl011_send(dev, ch); + + return ch; +} +#endif + +#endif /* CONFIG_UART_PL011 */ diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index fae2211d598f7..e9bb16af5b2f7 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -234,6 +234,14 @@ config SPI_DRIVER this driver is to support SPI testing. It is not suitable for use in any real driver application. +config SPI_ICE40 + bool "SPI iCE40 driver" + default n + depends on SPI_EXCHANGE + ---help--- + Enable support for a character driver at /dev/ice40-[N] for the iCE40 FPGA. + This driver is intended for uploading the bitsream to the FPGA. + config SPI_BITBANG bool "SPI bit-bang device" default n diff --git a/drivers/spi/Make.defs b/drivers/spi/Make.defs index f5600a368d5c9..acfdf113a972f 100644 --- a/drivers/spi/Make.defs +++ b/drivers/spi/Make.defs @@ -29,6 +29,10 @@ ifeq ($(CONFIG_SPI_EXCHANGE),y) endif endif +ifeq ($(CONFIG_SPI_ICE40),y) + CSRCS += ice40.c +endif + ifeq ($(CONFIG_SPI_SLAVE_DRIVER),y) CSRCS += spi_slave_driver.c endif diff --git a/drivers/spi/ice40.c b/drivers/spi/ice40.c new file mode 100644 index 0000000000000..50b318b59e776 --- /dev/null +++ b/drivers/spi/ice40.c @@ -0,0 +1,411 @@ +/**************************************************************************** + * drivers/spi/ice40.c + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Character driver methods */ + +static int ice40_open(FAR struct file *filep); + +static int ice40_close(FAR struct file *filep); + +static ssize_t ice40_read(FAR struct file *filep, FAR char *buffer, + size_t buflen); +static ssize_t ice40_write(FAR struct file *filep, FAR const char *buffer, + size_t buflen); +static int ice40_ioctl(FAR struct file *filep, int cmd, unsigned long arg); + +/* Helper functions */ + +static int ice40_init_fpga(FAR struct ice40_dev_s *dev); + +static int ice40_writeblk(FAR struct ice40_dev_s *dev, + FAR const char *buffer, + size_t buflen); + +static int ice40_endwrite(FAR struct ice40_dev_s *dev); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct file_operations g_ice40_fops = +{ + ice40_open, /* open */ + ice40_close, /* close */ + ice40_read, /* read */ + ice40_write, /* write */ + NULL, /* seek */ + ice40_ioctl, /* ioctl */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ice40_open + * + * Description: + * This function is called whenever the ICE40 device is opened. + * + ****************************************************************************/ + +static int +ice40_open(FAR struct file *filep) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct ice40_dev_s *dev = inode->i_private; + + DEBUGASSERT(dev != NULL); + + if (dev->is_open) + { + return -EBUSY; + } + + dev->is_open = true; + + return OK; +} + +/**************************************************************************** + * Name: ice40_close + * + * Description: + * This function is called whenever the ICE40 device is closed. + * + ****************************************************************************/ + +static int +ice40_close(FAR struct file *filep) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct ice40_dev_s *dev = inode->i_private; + + DEBUGASSERT(dev != NULL); + + if (dev->in_progress) + { + if (ice40_endwrite(dev)) + { + _err("ERROR: Failed to end writing to FPGA\n"); + dev->is_open = false; + return -EIO; + } + } + + dev->is_open = false; + + return OK; +} + +/**************************************************************************** + * Name: ice40_configspi + * + * Description: + * Configure the SPI instance for to match the DAT-31R5-SP+ + * specifications + * + ****************************************************************************/ + +static inline void +ice40_configspi(FAR struct spi_dev_s *spi) +{ + DEBUGASSERT(spi != NULL); + + /* Configure SPI Mode for the ICE40 */ + + SPI_SETMODE(spi, ICE40_SPI_MODE); + SPI_SETBITS(spi, 8); + + SPI_HWFEATURES(spi, 0); + SPI_SETFREQUENCY(spi, CONFIG_ICE40_SPI_FREQUENCY); +} + +/**************************************************************************** + * Name: ice40_init_fpga + * + * Description: + * Initialize the FPGA - set it to SPI Master load mode + * Reset the FPGA with the CS pin active low + * and send 8 dummy bits with CS high to start the SPI transfer. + * + ****************************************************************************/ + +static int +ice40_init_fpga(FAR struct ice40_dev_s *dev) +{ + DEBUGASSERT(dev != NULL); + DEBUGASSERT(dev->spi != NULL); + + SPI_LOCK(dev->spi, true); + + ice40_configspi(dev->spi); + + dev->ops->reset(dev, true); + up_udelay(2); + dev->ops->select(dev, true); + up_udelay(2); + dev->ops->reset(dev, false); + up_udelay(1200); + + dev->ops->select(dev, false); + SPI_SEND(dev->spi, 0xff); + dev->ops->select(dev, true); + + dev->in_progress = true; + + return 0; +} + +/**************************************************************************** + * Name: ice_v_writeblk + * + * Description: + * Write block to the ICE40 FPGA, max 4096 bytes + ****************************************************************************/ + +static inline int +ice40_writeblk(FAR struct ice40_dev_s *dev, FAR const char *buffer, + size_t buflen) +{ + uint32_t nbytes; + + DEBUGASSERT(dev != NULL); + DEBUGASSERT(dev->spi != NULL); + + DEBUGASSERT(buffer != NULL); + DEBUGASSERT(buflen > 0); + + if (!dev->in_progress) + { + _err("ERROR: FPGA not initialized\n"); + return -EINVAL; + } + + ice40_configspi(dev->spi); + + while (buflen > 0) + { + nbytes = buflen; + if (nbytes >= ICE_SPI_MAX_XFER) + { + nbytes = ICE_SPI_MAX_XFER; + } + + SPI_SNDBLOCK(dev->spi, buffer, nbytes); + + buffer += nbytes; + buflen -= nbytes; + } + + return 0; +} + +/**************************************************************************** + * Name: ice_v_endwrite + * + * Description: + * End writing bitstream to the ICE40 FPGA + ****************************************************************************/ + +static int +ice40_endwrite(FAR struct ice40_dev_s *dev) +{ + ice40_configspi(dev->spi); + int cdone = 0; + + DEBUGASSERT(dev != NULL); + DEBUGASSERT(dev->spi != NULL); + + if (!dev->in_progress) + { + _err("ERROR: FPGA not initialized\n"); + return -EINVAL; + } + + dev->ops->select(dev, false); + + for (size_t i = 0; i < ICE40_SPI_FINAL_CLK_CYCLES + 7 / 8; i++) + { + SPI_SEND(dev->spi, 0xff); + } + + cdone = dev->ops->get_status(dev); + if (cdone == 0) + { + _err("ERROR: CDONE not high after writing to FPGA\n"); + SPI_LOCK(dev->spi, false); + return -ENODEV; + } + + SPI_LOCK(dev->spi, false); + + dev->in_progress = false; + + return 0; +} + +/**************************************************************************** + * Name: ice40_write + * + * Description: + * Write buffer to the ICE40 FPGA + ****************************************************************************/ + +static ssize_t +ice40_write(FAR struct file *filep, FAR const char *buffer, size_t buflen) +{ + int ret; + + DEBUGASSERT(buffer != NULL); + DEBUGASSERT(filep != NULL); + + FAR struct inode *inode = filep->f_inode; + DEBUGASSERT(inode != NULL); + FAR struct ice40_dev_s *dev = inode->i_private; + DEBUGASSERT(dev != NULL); + + DEBUGASSERT(dev->spi != NULL); + + if (!dev->in_progress) + { + ret = ice40_init_fpga(dev); + if (ret < 0) + { + _err("ERROR: Failed to initialize FPGA: %d\n", ret); + return ret; + } + } + + ret = ice40_writeblk(dev, buffer, buflen); + if (ret < 0) + { + _err("ERROR: Failed to write to FPGA: %d\n", ret); + return ret; + } + + return buflen; +} + +/**************************************************************************** + * Name: ice40_read + * + * Description: + * Read is ignored. + ****************************************************************************/ + +static ssize_t +ice40_read(FAR struct file *filep, FAR char *buffer, size_t buflen) +{ + return 0; +} + +/**************************************************************************** + * Name: ice40_ioctl + * + * Description: + * The only available ICTL is RFIOC_SETATT. It expects a struct + * attenuator_control* as the argument to set the attenuation + * level. The channel is ignored as the DAT-31R5-SP+ has just a + * single attenuator. + ****************************************************************************/ + +static int +ice40_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct ice40_dev_s *dev = inode->i_private; + int ret = OK; + + switch (cmd) + { + case FPGAIOC_WRITE_INIT: + ret = ice40_init_fpga(dev); + break; + + case FPGAIOC_WRITE: + ret = ice40_writeblk(dev, (FAR const char *)arg, sizeof(arg)); + break; + case FPGAIOC_WRITE_COMPLETE: + ret = ice40_endwrite(dev); + break; + + default: + sninfo("Unrecognized cmd: %d\n", cmd); + ret = -EINVAL; + break; + } + + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ice40_register + * + * Description: + * Register the ice_v character device as 'devpath'. + * + ****************************************************************************/ + +int ice40_register(FAR const char *path, FAR struct ice40_dev_s *dev) +{ + int ret; + + /* Sanity check */ + + DEBUGASSERT(dev != NULL); + + /* Register the character driver */ + + ret = register_driver(path, &g_ice40_fops, 0666, dev); + if (ret < 0) + { + snerr("ERROR: Failed to register driver: %d\n", ret); + } + + return ret; +} diff --git a/drivers/syslog/Kconfig b/drivers/syslog/Kconfig index 227f81d843a0b..9753aa4417ea4 100644 --- a/drivers/syslog/Kconfig +++ b/drivers/syslog/Kconfig @@ -213,7 +213,7 @@ config RAMLOG_SYSLOG config SYSLOG_RPMSG bool "Log to RPMSG" - depends on RPTUN + depends on RPMSG depends on SCHED_WORKQUEUE default n ---help--- @@ -280,7 +280,7 @@ endif # SYSLOG_RPMSG config SYSLOG_RPMSG_SERVER bool "Enable RPMSG server for SYSLOG" default n - depends on RPTUN + depends on RPMSG ---help--- Use RPMSG to receive message from remote proc. diff --git a/drivers/syslog/syslog_device.c b/drivers/syslog/syslog_device.c index f382be3a6b907..759f3ab251e93 100644 --- a/drivers/syslog/syslog_device.c +++ b/drivers/syslog/syslog_device.c @@ -313,13 +313,6 @@ static int syslog_dev_outputready(FAR struct syslog_dev_s *syslog_dev) return -EAGAIN; /* Can't access the SYSLOG now... maybe next time? */ } - /* NOTE that the scheduler is locked. That is because we do not have - * fully initialized mutex capability until the SYSLOG device is - * successfully initialized. - */ - - sched_lock(); - /* Case (6) */ if (syslog_dev->sl_state == SYSLOG_FAILURE) @@ -352,12 +345,10 @@ static int syslog_dev_outputready(FAR struct syslog_dev_s *syslog_dev) (int)syslog_dev->sl_mode); if (ret < 0) { - sched_unlock(); return ret; } } - sched_unlock(); DEBUGASSERT(syslog_dev->sl_state == SYSLOG_OPENED); } @@ -758,7 +749,6 @@ void syslog_dev_uninitialize(FAR struct syslog_channel_s *channel) /* Attempt to flush any buffered data. */ - sched_lock(); syslog_dev_flush(channel); /* Close the detached file instance, and destroy the mutex. These are @@ -787,5 +777,4 @@ void syslog_dev_uninitialize(FAR struct syslog_channel_s *channel) /* Free the channel structure */ kmm_free(syslog_dev); - sched_unlock(); } diff --git a/drivers/syslog/syslog_filechannel.c b/drivers/syslog/syslog_filechannel.c index 0cf8ba23ef7f2..d6d3041c9dded 100644 --- a/drivers/syslog/syslog_filechannel.c +++ b/drivers/syslog/syslog_filechannel.c @@ -167,6 +167,7 @@ static void log_rotate(FAR const char *log_file) FAR struct syslog_channel_s *syslog_file_channel(FAR const char *devpath) { FAR struct syslog_channel_s *file_channel; + irqstate_t flags; /* Reset the default SYSLOG channel so that we can safely modify the * SYSLOG device. This is an atomic operation and we should be safe @@ -176,7 +177,7 @@ FAR struct syslog_channel_s *syslog_file_channel(FAR const char *devpath) * important debug output is lost while we futz with the channels. */ - sched_lock(); + flags = enter_critical_section(); /* Rotate the log file, if needed. */ @@ -209,7 +210,7 @@ FAR struct syslog_channel_s *syslog_file_channel(FAR const char *devpath) } errout_with_lock: - sched_unlock(); + leave_critical_section(flags); return file_channel; } diff --git a/drivers/syslog/syslog_intbuffer.c b/drivers/syslog/syslog_intbuffer.c index 6347e179f0179..cdff96df3a043 100644 --- a/drivers/syslog/syslog_intbuffer.c +++ b/drivers/syslog/syslog_intbuffer.c @@ -249,6 +249,7 @@ int syslog_add_intbuffer(int ch) int syslog_flush_intbuffer(bool force) { syslog_putc_t putfunc; + irqstate_t flags; int ch; int i; @@ -256,7 +257,7 @@ int syslog_flush_intbuffer(bool force) * concurrent modification by other tasks. */ - sched_lock(); + flags = enter_critical_section(); do { @@ -293,7 +294,7 @@ int syslog_flush_intbuffer(bool force) } while (ch != EOF); - sched_unlock(); + leave_critical_section(flags); return ch; } diff --git a/drivers/syslog/syslog_rpmsg.c b/drivers/syslog/syslog_rpmsg.c index 0409797ffaf6e..99af9e3c7121c 100644 --- a/drivers/syslog/syslog_rpmsg.c +++ b/drivers/syslog/syslog_rpmsg.c @@ -29,6 +29,7 @@ #include #include #include +#include #ifdef CONFIG_ARCH_LOWPUTC #include @@ -188,11 +189,14 @@ static void syslog_rpmsg_putchar(FAR struct syslog_rpmsg_s *priv, int ch, { if (priv->head + 1 - priv->tail >= priv->size) { + bool ret = false; + if (!priv->flush && !up_interrupt_context() && !sched_idletask()) { - syslog_rpmsg_transfer(priv, true); + ret = syslog_rpmsg_transfer(priv, true); } - else + + if (!ret) { /* Overwrite */ diff --git a/drivers/timers/Kconfig b/drivers/timers/Kconfig index cda936a23e19a..0fd4074727aef 100644 --- a/drivers/timers/Kconfig +++ b/drivers/timers/Kconfig @@ -339,6 +339,13 @@ config RTC_MCP794XX if RTC_MCP794XX +config MCP794XX_DATETIME_UTC + bool "Store datetime in UTC" + default n + ---help--- + If set, the datetime is stored in UTC timezone instead of timezone + defined by local time. + config MCP794XX_I2C_FREQUENCY int "MCP794XX I2C frequency" default 400000 @@ -367,12 +374,12 @@ endif # RTC_RX8010SJ config RTC_RPMSG bool "RPMSG RTC Driver" default n - depends on RPTUN + depends on RPMSG select ARCH_HAVE_RTC_SUBSECONDS config RTC_RPMSG_SERVER bool "The RTC RPMSG Role" - depends on RPTUN + depends on RPMSG config RTC_RPMSG_SERVER_NAME string "The name of RTC RPMSG Server" diff --git a/drivers/timers/mcp794xx.c b/drivers/timers/mcp794xx.c index 71881a9d432f0..2734c87f5a2bd 100644 --- a/drivers/timers/mcp794xx.c +++ b/drivers/timers/mcp794xx.c @@ -77,6 +77,7 @@ struct mcp794xx_dev_s { FAR struct i2c_master_s *i2c; /* Contained reference to the I2C bus driver. */ uint8_t addr; /* The I2C device address. */ + bool coarse_trim; /* Coarse trim mode */ }; /**************************************************************************** @@ -182,6 +183,105 @@ static int rtc_bcd2bin(uint8_t value) * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: mcp794xx_rtc_set_trim + * + * Description: + * Sets the digital trimming to correct for inaccuracies of clock source. + * Digital trimming consists of the MCP794XX periodically adding or + * subtracting clock cycles, resulting in small adjustments in the internal + * timing. + * + * Input Parameters: + * trim_val - Calculated trimming value, refer to MCP794XX reference + * manual. + * rtc_slow - True indicates RTC is behind real clock, false otherwise. + * This has to be set to ensure correct trimming direction. + * coarse_mode - MCP794XX allows coarse mode that trims every second + * instead of every minute. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int mcp794xx_rtc_set_trim(uint8_t trim_val, bool rtc_slow, bool coarse_mode) +{ + struct i2c_msg_s msg[2]; + uint8_t buffer[2]; + uint8_t address; + uint8_t ctrl; + int ret; + + if (g_mcp794xx.coarse_trim != coarse_mode) + { + address = MCP794XX_REG_CONTROL; + msg[0].frequency = CONFIG_MCP794XX_I2C_FREQUENCY; + msg[0].addr = g_mcp794xx.addr; + msg[0].flags = I2C_M_NOSTOP; + msg[0].buffer = &address; + msg[0].length = 1; + + msg[1].frequency = CONFIG_MCP794XX_I2C_FREQUENCY; + msg[1].addr = g_mcp794xx.addr; + msg[1].flags = I2C_M_READ; + msg[1].buffer = &ctrl; + msg[1].length = 1; + + ret = I2C_TRANSFER(g_mcp794xx.i2c, msg, 2); + if (ret < 0) + { + rtcerr("ERROR: I2C_TRANSFER failed: %d\n", ret); + return ret; + } + + ctrl &= ~MCP794XX_CONTROL_CRSTRIM; + if (coarse_mode) + { + ctrl |= MCP794XX_CONTROL_CRSTRIM; + } + + buffer[0] = MCP794XX_REG_CONTROL; + buffer[1] = ctrl; + msg[0].frequency = CONFIG_MCP794XX_I2C_FREQUENCY; + msg[0].addr = g_mcp794xx.addr; + msg[0].flags = 0; + msg[0].buffer = buffer; + msg[0].length = 2; + + ret = I2C_TRANSFER(g_mcp794xx.i2c, msg, 1); + if (ret < 0) + { + rtcerr("ERROR: I2C_TRANSFER failed: %d\n", ret); + return ret; + } + + g_mcp794xx.coarse_trim = coarse_mode; + } + + buffer[0] = MCP794XX_REG_OSCTRIM; + buffer[1] = trim_val & 0x7; + if (rtc_slow) + { + buffer[1] |= MCP794XX_OSCTRIM_SIGN; + } + + msg[0].frequency = CONFIG_MCP794XX_I2C_FREQUENCY; + msg[0].addr = g_mcp794xx.addr; + msg[0].flags = 0; + msg[0].buffer = buffer; + msg[0].length = 2; + + ret = I2C_TRANSFER(g_mcp794xx.i2c, msg, 1); + if (ret < 0) + { + rtcerr("ERROR: I2C_TRANSFER failed: %d\n", ret); + return ret; + } + + return OK; +} + /**************************************************************************** * Name: mcp794xx_rtc_initialize * @@ -211,9 +311,10 @@ int mcp794xx_rtc_initialize(FAR struct i2c_master_s *i2c, uint8_t addr) { /* Remember the i2c device and claim that the RTC is enabled */ - g_mcp794xx.i2c = i2c; - g_mcp794xx.addr = addr; - g_rtc_enabled = true; + g_mcp794xx.i2c = i2c; + g_mcp794xx.addr = addr; + g_mcp794xx.coarse_trim = false; + g_rtc_enabled = true; return OK; } @@ -407,11 +508,23 @@ int up_rtc_settime(FAR const struct timespec *tp) newtime++; } +#ifndef CONFIG_MCP794XX_DATETIME_UTC + /* Save datetime in local time. */ + if (localtime_r(&newtime, &newtm) == NULL) { rtcerr("ERROR: localtime_r failed\n"); return -EINVAL; } +#else + /* Save datetime in UTC time. */ + + if (gmtime_r(&newtime, &newtm) == NULL) + { + rtcerr("ERROR: gmtime_r failed\n"); + return -EINVAL; + } +#endif rtc_dumptime(&newtm, "New time"); diff --git a/drivers/timers/rpmsg_rtc.c b/drivers/timers/rpmsg_rtc.c index 0e94e43a89cc9..5f1e051f7f46e 100644 --- a/drivers/timers/rpmsg_rtc.c +++ b/drivers/timers/rpmsg_rtc.c @@ -24,6 +24,7 @@ #include +#include #include #include #include diff --git a/drivers/usbdev/Kconfig b/drivers/usbdev/Kconfig index f38475f42d590..bce9808b258b4 100644 --- a/drivers/usbdev/Kconfig +++ b/drivers/usbdev/Kconfig @@ -25,6 +25,12 @@ config USBDEV_DUALSPEED ---help--- Hardware handles high and full speed operation (USB 2.0) +config USBDEV_EPBUFFER_ALIGNMENT + int "The usbdev ep req bffer aligned bytes" + default 0 + ---help--- + The aligned bytes of usbdev ep req buffer + choice prompt "Select USB device powered" default USBDEV_SELFPOWERED @@ -1223,6 +1229,7 @@ endif # CDCECM config USBDEV_FS bool default n + select SCHED_HPWORK ---help--- Enables USBDEV FS support, userspace can use fs to control USB device. diff --git a/drivers/usbdev/cdcacm.c b/drivers/usbdev/cdcacm.c index ea439d8ec7b62..31a8d868a85b2 100644 --- a/drivers/usbdev/cdcacm.c +++ b/drivers/usbdev/cdcacm.c @@ -222,6 +222,7 @@ static bool cdcuart_rxflowcontrol(FAR struct uart_dev_s *dev, #endif static void cdcuart_txint(FAR struct uart_dev_s *dev, bool enable); static bool cdcuart_txempty(FAR struct uart_dev_s *dev); +static int cdcuart_release(FAR struct uart_dev_s *dev); /**************************************************************************** * Private Data @@ -272,7 +273,8 @@ static const struct uart_ops_s g_uartops = NULL, /* send */ cdcuart_txint, /* txinit */ NULL, /* txready */ - cdcuart_txempty /* txempty */ + cdcuart_txempty, /* txempty */ + cdcuart_release /* release */ }; /**************************************************************************** @@ -866,6 +868,16 @@ static int cdcacm_serialstate(FAR struct cdcacm_dev_s *priv) static void cdcacm_resetconfig(FAR struct cdcacm_dev_s *priv) { + /* When the USB is pulled out, if there is an unprocessed buffer, + * it needs to be push them to upper half serial drivers RX buffer. + */ + + if (priv->nrdq != 0) + { + cdcacm_release_rxpending(priv); + priv->nrdq = 0; + } + /* Are we configured? */ if (priv->config != CDCACM_CONFIGIDNONE) @@ -2800,6 +2812,28 @@ static bool cdcuart_txempty(FAR struct uart_dev_s *dev) return priv->nwrq >= CONFIG_CDCACM_NWRREQS; } +/**************************************************************************** + * Name: cdcuart_release + * + * Description: + * This is called to release some resource about the device when device + * was close and unregistered. + * + ****************************************************************************/ + +static int cdcuart_release(FAR struct uart_dev_s *dev) +{ + FAR struct cdcacm_dev_s *priv = (FAR struct cdcacm_dev_s *)dev->priv; + + usbtrace(CDCACM_CLASSAPI_RELEASE, 0); + + /* And free the memory resources. */ + + wd_cancel(&priv->rxfailsafe); + kmm_free(priv); + return OK; +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -3034,44 +3068,21 @@ int cdcacm_initialize(int minor, FAR void **handle) * standalone USB driver: * * classdev - The class object returned by cdcacm_classobject() - * handle - The opaque handle representing the class object returned by - * a previous call to cdcacm_initialize(). * * Returned Value: * None * ****************************************************************************/ -#ifdef CONFIG_CDCACM_COMPOSITE void cdcacm_uninitialize(FAR struct usbdevclass_driver_s *classdev) -#else -void cdcacm_uninitialize(FAR void *handle) -#endif { -#ifdef CONFIG_CDCACM_COMPOSITE FAR struct cdcacm_driver_s *drvr = (FAR struct cdcacm_driver_s *)classdev; -#else - FAR struct cdcacm_driver_s *drvr = (FAR struct cdcacm_driver_s *)handle; -#endif FAR struct cdcacm_dev_s *priv = drvr->dev; char devname[CDCACM_DEVNAME_SIZE]; int ret; -#ifdef CONFIG_CDCACM_COMPOSITE - /* Check for pass 2 uninitialization. We did most of the work on the - * first pass uninitialization. - */ - - if (priv->minor == (uint8_t)-1) - { - /* In this second and final pass, all that remains to be done is to - * free the memory resources. - */ - - wd_cancel(&priv->rxfailsafe); - kmm_free(priv); - return; - } +#ifndef CONFIG_CDCACM_COMPOSITE + usbdev_unregister(&drvr->drvr); #endif /* Un-register the CDC/ACM TTY device */ @@ -3083,36 +3094,6 @@ void cdcacm_uninitialize(FAR void *handle) usbtrace(TRACE_CLSERROR(USBSER_TRACEERR_UARTUNREGISTER), (uint16_t)-ret); } - - /* Unregister the driver (unless we are a part of a composite device). The - * device unregister logic will (1) return all of the requests to us then - * (2) all the unbind method. - * - * The same thing will happen in the composite case except that: (1) the - * composite driver will call usbdev_unregister() which will (2) return the - * requests for all members of the composite, and (3) call the unbind - * method in the composite device which will (4) call the unbind method - * for this device. - */ - -#ifndef CONFIG_CDCACM_COMPOSITE - usbdev_unregister(&drvr->drvr); - - /* And free the memory resources. */ - - wd_cancel(&priv->rxfailsafe); - kmm_free(priv); - -#else - /* For the case of the composite driver, there is a two pass - * uninitialization sequence. We cannot yet free the driver structure. - * We will do that on the second pass. We mark the fact that we have - * already uninitialized by setting the minor number to -1. If/when we - * are called again, then we will free the memory resources. - */ - - priv->minor = (uint8_t)-1; -#endif } /**************************************************************************** diff --git a/drivers/usbdev/cdcacm.h b/drivers/usbdev/cdcacm.h index 6e97148ef8a9d..00dfe6b58113c 100644 --- a/drivers/usbdev/cdcacm.h +++ b/drivers/usbdev/cdcacm.h @@ -181,6 +181,7 @@ #define CDCACM_CLASSAPI_TXREADY TRACE_EVENT(TRACE_CLASSAPI_ID, USBSER_TRACECLASSAPI_TXREADY) #define CDCACM_CLASSAPI_TXEMPTY TRACE_EVENT(TRACE_CLASSAPI_ID, USBSER_TRACECLASSAPI_TXEMPTY) #define CDCACM_CLASSAPI_FLOWCONTROL TRACE_EVENT(TRACE_CLASSAPI_ID, USBSER_TRACECLASSAPI_FLOWCONTROL) +#define CDCACM_CLASSAPI_RELEASE TRACE_EVENT(TRACE_CLASSAPI_ID, USBSER_TRACECLASSAPI_RELEASE) /**************************************************************************** * Public Types diff --git a/drivers/usbdev/cdcecm.c b/drivers/usbdev/cdcecm.c index 7faf8a501775b..1441a9af1d046 100644 --- a/drivers/usbdev/cdcecm.c +++ b/drivers/usbdev/cdcecm.c @@ -138,7 +138,6 @@ struct cdcecm_driver_s struct net_driver_s dev; /* Interface understood by the * network */ - bool registered; /* netdev is currently registered */ }; /**************************************************************************** @@ -348,8 +347,8 @@ static int cdcecm_txpoll(FAR struct net_driver_s *dev) * * Description: * After a packet has been received and dispatched to the network, it - * may return return with an outgoing packet. This function checks for - * that case and performs the transmission if necessary. + * may return with an outgoing packet. This function checks for that + * case and performs the transmission if necessary. * * Input Parameters: * priv - Reference to the driver state structure @@ -401,7 +400,7 @@ static void cdcecm_receive(FAR struct cdcecm_driver_s *self) * configuration. */ - /* Copy the data data from the hardware to self->dev.d_buf. Set + /* Copy the data from the hardware to self->dev.d_buf. Set * amount of data in self->dev.d_len */ @@ -950,6 +949,7 @@ static void cdcecm_resetconfig(FAR struct cdcecm_driver_s *self) static int cdcecm_setconfig(FAR struct cdcecm_driver_s *self, uint8_t config) { struct usb_epdesc_s epdesc; + bool is_high_speed; int ret = OK; if (config == self->config) @@ -979,7 +979,7 @@ static int cdcecm_setconfig(FAR struct cdcecm_driver_s *self, uint8_t config) self->epint->priv = self; - bool is_high_speed = (self->usbdev.speed == USB_SPEED_HIGH); + is_high_speed = (self->usbdev.speed == USB_SPEED_HIGH); cdcecm_mkepdesc(CDCECM_EP_BULKIN_IDX, &epdesc, &self->devinfo, is_high_speed); ret = EP_CONFIGURE(self->epbulkin, &epdesc, false); @@ -1365,7 +1365,7 @@ static int16_t cdcecm_mkcfgdesc(FAR uint8_t *desc, if (desc) { - FAR struct usb_ifdesc_s *ifdesc = (FAR struct usb_ifdesc_s *)desc; + FAR struct usb_ifdesc_s *ifdesc; ifdesc = (FAR struct usb_ifdesc_s *)desc; ifdesc->len = USB_SIZEOF_IFDESC; @@ -1385,7 +1385,7 @@ static int16_t cdcecm_mkcfgdesc(FAR uint8_t *desc, if (desc) { - FAR struct usb_ifdesc_s *ifdesc = (FAR struct usb_ifdesc_s *)desc; + FAR struct usb_ifdesc_s *ifdesc; ifdesc = (FAR struct usb_ifdesc_s *)desc; ifdesc->len = USB_SIZEOF_IFDESC; @@ -1864,11 +1864,8 @@ static int cdcecm_classobject(int minor, if (ret < 0) { nerr("netdev_register failed. ret: %d\n", ret); - return ret; } - self->registered = true; - *classdev = (FAR struct usbdevclass_driver_s *)self; return ret; } @@ -1887,44 +1884,18 @@ static int cdcecm_classobject(int minor, * CDC/ECM driver is an internal part of a composite device, or a * standalone USB driver: * - * classdev - The class object returned by cdcacm_classobject() - * handle - The opaque handle representing the class object returned by - * a previous call to cdcacm_initialize(). + * classdev - The class object returned by cdcecm_classobject() * * Returned Value: * None * ****************************************************************************/ -#ifdef CONFIG_CDCECM_COMPOSITE void cdcecm_uninitialize(FAR struct usbdevclass_driver_s *classdev) -#else -void cdcecm_uninitialize(FAR void *handle) -#endif { -#ifdef CONFIG_CDCECM_COMPOSITE FAR struct cdcecm_driver_s *self = (FAR struct cdcecm_driver_s *)classdev; -#else - FAR struct cdcecm_driver_s *self = (FAR struct cdcecm_driver_s *)handle; -#endif int ret; -#ifdef CONFIG_CDCECM_COMPOSITE - /* Check for pass 2 uninitialization. We did most of the work on the - * first pass uninitialization. - */ - - if (!self->registered) - { - /* In this second and final pass, all that remains to be done is to - * free the memory resources. - */ - - kmm_free(self); - return; - } -#endif - /* Un-register the CDC/ECM netdev device */ ret = netdev_unregister(&self->dev); @@ -1933,33 +1904,13 @@ void cdcecm_uninitialize(FAR void *handle) nerr("ERROR: netdev_unregister failed. ret: %d\n", ret); } - /* For the case of the composite driver, there is a two pass - * uninitialization sequence. We cannot yet free the driver structure. - * We will do that on the second pass. We mark the fact that we have - * already uninitialized by setting the registered flag to false. - * If/when we are called again, then we will free the memory resources. - */ - - self->registered = false; /* Successfully unregistered netdev */ - - /* Unregister the driver (unless we are a part of a composite device). The - * device unregister logic will (1) return all of the requests to us then - * (2) call the unbind method. - * - * The same thing will happen in the composite case except that: (1) the - * composite driver will call usbdev_unregister() which will (2) return the - * requests for all members of the composite, and (3) call the unbind - * method in the composite device which will (4) call the unbind method - * for this device. - */ - #ifndef CONFIG_CDCECM_COMPOSITE usbdev_unregister(&self->usbdev); +#endif /* And free the driver structure */ kmm_free(self); -#endif } /**************************************************************************** diff --git a/drivers/usbdev/composite.c b/drivers/usbdev/composite.c index 306cc40a6403b..e99844df0ade5 100644 --- a/drivers/usbdev/composite.c +++ b/drivers/usbdev/composite.c @@ -298,8 +298,6 @@ static int16_t composite_mkcfgdesc(FAR struct usbdevclass_driver_s *driver, memcpy(buf, priv->descs->cfgdesc, sizeof(struct usb_cfgdesc_s)); cfgdesc = (FAR struct usb_cfgdesc_s *)buf; - cfgdesc->totallen[0] = LSBYTE(priv->cfgdescsize); - cfgdesc->totallen[1] = MSBYTE(priv->cfgdescsize); cfgdesc->ninterfaces = priv->ninterfaces; /* Increment the size and buf to point right behind the information @@ -329,6 +327,9 @@ static int16_t composite_mkcfgdesc(FAR struct usbdevclass_driver_s *driver, #endif } + cfgdesc->totallen[0] = LSBYTE(total); + cfgdesc->totallen[1] = MSBYTE(total); + return total; } @@ -644,6 +645,20 @@ static int composite_setup(FAR struct usbdevclass_driver_s *driver, { ret = USB_SIZEOF_DEVDESC; memcpy(ctrlreq->buf, priv->descs->devdesc, ret); +#ifdef CONFIG_BOARD_USBDEV_PIDVID + { + uint16_t pid = board_usbdev_pid(); + uint16_t vid = board_usbdev_vid(); + FAR struct usb_devdesc_s *p_desc = + (FAR struct usb_devdesc_s *)ctrlreq->buf; + + p_desc->vendor[0] = LSBYTE(vid); + p_desc->vendor[1] = MSBYTE(vid); + + p_desc->product[0] = LSBYTE(pid); + p_desc->product[1] = MSBYTE(pid); + } +#endif } break; @@ -1002,6 +1017,7 @@ FAR void *composite_initialize(FAR const struct usbdev_devdescs_s *devdescs, FAR struct composite_devdesc_s *pdevices, uint8_t ndevices) { + FAR const struct usbdev_strdesc_s *strdesc; FAR struct composite_alloc_s *alloc; FAR struct composite_dev_s *priv; FAR struct composite_driver_s *drvr; @@ -1059,6 +1075,26 @@ FAR void *composite_initialize(FAR const struct usbdev_devdescs_s *devdescs, priv->ninterfaces += devobj->compdesc.devinfo.ninterfaces; } + /* Update cfgdescsize based on the longest string descriptor */ + +#ifdef CONFIG_BOARD_USBDEV_SERIALSTR + ret = sizeof(struct usb_strdesc_s) + strlen(board_usbdev_serialstr()) * 2; + if (priv->cfgdescsize < ret) + { + priv->cfgdescsize = ret; + } +#endif + + strdesc = devdescs->strdescs->strdesc; + for (i = 0; strdesc[i].string != NULL; i++) + { + ret = sizeof(struct usb_strdesc_s) + strlen(strdesc[i].string) * 2; + if (priv->cfgdescsize < ret) + { + priv->cfgdescsize = ret; + } + } + priv->ndevices = ndevices; /* Initialize the USB class driver structure */ @@ -1115,24 +1151,15 @@ void composite_uninitialize(FAR void *handle) DEBUGASSERT(alloc != NULL); - /* First phase uninitialization each of the member classes */ - priv = &alloc->dev; - for (i = 0; i < priv->ndevices; i++) - { - priv->device[i].compdesc.uninitialize(priv->device[i].dev); - } - /* Then unregister and destroy the composite class */ usbdev_unregister(&alloc->drvr.drvr); - /* Free any resources used by the composite driver */ - - /* None */ - - /* Second phase uninitialization: Clean up all memory resources */ + /* Uninitialization each of the member classes and clean up + * all memory resources + */ for (i = 0; i < priv->ndevices; i++) { diff --git a/drivers/usbdev/mtp.c b/drivers/usbdev/mtp.c index a96022902f43a..2c467190695c8 100644 --- a/drivers/usbdev/mtp.c +++ b/drivers/usbdev/mtp.c @@ -48,11 +48,6 @@ #define USBMTP_CHARDEV_PATH "/dev/mtp" -#define USBMTP_NUM_EPS (3) -#define USBMTP_EP_BULKIN_IDX (0) -#define USBMTP_EP_BULKOUT_IDX (1) -#define USBMTP_EP_INTIN_IDX (2) - /* USB Controller */ #ifdef CONFIG_USBDEV_SELFPOWERED @@ -303,7 +298,7 @@ static int16_t usbclass_mkcfgdesc(FAR uint8_t *buf, { bool hispeed = false; FAR struct usb_epdesc_s *epdesc; - FAR struct mtp_cfgdesc_s *dest; + FAR struct usb_ifdesc_s *dest; #ifdef CONFIG_USBDEV_DUALSPEED hispeed = (speed == USB_SPEED_HIGH); @@ -316,7 +311,7 @@ static int16_t usbclass_mkcfgdesc(FAR uint8_t *buf, } #endif - dest = (FAR struct mtp_cfgdesc_s *)buf; + dest = (FAR struct usb_ifdesc_s *)buf; epdesc = (FAR struct usb_epdesc_s *)(buf + sizeof(g_mtp_ifdesc)); memcpy(dest, &g_mtp_ifdesc, sizeof(g_mtp_ifdesc)); @@ -331,8 +326,8 @@ static int16_t usbclass_mkcfgdesc(FAR uint8_t *buf, #ifdef CONFIG_USBMTP_COMPOSITE /* For composite device, apply possible offset to the interface numbers */ - dest->ifdesc.ifno = devinfo->ifnobase; - dest->ifdesc.iif = devinfo->strbase + USBMTP_INTERFACESTRID; + dest->ifno = devinfo->ifnobase; + dest->iif = devinfo->strbase + USBMTP_INTERFACESTRID; #endif return sizeof(g_mtp_ifdesc) + 3 * USB_SIZEOF_EPDESC; diff --git a/drivers/usbdev/rndis.c b/drivers/usbdev/rndis.c index e6f798eb605ef..2d189d144caab 100644 --- a/drivers/usbdev/rndis.c +++ b/drivers/usbdev/rndis.c @@ -160,8 +160,6 @@ struct rndis_dev_s struct work_s rxwork; /* Worker for dispatching RX packets */ struct work_s pollwork; /* TX poll worker */ - bool registered; /* Has netdev_register() been called */ - uint8_t config; /* USB Configuration number */ FAR struct rndis_req_s *net_req; /* Pointer to request whose buffer is assigned to network */ FAR struct rndis_req_s *rx_req; /* Pointer request container that holds RX buffer */ @@ -2312,12 +2310,6 @@ static void usbclass_unbind(FAR struct usbdevclass_driver_s *driver, usbdev_freereq(priv->epbulkout, priv->rdreq); } - if (priv->registered) - { - netdev_unregister(&priv->netdev); - priv->registered = false; - } - /* Free write requests that are not in use (which should be all * of them */ @@ -2872,34 +2864,18 @@ static int usbclass_classobject(int minor, if (ret) { uerr("Failed to register net device"); - return ret; } - drvr->dev->registered = true; - - return OK; + return ret; } static void usbclass_uninitialize(FAR struct usbdevclass_driver_s *classdev) { FAR struct rndis_driver_s *drvr = (FAR struct rndis_driver_s *)classdev; FAR struct rndis_alloc_s *alloc = (FAR struct rndis_alloc_s *)drvr->dev; - if (!alloc->dev.registered) - { -#ifdef CONFIG_RNDIS_COMPOSITE - kmm_free(alloc); -#endif - return; - } - if (drvr->dev->registered) - { - netdev_unregister(&drvr->dev->netdev); - drvr->dev->registered = false; -#ifndef CONFIG_RNDIS_COMPOSITE - kmm_free(alloc); -#endif - return; - } + + netdev_unregister(&drvr->dev->netdev); + kmm_free(alloc); } /**************************************************************************** diff --git a/drivers/usbdev/usbdev_fs.c b/drivers/usbdev/usbdev_fs.c index 86a5235f974e6..c8093df6e5a0a 100644 --- a/drivers/usbdev/usbdev_fs.c +++ b/drivers/usbdev/usbdev_fs.c @@ -37,6 +37,7 @@ #include #include #include +#include #include "composite.h" #include "usbdev_fs.h" @@ -80,10 +81,11 @@ struct usbdev_fs_ep_s struct usbdev_fs_dev_s { FAR struct composite_dev_s *cdev; - bool registered; uint8_t config; + struct work_s work; struct usbdev_devinfo_s devinfo; FAR struct usbdev_fs_ep_s *eps; + bool uninitialized; }; struct usbdev_fs_driver_s @@ -263,15 +265,7 @@ static void usbdev_fs_rdcomplete(FAR struct usbdev_ep_s *ep, usbtrace(TRACE_CLASSRDCOMPLETE, sq_count(&fs_ep->reqq)); - /* Restart request due to either no reader or - * empty frame received. - */ - - if (fs_ep->crefs == 0) - { - uwarn("drop frame\n"); - goto restart_req; - } + /* Restart request due to empty frame received */ if (req->xfrd <= 0) { @@ -389,7 +383,7 @@ static int usbdev_fs_blocking_io(FAR struct usbdev_fs_ep_s *fs_ep, FAR usbdev_fs_waiter_sem_t **list, FAR struct sq_queue_s *queue) { - FAR usbdev_fs_waiter_sem_t sem; + usbdev_fs_waiter_sem_t sem; irqstate_t flags; int ret; @@ -443,6 +437,8 @@ static int usbdev_fs_blocking_io(FAR struct usbdev_fs_ep_s *fs_ep, cur_sem->next = sem.next; break; } + + cur_sem = cur_sem->next; } } @@ -480,7 +476,7 @@ static int usbdev_fs_open(FAR struct file *filep) fs_ep->crefs += 1; - assert(fs_ep->crefs != 0); + ASSERT(fs_ep->crefs != 0); nxmutex_unlock(&fs_ep->lock); return ret; @@ -514,7 +510,7 @@ static int usbdev_fs_close(FAR struct file *filep) fs_ep->crefs -= 1; - assert(fs_ep->crefs >= 0); + ASSERT(fs_ep->crefs >= 0); if (fs_ep->unlinked && fs_ep->crefs == 0) { @@ -529,10 +525,14 @@ static int usbdev_fs_close(FAR struct file *filep) } } - if (do_free) + if (do_free && fs->uninitialized) { + FAR struct usbdev_fs_driver_s *alloc = container_of( + fs, FAR struct usbdev_fs_driver_s, dev); + kmm_free(fs->eps); fs->eps = NULL; + kmm_free(alloc); } } else @@ -560,8 +560,6 @@ static ssize_t usbdev_fs_read(FAR struct file *filep, FAR char *buffer, irqstate_t flags; int ret; - assert(len > 0 && buffer != NULL); - ret = nxmutex_lock(&fs_ep->lock); if (ret < 0) { @@ -602,7 +600,7 @@ static ssize_t usbdev_fs_read(FAR struct file *filep, FAR char *buffer, /* Device ready for read */ - while (!sq_empty(&fs_ep->reqq) && len > 0) + while (!sq_empty(&fs_ep->reqq)) { FAR struct usbdev_fs_req_s *container; uint16_t reqlen; @@ -618,16 +616,24 @@ static ssize_t usbdev_fs_read(FAR struct file *filep, FAR char *buffer, { /* Output buffer full */ - memcpy(&buffer[retlen], - &container->req->buf[container->offset], - len); + if (buffer != NULL) + { + memcpy(&buffer[retlen], + &container->req->buf[container->offset], + len); + } + container->offset += len; retlen += len; break; } - memcpy(&buffer[retlen], - &container->req->buf[container->offset], reqlen); + if (buffer != NULL) + { + memcpy(&buffer[retlen], + &container->req->buf[container->offset], reqlen); + } + retlen += reqlen; len -= reqlen; @@ -648,6 +654,16 @@ static ssize_t usbdev_fs_read(FAR struct file *filep, FAR char *buffer, PANIC(); } + + /* The container buffer length is less than the maximum length. + * It is an independent packet of requests and needs to be + * returned directly. + */ + + if (reqlen < fs_ep->ep->maxpacket) + { + break; + } } nxmutex_unlock(&fs_ep->lock); @@ -713,7 +729,7 @@ static ssize_t usbdev_fs_write(FAR struct file *filep, /* Device ready for write */ - while (len > 0 && !sq_empty(&fs_ep->reqq)) + while (!sq_empty(&fs_ep->reqq)) { uint16_t cur_len; @@ -756,9 +772,12 @@ static ssize_t usbdev_fs_write(FAR struct file *filep, wlen += cur_len; len -= cur_len; + if (len == 0) + { + break; + } } - assert(wlen > 0); ret = wlen; errout: @@ -790,14 +809,6 @@ static int usbdev_fs_poll(FAR struct file *filep, FAR struct pollfd *fds, return ret; } - /* Check if the usbdev device has been unbind */ - - if (fs_ep->unlinked) - { - nxmutex_unlock(&fs_ep->lock); - return -ENOTCONN; - } - if (!setup) { /* This is a request to tear down the poll. */ @@ -842,9 +853,16 @@ static int usbdev_fs_poll(FAR struct file *filep, FAR struct pollfd *fds, eventset = 0; + /* Check if the usbdev device has been unbind */ + + if (fs_ep->unlinked) + { + eventset |= POLLHUP; + } + /* Notify the POLLIN/POLLOUT event if at least one request is available */ - if (!sq_empty(&fs_ep->reqq)) + else if (!sq_empty(&fs_ep->reqq)) { if (USB_ISEPIN(fs_ep->ep->eplog)) { @@ -856,7 +874,7 @@ static int usbdev_fs_poll(FAR struct file *filep, FAR struct pollfd *fds, } } - poll_notify(&fds, 1, eventset); + poll_notify(fs_ep->fds, CONFIG_USBDEV_FS_NPOLLWAITERS, eventset); exit_leave_critical: leave_critical_section(flags); @@ -883,12 +901,12 @@ static void usbdev_fs_connect(FAR struct usbdev_fs_dev_s *fs, int connect) if (connect) { - /* Notify poll/select with POLLIN */ + /* Notify poll/select with POLLPRI */ for (cnt = 0; cnt < devinfo->nendpoints; cnt++) { fs_ep = &fs->eps[cnt]; - poll_notify(fs_ep->fds, CONFIG_USBDEV_FS_NPOLLWAITERS, POLLIN); + poll_notify(fs_ep->fds, CONFIG_USBDEV_FS_NPOLLWAITERS, POLLPRI); } } else @@ -913,8 +931,7 @@ static void usbdev_fs_connect(FAR struct usbdev_fs_dev_s *fs, int connect) * ****************************************************************************/ -static int usbdev_fs_ep_bind(FAR const char *devname, - FAR struct usbdev_s *dev, uint8_t epno, +static int usbdev_fs_ep_bind(FAR struct usbdev_s *dev, uint8_t epno, FAR const struct usbdev_epinfo_s *epinfo, FAR struct usbdev_fs_ep_s *fs_ep) { @@ -978,8 +995,7 @@ static int usbdev_fs_ep_bind(FAR const char *devname, } fs_ep->crefs = 0; - - return register_driver(devname, &g_usbdev_fs_fops, 0666, fs_ep); + return 0; } /**************************************************************************** @@ -999,6 +1015,8 @@ static void usbdev_fs_ep_unbind(FAR const char *devname, /* Release request buffer */ + nxmutex_lock(&fs_ep->lock); + if (fs_ep->reqbuffer) { for (i = 0; i < epinfo->reqnum; i++) @@ -1035,8 +1053,13 @@ static void usbdev_fs_ep_unbind(FAR const char *devname, if (fs_ep->crefs <= 0) { + nxmutex_unlock(&fs_ep->lock); nxmutex_destroy(&fs_ep->lock); } + else + { + nxmutex_unlock(&fs_ep->lock); + } } /**************************************************************************** @@ -1071,6 +1094,43 @@ static void usbdev_fs_classresetconfig(FAR struct usbdev_fs_dev_s *fs) } } +/**************************************************************************** + * Name: usbdev_fs_register_driver + * + * Description: + * Register the driver after successful set configuration. + * + ****************************************************************************/ + +static void usbdev_fs_register_driver(FAR void *arg) +{ + FAR struct usbdev_fs_dev_s *fs = arg; + FAR struct usbdev_devinfo_s *devinfo = &fs->devinfo; + int i; + + for (i = 0; i < devinfo->nendpoints; i++) + { + char devname[32]; + int ret; + + snprintf(devname, sizeof(devname), "%s/ep%d", + devinfo->name, i + 1); + ret = register_driver(devname, &g_usbdev_fs_fops, 0666, &fs->eps[i]); + if (ret < 0) + { + uerr("Failed to register driver:%s, ret:%d\n", devname, ret); + while (i--) + { + snprintf(devname, sizeof(devname), "%s/ep%d", + devinfo->name, i + 1); + unregister_driver(devname); + } + + break; + } + } +} + /**************************************************************************** * Name: usbdev_fs_classsetconfig * @@ -1135,6 +1195,7 @@ static int usbdev_fs_classsetconfig(FAR struct usbdev_fs_dev_s *fs, } fs->config = config; + work_queue(HPWORK, &fs->work, usbdev_fs_register_driver, fs, 0); /* We are successfully configured. Char device is now active */ @@ -1161,7 +1222,6 @@ static int usbdev_fs_classbind(FAR struct usbdevclass_driver_s *driver, driver, FAR struct usbdev_fs_driver_s, drvr); FAR struct usbdev_fs_dev_s *fs = &fs_drvr->dev; FAR struct usbdev_devinfo_s *devinfo = &fs->devinfo; - char devname[32]; uint16_t i; int ret; @@ -1181,9 +1241,7 @@ static int usbdev_fs_classbind(FAR struct usbdevclass_driver_s *driver, for (i = 0; i < devinfo->nendpoints; i++) { fs->eps[i].dev = fs; - snprintf(devname, sizeof(devname), "%s/ep%d", - devinfo->name, i + 1); - ret = usbdev_fs_ep_bind(devname, dev, + ret = usbdev_fs_ep_bind(dev, devinfo->epno[i], devinfo->epinfos[i], &fs->eps[i]); @@ -1388,7 +1446,6 @@ int usbdev_fs_classobject(int minor, alloc->drvr.ops = &g_usbdev_fs_classops; *classdev = &alloc->drvr; - alloc->dev.registered = true; return OK; } @@ -1404,15 +1461,19 @@ void usbdev_fs_classuninitialize(FAR struct usbdevclass_driver_s *classdev) { FAR struct usbdev_fs_driver_s *alloc = container_of( classdev, FAR struct usbdev_fs_driver_s, drvr); + FAR struct usbdev_fs_dev_s *fs = &alloc->dev; + int i; - if (alloc->dev.registered) - { - alloc->dev.registered = false; - } - else + fs->uninitialized = true; + for (i = 0; i < fs->devinfo.nendpoints; i++) { - kmm_free(alloc); + if (fs->eps != NULL && fs->eps[i].crefs > 0) + { + return; + } } + + kmm_free(alloc); } /**************************************************************************** diff --git a/drivers/usbdev/usbdev_req.c b/drivers/usbdev/usbdev_req.c index a5b3d7801f153..19652f24daaad 100644 --- a/drivers/usbdev/usbdev_req.c +++ b/drivers/usbdev/usbdev_req.c @@ -47,7 +47,11 @@ # define EP_ALLOCBUFFER(ep,nb) (ep)->ops->allocbuffer(ep,nb) # define EP_FREEBUFFER(ep,buf) (ep)->ops->freebuffer(ep,buf) #else -# define EP_ALLOCBUFFER(ep,nb) kmm_malloc(nb) +# if CONFIG_USBDEV_EPBUFFER_ALIGNMENT != 0 +# define EP_ALLOCBUFFER(ep,nb) kmm_memalign(CONFIG_USBDEV_EPBUFFER_ALIGNMENT, nb) +# else +# define EP_ALLOCBUFFER(ep,nb) kmm_malloc(nb) +# endif # define EP_FREEBUFFER(ep,buf) kmm_free(buf) #endif diff --git a/drivers/usbdev/usbmsc.c b/drivers/usbdev/usbmsc.c index 98247d41aee8b..a2c91853b0c3a 100644 --- a/drivers/usbdev/usbmsc.c +++ b/drivers/usbdev/usbmsc.c @@ -1745,7 +1745,7 @@ int usbmsc_classobject(FAR void *handle, void usbmsc_uninitialize(FAR void *handle) { - FAR struct usbmsc_alloc_s *alloc = (FAR struct usbmsc_alloc_s *)handle; + FAR struct usbmsc_alloc_s *alloc = handle; FAR struct usbmsc_dev_s *priv; irqstate_t flags; int ret; @@ -1761,22 +1761,6 @@ void usbmsc_uninitialize(FAR void *handle) priv = &alloc->dev; -#ifdef CONFIG_USBMSC_COMPOSITE - /* Check for pass 2 uninitialization. We did most of the work on the - * first pass uninitialization. - */ - - if (priv->thpid == 0) - { - /* In this second and final pass, all that remains to be done is to - * free the memory resources. - */ - - kmm_free(priv); - return; - } -#endif - /* If the thread hasn't already exitted, tell it to exit now */ if (priv->thstate != USBMSC_STATE_NOTSTARTED) @@ -1855,16 +1839,7 @@ void usbmsc_uninitialize(FAR void *handle) nxsem_destroy(&priv->thsynch); nxmutex_destroy(&priv->thlock); nxsem_destroy(&priv->thwaitsem); - -#ifndef CONFIG_USBMSC_COMPOSITE - /* For the case of the composite driver, there is a two pass - * uninitialization sequence. We cannot yet free the driver structure. - * We will do that on the second pass (and we will know that it is the - * second pass because of priv->thpid == 0) - */ - kmm_free(priv); -#endif } /**************************************************************************** diff --git a/drivers/usbhost/Kconfig b/drivers/usbhost/Kconfig index 38d5aa40faab5..f0ee0beec3ad2 100644 --- a/drivers/usbhost/Kconfig +++ b/drivers/usbhost/Kconfig @@ -721,4 +721,13 @@ config USBHOST_FT232R_LATENCY endif # USBHOST_FT232R +config USBHOST_BTHCI + bool "Bluetooth HCI Driver" + default n + depends on WIRELESS_BLUETOOTH && USBHOST_HAVE_ASYNCH && !USBHOST_BULK_DISABLE && !USBHOST_INT_DISABLE + select USBHOST_ASYNCH + select SERIAL_REMOVABLE + ---help--- + Select this option to build in support for USB Bluetooth HCI devices. + endif # USBHOST diff --git a/drivers/usbhost/Make.defs b/drivers/usbhost/Make.defs index 1aa8cb8090946..02b4ffa81120c 100644 --- a/drivers/usbhost/Make.defs +++ b/drivers/usbhost/Make.defs @@ -70,6 +70,10 @@ ifeq ($(CONFIG_USBHOST_FT232R),y) CSRCS += usbhost_ft232r.c endif +ifeq ($(CONFIG_USBHOST_BTHCI),y) +CSRCS += usbhost_bthci.c +endif + # HCD debug/trace logic ifeq ($(CONFIG_USBHOST_TRACE),y) diff --git a/drivers/usbhost/usbhost_bthci.c b/drivers/usbhost/usbhost_bthci.c new file mode 100644 index 0000000000000..1b14a0b778747 --- /dev/null +++ b/drivers/usbhost/usbhost_bthci.c @@ -0,0 +1,1519 @@ +/**************************************************************************** + * drivers/usbhost/usbhost_bthci.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SCHED_WORKQUEUE +# warning "Worker thread support is required (CONFIG_SCHED_WORKQUEUE)" +#endif + +/* Driver support ***********************************************************/ + +/* This format is used to construct the /dev/bthci[n] device driver path. It + * defined here so that it will be used consistently in all places. + */ + +#define DEV_FORMAT "/dev/bthci%c" +#define DEV_NAMELEN 12 + +/* Used in usbhci_cfgdesc() */ + +#define USBHOST_IFFOUND 0x01 +#define USBHOST_BINFOUND 0x02 +#define USBHOST_BOUTFOUND 0x04 +#define USBHOST_IINFOUND 0x08 +#define USBHOST_ALLFOUND 0x0F + +#define USBHOST_MAX_CREFS 0x7fff + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure contains the internal, private state of the USB host class + * driver. + */ + +struct usbhost_state_s +{ + /* This is the externally visible portion of the state */ + + struct usbhost_class_s usbclass; + struct bt_driver_s btdev; + + /* The remainder of the fields are provide to the class driver */ + + char devchar; /* Character identifying the /dev/bthci[n] device */ + volatile bool disconnected; /* TRUE: Device has been disconnected */ + uint8_t ifno; /* Interface number */ + mutex_t lock; /* Used to maintain mutual exclusive access */ + struct work_s work; /* For interacting with the worker thread */ + FAR uint8_t *tbuffer; /* The allocated transfer buffer */ + size_t tbuflen; /* Size of the allocated transfer buffer */ + usbhost_ep_t bulkin; /* Bulk IN endpoint */ + usbhost_ep_t bulkout; /* Bulk OUT endpoint */ + usbhost_ep_t intin; /* Interrupt endpoint */ + FAR uint8_t *ctrlreq; /* Allocated ctrl request structure */ + FAR uint8_t *evbuffer; /* Allocated event buffer */ + size_t evbuflen; /* Size of the allocated event buffer */ + struct work_s acwork; /* For asynchronous event work */ + struct work_s evwork; /* For asynchronous event work */ + int16_t acbytes; /* The number of bytes actually transferred */ + int16_t evbytes; /* The number of bytes actually transferred */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Memory allocation services */ + +static inline FAR struct usbhost_state_s *usbhost_allocclass(void); +static inline void usbhost_freeclass(FAR struct usbhost_state_s *usbclass); + +/* Device name management */ + +static int usbhost_allocdevno(FAR struct usbhost_state_s *priv); +static void usbhost_freedevno(FAR struct usbhost_state_s *priv); +static inline void usbhost_mkdevname(FAR struct usbhost_state_s *priv, + FAR char *devname); + +/* Worker thread actions */ + +static void usbhost_destroy(FAR void *arg); + +/* Helpers for usbhci_connect() */ + +static inline int usbhci_cfgdesc(FAR struct usbhost_state_s *priv, + FAR const uint8_t *configdesc, + int desclen); +static inline int usbhost_devinit(FAR struct usbhost_state_s *priv); + +/* (Little Endian) Data helpers */ + +static inline uint16_t usbhost_getle16(const uint8_t *val); +static inline void usbhost_putle16(uint8_t *dest, uint16_t val); + +/* Transfer descriptor memory management */ + +static inline int usbhost_talloc(FAR struct usbhost_state_s *priv); +static inline void usbhost_tfree(FAR struct usbhost_state_s *priv); + +/* struct usbhost_registry_s methods */ + +static struct usbhost_class_s * + usbhost_create(FAR struct usbhost_hubport_s *hport, + FAR const struct usbhost_id_s *id); + +/* struct usbhost_class_s methods */ + +static int usbhci_connect(FAR struct usbhost_class_s *usbclass, + FAR const uint8_t *configdesc, int desclen); +static int usbhost_disconnected(FAR struct usbhost_class_s *usbclass); + +/* Driver methods -- + * depend upon the type of NuttX driver interface exported + */ + +static int usbhost_ctrl_cmd(FAR struct usbhost_state_s *priv, + uint8_t type, uint8_t req, uint16_t value, + uint16_t iface, uint8_t *payload, uint16_t len); +static void usbhost_event_work(FAR void *arg); +static void usbhost_event_callback(FAR void *arg, ssize_t nbytes); +static void usbhost_acl_callback(FAR void *arg, ssize_t nbytes); + +static ssize_t usbhost_cmd_tx(FAR struct usbhost_state_s *priv, + FAR const void *buffer, size_t buflen); +static ssize_t usbhost_acl_tx(FAR struct usbhost_state_s *priv, + FAR const void *buffer, size_t buflen); + +static int usbhost_bthci_send(FAR struct bt_driver_s *dev, + enum bt_buf_type_e type, + FAR void *data, size_t len); +static int usbhost_bthci_open(FAR struct bt_driver_s *dev); +static void usbhost_bthci_close(FAR struct bt_driver_s *dev); +static int usbhost_bthci_ioctl(FAR struct bt_driver_s *dev, + int cmd, unsigned long arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This structure provides the registry entry ID information that will be + * used to associate the USB class driver to a connected USB device. + */ + +static const struct usbhost_id_s g_id[] = +{ + { + USB_CLASS_WIRELESS_CONTROLLER, /* base */ + 0x01, /* subclass */ + 0x01, /* proto */ + 0, /* vid */ + 0 /* pid */ + }, +}; + +/* This is the USB host bthci class's registry entry */ + +static struct usbhost_registry_s g_bthci = +{ + NULL, /* flink */ + usbhost_create, /* create */ + 1, /* nids */ + &g_id[0] /* id[] */ +}; + +/* This is a bitmap that is used to allocate device names /dev/bthcia-z. */ + +static uint32_t g_devinuse; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_allocclass + * + * Description: + * This is really part of the logic that implements the create() method + * of struct usbhost_registry_s. This function allocates memory for one + * new class instance. + * + * Input Parameters: + * None + * + * Returned Value: + * On success, this function will return a non-NULL instance of struct + * usbhost_class_s. NULL is returned on failure; this function will + * will fail only if there are insufficient resources to create another + * USB host class instance. + * + ****************************************************************************/ + +static inline FAR struct usbhost_state_s *usbhost_allocclass(void) +{ + FAR struct usbhost_state_s *priv; + + DEBUGASSERT(!up_interrupt_context()); + + priv = (FAR struct usbhost_state_s *) + kmm_malloc(sizeof(struct usbhost_state_s)); + + uinfo("Allocated: %p\n", priv); + return priv; +} + +/**************************************************************************** + * Name: usbhost_freeclass + * + * Description: + * Free a class instance previously allocated by usbhost_allocclass(). + * + * Input Parameters: + * usbclass - A reference to the class instance to be freed. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void usbhost_freeclass(FAR struct usbhost_state_s *usbclass) +{ + DEBUGASSERT(usbclass != NULL); + + /* Free the class instance (perhaps calling sched_kmm_free() in case we are + * executing from an interrupt handler. + */ + + uinfo("Freeing: %p\n", usbclass); + kmm_free(usbclass); +} + +/**************************************************************************** + * Name: Device name management + * + * Description: + * Some tiny functions to coordinate management of device names. + * + ****************************************************************************/ + +static int usbhost_allocdevno(FAR struct usbhost_state_s *priv) +{ + irqstate_t flags; + int devno; + + flags = enter_critical_section(); + for (devno = 0; devno < 26; devno++) + { + uint32_t bitno = 1 << devno; + if ((g_devinuse & bitno) == 0) + { + g_devinuse |= bitno; + priv->devchar = 'a' + devno; + leave_critical_section(flags); + return OK; + } + } + + leave_critical_section(flags); + return -EMFILE; +} + +static void usbhost_freedevno(FAR struct usbhost_state_s *priv) +{ + if (priv->devchar >= 'a') + { + int devno = priv->devchar - 'a'; + + if (devno >= 0 && devno < 26) + { + irqstate_t flags = enter_critical_section(); + g_devinuse &= ~(1 << devno); + leave_critical_section(flags); + } + } +} + +static inline void usbhost_mkdevname(FAR struct usbhost_state_s *priv, + FAR char *devname) +{ + snprintf(devname, DEV_NAMELEN, DEV_FORMAT, priv->devchar); +} + +/**************************************************************************** + * Name: usbhost_destroy + * + * Description: + * The USB device has been disconnected and the reference count on the USB + * host class instance has gone to 1.. Time to destroy the USB host class + * instance. + * + * Input Parameters: + * arg - A reference to the class instance to be destroyed. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void usbhost_destroy(FAR void *arg) +{ + FAR struct usbhost_state_s *priv = (FAR struct usbhost_state_s *)arg; + FAR struct usbhost_hubport_s *hport; + FAR struct usbhost_driver_s *drvr; + + DEBUGASSERT(priv != NULL && priv->usbclass.hport != NULL); + hport = priv->usbclass.hport; + + DEBUGASSERT(hport->drvr); + drvr = hport->drvr; + + /* Release the device name used by this connection */ + + usbhost_freedevno(priv); + + /* Free the endpoints */ + + if (priv->bulkin) + { + DRVR_EPFREE(hport->drvr, priv->bulkin); + } + + if (priv->bulkout) + { + DRVR_EPFREE(hport->drvr, priv->bulkout); + } + + /* Cancel any pending asynchronous I/O */ + + if (priv->intin) + { + DRVR_EPFREE(hport->drvr, priv->intin); + } + + /* Free any transfer buffers */ + + usbhost_tfree(priv); + + /* Destroy the semaphores */ + + nxmutex_destroy(&priv->lock); + + /* Disconnect the USB host device */ + + DRVR_DISCONNECT(drvr, hport); + + /* Free the function address assigned to this device */ + + usbhost_devaddr_destroy(hport, hport->funcaddr); + hport->funcaddr = 0; + + /* And free the class instance. Hmmm.. this may execute on the worker + * thread and the work structure is part of what is getting freed. That + * should be okay because once the work contained is removed from the + * queue, it should not longer be accessed by the worker thread. + */ + + usbhost_freeclass(priv); +} + +/**************************************************************************** + * Name: usbhci_cfgdesc + * + * Description: + * This function implements the connect() method of struct + * usbhost_class_s. This method is a callback into the class + * implementation. It is used to provide the device's configuration + * descriptor to the class so that the class may initialize properly + * + * Input Parameters: + * priv - The USB host class instance. + * configdesc - A pointer to a uint8_t buffer container the configuration + * descriptor. + * desclen - The length in bytes of the configuration descriptor. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static inline int usbhci_cfgdesc(FAR struct usbhost_state_s *priv, + FAR const uint8_t *configdesc, int desclen) +{ + FAR struct usbhost_hubport_s *hport; + FAR struct usb_cfgdesc_s *cfgdesc; + FAR struct usb_desc_s *desc; + FAR struct usbhost_epdesc_s bindesc; + FAR struct usbhost_epdesc_s boutdesc; + FAR struct usbhost_epdesc_s iindesc; + int remaining; + uint8_t found = 0; + int ret; + + DEBUGASSERT(priv != NULL && priv->usbclass.hport && + configdesc != NULL && desclen >= sizeof(struct usb_cfgdesc_s)); + hport = priv->usbclass.hport; + + /* Verify that we were passed a configuration descriptor */ + + cfgdesc = (FAR struct usb_cfgdesc_s *)configdesc; + if (cfgdesc->type != USB_DESC_TYPE_CONFIG) + { + return -EINVAL; + } + + /* Get the total length of the configuration descriptor (little endian). + * It might be a good check to get the number of interfaces here too. + */ + + remaining = (int)usbhost_getle16(cfgdesc->totallen); + + /* Skip to the next entry descriptor */ + + configdesc += cfgdesc->len; + remaining -= cfgdesc->len; + + /* Loop where there are more dscriptors to examine */ + + while (remaining >= sizeof(struct usb_desc_s)) + { + /* What is the next descriptor? */ + + desc = (FAR struct usb_desc_s *)configdesc; + switch (desc->type) + { + /* Interface descriptor. We really should get the number of endpoints + * from this descriptor too. + */ + + case USB_DESC_TYPE_INTERFACE: + { + FAR struct usb_ifdesc_s *ifdesc = + (FAR struct usb_ifdesc_s *)configdesc; + + DEBUGASSERT(remaining >= USB_SIZEOF_IFDESC); + + /* Save the interface number and mark ONLY the interface found */ + + if (ifdesc->ifno == 0) + { + priv->ifno = ifdesc->ifno; + found |= USBHOST_IFFOUND; + } + } + break; + + /* Endpoint descriptor. Here, we expect two bulk endpoints, an IN + * and an OUT. + */ + + case USB_DESC_TYPE_ENDPOINT: + { + FAR struct usb_epdesc_s *epdesc = + (FAR struct usb_epdesc_s *)configdesc; + + DEBUGASSERT(remaining >= USB_SIZEOF_EPDESC); + + if ((epdesc->attr & USB_EP_ATTR_XFERTYPE_MASK) == + USB_EP_ATTR_XFER_INT) + { + if (USB_ISEPIN(epdesc->addr)) + { + iindesc.hport = hport; + iindesc.addr = epdesc->addr & + USB_EP_ADDR_NUMBER_MASK; + iindesc.in = true; + iindesc.xfrtype = USB_EP_ATTR_XFER_INT; + iindesc.interval = epdesc->interval; + iindesc.mxpacketsize = + usbhost_getle16(epdesc->mxpacketsize); + + if (iindesc.addr == 1) + { + found |= USBHOST_IINFOUND; + } + } + } + + /* Check for a bulk endpoint. */ + + if ((epdesc->attr & USB_EP_ATTR_XFERTYPE_MASK) == + USB_EP_ATTR_XFER_BULK) + { + /* Yes.. it is a bulk endpoint. IN or OUT? */ + + if (USB_ISEPOUT(epdesc->addr)) + { + /* It is an OUT bulk endpoint. There should be only one + * bulk OUT endpoint. + */ + + if ((found & USBHOST_BOUTFOUND) != 0) + { + /* Oops.. more than one endpoint. We don't know + * what to do with this. + */ + + return -EINVAL; + } + + /* Save the bulk OUT endpoint information */ + + boutdesc.hport = hport; + boutdesc.addr = epdesc->addr & + USB_EP_ADDR_NUMBER_MASK; + boutdesc.in = false; + boutdesc.xfrtype = USB_EP_ATTR_XFER_BULK; + boutdesc.interval = epdesc->interval; + boutdesc.mxpacketsize = + usbhost_getle16(epdesc->mxpacketsize); + + if (boutdesc.addr == 2) + { + found |= USBHOST_BOUTFOUND; + } + } + else + { + /* It is an IN bulk endpoint. There should be only one + * bulk IN endpoint. + */ + + if ((found & USBHOST_BINFOUND) != 0) + { + /* Oops.. more than one endpoint. We don't know + * what to do with this. + */ + + return -EINVAL; + } + + /* Save the bulk IN endpoint information */ + + bindesc.hport = hport; + bindesc.addr = epdesc->addr & + USB_EP_ADDR_NUMBER_MASK; + bindesc.in = 1; + bindesc.xfrtype = USB_EP_ATTR_XFER_BULK; + bindesc.interval = epdesc->interval; + bindesc.mxpacketsize = + usbhost_getle16(epdesc->mxpacketsize); + + if (bindesc.addr == 2) + { + found |= USBHOST_BINFOUND; + } + } + } + } + break; + + /* Other descriptors are just ignored for now */ + + default: + break; + } + + /* If we found everything we need with this interface, then break out + * of the loop early. + */ + + if (found == USBHOST_ALLFOUND) + { + break; + } + + /* Increment the address of the next descriptor */ + + configdesc += desc->len; + remaining -= desc->len; + } + + /* Sanity checking... did we find all of things that we need? */ + + if (found != USBHOST_ALLFOUND) + { + uerr("ERROR: Found IF:%s IIN:%s BIN:%s BOUT:%s\n", + (found & USBHOST_IFFOUND) != 0 ? "YES" : "NO", + (found & USBHOST_IINFOUND) != 0 ? "YES" : "NO", + (found & USBHOST_BINFOUND) != 0 ? "YES" : "NO", + (found & USBHOST_BOUTFOUND) != 0 ? "YES" : "NO"); + return -EINVAL; + } + + /* We are good... Allocate the endpoints */ + + ret = DRVR_EPALLOC(hport->drvr, &boutdesc, &priv->bulkout); + if (ret < 0) + { + uerr("ERROR: Failed to allocate Bulk OUT endpoint\n"); + return ret; + } + + ret = DRVR_EPALLOC(hport->drvr, &bindesc, &priv->bulkin); + if (ret < 0) + { + uerr("ERROR: Failed to allocate Bulk IN endpoint\n"); + DRVR_EPFREE(hport->drvr, priv->bulkout); + return ret; + } + + ret = DRVR_EPALLOC(hport->drvr, &iindesc, &priv->intin); + if (ret < 0) + { + uerr("ERROR: Failed to allocate Interrupt IN endpoint\n"); + (void)DRVR_EPFREE(hport->drvr, priv->bulkout); + (void)DRVR_EPFREE(hport->drvr, priv->bulkin); + return ret; + } + + uinfo("Endpoints allocated\n"); + return OK; +} + +/**************************************************************************** + * Name: usbhost_ctrl_cmd + * + * Description: + * Do a USB control transfer. + * + * Input Parameters: + * priv - A reference to the USB host class instance. + * type - Transfer flags. + * req - control transfer type. + * value - Value for control transfer. + * index - Index for control transfer. + * payload - Data buffer. + * len - Length of data buffer. + * + * Returned Value: + * 0 on success. Negated errno on failure. + * + ****************************************************************************/ + +static int usbhost_ctrl_cmd(FAR struct usbhost_state_s *priv, + uint8_t type, uint8_t req, uint16_t value, + uint16_t indx, uint8_t *payload, uint16_t len) +{ + FAR struct usbhost_hubport_s *hport; + struct usb_ctrlreq_s *ctrlreq; + int ret; + + hport = priv->usbclass.hport; + + ctrlreq = (struct usb_ctrlreq_s *)priv->ctrlreq; + ctrlreq->type = type; + ctrlreq->req = req; + + usbhost_putle16(ctrlreq->value, value); + usbhost_putle16(ctrlreq->index, indx); + usbhost_putle16(ctrlreq->len, len); + + if (type & USB_REQ_DIR_IN) + { + ret = DRVR_CTRLIN(hport->drvr, hport->ep0, ctrlreq, payload); + } + else + { + ret = DRVR_CTRLOUT(hport->drvr, hport->ep0, ctrlreq, payload); + } + + return ret; +} + +/**************************************************************************** + * Name: usbhost_event_callback + * + * Description: + * Handle event packet reception + * + * Input Parameters: + * arg - The argument provided when the asynchronous I/O was setup + * nbytes - The number of bytes actually transferred (or a negated errno + * value). + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void usbhost_event_callback(FAR void *arg, ssize_t nbytes) +{ + FAR struct usbhost_state_s *priv; + + priv = (FAR struct usbhost_state_s *)arg; + DEBUGASSERT(priv); + + if (priv->intin) + { + priv->evbytes = (int16_t)nbytes; + + if (priv->evbytes >= 0 && work_available(&priv->evwork)) + { + work_queue(LPWORK, &priv->evwork, + usbhost_event_work, + priv, 0); + } + } +} + +/**************************************************************************** + * Name: usbhost_event_work + * + * Description: + * Receive bluetooth events. + * + * Input Parameters: + * arg - A reference to the USB host class instance. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void usbhost_event_work(FAR void *arg) +{ + FAR struct usbhost_state_s *priv; + FAR struct usbhost_hubport_s *hport; + int ret; + + priv = (FAR struct usbhost_state_s *)arg; + DEBUGASSERT(priv); + + hport = priv->usbclass.hport; + DEBUGASSERT(hport); + + if (priv->evbytes > 0) + { + bt_netdev_receive(&priv->btdev, BT_EVT, priv->evbuffer, + priv->evbytes); + priv->evbytes = 0; + } + + if (priv->intin) + { + ret = DRVR_ASYNCH(hport->drvr, priv->intin, + (FAR uint8_t *)priv->evbuffer, + priv->evbuflen, usbhost_event_callback, + priv); + if (ret < 0) + { + uerr("ERROR: DRVR_ASYNCH failed: %d\n", ret); + } + } +} + +/**************************************************************************** + * Name: usbhost_cmd_tx + * + * Description: + * Send a bluetooth HCI command. + * + * Input Parameters: + * priv - A reference to the USB host class instance. + * buffer - The buffer to be sent by the driver. + * len - The length of the buffer. + * + * Returned Value: + * Zero is returned on success; a negated errno value is returned on any + * failure. + * + ****************************************************************************/ + +static ssize_t usbhost_cmd_tx(FAR struct usbhost_state_s *priv, + FAR const void *buffer, size_t buflen) +{ + int ret; + + nxmutex_lock(&priv->lock); + + ret = usbhost_ctrl_cmd(priv, + USB_REQ_DIR_OUT | USB_REQ_TYPE_CLASS | + USB_REQ_RECIPIENT_DEVICE, + 0, 0, 0, (uint8_t *)buffer, buflen); + + nxmutex_unlock(&priv->lock); + + return ret; +} + +/**************************************************************************** + * Name: usbhost_acl_work + * + * Description: + * Receive bluetooth ACL packets. + * + * Input Parameters: + * arg - A reference to the USB host class instance. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void usbhost_acl_work(FAR void *arg) +{ + FAR struct usbhost_state_s *priv; + FAR struct usbhost_hubport_s *hport; + int ret; + + priv = (FAR struct usbhost_state_s *)arg; + DEBUGASSERT(priv); + + hport = priv->usbclass.hport; + DEBUGASSERT(hport); + + if (priv->acbytes > 0) + { + bt_netdev_receive(&priv->btdev, BT_ACL_IN, priv->tbuffer, + priv->acbytes); + priv->acbytes = 0; + } + + if (priv->bulkin) + { + ret = DRVR_ASYNCH(hport->drvr, priv->bulkin, + (FAR uint8_t *)priv->tbuffer, + priv->tbuflen, usbhost_acl_callback, + priv); + if (ret < 0) + { + uerr("ERROR: DRVR_ASYNCH failed: %d\n", ret); + } + } +} + +/**************************************************************************** + * Name: usbhost_acl_callback + * + * Description: + * Handle ACL packet reception + * + * Input Parameters: + * arg - The argument provided when the asynchronous I/O was setup + * nbytes - The number of bytes actually transferred (or a negated errno + * value). + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void usbhost_acl_callback(FAR void *arg, ssize_t nbytes) +{ + FAR struct usbhost_state_s *priv; + + priv = (FAR struct usbhost_state_s *)arg; + DEBUGASSERT(priv); + + if (priv->bulkin) + { + priv->acbytes = (int16_t)nbytes; + + if (priv->acbytes >= 0 && work_available(&priv->acwork)) + { + work_queue(LPWORK, &priv->acwork, usbhost_acl_work, priv, 0); + } + } +} + +/**************************************************************************** + * Name: usbhost_acl_tx + * + * Description: + * Send a bluetooth ACL packet. + * + * Input Parameters: + * priv - A reference to the USB host class instance. + * buffer - The buffer to be sent by the driver. + * len - The length of the buffer. + * + * Returned Value: + * Zero is returned on success; a negated errno value is returned on any + * failure. + * + ****************************************************************************/ + +static ssize_t usbhost_acl_tx(FAR struct usbhost_state_s *priv, + FAR const void *buffer, size_t buflen) +{ + ssize_t nwritten = 0; + FAR struct usbhost_hubport_s *hport; + hport = priv->usbclass.hport; + DEBUGASSERT(hport); + + nxmutex_lock(&priv->lock); + + nwritten = DRVR_TRANSFER(hport->drvr, priv->bulkout, + (uint8_t *)buffer, buflen); + + if (nwritten < 0) + { + uerr("ERROR: DRVR_TRANSFER for ACL failed: %d\n", (int)nwritten); + } + else + { + nwritten = OK; + } + + nxmutex_unlock(&priv->lock); + + return nwritten; +} + +/**************************************************************************** + * Name: usbhost_bthci_send + * + * Description: + * Send the packet in the provided buffer. + * + * Input Parameters: + * btdev - An instance of the BT low-level driver's interface structure. + * type - The type of packet in the buffer. + * data - The buffer to be sent by the driver. + * len - The length of the buffer. + * + * Returned Value: + * Zero is returned on success; a negated errno value is returned on any + * failure. + * + ****************************************************************************/ + +static int usbhost_bthci_send(FAR struct bt_driver_s *dev, + enum bt_buf_type_e type, + FAR void *data, size_t len) +{ + int ret; + FAR struct usbhost_state_s *priv; + priv = container_of(dev, struct usbhost_state_s, btdev); + + if (type == BT_CMD) + { + ret = usbhost_cmd_tx(priv, data, len); + } + else if (type == BT_ACL_OUT) + { + ret = usbhost_acl_tx(priv, data, len); + } + else + { + ret = -EINVAL; + uerr("ERROR: unexpected packet type %x\n", type); + } + + return ret; +} + +/**************************************************************************** + * Name: usbhost_bthci_open + * + * Description: + * Initialize the bluetooth hardware. + * + * Input Parameters: + * dev - An instance of the BT low-level driver's interface structure. + * + * Returned Value: + * Zero is returned on success; a negated errno value is returned on any + * failure. + * + ****************************************************************************/ + +static int usbhost_bthci_open(FAR struct bt_driver_s *dev) +{ + return OK; +} + +/**************************************************************************** + * Name: usbhost_bthci_close + * + * Description: + * Close the bluetooth hardware. + * + * Input Parameters: + * dev - An instance of the BT low-level driver's interface structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void usbhost_bthci_close(FAR struct bt_driver_s *dev) +{ +} + +/**************************************************************************** + * Name: usbhost_bthci_ioctl + * + * Description: + * Handle IOCTL commands directed to this device. + * + * Input Parameters: + * dev - An instance of the BT low-level driver's interface structure. + * cmd - The IOCTL command + * arg - The argument for the IOCTL command + * + * Returned Value: + * Zero is returned on success; a negated errno value is returned on any + * failure. + * + ****************************************************************************/ + +static int usbhost_bthci_ioctl(FAR struct bt_driver_s *dev, + int cmd, unsigned long arg) +{ + return -ENOTTY; +} + +/**************************************************************************** + * Name: usbhost_devinit + * + * Description: + * The USB device has been successfully connected. This completes the + * initialization operations. It is first called after the + * configuration descriptor has been received. + * + * This function is called from the connect() method. This function always + * executes on the thread of the caller of connect(). + * + * Input Parameters: + * priv - A reference to the class instance. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline int usbhost_devinit(FAR struct usbhost_state_s *priv) +{ + int ret = OK; + + if (priv->bulkin && work_available(&priv->acwork)) + { + /* Begin monitoring of acl packets */ + + work_queue(LPWORK, &priv->acwork, usbhost_acl_work, priv, 0); + } + + if (priv->intin && work_available(&priv->evwork)) + { + /* Begin monitoring of message available events */ + + work_queue(LPWORK, &priv->evwork, usbhost_event_work, priv, 0); + } + + if (ret >= 0 && priv->devchar == 'a') + { + /* Register the driver with the network stack. */ + + ret = bt_netdev_register(&priv->btdev); + if (ret < 0) + { + uerr("ERROR: bt_netdev_register failed: %d\n", ret); + } + } + + /* Check if we successfully initialized. */ + + if (ret >= 0) + { + /* Ready for normal operation */ + + uinfo("Successfully initialized\n"); + } + + return ret; +} + +/**************************************************************************** + * Name: usbhost_getle16 + * + * Description: + * Get a (possibly unaligned) 16-bit little endian value. + * + * Input Parameters: + * val - A pointer to the first byte of the little endian value. + * + * Returned Value: + * A uint16_t representing the whole 16-bit integer value + * + ****************************************************************************/ + +static inline uint16_t usbhost_getle16(const uint8_t *val) +{ + return (uint16_t)val[1] << 8 | (uint16_t)val[0]; +} + +/**************************************************************************** + * Name: usbhost_putle16 + * + * Description: + * Put a (possibly unaligned) 16-bit little endian value. + * + * Input Parameters: + * dest - A pointer to the first byte to save the little endian value. + * val - The 16-bit value to be saved. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void usbhost_putle16(uint8_t *dest, uint16_t val) +{ + /* Little endian means LSB first in byte stream */ + + dest[0] = val & 0xff; + dest[1] = val >> 8; +} + +/**************************************************************************** + * Name: usbhost_talloc + * + * Description: + * Allocate transfer buffer memory. + * + * Input Parameters: + * priv - A reference to the class instance. + * + * Returned Value: + * On success, zero (OK) is returned. On failure, an negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +static inline int usbhost_talloc(FAR struct usbhost_state_s *priv) +{ + FAR struct usbhost_hubport_s *hport; + size_t maxlen; + int ret; + + DEBUGASSERT(priv != NULL && priv->usbclass.hport != NULL && + priv->tbuffer == NULL); + hport = priv->usbclass.hport; + + /* Allocate buffer for events. */ + + if (priv->intin) + { + ret = DRVR_ALLOC(hport->drvr, &priv->evbuffer, &priv->evbuflen); + if (ret < 0) + { + uerr("ERROR: DRVR_IOALLOC of evbuffer failed: %d\n", ret); + return ret; + } + } + + /* Allocate memory for control requests */ + + ret = DRVR_ALLOC(hport->drvr, (FAR uint8_t **)&priv->ctrlreq, &maxlen); + if (ret < 0) + { + uerr("ERROR: DRVR_ALLOC of ctrlreq failed: %d\n", ret); + + usbhost_tfree(priv); + return ret; + } + + DEBUGASSERT(maxlen >= sizeof(struct usb_ctrlreq_s)); + + ret = DRVR_ALLOC(hport->drvr, &priv->tbuffer, &priv->tbuflen); + if (ret < 0) + { + uerr("ERROR: DRVR_ALLOC of buffer failed: %d\n", ret); + usbhost_tfree(priv); + } + + return ret; +} + +/**************************************************************************** + * Name: usbhost_tfree + * + * Description: + * Free transfer buffer memory. + * + * Input Parameters: + * priv - A reference to the class instance. + * + * Returned Value: + * On success, zero (OK) is returned. On failure, an negated errno value + * is returned to indicate the nature of the failure. + * + ****************************************************************************/ + +static inline void usbhost_tfree(FAR struct usbhost_state_s *priv) +{ + FAR struct usbhost_hubport_s *hport; + + DEBUGASSERT(priv != NULL && priv->usbclass.hport != NULL); + hport = priv->usbclass.hport; + + if (priv->evbuffer) + { + DRVR_FREE(hport->drvr, priv->evbuffer); + priv->evbuffer = NULL; + priv->evbuflen = 0; + } + + if (priv->ctrlreq) + { + DRVR_FREE(hport->drvr, priv->ctrlreq); + priv->ctrlreq = NULL; + } + + if (priv->tbuffer) + { + DRVR_FREE(hport->drvr, priv->tbuffer); + priv->tbuffer = NULL; + priv->tbuflen = 0; + } +} + +/**************************************************************************** + * struct usbhost_registry_s methods + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_create + * + * Description: + * This function implements the create() method of struct + * usbhost_registry_s. The create() method is a callback into the class + * implementation. It is used to (1) create a new instance of the USB + * host class state and to (2) bind a USB host driver "session" to the + * class instance. Use of this create() method will support environments + * where there may be multiple USB ports and multiple USB devices + * simultaneously connected. + * + * Input Parameters: + * hport - The hub port that manages the new class instance. + * id - In the case where the device supports multiple base classes, + * subclasses, or protocols, this specifies which to configure for. + * + * Returned Value: + * On success, this function will return a non-NULL instance of struct + * usbhost_class_s that can be used by the USB host driver to communicate + * with the USB host class. NULL is returned on failure; this function + * will fail only if the hport input parameter is NULL or if there are + * insufficient resources to create another USB host class instance. + * + ****************************************************************************/ + +static FAR struct usbhost_class_s * +usbhost_create(FAR struct usbhost_hubport_s *hport, + FAR const struct usbhost_id_s *id) +{ + FAR struct usbhost_state_s *priv; + + /* Allocate a USB host class instance */ + + priv = usbhost_allocclass(); + if (priv == NULL) + { + return NULL; + } + + /* Initialize the allocated storage class instance */ + + memset(priv, 0, sizeof(struct usbhost_state_s)); + + /* Assign a device number to this class instance */ + + if (usbhost_allocdevno(priv) == OK) + { + /* Initialize class method function pointers */ + + priv->usbclass.hport = hport; + priv->usbclass.connect = usbhci_connect; + priv->usbclass.disconnected = usbhost_disconnected; + + priv->btdev.open = usbhost_bthci_open; + priv->btdev.send = usbhost_bthci_send; + priv->btdev.close = usbhost_bthci_close; + priv->btdev.ioctl = usbhost_bthci_ioctl; + + /* Initialize semaphores + * (this works okay in the interrupt context) + */ + + nxmutex_init(&priv->lock); + + /* Return the instance of the USB class driver */ + + return &priv->usbclass; + } + + /* An error occurred. Free the allocation and return NULL on all failures */ + + usbhost_freeclass(priv); + + return NULL; +} + +/**************************************************************************** + * struct usbhost_class_s methods + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhci_connect + * + * Description: + * This function implements the connect() method of struct + * usbhost_class_s. This method is a callback into the class + * implementation. It is used to provide the device's configuration + * descriptor to the class so that the class may initialize properly + * + * Input Parameters: + * usbclass - The USB host class entry previously obtained from a call to + * create(). + * configdesc - A pointer to a uint8_t buffer container the configuration + * descriptor. + * desclen - The length in bytes of the configuration descriptor. + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * NOTE that the class instance remains valid upon return with a failure. + * It is the responsibility of the higher level enumeration logic to call + * CLASS_DISCONNECTED to free up the class driver resources. + * + * Assumptions: + * - This function will *not* be called from an interrupt handler. + * - If this function returns an error, the USB host controller driver + * must call to DISCONNECTED method to recover from the error + * + ****************************************************************************/ + +static int usbhci_connect(FAR struct usbhost_class_s *usbclass, + FAR const uint8_t *configdesc, int desclen) +{ + FAR struct usbhost_state_s *priv = (FAR struct usbhost_state_s *)usbclass; + int ret; + + DEBUGASSERT(priv != NULL && + configdesc != NULL && + desclen >= sizeof(struct usb_cfgdesc_s)); + + /* Parse the configuration descriptor to get the endpoints */ + + ret = usbhci_cfgdesc(priv, configdesc, desclen); + if (ret < 0) + { + uerr("ERROR: usbhci_cfgdesc() failed: %d\n", ret); + } + else + { + ret = usbhost_talloc(priv); + if (ret < 0) + { + uerr("ERROR: Failed to allocate transfer buffer\n"); + return ret; + } + + /* Now configure the device and register the NuttX driver */ + + ret = usbhost_devinit(priv); + if (ret < 0) + { + uerr("ERROR: usbhost_devinit() failed: %d\n", ret); + } + } + + return ret; +} + +/**************************************************************************** + * Name: usbhost_disconnected + * + * Description: + * This function implements the disconnected() method of struct + * usbhost_class_s. This method is a callback into the class + * implementation. It is used to inform the class that the USB device has + * been disconnected. + * + * Input Parameters: + * usbclass - The USB host class entry previously obtained from a call to + * create(). + * + * Returned Value: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function may be called from an interrupt handler. + * + ****************************************************************************/ + +static int usbhost_disconnected(struct usbhost_class_s *usbclass) +{ + FAR struct usbhost_state_s *priv = (FAR struct usbhost_state_s *)usbclass; + irqstate_t flags; + + DEBUGASSERT(priv != NULL); + + /* Set an indication to any users of the device that the device is no + * longer available. + */ + + flags = enter_critical_section(); + + priv->disconnected = true; + + if (priv->devchar == 'a') + { + bt_netdev_unregister(&priv->btdev); + } + + /* Cancel any ongoing transfers */ + + work_cancel(LPWORK, &priv->acwork); + work_cancel(LPWORK, &priv->evwork); + + /* Destroy the class instance. If we are executing from an interrupt + * handler, then defer the destruction to the worker thread. + * Otherwise, destroy the instance now. + */ + + if (up_interrupt_context()) + { + /* Destroy the instance on the worker thread. */ + + DEBUGASSERT(priv->work.worker == NULL); + work_queue(LPWORK, &priv->work, usbhost_destroy, priv, 0); + } + else + { + /* Do the work now */ + + usbhost_destroy(priv); + } + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbhost_bthci_initialize + * + * Description: + * Initialize the USB class driver. This function should be called + * be platform-specific code in order to initialize and register support + * for the USB host class device. + * + * Input Parameters: + * None + * + * Returned Value: + * On success this function will return zero (OK); A negated errno value + * will be returned on failure. + * + ****************************************************************************/ + +int usbhost_bthci_initialize(void) +{ + /* Advertise our availability to support (certain) devices */ + + return usbhost_registerclass(&g_bthci); +} diff --git a/drivers/usbhost/usbhost_cdcmbim.c b/drivers/usbhost/usbhost_cdcmbim.c index 83e99272cc533..2df0f29262b5d 100644 --- a/drivers/usbhost/usbhost_cdcmbim.c +++ b/drivers/usbhost/usbhost_cdcmbim.c @@ -256,6 +256,7 @@ static void usbhost_notification_work(FAR void *arg); static void usbhost_notification_callback(FAR void *arg, ssize_t nbytes); static void usbhost_rxdata_work(FAR void *arg); static void usbhost_bulkin_work(FAR void *arg); +static void usbhost_bulkin_callback(FAR void *arg, ssize_t nbytes); static void usbhost_destroy(FAR void *arg); diff --git a/drivers/usbhost/usbhost_skeleton.c b/drivers/usbhost/usbhost_skeleton.c index 0c34f04e62bbb..5e0ecc971b86e 100644 --- a/drivers/usbhost/usbhost_skeleton.c +++ b/drivers/usbhost/usbhost_skeleton.c @@ -53,8 +53,8 @@ /* Driver support ***********************************************************/ -/* This format is used to construct the /dev/skel[n] device driver path. It - * defined here so that it will be used consistently in all places. +/* The format used to construct device file path, defined for consistent use + * from all places. */ #define DEV_FORMAT "/dev/skel%c" @@ -73,9 +73,7 @@ * Private Types ****************************************************************************/ -/* This structure contains the internal, private state of the USB host class - * driver. - */ +/* This is the internal, private state of the USB host class driver. */ struct usbhost_state_s { @@ -85,16 +83,16 @@ struct usbhost_state_s /* The remainder of the fields are provide to the class driver */ - char devchar; /* Character identifying the /dev/skel[n] device */ - volatile bool disconnected; /* TRUE: Device has been disconnected */ - uint8_t ifno; /* Interface number */ - int16_t crefs; /* Reference count on the driver instance */ - mutex_t lock; /* Used to maintain mutual exclusive access */ - struct work_s work; /* For interacting with the worker thread */ - FAR uint8_t *tbuffer; /* The allocated transfer buffer */ - size_t tbuflen; /* Size of the allocated transfer buffer */ - usbhost_ep_t epin; /* IN endpoint */ - usbhost_ep_t epout; /* OUT endpoint */ + char devchar; /* char in /dev/skel[n] format name */ + volatile bool disconnected; /* TRUE: Device has been disconnected */ + uint8_t ifno; /* Interface number */ + int16_t crefs; /* Reference count on the driver instance */ + mutex_t lock; /* Used for mutual exclusive access */ + struct work_s work; /* For interacting with the worker thread */ + FAR uint8_t *tbuffer; /* The allocated transfer buffer */ + size_t tbuflen; /* Size of the allocated transfer buffer */ + usbhost_ep_t epin; /* IN endpoint */ + usbhost_ep_t epout; /* OUT endpoint */ }; /**************************************************************************** @@ -156,8 +154,8 @@ static int usbhost_disconnected(FAR struct usbhost_class_s *usbclass); * Private Data ****************************************************************************/ -/* This structure provides the registry entry ID information that will be - * used to associate the USB class driver to a connected USB device. +/* This structure provides the registry entry ID information that will be + * used to associate the USB host class driver to a connected USB device. */ static const struct usbhost_id_s g_id = @@ -169,7 +167,7 @@ static const struct usbhost_id_s g_id = 0 /* pid */ }; -/* This is the USB host storage class's registry entry */ +/* This is the USB host class' registry entry */ static struct usbhost_registry_s g_skeleton = { @@ -179,7 +177,7 @@ static struct usbhost_registry_s g_skeleton = &g_id /* id[] */ }; -/* This is a bitmap that is used to allocate device names /dev/skela-z. */ +/* The bitmap depicting allocated device names in "/dev/skel[a-z]". */ static uint32_t g_devinuse; diff --git a/drivers/usrsock/Kconfig b/drivers/usrsock/Kconfig index 25d48d8d6afbe..2920575a2a9de 100644 --- a/drivers/usrsock/Kconfig +++ b/drivers/usrsock/Kconfig @@ -39,7 +39,7 @@ endif # NET_USRSOCK config NET_USRSOCK_RPMSG_SERVER bool "RPMSG usrsock" default n - depends on NET && RPTUN + depends on NET && RPMSG ---help--- Enable usrsock through RPMSG channel. diff --git a/drivers/usrsock/usrsock_rpmsg_server.c b/drivers/usrsock/usrsock_rpmsg_server.c index 9020ec8201efd..df8657fb621a4 100644 --- a/drivers/usrsock/usrsock_rpmsg_server.c +++ b/drivers/usrsock/usrsock_rpmsg_server.c @@ -32,6 +32,7 @@ #include +#include #include #include #include diff --git a/drivers/video/CMakeLists.txt b/drivers/video/CMakeLists.txt index 3462ba26e2fe7..50716d37a8be4 100644 --- a/drivers/video/CMakeLists.txt +++ b/drivers/video/CMakeLists.txt @@ -29,7 +29,7 @@ if(CONFIG_DRIVERS_VIDEO) endif() if(CONFIG_VIDEO_STREAM) - list(APPEND SRCS video.c video_framebuff.c) + list(APPEND SRCS v4l2_core.c video_framebuff.c v4l2_cap.c v4l2_m2m.c) endif() # These video drivers depend on I2C support diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 06669725cdaa4..5f5fbfc6fcdcb 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -49,6 +49,7 @@ if DRIVERS_VIDEO config VIDEO_FB bool "Framebuffer character driver" default n + select ARCH_VMA_MAPPING if BUILD_KERNEL config VIDEO_FB_NPOLLWAITERS int "Video fb poll count of each open structure" diff --git a/drivers/video/Make.defs b/drivers/video/Make.defs index 3bd614f612daa..b217a72e9c084 100644 --- a/drivers/video/Make.defs +++ b/drivers/video/Make.defs @@ -27,7 +27,7 @@ ifeq ($(CONFIG_VIDEO_FB),y) endif ifeq ($(CONFIG_VIDEO_STREAM),y) - CSRCS += video.c video_framebuff.c + CSRCS += v4l2_core.c video_framebuff.c v4l2_cap.c v4l2_m2m.c endif # These video drivers depend on I2C support diff --git a/drivers/video/fb.c b/drivers/video/fb.c index 5dcb9b41643d5..a0a1df78fa68d 100644 --- a/drivers/video/fb.c +++ b/drivers/video/fb.c @@ -135,6 +135,12 @@ static int fb_sem_wait(FAR struct fb_chardev_s *fb, static void fb_sem_post(FAR struct fb_chardev_s *fb, int overlay); #endif +#ifdef CONFIG_BUILD_KERNEL +static int fb_munmap(FAR struct task_group_s *group, + FAR struct mm_map_entry_s *entry, + FAR void *start, size_t length); +#endif + /**************************************************************************** * Private Data ****************************************************************************/ @@ -1002,6 +1008,22 @@ static int fb_ioctl(FAR struct file *filep, int cmd, unsigned long arg) return ret; } +#ifdef CONFIG_BUILD_KERNEL +static int fb_munmap(FAR struct task_group_s *group, + FAR struct mm_map_entry_s *entry, + FAR void *start, size_t length) +{ + if (group && entry) + { + ginfo("%p, len=%zu\n", entry->vaddr, entry->length); + vm_unmap_region(entry->vaddr, entry->length); + mm_map_remove(get_current_mm(), entry); + } + + return OK; +} +#endif + static int fb_mmap(FAR struct file *filep, FAR struct mm_map_entry_s *map) { FAR struct inode *inode; @@ -1032,7 +1054,15 @@ static int fb_mmap(FAR struct file *filep, FAR struct mm_map_entry_s *map) if (map->offset >= 0 && map->offset < panelinfo.fblen && map->length && map->offset + map->length <= panelinfo.fblen) { +#ifdef CONFIG_BUILD_KERNEL + map->vaddr = vm_map_region((uintptr_t)panelinfo.fbmem + map->offset, + panelinfo.fblen); + map->length = panelinfo.fblen; + map->munmap = fb_munmap; + mm_map_add(get_current_mm(), map); +#else map->vaddr = (FAR char *)panelinfo.fbmem + map->offset; +#endif return OK; } @@ -1610,51 +1640,3 @@ int fb_register_device(int display, int plane, kmm_free(fb); return ret; } - -/**************************************************************************** - * Name: fb_register - * - * Description: - * Register the framebuffer character device at /dev/fbN where N is the - * display number if the devices supports only a single plane. If the - * hardware supports multiple color planes, then the device will be - * registered at /dev/fbN.M where N is the again display number but M - * is the display plane. - * - * Input Parameters: - * display - The display number for the case of boards supporting multiple - * displays or for hardware that supports multiple - * layers (each layer is consider a display). Typically zero. - * plane - Identifies the color plane on hardware that supports separate - * framebuffer "planes" for each color component. - * - * Returned Value: - * Zero (OK) is returned success; a negated errno value is returned on any - * failure. - * - ****************************************************************************/ - -int fb_register(int display, int plane) -{ - FAR struct fb_vtable_s *vtable; - int ret; - - /* Initialize the frame buffer device. */ - - ret = up_fbinitialize(display); - if (ret < 0) - { - gerr("ERROR: up_fbinitialize() failed for display %d: %d\n", - display, ret); - return ret; - } - - vtable = up_fbgetvplane(display, plane); - if (vtable == NULL) - { - gerr("ERROR: up_fbgetvplane() failed, vplane=%d\n", plane); - return -EINVAL; - } - - return fb_register_device(display, plane, vtable); -} diff --git a/drivers/video/goldfish_camera.c b/drivers/video/goldfish_camera.c index a397b6e996b51..8984f46ecced3 100644 --- a/drivers/video/goldfish_camera.c +++ b/drivers/video/goldfish_camera.c @@ -34,6 +34,7 @@ #include #include #include +#include /**************************************************************************** * Pre-processor Definitions @@ -779,10 +780,7 @@ int goldfish_camera_initialize(void) snprintf(devpath, sizeof(devpath), "/dev/video%zd", i); } - video_register(devpath, - &priv[i]->data, - &sensor, - 1); + capture_register(devpath, &priv[i]->data, &sensor, 1); } return 0; diff --git a/drivers/video/isx012.c b/drivers/video/isx012.c index cc6200bee2a4f..97910971e85d0 100644 --- a/drivers/video/isx012.c +++ b/drivers/video/isx012.c @@ -195,8 +195,7 @@ struct isx012_dev_s struct imgsensor_s sensor; mutex_t i2c_lock; FAR struct i2c_master_s *i2c; /* I2C interface */ - uint8_t i2c_addr; /* I2C address */ - int i2c_freq; /* Frequency */ + struct i2c_config_s i2c_cfg; /* I2C config */ isx012_state_t state; /* ISX012 status */ uint8_t mode; /* ISX012 mode */ isx012_rect_t clip_video; /* Clip information for VIDEO */ @@ -216,7 +215,7 @@ typedef struct isx012_dev_s isx012_dev_t; static uint16_t isx012_getreg(FAR isx012_dev_t *priv, uint16_t regaddr, uint16_t regsize); static int isx012_putreg(FAR isx012_dev_t *priv, uint16_t regaddr, - uint16_t regval, uint16_t regsize); + uint32_t regval, uint16_t regsize); static int isx012_putreglist(FAR isx012_dev_t *priv, FAR const isx012_reg_t *reglist, size_t nentries); #ifdef ISX012_CHECK_IN_DETAIL @@ -675,16 +674,10 @@ static isx012_dev_t g_isx012_private = static uint16_t isx012_getreg(FAR isx012_dev_t *priv, uint16_t regaddr, uint16_t regsize) { - struct i2c_config_s config; - volatile uint16_t regval = 0; - volatile uint8_t buffer[2]; + uint16_t regval = 0; + uint8_t buffer[2]; int ret; - /* Set up the I2C configuration */ - - config.frequency = priv->i2c_freq; - config.address = priv->i2c_addr; - config.addrlen = 7; buffer[0] = regaddr >> 8; buffer[1] = regaddr & 0xff; @@ -692,7 +685,7 @@ static uint16_t isx012_getreg(FAR isx012_dev_t *priv, /* Write the register address */ - ret = i2c_write(priv->i2c, &config, (FAR uint8_t *)buffer, 2); + ret = i2c_write(priv->i2c, &priv->i2c_cfg, (FAR uint8_t *)buffer, 2); if (ret < 0) { verr("i2c_write failed: %d\n", ret); @@ -701,7 +694,8 @@ static uint16_t isx012_getreg(FAR isx012_dev_t *priv, { /* Restart and read 16bits from the register */ - ret = i2c_read(priv->i2c, &config, (FAR uint8_t *)buffer, regsize); + ret = i2c_read(priv->i2c, &priv->i2c_cfg, + (FAR uint8_t *)buffer, regsize); if (ret < 0) { verr("i2c_read failed: %d\n", ret); @@ -719,17 +713,12 @@ static uint16_t isx012_getreg(FAR isx012_dev_t *priv, } static int isx012_putreg(FAR isx012_dev_t *priv, - uint16_t regaddr, uint16_t regval, uint16_t regsize) + uint16_t regaddr, uint32_t regval, uint16_t regsize) { - struct i2c_config_s config; - volatile uint8_t buffer[4]; + uint8_t buffer[6]; int ret; - /* Set up the I2C configuration */ - - config.frequency = priv->i2c_freq; - config.address = priv->i2c_addr; - config.addrlen = 7; + DEBUGASSERT(regsize <= 4); /* Set up for the transfer */ @@ -742,7 +731,7 @@ static int isx012_putreg(FAR isx012_dev_t *priv, /* And do it */ - ret = i2c_write(priv->i2c, &config, + ret = i2c_write(priv->i2c, &priv->i2c_cfg, (FAR uint8_t *)buffer, regsize + 2); if (ret < 0) { @@ -779,7 +768,7 @@ static int isx012_chk_int_state(FAR isx012_dev_t *priv, uint32_t wait_time, uint32_t timeout) { int ret = 0; - volatile uint8_t data; + uint8_t data; uint32_t time = 0; nxsig_usleep(delay_time * 1000); @@ -1393,7 +1382,7 @@ int init_isx012(FAR isx012_dev_t *priv) #endif priv->state = STATE_ISX012_SLEEP; - priv->i2c_freq = I2CFREQ_FAST; + priv->i2c_cfg.frequency = I2CFREQ_FAST; /* initialize the isx012 hardware */ @@ -1441,9 +1430,10 @@ static int isx012_init(FAR struct imgsensor_s *sensor) FAR isx012_dev_t *priv = (FAR isx012_dev_t *)sensor; int ret = 0; - priv->i2c = board_isx012_initialize(); - priv->i2c_addr = ISX012_I2C_SLV_ADDR; - priv->i2c_freq = I2CFREQ_STANDARD; + priv->i2c = board_isx012_initialize(); + priv->i2c_cfg.address = ISX012_I2C_SLV_ADDR; + priv->i2c_cfg.addrlen = 7; + priv->i2c_cfg.frequency = I2CFREQ_STANDARD; ret = board_isx012_power_on(); if (ret < 0) @@ -1486,8 +1476,8 @@ static int isx012_uninit(FAR struct imgsensor_s *sensor) board_isx012_uninitialize(priv->i2c); - priv->i2c_freq = I2CFREQ_STANDARD; - priv->state = STATE_ISX012_POWEROFF; + priv->i2c_cfg.frequency = I2CFREQ_STANDARD; + priv->state = STATE_ISX012_POWEROFF; return ret; } @@ -1764,7 +1754,7 @@ static int isx012_get_supported_value(FAR struct imgsensor_s *sensor, break; case IMGSENSOR_ID_CONTRAST: - value->type = IMGSENSOR_CTRL_TYPE_U8FIXEDPOINT_Q7; + value->type = IMGSENSOR_CTRL_TYPE_INTEGER; range->minimum = ISX012_MIN_CONTRAST; range->maximum = ISX012_MAX_CONTRAST; range->step = ISX012_STEP_CONTRAST; @@ -1808,7 +1798,7 @@ static int isx012_get_supported_value(FAR struct imgsensor_s *sensor, break; case IMGSENSOR_ID_EXPOSURE: - value->type = IMGSENSOR_CTRL_TYPE_INTEGER_TIMES_3; + value->type = IMGSENSOR_CTRL_TYPE_INTEGER; range->minimum = ISX012_MIN_EXPOSURE; range->maximum = ISX012_MAX_EXPOSURE; range->step = ISX012_STEP_EXPOSURE; @@ -1925,7 +1915,7 @@ static int isx012_get_supported_value(FAR struct imgsensor_s *sensor, break; case IMGSENSOR_ID_WIDE_DYNAMIC_RANGE: - value->type = IMGSENSOR_CTRL_TYPE_BOOLEAN; + value->type = IMGSENSOR_CTRL_TYPE_INTEGER; range->minimum = ISX012_MIN_YGAMMA; range->maximum = ISX012_MAX_YGAMMA; range->step = ISX012_STEP_YGAMMA; diff --git a/drivers/video/isx019.c b/drivers/video/isx019.c index fd4796ef05ee1..72c17556771f3 100644 --- a/drivers/video/isx019.c +++ b/drivers/video/isx019.c @@ -99,14 +99,27 @@ /* For set_value() and get_value() I/F */ -#define SET_REGINFO(a, c, o, s) do \ +#define SET_REGINFO(a, c, o, t, s) do \ { \ (a)->category = (c); \ (a)->offset = (o); \ + (a)->type = (t); \ (a)->size = (s); \ } \ while (0); +/* Register type, which represents the number of bits and + * whether it is signed or unsigned. + */ + +#define ISX019_REGTYPE_INT8 (0) +#define ISX019_REGTYPE_UINT8 (1) +#define ISX019_REGTYPE_INT16 (2) + +#define SET_REGINFO_INT8(a, c, o) SET_REGINFO(a, c, o, ISX019_REGTYPE_INT8, 1) +#define SET_REGINFO_UINT8(a, c, o) SET_REGINFO(a, c, o, ISX019_REGTYPE_UINT8, 1) +#define SET_REGINFO_INT16(a, c, o) SET_REGINFO(a, c, o, ISX019_REGTYPE_INT16, 2) + #define VALIDATE_RANGE(v, min, max, step) (((v) >= (min)) && \ ((v) <= (max)) && \ (((v) - (min)) % (step) == 0)) @@ -183,15 +196,12 @@ struct isx019_default_value_s int32_t vflip_still; int32_t sharpness; int32_t ae; - int32_t exptime; int32_t wbmode; int32_t hdr; - int32_t iso; int32_t iso_auto; int32_t meter; int32_t spot_pos; int32_t threealock; - int32_t threeastatus; int32_t jpgquality; }; @@ -213,6 +223,7 @@ struct isx019_dev_s mutex_t fpga_lock; mutex_t i2c_lock; FAR struct i2c_master_s *i2c; + struct i2c_config_s i2c_cfg; float clock_ratio; isx019_default_value_t default_value; imgsensor_stream_type_t stream; @@ -221,9 +232,9 @@ struct isx019_dev_s uint8_t flip_still; isx019_rect_t clip_video; isx019_rect_t clip_still; - int32_t iso; double gamma; int32_t jpg_quality; + int32_t hue; imgsensor_colorfx_t colorfx; }; @@ -240,6 +251,7 @@ struct isx019_reginfo_s { uint16_t category; uint16_t offset; + uint8_t type; uint8_t size; }; @@ -797,6 +809,122 @@ static const int32_t g_isx019_wbmode[] = #define NR_WBMODE (sizeof(g_isx019_wbmode) / sizeof(int32_t)) +static const int32_t g_isx019_iso[] = +{ + 1000, /* ISO1 */ + 1200, /* ISO1.2 */ + 1600, /* ISO1.6 */ + 2000, /* ISO2 */ + 2500, /* ISO2.5 */ + 3000, /* ISO3 */ + 4000, /* ISO4 */ + 5000, /* ISO5 */ + 6000, /* ISO6 */ + 8000, /* ISO8 */ + 10000, /* ISO10 */ + 12000, /* ISO12 */ + 16000, /* ISO16 */ + 20000, /* ISO20 */ + 25000, /* ISO25 */ + 32000, /* ISO32 */ + 40000, /* ISO40 */ + 50000, /* ISO50 */ + 64000, /* ISO64 */ + 80000, /* ISO80 */ + 100000, /* ISO100 */ + 125000, /* ISO125 */ + 160000, /* ISO160 */ + 200000, /* ISO200 */ + 250000, /* ISO250 */ + 320000, /* ISO320 */ + 400000, /* ISO400 */ + 500000, /* ISO500 */ + 640000, /* ISO640 */ + 800000, /* ISO800 */ + 1000000, /* ISO1000 */ + 1250000, /* ISO1250 */ + 1600000, /* ISO1600 */ + 2000000, /* ISO2000 */ + 2500000, /* ISO2500 */ + 3200000, /* ISO3200 */ + 4000000, /* ISO4000 */ + 5000000, /* ISO5000 */ +}; + +#define NR_ISO (sizeof(g_isx019_iso) / sizeof(int32_t)) + +/* Gain values corresponding to each element of g_isx019_iso table. + * This needs to have the same size as g_isx019_iso. + */ + +static const uint8_t g_isx019_gain[] = +{ + 1, /* gain for ISO1 */ + 2, /* gain for ISO1.2 */ + 3, /* gain for ISO1.6 */ + 4, /* gain for ISO2 */ + 5, /* gain for ISO2.5 */ + 6, /* gain for ISO3 */ + 7, /* gain for ISO4 */ + 8, /* gain for ISO5 */ + 9, /* gain for ISO6 */ + 10, /* gain for ISO8 */ + 11, /* gain for ISO10 */ + 12, /* gain for ISO12 */ + 13, /* gain for ISO16 */ + 14, /* gain for ISO20 */ + 15, /* gain for ISO25 */ + 16, /* gain for ISO32 */ + 17, /* gain for ISO40 */ + 18, /* gain for ISO50 */ + 19, /* gain for ISO64 */ + 20, /* gain for ISO80 */ + 21, /* gain for ISO100 */ + 22, /* gain for ISO125 */ + 23, /* gain for ISO160 */ + 24, /* gain for ISO200 */ + 25, /* gain for ISO250 */ + 26, /* gain for ISO320 */ + 27, /* gain for ISO400 */ + 28, /* gain for ISO500 */ + 29, /* gain for ISO640 */ + 30, /* gain for ISO800 */ + 31, /* gain for ISO1000 */ + 32, /* gain for ISO1250 */ + 33, /* gain for ISO1600 */ + 34, /* gain for ISO2000 */ + 35, /* gain for ISO2500 */ + 36, /* gain for ISO3200 */ + 37, /* gain for ISO4000 */ + 38, /* gain for ISO5000 */ +}; + +static const int32_t g_isx019_iso_auto[] = +{ + IMGSENSOR_ISO_SENSITIVITY_MANUAL, + IMGSENSOR_ISO_SENSITIVITY_AUTO, +}; + +#define NR_ISO_AUTO (sizeof(g_isx019_iso_auto) / sizeof(int32_t)) + +static const int32_t g_isx019_metering[] = +{ + IMGSENSOR_EXPOSURE_METERING_AVERAGE, + IMGSENSOR_EXPOSURE_METERING_CENTER_WEIGHTED, + IMGSENSOR_EXPOSURE_METERING_SPOT, + IMGSENSOR_EXPOSURE_METERING_MATRIX, +}; + +#define NR_METERING (sizeof(g_isx019_metering) / sizeof(int32_t)) + +static const int32_t g_isx019_ae[] = +{ + IMGSENSOR_EXPOSURE_AUTO, + IMGSENSOR_EXPOSURE_MANUAL, +}; + +#define NR_AE (sizeof(g_isx019_ae) / sizeof(int32_t)) + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -804,30 +932,18 @@ static const int32_t g_isx019_wbmode[] = static int fpga_i2c_write(FAR isx019_dev_t *priv, uint8_t addr, FAR const void *data, uint8_t size) { - struct i2c_config_s config; static uint8_t buf[FPGA_I2C_REGSIZE_MAX + FPGA_I2C_REGADDR_LEN]; int ret; DEBUGASSERT(size <= FPGA_I2C_REGSIZE_MAX); - config.frequency = ISX019_I2C_FREQUENCY; - config.address = ISX019_I2C_SLVADDR; - config.addrlen = ISX019_I2C_SLVADDR_LEN; + priv->i2c_cfg.address = FPGA_I2C_SLVADDR; nxmutex_lock(&priv->i2c_lock); - - /* ISX019 requires that send read command to ISX019 before FPGA access. */ - - send_read_cmd(priv, &config, CAT_VERSION, ROM_VERSION, 1); - - config.frequency = FPGA_I2C_FREQUENCY; - config.address = FPGA_I2C_SLVADDR; - config.addrlen = FPGA_I2C_SLVADDR_LEN; - buf[FPGA_I2C_OFFSET_ADDR] = addr; memcpy(&buf[FPGA_I2C_OFFSET_WRITEDATA], data, size); ret = i2c_write(priv->i2c, - &config, + &priv->i2c_cfg, buf, size + FPGA_I2C_REGADDR_LEN); nxmutex_unlock(&priv->i2c_lock); @@ -839,31 +955,19 @@ static int fpga_i2c_read(FAR isx019_dev_t *priv, uint8_t addr, FAR void *data, uint8_t size) { int ret; - struct i2c_config_s config; DEBUGASSERT(size <= FPGA_I2C_REGSIZE_MAX); - config.frequency = ISX019_I2C_FREQUENCY; - config.address = ISX019_I2C_SLVADDR; - config.addrlen = ISX019_I2C_SLVADDR_LEN; + priv->i2c_cfg.address = FPGA_I2C_SLVADDR; nxmutex_lock(&priv->i2c_lock); - - /* ISX019 requires that send read command to ISX019 before FPGA access. */ - - send_read_cmd(priv, &config, CAT_VERSION, ROM_VERSION, 1); - - config.frequency = FPGA_I2C_FREQUENCY; - config.address = FPGA_I2C_SLVADDR; - config.addrlen = FPGA_I2C_SLVADDR_LEN; - ret = i2c_write(priv->i2c, - &config, + &priv->i2c_cfg, &addr, FPGA_I2C_REGADDR_LEN); if (ret >= 0) { - ret = i2c_read(priv->i2c, &config, data, size); + ret = i2c_read(priv->i2c, &priv->i2c_cfg, data, size); } nxmutex_unlock(&priv->i2c_lock); @@ -1008,20 +1112,17 @@ static int isx019_i2c_write(FAR isx019_dev_t *priv, uint8_t size) { int ret; - struct i2c_config_s config; DEBUGASSERT(size <= ISX019_I2C_REGSIZE_MAX); - config.frequency = ISX019_I2C_FREQUENCY; - config.address = ISX019_I2C_SLVADDR; - config.addrlen = ISX019_I2C_SLVADDR_LEN; + priv->i2c_cfg.address = ISX019_I2C_SLVADDR; nxmutex_lock(&priv->i2c_lock); - ret = send_write_cmd(priv, &config, cat, addr, data, size); + ret = send_write_cmd(priv, &priv->i2c_cfg, cat, addr, data, size); if (ret == OK) { - ret = recv_write_response(priv, &config); + ret = recv_write_response(priv, &priv->i2c_cfg); } nxmutex_unlock(&priv->i2c_lock); @@ -1065,20 +1166,17 @@ static int isx019_i2c_read(FAR isx019_dev_t *priv, uint8_t size) { int ret; - struct i2c_config_s config; DEBUGASSERT(size <= ISX019_I2C_REGSIZE_MAX); - config.frequency = ISX019_I2C_FREQUENCY; - config.address = ISX019_I2C_SLVADDR; - config.addrlen = ISX019_I2C_SLVADDR_LEN; + priv->i2c_cfg.address = ISX019_I2C_SLVADDR; nxmutex_lock(&priv->i2c_lock); - ret = send_read_cmd(priv, &config, cat, addr, size); + ret = send_read_cmd(priv, &priv->i2c_cfg, cat, addr, size); if (ret == OK) { - ret = recv_read_response(priv, &config, data, size); + ret = recv_read_response(priv, &priv->i2c_cfg, data, size); } nxmutex_unlock(&priv->i2c_lock); @@ -1179,6 +1277,8 @@ static int try_fpga_i2c(FAR isx019_dev_t *priv) static void power_on(FAR isx019_dev_t *priv) { priv->i2c = board_isx019_initialize(); + priv->i2c_cfg.frequency = ISX019_I2C_FREQUENCY; + priv->i2c_cfg.addrlen = ISX019_I2C_SLVADDR_LEN; board_isx019_power_on(); board_isx019_release_reset(); } @@ -1243,15 +1343,12 @@ static void store_default_value(FAR isx019_dev_t *priv) def->vflip_still = get_value32(priv, IMGSENSOR_ID_VFLIP_STILL); def->sharpness = get_value32(priv, IMGSENSOR_ID_SHARPNESS); def->ae = get_value32(priv, IMGSENSOR_ID_EXPOSURE_AUTO); - def->exptime = get_value32(priv, IMGSENSOR_ID_EXPOSURE_ABSOLUTE); def->wbmode = get_value32(priv, IMGSENSOR_ID_AUTO_N_PRESET_WB); def->hdr = get_value32(priv, IMGSENSOR_ID_WIDE_DYNAMIC_RANGE); - def->iso = get_value32(priv, IMGSENSOR_ID_ISO_SENSITIVITY); def->iso_auto = get_value32(priv, IMGSENSOR_ID_ISO_SENSITIVITY_AUTO); def->meter = get_value32(priv, IMGSENSOR_ID_EXPOSURE_METERING); def->spot_pos = get_value32(priv, IMGSENSOR_ID_SPOT_POSITION); def->threealock = get_value32(priv, IMGSENSOR_ID_3A_LOCK); - def->threeastatus = get_value32(priv, IMGSENSOR_ID_3A_STATUS); def->jpgquality = get_value32(priv, IMGSENSOR_ID_JPEG_QUALITY); } @@ -1265,9 +1362,22 @@ static int isx019_init(FAR struct imgsensor_s *sensor) fpga_init(priv); initialize_wbmode(priv); initialize_jpg_quality(priv); - store_default_value(priv); + + /* Set initial gamma value for getting current value API. */ + + priv->gamma = 1000; + + /* Because store_default_value() needs the clock ratio, + * clock_ratio has to be calculated first. + */ + clk = board_isx019_get_master_clock(); priv->clock_ratio = (float)clk / ISX019_STANDARD_MASTER_CLOCK; + store_default_value(priv); + + /* Store initial HUE value for getting current value API. */ + + priv->hue = priv->default_value.hue; return OK; } @@ -1793,7 +1903,7 @@ static int isx019_get_supported_value(FAR struct imgsensor_s *sensor, break; case IMGSENSOR_ID_AUTO_WHITE_BALANCE: - val->type = IMGSENSOR_CTRL_TYPE_INTEGER; + val->type = IMGSENSOR_CTRL_TYPE_BOOLEAN; SET_RANGE(val->u.range, MIN_AWB, MAX_AWB, STEP_AWB, def->awb); break; @@ -1811,25 +1921,25 @@ static int isx019_get_supported_value(FAR struct imgsensor_s *sensor, break; case IMGSENSOR_ID_HFLIP_VIDEO: - val->type = IMGSENSOR_CTRL_TYPE_INTEGER; + val->type = IMGSENSOR_CTRL_TYPE_BOOLEAN; SET_RANGE(val->u.range, MIN_HFLIP, MAX_HFLIP, STEP_HFLIP, def->hflip_video); break; case IMGSENSOR_ID_VFLIP_VIDEO: - val->type = IMGSENSOR_CTRL_TYPE_INTEGER; + val->type = IMGSENSOR_CTRL_TYPE_BOOLEAN; SET_RANGE(val->u.range, MIN_VFLIP, MAX_VFLIP, STEP_VFLIP, def->vflip_video); break; case IMGSENSOR_ID_HFLIP_STILL: - val->type = IMGSENSOR_CTRL_TYPE_INTEGER; + val->type = IMGSENSOR_CTRL_TYPE_BOOLEAN; SET_RANGE(val->u.range, MIN_HFLIP, MAX_HFLIP, STEP_HFLIP, def->hflip_still); break; case IMGSENSOR_ID_VFLIP_STILL: - val->type = IMGSENSOR_CTRL_TYPE_INTEGER; + val->type = IMGSENSOR_CTRL_TYPE_BOOLEAN; SET_RANGE(val->u.range, MIN_VFLIP, MAX_VFLIP, STEP_VFLIP, def->hflip_still); break; @@ -1849,15 +1959,17 @@ static int isx019_get_supported_value(FAR struct imgsensor_s *sensor, break; case IMGSENSOR_ID_EXPOSURE_AUTO: - val->type = IMGSENSOR_CTRL_TYPE_INTEGER; - SET_RANGE(val->u.range, MIN_AE, MAX_AE, - STEP_AE, def->ae); + val->type = IMGSENSOR_CTRL_TYPE_INTEGER_MENU; + SET_DISCRETE(val->u.discrete, + NR_AE, + g_isx019_ae, + IMGSENSOR_EXPOSURE_AUTO); break; case IMGSENSOR_ID_EXPOSURE_ABSOLUTE: val->type = IMGSENSOR_CTRL_TYPE_INTEGER; SET_RANGE(val->u.range, MIN_EXPOSURETIME, MAX_EXPOSURETIME, - STEP_EXPOSURETIME, def->exptime); + STEP_EXPOSURETIME, 0); /* 0 means undefined */ break; case IMGSENSOR_ID_AUTO_N_PRESET_WB: @@ -1875,21 +1987,27 @@ static int isx019_get_supported_value(FAR struct imgsensor_s *sensor, break; case IMGSENSOR_ID_ISO_SENSITIVITY: - val->type = IMGSENSOR_CTRL_TYPE_INTEGER; - SET_RANGE(val->u.range, MIN_ISO, MAX_ISO, - STEP_ISO, def->iso); + val->type = IMGSENSOR_CTRL_TYPE_INTEGER_MENU; + SET_DISCRETE(val->u.discrete, + NR_ISO, + g_isx019_iso, + 0); /* 0 means undefined */ break; case IMGSENSOR_ID_ISO_SENSITIVITY_AUTO: - val->type = IMGSENSOR_CTRL_TYPE_INTEGER; - SET_RANGE(val->u.range, MIN_AUTOISO, MAX_AUTOISO, - STEP_AUTOISO, def->iso_auto); + val->type = IMGSENSOR_CTRL_TYPE_INTEGER_MENU; + SET_DISCRETE(val->u.discrete, + NR_ISO_AUTO, + g_isx019_iso_auto, + IMGSENSOR_ISO_SENSITIVITY_AUTO); break; case IMGSENSOR_ID_EXPOSURE_METERING: - val->type = IMGSENSOR_CTRL_TYPE_INTEGER; - SET_RANGE(val->u.range, MIN_METER, MAX_METER, - STEP_METER, def->meter); + val->type = IMGSENSOR_CTRL_TYPE_INTEGER_MENU; + SET_DISCRETE(val->u.discrete, + NR_METERING, + g_isx019_metering, + IMGSENSOR_EXPOSURE_METERING_AVERAGE); break; case IMGSENSOR_ID_SPOT_POSITION: @@ -1912,8 +2030,10 @@ static int isx019_get_supported_value(FAR struct imgsensor_s *sensor, case IMGSENSOR_ID_3A_STATUS: val->type = IMGSENSOR_CTRL_TYPE_INTEGER; - SET_RANGE(val->u.range, MIN_3ASTATUS, MAX_3ASTATUS, - STEP_3ASTATUS, def->threeastatus); + SET_RANGE(val->u.range, MIN_3ASTATUS, + MAX_3ASTATUS, STEP_3ASTATUS, + IMGSENSOR_3A_STATUS_AE_OPERATING + | IMGSENSOR_3A_STATUS_AWB_OPERATING); break; case IMGSENSOR_ID_JPEG_QUALITY: @@ -1944,22 +2064,12 @@ static int32_t not_convert(int32_t val) static int32_t convert_brightness_is2reg(int32_t val) { - return (val << 2); + return (val * 4); } static int32_t convert_brightness_reg2is(int32_t val) { - return (val >> 2); -} - -static int32_t convert_hue_is2reg(int32_t val) -{ - return (val * 90) / 128; -} - -static int32_t convert_hue_reg2is(int32_t val) -{ - return (val * 128) / 90; + return (val / 4); } static int32_t convert_hdr_is2reg(int32_t val) @@ -2023,38 +2133,33 @@ static convert_t get_reginfo(uint32_t id, bool is_set, switch (id) { case IMGSENSOR_ID_BRIGHTNESS: - SET_REGINFO(reg, CAT_PICTTUNE, UIBRIGHTNESS, 2); + SET_REGINFO_INT16(reg, CAT_PICTTUNE, UIBRIGHTNESS); cvrt = is_set ? convert_brightness_is2reg : convert_brightness_reg2is; break; case IMGSENSOR_ID_CONTRAST: - SET_REGINFO(reg, CAT_PICTTUNE, UICONTRAST, 1); + SET_REGINFO_UINT8(reg, CAT_PICTTUNE, UICONTRAST); cvrt = not_convert; break; case IMGSENSOR_ID_SATURATION: - SET_REGINFO(reg, CAT_PICTTUNE, UISATURATION, 1); + SET_REGINFO_UINT8(reg, CAT_PICTTUNE, UISATURATION); cvrt = not_convert; break; - case IMGSENSOR_ID_HUE: - SET_REGINFO(reg, CAT_PICTTUNE, UIHUE, 1); - cvrt = is_set ? convert_hue_is2reg : convert_hue_reg2is; - break; - case IMGSENSOR_ID_EXPOSURE: - SET_REGINFO(reg, CAT_AEDGRM, EVSEL, 1); + SET_REGINFO_INT8(reg, CAT_AEDGRM, EVSEL); cvrt = not_convert; break; case IMGSENSOR_ID_SHARPNESS: - SET_REGINFO(reg, CAT_PICTTUNE, UISHARPNESS, 1); + SET_REGINFO_UINT8(reg, CAT_PICTTUNE, UISHARPNESS); cvrt = not_convert; break; case IMGSENSOR_ID_WIDE_DYNAMIC_RANGE: - SET_REGINFO(reg, CAT_AEWD, AEWDMODE, 1); + SET_REGINFO_UINT8(reg, CAT_AEWD, AEWDMODE); cvrt = is_set ? convert_hdr_is2reg : convert_hdr_reg2is; break; @@ -2065,6 +2170,23 @@ static convert_t get_reginfo(uint32_t id, bool is_set, return cvrt; } +static int set_hue(FAR isx019_dev_t *priv, + imgsensor_value_t val) +{ + int ret; + int val32 = val.value32 * 90 / 128; + + ret = isx019_i2c_write(priv, CAT_PICTTUNE, UIHUE, &val32, 1); + if (ret == OK) + { + /* Store value before conversion for get_hue(). */ + + priv->hue = val.value32; + } + + return ret; +} + static void set_flip(FAR uint8_t *flip, uint8_t direction, int32_t val) { DEBUGASSERT(flip); @@ -2578,18 +2700,21 @@ static int set_3aparameter(FAR isx019_dev_t *priv, return OK; } -static uint16_t calc_gain(double iso) +static uint16_t get_gain_from_iso(int32_t iso) { - double gain; + int i; - gain = 1 + 10 * log(iso) / M_LN10; + for (i = 0; i < NR_ISO; i++) + { + if (g_isx019_iso[i] == iso) + { + break; + } + } - /* In the above formula, the unit of gain is dB. - * Because the register has the 0.1dB unit, - * return 10 times dB value. - */ + /* Return gain corresponding to specified ISO sensitivity. */ - return (uint16_t)(gain * 10); + return (uint16_t)g_isx019_gain[i]; } static int set_iso(FAR isx019_dev_t *priv, @@ -2601,10 +2726,9 @@ static int set_iso(FAR isx019_dev_t *priv, * So, calculate gain from ISO sensitivity. */ - gain = calc_gain(val.value32 / 1000); + gain = get_gain_from_iso(val.value32) * 10; isx019_i2c_write(priv, CAT_CATAE, GAIN_PRIMODE, &gain, 2); - priv->iso = val.value32; return OK; } @@ -2617,7 +2741,6 @@ static int set_iso_auto(FAR isx019_dev_t *priv, if (val.value32 == IMGSENSOR_ISO_SENSITIVITY_AUTO) { gain = 0; - priv->iso = 0; } else /* IMGSENSOR_ISO_SENSITIVITY_MANUAL */ { @@ -2635,8 +2758,6 @@ static int set_iso_auto(FAR isx019_dev_t *priv, isx019_i2c_read(priv, CAT_AECOM, GAIN_LEVEL, &buf, 1); gain = buf * 3; } - - priv->iso = val.value32; } return isx019_i2c_write(priv, CAT_CATAE, GAIN_PRIMODE, &gain, 2); @@ -2893,6 +3014,10 @@ static setvalue_t set_value_func(uint32_t id) switch (id) { + case IMGSENSOR_ID_HUE: + func = set_hue; + break; + case IMGSENSOR_ID_GAMMA: func = set_gamma; break; @@ -2976,6 +3101,21 @@ static setvalue_t set_value_func(uint32_t id) return func; } +static int get_hue(FAR isx019_dev_t *priv, + FAR imgsensor_value_t *val) +{ + if (val == NULL) + { + return -EINVAL; + } + + /* Return stored value without reading register. */ + + val->value32 = priv->hue; + + return OK; +} + static int32_t get_flip(FAR uint8_t *flip, uint8_t direction) { DEBUGASSERT(flip); @@ -3293,56 +3433,46 @@ static int get_3astatus(FAR isx019_dev_t *priv, return OK; } -static double calc_iso(double gain) +static int32_t get_iso_from_gain(uint8_t gain) { - int k; - double z; - double r; - - /* ISO sensitivity = 10^((gain - 1) / 10) - * So, replace z = (gain - 1) / 10 and - * calculate 10^z. - */ + int i; - /* Divide z into integer and other parts. - * z = log10(E) (k * ln2 + r) - * (k : integer, r < 0.5 * ln2) - * - * Then, 10^z = (2^k) * e^r (r < 0.5 * ln2) - */ + /* g_isx019_gain and g_isx019_iso has the common index. */ - z = (gain - 1) / 10; + for (i = 0; i < NR_ISO; i++) + { + if (g_isx019_gain[i] == gain) + { + break; + } + } - k = z * M_LN10 / M_LN2; - r = z * M_LN10 - k * M_LN2; + if (i >= NR_ISO) + { + i = NR_ISO - 1; + } - return (1 << k) * exp(r); + return g_isx019_iso[i]; } static int get_iso(FAR isx019_dev_t *priv, FAR imgsensor_value_t *val) { - uint8_t buf = 0; + uint8_t gain = 0; if (val == NULL) { return -EINVAL; } - if (priv->iso == 0) - { - /* iso = 0 means auto adjustment mode. - * In such a case, get gain from auto adjustment value register, - * which has the unit 0.3dB, and convert the gain to ISO. - */ + /* The current gain value register has the 0.3dB unit. + * So, round the gain to integer, and convert to ISO. + */ - isx019_i2c_read(priv, CAT_AECOM, GAIN_LEVEL, &buf, 1); - val->value32 = calc_iso((double)buf * 0.3) * USEC_PER_MSEC; - } - else - { - val->value32 = priv->iso; - } + isx019_i2c_read(priv, CAT_AECOM, GAIN_LEVEL, &gain, 1); + gain = ((gain * 3) + 5) / 10; + + val->value32 = get_iso_from_gain(gain); return OK; } @@ -3395,6 +3525,10 @@ static getvalue_t get_value_func(uint32_t id) switch (id) { + case IMGSENSOR_ID_HUE: + func = get_hue; + break; + case IMGSENSOR_ID_GAMMA: func = get_gamma; break; @@ -3483,16 +3617,37 @@ static int isx019_get_value(FAR struct imgsensor_s *sensor, isx019_reginfo_t reg; convert_t cvrt; getvalue_t get; - int32_t val32; + union + { + int32_t i32; + int16_t i16; + int8_t i8; + } regval; DEBUGASSERT(val); cvrt = get_reginfo(id, false, ®); if (cvrt) { + memset(®val, 0, sizeof(regval)); ret = isx019_i2c_read(priv, - reg.category, reg.offset, &val32, reg.size); - val->value32 = cvrt(val32); + reg.category, reg.offset, ®val.i32, reg.size); + + switch (reg.type) + { + case ISX019_REGTYPE_INT8: + regval.i32 = (int32_t)regval.i8; + break; + + case ISX019_REGTYPE_INT16: + regval.i32 = (int32_t)regval.i16; + break; + + default: + break; + } + + val->value32 = cvrt(regval.i32); } else { diff --git a/drivers/video/isx019_range.h b/drivers/video/isx019_range.h index 35365a148e771..9489c1fc12db4 100644 --- a/drivers/video/isx019_range.h +++ b/drivers/video/isx019_range.h @@ -77,7 +77,7 @@ #define STEP_AE (1) #define MIN_EXPOSURETIME (1) -#define MAX_EXPOSURETIME (102000) +#define MAX_EXPOSURETIME (2740) #define STEP_EXPOSURETIME (1) #define MIN_WBMODE (0) diff --git a/drivers/video/mipidsi/mipi_dsi_device.c b/drivers/video/mipidsi/mipi_dsi_device.c index 10b8db4b05185..2cf6aca456ee3 100644 --- a/drivers/video/mipidsi/mipi_dsi_device.c +++ b/drivers/video/mipidsi/mipi_dsi_device.c @@ -1031,7 +1031,7 @@ mipi_dsi_device_register(FAR struct mipi_dsi_host *host, kmm_free(dev); dev = NULL; } -#endif // CONFIG_MIPI_DSI_DRIVER +#endif /* CONFIG_MIPI_DSI_DRIVER */ } return dev; diff --git a/drivers/video/v4l2_cap.c b/drivers/video/v4l2_cap.c new file mode 100644 index 0000000000000..2e24d0ecaf7b7 --- /dev/null +++ b/drivers/video/v4l2_cap.c @@ -0,0 +1,3820 @@ +/**************************************************************************** + * drivers/video/v4l2_cap.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "video_framebuff.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MAX_CAPTURE_FMT (2) +#define CAPTURE_FMT_MAIN (0) +#define CAPTURE_FMT_SUB (1) + +#define REMAINING_CAPNUM_INFINITY (-1) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +enum capture_state_e +{ + CAPTURE_STATE_STREAMOFF = 0, /* Capture trigger event is not received */ + CAPTURE_STATE_STREAMON = 1, /* Capture trigger event is received, + * but capture is not operated. + */ + CAPTURE_STATE_CAPTURE = 2, /* On capture */ +}; + +enum capture_state_cause_e +{ + CAUSE_CAPTURE_STOP = 0, /* Stop capture event for capture stream */ + CAUSE_CAPTURE_START = 1, /* Start capture event for capture stream */ + CAUSE_CAPTURE_DQBUF = 2, /* DQBUF timing for video stream */ + CAUSE_STILL_STOP = 3, /* Stop capture event for still stream */ + CAUSE_STILL_START = 4, /* Start capture event for still stream */ +}; + +enum capture_waitend_cause_e +{ + WAITEND_CAUSE_CAPTUREDONE = 0, + WAITEND_CAUSE_DQCANCEL = 1, + WAITEND_CAUSE_STILLSTOP = 2, +}; + +struct video_format_s +{ + uint16_t width; + uint16_t height; + uint32_t pixelformat; +}; + +typedef struct video_format_s video_format_t; + +struct capture_wait_capture_s +{ + sem_t dqbuf_wait_flg; + + /* Save container which capture is done */ + + FAR vbuf_container_t *done_container; + enum capture_waitend_cause_e waitend_cause; +}; + +typedef struct capture_wait_capture_s capture_wait_capture_t; + +struct capture_type_inf_s +{ + mutex_t lock_state; + enum capture_state_e state; + int32_t remaining_capnum; + capture_wait_capture_t wait_capture; + uint8_t nr_fmt; + video_format_t fmt[MAX_CAPTURE_FMT]; + struct v4l2_rect clip; + struct v4l2_fract frame_interval; + video_framebuff_t bufinf; + FAR uint8_t *bufheap; /* for V4L2_MEMORY_MMAP buffers */ + FAR struct pollfd *fds; + uint32_t seqnum; +}; + +typedef struct capture_type_inf_s capture_type_inf_t; + +struct capture_scene_params_s +{ + uint8_t mode; /* enum v4l2_scene_mode */ + + int32_t brightness; + int32_t contrast; + int32_t saturation; + int32_t hue; + bool awb; + int32_t red; + int32_t blue; + int32_t gamma; + uint32_t gamma_curve_sz; + uint8_t *gamma_curve; + int32_t ev; + bool hflip_video; + bool vflip_video; + bool hflip_still; + bool vflip_still; + int32_t sharpness; + enum v4l2_colorfx colorfx; + bool auto_brightness; + int32_t rotate; + enum v4l2_exposure_auto_type ae; + int32_t exposure_time; + int32_t focus; + bool af; + int32_t zoom; + int32_t iris; + enum v4l2_auto_n_preset_white_balance wb; + int32_t wdr; + bool stabilization; + enum v4l2_iso_sensitivity_auto_type iso_auto; + int32_t iso; + enum v4l2_exposure_metering meter; + int32_t spot_pos; + int32_t threea_lock; + enum v4l2_flash_led_mode led; + int32_t jpeg_quality; +}; + +typedef struct capture_scene_params_s capture_scene_params_t; + +struct capture_parameter_name_s +{ + uint32_t id; + const char *name; +}; + +typedef struct capture_parameter_name_s capture_parameter_name_t; + +struct capture_mng_s +{ + struct v4l2_s v4l2; + + /* Parameter of capture_initialize() */ + + mutex_t lock_open_num; + uint8_t open_num; + capture_type_inf_t capture_inf; + capture_type_inf_t still_inf; + FAR struct imgdata_s *imgdata; + FAR struct imgsensor_s *imgsensor; + enum v4l2_scene_mode capture_scene_mode; + uint8_t capture_scence_num; + FAR capture_scene_params_t *capture_scene_param[V4L2_SCENE_MODE_MAX]; +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + bool unlinked; +#endif +}; + +typedef struct capture_mng_s capture_mng_t; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static FAR capture_type_inf_t * +get_capture_type_inf(FAR capture_mng_t *cmng, uint8_t type); +static enum capture_state_e +estimate_next_capture_state(FAR capture_mng_t *cmng, + enum capture_state_cause_e cause); +static void change_capture_state(FAR capture_mng_t *cmng, + enum capture_state_e next_state); +static bool is_taking_still_picture(FAR capture_mng_t *cmng); +static bool is_bufsize_sufficient(FAR capture_mng_t *cmng, uint32_t bufsize); +static void cleanup_resources(FAR capture_mng_t *cmng); +static bool is_sem_waited(FAR sem_t *sem); +static int save_scene_param(FAR capture_mng_t *cmng, + enum v4l2_scene_mode mode, + uint32_t id, + FAR struct v4l2_ext_control *control); +static int complete_capture(uint8_t err_code, uint32_t datasize, + FAR const struct timeval *ts, + FAR void *arg); +static int validate_frame_setting(FAR capture_mng_t *cmng, + enum v4l2_buf_type type, + uint8_t nr_fmt, + FAR video_format_t *vfmt, + FAR struct v4l2_rect *clip, + FAR struct v4l2_fract *interval); +static size_t get_bufsize(FAR video_format_t *vf); + +/* ioctl function for each cmds of ioctl */ + +static int capture_querycap(FAR struct file *filep, + FAR struct v4l2_capability *cap); +static int capture_g_input(FAR int *num); +static int capture_enum_input(FAR struct file *filep, + FAR struct v4l2_input *input); +static int capture_reqbufs(FAR struct file *filep, + FAR struct v4l2_requestbuffers *reqbufs); +static int capture_querybuf(FAR struct file *filep, + FAR struct v4l2_buffer *buf); +static int capture_qbuf(FAR struct file *filep, + FAR struct v4l2_buffer *buf); +static int capture_dqbuf(FAR struct file *filep, + FAR struct v4l2_buffer *buf); +static int capture_cancel_dqbuf(FAR struct file *filep, + enum v4l2_buf_type type); +static int capture_g_fmt(FAR struct file *filep, + FAR struct v4l2_format *fmt); +static int capture_s_fmt(FAR struct file *filep, + FAR struct v4l2_format *fmt); +static int capture_try_fmt(FAR struct file *filep, + FAR struct v4l2_format *fmt); +static int capture_g_parm(FAR struct file *filep, + FAR struct v4l2_streamparm *parm); +static int capture_s_parm(FAR struct file *filep, + FAR struct v4l2_streamparm *parm); +static int capture_streamon(FAR struct file *filep, + FAR enum v4l2_buf_type *type); +static int capture_streamoff(FAR struct file *filep, + FAR enum v4l2_buf_type *type); +static int capture_do_halfpush(FAR struct file *filep, + bool enable); +static int capture_takepict_start(FAR struct file *filep, + int32_t capture_num); +static int capture_takepict_stop(FAR struct file *filep, + bool halfpush); +static int capture_s_selection(FAR struct file *filep, + FAR struct v4l2_selection *clip); +static int capture_g_selection(FAR struct file *filep, + FAR struct v4l2_selection *clip); +static int capture_queryctrl(FAR struct file *filep, + FAR struct v4l2_queryctrl *ctrl); +static int capture_query_ext_ctrl(FAR struct file *filep, + FAR struct v4l2_query_ext_ctrl *ctrl); +static int capture_querymenu(FAR struct file *filep, + FAR struct v4l2_querymenu *menu); +static int capture_g_ctrl(FAR struct file *filep, + FAR struct v4l2_control *ctrl); +static int capture_s_ctrl(FAR struct file *filep, + FAR struct v4l2_control *ctrl); +static int capture_g_ext_ctrls(FAR struct file *filep, + FAR struct v4l2_ext_controls *ctrls); +static int capture_s_ext_ctrls(FAR struct file *filep, + FAR struct v4l2_ext_controls *ctrls); +static int capture_query_ext_ctrl_scene(FAR struct file *filep, + FAR struct v4s_query_ext_ctrl_scene *ctrl); +static int capture_querymenu_scene(FAR struct file *filep, + FAR struct v4s_querymenu_scene *menu); +static int capture_g_ext_ctrls_scene(FAR struct file *filep, + FAR struct v4s_ext_controls_scene *ctrls); +static int capture_s_ext_ctrls_scene(FAR struct file *filep, + FAR struct v4s_ext_controls_scene *ctrls); +static int capture_enum_fmt(FAR struct file *filep, + FAR struct v4l2_fmtdesc *f); +static int capture_enum_frminterval(FAR struct file *filep, + FAR struct v4l2_frmivalenum *f); +static int capture_enum_frmsize(FAR struct file *filep, + FAR struct v4l2_frmsizeenum *f); + +/* File operations function */ + +static int capture_open(FAR struct file *filep); +static int capture_close(FAR struct file *filep); +static int capture_mmap(FAR struct file *filep, + FAR struct mm_map_entry_s *map); +static int capture_poll(FAR struct file *filep, + FAR struct pollfd *fds, bool setup); +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS +static int capture_unlink(FAR struct inode *inode); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct v4l2_ops_s g_capture_vops = +{ + capture_querycap, /* querycap */ + capture_g_input, /* g_input */ + capture_enum_input, /* enum_input */ + capture_reqbufs, /* reqbufs */ + capture_querybuf, /* querybuf */ + capture_qbuf, /* qbuf */ + capture_dqbuf, /* dqbuf */ + capture_cancel_dqbuf, /* cancel_dqbuf */ + capture_g_fmt, /* g_fmt */ + capture_s_fmt, /* s_fmt */ + capture_try_fmt, /* try_fmt */ + capture_g_parm, /* g_parm */ + capture_s_parm, /* s_parm */ + capture_streamon, /* streamon */ + capture_streamoff, /* streamoff */ + capture_do_halfpush, /* do_halfpush */ + capture_takepict_start, /* takepict_start */ + capture_takepict_stop, /* takepict_stop */ + capture_s_selection, /* s_selection */ + capture_g_selection, /* g_selection */ + capture_queryctrl, /* queryctrl */ + capture_query_ext_ctrl, /* query_ext_ctrl */ + capture_querymenu, /* querymenu */ + capture_g_ctrl, /* g_ctrl */ + capture_s_ctrl, /* s_ctrl */ + capture_g_ext_ctrls, /* g_ext_ctrls */ + capture_s_ext_ctrls, /* s_ext_ctrls */ + capture_query_ext_ctrl_scene, /* query_ext_ctrl_scene */ + capture_querymenu_scene, /* querymenu_scene */ + capture_g_ext_ctrls_scene, /* g_ext_ctrls_scene */ + capture_s_ext_ctrls_scene, /* s_ext_ctrls_scene */ + capture_enum_fmt, /* enum_fmt */ + capture_enum_frminterval, /* enum_frminterval */ + capture_enum_frmsize /* enum_frmsize */ +}; + +static const struct file_operations g_capture_fops = +{ + capture_open, /* open */ + capture_close, /* close */ + NULL, /* read */ + NULL, /* write */ + NULL, /* seek */ + NULL, /* ioctl */ + capture_mmap, /* mmap */ + NULL, /* truncate */ + capture_poll, /* poll */ +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + capture_unlink, /* unlink */ +#endif +}; + +static const capture_parameter_name_t g_capture_parameter_name[] = +{ + { + IMGSENSOR_ID_BRIGHTNESS, "Brightness" + }, + + { + IMGSENSOR_ID_CONTRAST, "Contrast" + }, + + { + IMGSENSOR_ID_SATURATION, "Saturation" + }, + + { + IMGSENSOR_ID_HUE, "Hue" + }, + + { + IMGSENSOR_ID_AUTO_WHITE_BALANCE, "Automatic white balance" + }, + + { + IMGSENSOR_ID_RED_BALANCE, "Red balance" + }, + + { + IMGSENSOR_ID_BLUE_BALANCE, "Blue balance" + }, + + { + IMGSENSOR_ID_GAMMA, "Gamma value" + }, + + { + IMGSENSOR_ID_GAMMA_CURVE, "Gamma adjustment(curve)" + }, + + { + IMGSENSOR_ID_EXPOSURE, "Exposure value" + }, + + { + IMGSENSOR_ID_HFLIP_VIDEO, "Mirror horizontally(VIDEO)" + }, + + { + IMGSENSOR_ID_VFLIP_VIDEO, "Mirror vertically(VIDEO)" + }, + + { + IMGSENSOR_ID_HFLIP_STILL, "Mirror horizontally(STILL)" + }, + + { + IMGSENSOR_ID_VFLIP_STILL, "Mirror vertically(STILL)" + }, + + { + IMGSENSOR_ID_SHARPNESS, "Sharpness" + }, + + { + IMGSENSOR_ID_COLOR_KILLER, "Color killer" + }, + + { + IMGSENSOR_ID_COLORFX, "Color effect" + }, + + { + IMGSENSOR_ID_AUTOBRIGHTNESS, "Auto brightness" + }, + + { + IMGSENSOR_ID_ROTATE, "Rotate" + }, + + { + IMGSENSOR_ID_EXPOSURE_AUTO, "Auto Exposure" + }, + + { + IMGSENSOR_ID_EXPOSURE_ABSOLUTE, "Exposure time(100 usec)" + }, + + { + IMGSENSOR_ID_FOCUS_ABSOLUTE, "Focus(absolute value)" + }, + + { + IMGSENSOR_ID_FOCUS_RELATIVE, "Focus(relative value)" + }, + + { + IMGSENSOR_ID_FOCUS_AUTO, "Continuous Auto Focus" + }, + + { + IMGSENSOR_ID_ZOOM_ABSOLUTE, "Zoom(absolute value)" + }, + + { + IMGSENSOR_ID_ZOOM_RELATIVE, "Zoom(relative value)" + }, + + { + IMGSENSOR_ID_ZOOM_CONTINUOUS, "Continuous zoom" + }, + + { + IMGSENSOR_ID_IRIS_ABSOLUTE, "Iris(absolute value)" + }, + + { + IMGSENSOR_ID_IRIS_RELATIVE, "Iris(relative value)" + }, + + { + IMGSENSOR_ID_AUTO_N_PRESET_WB, "Preset white balance" + }, + + { + IMGSENSOR_ID_WIDE_DYNAMIC_RANGE, "Wide dynamic range" + }, + + { + IMGSENSOR_ID_IMG_STABILIZATION, "Image stabilization" + }, + + { + IMGSENSOR_ID_ISO_SENSITIVITY, "ISO sensitivity" + }, + + { + IMGSENSOR_ID_ISO_SENSITIVITY_AUTO, "Automatic ISO sensitivity" + }, + + { + IMGSENSOR_ID_EXPOSURE_METERING, "Photometry" + }, + + { + IMGSENSOR_ID_SPOT_POSITION, "Spot position" + }, + + { + IMGSENSOR_ID_3A_LOCK, "Lock AWB/AE" + }, + + { + IMGSENSOR_ID_AUTO_FOCUS_START, "Start single Auto Focus" + }, + + { + IMGSENSOR_ID_AUTO_FOCUS_STOP, "Stop single Auto Focus" + }, + + { + IMGSENSOR_ID_3A_PARAMETER, "3A parameter" + }, + + { + IMGSENSOR_ID_3A_STATUS, "3A status" + }, + + { + IMGSENSOR_ID_FLASH_LED_MODE, "LED mode" + }, + + { + IMGSENSOR_ID_JPEG_QUALITY, "JPEG compression quality" + } +}; + +static FAR struct imgsensor_s **g_capture_registered_sensor = NULL; +static size_t g_capture_registered_sensor_num; +static FAR struct imgdata_s *g_capture_data = NULL; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static FAR capture_type_inf_t * +get_capture_type_inf(FAR capture_mng_t *cmng, uint8_t type) +{ + FAR capture_type_inf_t *type_inf; + + switch (type) + { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + type_inf = &cmng->capture_inf; + break; + + case V4L2_BUF_TYPE_STILL_CAPTURE: + type_inf = &cmng->still_inf; + break; + + default: /* Error case */ + type_inf = NULL; + break; + } + + return type_inf; +} + +static enum capture_state_e +estimate_next_capture_state(FAR capture_mng_t *cmng, + enum capture_state_cause_e cause) +{ + enum capture_state_e current_state = cmng->capture_inf.state; + + switch (cause) + { + case CAUSE_CAPTURE_STOP: + return CAPTURE_STATE_STREAMOFF; + + case CAUSE_CAPTURE_START: + if (is_taking_still_picture(cmng)) + { + return CAPTURE_STATE_STREAMON; + } + else + { + return CAPTURE_STATE_CAPTURE; + } + + case CAUSE_STILL_STOP: + if (current_state == CAPTURE_STATE_STREAMON) + { + return CAPTURE_STATE_CAPTURE; + } + else + { + return current_state; + } + + case CAUSE_STILL_START: + if (current_state == CAPTURE_STATE_CAPTURE) + { + return CAPTURE_STATE_STREAMON; + } + else + { + return current_state; + } + + case CAUSE_CAPTURE_DQBUF: + if (current_state == CAPTURE_STATE_STREAMON && + !is_taking_still_picture(cmng)) + { + return CAPTURE_STATE_CAPTURE; + } + else + { + return current_state; + } + + default: + return current_state; + } +} + +static void convert_to_imgdatafmt(FAR video_format_t *video, + FAR imgdata_format_t *data) +{ + ASSERT(video && data); + + data->width = video->width; + data->height = video->height; + switch (video->pixelformat) + { + case V4L2_PIX_FMT_NV12: + data->pixelformat = IMGDATA_PIX_FMT_NV12; + break; + + case V4L2_PIX_FMT_YUV420: + data->pixelformat = IMGDATA_PIX_FMT_YUV420P; + break; + + case V4L2_PIX_FMT_YUYV: + data->pixelformat = IMGDATA_PIX_FMT_YUYV; + break; + + case V4L2_PIX_FMT_UYVY: + data->pixelformat = IMGDATA_PIX_FMT_UYVY; + break; + + case V4L2_PIX_FMT_RGB565: + data->pixelformat = IMGDATA_PIX_FMT_RGB565; + break; + + case V4L2_PIX_FMT_JPEG: + data->pixelformat = IMGDATA_PIX_FMT_JPEG; + break; + + default: /* V4L2_PIX_FMT_JPEG_WITH_SUBIMG */ + data->pixelformat = IMGDATA_PIX_FMT_JPEG_WITH_SUBIMG; + break; + } +} + +static void convert_to_imgsensorfmt(FAR video_format_t *video, + FAR imgsensor_format_t *sensor) +{ + ASSERT(video && sensor); + + sensor->width = video->width; + sensor->height = video->height; + switch (video->pixelformat) + { + case V4L2_PIX_FMT_NV12: + sensor->pixelformat = IMGSENSOR_PIX_FMT_NV12; + break; + + case V4L2_PIX_FMT_YUV420: + sensor->pixelformat = IMGSENSOR_PIX_FMT_YUV420P; + break; + + case V4L2_PIX_FMT_YUYV: + sensor->pixelformat = IMGSENSOR_PIX_FMT_YUYV; + break; + + case V4L2_PIX_FMT_UYVY: + sensor->pixelformat = IMGSENSOR_PIX_FMT_UYVY; + break; + + case V4L2_PIX_FMT_RGB565: + sensor->pixelformat = IMGSENSOR_PIX_FMT_RGB565; + break; + + case V4L2_PIX_FMT_JPEG: + sensor->pixelformat = IMGSENSOR_PIX_FMT_JPEG; + break; + + default: /* V4L2_PIX_FMT_JPEG_WITH_SUBIMG */ + sensor->pixelformat = IMGSENSOR_PIX_FMT_JPEG_WITH_SUBIMG; + break; + } +} + +static void convert_to_imgdatainterval(FAR struct v4l2_fract *video, + FAR imgdata_interval_t *data) +{ + ASSERT(video && data); + + data->numerator = video->numerator; + data->denominator = video->denominator; +} + +static void convert_to_imgsensorinterval(FAR struct v4l2_fract *video, + FAR imgsensor_interval_t *sensor) +{ + ASSERT(video && sensor); + + sensor->numerator = video->numerator; + sensor->denominator = video->denominator; +} + +static bool is_clipped(FAR struct v4l2_rect *clip) +{ + bool ret = false; + + if (clip) + { + if (clip->left != 0 || clip->top != 0 || + clip->width != 0 || clip->height != 0) + { + ret = true; + } + } + + return ret; +} + +static void get_clipped_format(uint8_t nr_fmt, + FAR video_format_t *fmt, + FAR struct v4l2_rect *clip, + FAR video_format_t *c_fmt) +{ + DEBUGASSERT(fmt && c_fmt); + + if (is_clipped(clip)) + { + c_fmt[CAPTURE_FMT_MAIN].width = clip->width; + c_fmt[CAPTURE_FMT_MAIN].height = clip->height; + c_fmt[CAPTURE_FMT_MAIN].pixelformat = + fmt[CAPTURE_FMT_MAIN].pixelformat; + + if (nr_fmt > 1) + { + /* Clipped size of thumbnail is + * small as ratio of main size and thumbnail size. + */ + + memcpy(&c_fmt[CAPTURE_FMT_SUB], + &fmt[CAPTURE_FMT_SUB], + sizeof(video_format_t)); + + c_fmt[CAPTURE_FMT_SUB].width = + (uint32_t)c_fmt[CAPTURE_FMT_SUB].width * + clip->width / fmt[CAPTURE_FMT_MAIN].width; + + c_fmt[CAPTURE_FMT_SUB].height = + (uint32_t)c_fmt[CAPTURE_FMT_SUB].height * + clip->height / fmt[CAPTURE_FMT_MAIN].height; + } + } + else + { + memcpy(c_fmt, fmt, nr_fmt * sizeof(video_format_t)); + } +} + +static int start_capture(FAR struct capture_mng_s *cmng, + enum v4l2_buf_type type, + uint8_t nr_fmt, + FAR video_format_t *fmt, + FAR struct v4l2_rect *clip, + FAR struct v4l2_fract *interval, + uintptr_t bufaddr, uint32_t bufsize) +{ + video_format_t c_fmt[MAX_CAPTURE_FMT]; + imgdata_format_t df[MAX_CAPTURE_FMT]; + imgsensor_format_t sf[MAX_CAPTURE_FMT]; + imgdata_interval_t di; + imgsensor_interval_t si; + + ASSERT(fmt && interval && cmng->imgsensor && cmng->imgdata); + + get_clipped_format(nr_fmt, fmt, clip, c_fmt); + + convert_to_imgdatafmt(&c_fmt[CAPTURE_FMT_MAIN], &df[IMGDATA_FMT_MAIN]); + convert_to_imgdatafmt(&c_fmt[CAPTURE_FMT_SUB], &df[IMGDATA_FMT_SUB]); + convert_to_imgdatainterval(interval, &di); + convert_to_imgsensorfmt(&fmt[CAPTURE_FMT_MAIN], &sf[IMGSENSOR_FMT_MAIN]); + convert_to_imgsensorfmt(&fmt[CAPTURE_FMT_SUB], &sf[IMGSENSOR_FMT_SUB]); + convert_to_imgsensorinterval(interval, &si); + + IMGDATA_SET_BUF(cmng->imgdata, + nr_fmt, df, (FAR uint8_t *)bufaddr, bufsize); + IMGDATA_START_CAPTURE(cmng->imgdata, + nr_fmt, df, &di, complete_capture, cmng); + IMGSENSOR_START_CAPTURE(cmng->imgsensor, + type == V4L2_BUF_TYPE_VIDEO_CAPTURE ? + IMGSENSOR_STREAM_TYPE_VIDEO : IMGSENSOR_STREAM_TYPE_STILL, + nr_fmt, sf, &si); + return OK; +} + +static void stop_capture(FAR struct capture_mng_s *cmng, + enum v4l2_buf_type type) +{ + ASSERT(cmng->imgsensor && cmng->imgdata); + + IMGDATA_STOP_CAPTURE(cmng->imgdata); + IMGSENSOR_STOP_CAPTURE(cmng->imgsensor, + type == V4L2_BUF_TYPE_VIDEO_CAPTURE ? + IMGSENSOR_STREAM_TYPE_VIDEO : IMGSENSOR_STREAM_TYPE_STILL); +} + +static void change_capture_state(FAR capture_mng_t *cmng, + enum capture_state_e next_state) +{ + enum capture_state_e current_state = cmng->capture_inf.state; + enum capture_state_e updated_next_state = next_state; + + if (current_state != CAPTURE_STATE_CAPTURE && + next_state == CAPTURE_STATE_CAPTURE) + { + FAR vbuf_container_t *container = + video_framebuff_get_vacant_container(&cmng->capture_inf.bufinf); + if (container != NULL) + { + cmng->capture_inf.seqnum = 0; + start_capture(cmng, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + cmng->capture_inf.nr_fmt, + cmng->capture_inf.fmt, + &cmng->capture_inf.clip, + &cmng->capture_inf.frame_interval, + container->buf.m.userptr, + container->buf.length); + } + else + { + updated_next_state = CAPTURE_STATE_STREAMON; + } + } + else if (current_state == CAPTURE_STATE_CAPTURE && + next_state != CAPTURE_STATE_CAPTURE) + { + stop_capture(cmng, V4L2_BUF_TYPE_VIDEO_CAPTURE); + } + + cmng->capture_inf.state = updated_next_state; +} + +static bool is_taking_still_picture(FAR capture_mng_t *cmng) +{ + return cmng->still_inf.state == CAPTURE_STATE_STREAMON || + cmng->still_inf.state == CAPTURE_STATE_CAPTURE; +} + +static bool is_bufsize_sufficient(FAR capture_mng_t *cmng, uint32_t bufsize) +{ + /* Depend on format, frame size, and JPEG compression quality */ + + return true; +} + +static void initialize_frame_setting(FAR struct imgsensor_s *imgsensor, + FAR uint8_t *nr_fmt, + FAR video_format_t *fmt, + FAR struct v4l2_fract *interval) +{ + ASSERT(nr_fmt && fmt && interval); + + /* Initial setting : QVGA YUV4:2:2 15FPS */ + + *nr_fmt = 1; + if (imgsensor && imgsensor->frmsizes) + { + if (imgsensor->frmsizes[0].type == V4L2_FRMSIZE_TYPE_DISCRETE) + { + fmt[CAPTURE_FMT_MAIN].width = + imgsensor->frmsizes[0].discrete.width; + fmt[CAPTURE_FMT_MAIN].height = + imgsensor->frmsizes[0].discrete.height; + } + else + { + fmt[CAPTURE_FMT_MAIN].width = + imgsensor->frmsizes[0].stepwise.min_width; + fmt[CAPTURE_FMT_MAIN].height = + imgsensor->frmsizes[0].stepwise.min_height; + } + } + else + { + fmt[CAPTURE_FMT_MAIN].width = VIDEO_HSIZE_QVGA; + fmt[CAPTURE_FMT_MAIN].height = VIDEO_VSIZE_QVGA; + } + + if (imgsensor && imgsensor->fmtdescs) + { + fmt[CAPTURE_FMT_MAIN].pixelformat = imgsensor->fmtdescs[0].pixelformat; + } + else + { + fmt[CAPTURE_FMT_MAIN].pixelformat = V4L2_PIX_FMT_UYVY; + } + + if (imgsensor && imgsensor->frmintervals) + { + if (imgsensor->frmintervals[0].type == V4L2_FRMIVAL_TYPE_DISCRETE) + { + interval->denominator = + imgsensor->frmintervals[0].discrete.denominator; + interval->numerator = + imgsensor->frmintervals[0].discrete.numerator; + } + else + { + interval->denominator = + imgsensor->frmintervals[0].stepwise.min.denominator; + interval->numerator = + imgsensor->frmintervals[0].stepwise.min.numerator; + } + } + else + { + interval->denominator = 15; + interval->numerator = 1; + } +} + +static void initialize_streamresources(FAR capture_type_inf_t *type_inf, + FAR capture_mng_t *cmng) +{ + memset(type_inf, 0, sizeof(capture_type_inf_t)); + type_inf->remaining_capnum = REMAINING_CAPNUM_INFINITY; + nxmutex_init(&type_inf->lock_state); + nxsem_init(&type_inf->wait_capture.dqbuf_wait_flg, 0, 0); + initialize_frame_setting(cmng->imgsensor, &type_inf->nr_fmt, + type_inf->fmt, + &type_inf->frame_interval); + video_framebuff_init(&type_inf->bufinf); +} + +static int32_t get_default_value(FAR capture_mng_t *cmng, uint32_t id) +{ + imgsensor_supported_value_t value; + int ret; + + if (cmng->imgsensor == NULL) + { + /* Don't care(unsupported parameter) */ + + return 0; + } + + ret = IMGSENSOR_GET_SUPPORTED_VALUE(cmng->imgsensor, id, &value); + if (ret != OK) + { + /* Don't care(unsupported parameter) */ + + return 0; + } + + switch (value.type) + { + case IMGSENSOR_CTRL_TYPE_INTEGER_MENU: + return value.u.discrete.default_value; + + case IMGSENSOR_CTRL_TYPE_U8: + case IMGSENSOR_CTRL_TYPE_U16: + case IMGSENSOR_CTRL_TYPE_U32: + + /* Don't care */ + + return 0; + + default: + return value.u.range.default_value; + } +} + +static int32_t initialize_scene_gamma(FAR capture_mng_t *cmng, + FAR uint8_t **gamma) +{ + imgsensor_supported_value_t sup_val; + imgsensor_value_t val; + int32_t sz; + int ret; + + *gamma = NULL; + + ASSERT(cmng->imgsensor); + + ret = IMGSENSOR_GET_SUPPORTED_VALUE(cmng->imgsensor, + IMGSENSOR_ID_GAMMA_CURVE, &sup_val); + if (ret != OK) + { + /* Unsupported parameter */ + + return 0; + } + + switch (sup_val.type) + { + case IMGSENSOR_CTRL_TYPE_U8: + sz = sup_val.u.elems.nr_elems * sizeof(uint8_t); + if (sz / sizeof(uint8_t) != sup_val.u.elems.nr_elems) + { + /* Multiplication overflow */ + + return 0; + } + + break; + + case IMGSENSOR_CTRL_TYPE_U16: + sz = sup_val.u.elems.nr_elems * sizeof(uint16_t); + if (sz / sizeof(uint16_t) != sup_val.u.elems.nr_elems) + { + /* Multiplication overflow */ + + return 0; + } + + break; + + default: /* IMGSENSOR_CTRL_TYPE_U32 */ + sz = sup_val.u.elems.nr_elems * sizeof(uint32_t); + if (sz / sizeof(uint32_t) != sup_val.u.elems.nr_elems) + { + /* Multiplication overflow */ + + return 0; + } + + break; + } + + *gamma = kmm_malloc(sz); + val.p_u8 = (FAR uint8_t *)*gamma; + IMGSENSOR_GET_VALUE(cmng->imgsensor, IMGSENSOR_ID_GAMMA_CURVE, sz, &val); + return sz; +} + +static int initialize_scene_parameter(FAR capture_mng_t *cmng, + enum v4l2_scene_mode mode, + FAR capture_scene_params_t **vsp) +{ + FAR capture_scene_params_t *sp = + kmm_malloc(sizeof(capture_scene_params_t)); + + if (!sp) + { + return -ENOMEM; + } + + sp->mode = mode; + sp->brightness = get_default_value(cmng, IMGSENSOR_ID_BRIGHTNESS); + sp->contrast = get_default_value(cmng, IMGSENSOR_ID_CONTRAST); + sp->saturation = get_default_value(cmng, IMGSENSOR_ID_SATURATION); + sp->hue = get_default_value(cmng, IMGSENSOR_ID_HUE); + sp->awb = get_default_value(cmng, + IMGSENSOR_ID_AUTO_WHITE_BALANCE); + sp->red = get_default_value(cmng, IMGSENSOR_ID_RED_BALANCE); + sp->blue = get_default_value(cmng, IMGSENSOR_ID_BLUE_BALANCE); + sp->gamma = get_default_value(cmng, IMGSENSOR_ID_GAMMA); + sp->gamma_curve_sz = initialize_scene_gamma(cmng, &sp->gamma_curve); + sp->ev = get_default_value(cmng, IMGSENSOR_ID_EXPOSURE); + sp->hflip_video = get_default_value(cmng, IMGSENSOR_ID_HFLIP_VIDEO); + sp->vflip_video = get_default_value(cmng, IMGSENSOR_ID_VFLIP_VIDEO); + sp->hflip_still = get_default_value(cmng, IMGSENSOR_ID_HFLIP_STILL); + sp->vflip_still = get_default_value(cmng, IMGSENSOR_ID_VFLIP_STILL); + sp->sharpness = get_default_value(cmng, IMGSENSOR_ID_SHARPNESS); + sp->colorfx = get_default_value(cmng, IMGSENSOR_ID_COLORFX); + sp->auto_brightness = get_default_value(cmng, IMGSENSOR_ID_AUTOBRIGHTNESS); + sp->rotate = get_default_value(cmng, IMGSENSOR_ID_ROTATE); + sp->ae = get_default_value(cmng, IMGSENSOR_ID_EXPOSURE_AUTO); + sp->exposure_time = get_default_value(cmng, + IMGSENSOR_ID_EXPOSURE_ABSOLUTE); + sp->focus = get_default_value(cmng, IMGSENSOR_ID_FOCUS_ABSOLUTE); + sp->af = get_default_value(cmng, IMGSENSOR_ID_FOCUS_AUTO); + sp->zoom = get_default_value(cmng, IMGSENSOR_ID_ZOOM_ABSOLUTE); + sp->iris = get_default_value(cmng, IMGSENSOR_ID_IRIS_ABSOLUTE); + sp->wb = get_default_value(cmng, + IMGSENSOR_ID_AUTO_N_PRESET_WB); + sp->wdr = get_default_value(cmng, + IMGSENSOR_ID_WIDE_DYNAMIC_RANGE); + sp->stabilization = get_default_value(cmng, + IMGSENSOR_ID_IMG_STABILIZATION); + sp->iso_auto = get_default_value(cmng, + IMGSENSOR_ID_ISO_SENSITIVITY_AUTO); + sp->iso = get_default_value(cmng, + IMGSENSOR_ID_ISO_SENSITIVITY); + sp->meter = get_default_value(cmng, + IMGSENSOR_ID_EXPOSURE_METERING); + sp->threea_lock = get_default_value(cmng, IMGSENSOR_ID_3A_LOCK); + sp->led = get_default_value(cmng, IMGSENSOR_ID_FLASH_LED_MODE); + sp->jpeg_quality = get_default_value(cmng, IMGSENSOR_ID_JPEG_QUALITY); + + *vsp = sp; + + return OK; +} + +static void initialize_scenes_parameter(FAR capture_mng_t *cmng) +{ + memset(cmng->capture_scene_param, + 0, sizeof(cmng->capture_scene_param)); + + initialize_scene_parameter(cmng, V4L2_SCENE_MODE_NONE, + &cmng->capture_scene_param[cmng->capture_scence_num++]); +#ifdef CONFIG_VIDEO_SCENE_BACKLIGHT + initialize_scene_parameter(cmng, V4L2_SCENE_MODE_BACKLIGHT, + &cmng->capture_scene_param[cmng->capture_scence_num++]); +#endif /* CONFIG_VIDEO_SCENE_BACKLIGHT */ +#ifdef CONFIG_VIDEO_SCENE_BEACHSNOW + initialize_scene_parameter(cmng, V4L2_SCENE_MODE_BEACH_SNOW, + &cmng->capture_scene_param[cmng->capture_scence_num++]); +#endif /* CONFIG_VIDEO_SCENE_BEACHSNOW */ +#ifdef CONFIG_VIDEO_SCENE_CANDLELIGHT + initialize_scene_parameter(cmng, V4L2_SCENE_MODE_CANDLE_LIGHT, + &cmng->capture_scene_param[cmng->capture_scence_num++]); +#endif /* CONFIG_VIDEO_SCENE_CANDLELIGHT */ +#ifdef CONFIG_VIDEO_SCENE_DAWNDUSK + initialize_scene_parameter(cmng, V4L2_SCENE_MODE_DAWN_DUSK, + &cmng->capture_scene_param[cmng->capture_scence_num++]); +#endif /* CONFIG_VIDEO_SCENE_DAWNDUSK */ +#ifdef CONFIG_VIDEO_SCENE_FALLCOLORS + initialize_scene_parameter(cmng, V4L2_SCENE_MODE_FALL_COLORS, + &cmng->capture_scene_param[cmng->capture_scence_num++]); +#endif /* CONFIG_VIDEO_SCENE_FALLCOLORS */ +#ifdef CONFIG_VIDEO_SCENE_FIREWORKS + initialize_scene_parameter(cmng, V4L2_SCENE_MODE_FIREWORKS, + &cmng->capture_scene_param[cmng->capture_scence_num++]); +#endif /* CONFIG_VIDEO_SCENE_FIREWORKS */ +#ifdef CONFIG_VIDEO_SCENE_LANDSCAPE + initialize_scene_parameter(cmng, V4L2_SCENE_MODE_LANDSCAPE, + &cmng->capture_scene_param[cmng->capture_scence_num++]); +#endif /* CONFIG_VIDEO_SCENE_LANDSCAPE */ +#ifdef CONFIG_VIDEO_SCENE_NIGHT + initialize_scene_parameter(cmng, V4L2_SCENE_MODE_NIGHT, + &cmng->capture_scene_param[cmng->capture_scence_num++]); +#endif /* CONFIG_VIDEO_SCENE_NIGHT */ +#ifdef CONFIG_VIDEO_SCENE_PARTYINDOOR + initialize_scene_parameter(cmng, V4L2_SCENE_MODE_PARTY_INDOOR, + &cmng->capture_scene_param[cmng->capture_scence_num++]); +#endif /* CONFIG_VIDEO_SCENE_PARTYINDOOR */ +#ifdef CONFIG_VIDEO_SCENE_PORTRAIT + initialize_scene_parameter(cmng, V4L2_SCENE_MODE_PORTRAIT, + &cmng->capture_scene_param[cmng->capture_scence_num++]); +#endif /* CONFIG_VIDEO_SCENE_PORTRAIT */ +#ifdef CONFIG_VIDEO_SCENE_SPORTS + initialize_scene_parameter(cmng, V4L2_SCENE_MODE_SPORTS, + &cmng->capture_scene_param[cmng->capture_scence_num++]); +#endif /* CONFIG_VIDEO_SCENE_SPORTS */ +#ifdef CONFIG_VIDEO_SCENE_SUNSET + initialize_scene_parameter(cmng, V4L2_SCENE_MODE_SUNSET, + &cmng->capture_scene_param[cmng->capture_scence_num++]); +#endif /* CONFIG_VIDEO_SCENE_SUNSET */ +#ifdef CONFIG_VIDEO_SCENE_TEXT + initialize_scene_parameter(cmng, V4L2_SCENE_MODE_TEXT, + &cmng->capture_scene_param[cmng->capture_scence_num++]); +#endif /* CONFIG_VIDEO_SCENE_TEXT */ +} + +static void initialize_resources(FAR capture_mng_t *cmng) +{ + initialize_streamresources(&cmng->capture_inf, cmng); + initialize_streamresources(&cmng->still_inf, cmng); + initialize_scenes_parameter(cmng); +} + +static void cleanup_streamresources(FAR capture_type_inf_t *type_inf, + FAR capture_mng_t *cmng) +{ + video_framebuff_uninit(&type_inf->bufinf); + nxsem_destroy(&type_inf->wait_capture.dqbuf_wait_flg); + nxmutex_destroy(&type_inf->lock_state); + if (type_inf->bufheap != NULL) + { + if (cmng->imgdata->ops->free) + { + cmng->imgdata->ops->free(cmng->imgdata, type_inf->bufheap); + } + else + { + kumm_free(type_inf->bufheap); + } + + type_inf->bufheap = NULL; + } +} + +static void cleanup_scene_parameter(FAR capture_scene_params_t **vsp) +{ + FAR capture_scene_params_t *sp = *vsp; + ASSERT(sp); + + if (sp->gamma_curve != NULL) + { + kmm_free(sp->gamma_curve); + sp->gamma_curve = NULL; + sp->gamma_curve_sz = 0; + } + + kmm_free(sp); + *vsp = NULL; +} + +static void cleanup_scenes_parameter(FAR capture_mng_t *cmng) +{ + int i; + + for (i = 0; i < cmng->capture_scence_num; i++) + { + cleanup_scene_parameter(&cmng->capture_scene_param[i]); + } + + cmng->capture_scence_num = 0; +} + +static void cleanup_resources(FAR capture_mng_t *cmng) +{ + /* If in capture, stop */ + + if (cmng->capture_inf.state == CAPTURE_STATE_CAPTURE) + { + stop_capture(cmng, V4L2_BUF_TYPE_VIDEO_CAPTURE); + } + + if (cmng->still_inf.state == CAPTURE_STATE_CAPTURE) + { + stop_capture(cmng, V4L2_BUF_TYPE_STILL_CAPTURE); + } + + /* Clean up resource */ + + cleanup_streamresources(&cmng->capture_inf, cmng); + cleanup_streamresources(&cmng->still_inf, cmng); + cleanup_scenes_parameter(cmng); +} + +static bool is_sem_waited(FAR sem_t *sem) +{ + int semcount; + + return nxsem_get_value(sem, &semcount) == OK && semcount < 0; +} + +static int validate_frame_setting(FAR capture_mng_t *cmng, + enum v4l2_buf_type type, + uint8_t nr_fmt, + FAR video_format_t *vfmt, + FAR struct v4l2_rect *clip, + FAR struct v4l2_fract *interval) +{ + video_format_t c_fmt[MAX_CAPTURE_FMT]; + imgdata_format_t df[MAX_CAPTURE_FMT]; + imgsensor_format_t sf[MAX_CAPTURE_FMT]; + imgdata_interval_t di; + imgsensor_interval_t si; + int ret; + + ASSERT(vfmt && interval && cmng->imgsensor && cmng->imgdata); + + /* Return OK only in case both image data driver and + * image sensor driver support. + */ + + get_clipped_format(nr_fmt, vfmt, clip, c_fmt); + + convert_to_imgdatafmt(&c_fmt[CAPTURE_FMT_MAIN], &df[IMGDATA_FMT_MAIN]); + convert_to_imgdatafmt(&c_fmt[CAPTURE_FMT_SUB], &df[IMGDATA_FMT_SUB]); + convert_to_imgdatainterval(interval, &di); + convert_to_imgsensorfmt(&vfmt[CAPTURE_FMT_MAIN], &sf[IMGSENSOR_FMT_MAIN]); + convert_to_imgsensorfmt(&vfmt[CAPTURE_FMT_SUB], &sf[IMGSENSOR_FMT_SUB]); + convert_to_imgsensorinterval(interval, &si); + + ret = IMGSENSOR_VALIDATE_FRAME_SETTING(cmng->imgsensor, + type == V4L2_BUF_TYPE_VIDEO_CAPTURE ? + IMGSENSOR_STREAM_TYPE_VIDEO : IMGSENSOR_STREAM_TYPE_STILL, + nr_fmt, sf, &si); + if (ret != OK) + { + return ret; + } + + return IMGDATA_VALIDATE_FRAME_SETTING(cmng->imgdata, nr_fmt, df, &di); +} + +static size_t get_bufsize(FAR video_format_t *vf) +{ + size_t ret = vf->width * vf->height; + + switch (vf->pixelformat) + { + case V4L2_PIX_FMT_NV12: + case V4L2_PIX_FMT_YUV420: + return ret * 3 / 2; + case V4L2_PIX_FMT_YUYV: + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_RGB565: + case V4L2_PIX_FMT_JPEG: + default: + return ret * 2; + } +} + +static size_t get_heapsize(FAR capture_type_inf_t *type_inf) +{ + return type_inf->bufinf.container_size * + get_bufsize(&type_inf->fmt[CAPTURE_FMT_MAIN]); +} + +static bool validate_clip_range(int32_t pos, uint32_t c_sz, uint16_t frm_sz) +{ + return pos >= 0 && c_sz <= frm_sz && pos + c_sz <= frm_sz; +} + +static bool validate_clip_setting(FAR struct v4l2_rect *clip, + FAR video_format_t *fmt) +{ + DEBUGASSERT(clip && fmt); + + /* Not permit the setting which do not fit inside frame size. */ + + return validate_clip_range(clip->left, clip->width, fmt->width) && + validate_clip_range(clip->top, clip->height, fmt->height); +} + +static void set_parameter_name(uint32_t id, FAR char *name) +{ + int size = + sizeof(g_capture_parameter_name) / sizeof(capture_parameter_name_t); + int cnt; + + for (cnt = 0; cnt < size; cnt++) + { + if (g_capture_parameter_name[cnt].id == id) + { + break; + } + } + + ASSERT(cnt < size); + + /* copy size = 32 is due to V4L2 specification. */ + + strlcpy(name, g_capture_parameter_name[cnt].name, 32); +} + +static int set_intvalue(FAR struct capture_mng_s *cmng, + uint32_t id, int32_t value32) +{ + imgsensor_value_t value; + + ASSERT(cmng->imgsensor); + + value.value32 = value32; + return IMGSENSOR_SET_VALUE(cmng->imgsensor, id, sizeof(int32_t), value); +} + +static int set_pvalue(FAR struct capture_mng_s *cmng, + uint32_t id, int size, void *pval) +{ + imgsensor_value_t value; + + ASSERT(cmng->imgsensor); + + value.p_u8 = (FAR uint8_t *)pval; + return IMGSENSOR_SET_VALUE(cmng->imgsensor, id, size, value); +} + +static capture_scene_params_t *search_scene_param(FAR capture_mng_t *cmng, + enum v4l2_scene_mode mode) +{ + int i; + + for (i = 0; i < cmng->capture_scence_num; i++) + { + if (cmng->capture_scene_param[i]->mode == mode) + { + return cmng->capture_scene_param[i]; + } + } + + return NULL; +} + +static int reflect_scene_parameter(FAR capture_mng_t *cmng, + enum v4l2_scene_mode mode) +{ + capture_scene_params_t *sp; + + sp = search_scene_param(cmng, mode); + if (sp == NULL) + { + /* Unsupported scene mode */ + + return -EINVAL; + } + + set_intvalue(cmng, IMGSENSOR_ID_BRIGHTNESS, sp->brightness); + set_intvalue(cmng, IMGSENSOR_ID_CONTRAST, sp->contrast); + set_intvalue(cmng, IMGSENSOR_ID_SATURATION, sp->saturation); + set_intvalue(cmng, IMGSENSOR_ID_HUE , sp->hue); + set_intvalue(cmng, IMGSENSOR_ID_AUTO_WHITE_BALANCE, sp->awb); + set_intvalue(cmng, IMGSENSOR_ID_RED_BALANCE , sp->red); + set_intvalue(cmng, IMGSENSOR_ID_BLUE_BALANCE, sp->blue); + set_intvalue(cmng, IMGSENSOR_ID_GAMMA, sp->gamma); + set_pvalue(cmng, IMGSENSOR_ID_GAMMA_CURVE, + sp->gamma_curve_sz, sp->gamma_curve); + set_intvalue(cmng, IMGSENSOR_ID_EXPOSURE, sp->ev); + set_intvalue(cmng, IMGSENSOR_ID_HFLIP_VIDEO, sp->hflip_video); + set_intvalue(cmng, IMGSENSOR_ID_VFLIP_VIDEO, sp->vflip_video); + set_intvalue(cmng, IMGSENSOR_ID_HFLIP_STILL, sp->hflip_still); + set_intvalue(cmng, IMGSENSOR_ID_VFLIP_STILL, sp->vflip_still); + set_intvalue(cmng, IMGSENSOR_ID_SHARPNESS, sp->sharpness); + set_intvalue(cmng, IMGSENSOR_ID_COLORFX, sp->colorfx); + set_intvalue(cmng, IMGSENSOR_ID_AUTOBRIGHTNESS, sp->auto_brightness); + set_intvalue(cmng, IMGSENSOR_ID_ROTATE, sp->rotate); + set_intvalue(cmng, IMGSENSOR_ID_EXPOSURE_AUTO, sp->ae); + if (sp->ae == V4L2_EXPOSURE_MANUAL || + sp->ae == V4L2_EXPOSURE_SHUTTER_PRIORITY) + { + set_intvalue(cmng, IMGSENSOR_ID_EXPOSURE_ABSOLUTE, sp->exposure_time); + } + + set_intvalue(cmng, IMGSENSOR_ID_FOCUS_ABSOLUTE, sp->focus); + set_intvalue(cmng, IMGSENSOR_ID_FOCUS_AUTO, sp->af); + set_intvalue(cmng, IMGSENSOR_ID_ZOOM_ABSOLUTE, sp->zoom); + if (sp->ae == V4L2_EXPOSURE_MANUAL || + sp->ae == V4L2_EXPOSURE_APERTURE_PRIORITY) + { + set_intvalue(cmng, IMGSENSOR_ID_IRIS_ABSOLUTE, sp->iris); + } + + set_intvalue(cmng, IMGSENSOR_ID_AUTO_N_PRESET_WB, sp->wb); + set_intvalue(cmng, IMGSENSOR_ID_WIDE_DYNAMIC_RANGE, sp->wdr); + set_intvalue(cmng, IMGSENSOR_ID_IMG_STABILIZATION, sp->stabilization); + set_intvalue(cmng, IMGSENSOR_ID_ISO_SENSITIVITY_AUTO, sp->iso_auto); + if (sp->iso_auto == V4L2_ISO_SENSITIVITY_MANUAL) + { + set_intvalue(cmng, IMGSENSOR_ID_ISO_SENSITIVITY, sp->iso); + } + + set_intvalue(cmng, IMGSENSOR_ID_EXPOSURE_METERING, sp->meter); + set_intvalue(cmng, IMGSENSOR_ID_3A_LOCK, sp->threea_lock); + set_intvalue(cmng, IMGSENSOR_ID_FLASH_LED_MODE, sp->led); + set_intvalue(cmng, IMGSENSOR_ID_JPEG_QUALITY, sp->jpeg_quality); + + cmng->capture_scene_mode = mode; + return OK; +} + +static int read_scene_param(FAR struct capture_mng_s *cmng, + enum v4l2_scene_mode mode, + uint32_t id, + FAR struct v4l2_ext_control *control) +{ + imgsensor_supported_value_t value; + capture_scene_params_t *sp; + int ret = OK; + + ASSERT(cmng->imgsensor); + + if (control == NULL) + { + return -EINVAL; + } + + sp = search_scene_param(cmng, mode); + if (sp == NULL) + { + /* Unsupported scene mode */ + + return -EINVAL; + } + + ret = IMGSENSOR_GET_SUPPORTED_VALUE(cmng->imgsensor, id, &value); + if (ret < 0) + { + /* Unsupported camera parameter */ + + return ret; + } + + switch (id) + { + case IMGSENSOR_ID_BRIGHTNESS: + control->value = sp->brightness; + break; + + case IMGSENSOR_ID_CONTRAST: + control->value = sp->contrast; + break; + + case IMGSENSOR_ID_SATURATION: + control->value = sp->saturation; + break; + + case IMGSENSOR_ID_HUE: + control->value = sp->hue; + break; + + case IMGSENSOR_ID_AUTO_WHITE_BALANCE: + control->value = sp->awb; + break; + + case IMGSENSOR_ID_RED_BALANCE: + control->value = sp->red; + break; + + case IMGSENSOR_ID_BLUE_BALANCE: + control->value = sp->blue; + break; + + case IMGSENSOR_ID_GAMMA: + control->value = sp->gamma; + break; + + case IMGSENSOR_ID_GAMMA_CURVE: + memcpy(control->p_u8, + sp->gamma_curve, + sp->gamma_curve_sz); + break; + + case IMGSENSOR_ID_EXPOSURE: + control->value = sp->ev; + break; + + case IMGSENSOR_ID_HFLIP_VIDEO: + control->value = sp->hflip_video; + break; + + case IMGSENSOR_ID_VFLIP_VIDEO: + control->value = sp->vflip_video; + break; + + case IMGSENSOR_ID_HFLIP_STILL: + control->value = sp->hflip_still; + break; + + case IMGSENSOR_ID_VFLIP_STILL: + control->value = sp->vflip_still; + break; + + case IMGSENSOR_ID_SHARPNESS: + control->value = sp->sharpness; + break; + + case IMGSENSOR_ID_COLOR_KILLER: + control->value = sp->colorfx == V4L2_COLORFX_BW; + break; + + case IMGSENSOR_ID_COLORFX: + control->value = sp->colorfx; + break; + + case IMGSENSOR_ID_AUTOBRIGHTNESS: + control->value = sp->auto_brightness; + break; + + case IMGSENSOR_ID_ROTATE: + control->value = sp->rotate; + break; + + case IMGSENSOR_ID_EXPOSURE_AUTO: + control->value = sp->ae; + break; + + case IMGSENSOR_ID_EXPOSURE_ABSOLUTE: + control->value = sp->exposure_time; + break; + + case IMGSENSOR_ID_FOCUS_ABSOLUTE: + control->value = sp->focus; + break; + + case IMGSENSOR_ID_FOCUS_AUTO: + control->value = sp->af; + break; + + case IMGSENSOR_ID_ZOOM_ABSOLUTE: + control->value = sp->zoom; + break; + + case IMGSENSOR_ID_IRIS_ABSOLUTE: + control->value = sp->iris; + break; + + case IMGSENSOR_ID_AUTO_N_PRESET_WB: + control->value = sp->wb; + break; + + case IMGSENSOR_ID_WIDE_DYNAMIC_RANGE: + control->value = sp->wdr; + break; + + case IMGSENSOR_ID_IMG_STABILIZATION: + control->value = sp->stabilization; + break; + + case IMGSENSOR_ID_ISO_SENSITIVITY: + control->value = sp->iso; + break; + + case IMGSENSOR_ID_ISO_SENSITIVITY_AUTO: + control->value = sp->iso_auto; + break; + + case IMGSENSOR_ID_EXPOSURE_METERING: + control->value = sp->meter; + break; + + case IMGSENSOR_ID_SPOT_POSITION: + control->value = sp->spot_pos; + break; + + case IMGSENSOR_ID_3A_LOCK: + control->value = sp->threea_lock; + break; + + case IMGSENSOR_ID_FLASH_LED_MODE: + control->value = sp->led; + break; + + case IMGSENSOR_ID_JPEG_QUALITY: + control->value = sp->jpeg_quality; + break; + + default: + ret = -EINVAL; + break; + } + + return ret; +} + +static int check_range(int64_t value, + int64_t min, + int64_t max, + uint64_t step) +{ + if (value < min || value > max || + (value - min) % step != 0) + { + return -EINVAL; + } + + return OK; +} + +static int save_scene_param(FAR capture_mng_t *cmng, + enum v4l2_scene_mode mode, + uint32_t id, + FAR struct v4l2_ext_control *control) +{ + imgsensor_supported_value_t value; + FAR imgsensor_capability_range_t *range = &value.u.range; + FAR imgsensor_capability_discrete_t *disc = &value.u.discrete; + FAR imgsensor_capability_elems_t *elem = &value.u.elems; + FAR capture_scene_params_t *sp; + int ret; + int i; + + ASSERT(cmng->imgsensor); + + sp = search_scene_param(cmng, mode); + if (sp == NULL) + { + /* Unsupported scene mode */ + + return -EINVAL; + } + + ret = IMGSENSOR_GET_SUPPORTED_VALUE(cmng->imgsensor, id, &value); + if (ret < 0) + { + /* Unsupported camera parameter */ + + return ret; + } + + switch (value.type) + { + case IMGSENSOR_CTRL_TYPE_INTEGER_MENU: + for (i = 0; i < disc->nr_values; i++) + { + if (control->value == disc->values[i]) + { + break; + } + } + + if (i >= disc->nr_values) + { + return -EINVAL; + } + + break; + + case IMGSENSOR_CTRL_TYPE_U8: + if (control->size < elem->nr_elems * sizeof(uint8_t)) + { + return -EINVAL; + } + + for (i = 0; i < elem->nr_elems; i++) + { + ret = check_range(control->p_u8[i], + elem->minimum, + elem->maximum, + elem->step); + if (ret != OK) + { + return ret; + } + } + + break; + + case IMGSENSOR_CTRL_TYPE_U16: + if (control->size < elem->nr_elems * sizeof(uint16_t)) + { + return -EINVAL; + } + + for (i = 0; i < elem->nr_elems; i++) + { + ret = check_range(control->p_u16[i], + elem->minimum, + elem->maximum, + elem->step); + if (ret != OK) + { + return ret; + } + } + + break; + + case IMGSENSOR_CTRL_TYPE_U32: + if (control->size < elem->nr_elems * sizeof(uint32_t)) + { + return -EINVAL; + } + + for (i = 0; i < elem->nr_elems; i++) + { + ret = check_range(control->p_u32[i], + elem->minimum, + elem->maximum, + elem->step); + if (ret != OK) + { + return ret; + } + } + + break; + + default: + ret = check_range(control->value, + range->minimum, + range->maximum, + range->step); + if (ret != OK) + { + return ret; + } + + break; + } + + switch (id) + { + case IMGSENSOR_ID_BRIGHTNESS: + sp->brightness = control->value; + break; + + case IMGSENSOR_ID_CONTRAST: + sp->contrast = control->value; + break; + + case IMGSENSOR_ID_SATURATION: + sp->saturation = control->value; + break; + + case IMGSENSOR_ID_HUE: + sp->hue = control->value; + break; + + case IMGSENSOR_ID_AUTO_WHITE_BALANCE: + sp->awb = control->value; + break; + + case IMGSENSOR_ID_RED_BALANCE: + sp->red = control->value; + break; + + case IMGSENSOR_ID_BLUE_BALANCE: + sp->blue = control->value; + break; + + case IMGSENSOR_ID_GAMMA: + sp->gamma = control->value; + break; + + case IMGSENSOR_ID_GAMMA_CURVE: + memcpy(sp->gamma_curve, + control->p_u8, + sp->gamma_curve_sz); + break; + + case IMGSENSOR_ID_EXPOSURE: + sp->ev = control->value; + break; + + case IMGSENSOR_ID_HFLIP_VIDEO: + sp->hflip_video = control->value; + break; + + case IMGSENSOR_ID_VFLIP_VIDEO: + sp->vflip_video = control->value; + break; + + case IMGSENSOR_ID_HFLIP_STILL: + sp->hflip_still = control->value; + break; + + case IMGSENSOR_ID_VFLIP_STILL: + sp->vflip_still = control->value; + break; + + case IMGSENSOR_ID_SHARPNESS: + sp->sharpness = control->value; + break; + + case IMGSENSOR_ID_COLOR_KILLER: + sp->colorfx = control->value ? V4L2_COLORFX_BW : V4L2_COLORFX_NONE; + break; + + case IMGSENSOR_ID_COLORFX: + sp->colorfx = control->value; + break; + + case IMGSENSOR_ID_AUTOBRIGHTNESS: + sp->auto_brightness = control->value; + break; + + case IMGSENSOR_ID_ROTATE: + sp->rotate = control->value; + break; + + case IMGSENSOR_ID_EXPOSURE_AUTO: + sp->ae = control->value; + break; + + case IMGSENSOR_ID_EXPOSURE_ABSOLUTE: + sp->exposure_time = control->value; + break; + + case IMGSENSOR_ID_FOCUS_ABSOLUTE: + sp->focus = control->value; + break; + + case IMGSENSOR_ID_FOCUS_AUTO: + sp->af = control->value; + break; + + case IMGSENSOR_ID_ZOOM_ABSOLUTE: + sp->zoom = control->value; + break; + + case IMGSENSOR_ID_IRIS_ABSOLUTE: + sp->iris = control->value; + break; + + case IMGSENSOR_ID_AUTO_N_PRESET_WB: + sp->wb = control->value; + break; + + case IMGSENSOR_ID_WIDE_DYNAMIC_RANGE: + sp->wdr = control->value; + break; + + case IMGSENSOR_ID_IMG_STABILIZATION: + sp->stabilization = control->value; + break; + + case IMGSENSOR_ID_ISO_SENSITIVITY: + sp->iso = control->value; + break; + + case IMGSENSOR_ID_ISO_SENSITIVITY_AUTO: + sp->iso_auto = control->value; + break; + + case IMGSENSOR_ID_EXPOSURE_METERING: + sp->meter = control->value; + break; + + case IMGSENSOR_ID_SPOT_POSITION: + sp->spot_pos = control->value; + break; + + case IMGSENSOR_ID_3A_LOCK: + sp->threea_lock = control->value; + break; + + case IMGSENSOR_ID_FLASH_LED_MODE: + sp->led = control->value; + break; + + case IMGSENSOR_ID_JPEG_QUALITY: + sp->jpeg_quality = control->value; + break; + + default: + return -EINVAL; + } + + return OK; +} + +/* Callback function which device driver call when capture has done. */ + +static int complete_capture(uint8_t err_code, + uint32_t datasize, + FAR const struct timeval *ts, + FAR void *arg) +{ + FAR capture_mng_t *cmng = (FAR capture_mng_t *)arg; + FAR capture_type_inf_t *type_inf; + FAR vbuf_container_t *container = NULL; + enum v4l2_buf_type buf_type; + irqstate_t flags; + imgdata_format_t df[MAX_CAPTURE_FMT]; + video_format_t c_fmt[MAX_CAPTURE_FMT]; + + flags = enter_critical_section(); + + buf_type = cmng->still_inf.state == CAPTURE_STATE_CAPTURE ? + V4L2_BUF_TYPE_STILL_CAPTURE : V4L2_BUF_TYPE_VIDEO_CAPTURE; + + type_inf = get_capture_type_inf(cmng, buf_type); + if (type_inf == NULL) + { + leave_critical_section(flags); + return -EINVAL; + } + + poll_notify(&type_inf->fds, 1, POLLIN); + + if (err_code == 0) + { + type_inf->bufinf.vbuf_next->buf.flags = 0; + if (type_inf->remaining_capnum > 0) + { + type_inf->remaining_capnum--; + } + } + else + { + type_inf->bufinf.vbuf_next->buf.flags = V4L2_BUF_FLAG_ERROR; + } + + type_inf->bufinf.vbuf_next->buf.bytesused = datasize; + if (ts != NULL) + { + type_inf->bufinf.vbuf_next->buf.timestamp = *ts; + } + + video_framebuff_capture_done(&type_inf->bufinf); + + if (is_sem_waited(&type_inf->wait_capture.dqbuf_wait_flg)) + { + /* If waiting capture in DQBUF, + * get/save container and unlock wait + */ + + type_inf->wait_capture.done_container = + video_framebuff_pop_curr_container(&type_inf->bufinf); + type_inf->wait_capture.waitend_cause = WAITEND_CAUSE_CAPTUREDONE; + nxsem_post(&type_inf->wait_capture.dqbuf_wait_flg); + } + + if (type_inf->remaining_capnum == 0) + { + stop_capture(cmng, buf_type); + type_inf->state = CAPTURE_STATE_STREAMOFF; + + /* If stop still stream, notify it to video stream */ + + if (buf_type == V4L2_BUF_TYPE_STILL_CAPTURE && + is_sem_waited(&cmng->capture_inf.wait_capture.dqbuf_wait_flg)) + { + cmng->capture_inf.wait_capture.waitend_cause = + WAITEND_CAUSE_STILLSTOP; + nxsem_post(&cmng->capture_inf.wait_capture.dqbuf_wait_flg); + } + } + else + { + container = video_framebuff_get_vacant_container(&type_inf->bufinf); + if (container == NULL) + { + stop_capture(cmng, buf_type); + type_inf->state = CAPTURE_STATE_STREAMON; + } + else + { + get_clipped_format(type_inf->nr_fmt, + type_inf->fmt, + &type_inf->clip, + c_fmt); + + convert_to_imgdatafmt(&c_fmt[CAPTURE_FMT_MAIN], + &df[IMGDATA_FMT_MAIN]); + convert_to_imgdatafmt(&c_fmt[CAPTURE_FMT_SUB], + &df[IMGDATA_FMT_SUB]); + + IMGDATA_SET_BUF(cmng->imgdata, + type_inf->nr_fmt, + df, + (FAR uint8_t *)container->buf.m.userptr, + container->buf.length); + container->buf.sequence = type_inf->seqnum++; + } + } + + leave_critical_section(flags); + return OK; +} + +static FAR struct imgsensor_s * +get_connected_imgsensor(FAR struct imgsensor_s **sensors, + size_t sensor_num) +{ + FAR struct imgsensor_s *sensor = NULL; + int i; + + for (i = 0; i < sensor_num; i++) + { + if (sensors[i] && + IMGSENSOR_IS_AVAILABLE(sensors[i])) + { + sensor = sensors[i]; + break; + } + } + + return sensor; +} + +/**************************************************************************** + * Ioctl Functions + ****************************************************************************/ + +static int capture_querycap(FAR struct file *filep, + FAR struct v4l2_capability *cap) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR const char *name; + + if (cmng == NULL || cap == NULL) + { + return -EINVAL; + } + + ASSERT(cmng->imgsensor); + + name = IMGSENSOR_GET_DRIVER_NAME(cmng->imgsensor); + if (name == NULL) + { + return -ENOTTY; + } + + memset(cap, 0, sizeof(struct v4l2_capability)); + + /* cap->driver needs to be NULL-terminated. */ + + strlcpy((FAR char *)cap->driver, name, sizeof(cap->driver)); + cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; + + return OK; +} + +static int capture_g_input(FAR int *num) +{ + *num = 0; + return OK; +} + +static int capture_enum_input(FAR struct file *filep, + FAR struct v4l2_input *input) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR const char *name; + + if (cmng == NULL || input->index > 0) + { + return -EINVAL; + } + + ASSERT(cmng->imgsensor); + + name = IMGSENSOR_GET_DRIVER_NAME(cmng->imgsensor); + if (name == NULL) + { + return -ENOTTY; + } + + memset(input, 0, sizeof(struct v4l2_input)); + strlcpy((FAR char *)input->name, name, sizeof(input->name)); + input->type = V4L2_INPUT_TYPE_CAMERA; + + return OK; +} + +static int capture_reqbufs(FAR struct file *filep, + FAR struct v4l2_requestbuffers *reqbufs) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR capture_type_inf_t *type_inf; + struct imgdata_s *imgdata = cmng->imgdata; + + irqstate_t flags; + int ret = OK; + + if (cmng == NULL || reqbufs == NULL) + { + return -EINVAL; + } + + type_inf = get_capture_type_inf(cmng, reqbufs->type); + if (type_inf == NULL) + { + return -EINVAL; + } + + flags = enter_critical_section(); + + if (type_inf->state == CAPTURE_STATE_CAPTURE) + { + /* In capture, REQBUFS is not permitted */ + + ret = -EPERM; + } + else + { + if (reqbufs->count > V4L2_REQBUFS_COUNT_MAX) + { + reqbufs->count = V4L2_REQBUFS_COUNT_MAX; + } + + video_framebuff_change_mode(&type_inf->bufinf, reqbufs->mode); + ret = video_framebuff_realloc_container(&type_inf->bufinf, + reqbufs->count); + if (ret == OK && reqbufs->memory == V4L2_MEMORY_MMAP) + { + if (type_inf->bufheap != NULL) + { + if (imgdata->ops->free) + { + imgdata->ops->free(imgdata, type_inf->bufheap); + } + else + { + kumm_free(type_inf->bufheap); + } + } + + if (imgdata->ops->alloc) + { + type_inf->bufheap = imgdata->ops->alloc(imgdata, 32, + reqbufs->count * + get_bufsize(&type_inf->fmt[CAPTURE_FMT_MAIN])); + } + else + { + type_inf->bufheap = kumm_memalign(32, reqbufs->count * + get_bufsize(&type_inf->fmt[CAPTURE_FMT_MAIN])); + } + + if (type_inf->bufheap == NULL) + { + ret = -ENOMEM; + } + } + } + + leave_critical_section(flags); + return ret; +} + +static int capture_querybuf(FAR struct file *filep, + FAR struct v4l2_buffer *buf) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR capture_type_inf_t *type_inf; + + if (cmng == NULL || buf == NULL || buf->memory != V4L2_MEMORY_MMAP) + { + return -EINVAL; + } + + type_inf = get_capture_type_inf(cmng, buf->type); + if (type_inf == NULL) + { + return -EINVAL; + } + + if (buf->index >= type_inf->bufinf.container_size) + { + return -EINVAL; + } + + buf->length = get_bufsize(&type_inf->fmt[CAPTURE_FMT_MAIN]); + buf->m.offset = buf->length * buf->index; + + return OK; +} + +static int capture_qbuf(FAR struct file *filep, + FAR struct v4l2_buffer *buf) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR capture_type_inf_t *type_inf; + FAR vbuf_container_t *container; + enum capture_state_e next_capture_state; + irqstate_t flags; + + if (cmng == NULL || buf == NULL) + { + return -EINVAL; + } + + type_inf = get_capture_type_inf(cmng, buf->type); + if (type_inf == NULL) + { + return -EINVAL; + } + + if (!is_bufsize_sufficient(cmng, buf->length)) + { + return -EINVAL; + } + + container = video_framebuff_get_container(&type_inf->bufinf); + if (container == NULL) + { + return -ENOMEM; + } + + memcpy(&container->buf, buf, sizeof(struct v4l2_buffer)); + if (buf->memory == V4L2_MEMORY_MMAP) + { + /* only use userptr inside the container */ + + container->buf.length = get_bufsize(&type_inf->fmt[CAPTURE_FMT_MAIN]); + container->buf.m.userptr = (unsigned long)(type_inf->bufheap + + container->buf.length * buf->index); + } + + video_framebuff_queue_container(&type_inf->bufinf, container); + + nxmutex_lock(&type_inf->lock_state); + flags = enter_critical_section(); + if (type_inf->state == CAPTURE_STATE_STREAMON) + { + leave_critical_section(flags); + + if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) + { + nxmutex_lock(&cmng->still_inf.lock_state); + next_capture_state = + estimate_next_capture_state(cmng, CAUSE_CAPTURE_START); + change_capture_state(cmng, next_capture_state); + nxmutex_unlock(&cmng->still_inf.lock_state); + } + else + { + container = + video_framebuff_get_vacant_container(&type_inf->bufinf); + if (container != NULL) + { + type_inf->seqnum = 0; + start_capture(cmng, + buf->type, + type_inf->nr_fmt, + type_inf->fmt, + &type_inf->clip, + &type_inf->frame_interval, + container->buf.m.userptr, + container->buf.length); + type_inf->state = CAPTURE_STATE_CAPTURE; + } + } + } + else + { + leave_critical_section(flags); + } + + nxmutex_unlock(&type_inf->lock_state); + return OK; +} + +static int capture_dqbuf(FAR struct file *filep, + FAR struct v4l2_buffer *buf) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR capture_type_inf_t *type_inf; + FAR vbuf_container_t *container; + FAR sem_t *dqbuf_wait_flg; + enum capture_state_e next_capture_state; + irqstate_t flags; + + if (cmng == NULL || buf == NULL) + { + return -EINVAL; + } + + type_inf = get_capture_type_inf(cmng, buf->type); + if (type_inf == NULL) + { + return -EINVAL; + } + + container = video_framebuff_dq_valid_container(&type_inf->bufinf); + if (container == NULL) + { + if (filep->f_oflags & O_NONBLOCK) + { + return -EAGAIN; + } + + /* Not yet done capture. Wait done */ + + dqbuf_wait_flg = &type_inf->wait_capture.dqbuf_wait_flg; + + /* Loop until semaphore is unlocked by capture done or DQCANCEL */ + + do + { + if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) + { + /* If start capture condition is satisfied, start capture */ + + flags = enter_critical_section(); + next_capture_state = + estimate_next_capture_state(cmng, CAUSE_CAPTURE_DQBUF); + change_capture_state(cmng, next_capture_state); + leave_critical_section(flags); + } + + nxsem_wait_uninterruptible(dqbuf_wait_flg); + } + while (type_inf->wait_capture.waitend_cause == + WAITEND_CAUSE_STILLSTOP); + + container = type_inf->wait_capture.done_container; + if (container == NULL) + { + /* Waking up without captured data means abort. + * Therefore, Check cause. + */ + + if (type_inf->wait_capture.waitend_cause == WAITEND_CAUSE_DQCANCEL) + { + return -ECANCELED; + } + } + + type_inf->wait_capture.done_container = NULL; + } + + memcpy(buf, &container->buf, sizeof(struct v4l2_buffer)); + video_framebuff_free_container(&type_inf->bufinf, container); + + return OK; +} + +static int capture_cancel_dqbuf(FAR struct file *filep, + enum v4l2_buf_type type) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR capture_type_inf_t *type_inf; + + if (cmng == NULL) + { + return -EINVAL; + } + + type_inf = get_capture_type_inf(cmng, type); + if (type_inf == NULL) + { + return -EINVAL; + } + + if (!is_sem_waited(&type_inf->wait_capture.dqbuf_wait_flg)) + { + /* In not waiting DQBUF case, return OK */ + + return OK; + } + + type_inf->wait_capture.waitend_cause = WAITEND_CAUSE_DQCANCEL; + + /* If capture is done before nxsem_post, cause is overwritten */ + + return nxsem_post(&type_inf->wait_capture.dqbuf_wait_flg); +} + +static int capture_g_fmt(FAR struct file *filep, + FAR struct v4l2_format *fmt) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR capture_type_inf_t *type_inf; + + if (cmng == NULL) + { + return -EINVAL; + } + + type_inf = get_capture_type_inf(cmng, fmt->type); + if (type_inf == NULL) + { + return -EINVAL; + } + + memset(&fmt->fmt, 0, sizeof(fmt->fmt)); + fmt->fmt.pix.width = type_inf->fmt[CAPTURE_FMT_MAIN].width; + fmt->fmt.pix.height = type_inf->fmt[CAPTURE_FMT_MAIN].height; + fmt->fmt.pix.pixelformat = type_inf->fmt[CAPTURE_FMT_MAIN].pixelformat; + + return OK; +} + +static int capture_s_fmt(FAR struct file *filep, + FAR struct v4l2_format *fmt) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR capture_type_inf_t *type_inf; + int ret; + + if (cmng == NULL) + { + return -EINVAL; + } + + ret = capture_try_fmt(filep, fmt); + if (ret != 0) + { + return ret; + } + + type_inf = get_capture_type_inf(cmng, fmt->type); + if (type_inf == NULL) + { + return -EINVAL; + } + + if (type_inf->state != CAPTURE_STATE_STREAMOFF) + { + return -EBUSY; + } + + switch (fmt->fmt.pix.pixelformat) + { + case V4L2_PIX_FMT_SUBIMG_UYVY: + case V4L2_PIX_FMT_SUBIMG_RGB565: + if (type_inf->fmt[CAPTURE_FMT_MAIN].pixelformat != + V4L2_PIX_FMT_JPEG_WITH_SUBIMG) + { + return -EPERM; + } + + type_inf->fmt[CAPTURE_FMT_SUB].width = fmt->fmt.pix.width; + type_inf->fmt[CAPTURE_FMT_SUB].height = fmt->fmt.pix.height; + type_inf->fmt[CAPTURE_FMT_SUB].pixelformat = + fmt->fmt.pix.pixelformat == V4L2_PIX_FMT_SUBIMG_UYVY ? + V4L2_PIX_FMT_UYVY : V4L2_PIX_FMT_RGB565; + type_inf->nr_fmt = 2; + break; + + default: + type_inf->fmt[CAPTURE_FMT_MAIN].width = fmt->fmt.pix.width; + type_inf->fmt[CAPTURE_FMT_MAIN].height = fmt->fmt.pix.height; + type_inf->fmt[CAPTURE_FMT_MAIN].pixelformat = + fmt->fmt.pix.pixelformat; + type_inf->nr_fmt = 1; + break; + } + + return OK; +} + +static int capture_try_fmt(FAR struct file *filep, + FAR struct v4l2_format *fmt) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR capture_type_inf_t *type_inf; + video_format_t vf[MAX_CAPTURE_FMT]; + uint8_t nr_fmt; + + if (cmng == NULL || fmt == NULL) + { + return -EINVAL; + } + + ASSERT(cmng->imgsensor && cmng->imgdata); + + type_inf = get_capture_type_inf(cmng, fmt->type); + if (type_inf == NULL) + { + return -EINVAL; + } + + switch (fmt->fmt.pix.pixelformat) + { + case V4L2_PIX_FMT_SUBIMG_UYVY: + case V4L2_PIX_FMT_SUBIMG_RGB565: + if (type_inf->fmt[CAPTURE_FMT_MAIN].pixelformat != + V4L2_PIX_FMT_JPEG_WITH_SUBIMG) + { + return -EPERM; + } + + /* Validate both main image and subimage. */ + + nr_fmt = 2; + memcpy(&vf[CAPTURE_FMT_MAIN], + &type_inf->fmt[CAPTURE_FMT_MAIN], + sizeof(video_format_t)); + vf[CAPTURE_FMT_SUB].width = fmt->fmt.pix.width; + vf[CAPTURE_FMT_SUB].height = fmt->fmt.pix.height; + vf[CAPTURE_FMT_SUB].pixelformat = + fmt->fmt.pix.pixelformat == V4L2_PIX_FMT_SUBIMG_UYVY ? + V4L2_PIX_FMT_UYVY : V4L2_PIX_FMT_RGB565; + break; + case V4L2_PIX_FMT_NV12: + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_YUYV: + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_RGB565: + case V4L2_PIX_FMT_JPEG: + case V4L2_PIX_FMT_JPEG_WITH_SUBIMG: + nr_fmt = 1; + vf[CAPTURE_FMT_MAIN].width = fmt->fmt.pix.width; + vf[CAPTURE_FMT_MAIN].height = fmt->fmt.pix.height; + vf[CAPTURE_FMT_MAIN].pixelformat = fmt->fmt.pix.pixelformat; + break; + + default: + return -EINVAL; + } + + return validate_frame_setting(cmng, + fmt->type, + nr_fmt, + vf, + &type_inf->clip, + &type_inf->frame_interval); +} + +static int capture_g_parm(FAR struct file *filep, + FAR struct v4l2_streamparm *parm) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR capture_type_inf_t *type_inf; + int ret = -EINVAL; + + if (cmng == NULL || parm == NULL) + { + return -EINVAL; + } + + DEBUGASSERT(cmng->imgsensor); + + type_inf = get_capture_type_inf(cmng, parm->type); + if (type_inf == NULL) + { + return -EINVAL; + } + + memset(&parm->parm, 0, sizeof(parm->parm)); + + if (type_inf->state == CAPTURE_STATE_CAPTURE) + { + /* If capture is started and lower driver has the get_frame_interval(), + * query lower driver. + */ + + ret = IMGSENSOR_GET_FRAME_INTERVAL(cmng->imgsensor, parm->type, + (imgsensor_interval_t *)&parm->parm.capture.timeperframe); + } + + if (ret != OK) + { + /* In no capture state or error case, return stored value. */ + + memcpy(&parm->parm.capture.timeperframe, + &type_inf->frame_interval, + sizeof(struct v4l2_fract)); + } + + parm->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + return OK; +} + +static int capture_s_parm(FAR struct file *filep, + FAR struct v4l2_streamparm *parm) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR capture_type_inf_t *type_inf; + int ret; + + if (cmng == NULL || parm == NULL) + { + return -EINVAL; + } + + ASSERT(cmng->imgsensor && cmng->imgdata); + + type_inf = get_capture_type_inf(cmng, parm->type); + if (type_inf == NULL) + { + return -EINVAL; + } + + if (type_inf->state != CAPTURE_STATE_STREAMOFF) + { + return -EBUSY; + } + + ret = validate_frame_setting(cmng, + parm->type, + type_inf->nr_fmt, + type_inf->fmt, + &type_inf->clip, + &parm->parm.capture.timeperframe); + if (ret != OK) + { + return ret; + } + + memcpy(&type_inf->frame_interval, + &parm->parm.capture.timeperframe, + sizeof(struct v4l2_fract)); + + return ret; +} + +static int capture_streamon(FAR struct file *filep, + FAR enum v4l2_buf_type *type) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR capture_type_inf_t *type_inf; + enum capture_state_e next_capture_state; + int ret = OK; + + if (cmng == NULL || type == NULL) + { + return -EINVAL; + } + + type_inf = get_capture_type_inf(cmng, *type); + if (type_inf == NULL) + { + return -EINVAL; + } + + if (*type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + { + /* No procedure for VIDIOC_STREAMON(STILL_CAPTURE) */ + + return OK; + } + + nxmutex_lock(&type_inf->lock_state); + + if (type_inf->state != CAPTURE_STATE_STREAMOFF) + { + ret = -EPERM; + } + else + { + next_capture_state = + estimate_next_capture_state(cmng, CAUSE_CAPTURE_START); + change_capture_state(cmng, next_capture_state); + } + + nxmutex_unlock(&type_inf->lock_state); + return ret; +} + +static int capture_streamoff(FAR struct file *filep, + FAR enum v4l2_buf_type *type) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR capture_type_inf_t *type_inf; + enum capture_state_e next_capture_state; + irqstate_t flags; + int ret = OK; + + if (cmng == NULL || type == NULL) + { + return -EINVAL; + } + + type_inf = get_capture_type_inf(cmng, *type); + if (type_inf == NULL) + { + return -EINVAL; + } + + if (*type != V4L2_BUF_TYPE_VIDEO_CAPTURE) + { + /* No procedure for VIDIOC_STREAMOFF(STILL_CAPTURE) */ + + return OK; + } + + flags = enter_critical_section(); + + if (type_inf->state == CAPTURE_STATE_STREAMOFF) + { + ret = -EPERM; + } + else + { + next_capture_state = + estimate_next_capture_state(cmng, CAUSE_CAPTURE_STOP); + change_capture_state(cmng, next_capture_state); + } + + leave_critical_section(flags); + + return ret; +} + +static int capture_do_halfpush(FAR struct file *filep, bool enable) +{ + struct v4l2_ext_controls ext_controls; + struct v4l2_ext_control control[2]; + + /* Replace to VIDIOC_S_EXT_CTRLS format */ + + control[0].id = V4L2_CID_3A_LOCK; + control[0].value = enable ? + V4L2_LOCK_EXPOSURE | V4L2_LOCK_WHITE_BALANCE : 0; + control[1].id = V4L2_CID_AUTO_FOCUS_START; + control[1].value = enable ? true : false; + + ext_controls.ctrl_class = V4L2_CTRL_CLASS_CAMERA; + ext_controls.count = 2; + ext_controls.controls = control; + + /* Execute VIDIOC_S_EXT_CTRLS */ + + return capture_s_ext_ctrls(filep, &ext_controls); +} + +static int capture_takepict_start(FAR struct file *filep, + int32_t capture_num) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + enum capture_state_e next_capture_state; + FAR vbuf_container_t *container; + irqstate_t flags; + int ret = OK; + + if (cmng == NULL) + { + return -EINVAL; + } + + nxmutex_lock(&cmng->still_inf.lock_state); + + if (cmng->still_inf.state != CAPTURE_STATE_STREAMOFF) + { + ret = -EPERM; + } + else + { + if (capture_num > 0) + { + cmng->still_inf.remaining_capnum = capture_num; + } + else + { + cmng->still_inf.remaining_capnum = REMAINING_CAPNUM_INFINITY; + } + + /* Control video stream prior to still stream */ + + flags = enter_critical_section(); + + next_capture_state = estimate_next_capture_state(cmng, + CAUSE_STILL_START); + change_capture_state(cmng, next_capture_state); + + leave_critical_section(flags); + + container = + video_framebuff_get_vacant_container(&cmng->still_inf.bufinf); + if (container != NULL) + { + /* Start still stream capture */ + + start_capture(cmng, + V4L2_BUF_TYPE_STILL_CAPTURE, + cmng->still_inf.nr_fmt, + cmng->still_inf.fmt, + &cmng->still_inf.clip, + &cmng->still_inf.frame_interval, + container->buf.m.userptr, + container->buf.length); + + cmng->still_inf.state = CAPTURE_STATE_CAPTURE; + } + else + { + cmng->still_inf.state = CAPTURE_STATE_STREAMON; + } + } + + nxmutex_unlock(&cmng->still_inf.lock_state); + return ret; +} + +static int capture_takepict_stop(FAR struct file *filep, + bool halfpush) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + enum capture_state_e next_capture_state; + irqstate_t flags; + int ret = OK; + + if (cmng == NULL) + { + return -EINVAL; + } + + nxmutex_lock(&cmng->still_inf.lock_state); + + if (cmng->still_inf.state == CAPTURE_STATE_STREAMOFF && + cmng->still_inf.remaining_capnum == REMAINING_CAPNUM_INFINITY) + { + ret = -EPERM; + } + else + { + flags = enter_critical_section(); + if (cmng->still_inf.state == CAPTURE_STATE_CAPTURE) + { + stop_capture(cmng, V4L2_BUF_TYPE_STILL_CAPTURE); + } + + leave_critical_section(flags); + + cmng->still_inf.state = CAPTURE_STATE_STREAMOFF; + cmng->still_inf.remaining_capnum = REMAINING_CAPNUM_INFINITY; + + /* Control video stream */ + + nxmutex_lock(&cmng->capture_inf.lock_state); + next_capture_state = estimate_next_capture_state(cmng, + CAUSE_STILL_STOP); + change_capture_state(cmng, next_capture_state); + nxmutex_unlock(&cmng->capture_inf.lock_state); + } + + nxmutex_unlock(&cmng->still_inf.lock_state); + return ret; +} + +static int capture_s_selection(FAR struct file *filep, + FAR struct v4l2_selection *clip) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR capture_type_inf_t *type_inf; + uint32_t p_u32[IMGSENSOR_CLIP_NELEM]; + imgsensor_value_t val; + int32_t id; + int ret; + + if (cmng == NULL || clip == NULL) + { + return -EINVAL; + } + + ASSERT(cmng->imgsensor); + + type_inf = get_capture_type_inf(cmng, clip->type); + if (type_inf == NULL) + { + return -EINVAL; + } + + if (type_inf->state != CAPTURE_STATE_STREAMOFF) + { + return -EBUSY; + } + + if (!validate_clip_setting(&clip->r, type_inf->fmt)) + { + return -EINVAL; + } + + ret = validate_frame_setting(cmng, + clip->type, + type_inf->nr_fmt, + type_inf->fmt, + &clip->r, + &type_inf->frame_interval); + if (ret != OK) + { + return ret; + } + + id = clip->type == V4L2_BUF_TYPE_VIDEO_CAPTURE ? + IMGSENSOR_ID_CLIP_VIDEO : IMGSENSOR_ID_CLIP_STILL; + + p_u32[IMGSENSOR_CLIP_INDEX_LEFT] = clip->r.left; + p_u32[IMGSENSOR_CLIP_INDEX_TOP] = clip->r.top; + p_u32[IMGSENSOR_CLIP_INDEX_WIDTH] = clip->r.width; + p_u32[IMGSENSOR_CLIP_INDEX_HEIGHT] = clip->r.height; + + val.p_u32 = p_u32; + ret = IMGSENSOR_SET_VALUE(cmng->imgsensor, id, sizeof(p_u32), val); + if (ret != OK) + { + return ret; + } + + memcpy(&type_inf->clip, &clip->r, sizeof(struct v4l2_rect)); + return ret; +} + +static int capture_g_selection(FAR struct file *filep, + FAR struct v4l2_selection *clip) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR capture_type_inf_t *type_inf; + + if (cmng == NULL || clip == NULL) + { + return -EINVAL; + } + + type_inf = get_capture_type_inf(cmng, clip->type); + if (type_inf == NULL) + { + return -EINVAL; + } + + memcpy(&clip->r, &type_inf->clip, sizeof(struct v4l2_rect)); + return OK; +} + +static int capture_queryctrl(FAR struct file *filep, + FAR struct v4l2_queryctrl *ctrl) +{ + struct v4l2_query_ext_ctrl ext_ctrl; + int ret; + + if (ctrl == NULL) + { + return -EINVAL; + } + + /* Replace to VIDIOC_QUERY_EXT_CTRL format */ + + ext_ctrl.ctrl_class = ctrl->ctrl_class; + ext_ctrl.id = ctrl->id; + + ret = capture_query_ext_ctrl(filep, &ext_ctrl); + if (ret != OK) + { + return ret; + } + + if (ext_ctrl.type == V4L2_CTRL_TYPE_INTEGER64 || + ext_ctrl.type == V4L2_CTRL_TYPE_U8 || + ext_ctrl.type == V4L2_CTRL_TYPE_U16 || + ext_ctrl.type == V4L2_CTRL_TYPE_U32) + { + /* Unsupported type in VIDIOC_QUERYCTRL */ + + return -EINVAL; + } + + /* Replace gotten value to VIDIOC_QUERYCTRL */ + + ctrl->type = ext_ctrl.type; + ctrl->minimum = ext_ctrl.minimum; + ctrl->maximum = ext_ctrl.maximum; + ctrl->step = ext_ctrl.step; + ctrl->default_value = ext_ctrl.default_value; + ctrl->flags = ext_ctrl.flags; + strlcpy(ctrl->name, ext_ctrl.name, sizeof(ctrl->name)); + + return OK; +} + +static int capture_query_ext_ctrl(FAR struct file *filep, + FAR struct v4l2_query_ext_ctrl *attr) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + imgsensor_supported_value_t value; + imgsensor_capability_range_t *range = &value.u.range; + imgsensor_capability_discrete_t *disc = &value.u.discrete; + imgsensor_capability_elems_t *elem = &value.u.elems; + int ret; + + if (cmng == NULL || attr == NULL) + { + return -EINVAL; + } + + ASSERT(cmng->imgsensor); + + attr->flags = 0; + attr->elem_size = 0; + attr->elems = 1; + attr->nr_of_dims = 0; + memset(attr->dims, 0, sizeof(attr->dims)); + + if (attr->id == V4L2_CID_SCENE_MODE) + { + /* Scene mode is processed in only video driver. */ + + attr->type = V4L2_CTRL_TYPE_INTEGER_MENU; + attr->minimum = 0; + attr->maximum = cmng->capture_scence_num - 1; + attr->step = 1; + attr->default_value = 0; + attr->flags = 0; + strlcpy(attr->name, "Scene Mode", 32); + } + else + { + ret = IMGSENSOR_GET_SUPPORTED_VALUE(cmng->imgsensor, attr->id, &value); + if (ret < 0) + { + return ret; + } + + attr->type = value.type; + attr->flags = 0; + + switch (value.type) + { + case IMGSENSOR_CTRL_TYPE_INTEGER_MENU: + attr->minimum = 0; + attr->maximum = disc->nr_values - 1; + attr->step = 1; + attr->default_value = disc->default_value; + break; + + case IMGSENSOR_CTRL_TYPE_U8: + case IMGSENSOR_CTRL_TYPE_U16: + case IMGSENSOR_CTRL_TYPE_U32: + attr->minimum = elem->minimum; + attr->maximum = elem->maximum; + attr->step = elem->step; + attr->elems = elem->nr_elems; + break; + + default: + attr->minimum = range->minimum; + attr->maximum = range->maximum; + attr->step = range->step; + attr->default_value = range->default_value; + break; + } + + set_parameter_name(attr->id, attr->name); + } + + return OK; +} + +static int capture_querymenu(FAR struct file *filep, + FAR struct v4l2_querymenu *menu) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + imgsensor_supported_value_t value; + int ret; + + if (cmng == NULL || menu == NULL) + { + return -EINVAL; + } + + ASSERT(cmng->imgsensor); + + if (menu->id == V4L2_CID_SCENE_MODE) + { + /* Scene mode is processed in only video driver. */ + + if (menu->index > cmng->capture_scence_num - 1) + { + return -EINVAL; + } + + menu->value = cmng->capture_scene_param[menu->index]->mode; + } + else + { + ret = IMGSENSOR_GET_SUPPORTED_VALUE(cmng->imgsensor, + menu->id, + &value); + if (ret < 0) + { + return ret; + } + + if (value.type != IMGSENSOR_CTRL_TYPE_INTEGER_MENU) + { + /* VIDIOC_QUERYMENU is used only for + * IMGSENSOR_CTRL_TYPE_INTEGER_MENU. + */ + + return -EINVAL; + } + + if (menu->index >= value.u.discrete.nr_values) + { + return -EINVAL; + } + + menu->value = value.u.discrete.values[menu->index]; + } + + return OK; +} + +static int capture_g_ctrl(FAR struct file *filep, + FAR struct v4l2_control *ctrl) +{ + struct v4l2_ext_controls ext_controls; + struct v4l2_ext_control control; + int ret; + + if (ctrl == NULL) + { + return -EINVAL; + } + + memset(&ext_controls, 0, sizeof(struct v4l2_ext_controls)); + memset(&control, 0, sizeof(struct v4l2_ext_control)); + + /* Replace to VIDIOC_G_EXT_CTRLS format */ + + control.id = ctrl->id; + + ext_controls.ctrl_class = V4L2_CTRL_CLASS_USER; + ext_controls.count = 1; + ext_controls.controls = &control; + + /* Execute VIDIOC_G_EXT_CTRLS */ + + ret = capture_g_ext_ctrls(filep, &ext_controls); + if (ret == OK) + { + /* Replace gotten value to VIDIOC_G_CTRL parameter */ + + ctrl->value = control.value; + } + + return ret; +} + +static int capture_s_ctrl(FAR struct file *filep, + FAR struct v4l2_control *ctrl) +{ + struct v4l2_ext_controls ext_controls; + struct v4l2_ext_control control; + + if (ctrl == NULL) + { + return -EINVAL; + } + + /* Replace to VIDIOC_S_EXT_CTRLS format */ + + control.id = ctrl->id; + control.value = ctrl->value; + + ext_controls.ctrl_class = V4L2_CTRL_CLASS_USER; + ext_controls.count = 1; + ext_controls.controls = &control; + + /* Execute VIDIOC_S_EXT_CTRLS */ + + return capture_s_ext_ctrls(filep, &ext_controls); +} + +static int capture_g_ext_ctrls(FAR struct file *filep, + FAR struct v4l2_ext_controls *ctrls) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR struct v4l2_ext_control *control; + int ret = OK; + int cnt; + + if (cmng == NULL || ctrls == NULL) + { + return -EINVAL; + } + + ASSERT(cmng->imgsensor); + + for (cnt = 0, control = ctrls->controls; + cnt < ctrls->count; + cnt++, control++) + { + if (control->id == V4L2_CID_SCENE_MODE) + { + control->value = cmng->capture_scene_mode; + } + else + { + ret = IMGSENSOR_GET_VALUE(cmng->imgsensor, + control->id, + control->size, + (imgsensor_value_t *)&control->value64); + if (ret < 0) + { + /* Set cnt in that error occurred */ + + ctrls->error_idx = cnt; + return ret; + } + } + } + + return ret; +} + +static int capture_s_ext_ctrls(FAR struct file *filep, + FAR struct v4l2_ext_controls *ctrls) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR struct v4l2_ext_control *control; + int ret = OK; + int cnt; + + if (cmng == NULL || ctrls == NULL) + { + return -EINVAL; + } + + ASSERT(cmng->imgsensor); + + for (cnt = 0, control = ctrls->controls; + cnt < ctrls->count; + cnt++, control++) + { + if (control->id == V4L2_CID_SCENE_MODE) + { + ret = reflect_scene_parameter(cmng, control->value); + } + else + { + ret = IMGSENSOR_SET_VALUE(cmng->imgsensor, + control->id, + control->size, + (imgsensor_value_t)control->value64); + if (ret == 0) + { + if (cmng->capture_scene_mode == V4L2_SCENE_MODE_NONE) + { + save_scene_param(cmng, V4L2_SCENE_MODE_NONE, + control->id, + control); + } + } + } + + if (ret < 0) + { + /* Set cnt in that error occurred */ + + ctrls->error_idx = cnt; + return ret; + } + } + + return ret; +} + +static int capture_query_ext_ctrl_scene(FAR struct file *filep, + FAR struct v4s_query_ext_ctrl_scene *attr) +{ + if (attr == NULL) + { + return -EINVAL; + } + + return capture_query_ext_ctrl(filep, &attr->control); +} + +static int capture_querymenu_scene(FAR struct file *filep, + FAR struct v4s_querymenu_scene *menu) +{ + if (menu == NULL) + { + return -EINVAL; + } + + return capture_querymenu(filep, &menu->menu); +} + +static int capture_s_ext_ctrls_scene(FAR struct file *filep, + FAR struct v4s_ext_controls_scene *ctrls) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR struct v4l2_ext_control *control; + int ret = OK; + int cnt; + + if (cmng == NULL || ctrls == NULL) + { + return -EINVAL; + } + + for (cnt = 0, control = ctrls->control.controls; + cnt < ctrls->control.count; + cnt++, control++) + { + ret = save_scene_param(cmng, ctrls->mode, control->id, control); + if (ret != OK) + { + ctrls->control.error_idx = cnt; + return ret; + } + } + + return ret; +} + +static int capture_g_ext_ctrls_scene(FAR struct file *filep, + FAR struct v4s_ext_controls_scene *ctrls) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR struct v4l2_ext_control *control; + int ret = OK; + int cnt; + + if (cmng == NULL || ctrls == NULL) + { + return -EINVAL; + } + + for (cnt = 0, control = ctrls->control.controls; + cnt < ctrls->control.count; + cnt++, control++) + { + ret = read_scene_param(cmng, ctrls->mode, + control->id, + control); + if (ret != OK) + { + ctrls->control.error_idx = cnt; + return ret; + } + } + + return ret; +} + +static int capture_enum_fmt(FAR struct file *filep, + FAR struct v4l2_fmtdesc *f) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + + if (cmng == NULL || f == NULL) + { + return -EINVAL; + } + + if (cmng->imgsensor && cmng->imgsensor->fmtdescs) + { + if (f->index > cmng->imgsensor->fmtdescs_num) + { + return -EINVAL; + } + else + { + f->pixelformat = cmng->imgsensor->fmtdescs[f->index].pixelformat; + strlcpy(f->description, + cmng->imgsensor->fmtdescs[f->index].description, + sizeof(f->description)); + } + } + else + { + if (f->index > 0) + { + return -EINVAL; + } + + f->pixelformat = V4L2_PIX_FMT_UYVY; + } + + return 0; +} + +static int capture_enum_frmsize(FAR struct file *filep, + FAR struct v4l2_frmsizeenum *f) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + + if (cmng == NULL || f == NULL) + { + return -EINVAL; + } + + if (cmng->imgsensor && cmng->imgsensor->frmsizes) + { + if (f->index > cmng->imgsensor->frmsizes_num) + { + return -EINVAL; + } + else + { + f->type = cmng->imgsensor->frmsizes[f->index].type; + if (f->type == V4L2_FRMSIZE_TYPE_DISCRETE) + { + f->discrete = cmng->imgsensor->frmsizes[f->index].discrete; + } + else + { + f->stepwise = cmng->imgsensor->frmsizes[f->index].stepwise; + } + } + } + else + { + if (f->index > 0) + { + return -EINVAL; + } + + f->type = V4L2_FRMIVAL_TYPE_DISCRETE; + f->discrete.width = VIDEO_HSIZE_QVGA; + f->discrete.height = VIDEO_VSIZE_QVGA; + } + + return 0; +} + +static int capture_enum_frminterval(FAR struct file *filep, + FAR struct v4l2_frmivalenum *f) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + + if (cmng == NULL || f == NULL) + { + return -EINVAL; + } + + if (cmng->imgsensor && cmng->imgsensor->frmintervals) + { + if (f->index > cmng->imgsensor->frmintervals_num) + { + return -EINVAL; + } + else + { + f->type = cmng->imgsensor->frmintervals[f->index].type; + if (f->type == V4L2_FRMIVAL_TYPE_DISCRETE) + { + f->discrete = cmng->imgsensor->frmintervals[f->index].discrete; + } + else + { + f->stepwise = cmng->imgsensor->frmintervals[f->index].stepwise; + } + } + } + else + { + if (f->index > 0) + { + return -EINVAL; + } + + f->type = V4L2_FRMIVAL_TYPE_DISCRETE; + f->discrete.denominator = 15; + f->discrete.numerator = 1; + } + + return 0; +} + +/**************************************************************************** + * File Opterations Functions + ****************************************************************************/ + +static int capture_open(FAR struct file *filep) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + int ret = OK; + + if (cmng == NULL) + { + return -EINVAL; + } + + nxmutex_lock(&cmng->lock_open_num); + if (cmng->open_num == 0) + { + /* Only in first execution, open device */ + + ret = IMGSENSOR_INIT(cmng->imgsensor); + if (ret == OK) + { + ret = IMGDATA_INIT(cmng->imgdata); + if (ret == OK) + { + initialize_resources(cmng); + } + } + else + { + ret = -ENODEV; + } + } + + /* In second or later execution, ret is initial value(=OK) */ + + if (ret == OK) + { + cmng->open_num++; + } + + nxmutex_unlock(&cmng->lock_open_num); + return ret; +} + +static int capture_close(FAR struct file *filep) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + + if (cmng == NULL) + { + return -EINVAL; + } + + nxmutex_lock(&cmng->lock_open_num); + + if (--cmng->open_num == 0) + { + cleanup_resources(cmng); + IMGSENSOR_UNINIT(cmng->imgsensor); + IMGDATA_UNINIT(cmng->imgdata); +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + if (cmng->unlinked) + { + nxmutex_unlock(&cmng->lock_open_num); + nxmutex_destroy(&cmng->lock_open_num); + kmm_free(cmng); + inode->i_private = NULL; + return OK; + } + +#endif + } + + nxmutex_unlock(&cmng->lock_open_num); + return OK; +} + +static int capture_mmap(FAR struct file *filep, + FAR struct mm_map_entry_s *map) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR capture_type_inf_t *type_inf; + size_t heapsize; + int ret = -EINVAL; + + if (cmng == NULL) + { + return -EINVAL; + } + + type_inf = &cmng->capture_inf; + heapsize = get_heapsize(type_inf); + + if (map->offset >= 0 && map->offset < heapsize && + map->length && map->offset + map->length <= heapsize) + { + map->vaddr = type_inf->bufheap + map->offset; + ret = OK; + } + + return ret; +} + +static int capture_poll(FAR struct file *filep, + FAR struct pollfd *fds, bool setup) +{ + FAR struct inode *inode = filep->f_inode; + FAR capture_mng_t *cmng = inode->i_private; + FAR capture_type_inf_t *type_inf; + enum v4l2_buf_type buf_type; + irqstate_t flags; + + if (cmng == NULL) + { + return -EINVAL; + } + + buf_type = cmng->still_inf.state == CAPTURE_STATE_CAPTURE ? + V4L2_BUF_TYPE_STILL_CAPTURE : V4L2_BUF_TYPE_VIDEO_CAPTURE; + + type_inf = get_capture_type_inf(cmng, buf_type); + if (type_inf == NULL) + { + return -EINVAL; + } + + flags = enter_critical_section(); + + if (setup) + { + if (type_inf->fds == NULL) + { + type_inf->fds = fds; + fds->priv = &type_inf->fds; + if (!video_framebuff_is_empty(&type_inf->bufinf)) + { + poll_notify(&fds, 1, POLLIN); + } + } + else + { + leave_critical_section(flags); + return -EBUSY; + } + } + else if (fds->priv) + { + type_inf->fds = NULL; + fds->priv = NULL; + } + + leave_critical_section(flags); + + return OK; +} + +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS +static int capture_unlink(FAR struct inode *inode) +{ + FAR capture_mng_t *cmng = inode->i_private; + + if (cmng == NULL) + { + return -EINVAL; + } + + nxmutex_lock(&cmng->lock_open_num); + if (cmng->open_num == 0) + { + nxmutex_unlock(&cmng->lock_open_num); + nxmutex_destroy(&cmng->lock_open_num); + kmm_free(cmng); + inode->i_private = NULL; + } + else + { + cmng->unlinked = true; + nxmutex_unlock(&cmng->lock_open_num); + } + + nxmutex_destroy(&cmng->lock_open_num); + + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int capture_initialize(FAR const char *devpath) +{ + return capture_register(devpath, + g_capture_data, + g_capture_registered_sensor, + g_capture_registered_sensor_num); +} + +int capture_uninitialize(FAR const char *devpath) +{ + return capture_unregister(devpath); +} + +int capture_register(FAR const char *devpath, + FAR struct imgdata_s *data, + FAR struct imgsensor_s **sensors, + size_t sensor_num) +{ + FAR capture_mng_t *cmng; + int ret; + + /* Input devpath Error Check */ + + if (devpath == NULL || data == NULL) + { + return -EINVAL; + } + + /* Initialize capture device structure */ + + cmng = kmm_zalloc(sizeof(capture_mng_t)); + if (cmng == NULL) + { + verr("Failed to allocate instance\n"); + return -ENOMEM; + } + + cmng->v4l2.vops = &g_capture_vops; + cmng->v4l2.fops = &g_capture_fops; + + cmng->imgdata = data; + cmng->imgsensor = get_connected_imgsensor(sensors, sensor_num); + if (cmng->imgsensor == NULL) + { + kmm_free(cmng); + return -EINVAL; + } + + /* Initialize mutex */ + + nxmutex_init(&cmng->lock_open_num); + + /* Register the character driver */ + + ret = video_register(devpath, (FAR struct v4l2_s *)cmng); + if (ret < 0) + { + verr("Failed to register driver: %d\n", ret); + nxmutex_destroy(&cmng->lock_open_num); + kmm_free(cmng); + return ret; + } + + return OK; +} + +int capture_unregister(FAR const char *devpath) +{ + return unregister_driver(devpath); +} + +int imgsensor_register(FAR struct imgsensor_s *sensor) +{ + FAR struct imgsensor_s **new_addr; + int ret = -ENOMEM; + + new_addr = kmm_realloc(g_capture_registered_sensor, sizeof(sensor) * + (g_capture_registered_sensor_num + 1)); + if (new_addr != NULL) + { + new_addr[g_capture_registered_sensor_num++] = sensor; + g_capture_registered_sensor = new_addr; + ret = OK; + } + + return ret; +} + +void imgdata_register(FAR struct imgdata_s *data) +{ + g_capture_data = data; +} diff --git a/drivers/video/v4l2_core.c b/drivers/video/v4l2_core.c new file mode 100644 index 0000000000000..674308daaef01 --- /dev/null +++ b/drivers/video/v4l2_core.c @@ -0,0 +1,572 @@ +/**************************************************************************** + * drivers/video/v4l2_core.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Character driver methods. */ + +static int v4l2_open(FAR struct file *filep); +static int v4l2_close(FAR struct file *filep); +static ssize_t v4l2_read(FAR struct file *filep, + FAR char *buffer, size_t buflen); +static ssize_t v4l2_write(FAR struct file *filep, + FAR const char *buffer, size_t buflen); +static int v4l2_ioctl(FAR struct file *filep, + int cmd, unsigned long arg); +static int v4l2_mmap(FAR struct file *filep, + FAR struct mm_map_entry_s *map); +static int v4l2_poll(FAR struct file *filep, + FAR struct pollfd *fds, bool setup); +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS +static int v4l2_unlink(FAR struct inode *inode); +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +static const struct file_operations g_v4l2_fops = +{ + v4l2_open, /* open */ + v4l2_close, /* close */ + v4l2_read, /* read */ + v4l2_write, /* write */ + NULL, /* seek */ + v4l2_ioctl, /* ioctl */ + v4l2_mmap, /* mmap */ + NULL, /* truncate */ + v4l2_poll, /* poll */ +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + v4l2_unlink, /* unlink */ +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static int v4l2_open(FAR struct file *filep) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct v4l2_s *v4l2 = inode->i_private; + + if (v4l2->fops->open != NULL) + { + return v4l2->fops->open(filep); + } + + return -ENOTSUP; +} + +static int v4l2_close(FAR struct file *filep) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct v4l2_s *v4l2 = inode->i_private; + + if (v4l2->fops->close != NULL) + { + return v4l2->fops->close(filep); + } + + return -ENOTSUP; +} + +static ssize_t v4l2_read(FAR struct file *filep, + FAR char *buffer, size_t buflen) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct v4l2_s *v4l2 = inode->i_private; + + if (v4l2->fops->read != NULL) + { + return v4l2->fops->read(filep, buffer, buflen); + } + + return -ENOTSUP; +} + +static ssize_t v4l2_write(FAR struct file *filep, + FAR const char *buffer, size_t buflen) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct v4l2_s *v4l2 = inode->i_private; + + if (v4l2->fops->write != NULL) + { + return v4l2->fops->write(filep, buffer, buflen); + } + + return -ENOTSUP; +} + +static int v4l2_ioctl(FAR struct file *filep, + int cmd, unsigned long arg) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct v4l2_s *v4l2 = inode->i_private; + + switch (cmd) + { + case VIDIOC_QUERYCAP: + if (v4l2->vops->querycap == NULL) + { + break; + } + + return v4l2->vops->querycap(filep, + (FAR struct v4l2_capability *)arg); + + case VIDIOC_G_INPUT: + if (v4l2->vops->g_input == NULL) + { + break; + } + + return v4l2->vops->g_input((FAR int *)arg); + + case VIDIOC_ENUMINPUT: + if (v4l2->vops->enum_input == NULL) + { + break; + } + + return v4l2->vops->enum_input(filep, + (FAR struct v4l2_input *)arg); + + case VIDIOC_REQBUFS: + if (v4l2->vops->reqbufs == NULL) + { + break; + } + + return v4l2->vops->reqbufs(filep, + (FAR struct v4l2_requestbuffers *)arg); + + case VIDIOC_QUERYBUF: + if (v4l2->vops->querybuf == NULL) + { + break; + } + + return v4l2->vops->querybuf(filep, + (FAR struct v4l2_buffer *)arg); + + case VIDIOC_QBUF: + if (v4l2->vops->qbuf == NULL) + { + break; + } + + return v4l2->vops->qbuf(filep, + (FAR struct v4l2_buffer *)arg); + + case VIDIOC_DQBUF: + if (v4l2->vops->dqbuf == NULL) + { + break; + } + + return v4l2->vops->dqbuf(filep, + (FAR struct v4l2_buffer *)arg); + + case VIDIOC_CANCEL_DQBUF: + if (v4l2->vops->cancel_dqbuf == NULL) + { + break; + } + + return v4l2->vops->cancel_dqbuf(filep, + (FAR enum v4l2_buf_type)arg); + + case VIDIOC_STREAMON: + if (v4l2->vops->streamon == NULL) + { + break; + } + + return v4l2->vops->streamon(filep, + (FAR enum v4l2_buf_type *)arg); + + case VIDIOC_STREAMOFF: + if (v4l2->vops->streamoff == NULL) + { + break; + } + + return v4l2->vops->streamoff(filep, + (FAR enum v4l2_buf_type *)arg); + + case VIDIOC_DO_HALFPUSH: + if (v4l2->vops->do_halfpush == NULL) + { + break; + } + + return v4l2->vops->do_halfpush(filep, arg); + + case VIDIOC_TAKEPICT_START: + if (v4l2->vops->takepict_start == NULL) + { + break; + } + + return v4l2->vops->takepict_start(filep, (int32_t)arg); + + case VIDIOC_TAKEPICT_STOP: + if (v4l2->vops->takepict_stop == NULL) + { + break; + } + + return v4l2->vops->takepict_stop(filep, arg); + + case VIDIOC_S_SELECTION: + if (v4l2->vops->s_selection == NULL) + { + break; + } + + return v4l2->vops->s_selection(filep, + (FAR struct v4l2_selection *)arg); + + case VIDIOC_G_SELECTION: + if (v4l2->vops->g_selection == NULL) + { + break; + } + + return v4l2->vops->g_selection(filep, + (FAR struct v4l2_selection *)arg); + + case VIDIOC_TRY_FMT: + if (v4l2->vops->try_fmt == NULL) + { + break; + } + + return v4l2->vops->try_fmt(filep, + (FAR struct v4l2_format *)arg); + + case VIDIOC_G_FMT: + if (v4l2->vops->g_fmt == NULL) + { + break; + } + + return v4l2->vops->g_fmt(filep, + (FAR struct v4l2_format *)arg); + + case VIDIOC_S_FMT: + if (v4l2->vops->s_fmt == NULL) + { + break; + } + + return v4l2->vops->s_fmt(filep, + (FAR struct v4l2_format *)arg); + + case VIDIOC_S_PARM: + if (v4l2->vops->s_parm == NULL) + { + break; + } + + return v4l2->vops->s_parm(filep, + (FAR struct v4l2_streamparm *)arg); + + case VIDIOC_G_PARM: + if (v4l2->vops->g_parm == NULL) + { + break; + } + + return v4l2->vops->g_parm(filep, + (FAR struct v4l2_streamparm *)arg); + + case VIDIOC_QUERYCTRL: + if (v4l2->vops->queryctrl == NULL) + { + break; + } + + return v4l2->vops->queryctrl(filep, + (FAR struct v4l2_queryctrl *)arg); + + case VIDIOC_QUERY_EXT_CTRL: + if (v4l2->vops->query_ext_ctrl == NULL) + { + break; + } + + return v4l2->vops->query_ext_ctrl(filep, + (FAR struct v4l2_query_ext_ctrl *)arg); + + case VIDIOC_QUERYMENU: + if (v4l2->vops->querymenu == NULL) + { + break; + } + + return v4l2->vops->querymenu(filep, + (FAR struct v4l2_querymenu *)arg); + + case VIDIOC_G_CTRL: + if (v4l2->vops->g_ctrl == NULL) + { + break; + } + + return v4l2->vops->g_ctrl(filep, + (FAR struct v4l2_control *)arg); + + case VIDIOC_S_CTRL: + if (v4l2->vops->s_ctrl == NULL) + { + break; + } + + return v4l2->vops->s_ctrl(filep, + (FAR struct v4l2_control *)arg); + + case VIDIOC_G_EXT_CTRLS: + if (v4l2->vops->g_ext_ctrls == NULL) + { + break; + } + + return v4l2->vops->g_ext_ctrls(filep, + (FAR struct v4l2_ext_controls *)arg); + + case VIDIOC_S_EXT_CTRLS: + if (v4l2->vops->s_ext_ctrls == NULL) + { + break; + } + + return v4l2->vops->s_ext_ctrls(filep, + (FAR struct v4l2_ext_controls *)arg); + + case VIDIOC_G_STD: + break; + + case VIDIOC_S_STD: + break; + + case V4SIOC_QUERY_EXT_CTRL_SCENE: + if (v4l2->vops->query_ext_ctrl_scene == NULL) + { + break; + } + + return v4l2->vops->query_ext_ctrl_scene(filep, + (FAR struct v4s_query_ext_ctrl_scene *)arg); + + case V4SIOC_QUERYMENU_SCENE: + if (v4l2->vops->querymenu_scene == NULL) + { + break; + } + + return v4l2->vops->querymenu_scene(filep, + (FAR struct v4s_querymenu_scene *)arg); + + case V4SIOC_G_EXT_CTRLS_SCENE: + if (v4l2->vops->g_ext_ctrls_scene == NULL) + { + break; + } + + return v4l2->vops->g_ext_ctrls_scene(filep, + (FAR struct v4s_ext_controls_scene *)arg); + + case V4SIOC_S_EXT_CTRLS_SCENE: + if (v4l2->vops->s_ext_ctrls_scene == NULL) + { + break; + } + + return v4l2->vops->s_ext_ctrls_scene(filep, + (FAR struct v4s_ext_controls_scene *)arg); + + case VIDIOC_ENUM_FMT: + if (v4l2->vops->enum_fmt == NULL) + { + break; + } + + return v4l2->vops->enum_fmt(filep, + (FAR struct v4l2_fmtdesc *)arg); + + case VIDIOC_ENUM_FRAMEINTERVALS: + if (v4l2->vops->enum_frminterval == NULL) + { + break; + } + + return v4l2->vops->enum_frminterval(filep, + (FAR struct v4l2_frmivalenum *)arg); + + case VIDIOC_ENUM_FRAMESIZES: + if (v4l2->vops->enum_frmsize == NULL) + { + break; + } + + return v4l2->vops->enum_frmsize(filep, + (FAR struct v4l2_frmsizeenum *)arg); + + case VIDIOC_CROPCAP: + if (v4l2->vops->cropcap == NULL) + { + break; + } + + return v4l2->vops->cropcap(filep, + (FAR struct v4l2_cropcap *)arg); + + case VIDIOC_DQEVENT: + if (v4l2->vops->dqevent == NULL) + { + break; + } + + return v4l2->vops->dqevent(filep, + (FAR struct v4l2_event *)arg); + + case VIDIOC_SUBSCRIBE_EVENT: + if (v4l2->vops->subscribe_event == NULL) + { + break; + } + + return v4l2->vops->subscribe_event(filep, + (FAR struct v4l2_event_subscription *)arg); + + case VIDIOC_DECODER_CMD: + if (v4l2->vops->decoder_cmd == NULL) + { + break; + } + + return v4l2->vops->decoder_cmd(filep, + (FAR struct v4l2_decoder_cmd *)arg); + + case VIDIOC_ENCODER_CMD: + if (v4l2->vops->encoder_cmd == NULL) + { + break; + } + + return v4l2->vops->encoder_cmd(filep, + (FAR struct v4l2_encoder_cmd *)arg); + + default: + verr("Unrecognized cmd: %d\n", cmd); + break; + } + + return -ENOTTY; +} + +static int v4l2_mmap(FAR struct file *filep, + FAR struct mm_map_entry_s *map) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct v4l2_s *v4l2 = inode->i_private; + + if (v4l2->fops->mmap != NULL) + { + return v4l2->fops->mmap(filep, map); + } + + return -ENOTSUP; +} + +static int v4l2_poll(FAR struct file *filep, + FAR struct pollfd *fds, bool setup) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct v4l2_s *v4l2 = inode->i_private; + + if (v4l2->fops->poll != NULL) + { + return v4l2->fops->poll(filep, fds, setup); + } + + return -ENOTSUP; +} + +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS +static int v4l2_unlink(FAR struct inode *inode) +{ + FAR struct v4l2_s *v4l2 = inode->i_private; + + if (v4l2->fops->unlink != NULL) + { + return v4l2->fops->unlink(inode); + } + + return -ENOTSUP; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int video_register(FAR const char *devpath, FAR struct v4l2_s *v4l2) +{ + int ret; + + /* Input devpath Error Check */ + + if (devpath[0] != '/') + { + return -EINVAL; + } + + /* Register the character driver */ + + ret = register_driver(devpath, &g_v4l2_fops, 0666, v4l2); + if (ret < 0) + { + verr("Failed to register driver: %d\n", ret); + return ret; + } + + return OK; +} + +int video_unregister(FAR const char *devpath) +{ + return unregister_driver(devpath); +} diff --git a/drivers/video/v4l2_m2m.c b/drivers/video/v4l2_m2m.c new file mode 100644 index 0000000000000..f08f61cadf8c1 --- /dev/null +++ b/drivers/video/v4l2_m2m.c @@ -0,0 +1,1100 @@ +/**************************************************************************** + * drivers/video/v4l2_m2m.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +#include +#include + +#include "video_framebuff.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Offset base for buffers on the destination queue - used to distinguish + * between source and destination buffers when mmapping - they receive the + * same offsets but for different queues. + */ + +#define CAPTURE_BUF_OFFSET (1 << 30) +#define CODEC_EVENT_COUNT 6 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct codec_event_s +{ + sq_entry_t entry; + struct v4l2_event event; +}; + +typedef struct codec_event_s codec_event_t; + +struct codec_type_inf_s +{ + video_framebuff_t bufinf; + FAR uint8_t *bufheap; /* for V4L2_MEMORY_MMAP buffers */ + bool buflast; +}; + +typedef struct codec_type_inf_s codec_type_inf_t; + +struct codec_file_s +{ + codec_type_inf_t capture_inf; + codec_type_inf_t output_inf; + sq_queue_t event_avail; + sq_queue_t event_free; + codec_event_t event_pool[CODEC_EVENT_COUNT]; + FAR struct pollfd *fds; + FAR void *priv; +}; + +typedef struct codec_file_s codec_file_t; + +struct codec_mng_s +{ + struct v4l2_s v4l2; + FAR struct codec_s *codec; +}; + +typedef struct codec_mng_s codec_mng_t; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Character driver methods. */ + +static int codec_open(FAR struct file *filep); +static int codec_close(FAR struct file *filep); +static int codec_mmap(FAR struct file *filep, + FAR struct mm_map_entry_s *map); +static int codec_poll(FAR struct file *filep, + FAR struct pollfd *fds, bool setup); + +/* Common function */ + +static FAR codec_type_inf_t * +codec_get_type_inf(FAR struct codec_file_s *cfile, int type); + +/* ioctl function for each cmds of ioctl */ + +static int codec_querycap(FAR struct file *filep, + FAR struct v4l2_capability *cap); +static int codec_reqbufs(FAR struct file *filep, + FAR struct v4l2_requestbuffers *reqbufs); +static int codec_querybuf(FAR struct file *filep, + FAR struct v4l2_buffer *buf); +static int codec_qbuf(FAR struct file *filep, + FAR struct v4l2_buffer *buf); +static int codec_dqbuf(FAR struct file *filep, + FAR struct v4l2_buffer *buf); +static int codec_g_fmt(FAR struct file *filep, + FAR struct v4l2_format *fmt); +static int codec_s_fmt(FAR struct file *filep, + FAR struct v4l2_format *fmt); +static int codec_try_fmt(FAR struct file *filep, + FAR struct v4l2_format *fmt); +static int codec_g_parm(FAR struct file *filep, + FAR struct v4l2_streamparm *parm); +static int codec_s_parm(FAR struct file *filep, + FAR struct v4l2_streamparm *parm); +static int codec_streamon(FAR struct file *filep, + FAR enum v4l2_buf_type *type); +static int codec_streamoff(FAR struct file *filep, + FAR enum v4l2_buf_type *type); +static int codec_g_selection(FAR struct file *filep, + FAR struct v4l2_selection *clip); +static int codec_s_selection(FAR struct file *filep, + FAR struct v4l2_selection *clip); +static int codec_g_ext_ctrls(FAR struct file *filep, + FAR struct v4l2_ext_controls *ctrls); +static int codec_s_ext_ctrls(FAR struct file *filep, + FAR struct v4l2_ext_controls *ctrls); +static int codec_enum_fmt(FAR struct file *filep, + FAR struct v4l2_fmtdesc *fmt); +static int codec_cropcap(FAR struct file *filep, + FAR struct v4l2_cropcap *cropcap); +static int codec_dqevent(FAR struct file *filep, + FAR struct v4l2_event *event); +static int codec_subscribe_event(FAR struct file *filep, + FAR struct v4l2_event_subscription *sub); +static int codec_decoder_cmd(FAR struct file *filep, + FAR struct v4l2_decoder_cmd *cmd); +static int codec_encoder_cmd(FAR struct file *filep, + FAR struct v4l2_encoder_cmd *cmd); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct v4l2_ops_s g_codec_vops = +{ + codec_querycap, /* querycap */ + NULL, /* g_input */ + NULL, /* enum_input */ + codec_reqbufs, /* reqbufs */ + codec_querybuf, /* querybuf */ + codec_qbuf, /* qbuf */ + codec_dqbuf, /* dqbuf */ + NULL, /* cancel_dqbuf */ + codec_g_fmt, /* g_fmt */ + codec_s_fmt, /* s_fmt */ + codec_try_fmt, /* try_fmt */ + codec_g_parm, /* g_parm */ + codec_s_parm, /* s_parm */ + codec_streamon, /* streamon */ + codec_streamoff, /* streamoff */ + NULL, /* do_halfpush */ + NULL, /* takepict_start */ + NULL, /* takepict_stop */ + codec_s_selection, /* s_selection */ + codec_g_selection, /* g_selection */ + NULL, /* queryctrl */ + NULL, /* query_ext_ctrl */ + NULL, /* querymenu */ + NULL, /* g_ctrl */ + NULL, /* s_ctrl */ + codec_g_ext_ctrls, /* g_ext_ctrls */ + codec_s_ext_ctrls, /* s_ext_ctrls */ + NULL, /* query_ext_ctrl_scene */ + NULL, /* querymenu_scene */ + NULL, /* g_ext_ctrls_scene */ + NULL, /* s_ext_ctrls_scene */ + codec_enum_fmt, /* enum_fmt */ + NULL, /* enum_frminterval */ + NULL, /* enum_frmsize */ + codec_cropcap, /* cropcap */ + codec_dqevent, /* dqevent */ + codec_subscribe_event, /* subscribe_event */ + codec_decoder_cmd, /* decoder_cmd */ + codec_encoder_cmd /* encoder_cmd */ +}; + +static const struct file_operations g_codec_fops = +{ + codec_open, /* open */ + codec_close, /* close */ + NULL, /* read */ + NULL, /* write */ + NULL, /* seek */ + NULL, /* ioctl */ + codec_mmap, /* mmap */ + NULL, /* truncate */ + codec_poll, /* poll */ +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static FAR codec_type_inf_t * +codec_get_type_inf(FAR struct codec_file_s *cfile, int type) +{ + if (V4L2_TYPE_IS_OUTPUT(type)) + { + return &cfile->output_inf; + } + else + { + return &cfile->capture_inf; + } +} + +static int codec_querycap(FAR struct file *filep, + FAR struct v4l2_capability *cap) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + + return CODEC_QUERYCAP(cmng->codec, cfile->priv, cap); +} + +static int codec_enum_fmt(FAR struct file *filep, + FAR struct v4l2_fmtdesc *fmt) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + + if (fmt == NULL) + { + return -EINVAL; + } + + if (V4L2_TYPE_IS_OUTPUT(fmt->type)) + { + return CODEC_OUTPUT_ENUM_FMT(cmng->codec, cfile->priv, fmt); + } + else + { + return CODEC_CAPTURE_ENUM_FMT(cmng->codec, cfile->priv, fmt); + } +} + +static int codec_reqbufs(FAR struct file *filep, + FAR struct v4l2_requestbuffers *reqbufs) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + FAR codec_type_inf_t *type_inf; + irqstate_t flags; + size_t buf_size; + int ret = OK; + + if (reqbufs == NULL) + { + return -EINVAL; + } + + reqbufs->mode = V4L2_BUF_MODE_FIFO; + if (reqbufs->count > V4L2_REQBUFS_COUNT_MAX) + { + reqbufs->count = V4L2_REQBUFS_COUNT_MAX; + } + + if (V4L2_TYPE_IS_OUTPUT(reqbufs->type)) + { + buf_size = CODEC_OUTPUT_G_BUFSIZE(cmng->codec, cfile->priv); + } + else + { + buf_size = CODEC_CAPTURE_G_BUFSIZE(cmng->codec, cfile->priv); + } + + if (buf_size == 0) + { + return -EINVAL; + } + + flags = enter_critical_section(); + + type_inf = codec_get_type_inf(cfile, reqbufs->type); + video_framebuff_change_mode(&type_inf->bufinf, reqbufs->mode); + ret = video_framebuff_realloc_container(&type_inf->bufinf, + reqbufs->count); + if (ret == 0 && reqbufs->memory == V4L2_MEMORY_MMAP) + { + kumm_free(type_inf->bufheap); + type_inf->bufheap = kumm_memalign(32, reqbufs->count * buf_size); + if (type_inf->bufheap == NULL) + { + ret = -ENOMEM; + } + } + + leave_critical_section(flags); + return ret; +} + +static int codec_querybuf(FAR struct file *filep, + FAR struct v4l2_buffer *buf) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + FAR codec_type_inf_t *type_inf; + + if (buf == NULL || buf->memory != V4L2_MEMORY_MMAP) + { + return -EINVAL; + } + + type_inf = codec_get_type_inf(cfile, buf->type); + if (type_inf == NULL) + { + return -EINVAL; + } + + if (buf->index >= type_inf->bufinf.container_size) + { + return -EINVAL; + } + + if (V4L2_TYPE_IS_OUTPUT(buf->type)) + { + buf->length = CODEC_OUTPUT_G_BUFSIZE(cmng->codec, cfile->priv); + buf->m.offset = buf->length * buf->index; + } + else + { + buf->length = CODEC_CAPTURE_G_BUFSIZE(cmng->codec, cfile->priv); + buf->m.offset = buf->length * buf->index + CAPTURE_BUF_OFFSET; + } + + if (buf->length == 0) + { + return -EINVAL; + } + + return OK; +} + +static int codec_qbuf(FAR struct file *filep, + FAR struct v4l2_buffer *buf) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + FAR codec_type_inf_t *type_inf; + FAR vbuf_container_t *container; + size_t buf_size; + + if (buf == NULL) + { + return -EINVAL; + } + + type_inf = codec_get_type_inf(cfile, buf->type); + if (type_inf == NULL) + { + return -EINVAL; + } + + container = video_framebuff_get_container(&type_inf->bufinf); + if (container == NULL) + { + vwarn("get container failed\n"); + return -EAGAIN; + } + + memcpy(&container->buf, buf, sizeof(struct v4l2_buffer)); + if (buf->memory == V4L2_MEMORY_MMAP) + { + /* only use userptr inside the container */ + + if (V4L2_TYPE_IS_OUTPUT(buf->type)) + { + buf_size = CODEC_OUTPUT_G_BUFSIZE(cmng->codec, cfile->priv); + } + else + { + buf_size = CODEC_CAPTURE_G_BUFSIZE(cmng->codec, cfile->priv); + } + + if (buf_size == 0) + { + return -EINVAL; + } + + container->buf.length = buf_size; + container->buf.m.userptr = (unsigned long)(type_inf->bufheap + + container->buf.length * buf->index); + } + + video_framebuff_queue_container(&type_inf->bufinf, container); + + if (V4L2_TYPE_IS_OUTPUT(buf->type)) + { + return CODEC_OUTPUT_AVAILABLE(cmng->codec, cfile->priv); + } + else + { + return CODEC_CAPTURE_AVAILABLE(cmng->codec, cfile->priv); + } +} + +static int codec_dqbuf(FAR struct file *filep, + FAR struct v4l2_buffer *buf) +{ + FAR codec_file_t *cfile = filep->f_priv; + FAR codec_type_inf_t *type_inf; + FAR vbuf_container_t *container; + irqstate_t flags; + + if (buf == NULL) + { + return -EINVAL; + } + + type_inf = codec_get_type_inf(cfile, buf->type); + if (type_inf == NULL) + { + return -EINVAL; + } + + flags = enter_critical_section(); + + if (video_framebuff_is_empty(&type_inf->bufinf)) + { + leave_critical_section(flags); + return -EAGAIN; + } + + container = video_framebuff_dq_valid_container(&type_inf->bufinf); + if (container == NULL) + { + leave_critical_section(flags); + return -EAGAIN; + } + + memcpy(buf, &container->buf, sizeof(struct v4l2_buffer)); + video_framebuff_free_container(&type_inf->bufinf, container); + + vinfo("%s dequeue done\n", V4L2_TYPE_IS_OUTPUT(buf->type) ? + "output" : "capture"); + + leave_critical_section(flags); + return OK; +} + +static int codec_s_selection(FAR struct file *filep, + FAR struct v4l2_selection *clip) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + + if (clip == NULL) + { + return -EINVAL; + } + + if (V4L2_TYPE_IS_OUTPUT(clip->type)) + { + return CODEC_OUTPUT_S_SELECTION(cmng->codec, cfile->priv, clip); + } + else + { + return CODEC_CAPTURE_S_SELECTION(cmng->codec, cfile->priv, clip); + } +} + +static int codec_g_selection(FAR struct file *filep, + FAR struct v4l2_selection *clip) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + + if (clip == NULL) + { + return -EINVAL; + } + + if (V4L2_TYPE_IS_OUTPUT(clip->type)) + { + return CODEC_OUTPUT_G_SELECTION(cmng->codec, cfile->priv, clip); + } + else + { + return CODEC_CAPTURE_G_SELECTION(cmng->codec, cfile->priv, clip); + } +} + +static int codec_g_ext_ctrls(FAR struct file *filep, + FAR struct v4l2_ext_controls *ctrls) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + + if (ctrls == NULL) + { + return -EINVAL; + } + + return CODEC_G_EXT_CTRLS(cmng->codec, cfile->priv, ctrls); +} + +static int codec_s_ext_ctrls(FAR struct file *filep, + FAR struct v4l2_ext_controls *ctrls) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + + if (ctrls == NULL) + { + return -EINVAL; + } + + return CODEC_S_EXT_CTRLS(cmng->codec, cfile->priv, ctrls); +} + +static int codec_try_fmt(FAR struct file *filep, + FAR struct v4l2_format *fmt) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + + if (fmt == NULL) + { + return -EINVAL; + } + + if (V4L2_TYPE_IS_OUTPUT(fmt->type)) + { + return CODEC_OUTPUT_TRY_FMT(cmng->codec, cfile->priv, fmt); + } + else + { + return CODEC_CAPTURE_TRY_FMT(cmng->codec, cfile->priv, fmt); + } +} + +static int codec_g_fmt(FAR struct file *filep, + FAR struct v4l2_format *fmt) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + + if (fmt == NULL) + { + return -EINVAL; + } + + if (V4L2_TYPE_IS_OUTPUT(fmt->type)) + { + return CODEC_OUTPUT_G_FMT(cmng->codec, cfile->priv, fmt); + } + else + { + return CODEC_CAPTURE_G_FMT(cmng->codec, cfile->priv, fmt); + } +} + +static int codec_s_fmt(FAR struct file *filep, + FAR struct v4l2_format *fmt) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + + if (fmt == NULL) + { + return -EINVAL; + } + + if (V4L2_TYPE_IS_OUTPUT(fmt->type)) + { + return CODEC_OUTPUT_S_FMT(cmng->codec, cfile->priv, fmt); + } + else + { + return CODEC_CAPTURE_S_FMT(cmng->codec, cfile->priv, fmt); + } +} + +static int codec_g_parm(FAR struct file *filep, + FAR struct v4l2_streamparm *parm) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + + if (parm == NULL) + { + return -EINVAL; + } + + if (V4L2_TYPE_IS_OUTPUT(parm->type)) + { + return CODEC_OUTPUT_G_PARM(cmng->codec, cfile->priv, parm); + } + else + { + return CODEC_CAPTURE_G_PARM(cmng->codec, cfile->priv, parm); + } +} + +static int codec_s_parm(FAR struct file *filep, + FAR struct v4l2_streamparm *parm) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + + if (parm == NULL) + { + return -EINVAL; + } + + if (V4L2_TYPE_IS_OUTPUT(parm->type)) + { + return CODEC_OUTPUT_S_PARM(cmng->codec, cfile->priv, parm); + } + else + { + return CODEC_CAPTURE_S_PARM(cmng->codec, cfile->priv, parm); + } +} + +static int codec_streamon(FAR struct file *filep, + FAR enum v4l2_buf_type *type) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + FAR codec_type_inf_t *type_inf; + + if (type == NULL) + { + return -EINVAL; + } + + type_inf = codec_get_type_inf(cfile, *type); + if (type_inf == NULL) + { + return -EINVAL; + } + + type_inf->buflast = false; + + if (V4L2_TYPE_IS_OUTPUT(*type)) + { + return CODEC_OUTPUT_STREAMON(cmng->codec, cfile->priv); + } + else + { + return CODEC_CAPTURE_STREAMON(cmng->codec, cfile->priv); + } +} + +static int codec_streamoff(FAR struct file *filep, + FAR enum v4l2_buf_type *type) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + FAR codec_type_inf_t *type_inf; + + if (type == NULL) + { + return -EINVAL; + } + + type_inf = codec_get_type_inf(cfile, *type); + if (type_inf == NULL) + { + return -EINVAL; + } + + if (V4L2_TYPE_IS_OUTPUT(*type)) + { + return CODEC_OUTPUT_STREAMOFF(cmng->codec, cfile->priv); + } + else + { + return CODEC_CAPTURE_STREAMOFF(cmng->codec, cfile->priv); + } +} + +int codec_cropcap(FAR struct file *filep, + FAR struct v4l2_cropcap *cropcap) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + + if (cropcap == NULL) + { + return -EINVAL; + } + + if (V4L2_TYPE_IS_OUTPUT(cropcap->type)) + { + return CODEC_OUTPUT_CROPCAP(cmng->codec, cfile->priv, cropcap); + } + else + { + return CODEC_CAPTURE_CROPCAP(cmng->codec, cfile->priv, cropcap); + } +} + +int codec_dqevent(FAR struct file *filep, + FAR struct v4l2_event *event) +{ + FAR codec_file_t *cfile = filep->f_priv; + FAR codec_event_t *cevt; + irqstate_t flags; + + if (event == NULL) + { + return -EINVAL; + } + + flags = enter_critical_section(); + + if (sq_empty(&cfile->event_avail)) + { + leave_critical_section(flags); + return -ENOENT; + } + + cevt = (FAR codec_event_t *)sq_remfirst(&cfile->event_avail); + memcpy(event, &cevt->event, sizeof(struct v4l2_event)); + sq_addlast((FAR sq_entry_t *)cevt, &cfile->event_free); + + leave_critical_section(flags); + return OK; +} + +int codec_subscribe_event(FAR struct file *filep, + FAR struct v4l2_event_subscription *sub) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + + if (sub == NULL) + { + return -EINVAL; + } + + return CODEC_SUBSCRIBE_EVENT(cmng->codec, cfile->priv, sub); +} + +int codec_decoder_cmd(FAR struct file *filep, + FAR struct v4l2_decoder_cmd *cmd) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + + if (cmd == NULL) + { + return -EINVAL; + } + + return CODEC_DECODER_CMD(cmng->codec, cfile->priv, cmd); +} + +int codec_encoder_cmd(FAR struct file *filep, + FAR struct v4l2_encoder_cmd *cmd) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + + if (cmd == NULL) + { + return -EINVAL; + } + + return CODEC_ENCODER_CMD(cmng->codec, cfile->priv, cmd); +} + +/* file operations */ + +static int codec_open(FAR struct file *filep) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct codec_mng_s *cmng = inode->i_private; + FAR struct codec_file_s *cfile; + int ret; + int i; + + cfile = kmm_zalloc(sizeof(struct codec_file_s)); + if (cfile == NULL) + { + return -ENOMEM; + } + + filep->f_priv = cfile; + + ret = CODEC_OPEN(cmng->codec, cfile, &cfile->priv); + if (ret != OK) + { + kmm_free(cfile); + return ret; + } + + sq_init(&cfile->event_avail); + sq_init(&cfile->event_free); + + for (i = 0; i < CODEC_EVENT_COUNT; i++) + { + sq_addlast((FAR sq_entry_t *)&cfile->event_pool[i], + &cfile->event_free); + } + + video_framebuff_init(&cfile->capture_inf.bufinf); + video_framebuff_init(&cfile->output_inf.bufinf); + + return OK; +} + +static int codec_close(FAR struct file *filep) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + + CODEC_CLOSE(cmng->codec, cfile->priv); + + video_framebuff_uninit(&cfile->capture_inf.bufinf); + video_framebuff_uninit(&cfile->output_inf.bufinf); + kumm_free(cfile->capture_inf.bufheap); + kumm_free(cfile->output_inf.bufheap); + kmm_free(cfile); + + return OK; +} + +static int codec_munmap(FAR struct task_group_s *group, + FAR struct mm_map_entry_s *entry, + FAR void *start, size_t length) +{ + return mm_map_remove(get_group_mm(group), entry); +} + +static int codec_mmap(FAR struct file *filep, + FAR struct mm_map_entry_s *map) +{ + FAR struct inode *inode = filep->f_inode; + FAR codec_mng_t *cmng = inode->i_private; + FAR codec_file_t *cfile = filep->f_priv; + FAR codec_type_inf_t *type_inf; + int ret = -EINVAL; + size_t total_size; + size_t buf_size; + + if (map == NULL) + { + return -EINVAL; + } + + if (map->offset < CAPTURE_BUF_OFFSET) + { + type_inf = &cfile->output_inf; + buf_size = CODEC_OUTPUT_G_BUFSIZE(cmng->codec, cfile->priv); + } + else + { + type_inf = &cfile->capture_inf; + map->offset -= CAPTURE_BUF_OFFSET; + buf_size = CODEC_CAPTURE_G_BUFSIZE(cmng->codec, cfile->priv); + } + + if (buf_size == 0) + { + return -EINVAL; + } + + total_size = type_inf->bufinf.container_size * buf_size; + if (map->offset >= 0 && map->offset < total_size && + map->length && map->offset + map->length <= total_size) + { + map->vaddr = type_inf->bufheap + map->offset; + map->munmap = codec_munmap; + ret = mm_map_add(get_current_mm(), map); + } + + return ret; +} + +static int codec_poll(FAR struct file *filep, + FAR struct pollfd *fds, bool setup) +{ + FAR codec_file_t *cfile = filep->f_priv; + pollevent_t eventset = 0; + irqstate_t flags; + + flags = enter_critical_section(); + + if (setup) + { + if (cfile->fds == NULL) + { + cfile->fds = fds; + fds->priv = &cfile->fds; + + if (!video_framebuff_is_empty(&cfile->output_inf.bufinf)) + { + eventset |= POLLOUT; + } + + if (cfile->capture_inf.buflast || + !video_framebuff_is_empty(&cfile->capture_inf.bufinf)) + { + eventset |= POLLIN; + } + + if (!sq_empty(&cfile->event_avail)) + { + eventset |= POLLPRI; + } + + if (eventset > 0) + { + poll_notify(&cfile->fds, 1, eventset); + } + } + else + { + leave_critical_section(flags); + return -EBUSY; + } + } + else if (fds->priv) + { + cfile->fds = NULL; + fds->priv = NULL; + } + + leave_critical_section(flags); + return OK; +} + +static FAR struct v4l2_buffer *codec_get_buf(FAR codec_type_inf_t *type_inf) +{ + FAR vbuf_container_t *container; + + container = video_framebuff_get_vacant_container(&type_inf->bufinf); + if (container == NULL) + { + vinfo("No buffer available\n"); + return NULL; + } + + return &container->buf; +} + +static int codec_put_buf(FAR codec_file_t *cfile, + FAR codec_type_inf_t *type_inf, + FAR struct v4l2_buffer *buf) +{ + if (cfile == NULL || type_inf == NULL || buf == NULL) + { + return -EINVAL; + } + + if (buf->flags & V4L2_BUF_FLAG_LAST) + { + type_inf->buflast = true; + } + + video_framebuff_capture_done(&type_inf->bufinf); + poll_notify(&cfile->fds, 1, + V4L2_TYPE_IS_OUTPUT(buf->type) ? POLLOUT : POLLIN); + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int codec_register(FAR const char *devpath, FAR struct codec_s *codec) +{ + FAR struct codec_mng_s *cmng; + int ret; + + if (devpath == NULL || codec == NULL) + { + return -EINVAL; + } + + cmng = kmm_zalloc(sizeof(struct codec_mng_s)); + if (cmng == NULL) + { + verr("Failed to allocate codec instance\n"); + return -ENOMEM; + } + + cmng->v4l2.vops = &g_codec_vops; + cmng->v4l2.fops = &g_codec_fops; + cmng->codec = codec; + + /* Register the character driver */ + + ret = video_register(devpath, (FAR struct v4l2_s *)cmng); + if (ret < 0) + { + verr("Failed to register driver: %d\n", ret); + kmm_free(cmng); + return ret; + } + + return OK; +} + +int codec_unregister(FAR const char *devpath) +{ + return unregister_driver(devpath); +} + +FAR struct v4l2_buffer *codec_output_get_buf(void *cookie) +{ + FAR codec_file_t *cfile = cookie; + + return codec_get_buf(&cfile->output_inf); +} + +FAR struct v4l2_buffer *codec_capture_get_buf(void *cookie) +{ + FAR codec_file_t *cfile = cookie; + + return codec_get_buf(&cfile->capture_inf); +} + +int codec_output_put_buf(FAR void *cookie, FAR struct v4l2_buffer *buf) +{ + FAR codec_file_t *cfile = cookie; + + return codec_put_buf(cfile, &cfile->output_inf, buf); +} + +int codec_capture_put_buf(FAR void *cookie, FAR struct v4l2_buffer *buf) +{ + FAR codec_file_t *cfile = cookie; + + return codec_put_buf(cfile, &cfile->capture_inf, buf); +} + +int codec_queue_event(FAR void *cookie, FAR struct v4l2_event *evt) +{ + FAR codec_file_t *cfile = cookie; + FAR codec_event_t *cevt; + irqstate_t flags; + + flags = enter_critical_section(); + + cevt = (FAR codec_event_t *)sq_remfirst(&cfile->event_free); + if (cevt == NULL) + { + leave_critical_section(flags); + return -EINVAL; + } + + memcpy(&cevt->event, evt, sizeof(struct v4l2_event)); + sq_addlast((FAR sq_entry_t *)cevt, &cfile->event_avail); + + poll_notify(&cfile->fds, 1, POLLPRI); + leave_critical_section(flags); + + return OK; +} + diff --git a/drivers/video/video.c b/drivers/video/video.c deleted file mode 100644 index 105e2d87458f0..0000000000000 --- a/drivers/video/video.c +++ /dev/null @@ -1,3529 +0,0 @@ -/**************************************************************************** - * drivers/video/video.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include - -#include "video_framebuff.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define MAX_VIDEO_FILE_PATH (32) -#define MAX_VIDEO_FMT (2) -#define VIDEO_FMT_MAIN (0) -#define VIDEO_FMT_SUB (1) - -#define VIDEO_REMAINING_CAPNUM_INFINITY (-1) - -#define VIDEO_ID(x, y) (((x) << 16) | (y)) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -enum video_state_e -{ - VIDEO_STATE_STREAMOFF = 0, /* Capture trigger event is not received */ - VIDEO_STATE_STREAMON = 1, /* Capture trigger event is received, - * but capture is not operated. - */ - VIDEO_STATE_CAPTURE = 2, /* On capture */ -}; - -enum video_state_transition_cause -{ - CAUSE_VIDEO_STOP = 0, /* Stop capture event for video stream */ - CAUSE_VIDEO_START = 1, /* Start capture event for video stream */ - CAUSE_VIDEO_DQBUF = 2, /* DQBUF timing for video stream */ - CAUSE_STILL_STOP = 3, /* Stop capture event for still stream */ - CAUSE_STILL_START = 4, /* Start capture event for still stream */ -}; - -enum video_waitend_cause_e -{ - VIDEO_WAITEND_CAUSE_CAPTUREDONE = 0, - VIDEO_WAITEND_CAUSE_DQCANCEL = 1, - VIDEO_WAITEND_CAUSE_STILLSTOP = 2, -}; - -struct video_wait_capture_s -{ - sem_t dqbuf_wait_flg; - - /* Save container which capture is done */ - - FAR vbuf_container_t *done_container; - enum video_waitend_cause_e waitend_cause; -}; - -typedef struct video_wait_capture_s video_wait_capture_t; - -struct video_format_s -{ - uint16_t width; - uint16_t height; - uint32_t pixelformat; -}; - -typedef struct video_format_s video_format_t; - -struct video_type_inf_s -{ - mutex_t lock_state; - enum video_state_e state; - int32_t remaining_capnum; - video_wait_capture_t wait_capture; - uint8_t nr_fmt; - video_format_t fmt[MAX_VIDEO_FMT]; - struct v4l2_rect clip; - struct v4l2_fract frame_interval; - video_framebuff_t bufinf; - FAR uint8_t *bufheap; /* for V4L2_MEMORY_MMAP buffers */ - FAR struct pollfd *fds; - uint32_t seqnum; -}; - -typedef struct video_type_inf_s video_type_inf_t; - -struct video_scene_params_s -{ - uint8_t mode; /* enum v4l2_scene_mode */ - - int32_t brightness; - int32_t contrast; - int32_t saturation; - int32_t hue; - bool awb; - int32_t red; - int32_t blue; - int32_t gamma; - uint32_t gamma_curve_sz; - uint8_t *gamma_curve; - int32_t ev; - bool hflip_video; - bool vflip_video; - bool hflip_still; - bool vflip_still; - int32_t sharpness; - enum v4l2_colorfx colorfx; - bool auto_brightness; - int32_t rotate; - enum v4l2_exposure_auto_type ae; - int32_t exposure_time; - int32_t focus; - bool af; - int32_t zoom; - int32_t iris; - enum v4l2_auto_n_preset_white_balance wb; - int32_t wdr; - bool stabilization; - enum v4l2_iso_sensitivity_auto_type iso_auto; - int32_t iso; - enum v4l2_exposure_metering meter; - int32_t spot_pos; - int32_t threea_lock; - enum v4l2_flash_led_mode led; - int32_t jpeg_quality; -}; - -typedef struct video_scene_params_s video_scene_params_t; - -struct video_parameter_name_s -{ - uint32_t id; - const char *name; -}; - -typedef struct video_parameter_name_s video_parameter_name_t; - -struct video_mng_s -{ - /* Parameter of video_initialize() */ - - FAR char *devpath; - mutex_t lock_open_num; - uint8_t open_num; - video_type_inf_t video_inf; - video_type_inf_t still_inf; - FAR struct imgdata_s *imgdata; - FAR struct imgsensor_s *imgsensor; - enum v4l2_scene_mode video_scene_mode; - uint8_t video_scence_num; - FAR video_scene_params_t *video_scene_param[V4L2_SCENE_MODE_MAX]; -#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS - bool unlinked; -#endif -}; - -typedef struct video_mng_s video_mng_t; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Character driver methods. */ - -static int video_open(FAR struct file *filep); -static int video_close(FAR struct file *filep); -static ssize_t video_read(FAR struct file *filep, - FAR char *buffer, size_t buflen); -static ssize_t video_write(FAR struct file *filep, - FAR const char *buffer, size_t buflen); -static int video_ioctl(FAR struct file *filep, int cmd, unsigned long arg); -static int video_mmap(FAR struct file *filep, - FAR struct mm_map_entry_s *map); -static int video_poll(FAR struct file *filep, FAR struct pollfd *fds, - bool setup); -#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS -static int video_unlink(FAR struct inode *inode); -#endif -/* Common function */ - -static FAR video_type_inf_t * -get_video_type_inf(FAR video_mng_t *vmng, uint8_t type); -static enum video_state_e -estimate_next_video_state(FAR video_mng_t *vmng, - enum video_state_transition_cause cause); -static void change_video_state(FAR video_mng_t *vmng, - enum video_state_e next_state); -static bool is_taking_still_picture(FAR video_mng_t *vmng); -static bool is_bufsize_sufficient(FAR video_mng_t *vmng, uint32_t bufsize); -static void cleanup_resources(FAR video_mng_t *vmng); -static bool is_sem_waited(FAR sem_t *sem); -static int save_scene_param(FAR video_mng_t *vmng, - enum v4l2_scene_mode mode, - uint32_t id, - struct v4l2_ext_control *control); -static int video_complete_capture(uint8_t err_code, uint32_t datasize, - FAR const struct timeval *ts, - FAR void *arg); -static int validate_frame_setting(FAR video_mng_t *vmng, - enum v4l2_buf_type type, - uint8_t nr_fmt, - FAR video_format_t *vfmt, - FAR struct v4l2_rect *clip, - FAR struct v4l2_fract *interval); -static size_t get_bufsize(FAR video_format_t *vf); - -/* Internal function for each cmds of ioctl */ - -static int video_querycap(FAR video_mng_t *vmng, - FAR struct v4l2_capability *cap); -static int video_g_input(FAR int *num); -static int video_enum_input(FAR video_mng_t *vmng, - FAR struct v4l2_input *input); -static int video_reqbufs(FAR struct video_mng_s *vmng, - FAR struct v4l2_requestbuffers *reqbufs); -static int video_qbuf(FAR struct video_mng_s *vmng, - FAR struct v4l2_buffer *buf); -static int video_dqbuf(FAR struct video_mng_s *vmng, - FAR struct v4l2_buffer *buf, - int oflags); -static int video_cancel_dqbuf(FAR struct video_mng_s *vmng, - enum v4l2_buf_type type); -static int video_g_fmt(FAR struct video_mng_s *priv, - FAR struct v4l2_format *fmt); -static int video_s_fmt(FAR struct video_mng_s *priv, - FAR struct v4l2_format *fmt); -static int video_try_fmt(FAR struct video_mng_s *priv, - FAR struct v4l2_format *v4l2); -static int video_g_parm(FAR struct video_mng_s *priv, - FAR struct v4l2_streamparm *parm); -static int video_s_parm(FAR struct video_mng_s *priv, - FAR struct v4l2_streamparm *parm); -static int video_streamon(FAR struct video_mng_s *vmng, - FAR enum v4l2_buf_type *type); -static int video_streamoff(FAR struct video_mng_s *vmng, - FAR enum v4l2_buf_type *type); -static int video_do_halfpush(FAR struct video_mng_s *priv, - bool enable); -static int video_takepict_start(FAR struct video_mng_s *vmng, - int32_t capture_num); -static int video_takepict_stop(FAR struct video_mng_s *vmng, - bool halfpush); -static int video_queryctrl(FAR video_mng_t *vmng, - FAR struct v4l2_queryctrl *ctrl); -static int video_query_ext_ctrl(FAR video_mng_t *vmng, - FAR struct v4l2_query_ext_ctrl *ctrl); -static int video_querymenu(FAR video_mng_t *vmng, - FAR struct v4l2_querymenu *menu); -static int video_g_ctrl(FAR struct video_mng_s *priv, - FAR struct v4l2_control *ctrl); -static int video_s_ctrl(FAR struct video_mng_s *priv, - FAR struct v4l2_control *ctrl); -static int video_g_ext_ctrls(FAR struct video_mng_s *priv, - FAR struct v4l2_ext_controls *ctrls); -static int video_s_ext_ctrls(FAR struct video_mng_s *priv, - FAR struct v4l2_ext_controls *ctrls); -static int video_query_ext_ctrl_scene(FAR video_mng_t *vmng, - FAR struct v4s_query_ext_ctrl_scene *ctrl); -static int video_querymenu_scene(FAR video_mng_t *vmng, - FAR struct v4s_querymenu_scene *menu); -static int video_g_ext_ctrls_scene(FAR video_mng_t *vmng, - FAR struct v4s_ext_controls_scene *ctrls); -static int video_s_ext_ctrls_scene(FAR video_mng_t *vmng, - FAR struct v4s_ext_controls_scene *ctrls); - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static const struct file_operations g_video_fops = -{ - video_open, /* open */ - video_close, /* close */ - video_read, /* read */ - video_write, /* write */ - NULL, /* seek */ - video_ioctl, /* ioctl */ - video_mmap, /* mmap */ - NULL, /* truncate */ - video_poll, /* poll */ -#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS - video_unlink, /* unlink */ -#endif -}; - -static const video_parameter_name_t g_video_parameter_name[] = -{ - {IMGSENSOR_ID_BRIGHTNESS, "Brightness"}, - {IMGSENSOR_ID_CONTRAST, "Contrast"}, - {IMGSENSOR_ID_SATURATION, "Saturation"}, - {IMGSENSOR_ID_HUE, "Hue"}, - {IMGSENSOR_ID_AUTO_WHITE_BALANCE, "Automatic white balance"}, - {IMGSENSOR_ID_RED_BALANCE, "Red balance"}, - {IMGSENSOR_ID_BLUE_BALANCE, "Blue balance"}, - {IMGSENSOR_ID_GAMMA, "Gamma value"}, - {IMGSENSOR_ID_GAMMA_CURVE, "Gamma adjustment(curve)"}, - {IMGSENSOR_ID_EXPOSURE, "Exposure value"}, - {IMGSENSOR_ID_HFLIP_VIDEO, "Mirror horizontally(VIDEO)"}, - {IMGSENSOR_ID_VFLIP_VIDEO, "Mirror vertically(VIDEO)"}, - {IMGSENSOR_ID_HFLIP_STILL, "Mirror horizontally(STILL)"}, - {IMGSENSOR_ID_VFLIP_STILL, "Mirror vertically(STILL)"}, - {IMGSENSOR_ID_SHARPNESS, "Sharpness"}, - {IMGSENSOR_ID_COLOR_KILLER, "Color killer"}, - {IMGSENSOR_ID_COLORFX, "Color effect"}, - {IMGSENSOR_ID_AUTOBRIGHTNESS, "Auto brightness"}, - {IMGSENSOR_ID_ROTATE, "Rotate"}, - {IMGSENSOR_ID_EXPOSURE_AUTO, "Auto Exposure"}, - {IMGSENSOR_ID_EXPOSURE_ABSOLUTE, "Exposure time(100 usec)"}, - {IMGSENSOR_ID_FOCUS_ABSOLUTE, "Focus(absolute value)"}, - {IMGSENSOR_ID_FOCUS_RELATIVE, "Focus(relative value)"}, - {IMGSENSOR_ID_FOCUS_AUTO, "Continuous Auto Focus"}, - {IMGSENSOR_ID_ZOOM_ABSOLUTE, "Zoom(absolute value)"}, - {IMGSENSOR_ID_ZOOM_RELATIVE, "Zoom(relative value)"}, - {IMGSENSOR_ID_ZOOM_CONTINUOUS, "Continuous zoom"}, - {IMGSENSOR_ID_IRIS_ABSOLUTE, "Iris(absolute value)"}, - {IMGSENSOR_ID_IRIS_RELATIVE, "Iris(relative value)"}, - {IMGSENSOR_ID_AUTO_N_PRESET_WB, "Preset white balance"}, - {IMGSENSOR_ID_WIDE_DYNAMIC_RANGE, "Wide dynamic range"}, - {IMGSENSOR_ID_IMG_STABILIZATION, "Image stabilization"}, - {IMGSENSOR_ID_ISO_SENSITIVITY, "ISO sensitivity"}, - {IMGSENSOR_ID_ISO_SENSITIVITY_AUTO, "Automatic ISO sensitivity"}, - {IMGSENSOR_ID_EXPOSURE_METERING, "Photometry"}, - {IMGSENSOR_ID_SPOT_POSITION, "Spot position"}, - {IMGSENSOR_ID_3A_LOCK, "Lock AWB/AE"}, - {IMGSENSOR_ID_AUTO_FOCUS_START, "Start single Auto Focus"}, - {IMGSENSOR_ID_AUTO_FOCUS_STOP, "Stop single Auto Focus"}, - {IMGSENSOR_ID_3A_PARAMETER, "3A parameter"}, - {IMGSENSOR_ID_3A_STATUS, "3A status"}, - {IMGSENSOR_ID_FLASH_LED_MODE, "LED mode"}, - {IMGSENSOR_ID_JPEG_QUALITY, "JPEG compression quality"} -}; - -static FAR struct imgsensor_s **g_video_registered_sensor = NULL; -static size_t g_video_registered_sensor_num; -static FAR struct imgdata_s *g_video_data = NULL; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -static FAR video_type_inf_t * -get_video_type_inf(FAR video_mng_t *vmng, uint8_t type) -{ - FAR video_type_inf_t *type_inf; - - switch (type) - { - case V4L2_BUF_TYPE_VIDEO_CAPTURE: - type_inf = &vmng->video_inf; - break; - - case V4L2_BUF_TYPE_STILL_CAPTURE: - type_inf = &vmng->still_inf; - break; - - default: /* Error case */ - type_inf = NULL; - break; - } - - return type_inf; -} - -static enum video_state_e -estimate_next_video_state(FAR video_mng_t *vmng, - enum video_state_transition_cause cause) -{ - enum video_state_e current_state = vmng->video_inf.state; - - switch (cause) - { - case CAUSE_VIDEO_STOP: - return VIDEO_STATE_STREAMOFF; - - case CAUSE_VIDEO_START: - if (is_taking_still_picture(vmng)) - { - return VIDEO_STATE_STREAMON; - } - else - { - return VIDEO_STATE_CAPTURE; - } - - case CAUSE_STILL_STOP: - if (current_state == VIDEO_STATE_STREAMON) - { - return VIDEO_STATE_CAPTURE; - } - else - { - return current_state; - } - - case CAUSE_STILL_START: - if (current_state == VIDEO_STATE_CAPTURE) - { - return VIDEO_STATE_STREAMON; - } - else - { - return current_state; - } - - case CAUSE_VIDEO_DQBUF: - if (current_state == VIDEO_STATE_STREAMON && - !is_taking_still_picture(vmng)) - { - return VIDEO_STATE_CAPTURE; - } - else - { - return current_state; - } - - default: - return current_state; - } -} - -static void convert_to_imgdatafmt(FAR video_format_t *video, - FAR imgdata_format_t *data) -{ - ASSERT(video && data); - - data->width = video->width; - data->height = video->height; - switch (video->pixelformat) - { - case V4L2_PIX_FMT_NV12: - data->pixelformat = IMGDATA_PIX_FMT_NV12; - break; - - case V4L2_PIX_FMT_YUV420: - data->pixelformat = IMGDATA_PIX_FMT_YUV420P; - break; - - case V4L2_PIX_FMT_YUYV: - data->pixelformat = IMGDATA_PIX_FMT_YUYV; - break; - - case V4L2_PIX_FMT_UYVY: - data->pixelformat = IMGDATA_PIX_FMT_UYVY; - break; - - case V4L2_PIX_FMT_RGB565: - data->pixelformat = IMGDATA_PIX_FMT_RGB565; - break; - - case V4L2_PIX_FMT_JPEG: - data->pixelformat = IMGDATA_PIX_FMT_JPEG; - break; - - default: /* V4L2_PIX_FMT_JPEG_WITH_SUBIMG */ - data->pixelformat = IMGDATA_PIX_FMT_JPEG_WITH_SUBIMG; - break; - } -} - -static void convert_to_imgsensorfmt(FAR video_format_t *video, - FAR imgsensor_format_t *sensor) -{ - ASSERT(video && sensor); - - sensor->width = video->width; - sensor->height = video->height; - switch (video->pixelformat) - { - case V4L2_PIX_FMT_NV12: - sensor->pixelformat = IMGSENSOR_PIX_FMT_NV12; - break; - - case V4L2_PIX_FMT_YUV420: - sensor->pixelformat = IMGSENSOR_PIX_FMT_YUV420P; - break; - - case V4L2_PIX_FMT_YUYV: - sensor->pixelformat = IMGSENSOR_PIX_FMT_YUYV; - break; - - case V4L2_PIX_FMT_UYVY: - sensor->pixelformat = IMGSENSOR_PIX_FMT_UYVY; - break; - - case V4L2_PIX_FMT_RGB565: - sensor->pixelformat = IMGSENSOR_PIX_FMT_RGB565; - break; - - case V4L2_PIX_FMT_JPEG: - sensor->pixelformat = IMGSENSOR_PIX_FMT_JPEG; - break; - - default: /* V4L2_PIX_FMT_JPEG_WITH_SUBIMG */ - sensor->pixelformat = IMGSENSOR_PIX_FMT_JPEG_WITH_SUBIMG; - break; - } -} - -static void convert_to_imgdatainterval(FAR struct v4l2_fract *video, - FAR imgdata_interval_t *data) -{ - ASSERT(video && data); - - data->numerator = video->numerator; - data->denominator = video->denominator; -} - -static void convert_to_imgsensorinterval(FAR struct v4l2_fract *video, - FAR imgsensor_interval_t *sensor) -{ - ASSERT(video && sensor); - - sensor->numerator = video->numerator; - sensor->denominator = video->denominator; -} - -static bool is_clipped(FAR struct v4l2_rect *clip) -{ - bool ret = false; - - if (clip) - { - if (clip->left != 0 || clip->top != 0 || - clip->width != 0 || clip->height != 0) - { - ret = true; - } - } - - return ret; -} - -static void get_clipped_format(uint8_t nr_fmt, - FAR video_format_t *fmt, - FAR struct v4l2_rect *clip, - FAR video_format_t *c_fmt) -{ - DEBUGASSERT(fmt && c_fmt); - - if (is_clipped(clip)) - { - c_fmt[VIDEO_FMT_MAIN].width = clip->width; - c_fmt[VIDEO_FMT_MAIN].height = clip->height; - c_fmt[VIDEO_FMT_MAIN].pixelformat = fmt[VIDEO_FMT_MAIN].pixelformat; - - if (nr_fmt > 1) - { - /* Clipped size of thumbnail is - * small as ratio of main size and thumbnal size. - */ - - memcpy(&c_fmt[VIDEO_FMT_SUB], - &fmt[VIDEO_FMT_SUB], - sizeof(video_format_t)); - - c_fmt[VIDEO_FMT_SUB].width = - (uint32_t)c_fmt[VIDEO_FMT_SUB].width * - clip->width / fmt[VIDEO_FMT_MAIN].width; - - c_fmt[VIDEO_FMT_SUB].height = - (uint32_t)c_fmt[VIDEO_FMT_SUB].height * - clip->height / fmt[VIDEO_FMT_MAIN].height; - } - } - else - { - memcpy(c_fmt, fmt, nr_fmt * sizeof(video_format_t)); - } -} - -static int start_capture(FAR video_mng_t *vmng, - enum v4l2_buf_type type, - uint8_t nr_fmt, - FAR video_format_t *fmt, - FAR struct v4l2_rect *clip, - FAR struct v4l2_fract *interval, - uintptr_t bufaddr, uint32_t bufsize) -{ - video_format_t c_fmt[MAX_VIDEO_FMT]; - imgdata_format_t df[MAX_VIDEO_FMT]; - imgsensor_format_t sf[MAX_VIDEO_FMT]; - imgdata_interval_t di; - imgsensor_interval_t si; - - ASSERT(fmt && interval && vmng->imgsensor && vmng->imgdata); - - get_clipped_format(nr_fmt, fmt, clip, c_fmt); - - convert_to_imgdatafmt(&c_fmt[VIDEO_FMT_MAIN], &df[IMGDATA_FMT_MAIN]); - convert_to_imgdatafmt(&c_fmt[VIDEO_FMT_SUB], &df[IMGDATA_FMT_SUB]); - convert_to_imgdatainterval(interval, &di); - convert_to_imgsensorfmt(&fmt[VIDEO_FMT_MAIN], &sf[IMGSENSOR_FMT_MAIN]); - convert_to_imgsensorfmt(&fmt[VIDEO_FMT_SUB], &sf[IMGSENSOR_FMT_SUB]); - convert_to_imgsensorinterval(interval, &si); - - IMGDATA_SET_BUF(vmng->imgdata, - nr_fmt, df, (FAR uint8_t *)bufaddr, bufsize); - IMGDATA_START_CAPTURE(vmng->imgdata, - nr_fmt, df, &di, video_complete_capture, vmng); - IMGSENSOR_START_CAPTURE(vmng->imgsensor, - type == V4L2_BUF_TYPE_VIDEO_CAPTURE ? - IMGSENSOR_STREAM_TYPE_VIDEO : IMGSENSOR_STREAM_TYPE_STILL, - nr_fmt, sf, &si); - return OK; -} - -static void stop_capture(FAR video_mng_t *vmng, enum v4l2_buf_type type) -{ - ASSERT(vmng->imgsensor && vmng->imgdata); - - IMGDATA_STOP_CAPTURE(vmng->imgdata); - IMGSENSOR_STOP_CAPTURE(vmng->imgsensor, - type == V4L2_BUF_TYPE_VIDEO_CAPTURE ? - IMGSENSOR_STREAM_TYPE_VIDEO : IMGSENSOR_STREAM_TYPE_STILL); -} - -static void change_video_state(FAR video_mng_t *vmng, - enum video_state_e next_state) -{ - enum video_state_e current_state = vmng->video_inf.state; - enum video_state_e updated_next_state = next_state; - - if (current_state != VIDEO_STATE_CAPTURE && - next_state == VIDEO_STATE_CAPTURE) - { - FAR vbuf_container_t *container = - video_framebuff_get_vacant_container(&vmng->video_inf.bufinf); - if (container != NULL) - { - vmng->video_inf.seqnum = 0; - start_capture(vmng, - V4L2_BUF_TYPE_VIDEO_CAPTURE, - vmng->video_inf.nr_fmt, - vmng->video_inf.fmt, - &vmng->video_inf.clip, - &vmng->video_inf.frame_interval, - container->buf.m.userptr, - container->buf.length); - } - else - { - updated_next_state = VIDEO_STATE_STREAMON; - } - } - else if (current_state == VIDEO_STATE_CAPTURE && - next_state != VIDEO_STATE_CAPTURE) - { - stop_capture(vmng, V4L2_BUF_TYPE_VIDEO_CAPTURE); - } - - vmng->video_inf.state = updated_next_state; -} - -static bool is_taking_still_picture(FAR video_mng_t *vmng) -{ - return vmng->still_inf.state == VIDEO_STATE_STREAMON || - vmng->still_inf.state == VIDEO_STATE_CAPTURE; -} - -static bool is_bufsize_sufficient(FAR video_mng_t *vmng, uint32_t bufsize) -{ - /* Depend on format, frame size, and JPEG compression quality */ - - return true; -} - -static void initialize_frame_setting(FAR uint8_t *nr_fmt, - FAR video_format_t *fmt, - FAR struct v4l2_fract *interval) -{ - ASSERT(nr_fmt && fmt && interval); - - /* Initial setting : QVGA YUV4:2:2 15FPS */ - - *nr_fmt = 1; - fmt[VIDEO_FMT_MAIN].width = VIDEO_HSIZE_QVGA; - fmt[VIDEO_FMT_MAIN].height = VIDEO_VSIZE_QVGA; - fmt[VIDEO_FMT_MAIN].pixelformat = V4L2_PIX_FMT_UYVY; - interval->denominator = 15; - interval->numerator = 1; -} - -static void initialize_streamresources(FAR video_type_inf_t *type_inf) -{ - memset(type_inf, 0, sizeof(video_type_inf_t)); - type_inf->remaining_capnum = VIDEO_REMAINING_CAPNUM_INFINITY; - nxmutex_init(&type_inf->lock_state); - nxsem_init(&type_inf->wait_capture.dqbuf_wait_flg, 0, 0); - initialize_frame_setting(&type_inf->nr_fmt, - type_inf->fmt, - &type_inf->frame_interval); - video_framebuff_init(&type_inf->bufinf); -} - -static int32_t get_default_value(FAR video_mng_t *vmng, uint32_t id) -{ - imgsensor_supported_value_t value; - int ret; - - if (vmng->imgsensor == NULL) - { - /* Don't care(unsupported parameter) */ - - return 0; - } - - ret = IMGSENSOR_GET_SUPPORTED_VALUE(vmng->imgsensor, id, &value); - if (ret != OK) - { - /* Don't care(unsupported parameter) */ - - return 0; - } - - switch (value.type) - { - case IMGSENSOR_CTRL_TYPE_INTEGER_MENU: - return value.u.discrete.default_value; - - case IMGSENSOR_CTRL_TYPE_U8: - case IMGSENSOR_CTRL_TYPE_U16: - case IMGSENSOR_CTRL_TYPE_U32: - - /* Don't care */ - - return 0; - - default: - return value.u.range.default_value; - } -} - -static int32_t initialize_scene_gamma(FAR video_mng_t *vmng, uint8_t **gamma) -{ - imgsensor_supported_value_t sup_val; - imgsensor_value_t val; - int32_t sz; - int ret; - - *gamma = NULL; - - ASSERT(vmng->imgsensor); - - ret = IMGSENSOR_GET_SUPPORTED_VALUE(vmng->imgsensor, - IMGSENSOR_ID_GAMMA_CURVE, &sup_val); - if (ret != OK) - { - /* Unsupported parameter */ - - return 0; - } - - switch (sup_val.type) - { - case IMGSENSOR_CTRL_TYPE_U8: - sz = sup_val.u.elems.nr_elems * sizeof(uint8_t); - if (sz / sizeof(uint8_t) != sup_val.u.elems.nr_elems) - { - /* Multiplication overflow */ - - return 0; - } - - break; - - case IMGSENSOR_CTRL_TYPE_U16: - sz = sup_val.u.elems.nr_elems * sizeof(uint16_t); - if (sz / sizeof(uint16_t) != sup_val.u.elems.nr_elems) - { - /* Multiplication overflow */ - - return 0; - } - - break; - - default: /* IMGSENSOR_CTRL_TYPE_U32 */ - sz = sup_val.u.elems.nr_elems * sizeof(uint32_t); - if (sz / sizeof(uint32_t) != sup_val.u.elems.nr_elems) - { - /* Multiplication overflow */ - - return 0; - } - - break; - } - - *gamma = kmm_malloc(sz); - val.p_u8 = (FAR uint8_t *)*gamma; - IMGSENSOR_GET_VALUE(vmng->imgsensor, IMGSENSOR_ID_GAMMA_CURVE, sz, &val); - return sz; -} - -static int initialize_scene_parameter(FAR video_mng_t *vmng, - enum v4l2_scene_mode mode, - video_scene_params_t **vsp) -{ - FAR video_scene_params_t *sp = kmm_malloc(sizeof(video_scene_params_t)); - if (!sp) - { - return -ENOMEM; - } - - sp->brightness = get_default_value(vmng, IMGSENSOR_ID_BRIGHTNESS); - sp->contrast = get_default_value(vmng, IMGSENSOR_ID_CONTRAST); - sp->saturation = get_default_value(vmng, IMGSENSOR_ID_SATURATION); - sp->hue = get_default_value(vmng, IMGSENSOR_ID_HUE); - sp->awb = get_default_value(vmng, - IMGSENSOR_ID_AUTO_WHITE_BALANCE); - sp->red = get_default_value(vmng, IMGSENSOR_ID_RED_BALANCE); - sp->blue = get_default_value(vmng, IMGSENSOR_ID_BLUE_BALANCE); - sp->gamma = get_default_value(vmng, IMGSENSOR_ID_GAMMA); - sp->gamma_curve_sz = initialize_scene_gamma(vmng, &sp->gamma_curve); - sp->ev = get_default_value(vmng, IMGSENSOR_ID_EXPOSURE); - sp->hflip_video = get_default_value(vmng, IMGSENSOR_ID_HFLIP_VIDEO); - sp->vflip_video = get_default_value(vmng, IMGSENSOR_ID_VFLIP_VIDEO); - sp->hflip_still = get_default_value(vmng, IMGSENSOR_ID_HFLIP_STILL); - sp->vflip_still = get_default_value(vmng, IMGSENSOR_ID_VFLIP_STILL); - sp->sharpness = get_default_value(vmng, IMGSENSOR_ID_SHARPNESS); - sp->colorfx = get_default_value(vmng, IMGSENSOR_ID_COLORFX); - sp->auto_brightness = get_default_value(vmng, IMGSENSOR_ID_AUTOBRIGHTNESS); - sp->rotate = get_default_value(vmng, IMGSENSOR_ID_ROTATE); - sp->ae = get_default_value(vmng, IMGSENSOR_ID_EXPOSURE_AUTO); - sp->exposure_time = get_default_value(vmng, - IMGSENSOR_ID_EXPOSURE_ABSOLUTE); - sp->focus = get_default_value(vmng, IMGSENSOR_ID_FOCUS_ABSOLUTE); - sp->af = get_default_value(vmng, IMGSENSOR_ID_FOCUS_AUTO); - sp->zoom = get_default_value(vmng, IMGSENSOR_ID_ZOOM_ABSOLUTE); - sp->iris = get_default_value(vmng, IMGSENSOR_ID_IRIS_ABSOLUTE); - sp->wb = get_default_value(vmng, - IMGSENSOR_ID_AUTO_N_PRESET_WB); - sp->wdr = get_default_value(vmng, - IMGSENSOR_ID_WIDE_DYNAMIC_RANGE); - sp->stabilization = get_default_value(vmng, - IMGSENSOR_ID_IMG_STABILIZATION); - sp->iso_auto = get_default_value(vmng, - IMGSENSOR_ID_ISO_SENSITIVITY_AUTO); - sp->iso = get_default_value(vmng, - IMGSENSOR_ID_ISO_SENSITIVITY); - sp->meter = get_default_value(vmng, - IMGSENSOR_ID_EXPOSURE_METERING); - sp->threea_lock = get_default_value(vmng, IMGSENSOR_ID_3A_LOCK); - sp->led = get_default_value(vmng, IMGSENSOR_ID_FLASH_LED_MODE); - sp->jpeg_quality = get_default_value(vmng, IMGSENSOR_ID_JPEG_QUALITY); - - *vsp = sp; - - return OK; -} - -static void initialize_scenes_parameter(FAR video_mng_t *vmng) -{ - memset(vmng->video_scene_param, - 0, sizeof(vmng->video_scene_param)); - - initialize_scene_parameter(vmng, V4L2_SCENE_MODE_NONE, - &vmng->video_scene_param[vmng->video_scence_num++]); -#ifdef CONFIG_VIDEO_SCENE_BACKLIGHT - initialize_scene_parameter(vmng, V4L2_SCENE_MODE_BACKLIGHT, - &vmng->video_scene_param[vmng->video_scence_num++]); -#endif /* CONFIG_VIDEO_SCENE_BACKLIGHT */ -#ifdef CONFIG_VIDEO_SCENE_BEACHSNOW - initialize_scene_parameter(vmng, CONFIG_VIDEO_SCENE_BEACHSNOW, - &vmng->video_scene_param[vmng->video_scence_num++]); -#endif /* CONFIG_VIDEO_SCENE_BEACHSNOW */ -#ifdef CONFIG_VIDEO_SCENE_CANDLELIGHT - initialize_scene_parameter(vmng, CONFIG_VIDEO_SCENE_CANDLELIGHT, - &vmng->video_scene_param[vmng->video_scence_num++]); -#endif /* CONFIG_VIDEO_SCENE_CANDLELIGHT */ -#ifdef CONFIG_VIDEO_SCENE_DAWNDUSK - initialize_scene_parameter(vmng, CONFIG_VIDEO_SCENE_DAWNDUSK, - &vmng->video_scene_param[vmng->video_scence_num++]); -#endif /* CONFIG_VIDEO_SCENE_DAWNDUSK */ -#ifdef CONFIG_VIDEO_SCENE_FALLCOLORS - initialize_scene_parameter(vmng, CONFIG_VIDEO_SCENE_FALLCOLORS, - &vmng->video_scene_param[vmng->video_scence_num++]); -#endif /* CONFIG_VIDEO_SCENE_FALLCOLORS */ -#ifdef CONFIG_VIDEO_SCENE_FIREWORKS - initialize_scene_parameter(vmng, CONFIG_VIDEO_SCENE_FIREWORKS, - &vmng->video_scene_param[vmng->video_scence_num++]); -#endif /* CONFIG_VIDEO_SCENE_FIREWORKS */ -#ifdef CONFIG_VIDEO_SCENE_LANDSCAPE - initialize_scene_parameter(vmng, CONFIG_VIDEO_SCENE_LANDSCAPE, - &vmng->video_scene_param[vmng->video_scence_num++]); -#endif /* CONFIG_VIDEO_SCENE_LANDSCAPE */ -#ifdef CONFIG_VIDEO_SCENE_NIGHT - initialize_scene_parameter(vmng, CONFIG_VIDEO_SCENE_NIGHT, - &vmng->video_scene_param[vmng->video_scence_num++]); -#endif /* CONFIG_VIDEO_SCENE_NIGHT */ -#ifdef CONFIG_VIDEO_SCENE_PARTYINDOOR - initialize_scene_parameter(vmng, CONFIG_VIDEO_SCENE_PARTYINDOOR, - &vmng->video_scene_param[vmng->video_scence_num++]); -#endif /* CONFIG_VIDEO_SCENE_PARTYINDOOR */ -#ifdef CONFIG_VIDEO_SCENE_PORTRAIT - initialize_scene_parameter(vmng, CONFIG_VIDEO_SCENE_PORTRAIT, - &vmng->video_scene_param[vmng->video_scence_num++]); -#endif /* CONFIG_VIDEO_SCENE_PORTRAIT */ -#ifdef CONFIG_VIDEO_SCENE_SPORTS - initialize_scene_parameter(vmng, CONFIG_VIDEO_SCENE_SPORTS, - &vmng->video_scene_param[vmng->video_scence_num++]); -#endif /* CONFIG_VIDEO_SCENE_SPORTS */ -#ifdef CONFIG_VIDEO_SCENE_SUNSET - initialize_scene_parameter(vmng, CONFIG_VIDEO_SCENE_SUNSET, - &vmng->video_scene_param[vmng->video_scence_num++]); -#endif /* CONFIG_VIDEO_SCENE_SUNSET */ -#ifdef CONFIG_VIDEO_SCENE_TEXT - initialize_scene_parameter(vmng, CONFIG_VIDEO_SCENE_TEXT, - &vmng->video_scene_param[vmng->video_scence_num++]); -#endif /* CONFIG_VIDEO_SCENE_TEXT */ -} - -static void initialize_resources(FAR video_mng_t *vmng) -{ - initialize_streamresources(&vmng->video_inf); - initialize_streamresources(&vmng->still_inf); - initialize_scenes_parameter(vmng); -} - -static void cleanup_streamresources(FAR video_type_inf_t *type_inf) -{ - video_framebuff_uninit(&type_inf->bufinf); - nxsem_destroy(&type_inf->wait_capture.dqbuf_wait_flg); - nxmutex_destroy(&type_inf->lock_state); - if (type_inf->bufheap != NULL) - { - kumm_free(type_inf->bufheap); - type_inf->bufheap = NULL; - } -} - -static void cleanup_scene_parameter(FAR video_scene_params_t **vsp) -{ - FAR video_scene_params_t *sp = *vsp; - ASSERT(sp); - - if (sp->gamma_curve != NULL) - { - kmm_free(sp->gamma_curve); - sp->gamma_curve = NULL; - sp->gamma_curve_sz = 0; - } - - kmm_free(sp); - *vsp = NULL; -} - -static void cleanup_scenes_parameter(FAR video_mng_t *vmng) -{ - int i; - - for (i = 0; i < vmng->video_scence_num; i++) - { - cleanup_scene_parameter(&vmng->video_scene_param[i]); - } - - vmng->video_scence_num = 0; -} - -static void cleanup_resources(FAR video_mng_t *vmng) -{ - /* If in capture, stop */ - - if (vmng->video_inf.state == VIDEO_STATE_CAPTURE) - { - stop_capture(vmng, V4L2_BUF_TYPE_VIDEO_CAPTURE); - } - - if (vmng->still_inf.state == VIDEO_STATE_CAPTURE) - { - stop_capture(vmng, V4L2_BUF_TYPE_STILL_CAPTURE); - } - - /* Clean up resource */ - - cleanup_streamresources(&vmng->video_inf); - cleanup_streamresources(&vmng->still_inf); - cleanup_scenes_parameter(vmng); -} - -static bool is_sem_waited(FAR sem_t *sem) -{ - int semcount; - - return nxsem_get_value(sem, &semcount) == OK && semcount < 0; -} - -static FAR struct imgsensor_s * -get_connected_imgsensor(FAR struct imgsensor_s **sensors, - size_t sensor_num) -{ - FAR struct imgsensor_s *sensor = NULL; - int i; - - for (i = 0; i < sensor_num; i++) - { - if (sensors[i] && - IMGSENSOR_IS_AVAILABLE(sensors[i])) - { - sensor = sensors[i]; - break; - } - } - - return sensor; -} - -static int video_open(FAR struct file *filep) -{ - FAR struct inode *inode = filep->f_inode; - FAR video_mng_t *priv = inode->i_private; - int ret = OK; - - nxmutex_lock(&priv->lock_open_num); - if (priv->open_num == 0) - { - /* Only in first execution, open device */ - - ret = IMGSENSOR_INIT(priv->imgsensor); - if (ret == OK) - { - ret = IMGDATA_INIT(priv->imgdata); - if (ret == OK) - { - initialize_resources(priv); - } - } - else - { - ret = -ENODEV; - } - } - - /* In second or later execution, ret is initial value(=OK) */ - - if (ret == OK) - { - priv->open_num++; - } - - nxmutex_unlock(&priv->lock_open_num); - return ret; -} - -static int video_close(FAR struct file *filep) -{ - FAR struct inode *inode = filep->f_inode; - FAR video_mng_t *priv = inode->i_private; - - nxmutex_lock(&priv->lock_open_num); - - if (--priv->open_num == 0) - { - cleanup_resources(priv); - IMGSENSOR_UNINIT(priv->imgsensor); - IMGDATA_UNINIT(priv->imgdata); -#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS - if (priv->unlinked) - { - nxmutex_unlock(&priv->lock_open_num); - nxmutex_destroy(&priv->lock_open_num); - kmm_free(priv->devpath); - kmm_free(priv); - inode->i_private = NULL; - return OK; - } - -#endif - } - - nxmutex_unlock(&priv->lock_open_num); - return OK; -} - -static ssize_t video_read(FAR struct file *filep, - FAR char *buffer, size_t buflen) -{ - return -ENOTSUP; -} - -static ssize_t video_write(FAR struct file *filep, - FAR const char *buffer, size_t buflen) -{ - return -ENOTSUP; -} - -#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS -static int video_unlink(FAR struct inode *inode) -{ - FAR video_mng_t *priv = inode->i_private; - nxmutex_lock(&priv->lock_open_num); - if (priv->open_num == 0) - { - nxmutex_unlock(&priv->lock_open_num); - nxmutex_destroy(&priv->lock_open_num); - kmm_free(priv->devpath); - kmm_free(priv); - inode->i_private = NULL; - } - else - { - priv->unlinked = true; - nxmutex_unlock(&priv->lock_open_num); - } - - return OK; -} -#endif - -static int video_querycap(FAR video_mng_t *vmng, - FAR struct v4l2_capability *cap) -{ - FAR const char *name; - - ASSERT(vmng->imgsensor); - - if (cap == NULL) - { - return -EINVAL; - } - - name = IMGSENSOR_GET_DRIVER_NAME(vmng->imgsensor); - if (name == NULL) - { - return -ENOTTY; - } - - memset(cap, 0, sizeof(struct v4l2_capability)); - - /* cap->driver needs to be NULL-terminated. */ - - strlcpy((FAR char *)cap->driver, name, sizeof(cap->driver)); - cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING; - - return OK; -} - -static int video_g_input(FAR int *num) -{ - *num = 0; - return OK; -} - -static int video_enum_input(FAR video_mng_t *vmng, - FAR struct v4l2_input *input) -{ - FAR const char *name; - - ASSERT(vmng->imgsensor); - - if (input->index > 0) - { - return -EINVAL; - } - - name = IMGSENSOR_GET_DRIVER_NAME(vmng->imgsensor); - if (name == NULL) - { - return -ENOTTY; - } - - memset(input, 0, sizeof(struct v4l2_input)); - strlcpy((FAR char *)input->name, name, sizeof(input->name)); - input->type = V4L2_INPUT_TYPE_CAMERA; - - return OK; -} - -static int video_reqbufs(FAR struct video_mng_s *vmng, - FAR struct v4l2_requestbuffers *reqbufs) -{ - FAR video_type_inf_t *type_inf; - irqstate_t flags; - int ret = OK; - - if (vmng == NULL || reqbufs == NULL) - { - return -EINVAL; - } - - type_inf = get_video_type_inf(vmng, reqbufs->type); - if (type_inf == NULL) - { - return -EINVAL; - } - - flags = enter_critical_section(); - - if (type_inf->state == VIDEO_STATE_CAPTURE) - { - /* In capture, REQBUFS is not permitted */ - - ret = -EPERM; - } - else - { - if (reqbufs->count > V4L2_REQBUFS_COUNT_MAX) - { - reqbufs->count = V4L2_REQBUFS_COUNT_MAX; - } - - video_framebuff_change_mode(&type_inf->bufinf, reqbufs->mode); - ret = video_framebuff_realloc_container(&type_inf->bufinf, - reqbufs->count); - if (ret == OK && reqbufs->memory == V4L2_MEMORY_MMAP) - { - if (type_inf->bufheap != NULL) - { - kumm_free(type_inf->bufheap); - } - - type_inf->bufheap = kumm_memalign(32, - reqbufs->count * get_bufsize(&type_inf->fmt[VIDEO_FMT_MAIN])); - if (type_inf->bufheap == NULL) - { - ret = -ENOMEM; - } - } - } - - leave_critical_section(flags); - return ret; -} - -static int video_querybuf(FAR struct video_mng_s *vmng, - FAR struct v4l2_buffer *buf) -{ - FAR video_type_inf_t *type_inf; - - if (vmng == NULL || buf == NULL || buf->memory != V4L2_MEMORY_MMAP) - { - return -EINVAL; - } - - type_inf = get_video_type_inf(vmng, buf->type); - if (type_inf == NULL) - { - return -EINVAL; - } - - if (buf->index >= type_inf->bufinf.container_size) - { - return -EINVAL; - } - - buf->length = get_bufsize(&type_inf->fmt[VIDEO_FMT_MAIN]); - buf->m.offset = buf->length * buf->index; - - return OK; -} - -static int video_qbuf(FAR struct video_mng_s *vmng, - FAR struct v4l2_buffer *buf) -{ - FAR video_type_inf_t *type_inf; - FAR vbuf_container_t *container; - enum video_state_e next_video_state; - irqstate_t flags; - - if (vmng == NULL || buf == NULL) - { - return -EINVAL; - } - - type_inf = get_video_type_inf(vmng, buf->type); - if (type_inf == NULL) - { - return -EINVAL; - } - - if (!is_bufsize_sufficient(vmng, buf->length)) - { - return -EINVAL; - } - - container = video_framebuff_get_container(&type_inf->bufinf); - if (container == NULL) - { - return -ENOMEM; - } - - memcpy(&container->buf, buf, sizeof(struct v4l2_buffer)); - if (buf->memory == V4L2_MEMORY_MMAP) - { - /* only use userptr inside the container */ - - container->buf.length = get_bufsize(&type_inf->fmt[VIDEO_FMT_MAIN]); - container->buf.m.userptr = (unsigned long)(type_inf->bufheap + - container->buf.length * buf->index); - } - - video_framebuff_queue_container(&type_inf->bufinf, container); - - nxmutex_lock(&type_inf->lock_state); - flags = enter_critical_section(); - if (type_inf->state == VIDEO_STATE_STREAMON) - { - leave_critical_section(flags); - - if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) - { - nxmutex_lock(&vmng->still_inf.lock_state); - next_video_state = - estimate_next_video_state(vmng, CAUSE_VIDEO_START); - change_video_state(vmng, next_video_state); - nxmutex_unlock(&vmng->still_inf.lock_state); - } - else - { - container = - video_framebuff_get_vacant_container(&type_inf->bufinf); - if (container != NULL) - { - type_inf->seqnum = 0; - start_capture(vmng, - buf->type, - type_inf->nr_fmt, - type_inf->fmt, - &type_inf->clip, - &type_inf->frame_interval, - container->buf.m.userptr, - container->buf.length); - type_inf->state = VIDEO_STATE_CAPTURE; - } - } - } - else - { - leave_critical_section(flags); - } - - nxmutex_unlock(&type_inf->lock_state); - return OK; -} - -static int video_dqbuf(FAR struct video_mng_s *vmng, - FAR struct v4l2_buffer *buf, - int oflags) -{ - irqstate_t flags; - FAR video_type_inf_t *type_inf; - FAR vbuf_container_t *container; - FAR sem_t *dqbuf_wait_flg; - enum video_state_e next_video_state; - - if (vmng == NULL || buf == NULL) - { - return -EINVAL; - } - - type_inf = get_video_type_inf(vmng, buf->type); - if (type_inf == NULL) - { - return -EINVAL; - } - - container = video_framebuff_dq_valid_container(&type_inf->bufinf); - if (container == NULL) - { - if (oflags & O_NONBLOCK) - { - return -EAGAIN; - } - - /* Not yet done capture. Wait done */ - - dqbuf_wait_flg = &type_inf->wait_capture.dqbuf_wait_flg; - - /* Loop until semaphore is unlocked by capture done or DQCANCEL */ - - do - { - if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) - { - /* If start capture condition is satisfied, start capture */ - - flags = enter_critical_section(); - next_video_state = - estimate_next_video_state(vmng, CAUSE_VIDEO_DQBUF); - change_video_state(vmng, next_video_state); - leave_critical_section(flags); - } - - nxsem_wait_uninterruptible(dqbuf_wait_flg); - } - while (type_inf->wait_capture.waitend_cause == - VIDEO_WAITEND_CAUSE_STILLSTOP); - - container = type_inf->wait_capture.done_container; - if (container == NULL) - { - /* Waking up without captured data means abort. - * Therefore, Check cause. - */ - - if (type_inf->wait_capture.waitend_cause == - VIDEO_WAITEND_CAUSE_DQCANCEL) - { - return -ECANCELED; - } - } - - type_inf->wait_capture.done_container = NULL; - } - - memcpy(buf, &container->buf, sizeof(struct v4l2_buffer)); - video_framebuff_free_container(&type_inf->bufinf, container); - - return OK; -} - -static int video_cancel_dqbuf(FAR struct video_mng_s *vmng, - enum v4l2_buf_type type) -{ - FAR video_type_inf_t *type_inf; - - type_inf = get_video_type_inf(vmng, type); - if (type_inf == NULL) - { - return -EINVAL; - } - - if (!is_sem_waited(&type_inf->wait_capture.dqbuf_wait_flg)) - { - /* In not waiting DQBUF case, return OK */ - - return OK; - } - - type_inf->wait_capture.waitend_cause = VIDEO_WAITEND_CAUSE_DQCANCEL; - - /* If capture is done before nxsem_post, cause is overwritten */ - - return nxsem_post(&type_inf->wait_capture.dqbuf_wait_flg); -} - -static bool validate_clip_range(int32_t pos, uint32_t c_sz, uint16_t frm_sz) -{ - return pos >= 0 && c_sz <= frm_sz && pos + c_sz <= frm_sz; -} - -static bool validate_clip_setting(FAR struct v4l2_rect *clip, - FAR video_format_t *fmt) -{ - DEBUGASSERT(clip && fmt); - - /* Not permit the setting which do not fit inside frame size. */ - - return validate_clip_range(clip->left, clip->width, fmt->width) && - validate_clip_range(clip->top, clip->height, fmt->height); -} - -static int video_s_selection(FAR struct video_mng_s *vmng, - FAR struct v4l2_selection *clip) -{ - FAR video_type_inf_t *type_inf; - uint32_t p_u32[IMGSENSOR_CLIP_NELEM]; - imgsensor_value_t val; - int32_t id; - int ret; - - ASSERT(vmng && vmng->imgsensor); - - if (clip == NULL) - { - return -EINVAL; - } - - type_inf = get_video_type_inf(vmng, clip->type); - if (type_inf == NULL) - { - return -EINVAL; - } - - if (type_inf->state != VIDEO_STATE_STREAMOFF) - { - return -EBUSY; - } - - if (!validate_clip_setting(&clip->r, type_inf->fmt)) - { - return -EINVAL; - } - - ret = validate_frame_setting(vmng, - clip->type, - type_inf->nr_fmt, - type_inf->fmt, - &clip->r, - &type_inf->frame_interval); - if (ret != OK) - { - return ret; - } - - id = clip->type == V4L2_BUF_TYPE_VIDEO_CAPTURE ? - IMGSENSOR_ID_CLIP_VIDEO : IMGSENSOR_ID_CLIP_STILL; - - p_u32[IMGSENSOR_CLIP_INDEX_LEFT] = clip->r.left; - p_u32[IMGSENSOR_CLIP_INDEX_TOP] = clip->r.top; - p_u32[IMGSENSOR_CLIP_INDEX_WIDTH] = clip->r.width; - p_u32[IMGSENSOR_CLIP_INDEX_HEIGHT] = clip->r.height; - - val.p_u32 = p_u32; - ret = IMGSENSOR_SET_VALUE(vmng->imgsensor, id, sizeof(p_u32), val); - if (ret != OK) - { - return ret; - } - - memcpy(&type_inf->clip, &clip->r, sizeof(struct v4l2_rect)); - return ret; -} - -static int video_g_selection(FAR struct video_mng_s *vmng, - FAR struct v4l2_selection *clip) -{ - FAR video_type_inf_t *type_inf; - - ASSERT(vmng); - - if (clip == NULL) - { - return -EINVAL; - } - - type_inf = get_video_type_inf(vmng, clip->type); - if (type_inf == NULL) - { - return -EINVAL; - } - - memcpy(&clip->r, &type_inf->clip, sizeof(struct v4l2_rect)); - return OK; -} - -static int validate_frame_setting(FAR video_mng_t *vmng, - enum v4l2_buf_type type, - uint8_t nr_fmt, - FAR video_format_t *vfmt, - FAR struct v4l2_rect *clip, - FAR struct v4l2_fract *interval) -{ - video_format_t c_fmt[MAX_VIDEO_FMT]; - imgdata_format_t df[MAX_VIDEO_FMT]; - imgsensor_format_t sf[MAX_VIDEO_FMT]; - imgdata_interval_t di; - imgsensor_interval_t si; - int ret; - - ASSERT(vfmt && interval && vmng->imgsensor && vmng->imgdata); - - /* Return OK only in case both image data driver and - * image sensor driver support. - */ - - get_clipped_format(nr_fmt, vfmt, clip, c_fmt); - - convert_to_imgdatafmt(&c_fmt[VIDEO_FMT_MAIN], &df[IMGDATA_FMT_MAIN]); - convert_to_imgdatafmt(&c_fmt[VIDEO_FMT_SUB], &df[IMGDATA_FMT_SUB]); - convert_to_imgdatainterval(interval, &di); - convert_to_imgsensorfmt(&vfmt[VIDEO_FMT_MAIN], &sf[IMGSENSOR_FMT_MAIN]); - convert_to_imgsensorfmt(&vfmt[VIDEO_FMT_SUB], &sf[IMGSENSOR_FMT_SUB]); - convert_to_imgsensorinterval(interval, &si); - - ret = IMGSENSOR_VALIDATE_FRAME_SETTING(vmng->imgsensor, - type == V4L2_BUF_TYPE_VIDEO_CAPTURE ? - IMGSENSOR_STREAM_TYPE_VIDEO : IMGSENSOR_STREAM_TYPE_STILL, - nr_fmt, sf, &si); - if (ret != OK) - { - return ret; - } - - return IMGDATA_VALIDATE_FRAME_SETTING(vmng->imgdata, nr_fmt, df, &di); -} - -static size_t get_bufsize(FAR video_format_t *vf) -{ - size_t ret = vf->width * vf->height; - switch (vf->pixelformat) - { - case V4L2_PIX_FMT_NV12: - case V4L2_PIX_FMT_YUV420: - return ret * 3 / 2; - case V4L2_PIX_FMT_YUYV: - case V4L2_PIX_FMT_UYVY: - case V4L2_PIX_FMT_RGB565: - case V4L2_PIX_FMT_JPEG: - default: - return ret * 2; - } -} - -static size_t get_heapsize(FAR video_type_inf_t *type_inf) -{ - return type_inf->bufinf.container_size * - get_bufsize(&type_inf->fmt[VIDEO_FMT_MAIN]); -} - -static int video_try_fmt(FAR struct video_mng_s *priv, - FAR struct v4l2_format *v4l2) -{ - FAR video_type_inf_t *type_inf; - video_format_t vf[MAX_VIDEO_FMT]; - uint8_t nr_fmt; - - ASSERT(priv && priv->imgsensor && priv->imgdata); - - if (v4l2 == NULL) - { - return -EINVAL; - } - - type_inf = get_video_type_inf(priv, v4l2->type); - if (type_inf == NULL) - { - return -EINVAL; - } - - switch (v4l2->fmt.pix.pixelformat) - { - case V4L2_PIX_FMT_SUBIMG_UYVY: - case V4L2_PIX_FMT_SUBIMG_RGB565: - if (type_inf->fmt[VIDEO_FMT_MAIN].pixelformat != - V4L2_PIX_FMT_JPEG_WITH_SUBIMG) - { - return -EPERM; - } - - /* Validate both main image and subimage. */ - - nr_fmt = 2; - memcpy(&vf[VIDEO_FMT_MAIN], - &type_inf->fmt[VIDEO_FMT_MAIN], - sizeof(video_format_t)); - vf[VIDEO_FMT_SUB].width = v4l2->fmt.pix.width; - vf[VIDEO_FMT_SUB].height = v4l2->fmt.pix.height; - vf[VIDEO_FMT_SUB].pixelformat = - v4l2->fmt.pix.pixelformat == V4L2_PIX_FMT_SUBIMG_UYVY ? - V4L2_PIX_FMT_UYVY : V4L2_PIX_FMT_RGB565; - break; - case V4L2_PIX_FMT_NV12: - case V4L2_PIX_FMT_YUV420: - case V4L2_PIX_FMT_YUYV: - case V4L2_PIX_FMT_UYVY: - case V4L2_PIX_FMT_RGB565: - case V4L2_PIX_FMT_JPEG: - case V4L2_PIX_FMT_JPEG_WITH_SUBIMG: - nr_fmt = 1; - vf[VIDEO_FMT_MAIN].width = v4l2->fmt.pix.width; - vf[VIDEO_FMT_MAIN].height = v4l2->fmt.pix.height; - vf[VIDEO_FMT_MAIN].pixelformat = v4l2->fmt.pix.pixelformat; - break; - - default: - return -EINVAL; - } - - return validate_frame_setting(priv, - v4l2->type, - nr_fmt, - vf, - &type_inf->clip, - &type_inf->frame_interval); -} - -static int video_g_fmt(FAR struct video_mng_s *priv, - FAR struct v4l2_format *fmt) -{ - FAR video_type_inf_t *type_inf; - - type_inf = get_video_type_inf(priv, fmt->type); - if (type_inf == NULL) - { - return -EINVAL; - } - - memset(&fmt->fmt, 0, sizeof(fmt->fmt)); - fmt->fmt.pix.width = type_inf->fmt[VIDEO_FMT_MAIN].width; - fmt->fmt.pix.height = type_inf->fmt[VIDEO_FMT_MAIN].height; - fmt->fmt.pix.pixelformat = type_inf->fmt[VIDEO_FMT_MAIN].pixelformat; - - return OK; -} - -static int video_s_fmt(FAR struct video_mng_s *priv, - FAR struct v4l2_format *fmt) -{ - FAR video_type_inf_t *type_inf; - int ret; - - ret = video_try_fmt(priv, fmt); - if (ret != 0) - { - return ret; - } - - type_inf = get_video_type_inf(priv, fmt->type); - if (type_inf == NULL) - { - return -EINVAL; - } - - if (type_inf->state != VIDEO_STATE_STREAMOFF) - { - return -EBUSY; - } - - switch (fmt->fmt.pix.pixelformat) - { - case V4L2_PIX_FMT_SUBIMG_UYVY: - case V4L2_PIX_FMT_SUBIMG_RGB565: - if (type_inf->fmt[VIDEO_FMT_MAIN].pixelformat != - V4L2_PIX_FMT_JPEG_WITH_SUBIMG) - { - return -EPERM; - } - - type_inf->fmt[VIDEO_FMT_SUB].width = fmt->fmt.pix.width; - type_inf->fmt[VIDEO_FMT_SUB].height = fmt->fmt.pix.height; - type_inf->fmt[VIDEO_FMT_SUB].pixelformat = - fmt->fmt.pix.pixelformat == V4L2_PIX_FMT_SUBIMG_UYVY ? - V4L2_PIX_FMT_UYVY : V4L2_PIX_FMT_RGB565; - type_inf->nr_fmt = 2; - break; - - default: - type_inf->fmt[VIDEO_FMT_MAIN].width = fmt->fmt.pix.width; - type_inf->fmt[VIDEO_FMT_MAIN].height = fmt->fmt.pix.height; - type_inf->fmt[VIDEO_FMT_MAIN].pixelformat = fmt->fmt.pix.pixelformat; - type_inf->nr_fmt = 1; - break; - } - - return OK; -} - -static int video_s_parm(FAR struct video_mng_s *priv, - FAR struct v4l2_streamparm *parm) -{ - FAR video_type_inf_t *type_inf; - int ret; - - ASSERT(priv->imgsensor && priv->imgdata); - - type_inf = get_video_type_inf(priv, parm->type); - if (type_inf == NULL) - { - return -EINVAL; - } - - if (type_inf->state != VIDEO_STATE_STREAMOFF) - { - return -EBUSY; - } - - ret = validate_frame_setting(priv, - parm->type, - type_inf->nr_fmt, - type_inf->fmt, - &type_inf->clip, - &parm->parm.capture.timeperframe); - if (ret != OK) - { - return ret; - } - - memcpy(&type_inf->frame_interval, - &parm->parm.capture.timeperframe, - sizeof(struct v4l2_fract)); - - return ret; -} - -static int video_g_parm(FAR struct video_mng_s *vmng, - FAR struct v4l2_streamparm *parm) -{ - FAR video_type_inf_t *type_inf; - int ret = -EINVAL; - - DEBUGASSERT(vmng && vmng->imgsensor); - - type_inf = get_video_type_inf(vmng, parm->type); - if (type_inf == NULL) - { - return -EINVAL; - } - - memset(&parm->parm, 0, sizeof(parm->parm)); - - if (type_inf->state == VIDEO_STATE_CAPTURE) - { - /* If capture is started and lower driver has the get_frame_interval(), - * query lower driver. - */ - - ret = IMGSENSOR_GET_FRAME_INTERVAL(vmng->imgsensor, parm->type, - (imgsensor_interval_t *)&parm->parm.capture.timeperframe); - } - - if (ret != OK) - { - /* In no capture state or error case, return stored value. */ - - memcpy(&parm->parm.capture.timeperframe, - &type_inf->frame_interval, - sizeof(struct v4l2_fract)); - } - - parm->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; - return OK; -} - -static int video_streamon(FAR struct video_mng_s *vmng, - FAR enum v4l2_buf_type *type) -{ - FAR video_type_inf_t *type_inf; - enum video_state_e next_video_state; - int ret = OK; - - if (vmng == NULL || type == NULL) - { - return -EINVAL; - } - - type_inf = get_video_type_inf(vmng, *type); - if (type_inf == NULL) - { - return -EINVAL; - } - - if (*type != V4L2_BUF_TYPE_VIDEO_CAPTURE) - { - /* No procedure for VIDIOC_STREAMON(STILL_CAPTURE) */ - - return OK; - } - - nxmutex_lock(&type_inf->lock_state); - - if (type_inf->state != VIDEO_STATE_STREAMOFF) - { - ret = -EPERM; - } - else - { - next_video_state = - estimate_next_video_state(vmng, CAUSE_VIDEO_START); - change_video_state(vmng, next_video_state); - } - - nxmutex_unlock(&type_inf->lock_state); - return ret; -} - -static int video_streamoff(FAR struct video_mng_s *vmng, - FAR enum v4l2_buf_type *type) -{ - FAR video_type_inf_t *type_inf; - enum video_state_e next_video_state; - irqstate_t flags; - int ret = OK; - - if (vmng == NULL || type == NULL) - { - return -EINVAL; - } - - type_inf = get_video_type_inf(vmng, *type); - if (type_inf == NULL) - { - return -EINVAL; - } - - if (*type != V4L2_BUF_TYPE_VIDEO_CAPTURE) - { - /* No procedure for VIDIOC_STREAMOFF(STILL_CAPTURE) */ - - return OK; - } - - flags = enter_critical_section(); - - if (type_inf->state == VIDEO_STATE_STREAMOFF) - { - ret = -EPERM; - } - else - { - next_video_state = - estimate_next_video_state(vmng, CAUSE_VIDEO_STOP); - change_video_state(vmng, next_video_state); - } - - leave_critical_section(flags); - - return ret; -} - -static int video_do_halfpush(FAR struct video_mng_s *priv, bool enable) -{ - struct v4l2_ext_controls ext_controls; - struct v4l2_ext_control control[2]; - - /* Replace to VIDIOC_S_EXT_CTRLS format */ - - control[0].id = V4L2_CID_3A_LOCK; - control[0].value = enable ? - V4L2_LOCK_EXPOSURE | V4L2_LOCK_WHITE_BALANCE : 0; - control[1].id = V4L2_CID_AUTO_FOCUS_START; - control[1].value = enable ? true : false; - - ext_controls.ctrl_class = V4L2_CTRL_CLASS_CAMERA; - ext_controls.count = 2; - ext_controls.controls = control; - - /* Execute VIDIOC_S_EXT_CTRLS */ - - return video_s_ext_ctrls(priv, &ext_controls); -} - -static int video_takepict_start(FAR struct video_mng_s *vmng, - int32_t capture_num) -{ - enum video_state_e next_video_state; - FAR vbuf_container_t *container; - irqstate_t flags; - int ret = OK; - - if (vmng == NULL) - { - return -EINVAL; - } - - nxmutex_lock(&vmng->still_inf.lock_state); - - if (vmng->still_inf.state != VIDEO_STATE_STREAMOFF) - { - ret = -EPERM; - } - else - { - if (capture_num > 0) - { - vmng->still_inf.remaining_capnum = capture_num; - } - else - { - vmng->still_inf.remaining_capnum = VIDEO_REMAINING_CAPNUM_INFINITY; - } - - /* Control video stream prior to still stream */ - - flags = enter_critical_section(); - - next_video_state = estimate_next_video_state(vmng, - CAUSE_STILL_START); - change_video_state(vmng, next_video_state); - - leave_critical_section(flags); - - container = - video_framebuff_get_vacant_container(&vmng->still_inf.bufinf); - if (container != NULL) - { - /* Start still stream capture */ - - start_capture(vmng, - V4L2_BUF_TYPE_STILL_CAPTURE, - vmng->still_inf.nr_fmt, - vmng->still_inf.fmt, - &vmng->still_inf.clip, - &vmng->still_inf.frame_interval, - container->buf.m.userptr, - container->buf.length); - - vmng->still_inf.state = VIDEO_STATE_CAPTURE; - } - else - { - vmng->still_inf.state = VIDEO_STATE_STREAMON; - } - } - - nxmutex_unlock(&vmng->still_inf.lock_state); - return ret; -} - -static int video_takepict_stop(FAR struct video_mng_s *vmng, bool halfpush) -{ - enum video_state_e next_video_state; - irqstate_t flags; - int ret = OK; - - if (vmng == NULL) - { - return -EINVAL; - } - - nxmutex_lock(&vmng->still_inf.lock_state); - - if (vmng->still_inf.state == VIDEO_STATE_STREAMOFF && - vmng->still_inf.remaining_capnum == VIDEO_REMAINING_CAPNUM_INFINITY) - { - ret = -EPERM; - } - else - { - flags = enter_critical_section(); - if (vmng->still_inf.state == VIDEO_STATE_CAPTURE) - { - stop_capture(vmng, V4L2_BUF_TYPE_STILL_CAPTURE); - } - - leave_critical_section(flags); - - vmng->still_inf.state = VIDEO_STATE_STREAMOFF; - vmng->still_inf.remaining_capnum = VIDEO_REMAINING_CAPNUM_INFINITY; - - /* Control video stream */ - - nxmutex_lock(&vmng->video_inf.lock_state); - next_video_state = estimate_next_video_state(vmng, - CAUSE_STILL_STOP); - change_video_state(vmng, next_video_state); - nxmutex_unlock(&vmng->video_inf.lock_state); - } - - nxmutex_unlock(&vmng->still_inf.lock_state); - return ret; -} - -static int video_queryctrl(FAR video_mng_t *vmng, - FAR struct v4l2_queryctrl *ctrl) -{ - struct v4l2_query_ext_ctrl ext_ctrl; - int ret; - - if (ctrl == NULL) - { - return -EINVAL; - } - - /* Replace to VIDIOC_QUERY_EXT_CTRL format */ - - ext_ctrl.ctrl_class = ctrl->ctrl_class; - ext_ctrl.id = ctrl->id; - - ret = video_query_ext_ctrl(vmng, &ext_ctrl); - if (ret != OK) - { - return ret; - } - - if (ext_ctrl.type == V4L2_CTRL_TYPE_INTEGER64 || - ext_ctrl.type == V4L2_CTRL_TYPE_U8 || - ext_ctrl.type == V4L2_CTRL_TYPE_U16 || - ext_ctrl.type == V4L2_CTRL_TYPE_U32) - { - /* Unsupported type in VIDIOC_QUERYCTRL */ - - return -EINVAL; - } - - /* Replace gotten value to VIDIOC_QUERYCTRL */ - - ctrl->type = ext_ctrl.type; - ctrl->minimum = ext_ctrl.minimum; - ctrl->maximum = ext_ctrl.maximum; - ctrl->step = ext_ctrl.step; - ctrl->default_value = ext_ctrl.default_value; - ctrl->flags = ext_ctrl.flags; - strlcpy(ctrl->name, ext_ctrl.name, sizeof(ctrl->name)); - - return OK; -} - -static void set_parameter_name(uint32_t id, char *name) -{ - int size = - sizeof(g_video_parameter_name) / sizeof(video_parameter_name_t); - int cnt; - - for (cnt = 0; cnt < size; cnt++) - { - if (g_video_parameter_name[cnt].id == id) - { - break; - } - } - - ASSERT(cnt < size); - - /* copy size = 32 is due to V4L2 specification. */ - - strlcpy(name, g_video_parameter_name[cnt].name, 32); -} - -static int video_query_ext_ctrl(FAR struct video_mng_s *vmng, - FAR struct v4l2_query_ext_ctrl *attr) -{ - imgsensor_supported_value_t value; - imgsensor_capability_range_t *range = &value.u.range; - imgsensor_capability_discrete_t *disc = &value.u.discrete; - imgsensor_capability_elems_t *elem = &value.u.elems; - int ret; - - ASSERT(vmng->imgsensor); - - if (attr == NULL) - { - return -EINVAL; - } - - attr->flags = 0; - attr->elem_size = 0; - attr->nr_of_dims = 0; - memset(attr->dims, 0, sizeof(attr->dims)); - - if (attr->ctrl_class == V4L2_CTRL_CLASS_CAMERA && - attr->id == V4L2_CID_SCENE_MODE) - { - /* Scene mode is processed in only video driver. */ - - attr->type = V4L2_CTRL_TYPE_INTEGER_MENU; - attr->minimum = 0; - attr->maximum = vmng->video_scence_num - 1; - attr->step = 1; - attr->default_value = 0; - attr->flags = 0; - strlcpy(attr->name, "Scene Mode", 32); - } - else - { - ret = IMGSENSOR_GET_SUPPORTED_VALUE(vmng->imgsensor, - VIDEO_ID(attr->ctrl_class, attr->id), - &value); - if (ret < 0) - { - return ret; - } - - attr->type = value.type; - attr->flags = 0; - - switch (value.type) - { - case IMGSENSOR_CTRL_TYPE_INTEGER_MENU: - attr->minimum = 0; - attr->maximum = disc->nr_values - 1; - attr->step = 1; - attr->default_value = disc->default_value; - break; - - case IMGSENSOR_CTRL_TYPE_U8: - case IMGSENSOR_CTRL_TYPE_U16: - case IMGSENSOR_CTRL_TYPE_U32: - attr->minimum = elem->minimum; - attr->maximum = elem->maximum; - attr->step = elem->step; - attr->elems = elem->nr_elems; - break; - - default: - attr->minimum = range->minimum; - attr->maximum = range->maximum; - attr->step = range->step; - attr->default_value = range->default_value; - break; - } - - set_parameter_name(VIDEO_ID(attr->ctrl_class, attr->id), - attr->name); - } - - return OK; -} - -static int video_querymenu(FAR video_mng_t *vmng, - FAR struct v4l2_querymenu *menu) -{ - imgsensor_supported_value_t value; - int ret; - - ASSERT(vmng->imgsensor); - - if (menu == NULL) - { - return -EINVAL; - } - - if (menu->ctrl_class == V4L2_CTRL_CLASS_CAMERA && - menu->id == V4L2_CID_SCENE_MODE) - { - /* Scene mode is processed in only video driver. */ - - if (menu->index > vmng->video_scence_num - 1) - { - return -EINVAL; - } - - menu->value = vmng->video_scene_param[menu->index]->mode; - } - else - { - ret = IMGSENSOR_GET_SUPPORTED_VALUE(vmng->imgsensor, - VIDEO_ID(menu->ctrl_class, menu->id), - &value); - if (ret < 0) - { - return ret; - } - - if (value.type != IMGSENSOR_CTRL_TYPE_INTEGER_MENU) - { - /* VIDIOC_QUERYMENU is used only for - * IMGSENSOR_CTRL_TYPE_INTEGER_MENU. - */ - - return -EINVAL; - } - - if (menu->index >= value.u.discrete.nr_values) - { - return -EINVAL; - } - - menu->value = value.u.discrete.values[menu->index]; - } - - return OK; -} - -static int video_g_ctrl(FAR struct video_mng_s *priv, - FAR struct v4l2_control *ctrl) -{ - struct v4l2_ext_controls ext_controls; - struct v4l2_ext_control control; - int ret; - - memset(&ext_controls, 0, sizeof(struct v4l2_ext_controls)); - memset(&control, 0, sizeof(struct v4l2_ext_control)); - - if (ctrl == NULL) - { - return -EINVAL; - } - - /* Replace to VIDIOC_G_EXT_CTRLS format */ - - control.id = ctrl->id; - - ext_controls.ctrl_class = V4L2_CTRL_CLASS_USER; - ext_controls.count = 1; - ext_controls.controls = &control; - - /* Execute VIDIOC_G_EXT_CTRLS */ - - ret = video_g_ext_ctrls(priv, &ext_controls); - if (ret == OK) - { - /* Replace gotten value to VIDIOC_G_CTRL parameter */ - - ctrl->value = control.value; - } - - return ret; -} - -static int video_s_ctrl(FAR struct video_mng_s *priv, - FAR struct v4l2_control *ctrl) -{ - struct v4l2_ext_controls ext_controls; - struct v4l2_ext_control control; - - if (ctrl == NULL) - { - return -EINVAL; - } - - /* Replace to VIDIOC_S_EXT_CTRLS format */ - - control.id = ctrl->id; - control.value = ctrl->value; - - ext_controls.ctrl_class = V4L2_CTRL_CLASS_USER; - ext_controls.count = 1; - ext_controls.controls = &control; - - /* Execute VIDIOC_S_EXT_CTRLS */ - - return video_s_ext_ctrls(priv, &ext_controls); -} - -static int video_g_ext_ctrls(FAR struct video_mng_s *priv, - FAR struct v4l2_ext_controls *ctrls) -{ - FAR struct v4l2_ext_control *control; - int ret = OK; - int cnt; - - ASSERT(priv->imgsensor); - - if (priv == NULL || ctrls == NULL) - { - return -EINVAL; - } - - for (cnt = 0, control = ctrls->controls; - cnt < ctrls->count; - cnt++, control++) - { - ret = IMGSENSOR_GET_VALUE(priv->imgsensor, - VIDEO_ID(ctrls->ctrl_class, control->id), - control->size, - (imgsensor_value_t *)&control->value64); - if (ret < 0) - { - /* Set cnt in that error occurred */ - - ctrls->error_idx = cnt; - return ret; - } - } - - return ret; -} - -static int set_intvalue(FAR video_mng_t *vmng, - uint32_t id, int32_t value32) -{ - imgsensor_value_t value; - - ASSERT(vmng->imgsensor); - - value.value32 = value32; - return IMGSENSOR_SET_VALUE(vmng->imgsensor, id, sizeof(int32_t), value); -} - -static int set_pvalue(FAR video_mng_t *vmng, - uint32_t id, int size, void *pval) -{ - imgsensor_value_t value; - - ASSERT(vmng->imgsensor); - - value.p_u8 = (FAR uint8_t *)pval; - return IMGSENSOR_SET_VALUE(vmng->imgsensor, id, size, value); -} - -static video_scene_params_t *search_scene_param(FAR video_mng_t *vmng, - enum v4l2_scene_mode mode) -{ - int i; - - for (i = 0; i < vmng->video_scence_num; i++) - { - if (vmng->video_scene_param[i]->mode == mode) - { - return vmng->video_scene_param[i]; - } - } - - return NULL; -} - -static int reflect_scene_parameter(FAR video_mng_t *vmng, - enum v4l2_scene_mode mode) -{ - video_scene_params_t *sp; - - sp = search_scene_param(vmng, mode); - if (sp == NULL) - { - /* Unsupported scene mode */ - - return -EINVAL; - } - - set_intvalue(vmng, IMGSENSOR_ID_BRIGHTNESS, sp->brightness); - set_intvalue(vmng, IMGSENSOR_ID_CONTRAST, sp->contrast); - set_intvalue(vmng, IMGSENSOR_ID_SATURATION, sp->saturation); - set_intvalue(vmng, IMGSENSOR_ID_HUE , sp->hue); - set_intvalue(vmng, IMGSENSOR_ID_AUTO_WHITE_BALANCE, sp->awb); - set_intvalue(vmng, IMGSENSOR_ID_RED_BALANCE , sp->red); - set_intvalue(vmng, IMGSENSOR_ID_BLUE_BALANCE, sp->blue); - set_intvalue(vmng, IMGSENSOR_ID_GAMMA, sp->gamma); - set_pvalue(vmng, IMGSENSOR_ID_GAMMA_CURVE, - sp->gamma_curve_sz, sp->gamma_curve); - set_intvalue(vmng, IMGSENSOR_ID_EXPOSURE, sp->ev); - set_intvalue(vmng, IMGSENSOR_ID_HFLIP_VIDEO, sp->hflip_video); - set_intvalue(vmng, IMGSENSOR_ID_VFLIP_VIDEO, sp->vflip_video); - set_intvalue(vmng, IMGSENSOR_ID_HFLIP_STILL, sp->hflip_still); - set_intvalue(vmng, IMGSENSOR_ID_VFLIP_STILL, sp->vflip_still); - set_intvalue(vmng, IMGSENSOR_ID_SHARPNESS, sp->sharpness); - set_intvalue(vmng, IMGSENSOR_ID_COLORFX, sp->colorfx); - set_intvalue(vmng, IMGSENSOR_ID_AUTOBRIGHTNESS, sp->auto_brightness); - set_intvalue(vmng, IMGSENSOR_ID_ROTATE, sp->rotate); - set_intvalue(vmng, IMGSENSOR_ID_EXPOSURE_AUTO, sp->ae); - if (sp->ae == V4L2_EXPOSURE_MANUAL || - sp->ae == V4L2_EXPOSURE_SHUTTER_PRIORITY) - { - set_intvalue(vmng, IMGSENSOR_ID_EXPOSURE_ABSOLUTE, sp->exposure_time); - } - - set_intvalue(vmng, IMGSENSOR_ID_FOCUS_ABSOLUTE, sp->focus); - set_intvalue(vmng, IMGSENSOR_ID_FOCUS_AUTO, sp->af); - set_intvalue(vmng, IMGSENSOR_ID_ZOOM_ABSOLUTE, sp->zoom); - if (sp->ae == V4L2_EXPOSURE_MANUAL || - sp->ae == V4L2_EXPOSURE_APERTURE_PRIORITY) - { - set_intvalue(vmng, IMGSENSOR_ID_IRIS_ABSOLUTE, sp->iris); - } - - set_intvalue(vmng, IMGSENSOR_ID_AUTO_N_PRESET_WB, sp->wb); - set_intvalue(vmng, IMGSENSOR_ID_WIDE_DYNAMIC_RANGE, sp->wdr); - set_intvalue(vmng, IMGSENSOR_ID_IMG_STABILIZATION, sp->stabilization); - set_intvalue(vmng, IMGSENSOR_ID_ISO_SENSITIVITY_AUTO, sp->iso_auto); - if (sp->iso_auto == V4L2_ISO_SENSITIVITY_MANUAL) - { - set_intvalue(vmng, IMGSENSOR_ID_ISO_SENSITIVITY, sp->iso); - } - - set_intvalue(vmng, IMGSENSOR_ID_EXPOSURE_METERING, sp->meter); - set_intvalue(vmng, IMGSENSOR_ID_3A_LOCK, sp->threea_lock); - set_intvalue(vmng, IMGSENSOR_ID_FLASH_LED_MODE, sp->led); - set_intvalue(vmng, IMGSENSOR_ID_JPEG_QUALITY, sp->jpeg_quality); - - vmng->video_scene_mode = mode; - return OK; -} - -static int video_s_ext_ctrls(FAR struct video_mng_s *priv, - FAR struct v4l2_ext_controls *ctrls) -{ - FAR struct v4l2_ext_control *control; - int ret = OK; - int cnt; - - ASSERT(priv->imgsensor); - - if (priv == NULL || ctrls == NULL) - { - return -EINVAL; - } - - for (cnt = 0, control = ctrls->controls; - cnt < ctrls->count; - cnt++, control++) - { - if (ctrls->ctrl_class == V4L2_CTRL_CLASS_CAMERA && - control->id == V4L2_CID_SCENE_MODE) - { - ret = reflect_scene_parameter(priv, control->value); - } - else - { - ret = IMGSENSOR_SET_VALUE(priv->imgsensor, - VIDEO_ID(ctrls->ctrl_class, control->id), - control->size, - (imgsensor_value_t)control->value64); - if (ret == 0) - { - if (priv->video_scene_mode == V4L2_SCENE_MODE_NONE) - { - save_scene_param(priv, V4L2_SCENE_MODE_NONE, - VIDEO_ID(ctrls->ctrl_class, control->id), - control); - } - } - } - - if (ret < 0) - { - /* Set cnt in that error occurred */ - - ctrls->error_idx = cnt; - return ret; - } - } - - return ret; -} - -static int video_query_ext_ctrl_scene(FAR video_mng_t *vmng, - FAR struct v4s_query_ext_ctrl_scene *attr) -{ - if (attr == NULL) - { - return -EINVAL; - } - - return video_query_ext_ctrl(vmng, &attr->control); -} - -static int video_querymenu_scene(FAR video_mng_t *vmng, - FAR struct v4s_querymenu_scene *menu) -{ - if (menu == NULL) - { - return -EINVAL; - } - - return video_querymenu(vmng, &menu->menu); -} - -static int read_scene_param(FAR struct video_mng_s *vmng, - enum v4l2_scene_mode mode, - uint32_t id, - struct v4l2_ext_control *control) -{ - imgsensor_supported_value_t value; - video_scene_params_t *sp; - int ret = OK; - - ASSERT(vmng->imgsensor); - - if (control == NULL) - { - return -EINVAL; - } - - sp = search_scene_param(vmng, mode); - if (sp == NULL) - { - /* Unsupported scene mode */ - - return -EINVAL; - } - - ret = IMGSENSOR_GET_SUPPORTED_VALUE(vmng->imgsensor, id, &value); - if (ret < 0) - { - /* Unsupported camera parameter */ - - return ret; - } - - switch (id) - { - case IMGSENSOR_ID_BRIGHTNESS: - control->value = sp->brightness; - break; - - case IMGSENSOR_ID_CONTRAST: - control->value = sp->contrast; - break; - - case IMGSENSOR_ID_SATURATION: - control->value = sp->saturation; - break; - - case IMGSENSOR_ID_HUE: - control->value = sp->hue; - break; - - case IMGSENSOR_ID_AUTO_WHITE_BALANCE: - control->value = sp->awb; - break; - - case IMGSENSOR_ID_RED_BALANCE: - control->value = sp->red; - break; - - case IMGSENSOR_ID_BLUE_BALANCE: - control->value = sp->blue; - break; - - case IMGSENSOR_ID_GAMMA: - control->value = sp->gamma; - break; - - case IMGSENSOR_ID_GAMMA_CURVE: - memcpy(control->p_u8, - sp->gamma_curve, - sp->gamma_curve_sz); - break; - - case IMGSENSOR_ID_EXPOSURE: - control->value = sp->ev; - break; - - case IMGSENSOR_ID_HFLIP_VIDEO: - control->value = sp->hflip_video; - break; - - case IMGSENSOR_ID_VFLIP_VIDEO: - control->value = sp->vflip_video; - break; - - case IMGSENSOR_ID_HFLIP_STILL: - control->value = sp->hflip_still; - break; - - case IMGSENSOR_ID_VFLIP_STILL: - control->value = sp->vflip_still; - break; - - case IMGSENSOR_ID_SHARPNESS: - control->value = sp->sharpness; - break; - - case IMGSENSOR_ID_COLOR_KILLER: - control->value = sp->colorfx == V4L2_COLORFX_BW; - break; - - case IMGSENSOR_ID_COLORFX: - control->value = sp->colorfx; - break; - - case IMGSENSOR_ID_AUTOBRIGHTNESS: - control->value = sp->auto_brightness; - break; - - case IMGSENSOR_ID_ROTATE: - control->value = sp->rotate; - break; - - case IMGSENSOR_ID_EXPOSURE_AUTO: - control->value = sp->ae; - break; - - case IMGSENSOR_ID_EXPOSURE_ABSOLUTE: - control->value = sp->exposure_time; - break; - - case IMGSENSOR_ID_FOCUS_ABSOLUTE: - control->value = sp->focus; - break; - - case IMGSENSOR_ID_FOCUS_AUTO: - control->value = sp->af; - break; - - case IMGSENSOR_ID_ZOOM_ABSOLUTE: - control->value = sp->zoom; - break; - - case IMGSENSOR_ID_IRIS_ABSOLUTE: - control->value = sp->iris; - break; - - case IMGSENSOR_ID_AUTO_N_PRESET_WB: - control->value = sp->wb; - break; - - case IMGSENSOR_ID_WIDE_DYNAMIC_RANGE: - control->value = sp->wdr; - break; - - case IMGSENSOR_ID_IMG_STABILIZATION: - control->value = sp->stabilization; - break; - - case IMGSENSOR_ID_ISO_SENSITIVITY: - control->value = sp->iso; - break; - - case IMGSENSOR_ID_ISO_SENSITIVITY_AUTO: - control->value = sp->iso_auto; - break; - - case IMGSENSOR_ID_EXPOSURE_METERING: - control->value = sp->meter; - break; - - case IMGSENSOR_ID_SPOT_POSITION: - control->value = sp->spot_pos; - break; - - case IMGSENSOR_ID_3A_LOCK: - control->value = sp->threea_lock; - break; - - case IMGSENSOR_ID_FLASH_LED_MODE: - control->value = sp->led; - break; - - case IMGSENSOR_ID_JPEG_QUALITY: - control->value = sp->jpeg_quality; - break; - - default: - ret = -EINVAL; - break; - } - - return ret; -} - -static int video_g_ext_ctrls_scene(FAR video_mng_t *vmng, - FAR struct v4s_ext_controls_scene *ctrls) -{ - FAR struct v4l2_ext_control *control; - int ret = OK; - int cnt; - - if (ctrls == NULL) - { - return -EINVAL; - } - - for (cnt = 0, control = ctrls->control.controls; - cnt < ctrls->control.count; - cnt++, control++) - { - ret = read_scene_param(vmng, ctrls->mode, - VIDEO_ID(ctrls->control.ctrl_class, control->id), - control); - if (ret != OK) - { - ctrls->control.error_idx = cnt; - return ret; - } - } - - return ret; -} - -static int check_range(int64_t value, - int64_t min, - int64_t max, - uint64_t step) -{ - if (value < min || value > max || - (value - min) % step != 0) - { - return -EINVAL; - } - - return OK; -} - -static int save_scene_param(FAR video_mng_t *vmng, - enum v4l2_scene_mode mode, - uint32_t id, - struct v4l2_ext_control *control) -{ - imgsensor_supported_value_t value; - imgsensor_capability_range_t *range = &value.u.range; - imgsensor_capability_discrete_t *disc = &value.u.discrete; - imgsensor_capability_elems_t *elem = &value.u.elems; - video_scene_params_t *sp; - int ret; - int i; - - ASSERT(vmng->imgsensor); - - sp = search_scene_param(vmng, mode); - if (sp == NULL) - { - /* Unsupported scene mode */ - - return -EINVAL; - } - - ret = IMGSENSOR_GET_SUPPORTED_VALUE(vmng->imgsensor, id, &value); - if (ret < 0) - { - /* Unsupported camera parameter */ - - return ret; - } - - switch (value.type) - { - case IMGSENSOR_CTRL_TYPE_INTEGER_MENU: - for (i = 0; i < disc->nr_values; i++) - { - if (control->value == disc->values[i]) - { - break; - } - } - - if (i >= disc->nr_values) - { - return -EINVAL; - } - - break; - - case IMGSENSOR_CTRL_TYPE_U8: - if (control->size < elem->nr_elems * sizeof(uint8_t)) - { - return -EINVAL; - } - - for (i = 0; i < elem->nr_elems; i++) - { - ret = check_range(control->p_u8[i], - elem->minimum, - elem->maximum, - elem->step); - if (ret != OK) - { - return ret; - } - } - - break; - - case IMGSENSOR_CTRL_TYPE_U16: - if (control->size < elem->nr_elems * sizeof(uint16_t)) - { - return -EINVAL; - } - - for (i = 0; i < elem->nr_elems; i++) - { - ret = check_range(control->p_u16[i], - elem->minimum, - elem->maximum, - elem->step); - if (ret != OK) - { - return ret; - } - } - - break; - - case IMGSENSOR_CTRL_TYPE_U32: - if (control->size < elem->nr_elems * sizeof(uint32_t)) - { - return -EINVAL; - } - - for (i = 0; i < elem->nr_elems; i++) - { - ret = check_range(control->p_u32[i], - elem->minimum, - elem->maximum, - elem->step); - if (ret != OK) - { - return ret; - } - } - - break; - - default: - ret = check_range(control->value, - range->minimum, - range->maximum, - range->step); - if (ret != OK) - { - return ret; - } - - break; - } - - switch (id) - { - case IMGSENSOR_ID_BRIGHTNESS: - sp->brightness = control->value; - break; - - case IMGSENSOR_ID_CONTRAST: - sp->contrast = control->value; - break; - - case IMGSENSOR_ID_SATURATION: - sp->saturation = control->value; - break; - - case IMGSENSOR_ID_HUE: - sp->hue = control->value; - break; - - case IMGSENSOR_ID_AUTO_WHITE_BALANCE: - sp->awb = control->value; - break; - - case IMGSENSOR_ID_RED_BALANCE: - sp->red = control->value; - break; - - case IMGSENSOR_ID_BLUE_BALANCE: - sp->blue = control->value; - break; - - case IMGSENSOR_ID_GAMMA: - sp->gamma = control->value; - break; - - case IMGSENSOR_ID_GAMMA_CURVE: - memcpy(sp->gamma_curve, - control->p_u8, - sp->gamma_curve_sz); - break; - - case IMGSENSOR_ID_EXPOSURE: - sp->ev = control->value; - break; - - case IMGSENSOR_ID_HFLIP_VIDEO: - sp->hflip_video = control->value; - break; - - case IMGSENSOR_ID_VFLIP_VIDEO: - sp->vflip_video = control->value; - break; - - case IMGSENSOR_ID_HFLIP_STILL: - sp->hflip_still = control->value; - break; - - case IMGSENSOR_ID_VFLIP_STILL: - sp->vflip_still = control->value; - break; - - case IMGSENSOR_ID_SHARPNESS: - sp->sharpness = control->value; - break; - - case IMGSENSOR_ID_COLOR_KILLER: - sp->colorfx = control->value ? V4L2_COLORFX_BW : V4L2_COLORFX_NONE; - break; - - case IMGSENSOR_ID_COLORFX: - sp->colorfx = control->value; - break; - - case IMGSENSOR_ID_AUTOBRIGHTNESS: - sp->auto_brightness = control->value; - break; - - case IMGSENSOR_ID_ROTATE: - sp->rotate = control->value; - break; - - case IMGSENSOR_ID_EXPOSURE_AUTO: - sp->ae = control->value; - break; - - case IMGSENSOR_ID_EXPOSURE_ABSOLUTE: - sp->exposure_time = control->value; - break; - - case IMGSENSOR_ID_FOCUS_ABSOLUTE: - sp->focus = control->value; - break; - - case IMGSENSOR_ID_FOCUS_AUTO: - sp->af = control->value; - break; - - case IMGSENSOR_ID_ZOOM_ABSOLUTE: - sp->zoom = control->value; - break; - - case IMGSENSOR_ID_IRIS_ABSOLUTE: - sp->iris = control->value; - break; - - case IMGSENSOR_ID_AUTO_N_PRESET_WB: - sp->wb = control->value; - break; - - case IMGSENSOR_ID_WIDE_DYNAMIC_RANGE: - sp->wdr = control->value; - break; - - case IMGSENSOR_ID_IMG_STABILIZATION: - sp->stabilization = control->value; - break; - - case IMGSENSOR_ID_ISO_SENSITIVITY: - sp->iso = control->value; - break; - - case IMGSENSOR_ID_ISO_SENSITIVITY_AUTO: - sp->iso_auto = control->value; - break; - - case IMGSENSOR_ID_EXPOSURE_METERING: - sp->meter = control->value; - break; - - case IMGSENSOR_ID_SPOT_POSITION: - sp->spot_pos = control->value; - break; - - case IMGSENSOR_ID_3A_LOCK: - sp->threea_lock = control->value; - break; - - case IMGSENSOR_ID_FLASH_LED_MODE: - sp->led = control->value; - break; - - case IMGSENSOR_ID_JPEG_QUALITY: - sp->jpeg_quality = control->value; - break; - - default: - return -EINVAL; - } - - return OK; -} - -static int video_s_ext_ctrls_scene(FAR struct video_mng_s *vmng, - FAR struct v4s_ext_controls_scene *ctrls) -{ - FAR struct v4l2_ext_control *control; - int ret = OK; - int cnt; - - if (ctrls == NULL) - { - return -EINVAL; - } - - for (cnt = 0, control = ctrls->control.controls; - cnt < ctrls->control.count; - cnt++, control++) - { - ret = save_scene_param(vmng, ctrls->mode, - VIDEO_ID(ctrls->control.ctrl_class, control->id), - control); - if (ret != OK) - { - ctrls->control.error_idx = cnt; - return ret; - } - } - - return ret; -} - -/**************************************************************************** - * Name: video_ioctl - * - * Description: - * Standard character driver ioctl method. - * - ****************************************************************************/ - -static int video_ioctl(FAR struct file *filep, int cmd, unsigned long arg) -{ - FAR struct inode *inode = filep->f_inode; - FAR video_mng_t *priv = inode->i_private; - int ret = OK; - - switch (cmd) - { - case VIDIOC_QUERYCAP: - ret = video_querycap(priv, (FAR struct v4l2_capability *)arg); - break; - - case VIDIOC_G_INPUT: - ret = video_g_input((FAR int *)arg); - break; - - case VIDIOC_ENUMINPUT: - ret = video_enum_input(priv, (FAR struct v4l2_input *)arg); - break; - - case VIDIOC_REQBUFS: - ret = video_reqbufs(priv, (FAR struct v4l2_requestbuffers *)arg); - break; - - case VIDIOC_QUERYBUF: - ret = video_querybuf(priv, (FAR struct v4l2_buffer *)arg); - - break; - - case VIDIOC_QBUF: - ret = video_qbuf(priv, (FAR struct v4l2_buffer *)arg); - break; - - case VIDIOC_DQBUF: - ret = video_dqbuf(priv, (FAR struct v4l2_buffer *)arg, - filep->f_oflags); - break; - - case VIDIOC_CANCEL_DQBUF: - ret = video_cancel_dqbuf(priv, (FAR enum v4l2_buf_type)arg); - break; - - case VIDIOC_STREAMON: - ret = video_streamon(priv, (FAR enum v4l2_buf_type *)arg); - break; - - case VIDIOC_STREAMOFF: - ret = video_streamoff(priv, (FAR enum v4l2_buf_type *)arg); - break; - - case VIDIOC_DO_HALFPUSH: - ret = video_do_halfpush(priv, arg); - break; - - case VIDIOC_TAKEPICT_START: - ret = video_takepict_start(priv, (int32_t)arg); - break; - - case VIDIOC_TAKEPICT_STOP: - ret = video_takepict_stop(priv, arg); - break; - - case VIDIOC_S_SELECTION: - ret = video_s_selection(priv, (FAR struct v4l2_selection *)arg); - break; - - case VIDIOC_G_SELECTION: - ret = video_g_selection(priv, (FAR struct v4l2_selection *)arg); - break; - - case VIDIOC_TRY_FMT: - ret = video_try_fmt(priv, (FAR struct v4l2_format *)arg); - break; - - case VIDIOC_G_FMT: - ret = video_g_fmt(priv, (FAR struct v4l2_format *)arg); - break; - - case VIDIOC_S_FMT: - ret = video_s_fmt(priv, (FAR struct v4l2_format *)arg); - break; - - case VIDIOC_S_PARM: - ret = video_s_parm(priv, (FAR struct v4l2_streamparm *)arg); - break; - - case VIDIOC_G_PARM: - ret = video_g_parm(priv, (FAR struct v4l2_streamparm *)arg); - break; - - case VIDIOC_QUERYCTRL: - ret = video_queryctrl(priv, (FAR struct v4l2_queryctrl *)arg); - break; - - case VIDIOC_QUERY_EXT_CTRL: - ret = video_query_ext_ctrl(priv, - (FAR struct v4l2_query_ext_ctrl *)arg); - break; - - case VIDIOC_QUERYMENU: - ret = video_querymenu(priv, (FAR struct v4l2_querymenu *)arg); - break; - - case VIDIOC_G_CTRL: - ret = video_g_ctrl(priv, (FAR struct v4l2_control *)arg); - break; - - case VIDIOC_S_CTRL: - ret = video_s_ctrl(priv, (FAR struct v4l2_control *)arg); - break; - - case VIDIOC_G_EXT_CTRLS: - ret = video_g_ext_ctrls(priv, (FAR struct v4l2_ext_controls *)arg); - break; - - case VIDIOC_S_EXT_CTRLS: - ret = video_s_ext_ctrls(priv, (FAR struct v4l2_ext_controls *)arg); - break; - - case VIDIOC_G_STD: - ret = -ENODATA; - break; - - case VIDIOC_S_STD: - ret = -EINVAL; - break; - - case V4SIOC_QUERY_EXT_CTRL_SCENE: - ret = video_query_ext_ctrl_scene(priv, - (FAR struct v4s_query_ext_ctrl_scene *)arg); - break; - - case V4SIOC_QUERYMENU_SCENE: - ret = video_querymenu_scene(priv, - (FAR struct v4s_querymenu_scene *)arg); - break; - - case V4SIOC_G_EXT_CTRLS_SCENE: - ret = video_g_ext_ctrls_scene(priv, - (FAR struct v4s_ext_controls_scene *)arg); - break; - - case V4SIOC_S_EXT_CTRLS_SCENE: - ret = video_s_ext_ctrls_scene(priv, - (FAR struct v4s_ext_controls_scene *)arg); - break; - - default: - verr("Unrecognized cmd: %d\n", cmd); - ret = - ENOTTY; - break; - } - - return ret; -} - -static int video_mmap(FAR struct file *filep, FAR struct mm_map_entry_s *map) -{ - FAR struct inode *inode = filep->f_inode; - FAR video_mng_t *priv = inode->i_private; - FAR video_type_inf_t *type_inf = &priv->video_inf; - size_t heapsize = get_heapsize(type_inf); - int ret = -EINVAL; - - if (map->offset >= 0 && map->offset < heapsize && - map->length && map->offset + map->length <= heapsize) - { - map->vaddr = type_inf->bufheap + map->offset; - ret = OK; - } - - return ret; -} - -static int video_poll(FAR struct file *filep, struct pollfd *fds, bool setup) -{ - FAR struct inode *inode = filep->f_inode; - FAR video_mng_t *priv = inode->i_private; - FAR video_type_inf_t *type_inf; - enum v4l2_buf_type buf_type; - irqstate_t flags; - - buf_type = priv->still_inf.state == VIDEO_STATE_CAPTURE ? - V4L2_BUF_TYPE_STILL_CAPTURE : V4L2_BUF_TYPE_VIDEO_CAPTURE; - - type_inf = get_video_type_inf(priv, buf_type); - if (type_inf == NULL) - { - return -EINVAL; - } - - flags = enter_critical_section(); - - if (setup) - { - if (type_inf->fds == NULL) - { - type_inf->fds = fds; - fds->priv = &type_inf->fds; - if (!video_framebuff_is_empty(&type_inf->bufinf)) - { - poll_notify(&fds, 1, POLLIN); - } - } - else - { - leave_critical_section(flags); - return -EBUSY; - } - } - else if (fds->priv) - { - type_inf->fds = NULL; - fds->priv = NULL; - } - - leave_critical_section(flags); - - return OK; -} - -/* Callback function which device driver call when capture has done. */ - -static int video_complete_capture(uint8_t err_code, uint32_t datasize, - FAR const struct timeval *ts, - FAR void *arg) -{ - FAR video_mng_t *vmng = (FAR video_mng_t *)arg; - FAR video_type_inf_t *type_inf; - FAR vbuf_container_t *container = NULL; - enum v4l2_buf_type buf_type; - irqstate_t flags; - imgdata_format_t df[MAX_VIDEO_FMT]; - video_format_t c_fmt[MAX_VIDEO_FMT]; - - flags = enter_critical_section(); - - buf_type = vmng->still_inf.state == VIDEO_STATE_CAPTURE ? - V4L2_BUF_TYPE_STILL_CAPTURE : V4L2_BUF_TYPE_VIDEO_CAPTURE; - - type_inf = get_video_type_inf(vmng, buf_type); - if (type_inf == NULL) - { - leave_critical_section(flags); - return -EINVAL; - } - - poll_notify(&type_inf->fds, 1, POLLIN); - - if (err_code == 0) - { - type_inf->bufinf.vbuf_curr->buf.flags = 0; - if (type_inf->remaining_capnum > 0) - { - type_inf->remaining_capnum--; - } - } - else - { - type_inf->bufinf.vbuf_curr->buf.flags = V4L2_BUF_FLAG_ERROR; - } - - type_inf->bufinf.vbuf_curr->buf.bytesused = datasize; - if (ts != NULL) - { - type_inf->bufinf.vbuf_curr->buf.timestamp = *ts; - } - - video_framebuff_capture_done(&type_inf->bufinf); - - if (is_sem_waited(&type_inf->wait_capture.dqbuf_wait_flg)) - { - /* If waiting capture in DQBUF, - * get/save container and unlock wait - */ - - type_inf->wait_capture.done_container = - video_framebuff_pop_curr_container(&type_inf->bufinf); - type_inf->wait_capture.waitend_cause = - VIDEO_WAITEND_CAUSE_CAPTUREDONE; - nxsem_post(&type_inf->wait_capture.dqbuf_wait_flg); - } - - if (type_inf->remaining_capnum == 0) - { - stop_capture(vmng, buf_type); - type_inf->state = VIDEO_STATE_STREAMOFF; - - /* If stop still stream, notify it to video stream */ - - if (buf_type == V4L2_BUF_TYPE_STILL_CAPTURE && - is_sem_waited(&vmng->video_inf.wait_capture.dqbuf_wait_flg)) - { - vmng->video_inf.wait_capture.waitend_cause = - VIDEO_WAITEND_CAUSE_STILLSTOP; - nxsem_post(&vmng->video_inf.wait_capture.dqbuf_wait_flg); - } - } - else - { - container = video_framebuff_get_vacant_container(&type_inf->bufinf); - if (container == NULL) - { - stop_capture(vmng, buf_type); - type_inf->state = VIDEO_STATE_STREAMON; - } - else - { - get_clipped_format(type_inf->nr_fmt, - type_inf->fmt, - &type_inf->clip, - c_fmt); - - convert_to_imgdatafmt(&c_fmt[VIDEO_FMT_MAIN], - &df[IMGDATA_FMT_MAIN]); - convert_to_imgdatafmt(&c_fmt[VIDEO_FMT_SUB], &df[IMGDATA_FMT_SUB]); - - IMGDATA_SET_BUF(vmng->imgdata, - type_inf->nr_fmt, - df, - (FAR uint8_t *)container->buf.m.userptr, - container->buf.length); - container->buf.sequence = type_inf->seqnum++; - } - } - - leave_critical_section(flags); - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -int video_initialize(FAR const char *devpath) -{ - return video_register(devpath, - g_video_data, - g_video_registered_sensor, - g_video_registered_sensor_num); -} - -int video_uninitialize(FAR const char *devpath) -{ - return video_unregister(devpath); -} - -int video_register(FAR const char *devpath, - FAR struct imgdata_s *data, - FAR struct imgsensor_s **sensors, - size_t sensor_num) -{ - FAR video_mng_t *priv; - size_t allocsize; - int ret; - - /* Input devpath Error Check */ - - if (devpath == NULL || data == NULL) - { - return -EINVAL; - } - - allocsize = strnlen(devpath, MAX_VIDEO_FILE_PATH - 1/* Space for '\0' */); - if (allocsize < 2 || - devpath[0] != '/' || - (allocsize == MAX_VIDEO_FILE_PATH - 1 && - devpath[MAX_VIDEO_FILE_PATH] != '\0')) - { - return -EINVAL; - } - - /* Initialize video device structure */ - - priv = kmm_zalloc(sizeof(video_mng_t)); - if (priv == NULL) - { - verr("Failed to allocate instance\n"); - return -ENOMEM; - } - - priv->imgsensor = get_connected_imgsensor(sensors, sensor_num); - if (priv->imgsensor == NULL) - { - kmm_free(priv); - return -EINVAL; - } - - /* Save device path */ - - priv->devpath = kmm_malloc(allocsize + 1); - if (priv->devpath == NULL) - { - kmm_free(priv); - return -ENOMEM; - } - - memcpy(priv->devpath, devpath, allocsize); - priv->devpath[allocsize] = '\0'; - priv->imgdata = data; - - /* Initialize mutex */ - - nxmutex_init(&priv->lock_open_num); - - /* Register the character driver */ - - ret = register_driver(priv->devpath, &g_video_fops, 0666, priv); - if (ret < 0) - { - verr("Failed to register driver: %d\n", ret); - nxmutex_destroy(&priv->lock_open_num); - kmm_free(priv->devpath); - kmm_free(priv); - return ret; - } - - return OK; -} - -int video_unregister(FAR const char *devpath) -{ - return unregister_driver(devpath); -} - -int imgsensor_register(FAR struct imgsensor_s *sensor) -{ - FAR struct imgsensor_s **new_addr; - int ret = -ENOMEM; - - new_addr = kmm_realloc(g_video_registered_sensor, sizeof(sensor) * - (g_video_registered_sensor_num + 1)); - if (new_addr != NULL) - { - new_addr[g_video_registered_sensor_num++] = sensor; - g_video_registered_sensor = new_addr; - ret = OK; - } - - return ret; -} - -void imgdata_register(FAR struct imgdata_s *data) -{ - g_video_data = data; -} diff --git a/drivers/video/video_framebuff.c b/drivers/video/video_framebuff.c index 922e26fd54fc9..110a01d64d74d 100644 --- a/drivers/video/video_framebuff.c +++ b/drivers/video/video_framebuff.c @@ -41,7 +41,6 @@ static void init_buf_chain(video_framebuff_t *fbuf) fbuf->vbuf_empty = fbuf->vbuf_alloced; fbuf->vbuf_next = NULL; - fbuf->vbuf_curr = NULL; fbuf->vbuf_top = NULL; fbuf->vbuf_tail = NULL; @@ -103,8 +102,10 @@ int video_framebuff_realloc_container(video_framebuff_t *fbuf, int sz) { vbuf_container_t *vbuf; + nxmutex_lock(&fbuf->lock_empty); if (fbuf->container_size == sz) { + nxmutex_unlock(&fbuf->lock_empty); return OK; } @@ -119,6 +120,7 @@ int video_framebuff_realloc_container(video_framebuff_t *fbuf, int sz) } else { + nxmutex_unlock(&fbuf->lock_empty); return -ENOMEM; } } @@ -130,6 +132,8 @@ int video_framebuff_realloc_container(video_framebuff_t *fbuf, int sz) } init_buf_chain(fbuf); + nxmutex_unlock(&fbuf->lock_empty); + return OK; } @@ -168,7 +172,7 @@ void video_framebuff_queue_container(video_framebuff_t *fbuf, { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&fbuf->lock_queue); if (fbuf->vbuf_top != NULL) { fbuf->vbuf_tail->next = tgt; @@ -193,7 +197,7 @@ void video_framebuff_queue_container(video_framebuff_t *fbuf, tgt->next = NULL; } - leave_critical_section(flags); + spin_unlock_irqrestore(&fbuf->lock_queue, flags); } vbuf_container_t *video_framebuff_dq_valid_container(video_framebuff_t *fbuf) @@ -201,13 +205,13 @@ vbuf_container_t *video_framebuff_dq_valid_container(video_framebuff_t *fbuf) vbuf_container_t *ret = NULL; irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&fbuf->lock_queue); if (fbuf->vbuf_top != NULL && fbuf->vbuf_top != fbuf->vbuf_next) { ret = dequeue_vbuf_unsafe(fbuf); } - leave_critical_section(flags); + spin_unlock_irqrestore(&fbuf->lock_queue, flags); return ret; } @@ -217,16 +221,18 @@ video_framebuff_get_vacant_container(video_framebuff_t *fbuf) vbuf_container_t *ret; irqstate_t flags; - flags = enter_critical_section(); - ret = fbuf->vbuf_curr = fbuf->vbuf_next; - leave_critical_section(flags); + flags = spin_lock_irqsave(&fbuf->lock_queue); + ret = fbuf->vbuf_next; + spin_unlock_irqrestore(&fbuf->lock_queue, flags); return ret; } void video_framebuff_capture_done(video_framebuff_t *fbuf) { - fbuf->vbuf_curr = NULL; + irqstate_t flags; + + flags = spin_lock_irqsave(&fbuf->lock_queue); if (fbuf->vbuf_next != NULL) { fbuf->vbuf_next = fbuf->vbuf_next->next; @@ -236,6 +242,8 @@ void video_framebuff_capture_done(video_framebuff_t *fbuf) fbuf->vbuf_tail = fbuf->vbuf_tail->next; } } + + spin_unlock_irqrestore(&fbuf->lock_queue, flags); } void video_framebuff_change_mode(video_framebuff_t *fbuf, @@ -243,7 +251,7 @@ void video_framebuff_change_mode(video_framebuff_t *fbuf, { irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&fbuf->lock_queue); if (fbuf->mode != mode) { if (fbuf->vbuf_tail) @@ -262,7 +270,7 @@ void video_framebuff_change_mode(video_framebuff_t *fbuf, fbuf->mode = mode; } - leave_critical_section(flags); + spin_unlock_irqrestore(&fbuf->lock_queue, flags); } vbuf_container_t *video_framebuff_pop_curr_container(video_framebuff_t *fbuf) @@ -270,12 +278,12 @@ vbuf_container_t *video_framebuff_pop_curr_container(video_framebuff_t *fbuf) vbuf_container_t *ret = NULL; irqstate_t flags; - flags = enter_critical_section(); + flags = spin_lock_irqsave(&fbuf->lock_queue); if (fbuf->vbuf_top != NULL) { ret = dequeue_vbuf_unsafe(fbuf); } - leave_critical_section(flags); + spin_unlock_irqrestore(&fbuf->lock_queue, flags); return ret; } diff --git a/drivers/video/video_framebuff.h b/drivers/video/video_framebuff.h index 568d45e27e8b4..1aed3de6e57c5 100644 --- a/drivers/video/video_framebuff.h +++ b/drivers/video/video_framebuff.h @@ -26,7 +26,9 @@ ****************************************************************************/ #include + #include +#include /**************************************************************************** * Public Types @@ -42,14 +44,14 @@ typedef struct vbuf_container_s vbuf_container_t; struct video_framebuff_s { - enum v4l2_buf_mode mode; + enum v4l2_buf_mode mode; + spinlock_t lock_queue; mutex_t lock_empty; int container_size; vbuf_container_t *vbuf_alloced; vbuf_container_t *vbuf_empty; vbuf_container_t *vbuf_top; vbuf_container_t *vbuf_tail; - vbuf_container_t *vbuf_curr; vbuf_container_t *vbuf_next; }; diff --git a/drivers/video/vnc/vnc_fbdev.c b/drivers/video/vnc/vnc_fbdev.c index 49c2681840472..85d148bf8f5cd 100644 --- a/drivers/video/vnc/vnc_fbdev.c +++ b/drivers/video/vnc/vnc_fbdev.c @@ -581,102 +581,6 @@ static inline int vnc_wait_start(int display) * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: up_fbinitialize - * - * Description: - * Initialize the framebuffer video hardware associated with the display. - * - * Input Parameters: - * display - In the case of hardware with multiple displays, this - * specifies the display. Normally this is zero. - * - * Returned Value: - * Zero is returned on success; a negated errno value is returned on any - * failure. - * - ****************************************************************************/ - -int up_fbinitialize(int display) -{ - int ret; - FAR struct vnc_session_s *session; -#if defined (CONFIG_VNCSERVER_TOUCH) || defined (CONFIG_VNCSERVER_KBD) - char devname[NAME_MAX]; -#endif - - DEBUGASSERT(display >= 0 && display < RFB_MAX_DISPLAYS); - - /* Start the VNC server kernel thread. */ - - ret = vnc_start_server(display); - - if (ret < 0) - { - gerr("ERROR: vnc_start_server() failed: %d\n", ret); - return ret; - } - - /* Wait for the VNC server to be ready */ - - ret = vnc_wait_start(display); - - if (ret < 0) - { - gerr("ERROR: wait for vnc server start failed: %d\n", ret); - return ret; - } - - /* Save the input callout function information in the session structure. */ - - session = g_vnc_sessions[display]; - session->arg = session; - -#ifdef CONFIG_VNCSERVER_TOUCH - - ret = snprintf(devname, sizeof(devname), - CONFIG_VNCSERVER_TOUCH_DEVNAME "%d", display); - - if (ret < 0) - { - gerr("ERROR: Format vnc touch driver path failed.\n"); - return ret; - } - - ret = vnc_touch_register(devname, session); - - if (ret < 0) - { - gerr("ERROR: Initial vnc touch driver failed.\n"); - return ret; - } - - session->mouseout = vnc_touch_event; -#endif - -#ifdef CONFIG_VNCSERVER_KBD - ret = snprintf(devname, sizeof(devname), - CONFIG_VNCSERVER_KBD_DEVNAME "%d", display); - if (ret < 0) - { - gerr("ERROR: Format vnc keyboard driver path failed.\n"); - return ret; - } - - ret = vnc_kbd_register(devname, session); - - if (ret < 0) - { - gerr("ERROR: Initial vnc keyboard driver failed.\n"); - return ret; - } - - session->kbdout = vnc_kbd_event; -#endif - - return ret; -} - /**************************************************************************** * Name: vnc_fbinitialize * @@ -767,77 +671,149 @@ int vnc_fbinitialize(int display, vnc_kbdout_t kbdout, } /**************************************************************************** - * Name: up_fbgetvplane + * Name: vnc_fb_register * * Description: - * Return a a reference to the framebuffer object for the specified video - * plane of the specified plane. Many OSDs support multiple planes of - * video. + * Register the framebuffer support for the specified display. * * Input Parameters: - * display - In the case of hardware with multiple displays, this - * specifies the display. Normally this is zero. - * vplane - Identifies the plane being queried. + * display - The display number for the case of boards supporting multiple + * displays or for hardware that supports multiple + * layers (each layer is consider a display). Typically zero. * * Returned Value: - * A non-NULL pointer to the frame buffer access structure is returned on - * success; NULL is returned on any failure. + * Zero (OK) is returned success; a negated errno value is returned on any + * failure. * ****************************************************************************/ -FAR struct fb_vtable_s *up_fbgetvplane(int display, int vplane) +int vnc_fb_register(int display) { + FAR struct fb_vtable_s *vtable; FAR struct vnc_session_s *session; FAR struct vnc_fbinfo_s *fbinfo; +#if defined(CONFIG_VNCSERVER_TOUCH) || defined(CONFIG_VNCSERVER_KBD) + char devname[NAME_MAX]; +#endif + int ret; DEBUGASSERT(display >= 0 && display < RFB_MAX_DISPLAYS); - session = g_vnc_sessions[display]; - /* Verify that the session is still valid */ + /* Start the VNC server kernel thread. */ + + ret = vnc_start_server(display); + + if (ret < 0) + { + gerr("ERROR: vnc_start_server() failed: %d\n", ret); + return ret; + } + + /* Wait for the VNC server to be ready */ + + ret = vnc_wait_start(display); - if (session == NULL) + if (ret < 0) { - return NULL; + gerr("ERROR: wait for vnc server start failed: %d\n", ret); + return ret; } - if (vplane == 0) + /* Save the input callout function information in the session structure. */ + + session = g_vnc_sessions[display]; + session->arg = session; + +#ifdef CONFIG_VNCSERVER_TOUCH + ret = snprintf(devname, sizeof(devname), + CONFIG_VNCSERVER_TOUCH_DEVNAME "%d", display); + + if (ret < 0) { - /* Has the framebuffer information been initialized for this display? */ + gerr("ERROR: Format vnc touch driver path failed.\n"); + return ret; + } - fbinfo = &g_fbinfo[display]; - if (!fbinfo->initialized) - { - fbinfo->vtable.getvideoinfo = up_getvideoinfo, - fbinfo->vtable.getplaneinfo = up_getplaneinfo, + ret = vnc_touch_register(devname, session); + + if (ret < 0) + { + gerr("ERROR: Initial vnc touch driver failed.\n"); + return ret; + } + + session->mouseout = vnc_touch_event; +#endif + +#ifdef CONFIG_VNCSERVER_KBD + ret = snprintf(devname, sizeof(devname), + CONFIG_VNCSERVER_KBD_DEVNAME "%d", display); + if (ret < 0) + { + gerr("ERROR: Format vnc keyboard driver path failed.\n"); + return ret; + } + + ret = vnc_kbd_register(devname, session); + if (ret < 0) + { + gerr("ERROR: Initial vnc keyboard driver failed.\n"); + goto err_kbd_register_failed; + } + + session->kbdout = vnc_kbd_event; +#endif + + /* Has the framebuffer information been initialized for this display? */ + + fbinfo = &g_fbinfo[display]; + if (!fbinfo->initialized) + { + fbinfo->vtable.getvideoinfo = up_getvideoinfo, + fbinfo->vtable.getplaneinfo = up_getplaneinfo, #ifdef CONFIG_FB_CMAP - fbinfo->vtable.getcmap = up_getcmap, - fbinfo->vtable.putcmap = up_putcmap, + fbinfo->vtable.getcmap = up_getcmap, + fbinfo->vtable.putcmap = up_putcmap, #endif #ifdef CONFIG_FB_HWCURSOR - fbinfo->vtable.getcursor = up_getcursor, - fbinfo->vtable.setcursor = up_setcursor, + fbinfo->vtable.getcursor = up_getcursor, + fbinfo->vtable.setcursor = up_setcursor, #endif #ifdef CONFIG_FB_SYNC - fbinfo->vtable.waitforvsync = up_waitforsync; + fbinfo->vtable.waitforvsync = up_waitforsync; #endif - fbinfo->vtable.updatearea = up_updateearea, - fbinfo->display = display; - fbinfo->initialized = true; - } - - return &fbinfo->vtable; + fbinfo->vtable.updatearea = up_updateearea, + fbinfo->display = display; + fbinfo->initialized = true; } - else + + vtable = &fbinfo->vtable; + + ret = fb_register_device(display, 0, vtable); + if (ret < 0) { - return NULL; + gerr("ERROR: Initial vnc keyboard driver failed.\n"); + goto err_fb_register_failed; } + + return OK; + +err_fb_register_failed: +#ifdef CONFIG_VNCSERVER_KBD + vnc_kbd_unregister(session, devname); +err_kbd_register_failed: +#endif +#ifdef CONFIG_VNCSERVER_TOUCH + vnc_touch_unregister(session, devname); +#endif + return ret; } /**************************************************************************** - * Name: up_fbuninitialize + * Name: vnc_fb_unregister * * Description: - * Uninitialize the framebuffer support for the specified display. + * Unregister the framebuffer support for the specified display. * * Input Parameters: * display - In the case of hardware with multiple displays, this @@ -848,10 +824,10 @@ FAR struct fb_vtable_s *up_fbgetvplane(int display, int vplane) * ****************************************************************************/ -void up_fbuninitialize(int display) +void vnc_fb_unregister(int display) { FAR struct vnc_session_s *session; -#if defined(CONFIG_VNCSERVER_TOUCH) || defined (CONFIG_VNCSERVER_KBD) +#if defined(CONFIG_VNCSERVER_TOUCH) || defined(CONFIG_VNCSERVER_KBD) int ret; char devname[NAME_MAX]; #endif diff --git a/drivers/video/vnc/vnc_receiver.c b/drivers/video/vnc/vnc_receiver.c index 5f0dd7d0346a2..7c0840d385c19 100644 --- a/drivers/video/vnc/vnc_receiver.c +++ b/drivers/video/vnc/vnc_receiver.c @@ -330,7 +330,7 @@ int vnc_receiver(FAR struct vnc_session_s *session) * CONFIG_VNCSERVER_KBD. */ - session->kbdout(&session->kbd, keyevent->down, + session->kbdout(session->arg, keyevent->down, (FAR const uint8_t *)keyevent->key); #else diff --git a/drivers/virt/Kconfig b/drivers/virt/Kconfig new file mode 100644 index 0000000000000..6eee0ff10d236 --- /dev/null +++ b/drivers/virt/Kconfig @@ -0,0 +1,29 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# +# +# +menuconfig VIRT + bool "Virtualization" + default n + ---help--- + Drivers for virtualized and emulated devices + +if VIRT + +config VIRT_QEMU_PCI_TEST + bool "Driver for QEMU PCI test device" + default n + select PCI + ---help--- + Driver for QEMU PCI test device + +config VIRT_QEMU_EDU + bool "Driver for QEMU EDU test device" + default n + select PCI + ---help--- + Driver for QEMU EDU test device + +endif # VIRT diff --git a/drivers/virt/Make.defs b/drivers/virt/Make.defs new file mode 100644 index 0000000000000..856a9db7cb2bd --- /dev/null +++ b/drivers/virt/Make.defs @@ -0,0 +1,37 @@ +############################################################################ +# drivers/virt/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +ifeq ($(CONFIG_VIRT_QEMU_PCI_TEST),y) +CSRCS += qemu_pci_test.c +endif + +ifeq ($(CONFIG_VIRT_QEMU_EDU),y) +CSRCS += qemu_edu.c +endif + +# Include virt device driver build support +# +ifeq ($(CONFIG_VIRT),y) + +DEPPATH += --dep-path virt +VPATH += :virt +CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)drivers$(DELIM)virt + +endif diff --git a/drivers/virt/qemu_edu.c b/drivers/virt/qemu_edu.c new file mode 100644 index 0000000000000..0117d995eb677 --- /dev/null +++ b/drivers/virt/qemu_edu.c @@ -0,0 +1,470 @@ +/***************************************************************************** + * drivers/virt/qemu_edu.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + *****************************************************************************/ + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/***************************************************************************** + * Pre-processor Definitions + *****************************************************************************/ + +/* Registers defined for device. Size 4 for < 0x80. Size 8 for >= 0x80. */ + +#define EDU_REG_ID 0x00 /* Identification */ +#define EDU_REG_LIVE 0x04 /* Liveness Check */ +#define EDU_REG_FAC 0x08 /* Factorial Computation */ +#define EDU_REG_STATUS 0x20 /* Status */ +#define EDU_REG_INT_STATUS 0x24 /* Interupt Status */ +#define EDU_REG_INT_RAISE 0x60 /* Raise an interrupt */ +#define EDU_REG_INT_ACK 0x64 /* Acknowledge interrupt */ +#define EDU_REG_DMA_SOURCE 0x80 /* Source address for DMA transfer */ +#define EDU_REG_DMA_DEST 0x88 /* Destination address for DMA transfer */ +#define EDU_REG_DMA_COUNT 0x90 /* Size of area to transfer with DMA */ +#define EDU_REG_DMA_CMD 0x98 /* Control DMA tranfer */ + +#define EDU_CONTROL_BAR_ID 0 +#define EDU_CONTROL_BAR_OFFSET PCI_HEADER_NORM_BAR0 + +/* One 4096 bytes long buffer at offset 0x40000 is available in the + * EDU device + */ + +#define QEMU_EDU_DMABUF_OFFSET 0x40000 + +/***************************************************************************** + * Private Types + *****************************************************************************/ + +struct qemu_edu_priv_s +{ + uintptr_t base_addr; + sem_t isr_done; + uint32_t test_result; +}; + +/***************************************************************************** + * Private Functions Definitions + *****************************************************************************/ + +static void qemu_edu_write_reg32(uintptr_t addr, uint32_t val); + +static uint32_t qemu_edu_read_reg32(uintptr_t addr); + +static void qemu_edu_write_reg64(uintptr_t addr, uint64_t val); + +static void qemu_edu_test_poll(FAR struct pci_dev_s *dev, + uintptr_t base_addr); + +static void qemu_edu_test_intx(FAR struct pci_dev_s *dev, + struct qemu_edu_priv_s *drv_priv); + +static int qemu_edu_interrupt(int irq, void *context, FAR void *arg); + +static int qemu_edu_probe(FAR struct pci_bus_s *bus, + FAR const struct pci_dev_type_s *type, + uint16_t bdf); + +/***************************************************************************** + * Public Data + *****************************************************************************/ + +const struct pci_dev_type_s g_pci_type_qemu_edu = +{ + .vendor = 0x1234, + .device = 0x11e8, + .class_rev = PCI_ID_ANY, + .name = "Qemu PCI EDU device", + .probe = qemu_edu_probe +}; + +/***************************************************************************** + * Private Functions + *****************************************************************************/ + +/***************************************************************************** + * Name: qemu_edu_write_reg32 + * + * Description: + * Provide a write interface for 32bit mapped registers + * + * Input Parameters: + * addr - Register address + * val - Value to assign to register + * + *****************************************************************************/ + +static void qemu_edu_write_reg32(uintptr_t addr, uint32_t val) +{ + *(volatile uint32_t *)addr = val; +} + +/***************************************************************************** + * Name: qemu_edu_read_reg32 + * + * Description: + * Provide a read interface for 32bit mapped registers + * + * Returned Value: + * Register value + * + *****************************************************************************/ + +static uint32_t qemu_edu_read_reg32(uintptr_t addr) +{ + return *(volatile uint32_t *)addr; +} + +/***************************************************************************** + * Name: qemu_edu_write_reg64 + * + * Description: + * Provide a write interface for 64bit mapped registers + * + * Input Parameters: + * addr - Register address + * val - Value to assign to register + * + *****************************************************************************/ + +static void qemu_edu_write_reg64(uintptr_t addr, uint64_t val) +{ + *(volatile uint64_t *)addr = val; +} + +/***************************************************************************** + * Name: qemu_edu_test_poll + * + * Description: + * Performs basic functional test of PCI device and MMIO using polling + * of mapped register interfaces. + * + * Input Parameters: + * bus - An PCI device + * base_addr - Base address of device register space + * + *****************************************************************************/ + +static void qemu_edu_test_poll(FAR struct pci_dev_s *dev, uintptr_t base_addr) +{ + uint32_t test_value; + uint32_t test_read; + + pciinfo("Identification: 0x%08xu\n", + qemu_edu_read_reg32(base_addr + EDU_REG_ID)); + + /* Test Live Check */ + + test_value = 0xdeadbeef; + qemu_edu_write_reg32(base_addr + EDU_REG_LIVE, test_value); + test_read = qemu_edu_read_reg32(base_addr + EDU_REG_LIVE); + pciinfo("Live Check: Wrote: 0x%08x Read: 0x%08x Error Bits 0x%08x\n", + test_value, test_read, test_read ^ ~test_value); + pciinfo("TEST %s\n", ((test_read ^ ~test_value) == 0) ? "PASS" : "FAIL"); + + /* Test Factorial */ + + test_value = 10; + qemu_edu_write_reg32(base_addr + EDU_REG_STATUS, 0); + qemu_edu_write_reg32(base_addr + EDU_REG_FAC, test_value); + while (qemu_edu_read_reg32(base_addr + EDU_REG_STATUS) & 0x01) + { + pciinfo("Waiting to compute factorial..."); + usleep(10000); + } + + test_read = qemu_edu_read_reg32(base_addr + EDU_REG_FAC); + pciinfo("Computed factorial of %d as %d\n", test_value, test_read); + pciinfo("TEST %s\n", (test_read == 3628800) ? "PASS" : "FAIL"); +} + +/***************************************************************************** + * Name: qemu_edu_test_intx + * + * Description: + * Performs basic functional test of PCI device and MMIO using INTx + * + * Input Parameters: + * bus - An PCI device + * drv_priv - Struct containing internal state of driver + * + *****************************************************************************/ + +static void qemu_edu_test_intx(FAR struct pci_dev_s *dev, + FAR struct qemu_edu_priv_s *drv_priv) +{ + uintptr_t base_addr = drv_priv->base_addr; + uint32_t test_value; + + pciinfo("Identification: 0x%08xu\n", + qemu_edu_read_reg32(base_addr + EDU_REG_ID)); + + /* Test Read/Write */ + + test_value = 0xdeadbeef; + pciinfo("Triggering interrupt with value 0x%08x\n", test_value); + qemu_edu_write_reg32(base_addr + EDU_REG_INT_RAISE, test_value); + sem_wait(&drv_priv->isr_done); + pciinfo("TEST %s\n", + (drv_priv->test_result == test_value) ? "PASS" : "FAIL"); + + /* Test Factorial */ + + test_value = 5; + pciinfo("Computing factorial of %d\n", test_value); + qemu_edu_write_reg32(base_addr + EDU_REG_STATUS, 0x80); + qemu_edu_write_reg32(base_addr + EDU_REG_FAC, test_value); + sem_wait(&drv_priv->isr_done); + pciinfo("TEST %s\n", (drv_priv->test_result == 120) ? "PASS" : "FAIL"); + + /* Test ISR Status Cleanup */ + + qemu_edu_write_reg32(base_addr + EDU_REG_INT_RAISE, test_value); + sem_wait(&drv_priv->isr_done); + pciinfo("TEST %s\n", + (drv_priv->test_result == test_value) ? "PASS" : "FAIL"); +} + +/***************************************************************************** + * Name: qemu_edu_test_dma + * + * Description: + * Performs dma functional test of PCI device + * + * Input Parameters: + * bus - An PCI device + * drv_priv - Struct containing internal state of driver + * + *****************************************************************************/ + +static void qemu_edu_test_dma(FAR struct pci_dev_s *dev, + FAR struct qemu_edu_priv_s *drv_priv) +{ + uintptr_t base_addr = drv_priv->base_addr; + FAR void *test_block; + size_t block_size = 2048; + int i; + uint32_t psrand; + uint32_t tx_checksum; + uint32_t rx_checksum; + uint32_t dev_addr = QEMU_EDU_DMABUF_OFFSET; + + pciinfo("Identification: 0x%08xu\n", + qemu_edu_read_reg32(base_addr + EDU_REG_ID)); + + test_block = kmm_malloc(block_size); + for (i = 0; i < block_size; i++) + { + *((uint8_t *)test_block + i) = i & 0xff; + } + + tx_checksum = 0; + psrand = 0x0011223344; + for (i = 0; i < (block_size / 4); i++) + { + /* Fill the memory block with "random" data */ + + psrand ^= psrand << 13; + psrand ^= psrand >> 17; + psrand ^= psrand << 5; + *((uint32_t *)test_block + i) = psrand; + tx_checksum += psrand; + } + + pciinfo("Test block checksum 0x%08x\n", tx_checksum); + qemu_edu_write_reg64(base_addr + EDU_REG_DMA_SOURCE, (uint64_t)test_block); + qemu_edu_write_reg64(base_addr + EDU_REG_DMA_DEST, (uint64_t)dev_addr); + qemu_edu_write_reg64(base_addr + EDU_REG_DMA_COUNT, (uint64_t)block_size); + qemu_edu_write_reg32(base_addr + EDU_REG_STATUS, 0x00); + qemu_edu_write_reg64(base_addr + EDU_REG_DMA_CMD, 0x01 | 0x04); + sem_wait(&drv_priv->isr_done); + + pciinfo("DMA transfer to device complete.\n"); + + qemu_edu_write_reg64(base_addr + EDU_REG_DMA_DEST, (uint64_t)test_block); + qemu_edu_write_reg64(base_addr + EDU_REG_DMA_SOURCE, (uint64_t)dev_addr); + qemu_edu_write_reg64(base_addr + EDU_REG_DMA_COUNT, (uint64_t)block_size); + qemu_edu_write_reg32(base_addr + EDU_REG_STATUS, 0x00); + qemu_edu_write_reg64(base_addr + EDU_REG_DMA_CMD, 0x01 | 0x02 | 0x04); + sem_wait(&drv_priv->isr_done); + + pciinfo("DMA transfer from device complete.\n"); + rx_checksum = 0; + for (i = 0; i < block_size / 4; i++) + { + rx_checksum += *((uint32_t *)test_block + i); + } + + pciinfo("Received block checksum 0x%08x\n", rx_checksum); + pciinfo("TEST %s\n", (rx_checksum == tx_checksum) ? "PASS" : "FAIL"); +} + +/***************************************************************************** + * Name: qemu_edu_interrupt + * + * Description: + * EDU interrupt handler + * + *****************************************************************************/ + +static int qemu_edu_interrupt(int irq, FAR void *context, FAR void *arg) +{ + FAR struct qemu_edu_priv_s *drv_priv = (struct qemu_edu_priv_s *)arg; + uintptr_t base_addr; + uint32_t status; + + base_addr = drv_priv->base_addr; + status = qemu_edu_read_reg32(base_addr + EDU_REG_INT_STATUS); + + qemu_edu_write_reg32(base_addr + EDU_REG_INT_ACK, ~0U); + switch (status) + { + /* Factorial triggered */ + + case 0x1: + { + drv_priv->test_result + = qemu_edu_read_reg32(base_addr + EDU_REG_FAC); + pciinfo("Computed factorial: %d\n", drv_priv->test_result); + break; + } + + /* DMA triggered */ + + case 0x100: + { + pciinfo("DMA transfer complete\n"); + break; + } + + /* Generic write */ + + default: + { + drv_priv->test_result = status; + pciinfo("Received value: 0x%08x\n", status); + break; + } + } + + sem_post(&drv_priv->isr_done); + return OK; +} + +/***************************************************************************** + * Name: qemu_edu_probe + * + * Description: + * Initialize device + * + *****************************************************************************/ + +static int qemu_edu_probe(FAR struct pci_bus_s *bus, + FAR const struct pci_dev_type_s *type, + uint16_t bdf) +{ + struct qemu_edu_priv_s drv_priv; + struct pci_dev_s dev; + uint32_t bar; + uintptr_t bar_addr; + uint8_t irq; + + /* Get dev */ + + dev.bus = bus; + dev.type = type; + dev.bdf = bdf; + + pci_enable_bus_master(&dev); + pciinfo("Enabled bus mastering\n"); + pci_enable_io(&dev, PCI_SYS_RES_MEM); + pciinfo("Enabled memory resources\n"); + + if (pci_bar_valid(&dev, EDU_CONTROL_BAR_ID) != OK) + { + pcierr("Control BAR is not valid\n"); + DEBUGPANIC(); + return -EINVAL; + } + + bar_addr = pci_bar_addr(&dev, EDU_CONTROL_BAR_ID); + bar = bus->ops->pci_cfg_read(&dev, EDU_CONTROL_BAR_OFFSET, 4); + if ((bar & PCI_BAR_LAYOUT_MASK) != PCI_BAR_LAYOUT_MEM) + { + pcierr("Control bar expected to be MMIO\n"); + DEBUGPANIC(); + return -EINVAL; + } + + if (bus->ops->pci_map_bar(bar_addr, + pci_bar_size(&dev, EDU_CONTROL_BAR_ID)) != OK) + { + pcierr("Failed to map address space\n"); + DEBUGPANIC(); + return -EINVAL; + } + + pciinfo("Device Initialized\n"); + + /* Run Poll Tests */ + + qemu_edu_test_poll(&dev, bar_addr); + + /* Run IRQ Tests */ + + drv_priv.base_addr = bar_addr; + sem_init(&drv_priv.isr_done, 0, 0); + sem_setprotocol(&drv_priv.isr_done, SEM_PRIO_NONE); + + irq = IRQ0 + bus->ops->pci_cfg_read(&dev, PCI_HEADER_NORM_INT_LINE, 1); + pciinfo("Attaching IRQ %d to %p\n", irq, qemu_edu_interrupt); + irq_attach(irq, (xcpt_t)qemu_edu_interrupt, (void *)&drv_priv); + up_enable_irq(irq); + + qemu_edu_test_intx(&dev, &drv_priv); + qemu_edu_test_dma(&dev, &drv_priv); + + up_disable_irq(irq); + irq_detach(irq); + sem_destroy(&drv_priv.isr_done); + + /* Run MSI Tests */ + + /* Really should be cleaning up the mapped memory */ + + return OK; +} diff --git a/drivers/virt/qemu_pci_test.c b/drivers/virt/qemu_pci_test.c new file mode 100644 index 0000000000000..9ab30569b4e51 --- /dev/null +++ b/drivers/virt/qemu_pci_test.c @@ -0,0 +1,274 @@ +/***************************************************************************** + * drivers/virt/qemu_pci_test.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + *****************************************************************************/ + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/***************************************************************************** + * Pre-processor Definitions + *****************************************************************************/ + +/***************************************************************************** + * Private Functions Definitions + *****************************************************************************/ + +static uint32_t mem_read(FAR const volatile void *addr, int width); + +static void mem_write(FAR const volatile void *addr, uint32_t val, int width); + +static int qemu_pci_test_probe(FAR struct pci_bus_s *bus, + FAR const struct pci_dev_type_s *type, + uint16_t bdf); + +/***************************************************************************** + * Public Data + *****************************************************************************/ + +const struct pci_dev_type_s g_pci_type_qemu_pci_test = +{ + .vendor = 0x1b36, + .device = 0x0005, + .class_rev = PCI_ID_ANY, + .name = "Qemu PCI test device", + .probe = qemu_pci_test_probe +}; + +/***************************************************************************** + * Private Types + *****************************************************************************/ + +struct pci_test_dev_hdr_s +{ + uint8_t test; /* write-only, starts a given test number */ + uint8_t width; /* read-only, type and width of access for a test */ + uint8_t pad0[2]; + uint32_t offset; /* read-only, offset in this BAR for a given test */ + uint32_t data; /* read-only, data to use for a given test */ + uint32_t count; /* for debugging. number of writes detected. */ + uint8_t name[]; /* for debugging. 0-terminated ASCII string. */ +}; + +/* Structure the read and write helpers */ + +struct pci_test_dev_ops_s +{ + uint32_t (*read)(FAR const volatile void *addr, int width); + void (*write)(FAR const volatile void *addr, uint32_t val, int width); +}; + +/***************************************************************************** + * Private Data + *****************************************************************************/ + +static struct pci_test_dev_ops_s g_mem_ops = +{ + .read = mem_read, + .write = mem_write +}; + +/***************************************************************************** + * Private Functions + *****************************************************************************/ + +static uint32_t mem_read(FAR const volatile void *addr, int unused) +{ + return *(volatile uint32_t *)addr; +} + +static void mem_write(FAR const volatile void *addr, uint32_t val, int unused) +{ + *(volatile uint32_t *)addr = val; +} + +static bool qemu_pci_test_bar(FAR struct pci_test_dev_ops_s *test_ops, + FAR struct pci_test_dev_hdr_s *test_hdr, + uint16_t test_num) +{ + const int write_limit = 8; + uint32_t count; + uint32_t data; + uint32_t offset; + uint8_t width; + int write_cnt; + int i; + char testname[32]; + + pciinfo("WRITING Test# %d %p\n", test_num, &test_hdr->test); + test_ops->write(&test_hdr->test, test_num, 1); + + /* Reading of the string is a little ugly to handle the case where + * we must use the port access methods. For memory map we would + * be able to just read directly. + */ + + testname[sizeof(testname) - 1] = 0; + for (i = 0; i < sizeof(testname); i++) + { + testname[i] = (char)test_ops->read((void *)&test_hdr->name + i, 1); + if (testname[i] == 0) + { + break; + } + } + + pciinfo("Running test: %s\n", testname); + + count = test_ops->read(&test_hdr->count, 4); + pciinfo("COUNT: %04x\n", count); + if (count != 0) + { + return false; + } + + width = test_ops->read(&test_hdr->width, 1); + pciinfo("Width: %d\n", width); + + if (width == 0 || width > 4) + { + return false; + } + + data = test_ops->read(&test_hdr->data, 4); + pciinfo("Data: %04x\n", data); + + offset = test_ops->read(&test_hdr->offset, 4); + pciinfo("Offset: %04x\n", offset); + + for (write_cnt = 0; write_cnt < write_limit; write_cnt++) + { + pciinfo("Issuing WRITE to %p %x %d\n", + (void *)test_hdr + offset, + data, width); + test_ops->write((void *)test_hdr + offset, data, width); + } + + count = test_ops->read(&test_hdr->count, 4); + pciinfo("COUNT: %04x\n", count); + + if (!count) + { + return true; + } + + return (int)count == write_cnt; +} + +/***************************************************************************** + * Name: qemu_pci_test_probe + * + * Description: + * Initialize device + * + *****************************************************************************/ + +static int qemu_pci_test_probe(FAR struct pci_bus_s *bus, + FAR const struct pci_dev_type_s *type, + uint16_t bdf) +{ + struct pci_dev_s dev; + struct pci_test_dev_ops_s io_ops; + struct pci_test_dev_ops_s *test_ops; + struct pci_test_dev_hdr_s *test_hdr; + uint8_t bar_id; + uint32_t bar; + uint64_t bar_addr; + uint16_t test_cnt; + + /* Get dev */ + + dev.bus = bus; + dev.type = type; + dev.bdf = bdf; + + /* Get io ops */ + + io_ops.read = bus->ops->pci_io_read; + io_ops.write = bus->ops->pci_io_write; + + pci_enable_bus_master(&dev); + pciinfo("Enabled bus mastering\n"); + pci_enable_io(&dev, PCI_SYS_RES_MEM); + pci_enable_io(&dev, PCI_SYS_RES_IOPORT); + pciinfo("Enabled i/o port and memory resources\n"); + + for (bar_id = 0; bar_id < PCI_BAR_CNT; bar_id++) + { + /* Need to query the BAR for IO vs MEM + * Also handle if the bar is 64bit address + */ + + if (pci_bar_valid(&dev, bar_id) != OK) + { + continue; + } + + bar = bus->ops->pci_cfg_read(&dev, + PCI_HEADER_NORM_BAR0 + (bar_id * 4), 4); + + bar_addr = pci_bar_addr(&dev, bar_id); + test_hdr = (struct pci_test_dev_hdr_s *)bar_addr; + + if ((bar & PCI_BAR_LAYOUT_MASK) == PCI_BAR_LAYOUT_MEM) + { + test_ops = &g_mem_ops; + + /* If the BAR is MMIO the it must be mapped */ + + bus->ops->pci_map_bar(bar_addr, pci_bar_size(&dev, bar_id)); + } + else + { + test_ops = &io_ops; + } + + for (test_cnt = 0; test_cnt < 0xffff; test_cnt++) + { + if (!qemu_pci_test_bar(test_ops, test_hdr, test_cnt)) + { + break; + } + + pciinfo("Test Completed BAR [%d] TEST [%d]\n", bar_id, test_cnt); + } + + if (pci_bar_is_64(&dev, bar_id)) + { + bar_id++; + } + } + + return OK; +} diff --git a/drivers/virtio/CMakeLists.txt b/drivers/virtio/CMakeLists.txt index 9d9097e7ea574..9834d0fe4ee58 100644 --- a/drivers/virtio/CMakeLists.txt +++ b/drivers/virtio/CMakeLists.txt @@ -31,6 +31,14 @@ if(CONFIG_DRIVERS_VIRTIO_BLK) list(APPEND SRCS virtio-blk.c) endif() +if(CONFIG_DRIVERS_VIRTIO_GPU) + list(APPEND SRCS virtio-gpu.c) +endif() + +if(CONFIG_DRIVERS_VIRTIO_INPUT) + list(APPEND SRCS virtio-input.c) +endif() + if(CONFIG_DRIVERS_VIRTIO_NET) list(APPEND SRCS virtio-net.c) endif() @@ -39,6 +47,10 @@ if(CONFIG_DRIVERS_VIRTIO_RNG) list(APPEND SRCS virtio-rng.c) endif() +if(CONFIG_DRIVERS_VIRTIO_RPMB) + list(APPEND SRCS virtio-rpmb.c) +endif() + if(CONFIG_DRIVERS_VIRTIO_SERIAL) list(APPEND SRCS virtio-serial.c) endif() diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig index b70060a6ebc75..dbb87a140f2cb 100644 --- a/drivers/virtio/Kconfig +++ b/drivers/virtio/Kconfig @@ -5,7 +5,7 @@ menuconfig DRIVERS_VIRTIO bool "Virtio Device Support" - depends on OPENAMP + select OPENAMP default n if DRIVERS_VIRTIO diff --git a/drivers/virtio/virtio-gpu.c b/drivers/virtio/virtio-gpu.c index fd528d8ccba4b..1544c8aaa52eb 100644 --- a/drivers/virtio/virtio-gpu.c +++ b/drivers/virtio/virtio-gpu.c @@ -133,6 +133,8 @@ static FAR struct virtio_gpu_priv_s *g_virtio_gpu[VIRTIO_GPU_MAX_DISP]; /**************************************************************************** * Name: virtio_gpu_send_cmd + * Note: the caller should not touch `buf` after calling this, as it will be + * freed either here or in virtio_gpu_done(). ****************************************************************************/ static int virtio_gpu_send_cmd(FAR struct virtqueue *vq, @@ -146,6 +148,7 @@ static int virtio_gpu_send_cmd(FAR struct virtqueue *vq, sem_t sem; struct virtio_gpu_cookie_s cookie; + virtio_free_buf(vq->vq_dev, buf); nxsem_init(&sem, 0, 0); cookie.blocking = true; cookie.p = &sem; @@ -180,10 +183,14 @@ static int virtio_gpu_send_cmd(FAR struct virtqueue *vq, } else { - virtio_free_buf(vq->vq_dev, buf); kmm_free(cookie); } } + + if (buf && ret < 0) + { + virtio_free_buf(vq->vq_dev, buf); + } } return ret; diff --git a/drivers/virtio/virtio-mmio.c b/drivers/virtio/virtio-mmio.c index b9d1f90ebba42..2d1d404c819a1 100644 --- a/drivers/virtio/virtio-mmio.c +++ b/drivers/virtio/virtio-mmio.c @@ -553,16 +553,9 @@ static void virtio_mmio_write_config(FAR struct virtio_device *vdev, uint16_t u16data; uint8_t u8data; - if (vdev->id.version == VIRTIO_MMIO_VERSION_1 || length > 8) + if (vdev->id.version == VIRTIO_MMIO_VERSION_1) { - FAR char *s = src; - int i; - for (i = 0; i < length; i++) - { - metal_io_write8(&vmdev->cfg_io, write_offset + i, s[i]); - } - - return; + goto byte_write; } switch (length) @@ -587,7 +580,15 @@ static void virtio_mmio_write_config(FAR struct virtio_device *vdev, u32data); break; default: - DEBUGASSERT(0); +byte_write: + { + FAR char *s = src; + int i; + for (i = 0; i < length; i++) + { + metal_io_write8(&vmdev->cfg_io, write_offset + i, s[i]); + } + } } } @@ -606,16 +607,9 @@ static void virtio_mmio_read_config(FAR struct virtio_device *vdev, uint16_t u16data; uint8_t u8data; - if (vdev->id.version == VIRTIO_MMIO_VERSION_1 || length > 8) + if (vdev->id.version == VIRTIO_MMIO_VERSION_1) { - FAR char *d = dst; - int i; - for (i = 0; i < length; i++) - { - d[i] = metal_io_read8(&vmdev->cfg_io, read_offset + i); - } - - return; + goto byte_read; } switch (length) @@ -640,7 +634,15 @@ static void virtio_mmio_read_config(FAR struct virtio_device *vdev, memcpy(dst + sizeof(u32data), &u32data, sizeof(u32data)); break; default: - DEBUGASSERT(0); +byte_read: + { + FAR char *d = dst; + int i; + for (i = 0; i < length; i++) + { + d[i] = metal_io_read8(&vmdev->cfg_io, read_offset + i); + } + } } } @@ -721,6 +723,7 @@ static int virtio_mmio_interrupt(int irq, FAR void *context, FAR void *arg) uint32_t isr; isr = metal_io_read32(&vmdev->cfg_io, VIRTIO_MMIO_INTERRUPT_STATUS); + metal_io_write32(&vmdev->cfg_io, VIRTIO_MMIO_INTERRUPT_ACK, isr); if (isr & VIRTIO_MMIO_INTERRUPT_VRING) { for (i = 0; i < vmdev->vdev.vrings_num; i++) @@ -734,7 +737,6 @@ static int virtio_mmio_interrupt(int irq, FAR void *context, FAR void *arg) } } - metal_io_write32(&vmdev->cfg_io, VIRTIO_MMIO_INTERRUPT_ACK, isr); return OK; } @@ -779,8 +781,8 @@ static int virtio_mmio_init_device(FAR struct virtio_mmio_device_s *vmdev, vdev->id.device = metal_io_read32(&vmdev->cfg_io, VIRTIO_MMIO_DEVICE_ID); if (vdev->id.device == 0) { - vrterr("Device Id 0\n"); - return -EINVAL; + vrtinfo("Device Id 0\n"); + return -ENODEV; } vdev->id.vendor = metal_io_read32(&vmdev->cfg_io, VIRTIO_MMIO_VENDOR_ID); @@ -817,23 +819,11 @@ static int virtio_mmio_init_device(FAR struct virtio_mmio_device_s *vmdev, int virtio_register_mmio_device(FAR void *regs, int irq) { - struct metal_init_params params = METAL_INIT_DEFAULTS; FAR struct virtio_mmio_device_s *vmdev; - static bool onceinit; int ret; DEBUGASSERT(regs != NULL); - if (onceinit == false) - { - onceinit = true; - ret = metal_init(¶ms); - if (ret < 0) - { - return ret; - } - } - vmdev = kmm_zalloc(sizeof(*vmdev)); if (vmdev == NULL) { @@ -842,7 +832,12 @@ int virtio_register_mmio_device(FAR void *regs, int irq) } ret = virtio_mmio_init_device(vmdev, regs, irq); - if (ret < 0) + if (ret == -ENODEV) + { + vrtinfo("No virtio mmio device in regs=%p\n", regs); + goto err; + } + else if (ret < 0) { vrterr("virtio_mmio_device_init failed, ret=%d\n", ret); goto err; diff --git a/drivers/virtio/virtio.c b/drivers/virtio/virtio.c index e01a776880897..133c8950d8616 100644 --- a/drivers/virtio/virtio.c +++ b/drivers/virtio/virtio.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -119,8 +120,15 @@ void virtio_free_buf(FAR struct virtio_device *vdev, FAR void *buf) void virtio_register_drivers(void) { + struct metal_init_params params = METAL_INIT_DEFAULTS; int ret = OK; + ret = metal_init(¶ms); + if (ret < 0) + { + vrterr("metal_init failed, ret=%d\n", ret); + } + #ifdef CONFIG_DRIVERS_VIRTIO_BLK ret = virtio_register_blk_driver(); if (ret < 0) diff --git a/drivers/wireless/bluetooth/bt_rpmsghci_server.c b/drivers/wireless/bluetooth/bt_rpmsghci_server.c index fbd97d57680ea..be3e54b47b2bc 100644 --- a/drivers/wireless/bluetooth/bt_rpmsghci_server.c +++ b/drivers/wireless/bluetooth/bt_rpmsghci_server.c @@ -28,6 +28,7 @@ #include #include +#include #include #include diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.c b/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.c index 3c58fedf539ea..ab7b789f69e1b 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.c +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.c @@ -632,7 +632,7 @@ void bcmf_wl_auth_event_handler(FAR struct bcmf_dev_s *priv, if (type == WLC_E_PSK_SUP) { - carrier = (reason == WLC_E_SUP_OTHER) ? 1 : 0; + carrier = ((reason == WLC_E_SUP_OTHER) || (reason == 0)) ? 1 : 0; if (priv->auth_pending) { priv->auth_status = reason; @@ -1143,7 +1143,6 @@ int bcmf_wl_get_interface(FAR struct bcmf_dev_s *priv, FAR struct iwreq *iwr) FAR struct bcmf_dev_s *bcmf_allocate_device(void) { - int ret; FAR struct bcmf_dev_s *priv; /* Allocate a bcmf device structure */ @@ -1160,25 +1159,20 @@ FAR struct bcmf_dev_s *bcmf_allocate_device(void) /* Init control frames mutex and timeout signal */ - if ((ret = nxsem_init(&priv->control_mutex, 0, 1)) != OK) - { - goto exit_free_priv; - } + nxsem_init(&priv->control_mutex, 0, 1); + nxsem_init(&priv->control_timeout, 0, 0); - if ((ret = nxsem_init(&priv->control_timeout, 0, 0)) != OK) - { - goto exit_free_priv; - } + /* Init ioctl mutex */ + +#ifdef CONFIG_NETDEV_IOCTL + nxmutex_init(&priv->ioctl_mutex); +#endif /* Init scan timeout timer */ priv->scan_status = BCMF_SCAN_DISABLED; return priv; - -exit_free_priv: - kmm_free(priv); - return NULL; } /**************************************************************************** diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.h b/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.h index eec2a25adaca0..f405ce5c6813f 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.h +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_driver.h @@ -82,6 +82,9 @@ struct bcmf_dev_s uint16_t control_rxdata_len; /* Received control frame out buffer length */ FAR uint8_t *control_rxdata; /* Received control frame out buffer */ uint32_t control_status; /* Last received frame status */ +#ifdef CONFIG_NETDEV_IOCTL + mutex_t ioctl_mutex; /* Avoid handle multiple ioctl requests */ +#endif /* AP Scan state machine. * During scan, control_mutex is locked to prevent control requests diff --git a/drivers/wireless/ieee80211/bcm43xxx/bcmf_netdev.c b/drivers/wireless/ieee80211/bcm43xxx/bcmf_netdev.c index 0c5dbe88b759f..73211164fb837 100644 --- a/drivers/wireless/ieee80211/bcm43xxx/bcmf_netdev.c +++ b/drivers/wireless/ieee80211/bcm43xxx/bcmf_netdev.c @@ -936,6 +936,11 @@ static int bcmf_ioctl(FAR struct net_driver_s *dev, int cmd, return -EPERM; } + if ((ret = nxmutex_lock(&priv->ioctl_mutex)) < 0) + { + return ret; + } + #ifdef CONFIG_IEEE80211_BROADCOM_LOWPOWER bcmf_lowpower_poll(priv); #endif @@ -1072,6 +1077,8 @@ static int bcmf_ioctl(FAR struct net_driver_s *dev, int cmd, break; } + nxmutex_unlock(&priv->ioctl_mutex); + return ret; } #endif diff --git a/drivers/wireless/ieee802154/mrf24j40/Kconfig b/drivers/wireless/ieee802154/mrf24j40/Kconfig index 851b804a1462c..bff1af002dbc8 100644 --- a/drivers/wireless/ieee802154/mrf24j40/Kconfig +++ b/drivers/wireless/ieee802154/mrf24j40/Kconfig @@ -5,4 +5,10 @@ if IEEE802154_MRF24J40 +config IEEE802154_MRF24J40_FREQUENCY + int "SPI Frequency for MRF24J40" + default 8000000 + ---help--- + SPI SLCK frequency in Hz + endif # IEEE802154_MRF24J40 diff --git a/drivers/wireless/ieee802154/mrf24j40/mrf24j40.h b/drivers/wireless/ieee802154/mrf24j40/mrf24j40.h index cfcc731eb4ad0..5a3db74f22842 100644 --- a/drivers/wireless/ieee802154/mrf24j40/mrf24j40.h +++ b/drivers/wireless/ieee802154/mrf24j40/mrf24j40.h @@ -76,6 +76,8 @@ #define MRF24J40_SYMBOL_DURATION_PS 16000000 +#define MRF24J40_SPIMODE SPIDEV_MODE0 + /* Clock configuration macros */ #define MRF24J40_BEACONINTERVAL_NSEC(beaconorder) \ @@ -90,10 +92,6 @@ # error High priority work queue required in this driver #endif -#ifndef CONFIG_IEEE802154_MRF24J40_SPIMODE -# define CONFIG_IEEE802154_MRF24J40_SPIMODE SPIDEV_MODE0 -#endif - #ifndef CONFIG_IEEE802154_MRF24J40_FREQUENCY # define CONFIG_IEEE802154_MRF24J40_FREQUENCY 8000000 #endif @@ -174,7 +172,7 @@ static inline void mrf24j40_spi_lock(FAR struct spi_dev_s *spi) { SPI_LOCK(spi, 1); SPI_SETBITS(spi, 8); - SPI_SETMODE(spi, CONFIG_IEEE802154_MRF24J40_SPIMODE); + SPI_SETMODE(spi, MRF24J40_SPIMODE); SPI_SETFREQUENCY(spi, CONFIG_IEEE802154_MRF24J40_FREQUENCY); } diff --git a/drivers/wireless/ieee802154/mrf24j40/mrf24j40_radif.c b/drivers/wireless/ieee802154/mrf24j40/mrf24j40_radif.c index 6690eb2a24a20..ee31c0288656c 100644 --- a/drivers/wireless/ieee802154/mrf24j40/mrf24j40_radif.c +++ b/drivers/wireless/ieee802154/mrf24j40/mrf24j40_radif.c @@ -554,6 +554,12 @@ int mrf24j40_getattr(FAR struct ieee802154_radio_s *radio, } break; + case IEEE802154_ATTR_PHY_REGDUMP: + { + ret = mrf24j40_regdump(dev); + } + break; + default: ret = IEEE802154_STATUS_UNSUPPORTED_ATTRIBUTE; } diff --git a/fs/Kconfig b/fs/Kconfig index e66f2abcd5f87..6115ed19c724f 100644 --- a/fs/Kconfig +++ b/fs/Kconfig @@ -64,6 +64,10 @@ config FS_NEPOLL_DESCRIPTORS ---help--- The maximum number of default epoll descriptors for epoll_create1(2) +config FS_LOCK_BUCKET_SIZE + int "Maximum number of hash bucket using file locks" + default 0 + config DISABLE_PSEUDOFS_OPERATIONS bool "Disable pseudo-filesystem operations" default DEFAULT_SMALL diff --git a/fs/driver/fs_unregisterdriver.c b/fs/driver/fs_unregisterdriver.c index fd6b6ee297b8a..0b5d9b6c76ddd 100644 --- a/fs/driver/fs_unregisterdriver.c +++ b/fs/driver/fs_unregisterdriver.c @@ -44,6 +44,16 @@ int unregister_driver(FAR const char *path) { int ret; + /* Call unlink to release driver resource and inode. */ + + ret = nx_unlink(path); + if (ret >= 0) + { + return ret; + } + + /* If unlink failed, only remove inode. */ + ret = inode_lock(); if (ret >= 0) { diff --git a/fs/fat/fs_fat32.c b/fs/fat/fs_fat32.c index 0f4bbe8940f5d..700e09230c901 100644 --- a/fs/fat/fs_fat32.c +++ b/fs/fat/fs_fat32.c @@ -1316,7 +1316,7 @@ static int fat_ioctl(FAR struct file *filep, int cmd, unsigned long arg) /* ioctl calls are just passed through to the contained block driver */ nxmutex_unlock(&fs->fs_lock); - return -ENOSYS; + return -ENOTTY; } /**************************************************************************** diff --git a/fs/fat/fs_fat32.h b/fs/fat/fs_fat32.h index afff4598a0596..e1d7ce43a93c5 100644 --- a/fs/fat/fs_fat32.h +++ b/fs/fat/fs_fat32.h @@ -261,7 +261,7 @@ #define DIRSEC_NDXMASK(f) (((f)->fs_hwsectorsize - 1) >> 5) #define DIRSEC_NDIRS(f) (((f)->fs_hwsectorsize) >> 5) -#define DIRSEC_BYTENDX(f,i) (((i) & DIRSEC_NDXMASK(fs)) << 5) +#define DIRSEC_BYTENDX(f,i) (((i) & DIRSEC_NDXMASK(f)) << 5) #define SEC_NDXMASK(f) ((f)->fs_hwsectorsize - 1) #define SEC_NSECTORS(f,n) ((n) / (f)->fs_hwsectorsize) diff --git a/fs/fat/fs_fat32dirent.c b/fs/fat/fs_fat32dirent.c index b36f547dfa736..c8a4ed1af35e0 100644 --- a/fs/fat/fs_fat32dirent.c +++ b/fs/fat/fs_fat32dirent.c @@ -286,7 +286,7 @@ static uint8_t fat_lfnchecksum(FAR const uint8_t *sfname) * 0x2a-0x2c = '*', '+', ',' * 0x2e-0x2f = '.', '/' * 0x3a-0x3f = ':', ';', '<', '=', '>', '?' - * 0x5b-0x5d = '[', '\\', ;]' + * 0x5b-0x5d = '[', '\\', ']' * 0x7c = '|' * * '.' May only occur once within string and only within the first 9 @@ -296,7 +296,7 @@ static uint8_t fat_lfnchecksum(FAR const uint8_t *sfname) * Lower case characters are not allowed in directory names (without some * poorly documented operations on the NTRes directory byte). Lower case * codes may represent different characters in other character sets ("DOS - * code pages". The logic below does not, at present, support any other + * code pages"). The logic below does not, at present, support any other * character sets. * * Returned Value: @@ -2556,7 +2556,7 @@ int fat_finddirentry(FAR struct fat_mountpt_s *fs, } /* fd_index is the index into the current directory table. It is set to the - * the first, entry in the root directory. + * the first entry in the root directory. */ dirinfo->dir.fd_index = 0; @@ -2641,7 +2641,7 @@ int fat_finddirentry(FAR struct fat_mountpt_s *fs, if (terminator == '\0') { - /* Return success meaning that the description the matching + /* Return success meaning that the description matching the * directory entry is in dirinfo. */ diff --git a/fs/fat/fs_fat32util.c b/fs/fat/fs_fat32util.c index a1b8c2d7fbeda..5e121302de566 100644 --- a/fs/fat/fs_fat32util.c +++ b/fs/fat/fs_fat32util.c @@ -888,6 +888,8 @@ off_t fat_getcluster(struct fat_mountpt_s *fs, uint32_t clusterno) case FSTYPE_FAT16 : { + /* 16 bits per entry, ie. 2 bytes per entry */ + unsigned int fatoffset = 2 * clusterno; off_t fatsector = fs->fs_fatbase + SEC_NSECTORS(fs, fatoffset); @@ -905,6 +907,8 @@ off_t fat_getcluster(struct fat_mountpt_s *fs, uint32_t clusterno) case FSTYPE_FAT32 : { + /* 32 bits per entry, ie. 4 bytes per entry */ + unsigned int fatoffset = 4 * clusterno; off_t fatsector = fs->fs_fatbase + SEC_NSECTORS(fs, fatoffset); @@ -1332,7 +1336,7 @@ int fat_nextdirentry(struct fat_mountpt_s *fs, struct fs_fatdir_s *dir) ndx = dir->fd_index + 1; - /* Check if all of the directory entries in this sectory have + /* Check if all of the directory entries in this sector have * been examined. */ @@ -1368,7 +1372,7 @@ int fat_nextdirentry(struct fat_mountpt_s *fs, struct fs_fatdir_s *dir) * entire cluster comprising the directory. * * The current sector within the cluster is the entry number - * divided byte the number of entries per sector + * divided by the number of entries per sector */ int sector = ndx / DIRSEC_NDIRS(fs); diff --git a/fs/fs_initialize.c b/fs/fs_initialize.c index df7678d988d75..c7285ee1ab473 100644 --- a/fs/fs_initialize.c +++ b/fs/fs_initialize.c @@ -29,6 +29,7 @@ #include "rpmsgfs/rpmsgfs.h" #include "inode/inode.h" #include "aio/aio.h" +#include "vfs/lock.h" /**************************************************************************** * Private Functions @@ -83,6 +84,8 @@ void fs_initialize(void) inode_initialize(); + file_initlk(); + #ifdef CONFIG_FS_AIO /* Initialize for asynchronous I/O */ diff --git a/fs/inode/fs_files.c b/fs/inode/fs_files.c index c5f047ba947f5..40cb5f9911366 100644 --- a/fs/inode/fs_files.c +++ b/fs/inode/fs_files.c @@ -154,7 +154,7 @@ static int files_extend(FAR struct filelist *list, size_t row) spin_unlock_irqrestore(&list->fl_lock, flags); - if (tmp != NULL) + if (tmp != NULL && tmp != &list->fl_prefile) { kmm_free(tmp); } @@ -210,7 +210,12 @@ static int nx_dup3_from_tcb(FAR struct tcb_s *tcb, int fd1, int fd2, { FAR struct filelist *list; FAR struct file *filep; - FAR struct file file; +#ifdef CONFIG_FDCHECK + uint8_t f_tag_fdcheck; +#endif +#ifdef CONFIG_FDSAN + uint64_t f_tag_fdsan; +#endif int count; int ret; @@ -224,14 +229,12 @@ static int nx_dup3_from_tcb(FAR struct tcb_s *tcb, int fd1, int fd2, fd2 = fdcheck_restore(fd2); #endif - list = nxsched_get_files_from_tcb(tcb); + /* Get the file descriptor list. It should not be NULL in this context. */ + list = nxsched_get_files_from_tcb(tcb); count = files_countlist(list); - /* Get the file descriptor list. It should not be NULL in this context. */ - - if (fd1 < 0 || fd1 >= count || - fd2 < 0) + if (fd1 < 0 || fd1 >= count || fd2 < 0) { return -EBADF; } @@ -246,23 +249,39 @@ static int nx_dup3_from_tcb(FAR struct tcb_s *tcb, int fd1, int fd2, } filep = files_fget(list, fd2); - memcpy(&file, filep, sizeof(struct file)); - memset(filep, 0, sizeof(struct file)); + if (filep == NULL) + { + return -EBADF; + } + +#ifdef CONFIG_FDSAN + f_tag_fdsan = filep->f_tag_fdsan; +#endif + +#ifdef CONFIG_FDCHECK + f_tag_fdcheck = filep->f_tag_fdcheck; +#endif /* Perform the dup3 operation */ ret = file_dup3(files_fget(list, fd1), filep, flags); + if (ret < 0) + { + return ret; + } #ifdef CONFIG_FDSAN - filep->f_tag = file.f_tag; + filep->f_tag_fdsan = f_tag_fdsan; #endif - file_close(&file); +#ifdef CONFIG_FDCHECK + filep->f_tag_fdcheck = f_tag_fdcheck; +#endif #ifdef CONFIG_FDCHECK - return ret < 0 ? ret : fdcheck_protect(fd2); + return fdcheck_protect(fd2); #else - return ret < 0 ? ret : fd2; + return fd2; #endif } @@ -279,7 +298,13 @@ static int nx_dup3_from_tcb(FAR struct tcb_s *tcb, int fd1, int fd2, void files_initlist(FAR struct filelist *list) { - DEBUGASSERT(list); + /* The first row will reuse pre-allocated files, which will avoid + * unnecessary allocator accesses during file initialization. + */ + + list->fl_rows = 1; + list->fl_files = &list->fl_prefile; + list->fl_prefile = list->fl_prefiles; } /**************************************************************************** @@ -309,10 +334,16 @@ void files_releaselist(FAR struct filelist *list) file_close(&list->fl_files[i][j]); } - kmm_free(list->fl_files[i]); + if (i != 0) + { + kmm_free(list->fl_files[i]); + } } - kmm_free(list->fl_files); + if (list->fl_files != &list->fl_prefile) + { + kmm_free(list->fl_files); + } } /**************************************************************************** @@ -375,64 +406,54 @@ int file_allocate_from_tcb(FAR struct tcb_s *tcb, FAR struct inode *inode, int oflags, off_t pos, FAR void *priv, int minfd, bool addref) { + int i = minfd / CONFIG_NFILE_DESCRIPTORS_PER_BLOCK; + int j = minfd % CONFIG_NFILE_DESCRIPTORS_PER_BLOCK; FAR struct filelist *list; FAR struct file *filep; + irqstate_t flags; int ret; - int i; - int j; /* Get the file descriptor list. It should not be NULL in this context. */ list = nxsched_get_files_from_tcb(tcb); - /* Calculate minfd whether is in list->fl_files. - * if not, allocate a new filechunk. - */ + /* Find free file */ - i = minfd / CONFIG_NFILE_DESCRIPTORS_PER_BLOCK; - if (i >= list->fl_rows) + flags = spin_lock_irqsave(&list->fl_lock); + + for (; ; i++, j = 0) { - ret = files_extend(list, i + 1); - if (ret < 0) + if (i >= list->fl_rows) { - return ret; - } - } + spin_unlock_irqrestore(&list->fl_lock, flags); - /* Find free file */ + ret = files_extend(list, i + 1); + if (ret < 0) + { + return ret; + } + + flags = spin_lock_irqsave(&list->fl_lock); + } - j = minfd % CONFIG_NFILE_DESCRIPTORS_PER_BLOCK; - do - { do { - filep = files_fget_by_index(list, i, j); + filep = &list->fl_files[i][j]; if (filep->f_inode == NULL) { + filep->f_oflags = oflags; + filep->f_pos = pos; + filep->f_inode = inode; + filep->f_priv = priv; + goto found; } } while (++j < CONFIG_NFILE_DESCRIPTORS_PER_BLOCK); - - j = 0; } - while (++i < list->fl_rows); - /* The space of file array isn't enough, allocate a new filechunk */ - - ret = files_extend(list, i + 1); - if (ret < 0) - { - return ret; - } - - filep = files_fget_by_index(list, i, 0); found: - - filep->f_oflags = oflags; - filep->f_pos = pos; - filep->f_inode = inode; - filep->f_priv = priv; + spin_unlock_irqrestore(&list->fl_lock, flags); if (addref) { @@ -732,7 +753,6 @@ int dup3(int fd1, int fd2, int flags) int nx_close_from_tcb(FAR struct tcb_s *tcb, int fd) { FAR struct file *filep; - FAR struct file file; FAR struct filelist *list; #ifdef CONFIG_FDCHECK @@ -757,10 +777,7 @@ int nx_close_from_tcb(FAR struct tcb_s *tcb, int fd) return -EBADF; } - memcpy(&file, filep, sizeof(struct file)); - memset(filep, 0, sizeof(struct file)); - - return file_close(&file); + return file_close(filep); } /**************************************************************************** diff --git a/fs/inode/fs_foreachinode.c b/fs/inode/fs_foreachinode.c index 0db28289b5fa5..4fe1ef4e7276b 100644 --- a/fs/inode/fs_foreachinode.c +++ b/fs/inode/fs_foreachinode.c @@ -187,7 +187,7 @@ int foreach_inode(foreach_inode_t handler, FAR void *arg) ret = inode_lock(); if (ret >= 0) { - ret = foreach_inodelevel(g_root_inode->i_child, info); + ret = foreach_inodelevel(inode_root()->i_child, info); inode_unlock(); } @@ -211,7 +211,7 @@ int foreach_inode(foreach_inode_t handler, FAR void *arg) ret = inode_lock(); if (ret >= 0) { - ret = foreach_inodelevel(g_root_inode->i_child, &info); + ret = foreach_inodelevel(inode_root()->i_child, &info); inode_unlock(); } diff --git a/fs/inode/fs_inodereserve.c b/fs/inode/fs_inodereserve.c index 6f6ce6a2e063a..babc5e8de7475 100644 --- a/fs/inode/fs_inodereserve.c +++ b/fs/inode/fs_inodereserve.c @@ -141,7 +141,7 @@ static void inode_insert(FAR struct inode *node, void inode_root_reserve(void) { - g_root_inode = inode_alloc("", 0777); + inode_root() = inode_alloc("", 0777); } /**************************************************************************** diff --git a/fs/inode/fs_inodesearch.c b/fs/inode/fs_inodesearch.c index 79f2125ff53f4..f3f718328a4a8 100644 --- a/fs/inode/fs_inodesearch.c +++ b/fs/inode/fs_inodesearch.c @@ -69,11 +69,6 @@ static int _inode_compare(FAR const char *fname, FAR struct inode *node) { FAR char *nname = node->i_name; - if (!nname) - { - return 1; - } - if (!fname) { return -1; @@ -219,7 +214,7 @@ static int _inode_linktarget(FAR struct inode *node, static int _inode_search(FAR struct inode_search_s *desc) { FAR const char *name; - FAR struct inode *node = g_root_inode; + FAR struct inode *node = inode_root(); FAR struct inode *left = NULL; FAR struct inode *above = NULL; FAR const char *relpath = NULL; diff --git a/fs/inode/inode.h b/fs/inode/inode.h index 35186767659f5..c11d8f6d0e8d4 100644 --- a/fs/inode/inode.h +++ b/fs/inode/inode.h @@ -65,6 +65,8 @@ } \ while (0) +#define inode_root() g_root_inode + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/fs/littlefs/CMakeLists.txt b/fs/littlefs/CMakeLists.txt index b137ee5cc2356..c4920b0ae5dd8 100644 --- a/fs/littlefs/CMakeLists.txt +++ b/fs/littlefs/CMakeLists.txt @@ -29,8 +29,10 @@ if(CONFIG_FS_LITTLEFS) ${CMAKE_CURRENT_LIST_DIR}/littlefs BINARY_DIR ${CMAKE_BINARY_DIR}/fs/littlefs/littlefs - PATCH_COMMAND patch -p2 -d ${CMAKE_CURRENT_LIST_DIR} < - ${CMAKE_CURRENT_LIST_DIR}/lfs_util.patch) + PATCH_COMMAND + patch -p2 -d ${CMAKE_CURRENT_LIST_DIR} < + ${CMAKE_CURRENT_LIST_DIR}/lfs_util.patch COMMAND patch -p2 -d + ${CMAKE_CURRENT_LIST_DIR} < ${CMAKE_CURRENT_LIST_DIR}/lfs_getpath.patch) FetchContent_MakeAvailable(littlefs) endif() diff --git a/fs/littlefs/Make.defs b/fs/littlefs/Make.defs index 030b70941c7aa..7cd5736fa2034 100644 --- a/fs/littlefs/Make.defs +++ b/fs/littlefs/Make.defs @@ -51,6 +51,7 @@ $(LITTLEFS_TARBALL): $(Q) tar zxf littlefs/$(LITTLEFS_TARBALL) -C littlefs $(Q) mv littlefs/littlefs-$(LITTLEFS_VERSION) littlefs/littlefs $(Q) git apply littlefs/lfs_util.patch + $(Q) git apply littlefs/lfs_getpath.patch $(Q) touch littlefs/.littlefsunpack # Download and unpack tarball if no git repo found diff --git a/fs/littlefs/lfs_getpath.patch b/fs/littlefs/lfs_getpath.patch new file mode 100644 index 0000000000000..57be37a73a225 --- /dev/null +++ b/fs/littlefs/lfs_getpath.patch @@ -0,0 +1,147 @@ +From 696dfa6ce29cb44d22e48bf66032e217383d8a2f Mon Sep 17 00:00:00 2001 +From: zhouliang3 +Date: Tue, 24 Aug 2021 12:48:22 +0800 +Subject: [PATCH] fs/littlefs: Add the function of obtaining absolute path + +Signed-off-by: zhouliang3 +--- + lfs.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + lfs.h | 8 ++++++ + 2 files changed, 87 insertions(+) + +--- ./littlefs/littlefs/lfs.c ++++ ./littlefs/littlefs/lfs.c +@@ -542,6 +542,8 @@ static uint16_t lfs_fs_disk_version_minor(lfs_t *lfs) { + + + /// Internal operations predeclared here /// ++static lfs_ssize_t lfs_dir_rawpath(lfs_t *lfs, ++ lfs_mdir_t *dir, uint16_t id, char *path, lfs_size_t size); + #ifndef LFS_READONLY + static int lfs_dir_commit(lfs_t *lfs, lfs_mdir_t *dir, + const struct lfs_mattr *attrs, int attrcount); +@@ -3790,6 +3792,53 @@ static lfs_soff_t lfs_file_rawsize(lfs_t *lfs, lfs_file_t *file) { + return file->ctz.size; + } + ++static lfs_ssize_t lfs_dir_rawpath(lfs_t *lfs, ++ lfs_mdir_t *dir, uint16_t id, char *path, lfs_size_t size) { ++ struct lfs_info info; ++ char *next = path; ++ lfs_mdir_t parent; ++ lfs_ssize_t len; ++ lfs_stag_t tag; ++ int err; ++ ++ if (lfs_pair_cmp(lfs->root, dir->pair) != 0) { ++ tag = lfs_fs_parent(lfs, dir->pair, &parent); ++ if (tag < 0) { ++ return tag; ++ } ++ ++ len = lfs_dir_rawpath(lfs, &parent, lfs_tag_id(tag), next, size); ++ if (len < 0) { ++ return len; ++ } ++ ++ next += len; ++ size -= len; ++ } ++ ++ err = lfs_dir_getinfo(lfs, dir, id, &info); ++ if (err < 0) { ++ return err; ++ } ++ ++ len = strlen(info.name); ++ if (len >= size) { ++ return LFS_ERR_INVAL; ++ } ++ ++ memcpy(next, info.name, len + 1); ++ next += len; ++ ++ if (info.type == LFS_TYPE_DIR) { ++ *next++ = '/'; ++ if (++len >= size) { ++ return LFS_ERR_INVAL; ++ } ++ *next = '\0'; ++ } ++ ++ return next - path; ++} + + /// General fs operations /// + static int lfs_rawstat(lfs_t *lfs, const char *path, struct lfs_info *info) { +@@ -6042,6 +6091,22 @@ lfs_soff_t lfs_file_size(lfs_t *lfs, lfs_file_t *file) { + return res; + } + ++int lfs_file_path(lfs_t *lfs, lfs_file_t *file, char *path, lfs_size_t size) { ++ int err = LFS_LOCK(lfs->cfg); ++ if (err) { ++ return err; ++ } ++ ++ LFS_TRACE("lfs_file_path(%p, %p)", (void*)lfs, (void*)file); ++ LFS_ASSERT(lfs_mlist_isopen(lfs->mlist, (struct lfs_mlist*)file)); ++ ++ err = lfs_dir_rawpath(lfs, &file->m, file->id, path, size); ++ ++ LFS_TRACE("lfs_file_path -> %d", err); ++ LFS_UNLOCK(lfs->cfg); ++ return err < 0 ? err : 0; ++} ++ + #ifndef LFS_READONLY + int lfs_mkdir(lfs_t *lfs, const char *path) { + int err = LFS_LOCK(lfs->cfg); +@@ -6173,6 +6238,20 @@ lfs_ssize_t lfs_fs_size(lfs_t *lfs) { + return res; + } + ++int lfs_dir_path(lfs_t *lfs, lfs_dir_t *dir, char *path, lfs_size_t size) { ++ int err = LFS_LOCK(lfs->cfg); ++ if (err) { ++ return err; ++ } ++ ++ LFS_TRACE("lfs_dir_path(%p, %p)", (void*)lfs, (void*)dir); ++ err = lfs_dir_rawpath(lfs, &dir->m, dir->id, path, size); ++ ++ LFS_TRACE("lfs_dir_path -> %d", err); ++ LFS_UNLOCK(lfs->cfg); ++ return err < 0 ? err : 0; ++} ++ + int lfs_fs_traverse(lfs_t *lfs, int (*cb)(void *, lfs_block_t), void *data) { + int err = LFS_LOCK(lfs->cfg); + if (err) { +--- ./littlefs/littlefs/lfs.h ++++ ./littlefs/littlefs/lfs.h +@@ -629,6 +629,10 @@ int lfs_file_rewind(lfs_t *lfs, lfs_file_t *file); + // Returns the size of the file, or a negative error code on failure. + lfs_soff_t lfs_file_size(lfs_t *lfs, lfs_file_t *file); + ++// Get the absolute path of the open file. ++// ++// Returns a negative error code on failure. ++int lfs_file_path(lfs_t *lfs, lfs_file_t *file, char *path, lfs_size_t size); + + /// Directory operations /// + +@@ -679,6 +683,10 @@ lfs_soff_t lfs_dir_tell(lfs_t *lfs, lfs_dir_t *dir); + // Returns a negative error code on failure. + int lfs_dir_rewind(lfs_t *lfs, lfs_dir_t *dir); + ++// Get the absolute path of the directory ++// ++// Returns a negative error code on failure. ++int lfs_dir_path(lfs_t *lfs, lfs_dir_t *dir, char *path, lfs_size_t size); + + /// Filesystem-level filesystem operations + +-- +2.25.1 + diff --git a/fs/littlefs/lfs_vfs.c b/fs/littlefs/lfs_vfs.c index bc6c2cf7ad517..18aa9cb60f21c 100644 --- a/fs/littlefs/lfs_vfs.c +++ b/fs/littlefs/lfs_vfs.c @@ -29,6 +29,7 @@ #include #include +#include #include #include #include @@ -36,6 +37,7 @@ #include #include +#include "inode/inode.h" #include "littlefs/lfs.h" #include "littlefs/lfs_util.h" @@ -543,30 +545,68 @@ static off_t littlefs_seek(FAR struct file *filep, off_t offset, int whence) static int littlefs_ioctl(FAR struct file *filep, int cmd, unsigned long arg) { FAR struct littlefs_mountpt_s *fs; + FAR struct littlefs_file_s *priv; FAR struct inode *inode; FAR struct inode *drv; + int ret; /* Recover our private data from the struct file instance */ + priv = filep->f_priv; inode = filep->f_inode; fs = inode->i_private; drv = fs->drv; - if (INODE_IS_MTD(drv)) + ret = nxmutex_lock(&fs->lock); + if (ret < 0) { - return MTD_IOCTL(drv->u.i_mtd, cmd, arg); + return ret; } - else + + switch (cmd) { - if (drv->u.i_bops->ioctl != NULL) + case FIOC_FILEPATH: { - return drv->u.i_bops->ioctl(drv, cmd, arg); + FAR char *path = (FAR char *)(uintptr_t)arg; + ret = inode_getpath(inode, path, PATH_MAX); + if (ret >= 0) + { + size_t len = strlen(path); + if (path[len - 1] != '/') + { + path[len++] = '/'; + } + + ret = littlefs_convert_result(lfs_file_path(&fs->lfs, + &priv->file, + path + len, + PATH_MAX - len)); + } } - else + break; + + default: { - return -ENOTTY; + if (INODE_IS_MTD(drv)) + { + ret = MTD_IOCTL(drv->u.i_mtd, cmd, arg); + } + else + { + if (drv->u.i_bops->ioctl != NULL) + { + ret = drv->u.i_bops->ioctl(drv, cmd, arg); + } + else + { + ret = -ENOTTY; + } + } } } + + nxmutex_unlock(&fs->lock); + return ret; } /**************************************************************************** diff --git a/fs/mmap/fs_mmap.c b/fs/mmap/fs_mmap.c index 11ffb55b5c9ce..8b310e74b4956 100644 --- a/fs/mmap/fs_mmap.c +++ b/fs/mmap/fs_mmap.c @@ -73,7 +73,6 @@ static int file_mmap_(FAR struct file *filep, FAR void *start, * things. */ -#ifdef CONFIG_DEBUG_FEATURES /* A flags with MAP_PRIVATE and MAP_SHARED is invalid. */ if ((flags & MAP_PRIVATE) && (flags & MAP_SHARED)) @@ -99,7 +98,6 @@ static int file_mmap_(FAR struct file *filep, FAR void *start, ferr("ERROR: Invalid length, length=%zu\n", length); return -EINVAL; } -#endif /* CONFIG_DEBUG_FEATURES */ /* Check if we are just be asked to allocate memory, i.e., MAP_ANONYMOUS * set meaning that the memory is not backed up from a file. The file diff --git a/fs/mount/fs_mount.c b/fs/mount/fs_mount.c index ac5756854bcbc..2bbef28958a45 100644 --- a/fs/mount/fs_mount.c +++ b/fs/mount/fs_mount.c @@ -68,7 +68,7 @@ defined(CONFIG_FS_PROCFS) || defined(CONFIG_NFS) || \ defined(CONFIG_FS_TMPFS) || defined(CONFIG_FS_USERFS) || \ defined(CONFIG_FS_CROMFS) || defined(CONFIG_FS_UNIONFS) || \ - defined(CONFIG_FS_HOSTFS) + defined(CONFIG_FS_HOSTFS) || defined(CONFIG_FS_RPMSGFS) # define NODFS_SUPPORT #endif @@ -279,12 +279,12 @@ int nx_mount(FAR const char *source, FAR const char *target, { #if defined(BDFS_SUPPORT) || defined(MDFS_SUPPORT) || defined(NODFS_SUPPORT) FAR struct inode *drvr_inode = NULL; - FAR struct inode *mountpt_inode; + FAR struct inode *mountpt_inode = NULL; FAR const struct mountpt_operations *mops = NULL; #ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS struct inode_search_s desc; #endif - void *fshandle; + void *fshandle = NULL; int ret; /* Verify required pointer arguments */ @@ -293,7 +293,7 @@ int nx_mount(FAR const char *source, FAR const char *target, /* Find the specified filesystem. Try the block driver filesystems first */ - if (source != NULL && + if (source != NULL && source[0] != '\0' && find_blockdriver(source, mountflags, &drvr_inode) >= 0) { /* Find the block based file system */ @@ -310,7 +310,7 @@ int nx_mount(FAR const char *source, FAR const char *target, goto errout_with_inode; } } - else if (source != NULL && + else if (source != NULL && source[0] != '\0' && (ret = find_mtddriver(source, &drvr_inode)) >= 0) { /* Find the MTD based file system */ @@ -331,6 +331,7 @@ int nx_mount(FAR const char *source, FAR const char *target, #ifdef NODFS_SUPPORT if ((mops = mount_findfs(g_nonbdfsmap, filesystemtype)) != NULL) { + finfo("found %s\n", filesystemtype); } else #endif /* NODFS_SUPPORT */ diff --git a/fs/nxffs/nxffs_dump.c b/fs/nxffs/nxffs_dump.c index 783751029cb82..f4bcc88763864 100644 --- a/fs/nxffs/nxffs_dump.c +++ b/fs/nxffs/nxffs_dump.c @@ -61,7 +61,7 @@ struct nxffs_blkinfo_s #if defined(CONFIG_DEBUG_FEATURES) && defined(CONFIG_DEBUG_FS) static const char g_hdrformat[] = " BLOCK:OFFS TYPE STATE LENGTH\n"; -static const char g_format[] = " %5d:%-5d %s %s %5d\n"; +static const char g_format[] = " %5"PRIi32":%-5d %s %s %5"PRIu32"\n"; #endif /**************************************************************************** @@ -263,7 +263,8 @@ static inline ssize_t nxffs_analyzedata(FAR struct nxffs_blkinfo_s *blkinfo, if (crc != ecrc) { syslog(LOG_NOTICE, g_format, - blkinfo->block, offset, "DATA ", "CRC BAD", datlen); + blkinfo->block, offset, "DATA ", "CRC BAD", + (long unsigned int)datlen); return ERROR; } @@ -272,7 +273,8 @@ static inline ssize_t nxffs_analyzedata(FAR struct nxffs_blkinfo_s *blkinfo, if (blkinfo->verbose) { syslog(LOG_NOTICE, g_format, - blkinfo->block, offset, "DATA ", "OK ", datlen); + blkinfo->block, offset, "DATA ", "OK ", + (long unsigned int)datlen); } return SIZEOF_NXFFS_DATA_HDR + datlen; @@ -489,7 +491,7 @@ int nxffs_dump(FAR struct mtd_dev_s *mtd, bool verbose) } } - syslog(LOG_NOTICE, "%d blocks analyzed\n", blkinfo.nblocks); + syslog(LOG_NOTICE, "%" PRIi32 " blocks analyzed\n", blkinfo.nblocks); kmm_free(blkinfo.buffer); return OK; diff --git a/fs/partition/fs_mbr.c b/fs/partition/fs_mbr.c index 672c9d76da87e..d8eccf45f9125 100644 --- a/fs/partition/fs_mbr.c +++ b/fs/partition/fs_mbr.c @@ -36,7 +36,7 @@ ****************************************************************************/ #define MBR_SIZE 512 -#define MBR_LBA_TO_BLOCK(lba, blk) ((le32toh(lba) * 512 + (blk) - 1) / (blk)) +#define MBR_LBA_TO_BLOCK(lba, blk) (((blkcnt_t)le32toh(lba) * 512 + (blk) - 1) / (blk)) /**************************************************************************** * Private Types diff --git a/fs/procfs/fs_procfscpuload.c b/fs/procfs/fs_procfscpuload.c index 6c55e3e0bd5a7..0742d340d8a5d 100644 --- a/fs/procfs/fs_procfscpuload.c +++ b/fs/procfs/fs_procfscpuload.c @@ -203,8 +203,8 @@ static ssize_t cpuload_read(FAR struct file *filep, FAR char *buffer, if (filep->f_pos == 0) { - uint32_t total = 0; - uint32_t active = 0; + clock_t total = 0; + clock_t active = 0; uint32_t intpart; uint32_t fracpart; diff --git a/fs/procfs/fs_procfsmeminfo.c b/fs/procfs/fs_procfsmeminfo.c index 852e4a60b2068..0e145d2545fc9 100644 --- a/fs/procfs/fs_procfsmeminfo.c +++ b/fs/procfs/fs_procfsmeminfo.c @@ -293,7 +293,7 @@ static ssize_t meminfo_read(FAR struct file *filep, FAR char *buffer, /* The first line is the headers */ linesize = procfs_snprintf(procfile->line, MEMINFO_LINELEN, - "%13s%11s%11s%11s%11s%11s%7s%7s\n", "", + "%11s%11s%11s%11s%11s%11s%7s%7s\n", "", "total", "used", "free", "maxused", "maxfree", "nused", "nfree"); @@ -318,7 +318,7 @@ static ssize_t meminfo_read(FAR struct file *filep, FAR char *buffer, info = mm_mallinfo(entry->heap); linesize = procfs_snprintf(procfile->line, MEMINFO_LINELEN, - "%12s:%11lu%11lu%11lu%11lu%11lu" + "%10s:%11lu%11lu%11lu%11lu%11lu" "%7lu%7lu\n", entry->name, (unsigned long)info.arena, (unsigned long)info.uordblks, @@ -336,7 +336,7 @@ static ssize_t meminfo_read(FAR struct file *filep, FAR char *buffer, #ifdef CONFIG_MM_PGALLOC if (buflen > 0) { - struct pginfo_s pginfo; + struct pginfo_s pg_info; unsigned long total; unsigned long available; unsigned long allocated; @@ -347,15 +347,15 @@ static ssize_t meminfo_read(FAR struct file *filep, FAR char *buffer, /* Show page allocator information */ - mm_pginfo(&pginfo); + mm_pginfo(&pg_info); - total = (unsigned long)pginfo.ntotal << MM_PGSHIFT; - available = (unsigned long)pginfo.nfree << MM_PGSHIFT; + total = (unsigned long)pg_info.ntotal << MM_PGSHIFT; + available = (unsigned long)pg_info.nfree << MM_PGSHIFT; allocated = total - available; - max = (unsigned long)pginfo.mxfree << MM_PGSHIFT; + max = (unsigned long)pg_info.mxfree << MM_PGSHIFT; linesize = procfs_snprintf(procfile->line, MEMINFO_LINELEN, - "%12s:%11lu%11lu%11lu%11lu\n", + "%10s:%11lu%11lu%11lu%11lu\n", "Page", total, allocated, available, max); copysize = procfs_memcpy(procfile->line, linesize, buffer, buflen, @@ -377,7 +377,7 @@ static ssize_t meminfo_read(FAR struct file *filep, FAR char *buffer, meminfo_progmem(&progmem); linesize = procfs_snprintf(procfile->line, MEMINFO_LINELEN, - "%12s:%11lu%11lu%11lu%11lu%7lu%7lu\n", + "%10s:%11lu%11lu%11lu%11lu%7lu%7lu\n", "Prog", (unsigned long)progmem.arena, (unsigned long)progmem.uordblks, diff --git a/fs/procfs/fs_procfsproc.c b/fs/procfs/fs_procfsproc.c index c6b7145c0f126..4f5911e13042c 100644 --- a/fs/procfs/fs_procfsproc.c +++ b/fs/procfs/fs_procfsproc.c @@ -43,6 +43,7 @@ # include #endif +#include #include #include #include @@ -53,6 +54,7 @@ #include #include #include +#include #if !defined(CONFIG_SCHED_CPULOAD_NONE) || defined(CONFIG_SCHED_CRITMONITOR) # include @@ -1122,7 +1124,8 @@ static ssize_t proc_groupstatus(FAR struct proc_file_s *procfile, size_t copysize; size_t totalsize; #ifdef HAVE_GROUP_MEMBERS - int i; + FAR sq_entry_t *curr; + FAR sq_entry_t *next; #endif DEBUGASSERT(group != NULL); @@ -1168,13 +1171,14 @@ static ssize_t proc_groupstatus(FAR struct proc_file_s *procfile, buffer += copysize; remaining -= copysize; +#ifdef HAVE_GROUP_MEMBERS if (totalsize >= buflen) { return totalsize; } - linesize = procfs_snprintf(procfile->line, STATUS_LINELEN, "%-12s%d\n", - "Members:", group->tg_nmembers); + linesize = procfs_snprintf(procfile->line, STATUS_LINELEN, "%-12s%zu\n", + "Members:", sq_count(&group->tg_members)); copysize = procfs_memcpy(procfile->line, linesize, buffer, remaining, &offset); @@ -1182,7 +1186,6 @@ static ssize_t proc_groupstatus(FAR struct proc_file_s *procfile, buffer += copysize; remaining -= copysize; -#ifdef HAVE_GROUP_MEMBERS if (totalsize >= buflen) { return totalsize; @@ -1202,10 +1205,11 @@ static ssize_t proc_groupstatus(FAR struct proc_file_s *procfile, return totalsize; } - for (i = 0; i < group->tg_nmembers; i++) + sq_for_every_safe(&group->tg_members, curr, next) { + tcb = container_of(curr, struct tcb_s, member); linesize = procfs_snprintf(procfile->line, STATUS_LINELEN, " %d", - group->tg_members[i]); + tcb->pid); copysize = procfs_memcpy(procfile->line, linesize, buffer, remaining, &offset); diff --git a/fs/procfs/fs_procfsversion.c b/fs/procfs/fs_procfsversion.c index dabd0be5f60b4..cb182818b4ed0 100644 --- a/fs/procfs/fs_procfsversion.c +++ b/fs/procfs/fs_procfsversion.c @@ -201,8 +201,9 @@ static ssize_t version_read(FAR struct file *filep, FAR char *buffer, { uname(&name); linesize = procfs_snprintf(attr->line, VERSION_LINELEN, - "%s version %s %s\n", - name.sysname, name.release, name.version); + "%s version %s %s %s\n", + name.sysname, name.release, name.version, + CONFIG_BASE_DEFCONFIG); /* Save the linesize in case we are re-entered with f_pos > 0 */ diff --git a/fs/romfs/fs_romfs.h b/fs/romfs/fs_romfs.h index 20eabc3bc2c10..71dd3f716601b 100644 --- a/fs/romfs/fs_romfs.h +++ b/fs/romfs/fs_romfs.h @@ -160,14 +160,12 @@ struct romfs_file_s struct romfs_nodeinfo_s { -#ifdef CONFIG_FS_ROMFS_CACHE_NODE - FAR struct romfs_nodeinfo_s **rn_child; /* The node array for link to lower level */ - uint16_t rn_count; /* The count of node in rn_child level */ -#endif uint32_t rn_offset; /* Offset of real file header */ uint32_t rn_next; /* Offset of the next file header+flags */ uint32_t rn_size; /* Size (if file) */ #ifdef CONFIG_FS_ROMFS_CACHE_NODE + FAR struct romfs_nodeinfo_s **rn_child; /* The node array for link to lower level */ + uint16_t rn_count; /* The count of node in rn_child level */ uint8_t rn_namesize; /* The length of name of the entry */ char rn_name[1]; /* The name to the entry */ #endif diff --git a/fs/rpmsgfs/Kconfig b/fs/rpmsgfs/Kconfig index f4c88cc747965..957c84199b5be 100644 --- a/fs/rpmsgfs/Kconfig +++ b/fs/rpmsgfs/Kconfig @@ -6,7 +6,7 @@ config FS_RPMSGFS bool "RPMSG File System" default n - depends on RPTUN + depends on RPMSG ---help--- Use RPMSG file system to mount remote directories to local. This the method for user to use remote file like own core. @@ -14,6 +14,6 @@ config FS_RPMSGFS config FS_RPMSGFS_SERVER bool "RPMSG File Server" default n - depends on RPTUN + depends on RPMSG ---help--- Initialize RPMSG file system server automatically. diff --git a/fs/rpmsgfs/rpmsgfs.h b/fs/rpmsgfs/rpmsgfs.h index 271ab340b5172..24bcaeb1e5d5b 100644 --- a/fs/rpmsgfs/rpmsgfs.h +++ b/fs/rpmsgfs/rpmsgfs.h @@ -115,19 +115,35 @@ begin_packed_struct struct rpmsgfs_ioctl_s #define rpmsgfs_sync_s rpmsgfs_close_s #define rpmsgfs_dup_s rpmsgfs_close_s -begin_packed_struct struct rpmsgfs_fstat_s +begin_packed_struct struct rpmsgfs_stat_priv_s { - struct rpmsgfs_header_s header; - union - { - struct stat buf; - uint32_t reserved[16]; - }; + uint32_t dev; /* Device ID of device containing file */ + uint32_t mode; /* File type, attributes, and access mode bits */ + uint32_t rdev; /* Device ID (if file is character or block special) */ + uint16_t ino; /* File serial number */ + uint16_t nlink; /* Number of hard links to the file */ + int64_t size; /* Size of file/directory, in bytes */ + int64_t atim_sec; /* Time of last access, seconds */ + int64_t atim_nsec; /* Time of last access, nanoseconds */ + int64_t mtim_sec; /* Time of last modification, seconds */ + int64_t mtim_nsec; /* Time of last modification, nanoseconds */ + int64_t ctim_sec; /* Time of last status change, seconds */ + int64_t ctim_nsec; /* Time of last status change, nanoseconds */ + uint64_t blocks; /* Number of blocks allocated */ + int16_t uid; /* User ID of file */ + int16_t gid; /* Group ID of file */ + int16_t blksize; /* Block size used for filesystem I/O */ + uint16_t reserved; /* Reserved space */ +} end_packed_struct; +begin_packed_struct struct rpmsgfs_fstat_s +{ + struct rpmsgfs_header_s header; + struct rpmsgfs_stat_priv_s buf; union { - int32_t fd; - char pathname[0]; + int32_t fd; + char pathname[0]; }; } end_packed_struct; @@ -158,12 +174,15 @@ begin_packed_struct struct rpmsgfs_readdir_s begin_packed_struct struct rpmsgfs_statfs_s { struct rpmsgfs_header_s header; - union - { - struct statfs buf; - uint32_t reserved[16]; - }; - + uint32_t type; /* Type of filesystem */ + uint32_t reserved; /* Reserved space */ + uint64_t namelen; /* Maximum length of filenames */ + uint64_t bsize; /* Optimal block size for transfers */ + uint64_t blocks; /* Total data blocks in the file system of this size */ + uint64_t bfree; /* Free blocks in the file system */ + uint64_t bavail; /* Free blocks avail to non-superuser */ + uint64_t files; /* Total file nodes in the file system */ + uint64_t ffree; /* Free file nodes in the file system */ char pathname[0]; } end_packed_struct; @@ -183,18 +202,13 @@ begin_packed_struct struct rpmsgfs_mkdir_s begin_packed_struct struct rpmsgfs_fchstat_s { - struct rpmsgfs_header_s header; - int32_t flags; - union - { - struct stat buf; - uint32_t reserved[16]; - }; - + struct rpmsgfs_header_s header; + struct rpmsgfs_stat_priv_s buf; + int32_t flags; union { - int32_t fd; - char pathname[0]; + int32_t fd; + char pathname[0]; }; } end_packed_struct; diff --git a/fs/rpmsgfs/rpmsgfs_client.c b/fs/rpmsgfs/rpmsgfs_client.c index b2c65bbe890cd..cf47ea80bd27f 100644 --- a/fs/rpmsgfs/rpmsgfs_client.c +++ b/fs/rpmsgfs/rpmsgfs_client.c @@ -219,14 +219,14 @@ static int rpmsgfs_statfs_handler(FAR struct rpmsg_endpoint *ept, cookie->result = header->result; if (cookie->result >= 0) { - buf->f_type = rsp->buf.f_type; - buf->f_namelen = rsp->buf.f_namelen; - buf->f_bsize = rsp->buf.f_bsize; - buf->f_blocks = rsp->buf.f_blocks; - buf->f_bfree = rsp->buf.f_bfree; - buf->f_bavail = rsp->buf.f_bavail; - buf->f_files = rsp->buf.f_files; - buf->f_ffree = rsp->buf.f_ffree; + buf->f_type = rsp->type; + buf->f_namelen = rsp->namelen; + buf->f_bsize = rsp->bsize; + buf->f_blocks = rsp->blocks; + buf->f_bfree = rsp->bfree; + buf->f_bavail = rsp->bavail; + buf->f_files = rsp->files; + buf->f_ffree = rsp->ffree; } rpmsg_post(ept, &cookie->sem); @@ -247,19 +247,22 @@ static int rpmsgfs_stat_handler(FAR struct rpmsg_endpoint *ept, cookie->result = header->result; if (cookie->result >= 0) { - buf->st_dev = rsp->buf.st_dev; - buf->st_ino = rsp->buf.st_ino; - buf->st_mode = rsp->buf.st_mode; - buf->st_nlink = rsp->buf.st_nlink; - buf->st_uid = rsp->buf.st_uid; - buf->st_gid = rsp->buf.st_gid; - buf->st_rdev = rsp->buf.st_rdev; - buf->st_size = rsp->buf.st_size; - buf->st_atime = rsp->buf.st_atime; - buf->st_mtime = rsp->buf.st_mtime; - buf->st_ctime = rsp->buf.st_ctime; - buf->st_blksize = rsp->buf.st_blksize; - buf->st_blocks = rsp->buf.st_blocks; + buf->st_dev = rsp->buf.dev; + buf->st_ino = rsp->buf.ino; + buf->st_mode = rsp->buf.mode; + buf->st_nlink = rsp->buf.nlink; + buf->st_uid = rsp->buf.uid; + buf->st_gid = rsp->buf.gid; + buf->st_rdev = rsp->buf.rdev; + buf->st_size = rsp->buf.size; + buf->st_atim.tv_sec = rsp->buf.atim_sec; + buf->st_atim.tv_nsec = rsp->buf.atim_nsec; + buf->st_mtim.tv_sec = rsp->buf.mtim_sec; + buf->st_mtim.tv_nsec = rsp->buf.mtim_nsec; + buf->st_ctim.tv_sec = rsp->buf.ctim_sec; + buf->st_ctim.tv_nsec = rsp->buf.ctim_nsec; + buf->st_blksize = rsp->buf.blksize; + buf->st_blocks = rsp->buf.blocks; } rpmsg_post(ept, &cookie->sem); @@ -909,9 +912,24 @@ int rpmsgfs_client_fchstat(FAR void *handle, int fd, { struct rpmsgfs_fchstat_s msg = { - .flags = flags, - .buf = *buf, - .fd = fd, + .buf.dev = buf->st_dev, + .buf.ino = buf->st_ino, + .buf.mode = buf->st_mode, + .buf.nlink = buf->st_nlink, + .buf.uid = buf->st_uid, + .buf.gid = buf->st_gid, + .buf.rdev = buf->st_rdev, + .buf.size = buf->st_size, + .buf.atim_sec = buf->st_atim.tv_sec, + .buf.atim_nsec = buf->st_atim.tv_nsec, + .buf.mtim_sec = buf->st_mtim.tv_sec, + .buf.mtim_nsec = buf->st_mtim.tv_nsec, + .buf.ctim_sec = buf->st_ctim.tv_sec, + .buf.ctim_nsec = buf->st_ctim.tv_nsec, + .buf.blksize = buf->st_blksize, + .buf.blocks = buf->st_blocks, + .flags = flags, + .fd = fd, }; return rpmsgfs_send_recv(handle, RPMSGFS_FCHSTAT, true, diff --git a/fs/rpmsgfs/rpmsgfs_server.c b/fs/rpmsgfs/rpmsgfs_server.c index 00cd0636e5457..775b1452f3418 100644 --- a/fs/rpmsgfs/rpmsgfs_server.c +++ b/fs/rpmsgfs/rpmsgfs_server.c @@ -547,7 +547,22 @@ static int rpmsgfs_fstat_handler(FAR struct rpmsg_endpoint *ept, ret = file_fstat(filep, &buf); if (ret >= 0) { - msg->buf = buf; + msg->buf.dev = buf.st_dev; + msg->buf.ino = buf.st_ino; + msg->buf.mode = buf.st_mode; + msg->buf.nlink = buf.st_nlink; + msg->buf.uid = buf.st_uid; + msg->buf.gid = buf.st_gid; + msg->buf.rdev = buf.st_rdev; + msg->buf.size = buf.st_size; + msg->buf.atim_sec = buf.st_atim.tv_sec; + msg->buf.atim_nsec = buf.st_atim.tv_nsec; + msg->buf.mtim_sec = buf.st_mtim.tv_sec; + msg->buf.mtim_nsec = buf.st_mtim.tv_nsec; + msg->buf.ctim_sec = buf.st_ctim.tv_sec; + msg->buf.ctim_nsec = buf.st_ctim.tv_nsec; + msg->buf.blksize = buf.st_blksize; + msg->buf.blocks = buf.st_blocks; } } @@ -611,8 +626,8 @@ static int rpmsgfs_readdir_handler(FAR struct rpmsg_endpoint *ept, entry = readdir(dir); if (entry) { - size = MIN(rpmsg_virtio_get_buffer_size(ept->rdev), - rpmsg_virtio_get_rx_buffer_size(ept->rdev)); + size = MIN(rpmsg_get_tx_buffer_size(ept->rdev), + rpmsg_get_rx_buffer_size(ept->rdev)); size = MIN(size - len, strlen(entry->d_name) + 1); msg->type = entry->d_type; strlcpy(msg->name, entry->d_name, size); @@ -677,7 +692,14 @@ static int rpmsgfs_statfs_handler(FAR struct rpmsg_endpoint *ept, } else { - msg->buf = buf; + msg->type = buf.f_type; + msg->namelen = buf.f_namelen; + msg->bsize = buf.f_bsize; + msg->blocks = buf.f_blocks; + msg->bfree = buf.f_bfree; + msg->bavail = buf.f_bavail; + msg->files = buf.f_files; + msg->ffree = buf.f_ffree; } msg->header.result = ret; @@ -746,7 +768,22 @@ static int rpmsgfs_stat_handler(FAR struct rpmsg_endpoint *ept, ret = nx_stat(msg->pathname, &buf, 1); if (ret >= 0) { - msg->buf = buf; + msg->buf.dev = buf.st_dev; + msg->buf.ino = buf.st_ino; + msg->buf.mode = buf.st_mode; + msg->buf.nlink = buf.st_nlink; + msg->buf.uid = buf.st_uid; + msg->buf.gid = buf.st_gid; + msg->buf.rdev = buf.st_rdev; + msg->buf.size = buf.st_size; + msg->buf.atim_sec = buf.st_atim.tv_sec; + msg->buf.atim_nsec = buf.st_atim.tv_nsec; + msg->buf.mtim_sec = buf.st_mtim.tv_sec; + msg->buf.mtim_nsec = buf.st_mtim.tv_nsec; + msg->buf.ctim_sec = buf.st_ctim.tv_sec; + msg->buf.ctim_nsec = buf.st_ctim.tv_nsec; + msg->buf.blksize = buf.st_blksize; + msg->buf.blocks = buf.st_blocks; } msg->header.result = ret; @@ -765,7 +802,23 @@ static int rpmsgfs_fchstat_handler(FAR struct rpmsg_endpoint *ept, filep = rpmsgfs_get_file(priv, msg->fd); if (filep != NULL) { - buf = msg->buf; + buf.st_dev = msg->buf.dev; + buf.st_ino = msg->buf.ino; + buf.st_mode = msg->buf.mode; + buf.st_nlink = msg->buf.nlink ; + buf.st_uid = msg->buf.uid ; + buf.st_gid = msg->buf.gid; + buf.st_rdev = msg->buf.rdev; + buf.st_size = msg->buf.size; + buf.st_atim.tv_sec = msg->buf.atim_sec; + buf.st_atim.tv_nsec = msg->buf.atim_nsec; + buf.st_mtim.tv_sec = msg->buf.mtim_sec; + buf.st_mtim.tv_nsec = msg->buf.mtim_nsec; + buf.st_ctim.tv_sec = msg->buf.ctim_sec; + buf.st_ctim.tv_nsec = msg->buf.ctim_nsec; + buf.st_blksize = msg->buf.blksize; + buf.st_blocks = msg->buf.blocks; + ret = file_fchstat(filep, &buf, msg->flags); } @@ -783,7 +836,7 @@ static int rpmsgfs_chstat_handler(FAR struct rpmsg_endpoint *ept, if (msg->flags & CH_STAT_MODE) { - ret = chmod(msg->pathname, msg->buf.st_mode); + ret = chmod(msg->pathname, msg->buf.mode); if (ret < 0) { ret = -get_errno(); @@ -793,7 +846,7 @@ static int rpmsgfs_chstat_handler(FAR struct rpmsg_endpoint *ept, if (msg->flags & (CH_STAT_UID | CH_STAT_GID)) { - ret = chown(msg->pathname, msg->buf.st_uid, msg->buf.st_gid); + ret = chown(msg->pathname, msg->buf.uid, msg->buf.gid); if (ret < 0) { ret = -get_errno(); @@ -805,7 +858,8 @@ static int rpmsgfs_chstat_handler(FAR struct rpmsg_endpoint *ept, { if (msg->flags & CH_STAT_ATIME) { - times[0] = msg->buf.st_atim; + times[0].tv_sec = msg->buf.atim_sec; + times[0].tv_nsec = msg->buf.atim_nsec; } else { @@ -815,7 +869,8 @@ static int rpmsgfs_chstat_handler(FAR struct rpmsg_endpoint *ept, if (msg->flags & CH_STAT_MTIME) { - times[1] = msg->buf.st_mtim; + times[1].tv_sec = msg->buf.mtim_sec; + times[1].tv_nsec = msg->buf.mtim_nsec; } else { diff --git a/fs/shm/CMakeLists.txt b/fs/shm/CMakeLists.txt index d76fb17e3bcdd..d6770ea4f13c1 100644 --- a/fs/shm/CMakeLists.txt +++ b/fs/shm/CMakeLists.txt @@ -20,6 +20,6 @@ # Include POSIX message queue support -if(CONFIG_FS_SHM) +if(CONFIG_FS_SHMFS) target_sources(fs PRIVATE shm_open.c shm_unlink.c shmfs.c shmfs_alloc.c) endif() diff --git a/fs/shm/Kconfig b/fs/shm/Kconfig index 7ec28209a0bdb..77bdbe5a320f4 100644 --- a/fs/shm/Kconfig +++ b/fs/shm/Kconfig @@ -19,4 +19,4 @@ config FS_SHMFS_VFS_PATH The path to where shared memory objects will exist in the VFS namespace. -endif # FS_SHM +endif # FS_SHMFS diff --git a/fs/shm/shmfs.c b/fs/shm/shmfs.c index fef22222efd11..b7095907e7cf7 100644 --- a/fs/shm/shmfs.c +++ b/fs/shm/shmfs.c @@ -238,8 +238,13 @@ static int shmfs_truncate(FAR struct file *filep, off_t length) filep->f_inode->i_private = shmfs_alloc_object(length); if (!filep->f_inode->i_private) { + filep->f_inode->i_size = 0; ret = -EFAULT; } + else + { + filep->f_inode->i_size = length; + } } else if (object->length != length) { diff --git a/fs/shm/shmfs_alloc.c b/fs/shm/shmfs_alloc.c index 979fd4c3f4648..65fb74ca3efd4 100644 --- a/fs/shm/shmfs_alloc.c +++ b/fs/shm/shmfs_alloc.c @@ -22,7 +22,11 @@ * Included Files ****************************************************************************/ +#include + #include + +#include #include #include @@ -87,6 +91,12 @@ FAR struct shmfs_object_s *shmfs_alloc_object(size_t length) { break; } + else + { + /* Clear the page memory (requirement for truncate) */ + + up_addrenv_page_wipe((uintptr_t)pages[i]); + } } } diff --git a/fs/tmpfs/fs_tmpfs.c b/fs/tmpfs/fs_tmpfs.c index 46a5bf1001357..e4f5e6b2579b5 100644 --- a/fs/tmpfs/fs_tmpfs.c +++ b/fs/tmpfs/fs_tmpfs.c @@ -37,6 +37,7 @@ #include #include +#include "inode/inode.h" #include "fs_tmpfs.h" #ifndef CONFIG_DISABLE_MOUNTPOINT @@ -100,10 +101,12 @@ static int tmpfs_remove_dirent(FAR struct tmpfs_directory_s *tdo, FAR const char *name); static int tmpfs_add_dirent(FAR struct tmpfs_directory_s *tdo, FAR struct tmpfs_object_s *to, FAR const char *name); -static FAR struct tmpfs_file_s *tmpfs_alloc_file(void); +static FAR struct tmpfs_file_s * +tmpfs_alloc_file(FAR struct tmpfs_directory_s *parent); static int tmpfs_create_file(FAR struct tmpfs_s *fs, FAR const char *relpath, FAR struct tmpfs_file_s **tfo); -static FAR struct tmpfs_directory_s *tmpfs_alloc_directory(void); +static FAR struct tmpfs_directory_s * +tmpfs_alloc_directory(FAR struct tmpfs_directory_s *parent); static int tmpfs_create_directory(FAR struct tmpfs_s *fs, FAR const char *relpath, FAR struct tmpfs_directory_s **tdo); static int tmpfs_find_object(FAR struct tmpfs_s *fs, @@ -135,6 +138,7 @@ static ssize_t tmpfs_read(FAR struct file *filep, FAR char *buffer, static ssize_t tmpfs_write(FAR struct file *filep, FAR const char *buffer, size_t buflen); static off_t tmpfs_seek(FAR struct file *filep, off_t offset, int whence); +static int tmpfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg); static int tmpfs_sync(FAR struct file *filep); static int tmpfs_dup(FAR const struct file *oldp, FAR struct file *newp); static int tmpfs_fstat(FAR const struct file *filep, FAR struct stat *buf); @@ -178,7 +182,7 @@ const struct mountpt_operations g_tmpfs_operations = tmpfs_read, /* read */ tmpfs_write, /* write */ tmpfs_seek, /* seek */ - NULL, /* ioctl */ + tmpfs_ioctl, /* ioctl */ tmpfs_mmap, /* mmap */ tmpfs_truncate, /* truncate */ NULL, /* poll */ @@ -523,6 +527,7 @@ static int tmpfs_add_dirent(FAR struct tmpfs_directory_s *tdo, /* Save the new object info in the new directory entry */ + to->to_parent = tdo; tde = &tdo->tdo_entry[index]; tde->tde_object = to; tde->tde_name = newname; @@ -534,7 +539,8 @@ static int tmpfs_add_dirent(FAR struct tmpfs_directory_s *tdo, * Name: tmpfs_alloc_file ****************************************************************************/ -static FAR struct tmpfs_file_s *tmpfs_alloc_file(void) +static FAR struct tmpfs_file_s * +tmpfs_alloc_file(FAR struct tmpfs_directory_s *parent) { FAR struct tmpfs_file_s *tfo; @@ -550,12 +556,13 @@ static FAR struct tmpfs_file_s *tmpfs_alloc_file(void) * locked with one reference count. */ - tfo->tfo_alloc = 0; - tfo->tfo_type = TMPFS_REGULAR; - tfo->tfo_refs = 1; - tfo->tfo_flags = 0; - tfo->tfo_size = 0; - tfo->tfo_data = NULL; + tfo->tfo_alloc = 0; + tfo->tfo_type = TMPFS_REGULAR; + tfo->tfo_refs = 1; + tfo->tfo_parent = parent; + tfo->tfo_flags = 0; + tfo->tfo_size = 0; + tfo->tfo_data = NULL; nxrmutex_init(&tfo->tfo_lock); tmpfs_lock_file(tfo); @@ -643,7 +650,7 @@ static int tmpfs_create_file(FAR struct tmpfs_s *fs, * one reference count. */ - newtfo = tmpfs_alloc_file(); + newtfo = tmpfs_alloc_file(parent); if (newtfo == NULL) { ret = -ENOMEM; @@ -684,7 +691,8 @@ static int tmpfs_create_file(FAR struct tmpfs_s *fs, * Name: tmpfs_alloc_directory ****************************************************************************/ -static FAR struct tmpfs_directory_s *tmpfs_alloc_directory(void) +static FAR struct tmpfs_directory_s * +tmpfs_alloc_directory(FAR struct tmpfs_directory_s *parent) { FAR struct tmpfs_directory_s *tdo; @@ -701,6 +709,7 @@ static FAR struct tmpfs_directory_s *tmpfs_alloc_directory(void) tdo->tdo_alloc = 0; tdo->tdo_type = TMPFS_DIRECTORY; tdo->tdo_refs = 0; + tdo->tdo_parent = parent; tdo->tdo_nentries = 0; tdo->tdo_entry = NULL; @@ -788,7 +797,7 @@ static int tmpfs_create_directory(FAR struct tmpfs_s *fs, * the new directory and the object is not locked. */ - newtdo = tmpfs_alloc_directory(); + newtdo = tmpfs_alloc_directory(parent); if (newtdo == NULL) { ret = -ENOMEM; @@ -1070,6 +1079,52 @@ static int tmpfs_find_directory(FAR struct tmpfs_s *fs, return ret; } +/**************************************************************************** + * Name: tmpfs_getpath + ****************************************************************************/ + +static int tmpfs_getpath(FAR struct tmpfs_object_s *to, + FAR char *path, size_t len) +{ + FAR struct tmpfs_dirent_s *tde = NULL; + FAR struct tmpfs_directory_s *tdo; + uint16_t i; + + if (to->to_parent != NULL) + { + int ret = tmpfs_getpath((FAR struct tmpfs_object_s *)to->to_parent, + path, len); + if (ret < 0) + { + return ret; + } + + tdo = to->to_parent; + + for (i = 0; i < tdo->tdo_nentries; i++) + { + tde = &tdo->tdo_entry[i]; + if (to == tde->tde_object) + { + break; + } + } + + if (i == tdo->tdo_nentries) + { + return -ENOENT; + } + + strlcat(path, tde->tde_name, len); + if (to->to_type == TMPFS_DIRECTORY) + { + strlcat(path, "/", len); + } + } + + return OK; +} + /**************************************************************************** * Name: tmpfs_statfs_callout ****************************************************************************/ @@ -1712,6 +1767,44 @@ static int tmpfs_mmap(FAR struct file *filep, FAR struct mm_map_entry_s *map) return ret; } +/**************************************************************************** + * Name: tmpfs_ioctl + ****************************************************************************/ + +static int tmpfs_ioctl(FAR struct file *filep, int cmd, unsigned long arg) +{ + FAR struct tmpfs_file_s *tfo; + int ret = -ENOTTY; + + /* Sanity checks */ + + DEBUGASSERT(filep->f_priv != NULL); + + /* Recover our private data from the struct file instance */ + + tfo = filep->f_priv; + + /* Only one ioctl command is supported */ + + if (cmd == FIOC_FILEPATH) + { + FAR char *ptr = (FAR char *)((uintptr_t)arg); + ret = inode_getpath(filep->f_inode, ptr, PATH_MAX); + if (ret < 0) + { + return ret; + } + + ret = tmpfs_getpath((FAR struct tmpfs_object_s *)tfo, ptr, PATH_MAX); + if (ret < 0) + { + return ret; + } + } + + return ret; +} + /**************************************************************************** * Name: tmpfs_sync ****************************************************************************/ @@ -2071,7 +2164,7 @@ static int tmpfs_bind(FAR struct inode *blkdriver, FAR const void *data, * the file system structure. */ - tdo = tmpfs_alloc_directory(); + tdo = tmpfs_alloc_directory(NULL); if (tdo == NULL) { kmm_free(fs); diff --git a/fs/tmpfs/fs_tmpfs.h b/fs/tmpfs/fs_tmpfs.h index 49a640fff9eab..0a352dd51c94a 100644 --- a/fs/tmpfs/fs_tmpfs.h +++ b/fs/tmpfs/fs_tmpfs.h @@ -79,6 +79,7 @@ struct tmpfs_object_s size_t to_alloc; /* Allocated size of the memory object */ uint8_t to_type; /* See enum tmpfs_objtype_e */ uint8_t to_refs; /* Reference count */ + FAR struct tmpfs_directory_s *to_parent; }; /* The form of a directory memory object */ @@ -92,6 +93,7 @@ struct tmpfs_directory_s size_t tdo_alloc; /* Allocated size of the directory object */ uint8_t tdo_type; /* See enum tmpfs_objtype_e */ uint8_t tdo_refs; /* Reference count */ + FAR struct tmpfs_directory_s *tdo_parent; /* Remaining fields are unique to a directory object */ @@ -118,6 +120,7 @@ struct tmpfs_file_s size_t tfo_alloc; /* Allocated size of the file object */ uint8_t tfo_type; /* See enum tmpfs_objtype_e */ uint8_t tfo_refs; /* Reference count */ + FAR struct tmpfs_directory_s *tfo_parent; /* Remaining fields are unique to a directory object */ diff --git a/fs/vfs/CMakeLists.txt b/fs/vfs/CMakeLists.txt index deae984d4975d..2321dd59fd84e 100644 --- a/fs/vfs/CMakeLists.txt +++ b/fs/vfs/CMakeLists.txt @@ -48,6 +48,12 @@ set(SRCS fs_fsync.c fs_truncate.c) +# File lock support + +if(NOT "${CONFIG_FS_LOCK_BUCKET_SIZE}" STREQUAL "0") + list(APPEND SRCS fs_lock.c) +endif() + # Certain interfaces are not available if there is no mountpoint support if(NOT "${CONFIG_PSEUDOFS_SOFTLINKS}" STREQUAL "0") diff --git a/fs/vfs/Make.defs b/fs/vfs/Make.defs index de19051342b1e..1e8c5b8d4719d 100644 --- a/fs/vfs/Make.defs +++ b/fs/vfs/Make.defs @@ -29,6 +29,10 @@ CSRCS += fs_syncfs.c fs_truncate.c # Certain interfaces are not available if there is no mountpoint support +ifneq ($(CONFIG_FS_LOCK_BUCKET_SIZE),0) +CSRCS += fs_lock.c +endif + ifneq ($(CONFIG_PSEUDOFS_SOFTLINKS),0) CSRCS += fs_link.c fs_symlink.c fs_readlink.c endif diff --git a/fs/vfs/fs_close.c b/fs/vfs/fs_close.c index 926f48f4804cf..6058a41c047a4 100644 --- a/fs/vfs/fs_close.c +++ b/fs/vfs/fs_close.c @@ -28,20 +28,23 @@ #include #include #include +#include #include #include "inode/inode.h" +#include "vfs/lock.h" /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: file_close + * Name: file_close_without_clear * * Description: - * Close a file that was previously opened with file_open(). + * Close a file that was previously opened with file_open(), but without + * clear filep. * * Input Parameters: * filep - A pointer to a user provided memory location containing the @@ -53,7 +56,7 @@ * ****************************************************************************/ -int file_close(FAR struct file *filep) +int file_close_without_clear(FAR struct file *filep) { struct inode *inode; int ret = OK; @@ -65,6 +68,8 @@ int file_close(FAR struct file *filep) if (inode) { + file_closelk(filep); + /* Close the file, driver, or mountpoint. */ if (inode->u.i_ops && inode->u.i_ops->close) @@ -77,10 +82,45 @@ int file_close(FAR struct file *filep) /* And release the inode */ inode_release(inode); + } + + return ret; +} + +/**************************************************************************** + * Name: file_close + * + * Description: + * Close a file that was previously opened with file_open(). + * + * Input Parameters: + * filep - A pointer to a user provided memory location containing the + * open file data returned by file_open(). + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int file_close(FAR struct file *filep) +{ + int ret; + ret = file_close_without_clear(filep); + if (ret >= 0 && filep->f_inode) + { /* Reset the user file struct instance so that it cannot be reused. */ - memset(filep, 0, sizeof(*filep)); + filep->f_inode = NULL; + +#ifdef CONFIG_FDCHECK + filep->f_tag_fdcheck = 0; +#endif + +#ifdef CONFIG_FDSAN + filep->f_tag_fdsan = 0; +#endif } return ret; diff --git a/fs/vfs/fs_dup2.c b/fs/vfs/fs_dup2.c index cdfb9809dfd71..f5917456e7774 100644 --- a/fs/vfs/fs_dup2.c +++ b/fs/vfs/fs_dup2.c @@ -58,7 +58,6 @@ int file_dup3(FAR struct file *filep1, FAR struct file *filep2, int flags) { FAR struct inode *inode; - struct file temp; int ret; if (filep1 == NULL || filep1->f_inode == NULL || filep2 == NULL) @@ -85,23 +84,32 @@ int file_dup3(FAR struct file *filep1, FAR struct file *filep2, int flags) return ret; } - /* Then clone the file structure */ + /* If there is already an inode contained in the new file structure, + * close the file and release the inode. + * But we need keep the filep2->f_inode, incase of realloced by others. + */ - memset(&temp, 0, sizeof(temp)); + ret = file_close_without_clear(filep2); + if (ret < 0) + { + inode_release(inode); + return ret; + } /* The two filep don't share flags (the close-on-exec flag). */ if (flags == O_CLOEXEC) { - temp.f_oflags = filep1->f_oflags | O_CLOEXEC; + filep2->f_oflags = filep1->f_oflags | O_CLOEXEC; } else { - temp.f_oflags = filep1->f_oflags & ~O_CLOEXEC; + filep2->f_oflags = filep1->f_oflags & ~O_CLOEXEC; } - temp.f_pos = filep1->f_pos; - temp.f_inode = inode; + filep2->f_priv = NULL; + filep2->f_pos = filep1->f_pos; + filep2->f_inode = inode; /* Call the open method on the file, driver, mountpoint so that it * can maintain the correct open counts. @@ -116,7 +124,7 @@ int file_dup3(FAR struct file *filep1, FAR struct file *filep2, int flags) if (inode->u.i_mops->dup) { - ret = inode->u.i_mops->dup(filep1, &temp); + ret = inode->u.i_mops->dup(filep1, filep2); } } else @@ -124,25 +132,25 @@ int file_dup3(FAR struct file *filep1, FAR struct file *filep2, int flags) { /* (Re-)open the pseudo file or device driver */ - temp.f_priv = filep1->f_priv; + filep2->f_priv = filep1->f_priv; /* Add nonblock flags to avoid happening block when * calling open() */ - temp.f_oflags |= O_NONBLOCK; + filep2->f_oflags |= O_NONBLOCK; if (inode->u.i_ops->open) { - ret = inode->u.i_ops->open(&temp); + ret = inode->u.i_ops->open(filep2); } if (ret >= 0 && (filep1->f_oflags & O_NONBLOCK) == 0) { - ret = file_ioctl(&temp, FIONBIO, 0); + ret = file_ioctl(filep2, FIONBIO, 0); if (ret < 0 && inode->u.i_ops->close) { - ret = inode->u.i_ops->close(&temp); + ret = inode->u.i_ops->close(filep2); } } } @@ -156,16 +164,16 @@ int file_dup3(FAR struct file *filep1, FAR struct file *filep2, int flags) } } - /* If there is already an inode contained in the new file structure, - * close the file and release the inode. - */ + /* Copy tag */ - ret = file_close(filep2); - DEBUGASSERT(ret == 0); +#ifdef CONFIG_FDSAN + filep2->f_tag_fdsan = filep1->f_tag_fdsan; +#endif - /* Return the file structure */ +#ifdef CONFIG_FDCHECK + filep2->f_tag_fdcheck = filep1->f_tag_fdcheck; +#endif - memcpy(filep2, &temp, sizeof(temp)); return OK; } diff --git a/fs/vfs/fs_epoll.c b/fs/vfs/fs_epoll.c index 40ed949e32e71..ab51b46f651e3 100644 --- a/fs/vfs/fs_epoll.c +++ b/fs/vfs/fs_epoll.c @@ -33,6 +33,7 @@ #include #include +#include #include #include #include diff --git a/fs/vfs/fs_fcntl.c b/fs/vfs/fs_fcntl.c index 6cf31a0536835..925a605e8924b 100644 --- a/fs/vfs/fs_fcntl.c +++ b/fs/vfs/fs_fcntl.c @@ -35,6 +35,7 @@ #include #include "inode/inode.h" +#include "lock.h" /**************************************************************************** * Private Functions @@ -195,6 +196,12 @@ static int file_vfcntl(FAR struct file *filep, int cmd, va_list ap) * for the lock type which shall be set to F_UNLCK. */ + { + FAR struct flock *flock = va_arg(ap, FAR struct flock *); + ret = file_getlk(filep, flock); + } + + break; case F_SETLK: /* Set or clear a file segment lock according to the lock * description pointed to by the third argument, arg, taken as a @@ -206,6 +213,12 @@ static int file_vfcntl(FAR struct file *filep, int cmd, va_list ap) * shall return immediately with a return value of -1. */ + { + FAR struct flock *flock = va_arg(ap, FAR struct flock *); + ret = file_setlk(filep, flock, true); + } + + break; case F_SETLKW: /* This command shall be equivalent to F_SETLK except that if a * shared or exclusive lock is blocked by other locks, the thread @@ -216,9 +229,12 @@ static int file_vfcntl(FAR struct file *filep, int cmd, va_list ap) * the lock operation shall not be done. */ - ret = -ENOSYS; /* Not implemented */ - break; + { + FAR struct flock *flock = va_arg(ap, FAR struct flock *); + ret = file_setlk(filep, flock, false); + } + break; case F_GETPATH: /* Get the path of the file descriptor. The argument must be a buffer * of size PATH_MAX or greater. diff --git a/fs/vfs/fs_ioctl.c b/fs/vfs/fs_ioctl.c index 97e098132f292..672a92edcd9ec 100644 --- a/fs/vfs/fs_ioctl.c +++ b/fs/vfs/fs_ioctl.c @@ -43,9 +43,6 @@ static int file_vioctl(FAR struct file *filep, int req, va_list ap) { FAR struct inode *inode; -#ifdef CONFIG_FDSAN - FAR uint64_t *tag; -#endif unsigned long arg; int ret = -ENOTTY; @@ -113,15 +110,25 @@ static int file_vioctl(FAR struct file *filep, int req, va_list ap) break; #ifdef CONFIG_FDSAN - case FIOC_SETTAG: - tag = (FAR uint64_t *)arg; - filep->f_tag = *tag; + case FIOC_SETTAG_FDSAN: + filep->f_tag_fdsan = *(FAR uint64_t *)arg; + ret = OK; + break; + + case FIOC_GETTAG_FDSAN: + *(FAR uint64_t *)arg = filep->f_tag_fdsan; + ret = OK; + break; +#endif + +#ifdef CONFIG_FDCHECK + case FIOC_SETTAG_FDCHECK: + filep->f_tag_fdcheck = *(FAR uint8_t *)arg; ret = OK; break; - case FIOC_GETTAG: - tag = (FAR uint64_t *)arg; - *tag = filep->f_tag; + case FIOC_GETTAG_FDCHECK: + *(FAR uint8_t *)arg = filep->f_tag_fdcheck; ret = OK; break; #endif diff --git a/fs/vfs/fs_lock.c b/fs/vfs/fs_lock.c new file mode 100644 index 0000000000000..333653a270443 --- /dev/null +++ b/fs/vfs/fs_lock.c @@ -0,0 +1,793 @@ +/**************************************************************************** + * fs/vfs/fs_lock.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "lock.h" +#include "sched/sched.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_FS_LARGEFILE +# define OFFSET_MAX INT64_MAX +#else +# define OFFSET_MAX INT32_MAX +#endif + +#define l_end l_len + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct file_lock_s +{ + struct flock fl_lock; /* File lock related information */ + FAR struct file *fl_file; /* Identifies the file descriptor information + * held by the caller + */ + struct list_node fl_node; /* Used to manage each filelock by means of a + * chained list. + */ +}; + +struct file_lock_bucket_s +{ + struct list_node list; /* Manage a chained list for each + * filelock + */ + sem_t wait; /* Blocking lock, called when SETLKW is + * called and there is a conflict. + */ + size_t nwaiter; /* Indicates how many blocking locks are + * currently blocked. + */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct hsearch_data g_file_lock_table; +static mutex_t g_protect_lock = NXMUTEX_INITIALIZER; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: file_lock_get_path + ****************************************************************************/ + +static int file_lock_get_path(FAR struct file *filep, FAR char *path) +{ + FAR struct tcb_s *tcb = this_task(); + + /* We only apply file lock on mount points (f_inode won't be NULL). */ + + if (!INODE_IS_MOUNTPT(filep->f_inode) || + tcb->flags & TCB_FLAG_SIGNAL_ACTION) + { + return -EBADF; + } + + return file_fcntl(filep, F_GETPATH, path); +} + +/**************************************************************************** + * Name: file_lock_normalize + ****************************************************************************/ + +static int file_lock_normalize(FAR struct file *filep, + FAR struct flock *flock, + FAR struct flock *out) +{ + off_t start; + off_t end; + + /* Check that the type brought in the flock is correct */ + + switch (flock->l_type) + { + case F_RDLCK: + case F_WRLCK: + case F_UNLCK: + break; + default: + return -EINVAL; + } + + /* Converts and saves flock information */ + + switch (flock->l_whence) + { + case SEEK_SET: + { + start = 0; + } + + break; + case SEEK_CUR: + { + start = filep->f_pos; + } + + break; + case SEEK_END: + { + struct stat st; + int ret; + + ret = file_fstat(filep, &st); + if (ret < 0) + { + return ret; + } + + start = st.st_size; + } + + break; + default: + return -EINVAL; + } + + /* Check for overflow in converted flock */ + + if (flock->l_start > OFFSET_MAX - start) + { + return -EOVERFLOW; + } + + start += flock->l_start; + if (start < 0) + { + return -EINVAL; + } + + if (flock->l_len > 0) + { + if (flock->l_len - 1 > OFFSET_MAX - start) + { + return -EOVERFLOW; + } + + end = start + flock->l_len - 1; + } + else if (flock->l_len < 0) + { + if (start + flock->l_len < 0) + { + return -EINVAL; + } + + end = start - 1; + start += flock->l_len; + } + else + { + end = OFFSET_MAX; + } + + out->l_whence = SEEK_SET; + out->l_type = flock->l_type; + out->l_start = start; + out->l_end = end; + + return OK; +} + +/**************************************************************************** + * Name: file_lock_delete + ****************************************************************************/ + +static void file_lock_delete(FAR struct file_lock_s *file_lock) +{ + list_delete(&file_lock->fl_node); + kmm_free(file_lock); +} + +/**************************************************************************** + * Name: file_lock_delete_bucket + ****************************************************************************/ + +static void file_lock_delete_bucket(FAR struct file_lock_bucket_s *bucket, + FAR const char *filepath) +{ + ENTRY item; + + /* If there is still a lock on the chain table at this point, it means + * that there is still someone else holding it, so it doesn't need to be + * released + */ + + if (list_is_empty(&bucket->list)) + { + /* At this point, the file has no lock information context, so we can + * remove it from the hash table, and the return result is 0 or 1 means + * that the node does not exist, so we do not need to care about the + * final return results + */ + + item.key = (FAR char *)filepath; + hsearch_r(item, DELETE, NULL, &g_file_lock_table); + } +} + +/**************************************************************************** + * Name: file_lock_is_conflict + ****************************************************************************/ + +static bool file_lock_is_conflict(FAR struct flock *request, + FAR struct flock *internal) +{ + /* If the request is not exactly to the left or right of the internal, + * then there is an overlap. + */ + + if (request->l_start <= internal->l_end && request->l_end >= + internal->l_start) + { + if (request->l_type == F_WRLCK || internal->l_type == F_WRLCK) + { + return request->l_pid != internal->l_pid; + } + } + + return false; +} + +/**************************************************************************** + * Name: file_lock_find_bucket + ****************************************************************************/ + +static FAR struct file_lock_bucket_s * +file_lock_find_bucket(FAR const char *filepath) +{ + FAR ENTRY *hretvalue; + ENTRY item; + + item.key = (FAR char *)filepath; + item.data = NULL; + + if (hsearch_r(item, FIND, &hretvalue, &g_file_lock_table) == 1) + { + return hretvalue->data; + } + + return NULL; +} + +/**************************************************************************** + * Name: file_lock_create_bucket + ****************************************************************************/ + +static FAR struct file_lock_bucket_s * +file_lock_create_bucket(FAR const char *filepath) +{ + FAR struct file_lock_bucket_s *bucket; + FAR ENTRY *hretvalue; + ENTRY item; + + bucket = kmm_zalloc(sizeof(*bucket)); + if (bucket == NULL) + { + return NULL; + } + + /* Creating an instance store */ + + item.key = strdup(filepath); + if (item.key == NULL) + { + kmm_free(bucket); + return NULL; + } + + item.data = bucket; + + if (hsearch_r(item, ENTER, &hretvalue, &g_file_lock_table) == 0) + { + lib_free(item.key); + kmm_free(bucket); + return NULL; + } + + list_initialize(&bucket->list); + nxsem_init(&bucket->wait, 0, 0); + + return bucket; +} + +/**************************************************************************** + * Name: file_lock_modify + ****************************************************************************/ + +static int file_lock_modify(FAR struct file *filep, + FAR struct file_lock_bucket_s *bucket, + FAR struct flock *request) +{ + FAR struct file_lock_s *new_file_lock = NULL; + FAR struct file_lock_s *right = NULL; + FAR struct file_lock_s *left = NULL; + FAR struct file_lock_s *file_lock; + FAR struct file_lock_s *tmp; + bool added = false; + bool find = false; + + list_for_every_entry_safe(&bucket->list, file_lock, tmp, + struct file_lock_s, fl_node) + { + if (request->l_pid != file_lock->fl_lock.l_pid) + { + /* Only file locks with the same pid need to be processed, so the + * lookup is skipped. + */ + + if (find) + { + /* We've searched around and come back to the beginning. */ + + break; + } + } + else + { + find = true; + + /* Checking the type of overlapping locks */ + + if (request->l_type == file_lock->fl_lock.l_type) + { + /* Compare the starting point of the last lock with the + * starting point of the request, and use start - 1 instead of + * end + 1, because if end is "off_t" max, then end + 1 will + * be negative. + */ + + if (request->l_start - 1 > file_lock->fl_lock.l_end) + { + continue; + } + + if (request->l_end < file_lock->fl_lock.l_start - 1) + { + break; + } + + /* If the two locks are of the same type, then they are merged + * into one lock with a lower start position and a higher end + * position. + */ + + if (request->l_start < file_lock->fl_lock.l_start) + { + file_lock->fl_lock.l_start = request->l_start; + } + else + { + request->l_start = file_lock->fl_lock.l_start; + } + + if (request->l_end > file_lock->fl_lock.l_end) + { + file_lock->fl_lock.l_end = request->l_end; + } + else + { + request->l_end = file_lock->fl_lock.l_end; + } + + if (added) + { + file_lock_delete(file_lock); + continue; + } + + request = &file_lock->fl_lock; + added = true; + } + else + { + if (request->l_start > file_lock->fl_lock.l_end) + { + continue; + } + + if (request->l_end < file_lock->fl_lock.l_start) + { + break; + } + + /* Scenarios for handling different types of locks */ + + if (request->l_type == F_UNLCK) + { + added = true; + } + + /* The new lock and the old lock are adjacent or overlapping. + * The code will handle this depending on the situation. + * If the end address of the old lock is higher than the + * new lock, then go ahead and insert the new lock here. + */ + + if (request->l_start > file_lock->fl_lock.l_start) + { + left = file_lock; + } + + if (request->l_end < file_lock->fl_lock.l_end) + { + right = file_lock; + break; + } + + if (request->l_start <= file_lock->fl_lock.l_start) + { + /* In other cases, we are replacing old locks with new + * ones + */ + + if (added) + { + file_lock_delete(file_lock); + continue; + } + + memcpy(&file_lock->fl_lock, request, sizeof(struct flock)); + added = true; + } + } + } + } + + if (!added) + { + if (request->l_type == F_UNLCK) + { + return OK; + } + + /* insert a new lock */ + + new_file_lock = kmm_zalloc(sizeof(struct file_lock_s)); + if (new_file_lock == NULL) + { + return -ENOMEM; + } + + new_file_lock->fl_file = filep; + memcpy(&new_file_lock->fl_lock, request, sizeof(struct flock)); + list_add_before(&file_lock->fl_node, &new_file_lock->fl_node); + file_lock = new_file_lock; + } + + if (right) + { + if (left == right) + { + /* Splitting old locks */ + + new_file_lock = kmm_zalloc(sizeof(struct file_lock_s)); + if (new_file_lock == NULL) + { + return -ENOMEM; + } + + left = new_file_lock; + memcpy(left, right, sizeof(struct file_lock_s)); + list_add_before(&file_lock->fl_node, &left->fl_node); + } + + right->fl_lock.l_start = request->l_end + 1; + } + + if (left) + { + left->fl_lock.l_end = request->l_start - 1; + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: file_getlk + * + * Description: + * Attempts to lock the region (not a real lock), and if there is a + * conflict then returns information about the conflicting locks + * + * Input Parameters: + * filep - File structure instance + * flock - Lock types to be converted + * + * Returned Value: + * The resulting 0 on success. A errno value is returned on any failure. + * + ****************************************************************************/ + +int file_getlk(FAR struct file *filep, FAR struct flock *flock) +{ + FAR struct file_lock_bucket_s *bucket; + FAR struct file_lock_s *file_lock; + char path[PATH_MAX]; + int ret; + + /* We need to get the unique identifier (Path) via filep */ + + ret = file_lock_get_path(filep, path); + if (ret < 0) + { + return ret; + } + + /* Convert a flock to a posix lock */ + + ret = file_lock_normalize(filep, flock, flock); + if (ret < 0) + { + return ret; + } + + nxmutex_lock(&g_protect_lock); + + bucket = file_lock_find_bucket(path); + if (bucket != NULL) + { + list_for_every_entry(&bucket->list, file_lock, struct file_lock_s, + fl_node) + { + if (file_lock_is_conflict(flock, &file_lock->fl_lock)) + { + memcpy(flock, &file_lock->fl_lock, sizeof(*flock)); + goto out; + } + } + } + + flock->l_type = F_UNLCK; + + /* Convert back to flock + * The flock information saved in filelock is used as an offset + * to the relative position. And for upper level applications, + * l_len should be converted to cover the data quantity + */ + +out: + nxmutex_unlock(&g_protect_lock); + if (flock->l_end == OFFSET_MAX) + { + flock->l_len = 0; + } + else + { + flock->l_len = flock->l_end - flock->l_start + 1; + } + + return OK; +} + +/**************************************************************************** + * Name: file_setlk + * + * Description: + * Actual execution of locking and unlocking behaviors + * + * Input Parameters: + * filep - File structure instance + * flock - Lock types to be converted + * nonblock - Waiting for lock + * + * Returned Value: + * The resulting 0 on success. A errno value is returned on any failure. + * + ****************************************************************************/ + +int file_setlk(FAR struct file *filep, FAR struct flock *flock, + bool nonblock) +{ + FAR struct file_lock_bucket_s *bucket; + FAR struct file_lock_s *file_lock; + struct flock request; + char path[PATH_MAX]; + int ret; + + /* We need to get the unique identifier (Path) via filep */ + + ret = file_lock_get_path(filep, path); + if (ret < 0) + { + return ret; + } + + /* Convert a flock to a posix lock */ + + ret = file_lock_normalize(filep, flock, &request); + if (ret < 0) + { + return ret; + } + + request.l_pid = getpid(); + + nxmutex_lock(&g_protect_lock); + + bucket = file_lock_find_bucket(path); + if (bucket == NULL) + { + /* If we request to unlock and the bucket is not found, it means + * there is no lock here. + */ + + if (request.l_type == F_UNLCK) + { + nxmutex_unlock(&g_protect_lock); + return OK; + } + + /* It looks like we didn't find a bucket, let's go create one */ + + bucket = file_lock_create_bucket(path); + if (bucket == NULL) + { + nxmutex_unlock(&g_protect_lock); + return -ENOMEM; + } + } + else if (request.l_type != F_UNLCK) + { +retry: + list_for_every_entry(&bucket->list, file_lock, struct file_lock_s, + fl_node) + { + if (file_lock_is_conflict(&request, &file_lock->fl_lock)) + { + if (nonblock) + { + ret = -EAGAIN; + goto out; + } + + bucket->nwaiter++; + nxmutex_unlock(&g_protect_lock); + nxsem_wait(&bucket->wait); + nxmutex_lock(&g_protect_lock); + bucket->nwaiter--; + goto retry; + } + } + } + + ret = file_lock_modify(filep, bucket, &request); + if (ret < 0) + { + goto out; + } + + /* When there is a lock change, we need to wake up the blocking lock */ + + if (bucket->nwaiter > 0) + { + nxsem_post(&bucket->wait); + } + +out: + file_lock_delete_bucket(bucket, path); + nxmutex_unlock(&g_protect_lock); + return ret; +} + +/**************************************************************************** + * Name: file_closelk + * + * Description: + * Remove all locks associated with the filep when call close is applied. + * + * Input Parameters: + * filep - The filep that corresponds to the shutdown. + * + ****************************************************************************/ + +void file_closelk(FAR struct file *filep) +{ + FAR struct file_lock_bucket_s *bucket; + FAR struct file_lock_s *file_lock; + FAR struct file_lock_s *temp; + char path[PATH_MAX]; + bool deleted = false; + int ret; + + ret = file_lock_get_path(filep, path); + if (ret < 0) + { + /* It isn't an error if fs doesn't support F_GETPATH, so we just end + * it. + */ + + return; + } + + bucket = file_lock_find_bucket(path); + if (bucket == NULL) + { + /* There is no bucket here, so we don't need to free it. */ + + return; + } + + nxmutex_lock(&g_protect_lock); + list_for_every_entry_safe(&bucket->list, file_lock, temp, + struct file_lock_s, fl_node) + { + if (file_lock->fl_file == filep) + { + deleted = true; + file_lock_delete(file_lock); + } + } + + if (bucket->nwaiter > 0 && deleted) + { + nxsem_post(&bucket->wait); + } + else if (deleted) + { + file_lock_delete_bucket(bucket, path); + } + + nxmutex_unlock(&g_protect_lock); +} + +/**************************************************************************** + * Name: file_initlk + * + * Description: + * Initializing file locks + * + ****************************************************************************/ + +void file_initlk(void) +{ + /* Initialize file lock context hash table */ + + hcreate_r(CONFIG_FS_LOCK_BUCKET_SIZE, &g_file_lock_table); +} diff --git a/fs/vfs/fs_lseek.c b/fs/vfs/fs_lseek.c index 18c57e00b551e..3bae28992edae 100644 --- a/fs/vfs/fs_lseek.c +++ b/fs/vfs/fs_lseek.c @@ -84,15 +84,13 @@ off_t file_seek(FAR struct file *filep, off_t offset, int whence) /* FALLTHROUGH */ case SEEK_SET: - if (offset >= 0) - { - filep->f_pos = offset; /* Might be beyond the end-of-file */ - break; - } - else + if (offset < 0) { return -EINVAL; } + + filep->f_pos = offset; /* Might be beyond the end-of-file */ + break; case SEEK_END: diff --git a/fs/vfs/fs_stat.c b/fs/vfs/fs_stat.c index e6acc398580b6..200e629dcf7c1 100644 --- a/fs/vfs/fs_stat.c +++ b/fs/vfs/fs_stat.c @@ -278,12 +278,13 @@ int inode_stat(FAR struct inode *inode, FAR struct stat *buf, int resolve) } else #endif -#if defined(CONFIG_FS_SHM) +#if defined(CONFIG_FS_SHMFS) /* Check for shared memory */ if (INODE_IS_SHM(inode)) { buf->st_mode = S_IFSHM; + buf->st_size = inode->i_size; } else #endif diff --git a/fs/vfs/fs_syncfs.c b/fs/vfs/fs_syncfs.c index 0d4c8e76bda4e..12c328dc10442 100644 --- a/fs/vfs/fs_syncfs.c +++ b/fs/vfs/fs_syncfs.c @@ -36,7 +36,7 @@ * Name: file_syncfs * * Description: - * Equivalent to the standard syncsf() function except that is accepts a + * Equivalent to the standard syncfs() function except that is accepts a * struct file instance instead of a fd descriptor and it does not set * the errno variable * diff --git a/fs/vfs/lock.h b/fs/vfs/lock.h new file mode 100644 index 0000000000000..c1f888d22dd97 --- /dev/null +++ b/fs/vfs/lock.h @@ -0,0 +1,106 @@ +/**************************************************************************** + * fs/vfs/lock.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __FS_VFS_LOCK_H +#define __FS_VFS_LOCK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if CONFIG_FS_LOCK_BUCKET_SIZE == 0 +# define file_initlk() +# define file_closelk(filep) +# define file_getlk(filep, flock) ((void)flock, -ENOSYS) +# define file_setlk(filep, flock, nonblock) ((void)flock, -ENOSYS) +#else + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: file_initlk + * + * Description: + * Initializing file locks + * + ****************************************************************************/ + +void file_initlk(void); + +/**************************************************************************** + * Name: file_closelk + * + * Description: + * Remove all locks associated with the filep when call close is applied. + * + * Input Parameters: + * filep - The filep that corresponds to the shutdown. + * + ****************************************************************************/ + +void file_closelk(FAR struct file *filep); + +/**************************************************************************** + * Name: file_getlk + * + * Description: + * Attempts to lock the region (not a real lock), and if there is a + * conflict then returns information about the conflicting locks + * + * Input Parameters: + * filep - File structure instance + * flock - Lock types to be converted + * + * Returned Value: + * The resulting 0 on success. A errno value is returned on any failure. + * + ****************************************************************************/ + +int file_getlk(FAR struct file *filep, FAR struct flock *flock); + +/**************************************************************************** + * Name: file_setlk + * + * Description: + * Actual execution of locking and unlocking behaviors + * + * Input Parameters: + * filep - File structure instance + * flock - Lock types to be converted + * nonblock - Waiting for lock + * + * Returned Value: + * The resulting 0 on success. A errno value is returned on any failure. + * + ****************************************************************************/ + +int file_setlk(FAR struct file *filep, FAR struct flock *flock, + bool nonblock); + +#endif /* CONFIG_FS_LOCK_BUCKET_SIZE */ +#endif /* __FS_VFS_LOCK_H */ diff --git a/graphics/nxmu/nxmu_start.c b/graphics/nxmu/nxmu_start.c index 5bf224dc4d0af..d174ad7ecc64c 100644 --- a/graphics/nxmu/nxmu_start.c +++ b/graphics/nxmu/nxmu_start.c @@ -41,6 +41,10 @@ #include "nxmu.h" +#ifdef CONFIG_VNCSERVER +# include +#endif + /**************************************************************************** * Private Data ****************************************************************************/ @@ -108,6 +112,22 @@ static int nx_server(int argc, char *argv[]) dev->setpower(dev, ((3 * CONFIG_LCD_MAXPOWER + 3) / 4)); #else /* CONFIG_NX_LCDDRIVER */ +# ifdef CONFIG_VNCSERVER + /* Initialize the VNC server */ + int display; + + /* Get display parameters from the command line */ + + display = atoi(argv[1]); + + ret = vnc_fb_register(display); + if (ret < 0) + { + gerr("ERROR: vnc_fb_register() failed: %d\n", ret); + } + +# else /* CONFIG_VNCSERVER */ + /* Initialize the frame buffer device. */ int display; @@ -132,6 +152,7 @@ static int nx_server(int argc, char *argv[]) return EXIT_FAILURE; } +# endif /* CONFIG_VNCSERVER */ #endif /* CONFIG_NX_LCDDRIVER */ /* Then start the server (nx_run does not normally return) */ diff --git a/include/.gitignore b/include/.gitignore index 39c33176215b2..d8cacb241039c 100644 --- a/include/.gitignore +++ b/include/.gitignore @@ -6,7 +6,9 @@ /features.h /uClibc++ /libcxx +/libcxxabi /machine +/newlib /openamp /metal /etl diff --git a/include/assert.h b/include/assert.h index 45d6e4d323006..f80b657840c42 100644 --- a/include/assert.h +++ b/include/assert.h @@ -113,18 +113,26 @@ /* The C standard states that if NDEBUG is defined, assert will do nothing. * Users can define and undefine NDEBUG as they see fit to choose when assert * does something or does not do anything. + * + * #define assert(ignore) ((void)0) + * + * Reference link: + * https://pubs.opengroup.org/onlinepubs/009695399/basedefs/assert.h.html + * + * ASSERT/VERIFY is a non-standard interface, implemented using internal + * */ #ifdef NDEBUG -# define assert(f) ((void)(1 || (f))) -# define VERIFY(f) assert(f) +# define assert(f) ((void)0) +# define ASSERT(f) ((void)(1 || (f))) +# define VERIFY(f) ((void)(1 || (f))) #else # define assert(f) _ASSERT(f, __ASSERT_FILE__, __ASSERT_LINE__) +# define ASSERT(f) _ASSERT(f, __ASSERT_FILE__, __ASSERT_LINE__) # define VERIFY(f) _VERIFY(f, __ASSERT_FILE__, __ASSERT_LINE__) #endif -#define ASSERT(f) assert(f) - /* Suppress 3rd party library redefine _assert/__assert */ #define _assert _assert diff --git a/include/ctype.h b/include/ctype.h index a24231030cfab..3e560fb551045 100644 --- a/include/ctype.h +++ b/include/ctype.h @@ -33,6 +33,23 @@ #include #include +/**************************************************************************** + * Macro Definitions + ****************************************************************************/ + +/* GNU libstdc++ is expecting ctype.h to define a few macros for + * locale related functions like C++ streams. + */ + +#define _U 01 +#define _L 02 +#define _N 04 +#define _S 010 +#define _P 020 +#define _C 040 +#define _X 0100 +#define _B 0200 + /**************************************************************************** * Inline Functions ****************************************************************************/ diff --git a/include/cxx/cmath b/include/cxx/cmath index c6711b6aba83e..589ff40ff943e 100644 --- a/include/cxx/cmath +++ b/include/cxx/cmath @@ -30,6 +30,12 @@ #include +#undef signbit +#undef fpclassify +#undef isfinite +#undef isinf +#undef isnan + //*************************************************************************** // Namespace //*************************************************************************** @@ -54,6 +60,7 @@ namespace std using ::frexpf; using ::ldexpf; using ::logf; + using ::log1pf; using ::log10f; using ::log2f; using ::modff; @@ -66,6 +73,29 @@ namespace std using ::tanhf; using ::gamma; using ::lgamma; + + constexpr bool + signbit(float __x) + { return __builtin_signbit(__x); } + + constexpr int + fpclassify(float __x) + { return __builtin_fpclassify(FP_NAN, FP_INFINITE, FP_NORMAL, + FP_SUBNORMAL, FP_ZERO, __x); } + + constexpr bool + isfinite(float __x) + { return __builtin_isfinite(__x); } + + constexpr bool + isinf(float __x) + { return __builtin_isinf(__x); } + + constexpr bool + isnan(float __x) + { return __builtin_isnan(__x); } + + #endif #ifdef CONFIG_HAVE_DOUBLE @@ -83,6 +113,7 @@ namespace std using ::frexp; using ::ldexp; using ::log; + using ::log1p; using ::log10; using ::log2; using ::modf; @@ -93,6 +124,28 @@ namespace std using ::sqrt; using ::tan; using ::tanh; + + constexpr bool + signbit(double __x) + { return __builtin_signbit(__x); } + + constexpr int + fpclassify(double __x) + { return __builtin_fpclassify(FP_NAN, FP_INFINITE, FP_NORMAL, + FP_SUBNORMAL, FP_ZERO, __x); } + + constexpr bool + isfinite(double __x) + { return __builtin_isfinite(__x); } + + constexpr bool + isinf(double __x) + { return __builtin_isinf(__x); } + + constexpr bool + isnan(double __x) + { return __builtin_isnan(__x); } + #endif #ifdef CONFIG_HAVE_LONG_DOUBLE @@ -110,6 +163,7 @@ namespace std using ::frexpl; using ::ldexpl; using ::logl; + using ::log1pl; using ::log10l; using ::log2l; using ::modfl; @@ -120,6 +174,28 @@ namespace std using ::sqrtl; using ::tanl; using ::tanhl; + + constexpr bool + signbit(long double __x) + { return __builtin_signbit(__x); } + + constexpr int + fpclassify(long double __x) + { return __builtin_fpclassify(FP_NAN, FP_INFINITE, FP_NORMAL, + FP_SUBNORMAL, FP_ZERO, __x); } + + constexpr bool + isfinite(long double __x) + { return __builtin_isfinite(__x); } + + constexpr bool + isinf(long double __x) + { return __builtin_isinf(__x); } + + constexpr bool + isnan(long double __x) + { return __builtin_isnan(__x); } + #endif } diff --git a/include/cxx/cstdarg b/include/cxx/cstdarg index 8725369f1a4af..d8456d3f0f95d 100644 --- a/include/cxx/cstdarg +++ b/include/cxx/cstdarg @@ -27,8 +27,14 @@ #include + //*************************************************************************** // Namespace //*************************************************************************** +namespace std +{ + using ::va_list; +} + #endif // __INCLUDE_CXX_CSTDARG diff --git a/include/cxx/ctime b/include/cxx/ctime index 3f00c087fd651..ae4f14f2808aa 100644 --- a/include/cxx/ctime +++ b/include/cxx/ctime @@ -45,6 +45,8 @@ namespace std using ::clock_gettime; using ::mktime; using ::gmtime_r; + using ::gmtime; + using ::strftime; using ::timer_create; using ::timer_delete; using ::timer_settime; diff --git a/include/debug.h b/include/debug.h index e6b9163cd7ce2..00ff5682634c1 100644 --- a/include/debug.h +++ b/include/debug.h @@ -920,6 +920,42 @@ # define ipcinfo _none #endif +#ifdef CONFIG_DEBUG_PCI_ERROR +# define pcierr _err +#else +# define pcierr _none +#endif + +#ifdef CONFIG_DEBUG_PCI_WARN +# define pciwarn _warn +#else +# define pciwarn _none +#endif + +#ifdef CONFIG_DEBUG_PCI_INFO +# define pciinfo _info +#else +# define pciinfo _none +#endif + +#ifdef CONFIG_DEBUG_RPMSG_ERROR +# define rpmsgerr _err +#else +# define rpmsgerr _none +#endif + +#ifdef CONFIG_DEBUG_RPMSG_WARN +# define rpmsgwarn _warn +#else +# define rpmsgwarn _none +#endif + +#ifdef CONFIG_DEBUG_RPMSG_INFO +# define rpmsginfo _info +#else +# define rpmsginfo _none +#endif + /* Buffer dumping macros do not depend on varargs */ #ifdef CONFIG_DEBUG_ERROR diff --git a/include/inttypes.h b/include/inttypes.h index 056ad4ea6243d..58b1e6af93d43 100644 --- a/include/inttypes.h +++ b/include/inttypes.h @@ -348,7 +348,13 @@ * function. */ -typedef void *imaxdiv_t; /* Dummy type since imaxdiv is not yet supported */ +struct imaxdiv_s +{ + intmax_t quot; + intmax_t rem; +}; + +typedef struct imaxdiv_s imaxdiv_t; /**************************************************************************** * Public Function Prototypes diff --git a/include/netpacket/netlink.h b/include/netpacket/netlink.h index 2b443ac6a95b8..31daae56a1491 100644 --- a/include/netpacket/netlink.h +++ b/include/netpacket/netlink.h @@ -437,6 +437,160 @@ #define RTM_F_CLONED 0x200 /* This route is cloned */ +/* Attribute definitions for struct nfattr **********************************/ + +/* Macros to handle attribute lists */ + +#define NFNL_NFA_NEST 0x8000 +#define NFA_TYPE(attr) ((attr)->nfa_type & 0x7fff) + +#define NFA_MASK (sizeof(uint32_t) - 1) +#define NFA_ALIGN(n) (((n) + NFA_MASK) & ~NFA_MASK) +#define NFA_OK(nfa, n) \ + ((n) >= (int)sizeof(struct nfattr) && \ + (nfa)->nfa_len >= sizeof(struct nfattr) && \ + (nfa)->nfa_len <= (n)) +#define NFA_NEXT(nfa, attrlen) \ + ((attrlen) -= NFA_ALIGN((nfa)->nfa_len), \ + (FAR struct nfattr *)(((FAR char *)(nfa)) + NFA_ALIGN((nfa)->nfa_len))) +#define NFA_LENGTH(len) ((sizeof(struct nfattr)) + (len)) +#define NFA_SPACE(len) NFA_ALIGN(NFA_LENGTH(len)) +#define NFA_DATA(nfa) ((FAR void *)(((FAR char *)(nfa)) + NFA_LENGTH(0))) +#define NFA_PAYLOAD(nfa) ((int)((nfa)->nfa_len) - NFA_LENGTH(0)) + +/* Definitions for struct nfgenmsg ******************************************/ + +#define NFM_NFA(n) ((FAR struct nfattr *) \ + (((FAR char *)(n)) + \ + NLMSG_ALIGN(sizeof(struct nfgenmsg)))) +#define NFM_PAYLOAD(n) NLMSG_PAYLOAD(n, sizeof(struct nfgenmsg)) + +/* Definitions for NETLINK_NETFILTER ****************************************/ + +#define NFNETLINK_V0 0 + +/* netfilter netlink message types are split in two pieces: + * 8 bit subsystem, 8bit operation. + */ + +#define NFNL_SUBSYS_ID(x) (((x) & 0xff00) >> 8) +#define NFNL_MSG_TYPE(x) ((x) & 0x00ff) + +/* subsystems */ + +#define NFNL_SUBSYS_NONE 0 +#define NFNL_SUBSYS_CTNETLINK 1 +#define NFNL_SUBSYS_CTNETLINK_EXP 2 +#define NFNL_SUBSYS_QUEUE 3 +#define NFNL_SUBSYS_ULOG 4 +#define NFNL_SUBSYS_OSF 5 +#define NFNL_SUBSYS_IPSET 6 +#define NFNL_SUBSYS_ACCT 7 +#define NFNL_SUBSYS_CTNETLINK_TIMEOUT 8 +#define NFNL_SUBSYS_CTHELPER 9 +#define NFNL_SUBSYS_NFTABLES 10 +#define NFNL_SUBSYS_NFT_COMPAT 11 +#define NFNL_SUBSYS_HOOK 12 +#define NFNL_SUBSYS_COUNT 13 + +/* NETLINK_NETFILTER: subsystem CTNL (ip conntrack netlink) message types */ + +#define IPCTNL_MSG_CT_NEW 0 +#define IPCTNL_MSG_CT_GET 1 +#define IPCTNL_MSG_CT_DELETE 2 +#define IPCTNL_MSG_CT_GET_CTRZERO 3 +#define IPCTNL_MSG_CT_GET_STATS_CPU 4 +#define IPCTNL_MSG_CT_GET_STATS 5 +#define IPCTNL_MSG_CT_GET_DYING 6 +#define IPCTNL_MSG_CT_GET_UNCONFIRMED 7 +#define IPCTNL_MSG_MAX 8 + +/* NETLINK_NETFILTER: Conntrack attributes */ + +#define CTA_UNSPEC 0 +#define CTA_TUPLE_ORIG 1 +#define CTA_TUPLE_REPLY 2 +#define CTA_STATUS 3 +#define CTA_PROTOINFO 4 +#define CTA_HELP 5 +#define CTA_NAT_SRC 6 +#define CTA_TIMEOUT 7 +#define CTA_MARK 8 +#define CTA_COUNTERS_ORIG 9 +#define CTA_COUNTERS_REPLY 10 +#define CTA_USE 11 +#define CTA_ID 12 +#define CTA_NAT_DST 13 +#define CTA_TUPLE_MASTER 14 +#define CTA_SEQ_ADJ_ORIG 15 +#define CTA_NAT_SEQ_ADJ_ORIG CTA_SEQ_ADJ_ORIG +#define CTA_SEQ_ADJ_REPLY 16 +#define CTA_NAT_SEQ_ADJ_REPLY CTA_SEQ_ADJ_REPLY +#define CTA_ZONE 18 +#define CTA_SECCTX 19 +#define CTA_TIMESTAMP 20 +#define CTA_MARK_MASK 21 +#define CTA_LABELS 22 +#define CTA_LABELS_MASK 23 +#define CTA_SYNPROXY 24 +#define CTA_FILTER 25 +#define CTA_STATUS_MASK 26 +#define CTA_MAX 26 + +/* NETLINK_NETFILTER: Conntrack tuple attributes */ + +#define CTA_TUPLE_UNSPEC 0 +#define CTA_TUPLE_IP 1 +#define CTA_TUPLE_PROTO 2 +#define CTA_TUPLE_ZONE 3 +#define CTA_TUPLE_MAX 3 + +/* NETLINK_NETFILTER: Conntrack IP attributes */ + +#define CTA_IP_UNSPEC 0 +#define CTA_IP_V4_SRC 1 +#define CTA_IP_V4_DST 2 +#define CTA_IP_V6_SRC 3 +#define CTA_IP_V6_DST 4 +#define CTA_IP_MAX 4 + +/* NETLINK_NETFILTER: Conntrack protocol attributes */ + +#define CTA_PROTO_UNSPEC 0 +#define CTA_PROTO_NUM 1 +#define CTA_PROTO_SRC_PORT 2 +#define CTA_PROTO_DST_PORT 3 +#define CTA_PROTO_ICMP_ID 4 +#define CTA_PROTO_ICMP_TYPE 5 +#define CTA_PROTO_ICMP_CODE 6 +#define CTA_PROTO_ICMPV6_ID 7 +#define CTA_PROTO_ICMPV6_TYPE 8 +#define CTA_PROTO_ICMPV6_CODE 9 +#define CTA_PROTO_MAX 9 + +/* NFnetlink multicast groups (userspace) */ + +#define NF_NETLINK_CONNTRACK_NEW 0x00000001 +#define NF_NETLINK_CONNTRACK_UPDATE 0x00000002 +#define NF_NETLINK_CONNTRACK_DESTROY 0x00000004 +#define NF_NETLINK_CONNTRACK_EXP_NEW 0x00000008 +#define NF_NETLINK_CONNTRACK_EXP_UPDATE 0x00000010 +#define NF_NETLINK_CONNTRACK_EXP_DESTROY 0x00000020 + +/* NFnetlink multicast groups */ + +#define NFNLGRP_NONE 0 +#define NFNLGRP_CONNTRACK_NEW 1 +#define NFNLGRP_CONNTRACK_UPDATE 2 +#define NFNLGRP_CONNTRACK_DESTROY 3 +#define NFNLGRP_CONNTRACK_EXP_NEW 4 +#define NFNLGRP_CONNTRACK_EXP_UPDATE 5 +#define NFNLGRP_CONNTRACK_EXP_DESTROY 6 +#define NFNLGRP_NFTABLES 7 +#define NFNLGRP_ACCT_QUOTA 8 +#define NFNLGRP_NFTRACE 9 +#define NFNLGRP_MAX 9 + /**************************************************************************** * Public Type Definitions ****************************************************************************/ @@ -550,6 +704,36 @@ struct rtmsg uint32_t rtm_flags; }; +/* Structures used in prefix information. */ + +struct prefixmsg +{ + uint8_t prefix_family; + uint8_t prefix_pad1; + uint16_t prefix_pad2; + int32_t prefix_ifindex; + uint8_t prefix_type; + uint8_t prefix_len; + uint8_t prefix_flags; + uint8_t prefix_pad3; +}; + +enum +{ + PREFIX_UNSPEC, + PREFIX_ADDRESS, + PREFIX_CACHEINFO, + __PREFIX_MAX +}; + +#define PREFIX_MAX (__PREFIX_MAX - 1) + +struct prefix_cacheinfo +{ + uint32_t preferred_time; + uint32_t valid_time; +}; + /* <------- NLA_HDRLEN ------> <-- NLA_ALIGN(payload)--> * +---------------------+- - -+- - - - - - - - - -+- - -+ * | Header | Pad | Payload | Pad | @@ -584,6 +768,25 @@ struct nla_bitfield32 uint32_t selector; }; +/* NETLINK_NETFILTER Message Structures *************************************/ + +/* These attributes should be manipulated using only the NFA_* */ + +struct nfattr +{ + uint16_t nfa_len; + uint16_t nfa_type; +}; + +/* General form of address family dependent message. */ + +struct nfgenmsg +{ + uint8_t nfgen_family; /* AF_xxx */ + uint8_t version; /* nfnetlink version */ + uint16_t res_id; /* resource id */ +}; + /**************************************************************************** * Neighbor Discovery userland options */ diff --git a/include/nuttx/addrenv.h b/include/nuttx/addrenv.h index d8f0d7d46298d..686723255ebf0 100644 --- a/include/nuttx/addrenv.h +++ b/include/nuttx/addrenv.h @@ -190,9 +190,7 @@ # define CONFIG_ARCH_SHM_NPAGES 1 # endif -# define ARCH_SHM_MAXPAGES (CONFIG_ARCH_SHM_NPAGES * CONFIG_ARCH_SHM_MAXREGIONS) -# define ARCH_SHM_REGIONSIZE (CONFIG_ARCH_SHM_NPAGES * CONFIG_MM_PGSIZE) -# define ARCH_SHM_SIZE (CONFIG_ARCH_SHM_MAXREGIONS * ARCH_SHM_REGIONSIZE) +# define ARCH_SHM_SIZE (CONFIG_ARCH_SHM_NPAGES * CONFIG_MM_PGSIZE) # define ARCH_SHM_VEND (CONFIG_ARCH_SHM_VBASE + ARCH_SHM_SIZE - 1) # define ARCH_SCRATCH_VBASE ARCH_SHM_VEND diff --git a/include/nuttx/analog/hx711.h b/include/nuttx/analog/hx711.h new file mode 100644 index 0000000000000..b8aa4daa1f140 --- /dev/null +++ b/include/nuttx/analog/hx711.h @@ -0,0 +1,212 @@ +/**************************************************************************** + * include/nuttx/analog/hx711.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define HX711_MAX_AVG_SAMPLES 225 + +/* ioctl requests ***********************************************************/ + +/* Set how many samples to read from hx711 to get a single averaged value. + * Minimum value is 1. To prevent possible integer overflow, maximum value + * is HX711_MAX_AVG_SAMPLES. + */ + +#define HX711_SET_AVERAGE 0 + +/* Set channel to use for next read() operation. Channels 'a' and 'b' + * are available. Specify channel as 'a' character (0x61 hex) + */ + +#define HX711_SET_CHANNEL 1 + +/* Set gain to use for next read() operation. Channel 'b' only supports + * gain of 32, and channel 'a' supports gain 128 and 64 + */ + +#define HX711_SET_GAIN 2 + +/* Set what value coresponds to 1 unit. Takes integer. + * If set to 0 (default) driver will return raw readings from + * hx711 instead of calculated units. + */ + +#define HX711_SET_VAL_PER_UNIT 3 + +/* Depending on tensometer position, value will go higher or lower + * (into negative values) when mass increases. If your sign does + * not match, it can be changed by calling this. + * 1 - no sign change (default) + * -1 - sign will be changed + */ + +#define HX711_SET_SIGN 4 + +/* ioctl get functions */ + +/* Get current average, pass pointer to unsigned int type */ + +#define HX711_GET_AVERAGE 100 + +/* Get current channel, pass pointer to single char */ + +#define HX711_GET_CHANNEL 101 + +/* Get current gain, pass pointer to single unsignedchar */ + +#define HX711_GET_GAIN 102 + +/* Get current value per unit */ + +#define HX711_GET_VAL_PER_UNIT 103 + +/* Tare the scale. Accepts int value with desired precision. + * If HX711_VAL_PER_UNIT was set earlier, you should pass value + * in units, otherwise you need to pass raw value as read from hx711. + * Takes pointer to a float value. + */ + +#define HX711_TARE 200 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* hx711 exposes 2 pins for communication. One is for data reading, and + * second one is clock signal. This is similar to i2c but hx711 uses custom + * protocol that is not compatible with i2c in any way. + * + * Platform code should provide these functions to manipulate these GPIOs + */ + +struct hx711_lower_s +{ + /************************************************************************** + * Name: clock_set + * + * Description: + * Sets underlying GPIO pin according to val. + * + * Input Parameters: + * val - set GPIO pin high (1) or low (0) + * minor - hx711 device being manipulated + * + * Returned Value: + * OK on success, or negated errno on failure + * + **************************************************************************/ + + CODE int (*clock_set)(unsigned char minor, int val); + + /************************************************************************** + * Name: data_read + * + * Description: + * Reads current value of data GPIO pin. + * + * Input Parameters: + * minor - hx711 device being manipulated + * + * Returned Value: + * For success, return 0 when GPIO is low, 1 when GPIO is high + * or negated errno on failure. + * + **************************************************************************/ + + CODE int (*data_read)(unsigned char minor); + + /************************************************************************** + * Name: cleanup + * + * Description: + * This function is called when last instance of minor is closed and + * unlinked from fs so that hx711 minor instance is no longer available. + * Platform should free all resources it allocated to register the + * device. + * + * This function does not have to be set, if there is nothing to clean. + * + * Input Parameters: + * minor - hx711 instance being destroyed + * + **************************************************************************/ + + CODE void (*cleanup)(unsigned char minor); + + /************************************************************************** + * Name: data_irq + * + * Description: + * Setup (or tear down when handler is NULL) interrupt when data line + * goes from HIGH to LOW state (falling edge). + * + * hx711 is slow, on internal oscillator and RATE=0 it takes 100ms to + * sample a single reading. To avoid hogging CPU polling for data to + * go down, driver will install interrupt handler before reading. + * Once interrupt is received, driver will disable the handler. + * + * Input Parameters: + * minor - hx711 device being manipulated + * handler - function interrupt should call + * arg - private data for handler, should be passed to handler + * + * Returned Value: + * On successfull interrupt initialization 0 should be returned, + * when there was failure initializing interrupt -1 shall be returned. + * + **************************************************************************/ + + CODE int (*data_irq)(unsigned char minor, xcpt_t handler, void *arg); +}; + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: hx711_register + * + * Description: + * Register new hx711 device in /dev/hx711_%d. Multiple hx711 can be + * supported by providing different minor number. When driver calls + * platform specific function, minor number is passed back, so platform + * can know which hx711 is manipulated. + * + * Input Parameters: + * minor - unique number identifying hx711 chip. + * lower - provided by platform code to manipulate hx711 with platform + * dependant functions> + * + * Returned Value: + * OK on success, or negated errno on failure + * + ****************************************************************************/ + +int hx711_register(unsigned char minor, FAR struct hx711_lower_s *lower); diff --git a/include/nuttx/arch.h b/include/nuttx/arch.h index 2aee23fc8c7cb..11971e54cdf3a 100644 --- a/include/nuttx/arch.h +++ b/include/nuttx/arch.h @@ -781,6 +781,50 @@ void up_textheap_free(FAR void *p); bool up_textheap_heapmember(FAR void *p); #endif +/**************************************************************************** + * Name: up_textheap_data_address + * + * Description: + * If an instruction bus address is specified, return the corresponding + * data bus address. Otherwise, return the given address as it is. + * + * For some platforms, up_textheap_memalign() might return memory regions + * with separate instruction/data bus mappings. In that case, + * up_textheap_memalign() returns the address of the instruction bus + * mapping. + * The instruction bus mapping might provide only limited data access. + * (For example, only read-only, word-aligned access.) + * You can use up_textheap_data_address() to query the corresponding data + * bus mapping. + * + ****************************************************************************/ + +#if defined(CONFIG_ARCH_USE_TEXT_HEAP) +#if defined(CONFIG_ARCH_HAVE_TEXT_HEAP_SEPARATE_DATA_ADDRESS) +FAR void *up_textheap_data_address(FAR void *p); +#else +#define up_textheap_data_address(p) ((FAR void *)p) +#endif +#endif + +/**************************************************************************** + * Name: up_textheap_data_sync + * + * Description: + * Ensure modifications made on the data bus addresses (the addresses + * returned by up_textheap_data_address) fully visible on the corresponding + * instruction bus addresses. + * + ****************************************************************************/ + +#if defined(CONFIG_ARCH_USE_TEXT_HEAP) +#if defined(CONFIG_ARCH_HAVE_TEXT_HEAP_SEPARATE_DATA_ADDRESS) +void up_textheap_data_sync(void); +#else +#define up_textheap_data_sync() do {} while (0) +#endif +#endif + /**************************************************************************** * Name: up_dataheap_memalign * @@ -1378,7 +1422,7 @@ uintptr_t up_addrenv_page_vaddr(uintptr_t page); * vaddr - The virtual address. * * Returned Value: - * True if it is; false if it's not + * True if it is; false if it's not. * ****************************************************************************/ @@ -1386,6 +1430,25 @@ uintptr_t up_addrenv_page_vaddr(uintptr_t page); bool up_addrenv_user_vaddr(uintptr_t vaddr); #endif +/**************************************************************************** + * Name: up_addrenv_page_wipe + * + * Description: + * Wipe a page of physical memory, first mapping it into kernel virtual + * memory. + * + * Input Parameters: + * page - The page physical address. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_ADDRENV +void up_addrenv_page_wipe(uintptr_t page); +#endif + /**************************************************************************** * Name: up_addrenv_kmap_init * @@ -1640,7 +1703,7 @@ int up_prioritize_irq(int irq, int priority); * ****************************************************************************/ -#ifdef CONFIG_ARCH_HAVE_TRUSTZONE +#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT) void up_secure_irq(int irq, bool secure); #else # define up_secure_irq(i, s) @@ -1666,7 +1729,7 @@ void up_send_smp_call(cpu_set_t cpuset); * ****************************************************************************/ -#ifdef CONFIG_ARCH_HAVE_TRUSTZONE +#if defined(CONFIG_ARCH_TRUSTZONE_SECURE) || defined(CONFIG_ARCH_HIPRI_INTERRUPT) void up_secure_irq_all(bool secure); #else # define up_secure_irq_all(s) @@ -2237,6 +2300,29 @@ int up_cpu_pause(int cpu); bool up_cpu_pausereq(int cpu); #endif +/**************************************************************************** + * Name: up_cpu_paused_save + * + * Description: + * Handle a pause request from another CPU. Normally, this logic is + * executed from interrupt handling logic within the architecture-specific + * However, it is sometimes necessary to perform the pending + * pause operation in other contexts where the interrupt cannot be taken + * in order to avoid deadlocks. + * + * Input Parameters: + * None + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +int up_cpu_paused_save(void); +#endif + /**************************************************************************** * Name: up_cpu_paused * @@ -2268,6 +2354,26 @@ bool up_cpu_pausereq(int cpu); int up_cpu_paused(int cpu); #endif +/**************************************************************************** + * Name: up_cpu_paused_restore + * + * Description: + * Restore the state of the CPU after it was paused via up_cpu_pause(), + * and resume normal tasking. + * + * Input Parameters: + * None + * + * Returned Value: + * On success, OK is returned. Otherwise, a negated errno value indicating + * the nature of the failure is returned. + * + ****************************************************************************/ + +#ifdef CONFIG_SMP +int up_cpu_paused_restore(void); +#endif + /**************************************************************************** * Name: up_cpu_resume * @@ -2438,7 +2544,7 @@ void nxsched_alarm_tick_expiration(clock_t ticks); ****************************************************************************/ #ifdef CONFIG_SCHED_CPULOAD_EXTCLK -void nxsched_process_cpuload_ticks(uint32_t ticks); +void nxsched_process_cpuload_ticks(clock_t ticks); # define nxsched_process_cpuload() nxsched_process_cpuload_ticks(1) #endif @@ -2474,12 +2580,12 @@ void irq_dispatch(int irq, FAR void *context); struct tcb_s; size_t up_check_tcbstack(FAR struct tcb_s *tcb); #if defined(CONFIG_ARCH_INTERRUPTSTACK) && CONFIG_ARCH_INTERRUPTSTACK > 3 -size_t up_check_intstack(void); +size_t up_check_intstack(int cpu); #endif #endif #if defined(CONFIG_ARCH_INTERRUPTSTACK) && CONFIG_ARCH_INTERRUPTSTACK > 3 -uintptr_t up_get_intstackbase(void); +uintptr_t up_get_intstackbase(int cpu); #endif /**************************************************************************** diff --git a/include/nuttx/board.h b/include/nuttx/board.h index 55dcd633c9b03..a937bc437b04a 100644 --- a/include/nuttx/board.h +++ b/include/nuttx/board.h @@ -450,6 +450,23 @@ FAR void *board_composite_connect(int port, int configid); FAR const char *board_usbdev_serialstr(void); #endif +/**************************************************************************** + * Name: board_usbdev_pid,board_usbdev_vid + * + * Description: + * Use board unique pid/vid in the device descriptor. This is for that + * usb can be dynamically configured while the board is running + * + * Returned Value: + * The board unique pid/vid. + * + ****************************************************************************/ + +#if defined(CONFIG_BOARD_USBDEV_PIDVID) +uint16_t board_usbdev_pid(void); +uint16_t board_usbdev_vid(void); +#endif + /**************************************************************************** * Name: board_graphics_setup * diff --git a/include/nuttx/can/sja1000.h b/include/nuttx/can/sja1000.h new file mode 100644 index 0000000000000..f3faf09483767 --- /dev/null +++ b/include/nuttx/can/sja1000.h @@ -0,0 +1,236 @@ +/**************************************************************************** + * include/nuttx/can/sja1000.h + * + * SJA1000 CAN driver based on esp32c3_twai.h + * + * License header retained from original source. + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_CAN_SJA1000_H +#define __INCLUDE_NUTTX_CAN_SJA1000_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* CAN hardware-dependent bit-timing constant + * + * Used for calculating and checking bit-timing parameters + */ + +struct can_bittiming_const_s +{ + char name[16]; /* Name of the CAN controller hardware */ + uint32_t tseg1_min; /* Time segment 1 = prop_seg + phase_seg1 */ + uint32_t tseg1_max; + uint32_t tseg2_min; /* Time segment 2 = phase_seg2 */ + uint32_t tseg2_max; + uint32_t sjw_max; /* Synchronisation jump width */ + uint32_t brp_min; /* Bit-rate prescaler */ + uint32_t brp_max; + uint32_t brp_inc; +}; + +/* Type of the SJA1000 interrupt handling callback */ + +struct sja1000_config_s; /* Forward reference */ +typedef CODE void (*sja1000_handler_t)(FAR struct sja1000_config_s *config, + FAR void *arg); + +/* A reference to a structure of this type must be passed to the SJA1000 + * driver when the driver is instantiated. This structure provides + * information about the configuration of the SJA1000 and provides some + * board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied by + * the driver and is presumed to persist while the driver is active. The + * memory must be writeable because, under certain circumstances, the driver + * may modify the frequency. + */ + +struct sja1000_config_s +{ + /* Device configuration */ + + const struct can_bittiming_const_s *bittiming_const; + uint8_t port; /* SJA1000 device port number */ + uint8_t periph; /* Peripheral ID (optional) */ + uint8_t irq; /* IRQ associated with this SJA1000 */ + uint8_t cpu; /* CPU ID */ + int8_t cpuint; /* CPU interrupt assigned to this SJA1000 */ + uint32_t bitrate; /* Configured bit rate */ + uint32_t samplep; /* Configured sample point */ + uint32_t sjw; /* Synchronization jump width */ + uint32_t clk_freq; /* Peripheral clock frequency */ + bool loopback; /* Enable loopback mode */ + bool triple_sample; /* Enable triple-sampling of CAN BUS */ + + /* Device characterization */ + + /* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the driver from differences in GPIO + * interrupt handling by varying boards and MCUs. + * + * attach - Attach interrupt handler to the interrupt + * detach - Detach interrupt handler from the interrupt + */ + + CODE int (*attach)(FAR struct sja1000_config_s *config, + sja1000_handler_t handler, FAR void *arg); + CODE int (*detach)(FAR struct sja1000_config_s *config); +}; + +/* This structure provides the current state of a CAN peripheral */ + +struct sja1000_dev_s +{ + FAR struct sja1000_config_s *config; /* The constant configuration */ + uint8_t filters; /* STD/EXT filter bit allocator. */ + uint8_t nalloc; /* Number of allocated filters */ + uint32_t base; /* SJA1000 register base address */ + +#ifdef CONFIG_ARCH_HAVE_MULTICPU + spinlock_t lock; /* Device specific lock */ +#endif /* CONFIG_ARCH_HAVE_MULTICPU */ + + /* Register read/write callbacks. These operations all hidden behind + * callbacks to isolate the driver from differences in register read/write + * handling by varying boards and MCUs. + * + * getreg - Read from a register address + * putreg - Write to a register address + */ + + CODE uint32_t (*getreg)(struct sja1000_dev_s *sja_priv, uint32_t reg); + CODE void (*putreg)(struct sja1000_dev_s *sja_priv, uint32_t reg, + uint32_t value); + CODE void (*modifyreg32)(struct sja1000_dev_s *sja_priv, uint32_t reg, + uint32_t clearbits, uint32_t setbits); +}; + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +#ifdef CONFIG_CAN_SJA1000 + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Name: sja1000_getreg + * + * Description: + * Read the value of an SJA1000 register. + * + * Input Parameters: + * priv - sja1000 lower-half driver context + * reg - The SJA1000 register address to read + * + * Returned Value: + * + ****************************************************************************/ + +static inline uint32_t sja1000_getreg(struct sja1000_dev_s *sja_priv, + uint32_t reg) +{ + return sja_priv->getreg(sja_priv, reg); +} + +/**************************************************************************** + * Name: sja1000_putreg + * + * Description: + * Set the value of an SJA1000 register. + * + * Input Parameters: + * priv - sja1000 lower-half driver context + * reg - The SJA1000 register address to write + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void sja1000_putreg(struct sja1000_dev_s *sja_priv, + uint32_t reg, uint32_t value) +{ + sja_priv->putreg(sja_priv, reg, value); +} + +/**************************************************************************** + * Name: sja1000_modifyreg32 + * + * Description: + * Modify the value of an SJA1000 register. + * + * Input Parameters: + * priv - sja1000 lower-half driver context + * reg - The SJA1000 register address to modify + * clearbits - Bitmask of the bits to clear in a register + * setbits - Bitmask of the bits to set in a register + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void sja1000_modifyreg32(struct sja1000_dev_s *sja_priv, + uint32_t reg, uint32_t clearbits, uint32_t setbits) +{ + sja_priv->modifyreg32(sja_priv, reg, clearbits, setbits); +} + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: sja1000_instantiate + * + * Description: + * Initialize the selected SJA1000 CAN Bus Controller + * + * Input Parameters: + * priv - An instance of the "lower half" CAN driver state structure. + * + * Returned Value: + * Valid CAN device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct can_dev_s; + +FAR struct can_dev_s *sja1000_instantiate(FAR struct sja1000_dev_s *priv); + +#endif /* __ASSEMBLY__ */ + +#endif /* CONFIG_CAN_SJA1000 */ + +#endif /* __INCLUDE_NUTTX_CAN_SJA1000_H */ diff --git a/include/nuttx/clock.h b/include/nuttx/clock.h index 76ed107912b5f..e329fc2402159 100644 --- a/include/nuttx/clock.h +++ b/include/nuttx/clock.h @@ -277,8 +277,8 @@ #ifndef CONFIG_SCHED_CPULOAD_NONE struct cpuload_s { - volatile uint32_t total; /* Total number of clock ticks */ - volatile uint32_t active; /* Number of ticks while this thread was active */ + volatile clock_t total; /* Total number of clock ticks */ + volatile clock_t active; /* Number of ticks while this thread was active */ }; #endif diff --git a/include/nuttx/compiler.h b/include/nuttx/compiler.h index 222f37c12c8c5..c995c4b219cd9 100644 --- a/include/nuttx/compiler.h +++ b/include/nuttx/compiler.h @@ -207,8 +207,8 @@ /* Branch prediction */ -# define predict_true(x) __builtin_expect(!!(x), 1) -# define predict_false(x) __builtin_expect((x), 0) +# define predict_true(x) __builtin_expect(!!(x), 1) +# define predict_false(x) __builtin_expect(!!(x), 0) /* Code locate */ @@ -245,6 +245,7 @@ */ # define always_inline_function __attribute__((always_inline,no_instrument_function)) +# define inline_function __attribute__((always_inline)) inline # define noinline_function __attribute__((noinline)) /* The noinstrument_function attribute informs GCC don't instrument it */ @@ -302,6 +303,7 @@ # define malloc_like1(a) __attribute__((__malloc__(__builtin_free, 1))) __attribute__((__alloc_size__(a))) # define malloc_like2(a, b) __attribute__((__malloc__(__builtin_free, 1))) __attribute__((__alloc_size__(a, b))) # define realloc_like(a) __attribute__((__alloc_size__(a))) +# define realloc_like2(a, b) __attribute__((__alloc_size__(a, b))) # else # define fopen_like __attribute__((__malloc__)) # define popen_like __attribute__((__malloc__)) @@ -309,6 +311,7 @@ # define malloc_like1(a) __attribute__((__malloc__)) __attribute__((__alloc_size__(a))) # define malloc_like2(a, b) __attribute__((__malloc__)) __attribute__((__alloc_size__(a, b))) # define realloc_like(a) __attribute__((__alloc_size__(a))) +# define realloc_like2(a, b) __attribute__((__alloc_size__(a, b))) # endif /* Some versions of GCC have a separate __syslog__ format. @@ -557,6 +560,7 @@ /* SDCC does not support forced inlining. */ # define always_inline_function +# define inline_function inline # define noinline_function # define noinstrument_function # define nooptimiziation_function @@ -701,6 +705,7 @@ # define end_packed_struct # define naked_function # define always_inline_function +# define inline_function inline # define noinline_function # define noinstrument_function # define nooptimiziation_function @@ -813,6 +818,7 @@ # define reentrant_function # define naked_function # define always_inline_function +# define inline_function inline # define noinline_function # define noinstrument_function # define nooptimiziation_function @@ -904,6 +910,7 @@ # define reentrant_function # define naked_function # define always_inline_function +# define inline_function __forceinline # define noinline_function # define noinstrument_function # define nooptimiziation_function @@ -944,6 +951,85 @@ # define no_builtin(n) +/* TASKING (Infineon AURIX C/C++)-specific definitions **********************/ + +#elif defined(__TASKING__) + +/* Define these here and allow specific architectures to override as needed */ + +# define CONFIG_HAVE_LONG_LONG 1 +# define CONFIG_HAVE_FLOAT 1 +# define CONFIG_HAVE_DOUBLE 1 +# define CONFIG_HAVE_LONG_DOUBLE 1 + +/* Pre-processor */ + +# define CONFIG_CPP_HAVE_VARARGS 1 /* Supports variable argument macros */ + +/* Intriniscs */ + +# define CONFIG_HAVE_FUNCTIONNAME 1 /* Has __FUNCTION__ */ +# define CONFIG_HAVE_FILENAME 1 /* Has __FILE__ */ + +# undef CONFIG_CPP_HAVE_WARNING +# undef CONFIG_HAVE_WEAKFUNCTIONS +# define weak_alias(name, aliasname) +# define weak_data __attribute__((weak)) +# define weak_function __attribute__((weak)) +# define weak_const_function __attribute__((weak, __const__)) +# define restrict +# define noreturn_function +# define farcall_function __attribute__((long_call)) +# define predict_true(x) (x) +# define predict_false(x) (x) +# define aligned_data(n) __attribute__((aligned(n))) +# define locate_code(n) __attribute__((section(n))) +# define locate_data(n) __attribute__((section(n))) +# define begin_packed_struct +# define end_packed_struct __attribute__((packed)) +# define reentrant_function +# define naked_function +# define always_inline_function __attribute__((always_inline)) +# define noinline_function __attribute__((noinline)) +# define noinstrument_function +# define nooptimiziation_function __attribute__((optimize(0))) +# define nosanitize_address +# define nosanitize_undefined +# define nostackprotect_function +# define unused_code __attribute__((unused)) +# define unused_data __attribute__((unused)) +# define used_code __attribute__((used)) +# define used_data __attribute__((used)) +# define fopen_like +# define popen_like +# define malloc_like +# define malloc_like1(a) +# define malloc_like2(a, b) +# define realloc_like(a) +# define format_like(a) +# define printf_like(a, b) +# define syslog_like(a, b) +# define scanf_like(a, b) +# define strftime_like(a) + +# define FAR +# define NEAR +# define DSEG +# define CODE +# define IOBJ +# define IPTR + +# undef CONFIG_SMALL_MEMORY +# undef CONFIG_LONG_IS_NOT_INT +# undef CONFIG_PTR_IS_NOT_INT + +# define UNUSED(a) ((void)(1 || &(a))) + +# define offsetof(a, b) ((size_t)(&(((a *)(0))->b))) +# define return_address(x) 0 + +# define no_builtin(n) + /* Unknown compiler *********************************************************/ #else @@ -970,6 +1056,7 @@ # define reentrant_function # define naked_function # define always_inline_function +# define inline_function # define noinline_function # define noinstrument_function # define nooptimiziation_function diff --git a/include/nuttx/eeprom/spi_xx25xx.h b/include/nuttx/eeprom/spi_xx25xx.h index 5a1f760829390..29fcc98cbf790 100644 --- a/include/nuttx/eeprom/spi_xx25xx.h +++ b/include/nuttx/eeprom/spi_xx25xx.h @@ -25,7 +25,9 @@ * Public Types ****************************************************************************/ -/* DO NOT CHANGE ORDER, IT MATCHES CODE IN drivers/eeprom/spieeprom.c */ +/* DO NOT CHANGE ORDER, IT MATCHES CODE IN drivers/eeprom/spieeprom.c and + * drivers/mtd/at25ee.c + */ enum eeprom_25xx_e { diff --git a/include/nuttx/fdcheck.h b/include/nuttx/fdcheck.h index abf7e4baccfeb..af55f87ed1c5c 100644 --- a/include/nuttx/fdcheck.h +++ b/include/nuttx/fdcheck.h @@ -46,47 +46,47 @@ extern "C" * * Description: Obtain original fd information * - * Val carries the pid and fd information. - * The original fd information is stored in low bit of val. - * The pid information is stored in the high bit of val. + * Val carries the tag and fd information. + * The original fd information is stored in high bit of val. + * The tag information is stored in the low bit of val. * For ease of understanding, let's give an example where * the following information is represented in 32-bit binary format * - * val 00000000 00000000 01010101 10001010 + * val 00000000 00000000 10001010 00000001 * fd 00000000 00000000 00000000 10001010 - * pid 00000000 00000000 00000000 01010101 + * tag 00000000 00000000 00000000 00000001 * - * In this function, we also check if the pid information is correct. + * In this function, we also check tag information is correct. * If there is an error, it will panic. * * Input Parameters: - * val - this val carrying pid and original fd information + * val - this val carrying tag and original fd information * - * Returned Value: none + * Returned Value: The original fd is returned. * ****************************************************************************/ -int fdcheck_restore(int fd); +int fdcheck_restore(int val); /**************************************************************************** * Name: fdcheck_protect * - * Description: Obtain the combined value of fd and pid + * Description: Obtain the combined value of fd and tag * - * the return value carries the pid and fd information. + * the return value carries the tag and fd information. * The original fd information is stored in low bit of val. - * The pid information is stored in high bit of val. + * The tag information is stored in high bit of val. * For ease of understanding, let's give an example where * the following information is represented in 32-bit binary format * * fd 00000000 00000000 00000000 10001010 - * pid 00000000 00000000 00000000 01010101 - * val 00000000 00000000 01010101 10001010 + * tag 00000000 00000000 00000000 00000001 + * val 00000000 00000000 10001010 00000001 * * Input Parameters: * fd - original fd * - * Returned Value: the combined value of fd and pid + * Returned Value: the combined value of fd and tag * ****************************************************************************/ diff --git a/include/nuttx/fdt.h b/include/nuttx/fdt.h index 4e432a1394106..004a810cece9b 100644 --- a/include/nuttx/fdt.h +++ b/include/nuttx/fdt.h @@ -28,6 +28,7 @@ #include #include +#include #include /**************************************************************************** @@ -65,6 +66,9 @@ struct fdt_header_s * Store the pointer to the flattened device tree and verify that it at * least appears to be valid. This function will not fully parse the FDT. * + * Input Parameters: + * fdt_base - The pointer to the raw FDT. + * * Return: * Return -EINVAL if the fdt header does not have the expected magic value. * otherwise return OK. If OK is not returned the existing entry for FDT @@ -81,8 +85,269 @@ int fdt_register(FAR const char *fdt_base); * Return the pointer to a raw FDT. NULL is returned if no FDT has been * loaded. * + * Input Parameters: + * None + * + * Return: + * The pointer to the raw FDT. + * ****************************************************************************/ FAR const char *fdt_get(void); +/**************************************************************************** + * Name: fdt_get_irq + * + * Description: + * Get the interrupt number of the node + * + * Input Parameters: + * fdt - The pointer to the raw FDT. + * nodeoffset - The offset of the node + * offset - The offset of the property + * irqbase - The base of the interrupt number + * + * Return: + * The interrupt number of the node + * + ****************************************************************************/ + +int fdt_get_irq(FAR const void *fdt, int nodeoffset, + int offset, int irqbase); + +/**************************************************************************** + * Name: fdt_get_irq_by_path + * + * Description: + * Get the interrupt number of the node + * + * Input Parameters: + * fdt - The pointer to the raw FDT. + * offset - The offset of the node + * path - The path of the node + * irqbase - The base of the interrupt number + * + * Return: + * The interrupt number of the node + * + ****************************************************************************/ + +int fdt_get_irq_by_path(FAR const void *fdt, int offset, + const char *path, int irqbase); + +/**************************************************************************** + * Name: fdt_get_parent_address_cells + * + * Description: + * Get the parent address of the register space + * + * Input Parameters: + * fdt - The pointer to the raw FDT. + * offset - The offset of the node + * + * Return: + * The parent address of the register space + * + ****************************************************************************/ + +int fdt_get_parent_address_cells(FAR const void *fdt, int offset); + +/**************************************************************************** + * Name: fdt_get_parent_size_cells + * + * Description: + * Get the parent size of the register space + * + * Input Parameters: + * fdt - The pointer to the raw FDT. + * offset - The offset of the node + * + * Return: + * The parent size of the register space + * + ****************************************************************************/ + +int fdt_get_parent_size_cells(FAR const void *fdt, int offset); + +/**************************************************************************** + * Name: fdt_ld_by_cells + * + * Description: + * Load a 32-bit or 64-bit value from a buffer, depending on the number + * of address cells. + * + * Input Parameters: + * value - The pointer to the buffer + * cells - The number of address cells + * + * Return: + * The 32-bit or 64-bit value + * + ****************************************************************************/ + +uintptr_t fdt_ld_by_cells(FAR const void *value, int cells); + +/**************************************************************************** + * Name: fdt_get_reg_base_by_name + * + * Description: + * Get the value of the "reg" property by its offset in the "reg-names" + * property + * + * Input Parameters: + * fdt - The pointer to the raw FDT. + * offset - The offset to the node. + * reg_name - The name of the register + * + * Returned Value: + * The register address determined by its name. Returns 0 if: + * - The reg-names property doesn't exist. + * - The reg property doesn't exits. + * - The reg-names property doesn't contain the "reg_name". + * - The offset combined with the size is larger than the width of the + * "reg" field + * + ****************************************************************************/ + +uintptr_t fdt_get_reg_base_by_name(FAR const void *fdt, int offset, + const char *reg_name); + +/**************************************************************************** + * Name: fdt_get_reg_base + * + * Description: + * Get the base address of the register space + * + * Input Parameters: + * fdt - The pointer to the raw FDT. + * offset - The offset of the node + * index - The index of the register in the reg field. + * + * Return: + * The base address of the register space + * + ****************************************************************************/ + +uintptr_t fdt_get_reg_base(FAR const void *fdt, int offset, int index); + +/**************************************************************************** + * Name: fdt_get_reg_size + * + * Description: + * Get the size of the register space + * + * Input Parameters: + * fdt - The pointer to the raw FDT. + * offset - The offset of the node + * + * Return: + * The size of the register space + * + ****************************************************************************/ + +uintptr_t fdt_get_reg_size(FAR const void *fdt, int offset); + +/**************************************************************************** + * Name: fdt_get_reg_base_by_path + * + * Description: + * Get the base address of the register space + * + * Input Parameters: + * fdt - The pointer to the raw FDT. + * path - The path of the node + * + * Return: + * The base address of the register space + * + ****************************************************************************/ + +uintptr_t fdt_get_reg_base_by_path(FAR const void *fdt, + FAR const char *path); + +/**************************************************************************** + * Name: fdt_device_is_available + * + * Description: + * Test if node contains the "status" property with field set to okay or + * ok. + * + * Input Parameters: + * fdt - The pointer to the raw FDT. + * offset - The offset to the node to query. + * + * Returned Value: + * true: The node contains the status propertry, and is set to okay or + * ok. + * false: The node contains the status propertry, but it is set to + * something other than ok or okay. + * Always returns true if the node doesn't contain a status property. + * + ****************************************************************************/ + +bool fdt_device_is_available(FAR const void * fdt, int offset); + +/**************************************************************************** + * Name: fdt_get_node_label + * + * Description: + * Get the label for a given node. The device tree must be compiled with + * the -@ option in order for the symbol table to be generated. + * + * Input Parameters: + * fdt - The pointer to the raw FDT. + * offset - The offset to the node to query. + * + * Returned Value: + * Node label if found. NULL is returned if no label if found for the given + * node. + * + ****************************************************************************/ + +const char *fdt_get_node_label(FAR const void *fdt, int offset); + +/**************************************************************************** + * Name: fdt_get_clock_frequency + * + * Description: + * Get the value of the "clock-frequency" value for the given node. + * + * Input Parameters: + * fdt - The pointer to the raw FDT. + * offset - The offset to the node to query. + * + * Returned Value: + * The value of the clock-frequency property of the node. Zero is + * returned if the node doesn't contain a clock-frequency property. + * + ****************************************************************************/ + +uintptr_t fdt_get_clock_frequency(FAR const void *fdt, int offset); + +/**************************************************************************** + * Name: fdt_get_clock_frequency_from_clocks + * + * Description: + * Get the "clock-frequency" property for the given node, using the phandle + * specified in the "clocks" property + * + * Input Parameters: + * fdt - The pointer to the raw FDT. + * node - The offset to the node to query. + * offset - The offset of the phandle in the clocks property + * + * Returned Value: + * The value of the clock-frequency property of the node, following the + * specified phandle in the "clocks"' property. Returns 0 if: + * - The node doesn't have a "clocks" property + * - The offset given is larger than the length of the "clocks" property + * - The phandle specified by the "clocks" property doesn't contain a + * "clock-frequency" property. + * + ****************************************************************************/ + +uintptr_t fdt_get_clock_frequency_from_clocks(FAR const void *fdt, + int offset, + int index); + #endif /* __INCLUDE_NUTTX_FDT_H */ diff --git a/include/nuttx/fs/fs.h b/include/nuttx/fs/fs.h index f17a04f5eb0d3..067686dc60000 100644 --- a/include/nuttx/fs/fs.h +++ b/include/nuttx/fs/fs.h @@ -40,6 +40,7 @@ #include #include #include +#include /**************************************************************************** * Pre-processor Definitions @@ -412,7 +413,7 @@ struct inode uint16_t i_flags; /* Flags for inode */ union inode_ops_u u; /* Inode operations */ ino_t i_ino; /* Inode serial number */ -#ifdef CONFIG_PSEUDOFS_FILE +#if defined(CONFIG_PSEUDOFS_FILE) || defined(CONFIG_FS_SHMFS) size_t i_size; /* The size of per inode driver */ #endif #ifdef CONFIG_PSEUDOFS_ATTRIBUTES @@ -468,7 +469,11 @@ struct file FAR struct inode *f_inode; /* Driver or file system interface */ FAR void *f_priv; /* Per file driver private data */ #ifdef CONFIG_FDSAN - uint64_t f_tag; /* file owner tag, init to 0 */ + uint64_t f_tag_fdsan; /* File owner fdsan tag, init to 0 */ +#endif + +#ifdef CONFIG_FDCHECK + uint8_t f_tag_fdcheck; /* File owner fdcheck tag, init to 0 */ #endif }; @@ -484,6 +489,15 @@ struct filelist spinlock_t fl_lock; /* Manage access to the file list */ uint8_t fl_rows; /* The number of rows of fl_files array */ FAR struct file **fl_files; /* The pointer of two layer file descriptors array */ + + /* Pre-allocated files to avoid allocator access during thread creation + * phase, For functional safety requirements, increase + * CONFIG_NFILE_DESCRIPTORS_PER_BLOCK could also avoid allocator access + * caused by the file descriptor exceeding the limit. + */ + + FAR struct file *fl_prefile; + FAR struct file fl_prefiles[CONFIG_NFILE_DESCRIPTORS_PER_BLOCK]; }; /* The following structure defines the list of files used for standard C I/O. @@ -525,7 +539,7 @@ struct filelist #ifdef CONFIG_FILE_STREAM struct file_struct { - FAR struct file_struct *fs_next; /* Pointer to next file stream */ + sq_entry_t fs_entry; /* Entry of file stream */ rmutex_t fs_lock; /* Recursive lock */ cookie_io_functions_t fs_iofunc; /* Callbacks to user / system functions */ FAR void *fs_cookie; /* Pointer to file descriptor / cookie struct */ @@ -550,8 +564,7 @@ struct streamlist { mutex_t sl_lock; /* For thread safety */ struct file_struct sl_std[3]; - FAR struct file_struct *sl_head; - FAR struct file_struct *sl_tail; + sq_queue_t sl_queue; }; #endif /* CONFIG_FILE_STREAM */ @@ -1128,6 +1141,25 @@ int fs_getfilep(int fd, FAR struct file **filep); int file_close(FAR struct file *filep); +/**************************************************************************** + * Name: file_close_without_clear + * + * Description: + * Close a file that was previously opened with file_open(), but without + * clear filep. + * + * Input Parameters: + * filep - A pointer to a user provided memory location containing the + * open file data returned by file_open(). + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int file_close_without_clear(FAR struct file *filep); + /**************************************************************************** * Name: nx_close_from_tcb * diff --git a/include/nuttx/fs/hostfs.h b/include/nuttx/fs/hostfs.h index 24f41c9e7368a..9d7d045bcfe88 100644 --- a/include/nuttx/fs/hostfs.h +++ b/include/nuttx/fs/hostfs.h @@ -135,7 +135,7 @@ typedef int nuttx_fsid_t[2]; /* These must match the definition in include/time.h */ # ifdef CONFIG_SYSTEM_TIME64 -typedef int64_t nuttx_time_t; +typedef uint64_t nuttx_time_t; # else typedef uint32_t nuttx_time_t; # endif diff --git a/include/nuttx/fs/ioctl.h b/include/nuttx/fs/ioctl.h index b4aaca0b2674d..e2aed084819d6 100644 --- a/include/nuttx/fs/ioctl.h +++ b/include/nuttx/fs/ioctl.h @@ -81,7 +81,7 @@ #define _FBIOCBASE (0x2800) /* Frame buffer character driver ioctl commands */ #define _NXTERMBASE (0x2900) /* NxTerm character driver ioctl commands */ #define _RFIOCBASE (0x2a00) /* RF devices ioctl commands */ -#define _RPTUNBASE (0x2b00) /* Remote processor tunnel ioctl commands */ +#define _RPMSGBASE (0x2b00) /* Remote processor message ioctl commands */ #define _NOTECTLBASE (0x2c00) /* Note filter control ioctl commands*/ #define _NOTERAMBASE (0x2d00) /* Noteram device ioctl commands*/ #define _RCIOCBASE (0x2e00) /* Remote Control device ioctl commands */ @@ -99,6 +99,7 @@ #define _SEIOCBASE (0x3a00) /* Secure element ioctl commands */ #define _SYSLOGBASE (0x3c00) /* Syslog device ioctl commands */ #define _STEPIOBASE (0x3d00) /* Stepper device ioctl commands */ +#define _FPGACFGBASE (0x3e00) /* FPGA configuration ioctl commands */ #define _WLIOCBASE (0x8b00) /* Wireless modules ioctl network commands */ /* boardctl() commands share the same number space */ @@ -189,17 +190,29 @@ */ #ifdef CONFIG_FDSAN -#define FIOC_SETTAG _FIOC(0x000e) /* IN: FAR uint64_t * +#define FIOC_SETTAG_FDSAN _FIOC(0x000e) /* IN: FAR uint64_t * * Pointer to file tag * OUT: None */ -#define FIOC_GETTAG _FIOC(0x000f) /* IN: FAR uint64_t * +#define FIOC_GETTAG_FDSAN _FIOC(0x000f) /* IN: FAR uint64_t * * Pointer to file tag * OUT: None */ #endif +#ifdef CONFIG_FDCHECK +#define FIOC_SETTAG_FDCHECK _FIOC(0x0010) /* IN: FAR uint8_t * + * Pointer to file fdcheck tag + * OUT: None + */ + +#define FIOC_GETTAG_FDCHECK _FIOC(0x0011) /* IN: FAR uint8_t * + * Pointer to file fdcheck tag + * OUT: None + */ +#endif + /* NuttX file system ioctl definitions **************************************/ #define _DIOCVALID(c) (_IOC_TYPE(c)==_DIOCBASE) @@ -578,10 +591,10 @@ #define _RFIOCVALID(c) (_IOC_TYPE(c)==_RFIOCBASE) #define _RFIOC(nr) _IOC(_RFIOCBASE,nr) -/* Rptun drivers ************************************************************/ +/* Rpmsg drivers ************************************************************/ -#define _RPTUNIOCVALID(c) (_IOC_TYPE(c)==_RPTUNBASE) -#define _RPTUNIOC(nr) _IOC(_RPTUNBASE,nr) +#define _RPMSGIOCVALID(c) (_IOC_TYPE(c)==_RPMSGBASE) +#define _RPMSGIOC(nr) _IOC(_RPMSGBASE,nr) /* Notectl drivers **********************************************************/ @@ -682,6 +695,11 @@ #define _BOARDIOCVALID(c) (_IOC_TYPE(c)==_BOARDBASE) #define _BOARDIOC(nr) _IOC(_BOARDBASE,nr) +/* FPAG configuration ioctl definitions *************************************/ + +#define _FPGACFGVALID(c) (_IOC_TYPE(c) == _FPGACFGBASE) +#define _FPGACFGIOC(nr) _IOC(_FPGACFGBASE, nr) + /**************************************************************************** * Public Type Definitions ****************************************************************************/ diff --git a/include/nuttx/init.h b/include/nuttx/init.h index af3dce335f6ee..ec461492b147e 100644 --- a/include/nuttx/init.h +++ b/include/nuttx/init.h @@ -38,11 +38,14 @@ * initialization. */ -#define OSINIT_MM_READY() (g_nx_initstate >= OSINIT_MEMORY) -#define OSINIT_HW_READY() (g_nx_initstate >= OSINIT_HARDWARE) -#define OSINIT_OS_READY() (g_nx_initstate >= OSINIT_OSREADY) -#define OSINIT_IDLELOOP() (g_nx_initstate >= OSINIT_IDLELOOP) -#define OSINIT_OS_INITIALIZING() (g_nx_initstate < OSINIT_OSREADY) +#define nxsched_set_initstate(s) g_nx_initstate = (s) +#define nxsched_get_initstate() g_nx_initstate + +#define OSINIT_MM_READY() (nxsched_get_initstate() >= OSINIT_MEMORY) +#define OSINIT_HW_READY() (nxsched_get_initstate() >= OSINIT_HARDWARE) +#define OSINIT_OS_READY() (nxsched_get_initstate() >= OSINIT_OSREADY) +#define OSINIT_IDLELOOP() (nxsched_get_initstate() >= OSINIT_IDLELOOP) +#define OSINIT_OS_INITIALIZING() (nxsched_get_initstate() < OSINIT_OSREADY) /**************************************************************************** * Public Types diff --git a/include/nuttx/ioexpander/icjx.h b/include/nuttx/ioexpander/icjx.h new file mode 100644 index 0000000000000..aa133a4495d0d --- /dev/null +++ b/include/nuttx/ioexpander/icjx.h @@ -0,0 +1,110 @@ +/**************************************************************************** + * include/nuttx/ioexpander/icjx.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_IOEXPANDER_ICJX_H +#define __INCLUDE_NUTTX_IOEXPANDER_ICJX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ICJX_CTRL_WORD_CURR_SRC_DIS 0 /* Pin current source disabled */ +#define ICJX_CTRL_WORD_PULLDOWN_200U 1 /* 200 uA pull down */ +#define ICJX_CTRL_WORD_PULLDOWN_600U 2 /* 600 uA pull down */ +#define ICJX_CTRL_WORD_PULLDOWN_2M 3 /* 2 mA pull down */ +#define ICJX_CTRL_WORD_PULLUP_200U 5 /* 200 uA pull up */ +#define ICJX_CTRL_WORD_PULLUP_600U 6 /* 600 uA pull up */ +#define ICJX_CTRL_WORD_PULLUP_2M 7 /* 2 mA pull up*/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* A reference to a structure of this type must be passed to the iC-JX + * driver when the driver is instantiated. This structure provides + * information about the configuration of the iC-JX and provides some + * board-specific hooks. + * + * Memory for this structure is provided by the caller. It is not copied by + * the driver and is presumed to persist while the driver is active. The + * memory must be writeable because, under certain circumstances, the driver + * may modify the frequency. + */ + +struct icjx_config_s +{ + /* Device characterization */ + + uint8_t id; /* Device ID (if more expanders are used) */ + uint8_t verification; /* True if data verification on MISO line is used */ + uint8_t current_src; /* Current sources for pin nibbles (pull up, + * pull down) - see Control Word 2 register + */ + uint8_t addr; /* Device address (set by A(1:0) pins) */ + uint8_t mode; /* SPI mode */ + uint32_t frequency; /* SPI frequency */ + +#ifdef CONFIG_IOEXPANDER_INT_ENABLE + /* IRQ/GPIO access callbacks. These operations all hidden behind + * callbacks to isolate the iC-JX driver from differences in GPIO + * interrupt handling by varying boards and MCUs. + * + * attach - Attach the iC-JX interrupt handler to the GPIO interrupt + * enable - Enable or disable the GPIO interrupt + */ + + CODE int (*attach)(FAR struct icjx_config_s *config, xcpt_t handler, + FAR void *arg); + CODE void (*enable)(FAR struct icjx_config_s *config, bool enable); +#endif +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: icjx_initialize + * + * Description: + * Instantiate and configure the iC-JX device driver to use the + * provided SPI device instance. + * + * Input Parameters: + * spi - A SPI driver instance + * config - Persistent board configuration data + * + * Returned Value: + * an ioexpander_dev_s instance on success, NULL on failure. + * + ****************************************************************************/ + +struct spi_dev_s; +FAR struct ioexpander_dev_s *icjx_initialize(FAR struct spi_dev_s *spi, + FAR struct icjx_config_s *config); + +#endif /* __INCLUDE_NUTTX_IOEXPANDER_ICJX_H */ diff --git a/include/nuttx/lcd/ft80x.h b/include/nuttx/lcd/ft80x.h index 0ed5f08e9c17c..0a0c532a6047b 100644 --- a/include/nuttx/lcd/ft80x.h +++ b/include/nuttx/lcd/ft80x.h @@ -295,7 +295,7 @@ #define FT80X_REG_PLAYBACK_PLAY 0x1024bc /* Start audio playback */ #define FT80X_REG_PWM_HZ 0x1024c0 /* BACKLIGHT PWM output frequency (Hz) */ #define FT80X_REG_PWM_DUTY 0x1024c4 /* BACKLIGHT PWM output duty cycle 0=0%, - * 128=100% */ + * 128=100% */ #define FT80X_REG_MACRO_0 0x1024c8 /* Display list macro command 0 */ #define FT80X_REG_MACRO_1 0x1024cc /* Display list macro command 1 */ @@ -317,7 +317,7 @@ #if defined(CONFIG_LCD_FT800) #define FT80X_REG_TOUCH_ADC_MODE 0x1024f4 /* Select single ended (low power) or - * differential (accurate) sampling */ + * differential (accurate) sampling */ #define FT80X_REG_TOUCH_CHARGE 0x1024f8 /* Touch-screen charge time, units of 6 clocks */ #define FT80X_REG_TOUCH_SETTLE 0x1024fc /* Touch-screen settle time, units of 6 clocks */ #define FT80X_REG_TOUCH_OVERSAMPLE 0x102500 /* Touch-screen oversample factor */ @@ -326,7 +326,7 @@ #define FT80X_REG_TOUCH_RZ 0x10250c /* Touch-screen resistance */ #define FT80X_REG_TOUCH_SCREEN_XY 0x102510 /* Touch-screen screen (x-MSB16; y-LSB16) */ #define FT80X_REG_TOUCH_TAG_XY 0x102514 /* Touch-screen screen (x-MSB16; y-LSB16) - * used for tag lookup */ + * used for tag lookup */ #define FT80X_REG_TOUCH_TAG 0x102518 /* Touch-screen tag result */ #define FT80X_REG_TOUCH_TRANSFORM_A 0x10251c /* Touch-screen transform coefficient (s15.16) */ #define FT80X_REG_TOUCH_TRANSFORM_B 0x102520 /* Touch-screen transform coefficient (s15.16) */ @@ -349,16 +349,16 @@ * Bits [15:8]: configure register value */ /* 0x1024fc - 0x102504 Reserved */ #define FT80X_REG_CTOUCH_RAW_XY 0x102508 /* Compatibility mode: touch-screen raw - * (x-MSB16; y-LSB16) */ + * (x-MSB16; y-LSB16) */ #define FT80X_REG_CTOUCH_TOUCH1_XY 0x102508 /* Extended mode: touch-screen screen data for touch 1 - * (x-MSB16; y-LSB16) */ + * (x-MSB16; y-LSB16) */ #define FT80X_REG_CTOUCH_TOUCH4_Y 0x10250c /* Extended mode: touch-screen screen Y data for touch 4 */ #define FT80X_REG_CTOUCH_SCREEN_XY 0x102510 /* Compatibility mode: touch-screen screen - * (x-MSB16; y-LSB16) */ + * (x-MSB16; y-LSB16) */ #define FT80X_REG_CTOUCH_TOUCH0_XY 0x102510 /* Extended mode: touch-screen screen data for touch 0 - * (x-MSB16; y-LSB16) */ + * (x-MSB16; y-LSB16) */ #define FT80X_REG_CTOUCH_TAG_XY 0x102514 /* Touch-screen screen (x-MSB16; y-LSB16) - * used for tag lookup */ + * used for tag lookup */ #define FT80X_REG_CTOUCH_TAG 0x102518 /* Touch-screen tag result */ #define FT80X_REG_CTOUCH_TRANSFORM_A 0x10251c /* Touch-screen transform coefficient (s15.16) */ #define FT80X_REG_CTOUCH_TRANSFORM_B 0x102520 /* Touch-screen transform coefficient (s15.16) */ @@ -589,14 +589,14 @@ /* FT80X_REG_TOUCH_MODE */ #define TOUCH_MODE_OFF 0 /* Acquisition stopped, touch detection - * interrupt is still valid. */ + * interrupt is still valid. */ #define TOUCH_MODE_ONESHOT 1 /* Perform acquisition once every write of 1 * to REG_TOUCH_MODE. */ #define TOUCH_MODE_FRAMESYNC 2 /* Perform acquisition for every frame sync * (~60 data acquisition/second). */ #define TOUCH_MODE_CONTINUOUS 3 /* Perform acquisition continuously at - * approximately 1000 data acquisition / - * second. */ + * approximately 1000 data acquisition / + * second. */ /* Interrupts ***************************************************************/ diff --git a/include/nuttx/list.h b/include/nuttx/list.h index 328178b27382e..cadbccc335f50 100644 --- a/include/nuttx/list.h +++ b/include/nuttx/list.h @@ -44,8 +44,6 @@ * Included Files ****************************************************************************/ -#include - #include #include @@ -53,12 +51,28 @@ * Pre-processor Definitions ****************************************************************************/ +/* Name: list_container_of + * + * Description: + * Cast a member of a structure out to get the address of the containing + * structure + * + * Arguments: + * ptr - The pointer to the member. + * type - The type of the container struct this is embedded in. + * member - The name of the member within the struct. + */ + +#define list_container_of(ptr, type, member) \ + ((type *)((uintptr_t)(ptr) - offsetof(type, member))) + #define LIST_INITIAL_VALUE(list) { &(list), &(list) } #define LIST_INITIAL_CLEARED_VALUE { NULL, NULL } -#define list_in_list(item) ((item)->prev != NULL) -#define list_is_empty(list) ((list)->next == list) -#define list_is_clear(list) ((list)->next == NULL) +#define list_in_list(item) ((item)->prev != NULL) +#define list_is_empty(list) ((list)->next == list) +#define list_is_clear(list) ((list)->next == NULL) +#define list_is_singular(list) ((list)->next == (list)->prev) #define list_initialize(list) \ do \ @@ -89,11 +103,11 @@ ((item)->next != (list) ? (item)->next : \ (item)->next->next != (list) ? (item)->next->next : NULL) -#define list_entry(ptr, type, member) container_of(ptr, type, member) -#define list_first_entry(list, type, member) container_of((list)->next, type, member) -#define list_last_entry(list, type, member) container_of((list)->prev, type, member) -#define list_next_entry(list, type, member) container_of((list)->member.next, type, member) -#define list_prev_entry(list, type, member) container_of((list)->member.prev, type, member) +#define list_entry(ptr, type, member) list_container_of(ptr, type, member) +#define list_first_entry(list, type, member) list_container_of((list)->next, type, member) +#define list_last_entry(list, type, member) list_container_of((list)->prev, type, member) +#define list_next_entry(list, type, member) list_container_of((list)->member.next, type, member) +#define list_prev_entry(list, type, member) list_container_of((list)->member.prev, type, member) #define list_add_after(entry, new_entry) list_add_head(entry, new_entry) #define list_add_head(list, item) \ @@ -145,7 +159,7 @@ FAR type *__t = NULL; \ if(__node) \ { \ - __t = container_of(__node, type, member); \ + __t = list_container_of(__node, type, member); \ } \ __t; \ }) @@ -156,7 +170,7 @@ FAR type *__t = NULL; \ if(__node) \ { \ - __t = container_of(__node, type, member); \ + __t = list_container_of(__node, type, member); \ } \ __t; \ }) @@ -167,7 +181,7 @@ FAR type *__t = NULL; \ if(__node) \ { \ - __t = container_of(__node, type, member); \ + __t = list_container_of(__node, type, member); \ } \ __t; \ }) @@ -178,7 +192,7 @@ FAR type *__t = NULL; \ if(__node) \ { \ - __t = container_of(__node, type, member); \ + __t = list_container_of(__node, type, member); \ } \ __t; \ }) @@ -189,7 +203,7 @@ FAR type *__t = NULL; \ if(__node) \ { \ - __t = container_of(__node, type, member); \ + __t = list_container_of(__node, type, member); \ } \ __t; \ }) @@ -200,7 +214,7 @@ FAR type *__t = NULL; \ if(__node) \ { \ - __t = container_of(__node, type, member); \ + __t = list_container_of(__node, type, member); \ } \ __t; \ }) @@ -211,7 +225,7 @@ FAR type *__t = NULL; \ if(__node) \ { \ - __t = container_of(__node, type, member); \ + __t = list_container_of(__node, type, member); \ } \ __t; \ }) @@ -222,7 +236,7 @@ FAR type *__t = NULL; \ if(__node) \ { \ - __t = container_of(__node, type, member); \ + __t = list_container_of(__node, type, member); \ } \ __t; \ }) @@ -243,19 +257,26 @@ /* iterates over the list, entry should be the container structure type */ #define list_for_every_entry(list, entry, type, member) \ - for(entry = container_of((list)->next, type, member); \ + for(entry = list_container_of((list)->next, type, member); \ &entry->member != (list); \ - entry = container_of(entry->member.next, type, member)) + entry = list_container_of(entry->member.next, type, member)) /* iterates over the list in a safe way for deletion of current node * entry and temp_entry should be the container structure type * */ #define list_for_every_entry_safe(list, entry, temp, type, member) \ - for(entry = container_of((list)->next, type, member), \ - temp = container_of(entry->member.next, type, member); \ + for(entry = list_container_of((list)->next, type, member), \ + temp = list_container_of(entry->member.next, type, member); \ &entry->member != (list); entry = temp, \ - temp = container_of(temp->member.next, type, member)) + temp = list_container_of(temp->member.next, type, member)) + +/* Iterate from a given entry node in a safe way */ + +#define list_for_every_entry_safe_from(list, cur, temp, type, member) \ + for ((temp) = list_next_entry(cur, type, member); \ + &(cur)->member != (list); \ + (cur) = (temp), (temp) = list_next_entry(temp, type, member)) #define list_for_every_entry_continue(list, head, type, member) \ for ((list) = list_next_entry(list, type, member); \ @@ -267,9 +288,9 @@ */ #define list_for_every_entry_reverse(list, entry, type, member) \ - for(entry = container_of((list)->prev, type, member); \ + for(entry = list_container_of((list)->prev, type, member); \ &entry->member != (list); \ - entry = container_of(entry->member.prev, type, member)) + entry = list_container_of(entry->member.prev, type, member)) /**************************************************************************** * Public Type Definitions diff --git a/include/nuttx/mm/iob.h b/include/nuttx/mm/iob.h index 704d9d7bc206e..a69be9803e8ca 100644 --- a/include/nuttx/mm/iob.h +++ b/include/nuttx/mm/iob.h @@ -88,10 +88,18 @@ # define IOB_QEMPTY(q) ((q)->qh_head == NULL) #endif +#ifdef CONFIG_IOB_ALLOC +# define IOB_BUFSIZE(p) ((p)->io_bufsize) +#else +# define IOB_BUFSIZE(p) CONFIG_IOB_BUFSIZE +#endif + /**************************************************************************** * Public Types ****************************************************************************/ +typedef CODE void (*iob_free_cb_t)(FAR void *data); + /* Represents one I/O buffer. A packet is contained by one or more I/O * buffers in a chain. The io_pktlen is only valid for the I/O buffer at * the head of the chain. @@ -105,16 +113,24 @@ struct iob_s /* Payload */ -#if CONFIG_IOB_BUFSIZE < 256 +#if CONFIG_IOB_BUFSIZE < 256 && !defined(CONFIG_IOB_ALLOC) uint8_t io_len; /* Length of the data in the entry */ uint8_t io_offset; /* Data begins at this offset */ #else uint16_t io_len; /* Length of the data in the entry */ uint16_t io_offset; /* Data begins at this offset */ +# ifdef CONFIG_IOB_ALLOC + uint16_t io_bufsize; /* Total length of the data buffer */ +# endif #endif unsigned int io_pktlen; /* Total length of the packet */ - uint8_t io_data[CONFIG_IOB_BUFSIZE]; +#ifdef CONFIG_IOB_ALLOC + iob_free_cb_t io_free; /* Custom free callback */ + FAR uint8_t *io_data; +#else + uint8_t io_data[CONFIG_IOB_BUFSIZE]; +#endif }; #if CONFIG_IOB_NCHAINS > 0 @@ -203,6 +219,53 @@ FAR struct iob_s *iob_alloc(bool throttled); FAR struct iob_s *iob_tryalloc(bool throttled); +#ifdef CONFIG_IOB_ALLOC +/**************************************************************************** + * Name: iob_alloc_dynamic + * + * Description: + * Allocate an I/O buffer and playload from heap + * + * Input Parameters: + * size - The size of the io_data that is allocated. + * + * +---------+ + * | IOB | + * | io_data |--+ + * | buffer |<-+ + * +---------+ + * + ****************************************************************************/ + +FAR struct iob_s *iob_alloc_dynamic(uint16_t size); + +/**************************************************************************** + * Name: iob_alloc_with_data + * + * Description: + * Allocate an I/O buffer from heap and attach the external payload + * + * Input Parameters: + * data - Make io_data point to a specific address, the caller is + * responsible for the memory management. The caller should + * ensure that the memory is not freed before the iob is freed. + * + * +---------+ +-->+--------+ + * | IOB | | | data | + * | io_data |--+ +--------+ + * +---------+ + * + * size - The size of the data parameter + * free_cb - Notify the caller when the iob is freed. The caller can + * perform additional operations on the data before it is freed. + * The free_cb is called when the iob is freed. + * + ****************************************************************************/ + +FAR struct iob_s *iob_alloc_with_data(FAR void *data, uint16_t size, + iob_free_cb_t free_cb); +#endif + /**************************************************************************** * Name: iob_navail * diff --git a/include/nuttx/mm/kmap.h b/include/nuttx/mm/kmap.h index baa5630dca1e4..5fac2929567c6 100644 --- a/include/nuttx/mm/kmap.h +++ b/include/nuttx/mm/kmap.h @@ -38,7 +38,7 @@ void kmm_map_initialize(void); /**************************************************************************** - * Name: kmm_map_pages + * Name: kmm_map * * Description: * Map pages into kernel virtual memory. diff --git a/include/nuttx/mm/map.h b/include/nuttx/mm/map.h index 53c45c26b107d..7405ebce0db00 100644 --- a/include/nuttx/mm/map.h +++ b/include/nuttx/mm/map.h @@ -44,7 +44,7 @@ struct task_group_s; struct mm_map_entry_s { - FAR struct mm_map_entry *flink; /* this is used as sq_entry_t */ + FAR struct mm_map_entry_s *flink; /* this is used as sq_entry_t */ FAR void *vaddr; size_t length; off_t offset; @@ -56,11 +56,11 @@ struct mm_map_entry_s int i; } priv; - /* Drivers which register mappings may also - * implement the unmap function to undo anything done in mmap. - * Nb. Implementation must NOT use "this_task()->group" since - * this is not valid during process exit. The argument "group" will be - * NULL in this case. + /* Drivers which register mappings may also implement the unmap function + * to undo anything done in mmap. + * Nb. Implementation must NOT use "this_task()->group" since it is not + * valid during process exit. The argument "group" will be NULL in this + * case. */ int (*munmap)(FAR struct task_group_s *group, @@ -69,16 +69,15 @@ struct mm_map_entry_s size_t length); }; -/* A structure for the task group */ +/* memory mapping structure for the task group */ struct mm_map_s { - sq_queue_t mm_map_sq; - - size_t map_count; + sq_queue_t mm_map_sq; /* mappings list */ + size_t map_count; /* mappings list length */ #ifdef CONFIG_ARCH_VMA_MAPPING - GRAN_HANDLE mm_map_vpages; + GRAN_HANDLE mm_map_vpages; /* SHM virtual zone allocator */ #endif rmutex_t mm_map_mutex; @@ -125,7 +124,7 @@ void mm_map_unlock(void); * Name: mm_map_initialize * * Description: - * Initialization function, called only by group_initialize + * Initialization function, called only by group_postinitialize * * Input Parameters: * mm - Pointer to the mm_map structure to be initialized @@ -194,6 +193,48 @@ void vm_release_region(FAR struct mm_map_s *mm, FAR void *vaddr, #endif +#ifdef CONFIG_ARCH_VMA_MAPPING + +/**************************************************************************** + * Name: vm_map_region + * + * Description: + * Allocate virtual memory and maps given physical memory into user space + * of the current process. The mapped region can be larger than requested + * if given paddr isn't page-aligned, use with care so that not to create + * unwanted security holes. The returned virtual address has same in-page + * alignment as given paddr. + * + * Input Parameters: + * paddr - Starting physical address + * size - Size of the address range + * + * Returned Value: + * Virtual address if success, or NULL if error + * + ****************************************************************************/ + +FAR void *vm_map_region(uintptr_t paddr, size_t size); + +/**************************************************************************** + * Name: vm_unmap_region + * + * Description: + * Unmap previously mapped userspace device and release the virtual memory. + * + * Input Parameters: + * vaddr - Starting virtual address of the mapped device + * size - Size of the address range + * + * Returned Value: + * OK for success or negative value for error + * + ****************************************************************************/ + +int vm_unmap_region(FAR void *vaddr, size_t size); + +#endif /* CONFIG_ARCH_VMA_MAPPING */ + /**************************************************************************** * Name: mm_map_add * diff --git a/include/nuttx/mm/mempool.h b/include/nuttx/mm/mempool.h index 4a7c48ddc7bb0..a46eaa091c586 100644 --- a/include/nuttx/mm/mempool.h +++ b/include/nuttx/mm/mempool.h @@ -38,10 +38,10 @@ * Pre-processor Definitions ****************************************************************************/ -#if CONFIG_MM_DFAULT_ALIGNMENT == 0 +#if CONFIG_MM_DEFAULT_ALIGNMENT == 0 # define MEMPOOL_ALIGN (2 * sizeof(uintptr_t)) #else -# define MEMPOOL_ALIGN CONFIG_MM_DFAULT_ALIGNMENT +# define MEMPOOL_ALIGN CONFIG_MM_DEFAULT_ALIGNMENT #endif #if CONFIG_MM_BACKTRACE >= 0 diff --git a/include/nuttx/mm/mm.h b/include/nuttx/mm/mm.h index 265f92c986778..3e440947908d1 100644 --- a/include/nuttx/mm/mm.h +++ b/include/nuttx/mm/mm.h @@ -139,6 +139,10 @@ #define MM_DUMP_LEAK(dump, pid) \ ((dump) == PID_MM_LEAK && (pid) >= 0 && nxsched_get_tcb(pid) == NULL) +#define MM_INIT_MAGIC 0xcc +#define MM_ALLOC_MAGIC 0xaa +#define MM_FREE_MAGIC 0x55 + /**************************************************************************** * Public Types ****************************************************************************/ diff --git a/include/nuttx/modem/alt1250.h b/include/nuttx/modem/alt1250.h index 3c1e3cf528588..4d924fe554bd0 100644 --- a/include/nuttx/modem/alt1250.h +++ b/include/nuttx/modem/alt1250.h @@ -58,10 +58,11 @@ #define ALT1250_IOC_SETEVTBUFF _MODEMIOC(3) #define ALT1250_IOC_EXCHGCONTAINER _MODEMIOC(4) -#define ALT1250_EVTBIT_RESET (1ULL << 63) -#define ALT1250_EVTBIT_REPLY (1ULL << 62) -#define ALT1250_EVTBIT_STOPAPI (1ULL << 61) -#define ALT1250_EVTBIT_SUSPEND (1ULL << 60) +#define ALT1250_EVTBIT_RESET (1ULL << 63) +#define ALT1250_EVTBIT_REPLY (1ULL << 62) +#define ALT1250_EVTBIT_STOPAPI (1ULL << 61) +#define ALT1250_EVTBIT_SUSPEND (1ULL << 60) +#define ALT1250_EVTBIT_RESTARTAPI (1ULL << 59) /* Number of sockets */ diff --git a/include/nuttx/mqueue.h b/include/nuttx/mqueue.h index 1c4731d2a77e0..1e7121284c571 100644 --- a/include/nuttx/mqueue.h +++ b/include/nuttx/mqueue.h @@ -78,6 +78,10 @@ # define _MQ_TIMEDRECEIVE(d,m,l,p,t) mq_timedreceive(d,m,l,p,t) #endif +#ifndef CONFIG_FS_MQUEUE_NPOLLWAITERS +# define CONFIG_FS_MQUEUE_NPOLLWAITERS 0 +#endif + #if CONFIG_FS_MQUEUE_NPOLLWAITERS > 0 # define nxmq_pollnotify(msgq, eventset) \ poll_notify(msgq->fds, CONFIG_FS_MQUEUE_NPOLLWAITERS, eventset) @@ -584,6 +588,52 @@ int file_mq_timedsend(FAR struct file *mq, FAR const char *msg, size_t msglen, unsigned int prio, FAR const struct timespec *abstime); +/**************************************************************************** + * Name: file_mq_ticksend + * + * Description: + * This function adds the specified message (msg) to the message queue + * (mq). file_mq_ticksend() behaves just like mq_send(), except that if + * the queue is full and the O_NONBLOCK flag is not enabled for the + * message queue description, then abstime points to a structure which + * specifies a ceiling on the time for which the call will block. + * + * file_mq_ticksend() is functionally equivalent to mq_timedsend() except + * that: + * + * - It is not a cancellation point, and + * - It does not modify the errno value. + * + * See comments with mq_timedsend() for a more complete description of the + * behavior of this function + * + * Input Parameters: + * mq - Message queue descriptor + * msg - Message to send + * msglen - The length of the message in bytes + * prio - The priority of the message + * ticks - Ticks to wait from the start time until the semaphore is + * posted. + * + * Returned Value: + * This is an internal OS interface and should not be used by applications. + * It follows the NuttX internal error return policy: Zero (OK) is + * returned on success. A negated errno value is returned on failure. + * (see mq_timedsend() for the list list valid return values). + * + * EAGAIN The queue was empty, and the O_NONBLOCK flag was set for the + * message queue description referred to by mq. + * EINVAL Either msg or mq is NULL or the value of prio is invalid. + * EBADF Message queue opened not opened for writing. + * EMSGSIZE 'msglen' was greater than the maxmsgsize attribute of the + * message queue. + * EINTR The call was interrupted by a signal handler. + * + ****************************************************************************/ + +int file_mq_ticksend(FAR struct file *mq, FAR const char *msg, + size_t msglen, unsigned int prio, sclock_t ticks); + /**************************************************************************** * Name: file_mq_receive * @@ -652,6 +702,44 @@ ssize_t file_mq_timedreceive(FAR struct file *mq, FAR char *msg, size_t msglen, FAR unsigned int *prio, FAR const struct timespec *abstime); +/**************************************************************************** + * Name: file_mq_tickreceive + * + * Description: + * This function receives the oldest of the highest priority messages from + * the message queue specified by "mq." If the message queue is empty + * and O_NONBLOCK was not set, file_mq_tickreceive() will block until a + * message is added to the message queue (or until a timeout occurs). + * + * file_mq_tickreceive() is an internal OS interface. It is functionally + * equivalent to mq_timedreceive() except that: + * + * - It is not a cancellation point, and + * - It does not modify the errno value. + * + * See comments with mq_timedreceive() for a more complete description of + * the behavior of this function + * + * Input Parameters: + * mq - Message Queue Descriptor + * msg - Buffer to receive the message + * msglen - Size of the buffer in bytes + * prio - If not NULL, the location to store message priority. + * ticks - Ticks to wait from the start time until the semaphore is + * posted. + * + * Returned Value: + * This is an internal OS interface and should not be used by applications. + * It follows the NuttX internal error return policy: Zero (OK) is + * returned on success. A negated errno value is returned on failure. + * (see mq_timedreceive() for the list list valid return values). + * + ****************************************************************************/ + +ssize_t file_mq_tickreceive(FAR struct file *mq, FAR char *msg, + size_t msglen, FAR unsigned int *prio, + sclock_t ticks); + /**************************************************************************** * Name: file_mq_setattr * diff --git a/include/nuttx/mtd/mtd.h b/include/nuttx/mtd/mtd.h index 1a1c4923d904a..e6356e0b0e3f7 100644 --- a/include/nuttx/mtd/mtd.h +++ b/include/nuttx/mtd/mtd.h @@ -397,6 +397,28 @@ FAR struct mtd_dev_s *at24c_initialize(FAR struct i2c_master_s *dev, FAR struct mtd_dev_s *at24c_initialize(FAR struct i2c_master_s *dev); #endif +/**************************************************************************** + * Name: at25xx_initialize + * + * Description: + * Create an initialized MTD device instance for an AT25 SPI EEPROM + * MTD devices are not registered in the file system, but are created + * as instances that can be bound to other functions + * (such as a block or character driver front end). + * + * Input Parameters: + * dev - a reference to the spi device structure + * devtype - device type, from include/nuttx/eeprom/spi_xx25xx.h + * readonly - sets block driver to be readonly + * + * Returned Value: + * Initialised device structure (success) of NULL (fail) + * + ****************************************************************************/ + +FAR struct mtd_dev_s *at25ee_initialize(FAR struct spi_dev_s *dev, + int devtype, int readonly); + /**************************************************************************** * Name: at24c_uninitialize * diff --git a/include/nuttx/mtd/nand.h b/include/nuttx/mtd/nand.h index 08ad677dc9e8a..4be864ee1e1c4 100644 --- a/include/nuttx/mtd/nand.h +++ b/include/nuttx/mtd/nand.h @@ -98,7 +98,7 @@ extern "C" * * Returned Value: * A non-NULL MTD driver instance is returned on success. NULL is - * returned on any failaure. + * returned on any failure. * ****************************************************************************/ diff --git a/include/nuttx/mtd/nand_ram.h b/include/nuttx/mtd/nand_ram.h new file mode 100644 index 0000000000000..5229882e42b83 --- /dev/null +++ b/include/nuttx/mtd/nand_ram.h @@ -0,0 +1,101 @@ +/**************************************************************************** + * include/nuttx/mtd/nand_ram.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ +#ifndef __INCLUDE_NUTTX_MTD_NAND_RAM_H +#define __INCLUDE_NUTTX_MTD_NAND_RAM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define NAND_RAM_DEBUG CONFIG_MTD_NAND_RAM_DEBUG + +#define NAND_RAM_B(x) (x) +#define NAND_RAM_KB(x) (NAND_RAM_B(x) << 10) +#define NAND_RAM_MB(x) (NAND_RAM_KB(x) << 10) + +#define NAND_RAM_SIZE NAND_RAM_MB(CONFIG_MTD_NAND_RAM_SIZE) + +#define NAND_RAM_LOG_PAGES_PER_BLOCK ((uint32_t) 7) +#define NAND_RAM_PAGE_SIZE ((uint32_t) (1 << 9)) /* 512 B */ +#define NAND_RAM_SPARE_SIZE ((uint32_t) (1 << 4)) /* 16 B */ +#define NAND_RAM_N_PAGES ((uint32_t) NAND_RAM_SIZE / NAND_RAM_PAGE_SIZE) +#define NAND_RAM_TOTAL_PAGE_SIZE ((uint32_t) (NAND_RAM_PAGE_SIZE + NAND_RAM_SPARE_SIZE)) +#define NAND_RAM_PAGES_PER_BLOCK ((uint32_t) (NAND_RAM_BLOCK_SIZE / NAND_RAM_PAGE_SIZE)) +#define NAND_RAM_N_BLOCKS ((uint32_t) (NAND_RAM_N_PAGES / NAND_RAM_PAGES_PER_BLOCK)) +#define NAND_RAM_BLOCK_SIZE ((uint32_t) ((1 << NAND_RAM_LOG_PAGES_PER_BLOCK) * NAND_RAM_PAGE_SIZE)) + +#define NAND_RAM_PAGE_WRITTEN 0 +#define NAND_RAM_PAGE_FREE 1 + +#define NAND_RAM_BLOCK_GOOD 0xff + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +EXTERN FAR struct mtd_dev_s *g_nand_ram_mtd_wrapper; +EXTERN FAR struct mtd_dev_s *g_nand_ram_mtd_under; +EXTERN FAR struct nand_raw_s *g_nand_mtd_raw; + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +int nand_ram_eraseblock(FAR struct nand_raw_s *raw, off_t block); +int nand_ram_rawread(FAR struct nand_raw_s *raw, off_t block, + unsigned int page, FAR void *data, FAR void *spare); +int nand_ram_rawwrite(FAR struct nand_raw_s *raw, off_t block, + unsigned int page, FAR const void *data, + FAR const void *spare); +FAR struct mtd_dev_s *nand_ram_initialize(struct nand_raw_s *raw); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __TESTING_NAND_RAM_NAND_RAM_H */ \ No newline at end of file diff --git a/include/nuttx/mtd/nand_wrapper.h b/include/nuttx/mtd/nand_wrapper.h new file mode 100644 index 0000000000000..28304d107beb8 --- /dev/null +++ b/include/nuttx/mtd/nand_wrapper.h @@ -0,0 +1,84 @@ +/**************************************************************************** + * include/nuttx/mtd/nand_wrapper.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ +#ifndef __INCLUDE_NUTTX_MTD_NAND_WRAPPER_H +#define __INCLUDE_NUTTX_MTD_NAND_WRAPPER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct nand_wrapper_dev_s +{ + struct nand_dev_s wrapper; /* Wrapper device */ + struct nand_dev_s under; /* Underlying actuall upper half device */ +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +int nand_wrapper_erase(FAR struct mtd_dev_s *dev, off_t startblock, + size_t nblocks); +ssize_t nand_wrapper_bread(FAR struct mtd_dev_s *dev, off_t startpage, + size_t npages, FAR uint8_t *buffer); +ssize_t nand_wrapper_bwrite(FAR struct mtd_dev_s *dev, off_t startpage, + size_t npages, FAR const uint8_t *buffer); +int nand_wrapper_ioctl(FAR struct mtd_dev_s *dev, int cmd, + unsigned long arg); +int nand_wrapper_isbad(FAR struct mtd_dev_s *dev, off_t block); +int nand_wrapper_markbad(FAR struct mtd_dev_s *dev, off_t block); +void nand_wrapper_initialize(void); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __TESTING_NAND_RAM_NAND_RAM_H */ \ No newline at end of file diff --git a/include/nuttx/net/gmii.h b/include/nuttx/net/gmii.h index e4ab94edad527..ed8511461e7e3 100644 --- a/include/nuttx/net/gmii.h +++ b/include/nuttx/net/gmii.h @@ -80,6 +80,21 @@ #define GMII_KSZ90X1_RRDPSR 261 /* RGMII RX data pad skew */ #define GMII_KSZ90x1_ATR 263 /* Analog test register */ +/* Realtek RTL8211 PHY Extended Registers */ + +#define GMII_RTL8211F_NAME "RTL8211F" +#define GMII_RTL8211F_INER_A42 18 /* Interrupt Enable Register */ +#define GMII_RTL8211F_PHYCR1_A43 24 /* PHY Specific Control Register 1 */ +#define GMII_RTL8211F_PHYCR2_A43 25 /* PHY Specific Control Register 2 */ +#define GMII_RTL8211F_PHYSR_A43 26 /* PHY Specific Status Register */ +#define GMII_RTL8211F_INSR_A43 29 /* Interrupt Status Register */ +#define GMII_RTL8211F_PAGSR 31 /* Page Select Register */ +#define GMII_RTL8211F_PHYSCR_A46 20 /* PHY Special Cofig Register */ +#define GMII_RTL8211F_LCR_D04 16 /* LED Control Register */ +#define GMII_RTL8211F_EEELCR_D04 17 /* EEE LED Control Register */ +#define GMII_RTL8211F_MIICR_D08 21 /* MII Control Register */ +#define GMII_RTL8211F_INTBCR_D40 22 /* INTB Pin Control Register */ + /* MII register bit settings ************************************************/ /* MII Control register bit definitions */ @@ -280,6 +295,18 @@ #define GMII_KSZ90x1_INT_RF (1 << 1) /* Remote fault interrupt */ #define GMII_KSZ90x1_INT_LU (1 << 0) /* Link up interrupt */ +/* RTL8211 register bit settings ********************************************/ + +/* RTL8211F MII ID1/2 register bits */ + +#define GMII_PHYID1_RTL8211F 0x001c /* ID1 value for Realtek RTL8211F */ +#define GMII_PHYID2_RTL8211F 0xc878 /* ID2 value for Realtek RTL8211F */ +#define GMII_RTL8211F_PHYSR_SPEED_MASK 0x30 +#define GMII_RTL8211F_PHYSR_10MBPS 0x00 +#define GMII_RTL8211F_PHYSR_100MBPS 0x10 +#define GMII_RTL8211F_PHYSR_1000MBPS 0x20 +#define GMII_RTL8211F_PHYSR_DUPLEX 0x8 + /**************************************************************************** * Type Definitions ****************************************************************************/ diff --git a/include/nuttx/net/ip.h b/include/nuttx/net/ip.h index ec97434a2108a..6e6db2c0daab8 100644 --- a/include/nuttx/net/ip.h +++ b/include/nuttx/net/ip.h @@ -58,6 +58,7 @@ #include #include +#include /**************************************************************************** * Pre-processor Definitions @@ -245,6 +246,41 @@ struct ipv6_stats_s #endif /* CONFIG_NET_IPv6 */ #endif /* CONFIG_NET_STATISTICS */ +#ifdef CONFIG_NET_ARP_ACD +#define ARP_ACD_TMR_INTERVAL 100 /* milliseconds */ +#define ARP_ACD_TICKS_PER_SECOND (1000 / ARP_ACD_TMR_INTERVAL) + +/* RFC 5227 Constants */ + +#define ANNOUNCE_NUM 2 /* (number of announcement packets) */ +#define ANNOUNCE_INTERVAL 2 /* seconds (time between announcement packets) */ +#define ANNOUNCE_WAIT 2 /* seconds (delay before announcing) */ +#define DEFEND_INTERVAL 10 /* seconds (min. wait between defensive ARPs) */ + +/* arp acd entry states */ + +enum arp_acd_state_e +{ + ARP_ACD_STATE_INIT = 0, + ARP_ACD_STATE_ANNOUNCING = 1, + ARP_ACD_STATE_FINISH = 2 +}; + +#define ARP_ACD_ADDRESS_NO_CONFLICT 0 +#define ARP_ACD_ADDRESS_CONFLICT 1 + +struct arp_acd_s +{ + enum arp_acd_state_e state; /* current arp_acd_s status */ + int sendnum; /* sent number of probes or announces, dependent on state */ + bool conflict_flag; /* arp address conflict flag */ + bool need_announce; /* need to send arp announce packet */ + uint32_t ttw; /* ticks to wait */ + clock_t lastconflict; /* last conflict timestamp */ + struct work_s work; /* For deferred timeout operations */ +}; +#endif /* CONFIG_NET_ARP_ACD */ + /**************************************************************************** * Public Data ****************************************************************************/ diff --git a/include/nuttx/net/mii.h b/include/nuttx/net/mii.h index 623610cc26bd1..b9eeefc15ac85 100644 --- a/include/nuttx/net/mii.h +++ b/include/nuttx/net/mii.h @@ -21,11 +21,14 @@ #ifndef __INCLUDE_NUTTX_NET_MII_H #define __INCLUDE_NUTTX_NET_MII_H +#ifndef __ASSEMBLY__ + /**************************************************************************** * Included Files ****************************************************************************/ #include +#include /**************************************************************************** * Pre-processor Definitions @@ -62,12 +65,14 @@ /* AR8031: */ +#define MII_AR8031_NAME "AR8031" #define MII_AR8031_PSSR 0x11 /* Phy-Specific Status Register */ /* National Semiconductor DP83840: 0x07-0x11, 0x14, 0x1a, 0x1d-0x1f * reserved */ +#define MII_DP83840_NAME "DP83840" #define MII_DP83840_COUNTER 0x12 /* Disconnect counter */ #define MII_DP83840_FCSCOUNTER 0x13 /* False carrier sense counter */ #define MII_DP83840_NWAYTEST 0x14 /* N-way auto-neg test reg */ @@ -80,6 +85,7 @@ /* Am79c874: 0x08-0x0f, 0x14, 0x16, 0x19-0x1f reserved */ +#define MII_AM79C874_NAME "AM79C874" #define MII_AM79C874_NPADVERTISE 0x07 /* Auto-negotiation next page advertisement */ #define MII_AM79C874_MISCFEATURES 0x10 /* Miscellaneous features reg */ #define MII_AM79C874_INTCS 0x11 /* Interrupt control/status */ @@ -91,6 +97,7 @@ /* Luminary LM3S6918 built-in PHY: 0x07-0x0f, 0x14-0x16, 0x19-0x1f reserved */ +#define MII_LM3S6918_NAME "LM3S6918" #define MII_LM_VSPECIFIC 0x10 /* Vendor-Specific */ #define MII_LM_INTCS 0x11 /* Interrupt control/status */ #define MII_LM_DIAGNOSTIC 0x12 /* Diagnostic */ @@ -100,12 +107,14 @@ /* Micrel KS8721: 0x15, 0x1b, and 0x1f */ +#define MII_KS8721_NAME "KS8721" #define MII_KS8721_RXERCOUNTER 0x15 /* RXER counter */ #define MII_KS8721_INTCS 0x1b /* Interrupt control/status register */ #define MII_KS8721_10BTCR 0x1f /* 10BASE-TX PHY control register */ /* Micrel KSZ8041: 0x15, 0x1b, 0x1e-0x1f */ +#define MII_KSZ8041_NAME "KSZ8041" #define MII_KSZ8041_RXERR 0x15 /* RXERR Counter */ #define MII_KSZ8041_INT 0x1b /* Interrupt Control/Status */ #define MII_KSZ8041_PHYCTRL1 0x1e /* PHY Control 1 */ @@ -113,6 +122,7 @@ /* Micrel KSZ8051: 0x11, 0x15-0x18, 0x1b, 0x1d-0x1f */ +#define MII_KSZ8051_NAME "KSZ8051" #define MII_KSZ8051_AFEC1 0x11 /* AFE Control 1 */ #define MII_KSZ8051_RXERR 0x15 /* RXERR Counter */ #define MII_KSZ8051_OMSO 0x16 /* Operation Mode Strap Override */ @@ -124,6 +134,8 @@ #define MII_KSZ8051_PHYCTRL2 0x1f /* PHY Control 2 */ /* Micrel KSZ8061: 0x10-0x18, 0x1b, 0x1c-0x1f */ + +#define MII_KSZ8061_NAME "KSZ8061" #define MII_KSZ8061_DIG_CTRL 0x10 /* Digital Control */ #define MII_KSZ8061_AFE_CTRL_0 0x11 /* AFE Control 0 */ #define MII_KSZ8061_AFE_CTRL_1 0x12 /* AFE Control 1 */ @@ -141,6 +153,7 @@ /* Micrel KSZ8081: 0x10-0x11, 0x15-0x18, 0x1b, 0x1d-0x1f */ +#define MII_KSZ8081_NAME "KSZ8081" #define MII_KSZ8081_DRCTRL 0x10 /* Digital Reserve Control */ #define MII_KSZ8081_AFEC1 0x11 /* AFE Control 1 */ #define MII_KSZ8081_RXERR 0x15 /* RXERR Counter */ @@ -156,6 +169,7 @@ * 0x8-0x15, 0x13, 0x1c reserved */ +#define MII_DP83848C_NAME "DP83848C" #define MII_DP83848C_STS 0x10 /* RO PHY Status Register */ #define MII_DP83848C_MICR 0x11 /* RW MII Interrupt Control Register */ #define MII_DP83848C_MISR 0x12 /* RO MII Interrupt Status Register */ @@ -171,6 +185,7 @@ /* Texas Instruments DP83825I PHY Extended Registers. */ +#define MII_DP83825I_NAME "DP83825I" #define MII_DP83825I_PHYSTS 0x10 /* RO PHY Status Register */ #define MII_DP83825I_PHYSCR 0x11 /* RW PHY Specific Control Register */ #define MII_DP83825I_MISR1 0x12 /* RO MII Interrupt Status Register 1 */ @@ -189,6 +204,7 @@ /* SMSC LAN8720 PHY Extended Registers */ +#define MII_LAN8720_NAME "LAN8720" #define MII_LAN8720_REV 0x10 /* Silicon Revision Register */ #define MII_LAN8720_MCSR 0x11 /* Mode Control/Status Register */ #define MII_LAN8720_MODES 0x12 /* Special modes */ @@ -201,6 +217,8 @@ /* SMSC LAN8740/LAN8742A PHY Extended Registers */ +#define MII_LAN8740_NAME "LAN8740" +#define MII_LAN8742A_NAME "LAN8742A" #define MII_LAN8740_CONFIG 0x10 /* EDPD NDL/Crossover Timer/EEE Configuration */ #define MII_LAN8740_MCSR 0x11 /* Mode Control/Status Register */ #define MII_LAN8740_MODES 0x12 /* Special modes */ @@ -215,6 +233,7 @@ /* Motorcomm YT8512C/YT8512H Extended Registers */ +#define MII_YT8512_NAME "YT8512" #define MII_YT8512_PHYSFC 0x10 /* PHY Function conrtol Register */ #define MII_YT8512_PHYSTS 0x11 /* PHY Status Register */ #define MII_YT8512_IMR 0x12 /* Interrupt Mask Register */ @@ -728,12 +747,15 @@ /* TJA110X MII ID1/2 register bits */ +#define MII_TJA1100_NAME "TJA1100" #define MII_PHYID1_TJA1100 0x0180 /* ID1 value for NXP TJA1100 */ #define MII_PHYID2_TJA1100 0xdc40 /* ID2 value for NXP TJA1100 */ +#define MII_TJA1101_NAME "TJA1101" #define MII_PHYID1_TJA1101 0x0180 /* ID1 value for NXP TJA1101 */ #define MII_PHYID2_TJA1101 0xdd00 /* ID2 value for NXP TJA1101 */ +#define MII_TJA1103_NAME "TJA1103" #define MII_PHYID1_TJA1103 0x01b /* ID1 value for NXP TJA1103 */ #define MII_PHYID2_TJA1103 0xB013 /* ID2 value for NXP TJA1103 */ @@ -915,6 +937,24 @@ * Type Definitions ****************************************************************************/ +struct phy_desc_s +{ + char name[16]; /* The name of the PHY */ + uint16_t id1; /* The MII_PHYID1 registers value */ + uint16_t id2; /* The MII_PHYID2 registers value */ + uint16_t status; /* The Phys status register or 0xffff */ + uint16_t address_lo; /* The lowest address to check for the PHY */ + uint16_t address_high; /* The highest address to check for the PHY or + * 0xffff uses only the address_lo (one address) + */ + uint16_t mbps10; /* The bit mask for 10MBP if status is not 0xffff */ + uint16_t mbps100; /* The bit mask for 100MBP if status is not 0xffff */ + uint16_t duplex; /* The bit mask for DUPLEX if status is not 0xffff */ + uint16_t clause; /* The PHY clause supported. 22 or 45 */ + uint16_t mbps1000; /* The bit mask for 1000MBP if status is not 0xffff */ + uint16_t speed_mask; /* The bit mask for mbps10, 100, 1000 */ +}; + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ @@ -932,4 +972,5 @@ extern "C" } #endif +#endif /* __ASSEMBLY__ */ #endif /* __INCLUDE_NUTTX_NET_MII_H */ diff --git a/include/nuttx/net/neighbor.h b/include/nuttx/net/neighbor.h index b1d4a8adc7071..9dc43144b554b 100644 --- a/include/nuttx/net/neighbor.h +++ b/include/nuttx/net/neighbor.h @@ -79,9 +79,10 @@ struct neighbor_addr_s struct neighbor_entry_s { - net_ipv6addr_t ne_ipaddr; /* IPv6 address of the Neighbor */ - struct neighbor_addr_s ne_addr; /* Link layer address of the Neighbor */ - clock_t ne_time; /* For aging, units of tick */ + net_ipv6addr_t ne_ipaddr; /* IPv6 address of the Neighbor */ + struct neighbor_addr_s ne_addr; /* Link layer address of the Neighbor */ + clock_t ne_time; /* For aging, units of tick */ + FAR struct net_driver_s *ne_dev; /* The device driver structure */ }; #ifdef __cplusplus diff --git a/include/nuttx/net/netdev.h b/include/nuttx/net/netdev.h index 647e6d7305722..97cea719b703e 100644 --- a/include/nuttx/net/netdev.h +++ b/include/nuttx/net/netdev.h @@ -320,6 +320,9 @@ struct net_driver_s in_addr_t d_ipaddr; /* Host IPv4 address assigned to the network interface */ in_addr_t d_draddr; /* Default router IP address */ in_addr_t d_netmask; /* Network subnet mask */ +#ifdef CONFIG_NET_ARP_ACD + struct arp_acd_s d_acd; /* ipv4 acd entry */ +#endif /* CONFIG_NET_ARP_ACD */ #endif #ifdef CONFIG_NET_IPv6 @@ -1035,6 +1038,20 @@ void netdev_iob_clear(FAR struct net_driver_s *dev); void netdev_iob_release(FAR struct net_driver_s *dev); +/**************************************************************************** + * Name: netdev_iob_clone + * + * Description: + * Backup the current iob buffer for a given NIC by cloning it. + * + * Assumptions: + * The caller has locked the network. + * + ****************************************************************************/ + +FAR struct iob_s *netdev_iob_clone(FAR struct net_driver_s *dev, + bool throttled); + /**************************************************************************** * Name: netdev_ipv6_add/del * diff --git a/include/nuttx/net/netdev_lowerhalf.h b/include/nuttx/net/netdev_lowerhalf.h index 009d47f23e53e..bfe4089225cbd 100644 --- a/include/nuttx/net/netdev_lowerhalf.h +++ b/include/nuttx/net/netdev_lowerhalf.h @@ -69,6 +69,7 @@ */ #define NETPKT_BUFLEN CONFIG_IOB_BUFSIZE +#define NETPKT_BUFNUM CONFIG_IOB_NBUFFERS /**************************************************************************** * Public Types diff --git a/include/nuttx/net/netfilter/ip6_tables.h b/include/nuttx/net/netfilter/ip6_tables.h index 2bc9ece045257..69be30af9a1a0 100644 --- a/include/nuttx/net/netfilter/ip6_tables.h +++ b/include/nuttx/net/netfilter/ip6_tables.h @@ -47,6 +47,13 @@ #define IP6T_SO_GET_REVISION_TARGET (IP6T_BASE_CTL + 5) #define IP6T_SO_GET_MAX IP6T_SO_GET_REVISION_TARGET +/* Values for "flag" field in struct ip6t_ip6 (general ip6 structure). */ + +#define IP6T_F_PROTO 0x01 /* Set if rule cares about upper protocols */ +#define IP6T_F_TOS 0x02 /* Match the TOS. */ +#define IP6T_F_GOTO 0x04 /* Set if jump is a goto */ +#define IP6T_F_MASK 0x07 /* All possible flag bits mask. */ + /* Values for "inv" field in struct ip6t_ip6. */ #define IP6T_INV_VIA_IN 0x01 /* Invert the sense of IN IFACE. */ diff --git a/include/nuttx/net/netfilter/ip_tables.h b/include/nuttx/net/netfilter/ip_tables.h index d5017fa6ea2c2..a8dbac320830e 100644 --- a/include/nuttx/net/netfilter/ip_tables.h +++ b/include/nuttx/net/netfilter/ip_tables.h @@ -47,13 +47,6 @@ #define IPT_SO_GET_REVISION_TARGET (IPT_BASE_CTL + 3) #define IPT_SO_GET_MAX IPT_SO_GET_REVISION_TARGET -/* Values for "flag" field in struct ip6t_ip6 (general ip6 structure). */ - -#define IP6T_F_PROTO 0x01 /* Set if rule cares about upper protocols */ -#define IP6T_F_TOS 0x02 /* Match the TOS. */ -#define IP6T_F_GOTO 0x04 /* Set if jump is a goto */ -#define IP6T_F_MASK 0x07 /* All possible flag bits mask. */ - /* Values for "inv" field in struct ipt_ip. */ #define IPT_INV_VIA_IN 0x01 /* Invert the sense of IN IFACE. */ diff --git a/include/nuttx/net/netfilter/netfilter.h b/include/nuttx/net/netfilter/netfilter.h index 322255c8c961f..9c74351884534 100644 --- a/include/nuttx/net/netfilter/netfilter.h +++ b/include/nuttx/net/netfilter/netfilter.h @@ -25,6 +25,7 @@ * Included Files ****************************************************************************/ +#include #include /**************************************************************************** diff --git a/include/nuttx/nuttx.h b/include/nuttx/nuttx.h index b6f37daafc944..1c67a705e87d8 100644 --- a/include/nuttx/nuttx.h +++ b/include/nuttx/nuttx.h @@ -48,4 +48,9 @@ #define container_of(ptr, type, member) \ ((type *)((uintptr_t)(ptr) - offsetof(type, member))) +/* Stringify the arguments */ + +#define STRINGIFY_(x) #x +#define STRINGIFY(x) STRINGIFY_(x) + #endif /* __INCLUDE_NUTTX_NUTTX_H */ diff --git a/include/nuttx/page.h b/include/nuttx/page.h index 2971e14fb66b1..adce1c2ddb908 100644 --- a/include/nuttx/page.h +++ b/include/nuttx/page.h @@ -33,7 +33,7 @@ # include #endif -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /**************************************************************************** * Pre-processor Definitions @@ -455,5 +455,5 @@ int up_fillpage(FAR struct tcb_s *tcb, FAR void *vpage, #endif #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ #endif /* __INCLUDE_NUTTX_PAGE_H */ diff --git a/include/nuttx/pci/pci.h b/include/nuttx/pci/pci.h new file mode 100644 index 0000000000000..40f8859369853 --- /dev/null +++ b/include/nuttx/pci/pci.h @@ -0,0 +1,472 @@ +/**************************************************************************** + * include/nuttx/pci/pci.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_PCI_PCI_H +#define __INCLUDE_NUTTX_PCI_PCI_H + +#ifdef CONFIG_PCI + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* PCI config common registers */ + +#define PCI_CONFIG_VENDOR 0x00 +#define PCI_CONFIG_DEVICE 0x02 +#define PCI_CONFIG_COMMAND 0x04 +#define PCI_CONFIG_REV_ID 0x08 +#define PCI_CONFIG_PROG_IF 0x09 +#define PCI_CONFIG_SUBCLASS 0x0A +#define PCI_CONFIG_CLASS 0x0B +#define PCI_CONFIG_CACHE_LINE_SIZE 0x0C +#define PCI_CONFIG_LATENCY_TIMER 0x0D +#define PCI_CONFIG_HEADER_TYPE 0x0E +#define PCI_CONFIG_BIST 0x0F + +/* PCI config header types */ + +#define PCI_HEADER_NORMAL 0x00 +#define PCI_HEADER_BRIDGE 0x01 +#define PCI_HEADER_CARDBUS 0x02 +#define PCI_HEADER_TYPE_MASK 0x3F +#define PCI_HEADER_MASK_MULTI 0x80 + +/* PCI config registers type 0 (Normal devices) */ + +#define PCI_HEADER_NORM_BAR0 0x10 +#define PCI_HEADER_NORM_BAR1 0x14 +#define PCI_HEADER_NORM_BAR2 0x18 +#define PCI_HEADER_NORM_BAR3 0x1C +#define PCI_HEADER_NORM_BAR4 0x20 +#define PCI_HEADER_NORM_BAR5 0x24 +#define PCI_HEADER_NORM_CB_CIS 0x28 +#define PCI_HEADER_NORM_SUB_VID 0x2C +#define PCI_HEADER_NORM_SUB_ID 0x2E +#define PCI_HEADER_NORM_EXP_ROM 0x30 +#define PCI_HEADER_NORM_CAP 0x34 +#define PCI_HEADER_NORM_INT_LINE 0x3C +#define PCI_HEADER_NORM_INT_PIN 0x3D +#define PCI_HEADER_NORM_MIN_GRANT 0x3E +#define PCI_HEADER_NORM_MAX_LAT 0x3E + +/* PCI config registers type 1 (PCI-PCI bridge) */ + +#define PCI_CONFIG_SEC_BUS 0x19 + +/* PCI config registers type 2 (CardBus) */ + +/* PCI Base Class Codes */ + +#define PCI_CLASS_BASE_UNCLASSIFIED 0x00 +#define PCI_CLASS_BASE_MASS_STORAGE_CTRL 0x01 +#define PCI_CLASS_BASE_NETWORK_CTRL 0x02 +#define PCI_CLASS_BASE_DISPLAY_CTRL 0x03 +#define PCI_CLASS_BASE_MULTIMEDIA_CTRL 0x04 +#define PCI_CLASS_BASE_MEM_CTRL 0x05 +#define PCI_CLASS_BASE_BRG_DEV 0x06 +#define PCI_CLASS_BASE_SMPL_COM_CTRL 0x07 +#define PCI_CLASS_BASE_BSP 0x08 +#define PCI_CLASS_BASE_INPUT_DEV_CTRL 0x09 +#define PCI_CLASS_BASE_DOCK_STN 0x0A +#define PCI_CLASS_BASE_PROCESSOR 0x0B +#define PCI_CLASS_BASE_SBC 0x0C +#define PCI_CLASS_BASE_WIRELESS_CTRL 0x0D +#define PCI_CLASS_BASE_INTL_CTRL 0x0E +#define PCI_CLASS_BASE_SAT_COM_CTRL 0x0F +#define PCI_CLASS_BASE_ENCRYPT_CTRL 0x10 +#define PCI_CLASS_BASE_SPC 0x11 +#define PCI_CLASS_BASE_PROC_ACCEL 0x12 +#define PCI_CLASS_BASE_NON_ES_INST 0x13 + +/* Reserved 0x14-0x3F */ + +#define PCI_CLASS_BASE_CO_PROC 0x40 + +/* Reserved 0x41-0xFE */ + +#define PCI_CLASS_BASE_UNASSIGNED 0xFF + +/* PCI Sub Class Codes (most missing) */ + +/* Bridge Class */ + +#define PCI_CLASS_SUB_HOST_BRG 0x00 +#define PCI_CLASS_SUB_ISA_BRG 0x01 +#define PCI_CLASS_SUB_EISA_BRG 0x02 +#define PCI_CLASS_SUB_MCA_BRG 0x03 +#define PCI_CLASS_SUB_PCI_BRG 0x04 +#define PCI_CLASS_SUB_PCMCIA_BRG 0x05 +#define PCI_CLASS_SUB_NUBUS_BRG 0x06 +#define PCI_CLASS_SUB_CARDBUS_BRG 0x07 +#define PCI_CLASS_SUB_RACEWAY_BRG 0x08 +#define PCI_CLASS_SUB_PCI_TRNSP_BRG 0x09 +#define PCI_CLASS_SUB_INFINI_BRG 0x0A +#define PCI_CLASS_SUB_NUBUS_BRG 0x80 + +#define PCI_ID_ANY 0xffff + +/* PCI Command Register Bitmasks */ + +#define PCI_CMD_IO_SPACE 0x0001 +#define PCI_CMD_MEM_SPACE 0x0002 +#define PCI_CMD_BUS_MSTR 0x0004 +#define PCI_CMD_SPECIAL_CYC 0x0008 +#define PCI_CMD_MEM_INV 0x0030 +#define PCI_CMD_VGA_PLT 0x0040 +#define PCI_CMD_PAR_ERR 0x0080 +#define PCI_CMD_SERR 0x0100 +#define PCI_CMD_FST_B2B 0x0200 +#define PCI_CMD_INT 0x0400 + +/* PCI BAR Bitmasks */ + +#define PCI_BAR_LAYOUT_MASK 0x00000001 +#define PCI_BAR_TYPE_MASK 0x00000006 +#define PCI_BAR_MEM_PF_MASK 0x00000008 +#define PCI_BAR_MEM_BASE_MASK 0xfffffff0 +#define PCI_BAR_IO_BASE_MASK 0xfffffffc + +/* PCI BAR OFFSETS */ + +#define PCI_BAR_LAYOUT_OFFSET 0 +#define PCI_BAR_TYPE_OFFSET 1 +#define PCI_BAR_MEM_PF_OFFSET 3 +#define PCI_BAR_MEM_BASE_OFFSET 4 +#define PCI_BAR_IO_BASE_OFFSET 2 + +/* PCI BAR */ + +#define PCI_BAR_CNT 6 +#define PCI_BAR_INVALID 0 +#define PCI_BAR_LAYOUT_MEM 0 +#define PCI_BAR_LAYOUT_IO 1 +#define PCI_BAR_TYPE_32 0x00 +#define PCI_BAR_TYPE_16 0x01 /* This mode is not used */ +#define PCI_BAR_TYPE_64 0x02 + +/* PCI CAP */ + +#define PCI_CAP_ID_PM 0x01 /* Power Management */ +#define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics */ +#define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */ +#define PCI_CAP_ID_SLOT 0x04 /* Slot ID */ +#define PCI_CAP_ID_MSI 0x05 /* MSI */ +#define PCI_CAP_ID_CHP 0x06 /* CompactPCI Hot-Swap */ +#define PCI_CAP_ID_PCIX 0x07 /* PCI-X */ +#define PCI_CAP_ID_HT 0x08 /* HyperTransport */ +#define PCI_CAP_ID_VNDR 0x09 /* Vendor */ +#define PCI_CAP_ID_DBG 0x0A /* Debug */ +#define PCI_CAP_ID_CCRC 0x0B /* CompactPCI Central Resource Control */ +#define PCI_CAP_ID_HOT 0x0C /* Hot-Plug Controller */ +#define PCI_CAP_ID_BRG_VID 0x0D /* Bridge Vendor/Device ID */ +#define PCI_CAP_ID_AGP_BRG 0x0E /* AGP PCI-PCI Bridge */ +#define PCI_CAP_ID_SEC_DEV 0x0F /* Secure Device */ +#define PCI_CAP_ID_PCIE 0x10 /* PCIe */ +#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */ +#define PCI_CAP_ID_SATA 0x12 /* SATA */ +#define PCI_CAP_ID_ADVF 0x13 /* Advanced Features */ + +#define PCI_CAP_ID_END PCI_CAP_ID_ADVF + +/* Resource types used by PCI devices */ + +#define PCI_SYS_RES_IOPORT 0x00 +#define PCI_SYS_RES_MEM 0x01 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* The PCI driver interface */ + +struct pci_bus_s; +struct pci_dev_type_s; +struct pci_dev_s; + +/* Bus related operations */ + +struct pci_bus_ops_s +{ + /* Write 8, 16, 32, 64 bits data to PCI-E configuration space of device + * specified by dev. + */ + + CODE void (*pci_cfg_write)(FAR struct pci_dev_s *dev, int reg, + uint32_t val, int width); + + /* Read 8, 16, 32, 64 bits data to PCI-E configuration space of device + * specified by dev. + */ + + CODE uint32_t (*pci_cfg_read)(FAR struct pci_dev_s *dev, int reg, + int width); + + /* Map address in a 32 bits bar in the memory address space */ + + CODE int (*pci_map_bar)(uint64_t addr, uint64_t len); + + /* Read from IO port */ + + CODE uint32_t (*pci_io_read)(FAR const volatile void *addr, int width); + + /* Write to IO port */ + + CODE void (*pci_io_write)(FAR const volatile void *addr, uint32_t val, + int width); +}; + +/* PCI bus private data. */ + +struct pci_bus_s +{ + FAR const struct pci_bus_ops_s *ops; /* operations */ +}; + +/* PCI device type, defines by vendor ID and device ID */ + +struct pci_dev_type_s +{ + uint16_t vendor; /* Device vendor ID */ + uint16_t device; /* Device ID */ + uint32_t class_rev; /* Device reversion */ + const char *name; /* Human readable name */ + + /* Call back function when a device is probed */ + + CODE int (*probe)(FAR struct pci_bus_s *bus, + FAR const struct pci_dev_type_s *type, uint16_t bdf); +}; + +/* PCI device private data. */ + +struct pci_dev_s +{ + FAR struct pci_bus_s *bus; + FAR const struct pci_dev_type_s *type; + uint32_t bdf; +}; + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: pci_initialize + * + * Description: + * Initialize the PCI bus and enumerate the devices with give devices + * type array + * + * Input Parameters: + * bus - An PCI bus + * types - A array of PCI device types + * + * Returned Value: + * OK if the driver was successfully register; A negated errno value is + * returned on any failure. + * + ****************************************************************************/ + +int pci_initialize(FAR struct pci_bus_s *bus); + +/**************************************************************************** + * Name: pci_enable_io + * + * Description: + * Enable MMIO or IOPORT + * + * Input Parameters: + * dev - device + * space - which resource is being enabled + * PCI_SYS_RES_IOPORT for io port address decoding or + * PCI_RES_MEM for memory + * + * Return value: + * -EINVAL: error + * OK: OK + * + ****************************************************************************/ + +int pci_enable_io(FAR struct pci_dev_s *dev, int res); + +/**************************************************************************** + * Name: pci_disable_io + * + * Description: + * Enable MMIO or IOPORT + * + * Input Parameters: + * dev - device + * space - which resource is being disabled + * PCI_SYS_RES_IOPORT for io port address decoding or + * PCI_SYS_RES_MEM for memory + * + * Return value: + * -EINVAL: error + * OK: OK + * + ****************************************************************************/ + +int pci_disable_io(FAR struct pci_dev_s *dev, int res); + +/**************************************************************************** + * Name: pci_enable_bus_master + * + * Description: + * Enable bus mastering for device so it can perform PCI accesses + * + * Input Parameters: + * dev - device + * + * Return value: + * -EINVAL: error + * OK: OK + * + ****************************************************************************/ + +int pci_enable_bus_master(FAR struct pci_dev_s *dev); + +/**************************************************************************** + * Name: pci_disable_bus_master + * + * Description: + * Disable bus mastering for device + * + * Input Parameters: + * dev - device + * + * Return value: + * -EINVAL: error + * OK: OK + * + ****************************************************************************/ + +int pci_disable_bus_master(FAR struct pci_dev_s *dev); + +/**************************************************************************** + * Name: pci_bar_valid + * + * Description: + * Determine in if the address in the BAR is valid + * + * Input Parameters: + * dev - device + * bar_id - bar number + * + * Return value: + * -EINVAL: error + * OK: OK + * + ****************************************************************************/ + +int pci_bar_valid(FAR struct pci_dev_s *dev, uint8_t bar_id); + +/**************************************************************************** + * Name: pci_bar_is_64 + * + * Description: + * Determine in if the bar address is 64 bit. If it is the address includes + * the address in the next bar location. + * + * Input Parameters: + * dev - device + * bar_id - bar number + * + * Return value: + * true: 64bit address + * + ****************************************************************************/ + +bool pci_bar_is_64(FAR struct pci_dev_s *dev, uint8_t bar_id); + +/**************************************************************************** + * Name: pci_bar_size + * + * Description: + * Determine the size of the address space required by the BAR + * + * Input Parameters: + * dev - device + * bar_id - bar number + * + * Return value: + * Size of address space + * + ****************************************************************************/ + +uint64_t pci_bar_size(FAR struct pci_dev_s *dev, uint8_t bar_id); + +/**************************************************************************** + * Name: pci_bar_addr + * + * Description: + * Determine the size of the address space required by the BAR + * + * Input Parameters: + * dev - device + * bar_id - bar number + * + * Return value: + * full bar address + * + ****************************************************************************/ + +uint64_t pci_bar_addr(FAR struct pci_dev_s *dev, uint8_t bar_id); + +/**************************************************************************** + * Name: pci_dev_dump + * + * Description: + * Dump the configuration information for the device + * + * Input Parameters: + * dev - device + * + ****************************************************************************/ + +void pci_dev_dump(FAR struct pci_dev_s *dev); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif +#endif /* __INCLUDE_NUTTX_PCI_PCI_H */ diff --git a/include/nuttx/power/pm.h b/include/nuttx/power/pm.h index dc7311c32ea61..3bdd491f3e005 100644 --- a/include/nuttx/power/pm.h +++ b/include/nuttx/power/pm.h @@ -145,6 +145,15 @@ enum pm_state_e PM_COUNT, }; +#ifdef CONFIG_PM_PROCFS +struct pm_preparefail_s +{ + enum pm_state_e state; + struct timespec start; + struct timespec duration[PM_COUNT]; +}; +#endif + /* This structure contain pointers callback functions in the driver. These * callback functions can be used to provide power management information * to the driver. @@ -211,6 +220,10 @@ struct pm_callback_s CODE void (*notify)(FAR struct pm_callback_s *cb, int domain, enum pm_state_e pmstate); + +#ifdef CONFIG_PM_PROCFS + struct pm_preparefail_s preparefail[CONFIG_PM_NDOMAINS]; +#endif }; /* An instance of a given PM governor */ @@ -351,6 +364,19 @@ extern "C" void pm_initialize(void); +/**************************************************************************** + * Name: pm_stability_governor_initialize + * + * Description: + * Return the stability governor instance. + * + * Returned Value: + * A pointer to the governor struct. Otherwise NULL is returned on error. + * + ****************************************************************************/ + +FAR const struct pm_governor_s *pm_stability_governor_initialize(void); + /**************************************************************************** * Name: pm_greedy_governor_initialize * diff --git a/include/nuttx/queue.h b/include/nuttx/queue.h index 159f548e49615..6a07d6a4dc732 100644 --- a/include/nuttx/queue.h +++ b/include/nuttx/queue.h @@ -290,6 +290,14 @@ #define dq_inqueue(p, q) \ ((p)->flink || dq_tail(q) == (p)) +/* sq/dq_is_singular - tests whether a list has just one entry. */ + +#define sq_is_singular(q) \ + (!sq_empty(q) && (q)->head->flink == NULL) + +#define dq_is_singular(q) \ + (!dq_empty(q) && (q)->head->flink == NULL) + /**************************************************************************** * Public Type Definitions ****************************************************************************/ diff --git a/include/nuttx/rpmsg/rpmsg.h b/include/nuttx/rpmsg/rpmsg.h new file mode 100644 index 0000000000000..c8be7e014802a --- /dev/null +++ b/include/nuttx/rpmsg/rpmsg.h @@ -0,0 +1,139 @@ +/**************************************************************************** + * include/nuttx/rpmsg/rpmsg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_RPMSG_RPMSG_H +#define __INCLUDE_NUTTX_RPMSG_RPMSG_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_RPMSG + +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define RPMSGIOC_PANIC _RPMSGIOC(1) +#define RPMSGIOC_DUMP _RPMSGIOC(2) +#define RPMSGIOC_PING _RPMSGIOC(3) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct rpmsg_s +{ + struct metal_list bind; + rmutex_t lock; + struct metal_list node; + FAR const struct rpmsg_ops_s *ops; +#ifdef CONFIG_RPMSG_PING + struct rpmsg_endpoint ping; +#endif + struct rpmsg_device rdev[0]; +}; + +/** + * struct rpmsg_ops_s - Rpmsg device operations + * wait: wait sem. + * post: post sem. + * get_cpuname: get cpu name. + * get_tx_buffer_size: get tx buffer size. + * get_rx_buffer_size: get rx buffer size. + */ + +struct rpmsg_ops_s +{ + CODE int (*wait)(FAR struct rpmsg_s *rpmsg, FAR sem_t *sem); + CODE int (*post)(FAR struct rpmsg_s *rpmsg, FAR sem_t *sem); + CODE int (*ioctl)(FAR struct rpmsg_s *rpmsg, int cmd, unsigned long arg); + CODE void (*panic)(FAR struct rpmsg_s *rpmsg); + CODE void (*dump)(FAR struct rpmsg_s *rpmsg); + CODE FAR const char *(*get_cpuname)(FAR struct rpmsg_s *rpmsg); + CODE int (*get_tx_buffer_size)(FAR struct rpmsg_s *rpmsg); + CODE int (*get_rx_buffer_size)(FAR struct rpmsg_s *rpmsg); +}; + +CODE typedef void (*rpmsg_dev_cb_t)(FAR struct rpmsg_device *rdev, + FAR void *priv); +CODE typedef bool (*rpmsg_match_cb_t)(FAR struct rpmsg_device *rdev, + FAR void *priv, FAR const char *name, + uint32_t dest); +CODE typedef void (*rpmsg_bind_cb_t)(FAR struct rpmsg_device *rdev, + FAR void *priv, FAR const char *name, + uint32_t dest); + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +int rpmsg_wait(FAR struct rpmsg_endpoint *ept, FAR sem_t *sem); +int rpmsg_post(FAR struct rpmsg_endpoint *ept, FAR sem_t *sem); + +FAR const char *rpmsg_get_cpuname(FAR struct rpmsg_device *rdev); + +int rpmsg_get_tx_buffer_size(FAR struct rpmsg_device *rdev); +int rpmsg_get_rx_buffer_size(FAR struct rpmsg_device *rdev); + +int rpmsg_register_callback(FAR void *priv, + rpmsg_dev_cb_t device_created, + rpmsg_dev_cb_t device_destroy, + rpmsg_match_cb_t ns_match, + rpmsg_bind_cb_t ns_bind); +void rpmsg_unregister_callback(FAR void *priv, + rpmsg_dev_cb_t device_created, + rpmsg_dev_cb_t device_destroy, + rpmsg_match_cb_t ns_match, + rpmsg_bind_cb_t ns_bind); +void rpmsg_ns_bind(FAR struct rpmsg_device *rdev, + FAR const char *name, uint32_t dest); +void rpmsg_ns_unbind(FAR struct rpmsg_device *rdev, + FAR const char *name, uint32_t dest); +void rpmsg_device_created(FAR struct rpmsg_s *rpmsg); +void rpmsg_device_destory(FAR struct rpmsg_s *rpmsg); +int rpmsg_register(FAR const char *path, FAR struct rpmsg_s *rpmsg, + FAR const struct rpmsg_ops_s *ops); +void rpmsg_unregister(FAR const char *path, FAR struct rpmsg_s *rpmsg); +int rpmsg_ioctl(FAR const char *cpuname, int cmd, unsigned long arg); + +int rpmsg_panic(FAR const char *cpuname); +void rpmsg_dump_all(void); + +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_RPMSG */ +#endif /* __INCLUDE_NUTTX_RPMSG_RPMSG_H */ diff --git a/include/nuttx/rpmsg/rpmsg_ping.h b/include/nuttx/rpmsg/rpmsg_ping.h new file mode 100644 index 0000000000000..db0884c8c5608 --- /dev/null +++ b/include/nuttx/rpmsg/rpmsg_ping.h @@ -0,0 +1,47 @@ +/**************************************************************************** + * include/nuttx/rpmsg/rpmsg_ping.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_RPMSG_RPMSG_PING_H +#define __INCLUDE_NUTTX_RPMSG_RPMSG_PING_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_RPMSG_PING + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/* used for ioctl RPMSGIOC_PING */ + +struct rpmsg_ping_s +{ + int times; + int len; + int ack; + int sleep; /* unit: ms */ +}; + +#endif /* CONFIG_RPMSG_PING */ +#endif /* __INCLUDE_NUTTX_RPMSG_RPMSG_PING_H */ diff --git a/include/nuttx/rptun/openamp.h b/include/nuttx/rptun/openamp.h index 98f4d54c6d90e..c06080e02cea4 100644 --- a/include/nuttx/rptun/openamp.h +++ b/include/nuttx/rptun/openamp.h @@ -27,55 +27,6 @@ #include -#ifdef CONFIG_RPTUN +#include -#include -#include - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -typedef void (*rpmsg_dev_cb_t)(FAR struct rpmsg_device *rdev, - FAR void *priv); -typedef bool (*rpmsg_match_cb_t)(FAR struct rpmsg_device *rdev, - FAR void *priv, FAR const char *name, - uint32_t dest); -typedef void (*rpmsg_bind_cb_t)(FAR struct rpmsg_device *rdev, - FAR void *priv, FAR const char *name, - uint32_t dest); - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -int rpmsg_wait(FAR struct rpmsg_endpoint *ept, FAR sem_t *sem); -int rpmsg_post(FAR struct rpmsg_endpoint *ept, FAR sem_t *sem); - -const char *rpmsg_get_cpuname(FAR struct rpmsg_device *rdev); - -int rpmsg_register_callback(FAR void *priv, - rpmsg_dev_cb_t device_created, - rpmsg_dev_cb_t device_destroy, - rpmsg_match_cb_t ns_match, - rpmsg_bind_cb_t ns_bind); -void rpmsg_unregister_callback(FAR void *priv, - rpmsg_dev_cb_t device_created, - rpmsg_dev_cb_t device_destroy, - rpmsg_match_cb_t ns_match, - rpmsg_bind_cb_t ns_bind); - -#ifdef __cplusplus -} -#endif - -#endif /* CONFIG_RPTUN */ #endif /* __INCLUDE_NUTTX_RPTUN_OPENAMP_H */ diff --git a/include/nuttx/rptun/rptun.h b/include/nuttx/rptun/rptun.h index a27cc86582ecc..aafe4476cb7ca 100644 --- a/include/nuttx/rptun/rptun.h +++ b/include/nuttx/rptun/rptun.h @@ -29,19 +29,20 @@ #ifdef CONFIG_RPTUN -#include -#include +#include +#include +#include /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define RPTUNIOC_START _RPTUNIOC(1) -#define RPTUNIOC_STOP _RPTUNIOC(2) -#define RPTUNIOC_RESET _RPTUNIOC(3) -#define RPTUNIOC_PANIC _RPTUNIOC(4) -#define RPTUNIOC_DUMP _RPTUNIOC(5) -#define RPTUNIOC_PING _RPTUNIOC(6) +#define _RPTUNIOCVALID(c) _RPMSGIOCVALID(c) +#define _RPTUNIOC(nr) _RPMSGIOC(nr) + +#define RPTUNIOC_START _RPTUNIOC(100) +#define RPTUNIOC_STOP _RPTUNIOC(101) +#define RPTUNIOC_RESET _RPTUNIOC(102) #define RPTUN_NOTIFY_ALL (UINT32_MAX - 0) @@ -163,7 +164,7 @@ * OK unless an error occurs. Then a negated errno value is returned * ****************************************************************************/ -#define RPTUN_CONFIG(d, p) ((d)->ops->config ?\ +#define RPTUN_CONFIG(d, p) ((d)->ops->config ? \ (d)->ops->config(d, p) : 0) /**************************************************************************** @@ -342,16 +343,6 @@ struct rptun_dev_s FAR const struct rptun_ops_s *ops; }; -/* used for ioctl RPTUNIOC_PING */ - -struct rptun_ping_s -{ - int times; - int len; - bool ack; - int sleep; /* unit: ms */ -}; - /**************************************************************************** * Public Function Prototypes ****************************************************************************/ @@ -368,8 +359,6 @@ int rptun_initialize(FAR struct rptun_dev_s *dev); int rptun_boot(FAR const char *cpuname); int rptun_poweroff(FAR const char *cpuname); int rptun_reset(FAR const char *cpuname, int value); -int rptun_panic(FAR const char *cpuname); -void rptun_dump_all(void); #ifdef __cplusplus } diff --git a/include/nuttx/rwsem.h b/include/nuttx/rwsem.h index 69a89beb00ee1..2999bfcd528b7 100644 --- a/include/nuttx/rwsem.h +++ b/include/nuttx/rwsem.h @@ -25,7 +25,8 @@ * Included Files ****************************************************************************/ -#include +#include +#include /**************************************************************************** * Public Type Definitions @@ -33,11 +34,11 @@ typedef struct { - mutex_t protected; /* Protecting Locks for Read/Write Locked Tables */ - sem_t waiting; /* Reader/writer Waiting queue */ - int waiter; /* Waiter Count */ - int writer; /* Writer Count */ - int reader; /* Reader Count */ + spinlock_t protected; + sem_t waiting; + int waiter; + int writer; + int reader; } rw_semaphore_t; /**************************************************************************** diff --git a/include/nuttx/sched.h b/include/nuttx/sched.h index a80af294e02bf..2dcd7bd9c4950 100644 --- a/include/nuttx/sched.h +++ b/include/nuttx/sched.h @@ -45,6 +45,7 @@ #include #include #include +#include #include @@ -103,6 +104,8 @@ #define TCB_FLAG_HEAP_DUMP (1 << 11) /* Bit 11: Heap dump */ #define TCB_FLAG_DETACHED (1 << 12) /* Bit 12: Pthread detached */ #define TCB_FLAG_FORCED_CANCEL (1 << 13) /* Bit 13: Pthread cancel is forced */ +#define TCB_FLAG_JOIN_COMPLETED (1 << 14) /* Bit 14: Pthread join completed */ +#define TCB_FLAG_FREE_TCB (1 << 15) /* Bit 15: Free tcb after exit */ /* Values for struct task_group tg_flags */ @@ -193,6 +196,16 @@ #define get_current_mm() (get_group_mm(nxsched_self()->group)) +/* These are macros to access the current CPU and the current task on a CPU. + * These macros are intended to support a future SMP implementation. + */ + +#ifdef CONFIG_SMP +# define this_cpu() up_cpu_index() +#else +# define this_cpu() (0) +#endif + /**************************************************************************** * Public Type Definitions ****************************************************************************/ @@ -224,7 +237,7 @@ enum tstate_e TSTATE_WAIT_MQNOTEMPTY, /* BLOCKED - Waiting for a MQ to become not empty. */ TSTATE_WAIT_MQNOTFULL, /* BLOCKED - Waiting for a MQ to become not full. */ #endif -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING TSTATE_WAIT_PAGEFILL, /* BLOCKED - Waiting for page fill */ #endif #ifdef CONFIG_SIG_SIGSTOP_ACTION @@ -376,6 +389,17 @@ struct stackinfo_s /* from the stack. */ }; +/* struct task_join_s *******************************************************/ + +/* Used to save task join information */ + +struct task_join_s +{ + sq_entry_t entry; /* Implements link list */ + pid_t pid; /* Includes pid */ + pthread_addr_t exit_value; /* Returned data */ +}; + /* struct task_group_s ******************************************************/ /* All threads created by pthread_create belong in the same task group (along @@ -386,7 +410,6 @@ struct stackinfo_s * This structure should contain *all* resources shared by tasks and threads * that belong to the same task group: * - * Child exit status * Environment variables * PIC data space and address environments * File descriptors @@ -401,12 +424,6 @@ struct stackinfo_s * the struct task_group_s is free. */ -struct task_info_s; - -#ifndef CONFIG_DISABLE_PTHREAD -struct join_s; /* Forward reference */ - /* Defined in sched/pthread/pthread.h */ -#endif #ifdef CONFIG_BINFMT_LOADABLE struct binary_s; /* Forward reference */ /* Defined in include/nuttx/binfmt/binfmt.h */ @@ -414,9 +431,6 @@ struct binary_s; /* Forward reference struct task_group_s { -#if defined(HAVE_GROUP_MEMBERS) - struct task_group_s *flink; /* Supports a singly linked list */ -#endif pid_t tg_pid; /* The ID of the task within the group */ pid_t tg_ppid; /* This is the ID of the parent thread */ uint8_t tg_flags; /* See GROUP_FLAG_* definitions */ @@ -432,10 +446,8 @@ struct task_group_s /* Group membership *******************************************************/ - uint8_t tg_nmembers; /* Number of members in the group */ #ifdef HAVE_GROUP_MEMBERS - uint8_t tg_mxmembers; /* Number of members in allocation */ - FAR pid_t *tg_members; /* Members of the group */ + sq_queue_t tg_members; /* List of members for task */ #endif #ifdef CONFIG_BINFMT_LOADABLE @@ -471,15 +483,15 @@ struct task_group_s #ifndef CONFIG_DISABLE_PTHREAD /* Pthreads ***************************************************************/ - /* Pthread join Info: */ - - mutex_t tg_joinlock; /* Mutually exclusive access to join data */ - FAR struct join_s *tg_joinhead; /* Head of a list of join data */ - FAR struct join_s *tg_jointail; /* Tail of a list of join data */ + rmutex_t tg_joinlock; /* Synchronize access to tg_joinqueue */ + sq_queue_t tg_joinqueue; /* List of join status of tcb */ #endif /* Thread local storage ***************************************************/ +#ifndef CONFIG_MM_KERNEL_HEAP + struct task_info_s tg_info_; +#endif FAR struct task_info_s *tg_info; /* POSIX Signal Control Fields ********************************************/ @@ -494,6 +506,7 @@ struct task_group_s /* Environment variables **************************************************/ FAR char **tg_envp; /* Allocated environment strings */ + ssize_t tg_envpc; /* Maximum entries of environment array */ ssize_t tg_envc; /* Number of environment strings */ #endif @@ -516,7 +529,7 @@ struct task_group_s /* Virtual memory mapping info ********************************************/ - struct mm_map_s tg_mm_map; /* Task mmappings */ + struct mm_map_s tg_mm_map; /* Task group virtual memory mappings */ }; /* struct tcb_s *************************************************************/ @@ -536,13 +549,28 @@ struct tcb_s /* Task Group *************************************************************/ - FAR struct task_group_s *group; /* Pointer to shared task group data */ + FAR struct task_group_s *group; /* Pointer to shared task group */ + + /* Group membership *******************************************************/ + +#ifdef HAVE_GROUP_MEMBERS + sq_entry_t member; /* List entry of task member */ +#endif + + /* Task join **************************************************************/ + +#ifndef CONFIG_DISABLE_PTHREAD + sq_queue_t join_queue; /* List of wait entries for task */ + sq_entry_t join_entry; /* List entry of task join */ + sem_t join_sem; /* Semaphore for task join */ + pthread_addr_t join_val; /* Returned data */ +#endif /* Address Environment ****************************************************/ #ifdef CONFIG_ARCH_ADDRENV - FAR struct addrenv_s *addrenv_own; /* Task (group) own memory mappings */ - FAR struct addrenv_s *addrenv_curr; /* Current active memory mappings */ + FAR struct addrenv_s *addrenv_own; /* Task(group) own memory mappings */ + FAR struct addrenv_s *addrenv_curr; /* Current active memory mappings */ #endif /* Task Management Fields *************************************************/ @@ -557,8 +585,8 @@ struct tcb_s uint8_t task_state; /* Current state of the thread */ #ifdef CONFIG_PRIORITY_INHERITANCE - uint8_t boost_priority; /* "Boosted" priority of the thread */ - uint8_t base_priority; /* "Normal" priority of the thread */ + uint8_t boost_priority; /* Boosted priority of the thread */ + uint8_t base_priority; /* Normal priority of the thread */ FAR struct semholder_s *holdsem; /* List of held semaphores */ #endif @@ -566,7 +594,7 @@ struct tcb_s uint8_t cpu; /* CPU index if running/assigned */ cpu_set_t affinity; /* Bit set of permitted CPUs */ #endif - uint16_t flags; /* Misc. general status flags */ + uint32_t flags; /* Misc. general status flags */ int16_t lockcount; /* 0=preemptible (not-locked) */ #ifdef CONFIG_IRQCOUNT int16_t irqcount; /* 0=Not in critical section */ @@ -597,7 +625,7 @@ struct tcb_s /* External Module Support ************************************************/ #ifdef CONFIG_PIC - FAR struct dspace_s *dspace; /* Allocated area for .bss and .data */ + FAR struct dspace_s *dspace; /* Area for .bss and .data */ #endif /* POSIX Semaphore and Message Queue Control Fields ***********************/ @@ -610,7 +638,7 @@ struct tcb_s sigset_t sigwaitmask; /* Waiting for pending signals */ sq_queue_t sigpendactionq; /* List of pending signal actions */ sq_queue_t sigpostedq; /* List of posted signals */ - siginfo_t sigunbinfo; /* Signal info when task unblocked */ + siginfo_t *sigunbinfo; /* Signal info when task unblocked */ /* Robust mutex support ***************************************************/ @@ -621,19 +649,19 @@ struct tcb_s /* CPU load monitoring support ********************************************/ #ifndef CONFIG_SCHED_CPULOAD_NONE - uint32_t ticks; /* Number of ticks on this thread */ + clock_t ticks; /* Number of ticks on this thread */ #endif /* Pre-emption monitor support ********************************************/ #ifdef CONFIG_SCHED_CRITMONITOR - clock_t premp_start; /* Time when preemption disabled */ - clock_t premp_max; /* Max time preemption disabled */ - clock_t crit_start; /* Time critical section entered */ - clock_t crit_max; /* Max time in critical section */ - clock_t run_start; /* Time when thread begin run */ - clock_t run_max; /* Max time thread run */ - clock_t run_time; /* Total time thread run */ + clock_t premp_start; /* Time when preemption disabled */ + clock_t premp_max; /* Max time preemption disabled */ + clock_t crit_start; /* Time critical section entered */ + clock_t crit_max; /* Max time in critical section */ + clock_t run_start; /* Time when thread begin run */ + clock_t run_max; /* Max time thread run */ + clock_t run_time; /* Total time thread run */ #endif /* State save areas *******************************************************/ @@ -643,7 +671,7 @@ struct tcb_s struct xcptcontext xcp; /* Interrupt register save area */ #if CONFIG_TASK_NAME_SIZE > 0 - char name[CONFIG_TASK_NAME_SIZE + 1]; /* Task name (with NUL terminator */ + char name[CONFIG_TASK_NAME_SIZE + 1]; /* Task name (with NUL terminator) */ #endif #if CONFIG_SCHED_STACK_RECORD > 0 @@ -676,11 +704,15 @@ struct task_tcb_s struct tcb_s cmn; /* Common TCB fields */ + /* Task Group *************************************************************/ + + struct task_group_s group; /* Shared task group data */ + /* Task Management Fields *************************************************/ #ifdef CONFIG_SCHED_STARTHOOK - starthook_t starthook; /* Task startup function */ - FAR void *starthookarg; /* The argument passed to the function */ + starthook_t starthook; /* Task startup function */ + FAR void *starthookarg; /* The argument passed to the hook */ #endif }; @@ -704,10 +736,8 @@ struct pthread_tcb_s /* Task Management Fields *************************************************/ - pthread_trampoline_t trampoline; /* User-space pthread startup function */ - pthread_addr_t arg; /* Startup argument */ - FAR void *joininfo; /* Detach-able info to support join */ - bool join_complete; /* Join was completed */ + pthread_trampoline_t trampoline; /* User-space startup function */ + pthread_addr_t arg; /* Startup argument */ }; #endif /* !CONFIG_DISABLE_PTHREAD */ @@ -1180,7 +1210,7 @@ int group_exitinfo(pid_t pid, FAR struct binary_s *bininfo); * ****************************************************************************/ -#if CONFIG_RR_INTERVAL > 0 || defined(CONFIG_SCHED_RESUMESCHEDULER) +#if defined(CONFIG_SCHED_RESUMESCHEDULER) void nxsched_resume_scheduler(FAR struct tcb_s *tcb); #else # define nxsched_resume_scheduler(tcb) diff --git a/include/nuttx/sensors/adxl362.h b/include/nuttx/sensors/adxl362.h new file mode 100644 index 0000000000000..8102d9ffb8480 --- /dev/null +++ b/include/nuttx/sensors/adxl362.h @@ -0,0 +1,65 @@ +/**************************************************************************** + * include/nuttx/sensors/adxl362.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_SENSORS_ADXL362_H +#define __INCLUDE_NUTTX_SENSORS_ADXL362_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: adxl362_register + * + * Description: + * Register the ADXL362 character device as uorb + * + * Input Parameters: + * devno - device instance + * spi - An instance of the SPI interface to use to communicate with + * ADXL362 + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int adxl362_register(int devno, FAR struct spi_dev_s *spi); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_NUTTX_SENSORS_ADXL362_H */ diff --git a/include/nuttx/sensors/adxl372.h b/include/nuttx/sensors/adxl372.h index 896d7ba1b6767..3574e82901cb9 100644 --- a/include/nuttx/sensors/adxl372.h +++ b/include/nuttx/sensors/adxl372.h @@ -95,54 +95,54 @@ /* ADXL372 Accelerometer Register definitions */ -#define ADXL372_DEVID_AD (0x00 << 1) +#define ADXL372_DEVID_AD 0x00 # define ADXL372_DEVID_AD_VALUE 0xad -#define ADXL372_DEVID_MST (0x01 << 1) -# define ADXL372_DEVID_MST_VALUE 0x1D -#define ADXL372_PARTID (0x02 << 1) +#define ADXL372_DEVID_MST 0x01 +# define ADXL372_DEVID_MST_VALUE 0x1d +#define ADXL372_PARTID 0x02 # define ADXL372_PARTID_VALUE 0xfa -#define ADXL372_REVID (0x03 << 1) -#define ADXL372_STATUS (0x04 << 1) -#define ADXL372_STATUS2 (0x05 << 1) -#define ADXL372_FIFO_ENTRIES2 (0x06 << 1) -#define ADXL372_FIFO_ENTRIES (0x07 << 1) -#define ADXL372_XDATA_H (0x08 << 1) -#define ADXL372_XDATA_L (0x09 << 1) -#define ADXL372_YDATA_H (0x0a << 1) -#define ADXL372_YDATA_L (0x0b << 1) -#define ADXL372_ZDATA_H (0x0c << 1) -#define ADXL372_ZDATA_L (0x0d << 1) -#define ADXL372_THRESH_ACT_X_H (0x23 << 1) -#define ADXL372_FIFO_CTL (0x3a << 1) +#define ADXL372_REVID 0x03 +#define ADXL372_STATUS 0x04 +#define ADXL372_STATUS2 0x05 +#define ADXL372_FIFO_ENTRIES2 0x06 +#define ADXL372_FIFO_ENTRIES 0x07 +#define ADXL372_XDATA_H 0x08 +#define ADXL372_XDATA_L 0x09 +#define ADXL372_YDATA_H 0x0a +#define ADXL372_YDATA_L 0x0b +#define ADXL372_ZDATA_H 0x0c +#define ADXL372_ZDATA_L 0x0d +#define ADXL372_THRESH_ACT_X_H 0x23 +#define ADXL372_FIFO_CTL 0x3a # define ADXL372_FIFO_BYPASSED 0x00 # define ADXL372_FIFO_STREAMED 0x02 -#define ADXL372_INT1_MAP (0x3b << 1) +#define ADXL372_INT1_MAP 0x3b # define ADXL372_INT1_MAP_DR 0x01 # define ADXL372_INT1_MAP_FRDY 0x02 # define ADXL372_INT1_MAP_FFULL 0x04 -#define ADXL372_TIMING (0x3d << 1) +#define ADXL372_TIMING 0x3d # define ADXL372_TIMING_ODR400 (0x0 << 5) /* 400 Hz ODR */ # define ADXL372_TIMING_ODR800 (0x1 << 5) /* 800 Hz ODR */ # define ADXL372_TIMING_ODR1600 (0x2 << 5) /* 1600 Hz ODR */ # define ADXL372_TIMING_ODR3200 (0x3 << 5) /* 3200 Hz ODR */ # define ADXL372_TIMING_ODR6400 (0x4 << 5) /* 6400 Hz ODR */ -#define ADXL372_MEASURE (0x3e << 1) +#define ADXL372_MEASURE 0x3e # define ADXL372_MEAS_BW200 0x0 /* 200 Hz Bandwidth */ # define ADXL372_MEAS_BW400 0x1 /* 400 Hz Bandwidth */ # define ADXL372_MEAS_BW800 0x2 /* 800 Hz Bandwidth */ # define ADXL372_MEAS_BW1600 0x3 /* 1600 Hz Bandwidth */ # define ADXL372_MEAS_BW3200 0x4 /* 3200 Hz Bandwidth */ -#define ADXL372_POWER_CTL (0x3f << 1) +#define ADXL372_POWER_CTL 0x3f # define ADXL372_POWER_LPF_DISABLE (1 << 3) # define ADXL372_POWER_HPF_DISABLE (1 << 2) # define ADXL372_POWER_MODE_STANDBY 0x0 # define ADXL372_POWER_MODE_WAKEUP 0x1 # define ADXL372_POWER_MODE_INSTON 0x2 # define ADXL372_POWER_MODE_MEASURE 0x3 -#define ADXL372_RESET (0x41 << 1) +#define ADXL372_RESET 0x41 # define ADXL372_RESET_VALUE 0x52 -#define ADXL372_FIFO_DATA (0x42 << 1) -#define ADXL372_LAST (0x42 << 1) +#define ADXL372_FIFO_DATA 0x42 +#define ADXL372_LAST 0x42 #define ADXL372_SCRATCH ADXL372_THRESH_ACT_X_H /* SPI Bus Parameters */ @@ -154,6 +154,8 @@ * Public Types ****************************************************************************/ +#ifndef CONFIG_SENSORS_ADXL372_UORB + /* A reference to a structure of this type must be passed to the ADXL372 * driver. This structure provides information about the configuration * of the sensor and provides some board-specific hooks. @@ -227,6 +229,7 @@ struct adxl372_config_s FAR const struct adxl372_dvr_entry_vector_s *sc_ops; }; +#endif /**************************************************************************** * Public Function Prototypes @@ -258,9 +261,13 @@ extern "C" * ****************************************************************************/ +#ifndef CONFIG_SENSORS_ADXL372_UORB int adxl372_register(FAR const char *devpath, FAR struct spi_dev_s *spi, FAR struct adxl372_config_s *config); +#else +int adxl372_register_uorb(int devno, FAR struct spi_dev_s *spi); +#endif #undef EXTERN #ifdef __cplusplus diff --git a/include/nuttx/sensors/bh1749nuc.h b/include/nuttx/sensors/bh1749nuc.h index 33f559bade834..9892ad885a6de 100644 --- a/include/nuttx/sensors/bh1749nuc.h +++ b/include/nuttx/sensors/bh1749nuc.h @@ -46,6 +46,12 @@ struct bh1749nuc_data_s uint16_t green2; }; +struct bh1749nuc_config_s +{ + FAR struct i2c_master_s *i2c; + uint8_t addr; +}; + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ @@ -75,8 +81,13 @@ extern "C" * ****************************************************************************/ +#ifndef CONFIG_SENSORS_BH1749NUC_UORB int bh1749nuc_register(FAR const char *devpath, FAR struct i2c_master_s *i2c, uint8_t addr); +#else +int bh1749nuc_register_uorb(int devno, + FAR struct bh1749nuc_config_s *config); +#endif #undef EXTERN #ifdef __cplusplus diff --git a/include/nuttx/sensors/bmi160.h b/include/nuttx/sensors/bmi160.h index 22962789191fb..d43c3de448f21 100644 --- a/include/nuttx/sensors/bmi160.h +++ b/include/nuttx/sensors/bmi160.h @@ -30,10 +30,6 @@ #if defined(CONFIG_SENSORS_BMI160) || defined(CONFIG_SENSORS_BMI160_SCU) -#ifdef CONFIG_SENSORS_BMI160_SCU_I2C -#define CONFIG_SENSORS_BMI160_I2C -#endif - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -131,38 +127,18 @@ extern "C" * ****************************************************************************/ -#ifndef CONFIG_SENSORS_BMI160_SCU - -# ifdef CONFIG_SENSORS_BMI160_I2C -# ifdef CONFIG_SENSORS_BMI160_UORB +#ifdef CONFIG_SENSORS_BMI160_I2C +# ifdef CONFIG_SENSORS_BMI160_UORB int bmi160_register_uorb(int devno, FAR struct i2c_master_s *dev); -# else +# else int bmi160_register(FAR const char *devpath, FAR struct i2c_master_s *dev); -# endif /* CONFIG_SENSORS_BMI160_UORB */ -# else /* CONFIG_BMI160_SPI */ -# ifdef CONFIG_SENSORS_BMI160_UORB +# endif /* CONFIG_SENSORS_BMI160_UORB */ +#else /* CONFIG_BMI160_SPI */ +# ifdef CONFIG_SENSORS_BMI160_UORB int bmi160_register_uorb(int devno, FAR struct spi_dev_s *dev); -# else +# else int bmi160_register(FAR const char *devpath, FAR struct spi_dev_s *dev); -# endif /* CONFIG_SENSORS_BMI160_UORB */ -# endif - -#else /* CONFIG_SENSORS_BMI160_SCU */ - -# ifdef CONFIG_SENSORS_BMI160_I2C -int bmi160_init(FAR struct i2c_master_s *dev, int port); -int bmi160gyro_register(FAR const char *devpath, int minor, - FAR struct i2c_master_s *dev, int port); -int bmi160accel_register(FAR const char *devpath, int minor, - FAR struct i2c_master_s *dev, int port); -# else /* CONFIG_SENSORS_BMI160_SPI */ -int bmi160_init(FAR struct spi_dev_s *dev); -int bmi160gyro_register(FAR const char *devpath, int minor, - FAR struct spi_dev_s *dev); -int bmi160accel_register(FAR const char *devpath, int minor, - FAR struct spi_dev_s *dev); -# endif - +# endif /* CONFIG_SENSORS_BMI160_UORB */ #endif #undef EXTERN diff --git a/include/nuttx/sensors/bmi270.h b/include/nuttx/sensors/bmi270.h index 95199556d8a1c..7dee91d68cb1f 100644 --- a/include/nuttx/sensors/bmi270.h +++ b/include/nuttx/sensors/bmi270.h @@ -52,11 +52,14 @@ struct gyro_t struct accel_gyro_st_s { - struct gyro_t gyro; struct accel_t accel; + struct gyro_t gyro; uint32_t sensor_time; }; +struct i2c_master_s; +struct spi_dev_s; + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ @@ -86,12 +89,15 @@ extern "C" * ****************************************************************************/ -#ifdef CONFIG_SENSORS_BMI270_I2C -struct i2c_master_s; +#if defined(CONFIG_SENSORS_BMI270_I2C) && defined(CONFIG_SENSORS_BMI270_UORB) +int bmi270_register_uorb(int devno, FAR struct i2c_master_s *dev, + uint8_t addr); +#elif defined(CONFIG_SENSORS_BMI270_I2C) && !defined(CONFIG_SENSORS_BMI270_UORB) int bmi270_register(FAR const char *devpath, FAR struct i2c_master_s *dev, uint8_t addr); -#else /* CONFIG_BMI270_SPI */ -struct spi_dev_s; +#elif !defined(CONFIG_SENSORS_BMI270_I2C) && defined(CONFIG_SENSORS_BMI270_UORB) +int bmi270_register_uorb(int devno, FAR struct spi_dev_s *dev); +#elif !defined(CONFIG_SENSORS_BMI270_I2C) && !defined(CONFIG_SENSORS_BMI270_UORB) int bmi270_register(FAR const char *devpath, FAR struct spi_dev_s *dev); #endif diff --git a/include/nuttx/sensors/bmm150.h b/include/nuttx/sensors/bmm150.h new file mode 100644 index 0000000000000..7fc3ef7a14e00 --- /dev/null +++ b/include/nuttx/sensors/bmm150.h @@ -0,0 +1,80 @@ +/**************************************************************************** + * include/nuttx/sensors/bmm150.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_SENSORS_BMM150_H +#define __INCLUDE_NUTTX_SENSORS_BMM150_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct bmm150_config_s +{ + FAR struct i2c_master_s *i2c; + uint8_t addr; +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: bmm150_register + * + * Description: + * Register the BMM150 character device as uorb + * + * Input Parameters: + * devno - device instance + * config - device configuratio + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int bmm150_register_uorb(int devno, FAR struct bmm150_config_s *config); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_NUTTX_SENSORS_BMM150_H */ diff --git a/include/nuttx/sensors/lsm9ds1.h b/include/nuttx/sensors/lsm9ds1.h index a5cd2c6c35ccd..44ae703ca2c05 100644 --- a/include/nuttx/sensors/lsm9ds1.h +++ b/include/nuttx/sensors/lsm9ds1.h @@ -57,6 +57,14 @@ struct i2c_master_s; +struct lsm9ds1_config_s +{ + FAR struct i2c_master_s *i2c; + int addr_acc; + int addr_gyro; + int addr_mag; +}; + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ @@ -66,6 +74,8 @@ extern "C" { #endif +#ifndef CONFIG_SENSORS_LSM9DS1_UORB + /**************************************************************************** * Name: lsm9ds1accel_register * @@ -126,6 +136,26 @@ int lsm9ds1mag_register(FAR const char *devpath, FAR struct i2c_master_s *i2c, uint8_t addr); +#else + +/**************************************************************************** + * Name: lsm9ds1_register_uorb + * + * Description: + * Register the LSM9DS1 IMU as sensor device + * + * Input Parameters: + * devno - Instance number for driver + * config - configuratio + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int lsm9ds1_register_uorb(int devno, FAR struct lsm9ds1_config_s *config); +#endif + #ifdef __cplusplus } #endif diff --git a/include/nuttx/sensors/sensor.h b/include/nuttx/sensors/sensor.h index 3aa577a94c5e5..4fd0f385e9f8d 100644 --- a/include/nuttx/sensors/sensor.h +++ b/include/nuttx/sensors/sensor.h @@ -966,7 +966,7 @@ struct sensor_ops_s FAR struct file *filep, unsigned long arg); -/**************************************************************************** + /************************************************************************** * Name: calibrate * * This operation can trigger the calibration operation, and if the diff --git a/include/nuttx/serial/serial.h b/include/nuttx/serial/serial.h index aa7f7ff4dec96..13e5fc28c3b8a 100644 --- a/include/nuttx/serial/serial.h +++ b/include/nuttx/serial/serial.h @@ -88,6 +88,9 @@ #define uart_send(dev,ch) dev->ops->send(dev,ch) #define uart_receive(dev,s) dev->ops->receive(dev,s) +#define uart_release(dev) \ + ((dev)->ops->release ? (dev)->ops->release(dev) : -ENOSYS) + #ifdef CONFIG_SERIAL_TXDMA #define uart_dmasend(dev) \ ((dev)->ops->dmasend ? (dev)->ops->dmasend(dev) : -ENOSYS) @@ -254,6 +257,12 @@ struct uart_ops_s */ CODE bool (*txempty)(FAR struct uart_dev_s *dev); + + /* Call to release some resource about the device when device was close + * and unregistered. + */ + + CODE int (*release)(FAR struct uart_dev_s *dev); }; /* This is the device structure used by the driver. The caller of @@ -276,6 +285,7 @@ struct uart_dev_s volatile bool disconnected; /* true: Removable device is not connected */ #endif bool isconsole; /* true: This is the serial console */ + bool unlinked; /* true: This device driver has been unlinked. */ #if defined(CONFIG_TTY_SIGINT) || defined(CONFIG_TTY_SIGTSTP) || \ defined(CONFIG_TTY_FORCE_PANIC) || defined(CONFIG_TTY_LAUNCH) diff --git a/include/nuttx/serial/uart_cmsdk.h b/include/nuttx/serial/uart_cmsdk.h new file mode 100644 index 0000000000000..c0e6352fd03c0 --- /dev/null +++ b/include/nuttx/serial/uart_cmsdk.h @@ -0,0 +1,113 @@ +/**************************************************************************** + * include/nuttx/serial/uart_cmsdk.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_SERIAL_UART_CMSDK_H +#define __INCLUDE_NUTTX_SERIAL_UART_CMSDK_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets */ + +#define UART_RBR_OFFSET 0 /* Receiver Buffer Register */ +#define UART_THR_OFFSET 0 /* Transmit Holding Register */ +#define UART_STATE_OFFSET 1 /* Interrupt State Register */ +#define UART_CTRL_OFFSET 2 /* Interrupt Control Register */ +#define UART_INTSTS_OFFSET 3 /* Interrupt Status Clear Register */ +#define UART_BAUDDIV_OFFSET 4 /* Baud rate divider Register */ + +/* Register bit definitions */ + +#define UART_STATE_TX_BUF_FULL (1 << 0) +#define UART_STATE_RX_BUF_FULL (1 << 1) +#define UART_STATE_TX_BUF_OVERRUN (1 << 2) +#define UART_STATE_RX_BUF_OVERRUN (1 << 3) + +#define UART_CTRL_TX_ENABLE (1 << 0) +#define UART_CTRL_RX_ENABLE (1 << 1) +#define UART_CTRL_TX_INT_ENABLE (1 << 2) +#define UART_CTRL_RX_INT_ENABLE (1 << 3) +#define UART_CTRL_TX_OVERRUN_INT_ENABLE (1 << 4) +#define UART_CTRL_RX_OVERRUN_INT_ENABLE (1 << 5) +#define UART_CTRL_TSTMODE_ENABLE (1 << 6) +#define UART_CTRL_ALLIE (0x3C) + +#define UART_INTSTATUS_TX (1 << 0) +#define UART_INTSTATUS_RX (1 << 1) +#define UART_INTSTATUS_TX_OVERRUN (1 << 2) +#define UART_INTSTATUS_RX_OVERRUN (1 << 3) + +#define UART_BAUDDIV_MIN (16) +#define UART_BAUDDIV_MAX (0xfffff) + +#if defined(CONFIG_CMSDK_UART0_SERIAL_CONSOLE) && defined(CONFIG_CMSDK_UART0) +# undef CONFIG_CMSDK_UART1_SERIAL_CONSOLE +# undef CONFIG_CMSDK_UART2_SERIAL_CONSOLE +# define HAVE_CMSDK_CONSOLE 1 +#elif defined(CONFIG_CMSDK_UART1_SERIAL_CONSOLE) && defined(CONFIG_CMSDK_UART1) +# undef CONFIG_CMSDK_UART0_SERIAL_CONSOLE +# undef CONFIG_CMSDK_UART2_SERIAL_CONSOLE +# define HAVE_CMSDK_CONSOLE 1 +#elif defined(CONFIG_CMSDK_UART2_SERIAL_CONSOLE) && defined(CONFIG_CMSDK_UART2) +# undef CONFIG_CMSDK_UART0_SERIAL_CONSOLE +# undef CONFIG_CMSDK_UART1_SERIAL_CONSOLE +# define HAVE_CMSDK_CONSOLE 1 +#else +# undef CONFIG_CMSDK_UART0_SERIAL_CONSOLE +# undef CONFIG_CMSDK_UART1_SERIAL_CONSOLE +# undef CONFIG_CMSDK_UART2_SERIAL_CONSOLE +# undef HAVE_CMSDK_CONSOLE +#endif + +/**************************************************************************** + * Public functions prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: cmsdk_earlyserialinit + * + * Description: + * Performs the low level UART initialization early in debug so that the + * serial console will be available during bootup. This must be called + * before uart_serialinit. + * + ****************************************************************************/ + +void cmsdk_earlyserialinit(void); + +/**************************************************************************** + * Name: cmsdk_serialinit + * + * Description: + * Register serial console and serial ports. This assumes that + * up_earlyserialinit was called previously. + * + ****************************************************************************/ + +void cmsdk_serialinit(void); + +#endif /* __INCLUDE_NUTTX_SERIAL_UART_CMSDK_H */ diff --git a/include/nuttx/spi/ice40.h b/include/nuttx/spi/ice40.h new file mode 100644 index 0000000000000..675c2df8ff511 --- /dev/null +++ b/include/nuttx/spi/ice40.h @@ -0,0 +1,93 @@ +/**************************************************************************** + * include/nuttx/spi/ice40.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_SPI_ICE40_H +#define __INCLUDE_NUTTX_SPI_ICE40_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if(defined(CONFIG_SPI) && defined(CONFIG_SPI_ICE40)) + +#ifndef CONFIG_ICE40_SPI_FREQUENCY +# define CONFIG_ICE40_SPI_FREQUENCY 10000000 +#endif + +#define ICE40_SPI_MODE (SPIDEV_MODE0) /* SPI Mode 0: CPOL=0,CPHA=0 */ + +#define ICE40_SPI_FINAL_CLK_CYCLES 160 + +#define ICE_SPI_MAX_XFER 4096 + +#define FPGAIOC_WRITE_INIT _FPGACFGIOC(0x0001) +#define FPGAIOC_WRITE _FPGACFGIOC(0x0002) +#define FPGAIOC_WRITE_COMPLETE _FPGACFGIOC(0x0003) + +/**************************************************************************** + * Public Function Definitions + ****************************************************************************/ + +/**************************************************************************** + * Name: ice40_register + * + * Description: + * Register the ice_v character device as 'devpath'. + * + ****************************************************************************/ + +struct ice40_dev_s; + +struct ice40_ops_s +{ + CODE void(*reset)(FAR struct ice40_dev_s *dev, FAR bool reset); + CODE void(*select)(FAR struct ice40_dev_s *dev, FAR bool select); + CODE bool(*get_status)(FAR struct ice40_dev_s *dev); +}; + +struct ice40_dev_s +{ + FAR const struct ice40_ops_s *ops; + FAR struct spi_dev_s *spi; + bool is_open; + bool in_progress; +}; + +int ice40_register(FAR const char *path, FAR struct ice40_dev_s *dev); + +#endif /* CONFIG_SPI && CONFIG_SPI_ICE40 */ + +#endif /* __INCLUDE_NUTTX_SPI_ICE40_H */ \ No newline at end of file diff --git a/include/nuttx/spi/slave.h b/include/nuttx/spi/slave.h index 02de4e622d1e5..11b7bde8c8256 100644 --- a/include/nuttx/spi/slave.h +++ b/include/nuttx/spi/slave.h @@ -388,8 +388,7 @@ * * 4) When the first word from the master is shifted in, the SPI * controller driver will call the device's receive() method to - * provide the master with the command word that was just shifted - * in. + * provide the master command word that was just shifted in. * * For the case of bi-directional data transfer or of a transfer of * data from the SPI device to the master, the SPI device driver diff --git a/include/nuttx/spinlock.h b/include/nuttx/spinlock.h index 380d550c3a8cc..4fb1e54e1b41d 100644 --- a/include/nuttx/spinlock.h +++ b/include/nuttx/spinlock.h @@ -145,7 +145,7 @@ typedef union spinlock_u spinlock_t; #if defined(CONFIG_ARCH_HAVE_TESTSET) spinlock_t up_testset(FAR volatile spinlock_t *lock); -#elif !defined(CONFIG_SMP) +#else static inline spinlock_t up_testset(FAR volatile spinlock_t *lock) { irqstate_t flags; @@ -361,7 +361,7 @@ void spin_unlock_wo_note(FAR volatile spinlock_t *lock); * ****************************************************************************/ -#ifdef CONFIG_SMP +#ifdef CONFIG_SPINLOCK void spin_setbit(FAR volatile cpu_set_t *set, unsigned int cpu, FAR volatile spinlock_t *setlock, FAR volatile spinlock_t *orlock); @@ -384,7 +384,7 @@ void spin_setbit(FAR volatile cpu_set_t *set, unsigned int cpu, * ****************************************************************************/ -#ifdef CONFIG_SMP +#ifdef CONFIG_SPINLOCK void spin_clrbit(FAR volatile cpu_set_t *set, unsigned int cpu, FAR volatile spinlock_t *setlock, FAR volatile spinlock_t *orlock); @@ -443,7 +443,7 @@ void spin_clrbit(FAR volatile cpu_set_t *set, unsigned int cpu, * ****************************************************************************/ -#if defined(CONFIG_SMP) +#if defined(CONFIG_SPINLOCK) irqstate_t spin_lock_irqsave(FAR spinlock_t *lock); #else # define spin_lock_irqsave(l) ((void)(l), up_irq_save()) @@ -453,7 +453,7 @@ irqstate_t spin_lock_irqsave(FAR spinlock_t *lock); * Name: spin_lock_irqsave_wo_note ****************************************************************************/ -#if defined(CONFIG_SMP) +#if defined(CONFIG_SPINLOCK) irqstate_t spin_lock_irqsave_wo_note(FAR spinlock_t *lock); #else # define spin_lock_irqsave_wo_note(l) ((void)(l), up_irq_save()) @@ -488,7 +488,7 @@ irqstate_t spin_lock_irqsave_wo_note(FAR spinlock_t *lock); * ****************************************************************************/ -#if defined(CONFIG_SMP) +#if defined(CONFIG_SPINLOCK) void spin_unlock_irqrestore(FAR spinlock_t *lock, irqstate_t flags); #else # define spin_unlock_irqrestore(l, f) up_irq_restore(f) @@ -498,7 +498,7 @@ void spin_unlock_irqrestore(FAR spinlock_t *lock, irqstate_t flags); * Name: spin_unlock_irqrestore_wo_note ****************************************************************************/ -#if defined(CONFIG_SMP) +#if defined(CONFIG_SPINLOCK) void spin_unlock_irqrestore_wo_note(FAR spinlock_t *lock, irqstate_t flags); #else # define spin_unlock_irqrestore_wo_note(l, f) up_irq_restore(f) @@ -699,7 +699,7 @@ void write_unlock(FAR volatile rwlock_t *lock); * ****************************************************************************/ -#if defined(CONFIG_SMP) +#if defined(CONFIG_SPINLOCK) irqstate_t read_lock_irqsave(FAR rwlock_t *lock); #else # define read_lock_irqsave(l) ((void)(l), up_irq_save()) @@ -732,7 +732,7 @@ irqstate_t read_lock_irqsave(FAR rwlock_t *lock); * ****************************************************************************/ -#if defined(CONFIG_SMP) +#if defined(CONFIG_SPINLOCK) void read_unlock_irqrestore(FAR rwlock_t *lock, irqstate_t flags); #else # define read_unlock_irqrestore(l, f) up_irq_restore(f) @@ -771,7 +771,7 @@ void read_unlock_irqrestore(FAR rwlock_t *lock, irqstate_t flags); * ****************************************************************************/ -#if defined(CONFIG_SMP) +#if defined(CONFIG_SPINLOCK) irqstate_t write_lock_irqsave(FAR rwlock_t *lock); #else # define write_lock_irqsave(l) ((void)(l), up_irq_save()) @@ -806,7 +806,7 @@ irqstate_t write_lock_irqsave(FAR rwlock_t *lock); * ****************************************************************************/ -#if defined(CONFIG_SMP) +#if defined(CONFIG_SPINLOCK) void write_unlock_irqrestore(FAR rwlock_t *lock, irqstate_t flags); #else # define write_unlock_irqrestore(l, f) up_irq_restore(f) diff --git a/include/nuttx/timers/mcp794xx.h b/include/nuttx/timers/mcp794xx.h index 7b8abf1f9bb56..d75c63356c78e 100644 --- a/include/nuttx/timers/mcp794xx.h +++ b/include/nuttx/timers/mcp794xx.h @@ -41,6 +41,30 @@ extern "C" #define EXTERN extern #endif +/**************************************************************************** + * Name: mcp794xx_rtc_set_trim + * + * Description: + * Sets the digital trimming to correct for inaccuracies of clock source. + * Digital trimming consists of the MCP794XX periodically adding or + * subtracting clock cycles, resulting in small adjustments in the internal + * timing. + * + * Input Parameters: + * trim_val - Calculated trimming value, refer to MCP794XX reference + * manual. + * rtc_slow - True indicates RTC is behind real clock, false otherwise. + * This has to be set to ensure correct trimming direction. + * coarse_mode - MCP794XX allows coarse mode that trims every second + * instead of every minute. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int mcp794xx_rtc_set_trim(uint8_t trim_val, bool rtc_slow, bool coarse_mode); + /**************************************************************************** * Name: mcp794xx_rtc_initialize * diff --git a/include/nuttx/timers/pl031.h b/include/nuttx/timers/pl031.h index 15a5290811965..6f041d4a6e415 100644 --- a/include/nuttx/timers/pl031.h +++ b/include/nuttx/timers/pl031.h @@ -18,8 +18,8 @@ * ****************************************************************************/ -#ifndef __INCLUDE_NUTTX_TIMER_PL031_H -#define __INCLUDE_NUTTX_TIMER_PL031_H +#ifndef __INCLUDE_NUTTX_TIMERS_PL031_H +#define __INCLUDE_NUTTX_TIMERS_PL031_H /**************************************************************************** * Public Function Prototypes @@ -35,4 +35,4 @@ FAR struct rtc_lowerhalf_s *pl031_initialize(uintptr_t base, int irq); -#endif //__INCLUDE_NUTTX_TIMER_PL031_H +#endif /* __INCLUDE_NUTTX_TIMERS_PL031_H */ diff --git a/include/nuttx/timers/pwm.h b/include/nuttx/timers/pwm.h index f6fbdce717379..3e7a7c9812c23 100644 --- a/include/nuttx/timers/pwm.h +++ b/include/nuttx/timers/pwm.h @@ -118,13 +118,26 @@ /* These are helper definitions for setting PWM channel output polarity to * logical low or high level. The pulsed output should start with this - * logical value and should return to it when the output is disabled. + * logical value. + * The output polarity of the PWM's disabled channel does not depend on this + * value, refer to DCPOL instead. */ #define PWM_CPOL_NDEF 0 /* Not defined, default value by arch driver should be used */ #define PWM_CPOL_LOW 1 /* Logical zero */ #define PWM_CPOL_HIGH 2 /* Logical one */ +/* PWM disabled channel polarity ********************************************/ + +/* The output of the PWM disabled channel may depend on the platform + * dependant peripheral. These helper definitions can be used for setting + * the disabled channel's output state. + */ + +#define PWM_DCPOL_NDEF 0 /* Not defined, the default output state is arch dependant */ +#define PWM_DCPOL_LOW 1 /* Logical zero */ +#define PWM_DCPOL_HIGH 2 /* Logical one */ + /**************************************************************************** * Public Types ****************************************************************************/ @@ -146,6 +159,7 @@ struct pwm_chan_s ub16_t dead_time_b; #endif uint8_t cpol; + uint8_t dcpol; int8_t channel; }; #endif @@ -174,6 +188,7 @@ struct pwm_info_s * generate an indefinite number of pulses */ # endif uint8_t cpol; /* Channel polarity */ + uint8_t dcpol; /* Disabled channel polarity */ #endif /* CONFIG_PWM_MULTICHAN */ FAR void *arg; /* User provided argument to be used in the diff --git a/include/nuttx/tls.h b/include/nuttx/tls.h index 8b685a456c892..0d66a6055c1a7 100644 --- a/include/nuttx/tls.h +++ b/include/nuttx/tls.h @@ -27,7 +27,14 @@ #include -#include +#include +#include + +#include +#include + +#include +#include #include #include #include @@ -48,7 +55,6 @@ #endif #ifndef CONFIG_TLS_NELEM -# warning CONFIG_TLS_NELEM is not defined # define CONFIG_TLS_NELEM 0 #endif @@ -116,7 +122,8 @@ struct pthread_atfork_s struct task_info_s { mutex_t ta_lock; - FAR char **argv; /* Name+start-up parameters */ + int ta_argc; /* Number of arguments */ + FAR char **ta_argv; /* Name+start-up parameters */ #if CONFIG_TLS_TASK_NELEM > 0 uintptr_t ta_telem[CONFIG_TLS_TASK_NELEM]; /* Task local storage elements */ #endif diff --git a/include/nuttx/usb/cdc.h b/include/nuttx/usb/cdc.h index 429fc056d3f3e..362c3801fe165 100644 --- a/include/nuttx/usb/cdc.h +++ b/include/nuttx/usb/cdc.h @@ -361,8 +361,8 @@ #define ECMCAP_RVC_OK (1 << 1) /* Frames received without errors */ #define ECMCAP_XMIT_ERROR (1 << 2) /* Frames not transmitted, or transmitted with errors */ #define ECMCAP_RCV_ERROR (1 << 3) /* Frames received with errors that are not delivered - * to the USB host - */ + * to the USB host + */ #define ECMCAP_RCV_NO_BUFFER (1 << 4) /* Frame missed, no buffers */ #define ECMCAP_DIR_BYTES_XMIT (1 << 5) /* Directed bytes transmitted without errors */ #define ECMCAP_DIR_FRAMES_XMIT (1 << 6) /* Directed frames transmitted without errors */ diff --git a/include/nuttx/usb/cdcacm.h b/include/nuttx/usb/cdcacm.h index cda993b697189..98d7d3f8f45aa 100644 --- a/include/nuttx/usb/cdcacm.h +++ b/include/nuttx/usb/cdcacm.h @@ -312,6 +312,8 @@ enum cdcacm_event_e typedef CODE void (*cdcacm_callback_t)(enum cdcacm_event_e event); +struct usbdevclass_driver_s; + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ @@ -336,7 +338,6 @@ typedef CODE void (*cdcacm_callback_t)(enum cdcacm_event_e event); #if defined(CONFIG_USBDEV_COMPOSITE) && defined(CONFIG_CDCACM_COMPOSITE) struct usbdev_devinfo_s; -struct usbdevclass_driver_s; int cdcacm_classobject(int minor, FAR struct usbdev_devinfo_s *devinfo, FAR struct usbdevclass_driver_s **classdev); #endif @@ -378,19 +379,13 @@ int cdcacm_initialize(int minor, FAR void **handle); * standalone USB driver: * * classdev - The class object returned by cdcacm_classobject() - * handle - The opaque handle representing the class object returned by - * a previous call to cdcacm_initialize(). * * Returned Value: * None * ****************************************************************************/ -#if defined(CONFIG_USBDEV_COMPOSITE) && defined(CONFIG_CDCACM_COMPOSITE) void cdcacm_uninitialize(FAR struct usbdevclass_driver_s *classdev); -#else -void cdcacm_uninitialize(FAR void *handle); -#endif /**************************************************************************** * Name: cdcacm_get_composite_devdesc diff --git a/include/nuttx/usb/mtp.h b/include/nuttx/usb/mtp.h index 0e07a88ee7fca..da6a8cda7d41f 100644 --- a/include/nuttx/usb/mtp.h +++ b/include/nuttx/usb/mtp.h @@ -28,6 +28,20 @@ #include #include +/**************************************************************************** + * Preprocessor definitions + ****************************************************************************/ + +/* Indexes for devinfo.epno[] array. + * Used for composite device configuration. + */ + +#define USBMTP_NUM_EPS (3) + +#define USBMTP_EP_BULKIN_IDX (0) +#define USBMTP_EP_BULKOUT_IDX (1) +#define USBMTP_EP_INTIN_IDX (2) + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ diff --git a/include/nuttx/usb/usbdev_trace.h b/include/nuttx/usb/usbdev_trace.h index 9246c44963971..0993af5a0dbbe 100644 --- a/include/nuttx/usb/usbdev_trace.h +++ b/include/nuttx/usb/usbdev_trace.h @@ -187,6 +187,7 @@ #define USBSER_TRACECLASSAPI_TXREADY 0x000b #define USBSER_TRACECLASSAPI_TXEMPTY 0x000c #define USBSER_TRACECLASSAPI_FLOWCONTROL 0x000d +#define USBSER_TRACECLASSAPI_RELEASE 0x000e /* Values of the class error ID used by the USB serial driver */ diff --git a/include/nuttx/usb/usbhost.h b/include/nuttx/usb/usbhost.h index b0bc71e6cdaa3..c5a1110d95cfd 100644 --- a/include/nuttx/usb/usbhost.h +++ b/include/nuttx/usb/usbhost.h @@ -1013,7 +1013,7 @@ const struct usbhost_registry_s * * * Description: * Initialize the USB hub class. This function should be called - * be platform-specific code in order to initialize and register support + * by platform-specific code in order to initialize and register support * for the USB host storage class. * * Input Parameters: @@ -1034,7 +1034,7 @@ int usbhost_hub_initialize(void); * * Description: * Initialize the USB host storage class. This function should be called - * be platform-specific code in order to initialize and register support + * by platform-specific code in order to initialize and register support * for the USB host storage class. * * Input Parameters: @@ -1126,7 +1126,7 @@ void usbhost_msc_notifier_signal(uint8_t event, char sdchar); * * Description: * Initialize the USB host CDC/ACM class. This function should be called - * be platform-specific code in order to initialize and register support + * by platform-specific code in order to initialize and register support * for the USB host CDC/ACM class. * * Input Parameters: @@ -1147,7 +1147,7 @@ int usbhost_cdcacm_initialize(void); * * Description: * Initialize the USB FT232R driver. This function should be called - * be platform-specific code in order to initialize and register support + * by platform-specific code in order to initialize and register support * for the FT232R. * * Input Parameters: @@ -1168,7 +1168,7 @@ int usbhost_ft232r_initialize(void); * * Description: * Initialize the USB storage HID keyboard class driver. This function - * should be called be platform-specific code in order to initialize and + * should be called by platform-specific code in order to initialize and * register support for the USB host HID keyboard class device. * * Input Parameters: @@ -1189,7 +1189,7 @@ int usbhost_kbdinit(void); * * Description: * Initialize the USB storage HID mouse class driver. This function - * should be called be platform-specific code in order to initialize and + * should be called by platform-specific code in order to initialize and * register support for the USB host HID mouse class device. * * Input Parameters: @@ -1210,7 +1210,7 @@ int usbhost_mouse_init(void); * * Description: * Initialize the USB XBox controller driver. This function - * should be called be platform-specific code in order to initialize and + * should be called by platform-specific code in order to initialize and * register support for the USB XBox controller. * * Input Parameters: @@ -1225,12 +1225,33 @@ int usbhost_mouse_init(void); int usbhost_xboxcontroller_init(void); #endif +/**************************************************************************** + * Name: usbhost_bthci_initialize + * + * Description: + * Initialize the USB Bluetooth HCI class driver. This function should be + * called by platform-specific code in order to initialize and register + * support for the USB host class device. + * + * Input Parameters: + * None + * + * Returned Value: + * On success this function will return zero (OK); A negated errno value + * will be returned on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_BTHCI +int usbhost_bthci_initialize(void); +#endif + /**************************************************************************** * Name: usbhost_wlaninit * * Description: * Initialize the USB WLAN class driver. This function should be called - * be platform-specific code in order to initialize and register support + * by platform-specific code in order to initialize and register support * for the USB host class device. * * Input Parameters: diff --git a/include/nuttx/video/fb.h b/include/nuttx/video/fb.h index f247f7375244e..9a3c659599884 100644 --- a/include/nuttx/video/fb.h +++ b/include/nuttx/video/fb.h @@ -29,7 +29,10 @@ #include #include +#include +#include +#include #include /**************************************************************************** @@ -1106,7 +1109,30 @@ int fb_register_device(int display, int plane, * ****************************************************************************/ -int fb_register(int display, int plane); +static inline_function unused_code int fb_register(int display, int plane) +{ + FAR struct fb_vtable_s *vtable; + int ret; + + /* Initialize the frame buffer device. */ + + ret = up_fbinitialize(display); + if (ret < 0) + { + gerr("ERROR: up_fbinitialize() failed for display %d: %d\n", + display, ret); + return ret; + } + + vtable = up_fbgetvplane(display, plane); + if (vtable == NULL) + { + gerr("ERROR: up_fbgetvplane() failed, vplane=%d\n", plane); + return -EINVAL; + } + + return fb_register_device(display, plane, vtable); +} #undef EXTERN #ifdef __cplusplus diff --git a/include/nuttx/video/imgdata.h b/include/nuttx/video/imgdata.h index 03e03f70701dc..5f9af45873b5e 100644 --- a/include/nuttx/video/imgdata.h +++ b/include/nuttx/video/imgdata.h @@ -111,6 +111,14 @@ struct imgdata_ops_s FAR imgdata_capture_t callback, FAR void *arg); CODE int (*stop_capture)(FAR struct imgdata_s *data); + + /* This is a pair of user define frame memory allocation interface. + * If both are NULL, just using system memory operations. + */ + + CODE void *(*alloc)(FAR struct imgdata_s *data, + uint32_t align_size, uint32_t size); + CODE void (*free)(FAR struct imgdata_s *data, void *addr); }; /* Image data private data. This structure only defines the initial fields diff --git a/include/nuttx/video/imgsensor.h b/include/nuttx/video/imgsensor.h index 36fa9baef187b..920516e8a4a5a 100644 --- a/include/nuttx/video/imgsensor.h +++ b/include/nuttx/video/imgsensor.h @@ -34,49 +34,49 @@ /* Camera parameter IDs */ -#define IMGSENSOR_ID_BRIGHTNESS (0x00000000) -#define IMGSENSOR_ID_CONTRAST (0x00000001) -#define IMGSENSOR_ID_SATURATION (0x00000002) -#define IMGSENSOR_ID_HUE (0x00000003) -#define IMGSENSOR_ID_AUTO_WHITE_BALANCE (0x00000004) -#define IMGSENSOR_ID_RED_BALANCE (0x00000005) -#define IMGSENSOR_ID_BLUE_BALANCE (0x00000006) -#define IMGSENSOR_ID_GAMMA (0x00000007) -#define IMGSENSOR_ID_GAMMA_CURVE (0x00000008) -#define IMGSENSOR_ID_EXPOSURE (0x00000009) -#define IMGSENSOR_ID_HFLIP_VIDEO (0x0000000a) -#define IMGSENSOR_ID_VFLIP_VIDEO (0x0000000b) -#define IMGSENSOR_ID_HFLIP_STILL (0x0000000c) -#define IMGSENSOR_ID_VFLIP_STILL (0x0000000d) -#define IMGSENSOR_ID_SHARPNESS (0x0000000e) -#define IMGSENSOR_ID_COLOR_KILLER (0x0000000f) -#define IMGSENSOR_ID_COLORFX (0x00000010) -#define IMGSENSOR_ID_AUTOBRIGHTNESS (0x00000011) -#define IMGSENSOR_ID_ROTATE (0x00000012) -#define IMGSENSOR_ID_EXPOSURE_AUTO (0x00010000) -#define IMGSENSOR_ID_EXPOSURE_ABSOLUTE (0x00010001) -#define IMGSENSOR_ID_FOCUS_ABSOLUTE (0x00010002) -#define IMGSENSOR_ID_FOCUS_RELATIVE (0x00010003) -#define IMGSENSOR_ID_FOCUS_AUTO (0x00010004) -#define IMGSENSOR_ID_ZOOM_ABSOLUTE (0x00010005) -#define IMGSENSOR_ID_ZOOM_RELATIVE (0x00010006) -#define IMGSENSOR_ID_ZOOM_CONTINUOUS (0x00010007) -#define IMGSENSOR_ID_IRIS_ABSOLUTE (0x00010008) -#define IMGSENSOR_ID_IRIS_RELATIVE (0x00010009) -#define IMGSENSOR_ID_AUTO_N_PRESET_WB (0x0001000a) -#define IMGSENSOR_ID_WIDE_DYNAMIC_RANGE (0x0001000b) -#define IMGSENSOR_ID_IMG_STABILIZATION (0x0001000c) -#define IMGSENSOR_ID_ISO_SENSITIVITY (0x0001000d) -#define IMGSENSOR_ID_ISO_SENSITIVITY_AUTO (0x0001000e) -#define IMGSENSOR_ID_EXPOSURE_METERING (0x0001000f) -#define IMGSENSOR_ID_SPOT_POSITION (0x00010016) -#define IMGSENSOR_ID_3A_LOCK (0x00010011) -#define IMGSENSOR_ID_AUTO_FOCUS_START (0x00010012) -#define IMGSENSOR_ID_AUTO_FOCUS_STOP (0x00010013) -#define IMGSENSOR_ID_3A_PARAMETER (0x00010014) -#define IMGSENSOR_ID_3A_STATUS (0x00010015) -#define IMGSENSOR_ID_FLASH_LED_MODE (0x00020000) -#define IMGSENSOR_ID_JPEG_QUALITY (0x00030000) +#define IMGSENSOR_ID_BRIGHTNESS V4L2_CID_BRIGHTNESS +#define IMGSENSOR_ID_CONTRAST V4L2_CID_CONTRAST +#define IMGSENSOR_ID_SATURATION V4L2_CID_SATURATION +#define IMGSENSOR_ID_HUE V4L2_CID_HUE +#define IMGSENSOR_ID_AUTO_WHITE_BALANCE V4L2_CID_AUTO_WHITE_BALANCE +#define IMGSENSOR_ID_RED_BALANCE V4L2_CID_RED_BALANCE +#define IMGSENSOR_ID_BLUE_BALANCE V4L2_CID_BLUE_BALANCE +#define IMGSENSOR_ID_GAMMA V4L2_CID_GAMMA +#define IMGSENSOR_ID_GAMMA_CURVE V4L2_CID_GAMMA_CURVE +#define IMGSENSOR_ID_EXPOSURE V4L2_CID_EXPOSURE +#define IMGSENSOR_ID_HFLIP_VIDEO V4L2_CID_HFLIP +#define IMGSENSOR_ID_VFLIP_VIDEO V4L2_CID_VFLIP +#define IMGSENSOR_ID_HFLIP_STILL V4L2_CID_HFLIP_STILL +#define IMGSENSOR_ID_VFLIP_STILL V4L2_CID_VFLIP_STILL +#define IMGSENSOR_ID_SHARPNESS V4L2_CID_SHARPNESS +#define IMGSENSOR_ID_COLOR_KILLER V4L2_CID_COLOR_KILLER +#define IMGSENSOR_ID_COLORFX V4L2_CID_COLORFX +#define IMGSENSOR_ID_AUTOBRIGHTNESS V4L2_CID_AUTOBRIGHTNESS +#define IMGSENSOR_ID_ROTATE V4L2_CID_ROTATE +#define IMGSENSOR_ID_EXPOSURE_AUTO V4L2_CID_EXPOSURE_AUTO +#define IMGSENSOR_ID_EXPOSURE_ABSOLUTE V4L2_CID_EXPOSURE_ABSOLUTE +#define IMGSENSOR_ID_FOCUS_ABSOLUTE V4L2_CID_FOCUS_ABSOLUTE +#define IMGSENSOR_ID_FOCUS_RELATIVE V4L2_CID_FOCUS_RELATIVE +#define IMGSENSOR_ID_FOCUS_AUTO V4L2_CID_FOCUS_AUTO +#define IMGSENSOR_ID_ZOOM_ABSOLUTE V4L2_CID_ZOOM_ABSOLUTE +#define IMGSENSOR_ID_ZOOM_RELATIVE V4L2_CID_ZOOM_RELATIVE +#define IMGSENSOR_ID_ZOOM_CONTINUOUS V4L2_CID_ZOOM_CONTINUOUS +#define IMGSENSOR_ID_IRIS_ABSOLUTE V4L2_CID_IRIS_ABSOLUTE +#define IMGSENSOR_ID_IRIS_RELATIVE V4L2_CID_IRIS_RELATIVE +#define IMGSENSOR_ID_AUTO_N_PRESET_WB V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE +#define IMGSENSOR_ID_WIDE_DYNAMIC_RANGE V4L2_CID_WIDE_DYNAMIC_RANGE +#define IMGSENSOR_ID_IMG_STABILIZATION V4L2_CID_IMAGE_STABILIZATION +#define IMGSENSOR_ID_ISO_SENSITIVITY V4L2_CID_ISO_SENSITIVITY +#define IMGSENSOR_ID_ISO_SENSITIVITY_AUTO V4L2_CID_ISO_SENSITIVITY_AUTO +#define IMGSENSOR_ID_EXPOSURE_METERING V4L2_CID_EXPOSURE_METERING +#define IMGSENSOR_ID_SPOT_POSITION V4L2_CID_EXPOSURE_METERING_SPOT_POSITION +#define IMGSENSOR_ID_3A_LOCK V4L2_CID_3A_LOCK +#define IMGSENSOR_ID_AUTO_FOCUS_START V4L2_CID_AUTO_FOCUS_START +#define IMGSENSOR_ID_AUTO_FOCUS_STOP V4L2_CID_AUTO_FOCUS_STOP +#define IMGSENSOR_ID_3A_PARAMETER V4L2_CID_3A_PARAMETER +#define IMGSENSOR_ID_3A_STATUS V4L2_CID_3A_STATUS +#define IMGSENSOR_ID_FLASH_LED_MODE V4L2_CID_FLASH_LED_MODE +#define IMGSENSOR_ID_JPEG_QUALITY V4L2_CID_JPEG_COMPRESSION_QUALITY #define IMGSENSOR_ID_CLIP_VIDEO (0xFFFF0000) #define IMGSENSOR_ID_CLIP_STILL (0xFFFF0001) @@ -393,6 +393,12 @@ struct imgsensor_ops_s struct imgsensor_s { FAR const struct imgsensor_ops_s *ops; + size_t fmtdescs_num; + FAR const struct v4l2_fmtdesc *fmtdescs; + size_t frmsizes_num; + FAR const struct v4l2_frmsizeenum *frmsizes; + size_t frmintervals_num; + FAR const struct v4l2_frmivalenum *frmintervals; }; #ifdef __cplusplus diff --git a/include/nuttx/video/mipi_dsi.h b/include/nuttx/video/mipi_dsi.h index dc7eb4a96ceae..56f79c8472098 100644 --- a/include/nuttx/video/mipi_dsi.h +++ b/include/nuttx/video/mipi_dsi.h @@ -50,7 +50,7 @@ #define MIPI_DSI_MSG_REQ_ACK (1 << 0) /* Request ACK from peripheral */ #define MIPI_DSI_MSG_USE_LPM (1 << 1) /* Use Low Power Mode to - * transmit message */ + * transmit message */ #define MIPI_DSI_MSG_AFTER_FRAME (1 << 2) /* Transmit message after frame */ /* Tearing Effect Output Line mode */ diff --git a/include/nuttx/video/v4l2_cap.h b/include/nuttx/video/v4l2_cap.h new file mode 100644 index 0000000000000..ead917eb29b04 --- /dev/null +++ b/include/nuttx/video/v4l2_cap.h @@ -0,0 +1,87 @@ +/**************************************************************************** + * include/nuttx/video/v4l2_cap.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + ****************************************************************************/ + +#ifndef __NUTTX_VIDEO_V4L2_CAP_H +#define __NUTTX_VIDEO_V4L2_CAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/* Initialize capture driver. + * + * param [in] devpath: path to capture device + * + * Return on success, 0 is returned. On failure, + * negative value is returned. + */ + +int capture_initialize(FAR const char *devpath); + +/* Uninitialize capture driver. + * + * Return on success, 0 is returned. On failure, + * negative value is returned. + */ + +int capture_uninitialize(FAR const char *devpath); + +/* New API to register capture driver. + * + * param [in] devpath: path to capture device + * param [in] data: provide imgdata ops + * param [in] sensor: provide imgsensor ops array + * param [in] sensor_num: the number of imgsensor ops array + * + * Return on success, 0 is returned. On failure, + * negative value is returned. + */ + +int capture_register(FAR const char *devpath, + FAR struct imgdata_s *data, + FAR struct imgsensor_s **sensors, + size_t sensor_num); + +/* New API to Unregister capture driver. + * + * param [in] devpath: path to capture device + * + * Return on success, 0 is returned. On failure, + * negative value is returned. + */ + +int capture_unregister(FAR const char *devpath); + +#ifdef __cplusplus +} +#endif + +#endif /* __NUTTX_VIDEO_V4L2_CAP_H */ diff --git a/include/nuttx/video/v4l2_m2m.h b/include/nuttx/video/v4l2_m2m.h new file mode 100644 index 0000000000000..2b3f4767d50b4 --- /dev/null +++ b/include/nuttx/video/v4l2_m2m.h @@ -0,0 +1,307 @@ +/**************************************************************************** + * include/nuttx/video/v4l2_m2m.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_VIDEO_V4L2_M2M_H +#define __INCLUDE_NUTTX_VIDEO_V4L2_M2M_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Method access helper macros */ + +#define CODEC_OPEN(codec, cookie, priv) \ + ((codec)->ops->open ? \ + (codec)->ops->open(cookie, priv) : -ENOTTY) + +#define CODEC_CLOSE(codec, priv) \ + ((codec)->ops->close ? \ + (codec)->ops->close(priv) : -ENOTTY) + +#define CODEC_CAPTURE_STREAMON(codec, priv) \ + ((codec)->ops->capture_streamon ? \ + (codec)->ops->capture_streamon(priv) : -ENOTTY) + +#define CODEC_OUTPUT_STREAMON(codec, priv) \ + ((codec)->ops->output_streamon ? \ + (codec)->ops->output_streamon(priv) : -ENOTTY) + +#define CODEC_CAPTURE_STREAMOFF(codec, priv) \ + ((codec)->ops->capture_streamoff ? \ + (codec)->ops->capture_streamoff(priv) : -ENOTTY) + +#define CODEC_OUTPUT_STREAMOFF(codec, priv) \ + ((codec)->ops->output_streamoff ? \ + (codec)->ops->output_streamoff(priv) : -ENOTTY) + +#define CODEC_CAPTURE_AVAILABLE(codec, priv) \ + ((codec)->ops->capture_available ? \ + (codec)->ops->capture_available(priv) : 0) + +#define CODEC_OUTPUT_AVAILABLE(codec, priv) \ + ((codec)->ops->output_available ? \ + (codec)->ops->output_available(priv) : -ENOTTY) + +#define CODEC_QUERYCAP(codec, priv, cap) \ + ((codec)->ops->querycap ? \ + (codec)->ops->querycap(priv, cap) : -ENOTTY) + +#define CODEC_CAPTURE_ENUM_FMT(codec, priv, fmt) \ + ((codec)->ops->capture_enum_fmt ? \ + (codec)->ops->capture_enum_fmt(priv, fmt) : -ENOTTY) + +#define CODEC_OUTPUT_ENUM_FMT(codec, priv, fmt) \ + ((codec)->ops->output_enum_fmt ? \ + (codec)->ops->output_enum_fmt(priv, fmt) : -ENOTTY) + +#define CODEC_CAPTURE_G_FMT(codec, priv, fmt) \ + ((codec)->ops->capture_g_fmt ? \ + (codec)->ops->capture_g_fmt(priv, fmt) : -ENOTTY) + +#define CODEC_OUTPUT_G_FMT(codec, priv, fmt) \ + ((codec)->ops->output_g_fmt ? \ + (codec)->ops->output_g_fmt(priv, fmt) : -ENOTTY) + +#define CODEC_CAPTURE_S_FMT(codec, priv, fmt) \ + ((codec)->ops->capture_s_fmt ? \ + (codec)->ops->capture_s_fmt(priv, fmt) : -ENOTTY) + +#define CODEC_OUTPUT_S_FMT(codec, priv, fmt) \ + ((codec)->ops->output_s_fmt ? \ + (codec)->ops->output_s_fmt(priv, fmt) : -ENOTTY) + +#define CODEC_CAPTURE_TRY_FMT(codec, priv, fmt) \ + ((codec)->ops->capture_try_fmt ? \ + (codec)->ops->capture_try_fmt(priv, fmt) : -ENOTTY) + +#define CODEC_OUTPUT_TRY_FMT(codec, priv, fmt) \ + ((codec)->ops->output_try_fmt ? \ + (codec)->ops->output_try_fmt(priv, fmt) : -ENOTTY) + +#define CODEC_CAPTURE_G_PARM(codec, priv, parm) \ + ((codec)->ops->capture_g_parm ? \ + (codec)->ops->capture_g_parm(priv, parm) : -ENOTTY) + +#define CODEC_OUTPUT_G_PARM(codec, priv, parm) \ + ((codec)->ops->output_g_parm ? \ + (codec)->ops->output_g_parm(priv, parm) : -ENOTTY) + +#define CODEC_CAPTURE_S_PARM(codec, priv, parm) \ + ((codec)->ops->capture_s_parm ? \ + (codec)->ops->capture_s_parm(priv, parm) : -ENOTTY) + +#define CODEC_OUTPUT_S_PARM(codec, priv, parm) \ + ((codec)->ops->output_s_parm ? \ + (codec)->ops->output_s_parm(priv, parm) : -ENOTTY) + +#define CODEC_G_EXT_CTRLS(codec, priv, ctrls) \ + ((codec)->ops->g_ext_ctrls ? \ + (codec)->ops->g_ext_ctrls(priv, ctrls) : -ENOTTY) + +#define CODEC_S_EXT_CTRLS(codec, priv, ctrls) \ + ((codec)->ops->s_ext_ctrls ? \ + (codec)->ops->s_ext_ctrls(priv, ctrls) : -ENOTTY) + +#define CODEC_CAPTURE_G_SELECTION(codec, priv, clip) \ + ((codec)->ops->capture_g_selection ? \ + (codec)->ops->capture_g_selection(priv, clip) : -ENOTTY) + +#define CODEC_OUTPUT_G_SELECTION(codec, priv, clip) \ + ((codec)->ops->output_g_selection ? \ + (codec)->ops->output_g_selection(priv, clip) : -ENOTTY) + +#define CODEC_CAPTURE_S_SELECTION(codec, priv, clip) \ + ((codec)->ops->capture_s_selection ? \ + (codec)->ops->capture_s_selection(priv, clip) : -ENOTTY) + +#define CODEC_OUTPUT_S_SELECTION(codec, priv, clip) \ + ((codec)->ops->output_s_selection ? \ + (codec)->ops->output_s_selection(priv, clip) : -ENOTTY) + +#define CODEC_CAPTURE_CROPCAP(codec, priv, cropcap) \ + ((codec)->ops->capture_cropcap ? \ + (codec)->ops->capture_cropcap(priv, cropcap) : -ENOTTY) + +#define CODEC_OUTPUT_CROPCAP(codec, priv, cropcap) \ + ((codec)->ops->output_cropcap ? \ + (codec)->ops->output_cropcap(priv, cropcap) : -ENOTTY) + +#define CODEC_DQEVENT(codec, priv, event) \ + ((codec)->ops->dqevent ? \ + (codec)->ops->dqevent(priv, event) : -ENOTTY) + +#define CODEC_SUBSCRIBE_EVENT(codec, priv, sub) \ + ((codec)->ops->subscribe_event ? \ + (codec)->ops->subscribe_event(priv, sub) : -ENOTTY) + +#define CODEC_DECODER_CMD(codec, priv, cmd) \ + ((codec)->ops->decoder_cmd ? \ + (codec)->ops->decoder_cmd(priv, cmd) : -ENOTTY) + +#define CODEC_ENCODER_CMD(codec, priv, cmd) \ + ((codec)->ops->encoder_cmd ? \ + (codec)->ops->encoder_cmd(priv, cmd) : -ENOTTY) + +#define CODEC_CAPTURE_G_BUFSIZE(codec, priv) \ + ((codec)->ops->capture_g_bufsize ? \ + (codec)->ops->capture_g_bufsize(priv) : -ENOTTY) + +#define CODEC_OUTPUT_G_BUFSIZE(codec, priv) \ + ((codec)->ops->output_g_bufsize ? \ + (codec)->ops->output_g_bufsize(priv) : -ENOTTY) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +struct codec_s; +struct codec_ops_s +{ + CODE int (*open)(FAR void *cookie, FAR void **priv); + CODE int (*close)(FAR void *priv); + + CODE int (*capture_streamon)(FAR void *priv); + CODE int (*output_streamon)(FAR void *priv); + CODE int (*capture_streamoff)(FAR void *priv); + CODE int (*output_streamoff)(FAR void *priv); + + CODE int (*capture_available)(FAR void *priv); + CODE int (*output_available)(FAR void *priv); + + /* VIDIOC_QUERYCAP handler */ + + CODE int (*querycap)(FAR void *priv, + FAR struct v4l2_capability *cap); + + /* VIDIOC_ENUM_FMT handlers */ + + CODE int (*capture_enum_fmt)(FAR void *priv, + FAR struct v4l2_fmtdesc *fmt); + + CODE int (*output_enum_fmt)(FAR void *priv, + FAR struct v4l2_fmtdesc *fmt); + + /* VIDIOC_G_FMT handlers */ + + CODE int (*capture_g_fmt)(FAR void *priv, + FAR struct v4l2_format *fmt); + CODE int (*output_g_fmt)(FAR void *priv, + FAR struct v4l2_format *fmt); + + /* VIDIOC_S_FMT handlers */ + + CODE int (*capture_s_fmt)(FAR void *priv, + FAR struct v4l2_format *fmt); + CODE int (*output_s_fmt)(FAR void *priv, + FAR struct v4l2_format *fmt); + + /* VIDIOC_TRY_FMT handlers */ + + CODE int (*capture_try_fmt)(FAR void *priv, + FAR struct v4l2_format *fmt); + CODE int (*output_try_fmt)(FAR void *priv, + FAR struct v4l2_format *fmt); + + /* Buffer handlers */ + + CODE size_t (*capture_g_bufsize)(FAR void *priv); + CODE size_t (*output_g_bufsize)(FAR void *priv); + + /* Stream type-dependent parameter ioctls */ + + CODE int (*capture_g_parm)(FAR void *priv, + FAR struct v4l2_streamparm *parm); + CODE int (*output_g_parm)(FAR void *priv, + FAR struct v4l2_streamparm *parm); + CODE int (*capture_s_parm)(FAR void *priv, + FAR struct v4l2_streamparm *parm); + CODE int (*output_s_parm)(FAR void *priv, + FAR struct v4l2_streamparm *parm); + + /* Control handlers */ + + CODE int (*g_ext_ctrls)(FAR void *priv, + FAR struct v4l2_ext_controls *ctrls); + CODE int (*s_ext_ctrls)(FAR void *priv, + FAR struct v4l2_ext_controls *ctrls); + + /* Crop ioctls */ + + CODE int (*capture_g_selection)(FAR void *priv, + FAR struct v4l2_selection *clip); + CODE int (*output_g_selection)(FAR void *priv, + FAR struct v4l2_selection *clip); + CODE int (*capture_s_selection)(FAR void *priv, + FAR struct v4l2_selection *clip); + CODE int (*output_s_selection)(FAR void *priv, + FAR struct v4l2_selection *clip); + CODE int (*capture_cropcap)(FAR void *priv, + FAR struct v4l2_cropcap *cropcap); + CODE int (*output_cropcap)(FAR void *priv, + FAR struct v4l2_cropcap *cropcap); + + /* Event handlers */ + + CODE int (*subscribe_event)(FAR void *priv, + FAR struct v4l2_event_subscription *sub); + + /* Command handlers */ + + CODE int (*decoder_cmd)(FAR void *priv, + FAR struct v4l2_decoder_cmd *cmd); + CODE int (*encoder_cmd)(FAR void *priv, + FAR struct v4l2_encoder_cmd *cmd); +}; + +struct codec_s +{ + FAR const struct codec_ops_s *ops; +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +int codec_register(FAR const char *devpath, FAR struct codec_s *codec); +int codec_unregister(FAR const char *devpath); +FAR struct v4l2_buffer *codec_output_get_buf(FAR void *cookie); +FAR struct v4l2_buffer *codec_capture_get_buf(FAR void *cookie); +int codec_output_put_buf(FAR void *cookie, FAR struct v4l2_buffer *buf); +int codec_capture_put_buf(FAR void *cookie, FAR struct v4l2_buffer *buf); +int codec_queue_event(FAR void *cookie, FAR struct v4l2_event *evt); + +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_NUTTX_VIDEO_V4L2_M2M_H */ diff --git a/include/nuttx/video/video.h b/include/nuttx/video/video.h index 0b035318dad43..44aa821fdcbcc 100644 --- a/include/nuttx/video/video.h +++ b/include/nuttx/video/video.h @@ -30,6 +30,7 @@ ****************************************************************************/ #include +#include #ifdef __cplusplus extern "C" @@ -56,29 +57,99 @@ extern "C" #define VIDEO_VSIZE_3M (1536) /* 3M vertical size */ /**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -struct imgdata_s; -struct imgsensor_s; - -/* Initialize video driver. - * - * param [in] devpath: path to video device - * - * Return on success, 0 is returned. On failure, - * negative value is returned. - */ +* Public Types +*****************************************************************************/ -int video_initialize(FAR const char *devpath); +struct v4l2_s +{ + FAR const struct v4l2_ops_s *vops; + FAR const struct file_operations *fops; +}; -/* Uninitialize video driver. - * - * Return on success, 0 is returned. On failure, - * negative value is returned. - */ +struct v4l2_ops_s +{ + CODE int (*querycap)(FAR struct file *filep, + FAR struct v4l2_capability *cap); + CODE int (*g_input)(FAR int *num); + CODE int (*enum_input)(FAR struct file *filep, + FAR struct v4l2_input *input); + CODE int (*reqbufs)(FAR struct file *filep, + FAR struct v4l2_requestbuffers *reqbufs); + CODE int (*querybuf)(FAR struct file *filep, + FAR struct v4l2_buffer *buf); + CODE int (*qbuf)(FAR struct file *filep, + FAR struct v4l2_buffer *buf); + CODE int (*dqbuf)(FAR struct file *filep, + FAR struct v4l2_buffer *buf); + CODE int (*cancel_dqbuf)(FAR struct file *filep, + enum v4l2_buf_type type); + CODE int (*g_fmt)(FAR struct file *filep, + FAR struct v4l2_format *fmt); + CODE int (*s_fmt)(FAR struct file *filep, + FAR struct v4l2_format *fmt); + CODE int (*try_fmt)(FAR struct file *filep, + FAR struct v4l2_format *v4l2); + CODE int (*g_parm)(FAR struct file *filep, + FAR struct v4l2_streamparm *parm); + CODE int (*s_parm)(FAR struct file *filep, + FAR struct v4l2_streamparm *parm); + CODE int (*streamon)(FAR struct file *filep, + FAR enum v4l2_buf_type *type); + CODE int (*streamoff)(FAR struct file *filep, + FAR enum v4l2_buf_type *type); + CODE int (*do_halfpush)(FAR struct file *filep, + bool enable); + CODE int (*takepict_start)(FAR struct file *filep, + int32_t capture_num); + CODE int (*takepict_stop)(FAR struct file *filep, + bool halfpush); + CODE int (*s_selection)(FAR struct file *filep, + FAR struct v4l2_selection *clip); + CODE int (*g_selection)(FAR struct file *filep, + FAR struct v4l2_selection *clip); + CODE int (*queryctrl)(FAR struct file *filep, + FAR struct v4l2_queryctrl *ctrl); + CODE int (*query_ext_ctrl)(FAR struct file *filep, + FAR struct v4l2_query_ext_ctrl *ctrl); + CODE int (*querymenu)(FAR struct file *filep, + FAR struct v4l2_querymenu *menu); + CODE int (*g_ctrl)(FAR struct file *filep, + FAR struct v4l2_control *ctrl); + CODE int (*s_ctrl)(FAR struct file *filep, + FAR struct v4l2_control *ctrl); + CODE int (*g_ext_ctrls)(FAR struct file *filep, + FAR struct v4l2_ext_controls *ctrls); + CODE int (*s_ext_ctrls)(FAR struct file *filep, + FAR struct v4l2_ext_controls *ctrls); + CODE int (*query_ext_ctrl_scene)(FAR struct file *filep, + FAR struct v4s_query_ext_ctrl_scene *ctrl); + CODE int (*querymenu_scene)(FAR struct file *filep, + FAR struct v4s_querymenu_scene *menu); + CODE int (*g_ext_ctrls_scene)(FAR struct file *filep, + FAR struct v4s_ext_controls_scene *ctrls); + CODE int (*s_ext_ctrls_scene)(FAR struct file *filep, + FAR struct v4s_ext_controls_scene *ctrls); + CODE int (*enum_fmt)(FAR struct file *filep, + FAR struct v4l2_fmtdesc *f); + CODE int (*enum_frminterval)(FAR struct file *filep, + FAR struct v4l2_frmivalenum *f); + CODE int (*enum_frmsize)(FAR struct file *filep, + FAR struct v4l2_frmsizeenum *f); + CODE int (*cropcap)(FAR struct file *filep, + FAR struct v4l2_cropcap *cropcap); + CODE int (*dqevent)(FAR struct file *filep, + FAR struct v4l2_event *event); + CODE int (*subscribe_event)(FAR struct file *filep, + FAR struct v4l2_event_subscription *sub); + CODE int (*decoder_cmd)(FAR struct file *filep, + FAR struct v4l2_decoder_cmd *cmd); + CODE int (*encoder_cmd)(FAR struct file *filep, + FAR struct v4l2_encoder_cmd *cmd); +}; -int video_uninitialize(FAR const char *devpath); +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ /* New API to register video driver. * @@ -92,9 +163,7 @@ int video_uninitialize(FAR const char *devpath); */ int video_register(FAR const char *devpath, - FAR struct imgdata_s *data, - FAR struct imgsensor_s **sensors, - size_t sensor_num); + FAR struct v4l2_s *ctx); /* New API to Unregister video driver. * diff --git a/include/nuttx/video/video_controls.h b/include/nuttx/video/video_controls.h deleted file mode 100644 index 17324ea4bb9c0..0000000000000 --- a/include/nuttx/video/video_controls.h +++ /dev/null @@ -1,227 +0,0 @@ -/**************************************************************************** - * include/nuttx/video/video_controls.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __INCLUDE_NUTTX_VIDEO_VIDEO_CONTROLS_H -#define __INCLUDE_NUTTX_VIDEO_VIDEO_CONTROLS_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Control classes */ - -#define V4L2_CTRL_CLASS_USER (0x0000) /* Old-style 'user' controls */ -#define V4L2_CTRL_CLASS_CAMERA (0x0001) /* Camera class controls */ -#define V4L2_CTRL_CLASS_FLASH (0x0002) /* Camera flash controls */ -#define V4L2_CTRL_CLASS_JPEG (0x0003) /* JPEG-compression controls */ - -/* User-class control IDs */ - -#define V4L2_CID_BRIGHTNESS (0) /* Brightness */ -#define V4L2_CID_CONTRAST (1) /* Contrast */ -#define V4L2_CID_SATURATION (2) /* Saturation */ -#define V4L2_CID_HUE (3) /* Hue */ -#define V4L2_CID_AUTO_WHITE_BALANCE (4) /* AWB */ -#define V4L2_CID_RED_BALANCE (5) /* Red balance */ -#define V4L2_CID_BLUE_BALANCE (6) /* Blue balance */ -#define V4L2_CID_GAMMA (7) /* Gamma value adjustment */ -#define V4L2_CID_GAMMA_CURVE (8) /* Gamma curve adjustment */ -#define V4L2_CID_EXPOSURE (9) /* Exposure value */ -#define V4L2_CID_HFLIP (10) /* Mirror horizontally(VIDEO) */ -#define V4L2_CID_VFLIP (11) /* Mirror vertically(VIDEO) */ -#define V4L2_CID_HFLIP_STILL (12) /* Mirror horizontally(STILL) */ -#define V4L2_CID_VFLIP_STILL (13) /* Mirror vertically(STILL) */ -#define V4L2_CID_SHARPNESS (14) /* Sharpness */ -#define V4L2_CID_COLOR_KILLER (15) /* Color killer */ -#define V4L2_CID_COLORFX (16) /* Color effect */ - -/* Enumeration for V4L2_CID_COLORFX */ - -enum v4l2_colorfx -{ - V4L2_COLORFX_NONE = 0, /* No effect */ - V4L2_COLORFX_BW = 1, /* Black/white */ - V4L2_COLORFX_SEPIA = 2, /* Sepia */ - V4L2_COLORFX_NEGATIVE = 3, /* Positive/negative inversion */ - V4L2_COLORFX_EMBOSS = 4, /* Emboss */ - V4L2_COLORFX_SKETCH = 5, /* Sketch */ - V4L2_COLORFX_SKY_BLUE = 6, /* Sky blue */ - V4L2_COLORFX_GRASS_GREEN = 7, /* Grass green */ - V4L2_COLORFX_SKIN_WHITEN = 8, /* Skin whiten */ - V4L2_COLORFX_VIVID = 9, /* Vivid */ - V4L2_COLORFX_AQUA = 10, /* Aqua */ - V4L2_COLORFX_ART_FREEZE = 11, /* Art freeze */ - V4L2_COLORFX_SILHOUETTE = 12, /* Silhouette */ - V4L2_COLORFX_SOLARIZATION = 13, /* Solarization */ - V4L2_COLORFX_ANTIQUE = 14, /* Antique */ - V4L2_COLORFX_SET_CBCR = 15, /* Set CbCr */ - V4L2_COLORFX_PASTEL = 16 /* Pastel */ -}; -#define V4L2_CID_AUTOBRIGHTNESS (17) /* Auto brightness */ -#define V4L2_CID_ROTATE (18) /* Rotation */ - -/* Camera class control IDs */ - -#define V4L2_CID_EXPOSURE_AUTO (0) /* Auto exposure */ - -/* Enumeration for V4L2_CID_EXPOSURE_AUTO */ - -enum v4l2_exposure_auto_type -{ - /* Exposure time:auto, iris aperture:auto */ - - V4L2_EXPOSURE_AUTO = 0, - - /* Exposure time:manual, iris aperture:manual */ - - V4L2_EXPOSURE_MANUAL = 1, - - /* Exposure time:manual, iris aperture:auto */ - - V4L2_EXPOSURE_SHUTTER_PRIORITY = 2, - - /* Exposure time:auto, iris aperture:manual */ - - V4L2_EXPOSURE_APERTURE_PRIORITY = 3 -}; -#define V4L2_CID_EXPOSURE_ABSOLUTE (1) /* Exposure time */ - -#define V4L2_CID_FOCUS_ABSOLUTE (2) /* Focus */ -#define V4L2_CID_FOCUS_RELATIVE (3) /* Focus */ -#define V4L2_CID_FOCUS_AUTO (4) /* Auto focus */ - -#define V4L2_CID_ZOOM_ABSOLUTE (5) /* Zoom(absolute) */ -#define V4L2_CID_ZOOM_RELATIVE (6) /* Zoom(relative) */ -#define V4L2_CID_ZOOM_CONTINUOUS (7) /* Continuous zoom */ - -#define V4L2_CID_IRIS_ABSOLUTE (8) /* Iris(absolute) */ -#define V4L2_CID_IRIS_RELATIVE (9) /* Iris(relative) */ - -#define V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE (10) /* Preset white balance */ - -/* Enumeration for V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE */ - -enum v4l2_auto_n_preset_white_balance -{ - V4L2_WHITE_BALANCE_MANUAL = 0, /* Manual */ - V4L2_WHITE_BALANCE_AUTO = 1, /* Automatic */ - V4L2_WHITE_BALANCE_INCANDESCENT = 2, /* Incandescent */ - V4L2_WHITE_BALANCE_FLUORESCENT = 3, /* Fluorescent */ - V4L2_WHITE_BALANCE_FLUORESCENT_H = 4, /* Fluorescent H */ - V4L2_WHITE_BALANCE_HORIZON = 5, /* Horizon */ - V4L2_WHITE_BALANCE_DAYLIGHT = 6, /* Daylight */ - V4L2_WHITE_BALANCE_FLASH = 7, /* Flash */ - V4L2_WHITE_BALANCE_CLOUDY = 8, /* Cloudy */ - V4L2_WHITE_BALANCE_SHADE = 9, /* Shade */ -}; - -#define V4L2_CID_WIDE_DYNAMIC_RANGE (11) /* Wide dynamic range */ -#define V4L2_CID_IMAGE_STABILIZATION (12) /* Image stabilization */ - -#define V4L2_CID_ISO_SENSITIVITY (13) /* ISO sensitivity */ -#define V4L2_CID_ISO_SENSITIVITY_AUTO (14) /* Auto ISO sensitivity */ - -/* Enumeration for V4L2_CID_ISO_SENSITIVITY_AUTO */ - -enum v4l2_iso_sensitivity_auto_type -{ - V4L2_ISO_SENSITIVITY_MANUAL = 0, /* Manual */ - V4L2_ISO_SENSITIVITY_AUTO = 1, /* Automatic */ -}; - -#define V4L2_CID_EXPOSURE_METERING (15) /* Exposure metering */ - -/* Enumeration for V4L2_CID_EXPOSURE_METERING */ - -enum v4l2_exposure_metering -{ - V4L2_EXPOSURE_METERING_AVERAGE = 0, /* Average */ - V4L2_EXPOSURE_METERING_CENTER_WEIGHTED = 1, /* Center weighted */ - V4L2_EXPOSURE_METERING_SPOT = 2, /* Spot */ - V4L2_EXPOSURE_METERING_MATRIX = 3, /* Matrix */ -}; - -#define V4L2_CID_SCENE_MODE (16) /* Scene selection */ - -/* Enumeration for V4L2_CID_SCENE_MODE */ - -enum v4l2_scene_mode -{ - V4L2_SCENE_MODE_NONE = 0, /* No scene */ - V4L2_SCENE_MODE_BACKLIGHT = 1, /* Backlight */ - V4L2_SCENE_MODE_BEACH_SNOW = 2, /* Beach snow */ - V4L2_SCENE_MODE_CANDLE_LIGHT = 3, /* Candle light */ - V4L2_SCENE_MODE_DAWN_DUSK = 4, /* Dawn dask */ - V4L2_SCENE_MODE_FALL_COLORS = 5, /* Fall colors */ - V4L2_SCENE_MODE_FIREWORKS = 6, /* Fire works */ - V4L2_SCENE_MODE_LANDSCAPE = 7, /* Landscape */ - V4L2_SCENE_MODE_NIGHT = 8, /* Night */ - V4L2_SCENE_MODE_PARTY_INDOOR = 9, /* Indoor party */ - V4L2_SCENE_MODE_PORTRAIT = 10, /* Portrait */ - V4L2_SCENE_MODE_SPORTS = 11, /* Sports */ - V4L2_SCENE_MODE_SUNSET = 12, /* Sunset */ - V4L2_SCENE_MODE_TEXT = 13, /* Text */ - V4L2_SCENE_MODE_MAX = 14 /* Max number */ -}; - -#define V4L2_CID_3A_LOCK (17) /* Lock 3A */ -#define V4L2_LOCK_EXPOSURE (1 << 0) /* Exposure bit for - * V4L2_CID_3A_LOCK */ -#define V4L2_LOCK_WHITE_BALANCE (1 << 1) /* White balance bit for - * V4L2_CID_3A_LOCK */ -#define V4L2_LOCK_FOCUS (1 << 2) /* Focus bit for - * V4L2_CID_3A_LOCK */ - -#define V4L2_CID_AUTO_FOCUS_START (18) /* Start single AF */ -#define V4L2_CID_AUTO_FOCUS_STOP (19) /* Stop single AF */ - -#define V4L2_CID_3A_PARAMETER (20) /* 3A parameter */ -#define V4L2_CID_3A_STATUS (21) /* 3A status */ -#define V4L2_3A_STATUS_STABLE (0) /* 3A is stable */ -#define V4L2_3A_STATUS_AE_OPERATING (1 << 0) /* AE is operating */ -#define V4L2_3A_STATUS_AWB_OPERATING (1 << 1) /* AWB is operating */ -#define V4L2_3A_STATUS_AF_OPERATING (1 << 2) /* AF is operating */ - -/* Spot position in spot exposure metering */ - -#define V4L2_CID_EXPOSURE_METERING_SPOT_POSITION (22) - -/* Flash and privacy (indicator) light controls */ - -#define V4L2_CID_FLASH_LED_MODE (0) - -/* Enumeration for V4L2_CID_FLASH_LED_MODE */ - -enum v4l2_flash_led_mode -{ - V4L2_FLASH_LED_MODE_NONE, /* Not use LED */ - V4L2_FLASH_LED_MODE_FLASH, /* Flash mode */ - V4L2_FLASH_LED_MODE_TORCH, /* Torch mode */ -}; - -/* JPEG-class control IDs */ - -#define V4L2_CID_JPEG_COMPRESSION_QUALITY (0) /* JPEG quality */ - -#endif /* __INCLUDE_NUTTX_VIDEO_VIDEO_CONTROLS_H */ diff --git a/include/nuttx/video/vnc.h b/include/nuttx/video/vnc.h index 94111c3233188..42597f5b7add5 100644 --- a/include/nuttx/video/vnc.h +++ b/include/nuttx/video/vnc.h @@ -114,6 +114,42 @@ extern "C" int vnc_fbinitialize(int display, vnc_kbdout_t kbdout, vnc_mouseout_t mouseout, FAR void *arg); +/**************************************************************************** + * Name: vnc_fb_register + * + * Description: + * Register the framebuffer support for the specified display. + * + * Input Parameters: + * display - The display number for the case of boards supporting multiple + * displays or for hardware that supports multiple + * layers (each layer is consider a display). Typically zero. + * + * Returned Value: + * Zero (OK) is returned success; a negated errno value is returned on any + * failure. + * + ****************************************************************************/ + +int vnc_fb_register(int display); + +/**************************************************************************** + * Name: vnc_fb_unregister + * + * Description: + * Unregister the framebuffer support for the specified display. + * + * Input Parameters: + * display - In the case of hardware with multiple displays, this + * specifies the display. Normally this is zero. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void vnc_fb_unregister(int display); + #undef EXTERN #ifdef __cplusplus } diff --git a/include/nuttx/virt/qemu_pci.h b/include/nuttx/virt/qemu_pci.h new file mode 100644 index 0000000000000..6d5568d4635ed --- /dev/null +++ b/include/nuttx/virt/qemu_pci.h @@ -0,0 +1,57 @@ +/**************************************************************************** + * include/nuttx/virt/qemu_pci.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_VIRT_QEMU_PCI_H +#define __INCLUDE_NUTTX_VIRT_QEMU_PCI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#ifdef CONFIG_VIRT_QEMU_PCI_TEST +extern const struct pci_dev_type_s g_pci_type_qemu_pci_test; +#endif + +#ifdef CONFIG_VIRT_QEMU_EDU +extern const struct pci_dev_type_s g_pci_type_qemu_edu; +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_NUTTX_VIRT_QEMU_PCI_H */ diff --git a/include/nuttx/wireless/ieee802154/ieee802154_mac.h b/include/nuttx/wireless/ieee802154/ieee802154_mac.h index 9e2294c37f0bf..35f345ab23878 100644 --- a/include/nuttx/wireless/ieee802154/ieee802154_mac.h +++ b/include/nuttx/wireless/ieee802154/ieee802154_mac.h @@ -219,6 +219,7 @@ #define IEEE802154_MAX_PHY_PACKET_SIZE 127 #define IEEE802154_TURN_AROUND_TIME 12 /* symbol periods*/ +#define IEEE802154_SYMBOL_US 16 /* 16us */ /* IEEE 802.15.4 MAC constants */ @@ -251,6 +252,11 @@ #define IEEE802154_MAX_SIFS_FRAME_SIZE 18 #define IEEE802154_MIN_CAP_LENGTH 440 #define IEEE802154_UNIT_BACKOFF_PERIOD 20 +#define IEEE802154_LIFS_SYMBOLS 40 +#define IEEE802154_SIFS_SYMBOLS 12 +#define IEEE802154_ACKIFS_SYMBOLS 12 +#define IEEE802154_TIMESLOT_US (16 * 60) +#define IEEE802154_ACK_FRAME_SIZE 5 /* ACK length (FCF + Seq + FCS) */ /* IEEE 802.15.4 MAC PIB Attribute Defaults */ @@ -381,6 +387,7 @@ enum ieee802154_attr_e IEEE802154_ATTR_PHY_SYMBOL_DURATION, IEEE802154_ATTR_PHY_FCS_LEN, IEEE802154_ATTR_PHY_REGDUMP, + IEEE802154_ATTR_PHY_TRACEDUMP, /* MAC PIB Attributes */ diff --git a/include/nuttx/wireless/ioctl.h b/include/nuttx/wireless/ioctl.h index 6ffd84e866b1d..6d1614727b9fd 100644 --- a/include/nuttx/wireless/ioctl.h +++ b/include/nuttx/wireless/ioctl.h @@ -51,9 +51,9 @@ #define WLIOC_GETRADIOFREQ _WLCIOC(0x0002) /* arg: Pointer to uint32_t, */ /* frequency value (in MHz) */ #define WLIOC_SETADDR _WLCIOC(0x0003) /* arg: Pointer to address value, format - * of the address is driver specific */ + * of the address is driver specific */ #define WLIOC_GETADDR _WLCIOC(0x0004) /* arg: Pointer to address value, format - * of the address is driver specific */ + * of the address is driver specific */ #define WLIOC_SETTXPOWER _WLCIOC(0x0005) /* arg: Pointer to int32_t, */ /* output power (in dBm) */ #define WLIOC_GETTXPOWER _WLCIOC(0x0006) /* arg: Pointer to int32_t, */ diff --git a/include/nuttx/wireless/lte/lte_ioctl.h b/include/nuttx/wireless/lte/lte_ioctl.h index 457d531d3f388..d350a02af6e39 100644 --- a/include/nuttx/wireless/lte/lte_ioctl.h +++ b/include/nuttx/wireless/lte/lte_ioctl.h @@ -158,6 +158,7 @@ #define LTE_CMDID_SETCTXCB _CMDGRP_NOMDM(0x40) #define LTE_CMDID_COUNTWLOCK _CMDGRP_POWER(0x41) #define LTE_CMDID_REPEVT_DUMMY _CMDGRP_EVENT(0x42) +#define LTE_CMDID_RESTARTAPI _CMDGRP_NORMAL(0x43) #define LTE_CMDID_ACCEPT _CMDGRP_NORMAL(0x50) #define LTE_CMDID_BIND _CMDGRP_NORMAL(0x51) diff --git a/include/sched.h b/include/sched.h index 968268db4d661..9804e46a413f6 100644 --- a/include/sched.h +++ b/include/sched.h @@ -113,7 +113,7 @@ /* int CPU_EQUAL(FAR const cpu_set_t *set1, FAR const cpu_set_t *set2); */ -# define CPU_EQUAL(s1,s2) (*(s2) == *(s2)) +# define CPU_EQUAL(s1,s2) (*(s1) == *(s2)) /* REVISIT: Variably sized CPU sets are not supported */ @@ -254,6 +254,9 @@ int sched_getaffinity(pid_t pid, size_t cpusetsize, FAR cpu_set_t *mask); int sched_cpucount(FAR const cpu_set_t *set); int sched_getcpu(void); #else +# define sched_setaffinity(p, c, m) 0 +# define sched_getaffinity(p, c, m) (*(m) |= (1 << 0), 0) +# define sched_cpucount(s) 1 # define sched_getcpu() 0 #endif /* CONFIG_SMP */ diff --git a/include/search.h b/include/search.h new file mode 100644 index 0000000000000..20fa93fbd3bba --- /dev/null +++ b/include/search.h @@ -0,0 +1,163 @@ +/**************************************************************************** + * include/search.h + * + * $NetBSD: search.h,v 1.12 1999/02/22 10:34:28 christos Exp $ + * $FreeBSD: src/include/search.h,v 1.4 2002/03/23 17:24:53 imp Exp $ + * + * Written by J.T. Conklin + * Public domain. + * + ****************************************************************************/ + +#ifndef __INCLUDE_SEARCH_H +#define __INCLUDE_SEARCH_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Type Definitions + ****************************************************************************/ + +typedef struct entry +{ + FAR char *key; + FAR void *data; +} ENTRY; + +typedef enum +{ + FIND, + ENTER, + DELETE +} ACTION; + +struct hsearch_data +{ + FAR struct internal_head *htable; + size_t htablesize; +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: hcreate + * + * Description: + * The hcreate() function creates a new hashing table with nel elements. + * The hashing table will be used by subsequent calls to hsearch() with + * the same htab argument. The hashing table is initialized with nel + * hashing buckets. + * + * The hcreate_r() function is the reentrant version of hcreate(). + * + * Returned Value: + * If successful, hcreate() and hcreate_r() return 1; otherwise, they + * return 0. + * + ****************************************************************************/ + +int hcreate(size_t); + +/**************************************************************************** + * Name: hdestroy + * + * Description: + * The hdestroy() function destroys the hashing table specified by htab. + * The hashing table is destroyed only if there are no entries in the + * table. The hashing table cannot be used again until hcreate() or + * hcreate_r() is called. + * + * The hdestroy_r() function is the reentrant version of hdestroy(). + * + * Returned Value: + * None + * + ****************************************************************************/ + +void hdestroy(void); + +/**************************************************************************** + * Name: hsearch + * + * Description: + * The hsearch() function searches the hashing table specified by htab + * for an entry with a key matching that of item. If such an entry is + * found, hsearch() returns a pointer to the entry's data object. If + * such an entry is not found, hsearch() creates a new entry using the + * key and data objects specified by item and returns a pointer to the + * new entry's data object. + * + * The hsearch_r() function is the reentrant version of hsearch(). + * + * Returned Value: + * If successful, hsearch() and hsearch_r() return a pointer to the data + * object of the matching or newly created entry. Otherwise, they return + * NULL. + * + ****************************************************************************/ + +FAR ENTRY *hsearch(ENTRY, ACTION); + +/**************************************************************************** + * Name: hcreate_r + * + * Description: + * Create a new hash table. + * + * Input Parameters: + * nel - The number of elements in the hash table. + * htab - The location to return the hash table reference. + * + * Returned Value: + * 1 on success; 0 on failure with errno set appropriately. + * + ****************************************************************************/ + +int hcreate_r(size_t, FAR struct hsearch_data *); + +/**************************************************************************** + * Name: hdestroy_r + * + * Description: + * Destroy a hash table. + * + * Input Parameters: + * htab - The hash table to be destroyed. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void hdestroy_r(FAR struct hsearch_data *); + +/**************************************************************************** + * Name: hsearch_r + * + * Description: + * Search a hash table. + * + * Input Parameters: + * item - The search key. + * action - The action to take. + * result - The location to return the search result. + * htab - The hash table to be searched. + * + * Returned Value: + * 1 on success; 0 on failure with errno set appropriately. + * + ****************************************************************************/ + +int hsearch_r(ENTRY, ACTION, FAR ENTRY **, FAR struct hsearch_data *); + +#endif /* __INCLUDE_SEARCH_H */ diff --git a/include/stdlib.h b/include/stdlib.h index b29e59a5bd099..eefce6b57107a 100644 --- a/include/stdlib.h +++ b/include/stdlib.h @@ -233,6 +233,7 @@ FAR void *malloc(size_t) malloc_like1(1); FAR void *valloc(size_t) malloc_like1(1); void free(FAR void *); FAR void *realloc(FAR void *, size_t) realloc_like(2); +FAR void *reallocarray(FAR void *, size_t, size_t) realloc_like2(2, 3); FAR void *memalign(size_t, size_t) malloc_like1(2); FAR void *zalloc(size_t) malloc_like1(1); FAR void *calloc(size_t, size_t) malloc_like2(1, 2); diff --git a/include/strings.h b/include/strings.h index 6a91d7cb3b026..cde41afa84794 100644 --- a/include/strings.h +++ b/include/strings.h @@ -49,10 +49,6 @@ #define bcopy(b1,b2,len) memmove(b2,b1,len) #endif -#ifndef bzero /* See mm/README.txt */ -#define bzero(s,n) memset(s,0,n) -#endif - #define strcasecmp_l(s1, s2, l) strcasecmp(s1, s2) #define strncasecmp_l(s1, s2, n, l) strncasecmp(s1, s2, n) @@ -73,16 +69,77 @@ extern "C" * Public Function Prototypes ****************************************************************************/ +#ifdef CONFIG_HAVE_BUILTIN_FFS +static inline_function int ffs(int j) +{ + return __builtin_ffs(j); +} +#elif defined (CONFIG_HAVE_BUILTIN_CTZ) +static inline_function int ffs(int j) +{ + return __builtin_ctz(j) + 1; +} +#else int ffs(int j); +#endif + +#ifdef CONFIG_HAVE_BUILTIN_FFSL +static inline_function int ffsl(long j) +{ + return __builtin_ffsl(j); +} +#elif defined (CONFIG_HAVE_BUILTIN_CTZ) +static inline_function int ffsl(long j) +{ + return __builtin_ctzl(j) + 1; +} +#else int ffsl(long j); +#endif + #ifdef CONFIG_HAVE_LONG_LONG +# ifdef CONFIG_HAVE_BUILTIN_FFSLL +static inline_function int ffsll(long long j) +{ + return __builtin_ffsll(j); +} +# elif defined (CONFIG_HAVE_BUILTIN_CTZ) +static inline_function int ffsll(long long j) +{ + return __builtin_ctzll(j) + 1; +} +# else int ffsll(long long j); +# endif #endif +#ifdef CONFIG_HAVE_BUILTIN_CLZ +static inline_function int fls(int j) +{ + return (8 * sizeof(int)) - __builtin_clz(j); +} +#else int fls(int j); +#endif + +#ifdef CONFIG_HAVE_BUILTIN_CLZ +static inline_function int flsl(long j) +{ + return (8 * sizeof(long)) - __builtin_clzl(j); +} +#else int flsl(long j); +#endif + #ifdef CONFIG_HAVE_LONG_LONG +# ifdef CONFIG_HAVE_BUILTIN_CLZ +static inline_function int flsll(long long j) +{ + return (8 * sizeof(long long)) - __builtin_clzll(j); +} +# else int flsll(long long j); +# endif #endif unsigned int popcount(unsigned int j); @@ -95,11 +152,13 @@ FAR char *rindex(FAR const char *s, int c); int strcasecmp(FAR const char *, FAR const char *); int strncasecmp(FAR const char *, FAR const char *, size_t); +void bzero(FAR void *s, size_t n); + #if CONFIG_FORTIFY_SOURCE > 0 fortify_function(bzero) void bzero(FAR void *s, size_t n) { fortify_assert(n <= fortify_size(s, 0)); - return bzero(s, n); + return __real_bzero(s, n); } #endif diff --git a/include/sys/boardctl.h b/include/sys/boardctl.h index 9e70770091421..25ac632a0556b 100644 --- a/include/sys/boardctl.h +++ b/include/sys/boardctl.h @@ -209,6 +209,7 @@ #define BOARDIOC_SWITCH_BOOT _BOARDIOC(0x0013) #define BOARDIOC_BOOT_IMAGE _BOARDIOC(0x0014) #define BOARDIOC_RESET_CAUSE _BOARDIOC(0x0015) +#define BOARDIOC_IRQ_AFFINITY _BOARDIOC(0x0016) /* If CONFIG_BOARDCTL_IOCTL=y, then board-specific commands will be support. * In this case, all commands not recognized by boardctl() will be forwarded @@ -217,7 +218,7 @@ * User defined board commands may begin with this value: */ -#define BOARDIOC_USER _BOARDIOC(0x0016) +#define BOARDIOC_USER _BOARDIOC(0x0017) /**************************************************************************** * Public Type Definitions diff --git a/include/sys/socket.h b/include/sys/socket.h index 05b13bdaafb59..d723dfccae55f 100644 --- a/include/sys/socket.h +++ b/include/sys/socket.h @@ -288,6 +288,7 @@ #define SCM_RIGHTS 0x01 /* rw: access rights (array of int) */ #define SCM_CREDENTIALS 0x02 /* rw: struct ucred */ #define SCM_SECURITY 0x03 /* rw: security label */ +#define SCM_TIMESTAMP SO_TIMESTAMP /* Desired design of maximum size and alignment (see RFC2553) */ diff --git a/include/sys/types.h b/include/sys/types.h index e2b0745ce686f..a87827b5f199b 100644 --- a/include/sys/types.h +++ b/include/sys/types.h @@ -249,7 +249,7 @@ typedef uint16_t sa_family_t; #ifdef CONFIG_SYSTEM_TIME64 typedef uint64_t clock_t; -typedef int64_t time_t; /* Holds time in seconds */ +typedef uint64_t time_t; /* Holds time in seconds */ #else typedef uint32_t clock_t; typedef uint32_t time_t; /* Holds time in seconds */ @@ -268,11 +268,7 @@ typedef int32_t suseconds_t; /* This is the smallest integer type that will hold a bitset of all CPUs */ -#if (CONFIG_SMP_NCPUS <= 8) -typedef volatile uint8_t cpu_set_t; -#elif (CONFIG_SMP_NCPUS <= 16) -typedef volatile uint16_t cpu_set_t; -#elif (CONFIG_SMP_NCPUS <= 32) +#if (CONFIG_SMP_NCPUS <= 32) typedef volatile uint32_t cpu_set_t; #else # error SMP: Extensions needed to support this number of CPUs diff --git a/include/sys/video_controls.h b/include/sys/video_controls.h new file mode 100644 index 0000000000000..ebba6c2aa505e --- /dev/null +++ b/include/sys/video_controls.h @@ -0,0 +1,620 @@ +/**************************************************************************** + * include/sys/video_controls.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_SYS_VIDEO_CONTROLS_H +#define __INCLUDE_SYS_VIDEO_CONTROLS_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Control classes */ + +#define V4L2_CTRL_CLASS_USER (0x0100) /* Old-style 'user' controls */ +#define V4L2_CTRL_CLASS_CAMERA (0x0200) /* Camera class controls */ +#define V4L2_CTRL_CLASS_FLASH (0x0300) /* Camera flash controls */ +#define V4L2_CTRL_CLASS_JPEG (0x0400) /* JPEG-compression controls */ +#define V4L2_CTRL_CLASS_CODEC (0x0500) /* Stateful codec controls */ + +#define V4L2_CTRL_CLASS_MPEG V4L2_CTRL_CLASS_CODEC + +#define USER_CID(v) (V4L2_CTRL_CLASS_USER + (v)) +#define CAMERA_CID(v) (V4L2_CTRL_CLASS_CAMERA + (v)) +#define FLASH_CID(v) (V4L2_CTRL_CLASS_FLASH + (v)) +#define JPEG_CID(v) (V4L2_CTRL_CLASS_JPEG + (v)) + +/* User-class control IDs */ + +#define V4L2_CID_BRIGHTNESS USER_CID(0) /* Brightness */ +#define V4L2_CID_CONTRAST USER_CID(1) /* Contrast */ +#define V4L2_CID_SATURATION USER_CID(2) /* Saturation */ +#define V4L2_CID_HUE USER_CID(3) /* Hue */ +#define V4L2_CID_AUTO_WHITE_BALANCE USER_CID(4) /* AWB */ +#define V4L2_CID_RED_BALANCE USER_CID(5) /* Red balance */ +#define V4L2_CID_BLUE_BALANCE USER_CID(6) /* Blue balance */ +#define V4L2_CID_GAMMA USER_CID(7) /* Gamma value adjustment */ +#define V4L2_CID_GAMMA_CURVE USER_CID(8) /* Gamma curve adjustment */ +#define V4L2_CID_EXPOSURE USER_CID(9) /* Exposure value */ + +/* Mirror horizontally(VIDEO) */ + +#define V4L2_CID_HFLIP USER_CID(10) + +/* Mirror vertically(VIDEO) */ + +#define V4L2_CID_VFLIP USER_CID(11) + +/* Mirror horizontally(STILL) */ + +#define V4L2_CID_HFLIP_STILL USER_CID(12) + +/* Mirror vertically(STILL) */ + +#define V4L2_CID_VFLIP_STILL USER_CID(13) +#define V4L2_CID_SHARPNESS USER_CID(14) /* Sharpness */ +#define V4L2_CID_COLOR_KILLER USER_CID(15) /* Color killer */ +#define V4L2_CID_COLORFX USER_CID(16) /* Color effect */ + +/* Enumeration for V4L2_CID_COLORFX */ + +enum v4l2_colorfx +{ + V4L2_COLORFX_NONE = 0, /* No effect */ + V4L2_COLORFX_BW = 1, /* Black/white */ + V4L2_COLORFX_SEPIA = 2, /* Sepia */ + V4L2_COLORFX_NEGATIVE = 3, /* Positive/negative inversion */ + V4L2_COLORFX_EMBOSS = 4, /* Emboss */ + V4L2_COLORFX_SKETCH = 5, /* Sketch */ + V4L2_COLORFX_SKY_BLUE = 6, /* Sky blue */ + V4L2_COLORFX_GRASS_GREEN = 7, /* Grass green */ + V4L2_COLORFX_SKIN_WHITEN = 8, /* Skin whiten */ + V4L2_COLORFX_VIVID = 9, /* Vivid */ + V4L2_COLORFX_AQUA = 10, /* Aqua */ + V4L2_COLORFX_ART_FREEZE = 11, /* Art freeze */ + V4L2_COLORFX_SILHOUETTE = 12, /* Silhouette */ + V4L2_COLORFX_SOLARIZATION = 13, /* Solarization */ + V4L2_COLORFX_ANTIQUE = 14, /* Antique */ + V4L2_COLORFX_SET_CBCR = 15, /* Set CbCr */ + V4L2_COLORFX_PASTEL = 16 /* Pastel */ +}; + +#define V4L2_CID_AUTOBRIGHTNESS USER_CID(17) /* Auto brightness */ +#define V4L2_CID_ROTATE USER_CID(18) /* Rotation */ + +/* Camera class control IDs */ + +#define V4L2_CID_EXPOSURE_AUTO CAMERA_CID(0) /* Auto exposure */ + +/* Enumeration for V4L2_CID_EXPOSURE_AUTO */ + +enum v4l2_exposure_auto_type +{ + /* Exposure time:auto, iris aperture:auto */ + + V4L2_EXPOSURE_AUTO = 0, + + /* Exposure time:manual, iris aperture:manual */ + + V4L2_EXPOSURE_MANUAL = 1, + + /* Exposure time:manual, iris aperture:auto */ + + V4L2_EXPOSURE_SHUTTER_PRIORITY = 2, + + /* Exposure time:auto, iris aperture:manual */ + + V4L2_EXPOSURE_APERTURE_PRIORITY = 3 +}; + +#define V4L2_CID_EXPOSURE_ABSOLUTE CAMERA_CID(1) /* Exposure time */ + +#define V4L2_CID_FOCUS_ABSOLUTE CAMERA_CID(2) /* Focus */ +#define V4L2_CID_FOCUS_RELATIVE CAMERA_CID(3) /* Focus */ +#define V4L2_CID_FOCUS_AUTO CAMERA_CID(4) /* Auto focus */ + +#define V4L2_CID_ZOOM_ABSOLUTE CAMERA_CID(5) /* Zoom(absolute) */ +#define V4L2_CID_ZOOM_RELATIVE CAMERA_CID(6) /* Zoom(relative) */ +#define V4L2_CID_ZOOM_CONTINUOUS CAMERA_CID(7) /* Continuous zoom */ + +#define V4L2_CID_IRIS_ABSOLUTE CAMERA_CID(8) /* Iris(absolute) */ +#define V4L2_CID_IRIS_RELATIVE CAMERA_CID(9) /* Iris(relative) */ + +/* Preset white balance */ + +#define V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE CAMERA_CID(10) + +/* Enumeration for V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE */ + +enum v4l2_auto_n_preset_white_balance +{ + V4L2_WHITE_BALANCE_MANUAL = 0, /* Manual */ + V4L2_WHITE_BALANCE_AUTO = 1, /* Automatic */ + V4L2_WHITE_BALANCE_INCANDESCENT = 2, /* Incandescent */ + V4L2_WHITE_BALANCE_FLUORESCENT = 3, /* Fluorescent */ + V4L2_WHITE_BALANCE_FLUORESCENT_H = 4, /* Fluorescent H */ + V4L2_WHITE_BALANCE_HORIZON = 5, /* Horizon */ + V4L2_WHITE_BALANCE_DAYLIGHT = 6, /* Daylight */ + V4L2_WHITE_BALANCE_FLASH = 7, /* Flash */ + V4L2_WHITE_BALANCE_CLOUDY = 8, /* Cloudy */ + V4L2_WHITE_BALANCE_SHADE = 9, /* Shade */ +}; + +#define V4L2_CID_WIDE_DYNAMIC_RANGE CAMERA_CID(11) /* Wide dynamic range */ + +/* Image stabilization */ + +#define V4L2_CID_IMAGE_STABILIZATION CAMERA_CID(12) +#define V4L2_CID_ISO_SENSITIVITY CAMERA_CID(13) /* ISO sensitivity */ + +/* Auto ISO sensitivity */ + +#define V4L2_CID_ISO_SENSITIVITY_AUTO CAMERA_CID(14) + +/* Enumeration for V4L2_CID_ISO_SENSITIVITY_AUTO */ + +enum v4l2_iso_sensitivity_auto_type +{ + V4L2_ISO_SENSITIVITY_MANUAL = 0, /* Manual */ + V4L2_ISO_SENSITIVITY_AUTO = 1, /* Automatic */ +}; + +#define V4L2_CID_EXPOSURE_METERING CAMERA_CID(15) /* Exposure metering */ + +/* Enumeration for V4L2_CID_EXPOSURE_METERING */ + +enum v4l2_exposure_metering +{ + V4L2_EXPOSURE_METERING_AVERAGE = 0, /* Average */ + V4L2_EXPOSURE_METERING_CENTER_WEIGHTED = 1, /* Center weighted */ + V4L2_EXPOSURE_METERING_SPOT = 2, /* Spot */ + V4L2_EXPOSURE_METERING_MATRIX = 3, /* Matrix */ +}; + +#define V4L2_CID_SCENE_MODE CAMERA_CID(16) /* Scene selection */ + +/* Enumeration for V4L2_CID_SCENE_MODE */ + +enum v4l2_scene_mode +{ + V4L2_SCENE_MODE_NONE = 0, /* No scene */ + V4L2_SCENE_MODE_BACKLIGHT = 1, /* Backlight */ + V4L2_SCENE_MODE_BEACH_SNOW = 2, /* Beach snow */ + V4L2_SCENE_MODE_CANDLE_LIGHT = 3, /* Candle light */ + V4L2_SCENE_MODE_DAWN_DUSK = 4, /* Dawn dask */ + V4L2_SCENE_MODE_FALL_COLORS = 5, /* Fall colors */ + V4L2_SCENE_MODE_FIREWORKS = 6, /* Fire works */ + V4L2_SCENE_MODE_LANDSCAPE = 7, /* Landscape */ + V4L2_SCENE_MODE_NIGHT = 8, /* Night */ + V4L2_SCENE_MODE_PARTY_INDOOR = 9, /* Indoor party */ + V4L2_SCENE_MODE_PORTRAIT = 10, /* Portrait */ + V4L2_SCENE_MODE_SPORTS = 11, /* Sports */ + V4L2_SCENE_MODE_SUNSET = 12, /* Sunset */ + V4L2_SCENE_MODE_TEXT = 13, /* Text */ + V4L2_SCENE_MODE_MAX = 14 /* Max number */ +}; + +#define V4L2_CID_3A_LOCK CAMERA_CID(17) /* Lock 3A */ +#define V4L2_LOCK_EXPOSURE (1 << 0) /* Exposure bit for + * V4L2_CID_3A_LOCK */ +#define V4L2_LOCK_WHITE_BALANCE (1 << 1) /* White balance bit for + * V4L2_CID_3A_LOCK */ +#define V4L2_LOCK_FOCUS (1 << 2) /* Focus bit for + * V4L2_CID_3A_LOCK */ + +#define V4L2_CID_AUTO_FOCUS_START CAMERA_CID(18) /* Start single AF */ +#define V4L2_CID_AUTO_FOCUS_STOP CAMERA_CID(19) /* Stop single AF */ + +#define V4L2_CID_3A_PARAMETER CAMERA_CID(20) /* 3A parameter */ +#define V4L2_CID_3A_STATUS CAMERA_CID(21) /* 3A status */ +#define V4L2_3A_STATUS_STABLE (0) /* 3A is stable */ +#define V4L2_3A_STATUS_AE_OPERATING (1 << 0) /* AE is operating */ +#define V4L2_3A_STATUS_AWB_OPERATING (1 << 1) /* AWB is operating */ +#define V4L2_3A_STATUS_AF_OPERATING (1 << 2) /* AF is operating */ + +/* Spot position in spot exposure metering */ + +#define V4L2_CID_EXPOSURE_METERING_SPOT_POSITION CAMERA_CID(22) + +/* Flash and privacy (indicator) light controls */ + +#define V4L2_CID_FLASH_LED_MODE FLASH_CID(0) + +/* Enumeration for V4L2_CID_FLASH_LED_MODE */ + +enum v4l2_flash_led_mode +{ + V4L2_FLASH_LED_MODE_NONE, /* Not use LED */ + V4L2_FLASH_LED_MODE_FLASH, /* Flash mode */ + V4L2_FLASH_LED_MODE_TORCH, /* Torch mode */ +}; + +/* JPEG-class control IDs */ + +#define V4L2_CID_JPEG_COMPRESSION_QUALITY JPEG_CID(0) /* JPEG quality */ + +/* MPEG-class control IDs */ + +/* The MPEG controls are applicable to all codec controls + * and the 'MPEG' part of the define is historical + */ + +#define V4L2_CID_CODEC_BASE (V4L2_CTRL_CLASS_CODEC | 0x900) +#define V4L2_CID_CODEC_CLASS (V4L2_CTRL_CLASS_CODEC | 1) + +/* MPEG video controls specific to multiplexed streams */ + +#define V4L2_CID_MPEG_VIDEO_ENCODING (V4L2_CID_CODEC_BASE + 200) + +enum v4l2_mpeg_video_encoding +{ + V4L2_MPEG_VIDEO_ENCODING_MPEG_1 = 0, + V4L2_MPEG_VIDEO_ENCODING_MPEG_2 = 1, + V4L2_MPEG_VIDEO_ENCODING_MPEG_4_AVC = 2, +}; + +#define V4L2_CID_MPEG_VIDEO_ASPECT (V4L2_CID_CODEC_BASE + 201) + +enum v4l2_mpeg_video_aspect +{ + V4L2_MPEG_VIDEO_ASPECT_1x1 = 0, + V4L2_MPEG_VIDEO_ASPECT_4x3 = 1, + V4L2_MPEG_VIDEO_ASPECT_16x9 = 2, + V4L2_MPEG_VIDEO_ASPECT_221x100 = 3, +}; + +#define V4L2_CID_MPEG_VIDEO_B_FRAMES (V4L2_CID_CODEC_BASE + 202) +#define V4L2_CID_MPEG_VIDEO_GOP_SIZE (V4L2_CID_CODEC_BASE + 203) +#define V4L2_CID_MPEG_VIDEO_GOP_CLOSURE (V4L2_CID_CODEC_BASE + 204) +#define V4L2_CID_MPEG_VIDEO_PULLDOWN (V4L2_CID_CODEC_BASE + 205) +#define V4L2_CID_MPEG_VIDEO_BITRATE_MODE (V4L2_CID_CODEC_BASE + 206) + +enum v4l2_mpeg_video_bitrate_mode +{ + V4L2_MPEG_VIDEO_BITRATE_MODE_VBR = 0, + V4L2_MPEG_VIDEO_BITRATE_MODE_CBR = 1, + V4L2_MPEG_VIDEO_BITRATE_MODE_CQ = 2, +}; + +#define V4L2_CID_MPEG_VIDEO_BITRATE (V4L2_CID_CODEC_BASE + 207) +#define V4L2_CID_MPEG_VIDEO_BITRATE_PEAK (V4L2_CID_CODEC_BASE + 208) +#define V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION (V4L2_CID_CODEC_BASE + 209) +#define V4L2_CID_MPEG_VIDEO_MUTE (V4L2_CID_CODEC_BASE + 210) +#define V4L2_CID_MPEG_VIDEO_MUTE_YUV (V4L2_CID_CODEC_BASE + 211) +#define V4L2_CID_MPEG_VIDEO_DECODER_SLICE_INTERFACE (V4L2_CID_CODEC_BASE + 212) +#define V4L2_CID_MPEG_VIDEO_DECODER_MPEG4_DEBLOCK_FILTER (V4L2_CID_CODEC_BASE + 213) +#define V4L2_CID_MPEG_VIDEO_CYCLIC_INTRA_REFRESH_MB (V4L2_CID_CODEC_BASE + 214) +#define V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE (V4L2_CID_CODEC_BASE + 215) +#define V4L2_CID_MPEG_VIDEO_HEADER_MODE (V4L2_CID_CODEC_BASE + 216) + +enum v4l2_mpeg_video_header_mode +{ + V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE = 0, + V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME = 1, +}; + +#define V4L2_CID_MPEG_VIDEO_MAX_REF_PIC (V4L2_CID_CODEC_BASE + 217) +#define V4L2_CID_MPEG_VIDEO_MB_RC_ENABLE (V4L2_CID_CODEC_BASE + 218) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_BYTES (V4L2_CID_CODEC_BASE + 219) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB (V4L2_CID_CODEC_BASE + 220) +#define V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE (V4L2_CID_CODEC_BASE + 221) + +enum v4l2_mpeg_video_multi_slice_mode +{ + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE = 0, + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_MB = 1, + V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_MAX_BYTES = 2, + + /* Kept for backwards compatibility reasons. Stupid typo... */ + + V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB = 1, + V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES = 2, +}; + +#define V4L2_CID_MPEG_VIDEO_VBV_SIZE (V4L2_CID_CODEC_BASE + 222) +#define V4L2_CID_MPEG_VIDEO_DEC_PTS (V4L2_CID_CODEC_BASE + 223) +#define V4L2_CID_MPEG_VIDEO_DEC_FRAME (V4L2_CID_CODEC_BASE + 224) +#define V4L2_CID_MPEG_VIDEO_VBV_DELAY (V4L2_CID_CODEC_BASE + 225) +#define V4L2_CID_MPEG_VIDEO_REPEAT_SEQ_HEADER (V4L2_CID_CODEC_BASE + 226) +#define V4L2_CID_MPEG_VIDEO_MV_H_SEARCH_RANGE (V4L2_CID_CODEC_BASE + 227) +#define V4L2_CID_MPEG_VIDEO_MV_V_SEARCH_RANGE (V4L2_CID_CODEC_BASE + 228) +#define V4L2_CID_MPEG_VIDEO_FORCE_KEY_FRAME (V4L2_CID_CODEC_BASE + 229) +#define V4L2_CID_MPEG_VIDEO_BASELAYER_PRIORITY_ID (V4L2_CID_CODEC_BASE + 230) +#define V4L2_CID_MPEG_VIDEO_AU_DELIMITER (V4L2_CID_CODEC_BASE + 231) +#define V4L2_CID_MPEG_VIDEO_LTR_COUNT (V4L2_CID_CODEC_BASE + 232) +#define V4L2_CID_MPEG_VIDEO_FRAME_LTR_INDEX (V4L2_CID_CODEC_BASE + 233) +#define V4L2_CID_MPEG_VIDEO_USE_LTR_FRAMES (V4L2_CID_CODEC_BASE + 234) +#define V4L2_CID_MPEG_VIDEO_DEC_CONCEAL_COLOR (V4L2_CID_CODEC_BASE + 235) +#define V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD (V4L2_CID_CODEC_BASE + 236) +#define V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE (V4L2_CID_CODEC_BASE + 237) + +enum v4l2_mpeg_video_intra_refresh_period_type +{ + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_RANDOM = 0, + V4L2_CID_MPEG_VIDEO_INTRA_REFRESH_PERIOD_TYPE_CYCLIC = 1, +}; + +/* CIDs for the FWHT codec as used by the vicodec driver. */ + +#define V4L2_CID_FWHT_I_FRAME_QP (V4L2_CID_CODEC_BASE + 290) +#define V4L2_CID_FWHT_P_FRAME_QP (V4L2_CID_CODEC_BASE + 291) + +#define V4L2_CID_MPEG_VIDEO_H263_I_FRAME_QP (V4L2_CID_CODEC_BASE + 300) +#define V4L2_CID_MPEG_VIDEO_H263_P_FRAME_QP (V4L2_CID_CODEC_BASE + 301) +#define V4L2_CID_MPEG_VIDEO_H263_B_FRAME_QP (V4L2_CID_CODEC_BASE + 302) +#define V4L2_CID_MPEG_VIDEO_H263_MIN_QP (V4L2_CID_CODEC_BASE + 303) +#define V4L2_CID_MPEG_VIDEO_H263_MAX_QP (V4L2_CID_CODEC_BASE + 304) +#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP (V4L2_CID_CODEC_BASE + 350) +#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP (V4L2_CID_CODEC_BASE + 351) +#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP (V4L2_CID_CODEC_BASE + 352) +#define V4L2_CID_MPEG_VIDEO_H264_MIN_QP (V4L2_CID_CODEC_BASE + 353) +#define V4L2_CID_MPEG_VIDEO_H264_MAX_QP (V4L2_CID_CODEC_BASE + 354) +#define V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM (V4L2_CID_CODEC_BASE + 355) +#define V4L2_CID_MPEG_VIDEO_H264_CPB_SIZE (V4L2_CID_CODEC_BASE + 356) +#define V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE (V4L2_CID_CODEC_BASE + 357) + +enum v4l2_mpeg_video_h264_entropy_mode +{ + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC = 0, + V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC = 1, +}; + +#define V4L2_CID_MPEG_VIDEO_H264_I_PERIOD (V4L2_CID_CODEC_BASE + 358) +#define V4L2_CID_MPEG_VIDEO_H264_LEVEL (V4L2_CID_CODEC_BASE + 359) + +enum v4l2_mpeg_video_h264_level +{ + V4L2_MPEG_VIDEO_H264_LEVEL_1_0 = 0, + V4L2_MPEG_VIDEO_H264_LEVEL_1B = 1, + V4L2_MPEG_VIDEO_H264_LEVEL_1_1 = 2, + V4L2_MPEG_VIDEO_H264_LEVEL_1_2 = 3, + V4L2_MPEG_VIDEO_H264_LEVEL_1_3 = 4, + V4L2_MPEG_VIDEO_H264_LEVEL_2_0 = 5, + V4L2_MPEG_VIDEO_H264_LEVEL_2_1 = 6, + V4L2_MPEG_VIDEO_H264_LEVEL_2_2 = 7, + V4L2_MPEG_VIDEO_H264_LEVEL_3_0 = 8, + V4L2_MPEG_VIDEO_H264_LEVEL_3_1 = 9, + V4L2_MPEG_VIDEO_H264_LEVEL_3_2 = 10, + V4L2_MPEG_VIDEO_H264_LEVEL_4_0 = 11, + V4L2_MPEG_VIDEO_H264_LEVEL_4_1 = 12, + V4L2_MPEG_VIDEO_H264_LEVEL_4_2 = 13, + V4L2_MPEG_VIDEO_H264_LEVEL_5_0 = 14, + V4L2_MPEG_VIDEO_H264_LEVEL_5_1 = 15, + V4L2_MPEG_VIDEO_H264_LEVEL_5_2 = 16, + V4L2_MPEG_VIDEO_H264_LEVEL_6_0 = 17, + V4L2_MPEG_VIDEO_H264_LEVEL_6_1 = 18, + V4L2_MPEG_VIDEO_H264_LEVEL_6_2 = 19, +}; + +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_ALPHA (V4L2_CID_CODEC_BASE + 360) +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_BETA (V4L2_CID_CODEC_BASE + 361) +#define V4L2_CID_MPEG_VIDEO_H264_LOOP_FILTER_MODE (V4L2_CID_CODEC_BASE + 362) + +enum v4l2_mpeg_video_h264_loop_filter_mode +{ + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_ENABLED = 0, + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED = 1, + V4L2_MPEG_VIDEO_H264_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY = 2, +}; + +#define V4L2_CID_MPEG_VIDEO_H264_PROFILE (V4L2_CID_CODEC_BASE + 363) + +enum v4l2_mpeg_video_h264_profile +{ + V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE = 0, + V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE = 1, + V4L2_MPEG_VIDEO_H264_PROFILE_MAIN = 2, + V4L2_MPEG_VIDEO_H264_PROFILE_EXTENDED = 3, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH = 4, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10 = 5, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422 = 6, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_PREDICTIVE = 7, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_10_INTRA = 8, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_422_INTRA = 9, + V4L2_MPEG_VIDEO_H264_PROFILE_HIGH_444_INTRA = 10, + V4L2_MPEG_VIDEO_H264_PROFILE_CAVLC_444_INTRA = 11, + V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_BASELINE = 12, + V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH = 13, + V4L2_MPEG_VIDEO_H264_PROFILE_SCALABLE_HIGH_INTRA = 14, + V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH = 15, + V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH = 16, + V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH = 17, +}; + +#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_HEIGHT (V4L2_CID_CODEC_BASE + 364) +#define V4L2_CID_MPEG_VIDEO_H264_VUI_EXT_SAR_WIDTH (V4L2_CID_CODEC_BASE + 365) +#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_ENABLE (V4L2_CID_CODEC_BASE + 366) +#define V4L2_CID_MPEG_VIDEO_H264_VUI_SAR_IDC (V4L2_CID_CODEC_BASE + 367) + +enum v4l2_mpeg_video_h264_vui_sar_idc +{ + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_UNSPECIFIED = 0, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_1x1 = 1, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_12x11 = 2, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_10x11 = 3, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_16x11 = 4, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_40x33 = 5, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_24x11 = 6, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_20x11 = 7, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_32x11 = 8, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_80x33 = 9, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_18x11 = 10, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_15x11 = 11, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_64x33 = 12, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_160x99 = 13, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_4x3 = 14, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_3x2 = 15, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_2x1 = 16, + V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED = 17, +}; + +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FRAME_PACKING (V4L2_CID_CODEC_BASE + 368) +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_CURRENT_FRAME_0 (V4L2_CID_CODEC_BASE + 369) +#define V4L2_CID_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE (V4L2_CID_CODEC_BASE + 370) + +enum v4l2_mpeg_video_h264_sei_fp_arrangement_type +{ + V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_CHECKERBOARD = 0, + V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_COLUMN = 1, + V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_ROW = 2, + V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_SIDE_BY_SIDE = 3, + V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TOP_BOTTOM = 4, + V4L2_MPEG_VIDEO_H264_SEI_FP_ARRANGEMENT_TYPE_TEMPORAL = 5, +}; + +#define V4L2_CID_MPEG_VIDEO_H264_FMO (V4L2_CID_CODEC_BASE + 371) +#define V4L2_CID_MPEG_VIDEO_H264_FMO_MAP_TYPE (V4L2_CID_CODEC_BASE + 372) + +enum v4l2_mpeg_video_h264_fmo_map_type +{ + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES = 0, + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES = 1, + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_FOREGROUND_WITH_LEFT_OVER = 2, + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_BOX_OUT = 3, + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN = 4, + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN = 5, + V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_EXPLICIT = 6, +}; + +#define V4L2_CID_MPEG_VIDEO_H264_FMO_SLICE_GROUP (V4L2_CID_CODEC_BASE + 373) +#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_DIRECTION (V4L2_CID_CODEC_BASE + 374) + +enum v4l2_mpeg_video_h264_fmo_change_dir +{ + V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_RIGHT = 0, + V4L2_MPEG_VIDEO_H264_FMO_CHANGE_DIR_LEFT = 1, +}; + +#define V4L2_CID_MPEG_VIDEO_H264_FMO_CHANGE_RATE (V4L2_CID_CODEC_BASE + 375) +#define V4L2_CID_MPEG_VIDEO_H264_FMO_RUN_LENGTH (V4L2_CID_CODEC_BASE + 376) +#define V4L2_CID_MPEG_VIDEO_H264_ASO (V4L2_CID_CODEC_BASE + 377) +#define V4L2_CID_MPEG_VIDEO_H264_ASO_SLICE_ORDER (V4L2_CID_CODEC_BASE + 378) +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING (V4L2_CID_CODEC_BASE + 379) +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_TYPE (V4L2_CID_CODEC_BASE + 380) + +enum v4l2_mpeg_video_h264_hierarchical_coding_type +{ + V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_B = 0, + V4L2_MPEG_VIDEO_H264_HIERARCHICAL_CODING_P = 1, +}; + +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER (V4L2_CID_CODEC_BASE + 381) +#define V4L2_CID_MPEG_VIDEO_H264_HIERARCHICAL_CODING_LAYER_QP (V4L2_CID_CODEC_BASE + 382) +#define V4L2_CID_MPEG_VIDEO_H264_CONSTRAINED_INTRA_PREDICTION (V4L2_CID_CODEC_BASE + 383) +#define V4L2_CID_MPEG_VIDEO_H264_CHROMA_QP_INDEX_OFFSET (V4L2_CID_CODEC_BASE + 384) +#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP (V4L2_CID_CODEC_BASE + 385) +#define V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP (V4L2_CID_CODEC_BASE + 386) +#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP (V4L2_CID_CODEC_BASE + 387) +#define V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP (V4L2_CID_CODEC_BASE + 388) +#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP (V4L2_CID_CODEC_BASE + 389) +#define V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP (V4L2_CID_CODEC_BASE + 390) +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L0_BR (V4L2_CID_CODEC_BASE + 391) +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L1_BR (V4L2_CID_CODEC_BASE + 392) +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L2_BR (V4L2_CID_CODEC_BASE + 393) +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L3_BR (V4L2_CID_CODEC_BASE + 394) +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L4_BR (V4L2_CID_CODEC_BASE + 395) +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L5_BR (V4L2_CID_CODEC_BASE + 396) +#define V4L2_CID_MPEG_VIDEO_H264_HIER_CODING_L6_BR (V4L2_CID_CODEC_BASE + 397) +#define V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP (V4L2_CID_CODEC_BASE + 400) +#define V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP (V4L2_CID_CODEC_BASE + 401) +#define V4L2_CID_MPEG_VIDEO_MPEG4_B_FRAME_QP (V4L2_CID_CODEC_BASE + 402) +#define V4L2_CID_MPEG_VIDEO_MPEG4_MIN_QP (V4L2_CID_CODEC_BASE + 403) +#define V4L2_CID_MPEG_VIDEO_MPEG4_MAX_QP (V4L2_CID_CODEC_BASE + 404) +#define V4L2_CID_MPEG_VIDEO_MPEG4_LEVEL (V4L2_CID_CODEC_BASE + 405) + +enum v4l2_mpeg_video_mpeg4_level +{ + V4L2_MPEG_VIDEO_MPEG4_LEVEL_0 = 0, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_0B = 1, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_1 = 2, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_2 = 3, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_3 = 4, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_3B = 5, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_4 = 6, + V4L2_MPEG_VIDEO_MPEG4_LEVEL_5 = 7, +}; + +#define V4L2_CID_MPEG_VIDEO_MPEG4_PROFILE (V4L2_CID_CODEC_BASE + 406) + +enum v4l2_mpeg_video_mpeg4_profile +{ + V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE = 0, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_SIMPLE = 1, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_CORE = 2, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_SIMPLE_SCALABLE = 3, + V4L2_MPEG_VIDEO_MPEG4_PROFILE_ADVANCED_CODING_EFFICIENCY = 4, +}; + +#define V4L2_CID_MPEG_VIDEO_MPEG4_QPEL (V4L2_CID_CODEC_BASE + 407) + +/* Control IDs for VP8 streams + * Although VP8 is not part of MPEG we add these controls to the MPEG class + * as that class is already handling other video compression standards + */ +#define V4L2_CID_MPEG_VIDEO_VPX_NUM_PARTITIONS (V4L2_CID_CODEC_BASE + 500) + +enum v4l2_vp8_num_partitions +{ + V4L2_CID_MPEG_VIDEO_VPX_1_PARTITION = 0, + V4L2_CID_MPEG_VIDEO_VPX_2_PARTITIONS = 1, + V4L2_CID_MPEG_VIDEO_VPX_4_PARTITIONS = 2, + V4L2_CID_MPEG_VIDEO_VPX_8_PARTITIONS = 3, +}; + +#define V4L2_CID_MPEG_VIDEO_VPX_IMD_DISABLE_4X4 (V4L2_CID_CODEC_BASE + 501) +#define V4L2_CID_MPEG_VIDEO_VPX_NUM_REF_FRAMES (V4L2_CID_CODEC_BASE + 502) + +enum v4l2_vp8_num_ref_frames +{ + V4L2_CID_MPEG_VIDEO_VPX_1_REF_FRAME = 0, + V4L2_CID_MPEG_VIDEO_VPX_2_REF_FRAME = 1, + V4L2_CID_MPEG_VIDEO_VPX_3_REF_FRAME = 2, +}; + +#define V4L2_CID_MPEG_VIDEO_VPX_FILTER_LEVEL (V4L2_CID_CODEC_BASE + 503) +#define V4L2_CID_MPEG_VIDEO_VPX_FILTER_SHARPNESS (V4L2_CID_CODEC_BASE + 504) +#define V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_REF_PERIOD (V4L2_CID_CODEC_BASE + 505) +#define V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_SEL (V4L2_CID_CODEC_BASE + 506) + +enum v4l2_vp8_golden_frame_sel +{ + V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_USE_PREV = 0, + V4L2_CID_MPEG_VIDEO_VPX_GOLDEN_FRAME_USE_REF_PERIOD = 1, +}; + +#define V4L2_CID_MPEG_VIDEO_VPX_MIN_QP (V4L2_CID_CODEC_BASE + 507) +#define V4L2_CID_MPEG_VIDEO_VPX_MAX_QP (V4L2_CID_CODEC_BASE + 508) +#define V4L2_CID_MPEG_VIDEO_VPX_I_FRAME_QP (V4L2_CID_CODEC_BASE + 509) +#define V4L2_CID_MPEG_VIDEO_VPX_P_FRAME_QP (V4L2_CID_CODEC_BASE + 510) + +#define V4L2_CID_MPEG_VIDEO_VP8_PROFILE (V4L2_CID_CODEC_BASE + 511) + +enum v4l2_mpeg_video_vp8_profile +{ + V4L2_MPEG_VIDEO_VP8_PROFILE_0 = 0, + V4L2_MPEG_VIDEO_VP8_PROFILE_1 = 1, + V4L2_MPEG_VIDEO_VP8_PROFILE_2 = 2, + V4L2_MPEG_VIDEO_VP8_PROFILE_3 = 3, +}; + +#endif /* __INCLUDE_SYS_VIDEO_CONTROLS_H */ diff --git a/include/sys/videoio.h b/include/sys/videoio.h index 1576bd51c91f6..182e3763d8a5d 100644 --- a/include/sys/videoio.h +++ b/include/sys/videoio.h @@ -28,9 +28,9 @@ #include #include #include +#include #include -#include #ifdef __cplusplus extern "C" @@ -518,6 +518,8 @@ enum v4l2_buf_type || (type) == V4L2_BUF_TYPE_SDR_OUTPUT \ || (type) == V4L2_BUF_TYPE_META_OUTPUT) +#define V4L2_TYPE_IS_CAPTURE(type) (!V4L2_TYPE_IS_OUTPUT(type)) + /* Memory I/O method. Currently, support only V4L2_MEMORY_USERPTR. */ enum v4l2_memory @@ -775,15 +777,15 @@ typedef struct v4l2_plane v4l2_plane_t; struct v4l2_buffer { - uint16_t index; /* Buffer id */ - uint16_t type; /* enum #v4l2_buf_type */ + uint32_t index; /* Buffer id */ + uint32_t type; /* enum #v4l2_buf_type */ uint32_t bytesused; /* Driver sets the image size */ - uint16_t flags; /* Buffer flags. */ - uint16_t field; /* The field order of the image */ + uint32_t flags; /* Buffer flags. */ + uint32_t field; /* The field order of the image */ struct timeval timestamp; /* Frame timestamp */ struct v4l2_timecode timecode; /* Frame timecode */ - uint16_t sequence; /* Frame sequence number */ - uint16_t memory; /* enum #v4l2_memory */ + uint32_t sequence; /* Frame sequence number */ + uint32_t memory; /* enum #v4l2_memory */ union { uint32_t offset; @@ -897,8 +899,8 @@ struct v4l2_frmivalenum struct v4l2_pix_format { - uint16_t width; /* Image width in pixels */ - uint16_t height; /* Image height in pixels */ + uint32_t width; /* Image width in pixels */ + uint32_t height; /* Image height in pixels */ uint32_t pixelformat; /* The pixel format or type of compression. */ uint32_t field; /* enum #v4l2_field */ uint32_t bytesperline; /* For padding, zero if unused */ @@ -987,6 +989,16 @@ struct v4l2_captureparm uint32_t readbuffers; /* # of buffers for read */ }; +struct v4l2_outputparm +{ + uint32_t capability; /* Supported modes */ + uint32_t outputmode; /* Current mode */ + struct v4l2_fract timeperframe; /* Time per frame in seconds */ + uint32_t extendedmode; /* Driver-specific extensions */ + uint32_t writebuffers; /* # of buffers for write */ + uint32_t reserved[4]; +}; + struct v4l2_cropcap { uint32_t type; /* enum v4l2_buf_type */ @@ -1013,7 +1025,9 @@ struct v4l2_streamparm union { struct v4l2_captureparm capture; + struct v4l2_outputparm output; } parm; + uint8_t raw_data[200]; /* user-defined */ }; /* E V E N T S */ @@ -1141,7 +1155,7 @@ enum v4l2_ctrl_type struct v4l2_queryctrl { - uint16_t ctrl_class; /* Control class */ + uint16_t ctrl_class; /* Control class(not used) */ uint16_t id; /* Control id */ uint16_t type; /* enum #v4l2_ctrl_type */ char name[32]; /* Name of control */ @@ -1153,7 +1167,7 @@ struct v4l2_queryctrl struct v4l2_query_ext_ctrl { - uint16_t ctrl_class; /* Control class */ + uint16_t ctrl_class; /* Control class(not used) */ uint16_t id; /* Control id */ uint16_t type; /* enum #v4l2_ctrl_type */ char name[32]; /* Name of control */ @@ -1170,7 +1184,7 @@ struct v4l2_query_ext_ctrl struct v4l2_querymenu { - uint16_t ctrl_class; /* Camera control class */ + uint16_t ctrl_class; /* Camera control class(not used) */ uint16_t id; /* Camera control id */ uint32_t index; /* Index of menu. */ union diff --git a/include/threads.h b/include/threads.h index 2449dc62e3197..5044d47060519 100644 --- a/include/threads.h +++ b/include/threads.h @@ -203,7 +203,7 @@ static inline int mtx_init(FAR mtx_t *mutex, int type) * int mtx_timedlock(FAR mtx_t *mutex, FAR const struct timespec *tp); */ -#define mtx_timedlock(mutex,tp) pthread_mutex_timedwait(mutex,tp) +#define mtx_timedlock(mutex,tp) pthread_mutex_timedlock(mutex,tp) /* mtx_trylock: locks a mutex or returns without blocking if already locked * diff --git a/include/unistd.h b/include/unistd.h index cc88c845399fb..2e2f52419a0ac 100644 --- a/include/unistd.h +++ b/include/unistd.h @@ -289,6 +289,18 @@ # define execvpe execve #endif +/* Commands for lockf() + * F_ULOCK - Unlock + * F_LOCK - Blocking Exclusive Lock + * F_TLOCK - Attempted Exclusive Locking + * F_TEST - Test Locked Status + */ + +#define F_ULOCK 0 +#define F_LOCK 1 +#define F_TLOCK 2 +#define F_TEST 3 + /**************************************************************************** * Public Data ****************************************************************************/ @@ -337,6 +349,7 @@ ssize_t pread(int fd, FAR void *buf, size_t nbytes, off_t offset); ssize_t pwrite(int fd, FAR const void *buf, size_t nbytes, off_t offset); int ftruncate(int fd, off_t length); int fchown(int fd, uid_t owner, gid_t group); +int lockf(int fd, int cmd, off_t len); /* Check if a file descriptor corresponds to a terminal I/O file */ diff --git a/libs/libc/Makefile b/libs/libc/Makefile index 42d9f4c3e82a7..dd5a3452dd1c3 100644 --- a/libs/libc/Makefile +++ b/libs/libc/Makefile @@ -49,6 +49,7 @@ include pwd/Make.defs include queue/Make.defs include regex/Make.defs include sched/Make.defs +include search/Make.defs include semaphore/Make.defs include signal/Make.defs include spawn/Make.defs diff --git a/libs/libc/assert/Make.defs b/libs/libc/assert/Make.defs index 830a50c05fa7c..4b236fd02abde 100644 --- a/libs/libc/assert/Make.defs +++ b/libs/libc/assert/Make.defs @@ -24,8 +24,12 @@ ifeq ($(CONFIG_STACK_CANARIES),y) CSRCS += lib_stackchk.c endif -assert/lib_assert.c_CFLAGS += -fno-lto -assert/lib_stackchk.c_CFLAGS += -fno-lto +ifeq ($(CONFIG_ARCH_TOOLCHAIN_GNU),y) + ifeq ($(CONFIG_LTO_NONE),n) + assert/lib_assert.c_CFLAGS += -fno-lto + assert/lib_stackchk.c_CFLAGS += -fno-lto + endif +endif # Add the assert directory to the build diff --git a/libs/libc/audio/libsrc/Make.defs b/libs/libc/audio/libsrc/Make.defs index dc218ed785d4c..aed6918d12abb 100644 --- a/libs/libc/audio/libsrc/Make.defs +++ b/libs/libc/audio/libsrc/Make.defs @@ -20,19 +20,21 @@ ifeq ($(CONFIG_AUDIO_SRC),y) -PACKAGE=libsamplerate -VERSION=0.2.2 +PACKAGE = libsamplerate +VERSION = 0.2.2 + +SRCPATH = audio/libsrc # Download and unpack tarball if no git repo found -ifeq ($(wildcard libsamplerate/.git),) -libsamplerate: - $(call DOWNLOAD,https://codeload.github.com/libsndfile/libsamplerate/zip,master,libsamplerate.zip) - $(Q) unzip -o libsamplerate.zip - $(Q) mv libsamplerate-master libsamplerate +$(SRCPATH)/libsamplerate: +ifeq ($(wildcard $(SRCPATH)/libsamplerate/.git),) + $(call DOWNLOAD,https://codeload.github.com/libsndfile/libsamplerate/zip,master,$(SRCPATH)/libsamplerate.zip) + $(Q) unzip -o $(SRCPATH)/libsamplerate.zip -d $(SRCPATH) + $(Q) mv $(SRCPATH)/libsamplerate-master $(SRCPATH)/libsamplerate endif -$(TOPDIR)/include/nuttx/audio/samplerate.h : libsamplerate - $(Q) cp -rf libsamplerate/include/samplerate.h $(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)audio$(DELIM) +$(TOPDIR)/include/nuttx/audio/samplerate.h : $(SRCPATH)/libsamplerate + $(Q) cp -rf $(SRCPATH)/libsamplerate/include/samplerate.h $(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)audio$(DELIM) context:: $(TOPDIR)/include/nuttx/audio/samplerate.h @@ -45,7 +47,7 @@ CFLAGS += -DPACKAGE=\"$(PACKAGE)\" -DVERSION=\"$(VERSION)\" CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)audio -CFLAGS += -DCPU_CLIPS_NEGATIVE=0 +CFLAGS += -DCPU_CLIPS_NEGATIVE=0 -DCPU_CLIPS_POSITIVE=0 ifeq ($(CONFIG_SINC_FAST_CONVERTER),y) CFLAGS += -DENABLE_SINC_FAST_CONVERTER @@ -59,15 +61,15 @@ ifeq ($(CONFIG_SINC_BEST_CONVERTER),y) CFLAGS += -DENABLE_SINC_BEST_CONVERTER endif -VPATH += libsamplerate/src -SUBDIRS += libsamplerate/src -DEPPATH += --dep-path libsamplerate/src +VPATH += $(SRCPATH)/libsamplerate/src +SUBDIRS += $(SRCPATH)/libsamplerate/src +DEPPATH += --dep-path $(SRCPATH)/libsamplerate/src distclean:: $(call DELDIR, $(TOPDIR)$(DELIM)include$(DELIM)nuttx$(DELIM)audio$(DELIM)samplerate.h) -ifeq ($(wildcard libsamplerate/.git),) - $(call DELDIR, libsamplerate) - $(call DELFILE, libsamplerate.zip) +ifeq ($(wildcard $(SRCPATH)/libsamplerate/.git),) + $(call DELDIR, $(SRCPATH)/libsamplerate) + $(call DELFILE, $(SRCPATH)/libsamplerate.zip) endif endif diff --git a/libs/libc/ctype/CMakeLists.txt b/libs/libc/ctype/CMakeLists.txt index 2376e5e2a51f3..c77b2b4d41b2f 100644 --- a/libs/libc/ctype/CMakeLists.txt +++ b/libs/libc/ctype/CMakeLists.txt @@ -34,4 +34,5 @@ target_sources( lib_isupper.c lib_isxdigit.c lib_tolower.c - lib_toupper.c) + lib_toupper.c + lib_ctype.c) diff --git a/libs/libc/ctype/Make.defs b/libs/libc/ctype/Make.defs index cea6cd882b4ea..86c42727530a1 100644 --- a/libs/libc/ctype/Make.defs +++ b/libs/libc/ctype/Make.defs @@ -23,7 +23,7 @@ CSRCS += lib_isalnum.c lib_isalpha.c lib_isascii.c lib_isblank.c CSRCS += lib_iscntrl.c lib_isdigit.c lib_isgraph.c lib_islower.c CSRCS += lib_isprint.c lib_ispunct.c lib_isspace.c lib_isupper.c -CSRCS += lib_isxdigit.c lib_tolower.c lib_toupper.c +CSRCS += lib_isxdigit.c lib_tolower.c lib_toupper.c lib_ctype.c DEPPATH += --dep-path ctype VPATH += :ctype diff --git a/libs/libc/ctype/lib_ctype.c b/libs/libc/ctype/lib_ctype.c new file mode 100644 index 0000000000000..c0bea821c1880 --- /dev/null +++ b/libs/libc/ctype/lib_ctype.c @@ -0,0 +1,77 @@ +/**************************************************************************** + * libs/libc/ctype/lib_ctype.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* GNU libstdc++ is expecting an array _ctype_ to be defined. This array + * is usually defined in GNU libc or newlib. + * Here the system support only basic ASCII locale. + */ + +const char _ctype_[] = +{ + 0, + _C, _C, _C, _C, _C, _C, _C, _C, \ + _C, _C | _S, _C | _S, _C | _S, _C | _S, _C | _S, _C, _C, \ + _C, _C, _C, _C, _C, _C, _C, _C, \ + _C, _C, _C, _C, _C, _C, _C, _C, \ + _S | _B, _P, _P, _P, _P, _P, _P, _P, \ + _P, _P, _P, _P, _P, _P, _P, _P, \ + _N, _N, _N, _N, _N, _N, _N, _N, \ + _N, _N, _P, _P, _P, _P, _P, _P, \ + _P, _U | _X, _U | _X, _U | _X, _U | _X, _U | _X, _U | _X, _U, \ + _U, _U, _U, _U, _U, _U, _U, _U, \ + _U, _U, _U, _U, _U, _U, _U, _U, \ + _U, _U, _U, _P, _P, _P, _P, _P, \ + _P, _L | _X, _L | _X, _L | _X, _L | _X, _L | _X, _L | _X, _L, \ + _L, _L, _L, _L, _L, _L, _L, _L, \ + _L, _L, _L, _L, _L, _L, _L, _L, \ + _L, _L, _L, _P, _P, _P, _P, _C, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0 +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ diff --git a/libs/libc/fdt/CMakeLists.txt b/libs/libc/fdt/CMakeLists.txt index 1a470a432ecc3..a1167cc388ef3 100644 --- a/libs/libc/fdt/CMakeLists.txt +++ b/libs/libc/fdt/CMakeLists.txt @@ -19,12 +19,20 @@ # ############################################################################## if(CONFIG_LIBC_FDT) - set(VERSION CONFIG_LIBC_FDT_DTC_VERSION) + set(FDT_DIR ${CMAKE_CURRENT_LIST_DIR}/dtc) + if(NOT EXISTS ${FDT_DIR}) + set(VERSION ${CONFIG_LIBC_FDT_DTC_VERSION}) - FetchContent_Declare( - dtc URL https://github.com/dgibson/dtc/archive/v$(VERSION).zip) - FetchContent_Populate(dtc) - FetchContent_GetProperties(dtc) + FetchContent_Declare( + dtc + URL https://github.com/dgibson/dtc/archive/v${VERSION}.zip SOURCE_DIR + ${CMAKE_CURRENT_LIST_DIR}/dtc BINARY_DIR + ${CMAKE_BINARY_DIR}/libs/libc/fdt/dtc) + FetchContent_GetProperties(dtc) + if(NOT dtc_POPULATED) + FetchContent_Populate(dtc) + endif() + endif() set(SRCS fdt.c @@ -37,8 +45,9 @@ if(CONFIG_LIBC_FDT) fdt_addresses.c fdt_overlay.c fdt_check.c) - list(TRANSFORM SRCS PREPEND ${dtc_SOURCE_DIR}/libfdt/) + list(TRANSFORM SRCS PREPEND ${FDT_DIR}/libfdt/) + target_sources(c PRIVATE ${SRCS}) - target_include_directories(c PRIVATE ${dtc_SOURCE_DIR}/libfdt) + target_include_directories(c PRIVATE ${FDT_DIR}/libfdt) endif() diff --git a/libs/libc/inttypes/CMakeLists.txt b/libs/libc/inttypes/CMakeLists.txt index 14239dfde96ac..aaf5f6dbfba9b 100644 --- a/libs/libc/inttypes/CMakeLists.txt +++ b/libs/libc/inttypes/CMakeLists.txt @@ -18,4 +18,5 @@ # # ############################################################################## -target_sources(c PRIVATE lib_imaxabs.c lib_strtoimax.c lib_strtoumax.c) +target_sources(c PRIVATE lib_imaxabs.c lib_imaxdiv.c lib_strtoimax.c + lib_strtoumax.c) diff --git a/libs/libc/inttypes/Make.defs b/libs/libc/inttypes/Make.defs index 6c6903020454e..48c7e7661ef3c 100644 --- a/libs/libc/inttypes/Make.defs +++ b/libs/libc/inttypes/Make.defs @@ -20,7 +20,7 @@ # Add the inttypes C files to the build -CSRCS += lib_imaxabs.c lib_strtoimax.c lib_strtoumax.c +CSRCS += lib_imaxabs.c lib_imaxdiv.c lib_strtoimax.c lib_strtoumax.c # Add the inttypes directory to the build diff --git a/libs/libc/inttypes/lib_imaxdiv.c b/libs/libc/inttypes/lib_imaxdiv.c new file mode 100644 index 0000000000000..86055bd21645c --- /dev/null +++ b/libs/libc/inttypes/lib_imaxdiv.c @@ -0,0 +1,39 @@ +/**************************************************************************** + * libs/libc/inttypes/lib_imaxdiv.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +imaxdiv_t imaxdiv(intmax_t numer, intmax_t denom) +{ + imaxdiv_t f; + + f.quot = numer / denom; + f.rem = numer % denom; + return f; +} diff --git a/libs/libc/libc.csv b/libs/libc/libc.csv index c85ae93057dfa..3623e7ff62525 100644 --- a/libs/libc/libc.csv +++ b/libs/libc/libc.csv @@ -52,7 +52,7 @@ "dq_remfirst","nuttx/queue.h","","FAR dq_entry_t *","FAR dq_queue_t *" "dq_remlast","nuttx/queue.h","","FAR dq_entry_t *","FAR dq_queue_t *" "ether_ntoa","netinet/ether.h","","FAR char *","FAR const struct ether_addr *" -"execv","unistd.h","","int","FAR const char *","FAR char *const[]|FAR char *const *" +"execv","unistd.h","defined(CONFIG_LIBC_EXECFUNCS)","int","FAR const char *","FAR char *const[]|FAR char *const *" "exit","stdlib.h","","noreturn","int" "fchdir","unistd.h","!defined(CONFIG_DISABLE_ENVIRON)","int","int" "fclose","stdio.h","defined(CONFIG_FILE_STREAM)","int","FAR FILE *" @@ -213,9 +213,9 @@ "pthread_condattr_setclock","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_condattr_t *","clockid_t" "pthread_create","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_t *","FAR const pthread_attr_t *","pthread_startroutine_t","pthread_addr_t" "pthread_getname_np","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_t","char *","size_t" -"pthread_getspecific","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","FAR void *","pthread_key_t" -"pthread_key_create","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_key_t *","FAR void (*) (void *)|FAR void *" -"pthread_key_delete","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_key_t" +"pthread_getspecific","pthread.h","!defined(CONFIG_DISABLE_PTHREAD) && CONFIG_TLS_NELEM > 0","FAR void *","pthread_key_t" +"pthread_key_create","pthread.h","!defined(CONFIG_DISABLE_PTHREAD) && CONFIG_TLS_NELEM > 0","int","FAR pthread_key_t *","FAR void (*) (void *)|FAR void *" +"pthread_key_delete","pthread.h","!defined(CONFIG_DISABLE_PTHREAD) && CONFIG_TLS_NELEM > 0","int","pthread_key_t" "pthread_mutex_lock","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_mutex_t *" "pthread_mutexattr_destroy","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_mutexattr_t *" "pthread_mutexattr_getpshared","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_mutexattr_t *","FAR int *" @@ -229,14 +229,14 @@ "pthread_rwlock_rdlock","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_rwlock_t *" "pthread_rwlock_unlock","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","FAR pthread_rwlock_t *" "pthread_setname_np","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_t","const char *" -"pthread_setspecific","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","int","pthread_key_t","FAR const void *" +"pthread_setspecific","pthread.h","!defined(CONFIG_DISABLE_PTHREAD) && CONFIG_TLS_NELEM > 0","int","pthread_key_t","FAR const void *" "pthread_yield","pthread.h","!defined(CONFIG_DISABLE_PTHREAD)","void" "puts","stdio.h","defined(CONFIG_FILE_STREAM)","int","FAR const IPTR char *" "putwc","wchar.h","defined(CONFIG_FILE_STREAM)","wint_t","wchar_t","FAR FILE *" "putwc_unlocked","wchar.h","defined(CONFIG_FILE_STREAM)","wint_t","wchar_t","FAR FILE *" "putwchar","wchar.h","","wint_t","wchar_t" "pwritev","sys/uio.h","","ssize_t","int","FAR const struct iovec *","int","off_t" -"qsort","stdlib.h","","void","FAR void *","size_t","size_t","int(*)(FAR const void *","FAR const void *)" +"qsort","stdlib.h","","void","FAR void *","size_t","size_t","int(*)(FAR const void *,FAR const void *)" "raise","signal.h","","int","int" "rand","stdlib.h","","int" "readdir","dirent.h","","FAR struct dirent *","FAR DIR *" diff --git a/libs/libc/locale/CMakeLists.txt b/libs/libc/locale/CMakeLists.txt index e293a0590897a..71346f3999bf6 100644 --- a/libs/libc/locale/CMakeLists.txt +++ b/libs/libc/locale/CMakeLists.txt @@ -19,6 +19,13 @@ # ############################################################################## if(CONFIG_LIBC_LOCALE) - target_sources(c PRIVATE lib_duplocale.c lib_freelocale.c lib_localeconv.c - lib_newlocale.c lib_setlocale.c lib_uselocale.c) + target_sources( + c + PRIVATE lib_duplocale.c + lib_freelocale.c + lib_localeconv.c + lib_newlocale.c + lib_setlocale.c + lib_uselocale.c + lib_maxlocale.c) endif() diff --git a/libs/libc/locale/Make.defs b/libs/libc/locale/Make.defs index 5b6c0ba8d638d..4612ab584f5a1 100644 --- a/libs/libc/locale/Make.defs +++ b/libs/libc/locale/Make.defs @@ -25,6 +25,7 @@ ifeq ($(CONFIG_LIBC_LOCALE),y) CSRCS += lib_duplocale.c lib_freelocale.c lib_localeconv.c CSRCS += lib_newlocale.c lib_setlocale.c lib_uselocale.c CSRCS += lib_catalog.c lib_gettext.c lib_langinfo.c lib_iconv.c +CSRCS += lib_maxlocale.c # Add the locale directory to the build diff --git a/libs/libc/locale/lib_maxlocale.c b/libs/libc/locale/lib_maxlocale.c new file mode 100644 index 0000000000000..1e007531dd562 --- /dev/null +++ b/libs/libc/locale/lib_maxlocale.c @@ -0,0 +1,45 @@ +/**************************************************************************** + * libs/libc/locale/lib_maxlocale.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#ifdef CONFIG_LIBC_LOCALE + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* GNU libstdc++ is expecting some functions to be defined. + */ + +/* Shall return the max number of bytes of a multibyte character */ + +int __locale_mb_cur_max(void) +{ + return MB_CUR_MAX; +} + +#endif diff --git a/libs/libc/machine/arm/armv7-m/gnu/arch_memchr.S b/libs/libc/machine/arm/armv7-m/gnu/arch_memchr.S index 2ea5b2302859f..c90bd0bf1de64 100644 --- a/libs/libc/machine/arm/armv7-m/gnu/arch_memchr.S +++ b/libs/libc/machine/arm/armv7-m/gnu/arch_memchr.S @@ -136,6 +136,7 @@ */ .text + .section .text.memchr .thumb_func .align 4 .p2align 4,,15 diff --git a/libs/libc/machine/arm/armv7-m/gnu/arch_memcpy.S b/libs/libc/machine/arm/armv7-m/gnu/arch_memcpy.S index 630ece62b7906..e949ec4bc40a2 100644 --- a/libs/libc/machine/arm/armv7-m/gnu/arch_memcpy.S +++ b/libs/libc/machine/arm/armv7-m/gnu/arch_memcpy.S @@ -94,6 +94,7 @@ .syntax unified .text + .section .text.memcpy .align 2 .global memcpy .thumb diff --git a/libs/libc/machine/arm/armv7-m/gnu/arch_memmove.S b/libs/libc/machine/arm/armv7-m/gnu/arch_memmove.S index 68032ae1da98f..46705f5a74ae4 100644 --- a/libs/libc/machine/arm/armv7-m/gnu/arch_memmove.S +++ b/libs/libc/machine/arm/armv7-m/gnu/arch_memmove.S @@ -35,6 +35,8 @@ .thumb .syntax unified + .text + .section .text.memmove .global memmove .type memmove, %function memmove: diff --git a/libs/libc/machine/arm/armv7-m/gnu/arch_memset.S b/libs/libc/machine/arm/armv7-m/gnu/arch_memset.S index 47c2925736b6e..f3c25481b832c 100644 --- a/libs/libc/machine/arm/armv7-m/gnu/arch_memset.S +++ b/libs/libc/machine/arm/armv7-m/gnu/arch_memset.S @@ -35,6 +35,8 @@ .thumb .syntax unified + .text + .section .text.memset .global memset .type memset, %function memset: diff --git a/libs/libc/machine/arm/armv7-m/gnu/arch_strcmp.S b/libs/libc/machine/arm/armv7-m/gnu/arch_strcmp.S index 0c266bda0cb4f..40d54311627c4 100644 --- a/libs/libc/machine/arm/armv7-m/gnu/arch_strcmp.S +++ b/libs/libc/machine/arm/armv7-m/gnu/arch_strcmp.S @@ -72,6 +72,7 @@ .macro def_fn f p2align=0 .text + .section .text.strcmp .p2align \p2align .global \f .type \f, %function diff --git a/libs/libc/machine/arm/armv7-m/gnu/arch_strcpy.S b/libs/libc/machine/arm/armv7-m/gnu/arch_strcpy.S index 2ad81c452c975..30de5bdb23253 100644 --- a/libs/libc/machine/arm/armv7-m/gnu/arch_strcpy.S +++ b/libs/libc/machine/arm/armv7-m/gnu/arch_strcpy.S @@ -58,6 +58,7 @@ .syntax unified .text + .section .text.strcpy .align 2 .global strcpy .thumb diff --git a/libs/libc/machine/arm/armv7-m/gnu/arch_strlen.S b/libs/libc/machine/arm/armv7-m/gnu/arch_strlen.S index b40231fa3c8df..5371db28a2769 100644 --- a/libs/libc/machine/arm/armv7-m/gnu/arch_strlen.S +++ b/libs/libc/machine/arm/armv7-m/gnu/arch_strlen.S @@ -70,6 +70,7 @@ .macro def_fn f p2align=0 .text + .section .text.strlen .p2align \p2align .global \f .type \f, %function diff --git a/libs/libc/machine/arm64/CMakeLists.txt b/libs/libc/machine/arm64/CMakeLists.txt new file mode 100644 index 0000000000000..08cabb0ff20f5 --- /dev/null +++ b/libs/libc/machine/arm64/CMakeLists.txt @@ -0,0 +1,28 @@ +# ############################################################################## +# libs/libc/machine/arm64/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## +add_subdirectory(gnu) + +set(SRCS) + +if(CONFIG_LIBC_ARCH_ELF_64BIT) + list(APPEND SRCS arch_elf.c) +endif() + +target_sources(c PRIVATE ${SRCS}) diff --git a/libs/libc/machine/arm64/Make.defs b/libs/libc/machine/arm64/Make.defs index f4ff27d46e18c..c9c085d732f19 100644 --- a/libs/libc/machine/arm64/Make.defs +++ b/libs/libc/machine/arm64/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# libs/libc/machine/ARM64/Make.defs +# libs/libc/machine/arm64/Make.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/libs/libc/machine/arm64/gnu/CMakeLists.txt b/libs/libc/machine/arm64/gnu/CMakeLists.txt new file mode 100644 index 0000000000000..2d556c22b25bf --- /dev/null +++ b/libs/libc/machine/arm64/gnu/CMakeLists.txt @@ -0,0 +1,79 @@ +# ############################################################################## +# libs/libc/machine/arm64/gnu/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS) + +if(CONFIG_ARM64_MEMCHR) + list(APPEND SRCS arch_memchr.S) +endif() + +if(CONFIG_ARM64_MEMCMP) + list(APPEND SRCS arch_memcmp.S) +endif() + +if(CONFIG_ARM64_MEMCPY) + list(APPEND SRCS arch_memcpy.S) +endif() + +if(CONFIG_ARM64_MEMMOVE) + list(APPEND SRCS arch_memmove.S) +endif() + +if(CONFIG_ARM64_MEMSET) + list(APPEND SRCS arch_memset.S) +endif() + +if(CONFIG_ARM64_STRCHR) + list(APPEND SRCS arch_strchr.S) +endif() + +if(CONFIG_ARM64_STRCHRNUL) + list(APPEND SRCS arch_strchrnul.S) +endif() + +if(CONFIG_ARM64_STRCMP) + list(APPEND SRCS arch_strcmp.S) +endif() + +if(CONFIG_ARM64_STRCPY) + list(APPEND SRCS arch_strcpy.S) +endif() + +if(CONFIG_ARM64_STRLEN) + list(APPEND SRCS arch_strlen.S) +endif() + +if(CONFIG_ARM64_STRNCMP) + list(APPEND SRCS arch_strncmp.S) +endif() + +if(CONFIG_ARM64_STRNLEN) + list(APPEND SRCS arch_strnlen.S) +endif() + +if(CONFIG_ARM64_STRRCHR) + list(APPEND SRCS arch_strrchr.S) +endif() + +if(CONFIG_ARCH_SETJMP_H) + list(APPEND SRCS arch_setjmp.S) +endif() + +target_sources(c PRIVATE ${SRCS}) diff --git a/libs/libc/machine/x86_64/CMakeLists.txt b/libs/libc/machine/x86_64/CMakeLists.txt new file mode 100644 index 0000000000000..9d6e0982389a8 --- /dev/null +++ b/libs/libc/machine/x86_64/CMakeLists.txt @@ -0,0 +1,19 @@ +# ############################################################################## +# libs/libc/machine/x86_64/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## diff --git a/libs/libc/machine/x86_64/Kconfig b/libs/libc/machine/x86_64/Kconfig new file mode 100644 index 0000000000000..f72f3c094ce4c --- /dev/null +++ b/libs/libc/machine/x86_64/Kconfig @@ -0,0 +1,4 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# diff --git a/libs/libc/misc/Kconfig b/libs/libc/misc/Kconfig index f94e97f77690c..6227d520fb07f 100644 --- a/libs/libc/misc/Kconfig +++ b/libs/libc/misc/Kconfig @@ -81,6 +81,15 @@ config LIBC_FTOK_VFS_PATH ---help--- The relative path to where ftok will exist in the root namespace. +config LIBC_UNAME_DISABLE_TIMESTAMP + bool "Disable uname timestamp support" + default n + ---help--- + Currently uname command will print the timestamp + when the binary was built, and it generates an issue + because two identical built binaries will have differents + hashes/CRC. + choice prompt "Select memfd implementation" diff --git a/libs/libc/misc/Make.defs b/libs/libc/misc/Make.defs index a9e6e97ede17b..c3d19570f7f38 100644 --- a/libs/libc/misc/Make.defs +++ b/libs/libc/misc/Make.defs @@ -79,7 +79,9 @@ endif # To ensure uname information is newest, # add lib_utsname.o to phony target for force rebuild +#if !defined(CONFIG_LIBC_UNAME_DISABLE_TIMESTAMP) .PHONY: lib_utsname$(OBJEXT) +#endif # Add the misc directory to the build diff --git a/libs/libc/misc/lib_fdcheck.c b/libs/libc/misc/lib_fdcheck.c index 9163faacee924..8cf56dcc3b62a 100644 --- a/libs/libc/misc/lib_fdcheck.c +++ b/libs/libc/misc/lib_fdcheck.c @@ -25,6 +25,8 @@ #include #include #include +#include +#include #include #include @@ -35,97 +37,89 @@ * Pre-processor Definitions ****************************************************************************/ -#define FD_SHIFT 0 +#define TAG_SHIFT 0 +#define TAG_BITS 8 +#define TAG_MASK ((1 << TAG_BITS) - 1) + +#define FD_SHIFT (TAG_SHIFT + TAG_BITS) #define FD_BITS LOG2_CEIL(OPEN_MAX) #define FD_MASK ((1 << FD_BITS) - 1) -#define PID_SHIFT (FD_BITS + FD_SHIFT) -#define PID_BITS (8 * sizeof(int) - 1 - PID_SHIFT) -#define PID_MASK ((1 << PID_BITS) - 1) +static_assert(FD_BITS <= TAG_BITS, "FD_BITS is too long"); /**************************************************************************** - * Public Functions + * Private Data ****************************************************************************/ +static spinlock_t g_fdcheck_lock = SP_UNLOCKED; +static uint8_t g_fdcheck_tag = 0; + /**************************************************************************** - * Name: fdcheck_restore - * - * Description: Obtain original fd information - * - * Val carries the pid and fd information. - * The original fd information is stored in low bit of val. - * The pid information is stored in the high bit of val. - * For ease of understanding, let's give an example where - * the following information is represented in 32-bit binary format - * - * val 00000000 00000000 01010101 10001010 - * fd 00000000 00000000 00000000 10001010 - * pid 00000000 00000000 00000000 01010101 - * - * In this function, we also check if the pid information is correct. - * If there is an error, it will panic. - * - * Input Parameters: - * val - this val carrying pid and original fd information - * - * Returned Value: none - * + * Public Functions ****************************************************************************/ int fdcheck_restore(int val) { - int pid_expect; - int pid_now; - int ppid_now; + uint8_t tag_store; + int fd; - if (val <= 2) + /* If val is a bare fd（0~255）, we should return it directly */ + + fd = (val >> FD_SHIFT) & FD_MASK; + if (fd == 0 || val < 0) { return val; } - pid_expect = (val >> PID_SHIFT); - pid_now = (_SCHED_GETPID() & PID_MASK); - ppid_now = (_SCHED_GETPPID() & PID_MASK); - if (pid_expect != pid_now && pid_expect != ppid_now && pid_expect != 0) + int ret = ioctl(fd, FIOC_GETTAG_FDCHECK, &tag_store); + if (ret >= 0) { - ferr("pid_expect %d pid_now %d ppid_now %d\n", - pid_expect, pid_now, ppid_now); - PANIC(); + uint8_t tag_expect = (val >> TAG_SHIFT) & TAG_MASK; + if (tag_expect != tag_store) + { + ferr("tag_expect 0x%x tag_store 0x%x\n", + tag_expect, tag_store); + PANIC(); + } } - return val & FD_MASK; + return fd; } -/**************************************************************************** - * Name: fdcheck_protect - * - * Description: Obtain the combined value of fd and pid - * - * the return value carries the pid and fd information. - * The original fd information is stored in low bit of val. - * The pid information is stored in high bit of val. - * For ease of understanding, let's give an example where - * the following information is represented in 32-bit binary format - * - * fd 00000000 00000000 00000000 10001010 - * pid 00000000 00000000 00000000 01010101 - * val 00000000 00000000 01010101 10001010 - * - * Input Parameters: - * fd - original fd - * - * Returned Value: the combined value of fd and pid - * - ****************************************************************************/ - int fdcheck_protect(int fd) { + int protect_fd; + uint8_t tag; + int ret; + if (fd <= 2) { return fd; } - return (fd & FD_MASK) | ((_SCHED_GETPID() & PID_MASK) << PID_SHIFT); + protect_fd = (fd & FD_MASK) << FD_SHIFT; + ret = ioctl(fd, FIOC_GETTAG_FDCHECK, &tag); + DEBUGASSERT(ret >= 0); + if (tag == 0) + { + irqstate_t flags = spin_lock_irqsave(&g_fdcheck_lock); + if ((++g_fdcheck_tag & TAG_MASK) == 0) + { + ++g_fdcheck_tag; + } + + g_fdcheck_tag &= TAG_MASK; + protect_fd |= g_fdcheck_tag << TAG_SHIFT; + ret = ioctl(fd, FIOC_SETTAG_FDCHECK, &g_fdcheck_tag); + DEBUGASSERT(ret == 0); + spin_unlock_irqrestore(&g_fdcheck_lock, flags); + } + else + { + protect_fd |= (tag & TAG_MASK) << TAG_SHIFT; + } + + return protect_fd; } #endif diff --git a/libs/libc/misc/lib_fdsan.c b/libs/libc/misc/lib_fdsan.c index b71b2ac4c4c6e..628aa652cb59f 100644 --- a/libs/libc/misc/lib_fdsan.c +++ b/libs/libc/misc/lib_fdsan.c @@ -151,7 +151,7 @@ void android_fdsan_exchange_owner_tag(int fd, uint64_t expected_tag, uint64_t tag; int ret; - ret = ioctl(fd, FIOC_GETTAG, &tag); + ret = ioctl(fd, FIOC_GETTAG_FDSAN, &tag); if (ret < 0) { return; @@ -159,7 +159,7 @@ void android_fdsan_exchange_owner_tag(int fd, uint64_t expected_tag, if (tag == expected_tag) { - ret = ioctl(fd, FIOC_SETTAG, &new_tag); + ret = ioctl(fd, FIOC_SETTAG_FDSAN, &new_tag); DEBUGASSERT(ret == 0); } else diff --git a/libs/libc/misc/lib_utsname.c b/libs/libc/misc/lib_utsname.c index 6bfe796186255..2ae7064f32718 100644 --- a/libs/libc/misc/lib_utsname.c +++ b/libs/libc/misc/lib_utsname.c @@ -93,7 +93,8 @@ int uname(FAR struct utsname *name) strlcpy(name->release, CONFIG_VERSION_STRING, sizeof(name->release)); -#if defined(__DATE__) && defined(__TIME__) +#if defined(__DATE__) && defined(__TIME__) && \ + !defined(CONFIG_LIBC_UNAME_DISABLE_TIMESTAMP) snprintf(name->version, VERSION_NAMELEN, "%s %s %s", CONFIG_VERSION_BUILD, __DATE__, __TIME__); #else diff --git a/libs/libc/obstack/lib_obstack_malloc.c b/libs/libc/obstack/lib_obstack_malloc.c index 71c2a76e520e5..8382ad5dc5025 100644 --- a/libs/libc/obstack/lib_obstack_malloc.c +++ b/libs/libc/obstack/lib_obstack_malloc.c @@ -66,6 +66,7 @@ FAR void *lib_obstack_malloc(size_t size) obstack_alloc_failed_handler(); PANIC(); + return NULL; } FAR void *lib_obstack_realloc(FAR void *ptr, size_t size) @@ -79,4 +80,5 @@ FAR void *lib_obstack_realloc(FAR void *ptr, size_t size) obstack_alloc_failed_handler(); PANIC(); + return NULL; } diff --git a/libs/libc/regex/regcomp.c b/libs/libc/regex/regcomp.c index 15bc80e4fefab..600b3c3ed78cb 100644 --- a/libs/libc/regex/regcomp.c +++ b/libs/libc/regex/regcomp.c @@ -418,7 +418,7 @@ static reg_errcode_t tre_stack_push(tre_stack_t *s, return REG_ESPACE; } - assert(new_size > s->size); + ASSERT(new_size > s->size); s->size = new_size; s->stack = new_buffer; tre_stack_push(s, value); @@ -1802,7 +1802,7 @@ static reg_errcode_t tre_add_tags(tre_mem_t mem, tre_stack_t *stack, break; } - assert(tnfa->submatch_data[id].parents == NULL); + ASSERT(tnfa->submatch_data[id].parents == NULL); tnfa->submatch_data[id].parents = p; for (i = 0; parents[i] >= 0; i++) { @@ -1870,7 +1870,7 @@ static reg_errcode_t tre_add_tags(tre_mem_t mem, tre_stack_t *stack, } else { - assert(!IS_TAG(lit)); + ASSERT(!IS_TAG(lit)); } break; } @@ -2219,7 +2219,7 @@ static reg_errcode_t tre_add_tags(tre_mem_t mem, tre_stack_t *stack, default: { - assert(0); + ASSERT(0); } break; @@ -2250,7 +2250,7 @@ static reg_errcode_t tre_add_tags(tre_mem_t mem, tre_stack_t *stack, num_minimals++; } - assert(tree->num_tags == num_tags); + ASSERT(tree->num_tags == num_tags); tnfa->end_tag = num_tags; tnfa->num_tags = num_tags; tnfa->num_minimals = num_minimals; @@ -2424,7 +2424,7 @@ static reg_errcode_t tre_copy_ast(tre_mem_t mem, tre_stack_t *stack, default: { - assert(0); + ASSERT(0); break; } } @@ -2537,7 +2537,7 @@ static reg_errcode_t tre_expand_ast(tre_mem_t mem, tre_stack_t *stack, default: { - assert(0); + ASSERT(0); break; } } @@ -2684,7 +2684,7 @@ static reg_errcode_t tre_expand_ast(tre_mem_t mem, tre_stack_t *stack, default: { - assert(0); + ASSERT(0); break; } } @@ -2935,7 +2935,7 @@ static reg_errcode_t tre_match_empty(tre_stack_t *stack, case ASSERTION: { - assert(lit->code_max >= 1 || lit->code_max <= ASSERT_LAST); + ASSERT(lit->code_max >= 1 || lit->code_max <= ASSERT_LAST); if (assertions != NULL) { *assertions |= lit->code_max; @@ -2950,7 +2950,7 @@ static reg_errcode_t tre_match_empty(tre_stack_t *stack, default: { - assert(0); + ASSERT(0); } break; } @@ -2970,7 +2970,7 @@ static reg_errcode_t tre_match_empty(tre_stack_t *stack, else if (uni->right->nullable) STACK_PUSHX(stack, voidptr, uni->right) else - assert(0); + ASSERT(0); } break; @@ -2979,8 +2979,8 @@ static reg_errcode_t tre_match_empty(tre_stack_t *stack, /* The path must go through both children. */ cat = (tre_catenation_t *)node->obj; - assert(cat->left->nullable); - assert(cat->right->nullable); + ASSERT(cat->left->nullable); + ASSERT(cat->right->nullable); STACK_PUSHX(stack, voidptr, cat->left); STACK_PUSHX(stack, voidptr, cat->right); } @@ -3002,7 +3002,7 @@ static reg_errcode_t tre_match_empty(tre_stack_t *stack, default: { - assert(0); + ASSERT(0); } break; } @@ -3323,7 +3323,7 @@ static reg_errcode_t tre_compute_nfl(tre_mem_t mem, tre_stack_t *stack, default: { - assert(0); + ASSERT(0); } break; } @@ -3419,8 +3419,8 @@ static reg_errcode_t tre_make_trans(tre_pos_and_tags_t *p1, NULL ? ASSERT_CHAR_CLASS_NEG : 0); if (p1->backref >= 0) { - assert((trans->assertions & ASSERT_CHAR_CLASS) == 0); - assert(p2->backref < 0); + ASSERT((trans->assertions & ASSERT_CHAR_CLASS) == 0); + ASSERT(p2->backref < 0); trans->u.backref = p1->backref; trans->assertions |= ASSERT_BACKREF; } @@ -3627,11 +3627,11 @@ static reg_errcode_t tre_ast_to_tnfa(tre_ast_node_t *node, case ITERATION: { iter = (tre_iteration_t *)node->obj; - assert(iter->max == -1 || iter->max == 1); + ASSERT(iter->max == -1 || iter->max == 1); if (iter->max == -1) { - assert(iter->min == 0 || iter->min == 1); + ASSERT(iter->min == 0 || iter->min == 1); /* Add a transition from each last position in the iterated * expression to each first position. diff --git a/libs/libc/regex/regexec.c b/libs/libc/regex/regexec.c index f39bf5334dbfe..0a9dfb8427af4 100644 --- a/libs/libc/regex/regexec.c +++ b/libs/libc/regex/regexec.c @@ -133,7 +133,7 @@ static int tre_tag_order(int num_tags, tre_tag_direction_t *tag_directions, } } - /* assert(0); */ + /* ASSERT(0); */ return 0; } @@ -508,7 +508,7 @@ static reg_errcode_t tre_tnfa_run_parallel(const tre_tnfa_t *tnfa, else { - assert(reach_pos[trans_i->state_id].pos == pos); + ASSERT(reach_pos[trans_i->state_id].pos == pos); /* Another path has also reached this state. We choose * the winner by examining the tag values for both @@ -681,7 +681,7 @@ typedef struct tre_backtrack_struct *tre_backtrack_t; do \ { \ int i; \ - assert(stack->prev); \ + ASSERT(stack->prev); \ pos = stack->item.pos; \ str_byte = stack->item.str_byte; \ state = stack->item.state; \ @@ -1181,10 +1181,10 @@ static void tre_fill_pmatch(size_t nmatch, regmatch_t pmatch[], int cflags, { if (pmatch[i].rm_eo == -1) { - assert(pmatch[i].rm_so == -1); + ASSERT(pmatch[i].rm_so == -1); } - assert(pmatch[i].rm_so <= pmatch[i].rm_eo); + ASSERT(pmatch[i].rm_so <= pmatch[i].rm_eo); parents = submatch_data[i].parents; if (parents != NULL) diff --git a/libs/libc/search/CMakeLists.txt b/libs/libc/search/CMakeLists.txt new file mode 100644 index 0000000000000..3c32686e94421 --- /dev/null +++ b/libs/libc/search/CMakeLists.txt @@ -0,0 +1,23 @@ +# ############################################################################## +# libs/libc/search/CMakeLists.txt +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(SRCS hash_func.c hcreate.c hcreate_r.c) + +target_sources(c PRIVATE ${SRCS}) diff --git a/libs/libc/search/Make.defs b/libs/libc/search/Make.defs new file mode 100644 index 0000000000000..a22ea40bb3aeb --- /dev/null +++ b/libs/libc/search/Make.defs @@ -0,0 +1,28 @@ +############################################################################ +# libs/libc/search/Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Add the search C files to the build + +CSRCS += hcreate_r.c hcreate.c hash_func.c + +# Add the search directory to the build + +DEPPATH += --dep-path search +VPATH += :search diff --git a/libs/libc/search/hash_func.c b/libs/libc/search/hash_func.c new file mode 100644 index 0000000000000..c237121085bae --- /dev/null +++ b/libs/libc/search/hash_func.c @@ -0,0 +1,126 @@ +/**************************************************************************** + * libs/libc/search/hash_func.c + * + * Copyright (c) 1990, 1993 + * The Regents of the University of California. All rights reserved. + * + * This code is derived from software contributed to Berkeley by + * Margo Seltzer. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the University nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define HASH4 h = (h << 5) + h + *key++; + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +static uint32_t hash4(FAR const void *, size_t); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Global default hash function */ + +uint32_t (*g_default_hash)(FAR const void *, size_t) = hash4; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/* Hash function from Chris Torek. */ + +static uint32_t hash4(FAR const void *keyarg, size_t len) +{ + FAR const u_char *key = keyarg; + uint32_t h = 0; + size_t loop; + + if (len > 0) + { + loop = (len + 8 - 1) >> 3; + switch (len & (8 - 1)) + { + case 0: + do + { + HASH4; + + /* FALLTHROUGH */ + + case 7: + HASH4; + + /* FALLTHROUGH */ + + case 6: + HASH4; + + /* FALLTHROUGH */ + + case 5: + HASH4; + + /* FALLTHROUGH */ + + case 4: + HASH4; + + /* FALLTHROUGH */ + + case 3: + HASH4; + + /* FALLTHROUGH */ + + case 2: + HASH4; + + /* FALLTHROUGH */ + + case 1: + HASH4; + } + while (--loop); + } + } + + return h; +} diff --git a/libs/libc/search/hcreate.c b/libs/libc/search/hcreate.c new file mode 100644 index 0000000000000..ae64ec9676ae7 --- /dev/null +++ b/libs/libc/search/hcreate.c @@ -0,0 +1,140 @@ +/**************************************************************************** + * libs/libc/search/hcreate.c + * + * $NetBSD: hcreate.c,v 1.2 2001/02/19 21:26:04 ross Exp $ + * + * Copyright (c) 2001 Christopher G. Demetriou + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * <> + * + * + * hcreate() / hsearch() / hdestroy() + * + * SysV/XPG4 hash table functions. + * + * Implementation done based on NetBSD manual page and Solaris manual page, + * plus my own personal experience about how they're supposed to work. + * + * I tried to look at Knuth (as cited by the Solaris manual page), but + * nobody had a copy in the office, so... + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct hsearch_data g_htab; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: hcreate + * + * Description: + * The hcreate() function creates a new hashing table with nel elements. + * The hashing table will be used by subsequent calls to hsearch() with + * the same htab argument. The hashing table is initialized with nel + * hashing buckets. + * + * The hcreate_r() function is the reentrant version of hcreate(). + * + * Returned Value: + * If successful, hcreate() and hcreate_r() return 1; otherwise, they + * return 0. + * + ****************************************************************************/ + +int hcreate(size_t nel) +{ + return hcreate_r(nel, &g_htab); +} + +/**************************************************************************** + * Name: hdestroy + * + * Description: + * The hdestroy() function destroys the hashing table specified by htab. + * The hashing table is destroyed only if there are no entries in the + * table. The hashing table cannot be used again until hcreate() or + * hcreate_r() is called. + * + * The hdestroy_r() function is the reentrant version of hdestroy(). + * + * Returned Value: + * None + * + ****************************************************************************/ + +void hdestroy(void) +{ + hdestroy_r(&g_htab); +} + +/**************************************************************************** + * Name: hsearch + * + * Description: + * The hsearch() function searches the hashing table specified by htab + * for an entry with a key matching that of item. If such an entry is + * found, hsearch() returns a pointer to the entry's data object. If + * such an entry is not found, hsearch() creates a new entry using the + * key and data objects specified by item and returns a pointer to the + * new entry's data object. + * + * The hsearch_r() function is the reentrant version of hsearch(). + * + * Returned Value: + * If successful, hsearch() and hsearch_r() return a pointer to the data + * object of the matching or newly created entry. Otherwise, they return + * NULL. + * + ****************************************************************************/ + +FAR ENTRY *hsearch(ENTRY item, ACTION action) +{ + FAR ENTRY *retval; + + hsearch_r(item, action, &retval, &g_htab); + + return retval; +} diff --git a/libs/libc/search/hcreate_r.c b/libs/libc/search/hcreate_r.c new file mode 100644 index 0000000000000..6c35e78032e55 --- /dev/null +++ b/libs/libc/search/hcreate_r.c @@ -0,0 +1,280 @@ +/**************************************************************************** + * libs/libc/search/hcreate_r.c + * + * $NetBSD: hcreate.c,v 1.2 2001/02/19 21:26:04 ross Exp $ + * + * Copyright (c) 2001 Christopher G. Demetriou + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * <> + * + * hcreate() / hsearch() / hdestroy() + * + * SysV/XPG4 hash table functions. + * + * Implementation done based on NetBSD manual page and Solaris manual page, + * plus my own personal experience about how they're supposed to work. + * + * I tried to look at Knuth (as cited by the Solaris manual page), but + * nobody had a copy in the office, so... + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include +#include + +#include "libc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define MIN_BUCKETS_LG2 4 +#define MIN_BUCKETS (1 << MIN_BUCKETS_LG2) +#define MAX_BUCKETS_LG2 (sizeof (size_t) * 8 - 1 - 5) +#define MAX_BUCKETS ((size_t)1 << MAX_BUCKETS_LG2) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct internal_entry +{ + SLIST_ENTRY(internal_entry) link; + ENTRY ent; +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +SLIST_HEAD(internal_head, internal_entry); +extern uint32_t (*g_default_hash)(FAR const void *, size_t); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: hcreate_r + * + * Description: + * Create a new hash table. + * + * Input Parameters: + * nel - The number of elements in the hash table. + * htab - The location to return the hash table reference. + * + * Returned Value: + * 1 on success; 0 on failure with errno set appropriately. + * + ****************************************************************************/ + +int hcreate_r(size_t nel, FAR struct hsearch_data *htab) +{ + size_t idx; + unsigned int p2; + + /* Make sure this this isn't called when a table already exists. */ + + if (htab->htable != NULL) + { + _NX_SETERRNO(-EINVAL); + return 0; + } + + /* If nel is too small, make it min sized. */ + + if (nel < MIN_BUCKETS) + { + nel = MIN_BUCKETS; + } + + /* If it's too large, cap it. */ + + if (nel > MAX_BUCKETS) + { + nel = MAX_BUCKETS; + } + + /* If it's is not a power of two in size, round up. */ + + if ((nel & (nel - 1)) != 0) + { + for (p2 = 0; nel != 0; p2++) + { + nel >>= 1; + } + + nel = 1 << p2; + } + + /* Allocate the table. */ + + htab->htablesize = nel; + htab->htable = lib_malloc(htab->htablesize * sizeof htab->htable[0]); + if (htab->htable == NULL) + { + _NX_SETERRNO(-ENOMEM); + return 0; + } + + /* Initialize it. */ + + for (idx = 0; idx < htab->htablesize; idx++) + { + SLIST_INIT(&(htab->htable[idx])); + } + + return 1; +} + +/**************************************************************************** + * Name: hdestroy_r + * + * Description: + * Destroy a hash table. + * + * Input Parameters: + * htab - The hash table to be destroyed. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void hdestroy_r(FAR struct hsearch_data *htab) +{ + FAR struct internal_entry *ie; + size_t idx; + + if (htab->htable == NULL) + { + return; + } + + for (idx = 0; idx < htab->htablesize; idx++) + { + while (!SLIST_EMPTY(&(htab->htable[idx]))) + { + ie = SLIST_FIRST(&(htab->htable[idx])); + SLIST_REMOVE_HEAD(&(htab->htable[idx]), link); + lib_free(ie->ent.key); + lib_free(ie->ent.data); + lib_free(ie); + } + } + + lib_free(htab->htable); + htab->htable = NULL; +} + +/**************************************************************************** + * Name: hsearch_r + * + * Description: + * Search for an entry in a hash table. + * + * Input Parameters: + * item - The search key + * action - The action to take if the item is not found + * retval - The location to return the search result + * htab - The hash table to be searched + * + * Returned Value: + * 1 on success; 0 on failure with errno set appropriately. + * + ****************************************************************************/ + +int hsearch_r(ENTRY item, ACTION action, FAR ENTRY **retval, + FAR struct hsearch_data *htab) +{ + FAR struct internal_head *head; + FAR struct internal_entry *ie; + uint32_t hashval; + size_t len; + + len = strlen(item.key); + hashval = (*g_default_hash)(item.key, len); + + head = &(htab->htable[hashval & (htab->htablesize - 1)]); + ie = SLIST_FIRST(head); + while (ie != NULL) + { + if (strcmp(ie->ent.key, item.key) == 0) + { + break; + } + + ie = SLIST_NEXT(ie, link); + } + + if (action == DELETE) + { + if (ie != NULL) + { + SLIST_REMOVE(head, ie, internal_entry, link); + lib_free(ie->ent.key); + lib_free(ie->ent.data); + lib_free(ie); + return 1; + } + + return 0; + } + else if (ie != NULL) + { + *retval = &ie->ent; + return 1; + } + else if (action == FIND) + { + *retval = NULL; + return 0; + } + + ie = lib_malloc(sizeof *ie); + if (ie == NULL) + { + *retval = NULL; + return 0; + } + + ie->ent.key = item.key; + ie->ent.data = item.data; + + SLIST_INSERT_HEAD(head, ie, link); + *retval = &ie->ent; + return 1; +} diff --git a/libs/libc/stdio/lib_fclose.c b/libs/libc/stdio/lib_fclose.c index 174238c45f68c..98b28ed417b26 100644 --- a/libs/libc/stdio/lib_fclose.c +++ b/libs/libc/stdio/lib_fclose.c @@ -59,8 +59,6 @@ int fclose(FAR FILE *stream) { FAR struct streamlist *slist; - FAR FILE *prev = NULL; - FAR FILE *next; int errcode = EINVAL; int ret = ERROR; int status; @@ -91,27 +89,7 @@ int fclose(FAR FILE *stream) slist = lib_get_streams(); nxmutex_lock(&slist->sl_lock); - for (next = slist->sl_head; next; prev = next, next = next->fs_next) - { - if (next == stream) - { - if (next == slist->sl_head) - { - slist->sl_head = next->fs_next; - } - else - { - prev->fs_next = next->fs_next; - } - - if (next == slist->sl_tail) - { - slist->sl_tail = prev; - } - - break; - } - } + sq_rem(&stream->fs_entry, &slist->sl_queue); nxmutex_unlock(&slist->sl_lock); diff --git a/libs/libc/stdio/lib_fopen.c b/libs/libc/stdio/lib_fopen.c index d446e0960cb72..1576ee41f7560 100644 --- a/libs/libc/stdio/lib_fopen.c +++ b/libs/libc/stdio/lib_fopen.c @@ -98,22 +98,19 @@ FAR FILE *fdopen(int fd, FAR const char *mode) goto errout; } - if (list->sl_tail) - { - list->sl_tail->fs_next = filep; - list->sl_tail = filep; - } - else - { - list->sl_head = filep; - list->sl_tail = filep; - } + sq_addlast(&filep->fs_entry, &list->sl_queue); nxmutex_unlock(&list->sl_lock); /* Initialize the mutex the manages access to the buffer */ nxrmutex_init(&filep->fs_lock); + +#ifdef CONFIG_FDSAN + android_fdsan_exchange_owner_tag(fd, 0, + android_fdsan_create_owner_tag(ANDROID_FDSAN_OWNER_TYPE_FILE, + (uintptr_t)filep)); +#endif } else { @@ -144,12 +141,6 @@ FAR FILE *fdopen(int fd, FAR const char *mode) filep->fs_cookie = (FAR void *)(intptr_t)fd; filep->fs_oflags = oflags; -#ifdef CONFIG_FDSAN - android_fdsan_exchange_owner_tag(fd, 0, - android_fdsan_create_owner_tag(ANDROID_FDSAN_OWNER_TYPE_FILE, - (uintptr_t)filep)); -#endif - /* Assign custom callbacks to NULL. */ filep->fs_iofunc.read = NULL; @@ -324,7 +315,6 @@ int lib_mode2oflags(FAR const char *mode) default: goto errout; - break; } break; @@ -401,7 +391,6 @@ int lib_mode2oflags(FAR const char *mode) default: goto errout; - break; } } diff --git a/libs/libc/stdio/lib_libflushall.c b/libs/libc/stdio/lib_libflushall.c index 2c4f37c592c9f..f8b60b27c7523 100644 --- a/libs/libc/stdio/lib_libflushall.c +++ b/libs/libc/stdio/lib_libflushall.c @@ -28,6 +28,7 @@ #include #include +#include #include #include "libc.h" @@ -47,6 +48,7 @@ int lib_flushall_unlocked(FAR struct streamlist *list) { + FAR sq_entry_t *entry; int lasterrno = OK; int ret; @@ -64,8 +66,10 @@ int lib_flushall_unlocked(FAR struct streamlist *list) lib_fflush_unlocked(&list->sl_std[i]); } - for (stream = list->sl_head; stream != NULL; stream = stream->fs_next) + sq_for_every(&list->sl_queue, entry) { + stream = container_of(entry, struct file_struct, fs_entry); + /* If the stream is opened for writing, then flush all of * the pending write data in the stream. */ @@ -95,6 +99,7 @@ int lib_flushall_unlocked(FAR struct streamlist *list) int lib_flushall(FAR struct streamlist *list) { + FAR sq_entry_t *entry; int lasterrno = OK; int ret; @@ -114,8 +119,10 @@ int lib_flushall(FAR struct streamlist *list) lib_fflush(&list->sl_std[i]); } - for (stream = list->sl_head; stream != NULL; stream = stream->fs_next) + sq_for_every(&list->sl_queue, entry) { + stream = container_of(entry, struct file_struct, fs_entry); + /* If the stream is opened for writing, then flush all of * the pending write data in the stream. */ diff --git a/libs/libc/stdlib/CMakeLists.txt b/libs/libc/stdlib/CMakeLists.txt index bc233a9b74589..f2a21cd7da336 100644 --- a/libs/libc/stdlib/CMakeLists.txt +++ b/libs/libc/stdlib/CMakeLists.txt @@ -39,6 +39,7 @@ set(SRCS lib_bsearch.c lib_rand.c lib_rand48.c + lib_reallocarray.c lib_qsort.c lib_srand.c lib_strtol.c diff --git a/libs/libc/stdlib/Make.defs b/libs/libc/stdlib/Make.defs index be2833c1d9a32..4f719d4a04512 100644 --- a/libs/libc/stdlib/Make.defs +++ b/libs/libc/stdlib/Make.defs @@ -28,6 +28,7 @@ CSRCS += lib_strtoll.c lib_strtoul.c lib_strtoull.c lib_strtold.c CSRCS += lib_checkbase.c lib_mktemp.c lib_mkstemp.c lib_mkdtemp.c CSRCS += lib_aligned_alloc.c lib_posix_memalign.c lib_valloc.c lib_mblen.c CSRCS += lib_mbtowc.c lib_wctomb.c lib_mbstowcs.c lib_wcstombs.c lib_atexit.c +CSRCS += lib_reallocarray.c ifeq ($(CONFIG_PSEUDOTERM),y) CSRCS += lib_ptsname.c lib_ptsnamer.c lib_unlockpt.c lib_openpty.c diff --git a/libs/libc/stdlib/lib_getprogname.c b/libs/libc/stdlib/lib_getprogname.c index a0a712151b23d..6d1f541659ad4 100644 --- a/libs/libc/stdlib/lib_getprogname.c +++ b/libs/libc/stdlib/lib_getprogname.c @@ -40,5 +40,5 @@ FAR const char *getprogname(void) FAR struct task_info_s *info; info = task_get_info(); - return info->argv[0]; + return info->ta_argv[0]; } diff --git a/libs/libc/stdlib/lib_reallocarray.c b/libs/libc/stdlib/lib_reallocarray.c new file mode 100644 index 0000000000000..1931a9891dbc6 --- /dev/null +++ b/libs/libc/stdlib/lib_reallocarray.c @@ -0,0 +1,78 @@ +/**************************************************************************** + * libs/libc/stdlib/lib_reallocarray.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include "libc.h" + +/**************************************************************************** + * Pre-processor definitions + ****************************************************************************/ + +/* Set overflow control only if larger than 65536 for bit platforms. The + * limit is the same as in OpenBSD. + */ + +#define CHECK_OVERFLOW_LIMIT (1UL << (sizeof(size_t) * 4)) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: reallocarray + * + * Description: + * The reallocarray function has the same functionality as realloc but + * it fails safely if multiplication overflow occurs. + * + * Input Parameters: + * ptr - old memory to be reallocated and freed + * nmemb - number of elements + * size - size of one element in bytes + * + * Returned Value: + * Upon successful completion, the address of the re-allocated memory + * is returned and previous pointer is freed. NULL is returned on error + * with original block of memory left unchanged. + * + ****************************************************************************/ + +FAR void *reallocarray(FAR void *ptr, size_t nmemb, size_t size) +{ + if (nmemb != 0 && (nmemb >= CHECK_OVERFLOW_LIMIT || + size >= CHECK_OVERFLOW_LIMIT)) + { + /* Do division only if at least one element is larget than limit */ + + if ((SIZE_MAX / nmemb) < size) + { + set_errno(ENOMEM); + return NULL; + } + } + + return lib_realloc(ptr, nmemb * size); +} diff --git a/libs/libc/string/Make.defs b/libs/libc/string/Make.defs index cec3d1ff6269a..54989a901cd01 100644 --- a/libs/libc/string/Make.defs +++ b/libs/libc/string/Make.defs @@ -30,7 +30,7 @@ CSRCS += lib_strndup.c lib_strcasestr.c lib_strpbrk.c lib_strrchr.c CSRCS += lib_strspn.c lib_strstr.c lib_strtok.c lib_strtokr.c CSRCS += lib_strsep.c lib_strerrorr.c lib_explicit_bzero.c lib_strsignal.c CSRCS += lib_index.c lib_rindex.c lib_timingsafe_bcmp.c lib_strverscmp.c -CSRCS += lib_mempcpy.c lib_rawmemchr.c +CSRCS += lib_mempcpy.c lib_rawmemchr.c lib_bzero.c CSRCS += lib_memchr.c lib_memcmp.c lib_memmove.c lib_memset.c CSRCS += lib_strchr.c lib_strcmp.c lib_strcpy.c lib_strlcat.c diff --git a/libs/libc/string/lib_bzero.c b/libs/libc/string/lib_bzero.c new file mode 100644 index 0000000000000..a0dfeace4eab8 --- /dev/null +++ b/libs/libc/string/lib_bzero.c @@ -0,0 +1,40 @@ +/**************************************************************************** + * libs/libc/string/lib_bzero.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: bzero + ****************************************************************************/ + +void bzero(FAR void *s, size_t n) +{ + memset(s, 0, n); +} diff --git a/libs/libc/string/lib_ffs.c b/libs/libc/string/lib_ffs.c index 30f185b038def..3ee8feff64e4b 100644 --- a/libs/libc/string/lib_ffs.c +++ b/libs/libc/string/lib_ffs.c @@ -18,13 +18,6 @@ * ****************************************************************************/ -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -55,13 +48,6 @@ int ffs(int j) if (j != 0) { -#ifdef CONFIG_HAVE_BUILTIN_FFS - ret = __builtin_ffs(j); -#elif defined (CONFIG_HAVE_BUILTIN_CTZ) - /* Count trailing zeros function can be used to implement ffs. */ - - ret = __builtin_ctz(j) + 1; -#else unsigned int value = (unsigned int)j; int bitno; @@ -73,7 +59,6 @@ int ffs(int j) break; } } -#endif } return ret; diff --git a/libs/libc/string/lib_ffsl.c b/libs/libc/string/lib_ffsl.c index 63acc95064caf..b7a8a884ccb24 100644 --- a/libs/libc/string/lib_ffsl.c +++ b/libs/libc/string/lib_ffsl.c @@ -18,13 +18,6 @@ * ****************************************************************************/ -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -55,13 +48,6 @@ int ffsl(long j) if (j != 0) { -#ifdef CONFIG_HAVE_BUILTIN_FFSL - ret = __builtin_ffsl(j); -#elif defined (CONFIG_HAVE_BUILTIN_CTZ) - /* Count trailing zeros function can be used to implement ffs. */ - - ret = __builtin_ctzl(j) + 1; -#else unsigned long value = (unsigned long)j; int bitno; @@ -73,7 +59,6 @@ int ffsl(long j) break; } } -#endif } return ret; diff --git a/libs/libc/string/lib_ffsll.c b/libs/libc/string/lib_ffsll.c index 6fc45a880e627..11e07b1a59df7 100644 --- a/libs/libc/string/lib_ffsll.c +++ b/libs/libc/string/lib_ffsll.c @@ -18,13 +18,6 @@ * ****************************************************************************/ -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -57,13 +50,6 @@ int ffsll(long long j) if (j != 0) { -#ifdef CONFIG_HAVE_BUILTIN_FFSLL - ret = __builtin_ffsll(j); -#elif defined (CONFIG_HAVE_BUILTIN_CTZ) - /* Count trailing zeros function can be used to implement ffs. */ - - ret = __builtin_ctzll(j) + 1; -#else unsigned long long value = (unsigned long long)j; int bitno; @@ -75,10 +61,8 @@ int ffsll(long long j) break; } } -#endif } return ret; } - #endif diff --git a/libs/libc/string/lib_fls.c b/libs/libc/string/lib_fls.c index 1d1a367b3d71c..e5ff8188a712b 100644 --- a/libs/libc/string/lib_fls.c +++ b/libs/libc/string/lib_fls.c @@ -18,13 +18,6 @@ * ****************************************************************************/ -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -55,11 +48,6 @@ int fls(int j) if (j != 0) { -#ifdef CONFIG_HAVE_BUILTIN_CLZ - /* Count leading zeros function can be used to implement fls. */ - - ret = NBITS - __builtin_clz(j); -#else unsigned int value = (unsigned int)j; int bitno; @@ -71,7 +59,6 @@ int fls(int j) break; } } -#endif } return ret; diff --git a/libs/libc/string/lib_flsl.c b/libs/libc/string/lib_flsl.c index 9e166fe8cfe37..6c0f8b5c9c055 100644 --- a/libs/libc/string/lib_flsl.c +++ b/libs/libc/string/lib_flsl.c @@ -18,13 +18,6 @@ * ****************************************************************************/ -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -55,11 +48,6 @@ int flsl(long j) if (j != 0) { -#ifdef CONFIG_HAVE_BUILTIN_CLZ - /* Count leading zeros function can be used to implement fls. */ - - ret = NBITS - __builtin_clzl(j); -#else unsigned long value = (unsigned long)j; int bitno; @@ -71,7 +59,6 @@ int flsl(long j) break; } } -#endif } return ret; diff --git a/libs/libc/string/lib_flsll.c b/libs/libc/string/lib_flsll.c index bd788e2b91ca6..c81e3e6896733 100644 --- a/libs/libc/string/lib_flsll.c +++ b/libs/libc/string/lib_flsll.c @@ -18,13 +18,6 @@ * ****************************************************************************/ -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -57,11 +50,6 @@ int flsll(long long j) if (j != 0) { -#ifdef CONFIG_HAVE_BUILTIN_CLZ - /* Count leading zeros function can be used to implement fls. */ - - ret = NBITS - __builtin_clzll(j); -#else unsigned long long value = (unsigned long long)j; int bitno; @@ -73,10 +61,8 @@ int flsll(long long j) break; } } -#endif } return ret; } - #endif diff --git a/libs/libc/string/lib_memmem.c b/libs/libc/string/lib_memmem.c index 77dbd4b3573ee..f54ea9817c118 100644 --- a/libs/libc/string/lib_memmem.c +++ b/libs/libc/string/lib_memmem.c @@ -51,12 +51,17 @@ FAR void *memmem(FAR const void *haystack, size_t haystacklen, size_t i; size_t y; + if (needlelen == 0) + { + return (void *)haystack; + } + if (needlelen > haystacklen) { return NULL; } - for (i = 0; i < haystacklen - needlelen; i++) + for (i = 0; i <= haystacklen - needlelen; i++) { y = 0; while (h[i + y] == n[y]) diff --git a/libs/libc/string/lib_strcasestr.c b/libs/libc/string/lib_strcasestr.c index 369044253d31f..9ccddaff167c0 100644 --- a/libs/libc/string/lib_strcasestr.c +++ b/libs/libc/string/lib_strcasestr.c @@ -92,7 +92,7 @@ FAR char *strcasestr(FAR const char *str, FAR const char *substr) * substring. */ - return NULL; + break; } /* Check if this is the beginning of a matching substring diff --git a/libs/libc/symtab/symtab_findbyvalue.c b/libs/libc/symtab/symtab_findbyvalue.c index 86ac0819324fe..eaed5a0bb7407 100644 --- a/libs/libc/symtab/symtab_findbyvalue.c +++ b/libs/libc/symtab/symtab_findbyvalue.c @@ -92,7 +92,7 @@ symtab_findbyvalue(FAR const struct symtab_s *symtab, } else if (symtab[mid].sym_value < value) { - if (symtab[mid + 1].sym_value >= value) + if (symtab[mid + 1].sym_value > value) { break; } diff --git a/libs/libc/tls/tls_getinfo.c b/libs/libc/tls/tls_getinfo.c index 25ed601280caf..8f65df48d91de 100644 --- a/libs/libc/tls/tls_getinfo.c +++ b/libs/libc/tls/tls_getinfo.c @@ -28,6 +28,7 @@ #include #include +#include #if !defined(up_tls_info) && (defined(__KERNEL__) || !defined(CONFIG_TLS_ALIGNED)) diff --git a/libs/libc/unistd/Make.defs b/libs/libc/unistd/Make.defs index c30bc721bec1b..6605e2fdbd062 100644 --- a/libs/libc/unistd/Make.defs +++ b/libs/libc/unistd/Make.defs @@ -30,6 +30,7 @@ CSRCS += lib_setrlimit.c lib_getrlimit.c lib_setpriority.c lib_getpriority.c CSRCS += lib_futimes.c lib_lutimes.c lib_gethostname.c lib_sethostname.c CSRCS += lib_fchownat.c lib_linkat.c lib_readlinkat.c lib_symlinkat.c CSRCS += lib_unlinkat.c lib_usleep.c lib_getpgrp.c lib_getpgid.c +CSRCS += lib_lockf.c ifneq ($(CONFIG_SCHED_USER_IDENTITY),y) CSRCS += lib_setuid.c lib_setgid.c lib_getuid.c lib_getgid.c diff --git a/libs/libc/unistd/lib_getopt_common.c b/libs/libc/unistd/lib_getopt_common.c index be3e22a21a5c5..cede600c67765 100644 --- a/libs/libc/unistd/lib_getopt_common.c +++ b/libs/libc/unistd/lib_getopt_common.c @@ -153,7 +153,6 @@ static int getopt_long_option(FAR struct getopt_s *go, default: goto errout; - break; } } else @@ -213,7 +212,6 @@ static int getopt_long_option(FAR struct getopt_s *go, default: goto errout; - break; } } diff --git a/libs/libc/unistd/lib_lockf.c b/libs/libc/unistd/lib_lockf.c new file mode 100644 index 0000000000000..4ceade3cc7352 --- /dev/null +++ b/libs/libc/unistd/lib_lockf.c @@ -0,0 +1,117 @@ +/**************************************************************************** + * libs/libc/unistd/lib_lockf.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: lockf + * + * Description: + * lockf() is a function that allows a process to apply or remove an + * advisory lock on an open file. The lock can be either a shared (read) + * lock or an exclusive (write) lock. This lock is advisory, meaning that + * it is not enforced by the system and it is up to cooperating processes + * to honor the lock. + * + * Input Parameters: + * fd - File descriptor of the open file. + * cmd - Specifies the type of lock operation to be performed. + * It can be one of the following: + * F_LOCK: Request an exclusive (write) lock. If the lock is not + * available, the call may block until it can be acquired. + * F_TLOCK: Try to request an exclusive (write) lock. If the lock is not + * available, the call will not block and will return + * immediately. + * F_ULOCK: Unlock an existing lock. + * F_TEST: Test the lock. Returns 0 if the file is unlocked or locked by + * the calling process, or -1 with errno set to EACCES if another + * process holds the lock. + * len - Length of the locked region, relative to the current file + * position. + * + * Returned Value: + * The returned value of lockf() depends on the success or failure of the + * operation. On success, the return value is 0. On failure, the return + * value is -1, and the errno variable is set to indicate the specific + * error. + * + ****************************************************************************/ + +int lockf(int fd, int cmd, off_t len) +{ + struct flock lock; + + lock.l_whence = SEEK_CUR; + lock.l_start = 0; + lock.l_len = len; + + switch (cmd) + { + case F_LOCK: + { + lock.l_type = F_WRLCK; + return fcntl(fd, F_SETLKW, &lock); + } + + case F_TLOCK: + { + lock.l_type = F_WRLCK; + return fcntl(fd, F_SETLK, &lock); + } + + case F_ULOCK: + { + lock.l_type = F_UNLCK; + return fcntl(fd, F_SETLK, &lock); + } + + case F_TEST: + { + lock.l_type = F_RDLCK; + if (fcntl(fd, F_GETLK, &lock) < 0) + { + return ERROR; + } + + /* Check result */ + + if (lock.l_type == F_UNLCK || lock.l_pid == getpid()) + { + return OK; + } + + set_errno(EACCES); + return ERROR; + } + } + + set_errno(EINVAL); + return ERROR; +} diff --git a/libs/libc/wctype/lib_iswctype.c b/libs/libc/wctype/lib_iswctype.c index 235b8e18eca63..034ea9b7991aa 100644 --- a/libs/libc/wctype/lib_iswctype.c +++ b/libs/libc/wctype/lib_iswctype.c @@ -147,7 +147,7 @@ int iswctype(wint_t c, wctype_t desc) return iswxdigit(c); default: - return 0; /* eliminate warning */ + break; /* eliminate warning */ } /* Otherwise unknown */ diff --git a/libs/libm/libm/CMakeLists.txt b/libs/libm/libm/CMakeLists.txt index 5b406cc8ee0b0..af794c0125b88 100644 --- a/libs/libm/libm/CMakeLists.txt +++ b/libs/libm/libm/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# libs/libc/math/CMakeLists.txt +# libs/libm/libm/CMakeLists.txt # # Licensed to the Apache Software Foundation (ASF) under one or more contributor # license agreements. See the NOTICE file distributed with this work for diff --git a/libs/libm/newlib/0003-newlib-fix-compilation-for-x86.patch b/libs/libm/newlib/0003-newlib-fix-compilation-for-x86.patch new file mode 100644 index 0000000000000..eea5de8e5c130 --- /dev/null +++ b/libs/libm/newlib/0003-newlib-fix-compilation-for-x86.patch @@ -0,0 +1,39 @@ +From 3035e2e223999497364dbc54b881ebc958be701c Mon Sep 17 00:00:00 2001 +From: p-szafonimateusz +Date: Thu, 22 Feb 2024 15:05:36 +0100 +Subject: [PATCH] newlib: fix compilation for x86 + +Change-Id: I5286ef72e358010ea7b4805e6087b06f67e42d44 +Signed-off-by: p-szafonimateusz +--- + newlib/libc/machine/shared_x86/sys/fenv.h | 1 + + newlib/libm/machine/shared_x86/fenv.c | 1 + + 2 files changed, 2 insertions(+) + +diff --git a/newlib/newlib/newlib/libc/machine/shared_x86/sys/fenv.h newlib/newlib/newlib/libc/machine/shared_x86/sys/fenv.h +index 243cac27a..be39db4d0 100644 +--- a/newlib/newlib/newlib/libc/machine/shared_x86/sys/fenv.h ++++ newlib/newlib/newlib/libc/machine/shared_x86/sys/fenv.h +@@ -30,6 +30,7 @@ + #define _SYS_FENV_H 1 + + #include ++#include + + #ifdef __cplusplus + extern "C" { +diff --git a/newlib/newlib/newlib/libm/machine/shared_x86/fenv.c newlib/newlib/newlib/libm/machine/shared_x86/fenv.c +index ccc08e2d8..892a8b2cd 100644 +--- a/newlib/newlib/newlib/libm/machine/shared_x86/fenv.c ++++ newlib/newlib/newlib/libm/machine/shared_x86/fenv.c +@@ -5,6 +5,7 @@ + */ + + #define _GNU_SOURCE // for FE_NOMASK_ENV ++#define __GNU_VISIBLE 1 + + #include + #include +-- +2.43.1 + diff --git a/libs/libm/newlib/CMakeLists.txt b/libs/libm/newlib/CMakeLists.txt index 34004646de86a..7fdba7589484f 100644 --- a/libs/libm/newlib/CMakeLists.txt +++ b/libs/libm/newlib/CMakeLists.txt @@ -40,7 +40,9 @@ if(CONFIG_LIBM_NEWLIB) patch -p1 -d ${CMAKE_CURRENT_LIST_DIR} < ${CMAKE_CURRENT_LIST_DIR}/0001-newlib-libm-fix-__RCSID-build-error.patch && patch -p1 -d ${CMAKE_CURRENT_LIST_DIR} < - ${CMAKE_CURRENT_LIST_DIR}/0002-newlib-libm-remove-include-reent.h.patch) + ${CMAKE_CURRENT_LIST_DIR}/0002-newlib-libm-remove-include-reent.h.patch + && patch -p1 -d ${CMAKE_CURRENT_LIST_DIR} < + ${CMAKE_CURRENT_LIST_DIR}/0003-newlib-fix-compilation-for-x86.patch) FetchContent_GetProperties(newlib_fetch) @@ -85,8 +87,18 @@ if(CONFIG_LIBM_NEWLIB) file(GLOB_RECURSE ARCH_CSRCS ${NEWLIB_DIR}/newlib/libm/machine/${ARCH_DIR}/*.c) + if(CONFIG_ARCH_X86_64) + file(GLOB_RECURSE ARCH_CSRCS ${NEWLIB_DIR}/newlib/libm/fenv/*.c) + endif() + set(CSRCS ${COMMON_CSRCS} ${COMPLEX_CSRCS} ${ARCH_CSRCS}) + # aggresive optimisation can replace occurrences of sinl() and cosl() with + # sincosl(), but sincosl() is missing in newlib which causes error. So let's + # use custom implementation here. + + list(APPEND CSRCS ${CMAKE_CURRENT_LIST_DIR}/sincosl.c) + if(CONFIG_LIBM_NEWLIB_HW_FP) file(GLOB_RECURSE MATHFP_CSRCS ${NEWLIB_DIR}/newlib/libm/mathfp/*.c) list(APPEND CSRCS ${MATHFP_CSRCS}) @@ -111,6 +123,10 @@ if(CONFIG_LIBM_NEWLIB) set(INCDIR ${CMAKE_CURRENT_LIST_DIR}/include ${NEWLIB_DIR}/newlib/libm/common) + if(CONFIG_ARCH_X86_64) + list(APPEND INCDIR ${NEWLIB_DIR}/newlib/libc/machine/shared_x86/sys) + endif() + # ############################################################################ # Library Configuration # ############################################################################ @@ -121,4 +137,9 @@ if(CONFIG_LIBM_NEWLIB) target_include_directories(m PRIVATE ${INCDIR}) target_compile_options(m PRIVATE ${CFLAGS}) + set_property( + TARGET nuttx + APPEND + PROPERTY NUTTX_INCLUDE_DIRECTORIES ${CMAKE_CURRENT_LIST_DIR}/include) + endif() diff --git a/libs/libm/newlib/Make.defs b/libs/libm/newlib/Make.defs index ef7e25c94cac2..91540687235fd 100644 --- a/libs/libm/newlib/Make.defs +++ b/libs/libm/newlib/Make.defs @@ -39,6 +39,7 @@ newlib/newlib: $(NEWLIB_BASENAME)-$(NEWLIB_VERSION).tar.gz $(Q) mv $(NEWLIB_BASENAME)-$(NEWLIB_VERSION) newlib/newlib $(Q) patch -p0 < newlib/0001-newlib-libm-fix-__RCSID-build-error.patch $(Q) patch -p0 < newlib/0002-newlib-libm-remove-include-reent.h.patch + $(Q) patch -p0 < newlib/0003-newlib-fix-compilation-for-x86.patch $(Q) touch $@ endif @@ -81,6 +82,20 @@ endif CSRCS += $(wildcard newlib/newlib/newlib/libm/machine/$(ARCH)/*.c) VPATH += :newlib/newlib/newlib/libm/machine/$(ARCH) +ifeq ($(CONFIG_ARCH_X86_64),y) +CSRCS += $(wildcard newlib/newlib/newlib/libm/fenv/*.c) +VPATH += :newlib/newlib/newlib/libm/fenv + +CFLAGS += ${INCDIR_PREFIX}newlib/newlib/newlib/libc/machine/shared_x86/sys +endif + +# aggresive optimisation can replace occurrences of sinl() and cosl() with +# sincosl(), but sincosl() is missing in newlib which causes error. So let's +# use custom implementation here. + +CSRCS += newlib/sincosl.c +VPATH += :newlib + ifeq ($(CONFIG_LIBM_NEWLIB_HW_FP),y) CSRCS += $(wildcard newlib/newlib/newlib/libm/mathfp/*.c) VPATH += :newlib/newlib/newlib/libm/mathfp diff --git a/libs/libm/newlib/sincosl.c b/libs/libm/newlib/sincosl.c new file mode 100644 index 0000000000000..3ff6836265337 --- /dev/null +++ b/libs/libm/newlib/sincosl.c @@ -0,0 +1,35 @@ +/**************************************************************************** + * libs/libm/newlib/sincosl.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void sincosl(long double x, long double *s, long double *c) +{ + *s = sinl(x); + *c = cosl(x); +} diff --git a/libs/libm/openlibm/Make.defs b/libs/libm/openlibm/Make.defs index 0517312e9684a..1494863f03e10 100644 --- a/libs/libm/openlibm/Make.defs +++ b/libs/libm/openlibm/Make.defs @@ -1,4 +1,3 @@ - ############################################################################ # libs/libm/openlibm/Make.defs # diff --git a/libs/libxx/0001-libcxx-remove-mach-time-h.patch b/libs/libxx/0001-libcxx-remove-mach-time-h.patch new file mode 100644 index 0000000000000..7019bc6d563be --- /dev/null +++ b/libs/libxx/0001-libcxx-remove-mach-time-h.patch @@ -0,0 +1,13 @@ +--- libcxx/src/chrono.cpp ++++ libcxx/src/chrono.cpp +@@ -48,10 +48,6 @@ + # include + #endif + +-#if __has_include() +-# include +-#endif +- + #if defined(__ELF__) && defined(_LIBCPP_LINK_RT_LIB) + # pragma comment(lib, "rt") + #endif diff --git a/libs/libxx/Kconfig b/libs/libxx/Kconfig index 4e52b2f1473cf..d38134b93dd59 100644 --- a/libs/libxx/Kconfig +++ b/libs/libxx/Kconfig @@ -26,6 +26,13 @@ choice prompt "C++ Library" default LIBCXXMINI +config LIBCXXTOOLCHAIN + bool "Toolchain C++ support" + select HAVE_CXXINITIALIZE + select LIBC_LOCALE + ---help--- + Use Standard C++ library from toolchain. + config LIBCXXMINI bool "Basic C++ support" ---help--- diff --git a/libs/libxx/etl.defs b/libs/libxx/etl.defs index 85e209064e5d3..d8de05b13b157 100644 --- a/libs/libxx/etl.defs +++ b/libs/libxx/etl.defs @@ -1,5 +1,5 @@ ############################################################################ -# libs/libxx/stdex.defs +# libs/libxx/etl.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/libs/libxx/libcxx.cmake b/libs/libxx/libcxx.cmake index 0b4f01910235b..d8a281cc5f6b8 100644 --- a/libs/libxx/libcxx.cmake +++ b/libs/libxx/libcxx.cmake @@ -43,7 +43,9 @@ if(NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/libcxx) patch -p1 -d ${CMAKE_CURRENT_LIST_DIR}/libcxx < ${CMAKE_CURRENT_LIST_DIR}/0001_fix_stdatomic_h_miss_typedef.patch && patch -p3 -d ${CMAKE_CURRENT_LIST_DIR}/libcxx < - ${CMAKE_CURRENT_LIST_DIR}/mbstate_t.patch + ${CMAKE_CURRENT_LIST_DIR}/mbstate_t.patch && patch -p1 -d + ${CMAKE_CURRENT_LIST_DIR}/libcxx < + ${CMAKE_CURRENT_LIST_DIR}/0001-libcxx-remove-mach-time-h.patch DOWNLOAD_NO_PROGRESS true TIMEOUT 30) @@ -53,35 +55,27 @@ if(NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/libcxx) FetchContent_Populate(libcxx) endif() - execute_process( - COMMAND - sh -c - "ln -s ${CMAKE_CURRENT_LIST_DIR}/libcxx/include ${NUTTX_DIR}/include/libcxx" - WORKING_DIRECTORY ${CMAKE_CURRENT_LIST_DIR}) - execute_process( - COMMAND - sh -c - "cp ${CMAKE_CURRENT_LIST_DIR}/__config_site ${NUTTX_DIR}/include/libcxx/__config_site" - WORKING_DIRECTORY ${CMAKE_CURRENT_LIST_DIR}) endif() -set_property( - TARGET nuttx - APPEND - PROPERTY NUTTX_INCLUDE_DIRECTORIES ${CMAKE_CURRENT_LIST_DIR}/libcxx/include) +nuttx_create_symlink(${CMAKE_CURRENT_LIST_DIR}/libcxx/include + ${CMAKE_BINARY_DIR}/include/libcxx) + +configure_file(${CMAKE_CURRENT_LIST_DIR}/__config_site + ${CMAKE_BINARY_DIR}/include/libcxx/__config_site COPYONLY) set_property( TARGET nuttx APPEND - PROPERTY NUTTX_INCLUDE_DIRECTORIES ${CMAKE_CURRENT_LIST_DIR}/libcxx/src) + PROPERTY NUTTX_CXX_INCLUDE_DIRECTORIES ${CMAKE_BINARY_DIR}/include/libcxx) add_compile_definitions(_LIBCPP_BUILDING_LIBRARY) if(CONFIG_LIBSUPCXX) add_compile_definitions(__GLIBCXX__) endif() -set(CMAKE_CXX_STANDARD 17) +set(CMAKE_CXX_STANDARD 20) set(CMAKE_CXX_STANDARD_REQUIRED ON) +set(CMAKE_CXX_EXTENSIONS ON) set(SRCS) set(SRCSTMP) @@ -103,35 +97,47 @@ if(NOT DEFINED GCCVER) endif() if(GCCVER EQUAL 12) - set_source_files_properties(libcxx/src/filesystem/operations.cpp - PROPERTIES COMPILE_FLAGS -Wno-maybe-uninitialized) - set_source_files_properties(libcxx/src/locale.cpp - PROPERTIES COMPILE_FLAGS -Wno-maybe-uninitialized) - set_source_files_properties( - libcxx/src/string.cpp PROPERTIES COMPILE_FLAGS -Wno-alloc-size-larger-than) - set_source_files_properties(libcxx/src/charconv.cpp - PROPERTIES COMPILE_FLAGS -Wno-attributes) - set_source_files_properties(libcxx/src/locale.cpp PROPERTIES COMPILE_FLAGS - -Wno-attributes) + nuttx_append_source_file_properties(libcxx/src/filesystem/operations.cpp + COMPILE_FLAGS -Wno-maybe-uninitialized) + nuttx_append_source_file_properties(libcxx/src/locale.cpp COMPILE_FLAGS + -Wno-maybe-uninitialized) + nuttx_append_source_file_properties(libcxx/src/string.cpp COMPILE_FLAGS + -Wno-alloc-size-larger-than) + nuttx_append_source_file_properties(libcxx/src/charconv.cpp COMPILE_FLAGS + -Wno-attributes) + nuttx_append_source_file_properties(libcxx/src/locale.cpp COMPILE_FLAGS + -Wno-attributes) endif() if(GCCVER GREATER_EQUAL 12) - set_source_files_properties( - libcxx/src/string.cpp PROPERTIES COMPILE_FLAGS -Wno-deprecated-declarations) - set_source_files_properties(libcxx/src/filesystem/path.cpp - PROPERTIES COMPILE_FLAGS -Wno-shadow) - set_source_files_properties(libcxx/src/ryu/d2s.cpp - PROPERTIES COMPILE_FLAGS -Wno-maybe-uninitialized) + nuttx_append_source_file_properties(libcxx/src/string.cpp COMPILE_FLAGS + -Wno-deprecated-declarations) + nuttx_append_source_file_properties(libcxx/src/filesystem/path.cpp + COMPILE_FLAGS -Wno-shadow) + nuttx_append_source_file_properties(libcxx/src/ryu/d2s.cpp COMPILE_FLAGS + -Wno-maybe-uninitialized) endif() -set_source_files_properties(libcxx/src/barrier.cpp PROPERTIES COMPILE_FLAGS - -Wno-shadow) -set_source_files_properties(libcxx/src/locale.cpp PROPERTIES COMPILE_FLAGS - -Wno-shadow) -set_source_files_properties(libcxx/src/filesystem/operations.cpp - PROPERTIES COMPILE_FLAGS -Wno-shadow) -set_source_files_properties(libcxx/src/condition_variable.cpp - PROPERTIES COMPILE_FLAGS -Wno-sign-compare) +if(GCCVER GREATER_EQUAL 13) + nuttx_append_source_file_properties(libcxx/src/string.cpp COMPILE_FLAGS + -Wno-alloc-size-larger-than) +endif() + +nuttx_append_source_file_properties(libcxx/src/barrier.cpp COMPILE_FLAGS + -Wno-shadow) +nuttx_append_source_file_properties(libcxx/src/locale.cpp COMPILE_FLAGS + -Wno-shadow) +nuttx_append_source_file_properties(libcxx/src/filesystem/operations.cpp + COMPILE_FLAGS -Wno-shadow) +nuttx_append_source_file_properties(libcxx/src/condition_variable.cpp + COMPILE_FLAGS -Wno-sign-compare) nuttx_add_system_library(libcxx) target_sources(libcxx PRIVATE ${SRCS}) +if(CONFIG_LIBCXXABI) + target_include_directories( + libcxx BEFORE PRIVATE ${CMAKE_CURRENT_LIST_DIR}/libcxxabi/include) +endif() + +target_include_directories(libcxx BEFORE + PRIVATE ${CMAKE_CURRENT_LIST_DIR}/libcxx/src) diff --git a/libs/libxx/libcxx.defs b/libs/libxx/libcxx.defs index 32e07b0a5302f..4f8bfd3ca6bc1 100644 --- a/libs/libxx/libcxx.defs +++ b/libs/libxx/libcxx.defs @@ -30,6 +30,7 @@ libcxx: libcxx-$(LIBCXX_VERSION).src.tar.xz --exclude libcxx-$(LIBCXX_VERSION).src/test/std/pstl $(Q) mv libcxx-$(LIBCXX_VERSION).src libcxx $(Q) patch -p2 < mbstate_t.patch + $(Q) patch -p0 < 0001-libcxx-remove-mach-time-h.patch $(Q) touch $@ endif @@ -139,9 +140,11 @@ endif # warning on gcc >= 12.3.Rel1 # libcxx/src/string.cpp:58:33: warning: 'template struct std::__1::char_traits' is deprecated: char_traits for T not equal to char, wchar_t, char8_t, char16_t or char32_t is non-standard and is provided for a temporary period. It will be removed in LLVM 18, so please migrate off of it. [-Wdeprecated-declarations] # 58 | template string operator+, allocator>(char const*, string const&); +ifneq ($(GCCVER),) ifeq ($(shell expr $(GCCVER) \>= 12), 1) libcxx/src/string.cpp_CXXFLAGS += -Wno-deprecated-declarations endif +endif # warning on gcc >= 12.3.Rel1 # libcxx/src/filesystem/path.cpp:14: @@ -166,17 +169,21 @@ endif # libcxx/src/filesystem/path_parser.h:55:15: note: shadowed declaration is here # 55 | ParserState State; # | ^~~~~ +ifneq ($(GCCVER),) ifeq ($(shell expr $(GCCVER) \>= 12), 1) libcxx/src/filesystem/path.cpp_CXXFLAGS += -Wno-shadow endif +endif # warning on gcc >= 12.3.Rel1 # libcxx/src/ryu/d2s.cpp:490:31: warning: '_Trailing_zero_bits' may be used uninitialized [-Wmaybe-uninitialized] # 490 | _Trailing_zero_bits += 32; # | ~~~~~~~~~~~~~~~~~~~~^~~~~ +ifneq ($(GCCVER),) ifeq ($(shell expr $(GCCVER) \>= 12), 1) libcxx/src/ryu/d2s.cpp_CXXFLAGS += -Wno-maybe-uninitialized endif +endif CPPSRCS += $(wildcard libcxx/src/*.cpp) diff --git a/libs/libxx/libcxxabi.cmake b/libs/libxx/libcxxabi.cmake index 30393e011377b..976fca9d7c381 100644 --- a/libs/libxx/libcxxabi.cmake +++ b/libs/libxx/libcxxabi.cmake @@ -20,7 +20,7 @@ if(NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/libcxxabi) - set(LIBCXXABI_VERSION CONFIG_LIBCXXABI_VERSION) + set(LIBCXXABI_VERSION ${CONFIG_LIBCXXABI_VERSION}) FetchContent_Declare( libcxxabi @@ -39,9 +39,7 @@ if(NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/libcxxabi) "" TEST_COMMAND "" - PATCH_COMMAND - patch -p0 -d ${CMAKE_CURRENT_LIST_DIR} < - ${CMAKE_CURRENT_LIST_DIR}/0001-libc-abi-avoid-the-waring-__EXCEPTIONS-is-not-define.patch + PATCH_COMMAND "" DOWNLOAD_NO_PROGRESS true TIMEOUT 30) @@ -54,12 +52,6 @@ endif() nuttx_add_system_library(libcxxabi) -set_property( - TARGET nuttx - APPEND - PROPERTY NUTTX_INCLUDE_DIRECTORIES - ${CMAKE_CURRENT_LIST_DIR}/libcxxabi/include) - set(SRCS) # C++ABI files @@ -101,4 +93,11 @@ foreach(src ${SRCS}) list(APPEND TARGET_SRCS ${src}) endforeach() +# RTTI is required for building the libcxxabi library +target_compile_options(libcxxabi PRIVATE -frtti) + target_sources(libcxxabi PRIVATE ${TARGET_SRCS}) +target_compile_options(libcxxabi PRIVATE -frtti) +target_include_directories( + libcxxabi BEFORE PRIVATE ${CMAKE_CURRENT_LIST_DIR}/libcxxabi/include + ${CMAKE_CURRENT_LIST_DIR}/libcxx/src) diff --git a/libs/libxx/libcxxabi.defs b/libs/libxx/libcxxabi.defs index f64087a7f60ec..10c67d06558f5 100644 --- a/libs/libxx/libcxxabi.defs +++ b/libs/libxx/libcxxabi.defs @@ -20,6 +20,8 @@ LIBCXXABI_VERSION=$(patsubst "%",%,$(CONFIG_LIBCXXABI_VERSION)) +# Download and unpack tarball if no git repo found +ifeq ($(wildcard libcxxabi/.git),) libcxxabi-$(LIBCXXABI_VERSION).src.tar.xz: $(call DOWNLOAD,https://github.com/llvm/llvm-project/releases/download/llvmorg-$(LIBCXXABI_VERSION),libcxxabi-$(LIBCXXABI_VERSION).src.tar.xz) @@ -27,14 +29,19 @@ libcxxabi: libcxxabi-$(LIBCXXABI_VERSION).src.tar.xz $(Q) tar -xf libcxxabi-$(LIBCXXABI_VERSION).src.tar.xz $(Q) mv libcxxabi-$(LIBCXXABI_VERSION).src libcxxabi $(Q) touch $@ +endif + +$(TOPDIR)/include/libcxxabi: libcxxabi + $(Q) $(DIRLINK) $(CURDIR)/libcxxabi/include $(TOPDIR)/include/libcxxabi + $(Q) cp $(CURDIR)/__config_site $(TOPDIR)/include/libcxxabi/__config_site + +context:: $(TOPDIR)/include/libcxxabi -# Download and unpack tarball if no git repo found -ifeq ($(wildcard libcxxabi/.git),) distclean:: - $(Q) $(DELFILE) libcxxabi-$(LIBCXXABI_VERSION).src.tar.xz + $(Q) $(DIRUNLINK) $(TOPDIR)/include/libcxxabi +ifeq ($(wildcard libcxxabi/.git),) + $(Q) $(DELFILE) libcxxabi-$(LIBCXX_VERSION).src.tar.xz $(call DELDIR, libcxxabi) - -context:: libcxxabi endif ifeq ($(CONFIG_LIBCXXABI), y) diff --git a/libs/libxx/libcxxmini.cmake b/libs/libxx/libcxxmini.cmake index df053e9746dc8..3464dbc9697e2 100644 --- a/libs/libxx/libcxxmini.cmake +++ b/libs/libxx/libcxxmini.cmake @@ -47,4 +47,4 @@ set(CMAKE_CXX_STANDARD_REQUIRED ON) set_property( TARGET nuttx APPEND - PROPERTY NUTTX_INCLUDE_DIRECTORIES ${NUTTX_DIR}/include/cxx) + PROPERTY NUTTX_CXX_INCLUDE_DIRECTORIES ${NUTTX_DIR}/include/cxx) diff --git a/libs/libxx/uClibc++.cmake b/libs/libxx/uClibc++.cmake new file mode 100644 index 0000000000000..72c3f51dd5320 --- /dev/null +++ b/libs/libxx/uClibc++.cmake @@ -0,0 +1,112 @@ +# ############################################################################## +# libs/libxx/uClibc++.cmake +# +# Licensed to the Apache Software Foundation (ASF) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. The ASF licenses this +# file to you under the Apache License, Version 2.0 (the "License"); you may not +# use this file except in compliance with the License. You may obtain a copy of +# the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations under +# the License. +# +# ############################################################################## + +set(UCLIBCXX_DIR ${CMAKE_CURRENT_LIST_DIR}/uClibc++) + +if(NOT EXISTS ${UCLIBCXX_DIR}) + + set(UCLIBCXX_VERSION 0.2.5) + + FetchContent_Declare( + uClibc++ + DOWNLOAD_NAME "uClibc++-${UCLIBCXX_VERSION}.tar.bz2" + DOWNLOAD_DIR ${CMAKE_CURRENT_LIST_DIR} + URL "https://git.busybox.net/uClibc++/snapshot/uClibc++-${UCLIBCXX_VERSION}.tar.bz2" + SOURCE_DIR + ${CMAKE_CURRENT_LIST_DIR}/uClibc++ + BINARY_DIR + ${CMAKE_BINARY_DIR}/libs/libc/uClibc++ + CONFIGURE_COMMAND + "" + BUILD_COMMAND + "" + INSTALL_COMMAND + "" + TEST_COMMAND + "" + PATCH_COMMAND + patch -p1 -d ${CMAKE_CURRENT_LIST_DIR}/uClibc++ < + ${CMAKE_CURRENT_LIST_DIR}/0001-uClibcxx-basic_definitions-fix-GCC-specific-definiti.patch + && patch -p1 -d ${CMAKE_CURRENT_LIST_DIR}/uClibc++ < + ${CMAKE_CURRENT_LIST_DIR}/0001-uclibxx-use-overload-constructor-of-filebuf-ostream.patch + DOWNLOAD_NO_PROGRESS true + TIMEOUT 30) + + FetchContent_GetProperties(uClibc++) + + if(NOT uClibc++_POPULATED) + FetchContent_Populate(uClibc++) + endif() + +endif() + +nuttx_create_symlink(${CMAKE_CURRENT_LIST_DIR}/uClibc++/include + ${CMAKE_BINARY_DIR}/include/uClibc++) + +configure_file( + ${CMAKE_CURRENT_LIST_DIR}/system_configuration.h + ${CMAKE_BINARY_DIR}/include/uClibc++/system_configuration.h COPYONLY) + +set_property( + TARGET nuttx + APPEND + PROPERTY NUTTX_CXX_INCLUDE_DIRECTORIES ${CMAKE_BINARY_DIR}/include/uClibc++) + +set(SRCS + algorithm.cpp + associative_base.cpp + bitset.cpp + char_traits.cpp + complex.cpp + deque.cpp + exception.cpp + fstream.cpp + func_exception.cpp + iomanip.cpp + ios.cpp + iostream.cpp + istream.cpp + iterator.cpp + limits.cpp + list.cpp + locale.cpp + map.cpp + numeric.cpp + ostream.cpp + queue.cpp + set.cpp + sstream.cpp + stack.cpp + stdexcept.cpp + streambuf.cpp + string.cpp + utility.cpp + valarray.cpp + vector.cpp) + +set(TARGET_SRCS) + +foreach(src ${SRCS}) + string(PREPEND src uClibc++/src/) + list(APPEND TARGET_SRCS ${src}) +endforeach() + +nuttx_add_system_library(uClibc++) +target_sources(uClibc++ PRIVATE ${TARGET_SRCS}) diff --git a/libs/libxx/uClibc++.defs b/libs/libxx/uClibc++.defs index 71b5d438144b8..b8f5436b464a2 100644 --- a/libs/libxx/uClibc++.defs +++ b/libs/libxx/uClibc++.defs @@ -1,5 +1,5 @@ ############################################################################ -# libs/libxx/libcxx.defs +# libs/libxx/uClibc++.defs # # Licensed to the Apache Software Foundation (ASF) under one or more # contributor license agreements. See the NOTICE file distributed with diff --git a/mm/Kconfig b/mm/Kconfig index 0f5fa845205b8..ab67ee2dfdc22 100644 --- a/mm/Kconfig +++ b/mm/Kconfig @@ -60,7 +60,7 @@ config MM_KERNEL_HEAPSIZE user-mode heap. This value may need to be aligned to units of the size of the smallest memory protection region. -config MM_DFAULT_ALIGNMENT +config MM_DEFAULT_ALIGNMENT int "Memory default alignment in bytes" default 0 range 0 64 @@ -191,13 +191,15 @@ config MM_SHM depends on MM_PGALLOC && BUILD_KERNEL select ARCH_VMA_MAPPING ---help--- - Build in support for the shared memory interfaces shmget(), shmat(), - shmctl(), and shmdt(). + Build support for mapping physical memory to user-space via + shared memory interfaces like shmget(), shmat(), shmctl(), + etc, or device mapping interfaces like vm_map_region() etc. config MM_KMAP bool "Support for dynamic kernel virtual mappings" default n depends on MM_PGALLOC && BUILD_KERNEL + select ARCH_KVMA_MAPPING ---help--- Build support for dynamically mapping pages from the page pool into kernel virtual memory. This includes pages that are already mapped @@ -281,6 +283,21 @@ config MM_KASAN_DISABLE_WRITES_CHECK ---help--- This option disable kasan writes check. +config MM_KASAN_GLOBAL + bool "Enable global data check" + depends on MM_KASAN + default n + ---help--- + This option enables KASan global data check. + It's used to extract segments in the linker script. + Two new segments need to be created, one being + ".kasan.unused: { *(.data..LASANLOC*) }", + used to eliminate excess data generated. + One is ".kasan.global:{ + KEEP ( *(. data.. LASAN0)) + KEEP ( *(. data. rel. local.. LASAN0)) + }", used to extract data generated by the compiler + config MM_UBSAN bool "Undefined Behavior Sanitizer" default n @@ -322,8 +339,10 @@ config MM_FILL_ALLOCATIONS bool "Fill allocations with debug value" default n ---help--- - Fill all malloc() allocations with 0xAA. This helps - detecting uninitialized variable errors. + Fill all malloc() allocations with MM_ALLOC_MAGIC. + Fill all add_addregion() with MM_INIT_MAGIC. + Fill all free() with MM_FREE_MAGIC. + This helps detecting uninitialized variable errors. config MM_BACKTRACE int "The depth of backtrace" diff --git a/mm/iob/Kconfig b/mm/iob/Kconfig index e00deb759c96f..ce30937b5d59a 100644 --- a/mm/iob/Kconfig +++ b/mm/iob/Kconfig @@ -103,6 +103,12 @@ config IOB_NOTIFIER_DIV a notification will be sent only when there are a multiple of 4 IOBs available. +config IOB_ALLOC + bool "Dynamic I/O buffer allocation" + default n + ---help--- + This option will enable dynamic I/O buffer allocation + config IOB_DEBUG bool "Force I/O buffer debug" default n diff --git a/mm/iob/iob.h b/mm/iob/iob.h index 14947915de507..77ff58ec54b14 100644 --- a/mm/iob/iob.h +++ b/mm/iob/iob.h @@ -39,6 +39,8 @@ * Pre-processor Definitions ****************************************************************************/ +#define ROUNDUP(x, y) (((x) + (y) - 1) / (y) * (y)) + #if defined(CONFIG_DEBUG_FEATURES) && defined(CONFIG_IOB_DEBUG) # define ioberr _err # define iobwarn _warn diff --git a/mm/iob/iob_alloc.c b/mm/iob/iob_alloc.c index 5edb369e34fd1..c182b943a9dd6 100644 --- a/mm/iob/iob_alloc.c +++ b/mm/iob/iob_alloc.c @@ -30,6 +30,9 @@ #include #include #include +#ifdef CONFIG_IOB_ALLOC +# include +#endif #include #include "iob.h" @@ -197,6 +200,23 @@ static FAR struct iob_s *iob_allocwait(bool throttled, unsigned int timeout) return iob; } +#ifdef CONFIG_IOB_ALLOC +/**************************************************************************** + * Name: iob_free_dynamic + * + * Description: + * Dummy free callback function, do nothing. + * + * Input Parameters: + * data - + * + ****************************************************************************/ + +static void iob_free_dynamic(FAR void *data) +{ +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -329,3 +349,91 @@ FAR struct iob_s *iob_tryalloc(bool throttled) spin_unlock_irqrestore(&g_iob_lock, flags); return NULL; } + +#ifdef CONFIG_IOB_ALLOC + +/**************************************************************************** + * Name: iob_alloc_dynamic + * + * Description: + * Allocate an I/O buffer and playload from heap + * + * Input Parameters: + * size - The size of the io_data that is allocated. + * + * +---------+ + * | IOB | + * | io_data |--+ + * | buffer |<-+ + * +---------+ + * + ****************************************************************************/ + +FAR struct iob_s *iob_alloc_dynamic(uint16_t size) +{ + FAR struct iob_s *iob; + size_t alignsize; + + alignsize = ROUNDUP(sizeof(struct iob_s), CONFIG_IOB_ALIGNMENT) + size; + + iob = kmm_memalign(CONFIG_IOB_ALIGNMENT, alignsize); + if (iob) + { + iob->io_flink = NULL; /* Not in a chain */ + iob->io_len = 0; /* Length of the data in the entry */ + iob->io_offset = 0; /* Offset to the beginning of data */ + iob->io_bufsize = size; /* Total length of the iob buffer */ + iob->io_pktlen = 0; /* Total length of the packet */ + iob->io_free = iob_free_dynamic; /* Customer free callback */ + iob->io_data = (FAR uint8_t *)ROUNDUP((uintptr_t)(iob + 1), + CONFIG_IOB_ALIGNMENT); + } + + return iob; +} + +/**************************************************************************** + * Name: iob_alloc_with_data + * + * Description: + * Allocate an I/O buffer from heap and attach the external payload + * + * Input Parameters: + * data - Make io_data point to a specific address, the caller is + * responsible for the memory management. The caller should + * ensure that the memory is not freed before the iob is freed. + * + * +---------+ +-->+--------+ + * | IOB | | | data | + * | io_data |--+ +--------+ + * +---------+ + * + * size - The size of the data parameter + * free_cb - Notify the caller when the iob is freed. The caller can + * perform additional operations on the data before it is freed. + * The free_cb is called when the iob is freed. + * + ****************************************************************************/ + +FAR struct iob_s *iob_alloc_with_data(FAR void *data, uint16_t size, + iob_free_cb_t free_cb) +{ + FAR struct iob_s *iob; + + DEBUGASSERT(free_cb != NULL); + + iob = kmm_malloc(sizeof(struct iob_s)); + if (iob) + { + iob->io_flink = NULL; /* Not in a chain */ + iob->io_len = 0; /* Length of the data in the entry */ + iob->io_offset = 0; /* Offset to the beginning of data */ + iob->io_bufsize = size; /* Total length of the iob buffer */ + iob->io_pktlen = 0; /* Total length of the packet */ + iob->io_free = free_cb; /* Customer free callback */ + iob->io_data = data; + } + + return iob; +} +#endif diff --git a/mm/iob/iob_clone.c b/mm/iob/iob_clone.c index 109e3d6bd8018..82e319e543929 100644 --- a/mm/iob/iob_clone.c +++ b/mm/iob/iob_clone.c @@ -139,7 +139,7 @@ int iob_clone_partial(FAR struct iob_s *iob1, unsigned int len, while (iob2 != NULL) { - avail2 = CONFIG_IOB_BUFSIZE - iob2->io_offset; + avail2 = IOB_BUFSIZE(iob2) - iob2->io_offset; if ((int)(offset2 - avail2) < 0) { break; @@ -173,7 +173,7 @@ int iob_clone_partial(FAR struct iob_s *iob1, unsigned int len, */ dest = &iob2->io_data[iob2->io_offset + offset2]; - avail2 = CONFIG_IOB_BUFSIZE - iob2->io_offset - offset2; + avail2 = IOB_BUFSIZE(iob2) - iob2->io_offset - offset2; /* Copy the smaller of the two and update the srce and destination * offsets. @@ -218,7 +218,7 @@ int iob_clone_partial(FAR struct iob_s *iob1, unsigned int len, * transferred? */ - if ((int)(offset2 + iob2->io_offset - CONFIG_IOB_BUFSIZE) >= 0 && + if ((int)(offset2 + iob2->io_offset - IOB_BUFSIZE(iob2)) >= 0 && iob1 != NULL) { ret = iob_next(iob2, throttled, block); diff --git a/mm/iob/iob_contig.c b/mm/iob/iob_contig.c index 3d678189f429b..7a529ea0d8231 100644 --- a/mm/iob/iob_contig.c +++ b/mm/iob/iob_contig.c @@ -57,7 +57,7 @@ int iob_contig(FAR struct iob_s *iob, unsigned int len) * then you will need to increase CONFIG_IOB_BUFSIZE. */ - DEBUGASSERT(len <= CONFIG_IOB_BUFSIZE); + DEBUGASSERT(len <= IOB_BUFSIZE(iob)); /* Check if there is already sufficient, contiguous space at the beginning * of the packet diff --git a/mm/iob/iob_copyin.c b/mm/iob/iob_copyin.c index 0d221ee3b9352..fb69aa00c6506 100644 --- a/mm/iob/iob_copyin.c +++ b/mm/iob/iob_copyin.c @@ -128,7 +128,7 @@ static int iob_copyin_internal(FAR struct iob_s *iob, FAR const uint8_t *src, /* Yes.. We can extend this buffer to the up to the very end. */ - maxlen = CONFIG_IOB_BUFSIZE - iob->io_offset; + maxlen = IOB_BUFSIZE(iob) - iob->io_offset; /* This is the new buffer length that we need. Of course, * clipped to the maximum possible size in this buffer. diff --git a/mm/iob/iob_free.c b/mm/iob/iob_free.c index f2c04be9173fc..b8a26cce497a5 100644 --- a/mm/iob/iob_free.c +++ b/mm/iob/iob_free.c @@ -30,6 +30,9 @@ #include #include +#ifdef CONFIG_IOB_ALLOC +# include +#endif #include #include "iob.h" @@ -112,6 +115,15 @@ FAR struct iob_s *iob_free(FAR struct iob_s *iob) next, next->io_pktlen, next->io_len); } +#ifdef CONFIG_IOB_ALLOC + if (iob->io_free != NULL) + { + iob->io_free(iob->io_data); + kmm_free(iob); + return next; + } +#endif + /* Free the I/O buffer by adding it to the head of the free or the * committed list. We don't know what context we are called from so * we use extreme measures to protect the free list: We disable diff --git a/mm/iob/iob_initialize.c b/mm/iob/iob_initialize.c index d232f1e7bf404..8852d134756f1 100644 --- a/mm/iob/iob_initialize.c +++ b/mm/iob/iob_initialize.c @@ -34,11 +34,15 @@ * Pre-processor Definitions ****************************************************************************/ -#define ROUNDUP(x, y) (((x) + (y) - 1) / (y) * (y)) - /* Fix the I/O Buffer size with specified alignment size */ -#define IOB_ALIGN_SIZE ROUNDUP(sizeof(struct iob_s), CONFIG_IOB_ALIGNMENT) +#ifdef CONFIG_IOB_ALLOC +# define IOB_ALIGN_SIZE ROUNDUP(sizeof(struct iob_s) + CONFIG_IOB_BUFSIZE, \ + CONFIG_IOB_ALIGNMENT) +#else +# define IOB_ALIGN_SIZE ROUNDUP(sizeof(struct iob_s), CONFIG_IOB_ALIGNMENT) +#endif + #define IOB_BUFFER_SIZE (IOB_ALIGN_SIZE * CONFIG_IOB_NBUFFERS + \ CONFIG_IOB_ALIGNMENT - 1) @@ -138,8 +142,12 @@ void iob_initialize(void) /* Add the pre-allocate I/O buffer to the head of the free list */ - iob->io_flink = g_iob_freelist; - g_iob_freelist = iob; + iob->io_flink = g_iob_freelist; +#ifdef CONFIG_IOB_ALLOC + iob->io_bufsize = CONFIG_IOB_BUFSIZE; + iob->io_data = (FAR uint8_t *)(iob + 1); +#endif + g_iob_freelist = iob; } #if CONFIG_IOB_NCHAINS > 0 diff --git a/mm/iob/iob_pack.c b/mm/iob/iob_pack.c index 55b590311f35c..6fdce16cbe85a 100644 --- a/mm/iob/iob_pack.c +++ b/mm/iob/iob_pack.c @@ -86,7 +86,7 @@ FAR struct iob_s *iob_pack(FAR struct iob_s *iob) */ ncopy = next->io_len; - navail = CONFIG_IOB_BUFSIZE - iob->io_len; + navail = IOB_BUFSIZE(iob) - iob->io_len; if (ncopy > navail) { ncopy = navail; diff --git a/mm/iob/iob_reserve.c b/mm/iob/iob_reserve.c index e1964d5d14f61..d707f1fa398ff 100644 --- a/mm/iob/iob_reserve.c +++ b/mm/iob/iob_reserve.c @@ -49,9 +49,9 @@ void iob_reserve(FAR struct iob_s *iob, unsigned int reserved) while (iob != NULL && reserved > 0) { - if (reserved > CONFIG_IOB_BUFSIZE) + if (reserved > IOB_BUFSIZE(iob)) { - offset = CONFIG_IOB_BUFSIZE; + offset = IOB_BUFSIZE(iob); } else { diff --git a/mm/iob/iob_tailroom.c b/mm/iob/iob_tailroom.c index d0c999156c8ca..883f220693f21 100644 --- a/mm/iob/iob_tailroom.c +++ b/mm/iob/iob_tailroom.c @@ -48,5 +48,5 @@ unsigned int iob_tailroom(FAR struct iob_s *iob) iob = iob->io_flink; } - return CONFIG_IOB_BUFSIZE - (iob->io_offset + iob->io_len); + return IOB_BUFSIZE(iob) - (iob->io_offset + iob->io_len); } diff --git a/mm/iob/iob_update_pktlen.c b/mm/iob/iob_update_pktlen.c index e6e1fd46e32b9..0b9ebc8d40c30 100644 --- a/mm/iob/iob_update_pktlen.c +++ b/mm/iob/iob_update_pktlen.c @@ -49,9 +49,9 @@ int iob_update_pktlen(FAR struct iob_s *iob, unsigned int pktlen, { FAR struct iob_s *penultimate; FAR struct iob_s *next; - uint16_t offset = 0; + int remain = pktlen; int ninqueue = 0; - int nrequire; + int nrequire = 0; uint16_t len; /* The data offset must be less than CONFIG_IOB_BUFSIZE */ @@ -67,20 +67,28 @@ int iob_update_pktlen(FAR struct iob_s *iob, unsigned int pktlen, while (next != NULL) { ninqueue++; - offset += next->io_offset; penultimate = next; + if (remain > 0) + { + nrequire++; + remain -= IOB_BUFSIZE(next) - next->io_offset; + } + next = next->io_flink; } - /* Trim inqueue entries if needed */ + if (remain > 0) + { + nrequire += (remain + CONFIG_IOB_BUFSIZE - 1) / CONFIG_IOB_BUFSIZE; + } - nrequire = (pktlen + offset + CONFIG_IOB_BUFSIZE - 1) / - CONFIG_IOB_BUFSIZE; if (nrequire == 0) { nrequire = 1; } + /* Trim inqueue entries if needed */ + if (nrequire < ninqueue) { /* Loop until complete the trim */ @@ -130,9 +138,9 @@ int iob_update_pktlen(FAR struct iob_s *iob, unsigned int pktlen, next = iob; while (next != NULL && pktlen > 0) { - if (pktlen + next->io_offset > CONFIG_IOB_BUFSIZE) + if (pktlen + next->io_offset > IOB_BUFSIZE(next)) { - len = CONFIG_IOB_BUFSIZE - next->io_offset; + len = IOB_BUFSIZE(next) - next->io_offset; } else { diff --git a/mm/kasan/Make.defs b/mm/kasan/Make.defs index e8e464da5a68d..a629b48e3bbe5 100644 --- a/mm/kasan/Make.defs +++ b/mm/kasan/Make.defs @@ -24,8 +24,12 @@ CSRCS += kasan.c # Disable kernel-address in mm subsystem -CFLAGS += -fno-sanitize=kernel-address -CFLAGS += -fno-lto +ifeq ($(CONFIG_ARCH_TOOLCHAIN_GNU),y) + CFLAGS += -fno-sanitize=kernel-address + ifeq ($(CONFIG_LTO_NONE),n) + CFLAGS += -fno-lto + endif +endif # Add the core heap directory to the build diff --git a/mm/kasan/kasan.c b/mm/kasan/kasan.c index fb91d6fc87d5e..b8a4843abd724 100644 --- a/mm/kasan/kasan.c +++ b/mm/kasan/kasan.c @@ -50,6 +50,16 @@ #define KASAN_REGION_SIZE(size) \ (sizeof(struct kasan_region_s) + KASAN_SHADOW_SIZE(size)) +#ifdef CONFIG_MM_KASAN_GLOBAL + +# define KASAN_GLOBAL_SHADOW_SCALE (32) + +# define KASAN_GLOBAL_NEXT_REGION(region) \ + (FAR struct kasan_region_s *) \ + ((FAR char *)region->shadow + (size_t)region->next) + +#endif + #define KASAN_INIT_VALUE 0xDEADCAFE /**************************************************************************** @@ -59,9 +69,9 @@ struct kasan_region_s { FAR struct kasan_region_s *next; - uintptr_t begin; - uintptr_t end; - uintptr_t shadow[1]; + uintptr_t begin; + uintptr_t end; + uintptr_t shadow[1]; }; /**************************************************************************** @@ -72,6 +82,14 @@ static spinlock_t g_lock; static FAR struct kasan_region_s *g_region; static uint32_t g_region_init; +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef CONFIG_MM_KASAN_GLOBAL +extern const unsigned char g_globals_region[]; +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -99,6 +117,22 @@ static FAR uintptr_t *kasan_mem_to_shadow(FAR const void *ptr, size_t size, } } +#ifdef CONFIG_MM_KASAN_GLOBAL + for (region = (FAR struct kasan_region_s *)g_globals_region; + region->next; + region = KASAN_GLOBAL_NEXT_REGION(region)) + { + if (addr >= region->begin && addr < region->end) + { + DEBUGASSERT(addr + size <= region->end); + addr -= region->begin; + addr /= KASAN_GLOBAL_SHADOW_SCALE; + *bit = addr % KASAN_BITS_PER_WORD; + return ®ion->shadow[addr / KASAN_BITS_PER_WORD]; + } + } +#endif + return NULL; } @@ -314,3 +348,15 @@ DEFINE_ASAN_LOAD_STORE(2) DEFINE_ASAN_LOAD_STORE(4) DEFINE_ASAN_LOAD_STORE(8) DEFINE_ASAN_LOAD_STORE(16) + +#ifdef CONFIG_MM_KASAN_GLOBAL +void __asan_register_globals(void *ptr, ssize_t size) +{ + /* Shut up compiler complaints */ +} + +void __asan_unregister_globals(void *ptr, ssize_t size) +{ + /* Shut up compiler complaints */ +} +#endif diff --git a/mm/map/mm_map.c b/mm/map/mm_map.c index 5d89bced60100..0756c00d220ef 100644 --- a/mm/map/mm_map.c +++ b/mm/map/mm_map.c @@ -64,7 +64,15 @@ static bool in_range(FAR const void *start, size_t length, int mm_map_lock(void) { - return nxrmutex_lock(&get_current_mm()->mm_map_mutex); + FAR struct tcb_s *tcb = nxsched_self(); + FAR struct task_group_s *group = tcb->group; + + if (group == NULL) + { + return -EINVAL; + } + + return nxrmutex_lock(&group->tg_mm_map.mm_map_mutex); } /**************************************************************************** @@ -77,7 +85,15 @@ int mm_map_lock(void) void mm_map_unlock(void) { - DEBUGVERIFY(nxrmutex_unlock(&get_current_mm()->mm_map_mutex)); + FAR struct tcb_s *tcb = nxsched_self(); + FAR struct task_group_s *group = tcb->group; + + if (group == NULL) + { + return; + } + + DEBUGVERIFY(nxrmutex_unlock(&group->tg_mm_map.mm_map_mutex)); } /**************************************************************************** @@ -101,8 +117,7 @@ void mm_map_initialize(FAR struct mm_map_s *mm, bool kernel) if (!kernel) { mm->mm_map_vpages = gran_initialize((FAR void *)CONFIG_ARCH_SHM_VBASE, - ARCH_SHM_MAXPAGES << MM_PGSHIFT, - MM_PGSHIFT, MM_PGSHIFT); + ARCH_SHM_SIZE, MM_PGSHIFT, MM_PGSHIFT); if (!mm->mm_map_vpages) { merr("gran_initialize() failed\n"); diff --git a/mm/map/vm_region.c b/mm/map/vm_region.c index 765f62bcbc4b9..0c94c74de4bfd 100644 --- a/mm/map/vm_region.c +++ b/mm/map/vm_region.c @@ -22,8 +22,10 @@ * Included Files ****************************************************************************/ +#include #include #include +#include #include /**************************************************************************** @@ -62,8 +64,7 @@ FAR void *vm_alloc_region(FAR struct mm_map_s *mm, FAR void *vaddr, } else { - ret = gran_reserve(mm->mm_map_vpages, (uintptr_t)vaddr, - size); + ret = gran_reserve(mm->mm_map_vpages, (uintptr_t)vaddr, size); } } @@ -92,3 +93,60 @@ void vm_release_region(FAR struct mm_map_s *mm, FAR void *vaddr, size_t size) gran_free(mm->mm_map_vpages, vaddr, size); } } + +/* map physical region to userspace */ + +FAR void *vm_map_region(uintptr_t paddr, size_t size) +{ + FAR void *vaddr; + uintptr_t tvaddr; + size_t npages; + uintptr_t tpaddr = MM_PGALIGNDOWN(paddr); + uint i = 0; + int ret = OK; + + DEBUGASSERT(paddr); + + size += (paddr & MM_PGMASK); + npages = MM_NPAGES(size); + DEBUGASSERT(npages); + + vaddr = vm_alloc_region(get_current_mm(), 0, size); + if (vaddr) + { + tvaddr = (uintptr_t)vaddr; + for (; i < npages; i++, tvaddr += MM_PGSIZE, tpaddr += MM_PGSIZE) + { + ret = up_shmat(&tpaddr, 1, tvaddr); + if (ret) + { + goto error; + } + } + } + + return vaddr + (MM_PGMASK & paddr); + +error: + if (i) /* undo alway mapped pages */ + { + up_shmdt((uintptr_t)vaddr, i); + } + + vm_release_region(get_current_mm(), vaddr, size); + return 0; +} + +/* unmap userspace device pointer */ + +int vm_unmap_region(FAR void *vaddr, size_t size) +{ + int ret; + + DEBUGASSERT(size && vaddr); + size += ((uintptr_t)vaddr & MM_PGMASK); + vaddr = (void *)MM_PGALIGNDOWN(vaddr); + ret = up_shmdt((uintptr_t)vaddr, MM_NPAGES(size)); + vm_release_region(get_current_mm(), vaddr, size); + return ret; +} diff --git a/mm/mempool/mempool.c b/mm/mempool/mempool.c index 206c835583d46..46f278e373dce 100644 --- a/mm/mempool/mempool.c +++ b/mm/mempool/mempool.c @@ -274,7 +274,7 @@ FAR void *mempool_alloc(FAR struct mempool_s *pool) } #ifdef CONFIG_MM_FILL_ALLOCATIONS - memset(blk, 0xaa, pool->blocksize); + memset(blk, MM_ALLOC_MAGIC, pool->blocksize); #endif #if CONFIG_MM_BACKTRACE >= 0 @@ -317,7 +317,7 @@ void mempool_free(FAR struct mempool_s *pool, FAR void *blk) #endif #ifdef CONFIG_MM_FILL_ALLOCATIONS - memset(blk, 0x55, pool->blocksize); + memset(blk, MM_FREE_MAGIC, pool->blocksize); #endif if (pool->interruptsize > blocksize) diff --git a/mm/mm_gran/CMakeLists.txt b/mm/mm_gran/CMakeLists.txt index 50e8dbbd8c21a..4de3860fdab0f 100644 --- a/mm/mm_gran/CMakeLists.txt +++ b/mm/mm_gran/CMakeLists.txt @@ -22,15 +22,9 @@ if(CONFIG_GRAN) - set(SRCS - mm_graninit.c - mm_granrelease.c - mm_granreserve.c - mm_granalloc.c - mm_granmark.c - mm_granfree.c - mm_graninfo.c - mm_grancritical.c) + set(SRCS mm_graninit.c mm_granrelease.c mm_graninfo.c mm_grancritical.c) + list(APPEND SRCS mm_grantable.c mm_granfree.c mm_granalloc.c) + list(APPEND SRCS mm_granreserve.c) # A page allocator based on the granule allocator diff --git a/mm/mm_gran/Make.defs b/mm/mm_gran/Make.defs index ef7f12ba6783a..7ec0c63153a2b 100644 --- a/mm/mm_gran/Make.defs +++ b/mm/mm_gran/Make.defs @@ -21,8 +21,9 @@ # An optional granule allocator ifeq ($(CONFIG_GRAN),y) -CSRCS += mm_graninit.c mm_granrelease.c mm_granreserve.c mm_granalloc.c -CSRCS += mm_granmark.c mm_granfree.c mm_graninfo.c mm_grancritical.c + +CSRCS += mm_graninit.c mm_granrelease.c mm_graninfo.c mm_grancritical.c +CSRCS += mm_grantable.c mm_granfree.c mm_granalloc.c mm_granreserve.c # A page allocator based on the granule allocator diff --git a/mm/mm_gran/mm_gran.h b/mm/mm_gran/mm_gran.h index 5840d9682f107..9c64e987b19a0 100644 --- a/mm/mm_gran/mm_gran.h +++ b/mm/mm_gran/mm_gran.h @@ -47,7 +47,7 @@ /* Debug */ -#ifdef CONFIG_DEBUG_GRAM +#ifdef CONFIG_DEBUG_GRAN # define granerr _err # define granwarn _warn # define graninfo _info diff --git a/mm/mm_gran/mm_granalloc.c b/mm/mm_gran/mm_granalloc.c index 88264311a212e..7727e2120a4cf 100644 --- a/mm/mm_gran/mm_granalloc.c +++ b/mm/mm_gran/mm_granalloc.c @@ -25,10 +25,12 @@ #include #include +#include #include #include "mm_gran/mm_gran.h" +#include "mm_gran/mm_grantable.h" #ifdef CONFIG_GRAN @@ -36,215 +38,45 @@ * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: gran_alloc - * - * Description: - * Allocate memory from the granule heap. - * - * NOTE: The current implementation also restricts the maximum allocation - * size to 32 granules. That restriction could be eliminated with some - * additional coding effort. - * - * Input Parameters: - * handle - The handle previously returned by gran_initialize - * size - The size of the memory region to allocate. - * - * Returned Value: - * On success, a non-NULL pointer to the allocated memory is returned; - * NULL is returned on failure. - * - ****************************************************************************/ - FAR void *gran_alloc(GRAN_HANDLE handle, size_t size) { - FAR struct gran_s *priv = (FAR struct gran_s *)handle; - unsigned int ngranules; - size_t tmpmask; - uintptr_t alloc; - uint32_t curr; - uint32_t next; - uint32_t mask; - int granidx; - int gatidx; - int bitidx; - int shift; - int ret; - - DEBUGASSERT(priv != NULL && size <= 32 * (1 << priv->log2gran)); - - if (priv != NULL && size > 0) + FAR gran_t *gran = (FAR gran_t *)handle; + size_t ngran; + int posi; + int ret; + uintptr_t retp; + + DEBUGASSERT(gran); + ngran = NGRANULE(gran, size); + if (!ngran || ngran > gran->ngranules) { - /* Get exclusive access to the GAT */ - - ret = gran_enter_critical(priv); - if (ret < 0) - { - return NULL; - } - - /* How many contiguous granules we we need to find? */ - - tmpmask = (1 << priv->log2gran) - 1; - ngranules = (size + tmpmask) >> priv->log2gran; - - /* Then create mask for that number of granules */ - - DEBUGASSERT(ngranules <= 32); - mask = 0xffffffff >> (32 - ngranules); - - /* Now search the granule allocation table for that number - * of contiguous - */ - - for (granidx = 0; granidx < priv->ngranules; granidx += 32) - { - /* Get the GAT index associated with the granule table entry */ - - gatidx = granidx >> 5; - curr = priv->gat[gatidx]; - - /* Handle the case where there are no free granules in the entry */ - - if (curr == 0xffffffff) - { - continue; - } - - /* Get the next entry from the GAT to support a 64 bit shift */ - - if (granidx + 32 < priv->ngranules) - { - next = priv->gat[gatidx + 1]; - } - - /* Use all ones when are at the last entry in the GAT (meaning - * nothing can be allocated. - */ - - else - { - next = 0xffffffff; - } - - /* Search through the allocations in the 'curr' GAT entry - * to see if we can satisfy the allocation starting in that - * entry. - * - * This loop continues until either all of the bits have been - * examined (bitidx >= 32), or until there are insufficient - * granules left to satisfy the allocation. - */ - - alloc = priv->heapstart + (granidx << priv->log2gran); - - for (bitidx = 0; - bitidx < 32 && - (granidx + bitidx + ngranules) <= priv->ngranules; - ) - { - /* Break out if there are no further free bits in 'curr'. - * All of the zero bits might have gotten shifted out. - */ - - if (curr == 0xffffffff) - { - break; - } - - /* Check for the first zero bit in the lower or upper 16-bits. - * From the test above, we know that at least one of the 32- - * bits in 'curr' is zero. - */ - - else if ((curr & 0x0000ffff) == 0x0000ffff) - { - /* Not in the lower 16 bits. The first free bit must be - * in the upper 16 bits. - */ - - shift = 16; - } - - /* We know that the first free bit is now within the lower 16 - * bits of 'curr'. Is it in the upper or lower byte? - */ - - else if ((curr & 0x0000ff) == 0x000000ff) - { - /* Not in the lower 8 bits. The first free bit must be in - * the upper 8 bits. - */ - - shift = 8; - } - - /* We know that the first free bit is now within the lower 4 - * bits of 'curr'. Is it in the upper or lower nibble? - */ - - else if ((curr & 0x00000f) == 0x0000000f) - { - /* Not in the lower 4 bits. The first free bit must be in - * the upper 4 bits. - */ - - shift = 4; - } - - /* We know that the first free bit is now within the lower 4 - * bits of 'curr'. Is it in the upper or lower pair? - */ - - else if ((curr & 0x000003) == 0x00000003) - { - /* Not in the lower 2 bits. The first free bit must be in - * the upper 2 bits. - */ - - shift = 2; - } - - /* We know that the first free bit is now within the lower 4 - * bits of 'curr'. Check if we have the allocation at this - * bit position. - */ - - else if ((curr & mask) == 0) - { - /* Yes.. mark these granules allocated */ - - gran_mark_allocated(priv, alloc, ngranules); - - /* And return the allocation address */ - - gran_leave_critical(priv); - return (FAR void *)alloc; - } - - /* The free allocation does not start at this position */ - - else - { - shift = 1; - } + return NULL; + } - /* Set up for the next time through the loop. Perform a 64 - * bit shift to move to the next gran position and increment - * to the next candidate allocation address. - */ + ret = gran_enter_critical(gran); + if (ret < 0) + { + return NULL; + } - alloc += (shift << priv->log2gran); - curr = (curr >> shift) | (next << (32 - shift)); - next >>= shift; - bitidx += shift; - } - } + posi = gran_search(gran, ngran); + if (posi >= 0) + { + gran_set(gran, posi, ngran); + } - gran_leave_critical(priv); + gran_leave_critical(gran); + if (posi < 0) + { + return NULL; } - return NULL; + retp = gran->heapstart + (posi << gran->log2gran); + graninfo("heap=%"PRIxPTR" posi=%d retp=%"PRIxPTR" size=%zu n=%zu\n", + gran->heapstart, posi, retp, size, ngran); + DEBUGASSERT(retp >= gran->heapstart); + DEBUGASSERT(retp < gran->heapstart + GRANBYTE(gran)); + return (FAR void *)retp; } #endif /* CONFIG_GRAN */ diff --git a/mm/mm_gran/mm_granfree.c b/mm/mm_gran/mm_granfree.c index 5f2d4b2f4eb1c..e2a667b5d1226 100644 --- a/mm/mm_gran/mm_granfree.c +++ b/mm/mm_gran/mm_granfree.c @@ -25,11 +25,12 @@ #include #include -#include +#include #include #include "mm_gran/mm_gran.h" +#include "mm_gran/mm_grantable.h" #ifdef CONFIG_GRAN @@ -37,100 +38,35 @@ * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: gran_free - * - * Description: - * Return memory to the granule heap. - * - * Input Parameters: - * handle - The handle previously returned by gran_initialize - * memory - A pointer to memory previoiusly allocated by gran_alloc. - * - * Returned Value: - * None - * - ****************************************************************************/ - void gran_free(GRAN_HANDLE handle, FAR void *memory, size_t size) { - FAR struct gran_s *priv = (FAR struct gran_s *)handle; - unsigned int granno; - unsigned int gatidx; - unsigned int gatbit; - unsigned int granmask; - unsigned int ngranules; - unsigned int avail; - uint32_t gatmask; - int ret; + FAR gran_t *gran = (FAR gran_t *)handle; + uint ngran; + size_t posi; + int ret; + + DEBUGASSERT(gran && memory && size); + DEBUGASSERT(GRAN_PRODUCT(gran, memory)); + DEBUGASSERT(GRAN_INRANGE(gran, (((uintptr_t)memory) + size - 1))); - DEBUGASSERT(priv != NULL && memory && size <= 32 * (1 << priv->log2gran)); + posi = MEM2GRAN(gran, memory); + ngran = NGRANULE(gran, size); - /* Get exclusive access to the GAT */ + graninfo(" heap=%"PRIxPTR" posi=%zu addr=%zx size=%zu n=%d\n", + gran->heapstart, posi, (size_t)memory, size, ngran); do { - ret = gran_enter_critical(priv); - - /* The only error Should happen on task cancellation. We must - * try again in this case to avoid stranding the granule memory. - */ - + ret = gran_enter_critical(gran); DEBUGASSERT(ret == OK || ret == -ECANCELED); } - while (ret < 0); - - /* Determine the granule number of the first granule in the allocation */ - - granno = ((uintptr_t)memory - priv->heapstart) >> priv->log2gran; - - /* Determine the GAT table index and bit number associated with the - * allocation. - */ - - gatidx = granno >> 5; - gatbit = granno & 31; - - /* Determine the number of granules in the allocation */ - - granmask = (1 << priv->log2gran) - 1; - ngranules = (size + granmask) >> priv->log2gran; - - /* Clear bits in the GAT entry or entries */ - - avail = 32 - gatbit; - if (ngranules > avail) - { - /* Clear bits in the first GAT entry */ - - gatmask = (0xffffffff << gatbit); - DEBUGASSERT((priv->gat[gatidx] & gatmask) == gatmask); - - priv->gat[gatidx] &= ~gatmask; - ngranules -= avail; - - /* Clear bits in the second GAT entry */ - - gatmask = 0xffffffff >> (32 - ngranules); - DEBUGASSERT((priv->gat[gatidx + 1] & gatmask) == gatmask); - - priv->gat[gatidx + 1] &= ~gatmask; - } + while (ret < 0); /* Retry upon task cancellation */ - /* Handle the case where where all of the granules came from one entry */ - - else - { - /* Clear bits in a single GAT entry */ - - gatmask = 0xffffffff >> (32 - ngranules); - gatmask <<= gatbit; - DEBUGASSERT((priv->gat[gatidx] & gatmask) == gatmask); - - priv->gat[gatidx] &= ~gatmask; - } + /* check double free */ - gran_leave_critical(priv); + DEBUGASSERT(gran_match(gran, posi, ngran, 1, NULL)); + gran_clear(gran, posi, ngran); + gran_leave_critical(gran); } #endif /* CONFIG_GRAN */ diff --git a/mm/mm_gran/mm_granmark.c b/mm/mm_gran/mm_granmark.c deleted file mode 100644 index 634778b414f02..0000000000000 --- a/mm/mm_gran/mm_granmark.c +++ /dev/null @@ -1,121 +0,0 @@ -/**************************************************************************** - * mm/mm_gran/mm_granmark.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include - -#include "mm_gran/mm_gran.h" - -#ifdef CONFIG_GRAN - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: gran_mark_allocated - * - * Description: - * Mark a range of granules as allocated. - * - * Input Parameters: - * priv - The granule heap state structure. - * alloc - The address of the allocation. - * ngranules - The number of granules allocated - * - * Returned Value: - * On success, a non-NULL pointer to the allocated memory is returned; - * NULL is returned on failure. - * - ****************************************************************************/ - -FAR void *gran_mark_allocated(FAR struct gran_s *priv, uintptr_t alloc, - unsigned int ngranules) -{ - unsigned int granno; - unsigned int gatidx; - unsigned int gatbit; - unsigned int avail; - uint32_t gatmask; - - /* Determine the granule number of the allocation */ - - granno = (alloc - priv->heapstart) >> priv->log2gran; - - /* Determine the GAT table index associated with the allocation */ - - gatidx = granno >> 5; - gatbit = granno & 31; - - /* Mark bits in the GAT entry or entries */ - - avail = 32 - gatbit; - if (ngranules > avail) - { - uint32_t gatmask2; - - gatmask = 0xffffffff << gatbit; - ngranules -= avail; - gatmask2 = 0xffffffff >> (32 - ngranules); - - /* Check that the area is free, from both mask words */ - - if (((priv->gat[gatidx] & gatmask) != 0) || - ((priv->gat[gatidx + 1] & gatmask2) != 0)) - { - return NULL; - } - - /* Mark bits in the first and second GAT entry */ - - priv->gat[gatidx] |= gatmask; - priv->gat[gatidx + 1] |= gatmask2; - } - - /* Handle the case where where all of the granules come from one entry */ - - else - { - gatmask = 0xffffffff >> (32 - ngranules); - gatmask <<= gatbit; - - /* Check that the area is free */ - - if ((priv->gat[gatidx] & gatmask) != 0) - { - return NULL; - } - - /* Mark bits in a single GAT entry */ - - priv->gat[gatidx] |= gatmask; - } - - return (FAR void *)alloc; -} - -#endif /* CONFIG_GRAN */ diff --git a/mm/mm_gran/mm_granreserve.c b/mm/mm_gran/mm_granreserve.c index 4930b02d086d1..eb6aabfb79f82 100644 --- a/mm/mm_gran/mm_granreserve.c +++ b/mm/mm_gran/mm_granreserve.c @@ -25,10 +25,12 @@ #include #include +#include #include #include "mm_gran/mm_gran.h" +#include "mm_gran/mm_grantable.h" #ifdef CONFIG_GRAN @@ -36,67 +38,58 @@ * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: gran_reserve - * - * Description: - * Reserve memory in the granule heap. This will reserve the granules - * that contain the start and end addresses plus all of the granules - * in between. This should be done early in the initialization sequence - * before any other allocations are made. - * - * Reserved memory can never be allocated (it can be freed however which - * essentially unreserves the memory). - * - * Input Parameters: - * handle - The handle previously returned by gran_initialize - * start - The address of the beginning of the region to be reserved. - * size - The size of the region to be reserved - * - * Returned Value: - * On success, a non-NULL pointer to the allocated memory is returned; - * NULL is returned on failure. - * - ****************************************************************************/ - FAR void *gran_reserve(GRAN_HANDLE handle, uintptr_t start, size_t size) { - FAR struct gran_s *priv = (FAR struct gran_s *)handle; - FAR void *ret = NULL; + FAR gran_t *gran = (FAR gran_t *)handle; + uintptr_t end; + size_t ngran; + size_t posi; + bool avail; + + DEBUGASSERT(gran); + if (!size || size > GRANBYTE(gran)) + { + return NULL; + } - DEBUGASSERT(priv != NULL); + /* align down/up start/ending addresses */ - if (size > 0) + end = END_RSRV(gran, start, size); + if (!GRAN_INRANGE(gran, end)) { - uintptr_t mask = (1 << priv->log2gran) - 1; - uintptr_t end = start + size - 1; - unsigned int ngranules; + return NULL; + } - /* Get the aligned (down) start address and the aligned (up) end - * address - */ + start = MEM_RSRV(gran, start); + if (!GRAN_INRANGE(gran, start)) + { + return NULL; + } - start &= ~mask; - end = (end + mask) & ~mask; + /* convert unit to granule */ - /* Calculate the new size in granules */ + posi = MEM2GRAN(gran, start); + ngran = ((end - start) >> gran->log2gran) + 1; - ngranules = ((end - start) >> priv->log2gran) + 1; + /* lock the granule allocator */ - /* Must lock the granule allocator */ + if (gran_enter_critical(gran) < 0) + { + return NULL; + } - if (gran_enter_critical(priv) < 0) - { - return NULL; - } + avail = gran_match(gran, posi, ngran, 0, NULL); + if (avail) + { + gran_set(gran, posi, ngran); + } - /* And reserve the granules */ + gran_leave_critical(gran); - ret = gran_mark_allocated(priv, start, ngranules); - gran_leave_critical(priv); - } + graninfo("%s posi=%zu retp=%zx size=%zu n=%zu\n", + avail ? " done" : " error", posi, (size_t)start, size, ngran); - return ret; + return avail ? (FAR void *)start : NULL; } #endif /* CONFIG_GRAN */ diff --git a/mm/mm_gran/mm_grantable.c b/mm/mm_gran/mm_grantable.c new file mode 100644 index 0000000000000..93c027db4c96f --- /dev/null +++ b/mm/mm_gran/mm_grantable.c @@ -0,0 +1,291 @@ +/**************************************************************************** + * mm/mm_gran/mm_grantable.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "mm_gran/mm_gran.h" +#include "mm_gran/mm_grantable.h" + +#ifdef CONFIG_GRAN + +/**************************************************************************** + * Preprocessors + ****************************************************************************/ + +#define GATCFULL 0xffffffffu /* a full GAT cell */ +#define DEBRUJIN_NUM 0x077CB531UL /* the de Bruijn Sequence */ + +/**************************************************************************** + * Private data + ****************************************************************************/ + +#if !defined(CONFIG_HAVE_BUILTIN_CLZ) || !defined(CONFIG_HAVE_BUILTIN_CTZ) + +/* The de Bruijn lookup table to get n from BIT(n). */ + +static const uint8_t DEBRUJIN_LUT[32] = +{ + 0, 1, 28, 2, 29, 14, 24, 3, 30, 22, 20, 15, 25, 17, 4, 8, + 31, 27, 13, 23, 21, 19, 16, 7, 26, 12, 18, 6, 11, 5, 10, 9 +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* return BIT(MSB(n)) */ + +uint32_t msb_mask(uint32_t n) +{ + /* see https://www.geeksforgeeks.org/find-significant-set-bit-number */ + + DEBUGASSERT(n); + n |= n >> 1; + n |= n >> 2; + n |= n >> 4; + n |= n >> 8; + n |= n >> 16; + + n = ((n + 1) >> 1) | (n & (1 << ((sizeof(n) << 3)-1))); + return n; +} + +/* return BIT(LSB(n)) */ + +uint32_t lsb_mask(uint32_t n) +{ + DEBUGASSERT(n); + return (-n & n) & GATCFULL; +} + +/* set or clear a GAT cell with given bit mask */ + +static void cell_set(gran_t *gran, uint32_t cell, uint32_t mask, bool val) +{ + if (val) + { + gran->gat[cell] |= mask; + } + else + { + gran->gat[cell] &= ~mask; + } +} + +/* set or clear a range of GAT bits */ + +static void gran_set_(gran_t *gran, gatr_t *rang, bool val) +{ + uint32_t c; + + cell_set(gran, rang->sidx, rang->smask, val); + if (rang->sidx != rang->eidx) + { + cell_set(gran, rang->eidx, rang->emask, val); + c = rang->sidx + 1; + for (; c < rang->eidx; c++) + { + cell_set(gran, c, GATCFULL, val); + } + } + + return; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/* prepare given GAT range instance for later use. */ + +int gran_range(const gran_t *gran, size_t posi, size_t size, + gatr_t *rang) +{ + if (!gran || gran->ngranules < posi + size) + { + return -EINVAL; + } + + if (rang == NULL) + { + return -ENOMEM; + } + + rang->width = GATC_BITS(gran); + + rang->sidx = posi / rang->width; + rang->soff = posi % rang->width; + + posi += size - 1; + rang->eidx = posi / GATC_BITS(gran); + rang->eoff = posi % GATC_BITS(gran); + + rang->smask = ~(BIT(rang->soff) - 1); + rang->emask = (BIT(rang->eoff) - 1) | BIT(rang->eoff); + + if (rang->sidx == rang->eidx) + { + rang->smask &= rang->emask; /* combine the masks */ + rang->emask = rang->smask; + } + + return OK; +} + +/* checks if a range of granule matches the expected status */ + +bool gran_match(const gran_t *gran, size_t posi, size_t size, bool used, + size_t *mpos) +{ + uint32_t c; /* cell index */ + uint32_t v; /* masked cell value */ + uint32_t e; /* expected cell value */ + gatr_t r; /* range helper */ + + gran_range(gran, posi, size, &r); + + /* check the ending cell */ + + c = r.eidx; + e = used ? r.emask : 0 ; + v = gran->gat[c] & r.emask; + if (v != e) + { + goto failure; + } + + if (r.sidx == r.eidx) + { + return true; + } + + /* check cells in between */ + + c = r.eidx - 1; + e = used ? GATCFULL : 0; + for (; c > r.sidx; c--) + { + v = gran->gat[c]; + if (v != e) + { + goto failure; + } + } + + /* check the starting cell */ + + c = r.sidx; + e = used ? r.smask : 0 ; + v = gran->gat[c] & r.smask; + if (v != e) + { + goto failure; + } + + return true; + +failure: + + if (mpos && !used) + { + /* offset of last used when matching for free */ + + DEBUGASSERT(v); +#ifdef CONFIG_HAVE_BUILTIN_CLZ + *mpos = 31 - __builtin_clz(v); +#else + *mpos = (uint32_t)((msb_mask(v)) * DEBRUJIN_NUM) >> 27; + DEBUGASSERT(*mpos < sizeof(DEBRUJIN_LUT)); + *mpos = DEBRUJIN_LUT[*mpos]; +#endif + *mpos += c * GATC_BITS(gran); + } + + return false; +} + +/* returns granule number of free range or negative error */ + +int gran_search(const gran_t *gran, size_t size) +{ + int ret = -EINVAL; + + if (gran == NULL || gran->ngranules < size) + { + return ret; + } + + ret = -ENOMEM; + for (size_t i = 0; i <= gran->ngranules - size; i++) + { + if (gran_match(gran, i, size, 0, &i)) + { + ret = i; + break; + } + } + + return ret; +} + +/* set a range of granules */ + +int gran_set(gran_t *gran, size_t posi, size_t size) +{ + gatr_t rang; + int ret = gran_range(gran, posi, size, &rang); + + if (ret == OK) + { + gran_set_(gran, &rang, true); + } + + return ret; +} + +/* clear a range of granules */ + +int gran_clear(gran_t *gran, size_t posi, size_t size) +{ + gatr_t rang; + int ret = gran_range(gran, posi, size, &rang); + + if (ret == OK) + { + gran_set_(gran, &rang, false); + } + + return ret; +} + +#endif /* CONFIG_GRAN */ diff --git a/mm/mm_gran/mm_grantable.h b/mm/mm_gran/mm_grantable.h new file mode 100644 index 0000000000000..1a1864bf2cc00 --- /dev/null +++ b/mm/mm_gran/mm_grantable.h @@ -0,0 +1,159 @@ +/**************************************************************************** + * mm/mm_gran/mm_grantable.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __MM_MM_GRAN_MM_GRANTABLE_H +#define __MM_MM_GRAN_MM_GRANTABLE_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Granule arithmetics */ + +#define GRANSIZE(g) (1 << g->log2gran) +#define GRANMASK(g) (GRANSIZE(g) - 1) +#define NGRANULE(g, s) ((s + GRANMASK(g)) >> g->log2gran) + +#define GRANBYTE(g) ((size_t)g->ngranules << g->log2gran) +#define GRANENDA(g) (GRANBYTE(g) + g->heapstart) +#define MEM2GRAN(g, m) ((((uintptr_t)m) - g->heapstart) >> g->log2gran) +#define GRAN2MEM(g, x) ((((uintptr_t)x) << g->log2gran) + g->heapstart) + +#define GRAN_ALIGNED(g, m) ((((uintptr_t)(m)) & GRANMASK(g)) == 0) +#define GRAN_INRANGE(g, m) (g->heapstart <= (uintptr_t)(m) && \ + (uintptr_t)(m) < GRANENDA(g)) +#define GRAN_PRODUCT(g, m) (GRAN_ALIGNED(g, m) && GRAN_INRANGE(g, m)) + +#define ALIGNDN(g, m) (((size_t)m) & ~GRANMASK(g)) +#define ALIGNUP(g, m) ((((size_t)m) + GRANMASK(g)) & ~GRANMASK(g)) + +/* gran_reserve related */ + +#define MEM_RSRV(g, m) ALIGNDN(g, m) +#define END_RSRV(g, m, s) ALIGNUP(g, (((size_t)m) + s - 1)) +#define NUM_RSRV(g, m, s) (((END_RSRV(g, m, s) - MEM_RSRV(g, m)) \ + >> g->log2gran) + 1) +#define LEN_RSRV(g, m, s) ((size_t)(NUM_RSRV(g, m, s) << g->log2gran)) + +/* GAT table related */ + +#define GATC_BITS(g) (sizeof(g->gat[0]) << 3) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Structure for a range of granules in GAT */ + +struct gran_range_s +{ + uint16_t sidx; /* index of the starting GAT cell */ + uint16_t eidx; /* index of the ending GAT cell */ + uint8_t soff; /* offset of bit in starting cell */ + uint8_t eoff; /* offset of bit in ending cell */ + uint16_t width; /* width of cell in bits */ + uint32_t smask; /* mask of the starting GAT cell */ + uint32_t emask; /* mask of the ending GAT cell */ +}; + +typedef struct gran_range_s gatr_t; +typedef struct gran_s gran_t; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: gran_range + * + * Description: + * populate a gran_range_s instance for later use + * + * Input Parameters: + * gran - Pointer to the gran state + * posi - Position of starting granule + * size - Length of range + * + * Output Parameters: + * rang - The range instance to be prepared + * + * Return value: + * OK or negative errno + ****************************************************************************/ + +int gran_range(const gran_t *gran, size_t posi, size_t size, gatr_t *rang); + +/**************************************************************************** + * Name: gran_match + * + * Description: + * check if a continuous range of granules all have expected status + * + * Input Parameters: + * gran - Pointer to the gran state + * posi - Position of starting granule + * size - Length of range + * used - Expected state, true for used, false for empty. + * + * Output Parameters: + * mism - Optional last failed position upon free range matching. + * + * Return value: + * true for match, false otherwise. + ****************************************************************************/ + +bool gran_match(const gran_t *gran, size_t posi, size_t size, bool used, + size_t *mism); + +/**************************************************************************** + * Name: gran_search + * + * Description: + * search for continuous range of free granules + * + * Input Parameters: + * gran - Pointer to the gran state + * size - Length of range + * + * Return value: + * position of negative error number. + ****************************************************************************/ + +int gran_search(const gran_t *gran, size_t size); + +/**************************************************************************** + * Name: gran_set, gran_clear + * + * Description: + * Set or clear a range of granule in the GAT + * + * Input Parameters: + * gran - Pointer to the gran state + * posi - Range starting bit index + * size - Range size + * + * Return value: + * OK on success or negative value on error + ****************************************************************************/ + +int gran_set(gran_t *gran, size_t posi, size_t size); +int gran_clear(gran_t *gran, size_t posi, size_t size); + +#endif /* __MM_MM_GRAN_MM_GRANTABLE_H */ diff --git a/mm/mm_heap/mm.h b/mm/mm_heap/mm.h index 2df5fe6528d0d..eb7809e63823b 100644 --- a/mm/mm_heap/mm.h +++ b/mm/mm_heap/mm.h @@ -112,17 +112,19 @@ #define MM_MAX_CHUNK (1 << MM_MAX_SHIFT) #define MM_NNODES (MM_MAX_SHIFT - MM_MIN_SHIFT + 1) -#if CONFIG_MM_DFAULT_ALIGNMENT == 0 +#if CONFIG_MM_DEFAULT_ALIGNMENT == 0 # define MM_ALIGN (2 * sizeof(uintptr_t)) #else -# define MM_ALIGN CONFIG_MM_DFAULT_ALIGNMENT +# define MM_ALIGN CONFIG_MM_DEFAULT_ALIGNMENT #endif #define MM_GRAN_MASK (MM_ALIGN - 1) #define MM_ALIGN_UP(a) (((a) + MM_GRAN_MASK) & ~MM_GRAN_MASK) #define MM_ALIGN_DOWN(a) ((a) & ~MM_GRAN_MASK) -/* An allocated chunk is distinguished from a free chunk by bit 0 - * of the 'preceding' chunk size. If set, then this is an allocated chunk. +/* Due to alignment, the lowest two bits of valid chunk size are always + * zero, thus the two bits are reused to depict allocation status: bit + * 0 depicts the allocation state of current chunk, and bit 1 depicts that + * of the physically preceding chunk. */ #define MM_ALLOC_BIT 0x1 @@ -169,14 +171,11 @@ typedef uint16_t mmsize_t; typedef size_t mmsize_t; #endif -/* This describes an allocated chunk. An allocated chunk is - * distinguished from a free chunk by bit 15/31 of the 'preceding' chunk - * size. If set, then this is an allocated chunk. - */ +/* This describes an allocated chunk */ struct mm_allocnode_s { - mmsize_t preceding; /* Size of the preceding chunk */ + mmsize_t preceding; /* Physical preceding chunk size */ mmsize_t size; /* Size of this chunk */ #if CONFIG_MM_BACKTRACE >= 0 pid_t pid; /* The pid for caller */ @@ -191,7 +190,7 @@ struct mm_allocnode_s struct mm_freenode_s { - mmsize_t preceding; /* Size of the preceding chunk */ + mmsize_t preceding; /* Physical preceding chunk size */ mmsize_t size; /* Size of this chunk */ #if CONFIG_MM_BACKTRACE >= 0 pid_t pid; /* The pid for caller */ @@ -220,9 +219,7 @@ struct mm_delaynode_s struct mm_heap_s { - /* Mutually exclusive access to this data set is enforced with - * the following un-named mutex. - */ + /* Mutex for controling access to this heap */ mutex_t mm_lock; @@ -238,7 +235,7 @@ struct mm_heap_s size_t mm_curused; - /* This is the first and last nodes of the heap */ + /* The first and last allocated nodes of each region */ FAR struct mm_allocnode_s *mm_heapstart[CONFIG_MM_REGIONS]; FAR struct mm_allocnode_s *mm_heapend[CONFIG_MM_REGIONS]; @@ -249,14 +246,12 @@ struct mm_heap_s /* All free nodes are maintained in a doubly linked list. This * array provides some hooks into the list at various points to - * speed searches for free nodes. + * speed up searching of free nodes. */ struct mm_freenode_s mm_nodelist[MM_NNODES]; - /* Free delay list, for some situations where we can't do free - * immdiately. - */ + /* Free delay list, as sometimes we can't do free immdiately. */ FAR struct mm_delaynode_s *mm_delaylist[CONFIG_SMP_NCPUS]; diff --git a/mm/mm_heap/mm_checkcorruption.c b/mm/mm_heap/mm_checkcorruption.c index 2a195e4e4c43c..4b9e0c99691ef 100644 --- a/mm/mm_heap/mm_checkcorruption.c +++ b/mm/mm_heap/mm_checkcorruption.c @@ -44,18 +44,18 @@ static void checkcorruption_handler(FAR struct mm_allocnode_s *node, if (MM_NODE_IS_ALLOC(node)) { - assert(nodesize >= MM_SIZEOF_ALLOCNODE); + ASSERT(nodesize >= MM_SIZEOF_ALLOCNODE); } else { FAR struct mm_freenode_s *fnode = (FAR void *)node; - assert(nodesize >= MM_MIN_CHUNK); - assert(fnode->blink->flink == fnode); - assert(MM_SIZEOF_NODE(fnode->blink) <= nodesize); - assert(fnode->flink == NULL || + ASSERT(nodesize >= MM_MIN_CHUNK); + ASSERT(fnode->blink->flink == fnode); + ASSERT(MM_SIZEOF_NODE(fnode->blink) <= nodesize); + ASSERT(fnode->flink == NULL || fnode->flink->blink == fnode); - assert(fnode->flink == NULL || + ASSERT(fnode->flink == NULL || MM_SIZEOF_NODE(fnode->flink) == 0 || MM_SIZEOF_NODE(fnode->flink) >= nodesize); } diff --git a/mm/mm_heap/mm_free.c b/mm/mm_heap/mm_free.c index d29f901e846a5..6b2fc51e10045 100644 --- a/mm/mm_heap/mm_free.c +++ b/mm/mm_heap/mm_free.c @@ -28,6 +28,7 @@ #include #include +#include #include #include "mm_heap/mm.h" @@ -47,11 +48,11 @@ static void add_delaylist(FAR struct mm_heap_s *heap, FAR void *mem) flags = up_irq_save(); - tmp->flink = heap->mm_delaylist[up_cpu_index()]; - heap->mm_delaylist[up_cpu_index()] = tmp; + tmp->flink = heap->mm_delaylist[this_cpu()]; + heap->mm_delaylist[this_cpu()] = tmp; #if CONFIG_MM_FREE_DELAYCOUNT_MAX > 0 - heap->mm_delaycount[up_cpu_index()]++; + heap->mm_delaycount[this_cpu()]++; #endif up_irq_restore(flags); @@ -90,7 +91,7 @@ void mm_delayfree(FAR struct mm_heap_s *heap, FAR void *mem, bool delay) } #ifdef CONFIG_MM_FILL_ALLOCATIONS - memset(mem, 0x55, mm_malloc_size(heap, mem)); + memset(mem, MM_FREE_MAGIC, mm_malloc_size(heap, mem)); #endif kasan_poison(mem, mm_malloc_size(heap, mem)); diff --git a/mm/mm_heap/mm_initialize.c b/mm/mm_heap/mm_initialize.c index 676f1901f4284..31c44d64ef8fd 100644 --- a/mm/mm_heap/mm_initialize.c +++ b/mm/mm_heap/mm_initialize.c @@ -129,6 +129,12 @@ void mm_addregion(FAR struct mm_heap_s *heap, FAR void *heapstart, DEBUGASSERT(heapsize <= MMSIZE_MAX + 1); #endif +#ifdef CONFIG_MM_FILL_ALLOCATIONS + /* Use the fill value to mark uninitialized user memory */ + + memset(heapstart, MM_INIT_MAGIC, heapsize); +#endif + /* Register to KASan for access check */ kasan_register(heapstart, &heapsize); diff --git a/mm/mm_heap/mm_malloc.c b/mm/mm_heap/mm_malloc.c index 30e307f577826..cd1b06ab97b61 100644 --- a/mm/mm_heap/mm_malloc.c +++ b/mm/mm_heap/mm_malloc.c @@ -64,21 +64,21 @@ static bool free_delaylist(FAR struct mm_heap_s *heap, bool force) flags = up_irq_save(); - tmp = heap->mm_delaylist[up_cpu_index()]; + tmp = heap->mm_delaylist[this_cpu()]; #if CONFIG_MM_FREE_DELAYCOUNT_MAX > 0 if (tmp == NULL || (!force && - heap->mm_delaycount[up_cpu_index()] < CONFIG_MM_FREE_DELAYCOUNT_MAX)) + heap->mm_delaycount[this_cpu()] < CONFIG_MM_FREE_DELAYCOUNT_MAX)) { up_irq_restore(flags); return false; } - heap->mm_delaycount[up_cpu_index()] = 0; + heap->mm_delaycount[this_cpu()] = 0; #endif - heap->mm_delaylist[up_cpu_index()] = NULL; + heap->mm_delaylist[this_cpu()] = NULL; up_irq_restore(flags); @@ -305,7 +305,7 @@ FAR void *mm_malloc(FAR struct mm_heap_s *heap, size_t size) MM_ADD_BACKTRACE(heap, node); kasan_unpoison(ret, mm_malloc_size(heap, ret)); #ifdef CONFIG_MM_FILL_ALLOCATIONS - memset(ret, 0xaa, alignsize - MM_ALLOCNODE_OVERHEAD); + memset(ret, MM_ALLOC_MAGIC, alignsize - MM_ALLOCNODE_OVERHEAD); #endif #ifdef CONFIG_DEBUG_MM minfo("Allocated %p, size %zu\n", ret, alignsize); diff --git a/mm/tlsf/mm_tlsf.c b/mm/tlsf/mm_tlsf.c index ad7801f670e6d..e67f73d79680f 100644 --- a/mm/tlsf/mm_tlsf.c +++ b/mm/tlsf/mm_tlsf.c @@ -189,11 +189,11 @@ static void add_delaylist(FAR struct mm_heap_s *heap, FAR void *mem) flags = up_irq_save(); - tmp->flink = heap->mm_delaylist[up_cpu_index()]; - heap->mm_delaylist[up_cpu_index()] = tmp; + tmp->flink = heap->mm_delaylist[this_cpu()]; + heap->mm_delaylist[this_cpu()] = tmp; #if CONFIG_MM_FREE_DELAYCOUNT_MAX > 0 - heap->mm_delaycount[up_cpu_index()]++; + heap->mm_delaycount[this_cpu()]++; #endif up_irq_restore(flags); @@ -215,21 +215,21 @@ static bool free_delaylist(FAR struct mm_heap_s *heap, bool force) flags = up_irq_save(); - tmp = heap->mm_delaylist[up_cpu_index()]; + tmp = heap->mm_delaylist[this_cpu()]; #if CONFIG_MM_FREE_DELAYCOUNT_MAX > 0 if (tmp == NULL || (!force && - heap->mm_delaycount[up_cpu_index()] < CONFIG_MM_FREE_DELAYCOUNT_MAX)) + heap->mm_delaycount[this_cpu()] < CONFIG_MM_FREE_DELAYCOUNT_MAX)) { up_irq_restore(flags); return false; } - heap->mm_delaycount[up_cpu_index()] = 0; + heap->mm_delaycount[this_cpu()] = 0; #endif - heap->mm_delaylist[up_cpu_index()] = NULL; + heap->mm_delaylist[this_cpu()] = NULL; up_irq_restore(flags); @@ -503,7 +503,7 @@ static void mm_delayfree(FAR struct mm_heap_s *heap, FAR void *mem, if (mm_lock(heap) == 0) { #ifdef CONFIG_MM_FILL_ALLOCATIONS - memset(mem, 0x55, mm_malloc_size(heap, mem)); + memset(mem, MM_FREE_MAGIC, mm_malloc_size(heap, mem)); #endif kasan_poison(mem, mm_malloc_size(heap, mem)); @@ -575,6 +575,12 @@ void mm_addregion(FAR struct mm_heap_s *heap, FAR void *heapstart, # define idx 0 #endif +#ifdef CONFIG_MM_FILL_ALLOCATIONS + /* Use the fill value to mark uninitialized user memory */ + + memset(heapstart, 0xcc, heapsize); +#endif + /* Register to KASan for access check */ kasan_register(heapstart, &heapsize); @@ -1144,7 +1150,7 @@ FAR void *mm_malloc(FAR struct mm_heap_s *heap, size_t size) kasan_unpoison(ret, mm_malloc_size(heap, ret)); #ifdef CONFIG_MM_FILL_ALLOCATIONS - memset(ret, 0xaa, mm_malloc_size(heap, ret)); + memset(ret, 0xaa, nodesize); #endif } diff --git a/net/Kconfig b/net/Kconfig index 1eca79c99e5ad..cbe807a50a982 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -57,6 +57,20 @@ config NET_PROMISCUOUS Force the Ethernet driver to operate in promiscuous mode (if supported by the Ethernet driver). +config NET_DEFAULT_MIN_PORT + int "Net Default Min Port" + range 1 65535 + default 4096 + ---help--- + Default Network min port + +config NET_DEFAULT_MAX_PORT + int "Net Default Max Port" + range NET_DEFAULT_MIN_PORT 65535 + default 32000 + ---help--- + Default Network max port + menu "Driver buffer configuration" config NET_ETH_PKTSIZE @@ -394,7 +408,7 @@ choice depends on NET_STAR default NET_STARPOINT ---help--- - Specifies the role of this not in the star configuration. + Specifies the role of this node in the star configuration. config NET_STARPOINT bool "Point node in star" diff --git a/net/arp/Kconfig b/net/arp/Kconfig index 01a8032065cee..9b3286fed603b 100644 --- a/net/arp/Kconfig +++ b/net/arp/Kconfig @@ -76,5 +76,12 @@ config NET_ARP_DUMP ---help--- Dump ARP packets to the SYSLOG device. +config NET_ARP_ACD + bool "Support of ARP address Address Conflict Detection" + default n + depends on NET_ARP_SEND + ---help--- + Enable Support of ARP address Address Conflict Detection + endif # NET_ARP endmenu # ARP Configuration diff --git a/net/arp/Make.defs b/net/arp/Make.defs index a48d007898594..c090646baf844 100644 --- a/net/arp/Make.defs +++ b/net/arp/Make.defs @@ -35,6 +35,10 @@ ifeq ($(CONFIG_NET_ARP_DUMP),y) NET_CSRCS += arp_dump.c endif +ifeq ($(CONFIG_NET_ARP_ACD),y) +NET_CSRCS += arp_acd.c +endif + # Include arp build support DEPPATH += --dep-path arp diff --git a/net/arp/arp.h b/net/arp/arp.h index 7e2c9887c289d..03648007f4591 100644 --- a/net/arp/arp.h +++ b/net/arp/arp.h @@ -128,9 +128,12 @@ struct arp_iphdr_s * operated upon from the network driver poll. */ +typedef CODE void (*arp_send_finish_cb_t)(FAR struct net_driver_s *dev, + int result); struct arp_send_s { FAR struct devif_callback_s *snd_cb; /* Reference to callback instance */ + FAR arp_send_finish_cb_t finish_cb; /* Reference to send finish callback */ sem_t snd_sem; /* Used to wake up the waiting thread */ uint8_t snd_retries; /* Retry count */ volatile bool snd_sent; /* True: if request sent */ @@ -275,6 +278,33 @@ int arp_send(in_addr_t ipaddr); # define arp_send(i) (0) #endif +/**************************************************************************** + * Name: arp_send_async + * + * Description: + * The arp_send_async() call may be to send an ARP request asyncly to + * resolve an IPv4 address. + * + * Input Parameters: + * ipaddr The IP address to be queried. + * cb The callback when ARP send is finished, should not be NULL. + * + * Returned Value: + * Zero (OK) is returned on success the arp been sent to the driver. + * On error a negated errno value is returned: + * + * -ETIMEDOUT: The number or retry counts has been exceed. + * -EHOSTUNREACH: Could not find a route to the host + * + * Assumptions: + * This function is called from the normal tasking context. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_ARP_SEND +int arp_send_async(in_addr_t ipaddr, arp_send_finish_cb_t cb); +#endif + /**************************************************************************** * Name: arp_poll * @@ -523,6 +553,58 @@ void arp_dump(FAR struct arp_hdr_s *arp); # define arp_dump(arp) #endif +#ifdef CONFIG_NET_ARP_ACD + +/**************************************************************************** + * Name: arp_acd_update + * + * Description: + * interface of ARP Address Conflict Detection monitor + * + * Input Parameters: + * dev - The device driver structure to use in the send operation + * + * Returned Value: + * none + * + ****************************************************************************/ + +void arp_acd_update(FAR struct net_driver_s *dev); + +/**************************************************************************** + * Name: arp_acd_set_addr + * + * Description: + * setting address interface of ARP Address Conflict Detection + * + * Input Parameters: + * dev - The device driver structure to use in the send operation + * + * Returned Value: + * none + * + ****************************************************************************/ + +void arp_acd_set_addr(FAR struct net_driver_s *dev); + +/**************************************************************************** + * Name: arp_acd_setup + * + * Description: + * set up interface of ARP Address Conflict Detection + * + * Input Parameters: + * dev - The device driver structure to use in the send operation + * + * Returned Value: + * none + * + ****************************************************************************/ + +void arp_acd_setup(FAR struct net_driver_s *dev); + +#endif /* CONFIG_NET_ARP_ACD */ + #else /* CONFIG_NET_ARP */ /* If ARP is disabled, stub out all ARP interfaces */ diff --git a/net/arp/arp_acd.c b/net/arp/arp_acd.c new file mode 100644 index 0000000000000..20a182e8d86bc --- /dev/null +++ b/net/arp/arp_acd.c @@ -0,0 +1,281 @@ +/**************************************************************************** + * net/arp/arp_acd.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ +#include + +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "arp/arp.h" +#include "netlink/netlink.h" +#include "utils/utils.h" + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void arp_acd_try_announce(FAR void *net_dev); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arp_acd_arrange_announce + * + * Description: + * creat work_queue to send ARP announce + * + * Input Parameters: + * dev - The device driver structure to use in the send operation + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void arp_acd_arrange_announce(FAR struct net_driver_s *dev) +{ + if (dev->d_acd.need_announce == true) + { + return; + } + + if (!work_available(&dev->d_acd.work)) + { + nerr("ERROR work unavailable \n"); + return; + } + + int ret = work_queue(LPWORK, &dev->d_acd.work, arp_acd_try_announce, + (FAR void *)dev, DSEC2TICK(dev->d_acd.ttw)); + if (ret != OK) + { + nerr("ERROR ret %d \n", ret); + } +} + +/**************************************************************************** + * Name: arp_acd_send_finish + * + * Description: + * send finish process of ARP Address Conflict Detection + * + * Input Parameters: + * dev - The device driver structure to use in the send operation + * result - arp send result + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void arp_acd_send_finish(FAR struct net_driver_s *dev, int result) +{ + if (result < 0) + { + nerr("ERROR: arp_send result: %d\n", result); + } + else + { + arp_acd_arrange_announce(dev); + } +} + +/**************************************************************************** + * Name: arp_acd_try_announce + * + * Description: + * process status of ARP Address Conflict Detection + * + * Input Parameters: + * net_dev - The device driver structure to use in the send operation + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void arp_acd_try_announce(FAR void *net_dev) +{ + FAR struct net_driver_s *dev = net_dev; + + if (dev == NULL || dev->d_acd.state != ARP_ACD_STATE_ANNOUNCING) + { + return; + } + + /* arp_acd_announce */ + + arp_send_async(dev->d_ipaddr, arp_acd_send_finish); + dev->d_acd.sendnum++; + + if (dev->d_acd.sendnum >= ANNOUNCE_NUM) + { + dev->d_acd.sendnum = 0; + dev->d_acd.ttw = 0; + dev->d_acd.state = ARP_ACD_STATE_FINISH; + } + else + { + dev->d_acd.ttw = ANNOUNCE_INTERVAL * ARP_ACD_TICKS_PER_SECOND; + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: arp_acd_update + * + * Description: + * interface of ARP Address Conflict Detection monitor + * + * Input Parameters: + * dev - The device driver structure to use in the send operation + * + * Returned Value: + * none + * + ****************************************************************************/ + +void arp_acd_update(FAR struct net_driver_s *dev) +{ + FAR struct arp_hdr_s *arp = ARPBUF; + clock_t now = clock_systime_ticks(); + + if (dev->d_acd.conflict_flag == ARP_ACD_ADDRESS_CONFLICT) + { + return; + } + + if (!net_ipv4addr_hdrcmp(arp->ah_sipaddr, &dev->d_ipaddr) || + (memcmp(arp->ah_shwaddr, dev->d_mac.ether.ether_addr_octet, + sizeof(arp->ah_shwaddr)) == 0)) + { + return; + } + + if ((dev->d_acd.lastconflict > 0) && + (now - dev->d_acd.lastconflict) < + DSEC2TICK(DEFEND_INTERVAL * ARP_ACD_TICKS_PER_SECOND)) + { + nerr("ERROR: detect conflict again \n"); + dev->d_acd.lastconflict = 0; + dev->d_acd.conflict_flag = ARP_ACD_ADDRESS_CONFLICT; + if (dev->d_acd.state != ARP_ACD_STATE_ANNOUNCING) + { + dev->d_acd.state = ARP_ACD_STATE_INIT; + dev->d_acd.sendnum = 0; + dev->d_acd.ttw = 0; + } + } + else + { + nerr("ERROR: detect conflict \n"); + dev->d_acd.lastconflict = now; + if (dev->d_acd.state != ARP_ACD_STATE_ANNOUNCING) + { + arp_acd_arrange_announce(dev); + + dev->d_acd.state = ARP_ACD_STATE_ANNOUNCING; + dev->d_acd.sendnum = 0; + dev->d_acd.ttw = + ANNOUNCE_WAIT * ARP_ACD_TICKS_PER_SECOND; + } + } +} + +/**************************************************************************** + * Name: arp_acd_setup + * + * Description: + * set up interface of ARP Address Conflict Detection + * + * Input Parameters: + * dev - The device driver structure to use in the send operation + * + * Returned Value: + * none + * + ****************************************************************************/ + +void arp_acd_setup(FAR struct net_driver_s *dev) +{ + if (dev->d_acd.need_announce == false) + { + return; + } + + dev->d_acd.state = ARP_ACD_STATE_ANNOUNCING; + dev->d_acd.sendnum = 0; + dev->d_acd.ttw = 0; + dev->d_acd.conflict_flag = ARP_ACD_ADDRESS_NO_CONFLICT; + dev->d_acd.lastconflict = 0; + dev->d_acd.need_announce = false; + + arp_acd_arrange_announce(dev); +} + +/**************************************************************************** + * Name: arp_acd_set_addr + * + * Description: + * setting address interface of ARP Address Conflict Detection + * + * Input Parameters: + * dev - The device driver structure to use in the send operation + * + * Returned Value: + * none + * + ****************************************************************************/ + +void arp_acd_set_addr(FAR struct net_driver_s *dev) +{ + if (!net_ipv4addr_cmp(dev->d_ipaddr, INADDR_ANY)) + { + dev->d_acd.need_announce = true; + if (IFF_IS_UP(dev->d_flags)) + { + arp_acd_setup(dev); + } + } + else + { + dev->d_acd.need_announce = false; + dev->d_acd.state = ARP_ACD_STATE_INIT; + } +} diff --git a/net/arp/arp_input.c b/net/arp/arp_input.c index 03892bb1dca86..a76f48fa61388 100644 --- a/net/arp/arp_input.c +++ b/net/arp/arp_input.c @@ -98,6 +98,11 @@ static int arp_in(FAR struct net_driver_s *dev) dev->d_len = 0; ipaddr = net_ip4addr_conv32(arp->ah_dipaddr); + +#ifdef CONFIG_NET_ARP_ACD + arp_acd_update(dev); +#endif /* CONFIG_NET_ARP_ACD */ + switch (arp->ah_opcode) { case HTONS(ARP_REQUEST): diff --git a/net/arp/arp_send.c b/net/arp/arp_send.c index bed3b5896642a..6eb568b10b1f7 100644 --- a/net/arp/arp_send.c +++ b/net/arp/arp_send.c @@ -31,6 +31,7 @@ #include #include +#include #include #include #include @@ -50,7 +51,8 @@ * Name: arp_send_terminate ****************************************************************************/ -static void arp_send_terminate(FAR struct arp_send_s *state, int result) +static void arp_send_terminate(FAR struct net_driver_s *dev, + FAR struct arp_send_s *state, int result) { /* Don't allow any further call backs. */ @@ -63,6 +65,14 @@ static void arp_send_terminate(FAR struct arp_send_s *state, int result) /* Wake up the waiting thread */ nxsem_post(&state->snd_sem); + + if (state->finish_cb != NULL) + { + nxsem_destroy(&state->snd_sem); + arp_callback_free(dev, state->snd_cb); + state->finish_cb(dev, result); + kmm_free(state); + } } /**************************************************************************** @@ -93,7 +103,7 @@ static uint16_t arp_send_eventhandler(FAR struct net_driver_s *dev, if ((flags & NETDEV_DOWN) != 0) { nerr("ERROR: Interface is down\n"); - arp_send_terminate(state, -ENETUNREACH); + arp_send_terminate(dev, state, -ENETUNREACH); return flags; } @@ -130,7 +140,7 @@ static uint16_t arp_send_eventhandler(FAR struct net_driver_s *dev, /* Don't allow any further call backs. */ - arp_send_terminate(state, OK); + arp_send_terminate(dev, state, OK); } return flags; @@ -319,6 +329,7 @@ int arp_send(in_addr_t ipaddr) state.snd_cb->flags = (ARP_POLL | NETDEV_DOWN); state.snd_cb->priv = (FAR void *)&state; state.snd_cb->event = arp_send_eventhandler; + state.finish_cb = NULL; /* Notify the device driver that new TX data is available. */ @@ -385,4 +396,82 @@ int arp_send(in_addr_t ipaddr) return ret; } +/**************************************************************************** + * Name: arp_send_async + * + * Description: + * The arp_send_async() call may be to send an ARP request asyncly to + * resolve an IPv4 address. + * + * Input Parameters: + * ipaddr The IP address to be queried. + * cb The callback when ARP send is finished, should not be NULL. + * + * Returned Value: + * Zero (OK) is returned on success the arp been sent to the driver. + * On error a negated errno value is returned: + * + * -ETIMEDOUT: The number or retry counts has been exceed. + * -EHOSTUNREACH: Could not find a route to the host + * + * Assumptions: + * This function is called from the normal tasking context. + * + ****************************************************************************/ + +int arp_send_async(in_addr_t ipaddr, arp_send_finish_cb_t cb) +{ + FAR struct net_driver_s *dev; + FAR struct arp_send_s *state = kmm_zalloc(sizeof(struct arp_send_s)); + int ret = 0; + + if (!state) + { + nerr("ERROR: %s \n", ENOMEM_STR); + ret = -ENOMEM; + goto errout; + } + + dev = netdev_findby_ripv4addr(INADDR_ANY, ipaddr); + if (!dev) + { + nerr("ERROR: Unreachable: %08lx\n", (unsigned long)ipaddr); + ret = -EHOSTUNREACH; + goto errout; + } + + net_lock(); + state->snd_cb = arp_callback_alloc(dev); + if (!state->snd_cb) + { + nerr("ERROR: Failed to allocate a callback\n"); + ret = -ENOMEM; + goto errout_with_lock; + } + + nxsem_init(&state->snd_sem, 0, 0); /* Doesn't really fail */ + state->snd_ipaddr = ipaddr; /* IP address to query */ + + /* Remember the routing device name */ + + strlcpy((FAR char *)state->snd_ifname, + (FAR const char *)dev->d_ifname, IFNAMSIZ); + + /* Arm/re-arm the callback */ + + state->snd_cb->flags = (ARP_POLL | NETDEV_DOWN); + state->snd_cb->priv = (FAR void *)state; + state->snd_cb->event = arp_send_eventhandler; + state->finish_cb = cb; + + /* Notify the device driver that new TX data is available. */ + + netdev_txnotify_dev(dev); + +errout_with_lock: + net_unlock(); +errout: + return ret; +} + #endif /* CONFIG_NET_ARP_SEND */ diff --git a/net/arp/arp_table.c b/net/arp/arp_table.c index cfba3d2d6705b..5b4c691f3ce0a 100644 --- a/net/arp/arp_table.c +++ b/net/arp/arp_table.c @@ -61,6 +61,7 @@ #include #include "netdev/netdev.h" +#include "netlink/netlink.h" #include "arp/arp.h" #ifdef CONFIG_NET_ARP @@ -208,6 +209,37 @@ static FAR struct arp_entry_s *arp_lookup(in_addr_t ipaddr, return NULL; } +/**************************************************************************** + * Name: arp_get_arpreq + * + * Description: + * Translate (struct arp_entry_s) to (struct arpreq) for netlink notify. + * + * Input Parameters: + * output - Location to return the ARP table copy + * input - The arp entry in table + * + ****************************************************************************/ + +#ifdef CONFIG_NETLINK_ROUTE +static void arp_get_arpreq(FAR struct arpreq *output, + FAR struct arp_entry_s *input) +{ + FAR struct sockaddr_in *outaddr; + + DEBUGASSERT(output != NULL && input != NULL); + + outaddr = (FAR struct sockaddr_in *)&output->arp_pa; + outaddr->sin_family = AF_INET; + outaddr->sin_port = 0; + outaddr->sin_addr.s_addr = input->at_ipaddr; + memcpy(output->arp_ha.sa_data, input->at_ethaddr.ether_addr_octet, + sizeof(struct ether_addr)); + strlcpy((FAR char *)output->arp_dev, input->at_dev->d_ifname, + sizeof(output->arp_dev)); +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -237,6 +269,11 @@ int arp_update(FAR struct net_driver_s *dev, in_addr_t ipaddr, FAR const uint8_t *ethaddr) { FAR struct arp_entry_s *tabptr = &g_arptable[0]; +#ifdef CONFIG_NETLINK_ROUTE + struct arpreq arp_notify; + bool found = false; + bool new_entry; +#endif int i; /* Walk through the ARP mapping table and try to find an entry to @@ -257,6 +294,9 @@ int arp_update(FAR struct net_driver_s *dev, in_addr_t ipaddr, /* An old entry found, break. */ tabptr = &g_arptable[i]; +#ifdef CONFIG_NETLINK_ROUTE + found = true; +#endif break; } else @@ -267,6 +307,21 @@ int arp_update(FAR struct net_driver_s *dev, in_addr_t ipaddr, } } + /* When overwite old entry, notify old entry RTM_DELNEIGH */ + +#ifdef CONFIG_NETLINK_ROUTE + if (!found && tabptr->at_ipaddr != 0) + { + arp_get_arpreq(&arp_notify, tabptr); + netlink_neigh_notify(&arp_notify, RTM_DELNEIGH, AF_INET); + } + + /* Need to notify when entry is not found or changes in table */ + + new_entry = !found || memcmp(tabptr->at_ethaddr.ether_addr_octet, + ethaddr, ETHER_ADDR_LEN) != 0; +#endif + /* Now, tabptr is the ARP table entry which we will fill with the new * information. */ @@ -275,6 +330,17 @@ int arp_update(FAR struct net_driver_s *dev, in_addr_t ipaddr, memcpy(tabptr->at_ethaddr.ether_addr_octet, ethaddr, ETHER_ADDR_LEN); tabptr->at_dev = dev; tabptr->at_time = clock_systime_ticks(); + + /* Notify the new entry */ + +#ifdef CONFIG_NETLINK_ROUTE + if (new_entry) + { + arp_get_arpreq(&arp_notify, tabptr); + netlink_neigh_notify(&arp_notify, RTM_NEWNEIGH, AF_INET); + } +#endif + return OK; } @@ -392,12 +458,21 @@ int arp_find(in_addr_t ipaddr, FAR uint8_t *ethaddr, int arp_delete(in_addr_t ipaddr, FAR struct net_driver_s *dev) { FAR struct arp_entry_s *tabptr; - +#ifdef CONFIG_NETLINK_ROUTE + struct arpreq arp_notify; +#endif /* Check if the IPv4 address is in the ARP table. */ tabptr = arp_lookup(ipaddr, dev); if (tabptr != NULL) { + /* Notify to netlink */ + +#ifdef CONFIG_NETLINK_ROUTE + arp_get_arpreq(&arp_notify, tabptr); + netlink_neigh_notify(&arp_notify, RTM_DELNEIGH, AF_INET); +#endif + /* Yes.. Set the IP address to zero to "delete" it */ tabptr->at_ipaddr = 0; @@ -459,7 +534,6 @@ unsigned int arp_snapshot(FAR struct arpreq *snapshot, unsigned int nentries) { FAR struct arp_entry_s *tabptr; - FAR struct sockaddr_in *outaddr; clock_t now; unsigned int ncopied; int i; @@ -474,16 +548,7 @@ unsigned int arp_snapshot(FAR struct arpreq *snapshot, if (tabptr->at_ipaddr != 0 && now - tabptr->at_time <= ARP_MAXAGE_TICK) { - outaddr = (FAR struct sockaddr_in *)&snapshot[ncopied].arp_pa; - outaddr->sin_family = AF_INET; - outaddr->sin_port = 0; - outaddr->sin_addr.s_addr = tabptr->at_ipaddr; - memcpy(snapshot[ncopied].arp_ha.sa_data, - tabptr->at_ethaddr.ether_addr_octet, - sizeof(struct ether_addr)); - strlcpy((FAR char *)snapshot[ncopied].arp_dev, - tabptr->at_dev->d_ifname, - sizeof(snapshot[ncopied].arp_dev)); + arp_get_arpreq(&snapshot[ncopied], tabptr); ncopied++; } } diff --git a/net/bluetooth/bluetooth_conn.c b/net/bluetooth/bluetooth_conn.c index 8fd6e1df622f8..38b3115ae559a 100644 --- a/net/bluetooth/bluetooth_conn.c +++ b/net/bluetooth/bluetooth_conn.c @@ -125,7 +125,7 @@ FAR struct bluetooth_conn_s *bluetooth_conn_alloc(void) { #if CONFIG_NET_BLUETOOTH_MAX_CONNS > 0 if (dq_count(&g_active_bluetooth_connections) + - CONFIG_NET_BLUETOOTH_ALLOC_CONNS >= CONFIG_NET_BLUETOOTH_MAX_CONNS) + CONFIG_NET_BLUETOOTH_ALLOC_CONNS > CONFIG_NET_BLUETOOTH_MAX_CONNS) { net_unlock(); return NULL; diff --git a/net/can/can.h b/net/can/can.h index 46de920dc880a..1c0a78c006082 100644 --- a/net/can/can.h +++ b/net/can/can.h @@ -184,6 +184,25 @@ void can_free(FAR struct can_conn_s *conn); FAR struct can_conn_s *can_nextconn(FAR struct can_conn_s *conn); +/**************************************************************************** + * Name: can_active() + * + * Description: + * Traverse the list of NetLink connections that match dev + * + * Input Parameters: + * dev - The device to search for. + * conn - The current connection; may be NULL to start the search at the + * beginning + * + * Assumptions: + * This function is called from NetLink device logic. + * + ****************************************************************************/ + +FAR struct can_conn_s *can_active(FAR struct net_driver_s *dev, + FAR struct can_conn_s *conn); + /**************************************************************************** * Name: can_callback * diff --git a/net/can/can_callback.c b/net/can/can_callback.c index d8ebfc65506ef..0ca5363406d1c 100644 --- a/net/can/can_callback.c +++ b/net/can/can_callback.c @@ -214,11 +214,16 @@ uint16_t can_datahandler(FAR struct net_driver_s *dev, can_readahead_signal(conn); #endif ret = iob->io_pktlen; - } - /* Device buffer must be enqueue or freed, clear the handle */ + /* Device buffer has been enqueued, clear the handle */ - netdev_iob_clear(dev); + netdev_iob_clear(dev); + } + else + { + nerr("ERROR: Failed to queue the I/O buffer chain: %d\n", ret); + netdev_iob_release(dev); + } return ret; } diff --git a/net/can/can_conn.c b/net/can/can_conn.c index 28f1a46001a87..a6cd63bc202ed 100644 --- a/net/can/can_conn.c +++ b/net/can/can_conn.c @@ -112,8 +112,8 @@ FAR struct can_conn_s *can_alloc(void) if (dq_peek(&g_free_can_connections) == NULL) { #if CONFIG_CAN_MAX_CONNS > 0 - if (dq_count(&g_active_can_connections) + CONFIG_CAN_ALLOC_CONNS - >= CONFIG_CAN_MAX_CONNS) + if (dq_count(&g_active_can_connections) + + CONFIG_CAN_ALLOC_CONNS > CONFIG_CAN_MAX_CONNS) { nxmutex_unlock(&g_free_lock); return NULL; @@ -225,4 +225,34 @@ FAR struct can_conn_s *can_nextconn(FAR struct can_conn_s *conn) } } +/**************************************************************************** + * Name: can_active() + * + * Description: + * Traverse the list of NetLink connections that match dev + * + * Input Parameters: + * dev - The device to search for. + * conn - The current connection; may be NULL to start the search at the + * beginning + * + * Assumptions: + * This function is called from NetLink device logic. + * + ****************************************************************************/ + +FAR struct can_conn_s *can_active(FAR struct net_driver_s *dev, + FAR struct can_conn_s *conn) +{ + while ((conn = can_nextconn(conn)) != NULL) + { + if (conn->dev == NULL || conn->dev == dev) + { + break; + } + } + + return conn; +} + #endif /* CONFIG_NET_CAN */ diff --git a/net/can/can_input.c b/net/can/can_input.c index 42ae6c86ff048..35d4a73fd1d3d 100644 --- a/net/can/can_input.c +++ b/net/can/can_input.c @@ -128,17 +128,18 @@ const uint8_t len_to_can_dlc[65] = }; /**************************************************************************** - * Public Functions + * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: can_in + * Name: can_input_conn * * Description: * Handle incoming packet input * * Input Parameters: - * dev - The device driver structure containing the received packet + * dev - The device driver structure containing the received packet + * conn - A pointer to the CAN connection structure * * Returned Value: * OK The packet has been processed and can be deleted @@ -151,50 +152,96 @@ const uint8_t len_to_can_dlc[65] = * ****************************************************************************/ -static int can_in(struct net_driver_s *dev) +static int can_input_conn(FAR struct net_driver_s *dev, + FAR struct can_conn_s *conn) { - FAR struct can_conn_s *conn = NULL; - int ret = OK; + uint16_t flags; uint16_t buflen = dev->d_len; + int ret = OK; + + /* Setup for the application callback */ - do + dev->d_appdata = dev->d_buf; + dev->d_sndlen = 0; + dev->d_len = buflen; + + /* Perform the application callback */ + + flags = can_callback(dev, conn, CAN_NEWDATA); + + /* If the operation was successful, the CAN_NEWDATA flag is removed + * and thus the packet can be deleted (OK will be returned). + */ + + if ((flags & CAN_NEWDATA) != 0) { - conn = can_nextconn(conn); + /* No.. the packet was not processed now. Return -EAGAIN so + * that the driver may retry again later. We still need to + * set d_len to zero so that the driver is aware that there + * is nothing to be sent. + */ - if (conn && (conn->dev == NULL || dev == conn->dev)) - { - uint16_t flags; + nwarn("WARNING: Packet not processed\n"); + ret = -EAGAIN; + } - /* Setup for the application callback */ + return ret; +} - dev->d_appdata = dev->d_buf; - dev->d_sndlen = 0; - dev->d_len = buflen; +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: can_in + * + * Description: + * Handle incoming packet input + * + * Input Parameters: + * dev - The device driver structure containing the received packet + * + * Returned Value: + * OK The packet has been processed and can be deleted + * -EAGAIN There is a matching connection, but could not dispatch the packet + * yet. Useful when a packet arrives before a recv call is in + * place. + * + * Assumptions: + * This function can be called from an interrupt. + * + ****************************************************************************/ - /* Perform the application callback */ +static int can_in(FAR struct net_driver_s *dev) +{ + FAR struct can_conn_s *conn = can_active(dev, NULL); + FAR struct can_conn_s *nextconn; - flags = can_callback(dev, conn, CAN_NEWDATA); + /* Do we have second connection that can hold this packet? */ - /* If the operation was successful, the CAN_NEWDATA flag is removed - * and thus the packet can be deleted (OK will be returned). - */ + while ((nextconn = can_active(dev, conn)) != NULL) + { + /* Yes... There are multiple listeners on the same dev. + * We need to clone the packet and deliver it to each listener. + */ - if ((flags & CAN_NEWDATA) != 0) - { - /* No.. the packet was not processed now. Return -EAGAIN so - * that the driver may retry again later. We still need to - * set d_len to zero so that the driver is aware that there - * is nothing to be sent. - */ + FAR struct iob_s *iob = netdev_iob_clone(dev, false); - nwarn("WARNING: Packet not processed\n"); - ret = -EAGAIN; - } + if (iob == NULL) + { + nerr("ERROR: IOB clone failed.\n"); + break; /* We can still process one time without clone. */ } + + can_input_conn(dev, conn); + + netdev_iob_replace(dev, iob); + conn = nextconn; } - while (conn); - return ret; + /* We can deliver the packet directly to the last listener. */ + + return can_input_conn(dev, conn); } /**************************************************************************** diff --git a/net/devif/ipv4_input.c b/net/devif/ipv4_input.c index 4e7f2eb16f17d..0875c786a8124 100644 --- a/net/devif/ipv4_input.c +++ b/net/devif/ipv4_input.c @@ -235,14 +235,10 @@ static int ipv4_in(FAR struct net_driver_s *dev) goto drop; } -#ifdef CONFIG_NET_NAT +#ifdef CONFIG_NET_NAT44 /* Try NAT inbound, rule matching will be performed in NAT module. */ - if (ipv4_nat_inbound(dev, ipv4) < 0) - { - nwarn("WARNING: Performing NAT inbound failed!\n"); - goto drop; - } + ipv4_nat_inbound(dev, ipv4); #endif /* Get the destination IP address in a friendlier form */ diff --git a/net/devif/ipv6_input.c b/net/devif/ipv6_input.c index 3be7d875a9465..b6e133c78d161 100644 --- a/net/devif/ipv6_input.c +++ b/net/devif/ipv6_input.c @@ -47,6 +47,7 @@ #include "pkt/pkt.h" #include "icmpv6/icmpv6.h" +#include "nat/nat.h" #include "netdev/netdev.h" #include "ipforward/ipforward.h" #include "inet/inet.h" @@ -296,6 +297,12 @@ static int ipv6_in(FAR struct net_driver_s *dev) nxthdr = exthdr->nxthdr; } +#ifdef CONFIG_NET_NAT66 + /* Try NAT inbound, rule matching will be performed in NAT module. */ + + ipv6_nat_inbound(dev, ipv6); +#endif + #ifdef CONFIG_NET_BROADCAST /* Check for a multicast packet, which may be destined to us (even if * there is no IP address yet assigned to the device). We only expect diff --git a/net/icmp/icmp_conn.c b/net/icmp/icmp_conn.c index 0cda4685b2b9b..efb4b83a15f45 100644 --- a/net/icmp/icmp_conn.c +++ b/net/icmp/icmp_conn.c @@ -114,7 +114,7 @@ FAR struct icmp_conn_s *icmp_alloc(void) { #if CONFIG_NET_ICMP_MAX_CONNS > 0 if (dq_count(&g_active_icmp_connections) + - CONFIG_NET_ICMP_ALLOC_CONNS >= CONFIG_NET_ICMP_MAX_CONNS) + CONFIG_NET_ICMP_ALLOC_CONNS > CONFIG_NET_ICMP_MAX_CONNS) { nxmutex_unlock(&g_free_lock); return NULL; diff --git a/net/icmpv6/icmpv6_autoconfig.c b/net/icmpv6/icmpv6_autoconfig.c index ec8adecaad06d..804fc6d5748e2 100644 --- a/net/icmpv6/icmpv6_autoconfig.c +++ b/net/icmpv6/icmpv6_autoconfig.c @@ -340,17 +340,21 @@ int icmpv6_autoconfig(FAR struct net_driver_s *dev) * method must be employed. */ - ret = icmpv6_neighbor(dev, lladdr); - if (ret >= 0) + if (dev->d_lltype == NET_LL_ETHERNET || + dev->d_lltype == NET_LL_IEEE80211) { - /* Hmmm... someone else responded to our Neighbor Solicitation. We - * have no back-up plan in place. Just bail. - */ + ret = icmpv6_neighbor(dev, lladdr); + if (ret >= 0) + { + /* Hmmm... someone else responded to our Neighbor Solicitation. We + * have no back-up plan in place. Just bail. + */ - nerr("ERROR: IP conflict\n"); + nerr("ERROR: IP conflict\n"); - net_unlock(); - return -EEXIST; + net_unlock(); + return -EEXIST; + } } #endif @@ -363,6 +367,7 @@ int icmpv6_autoconfig(FAR struct net_driver_s *dev) ret = netdev_ipv6_add(dev, lladdr, net_ipv6_mask2pref(g_ipv6_llnetmask)); if (ret < 0) { + net_unlock(); return ret; } @@ -387,6 +392,12 @@ int icmpv6_autoconfig(FAR struct net_driver_s *dev) ret = icmpv6_send_message(dev, false); if (ret < 0) { + /* Remove our wait structure from the list (we may no longer be + * at the head of the list). + */ + + icmpv6_rwait_cancel(¬ify); + nerr("ERROR: Failed send router solicitation: %d\n", ret); break; } diff --git a/net/icmpv6/icmpv6_conn.c b/net/icmpv6/icmpv6_conn.c index e6ee072a63232..5da518c9fb7f6 100644 --- a/net/icmpv6/icmpv6_conn.c +++ b/net/icmpv6/icmpv6_conn.c @@ -115,7 +115,7 @@ FAR struct icmpv6_conn_s *icmpv6_alloc(void) { #if CONFIG_NET_ICMPv6_MAX_CONNS > 0 if (dq_count(&g_active_icmpv6_connections) + - CONFIG_NET_ICMPv6_ALLOC_CONNS >= CONFIG_NET_ICMPv6_MAX_CONNS) + CONFIG_NET_ICMPv6_ALLOC_CONNS > CONFIG_NET_ICMPv6_MAX_CONNS) { nxmutex_unlock(&g_free_lock); return NULL; diff --git a/net/icmpv6/icmpv6_input.c b/net/icmpv6/icmpv6_input.c index 17d9137b54781..e2be6241acfb9 100644 --- a/net/icmpv6/icmpv6_input.c +++ b/net/icmpv6/icmpv6_input.c @@ -36,6 +36,7 @@ #include #include "devif/devif.h" +#include "netlink/netlink.h" #include "neighbor/neighbor.h" #include "utils/utils.h" #include "icmpv6/icmpv6.h" @@ -450,6 +451,8 @@ void icmpv6_input(FAR struct net_driver_s *dev, unsigned int iplen) { icmpv6_setaddresses(dev, ipv6->srcipaddr, prefixopt->prefix, prefixopt->preflen); + netlink_ipv6_prefix_notify(dev, RTM_NEWPREFIX, + prefixopt); } /* Notify any waiting threads */ diff --git a/net/icmpv6/icmpv6_neighbor.c b/net/icmpv6/icmpv6_neighbor.c index ac2c7b4a943ee..b6bd1df0db34b 100644 --- a/net/icmpv6/icmpv6_neighbor.c +++ b/net/icmpv6/icmpv6_neighbor.c @@ -216,6 +216,17 @@ int icmpv6_neighbor(FAR struct net_driver_s *dev, goto errout; } + /* Neighbor support is only built if the Ethernet link layer is supported. + * Continue and send the Solicitation only if this device uses the + * Ethernet link layer protocol. + */ + + if (dev->d_lltype != NET_LL_ETHERNET && + dev->d_lltype != NET_LL_IEEE80211) + { + return OK; + } + /* Check if the destination address is on the local network. */ if (NETDEV_V6ADDR_ONLINK(dev, ipaddr) || net_is_addr_linklocal(ipaddr)) diff --git a/net/icmpv6/icmpv6_rnotify.c b/net/icmpv6/icmpv6_rnotify.c index 4376c22e7991c..5d9e5d6f822b5 100644 --- a/net/icmpv6/icmpv6_rnotify.c +++ b/net/icmpv6/icmpv6_rnotify.c @@ -36,6 +36,7 @@ #include #include "netdev/netdev.h" +#include "netlink/netlink.h" #include "utils/utils.h" #include "icmpv6/icmpv6.h" @@ -136,6 +137,7 @@ void icmpv6_setaddresses(FAR struct net_driver_s *dev, NTOHS(addr[4]), NTOHS(addr[5]), NTOHS(addr[6]), NTOHS(addr[7])); netdev_ipv6_add(dev, addr, preflen); + netlink_device_notify_ipaddr(dev, RTM_NEWADDR, AF_INET6, addr, preflen); /* Finally, copy the router address */ diff --git a/net/ieee802154/ieee802154_conn.c b/net/ieee802154/ieee802154_conn.c index b7a5e25f8143e..14769c2d66a63 100644 --- a/net/ieee802154/ieee802154_conn.c +++ b/net/ieee802154/ieee802154_conn.c @@ -119,8 +119,7 @@ FAR struct ieee802154_conn_s *ieee802154_conn_alloc(void) { #if CONFIG_NET_IEEE802154_MAX_CONNS > 0 if (dq_count(&g_active_ieee802154_connections) + - CONFIG_NET_IEEE802154_ALLOC_CONNS - >= CONFIG_NET_IEEE802154_MAX_CONNS) + CONFIG_NET_IEEE802154_ALLOC_CONNS > CONFIG_NET_IEEE802154_MAX_CONNS) { net_unlock(); return NULL; diff --git a/net/inet/ipv4_setsockopt.c b/net/inet/ipv4_setsockopt.c index 741e6168cd2c0..d5b932994edc7 100644 --- a/net/inet/ipv4_setsockopt.c +++ b/net/inet/ipv4_setsockopt.c @@ -305,10 +305,6 @@ int ipv4_setsockopt(FAR struct socket *psock, int option, /* The following IPv4 socket options are defined, but not implemented */ - case IP_MULTICAST_LOOP: /* Set/read boolean that determines - * whether sent multicast packets - * should be looped back to local - * sockets. */ case IP_UNBLOCK_SOURCE: /* Unblock previously blocked multicast * source */ case IP_BLOCK_SOURCE: /* Stop receiving multicast data from @@ -327,8 +323,12 @@ int ipv4_setsockopt(FAR struct socket *psock, int option, nwarn("WARNING: Unimplemented IPv4 option: %d\n", option); ret = -ENOSYS; break; -#endif /* CONFIG_NET_IGMP */ + case IP_MULTICAST_LOOP: /* Set/read boolean that determines + * whether sent multicast packets + * should be looped back to local + * sockets. */ +#endif /* CONFIG_NET_IGMP */ case IP_PKTINFO: { FAR struct socket_conn_s *conn; diff --git a/net/inet/ipv6_setsockopt.c b/net/inet/ipv6_setsockopt.c index 2fc08de040427..f0a0e2e480101 100644 --- a/net/inet/ipv6_setsockopt.c +++ b/net/inet/ipv6_setsockopt.c @@ -137,13 +137,11 @@ int ipv6_setsockopt(FAR struct socket *psock, int option, ret = OK; break; } -#endif +#endif /* NET_UDP_HAVE_STACK */ +#endif /* CONFIG_NET_MLD */ /* The following IPv6 socket options are defined, but not implemented */ - case IPV6_MULTICAST_LOOP: /* Multicast packets are delivered back to - * the local application */ -#endif case IPV6_V6ONLY: /* Restrict AF_INET6 socket to IPv6 * communications only */ nwarn("WARNING: Unimplemented IPv6 option: %d\n", option); @@ -160,6 +158,10 @@ int ipv6_setsockopt(FAR struct socket *psock, int option, } break; +#ifdef CONFIG_NET_MLD + case IPV6_MULTICAST_LOOP: /* Multicast packets are delivered back to + * the local application */ +#endif case IPV6_RECVPKTINFO: case IPV6_RECVHOPLIMIT: { diff --git a/net/ipforward/ipv4_forward.c b/net/ipforward/ipv4_forward.c index ac608681ed528..8554546933600 100644 --- a/net/ipforward/ipv4_forward.c +++ b/net/ipforward/ipv4_forward.c @@ -286,13 +286,13 @@ static int ipv4_dev_forward(FAR struct net_driver_s *dev, goto errout_with_fwd; } -#ifdef CONFIG_NET_NAT +#ifdef CONFIG_NET_NAT44 /* Try NAT outbound, rule matching will be performed in NAT module. */ ret = ipv4_nat_outbound(fwd->f_dev, ipv4, NAT_MANIP_SRC); if (ret < 0) { - nwarn("WARNING: Performing NAT outbound failed, dropping!\n"); + nwarn("WARNING: Performing NAT44 outbound failed, dropping!\n"); goto errout_with_fwd; } #endif @@ -364,22 +364,13 @@ static int ipv4_forward_callback(FAR struct net_driver_s *fwddev, { /* Backup the forward IP packet */ - iob = iob_tryalloc(true); + iob = netdev_iob_clone(dev, true); if (iob == NULL) { - nerr("ERROR: iob alloc failed when forward broadcast\n"); + nerr("ERROR: IOB clone failed when forwarding broadcast.\n"); return -ENOMEM; } - iob_reserve(iob, CONFIG_NET_LL_GUARDSIZE); - ret = iob_clone_partial(dev->d_iob, dev->d_iob->io_pktlen, 0, - iob, 0, true, false); - if (ret < 0) - { - iob_free_chain(iob); - return ret; - } - /* Recover the pointer to the IPv4 header in the receiving device's * d_buf. */ @@ -541,13 +532,13 @@ int ipv4_forward(FAR struct net_driver_s *dev, FAR struct ipv4_hdr_s *ipv4) #ifdef CONFIG_NET_ICMP reply: -# ifdef CONFIG_NET_NAT +# ifdef CONFIG_NET_NAT44 /* Before we reply ICMP, call NAT outbound to try to translate destination * address & port back to original status. */ ipv4_nat_outbound(dev, ipv4, NAT_MANIP_DST); -# endif /* CONFIG_NET_NAT */ +# endif /* CONFIG_NET_NAT44 */ icmp_reply(dev, icmp_reply_type, icmp_reply_code); return OK; diff --git a/net/ipforward/ipv6_forward.c b/net/ipforward/ipv6_forward.c index 48698a2e7e423..5f39a0ad0803d 100644 --- a/net/ipforward/ipv6_forward.c +++ b/net/ipforward/ipv6_forward.c @@ -35,6 +35,7 @@ #include #include +#include "nat/nat.h" #include "netdev/netdev.h" #include "sixlowpan/sixlowpan.h" #include "devif/devif.h" @@ -423,6 +424,17 @@ static int ipv6_dev_forward(FAR struct net_driver_s *dev, goto errout_with_fwd; } +#ifdef CONFIG_NET_NAT66 + /* Try NAT outbound, rule matching will be performed in NAT module. */ + + ret = ipv6_nat_outbound(fwd->f_dev, ipv6, NAT_MANIP_SRC); + if (ret < 0) + { + nwarn("WARNING: Performing NAT66 outbound failed, dropping!\n"); + goto errout_with_fwd; + } +#endif + /* Then set up to forward the packet according to the protocol. */ ret = ipfwd_forward(fwd); @@ -491,22 +503,13 @@ static int ipv6_forward_callback(FAR struct net_driver_s *fwddev, { /* Backup the forward IP packet */ - iob = iob_tryalloc(true); + iob = netdev_iob_clone(dev, true); if (iob == NULL) { - nerr("ERROR: iob alloc failed when forward broadcast\n"); + nerr("ERROR: IOB clone failed when forwarding broadcast.\n"); return -ENOMEM; } - iob_reserve(iob, CONFIG_NET_LL_GUARDSIZE); - ret = iob_clone_partial(dev->d_iob, dev->d_iob->io_pktlen, 0, - iob, 0, true, false); - if (ret < 0) - { - iob_free_chain(iob); - return ret; - } - /* Recover the pointer to the IPv6 header in the receiving device's * d_buf. */ @@ -569,6 +572,11 @@ int ipv6_forward(FAR struct net_driver_s *dev, FAR struct ipv6_hdr_s *ipv6) { FAR struct net_driver_s *fwddev; int ret; +#ifdef CONFIG_NET_ICMPv6 + int icmpv6_reply_type; + int icmpv6_reply_code; + int icmpv6_reply_data; +#endif /* CONFIG_NET_ICMP */ /* Search for a device that can forward this packet. */ @@ -668,18 +676,22 @@ int ipv6_forward(FAR struct net_driver_s *dev, FAR struct ipv6_hdr_s *ipv6) switch (ret) { case -ENETUNREACH: - icmpv6_reply(dev, ICMPv6_DEST_UNREACHABLE, ICMPv6_ADDR_UNREACH, 0); - return OK; + icmpv6_reply_type = ICMPv6_DEST_UNREACHABLE; + icmpv6_reply_code = ICMPv6_ADDR_UNREACH; + icmpv6_reply_data = 0; + goto reply; case -EFBIG: - icmpv6_reply(dev, ICMPv6_PACKET_TOO_BIG, 0, - NETDEV_PKTSIZE(fwddev) - NET_LL_HDRLEN(fwddev)); - return OK; + icmpv6_reply_type = ICMPv6_PACKET_TOO_BIG; + icmpv6_reply_code = 0; + icmpv6_reply_data = NETDEV_PKTSIZE(fwddev) - NET_LL_HDRLEN(fwddev); + goto reply; case -EMULTIHOP: - icmpv6_reply(dev, ICMPv6_PACKET_TIME_EXCEEDED, ICMPV6_EXC_HOPLIMIT, - 0); - return OK; + icmpv6_reply_type = ICMPv6_PACKET_TIME_EXCEEDED; + icmpv6_reply_code = ICMPV6_EXC_HOPLIMIT; + icmpv6_reply_data = 0; + goto reply; default: break; /* We don't know how to reply, just go on (to drop). */ @@ -688,6 +700,20 @@ int ipv6_forward(FAR struct net_driver_s *dev, FAR struct ipv6_hdr_s *ipv6) dev->d_len = 0; return ret; + +#ifdef CONFIG_NET_ICMPv6 +reply: +# ifdef CONFIG_NET_NAT66 + /* Before we reply ICMPv6, call NAT outbound to try to translate + * destination address & port back to original status. + */ + + ipv6_nat_outbound(dev, ipv6, NAT_MANIP_DST); +# endif /* CONFIG_NET_NAT66 */ + + icmpv6_reply(dev, icmpv6_reply_type, icmpv6_reply_code, icmpv6_reply_data); + return OK; +#endif /* CONFIG_NET_ICMP */ } /**************************************************************************** diff --git a/net/ipfrag/CMakeLists.txt b/net/ipfrag/CMakeLists.txt index 4d2b258fa104b..4f614075bb1e8 100644 --- a/net/ipfrag/CMakeLists.txt +++ b/net/ipfrag/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# net/tcp/CMakeLists.txt +# net/ipfrag/CMakeLists.txt # # Licensed to the Apache Software Foundation (ASF) under one or more contributor # license agreements. See the NOTICE file distributed with this work for diff --git a/net/ipfrag/ipfrag.c b/net/ipfrag/ipfrag.c index 47f69942bd488..3253eef969ca2 100644 --- a/net/ipfrag/ipfrag.c +++ b/net/ipfrag/ipfrag.c @@ -171,7 +171,7 @@ ip_fragout_allocfragbuf(FAR struct iob_queue_s *fragq); static void ip_fragin_timerout_expiry(wdparm_t arg) { - assert(g_wkfragtimeout.worker == NULL); + ASSERT(g_wkfragtimeout.worker == NULL); work_queue(IPFRAGWORK, &g_wkfragtimeout, ip_fragin_timerwork, NULL, 0); } @@ -525,7 +525,7 @@ ip_fragout_allocfragbuf(FAR struct iob_queue_s *fragq) uint32_t ip_frag_remnode(FAR struct ip_fragsnode_s *node) { g_bufoccupy -= node->bufcnt; - assert(g_bufoccupy < CONFIG_IOB_NBUFFERS); + ASSERT(g_bufoccupy < CONFIG_IOB_NBUFFERS); sq_rem((FAR sq_entry_t *)node, &g_assemblyhead_ipid); sq_rem((FAR sq_entry_t *)&node->flinkat, &g_assemblyhead_time); @@ -799,7 +799,7 @@ int32_t ip_fragout_slice(FAR struct iob_s *iob, uint8_t domain, uint16_t mtu, return 0; } - assert(iob->io_pktlen > mtu); + ASSERT(iob->io_pktlen > mtu); #ifdef CONFIG_NET_IPv4 if (domain == PF_INET) diff --git a/net/ipfrag/ipv4_frag.c b/net/ipfrag/ipv4_frag.c index 0d467eb60ddaa..c4cd50651419d 100644 --- a/net/ipfrag/ipv4_frag.c +++ b/net/ipfrag/ipv4_frag.c @@ -378,7 +378,7 @@ int32_t ipv4_fragout(FAR struct net_driver_s *dev, uint16_t mtu) */ nfrags = ip_fragout_slice(dev->d_iob, PF_INET, mtu, hdrlen, &fragq); - assert(nfrags > 1); + ASSERT(nfrags > 1); netdev_iob_clear(dev); /* Fill the L3 header into the reserved space */ diff --git a/net/ipfrag/ipv6_frag.c b/net/ipfrag/ipv6_frag.c index ab19cab73b0aa..a46dcd86a2de5 100644 --- a/net/ipfrag/ipv6_frag.c +++ b/net/ipfrag/ipv6_frag.c @@ -588,7 +588,7 @@ int32_t ipv6_fragout(FAR struct net_driver_s *dev, uint16_t mtu) */ nfrags = ip_fragout_slice(dev->d_iob, PF_INET6, mtu, unfraglen, &fragq); - assert(nfrags > 1); + ASSERT(nfrags > 1); netdev_iob_clear(dev); ipid = ++g_ipv6id; diff --git a/net/local/local.h b/net/local/local.h index ad74deb212100..1733d1ffcbb74 100644 --- a/net/local/local.h +++ b/net/local/local.h @@ -88,7 +88,7 @@ enum local_state_s * connection structures: * * 1. Server. A SOCK_STREAM that only listens for and accepts - * connections from server. + * connections from client. * 2. Client. A SOCK_STREAM peer that connects via the server. * 3. Peer. A connected SOCK_STREAM that sends() and recvs() packets. * May either be the client that connect with the server of the @@ -98,8 +98,7 @@ enum local_state_s * And * * 4. Connectionless. Like a peer but using a connectionless datagram - * style of communication. SOCK_DRAM support has not yet been - * implemented. + * style of communication. */ struct devif_callback_s; /* Forward reference */ @@ -143,7 +142,6 @@ struct local_conn_s /* SOCK_STREAM fields common to both client and server */ sem_t lc_waitsem; /* Use to wait for a connection to be accepted */ - FAR struct socket *lc_psock; /* A reference to the socket structure */ /* The following is a list if poll structures of threads waiting for * socket events. diff --git a/net/local/local_accept.c b/net/local/local_accept.c index 387996a324950..b802cf5754ffc 100644 --- a/net/local/local_accept.c +++ b/net/local/local_accept.c @@ -23,7 +23,6 @@ ****************************************************************************/ #include -#if defined(CONFIG_NET) && defined(CONFIG_NET_LOCAL_STREAM) #include #include @@ -99,7 +98,7 @@ int local_accept(FAR struct socket *psock, FAR struct sockaddr *addr, FAR socklen_t *addrlen, FAR struct socket *newsock, int flags) { - FAR struct local_conn_s *server; + FAR struct local_conn_s *server = psock->s_conn; FAR struct local_conn_s *conn; FAR dq_entry_t *waiter; bool nonblock = !!(flags & SOCK_NONBLOCK); @@ -116,12 +115,6 @@ int local_accept(FAR struct socket *psock, FAR struct sockaddr *addr, return -EOPNOTSUPP; } - /* Verify that a valid memory block has been provided to receive the - * address - */ - - server = psock->s_conn; - if (server->lc_proto != SOCK_STREAM || server->lc_state != LOCAL_STATE_LISTENING) { @@ -137,7 +130,6 @@ int local_accept(FAR struct socket *psock, FAR struct sockaddr *addr, */ waiter = dq_remfirst(&server->u.server.lc_waiters); - if (waiter) { conn = container_of(waiter, struct local_conn_s, @@ -150,8 +142,6 @@ int local_accept(FAR struct socket *psock, FAR struct sockaddr *addr, /* Setup the accpet socket structure */ - conn->lc_psock = newsock; - newsock->s_domain = psock->s_domain; newsock->s_type = SOCK_STREAM; newsock->s_sockif = psock->s_sockif; @@ -194,5 +184,3 @@ int local_accept(FAR struct socket *psock, FAR struct sockaddr *addr, } } } - -#endif /* CONFIG_NET && CONFIG_NET_LOCAL_STREAM */ diff --git a/net/local/local_bind.c b/net/local/local_bind.c index a7678782692cb..a218597ca3ddd 100644 --- a/net/local/local_bind.c +++ b/net/local/local_bind.c @@ -23,7 +23,6 @@ ****************************************************************************/ #include -#if defined(CONFIG_NET) && defined(CONFIG_NET_LOCAL) #include #include @@ -38,7 +37,7 @@ ****************************************************************************/ /**************************************************************************** - * Name: local_bind + * Name: psock_local_bind * * Description: * This function implements the low-level parts of the standard local @@ -49,7 +48,7 @@ int psock_local_bind(FAR struct socket *psock, FAR const struct sockaddr *addr, socklen_t addrlen) { - FAR struct local_conn_s *conn; + FAR struct local_conn_s *conn = psock->s_conn; FAR const struct sockaddr_un *unaddr = (FAR const struct sockaddr_un *)addr; @@ -60,8 +59,6 @@ int psock_local_bind(FAR struct socket *psock, return -EINVAL; } - conn = psock->s_conn; - /* Save the address family */ conn->lc_proto = psock->s_type; @@ -95,5 +92,3 @@ int psock_local_bind(FAR struct socket *psock, conn->lc_state = LOCAL_STATE_BOUND; return OK; } - -#endif /* CONFIG_NET && CONFIG_NET_LOCAL */ diff --git a/net/local/local_conn.c b/net/local/local_conn.c index d8797c53fad00..55986393c5a1c 100644 --- a/net/local/local_conn.c +++ b/net/local/local_conn.c @@ -23,7 +23,6 @@ ****************************************************************************/ #include -#if defined(CONFIG_NET) && defined(CONFIG_NET_LOCAL) #include #include @@ -118,9 +117,10 @@ FAR struct local_conn_s *local_alloc(void) * necessary to zerio-ize any structure elements. */ + conn->lc_crefs = 1; + #ifdef CONFIG_NET_LOCAL_STREAM nxsem_init(&conn->lc_waitsem, 0, 0); - #endif /* This semaphore is used for sending safely in multithread. @@ -174,10 +174,6 @@ int local_alloc_accept(FAR struct local_conn_s *server, return -ENOMEM; } - /* Initialize the new connection structure */ - - local_addref(conn); - conn->lc_proto = SOCK_STREAM; conn->lc_type = LOCAL_TYPE_PATHNAME; conn->lc_state = LOCAL_STATE_CONNECTED; @@ -350,5 +346,3 @@ void local_subref(FAR struct local_conn_s *conn) local_release(conn); } } - -#endif /* CONFIG_NET && CONFIG_NET_LOCAL */ diff --git a/net/local/local_connect.c b/net/local/local_connect.c index 538bed5d0bcc9..6ae84213d74bb 100644 --- a/net/local/local_connect.c +++ b/net/local/local_connect.c @@ -40,8 +40,6 @@ #include "socket/socket.h" #include "local/local.h" -#ifdef CONFIG_NET_LOCAL_STREAM - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -94,7 +92,6 @@ static int inline local_stream_connect(FAR struct local_conn_s *client, { nerr("ERROR: Failed to create FIFOs for %s: %d\n", client->lc_path, ret); - return ret; } @@ -107,7 +104,6 @@ static int inline local_stream_connect(FAR struct local_conn_s *client, { nerr("ERROR: Failed to open write-only FIFOs for %s: %d\n", client->lc_path, ret); - goto errout_with_fifos; } @@ -118,7 +114,6 @@ static int inline local_stream_connect(FAR struct local_conn_s *client, { nerr("ERROR: Failed to alloc accept conn %s: %d\n", client->lc_path, ret); - goto errout_with_outfd; } @@ -129,9 +124,8 @@ static int inline local_stream_connect(FAR struct local_conn_s *client, ret = local_open_client_rx(client, nonblock); if (ret < 0) { - nerr("ERROR: Failed to open write-only FIFOs for %s: %d\n", + nerr("ERROR: Failed to open read-only FIFOs for %s: %d\n", client->lc_path, ret); - goto errout_with_conn; } @@ -220,15 +214,13 @@ int32_t local_generate_instance_id(void) int psock_local_connect(FAR struct socket *psock, FAR const struct sockaddr *addr) { - FAR struct local_conn_s *client; + FAR struct local_conn_s *client = psock->s_conn; FAR struct sockaddr_un *unaddr = (FAR struct sockaddr_un *)addr; FAR const char *unpath = unaddr->sun_path; FAR struct local_conn_s *conn = NULL; uint8_t type = LOCAL_TYPE_PATHNAME; struct stat buf; - int ret; - - client = psock->s_conn; + int ret = OK; if (client->lc_state == LOCAL_STATE_ACCEPT || client->lc_state == LOCAL_STATE_CONNECTED) @@ -247,9 +239,9 @@ int psock_local_connect(FAR struct socket *psock, net_lock(); while ((conn = local_nextconn(conn)) != NULL) { - /* Slef found, continue */ + /* Self found, continue */ - if (conn == psock->s_conn) + if (conn == client) { continue; } @@ -272,8 +264,6 @@ int psock_local_connect(FAR struct socket *psock, conn->lc_type == type && conn->lc_proto == SOCK_STREAM && strncmp(conn->lc_path, unpath, UNIX_PATH_MAX - 1) == 0) { - ret = OK; - /* Bind the address and protocol */ client->lc_type = conn->lc_type; @@ -287,11 +277,8 @@ int psock_local_connect(FAR struct socket *psock, /* We have to do more for the SOCK_STREAM family */ - if (conn->lc_proto == SOCK_STREAM) - { - ret = local_stream_connect(client, conn, + ret = local_stream_connect(client, conn, _SS_ISNONBLOCK(client->lc_conn.s_flags)); - } net_unlock(); return ret; @@ -310,5 +297,3 @@ int psock_local_connect(FAR struct socket *psock, ret = nx_stat(unpath, &buf, 1); return ret < 0 ? ret : -ECONNREFUSED; } - -#endif /* CONFIG_NET_LOCAL_STREAM */ diff --git a/net/local/local_fifo.c b/net/local/local_fifo.c index 4f555c57fd2a6..48776cf647a0f 100644 --- a/net/local/local_fifo.c +++ b/net/local/local_fifo.c @@ -23,7 +23,6 @@ ****************************************************************************/ #include -#if defined(CONFIG_NET) && defined(CONFIG_NET_LOCAL) #include #include @@ -156,7 +155,7 @@ static bool local_fifo_exists(FAR const char *path) * In that case, we will return false and mkfifo() will fail. */ - return (bool)S_ISFIFO(buf.st_mode); + return S_ISFIFO(buf.st_mode); } /**************************************************************************** @@ -294,7 +293,8 @@ static int local_tx_open(FAR struct local_conn_s *conn, FAR const char *path, if (nonblock == false) { - ret = file_fcntl(&conn->lc_outfile, F_SETFL, O_WRONLY); + ret = nonblock; + ret = file_ioctl(&conn->lc_outfile, FIONBIO, &ret); if (ret < 0) { return ret; @@ -477,12 +477,12 @@ int local_release_fifos(FAR struct local_conn_s *conn) int ret1; int ret2; - /* Destroy the client-to-server FIFO if it exists. */ + /* Destroy the server-to-client FIFO if it exists. */ local_sc_name(conn, path); ret1 = local_release_fifo(path); - /* Destroy the server-to-client FIFO if it exists. */ + /* Destroy the client-to-server FIFO if it exists. */ local_cs_name(conn, path); ret2 = local_release_fifo(path); @@ -609,7 +609,7 @@ int local_open_server_rx(FAR struct local_conn_s *server, bool nonblock) local_cs_name(server, path); - /* Then open the file for write-only access */ + /* Then open the file for read-only access */ ret = local_rx_open(server, path, nonblock); if (ret == OK) @@ -626,7 +626,7 @@ int local_open_server_rx(FAR struct local_conn_s *server, bool nonblock) * Name: local_open_server_tx * * Description: - * Only the server-side of the server-to-client FIFO. + * Open the server-side of the server-to-client FIFO. * ****************************************************************************/ @@ -639,7 +639,7 @@ int local_open_server_tx(FAR struct local_conn_s *server, bool nonblock) local_sc_name(server, path); - /* Then open the file for read-only access */ + /* Then open the file for write-only access */ ret = local_tx_open(server, path, nonblock); if (ret == OK) @@ -656,7 +656,7 @@ int local_open_server_tx(FAR struct local_conn_s *server, bool nonblock) * Name: local_open_receiver * * Description: - * Only the receiving side of the half duplex FIFO. + * Open the receiving side of the half duplex FIFO. * ****************************************************************************/ @@ -678,16 +678,15 @@ int local_open_receiver(FAR struct local_conn_s *conn, bool nonblock) /* Policy: Free FIFO resources when the buffer is empty. */ ret = local_set_policy(&conn->lc_infile, 1); - if (ret == 0) { - /* Set POLLOUT threshold bigger than preamble len. + /* Set POLLIN threshold bigger than preamble len. * This is to avoid non-blocking read failed with -EAGAIN when * only preamble len is sent and read by reader. */ - ret = local_set_polloutthreshold(&conn->lc_infile, - sizeof(uint16_t)); + ret = local_set_pollinthreshold(&conn->lc_infile, + sizeof(uint16_t)); } } @@ -699,7 +698,7 @@ int local_open_receiver(FAR struct local_conn_s *conn, bool nonblock) * Name: local_open_sender * * Description: - * Only the sending side of the half duplex FIFO. + * Open the sending side of the half duplex FIFO. * ****************************************************************************/ @@ -714,7 +713,7 @@ int local_open_sender(FAR struct local_conn_s *conn, FAR const char *path, local_hd_name(path, fullpath); - /* Then open the file for read-only access */ + /* Then open the file for write-only access */ ret = local_tx_open(conn, fullpath, nonblock); if (ret == OK) @@ -724,13 +723,13 @@ int local_open_sender(FAR struct local_conn_s *conn, FAR const char *path, ret = local_set_policy(&conn->lc_outfile, 1); if (ret == 0) { - /* Set POLLIN threshold bigger than preamble len. - * This is to avoid non-blocking read failed with -EAGAIN when + /* Set POLLOUT threshold bigger than preamble len. + * This is to avoid non-blocking write failed with -EAGAIN when * only preamble len is sent and read by reader. */ - ret = local_set_pollinthreshold(&conn->lc_outfile, - sizeof(uint16_t)); + ret = local_set_polloutthreshold(&conn->lc_outfile, + sizeof(uint16_t)); } } @@ -763,5 +762,3 @@ int local_set_nonblocking(FAR struct local_conn_s *conn) return ret; } - -#endif /* CONFIG_NET && CONFIG_NET_LOCAL */ diff --git a/net/local/local_listen.c b/net/local/local_listen.c index 08125afba1063..c9c8a4ff80869 100644 --- a/net/local/local_listen.c +++ b/net/local/local_listen.c @@ -23,7 +23,6 @@ ****************************************************************************/ #include -#if defined(CONFIG_NET) && defined(CONFIG_NET_LOCAL_STREAM) #include #include @@ -66,7 +65,7 @@ int local_listen(FAR struct socket *psock, int backlog) { - FAR struct local_conn_s *server; + FAR struct local_conn_s *server = psock->s_conn; /* Verify that the sockfd corresponds to a connected SOCK_STREAM in this * address family. @@ -81,8 +80,6 @@ int local_listen(FAR struct socket *psock, int backlog) net_lock(); - server = psock->s_conn; - /* Some sanity checks */ if (server->lc_proto != SOCK_STREAM || @@ -119,5 +116,3 @@ int local_listen(FAR struct socket *psock, int backlog) return OK; } - -#endif /* CONFIG_NET && CONFIG_NET_LOCAL_STREAM */ diff --git a/net/local/local_netpoll.c b/net/local/local_netpoll.c index 4c9b5206978c4..60974d49e8f64 100644 --- a/net/local/local_netpoll.c +++ b/net/local/local_netpoll.c @@ -46,8 +46,6 @@ static int local_event_pollsetup(FAR struct local_conn_s *conn, FAR struct pollfd *fds, bool setup) { - pollevent_t eventset; - int ret = OK; int i; if (setup) @@ -80,14 +78,11 @@ static int local_event_pollsetup(FAR struct local_conn_s *conn, return -EBUSY; } - eventset = 0; if (conn->lc_state == LOCAL_STATE_LISTENING && dq_peek(&conn->u.server.lc_waiters) != NULL) { - eventset |= POLLIN; + poll_notify(&fds, 1, POLLIN); } - - poll_notify(&fds, 1, eventset); } else { @@ -108,7 +103,7 @@ static int local_event_pollsetup(FAR struct local_conn_s *conn, nxmutex_unlock(&conn->lc_polllock); } - return ret; + return OK; } /**************************************************************************** @@ -121,7 +116,6 @@ static void local_inout_poll_cb(FAR struct pollfd *fds) poll_notify(&originfds, 1, fds->revents); } - #endif /**************************************************************************** @@ -160,14 +154,12 @@ void local_event_pollnotify(FAR struct local_conn_s *conn, int local_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds) { - FAR struct local_conn_s *conn; - int ret = -ENOSYS; - - conn = psock->s_conn; + FAR struct local_conn_s *conn = psock->s_conn; + int ret = OK; if (conn->lc_proto == SOCK_DGRAM) { - return ret; + return -ENOSYS; } #ifdef CONFIG_NET_LOCAL_STREAM @@ -280,7 +272,6 @@ int local_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds) break; default: - ret = OK; break; } #endif @@ -312,11 +303,9 @@ int local_pollsetup(FAR struct socket *psock, FAR struct pollfd *fds) int local_pollteardown(FAR struct socket *psock, FAR struct pollfd *fds) { - FAR struct local_conn_s *conn; + FAR struct local_conn_s *conn = psock->s_conn; int ret = OK; - conn = psock->s_conn; - if (conn->lc_proto == SOCK_DGRAM) { return -ENOSYS; diff --git a/net/local/local_recvmsg.c b/net/local/local_recvmsg.c index 3ad99e6ade2b5..a0632699b468e 100644 --- a/net/local/local_recvmsg.c +++ b/net/local/local_recvmsg.c @@ -23,7 +23,6 @@ ****************************************************************************/ #include -#if defined(CONFIG_NET) && defined(CONFIG_NET_LOCAL) #include #include @@ -237,13 +236,19 @@ psock_stream_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, /* Verify that this is a connected peer socket */ - if (conn->lc_state != LOCAL_STATE_CONNECTED || - conn->lc_infile.f_inode == NULL) + if (conn->lc_state != LOCAL_STATE_CONNECTED) { nerr("ERROR: not connected\n"); return -ENOTCONN; } + /* Check shutdown state */ + + if (conn->lc_infile.f_inode == NULL) + { + return 0; + } + /* If it is non-blocking mode, the data in fifo is 0 and * returns directly */ @@ -368,7 +373,6 @@ psock_dgram_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, if (conn->pktlen <= 0) { ret = local_sync(&conn->lc_infile); - if (ret < 0) { nerr("ERROR: Failed to get packet length: %d\n", ret); @@ -467,7 +471,7 @@ psock_dgram_recvfrom(FAR struct socket *psock, FAR void *buf, size_t len, return ret < 0 ? ret : readlen; } -#endif /* CONFIG_NET_LOCAL_STREAM */ +#endif /* CONFIG_NET_LOCAL_DGRAM */ /**************************************************************************** * Public Functions @@ -543,5 +547,3 @@ ssize_t local_recvmsg(FAR struct socket *psock, FAR struct msghdr *msg, return len; } - -#endif /* CONFIG_NET && CONFIG_NET_LOCAL */ diff --git a/net/local/local_recvutils.c b/net/local/local_recvutils.c index d3f8ae2b47d27..0fee12fae9cb5 100644 --- a/net/local/local_recvutils.c +++ b/net/local/local_recvutils.c @@ -36,8 +36,6 @@ #include "local/local.h" -#if defined(CONFIG_NET) && defined(CONFIG_NET_LOCAL) - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -190,8 +188,8 @@ int local_getaddr(FAR struct local_conn_s *conn, FAR struct sockaddr *addr, if (totlen > *addrlen) { - pathlen -= (totlen - *addrlen); - totlen = *addrlen; + pathlen -= (totlen - *addrlen); + totlen = *addrlen; } /* Copy the Unix domain address */ @@ -206,5 +204,3 @@ int local_getaddr(FAR struct local_conn_s *conn, FAR struct sockaddr *addr, *addrlen = totlen; return OK; } - -#endif /* CONFIG_NET && CONFIG_NET_LOCAL */ diff --git a/net/local/local_release.c b/net/local/local_release.c index 1d302f3ffef36..172e8d241bba2 100644 --- a/net/local/local_release.c +++ b/net/local/local_release.c @@ -23,7 +23,6 @@ ****************************************************************************/ #include -#if defined(CONFIG_NET) && defined(CONFIG_NET_LOCAL) #include #include @@ -78,7 +77,7 @@ int local_release(FAR struct local_conn_s *conn) /* Are there still clients waiting for a connection to the server? */ for (waiter = dq_peek(&conn->u.server.lc_waiters); - waiter; + waiter != NULL; waiter = dq_next(&accept->u.accept.lc_waiter)) { accept = container_of(waiter, struct local_conn_s, @@ -100,5 +99,3 @@ int local_release(FAR struct local_conn_s *conn) net_unlock(); return OK; } - -#endif /* CONFIG_NET && CONFIG_NET_LOCAL */ diff --git a/net/local/local_sendmsg.c b/net/local/local_sendmsg.c index 6068f5ceafd00..0ae6c5719fb7d 100644 --- a/net/local/local_sendmsg.c +++ b/net/local/local_sendmsg.c @@ -23,7 +23,6 @@ ****************************************************************************/ #include -#if defined(CONFIG_NET) && defined(CONFIG_NET_LOCAL) #include #include @@ -58,6 +57,18 @@ ****************************************************************************/ #ifdef CONFIG_NET_LOCAL_SCM +static void local_freectl(FAR struct local_conn_s *conn, int count) +{ + FAR struct local_conn_s *peer = conn->lc_peer; + + while (count-- > 0) + { + file_close(peer->lc_cfps[--peer->lc_cfpcount]); + kmm_free(peer->lc_cfps[peer->lc_cfpcount]); + peer->lc_cfps[peer->lc_cfpcount] = NULL; + } +} + static int local_sendctl(FAR struct local_conn_s *conn, FAR struct msghdr *msg) { @@ -71,7 +82,6 @@ static int local_sendctl(FAR struct local_conn_s *conn, int i = 0; net_lock(); - peer = conn->lc_peer; if (peer == NULL) { @@ -91,7 +101,7 @@ static int local_sendctl(FAR struct local_conn_s *conn, fds = (int *)CMSG_DATA(cmsg); count = (cmsg->cmsg_len - sizeof(struct cmsghdr)) / sizeof(int); - if (count + peer->lc_cfpcount > LOCAL_NCONTROLFDS) + if (count + peer->lc_cfpcount >= LOCAL_NCONTROLFDS) { ret = -EMFILE; goto fail; @@ -124,19 +134,11 @@ static int local_sendctl(FAR struct local_conn_s *conn, } net_unlock(); - return count; fail: - while (i-- > 0) - { - file_close(peer->lc_cfps[--peer->lc_cfpcount]); - kmm_free(peer->lc_cfps[peer->lc_cfpcount]); - peer->lc_cfps[peer->lc_cfpcount] = NULL; - } - + local_freectl(conn, i); net_unlock(); - return ret; } #endif /* CONFIG_NET_LOCAL_SCM */ @@ -175,27 +177,32 @@ static ssize_t local_send(FAR struct socket *psock, case SOCK_DGRAM: #endif /* CONFIG_NET_LOCAL_DGRAM */ { - FAR struct local_conn_s *peer; + FAR struct local_conn_s *conn = psock->s_conn; /* Local TCP packet send */ DEBUGASSERT(buf); - peer = psock->s_conn; /* Verify that this is a connected peer socket and that it has * opened the outgoing FIFO for write-only access. */ - if (peer->lc_state != LOCAL_STATE_CONNECTED || - peer->lc_outfile.f_inode == NULL) + if (conn->lc_state != LOCAL_STATE_CONNECTED) { nerr("ERROR: not connected\n"); return -ENOTCONN; } + /* Check shutdown state */ + + if (conn->lc_outfile.f_inode == NULL) + { + return -EPIPE; + } + /* Send the packet */ - ret = nxmutex_lock(&peer->lc_sendlock); + ret = nxmutex_lock(&conn->lc_sendlock); if (ret < 0) { /* May fail because the task was canceled. */ @@ -203,9 +210,9 @@ static ssize_t local_send(FAR struct socket *psock, return ret; } - ret = local_send_packet(&peer->lc_outfile, buf, len, + ret = local_send_packet(&conn->lc_outfile, buf, len, psock->s_type == SOCK_DGRAM); - nxmutex_unlock(&peer->lc_sendlock); + nxmutex_unlock(&conn->lc_sendlock); } break; default: @@ -417,19 +424,10 @@ ssize_t local_sendmsg(FAR struct socket *psock, FAR struct msghdr *msg, if (len < 0 && count > 0) { net_lock(); - - while (count-- > 0) - { - file_close(conn->lc_cfps[--conn->lc_cfpcount]); - kmm_free(conn->lc_cfps[conn->lc_cfpcount]); - conn->lc_cfps[conn->lc_cfpcount] = NULL; - } - + local_freectl(conn, count); net_unlock(); } #endif return len; } - -#endif /* CONFIG_NET && CONFIG_NET_LOCAL */ diff --git a/net/local/local_sendpacket.c b/net/local/local_sendpacket.c index a922a05520cc5..5933b174ee80c 100644 --- a/net/local/local_sendpacket.c +++ b/net/local/local_sendpacket.c @@ -36,8 +36,6 @@ #include "local/local.h" -#if defined(CONFIG_NET) && defined(CONFIG_NET_LOCAL) - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -164,5 +162,3 @@ int local_send_packet(FAR struct file *filep, FAR const struct iovec *buf, return len16 > 0 ? len16 : ret; } - -#endif /* CONFIG_NET && CONFIG_NET_LOCAL */ diff --git a/net/local/local_sockif.c b/net/local/local_sockif.c index e40be55151b03..66ff11fe807fc 100644 --- a/net/local/local_sockif.c +++ b/net/local/local_sockif.c @@ -41,8 +41,6 @@ #include "local/local.h" -#ifdef CONFIG_NET_LOCAL - /**************************************************************************** * Private Function Prototypes ****************************************************************************/ @@ -126,7 +124,6 @@ const struct sock_intf_s g_local_sockif = * ****************************************************************************/ -#if defined(CONFIG_NET_LOCAL_STREAM) || defined(CONFIG_NET_LOCAL_DGRAM) static int local_sockif_alloc(FAR struct socket *psock) { /* Allocate the local connection structure */ @@ -139,21 +136,11 @@ static int local_sockif_alloc(FAR struct socket *psock) return -ENOMEM; } - /* Set the reference count on the connection structure. This reference - * count will be incremented only if the socket is dup'ed - */ - - local_addref(conn); - /* Save the pre-allocated connection in the socket structure */ psock->s_conn = conn; -#if defined(CONFIG_NET_LOCAL_STREAM) - conn->lc_psock = psock; -#endif return OK; } -#endif /**************************************************************************** * Name: local_setup @@ -209,7 +196,6 @@ static int local_setup(FAR struct socket *psock) return local_sockif_alloc(psock); #endif /* CONFIG_NET_LOCAL_DGRAM */ -#if defined(CONFIG_NET_LOCAL_STREAM) || defined(CONFIG_NET_LOCAL_DGRAM) case SOCK_CTRL: if (psock->s_proto == 0 || psock->s_proto == IPPROTO_TCP || psock->s_proto == IPPROTO_UDP) @@ -220,7 +206,6 @@ static int local_setup(FAR struct socket *psock) } return -EPROTONOSUPPORT; -#endif default: return -EPROTONOSUPPORT; @@ -295,7 +280,7 @@ static int local_bind(FAR struct socket *psock, /* Verify that a valid address has been provided */ - if (addr->sa_family != AF_LOCAL || addrlen < sizeof(sa_family_t)) + if (addrlen < sizeof(sa_family_t) || addr->sa_family != AF_LOCAL) { nerr("ERROR: Invalid address length: %d < %zu\n", addrlen, sizeof(sa_family_t)); @@ -308,7 +293,6 @@ static int local_bind(FAR struct socket *psock, { /* Bind a local TCP/IP stream or datagram socket */ -#if defined(CONFIG_NET_LOCAL_STREAM) || defined(CONFIG_NET_LOCAL_DGRAM) #ifdef CONFIG_NET_LOCAL_STREAM case SOCK_STREAM: #endif @@ -322,7 +306,6 @@ static int local_bind(FAR struct socket *psock, ret = psock_local_bind(psock, addr, addrlen); } break; -#endif /* CONFIG_NET_LOCAL_STREAM || CONFIG_NET_LOCAL_DGRAM */ default: ret = -EBADF; @@ -365,7 +348,7 @@ static int local_getsockname(FAR struct socket *psock, FAR socklen_t *addrlen) { FAR struct sockaddr_un *unaddr = (FAR struct sockaddr_un *)addr; - FAR struct local_conn_s *conn; + FAR struct local_conn_s *conn = psock->s_conn; if (*addrlen < sizeof(sa_family_t)) { @@ -375,8 +358,6 @@ static int local_getsockname(FAR struct socket *psock, return OK; } - conn = psock->s_conn; - /* Save the address family */ unaddr->sun_family = AF_LOCAL; @@ -386,11 +367,11 @@ static int local_getsockname(FAR struct socket *psock, if (conn->lc_type == LOCAL_TYPE_UNNAMED) { - /* Zero-length sun_path... This is an abstract Unix domain socket */ + /* Zero-length sun_path... */ *addrlen = sizeof(sa_family_t); } - else /* conn->lc_type = LOCAL_TYPE_PATHNAME */ + else { /* Get the full length of the socket name (incl. null terminator) */ @@ -460,8 +441,8 @@ static int local_getpeername(FAR struct socket *psock, FAR socklen_t *addrlen) { FAR struct sockaddr_un *unaddr = (FAR struct sockaddr_un *)addr; - FAR struct local_conn_s *conn; - FAR struct local_conn_s *peer; + FAR struct local_conn_s *conn = psock->s_conn; + FAR struct local_conn_s *peer = conn->lc_peer; if (*addrlen < sizeof(sa_family_t)) { @@ -473,15 +454,11 @@ static int local_getpeername(FAR struct socket *psock, /* Verify that the socket has been connected */ - conn = psock->s_conn; - if (conn->lc_state != LOCAL_STATE_CONNECTED) { return -ENOTCONN; } - peer = conn->lc_peer; - /* Save the address family */ unaddr->sun_family = AF_LOCAL; @@ -491,11 +468,11 @@ static int local_getpeername(FAR struct socket *psock, if (peer->lc_type == LOCAL_TYPE_UNNAMED) { - /* Zero-length sun_path... This is an abstract Unix domain socket */ + /* Zero-length sun_path... */ *addrlen = sizeof(sa_family_t); } - else /* conn->lc_type = LOCAL_TYPE_PATHNAME */ + else { /* Get the full length of the socket name (incl. null terminator) */ @@ -518,13 +495,11 @@ static int local_getpeername(FAR struct socket *psock, if (peer->lc_type == LOCAL_TYPE_ABSTRACT) { unaddr->sun_path[0] = '\0'; - strlcpy(&unaddr->sun_path[1], - peer->lc_path, namelen - 1); + strlcpy(&unaddr->sun_path[1], peer->lc_path, namelen - 1); } else { - strlcpy(unaddr->sun_path, - peer->lc_path, namelen); + strlcpy(unaddr->sun_path, peer->lc_path, namelen); } *addrlen = sizeof(sa_family_t) + namelen; @@ -702,20 +677,16 @@ static int local_connect(FAR struct socket *psock, { /* Perform the datagram connection logic */ - /* #warning Missing logic */ - return -ENOSYS; } break; #endif /* CONFIG_NET_LOCAL_DGRAM */ -#if defined(CONFIG_NET_LOCAL_STREAM) || defined(CONFIG_NET_LOCAL_DGRAM) case SOCK_CTRL: { return -ENOSYS; } break; -#endif default: return -EBADF; @@ -781,7 +752,6 @@ static int local_close(FAR struct socket *psock) switch (psock->s_type) { -#if defined(CONFIG_NET_LOCAL_STREAM) || defined(CONFIG_NET_LOCAL_DGRAM) #ifdef CONFIG_NET_LOCAL_STREAM case SOCK_STREAM: #endif @@ -795,10 +765,8 @@ static int local_close(FAR struct socket *psock) */ local_subref(psock->s_conn); - return OK; } -#endif /* CONFIG_NET_LOCAL_STREAM || CONFIG_NET_LOCAL_DGRAM */ default: return -EBADF; @@ -820,11 +788,9 @@ static int local_close(FAR struct socket *psock) static int local_ioctl(FAR struct socket *psock, int cmd, unsigned long arg) { - FAR struct local_conn_s *conn; + FAR struct local_conn_s *conn = psock->s_conn; int ret = OK; - conn = psock->s_conn; - switch (cmd) { case FIONBIO: @@ -981,6 +947,10 @@ static int local_socketpair(FAR struct socket *psocks[2]) for (i = 0; i < 2; i++) { ret = local_set_pollthreshold(conns[i], sizeof(uint16_t)); + if (ret < 0) + { + goto errout; + } } } #endif @@ -1048,10 +1018,8 @@ static int local_shutdown(FAR struct socket *psock, int how) case SOCK_DGRAM: return -EOPNOTSUPP; #endif -#if defined(CONFIG_NET_LOCAL_STREAM) || defined(CONFIG_NET_LOCAL_DGRAM) case SOCK_CTRL: return -EOPNOTSUPP; -#endif default: return -EBADF; } @@ -1060,5 +1028,3 @@ static int local_shutdown(FAR struct socket *psock, int how) /**************************************************************************** * Public Functions ****************************************************************************/ - -#endif /* CONFIG_NET_LOCAL */ diff --git a/net/nat/CMakeLists.txt b/net/nat/CMakeLists.txt index 0e8dd83f5c868..9bb2c7443a488 100644 --- a/net/nat/CMakeLists.txt +++ b/net/nat/CMakeLists.txt @@ -22,8 +22,16 @@ if(CONFIG_NET_NAT) - if(CONFIG_NET_IPv4) - target_sources(net PRIVATE ipv4_nat.c ipv4_nat_entry.c) + list(APPEND SRCS nat.c) + + if(CONFIG_NET_NAT44) + list(APPEND SRCS ipv4_nat.c ipv4_nat_entry.c) + endif() + + if(CONFIG_NET_NAT66) + list(APPEND SRCS ipv6_nat.c ipv6_nat_entry.c) endif() + target_sources(net PRIVATE ${SRCS}) + endif() diff --git a/net/nat/Kconfig b/net/nat/Kconfig index 0adc09c53730f..dd95682772fe5 100644 --- a/net/nat/Kconfig +++ b/net/nat/Kconfig @@ -6,14 +6,64 @@ config NET_NAT bool "Network Address Translation (NAT)" default n - depends on NET_IPFORWARD && IOB_BUFSIZE >= 68 + depends on NET_IPFORWARD ---help--- Enable or disable Network Address Translation (NAT) function. Note: When forwarding IPv4 packet and applying NAT, NAT may be applied directly on a single I/O buffer containing L3 packet header, and NAT may need a continuous buffer of at least 68 Bytes - (IPv4 20B + ICMP 8B + IPv4 20B + TCP 20B). + (IPv4 20B + ICMP 8B + IPv4 20B + TCP 20B). And 108 Bytes for IPv6. + +config NET_NAT44 + bool "IPv4-to-IPv4 NAT (NAT44)" + default y + depends on NET_IPv4 && NET_NAT + depends on IOB_BUFSIZE >= 68 + +choice + prompt "NAT44 Type" + default NET_NAT44_FULL_CONE + depends on NET_NAT44 + +config NET_NAT44_FULL_CONE + bool "Full Cone NAT" + ---help--- + Full Cone NAT is easier to traverse than Symmetric NAT, and uses + less resources than Symmetric NAT. + +config NET_NAT44_SYMMETRIC + bool "Symmetric NAT" + ---help--- + Symmetric NAT will be safer than Full Cone NAT, be more difficult + to traverse, and has more entries which may lead to heavier load. + +endchoice + +config NET_NAT66 + bool "IPv6-to-IPv6 NAT (NAT66)" + default y + depends on NET_IPv6 && NET_NAT + depends on IOB_BUFSIZE >= 108 + +choice + prompt "NAT66 Type" + default NET_NAT66_FULL_CONE + depends on NET_NAT66 + +config NET_NAT66_FULL_CONE + bool "Full Cone NAT" + ---help--- + Full Cone NAT is easier to traverse than Symmetric NAT, and uses + less resources than Symmetric NAT. + +config NET_NAT66_SYMMETRIC + bool "Symmetric NAT" + ---help--- + Symmetric NAT will be safer than Full Cone NAT, be more difficult + to traverse, and has more entries which may lead to heavier load. + +endchoice config NET_NAT_HASH_BITS int "The bits of NAT entry hashtable" @@ -54,6 +104,13 @@ config NET_NAT_ICMP_EXPIRE_SEC Note: The default value 60 is suggested by RFC5508, Section 3.2, Page 8. +config NET_NAT_ICMPv6_EXPIRE_SEC + int "ICMPv6 NAT entry expiration seconds" + default 60 + depends on NET_NAT + ---help--- + The expiration time for idle ICMPv6 entry in NAT. + config NET_NAT_ENTRY_RECLAIM_SEC int "The time to auto reclaim all expired entries" default 3600 diff --git a/net/nat/Make.defs b/net/nat/Make.defs index 43d185837e39d..b5316ca4c953d 100644 --- a/net/nat/Make.defs +++ b/net/nat/Make.defs @@ -22,10 +22,16 @@ ifeq ($(CONFIG_NET_NAT),y) -ifeq ($(CONFIG_NET_IPv4),y) +NET_CSRCS += nat.c + +ifeq ($(CONFIG_NET_NAT44),y) NET_CSRCS += ipv4_nat.c ipv4_nat_entry.c endif +ifeq ($(CONFIG_NET_NAT66),y) +NET_CSRCS += ipv6_nat.c ipv6_nat_entry.c +endif + # Include NAT build support DEPPATH += --dep-path nat diff --git a/net/nat/ipv4_nat.c b/net/nat/ipv4_nat.c index e38b0cd108983..60098a5a00b1d 100644 --- a/net/nat/ipv4_nat.c +++ b/net/nat/ipv4_nat.c @@ -26,7 +26,6 @@ #include #include -#include #include #include #include @@ -38,26 +37,12 @@ #include "nat/nat.h" #include "utils/utils.h" -#if defined(CONFIG_NET_NAT) && defined(CONFIG_NET_IPv4) +#ifdef CONFIG_NET_NAT44 /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Adjust checksums in headers. */ - -#define chksum_adjust(chksum,optr,nptr,len) \ - net_chksum_adjust((FAR uint16_t *)(chksum), (FAR uint16_t *)(optr), len, \ - (FAR uint16_t *)(nptr), len) - -/* Getting IP & Port to manipulate from L3/L4 header. */ - -#define MANIP_IPADDR(iphdr,manip_type) \ - ((manip_type) == NAT_MANIP_SRC ? (iphdr)->srcipaddr : (iphdr)->destipaddr) - -#define MANIP_PORT(l4hdr,manip_type) \ - ((manip_type) == NAT_MANIP_SRC ? &(l4hdr)->srcport : &(l4hdr)->destport) - /* Getting L4 header from IPv4 header. */ #define L4_HDR(ipv4) \ @@ -75,11 +60,11 @@ * Private Function Prototypes ****************************************************************************/ -static FAR struct ipv4_nat_entry * +static FAR ipv4_nat_entry_t * ipv4_nat_inbound_internal(FAR struct ipv4_hdr_s *ipv4, enum nat_manip_type_e manip_type); -static FAR struct ipv4_nat_entry * +static FAR ipv4_nat_entry_t * ipv4_nat_outbound_internal(FAR struct net_driver_s *dev, FAR struct ipv4_hdr_s *ipv4, enum nat_manip_type_e manip_type); @@ -96,7 +81,7 @@ ipv4_nat_outbound_internal(FAR struct net_driver_s *dev, * ****************************************************************************/ -static inline uint16_t ipv4_nat_l4_hdrlen(uint8_t proto) +static inline uint8_t ipv4_nat_l4_hdrlen(uint8_t proto) { switch (proto) { @@ -113,7 +98,7 @@ static inline uint16_t ipv4_nat_l4_hdrlen(uint8_t proto) return ICMP_HDRLEN; #endif default: - DEBUGASSERT(false); + nwarn("WARNING: Unsupported protocol %u inside ICMP\n", proto); } return 0; @@ -132,23 +117,21 @@ static inline uint16_t ipv4_nat_l4_hdrlen(uint8_t proto) * Input Parameters: * ipv4 - Points to the IPv4 header to adjust. * l4chksum - Points to the L4 checksum to adjust, NULL for not adjust. + * old_ip - The IP to be set. * new_ip - The IP to set into header. - * manip_type - Whether manipulate source ip or destination ip. * ****************************************************************************/ static void ipv4_nat_ip_adjust(FAR struct ipv4_hdr_s *ipv4, - FAR uint16_t *l4chksum, in_addr_t new_ip, - enum nat_manip_type_e manip_type) + FAR uint16_t *l4chksum, FAR uint16_t *old_ip, + in_addr_t new_ip) { - FAR uint16_t *old_ip = MANIP_IPADDR(ipv4, manip_type); - if (l4chksum != NULL) { - chksum_adjust(l4chksum, old_ip, &new_ip, sizeof(new_ip)); + nat_chksum_adjust(l4chksum, old_ip, &new_ip, sizeof(new_ip)); } - chksum_adjust(&ipv4->ipchksum, old_ip, &new_ip, sizeof(new_ip)); + nat_chksum_adjust(&ipv4->ipchksum, old_ip, &new_ip, sizeof(new_ip)); net_ipv4addr_hdrcopy(old_ip, &new_ip); } @@ -170,7 +153,7 @@ static void ipv4_nat_port_adjust(FAR uint16_t *l4chksum, { if (l4chksum != NULL) { - chksum_adjust(l4chksum, old_port, &new_port, sizeof(new_port)); + nat_chksum_adjust(l4chksum, old_port, &new_port, sizeof(new_port)); } *old_port = new_port; @@ -197,17 +180,21 @@ static void ipv4_nat_port_adjust(FAR uint16_t *l4chksum, ****************************************************************************/ #ifdef CONFIG_NET_TCP -static FAR struct ipv4_nat_entry * +static FAR ipv4_nat_entry_t * ipv4_nat_inbound_tcp(FAR struct ipv4_hdr_s *ipv4, enum nat_manip_type_e manip_type) { - FAR struct tcp_hdr_s *tcp = L4_HDR(ipv4); - FAR uint16_t *external_ip = MANIP_IPADDR(ipv4, manip_type); - FAR uint16_t *external_port = MANIP_PORT(tcp, manip_type); - FAR struct ipv4_nat_entry *entry = + FAR struct tcp_hdr_s *tcp = L4_HDR(ipv4); + FAR uint16_t *external_ip = MANIP_IPADDR(ipv4, manip_type); + FAR uint16_t *external_port = MANIP_PORT(tcp, manip_type); + FAR uint16_t *peer_ip = PEER_IPADDR(ipv4, manip_type); + FAR uint16_t *peer_port = PEER_PORT(tcp, manip_type); + FAR ipv4_nat_entry_t *entry = ipv4_nat_inbound_entry_find(IP_PROTO_TCP, net_ip4addr_conv32(external_ip), - *external_port, true); + *external_port, + net_ip4addr_conv32(peer_ip), + *peer_port, true); if (!entry) { return NULL; @@ -219,7 +206,7 @@ ipv4_nat_inbound_tcp(FAR struct ipv4_hdr_s *ipv4, */ ipv4_nat_port_adjust(&tcp->tcpchksum, external_port, entry->local_port); - ipv4_nat_ip_adjust(ipv4, &tcp->tcpchksum, entry->local_ip, manip_type); + ipv4_nat_ip_adjust(ipv4, &tcp->tcpchksum, external_ip, entry->local_ip); return entry; } @@ -246,18 +233,22 @@ ipv4_nat_inbound_tcp(FAR struct ipv4_hdr_s *ipv4, ****************************************************************************/ #ifdef CONFIG_NET_UDP -static FAR struct ipv4_nat_entry * +static FAR ipv4_nat_entry_t * ipv4_nat_inbound_udp(FAR struct ipv4_hdr_s *ipv4, enum nat_manip_type_e manip_type) { - FAR struct udp_hdr_s *udp = L4_HDR(ipv4); - FAR uint16_t *external_ip = MANIP_IPADDR(ipv4, manip_type); - FAR uint16_t *external_port = MANIP_PORT(udp, manip_type); - FAR uint16_t *udpchksum; - FAR struct ipv4_nat_entry *entry = + FAR struct udp_hdr_s *udp = L4_HDR(ipv4); + FAR uint16_t *external_ip = MANIP_IPADDR(ipv4, manip_type); + FAR uint16_t *external_port = MANIP_PORT(udp, manip_type); + FAR uint16_t *peer_ip = PEER_IPADDR(ipv4, manip_type); + FAR uint16_t *peer_port = PEER_PORT(udp, manip_type); + FAR uint16_t *udpchksum; + FAR ipv4_nat_entry_t *entry = ipv4_nat_inbound_entry_find(IP_PROTO_UDP, net_ip4addr_conv32(external_ip), - *external_port, true); + *external_port, + net_ip4addr_conv32(peer_ip), + *peer_port, true); if (!entry) { @@ -269,7 +260,7 @@ ipv4_nat_inbound_udp(FAR struct ipv4_hdr_s *ipv4, udpchksum = udp->udpchksum != 0 ? &udp->udpchksum : NULL; ipv4_nat_port_adjust(udpchksum, external_port, entry->local_port); - ipv4_nat_ip_adjust(ipv4, udpchksum, entry->local_ip, manip_type); + ipv4_nat_ip_adjust(ipv4, udpchksum, external_ip, entry->local_ip); return entry; } @@ -296,21 +287,23 @@ ipv4_nat_inbound_udp(FAR struct ipv4_hdr_s *ipv4, ****************************************************************************/ #ifdef CONFIG_NET_ICMP -static FAR struct ipv4_nat_entry * +static FAR ipv4_nat_entry_t * ipv4_nat_inbound_icmp(FAR struct ipv4_hdr_s *ipv4, enum nat_manip_type_e manip_type) { - FAR struct icmp_hdr_s *icmp = L4_HDR(ipv4); - FAR uint16_t *external_ip; - FAR struct ipv4_nat_entry *entry; + FAR struct icmp_hdr_s *icmp = L4_HDR(ipv4); + FAR uint16_t *external_ip = MANIP_IPADDR(ipv4, manip_type); + FAR uint16_t *peer_ip = PEER_IPADDR(ipv4, manip_type); + FAR ipv4_nat_entry_t *entry; switch (icmp->type) { case ICMP_ECHO_REQUEST: case ICMP_ECHO_REPLY: - external_ip = MANIP_IPADDR(ipv4, manip_type); entry = ipv4_nat_inbound_entry_find(IP_PROTO_ICMP, net_ip4addr_conv32(external_ip), + icmp->id, + net_ip4addr_conv32(peer_ip), icmp->id, true); if (!entry) { @@ -319,7 +312,7 @@ ipv4_nat_inbound_icmp(FAR struct ipv4_hdr_s *ipv4, ipv4_nat_port_adjust(&icmp->icmpchksum, &icmp->id, entry->local_port); - ipv4_nat_ip_adjust(ipv4, NULL, entry->local_ip, manip_type); + ipv4_nat_ip_adjust(ipv4, NULL, external_ip, entry->local_ip); return entry; case ICMP_DEST_UNREACHABLE: @@ -336,13 +329,24 @@ ipv4_nat_inbound_icmp(FAR struct ipv4_hdr_s *ipv4, FAR struct ipv4_hdr_s *inner = (FAR struct ipv4_hdr_s *)(icmp + 1); - FAR void *inner_l4 = L4_HDR(inner); - int16_t inner_l4len = ((ipv4->len[0] << 8) + ipv4->len[1]) - - ((intptr_t)inner_l4 - (intptr_t)ipv4); - uint16_t inner_l4hdrbak[L4_MAXHDRLEN / 2]; - uint16_t inner_l4hdrlen; + FAR void *inner_l4; + uint16_t outer_l3len = (ipv4->len[0] << 8) + ipv4->len[1]; + int16_t inner_l4len; + int16_t inner_l4hdrlen; + uint16_t inner_l4hdrbak[L4_MAXHDRLEN]; + + /* Make sure we have a full inner IPv4 header. */ + + if (outer_l3len < (uintptr_t)(inner + 1) - (uintptr_t)ipv4) + { + return NULL; + } - if (inner_l4len < 8) + inner_l4 = L4_HDR(inner); + inner_l4len = (intptr_t)ipv4 + outer_l3len - (intptr_t)inner_l4; + inner_l4hdrlen = ipv4_nat_l4_hdrlen(inner->proto); + inner_l4hdrlen = MIN(inner_l4len, inner_l4hdrlen); + if (inner_l4hdrlen < 8) { /* RFC792: The original L4 data should be at least 64 bits. */ @@ -351,8 +355,6 @@ ipv4_nat_inbound_icmp(FAR struct ipv4_hdr_s *ipv4, /* Try backup origin L4 header for later checksum update. */ - inner_l4hdrlen = MIN(inner_l4len, - ipv4_nat_l4_hdrlen(inner->proto)); DEBUGASSERT((intptr_t)inner_l4 - (intptr_t)ipv4 + inner_l4hdrlen <= CONFIG_IOB_BUFSIZE); memcpy(inner_l4hdrbak, inner_l4, inner_l4hdrlen); @@ -368,15 +370,15 @@ ipv4_nat_inbound_icmp(FAR struct ipv4_hdr_s *ipv4, /* Adjust outer IP */ - ipv4_nat_ip_adjust(ipv4, NULL, entry->local_ip, manip_type); + ipv4_nat_ip_adjust(ipv4, NULL, external_ip, entry->local_ip); /* Recalculate ICMP checksum, we only need to re-calc data in L4 * header, because the inner IPv4 header's checksum is updated, * and the overall checksum of IPv4 header will not change. */ - chksum_adjust(&icmp->icmpchksum, inner_l4hdrbak, inner_l4, - inner_l4hdrlen); + nat_chksum_adjust(&icmp->icmpchksum, inner_l4hdrbak, inner_l4, + inner_l4hdrlen); return entry; } @@ -407,21 +409,24 @@ ipv4_nat_inbound_icmp(FAR struct ipv4_hdr_s *ipv4, ****************************************************************************/ #ifdef CONFIG_NET_TCP -static FAR struct ipv4_nat_entry * +static FAR ipv4_nat_entry_t * ipv4_nat_outbound_tcp(FAR struct net_driver_s *dev, FAR struct ipv4_hdr_s *ipv4, enum nat_manip_type_e manip_type) { - FAR struct tcp_hdr_s *tcp = L4_HDR(ipv4); - FAR uint16_t *local_ip = MANIP_IPADDR(ipv4, manip_type); - FAR uint16_t *local_port = MANIP_PORT(tcp, manip_type); - FAR struct ipv4_nat_entry *entry; + FAR struct tcp_hdr_s *tcp = L4_HDR(ipv4); + FAR uint16_t *local_ip = MANIP_IPADDR(ipv4, manip_type); + FAR uint16_t *local_port = MANIP_PORT(tcp, manip_type); + FAR uint16_t *peer_ip = PEER_IPADDR(ipv4, manip_type); + FAR uint16_t *peer_port = PEER_PORT(tcp, manip_type); + FAR ipv4_nat_entry_t *entry; /* Only create entry when it's the outermost packet (manip type is SRC). */ entry = ipv4_nat_outbound_entry_find(dev, IP_PROTO_TCP, net_ip4addr_conv32(local_ip), *local_port, - (manip_type == NAT_MANIP_SRC)); + net_ip4addr_conv32(peer_ip), *peer_port, + manip_type == NAT_MANIP_SRC); if (!entry) { return NULL; @@ -433,7 +438,7 @@ ipv4_nat_outbound_tcp(FAR struct net_driver_s *dev, */ ipv4_nat_port_adjust(&tcp->tcpchksum, local_port, entry->external_port); - ipv4_nat_ip_adjust(ipv4, &tcp->tcpchksum, entry->external_ip, manip_type); + ipv4_nat_ip_adjust(ipv4, &tcp->tcpchksum, local_ip, entry->external_ip); return entry; } @@ -460,22 +465,25 @@ ipv4_nat_outbound_tcp(FAR struct net_driver_s *dev, ****************************************************************************/ #ifdef CONFIG_NET_UDP -static FAR struct ipv4_nat_entry * +static FAR ipv4_nat_entry_t * ipv4_nat_outbound_udp(FAR struct net_driver_s *dev, FAR struct ipv4_hdr_s *ipv4, enum nat_manip_type_e manip_type) { - FAR struct udp_hdr_s *udp = L4_HDR(ipv4); - FAR uint16_t *local_ip = MANIP_IPADDR(ipv4, manip_type); - FAR uint16_t *local_port = MANIP_PORT(udp, manip_type); - FAR uint16_t *udpchksum; - FAR struct ipv4_nat_entry *entry; + FAR struct udp_hdr_s *udp = L4_HDR(ipv4); + FAR uint16_t *local_ip = MANIP_IPADDR(ipv4, manip_type); + FAR uint16_t *local_port = MANIP_PORT(udp, manip_type); + FAR uint16_t *peer_ip = PEER_IPADDR(ipv4, manip_type); + FAR uint16_t *peer_port = PEER_PORT(udp, manip_type); + FAR uint16_t *udpchksum; + FAR ipv4_nat_entry_t *entry; /* Only create entry when it's the outermost packet (manip type is SRC). */ entry = ipv4_nat_outbound_entry_find(dev, IP_PROTO_UDP, net_ip4addr_conv32(local_ip), *local_port, - (manip_type == NAT_MANIP_SRC)); + net_ip4addr_conv32(peer_ip), *peer_port, + manip_type == NAT_MANIP_SRC); if (!entry) { return NULL; @@ -486,7 +494,7 @@ ipv4_nat_outbound_udp(FAR struct net_driver_s *dev, udpchksum = udp->udpchksum != 0 ? &udp->udpchksum : NULL; ipv4_nat_port_adjust(udpchksum, local_port, entry->external_port); - ipv4_nat_ip_adjust(ipv4, udpchksum, entry->external_ip, manip_type); + ipv4_nat_ip_adjust(ipv4, udpchksum, local_ip, entry->external_ip); return entry; } @@ -513,14 +521,15 @@ ipv4_nat_outbound_udp(FAR struct net_driver_s *dev, ****************************************************************************/ #ifdef CONFIG_NET_ICMP -static FAR struct ipv4_nat_entry * +static FAR ipv4_nat_entry_t * ipv4_nat_outbound_icmp(FAR struct net_driver_s *dev, FAR struct ipv4_hdr_s *ipv4, enum nat_manip_type_e manip_type) { - FAR struct icmp_hdr_s *icmp = L4_HDR(ipv4); - FAR uint16_t *local_ip = MANIP_IPADDR(ipv4, manip_type); - FAR struct ipv4_nat_entry *entry; + FAR struct icmp_hdr_s *icmp = L4_HDR(ipv4); + FAR uint16_t *local_ip = MANIP_IPADDR(ipv4, manip_type); + FAR uint16_t *peer_ip = PEER_IPADDR(ipv4, manip_type); + FAR ipv4_nat_entry_t *entry; switch (icmp->type) { @@ -533,7 +542,8 @@ ipv4_nat_outbound_icmp(FAR struct net_driver_s *dev, entry = ipv4_nat_outbound_entry_find(dev, IP_PROTO_ICMP, net_ip4addr_conv32(local_ip), icmp->id, - (manip_type == NAT_MANIP_SRC)); + net_ip4addr_conv32(peer_ip), icmp->id, + manip_type == NAT_MANIP_SRC); if (!entry) { return NULL; @@ -541,7 +551,7 @@ ipv4_nat_outbound_icmp(FAR struct net_driver_s *dev, ipv4_nat_port_adjust(&icmp->icmpchksum, &icmp->id, entry->external_port); - ipv4_nat_ip_adjust(ipv4, NULL, entry->external_ip, manip_type); + ipv4_nat_ip_adjust(ipv4, NULL, local_ip, entry->external_ip); return entry; case ICMP_DEST_UNREACHABLE: @@ -558,13 +568,24 @@ ipv4_nat_outbound_icmp(FAR struct net_driver_s *dev, FAR struct ipv4_hdr_s *inner = (FAR struct ipv4_hdr_s *)(icmp + 1); - FAR void *inner_l4 = L4_HDR(inner); - int16_t inner_l4len = ((ipv4->len[0] << 8) + ipv4->len[1]) - - ((intptr_t)inner_l4 - (intptr_t)ipv4); - uint16_t inner_l4hdrbak[L4_MAXHDRLEN / 2]; - uint16_t inner_l4hdrlen; + FAR void *inner_l4; + uint16_t outer_l3len = (ipv4->len[0] << 8) + ipv4->len[1]; + int16_t inner_l4len; + int16_t inner_l4hdrlen; + uint16_t inner_l4hdrbak[L4_MAXHDRLEN]; + + /* Make sure we have a full inner IPv4 header. */ + + if (outer_l3len < (uintptr_t)(inner + 1) - (uintptr_t)ipv4) + { + return NULL; + } - if (inner_l4len < 8) + inner_l4 = L4_HDR(inner); + inner_l4len = (intptr_t)ipv4 + outer_l3len - (intptr_t)inner_l4; + inner_l4hdrlen = ipv4_nat_l4_hdrlen(inner->proto); + inner_l4hdrlen = MIN(inner_l4len, inner_l4hdrlen); + if (inner_l4hdrlen < 8) { /* RFC792: The original L4 data should be at least 64 bits. */ @@ -573,8 +594,6 @@ ipv4_nat_outbound_icmp(FAR struct net_driver_s *dev, /* Try backup origin L4 header for later checksum update. */ - inner_l4hdrlen = MIN(inner_l4len, - ipv4_nat_l4_hdrlen(inner->proto)); DEBUGASSERT((intptr_t)inner_l4 - (intptr_t)ipv4 + inner_l4hdrlen <= CONFIG_IOB_BUFSIZE); memcpy(inner_l4hdrbak, inner_l4, inner_l4hdrlen); @@ -590,15 +609,15 @@ ipv4_nat_outbound_icmp(FAR struct net_driver_s *dev, /* Adjust outer IP */ - ipv4_nat_ip_adjust(ipv4, NULL, entry->external_ip, manip_type); + ipv4_nat_ip_adjust(ipv4, NULL, local_ip, entry->external_ip); /* Recalculate ICMP checksum, we only need to re-calc data in L4 * header, because the inner IPv4 header's checksum is updated, * and the overall checksum of IPv4 header will not change. */ - chksum_adjust(&icmp->icmpchksum, inner_l4hdrbak, inner_l4, - inner_l4hdrlen); + nat_chksum_adjust(&icmp->icmpchksum, inner_l4hdrbak, inner_l4, + inner_l4hdrlen); return entry; } @@ -628,7 +647,7 @@ ipv4_nat_outbound_icmp(FAR struct net_driver_s *dev, * ****************************************************************************/ -static FAR struct ipv4_nat_entry * +static FAR ipv4_nat_entry_t * ipv4_nat_inbound_internal(FAR struct ipv4_hdr_s *ipv4, enum nat_manip_type_e manip_type) { @@ -673,7 +692,7 @@ ipv4_nat_inbound_internal(FAR struct ipv4_hdr_s *ipv4, * ****************************************************************************/ -static FAR struct ipv4_nat_entry * +static FAR ipv4_nat_entry_t * ipv4_nat_outbound_internal(FAR struct net_driver_s *dev, FAR struct ipv4_hdr_s *ipv4, enum nat_manip_type_e manip_type) @@ -703,74 +722,6 @@ ipv4_nat_outbound_internal(FAR struct net_driver_s *dev, * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: ipv4_nat_enable - * - * Description: - * Enable NAT function on a network device. - * - * Input Parameters: - * dev - The device on which the outbound packets will be masqueraded. - * - * Returned Value: - * Zero is returned if NAT function is successfully enabled on the device; - * A negated errno value is returned if failed. - * - ****************************************************************************/ - -int ipv4_nat_enable(FAR struct net_driver_s *dev) -{ - net_lock(); - - if (IFF_IS_NAT(dev->d_flags)) - { - nwarn("WARNING: NAT was already enabled for %s!\n", dev->d_ifname); - net_unlock(); - return -EEXIST; - } - - IFF_SET_NAT(dev->d_flags); - - net_unlock(); - return OK; -} - -/**************************************************************************** - * Name: ipv4_nat_disable - * - * Description: - * Disable NAT function on a network device. - * - * Input Parameters: - * dev - The device on which the NAT function will be disabled. - * - * Returned Value: - * Zero is returned if NAT function is successfully disabled on the device; - * A negated errno value is returned if failed. - * - ****************************************************************************/ - -int ipv4_nat_disable(FAR struct net_driver_s *dev) -{ - net_lock(); - - if (!IFF_IS_NAT(dev->d_flags)) - { - nwarn("WARNING: NAT was not enabled for %s!\n", dev->d_ifname); - net_unlock(); - return -ENODEV; - } - - /* Clear entries related to dev. */ - - ipv4_nat_entry_clear(dev); - - IFF_CLR_NAT(dev->d_flags); - - net_unlock(); - return OK; -} - /**************************************************************************** * Name: ipv4_nat_inbound * @@ -781,15 +732,10 @@ int ipv4_nat_disable(FAR struct net_driver_s *dev) * dev - The device on which the packet is received. * ipv4 - Points to the IPv4 header with dev->d_buf. * - * Returned Value: - * Zero is returned if NAT is successfully applied, or is not enabled for - * this packet; - * A negated errno value is returned if error occured. - * ****************************************************************************/ -int ipv4_nat_inbound(FAR struct net_driver_s *dev, - FAR struct ipv4_hdr_s *ipv4) +void ipv4_nat_inbound(FAR struct net_driver_s *dev, + FAR struct ipv4_hdr_s *ipv4) { /* We only process packets from NAT device and targeting at the address * assigned to the device. @@ -798,17 +744,8 @@ int ipv4_nat_inbound(FAR struct net_driver_s *dev, if (IFF_IS_NAT(dev->d_flags) && net_ipv4addr_hdrcmp(ipv4->destipaddr, &dev->d_ipaddr)) { - FAR struct ipv4_nat_entry *entry = - ipv4_nat_inbound_internal(ipv4, NAT_MANIP_DST); - if (!entry) - { - /* Inbound without entry is OK (e.g. towards NuttX itself), skip. */ - - return OK; - } + ipv4_nat_inbound_internal(ipv4, NAT_MANIP_DST); } - - return OK; } /**************************************************************************** @@ -844,41 +781,17 @@ int ipv4_nat_outbound(FAR struct net_driver_s *dev, { /* TODO: Skip broadcast? */ - FAR struct ipv4_nat_entry *entry = + FAR ipv4_nat_entry_t *entry = ipv4_nat_outbound_internal(dev, ipv4, manip_type); if (manip_type == NAT_MANIP_SRC && !entry) { /* Outbound entry creation failed, should have entry. */ - return -ENOMEM; + return -ENOENT; } } return OK; } -/**************************************************************************** - * Name: ipv4_nat_port_inuse - * - * Description: - * Check whether a port is currently used by NAT. - * - * Input Parameters: - * protocol - The L4 protocol of the packet. - * ip - The IP bind with the port (in network byte order). - * port - The port number to check (in network byte order). - * - * Returned Value: - * True if the port is already used by NAT, otherwise false. - * - ****************************************************************************/ - -bool ipv4_nat_port_inuse(uint8_t protocol, in_addr_t ip, uint16_t port) -{ - FAR struct ipv4_nat_entry *entry = - ipv4_nat_inbound_entry_find(protocol, ip, port, false); - - return entry != NULL; -} - -#endif /* CONFIG_NET_NAT && CONFIG_NET_IPv4 */ +#endif /* CONFIG_NET_NAT44 */ diff --git a/net/nat/ipv4_nat_entry.c b/net/nat/ipv4_nat_entry.c index e32b3c73c9276..6793ecfdcd3c1 100644 --- a/net/nat/ipv4_nat_entry.c +++ b/net/nat/ipv4_nat_entry.c @@ -31,30 +31,18 @@ #include #include #include -#include -#include "icmp/icmp.h" #include "nat/nat.h" -#include "tcp/tcp.h" -#include "udp/udp.h" +#include "netlink/netlink.h" -#if defined(CONFIG_NET_NAT) && defined(CONFIG_NET_IPv4) - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* TODO: Why we limit to 32000 in net stack? */ - -#define NAT_PORT_REASSIGN_MAX 32000 -#define NAT_PORT_REASSIGN_MIN 4096 +#ifdef CONFIG_NET_NAT44 /**************************************************************************** * Private Data ****************************************************************************/ -static DECLARE_HASHTABLE(g_table_inbound, CONFIG_NET_NAT_HASH_BITS); -static DECLARE_HASHTABLE(g_table_outbound, CONFIG_NET_NAT_HASH_BITS); +static DECLARE_HASHTABLE(g_nat44_inbound, CONFIG_NET_NAT_HASH_BITS); +static DECLARE_HASHTABLE(g_nat44_outbound, CONFIG_NET_NAT_HASH_BITS); /**************************************************************************** * Private Functions @@ -92,148 +80,6 @@ static inline uint32_t ipv4_nat_outbound_key(in_addr_t local_ip, ((uint32_t)protocol << 8) ^ ((uint32_t)local_port << 16); } -/**************************************************************************** - * Name: ipv4_nat_select_port_without_stack - * - * Description: - * Select an available port number for TCP/UDP protocol, or id for ICMP. - * Used when corresponding stack is disabled. - * - * Input Parameters: - * protocol - The L4 protocol of the packet. - * ip - The IP bind with the port (in network byte order). - * portno - The local port (in network byte order), as reference. - * - * Returned Value: - * port number on success; 0 on failure - * - ****************************************************************************/ - -#if (defined(CONFIG_NET_TCP) && defined(CONFIG_NET_TCP_NO_STACK)) || \ - (defined(CONFIG_NET_UDP) && defined(CONFIG_NET_UDP_NO_STACK)) || \ - (defined(CONFIG_NET_ICMP) && !defined(CONFIG_NET_ICMP_SOCKET)) - -static uint16_t ipv4_nat_select_port_without_stack( - uint8_t protocol, in_addr_t ip, uint16_t portno) -{ - uint16_t hport = NTOHS(portno); - while (ipv4_nat_port_inuse(protocol, ip, portno)) - { - if (++hport >= NAT_PORT_REASSIGN_MAX) - { - hport = NAT_PORT_REASSIGN_MIN; - } - - portno = HTONS(hport); - } - - return portno; -} - -#endif - -/**************************************************************************** - * Name: ipv4_nat_select_port - * - * Description: - * Select an available port number for TCP/UDP protocol, or id for ICMP. - * - * Input Parameters: - * dev - The device on which the packet will be sent. - * protocol - The L4 protocol of the packet. - * local_port - The local port of the packet, as reference. - * - * Returned Value: - * port number on success; 0 on failure - * - ****************************************************************************/ - -static uint16_t ipv4_nat_select_port(FAR struct net_driver_s *dev, - uint8_t protocol, - uint16_t local_port) -{ - switch (protocol) - { -#ifdef CONFIG_NET_TCP - case IP_PROTO_TCP: - { -#ifndef CONFIG_NET_TCP_NO_STACK - /* Try to select local_port first. */ - - int ret = tcp_selectport(PF_INET, - (FAR const union ip_addr_u *)&dev->d_ipaddr, - local_port); - - /* If failed, try select another unused port. */ - - if (ret < 0) - { - ret = tcp_selectport(PF_INET, - (FAR const union ip_addr_u *)&dev->d_ipaddr, 0); - } - - return ret > 0 ? ret : 0; -#else - return ipv4_nat_select_port_without_stack(IP_PROTO_TCP, - dev->d_ipaddr, - local_port); -#endif - } -#endif - -#ifdef CONFIG_NET_UDP - case IP_PROTO_UDP: - { -#ifndef CONFIG_NET_UDP_NO_STACK - union ip_binding_u u; - u.ipv4.laddr = dev->d_ipaddr; - u.ipv4.raddr = INADDR_ANY; - - /* TODO: Try keep origin port as possible. */ - - return HTONS(udp_select_port(PF_INET, &u)); -#else - return ipv4_nat_select_port_without_stack(IP_PROTO_UDP, - dev->d_ipaddr, - local_port); -#endif - } -#endif - -#ifdef CONFIG_NET_ICMP - case IP_PROTO_ICMP: - { -#ifdef CONFIG_NET_ICMP_SOCKET - uint16_t id = local_port; - uint16_t hid = NTOHS(id); - while (icmp_findconn(dev, id) || - ipv4_nat_port_inuse(IP_PROTO_ICMP, dev->d_ipaddr, id)) - { - if (++hid >= NAT_PORT_REASSIGN_MAX) - { - hid = NAT_PORT_REASSIGN_MIN; - } - - id = HTONS(hid); - } - - return id; -#else - return ipv4_nat_select_port_without_stack(IP_PROTO_ICMP, - dev->d_ipaddr, - local_port); -#endif - } -#endif - } - - /* TODO: Currently select original port for unsupported protocol, maybe - * return zero to indicate failure. - */ - - return local_port; -} - /**************************************************************************** * Name: ipv4_nat_entry_refresh * @@ -245,42 +91,9 @@ static uint16_t ipv4_nat_select_port(FAR struct net_driver_s *dev, * ****************************************************************************/ -static void ipv4_nat_entry_refresh(FAR struct ipv4_nat_entry *entry) +static void ipv4_nat_entry_refresh(FAR ipv4_nat_entry_t *entry) { - /* Note: May add logic here to move recent node to head side if each chain - * in hashtable is still too long (with long expire time). - */ - - switch (entry->protocol) - { -#ifdef CONFIG_NET_TCP - case IP_PROTO_TCP: - /* NOTE: According to RFC2663, Section 2.6, Page 5, we can reduce the - * time to 4min if we have received FINs from both side of one - * connection, and keep 24h for other TCP connections. However, full - * cone NAT may have multiple connections on one entry, so this - * optimization may not work and we only use one expiration time. - */ - - entry->expire_time = TICK2SEC(clock_systime_ticks()) + - CONFIG_NET_NAT_TCP_EXPIRE_SEC; - break; -#endif - -#ifdef CONFIG_NET_UDP - case IP_PROTO_UDP: - entry->expire_time = TICK2SEC(clock_systime_ticks()) + - CONFIG_NET_NAT_UDP_EXPIRE_SEC; - break; -#endif - -#ifdef CONFIG_NET_ICMP - case IP_PROTO_ICMP: - entry->expire_time = TICK2SEC(clock_systime_ticks()) + - CONFIG_NET_NAT_ICMP_EXPIRE_SEC; - break; -#endif - } + entry->expire_time = nat_expire_time(entry->protocol); } /**************************************************************************** @@ -295,19 +108,21 @@ static void ipv4_nat_entry_refresh(FAR struct ipv4_nat_entry *entry) * external_port - The external port of the packet. * local_ip - The local ip of the packet. * local_port - The local port of the packet. + * peer_ip - The peer ip of the packet. + * peer_port - The peer port of the packet. * * Returned Value: * Pointer to entry on success; null on failure * ****************************************************************************/ -static FAR struct ipv4_nat_entry * +static FAR ipv4_nat_entry_t * ipv4_nat_entry_create(uint8_t protocol, in_addr_t external_ip, uint16_t external_port, - in_addr_t local_ip, uint16_t local_port) + in_addr_t local_ip, uint16_t local_port, + in_addr_t peer_ip, uint16_t peer_port) { - FAR struct ipv4_nat_entry *entry = - kmm_malloc(sizeof(struct ipv4_nat_entry)); + FAR ipv4_nat_entry_t *entry = kmm_malloc(sizeof(ipv4_nat_entry_t)); if (entry == NULL) { nwarn("WARNING: Failed to allocate IPv4 NAT entry\n"); @@ -319,14 +134,22 @@ ipv4_nat_entry_create(uint8_t protocol, entry->external_port = external_port; entry->local_ip = local_ip; entry->local_port = local_port; +#ifdef CONFIG_NET_NAT44_SYMMETRIC + entry->peer_ip = peer_ip; + entry->peer_port = peer_port; +#endif ipv4_nat_entry_refresh(entry); - hashtable_add(g_table_inbound, &entry->hash_inbound, + hashtable_add(g_nat44_inbound, &entry->hash_inbound, ipv4_nat_inbound_key(external_ip, external_port, protocol)); - hashtable_add(g_table_outbound, &entry->hash_outbound, + hashtable_add(g_nat44_outbound, &entry->hash_outbound, ipv4_nat_outbound_key(local_ip, local_port, protocol)); +#ifdef CONFIG_NETLINK_NETFILTER + netlink_conntrack_notify(IPCTNL_MSG_CT_NEW, PF_INET, entry); +#endif + return entry; } @@ -341,21 +164,26 @@ ipv4_nat_entry_create(uint8_t protocol, * ****************************************************************************/ -static void ipv4_nat_entry_delete(FAR struct ipv4_nat_entry *entry) +static void ipv4_nat_entry_delete(FAR ipv4_nat_entry_t *entry) { - ninfo("INFO: Removing NAT entry proto=%" PRIu8 + ninfo("INFO: Removing NAT44 entry proto=%" PRIu8 ", local=%" PRIx32 ":%" PRIu16 ", external=:%" PRIu16 "\n", entry->protocol, entry->local_ip, entry->local_port, entry->external_port); - hashtable_delete(g_table_inbound, &entry->hash_inbound, + hashtable_delete(g_nat44_inbound, &entry->hash_inbound, ipv4_nat_inbound_key(entry->external_ip, entry->external_port, entry->protocol)); - hashtable_delete(g_table_outbound, &entry->hash_outbound, - ipv4_nat_outbound_key(entry->local_ip, entry->local_port, + hashtable_delete(g_nat44_outbound, &entry->hash_outbound, + ipv4_nat_outbound_key(entry->local_ip, + entry->local_port, entry->protocol)); +#ifdef CONFIG_NETLINK_NETFILTER + netlink_conntrack_notify(IPCTNL_MSG_CT_DELETE, PF_INET, entry); +#endif + kmm_free(entry); } @@ -376,36 +204,51 @@ static void ipv4_nat_entry_delete(FAR struct ipv4_nat_entry *entry) ****************************************************************************/ #if CONFIG_NET_NAT_ENTRY_RECLAIM_SEC > 0 +static void ipv4_nat_reclaim_entry_cb(FAR ipv4_nat_entry_t *entry, + FAR void *arg) +{ + int32_t current_time = *(FAR int32_t *)arg; + + if (entry->expire_time - current_time <= 0) + { + ipv4_nat_entry_delete(entry); + } +} + static void ipv4_nat_reclaim_entry(int32_t current_time) { static int32_t next_reclaim_time = CONFIG_NET_NAT_ENTRY_RECLAIM_SEC; if (next_reclaim_time - current_time <= 0) { - FAR hash_node_t *p; - FAR hash_node_t *tmp; - int count = 0; - int i; - - ninfo("INFO: Reclaiming all expired NAT entries.\n"); + ninfo("INFO: Reclaiming all expired NAT44 entries.\n"); + ipv4_nat_entry_foreach(ipv4_nat_reclaim_entry_cb, ¤t_time); + next_reclaim_time = current_time + CONFIG_NET_NAT_ENTRY_RECLAIM_SEC; + } +} +#else +# define ipv4_nat_reclaim_entry(t) +#endif - hashtable_for_every_safe(g_table_inbound, p, tmp, i) - { - FAR struct ipv4_nat_entry *entry = - container_of(p, struct ipv4_nat_entry, hash_inbound); +/**************************************************************************** + * Name: ipv4_nat_entry_clear_cb + * + * Description: + * Clear an entry related to dev. Called when NAT will be disabled on + * any device. + * + ****************************************************************************/ - if (entry->expire_time - current_time <= 0) - { - ipv4_nat_entry_delete(entry); - count++; - } - } +static void ipv4_nat_entry_clear_cb(FAR ipv4_nat_entry_t *entry, + FAR void *arg) +{ + FAR struct net_driver_s *dev = arg; - ninfo("INFO: %d expired NAT entries reclaimed.\n", count); - next_reclaim_time = current_time + CONFIG_NET_NAT_ENTRY_RECLAIM_SEC; + if (net_ipv4addr_cmp(entry->external_ip, dev->d_ipaddr)) + { + ipv4_nat_entry_delete(entry); } } -#endif /**************************************************************************** * Public Functions @@ -419,7 +262,7 @@ static void ipv4_nat_reclaim_entry(int32_t current_time) * any device. * * Input Parameters: - * dev - The device on which NAT entries will be cleared. + * dev - The device on which NAT entries will be cleared. * * Assumptions: * NAT is initialized. @@ -427,22 +270,35 @@ static void ipv4_nat_reclaim_entry(int32_t current_time) ****************************************************************************/ void ipv4_nat_entry_clear(FAR struct net_driver_s *dev) +{ + ninfo("INFO: Clearing all NAT44 entries for %s\n", dev->d_ifname); + ipv4_nat_entry_foreach(ipv4_nat_entry_clear_cb, dev); +} + +/**************************************************************************** + * Name: ipv4_nat_entry_foreach + * + * Description: + * Call the callback function for each NAT entry. + * + * Input Parameters: + * cb - The callback function. + * arg - The argument to pass to the callback function. + * + ****************************************************************************/ + +void ipv4_nat_entry_foreach(ipv4_nat_entry_cb_t cb, FAR void *arg) { FAR hash_node_t *p; FAR hash_node_t *tmp; int i; - ninfo("INFO: Clearing all NAT entries for %s\n", dev->d_ifname); - - hashtable_for_every_safe(g_table_inbound, p, tmp, i) + hashtable_for_every_safe(g_nat44_inbound, p, tmp, i) { - FAR struct ipv4_nat_entry *entry = - container_of(p, struct ipv4_nat_entry, hash_inbound); + FAR ipv4_nat_entry_t *entry = + container_of(p, ipv4_nat_entry_t, hash_inbound); - if (net_ipv4addr_cmp(entry->external_ip, dev->d_ipaddr)) - { - ipv4_nat_entry_delete(entry); - } + cb(entry, arg); } } @@ -456,6 +312,8 @@ void ipv4_nat_entry_clear(FAR struct net_driver_s *dev) * protocol - The L4 protocol of the packet. * external_ip - The external ip of the packet, supports INADDR_ANY. * external_port - The external port of the packet. + * peer_ip - The peer ip of the packet. + * peer_port - The peer port of the packet. * refresh - Whether to refresh the selected entry. * * Returned Value: @@ -463,24 +321,26 @@ void ipv4_nat_entry_clear(FAR struct net_driver_s *dev) * ****************************************************************************/ -FAR struct ipv4_nat_entry * +FAR ipv4_nat_entry_t * ipv4_nat_inbound_entry_find(uint8_t protocol, in_addr_t external_ip, - uint16_t external_port, bool refresh) + uint16_t external_port, in_addr_t peer_ip, + uint16_t peer_port, bool refresh) { FAR hash_node_t *p; FAR hash_node_t *tmp; bool skip_ip = net_ipv4addr_cmp(external_ip, INADDR_ANY); +#ifdef CONFIG_NET_NAT44_SYMMETRIC + bool skip_peer = net_ipv4addr_cmp(peer_ip, INADDR_ANY); +#endif int32_t current_time = TICK2SEC(clock_systime_ticks()); -#if CONFIG_NET_NAT_ENTRY_RECLAIM_SEC > 0 ipv4_nat_reclaim_entry(current_time); -#endif - hashtable_for_every_possible_safe(g_table_inbound, p, tmp, + hashtable_for_every_possible_safe(g_nat44_inbound, p, tmp, ipv4_nat_inbound_key(external_ip, external_port, protocol)) { - FAR struct ipv4_nat_entry *entry = - container_of(p, struct ipv4_nat_entry, hash_inbound); + FAR ipv4_nat_entry_t *entry = + container_of(p, ipv4_nat_entry_t, hash_inbound); /* Remove expired entries. */ @@ -492,7 +352,12 @@ ipv4_nat_inbound_entry_find(uint8_t protocol, in_addr_t external_ip, if (entry->protocol == protocol && (skip_ip || net_ipv4addr_cmp(entry->external_ip, external_ip)) && - entry->external_port == external_port) + entry->external_port == external_port +#ifdef CONFIG_NET_NAT44_SYMMETRIC + && (skip_peer || (net_ipv4addr_cmp(entry->peer_ip, peer_ip) && + entry->peer_port == peer_port)) +#endif + ) { if (refresh) { @@ -525,6 +390,8 @@ ipv4_nat_inbound_entry_find(uint8_t protocol, in_addr_t external_ip, * protocol - The L4 protocol of the packet. * local_ip - The local ip of the packet. * local_port - The local port of the packet. + * peer_ip - The peer ip of the packet. + * peer_port - The peer port of the packet. * try_create - Try create the entry if no entry found. * * Returned Value: @@ -532,24 +399,24 @@ ipv4_nat_inbound_entry_find(uint8_t protocol, in_addr_t external_ip, * ****************************************************************************/ -FAR struct ipv4_nat_entry * +FAR ipv4_nat_entry_t * ipv4_nat_outbound_entry_find(FAR struct net_driver_s *dev, uint8_t protocol, in_addr_t local_ip, uint16_t local_port, + in_addr_t peer_ip, uint16_t peer_port, bool try_create) { FAR hash_node_t *p; FAR hash_node_t *tmp; + uint16_t external_port; int32_t current_time = TICK2SEC(clock_systime_ticks()); -#if CONFIG_NET_NAT_ENTRY_RECLAIM_SEC > 0 ipv4_nat_reclaim_entry(current_time); -#endif - hashtable_for_every_possible_safe(g_table_outbound, p, tmp, + hashtable_for_every_possible_safe(g_nat44_outbound, p, tmp, ipv4_nat_outbound_key(local_ip, local_port, protocol)) { - FAR struct ipv4_nat_entry *entry = - container_of(p, struct ipv4_nat_entry, hash_outbound); + FAR ipv4_nat_entry_t *entry = + container_of(p, ipv4_nat_entry_t, hash_outbound); /* Remove expired entries. */ @@ -562,7 +429,12 @@ ipv4_nat_outbound_entry_find(FAR struct net_driver_s *dev, uint8_t protocol, if (entry->protocol == protocol && net_ipv4addr_cmp(entry->external_ip, dev->d_ipaddr) && net_ipv4addr_cmp(entry->local_ip, local_ip) && - entry->local_port == local_port) + entry->local_port == local_port +#ifdef CONFIG_NET_NAT44_SYMMETRIC + && net_ipv4addr_cmp(entry->peer_ip, peer_ip) && + entry->peer_port == peer_port +#endif + ) { ipv4_nat_entry_refresh(entry); return entry; @@ -580,7 +452,8 @@ ipv4_nat_outbound_entry_find(FAR struct net_driver_s *dev, uint8_t protocol, "proto=%" PRIu8 ", local=%" PRIx32 ":%" PRIu16 ", try create one.\n", protocol, local_ip, local_port); - uint16_t external_port = ipv4_nat_select_port(dev, protocol, local_port); + external_port = nat_port_select(dev, PF_INET, protocol, + (FAR union ip_addr_u *)&dev->d_ipaddr, local_port); if (!external_port) { nwarn("WARNING: Failed to find an available port!\n"); @@ -588,7 +461,7 @@ ipv4_nat_outbound_entry_find(FAR struct net_driver_s *dev, uint8_t protocol, } return ipv4_nat_entry_create(protocol, dev->d_ipaddr, external_port, - local_ip, local_port); + local_ip, local_port, peer_ip, peer_port); } -#endif /* CONFIG_NET_NAT && CONFIG_NET_IPv4 */ +#endif /* CONFIG_NET_NAT44 */ diff --git a/net/nat/ipv6_nat.c b/net/nat/ipv6_nat.c new file mode 100644 index 0000000000000..a77132040c8af --- /dev/null +++ b/net/nat/ipv6_nat.c @@ -0,0 +1,685 @@ +/**************************************************************************** + * net/nat/ipv6_nat.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "nat/nat.h" +#include "utils/utils.h" + +#ifdef CONFIG_NET_NAT66 + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static FAR ipv6_nat_entry_t * +ipv6_nat_inbound_internal(FAR struct ipv6_hdr_s *ipv6, + enum nat_manip_type_e manip_type); + +static FAR ipv6_nat_entry_t * +ipv6_nat_outbound_internal(FAR struct net_driver_s *dev, + FAR struct ipv6_hdr_s *ipv6, + enum nat_manip_type_e manip_type); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ipv6_nat_ip_adjust + * + * Description: + * Adjust address and checksum for network packet. + * + * Input Parameters: + * l4chksum - Points to the L4 checksum to adjust, NULL for not adjust. + * old_ip - The IP to be set. + * new_ip - The IP to set into header. + * + ****************************************************************************/ + +static void ipv6_nat_ip_adjust(FAR uint16_t *l4chksum, FAR uint16_t *old_ip, + net_ipv6addr_t new_ip) +{ + /* TODO: Maybe we can accelerate the checksum adjustment by pre-calculate a + * difference of checksum, and apply it to each packet, instead of calling + * chksum_adjust each time. + */ + + if (l4chksum != NULL) + { + nat_chksum_adjust(l4chksum, old_ip, new_ip, sizeof(net_ipv6addr_t)); + } + + net_ipv6addr_hdrcopy(old_ip, new_ip); +} + +/**************************************************************************** + * Name: ipv6_nat_port_adjust + * + * Description: + * Adjust port and checksum for network packet. + * + * Input Parameters: + * l4chksum - Points to the L4 checksum to adjust, NULL for not adjust. + * old_port - The port to be set. + * new_port - The port to set into header. + * + ****************************************************************************/ + +static void ipv6_nat_port_adjust(FAR uint16_t *l4chksum, + FAR uint16_t *old_port, uint16_t new_port) +{ + if (l4chksum != NULL) + { + nat_chksum_adjust(l4chksum, old_port, &new_port, sizeof(new_port)); + } + + *old_port = new_port; +} + +/**************************************************************************** + * Name: ipv6_nat_inbound_tcp + * + * Description: + * Check if a received TCP packet belongs to a NAT entry. If so, translate + * the external IP/Port to local IP/Port. + * + * Input Parameters: + * ipv6 - Points to the IPv6 header to translate. + * tcp - Points to the TCP header to translate. + * manip_type - Whether external IP/Port is in source or destination. + * + * Returned Value: + * The corresponding NAT entry of the packet. + * + * Assumptions: + * Packet is received on NAT device and is targeting at the address + * assigned to the device. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_TCP +static FAR ipv6_nat_entry_t * +ipv6_nat_inbound_tcp(FAR struct ipv6_hdr_s *ipv6, FAR struct tcp_hdr_s *tcp, + enum nat_manip_type_e manip_type) +{ + FAR uint16_t *external_ip = MANIP_IPADDR(ipv6, manip_type); + FAR uint16_t *external_port = MANIP_PORT(tcp, manip_type); + FAR uint16_t *peer_ip = PEER_IPADDR(ipv6, manip_type); + FAR uint16_t *peer_port = PEER_PORT(tcp, manip_type); + FAR ipv6_nat_entry_t *entry = + ipv6_nat_inbound_entry_find(IP_PROTO_TCP, + external_ip, *external_port, + peer_ip, *peer_port, true); + if (!entry) + { + return NULL; + } + + /* Note: Field tcpchksum is not guaranteed exists in TCP header inside + * ICMPv6 Error MSG, but we manually guarantee that it is inside valid + * address (IOB >= IP + ICMPv6 + IP + TCP), so we can update it safely. + */ + + ipv6_nat_port_adjust(&tcp->tcpchksum, external_port, entry->local_port); + ipv6_nat_ip_adjust(&tcp->tcpchksum, external_ip, entry->local_ip); + + return entry; +} +#endif + +/**************************************************************************** + * Name: ipv6_nat_inbound_udp + * + * Description: + * Check if a received UDP packet belongs to a NAT entry. If so, translate + * the external IP/Port to local IP/Port. + * + * Input Parameters: + * ipv6 - Points to the IPv6 header to translate. + * udp - Points to the UDP header to translate. + * manip_type - Whether external IP/Port is in source or destination. + * + * Returned Value: + * The corresponding NAT entry of the packet. + * + * Assumptions: + * Packet is received on NAT device and is targeting at the address + * assigned to the device. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_UDP +static FAR ipv6_nat_entry_t * +ipv6_nat_inbound_udp(FAR struct ipv6_hdr_s *ipv6, FAR struct udp_hdr_s *udp, + enum nat_manip_type_e manip_type) +{ + FAR uint16_t *external_ip = MANIP_IPADDR(ipv6, manip_type); + FAR uint16_t *external_port = MANIP_PORT(udp, manip_type); + FAR uint16_t *peer_ip = PEER_IPADDR(ipv6, manip_type); + FAR uint16_t *peer_port = PEER_PORT(udp, manip_type); + FAR uint16_t *udpchksum; + FAR ipv6_nat_entry_t *entry = + ipv6_nat_inbound_entry_find(IP_PROTO_UDP, + external_ip, *external_port, + peer_ip, *peer_port, true); + + if (!entry) + { + return NULL; + } + + /* UDP checksum has special case 0 (no checksum) */ + + udpchksum = udp->udpchksum != 0 ? &udp->udpchksum : NULL; + + ipv6_nat_port_adjust(udpchksum, external_port, entry->local_port); + ipv6_nat_ip_adjust(udpchksum, external_ip, entry->local_ip); + + return entry; +} +#endif + +/**************************************************************************** + * Name: ipv6_nat_inbound_icmpv6 + * + * Description: + * Check if a received ICMPv6 packet belongs to a NAT entry. If so, + * translate the external IP/ID to local IP/ID. + * + * Input Parameters: + * ipv6 - Points to the IPv6 header to translate. + * icmpv6 - Points to the ICMPv6 header to translate. + * manip_type - Whether external IP is in source or destination. + * + * Returned Value: + * The corresponding NAT entry of the packet. + * + * Assumptions: + * Packet is received on g_dev and is targeting at the address assigned to + * g_dev. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_ICMPv6 +static FAR ipv6_nat_entry_t * +ipv6_nat_inbound_icmpv6(FAR struct ipv6_hdr_s *ipv6, + FAR struct icmpv6_hdr_s *icmpv6, + enum nat_manip_type_e manip_type) +{ + FAR uint16_t *external_ip = MANIP_IPADDR(ipv6, manip_type); + FAR uint16_t *peer_ip = PEER_IPADDR(ipv6, manip_type); + FAR ipv6_nat_entry_t *entry; + + switch (icmpv6->type) + { + case ICMPv6_ECHO_REQUEST: + case ICMPv6_ECHO_REPLY: + entry = ipv6_nat_inbound_entry_find(IP_PROTO_ICMP6, + external_ip, icmpv6->data[0], + peer_ip, icmpv6->data[0], true); + if (!entry) + { + return NULL; + } + + ipv6_nat_port_adjust(&icmpv6->chksum, + &icmpv6->data[0], entry->local_port); + ipv6_nat_ip_adjust(&icmpv6->chksum, external_ip, entry->local_ip); + return entry; + + case ICMPv6_DEST_UNREACHABLE: + case ICMPv6_PACKET_TOO_BIG: + case ICMPv6_PACKET_TIME_EXCEEDED: + case ICMPv6_PACKET_PARAM_PROBLEM: + /* ICMPv6 Error MSG inside another ICMPv6 Error MSG is forbidden by + * RFC4443, Section 2.4, Page 6, so we only process the outermost + * ICMPv6 Error MSG (manip type is DST). + */ + + if (manip_type == NAT_MANIP_DST) + { + /* The payload in the ICMPv6 packet is the origin packet we sent. + * We don't need to check or backup any inner L4 data, because + * every ICMPv6 error message (type < 128) MUST include as much + * of the IPv6 offending (invoking) packet as possible. And the + * inner packet will be translated by the inbound process + * without needed to modify any outer packet checksum. + */ + + FAR struct ipv6_hdr_s *inner = + (FAR struct ipv6_hdr_s *)(icmpv6 + 1); + + /* Find entry and translate inner. */ + + entry = ipv6_nat_inbound_internal(inner, NAT_MANIP_SRC); + + if (!entry) + { + return NULL; + } + + /* Adjust outer IP */ + + ipv6_nat_ip_adjust(&icmpv6->chksum, external_ip, + entry->local_ip); + + return entry; + } + } + + return NULL; +} +#endif + +/**************************************************************************** + * Name: ipv6_nat_outbound_tcp + * + * Description: + * Check if we want to perform NAT with this outbound TCP packet before + * sending it. If so, translate the local IP/Port to external IP/Port. + * + * Input Parameters: + * dev - The device to sent the packet (to get external IP). + * ipv6 - Points to the IPv6 header to translate. + * tcp - Points to the TCP header to translate. + * manip_type - Whether local IP/Port is in source or destination. + * + * Returned Value: + * The corresponding NAT entry of the packet. + * + * Assumptions: + * Packet will be sent on NAT device. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_TCP +static FAR ipv6_nat_entry_t * +ipv6_nat_outbound_tcp(FAR struct net_driver_s *dev, + FAR struct ipv6_hdr_s *ipv6, FAR struct tcp_hdr_s *tcp, + enum nat_manip_type_e manip_type) +{ + FAR uint16_t *local_ip = MANIP_IPADDR(ipv6, manip_type); + FAR uint16_t *local_port = MANIP_PORT(tcp, manip_type); + FAR uint16_t *peer_ip = PEER_IPADDR(ipv6, manip_type); + FAR uint16_t *peer_port = PEER_PORT(tcp, manip_type); + FAR ipv6_nat_entry_t *entry; + + /* Only create entry when it's the outermost packet (manip type is SRC). */ + + entry = ipv6_nat_outbound_entry_find(dev, IP_PROTO_TCP, + local_ip, *local_port, peer_ip, *peer_port, + manip_type == NAT_MANIP_SRC); + if (!entry) + { + return NULL; + } + + /* Note: Field tcpchksum is not guaranteed exists in TCP header inside + * ICMPv6 Error MSG, but we manually guarantee that it is inside valid + * address (IOB >= IP + ICMPv6 + IP + TCP), so we can update it safely. + */ + + ipv6_nat_port_adjust(&tcp->tcpchksum, local_port, entry->external_port); + ipv6_nat_ip_adjust(&tcp->tcpchksum, local_ip, entry->external_ip); + + return entry; +} +#endif + +/**************************************************************************** + * Name: ipv6_nat_outbound_udp + * + * Description: + * Check if we want to perform NAT with this outbound UDP packet before + * sending it. If so, translate the local IP/Port to external IP/Port. + * + * Input Parameters: + * dev - The device to sent the packet (to get external IP). + * ipv6 - Points to the IPv6 header to translate. + * udp - Points to the UDP header to translate. + * manip_type - Whether local IP/Port is in source or destination. + * + * Returned Value: + * The corresponding NAT entry of the packet. + * + * Assumptions: + * Packet will be sent on NAT device. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_UDP +static FAR ipv6_nat_entry_t * +ipv6_nat_outbound_udp(FAR struct net_driver_s *dev, + FAR struct ipv6_hdr_s *ipv6, FAR struct udp_hdr_s *udp, + enum nat_manip_type_e manip_type) +{ + FAR uint16_t *local_ip = MANIP_IPADDR(ipv6, manip_type); + FAR uint16_t *local_port = MANIP_PORT(udp, manip_type); + FAR uint16_t *peer_ip = PEER_IPADDR(ipv6, manip_type); + FAR uint16_t *peer_port = PEER_PORT(udp, manip_type); + FAR uint16_t *udpchksum; + FAR ipv6_nat_entry_t *entry; + + /* Only create entry when it's the outermost packet (manip type is SRC). */ + + entry = ipv6_nat_outbound_entry_find(dev, IP_PROTO_UDP, + local_ip, *local_port, peer_ip, *peer_port, + manip_type == NAT_MANIP_SRC); + if (!entry) + { + return NULL; + } + + /* UDP checksum has special case 0 (no checksum) */ + + udpchksum = udp->udpchksum != 0 ? &udp->udpchksum : NULL; + + ipv6_nat_port_adjust(udpchksum, local_port, entry->external_port); + ipv6_nat_ip_adjust(udpchksum, local_ip, entry->external_ip); + + return entry; +} +#endif + +/**************************************************************************** + * Name: ipv6_nat_outbound_icmpv6 + * + * Description: + * Check if we want to perform NAT with this outbound ICMPv6 packet before + * sending it. If so, translate the local IP/ID to external IP/ID. + * + * Input Parameters: + * dev - The device to sent the packet (to get external IP). + * ipv6 - Points to the IPv6 header to translate. + * icmpv6 - Points to the ICMPv6 header to translate. + * manip_type - Whether local IP is in source or destination. + * + * Returned Value: + * The corresponding NAT entry of the packet. + * + * Assumptions: + * Packet will be sent on NAT device. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_ICMPv6 +static FAR ipv6_nat_entry_t * +ipv6_nat_outbound_icmpv6(FAR struct net_driver_s *dev, + FAR struct ipv6_hdr_s *ipv6, + FAR struct icmpv6_hdr_s *icmpv6, + enum nat_manip_type_e manip_type) +{ + FAR uint16_t *local_ip = MANIP_IPADDR(ipv6, manip_type); + FAR uint16_t *peer_ip = PEER_IPADDR(ipv6, manip_type); + FAR ipv6_nat_entry_t *entry; + + switch (icmpv6->type) + { + case ICMPv6_ECHO_REQUEST: + case ICMPv6_ECHO_REPLY: + + /* Note: Only create new entry when it's the outermost packet (that + * is, manip type is SRC). + */ + + entry = ipv6_nat_outbound_entry_find(dev, IP_PROTO_ICMP6, + local_ip, icmpv6->data[0], peer_ip, icmpv6->data[0], + manip_type == NAT_MANIP_SRC); + if (!entry) + { + return NULL; + } + + ipv6_nat_port_adjust(&icmpv6->chksum, + &icmpv6->data[0], entry->external_port); + ipv6_nat_ip_adjust(&icmpv6->chksum, local_ip, entry->external_ip); + return entry; + + case ICMPv6_DEST_UNREACHABLE: + case ICMPv6_PACKET_TOO_BIG: + case ICMPv6_PACKET_TIME_EXCEEDED: + case ICMPv6_PACKET_PARAM_PROBLEM: + /* ICMPv6 Error MSG inside another ICMPv6 Error MSG is forbidden by + * RFC4443, Section 2.4, Page 6, so we only process the outermost + * ICMPv6 Error MSG (manip type is DST). + */ + + if (manip_type == NAT_MANIP_SRC) + { + /* The payload in the ICMPv6 packet is the origin packet we got. + * We don't need to check or backup any inner L4 data, because + * every ICMPv6 error message (type < 128) MUST include as much + * of the IPv6 offending (invoking) packet as possible. And the + * inner packet will be translated by the inbound process + * without needed to modify any outer packet checksum. + */ + + FAR struct ipv6_hdr_s *inner = + (FAR struct ipv6_hdr_s *)(icmpv6 + 1); + + /* Find entry and translate inner. */ + + entry = ipv6_nat_outbound_internal(dev, inner, NAT_MANIP_DST); + + if (!entry) + { + return NULL; + } + + /* Adjust outer IP */ + + ipv6_nat_ip_adjust(&icmpv6->chksum, local_ip, + entry->external_ip); + + return entry; + } + } + + return NULL; +} +#endif + +/**************************************************************************** + * Name: ipv6_nat_inbound_internal + * + * Description: + * Check if a received packet belongs to a NAT entry. If so, translate + * the external IP/Port to local IP/Port. + * + * Input Parameters: + * ipv6 - Points to the IPv6 header to translate. + * manip_type - Whether external IP/Port is in source or destination. + * + * Returned Value: + * The corresponding NAT entry of the packet. + * + * Assumptions: + * Packet is received on NAT device and is targeting at the address + * assigned to the device. + * + ****************************************************************************/ + +static FAR ipv6_nat_entry_t * +ipv6_nat_inbound_internal(FAR struct ipv6_hdr_s *ipv6, + enum nat_manip_type_e manip_type) +{ + uint8_t proto; + FAR void *l4hdr = net_ipv6_payload(ipv6, &proto); + + switch (ipv6->proto) + { +#ifdef CONFIG_NET_TCP + case IP_PROTO_TCP: + return ipv6_nat_inbound_tcp(ipv6, l4hdr, manip_type); +#endif + +#ifdef CONFIG_NET_UDP + case IP_PROTO_UDP: + return ipv6_nat_inbound_udp(ipv6, l4hdr, manip_type); +#endif + +#ifdef CONFIG_NET_ICMPv6 + case IP_PROTO_ICMP6: + return ipv6_nat_inbound_icmpv6(ipv6, l4hdr, manip_type); +#endif + } + + return NULL; +} + +/**************************************************************************** + * Name: ipv6_nat_outbound_internal + * + * Description: + * Check if we want to perform NAT with this outbound packet before + * sending it. If so, translate the local IP/Port to external IP/Port. + * + * Input Parameters: + * dev - The device to sent the packet (to get external IP). + * ipv6 - Points to the IPv6 header to translate. + * manip_type - Whether local IP/Port is in source or destination. + * + * Returned Value: + * The corresponding NAT entry of the packet. + * + * Assumptions: + * Packet will be sent on NAT device. + * + ****************************************************************************/ + +static FAR ipv6_nat_entry_t * +ipv6_nat_outbound_internal(FAR struct net_driver_s *dev, + FAR struct ipv6_hdr_s *ipv6, + enum nat_manip_type_e manip_type) +{ + uint8_t proto; + FAR void *l4hdr = net_ipv6_payload(ipv6, &proto); + + switch (proto) + { +#ifdef CONFIG_NET_TCP + case IP_PROTO_TCP: + return ipv6_nat_outbound_tcp(dev, ipv6, l4hdr, manip_type); +#endif + +#ifdef CONFIG_NET_UDP + case IP_PROTO_UDP: + return ipv6_nat_outbound_udp(dev, ipv6, l4hdr, manip_type); +#endif + +#ifdef CONFIG_NET_ICMPv6 + case IP_PROTO_ICMP6: + return ipv6_nat_outbound_icmpv6(dev, ipv6, l4hdr, manip_type); +#endif + } + + return NULL; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ipv6_nat_inbound + * + * Description: + * Check if a received packet belongs to a NAT entry. If so, translate it. + * + * Input Parameters: + * dev - The device on which the packet is received. + * ipv6 - Points to the IPv6 header with dev->d_buf. + * + ****************************************************************************/ + +void ipv6_nat_inbound(FAR struct net_driver_s *dev, + FAR struct ipv6_hdr_s *ipv6) +{ + /* We only process packets from NAT device and targeting at the address + * assigned to the device. + */ + + if (IFF_IS_NAT(dev->d_flags) && + NETDEV_IS_MY_V6ADDR(dev, ipv6->destipaddr)) + { + ipv6_nat_inbound_internal(ipv6, NAT_MANIP_DST); + } +} + +/**************************************************************************** + * Name: ipv6_nat_outbound + * + * Description: + * Check if we want to perform NAT with this outbound packet before sending + * it. If so, translate it. + * + * Input Parameters: + * dev - The device on which the packet will be sent. + * ipv6 - Points to the IPv6 header to be filled into dev->d_buf later. + * manip_type - Whether local IP/Port is in source or destination. + * + * Returned Value: + * Zero is returned if NAT is successfully applied, or is not enabled for + * this packet; + * A negated errno value is returned if error occured. + * + ****************************************************************************/ + +int ipv6_nat_outbound(FAR struct net_driver_s *dev, + FAR struct ipv6_hdr_s *ipv6, + enum nat_manip_type_e manip_type) +{ + /* We only process packets targeting at NAT device but not targeting at the + * address assigned to the device. + */ + + if (IFF_IS_NAT(dev->d_flags) && + !NETDEV_IS_MY_V6ADDR(dev, ipv6->srcipaddr) && + !NETDEV_IS_MY_V6ADDR(dev, ipv6->destipaddr)) + { + FAR ipv6_nat_entry_t *entry = + ipv6_nat_outbound_internal(dev, ipv6, manip_type); + if (manip_type == NAT_MANIP_SRC && !entry) + { + /* Outbound entry creation failed, should have entry. */ + + return -ENOENT; + } + } + + return OK; +} + +#endif /* CONFIG_NET_NAT66 */ diff --git a/net/nat/ipv6_nat_entry.c b/net/nat/ipv6_nat_entry.c new file mode 100644 index 0000000000000..c8f8493faf9b2 --- /dev/null +++ b/net/nat/ipv6_nat_entry.c @@ -0,0 +1,471 @@ +/**************************************************************************** + * net/nat/ipv6_nat_entry.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include +#include +#include + +#include "inet/inet.h" +#include "nat/nat.h" +#include "netlink/netlink.h" + +#ifdef CONFIG_NET_NAT66 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static DECLARE_HASHTABLE(g_nat66_inbound, CONFIG_NET_NAT_HASH_BITS); +static DECLARE_HASHTABLE(g_nat66_outbound, CONFIG_NET_NAT_HASH_BITS); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ipv6_nat_hash_key + * + * Description: + * Create a hash key for NAT66. + * + ****************************************************************************/ + +static inline uint32_t ipv6_nat_hash_key(const net_ipv6addr_t ip, + uint16_t port, uint8_t protocol) +{ + uint32_t key = (((uint32_t)ip[0] << 16) | ip[1]) ^ + (((uint32_t)ip[2] << 16) | ip[3]) ^ + (((uint32_t)ip[4] << 16) | ip[5]) ^ + (((uint32_t)ip[6] << 16) | ip[7]); + + return key ^ ((uint32_t)protocol << 16) ^ port; +} + +/**************************************************************************** + * Name: ipv6_nat_entry_refresh + * + * Description: + * Refresh a NAT entry, update its expiration time. + * + * Input Parameters: + * entry - The entry to refresh. + * + ****************************************************************************/ + +static void ipv6_nat_entry_refresh(FAR ipv6_nat_entry_t *entry) +{ + entry->expire_time = nat_expire_time(entry->protocol); +} + +/**************************************************************************** + * Name: ipv6_nat_entry_create + * + * Description: + * Create a NAT entry and insert into entry list. + * + * Input Parameters: + * protocol - The L4 protocol of the packet. + * external_ip - The external ip of the packet. + * external_port - The external port of the packet. + * local_ip - The local ip of the packet. + * local_port - The local port of the packet. + * peer_ip - The peer ip of the packet. + * peer_port - The peer port of the packet. + * + * Returned Value: + * Pointer to entry on success; null on failure + * + ****************************************************************************/ + +static FAR ipv6_nat_entry_t * +ipv6_nat_entry_create(uint8_t protocol, const net_ipv6addr_t external_ip, + uint16_t external_port, const net_ipv6addr_t local_ip, + uint16_t local_port, const net_ipv6addr_t peer_ip, + uint16_t peer_port) +{ + FAR ipv6_nat_entry_t *entry = kmm_malloc(sizeof(ipv6_nat_entry_t)); + if (entry == NULL) + { + nwarn("WARNING: Failed to allocate IPv6 NAT entry\n"); + return NULL; + } + + entry->protocol = protocol; + entry->external_port = external_port; + entry->local_port = local_port; +#ifdef CONFIG_NET_NAT66_SYMMETRIC + entry->peer_port = peer_port; +#endif + net_ipv6addr_copy(entry->external_ip, external_ip); + net_ipv6addr_copy(entry->local_ip, local_ip); +#ifdef CONFIG_NET_NAT66_SYMMETRIC + net_ipv6addr_copy(entry->peer_ip, peer_ip); +#endif + + ipv6_nat_entry_refresh(entry); + + hashtable_add(g_nat66_inbound, &entry->hash_inbound, + ipv6_nat_hash_key(external_ip, external_port, protocol)); + hashtable_add(g_nat66_outbound, &entry->hash_outbound, + ipv6_nat_hash_key(local_ip, local_port, protocol)); + +#ifdef CONFIG_NETLINK_NETFILTER + netlink_conntrack_notify(IPCTNL_MSG_CT_NEW, PF_INET6, entry); +#endif + + return entry; +} + +/**************************************************************************** + * Name: ipv6_nat_entry_delete + * + * Description: + * Delete a NAT entry and remove from entry list. + * + * Input Parameters: + * entry - The entry to remove. + * + ****************************************************************************/ + +static void ipv6_nat_entry_delete(FAR ipv6_nat_entry_t *entry) +{ + ninfo("INFO: Removing NAT66 entry proto=%" PRIu8 + ", local=%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x:%" PRIu16 + ", external=:%" PRIu16 "\n", + entry->protocol, entry->local_ip[0], entry->local_ip[1], + entry->local_ip[2], entry->local_ip[3], entry->local_ip[4], + entry->local_ip[5], entry->local_ip[6], entry->local_ip[7], + entry->local_port, entry->external_port); + + hashtable_delete(g_nat66_inbound, &entry->hash_inbound, + ipv6_nat_hash_key(entry->external_ip, + entry->external_port, + entry->protocol)); + hashtable_delete(g_nat66_outbound, &entry->hash_outbound, + ipv6_nat_hash_key(entry->local_ip, + entry->local_port, + entry->protocol)); + +#ifdef CONFIG_NETLINK_NETFILTER + netlink_conntrack_notify(IPCTNL_MSG_CT_DELETE, PF_INET6, entry); +#endif + + kmm_free(entry); +} + +/**************************************************************************** + * Name: ipv6_nat_reclaim_entry + * + * Description: + * Try reclaim all expired NAT entries. + * Only works after every CONFIG_NET_NAT_ENTRY_RECLAIM_SEC (low frequency). + * + * Although expired entries will be automatically reclaimed when matching + * inbound/outbound entries, there might be some situations that entries + * will be kept in memory, e.g. big hashtable with only a few connections. + * + * Assumptions: + * NAT is initialized. + * + ****************************************************************************/ + +#if CONFIG_NET_NAT_ENTRY_RECLAIM_SEC > 0 +static void ipv6_nat_reclaim_entry_cb(FAR ipv6_nat_entry_t *entry, + FAR void *arg) +{ + int32_t current_time = *(FAR int32_t *)arg; + + if (entry->expire_time - current_time <= 0) + { + ipv6_nat_entry_delete(entry); + } +} + +static void ipv6_nat_reclaim_entry(int32_t current_time) +{ + static int32_t next_reclaim_time = CONFIG_NET_NAT_ENTRY_RECLAIM_SEC; + + if (next_reclaim_time - current_time <= 0) + { + ninfo("INFO: Reclaiming all expired NAT66 entries.\n"); + ipv6_nat_entry_foreach(ipv6_nat_reclaim_entry_cb, ¤t_time); + next_reclaim_time = current_time + CONFIG_NET_NAT_ENTRY_RECLAIM_SEC; + } +} +#else +# define ipv6_nat_reclaim_entry(t) +#endif + +/**************************************************************************** + * Name: ipv6_nat_entry_clear_cb + * + * Description: + * Clear an entry related to dev. Called when NAT will be disabled on + * any device. + * + ****************************************************************************/ + +static void ipv6_nat_entry_clear_cb(FAR ipv6_nat_entry_t *entry, + FAR void *arg) +{ + FAR struct net_driver_s *dev = arg; + + if (NETDEV_IS_MY_V6ADDR(dev, entry->external_ip)) + { + ipv6_nat_entry_delete(entry); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: ipv6_nat_entry_clear + * + * Description: + * Clear all entries related to dev. Called when NAT will be disabled on + * any device. + * + * Input Parameters: + * dev - The device on which NAT entries will be cleared. + * + * Assumptions: + * NAT is initialized. + * + ****************************************************************************/ + +void ipv6_nat_entry_clear(FAR struct net_driver_s *dev) +{ + ninfo("INFO: Clearing all NAT66 entries for %s\n", dev->d_ifname); + ipv6_nat_entry_foreach(ipv6_nat_entry_clear_cb, dev); +} + +/**************************************************************************** + * Name: ipv6_nat_entry_foreach + * + * Description: + * Call the callback function for each NAT entry. + * + * Input Parameters: + * cb - The callback function. + * arg - The argument to pass to the callback function. + * + ****************************************************************************/ + +void ipv6_nat_entry_foreach(ipv6_nat_entry_cb_t cb, FAR void *arg) +{ + FAR hash_node_t *p; + FAR hash_node_t *tmp; + int i; + + hashtable_for_every_safe(g_nat66_inbound, p, tmp, i) + { + FAR ipv6_nat_entry_t *entry = + container_of(p, ipv6_nat_entry_t, hash_inbound); + + cb(entry, arg); + } +} + +/**************************************************************************** + * Name: ipv6_nat_inbound_entry_find + * + * Description: + * Find the inbound entry in NAT entry list. + * + * Input Parameters: + * protocol - The L4 protocol of the packet. + * external_ip - The external ip of the packet, supports INADDR_ANY. + * external_port - The external port of the packet. + * peer_ip - The peer ip of the packet. + * peer_port - The peer port of the packet. + * refresh - Whether to refresh the selected entry. + * + * Returned Value: + * Pointer to entry on success; null on failure + * + ****************************************************************************/ + +FAR ipv6_nat_entry_t * +ipv6_nat_inbound_entry_find(uint8_t protocol, + const net_ipv6addr_t external_ip, + uint16_t external_port, + const net_ipv6addr_t peer_ip, + uint16_t peer_port, bool refresh) +{ + FAR hash_node_t *p; + FAR hash_node_t *tmp; + bool skip_ip = net_ipv6addr_cmp(external_ip, g_ipv6_unspecaddr); +#ifdef CONFIG_NET_NAT66_SYMMETRIC + bool skip_peer = net_ipv6addr_cmp(peer_ip, g_ipv6_unspecaddr); +#endif + int32_t current_time = TICK2SEC(clock_systime_ticks()); + + ipv6_nat_reclaim_entry(current_time); + + hashtable_for_every_possible_safe(g_nat66_inbound, p, tmp, + ipv6_nat_hash_key(external_ip, external_port, protocol)) + { + FAR ipv6_nat_entry_t *entry = + container_of(p, ipv6_nat_entry_t, hash_inbound); + + /* Remove expired entries. */ + + if (entry->expire_time - current_time <= 0) + { + ipv6_nat_entry_delete(entry); + continue; + } + + if (entry->protocol == protocol && + (skip_ip || net_ipv6addr_cmp(entry->external_ip, external_ip)) && + entry->external_port == external_port +#ifdef CONFIG_NET_NAT66_SYMMETRIC + && (skip_peer || (net_ipv6addr_cmp(entry->peer_ip, peer_ip) && + entry->peer_port == peer_port)) +#endif + ) + { + if (refresh) + { + ipv6_nat_entry_refresh(entry); + } + + return entry; + } + } + + if (refresh) /* false = a test of whether entry exists, no need to warn */ + { + nwarn("WARNING: Failed to find IPv6 inbound NAT entry for proto=" + "%" PRIu8 ",external=[%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x]:" + "%" PRIu16 "\n", + protocol, external_ip[0], external_ip[1], external_ip[2], + external_ip[3], external_ip[4], external_ip[5], external_ip[6], + external_ip[7], external_port); + } + + return NULL; +} + +/**************************************************************************** + * Name: ipv6_nat_outbound_entry_find + * + * Description: + * Find the outbound entry in NAT entry list. Create one if corresponding + * entry does not exist. + * + * Input Parameters: + * dev - The device on which the packet will be sent. + * protocol - The L4 protocol of the packet. + * local_ip - The local ip of the packet. + * local_port - The local port of the packet. + * peer_ip - The peer ip of the packet. + * peer_port - The peer port of the packet. + * try_create - Try create the entry if no entry found. + * + * Returned Value: + * Pointer to entry on success; null on failure + * + ****************************************************************************/ + +FAR ipv6_nat_entry_t * +ipv6_nat_outbound_entry_find(FAR struct net_driver_s *dev, uint8_t protocol, + const net_ipv6addr_t local_ip, + uint16_t local_port, + const net_ipv6addr_t peer_ip, + uint16_t peer_port, bool try_create) +{ + FAR hash_node_t *p; + FAR hash_node_t *tmp; + FAR union ip_addr_u *external_ip; + uint16_t external_port; + int32_t current_time = TICK2SEC(clock_systime_ticks()); + + ipv6_nat_reclaim_entry(current_time); + + hashtable_for_every_possible_safe(g_nat66_outbound, p, tmp, + ipv6_nat_hash_key(local_ip, local_port, protocol)) + { + FAR ipv6_nat_entry_t *entry = + container_of(p, ipv6_nat_entry_t, hash_outbound); + + /* Remove expired entries. */ + + if (entry->expire_time - current_time <= 0) + { + ipv6_nat_entry_delete(entry); + continue; + } + + if (entry->protocol == protocol && + NETDEV_IS_MY_V6ADDR(dev, entry->external_ip) && + net_ipv6addr_cmp(entry->local_ip, local_ip) && + entry->local_port == local_port +#ifdef CONFIG_NET_NAT66_SYMMETRIC + && net_ipv6addr_cmp(entry->peer_ip, peer_ip) && + entry->peer_port == peer_port +#endif + ) + { + ipv6_nat_entry_refresh(entry); + return entry; + } + } + + if (!try_create) + { + return NULL; + } + + /* Failed to find the entry, create one. */ + + ninfo("INFO: Failed to find IPv6 outbound NAT entry for proto=%" PRIu8 + ", local=[%04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x]:%" PRIu16 + ", try create one.\n", + protocol, local_ip[0], local_ip[1], local_ip[2], local_ip[3], + local_ip[4], local_ip[5], local_ip[6], local_ip[7], local_port); + + external_ip = (FAR union ip_addr_u *)netdev_ipv6_srcaddr(dev, peer_ip); + external_port = nat_port_select(dev, PF_INET6, protocol, + external_ip, local_port); + + if (!external_port) + { + nwarn("WARNING: Failed to find an available port!\n"); + return NULL; + } + + return ipv6_nat_entry_create(protocol, external_ip->ipv6, external_port, + local_ip, local_port, peer_ip, peer_port); +} + +#endif /* CONFIG_NET_NAT66 */ diff --git a/net/nat/nat.c b/net/nat/nat.c new file mode 100644 index 0000000000000..454efd516bb6b --- /dev/null +++ b/net/nat/nat.c @@ -0,0 +1,404 @@ +/**************************************************************************** + * net/nat/nat.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "icmp/icmp.h" +#include "icmpv6/icmpv6.h" +#include "inet/inet.h" +#include "nat/nat.h" +#include "tcp/tcp.h" +#include "udp/udp.h" +#include "utils/utils.h" + +#ifdef CONFIG_NET_NAT + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nat_port_select_without_stack + * + * Description: + * Select an available port number for TCP/UDP protocol, or id for ICMP. + * Used when corresponding stack is disabled. + * + * Input Parameters: + * domain - The domain of the packet. + * protocol - The L4 protocol of the packet. + * ip - The IP bind with the port (in network byte order). + * local_port - The local port (in network byte order), as reference. + * + * Returned Value: + * port number on success; 0 on failure + * + ****************************************************************************/ + +#if (defined(CONFIG_NET_TCP) && defined(CONFIG_NET_TCP_NO_STACK)) || \ + (defined(CONFIG_NET_UDP) && defined(CONFIG_NET_UDP_NO_STACK)) || \ + (defined(CONFIG_NET_ICMP) && !defined(CONFIG_NET_ICMP_SOCKET)) || \ + (defined(CONFIG_NET_ICMPv6) && !defined(CONFIG_NET_ICMPv6_SOCKET)) + +static uint16_t nat_port_select_without_stack( + uint8_t domain, uint8_t protocol, FAR const union ip_addr_u *ip, + uint16_t local_port) +{ + uint16_t portno = local_port; + uint16_t hport = NTOHS(portno); + while (nat_port_inuse(domain, protocol, ip, portno)) + { + NET_PORT_NEXT_NH(portno, hport); + if (portno == local_port) + { + /* We have looped back, failed. */ + + return 0; + } + } + + return portno; +} + +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nat_enable + * + * Description: + * Enable NAT function on a network device. + * + * Input Parameters: + * dev - The device on which the outbound packets will be masqueraded. + * + * Returned Value: + * Zero is returned if NAT function is successfully enabled on the device; + * A negated errno value is returned if failed. + * + ****************************************************************************/ + +int nat_enable(FAR struct net_driver_s *dev) +{ + net_lock(); + + if (IFF_IS_NAT(dev->d_flags)) + { + nwarn("WARNING: NAT was already enabled for %s!\n", dev->d_ifname); + net_unlock(); + return -EEXIST; + } + + IFF_SET_NAT(dev->d_flags); + + net_unlock(); + return OK; +} + +/**************************************************************************** + * Name: nat_disable + * + * Description: + * Disable NAT function on a network device. + * + * Input Parameters: + * dev - The device on which the NAT function will be disabled. + * + * Returned Value: + * Zero is returned if NAT function is successfully disabled on the device; + * A negated errno value is returned if failed. + * + ****************************************************************************/ + +int nat_disable(FAR struct net_driver_s *dev) +{ + net_lock(); + + if (!IFF_IS_NAT(dev->d_flags)) + { + nwarn("WARNING: NAT was not enabled for %s!\n", dev->d_ifname); + net_unlock(); + return -ENODEV; + } + + /* Clear entries related to dev. */ + +#ifdef CONFIG_NET_NAT44 + ipv4_nat_entry_clear(dev); +#endif +#ifdef CONFIG_NET_NAT66 + ipv6_nat_entry_clear(dev); +#endif + + IFF_CLR_NAT(dev->d_flags); + + net_unlock(); + return OK; +} + +/**************************************************************************** + * Name: nat_port_inuse + * + * Description: + * Check whether a port is currently used by NAT. + * + * Input Parameters: + * domain - The domain of the packet. + * protocol - The L4 protocol of the packet. + * ip - The IP bind with the port (in network byte order). + * port - The port number to check (in network byte order). + * + * Returned Value: + * True if the port is already used by NAT, otherwise false. + * + ****************************************************************************/ + +bool nat_port_inuse(uint8_t domain, uint8_t protocol, + FAR const union ip_addr_u *ip, uint16_t port) +{ +#ifdef CONFIG_NET_NAT44 + if (domain == PF_INET) + { + return !!ipv4_nat_inbound_entry_find(protocol, ip->ipv4, port, + INADDR_ANY, 0, false); + } +#endif + +#ifdef CONFIG_NET_NAT66 + if (domain == PF_INET6) + { + return !!ipv6_nat_inbound_entry_find(protocol, ip->ipv6, port, + g_ipv6_unspecaddr, 0, false); + } +#endif + + return false; +} + +/**************************************************************************** + * Name: nat_port_select + * + * Description: + * Select an available port number for TCP/UDP protocol, or id for ICMP. + * + * Input Parameters: + * dev - The device on which the packet will be sent. + * domain - The domain of the packet. + * protocol - The L4 protocol of the packet. + * external_ip - The external IP bind with the port. + * local_port - The local port of the packet, as reference. + * + * Returned Value: + * External port number on success; 0 on failure + * + ****************************************************************************/ + +uint16_t nat_port_select(FAR struct net_driver_s *dev, + uint8_t domain, uint8_t protocol, + FAR const union ip_addr_u *external_ip, + uint16_t local_port) +{ + switch (protocol) + { +#ifdef CONFIG_NET_TCP + case IP_PROTO_TCP: + { +#ifndef CONFIG_NET_TCP_NO_STACK + /* Try to select local_port first. */ + + int ret = tcp_selectport(domain, external_ip, local_port); + + /* If failed, try select another unused port. */ + + if (ret < 0) + { + ret = tcp_selectport(domain, external_ip, 0); + } + + return ret > 0 ? ret : 0; +#else + return nat_port_select_without_stack(domain, IP_PROTO_TCP, + external_ip, local_port); +#endif + } +#endif + +#ifdef CONFIG_NET_UDP + case IP_PROTO_UDP: + { +#ifndef CONFIG_NET_UDP_NO_STACK + union ip_binding_u u; + +#ifdef CONFIG_NET_IPv4 +#ifdef CONFIG_NET_IPv6 + if (domain == PF_INET) +#endif + { + u.ipv4.laddr = external_ip->ipv4; + u.ipv4.raddr = INADDR_ANY; + } +#endif +#ifdef CONFIG_NET_IPv6 +#ifdef CONFIG_NET_IPv4 + else +#endif + { + net_ipv6addr_copy(u.ipv6.laddr, external_ip->ipv6); + net_ipv6addr_copy(u.ipv6.raddr, g_ipv6_unspecaddr); + } +#endif + + /* TODO: Try keep origin port as possible. */ + + return HTONS(udp_select_port(domain, &u)); +#else + return nat_port_select_without_stack(domain, IP_PROTO_UDP, + external_ip, local_port); +#endif + } +#endif + +#ifdef CONFIG_NET_ICMP + case IP_PROTO_ICMP: + { +#ifdef CONFIG_NET_ICMP_SOCKET + uint16_t id = local_port; + uint16_t hid = NTOHS(id); + while (icmp_findconn(dev, id) || + nat_port_inuse(domain, IP_PROTO_ICMP, external_ip, id)) + { + NET_PORT_NEXT_NH(id, hid); + if (id == local_port) + { + /* We have looped back, failed. */ + + return 0; + } + } + + return id; +#else + return nat_port_select_without_stack(domain, IP_PROTO_ICMP, + external_ip, local_port); +#endif + } +#endif + +#ifdef CONFIG_NET_ICMPv6 + case IP_PROTO_ICMP6: + { +#ifdef CONFIG_NET_ICMPv6_SOCKET + uint16_t id = local_port; + uint16_t hid = NTOHS(id); + while (icmpv6_active(id) || + nat_port_inuse(domain, IP_PROTO_ICMP6, external_ip, id)) + { + NET_PORT_NEXT_NH(id, hid); + if (id == local_port) + { + /* We have looped back, failed. */ + + return 0; + } + } + + return id; +#else + return nat_port_select_without_stack(domain, IP_PROTO_ICMP6, + external_ip, local_port); +#endif + } +#endif + } + + /* Select original port for unsupported protocol. */ + + return local_port; +} + +/**************************************************************************** + * Name: nat_expire_time + * + * Description: + * Get the expiration time of a specific protocol. + * + * Input Parameters: + * protocol - The L4 protocol of the packet. + * + * Returned Value: + * The expiration time of the protocol. + * + ****************************************************************************/ + +uint32_t nat_expire_time(uint8_t protocol) +{ + /* Note: May add logic here to move recent node to head side if each chain + * in hashtable is still too long (with long expire time). + */ + + switch (protocol) + { +#ifdef CONFIG_NET_TCP + case IP_PROTO_TCP: + /* NOTE: According to RFC2663, Section 2.6, Page 5, we can reduce the + * time to 4min if we have received FINs from both side of one + * connection, and keep 24h for other TCP connections. However, full + * cone NAT may have multiple connections on one entry, so this + * optimization may not work and we only use one expiration time. + */ + + return TICK2SEC(clock_systime_ticks()) + + CONFIG_NET_NAT_TCP_EXPIRE_SEC; +#endif + +#ifdef CONFIG_NET_UDP + case IP_PROTO_UDP: + return TICK2SEC(clock_systime_ticks()) + + CONFIG_NET_NAT_UDP_EXPIRE_SEC; +#endif + +#ifdef CONFIG_NET_ICMP + case IP_PROTO_ICMP: + return TICK2SEC(clock_systime_ticks()) + + CONFIG_NET_NAT_ICMP_EXPIRE_SEC; +#endif + +#ifdef CONFIG_NET_ICMPv6 + case IP_PROTO_ICMP6: + return TICK2SEC(clock_systime_ticks()) + + CONFIG_NET_NAT_ICMPv6_EXPIRE_SEC; +#endif + + default: + nwarn("WARNING: Unsupported protocol %" PRIu8 "\n", protocol); + return 0; + } +} + +#endif /* CONFIG_NET_NAT */ diff --git a/net/nat/nat.h b/net/nat/nat.h index 4c70ceeb95e97..4ef2d40e8033f 100644 --- a/net/nat/nat.h +++ b/net/nat/nat.h @@ -36,13 +36,39 @@ #include #include -#if defined(CONFIG_NET_NAT) && defined(CONFIG_NET_IPv4) +#ifdef CONFIG_NET_NAT + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Adjust checksums in headers. */ + +#define nat_chksum_adjust(chksum,optr,nptr,len) \ + net_chksum_adjust((FAR uint16_t *)(chksum), (FAR uint16_t *)(optr), len, \ + (FAR uint16_t *)(nptr), len) + +/* Getting IP & Port to manipulate from L3/L4 header. */ + +#define MANIP_IPADDR(iphdr,manip_type) \ + ((manip_type) == NAT_MANIP_SRC ? (iphdr)->srcipaddr : (iphdr)->destipaddr) + +#define MANIP_PORT(l4hdr,manip_type) \ + ((manip_type) == NAT_MANIP_SRC ? &(l4hdr)->srcport : &(l4hdr)->destport) + +/* Getting peer IP & Port (just other than MANIP) */ + +#define PEER_IPADDR(iphdr,manip_type) \ + ((manip_type) != NAT_MANIP_SRC ? (iphdr)->srcipaddr : (iphdr)->destipaddr) + +#define PEER_PORT(l4hdr,manip_type) \ + ((manip_type) != NAT_MANIP_SRC ? &(l4hdr)->srcport : &(l4hdr)->destport) /**************************************************************************** * Public Types ****************************************************************************/ -struct ipv4_nat_entry +struct ipv4_nat_entry_s { hash_node_t hash_inbound; hash_node_t hash_outbound; @@ -55,18 +81,53 @@ struct ipv4_nat_entry * |----------------| * * Full cone NAT only need to save local ip:port and external ip:port. + * Symmetric NAT need to save peer ip:port as well. * For ICMP, save id in port field. */ in_addr_t local_ip; /* IP address of the local (private) host. */ in_addr_t external_ip; /* External IP address. */ +#ifdef CONFIG_NET_NAT44_SYMMETRIC + in_addr_t peer_ip; /* Peer IP address. */ +#endif uint16_t local_port; /* Port of the local (private) host. */ uint16_t external_port; /* The external port of local (private) host. */ +#ifdef CONFIG_NET_NAT44_SYMMETRIC + uint16_t peer_port; /* Peer port. */ +#endif uint8_t protocol; /* L4 protocol (TCP, UDP etc). */ int32_t expire_time; /* The expiration time of this entry. */ }; +struct ipv6_nat_entry_s +{ + hash_node_t hash_inbound; + hash_node_t hash_outbound; + + net_ipv6addr_t local_ip; /* IP address of the local host. */ + net_ipv6addr_t external_ip; /* External IP address. */ +#ifdef CONFIG_NET_NAT66_SYMMETRIC + net_ipv6addr_t peer_ip; /* Peer IP address. */ +#endif + uint16_t local_port; /* Port of the local host. */ + uint16_t external_port; /* The external port of local host. */ +#ifdef CONFIG_NET_NAT66_SYMMETRIC + uint16_t peer_port; /* Peer port. */ +#endif + uint8_t protocol; /* L4 protocol (TCP, UDP etc). */ + + int32_t expire_time; /* The expiration time of this entry. */ +}; + +typedef struct ipv4_nat_entry_s ipv4_nat_entry_t; +typedef struct ipv6_nat_entry_s ipv6_nat_entry_t; + +typedef CODE void (*ipv4_nat_entry_cb_t)(FAR ipv4_nat_entry_t *entry, + FAR void *arg); +typedef CODE void (*ipv6_nat_entry_cb_t)(FAR ipv6_nat_entry_t *entry, + FAR void *arg); + /* NAT IP/Port manipulate type, to indicate whether to manipulate source or * destination IP/Port in a packet. */ @@ -82,7 +143,7 @@ enum nat_manip_type_e ****************************************************************************/ /**************************************************************************** - * Name: ipv4_nat_enable + * Name: nat_enable * * Description: * Enable NAT function on a network device. @@ -96,10 +157,10 @@ enum nat_manip_type_e * ****************************************************************************/ -int ipv4_nat_enable(FAR struct net_driver_s *dev); +int nat_enable(FAR struct net_driver_s *dev); /**************************************************************************** - * Name: ipv4_nat_disable + * Name: nat_disable * * Description: * Disable NAT function on a network device. @@ -113,38 +174,39 @@ int ipv4_nat_enable(FAR struct net_driver_s *dev); * ****************************************************************************/ -int ipv4_nat_disable(FAR struct net_driver_s *dev); +int nat_disable(FAR struct net_driver_s *dev); /**************************************************************************** - * Name: ipv4_nat_inbound + * Name: ipv4/ipv6_nat_inbound * * Description: * Check if a received packet belongs to a NAT entry. If so, translate it. * * Input Parameters: - * dev - The device on which the packet is received. - * ipv4 - Points to the IPv4 header with dev->d_buf. - * - * Returned Value: - * Zero is returned if NAT is successfully applied, or is not enabled for - * this packet; - * A negated errno value is returned if error occured. + * dev - The device on which the packet is received. + * ipv4/ipv6 - Points to the IP header with dev->d_buf. * ****************************************************************************/ -int ipv4_nat_inbound(FAR struct net_driver_s *dev, - FAR struct ipv4_hdr_s *ipv4); +#ifdef CONFIG_NET_NAT44 +void ipv4_nat_inbound(FAR struct net_driver_s *dev, + FAR struct ipv4_hdr_s *ipv4); +#endif +#ifdef CONFIG_NET_NAT66 +void ipv6_nat_inbound(FAR struct net_driver_s *dev, + FAR struct ipv6_hdr_s *ipv6); +#endif /**************************************************************************** - * Name: ipv4_nat_outbound + * Name: ipv4/ipv6_nat_outbound * * Description: * Check if we want to perform NAT with this outbound packet before sending * it. If so, translate it. * * Input Parameters: - * dev - The device on which the packet will be sent. - * ipv4 - Points to the IPv4 header to be filled into dev->d_buf later. + * dev - The device on which the packet will be sent. + * ipv4/ipv6 - Points to the IP header to be filled into dev->d_buf later. * manip_type - Whether local IP/Port is in source or destination. * * Returned Value: @@ -154,17 +216,25 @@ int ipv4_nat_inbound(FAR struct net_driver_s *dev, * ****************************************************************************/ +#ifdef CONFIG_NET_NAT44 int ipv4_nat_outbound(FAR struct net_driver_s *dev, FAR struct ipv4_hdr_s *ipv4, enum nat_manip_type_e manip_type); +#endif +#ifdef CONFIG_NET_NAT66 +int ipv6_nat_outbound(FAR struct net_driver_s *dev, + FAR struct ipv6_hdr_s *ipv6, + enum nat_manip_type_e manip_type); +#endif /**************************************************************************** - * Name: ipv4_nat_port_inuse + * Name: nat_port_inuse * * Description: * Check whether a port is currently used by NAT. * * Input Parameters: + * domain - The domain of the packet. * protocol - The L4 protocol of the packet. * ip - The IP bind with the port (in network byte order). * port - The port number to check (in network byte order). @@ -174,27 +244,91 @@ int ipv4_nat_outbound(FAR struct net_driver_s *dev, * ****************************************************************************/ -bool ipv4_nat_port_inuse(uint8_t protocol, in_addr_t ip, uint16_t port); +bool nat_port_inuse(uint8_t domain, uint8_t protocol, + FAR const union ip_addr_u *ip, uint16_t port); /**************************************************************************** - * Name: ipv4_nat_entry_clear + * Name: nat_port_select + * + * Description: + * Select an available port number for TCP/UDP protocol, or id for ICMP. + * + * Input Parameters: + * dev - The device on which the packet will be sent. + * domain - The domain of the packet. + * protocol - The L4 protocol of the packet. + * external_ip - The external IP bind with the port. + * local_port - The local port of the packet, as reference. + * + * Returned Value: + * External port number on success; 0 on failure + * + ****************************************************************************/ + +uint16_t nat_port_select(FAR struct net_driver_s *dev, + uint8_t domain, uint8_t protocol, + FAR const union ip_addr_u *external_ip, + uint16_t local_port); + +/**************************************************************************** + * Name: nat_expire_time + * + * Description: + * Get the expiration time of a specific protocol. + * + * Input Parameters: + * protocol - The L4 protocol of the packet. + * + * Returned Value: + * The expiration time of the protocol. + * + ****************************************************************************/ + +uint32_t nat_expire_time(uint8_t protocol); + +/**************************************************************************** + * Name: ipv4/ipv6_nat_entry_foreach + * + * Description: + * Call the callback function for each NAT entry. + * + * Input Parameters: + * cb - The callback function. + * arg - The argument to pass to the callback function. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NAT44 +void ipv4_nat_entry_foreach(ipv4_nat_entry_cb_t cb, FAR void *arg); +#endif +#ifdef CONFIG_NET_NAT66 +void ipv6_nat_entry_foreach(ipv6_nat_entry_cb_t cb, FAR void *arg); +#endif + +/**************************************************************************** + * Name: ipv4/ipv6_nat_entry_clear * * Description: * Clear all entries related to dev. Called when NAT will be disabled on * any device. * * Input Parameters: - * dev - The device on which NAT entries will be cleared. + * dev - The device on which NAT entries will be cleared. * * Assumptions: * NAT is initialized. * ****************************************************************************/ +#ifdef CONFIG_NET_NAT44 void ipv4_nat_entry_clear(FAR struct net_driver_s *dev); +#endif +#ifdef CONFIG_NET_NAT66 +void ipv6_nat_entry_clear(FAR struct net_driver_s *dev); +#endif /**************************************************************************** - * Name: ipv4_nat_inbound_entry_find + * Name: ipv4/ipv6_nat_inbound_entry_find * * Description: * Find the inbound entry in NAT entry list. @@ -203,6 +337,8 @@ void ipv4_nat_entry_clear(FAR struct net_driver_s *dev); * protocol - The L4 protocol of the packet. * external_ip - The external ip of the packet, supports INADDR_ANY. * external_port - The external port of the packet. + * peer_ip - The peer ip of the packet. + * peer_port - The peer port of the packet. * refresh - Whether to refresh the selected entry. * * Returned Value: @@ -210,12 +346,23 @@ void ipv4_nat_entry_clear(FAR struct net_driver_s *dev); * ****************************************************************************/ -FAR struct ipv4_nat_entry * +#ifdef CONFIG_NET_NAT44 +FAR ipv4_nat_entry_t * ipv4_nat_inbound_entry_find(uint8_t protocol, in_addr_t external_ip, - uint16_t external_port, bool refresh); + uint16_t external_port, in_addr_t peer_ip, + uint16_t peer_port, bool refresh); +#endif +#ifdef CONFIG_NET_NAT66 +FAR ipv6_nat_entry_t * +ipv6_nat_inbound_entry_find(uint8_t protocol, + const net_ipv6addr_t external_ip, + uint16_t external_port, + const net_ipv6addr_t peer_ip, + uint16_t peer_port, bool refresh); +#endif /**************************************************************************** - * Name: ipv4_nat_outbound_entry_find + * Name: ipv4/ipv6_nat_outbound_entry_find * * Description: * Find the outbound entry in NAT entry list. Create one if corresponding @@ -226,6 +373,8 @@ ipv4_nat_inbound_entry_find(uint8_t protocol, in_addr_t external_ip, * protocol - The L4 protocol of the packet. * local_ip - The local ip of the packet. * local_port - The local port of the packet. + * peer_ip - The peer ip of the packet. + * peer_port - The peer port of the packet. * try_create - Try create the entry if no entry found. * * Returned Value: @@ -233,10 +382,21 @@ ipv4_nat_inbound_entry_find(uint8_t protocol, in_addr_t external_ip, * ****************************************************************************/ -FAR struct ipv4_nat_entry * +#ifdef CONFIG_NET_NAT44 +FAR ipv4_nat_entry_t * ipv4_nat_outbound_entry_find(FAR struct net_driver_s *dev, uint8_t protocol, in_addr_t local_ip, uint16_t local_port, + in_addr_t peer_ip, uint16_t peer_port, bool try_create); - -#endif /* CONFIG_NET_NAT && CONFIG_NET_IPv4 */ +#endif +#ifdef CONFIG_NET_NAT66 +FAR ipv6_nat_entry_t * +ipv6_nat_outbound_entry_find(FAR struct net_driver_s *dev, uint8_t protocol, + const net_ipv6addr_t local_ip, + uint16_t local_port, + const net_ipv6addr_t peer_ip, + uint16_t peer_port, bool try_create); +#endif + +#endif /* CONFIG_NET_NAT */ #endif /* __NET_NAT_NAT_H */ diff --git a/net/neighbor/neighbor_add.c b/net/neighbor/neighbor_add.c index c66185c0b8386..6257f6abb2087 100644 --- a/net/neighbor/neighbor_add.c +++ b/net/neighbor/neighbor_add.c @@ -36,6 +36,7 @@ #include #include "netdev/netdev.h" +#include "netlink/netlink.h" #include "neighbor/neighbor.h" /**************************************************************************** @@ -65,6 +66,8 @@ void neighbor_add(FAR struct net_driver_s *dev, FAR net_ipv6addr_t ipaddr, uint8_t lltype; clock_t oldest_time; int oldest_ndx; + bool found = false; + bool new_entry; int i; DEBUGASSERT(dev != NULL && addr != NULL); @@ -85,6 +88,7 @@ void neighbor_add(FAR struct net_driver_s *dev, FAR net_ipv6addr_t ipaddr, net_ipv6addr_cmp(g_neighbors[i].ne_ipaddr, ipaddr)) { oldest_ndx = i; + found = true; break; } @@ -95,10 +99,24 @@ void neighbor_add(FAR struct net_driver_s *dev, FAR net_ipv6addr_t ipaddr, } } + /* When overwite old entry, need to notify RTM_DELNEIGH */ + + if (!found && g_neighbors[oldest_ndx].ne_time != 0) + { + netlink_neigh_notify(&g_neighbors[oldest_ndx], RTM_DELNEIGH, + AF_INET6); + } + + /* Need to notify when entry is not found or changes in table */ + + new_entry = !found || memcmp(&g_neighbors[oldest_ndx].ne_addr.u, addr, + g_neighbors[oldest_ndx].ne_addr.na_llsize) != 0; + /* Use the oldest or first free entry (either pointed to by the * "oldest_ndx" variable). */ + g_neighbors[oldest_ndx].ne_dev = dev; g_neighbors[oldest_ndx].ne_time = clock_systime_ticks(); net_ipv6addr_copy(g_neighbors[oldest_ndx].ne_ipaddr, ipaddr); @@ -108,6 +126,14 @@ void neighbor_add(FAR struct net_driver_s *dev, FAR net_ipv6addr_t ipaddr, memcpy(&g_neighbors[oldest_ndx].ne_addr.u, addr, g_neighbors[oldest_ndx].ne_addr.na_llsize); + /* Notify the new entry */ + + if (new_entry) + { + netlink_neigh_notify(&g_neighbors[oldest_ndx], RTM_NEWNEIGH, + AF_INET6); + } + /* Dump the contents of the new entry */ neighbor_dumpentry("Added entry", &g_neighbors[oldest_ndx]); diff --git a/net/netdev/netdev_findbyaddr.c b/net/netdev/netdev_findbyaddr.c index 35cb6c705484f..bfe5745d9b8f4 100644 --- a/net/netdev/netdev_findbyaddr.c +++ b/net/netdev/netdev_findbyaddr.c @@ -25,6 +25,7 @@ #include #include +#include #include #include #include @@ -34,6 +35,8 @@ #include #include +#include "arp/arp.h" +#include "neighbor/neighbor.h" #include "utils/utils.h" #include "devif/devif.h" #include "inet/inet.h" @@ -41,11 +44,11 @@ #include "netdev/netdev.h" /**************************************************************************** - * Public Functions + * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: netdev_findby_lipv4addr + * Name: netdev_prefixlen_findby_lipv4addr * * Description: * Find a previously registered network device by matching a local address @@ -55,6 +58,7 @@ * Input Parameters: * lipaddr - Local, IPv4 address assigned to the network device. Or any * IPv4 address on the sub-net served by the network device. + * prefixlen - The length of matching prefix. Range: -1(no match) ~ 32 * * Returned Value: * Pointer to driver on success; null on failure @@ -62,9 +66,15 @@ ****************************************************************************/ #ifdef CONFIG_NET_IPv4 -FAR struct net_driver_s *netdev_findby_lipv4addr(in_addr_t lipaddr) +static FAR struct net_driver_s * +netdev_prefixlen_findby_lipv4addr(in_addr_t lipaddr, FAR int8_t *prefixlen) { FAR struct net_driver_s *dev; + FAR struct net_driver_s *bestdev = NULL; + int8_t bestpref = -1; +#ifdef CONFIG_ROUTE_LONGEST_MATCH + int8_t len; +#endif /* Examine each registered network device */ @@ -76,6 +86,7 @@ FAR struct net_driver_s *netdev_findby_lipv4addr(in_addr_t lipaddr) if ((dev->d_flags & IFF_UP) != 0 && !net_ipv4addr_cmp(dev->d_ipaddr, INADDR_ANY)) { +#ifndef CONFIG_ROUTE_LONGEST_MATCH /* Yes.. check for an address match (under the netmask) */ if (net_ipv4addr_maskcmp(dev->d_ipaddr, lipaddr, @@ -83,21 +94,58 @@ FAR struct net_driver_s *netdev_findby_lipv4addr(in_addr_t lipaddr) { /* Its a match */ - net_unlock(); - return dev; + bestdev = dev; + bestpref = 32; /* Regard as best (exact) match */ + break; + } +#else + /* Longest prefix flow: First, check for an exact address match */ + + if (net_ipv4addr_cmp(dev->d_ipaddr, lipaddr)) + { + /* It's an exact match */ + + bestdev = dev; + bestpref = 32; + break; + } + + /* Then, check for an address match (under the netmask) */ + + if (net_ipv4addr_maskcmp(dev->d_ipaddr, lipaddr, + dev->d_netmask)) + { + len = (int8_t)net_ipv4_mask2pref(dev->d_netmask); + + /* Regard current device as better if: + * 1. It has longer prefix length + * 2. It has the same prefix length but it has target address + * in the ARP cache (We don't have other information + * for the precedence of networks) + */ + + if (len > bestpref +#ifdef CONFIG_NET_ARP + || (len == bestpref && arp_find(lipaddr, NULL, dev) == OK) +#endif + ) + { + bestdev = dev; + bestpref = len; + } } +#endif /* CONFIG_ROUTE_LONGEST_MATCH */ } } - /* No device with the matching address found */ - net_unlock(); - return NULL; + *prefixlen = bestpref; + return bestdev; } #endif /* CONFIG_NET_IPv4 */ /**************************************************************************** - * Name: netdev_findby_lipv6addr + * Name: netdev_prefixlen_findby_lipv6addr * * Description: * Find a previously registered network device by matching a local address @@ -107,6 +155,7 @@ FAR struct net_driver_s *netdev_findby_lipv4addr(in_addr_t lipaddr) * Input Parameters: * lipaddr - Local, IPv6 address assigned to the network device. Or any * IPv6 address on the sub-net served by the network device. + * prefixlen - The length of matching prefix. Range: -1(no match) ~ 128 * * Returned Value: * Pointer to driver on success; null on failure @@ -114,36 +163,143 @@ FAR struct net_driver_s *netdev_findby_lipv4addr(in_addr_t lipaddr) ****************************************************************************/ #ifdef CONFIG_NET_IPv6 -FAR struct net_driver_s *netdev_findby_lipv6addr( - const net_ipv6addr_t lipaddr) +static FAR struct net_driver_s * +netdev_prefixlen_findby_lipv6addr(const net_ipv6addr_t lipaddr, + FAR int16_t *prefixlen) { FAR struct net_driver_s *dev; + FAR struct net_driver_s *bestdev = NULL; + int16_t bestpref = -1; +#ifdef CONFIG_ROUTE_LONGEST_MATCH + FAR struct netdev_ifaddr6_s *ifaddr6; + FAR struct neighbor_entry_s *ne; + FAR struct net_driver_s *hint; + int16_t len; +#endif + + net_lock(); + +#ifdef CONFIG_ROUTE_LONGEST_MATCH + /* Find a hint from neighbor table in case same prefix length exists on + * multiple devices. + */ + + ne = neighbor_findentry(lipaddr); + hint = ne ? ne->ne_dev : NULL; +#endif /* Examine each registered network device */ - net_lock(); for (dev = g_netdevices; dev; dev = dev->flink) { /* Is the interface in the "up" state? */ if ((dev->d_flags & IFF_UP) != 0 && NETDEV_HAS_V6ADDR(dev)) { +#ifndef CONFIG_ROUTE_LONGEST_MATCH /* Yes.. check for an address match (under the netmask) */ if (NETDEV_V6ADDR_ONLINK(dev, lipaddr)) { /* Its a match */ - net_unlock(); - return dev; + bestdev = dev; + bestpref = 128; /* Regard as best (exact) match */ + break; } +#else + /* Longest prefix flow: First, check for an exact address match */ + + if (NETDEV_IS_MY_V6ADDR(dev, lipaddr)) + { + /* It's an exact match */ + + bestdev = dev; + bestpref = 128; + break; + } + + /* Then, check for an address match (under the netmask) */ + + if ((ifaddr6 = netdev_ipv6_lookup(dev, lipaddr, true)) != NULL) + { + len = (int16_t)net_ipv6_mask2pref(ifaddr6->mask); + + /* Regard current device as better if: + * 1. It has longer prefix length + * 2. It has the same prefix length but it has target address + * in the neighbor cache (We don't have other information + * for the precedence of networks) + */ + + if (len > bestpref || (len == bestpref && hint == dev)) + { + bestdev = dev; + bestpref = len; + } + } +#endif /* CONFIG_ROUTE_LONGEST_MATCH */ } } - /* No device with the matching address found */ - net_unlock(); - return NULL; + *prefixlen = bestpref; + return bestdev; +} +#endif /* CONFIG_NET_IPv6 */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: netdev_findby_lipv4addr + * + * Description: + * Find a previously registered network device by matching a local address + * with the subnet served by the device. Only "up" devices are considered + * (since a "down" device has no meaningful address). + * + * Input Parameters: + * lipaddr - Local, IPv4 address assigned to the network device. Or any + * IPv4 address on the sub-net served by the network device. + * + * Returned Value: + * Pointer to driver on success; null on failure + * + ****************************************************************************/ + +#ifdef CONFIG_NET_IPv4 +FAR struct net_driver_s *netdev_findby_lipv4addr(in_addr_t lipaddr) +{ + int8_t prefixlen; + return netdev_prefixlen_findby_lipv4addr(lipaddr, &prefixlen); +} +#endif /* CONFIG_NET_IPv4 */ + +/**************************************************************************** + * Name: netdev_findby_lipv6addr + * + * Description: + * Find a previously registered network device by matching a local address + * with the subnet served by the device. Only "up" devices are considered + * (since a "down" device has no meaningful address). + * + * Input Parameters: + * lipaddr - Local, IPv6 address assigned to the network device. Or any + * IPv6 address on the sub-net served by the network device. + * + * Returned Value: + * Pointer to driver on success; null on failure + * + ****************************************************************************/ + +#ifdef CONFIG_NET_IPv6 +FAR struct net_driver_s *netdev_findby_lipv6addr( + const net_ipv6addr_t lipaddr) +{ + int16_t prefixlen; + return netdev_prefixlen_findby_lipv6addr(lipaddr, &prefixlen); } #endif /* CONFIG_NET_IPv6 */ @@ -168,7 +324,8 @@ FAR struct net_driver_s *netdev_findby_lipv6addr( FAR struct net_driver_s *netdev_findby_ripv4addr(in_addr_t lipaddr, in_addr_t ripaddr) { - struct net_driver_s *dev; + FAR struct net_driver_s *dev; + int8_t prefixlen; #ifdef CONFIG_NET_ROUTE in_addr_t router; int ret; @@ -198,22 +355,20 @@ FAR struct net_driver_s *netdev_findby_ripv4addr(in_addr_t lipaddr, } } - /* Check if the address maps to a locally available network */ - - dev = netdev_findby_lipv4addr(ripaddr); - if (dev) - { - return dev; - } + /* Check if the address maps to a locally available network + * Note: If longest prefix match is not enabled, prefixlen will be 32 if + * matched and it will disable further routing lookup. + */ - /* No.. The address lies on an external network */ + dev = netdev_prefixlen_findby_lipv4addr(ripaddr, &prefixlen); #ifdef CONFIG_NET_ROUTE /* If we have a routing table, then perhaps we can find the local - * address of a router that can forward packets to the external network. + * address of a router that can forward packets to the external network + * with longer prefix. */ - ret = net_ipv4_router(ripaddr, &router); + ret = net_ipv4_router(ripaddr, &router, prefixlen); if (ret >= 0) { /* Success... try to find the network device associated with the local @@ -221,13 +376,16 @@ FAR struct net_driver_s *netdev_findby_ripv4addr(in_addr_t lipaddr, */ dev = netdev_findby_lipv4addr(router); - if (dev) - { - return dev; - } } #endif /* CONFIG_NET_ROUTE */ + /* Return the device we found. */ + + if (dev) + { + return dev; + } + /* The above lookup will fail if the packet is being sent out of our * out subnet to a router and there is no routing information. Let's * try the default network device. @@ -259,7 +417,8 @@ FAR struct net_driver_s *netdev_findby_ripv6addr( const net_ipv6addr_t lipaddr, const net_ipv6addr_t ripaddr) { - struct net_driver_s *dev; + FAR struct net_driver_s *dev; + int16_t prefixlen; #ifdef CONFIG_NET_ROUTE net_ipv6addr_t router; int ret; @@ -291,22 +450,20 @@ FAR struct net_driver_s *netdev_findby_ripv6addr( } } - /* Check if the address maps to a locally available network */ - - dev = netdev_findby_lipv6addr(ripaddr); - if (dev) - { - return dev; - } + /* Check if the address maps to a locally available network + * Note: If longest prefix match is not enabled, prefixlen will be 128 if + * matched and it will disable further routing lookup. + */ - /* No.. The address lies on an external network */ + dev = netdev_prefixlen_findby_lipv6addr(ripaddr, &prefixlen); #ifdef CONFIG_NET_ROUTE /* If we have a routing table, then perhaps we can find the local - * address of a router that can forward packets to the external network. + * address of a router that can forward packets to the external network + * with longer prefix. */ - ret = net_ipv6_router(ripaddr, router); + ret = net_ipv6_router(ripaddr, router, prefixlen); if (ret >= 0) { /* Success... try to find the network device associated with the local @@ -314,13 +471,16 @@ FAR struct net_driver_s *netdev_findby_ripv6addr( */ dev = netdev_findby_lipv6addr(router); - if (dev) - { - return dev; - } } #endif /* CONFIG_NET_ROUTE */ + /* Return the device we found. */ + + if (dev) + { + return dev; + } + /* The above lookup will fail if the packet is being sent out of our * out subnet to a router and there is no routing information. Let's * try the default network device. diff --git a/net/netdev/netdev_iob.c b/net/netdev/netdev_iob.c index 1c4886b2090b8..999f7776e39a7 100644 --- a/net/netdev/netdev_iob.c +++ b/net/netdev/netdev_iob.c @@ -153,3 +153,41 @@ void netdev_iob_release(FAR struct net_driver_s *dev) dev->d_buf = NULL; } + +/**************************************************************************** + * Name: netdev_iob_clone + * + * Description: + * Backup the current iob buffer for a given NIC by cloning it. + * + * Assumptions: + * The caller has locked the network. + * + ****************************************************************************/ + +FAR struct iob_s *netdev_iob_clone(FAR struct net_driver_s *dev, + bool throttled) +{ + FAR struct iob_s *iob; + int ret; + + iob = iob_tryalloc(throttled); + if (iob == NULL) + { + nwarn("WARNING: IOB alloc failed for dev %s!\n", dev->d_ifname); + return NULL; + } + + iob_reserve(iob, CONFIG_NET_LL_GUARDSIZE); + ret = iob_clone_partial(dev->d_iob, dev->d_iob->io_pktlen, 0, + iob, 0, throttled, false); + if (ret < 0) + { + iob_free_chain(iob); + nwarn("WARNING: IOB clone failed for dev %s, ret=%d!\n", + dev->d_ifname, ret); + return NULL; + } + + return iob; +} diff --git a/net/netdev/netdev_ioctl.c b/net/netdev/netdev_ioctl.c index 54538e79591c2..56129d6ae6bc9 100644 --- a/net/netdev/netdev_ioctl.c +++ b/net/netdev/netdev_ioctl.c @@ -982,6 +982,11 @@ static int netdev_ifr_ioctl(FAR struct socket *psock, int cmd, /* Yes.. bring the interface up */ ret = netdev_ifup(dev); +#ifdef CONFIG_NET_ARP_ACD + /* having address then start acd */ + + arp_acd_setup(dev); +#endif /* CONFIG_NET_ARP_ACD */ } /* Is this a request to take the interface down? */ @@ -1080,9 +1085,19 @@ static int netdev_ifr_ioctl(FAR struct socket *psock, int cmd, #ifdef CONFIG_NET_IPv4 if (psock->s_domain != PF_INET6) { + if (net_ipv4addr_cmp(dev->d_ipaddr, + ((FAR struct sockaddr_in *)&req->ifr_addr)->sin_addr.s_addr)) + { + break; + } + ioctl_set_ipv4addr(&dev->d_ipaddr, &req->ifr_addr); netlink_device_notify_ipaddr(dev, RTM_NEWADDR, AF_INET, &dev->d_ipaddr, net_ipv4_mask2pref(dev->d_netmask)); + +#ifdef CONFIG_NET_ARP_ACD + arp_acd_set_addr(dev); +#endif /* CONFIG_NET_ARP_ACD */ } #endif diff --git a/net/netfilter/ipt_nat.c b/net/netfilter/ipt_nat.c index 914845fff4624..682f3018ceffb 100644 --- a/net/netfilter/ipt_nat.c +++ b/net/netfilter/ipt_nat.c @@ -60,12 +60,12 @@ static int adjust_nat(FAR struct net_driver_s *dev, FAR void *arg) if (strcmp(target->u.user.name, XT_MASQUERADE_TARGET) == 0 && strcmp(dev->d_ifname, entry->ip.outiface) == 0) { - ipv4_nat_enable(dev); + nat_enable(dev); return 0; } } - ipv4_nat_disable(dev); + nat_disable(dev); return 0; } diff --git a/net/netlink/CMakeLists.txt b/net/netlink/CMakeLists.txt index feb14b41af3cd..6f525c6d576e5 100644 --- a/net/netlink/CMakeLists.txt +++ b/net/netlink/CMakeLists.txt @@ -27,5 +27,9 @@ if(CONFIG_NET_NETLINK) list(APPEND SRCS netlink_route.c netlink_attr.c) endif() + if(CONFIG_NETLINK_NETFILTER) + list(APPEND SRCS netlink_netfilter.c) + endif() + target_sources(net PRIVATE ${SRCS}) endif() diff --git a/net/netlink/Kconfig b/net/netlink/Kconfig index cacf2eaf917cd..dd788e600666d 100644 --- a/net/netlink/Kconfig +++ b/net/netlink/Kconfig @@ -116,7 +116,22 @@ config NETLINK_VALIDATE_POLICY VALIDATE_POLICY is used to make sure the parameters you pass in are valid. +config NETLINK_DISABLE_NEWPREFIX + bool "Disable RTM_NEWPREFIX support" + default n + ---help--- + RTM_NEWPREFIX is used to set netdev prefix. + endif # NETLINK_ROUTE + +config NETLINK_NETFILTER + bool "Netlink Netfilter protocol" + default n + depends on NET_NAT + ---help--- + Support the NETLINK_NETFILTER protocol option, mainly + for conntrack with NAT. + endmenu # Netlink Protocols endif # NET_NETLINK endmenu # Netlink Socket Support diff --git a/net/netlink/Make.defs b/net/netlink/Make.defs index b18597cca35eb..363e9f2a931dc 100644 --- a/net/netlink/Make.defs +++ b/net/netlink/Make.defs @@ -29,6 +29,10 @@ ifeq ($(CONFIG_NETLINK_ROUTE),y) NET_CSRCS += netlink_route.c netlink_attr.c endif +ifeq ($(CONFIG_NETLINK_NETFILTER),y) +NET_CSRCS += netlink_netfilter.c +endif + # Include netlink build support DEPPATH += --dep-path netlink diff --git a/net/netlink/netlink.h b/net/netlink/netlink.h index c2b83ed0fa6f0..9932a9635fab0 100644 --- a/net/netlink/netlink.h +++ b/net/netlink/netlink.h @@ -32,6 +32,7 @@ #include #include +#include #include #include #include @@ -46,6 +47,9 @@ #ifndef CONFIG_NETLINK_ROUTE # define netlink_device_notify(dev) # define netlink_device_notify_ipaddr(dev, type, domain, addr, preflen) +# define netlink_route_notify(route, type, domain) +# define netlink_neigh_notify(neigh, type, domain) +# define netlink_ipv6_prefix_notify(dev, type, pinfo) #endif #ifdef CONFIG_NET_NETLINK @@ -398,6 +402,29 @@ void netlink_notifier_teardown(FAR struct netlink_conn_s *conn); void netlink_notifier_signal(FAR struct netlink_conn_s *conn); +/**************************************************************************** + * Name: netlink_add_terminator + * + * Description: + * Add one NLMSG_DONE response to handle. + * + * Input Parameters: + * handle - The handle previously provided to the sendto() implementation + * for the protocol. This is an opaque reference to the Netlink + * socket state structure. + * req - The request message header. + * group - The broadcast group index, 0 for normal response. + * + * Returned Value: + * Zero (OK) is returned if the terminator was successfully added to the + * response list. + * A negated error value is returned if an unexpected error occurred. + * + ****************************************************************************/ + +int netlink_add_terminator(NETLINK_HANDLE handle, + FAR const struct nlmsghdr *req, int group); + /**************************************************************************** * Name: netlink_tryget_response * @@ -489,6 +516,59 @@ void netlink_device_notify_ipaddr(FAR struct net_driver_s *dev, int type, int domain, FAR const void *addr, uint8_t preflen); +/**************************************************************************** + * Name: netlink_route_notify + * + * Description: + * Perform the route broadcast for the NETLINK_NETFILTER protocol. + * + * Input Parameters: + * route - The route entry + * type - The type of the message, RTM_*ROUTE + * domain - The domain of the message + * + ****************************************************************************/ + +#if defined CONFIG_NETLINK_DISABLE_GETROUTE +# define netlink_route_notify(route, type, domain) +#else +void netlink_route_notify(FAR const void *route, int type, int domain); +#endif + +/**************************************************************************** + * Name: netlink_neigh_notify() + * + * Description: + * Perform the neigh broadcast for the NETLINK_ROUTE protocol. + * + * Input Parameters: + * neigh - The ARP entry or neighbour entry + * type - The type of the message, RTM_*NEIGH + * domain - The domain of the message + * + ****************************************************************************/ + +#if defined(CONFIG_NETLINK_DISABLE_GETNEIGH) +# define netlink_neigh_notify(neigh, type, domain) +#else +void netlink_neigh_notify(FAR const void *neigh, int type, int domain); +#endif + +/**************************************************************************** + * Name: netlink_ipv6_prefix_notify() + * + * Description: + * Perform the RA prefix for the NETLINK_ROUTE protocol. + * + ****************************************************************************/ + +#if defined(CONFIG_NETLINK_DISABLE_NEWPREFIX) || !defined(CONFIG_NET_IPV6) +# define netlink_ipv6_prefix_notify(dev, type, pinfo) +#else +void netlink_ipv6_prefix_notify(FAR struct net_driver_s *dev, int type, + FAR const struct icmpv6_prefixinfo_s *pinfo); +#endif + /**************************************************************************** * Name: nla_next * @@ -520,7 +600,40 @@ int nla_parse(FAR struct nlattr **tb, int maxtype, FAR const struct nlattr *head, int len, FAR const struct nla_policy *policy, FAR struct netlink_ext_ack *extack); -#endif +#endif /* CONFIG_NETLINK_ROUTE */ + +/**************************************************************************** + * Name: netlink_netfilter_sendto + * + * Description: + * Perform the sendto() operation for the NETLINK_NETFILTER protocol. + * + ****************************************************************************/ + +#ifdef CONFIG_NETLINK_NETFILTER +ssize_t netlink_netfilter_sendto(NETLINK_HANDLE handle, + FAR const struct nlmsghdr *nlmsg, + size_t len, int flags, + FAR const struct sockaddr_nl *to, + socklen_t tolen); + +/**************************************************************************** + * Name: netlink_conntrack_notify + * + * Description: + * Perform the conntrack broadcast for the NETLINK_NETFILTER protocol. + * + * Input Parameters: + * type - The type of the message, IPCTNL_MSG_CT_* + * domain - The domain of the message + * nat_entry - The NAT entry + * + ****************************************************************************/ + +void netlink_conntrack_notify(uint8_t type, uint8_t domain, + FAR const void *nat_entry); + +#endif /* CONFIG_NETLINK_NETFILTER */ #undef EXTERN #ifdef __cplusplus diff --git a/net/netlink/netlink_conn.c b/net/netlink/netlink_conn.c index c31eeaccc9c88..8f7673850c611 100644 --- a/net/netlink/netlink_conn.c +++ b/net/netlink/netlink_conn.c @@ -92,6 +92,43 @@ static void netlink_response_available(FAR void *arg) nxsem_post(arg); } +/**************************************************************************** + * Name: netlink_get_terminator + * + * Description: + * Generate one NLMSG_DONE response. + * + ****************************************************************************/ + +static FAR struct netlink_response_s * +netlink_get_terminator(FAR const struct nlmsghdr *req) +{ + FAR struct netlink_response_s *resp; + FAR struct nlmsghdr *hdr; + + /* Allocate the list terminator */ + + resp = kmm_zalloc(sizeof(struct netlink_response_s)); + if (resp == NULL) + { + nerr("ERROR: Failed to allocate response terminator.\n"); + return NULL; + } + + /* Initialize and send the list terminator */ + + hdr = &resp->msg; + hdr->nlmsg_len = sizeof(struct nlmsghdr); + hdr->nlmsg_type = NLMSG_DONE; + hdr->nlmsg_flags = req ? req->nlmsg_flags : 0; + hdr->nlmsg_seq = req ? req->nlmsg_seq : 0; + hdr->nlmsg_pid = req ? req->nlmsg_pid : 0; + + /* Finally, return the response */ + + return resp; +} + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -144,7 +181,7 @@ FAR struct netlink_conn_s *netlink_alloc(void) { #if CONFIG_NETLINK_MAX_CONNS > 0 if (dq_count(&g_active_netlink_connections) + - CONFIG_NETLINK_ALLOC_CONNS >= CONFIG_NETLINK_MAX_CONNS) + CONFIG_NETLINK_ALLOC_CONNS > CONFIG_NETLINK_MAX_CONNS) { nxmutex_unlock(&g_free_lock); return NULL; @@ -286,6 +323,49 @@ void netlink_add_response(NETLINK_HANDLE handle, net_unlock(); } +/**************************************************************************** + * Name: netlink_add_terminator + * + * Description: + * Add one NLMSG_DONE response to handle. + * + * Input Parameters: + * handle - The handle previously provided to the sendto() implementation + * for the protocol. This is an opaque reference to the Netlink + * socket state structure. + * req - The request message header. + * group - The broadcast group index, 0 for normal response. + * + * Returned Value: + * Zero (OK) is returned if the terminator was successfully added to the + * response list. + * A negated error value is returned if an unexpected error occurred. + * + ****************************************************************************/ + +int netlink_add_terminator(NETLINK_HANDLE handle, + FAR const struct nlmsghdr *req, int group) +{ + FAR struct netlink_response_s *resp; + + resp = netlink_get_terminator(req); + if (resp == NULL) + { + return -ENOMEM; + } + + if (group > 0) + { + netlink_add_broadcast(group, resp); + } + else + { + netlink_add_response(handle, resp); + } + + return OK; +} + /**************************************************************************** * Name: netlink_add_broadcast * diff --git a/net/netlink/netlink_netfilter.c b/net/netlink/netlink_netfilter.c new file mode 100644 index 0000000000000..1fbdc90003a22 --- /dev/null +++ b/net/netlink/netlink_netfilter.c @@ -0,0 +1,703 @@ +/**************************************************************************** + * net/netlink/netlink_netfilter.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#include "inet/inet.h" +#include "nat/nat.h" +#include "netlink/netlink.h" +#include "utils/utils.h" + +#ifdef CONFIG_NETLINK_NETFILTER + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct nfnl_sendto_request_s +{ + struct nlmsghdr hdr; + struct nfgenmsg msg; +}; + +struct nfnl_info_s +{ + NETLINK_HANDLE handle; + FAR const struct nfnl_sendto_request_s *req; +}; + +struct nfnl_ipv4addr_s +{ + struct nfattr attr; + in_addr_t addr; +}; + +struct nfnl_ipv6addr_s +{ + struct nfattr attr; + net_ipv6addr_t addr; +}; + +struct nfnl_attr_u8_s +{ + struct nfattr attr; + uint8_t value; + uint8_t pad[3]; +}; + +struct nfnl_attr_u16_s +{ + struct nfattr attr; + uint16_t value; + uint16_t pad[1]; +}; + +/* Struct of a conntrack tuple + * +------+--------------+-----------------+ + * | attr | CTA_TUPLE_IP | CTA_TUPLE_PROTO | + * +------+--------------+-----------------+ + */ + +/* CTA_TUPLE_IP definitions */ + +struct conntrack_tuple_ipv4_s +{ + struct nfattr attr; + struct nfnl_ipv4addr_s src; + struct nfnl_ipv4addr_s dst; +}; + +struct conntrack_tuple_ipv6_s +{ + struct nfattr attr; + struct nfnl_ipv6addr_s src; + struct nfnl_ipv6addr_s dst; +}; + +/* CTA_TUPLE_PROTO definitions */ + +struct conntrack_tuple_tcpudp_s +{ + struct nfattr attr; + struct nfnl_attr_u8_s proto; + struct nfnl_attr_u16_s sport; + struct nfnl_attr_u16_s dport; +}; + +struct conntrack_tuple_icmp_s +{ + struct nfattr attr; + struct nfnl_attr_u8_s proto; + struct nfnl_attr_u16_s id; + struct nfnl_attr_u8_s type; + struct nfnl_attr_u8_s code; +}; + +/* Struct of a conntrack response + * +-----+-----+-----------------+----------------+ + * | hdr | msg | tuple of origin | tuple of reply | + * +-----+-----+-----------------+----------------+ + */ + +struct conntrack_recvfrom_response_s +{ + struct nlmsghdr hdr; + struct nfgenmsg msg; + uint8_t data[1]; +}; + +#define SIZEOF_CTNL_RECVFROM_RESPONSE_S(n) \ + (sizeof(struct conntrack_recvfrom_response_s) + (n) - 1) + +struct conntrack_recvfrom_rsplist_s +{ + sq_entry_t flink; + struct conntrack_recvfrom_response_s payload; +}; + +#define SIZEOF_CTNL_RECVFROM_RSPLIST_S(n) \ + (sizeof(struct conntrack_recvfrom_rsplist_s) + (n) - 1) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: netlink_conntrack_tuple_size + * + * Description: + * Get the size of a CTA_TUPLE. Struct of a conntrack tuple: + * +------+--------------+-----------------+ + * | attr | CTA_TUPLE_IP | CTA_TUPLE_PROTO | + * +------+--------------+-----------------+ + * + * Input Parameters: + * domain - The domain of the tuple + * proto - The protocol of the tuple + * + * Returned Value: + * The size of the tuple. + * + ****************************************************************************/ + +static ssize_t netlink_conntrack_tuple_size(uint8_t domain, uint8_t proto) +{ + size_t size = sizeof(struct nfattr); + + switch (domain) + { + case PF_INET: + size += sizeof(struct conntrack_tuple_ipv4_s); + break; + + case PF_INET6: + size += sizeof(struct conntrack_tuple_ipv6_s); + break; + + default: + return -EINVAL; + } + + switch (proto) + { + case IPPROTO_TCP: + case IPPROTO_UDP: + size += sizeof(struct conntrack_tuple_tcpudp_s); + break; + + case IPPROTO_ICMP: + case IPPROTO_ICMP6: + size += sizeof(struct conntrack_tuple_icmp_s); + break; + + default: + return -EINVAL; + } + + return size; +} + +/**************************************************************************** + * Name: netlink_conntrack_fill_ip + * + * Description: + * Fill the data of a CTA_TUPLE_IP. + * + * Input Parameters: + * buf - The buffer to fill + * domain - The domain of the addresses + * src - The source address + * dst - The destination address + * + * Returned Value: + * The size of the filled data. + * + ****************************************************************************/ + +static size_t netlink_conntrack_fill_ip(FAR void *buf, uint8_t domain, + FAR const void *src, + FAR const void *dst) +{ +#ifdef CONFIG_NET_NAT44 + if (domain == PF_INET) + { + FAR struct conntrack_tuple_ipv4_s *tuple_ipv4 = buf; + + tuple_ipv4->attr.nfa_len = sizeof(struct conntrack_tuple_ipv4_s); + tuple_ipv4->attr.nfa_type = CTA_TUPLE_IP | NFNL_NFA_NEST; + + tuple_ipv4->src.attr.nfa_len = NFA_LENGTH(sizeof(in_addr_t)); + tuple_ipv4->src.attr.nfa_type = CTA_IP_V4_SRC; + net_ipv4addr_hdrcopy(&tuple_ipv4->src.addr, src); + + tuple_ipv4->dst.attr.nfa_len = NFA_LENGTH(sizeof(in_addr_t)); + tuple_ipv4->dst.attr.nfa_type = CTA_IP_V4_DST; + net_ipv4addr_hdrcopy(&tuple_ipv4->dst.addr, dst); + + return tuple_ipv4->attr.nfa_len; + } +#endif + +#ifdef CONFIG_NET_NAT66 + if (domain == PF_INET6) + { + FAR struct conntrack_tuple_ipv6_s *tuple_ipv6 = buf; + + tuple_ipv6->attr.nfa_len = sizeof(struct conntrack_tuple_ipv6_s); + tuple_ipv6->attr.nfa_type = CTA_TUPLE_IP | NFNL_NFA_NEST; + + tuple_ipv6->src.attr.nfa_len = NFA_LENGTH(sizeof(net_ipv6addr_t)); + tuple_ipv6->src.attr.nfa_type = CTA_IP_V6_SRC; + net_ipv6addr_hdrcopy(tuple_ipv6->src.addr, src); + + tuple_ipv6->dst.attr.nfa_len = NFA_LENGTH(sizeof(net_ipv6addr_t)); + tuple_ipv6->dst.attr.nfa_type = CTA_IP_V6_DST; + net_ipv6addr_hdrcopy(tuple_ipv6->dst.addr, dst); + + return tuple_ipv6->attr.nfa_len; + } +#endif + + return 0; +} + +/**************************************************************************** + * Name: netlink_conntrack_fill_proto + * + * Description: + * Fill the data of a CTA_TUPLE_PROTO. + * + * Input Parameters: + * buf - The buffer to fill + * proto - The protocol of the tuple + * sport - The source port + * dport - The destination port + * reply - True if the tuple is a reply + * + * Returned Value: + * The size of the filled data. + * + ****************************************************************************/ + +static size_t netlink_conntrack_fill_proto(FAR void *buf, uint8_t proto, + uint16_t sport, uint16_t dport, + bool reply) +{ + switch (proto) + { +#ifdef CONFIG_NET_TCP + case IPPROTO_TCP: +#endif +#ifdef CONFIG_NET_UDP + case IPPROTO_UDP: +#endif +#if defined(CONFIG_NET_TCP) || defined(CONFIG_NET_UDP) + { + FAR struct conntrack_tuple_tcpudp_s *tuple_tcpudp = buf; + + tuple_tcpudp->attr.nfa_len = + sizeof(struct conntrack_tuple_tcpudp_s); + tuple_tcpudp->attr.nfa_type = CTA_TUPLE_PROTO | NFNL_NFA_NEST; + + tuple_tcpudp->proto.attr.nfa_len = NFA_LENGTH(sizeof(uint8_t)); + tuple_tcpudp->proto.attr.nfa_type = CTA_PROTO_NUM; + tuple_tcpudp->proto.value = proto; + + tuple_tcpudp->sport.attr.nfa_len = NFA_LENGTH(sizeof(uint16_t)); + tuple_tcpudp->sport.attr.nfa_type = CTA_PROTO_SRC_PORT; + tuple_tcpudp->sport.value = sport; + + tuple_tcpudp->dport.attr.nfa_len = NFA_LENGTH(sizeof(uint16_t)); + tuple_tcpudp->dport.attr.nfa_type = CTA_PROTO_DST_PORT; + tuple_tcpudp->dport.value = dport; + + return tuple_tcpudp->attr.nfa_len; + } +#endif + +#ifdef CONFIG_NET_ICMP + case IPPROTO_ICMP: +#endif +#ifdef CONFIG_NET_ICMPv6 + case IPPROTO_ICMP6: +#endif +#if defined(CONFIG_NET_ICMP) || defined(CONFIG_NET_ICMPv6) + { + FAR struct conntrack_tuple_icmp_s *tuple_icmp = buf; + + tuple_icmp->attr.nfa_len = sizeof(struct conntrack_tuple_icmp_s); + tuple_icmp->attr.nfa_type = CTA_TUPLE_PROTO | NFNL_NFA_NEST; + + tuple_icmp->proto.attr.nfa_len = NFA_LENGTH(sizeof(uint8_t)); + tuple_icmp->proto.attr.nfa_type = CTA_PROTO_NUM; + tuple_icmp->proto.value = proto; + + tuple_icmp->id.attr.nfa_len = NFA_LENGTH(sizeof(uint16_t)); + tuple_icmp->id.value = reply ? dport : sport; + + tuple_icmp->type.attr.nfa_len = NFA_LENGTH(sizeof(uint8_t)); + + tuple_icmp->code.attr.nfa_len = NFA_LENGTH(sizeof(uint8_t)); + tuple_icmp->code.value = 0; + +#ifdef CONFIG_NET_ICMP + if (proto == IPPROTO_ICMP) + { + tuple_icmp->id.attr.nfa_type = CTA_PROTO_ICMP_ID; + tuple_icmp->type.attr.nfa_type = CTA_PROTO_ICMP_TYPE; + tuple_icmp->type.value = reply ? ICMP_ECHO_REPLY : + ICMP_ECHO_REQUEST; + tuple_icmp->code.attr.nfa_type = CTA_PROTO_ICMP_CODE; + } +#endif + +#ifdef CONFIG_NET_ICMPv6 + if (proto == IPPROTO_ICMP6) + { + tuple_icmp->id.attr.nfa_type = CTA_PROTO_ICMPV6_ID; + tuple_icmp->type.attr.nfa_type = CTA_PROTO_ICMPV6_TYPE; + tuple_icmp->type.value = reply ? ICMPv6_ECHO_REPLY : + ICMPv6_ECHO_REQUEST; + tuple_icmp->code.attr.nfa_type = CTA_PROTO_ICMPV6_CODE; + } +#endif + + return tuple_icmp->attr.nfa_len; + } +#endif + } + + return 0; +} + +/**************************************************************************** + * Name: netlink_get_ipv4/ipv6_conntrack + * + * Description: + * Get the conntrack response corresponding to an NAT entry. + * + ****************************************************************************/ + +static FAR struct netlink_response_s * +netlink_get_conntrack(FAR const struct nlmsghdr *req, uint16_t flags, + uint8_t type, uint8_t domain, uint8_t proto, + FAR const void *lipaddr, uint16_t lport, + FAR const void *eipaddr, uint16_t eport, + FAR const void *ripaddr, uint16_t rport) +{ + FAR struct conntrack_recvfrom_rsplist_s *entry; + FAR struct nfattr *tuple; + ssize_t tuple_size = netlink_conntrack_tuple_size(domain, proto); + size_t offset = 0; + size_t allocsize; + size_t rspsize; + + if (tuple_size < 0) + { + nerr("ERROR: Failed to get tuple size in response.\n"); + return NULL; + } + + rspsize = SIZEOF_CTNL_RECVFROM_RESPONSE_S(tuple_size * 2); + allocsize = SIZEOF_CTNL_RECVFROM_RSPLIST_S(tuple_size * 2); + + entry = kmm_malloc(allocsize); + if (entry == NULL) + { + nerr("ERROR: Failed to allocate response buffer.\n"); + return NULL; + } + + entry->payload.hdr.nlmsg_len = rspsize; + entry->payload.hdr.nlmsg_type = type | (NFNL_SUBSYS_CTNETLINK << 8); + entry->payload.hdr.nlmsg_flags = flags; + entry->payload.hdr.nlmsg_seq = req ? req->nlmsg_seq : 0; + entry->payload.hdr.nlmsg_pid = req ? req->nlmsg_pid : 0; + + entry->payload.msg.nfgen_family = domain; + entry->payload.msg.version = NFNETLINK_V0; + entry->payload.msg.res_id = 0; + + /* CTA_TUPLE_ORIG */ + + tuple = (FAR struct nfattr *)&entry->payload.data[offset]; + tuple->nfa_len = tuple_size; + tuple->nfa_type = CTA_TUPLE_ORIG | NFNL_NFA_NEST; + offset += sizeof(struct nfattr); + + offset += netlink_conntrack_fill_ip(&entry->payload.data[offset], domain, + lipaddr, ripaddr); + offset += netlink_conntrack_fill_proto(&entry->payload.data[offset], proto, + lport, rport, false); + + DEBUGASSERT(offset == tuple_size); + + /* CTA_TUPLE_REPLY */ + + tuple = (FAR struct nfattr *)&entry->payload.data[offset]; + tuple->nfa_len = tuple_size; + tuple->nfa_type = CTA_TUPLE_REPLY | NFNL_NFA_NEST; + offset += sizeof(struct nfattr); + + offset += netlink_conntrack_fill_ip(&entry->payload.data[offset], domain, + ripaddr, eipaddr); + offset += netlink_conntrack_fill_proto(&entry->payload.data[offset], proto, + rport, eport, true); + + DEBUGASSERT(offset == tuple_size * 2); + + return (FAR struct netlink_response_s *)entry; +} + +#ifdef CONFIG_NET_NAT44 +static FAR struct netlink_response_s * +netlink_get_ipv4_conntrack(FAR const struct nlmsghdr *req, + FAR const ipv4_nat_entry_t *entry, + uint16_t flags, uint8_t type) +{ +#ifndef CONFIG_NET_NAT44_SYMMETRIC + const in_addr_t any = INADDR_ANY; +#endif + return netlink_get_conntrack(req, flags, type, PF_INET, entry->protocol, + &entry->local_ip, entry->local_port, + &entry->external_ip, entry->external_port, +#ifdef CONFIG_NET_NAT44_SYMMETRIC + &entry->peer_ip, entry->peer_port +#else + &any, 0 /* Zero-address */ +#endif + ); +} +#endif + +#ifdef CONFIG_NET_NAT66 +static FAR struct netlink_response_s * +netlink_get_ipv6_conntrack(FAR const struct nlmsghdr *req, + FAR const ipv6_nat_entry_t *entry, + uint16_t flags, uint8_t type) +{ + return netlink_get_conntrack(req, flags, type, PF_INET6, entry->protocol, + entry->local_ip, entry->local_port, + entry->external_ip, entry->external_port, +#ifdef CONFIG_NET_NAT66_SYMMETRIC + entry->peer_ip, entry->peer_port +#else + g_ipv6_unspecaddr, 0 /* Zero-address */ +#endif + ); +} +#endif + +/**************************************************************************** + * Name: netlink_add_ipv4/ipv6_conntrack + * + * Description: + * Add the conntrack response of an IPv4/IPv6 NAT entry. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_NAT44 +static void netlink_add_ipv4_conntrack(FAR ipv4_nat_entry_t *entry, + FAR void *arg) +{ + FAR struct nfnl_info_s *info = arg; + FAR struct netlink_response_s *resp; + uint16_t flags = NLM_F_MULTI | NLM_F_DUMP_FILTERED; + + resp = netlink_get_ipv4_conntrack(&info->req->hdr, entry, flags, + IPCTNL_MSG_CT_NEW); + if (resp != NULL) + { + netlink_add_response(info->handle, resp); + } +} +#endif + +#ifdef CONFIG_NET_NAT66 +static void netlink_add_ipv6_conntrack(FAR ipv6_nat_entry_t *entry, + FAR void *arg) +{ + FAR struct nfnl_info_s *info = arg; + FAR struct netlink_response_s *resp; + uint16_t flags = NLM_F_MULTI | NLM_F_DUMP_FILTERED; + + resp = netlink_get_ipv6_conntrack(&info->req->hdr, entry, flags, + IPCTNL_MSG_CT_NEW); + + if (resp != NULL) + { + netlink_add_response(info->handle, resp); + } +} +#endif + +/**************************************************************************** + * Name: netlink_list_conntrack + * + * Description: + * Return the entire NAT table. + * + ****************************************************************************/ + +static int netlink_list_conntrack(NETLINK_HANDLE handle, + FAR const struct nfnl_sendto_request_s *req) +{ + struct nfnl_info_s info; + uint8_t type = NFNL_MSG_TYPE(req->hdr.nlmsg_type); + if (type != IPCTNL_MSG_CT_GET) + { + return -ENOSYS; + } + + info.handle = handle; + info.req = req; + + switch (req->msg.nfgen_family) + { +#ifdef CONFIG_NET_NAT44 + case AF_INET: + ipv4_nat_entry_foreach(netlink_add_ipv4_conntrack, &info); + break; +#endif + +#ifdef CONFIG_NET_NAT66 + case AF_INET6: + ipv6_nat_entry_foreach(netlink_add_ipv6_conntrack, &info); + break; +#endif + + default: + return -ENOSYS; + } + + return netlink_add_terminator(handle, &req->hdr, 0); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: netlink_netfilter_sendto + * + * Description: + * Perform the sendto() operation for the NETLINK_NETFILTER protocol. + * + ****************************************************************************/ + +ssize_t netlink_netfilter_sendto(NETLINK_HANDLE handle, + FAR const struct nlmsghdr *nlmsg, + size_t len, int flags, + FAR const struct sockaddr_nl *to, + socklen_t tolen) +{ + FAR const struct nfnl_sendto_request_s *req = + (FAR const struct nfnl_sendto_request_s *)nlmsg; + ssize_t ret = -ENOSYS; + uint8_t subsys; + + DEBUGASSERT(handle != NULL && nlmsg != NULL && + nlmsg->nlmsg_len >= sizeof(struct nlmsghdr) && + len >= sizeof(struct nlmsghdr) && + len >= nlmsg->nlmsg_len && to != NULL && + tolen >= sizeof(struct sockaddr_nl)); + + /* Split subsys and type from nlmsg->nlmsg_type */ + + subsys = NFNL_SUBSYS_ID(nlmsg->nlmsg_type); + + /* Handle according to the subsystem */ + + switch (subsys) + { + case NFNL_SUBSYS_CTNETLINK: + ret = netlink_list_conntrack(handle, req); + break; + } + + /* On success, return the size of the request that was processed */ + + if (ret >= 0) + { + ret = len; + } + + return ret; +} + +/**************************************************************************** + * Name: netlink_conntrack_notify + * + * Description: + * Perform the conntrack broadcast for the NETLINK_NETFILTER protocol. + * + * Input Parameters: + * type - The type of the message, IPCTNL_MSG_CT_* + * domain - The domain of the message + * nat_entry - The NAT entry + * + ****************************************************************************/ + +void netlink_conntrack_notify(uint8_t type, uint8_t domain, + FAR const void *nat_entry) +{ + FAR struct netlink_response_s *resp; + uint16_t flags; + int group; + + switch (type) + { + case IPCTNL_MSG_CT_NEW: + group = NFNLGRP_CONNTRACK_NEW; + flags = NLM_F_EXCL | NLM_F_CREATE; + break; + + case IPCTNL_MSG_CT_DELETE: + group = NFNLGRP_CONNTRACK_DESTROY; + flags = 0; + break; + + default: + return; + } + + switch (domain) + { +#ifdef CONFIG_NET_NAT44 + case PF_INET: + resp = netlink_get_ipv4_conntrack(NULL, nat_entry, flags, type); + break; +#endif + +#ifdef CONFIG_NET_NAT66 + case PF_INET6: + resp = netlink_get_ipv6_conntrack(NULL, nat_entry, flags, type); + break; +#endif + + default: + return; + } + + if (resp != NULL) + { + netlink_add_broadcast(group, resp); + } +} + +#endif /* CONFIG_NETLINK_NETFILTER */ diff --git a/net/netlink/netlink_route.c b/net/netlink/netlink_route.c index 82192203ef07a..b4fecc769df06 100644 --- a/net/netlink/netlink_route.c +++ b/net/netlink/netlink_route.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include @@ -179,6 +180,32 @@ struct getaddr_recvfrom_rsplist_s struct getaddr_recvfrom_response_s payload; }; +struct getprefix_recvfrom_addr_s +{ + struct rtattr attr; + net_ipv6addr_t addr; +}; + +struct getprefix_recvfrom_cache_s +{ + struct rtattr attr; + struct prefix_cacheinfo pci; +}; + +struct getprefix_recvfrom_response_s +{ + struct nlmsghdr hdr; + struct prefixmsg pmsg; + struct getprefix_recvfrom_addr_s prefix; + struct getprefix_recvfrom_cache_s pci; +}; + +struct getprefix_recvfrom_rsplist_s +{ + sq_entry_t flink; + struct getprefix_recvfrom_response_s payload; +}; + /* netdev_foreach() callback */ struct nlroute_sendto_request_s @@ -440,66 +467,6 @@ netlink_get_ifaddr(FAR struct net_driver_s *dev, int domain, int type, } #endif -/**************************************************************************** - * Name: netlink_get_terminator - * - * Description: - * Generate one NLMSG_DONE response. - * - ****************************************************************************/ - -static FAR struct netlink_response_s * -netlink_get_terminator(FAR const struct nlroute_sendto_request_s *req) -{ - FAR struct netlink_response_s *resp; - FAR struct nlmsghdr *hdr; - - /* Allocate the list terminator */ - - resp = kmm_zalloc(sizeof(struct netlink_response_s)); - if (resp == NULL) - { - nerr("ERROR: Failed to allocate response terminator.\n"); - return NULL; - } - - /* Initialize and send the list terminator */ - - hdr = &resp->msg; - hdr->nlmsg_len = sizeof(struct nlmsghdr); - hdr->nlmsg_type = NLMSG_DONE; - hdr->nlmsg_flags = req ? req->hdr.nlmsg_flags : 0; - hdr->nlmsg_seq = req ? req->hdr.nlmsg_seq : 0; - hdr->nlmsg_pid = req ? req->hdr.nlmsg_pid : 0; - - /* Finally, return the response */ - - return resp; -} - -/**************************************************************************** - * Name: netlink_add_terminator - * - * Description: - * Add one NLMSG_DONE response to handle. - * - ****************************************************************************/ - -static int netlink_add_terminator(NETLINK_HANDLE handle, - FAR const struct nlroute_sendto_request_s *req) -{ - FAR struct netlink_response_s * resp; - - resp = netlink_get_terminator(req); - if (resp == NULL) - { - return -ENOMEM; - } - - netlink_add_response(handle, resp); - return OK; -} - /**************************************************************************** * Name: netlink_get_devlist * @@ -544,12 +511,12 @@ static int netlink_get_devlist(NETLINK_HANDLE handle, return ret; } - return netlink_add_terminator(handle, req); + return netlink_add_terminator(handle, &req->hdr, 0); } #endif /**************************************************************************** - * Name: netlink_get_arptable() + * Name: netlink_fill_arptable() * * Description: * Return the entire ARP table. @@ -557,45 +524,20 @@ static int netlink_get_devlist(NETLINK_HANDLE handle, ****************************************************************************/ #if defined(CONFIG_NET_ARP) && !defined(CONFIG_NETLINK_DISABLE_GETNEIGH) -static int netlink_get_arptable(NETLINK_HANDLE handle, - FAR const struct nlroute_sendto_request_s *req) +static size_t netlink_fill_arptable( + FAR struct getneigh_recvfrom_rsplist_s **entry) { - FAR struct getneigh_recvfrom_rsplist_s *entry; unsigned int ncopied; size_t allocsize; size_t tabsize; size_t rspsize; - /* Preallocate memory to hold the maximum sized ARP table - * REVISIT: This is probably excessively large and could cause false - * memory out conditions. A better approach would be to actually count - * the number of valid entries in the ARP table. - */ - - tabsize = CONFIG_NET_ARPTAB_SIZE * sizeof(struct arpreq); - rspsize = SIZEOF_NLROUTE_RECVFROM_RESPONSE_S(tabsize); - allocsize = SIZEOF_NLROUTE_RECVFROM_RSPLIST_S(tabsize); - - entry = kmm_zalloc(allocsize); - if (entry == NULL) - { - nerr("ERROR: Failed to allocate response buffer.\n"); - return -ENOMEM; - } - - /* Populate the entry */ - - memcpy(&entry->payload.hdr, &req->hdr, sizeof(struct nlmsghdr)); - entry->payload.hdr.nlmsg_len = rspsize; - entry->payload.msg.ndm_family = req->gen.rtgen_family; - entry->payload.attr.rta_len = RTA_LENGTH(tabsize); - /* Lock the network so that the ARP table will be stable, then copy * the ARP table into the allocated memory. */ net_lock(); - ncopied = arp_snapshot((FAR struct arpreq *)entry->payload.data, + ncopied = arp_snapshot((FAR struct arpreq *)(*entry)->payload.data, CONFIG_NET_ARPTAB_SIZE); net_unlock(); @@ -603,7 +545,7 @@ static int netlink_get_arptable(NETLINK_HANDLE handle, * we can trim the allocation. */ - if (ncopied < CONFIG_NET_ARPTAB_SIZE) + if (ncopied > 0) { FAR struct getneigh_recvfrom_rsplist_s *newentry; @@ -611,27 +553,23 @@ static int netlink_get_arptable(NETLINK_HANDLE handle, rspsize = SIZEOF_NLROUTE_RECVFROM_RESPONSE_S(tabsize); allocsize = SIZEOF_NLROUTE_RECVFROM_RSPLIST_S(tabsize); - newentry = (FAR struct getneigh_recvfrom_rsplist_s *) - kmm_realloc(entry, allocsize); + newentry = kmm_realloc(*entry, allocsize); if (newentry != NULL) { - entry = newentry; + *entry = newentry; } - entry->payload.hdr.nlmsg_len = rspsize; - entry->payload.attr.rta_len = RTA_LENGTH(tabsize); + (*entry)->payload.hdr.nlmsg_len = rspsize; + (*entry)->payload.attr.rta_len = RTA_LENGTH(tabsize); } - /* Finally, add the data to the list of pending responses */ - - netlink_add_response(handle, (FAR struct netlink_response_s *)entry); - return OK; + return ncopied; } #endif /**************************************************************************** - * Name: netlink_get_nbtable() + * Name: netlink_fill_nbtable() * * Description: * Return the entire IPv6 neighbor table. @@ -639,55 +577,29 @@ static int netlink_get_arptable(NETLINK_HANDLE handle, ****************************************************************************/ #if defined(CONFIG_NET_IPv6) && !defined(CONFIG_NETLINK_DISABLE_GETNEIGH) -static int netlink_get_nbtable(NETLINK_HANDLE handle, - FAR const struct nlroute_sendto_request_s *req) +static size_t netlink_fill_nbtable( + FAR struct getneigh_recvfrom_rsplist_s **entry) { - FAR struct getneigh_recvfrom_rsplist_s *entry; unsigned int ncopied; size_t allocsize; size_t tabsize; size_t rspsize; - /* Preallocate memory to hold the maximum sized Neighbor table - * REVISIT: This is probably excessively large and could cause false - * memory out conditions. A better approach would be to actually count - * the number of valid entries in the Neighbor table. - */ - - tabsize = CONFIG_NET_IPv6_NCONF_ENTRIES * - sizeof(struct neighbor_entry_s); - rspsize = SIZEOF_NLROUTE_RECVFROM_RESPONSE_S(tabsize); - allocsize = SIZEOF_NLROUTE_RECVFROM_RSPLIST_S(tabsize); - - entry = kmm_zalloc(allocsize); - if (entry == NULL) - { - nerr("ERROR: Failed to allocate response buffer.\n"); - return -ENOMEM; - } - - /* Populate the entry */ - - memcpy(&entry->payload.hdr, &req->hdr, sizeof(struct nlmsghdr)); - entry->payload.hdr.nlmsg_len = rspsize; - entry->payload.msg.ndm_family = req->gen.rtgen_family; - entry->payload.attr.rta_len = RTA_LENGTH(tabsize); - /* Lock the network so that the Neighbor table will be stable, then * copy the Neighbor table into the allocated memory. */ net_lock(); ncopied = neighbor_snapshot( - (FAR struct neighbor_entry_s *)entry->payload.data, - CONFIG_NET_IPv6_NCONF_ENTRIES); + (FAR struct neighbor_entry_s *)(*entry)->payload.data, + CONFIG_NET_IPv6_NCONF_ENTRIES); net_unlock(); /* Now we have the real number of valid entries in the Neighbor table * and we can trim the allocation. */ - if (ncopied < CONFIG_NET_IPv6_NCONF_ENTRIES) + if (ncopied > 0) { FAR struct getneigh_recvfrom_rsplist_s *newentry; @@ -695,25 +607,147 @@ static int netlink_get_nbtable(NETLINK_HANDLE handle, rspsize = SIZEOF_NLROUTE_RECVFROM_RESPONSE_S(tabsize); allocsize = SIZEOF_NLROUTE_RECVFROM_RSPLIST_S(tabsize); - newentry = (FAR struct getneigh_recvfrom_rsplist_s *) - kmm_realloc(entry, allocsize); + newentry = kmm_realloc(*entry, allocsize); if (newentry != NULL) { - entry = newentry; + *entry = newentry; } - entry->payload.hdr.nlmsg_len = rspsize; - entry->payload.attr.rta_len = RTA_LENGTH(tabsize); + (*entry)->payload.hdr.nlmsg_len = rspsize; + (*entry)->payload.attr.rta_len = RTA_LENGTH(tabsize); } - /* Finally, add the response to the list of pending responses */ - - netlink_add_response(handle, (FAR struct netlink_response_s *)entry); - return OK; + return ncopied; } #endif +/**************************************************************************** + * Name: netlink_fill_nbtable() + * + * Description: + * Return the entire IPv6 neighbor table. + * + ****************************************************************************/ + +#if !defined(CONFIG_NETLINK_DISABLE_GETNEIGH) +static FAR struct netlink_response_s * +netlink_get_neighbor(FAR const void *neigh, int domain, int type, + FAR const struct nlroute_sendto_request_s *req) +{ + FAR struct getneigh_recvfrom_rsplist_s *alloc; + FAR struct getneigh_recvfrom_response_s *resp; + size_t allocsize; + size_t tabsize; + size_t tabnum; + size_t rspsize; + + /* Preallocate memory to hold the maximum sized ARP table + * REVISIT: This is probably excessively large and could cause false + * memory out conditions. A better approach would be to actually count + * the number of valid entries in the ARP table. + */ + +#if defined(CONFIG_NET_ARP) + if (domain == AF_INET) + { + tabnum = req ? CONFIG_NET_ARPTAB_SIZE : 1; + tabsize = tabnum * sizeof(struct arpreq); + } + else +#endif +#if defined(CONFIG_NET_IPv6) + if (domain == AF_INET6) + { + tabnum = req ? CONFIG_NET_IPv6_NCONF_ENTRIES : 1; + tabsize = tabnum * sizeof(struct neighbor_entry_s); + } + else +#endif + { + return NULL; + } + + rspsize = SIZEOF_NLROUTE_RECVFROM_RESPONSE_S(tabsize); + allocsize = SIZEOF_NLROUTE_RECVFROM_RSPLIST_S(tabsize); + + /* Allocate the response buffer */ + + alloc = kmm_zalloc(allocsize); + if (alloc == NULL) + { + nerr("ERROR: Failed to allocate response buffer.\n"); + return NULL; + } + + /* Initialize the response buffer */ + + resp = &alloc->payload; + resp->hdr.nlmsg_len = rspsize; + resp->hdr.nlmsg_type = type; + resp->hdr.nlmsg_flags = req ? req->hdr.nlmsg_flags : 0; + resp->hdr.nlmsg_seq = req ? req->hdr.nlmsg_seq : 0; + resp->hdr.nlmsg_pid = req ? req->hdr.nlmsg_pid : 0; + + resp->msg.ndm_family = domain; + resp->attr.rta_len = RTA_LENGTH(tabsize); + + /* Copy neigh or arp entries into resp data */ + + if (req == NULL) + { + if (neigh == NULL) + { + return NULL; + } + + /* Only one entry need to notify */ + + memcpy(resp->data, neigh, tabsize); + } +#if defined(CONFIG_NET_ARP) + else if (domain == AF_INET) + { + tabnum = netlink_fill_arptable(&alloc); + } +#endif +#if defined(CONFIG_NET_IPv6) + else if (domain == AF_INET6) + { + tabnum = netlink_fill_nbtable(&alloc); + } +#endif + + /* If no entry in table, just free alloc */ + + if (tabnum <= 0) + { + kmm_free(alloc); + nwarn("WARNING: Failed to get entry in %s table.\n", + domain == AF_INET ? "ARP" : "neighbor"); + return NULL; + } + + return (FAR struct netlink_response_s *)alloc; +} + +static int netlink_get_neighborlist(NETLINK_HANDLE handle, int domain, + FAR const struct nlroute_sendto_request_s *req) +{ + FAR struct netlink_response_s *resp; + + resp = netlink_get_neighbor(NULL, domain, RTM_GETNEIGH, req); + if (resp == NULL) + { + return -ENOENT; + } + + netlink_add_response(handle, resp); + + return netlink_add_terminator(handle, &req->hdr, 0); +} +#endif /* CONFIG_NETLINK_DISABLE_GETNEIGH */ + /**************************************************************************** * Name: netlink_ipv4_route * @@ -723,15 +757,14 @@ static int netlink_get_nbtable(NETLINK_HANDLE handle, ****************************************************************************/ #if defined(CONFIG_NET_IPv4) && !defined(CONFIG_NETLINK_DISABLE_GETROUTE) -static int netlink_ipv4_route(FAR struct net_route_ipv4_s *route, - FAR void *arg) +static FAR struct netlink_response_s * +netlink_get_ipv4_route(FAR const struct net_route_ipv4_s *route, int type, + FAR const struct nlroute_sendto_request_s *req) { FAR struct getroute_recvfrom_ipv4resplist_s *alloc; FAR struct getroute_recvfrom_ipv4response_s *resp; - FAR struct nlroute_info_s *info; - DEBUGASSERT(route != NULL && arg != NULL); - info = (FAR struct nlroute_info_s *)arg; + DEBUGASSERT(route != NULL); /* Allocate the response */ @@ -739,19 +772,19 @@ static int netlink_ipv4_route(FAR struct net_route_ipv4_s *route, kmm_zalloc(sizeof(struct getroute_recvfrom_ipv4resplist_s)); if (alloc == NULL) { - return -ENOMEM; + return NULL; } /* Format the response */ resp = &alloc->payload; resp->hdr.nlmsg_len = sizeof(struct getroute_recvfrom_ipv4response_s); - resp->hdr.nlmsg_type = RTM_NEWROUTE; - resp->hdr.nlmsg_flags = info->req->hdr.nlmsg_flags; - resp->hdr.nlmsg_seq = info->req->hdr.nlmsg_seq; - resp->hdr.nlmsg_pid = info->req->hdr.nlmsg_pid; + resp->hdr.nlmsg_type = type; + resp->hdr.nlmsg_flags = req ? req->hdr.nlmsg_flags : 0; + resp->hdr.nlmsg_seq = req ? req->hdr.nlmsg_seq : 0; + resp->hdr.nlmsg_pid = req ? req->hdr.nlmsg_pid : 0; - resp->rte.rtm_family = info->req->gen.rtgen_family; + resp->rte.rtm_family = AF_INET; resp->rte.rtm_table = RT_TABLE_MAIN; resp->rte.rtm_protocol = RTPROT_STATIC; resp->rte.rtm_scope = RT_SCOPE_SITE; @@ -768,15 +801,39 @@ static int netlink_ipv4_route(FAR struct net_route_ipv4_s *route, resp->gateway.attr.rta_type = RTA_GATEWAY; resp->gateway.addr = route->router; + return (FAR struct netlink_response_s *)alloc; +} + +/**************************************************************************** + * Name: netlink_ipv4route_callback + * + * Input Parameters: + * route - The entry of IPV4 routing table. + * arg - The netlink info of request. + * + ****************************************************************************/ + +static int netlink_ipv4route_callback(FAR struct net_route_ipv4_s *route, + FAR void *arg) +{ + FAR struct nlroute_info_s *info = arg; + FAR struct netlink_response_s *resp; + + resp = netlink_get_ipv4_route(route, RTM_NEWROUTE, info->req); + if (resp == NULL) + { + return -ENOENT; + } + /* Finally, add the response to the list of pending responses */ - netlink_add_response(info->handle, (FAR struct netlink_response_s *)alloc); + netlink_add_response(info->handle, resp); return OK; } #endif /**************************************************************************** - * Name: netlink_get_ipv4route + * Name: netlink_list_ipv4_route * * Description: * Dump a list of all network devices of the specified type. @@ -784,7 +841,7 @@ static int netlink_ipv4_route(FAR struct net_route_ipv4_s *route, ****************************************************************************/ #if defined(CONFIG_NET_IPv4) && !defined(CONFIG_NETLINK_DISABLE_GETROUTE) -static int netlink_get_ipv4route(NETLINK_HANDLE handle, +static int netlink_list_ipv4_route(NETLINK_HANDLE handle, FAR const struct nlroute_sendto_request_s *req) { struct nlroute_info_s info; @@ -795,7 +852,7 @@ static int netlink_get_ipv4route(NETLINK_HANDLE handle, info.handle = handle; info.req = req; - ret = net_foreachroute_ipv4(netlink_ipv4_route, &info); + ret = net_foreachroute_ipv4(netlink_ipv4route_callback, &info); if (ret < 0) { return ret; @@ -803,12 +860,12 @@ static int netlink_get_ipv4route(NETLINK_HANDLE handle, /* Terminate the routing table */ - return netlink_add_terminator(handle, req); + return netlink_add_terminator(handle, &req->hdr, 0); } #endif /**************************************************************************** - * Name: netlink_ipv6_route + * Name: netlink_get_ipv6_route * * Description: * Dump a list of all network devices of the specified type. @@ -816,15 +873,14 @@ static int netlink_get_ipv4route(NETLINK_HANDLE handle, ****************************************************************************/ #if defined(CONFIG_NET_IPv6) && !defined(CONFIG_NETLINK_DISABLE_GETROUTE) -static int netlink_ipv6_route(FAR struct net_route_ipv6_s *route, - FAR void *arg) +static FAR struct netlink_response_s * +netlink_get_ipv6_route(FAR const struct net_route_ipv6_s *route, int type, + FAR const struct nlroute_sendto_request_s *req) { FAR struct getroute_recvfrom_ipv6resplist_s *alloc; FAR struct getroute_recvfrom_ipv6response_s *resp; - FAR struct nlroute_info_s *info; - DEBUGASSERT(route != NULL && arg != NULL); - info = (FAR struct nlroute_info_s *)arg; + DEBUGASSERT(route != NULL); /* Allocate the response */ @@ -832,19 +888,19 @@ static int netlink_ipv6_route(FAR struct net_route_ipv6_s *route, kmm_zalloc(sizeof(struct getroute_recvfrom_ipv6resplist_s)); if (alloc == NULL) { - return -ENOMEM; + return NULL; } /* Format the response */ resp = &alloc->payload; resp->hdr.nlmsg_len = sizeof(struct getroute_recvfrom_ipv6response_s); - resp->hdr.nlmsg_type = RTM_NEWROUTE; - resp->hdr.nlmsg_flags = info->req->hdr.nlmsg_flags; - resp->hdr.nlmsg_seq = info->req->hdr.nlmsg_seq; - resp->hdr.nlmsg_pid = info->req->hdr.nlmsg_pid; + resp->hdr.nlmsg_type = type; + resp->hdr.nlmsg_flags = req ? req->hdr.nlmsg_flags : 0; + resp->hdr.nlmsg_seq = req ? req->hdr.nlmsg_seq : 0; + resp->hdr.nlmsg_pid = req ? req->hdr.nlmsg_pid : 0; - resp->rte.rtm_family = info->req->gen.rtgen_family; + resp->rte.rtm_family = AF_INET6; resp->rte.rtm_table = RT_TABLE_MAIN; resp->rte.rtm_protocol = RTPROT_STATIC; resp->rte.rtm_scope = RT_SCOPE_SITE; @@ -861,15 +917,43 @@ static int netlink_ipv6_route(FAR struct net_route_ipv6_s *route, resp->gateway.attr.rta_type = RTA_GATEWAY; net_ipv6addr_copy(resp->gateway.addr, route->router); + return (FAR struct netlink_response_s *)alloc; +} + +/**************************************************************************** + * Name: netlink_ipv6route_callback + * + * Description: + * Response netlink message from ipv6 route list. + * + * Input Parameters: + * route - The entry of IPV6 routing table. + * arg - The netlink info of request. + * + ****************************************************************************/ + +static int netlink_ipv6route_callback(FAR struct net_route_ipv6_s *route, + FAR void *arg) +{ + FAR struct nlroute_info_s *info = arg; + FAR struct netlink_response_s *resp; + + resp = netlink_get_ipv6_route(route, RTM_NEWROUTE, info->req); + if (resp == NULL) + { + return -ENOENT; + } + /* Finally, add the response to the list of pending responses */ - netlink_add_response(info->handle, (FAR struct netlink_response_s *)alloc); + netlink_add_response(info->handle, resp); + return OK; } #endif /**************************************************************************** - * Name: netlink_get_ip6vroute + * Name: netlink_get_ipv6route * * Description: * Dump a list of all network devices of the specified type. @@ -877,7 +961,7 @@ static int netlink_ipv6_route(FAR struct net_route_ipv6_s *route, ****************************************************************************/ #if defined(CONFIG_NET_IPv6) && !defined(CONFIG_NETLINK_DISABLE_GETROUTE) -static int netlink_get_ip6vroute(NETLINK_HANDLE handle, +static int netlink_list_ipv6_route(NETLINK_HANDLE handle, FAR const struct nlroute_sendto_request_s *req) { struct nlroute_info_s info; @@ -888,7 +972,7 @@ static int netlink_get_ip6vroute(NETLINK_HANDLE handle, info.handle = handle; info.req = req; - ret = net_foreachroute_ipv6(netlink_ipv6_route, &info); + ret = net_foreachroute_ipv6(netlink_ipv6route_callback, &info); if (ret < 0) { return ret; @@ -896,7 +980,7 @@ static int netlink_get_ip6vroute(NETLINK_HANDLE handle, /* Terminate the routing table */ - return netlink_add_terminator(handle, req); + return netlink_add_terminator(handle, &req->hdr, 0); } #endif @@ -1188,7 +1272,59 @@ static int netlink_get_addr(NETLINK_HANDLE handle, return ret; } - return netlink_add_terminator(handle, req); + return netlink_add_terminator(handle, &req->hdr, 0); +} +#endif + +#if !defined(CONFIG_NETLINK_DISABLE_NEWADDR) && defined(CONFIG_NET_IPV6) +static FAR struct netlink_response_s * +netlink_fill_ipv6prefix(FAR struct net_driver_s *dev, int type, + FAR const struct icmpv6_prefixinfo_s *pinfo) +{ + FAR struct getprefix_recvfrom_rsplist_s *alloc; + FAR struct getprefix_recvfrom_response_s *resp; + + DEBUGASSERT(dev != NULL && pinfo != NULL); + + alloc = kmm_zalloc(sizeof(struct getprefix_recvfrom_rsplist_s)); + if (alloc == NULL) + { + nerr("ERROR: Failed to allocate response buffer.\n"); + return NULL; + } + + /* Initialize the response buffer */ + + resp = &alloc->payload; + + resp->hdr.nlmsg_len = sizeof(struct getprefix_recvfrom_response_s); + resp->hdr.nlmsg_type = type; + resp->hdr.nlmsg_flags = 0; + resp->hdr.nlmsg_seq = 0; + resp->hdr.nlmsg_pid = 0; + + resp->pmsg.prefix_family = AF_INET6; +#ifdef CONFIG_NETDEV_IFINDEX + resp->pmsg.prefix_ifindex = dev->d_ifindex; +#endif + resp->pmsg.prefix_len = pinfo->optlen; + resp->pmsg.prefix_type = pinfo->opttype; + + resp->prefix.attr.rta_len = RTA_LENGTH(sizeof(net_ipv6addr_t)); + resp->prefix.attr.rta_type = PREFIX_ADDRESS; + net_ipv6addr_copy(resp->prefix.addr, pinfo->prefix); + + resp->pci.attr.rta_len = RTA_LENGTH(sizeof(struct prefix_cacheinfo)); + resp->pci.attr.rta_type = PREFIX_CACHEINFO; + + resp->pci.pci.preferred_time = NTOHS(pinfo->plifetime[0]) << 16; + resp->pci.pci.preferred_time |= NTOHS(pinfo->plifetime[1]); + resp->pci.pci.valid_time = NTOHS(pinfo->vlifetime[0]) << 16; + resp->pci.pci.valid_time |= NTOHS(pinfo->vlifetime[1]); + + /* Finally, return the response */ + + return (FAR struct netlink_response_s *)alloc; } #endif @@ -1244,7 +1380,7 @@ ssize_t netlink_route_sendto(NETLINK_HANDLE handle, if (req->gen.rtgen_family == AF_INET) { - ret = netlink_get_arptable(handle, req); + ret = netlink_get_neighborlist(handle, AF_INET, req); } else #endif @@ -1254,7 +1390,7 @@ ssize_t netlink_route_sendto(NETLINK_HANDLE handle, if (req->gen.rtgen_family == AF_INET6) { - ret = netlink_get_nbtable(handle, req); + ret = netlink_get_neighborlist(handle, AF_INET6, req); } else #endif @@ -1271,14 +1407,14 @@ ssize_t netlink_route_sendto(NETLINK_HANDLE handle, #ifdef CONFIG_NET_IPv4 if (req->gen.rtgen_family == AF_INET) { - ret = netlink_get_ipv4route(handle, req); + ret = netlink_list_ipv4_route(handle, req); } else #endif #ifdef CONFIG_NET_IPv6 if (req->gen.rtgen_family == AF_INET6) { - ret = netlink_get_ip6vroute(handle, req); + ret = netlink_list_ipv6_route(handle, req); } else #endif @@ -1394,12 +1530,7 @@ void netlink_device_notify(FAR struct net_driver_s *dev) if (resp != NULL) { netlink_add_broadcast(RTNLGRP_LINK, resp); - - resp = netlink_get_terminator(NULL); - if (resp != NULL) - { - netlink_add_broadcast(RTNLGRP_LINK, resp); - } + netlink_add_terminator(NULL, NULL, RTNLGRP_LINK); } } #endif @@ -1448,13 +1579,110 @@ void netlink_device_notify_ipaddr(FAR struct net_driver_s *dev, } netlink_add_broadcast(group, resp); + netlink_add_terminator(NULL, NULL, group); + } +} +#endif - resp = netlink_get_terminator(NULL); - if (resp != NULL) - { - netlink_add_broadcast(group, resp); - } +/**************************************************************************** + * Name: netlink_route_notify + * + * Description: + * Perform the route broadcast for the NETLINK_NETFILTER protocol. + * + * Input Parameters: + * route - The route entry + * type - The type of the message, RTM_*ROUTE + * domain - The domain of the message + * + ****************************************************************************/ + +#ifndef CONFIG_NETLINK_DISABLE_GETROUTE +void netlink_route_notify(FAR const void *route, int type, int domain) +{ + FAR struct netlink_response_s *resp; + int group; + + DEBUGASSERT(route != NULL); + +#ifdef CONFIG_NET_IPv4 + if (domain == AF_INET) + { + resp = netlink_get_ipv4_route((FAR struct net_route_ipv4_s *)route, + type, NULL); + group = RTNLGRP_IPV4_ROUTE; + } + else +#endif +#ifdef CONFIG_NET_IPv6 + if (domain == AF_INET6) + { + resp = netlink_get_ipv6_route((FAR struct net_route_ipv6_s *)route, + type, NULL); + group = RTNLGRP_IPV6_ROUTE; + } + else +#endif + { + nwarn("netlink_route_notify unknown type %d domain %d\n", + type, domain); + return; + } + + if (resp != NULL) + { + netlink_add_broadcast(group, resp); + netlink_add_terminator(NULL, NULL, group); + } +} +#endif + +/**************************************************************************** + * Name: netlink_neigh_notify() + * + * Description: + * Perform the neigh broadcast for the NETLINK_ROUTE protocol. + * + ****************************************************************************/ + +#ifndef CONFIG_NETLINK_DISABLE_GETNEIGH +void netlink_neigh_notify(FAR const void *neigh, int type, int domain) +{ + FAR struct netlink_response_s *resp; + + resp = netlink_get_neighbor(neigh, domain, type, NULL); + if (resp == NULL) + { + return; + } + + netlink_add_broadcast(RTNLGRP_NEIGH, resp); + netlink_add_terminator(NULL, NULL, RTNLGRP_NEIGH); +} +#endif + +/**************************************************************************** + * Name: netlink_ipv6_prefix_notify() + * + * Description: + * Perform the RA prefix for the NETLINK_ROUTE protocol. + * + ****************************************************************************/ + +#if !defined(CONFIG_NETLINK_DISABLE_NEWADDR) && defined(CONFIG_NET_IPV6) +void netlink_ipv6_prefix_notify(FAR struct net_driver_s *dev, int type, + FAR const struct icmpv6_prefixinfo_s *pinfo) +{ + FAR struct netlink_response_s *resp; + + resp = netlink_fill_ipv6prefix(dev, type, pinfo); + if (resp == NULL) + { + return; } + + netlink_add_broadcast(RTNLGRP_IPV6_PREFIX, resp); + netlink_add_terminator(NULL, NULL, RTNLGRP_IPV6_PREFIX); } #endif diff --git a/net/netlink/netlink_sockif.c b/net/netlink/netlink_sockif.c index abfa27d9fc523..72de037697bb6 100644 --- a/net/netlink/netlink_sockif.c +++ b/net/netlink/netlink_sockif.c @@ -129,6 +129,11 @@ static int netlink_setup(FAR struct socket *psock) break; #endif +#ifdef CONFIG_NETLINK_NETFILTER + case NETLINK_NETFILTER: + break; +#endif + default: return -EPROTONOSUPPORT; } @@ -621,6 +626,15 @@ static ssize_t netlink_sendmsg(FAR struct socket *psock, break; #endif +#ifdef CONFIG_NETLINK_NETFILTER + case NETLINK_NETFILTER: + ret = netlink_netfilter_sendto(conn, nlmsg, + msg->msg_iov->iov_len, flags, + (FAR const struct sockaddr_nl *)to, + tolen); + break; +#endif + default: ret = -EOPNOTSUPP; break; diff --git a/net/pkt/Kconfig b/net/pkt/Kconfig index 79c600085c8df..b594e130a098d 100644 --- a/net/pkt/Kconfig +++ b/net/pkt/Kconfig @@ -18,8 +18,6 @@ config NET_PKT a packet socket will bypass the network altogether and be placed in the transmission buffer of the network interface driver. - REVISIT: Currently only implemented for Ethernet. - if NET_PKT config NET_PKT_PREALLOC_CONNS diff --git a/net/pkt/pkt.h b/net/pkt/pkt.h index e74f8fd95cf19..f7d193a48df91 100644 --- a/net/pkt/pkt.h +++ b/net/pkt/pkt.h @@ -60,9 +60,7 @@ struct pkt_conn_s /* Pkt socket-specific content follows */ - uint8_t lmac[6]; /* The local Ethernet address in network byte order */ uint8_t ifindex; - uint16_t proto; uint8_t crefs; /* Reference counts on this instance */ /* Read-ahead buffering. @@ -97,7 +95,6 @@ EXTERN const struct sock_intf_s g_pkt_sockif; ****************************************************************************/ struct net_driver_s; /* Forward reference */ -struct eth_hdr_s; /* Forward reference */ struct socket; /* Forward reference */ /**************************************************************************** @@ -137,15 +134,15 @@ void pkt_free(FAR struct pkt_conn_s *conn); * Name: pkt_active() * * Description: - * Find a connection structure that is the appropriate - * connection to be used with the provided Ethernet header + * Find a connection structure that is the appropriate connection to be + * used with the provided network device * * Assumptions: * This function is called from network logic at with the network locked. * ****************************************************************************/ -FAR struct pkt_conn_s *pkt_active(FAR struct eth_hdr_s *buf); +FAR struct pkt_conn_s *pkt_active(FAR struct net_driver_s *dev); /**************************************************************************** * Name: pkt_nextconn() diff --git a/net/pkt/pkt_conn.c b/net/pkt/pkt_conn.c index b74f4a54cb284..bb5d3a6dbde9d 100644 --- a/net/pkt/pkt_conn.c +++ b/net/pkt/pkt_conn.c @@ -117,8 +117,8 @@ FAR struct pkt_conn_s *pkt_alloc(void) if (dq_peek(&g_free_pkt_connections) == NULL) { #if CONFIG_NET_PKT_MAX_CONNS > 0 - if (dq_count(&g_active_pkt_connections) + CONFIG_NET_PKT_ALLOC_CONNS - >= CONFIG_NET_PKT_MAX_CONNS) + if (dq_count(&g_active_pkt_connections) + + CONFIG_NET_PKT_ALLOC_CONNS > CONFIG_NET_PKT_MAX_CONNS) { nxmutex_unlock(&g_free_lock); return NULL; @@ -194,24 +194,21 @@ void pkt_free(FAR struct pkt_conn_s *conn) * * Description: * Find a connection structure that is the appropriate connection to be - * used with the provided Ethernet header + * used with the provided network device * * Assumptions: * This function is called from network logic at with the network locked. * ****************************************************************************/ -FAR struct pkt_conn_s *pkt_active(FAR struct eth_hdr_s *buf) +FAR struct pkt_conn_s *pkt_active(FAR struct net_driver_s *dev) { FAR struct pkt_conn_s *conn = (FAR struct pkt_conn_s *)g_active_pkt_connections.head; while (conn) { - /* FIXME lmac in conn should have been set by pkt_bind() */ - - if (eth_addr_cmp(buf->dest, conn->lmac) || - eth_addr_cmp(buf->src, conn->lmac)) + if (dev->d_ifindex == conn->ifindex) { /* Matching connection found.. return a reference to it */ diff --git a/net/pkt/pkt_input.c b/net/pkt/pkt_input.c index 4e8fed8162528..3f06ce21d37c0 100644 --- a/net/pkt/pkt_input.c +++ b/net/pkt/pkt_input.c @@ -131,10 +131,9 @@ static uint16_t pkt_datahandler(FAR struct net_driver_s *dev, static int pkt_in(FAR struct net_driver_s *dev) { FAR struct pkt_conn_s *conn; - FAR struct eth_hdr_s *pbuf = ETHBUF; int ret = OK; - conn = pkt_active(pbuf); + conn = pkt_active(dev); if (conn) { uint16_t flags; diff --git a/net/pkt/pkt_sendmsg.c b/net/pkt/pkt_sendmsg.c index 08ed662c52cc8..1ff6f0eef2435 100644 --- a/net/pkt/pkt_sendmsg.c +++ b/net/pkt/pkt_sendmsg.c @@ -194,7 +194,7 @@ ssize_t pkt_sendmsg(FAR struct socket *psock, FAR struct msghdr *msg, /* Only SOCK_RAW is supported */ - if (psock->s_type == SOCK_RAW) + if (psock->s_type != SOCK_RAW) { /* EDESTADDRREQ. Signifies that the socket is not connection-mode and * no peer address is set. diff --git a/net/pkt/pkt_sockif.c b/net/pkt/pkt_sockif.c index b2f58a9ce2a8b..888bc624c71bf 100644 --- a/net/pkt/pkt_sockif.c +++ b/net/pkt/pkt_sockif.c @@ -242,7 +242,7 @@ static int pkt_bind(FAR struct socket *psock, ifindex = ((FAR struct sockaddr_ll *)addr)->sll_ifindex; - /* Get the MAC address of that interface */ + /* Check if we have that interface */ dev = netdev_findbyindex(ifindex); if (dev == NULL) @@ -250,18 +250,9 @@ static int pkt_bind(FAR struct socket *psock, return -EADDRNOTAVAIL; } - /* Only Ethernet is supported */ - - if (dev->d_lltype != NET_LL_ETHERNET && - dev->d_lltype != NET_LL_IEEE80211) - { - return -EAFNOSUPPORT; - } - - /* Put ifindex and mac address into connection */ + /* Put ifindex into connection */ conn->ifindex = ifindex; - memcpy(conn->lmac, dev->d_mac.ether.ether_addr_octet, 6); return OK; } diff --git a/net/procfs/netdev_statistics.c b/net/procfs/netdev_statistics.c index e62fd59830c15..aeaa43d3e334a 100644 --- a/net/procfs/netdev_statistics.c +++ b/net/procfs/netdev_statistics.c @@ -293,6 +293,13 @@ static int netprocfs_inet4addresses(FAR struct netprocfs_file_s *netfile) len += snprintf(&netfile->line[len], NET_LINELEN - len, "\tinet addr:%s ", inet_ntoa_r(addr, inetaddr, sizeof(inetaddr))); +#ifdef CONFIG_NET_ARP_ACD + if (dev->d_acd.conflict_flag == ARP_ACD_ADDRESS_CONFLICT) + { + len += snprintf(&netfile->line[len], NET_LINELEN - len, + "(conflict!) "); + } +#endif /* Show the IPv4 default router address */ diff --git a/net/route/Kconfig b/net/route/Kconfig index 03cf002778c3f..a7191e91307ac 100644 --- a/net/route/Kconfig +++ b/net/route/Kconfig @@ -137,5 +137,12 @@ config ROUTE_MAX_IPv6_CACHEROUTES This determines the maximum number of routes that can be cached in memory. +config ROUTE_LONGEST_MATCH + bool "Enable longest prefix match support" + default y + ---help--- + Enable support for longest prefix match routing. + ("Longest Match" in RFC 1812, Section 5.2.4.3, Page 75) + endif # NET_ROUTE -endmenu # ARP Configuration +endmenu # Routing Table Configuration diff --git a/net/route/net_add_fileroute.c b/net/route/net_add_fileroute.c index 6c846c6c6fcbc..51593ac47aae3 100644 --- a/net/route/net_add_fileroute.c +++ b/net/route/net_add_fileroute.c @@ -33,6 +33,7 @@ #include #include +#include "netlink/netlink.h" #include "route/fileroute.h" #include "route/route.h" @@ -84,6 +85,8 @@ int net_addroute_ipv4(in_addr_t target, in_addr_t netmask, in_addr_t router) nwritten = net_writeroute_ipv4(&fshandle, &route); net_closeroute_ipv4(&fshandle); + + netlink_route_notify(&route, RTM_NEWROUTE, AF_INET); return nwritten >= 0 ? 0 : (int)nwritten; } #endif @@ -118,6 +121,8 @@ int net_addroute_ipv6(net_ipv6addr_t target, net_ipv6addr_t netmask, nwritten = net_writeroute_ipv6(&fshandle, &route); net_closeroute_ipv6(&fshandle); + + netlink_route_notify(&route, RTM_NEWROUTE, AF_INET6); return nwritten >= 0 ? 0 : (int)nwritten; } #endif diff --git a/net/route/net_add_ramroute.c b/net/route/net_add_ramroute.c index 05adde4625b15..5f1907839dc09 100644 --- a/net/route/net_add_ramroute.c +++ b/net/route/net_add_ramroute.c @@ -34,6 +34,7 @@ #include +#include "netlink/netlink.h" #include "route/ramroute.h" #include "route/route.h" @@ -86,6 +87,8 @@ int net_addroute_ipv4(in_addr_t target, in_addr_t netmask, in_addr_t router) ramroute_ipv4_addlast((FAR struct net_route_ipv4_entry_s *)route, &g_ipv4_routes); net_unlock(); + + netlink_route_notify(route, RTM_NEWROUTE, AF_INET); return OK; } #endif @@ -121,6 +124,8 @@ int net_addroute_ipv6(net_ipv6addr_t target, net_ipv6addr_t netmask, ramroute_ipv6_addlast((FAR struct net_route_ipv6_entry_s *)route, &g_ipv6_routes); net_unlock(); + + netlink_route_notify(route, RTM_NEWROUTE, AF_INET6); return OK; } #endif diff --git a/net/route/net_alloc_ramroute.c b/net/route/net_alloc_ramroute.c index 85d8127574b4a..17d60f7f03883 100644 --- a/net/route/net_alloc_ramroute.c +++ b/net/route/net_alloc_ramroute.c @@ -159,6 +159,11 @@ FAR struct net_route_ipv4_s *net_allocroute_ipv4(void) route = ramroute_ipv4_remfirst(&g_free_ipv4routes); net_unlock(); + if (!route) + { + return NULL; + } + return &route->entry; } #endif @@ -177,6 +182,11 @@ FAR struct net_route_ipv6_s *net_allocroute_ipv6(void) route = ramroute_ipv6_remfirst(&g_free_ipv6routes); net_unlock(); + if (!route) + { + return NULL; + } + return &route->entry; } #endif diff --git a/net/route/net_del_fileroute.c b/net/route/net_del_fileroute.c index dff88fe7dff64..5c232ec0309fa 100644 --- a/net/route/net_del_fileroute.c +++ b/net/route/net_del_fileroute.c @@ -36,6 +36,7 @@ #include #include +#include "netlink/netlink.h" #include "route/fileroute.h" #include "route/cacheroute.h" #include "route/route.h" @@ -313,6 +314,8 @@ int net_delroute_ipv4(in_addr_t target, in_addr_t netmask) filesize = (nentries - 1) * sizeof(struct net_route_ipv4_s); ret = file_truncate(&fshandle, filesize); + netlink_route_notify(&match, RTM_DELROUTE, AF_INET); + errout_with_fshandle: net_closeroute_ipv4(&fshandle); @@ -464,6 +467,8 @@ int net_delroute_ipv6(net_ipv6addr_t target, net_ipv6addr_t netmask) filesize = (nentries - 1) * sizeof(struct net_route_ipv6_s); ret = file_truncate(&fshandle, filesize); + netlink_route_notify(&match, RTM_DELROUTE, AF_INET6); + errout_with_fshandle: net_closeroute_ipv6(&fshandle); diff --git a/net/route/net_del_ramroute.c b/net/route/net_del_ramroute.c index 5914dd46d2469..71e8b067b725f 100644 --- a/net/route/net_del_ramroute.c +++ b/net/route/net_del_ramroute.c @@ -32,6 +32,7 @@ #include #include +#include "netlink/netlink.h" #include "route/ramroute.h" #include "route/route.h" @@ -64,10 +65,10 @@ struct route_match_ipv6_s ****************************************************************************/ /**************************************************************************** - * Name: net_match_ipv4 + * Name: net_del_ipv4route * * Description: - * Return 1 if the route is available + * Return 1 if the route is available, and delete the match route * * Input Parameters: * route - The next route to examine @@ -79,7 +80,8 @@ struct route_match_ipv6_s ****************************************************************************/ #ifdef CONFIG_ROUTE_IPv4_RAMROUTE -static int net_match_ipv4(FAR struct net_route_ipv4_s *route, FAR void *arg) +static int net_del_ipv4route(FAR struct net_route_ipv4_s *route, + FAR void *arg) { FAR struct route_match_ipv4_s *match = (FAR struct route_match_ipv4_s *)arg; @@ -109,6 +111,8 @@ static int net_match_ipv4(FAR struct net_route_ipv4_s *route, FAR void *arg) ramroute_ipv4_remfirst(&g_ipv4_routes); } + netlink_route_notify(route, RTM_DELROUTE, AF_INET); + /* And free the routing table entry by adding it to the free list */ net_freeroute_ipv4(route); @@ -126,8 +130,8 @@ static int net_match_ipv4(FAR struct net_route_ipv4_s *route, FAR void *arg) #endif #ifdef CONFIG_ROUTE_IPv6_RAMROUTE -static int net_match_ipv6( - FAR struct net_route_ipv6_s *route, FAR void *arg) +static int net_del_ipv6route(FAR struct net_route_ipv6_s *route, + FAR void *arg) { FAR struct route_match_ipv6_s *match = (FAR struct route_match_ipv6_s *)arg; @@ -165,6 +169,8 @@ static int net_match_ipv6( ramroute_ipv6_remfirst(&g_ipv6_routes); } + netlink_route_notify(route, RTM_DELROUTE, AF_INET6); + /* And free the routing table entry by adding it to the free list */ net_freeroute_ipv6(route); @@ -211,7 +217,7 @@ int net_delroute_ipv4(in_addr_t target, in_addr_t netmask) /* Then remove the entry from the routing table */ - return net_foreachroute_ipv4(net_match_ipv4, &match) ? OK : -ENOENT; + return net_foreachroute_ipv4(net_del_ipv4route, &match) ? OK : -ENOENT; } #endif @@ -228,7 +234,7 @@ int net_delroute_ipv6(net_ipv6addr_t target, net_ipv6addr_t netmask) /* Then remove the entry from the routing table */ - return net_foreachroute_ipv6(net_match_ipv6, &match) ? OK : -ENOENT; + return net_foreachroute_ipv6(net_del_ipv6route, &match) ? OK : -ENOENT; } #endif diff --git a/net/route/net_router.c b/net/route/net_router.c index 1ccea8fa4964b..c1a135685c81a 100644 --- a/net/route/net_router.c +++ b/net/route/net_router.c @@ -35,6 +35,7 @@ #include "devif/devif.h" #include "route/cacheroute.h" #include "route/route.h" +#include "utils/utils.h" #if defined(CONFIG_NET) && defined(CONFIG_NET_ROUTE) @@ -42,7 +43,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_ROUTE_IPv6_CACHEROUTE +#ifdef CONFIG_ROUTE_IPv4_CACHEROUTE # define IPv4_ROUTER entry.router #else # define IPv4_ROUTER router @@ -67,6 +68,14 @@ struct route_ipv4_match_s #else in_addr_t router; /* IPv4 address of router a local networks */ #endif +#ifdef CONFIG_ROUTE_LONGEST_MATCH + /* Only match prefix longer than prefixlen, equals to entry.netmask if we + * have got a match (then we only find longer prefix later). + * Range: -1 ~ 32 + */ + + int8_t prefixlen; +#endif }; #endif @@ -79,6 +88,14 @@ struct route_ipv6_match_s #else net_ipv6addr_t router; /* IPv6 address of router a local networks */ #endif +#ifdef CONFIG_ROUTE_LONGEST_MATCH + /* Only match prefix longer than prefixlen, equals to entry.netmask if we + * have got a match (then we only find longer prefix later). + * Range: -1 ~ 128 + */ + + int16_t prefixlen; +#endif }; #endif @@ -106,13 +123,20 @@ static int net_ipv4_match(FAR struct net_route_ipv4_s *route, FAR void *arg) { FAR struct route_ipv4_match_s *match = (FAR struct route_ipv4_match_s *)arg; +#ifdef CONFIG_ROUTE_LONGEST_MATCH + int8_t prefixlen = (int8_t)net_ipv4_mask2pref(route->netmask); +#endif /* To match, the masked target addresses must be the same. In the event * of multiple matches, only the first is returned. There is not (yet) any * concept for the precedence of networks. */ - if (net_ipv4addr_maskcmp(route->target, match->target, route->netmask)) + if (net_ipv4addr_maskcmp(route->target, match->target, route->netmask) +#ifdef CONFIG_ROUTE_LONGEST_MATCH + && prefixlen > match->prefixlen +#endif + ) { #ifdef CONFIG_ROUTE_IPv4_CACHEROUTE /* They match.. Copy the entire routing table entry */ @@ -123,7 +147,13 @@ static int net_ipv4_match(FAR struct net_route_ipv4_s *route, FAR void *arg) net_ipv4addr_copy(match->router, route->router); #endif +#ifdef CONFIG_ROUTE_LONGEST_MATCH + /* Cache the prefix length */ + + match->prefixlen = prefixlen; +#else return 1; +#endif } return 0; @@ -150,13 +180,20 @@ static int net_ipv6_match(FAR struct net_route_ipv6_s *route, FAR void *arg) { FAR struct route_ipv6_match_s *match = (FAR struct route_ipv6_match_s *)arg; +#ifdef CONFIG_ROUTE_LONGEST_MATCH + int16_t prefixlen = (int16_t)net_ipv6_mask2pref(route->netmask); +#endif /* To match, the masked target addresses must be the same. In the event * of multiple matches, only the first is returned. There is not (yet) any * concept for the precedence of networks. */ - if (net_ipv6addr_maskcmp(route->target, match->target, route->netmask)) + if (net_ipv6addr_maskcmp(route->target, match->target, route->netmask) +#ifdef CONFIG_ROUTE_LONGEST_MATCH + && prefixlen > match->prefixlen +#endif + ) { #ifdef CONFIG_ROUTE_IPv6_CACHEROUTE /* They match.. Copy the entire routing table entry */ @@ -167,7 +204,13 @@ static int net_ipv6_match(FAR struct net_route_ipv6_s *route, FAR void *arg) net_ipv6addr_copy(match->router, route->router); #endif +#ifdef CONFIG_ROUTE_LONGEST_MATCH + /* Cache the prefix length */ + + match->prefixlen = prefixlen; +#else return 1; +#endif } return 0; @@ -186,9 +229,12 @@ static int net_ipv6_match(FAR struct net_route_ipv6_s *route, FAR void *arg) * router on a local network that can forward to the external network. * * Input Parameters: - * target - An IPv4 address on a remote network to use in the lookup. - * router - The address of router on a local network that can forward our - * packets to the target. + * target - An IPv4 address on a remote network to use in the lookup. + * router - The address of router on a local network that can forward + * our packets to the target. + * prefixlen - The prefix length of previously matched routes (maybe on + * device), will only match prefix longer than prefixlen. + * Range: -1(match all) ~ 32(match none) * * Returned Value: * OK on success; Negated errno on failure. @@ -196,11 +242,19 @@ static int net_ipv6_match(FAR struct net_route_ipv6_s *route, FAR void *arg) ****************************************************************************/ #ifdef CONFIG_NET_IPv4 -int net_ipv4_router(in_addr_t target, FAR in_addr_t *router) +int net_ipv4_router(in_addr_t target, FAR in_addr_t *router, + int8_t prefixlen) { struct route_ipv4_match_s match; int ret; + /* Just early return for long prefix, maybe already got exact match. */ + + if (prefixlen >= 32) + { + return -ENOENT; + } + /* Do not route the special broadcast IP address */ if (net_ipv4addr_cmp(target, INADDR_BROADCAST)) @@ -212,6 +266,9 @@ int net_ipv4_router(in_addr_t target, FAR in_addr_t *router) memset(&match, 0, sizeof(struct route_ipv4_match_s)); net_ipv4addr_copy(match.target, target); +#ifdef CONFIG_ROUTE_LONGEST_MATCH + match.prefixlen = prefixlen; +#endif #ifdef CONFIG_ROUTE_IPv4_CACHEROUTE /* First see if we can find a router entry in the cache */ @@ -229,7 +286,12 @@ int net_ipv4_router(in_addr_t target, FAR in_addr_t *router) /* Did we find a route? */ +#ifdef CONFIG_ROUTE_LONGEST_MATCH + UNUSED(ret); + if (match.prefixlen <= prefixlen) +#else if (ret <= 0) +#endif { /* No.. there is no route for this address */ @@ -261,9 +323,12 @@ int net_ipv4_router(in_addr_t target, FAR in_addr_t *router) * router on a local network that can forward to the external network. * * Input Parameters: - * target - An IPv6 address on a remote network to use in the lookup. - * router - The address of router on a local network that can forward our - * packets to the target. + * target - An IPv6 address on a remote network to use in the lookup. + * router - The address of router on a local network that can forward + * our packets to the target. + * prefixlen - The prefix length of previously matched routes (maybe on + * device), will only match prefix longer than prefixlen. + * Range: -1(match all) ~ 128(match none) * * Returned Value: * OK on success; Negated errno on failure. @@ -271,11 +336,19 @@ int net_ipv4_router(in_addr_t target, FAR in_addr_t *router) ****************************************************************************/ #ifdef CONFIG_NET_IPv6 -int net_ipv6_router(const net_ipv6addr_t target, net_ipv6addr_t router) +int net_ipv6_router(const net_ipv6addr_t target, net_ipv6addr_t router, + int16_t prefixlen) { struct route_ipv6_match_s match; int ret; + /* Just early return for long prefix, maybe already got exact match. */ + + if (prefixlen >= 128) + { + return -ENOENT; + } + /* Do not route to any the special IPv6 multicast addresses */ if (target[0] == HTONS(0xff02)) @@ -287,6 +360,9 @@ int net_ipv6_router(const net_ipv6addr_t target, net_ipv6addr_t router) memset(&match, 0, sizeof(struct route_ipv6_match_s)); net_ipv6addr_copy(match.target, target); +#ifdef CONFIG_ROUTE_LONGEST_MATCH + match.prefixlen = prefixlen; +#endif #ifdef CONFIG_ROUTE_IPv6_CACHEROUTE /* First see if we can find a router entry in the cache */ @@ -304,7 +380,12 @@ int net_ipv6_router(const net_ipv6addr_t target, net_ipv6addr_t router) /* Did we find a route? */ +#ifdef CONFIG_ROUTE_LONGEST_MATCH + UNUSED(ret); + if (match.prefixlen <= prefixlen) +#else if (ret <= 0) +#endif { /* No.. there is no route for this address */ diff --git a/net/route/netdev_router.c b/net/route/netdev_router.c index 348e702281114..8ba711736e769 100644 --- a/net/route/netdev_router.c +++ b/net/route/netdev_router.c @@ -34,6 +34,7 @@ #include "netdev/netdev.h" #include "route/cacheroute.h" #include "route/route.h" +#include "utils/utils.h" #if defined(CONFIG_NET) && defined(CONFIG_NET_ROUTE) @@ -41,7 +42,7 @@ * Pre-processor Definitions ****************************************************************************/ -#ifdef CONFIG_ROUTE_IPv6_CACHEROUTE +#ifdef CONFIG_ROUTE_IPv4_CACHEROUTE # define IPv4_ROUTER entry.router #else # define IPv4_ROUTER router @@ -67,6 +68,14 @@ struct route_ipv4_devmatch_s #else in_addr_t router; /* IPv4 address of router a local networks */ #endif +#ifdef CONFIG_ROUTE_LONGEST_MATCH + /* Only match prefix longer than prefixlen, equals to entry.netmask if we + * have got a match (then we only find longer prefix later). + * Range: -1 ~ 32 + */ + + int8_t prefixlen; +#endif }; #endif @@ -80,6 +89,14 @@ struct route_ipv6_devmatch_s #else net_ipv6addr_t router; /* IPv6 address of router a local networks */ #endif +#ifdef CONFIG_ROUTE_LONGEST_MATCH + /* Only match prefix longer than prefixlen, equals to entry.netmask if we + * have got a match (then we only find longer prefix later). + * Range: -1 ~ 128 + */ + + int16_t prefixlen; +#endif }; #endif @@ -109,16 +126,24 @@ static int net_ipv4_devmatch(FAR struct net_route_ipv4_s *route, FAR struct route_ipv4_devmatch_s *match = (FAR struct route_ipv4_devmatch_s *)arg; FAR struct net_driver_s *dev = match->dev; +#ifdef CONFIG_ROUTE_LONGEST_MATCH + int8_t prefixlen = (int8_t)net_ipv4_mask2pref(route->netmask); +#endif /* To match, (1) the masked target addresses must be the same, and (2) the * router address must like on the network provided by the device. * - * In the event of multiple matches, only the first is returned. There - * not (yet) any concept for the precedence of networks. + * In the event of multiple matches, we try to get the longest prefix if + * CONFIG_ROUTE_LONGEST_MATCH is set, otherwise only the first match is + * returned. */ if (net_ipv4addr_maskcmp(route->target, match->target, route->netmask) && - net_ipv4addr_maskcmp(route->router, dev->d_ipaddr, dev->d_netmask)) + net_ipv4addr_maskcmp(route->router, dev->d_ipaddr, dev->d_netmask) +#ifdef CONFIG_ROUTE_LONGEST_MATCH + && prefixlen > match->prefixlen +#endif + ) { #ifdef CONFIG_ROUTE_IPv4_CACHEROUTE /* They match.. Copy the entire routing table entry */ @@ -129,7 +154,13 @@ static int net_ipv4_devmatch(FAR struct net_route_ipv4_s *route, net_ipv4addr_copy(match->router, route->router); #endif +#ifdef CONFIG_ROUTE_LONGEST_MATCH + /* Cache the prefix length */ + + match->prefixlen = prefixlen; +#else return 1; +#endif } return 0; @@ -158,16 +189,24 @@ static int net_ipv6_devmatch(FAR struct net_route_ipv6_s *route, FAR struct route_ipv6_devmatch_s *match = (FAR struct route_ipv6_devmatch_s *)arg; FAR struct net_driver_s *dev = match->dev; +#ifdef CONFIG_ROUTE_LONGEST_MATCH + int16_t prefixlen = (int16_t)net_ipv6_mask2pref(route->netmask); +#endif /* To match, (1) the masked target addresses must be the same, and (2) the * router address must like on the network provided by the device. * - * In the event of multiple matches, only the first is returned. There - * not (yet) any concept for the precedence of networks. + * In the event of multiple matches, we try to get the longest prefix if + * CONFIG_ROUTE_LONGEST_MATCH is set, otherwise only the first match is + * returned. */ if (net_ipv6addr_maskcmp(route->target, match->target, route->netmask) && - NETDEV_V6ADDR_ONLINK(dev, route->router)) + NETDEV_V6ADDR_ONLINK(dev, route->router) +#ifdef CONFIG_ROUTE_LONGEST_MATCH + && prefixlen > match->prefixlen +#endif + ) { #ifdef CONFIG_ROUTE_IPv6_CACHEROUTE /* They match.. Copy the entire routing table entry */ @@ -178,7 +217,13 @@ static int net_ipv6_devmatch(FAR struct net_route_ipv6_s *route, net_ipv6addr_copy(match->router, route->router); #endif +#ifdef CONFIG_ROUTE_LONGEST_MATCH + /* Cache the prefix length */ + + match->prefixlen = prefixlen; +#else return 1; +#endif } return 0; @@ -222,6 +267,9 @@ void netdev_ipv4_router(FAR struct net_driver_s *dev, in_addr_t target, memset(&match, 0, sizeof(struct route_ipv4_devmatch_s)); match.dev = dev; net_ipv4addr_copy(match.target, target); +#ifdef CONFIG_ROUTE_LONGEST_MATCH + match.prefixlen = -1; +#endif #ifdef CONFIG_ROUTE_IPv4_CACHEROUTE /* First see if we can find a router entry in the cache */ @@ -239,7 +287,12 @@ void netdev_ipv4_router(FAR struct net_driver_s *dev, in_addr_t target, /* Did we find a route? */ +#ifdef CONFIG_ROUTE_LONGEST_MATCH + UNUSED(ret); + if (match.prefixlen >= 0) +#else if (ret > 0) +#endif { /* We found a route. */ @@ -301,6 +354,9 @@ void netdev_ipv6_router(FAR struct net_driver_s *dev, memset(&match, 0, sizeof(struct route_ipv6_devmatch_s)); match.dev = dev; net_ipv6addr_copy(match.target, target); +#ifdef CONFIG_ROUTE_LONGEST_MATCH + match.prefixlen = -1; +#endif #ifdef CONFIG_ROUTE_IPv6_CACHEROUTE /* First see if we can find a router entry in the cache */ @@ -318,7 +374,12 @@ void netdev_ipv6_router(FAR struct net_driver_s *dev, /* Did we find a route? */ +#ifdef CONFIG_ROUTE_LONGEST_MATCH + UNUSED(ret); + if (match.prefixlen >= 0) +#else if (ret > 0) +#endif { /* We found a route. */ diff --git a/net/route/route.h b/net/route/route.h index 7548c216c9ecb..d018b166501dd 100644 --- a/net/route/route.h +++ b/net/route/route.h @@ -159,9 +159,12 @@ int net_delroute_ipv6(net_ipv6addr_t target, net_ipv6addr_t netmask); * router on a local network that can forward to the external network. * * Input Parameters: - * target - An IPv4 address on a remote network to use in the lookup. - * router - The address of router on a local network that can forward our - * packets to the target. + * target - An IPv4 address on a remote network to use in the lookup. + * router - The address of router on a local network that can forward + * our packets to the target. + * prefixlen - The prefix length of previously matched routes (maybe on + * device), will only match prefix longer than prefixlen. + * Range: -1(match all) ~ 32(match none) * * Returned Value: * OK on success; Negated errno on failure. @@ -169,7 +172,8 @@ int net_delroute_ipv6(net_ipv6addr_t target, net_ipv6addr_t netmask); ****************************************************************************/ #ifdef CONFIG_NET_IPv4 -int net_ipv4_router(in_addr_t target, FAR in_addr_t *router); +int net_ipv4_router(in_addr_t target, FAR in_addr_t *router, + int8_t prefixlen); #endif /**************************************************************************** @@ -180,9 +184,12 @@ int net_ipv4_router(in_addr_t target, FAR in_addr_t *router); * router on a local network that can forward to the external network. * * Input Parameters: - * target - An IPv6 address on a remote network to use in the lookup. - * router - The address of router on a local network that can forward our - * packets to the target. + * target - An IPv6 address on a remote network to use in the lookup. + * router - The address of router on a local network that can forward + * our packets to the target. + * prefixlen - The prefix length of previously matched routes (maybe on + * device), will only match prefix longer than prefixlen. + * Range: -1(match all) ~ 128(match none) * * Returned Value: * OK on success; Negated errno on failure. @@ -190,7 +197,8 @@ int net_ipv4_router(in_addr_t target, FAR in_addr_t *router); ****************************************************************************/ #ifdef CONFIG_NET_IPv6 -int net_ipv6_router(const net_ipv6addr_t target, net_ipv6addr_t router); +int net_ipv6_router(const net_ipv6addr_t target, net_ipv6addr_t router, + int16_t prefixlen); #endif /**************************************************************************** diff --git a/net/rpmsg/Kconfig b/net/rpmsg/Kconfig index b876c61651da5..4767abd8eee90 100644 --- a/net/rpmsg/Kconfig +++ b/net/rpmsg/Kconfig @@ -8,7 +8,7 @@ menu "RPMSG Socket Support" config NET_RPMSG bool "RPMSG domain (remote) sockets" - depends on RPTUN + depends on RPMSG default n ---help--- Enable or disable RPMSG (aka remote) sockets. diff --git a/net/rpmsg/rpmsg_sockif.c b/net/rpmsg/rpmsg_sockif.c index 4ff98382048f6..46eadc27f48c2 100644 --- a/net/rpmsg/rpmsg_sockif.c +++ b/net/rpmsg/rpmsg_sockif.c @@ -146,7 +146,7 @@ static int rpmsg_socket_bind(FAR struct socket *psock, static int rpmsg_socket_getsockname(FAR struct socket *psock, FAR struct sockaddr *addr, FAR socklen_t *addrlen); -static int rpmsg_socket_getconnname(FAR struct socket *psock, +static int rpmsg_socket_getpeername(FAR struct socket *psock, FAR struct sockaddr *addr, FAR socklen_t *addrlen); static int rpmsg_socket_listen(FAR struct socket *psock, int backlog); @@ -184,7 +184,7 @@ const struct sock_intf_s g_rpmsg_sockif = rpmsg_socket_addref, /* si_addref */ rpmsg_socket_bind, /* si_bind */ rpmsg_socket_getsockname, /* si_getsockname */ - rpmsg_socket_getconnname, /* si_getconnname */ + rpmsg_socket_getpeername, /* si_getpeername */ rpmsg_socket_listen, /* si_listen */ rpmsg_socket_connect, /* si_connect */ rpmsg_socket_accept, /* si_accept */ @@ -673,13 +673,13 @@ static int rpmsg_socket_getsockname(FAR struct socket *psock, if (ret >= 0) { strlcpy(((struct sockaddr_rpmsg *)addr)->rp_cpu, - CONFIG_RPTUN_LOCAL_CPUNAME, RPMSG_SOCKET_CPU_SIZE); + CONFIG_RPMSG_LOCAL_CPUNAME, RPMSG_SOCKET_CPU_SIZE); } return ret; } -static int rpmsg_socket_getconnname(FAR struct socket *psock, +static int rpmsg_socket_getpeername(FAR struct socket *psock, FAR struct sockaddr *addr, FAR socklen_t *addrlen) { @@ -1301,7 +1301,7 @@ static ssize_t rpmsg_socket_recvmsg(FAR struct socket *psock, _SO_TIMEOUT(conn->sconn.s_rcvtimeo)); if (!conn->ept.rdev || conn->unbind) { - ret = -ECONNRESET; + ret = 0; } nxmutex_lock(&conn->recvlock); @@ -1374,14 +1374,14 @@ static void rpmsg_socket_path(FAR struct rpmsg_socket_conn_s *conn, { snprintf(buf, len, "rpmsg:[%s:[%s%s]<->%s]", - CONFIG_RPTUN_LOCAL_CPUNAME, conn->rpaddr.rp_name, + CONFIG_RPMSG_LOCAL_CPUNAME, conn->rpaddr.rp_name, conn->nameid, conn->rpaddr.rp_cpu); } else /* Client */ { snprintf(buf, len, "rpmsg:[%s<->%s:[%s%s]]", - CONFIG_RPTUN_LOCAL_CPUNAME, conn->rpaddr.rp_cpu, + CONFIG_RPMSG_LOCAL_CPUNAME, conn->rpaddr.rp_cpu, conn->rpaddr.rp_name, conn->nameid); } } diff --git a/net/tcp/tcp_conn.c b/net/tcp/tcp_conn.c index 8b721a2edfa76..1ffa35fa0ed48 100644 --- a/net/tcp/tcp_conn.c +++ b/net/tcp/tcp_conn.c @@ -514,8 +514,8 @@ static FAR struct tcp_conn_s *tcp_alloc_conn(void) if (dq_peek(&g_free_tcp_connections) == NULL) { #if CONFIG_NET_TCP_MAX_CONNS > 0 - if (dq_count(&g_active_tcp_connections) + CONFIG_NET_TCP_ALLOC_CONNS - >= CONFIG_NET_TCP_MAX_CONNS) + if (dq_count(&g_active_tcp_connections) + + CONFIG_NET_TCP_ALLOC_CONNS > CONFIG_NET_TCP_MAX_CONNS) { return NULL; } @@ -583,42 +583,34 @@ int tcp_selectport(uint8_t domain, if (g_last_tcp_port == 0) { - net_getrandom(&g_last_tcp_port, sizeof(uint16_t)); - - g_last_tcp_port = g_last_tcp_port % 32000; - - if (g_last_tcp_port < 4096) - { - g_last_tcp_port += 4096; - } + NET_PORT_RANDOM_INIT(g_last_tcp_port); } if (portno == 0) { + uint16_t loop_start = g_last_tcp_port; + /* No local port assigned. Loop until we find a valid listen port - * number that is not being used by any other connection. NOTE the - * following loop is assumed to terminate but could not if all - * 32000-4096+1 ports are in used (unlikely). + * number that is not being used by any other connection. */ do { /* Guess that the next available port number will be the one after - * the last port number assigned. Make sure that the port number - * is within range. + * the last port number assigned. */ - if (++g_last_tcp_port >= 32000) + NET_PORT_NEXT_NH(portno, g_last_tcp_port); + if (g_last_tcp_port == loop_start) { - g_last_tcp_port = 4096; - } + /* We have looped back, failed. */ - portno = HTONS(g_last_tcp_port); + return -EADDRINUSE; + } } while (tcp_listener(domain, ipaddr, portno) -#if defined(CONFIG_NET_NAT) && defined(CONFIG_NET_IPv4) - || (domain == PF_INET && - ipv4_nat_port_inuse(IP_PROTO_TCP, ipaddr->ipv4, portno)) +#ifdef CONFIG_NET_NAT + || nat_port_inuse(domain, IP_PROTO_TCP, ipaddr, portno) #endif ); } @@ -629,9 +621,8 @@ int tcp_selectport(uint8_t domain, */ if (tcp_listener(domain, ipaddr, portno) -#if defined(CONFIG_NET_NAT) && defined(CONFIG_NET_IPv4) - || (domain == PF_INET && - ipv4_nat_port_inuse(IP_PROTO_TCP, ipaddr->ipv4, portno)) +#ifdef CONFIG_NET_NAT + || nat_port_inuse(domain, IP_PROTO_TCP, ipaddr, portno) #endif ) { @@ -1319,7 +1310,7 @@ int tcp_bind(FAR struct tcp_conn_s *conn, FAR const struct sockaddr *addr) int tcp_connect(FAR struct tcp_conn_s *conn, FAR const struct sockaddr *addr) { int port; - int ret; + int ret = OK; /* The connection is expected to be in the TCP_ALLOCATED state.. i.e., * allocated via up_tcpalloc(), but not yet put into the active connections @@ -1468,7 +1459,7 @@ int tcp_connect(FAR struct tcp_conn_s *conn, FAR const struct sockaddr *addr) #if defined(CONFIG_NET_ARP_SEND) || defined(CONFIG_NET_ICMPv6_NEIGHBOR) #ifdef CONFIG_NET_ARP_SEND -#ifdef CONFIG_NET_ICMPv6_NEIGHBOR +#if defined(CONFIG_NET_IPv4) && defined(CONFIG_NET_IPv6) if (conn->domain == PF_INET) #endif { @@ -1479,8 +1470,8 @@ int tcp_connect(FAR struct tcp_conn_s *conn, FAR const struct sockaddr *addr) #endif /* CONFIG_NET_ARP_SEND */ #ifdef CONFIG_NET_ICMPv6_NEIGHBOR -#ifdef CONFIG_NET_ARP_SEND - else +#if defined(CONFIG_NET_IPv4) && defined(CONFIG_NET_IPv6) + if (conn->domain == PF_INET6) #endif { /* Make sure that the IP address mapping is in the Neighbor Table */ diff --git a/net/tcp/tcp_getsockopt.c b/net/tcp/tcp_getsockopt.c index 5284716d2b192..e3cbdf7f0c856 100644 --- a/net/tcp/tcp_getsockopt.c +++ b/net/tcp/tcp_getsockopt.c @@ -133,23 +133,6 @@ int tcp_getsockopt(FAR struct socket *psock, int option, } break; - case TCP_NODELAY: /* Avoid coalescing of small segments. */ - if (*value_len < sizeof(int)) - { - ret = -EINVAL; - } - else - { - FAR int *nodelay = (FAR int *)value; - - /* Always true here since we do not support Nagle. */ - - *nodelay = 1; - *value_len = sizeof(int); - ret = OK; - } - break; - case TCP_KEEPIDLE: /* Start keepalives after this IDLE period */ case TCP_KEEPINTVL: /* Interval between keepalives */ { @@ -218,6 +201,23 @@ int tcp_getsockopt(FAR struct socket *psock, int option, break; #endif /* CONFIG_NET_TCP_KEEPALIVE */ + case TCP_NODELAY: /* Avoid coalescing of small segments. */ + if (*value_len < sizeof(int)) + { + ret = -EINVAL; + } + else + { + FAR int *nodelay = (FAR int *)value; + + /* Always true here since we do not support Nagle. */ + + *nodelay = 1; + *value_len = sizeof(int); + ret = OK; + } + break; + case TCP_MAXSEG: /* The maximum segment size */ if (*value_len < sizeof(int)) { diff --git a/net/tcp/tcp_input.c b/net/tcp/tcp_input.c index 77b1b06d089d0..07f297affad23 100644 --- a/net/tcp/tcp_input.c +++ b/net/tcp/tcp_input.c @@ -254,9 +254,11 @@ static bool tcp_snd_wnd_update(FAR struct tcp_conn_s *conn, conn->snd_wl1 = seq; conn->snd_wl2 = ackseq; - conn->snd_wnd = wnd; - - return true; + if (conn->snd_wnd != wnd) + { + conn->snd_wnd = wnd; + return true; + } } return false; diff --git a/net/tcp/tcp_send_buffered.c b/net/tcp/tcp_send_buffered.c index 874b8d5c0ebc3..f2558812cf34c 100644 --- a/net/tcp/tcp_send_buffered.c +++ b/net/tcp/tcp_send_buffered.c @@ -173,34 +173,6 @@ static void psock_writebuffer_notify(FAR struct tcp_conn_s *conn) static void retransmit_segment(FAR struct tcp_conn_s *conn, FAR struct tcp_wrbuffer_s *wrb) { - uint16_t sent; - - /* Reset the number of bytes sent sent from the write buffer */ - - sent = TCP_WBSENT(wrb); - if (conn->tx_unacked > sent) - { - conn->tx_unacked -= sent; - } - else - { - conn->tx_unacked = 0; - } - - if (conn->sent > sent) - { - conn->sent -= sent; - } - else - { - conn->sent = 0; - } - - TCP_WBSENT(wrb) = 0; - ninfo("REXMIT: wrb=%p sent=%u, " - "conn tx_unacked=%" PRId32 " sent=%" PRId32 "\n", - wrb, TCP_WBSENT(wrb), conn->tx_unacked, conn->sent); - /* Free any write buffers that have exceed the retry count */ if (++TCP_WBNRTX(wrb) >= TCP_MAXRTX) @@ -231,6 +203,36 @@ static void retransmit_segment(FAR struct tcp_conn_s *conn, } else { + uint16_t sent; + + sent = TCP_WBSENT(wrb); + + ninfo("REXMIT: wrb=%p sent=%u, " + "conn tx_unacked=%" PRId32 " sent=%" PRId32 "\n", + wrb, TCP_WBSENT(wrb), conn->tx_unacked, conn->sent); + + /* Reset the number of bytes sent sent from the write buffer */ + + if (conn->tx_unacked > sent) + { + conn->tx_unacked -= sent; + } + else + { + conn->tx_unacked = 0; + } + + if (conn->sent > sent) + { + conn->sent -= sent; + } + else + { + conn->sent = 0; + } + + TCP_WBSENT(wrb) = 0; + /* Insert the write buffer into the write_q (in sequence * number order). The retransmission will occur below * when the write buffer with the lowest sequence number @@ -859,35 +861,6 @@ static uint16_t psock_send_eventhandler(FAR struct net_driver_s *dev, if (wrb != NULL && TCP_WBSENT(wrb) > 0) { FAR struct tcp_wrbuffer_s *tmp; - uint16_t sent; - - /* Yes.. Reset the number of bytes sent sent from - * the write buffer - */ - - sent = TCP_WBSENT(wrb); - if (conn->tx_unacked > sent) - { - conn->tx_unacked -= sent; - } - else - { - conn->tx_unacked = 0; - } - - if (conn->sent > sent) - { - conn->sent -= sent; - } - else - { - conn->sent = 0; - } - - TCP_WBSENT(wrb) = 0; - ninfo("REXMIT: wrb=%p sent=%u, " - "conn tx_unacked=%" PRId32 " sent=%" PRId32 "\n", - wrb, TCP_WBSENT(wrb), conn->tx_unacked, conn->sent); /* Increment the retransmit count on this write buffer. */ @@ -924,6 +897,39 @@ static uint16_t psock_send_eventhandler(FAR struct net_driver_s *dev, conn->expired++; } + else + { + uint16_t sent; + + sent = TCP_WBSENT(wrb); + ninfo("REXMIT: wrb=%p sent=%u, " + "conn tx_unacked=%" PRId32 " sent=%" PRId32 "\n", + wrb, TCP_WBSENT(wrb), conn->tx_unacked, conn->sent); + + /* Yes.. Reset the number of bytes sent sent from + * the write buffer + */ + + if (conn->tx_unacked > sent) + { + conn->tx_unacked -= sent; + } + else + { + conn->tx_unacked = 0; + } + + if (conn->sent > sent) + { + conn->sent -= sent; + } + else + { + conn->sent = 0; + } + + TCP_WBSENT(wrb) = 0; + } } /* Move all segments that have been sent but not ACKed to the write @@ -1304,9 +1310,7 @@ ssize_t psock_tcp_send(FAR struct socket *psock, FAR const void *buf, #if defined(CONFIG_NET_ARP_SEND) || defined(CONFIG_NET_ICMPv6_NEIGHBOR) #ifdef CONFIG_NET_ARP_SEND -#ifdef CONFIG_NET_ICMPv6_NEIGHBOR if (psock->s_domain == PF_INET) -#endif { /* Make sure that the IP address mapping is in the ARP table */ @@ -1315,9 +1319,7 @@ ssize_t psock_tcp_send(FAR struct socket *psock, FAR const void *buf, #endif /* CONFIG_NET_ARP_SEND */ #ifdef CONFIG_NET_ICMPv6_NEIGHBOR -#ifdef CONFIG_NET_ARP_SEND - else -#endif + if (psock->s_domain == PF_INET6) { /* Make sure that the IP address mapping is in the Neighbor Table */ diff --git a/net/tcp/tcp_send_unbuffered.c b/net/tcp/tcp_send_unbuffered.c index c01c3c5a26380..4b4f9882b1440 100644 --- a/net/tcp/tcp_send_unbuffered.c +++ b/net/tcp/tcp_send_unbuffered.c @@ -508,9 +508,7 @@ ssize_t psock_tcp_send(FAR struct socket *psock, #if defined(CONFIG_NET_ARP_SEND) || defined(CONFIG_NET_ICMPv6_NEIGHBOR) #ifdef CONFIG_NET_ARP_SEND -#ifdef CONFIG_NET_ICMPv6_NEIGHBOR if (psock->s_domain == PF_INET) -#endif { /* Make sure that the IP address mapping is in the ARP table */ @@ -519,9 +517,7 @@ ssize_t psock_tcp_send(FAR struct socket *psock, #endif /* CONFIG_NET_ARP_SEND */ #ifdef CONFIG_NET_ICMPv6_NEIGHBOR -#ifdef CONFIG_NET_ARP_SEND - else -#endif + if (psock->s_domain == PF_INET6) { /* Make sure that the IP address mapping is in the Neighbor Table */ diff --git a/net/tcp/tcp_sendfile.c b/net/tcp/tcp_sendfile.c index 0cbac05fb13ce..6f27a806b2ce8 100644 --- a/net/tcp/tcp_sendfile.c +++ b/net/tcp/tcp_sendfile.c @@ -417,7 +417,7 @@ ssize_t tcp_sendfile(FAR struct socket *psock, FAR struct file *infile, FAR struct tcp_conn_s *conn; struct sendfile_s state; off_t startpos; - int ret; + int ret = OK; conn = psock->s_conn; DEBUGASSERT(conn != NULL); @@ -434,19 +434,16 @@ ssize_t tcp_sendfile(FAR struct socket *psock, FAR struct file *infile, #if defined(CONFIG_NET_ARP_SEND) || defined(CONFIG_NET_ICMPv6_NEIGHBOR) #ifdef CONFIG_NET_ARP_SEND -#ifdef CONFIG_NET_ICMPv6_NEIGHBOR if (psock->s_domain == PF_INET) -#endif { /* Make sure that the IP address mapping is in the ARP table */ ret = arp_send(conn->u.ipv4.raddr); } #endif /* CONFIG_NET_ARP_SEND */ + #ifdef CONFIG_NET_ICMPv6_NEIGHBOR -#ifdef CONFIG_NET_ARP_SEND - else -#endif + if (psock->s_domain == PF_INET6) { /* Make sure that the IP address mapping is in the Neighbor Table */ diff --git a/net/tcp/tcp_setsockopt.c b/net/tcp/tcp_setsockopt.c index fdbb58df93052..ba2bdf6522ad8 100644 --- a/net/tcp/tcp_setsockopt.c +++ b/net/tcp/tcp_setsockopt.c @@ -130,23 +130,6 @@ int tcp_setsockopt(FAR struct socket *psock, int option, } break; - case TCP_NODELAY: /* Avoid coalescing of small segments. */ - if (value_len != sizeof(int)) - { - ret = -EDOM; - } - else - { - int nodelay = *(FAR int *)value; - - if (!nodelay) - { - nerr("ERROR: TCP_NODELAY not supported\n"); - ret = -ENOSYS; - } - } - break; - case TCP_KEEPIDLE: /* Start keepalives after this IDLE period */ case TCP_KEEPINTVL: /* Interval between keepalives */ { @@ -230,6 +213,23 @@ int tcp_setsockopt(FAR struct socket *psock, int option, break; #endif /* CONFIG_NET_TCP_KEEPALIVE */ + case TCP_NODELAY: /* Avoid coalescing of small segments. */ + if (value_len != sizeof(int)) + { + ret = -EDOM; + } + else + { + int nodelay = *(FAR int *)value; + + if (!nodelay) + { + nerr("ERROR: TCP_NODELAY not supported\n"); + ret = -ENOSYS; + } + } + break; + case TCP_MAXSEG: /* The maximum segment size */ if (value_len != sizeof(int)) { diff --git a/net/udp/udp.h b/net/udp/udp.h index 8b8aa4bfe106a..f596ebf3dc1cf 100644 --- a/net/udp/udp.h +++ b/net/udp/udp.h @@ -237,6 +237,7 @@ void udp_free(FAR struct udp_conn_s *conn); ****************************************************************************/ FAR struct udp_conn_s *udp_active(FAR struct net_driver_s *dev, + FAR struct udp_conn_s *conn, FAR struct udp_hdr_s *udp); /**************************************************************************** @@ -264,6 +265,9 @@ FAR struct udp_conn_s *udp_nextconn(FAR struct udp_conn_s *conn); * implementation, it is reasonable to assume that that error cannot happen * and that a port number will always be available. * + * Returned Value: + * Next available port number in host byte order, 0 for failure. + * ****************************************************************************/ uint16_t udp_select_port(uint8_t domain, FAR union ip_binding_u *u); diff --git a/net/udp/udp_conn.c b/net/udp/udp_conn.c index 49fa9c3f54acf..2bfc04e37f4bd 100644 --- a/net/udp/udp_conn.c +++ b/net/udp/udp_conn.c @@ -70,6 +70,7 @@ #include "socket/socket.h" #include "igmp/igmp.h" #include "udp/udp.h" +#include "utils/utils.h" /**************************************************************************** * Private Data @@ -188,15 +189,16 @@ static FAR struct udp_conn_s *udp_find_conn(uint8_t domain, #ifdef CONFIG_NET_IPv4 static inline FAR struct udp_conn_s * - udp_ipv4_active(FAR struct net_driver_s *dev, FAR struct udp_hdr_s *udp) +udp_ipv4_active(FAR struct net_driver_s *dev, FAR struct udp_conn_s *conn, + FAR struct udp_hdr_s *udp) { #ifdef CONFIG_NET_BROADCAST static const in_addr_t bcast = INADDR_BROADCAST; #endif FAR struct ipv4_hdr_s *ip = IPv4BUF; - FAR struct udp_conn_s *conn; - conn = (FAR struct udp_conn_s *)g_active_udp_connections.head; + conn = udp_nextconn(conn); + while (conn) { /* If the local UDP port is non-zero, the connection is considered @@ -330,12 +332,13 @@ static inline FAR struct udp_conn_s * #ifdef CONFIG_NET_IPv6 static inline FAR struct udp_conn_s * - udp_ipv6_active(FAR struct net_driver_s *dev, FAR struct udp_hdr_s *udp) +udp_ipv6_active(FAR struct net_driver_s *dev, FAR struct udp_conn_s *conn, + FAR struct udp_hdr_s *udp) { FAR struct ipv6_hdr_s *ip = IPv6BUF; - FAR struct udp_conn_s *conn; - conn = (FAR struct udp_conn_s *)g_active_udp_connections.head; + conn = udp_nextconn(conn); + while (conn != NULL) { /* If the local UDP port is non-zero, the connection is considered @@ -474,8 +477,8 @@ static FAR struct udp_conn_s *udp_alloc_conn(void) if (dq_peek(&g_free_udp_connections) == NULL) { #if CONFIG_NET_UDP_MAX_CONNS > 0 - if (dq_count(&g_active_udp_connections) + CONFIG_NET_UDP_ALLOC_CONNS - >= CONFIG_NET_UDP_MAX_CONNS) + if (dq_count(&g_active_udp_connections) + + CONFIG_NET_UDP_ALLOC_CONNS > CONFIG_NET_UDP_MAX_CONNS) { return NULL; } @@ -523,7 +526,7 @@ static FAR struct udp_conn_s *udp_alloc_conn(void) * None * * Returned Value: - * Next available port number + * Next available port number in host byte order, 0 for failure. * ****************************************************************************/ @@ -538,38 +541,30 @@ uint16_t udp_select_port(uint8_t domain, FAR union ip_binding_u *u) if (g_last_udp_port == 0) { - g_last_udp_port = clock_systime_ticks() % 32000; - - if (g_last_udp_port < 4096) - { - g_last_udp_port += 4096; - } + NET_PORT_RANDOM_INIT(g_last_udp_port); } /* Find an unused local port number. Loop until we find a valid * listen port number that is not being used by any other connection. */ + portno = g_last_udp_port; /* Record a starting port number */ + do { - /* Guess that the next available port number will be the one after - * the last port number assigned. - */ - - ++g_last_udp_port; - - /* Make sure that the port number is within range */ - - if (g_last_udp_port >= 32000) + NET_PORT_NEXT_H(g_last_udp_port); + if (g_last_udp_port == portno) { - g_last_udp_port = 4096; + /* We have looped back, failed. */ + + portno = 0; + goto errout; } } while (udp_find_conn(domain, u, HTONS(g_last_udp_port), 0) != NULL -#if defined(CONFIG_NET_NAT) && defined(CONFIG_NET_IPv4) - || (domain == PF_INET && - ipv4_nat_port_inuse(IP_PROTO_UDP, u->ipv4.laddr, - HTONS(g_last_udp_port))) +#ifdef CONFIG_NET_NAT + || nat_port_inuse(domain, IP_PROTO_UDP, (FAR union ip_addr_u *)u, + HTONS(g_last_udp_port)) #endif ); @@ -578,6 +573,8 @@ uint16_t udp_select_port(uint8_t domain, FAR union ip_binding_u *u) */ portno = g_last_udp_port; + +errout: net_unlock(); return portno; @@ -747,6 +744,7 @@ void udp_free(FAR struct udp_conn_s *conn) ****************************************************************************/ FAR struct udp_conn_s *udp_active(FAR struct net_driver_s *dev, + FAR struct udp_conn_s *conn, FAR struct udp_hdr_s *udp) { #ifdef CONFIG_NET_IPv6 @@ -754,7 +752,7 @@ FAR struct udp_conn_s *udp_active(FAR struct net_driver_s *dev, if (IFF_IS_IPv6(dev->d_flags)) #endif { - return udp_ipv6_active(dev, udp); + return udp_ipv6_active(dev, conn, udp); } #endif /* CONFIG_NET_IPv6 */ @@ -763,7 +761,7 @@ FAR struct udp_conn_s *udp_active(FAR struct net_driver_s *dev, else #endif { - return udp_ipv4_active(dev, udp); + return udp_ipv4_active(dev, conn, udp); } #endif /* CONFIG_NET_IPv4 */ } @@ -917,8 +915,16 @@ int udp_bind(FAR struct udp_conn_s *conn, FAR const struct sockaddr *addr) { /* Yes.. Select any unused local port number */ - conn->lport = HTONS(udp_select_port(conn->domain, &conn->u)); - ret = OK; + portno = HTONS(udp_select_port(conn->domain, &conn->u)); + if (portno == 0) + { + ret = -EADDRINUSE; + } + else + { + conn->lport = portno; + ret = OK; + } } else { @@ -937,10 +943,9 @@ int udp_bind(FAR struct udp_conn_s *conn, FAR const struct sockaddr *addr) 0 #endif ) == NULL -#if defined(CONFIG_NET_NAT) && defined(CONFIG_NET_IPv4) - && !(conn->domain == PF_INET && - ipv4_nat_port_inuse(IP_PROTO_UDP, conn->u.ipv4.laddr, - portno)) +#ifdef CONFIG_NET_NAT + && !nat_port_inuse(conn->domain, IP_PROTO_UDP, + (FAR union ip_addr_u *)&conn->u, portno) #endif ) { @@ -1000,6 +1005,11 @@ int udp_connect(FAR struct udp_conn_s *conn, FAR const struct sockaddr *addr) */ conn->lport = HTONS(udp_select_port(conn->domain, &conn->u)); + if (!conn->lport) + { + nerr("ERROR: Failed to get a local port!\n"); + return -EADDRINUSE; + } } /* Is there a remote port (rport)? */ diff --git a/net/udp/udp_input.c b/net/udp/udp_input.c index aff8e6e79c8b5..47d995ff63ecf 100644 --- a/net/udp/udp_input.c +++ b/net/udp/udp_input.c @@ -63,6 +63,125 @@ * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: udp_is_broadcast + * + * Description: + * Check if the destination address is a broadcast/multicast address. + * + * Input Parameters: + * dev - The device driver structure containing the received UDP packet + * + * Returned Value: + * True if the destination address is a broadcast/multicast address + * + ****************************************************************************/ + +#if defined(CONFIG_NET_SOCKOPTS) && defined(CONFIG_NET_BROADCAST) +static bool udp_is_broadcast(FAR struct net_driver_s *dev) +{ + /* Check if the destination address is a broadcast/multicast address */ + +#ifdef CONFIG_NET_IPv4 +# ifdef CONFIG_NET_IPv6 + if (IFF_IS_IPv4(dev->d_flags)) +# endif + { + FAR struct ipv4_hdr_s *ipv4 = IPv4BUF; + in_addr_t destipaddr = net_ip4addr_conv32(ipv4->destipaddr); + + return net_ipv4addr_cmp(destipaddr, INADDR_BROADCAST) || + IN_MULTICAST(NTOHL(destipaddr)) || + (net_ipv4addr_maskcmp(destipaddr, dev->d_ipaddr, dev->d_netmask) + && net_ipv4addr_broadcast(destipaddr, dev->d_netmask)); + } +#endif +#ifdef CONFIG_NET_IPv6 +# ifdef CONFIG_NET_IPv4 + else +# endif + { + FAR struct ipv6_hdr_s *ipv6 = IPv6BUF; + return net_is_addr_mcast(ipv6->destipaddr); + } +#endif + + return false; +} +#endif + +/**************************************************************************** + * Name: udp_input_conn + * + * Description: + * Handle incoming UDP input for the case where there is an active + * connection. + * + * Input Parameters: + * dev - The device driver structure containing the received UDP pkt + * conn - The UDP connection structure associated with the packet + * udpiplen - Length of the IP and UDP headers + * + * Returned Value: + * OK - The packet has been processed + * -EAGAIN - Hold the packet and try again later. There is a listening + * socket but no receive in place to catch the packet yet. The + * device's d_len will be set to zero in this case as there is + * no outgoing data. + * + * Assumptions: + * The network is locked. + * + ****************************************************************************/ + +static int udp_input_conn(FAR struct net_driver_s *dev, + FAR struct udp_conn_s *conn, unsigned int udpiplen) +{ + uint16_t flags; + + /* Set-up for the application callback */ + + dev->d_appdata = IPBUF(udpiplen); + dev->d_sndlen = 0; + + /* Perform the application callback */ + + flags = udp_callback(dev, conn, UDP_NEWDATA); + + /* If the operation was successful and the UDP data was "consumed," + * then the UDP_NEWDATA flag will be cleared by logic in + * udp_callback(). The packet memory can then be freed by the + * network driver. OK will be returned to the network driver to + * indicate this case. + * + * "Consumed" here means that either the received data was (1) + * accepted by a socket waiting for data on the port or was (2) + * buffered in the UDP socket's read-ahead buffer. + */ + + if ((flags & UDP_NEWDATA) != 0) + { + /* No.. the packet was not processed now. Return -EAGAIN so + * that the driver may retry again later. We still need to + * set d_len to zero so that the driver is aware that there + * is nothing to be sent. + */ + + nwarn("WARNING: Packet not processed\n"); + dev->d_len = 0; + return -EAGAIN; + } + + /* If the application has data to send, setup the UDP/IP header */ + + if (dev->d_sndlen > 0) + { + udp_send(dev, conn); + } + + return OK; +} + /**************************************************************************** * Name: udp_input * @@ -90,6 +209,10 @@ static int udp_input(FAR struct net_driver_s *dev, unsigned int iplen) { FAR struct udp_hdr_s *udp; FAR struct udp_conn_s *conn; +#if defined(CONFIG_NET_SOCKOPTS) && defined(CONFIG_NET_BROADCAST) + FAR struct udp_conn_s *nextconn; + FAR struct iob_s *iob; +#endif unsigned int udpiplen; #ifdef CONFIG_NET_UDP_CHECKSUMS uint16_t chksum; @@ -157,64 +280,54 @@ static int udp_input(FAR struct net_driver_s *dev, unsigned int iplen) { /* Demultiplex this UDP packet between the UDP "connections". * - * REVISIT: The logic here expects either a single receive socket or - * none at all. However, multiple sockets should be capable of - * receiving a UDP datagram (multicast reception). This could be - * handled easily by something like: - * - * for (conn = NULL; conn = udp_active(dev, udp); ) - * - * If the callback logic that receives a packet responds with an - * outgoing packet, then it will over-write the received buffer, - * however. recvfrom() will not do that, however. We would have to - * make that the rule: Recipients of a UDP packet must treat the - * packet as read-only. + * REVISIT: If the callback logic that receives a packet responds with + * an outgoing packet, then it may be ignored. recvfrom() will not do + * that, however. */ - conn = udp_active(dev, udp); + conn = udp_active(dev, NULL, udp); if (conn) { - uint16_t flags; - - /* Set-up for the application callback */ - - dev->d_appdata = IPBUF(udpiplen); - dev->d_sndlen = 0; + /* We'll only get multiple conn when we support SO_REUSEADDR */ - /* Perform the application callback */ +#if defined(CONFIG_NET_SOCKOPTS) && defined(CONFIG_NET_BROADCAST) + /* Check if the destination is a broadcast/multicast address */ - flags = udp_callback(dev, conn, UDP_NEWDATA); - - /* If the operation was successful and the UDP data was "consumed," - * then the UDP_NEWDATA flag will be cleared by logic in - * udp_callback(). The packet memory can then be freed by the - * network driver. OK will be returned to the network driver to - * indicate this case. - * - * "Consumed" here means that either the received data was (1) - * accepted by a socket waiting for data on the port or was (2) - * buffered in the UDP socket's read-ahead buffer. - */ - - if ((flags & UDP_NEWDATA) != 0) + if (udp_is_broadcast(dev)) { - /* No.. the packet was not processed now. Return -EAGAIN so - * that the driver may retry again later. We still need to - * set d_len to zero so that the driver is aware that there - * is nothing to be sent. - */ - - nwarn("WARNING: Packet not processed\n"); - dev->d_len = 0; - ret = -EAGAIN; + /* Do we have second connection that can hold this packet? */ + + while ((nextconn = udp_active(dev, conn, udp)) != NULL) + { + /* Yes... There are multiple listeners on the same port. + * We need to clone the packet and deliver it to each + * listener. + */ + + iob = netdev_iob_clone(dev, true); + if (iob == NULL) + { + nerr("ERROR: IOB clone failed.\n"); + break; /* We can still process once without clone. */ + } + + ret = udp_input_conn(dev, conn, udpiplen); + if (ret < 0) + { + nwarn("WARNING: A conn failed to process the pkt %d\n", + ret); /* We can still continue for next conn. */ + } + + netdev_iob_replace(dev, iob); + udp = IPBUF(iplen); + conn = nextconn; + } } +#endif - /* If the application has data to send, setup the UDP/IP header */ + /* We can deliver the packet directly to the last listener. */ - if (dev->d_sndlen > 0) - { - udp_send(dev, conn); - } + ret = udp_input_conn(dev, conn, udpiplen); } else { diff --git a/net/udp/udp_send.c b/net/udp/udp_send.c index 2e3180af949ba..27c90b92f91a0 100644 --- a/net/udp/udp_send.c +++ b/net/udp/udp_send.c @@ -58,9 +58,67 @@ #include "devif/devif.h" #include "inet/inet.h" +#include "socket/socket.h" #include "utils/utils.h" #include "udp/udp.h" +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: udp_send_loopback + * + * Description: + * Send a copy of the UDP packet to ourself. + * + * Input Parameters: + * dev - The device driver structure to use in the send operation + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_NET_SOCKOPTS) && \ + (defined(CONFIG_NET_IGMP) || defined(CONFIG_NET_MLD)) +static void udp_send_loopback(FAR struct net_driver_s *dev) +{ + FAR struct iob_s *iob = netdev_iob_clone(dev, true); + if (iob == NULL) + { + nerr("ERROR: IOB clone failed when looping UDP.\n"); + return; + } + +#ifdef CONFIG_NET_IPv4 +#ifdef CONFIG_NET_IPv6 + if (IFF_IS_IPv4(dev->d_flags)) +#endif + { + ninfo("IPv4 frame\n"); + NETDEV_RXIPV4(dev); + ipv4_input(dev); + } +#endif /* CONFIG_NET_IPv4 */ + +#ifdef CONFIG_NET_IPv6 +#ifdef CONFIG_NET_IPv4 + else +#endif + { + ninfo("IPv6 frame\n"); + NETDEV_RXIPV6(dev); + ipv6_input(dev); + } +#endif /* CONFIG_NET_IPv6 */ + + /* Restore device IOB with backup IOB */ + + netdev_iob_replace(dev, iob); +} +#endif + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -86,6 +144,9 @@ void udp_send(FAR struct net_driver_s *dev, FAR struct udp_conn_s *conn) { FAR struct udp_hdr_s *udp; +#ifdef CONFIG_NET_IPv6 + FAR const uint16_t *laddr; +#endif #ifdef CONFIG_NET_IPv4 in_addr_t raddr; #endif @@ -148,9 +209,16 @@ void udp_send(FAR struct net_driver_s *dev, FAR struct udp_conn_s *conn) dev->d_len = dev->d_sndlen + UDP_HDRLEN; + /* We use the laddr if the conn is bounded to an address, otherwise + * find a suitable source address corresponding to the raddr + */ + + laddr = !net_ipv6addr_cmp(conn->u.ipv6.laddr, g_ipv6_unspecaddr) ? + conn->u.ipv6.laddr : + netdev_ipv6_srcaddr(dev, conn->u.ipv6.raddr); + ipv6_build_header(IPv6BUF, dev->d_len, IP_PROTO_UDP, - netdev_ipv6_srcaddr(dev, conn->u.ipv6.laddr), - conn->u.ipv6.raddr, + laddr, conn->u.ipv6.raddr, conn->sconn.ttl, conn->sconn.s_tclass); /* The total length to send is the size of the application data @@ -182,9 +250,7 @@ void udp_send(FAR struct net_driver_s *dev, FAR struct udp_conn_s *conn) #ifdef CONFIG_NET_IPv4 #ifdef CONFIG_NET_IPv6 - if (conn->domain == PF_INET || - (conn->domain == PF_INET6 && - ip6_is_ipv4addr((FAR struct in6_addr *)conn->u.ipv6.raddr))) + if (IFF_IS_IPv4(dev->d_flags)) #endif { udp->udpchksum = ~udp_ipv4_chksum(dev); @@ -211,6 +277,32 @@ void udp_send(FAR struct net_driver_s *dev, FAR struct udp_conn_s *conn) #ifdef CONFIG_NET_STATISTICS g_netstats.udp.sent++; #endif + +#ifdef CONFIG_NET_SOCKOPTS + /* Try loopback multicast to ourself. */ + +#ifdef CONFIG_NET_IGMP + if (_SO_GETOPT(conn->sconn.s_options, IP_MULTICAST_LOOP) && +#ifdef CONFIG_NET_IPv6 + IFF_IS_IPv4(dev->d_flags) && +#endif + IN_MULTICAST(NTOHL(raddr))) + { + udp_send_loopback(dev); + } +#endif /* CONFIG_NET_IGMP */ + +#ifdef CONFIG_NET_MLD + if (_SO_GETOPT(conn->sconn.s_options, IPV6_MULTICAST_LOOP) && +#ifdef CONFIG_NET_IPv4 + IFF_IS_IPv6(dev->d_flags) && +#endif + IN6_IS_ADDR_MULTICAST((FAR struct in6_addr *)conn->u.ipv6.raddr)) + { + udp_send_loopback(dev); + } +#endif /* CONFIG_NET_MLD */ +#endif /* CONFIG_NET_SOCKOPTS */ } } diff --git a/net/udp/udp_sendto_buffered.c b/net/udp/udp_sendto_buffered.c index 18dd21c6e4457..67236db00b29b 100644 --- a/net/udp/udp_sendto_buffered.c +++ b/net/udp/udp_sendto_buffered.c @@ -151,12 +151,6 @@ static void sendto_writebuffer_release(FAR struct udp_conn_s *conn) wrb = (FAR struct udp_wrbuffer_s *)sq_remfirst(&conn->write_q); DEBUGASSERT(wrb != NULL); - /* Do not need to release wb_iob, the life cycle of wb_iob is - * handed over to the network device - */ - - wrb->wb_iob = NULL; - udp_wrbuffer_release(wrb); /* Set up for the next packet transfer by setting the connection @@ -263,6 +257,11 @@ static int sendto_next_transfer(FAR struct udp_conn_s *conn) */ conn->lport = HTONS(udp_select_port(conn->domain, &conn->u)); + if (!conn->lport) + { + nerr("ERROR: Failed to get a local port!\n"); + return -EADDRINUSE; + } } /* Get the device that will handle the remote packet transfers. This @@ -450,6 +449,12 @@ static uint16_t sendto_eventhandler(FAR struct net_driver_s *dev, dev->d_sndlen = wrb->wb_iob->io_pktlen - udpiplen; ninfo("wrb=%p sndlen=%d\n", wrb, dev->d_sndlen); + /* Do not need to release wb_iob, the life cycle of wb_iob is + * handed over to the network device + */ + + wrb->wb_iob = NULL; + #ifdef NEED_IPDOMAIN_SUPPORT /* If both IPv4 and IPv6 support are enabled, then we will need to * select which one to use when generating the outgoing packet. @@ -593,9 +598,7 @@ ssize_t psock_udp_sendto(FAR struct socket *psock, FAR const void *buf, * the ARP table. */ -#ifdef CONFIG_NET_ICMPv6_NEIGHBOR if (psock->s_domain == PF_INET) -#endif { in_addr_t destipaddr; @@ -632,9 +635,7 @@ ssize_t psock_udp_sendto(FAR struct socket *psock, FAR const void *buf, * the neighbor table. */ -#ifdef CONFIG_NET_ARP_SEND - else -#endif + if (psock->s_domain == PF_INET6) { FAR const uint16_t *destipaddr; @@ -792,6 +793,7 @@ ssize_t psock_udp_sendto(FAR struct socket *psock, FAR const void *buf, else { memcpy(&wrb->wb_dest, to, tolen); + udp_connect(conn, to); } /* Skip l2/l3/l4 offset before copy */ diff --git a/net/udp/udp_sendto_unbuffered.c b/net/udp/udp_sendto_unbuffered.c index 6e93c22a6dc22..b45625b7a3324 100644 --- a/net/udp/udp_sendto_unbuffered.c +++ b/net/udp/udp_sendto_unbuffered.c @@ -267,7 +267,7 @@ ssize_t psock_udp_sendto(FAR struct socket *psock, FAR const void *buf, { FAR struct udp_conn_s *conn; struct sendto_s state; - int ret; + int ret = OK; /* Verify that the sockfd corresponds to valid, allocated socket */ @@ -314,9 +314,7 @@ ssize_t psock_udp_sendto(FAR struct socket *psock, FAR const void *buf, * the ARP table. */ -#ifdef CONFIG_NET_ICMPv6_NEIGHBOR if (psock->s_domain == PF_INET) -#endif { in_addr_t destipaddr; @@ -353,9 +351,7 @@ ssize_t psock_udp_sendto(FAR struct socket *psock, FAR const void *buf, * the neighbor table. */ -#ifdef CONFIG_NET_ARP_SEND - else -#endif + if (psock->s_domain == PF_INET6) { FAR const uint16_t *destipaddr; diff --git a/net/usrsock/usrsock_conn.c b/net/usrsock/usrsock_conn.c index c11cf8de952e3..18b5eb5cbc7dc 100644 --- a/net/usrsock/usrsock_conn.c +++ b/net/usrsock/usrsock_conn.c @@ -90,7 +90,7 @@ FAR struct usrsock_conn_s *usrsock_alloc(void) { #if CONFIG_NET_USRSOCK_MAX_CONNS > 0 if (dq_count(&g_active_usrsock_connections) + - CONFIG_NET_USRSOCK_ALLOC_CONNS >= CONFIG_NET_USRSOCK_MAX_CONNS) + CONFIG_NET_USRSOCK_ALLOC_CONNS > CONFIG_NET_USRSOCK_MAX_CONNS) { nxmutex_unlock(&g_free_lock); return NULL; diff --git a/net/utils/CMakeLists.txt b/net/utils/CMakeLists.txt index 27868b2fcd38d..94dd7e70e431d 100644 --- a/net/utils/CMakeLists.txt +++ b/net/utils/CMakeLists.txt @@ -37,7 +37,7 @@ set(SRCS # IPv6 utilities if(CONFIG_NET_IPv6) - list(APPEND SRCS net_ipv6_maskcmp.c net_ipv6_pref2mask.c) + list(APPEND SRCS net_ipv6_maskcmp.c net_ipv6_pref2mask.c net_ipv6_payload.c) endif() # TCP utilities diff --git a/net/utils/Make.defs b/net/utils/Make.defs index 764dee148113b..5039a07980393 100644 --- a/net/utils/Make.defs +++ b/net/utils/Make.defs @@ -27,7 +27,7 @@ NET_CSRCS += net_cmsg.c net_iob_concat.c net_getrandom.c net_mask2pref.c # IPv6 utilities ifeq ($(CONFIG_NET_IPv6),y) -NET_CSRCS += net_ipv6_maskcmp.c net_ipv6_pref2mask.c +NET_CSRCS += net_ipv6_maskcmp.c net_ipv6_pref2mask.c net_ipv6_payload.c endif # TCP utilities diff --git a/net/utils/net_ipv6_payload.c b/net/utils/net_ipv6_payload.c new file mode 100644 index 0000000000000..fc1c5d89621be --- /dev/null +++ b/net/utils/net_ipv6_payload.c @@ -0,0 +1,74 @@ +/**************************************************************************** + * net/utils/net_ipv6_payload.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#ifdef CONFIG_NET_IPv6 + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: net_ipv6_payload + * + * Description: + * Given a pointer to the IPv6 header, this function will return a pointer + * to the beginning of the L4 payload. + * + * Input Parameters: + * ipv6 - A pointer to the IPv6 header. + * proto - The location to return the protocol number in the IPv6 header. + * + * Returned Value: + * A pointer to the beginning of the payload. + * + ****************************************************************************/ + +FAR void *net_ipv6_payload(FAR struct ipv6_hdr_s *ipv6, FAR uint8_t *proto) +{ + FAR struct ipv6_extension_s *exthdr; + FAR uint8_t *payload = (FAR uint8_t *)ipv6 + IPv6_HDRLEN; + uint8_t nxthdr = ipv6->proto; + uint16_t extlen; + + while (ipv6_exthdr(nxthdr)) + { + /* Just skip over the extension header */ + + exthdr = (FAR struct ipv6_extension_s *)payload; + extlen = EXTHDR_LEN(exthdr->len); + + payload += extlen; + nxthdr = exthdr->nxthdr; + } + + *proto = nxthdr; + return payload; +} + +#endif /* CONFIG_NET_IPv6 */ diff --git a/net/utils/utils.h b/net/utils/utils.h index 04fe60a442b6a..6cc68f893840d 100644 --- a/net/utils/utils.h +++ b/net/utils/utils.h @@ -30,6 +30,47 @@ #include #include +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some utils for port selection */ + +#define NET_PORT_RANDOM_INIT(port) \ + do \ + { \ + net_getrandom(&(port), sizeof(port)); \ + (port) = (port) % (CONFIG_NET_DEFAULT_MAX_PORT - \ + CONFIG_NET_DEFAULT_MIN_PORT + 1); \ + (port) += CONFIG_NET_DEFAULT_MIN_PORT; \ + } while (0) + +/* Get next net port number, and make sure that the port number is within + * range. In host byte order. + */ + +#define NET_PORT_NEXT_H(hport) \ + do \ + { \ + ++(hport); \ + if ((hport) > CONFIG_NET_DEFAULT_MAX_PORT || \ + (hport) < CONFIG_NET_DEFAULT_MIN_PORT) \ + { \ + (hport) = CONFIG_NET_DEFAULT_MIN_PORT; \ + } \ + } while (0) + +/* Get next net port number, and make sure that the port number is within + * range. In both network & host byte order. + */ + +#define NET_PORT_NEXT_NH(nport, hport) \ + do \ + { \ + NET_PORT_NEXT_H(hport); \ + (nport) = HTONS(hport); \ + } while (0) + /**************************************************************************** * Public Types ****************************************************************************/ @@ -254,6 +295,26 @@ uint8_t net_ipv6_mask2pref(FAR const uint16_t *mask); void net_ipv6_pref2mask(net_ipv6addr_t mask, uint8_t preflen); #endif +/**************************************************************************** + * Name: net_ipv6_payload + * + * Description: + * Given a pointer to the IPv6 header, this function will return a pointer + * to the beginning of the L4 payload. + * + * Input Parameters: + * ipv6 - A pointer to the IPv6 header. + * proto - The location to return the protocol number in the IPv6 header. + * + * Returned Value: + * A pointer to the beginning of the payload. + * + ****************************************************************************/ + +#ifdef CONFIG_NET_IPv6 +FAR void *net_ipv6_payload(FAR struct ipv6_hdr_s *ipv6, FAR uint8_t *proto); +#endif + /**************************************************************************** * Name: net_iob_concat * diff --git a/openamp/0003-libmetal-nuttx-io.c-Fix-void-pointer-arithmetic-in-a.patch b/openamp/0003-libmetal-nuttx-io.c-Fix-void-pointer-arithmetic-in-a.patch new file mode 100644 index 0000000000000..88ce403c93f8c --- /dev/null +++ b/openamp/0003-libmetal-nuttx-io.c-Fix-void-pointer-arithmetic-in-a.patch @@ -0,0 +1,36 @@ +From 59e2764f9d0598ad0135286d4a0ee1ac95893bba Mon Sep 17 00:00:00 2001 +From: Jukka Laitinen +Date: Mon, 12 Feb 2024 13:27:13 +0200 +Subject: [PATCH] libmetal/nuttx/io.c: Fix void pointer arithmetic in access + alignment + +Signed-off-by: Jukka Laitinen +--- + libmetal/lib/system/nuttx/io.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/lib/system/nuttx/io.c libmetal/lib/system/nuttx/io.c +index 3ce9cbe..ab9bc6a 100644 +--- a/lib/system/nuttx/io.c ++++ libmetal/lib/system/nuttx/io.c +@@ -45,7 +45,7 @@ static int metal_io_block_read_(struct metal_io_region *io, + *(uint32_t *)dst = *(uint32_t *)va; + else if (len == 8) { + *(uint32_t *)dst = *(uint32_t *)va; +- *(uint32_t *)(dst + 4) = *(uint32_t *)(va + 4); ++ *((uint32_t *)dst + 1) = *((uint32_t *)va + 1); + } else + memcpy(dst, va, len); + +@@ -68,7 +68,7 @@ static int metal_io_block_write_(struct metal_io_region *io, + *(uint32_t *)va = *(uint32_t *)src; + else if (len == 8) { + *(uint32_t *)va = *(uint32_t *)src; +- *(uint32_t *)(va + 4) = *(uint32_t *)(src + 4); ++ *((uint32_t *)va + 1) = *((uint32_t *)src + 1); + } else + memcpy(va, src, len); + +-- +2.34.1 + diff --git a/openamp/Kconfig b/openamp/Kconfig index bb1f7710074ea..f32d1a05364f2 100644 --- a/openamp/Kconfig +++ b/openamp/Kconfig @@ -4,7 +4,7 @@ # config OPENAMP - bool "Open Asymmetric Multi Processing support" + bool default n ---help--- Enable or disable Open Asymmetric Multi Processing features diff --git a/openamp/libmetal.cmake b/openamp/libmetal.cmake index fb63e1b0875cc..0f150c5bcf78d 100644 --- a/openamp/libmetal.cmake +++ b/openamp/libmetal.cmake @@ -36,6 +36,10 @@ if(NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/libmetal) PATCH_COMMAND patch -p0 -d ${CMAKE_CURRENT_LIST_DIR} < ${CMAKE_CURRENT_LIST_DIR}/0001-libmetal-add-metal_list_for_each_safe-support.patch + && patch -p0 -d ${CMAKE_CURRENT_LIST_DIR} < + ${CMAKE_CURRENT_LIST_DIR}/0002-libmetal-nuttx-io.c-align-access-when-read-write-siz.patch + && patch -p0 -d ${CMAKE_CURRENT_LIST_DIR} < + ${CMAKE_CURRENT_LIST_DIR}/0003-libmetal-nuttx-io.c-Fix-void-pointer-arithmetic-in-a.patch DOWNLOAD_NO_PROGRESS true TIMEOUT 30) diff --git a/openamp/libmetal.defs b/openamp/libmetal.defs index b3369496abe8c..90e8a690bee8c 100644 --- a/openamp/libmetal.defs +++ b/openamp/libmetal.defs @@ -79,6 +79,7 @@ libmetal.zip: $(Q) mv libmetal-$(VERSION) libmetal $(Q) patch -p0 < 0001-libmetal-add-metal_list_for_each_safe-support.patch $(Q) patch -p0 < 0002-libmetal-nuttx-io.c-align-access-when-read-write-siz.patch + $(Q) patch -p0 < 0003-libmetal-nuttx-io.c-Fix-void-pointer-arithmetic-in-a.patch .libmetal_headers: libmetal.zip else diff --git a/sched/Kconfig b/sched/Kconfig index 40512719b6722..1877b944c4c15 100644 --- a/sched/Kconfig +++ b/sched/Kconfig @@ -47,7 +47,7 @@ config DISABLE_ENVIRON endif # DISABLE_OS_API config DISABLE_IDLE_LOOP - bool + bool "Disable idle loop support" default n ---help--- This option allows nx_start to return instead of @@ -351,7 +351,6 @@ config SMP depends on ARCH_HAVE_TESTSET depends on ARCH_INTERRUPTSTACK != 0 select SPINLOCK - select SCHED_RESUMESCHEDULER select IRQCOUNT ---help--- Enables support for Symmetric Multi-Processing (SMP) on a multi-CPU @@ -528,6 +527,86 @@ config INIT_MOUNT_DATA endif # INIT_MOUNT endif # INIT_FILE +menuconfig ETC_ROMFS + bool "Auto-mount etc baked-in ROMFS image" + default n + depends on !DISABLE_MOUNTPOINT && FS_ROMFS + ---help--- + Mount a ROMFS filesystem at /etc and provide a system init + script at /etc/init.d/rc.sysinit and a startup script + at /etc/init.d/rcS. The default system init script will mount + a FAT FS RAMDISK at /tmp but the logic is easily extensible. + +if ETC_ROMFS + +config ETC_CROMFS + bool "Support CROMFS (compressed) start-up script" + default n + depends on FS_CROMFS + ---help--- + Mount a CROMFS filesystem at /etc and provide a compressed system + init script at /etc/init.d/rc.sysinit and a startup script + at /etc/init.d/rcS. + +config ETC_ROMFSMOUNTPT + string "Mountpoint of the etc romfs image" + default "/etc" + +config ETC_ROMFSDEVNO + int "ROMFS block device minor number" + default 0 + ---help--- + This is the minor number of the ROMFS block device. The default is + '0' corresponding to /dev/ram0. + +config ETC_ROMFSSECTSIZE + int "ROMFS sector size" + default 64 + ---help--- + This is the sector size to use with the ROMFS volume. Since the + default volume is very small, this defaults to 64 but should be + increased if the ROMFS volume were to be become large. Any value + selected must be a power of 2. + +config ETC_FATDEVNO + int "FAT block device minor number" + default 1 + depends on FS_FAT + ---help--- + When the default rcS file used when ETC_ROMFS is selected, it + will mount a FAT FS under /tmp. This is the minor number of the FAT + FS block device. The default is '1' corresponding to /dev/ram1. + +config ETC_FATSECTSIZE + int "FAT sector size" + default 512 + depends on FS_FAT + ---help--- + When the default rcS file used when ETC_ROMFS is selected, it + will mount a FAT FS under /tmp. This is the sector size use with the + FAT FS. Default is 512. + +config ETC_FATNSECTORS + int "FAT number of sectors" + default 1024 + depends on FS_FAT + ---help--- + When the default rcS file used when ETC_ROMFS is selected, it + will mount a FAT FS under /tmp. This is the number of sectors to use + with the FAT FS. Default is 1024. The amount of memory used by the + FAT FS will be ETC_FATSECTSIZE * ETC_FATNSECTORS bytes. + +config ETC_FATMOUNTPT + string "FAT mount point" + default "/tmp" + depends on FS_FAT + ---help--- + When the default rcS file used when ETC_ROMFS is selected, it + will mount a FAT FS under /tmp. This is the location where the FAT + FS will be mounted. Default is "/tmp". + +endif # ETC_ROMFS + config RR_INTERVAL int "Round robin timeslice (MSEC)" default 0 diff --git a/sched/clock/clock_gettime.c b/sched/clock/clock_gettime.c index 0dffa8ae135c7..808ca7aefabed 100644 --- a/sched/clock/clock_gettime.c +++ b/sched/clock/clock_gettime.c @@ -30,9 +30,11 @@ #include #include +#include #include #include #include +#include #include "clock/clock.h" #ifdef CONFIG_CLOCK_TIMEKEEPING @@ -164,11 +166,14 @@ int clock_gettime(clockid_t clock_id, struct timespec *tp) } else if (clock_type == CLOCK_PROCESS_CPUTIME_ID) { - FAR struct task_group_s *group; unsigned long runtime; - irqstate_t flags; - int i; FAR struct tcb_s *tcb; +# ifdef HAVE_GROUP_MEMBERS + FAR struct task_group_s *group; + FAR sq_entry_t *curr; + FAR sq_entry_t *next; + irqstate_t flags; +# endif if (pid == 0) { @@ -183,20 +188,23 @@ int clock_gettime(clockid_t clock_id, struct timespec *tp) if (tcb != NULL) { +# ifdef HAVE_GROUP_MEMBERS group = tcb->group; runtime = 0; - flags = enter_critical_section(); - for (i = group->tg_nmembers - 1; i >= 0; i--) + flags = spin_lock_irqsave(NULL); + sq_for_every_safe(&group->tg_members, curr, next) { - tcb = nxsched_get_tcb(group->tg_members[i]); - if (tcb != NULL) - { - runtime += tcb->run_time; - } + tcb = container_of(curr, struct tcb_s, member); + + runtime += tcb->run_time; } - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); +# else /* HAVE_GROUP_MEMBERS */ + runtime = tcb->run_time; +# endif /* HAVE_GROUP_MEMBERS */ + perf_convert(runtime, tp); } else diff --git a/sched/environ/env_dup.c b/sched/environ/env_dup.c index 3e3be281e8406..8a41b393e98ce 100644 --- a/sched/environ/env_dup.c +++ b/sched/environ/env_dup.c @@ -70,16 +70,16 @@ int env_dup(FAR struct task_group_s *group, FAR char * const *envcp) DEBUGASSERT(group != NULL); - /* Pre-emption must be disabled throughout the following because the - * environment may be shared. - */ - - sched_lock(); - /* Is there an environment ? */ if (envcp != NULL) { + /* Pre-emption must be disabled throughout the following because the + * environment may be shared. + */ + + sched_lock(); + /* Count the strings */ while (envcp[envc] != NULL) @@ -88,6 +88,7 @@ int env_dup(FAR struct task_group_s *group, FAR char * const *envcp) } group->tg_envc = envc; + group->tg_envpc = (envc + SCHED_ENVIRON_RESERVED + 1); /* A special case is that the parent has an "empty" environment * allocation, i.e., there is an allocation in place but it @@ -98,7 +99,7 @@ int env_dup(FAR struct task_group_s *group, FAR char * const *envcp) { /* There is an environment, duplicate it */ - envp = group_malloc(group, sizeof(*envp) * (envc + 1)); + envp = group_malloc(group, sizeof(*envp) * group->tg_envpc); if (envp == NULL) { /* The parent's environment can not be inherited due to a @@ -138,9 +139,10 @@ int env_dup(FAR struct task_group_s *group, FAR char * const *envcp) /* Save the child environment allocation. */ group->tg_envp = envp; + + sched_unlock(); } - sched_unlock(); return ret; } diff --git a/sched/environ/env_release.c b/sched/environ/env_release.c index 9d4e5105708ae..9b041aa7a3902 100644 --- a/sched/environ/env_release.c +++ b/sched/environ/env_release.c @@ -83,8 +83,9 @@ void env_release(FAR struct task_group_s *group) * task group structure are reset to initial values. */ - group->tg_envp = NULL; - group->tg_envc = 0; + group->tg_envp = NULL; + group->tg_envpc = 0; + group->tg_envc = 0; } #endif /* CONFIG_DISABLE_ENVIRON */ diff --git a/sched/environ/env_removevar.c b/sched/environ/env_removevar.c index 93a10b0270d10..7ff4707ee9320 100644 --- a/sched/environ/env_removevar.c +++ b/sched/environ/env_removevar.c @@ -86,14 +86,17 @@ void env_removevar(FAR struct task_group_s *group, ssize_t index) { group_free(group, group->tg_envp); group->tg_envp = NULL; + group->tg_envpc = 0; } - else + else if (group->tg_envc <= + (group->tg_envpc - SCHED_ENVIRON_RESERVED * 2)) { /* Reallocate the environment to reclaim a little memory */ + group->tg_envpc = group->tg_envc + SCHED_ENVIRON_RESERVED + 1; + group->tg_envp = group_realloc(group, group->tg_envp, - sizeof(*group->tg_envp) * - (group->tg_envc + 1)); + sizeof(*group->tg_envp) * group->tg_envpc); DEBUGASSERT(group->tg_envp != NULL); } } diff --git a/sched/environ/env_setenv.c b/sched/environ/env_setenv.c index bc5850dd0c9b8..6180bc4fc3ce4 100644 --- a/sched/environ/env_setenv.c +++ b/sched/environ/env_setenv.c @@ -71,7 +71,8 @@ int setenv(FAR const char *name, FAR const char *value, int overwrite) FAR struct task_group_s *group; FAR char *pvar; FAR char **envp; - ssize_t envc = 0; + ssize_t envc; + ssize_t envpc; ssize_t ret = OK; int varlen; @@ -153,33 +154,41 @@ int setenv(FAR const char *name, FAR const char *value, int overwrite) goto errout_with_lock; } - if (group->tg_envp) + envc = group->tg_envc; + + if (group->tg_envp == NULL) { - envc = group->tg_envc; - envp = group_realloc(group, group->tg_envp, - sizeof(*envp) * (envc + 2)); + envpc = SCHED_ENVIRON_RESERVED + 2; + + envp = group_malloc(group, sizeof(*envp) * envpc); if (envp == NULL) { ret = ENOMEM; goto errout_with_var; } + + group->tg_envp = envp; + group->tg_envpc = envpc; } - else + else if (envc >= group->tg_envpc - 1) { - envp = group_malloc(group, sizeof(*envp) * 2); + envpc = envc + SCHED_ENVIRON_RESERVED + 2; + + envp = group_realloc(group, group->tg_envp, sizeof(*envp) * envpc); if (envp == NULL) { ret = ENOMEM; goto errout_with_var; } - } - envp[envc++] = pvar; - envp[envc] = NULL; + group->tg_envp = envp; + group->tg_envpc = envpc; + } /* Save the new buffer and count */ - group->tg_envp = envp; + group->tg_envp[envc++] = pvar; + group->tg_envp[envc] = NULL; group->tg_envc = envc; /* Now, put the new name=value string into the environment buffer */ diff --git a/sched/environ/environ.h b/sched/environ/environ.h index 615306c736c6a..e1846116dbfe8 100644 --- a/sched/environ/environ.h +++ b/sched/environ/environ.h @@ -37,6 +37,8 @@ # define env_release(group) (0) #else +# define SCHED_ENVIRON_RESERVED (4) + /**************************************************************************** * Public Data ****************************************************************************/ diff --git a/sched/group/CMakeLists.txt b/sched/group/CMakeLists.txt index 0f6bc8b22ae58..3ec2de2a9ef39 100644 --- a/sched/group/CMakeLists.txt +++ b/sched/group/CMakeLists.txt @@ -22,7 +22,6 @@ set(SRCS group_create.c group_join.c group_leave.c - group_find.c group_setupidlefiles.c group_setuptaskfiles.c group_foreachchild.c diff --git a/sched/group/Make.defs b/sched/group/Make.defs index 7115c6fa29ef3..e7f773de3411a 100644 --- a/sched/group/Make.defs +++ b/sched/group/Make.defs @@ -18,7 +18,7 @@ # ############################################################################ -CSRCS += group_create.c group_join.c group_leave.c group_find.c +CSRCS += group_create.c group_join.c group_leave.c CSRCS += group_setupidlefiles.c group_setuptaskfiles.c CSRCS += group_foreachchild.c group_killchildren.c group_signal.c CSRCS += group_argvstr.c diff --git a/sched/group/group.h b/sched/group/group.h index 839e4e2710226..484239d82cc7d 100644 --- a/sched/group/group.h +++ b/sched/group/group.h @@ -44,12 +44,6 @@ typedef int (*foreachchild_t)(pid_t pid, FAR void *arg); * Public Data ****************************************************************************/ -#if defined(HAVE_GROUP_MEMBERS) -/* This is the head of a list of all group members */ - -extern FAR struct task_group_s *g_grouphead; -#endif - /**************************************************************************** * Public Function Prototypes ****************************************************************************/ @@ -62,8 +56,8 @@ void task_initialize(void); /* Task group data structure management */ -int group_allocate(FAR struct task_tcb_s *tcb, uint8_t ttype); -void group_initialize(FAR struct task_tcb_s *tcb); +int group_initialize(FAR struct task_tcb_s *tcb, uint8_t ttype); +void group_postinitialize(FAR struct task_tcb_s *tcb); #ifndef CONFIG_DISABLE_PTHREAD int group_bind(FAR struct pthread_tcb_s *tcb); int group_join(FAR struct pthread_tcb_s *tcb); @@ -75,10 +69,6 @@ void group_add_waiter(FAR struct task_group_s *group); void group_del_waiter(FAR struct task_group_s *group); #endif -#if defined(HAVE_GROUP_MEMBERS) -FAR struct task_group_s *group_findbypid(pid_t pid); -#endif - #ifdef HAVE_GROUP_MEMBERS int group_foreachchild(FAR struct task_group_s *group, foreachchild_t handler, FAR void *arg); diff --git a/sched/group/group_argvstr.c b/sched/group/group_argvstr.c index d2a555770034a..dbf483401f12b 100644 --- a/sched/group/group_argvstr.c +++ b/sched/group/group_argvstr.c @@ -90,7 +90,7 @@ size_t group_argvstr(FAR struct tcb_s *tcb, FAR char *args, size_t size) else #endif { - FAR char **argv = tcb->group->tg_info->argv + 1; + FAR char **argv = tcb->group->tg_info->ta_argv + 1; while (*argv != NULL && n < size) { diff --git a/sched/group/group_create.c b/sched/group/group_create.c index 735d39b72e0ce..1648e286f79f1 100644 --- a/sched/group/group_create.c +++ b/sched/group/group_create.c @@ -39,24 +39,10 @@ #include "group/group.h" #include "tls/tls.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Is this worth making a configuration option? */ - -#define GROUP_INITIAL_MEMBERS 4 - /**************************************************************************** * Public Data ****************************************************************************/ -#if defined(HAVE_GROUP_MEMBERS) -/* This is the head of a list of all group members */ - -FAR struct task_group_s *g_grouphead; -#endif - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -102,7 +88,7 @@ static inline void group_inherit_identity(FAR struct task_group_s *group) ****************************************************************************/ /**************************************************************************** - * Name: group_allocate + * Name: group_initialize * * Description: * Create and a new task group structure for the specified TCB. This @@ -110,8 +96,8 @@ static inline void group_inherit_identity(FAR struct task_group_s *group) * allocated and zeroed, but otherwise uninitialized. The full creation * of the group of a two step process: (1) First, this function allocates * group structure early in the task creation sequence in order to provide - * a group container, then (2) group_initialize() is called to set up the - * group membership. + * a group container, then (2) group_postinitialize() is called to set up + * the group membership. * * Input Parameters: * tcb - The tcb in need of the task group. @@ -126,7 +112,7 @@ static inline void group_inherit_identity(FAR struct task_group_s *group) * ****************************************************************************/ -int group_allocate(FAR struct task_tcb_s *tcb, uint8_t ttype) +int group_initialize(FAR struct task_tcb_s *tcb, uint8_t ttype) { FAR struct task_group_s *group; int ret; @@ -135,11 +121,7 @@ int group_allocate(FAR struct task_tcb_s *tcb, uint8_t ttype) /* Allocate the group structure and assign it to the TCB */ - group = kmm_zalloc(sizeof(struct task_group_s)); - if (!group) - { - return -ENOMEM; - } + group = &tcb->group; #if defined(CONFIG_MM_KERNEL_HEAP) /* If this group is being created for a privileged thread, then all @@ -153,18 +135,9 @@ int group_allocate(FAR struct task_tcb_s *tcb, uint8_t ttype) #endif /* defined(CONFIG_MM_KERNEL_HEAP) */ #ifdef HAVE_GROUP_MEMBERS - /* Allocate space to hold GROUP_INITIAL_MEMBERS members of the group */ + /* Initialize member list of the group */ - group->tg_members = kmm_malloc(GROUP_INITIAL_MEMBERS * sizeof(pid_t)); - if (!group->tg_members) - { - ret = -ENOMEM; - goto errout_with_group; - } - - /* Number of members in allocation */ - - group->tg_mxmembers = GROUP_INITIAL_MEMBERS; + sq_init(&group->tg_members); #endif /* Attach the group to the TCB */ @@ -184,13 +157,14 @@ int group_allocate(FAR struct task_tcb_s *tcb, uint8_t ttype) ret = task_init_info(group); if (ret < 0) { - goto errout_with_member; + return ret; } #ifndef CONFIG_DISABLE_PTHREAD - /* Initialize the pthread join mutex */ + /* Initialize the task group join */ - nxmutex_init(&group->tg_joinlock); + nxrmutex_init(&group->tg_joinlock); + sq_init(&group->tg_joinqueue); #endif #if defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_SCHED_HAVE_PARENT) @@ -200,24 +174,17 @@ int group_allocate(FAR struct task_tcb_s *tcb, uint8_t ttype) #endif return OK; - -errout_with_member: -#ifdef HAVE_GROUP_MEMBERS - kmm_free(group->tg_members); -errout_with_group: -#endif - kmm_free(group); - return ret; } /**************************************************************************** - * Name: group_initialize + * Name: group_postinitialize * * Description: * Add the task as the initial member of the group. The full creation of * the group of a two step process: (1) First, this group structure is - * allocated by group_allocate() early in the task creation sequence, then - * (2) this function is called to set up the initial group membership. + * allocated by group_initialize() early in the task creation sequence, + * then (2) this function is called to set up the initial group + * membership. * * Input Parameters: * tcb - The tcb in need of the task group. @@ -231,12 +198,9 @@ int group_allocate(FAR struct task_tcb_s *tcb, uint8_t ttype) * ****************************************************************************/ -void group_initialize(FAR struct task_tcb_s *tcb) +void group_postinitialize(FAR struct task_tcb_s *tcb) { FAR struct task_group_s *group; -#if defined(HAVE_GROUP_MEMBERS) - irqstate_t flags; -#endif DEBUGASSERT(tcb && tcb->cmn.group); group = tcb->cmn.group; @@ -249,7 +213,7 @@ void group_initialize(FAR struct task_tcb_s *tcb) #ifdef HAVE_GROUP_MEMBERS /* Assign the PID of this new task as a member of the group. */ - group->tg_members[0] = tcb->cmn.pid; + sq_addlast(&tcb->cmn.member, &group->tg_members); #endif /* Save the ID of the main task within the group of threads. This needed @@ -259,17 +223,4 @@ void group_initialize(FAR struct task_tcb_s *tcb) */ group->tg_pid = tcb->cmn.pid; - - /* Mark that there is one member in the group, the main task */ - - group->tg_nmembers = 1; - -#if defined(HAVE_GROUP_MEMBERS) - /* Add the initialized entry to the list of groups */ - - flags = enter_critical_section(); - group->flink = g_grouphead; - g_grouphead = group; - leave_critical_section(flags); -#endif } diff --git a/sched/group/group_find.c b/sched/group/group_find.c deleted file mode 100644 index 822ee91d3155d..0000000000000 --- a/sched/group/group_find.c +++ /dev/null @@ -1,87 +0,0 @@ -/**************************************************************************** - * sched/group/group_find.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include "group/group.h" -#include "environ/environ.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: group_findbypid - * - * Description: - * Given a task ID, find the group task structure with was started by that - * task ID. That task's ID is retained in the group as tg_pid and will - * be remember even if the main task thread leaves the group. - * - * Input Parameters: - * pid - The task ID of the main task thread. - * - * Returned Value: - * On success, a pointer to the group task structure is returned. This - * function can fail only if there is no group that corresponds to the - * task ID. - * - * Assumptions: - * Called during when signally tasks in a safe context. No special - * precautions should be required here. However, extra care is taken when - * accessing the global g_grouphead list. - * - ****************************************************************************/ - -#if defined(HAVE_GROUP_MEMBERS) -FAR struct task_group_s *group_findbypid(pid_t pid) -{ - FAR struct task_group_s *group; - irqstate_t flags; - - /* Find the status structure with the matching PID */ - - flags = enter_critical_section(); - for (group = g_grouphead; group; group = group->flink) - { - if (group->tg_pid == pid) - { - leave_critical_section(flags); - return group; - } - } - - leave_critical_section(flags); - return NULL; -} -#endif diff --git a/sched/group/group_foreachchild.c b/sched/group/group_foreachchild.c index 81761ba6e8303..1fd38bac3b6b0 100644 --- a/sched/group/group_foreachchild.c +++ b/sched/group/group_foreachchild.c @@ -25,7 +25,9 @@ #include #include +#include #include +#include #include "group/group.h" @@ -58,23 +60,27 @@ int group_foreachchild(FAR struct task_group_s *group, foreachchild_t handler, FAR void *arg) { - int ret; - int i; + FAR sq_entry_t *curr; + FAR sq_entry_t *next; + int ret = OK; DEBUGASSERT(group); /* Visit the main thread last (if present) */ - for (i = group->tg_nmembers - 1; i >= 0; i--) + sq_for_every_safe(&group->tg_members, curr, next) { - ret = handler(group->tg_members[i], arg); - if (ret != 0) + FAR struct tcb_s *mtcb = + container_of(curr, struct tcb_s, member); + + ret = handler(mtcb->pid, arg); + if (ret != OK) { - return ret; + break; } } - return 0; + return ret; } #endif /* HAVE_GROUP_MEMBERS */ diff --git a/sched/group/group_join.c b/sched/group/group_join.c index 42d82310f18fd..48befc1d3b4fc 100644 --- a/sched/group/group_join.c +++ b/sched/group/group_join.c @@ -38,102 +38,6 @@ #ifndef CONFIG_DISABLE_PTHREAD -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Is this worth making a configuration option? */ - -#define GROUP_REALLOC_MEMBERS 4 - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: group_addmember - * - * Description: - * Add a new member to a group. - * - * Input Parameters: - * group - The task group to add the new member - * pid - The new member - * - * Returned Value: - * 0 (OK) on success; a negated errno value on failure. - * - * Assumptions: - * Called during thread creation and during reparenting in a safe context. - * No special precautions are required here. - * - ****************************************************************************/ - -#ifdef HAVE_GROUP_MEMBERS -static inline int group_addmember(FAR struct task_group_s *group, pid_t pid) -{ - FAR pid_t *oldmembers = NULL; - irqstate_t flags; - - DEBUGASSERT(group && group->tg_nmembers < UINT8_MAX); - - /* Will we need to extend the size of the array of groups? */ - - if (group->tg_nmembers >= group->tg_mxmembers) - { - FAR pid_t *newmembers; - unsigned int newmax; - - /* Yes... reallocate the array of members */ - - newmax = group->tg_mxmembers + GROUP_REALLOC_MEMBERS; - if (newmax > UINT8_MAX) - { - newmax = UINT8_MAX; - } - - newmembers = kmm_malloc(sizeof(pid_t) * newmax); - - if (!newmembers) - { - serr("ERROR: Failed to reallocate tg_members\n"); - return -ENOMEM; - } - - /* Save the new number of members in the reallocated members array. - * We need to make the following atomic because the member list - * may be traversed from an interrupt handler (read-only). - */ - - flags = spin_lock_irqsave(NULL); - memcpy(newmembers, group->tg_members, - sizeof(pid_t) * group->tg_mxmembers); - oldmembers = group->tg_members; - group->tg_members = newmembers; - group->tg_mxmembers = newmax; - } - else - { - flags = spin_lock_irqsave(NULL); - } - - /* Assign this new pid to the group; group->tg_nmembers will be incremented - * by the caller. - */ - - group->tg_members[group->tg_nmembers] = pid; - group->tg_nmembers++; - spin_unlock_irqrestore(NULL, flags); - - if (oldmembers != NULL) - { - kmm_free(oldmembers); - } - - return OK; -} -#endif /* HAVE_GROUP_MEMBERS */ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -142,12 +46,7 @@ static inline int group_addmember(FAR struct task_group_s *group, pid_t pid) * Name: group_bind * * Description: - * A thread joins the group when it is created. This is a two step process, - * first, the group must bound to the new threads TCB. group_bind() does - * this (at the return from group_join, things are a little unstable: The - * group has been bound, but tg_nmembers has not yet been incremented). - * Then, after the new thread is initialized and has a PID assigned to it, - * group_join() is called, incrementing the tg_nmembers count on the group. + * A thread joins the group when it is created. * * Input Parameters: * tcb - The TCB of the new "child" task that need to join the group. @@ -179,12 +78,7 @@ int group_bind(FAR struct pthread_tcb_s *tcb) * Name: group_join * * Description: - * A thread joins the group when it is created. This is a two step process, - * first, the group must bound to the new threads TCB. group_bind() does - * this (at the return from group_join, things are a little unstable: The - * group has been bound, but tg_nmembers has not yet been incremented). - * Then, after the new thread is initialized and has a PID assigned to it, - * group_join() is called, incrementing the tg_nmembers count on the group. + * A thread joins the group when it is created. * * Input Parameters: * tcb - The TCB of the new "child" task that need to join the group. @@ -203,32 +97,19 @@ int group_bind(FAR struct pthread_tcb_s *tcb) int group_join(FAR struct pthread_tcb_s *tcb) { FAR struct task_group_s *group; -#ifdef HAVE_GROUP_MEMBERS - int ret; -#else irqstate_t flags; -#endif - DEBUGASSERT(tcb && tcb->cmn.group && - tcb->cmn.group->tg_nmembers < UINT8_MAX); + DEBUGASSERT(tcb && tcb->cmn.group); /* Get the group from the TCB */ group = tcb->cmn.group; -#ifdef HAVE_GROUP_MEMBERS /* Add the member to the group */ - ret = group_addmember(group, tcb->cmn.pid); - if (ret < 0) - { - return ret; - } -#else flags = spin_lock_irqsave(NULL); - group->tg_nmembers++; + sq_addfirst(&tcb->cmn.member, &group->tg_members); spin_unlock_irqrestore(NULL, flags); -#endif return OK; } diff --git a/sched/group/group_killchildren.c b/sched/group/group_killchildren.c index bafe734071979..5c44396284125 100644 --- a/sched/group/group_killchildren.c +++ b/sched/group/group_killchildren.c @@ -181,29 +181,34 @@ int group_kill_children(FAR struct tcb_s *tcb) #if defined(CONFIG_GROUP_KILL_CHILDREN_TIMEOUT_MS) && \ CONFIG_GROUP_KILL_CHILDREN_TIMEOUT_MS != 0 - /* Send SIGTERM for each first */ - group_foreachchild(tcb->group, group_kill_children_handler, - (FAR void *)((uintptr_t)tcb->pid)); + if ((tcb->flags & TCB_FLAG_FORCED_CANCEL) == 0) + { + /* Send SIGTERM for each first */ - /* Wait a bit for child exit */ + group_foreachchild(tcb->group, group_kill_children_handler, + (FAR void *)((uintptr_t)tcb->pid)); - ret = CONFIG_GROUP_KILL_CHILDREN_TIMEOUT_MS; - while (1) - { - if (tcb->group->tg_nmembers <= 1) + /* Wait a bit for child exit */ + + ret = CONFIG_GROUP_KILL_CHILDREN_TIMEOUT_MS; + while (1) { - break; - } + if (sq_empty(&tcb->group->tg_members) || + sq_is_singular(&tcb->group->tg_members)) + { + break; + } - nxsig_usleep(USEC_PER_MSEC); + nxsig_usleep(USEC_PER_MSEC); # if CONFIG_GROUP_KILL_CHILDREN_TIMEOUT_MS > 0 - if (--ret < 0) - { - break; - } + if (--ret < 0) + { + break; + } # endif + } } #endif diff --git a/sched/group/group_leave.c b/sched/group/group_leave.c index 6dfef6c1ccd5f..fe452f27c4c68 100644 --- a/sched/group/group_leave.c +++ b/sched/group/group_leave.c @@ -29,6 +29,7 @@ #include #include +#include #include #include #include @@ -49,65 +50,6 @@ * Private Functions ****************************************************************************/ -/**************************************************************************** - * Name: group_remove - * - * Description: - * Remove a group from the list of groups. - * - * Input Parameters: - * group - The group to be removed. - * - * Returned Value: - * None. - * - * Assumptions: - * Called during task deletion in a safe context. No special precautions - * are required here. - * - ****************************************************************************/ - -#if defined(HAVE_GROUP_MEMBERS) -static void group_remove(FAR struct task_group_s *group) -{ - FAR struct task_group_s *curr; - FAR struct task_group_s *prev; - irqstate_t flags; - - /* Let's be especially careful while access the global task group list. - * This is probably un-necessary. - */ - - flags = enter_critical_section(); - - /* Find the task group structure */ - - for (prev = NULL, curr = g_grouphead; - curr && curr != group; - prev = curr, curr = curr->flink); - - /* Did we find it? If so, remove it from the list. */ - - if (curr) - { - /* Do we remove it from mid-list? Or from the head of the list? */ - - if (prev) - { - prev->flink = curr->flink; - } - else - { - g_grouphead = curr->flink; - } - - curr->flink = NULL; - } - - leave_critical_section(flags); -} -#endif - /**************************************************************************** * Name: group_release * @@ -126,7 +68,8 @@ static void group_remove(FAR struct task_group_s *group) * ****************************************************************************/ -static inline void group_release(FAR struct task_group_s *group) +static inline void +group_release(FAR struct task_group_s *group, uint8_t ttype) { task_uninit_info(group); @@ -164,22 +107,6 @@ static inline void group_release(FAR struct task_group_s *group) mm_map_destroy(&group->tg_mm_map); -#if defined(HAVE_GROUP_MEMBERS) - /* Remove the group from the list of groups */ - - group_remove(group); -#endif - -#ifdef HAVE_GROUP_MEMBERS - /* Release the members array */ - - if (group->tg_members) - { - kmm_free(group->tg_members); - group->tg_members = NULL; - } -#endif - #ifdef CONFIG_BINFMT_LOADABLE /* If the exiting task was loaded into RAM from a file, then we need to * lease all of the memory resource when the last thread exits the task @@ -193,66 +120,19 @@ static inline void group_release(FAR struct task_group_s *group) } #endif - /* Mark the group as deleted now */ - - group->tg_flags |= GROUP_FLAG_DELETED; - /* Then drop the group freeing the allocated memory */ - group_drop(group); -} - -/**************************************************************************** - * Name: group_removemember - * - * Description: - * Remove a member from a group. - * - * Input Parameters: - * group - The group from which to remove the member. - * pid - The member to be removed. - * - * Returned Value: - * On success, returns the number of members remaining in the group (>=0). - * Can fail only if the member is not found in the group. On failure, - * returns -ENOENT - * - * Assumptions: - * Called during task deletion and also from the reparenting logic, both - * in a safe context. No special precautions are required here. - * - ****************************************************************************/ - -#ifdef HAVE_GROUP_MEMBERS -static inline void group_removemember(FAR struct task_group_s *group, - pid_t pid) -{ - irqstate_t flags; - int i; - - DEBUGASSERT(group); - - /* Find the member in the array of members and remove it */ - - for (i = 0; i < group->tg_nmembers; i++) +#ifndef CONFIG_DISABLE_PTHREAD + if (ttype == TCB_FLAG_TTYPE_PTHREAD) { - /* Does this member have the matching pid */ + /* Mark the group as deleted now */ - if (group->tg_members[i] == pid) - { - /* Remove the member from the array of members. This must be an - * atomic operation because the member array may be accessed from - * interrupt handlers (read-only). - */ - - flags = enter_critical_section(); - group->tg_members[i] = group->tg_members[group->tg_nmembers - 1]; - group->tg_nmembers--; - leave_critical_section(flags); - } + group->tg_flags |= GROUP_FLAG_DELETED; + + group_drop(group); } +#endif } -#endif /* HAVE_GROUP_MEMBERS */ /**************************************************************************** * Public Functions @@ -279,10 +159,12 @@ static inline void group_removemember(FAR struct task_group_s *group, * ****************************************************************************/ -#ifdef HAVE_GROUP_MEMBERS void group_leave(FAR struct tcb_s *tcb) { FAR struct task_group_s *group; +#ifdef HAVE_GROUP_MEMBERS + irqstate_t flags; +#endif DEBUGASSERT(tcb); @@ -291,72 +173,31 @@ void group_leave(FAR struct tcb_s *tcb) group = tcb->group; if (group) { - /* Remove the member from group. This function may be called - * during certain error handling before the PID has been - * added to the group. In this case tcb->pid will be uninitialized - * group_removemember() will fail. - */ - - group_removemember(group, tcb->pid); - - /* Have all of the members left the group? */ - - if (group->tg_nmembers == 0) - { - /* Yes.. Release all of the resource held by the task group */ - - group_release(group); - } - /* In any event, we can detach the group from the TCB so that we won't * do this again. */ tcb->group = NULL; - } -} - -#else /* HAVE_GROUP_MEMBERS */ - -void group_leave(FAR struct tcb_s *tcb) -{ - FAR struct task_group_s *group; - - DEBUGASSERT(tcb); - /* Make sure that we have a group */ + /* Remove the member from group. */ - group = tcb->group; - if (group) - { - /* Yes, we have a group.. Is this the last member of the group? */ - - if (group->tg_nmembers > 1) - { - /* No.. just decrement the number of members in the group */ - - group->tg_nmembers--; - } +#ifdef HAVE_GROUP_MEMBERS + flags = spin_lock_irqsave(NULL); + sq_rem(&tcb->member, &group->tg_members); + spin_unlock_irqrestore(NULL, flags); - /* Yes.. that was the last member remaining in the group */ + /* Have all of the members left the group? */ - else + if (sq_empty(&group->tg_members)) +#endif { - /* Release all of the resource held by the task group */ + /* Yes.. Release all of the resource held by the task group */ - group_release(group); + group_release(group, tcb->flags & TCB_FLAG_TTYPE_MASK); } - - /* In any event, we can detach the group from the TCB so we won't do - * this again. - */ - - tcb->group = NULL; } } -#endif /* HAVE_GROUP_MEMBERS */ - /**************************************************************************** * Name: group_drop * @@ -380,6 +221,8 @@ void group_leave(FAR struct tcb_s *tcb) void group_drop(FAR struct task_group_s *group) { + FAR struct task_tcb_s *tcb; + #if defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_SCHED_HAVE_PARENT) /* If there are threads waiting for this group to be freed, then we cannot * yet free the memory resources. Instead just mark the group deleted @@ -394,13 +237,17 @@ void group_drop(FAR struct task_group_s *group) } else #endif - /* Finally, if no one needs the group and it has been deleted, remove it */ if (group->tg_flags & GROUP_FLAG_DELETED) { + tcb = container_of(group, struct task_tcb_s, group); + /* Release the group container itself */ - kmm_free(group); + if (tcb->cmn.flags & TCB_FLAG_FREE_TCB) + { + kmm_free(tcb); + } } } diff --git a/sched/init/init.h b/sched/init/init.h index 1e389b5cd070f..31d335772880a 100644 --- a/sched/init/init.h +++ b/sched/init/init.h @@ -97,8 +97,8 @@ void nx_idle_trampoline(void); * the conclusion of basic OS initialization. These initial system tasks * may include: * - * - pg_worker: The page-fault worker thread (only if CONFIG_PAGING is - * defined. + * - pg_worker: The page-fault worker thread (if CONFIG_LEGACY_PAGING is + * defined). * - work_thread: The work thread. This general thread can be used to * perform most any kind of queued work. Its primary * function is to serve as the "bottom half" of device diff --git a/sched/init/nx_bringup.c b/sched/init/nx_bringup.c index 6244908ad346d..c1944a45be4d7 100644 --- a/sched/init/nx_bringup.c +++ b/sched/init/nx_bringup.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include #include @@ -41,7 +42,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING # include "paging/paging.h" #endif @@ -50,6 +51,11 @@ #include "init/init.h" #include "misc/coredump.h" +#ifdef CONFIG_ETC_ROMFS +# include +# include +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -116,6 +122,15 @@ extern const int CONFIG_INIT_NEXPORTS; # define CONFIG_INIT_PRIORITY SCHED_PRIORITY_DEFAULT #endif +#ifdef CONFIG_ETC_ROMFS +# define NSECTORS(b) (((b)+CONFIG_ETC_ROMFSSECTSIZE-1)/CONFIG_ETC_ROMFSSECTSIZE) +# define MKMOUNT_DEVNAME(m) "/dev/ram" STRINGIFY(m) +# define MOUNT_DEVNAME MKMOUNT_DEVNAME(CONFIG_ETC_ROMFSDEVNO) + +extern const unsigned char romfs_img[]; +extern const unsigned int romfs_img_len; +#endif + /**************************************************************************** * Private Functions ****************************************************************************/ @@ -136,7 +151,7 @@ extern const int CONFIG_INIT_NEXPORTS; * ****************************************************************************/ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING static inline void nx_pgworker(void) { /* Start the page fill worker kernel thread that will resolve page faults. @@ -152,10 +167,10 @@ static inline void nx_pgworker(void) DEBUGASSERT(g_pgworker > 0); } -#else /* CONFIG_PAGING */ +#else /* CONFIG_LEGACY_PAGING */ # define nx_pgworker() -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ /**************************************************************************** * Name: nx_workqueues @@ -211,6 +226,58 @@ static inline void nx_workqueues(void) #endif /* CONFIG_SCHED_WORKQUEUE */ +/**************************************************************************** + * Name: nx_romfsetc + * + * Description: mount baked-in ROMFS image to /etc. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ETC_ROMFS +static inline void nx_romfsetc(void) +{ + int ret; + +#ifndef CONFIG_ETC_CROMFS + /* Create a ROM disk for the /etc filesystem */ + + ret = romdisk_register(CONFIG_ETC_ROMFSDEVNO, romfs_img, + NSECTORS(romfs_img_len), + CONFIG_ETC_ROMFSSECTSIZE); + if (ret < 0) + { + ferr("ERROR: romdisk_register failed: %d\n", -ret); + return; + } +#endif + + /* Mount the file system */ + + finfo("Mounting ROMFS filesystem at target=%s with source=%s\n", + CONFIG_ETC_ROMFSMOUNTPT, MOUNT_DEVNAME); + +#if defined(CONFIG_ETC_CROMFS) + ret = nx_mount(MOUNT_DEVNAME, CONFIG_ETC_ROMFSMOUNTPT, + "cromfs", MS_RDONLY, NULL); +#else + ret = nx_mount(MOUNT_DEVNAME, CONFIG_ETC_ROMFSMOUNTPT, + "romfs", MS_RDONLY, NULL); +#endif + if (ret < 0) + { + ferr("ERROR: nx_mount(%s,%s,romfs) failed: %d\n", + MOUNT_DEVNAME, CONFIG_ETC_ROMFSMOUNTPT, ret); + } +} + +#endif /* CONFIG_ETC_ROMFS */ + /**************************************************************************** * Name: nx_start_application * @@ -241,6 +308,10 @@ static inline void nx_start_application(void) #endif int ret; +#ifdef CONFIG_ETC_ROMFS + nx_romfsetc(); +#endif + #ifdef CONFIG_BOARD_LATE_INITIALIZE /* Perform any last-minute, board-specific initialization, if so * configured. @@ -385,8 +456,8 @@ static inline void nx_create_initthread(void) * the conclusion of basic OS initialization. These initial system tasks * may include: * - * - pg_worker: The page-fault worker thread (only if CONFIG_PAGING is - * defined. + * - pg_worker: The page-fault worker thread (if CONFIG_LEGACY_PAGING is + * defined). * - work_thread: The work thread. This general thread can be used to * perform most any kind of queued work. Its primary * function is to serve as the "bottom half" of device diff --git a/sched/init/nx_start.c b/sched/init/nx_start.c index 98a5f1cfb7dd9..26fd5400e063e 100644 --- a/sched/init/nx_start.c +++ b/sched/init/nx_start.c @@ -46,6 +46,7 @@ #include #include +#include "task/task.h" #include "sched/sched.h" #include "signal/signal.h" #include "semaphore/semaphore.h" @@ -142,7 +143,7 @@ dq_queue_t g_pendingtasks; dq_queue_t g_waitingforsignal; -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /* This is the list of all tasks that are blocking waiting for a page fill */ dq_queue_t g_waitingforfill; @@ -183,77 +184,7 @@ volatile int g_npidhash; * ordered list or not. */ -const struct tasklist_s g_tasklisttable[NUM_TASK_STATES] = -{ - { /* TSTATE_TASK_INVALID */ - NULL, - 0 - }, - { /* TSTATE_TASK_PENDING */ - &g_pendingtasks, - TLIST_ATTR_PRIORITIZED - }, -#ifdef CONFIG_SMP - { /* TSTATE_TASK_READYTORUN */ - &g_readytorun, - TLIST_ATTR_PRIORITIZED - }, - { /* TSTATE_TASK_ASSIGNED */ - g_assignedtasks, - TLIST_ATTR_PRIORITIZED | TLIST_ATTR_INDEXED | TLIST_ATTR_RUNNABLE - }, - { /* TSTATE_TASK_RUNNING */ - g_assignedtasks, - TLIST_ATTR_PRIORITIZED | TLIST_ATTR_INDEXED | TLIST_ATTR_RUNNABLE - }, -#else - { /* TSTATE_TASK_READYTORUN */ - &g_readytorun, - TLIST_ATTR_PRIORITIZED | TLIST_ATTR_RUNNABLE - }, - { /* TSTATE_TASK_RUNNING */ - &g_readytorun, - TLIST_ATTR_PRIORITIZED | TLIST_ATTR_RUNNABLE - }, -#endif - { /* TSTATE_TASK_INACTIVE */ - &g_inactivetasks, - 0 - }, - { /* TSTATE_WAIT_SEM */ - (FAR void *)offsetof(sem_t, waitlist), - TLIST_ATTR_PRIORITIZED | TLIST_ATTR_OFFSET - }, - { /* TSTATE_WAIT_SIG */ - &g_waitingforsignal, - 0 - } -#ifndef CONFIG_DISABLE_MQUEUE - , - { /* TSTATE_WAIT_MQNOTEMPTY */ - (FAR void *)offsetof(struct mqueue_inode_s, cmn.waitfornotempty), - TLIST_ATTR_PRIORITIZED | TLIST_ATTR_OFFSET - }, - { /* TSTATE_WAIT_MQNOTFULL */ - (FAR void *)offsetof(struct mqueue_inode_s, cmn.waitfornotfull), - TLIST_ATTR_PRIORITIZED | TLIST_ATTR_OFFSET - } -#endif -#ifdef CONFIG_PAGING - , - { /* TSTATE_WAIT_PAGEFILL */ - &g_waitingforfill, - TLIST_ATTR_PRIORITIZED - } -#endif -#ifdef CONFIG_SIG_SIGSTOP_ACTION - , - { /* TSTATE_TASK_STOPPED */ - &g_stoppedtasks, - 0 /* See tcb->prev_state */ - }, -#endif -}; +struct tasklist_s g_tasklisttable[NUM_TASK_STATES]; /* This is the current initialization state. The level of initialization * is only important early in the start-up sequence when certain OS or @@ -294,44 +225,138 @@ static const char g_idlename[] = "Idle_Task"; static FAR char *g_idleargv[CONFIG_SMP_NCPUS][2]; /**************************************************************************** - * Public Functions + * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: nx_start + * Name: tasklist_initialize * * Description: - * This function is called to initialize the operating system and to spawn - * the user initialization thread of execution. This is the initial entry - * point into NuttX. - * - * Input Parameters: - * None - * - * Returned Value: - * Does not return. + * Initialization of table of task lists.This table is indexed by the + * task state enumeration type (tstate_t) and provides a pointer to + * the associated static task list (if there is one) as well as a set + * of attribute flags indicating properties of the list, for example, + * if the list is an ordered list or not. * ****************************************************************************/ -void nx_start(void) +static void tasklist_initialize(void) { - int i; + FAR struct tasklist_s *tlist = (FAR void *)&g_tasklisttable; - sinfo("Entry\n"); + /* TSTATE_TASK_INVALID */ - /* Boot up is complete */ + tlist[TSTATE_TASK_INVALID].list = NULL; + tlist[TSTATE_TASK_INVALID].attr = 0; - g_nx_initstate = OSINIT_BOOT; + /* TSTATE_TASK_PENDING */ - /* Initialize RTOS Data ***************************************************/ + tlist[TSTATE_TASK_PENDING].list = list_pendingtasks(); + tlist[TSTATE_TASK_PENDING].attr = TLIST_ATTR_PRIORITIZED; - sched_trace_begin(); +#ifdef CONFIG_SMP - /* Initialize the IDLE task TCB *******************************************/ + /* TSTATE_TASK_READYTORUN */ + + tlist[TSTATE_TASK_READYTORUN].list = list_readytorun(); + tlist[TSTATE_TASK_READYTORUN].attr = TLIST_ATTR_PRIORITIZED; + + /* TSTATE_TASK_ASSIGNED */ + + tlist[TSTATE_TASK_ASSIGNED].list = list_assignedtasks(0); + tlist[TSTATE_TASK_ASSIGNED].attr = TLIST_ATTR_PRIORITIZED | + TLIST_ATTR_INDEXED | + TLIST_ATTR_RUNNABLE; + + /* TSTATE_TASK_RUNNING */ + + tlist[TSTATE_TASK_RUNNING].list = list_assignedtasks(0); + tlist[TSTATE_TASK_RUNNING].attr = TLIST_ATTR_PRIORITIZED | + TLIST_ATTR_INDEXED | + TLIST_ATTR_RUNNABLE; +#else + + /* TSTATE_TASK_READYTORUN */ + + tlist[TSTATE_TASK_READYTORUN].list = list_readytorun(); + tlist[TSTATE_TASK_READYTORUN].attr = TLIST_ATTR_PRIORITIZED | + TLIST_ATTR_RUNNABLE; + + /* TSTATE_TASK_RUNNING */ + + tlist[TSTATE_TASK_RUNNING].list = list_readytorun(); + tlist[TSTATE_TASK_RUNNING].attr = TLIST_ATTR_PRIORITIZED | + TLIST_ATTR_RUNNABLE; +#endif + + /* TSTATE_TASK_INACTIVE */ + + tlist[TSTATE_TASK_INACTIVE].list = list_inactivetasks(); + tlist[TSTATE_TASK_INACTIVE].attr = 0; + + /* TSTATE_WAIT_SEM */ + + tlist[TSTATE_WAIT_SEM].list = (FAR void *)offsetof(sem_t, waitlist); + tlist[TSTATE_WAIT_SEM].attr = TLIST_ATTR_PRIORITIZED | + TLIST_ATTR_OFFSET; + + /* TSTATE_WAIT_SIG */ + + tlist[TSTATE_WAIT_SIG].list = list_waitingforsignal(); + tlist[TSTATE_WAIT_SIG].attr = 0; + +#ifndef CONFIG_DISABLE_MQUEUE + + /* TSTATE_WAIT_MQNOTEMPTY */ + + tlist[TSTATE_WAIT_MQNOTEMPTY].list = + (FAR void *)offsetof(struct mqueue_inode_s, cmn.waitfornotempty); + tlist[TSTATE_WAIT_MQNOTEMPTY].attr = TLIST_ATTR_PRIORITIZED | + TLIST_ATTR_OFFSET; + + /* TSTATE_WAIT_MQNOTFULL */ + + tlist[TSTATE_WAIT_MQNOTFULL].list = + (FAR void *)offsetof(struct mqueue_inode_s, cmn.waitfornotfull); + tlist[TSTATE_WAIT_MQNOTFULL].attr = TLIST_ATTR_PRIORITIZED | + TLIST_ATTR_OFFSET; +#endif + +#ifdef CONFIG_LEGACY_PAGING + + /* TSTATE_WAIT_PAGEFILL */ + + tlist[TSTATE_WAIT_PAGEFILL].list = list_waitingforfill(); + tlist[TSTATE_WAIT_PAGEFILL].attr = TLIST_ATTR_PRIORITIZED; +#endif + +#ifdef CONFIG_SIG_SIGSTOP_ACTION + + /* TSTATE_TASK_STOPPED */ + + tlist[TSTATE_TASK_STOPPED].list = list_stoppedtasks(); + tlist[TSTATE_TASK_STOPPED].attr = 0; + +#endif +} + +/**************************************************************************** + * Name: idle_task_initialize + * + * Description: + * IDLE Task Initialization + * + ****************************************************************************/ + +static void idle_task_initialize(void) +{ + FAR struct task_tcb_s *tcb; + FAR dq_queue_t *tasklist; + int i; for (i = 0; i < CONFIG_SMP_NCPUS; i++) { - FAR dq_queue_t *tasklist; + tcb = &g_idletcb[i]; /* Initialize a TCB for this thread of execution. NOTE: The default * value for most components of the g_idletcb are zero. The entire @@ -340,9 +365,9 @@ void nx_start(void) * that has pid == 0 and sched_priority == 0. */ - memset((void *)&g_idletcb[i], 0, sizeof(struct task_tcb_s)); - g_idletcb[i].cmn.pid = i; - g_idletcb[i].cmn.task_state = TSTATE_TASK_RUNNING; + memset(tcb, 0, sizeof(struct task_tcb_s)); + tcb->cmn.pid = i; + tcb->cmn.task_state = TSTATE_TASK_RUNNING; /* Set the entry point. This is only for debug purposes. NOTE: that * the start_t entry point is not saved. That is acceptable, however, @@ -353,14 +378,14 @@ void nx_start(void) #ifdef CONFIG_SMP if (i > 0) { - g_idletcb[i].cmn.start = nx_idle_trampoline; - g_idletcb[i].cmn.entry.main = (main_t)nx_idle_trampoline; + tcb->cmn.start = nx_idle_trampoline; + tcb->cmn.entry.main = (main_t)nx_idle_trampoline; } else #endif { - g_idletcb[i].cmn.start = nx_start; - g_idletcb[i].cmn.entry.main = (main_t)nx_start; + tcb->cmn.start = nx_start; + tcb->cmn.entry.main = (main_t)nx_start; } /* Set the task flags to indicate that this is a kernel thread and, if @@ -368,8 +393,8 @@ void nx_start(void) */ #ifdef CONFIG_SMP - g_idletcb[i].cmn.flags = (TCB_FLAG_TTYPE_KERNEL | TCB_FLAG_CPU_LOCKED); - g_idletcb[i].cmn.cpu = i; + tcb->cmn.flags = (TCB_FLAG_TTYPE_KERNEL | TCB_FLAG_CPU_LOCKED); + tcb->cmn.cpu = i; /* Set the affinity mask to allow the thread to run on all CPUs. No, * this IDLE thread can only run on its assigned CPU. That is @@ -379,20 +404,19 @@ void nx_start(void) * the IDLE task. */ - g_idletcb[i].cmn.affinity = + tcb->cmn.affinity = (cpu_set_t)(CONFIG_SMP_DEFAULT_CPUSET & SCHED_ALL_CPUS); #else - g_idletcb[i].cmn.flags = TCB_FLAG_TTYPE_KERNEL; + tcb->cmn.flags = TCB_FLAG_TTYPE_KERNEL; #endif #if CONFIG_TASK_NAME_SIZE > 0 /* Set the IDLE task name */ # ifdef CONFIG_SMP - snprintf(g_idletcb[i].cmn.name, CONFIG_TASK_NAME_SIZE, "CPU%d IDLE", - i); + snprintf(tcb->cmn.name, CONFIG_TASK_NAME_SIZE, "CPU%d IDLE", i); # else - strlcpy(g_idletcb[i].cmn.name, g_idlename, CONFIG_TASK_NAME_SIZE); + strlcpy(tcb->cmn.name, g_idlename, CONFIG_TASK_NAME_SIZE); # endif /* Configure the task name in the argument list. The IDLE task does @@ -403,7 +427,7 @@ void nx_start(void) * stack and there is no support that yet. */ - g_idleargv[i][0] = g_idletcb[i].cmn.name; + g_idleargv[i][0] = tcb->cmn.name; #else g_idleargv[i][0] = (FAR char *)g_idlename; #endif /* CONFIG_TASK_NAME_SIZE */ @@ -413,20 +437,125 @@ void nx_start(void) */ #ifdef CONFIG_SMP - tasklist = TLIST_HEAD(&g_idletcb[i].cmn, i); + tasklist = TLIST_HEAD(&tcb->cmn, i); #else - tasklist = TLIST_HEAD(&g_idletcb[i].cmn); + tasklist = TLIST_HEAD(&tcb->cmn); #endif - dq_addfirst((FAR dq_entry_t *)&g_idletcb[i], tasklist); + dq_addfirst((FAR dq_entry_t *)tcb, tasklist); /* Mark the idle task as the running task */ - g_running_tasks[i] = &g_idletcb[i].cmn; + g_running_tasks[i] = &tcb->cmn; } +} + +/**************************************************************************** + * Name: idle_group_initialize + * + * Description: + * IDLE Group Initialization + * + ****************************************************************************/ + +static void idle_group_initialize(void) +{ + FAR struct task_tcb_s *tcb; + int hashndx; + int i; + + /* Assign the process ID(s) of ZERO to the idle task(s) */ + + for (i = 0; i < CONFIG_SMP_NCPUS; i++) + { + tcb = &g_idletcb[i]; + + hashndx = PIDHASH(i); + nxsched_pidhash()[hashndx] = &tcb->cmn; + + /* Allocate the IDLE group */ + + DEBUGVERIFY(group_initialize(tcb, tcb->cmn.flags)); + tcb->cmn.group->tg_info->ta_argv = &g_idleargv[i][0]; + + /* Initialize the task join */ + + nxtask_joininit(&tcb->cmn); + +#ifdef CONFIG_SMP + /* Create a stack for all CPU IDLE threads (except CPU0 which already + * has a stack). + */ + + if (i > 0) + { + DEBUGVERIFY(up_cpu_idlestack(i, &tcb->cmn, + CONFIG_IDLETHREAD_STACKSIZE)); + } +#endif + + /* Initialize the processor-specific portion of the TCB */ + + up_initial_state(&tcb->cmn); + + /* Initialize the thread local storage */ + + tls_init_info(&tcb->cmn); + + /* Complete initialization of the IDLE group. Suppress retention + * of child status in the IDLE group. + */ + + group_postinitialize(tcb); + tcb->cmn.group->tg_flags = GROUP_FLAG_NOCLDWAIT | + GROUP_FLAG_PRIVILEGED; + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nx_start + * + * Description: + * This function is called to initialize the operating system and to spawn + * the user initialization thread of execution. This is the initial entry + * point into NuttX. + * + * Input Parameters: + * None + * + * Returned Value: + * Does not return. + * + ****************************************************************************/ + +void nx_start(void) +{ + int i; + + sinfo("Entry\n"); + + /* Boot up is complete */ + + nxsched_set_initstate(OSINIT_BOOT); + + /* Initialize RTOS Data ***************************************************/ + + sched_trace_begin(); + + /* Initialize task list table *********************************************/ + + tasklist_initialize(); + + /* Initialize the IDLE task TCB *******************************************/ + + idle_task_initialize(); /* Task lists are initialized */ - g_nx_initstate = OSINIT_TASKLISTS; + nxsched_set_initstate(OSINIT_TASKLISTS); /* Initialize RTOS facilities *********************************************/ @@ -494,65 +623,25 @@ void nx_start(void) /* Initialize the logic that determine unique process IDs. */ - g_npidhash = 4; - while (g_npidhash <= CONFIG_SMP_NCPUS) + nxsched_npidhash() = 4; + while (nxsched_npidhash() <= CONFIG_SMP_NCPUS) { - g_npidhash <<= 1; + nxsched_npidhash() <<= 1; } - g_pidhash = kmm_zalloc(sizeof(*g_pidhash) * g_npidhash); - DEBUGASSERT(g_pidhash); + nxsched_pidhash() = + kmm_zalloc(sizeof(*nxsched_pidhash()) * nxsched_npidhash()); + DEBUGASSERT(nxsched_pidhash()); /* IDLE Group Initialization **********************************************/ - for (i = 0; i < CONFIG_SMP_NCPUS; i++) - { - int hashndx; - - /* Assign the process ID(s) of ZERO to the idle task(s) */ - - hashndx = PIDHASH(i); - g_pidhash[hashndx] = &g_idletcb[i].cmn; - - /* Allocate the IDLE group */ - - DEBUGVERIFY(group_allocate(&g_idletcb[i], g_idletcb[i].cmn.flags)); - g_idletcb[i].cmn.group->tg_info->argv = &g_idleargv[i][0]; - -#ifdef CONFIG_SMP - /* Create a stack for all CPU IDLE threads (except CPU0 which already - * has a stack). - */ - - if (i > 0) - { - DEBUGVERIFY(up_cpu_idlestack(i, &g_idletcb[i].cmn, - CONFIG_IDLETHREAD_STACKSIZE)); - } -#endif - - /* Initialize the processor-specific portion of the TCB */ - - up_initial_state(&g_idletcb[i].cmn); + idle_group_initialize(); - /* Initialize the thread local storage */ - - tls_init_info(&g_idletcb[i].cmn); - - /* Complete initialization of the IDLE group. Suppress retention - * of child status in the IDLE group. - */ - - group_initialize(&g_idletcb[i]); - g_idletcb[i].cmn.group->tg_flags = GROUP_FLAG_NOCLDWAIT | - GROUP_FLAG_PRIVILEGED; - } - - g_lastpid = CONFIG_SMP_NCPUS - 1; + nxsched_lastpid() = CONFIG_SMP_NCPUS - 1; /* The memory manager is available */ - g_nx_initstate = OSINIT_MEMORY; + nxsched_set_initstate(OSINIT_MEMORY); /* Initialize tasking data structures */ @@ -595,12 +684,6 @@ void nx_start(void) nxmq_initialize(); #endif -#ifndef CONFIG_DISABLE_MQUEUE_SYSV - /* Initialize the System V message queue facility (if in link) */ - - nxmsg_initialize(); -#endif - #ifdef CONFIG_NET /* Initialize the networking system */ @@ -638,7 +721,7 @@ void nx_start(void) /* Hardware resources are now available */ - g_nx_initstate = OSINIT_HARDWARE; + nxsched_set_initstate(OSINIT_HARDWARE); /* Setup for Multi-Tasking ************************************************/ @@ -684,7 +767,7 @@ void nx_start(void) /* The OS is fully initialized and we are beginning multi-tasking */ - g_nx_initstate = OSINIT_OSREADY; + nxsched_set_initstate(OSINIT_OSREADY); /* Create initial tasks and bring-up the system */ @@ -692,7 +775,7 @@ void nx_start(void) /* Enter to idleloop */ - g_nx_initstate = OSINIT_IDLELOOP; + nxsched_set_initstate(OSINIT_IDLELOOP); /* Let other threads have access to the memory manager */ diff --git a/sched/irq/CMakeLists.txt b/sched/irq/CMakeLists.txt index a1d9f77b27347..b569005c34019 100644 --- a/sched/irq/CMakeLists.txt +++ b/sched/irq/CMakeLists.txt @@ -20,7 +20,7 @@ set(SRCS irq_initialize.c irq_attach.c irq_dispatch.c irq_unexpectedisr.c) -if(CONFIG_SMP) +if(CONFIG_SPINLOCK) list(APPEND SRCS irq_spinlock.c) endif() diff --git a/sched/irq/Make.defs b/sched/irq/Make.defs index aa4b6e692446b..926fe4caf8adb 100644 --- a/sched/irq/Make.defs +++ b/sched/irq/Make.defs @@ -20,7 +20,7 @@ CSRCS += irq_initialize.c irq_attach.c irq_dispatch.c irq_unexpectedisr.c -ifeq ($(CONFIG_SMP),y) +ifeq ($(CONFIG_SPINLOCK),y) CSRCS += irq_spinlock.c endif diff --git a/sched/irq/irq.h b/sched/irq/irq.h index 7088249c5d4dd..b1be90ea85069 100644 --- a/sched/irq/irq.h +++ b/sched/irq/irq.h @@ -150,33 +150,6 @@ void irq_initialize(void); int irq_unexpected_isr(int irq, FAR void *context, FAR void *arg); -/**************************************************************************** - * Name: irq_cpu_locked - * - * Description: - * Test if the IRQ lock set OR if this CPU holds the IRQ lock - * There is an interaction with pre-emption controls and IRQ locking: - * Even if the pre-emption is enabled, tasks will be forced to pend if - * the IRQ lock is also set UNLESS the CPU starting the task is the - * holder of the IRQ lock. - * - * Input Parameters: - * rtcb - Points to the blocked TCB that is ready-to-run - * - * Returned Value: - * true - IRQs are locked by a different CPU. - * false - IRQs are unlocked OR if they are locked BUT this CPU - * is the holder of the lock. - * - * Warning: This values are volatile at only valid at the instance that - * the CPU set was queried. - * - ****************************************************************************/ - -#ifdef CONFIG_SMP -bool irq_cpu_locked(int cpu); -#endif - /**************************************************************************** * Name: irq_foreach * diff --git a/sched/irq/irq_attach.c b/sched/irq/irq_attach.c index 0ca62f023872c..83249c4a2ef97 100644 --- a/sched/irq/irq_attach.c +++ b/sched/irq/irq_attach.c @@ -72,7 +72,7 @@ int irq_attach(int irq, xcpt_t isr, FAR void *arg) * to the unexpected interrupt handler. */ - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (isr == NULL) { /* Disable the interrupt if we can before detaching it. We might @@ -121,7 +121,7 @@ int irq_attach(int irq, xcpt_t isr, FAR void *arg) g_irqvector[ndx].count = 0; #endif - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); ret = OK; } diff --git a/sched/irq/irq_chain.c b/sched/irq/irq_chain.c index ba83b0befa0fb..f5bd0736c98d3 100644 --- a/sched/irq/irq_chain.c +++ b/sched/irq/irq_chain.c @@ -218,7 +218,7 @@ int irqchain_detach(int irq, xcpt_t isr, FAR void *arg) ndx = irq; #endif - flags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); if (g_irqvector[ndx].handler == irqchain_dispatch) { @@ -264,7 +264,7 @@ int irqchain_detach(int irq, xcpt_t isr, FAR void *arg) ret = irq_detach(irq); } - leave_critical_section(flags); + spin_unlock_irqrestore(NULL, flags); } return ret; diff --git a/sched/irq/irq_csection.c b/sched/irq/irq_csection.c index 799182960d7c3..c42a8b2d25ed7 100644 --- a/sched/irq/irq_csection.c +++ b/sched/irq/irq_csection.c @@ -188,200 +188,205 @@ irqstate_t enter_critical_section(void) try_again: ret = up_irq_save(); - /* Verify that the system has sufficiently initialized so that the task - * lists are valid. + /* If called from an interrupt handler, then just take the spinlock. + * If we are already in a critical section, this will lock the CPU + * in the interrupt handler. Sounds worse than it is. */ - if (g_nx_initstate >= OSINIT_TASKLISTS) + if (up_interrupt_context()) { - /* If called from an interrupt handler, then just take the spinlock. - * If we are already in a critical section, this will lock the CPU - * in the interrupt handler. Sounds worse than it is. + /* We are in an interrupt handler. How can this happen? + * + * 1. We were not in a critical section when the interrupt + * occurred. In this case, the interrupt was entered with: + * + * g_cpu_irqlock = SP_UNLOCKED. + * g_cpu_nestcount = 0 + * All CPU bits in g_cpu_irqset should be zero + * + * 2. We were in a critical section and interrupts on this + * this CPU were disabled -- this is an impossible case. + * + * 3. We were in critical section, but up_irq_save() only + * disabled local interrupts on a different CPU; + * Interrupts could still be enabled on this CPU. + * + * g_cpu_irqlock = SP_LOCKED. + * g_cpu_nestcount = 0 + * The bit in g_cpu_irqset for this CPU should be zero + * + * 4. An extension of 3 is that we may be re-entered numerous + * times from the same interrupt handler. In that case: + * + * g_cpu_irqlock = SP_LOCKED. + * g_cpu_nestcount > 0 + * The bit in g_cpu_irqset for this CPU should be zero + * + * NOTE: However, the interrupt entry conditions can change due + * to previous processing by the interrupt handler that may + * instantiate a new thread that has irqcount > 0 and may then + * set the bit in g_cpu_irqset and g_cpu_irqlock = SP_LOCKED */ - if (up_interrupt_context()) + /* Handle nested calls to enter_critical_section() from the same + * interrupt. + */ + + cpu = this_cpu(); + if (g_cpu_nestcount[cpu] > 0) { - /* We are in an interrupt handler. How can this happen? - * - * 1. We were not in a critical section when the interrupt - * occurred. In this case, the interrupt was entered with: - * - * g_cpu_irqlock = SP_UNLOCKED. - * g_cpu_nestcount = 0 - * All CPU bits in g_cpu_irqset should be zero - * - * 2. We were in a critical section and interrupts on this - * this CPU were disabled -- this is an impossible case. - * - * 3. We were in critical section, but up_irq_save() only - * disabled local interrupts on a different CPU; - * Interrupts could still be enabled on this CPU. - * - * g_cpu_irqlock = SP_LOCKED. - * g_cpu_nestcount = 0 - * The bit in g_cpu_irqset for this CPU should be zero - * - * 4. An extension of 3 is that we may be re-entered numerous - * times from the same interrupt handler. In that case: - * - * g_cpu_irqlock = SP_LOCKED. - * g_cpu_nestcount > 0 - * The bit in g_cpu_irqset for this CPU should be zero - * - * NOTE: However, the interrupt entry conditions can change due - * to previous processing by the interrupt handler that may - * instantiate a new thread that has irqcount > 0 and may then - * set the bit in g_cpu_irqset and g_cpu_irqlock = SP_LOCKED - */ + DEBUGASSERT(spin_is_locked(&g_cpu_irqlock) && + g_cpu_nestcount[cpu] < UINT8_MAX); + g_cpu_nestcount[cpu]++; + } - /* Handle nested calls to enter_critical_section() from the same - * interrupt. - */ + /* This is the first call to enter_critical_section from the + * interrupt handler. + */ - cpu = this_cpu(); - if (g_cpu_nestcount[cpu] > 0) - { - DEBUGASSERT(spin_is_locked(&g_cpu_irqlock) && - g_cpu_nestcount[cpu] < UINT8_MAX); - g_cpu_nestcount[cpu]++; - } + else + { + int paused = false; - /* This is the first call to enter_critical_section from the - * interrupt handler. + /* Make sure that the g_cpu_irqset was not already set + * by previous logic on this CPU that was executed by the + * interrupt handler. We know that the bit in g_cpu_irqset + * for this CPU was zero on entry into the interrupt handler, + * so if it is non-zero now then we know that was the case. */ - else + if ((g_cpu_irqset & (1 << cpu)) == 0) { - /* Make sure that the g_cpu_irqset was not already set - * by previous logic on this CPU that was executed by the - * interrupt handler. We know that the bit in g_cpu_irqset - * for this CPU was zero on entry into the interrupt handler, - * so if it is non-zero now then we know that was the case. + /* Wait until we can get the spinlock (meaning that we are + * no longer blocked by the critical section). */ - if ((g_cpu_irqset & (1 << cpu)) == 0) +try_again_in_irq: + if (!irq_waitlock(cpu)) { - /* Wait until we can get the spinlock (meaning that we are - * no longer blocked by the critical section). + /* We are in a deadlock condition due to a pending + * pause request interrupt. Break the deadlock by + * handling the pause request now. */ -try_again_in_irq: - if (!irq_waitlock(cpu)) + if (!paused) { - /* We are in a deadlock condition due to a pending - * pause request interrupt. Break the deadlock by - * handling the pause request now. - */ - - DEBUGVERIFY(up_cpu_paused(cpu)); - - /* NOTE: As the result of up_cpu_paused(cpu), this CPU - * might set g_cpu_irqset in nxsched_resume_scheduler() - * However, another CPU might hold g_cpu_irqlock. - * To avoid this situation, releae g_cpu_irqlock first. - */ - - if ((g_cpu_irqset & (1 << cpu)) != 0) - { - spin_clrbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock, - &g_cpu_irqlock); - } - - /* NOTE: Here, this CPU does not hold g_cpu_irqlock, - * so call irq_waitlock(cpu) to acquire g_cpu_irqlock. - */ - - goto try_again_in_irq; + up_cpu_paused_save(); } + + DEBUGVERIFY(up_cpu_paused(cpu)); + paused = true; + + /* NOTE: As the result of up_cpu_paused(cpu), this CPU + * might set g_cpu_irqset in nxsched_resume_scheduler() + * However, another CPU might hold g_cpu_irqlock. + * To avoid this situation, releae g_cpu_irqlock first. + */ + + if ((g_cpu_irqset & (1 << cpu)) != 0) + { + spin_clrbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock, + &g_cpu_irqlock); + } + + /* NOTE: Here, this CPU does not hold g_cpu_irqlock, + * so call irq_waitlock(cpu) to acquire g_cpu_irqlock. + */ + + goto try_again_in_irq; } + } - /* In any event, the nesting count is now one */ + /* In any event, the nesting count is now one */ - g_cpu_nestcount[cpu] = 1; + g_cpu_nestcount[cpu] = 1; - /* Also set the CPU bit so that other CPUs will be aware that - * this CPU holds the critical section. - */ + /* Also set the CPU bit so that other CPUs will be aware that + * this CPU holds the critical section. + */ - spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock, - &g_cpu_irqlock); + spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock, + &g_cpu_irqlock); + if (paused) + { + up_cpu_paused_restore(); } } - else + } + else + { + /* Normal tasking environment. + * + * Get the TCB of the currently executing task on this CPU (avoid + * using this_task() which can recurse. + */ + + cpu = this_cpu(); + rtcb = current_task(cpu); + DEBUGASSERT(rtcb != NULL); + + /* Do we already have interrupts disabled? */ + + if (rtcb->irqcount > 0) { - /* Normal tasking environment. + /* Yes... make sure that the spinlock is set and increment the + * IRQ lock count. * - * Get the TCB of the currently executing task on this CPU (avoid - * using this_task() which can recurse. + * NOTE: If irqcount > 0 then (1) we are in a critical section, + * and (2) this CPU should hold the lock. */ - cpu = this_cpu(); - rtcb = current_task(cpu); - DEBUGASSERT(rtcb != NULL); + DEBUGASSERT(spin_is_locked(&g_cpu_irqlock) && + (g_cpu_irqset & (1 << this_cpu())) != 0 && + rtcb->irqcount < INT16_MAX); + rtcb->irqcount++; + } + else + { + /* If we get here with irqcount == 0, then we know that the + * current task running on this CPU is not in a critical + * section. However other tasks on other CPUs may be in a + * critical section. If so, we must wait until they release + * the spinlock. + */ - /* Do we already have interrupts disabled? */ + DEBUGASSERT((g_cpu_irqset & (1 << cpu)) == 0); - if (rtcb->irqcount > 0) + if (!irq_waitlock(cpu)) { - /* Yes... make sure that the spinlock is set and increment the - * IRQ lock count. - * - * NOTE: If irqcount > 0 then (1) we are in a critical section, - * and (2) this CPU should hold the lock. + /* We are in a deadlock condition due to a pending pause + * request interrupt. Re-enable interrupts on this CPU + * and try again. Briefly re-enabling interrupts should + * be sufficient to permit processing the pending pause + * request. */ - DEBUGASSERT(spin_is_locked(&g_cpu_irqlock) && - (g_cpu_irqset & (1 << this_cpu())) != 0 && - rtcb->irqcount < INT16_MAX); - rtcb->irqcount++; + up_irq_restore(ret); + goto try_again; } - else - { - /* If we get here with irqcount == 0, then we know that the - * current task running on this CPU is not in a critical - * section. However other tasks on other CPUs may be in a - * critical section. If so, we must wait until they release - * the spinlock. - */ - - DEBUGASSERT((g_cpu_irqset & (1 << cpu)) == 0); - - if (!irq_waitlock(cpu)) - { - /* We are in a deadlock condition due to a pending pause - * request interrupt. Re-enable interrupts on this CPU - * and try again. Briefly re-enabling interrupts should - * be sufficient to permit processing the pending pause - * request. - */ - - up_irq_restore(ret); - goto try_again; - } - /* Then set the lock count to 1. - * - * Interrupts disables must follow a stacked order. We - * cannot other context switches to re-order the enabling - * disabling of interrupts. - * - * The scheduler accomplishes this by treating the irqcount - * like lockcount: Both will disable pre-emption. - */ + /* Then set the lock count to 1. + * + * Interrupts disables must follow a stacked order. We + * cannot other context switches to re-order the enabling + * disabling of interrupts. + * + * The scheduler accomplishes this by treating the irqcount + * like lockcount: Both will disable pre-emption. + */ - spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock, - &g_cpu_irqlock); - rtcb->irqcount = 1; + spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock, + &g_cpu_irqlock); + rtcb->irqcount = 1; - /* Note that we have entered the critical section */ + /* Note that we have entered the critical section */ #ifdef CONFIG_SCHED_CRITMONITOR - nxsched_critmon_csection(rtcb, true); + nxsched_critmon_csection(rtcb, true); #endif #ifdef CONFIG_SCHED_INSTRUMENTATION_CSECTION - sched_note_csection(rtcb, true); + sched_note_csection(rtcb, true); #endif - } } } @@ -400,11 +405,9 @@ irqstate_t enter_critical_section(void) ret = up_irq_save(); - /* Check if we were called from an interrupt handler and that the task - * lists have been initialized. - */ + /* Check if we were called from an interrupt handler */ - if (!up_interrupt_context() && g_nx_initstate >= OSINIT_TASKLISTS) + if (!up_interrupt_context()) { FAR struct tcb_s *rtcb = this_task(); DEBUGASSERT(rtcb != NULL); @@ -447,137 +450,101 @@ void leave_critical_section(irqstate_t flags) { int cpu; - /* Verify that the system has sufficiently initialized so that the task - * lists are valid. + /* If called from an interrupt handler, then just release the + * spinlock. The interrupt handling logic should already hold the + * spinlock if enter_critical_section() has been called. Unlocking + * the spinlock will allow interrupt handlers on other CPUs to execute + * again. */ - if (g_nx_initstate >= OSINIT_TASKLISTS) + if (up_interrupt_context()) { - /* If called from an interrupt handler, then just release the - * spinlock. The interrupt handling logic should already hold the - * spinlock if enter_critical_section() has been called. Unlocking - * the spinlock will allow interrupt handlers on other CPUs to execute - * again. + /* We are in an interrupt handler. Check if the last call to + * enter_critical_section() was nested. */ - if (up_interrupt_context()) + cpu = this_cpu(); + if (g_cpu_nestcount[cpu] > 1) { - /* We are in an interrupt handler. Check if the last call to - * enter_critical_section() was nested. - */ - - cpu = this_cpu(); - if (g_cpu_nestcount[cpu] > 1) - { - /* Yes.. then just decrement the nesting count */ - - DEBUGASSERT(spin_is_locked(&g_cpu_irqlock)); - g_cpu_nestcount[cpu]--; - } - else - { - /* No, not nested. Restore the g_cpu_irqset for this CPU - * and release the spinlock (if necessary). - */ + /* Yes.. then just decrement the nesting count */ - DEBUGASSERT(spin_is_locked(&g_cpu_irqlock) && - g_cpu_nestcount[cpu] == 1); + DEBUGASSERT(spin_is_locked(&g_cpu_irqlock)); + g_cpu_nestcount[cpu]--; + } + else + { + /* No, not nested. Restore the g_cpu_irqset for this CPU + * and release the spinlock (if necessary). + */ - FAR struct tcb_s *rtcb = current_task(cpu); - DEBUGASSERT(rtcb != NULL); + DEBUGASSERT(spin_is_locked(&g_cpu_irqlock) && + g_cpu_nestcount[cpu] == 1); - if (rtcb->irqcount <= 0) - { - spin_clrbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock, - &g_cpu_irqlock); - } + FAR struct tcb_s *rtcb = current_task(cpu); + DEBUGASSERT(rtcb != NULL); - g_cpu_nestcount[cpu] = 0; + if (rtcb->irqcount <= 0) + { + spin_clrbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock, + &g_cpu_irqlock); } + + g_cpu_nestcount[cpu] = 0; } - else - { - FAR struct tcb_s *rtcb; + } + else + { + FAR struct tcb_s *rtcb; - /* Get the TCB of the currently executing task on this CPU (avoid - * using this_task() which can recurse. - */ + /* Get the TCB of the currently executing task on this CPU (avoid + * using this_task() which can recurse. + */ - cpu = this_cpu(); - rtcb = current_task(cpu); - DEBUGASSERT(rtcb != NULL && rtcb->irqcount > 0); + cpu = this_cpu(); + rtcb = current_task(cpu); + DEBUGASSERT(rtcb != NULL && rtcb->irqcount > 0); - /* Normal tasking context. We need to coordinate with other - * tasks. - * - * Will we still have interrupts disabled after decrementing the - * count? - */ + /* Normal tasking context. We need to coordinate with other + * tasks. + * + * Will we still have interrupts disabled after decrementing the + * count? + */ - if (rtcb->irqcount > 1) - { - /* Yes... the spinlock should remain set */ + if (rtcb->irqcount > 1) + { + /* Yes... the spinlock should remain set */ - DEBUGASSERT(spin_is_locked(&g_cpu_irqlock)); - rtcb->irqcount--; - } - else - { - /* No.. Note that we have left the critical section */ + DEBUGASSERT(spin_is_locked(&g_cpu_irqlock)); + rtcb->irqcount--; + } + else + { + /* No.. Note that we have left the critical section */ #ifdef CONFIG_SCHED_CRITMONITOR - nxsched_critmon_csection(rtcb, false); + nxsched_critmon_csection(rtcb, false); #endif #ifdef CONFIG_SCHED_INSTRUMENTATION_CSECTION - sched_note_csection(rtcb, false); + sched_note_csection(rtcb, false); #endif - /* Decrement our count on the lock. If all CPUs have - * released, then unlock the spinlock. - */ - - DEBUGASSERT(spin_is_locked(&g_cpu_irqlock) && - (g_cpu_irqset & (1 << cpu)) != 0); - - /* Check if releasing the lock held by this CPU will unlock the - * critical section. - */ - - if ((g_cpu_irqset & ~(1 << cpu)) == 0) - { - /* Yes.. Check if there are pending tasks and that pre- - * emption is also enabled. This is necessary because we - * may have deferred the nxsched_merge_pending() call in - * sched_unlock() because we were within a critical - * section then. - */ + /* Decrement our count on the lock. If all CPUs have + * released, then unlock the spinlock. + */ - if (g_pendingtasks.head != NULL && - !nxsched_islocked_global()) - { - /* Release any ready-to-run tasks that have collected - * in g_pendingtasks. NOTE: This operation has a very - * high likelihood of causing this task to be switched - * out! - */ - - if (nxsched_merge_pending()) - { - up_switch_context(this_task(), rtcb); - } - } - } + DEBUGASSERT(spin_is_locked(&g_cpu_irqlock) && + (g_cpu_irqset & (1 << cpu)) != 0); - /* Now, possibly on return from a context switch, clear our - * count on the lock. If all CPUs have released the lock, - * then unlock the global IRQ spinlock. - */ + /* Now, possibly on return from a context switch, clear our + * count on the lock. If all CPUs have released the lock, + * then unlock the global IRQ spinlock. + */ - rtcb->irqcount = 0; - spin_clrbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock, - &g_cpu_irqlock); + rtcb->irqcount = 0; + spin_clrbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock, + &g_cpu_irqlock); - /* Have all CPUs released the lock? */ - } + /* Have all CPUs released the lock? */ } } @@ -596,7 +563,7 @@ void leave_critical_section(irqstate_t flags) * lists have been initialized. */ - if (!up_interrupt_context() && g_nx_initstate >= OSINIT_TASKLISTS) + if (!up_interrupt_context()) { FAR struct tcb_s *rtcb = this_task(); DEBUGASSERT(rtcb != NULL); @@ -625,80 +592,6 @@ void leave_critical_section(irqstate_t flags) } #endif -/**************************************************************************** - * Name: irq_cpu_locked - * - * Description: - * Test if the IRQ lock set OR if this CPU holds the IRQ lock - * There is an interaction with pre-emption controls and IRQ locking: - * Even if the pre-emption is enabled, tasks will be forced to pend if - * the IRQ lock is also set UNLESS the CPU starting the task is the - * holder of the IRQ lock. - * - * Input Parameters: - * cpu - Points to which cpu - * - * Returned Value: - * true - IRQs are locked by a different CPU. - * false - IRQs are unlocked OR if they are locked BUT this CPU - * is the holder of the lock. - * - * Warning: This values are volatile at only valid at the instance that - * the CPU set was queried. - * - ****************************************************************************/ - -#ifdef CONFIG_SMP -bool irq_cpu_locked(int cpu) -{ - cpu_set_t irqset; - - /* g_cpu_irqset is not valid in early phases of initialization */ - - if (g_nx_initstate < OSINIT_OSREADY) - { - /* We are still single threaded. In either state of g_cpu_irqlock, - * the correct return value should always be false. - */ - - return false; - } - - /* Test if g_cpu_irqlock is locked. We don't really need to use check - * g_cpu_irqlock to do this, we can use the g_cpu_set. - * - * Sample the g_cpu_irqset once. That is an atomic operation. All - * subsequent operations will operate on the sampled cpu set. - */ - - irqset = (cpu_set_t)g_cpu_irqset; - if (irqset != 0) - { - /* Some CPU holds the lock. So g_cpu_irqlock should be locked. - * Return false if the 'cpu' is the holder of the lock; return - * true if g_cpu_irqlock is locked, but this CPU is not the - * holder of the lock. - */ - - return ((irqset & (1 << cpu)) == 0); - } - - /* No CPU holds the lock */ - - else - { - /* In this case g_cpu_irqlock should be unlocked. However, if - * the lock was established in the interrupt handler AND there are - * no bits set in g_cpu_irqset, that probably means only that - * critical section was established from an interrupt handler. - * Return false in either case. - */ - - return false; - } -} -#endif - /**************************************************************************** * Name: restore_critical_section * diff --git a/sched/irq/irq_spinlock.c b/sched/irq/irq_spinlock.c index 21a90762eba1a..efbf82023417c 100644 --- a/sched/irq/irq_spinlock.c +++ b/sched/irq/irq_spinlock.c @@ -31,7 +31,7 @@ #include "sched/sched.h" -#if defined(CONFIG_SMP) +#if defined(CONFIG_SPINLOCK) /**************************************************************************** * Public Data @@ -100,7 +100,7 @@ irqstate_t spin_lock_irqsave(spinlock_t *lock) if (NULL == lock) { - int me = this_cpu(); + int me = up_cpu_index(); if (0 == g_irq_spin_count[me]) { spin_lock(&g_irq_spin); @@ -128,7 +128,7 @@ irqstate_t spin_lock_irqsave_wo_note(spinlock_t *lock) if (NULL == lock) { - int me = this_cpu(); + int me = up_cpu_index(); if (0 == g_irq_spin_count[me]) { spin_lock_wo_note(&g_irq_spin); @@ -178,7 +178,7 @@ void spin_unlock_irqrestore(spinlock_t *lock, irqstate_t flags) { if (NULL == lock) { - int me = this_cpu(); + int me = up_cpu_index(); DEBUGASSERT(0 < g_irq_spin_count[me]); g_irq_spin_count[me]--; @@ -203,7 +203,7 @@ void spin_unlock_irqrestore_wo_note(spinlock_t *lock, irqstate_t flags) { if (NULL == lock) { - int me = this_cpu(); + int me = up_cpu_index(); DEBUGASSERT(0 < g_irq_spin_count[me]); g_irq_spin_count[me]--; @@ -351,7 +351,7 @@ irqstate_t write_lock_irqsave(rwlock_t *lock) if (NULL == lock) { - int me = this_cpu(); + int me = up_cpu_index(); if (0 == g_irq_rwspin_count[me]) { write_lock(&g_irq_rwspin); @@ -401,7 +401,7 @@ void write_unlock_irqrestore(rwlock_t *lock, irqstate_t flags) { if (NULL == lock) { - int me = this_cpu(); + int me = up_cpu_index(); DEBUGASSERT(0 < g_irq_rwspin_count[me]); g_irq_rwspin_count[me]--; @@ -418,4 +418,4 @@ void write_unlock_irqrestore(rwlock_t *lock, irqstate_t flags) up_irq_restore(flags); } #endif /* CONFIG_RW_SPINLOCK */ -#endif /* CONFIG_SMP */ +#endif /* CONFIG_SPINLOCK */ diff --git a/sched/misc/CMakeLists.txt b/sched/misc/CMakeLists.txt index dc410e7121931..a8eee418cb869 100644 --- a/sched/misc/CMakeLists.txt +++ b/sched/misc/CMakeLists.txt @@ -1,5 +1,5 @@ # ############################################################################## -# sched/sched/CMakeLists.txt +# sched/misc/CMakeLists.txt # # Licensed to the Apache Software Foundation (ASF) under one or more contributor # license agreements. See the NOTICE file distributed with this work for @@ -24,10 +24,6 @@ if(CONFIG_ARCH_DEADLOCKDUMP) list(APPEND SRCS deadlock.c) endif() -if(CONFIG_DUMP_ON_EXIT) - list(APPEND SRCS dump.c) -endif() - if(CONFIG_BOARD_COREDUMP_SYSLOG OR CONFIG_BOARD_COREDUMP_BLKDEV) list(APPEND SRCS coredump.c) endif() diff --git a/sched/misc/Make.defs b/sched/misc/Make.defs index 08142fadf3702..ca27b7405c190 100644 --- a/sched/misc/Make.defs +++ b/sched/misc/Make.defs @@ -24,10 +24,6 @@ ifeq ($(CONFIG_ARCH_DEADLOCKDUMP),y) CSRCS += deadlock.c endif -ifeq ($(CONFIG_DUMP_ON_EXIT),y) -CSRCS += dump.c -endif - ifneq ($(CONFIG_BOARD_COREDUMP_SYSLOG)$(CONFIG_BOARD_COREDUMP_BLKDEV),) CSRCS += coredump.c endif diff --git a/sched/misc/assert.c b/sched/misc/assert.c index b63f664c28c62..6d87199eb143c 100644 --- a/sched/misc/assert.c +++ b/sched/misc/assert.c @@ -71,6 +71,13 @@ #endif #define DUMP_PTR(p, x) ((uintptr_t)(&(p)[(x)]) < stack_top ? (p)[(x)] : 0) +#define DUMP_STRIDE (sizeof(FAR void *) * 8) + +#if UINTPTR_MAX <= UINT32_MAX +# define DUMP_FORMAT " %08" PRIxPTR "" +#elif UINTPTR_MAX <= UINT64_MAX +# define DUMP_FORMAT " %016" PRIxPTR "" +#endif /**************************************************************************** * Private Data @@ -128,13 +135,12 @@ static void stack_dump(uintptr_t sp, uintptr_t stack_top) { uintptr_t stack; - for (stack = sp; stack <= stack_top; stack += 32) + for (stack = sp; stack <= stack_top; stack += DUMP_STRIDE) { - FAR uint32_t *ptr = (FAR uint32_t *)stack; + FAR uintptr_t *ptr = (FAR uintptr_t *)stack; - _alert("%p: %08" PRIx32 " %08" PRIx32 " %08" PRIx32 - " %08" PRIx32 " %08" PRIx32 " %08" PRIx32 " %08" PRIx32 - " %08" PRIx32 "\n", + _alert("%p:"DUMP_FORMAT DUMP_FORMAT DUMP_FORMAT DUMP_FORMAT + DUMP_FORMAT DUMP_FORMAT DUMP_FORMAT DUMP_FORMAT "\n", (FAR void *)stack, DUMP_PTR(ptr, 0), DUMP_PTR(ptr , 1), DUMP_PTR(ptr, 2), DUMP_PTR(ptr, 3), DUMP_PTR(ptr, 4), DUMP_PTR(ptr, 5), DUMP_PTR(ptr , 6), DUMP_PTR(ptr, 7)); @@ -160,9 +166,9 @@ static void dump_stack(FAR const char *tag, uintptr_t sp, /* Get more information */ - if (sp - 32 >= base) + if (sp - DUMP_STRIDE >= base) { - sp -= 32; + sp -= DUMP_STRIDE; } stack_dump(sp, top); @@ -194,7 +200,7 @@ static void dump_stack(FAR const char *tag, uintptr_t sp, static void dump_stacks(FAR struct tcb_s *rtcb, uintptr_t sp) { #if CONFIG_ARCH_INTERRUPTSTACK > 0 - uintptr_t intstack_base = up_get_intstackbase(); + uintptr_t intstack_base = up_get_intstackbase(up_cpu_index()); size_t intstack_size = CONFIG_ARCH_INTERRUPTSTACK; uintptr_t intstack_top = intstack_base + intstack_size; uintptr_t intstack_sp = 0; @@ -243,7 +249,7 @@ static void dump_stacks(FAR struct tcb_s *rtcb, uintptr_t sp) intstack_base, intstack_size, #ifdef CONFIG_STACK_COLORATION - up_check_intstack() + up_check_intstack(up_cpu_index()) #else 0 #endif @@ -405,17 +411,8 @@ static void dump_backtrace(FAR struct tcb_s *tcb, FAR void *arg) static void dump_tasks(void) { -#if CONFIG_ARCH_INTERRUPTSTACK > 0 && defined(CONFIG_STACK_COLORATION) - size_t stack_used = up_check_intstack(); - size_t stack_filled = 0; - - if (stack_used > 0) - { - /* Use fixed-point math with one decimal place */ - - stack_filled = 10 * 100 * - stack_used / CONFIG_ARCH_INTERRUPTSTACK; - } +#if CONFIG_ARCH_INTERRUPTSTACK > 0 + int cpu; #endif /* Dump interesting properties of each task in the crash environment */ @@ -438,31 +435,50 @@ static void dump_tasks(void) " COMMAND\n"); #if CONFIG_ARCH_INTERRUPTSTACK > 0 - _alert(" ---- ---" + for (cpu = 0; cpu < CONFIG_SMP_NCPUS; cpu++) + { +# ifdef CONFIG_STACK_COLORATION + size_t stack_used = up_check_intstack(cpu); + size_t stack_filled = 0; + + if (stack_used > 0) + { + /* Use fixed-point math with one decimal place */ + + stack_filled = 10 * 100 * + stack_used / CONFIG_ARCH_INTERRUPTSTACK; + } +# endif + + _alert(" ---- ---" # ifdef CONFIG_SMP - " ----" + " %4d" # endif - " --- --------" - " ------- ---" - " ------- ----------" - " ----------------" - " %p" - " %7u" + " --- --------" + " ------- ---" + " ------- ----------" + " ----------------" + " %p" + " %7u" # ifdef CONFIG_STACK_COLORATION - " %7zu %3zu.%1zu%%%c" + " %7zu %3zu.%1zu%%%c" # endif # ifndef CONFIG_SCHED_CPULOAD_NONE - " ----" + " ----" # endif - " irq\n" - , (FAR void *)up_get_intstackbase() - , CONFIG_ARCH_INTERRUPTSTACK + " irq\n" +#ifdef CONFIG_SMP + , cpu +#endif + , (FAR void *)up_get_intstackbase(cpu) + , CONFIG_ARCH_INTERRUPTSTACK # ifdef CONFIG_STACK_COLORATION - , stack_used - , stack_filled / 10, stack_filled % 10, - (stack_filled >= 10 * 80 ? '!' : ' ') + , stack_used + , stack_filled / 10, stack_filled % 10, + (stack_filled >= 10 * 80 ? '!' : ' ') # endif - ); + ); + } #endif nxsched_foreach(dump_task, NULL); @@ -514,8 +530,8 @@ void _assert(FAR const char *filename, int linenum, #endif struct panic_notifier_s notifier_data; struct utsname name; + irqstate_t flags; bool fatal = true; - int flags; #if CONFIG_TASK_NAME_SIZE > 0 if (rtcb->group && !(rtcb->flags & TCB_FLAG_TTYPE_KERNEL)) @@ -526,8 +542,6 @@ void _assert(FAR const char *filename, int linenum, flags = enter_critical_section(); - sched_lock(); - /* try to save current context if regs is null */ if (regs == NULL) @@ -581,7 +595,7 @@ void _assert(FAR const char *filename, int linenum, msg ? msg : "", filename ? filename : "", linenum, #ifdef CONFIG_SMP - up_cpu_index(), + this_cpu(), #endif #if CONFIG_TASK_NAME_SIZE > 0 rtcb->name, @@ -662,7 +676,5 @@ void _assert(FAR const char *filename, int linenum, #endif } - sched_unlock(); - leave_critical_section(flags); } diff --git a/sched/misc/dump.c b/sched/misc/dump.c deleted file mode 100644 index d8aebbd9f0747..0000000000000 --- a/sched/misc/dump.c +++ /dev/null @@ -1,97 +0,0 @@ -/**************************************************************************** - * sched/misc/dump.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_DUMP_ON_EXIT - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: dumphandler - * - * Description: - * Dump the state of all tasks whenever on task exits. This is debug - * instrumentation that was added to check file-related reference counting - * but could be useful again sometime in the future. - * - ****************************************************************************/ - -static void dumphandler(FAR struct tcb_s *tcb, FAR void *arg) -{ - FAR struct filelist *filelist; - int i; - int j; - - sinfo(" TCB=%p name=%s\n", tcb, tcb->name); - sinfo(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state); - - filelist = &tcb->group->tg_filelist; - for (i = 0; i < filelist->fl_rows; i++) - { - for (j = 0; j < CONFIG_NFILE_DESCRIPTORS_PER_BLOCK; j++) - { - struct inode *inode = filelist->fl_files[i][j].f_inode; - if (inode) - { - sinfo(" fd=%d refcount=%d\n", - i * CONFIG_NFILE_DESCRIPTORS_PER_BLOCK + j, - inode->i_crefs); - } - } - } -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: nxsched_dumponexit - * - * Description: - * Dump the state of all tasks whenever on task exits. This is debug - * instrumentation that was added to check file-related reference counting - * but could be useful again sometime in the future. - * - ****************************************************************************/ - -void nxsched_dumponexit(void) -{ - sinfo("Other tasks:\n"); - nxsched_foreach(dumphandler, NULL); -} - -#endif /* CONFIG_DUMP_ON_EXIT */ diff --git a/sched/mqueue/CMakeLists.txt b/sched/mqueue/CMakeLists.txt index 75d51e76d2709..4373aff376b37 100644 --- a/sched/mqueue/CMakeLists.txt +++ b/sched/mqueue/CMakeLists.txt @@ -19,6 +19,11 @@ # ############################################################################## set(SRCS) + +if(NOT CONFIG_DISABLE_MQUEUE OR NOT CONFIG_DISABLE_MQUEUE) + list(APPEND SRCS mq_initialize.c mq_waitirq.c mq_recover.c) +endif() + if(NOT CONFIG_DISABLE_MQUEUE) list( @@ -30,13 +35,10 @@ if(NOT CONFIG_DISABLE_MQUEUE) mq_receive.c mq_timedreceive.c mq_rcvinternal.c - mq_initialize.c mq_msgfree.c mq_msgqalloc.c mq_msgqfree.c - mq_recover.c mq_setattr.c - mq_waitirq.c mq_notify.c mq_getattr.c) diff --git a/sched/mqueue/Make.defs b/sched/mqueue/Make.defs index 2772ed17186bd..0608bf733987b 100644 --- a/sched/mqueue/Make.defs +++ b/sched/mqueue/Make.defs @@ -18,12 +18,16 @@ # ############################################################################ +ifneq ($(CONFIG_DISABLE_MQUEUE)$(CONFIG_DISABLE_MQUEUE_SYSV),yy) + CSRCS += mq_initialize.c mq_waitirq.c mq_recover.c +endif + ifneq ($(CONFIG_DISABLE_MQUEUE),y) CSRCS += mq_send.c mq_timedsend.c mq_sndinternal.c mq_receive.c -CSRCS += mq_timedreceive.c mq_rcvinternal.c mq_initialize.c -CSRCS += mq_msgfree.c mq_msgqalloc.c mq_msgqfree.c mq_recover.c -CSRCS += mq_setattr.c mq_waitirq.c mq_notify.c mq_getattr.c +CSRCS += mq_timedreceive.c mq_rcvinternal.c mq_getattr.c +CSRCS += mq_msgfree.c mq_msgqalloc.c mq_msgqfree.c +CSRCS += mq_setattr.c mq_notify.c endif diff --git a/sched/mqueue/mq_initialize.c b/sched/mqueue/mq_initialize.c index 44a137f35f217..b0cc3ea5a90d4 100644 --- a/sched/mqueue/mq_initialize.c +++ b/sched/mqueue/mq_initialize.c @@ -29,63 +29,79 @@ #include #include "mqueue/mqueue.h" +#include "mqueue/msg.h" /**************************************************************************** * Public Data ****************************************************************************/ +#ifndef CONFIG_DISABLE_MQUEUE + /* The g_msgfree is a list of messages that are available for general * use. The number of messages in this list is a system configuration * item. */ -struct list_node g_msgfree = LIST_INITIAL_VALUE(g_msgfree); +struct list_node g_msgfree; /* The g_msgfreeInt is a list of messages that are reserved for use by * interrupt handlers. */ -struct list_node g_msgfreeirq = LIST_INITIAL_VALUE(g_msgfreeirq); +struct list_node g_msgfreeirq; + +#endif /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: mq_msgblockalloc + * Name: mq_msgblockinit * * Description: - * Allocate a block of messages and place them on the free list. + * Initialize a block of messages and place them on the free list. * * Input Parameters: * queue * ****************************************************************************/ -static void -mq_msgblockalloc(FAR struct list_node *list, uint16_t nmsgs, - uint8_t alloc_type) +#ifndef CONFIG_DISABLE_MQUEUE +static FAR void * mq_msgblockinit(FAR struct list_node *list, + FAR struct mqueue_msg_s *mqmsgblock, + uint16_t nmsgs, uint8_t alloc_type) { - FAR struct mqueue_msg_s *mqmsgblock; + int i; + for (i = 0; i < nmsgs; i++) + { + mqmsgblock->type = alloc_type; + list_add_tail(list, &mqmsgblock->node); + mqmsgblock++; + } - /* The list must be loaded at initialization time to hold the - * configured number of messages. - */ + return mqmsgblock; +} +#endif - mqmsgblock = (FAR struct mqueue_msg_s *) - kmm_malloc(sizeof(struct mqueue_msg_s) * nmsgs); +/**************************************************************************** + * Name: sysv_msgblockinit + ****************************************************************************/ - if (mqmsgblock) +#ifndef CONFIG_DISABLE_MQUEUE_SYSV +static FAR void *sysv_msgblockinit(FAR struct list_node *list, + FAR struct msgbuf_s *msg, uint16_t nmsgs) +{ + int i; + for (i = 0; i < nmsgs; i++) { - int i; - for (i = 0; i < nmsgs; i++) - { - mqmsgblock->type = alloc_type; - list_add_tail(list, &mqmsgblock->node); - mqmsgblock++; - } + list_add_tail(list, &msg->node); + msg++; } + + return msg; } +#endif /**************************************************************************** * Public Functions @@ -109,19 +125,45 @@ mq_msgblockalloc(FAR struct list_node *list, uint16_t nmsgs, void nxmq_initialize(void) { + FAR void *msg; + sched_trace_begin(); - /* Allocate a block of messages for general use */ + msg = kmm_malloc( +#ifndef CONFIG_DISABLE_MQUEUE + sizeof(struct mqueue_msg_s) * + (CONFIG_PREALLOC_MQ_MSGS + CONFIG_PREALLOC_MQ_IRQ_MSGS) +#endif +#ifndef CONFIG_DISABLE_MQUEUE_SYSV + + sizeof(struct msgbuf_s) * CONFIG_PREALLOC_MQ_MSGS +#endif + ); + + DEBUGASSERT(msg != NULL); + + /* Initialize a block of messages for general use */ - mq_msgblockalloc(&g_msgfree, CONFIG_PREALLOC_MQ_MSGS, - MQ_ALLOC_FIXED); +#ifndef CONFIG_DISABLE_MQUEUE + list_initialize(&g_msgfree); - /* Allocate a block of messages for use exclusively by + msg = mq_msgblockinit(&g_msgfree, msg, CONFIG_PREALLOC_MQ_MSGS, + MQ_ALLOC_FIXED); + + /* Initialize a block of messages for use exclusively by * interrupt handlers */ - mq_msgblockalloc(&g_msgfreeirq, CONFIG_PREALLOC_MQ_IRQ_MSGS, - MQ_ALLOC_IRQ); + list_initialize(&g_msgfreeirq); + + msg = mq_msgblockinit(&g_msgfreeirq, msg, CONFIG_PREALLOC_MQ_IRQ_MSGS, + MQ_ALLOC_IRQ); +#endif + +#ifndef CONFIG_DISABLE_MQUEUE_SYSV + list_initialize(&g_msgfreelist); + + msg = sysv_msgblockinit(&g_msgfreelist, msg, CONFIG_PREALLOC_MQ_MSGS); +#endif sched_trace_end(); } diff --git a/sched/mqueue/mq_timedreceive.c b/sched/mqueue/mq_timedreceive.c index f8b3153a7dc6c..db5833fe314c9 100644 --- a/sched/mqueue/mq_timedreceive.c +++ b/sched/mqueue/mq_timedreceive.c @@ -102,22 +102,12 @@ static void nxmq_rcvtimeout(wdparm_t pid) ****************************************************************************/ /**************************************************************************** - * Name: file_mq_timedreceive + * Name: file_mq_timedreceive_internal * * Description: - * This function receives the oldest of the highest priority messages from - * the message queue specified by "mq." If the message queue is empty - * and O_NONBLOCK was not set, file_mq_timedreceive() will block until a - * message is added to the message queue (or until a timeout occurs). - * - * file_mq_timedreceive() is an internal OS interface. It is functionally - * equivalent to mq_timedreceive() except that: - * - * - It is not a cancellation point, and - * - It does not modify the errno value. - * - * See comments with mq_timedreceive() for a more complete description of - * the behavior of this function + * This is an internal function of file_mq_timedreceive()/ + * file_mq_tickreceive(), please refer to the detailed description for + * more information. * * Input Parameters: * mq - Message Queue Descriptor @@ -125,6 +115,8 @@ static void nxmq_rcvtimeout(wdparm_t pid) * msglen - Size of the buffer in bytes * prio - If not NULL, the location to store message priority. * abstime - the absolute time to wait until a timeout is declared. + * ticks - Ticks to wait from the start time until the semaphore is + * posted. * * Returned Value: * This is an internal OS interface and should not be used by applications. @@ -134,9 +126,11 @@ static void nxmq_rcvtimeout(wdparm_t pid) * ****************************************************************************/ -ssize_t file_mq_timedreceive(FAR struct file *mq, FAR char *msg, - size_t msglen, FAR unsigned int *prio, - FAR const struct timespec *abstime) +static ssize_t +file_mq_timedreceive_internal(FAR struct file *mq, FAR char *msg, + size_t msglen, FAR unsigned int *prio, + FAR const struct timespec *abstime, + sclock_t ticks) { FAR struct tcb_s *rtcb = this_task(); FAR struct mqueue_inode_s *msgq; @@ -156,11 +150,6 @@ ssize_t file_mq_timedreceive(FAR struct file *mq, FAR char *msg, return ret; } - if (!abstime || abstime->tv_nsec < 0 || abstime->tv_nsec >= 1000000000) - { - return -EINVAL; - } - msgq = mq->f_inode->i_private; /* Furthermore, nxmq_wait_receive() expects to have interrupts disabled @@ -175,28 +164,37 @@ ssize_t file_mq_timedreceive(FAR struct file *mq, FAR char *msg, if (list_is_empty(&msgq->msglist)) { - sclock_t ticks; - - /* Convert the timespec to clock ticks. We must have interrupts - * disabled here so that this time stays valid until the wait begins. - */ - - ret = clock_abstime2ticks(CLOCK_REALTIME, abstime, &ticks); + if (abstime != NULL) + { + if (abstime->tv_nsec < 0 || abstime->tv_nsec >= 1000000000) + { + ret = -EINVAL; + } + else + { + /* Convert the timespec to clock ticks. + * We must have interrupts disabled here so that + * this time stays valid until the wait begins. + */ + + ret = clock_abstime2ticks(CLOCK_REALTIME, abstime, &ticks); + } + + /* Handle any time-related errors */ + + if (ret != OK) + { + goto errout_in_critical_section; + } + } /* If the time has already expired and the message queue is empty, * return immediately. */ - if (ret == OK && ticks <= 0) + if (ticks <= 0) { - ret = ETIMEDOUT; - } - - /* Handle any time-related errors */ - - if (ret != OK) - { - ret = -ret; + ret = -ETIMEDOUT; goto errout_in_critical_section; } @@ -238,6 +236,87 @@ ssize_t file_mq_timedreceive(FAR struct file *mq, FAR char *msg, return ret; } +/**************************************************************************** + * Name: file_mq_timedreceive + * + * Description: + * This function receives the oldest of the highest priority messages from + * the message queue specified by "mq." If the message queue is empty + * and O_NONBLOCK was not set, file_mq_timedreceive() will block until a + * message is added to the message queue (or until a timeout occurs). + * + * file_mq_timedreceive() is an internal OS interface. It is functionally + * equivalent to mq_timedreceive() except that: + * + * - It is not a cancellation point, and + * - It does not modify the errno value. + * + * See comments with mq_timedreceive() for a more complete description of + * the behavior of this function + * + * Input Parameters: + * mq - Message Queue Descriptor + * msg - Buffer to receive the message + * msglen - Size of the buffer in bytes + * prio - If not NULL, the location to store message priority. + * abstime - the absolute time to wait until a timeout is declared. + * + * Returned Value: + * This is an internal OS interface and should not be used by applications. + * It follows the NuttX internal error return policy: Zero (OK) is + * returned on success. A negated errno value is returned on failure. + * (see mq_timedreceive() for the list list valid return values). + * + ****************************************************************************/ + +ssize_t file_mq_timedreceive(FAR struct file *mq, FAR char *msg, + size_t msglen, FAR unsigned int *prio, + FAR const struct timespec *abstime) +{ + return file_mq_timedreceive_internal(mq, msg, msglen, prio, abstime, 0); +} + +/**************************************************************************** + * Name: file_mq_tickreceive + * + * Description: + * This function receives the oldest of the highest priority messages from + * the message queue specified by "mq." If the message queue is empty + * and O_NONBLOCK was not set, file_mq_tickreceive() will block until a + * message is added to the message queue (or until a timeout occurs). + * + * file_mq_tickreceive() is an internal OS interface. It is functionally + * equivalent to mq_timedreceive() except that: + * + * - It is not a cancellation point, and + * - It does not modify the errno value. + * + * See comments with mq_timedreceive() for a more complete description of + * the behavior of this function + * + * Input Parameters: + * mq - Message Queue Descriptor + * msg - Buffer to receive the message + * msglen - Size of the buffer in bytes + * prio - If not NULL, the location to store message priority. + * ticks - Ticks to wait from the start time until the semaphore is + * posted. + * + * Returned Value: + * This is an internal OS interface and should not be used by applications. + * It follows the NuttX internal error return policy: Zero (OK) is + * returned on success. A negated errno value is returned on failure. + * (see mq_timedreceive() for the list list valid return values). + * + ****************************************************************************/ + +ssize_t file_mq_tickreceive(FAR struct file *mq, FAR char *msg, + size_t msglen, FAR unsigned int *prio, + sclock_t ticks) +{ + return file_mq_timedreceive_internal(mq, msg, msglen, prio, NULL, ticks); +} + /**************************************************************************** * Name: nxmq_timedreceive * @@ -284,7 +363,7 @@ ssize_t nxmq_timedreceive(mqd_t mqdes, FAR char *msg, size_t msglen, return ret; } - return file_mq_timedreceive(filep, msg, msglen, prio, abstime); + return file_mq_timedreceive_internal(filep, msg, msglen, prio, abstime, 0); } /**************************************************************************** diff --git a/sched/mqueue/mq_timedsend.c b/sched/mqueue/mq_timedsend.c index 8727043750a5d..abe0ab4705f0b 100644 --- a/sched/mqueue/mq_timedsend.c +++ b/sched/mqueue/mq_timedsend.c @@ -101,23 +101,11 @@ static void nxmq_sndtimeout(wdparm_t pid) ****************************************************************************/ /**************************************************************************** - * Name: file_mq_timedsend + * Name: file_mq_timedsend_internal * * Description: - * This function adds the specified message (msg) to the message queue - * (mq). file_mq_timedsend() behaves just like mq_send(), except that if - * the queue is full and the O_NONBLOCK flag is not enabled for the - * message queue description, then abstime points to a structure which - * specifies a ceiling on the time for which the call will block. - * - * file_mq_timedsend() is functionally equivalent to mq_timedsend() except - * that: - * - * - It is not a cancellation point, and - * - It does not modify the errno value. - * - * See comments with mq_timedsend() for a more complete description of the - * behavior of this function + * This is an internal function of file_mq_timedsend()/file_mq_ticksend(), + * please refer to the detailed description for more information. * * Input Parameters: * mq - Message queue descriptor @@ -125,6 +113,8 @@ static void nxmq_sndtimeout(wdparm_t pid) * msglen - The length of the message in bytes * prio - The priority of the message * abstime - the absolute time to wait until a timeout is decleared + * ticks - Ticks to wait from the start time until the semaphore is + * posted. * * Returned Value: * This is an internal OS interface and should not be used by applications. @@ -142,15 +132,16 @@ static void nxmq_sndtimeout(wdparm_t pid) * ****************************************************************************/ -int file_mq_timedsend(FAR struct file *mq, FAR const char *msg, - size_t msglen, unsigned int prio, - FAR const struct timespec *abstime) +static int +file_mq_timedsend_internal(FAR struct file *mq, FAR const char *msg, + size_t msglen, unsigned int prio, + FAR const struct timespec *abstime, + sclock_t ticks) { FAR struct tcb_s *rtcb = this_task(); FAR struct mqueue_inode_s *msgq; FAR struct mqueue_msg_s *mqmsg; irqstate_t flags; - sclock_t ticks; int ret; DEBUGASSERT(up_interrupt_context() == false); @@ -205,40 +196,46 @@ int file_mq_timedsend(FAR struct file *mq, FAR const char *msg, goto out_send_message; } - /* The message queue is full... We are going to wait. Now we must have a - * valid time value. + /* The message queue is full... We are going to wait. + * Now we must have a valid time value. */ - if (!abstime || abstime->tv_nsec < 0 || abstime->tv_nsec >= 1000000000) + if (abstime != NULL) { - ret = -EINVAL; - nxmq_free_msg(mqmsg); - goto errout_in_critical_section; + if (abstime->tv_nsec < 0 || abstime->tv_nsec >= 1000000000) + { + ret = -EINVAL; + } + else + { + /* We are not in an interrupt handler and the message queue + * is full. Set up a timed wait for the message queue to + * become non-full. + * + * Convert the timespec to clock ticks. We must have interrupts + * disabled here so that this time stays valid until the wait + * begins. + */ + + ret = clock_abstime2ticks(CLOCK_REALTIME, abstime, &ticks); + } + + /* Handle any time-related errors */ + + if (ret != OK) + { + nxmq_free_msg(mqmsg); + goto errout_in_critical_section; + } } - /* We are not in an interrupt handler and the message queue is full. - * Set up a timed wait for the message queue to become non-full. - * - * Convert the timespec to clock ticks. We must have interrupts - * disabled here so that this time stays valid until the wait begins. - */ - - ret = clock_abstime2ticks(CLOCK_REALTIME, abstime, &ticks); - /* If the time has already expired and the message queue is empty, * return immediately. */ - if (ret == OK && ticks <= 0) + if (ticks <= 0) { - ret = ETIMEDOUT; - } - - /* Handle any time-related errors */ - - if (ret != OK) - { - ret = -ret; + ret = -ETIMEDOUT; nxmq_free_msg(mqmsg); goto errout_in_critical_section; } @@ -271,6 +268,12 @@ int file_mq_timedsend(FAR struct file *mq, FAR const char *msg, out_send_message: ret = nxmq_do_send(msgq, mqmsg, msg, msglen, prio); } + else + { + /* free the message as it can't be sent */ + + nxmq_free_msg(mqmsg); + } /* Exit here with (1) the scheduler locked, (2) a message allocated, (3) a * wdog allocated, and (4) interrupts disabled. @@ -282,6 +285,104 @@ int file_mq_timedsend(FAR struct file *mq, FAR const char *msg, return ret; } +/**************************************************************************** + * Name: file_mq_timedsend + * + * Description: + * This function adds the specified message (msg) to the message queue + * (mq). file_mq_timedsend() behaves just like mq_send(), except that if + * the queue is full and the O_NONBLOCK flag is not enabled for the + * message queue description, then abstime points to a structure which + * specifies a ceiling on the time for which the call will block. + * + * file_mq_timedsend() is functionally equivalent to mq_timedsend() except + * that: + * + * - It is not a cancellation point, and + * - It does not modify the errno value. + * + * See comments with mq_timedsend() for a more complete description of the + * behavior of this function + * + * Input Parameters: + * mq - Message queue descriptor + * msg - Message to send + * msglen - The length of the message in bytes + * prio - The priority of the message + * abstime - the absolute time to wait until a timeout is decleared + * + * Returned Value: + * This is an internal OS interface and should not be used by applications. + * It follows the NuttX internal error return policy: Zero (OK) is + * returned on success. A negated errno value is returned on failure. + * (see mq_timedsend() for the list list valid return values). + * + * EAGAIN The queue was empty, and the O_NONBLOCK flag was set for the + * message queue description referred to by mq. + * EINVAL Either msg or mq is NULL or the value of prio is invalid. + * EBADF Message queue opened not opened for writing. + * EMSGSIZE 'msglen' was greater than the maxmsgsize attribute of the + * message queue. + * EINTR The call was interrupted by a signal handler. + * + ****************************************************************************/ + +int file_mq_timedsend(FAR struct file *mq, FAR const char *msg, + size_t msglen, unsigned int prio, + FAR const struct timespec *abstime) +{ + return file_mq_timedsend_internal(mq, msg, msglen, prio, abstime, 0); +} + +/**************************************************************************** + * Name: file_mq_ticksend + * + * Description: + * This function adds the specified message (msg) to the message queue + * (mq). file_mq_ticksend() behaves just like mq_send(), except that if + * the queue is full and the O_NONBLOCK flag is not enabled for the + * message queue description, then abstime points to a structure which + * specifies a ceiling on the time for which the call will block. + * + * file_mq_ticksend() is functionally equivalent to mq_timedsend() except + * that: + * + * - It is not a cancellation point, and + * - It does not modify the errno value. + * + * See comments with mq_timedsend() for a more complete description of the + * behavior of this function + * + * Input Parameters: + * mq - Message queue descriptor + * msg - Message to send + * msglen - The length of the message in bytes + * prio - The priority of the message + * ticks - Ticks to wait from the start time until the semaphore is + * posted. + * + * Returned Value: + * This is an internal OS interface and should not be used by applications. + * It follows the NuttX internal error return policy: Zero (OK) is + * returned on success. A negated errno value is returned on failure. + * (see mq_timedsend() for the list list valid return values). + * + * EAGAIN The queue was empty, and the O_NONBLOCK flag was set for the + * message queue description referred to by mq. + * EINVAL Either msg or mq is NULL or the value of prio is invalid. + * EBADF Message queue opened not opened for writing. + * EMSGSIZE 'msglen' was greater than the maxmsgsize attribute of the + * message queue. + * EINTR The call was interrupted by a signal handler. + * + ****************************************************************************/ + +int file_mq_ticksend(FAR struct file *mq, FAR const char *msg, + size_t msglen, unsigned int prio, sclock_t ticks) +{ + return file_mq_timedsend_internal(mq, msg, msglen, prio, NULL, ticks); +} + /**************************************************************************** * Name: nxmq_timedsend * @@ -336,7 +437,7 @@ int nxmq_timedsend(mqd_t mqdes, FAR const char *msg, size_t msglen, return ret; } - return file_mq_timedsend(filep, msg, msglen, prio, abstime); + return file_mq_timedsend_internal(filep, msg, msglen, prio, abstime, 0); } /**************************************************************************** diff --git a/sched/mqueue/msg.h b/sched/mqueue/msg.h index 273b9be1f02b6..7a1c52c1a0176 100644 --- a/sched/mqueue/msg.h +++ b/sched/mqueue/msg.h @@ -83,16 +83,6 @@ EXTERN struct list_node g_msgfreelist; * Public Function Prototypes ****************************************************************************/ -/**************************************************************************** - * Name: nxmsg_initialize - * - * Description: - * Initialize the message queue - * - ****************************************************************************/ - -void nxmsg_initialize(void); - /**************************************************************************** * Name: nxmsg_alloc * diff --git a/sched/mqueue/msginternal.c b/sched/mqueue/msginternal.c index 96e22cc2ee08e..712678fb3e742 100644 --- a/sched/mqueue/msginternal.c +++ b/sched/mqueue/msginternal.c @@ -42,7 +42,7 @@ static FAR struct msgq_s **g_msgqs; /* The pointer of two layer file descriptors * Public Data ****************************************************************************/ -struct list_node g_msgfreelist = LIST_INITIAL_VALUE(g_msgfreelist); +struct list_node g_msgfreelist; /**************************************************************************** * Private Functions @@ -99,26 +99,6 @@ static FAR struct msgq_s *nxmsg_alloc_internal(void) * Public Functions ****************************************************************************/ -/**************************************************************************** - * Name: nxmsg_initialize - ****************************************************************************/ - -void nxmsg_initialize(void) -{ - FAR struct msgbuf_s *msg; - - msg = kmm_malloc(sizeof(*msg) * CONFIG_PREALLOC_MQ_MSGS); - if (msg) - { - int i; - for (i = 0; i < CONFIG_PREALLOC_MQ_MSGS; i++) - { - list_add_tail(&g_msgfreelist, &msg->node); - msg++; - } - } -} - /**************************************************************************** * Name: nxmsg_alloc ****************************************************************************/ diff --git a/sched/paging/CMakeLists.txt b/sched/paging/CMakeLists.txt index 2130aaeb201f0..5504143b9d99d 100644 --- a/sched/paging/CMakeLists.txt +++ b/sched/paging/CMakeLists.txt @@ -18,7 +18,7 @@ # # ############################################################################## -if(CONFIG_PAGING) +if(CONFIG_LEGACY_PAGING) target_sources(sched PRIVATE pg_miss.c pg_worker.c) diff --git a/sched/paging/Make.defs b/sched/paging/Make.defs index f609926bb92e2..b717d1c25e008 100644 --- a/sched/paging/Make.defs +++ b/sched/paging/Make.defs @@ -18,7 +18,7 @@ # ############################################################################ -ifeq ($(CONFIG_PAGING),y) +ifeq ($(CONFIG_LEGACY_PAGING),y) CSRCS += pg_miss.c pg_worker.c diff --git a/sched/paging/paging.h b/sched/paging/paging.h index 948713d09e68f..84caa49b464f0 100644 --- a/sched/paging/paging.h +++ b/sched/paging/paging.h @@ -29,7 +29,7 @@ #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /**************************************************************************** * Pre-processor Definitions @@ -102,5 +102,5 @@ extern FAR struct tcb_s *g_pftcb; int pg_worker(int argc, FAR char *argv[]); #endif /* __ASSEMBLY__ */ -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ #endif /* __SCHED_PAGING_PAGING_H */ diff --git a/sched/paging/pg_miss.c b/sched/paging/pg_miss.c index f6c9260edfabe..8b10245bc9ef9 100644 --- a/sched/paging/pg_miss.c +++ b/sched/paging/pg_miss.c @@ -33,7 +33,7 @@ #include #include -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING #include "sched/sched.h" #include "paging/paging.h" @@ -143,7 +143,7 @@ void pg_miss(void) /* Add the task to the specified blocked task list */ ftcb->task_state = TSTATE_WAIT_PAGEFILL; - nxsched_add_prioritized(ftcb, &g_waitingforfill); + nxsched_add_prioritized(ftcb, list_waitingforfill()); /* Now, perform the context switch if one is needed */ @@ -183,4 +183,4 @@ void pg_miss(void) } } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/sched/paging/pg_worker.c b/sched/paging/pg_worker.c index 4e11d00f24101..b58da4848d803 100644 --- a/sched/paging/pg_worker.c +++ b/sched/paging/pg_worker.c @@ -42,7 +42,7 @@ #include "sched/sched.h" #include "paging/paging.h" -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING /**************************************************************************** * Public Data @@ -136,7 +136,8 @@ static void pg_callback(FAR struct tcb_s *tcb, int result) pginfo("g_pftcb: %p\n", g_pftcb); if (g_pftcb) { - FAR struct tcb_s *htcb = (FAR struct tcb_s *)g_waitingforfill.head; + FAR struct tcb_s *htcb = (FAR struct tcb_s *) + list_waitingforfill()->head; FAR struct tcb_s *wtcb = nxsched_get_tcb(g_pgworker); /* Find the higher priority between the task waiting for the fill to @@ -225,7 +226,7 @@ static inline bool pg_dequeue(void) { /* Remove the TCB from the head of the list (if any) */ - g_pftcb = (FAR struct tcb_s *)dq_remfirst(&g_waitingforfill); + g_pftcb = (FAR struct tcb_s *)dq_remfirst(list_waitingforfill()); pginfo("g_pftcb: %p\n", g_pftcb); if (g_pftcb != NULL) { @@ -693,4 +694,4 @@ int pg_worker(int argc, FAR char *argv[]) return OK; /* To keep some compilers happy */ } -#endif /* CONFIG_PAGING */ +#endif /* CONFIG_LEGACY_PAGING */ diff --git a/sched/pthread/CMakeLists.txt b/sched/pthread/CMakeLists.txt index 3e6675145b36f..2d30f32feec8d 100644 --- a/sched/pthread/CMakeLists.txt +++ b/sched/pthread/CMakeLists.txt @@ -38,7 +38,7 @@ if(NOT CONFIG_DISABLE_PTHREAD) pthread_condclockwait.c pthread_sigmask.c pthread_cancel.c - pthread_initialize.c + pthread_sem.c pthread_completejoin.c pthread_findjoininfo.c pthread_release.c diff --git a/sched/pthread/Make.defs b/sched/pthread/Make.defs index d8d7cb8928f2a..6911317c70e2d 100644 --- a/sched/pthread/Make.defs +++ b/sched/pthread/Make.defs @@ -26,7 +26,7 @@ CSRCS += pthread_mutexinit.c pthread_mutexdestroy.c CSRCS += pthread_mutextimedlock.c pthread_mutextrylock.c pthread_mutexunlock.c CSRCS += pthread_condwait.c pthread_condsignal.c pthread_condbroadcast.c CSRCS += pthread_condclockwait.c pthread_sigmask.c pthread_cancel.c -CSRCS += pthread_initialize.c pthread_completejoin.c pthread_findjoininfo.c +CSRCS += pthread_sem.c pthread_completejoin.c pthread_findjoininfo.c CSRCS += pthread_release.c pthread_setschedprio.c CSRCS += pthread_barrierwait.c diff --git a/sched/pthread/pthread.h b/sched/pthread/pthread.h index e53ad3e537d77..f4d04e8f5552b 100644 --- a/sched/pthread/pthread.h +++ b/sched/pthread/pthread.h @@ -36,29 +36,6 @@ #include #include -/**************************************************************************** - * Public Type Declarations - ****************************************************************************/ - -/* The following defines an entry in the pthread logic's local data set. - * Note that this structure is used to implemented a singly linked list. - * This structure is used (instead of, say, a binary search tree) because - * the data set will be searched using the pid as a key -- a process IDs will - * always be created in a montonically increasing fashion. - */ - -struct join_s -{ - FAR struct join_s *next; /* Implements link list */ - uint8_t crefs; /* Reference count */ - bool detached; /* true: pthread_detached'ed */ - bool terminated; /* true: detach'ed+exit'ed */ - pthread_t thread; /* Includes pid */ - sem_t exit_sem; /* Implements join */ - sem_t data_sem; /* Implements join */ - pthread_addr_t exit_value; /* Returned data */ -}; - /**************************************************************************** * Public Data ****************************************************************************/ @@ -83,9 +60,9 @@ int pthread_setup_scheduler(FAR struct pthread_tcb_s *tcb, int priority, int pthread_completejoin(pid_t pid, FAR void *exit_value); void pthread_destroyjoin(FAR struct task_group_s *group, - FAR struct join_s *pjoin); -int pthread_findjoininfo(FAR struct task_group_s *group, - pid_t pid, FAR struct join_s **join); + FAR struct task_join_s *pjoin); +int pthread_findjoininfo(FAR struct task_group_s *group, pid_t pid, + FAR struct task_join_s **join, bool create); void pthread_release(FAR struct task_group_s *group); int pthread_sem_take(FAR sem_t *sem, FAR const struct timespec *abs_timeout); diff --git a/sched/pthread/pthread_completejoin.c b/sched/pthread/pthread_completejoin.c index 42656c1705654..e7c60e0d8a5ef 100644 --- a/sched/pthread/pthread_completejoin.c +++ b/sched/pthread/pthread_completejoin.c @@ -24,6 +24,7 @@ #include +#include #include #include #include @@ -35,133 +36,6 @@ #include "group/group.h" #include "pthread/pthread.h" -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: pthread_notifywaiters - * - * Description: - * Notify all other threads waiting in phread join for this thread's - * exit data. This must be done by the child at child thread - * destruction time. - * - ****************************************************************************/ - -static bool pthread_notifywaiters(FAR struct join_s *pjoin) -{ - int ntasks_waiting; - int status; - - sinfo("pjoin=%p\n", pjoin); - - /* Are any tasks waiting for our exit value? */ - - status = nxsem_get_value(&pjoin->exit_sem, &ntasks_waiting); - if (status == OK && ntasks_waiting < 0) - { - /* Set the data semaphore so that this thread will be - * awakened when all waiting tasks receive the data - */ - - nxsem_init(&pjoin->data_sem, 0, (ntasks_waiting + 1)); - - /* Post the semaphore to restart each thread that is waiting - * on the semaphore - */ - - do - { - status = pthread_sem_give(&pjoin->exit_sem); - if (status == OK) - { - status = nxsem_get_value(&pjoin->exit_sem, &ntasks_waiting); - } - } - while (ntasks_waiting < 0 && status == OK); - - /* Now wait for all these restarted tasks to obtain the return - * value. - */ - - nxsem_wait_uninterruptible(&pjoin->data_sem); - return true; - } - - return false; -} - -/**************************************************************************** - * Name: pthread_removejoininfo - * - * Description: - * Remove a join structure from the local data set. - * - * Input Parameters: - * pid - * - * Returned Value: - * None. - * - * Assumptions: - * The caller has provided protection from re-entrancy. - * - ****************************************************************************/ - -static void pthread_removejoininfo(FAR struct task_group_s *group, - pid_t pid) -{ - FAR struct join_s *prev; - FAR struct join_s *join; - - /* Find the entry with the matching pid */ - - for (prev = NULL, join = group->tg_joinhead; - (join && (pid_t)join->thread != pid); - prev = join, join = join->next); - - /* Remove it from the data set. */ - - /* First check if this is the entry at the head of the list. */ - - if (join) - { - if (!prev) - { - /* Check if this is the only entry in the list */ - - if (!join->next) - { - group->tg_joinhead = NULL; - group->tg_jointail = NULL; - } - - /* Otherwise, remove it from the head of the list */ - - else - { - group->tg_joinhead = join->next; - } - } - - /* It is not at the head of the list, check if it is at the tail. */ - - else if (!join->next) - { - group->tg_jointail = prev; - prev->next = NULL; - } - - /* No, remove it from the middle of the list. */ - - else - { - prev->next = join->next; - } - } -} - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -189,59 +63,53 @@ static void pthread_removejoininfo(FAR struct task_group_s *group, int pthread_completejoin(pid_t pid, FAR void *exit_value) { FAR struct tcb_s *tcb = nxsched_get_tcb(pid); - FAR struct task_group_s *group = tcb ? tcb->group : NULL; - FAR struct join_s *pjoin; - int ret; + FAR struct task_group_s *group = tcb->group; + FAR struct task_join_s *join; + FAR struct tcb_s *wtcb; + FAR sq_entry_t *curr; + FAR sq_entry_t *next; + int ret = OK; - sinfo("pid=%d exit_value=%p group=%p\n", pid, exit_value, group); - DEBUGASSERT(group && tcb); + sinfo("pid=%d exit_value=%p\n", pid, exit_value); - /* First, find thread's structure in the private data set. */ + nxrmutex_lock(&group->tg_joinlock); - nxmutex_lock(&group->tg_joinlock); - ret = pthread_findjoininfo(group, pid, &pjoin); - if (ret != OK) + if (!sq_empty(&tcb->join_queue)) { - nxmutex_unlock(&group->tg_joinlock); + sq_for_every_safe(&tcb->join_queue, curr, next) + { + /* Remove join entry from queue */ - return ((tcb->flags & TCB_FLAG_DETACHED) || - (tcb->flags & TCB_FLAG_TTYPE_MASK) != TCB_FLAG_TTYPE_PTHREAD) ? - OK : ERROR; - } - else - { - FAR struct pthread_tcb_s *ptcb = (FAR struct pthread_tcb_s *)tcb; - bool waiters; + sq_rem(curr, &tcb->join_queue); - /* Save the return exit value in the thread structure. */ + /* Get tcb entry which waiting for the join */ - pjoin->terminated = true; - pjoin->exit_value = exit_value; - ptcb->join_complete = true; + wtcb = container_of(curr, struct tcb_s, join_entry); - /* Notify waiters of the availability of the exit value */ + /* Save the return exit value in the thread structure. */ - waiters = pthread_notifywaiters(pjoin); + wtcb->join_val = exit_value; - /* If there are no waiters and if the thread is marked as detached. - * then discard the join information now. Otherwise, the pthread - * join logic will call pthread_destroyjoin() when all of the threads - * have sampled the exit value. - */ + /* Notify waiters of the availability of the exit value */ - if (!waiters && pjoin->detached) + nxsem_post(&wtcb->join_sem); + } + } + else if (!sq_is_singular(&tcb->group->tg_members) && + (tcb->flags & TCB_FLAG_DETACHED) == 0) + { + ret = pthread_findjoininfo(tcb->group, pid, &join, true); + if (ret == OK) { - pthread_destroyjoin(group, pjoin); + join->exit_value = exit_value; } + } - /* Giving the following semaphore will allow the waiters - * to call pthread_destroyjoin. - */ + tcb->flags |= TCB_FLAG_JOIN_COMPLETED; - nxmutex_unlock(&group->tg_joinlock); - } + nxrmutex_unlock(&group->tg_joinlock); - return OK; + return ret; } /**************************************************************************** @@ -261,18 +129,15 @@ int pthread_completejoin(pid_t pid, FAR void *exit_value) ****************************************************************************/ void pthread_destroyjoin(FAR struct task_group_s *group, - FAR struct join_s *pjoin) + FAR struct task_join_s *pjoin) { sinfo("pjoin=%p\n", pjoin); /* Remove the join info from the set of joins */ - pthread_removejoininfo(group, (pid_t)pjoin->thread); - - /* Destroy its semaphores */ - - nxsem_destroy(&pjoin->data_sem); - nxsem_destroy(&pjoin->exit_sem); + nxrmutex_lock(&group->tg_joinlock); + sq_rem(&pjoin->entry, &group->tg_joinqueue); + nxrmutex_unlock(&group->tg_joinlock); /* And deallocate the pjoin structure */ diff --git a/sched/pthread/pthread_create.c b/sched/pthread/pthread_create.c index 87452cdc3afd8..1ba6c1b3ba8f1 100644 --- a/sched/pthread/pthread_create.c +++ b/sched/pthread/pthread_create.c @@ -40,6 +40,7 @@ #include #include +#include "task/task.h" #include "sched/sched.h" #include "group/group.h" #include "clock/clock.h" @@ -208,14 +209,19 @@ int nx_pthread_create(pthread_trampoline_t trampoline, FAR pthread_t *thread, /* Allocate a TCB for the new task. */ - ptcb = (FAR struct pthread_tcb_s *) - kmm_zalloc(sizeof(struct pthread_tcb_s)); + ptcb = kmm_zalloc(sizeof(struct pthread_tcb_s)); if (!ptcb) { serr("ERROR: Failed to allocate TCB\n"); return ENOMEM; } + ptcb->cmn.flags |= TCB_FLAG_FREE_TCB; + + /* Initialize the task join */ + + nxtask_joininit(&ptcb->cmn); + /* Bind the parent's group to the new TCB (we have not yet joined the * group). */ @@ -473,7 +479,7 @@ int nx_pthread_create(pthread_trampoline_t trampoline, FAR pthread_t *thread, else { sched_unlock(); - dq_rem((FAR dq_entry_t *)ptcb, &g_inactivetasks); + dq_rem((FAR dq_entry_t *)ptcb, list_inactivetasks()); errcode = EIO; goto errout_with_tcb; diff --git a/sched/pthread/pthread_detach.c b/sched/pthread/pthread_detach.c index f1476515ff613..9eac0625dedeb 100644 --- a/sched/pthread/pthread_detach.c +++ b/sched/pthread/pthread_detach.c @@ -64,45 +64,43 @@ int pthread_detach(pthread_t thread) { FAR struct tcb_s *rtcb = this_task(); FAR struct task_group_s *group = rtcb->group; - FAR struct join_s *pjoin; + FAR struct task_join_s *join; + FAR struct tcb_s *tcb; int ret; - sinfo("Thread=%d group=%p\n", thread, group); - DEBUGASSERT(group); + nxrmutex_lock(&group->tg_joinlock); - /* Find the entry associated with this pthread. */ - - nxmutex_lock(&group->tg_joinlock); - ret = pthread_findjoininfo(group, (pid_t)thread, &pjoin); - if (ret == OK) + tcb = nxsched_get_tcb((pid_t)thread); + if (tcb == NULL || (tcb->flags & TCB_FLAG_JOIN_COMPLETED) != 0) { - /* Has the thread already terminated? */ + /* Destroy the join information */ - if (pjoin->terminated) + ret = pthread_findjoininfo(group, (pid_t)thread, &join, false); + if (ret == OK) { - /* YES.. just remove the thread entry. */ - - pthread_destroyjoin(group, pjoin); + pthread_destroyjoin(group, join); } else { - /* NO.. Just mark the thread as detached. It - * will be removed and deallocated when the - * thread exits - */ - - if (pjoin->detached) - { - ret = EINVAL; - } - else - { - pjoin->detached = true; - } + ret = ESRCH; } + + goto errout; + } + + if ((group != tcb->group) || + (tcb->flags & TCB_FLAG_DETACHED) != 0) + { + ret = EINVAL; + } + else + { + tcb->flags |= TCB_FLAG_DETACHED; + ret = OK; } - nxmutex_unlock(&group->tg_joinlock); +errout: + nxrmutex_unlock(&group->tg_joinlock); sinfo("Returning %d\n", ret); return ret; diff --git a/sched/pthread/pthread_findjoininfo.c b/sched/pthread/pthread_findjoininfo.c index 5250e55b43ded..4e9511b58e65a 100644 --- a/sched/pthread/pthread_findjoininfo.c +++ b/sched/pthread/pthread_findjoininfo.c @@ -28,6 +28,8 @@ #include #include +#include + #include "group/group.h" #include "pthread/pthread.h" @@ -35,71 +37,6 @@ * Private Functions ****************************************************************************/ -/**************************************************************************** - * Name: pthread_createjoininfo - * - * Description: - * Allocate a detachable structure to support pthread_join logic and add - * the joininfo to the thread. - * - * Input Parameters: - * ptcb - * - * Output Parameters: - * pjoin - joininfo point - * - * Returned Value: - * 0 if successful. - * - * Assumptions: - * - ****************************************************************************/ - -int pthread_createjoininfo(FAR struct pthread_tcb_s *ptcb, - FAR struct join_s **pjoin) -{ - /* Allocate a detachable structure to support pthread_join logic */ - - *pjoin = kmm_zalloc(sizeof(struct join_s)); - if (*pjoin == NULL) - { - serr("ERROR: Failed to allocate join\n"); - return EINVAL; - } - - (*pjoin)->thread = (pthread_t)ptcb->cmn.pid; - - /* Initialize the semaphore in the join structure to zero. */ - - if (nxsem_init(&(*pjoin)->exit_sem, 0, 0) < 0) - { - kmm_free(*pjoin); - return EINVAL; - } - else - { - FAR struct task_group_s *group = ptcb->cmn.group; - - /* Attach the join info to the TCB. */ - - ptcb->joininfo = (FAR void *)(*pjoin); - - (*pjoin)->next = NULL; - if (!group->tg_jointail) - { - group->tg_joinhead = *pjoin; - } - else - { - group->tg_jointail->next = *pjoin; - } - - group->tg_jointail = *pjoin; - } - - return OK; -} - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -130,55 +67,48 @@ int pthread_createjoininfo(FAR struct pthread_tcb_s *ptcb, * ****************************************************************************/ -int pthread_findjoininfo(FAR struct task_group_s *group, - pid_t pid, FAR struct join_s **pjoin) +int pthread_findjoininfo(FAR struct task_group_s *group, pid_t pid, + FAR struct task_join_s **pjoin, bool create) { - FAR struct pthread_tcb_s *ptcb; - FAR struct tcb_s *tcb; + FAR struct task_join_s *join; + FAR sq_entry_t *curr; + FAR sq_entry_t *next; - DEBUGASSERT(group); + nxrmutex_lock(&group->tg_joinlock); - /* Find the entry with the matching pid */ - - for (*pjoin = group->tg_joinhead; - (*pjoin && (pid_t)(*pjoin)->thread != pid); - *pjoin = (*pjoin)->next); - - /* and return it */ - - if (*pjoin) + sq_for_every_safe(&group->tg_joinqueue, curr, next) { - return OK; + join = container_of(curr, struct task_join_s, entry); + + if (join->pid == pid) + { + goto found; + } } - /* Task has been deleted, return ESRCH */ + nxrmutex_unlock(&group->tg_joinlock); - tcb = nxsched_get_tcb(pid); - if (tcb == NULL) + if (!create) { - return ESRCH; + return EINVAL; } - /* Task was detached or not a pthread, return EINVAL */ - - if ((tcb->flags & TCB_FLAG_DETACHED) != 0 || - (tcb->flags & TCB_FLAG_TTYPE_MASK) != TCB_FLAG_TTYPE_PTHREAD) + join = kmm_zalloc(sizeof(struct task_join_s)); + if (join == NULL) { - return EINVAL; + return ENOMEM; } - ptcb = (FAR struct pthread_tcb_s *)tcb; + join->pid = pid; - /* Task was join completed, is in the process - * of being deleted, return ESRCH - */ + nxrmutex_lock(&group->tg_joinlock); - if (ptcb->join_complete) - { - return ESRCH; - } + sq_addfirst(&join->entry, &group->tg_joinqueue); + +found: + nxrmutex_unlock(&group->tg_joinlock); - /* Else create joininfo for the task */ + *pjoin = join; - return pthread_createjoininfo(ptcb, pjoin); + return OK; } diff --git a/sched/pthread/pthread_initialize.c b/sched/pthread/pthread_initialize.c deleted file mode 100644 index acb0964b9f594..0000000000000 --- a/sched/pthread/pthread_initialize.c +++ /dev/null @@ -1,122 +0,0 @@ -/**************************************************************************** - * sched/pthread/pthread_initialize.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include - -#include "pthread/pthread.h" - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: pthread_sem_take, pthread_sem_trytake, and - * pthread_sem_give - * - * Description: - * Support managed access to the private data sets. - * - * REVISIT: These functions really do nothing more than match the return - * value of the semaphore functions (0 or -1 with errno set) to the - * return value of more pthread functions (0 or errno). A better solution - * would be to use an internal version of the semaphore functions that - * return the error value in the correct form. - * - * Input Parameters: - * sem - The semaphore to lock or unlock - * - * Returned Value: - * 0 on success or an errno value on failure. - * - ****************************************************************************/ - -int pthread_sem_take(FAR sem_t *sem, FAR const struct timespec *abs_timeout) -{ - int ret; - - if (abs_timeout == NULL) - { - ret = nxsem_wait_uninterruptible(sem); - } - else - { - ret = nxsem_timedwait_uninterruptible(sem, abs_timeout); - } - - return -ret; -} - -#ifdef CONFIG_PTHREAD_MUTEX_UNSAFE -int pthread_sem_trytake(FAR sem_t *sem) -{ - int ret = EINVAL; - - /* Verify input parameters */ - - DEBUGASSERT(sem != NULL); - if (sem != NULL) - { - /* Try to take the semaphore */ - - int status = nxsem_trywait(sem); - ret = status < 0 ? -status : OK; - } - - return ret; -} -#endif - -int pthread_sem_give(FAR sem_t *sem) -{ - int ret; - - /* Verify input parameters */ - - DEBUGASSERT(sem != NULL); - if (sem != NULL) - { - /* Give the semaphore */ - - ret = nxsem_post(sem); - if (ret < 0) - { - return -ret; - } - - return OK; - } - else - { - /* NULL semaphore pointer! */ - - return EINVAL; - } -} diff --git a/sched/pthread/pthread_join.c b/sched/pthread/pthread_join.c index 9c27cde9aa9cc..5c39b4a44e75c 100644 --- a/sched/pthread/pthread_join.c +++ b/sched/pthread/pthread_join.c @@ -34,7 +34,6 @@ #include #include "sched/sched.h" -#include "group/group.h" #include "pthread/pthread.h" /**************************************************************************** @@ -74,153 +73,99 @@ int pthread_join(pthread_t thread, FAR pthread_addr_t *pexit_value) { FAR struct tcb_s *rtcb = this_task(); FAR struct task_group_s *group = rtcb->group; - FAR struct join_s *pjoin; - int ret; - - sinfo("thread=%d group=%p\n", thread, group); - DEBUGASSERT(group); + FAR struct task_join_s *join; + FAR struct tcb_s *tcb; + int ret = OK; /* pthread_join() is a cancellation point */ enter_cancellation_point(); - /* First make sure that this is not an attempt to join to - * ourself. - */ - - if ((pid_t)thread == nxsched_gettid()) - { - leave_cancellation_point(); - return EDEADLK; - } - - /* Make sure no other task is mucking with the data structures - * while we are performing the following operations. NOTE: - * we can be also sure that pthread_exit() will not execute - * because it will also attempt to get this semaphore. - */ - - nxmutex_lock(&group->tg_joinlock); - - /* Find the join information associated with this thread. - * This can fail for one of three reasons: (1) There is no - * thread associated with 'thread,' (2) the thread is a task - * and does not have join information, or (3) the thread - * was detached and has exited. - */ + nxrmutex_lock(&group->tg_joinlock); - ret = pthread_findjoininfo(group, (pid_t)thread, &pjoin); - if (ret == OK) + tcb = nxsched_get_tcb((pid_t)thread); + if (tcb == NULL || (tcb->flags & TCB_FLAG_JOIN_COMPLETED) != 0) { - if (pjoin->detached) + ret = pthread_findjoininfo(group, (pid_t)thread, &join, false); + if (ret == OK) { - nxmutex_unlock(&group->tg_joinlock); - leave_cancellation_point(); - return EINVAL; - } - - /* NOTE: sched_lock() is not enough for SMP - * because another CPU would continue the pthread and exit - * sequences so need to protect it with a critical section - */ - -#ifdef CONFIG_SMP - irqstate_t flags = enter_critical_section(); -#endif - - /* We found the join info structure. Increment for the reference - * to the join structure that we have. This will keep things - * stable for we have to do - */ - - sched_lock(); - pjoin->crefs++; - - /* Check if the thread is still running. If not, then things are - * simpler. There are still race conditions to be concerned with. - * For example, there could be multiple threads executing in the - * 'else' block below when we enter! - */ + /* Destroy the join information after obtain the exit value */ - if (pjoin->terminated) - { - sinfo("Thread has terminated\n"); - - /* Get the thread exit value from the terminated thread. */ - - if (pexit_value) + if (pexit_value != NULL) { - sinfo("exit_value=%p\n", pjoin->exit_value); - *pexit_value = pjoin->exit_value; + *pexit_value = join->exit_value; } + + pthread_destroyjoin(group, join); } else { - sinfo("Thread is still running\n"); + ret = ESRCH; + } - /* Relinquish the data set semaphore. Since pre-emption is - * disabled, we can be certain that no task has the - * opportunity to run between the time we relinquish the - * join semaphore and the time that we wait on the thread exit - * semaphore. - */ + goto errout; + } - nxmutex_unlock(&group->tg_joinlock); + /* First make sure that this is not an attempt to join to + * ourself. + */ - /* Take the thread's thread exit semaphore. We will sleep here - * until the thread exits. We need to exercise caution because - * there could be multiple threads waiting here for the same - * pthread to exit. - */ + if (tcb == rtcb) + { + ret = EDEADLK; + goto errout; + } - nxsem_wait_uninterruptible(&pjoin->exit_sem); + /* Task was detached or not a pthread, return EINVAL */ - /* The thread has exited! Get the thread exit value */ + if ((tcb->group != group) || + (tcb->flags & TCB_FLAG_DETACHED) != 0) + { + ret = EINVAL; + goto errout; + } - if (pexit_value) - { - *pexit_value = pjoin->exit_value; - sinfo("exit_value=%p\n", pjoin->exit_value); - } + /* Relinquish the data set semaphore. Since pre-emption is + * disabled, we can be certain that no task has the + * opportunity to run between the time we relinquish the + * join semaphore and the time that we wait on the thread exit + * semaphore. + */ - /* Post the thread's data semaphore so that the exiting thread - * will know that we have received the data. - */ + sq_addfirst(&rtcb->join_entry, &tcb->join_queue); - pthread_sem_give(&pjoin->data_sem); + nxrmutex_unlock(&group->tg_joinlock); - /* Retake the join semaphore, we need to hold this when - * pthread_destroyjoin is called. - */ + /* Take the thread's thread exit semaphore. We will sleep here + * until the thread exits. We need to exercise caution because + * there could be multiple threads waiting here for the same + * pthread to exit. + */ - nxmutex_lock(&group->tg_joinlock); - } + nxsem_wait_uninterruptible(&rtcb->join_sem); - /* Pre-emption is okay now. The logic still cannot be re-entered - * because we hold the join semaphore - */ + nxrmutex_lock(&group->tg_joinlock); - sched_unlock(); + /* The thread has exited! Get the thread exit value */ -#ifdef CONFIG_SMP - leave_critical_section(flags); -#endif + if (pexit_value != NULL) + { + *pexit_value = rtcb->join_val; + } - /* Release our reference to the join structure and, if the reference - * count decrements to zero, deallocate the join structure. - */ +errout: + nxrmutex_unlock(&group->tg_joinlock); - if (--pjoin->crefs <= 0) - { - pthread_destroyjoin(group, pjoin); - } + leave_cancellation_point(); - ret = OK; + if (pexit_value) + { + sinfo("Returning %d, exit_value %p\n", ret, *pexit_value); + } + else + { + sinfo("Returning %d\n", ret); } - nxmutex_unlock(&group->tg_joinlock); - - leave_cancellation_point(); - sinfo("Returning %d\n", ret); return ret; } diff --git a/sched/pthread/pthread_release.c b/sched/pthread/pthread_release.c index c4186177cf99b..9693dc4c82cde 100644 --- a/sched/pthread/pthread_release.c +++ b/sched/pthread/pthread_release.c @@ -28,6 +28,7 @@ #include #include +#include #include #include "pthread/pthread.h" @@ -58,32 +59,22 @@ void pthread_release(FAR struct task_group_s *group) { - FAR struct join_s *join; - DEBUGASSERT(group); + FAR sq_entry_t *curr; + FAR sq_entry_t *next; /* Visit and delete each join structure still in the list. Since we * are last exiting thread of the group, no special protection should * be required. */ - while (group->tg_joinhead) + sq_for_every_safe(&group->tg_joinqueue, curr, next) { - /* Remove the join from the head of the list. */ + /* Deallocate the join structure */ - join = group->tg_joinhead; - group->tg_joinhead = join->next; - - /* Destroy the join semaphores */ - - nxsem_destroy(&join->data_sem); - nxsem_destroy(&join->exit_sem); - - /* And deallocate the join structure */ - - kmm_free(join); + kmm_free(container_of(curr, struct task_join_s, entry)); } /* Destroy the join list mutex */ - nxmutex_destroy(&group->tg_joinlock); + nxrmutex_destroy(&group->tg_joinlock); } diff --git a/sched/pthread/pthread_sem.c b/sched/pthread/pthread_sem.c new file mode 100644 index 0000000000000..7d3dc3d14065a --- /dev/null +++ b/sched/pthread/pthread_sem.c @@ -0,0 +1,122 @@ +/**************************************************************************** + * sched/pthread/pthread_sem.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#include "pthread/pthread.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: pthread_sem_take, pthread_sem_trytake, and + * pthread_sem_give + * + * Description: + * Support managed access to the private data sets. + * + * REVISIT: These functions really do nothing more than match the return + * value of the semaphore functions (0 or -1 with errno set) to the + * return value of more pthread functions (0 or errno). A better solution + * would be to use an internal version of the semaphore functions that + * return the error value in the correct form. + * + * Input Parameters: + * sem - The semaphore to lock or unlock + * + * Returned Value: + * 0 on success or an errno value on failure. + * + ****************************************************************************/ + +int pthread_sem_take(FAR sem_t *sem, FAR const struct timespec *abs_timeout) +{ + int ret; + + if (abs_timeout == NULL) + { + ret = nxsem_wait_uninterruptible(sem); + } + else + { + ret = nxsem_timedwait_uninterruptible(sem, abs_timeout); + } + + return -ret; +} + +#ifdef CONFIG_PTHREAD_MUTEX_UNSAFE +int pthread_sem_trytake(FAR sem_t *sem) +{ + int ret = EINVAL; + + /* Verify input parameters */ + + DEBUGASSERT(sem != NULL); + if (sem != NULL) + { + /* Try to take the semaphore */ + + int status = nxsem_trywait(sem); + ret = status < 0 ? -status : OK; + } + + return ret; +} +#endif + +int pthread_sem_give(FAR sem_t *sem) +{ + int ret; + + /* Verify input parameters */ + + DEBUGASSERT(sem != NULL); + if (sem != NULL) + { + /* Give the semaphore */ + + ret = nxsem_post(sem); + if (ret < 0) + { + return -ret; + } + + return OK; + } + else + { + /* NULL semaphore pointer! */ + + return EINVAL; + } +} diff --git a/sched/sched/CMakeLists.txt b/sched/sched/CMakeLists.txt index 29ac1b6346016..998c82f0c32ff 100644 --- a/sched/sched/CMakeLists.txt +++ b/sched/sched/CMakeLists.txt @@ -120,6 +120,10 @@ if(CONFIG_SCHED_BACKTRACE) list(APPEND SRCS sched_backtrace.c) endif() +if(CONFIG_DUMP_ON_EXIT) + list(APPEND SRCS sched_dumponexit.c) +endif() + if(CONFIG_SMP_CALL) list(APPEND SRCS sched_smp.c) endif() diff --git a/sched/sched/Make.defs b/sched/sched/Make.defs index 422f010738077..2ff311780e467 100644 --- a/sched/sched/Make.defs +++ b/sched/sched/Make.defs @@ -96,6 +96,10 @@ ifeq ($(CONFIG_SCHED_BACKTRACE),y) CSRCS += sched_backtrace.c endif +ifeq ($(CONFIG_DUMP_ON_EXIT),y) +CSRCS += sched_dumponexit.c +endif + ifeq ($(CONFIG_SMP_CALL),y) CSRCS += sched_smp.c endif diff --git a/sched/sched/sched.h b/sched/sched/sched.h index ceefc2b8c2e88..49faca75df4ac 100644 --- a/sched/sched/sched.h +++ b/sched/sched/sched.h @@ -42,18 +42,32 @@ #define PIDHASH(pid) ((pid) & (g_npidhash - 1)) +/* The state of a task is indicated both by the task_state field of the TCB + * and by a series of task lists. All of these tasks lists are declared + * below. Although it is not always necessary, most of these lists are + * prioritized so that common list handling logic can be used (only the + * g_readytorun, the g_pendingtasks, and the g_waitingforsemaphore lists + * need to be prioritized). + */ + +#define list_readytorun() (&g_readytorun) +#define list_pendingtasks() (&g_pendingtasks) +#define list_waitingforsignal() (&g_waitingforsignal) +#define list_waitingforfill() (&g_waitingforfill) +#define list_stoppedtasks() (&g_stoppedtasks) +#define list_inactivetasks() (&g_inactivetasks) +#define list_assignedtasks(cpu) (&g_assignedtasks[cpu]) + /* These are macros to access the current CPU and the current task on a CPU. * These macros are intended to support a future SMP implementation. * NOTE: this_task() for SMP is implemented in sched_thistask.c */ #ifdef CONFIG_SMP -# define current_task(cpu) ((FAR struct tcb_s *)g_assignedtasks[cpu].head) -# define this_cpu() up_cpu_index() +# define current_task(cpu) ((FAR struct tcb_s *)list_assignedtasks(cpu)->head) #else -# define current_task(cpu) ((FAR struct tcb_s *)g_readytorun.head) -# define this_cpu() (0) -# define this_task() (current_task(this_cpu())) +# define current_task(cpu) ((FAR struct tcb_s *)list_readytorun()->head) +# define this_task() (current_task(up_cpu_index())) #endif #define is_idle_task(t) ((t)->pid < CONFIG_SMP_NCPUS) @@ -63,7 +77,7 @@ */ #define running_task() \ - (up_interrupt_context() ? g_running_tasks[this_cpu()] : this_task()) + (up_interrupt_context() ? g_running_tasks[up_cpu_index()] : this_task()) /* List attribute flags */ @@ -103,6 +117,10 @@ # define CRITMONITOR_PANIC(fmt, ...) _alert(fmt, ##__VA_ARGS__) #endif +#define nxsched_pidhash() g_pidhash +#define nxsched_npidhash() g_npidhash +#define nxsched_lastpid() g_lastpid + /**************************************************************************** * Public Type Definitions ****************************************************************************/ @@ -194,7 +212,7 @@ extern dq_queue_t g_waitingforsignal; /* This is the list of all tasks that are blocking waiting for a page fill */ -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING extern dq_queue_t g_waitingforfill; #endif @@ -233,14 +251,14 @@ extern volatile int g_npidhash; * ordered list or not. */ -extern const struct tasklist_s g_tasklisttable[NUM_TASK_STATES]; +extern struct tasklist_s g_tasklisttable[NUM_TASK_STATES]; #ifndef CONFIG_SCHED_CPULOAD_NONE /* This is the total number of clock tick counts. Essentially the * 'denominator' for all CPU load calculations. */ -extern volatile uint32_t g_cpuload_total; +extern volatile clock_t g_cpuload_total; #endif /* Declared in sched_lock.c *************************************************/ @@ -399,8 +417,8 @@ int nxsched_pause_cpu(FAR struct tcb_s *tcb); #if defined(CONFIG_SCHED_CPULOAD_SYSCLK) || \ defined (CONFIG_SCHED_CPULOAD_CRITMONITOR) -void nxsched_process_taskload_ticks(FAR struct tcb_s *tcb, uint32_t ticks); -void nxsched_process_cpuload_ticks(uint32_t ticks); +void nxsched_process_taskload_ticks(FAR struct tcb_s *tcb, clock_t ticks); +void nxsched_process_cpuload_ticks(clock_t ticks); #define nxsched_process_cpuload() nxsched_process_cpuload_ticks(1) #endif diff --git a/sched/sched/sched_addreadytorun.c b/sched/sched/sched_addreadytorun.c index a4434423e0f76..25acc1087018c 100644 --- a/sched/sched/sched_addreadytorun.c +++ b/sched/sched/sched_addreadytorun.c @@ -82,14 +82,14 @@ bool nxsched_add_readytorun(FAR struct tcb_s *btcb) * g_pendingtasks task list for now. */ - nxsched_add_prioritized(btcb, &g_pendingtasks); + nxsched_add_prioritized(btcb, list_pendingtasks()); btcb->task_state = TSTATE_TASK_PENDING; ret = false; } /* Otherwise, add the new task to the ready-to-run task list */ - else if (nxsched_add_prioritized(btcb, &g_readytorun)) + else if (nxsched_add_prioritized(btcb, list_readytorun())) { /* The new btcb was added at the head of the ready-to-run list. It * is now the new active task! @@ -153,7 +153,6 @@ bool nxsched_add_readytorun(FAR struct tcb_s *btcb) { FAR struct tcb_s *rtcb; FAR dq_queue_t *tasklist; - bool switched; bool doswitch; int task_state; int cpu; @@ -165,6 +164,7 @@ bool nxsched_add_readytorun(FAR struct tcb_s *btcb) { /* Yes.. that is the CPU we must use */ + task_state = TSTATE_TASK_ASSIGNED; cpu = btcb->cpu; } else @@ -173,6 +173,7 @@ bool nxsched_add_readytorun(FAR struct tcb_s *btcb) * (possibly its IDLE task). */ + task_state = TSTATE_TASK_READYTORUN; cpu = nxsched_select_cpu(btcb->affinity); } @@ -191,24 +192,6 @@ bool nxsched_add_readytorun(FAR struct tcb_s *btcb) task_state = TSTATE_TASK_RUNNING; } - /* If it will not be running, but is locked to a CPU, then it will be in - * the assigned state. - */ - - else if ((btcb->flags & TCB_FLAG_CPU_LOCKED) != 0) - { - task_state = TSTATE_TASK_ASSIGNED; - cpu = btcb->cpu; - } - - /* Otherwise, it will be ready-to-run, but not not yet running */ - - else - { - task_state = TSTATE_TASK_READYTORUN; - cpu = 0; /* CPU does not matter */ - } - /* If the selected state is TSTATE_TASK_RUNNING, then we would like to * start running the task. Be we cannot do that if pre-emption is * disabled. If the selected state is TSTATE_TASK_READYTORUN, then it @@ -223,14 +206,14 @@ bool nxsched_add_readytorun(FAR struct tcb_s *btcb) */ me = this_cpu(); - if ((nxsched_islocked_global() || irq_cpu_locked(me)) && + if ((nxsched_islocked_global()) && task_state != TSTATE_TASK_ASSIGNED) { /* Add the new ready-to-run task to the g_pendingtasks task list for * now. */ - nxsched_add_prioritized(btcb, &g_pendingtasks); + nxsched_add_prioritized(btcb, list_pendingtasks()); btcb->task_state = TSTATE_TASK_PENDING; doswitch = false; } @@ -244,7 +227,7 @@ bool nxsched_add_readytorun(FAR struct tcb_s *btcb) * Add the task to the ready-to-run (but not running) task list */ - nxsched_add_prioritized(btcb, &g_readytorun); + nxsched_add_prioritized(btcb, list_readytorun()); btcb->task_state = TSTATE_TASK_READYTORUN; doswitch = false; @@ -264,15 +247,15 @@ bool nxsched_add_readytorun(FAR struct tcb_s *btcb) * and check if a context switch will occur */ - tasklist = &g_assignedtasks[cpu]; - switched = nxsched_add_prioritized(btcb, tasklist); + tasklist = list_assignedtasks(cpu); + doswitch = nxsched_add_prioritized(btcb, tasklist); /* If the selected task list was the g_assignedtasks[] list and if the * new tasks is the highest priority (RUNNING) task, then a context * switch will occur. */ - if (switched) + if (doswitch) { FAR struct tcb_s *next; @@ -338,18 +321,16 @@ bool nxsched_add_readytorun(FAR struct tcb_s *btcb) if (nxsched_islocked_global()) { next->task_state = TSTATE_TASK_PENDING; - tasklist = &g_pendingtasks; + tasklist = list_pendingtasks(); } else { next->task_state = TSTATE_TASK_READYTORUN; - tasklist = &g_readytorun; + tasklist = list_readytorun(); } nxsched_add_prioritized(next, tasklist); } - - doswitch = true; } else { @@ -366,6 +347,7 @@ bool nxsched_add_readytorun(FAR struct tcb_s *btcb) btcb->cpu = cpu; btcb->task_state = TSTATE_TASK_ASSIGNED; + doswitch = false; } /* All done, restart the other CPU (if it was paused). */ diff --git a/sched/sched/sched_cpuload.c b/sched/sched/sched_cpuload.c index 59cd5d88c2397..1eb7cb8906d8a 100644 --- a/sched/sched/sched_cpuload.c +++ b/sched/sched/sched_cpuload.c @@ -76,7 +76,7 @@ * each would have a load of 25% of the total. */ -volatile uint32_t g_cpuload_total; +volatile clock_t g_cpuload_total; /**************************************************************************** * Public Functions @@ -97,12 +97,8 @@ volatile uint32_t g_cpuload_total; * ****************************************************************************/ -void nxsched_process_taskload_ticks(FAR struct tcb_s *tcb, uint32_t ticks) +void nxsched_process_taskload_ticks(FAR struct tcb_s *tcb, clock_t ticks) { - irqstate_t flags; - - flags = enter_critical_section(); - tcb->ticks += ticks; g_cpuload_total += ticks; @@ -115,12 +111,12 @@ void nxsched_process_taskload_ticks(FAR struct tcb_s *tcb, uint32_t ticks) * total. */ - for (i = 0; i < g_npidhash; i++) + for (i = 0; i < nxsched_npidhash(); i++) { - if (g_pidhash[i]) + if (nxsched_pidhash()[i]) { - g_pidhash[i]->ticks >>= 1; - total += g_pidhash[i]->ticks; + nxsched_pidhash()[i]->ticks >>= 1; + total += nxsched_pidhash()[i]->ticks; } } @@ -128,8 +124,6 @@ void nxsched_process_taskload_ticks(FAR struct tcb_s *tcb, uint32_t ticks) g_cpuload_total = total; } - - leave_critical_section(flags); } /**************************************************************************** @@ -153,7 +147,7 @@ void nxsched_process_taskload_ticks(FAR struct tcb_s *tcb, uint32_t ticks) * ****************************************************************************/ -void nxsched_process_cpuload_ticks(uint32_t ticks) +void nxsched_process_cpuload_ticks(clock_t ticks) { int i; @@ -215,10 +209,11 @@ int clock_cpuload(int pid, FAR struct cpuload_s *cpuload) * do this too, but this would require a little more overhead. */ - if (g_pidhash[hash_index] && g_pidhash[hash_index]->pid == pid) + if (nxsched_pidhash()[hash_index] && + nxsched_pidhash()[hash_index]->pid == pid) { cpuload->total = g_cpuload_total; - cpuload->active = g_pidhash[hash_index]->ticks; + cpuload->active = nxsched_pidhash()[hash_index]->ticks; ret = OK; } diff --git a/sched/sched/sched_cpuselect.c b/sched/sched/sched_cpuselect.c index a225afaa15576..1d49750cd32bb 100644 --- a/sched/sched/sched_cpuselect.c +++ b/sched/sched/sched_cpuselect.c @@ -77,7 +77,7 @@ int nxsched_select_cpu(cpu_set_t affinity) if ((affinity & (1 << i)) != 0) { FAR struct tcb_s *rtcb = (FAR struct tcb_s *) - g_assignedtasks[i].head; + list_assignedtasks(i)->head; /* If this CPU is executing its IDLE task, then use it. The * IDLE task is always the last task in the assigned task list. diff --git a/sched/sched/sched_dumponexit.c b/sched/sched/sched_dumponexit.c new file mode 100644 index 0000000000000..f1a07bd946aa4 --- /dev/null +++ b/sched/sched/sched_dumponexit.c @@ -0,0 +1,97 @@ +/**************************************************************************** + * sched/sched/sched_dumponexit.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_DUMP_ON_EXIT + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: dumphandler + * + * Description: + * Dump the state of all tasks whenever on task exits. This is debug + * instrumentation that was added to check file-related reference counting + * but could be useful again sometime in the future. + * + ****************************************************************************/ + +static void dumphandler(FAR struct tcb_s *tcb, FAR void *arg) +{ + FAR struct filelist *filelist; + int i; + int j; + + sinfo(" TCB=%p name=%s\n", tcb, tcb->name); + sinfo(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state); + + filelist = &tcb->group->tg_filelist; + for (i = 0; i < filelist->fl_rows; i++) + { + for (j = 0; j < CONFIG_NFILE_DESCRIPTORS_PER_BLOCK; j++) + { + struct inode *inode = filelist->fl_files[i][j].f_inode; + if (inode) + { + sinfo(" fd=%d refcount=%d\n", + i * CONFIG_NFILE_DESCRIPTORS_PER_BLOCK + j, + inode->i_crefs); + } + } + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nxsched_dumponexit + * + * Description: + * Dump the state of all tasks whenever on task exits. This is debug + * instrumentation that was added to check file-related reference counting + * but could be useful again sometime in the future. + * + ****************************************************************************/ + +void nxsched_dumponexit(void) +{ + sinfo("Other tasks:\n"); + nxsched_foreach(dumphandler, NULL); +} + +#endif /* CONFIG_DUMP_ON_EXIT */ diff --git a/sched/sched/sched_foreach.c b/sched/sched/sched_foreach.c index ed69e979ecef7..5b54b2bb99596 100644 --- a/sched/sched/sched_foreach.c +++ b/sched/sched/sched_foreach.c @@ -64,13 +64,13 @@ void nxsched_foreach(nxsched_foreach_t handler, FAR void *arg) flags = enter_critical_section(); sched_lock(); - for (ndx = 0; ndx < g_npidhash; ndx++) + for (ndx = 0; ndx < nxsched_npidhash(); ndx++) { /* This test and the function call must be atomic */ - if (g_pidhash[ndx]) + if (nxsched_pidhash()[ndx]) { - handler(g_pidhash[ndx], arg); + handler(nxsched_pidhash()[ndx], arg); } } diff --git a/sched/sched/sched_get_stateinfo.c b/sched/sched/sched_get_stateinfo.c index b2105431a1676..e8c3a009091ff 100644 --- a/sched/sched/sched_get_stateinfo.c +++ b/sched/sched/sched_get_stateinfo.c @@ -53,7 +53,7 @@ static FAR const char * const g_statenames[] = , "Waiting,MQ empty" , "Waiting,MQ full" #endif -#ifdef CONFIG_PAGING +#ifdef CONFIG_LEGACY_PAGING , "Waiting,Paging fill" #endif #ifdef CONFIG_SIG_SIGSTOP_ACTION diff --git a/sched/sched/sched_getaffinity.c b/sched/sched/sched_getaffinity.c index b94f997eb2da0..5c350758e9d94 100644 --- a/sched/sched/sched_getaffinity.c +++ b/sched/sched/sched_getaffinity.c @@ -69,13 +69,15 @@ int nxsched_get_affinity(pid_t pid, size_t cpusetsize, FAR cpu_set_t *mask) { FAR struct tcb_s *tcb; + irqstate_t flags; int ret; DEBUGASSERT(cpusetsize == sizeof(cpu_set_t) && mask != NULL); /* Verify that the PID corresponds to a real task */ - sched_lock(); + flags = enter_critical_section(); + if (pid == 0) { tcb = this_task(); @@ -97,7 +99,7 @@ int nxsched_get_affinity(pid_t pid, size_t cpusetsize, FAR cpu_set_t *mask) ret = OK; } - sched_unlock(); + leave_critical_section(flags); return ret; } diff --git a/sched/sched/sched_getcpu.c b/sched/sched/sched_getcpu.c index 85a172f458fde..2124d5bb6886b 100644 --- a/sched/sched/sched_getcpu.c +++ b/sched/sched/sched_getcpu.c @@ -61,5 +61,5 @@ int sched_getcpu(void) { - return up_cpu_index(); /* Does not fail */ + return this_cpu(); /* Does not fail */ } diff --git a/sched/sched/sched_getparam.c b/sched/sched/sched_getparam.c index fd196be53b2ed..89320cd88625d 100644 --- a/sched/sched/sched_getparam.c +++ b/sched/sched/sched_getparam.c @@ -70,6 +70,7 @@ int nxsched_get_param(pid_t pid, FAR struct sched_param *param) { FAR struct tcb_s *rtcb; FAR struct tcb_s *tcb; + irqstate_t flags; int ret = OK; if (param == NULL) @@ -93,7 +94,7 @@ int nxsched_get_param(pid_t pid, FAR struct sched_param *param) { /* Get the TCB associated with this PID */ - sched_lock(); + flags = enter_critical_section(); tcb = nxsched_get_tcb(pid); if (!tcb) { @@ -137,7 +138,7 @@ int nxsched_get_param(pid_t pid, FAR struct sched_param *param) #endif } - sched_unlock(); + leave_critical_section(flags); } return ret; diff --git a/sched/sched/sched_gettcb.c b/sched/sched/sched_gettcb.c index 323db70b8db35..3030355dcf35c 100644 --- a/sched/sched/sched_gettcb.c +++ b/sched/sched/sched_gettcb.c @@ -62,7 +62,7 @@ FAR struct tcb_s *nxsched_get_tcb(pid_t pid) * whether the PID is within range. */ - if (g_pidhash != NULL && pid >= 0) + if (nxsched_pidhash() != NULL && pid >= 0) { /* The test and the return setup should be atomic. This still does * not provide proper protection if the recipient of the TCB does not @@ -76,11 +76,12 @@ FAR struct tcb_s *nxsched_get_tcb(pid_t pid) /* Verify that the correct TCB was found. */ - if (g_pidhash[hash_ndx] != NULL && pid == g_pidhash[hash_ndx]->pid) + if (nxsched_pidhash()[hash_ndx] != NULL && + pid == nxsched_pidhash()[hash_ndx]->pid) { /* Return the TCB associated with this pid (if any) */ - ret = g_pidhash[hash_ndx]; + ret = nxsched_pidhash()[hash_ndx]; } } diff --git a/sched/sched/sched_idletask.c b/sched/sched/sched_idletask.c index a402a2b39a3dc..3c8edeccbde99 100644 --- a/sched/sched/sched_idletask.c +++ b/sched/sched/sched_idletask.c @@ -62,7 +62,7 @@ bool sched_idletask(void) * have been initialized and, in that case, rtcb may be NULL. */ - DEBUGASSERT(rtcb != NULL || g_nx_initstate < OSINIT_TASKLISTS); + DEBUGASSERT(rtcb != NULL || nxsched_get_initstate() < OSINIT_TASKLISTS); if (rtcb != NULL) { /* The IDLE task TCB is distinguishable by a few things: diff --git a/sched/sched/sched_lock.c b/sched/sched/sched_lock.c index 7d9dc49755da4..16cf8d46a806f 100644 --- a/sched/sched/sched_lock.c +++ b/sched/sched/sched_lock.c @@ -213,8 +213,8 @@ int sched_lock(void) * unlocked and nxsched_merge_pending() is called. */ - nxsched_merge_prioritized(&g_readytorun, - &g_pendingtasks, + nxsched_merge_prioritized(list_readytorun(), + list_pendingtasks(), TSTATE_TASK_PENDING); leave_critical_section(flags); diff --git a/sched/sched/sched_mergepending.c b/sched/sched/sched_mergepending.c index 9915eb3abde09..a8fc20e342389 100644 --- a/sched/sched/sched_mergepending.c +++ b/sched/sched/sched_mergepending.c @@ -89,7 +89,7 @@ bool nxsched_merge_pending(void) if (rtcb->lockcount == 0) { - for (ptcb = (FAR struct tcb_s *)g_pendingtasks.head; + for (ptcb = (FAR struct tcb_s *)list_pendingtasks()->head; ptcb; ptcb = pnext) { @@ -128,7 +128,8 @@ bool nxsched_merge_pending(void) ptcb->flink = rtcb; ptcb->blink = NULL; rtcb->blink = ptcb; - g_readytorun.head = (FAR dq_entry_t *)ptcb; + list_readytorun()->head + = (FAR dq_entry_t *)ptcb; rtcb->task_state = TSTATE_TASK_READYTORUN; ptcb->task_state = TSTATE_TASK_RUNNING; ret = true; @@ -151,8 +152,8 @@ bool nxsched_merge_pending(void) /* Mark the input list empty */ - g_pendingtasks.head = NULL; - g_pendingtasks.tail = NULL; + list_pendingtasks()->head = NULL; + list_pendingtasks()->tail = NULL; } return ret; @@ -189,7 +190,6 @@ bool nxsched_merge_pending(void) FAR struct tcb_s *tcb; bool ret = false; int cpu; - int me; /* Remove and process every TCB in the g_pendingtasks list. * @@ -197,12 +197,11 @@ bool nxsched_merge_pending(void) * some CPU other than this one is in a critical section. */ - me = this_cpu(); - if (!nxsched_islocked_global() && !irq_cpu_locked(me)) + if (!nxsched_islocked_global()) { /* Find the CPU that is executing the lowest priority task */ - ptcb = (FAR struct tcb_s *)dq_peek(&g_pendingtasks); + ptcb = (FAR struct tcb_s *)dq_peek(list_pendingtasks()); if (ptcb == NULL) { /* The pending task list is empty */ @@ -226,7 +225,7 @@ bool nxsched_merge_pending(void) { /* Remove the task from the pending task list */ - tcb = (FAR struct tcb_s *)dq_remfirst(&g_pendingtasks); + tcb = (FAR struct tcb_s *)dq_remfirst(list_pendingtasks()); /* Add the pending task to the correct ready-to-run list. */ @@ -236,15 +235,15 @@ bool nxsched_merge_pending(void) * Check if that happened. */ - if (nxsched_islocked_global() || irq_cpu_locked(me)) + if (nxsched_islocked_global()) { /* Yes.. then we may have incorrectly placed some TCBs in the * g_readytorun list (unlikely, but possible). We will have to * move them back to the pending task list. */ - nxsched_merge_prioritized(&g_readytorun, - &g_pendingtasks, + nxsched_merge_prioritized(list_readytorun(), + list_pendingtasks(), TSTATE_TASK_PENDING); /* And return with the scheduler locked and tasks in the @@ -256,7 +255,7 @@ bool nxsched_merge_pending(void) /* Set up for the next time through the loop */ - ptcb = (FAR struct tcb_s *)dq_peek(&g_pendingtasks); + ptcb = (FAR struct tcb_s *)dq_peek(list_pendingtasks()); if (ptcb == NULL) { /* The pending task list is empty */ @@ -272,8 +271,8 @@ bool nxsched_merge_pending(void) * tasks in the pending task list to the ready-to-run task list. */ - nxsched_merge_prioritized(&g_pendingtasks, - &g_readytorun, + nxsched_merge_prioritized(list_pendingtasks(), + list_readytorun(), TSTATE_TASK_READYTORUN); } diff --git a/sched/sched/sched_releasetcb.c b/sched/sched/sched_releasetcb.c index dc996af946610..e5745116fa230 100644 --- a/sched/sched/sched_releasetcb.c +++ b/sched/sched/sched_releasetcb.c @@ -31,6 +31,7 @@ #include #include +#include "task/task.h" #include "sched/sched.h" #include "group/group.h" #include "timer/timer.h" @@ -56,7 +57,7 @@ static void nxsched_releasepid(pid_t pid) * total for all threads. */ - g_cpuload_total -= g_pidhash[hash_ndx]->ticks; + g_cpuload_total -= nxsched_pidhash()[hash_ndx]->ticks; #endif /* Make any pid associated with this hash available. Note: @@ -64,7 +65,7 @@ static void nxsched_releasepid(pid_t pid) * following action is atomic */ - g_pidhash[hash_ndx] = NULL; + nxsched_pidhash()[hash_ndx] = NULL; leave_critical_section(flags); } @@ -97,6 +98,9 @@ static void nxsched_releasepid(pid_t pid) int nxsched_release_tcb(FAR struct tcb_s *tcb, uint8_t ttype) { +#ifndef CONFIG_DISABLE_PTHREAD + FAR struct task_tcb_s *ttcb; +#endif int ret = OK; if (tcb) @@ -161,9 +165,37 @@ int nxsched_release_tcb(FAR struct tcb_s *tcb, uint8_t ttype) group_leave(tcb); +#ifndef CONFIG_DISABLE_PTHREAD + /* Destroy the pthread join mutex */ + + nxtask_joindestroy(tcb); + + /* Kernel thread and group still reference by pthread */ + + if (ttype != TCB_FLAG_TTYPE_PTHREAD) + { + ttcb = (FAR struct task_tcb_s *)tcb; + if (!sq_empty(&ttcb->group.tg_members) +#if defined(CONFIG_SCHED_WAITPID) && !defined(CONFIG_SCHED_HAVE_PARENT) + || ttcb->group.tg_nwaiters > 0 +#endif + ) + { + /* Mark the group as deleted now */ + + ttcb->group.tg_flags |= GROUP_FLAG_DELETED; + + return ret; + } + } +#endif + /* And, finally, release the TCB itself */ - kmm_free(tcb); + if (tcb->flags & TCB_FLAG_FREE_TCB) + { + kmm_free(tcb); + } } return ret; diff --git a/sched/sched/sched_removereadytorun.c b/sched/sched/sched_removereadytorun.c index ba954c4d5f8b7..4d9050b36ac63 100644 --- a/sched/sched/sched_removereadytorun.c +++ b/sched/sched/sched_removereadytorun.c @@ -97,7 +97,7 @@ bool nxsched_remove_readytorun(FAR struct tcb_s *rtcb, bool merge) rtcb->task_state = TSTATE_TASK_INVALID; - if (g_pendingtasks.head && merge) + if (list_pendingtasks()->head && merge) { doswitch |= nxsched_merge_pending(); } @@ -200,7 +200,7 @@ bool nxsched_remove_readytorun(FAR struct tcb_s *rtcb, bool merge) * CPU. */ - for (rtrtcb = (FAR struct tcb_s *)g_readytorun.head; + for (rtrtcb = (FAR struct tcb_s *)list_readytorun()->head; rtrtcb != NULL && !CPU_ISSET(cpu, &rtrtcb->affinity); rtrtcb = rtrtcb->flink); @@ -218,7 +218,7 @@ bool nxsched_remove_readytorun(FAR struct tcb_s *rtcb, bool merge) * list and add to the head of the g_assignedtasks[cpu] list. */ - dq_rem((FAR dq_entry_t *)rtrtcb, &g_readytorun); + dq_rem((FAR dq_entry_t *)rtrtcb, list_readytorun()); dq_addfirst((FAR dq_entry_t *)rtrtcb, tasklist); rtrtcb->cpu = cpu; @@ -279,7 +279,7 @@ bool nxsched_remove_readytorun(FAR struct tcb_s *rtcb, bool merge) rtcb->task_state = TSTATE_TASK_INVALID; - if (g_pendingtasks.head && merge) + if (list_pendingtasks()->head && merge) { doswitch |= nxsched_merge_pending(); } diff --git a/sched/sched/sched_reprioritizertr.c b/sched/sched/sched_reprioritizertr.c index a94cf0e298b69..8b4c6b98c2a4d 100644 --- a/sched/sched/sched_reprioritizertr.c +++ b/sched/sched/sched_reprioritizertr.c @@ -82,7 +82,7 @@ bool nxsched_reprioritize_rtr(FAR struct tcb_s *tcb, int priority) * time to add any pending tasks back into the ready-to-run list. */ - if (switch_needed && g_pendingtasks.head) + if (switch_needed && list_pendingtasks()->head) { nxsched_merge_pending(); } diff --git a/sched/sched/sched_resumescheduler.c b/sched/sched/sched_resumescheduler.c index 77d6bc92d2ff5..025e0e2a43e53 100644 --- a/sched/sched/sched_resumescheduler.c +++ b/sched/sched/sched_resumescheduler.c @@ -33,7 +33,7 @@ #include "irq/irq.h" #include "sched/sched.h" -#if CONFIG_RR_INTERVAL > 0 || defined(CONFIG_SCHED_RESUMESCHEDULER) +#if defined(CONFIG_SCHED_RESUMESCHEDULER) /**************************************************************************** * Public Functions diff --git a/sched/sched/sched_setpriority.c b/sched/sched/sched_setpriority.c index 711ecb61f768c..abe031242b7b8 100644 --- a/sched/sched/sched_setpriority.c +++ b/sched/sched/sched_setpriority.c @@ -68,11 +68,11 @@ static FAR struct tcb_s *nxsched_nexttcb(FAR struct tcb_s *tcb) * then use the 'nxttcb' which will probably be the IDLE thread. */ - if (!nxsched_islocked_global() && !irq_cpu_locked(this_cpu())) + if (!nxsched_islocked_global()) { /* Search for the highest priority task that can run on tcb->cpu. */ - for (rtrtcb = (FAR struct tcb_s *)g_readytorun.head; + for (rtrtcb = (FAR struct tcb_s *)list_readytorun()->head; rtrtcb != NULL && !CPU_ISSET(tcb->cpu, &rtrtcb->affinity); rtrtcb = rtrtcb->flink); @@ -154,7 +154,7 @@ static inline void nxsched_running_setpriority(FAR struct tcb_s *tcb, DEBUGASSERT(check == false); UNUSED(check); - nxsched_add_prioritized(nxttcb, &g_pendingtasks); + nxsched_add_prioritized(nxttcb, list_pendingtasks()); nxttcb->task_state = TSTATE_TASK_PENDING; #ifdef CONFIG_SMP diff --git a/sched/sched/sched_suspend.c b/sched/sched/sched_suspend.c index 53bd8f294a9b3..8d4be93eaad87 100644 --- a/sched/sched/sched_suspend.c +++ b/sched/sched/sched_suspend.c @@ -75,7 +75,7 @@ void nxsched_suspend(FAR struct tcb_s *tcb) /* Move the TCB to the g_stoppedtasks list. */ tcb->task_state = TSTATE_TASK_STOPPED; - dq_addlast((FAR dq_entry_t *)tcb, &g_stoppedtasks); + dq_addlast((FAR dq_entry_t *)tcb, list_stoppedtasks()); } else { @@ -97,7 +97,7 @@ void nxsched_suspend(FAR struct tcb_s *tcb) /* Add the task to the specified blocked task list */ tcb->task_state = TSTATE_TASK_STOPPED; - dq_addlast((FAR dq_entry_t *)tcb, &g_stoppedtasks); + dq_addlast((FAR dq_entry_t *)tcb, list_stoppedtasks()); /* Now, perform the context switch if one is needed */ diff --git a/sched/sched/sched_unlock.c b/sched/sched/sched_unlock.c index eec27fd4a2336..87beda977f5a9 100644 --- a/sched/sched/sched_unlock.c +++ b/sched/sched/sched_unlock.c @@ -137,8 +137,8 @@ int sched_unlock(void) * BEFORE it clears IRQ lock. */ - if (!nxsched_islocked_global() && !irq_cpu_locked(cpu) && - g_pendingtasks.head != NULL) + if (!nxsched_islocked_global() && + list_pendingtasks()->head != NULL) { if (nxsched_merge_pending()) { @@ -272,7 +272,7 @@ int sched_unlock(void) * fully independently. */ - if (g_pendingtasks.head != NULL) + if (list_pendingtasks()->head != NULL) { if (nxsched_merge_pending()) { diff --git a/sched/sched/sched_verifytcb.c b/sched/sched/sched_verifytcb.c index 01a6f19bd9fa0..1dbe79f1d48b7 100644 --- a/sched/sched/sched_verifytcb.c +++ b/sched/sched/sched_verifytcb.c @@ -72,7 +72,7 @@ bool nxsched_verify_tcb(FAR struct tcb_s *tcb) bool valid; flags = enter_critical_section(); - valid = tcb == g_pidhash[PIDHASH(tcb->pid)]; + valid = tcb == nxsched_pidhash()[PIDHASH(tcb->pid)]; leave_critical_section(flags); return valid; diff --git a/sched/sched/sched_waitid.c b/sched/sched/sched_waitid.c index 0dcbb087fe0ff..22188f5755626 100644 --- a/sched/sched/sched_waitid.c +++ b/sched/sched/sched_waitid.c @@ -152,6 +152,7 @@ int waitid(idtype_t idtype, id_t id, FAR siginfo_t *info, int options) FAR struct child_status_s *child; bool retains; #endif + irqstate_t flags; sigset_t set; int errcode; int ret; @@ -198,18 +199,7 @@ int waitid(idtype_t idtype, id_t id, FAR siginfo_t *info, int options) sigemptyset(&set); nxsig_addset(&set, SIGCHLD); - - /* NOTE: sched_lock() is not enough for SMP - * because the child task is running on another CPU - */ - -#ifdef CONFIG_SMP - irqstate_t flags = enter_critical_section(); -#else - /* Disable pre-emption so that nothing changes while the loop executes */ - - sched_lock(); -#endif + flags = enter_critical_section(); /* Verify that this task actually has children and that the requested * TCB is actually a child of this task. @@ -464,20 +454,12 @@ int waitid(idtype_t idtype, id_t id, FAR siginfo_t *info, int options) } } -#ifdef CONFIG_SMP leave_critical_section(flags); -#else - sched_unlock(); -#endif leave_cancellation_point(); return OK; errout: -#ifdef CONFIG_SMP leave_critical_section(flags); -#else - sched_unlock(); -#endif leave_cancellation_point(); set_errno(errcode); return ERROR; diff --git a/sched/sched/sched_waitpid.c b/sched/sched/sched_waitpid.c index 078a35a7bafc7..ff77a83e44c66 100644 --- a/sched/sched/sched_waitpid.c +++ b/sched/sched/sched_waitpid.c @@ -101,13 +101,7 @@ pid_t nxsched_waitpid(pid_t pid, int *stat_loc, int options) * because the child task is running on another CPU */ -#ifdef CONFIG_SMP irqstate_t flags = enter_critical_section(); -#else - /* Disable pre-emption so that nothing changes in the following tests */ - - sched_lock(); -#endif /* Get the TCB corresponding to this PID */ @@ -198,12 +192,7 @@ pid_t nxsched_waitpid(pid_t pid, int *stat_loc, int options) ret = pid; errout: -#ifdef CONFIG_SMP leave_critical_section(flags); -#else - sched_unlock(); -#endif - return ret; } @@ -230,6 +219,7 @@ pid_t nxsched_waitpid(pid_t pid, int *stat_loc, int options) bool retains; #endif FAR struct siginfo info; + irqstate_t flags; sigset_t set; int ret; @@ -237,18 +227,7 @@ pid_t nxsched_waitpid(pid_t pid, int *stat_loc, int options) sigemptyset(&set); nxsig_addset(&set, SIGCHLD); - - /* NOTE: sched_lock() is not enough for SMP - * because the child task is running on another CPU - */ - -#ifdef CONFIG_SMP - irqstate_t flags = enter_critical_section(); -#else - /* Disable pre-emption so that nothing changes while the loop executes */ - - sched_lock(); -#endif + flags = enter_critical_section(); /* Verify that this task actually has children and that the requested PID * is actually a child of this task. @@ -495,12 +474,7 @@ pid_t nxsched_waitpid(pid_t pid, int *stat_loc, int options) ret = pid; errout: -#ifdef CONFIG_SMP leave_critical_section(flags); -#else - sched_unlock(); -#endif - return ret; } #endif /* CONFIG_SCHED_HAVE_PARENT */ diff --git a/sched/semaphore/sem_rw.c b/sched/semaphore/sem_rw.c index 2a6f566dd1ba8..238c071a489af 100644 --- a/sched/semaphore/sem_rw.c +++ b/sched/semaphore/sem_rw.c @@ -23,6 +23,8 @@ ****************************************************************************/ #include +#include +#include /**************************************************************************** * Private Functions @@ -61,11 +63,11 @@ static inline void up_wait(FAR rw_semaphore_t *rwsem) int down_read_trylock(FAR rw_semaphore_t *rwsem) { - nxmutex_lock(&rwsem->protected); + irqstate_t flags = spin_lock_irqsave(&rwsem->protected); if (rwsem->writer > 0) { - nxmutex_unlock(&rwsem->protected); + spin_unlock_irqrestore(&rwsem->protected, flags); return 0; } @@ -75,7 +77,7 @@ int down_read_trylock(FAR rw_semaphore_t *rwsem) rwsem->reader++; - nxmutex_unlock(&rwsem->protected); + spin_unlock_irqrestore(&rwsem->protected, flags); return 1; } @@ -97,14 +99,14 @@ void down_read(FAR rw_semaphore_t *rwsem) * block and wait for the write-lock to be unlocked. */ - nxmutex_lock(&rwsem->protected); + irqstate_t flags = spin_lock_irqsave(&rwsem->protected); while (rwsem->writer > 0) { rwsem->waiter++; - nxmutex_unlock(&rwsem->protected); + spin_unlock_irqrestore(&rwsem->protected, flags); nxsem_wait(&rwsem->waiting); - nxmutex_lock(&rwsem->protected); + flags = spin_lock_irqsave(&rwsem->protected); rwsem->waiter--; } @@ -114,7 +116,7 @@ void down_read(FAR rw_semaphore_t *rwsem) rwsem->reader++; - nxmutex_unlock(&rwsem->protected); + spin_unlock_irqrestore(&rwsem->protected, flags); } /**************************************************************************** @@ -130,7 +132,7 @@ void down_read(FAR rw_semaphore_t *rwsem) void up_read(FAR rw_semaphore_t *rwsem) { - nxmutex_lock(&rwsem->protected); + irqstate_t flags = spin_lock_irqsave(&rwsem->protected); DEBUGASSERT(rwsem->reader > 0); @@ -141,7 +143,7 @@ void up_read(FAR rw_semaphore_t *rwsem) up_wait(rwsem); } - nxmutex_unlock(&rwsem->protected); + spin_unlock_irqrestore(&rwsem->protected, flags); } /**************************************************************************** @@ -160,11 +162,11 @@ void up_read(FAR rw_semaphore_t *rwsem) int down_write_trylock(FAR rw_semaphore_t *rwsem) { - nxmutex_lock(&rwsem->protected); + irqstate_t flags = spin_lock_irqsave(&rwsem->protected); if (rwsem->writer > 0 || rwsem->reader > 0) { - nxmutex_unlock(&rwsem->protected); + spin_unlock_irqrestore(&rwsem->protected, flags); return 0; } @@ -172,7 +174,7 @@ int down_write_trylock(FAR rw_semaphore_t *rwsem) rwsem->writer++; - nxmutex_unlock(&rwsem->protected); + spin_unlock_irqrestore(&rwsem->protected, flags); return 1; } @@ -190,14 +192,14 @@ int down_write_trylock(FAR rw_semaphore_t *rwsem) void down_write(FAR rw_semaphore_t *rwsem) { - nxmutex_lock(&rwsem->protected); + irqstate_t flags = spin_lock_irqsave(&rwsem->protected); while (rwsem->reader > 0 || rwsem->writer > 0) { rwsem->waiter++; - nxmutex_unlock(&rwsem->protected); + spin_unlock_irqrestore(&rwsem->protected, flags); nxsem_wait(&rwsem->waiting); - nxmutex_lock(&rwsem->protected); + flags = spin_lock_irqsave(&rwsem->protected); rwsem->waiter--; } @@ -205,7 +207,7 @@ void down_write(FAR rw_semaphore_t *rwsem) rwsem->writer++; - nxmutex_unlock(&rwsem->protected); + spin_unlock_irqrestore(&rwsem->protected, flags); } /**************************************************************************** @@ -221,7 +223,7 @@ void down_write(FAR rw_semaphore_t *rwsem) void up_write(FAR rw_semaphore_t *rwsem) { - nxmutex_lock(&rwsem->protected); + irqstate_t flags = spin_lock_irqsave(&rwsem->protected); DEBUGASSERT(rwsem->writer > 0); @@ -229,7 +231,7 @@ void up_write(FAR rw_semaphore_t *rwsem) up_wait(rwsem); - nxmutex_unlock(&rwsem->protected); + spin_unlock_irqrestore(&rwsem->protected, flags); } /**************************************************************************** @@ -253,16 +255,11 @@ int init_rwsem(FAR rw_semaphore_t *rwsem) /* Initialize structure information */ - ret = nxmutex_init(&rwsem->protected); - if (ret < 0) - { - return ret; - } + spin_lock_init(&rwsem->protected); ret = nxsem_init(&rwsem->waiting, 0, 0); if (ret < 0) { - nxmutex_destroy(&rwsem->protected); return ret; } @@ -292,6 +289,5 @@ void destroy_rwsem(FAR rw_semaphore_t *rwsem) DEBUGASSERT(rwsem->waiter == 0 && rwsem->reader == 0 && rwsem->writer == 0); - nxmutex_destroy(&rwsem->protected); nxsem_destroy(&rwsem->waiting); } diff --git a/sched/signal/sig_dispatch.c b/sched/signal/sig_dispatch.c index d910fb090447a..45744cb9f57f5 100644 --- a/sched/signal/sig_dispatch.c +++ b/sched/signal/sig_dispatch.c @@ -398,7 +398,11 @@ int nxsig_tcbdispatch(FAR struct tcb_s *stcb, siginfo_t *info) (masked == 0 || nxsig_ismember(&stcb->sigwaitmask, info->si_signo))) { - memcpy(&stcb->sigunbinfo, info, sizeof(siginfo_t)); + if (stcb->sigunbinfo != NULL) + { + memcpy(stcb->sigunbinfo, info, sizeof(siginfo_t)); + } + sigemptyset(&stcb->sigwaitmask); if (WDOG_ISACTIVE(&stcb->waitdog)) @@ -408,7 +412,7 @@ int nxsig_tcbdispatch(FAR struct tcb_s *stcb, siginfo_t *info) /* Remove the task from waitting list */ - dq_rem((FAR dq_entry_t *)stcb, &g_waitingforsignal); + dq_rem((FAR dq_entry_t *)stcb, list_waitingforsignal()); /* Add the task to ready-to-run task list and * perform the context switch if one is needed @@ -461,7 +465,11 @@ int nxsig_tcbdispatch(FAR struct tcb_s *stcb, siginfo_t *info) if (stcb->task_state == TSTATE_WAIT_SIG) { - memcpy(&stcb->sigunbinfo, info, sizeof(siginfo_t)); + if (stcb->sigunbinfo != NULL) + { + memcpy(stcb->sigunbinfo, info, sizeof(siginfo_t)); + } + sigemptyset(&stcb->sigwaitmask); if (WDOG_ISACTIVE(&stcb->waitdog)) @@ -471,7 +479,7 @@ int nxsig_tcbdispatch(FAR struct tcb_s *stcb, siginfo_t *info) /* Remove the task from waitting list */ - dq_rem((FAR dq_entry_t *)stcb, &g_waitingforsignal); + dq_rem((FAR dq_entry_t *)stcb, list_waitingforsignal()); /* Add the task to ready-to-run task list and * perform the context switch if one is needed @@ -535,7 +543,7 @@ int nxsig_tcbdispatch(FAR struct tcb_s *stcb, siginfo_t *info) #else /* Remove the task from waitting list */ - dq_rem((FAR dq_entry_t *)stcb, &g_stoppedtasks); + dq_rem((FAR dq_entry_t *)stcb, list_stoppedtasks()); /* Add the task to ready-to-run task list and * perform the context switch if one is needed @@ -614,7 +622,7 @@ int nxsig_dispatch(pid_t pid, FAR siginfo_t *info) * created the task group. Try looking it up. */ - group = group_findbypid(pid); + group = task_getgroup(pid); } /* Did we locate the group? */ diff --git a/sched/signal/sig_initialize.c b/sched/signal/sig_initialize.c index 12d7cec37f231..3f9e2a1e67e86 100644 --- a/sched/signal/sig_initialize.c +++ b/sched/signal/sig_initialize.c @@ -68,111 +68,56 @@ sq_queue_t g_sigpendingsignal; sq_queue_t g_sigpendingirqsignal; -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* g_sigpendingactionalloc is a pointer to the start of the allocated - * blocks of pending signal actions. - */ - -static sigq_t *g_sigpendingactionalloc; - -/* g_sigpendingirqactionalloc is a pointer to the start of the allocated - * block of pending signal actions. - */ - -static sigq_t *g_sigpendingirqactionalloc; - -/* g_sigpendingsignalalloc is a pointer to the start of the allocated - * blocks of pending signals. - */ - -static sigpendq_t *g_sigpendingsignalalloc; - -/* g_sigpendingirqsignalalloc is a pointer to the start of the allocated - * blocks of pending signals. - */ - -static sigpendq_t *g_sigpendingirqsignalalloc; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static sigq_t *nxsig_alloc_block(sq_queue_t *siglist, uint16_t nsigs, - uint8_t sigtype); -static sigpendq_t *nxsig_alloc_pendingsignalblock(sq_queue_t *siglist, - uint16_t nsigs, - uint8_t sigtype); - /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: nxsig_alloc_block + * Name: nxsig_init_block * * Description: - * Allocate a block of pending signal actions and place them + * Initialize a block of pending signal actions and place them * on the free list. * ****************************************************************************/ -static FAR sigq_t *nxsig_alloc_block(sq_queue_t *siglist, uint16_t nsigs, - uint8_t sigtype) +static void *nxsig_init_block(sq_queue_t *siglist, FAR sigq_t *sigq, + uint16_t nsigs, uint8_t sigtype) { - FAR sigq_t *sigqalloc; - FAR sigq_t *sigq; int i; - /* Allocate a block of pending signal actions. */ - - sigqalloc = kmm_malloc(sizeof(sigq_t) * nsigs); - if (sigqalloc != NULL) + for (i = 0; i < nsigs; i++) { - sigq = sigqalloc; - for (i = 0; i < nsigs; i++) - { - sigq->type = sigtype; - sq_addlast((FAR sq_entry_t *)sigq++, siglist); - } + sigq->type = sigtype; + sq_addlast((FAR sq_entry_t *)sigq++, siglist); } - return sigqalloc; + return sigq; } /**************************************************************************** - * Name: nxsig_alloc_pendingsignalblock + * Name: nxsig_init_pendingsignalblock * * Description: - * Allocate a block of pending signal structures and place them on + * Initialize a block of pending signal structures and place them on * the free list. * ****************************************************************************/ -static sigpendq_t *nxsig_alloc_pendingsignalblock(sq_queue_t *siglist, - uint16_t nsigs, - uint8_t sigtype) +static void *nxsig_init_pendingsignalblock(FAR sq_queue_t *siglist, + FAR sigpendq_t *sigpend, + uint16_t nsigs, + uint8_t sigtype) { - FAR sigpendq_t *sigpendalloc; - FAR sigpendq_t *sigpend; int i; - /* Allocate a block of pending signal structures */ - - sigpendalloc = kmm_malloc(sizeof(sigpendq_t) * nsigs); - if (sigpendalloc != NULL) + for (i = 0; i < nsigs; i++) { - sigpend = sigpendalloc; - for (i = 0; i < nsigs; i++) - { - sigpend->type = sigtype; - sq_addlast((FAR sq_entry_t *)sigpend++, siglist); - } + sigpend->type = sigtype; + sq_addlast((FAR sq_entry_t *)sigpend++, siglist); } - return sigpendalloc; + return sigpend; } /**************************************************************************** @@ -189,6 +134,8 @@ static sigpendq_t *nxsig_alloc_pendingsignalblock(sq_queue_t *siglist, void nxsig_initialize(void) { + FAR void *sigpool; + sched_trace_begin(); /* Initialize free lists */ @@ -201,28 +148,24 @@ void nxsig_initialize(void) /* Add a block of signal structures to each list */ - g_sigpendingactionalloc = - nxsig_alloc_block(&g_sigpendingaction, - NUM_PENDING_ACTIONS, - SIG_ALLOC_FIXED); - DEBUGASSERT(g_sigpendingactionalloc != NULL); - - g_sigpendingirqactionalloc = - nxsig_alloc_block(&g_sigpendingirqaction, - CONFIG_SIG_PREALLOC_IRQ_ACTIONS, - SIG_ALLOC_IRQ); - DEBUGASSERT(g_sigpendingirqactionalloc != NULL); - - g_sigpendingsignalalloc = - nxsig_alloc_pendingsignalblock(&g_sigpendingsignal, - NUM_SIGNALS_PENDING, - SIG_ALLOC_FIXED); - DEBUGASSERT(g_sigpendingsignalalloc != NULL); - - g_sigpendingirqsignalalloc = - nxsig_alloc_pendingsignalblock(&g_sigpendingirqsignal, - CONFIG_SIG_PREALLOC_IRQ_ACTIONS, - SIG_ALLOC_IRQ); - DEBUGASSERT(g_sigpendingirqsignalalloc != NULL); + sigpool = + kmm_malloc(sizeof(sigq_t) * + (NUM_PENDING_ACTIONS + CONFIG_SIG_PREALLOC_IRQ_ACTIONS) + + sizeof(sigpendq_t) * + (NUM_SIGNALS_PENDING + CONFIG_SIG_PREALLOC_IRQ_ACTIONS)); + + DEBUGASSERT(sigpool != NULL); + + sigpool = nxsig_init_block(&g_sigpendingaction, sigpool, + NUM_PENDING_ACTIONS, SIG_ALLOC_FIXED); + sigpool = nxsig_init_block(&g_sigpendingirqaction, sigpool, + CONFIG_SIG_PREALLOC_IRQ_ACTIONS, + SIG_ALLOC_IRQ); + sigpool = nxsig_init_pendingsignalblock(&g_sigpendingsignal, sigpool, + NUM_SIGNALS_PENDING, + SIG_ALLOC_FIXED); + sigpool = nxsig_init_pendingsignalblock(&g_sigpendingirqsignal, sigpool, + CONFIG_SIG_PREALLOC_IRQ_ACTIONS, + SIG_ALLOC_IRQ); sched_trace_end(); } diff --git a/sched/signal/sig_suspend.c b/sched/signal/sig_suspend.c index b4e4667fda376..e6dbc203dd0af 100644 --- a/sched/signal/sig_suspend.c +++ b/sched/signal/sig_suspend.c @@ -132,7 +132,7 @@ int sigsuspend(FAR const sigset_t *set) /* Add the task to the specified blocked task list */ rtcb->task_state = TSTATE_WAIT_SIG; - dq_addlast((FAR dq_entry_t *)rtcb, &g_waitingforsignal); + dq_addlast((FAR dq_entry_t *)rtcb, list_waitingforsignal()); /* Now, perform the context switch if one is needed */ diff --git a/sched/signal/sig_timedwait.c b/sched/signal/sig_timedwait.c index c75eaf8eda87f..1b7985deebd29 100644 --- a/sched/signal/sig_timedwait.c +++ b/sched/signal/sig_timedwait.c @@ -99,18 +99,21 @@ static void nxsig_timeout(wdparm_t arg) { FAR struct tcb_s *rtcb = this_task(); - wtcb->sigunbinfo.si_signo = SIG_WAIT_TIMEOUT; - wtcb->sigunbinfo.si_code = SI_TIMER; - wtcb->sigunbinfo.si_errno = ETIMEDOUT; - wtcb->sigunbinfo.si_value.sival_int = 0; + if (wtcb->sigunbinfo != NULL) + { + wtcb->sigunbinfo->si_signo = SIG_WAIT_TIMEOUT; + wtcb->sigunbinfo->si_code = SI_TIMER; + wtcb->sigunbinfo->si_errno = ETIMEDOUT; + wtcb->sigunbinfo->si_value.sival_int = 0; #ifdef CONFIG_SCHED_HAVE_PARENT - wtcb->sigunbinfo.si_pid = 0; /* Not applicable */ - wtcb->sigunbinfo.si_status = OK; + wtcb->sigunbinfo->si_pid = 0; /* Not applicable */ + wtcb->sigunbinfo->si_status = OK; #endif + } /* Remove the task from waitting list */ - dq_rem((FAR dq_entry_t *)wtcb, &g_waitingforsignal); + dq_rem((FAR dq_entry_t *)wtcb, list_waitingforsignal()); /* Add the task to ready-to-run task list, and * perform the context switch if one is needed @@ -166,18 +169,21 @@ void nxsig_wait_irq(FAR struct tcb_s *wtcb, int errcode) { FAR struct tcb_s *rtcb = this_task(); - wtcb->sigunbinfo.si_signo = SIG_CANCEL_TIMEOUT; - wtcb->sigunbinfo.si_code = SI_USER; - wtcb->sigunbinfo.si_errno = errcode; - wtcb->sigunbinfo.si_value.sival_int = 0; + if (wtcb->sigunbinfo != NULL) + { + wtcb->sigunbinfo->si_signo = SIG_CANCEL_TIMEOUT; + wtcb->sigunbinfo->si_code = SI_USER; + wtcb->sigunbinfo->si_errno = errcode; + wtcb->sigunbinfo->si_value.sival_int = 0; #ifdef CONFIG_SCHED_HAVE_PARENT - wtcb->sigunbinfo.si_pid = 0; /* Not applicable */ - wtcb->sigunbinfo.si_status = OK; + wtcb->sigunbinfo->si_pid = 0; /* Not applicable */ + wtcb->sigunbinfo->si_status = OK; #endif + } /* Remove the task from waitting list */ - dq_rem((FAR dq_entry_t *)wtcb, &g_waitingforsignal); + dq_rem((FAR dq_entry_t *)wtcb, list_waitingforsignal()); /* Add the task to ready-to-run task list, and * perform the context switch if one is needed @@ -244,6 +250,7 @@ int nxsig_timedwait(FAR const sigset_t *set, FAR struct siginfo *info, irqstate_t flags; sclock_t waitticks; bool switch_needed; + siginfo_t sinfo; int ret; DEBUGASSERT(set != NULL); @@ -311,6 +318,8 @@ int nxsig_timedwait(FAR const sigset_t *set, FAR struct siginfo *info, } #endif + rtcb->sigunbinfo = (info == NULL) ? &sinfo : info; + /* Check if we should wait for the timeout */ if (timeout != NULL) @@ -358,7 +367,7 @@ int nxsig_timedwait(FAR const sigset_t *set, FAR struct siginfo *info, /* Add the task to the specified blocked task list */ rtcb->task_state = TSTATE_WAIT_SIG; - dq_addlast((FAR dq_entry_t *)rtcb, &g_waitingforsignal); + dq_addlast((FAR dq_entry_t *)rtcb, list_waitingforsignal()); /* Now, perform the context switch if one is needed */ @@ -373,6 +382,8 @@ int nxsig_timedwait(FAR const sigset_t *set, FAR struct siginfo *info, } else { + rtcb->sigunbinfo = NULL; + leave_critical_section(flags); return -EAGAIN; } @@ -400,7 +411,7 @@ int nxsig_timedwait(FAR const sigset_t *set, FAR struct siginfo *info, /* Add the task to the specified blocked task list */ rtcb->task_state = TSTATE_WAIT_SIG; - dq_addlast((FAR dq_entry_t *)rtcb, &g_waitingforsignal); + dq_addlast((FAR dq_entry_t *)rtcb, list_waitingforsignal()); /* Now, perform the context switch if one is needed */ @@ -418,26 +429,19 @@ int nxsig_timedwait(FAR const sigset_t *set, FAR struct siginfo *info, * or timeout) that awakened us. */ - if (GOOD_SIGNO(rtcb->sigunbinfo.si_signo)) + if (GOOD_SIGNO(rtcb->sigunbinfo->si_signo)) { /* We were awakened by a signal... but is it one of the signals * that we were waiting for? */ - if (nxsig_ismember(set, rtcb->sigunbinfo.si_signo)) + if (nxsig_ismember(set, rtcb->sigunbinfo->si_signo)) { - /* Return the signal info to the caller if so requested */ - - if (info != NULL) - { - memcpy(info, &rtcb->sigunbinfo, sizeof(struct siginfo)); - } - /* Yes.. the return value is the number of the signal that * awakened us. */ - ret = rtcb->sigunbinfo.si_signo; + ret = rtcb->sigunbinfo->si_signo; } else { @@ -453,11 +457,11 @@ int nxsig_timedwait(FAR const sigset_t *set, FAR struct siginfo *info, */ #ifdef CONFIG_CANCELLATION_POINTS - if (rtcb->sigunbinfo.si_signo == SIG_CANCEL_TIMEOUT) + if (rtcb->sigunbinfo->si_signo == SIG_CANCEL_TIMEOUT) { /* The wait was canceled */ - ret = -rtcb->sigunbinfo.si_errno; + ret = -rtcb->sigunbinfo->si_errno; DEBUGASSERT(ret < 0); } else @@ -467,11 +471,13 @@ int nxsig_timedwait(FAR const sigset_t *set, FAR struct siginfo *info, * error. */ - DEBUGASSERT(rtcb->sigunbinfo.si_signo == SIG_WAIT_TIMEOUT); + DEBUGASSERT(rtcb->sigunbinfo->si_signo == SIG_WAIT_TIMEOUT); ret = -EAGAIN; } } + rtcb->sigunbinfo = NULL; + leave_critical_section(flags); } diff --git a/sched/task/CMakeLists.txt b/sched/task/CMakeLists.txt index 9e0f98ac54448..3f049de62137f 100644 --- a/sched/task/CMakeLists.txt +++ b/sched/task/CMakeLists.txt @@ -36,6 +36,7 @@ set(SRCS task_cancelpt.c task_terminate.c task_gettid.c + task_join.c exit.c) if(CONFIG_SCHED_HAVE_PARENT) diff --git a/sched/task/Make.defs b/sched/task/Make.defs index 1db20a6a054bd..199ff51bda5cd 100644 --- a/sched/task/Make.defs +++ b/sched/task/Make.defs @@ -22,7 +22,7 @@ CSRCS += task_create.c task_init.c task_setup.c task_activate.c CSRCS += task_start.c task_delete.c task_exit.c task_exithook.c CSRCS += task_getgroup.c task_getpid.c task_prctl.c task_recover.c CSRCS += task_restart.c task_spawnparms.c task_cancelpt.c task_terminate.c -CSRCS += task_gettid.c exit.c +CSRCS += task_gettid.c exit.c task_join.c ifeq ($(CONFIG_SCHED_HAVE_PARENT),y) CSRCS += task_getppid.c task_reparent.c diff --git a/sched/task/task.h b/sched/task/task.h index ca63d2c756a3f..9de238be3907f 100644 --- a/sched/task/task.h +++ b/sched/task/task.h @@ -58,4 +58,14 @@ void nxtask_recover(FAR struct tcb_s *tcb); bool nxnotify_cancellation(FAR struct tcb_s *tcb); +/* Task Join */ + +#ifndef CONFIG_DISABLE_PTHREAD +void nxtask_joininit(FAR struct tcb_s *tcb); +void nxtask_joindestroy(FAR struct tcb_s *tcb); +#else +# define nxtask_joininit(tcb) +# define nxtask_joindestroy(tcb) +#endif + #endif /* __SCHED_TASK_TASK_H */ diff --git a/sched/task/task_activate.c b/sched/task/task_activate.c index 7fb6496183d2e..564403d20df8a 100644 --- a/sched/task/task_activate.c +++ b/sched/task/task_activate.c @@ -84,6 +84,13 @@ void nxtask_activate(FAR struct tcb_s *tcb) nxsched_remove_blocked(tcb); +#if CONFIG_TASK_NAME_SIZE > 0 + sinfo("%s pid=%d,TCB=%p\n", tcb->name, +#else + sinfo("pid=%d,TCB=%p\n", +#endif + tcb->pid, tcb); + /* Add the task to ready-to-run task list, and * perform the context switch if one is needed */ diff --git a/sched/task/task_create.c b/sched/task/task_create.c index 17a84202d0856..f934078a374c9 100644 --- a/sched/task/task_create.c +++ b/sched/task/task_create.c @@ -91,7 +91,7 @@ int nxthread_create(FAR const char *name, uint8_t ttype, int priority, /* Setup the task type */ - tcb->cmn.flags = ttype; + tcb->cmn.flags = ttype | TCB_FLAG_FREE_TCB; /* Initialize the task */ diff --git a/sched/task/task_exit.c b/sched/task/task_exit.c index 02a5c83064cab..28272f630877e 100644 --- a/sched/task/task_exit.c +++ b/sched/task/task_exit.c @@ -25,6 +25,7 @@ #include #include +#include #include "sched/sched.h" @@ -88,6 +89,13 @@ int nxtask_exit(void) dtcb = this_task(); #endif +#if CONFIG_TASK_NAME_SIZE > 0 + sinfo("%s pid=%d,TCB=%p\n", dtcb->name, +#else + sinfo("pid=%d,TCB=%p\n", +#endif + dtcb->pid, dtcb); + /* Update scheduler parameters */ nxsched_suspend_scheduler(dtcb); diff --git a/sched/task/task_exithook.c b/sched/task/task_exithook.c index ca1a7ef2daaaa..0a586f890806c 100644 --- a/sched/task/task_exithook.c +++ b/sched/task/task_exithook.c @@ -147,7 +147,7 @@ static inline void nxtask_sigchild(pid_t ppid, FAR struct tcb_s *ctcb, * this case, the child task group has been orphaned. */ - pgrp = group_findbypid(ppid); + pgrp = task_getgroup(ppid); if (!pgrp) { /* Set the task group ID to an invalid group ID. The dead parent @@ -174,7 +174,7 @@ static inline void nxtask_sigchild(pid_t ppid, FAR struct tcb_s *ctcb, * should generate SIGCHLD. */ - if (chgrp->tg_nmembers == 1) + if (sq_is_singular(&chgrp->tg_members)) { /* Mark that all of the threads in the task group have exited */ @@ -360,7 +360,9 @@ static inline void nxtask_exitwakeup(FAR struct tcb_s *tcb, int status) /* Is this the last thread in the group? */ - if (group->tg_nmembers == 1) +#ifndef CONFIG_DISABLE_PTHREAD + if (sq_is_singular(&group->tg_members)) +#endif { /* Yes.. Wakeup any tasks waiting for this task to exit */ diff --git a/sched/task/task_fork.c b/sched/task/task_fork.c index a10db44087c33..66854106c157c 100644 --- a/sched/task/task_fork.c +++ b/sched/task/task_fork.c @@ -142,9 +142,15 @@ FAR struct task_tcb_s *nxtask_setup_fork(start_t retaddr) goto errout; } + child->cmn.flags |= TCB_FLAG_FREE_TCB; + + /* Initialize the task join */ + + nxtask_joininit(&child->cmn); + /* Allocate a new task group with the same privileges as the parent */ - ret = group_allocate(child, ttype); + ret = group_initialize(child, ttype); if (ret < 0) { goto errout_with_tcb; @@ -205,8 +211,8 @@ FAR struct task_tcb_s *nxtask_setup_fork(start_t retaddr) /* Setup to pass parameters to the new task */ - ret = nxtask_setup_arguments(child, parent->group->tg_info->argv[0], - &parent->group->tg_info->argv[1]); + ret = nxtask_setup_arguments(child, parent->group->tg_info->ta_argv[0], + &parent->group->tg_info->ta_argv[1]); if (ret < OK) { goto errout_with_tcb; @@ -214,7 +220,7 @@ FAR struct task_tcb_s *nxtask_setup_fork(start_t retaddr) /* Now we have enough in place that we can join the group */ - group_initialize(child); + group_postinitialize(child); sinfo("parent=%p, returning child=%p\n", parent, child); return child; @@ -312,7 +318,7 @@ void nxtask_abort_fork(FAR struct task_tcb_s *child, int errcode) { /* The TCB was added to the active task list by nxtask_setup_scheduler() */ - dq_rem((FAR dq_entry_t *)child, &g_inactivetasks); + dq_rem((FAR dq_entry_t *)child, list_inactivetasks()); /* Release the TCB */ diff --git a/sched/task/task_getgroup.c b/sched/task/task_getgroup.c index dbf003d9ba4cd..cd79cc4f96f66 100644 --- a/sched/task/task_getgroup.c +++ b/sched/task/task_getgroup.c @@ -50,8 +50,7 @@ * * Assumptions: * Called during when signally tasks in a safe context. No special - * precautions should be required here. However, extra care is taken when - * accessing the global g_grouphead list. + * precautions should be required here. * ****************************************************************************/ diff --git a/sched/task/task_init.c b/sched/task/task_init.c index bce71184cd3c1..d67fd5a3618f2 100644 --- a/sched/task/task_init.c +++ b/sched/task/task_init.c @@ -103,7 +103,7 @@ int nxtask_init(FAR struct task_tcb_s *tcb, const char *name, int priority, #ifdef CONFIG_ARCH_ADDRENV /* Kernel threads do not own any address environment */ - if ((ttype & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_KERNEL) + if (ttype == TCB_FLAG_TTYPE_KERNEL) { tcb->cmn.addrenv_own = NULL; } @@ -111,13 +111,19 @@ int nxtask_init(FAR struct task_tcb_s *tcb, const char *name, int priority, /* Create a new task group */ - ret = group_allocate(tcb, tcb->cmn.flags); + ret = group_initialize(tcb, tcb->cmn.flags); if (ret < 0) { sched_trace_end(); return ret; } +#ifndef CONFIG_DISABLE_PTHREAD + /* Initialize the task join */ + + nxtask_joininit(&tcb->cmn); +#endif + /* Duplicate the parent tasks environment */ ret = env_dup(tcb->cmn.group, envp); @@ -179,7 +185,7 @@ int nxtask_init(FAR struct task_tcb_s *tcb, const char *name, int priority, /* Now we have enough in place that we can join the group */ - group_initialize(tcb); + group_postinitialize(tcb); sched_trace_end(); return ret; @@ -193,7 +199,7 @@ int nxtask_init(FAR struct task_tcb_s *tcb, const char *name, int priority, * user memory region that will be destroyed anyway (and the * address environment has probably already been destroyed at * this point.. so we would crash if we even tried it). But if - * this is a privileged group, when we still have to release the + * this is a privileged group, then we still have to release the * memory using the kernel allocator. */ @@ -204,6 +210,8 @@ int nxtask_init(FAR struct task_tcb_s *tcb, const char *name, int priority, } } + nxtask_joindestroy(&tcb->cmn); + group_leave(&tcb->cmn); sched_trace_end(); @@ -216,8 +224,8 @@ int nxtask_init(FAR struct task_tcb_s *tcb, const char *name, int priority, * Description: * Undo all operations on a TCB performed by task_init() and release the * TCB by calling kmm_free(). This is intended primarily to support - * error recovery operations after a successful call to task_init() such - * was when a subsequent call to task_activate fails. + * error recovery operations after a successful call to task_init() + * when a subsequent call to task_activate fails. * * Caution: Freeing of the TCB itself might be an unexpected side-effect. * @@ -235,7 +243,7 @@ void nxtask_uninit(FAR struct task_tcb_s *tcb) * nxtask_setup_scheduler(). */ - dq_rem((FAR dq_entry_t *)tcb, &g_inactivetasks); + dq_rem((FAR dq_entry_t *)tcb, list_inactivetasks()); /* Release all resources associated with the TCB... Including the TCB * itself. diff --git a/sched/task/task_join.c b/sched/task/task_join.c new file mode 100644 index 0000000000000..c6216fd1081c2 --- /dev/null +++ b/sched/task/task_join.c @@ -0,0 +1,64 @@ +/**************************************************************************** + * sched/task/task_join.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "sched/sched.h" +#include "group/group.h" +#include "pthread/pthread.h" + +#ifndef CONFIG_DISABLE_PTHREAD + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nxtask_joindestroy + ****************************************************************************/ + +void nxtask_joindestroy(FAR struct tcb_s *tcb) +{ + nxsem_destroy(&tcb->join_sem); +} + +/**************************************************************************** + * Name: nxtask_joininit + ****************************************************************************/ + +void nxtask_joininit(FAR struct tcb_s *tcb) +{ + sq_init(&tcb->join_queue); + nxsem_init(&tcb->join_sem, 0, 0); +} + +#endif /* !CONFIG_DISABLE_PTHREAD */ diff --git a/sched/task/task_posixspawn.c b/sched/task/task_posixspawn.c index b6000de462c9e..66d62e4ca633a 100644 --- a/sched/task/task_posixspawn.c +++ b/sched/task/task_posixspawn.c @@ -218,9 +218,6 @@ int posix_spawn(FAR pid_t *pid, FAR const char *path, FAR const posix_spawnattr_t *attr, FAR char * const argv[], FAR char * const envp[]) { - sinfo("pid=%p path=%s file_actions=%p attr=%p argv=%p\n", - pid, path, file_actions, attr, argv); - return nxposix_spawn_exec(pid, path, file_actions != NULL ? *file_actions : NULL, attr, argv, envp); diff --git a/sched/task/task_reparent.c b/sched/task/task_reparent.c index e6c725332e286..60662a1b311f5 100644 --- a/sched/task/task_reparent.c +++ b/sched/task/task_reparent.c @@ -94,7 +94,7 @@ int task_reparent(pid_t ppid, pid_t chpid) /* Get the old parent task's task group (ogrp) */ - ogrp = group_findbypid(opid); + ogrp = task_getgroup(opid); if (!ogrp) { ret = -ESRCH; @@ -111,7 +111,7 @@ int task_reparent(pid_t ppid, pid_t chpid) /* Get the grandparent task's task group (pgrp) */ ppid = ogrp->tg_ppid; - pgrp = group_findbypid(ppid); + pgrp = task_getgroup(ppid); } else { diff --git a/sched/task/task_restart.c b/sched/task/task_restart.c index cb722f44fe57b..a32d77ca52f9a 100644 --- a/sched/task/task_restart.c +++ b/sched/task/task_restart.c @@ -177,7 +177,7 @@ static int nxtask_restart(pid_t pid) /* Add the task to the inactive task list */ - dq_addfirst((FAR dq_entry_t *)tcb, &g_inactivetasks); + dq_addfirst((FAR dq_entry_t *)tcb, list_inactivetasks()); tcb->cmn.task_state = TSTATE_TASK_INACTIVE; #ifdef CONFIG_SMP diff --git a/sched/task/task_setup.c b/sched/task/task_setup.c index b41a37899c35a..61a8b615643b1 100644 --- a/sched/task/task_setup.c +++ b/sched/task/task_setup.c @@ -88,12 +88,12 @@ static int nxtask_assign_pid(FAR struct tcb_s *tcb) int i; /* NOTE: - * ERROR means that the g_pidhash[] table is completely full. + * ERROR means that the nxsched_pidhash()[] table is completely full. * We cannot allow another task to be started. */ /* Protect the following operation with a critical section - * because g_pidhash is accessed from an interrupt context + * because nxsched_pidhash() is accessed from an interrupt context */ irqstate_t flags = enter_critical_section(); @@ -104,8 +104,8 @@ static int nxtask_assign_pid(FAR struct tcb_s *tcb) /* Get the next process ID candidate */ - next_pid = g_lastpid + 1; - for (i = 0; i < g_npidhash; i++) + next_pid = nxsched_lastpid() + 1; + for (i = 0; i < nxsched_npidhash(); i++) { /* Verify that the next_pid is in the valid range */ @@ -120,13 +120,13 @@ static int nxtask_assign_pid(FAR struct tcb_s *tcb) /* Check if there is a (potential) duplicate of this pid */ - if (!g_pidhash[hash_ndx]) + if (!nxsched_pidhash()[hash_ndx]) { /* Assign this PID to the task */ - g_pidhash[hash_ndx] = tcb; + nxsched_pidhash()[hash_ndx] = tcb; tcb->pid = next_pid; - g_lastpid = next_pid; + nxsched_lastpid() = next_pid; leave_critical_section(flags); return OK; @@ -135,35 +135,35 @@ static int nxtask_assign_pid(FAR struct tcb_s *tcb) next_pid++; } - /* If we get here, then the g_pidhash[] table is completely full. - * We will alloc new space and copy original g_pidhash to it to + /* If we get here, then the nxsched_pidhash()[] table is completely full. + * We will alloc new space and copy original nxsched_pidhash() to it to * expand space. */ - pidhash = kmm_zalloc(g_npidhash * 2 * sizeof(*pidhash)); + pidhash = kmm_zalloc(nxsched_npidhash() * 2 * sizeof(*pidhash)); if (pidhash == NULL) { leave_critical_section(flags); return -ENOMEM; } - g_npidhash *= 2; + nxsched_npidhash() *= 2; /* All original pid and hash_ndx are mismatch, * so we need to rebuild their relationship */ - for (i = 0; i < g_npidhash / 2; i++) + for (i = 0; i < nxsched_npidhash() / 2; i++) { - hash_ndx = PIDHASH(g_pidhash[i]->pid); + hash_ndx = PIDHASH(nxsched_pidhash()[i]->pid); DEBUGASSERT(pidhash[hash_ndx] == NULL); - pidhash[hash_ndx] = g_pidhash[i]; + pidhash[hash_ndx] = nxsched_pidhash()[i]; } /* Release resource for original g_pidhash, using new g_pidhash */ - temp = g_pidhash; - g_pidhash = pidhash; + temp = nxsched_pidhash(); + nxsched_pidhash() = pidhash; kmm_free(temp); /* Let's try every allowable pid again */ @@ -452,7 +452,7 @@ static int nxthread_setup_scheduler(FAR struct tcb_s *tcb, int priority, /* Add the task to the inactive task list */ sched_lock(); - dq_addfirst((FAR dq_entry_t *)tcb, &g_inactivetasks); + dq_addfirst((FAR dq_entry_t *)tcb, list_inactivetasks()); tcb->task_state = TSTATE_TASK_INACTIVE; sched_unlock(); } @@ -629,7 +629,9 @@ static int nxtask_setup_stackargs(FAR struct task_tcb_s *tcb, */ stackargv[argc + 1] = NULL; - tcb->cmn.group->tg_info->argv = stackargv; + + tcb->cmn.group->tg_info->ta_argc = argc; + tcb->cmn.group->tg_info->ta_argv = stackargv; return OK; } diff --git a/sched/task/task_spawn.c b/sched/task/task_spawn.c index 9554fdaad2480..c2f972341c012 100644 --- a/sched/task/task_spawn.c +++ b/sched/task/task_spawn.c @@ -99,7 +99,7 @@ static int nxtask_spawn_create(FAR const char *name, int priority, /* Setup the task type */ - tcb->cmn.flags = TCB_FLAG_TTYPE_TASK; + tcb->cmn.flags = TCB_FLAG_TTYPE_TASK | TCB_FLAG_FREE_TCB; /* Initialize the task */ diff --git a/sched/task/task_start.c b/sched/task/task_start.c index 42ac5f0b27773..8d6bf9e909a91 100644 --- a/sched/task/task_start.c +++ b/sched/task/task_start.c @@ -39,16 +39,6 @@ #include "signal/signal.h" #include "task/task.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* This is an artificial limit to detect error conditions where an argv[] - * list is not properly terminated. - */ - -#define MAX_START_ARGS 256 - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -75,67 +65,55 @@ void nxtask_start(void) { - FAR struct task_tcb_s *tcb = (FAR struct task_tcb_s *)this_task(); + FAR struct tcb_s *tcb = this_task(); +#ifdef CONFIG_SCHED_STARTHOOK + FAR struct task_tcb_s *ttcb = (FAR struct task_tcb_s *)tcb; +#endif int exitcode = EXIT_FAILURE; int argc; - DEBUGASSERT((tcb->cmn.flags & TCB_FLAG_TTYPE_MASK) != \ + DEBUGASSERT((tcb->flags & TCB_FLAG_TTYPE_MASK) != \ TCB_FLAG_TTYPE_PTHREAD); #ifdef CONFIG_SIG_DEFAULT - if ((tcb->cmn.flags & TCB_FLAG_TTYPE_MASK) != TCB_FLAG_TTYPE_KERNEL) + if ((tcb->flags & TCB_FLAG_TTYPE_MASK) != TCB_FLAG_TTYPE_KERNEL) { /* Set up default signal actions for NON-kernel thread */ - nxsig_default_initialize(&tcb->cmn); + nxsig_default_initialize(tcb); } #endif /* Execute the start hook if one has been registered */ #ifdef CONFIG_SCHED_STARTHOOK - if (tcb->starthook != NULL) + if (ttcb->starthook != NULL) { - tcb->starthook(tcb->starthookarg); + ttcb->starthook(ttcb->starthookarg); } #endif - /* Count how many non-null arguments we are passing. The first non-null - * argument terminates the list . - */ + /* Add program name */ - argc = 1; - while (tcb->cmn.group->tg_info->argv[argc]) - { - /* Increment the number of args. Here is a sanity check to - * prevent running away with an unterminated argv[] list. - * MAX_START_ARGS should be sufficiently large that this never - * happens in normal usage. - */ - - if (++argc > MAX_START_ARGS) - { - _exit(EXIT_FAILURE); - } - } + argc = tcb->group->tg_info->ta_argc + 1; /* Call the 'main' entry point passing argc and argv. In the kernel build * this has to be handled differently if we are starting a user-space task; * we have to switch to user-mode before calling the task. */ - if ((tcb->cmn.flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_KERNEL) + if ((tcb->flags & TCB_FLAG_TTYPE_MASK) == TCB_FLAG_TTYPE_KERNEL) { - exitcode = tcb->cmn.entry.main(argc, tcb->cmn.group->tg_info->argv); + exitcode = tcb->entry.main(argc, tcb->group->tg_info->ta_argv); } else { #ifdef CONFIG_BUILD_FLAT - nxtask_startup(tcb->cmn.entry.main, argc, - tcb->cmn.group->tg_info->argv); + nxtask_startup(tcb->entry.main, argc, + tcb->group->tg_info->ta_argv); #else - up_task_start(tcb->cmn.entry.main, argc, - tcb->cmn.group->tg_info->argv); + up_task_start(tcb->entry.main, argc, + tcb->group->tg_info->ta_argv); #endif } diff --git a/sched/timer/timer_initialize.c b/sched/timer/timer_initialize.c index 4db056ae1cb72..fe8a8d3190599 100644 --- a/sched/timer/timer_initialize.c +++ b/sched/timer/timer_initialize.c @@ -167,11 +167,11 @@ FAR struct posix_timer_s *timer_gethandle(timer_t timerid) { FAR struct posix_timer_s *timer = NULL; FAR sq_entry_t *entry; - irqstate_t intflags; + irqstate_t flags; if (timerid != NULL) { - intflags = enter_critical_section(); + flags = spin_lock_irqsave(NULL); sq_for_every(&g_alloctimers, entry) { @@ -182,7 +182,7 @@ FAR struct posix_timer_s *timer_gethandle(timer_t timerid) } } - leave_critical_section(intflags); + spin_unlock_irqrestore(NULL, flags); } return timer; diff --git a/sched/tls/task_initinfo.c b/sched/tls/task_initinfo.c index 15f2380ecb261..7818e8f0390fe 100644 --- a/sched/tls/task_initinfo.c +++ b/sched/tls/task_initinfo.c @@ -52,8 +52,7 @@ static void task_init_stream(FAR struct streamlist *list) /* Initialize the list access mutex */ nxmutex_init(&list->sl_lock); - list->sl_head = NULL; - list->sl_tail = NULL; + sq_init(&list->sl_queue); /* Initialize stdin, stdout and stderr stream */ @@ -119,11 +118,15 @@ int task_init_info(FAR struct task_group_s *group) /* Allocate task info for group */ +#ifdef CONFIG_MM_KERNEL_HEAP info = group_zalloc(group, sizeof(struct task_info_s)); if (info == NULL) { return -ENOMEM; } +#else + info = &group->tg_info_; +#endif /* Initialize user space mutex */ diff --git a/sched/tls/task_uninitinfo.c b/sched/tls/task_uninitinfo.c index 9e7ae8b152418..9c3cffa025bb3 100644 --- a/sched/tls/task_uninitinfo.c +++ b/sched/tls/task_uninitinfo.c @@ -22,9 +22,11 @@ * Included Files ****************************************************************************/ +#include #include #include #include +#include #include "tls.h" @@ -47,6 +49,8 @@ static void task_uninit_stream(FAR struct task_group_s *group) { FAR struct streamlist *list; FAR struct file_struct *stream; + FAR sq_entry_t *curr; + FAR sq_entry_t *next; DEBUGASSERT(group && group->tg_info); list = &group->tg_info->ta_streamlist; @@ -66,11 +70,9 @@ static void task_uninit_stream(FAR struct task_group_s *group) /* Release each stream in the list */ - list->sl_tail = NULL; - while (list->sl_head != NULL) + sq_for_every_safe(&list->sl_queue, curr, next) { - stream = list->sl_head; - list->sl_head = stream->fs_next; + stream = container_of(curr, struct file_struct, fs_entry); #ifndef CONFIG_STDIO_DISABLE_BUFFERING /* Destroy the mutex that protects the IO buffer */ @@ -142,5 +144,7 @@ void task_uninit_info(FAR struct task_group_s *group) #endif /* CONFIG_FILE_STREAM */ nxmutex_destroy(&info->ta_lock); +#ifdef CONFIG_MM_KERNEL_HEAP group_free(group, info); +#endif } diff --git a/sched/tls/tls.h b/sched/tls/tls.h index 474085ba0f178..913761b74d88f 100644 --- a/sched/tls/tls.h +++ b/sched/tls/tls.h @@ -25,6 +25,7 @@ * Included Files ****************************************************************************/ +#include #include #include diff --git a/sched/wqueue/kwork_cancel.c b/sched/wqueue/kwork_cancel.c index 332d3fa90a5db..66d08222272d0 100644 --- a/sched/wqueue/kwork_cancel.c +++ b/sched/wqueue/kwork_cancel.c @@ -148,7 +148,7 @@ int work_cancel(int qid, FAR struct work_s *work) { /* Cancel high priority work */ - return work_qcancel((FAR struct kwork_wqueue_s *)&g_hpwork, + return work_qcancel((FAR struct kwork_wqueue_s *)&hpwork(), -1, work); } else @@ -158,7 +158,7 @@ int work_cancel(int qid, FAR struct work_s *work) { /* Cancel low priority work */ - return work_qcancel((FAR struct kwork_wqueue_s *)&g_lpwork, + return work_qcancel((FAR struct kwork_wqueue_s *)&lpwork(), -1, work); } else @@ -196,7 +196,7 @@ int work_cancel_sync(int qid, FAR struct work_s *work) { /* Cancel high priority work */ - return work_qcancel((FAR struct kwork_wqueue_s *)&g_hpwork, + return work_qcancel((FAR struct kwork_wqueue_s *)&hpwork(), CONFIG_SCHED_HPNTHREADS, work); } else @@ -206,7 +206,7 @@ int work_cancel_sync(int qid, FAR struct work_s *work) { /* Cancel low priority work */ - return work_qcancel((FAR struct kwork_wqueue_s *)&g_lpwork, + return work_qcancel((FAR struct kwork_wqueue_s *)&lpwork(), CONFIG_SCHED_LPNTHREADS, work); } else diff --git a/sched/wqueue/kwork_inherit.c b/sched/wqueue/kwork_inherit.c index 05fdc59845617..920fcc094c829 100644 --- a/sched/wqueue/kwork_inherit.c +++ b/sched/wqueue/kwork_inherit.c @@ -219,16 +219,14 @@ void lpwork_boostpriority(uint8_t reqprio) /* Prevent context switches until we get the priorities right */ flags = enter_critical_section(); - sched_lock(); /* Adjust the priority of every worker thread */ for (wndx = 0; wndx < CONFIG_SCHED_LPNTHREADS; wndx++) { - lpwork_boostworker(g_lpwork.worker[wndx].pid, reqprio); + lpwork_boostworker(lpwork().worker[wndx].pid, reqprio); } - sched_unlock(); leave_critical_section(flags); } @@ -265,16 +263,14 @@ void lpwork_restorepriority(uint8_t reqprio) /* Prevent context switches until we get the priorities right */ flags = enter_critical_section(); - sched_lock(); /* Adjust the priority of every worker thread */ for (wndx = 0; wndx < CONFIG_SCHED_LPNTHREADS; wndx++) { - lpwork_restoreworker(g_lpwork.worker[wndx].pid, reqprio); + lpwork_restoreworker(lpwork().worker[wndx].pid, reqprio); } - sched_unlock(); leave_critical_section(flags); } diff --git a/sched/wqueue/kwork_queue.c b/sched/wqueue/kwork_queue.c index f850cad0a8ccc..4b60398d32e8b 100644 --- a/sched/wqueue/kwork_queue.c +++ b/sched/wqueue/kwork_queue.c @@ -67,7 +67,7 @@ static void hp_work_timer_expiry(wdparm_t arg) { irqstate_t flags = enter_critical_section(); - queue_work(g_hpwork, arg); + queue_work(hpwork(), arg); leave_critical_section(flags); } #endif @@ -80,7 +80,7 @@ static void hp_work_timer_expiry(wdparm_t arg) static void lp_work_timer_expiry(wdparm_t arg) { irqstate_t flags = enter_critical_section(); - queue_work(g_lpwork, arg); + queue_work(lpwork(), arg); leave_critical_section(flags); } #endif @@ -152,7 +152,7 @@ int work_queue(int qid, FAR struct work_s *work, worker_t worker, if (!delay) { - queue_work(g_hpwork, work); + queue_work(hpwork(), work); } else { @@ -169,7 +169,7 @@ int work_queue(int qid, FAR struct work_s *work, worker_t worker, if (!delay) { - queue_work(g_lpwork, work); + queue_work(lpwork(), work); } else { diff --git a/sched/wqueue/kwork_thread.c b/sched/wqueue/kwork_thread.c index a0a9ea540622b..879202c007c82 100644 --- a/sched/wqueue/kwork_thread.c +++ b/sched/wqueue/kwork_thread.c @@ -305,7 +305,7 @@ void work_foreach(int qid, work_foreach_t handler, FAR void *arg) #ifdef CONFIG_SCHED_HPWORK if (qid == HPWORK) { - wqueue = (FAR struct kwork_wqueue_s *)&g_hpwork; + wqueue = (FAR struct kwork_wqueue_s *)&hpwork(); nthread = CONFIG_SCHED_HPNTHREADS; } else @@ -313,7 +313,7 @@ void work_foreach(int qid, work_foreach_t handler, FAR void *arg) #ifdef CONFIG_SCHED_LPWORK if (qid == LPWORK) { - wqueue = (FAR struct kwork_wqueue_s *)&g_lpwork; + wqueue = (FAR struct kwork_wqueue_s *)&lpwork(); nthread = CONFIG_SCHED_LPNTHREADS; } else @@ -352,7 +352,7 @@ int work_start_highpri(void) return work_thread_create(HPWORKNAME, CONFIG_SCHED_HPWORKPRIORITY, CONFIG_SCHED_HPWORKSTACKSIZE, CONFIG_SCHED_HPNTHREADS, - (FAR struct kwork_wqueue_s *)&g_hpwork); + (FAR struct kwork_wqueue_s *)&hpwork()); } #endif /* CONFIG_SCHED_HPWORK */ @@ -380,7 +380,7 @@ int work_start_lowpri(void) return work_thread_create(LPWORKNAME, CONFIG_SCHED_LPWORKPRIORITY, CONFIG_SCHED_LPWORKSTACKSIZE, CONFIG_SCHED_LPNTHREADS, - (FAR struct kwork_wqueue_s *)&g_lpwork); + (FAR struct kwork_wqueue_s *)&lpwork()); } #endif /* CONFIG_SCHED_LPWORK */ diff --git a/sched/wqueue/wqueue.h b/sched/wqueue/wqueue.h index 66f2ed5a4c6ce..58b23f1112456 100644 --- a/sched/wqueue/wqueue.h +++ b/sched/wqueue/wqueue.h @@ -105,12 +105,16 @@ struct lp_wqueue_s #ifdef CONFIG_SCHED_HPWORK /* The state of the kernel mode, high priority work queue. */ +#define hpwork() g_hpwork + extern struct hp_wqueue_s g_hpwork; #endif #ifdef CONFIG_SCHED_LPWORK /* The state of the kernel mode, low priority work queue(s). */ +#define lpwork() g_lpwork + extern struct lp_wqueue_s g_lpwork; #endif diff --git a/syscall/CMakeLists.txt b/syscall/CMakeLists.txt index 53fdbb1768793..5ad019828e284 100644 --- a/syscall/CMakeLists.txt +++ b/syscall/CMakeLists.txt @@ -22,6 +22,14 @@ file(STRINGS syscall.csv SYSCALLS) list(TRANSFORM SYSCALLS REPLACE "^\"([^,]+)\",.+" "\\1") list(TRANSFORM SYSCALLS APPEND ".c") +# generate the host tool + +add_custom_target( + mksyscall + COMMAND cmake -B ${CMAKE_BINARY_DIR}/bin -S ${CMAKE_SOURCE_DIR}/tools && cmake + --build ${CMAKE_BINARY_DIR}/bin --target mksyscall + SOURCES ${CMAKE_SOURCE_DIR}/tools/mksyscall.c) + if(CONFIG_LIB_SYSCALL) add_subdirectory(proxies) add_subdirectory(stubs) diff --git a/syscall/proxies/CMakeLists.txt b/syscall/proxies/CMakeLists.txt index a36a285284871..80f9dec52d1ed 100644 --- a/syscall/proxies/CMakeLists.txt +++ b/syscall/proxies/CMakeLists.txt @@ -27,7 +27,7 @@ add_custom_command( COMMAND ${CMAKE_BINARY_DIR}/bin/mksyscall -p ${CMAKE_CURRENT_LIST_DIR}/../syscall.csv WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - DEPENDS nuttx_host_tools) + DEPENDS mksyscall) # add sources to target target_sources(proxies PRIVATE ${SYSCALLS}) diff --git a/syscall/stubs/CMakeLists.txt b/syscall/stubs/CMakeLists.txt index b3ce6d8b896cc..69341b42039b3 100644 --- a/syscall/stubs/CMakeLists.txt +++ b/syscall/stubs/CMakeLists.txt @@ -27,7 +27,7 @@ add_custom_command( COMMAND ${CMAKE_BINARY_DIR}/bin/mksyscall -s ${CMAKE_CURRENT_LIST_DIR}/../syscall.csv WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR} - DEPENDS nuttx_host_tools) + DEPENDS mksyscall) # add sources to target target_sources(stubs PRIVATE ${SYSCALLS}) diff --git a/syscall/syscall.csv b/syscall/syscall.csv index adb54f8c72c51..8a17ba0cba2e3 100644 --- a/syscall/syscall.csv +++ b/syscall/syscall.csv @@ -154,7 +154,7 @@ "setgid","unistd.h","defined(CONFIG_SCHED_USER_IDENTITY)","int","gid_t" "sethostname","unistd.h","","int","FAR const char *","size_t" "setitimer","sys/time.h","!defined(CONFIG_DISABLE_POSIX_TIMERS)","int","int","FAR const struct itimerval *","FAR struct itimerval *" -"setsockopt","sys/socket.h","defined(CONFIG_NET)","int","int","int","int","FAR const void *","socklen_t" +"setsockopt","sys/socket.h","defined(CONFIG_NET) && defined(CONFIG_NET_SOCKOPTS)","int","int","int","int","FAR const void *","socklen_t" "settimeofday","sys/time.h","","int","FAR const struct timeval *","FAR const struct timezone *" "setuid","unistd.h","defined(CONFIG_SCHED_USER_IDENTITY)","int","uid_t" "shm_open","sys/mman.h","defined(CONFIG_FS_SHMFS)","int","FAR const char *","int","mode_t" diff --git a/tools/Config.mk b/tools/Config.mk index 92c753b8f64f2..a49dc6a6d61b8 100644 --- a/tools/Config.mk +++ b/tools/Config.mk @@ -578,6 +578,11 @@ ifeq ($(CONFIG_STACK_USAGE),y) EXTRA += *.su endif +ifeq ($(CONFIG_ARCH_TOOLCHAIN_TASKING),y) + EXTRA += *.d + EXTRA += *.src +endif + ifeq ($(CONFIG_WINDOWS_NATIVE),y) define CLEAN $(Q) if exist *$(OBJEXT) (del /f /q *$(OBJEXT)) @@ -659,6 +664,10 @@ else endif endif +ifeq ($(CONFIG_LIBCXXABI),y) +ARCHXXINCLUDES += ${INCSYSDIR_PREFIX}$(TOPDIR)$(DELIM)include$(DELIM)libcxxabi +endif + ifeq ($(CONFIG_LIBM_NEWLIB),y) ARCHINCLUDES += ${INCSYSDIR_PREFIX}$(TOPDIR)$(DELIM)include$(DELIM)newlib ARCHXXINCLUDES += ${INCSYSDIR_PREFIX}$(TOPDIR)$(DELIM)include$(DELIM)newlib diff --git a/tools/Export.mk b/tools/Export.mk index 33032423fef49..ec7fa5c2e2c46 100644 --- a/tools/Export.mk +++ b/tools/Export.mk @@ -80,6 +80,31 @@ endif @echo "OBJDUMP=\"$(OBJDUMP)\"" >> $(EXPORTDIR)/makeinfo.sh @echo "OBJEXT=\"$(OBJEXT)\"" >> $(EXPORTDIR)/makeinfo.sh @echo "STRIP=\"$(STRIP)\"" >> $(EXPORTDIR)/makeinfo.sh + @echo "NUTTX_ARCH=\"$(CONFIG_ARCH)\"" >> $(EXPORTDIR)/makeinfo.sh +ifdef CONFIG_ARCH_CHIP + @echo "NUTTX_ARCH_CHIP=\"$(CONFIG_ARCH_CHIP)\"" >> $(EXPORTDIR)/makeinfo.sh +else + @echo "NUTTX_ARCH_CHIP=\"$(ARCH_CHIP_CUSTOM_NAME)\"" >> $(EXPORTDIR)/makeinfo.sh +endif +ifdef CONFIG_ARCH_BOARD + @echo "NUTTX_BOARD=\"$(CONFIG_ARCH_BOARD)\"" >> $(EXPORTDIR)/makeinfo.sh +else + @echo "NUTTX_BOARD=\"$(CONFIG_ARCH_BOARD_CUSTOM_NAME)\"" >> $(EXPORTDIR)/makeinfo.sh +endif +ifdef CONFIG_BUILD_FLAT + @echo "NUTTX_BUILD=\"flat\"" >> $(EXPORTDIR)/makeinfo.sh +endif +ifdef CONFIG_BUILD_PROTECTED + @echo "NUTTX_BUILD=\"protected\"" >> $(EXPORTDIR)/makeinfo.sh +endif +ifdef CONFIG_BUILD_KERNEL + @echo "NUTTX_BUILD=\"kernel\"" >> $(EXPORTDIR)/makeinfo.sh +endif +ifdef CONFIG_LIBCXX + @echo "NUTTX_CXX=\"libcxx\"" >> $(EXPORTDIR)/makeinfo.sh +else + @echo "NUTTX_CXX=\"cxx\"" >> $(EXPORTDIR)/makeinfo.sh +endif $(Q) chmod 755 $(EXPORTDIR)/makeinfo.sh clean: diff --git a/tools/Unix.mk b/tools/Unix.mk index bd8384c03acf3..0597afc6e3a87 100644 --- a/tools/Unix.mk +++ b/tools/Unix.mk @@ -24,12 +24,6 @@ ifeq ($(V),) MAKE := $(MAKE) -s --no-print-directory endif -# Build any necessary tools needed early in the build. -# incdir - Is needed immediately by all Make.defs file. - -DUMMY := ${shell $(MAKE) -C tools -f Makefile.host incdir \ - INCDIR="$(TOPDIR)/tools/incdir.sh"} - include $(TOPDIR)/Make.defs # GIT directory present @@ -222,6 +216,13 @@ include/setjmp.h: include/nuttx/lib/setjmp.h $(Q) cp -f include/nuttx/lib/setjmp.h include/setjmp.h endif +# Targets used to generate compiler-specific include paths +# Build this tools needed early in the build +# so we define it as a dependency of `context` target + +tools/incdir$(HOSTEXEEXT): + $(Q) $(MAKE) -C tools -f Makefile.host incdir INCDIR="$(TOPDIR)/tools/incdir.sh" + # Targets used to build include/nuttx/version.h. Creation of version.h is # part of the overall NuttX configuration sequence. Notice that the # tools/mkversion tool is built and used to create include/nuttx/version.h @@ -440,7 +441,7 @@ endif CONTEXTDIRS_DEPS = $(patsubst %,%/.context,$(CONTEXTDIRS)) -context: include/nuttx/config.h include/nuttx/version.h .dirlinks $(CONTEXTDIRS_DEPS) | staging +context: tools/incdir$(HOSTEXEEXT) include/nuttx/config.h include/nuttx/version.h .dirlinks $(CONTEXTDIRS_DEPS) | staging staging: $(Q) mkdir -p $@ @@ -739,7 +740,8 @@ savedefconfig: apps_preconfig # that the archiver is 'ar' export: $(NUTTXLIBS) - $(Q) MAKE="${MAKE}" $(MKEXPORT) $(MKEXPORT_ARGS) -l "$(EXPORTLIBS)" + $(Q) ZIG="${ZIG}" ZIGFLAGS="${ZIGFLAGS}" MAKE="${MAKE}" \ + $(MKEXPORT) $(MKEXPORT_ARGS) -l "$(EXPORTLIBS)" # General housekeeping targets: dependencies, cleaning, etc. # diff --git a/tools/Win.mk b/tools/Win.mk index bf14b01cafa27..05d54b7ace766 100644 --- a/tools/Win.mk +++ b/tools/Win.mk @@ -22,12 +22,6 @@ export SHELL=cmd export TOPDIR := ${shell echo %CD%} -# Build any necessary tools needed early in the build. -# incdir - Is needed immediately by all Make.defs file. - -DUMMY := ${shell $(MAKE) -C tools -f Makefile.host incdir \ - INCDIR="$(TOPDIR)\tools\incdir.bat"} - include $(TOPDIR)\Make.defs -include $(TOPDIR)\.version @@ -210,6 +204,13 @@ else include\setjmp.h: endif +# Targets used to generate compiler-specific include paths +# Build this tools needed early in the build +# so we define it as a dependency of `context` target + +tools\incdir$(HOSTEXEEXT): + $(Q) $(MAKE) -C tools -f Makefile.host incdir INCDIR="$(TOPDIR)\tools\incdir.bat" + # Targets used to build include\nuttx\version.h. Creation of version.h is # part of the overall NuttX configuration sequence. Notice that the # tools\mkversion tool is built and used to create include\nuttx\version.h @@ -424,7 +425,7 @@ endif CONTEXTDIRS_DEPS = $(patsubst %,%\.context,$(CONTEXTDIRS)) -context: include\nuttx\config.h include\nuttx\version.h $(CONTEXTDIRS_DEPS) .dirlinks | staging +context: tools\incdir$(HOSTEXEEXT) include\nuttx\config.h include\nuttx\version.h $(CONTEXTDIRS_DEPS) .dirlinks | staging ifeq ($(NEED_MATH_H),y) context: include\math.h diff --git a/tools/Zig.defs b/tools/Zig.defs index 870d7372fb19c..b1de13117e737 100644 --- a/tools/Zig.defs +++ b/tools/Zig.defs @@ -39,4 +39,6 @@ endif # Convert cortex-xxx/sifive-exx to cortex_xxx/sifive_exx +ifneq ($(LLVM_CPUTYPE),) ZIGFLAGS += -mcpu $(subst -,_,$(LLVM_CPUTYPE)) +endif diff --git a/tools/apps-or-nuttx-Make.defs b/tools/apps-or-nuttx-Make.defs new file mode 100644 index 0000000000000..1639b649fb93b --- /dev/null +++ b/tools/apps-or-nuttx-Make.defs @@ -0,0 +1,36 @@ +############################################################################ +# apps-or-nuttx-Make.defs +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +-include $(TOPDIR)/.config +# CONFIG_APPS_DIR can be over-ridden from the command line or in the .config file. +# The default value of CONFIG_APPS_DIR is ../apps. Ultimately, the application +# will be built if APPDIR is defined. APPDIR will be defined if a directory containing +# a Makefile is found at the path provided by CONFIG_APPS_DIR + +ifeq ($(CONFIG_APPS_DIR),) +CONFIG_APPS_DIR = $(TOPDIR)/../apps +endif +APPDIR := $(realpath ${shell if [ -r $(CONFIG_APPS_DIR)/Makefile ]; then echo "$(CONFIG_APPS_DIR)"; fi}) + +ifeq ($(APPDIR),) +include $(TOPDIR)/Make.defs +else +include $(APPDIR)/Make.defs +endif diff --git a/tools/checkpatch.sh b/tools/checkpatch.sh index 620889582aaa6..17b46ed92dfae 100755 --- a/tools/checkpatch.sh +++ b/tools/checkpatch.sh @@ -101,7 +101,7 @@ check_file() { elif ! cmake-format --check $@ 2>&1; then if [ $cmake_warning_once == 0 ]; then echo -e "\ncmake-format check failed, run following command to update the style:" - echo -e " $ cmake-format -o \n" + echo -e " $ cmake-format -o \n" cmake-format --check $@ 2>&1 cmake_warning_once=1 fi diff --git a/tools/ci/cibuild.sh b/tools/ci/cibuild.sh index c2120f6dcb574..a9c7e8d494ec3 100755 --- a/tools/ci/cibuild.sh +++ b/tools/ci/cibuild.sh @@ -1,509 +1,92 @@ #!/usr/bin/env bash - -# Licensed to the Apache Software Foundation (ASF) under one -# or more contributor license agreements. See the NOTICE file -# distributed with this work for additional information -# regarding copyright ownership. The ASF licenses this file -# to you under the Apache License, Version 2.0 (the -# "License"); you may not use this file except in compliance -# with the License. You may obtain a copy of the License at +############################################################################ +# tools/ci/cibuild.sh +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at # -# http://www.apache.org/licenses/LICENSE-2.0 +# http://www.apache.org/licenses/LICENSE-2.0 # -# Unless required by applicable law or agreed to in writing, -# software distributed under the License is distributed on an -# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY -# KIND, either express or implied. See the License for the -# specific language governing permissions and limitations +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations # under the License. - -# Prerequisites for macOS -# - Xcode (cc, etc) -# - homebrew -# - autoconf -# - wget - +# +############################################################################ set -e set -o xtrace -WD=$(cd "$(dirname "$0")" && pwd) -WORKSPACE=$(cd "${WD}"/../../../ && pwd -P) -nuttx=${WORKSPACE}/nuttx -apps=${WORKSPACE}/apps -tools=${WORKSPACE}/tools -os=$(uname -s) -EXTRA_PATH= - -function add_path { - PATH=$1:${PATH} - EXTRA_PATH=$1:${EXTRA_PATH} -} - -function arm-clang-toolchain { - add_path "${tools}"/clang-arm-none-eabi/bin - - if [ ! -f "${tools}/clang-arm-none-eabi/bin/clang" ]; then - local flavor - case ${os} in - Linux) - flavor=Linux - ;; - esac - cd "${tools}" - curl -O -L -s https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-17.0.1/LLVMEmbeddedToolchainForArm-17.0.1-${flavor}-x86_64.tar.xz - xz -d LLVMEmbeddedToolchainForArm-17.0.1-${flavor}.tar.xz - mv LLVMEmbeddedToolchainForArm-17.0.1 clang-arm-none-eabi - cp /usr/bin/clang-extdef-mapping-10 clang-arm-none-eabi/bin/clang-extdef-mapping - rm LLVMEmbeddedToolchainForArm-17.0.1-${flavor}.tar.xz - fi - - command clang --version -} - -function arm-gcc-toolchain { - add_path "${tools}"/gcc-arm-none-eabi/bin - - if [ ! -f "${tools}/gcc-arm-none-eabi/bin/arm-none-eabi-gcc" ]; then - local flavor - case ${os} in - Darwin) - flavor=-darwin - ;; - Linux) - flavor= - ;; - esac - cd "${tools}" - wget --quiet https://developer.arm.com/-/media/Files/downloads/gnu/13.2.Rel1/binrel/arm-gnu-toolchain-13.2.Rel1${flavor}-x86_64-arm-none-eabi.tar.xz - xz -d arm-gnu-toolchain-13.2.Rel1${flavor}-x86_64-arm-none-eabi.tar.xz - tar xf arm-gnu-toolchain-13.2.Rel1${flavor}-x86_64-arm-none-eabi.tar - mv arm-gnu-toolchain-13.2.Rel1${flavor}-x86_64-arm-none-eabi gcc-arm-none-eabi - rm arm-gnu-toolchain-13.2.Rel1${flavor}-x86_64-arm-none-eabi.tar - fi - - command arm-none-eabi-gcc --version -} - -function arm64-gcc-toolchain { - add_path "${tools}"/gcc-aarch64-none-elf/bin - - if [ ! -f "${tools}/gcc-aarch64-none-elf/bin/aarch64-none-elf-gcc" ]; then - local flavor - case ${os} in - Darwin) - flavor=-darwin - ;; - Linux) - flavor= - ;; - esac - cd "${tools}" - wget --quiet https://developer.arm.com/-/media/Files/downloads/gnu/13.2.Rel1/binrel/arm-gnu-toolchain-13.2.Rel1${flavor}-x86_64-aarch64-none-elf.tar.xz - xz -d arm-gnu-toolchain-13.2.Rel1${flavor}-x86_64-aarch64-none-elf.tar.xz - tar xf arm-gnu-toolchain-13.2.Rel1${flavor}-x86_64-aarch64-none-elf.tar - mv arm-gnu-toolchain-13.2.Rel1${flavor}-x86_64-aarch64-none-elf gcc-aarch64-none-elf - rm arm-gnu-toolchain-13.2.Rel1${flavor}-x86_64-aarch64-none-elf.tar - fi - - command aarch64-none-elf-gcc --version -} - -function avr-gcc-toolchain { - if ! type avr-gcc &> /dev/null; then - case ${os} in - Darwin) - brew tap osx-cross/avr - brew install avr-gcc - ;; - Linux) - apt-get install -y avr-libc gcc-avr - ;; - esac - fi - - command avr-gcc --version -} - -function binutils { - mkdir -p "${tools}"/bintools/bin - add_path "${tools}"/bintools/bin - - if ! type objcopy &> /dev/null; then - case ${os} in - Darwin) - brew install binutils - # It is possible we cached prebuilt but did brew install so recreate - # symlink if it exists - rm -f "${tools}"/bintools/bin/objcopy - ln -s /usr/local/opt/binutils/bin/objcopy "${tools}"/bintools/bin/objcopy - ;; - esac - fi - - command objcopy --version -} -function bloaty { - add_path "${tools}"/bloaty/bin - - if [ ! -f "${tools}/bloaty/bin/bloaty" ]; then - git clone --branch main https://github.com/google/bloaty "${tools}"/bloaty-src - cd "${tools}"/bloaty-src - # Due to issues with latest MacOS versions use pinned commit. - # https://github.com/google/bloaty/pull/326 - git checkout 52948c107c8f81045e7f9223ec02706b19cfa882 - mkdir -p "${tools}"/bloaty - cmake -D BLOATY_PREFER_SYSTEM_CAPSTONE=NO -DCMAKE_SYSTEM_PREFIX_PATH="${tools}"/bloaty - make install -j 6 - cd "${tools}" - rm -rf bloaty-src - fi - - command bloaty --version -} +CID=$(cd "$(dirname "$0")" && pwd) +CIWORKSPACE=$(cd "${CID}"/../../../ && pwd -P) +CIPLAT=${CIWORKSPACE}/nuttx/tools/ci/platforms +nuttx=${CIWORKSPACE}/nuttx +apps=${CIWORKSPACE}/apps -function c-cache { - add_path "${tools}"/ccache/bin - - if ! type ccache &> /dev/null; then - case ${os} in - Darwin) - brew install ccache - ;; - Linux) - cd "${tools}"; - wget https://github.com/ccache/ccache/releases/download/v3.7.7/ccache-3.7.7.tar.gz - tar zxf ccache-3.7.7.tar.gz - cd ccache-3.7.7; ./configure --prefix="${tools}"/ccache; make; make install - cd "${tools}"; rm -rf ccache-3.7.7; rm ccache-3.7.7.tar.gz - ;; - esac - fi - - command ccache --version -} - -function clang-tidy { - if ! type clang-tidy &> /dev/null; then - case ${os} in - Linux) - apt-get install -y clang clang-tidy - ;; - esac - fi - - command clang-tidy --version -} - -function elf-toolchain { - if ! type x86_64-elf-gcc &> /dev/null; then - case ${os} in - Darwin) - brew install x86_64-elf-gcc - ;; - esac - fi - - command x86_64-elf-gcc --version -} - -function util-linux { - if ! type flock &> /dev/null; then - case ${os} in - Darwin) - brew tap discoteq/discoteq - brew install flock - ;; - Linux) - apt-get install -y util-linux - ;; - esac - fi - - command flock --version -} - -function gen-romfs { - if ! type genromfs &> /dev/null; then - case ${os} in - Darwin) - brew tap PX4/px4 - brew install genromfs - ;; - Linux) - apt-get install -y genromfs - ;; - esac - fi -} - -function gperf { - add_path "${tools}"/gperf/bin - - if [ ! -f "${tools}/gperf/bin/gperf" ]; then - cd "${tools}" - wget --quiet http://ftp.gnu.org/pub/gnu/gperf/gperf-3.1.tar.gz - tar zxf gperf-3.1.tar.gz - cd "${tools}"/gperf-3.1 - ./configure --prefix="${tools}"/gperf; make; make install - cd "${tools}" - rm -rf gperf-3.1; rm gperf-3.1.tar.gz - fi - - command gperf --version -} - -function kconfig-frontends { - add_path "${tools}"/kconfig-frontends/bin +os=$(uname -s) +if [ -f /etc/os-release ]; then + osname=$(grep "^ID=" /etc/os-release | cut -d'=' -f2 | tr -d '"') +else + osname=${os} +fi - if [ ! -f "${tools}/kconfig-frontends/bin/kconfig-conf" ]; then - git clone https://bitbucket.org/nuttx/tools.git "${tools}"/nuttx-tools - cd "${tools}"/nuttx-tools/kconfig-frontends - ./configure --prefix="${tools}"/kconfig-frontends \ - --disable-kconfig --disable-nconf --disable-qconf \ - --disable-gconf --disable-mconf --disable-static \ - --disable-shared --disable-L10n - # Avoid "aclocal/automake missing" errors - touch aclocal.m4 Makefile.in - make install - cd "${tools}" - rm -rf nuttx-tools - fi +function to_do { + echo "" + echo "NuttX TODO: $1" + echo "The $1 platform does not appear to have been added to this project." + echo "" + exit 1 } -function mips-gcc-toolchain { - if [ ! -d "${tools}/pinguino-compilers" ]; then - cd "${tools}" - git clone https://github.com/PinguinoIDE/pinguino-compilers - fi +function install_tools { + export NUTTXTOOLS=${CIWORKSPACE}/tools + mkdir -p "${NUTTXTOOLS}" - case ${os} in + case ${osname} in + alpine) + to_do "alpine" + ;; + arch) + to_do "arch" + ;; + CYGWIN*) + to_do "CYGWIN" + ;; + debian) + to_do "debian" + ;; + fedora) + to_do "fedora" + ;; + freebsd) + to_do "freebsd" + ;; Darwin) - add_path "${tools}"/pinguino-compilers/macosx/p32/bin - command mips-elf-gcc --version + "${CIPLAT}"/darwin.sh ;; Linux) - add_path "${tools}"/pinguino-compilers/linux64/p32/bin - command p32-gcc --version + "${CIPLAT}"/linux.sh + ;; + manjaro) + to_do "manjaro" + ;; + msys2) + "${CIPLAT}"/msys2.sh + ;; + ubuntu) + "${CIPLAT}"/ubuntu.sh + ;; + *) + to_do "unknown" ;; esac -} - -function python-tools { - # Python User Env - export PIP_USER=yes - export PYTHONUSERBASE=${tools}/pylocal - add_path "${PYTHONUSERBASE}"/bin - - # workaround for Cython issue - # https://github.com/yaml/pyyaml/pull/702#issuecomment-1638930830 - pip3 install "Cython<3.0" - git clone https://github.com/yaml/pyyaml.git && \ - cd pyyaml && \ - git checkout release/5.4.1 && \ - sed -i.bak 's/Cython/Cython<3.0/g' pyproject.toml && \ - python setup.py sdist && \ - pip3 install --pre dist/PyYAML-5.4.1.tar.gz - cd .. - - pip3 install \ - cmake-format \ - CodeChecker \ - cvt2utf \ - cxxfilt \ - esptool==4.5.1 \ - imgtool==1.9.0 \ - kconfiglib \ - pexpect==4.8.0 \ - pyelftools \ - pyserial==3.5 \ - pytest==6.2.5 \ - pytest-json==0.4.0 \ - pytest-ordering==0.6 \ - pytest-repeat==0.9.1 -} - -function riscv-gcc-toolchain { - add_path "${tools}"/riscv-none-elf-gcc/bin - - if [ ! -f "${tools}/riscv-none-elf-gcc/bin/riscv-none-elf-gcc" ]; then - local flavor - case ${os} in - Darwin) - flavor=darwin-x64 - ;; - Linux) - flavor=linux-x64 - ;; - esac - cd "${tools}" - wget --quiet https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-${flavor}.tar.gz - tar zxf xpack-riscv-none-elf-gcc-13.2.0-2-${flavor}.tar.gz - mv xpack-riscv-none-elf-gcc-13.2.0-2 riscv-none-elf-gcc - rm xpack-riscv-none-elf-gcc-13.2.0-2-${flavor}.tar.gz - fi - - command riscv-none-elf-gcc --version -} - -function rust { - mkdir -p "${tools}"/rust/bin - add_path "${tools}"/rust/bin - - if ! type rustc &> /dev/null; then - case ${os} in - Darwin) - brew install rust - ;; - Linux) - # Currently Debian installed rustc doesn't support 2021 edition. - export CARGO_HOME=${tools}/rust - curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s -- -y - ;; - esac - fi - - command rustc --version -} - -function rx-gcc-toolchain { - add_path "${tools}"/renesas-toolchain/rx-elf-gcc/bin - - if [ ! -f "${tools}/renesas-toolchain/rx-elf-gcc/bin/rx-elf-gcc" ]; then - case ${os} in - Linux) - # Download toolchain source code - # RX toolchain is built from source code. Once prebuilt RX toolchain is made available, the below code snippet can be removed. - mkdir -p "${tools}"/renesas-tools/rx/source; cd "${tools}"/renesas-tools/rx/source - wget --quiet https://gcc-renesas.com/downloads/d.php?f=rx/binutils/4.8.4.201803-gnurx/rx_binutils2.24_2018Q3.tar.gz \ - -O rx_binutils2.24_2018Q3.tar.gz - tar zxf rx_binutils2.24_2018Q3.tar.gz - wget --quiet https://gcc-renesas.com/downloads/d.php?f=rx/gcc/4.8.4.201803-gnurx/rx_gcc_4.8.4_2018Q3.tar.gz \ - -O rx_gcc_4.8.4_2018Q3.tar.gz - tar zxf rx_gcc_4.8.4_2018Q3.tar.gz - wget --quiet https://gcc-renesas.com/downloads/d.php?f=rx/newlib/4.8.4.201803-gnurx/rx_newlib2.2.0_2018Q3.tar.gz \ - -O rx_newlib2.2.0_2018Q3.tar.gz - tar zxf rx_newlib2.2.0_2018Q3.tar.gz - - # Install binutils - cd "${tools}"/renesas-tools/rx/source/binutils; chmod +x ./configure ./mkinstalldirs - mkdir -p "${tools}"/renesas-tools/rx/build/binutils; cd "${tools}"/renesas-tools/rx/build/binutils - "${tools}"/renesas-tools/rx/source/binutils/configure --target=rx-elf --prefix="${tools}"/renesas-toolchain/rx-elf-gcc \ - --disable-werror - make; make install - - # Install gcc - cd "${tools}"/renesas-tools/rx/source/gcc - chmod +x ./contrib/download_prerequisites ./configure ./move-if-change ./libgcc/mkheader.sh - ./contrib/download_prerequisites - sed -i '1s/^/@documentencoding ISO-8859-1\n/' ./gcc/doc/gcc.texi - sed -i 's/@tex/\n&/g' ./gcc/doc/gcc.texi && sed -i 's/@end tex/\n&/g' ./gcc/doc/gcc.texi - mkdir -p "${tools}"/renesas-tools/rx/build/gcc; cd "${tools}"/renesas-tools/rx/build/gcc - "${tools}"/renesas-tools/rx/source/gcc/configure --target=rx-elf --prefix="${tools}"/renesas-toolchain/rx-elf-gcc \ - --disable-shared --disable-multilib --disable-libssp --disable-libstdcxx-pch --disable-werror --enable-lto \ - --enable-gold --with-pkgversion=GCC_Build_1.02 --with-newlib --enable-languages=c - make; make install - - # Install newlib - cd "${tools}"/renesas-tools/rx/source/newlib; chmod +x ./configure - mkdir -p "${tools}"/renesas-tools/rx/build/newlib; cd "${tools}"/renesas-tools/rx/build/newlib - "${tools}"/renesas-tools/rx/source/newlib/configure --target=rx-elf --prefix="${tools}"/renesas-toolchain/rx-elf-gcc - make; make install - rm -rf "${tools}"/renesas-tools/ - ;; - esac - fi - - command rx-elf-gcc --version -} - -function sparc-gcc-toolchain { - add_path "${tools}"/sparc-gaisler-elf-gcc/bin - - if [ ! -f "${tools}/sparc-gaisler-elf-gcc/bin/sparc-gaisler-elf-gcc" ]; then - case ${os} in - Linux) - cd "${tools}" - wget --quiet https://www.gaisler.com/anonftp/bcc2/bin/bcc-2.1.0-gcc-linux64.tar.xz - xz -d bcc-2.1.0-gcc-linux64.tar.xz - tar xf bcc-2.1.0-gcc-linux64.tar - mv bcc-2.1.0-gcc sparc-gaisler-elf-gcc - rm bcc-2.1.0-gcc-linux64.tar - ;; - esac - fi - - command sparc-gaisler-elf-gcc --version -} - -function xtensa-esp32-gcc-toolchain { - add_path "${tools}"/xtensa-esp32-elf/bin - - if [ ! -f "${tools}/xtensa-esp32-elf/bin/xtensa-esp32-elf-gcc" ]; then - cd "${tools}" - case ${os} in - Darwin) - wget --quiet https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32-elf-12.2.0_20230208-x86_64-apple-darwin.tar.xz - xz -d xtensa-esp32-elf-12.2.0_20230208-x86_64-apple-darwin.tar.xz - tar xf xtensa-esp32-elf-12.2.0_20230208-x86_64-apple-darwin.tar - rm xtensa-esp32-elf-12.2.0_20230208-x86_64-apple-darwin.tar - ;; - Linux) - wget --quiet https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/xtensa-esp32-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz - xz -d xtensa-esp32-elf-12.2.0_20230208-x86_64-linux-gnu.tar.xz - tar xf xtensa-esp32-elf-12.2.0_20230208-x86_64-linux-gnu.tar - rm xtensa-esp32-elf-12.2.0_20230208-x86_64-linux-gnu.tar - ;; - esac - fi - - command xtensa-esp32-elf-gcc --version -} - -function u-boot-tools { - if ! type mkimage &> /dev/null; then - case ${os} in - Darwin) - brew install u-boot-tools - ;; - Linux) - apt-get install -y u-boot-tools - ;; - esac - fi -} -function wasi-sdk { - add_path "${tools}"/wamrc - - if [ ! -f "${tools}/wasi-sdk/bin/clang" ]; then - cd "${tools}" - mkdir wamrc - - case ${os} in - Darwin) - wget --quiet https://github.com/WebAssembly/wasi-sdk/releases/download/wasi-sdk-19/wasi-sdk-19.0-macos.tar.gz - tar xzf wasi-sdk-19.0-macos.tar.gz - mv wasi-sdk-19.0 wasi-sdk - cd wamrc - wget --quiet https://github.com/bytecodealliance/wasm-micro-runtime/releases/download/WAMR-1.1.2/wamrc-1.1.2-x86_64-macos-latest.tar.gz - tar xzf wamrc-1.1.2-x86_64-macos-latest.tar.gz - ;; - Linux) - wget --quiet https://github.com/WebAssembly/wasi-sdk/releases/download/wasi-sdk-19/wasi-sdk-19.0-linux.tar.gz - tar xzf wasi-sdk-19.0-linux.tar.gz - mv wasi-sdk-19.0 wasi-sdk - cd wamrc - wget --quiet https://github.com/bytecodealliance/wasm-micro-runtime/releases/download/WAMR-1.1.2/wamrc-1.1.2-x86_64-ubuntu-20.04.tar.gz - tar xzf wamrc-1.1.2-x86_64-ubuntu-20.04.tar.gz - ;; - esac - fi - - export WASI_SDK_PATH="${tools}/wasi-sdk" - - command ${WASI_SDK_PATH}/bin/clang --version - command wamrc --version + source "${CIWORKSPACE}"/tools/env.sh } function usage { @@ -516,38 +99,14 @@ function usage { echo " -s setup repos" echo " -c enable ccache" echo " -* support all options in testbuild.sh" - echo " -h will show this help test and terminate" + echo " -h will show this help text and terminate" echo " select testlist file" echo "" exit 1 } function enable_ccache { - export CCACHE_DIR="${tools}"/ccache -} - -function setup_links { - mkdir -p "${tools}"/ccache/bin/ - ln -sf "$(which ccache)" "${tools}"/ccache/bin/aarch64-none-elf-gcc - ln -sf "$(which ccache)" "${tools}"/ccache/bin/aarch64-none-elf-g++ - ln -sf "$(which ccache)" "${tools}"/ccache/bin/arm-none-eabi-gcc - ln -sf "$(which ccache)" "${tools}"/ccache/bin/arm-none-eabi-g++ - ln -sf "$(which ccache)" "${tools}"/ccache/bin/avr-gcc - ln -sf "$(which ccache)" "${tools}"/ccache/bin/avr-g++ - ln -sf "$(which ccache)" "${tools}"/ccache/bin/cc - ln -sf "$(which ccache)" "${tools}"/ccache/bin/c++ - ln -sf "$(which ccache)" "${tools}"/ccache/bin/clang - ln -sf "$(which ccache)" "${tools}"/ccache/bin/clang++ - ln -sf "$(which ccache)" "${tools}"/ccache/bin/gcc - ln -sf "$(which ccache)" "${tools}"/ccache/bin/g++ - ln -sf "$(which ccache)" "${tools}"/ccache/bin/p32-gcc - ln -sf "$(which ccache)" "${tools}"/ccache/bin/riscv64-unknown-elf-gcc - ln -sf "$(which ccache)" "${tools}"/ccache/bin/riscv64-unknown-elf-g++ - ln -sf "$(which ccache)" "${tools}"/ccache/bin/sparc-gaisler-elf-gcc - ln -sf "$(which ccache)" "${tools}"/ccache/bin/sparc-gaisler-elf-g++ - ln -sf "$(which ccache)" "${tools}"/ccache/bin/x86_64-elf-gcc - ln -sf "$(which ccache)" "${tools}"/ccache/bin/x86_64-elf-g++ - ln -sf "$(which ccache)" "${tools}"/ccache/bin/xtensa-esp32-elf-gcc + export CCACHE_DIR="${CIWORKSPACE}"/tools/ccache } function setup_repos { @@ -570,49 +129,13 @@ function setup_repos { popd } -function install_tools { - mkdir -p "${tools}" - -case ${os} in - Darwin) - install="arm-gcc-toolchain arm64-gcc-toolchain avr-gcc-toolchain binutils bloaty elf-toolchain gen-romfs gperf kconfig-frontends mips-gcc-toolchain python-tools riscv-gcc-toolchain rust xtensa-esp32-gcc-toolchain u-boot-tools util-linux wasi-sdk c-cache" - mkdir -p "${tools}"/homebrew - export HOMEBREW_CACHE=${tools}/homebrew - # https://github.com/apache/arrow/issues/15025 - rm -f /usr/local/bin/2to3* || : - rm -f /usr/local/bin/idle3* || : - rm -f /usr/local/bin/pydoc3* || : - rm -f /usr/local/bin/python3* || : - rm -f /usr/local/bin/python3-config || : - # same for openssl - rm -f /usr/local/bin/openssl || : - ;; - Linux) - install="arm-clang-toolchain arm-gcc-toolchain arm64-gcc-toolchain avr-gcc-toolchain binutils bloaty clang-tidy gen-romfs gperf kconfig-frontends mips-gcc-toolchain python-tools riscv-gcc-toolchain rust rx-gcc-toolchain sparc-gcc-toolchain xtensa-esp32-gcc-toolchain u-boot-tools util-linux wasi-sdk c-cache" - ;; -esac - - pushd . - for func in ${install}; do - ${func} - done - popd - - setup_links - echo PATH="${EXTRA_PATH}"/"${PATH}" > "${tools}"/env.sh -} - function run_builds { local ncpus - - case ${os} in - Darwin) - ncpus=$(sysctl -n hw.ncpu) - ;; - Linux) - ncpus=$(grep -c ^processor /proc/cpuinfo) - ;; - esac + if [ "X$osname" == "XDarwin" ]; then + ncpus=$(sysctl -n hw.ncpu) + else + ncpus=$(grep -c ^processor /proc/cpuinfo) + fi options+="-j ${ncpus}" @@ -621,6 +144,7 @@ function run_builds { done if [ -d "${CCACHE_DIR}" ]; then + # Print a summary of configuration and statistics counters ccache -s fi } diff --git a/tools/ci/cirun.sh b/tools/ci/cirun.sh index 7073de5a12aa0..73f240c2f5c2f 100755 --- a/tools/ci/cirun.sh +++ b/tools/ci/cirun.sh @@ -18,10 +18,15 @@ if [ "$BOARD" == "sim" ]; then mark="common or ${BOARD}" else if [ "${config:$((-2))}" == "64" ]; then - BOARD="${BOARD}64" + BOARD="${BOARD}64" + fi + if [ "$BOARD" == "rv-virt" ]; then + target="qemu" + mark="qemu or rv_virt" + else + target="qemu" + mark=$target fi - target="qemu" - mark=$target fi core=$target @@ -35,6 +40,8 @@ ret="$?" find ${nuttx}/tools/ci/testrun -name '__pycache__' |xargs rm -rf find ${nuttx}/tools/ci/testrun -name '.pytest_cache' |xargs rm -rf rm -rf ${logs} +rm -f ${nuttx}/fatfs.img + echo $ret exit $ret diff --git a/tools/ci/docker/linux/Dockerfile b/tools/ci/docker/linux/Dockerfile index 85a2da3e0a924..5aecc256e92ac 100644 --- a/tools/ci/docker/linux/Dockerfile +++ b/tools/ci/docker/linux/Dockerfile @@ -267,7 +267,7 @@ RUN mkdir -p cmake && \ RUN dpkg --add-architecture i386 # This is used for the final images so make sure to not store apt cache # Note: xtensa-esp32-elf-gdb is linked to libpython2.7 -RUN apt-get update -qq && DEBIAN_FRONTEND="noninteractive" apt-get install -y -qq --no-install-recommends \ +RUN apt-get update -qq && DEBIAN_FRONTEND="noninteractive" TZ=Etc/UTC apt-get install -y -qq --no-install-recommends \ -o APT::Immediate-Configure=0 \ avr-libc \ ccache \ @@ -306,6 +306,8 @@ RUN apt-get update -qq && DEBIAN_FRONTEND="noninteractive" apt-get install -y -q unzip \ wget \ xxd \ + file \ + tclsh \ && rm -rf /var/lib/apt/lists/* # Set GCC-12 as Default compiler @@ -343,10 +345,11 @@ RUN pip3 install pytest==6.2.5 RUN pip3 install pytest-json==0.4.0 RUN pip3 install pytest-ordering==0.6 RUN pip3 install pytest-repeat==0.9.1 -# Install lark stringcase and jinja2 for matter build +# Install lark stringcase jinja2 and coloredlogs for matter build RUN pip3 install lark RUN pip3 install stringcase RUN pip3 install jinja2 +RUN pip3 install coloredlogs # Upgrade nodejs to the latest version RUN npm install -g n && n stable && hash -r diff --git a/tools/ci/platforms/darwin.sh b/tools/ci/platforms/darwin.sh new file mode 100755 index 0000000000000..eaa7905c7ad3c --- /dev/null +++ b/tools/ci/platforms/darwin.sh @@ -0,0 +1,361 @@ +#!/usr/bin/env sh +############################################################################ +# tools/ci/platforms/darwin.sh +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Darwin + +# Prerequisites for macOS +# - Xcode (cc, etc) +# - homebrew +# - autoconf +# - wget + +set -e +set -o xtrace + +add_path() { + PATH=$1:${PATH} +} + +arm_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/gcc-arm-none-eabi/bin + + if [ ! -f "${NUTTXTOOLS}/gcc-arm-none-eabi/bin/arm-none-eabi-gcc" ]; then + local basefile + basefile=arm-gnu-toolchain-13.2.rel1-darwin-x86_64-arm-none-eabi + cd "${NUTTXTOOLS}" + wget --quiet https://developer.arm.com/-/media/Files/downloads/gnu/13.2.rel1/binrel/${basefile}.tar.xz + xz -d ${basefile}.tar.xz + tar xf ${basefile}.tar + mv ${basefile} gcc-arm-none-eabi + rm ${basefile}.tar + fi + + command arm-none-eabi-gcc --version +} + +arm64_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/gcc-aarch64-none-elf/bin + + if [ ! -f "${NUTTXTOOLS}/gcc-aarch64-none-elf/bin/aarch64-none-elf-gcc" ]; then + local basefile + basefile=arm-gnu-toolchain-13.2.Rel1-darwin-x86_64-aarch64-none-elf + cd "${NUTTXTOOLS}" + # Download the latest ARM64 GCC toolchain prebuilt by ARM + wget --quiet https://developer.arm.com/-/media/Files/downloads/gnu/13.2.Rel1/binrel/${basefile}.tar.xz + xz -d ${basefile}.tar.xz + tar xf ${basefile}.tar + mv ${basefile} gcc-aarch64-none-elf + rm ${basefile}.tar + fi + + command aarch64-none-elf-gcc --version +} + +avr_gcc_toolchain() { + if ! type avr-gcc > /dev/null 2>&1; then + brew tap osx-cross/avr + brew install avr-gcc + fi + + command avr-gcc --version +} + +binutils() { + mkdir -p "${NUTTXTOOLS}"/bintools/bin + add_path "${NUTTXTOOLS}"/bintools/bin + + if ! type objcopy > /dev/null 2>&1; then + brew install binutils + # It is possible we cached prebuilt but did brew install so recreate + # symlink if it exists + rm -f "${NUTTXTOOLS}"/bintools/bin/objcopy + ln -s /usr/local/opt/binutils/bin/objcopy "${NUTTXTOOLS}"/bintools/bin/objcopy + fi + + command objcopy --version +} + +bloaty() { + add_path "${NUTTXTOOLS}"/bloaty/bin + + if [ ! -f "${NUTTXTOOLS}/bloaty/bin/bloaty" ]; then + git clone --branch main https://github.com/google/bloaty "${NUTTXTOOLS}"/bloaty-src + cd "${NUTTXTOOLS}"/bloaty-src + # Due to issues with latest MacOS versions use pinned commit. + # https://github.com/google/bloaty/pull/326 + git checkout 52948c107c8f81045e7f9223ec02706b19cfa882 + mkdir -p "${NUTTXTOOLS}"/bloaty + cmake -B build/bloaty -D BLOATY_PREFER_SYSTEM_CAPSTONE=NO -D CMAKE_INSTALL_PREFIX="${NUTTXTOOLS}"/bloaty + cmake --build build/bloaty + cmake --build build/bloaty --target install + cd "${NUTTXTOOLS}" + rm -rf bloaty-src + ls -a "${NUTTXTOOLS}"/bloaty + fi + + command bloaty --version +} + +c_cache() { + add_path "${NUTTXTOOLS}"/ccache/bin + + if ! type ccache > /dev/null 2>&1; then + brew install ccache + fi + setup_links + command ccache --version +} + +elf_toolchain() { + if ! type x86_64-elf-gcc > /dev/null 2>&1; then + brew install x86_64-elf-gcc + fi + + command x86_64-elf-gcc --version +} + +gen_romfs() { + if ! type genromfs > /dev/null 2>&1; then + brew tap PX4/px4 + brew install genromfs + fi +} + +gperf() { + add_path "${NUTTXTOOLS}"/gperf/bin + + if [ ! -f "${NUTTXTOOLS}/gperf/bin/gperf" ]; then + local basefile + basefile=gperf-3.1 + + cd "${NUTTXTOOLS}" + wget --quiet http://ftp.gnu.org/pub/gnu/gperf/${basefile}.tar.gz + tar zxf ${basefile}.tar.gz + cd "${NUTTXTOOLS}"/${basefile} + ./configure --prefix="${NUTTXTOOLS}"/gperf; make; make install + cd "${NUTTXTOOLS}" + rm -rf ${basefile}; rm ${basefile}.tar.gz + fi + + command gperf --version +} + +kconfig_frontends() { + add_path "${NUTTXTOOLS}"/kconfig-frontends/bin + + if [ ! -f "${NUTTXTOOLS}/kconfig-frontends/bin/kconfig-conf" ]; then + git clone https://bitbucket.org/nuttx/tools.git "${NUTTXTOOLS}"/nuttx-tools + cd "${NUTTXTOOLS}"/nuttx-tools/kconfig-frontends + ./configure --prefix="${NUTTXTOOLS}"/kconfig-frontends \ + --disable-kconfig --disable-nconf --disable-qconf \ + --disable-gconf --disable-mconf --disable-static \ + --disable-shared --disable-L10n + # Avoid "aclocal/automake missing" errors + touch aclocal.m4 Makefile.in + make install + cd "${NUTTXTOOLS}" + rm -rf nuttx-tools + fi +} + +mips_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/pinguino-compilers/macosx/p32/bin + + if [ ! -d "${NUTTXTOOLS}/pinguino-compilers" ]; then + cd "${NUTTXTOOLS}" + git clone https://github.com/PinguinoIDE/pinguino-compilers + fi + + command mips-elf-gcc --version +} + +python_tools() { + # Python User Env + export PIP_USER=yes + export PYTHONUSERBASE=${NUTTXTOOLS}/pylocal + echo "export PIP_USER=yes" >> "${NUTTXTOOLS}"/env.sh + echo "export PYTHONUSERBASE=${NUTTXTOOLS}/pylocal" >> "${NUTTXTOOLS}"/env.sh + add_path "${PYTHONUSERBASE}"/bin + + # workaround for Cython issue + # https://github.com/yaml/pyyaml/pull/702#issuecomment-1638930830 + pip3 install "Cython<3.0" + git clone https://github.com/yaml/pyyaml.git && \ + cd pyyaml && \ + git checkout release/5.4.1 && \ + sed -i.bak 's/Cython/Cython<3.0/g' pyproject.toml && \ + python setup.py sdist && \ + pip3 install --pre dist/PyYAML-5.4.1.tar.gz + cd .. + rm -rf pyyaml + + pip3 install \ + cmake-format \ + cvt2utf \ + cxxfilt \ + esptool==4.5.1 \ + imgtool==1.9.0 \ + kconfiglib \ + pexpect==4.8.0 \ + pyelftools \ + pyserial==3.5 \ + pytest==6.2.5 \ + pytest-json==0.4.0 \ + pytest-ordering==0.6 \ + pytest-repeat==0.9.1 +} + +riscv_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/riscv-none-elf-gcc/bin + + if [ ! -f "${NUTTXTOOLS}/riscv-none-elf-gcc/bin/riscv-none-elf-gcc" ]; then + local basefile + basefile=xpack-riscv-none-elf-gcc-13.2.0-2-darwin-x64 + cd "${NUTTXTOOLS}" + # Download the latest RISCV GCC toolchain prebuilt by xPack + wget --quiet https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/${basefile}.tar.gz + tar zxf ${basefile}.tar.gz + mv xpack-riscv-none-elf-gcc-13.2.0-2 riscv-none-elf-gcc + rm ${basefile}.tar.gz + fi + command riscv-none-elf-gcc --version +} + +rust() { + if ! type rustc > /dev/null 2>&1; then + brew install rust + fi + + command rustc --version +} + +xtensa_esp32_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/xtensa-esp32-elf/bin + + if [ ! -f "${NUTTXTOOLS}/xtensa-esp32-elf/bin/xtensa-esp32-elf-gcc" ]; then + local basefile + basefile=xtensa-esp32-elf-12.2.0_20230208-x86_64-apple-darwin + cd "${NUTTXTOOLS}" + wget --quiet https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/${basefile}.tar.xz + xz -d ${basefile}.tar.xz + tar xf ${basefile}.tar + rm ${basefile}.tar + fi + + command xtensa-esp32-elf-gcc --version +} + +u_boot_tools() { + if ! type mkimage > /dev/null 2>&1; then + brew install u-boot-tools + fi +} + +util_linux() { + if ! type flock > /dev/null 2>&1; then + brew tap discoteq/discoteq + brew install flock + fi + + command flock --version +} + +wasi_sdk() { + add_path "${NUTTXTOOLS}"/wamrc + + if [ ! -f "${NUTTXTOOLS}/wamrc/wasi-sdk/bin/clang" ]; then + local wasibasefile + local wasmbasefile + wasibasefile=wasi-sdk-19.0-macos + wasmbasefile=wamrc-1.1.2-x86_64-macos-latest + cd "${NUTTXTOOLS}" + mkdir -p wamrc + wget --quiet https://github.com/WebAssembly/wasi-sdk/releases/download/wasi-sdk-19/${wasibasefile}.tar.gz + tar xzf ${wasibasefile}.tar.gz + mv wasi-sdk-19.0 wasi-sdk + rm ${wasibasefile}.tar.gz + cd wamrc + wget --quiet https://github.com/bytecodealliance/wasm-micro-runtime/releases/download/WAMR-1.1.2/${wasmbasefile}.tar.gz + tar xzf ${wasmbasefile}.tar.gz + rm ${wasmbasefile}.tar.gz + fi + + export WASI_SDK_PATH="${NUTTXTOOLS}/wasi-sdk" + echo "export WASI_SDK_PATH=${NUTTXTOOLS}/wasi-sdk" >> "${NUTTXTOOLS}"/env.sh + + command "${WASI_SDK_PATH}"/bin/clang --version + command wamrc --version +} + +setup_links() { + # Configure ccache + mkdir -p "${NUTTXTOOLS}"/ccache/bin/ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/aarch64-none-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/aarch64-none-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/arm-none-eabi-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/arm-none-eabi-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/avr-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/avr-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/cc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/c++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/clang + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/clang++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/p32-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/riscv64-unknown-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/riscv64-unknown-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/sparc-gaisler-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/sparc-gaisler-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/x86_64-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/x86_64-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/xtensa-esp32-elf-gcc +} + +install_build_tools() { + mkdir -p "${NUTTXTOOLS}" + echo "#!/usr/bin/env sh" > "${NUTTXTOOLS}"/env.sh + + install="arm_gcc_toolchain arm64_gcc_toolchain avr_gcc_toolchain binutils bloaty elf_toolchain gen_romfs gperf kconfig_frontends mips_gcc_toolchain python_tools riscv_gcc_toolchain rust xtensa_esp32_gcc_toolchain u_boot_tools util_linux wasi_sdk c_cache" + + mkdir -p "${NUTTXTOOLS}"/homebrew + export HOMEBREW_CACHE=${NUTTXTOOLS}/homebrew + echo "export HOMEBREW_CACHE=${NUTTXTOOLS}/homebrew" >> "${NUTTXTOOLS}"/env.sh + # https://github.com/apache/arrow/issues/15025 + rm -f /usr/local/bin/2to3* || : + rm -f /usr/local/bin/idle3* || : + rm -f /usr/local/bin/pydoc3* || : + rm -f /usr/local/bin/python3* || : + rm -f /usr/local/bin/python3-config || : + # same for openssl + rm -f /usr/local/bin/openssl || : + + oldpath=$(cd . && pwd -P) + for func in ${install}; do + ${func} + done + cd "${oldpath}" + + echo "PATH=${PATH}" >> "${NUTTXTOOLS}"/env.sh + echo "export PATH" >> "${NUTTXTOOLS}"/env.sh +} + +install_build_tools diff --git a/tools/ci/platforms/linux.sh b/tools/ci/platforms/linux.sh new file mode 100755 index 0000000000000..b78ca2c2bdc83 --- /dev/null +++ b/tools/ci/platforms/linux.sh @@ -0,0 +1,380 @@ +#!/usr/bin/env bash +############################################################################ +# tools/ci/platforms/linux.sh +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Linux + +set -e +set -o xtrace + +add_path() { + PATH=$1:${PATH} +} + +arm_clang_toolchain() { + add_path "${NUTTXTOOLS}"/clang-arm-none-eabi/bin + + if [ ! -f "${NUTTXTOOLS}/clang-arm-none-eabi/bin/clang" ]; then + local basefile + basefile=LLVMEmbeddedToolchainForArm-17.0.1-Linux-x86_64 + cd "${NUTTXTOOLS}" + # Download the latest ARM clang toolchain prebuilt by ARM + curl -O -L -s https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-17.0.1/${basefile}.tar.xz + xz -d ${basefile}.tar.xz + tar xf ${basefile}.tar + mv ${basefile} clang-arm-none-eabi + rm ${basefile}.tar + fi + + command clang --version +} + +arm_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/gcc-arm-none-eabi/bin + + if [ ! -f "${NUTTXTOOLS}/gcc-arm-none-eabi/bin/arm-none-eabi-gcc" ]; then + local basefile + basefile=arm-gnu-toolchain-13.2.Rel1-x86_64-arm-none-eabi + cd "${NUTTXTOOLS}" + # Download the latest ARM GCC toolchain prebuilt by ARM + wget --quiet https://developer.arm.com/-/media/Files/downloads/gnu/13.2.rel1/binrel/${basefile}.tar.xz + xz -d ${basefile}.tar.xz + tar xf ${basefile}.tar + mv ${basefile} gcc-arm-none-eabi + rm ${basefile}.tar + fi + + command arm-none-eabi-gcc --version +} + +arm64_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/gcc-aarch64-none-elf/bin + + if [ ! -f "${NUTTXTOOLS}/gcc-aarch64-none-elf/bin/aarch64-none-elf-gcc" ]; then + local basefile + basefile=arm-gnu-toolchain-13.2.Rel1-x86_64-aarch64-none-elf + cd "${NUTTXTOOLS}" + # Download the latest ARM64 GCC toolchain prebuilt by ARM + wget --quiet https://developer.arm.com/-/media/Files/downloads/gnu/13.2.Rel1/binrel/${basefile}.tar.xz + xz -d ${basefile}.tar.xz + tar xf ${basefile}.tar + mv ${basefile} gcc-aarch64-none-elf + rm ${basefile}.tar + fi + + command aarch64-none-elf-gcc --version +} + +bloaty() { + add_path "${NUTTXTOOLS}"/bloaty/bin + + if [ ! -f "${NUTTXTOOLS}/bloaty/bin/bloaty" ]; then + git clone --depth 1 --branch v1.1 https://github.com/google/bloaty "${NUTTXTOOLS}"/bloaty-src + mkdir -p "${NUTTXTOOLS}"/bloaty + cd "${NUTTXTOOLS}"/bloaty-src + cmake -B build -DCMAKE_INSTALL_PREFIX="${NUTTXTOOLS}"/bloaty + cmake --build build + cmake --build build --target install + cd "${NUTTXTOOLS}" + rm -rf bloaty-src + ls -a "${NUTTXTOOLS}"/bloaty + fi + + command bloaty --version +} + +kconfig_frontends() { + add_path "${NUTTXTOOLS}"/kconfig-frontends/bin + + if [ ! -f "${NUTTXTOOLS}/kconfig-frontends/bin/kconfig-conf" ]; then + git clone https://bitbucket.org/nuttx/tools.git "${NUTTXTOOLS}"/nuttx-tools + cd "${NUTTXTOOLS}"/nuttx-tools/kconfig-frontends + ./configure --prefix="${NUTTXTOOLS}"/kconfig-frontends \ + --disable-kconfig --disable-nconf --disable-qconf \ + --disable-gconf --disable-mconf --disable-static \ + --disable-shared --disable-L10n + # Avoid "aclocal/automake missing" errors + touch aclocal.m4 Makefile.in + make install + cd "${NUTTXTOOLS}" + rm -rf nuttx-tools + fi +} + +mips_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/pinguino-compilers/p32/bin + + if [ ! -d "${NUTTXTOOLS}/pinguino-compilers/p32/bin/p32-gcc" ]; then + local basefile + basefile=pinguino-linux64-p32 + mkdir -p "${NUTTXTOOLS}"/pinguino-compilers + cd "${NUTTXTOOLS}" + # Download the latest pinguino toolchain prebuilt by 32bit + curl -O -L -s https://github.com/PinguinoIDE/pinguino-compilers/releases/download/v20.10/${basefile}.zip + unzip -qo ${basefile}.zip + mv p32 "${NUTTXTOOLS}"/pinguino-compilers/p32 + rm ${basefile}.zip + fi + + command p32-gcc --version +} + +python_tools() { + + pip3 install \ + cmake-format \ + CodeChecker \ + cvt2utf \ + cxxfilt \ + esptool \ + imgtool \ + kconfiglib \ + pexpect==4.8.0 \ + pyelftools \ + pyserial==3.5 \ + pytest==6.2.5 \ + pytest-json==0.4.0 \ + pytest-ordering==0.6 \ + pytest-repeat==0.9.1 +} + +riscv_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/riscv-none-elf-gcc/bin + + if [ ! -f "${NUTTXTOOLS}/riscv-none-elf-gcc/bin/riscv-none-elf-gcc" ]; then + local basefile + basefile=xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64 + cd "${NUTTXTOOLS}" + # Download the latest RISCV GCC toolchain prebuilt by xPack + wget --quiet https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/${basefile}.tar.gz + tar zxf ${basefile}.tar.gz + mv xpack-riscv-none-elf-gcc-13.2.0-2 riscv-none-elf-gcc + rm ${basefile}.tar.gz + fi + command riscv-none-elf-gcc --version +} + +rx_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/renesas-toolchain/rx-elf-gcc/bin + + if [ ! -f "${NUTTXTOOLS}/renesas-toolchain/rx-elf-gcc/bin/rx-elf-gcc" ]; then + # Download toolchain source code + # RX toolchain is built from source code. Once prebuilt RX toolchain is made available, the below code snippet can be removed. + local basefilebinutils + local basefilegcc + local basefilenewlib + basefilebinutils=binutils-2.36.1 + basefilegcc=gcc-8.3.0 + basefilenewlib=newlib-4.1.0 + + mkdir -p "${NUTTXTOOLS}"/renesas-tools/source + curl -L -s "https://llvm-gcc-renesas.com/downloads/d.php?f=rx/binutils/8.3.0.202305-gnurx/binutils-2.36.1.tar.gz" -o ${basefilebinutils}.tar.gz + tar zxf ${basefilebinutils}.tar.gz + mv ${basefilebinutils} "${NUTTXTOOLS}"/renesas-tools/source/binutils + rm ${basefilebinutils}.tar.gz + + curl -L -s "https://llvm-gcc-renesas.com/downloads/d.php?f=rx/gcc/8.3.0.202305-gnurx/gcc-8.3.0.tar.gz" -o ${basefilegcc}.tar.gz + tar zxf ${basefilegcc}.tar.gz + mv ${basefilegcc} "${NUTTXTOOLS}"/renesas-tools/source/gcc + rm ${basefilegcc}.tar.gz + + curl -L -s "https://llvm-gcc-renesas.com/downloads/d.php?f=rx/newlib/8.3.0.202305-gnurx/newlib-4.1.0.tar.gz" -o ${basefilenewlib}.tar.gz + tar zxf ${basefilenewlib}.tar.gz + mv ${basefilenewlib} "${NUTTXTOOLS}"/renesas-tools/source/newlib + rm ${basefilenewlib}.tar.gz + + # Install binutils + cd "${NUTTXTOOLS}"/renesas-tools/source/binutils; chmod +x ./configure ./mkinstalldirs + mkdir -p "${NUTTXTOOLS}"/renesas-tools/build/binutils; cd "${NUTTXTOOLS}"/renesas-tools/build/binutils + "${NUTTXTOOLS}"/renesas-tools/source/binutils/configure --target=rx-elf --prefix="${NUTTXTOOLS}"/renesas-toolchain/rx-elf-gcc \ + --disable-werror + make; make install + + # Install gcc + cd "${NUTTXTOOLS}"/renesas-tools/source/gcc + chmod +x ./contrib/download_prerequisites ./configure ./move-if-change ./libgcc/mkheader.sh + ./contrib/download_prerequisites + sed -i '1s/^/@documentencoding ISO-8859-1\n/' ./gcc/doc/gcc.texi + sed -i 's/@tex/\n&/g' ./gcc/doc/gcc.texi && sed -i 's/@end tex/\n&/g' ./gcc/doc/gcc.texi + mkdir -p "${NUTTXTOOLS}"/renesas-tools/build/gcc; cd "${NUTTXTOOLS}"/renesas-tools/build/gcc + "${NUTTXTOOLS}"/renesas-tools/source/gcc/configure --target=rx-elf --prefix="${NUTTXTOOLS}"/renesas-toolchain/rx-elf-gcc \ + --disable-shared --disable-multilib --disable-libssp --disable-libstdcxx-pch --disable-werror --enable-lto \ + --enable-gold --with-pkgversion=GCC_Build_1.02 --with-newlib --enable-languages=c + make; make install + + # Install newlib + cd "${NUTTXTOOLS}"/renesas-tools/source/newlib; chmod +x ./configure + mkdir -p "${NUTTXTOOLS}"/renesas-tools/build/newlib; cd "${NUTTXTOOLS}"/renesas-tools/build/newlib + "${NUTTXTOOLS}"/renesas-tools/source/newlib/configure --target=rx-elf --prefix="${NUTTXTOOLS}"/renesas-toolchain/rx-elf-gcc + make; make install + rm -rf "${NUTTXTOOLS}"/renesas-tools/ + fi + + command rx-elf-gcc --version +} + +sparc_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/sparc-gaisler-elf-gcc/bin + + if [ ! -f "${NUTTXTOOLS}/sparc-gaisler-elf-gcc/bin/sparc-gaisler-elf-gcc" ]; then + local basefile + basefile=bcc-2.1.0-gcc-linux64 + cd "${NUTTXTOOLS}" + # Download the SPARC GCC toolchain prebuilt by Gaisler + wget --quiet https://www.gaisler.com/anonftp/bcc2/bin/${basefile}.tar.xz + xz -d ${basefile}.tar.xz + tar xf ${basefile}.tar + mv bcc-2.1.0-gcc sparc-gaisler-elf-gcc + rm ${basefile}.tar + fi + + command sparc-gaisler-elf-gcc --version +} + +xtensa_esp32_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/xtensa-esp32-elf/bin + + if [ ! -f "${NUTTXTOOLS}/xtensa-esp32-elf/bin/xtensa-esp32-elf-gcc" ]; then + local basefile + basefile=xtensa-esp32-elf-12.2.0_20230208-x86_64-linux-gnu + cd "${NUTTXTOOLS}" + # Download the latest ESP32 GCC toolchain prebuilt by Espressif + wget --quiet https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/${basefile}.tar.xz + xz -d ${basefile}.tar.xz + tar xf ${basefile}.tar + rm ${basefile}.tar + fi + + command xtensa-esp32-elf-gcc --version +} + +xtensa_esp32s2_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/xtensa-esp32s2-elf/bin + + if [ ! -f "${NUTTXTOOLS}/xtensa-esp32s2-elf/bin/xtensa-esp32s2-elf-gcc" ]; then + local basefile + basefile=xtensa-esp32s2-elf-12.2.0_20230208-x86_64-linux-gnu + cd "${NUTTXTOOLS}" + # Download the latest ESP32 S2 GCC toolchain prebuilt by Espressif + wget --quiet https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/${basefile}.tar.xz + xz -d ${basefile}.tar.xz + tar xf ${basefile}.tar + rm ${basefile}.tar + fi + + command xtensa-esp32s2-elf-gcc --version +} + +xtensa_esp32s3_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/xtensa-esp32s3-elf/bin + + if [ ! -f "${NUTTXTOOLS}/xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-gcc" ]; then + local basefile + basefile=xtensa-esp32s3-elf-12.2.0_20230208-x86_64-linux-gnu + cd "${NUTTXTOOLS}" + # Download the latest ESP32 S3 GCC toolchain prebuilt by Espressif + wget --quiet https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/${basefile}.tar.xz + xz -d ${basefile}.tar.xz + tar xf ${basefile}.tar + rm ${basefile}.tar + fi + + command xtensa-esp32s3-elf-gcc --version +} + +wasi_sdk() { + add_path "${NUTTXTOOLS}"/wamrc + + if [ ! -f "${NUTTXTOOLS}/wasi-sdk/bin/clang" ]; then + local wasibasefile + local wasmbasefile + wasibasefile=wasi-sdk-19.0-linux + wasmbasefile=wamrc-1.1.2-x86_64-ubuntu-20.04 + cd "${NUTTXTOOLS}" + mkdir -p wamrc + + # Download the latest WASI-enabled WebAssembly C/C++ toolchain prebuilt by WASM + wget --quiet https://github.com/WebAssembly/wasi-sdk/releases/download/wasi-sdk-19/${wasibasefile}.tar.gz + tar xzf ${wasibasefile}.tar.gz + mv wasi-sdk-19.0 wasi-sdk + rm ${wasibasefile}.tar.gz + cd wamrc + # Download the latest "wamrc" AOT compiler prebuilt by WAMR + wget --quiet https://github.com/bytecodealliance/wasm-micro-runtime/releases/download/WAMR-1.1.2/${wasmbasefile}.tar.gz + tar xzf ${wasmbasefile}.tar.gz + rm ${wasmbasefile}.tar.gz + + fi + + export WASI_SDK_PATH="${NUTTXTOOLS}/wasi-sdk" + echo "export WASI_SDK_PATH=${NUTTXTOOLS}/wasi-sdk" >> "${NUTTXTOOLS}"/env.sh + + command "${WASI_SDK_PATH}"/bin/clang --version + command wamrc --version +} + +setup_links() { + # Configure ccache + mkdir -p "${NUTTXTOOLS}"/ccache/bin/ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/aarch64-none-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/aarch64-none-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/arm-none-eabi-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/arm-none-eabi-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/avr-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/avr-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/cc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/c++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/clang + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/clang++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/p32-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/rx-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/riscv-none-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/riscv-none-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/sparc-gaisler-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/sparc-gaisler-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/x86_64-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/x86_64-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/xtensa-esp32-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/xtensa-esp32-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/xtensa-esp32s2-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/xtensa-esp32s2-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/xtensa-esp32s3-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/xtensa-esp32s3-elf-g++ +} + +install_build_tools() { + mkdir -p "${NUTTXTOOLS}" + echo "#!/usr/bin/env sh" > "${NUTTXTOOLS}"/env.sh + + install="arm_clang_toolchain arm_gcc_toolchain arm64_gcc_toolchain bloaty kconfig_frontends mips_gcc_toolchain python_tools riscv_gcc_toolchain rx_gcc_toolchain sparc_gcc_toolchain xtensa_esp32_gcc_toolchain util_linux wasi_sdk" + + oldpath=$(cd . && pwd -P) + for func in ${install}; do + ${func} + done + cd "${oldpath}" + + echo "PATH=${PATH}" >> "${NUTTXTOOLS}"/env.sh + echo "export PATH" >> "${NUTTXTOOLS}"/env.sh +} + +install_build_tools diff --git a/tools/ci/platforms/msys2.sh b/tools/ci/platforms/msys2.sh new file mode 100755 index 0000000000000..f5230e778c368 --- /dev/null +++ b/tools/ci/platforms/msys2.sh @@ -0,0 +1,295 @@ +#!/usr/bin/env sh +############################################################################ +# tools/ci/platforms/msys2.sh +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# MSYS2 + +set -e +set -o xtrace + +add_path() { + PATH=$1:${PATH} +} + +arm_clang_toolchain() { + add_path "${NUTTXTOOLS}"/clang-arm-none-eabi/bin + + if [ ! -f "${NUTTXTOOLS}/clang-arm-none-eabi/bin/clang" ]; then + local basefile + basefile=LLVMEmbeddedToolchainForArm-17.0.1-Windows-x86_64 + cd "${NUTTXTOOLS}" + # Download the latest ARM clang toolchain prebuilt by ARM + curl -O -L -s https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-17.0.1/${basefile}.zip + unzip -qo ${basefile}.zip + mv ${basefile} clang-arm-none-eabi + rm ${basefile}.zip + fi + + command clang --version +} + +arm_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/gcc-arm-none-eabi/bin + + if [ ! -f "${NUTTXTOOLS}/gcc-arm-none-eabi/bin/arm-none-eabi-gcc" ]; then + local basefile + basefile=arm-gnu-toolchain-13.2.Rel1-mingw-w64-i686-arm-none-eabi + cd "${NUTTXTOOLS}" + wget --quiet https://developer.arm.com/-/media/Files/downloads/gnu/13.2.rel1/binrel/${basefile}.zip + unzip -qo ${basefile}.zip + mv ${basefile} gcc-arm-none-eabi + rm ${basefile}.zip + fi + + command arm-none-eabi-gcc --version +} + +arm64_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/gcc-aarch64-none-elf/bin + + if [ ! -f "${NUTTXTOOLS}/gcc-aarch64-none-elf/bin/aarch64-none-elf-gcc" ]; then + local basefile + basefile=arm-gnu-toolchain-13.2.rel1-mingw-w64-i686-aarch64-none-elf + cd "${NUTTXTOOLS}" + # Download the latest ARM64 GCC toolchain prebuilt by ARM + wget --quiet https://developer.arm.com/-/media/Files/downloads/gnu/13.2.Rel1/binrel/${basefile}.zip + unzip -qo ${basefile}.zip + mv ${basefile} gcc-aarch64-none-elf + rm ${basefile}.zip + fi + + command aarch64-none-elf-gcc --version +} + +c_cache() { + add_path "${NUTTXTOOLS}"/ccache/bin + + if ! type ccache > /dev/null 2>&1; then + pacman -S --noconfirm --needed ccache + fi + setup_links + command ccache --version +} + +esp_tool() { + add_path "${NUTTXTOOLS}"/esp-tool + + if ! type esptool > /dev/null 2>&1; then + local basefile + basefile=esptool-v4.7.0-win64 + cd "${NUTTXTOOLS}" + curl -O -L -s https://github.com/espressif/esptool/releases/download/v4.7.0/${basefile}.zip + unzip -qo ${basefile}.zip + mv esptool-win64 esp-tool + rm ${basefile}.zip + fi + command esptool version +} + +gen_romfs() { + add_path "${NUTTXTOOLS}"/genromfs/usr/bin + + if ! type genromfs > /dev/null 2>&1; then + git clone https://bitbucket.org/nuttx/tools.git "${NUTTXTOOLS}"/nuttx-tools + cd "${NUTTXTOOLS}"/nuttx-tools + tar zxf genromfs-0.5.2.tar.gz + cd genromfs-0.5.2 + make install PREFIX="${NUTTXTOOLS}"/genromfs + cd "${NUTTXTOOLS}" + rm -rf nuttx-tools + fi +} + +kconfig_frontends() { + add_path "${NUTTXTOOLS}"/kconfig-frontends/bin + + if [ ! -f "${NUTTXTOOLS}/kconfig-frontends/bin/kconfig-conf" ]; then + git clone https://bitbucket.org/nuttx/tools.git "${NUTTXTOOLS}"/nuttx-tools + cd "${NUTTXTOOLS}"/nuttx-tools/kconfig-frontends + ./configure --prefix="${NUTTXTOOLS}"/kconfig-frontends \ + --disable-kconfig --disable-nconf --disable-qconf \ + --disable-gconf --disable-mconf --disable-static \ + --disable-shared --disable-L10n + # Avoid "aclocal/automake missing" errors + touch aclocal.m4 Makefile.in + make install + cd "${NUTTXTOOLS}" + rm -rf nuttx-tools + fi +} + +mips_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/pinguino-compilers/windows64/p32/bin + + if [ ! -d "${NUTTXTOOLS}/pinguino-compilers" ]; then + cd "${NUTTXTOOLS}" + git clone https://github.com/PinguinoIDE/pinguino-compilers + fi + + command p32-gcc --version +} + +riscv_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/riscv-none-elf-gcc/bin + + if [ ! -f "${NUTTXTOOLS}/riscv-none-elf-gcc/bin/riscv-none-elf-gcc" ]; then + local basefile + basefile=xpack-riscv-none-elf-gcc-13.2.0-2-win32-x64 + cd "${NUTTXTOOLS}" + # Download the latest RISCV GCC toolchain prebuilt by xPack + wget --quiet https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/${basefile}.zip + unzip -qo ${basefile}.zip + mv xpack-riscv-none-elf-gcc-13.2.0-2 riscv-none-elf-gcc + rm ${basefile}.zip + fi + command riscv-none-elf-gcc --version +} + +rust() { + add_path "${NUTTXTOOLS}"/rust/cargo/bin + # Configuring the PATH environment variable + export CARGO_HOME=${NUTTXTOOLS}/rust/cargo + export RUSTUP_HOME=${NUTTXTOOLS}/rust/rustup + echo "export CARGO_HOME=${NUTTXTOOLS}/rust/cargo" >> "${NUTTXTOOLS}"/env.sh + echo "export RUSTUP_HOME=${NUTTXTOOLS}/rust/rustup" >> "${NUTTXTOOLS}"/env.sh + if ! type rustc > /dev/null 2>&1; then + local basefile + basefile=x86_64-pc-windows-gnu + mkdir -p "${NUTTXTOOLS}"/rust + cd "${NUTTXTOOLS}" + # Download tool rustup-init.exe + curl -O -L -s https://static.rust-lang.org/rustup/dist/x86_64-pc-windows-gnu/rustup-init.exe + # Install Rust target x86_64-pc-windows-gnu + ./rustup-init.exe -y --default-host ${basefile} --no-modify-path + # Install targets supported from NuttX + "$CARGO_HOME"/bin/rustup target add thumbv6m-none-eabi + "$CARGO_HOME"/bin/rustup target add thumbv7m-none-eabi + rm rustup-init.exe + fi + command rustc --version +} + +sparc_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/sparc-gaisler-elf-gcc/bin + + if [ ! -f "${NUTTXTOOLS}/sparc-gaisler-elf-gcc/bin/sparc-gaisler-elf-gcc" ]; then + local basefile + basefile=bcc-2.1.0-gcc-mingw64 + cd "${NUTTXTOOLS}" + # Download the SPARC GCC toolchain prebuilt by Gaisler + wget --quiet https://www.gaisler.com/anonftp/bcc2/bin/${basefile}.zip + unzip -qo ${basefile}.zip + mv bcc-2.1.0-gcc sparc-gaisler-elf-gcc + rm ${basefile}.zip + fi + + command sparc-gaisler-elf-gcc --version +} + +xtensa_esp32_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/xtensa-esp32-elf/bin + + if [ ! -f "${NUTTXTOOLS}/xtensa-esp32-elf/bin/xtensa-esp32-elf-gcc" ]; then + local basefile + basefile=xtensa-esp32-elf-12.2.0_20230208-x86_64-w64-mingw32 + cd "${NUTTXTOOLS}" + # Download the latest ESP32 GCC toolchain prebuilt by Espressif + wget --quiet https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/${basefile}.zip + unzip -qo ${basefile}.zip + rm ${basefile}.zip + fi + + command xtensa-esp32-elf-gcc --version +} + +xtensa_esp32s2_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/xtensa-esp32s2-elf/bin + + if [ ! -f "${NUTTXTOOLS}/xtensa-esp32s2-elf/bin/xtensa-esp32s2-elf-gcc" ]; then + local basefile + basefile=xtensa-esp32s2-elf-12.2.0_20230208-x86_64-w64-mingw32 + cd "${NUTTXTOOLS}" + # Download the latest ESP32 S2 GCC toolchain prebuilt by Espressif + wget --quiet https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/${basefile}.zip + unzip -qo ${basefile}.zip + rm ${basefile}.zip + fi + + command xtensa-esp32s2-elf-gcc --version +} + +xtensa_esp32s3_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/xtensa-esp32s3-elf/bin + + if [ ! -f "${NUTTXTOOLS}/xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-gcc" ]; then + local basefile + basefile=xtensa-esp32s3-elf-12.2.0_20230208-x86_64-w64-mingw32 + cd "${NUTTXTOOLS}" + # Download the latest ESP32 S3 GCC toolchain prebuilt by Espressif + wget --quiet https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/${basefile}.zip + unzip -qo ${basefile}.zip + rm ${basefile}.zip + fi + + command xtensa-esp32s3-elf-gcc --version +} + +setup_links() { + # Configure ccache + mkdir -p "${NUTTXTOOLS}"/ccache/bin/ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/aarch64-none-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/aarch64-none-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/arm-none-eabi-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/arm-none-eabi-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/avr-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/avr-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/cc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/c++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/clang + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/clang++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/p32-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/riscv64-unknown-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/riscv64-unknown-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/sparc-gaisler-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/sparc-gaisler-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/x86_64-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/x86_64-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/xtensa-esp32-elf-gcc +} + +install_build_tools() { + mkdir -p "${NUTTXTOOLS}" + echo "#!/usr/bin/env sh" > "${NUTTXTOOLS}"/env.sh + + install="arm_clang_toolchain arm_gcc_toolchain arm64_gcc_toolchain kconfig_frontends riscv_gcc_toolchain rust" + + oldpath=$(cd . && pwd -P) + for func in ${install}; do + ${func} + done + cd "${oldpath}" + + echo "PATH=${PATH}" >> "${NUTTXTOOLS}"/env.sh + echo "export PATH" >> "${NUTTXTOOLS}"/env.sh +} + +install_build_tools diff --git a/tools/ci/platforms/ubuntu.sh b/tools/ci/platforms/ubuntu.sh new file mode 100755 index 0000000000000..a3cffd9eba936 --- /dev/null +++ b/tools/ci/platforms/ubuntu.sh @@ -0,0 +1,450 @@ +#!/usr/bin/env sh +############################################################################ +# tools/ci/platforms/ubuntu.sh +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# Ubuntu + +set -e +set -o xtrace + +add_path() { + PATH=$1:${PATH} +} + +arm_clang_toolchain() { + add_path "${NUTTXTOOLS}"/clang-arm-none-eabi/bin + + if [ ! -f "${NUTTXTOOLS}/clang-arm-none-eabi/bin/clang" ]; then + local basefile + basefile=LLVMEmbeddedToolchainForArm-17.0.1-Linux-x86_64 + cd "${NUTTXTOOLS}" + # Download the latest ARM clang toolchain prebuilt by ARM + curl -O -L -s https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-17.0.1/${basefile}.tar.xz + xz -d ${basefile}.tar.xz + tar xf ${basefile}.tar + mv ${basefile} clang-arm-none-eabi + rm ${basefile}.tar + fi + + command clang --version +} + +arm_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/gcc-arm-none-eabi/bin + + if [ ! -f "${NUTTXTOOLS}/gcc-arm-none-eabi/bin/arm-none-eabi-gcc" ]; then + local basefile + basefile=arm-gnu-toolchain-13.2.Rel1-x86_64-arm-none-eabi + cd "${NUTTXTOOLS}" + # Download the latest ARM GCC toolchain prebuilt by ARM + wget --quiet https://developer.arm.com/-/media/Files/downloads/gnu/13.2.rel1/binrel/${basefile}.tar.xz + xz -d ${basefile}.tar.xz + tar xf ${basefile}.tar + mv ${basefile} gcc-arm-none-eabi + rm ${basefile}.tar + fi + + command arm-none-eabi-gcc --version +} + +arm64_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/gcc-aarch64-none-elf/bin + + if [ ! -f "${NUTTXTOOLS}/gcc-aarch64-none-elf/bin/aarch64-none-elf-gcc" ]; then + local basefile + basefile=arm-gnu-toolchain-13.2.Rel1-x86_64-aarch64-none-elf + cd "${NUTTXTOOLS}" + # Download the latest ARM64 GCC toolchain prebuilt by ARM + wget --quiet https://developer.arm.com/-/media/Files/downloads/gnu/13.2.Rel1/binrel/${basefile}.tar.xz + xz -d ${basefile}.tar.xz + tar xf ${basefile}.tar + mv ${basefile} gcc-aarch64-none-elf + rm ${basefile}.tar + fi + + command aarch64-none-elf-gcc --version +} + +avr_gcc_toolchain() { + if ! type avr-gcc > /dev/null 2>&1; then + sudo apt-get install -y binutils-avr gcc-avr avr-libc + fi + + command avr-gcc --version +} + +binutils() { + if ! type objcopy > /dev/null 2>&1; then + sudo apt-get install -y binutils-dev + fi + + command objcopy --version +} + +bloaty() { + add_path "${NUTTXTOOLS}"/bloaty/bin + + if [ ! -f "${NUTTXTOOLS}/bloaty/bin/bloaty" ]; then + git clone --depth 1 --branch v1.1 https://github.com/google/bloaty "${NUTTXTOOLS}"/bloaty-src + mkdir -p "${NUTTXTOOLS}"/bloaty + cd "${NUTTXTOOLS}"/bloaty-src + cmake -B build -DCMAKE_INSTALL_PREFIX="${NUTTXTOOLS}"/bloaty + cmake --build build + cmake --build build --target install + cd "${NUTTXTOOLS}" + rm -rf bloaty-src + ls -a "${NUTTXTOOLS}"/bloaty + fi + + command bloaty --version +} + +c_cache() { + if ! type ccache > /dev/null 2>&1; then + sudo apt-get install -y ccache + fi + setup_links + command ccache --version +} + +clang_tidy() { + if ! type clang-tidy > /dev/null 2>&1; then + sudo apt-get install -y clang clang-tidy + fi + + command clang-tidy --version +} + +util_linux() { + if ! type flock > /dev/null 2>&1; then + sudo apt-get install -y util-linux + fi + + command flock --version +} + +gen_romfs() { + if ! type genromfs > /dev/null 2>&1; then + sudo apt-get install -y genromfs + fi +} + +gperf() { + if ! type gperf > /dev/null 2>&1; then + sudo apt-get install -y gperf + fi + +} + +kconfig_frontends() { + add_path "${NUTTXTOOLS}"/kconfig-frontends/bin + + if [ ! -f "${NUTTXTOOLS}/kconfig-frontends/bin/kconfig-conf" ]; then + git clone https://bitbucket.org/nuttx/tools.git "${NUTTXTOOLS}"/nuttx-tools + cd "${NUTTXTOOLS}"/nuttx-tools/kconfig-frontends + ./configure --prefix="${NUTTXTOOLS}"/kconfig-frontends \ + --disable-kconfig --disable-nconf --disable-qconf \ + --disable-gconf --disable-mconf --disable-static \ + --disable-shared --disable-L10n + # Avoid "aclocal/automake missing" errors + touch aclocal.m4 Makefile.in + make install + cd "${NUTTXTOOLS}" + rm -rf nuttx-tools + fi +} + +mips_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/pinguino-compilers/p32/bin + + if [ ! -d "${NUTTXTOOLS}/pinguino-compilers/p32/bin/p32-gcc" ]; then + local basefile + basefile=pinguino-linux64-p32 + mkdir -p "${NUTTXTOOLS}"/pinguino-compilers + cd "${NUTTXTOOLS}" + # Download the latest pinguino toolchain prebuilt by 32bit + curl -O -L -s https://github.com/PinguinoIDE/pinguino-compilers/releases/download/v20.10/${basefile}.zip + unzip -qo ${basefile}.zip + mv p32 "${NUTTXTOOLS}"/pinguino-compilers/p32 + rm ${basefile}.zip + fi + + command p32-gcc --version +} + +python_tools() { + + pip3 install \ + cmake-format \ + CodeChecker \ + cvt2utf \ + cxxfilt \ + esptool \ + imgtool \ + kconfiglib \ + pexpect==4.8.0 \ + pyelftools \ + pyserial==3.5 \ + pytest==6.2.5 \ + pytest-json==0.4.0 \ + pytest-ordering==0.6 \ + pytest-repeat==0.9.1 +} + +riscv_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/riscv-none-elf-gcc/bin + + if [ ! -f "${NUTTXTOOLS}/riscv-none-elf-gcc/bin/riscv-none-elf-gcc" ]; then + local basefile + basefile=xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64 + cd "${NUTTXTOOLS}" + # Download the latest RISCV GCC toolchain prebuilt by xPack + wget --quiet https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/${basefile}.tar.gz + tar zxf ${basefile}.tar.gz + mv xpack-riscv-none-elf-gcc-13.2.0-2 riscv-none-elf-gcc + rm ${basefile}.tar.gz + fi + command riscv-none-elf-gcc --version +} + +rust() { + if ! type rustc > /dev/null 2>&1; then + sudo apt-get install rustc + # Install targets supported from NuttX + rustup target add thumbv6m-none-eabi + rustup target add thumbv7m-none-eabi + fi + + command rustc --version +} + +rx_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/renesas-toolchain/rx-elf-gcc/bin + + if [ ! -f "${NUTTXTOOLS}/renesas-toolchain/rx-elf-gcc/bin/rx-elf-gcc" ]; then + # Download toolchain source code + # RX toolchain is built from source code. Once prebuilt RX toolchain is made available, the below code snippet can be removed. + local basefilebinutils + local basefilegcc + local basefilenewlib + basefilebinutils=binutils-2.36.1 + basefilegcc=gcc-8.3.0 + basefilenewlib=newlib-4.1.0 + + mkdir -p "${NUTTXTOOLS}"/renesas-tools/source + curl -L -s "https://llvm-gcc-renesas.com/downloads/d.php?f=rx/binutils/8.3.0.202305-gnurx/binutils-2.36.1.tar.gz" -o ${basefilebinutils}.tar.gz + tar zxf ${basefilebinutils}.tar.gz + mv ${basefilebinutils} "${NUTTXTOOLS}"/renesas-tools/source/binutils + rm ${basefilebinutils}.tar.gz + + curl -L -s "https://llvm-gcc-renesas.com/downloads/d.php?f=rx/gcc/8.3.0.202305-gnurx/gcc-8.3.0.tar.gz" -o ${basefilegcc}.tar.gz + tar zxf ${basefilegcc}.tar.gz + mv ${basefilegcc} "${NUTTXTOOLS}"/renesas-tools/source/gcc + rm ${basefilegcc}.tar.gz + + curl -L -s "https://llvm-gcc-renesas.com/downloads/d.php?f=rx/newlib/8.3.0.202305-gnurx/newlib-4.1.0.tar.gz" -o ${basefilenewlib}.tar.gz + tar zxf ${basefilenewlib}.tar.gz + mv ${basefilenewlib} "${NUTTXTOOLS}"/renesas-tools/source/newlib + rm ${basefilenewlib}.tar.gz + + # Install binutils + cd "${NUTTXTOOLS}"/renesas-tools/source/binutils; chmod +x ./configure ./mkinstalldirs + mkdir -p "${NUTTXTOOLS}"/renesas-tools/build/binutils; cd "${NUTTXTOOLS}"/renesas-tools/build/binutils + "${NUTTXTOOLS}"/renesas-tools/source/binutils/configure --target=rx-elf --prefix="${NUTTXTOOLS}"/renesas-toolchain/rx-elf-gcc \ + --disable-werror + make; make install + + # Install gcc + cd "${NUTTXTOOLS}"/renesas-tools/source/gcc + chmod +x ./contrib/download_prerequisites ./configure ./move-if-change ./libgcc/mkheader.sh + ./contrib/download_prerequisites + sed -i '1s/^/@documentencoding ISO-8859-1\n/' ./gcc/doc/gcc.texi + sed -i 's/@tex/\n&/g' ./gcc/doc/gcc.texi && sed -i 's/@end tex/\n&/g' ./gcc/doc/gcc.texi + mkdir -p "${NUTTXTOOLS}"/renesas-tools/build/gcc; cd "${NUTTXTOOLS}"/renesas-tools/build/gcc + "${NUTTXTOOLS}"/renesas-tools/source/gcc/configure --target=rx-elf --prefix="${NUTTXTOOLS}"/renesas-toolchain/rx-elf-gcc \ + --disable-shared --disable-multilib --disable-libssp --disable-libstdcxx-pch --disable-werror --enable-lto \ + --enable-gold --with-pkgversion=GCC_Build_1.02 --with-newlib --enable-languages=c + make; make install + + # Install newlib + cd "${NUTTXTOOLS}"/renesas-tools/source/newlib; chmod +x ./configure + mkdir -p "${NUTTXTOOLS}"/renesas-tools/build/newlib; cd "${NUTTXTOOLS}"/renesas-tools/build/newlib + "${NUTTXTOOLS}"/renesas-tools/source/newlib/configure --target=rx-elf --prefix="${NUTTXTOOLS}"/renesas-toolchain/rx-elf-gcc + make; make install + rm -rf "${NUTTXTOOLS}"/renesas-tools/ + fi + + command rx-elf-gcc --version +} + +sparc_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/sparc-gaisler-elf-gcc/bin + + if [ ! -f "${NUTTXTOOLS}/sparc-gaisler-elf-gcc/bin/sparc-gaisler-elf-gcc" ]; then + local basefile + basefile=bcc-2.1.0-gcc-linux64 + cd "${NUTTXTOOLS}" + # Download the SPARC GCC toolchain prebuilt by Gaisler + wget --quiet https://www.gaisler.com/anonftp/bcc2/bin/${basefile}.tar.xz + xz -d ${basefile}.tar.xz + tar xf ${basefile}.tar + mv bcc-2.1.0-gcc sparc-gaisler-elf-gcc + rm ${basefile}.tar + fi + + command sparc-gaisler-elf-gcc --version +} + +xtensa_esp32_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/xtensa-esp32-elf/bin + + if [ ! -f "${NUTTXTOOLS}/xtensa-esp32-elf/bin/xtensa-esp32-elf-gcc" ]; then + local basefile + basefile=xtensa-esp32-elf-12.2.0_20230208-x86_64-linux-gnu + cd "${NUTTXTOOLS}" + # Download the latest ESP32 GCC toolchain prebuilt by Espressif + wget --quiet https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/${basefile}.tar.xz + xz -d ${basefile}.tar.xz + tar xf ${basefile}.tar + rm ${basefile}.tar + fi + + command xtensa-esp32-elf-gcc --version +} + +xtensa_esp32s2_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/xtensa-esp32s2-elf/bin + + if [ ! -f "${NUTTXTOOLS}/xtensa-esp32s2-elf/bin/xtensa-esp32s2-elf-gcc" ]; then + local basefile + basefile=xtensa-esp32s2-elf-12.2.0_20230208-x86_64-linux-gnu + cd "${NUTTXTOOLS}" + # Download the latest ESP32 S2 GCC toolchain prebuilt by Espressif + wget --quiet https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/${basefile}.tar.xz + xz -d ${basefile}.tar.xz + tar xf ${basefile}.tar + rm ${basefile}.tar + fi + + command xtensa-esp32s2-elf-gcc --version +} + +xtensa_esp32s3_gcc_toolchain() { + add_path "${NUTTXTOOLS}"/xtensa-esp32s3-elf/bin + + if [ ! -f "${NUTTXTOOLS}/xtensa-esp32s3-elf/bin/xtensa-esp32s3-elf-gcc" ]; then + local basefile + basefile=xtensa-esp32s3-elf-12.2.0_20230208-x86_64-linux-gnu + cd "${NUTTXTOOLS}" + # Download the latest ESP32 S3 GCC toolchain prebuilt by Espressif + wget --quiet https://github.com/espressif/crosstool-NG/releases/download/esp-12.2.0_20230208/${basefile}.tar.xz + xz -d ${basefile}.tar.xz + tar xf ${basefile}.tar + rm ${basefile}.tar + fi + + command xtensa-esp32s3-elf-gcc --version +} + +u_boot_tools() { + if ! type mkimage > /dev/null 2>&1; then + sudo apt-get install -y u-boot-tools + fi +} + +wasi_sdk() { + add_path "${NUTTXTOOLS}"/wamrc + + if [ ! -f "${NUTTXTOOLS}/wasi-sdk/bin/clang" ]; then + local wasibasefile + local wasmbasefile + wasibasefile=wasi-sdk-19.0-linux + wasmbasefile=wamrc-1.1.2-x86_64-ubuntu-20.04 + cd "${NUTTXTOOLS}" + mkdir -p wamrc + + # Download the latest WASI-enabled WebAssembly C/C++ toolchain prebuilt by WASM + wget --quiet https://github.com/WebAssembly/wasi-sdk/releases/download/wasi-sdk-19/${wasibasefile}.tar.gz + tar xzf ${wasibasefile}.tar.gz + mv wasi-sdk-19.0 wasi-sdk + rm ${wasibasefile}.tar.gz + cd wamrc + # Download the latest "wamrc" AOT compiler prebuilt by WAMR + wget --quiet https://github.com/bytecodealliance/wasm-micro-runtime/releases/download/WAMR-1.1.2/${wasmbasefile}.tar.gz + tar xzf ${wasmbasefile}.tar.gz + rm ${wasmbasefile}.tar.gz + + fi + + export WASI_SDK_PATH="${NUTTXTOOLS}/wasi-sdk" + echo "export WASI_SDK_PATH=${NUTTXTOOLS}/wasi-sdk" >> "${NUTTXTOOLS}"/env.sh + + command "${WASI_SDK_PATH}"/bin/clang --version + command wamrc --version +} + +setup_links() { + # Configure ccache + mkdir -p "${NUTTXTOOLS}"/ccache/bin/ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/aarch64-none-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/aarch64-none-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/arm-none-eabi-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/arm-none-eabi-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/avr-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/avr-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/cc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/c++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/clang + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/clang++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/p32-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/rx-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/riscv-none-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/riscv-none-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/sparc-gaisler-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/sparc-gaisler-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/x86_64-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/x86_64-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/xtensa-esp32-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/xtensa-esp32-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/xtensa-esp32s2-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/xtensa-esp32s2-elf-g++ + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/xtensa-esp32s3-elf-gcc + ln -sf "$(which ccache)" "${NUTTXTOOLS}"/ccache/bin/xtensa-esp32s3-elf-g++ +} + +install_build_tools() { + mkdir -p "${NUTTXTOOLS}" + echo "#!/usr/bin/env sh" > "${NUTTXTOOLS}"/env.sh + + install="arm_clang_toolchain arm_gcc_toolchain arm64_gcc_toolchain avr_gcc_toolchain binutils bloaty clang_tidy gen_romfs gperf kconfig_frontends mips_gcc_toolchain python_tools riscv_gcc_toolchain rust rx_gcc_toolchain sparc_gcc_toolchain xtensa_esp32_gcc_toolchain u_boot_tools util_linux wasi_sdk c_cache" + + oldpath=$(cd . && pwd -P) + for func in ${install}; do + ${func} + done + cd "${oldpath}" + + echo "PATH=${PATH}" >> "${NUTTXTOOLS}"/env.sh + echo "export PATH" >> "${NUTTXTOOLS}"/env.sh +} + +install_build_tools diff --git a/tools/ci/testlist/macos.dat b/tools/ci/testlist/macos.dat index 30bd0905f9c9b..70c05ee29dbcf 100644 --- a/tools/ci/testlist/macos.dat +++ b/tools/ci/testlist/macos.dat @@ -26,8 +26,8 @@ # RISC-V /risc-v/bl602/bl602evb/configs/wifi -/risc-v/esp32c3/esp32c3-devkit/configs/cxx -/risc-v/esp32c3/esp32c3-devkit/configs/wifi +/risc-v/esp32c3-legacy/esp32c3-devkit/configs/cxx +/risc-v/esp32c3-legacy/esp32c3-devkit/configs/wifi # x86_64-elf-gcc from homebrew doesn't seem to # provide __udivdi3 etc for -m32, so we do not build diff --git a/tools/ci/testlist/msys2.dat b/tools/ci/testlist/msys2.dat new file mode 100644 index 0000000000000..3a9c933963b6e --- /dev/null +++ b/tools/ci/testlist/msys2.dat @@ -0,0 +1,12 @@ +# Chose a minimalistic subset of board/configs due to MSYS2 builds +# being extremely slow on GitHub + +# ARM + +/arm/stm32/nucleo-l152re/configs/nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI + +/arm/stm32/nucleo-f4x1re/configs/f411-nsh,CONFIG_ARM_TOOLCHAIN_GNU_EABI + +# ARM64 + +/arm64/qemu/qemu-armv8a/configs/nsh_smp diff --git a/tools/ci/testlist/other.dat b/tools/ci/testlist/other.dat index b6a3b48a8edb8..bda16339b891a 100644 --- a/tools/ci/testlist/other.dat +++ b/tools/ci/testlist/other.dat @@ -22,3 +22,13 @@ -xx3823:nsh /arm64 + +# arm64 Boards build by CMake +CMake,qemu-armv8a:citest +CMake,qemu-armv8a:citest_smp +CMake,qemu-armv8a:nsh +CMake,qemu-armv8a:nsh_fiq +CMake,qemu-armv8a:nsh_gicv2 +CMake,qemu-armv8a:nsh_smp +CMake,qemu-armv8a:nsh_smp_tickless +CMake,qemu-armv8a:sotest diff --git a/tools/ci/testlist/xtensa.dat b/tools/ci/testlist/xtensa.dat index 0fec540ce6771..a82a1ee9b059c 100644 --- a/tools/ci/testlist/xtensa.dat +++ b/tools/ci/testlist/xtensa.dat @@ -1 +1,4 @@ /xtensa + +# We do not set ESPTOOL_BINDIR in this build +-esp32-devkitc:qemu-openeth diff --git a/tools/ci/testrun/pytest.ini b/tools/ci/testrun/pytest.ini index 6452c380670dd..11b9bb8ff39e8 100644 --- a/tools/ci/testrun/pytest.ini +++ b/tools/ci/testrun/pytest.ini @@ -14,4 +14,5 @@ markers = common : 'marks tests as common' sim : 'marks tests as simulator' qemu : 'marks tests as qemu' + rv_virt : 'marks tests as rv-virt' disable_autouse : 'disable autouse' diff --git a/tools/ci/testrun/script/test_example/test_example.py b/tools/ci/testrun/script/test_example/test_example.py index 9fac6af202ad7..4ba779c662949 100644 --- a/tools/ci/testrun/script/test_example/test_example.py +++ b/tools/ci/testrun/script/test_example/test_example.py @@ -16,7 +16,7 @@ def test_helloxx(p): def test_pipe(p): - ret = p.sendCommand("pipe", "redirect_reader: Returning success", 60) + ret = p.sendCommand("pipe", "redirect_reader: Returning success", timeout=60) assert ret == 0 @@ -26,5 +26,5 @@ def test_popen(p): def test_usrsocktest(p): - ret = p.sendCommand("usrsocktest", "FAILED:0", 60) + ret = p.sendCommand("usrsocktest", "FAILED:0", timeout=60) assert ret == 0 diff --git a/tools/ci/testrun/script/test_framework/__init__.py b/tools/ci/testrun/script/test_framework/__init__.py new file mode 100644 index 0000000000000..f18cc000eb242 --- /dev/null +++ b/tools/ci/testrun/script/test_framework/__init__.py @@ -0,0 +1,2 @@ +#!/usr/bin/python3 +# encoding: utf-8 diff --git a/tools/ci/testrun/script/test_framework/test_cmocka.py b/tools/ci/testrun/script/test_framework/test_cmocka.py new file mode 100644 index 0000000000000..7d5f4d7b9badf --- /dev/null +++ b/tools/ci/testrun/script/test_framework/test_cmocka.py @@ -0,0 +1,40 @@ +#!/usr/bin/python3 +# encoding: utf-8 + +import os + +import pytest + +pytestmark = [pytest.mark.common, pytest.mark.rv_virt] + +cmocka_list_start = "cmocka_list_start" +cmocka_list_end = "cmocka_list_end" +cmocka_test_start = "cmocka_test_start" +cmocka_test_end = "cmocka_test_end" + + +@pytest.mark.run(order=1) +def test_cmocka(p): + if p.board == "sim": + os.mkdir("./test") + ret = p.sendCommand("mount -t hostfs -o fs=./test /data") + if p.board == "rv-virt": + ret = p.sendCommand("mount -t vfat /dev/virtblk0 /data") + + p.sendCommand(f"echo {cmocka_list_start}") + p.sendCommand("cmocka --list", "Cmocka Test Completed") + p.sendCommand(f"echo {cmocka_list_end}") + + p.sendCommand(f"echo {cmocka_test_start}") + ret = p.sendCommand( + "cmocka --skip test_case_posix_timer|test_case_oneshot|write_default|read_default|burst_test|gpiotest01|" + "test_playback.*|test_interaction.*|test_stress.*|test_capture.*", + "Cmocka Test Completed", + timeout=1200, + ) + p.sendCommand(f"echo {cmocka_test_end}") + + if p.board == "sim": + os.rmdir("./test") + + assert ret == 0 diff --git a/tools/ci/testrun/script/test_libuv/__init__.py b/tools/ci/testrun/script/test_libuv/__init__.py new file mode 100644 index 0000000000000..f18cc000eb242 --- /dev/null +++ b/tools/ci/testrun/script/test_libuv/__init__.py @@ -0,0 +1,2 @@ +#!/usr/bin/python3 +# encoding: utf-8 diff --git a/tools/ci/testrun/script/test_libuv/test_libuv.py b/tools/ci/testrun/script/test_libuv/test_libuv.py new file mode 100644 index 0000000000000..1a336a809dd58 --- /dev/null +++ b/tools/ci/testrun/script/test_libuv/test_libuv.py @@ -0,0 +1,427 @@ +#!/usr/bin/python3 +# encoding: utf-8 + +import pytest + + +class TestLibuv: + pytestmark = [pytest.mark.sim] + + def test_test_macros(self, p): + ret = p.sendCommand( + "uv_run_tests test_macros", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_close_order(self, p): + ret = p.sendCommand( + "uv_run_tests close_order", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_run_once(self, p): + ret = p.sendCommand( + "uv_run_tests run_once", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_run_nowait(self, p): + ret = p.sendCommand( + "uv_run_tests run_nowait", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_loop_alive(self, p): + ret = p.sendCommand( + "uv_run_tests loop_alive", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_loop_close(self, p): + ret = p.sendCommand( + "uv_run_tests loop_close", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_loop_instant_close(self, p): + ret = p.sendCommand( + "uv_run_tests loop_instant_close", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_loop_stop(self, p): + ret = p.sendCommand( + "uv_run_tests loop_stop", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_loop_backend_timeout(self, p): + ret = p.sendCommand( + "uv_run_tests loop_backend_timeout", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_default_loop_close(self, p): + ret = p.sendCommand( + "uv_run_tests default_loop_close", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_barrier_1(self, p): + ret = p.sendCommand( + "uv_run_tests barrier_1", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_barrier_2(self, p): + ret = p.sendCommand( + "uv_run_tests barrier_2", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_barrier_3(self, p): + ret = p.sendCommand( + "uv_run_tests barrier_3", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_barrier_serial_thread(self, p): + ret = p.sendCommand( + "uv_run_tests barrier_serial_thread", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_barrier_serial_thread_single(self, p): + ret = p.sendCommand( + "uv_run_tests barrier_serial_thread_single", + ["not ok 1 -", "ok 1 -"], + timeout=10, + ) + assert ret == 1 + + def test_condvar_1(self, p): + ret = p.sendCommand( + "uv_run_tests condvar_1", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_condvar_2(self, p): + ret = p.sendCommand( + "uv_run_tests condvar_2", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_condvar_3(self, p): + ret = p.sendCommand( + "uv_run_tests condvar_3", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_condvar_4(self, p): + ret = p.sendCommand( + "uv_run_tests condvar_4", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_condvar_5(self, p): + ret = p.sendCommand( + "uv_run_tests condvar_5", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_semaphore_1(self, p): + ret = p.sendCommand( + "uv_run_tests semaphore_1", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_semaphore_2(self, p): + ret = p.sendCommand( + "uv_run_tests semaphore_2", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_semaphore_3(self, p): + ret = p.sendCommand( + "uv_run_tests semaphore_3", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_timer(self, p): + ret = p.sendCommand("uv_run_tests timer", ["not ok 1 -", "ok 1 -"], timeout=10) + assert ret == 1 + + def test_timer_init(self, p): + ret = p.sendCommand( + "uv_run_tests timer_init", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_timer_again(self, p): + ret = p.sendCommand( + "uv_run_tests timer_again", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_timer_start_twice(self, p): + ret = p.sendCommand( + "uv_run_tests timer_start_twice", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_timer_order(self, p): + ret = p.sendCommand( + "uv_run_tests timer_order", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_timer_huge_timeout(self, p): + ret = p.sendCommand( + "uv_run_tests timer_huge_timeout", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_timer_huge_repeat(self, p): + ret = p.sendCommand( + "uv_run_tests timer_huge_repeat", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_timer_run_once(self, p): + ret = p.sendCommand( + "uv_run_tests timer_run_once", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_timer_from_check(self, p): + ret = p.sendCommand( + "uv_run_tests timer_from_check", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_timer_is_closing(self, p): + ret = p.sendCommand( + "uv_run_tests timer_is_closing", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_timer_null_callback(self, p): + ret = p.sendCommand( + "uv_run_tests timer_null_callback", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_timer_early_check(self, p): + ret = p.sendCommand( + "uv_run_tests timer_early_check", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_loop_handles(self, p): + ret = p.sendCommand( + "uv_run_tests loop_handles", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_walk_handles(self, p): + ret = p.sendCommand( + "uv_run_tests walk_handles", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_active(self, p): + ret = p.sendCommand("uv_run_tests active", ["not ok 1 -", "ok 1 -"], timeout=10) + assert ret == 1 + + def test_embed(self, p): + if p.board in ["sim"]: + pytest.skip("unsupported at %s" % p.board) + ret = p.sendCommand("uv_run_tests embed", ["not ok 1 -", "ok 1 -"], timeout=10) + assert ret == 1 + + @pytest.mark.skip(reason="VELAPLATFO-6346") + def test_async(self, p): + if p.ci: + pytest.skip("unsupported at %s" % p.board) + if p.board in ["sim", "vela"]: + pytest.skip("unsupported at %s" % p.board) + ret = p.sendCommand("uv_run_tests async", ["not ok 1 -", "ok 1 -"], timeout=10) + assert ret == 1 + + def test_async_null_cb(self, p): + if p.ci: + pytest.skip("unsupported at %s" % p.board) + if p.board in ["sim", "vela"]: + pytest.skip("unsupported at %s" % p.board) + ret = p.sendCommand( + "uv_run_tests async_null_cb", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_homedir(self, p): + ret = p.sendCommand( + "uv_run_tests homedir", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_tmpdir(self, p): + ret = p.sendCommand("uv_run_tests tmpdir", ["not ok 1 -", "ok 1 -"], timeout=10) + assert ret == 1 + + def test_hrtime(self, p): + ret = p.sendCommand("uv_run_tests hrtime", ["not ok 1 -", "ok 1 -"], timeout=25) + assert ret == 1 + + def test_gettimeofday(self, p): + ret = p.sendCommand( + "uv_run_tests gettimeofday", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_poll_oob(self, p): + if p.board in ["sim"]: + pytest.skip("unsupported at %s" % p.board) + ret = p.sendCommand( + "uv_run_tests poll_oob", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_threadpool_queue_work_simple(self, p): + ret = p.sendCommand( + "uv_run_tests threadpool_queue_work_simple", + ["not ok 1 -", "ok 1 -"], + timeout=10, + ) + assert ret == 1 + + def test_threadpool_queue_work_einval(self, p): + ret = p.sendCommand( + "uv_run_tests threadpool_queue_work_einval", + ["not ok 1 -", "ok 1 -"], + timeout=10, + ) + assert ret == 1 + + def test_threadpool_cancel_getnameinfo(self, p): + ret = p.sendCommand( + "uv_run_tests threadpool_cancel_getnameinfo", + ["not ok 1 -", "ok 1 -"], + timeout=10, + ) + assert ret == 1 + + def test_threadpool_cancel_random(self, p): + ret = p.sendCommand( + "uv_run_tests threadpool_cancel_random", + ["not ok 1 -", "ok 1 -"], + timeout=10, + ) + assert ret == 1 + + def test_threadpool_cancel_work(self, p): + ret = p.sendCommand( + "uv_run_tests threadpool_cancel_work", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_threadpool_cancel_single(self, p): + ret = p.sendCommand( + "uv_run_tests threadpool_cancel_single", + ["not ok 1 -", "ok 1 -"], + timeout=10, + ) + assert ret == 1 + + def test_thread_local_storage(self, p): + ret = p.sendCommand( + "uv_run_tests thread_local_storage", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_thread_stack_size(self, p): + ret = p.sendCommand( + "uv_run_tests thread_stack_size", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_thread_mutex(self, p): + ret = p.sendCommand( + "uv_run_tests thread_mutex", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_thread_mutex_recursive(self, p): + ret = p.sendCommand( + "uv_run_tests thread_mutex_recursive", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_thread_rwlock(self, p): + ret = p.sendCommand( + "uv_run_tests thread_rwlock", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_thread_rwlock_trylock(self, p): + ret = p.sendCommand( + "uv_run_tests thread_rwlock_trylock", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_thread_create(self, p): + ret = p.sendCommand( + "uv_run_tests thread_create", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_thread_equal(self, p): + ret = p.sendCommand( + "uv_run_tests thread_equal", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_queue_foreach_delete(self, p): + ret = p.sendCommand( + "uv_run_tests queue_foreach_delete", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_random_async(self, p): + if p.ci: + pytest.skip("unsupported at %s" % p.board) + ret = p.sendCommand( + "uv_run_tests random_async", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_random_sync(self, p): + if p.ci: + pytest.skip("unsupported at %s" % p.board) + ret = p.sendCommand( + "uv_run_tests random_sync", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_handle_type_name(self, p): + ret = p.sendCommand( + "uv_run_tests handle_type_name", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_req_type_name(self, p): + ret = p.sendCommand( + "uv_run_tests req_type_name", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_utf8_decode1(self, p): + ret = p.sendCommand( + "uv_run_tests utf8_decode1", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 + + def test_utf8_decode1_overrun(self, p): + ret = p.sendCommand( + "uv_run_tests utf8_decode1_overrun", ["not ok 1 -", "ok 1 -"], timeout=10 + ) + assert ret == 1 diff --git a/tools/ci/testrun/script/test_open_posix/__init__.py b/tools/ci/testrun/script/test_open_posix/__init__.py new file mode 100644 index 0000000000000..f18cc000eb242 --- /dev/null +++ b/tools/ci/testrun/script/test_open_posix/__init__.py @@ -0,0 +1,2 @@ +#!/usr/bin/python3 +# encoding: utf-8 diff --git a/tools/ci/testrun/script/test_open_posix/test_openposix_.py b/tools/ci/testrun/script/test_open_posix/test_openposix_.py new file mode 100644 index 0000000000000..5585869862c0d --- /dev/null +++ b/tools/ci/testrun/script/test_open_posix/test_openposix_.py @@ -0,0 +1,11184 @@ +#!/usr/bin/python3 +# encoding: utf-8 +import pytest + +pytestmark = [pytest.mark.sim, pytest.mark.rv_virt] + + +def test_ltp_interfaces_mq_send_4_2(p): + ret = p.sendCommand( + "ltp_interfaces_mq_send_4_2", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigprocmask_12_1(p): +# ret = p.sendCommand( +# "ltp_interfaces_sigprocmask_12_1", +# ["PASSED", "passed", "Passed", "PASS"], +# timeout=10, +# ) +# retID = p.sendCommand("echo $?", "0", timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_timedwrlock_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_timedwrlock_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_9_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_9_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=30, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_condattr_destroy_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_condattr_destroy_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_cancel_2_2(p): + ret = p.sendCommand( + "ltp_interfaces_aio_cancel_2_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_18(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_18", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigaction_3_23(p): +# ret = p.sendCommand('ltp_interfaces_sigaction_3_23', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_41(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_41", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigismember_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigismember_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_time_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_time_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_unlock_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_unlock_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_37_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_37_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_signal_7_1(p): + ret = p.sendCommand("ltp_interfaces_signal_7_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_unlink_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_unlink_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_open_11_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_open_11_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_getvalue_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_getvalue_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_getdetachstate_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_getdetachstate_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_97(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_97", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_receive_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_receive_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mmap_6_4(p): + ret = p.sendCommand( + "ltp_interfaces_mmap_6_4", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_strlen_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_strlen_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_getcpuclockid_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_getcpuclockid_1_1", ["new thread"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_detach_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_detach_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_tryrdlock_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_tryrdlock_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_16(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_16", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sem_open_6_1(p): +# ret = p.sendCommand('ltp_interfaces_sem_open_6_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_pthread_getschedparam_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_getschedparam_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_wait_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_sem_wait_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_init_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_init_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_104(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_104", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_open_27_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_open_27_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_22(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_22", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_15(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_15", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_strcpy_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_strcpy_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_19(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_19", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_join_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_join_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_settime_9_1(p): + ret = p.sendCommand( + "ltp_interfaces_timer_settime_9_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_open_12_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_open_12_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_35(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_35", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_23(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_23", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigaction_4_84(p): +# ret = p.sendCommand( +# "ltp_interfaces_sigaction_4_84", +# ["PASSED", "passed", "Passed", "PASS"], +# timeout=10, +# ) +# retID = p.sendCommand("echo $?", "0", timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sched_setparam_25_1(p): + ret = p.sendCommand( + "ltp_interfaces_sched_setparam_25_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigset_1_1(p): + ret = p.sendCommand("ltp_interfaces_sigset_1_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_gettime_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_timer_gettime_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_12(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_12", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_settime_17_2(p): + ret = p.sendCommand( + "ltp_interfaces_clock_settime_17_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sched_setscheduler_19_3(p): +# ret = p.sendCommand('ltp_interfaces_sched_setscheduler_19_3', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigqueue_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigqueue_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_timer_gettime_speculative_6_1(p): + ret = p.sendCommand( + "ltp_timer_gettime_speculative_6_1", ["errno==EINVAL"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_setschedprio_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_setschedprio_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_destroy_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_destroy_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_69(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_69", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mmap_21_1(p): + ret = p.sendCommand( + "ltp_interfaces_mmap_21_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_61(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_61", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_timer_settime_speculative_12_3(p): + ret = p.sendCommand( + "ltp_timer_settime_speculative_12_3", ["errno==EINVAL"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_init_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_init_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_102(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_102", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_27(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_27", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_read_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_read_7_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigset_2_1(p): + ret = p.sendCommand("ltp_interfaces_sigset_2_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_7(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_7", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_send_4_3(p): + ret = p.sendCommand( + "ltp_interfaces_mq_send_4_3", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setschedpolicy_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setschedpolicy_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_close_3_2(p): + ret = p.sendCommand( + "ltp_interfaces_mq_close_3_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_nanosleep_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_nanosleep_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_93(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_93", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_getparam_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sched_getparam_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_receive_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_receive_8_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutex_destroy_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutex_destroy_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setinheritsched_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setinheritsched_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_rdlock_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_rdlock_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=30, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setscope_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setscope_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_fsync_14_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_fsync_14_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigaction_18_8(p): +# ret = p.sendCommand('ltp_interfaces_sigaction_18_8', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_raise_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_raise_2_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_51(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_51", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_munlock_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_munlock_7_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_setcancelstate_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_setcancelstate_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_8(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_8", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_55(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_55", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_75(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_75", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_sigmask_6_1(p): + ret = p.sendCommand("ltp_interfaces_pthread_sigmask_6_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_5(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_5", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutex_destroy_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutex_destroy_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigaction_4_85(p): +# ret = p.sendCommand('ltp_interfaces_sigaction_4_85', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_mq_open_7_3(p): + ret = p.sendCommand( + "ltp_interfaces_mq_open_7_3", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_77(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_77", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_lio_listio_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_lio_listio_8_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigaction_13_14(p): +# ret = p.sendCommand('ltp_interfaces_sigaction_13_14', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_pthread_kill_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_kill_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_25(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_25", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_clock_settime_speculative_4_4(p): + ret = p.sendCommand( + "ltp_clock_settime_speculative_4_4", + ["Implementation does repeat signals on clock reset", "clock reset"], + timeout=30, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_nanosleep_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_nanosleep_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_11_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_11_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_open_18_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_open_18_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_21(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_21", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_29_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_29_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_timer_settime_speculative_12_2(p): + ret = p.sendCommand( + "ltp_timer_settime_speculative_12_2", ["errno==EINVAL"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_12(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_12", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_open_15_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_open_15_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_8(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_8", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigset_4_1(p): + ret = p.sendCommand("ltp_interfaces_sigset_4_1", ["Inside handler"], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_7(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_7", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_gettime_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_gettime_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_7(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_7", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_settime_3_3(p): + ret = p.sendCommand( + "ltp_interfaces_timer_settime_3_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_23(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_23", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_3(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigignore_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigignore_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_53(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_53", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_barrierattr_setpshared_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_barrierattr_setpshared_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_barrier_wait_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_barrier_wait_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_17(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_17", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_open_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_sem_open_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigprocmask_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigprocmask_7_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_detach_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_detach_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_9(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_9", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_13(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_13", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_spin_trylock_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_spin_trylock_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigpause_1_1(p): + pytest.skip("unsupported") + ret = p.sendCommand( + "ltp_interfaces_sigpause_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_15_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_15_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_21(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_21", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_79(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_79", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigprocmask_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigprocmask_8_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sched_setscheduler_19_2(p): +# ret = p.sendCommand('ltp_interfaces_sched_setscheduler_19_2', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_init_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_init_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_4(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_4", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_definitions_errno_h_4_1(p): + ret = p.sendCommand("ltp_definitions_errno_h_4_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_init_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_init_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaddset_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_sigaddset_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_fsync_8_3(p): + ret = p.sendCommand( + "ltp_interfaces_aio_fsync_8_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_13(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_13", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_detach_4_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_detach_4_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigwait_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigwait_4_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_21(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_21", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutexattr_destroy_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutexattr_destroy_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_settime_8_2(p): + ret = p.sendCommand( + "ltp_interfaces_timer_settime_8_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_19(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_19", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_22(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_22", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_unlink_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_unlink_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaddset_1_3(p): + ret = p.sendCommand( + "ltp_interfaces_sigaddset_1_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_71(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_71", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setinheritsched_2_4(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setinheritsched_2_4", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_50(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_50", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setschedpolicy_1_3(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setschedpolicy_1_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_14_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_14_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_20(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_20", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_3(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_init_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_init_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_16(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_16", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_16(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_16", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_timedwrlock_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_timedwrlock_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedreceive_11_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedreceive_11_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_init_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_init_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_4(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_4", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigpending_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigpending_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigismember_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigismember_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_wait_11_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_wait_11_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlockattr_destroy_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlockattr_destroy_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutexattr_setpshared_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutexattr_setpshared_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_19(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_19", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_detach_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_detach_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_lio_listio_10_1(p): + ret = p.sendCommand( + "ltp_interfaces_lio_listio_10_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_sigmask_8_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_sigmask_8_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_write_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_write_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_99(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_99", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_asctime_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_asctime_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_mutexattr_gettype_1_4(p): +# ret = p.sendCommand('ltp_interfaces_pthread_mutexattr_gettype_1_4', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_19(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_19", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigfillset_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigfillset_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_settime_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_timer_settime_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=30, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_write_9_2(p): + ret = p.sendCommand( + "ltp_interfaces_aio_write_9_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_cancel_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_cancel_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_post_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_sem_post_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigtimedwait_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigtimedwait_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_barrierattr_init_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_barrierattr_init_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_9(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_9", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_send_14_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_send_14_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_kill_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_kill_2_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_60(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_60", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_get_priority_max_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sched_get_priority_max_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_11(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_11", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_mq_getattr_speculative_7_1(p): + ret = p.sendCommand( + "ltp_mq_getattr_speculative_7_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_setattr_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_setattr_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_kill_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_kill_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_create_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_create_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigwait_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigwait_6_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_behavior_WIFEXITED_1_2(p): + ret = p.sendCommand( + "ltp_behavior_WIFEXITED_1_2", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_write_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_write_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_settime_19_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_settime_19_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_return_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_return_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_definitions_signal_h_19_1(p): + ret = p.sendCommand("ltp_definitions_signal_h_19_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_rdlock_2_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_rdlock_2_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=30, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_read_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_read_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_26(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_26", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_49(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_49", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_40(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_40", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigpause_2_1(p): + pytest.skip("unsupported") + ret = p.sendCommand( + "ltp_interfaces_sigpause_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_4_3(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_4_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigfillset_2_1(p): + ret = p.sendCommand("ltp_interfaces_sigfillset_2_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mmap_24_1(p): + ret = p.sendCommand( + "ltp_interfaces_mmap_24_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigqueue_2_2(p): + ret = p.sendCommand( + "ltp_interfaces_sigqueue_2_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigprocmask_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigprocmask_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedreceive_13_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedreceive_13_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_notify_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_notify_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_9(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_9", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_fsync_12_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_fsync_12_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_14(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_14", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mmap_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_mmap_1_2", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_key_delete_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_key_delete_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_2(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_10(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_10", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigdelset_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigdelset_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_getparam_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_sched_getparam_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_19(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_19", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_getres_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_getres_8_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_open_20_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_open_20_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_23(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_23", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_13(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_13", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_6(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_6", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_close_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_close_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_unlink_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_unlink_7_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_fsync_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_fsync_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_sigmask_9_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_sigmask_9_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_cleanup_pop_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_cleanup_pop_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_self_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_self_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_mutexattr_gettype_1_2(p): +# ret = p.sendCommand('ltp_interfaces_pthread_mutexattr_gettype_1_2', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_12(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_12", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutexattr_getpshared_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutexattr_getpshared_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_timer_settime_speculative_12_1(p): + ret = p.sendCommand( + "ltp_timer_settime_speculative_12_1", ["errno==EINVAL"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_aio_error_3_1(p): +# ret = p.sendCommand('ltp_interfaces_aio_error_3_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sched_setscheduler_19_5(p): + ret = p.sendCommand( + "ltp_interfaces_sched_setscheduler_19_5", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_error_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_error_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_82(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_82", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_3(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigaction_12_33(p): +# ret = p.sendCommand('ltp_interfaces_sigaction_12_33', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_timedwrlock_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_timedwrlock_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_15(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_15", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_26(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_26", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_raise_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_raise_6_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_8_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_72(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_72", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_send_10_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_send_10_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigwaitinfo_8_1(p): + ret = p.sendCommand("ltp_interfaces_sigwaitinfo_8_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_timedrdlock_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_timedrdlock_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_17(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_17", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_read_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_read_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_ctime_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_ctime_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_receive_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_receive_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_18(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_18", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_timedwait_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_timedwait_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigwaitinfo_9_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigwaitinfo_9_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_write_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_write_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_6(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_6", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mmap_32_1(p): + ret = p.sendCommand( + "ltp_interfaces_mmap_32_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_16(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_16", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_24(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_24", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_11(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_11", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigqueue_8_1(p): + ret = p.sendCommand("ltp_interfaces_sigqueue_8_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_39_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_39_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_24(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_24", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_7_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_setparam_22_1(p): + ret = p.sendCommand( + "ltp_interfaces_sched_setparam_22_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_gettime_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_gettime_8_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_47(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_47", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_23(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_23", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_11(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_11", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_notify_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_notify_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_yield_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_sched_yield_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_killpg_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_killpg_8_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_barrierattr_init_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_barrierattr_init_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_init_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_init_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_10(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_10", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_open_15_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_open_15_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_setscheduler_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_sched_setscheduler_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_80(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_80", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_fsync_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_fsync_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaddset_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigaddset_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigpause_4_1(p): + pytest.skip("unsupported") + ret = p.sendCommand( + "ltp_interfaces_sigpause_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_19(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_19", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_lio_listio_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_lio_listio_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_aio_write_2_1(p): +# ret = p.sendCommand('ltp_interfaces_aio_write_2_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutexattr_setprotocol_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutexattr_setprotocol_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_attr_setstack_4_1(p): +# ret = p.sendCommand('ltp_interfaces_pthread_attr_setstack_4_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigpending_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_sigpending_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_38_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_38_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_spin_init_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_spin_init_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigemptyset_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigemptyset_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_unlink_4_2(p): + ret = p.sendCommand( + "ltp_interfaces_sem_unlink_4_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_send_11_2(p): + ret = p.sendCommand( + "ltp_interfaces_mq_send_11_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_sigmask_4_1(p): +# ret = p.sendCommand("ltp_interfaces_pthread_sigmask_4_1", [""], timeout=10) +# retID = p.sendCommand("echo $?", "0", timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_48(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_48", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigprocmask_6_1(p): +# ret = p.sendCommand('ltp_interfaces_sigprocmask_6_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_21(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_21", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigaction_13_7(p): +# ret = p.sendCommand('ltp_interfaces_sigaction_13_7', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_gmtime_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_gmtime_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_destroy_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_destroy_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_20(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_20", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_4(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_4", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_lio_listio_9_1(p): + ret = p.sendCommand( + "ltp_interfaces_lio_listio_9_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigtimedwait_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigtimedwait_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_59(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_59", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_11(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_11", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_fsync_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_fsync_8_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_post_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_post_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mmap_6_6(p): + ret = p.sendCommand( + "ltp_interfaces_mmap_6_6", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_barrierattr_setpshared_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_barrierattr_setpshared_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mmap_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_mmap_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_functional_semaphores_sem_philosopher(p): +# ret = p.sendCommand('ltp_functional_semaphores_sem_philosopher', ['ap>'], timeout=70) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + +# def test_ltp_definitions_aio_h_2_1(p): +# ret = p.sendCommand('ltp_definitions_aio_h_2_1', [''], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sched_get_priority_max_1_4(p): + ret = p.sendCommand( + "ltp_interfaces_sched_get_priority_max_1_4", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_join_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_join_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_25(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_25", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_getvalue_2_2(p): + ret = p.sendCommand( + "ltp_interfaces_sem_getvalue_2_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_3(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_kill_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_kill_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sighold_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sighold_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_sigmask_14_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_sigmask_14_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_settime_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_settime_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_timedwrlock_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_timedwrlock_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=30, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_init_2_2(p): + ret = p.sendCommand( + "ltp_interfaces_sem_init_2_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigtimedwait_4_1(p): +# ret = p.sendCommand('ltp_interfaces_sigtimedwait_4_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sem_wait_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_wait_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_25(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_25", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_notify_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_notify_8_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_5(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_5", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_26(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_26", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_open_13_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_open_13_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_send_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_send_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutexattr_init_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutexattr_init_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_2(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigignore_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigignore_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sighold_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_sighold_2_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_22(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_22", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_26(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_26", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_gettime_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_timer_gettime_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_29(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_29", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_condattr_getpshared_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_condattr_getpshared_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_26(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_26", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_5(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_5", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_raise_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_raise_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_28_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_28_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_15(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_15", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_3(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_raise_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_raise_7_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_cancel_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_cancel_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_mutexattr_settype_3_3(p): +# ret = p.sendCommand('ltp_interfaces_pthread_mutexattr_settype_3_3', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_pthread_cancel_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_cancel_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutex_trylock_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutex_trylock_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_unlink_9_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_unlink_9_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigdelset_1_4(p): + ret = p.sendCommand( + "ltp_interfaces_sigdelset_1_4", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_return_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_return_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_14(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_14", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_21_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_21_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_12(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_12", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_getres_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_getres_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_settime_20_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_settime_20_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_timer_settime_8_3(p): +# ret = p.sendCommand('ltp_interfaces_timer_settime_8_3', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_killpg_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_killpg_2_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_getvalue_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_getvalue_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_close_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_close_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigrelse_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigrelse_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_open_9_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_open_9_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_20(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_20", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_81(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_81", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_open_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_open_8_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_sigmask_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_sigmask_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_close_3_2(p): + ret = p.sendCommand( + "ltp_interfaces_sem_close_3_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_gmtime_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_gmtime_2_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigqueue_11_1(p): +# ret = p.sendCommand('ltp_interfaces_sigqueue_11_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_timer_getoverrun_speculative_6_2(p): + ret = p.sendCommand( + "ltp_timer_getoverrun_speculative_6_2", ["errno=EINVAL"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_20(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_20", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedreceive_15_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedreceive_15_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_5(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_5", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_setparam_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_sched_setparam_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_4_2(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_4_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_getcpuclockid_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_getcpuclockid_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_26(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_26", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_create_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_create_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_56(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_56", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_init_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_init_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_functional_semaphores_sem_conpro(p): + ret = p.sendCommand( + "ltp_functional_semaphores_sem_conpro", ["taken 900"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_88(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_88", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigqueue_6_1(p): + ret = p.sendCommand("ltp_interfaces_sigqueue_6_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_3(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_9(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_9", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_setspecific_1_2(p): +# ret = p.sendCommand('ltp_interfaces_pthread_setspecific_1_2', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_3(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_open_10_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_open_10_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigdelset_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigdelset_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_18_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_18_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_28(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_28", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_detach_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_detach_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_24(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_24", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutex_init_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutex_init_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_condattr_setpshared_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_condattr_setpshared_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_init_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_init_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_notify_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_notify_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_nanosleep_10000_1(p): + ret = p.sendCommand( + "ltp_interfaces_nanosleep_10000_1", ["All tests PASSED"], timeout=30 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigwait_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigwait_2_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_condattr_destroy_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_condattr_destroy_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_gettime_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_gettime_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_setattr_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_setattr_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_getvalue_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_getvalue_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_create_12_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_create_12_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_cond_init_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_cond_init_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_9_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_9_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_unlink_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_unlink_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_20(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_20", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_cond_init_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_cond_init_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutexattr_getpshared_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutexattr_getpshared_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_post_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_post_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_20_3(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_20_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigset_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigset_7_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_condattr_getclock_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_condattr_getclock_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_mq_unlink_1_1(p): +# ret = p.sendCommand('ltp_interfaces_mq_unlink_1_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=5) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sched_getscheduler_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sched_getscheduler_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_destroy_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_destroy_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_nanosleep_11_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_nanosleep_11_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_join_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_join_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_28_2(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_28_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_26_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_26_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mlock_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_mlock_5_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_localtime_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_localtime_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_cond_init_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_cond_init_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_2(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_21(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_21", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_getres_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_getres_7_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_cleanup_push_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_cleanup_push_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_11(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_11", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_21(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_21", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_6(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_6", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_open_2_2(p): + ret = p.sendCommand( + "ltp_interfaces_sem_open_2_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutexattr_destroy_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutexattr_destroy_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_7(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_7", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sched_getparam_3_1(p): +# ret = p.sendCommand('ltp_interfaces_sched_getparam_3_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaddset_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigaddset_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mmap_19_1(p): + ret = p.sendCommand( + "ltp_interfaces_mmap_19_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_24(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_24", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_gettime_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_gettime_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigrelse_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigrelse_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_timedwait_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_timedwait_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutex_timedlock_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutex_timedlock_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_6(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_6", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_pthread_key_create_speculative_5_1(p): + ret = p.sendCommand( + "ltp_pthread_key_create_speculative_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_10(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_10", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_settime_9_2(p): + ret = p.sendCommand( + "ltp_interfaces_timer_settime_9_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=30, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_8(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_8", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_setcancelstate_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_setcancelstate_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_lio_listio_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_lio_listio_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_6(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_6", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_receive_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_receive_7_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_attr_setinheritsched_2_1(p): +# ret = p.sendCommand('ltp_interfaces_pthread_attr_setinheritsched_2_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_11(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_11", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_write_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_write_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_18(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_18", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_92(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_92", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_fsync_8_2(p): + ret = p.sendCommand( + "ltp_interfaces_aio_fsync_8_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_open_19_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_open_19_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_mutexattr_settype_7_1(p): +# ret = p.sendCommand('ltp_interfaces_pthread_mutexattr_settype_7_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_4(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_4", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutexattr_gettype_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutexattr_gettype_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_83(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_83", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigtimedwait_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigtimedwait_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_receive_10_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_receive_10_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_8_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_delete_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_timer_delete_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigprocmask_10_1(p): +# ret = p.sendCommand('ltp_interfaces_sigprocmask_10_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_9(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_9", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_cancel_9_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_cancel_9_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_39_2(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_39_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_10(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_10", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_spin_destroy_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_spin_destroy_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_open_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_open_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigprocmask_17_1(p): +# ret = p.sendCommand( +# "ltp_interfaces_sigprocmask_17_1", +# ["PASSED", "passed", "Passed", "PASS"], +# timeout=10, +# ) +# retID = p.sendCommand("echo $?", "0", timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_11(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_11", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_mutex_init_4_1(p): +# ret = p.sendCommand('ltp_interfaces_pthread_mutex_init_4_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaltstack_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigaltstack_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_18(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_18", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_15(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_15", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_4(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_4", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_send_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_send_3_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_20_2(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_20_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_22_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_22_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_wrlock_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_wrlock_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_timedrdlock_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_timedrdlock_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_create_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_create_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigwaitinfo_2_1(p): + ret = p.sendCommand("ltp_interfaces_sigwaitinfo_2_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_44(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_44", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_clock_settime_17_1(p): +# ret = p.sendCommand('ltp_interfaces_clock_settime_17_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_sched_getparam_speculative_7_1(p): + ret = p.sendCommand("ltp_sched_getparam_speculative_7_1", ["NULL"], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_24(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_24", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_sigmask_8_3(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_sigmask_8_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_2(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_18(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_18", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_nanosleep_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_nanosleep_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_condattr_getpshared_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_condattr_getpshared_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_kill_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_kill_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setinheritsched_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setinheritsched_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedreceive_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedreceive_7_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_13(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_13", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_mq_timedreceive_speculative_10_2(p): + ret = p.sendCommand( + "ltp_mq_timedreceive_speculative_10_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigaction_28_15(p): +# ret = p.sendCommand('ltp_interfaces_sigaction_28_15', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_30(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_30", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigset_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigset_6_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_signal_3_1(p): + ret = p.sendCommand("ltp_interfaces_signal_3_1", ["Inside handler"], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_23(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_23", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_17(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_17", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_21(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_21", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_close_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_close_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_9(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_9", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sem_getvalue_2_1(p): +# ret = p.sendCommand('ltp_interfaces_sem_getvalue_2_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_pthread_sigmask_15_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_sigmask_15_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_91(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_91", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigismember_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigismember_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_setparam_23_1(p): + ret = p.sendCommand( + "ltp_interfaces_sched_setparam_23_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_sigmask_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_sigmask_8_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_14(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_14", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigdelset_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_sigdelset_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_mq_open_speculative_26_1(p): +# ret = p.sendCommand('ltp_mq_open_speculative_26_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_13_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_13_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_20(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_20", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_send_13_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_send_13_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_17_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_17_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaddset_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigaddset_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_gettime_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_timer_gettime_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_getscheduler_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_sched_getscheduler_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_getschedparam_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_getschedparam_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_read_11_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_read_11_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_14(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_14", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_lio_listio_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_lio_listio_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_definitions_errno_h_3_2(p): + ret = p.sendCommand("ltp_definitions_errno_h_3_2", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_condattr_init_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_condattr_init_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_9(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_9", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_90(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_90", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigprocmask_8_3(p): + ret = p.sendCommand( + "ltp_interfaces_sigprocmask_8_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigwait_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigwait_7_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutexattr_setprotocol_3_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutexattr_setprotocol_3_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_rr_get_interval_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sched_rr_get_interval_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigwaitinfo_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigwaitinfo_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_timedwait_11_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_timedwait_11_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_destroy_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_destroy_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mlock_10_1(p): + ret = p.sendCommand( + "ltp_interfaces_mlock_10_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_gettime_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_clock_gettime_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_cond_init_4_3(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_cond_init_4_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_post_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_post_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlockattr_getpshared_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlockattr_getpshared_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutexattr_getpshared_1_3(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutexattr_getpshared_1_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_munmap_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_munmap_8_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_74(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_74", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_6(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_6", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigprocmask_8_2(p): + ret = p.sendCommand( + "ltp_interfaces_sigprocmask_8_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_24(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_24", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_settime_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_settime_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_getres_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_getres_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_26(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_26", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_key_delete_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_key_delete_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_get_priority_min_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_sched_get_priority_min_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigaction_19_11(p): +# ret = p.sendCommand('ltp_interfaces_sigaction_19_11', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_22(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_22", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigtimedwait_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigtimedwait_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_mq_open_3_1(p): +# ret = p.sendCommand('ltp_interfaces_mq_open_3_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setschedparam_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setschedparam_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_attr_setstacksize_1_1(p): +# ret = p.sendCommand('ltp_interfaces_pthread_attr_setstacksize_1_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_pthread_rwlock_trywrlock_speculative_3_1(p): + ret = p.sendCommand( + "ltp_pthread_rwlock_trywrlock_speculative_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_timedwrlock_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_timedwrlock_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sem_open_2_1(p): +# ret = p.sendCommand('ltp_interfaces_sem_open_2_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlockattr_init_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlockattr_init_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=5) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_2(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_nanosleep_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_nanosleep_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_16(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_16", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_2(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_cancel_10_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_cancel_10_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_mlockall_8_1(p): +# ret = p.sendCommand('ltp_interfaces_mlockall_8_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_37(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_37", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_setcancelstate_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_setcancelstate_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutexattr_init_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutexattr_init_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sem_open_4_1(p): +# ret = p.sendCommand('ltp_interfaces_sem_open_4_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_10(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_10", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_5(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_5", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_setschedparam_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_setschedparam_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_3_2(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_3_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setschedparam_1_4(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setschedparam_1_4", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=5) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_2(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setdetachstate_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setdetachstate_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_init_5_2(p): + ret = p.sendCommand( + "ltp_interfaces_sem_init_5_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_68(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_68", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_key_create_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_key_create_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_mutexattr_gettype_1_3(p): +# ret = p.sendCommand('ltp_interfaces_pthread_mutexattr_gettype_1_3', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_aio_fsync_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_fsync_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_18(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_18", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutexattr_destroy_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutexattr_destroy_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlockattr_init_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlockattr_init_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_62(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_62", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_13(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_13", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_create_1_3(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_create_1_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlockattr_destroy_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlockattr_destroy_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_condattr_setclock_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_condattr_setclock_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_signal_6_1(p): + ret = p.sendCommand("ltp_interfaces_signal_6_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_equal_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_equal_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_19(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_19", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_36(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_36", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_timer_delete_speculative_5_2(p): + ret = p.sendCommand( + "ltp_timer_delete_speculative_5_2", ["errno=EINVAL"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_behavior_WIFEXITED_1_1(p): + ret = p.sendCommand( + "ltp_behavior_WIFEXITED_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mmap_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_mmap_5_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_cond_destroy_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_cond_destroy_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_19(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_19", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_10(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_10", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigaction_3_22(p): +# ret = p.sendCommand('ltp_interfaces_sigaction_3_22', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_munlock_11_1(p): + ret = p.sendCommand( + "ltp_interfaces_munlock_11_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_cleanup_pop_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_cleanup_pop_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_unlink_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_unlink_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_fsync_9_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_fsync_9_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_23(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_23", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigpause_3_1(p): + pytest.skip("unsupported") + ret = p.sendCommand( + "ltp_interfaces_sigpause_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutexattr_destroy_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutexattr_destroy_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_unlock_4_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_unlock_4_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigpending_1_3(p): + ret = p.sendCommand( + "ltp_interfaces_sigpending_1_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_cancel_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_cancel_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_26(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_26", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigaction_4_64(p): +# ret = p.sendCommand('ltp_interfaces_sigaction_4_64', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigwaitinfo_7_1(p): + ret = p.sendCommand("ltp_interfaces_sigwaitinfo_7_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigaction_2_8(p): +# ret = p.sendCommand('ltp_interfaces_sigaction_2_8', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigset_8_1(p): + ret = p.sendCommand("ltp_interfaces_sigset_8_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_4(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_4", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_read_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_read_8_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_get_priority_max_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_sched_get_priority_max_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_destroy_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_destroy_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_16(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_16", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_18(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_18", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_10(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_10", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_41_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_41_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_87(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_87", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_3(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_timer_create_speculative_15_1(p): + ret = p.sendCommand( + "ltp_timer_create_speculative_15_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_spin_lock_3_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_spin_lock_3_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_25(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_25", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigwait_6_2(p): + ret = p.sendCommand( + "ltp_interfaces_sigwait_6_2", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_18(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_18", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mmap_6_5(p): + ret = p.sendCommand( + "ltp_interfaces_mmap_6_5", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_post_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_post_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_setscheduler_19_1(p): + ret = p.sendCommand( + "ltp_interfaces_sched_setscheduler_19_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_create_16_1(p): + ret = p.sendCommand( + "ltp_interfaces_timer_create_16_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_setspecific_1_1(p): +# ret = p.sendCommand('ltp_interfaces_pthread_setspecific_1_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_4(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_4", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_killpg_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_killpg_5_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_21(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_21", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_receive_12_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_receive_12_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigqueue_4_1(p): + ret = p.sendCommand("ltp_interfaces_sigqueue_4_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sem_open_5_1(p): +# ret = p.sendCommand('ltp_interfaces_sem_open_5_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_12(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_12", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_timedrdlock_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_timedrdlock_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_init_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_init_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigpending_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigpending_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaltstack_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigaltstack_8_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=5) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigaction_23_10(p): +# ret = p.sendCommand('ltp_interfaces_sigaction_23_10', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_strchr_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_strchr_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_20(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_20", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_key_delete_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_key_delete_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_close_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_close_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedreceive_17_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedreceive_17_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_setscheduler_17_5(p): + ret = p.sendCommand( + "ltp_interfaces_sched_setscheduler_17_5", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_nanosleep_13_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_nanosleep_13_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_38(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_38", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_22(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_22", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_24(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_24", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_15(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_15", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_init_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_init_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_22(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_22", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_mutex_trylock_2_1(p): +# ret = p.sendCommand('ltp_interfaces_pthread_mutex_trylock_2_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_mktime_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_mktime_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigwaitinfo_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigwaitinfo_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_timedwait_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_timedwait_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_17(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_17", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_atfork_2_1(p): +# ret = p.sendCommand('ltp_interfaces_pthread_atfork_2_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_pthread_cleanup_push_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_cleanup_push_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_sigmask_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_sigmask_7_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_read_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_read_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_getinheritsched_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_getinheritsched_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedreceive_17_3(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedreceive_17_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_timedwait_6_2(p): + ret = p.sendCommand( + "ltp_interfaces_sem_timedwait_6_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_strftime_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_strftime_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_94(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_94", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_condattr_destroy_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_condattr_destroy_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_24(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_24", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_unlink_10_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_unlink_10_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_once_1_2(p): + ret = p.sendCommand("ltp_interfaces_pthread_once_1_2", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_25(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_25", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_43(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_43", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_unlink_11_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_unlink_11_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_attr_getstacksize_1_1(p): +# ret = p.sendCommand('ltp_interfaces_pthread_attr_getstacksize_1_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +# def test_ltp_interfaces_pthread_kill_6_1(p): +# ret = p.sendCommand("ltp_interfaces_pthread_kill_6_1", ["ESRCH"], timeout=10) +# retID = p.sendCommand("echo $?", "0", timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_15(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_15", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_42(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_42", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_15_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_15_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_condattr_getclock_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_condattr_getclock_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_killpg_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_killpg_6_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedreceive_14_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedreceive_14_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_13(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_13", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_mutexattr_setpshared_3_1(p): +# ret = p.sendCommand('ltp_interfaces_pthread_mutexattr_setpshared_3_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + +# def test_ltp_interfaces_aio_return_3_2(p): +# ret = p.sendCommand('ltp_interfaces_aio_return_3_2', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setdetachstate_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setdetachstate_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_write_8_2(p): + ret = p.sendCommand( + "ltp_interfaces_aio_write_8_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_13(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_13", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_cleanup_push_1_3(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_cleanup_push_1_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_lio_listio_13_1(p): + ret = p.sendCommand( + "ltp_interfaces_lio_listio_13_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_lio_listio_18_1(p): + ret = p.sendCommand( + "ltp_interfaces_lio_listio_18_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_spin_lock_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_spin_lock_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_getattr_2_2(p): + ret = p.sendCommand( + "ltp_interfaces_mq_getattr_2_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_mq_open_speculative_6_1(p): + ret = p.sendCommand("ltp_mq_open_speculative_6_1", ["does not fail"], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_cond_destroy_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_cond_destroy_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_setscheduler_17_1(p): + ret = p.sendCommand( + "ltp_interfaces_sched_setscheduler_17_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_17(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_17", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_11_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_11_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_19(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_19", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_settime_8_4(p): + ret = p.sendCommand( + "ltp_interfaces_timer_settime_8_4", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_28_3(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_28_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_key_create_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_key_create_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_70(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_70", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mmap_10_1(p): + ret = p.sendCommand( + "ltp_interfaces_mmap_10_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_once_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_once_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_unlink_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_unlink_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_write_9_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_write_9_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_5(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_5", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_attr_setstacksize_4_1(p): +# ret = p.sendCommand('ltp_interfaces_pthread_attr_setstacksize_4_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_19_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_19_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_wait_13_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_wait_13_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_trywrlock_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_trywrlock_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedreceive_17_2(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedreceive_17_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_lio_listio_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_lio_listio_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigwait_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigwait_3_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_lio_listio_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_lio_listio_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_settime_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_timer_settime_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_103(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_103", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setstack_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setstack_7_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_rdlock_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_rdlock_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setdetachstate_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setdetachstate_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_functional_semaphores_sem_sleepingbarber(p): +# ret = p.sendCommand('ltp_functional_semaphores_sem_sleepingbarber', ['nice hair.'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_definitions_signal_h_13_1(p): + ret = p.sendCommand( + "ltp_definitions_signal_h_13_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_31(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_31", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_timer_gettime_speculative_6_2(p): + ret = p.sendCommand( + "ltp_timer_gettime_speculative_6_2", ["errno==EINVAL"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_13_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_13_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_52(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_52", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_54(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_54", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_attr_setschedparam_1_1(p): +# ret = p.sendCommand('ltp_interfaces_pthread_attr_setschedparam_1_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_raise_10000_1(p): + ret = p.sendCommand( + "ltp_interfaces_raise_10000_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_9(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_9", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_9(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_9", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_open_1_4(p): + ret = p.sendCommand( + "ltp_interfaces_sem_open_1_4", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedreceive_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedreceive_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_definitions_aio_h_4_1(p): + ret = p.sendCommand("ltp_definitions_aio_h_4_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_3(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_mutex_trylock_1_2(p): +# ret = p.sendCommand('ltp_interfaces_pthread_mutex_trylock_1_2', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + +# def test_ltp_interfaces_aio_fsync_5_1(p): +# ret = p.sendCommand('ltp_interfaces_aio_fsync_5_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_86(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_86", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_12(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_12", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_26(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_26", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_9(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_9", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_gettime_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_gettime_7_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigaction_8_17(p): +# ret = p.sendCommand('ltp_interfaces_sigaction_8_17', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_15(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_15", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_14(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_14", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_7(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_7", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_5(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_5", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_76(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_76", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_mutex_destroy_2_2(p): +# ret = p.sendCommand('ltp_interfaces_pthread_mutex_destroy_2_2', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_11_2(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_11_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_getdetachstate_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_getdetachstate_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_definitions_signal_h_26_1(p): + ret = p.sendCommand("ltp_definitions_signal_h_26_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_exit_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_exit_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_timedwait_2_2(p): + ret = p.sendCommand( + "ltp_interfaces_sem_timedwait_2_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_22(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_22", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_7(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_7", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_21(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_21", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_12(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_12", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_open_29_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_open_29_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigprocmask_4_1(p): +# ret = p.sendCommand( +# "ltp_interfaces_sigprocmask_4_1", +# ["PASSED", "passed", "Passed", "PASS"], +# timeout=10, +# ) +# retID = p.sendCommand("echo $?", "0", timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setschedpolicy_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setschedpolicy_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_barrierattr_getpshared_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_barrierattr_getpshared_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_kill_7_1(p): + ret = p.sendCommand("ltp_interfaces_pthread_kill_7_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_post_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_post_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_mutexattr_gettype_1_5(p): +# ret = p.sendCommand('ltp_interfaces_pthread_mutexattr_gettype_1_5', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_pthread_condattr_destroy_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_condattr_destroy_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setschedparam_1_3(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setschedparam_1_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_functional_semaphores_sem_readerwriter(p): +# ret = p.sendCommand('ltp_functional_semaphores_sem_readerwriter', ['exit.'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_mq_timedsend_speculative_18_2(p): + ret = p.sendCommand( + "ltp_mq_timedsend_speculative_18_2", ["did not fail"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_cancel_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_cancel_8_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_mq_send_9_1(p): +# ret = p.sendCommand('ltp_interfaces_mq_send_9_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_mq_send_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_send_2_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigwait_8_1(p): +# ret = p.sendCommand('ltp_interfaces_sigwait_8_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + +# def test_ltp_interfaces_sigwait_1_1(p): +# ret = p.sendCommand('ltp_interfaces_sigwait_1_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_78(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_78", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_16_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_16_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_attr_setstack_6_1(p): +# ret = p.sendCommand('ltp_interfaces_pthread_attr_setstack_6_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setschedpolicy_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setschedpolicy_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_kill_2_1(p): +# ret = p.sendCommand('ltp_interfaces_pthread_kill_2_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_timedrdlock_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_timedrdlock_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_init_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_init_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_25(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_25", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_strftime_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_strftime_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutexattr_setpshared_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutexattr_setpshared_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_open_23_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_open_23_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_getpid_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_getpid_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_wait_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_wait_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_fsync_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_fsync_7_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_8(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_8", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_unlink_10_2(p): + ret = p.sendCommand( + "ltp_interfaces_shm_unlink_10_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mmap_27_1(p): + ret = p.sendCommand( + "ltp_interfaces_mmap_27_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_get_priority_min_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sched_get_priority_min_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_20(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_20", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigqueue_10_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigqueue_10_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_12(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_12", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_pthread_join_speculative_6_1(p): + ret = p.sendCommand( + "ltp_pthread_join_speculative_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_sigmask_16_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_sigmask_16_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_unlink_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_unlink_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigemptyset_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigemptyset_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_58(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_58", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_wrlock_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_wrlock_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=30, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_20(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_20", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_mq_unlink_speculative_7_2(p): + ret = p.sendCommand( + "ltp_mq_unlink_speculative_7_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigset_9_1(p): + ret = p.sendCommand("ltp_interfaces_sigset_9_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_21(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_21", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_close_3_3(p): + ret = p.sendCommand( + "ltp_interfaces_mq_close_3_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_rwlock_rdlock_1_1(p): +# ret = p.sendCommand('ltp_interfaces_pthread_rwlock_rdlock_1_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigignore_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigignore_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_8(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_8", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_7(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_7", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_open_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_open_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_nanosleep_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_nanosleep_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_shm_open_25_1(p): +# ret = p.sendCommand( +# "ltp_interfaces_shm_open_25_1", +# ["PASSED", "passed", "Passed", "PASS"], +# timeout=10, +# ) +# retID = p.sendCommand("echo $?", "0", timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sem_wait_12_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_wait_12_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_lio_listio_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_lio_listio_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_get_priority_max_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_sched_get_priority_max_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_5(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_5", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_pthread_getcpuclockid_speculative_3_1(p): + ret = p.sendCommand( + "ltp_pthread_getcpuclockid_speculative_3_1", ["doesn't exist"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_create_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_create_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_65(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_65", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_getattr_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_getattr_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_getscheduler_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_sched_getscheduler_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_10(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_10", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_wait_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_wait_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_once_2_1(p): + ret = p.sendCommand("ltp_interfaces_pthread_once_2_1", [""], timeout=20) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutexattr_setpshared_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutexattr_setpshared_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_difftime_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_difftime_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_getschedparam_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_getschedparam_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_12_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_12_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_23(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_23", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_killpg_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_killpg_4_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_15(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_15", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_setattr_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_setattr_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigaction_19_15(p): +# ret = p.sendCommand('ltp_interfaces_sigaction_19_15', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + +# def test_ltp_interfaces_fsync_5_1(p): +# ret = p.sendCommand('ltp_interfaces_fsync_5_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigset_5_1(p): + ret = p.sendCommand("ltp_interfaces_sigset_5_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_14(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_14", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_open_1_3(p): + ret = p.sendCommand( + "ltp_interfaces_sem_open_1_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_3(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_send_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_send_4_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigaction_6_14(p): +# ret = p.sendCommand('ltp_interfaces_sigaction_6_14', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_23(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_23", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_fork_1_1(p): +# ret = p.sendCommand('ltp_interfaces_fork_1_1', [''], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_4(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_4", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_12(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_12", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_barrier_destroy_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_barrier_destroy_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_13(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_13", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_10(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_10", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_2(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=5) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigwaitinfo_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigwaitinfo_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_timer_getoverrun_speculative_6_1(p): +# ret = p.sendCommand('ltp_timer_getoverrun_speculative_6_1', ['errno=EINVAL'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_89(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_89", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_14(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_14", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_25(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_25", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_100(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_100", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_timer_gettime_speculative_6_3(p): + ret = p.sendCommand( + "ltp_timer_gettime_speculative_6_3", ["errno==EINVAL"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_join_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_join_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_timedwait_10_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_timedwait_10_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_24(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_24", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_25(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_25", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_18(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_18", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_suspend_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_suspend_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigaction_18_16(p): +# ret = p.sendCommand('ltp_interfaces_sigaction_18_16', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_pthread_condattr_setpshared_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_condattr_setpshared_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_condattr_setclock_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_condattr_setclock_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_write_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_write_8_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_strftime_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_strftime_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_unlock_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_unlock_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_73(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_73", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_aio_write_1_2(p): +# ret = p.sendCommand('ltp_interfaces_aio_write_1_2', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_mq_getattr_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_getattr_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_setattr_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_mq_setattr_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_get_priority_min_1_4(p): + ret = p.sendCommand( + "ltp_interfaces_sched_get_priority_min_1_4", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_11(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_11", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutexattr_setpshared_3_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutexattr_setpshared_3_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_fsync_8_4(p): + ret = p.sendCommand( + "ltp_interfaces_aio_fsync_8_4", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_8(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_8", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_67(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_67", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_25(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_25", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_create_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_timer_create_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_getschedpolicy_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_getschedpolicy_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_join_6_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_join_6_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_settime_3_2(p): + ret = p.sendCommand( + "ltp_interfaces_timer_settime_3_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_destroy_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_destroy_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_unlink_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_unlink_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_5(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_5", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sched_setscheduler_19_4(p): +# ret = p.sendCommand('ltp_interfaces_sched_setscheduler_19_4', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_13(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_13", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_unlink_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_unlink_7_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_barrier_destroy_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_barrier_destroy_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_19_16(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_19_16", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_setschedparam_1_2(p): + ret = p.sendCommand("ltp_interfaces_pthread_setschedparam_1_2", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_63(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_63", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_send_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_send_8_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_34(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_34", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_setschedparam_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_setschedparam_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_unlink_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_unlink_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_send_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_send_7_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_read_3_2(p): + ret = p.sendCommand( + "ltp_interfaces_aio_read_3_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_12(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_12", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_39(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_39", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_signal_5_1(p): + ret = p.sendCommand("ltp_interfaces_signal_5_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_16(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_16", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_barrier_init_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_barrier_init_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_7(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_7", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigprocmask_9_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigprocmask_9_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_46(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_46", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_25(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_25", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sigqueue_7_1(p): +# ret = p.sendCommand( +# "ltp_interfaces_sigqueue_7_1", ["1, 2, 3", "62, 63,"], timeout=10 +# ) +# retID = p.sendCommand("echo $?", "0", timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_mq_open_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_open_7_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_mq_open_speculative_2_2(p): +# ret = p.sendCommand('ltp_mq_open_speculative_2_2', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_pthread_barrier_wait_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_barrier_wait_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_timers_clocks_invaliddates(p): + ret = p.sendCommand( + "ltp_timers_clocks_invaliddates", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_mq_open_speculative_2_3(p): + ret = p.sendCommand( + "ltp_mq_open_speculative_2_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigdelset_1_3(p): + ret = p.sendCommand( + "ltp_interfaces_sigdelset_1_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setscope_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setscope_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_getattr_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_getattr_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_14(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_14", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_receive_11_2(p): + ret = p.sendCommand( + "ltp_interfaces_mq_receive_11_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sched_rr_get_interval_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_sched_rr_get_interval_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_attr_getstack_1_1(p): +# ret = p.sendCommand('ltp_interfaces_pthread_attr_getstack_1_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_7(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_7", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_sched_rr_get_interval_speculative_5_1(p): + ret = p.sendCommand( + "ltp_sched_rr_get_interval_speculative_5_1", ["NULL"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_13(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_13", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_read_10_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_read_10_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_mutexattr_getpshared_1_2(p): +# ret = p.sendCommand('ltp_interfaces_pthread_mutexattr_getpshared_1_2', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_raise_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_raise_4_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_strncpy_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_strncpy_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setinheritsched_2_3(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setinheritsched_2_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=5) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigset_10_1(p): + ret = p.sendCommand("ltp_interfaces_sigset_10_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_settime_8_1(p): + ret = p.sendCommand( + "ltp_interfaces_timer_settime_8_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_open_21_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_open_21_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_95(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_95", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedreceive_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedreceive_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_nanosleep_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_nanosleep_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_behavior_timers_2_1(p): + ret = p.sendCommand( + "ltp_behavior_timers_2_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_aio_return_3_1(p): +# ret = p.sendCommand('ltp_interfaces_aio_return_3_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sighold_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_sighold_3_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_setcancelstate_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_setcancelstate_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_20_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_20_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlock_timedrdlock_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlock_timedrdlock_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_raise_1_2(p): +# ret = p.sendCommand('ltp_interfaces_raise_1_2', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_clock_getres_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_getres_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_getspecific_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_getspecific_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_20(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_20", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_signal_1_1(p): + ret = p.sendCommand("ltp_interfaces_signal_1_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_fsync_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_fsync_4_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_barrierattr_destroy_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_barrierattr_destroy_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_6(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_6", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_17(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_17", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_45(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_45", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setdetachstate_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setdetachstate_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_behavior_timers_1_1(p): + ret = p.sendCommand( + "ltp_behavior_timers_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_8(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_8", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_open_25_2(p): + ret = p.sendCommand( + "ltp_interfaces_mq_open_25_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_attr_setinheritsched_2_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_attr_setinheritsched_2_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_66(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_66", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_16(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_16", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_gettime_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_timer_gettime_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_8(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_8", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_sem_unlink_6_1(p): +# ret = p.sendCommand('ltp_interfaces_sem_unlink_6_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_timer_getoverrun_speculative_6_3(p): + ret = p.sendCommand( + "ltp_timer_getoverrun_speculative_6_3", ["errno==EINVAL"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_mutexattr_settype_1_1(p): +# ret = p.sendCommand('ltp_interfaces_pthread_mutexattr_settype_1_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_aio_cancel_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_cancel_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_2(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_signal_2_1(p): + ret = p.sendCommand("ltp_interfaces_signal_2_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutex_init_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutex_init_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_definitions_sched_h_10_1(p): + ret = p.sendCommand("ltp_definitions_sched_h_10_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigset_3_1(p): + ret = p.sendCommand("ltp_interfaces_sigset_3_1", ["Inside handler"], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_nanosleep_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_nanosleep_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigrelse_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigrelse_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_cancel_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_cancel_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedsend_20_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedsend_20_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_send_3_2(p): + ret = p.sendCommand( + "ltp_interfaces_mq_send_3_2", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_timer_delete_speculative_5_1(p): + ret = p.sendCommand( + "ltp_timer_delete_speculative_5_1", ["errno=EINVAL"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +# def test_ltp_interfaces_pthread_attr_setstack_1_1(p): +# ret = p.sendCommand('ltp_interfaces_pthread_attr_setstack_1_1', ['PASSED', 'passed', 'Passed', 'PASS'], timeout=10) +# retID = p.sendCommand('echo $?', '0', timeout=2) +# assert ret >= 0 +# assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_19(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_19", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_4(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_4", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_clock_getres_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_clock_getres_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedreceive_10_2(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedreceive_10_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_create_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_create_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_12_32(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_12_32", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_5(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_5", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_testcancel_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_testcancel_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_condattr_setclock_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_condattr_setclock_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_timedwait_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_timedwait_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_read_5_1(p): + ret = p.sendCommand( + "ltp_interfaces_aio_read_5_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_18(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_18", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_17(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_17", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_2_22(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_2_22", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_stress_signals_sigismember_stress_1(p): + ret = p.sendCommand("ltp_stress_signals_sigismember_stress_1", [""], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_definitions_mqueue_h_1_1(p): + ret = p.sendCommand( + "ltp_definitions_mqueue_h_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_condattr_setclock_1_3(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_condattr_setclock_1_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_killpg_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_killpg_1_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_timedreceive_10_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_timedreceive_10_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_send_11_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_send_11_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_barrier_init_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_barrier_init_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlockattr_setpshared_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlockattr_setpshared_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_close_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_close_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_open_14_2(p): + ret = p.sendCommand( + "ltp_interfaces_shm_open_14_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mmap_23_1(p): + ret = p.sendCommand( + "ltp_interfaces_mmap_23_1", ["PASSED", "passed", "Passed", "PASS"], timeout=10 + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_close_2_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_close_2_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_condattr_setpshared_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_condattr_setpshared_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigqueue_9_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigqueue_9_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_lio_listio_12_1(p): + ret = p.sendCommand( + "ltp_interfaces_lio_listio_12_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_lio_listio_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_lio_listio_7_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutex_destroy_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutex_destroy_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_cancel_4_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_cancel_4_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_timedwait_7_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_timedwait_7_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_rwlockattr_getpshared_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_rwlockattr_getpshared_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_8_6(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_8_6", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_gettime_2_2(p): + ret = p.sendCommand( + "ltp_interfaces_timer_gettime_2_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigignore_6_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigignore_6_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_28_22(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_28_22", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_17(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_17", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigprocmask_15_1(p): + ret = p.sendCommand( + "ltp_interfaces_sigprocmask_15_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_shm_unlink_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_shm_unlink_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_96(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_96", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_18_6(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_18_6", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_23(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_23", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_101(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_101", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_gettime_1_3(p): + ret = p.sendCommand( + "ltp_interfaces_timer_gettime_1_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_6(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_6", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_sigmask_12_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_sigmask_12_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_3_26(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_3_26", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_23_4(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_23_4", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_aio_read_11_2(p): + ret = p.sendCommand( + "ltp_interfaces_aio_read_11_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_mq_receive_11_1(p): + ret = p.sendCommand( + "ltp_interfaces_mq_receive_11_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_6_11(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_6_11", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sem_init_3_1(p): + ret = p.sendCommand( + "ltp_interfaces_sem_init_3_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_lio_listio_15_1(p): + ret = p.sendCommand( + "ltp_interfaces_lio_listio_15_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_1_17(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_1_17", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_13_24(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_13_24", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_delete_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_timer_delete_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_stress_semaphores_multi_con_pro(p): + ret = p.sendCommand("ltp_stress_semaphores_multi_con_pro 5", ["exit."], timeout=10) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutexattr_setpshared_2_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutexattr_setpshared_2_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_mutexattr_getprotocol_1_1(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_mutexattr_getprotocol_1_1", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_pthread_create_1_2(p): + ret = p.sendCommand( + "ltp_interfaces_pthread_create_1_2", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_98(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_98", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_sigaction_4_57(p): + ret = p.sendCommand( + "ltp_interfaces_sigaction_4_57", + ["PASSED", "passed", "Passed", "PASS"], + timeout=10, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 + + +def test_ltp_interfaces_timer_settime_5_3(p): + ret = p.sendCommand( + "ltp_interfaces_timer_settime_5_3", + ["PASSED", "passed", "Passed", "PASS"], + timeout=200, + ) + retID = p.sendCommand("echo $?", "0", timeout=2) + assert ret >= 0 + assert retID >= 0 diff --git a/tools/ci/testrun/script/test_os/test_os.py b/tools/ci/testrun/script/test_os/test_os.py index bd8c6f393863a..5028ccb266eb8 100644 --- a/tools/ci/testrun/script/test_os/test_os.py +++ b/tools/ci/testrun/script/test_os/test_os.py @@ -1,5 +1,7 @@ #!/usr/bin/env python3 # encoding: utf-8 +import os + import pytest pytestmark = [pytest.mark.common, pytest.mark.qemu] @@ -7,14 +9,18 @@ def test_ostest(p): - ret = p.sendCommand("ostest", "Exiting with status 0", 300) + if p.board == "sim": + os.mkdir("./test") + ret = p.sendCommand("mount -t hostfs -o fs=./test /data") + + ret = p.sendCommand("ostest", "Exiting with status 0", timeout=300) assert ret == 0 def test_mm(p): if p.board in do_not_support: pytest.skip("unsupported at {}".format(p.board)) - ret = p.sendCommand("mm", "TEST COMPLETE", 120) + ret = p.sendCommand("mm", "TEST COMPLETE", timeout=120) assert ret == 0 @@ -56,9 +62,12 @@ def test_fs_test(p): pytest.skip("unsupported at {}".format(p.board)) fstest_dir = "{}/{}_fstest".format(p.fs, p.core) p.sendCommand("mkdir %s" % fstest_dir) - ret = p.sendCommand("fstest -n 10 -m %s" % fstest_dir, "FAILED: 0", 2000) + ret = p.sendCommand("fstest -n 10 -m %s" % fstest_dir, "FAILED: 0", timeout=2000) p.sendCommand("ls %s" % fstest_dir) p.sendCommand("rmdir %s" % fstest_dir) + + if p.board == "sim": + os.rmdir("./test") assert ret == 0 @@ -67,6 +76,6 @@ def test_psram_test(p): if p.board in do_not_support: pytest.skip("unsupported at {}".format(p.board)) if p.sendCommand("ls /", "tmp/") == 0: - ret = p.sendCommand("fstest -n 10 -m /tmp", "Final memory usage", 500) + ret = p.sendCommand("fstest -n 10 -m /tmp", "Final memory usage", timeout=500) p.sendCommand("ls /tmp") assert ret == 0 diff --git a/tools/ci/testrun/utils/common.py b/tools/ci/testrun/utils/common.py index 63ff550e7de4f..3dc64584408fd 100644 --- a/tools/ci/testrun/utils/common.py +++ b/tools/ci/testrun/utils/common.py @@ -4,13 +4,43 @@ import re import subprocess import time +from enum import Enum import pexpect import pexpect.fdpexpect +import pexpect.spawnbase import serial rootPath = os.path.dirname(os.path.abspath(__file__)) +tmp_read_nonblocking = pexpect.spawnbase.SpawnBase.read_nonblocking + + +def enhanced_read_nonblocking(self, size=1, timeout=None): + return re.sub( + r"(\x9B|\x1B\[)[0-?]*[ -\/]*[@-~]", + "", + tmp_read_nonblocking(self, size, timeout).decode(errors="ignore"), + ).encode() + + +pexpect.spawnbase.SpawnBase.read_nonblocking = enhanced_read_nonblocking + + +class StatusCodeEnum(Enum): + NORMAL = (0, "Normal") + TIMEOUT_ERR = (-1, "Timeout") + EOF_ERR = (-2, "EOF") + CRASH_ERR = (-3, "Crash happened") + BUSYLOOP_ERR = (-4, "Busy loop happened") + UNKNOWN_ERR = (-5, "Unknown") + + @staticmethod + def get_enum_msg_by_code(status_code): + for status in StatusCodeEnum: + if status.value[0] == status_code: + return status.value[1] + class connectNuttx(object): def __init__( @@ -40,6 +70,7 @@ def __init__( self.target = target self.enter = "\r" self.debug_flag = 0 + self.format_str_len = 105 # get PROMPT value and rate value self.PROMPT = getConfigValue( self.path, self.board, core=self.core, flag="NSH_PROMPT_STRING" @@ -107,38 +138,130 @@ def sendControlCmd(self, cmd, expect="ap>", timeout=10): self.process.send(byte) time.sleep(1) self.process.send(byte) - time.sleep(1) - self.process.sendline("\n") - ret = self.process.expect_exact(expect) - return ret + + def print_format_str(self, string, type="text"): + str_prefix = "+" + str_suffix = "+" + + if type == "head": + rest_char_len = self.format_str_len - 2 - len(string) + half_len = int(rest_char_len / 2) + print( + str_prefix + + "-" * half_len + + string + + "-" * (rest_char_len - half_len) + + str_suffix + ) + elif type == "tail": + rest_char_len = self.format_str_len - 2 + print(str_prefix + "-" * rest_char_len + str_suffix) + elif type == "text": + str_prefix = "| " + str_suffix = " |" + rest_char_len = ( + self.format_str_len - len(str_prefix) - len(str_suffix) - len(string) + ) + print( + str_prefix + + string + + " " * (1 if rest_char_len < 1 else rest_char_len) + + str_suffix + ) + else: + print(string) + + def clean_buffer(self): + i = -1 + while True: + if ( + ( + self.process.before is not None + and self.process.before.decode(errors="ignore") + .replace("\r", "") + .replace("\n", "") + != "" + ) + or ( + self.process.after is not None + and self.process.after != pexpect.TIMEOUT + and self.process.after.decode(errors="ignore") + .replace("\r", "") + .replace("\n", "") + != "" + ) + or i == 0 + ): + i = self.process.expect( + [re.compile(b".+"), pexpect.TIMEOUT, pexpect.EOF], timeout=0.1 + ) + else: + while True: + try: + self.process.read_nonblocking( + size=self.process.maxread, timeout=0.1 + ) + except Exception: + break + self.process.before = b"" + self.process.after = b"" + break # send command to nsh - def sendCommand(self, cmd, expect="", timeout=10, flag=""): + def sendCommand(self, cmd, *argc, **argv): + expect = [] + timeout = 10 + ret = StatusCodeEnum.NORMAL.value[0] + length = len(argc) + if length == 0: + expect.append(self.PROMPT) + else: + for i in argc: + expect.append(i) + length = len(argv) + if length != 0: + for key, value in argv.items(): + if key == "timeout": + timeout = value if self.method != "minicom": time.sleep(0.5) - if not expect: - expect = self.PROMPT - self.process.buffer = b"" - self.process.sendline(cmd) + if self.target == "qemu": + self.clean_buffer() + self.process.sendline(cmd) + else: + self.clean_buffer() + self.process.sendline(cmd) + time.sleep(0.1) + self.process.send("\r\n\r\n") try: - ret = self.process.expect(expect, timeout=timeout) - except pexpect.TIMEOUT: - print("Debug: TIMEOUT '%s' exist and run next test case" % cmd) - ret = -1 - except pexpect.EOF: - print("Debug: EOF raise exception") - ret = -2 - finally: - if self.debug_flag: - self.debug(cmd, ret) - self.process.buffer = b"" - self.process.sendline("\n") - if flag: - is_newline = self.process.expect_exact(flag, timeout=timeout) + for i in expect: + ret = self.process.expect(i, timeout=timeout) + except Exception as e: + self.print_format_str(" Catch Exception ", type="head") + + if isinstance(e, pexpect.TIMEOUT): + ret = StatusCodeEnum.TIMEOUT_ERR.value[0] + + elif isinstance(e, pexpect.EOF): + ret = StatusCodeEnum.EOF_ERR.value[0] + self.print_format_str(f"An pexpect.EOF error occurred: {str(e)}") + else: - is_newline = self.process.expect_exact(self.PROMPT, timeout=timeout) - if self.debug_flag: - self.debug("NEWLINE", is_newline) + ret = StatusCodeEnum.UNKNOWN_ERR.value[0] + self.print_format_str(f"An unexpected error occurred: {str(e)}") + + self.print_format_str(" Result ", type="head") + self.print_format_str(f"Command : '{cmd}'") + self.print_format_str(f"Expect value: {str(expect)}") + self.print_format_str(f"Timeout : {timeout}s") + self.print_format_str( + f"Test result : {StatusCodeEnum.get_enum_msg_by_code(ret)}" + ) + self.print_format_str("", type="tail") + + finally: + self.debug(cmd, ret) + if self.method != "minicom": time.sleep(0.5) return ret @@ -151,15 +274,16 @@ def switch_to_original_core(self): self.process.expect_exact(self.PROMPT) def debug(self, cmd, ret): - print("********************* DEBUG START ********************") - if cmd == "\n": - cmd = r"\n" - print("cmd: %s\n" % cmd) - print("ret: %s\n" % str(ret)) - print("before: %s\n" % repr(self.process.before)) - print("after: %s\n" % repr(self.process.after)) - print("buffer: %s\n" % repr(self.process.buffer)) - print("********************** DEBUG END **********************") + if self.debug_flag: + print("********************* DEBUG START ********************") + if cmd == "\n": + cmd = r"\n" + print("cmd: {}".format(cmd)) + print("ret: {}".format(ret)) + print("before: {}".format(self.process.before.decode(errors="ignore"))) + print("after: {}".format(self.process.after.decode(errors="ignore"))) + print("buffer: {}".format(self.process.buffer.decode(errors="ignore"))) + print("********************** DEBUG END **********************") def cleanup(self): if self.target == "sim": @@ -220,15 +344,26 @@ def startQemu(self, path, log_path, board="qemu", sudo=False): ) if flag1 == "qemu-rv": flag2 = getConfigValue(path, board, core=None, flag="ARCH_RV64") + options = "" if flag2: riscv = "qemu-system-riscv64" else: riscv = "qemu-system-riscv32" + fs_flag = getConfigValue(path, board, core=None, flag="DRIVERS_VIRTIO_BLK") + if fs_flag: + os.system("dd if=/dev/zero of=fatfs.img bs=512 count=128K") + os.system("mkfs.fat fatfs.img") + os.system("chmod 777 ./fatfs.img") + options = ( + "-drive index=0,id=userdata,if=none,format=raw,file=./fatfs.img " + "-device virtio-blk-device,bus=virtio-mmio-bus.0,drive=userdata" + ) self.process = pexpect.spawn( "bash", [ "-c", - "%s -M virt -bios ./nuttx -nographic | tee %s" % (riscv, self.log), + "%s -M virt -bios ./nuttx -nographic %s | tee %s" + % (riscv, options, self.log), ], ) self.process.expect(self.PROMPT) diff --git a/tools/ci/testrun/utils/data_model.py b/tools/ci/testrun/utils/data_model.py new file mode 100644 index 0000000000000..ef74645631c7d --- /dev/null +++ b/tools/ci/testrun/utils/data_model.py @@ -0,0 +1,235 @@ +import re +from datetime import datetime +from typing import Dict, List + +""" +cmocka.json +""" + +Passed = "Passed" +Failed = "Failed" +Unexecuted = "Unexecuted" + + +class CaseInfo: + def __init__(self, test_suite_name, test_case_name, status, log=None): + self.test_suite_name = test_suite_name + # case name，e.g. "TestNuttxMm01" + self.test_case_name = test_case_name + # result: Passed or Failed + self.status = status + # log + self.log: List = [""] if log is None else log + + +class SuiteInfo: + def __init__(self, test_suite_name): + # suite name, e.g. "NuttxMmTestSuites" + self.test_suite_name = test_suite_name + # all test cases in the current test suite + self.test_cases: Dict[str, CaseInfo] = dict() + # number of cases passed in the current test suites + self.passed_count = 0 + # number of cases failed in the current test suites + self.failed_count = 0 + # case run count + self.run_count = 0 + # unexecuted count + self.unexecuted_count = 0 + # number of cases in the current test suites + self.cases_count = 0 + # suite run flag + self.is_suite_run = False + + +class CmockaSummary: + def __init__(self, duration=0): + # number of all test suites + self.total_suites_count = 0 + # all test cases number + self.total_cases_count = 0 + # number of all passed cases + self.total_passed_count = 0 + # number of all failed cases + self.total_failed_count = 0 + # number of all unknown cases + self.total_unexecuted_count = 0 + # duration + self.duration = duration + + +class CmockaSingleCoreRecord: + def __init__(self, lines, core="", board="", log="", duration=0): + # create time + self.create_at = datetime.now().strftime("%Y-%m-%d %H:%M:%S") + # core + self.core = "" if core is None else core + # board + self.board = "" if board is None else board + # cmocka info + self.test_suites: Dict[str, SuiteInfo] = dict() + # summary + self.summary = CmockaSummary(duration) + # log path + self.log = "" if log is None else log + # bad_case + self.bad_case_tip = "" + + suite_pattern = r"\] (?P[a-zA-Z]*TestSuites)" + case_pattern = r"\]\s+(?PTestNuttx\w+)" + lines_iter = iter(lines) + + current_suite = None + while True: + try: + line = next(lines_iter) + if (suite_match := re.search(suite_pattern, line)) is not None: + current_suite = suite_match.group("test_suite_name") + + elif ( + current_suite is not None + and (case_match := re.search(case_pattern, line)) is not None + ): + current_case = case_match.group("test_case_name") + self.append(CaseInfo(current_suite, current_case, Unexecuted)) + + except StopIteration: + break + + def append(self, object: CaseInfo): + suite: SuiteInfo = self.test_suites.get(object.test_suite_name) + if suite is None: + suite = SuiteInfo(object.test_suite_name) + self.test_suites.update({object.test_suite_name: suite}) + suite.test_cases.update({object.test_case_name: object}) + + passed_count = 0 + failed_count = 0 + unexecuted_count = 0 + + test_case: CaseInfo + for test_case in suite.test_cases.values(): + if test_case.status == Passed: + passed_count += 1 + elif test_case.status == Failed: + failed_count += 1 + else: + unexecuted_count += 1 + suite.passed_count = passed_count + suite.failed_count = failed_count + suite.unexecuted_count = unexecuted_count + suite.run_count = passed_count + failed_count + suite.cases_count = passed_count + failed_count + unexecuted_count + if passed_count + failed_count != 0: + suite.is_suite_run = True + + total_passed_count = 0 + total_failed_count = 0 + total_unexecuted_count = 0 + total_cases_count = 0 + + suite: SuiteInfo + for suite in self.test_suites.values(): + total_passed_count += suite.passed_count + total_failed_count += suite.failed_count + total_unexecuted_count += suite.unexecuted_count + total_cases_count += suite.cases_count + + self.summary.total_passed_count = total_passed_count + self.summary.total_failed_count = total_failed_count + self.summary.total_unexecuted_count = total_unexecuted_count + self.summary.total_cases_count = total_cases_count + self.summary.total_suites_count = len(self.test_suites) + + def process(self, lines, err_code): + # regular expression + suite_start_pattern = r"\] (?P[a-zA-Z]*TestSuites): Running (?P\d+) test\(s\)" + case_run_pattern = r"\[\s+RUN\s+\] (?PTestNuttx\w+)" + case_pass_pattern = r"\[\s+OK\s+\] (?PTestNuttx\w+)" + case_fail_pattern = r"\[\s+FAILED\s+\] (?PTestNuttx\w+)" + + lines_iter = iter(lines) + line = next(lines_iter) + while True: + try: + interrupt_flag = False + # matching new test suites + if ( + suite_start_match := re.search(suite_start_pattern, line) + ) is not None: + test_suite_name = suite_start_match.group("test_suite_name") + cases_count = int(suite_start_match.group("cases_count")) + suite_end_pattern = r"{}: {} test(s) run.".format( + test_suite_name, cases_count + ) + + line = next(lines_iter) + while True: + if ( + case_run_match := re.search(case_run_pattern, line) + ) is not None: + test_case_name = case_run_match.group("test_case_name") + log = [line] + + while True: + try: + line = next(lines_iter) + log.append(line) + except StopIteration: + self.append( + CaseInfo( + test_suite_name, test_case_name, Failed, log + ) + ) + if err_code == -3: + self.bad_case_tip = f"This case was not executed, \ + because crash occurred after running '{test_case_name}'." + elif err_code == -4: + self.bad_case_tip = f"This case was not executed, \ + because no response for a long time after running '{test_case_name}'." + elif err_code == -1: + self.bad_case_tip = f"This case was not executed, \ + because the maximum waiting time has been exceeded \ + while running '{test_case_name}'." + else: + self.bad_case_tip = "This case was not executed due to unknown reasons." + raise StopIteration + + if re.search(case_pass_pattern, line) is not None: + self.append( + CaseInfo( + test_suite_name, test_case_name, Passed, log + ) + ) + break + + elif re.search(case_fail_pattern, line) is not None: + self.append( + CaseInfo( + test_suite_name, test_case_name, Failed, log + ) + ) + break + + elif re.search(suite_start_pattern, line) is not None: + self.append( + CaseInfo( + test_suite_name, test_case_name, Failed, log + ) + ) + interrupt_flag = True + break + + elif suite_end_pattern in line: + break + + if interrupt_flag: + break + + line = next(lines_iter) + + if interrupt_flag: + continue + line = next(lines_iter) + except StopIteration: + break diff --git a/tools/configure.sh b/tools/configure.sh index b5aba45ec621c..023cc1ebe4e3f 100755 --- a/tools/configure.sh +++ b/tools/configure.sh @@ -24,7 +24,7 @@ TOPDIR="${WD}/.." MAKECMD="make" USAGE=" -USAGE: ${0} [-E] [-e] [-l|m|c|g|n|B] [L] [-a ] [make-opts] +USAGE: ${0} [-E] [-e] [-l|m|c|g|n|B] [-L [boardname]] [-a ] [make-opts] Where: -E enforces distclean if already configured. @@ -37,7 +37,8 @@ Where: -B selects the *BSD (B) host environment. Default: Use host setup in the defconfig file Default Windows: Cygwin - -L Lists all available configurations. + -L lists available configurations for given boards, or all boards if no + board is given. board name can be partial here. -a is the path to the apps/ directory, relative to the nuttx directory is either: @@ -70,7 +71,13 @@ unset distclean function dumpcfgs { - configlist=`find ${TOPDIR}/boards -name defconfig` + if [ -n "$1" ]; then + local boards=$(find ${TOPDIR}/boards -mindepth 3 -maxdepth 3 -type d -name "*$1*") + [ -z "$boards" ] && { echo board "$1" not found; return ;} + configlist=$(find $boards -name defconfig -type f) + else + configlist=$(find ${TOPDIR}/boards -name defconfig -type f) + fi for defconfig in ${configlist}; do config=`dirname ${defconfig} | sed -e "s,${TOPDIR}/boards/,,g"` boardname=`echo ${config} | cut -d'/' -f3` @@ -109,7 +116,8 @@ while [ ! -z "$1" ]; do exit 0 ;; -L ) - dumpcfgs + shift + dumpcfgs $1 exit 0 ;; *) @@ -269,6 +277,10 @@ if [ -z "${appdir}" ]; then if [ -d "${TOPDIR}/../apps" ]; then appdir="../apps" + elif [ -d "${TOPDIR}/../nuttx-apps" ]; then + appdir="../nuttx-apps" + elif [ -d "${TOPDIR}/../nuttx-apps.git" ]; then + appdir="../nuttx-apps.git" else # Check for a versioned apps/ directory diff --git a/tools/cxd56/mkspk.c b/tools/cxd56/mkspk.c index f34d06dc2e075..6e20403049919 100644 --- a/tools/cxd56/mkspk.c +++ b/tools/cxd56/mkspk.c @@ -243,7 +243,7 @@ static void *create_image(struct elf_file *elf, int core, char *savename, psize = 0; for (i = 0, ph = elf->phdr; i < elf->ehdr->e_phnum; i++, ph++) { - if (ph->p_type != PT_LOAD || ph->p_filesz == 0) + if (ph->p_type != PT_LOAD || ph->p_memsz == 0) { continue; } @@ -297,7 +297,7 @@ static void *create_image(struct elf_file *elf, int core, char *savename, offset = ((char *)pi - img) + (nphs * sizeof(*pi)); for (i = 0; i < elf->ehdr->e_phnum; i++, ph++) { - if (ph->p_type != PT_LOAD || ph->p_filesz == 0) + if (ph->p_type != PT_LOAD || ph->p_memsz == 0) continue; pi->load_address = ph->p_paddr; pi->offset = offset; diff --git a/tools/esp32s3/Config.mk b/tools/esp32s3/Config.mk index 039f1e7c54cee..b44c081a0aca3 100644 --- a/tools/esp32s3/Config.mk +++ b/tools/esp32s3/Config.mk @@ -98,6 +98,13 @@ else ifeq ($(CONFIG_ESP32S3_APP_FORMAT_MCUBOOT),y) IMGTOOL_SIGN_ARGS := --pad $(VERIFIED) $(IMGTOOL_ALIGN_ARGS) -v 0 -s auto \ -H $(CONFIG_ESP32S3_APP_MCUBOOT_HEADER_SIZE) --pad-header \ -S $(CONFIG_ESP32S3_OTA_SLOT_SIZE) +else +# CONFIG_ESPRESSIF_SIMPLE_BOOT + + APP_OFFSET := 0x0000 + APP_IMAGE := nuttx.bin + FLASH_APP := $(APP_OFFSET) $(APP_IMAGE) + ESPTOOL_BINDIR := . endif ESPTOOL_BINS += $(FLASH_APP) @@ -157,6 +164,25 @@ define MKIMAGE $(Q) echo nuttx.bin >> nuttx.manifest $(Q) echo "Generated: nuttx.bin (MCUboot compatible)" endef +else +define MKIMAGE + $(Q) echo "MKIMAGE: ESP32-S3 binary" + $(Q) if ! esptool.py version 1>/dev/null 2>&1; then \ + echo ""; \ + echo "esptool.py not found. Please run: \"pip install esptool\""; \ + echo ""; \ + echo "Run make again to create the nuttx.bin image."; \ + exit 1; \ + fi + $(Q) if [ -z $(FLASH_SIZE) ]; then \ + echo "Missing Flash memory size configuration."; \ + exit 1; \ + fi + $(eval ELF2IMAGE_OPTS := $(if $(CONFIG_ESPRESSIF_SIMPLE_BOOT),--ram-only-header) -fs $(FLASH_SIZE) -fm $(FLASH_MODE) -ff $(FLASH_FREQ)) + esptool.py -c esp32s3 elf2image $(ELF2IMAGE_OPTS) -o nuttx.bin nuttx + $(Q) echo nuttx.bin >> nuttx.manifest + $(Q) echo "Generated: nuttx.bin" +endef endif # PREBUILD -- Perform pre build operations diff --git a/tools/espressif/Config.mk b/tools/espressif/Config.mk index d95b594b1b570..e2d9b4cb8d503 100644 --- a/tools/espressif/Config.mk +++ b/tools/espressif/Config.mk @@ -72,6 +72,8 @@ ifdef ESPTOOL_BINDIR BOOTLOADER := $(ESPTOOL_BINDIR)/mcuboot-$(CHIP_SERIES).bin FLASH_BL := $(BL_OFFSET) $(BOOTLOADER) ESPTOOL_BINS := $(FLASH_BL) + else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + else BL_OFFSET := 0x0 PT_OFFSET := $(CONFIG_ESPRESSIF_PARTITION_TABLE_OFFSET) @@ -98,6 +100,11 @@ ifeq ($(CONFIG_ESPRESSIF_BOOTLOADER_MCUBOOT),y) IMGTOOL_SIGN_ARGS := --pad $(VERIFIED) $(IMGTOOL_ALIGN_ARGS) -v 0 -s auto \ -H $(CONFIG_ESPRESSIF_APP_MCUBOOT_HEADER_SIZE) --pad-header \ -S $(CONFIG_ESPRESSIF_OTA_SLOT_SIZE) +else ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) + APP_OFFSET := 0x0000 + APP_IMAGE := nuttx.bin + FLASH_APP := $(APP_OFFSET) $(APP_IMAGE) + ESPTOOL_BINDIR := . else APP_OFFSET := 0x10000 APP_IMAGE := nuttx.bin @@ -157,7 +164,7 @@ define MKIMAGE echo "Missing Flash memory size configuration."; \ exit 1; \ fi - $(eval ELF2IMAGE_OPTS := -fs $(FLASH_SIZE) -fm $(FLASH_MODE) -ff $(FLASH_FREQ)) + $(eval ELF2IMAGE_OPTS := $(if $(CONFIG_ESPRESSIF_SIMPLE_BOOT),--ram-only-header) -fs $(FLASH_SIZE) -fm $(FLASH_MODE) -ff $(FLASH_FREQ)) esptool.py -c $(CHIP_SERIES) elf2image $(ELF2IMAGE_OPTS) -o nuttx.bin nuttx $(Q) echo nuttx.bin >> nuttx.manifest $(Q) echo "Generated: nuttx.bin" diff --git a/tools/gdb/memdump.py b/tools/gdb/memdump.py index a53e20831f788..5f0d1cc3f9f1e 100644 --- a/tools/gdb/memdump.py +++ b/tools/gdb/memdump.py @@ -18,6 +18,8 @@ # ############################################################################ +import argparse + import gdb import utils from lists import list_for_each_entry, sq_for_every, sq_queue @@ -35,6 +37,11 @@ PID_MM_MEMPOOL = -1 +def mm_nodesize(size) -> int: + """Return the real size of a memory node""" + return size & ~MM_MASK_BIT + + def mm_foreach(heap): """Iterate over a heap, yielding each node""" node = gdb.Value(heap["mm_heapstart"][0]).cast( @@ -43,7 +50,7 @@ def mm_foreach(heap): while 1: yield node next = gdb.Value(node).cast(gdb.lookup_type("char").pointer()) - next = gdb.Value(next + (node["size"] & ~MM_MASK_BIT)).cast( + next = gdb.Value(next + mm_nodesize(node["size"])).cast( gdb.lookup_type("struct mm_allocnode_s").pointer() ) if node >= heap["mm_heapend"].dereference() or next == node: @@ -66,7 +73,7 @@ class Nxmemdump(gdb.Command): def __init__(self): super(Nxmemdump, self).__init__("memdump", gdb.COMMAND_USER) - def mempool_dump(self, mpool, pid, seqmin, seqmax): + def mempool_dump(self, mpool, pid, seqmin, seqmax, address): """Dump the mempool memory""" for pool in mempool_multiple_foreach(mpool): if pid == PID_MM_FREE: @@ -95,7 +102,7 @@ def mempool_dump(self, mpool, pid, seqmin, seqmax): "%6d%12u%12u%#*x" % ( node["pid"], - pool["blocksize"] & ~MM_MASK_BIT, + mm_nodesize(pool["blocksize"]), node["seqno"], self.align, (int)(charnode - pool["blocksize"]), @@ -111,11 +118,23 @@ def mempool_dump(self, mpool, pid, seqmin, seqmax): ) ) + if address and ( + address < int(charnode) + and address >= (int)(charnode - pool["blocksize"]) + ): + gdb.write( + "\nThe address 0x%x found belongs to" + "the mempool node with base address 0x%x\n" + % (address, charnode) + ) + return True + gdb.write("\n") self.aordblks += 1 self.uordblks += pool["blocksize"] + return False - def memdump(self, pid, seqmin, seqmax): + def memdump(self, pid, seqmin, seqmax, address): """Dump the heap memory""" if pid >= PID_MM_ALLOC: gdb.write("Dump all used memory node info:\n") @@ -129,7 +148,8 @@ def memdump(self, pid, seqmin, seqmax): heap = gdb.parse_and_eval("g_mmheap") if heap.type.has_key("mm_mpool"): - self.mempool_dump(heap["mm_mpool"], pid, seqmin, seqmax) + if self.mempool_dump(heap["mm_mpool"], pid, seqmin, seqmax, address): + return for node in mm_foreach(heap): if node["size"] & MM_ALLOC_BIT != 0: @@ -142,7 +162,7 @@ def memdump(self, pid, seqmin, seqmax): "%6d%12u%12u%#*x" % ( node["pid"], - node["size"] & ~MM_MASK_BIT, + mm_nodesize(node["size"]), node["seqno"], self.align, (int)( @@ -164,15 +184,29 @@ def memdump(self, pid, seqmin, seqmax): gdb.write("\n") + if address and ( + address < int(charnode + node["size"]) + and address + >= (int)( + charnode + gdb.lookup_type("struct mm_allocnode_s").sizeof + ) + ): + gdb.write( + "\nThe address 0x%x found belongs to" + "the memory node with base address 0x%x\n" + % (address, charnode) + ) + return + self.aordblks += 1 - self.uordblks += node["size"] & ~MM_MASK_BIT + self.uordblks += mm_nodesize(node["size"]) else: if pid == PID_MM_FREE: charnode = gdb.Value(node).cast(gdb.lookup_type("char").pointer()) gdb.write( "%12u%#*x\n" % ( - node["size"] & ~MM_MASK_BIT, + mm_nodesize(node["size"]), self.align, (int)( charnode @@ -181,7 +215,7 @@ def memdump(self, pid, seqmin, seqmax): ) ) self.aordblks += 1 - self.uordblks += node["size"] & ~MM_MASK_BIT + self.uordblks += mm_nodesize(node["size"]) gdb.write("%12s%12s\n" % ("Total Blks", "Total Size")) gdb.write("%12d%12d\n" % (self.aordblks, self.uordblks)) @@ -189,36 +223,43 @@ def memdump(self, pid, seqmin, seqmax): def complete(self, text, word): return gdb.COMPLETE_SYMBOL + def parse_arguments(self, argv): + parser = argparse.ArgumentParser(description="memdump command") + parser.add_argument("-p", "--pid", type=str, help="Thread PID") + parser.add_argument("-a", "--addr", type=str, help="Query memory address") + parser.add_argument("-i", "--min", type=str, help="Minimum value") + parser.add_argument("-x", "--max", type=str, help="Maximum value") + parser.add_argument("--used", action="store_true", help="Used flag") + parser.add_argument("--free", action="store_true", help="Free flag") + args = parser.parse_args(args=(None if len(argv) == 1 else argv)) + return { + "pid": int(args.pid, 0) if args.pid else None, + "seqmin": int(args.min, 0) if args.min else 0, + "seqmax": int(args.max, 0) if args.max else 0xFFFFFFFF, + "used": args.used, + "free": args.free, + "addr": int(args.addr, 0) if args.addr else None, + } + def invoke(self, args, from_tty): if gdb.lookup_type("size_t").sizeof == 4: self.align = 11 else: self.align = 19 - arg = args.split(" ") + arg = self.parse_arguments(args.split(" ")) - if arg[0] == "": + pid = PID_MM_ALLOC + if arg["used"]: pid = PID_MM_ALLOC - elif arg[0] == "used": - pid = PID_MM_ALLOC - elif arg[0] == "free": + elif arg["free"]: pid = PID_MM_LEAK - else: - pid = int(arg[0]) - - if len(arg) == 2: - seqmin = int(arg[1]) - else: - seqmin = 0 - - if len(arg) == 3: - seqmax = int(arg[2]) - else: - seqmax = 0xFFFFFFFF + elif arg["pid"]: + pid = arg["pid"] self.aordblks = 0 self.uordblks = 0 - self.memdump(pid, seqmin, seqmax) + self.memdump(pid, arg["seqmin"], arg["seqmax"], arg["addr"]) Nxmemdump() diff --git a/tools/imx9/Config.mk b/tools/imx9/Config.mk new file mode 100644 index 0000000000000..af7f0ee010009 --- /dev/null +++ b/tools/imx9/Config.mk @@ -0,0 +1,33 @@ +############################################################################ +# tools/imx9/Config.mk +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# These are the macros that will be used in the NuttX make system to compile +# and assembly source files and to insert the resulting object files into an +# archive. These replace the default definitions at tools/Config.mk + +# POSTBUILD -- Perform post build operations + +ifeq ($(CONFIG_IMX9_BOOTLOADER),y) +define POSTBUILD + $(Q) echo "Removing sections" + $(Q) $(OBJCOPY) -O binary -R .bss -R .initstack $(BIN) nuttx.bin + $(Q) ([ $$? -eq 0 ] && echo "Done.") +endef +endif diff --git a/tools/incdir.c b/tools/incdir.c index 67c6035e7e50a..8d9e338329cf4 100644 --- a/tools/incdir.c +++ b/tools/incdir.c @@ -67,7 +67,8 @@ enum compiler_e COMPILER_CLANG, COMPILER_MINGW, COMPILER_SDCC, - COMPILER_ZDSII + COMPILER_ZDSII, + COMPILER_TASKING }; /**************************************************************************** @@ -200,6 +201,10 @@ static enum compiler_e get_compiler(char *ccname) { return COMPILER_ZDSII; } + else if (strstr(ccname, "ctc") != NULL) + { + return COMPILER_TASKING; + } else { /* Unknown compiler. Assume GCC-compatible */ @@ -347,7 +352,7 @@ int main(int argc, char **argv, char **envp) wintool = true; #endif } - else if (compiler == COMPILER_SDCC) + else if (compiler == COMPILER_SDCC || compiler == COMPILER_TASKING) { cmdarg = "-I"; } diff --git a/tools/kasan_global.py b/tools/kasan_global.py new file mode 100755 index 0000000000000..3967079dffc26 --- /dev/null +++ b/tools/kasan_global.py @@ -0,0 +1,306 @@ +#!/usr/bin/env python3 +############################################################################ +# tools/kasan_global.py +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +import argparse +import os + +from construct import Int32ul, Int64ul, Struct +from elftools.elf.elffile import ELFFile + +debug = False + +# N-byte aligned shadow area 1 bit +KASAN_GLOBAL_ALIGN = 32 + +# The maximum gap that two data segments can tolerate +KASAN_MAX_DATA_GAP = 1 << 16 + +# The section where the global variable descriptor +# generated by the compiler is located +KASAN_SECTION = ".kasan.global" + +# The structure of parsing strings required for 32-bit and 64 bit +KASAN_GLOBAL_STRUCT_32 = Struct( + "beg" / Int32ul, + "size" / Int32ul, + "size_with_redzone" / Int32ul, + "name" / Int32ul, + "module_name" / Int32ul, + "has_dynamic_init" / Int32ul, + "location" / Int32ul, + "odr_indicator" / Int32ul, +) + +KASAN_GLOBAL_STRUCT_64 = Struct( + "beg" / Int64ul, + "size" / Int64ul, + "size_with_redzone" / Int64ul, + "name" / Int64ul, + "module_name" / Int64ul, + "has_dynamic_init" / Int64ul, + "location" / Int64ul, + "odr_indicator" / Int64ul, +) + + +# Global configuration information +class Config: + def __init__(self, outpath, elf, ldscript): + self.outpath = outpath + self.elf = elf + self.ldscript = ldscript + + if self.elf is None or os.path.exists(self.elf) is False: + self.elf = None + return + + with open(self.elf, "rb") as file: + elf_file = ELFFile(file) + elf_header = elf_file.header + + # Obtain bit width + bitness = elf_header["e_ident"]["EI_CLASS"] + if bitness == "ELFCLASS32": + self.bitwides = 32 + elif bitness == "ELFCLASS64": + self.bitwides = 64 + + # Big and little end + endianness = elf_header["e_ident"]["EI_DATA"] + if endianness == "ELFDATA2LSB": + self.endian = "little" + elif endianness == "ELFDATA2MSB": + self.endian = "big" + + +class KASanRegion: + def __init__(self, start, end) -> None: + self.start = start + self.end = end + self.size = int((end - start) // KASAN_GLOBAL_ALIGN // 8) + 1 + self.shadow = bytearray(b"\x00" * self.size) + + def mark_bit(self, index, nbits): + self.shadow[index] |= 1 << nbits + + def poison(self, dict): + dict_size = dict["size"] + if dict_size % 32: + dict_size = int((dict_size + 31) // 32) * 32 + + distance = (dict["beg"] + dict_size - self.start) // KASAN_GLOBAL_ALIGN + index = int(distance // 8) + nbits = distance % 8 + if debug: + print( + "regin: %08x addr: %08x size: %d bits: %d || poison index: %d nbits: %d" + % ( + self.start, + dict["beg"], + dict["size"], + int(dict["size_with_redzone"] // KASAN_GLOBAL_ALIGN), + index, + nbits, + ) + ) + + # Using 32bytes: with 1bit alignment, + # only one bit of inaccessible area exists for each pair of global variables. + self.mark_bit(index, nbits) + + +class KASanInfo: + def __init__(self) -> None: + # Record the starting position of the merged data block + self.data_sections = [] + # Record the kasan region corresponding to each data block + self.regions: list[KASanRegion] = [] + + def merge_ranges(self, dict): + if len(self.data_sections) == 0: + self.data_sections.append( + [dict["beg"], dict["beg"] + dict["size_with_redzone"]] + ) + return + start = dict["beg"] + end = dict["beg"] + dict["size_with_redzone"] + if start - self.data_sections[-1][1] <= KASAN_MAX_DATA_GAP: + self.data_sections[-1][1] = end + else: + self.data_sections.append([start, end]) + + def create_region(self): + for i in self.data_sections: + start = i[0] + end = i[1] + if debug: + print("KAsan Shadow Block: %08x ---- %08x" % (start, end)) + self.regions.append(KASanRegion(start, end)) + + def mark_shadow(self, dict): + for i in self.regions: + start = i.start + end = i.end + if start <= dict["beg"] and dict["beg"] <= end: + i.poison(dict) + break + + +# Global variable descriptor +def get_global_dict(GLOBAL_STRUCT: Struct, bytes: bytes): + dict = GLOBAL_STRUCT.parse(bytes) + return { + "beg": dict.beg, + "size": dict.size, + "size_with_redzone": dict.size_with_redzone, + } + + +def get_elf_section(elf, section) -> bytes: + with open(elf, "rb") as file: + elf = ELFFile(file) + for i in elf.iter_sections(): + if i.name == section: + return i.data() + return None + + +def long_to_bytestring(bitwides, endian, value: int) -> str: + res = "" + byte_array = value.to_bytes(length=int(bitwides / 8), byteorder=endian) + for i in byte_array: + res += "0x%02x, " % (i) + return res + + +def create_kasan_file(config: Config, region_list=[]): + region: KASanRegion = None + with open(config.outpath, "w") as file: + file.write("const unsigned char\ng_globals_region[] = {\n") + for i in range(len(region_list)): + region = region_list[i] + + # Fill the array of regions + # The filling order is as follows, from mm/kasan/generic.c + # The data set to 0 is assigned by the program body + # 1. FAR struct kasan_region_s *next; + # This type will be used to record the size of the shadow area + # to facilitate the program to traverse the array. + # 2. uintptr_t begin; + # 3. uintptr_t end; + # 4. uintptr_t shadow[1]; + + file.write( + "%s\n" + % (long_to_bytestring(config.bitwides, config.endian, region.size)) + ) + file.write( + "%s\n" + % (long_to_bytestring(config.bitwides, config.endian, region.start)) + ) + file.write( + "%s\n" + % (long_to_bytestring(config.bitwides, config.endian, region.end)) + ) + + for j in range(len(region.shadow)): + if j % 8 == 0: + file.write("\n") + file.write("0x%02x, " % (region.shadow[j])) + + file.write("\n") + file.write("0x00, 0x00, 0x00, 0x00,0x00, 0x00,0x00, 0x00\n") + file.write("\n};") + + +# Error extraction section processing to enable the program to compile successfully +def handle_error(config: Config, string=None): + if string: + print(string) + create_kasan_file(config) + exit(0) + + +def parse_args() -> Config: + global debug + parser = argparse.ArgumentParser(description="Build kasan global variable region") + parser.add_argument("-o", "--outpath", help="outpath") + parser.add_argument("-d", "--ldscript", help="ld script path(Only support sim)") + parser.add_argument("-e", "--elffile", help="elffile") + parser.add_argument( + "--debug", + action="store_true", + default=False, + help="if enabled, it will show more logs.", + ) + + args = parser.parse_args() + debug = args.debug + return Config(args.outpath, args.elffile, args.ldscript) + + +def main(): + config = parse_args() + if config.elf is None: + handle_error(config) + + # Identify the segment information that needs to be extracted + section = get_elf_section(config.elf, KASAN_SECTION) + if section is None: + handle_error( + config, + "Please update the link script, section ['%s'] cannot be found" + % (KASAN_SECTION), + ) + + # List of global variable descriptors + dict_list = [] + + # Extract all global variable descriptors within the + if config.bitwides == 32: + global_struct = KASAN_GLOBAL_STRUCT_32 + elif config.bitwides == 64: + global_struct = KASAN_GLOBAL_STRUCT_64 + + step = global_struct.sizeof() + for i in range(0, len(section), step): + dict = get_global_dict(global_struct, section[i : i + step]) + dict_list.append(dict) + + dict_list = sorted(dict_list, key=lambda item: item["beg"]) + + # Merge all global variables to obtain several segments of the distribution range + kasan = KASanInfo() + for i in dict_list: + kasan.merge_ranges(i) + + # Create empty shadow zone + kasan.create_region() + + # Mark on the shadow area + for i in dict_list: + kasan.mark_shadow(i) + + create_kasan_file(config, kasan.regions) + + +if __name__ == "__main__": + main() diff --git a/tools/link.sh b/tools/link.sh index 2027b3ac1e6b5..70b2e0919329d 100755 --- a/tools/link.sh +++ b/tools/link.sh @@ -82,7 +82,7 @@ ln -s "${src}" "${dest}" || \ # Verify that the link was created -if [ -e ${dest} ] && [ -h ${desg} ]; then +if [ -e ${dest} ] && [ -h ${dest} ]; then # The file exists and is a symlink (i.e. the symlink isn't broken) exit 0 diff --git a/tools/minidumpserver.py b/tools/minidumpserver.py index 0c1441a312c7c..469e8a36c8af8 100755 --- a/tools/minidumpserver.py +++ b/tools/minidumpserver.py @@ -43,9 +43,16 @@ DEFAULT_GDB_INIT_CMD = "-ex 'bt full' -ex 'info reg' -ex 'display /40i $pc-40'" - logger = logging.getLogger() +# The global register table is dictionary like {arch:{reg:ndx}} +# +# where arch is the CPU architecture name; +# reg is the name of the register as used in log file +# ndx is the index of the register in GDB group registers list +# +# Registers with multiple convenient names can have multiple entries here, one +# for each name and with the same index. reg_table = { "arm": { "R0": 0, @@ -104,6 +111,7 @@ "PC": 15, "CPSR": 41, }, + # rv64 works with gdb-multiarch on Ubuntu "riscv": { "ZERO": 0, "RA": 1, @@ -138,6 +146,8 @@ "T5": 30, "T6": 31, "PC": 32, + "S0": 8, + "EPC": 32, }, # use xtensa-esp32s3-elf-gdb register table "esp32s3": { @@ -213,6 +223,9 @@ "WINDOWSTART": 1, "PS": 0x40000, }, + "riscv": { + "ZERO": 0, + }, } @@ -238,10 +251,15 @@ class DumpELFFile: def __init__(self, elffile: str): self.elffile = elffile self.__memories = [] + self.__arch = None + self.__xlen = None + self.__text = 0 def parse(self): self.__memories = [] elf = ELFFile.load_from_path(self.elffile) + self.__arch = elf.get_machine_arch().lower().replace("-", "") + self.__xlen = elf.elfclass for section in elf.iter_sections(): # REALLY NEED to match exact type as all other sections @@ -284,12 +302,32 @@ def parse(self): self.__memories.append(memory) + # record first text segment address + for segment in elf.iter_segments(): + if segment.header.p_flags & 1 and not self.__text: + self.__text = segment.header.p_vaddr + elf.close() return True + def merge(self, other): + if other.arch() == self.arch() and other.xlen() == self.xlen(): + self.__memories += other.get_memories() + else: + raise TypeError("inconsistent ELF types") + def get_memories(self): return self.__memories + def arch(self): + return self.__arch + + def xlen(self): + return self.__xlen + + def text(self): + return self.__text + class DumpLogFile: def __init__(self, logfile): @@ -299,6 +337,7 @@ def __init__(self, logfile): self.reg_table = dict() def _init_register(self): + # registers list should be able to hold the max index self.registers = [b"x"] * (max(self.reg_table.values()) + 1) def _parse_register(self, line): @@ -314,6 +353,9 @@ def _parse_register(self, line): if reg_name in self.reg_table: reg_index = self.reg_table[reg_name] self.registers[reg_index] = int(reg_val, 16) + else: + raise Exception("Unknown register name: ", reg_name) + return True def _parse_fix_register(self, arch): @@ -345,7 +387,7 @@ def _parse_stack(self, line, start, data): start = addr_start for val in match_res.groupdict()["VALS"].split(): - data = data + struct.pack(" unknown value # Send in "xxxxxxxx" - pkt += b"x" * 8 + pkt += b"x" * self.reg_digits self.put_gdb_packet(pkt) def handle_register_single_read_packet(self, pkt): - reg_fmt = " [output file]") + print( + "Usage: mkallsyms.py [noconst] [output file] [order symbols by name]" + ) os._exit(errno.ENOENT) -def parse_args(argv): - index = 1 - argc = len(argv) - outfile = None - elffile = None - - if argc > index and argv[index] == "--version": - print("mkallsyms.py: based on pyelftools %s" % __version__) - os.exit(0) - - if argc > index and argv[index] == "noconst": - noconst = True - index += 1 - else: - noconst = False - - if argc > index: - elffile = argv[index] - index += 1 - - if argc > index: - outfile = open(argv[index], "w") - else: - outfile = sys.stdout - - return noconst, elffile, outfile - - if __name__ == "__main__": - noconst, elffile, outfile = parse_args(sys.argv) - readelf = SymbolTables(elffile, outfile) - readelf.parse_symbol() - readelf.print_symbol_tables(noconst) + parser = argparse.ArgumentParser( + description="Process ELF binary to extract symbols." + ) + parser.add_argument("elffile", help="Path to the ELF binary file.") + parser.add_argument( + "outfile", + nargs="?", + type=argparse.FileType("w"), + default=sys.stdout, + help="Output file to write symbols to (default: stdout).", + ) + parser.add_argument("--noconst", action="store_true", help="Exclude const symbols.") + parser.add_argument( + "--version", + action="version", + version="mkallsyms.py: based on pyelftools %s" % __version__, + ) + parser.add_argument( + "--orderbyname", + nargs="?", + const=False, + default=False, + help='Order symbols by name (specify "y" to enable, default: False).', + ) + args = parser.parse_args() + + readelf = SymbolTables(args.elffile, args.outfile) + readelf.parse_symbol(args.orderbyname) + readelf.print_symbol_tables(args.noconst) diff --git a/tools/mkdeps.c b/tools/mkdeps.c index da9a3f5b8874a..a38d245e2e006 100644 --- a/tools/mkdeps.c +++ b/tools/mkdeps.c @@ -81,12 +81,12 @@ * Private Types ****************************************************************************/ -enum slashmode_e +typedef enum { - MODE_FSLASH = 0, - MODE_BSLASH = 1, - MODE_DBLBACK = 2 -}; + COMPILER_GNU = 0, + COMPILER_TASKING = 1, + COMPILER_NUM = 2 +} compiler_t; /**************************************************************************** * Private Data @@ -115,10 +115,37 @@ static char g_posixpath[MAX_PATH]; static char g_shquote[MAX_SHQUOTE]; #endif +static const char * const g_moptions[COMPILER_NUM][2] = +{ + /* GNU C/C++ Compiler */ + + { + " -M ", + " -MT " + }, + + /* Tasking C/C++ Compiler */ + + { + " -Em ", + " --pass-c=--make-target=" + } +}; + /**************************************************************************** * Private Functions ****************************************************************************/ +static compiler_t get_compiler(char *ccname) +{ + if (strstr(ccname, "ctc") != NULL) + { + return COMPILER_TASKING; + } + + return COMPILER_GNU; +} + /* MinGW does not seem to provide strtok_r */ #ifndef HAVE_STRTOK_R @@ -684,7 +711,7 @@ static const char *convert_path(const char *path) static void do_dependency(const char *file) { - static const char moption[] = " -M "; + const char * const * moption; struct stat buf; char *alloc; char *altpath; @@ -705,6 +732,8 @@ static void do_dependency(const char *file) separator = g_winnative ? '\\' : '/'; #endif + moption = g_moptions[get_compiler(g_cc)]; + /* Copy the compiler into the command buffer */ cmdlen = strlen(g_cc); @@ -741,15 +770,15 @@ static void do_dependency(const char *file) *dotptr = '\0'; } - snprintf(tmp, NAME_MAX + 6, " -MT %s%c%s%s ", - g_objpath, separator, objname, g_suffix); + snprintf(tmp, NAME_MAX + 6, "%s%s%c%s%s ", + moption[1], g_objpath, separator, objname, g_suffix); expanded = do_expand(tmp); cmdlen += strlen(expanded); if (cmdlen >= MAX_BUFFER) { fprintf(stderr, "ERROR: Option string is too long [%d/%d]: %s\n", - cmdlen, MAX_BUFFER, moption); + cmdlen, MAX_BUFFER, moption[0]); exit(EXIT_FAILURE); } @@ -759,15 +788,15 @@ static void do_dependency(const char *file) /* Copy " -M " */ - cmdlen += strlen(moption); + cmdlen += strlen(moption[0]); if (cmdlen >= MAX_BUFFER) { fprintf(stderr, "ERROR: Option string is too long [%d/%d]: %s\n", - cmdlen, MAX_BUFFER, moption); + cmdlen, MAX_BUFFER, moption[0]); exit(EXIT_FAILURE); } - strcat(g_command, moption); + strcat(g_command, moption[0]); /* Copy the CFLAGS into the command buffer */ diff --git a/tools/mkexport.sh b/tools/mkexport.sh index 14d3e39e49591..01fe771ef4dec 100755 --- a/tools/mkexport.sh +++ b/tools/mkexport.sh @@ -182,10 +182,15 @@ cp "${TOPDIR}/tools/incdir.c" "${EXPORTDIR}/tools/." # Copy the board specific linker if found, or use the default when not. -if [ -f "${BOARDDIR}/scripts/gnu-elf.ld" ]; then - cp -f "${BOARDDIR}/scripts/gnu-elf.ld" "${EXPORTDIR}/scripts/." +APPLD=gnu-elf.ld +if [ -f "${BOARDDIR}/scripts/${APPLD}" ]; then + cp -f "${BOARDDIR}/scripts/${APPLD}" "${EXPORTDIR}/scripts/." else - cp -f "${TOPDIR}/binfmt/libelf/gnu-elf.ld" "${EXPORTDIR}/scripts/." + cp -f "${TOPDIR}/binfmt/libelf/${APPLD}" "${EXPORTDIR}/scripts/." +fi + +if [ "${NUTTX_BUILD}" = "kernel" ]; then + LDNAME=${APPLD} fi # Copy the board config script @@ -243,6 +248,8 @@ echo "NM = ${NM}" >>"${EXPORTDIR}/scripts/Make.defs" echo "STRIP = ${STRIP}" >>"${EXPORTDIR}/scripts/Make.defs" echo "OBJCOPY = ${OBJCOPY}" >>"${EXPORTDIR}/scripts/Make.defs" echo "OBJDUMP = ${OBJDUMP}" >>"${EXPORTDIR}/scripts/Make.defs" +echo "ZIG = ${ZIG}" >>"${EXPORTDIR}/scripts/Make.defs" +echo "ZIGFLAGS = ${ZIGFLAGS}" >>"${EXPORTDIR}/scripts/Make.defs" echo "NXFLATLDFLAGS1 = ${NXFLATLDFLAGS1}" >>"${EXPORTDIR}/scripts/Make.defs" echo "NXFLATLDFLAGS2 = ${NXFLATLDFLAGS2}" >>"${EXPORTDIR}/scripts/Make.defs" echo "OBJEXT = ${OBJEXT}" >>"${EXPORTDIR}/scripts/Make.defs" @@ -255,6 +262,11 @@ echo "HOSTLDFLAGS = ${HOSTLDFLAGS}" >>"${EXPORTDIR}/scripts/Make.defs" echo "HOSTEXEEXT = ${HOSTEXEEXT}" >>"${EXPORTDIR}/scripts/Make.defs" echo "LDNAME = ${LDNAME}" >>"${EXPORTDIR}/scripts/Make.defs" echo "LDELFFLAGS = ${LDELFFLAGS}" >>"${EXPORTDIR}/scripts/Make.defs" +echo "NUTTX_ARCH = ${NUTTX_ARCH}" >>"${EXPORTDIR}/scripts/Make.defs" +echo "NUTTX_ARCH_CHIP = ${NUTTX_ARCH_CHIP}" >>"${EXPORTDIR}/scripts/Make.defs" +echo "NUTTX_BOARD = ${NUTTX_BOARD}" >>"${EXPORTDIR}/scripts/Make.defs" +echo "NUTTX_BUILD = ${NUTTX_BUILD}" >>"${EXPORTDIR}/scripts/Make.defs" +echo "NUTTX_CXX = ${NUTTX_CXX}" >>"${EXPORTDIR}/scripts/Make.defs" echo "set(ARCHCFLAGS \"${ARCHCFLAGS}\")" > "${EXPORTDIR}/scripts/target.cmake" echo "set(ARCHCPUFLAGS \"${ARCHCPUFLAGS}\")" >>"${EXPORTDIR}/scripts/target.cmake" @@ -281,6 +293,11 @@ echo "set(HOSTLDFLAGS \"${HOSTLDFLAGS}\")" >>"${EXPORTDIR}/scripts/ echo "set(HOSTEXEEXT \"${HOSTEXEEXT}\")" >>"${EXPORTDIR}/scripts/target.cmake" echo "set(LDNAME \"${LDNAME}\")" >>"${EXPORTDIR}/scripts/target.cmake" echo "set(LDELFFLAGS \"${LDELFFLAGS}\")" >>"${EXPORTDIR}/scripts/target.cmake" +echo "set(NUTTX_ARCH \"${NUTTX_ARCH}\")" >>"${EXPORTDIR}/scripts/target.cmake" +echo "set(NUTTX_ARCH_CHIP \"${NUTTX_ARCH_CHIP}\")" >>"${EXPORTDIR}/scripts/target.cmake" +echo "set(NUTTX_BOARD \"${NUTTX_BOARD}\")" >>"${EXPORTDIR}/scripts/target.cmake" +echo "set(NUTTX_BUILD \"${NUTTX_BUILD}\")" >>"${EXPORTDIR}/scripts/target.cmake" +echo "set(NUTTX_CXX \"${NUTTX_CXX}\")" >>"${EXPORTDIR}/scripts/target.cmake" # Additional compilation options when the kernel is built diff --git a/tools/mkromfsimg.sh b/tools/mkromfsimg.sh index cbf2d0e3e1af8..285d79b312cea 100755 --- a/tools/mkromfsimg.sh +++ b/tools/mkromfsimg.sh @@ -28,7 +28,7 @@ rcsysinittemplate=$rcsysinitfile.template rcsfile=rcS rcstemplate=$rcsfile.template romfsimg=romfs.img -headerfile=nsh_romfsimg.h +headerfile=etc_romfs.c # Get the input parameters @@ -79,25 +79,25 @@ if [ ! -r $topdir/.config ]; then exit 1 fi -romfsetc=`grep CONFIG_NSH_ROMFSETC= $topdir/.config | cut -d'=' -f2` +romfsetc=`grep CONFIG_ETC_ROMFS= $topdir/.config | cut -d'=' -f2` disablempt=`grep CONFIG_DISABLE_MOUNTPOINT= $topdir/.config | cut -d'=' -f2` disablescript=`grep CONFIG_NSH_DISABLESCRIPT= $topdir/.config | cut -d'=' -f2` devconsole=`grep CONFIG_DEV_CONSOLE= $topdir/.config | cut -d'=' -f2` romfs=`grep CONFIG_FS_ROMFS= $topdir/.config | cut -d'=' -f2` -romfsmpt=`grep CONFIG_NSH_ROMFSMOUNTPT= $topdir/.config | cut -d'=' -f2` +romfsmpt=`grep CONFIG_ETC_ROMFSMOUNTPT= $topdir/.config | cut -d'=' -f2` initscript=`grep CONFIG_NSH_INITSCRIPT= $topdir/.config | cut -d'=' -f2` sysinitscript=`grep CONFIG_NSH_SYSINITSCRIPT= $topdir/.config | cut -d'=' -f2` -romfsdevno=`grep CONFIG_NSH_ROMFSDEVNO= $topdir/.config | cut -d'=' -f2` -romfssectsize=`grep CONFIG_NSH_ROMFSSECTSIZE= $topdir/.config | cut -d'=' -f2` +romfsdevno=`grep CONFIG_ETC_ROMFSDEVNO= $topdir/.config | cut -d'=' -f2` +romfssectsize=`grep CONFIG_ETC_ROMFSSECTSIZE= $topdir/.config | cut -d'=' -f2` # If we disabled FAT FS requirement, we don't need to check it if [ "$usefat" = true ]; then fatfs=`grep CONFIG_FS_FAT= $topdir/.config | cut -d'=' -f2` - fatdevno=`grep CONFIG_NSH_FATDEVNO= $topdir/.config | cut -d'=' -f2` - fatsectsize=`grep CONFIG_NSH_FATSECTSIZE= $topdir/.config | cut -d'=' -f2` - fatnsectors=`grep CONFIG_NSH_FATNSECTORS= $topdir/.config | cut -d'=' -f2` - fatmpt=`grep CONFIG_NSH_FATMOUNTPT= $topdir/.config | cut -d'=' -f2` + fatdevno=`grep CONFIG_ETC_FATDEVNO= $topdir/.config | cut -d'=' -f2` + fatsectsize=`grep CONFIG_ETC_FATSECTSIZE= $topdir/.config | cut -d'=' -f2` + fatnsectors=`grep CONFIG_ETC_FATNSECTORS= $topdir/.config | cut -d'=' -f2` + fatmpt=`grep CONFIG_ETC_FATMOUNTPT= $topdir/.config | cut -d'=' -f2` fi # The following settings are required for general ROMFS support @@ -184,7 +184,7 @@ fi # /., /./*, /.., or /../* if [ ${romfsmpt:0:1} != "\"" ]; then - echo "CONFIG_NSH_ROMFSMOUNTPT must be a string" + echo "CONFIG_ETC_ROMFSMOUNTPT must be a string" echo "Change it so that it is enclosed in quotes." exit 1 fi @@ -192,7 +192,7 @@ fi uromfsmpt=`echo $romfsmpt | sed -e "s/\"//g"` if [ ${uromfsmpt:0:1} != "/" ]; then - echo "CONFIG_NSH_ROMFSMOUNTPT must be an absolute path in the target FS" + echo "CONFIG_ETC_ROMFSMOUNTPT must be an absolute path in the target FS" echo "Change it so that it begins with the character '/'. Eg. /etc" exit 1 fi @@ -204,7 +204,7 @@ done if [ -z "$tmpdir" -o "X$tmpdir" = "Xdev" -o "X$tmpdir" = "." -o \ ${tmpdir:0:2} = "./" -o "X$tmpdir" = ".." -o ${tmpdir:0:3} = "../" ]; then - echo "Invalid CONFIG_NSH_ROMFSMOUNTPT selection." + echo "Invalid CONFIG_ETC_ROMFSMOUNTPT selection." exit 1 fi diff --git a/tools/nxstyle.c b/tools/nxstyle.c index bce1c6325544a..8dab2a29afe9a 100644 --- a/tools/nxstyle.c +++ b/tools/nxstyle.c @@ -206,7 +206,8 @@ static const char *g_white_prefix[] = "ub32", /* Ref: include/fixedmath.h */ "lua_", /* Ref: apps/interpreters/lua/lua-5.x.x/src/lua.h */ "luaL_", /* Ref: apps/interpreters/lua/lua-5.x.x/src/lauxlib.h */ - + "V4L2_", /* Ref: include/sys/video_controls.h */ + "Ifx", /* Ref: arch/tricore/src */ NULL }; @@ -450,6 +451,35 @@ static const char *g_white_content_list[] = "CurrentTime", "XUnmapWindow", + /* Ref: + * nuttx/arch/sim/src/sim_hostdecoder.* + */ + + "ISVCDecoder", + "SBufferInfo", + "SDecodingParam", + "eEcActiveIdc", + "sVideoProperty", + "eVideoBsType", + "cmResultSuccess", + "uiInBsTimeStamp", + "dsErrorFree", + "iBufferStatus", + "UsrData", + "sSystemBuffer", + "iWidth", + "iHeight", + "iStride", + "uiOutYuvTimeStamp", + "WelsCreateDecoder", + "WelsDestroyDecoder", + "Initialize", + "Uninitialize", + "DecodeFrame2", + "FlushFrame", + "SetOption", + "GetOption", + /* Ref: * sim/posix/sim_deviceimage.c */ @@ -569,6 +599,12 @@ static const char *g_white_content_list[] = static const char *g_white_headers[] = { "windows.h", + + /* Ref: + * arch/tricore/src/common/tricore_serial.c + */ + + "IfxAsclin_Asc.h", NULL }; @@ -1860,6 +1896,7 @@ int main(int argc, char **argv, char **envp) if (pnest == 0) { int tmppnest; + bool tmpbstring; /* Note, we have not yet parsed each character on the line so * a comma have have been be preceded by '(' on the same line. @@ -1867,11 +1904,11 @@ int main(int argc, char **argv, char **envp) * case. */ - for (i = indent, tmppnest = 0; + for (i = indent, tmppnest = 0, tmpbstring = false; line[i] != '\n' && line[i] != '\0'; i++) { - if (tmppnest == 0 && line[i] == ',') + if (tmppnest == 0 && !tmpbstring && line[i] == ',') { ERROR("Multiple data definitions", lineno, i + 1); break; @@ -1891,6 +1928,10 @@ int main(int argc, char **argv, char **envp) tmppnest--; } + else if (line[i] == '"') + { + tmpbstring = !tmpbstring; + } else if (line[i] == ';') { /* Break out if the semicolon terminates the @@ -3081,7 +3122,16 @@ int main(int argc, char **argv, char **envp) if (m > g_maxline && !rhcomment) { - ERROR("Long line found", lineno, m); + /* Ignore the line 2 (file path) */ + + if (lineno == 2) + { + INFO("Skipping checking line 2: path file\n", 2, m); + } + else + { + ERROR("Long line found", lineno, m); + } } } diff --git a/tools/simwifi/sim_wifi.sh b/tools/simwifi/sim_wifi.sh index 5b7c785ece027..6162d75a055fe 100755 --- a/tools/simwifi/sim_wifi.sh +++ b/tools/simwifi/sim_wifi.sh @@ -23,6 +23,7 @@ NUTTX_BR_IF="nuttx0" RUN_DIR="/var/run/simwifi" +LINK_DIR="/usr/bin" CUR_DIR="" DBG_LEVEL=1 @@ -509,6 +510,8 @@ init() init_env + ln -s $CUR_DIR/sim_wifi.sh $LINK_DIR/sim_wifi.sh + echo "defwan:$1" > $DEFCONF_FILE [ -n "$1" -a -n "$(ifconfig | grep $1)" ] && start_bridge $1 @@ -520,11 +523,21 @@ init() clean() { + [ -z "$1" ] && { + echo "Missing the default wan interface." + exit -1 + } + recovery_to_init + rm $LINK_DIR/sim_wifi.sh + cur_mode=$(get_var mode $DEFCONF_FILE) [ "$cur_mode" = "hwsim" ] && modprobe -r mac80211_hwsim + echo "defwan:$1" > $DEFCONF_FILE + [ -n "$1" -a -n "$(ifconfig | grep $1)" ] && stop_bridge $1 + rm -fr $RUN_DIR rm -f $UDHCPC_SCRIPT } @@ -532,7 +545,7 @@ clean() usage() { echo "$(basename $SOURCE) (rename |" - echo -e "\t init |clean |" + echo -e "\t init |clean |" echo -e "\t start_wpa |stop_wpa |" echo -e "\t start_hostapd |stop_hostapd |" echo -e "\t start_udhcpc |stop_udhcpc |" @@ -552,7 +565,7 @@ get_script_path $0 case $1 in init) init $2 $3;; - clean) clean;; + clean) clean $2;; start_bridge) start_bridge $2;; stop_bridge) stop_bridge $2;; start_hwsim) start_hwsim $2 $3;; diff --git a/tools/toolchain.cmake.export b/tools/toolchain.cmake.export index b943f217c0653..1e9bc7ca5a493 100644 --- a/tools/toolchain.cmake.export +++ b/tools/toolchain.cmake.export @@ -1,5 +1,6 @@ set(CMAKE_SYSTEM_NAME Generic) set(CMAKE_SYSTEM_VERSION 1) +set(NUTTX 1) set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY) @@ -8,25 +9,31 @@ include(${NUTTX_PATH}/scripts/target.cmake) set(LINKER_SCRIPT ${NUTTX_PATH}/scripts/${LDNAME}) -set(CMAKE_C_FLAGS "${ARCHCPUFLAGS} ${ARCHCFLAGS} -D__NuttX__") +set(CMAKE_C_FLAGS "${ARCHCPUFLAGS} ${ARCHCFLAGS} -D__NuttX__") set(CMAKE_CXX_FLAGS "${ARCHCPUFLAGS} ${ARCHCXXFLAGS} -D__NuttX__") set(CMAKE_C_STANDARD_INCLUDE_DIRECTORIES ${NUTTX_PATH}/include ${NUTTX_PATH}/arch/chip) set(CMAKE_CXX_STANDARD_INCLUDE_DIRECTORIES - ${NUTTX_PATH}/include/libcxx ${NUTTX_PATH}/include ${NUTTX_PATH}/arch/chip) + ${NUTTX_PATH}/include/${NUTTX_CXX} ${NUTTX_PATH}/include + ${NUTTX_PATH}/arch/chip) + +file(GLOB STARTUP_OBJS ${NUTTX_PATH}/startup/*) add_compile_options(-nostdlib) add_compile_options(-ffunction-sections -fdata-sections) -link_libraries( - "-L${NUTTX_PATH}/libs -Wl,--start-group ${LDLIBS} ${EXTRA_LIBS} -Wl,--end-group" +# same entry used for all build modes in crt0.c and arch/.../xxx_start.c + +set(ENTRY_NAME "__start") + +set(CMAKE_C_LINK_EXECUTABLE + " ${LDFLAGS} --entry=${ENTRY_NAME} -T${LINKER_SCRIPT} ${STARTUP_OBJS} -o -L${NUTTX_PATH}/libs --start-group ${LDLIBS} ${EXTRA_LIBS} --end-group" +) +set(CMAKE_CXX_LINK_EXECUTABLE + " ${LDFLAGS} --entry=${ENTRY_NAME} -T${LINKER_SCRIPT} ${STARTUP_OBJS} -o -L${NUTTX_PATH}/libs --start-group ${LDLIBS} ${EXTRA_LIBS} --end-group" ) -add_link_options(-Wl,--entry=__start) -add_link_options(-nostdlib) -add_link_options(-Wl,--gc-sections) -add_link_options(-T${LINKER_SCRIPT}) set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY) diff --git a/tools/uncrustify.cfg b/tools/uncrustify.cfg index c98710f70fb68..7e05e70906c5a 100644 --- a/tools/uncrustify.cfg +++ b/tools/uncrustify.cfg @@ -104,7 +104,7 @@ cmt_star_cont = true # Add star to comment continuation cmt_sp_before_star_cont = 0 # was 1. One space before star on subsequent comment lines # The value 1 added an extra space, indenting by 2. cmt_sp_after_star_cont = 1 # One space after star on subsequent comment lines -cmt_multi_check_last = true # Multi-line comments with a '*' lead, remove leading spaces +cmt_multi_check_last = false # Multi-line comments with a '*' lead, remove leading spaces # cmt_insert_file_header # filename containing the file header # cmt_insert_file_footer # filename containing the file footer # cmt_insert_func_header # filename containing the function header diff --git a/wireless/bluetooth/bt_hcicore.c b/wireless/bluetooth/bt_hcicore.c index d7e192247e6af..bff024e263612 100644 --- a/wireless/bluetooth/bt_hcicore.c +++ b/wireless/bluetooth/bt_hcicore.c @@ -329,7 +329,7 @@ static void hci_cmd_done(uint16_t opcode, uint8_t status, if (g_btdev.sent_cmd->u.hci.opcode != opcode) { - wlerr("ERROR: Unexpected completion of opcode 0x%04x " \ + wlerr("ERROR: Unexpected completion of opcode 0x%04x " "expected 0x%04x\n", opcode, g_btdev.sent_cmd->u.hci.opcode); return; diff --git a/wireless/bluetooth/bt_ioctl.c b/wireless/bluetooth/bt_ioctl.c index c738dd7e30e50..499ff59cea192 100644 --- a/wireless/bluetooth/bt_ioctl.c +++ b/wireless/bluetooth/bt_ioctl.c @@ -58,6 +58,7 @@ struct btnet_scanstate_s volatile bool bs_scanning; /* True: Scanning in progress */ volatile uint8_t bs_head; /* Head of circular list (for removal) */ uint8_t bs_tail; /* Tail of circular list (for addition) */ + uint32_t msgcount; /* Number of warnings printed */ struct bt_scanresponse_s bs_rsp[CONFIG_BLUETOOTH_MAXSCANRESULT]; }; @@ -185,7 +186,12 @@ static void btnet_scan_callback(FAR const bt_addr_le_t *addr, head = g_scanstate.bs_head; if (nexttail == head) { - wlerr("ERROR: Too many scan results\n"); + /* Print only one error message for each SIOCBTSCANSTART call */ + + if (g_scanstate.msgcount++ == 0) + { + wlerr("ERROR: Too many scan results\n"); + } if (++head >= CONFIG_BLUETOOTH_MAXSCANRESULT) { @@ -624,6 +630,7 @@ int btnet_ioctl(FAR struct net_driver_s *netdev, int cmd, unsigned long arg) g_scanstate.bs_scanning = true; g_scanstate.bs_head = 0; g_scanstate.bs_tail = 0; + g_scanstate.msgcount = 0; ret = bt_start_scanning(btreq->btr_dupenable, btnet_scan_callback); diff --git a/wireless/ieee802154/mac802154.c b/wireless/ieee802154/mac802154.c index bf64dae181c78..9789570c9ca17 100644 --- a/wireless/ieee802154/mac802154.c +++ b/wireless/ieee802154/mac802154.c @@ -458,9 +458,9 @@ static void mac802154_notify_worker(FAR void *arg) * This function is called in the following scenarios: * - The MAC receives a START.request primitive * - Upon receiving the IEEE802154_SFEVENT_ENDOFACTIVE event from the - * this radio layer, the MAC checks the bf_update flag and if set - * calls function. The bf_update flag is set when various attributes - * that effect the beacon are updated. + * this radio layer, the MAC checks the beaconupdate flag and if set + * calls function. The beaconupdate flag is set when various + * attributes that effect the beacon are updated. * * Internal function used by various parts of the MAC layer. This function * uses the various MAC attributes to update the beacon frame. It loads @@ -778,8 +778,8 @@ static void mac802154_purge_worker(FAR void *arg) ****************************************************************************/ static int - mac802154_radiopoll(FAR const struct ieee802154_radiocb_s *radiocb, - bool gts, FAR struct ieee802154_txdesc_s **txdesc) +mac802154_radiopoll(FAR const struct ieee802154_radiocb_s *radiocb, + bool gts, FAR struct ieee802154_txdesc_s **txdesc) { FAR struct mac802154_radiocb_s *cb = (FAR struct mac802154_radiocb_s *)radiocb; diff --git a/wireless/ieee802154/mac802154_assoc.c b/wireless/ieee802154/mac802154_assoc.c index 43d08c39c2840..198c5e68a0686 100644 --- a/wireless/ieee802154/mac802154_assoc.c +++ b/wireless/ieee802154/mac802154_assoc.c @@ -146,7 +146,9 @@ int mac802154_req_associate(MACHANDLE mac, return ret; } - /* Get a uin16_t reference to the first two bytes. ie frame control field */ + /* Get a uint16_t reference to the first two bytes. ie frame control + * field + */ iob->io_data[0] = 0; iob->io_data[1] = 0; @@ -879,7 +881,7 @@ static void mac802154_assoctimeout(FAR void *arg) } /**************************************************************************** - * Name: mac802154_extract_assocrespj + * Name: mac802154_extract_assocresp * * Description: * Create and send a Data request command to extract the Association